Abstract:
A high gain, very wide common mode range, self-biased operational amplifier comprising complementary differential transistor pairs biased by biasing transistors and current mirrors, and further comprising cascode transistors to provide a high amplifier output impedance, wherein the biasing transistors, current mirrors, and cascode transistors are all self-biased via negative feedback.

Description:
FIELD 
     Embodiments of the present invention relate to analog circuits, and more particularly, to operational amplifiers. 
     BACKGROUND 
     Many prior art CMOS (Complementary-Metal-Oxide-Semiconductor) operational amplifiers rely upon external biasing in order to bias in the saturation region various FETs (Field-Effect-Transistor) that serve as current sources (or active loads) in the operational amplifiers. However, external biasing may be sensitive to process technology, supply voltage, and temperature. Furthermore, because the overall gain and output resistance of an operational amplifier may both be very high and difficult to accurately model, the output node voltages for zero differential input voltage is very difficult to predict. In general, these node voltages should be at or near V cc /2 for zero differential input voltage, where V cc  is the supply voltage. 
     Other prior art operational amplifiers have utilized various methods of self-biasing with negative feedback, so that the output node voltages are nominally at V cc/ 2. However, for some of these prior art operational amplifiers, external biasing is not completely eliminated, and for others, some or all the FETs that serve as the current sources are biased in their linear region instead of their saturation region, resulting in reduced voltage gain. The present invention addresses these problems. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit for an embodiment of the present invention. 
    
    
     DESCRIPTION OF EMBODIMENTS 
     FIG. 1 is a circuit for an embodiment of a high gain, very wide common mode range, self-biased operational amplifier. The operational amplifier of FIG. 1 may be considered a transconductance amplifier, in that a small-signal current is provided to a load in response to a differential voltage at input nodes  102  and  104 . The load in FIG. 1 may be taken as the output resistance of transistor  5 B in parallel with transistor  6 B. The operational amplifier of FIG. 1 is self-biasing because no external biasing is needed. 
     Transistors  1 A and  1 B are pMOSFETs (p-Metal-Oxide-Semiconductor-Field-Effect-Transistor) arranged as a first differential pair of transistors having their sources connected to each other, and transistors  2 A and  2 B are nMOSFETs arranged as a second differential pair having their sources connected to each other. The two differential pairs are complementary to each other in that they comprise transistors having complementary carrier types, i.e., transistors  1 A and  1 B are of p-carrier type and transistors  2 A and  2 B are of n-carrier type. The gates of transistors  1 A and  2 A are connected to input node  102 , and the gates of transistors  1 B and  2 B are connected to input node  104 . 
     Transistor  3  sources bias current to the differential pair  1 A and  1 B. Transistors  8 A and  8 B comprise a current mirror. Transistor  8 A sinks bias currents from transistors  1 A and  6 A, and transistor  8 B sinks bias currents from transistors  1 B and  6 B. The bias current sourced by transistor  3  is equal in magnitude to the sum of the bias currents sunk by transistors  1 A and  1 B. When the voltage differential between nodes  102  and  104  is zero, transistors  8 A and  8 B sink equal bias currents. 
     Similarly, transistors  7 A and  7 B comprise a current mirror. Transistor  7 A sources bias currents to transistors  2 A and  5 A, and transistor  7 B sources bias currents to transistors  2 B and  5 B. Transistor  4  sinks bias current from the differential pair  2 A and  2 B. The bias current sunk by transistor  4  is equal in magnitude to the sum of the bias currents sourced by transistors  2 A and  2 B. When the voltage differential between nodes  102  and  104  is zero, transistors  7 A and  7 B source equal bias currents. 
     The gate of transistor  7 A is connected to its drain, as well as to the gates of transistors  3  and  7 B. Because the gate of transistor  7 A is connected to its drain, it is biased in its saturation region as long as its gate-source voltage V GS  is more negative than V TP , the pMOSFET threshold voltage. Consequently, transistors  3  and  7 B are also biased in their saturation regions within a margin of V TP . Similarly, the gate of transistor  8 A is connected to its drain, as well as to the gates of transistors  4  and  8 B. Because the gate of transistor  8 A is connected to its drain, it is biased in its saturation region as long as its gate-source voltage V GS  is more positive than V TN , the nMOSFET threshold voltage. Consequently, transistors  4  and  8 B are also biased in their saturation regions within a margin of V TN . 
     Transistors  2 B and  5 B are arranged as a folded-cascode pair. Transistor  5 B is a pMOSFET, so that the folded-cascode pair  2 B and  5 B is comprised of transistors having complementary carrier types. Cascode transistor  5 B provides impedance translation. That is, the impedance at node  112  is very much smaller than the impedance at node  106 . Similarly, transistors  1 B and  6 B are arranged as a folded-cascode pair with complementary carrier types, where the impedance at node  114  is much smaller than the impedance at node  106 . The use of cascode transistors  5 B and  6 B provides a high output impedance, which helps to provide a high amplifier gain because gain is determined by the product of the input transconductance and the output impedance. 
     Transistors  5 A and  2 A, and transistors  6 A and  1 A, are arranged as folded-cascode pairs having complementary carrier types. The gate of transistor  5 A is connected to its drain, and the gate of transistor  6 A is connected to its drain, so that transistors  5 A and  6 A are biased in their saturation regions. The gates and drains of transistors  5 A and  6 A, which are at the same potential, are connected to the gates of transistors  5 B and  6 B and, thereby, bias them. 
     The complementary arrangement of the amplifier of FIG. 1 provides for a very wide common mode range of operation, as reasoned as follows. If the common mode input voltage is low such that transistors  2 A and  2 B are in cut-off, then transistors  1 A and  1 B will still be ON and will continue to amplify. Conversely, if the common mode input voltage is high such that transistors  1 A and  1 B are in cut-off, then transistors  2 A and  2 B will still be ON and will continue to amplify. In this way, the amplifier of FIG. 1 will provide amplification over a wide common mode input voltage range. 
     The self-biasing arrangement of the amplifier of FIG. 1 creates negative-feedback loops that stabilize the various bias voltages. Variations in processing parameters or operating conditions that shift the bias voltages away from their nominal values result in a shift in the bias voltages so as to be self-correcting. 
     Furthermore, the self-biasing arrangement of the embodiment of FIG. 1 also contributes to its differential gain, which may be heuristically argued as follows. Suppose input node  102  goes HIGH and input node  104  goes LOW. Small-signal current is drawn from nodes  108  and  110  by transistors  2 A and lA, respectively, and small-signal current is injected into nodes  112  and  114  by transistors  2 B and  1 B, respectively. With small-signal current injected into nodes  112  and  114 , more current will be sourced into transistor  5 B, and less current will be sunk from transistor  6 B, and as a result, node  106  will go HIGH. In addition, because small-signal current is drawn from nodes  108  and  110 , these nodes go LOW. Because the gates of transistors  3  and  7 B are connected to node  108 , they conduct more strongly, thereby causing the voltage at node  106  to go even higher. Furthermore, because the gates of transistors  4  and  8 B are connected to node  110 , these transistors conduct more weakly, thereby also causing the voltage at node  106  to go still even higher. 
     Various modifications may be made to the described embodiments without departing from the scope of the invention as claimed below.