Abstract:
The structures and methods of reading out semiconductor Non-Volatile Memory (NVM) using referencing cells are disclosed. The new invented scheme can reduce large current consumption from the direct current biasing in the conventional scheme and achieve a high resolution on the cell threshold voltage with a good sensing speed.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an integrated circuit for sensing the stored information of a semiconductor Non-Volatile Memory (NVM). In particular, the present invention relates to circuitry and operating method of using a referencing memory cell to sense the information stored in a semiconductor NVM. 
         [0003]    2. Description of the Related Art 
         [0004]    Semiconductor Non-Volatile Memory (NVM), and particularly Electrically Erasable, Programmable Read-Only Memories (EEPROM), exhibit wide spread applicability in a range of electronic equipments from computers, to telecommunications hardware, to consumer appliances. EEPROM cells store datum by modulating their threshold voltages (device on/off voltage) of the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) by the injection of charge carriers into the charge-storage layer above the channel regions of the MOSFETs. For example, an accumulation of electrons in the floating gate, or in a charge-trap dielectric layer, or nano-crystals above the transistor channel region, causes the MOSFET to exhibit a relatively high threshold voltage. The unique threshold voltage of the memory cell modulated by the stored charges can be applied to represent a state of information. When the power of the semiconductor memory cell is “off” the stored charges still remain in the memory cells. Therefore, the stored information for the correspondent threshold voltage in the memory cells is “non-volatile” even with the power “off”. One class of EEPROMs, Flash EEPROM, may be regarded as specifically configured EEPROMs into cell array that may be erased only on a global or sector-by-sector basis. Flash EEPROM has the advantages of higher compact density and high programming/erase speed over the conventional EEPROM. Flash EEPROM arrays have been broadly applied to mass storage of program codes and digital datum for electronic equipments. 
         [0005]    The conventional current-sensing scheme for reading-out the EEPROM cells using a referencing semiconductor NVM cell is shown in  FIG. 1 , where voltage biases are applied to control gate, source electrode, substrate electrode, and one terminal of a pull-up element  130  with the other terminal attached to the drain electrode of a read EEPROM cell M c . The current flowing through the drain electrode is then amplified by a current mirror amplifier  120 . An identical circuit configuration attached with a referencing cell M rf  is also constructed. The two outputs of the pair of the symmetrical circuitries attached with a read NVM cell M c  and a referencing cell M rf  respectively are then fed into a differential voltage sense amplifier  110  for the comparison of the amplified currents. The output of the differential voltage sense amplifier  110  further pushes the voltage comparison result to a data latch buffer (not shown). The final outcome of the data latch buffer indicates that the current generated from the read NVM cell M c  with the applied voltage biases is greater than the referencing current and vice versa. In one particular case for the referencing current generated from an identical referencing NVM cell M rf  with the same applied biased to both read cell M c  and referencing cell M rf , the outcome of the data latch buffer indicates that the threshold voltage of the read cell M c  with less cell current is higher than that of the referencing cell M rf  and vice versa. Therefore, with the same biases to the identical read and reference cells, the sensing scheme is basically to compare the cells&#39; threshold voltages between the read cell M c  and the referencing cell M rf . Since the mismatch between the symmetrical circuitries and memory cells from manufacturing non-uniformity causes the ambiguity of cells&#39; threshold voltages, in practice, a cell threshold voltage guard band between the read cell and referencing cell has to take into account to separate the ambiguity. This cell threshold voltage guard band imposes a limitation on the numbers of states represented by the threshold voltages of NVM cells in the multi-bit per cell storage application. 
         [0006]    One disadvantage for the conventional current-sense scheme is that the cell currents for both cells require being “on” and amplified by the current mirror amplifiers  120  to maintain steady state voltage potentials at the two inputs of the differential voltage sense amplifier  110 . Due to the direct current paths from the pull-up elements  130  to NVM cells and, mostly from the amplified mirrored currents, the power consumption for the sense scheme is high. In practice, the high current consumption in the sensing circuitry imposes a key limitation factor of having a large number of NVM cells parallel read in semiconductor NVM circuit design. 
         [0007]    In this invention, we have proposed a new kind of semiconductor NVM reading-out scheme using a referencing cell. The new scheme can resolve the threshold voltage difference between the read cell and the referencing cell to a very good accuracy with a proper sensing speed. In particular, the new scheme has no direct current paths in the circuitry but only the switching currents during the sensing period resulting in a small current consumption reading. 
       SUMMARY OF THE INVENTION 
       [0008]      FIG. 2  shows the circuit schematic for the proposed sensing scheme. The source electrode and drain electrode of a read NVM cell M c  are connected to the ground and one terminal of an equivalent loaded capacitor C c  with the other terminal to the ground, respectively. The total capacitance of the equivalent capacitor C c  consists of the capacitance of an adjustment capacitor, bit line capacitances, and other remaining parasitic capacitances. Symmetrically, the source electrode and drain electrode of a reference NVM cell M rf  are connected to the ground and one terminal of another equivalent loaded capacitor C rf  with the other terminal to the ground, respectively. The total capacitance of the equivalent capacitor C rf  includes the capacitance from the other adjustment capacitor, bit line capacitances, and other remaining parasitic capacitances. Both the capacitances of the equivalent capacitors C c  and C rf  are matched to a capacitance value C L  within a fair tolerance by adjusting the adjustment capacitors in the read line and referencing line, respectively. The terminals X and Y between the read NVM drain electrode and the equivalent loaded capacitor C c , and the referencing NVM drain electrodes and the equivalent loaded capacitor C rf  are connected to electrical switches Q 1  and Q 2 , respectively for charging the two equivalent loaded capacitors C c  and C rf  to a preset voltage, V R . Meanwhile, the two terminals X and Y are also connected to two input terminals V iL  and V iR  of the differential voltage sense amplifier  210  shown in  FIG. 3 . 
         [0009]    The circuit schematic of the differential voltage sense amplifier  210  is shown in  FIG. 3 . The differential voltage sense amplifier  210  is constructed by four P-type MOSFETs and seven N-type MOSFETs. MP 1 , MP 2 , MN 1 , MN 2 , and MN 3  are the mirrored symmetry of MP 3 , MP 4 , MN 4 , MN 5 , and MN 6  as depicted in  FIG. 3 . The two input terminals V iL  and V iR  are the gates of MN 2  and MN 5 . The output node OUT and output reverse node OUTB are the two terminals of the symmetrical differential pair located at the drain electrodes of the P-type MOSFETs and the drain electrodes of MN 1  and MN 4 , respectively. The gates of MP 1 , MP 3 , and MN 7  are connected to an enabled signal SAEnb. When the enabled signal SAEnb is at “low” state, the voltage sense amplifier  210  is disabled. MP 1  and MP 3  are turned on to charge both the output nodes, OUT and OUTB to maintain the “high” state with a voltage potential, V DD , while MN 7  is “off” to cut the current paths to the ground. When the enable signal SAEnb goes to “high”, MP 1  and MP 3  are “off” and MN 7  is “on”. The two output nodes (OUT and OUTB) begin to discharge to the ground. Since the differential voltage sense amplifier  210  is constructed as symmetrical as possible, the small voltage difference at the two voltage input nodes of the gates of MN 2  and MN 5  can break the balance of the symmetrical current paths of the left-right portions of the circuitries. The asymmetrical currents are further amplified through the positive feedback of the latch of MP 2 /MN 1 /MN 3  and MP 4 /MN 4 /MN 6 . The output nodes, OUT and OUTB, are then latched to “high” and “low” states, respectively, and vice versa. 
         [0010]      FIG. 4  shows the operation sequence for the invented sense scheme. The voltage potentials V iL  and V iR  at the two capacitor nodes are illustrated in the top drawing of  FIG. 4 . Initially with the selected read NVM cell M c  and referencing NVM cell M rf  deactivated, the two capacitor nodes (V iL  and V iR ) are charged to a preset voltage V iR  through switches Q 1  and Q 2  (turned “ON” by a control signal CS) respectively for a charging time T c . When the gates of the selected read cell M c  and referencing cell M rf  are activated by applying voltage biases V gs  after the pre-charging, the two capacitors (C c  and C rf ) begin to discharge through the read NVM cell M c  and referencing NVM cell M rf  respectively for an elapsing time T e . Depending on the applied gate voltage V gs  to the cell&#39;s threshold voltage V th , the voltage potentials, V iL  and V iR  at the capacitor nodes drop according to their discharge rates. As illustrated at the top drawing of  FIG. 4 , the dotted line (i) represents the voltage potential (V iL  or V iR ) at the capacitor node with an applied gate voltage bias smaller than the cell&#39;s threshold voltage, V gs &lt;V th ; the dashed line (ii) represents the voltage potential (V iL  or V iR ) at the capacitor node with an applied gate voltage bias equal to the cell&#39;s threshold voltage, V gs =V th ; the solid line (iii) represents the voltage potential (V iL  or V iR ) at the capacitor node with an applied gate voltage bias larger than the cell&#39;s threshold voltage, V gs &gt;V th . When the differential sense amplifier  210  is enabled after the elapsing time T e , the differential voltage sense amplifier  210  senses the voltage difference between V iL  and V iR , and latches to a “high/low” state or a “low/high” state. Since the larger NVM gate voltage V gs  to the cell&#39;s threshold voltage V th  is applied, the faster the discharge rate is and the faster the voltage potential (V iL  or V iR ) at the capacitor node drops. Therefore with the same gate voltage bias V gs  applied to the gates of the read cell M c  and the referencing cells M rf , the output node OUT of the differential voltage amplifier  210  ( FIG. 3 ) are latched to a “low” state for the read cell&#39;s threshold voltage higher than that of the referencing cell M rf , and vice versa. 
         [0011]    For the illustrated case in  FIG. 4 , the applied gate voltage and threshold voltage of the reference cell M rf  is set to be V gs =V thrf . Throughout the specification and drawings, V thc  and V thrf  denote the threshold voltages of the read cell M c  and the referencing cells M rf  respectively. Thus, the output nodes, OUT illustrated at the bottom drawing of  FIG. 4 , are latched to the “low” state and the “high” state for V gs &lt;V thc  (dashed line) and V gs &gt;V thc  (solid line) respectively during the sensing time T s . When the differential voltage sense amplifier  210  is disabled after the sensing time T s , the output node OUT and its reverse node OUTB are both charged back to the “high” state and ready for the next sensing. 
         [0012]    The present invention is better understood upon consideration of the detailed description below, in conjunction with the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    For a better understanding of the present invention and to show how it may be carried into effect, reference is now made to the following drawings, which show the preferred embodiments of the present invention, in which: 
           [0014]      FIG. 1  shows the conventional current-sensing scheme for reading-out the EEPROM cells using a referencing NVM cell. 
           [0015]      FIG. 2  shows the circuit schematic for the invented sensing scheme using a referencing cell. 
           [0016]      FIG. 3  shows the circuit schematic of the differential voltage sense amplifier for this invention. 
           [0017]      FIG. 4  shows operation sequence for the invented sensing scheme in three time stages: (1) Charging, (2) Elapsing, and (3) Sensing, and illustrates the voltage potentials at the capacitor node for (a) a read NVM cell with a threshold voltage equal to an applied gate voltage (dashed line(ii)) (b) a read NVM cell with higher threshold voltage (dotted line(i)), and (c) a read NVM cell with lower threshold voltage (solid line (iii)). 
           [0018]      FIG. 5  show an embodiment of the simulation results for the voltage potentials at the two capacitor nodes for the various (V gs -V th )s and the correspondent voltage outputs at the terminal OUT in comparison with the referencing cell with the condition of (V gs -V thrf =0). 
           [0019]      FIG. 6  shows circuit schematic for a NOR-type flash EEPROM array in accordance with one embodiment of the present invention. 
           [0020]      FIG. 7  shows the circuit schematic for a NAND-type flash EEPROM array in accordance with another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure. 
         [0022]      FIG. 6  shows the circuit schematic for a NOR-type flash EEPROM array in accordance with one embodiment of the present invention. The memory cell array in the NOR flash array is organized as the followings: The gates of a row of “M” memory cells M c  form a single word line. The source electrodes of NVM cells M c  are connected to a common ground horizontally and the drain electrodes of a column of “N” NVM cells M c  are connected to a single bit line. Through “p×1” multiplex switches  62 , each bit line is connected to one terminal of each of “k” differential voltage sense amplifiers SA 1 -SA k . Meanwhile, the total capacitances of the equivalent loaded capacitors C c  and C rf  on the two input nodes of the differential voltage sense amplifier (SA 1 -SA k ) including adjusted capacitances, bit line capacitances and parasitic capacitances are matched to a capacitance value of C L  by adding two independent adjustment capacitors (not shown) in the read cell circuit path and reference cell circuit path, respectively. In the embodiment, the capacitance of each equivalent loaded capacitors, C c  and C rf , in a 128 Mega-bit NOR flash array is designed to be about 300 fF (300×10 −15  Farad). 
         [0023]    When a “read” command and an address of memory cells are given from the control circuitry, the selected bit lines correspondent to the memory cell address and the reference bit line are pre-charged to a “read voltage” V R ≅1.2 V for 10 nano-seconds. A gate voltage V gs  is applied to both the selected word line of the correspondent memory address and the gate of the reference cell M rf . The selected bit lines, the reference bit line and their attached nodes begin to discharge through the read NVM cells M c  and the reference cell M rf , respectively. After an elapsing time T e ≅10 nano-seconds, the differential voltage sense amplifiers (SA 1 -SA k ) are enabled. The voltage level differences relative to that of the reference cell at the two input terminals of each differential voltage sense amplifier (SA 1 -SA k ) are sensed and latched to a “low” state or a “high” state accordingly during the sensing time, T s ≅20 nano-seconds. Therefore the parallel sensing of “k” NVM cells is achieved. After the sensing time, the entire differential voltage sense amplifiers (SA 1 -SA k ) are disabled and charged back to their standby state for the next sensing. It is noted that each differential voltage sense amplifier in  FIGS. 6 and 7  has the same circuit configuration as that shown in  FIG. 3 . 
         [0024]      FIG. 5  has shown the simulation results for the operation sequence according to the embodiment of  FIG. 6 . The threshold voltage of the reference cell is programmed to be the same as the applied gate voltage, i.e., V gs =V thrf . It can be easily seen in the middle of  FIG. 5  that if the threshold voltages of NVM cells are greater than that of the reference cell (i.e., V thc &gt;V thrf ), the sense amplifier output OUT, is latched to a “low” state. For the “lower” threshold voltages of NVM cells (i.e., V thc &lt;V thrf ), the sense amplifier output OUT is latched to a “high” state during the sensing period. In standby mode, the output terminals, OUT and OUTB, of each differential voltage sense amplifier (SA 1 -SA k ) both return to the “high” state as shown in the middle of  FIG. 5 . 
         [0025]    One embodiment for using the present invention in an NAND flash array is illustrated in  FIG. 7 . The NAND flash array consists of multiple semiconductor NVM cell strings, where the “N” NVM cells are connected in series in a single NAND string. Each NAND string is through an SSL transistor connected to an individual bit line attached with one of the sense amplifiers (SA 1 -SA M ). The two MOSFET SSL and GSL in the NAND string are the two switches to access the shared bit line and the ground line, respectively. In a typical NAND array, there are “M” units of sense amplifiers (SA 1 -SA M ). As illustrated in  FIG. 7 , the sense amplifiers (SA 1 -SA M ) are arranged to the “top” for the “odd” bit lines and the “bottom” for the “even” bit lines. The referencing NAND string is constructed as the same manner of the read NAND string. The loaded capacitances of equivalent capacitors, C c  and C rf , for the read string and the reference string are matched to a pre-determined capacitance value of C L  within a fair tolerance by adding two adjusted capacitors in the read cell line and referencing line, respectively. 
         [0026]    When a “read” command and an address of memory cells are given from the control circuitry, the selected NAND string is attached to the selected bit line and the ground line by activating SSL and GSL, respectively. The unselected word lines in the NAND string are applied with voltage bias V pass  to pass the voltage biases to the source electrode and drain electrode of the selected NVM cell in the NAND string. The referencing NAND string is also applied with the same bias condition as the read NAND string. While the selected read word line and reference word line are deactivated with a low voltage (i.e., low enough to turn off the selected NVM cells and the selected reference cell), the selected bit lines and reference bit line are pre-charged to a “read voltage” V R . After the bit lines charging, a gate voltage V gs  is applied to both the selected read word line and reference word line. The selected read bit lines and reference bit line at their attached nodes begin to discharge through the selected read NVM cells and the selected reference cell, respectively. After an elapsing time, the sense amplifiers (SA 1 -SA M ) are enabled. The sense amplifier output, OUT, is latched to a “low” state for the threshold voltages of NVM cells are greater than that of the reference cell (i.e., V thc &gt;V thrf ). The sense amplifier output, OUT, is latched to a “high” state for the “lower” threshold voltages of NVM cells (i.e., V thc &lt;V thrf ). The voltage level differences relative to that of the reference cell at the input terminals of each differential voltage sense amplifiers (SA 1 -SA M ) are sensed and latched to a “low” state or a “high” state accordingly during the sensing time. Therefore, the parallel sensing of multiple NVM cells is achieved. After the sensing time, the entire differential voltage sense amplifiers (SA 1 -SA M ) are disabled and charged back to their standby state for the next sensing. 
         [0027]    The above read circuitries and method of sensing are valid for any kind of semiconductor NVM cells. By using the various circuitries based on the configuration and the operational waveforms or different types of semiconductor NVM cells, those skilled in the art would realize that the embodiments of the present invention described herein are illustrative only and are not in any way limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of this description.