Abstract:
A bidirectional serial-parallel-serial charge-coupled device wherein each serial section is both an input register and an output register, and serial streams of charge packets flow simultaneously in opposite directions in the parallel section. Odd data bits of a serial input stream flow into a first serial register and then through the parallel section in one direction and then out of the second serial register, while concurrently the even data bits flow into the second serial register and then through the parallel section in the opposite direction and then out of the first serial register. The data transfer rate is thereby substantially doubled.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to serial-parallel-serial charge-coupled devices, and more particularly to a bidirectional device wherein serial streams of charge packets flow simultaneously in opposite directions through the parallel section. 
     2. Description of the Prior Art 
     Charge-coupled device (CCD) structures for use in data processing system storage and communication signal processing are well-known in the art. Referring to the patents and publications listed below under the heading &#34;References Cited By Applicant&#34;, Boyle and Smith [Refs. 1, 2, 3] originally disclosed the basic charge-coupled concept. Weimer [Ref. 4] disclosed the serial-parallel-serial arrangement. Tompsett [Ref. 5] reviewed further early work, including the serial-parallel-serial configuration. Collins et al. [Ref. 6] disclosed a serial-parallel-serial structure with doublelevel metallization. Carnes, Kosonocky and Sauer [Refs. 7, 8] disclosed further advances including two-phase operation, buried channel structures, and applications to analog signal processing and image sensors. 
     In a serial-parallel-serial configuration, a data bit stream is injected into a serial CCD shift register from where it is transferred in parallel to a parallel storage section. The data can then be shifted in parallel through the parallel section, and then transferred in parallel to an output serial register, from where it is shifted out as a serial bit stream. 
     This serial-parallel-serial configuration had bit density limitations because charge-coupled devices require both transfer and storage sites. That is, in a two-phase serial shift register, the storage of one bit of information requires not only a storage site but also a transfer site so that bits are actually stored at one instant of time in only one-half of the available sites. For example, in a two-phase serial CCD with eight sites, only four bits can be stored. The parallel section was similarly limited in that the channel width was necessarily twice the width of a single site in the serial sections so that only one-half of the potentially available storage sites in the parallel section could be utilized. 
     Bit storage density was then significantly improved by the interlaced modification of the serial-parallel-serial configuration. In an interlaced version of the above example having eight sites and two-phase operation, all eight serial bits can be transferred in parallel through the parallel section, at least theoretically doubling the number of bits that can be stored in the parallel section. Embodiments of interlaced configuations are disclosed by Elmer et al. [Ref. 9, 10, 11], Kosonocky [Ref. 8], and Erb [Ref. 12]. 
     Although the charge-coupled device structure is substantially simpler and therefore less expensive to manufacture than random access memory structures, the charge-coupled device operates in a serial access mode and is therefore substantially slower in operation. This is the major disadvantage of charge-coupled devices as compared with random access memory circuits. 
     The serial access aspect of charge-coupled devices is further aggravated by the alternate-cycle mode of operation of prior charge-coupled devices. That is, the requirement for alternating transfer and storage sites heretofore made it necessary to input and output the successive data bits at alternate clock cycles. For example, if the clock frequency were two megahertz then the data transfer rate would be only one megahertz. 
     This performance limitation of the prior art could not be obviated by simply increasing the clock frequency. The power dissipation of the device is approximately proportional to the clock frequency, in accordance with the formula: 
     
         Power=K×Capacitance×Voltage.sup.2 ×Frequency 
    
     Therefore, for a given power dissipation the clock frequency is substantially predetermined, and any attempt to substantially increase the data transfer rate by increasing the clock frequency results in a proportionate increase in the power dissipation. 
     SUMMARY OF THE INVENTION 
     It is therefore a primary object of the present invention to provide a novel serial-parallel-serial charge-coupled device structure which obviates the data transfer rate limitation arising from the alternate-cycle data transfer mode of operation of the prior art devices. 
     That is, the device in accordance with the present invention operates in a novel manner so as to input and output the successive data bits at every clock cycle rather than at alternate clock cycles as heretofore necessary in the prior art. As a result, the performance of the present invention, as measured by the data transfer rate, is almost double that of equivalent prior art devices. 
     This performance increase is achieved in the present invention by providing that each of the serial sections function as both an input register and an output register. The input serial data bit stream is divided into two data bit streams with the alternate odd bits flowing to a first serial register and the alternate even bits flowing to the second serial register. 
     The parallel section is also novel in that it is bidirectional. The odd data bits flow in one direction through the parallel section while simultaneously the even data bits flow in the opposite direction through the same parallel section. 
     Thus the odd bits enter the first serial register but end up in the second serial register, while the even bits enter the second serial register but end up in the first serial register. The odd bits may then be output from the second serial register, or alternatively may be regenerated and transmitted back to the first serial register to repeat this cycle of operation. Similarly, the even bits may be output from the first serial register, or alternatively may be regenerated and transmitted back to the second serial register to repeat the cycle of operation. 
     At each and every clock cycle, with the exception of the skip interval described below upon transfer between serial and parallel sections, a data bit is either output from the serial-parallel-serial configuration or regenerated and transferred to the other serial register. The odd data bits will thus be output or regenerated at the Phase 1 clock cycles, for example, and the even data bits will be output or regenerated at the alternate Phase 2 clock cycles. Therefore, except for the skip intervals, two bits will be transferred for every pair of clock cycles, thereby approximately doubling the performance as compared with equivalent prior art devices. 
    
    
     IN THE DRAWINGS 
     FIG. 1 is a schematic view of a bidirectional serial-parallel-serial configuration in accordance with the present invention. 
     FIG. 2 is a schematic view of the serial and parallel sections and showing the data flow paths indicated in dash-dot lines. 
     FIGS. 3 to 14 inclusive show the step-by-step sequence of the flow of data bits through the serial and parallel sections. 
     FIG. 15 depicts the clocking associated with FIGS. 3 through 14 and shows the skip interval. 
    
    
     DETAILED DESCRIPTION 
     Referring first to FIG. 1 wherein is shown a preferred embodiment, a parallel section P extends between a first serial section S1 and a second serial section S2. Unlike the serial sections of serial-parallel-serial configurations of the prior art, in the disclosed embodiment each of the serial sections S1, S2 functions as both an input section and an output section. The parallel section P also differs from parallel sections of the prior art in that it is bidirectional, as shown by the arrows in FIG. 1. That is, parallel section P comprises a matrix of charge packet storage sites forming vertical columns or paths extending between the serial sections S1, S2. In alternate columns the direction of charge packet transfer is shown as downward from serial section S2 to serial section S1, and is shown as upward from serial section S1 to serial section S2 in the other columns. 
     Serial section S1 is provided at its right-hand end, as viewed in FIG. 1, with an output 01 from which the data bits are transmitted serially to a conventional regenerator 1. The data bits may then be transmitted along a bidirectional bus B1 to a conventional input/output receiver/driver device I/O R/D from which the data bits may be transmitted from the OUTPUT port. Alternately, the data bits may be transmitted from regenerator 1 by bus B2 to the input I2 at the left-hand end of the second serial section S2. After being serially shifted into the latter, the data bits in the form of discrete charge packets may then be transmitted in parallel downwardly through the alternate parallel section columns having downwardly directed arrows applied thereto in the drawing. This row of data bits may then be transferred to the first serial section S1 and the cycle may be repeated. 
     In a similar manner, data bits in the form of discrete charge packets present in the second serial section S2 may be transmitted to regenerator 2 and then transmitted to input/output receiver/driver device I/O R/D by a bidirectional bus B3. Alternately, the data bits transmitted from the second serial section S2 to regenerator 2 may be transmitted by bus B4 to the input I1 at the left-hand end of the first serial section S1. The data bits may then be transferred in parallel from serial section S1 into the lower row of parallel section P and then transferred upwardly along the alternate upwardly-directed columns or channels of parallel section P so as to eventually arrive in their original charge storage sites within the second serial section S2. 
     Referring now to FIG. 2, there is shown the serial-parallel-serial configuration of FIG. 1 with the logic blocks omitted and the respective data flow paths indicated symbolically by the dash-dot lines for clarity in illustration. It will be seen in FIG. 2 that the data bits transmitted from the output O2 of the second serial section S2 may be regenerated and transmitted to the input I1 of the first serial section S1. Similary, the data bits transmitted from the output O1 of the first serial section S1 may be regenerated and transmitted to the input I2 of the second serial section S2. 
     For simplicity and clarity in illustration, the disclosed embodiment of the invention is shown as having a parallel section P with only eight columns or channels of charge packet storage sites, each column being designated by a respective one of the references C1 through C8. As shown in the drawing, the data flow paths of the odd-numbered columns C1, C3, C5, C7 flow upwardly from the first serial section S1 to the second serial section S2 as indicated by the arrows. The alternate even-numbered columns C2, C4, C6, C8 have downwardly extending arrows applied thereto to indicate that the data bits in these columns flow downwardly from the serial section S2 to the serial section S1. 
     Referring now to FIGS. 3 to 14 inclusive, there is shown the step-by-step sequence of the bidirectional interlaced flow of data bits. Referring first to FIG. 3, it will be assumed that the alternate odd data bits 1, 3, 5, 7 of a serial bit stream have been shifted serially into the first serial section S1 and that the alternate even data bits 2, 4, 6, 8 of the stream have then been shifted serially into the second serial section S2. The bits previously shifted into the parallel section P are indicated by the numerals in FIG. 3 in the respective charge storage sites constituting the matrix of the parallel section. 
     Referring now to FIG. 15, this depicts the clocking associated with the bit sequences before and up to FIG. 3. At this point a skip interval is incurred because a series to parallel transfer is performed. 
     Data is not inputted or outputted from this structure during the skip interval. FIGS. 4, 5 and 6 are associated with skip interval during the transfer of data between the series and parallel sections, while FIGS. 7 through 14 are associated with external recirculation or data inputting and outputting. 
     As shown in FIG. 4, upon application of clock pulse φE, the odd data bits 1, 3, 5, 7 are transferred in parallel to the lowermost row of the matrix constituting parallel section P, and at the same time the even data bits 2, 4, 6, 8 in the second serial section 2 are transferred downwardly to the uppermost row of parallel section P. The bits within the matrix are also shifted to new storage sites as shown in FIG. 4. The even data bits 2, 4, 6, 8 are transferred to the even-numbered columns C2, C4, C6, C8 having downwardly-directed flow paths as indicated in FIGS. 1 and 2, whereas the odd data bits 1, 3, 5, 7 are transferred to the odd-numbered columns C1, C3, C5, C7 having upwardly-directed flow paths indicated by the arrows in said figures. 
     As shown in FIG. 5, application of the clock pulse φ0 then causes the data bits represented by charge storage packets within the parallel section P to be shifted vertically to the next adjacent charge storages site in the respective columns, with those data bits in columns C2, C4, C6, C8 moving downwardly and those data bits within columns C1, C3, C5, C7 moving upwardly. The application of clock pulse φ1 also causes bits 10, 12, 14, 16 to be transferred in parallel from the lowermost row of parallel section P into the first serial section S1. Simultaneously, the application of clock pulse φ1 causes bits 9, 11, 13, 15 to be transferred in parallel from the uppermost row of parallel section P into the second serial section S2. 
     Referring now to FIG. 6, alternate application of clock pulses φ1 and φ2 cause bits 9, 11, 13, 15 to be shifted serially through the second serial section S2 toward the output end of the latter. These bits may be transmitted to the output port designated OUTPUT in FIG. 1, or may be transmitted to the input end of the first serial section S1 as shown in FIG. 7 where bit 9 has been transferred to the first charge storage site of the first serial section S1. 
     In a similar manner, bits 10, 12, 14, 16 are shifted serially through the first serial section S1, as shown in FIG. 7, and may be transmitted to the output port, or may be transmitted to the input end of the second serial section S2. The latter alternative is shown in FIG. 8 wherein bit 10 has been transferred to the first charge storage site of the second serial section S2. 
     Referring now to FIGS. 9 to 14, application of clock signals φ1 and φ2 is shown as serially shifting the bit sequence 9, 11, 13, 15 out of the second serial section S2 and into the first serial section S1, while the bit sequence 10, 12, 14, 16 is being serially shifted out of the first serial section S1 and into the second serial section S2. The progressive steps are shown sequentially in FIGS. 10, 11, 12 and 13, with the final result of this transfer being shown in FIG. 14. 
     The clock signal φE will then transfer bits 10, 12, 14, 16 into alternate charge storage sites of the uppermost row of parallel section P, while simultaneously bits 9, 11, 13, 15 are transferred into alternate charge storage sites in the lowermost row of parallel section P, in a manner similar to that shown by the transition occurring from FIG. 3 to FIG. 4 and described above. It will be seen that continued strobing of the clock signals φ1, φ2, φE will eventually transfer all of the data bits to their original positions shown in FIG. 3, assuming that the device is maintained in the regenerative mode. 
     While the invention has been shown and particularly described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention which is delineated in the appended claims. 
     REFERENCES CITED BY APPLICANT 
     1. boyle, W. S. and Smith, G. E., &#34;Charge Coupled Semiconductor Devices,&#34; Bell Sys. Tech. J. (April 1970) pp. 587-593. 
     2. Boyle, W. S. and Smith, G. E., U.S. Pat. No. 3,858,232; issued Dec. 31, 1974; filed Nov. 9, 1971. 
     3. Smith, G. E., U.S. Pat. No. 3,761,744; issued Sept. 25, 1973; filed Dec. 2, 1971. 
     4. Weimer, P. K., U.S. Pat. No. 3,763,480; issued Oct. 2, 1973; filed Oct. 12, 1971. 
     5. Tompsett, M. F., &#34;Charge Transfer Devices,&#34; J. Vac. Sci. Technol., Vol. 9, No. 4, (July-August 1972) pp. 1166-1181. 
     6. Collins, D. R., Barton, J. B., Buss, D. C., Kmetz, A. R., and Schroeder, J. E., &#34;CCD Memory Options,&#34; 1973 IEEE International Solid-State Circuits Conference, (February 1973) pp. 136-137, 210. 
     7. Carnes, J. E. and Kosonocky, W. F., &#34;Charge-Coupled Devices and Applications,&#34; Solid State Technology, (April 1974) pp. 67-77. 
     8. Kosonocky, W. F. and Sauer, D. J., U.S. Pat. No. 3,967,254; issued June 29, 1976; filed Nov. 18, 1974. 
     9. Elmer, B. R., Tchon, W. E., Denboer, A. J., Frommer, R., Kohyama, S. and Hirabayashi, K. &#34;Fault Tolerant 92160 Bit Multiphase CCD Memory,&#34; IEEE International Solid-State Circuits Conference (February 1977) pp. 116-117. 
     10. Elmer, B. R., U.S. Pat. No. 4,024,509; issued May 17, 1977; filed June 30, 1975. 
     11. Elmer, B. R. and Tchon, W. E., U.S. Pat. No. 3,986,179; issued Oct. 12, 1976; filed June 30, 1975. 
     12. Erb, D. M., U.S. Pat. No. 3,913,077; issued Oct. 14, 1975; filed Apr. 17, 1974.