Abstract:
A circuit utilizing Josephson junctions to perform high speed logic gate switching functions. Three &#34;Y&#34; connected resistors have Josephson junction devices at their non-connected ends. The resistances of the resistors, the critical currents of the Josephson junctions, and the amplitudes of input currents to two of the resistor-Josephson junction connections are selected so that, when the input currents are applied at the same time, the third Josephson junction is switched to the voltage state and both input currents are derived from the third Josephson junction-resistor connection as an input current. In another embodiment, the basic circuit has additional resistor-Josephson junction input arms, producing an M/N logic gate function. In another embodiment, the resistors are &#34;Δ&#34; connected. The resulting logic gates have wide operational margins, high speed switching capabilities and small size.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to circuits utilizing the Josephson effect and, more particularly, to such a logic gate which has a very short gate delay time and a wide operational margin and which is feasible for a high degree of integration. 
     Various kinds of logic gates have been proposed using Josephson junctions to take advantage of their low power dissipation and high switching speeds. For example, refer to the paper, &#34;Josephson-Logic Devices and Circuits&#34; by TUSHAR R. GHEEWALA, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 10, OCTOBER 1980, PP 1857-1869. The basic construction of the logic gate is of the interference type, consisting of a plurality of Josephson junctions and inductances adapted to electrically connect the Josephson junctions. An input current is directly injected into the logic gate or electromagnetically coupled with a control line of the logic gate, thereby switching the gate to the voltage state. T. R. Gheewala describes in his paper &#34;Josephson logic circuits based on nonlinear current injection in interferometer devices&#34;, Applied Physics Letter, Vol. 33, No. 8, pp. 781-783, a Josephson logic gate which is designed for wider margins and higher switching speeds. FIG. 3(a) in page 782 of this paper shows an AND gate equipped with an interferometer gate having two Josephson junctions having critical currents I 01  and I 02 , respectively, and a series connection of inductances L 1  and L 2  having inductance values L 1  &#39; and L 2  &#39;. The Josephson junctions are connected in parallel by the series connection of the inductances. One input I a  is coupled to the node between the inductances L 1  and L 2  and the other I b  to one end of the inductance L 1 . To optimize the operation (operational margins) of this gate, the inductance values L 1  &#39; and L 2  &#39; and the critical currents I 01  and L 02  are chosen to satisfy equations: 
     
         L.sub.1 &#39;I.sub.01 =L.sub.2 &#39;I.sub.02                       ( 1) 
    
     
         I.sub.02 (L.sub.1 &#39;+L.sub.2 &#39;)=φ.sub.0                 ( 2) 
    
     where φ 0  indicates a natural constant called &#34;magnetic flux quantum&#34; and having a value of the order of 2.07 pH.mA. However, the logic gate as described above is disadvantageous in various respects. Although the critical current should be small in order to reduce the power dissipation, the current I 02  and the inductance values L 1  &#39; and L 2  &#39; cannot be reduced at the same time as seen from the equation (2) so that a large chip area is required to attain this lower power dissipation. Since the gate includes both inductances and Josephson junction capacitance, a resonance phenomena is caused which should be damped for high speed operations. Furthermore, a gate of this kind tends to trap stray magnetic fields when switching to its superconducting state; the trapped magnetic fields can cause the gate to malfunction. These problems exist not only in the above-described AND gate but in all logic gates of the interference type. 
     U.S. Pat. No. 4,275,314 discloses an AND gate which attempts to eliminate the above-described drawbacks by not providing with an inductance component. The AND gate, as shown in FIG. 3 of this U.S. Pat. specification, uses the circuit indicated in FIG. 1 (named JAWS) as a one-input OR gate and cascades two such OR gates. When one input is supplied to the first stage JAWS, the bias current fed to the first stage JAWS is coupled to the second stage JAWS as the second bias current. When the other signal arrives at the second stage JAWS, the second bias current is steered to the output side. This type of logic gate, although free from the drawbacks inherent in the AND gate previously described due to the absence of inductance component, nonetheless possesses several disadvantageous characteristics. First, the cascaded JAWS result in a high degree of intricacy in the circuit construction. Second, the input sensitivity, i.e., the ratio of the input current to the minimum amount of current necessary to switch the device, is as small as 1, which makes the overdrive capability relatively small. This reduction in overdrive capability reduces the ability of the gate to speed up the switching action (i.e. shorten the turn-on delay time of the gate). In more detail, an output of a gate using Josephson junctions generally appears (with a time constant of a load resistance R L  and a Josephson junction capacitance C) upon the lapse of a turn-on delay time after an input current has exceeded a threshold for the circuit operation. The turn-on delay time decreases inversely with respect to the overdrive capability defined by (I 0  -I th )/I 0  where I 0  is the input current and I th  the threshold current for a predetermined gate current, as described in TURN-ON DELAY OF JOSEPHSON INTERFEROMETER LOGIC DEVICES, IEEE TRANSACTIONS ON MAGNETICS, VOL. MAG-15, NO. 1, JANUARY 1979, pp. 562-565. Obviously, the overdrive capability increases with the input sensitivity which is defined by an inclination of a control characteristic line of the gate while the turn on delay time decreases as the input sensitivity becomes higher. Thus, it is desirable to make the input sensitivity as high as possible in order to speed up the switching actions of the gate by shortening the turn-on delay time. As previously mentioned, the input sensitivity of the above-mentioned gate is 1 which is relatively low sensitivity to promote high speed switching. 
     Using the interferometer gate already discussed, a logic gate can be constructed having two or more input lines, and producing an output when input currents flow through a predetermined number or more of the input lines, (e.g., a 2/3 logic gate can be produced in which an output appears when input currents flow through two or more of three input lines). In the 2/3 logic gate, for instance, a gate current is constantly fed to the Josephson junctions J 1  and J 2  through the inductances L 1  and L 2  of the interferometer gate, respectively, and the critical currents are selected such that the gate switches in response to the flow of input currents through two or more of the three input lines. 
     With this construction, however, not only do the previously described problems remain unsolved, but the input current margins are narrow and it is difficult to realize a highly integrated circuit. More specifically, supposing that the minimum input current necessary for switching a gate under the supply of a gate current is I t , the range (margins) of the input current I in  required for operation of the 2/3 logic gate is quite narrow (e.g., between I t  /2 and I t ). With respect to actual production, however, the input current margins will be still narrower in view of the lack of uniformity of critical current and inductance among integrated circuits. Moreover, the need for three input lines for magnetic coupling in the gate cannot be met without rendering the device design quite difficult since it is hard to equalize the degrees of magnetic coupling between the input lines and the inductances. These problems also exist in multi-input AND gates. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a circuit utilizing the Josephson effect which is feasible for high integration and free from resonance due to the capacitance of Josephson junctions. 
     It is another object of the present invention to provide a circuit utilizing the Josephson effect which is provided with wide operational margins and capable of high speed switching. 
     It is a further object of the present invention to provide a two-input AND gate utilizing the Josephson effect which has the advantages mentioned above. 
     It is yet another object of the present invention to provide a multi-input logic gate utilizing the Josephson effect which has the various advantages mentioned above and produces an output when inputs come in through a predetermined number or more of multiple inputs. 
     It is a still further object of the present invention to provide an amplifier utilizing the Josephson effect which features all the advantages described above. 
     In accordance with one embodiment of the present invention, there is provided a circuit comprising a first resistor, a second resistor and a third resistor having predetermined resistances R 1 , R 2  and R 3 , respectively, and connected together at one end thereof, a first Josephson junction and a second Josephson junction having predetermined critical currents I 01  and I 02 , respectively, and connected in parallel with the other end of the first and second resistors, respectively, and a specific Josephson junction having a predetermined critical current I 0  and connected in series with the other end of the third resistor; and circuits utilizing the Josephson effect having the AND function whereby an output current may be derived from the node between the third resistor and the specific Josephson junction when the first and second input currents are supplied at the same time, and having an amplifying function whereby a predetermined gate current is constantly supplied from the other end of the second resistor and an output, which is an amplified version of an input current from the other end of the first resistor, appears at the node between the third resistor and the specific Josephson junction. 
     In accordance with another embodiment of the present invention, there is provided a circuit utilizing the Josephson effect and having the multi-input AND function in which a plurality of resistors are additionally connected at one end thereof to the node among the first, second and third resistors of above-mentioned circuits, each of said plurality of resistors having a Josephson junction with a predetermined critical current connected in parallel at the other end thereof. Properly selecting the resistances, critical currents and input currents will provide a circuit having an M/N logic gate (M≦N) function. 
     In accordance with yet another embodiment of the present invention, there are provided circuits comprising a first resistor and a second resistor connected together at one end thereof and provided with predetermined resistances, respectively, a first Josephson junction and a second Josephson junction connected in parallel with the other end of the first and second resistors, respectively, and having predetermined critical currents, a specific Josephson junction having a predetermined critical current and connected in series with the node between the first and second resistors, and a first specific resistor connected between the other end of the first and second resistors and having a predetermined resistance; and circuits utilizing the Josephson effect having an AND function whereby an output appears at the node between the specific Josephson junction and the first and second resistors when input currents are supplied to the other end of the first and second resistors at the same time, and having an amplifying function whereby a predetermined gate current is caused to constantly flow from the other end of the second resistor and an output, which is an amplified version of an input current from the other end of the first resistor, appears at the node between the specific Josephson junction and the first and second resistor. 
     Other objects and features of the present invention will become apparent from the following description when read with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B are diagrams of a circuit with a two-input AND function embodying the present invention and a graph showing its control characteristics, respectively; 
     FIG. 2 is a diagram of a circuit using the arrangement shown in FIG. 1A and furnished with the amplifying function; 
     FIGS. 3A and 3B are diagrams of a circuit with a 2/3 logic gate function according to another embodiment of the present invention and a graph showing its control characteristics, respectively; 
     FIGS. 4A and 4B are diagrams of a circuit with a two-input AND function according to still another embodiment of the present invention and a graph showing its control characteristics, respectively; and 
     FIG. 5 is a diagram of a circuit having an amplifying function and using the arrangement shown in FIG. 4A. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1A of the drawings, an example of two-input AND gate according to the present invention is illustrated. The AND gate shown includes three resistors R 1 , R 2 , and R 3  which are connected in Y configuration about a node C. Josephson junctions J 1  and J 2  are connected in parallel with the resistors R 1  and R 2 , respectively. A Josephson junction J 3  is connected in series with the resistor R 3 , and a load resistor R L  is connected through an output line in parallel with the Josephson junction J 3 . Critical currents I 01 , I 02  and I 03  of the Josephson junctions J 1 , J 2  and J 3  and resistances r 1 , r 2  and r 3  of the resistors R 1 , R 2  and R 3  are individually selected to satisfy the relationship: 
     
         I.sub.01 =I.sub.02 =I.sub.03 /2≠I.sub.0              (3) 
    
     
         r.sub.1 =r.sub.2 =2r.sub.3                                 (4) 
    
     Suppose that one of input currents I a  and I b  is injected into the AND gate through one of input terminals 10 and 11 (for example the input current I a  through the input terminal 10). Where the input current I a  is preselected to be larger than I 0  as defined by the equation (3), the Josephson junction J 1  is switched to the voltage state. Two thirds of the input current flowing through the resistor R 1  is injected into the Josephson junction J 3  through the resistor R 3  and one third of the current I a  is injected into the Josephson junction J 2  through the resistor R 2 , as defined by the equation (4). Here, the Josephson junctions J 2  and J 3  will remain in the zero voltage state to deliver no output current to the resistor R L  if the following relationships are satisfied: 
     
         I.sub.a /3≦I.sub.0                                  (5) 
    
     
         I.sub.a &gt;I.sub.0                                           (6) 
    
     The input current Ib from input terminal 11 is injected into the AND gate after the input current I a , and satisfies the relationships: 
     
         I.sub.a /3+I.sub.b &gt;I.sub.0                                (7) 
    
     
         I.sub.a +I.sub.b &gt;2I.sub.0                                 (8) 
    
     Then, the condition (7) brings the Josephson junction J 2  into the voltage state to allow the input currents I a  and I b  to be steered into the Josephson junction J 3 . The condition (8) then brings the Josephson junction J 3  into the voltage state so that the input currents I a  and I b  are passed through the output line to the load resistor R L . Where the supply of the input current I b  occurs before that of the input current I a , the above description will also apply if I a  and I b  are exchanged in the foregoing equations. 
     FIG. 1B is a graph showing control characteristics of the logic gate provided by the relationships (5), (6), (7) and (8) and their versions with I a  and I b  interchanged. The hatched area of the graph indicates the voltage state. It will be seen from the graph that when only one of the input currents I a  and I b  is supplied, the logic gate is not switched to the voltage state if the input current is smaller than 3I 0  ; when both the input currents I a  and I b  are supplied and have the same magnitude, the logic gate is switched to the voltage state if I a  =I b  &gt;I 0 . Generally, operational margins of a logic gate for the AND function increase as the input current I a  (=I b ) necessary for the transition of the logic gate to the voltage state under the supply of both the currents I a  and I b  grows smaller than the input current I a  or I b  necessary for transition under I a  or I b  only. 
     Thus, the logic gate of this embodiment has wide operational margins and, as will be seen from FIG. 1B, its input sensitivity is as high as 3, which promotes high speed switching. Furthermore, in the logic gate according to this embodiment, there is no limitation as indicated by the equation (2), but the Josephson critical currents and resistances need only to satisfy the relationships (3) and (4). The logic gate on the substrate, therefore, can be designed to be very small (that is, the size of the gate is only limited by the ability of the lithography technique). The absence of inductances eliminates the resonance due to the Josephson junction capacitance, and the gate thus requires no additional provision against resonance in the circuit design. Since the logic gate is not of the superconducting loop type, it would not be affected in operation even when trapping stray magnetic fields in the ground plane. 
     The current injection type logic gate of this embodiment is also usable as a current amplifier due to its high gain characteristic. An amplifier application will now be described with reference to FIG. 2. 
     Referring to FIG. 2, a predetermined current I g  is constantly caused to flow from an input terminal 21. Considering the margins, the current I g  is preset to be 75% of 3I 0 . The operation point, therefore, may be the one indicated by 12 in the control characteristic shown in FIG. 1B (where I g  =I b ). In this situation, the minimum input current I a  required for the transition of the logic gate to the voltage state is 0.25 I 0 . Neglecting leak currents of the Josephson junctions under the voltage state, the logic gate will provide an output current expressed as 3I 0  ×0.75+0.25I 0  which in turn provides a current gain of 10. In practice, the input current I a  will be set at a larger value than 0.25I 0  in consideration of the margins and, accordingly, the operation point of the gate circuit under the voltage state will correspond to reference numeral 13 shown in FIG. 1B. 
     Another embodiment of the logic gate of the present invention will be described hereunder which is constructed to produce an output when input currents are supplied through a predetermined number or more of a plurality (three or more) of input lines. 
     Referring to FIG. 3A, there is shown a 2/3 logic gate which has input terminals 30, 31 and 32 and produces an output at the load resistor R L  when input currents are supplied to two or more of the three input terminals. Basically, the logic gate shown in FIG. 3A is constructed by connecting one end of a resistor R 4  to the node C of the AND gate indicated in FIG. 1A and connecting a Josephson junction J 4  in parallel with the other end of the resistor R 4 . It will be seen that a logic gate with four or more inputs can be designed as desired, employing the same concept. 
     The logic gate shown in FIG. 3A will operate as follows. For simplicity of description, the Josephson circuits J 1 , J 2 , J 3  and J 4  are assumed to have equal critical current I 1  and the resistors R 1 , R 2 , R 3  and R 4  are assumed to be of equal resistance. 
     Suppose that input currents I a , I b  and I c  are sequentially supplied to the respective input terminals 30, 31 and 32 in the order named. The input current I a  having a value larger than the Josephson critical current I 1  switches the Josephson junction J 1  to the voltage state and is thereby trisected into the Josephson junctions J 2 , J 3  and J 4 . In order that the logic gate may not be switched under the above condition, I a  and I 1  are chosen to have relationship: 
     
         I.sub.a /3&lt;I.sub.1                                         (9) 
    
     
         I.sub.a &gt;I.sub.1                                           (10) 
    
     Thereafter, the input terminal 31 is supplied with the input current I b  which meets a condition: 
     
         I.sub.a /3+I.sub.b &gt;I.sub.1                                (11) 
    
     Then, the Josephson junction J 4  is switched to the voltage state so that the input currents I a  and I b  are individually bisected and steered into the Josephson junctions J 2  and J 3 . At this instant, the Josephson junctions J 2  and J 3  become switched to the voltage state if the following relationship is maintained: 
     
         I.sub.a +I.sub.b &gt;2I.sub.1                                 (12) 
    
     This allows the composite input current I a  +I b  to flow out into the output line which terminates at the load resistor R L . Though the other input current I c  may thereafter be injected through the input terminal 32, it is simply steered into the output line through the resistors R 2  and R 3  because all of the Josephson junctions J 1 , J 2 , J 3  and J 4  have been switched to the voltage state. As a result, the input current I a  +I b  +I c  is coupled to the load resistor R L  through an output line. The same operation procedure, except for the interchange of I a  and I b , will occur when I b  is injected into the logic gate before I a . 
     The resulting control characteristics of the logic gate shown in FIG. 3A are graphically represented in FIG. 3B. The hatched area of the graph indicates the voltage state of the logic gate. While the input currents I a  and I b  have been assumed to be coupled to the logic circuit before the input current I c , it will be understood that the control characteristics shown in FIG. 3 also apply to a case wherein the currents I a  and I c  are supplied before the current I b  or to a case wherein the currents I b  and I c  are supplied before the current I a , except for the substitution of I a  and I b  by I a  and I c  or by I b  and I c , respectively. These substitutions hold because the logic gate shown in FIG. 3A is symmetric with respect to the input currents I a , I b  and I c . Indicated by the numeral 33 in FIG. 3B is the operation point of the logic gate provided by the supply of input currents I a  and I b  whose magnitude is 2I 1 . 
     It will be seen that the logic gate shown in FIG. 3A is properly operable as long as the magnitude I 0  of the input currents I a , I b  and I c  satisfies the relationship: 
     
         I.sub.1 &lt;I.sub.0 ≦3I.sub.1                          (13) 
    
     The margins of the input current are as wide as 2I 1  ±50%. Incidentally, the margins of the input current of the prior art 2/3 logic gate which relies on an interferometer are not more than 0.75I t  ±33.3%. Moreover, as shown in FIG. 3A, the logic gate is fully symmetrical in structure with respect to the input currents I a , I b  and I c , and requires no attention to the uniformity of the magnetic coupling between input currents and inductances, so that the complex device design is avoided. Apart from these outstanding advantages, the absence of inductances as described in relation with FIG. 1A permits the logic gate of FIG. 3A to be made small, highly integrated and freed from an implementation against resonance. 
     It will be apparent in the circuitry of FIG. 3A that various values can be employed for the input currents, critical currents of the Josephson junctions, and resistances of the resistors. It will also be apparent that a multi-input AND gate can be constructed by selecting each input current and critical current such that when each input current is coupled to the corresponding input terminal, the associated Josephson junction becomes switched to the voltage state, and the Josephson junction J 3  is switched to the voltage state by the sum of all the input currents. 
     Referring to FIG. 4A, a farther embodiment of the present invention is shown which is an AND gate having two input terminals. The AND gate in FIG. 4A is essentially similar to the AND gate in FIG. 1A except that the resistor R 3  is omitted and replaced by a resistor R 5  which is connected between two input terminals. As shown, the AND gate comprises Josephson juntions J 1 , J 2  and J 5  having critical currents I 01 , I 02  and I 05 , resistors R 1 , R 2  and R 5  having resistances r 1 , r 2  and r 5 , a load resistor R L  having a resistance r L , and input terminals 40 and 41 to be supplied with input currents I a  and I b , respectively. In this embodiment, the critical currents I 01 , I 02  and I 05  and the resistances r 1 , r 2  and r 5  are individually chosen to satisfy relationships: 
     
         I.sub.01 =I.sub.02 =I.sub.05 /2.tbd.I.sub.0                (14) 
    
     
         r.sub.1 =r.sub.2 =r.sub.5 /2                               (15) 
    
     Suppose that one of input currents I a  and I b  is injected into the AND gate through one of the input terminals 40 and 41, (for example, the input current I a  through the input terminal 40). Where the input current I a  is preselected to be larger than I 0  as defined by the equation (14), the Josephson junction J 1  becomes switched to the voltage state. Then, two thirds of the input current flowing through the resistor R 1  is injected into the Josephson junction J 5  and one third is injected into the Josephson junction J 2  through the resistor R 5 , as defined by the equation (15). Here, the Josephson junctions J 2  and J 5  will remain in the zero voltage state to deliver no output current to the load resistor R L  if the following relationships hold: 
     
         I.sub.a /3≦I.sub.0                                  (16) 
    
     
         I.sub.a &gt;I.sub.0                                           (17) 
    
     Injected into the AND gate after the input current I a  is the input current I b  through the input terminal 41 which is supposed to meet the relationships: 
     
         I.sub.a /3+I.sub.b &gt;I.sub.0                                (18) 
    
     
         I.sub.a +I.sub.b &gt;2I.sub.0                                 (19) 
    
     Then, the condition (18) brings the Josephson junction J 2  into the voltage state to allow the input currents I a  and I b  to be injected into the Josephson junction J 5 . The condition (19) then brings the Josephson junction J 5  into the voltage state so that the input currents I a  and I b  are steered through an output line to the load resistor R L . Where the supply of the input current I b  occurs before that of the input current I a , the above description will also apply if I a  and I b  are exchanged in the relationships. 
     FIG. 4B is a graph similar to FIG. 1B and shows control characteristics of the logic gate provided by the relationships (16) to (19) and their versions with I a  and I b  interchanged. It will be seen from the graph that when only one of the input currents I a  and I b  is supplied, the logic gate is not switched to the voltage state if the input current is smaller than 3I 0  ; on the other hand, when both the input currents I a  and I b  are supplied and have the same magnitude, the logic gate is switched to the voltage state if I a  =I b  &gt;I 0 . Thus, like the AND gate shown in FIG. 1A, the AND gate of FIG. 4A has wide operational margins and is capable of high speed switching. It is apparent that all the advantages discussed in connection with the circuitry of FIG. 1A are applicable to the circuitry of FIG. 4A. 
     Thus, the logic gate shown in FIG. 4A is also usable as a current amplifier due to its high gain characteristic. Such an application is illustrated in FIG. 5. As shown, a predetermined current I g  is caused to constantly flow from an input terminal 51. Considering the margins, the current I g  is preset to 75% of 3I 0 . The operation point under this condition may be the one indicated by the numeral 42 in FIG. 4B. In this situation, the minimum input current I a  from an input terminal 50 required for the transition of the logic gate to the voltage state is 0.25I 0 . Neglecting leakage currents of the Josephson junctions under the voltage state, the logic gate will provide an output current expressed as 3I 0  ×0.75+0.25I 0  which in turn provide a current gain of 10. In practice, the input current I a  will be set at a larger value than 0.25I 0  in consideration of the margins and, accordingly, the operation point of the gate circuit under the voltage state will be the one corresponding to 43 shown in FIG. 5.