Abstract:
A method and system for accurate timing in a low current system useful in fuzing applications generates a first count of oscillations of an oscillator of unknown frequency during a first period of unknown duration. A second count of oscillations of the oscillator is generated during a second period of a known duration. The duration of the first period is calculated based on the first count and the second count. A solid-state, thin-film battery is able to be used by virtue of low-current characteristics of the system, enabling extended shelf life for fuzing systems.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates generally to microcontroller circuits and, in particular, to ultra low current microcontroller circuits.  
         BACKGROUND OF THE INVENTION  
         [0002]    Fuzing systems generally use a power source coupled with a timing system to trigger a firing circuit. It is often a requirement for such fuzing systems to have an extended shelf life. It is also often a requirement for such fuzing systems to be operable over a wide temperature range.  
           [0003]    Solid-state lithium (SSLi) batteries have a long shelf life of twenty years or more. This longevity is partly due to chemical stability and partly due to a self-discharge rate of less than 2% of capacity per year per cm 2 . N. J. Dudney et al.,  Rechargeable Thin-Fm Batteries with LiMn   2 O 4  and LiCoO 2  Cathodes, 197 th  meeting of the Electrochemical Society, 4 (Spring 2000). Unfortunately, use of SSLi batteries in conventional fuzing systems has been generally rejected because SSLi batteries have poor low or cold temperature performance. For example, an SSLi battery having a current capacity of 100μ amperes at a temperature of +20° C. may have a current capacity of only 20μ amperes at a temperature of −50° C. The limited ability of an SSLi battery to deliver current at cold temperatures is due to a dramatic nonlinear increase of its internal resistance as a function of lowered temperatures.  
           [0004]    It would thus be desirable to overcome the shortcomings of conventional fuzing systems.  
         SUMMARY OF THE INVENTION  
         [0005]    To achieve these and other objects, and in view of its purposes, the present invention provides a method and system for accurate timing in a low current system. A first count corresponding to oscillations of a first oscillator during a first period of unknown duration is generated. A second count corresponding to oscillations of the first oscillator during a second period of known duration is generated. The duration of the first period is calculated based on the first count and the second count.  
           [0006]    It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0007]    The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures:  
         [0008]    [0008]FIG. 1 is a schematic of a circuit according to a first exemplary embodiment of the present invention;  
         [0009]    [0009]FIG. 2 is a flow chart of a main processor routine according to the first exemplary embodiment;  
         [0010]    [0010]FIG. 3 is a flow chart of a timer interrupt service routine according to the first exemplary embodiment;  
         [0011]    [0011]FIG. 4 is a flow chart of a watchdog interrupt service routine according to the first exemplary embodiment;  
         [0012]    [0012]FIG. 5 is a block diagram of a second exemplary embodiment of the present invention;  
         [0013]    [0013]FIG. 6A-D are schematics of a circuit according to the second exemplary embodiment;  
         [0014]    [0014]FIG. 7 is a flow chart of a main processor routine according to the second exemplary embodiment;  
         [0015]    [0015]FIG. 8 is a flow chart of a timer interrupt service routine according to the second exemplary embodiment; and  
         [0016]    [0016]FIG. 9 is a flow chart of a watchdog interrupt service routine according to the second exemplary embodiment. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
     First Exemplary Embodiment  
       [0017]    Referring now to the drawing, in which like reference numerals refer to like elements throughout, FIG. 1 illustrates an exemplary low current microprocessor circuit  100  having a shelf life of twenty years in a self-destruct application for fuzing systems. The circuit  100  comprises three functional areas, a power supply  120 , a firing circuit  140 , and a controller  160 .  
         [0018]    The power supply  120  comprises the following components: a solid-state lithium (SSLi) battery BT 1 ; a switch SW 1 ; resistors R 9 , R 10 , and R 12 ; capacitors C 1 , C 5 , and C 6 ; and a low quiescent regulator U 2 .  
         [0019]    The power supply  120  regulates input voltages from a power source (battery BT 1  in this case) ranging from 2 volts to 12 volts to one of two output levels determined by the controller  160 . In this exemplary embodiment, the two output voltages are 2 volts and 3 volts. The regulator U 2  in this exemplary embodiment is a Maxim MAX1725 regulator which operates at a current of less than 3.0μ amperes. The resistors R 10  and R 12  form a feedback network that determines the voltage level of the output voltage signal line  122 . The feedback network is coupled to the controller  160  by a resistor R 9  whereby the controller  160  can control the output voltage signal  122  by altering the feedback to the regulator U 2 . The capacitors C 1 , C 5  and C 6  provide stability and filtration.  
         [0020]    In addition to generating the voltage on output voltage signal line  122 , the power supply  120  charges capacitor C 3  of the firing circuit  140  to the same voltage as the battery BT 1 . The firing circuit  140  is connected to the output of the battery BT 1  before the regulator U 2  so the firing circuit  140  can benefit from the full potential of the battery BT 1 .  
         [0021]    The firing circuit  140  comprises the following components: resistors R 1 , R 3  and R 5 ; capacitors C 3  and C 4 ; and a silicon controlled rectifier (SCR) D 1 . The firing circuit  140  stores energy in the form of a charge on capacitor C 3  and delivers a firing energy to the output JH 1  in response to a firing signal from the controller  160  on output signal line  142 . The resistor R 1  couples the firing circuit  140  to the power supply  120  and limits the peak current drawn by the firing circuit  140  from the battery BT 1 , in this case to  50 μ amperes. In addition to limiting current drawn from the battery BT 1 , the resistance of resistor R 1  is also chosen so the RC time constant of resistor R 1  and capacitor C 3  allows capacitor C 3  to adequately charge prior to delivery of the firing energy to output JH 1 . In this exemplary embodiment, the RC time constant is chosen to be below 12 seconds to ensure that capacitor C 3  is fully charged within about  45  seconds after switch SW 1  is closed.  
         [0022]    The firing signal generated by the controller  160  on output signal line  142  is coupled to the SCR D 1  via a resistor R 3 . In response to the firing signal from the controller  160 , the SCR D 1  will act like a closed switch and current will flow from the charged capacitor C 3  to the output JH 1 , thereby ‘dumping’ the firing energy into an output device (not shown). In this exemplary embodiment, the output device is a pyrotechnic device, and, more particularly, is an electrically initiated detonator under the part name M100.  
         [0023]    The controller  160  comprises the following components: resistors R 2  and R 4 ; capacitor C 2 ; quartz crystal Y 1 ; and mixed signal microcontroller U 1 . The controller  160  functions, via firmware, to control the voltage level of the output voltage signal line  122  output by the regulator U 2 , to compensate for the startup delay of the crystal Y 1  and keep time, and to generate the firing signal on output signal line  142 .  
         [0024]    In this exemplary embodiment, the microcontroller U 1  is a Texas Instruments MSP430F1101PW Mixed Signal Microcontroller. The microcontroller U 1  has three operating modes, one of which is a low power mode. In the low power mode, the microcontroller U 1  is clocked by a low frequency, standard 32.768 kHz crystal Y 1 , and typically operates at a current below 2μ amperes.  
         [0025]    A low frequency crystal oscillator is used due to its low power requirement. Low frequency crystal oscillators provide high accuracy timing; however they have a long startup delay that is exacerbated in low current environments. This may result in inaccurate timing from power-on-reset (POR). For example, if a crystal oscillator inconsistently takes between 200 m seconds and 600 m seconds to start, this may result in a significant and undesirable error in timing from POR.  
         [0026]    The controller  160  corrects for the startup delay of the crystal oscillator by means of firmware discussed subsequently to achieve high accuracy timing from power-on-reset (POR) in a low current system. It should be noted that equipping controller  160  with firmware for achieving high accuracy timing is optional in many applications where such high accuracy timing is not critical, including self-destruct circuits. Thus, although controller  160  in this embodiment includes such firmware for startup delay correction, it is not a requirement to achieve the long-shelf life and other advantages associated with this embodiment.  
         [0027]    Immediately following POR, a microprocessor begins counting via an internal RC oscillator that has a negligible startup delay. The RC oscillator has an unknown frequency due to variances in its oscillation frequency of up to 100% that result from wide temperature and process variations. When the crystal oscillator starts, the microprocessor stores the number of cycles of the RC oscillator since POR. This provides the crystal startup time in terms of the RC oscillator cycles at an unknown frequency.  
         [0028]    In order to accurately determine the crystal startup time, the number of RC oscillator cycles occurring during the startup time is then converted to a number of crystal oscillator cycles which are at a known frequency. This is accomplished by timing the number of RC oscillator cycles during a predetermined number of crystal oscillator cycles. The accurate startup time may then be applied to calculate an accurate system time from POR.  
         [0029]    The operation of the microcontroller U 1  is described below with reference to flow charts of a main processor routine shown in FIG. 2, a timer interrupt service routine shown in FIG. 3, and a watchdog interrupt service routine shown in FIG. 4.  
         [0030]    The microcontroller U 1  comprises an internal RC oscillator that functions as a clock source for the central processing unit (CPU) of the microcontroller upon power-on-reset. With reference to FIG. 2, upon power-on-reset (step  202 ), the microcontroller U 1  configures (step  204 ) an internal timer (Timer A) to count the cycles of the internal RC oscillator. The Timer A interrupt is then enabled (step  206 ) to generate an interrupt upon any overflow of Timer A that may occur. Listed below is exemplary firmware in pseudo C code to implement the above functions.  
                                                 // Initialize Xtal startup timing                BCSCTL1 = 0x84;   // ACLK = 1/1 Xtal           BCSCTL2 = 0x00;   // SMCLK = 1/1 DCOCLK           CCR0 = 0xFFFF;   // Set CCR0 to max           TACTL = 0x2D4;   // Timer = 1/1 SMCLK           CCTL0 = CCIE;   // enable CCR0 interrupt                      
 
         [0031]    After setting up Timer A and enabling its interrupts, the CPU will continue initializing the remaining hardware and software registers (step  208 ). The CPU also initializes the Watchdog Timer (steps  210 ,  212 ) so that it will generate an interrupt after the crystal oscillator begins oscillating. Listed below is exemplary firmware in pseudo C code to implement the above functions.  
                                                                             //Now setup the ports                P1OUT = 0;   // All outputs = 0           P1DIR = 0xF3;   // same as above           IE1 |= WDTIE;   // enable watchdog interrupts           _EINT( );                WDTCTL = 0x5A1F;   // Start WDT as 1.953 mSec Timer                Proc_Time = D_Proc_Time;   // Get default proc_time                      
 
         [0032]    At this point the main processor routine waits until the Watchdog Interrupt Service Routine completes its tasks. To save power, the CPU is placed in the low power ‘sleep’ mode (step  214 ). Listed below is exemplary firmware in pseudo C code to implement the above functions.  
                                                                     // Check Xtal startup flag - wait for watchdog interrupt                while (XtalFlg == 0)           {                _BIS_SR(CPUOFF);   // Enter LPM0                }                      
 
         [0033]    The watchdog timer interrupt service routine, described with reference to FIG. 4, is first used to indicate when the crystal Y 1  oscillator is oscillating. The watchdog timer is clocked by the crystal oscillator. Upon the occurrence of a first watchdog interrupt indicating the startup of the crystal oscillator, the current Timer A value is saved (step  404 ) in a temporary location, Temp_TA, for later use within the watchdog timer interrupt service routine. The routine will then proceed depending on the value of the variable XcntFlg (step  406 ). The value of XcntFlg will be zero upon the first watchdog interrupt to cause the first interrupt to store the value of Temp_TA, which is the Timer A count representing the number of oscillations of the RC oscillator before crystal Y 1  startup, in X_Count (step  408 ). The value of XcntFlg is then set to 1 (step  410 ) and the watchdog interrupt service routine is exited (step  412 ).  
         [0034]    Upon the next occurrence of a watchdog interrupt, the current Timer A value is saved (step  404 ) in a temporary location, Temp_TA, for later use within the watchdog timer interrupt service routine. The value of XcntFlg=1 is set after the first watchdog interrupt and the routine will proceed (from step  406 ) to save Temp_TA (Timer A value) in P-Count (step  414 ). The value now stored in P-Count represents the number of oscillations of the RC oscillator in 1.953 ms. The watchdog interrupt is disabled (step  416 ) and the CPU is returned to the run mode (step  418 ) so that the main processor routine can continue (with step  216  in FIG. 2) before exiting (step  412 ) the watchdog interrupt service routine after the second watchdog interrupt. Listed below is exemplary firmware in pseudo C code to implement the watchdog interrupt service routine.  
                                                                                                                                                                                     // ***** Watchdog Timer interrupt service routine       interrupt[WDT_VECTOR] void watchdog timer(void)       {                Temp_TA = TA_HW * 0x10000 + TAR; // Save current Timer                if (XcntFlg == 0)   // Is this X_Count (first time?)           {                X_Count = Temp_TA;   // Yes - save as X_Count           XcntFlg = 1;   // and mark as complete                }           else           {           P_Count = Temp_TA - X_Count: // save P_Count           if (P_Count &gt; 0xFE00)                {   // P_Count Long - crystal must            // not be running properly                X_Count = Temp_TA;   // Resave X_Count                }           else                {   // Within range - must be P_Count                WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer                IE1 &amp; !WDTIE;   // disable watchdog interrupts           LPM4_EXIT;   // leave LPM           XtalFlg = 1;   // we&#39;re done timing                }            }                  
 
         [0035]    Once the watchdog interrupt service routine has completed, the CPU is returned to the run mode. With reference to FIG. 2, the main processor routine then calculates the startup time (Proc_Time) of the crystal oscillator (step  216 ).  
         [0036]    //Calculate crystal startup time (in terms of final timer counts)  
         [0037]    Proc_Time=4*(X_Count/P_Count);  
         [0038]    This startup time will be subtracted from desired time to self-destruct (step  218 ) and Timer A is then re-initialized and preset with the desired time minus the startup delay time (step  220 ). The CPU sets the output voltage signal  122  to 2 volts (step  222 ) by altering the feedback to regulator U 2  to reduce power consumption and the CPU is then again placed in the low power mode (step  224 ) while it waits for the Timer A interrupt to occur at the desired time.  
                                                                                                             // Restart Timer with final countdown                CCR0 = Timeout - Proc_Time;   // calculate timer setting           TACTL = 0x00;   // disable timer           BCSCTL1 |= DIVA1 + DIVA0;   // set clock for Aclk = 1/8 Xtal           TACTL = 0x1D4;   // restart timer 1/8 Aclk           CCTL0 |= CCIE;   // enable timer interrupt                TmrFlg = 1;   // This is it!            // Go to sleep . . .                while (1)           {                _BIS_SR(LPM3);   // Enter LPM3 (just timer running                }            } // END OF MAIN                  
 
         [0039]    The Timer A interrupt service routine is described with reference to FIG. 3. Timer A serves two functions. As described above with regard to FIG. 2 (step  206 ), Timer A is initially clocked by the RC oscillator and configured to count the oscillations of the RC oscillator and generate an interrupt (step  302 ) upon an overflow. To ensure that an overflow does not affect calculations, an additional 16 bits of resolution is added in firmware. This is implemented by incrementing TA_HW (step  304 ) upon each Timer A interrupt. The Tmr_Flg equals 0 during this first function of Timer A and the interrupt routine is exited (step  312 ) after each interrupt which increments TA_HW.  
         [0040]    The second function of Timer A is to perform the timing for triggering the SCR. Timer A is initialized to perform this second function when the main processor routine (described above with reference to FIG. 2) reinitializes Timer A (step  220 ) to be clocked by the crystal oscillator and to perform the timing function for initiating generation of the firing signal by the controller  160  on output signal line  142 . The reinitialization by the main processor routine includes setting the Tmr_Flg to 1 (see step  220  with regard to FIG. 2 and the main processor routine). When a Timer A interrupt is generated (step  302 ) after Timer A counts to the desired time minus the startup delay time, because Tmr_Flg now equals 1 (step  306 ), the routine proceeds to increase the voltage level of output voltage signal line  122  to three volts (step  308 ) and then fires the SCR (step  310 ) and the M100 detonator. Listed below is exemplary firmware in pseudo C code to implement the Timer A interrupt service routine.  
                                                                                                                     // ***** Timer A0 interrupt service routine (CCFIG0)       interrupt[TIMERA0_VECTOR] void Timer_A0 (void)       {                ++TA_HW;   // Increment High word           if(TmrFlg == 1)           {                while (1)   // DO THIS LOOP FOREVER           {                P1OUT &amp;= !Vdwn;   // power up to 3.3V (Vdwn = 0)                P1OUT |= Output;   // Fire SCR                }                }            }                  
 
         [0041]    While others have rejected the use of SSLi batteries for cold temperature applications, the above-described exemplary fuzing system exploits the advantage of a long shelf life of an SSLi battery while compensating for its poor low temperature performance by combining the battery with an ultra low current microcontroller circuit. As used herein, the term “ultra low current” is less than twenty-five microamperes (25 μA or 25 millionths of an ampere).  
         [0042]    Each component of the circuit may consume current once the switch SW 1  is closed. The current budget of the circuit is analyzed below by calculating the net draw on the battery BT 1  by summing of all the individual currents loops (in accordance with Kirchhoff&#39;s Second Law at any point in a circuit where the current can divide, the sum of the currents into a junction must equal the sum of the currents out of the junction). The current budget of the exemplary circuit of FIG. 1 is estimated below in Table  1  on a per loop basis using worst-case average currents. As used in Table  1  below, the term “A+B” means A in series with B and the term “A∥B” means A in parallel with B.  
                                         TABLE 1                                   Current Loop   Current (μA)                                        U1 + Y1 + (R2∥R4)   2           U2   3           R1 + [C3∥(R5 + D1 AC )]   4           R3 + (C4∥D1 GC ) + R5   0           R10 + (R9∥R12)   2           C1∥C6   &lt;1           C5∥C2   &lt;1           TOTAL   &lt;14                      
 
         [0043]    The above calculation is for a worst scenario and the typical current budget for the exemplary circuit is 8 μA. Other applications may require additional current but are not expected to exceed 25 μA.  
         [0044]    The remaining capacity of a 100 tA 1 cm 2  battery after 20 years is calculated according to the following formula:  
           R=C* (1− Apt )  
         [0045]    Where R is the remaining capacity, C is the starting capacity, A is cathode surface area, p is the percent discharge per unit time per unit surface area, and t is tine. After 20 years, the remaining capacity R equals  
           R= 100*(1−1*0.02*20)=60 μAh  
         [0046]    A circuit according to the exemplary embodiment requires about 0.7 μAh to function for two minutes which is within the remaining capacity R of the battery.  
       Second Exemplary Embodiment  
       [0047]    [0047]FIG. 5 is a block diagram  500  of a circuit according to the second exemplary embodiment described below with reference to the circuit of FIGS.  6 A-D. The circuit of FIGS.  6 A-D comprises seven functional areas: a power supply  600 ; a rectifier  610 ; a charge storage circuit  620 ; an analog input circuit  630 ; a controller  640 ; a firing circuit  650 ; and an optional second safety  660 . The energy to power the circuit is delivered to the circuit as a pulse that charges a bank of capacitors. In order to survive a timing demand of  24  seconds and retain sufficient energy for detonation, the circuit is designed to draw less than 25 uA. A crystal Y 2  provides an accurate time reference and a low frequency crystal consumes less operating current than a high frequency crystal. This trade-off is negated in accordance with the method described above with regard to the first exemplary embodiment to obtain high timing accuracy with low current consumption.  
         [0048]    With reference to FIG. 6A, the rectifier  610  comprises dual diodes D 2  and D 3  and resistor R 6 . The dual diodes D 2  and D 3  are configured as a variation of a bridge rectifier. There is a setter signal which has a positive going portion and a negative going portion that comes from a fire control system. The setter signal is isolated from ground and is manifested as a positive or negative potential between input signals CHG 1  and CHG 2 . The input signal CHG 1  is first positive relative to CHG 2  and then the potential is reversed so that CHG 1  is negative relative to CHG 2 . The exemplary circuit of FIGS.  6 A-D uses the setter signal for two purposes: 1) the signal is interpreted for timing information contained in the peak-to-peak amplitude; and 2) the negative going portion of the setter signal is used as a power source for the circuit.  
         [0049]    The charge storage circuit  620  comprises two banks of capacitors identified by the voltage they bare: bank Vcp comprising capacitors C 17 , C 18  and C 19  and bank Vcn comprising capacitors C 10 , C 11 , C 12  and C 13 . The rectifier  610  directs the positive portion of the setter signal to bank Vcp and the negative portion of the setter signal to bank Vcn and ensures that the charge stored on both capacitor banks is positive relative to the microcontroller U 3  (FIG. 6B). The resistor R 6  of the rectifier  610  is a pulldown resistor used to start the timer when a setback switch (not shown) connects the CHG 1  signal to the STRT signal resulting in a voltage drop on pin 3 of U 3  to trigger the start.  
         [0050]    The total capacitance of bank Vcp is 12 μF and it records the maximum positive voltage of the setter signal, which contains timing information, and may be selectable as a possible energy source for the optional second safety. The total capacitance of bank Vcn is 132 μF and it records the maximum negative voltage of the setter signal, which contains timing information, provides a source of power during the timing phase, and may be selectable as a possible energy source for the optional second safety.  
         [0051]    The power supply comprises a regulator U 4 , a zener diode D 4 , resistors R 11 , R 18 , R 19  and R 20 , and capacitors C 7  and C 8 . Like the first exemplary embodiment, the power supply is based on the Maxim MAX1725 low quiescent voltage regulator, however; in this case, there is not a battery. The resistor R 11  and zener D 3  make up a protective pre-regulator that protects the input of the regulator U 4  from voltages greater than 12 volts. The resistors R 19  and R 20  form a feedback network that determines the voltage level of output voltage signal line  622 . The feedback network is coupled to the controller  640  by a resistor R 18  thereby permitting the controller  640  to control the output voltage by altering the feedback. The power supply  600  includes a capacitor C 7  for stability and a capacitor C 8  as a high frequency noise bypass.  
         [0052]    The analog input circuit comprises resistors R 14 , R 15  and R 16 , R 17  arranged as a pair of voltage dividers. The analog input circuit interfaces the capacitor banks of the charge storage circuit  620  to the analog to digital (A/D) converters of the microcontroller U 3  (in FIG. 6B). The analog input circuit  630  scales the Vcn and Vcp signals into a range below 3 volts for A/D conversion. The resistors R 16 , R 17  divide the Vcp signal by a ratio of approximately 4.3:1 (approximately 23%) to become V_CP. The resistors R 14 , R 15  divide the Vcn signal by a ratio of approximately 5.9:1 (approximately 17%) to become V_CN.  
         [0053]    With reference to FIG. 6B, the controller circuit  640  comprises a mixed signal microcontroller U 3 , a header J 1 , resistors R 21 , R 22  and R 7 , and a crystal Y 2 . In this exemplary embodiment, the microcontroller U 3  is a Texas Instruments MSP430F1122 Mixed Signal Microcontroller that is an ultra low current microcontroller with embedded hardware A/D converters. The microcontroller U 3  serves to vary the power supply  600  voltage signal  622  Vcc, to analog to digitally A/D convert V_CP and V_CN to interpret timing information within the setter signal, to compensate for the crystal Y 2  startup delay and keep time, to optionally function either of the second safety SCR&#39;s, if applicable and to signal the firing circuit time out.  
         [0054]    The header J 1  is a JTAG port and enables a computer interface to read and write the program memory. This provides a data-recording feature to allow post-event access to and analysis of critical launch and process information such as setback time, temperature, and A/D conversion values.  
         [0055]    The firing circuit  650  comprises a silicon controlled rectifier SCR 1 , resistors R 8 , R 13 , and a capacitor C 9 . A resistor R 8  interfaces the microcontroller U 3  to the gate of the SCR 1 . The firing energy is provided by the charge that remains on the Vcn capacitor bank at the time the microcontroller U 3  activates the SCR 1  signal. In this exemplary embodiment, the output signal OUT at connector JH 8  is coupled to an M84 electrical detonator. The energy of this output signal OUT must be 50 μJ (500 erg) or more as is required to initiate the detonator. The capacitor C 9  is a filter and the resistor R 13  prevents the inadvertent triggering of SCR 1  due to noise and/or the sudden appearance of the M84 impedance upon arming.  
         [0056]    The optional second safety  660  comprises a pair of firing circuits comprising silicon controlled rectifiers SCR 2 , SCR 3 , resistors R 14 , R 15 , and capacitors C 14 , C 15 , and C 16 . This provides the optional ability to function a piston actuator as a second safety whereby the controller U 3  will function the piston from either Vcp signal or the Vcn signal, depending on whether or not the former has sufficient energy. A capacitor C 16  limits the amount of energy delivered in the event the piston shorts rather than opens post initiation while capacitors C 14 , C 15  are filters.  
         [0057]    The microcontroller U 3  comprises an internal RC oscillator that functions as a clock source for the central processing unit (CPU) of the microcontroller upon power-on-reset (POR). With reference to FIG. 7, upon power-on-reset (step  702 ), the microcontroller U 3  configures (step  704 ) an internal timer (Timer A) to count the cycles of the internal RC oscillator. The Timer A interrupt is then enabled (step  706 ) so that an interrupt is generated upon any overflows of Timer A that may occur. Listed below is exemplary firmware in pseudo C code to implement the above functions.  
                                                 // Initialize Xtal startup timing                BCSCTL1 = 0x84;   // ACLK = 1/1 Xtal           BCSCTL2 = 0x00;   // SMCLK = 1/1 DCOCLK           CCR0 = 0xFFFF;   // Set CCR0 to max           TACTL = 0x2D4;   // Timer = 1/1 SMCLK           CCTL0 = CCIE;   // enable CCR0 interrupt                      
 
         [0058]    After setting up Timer A and enabling its interrupts, the CPU will continue initializing the remaining hardware and software registers (step  708 ) required for the timing tasks. The CPU also initializes the Watchdog Timer (steps  710 ,  712 ) so that it will generate an interrupt after the crystal oscillator begins oscillating. Listed below is exemplary firmware in pseudo C code to implement the above functions.  
                                                                             // OK Now setup the ports                P1OUT = 0;   // All outputs = 0           P1DIR = 0xF3;   // same as above           IE1 |= WDTIE;   // enable watchdog interrupts           _EINT( );                WDTCTL = 0x5A1F;   // Start WDT as 1.953 mSec Timer                Proc_Time = D_Proc_Time;   // Get default proc_time                      
 
         [0059]    The main routine now enables the A/D converter and converts (step  714 ) both the range (V_CP) and power (V_CN) voltages and, when complete, disables the A/D converter to save power. This A/D conversion is performed while timing the crystal startup with the RC oscillator. All timing functions are accomplished in hardware timers and interrupt service routines and therefore have no special requirements on the main routine. Listed below is exemplary firmware in pseudo C code to implement the A/D conversion.  
         [0060]    //Convert Range and Power analog inputs  
         [0061]    ConvertAnalog (Range, Power);  
         [0062]    At this point the main processor routine waits until the Watchdog Interrupt Service Routine (see description of watchdog interrupt service routine above with reference to FIG. 4 of the first exemplary embodiment) completes its tasks. To save power, the CPU is placed in the low power ‘sleep’ mode (step  716 ). Listed below is exemplary firmware in pseudo C code to implement the above functions.  
                                                                     // Check Xtal startup flag - wait for watchdog interrupt                while (XtalFlg == 0)           {                _BIS_SR(CPUOFF);   // Enter LPM0                }                      
 
         [0063]    Once the watchdog interrupt service routine has completed, the CPU is returned to the run mode. The main processor routine then calculates the startup time of the crystal oscillator (step  718 ) as described above with regard to the first exemplary embodiment.  
         [0064]    Timer A is then updated with the correct timeout value. The correct timeout is calculated (steps  720 ,  722 ) from the range and power voltages that were A/D converted earlier. The timer is started before this calculation so the time to perform the calculation is not added to the desired timeout. Timer A is then re-initialized and preset with the desired time minus the startup delay time (step  724 ).  
                                                                                             // Calculate desired timeout                Timeout = CalculateTimeout (Range, Power);                CCR0 = Timeout - Proc_Time;   // calculate timer setting            // Restart Timer with final countdown                CCR0 = Timeout - Proc_Time;   // max timer setting           TACTL = 0x00;   // disable timer           BCSCTL1 |= DIVA1 + DIVA0;   // set clock for Aclk = 1/8 Xtal           TACTL = 0x1D4;   // restart timer 1/8 Aclk           CCTL0 |= CCIE;   // enable timer interrupt                TmrFlg = 1;   // This is it!                      
 
         [0065]    The CPU then sets the PWR_DN signal to alter the power supply  600  feedback to regulator U 4  to reduce the output voltage Vcc to 2 volts (step  726 ) to reduce power consumption. The CPU is then again placed in the low power mode (step  728 ) while it waits for the Timer A interrupt. The main routine has completed its task and therefore has an endless loop around the sleep command to protect against a run-away condition. The final detonation function is carried out in the Timer A Interrupt Service Routine.  
                                                                           // Go to sleep . . .                while (1)           {                _BIS_SR(LPM3);   // Enter LPM3 (just timer running                }            } // END OF MAIN                  
 
         [0066]    The watchdog timer interrupt service routine, described with reference to FIG. 9, is used to indicate when the crystal Y 2  oscillator is oscillating. The watchdog timer is clocked by the crystal oscillator. Upon the occurrence of a first watchdog interrupt indicating the startup of the crystal oscillator, the current Timer A value is saved (step  904 ) in a temporary location, Temp_TA, for later use within the watchdog timer interrupt service routine. The routine will then proceed depending on the value of the variable XcntFlg (step  906 ). The value of XcntFlg will be zero upon the first watchdog interrupt resulting in the first interrupt causing the value of Temp_TA, which is the Timer A count representing the number of oscillations of the RC oscillator before crystal Y 1  startup, to be stored in X_Count (step  908 ). The value of XcntFlg is then set to 1(step  910 ) and the watchdog interrupt service routine is exited (step  912 ).  
         [0067]    Upon the next occurrence of a watchdog interrupt, the current Timer A value is saved (step  904 ) in temporary location Temp_TA for later use within the watchdog timer interrupt service routine. The value of XcntFlg now equals 1 as set after the first watchdog interrupt and the routine will proceed (from step  906 ) to save Temp_TA (Timer A value) in P-Count (step  914 ). The value now stored in P-Count represents the number of oscillations of the RC oscillator in 1.953 ms. The watchdog interrupt is then disabled (step  916 ) and the CPU is returned to the run mode (step  918 ) so that the main processor routine can continue (with step  718  in FIG. 7) before exiting (step  912 ) the watchdog interrupt service routine. Listed below is exemplary firmware in pseudo C code to implement the watchdog interrupt service routine.  
                                                                                                                                                                                     // ***** Watchdog Timer interrupt service routine       interrupt[WDT_VECTOR] void watchdog timer(void)       {                Temp_TA = TA_HW * 0x10000 + TAR; // Save current Timer                if (XcntFlg == 0)   // Is this X_Count (first time?)           {                X_Count = Temp_TA;   // Yes - save as X_Count           XcntFlg = 1;   // and mark as complete                }           else           {           P_Count = Temp_TA - X_Count: // save P_Count           if (P_Count &gt; 0xFE00)                {   // P_Count Long - crystal must            // not be running properly                X_Count = Temp_TA;   // Resave X_Count                }           else                {   // Within range - must be P_Count                WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer                IE1 &amp; !WDTIE;   // disable watchdog interrupts           LPM4_EXIT;   // leave LPM           XtalFlg = 1;   // we&#39;re done timing           }                }            }                  
 
         [0068]    The Timer A interrupt service routine, described with reference to FIG. 8. Timer A serves two functions. As described above with regard to FIG. 7 (step  706 ), Timer A is initially clocked by the RC oscillator and configured to count the oscillations of the RC oscillator and generate an interrupt (step  802 ) upon an overflow. To ensure that an overflow does not affect calculations, an additional 16 bits of resolution is added in firmware. This is implemented by incrementing TA_HW (step  804 ) upon each Timer A interrupt. Thus,  
         [0069]    TA_HW functions as the high order 16 bits of the count of the RC oscillator. The Tmr_Flg equals 0 during this first function of Timer A and the interrupt routine is exited (step  812 ).  
         [0070]    Timer A is initialized for its second function after the second watchdog interrupt occurs when the main processor routine (described above with reference to FIG. 7) reinitializes Timer A (step  724 ) to be clocked by the crystal oscillator and to perform the timing function for initiating generation of the firing signal by the controller  160  on output signal line  142 . The reinitialization by the main processor routine includes setting the Tmr_Flg to 1 (see step  724  with regard to FIG. 7 and the main processor routine). When a Timer A interrupt is generated (step  802 ) after Timer A counts to the desired time minus the startup delay time, because Tmr_Flg now equals (step  806 ), the routine proceeds to increase the voltage level of output voltage signal line  622  to three volts (step  808 ) and then fires the SCR 1  (step  810 ). Listed below is exemplary firmware in pseudo C code to implement the Timer A interrupt service routine.  
                                                                                                                     // ***** Timer A0 interrupt service routine (CCFIG0)       interrupt[TIMERA0_VECTOR] void Timer_A0 (void)       {                ++TA_HW;   // Increment High word           if(TmrFlg == 1)           {                while (1)   // DO THIS LOOP FOREVER           {                P1OUT &amp;= !Vdwn;   // power up to 3.3V (Vdwn = 0)                P1OUT |= Output;   // Fire SCR                }                }            }                  
 
         [0071]    Thus, the second exemplary embodiment allows a system to achieve high accuracy timing from POR at a very low current. This is possible due to the correction of the crystal startup delay. With the correction, the standard deviation of timing from POR is less than 8 ms despite crystal startup delays arbitrarily ranging between 200 ms and 600 ms. Although higher frequency crystal oscillators can start almost instantly and theoretically could provide comparable standard deviations, such high frequency crystal oscillators require a greater operating current and would result in a low power system running out of power before function (detonation) time. The present invention allows a system using a low frequency crystal oscillator to have the same quick start timing that a high frequency crystal oscillator provides but without the high current consumption of a high frequency crystal.  
         [0072]    Although illustrated and described above with reference to certain specific embodiments, the present invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention.