Abstract:
A matched set of integrated circuit chips ( 74, 78 ) and a method for assembling such integrated circuit chips ( 74, 78 ) into a matched set are disclosed. A first semiconductor wafer ( 62 ) having a plurality of integrated circuit chips ( 74 ) of a first type and a second semiconductor wafer ( 64 ) having a plurality of integrated circuit chips ( 78 ) of a second type are electrically and mechanically coupled to an interposer ( 52 ) to form a wafer-interposer assembly ( 50 ). The integrated circuit chips ( 74, 78 ) of the first and second wafers ( 62, 64 ) are then tested together. The wafer-interposer assembly ( 52 ) is then diced into a plurality of chip assemblies having chips ( 74 ) of the first type and a plurality of chip assemblies having chips ( 78 ) of the second type. Based upon the testing, at least one of the chip assemblies having chips ( 74 ) of the first type and at least one of the chip assemblies having chips ( 78 ) of the second type are selected for inclusion in the matched set.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention relates in general to integrated circuits and, more particularly, to wafer level testing and selection of system components for a match set using an interposer that accommodates multiple wafers containing the component parts of the matched set. 
     BACKGROUND OF THE INVENTION 
     Modern electronic devices utilize semiconductor chips, commonly referred to as integrated circuits, which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect the chips with other elements of the circuit. Such substrates may then be secured to an external circuit board or chassis. 
     The size of the chips and substrate assembly is a major concern in modern electronic product design. The size of each subassembly influences the size of the overall electronic device. Moreover, the size of each subassembly controls the required distance between each chip and between chips and other elements of the circuit. Delays in transmission of electrical signals between chips are directly related to these distances. These delays limit the speed of operation of the device. Thus, more compact interconnection assemblies, with smaller distances between chips and smaller signal transmission delays, can permit faster operations. 
     One approach for improving overall system performance is through the use of matched sets. For example, several identical or dissimilar components that have been identified by the individual testing phase of component processing to have certain performance tracking characteristics may be assembled together as a matched set. The components of such a matched sets are frequently attached to a single substrate in close proximity to one another. This strategy improves performance compared to conventional or non-optimized systems by reducing the overall space needed to accommodate the chips and by, among other things, shortening the distance between chips. Specifically, interconnect inductance and signal transmission delays are all reduced. 
     One type of matched set includes a collection of identical components which have been identified to meet specific system performance requirements. For example, radio frequency (RF) systems often employ identical filters, switches, power dividers, mixers and high frequency amplifiers. Typically, each of the identical components has been extensively tested individually prior to inclusion in this type of system. The individual characterization tests for a filter, for instance, might measure insertion loss and phase shift as a function of frequency, input power and temperature. These multi-dimensional arrays of data are then compared to each other to identify individual components that perform within acceptable limits relative to each other. Components that are found to exhibit similar behavior under the various input stimuli will constitute a matched set of identical devices. Conversely, components that are found to exhibit dissimilar behavior under the various input stimuli, for example, the gain of one component having a negative slope over temperature while the gain of another component having a positive slope over temperature, will constitute a mismatch of components that will not be placed in a chip collection. 
     Another type of matched set includes components of different device types that are combined such that the aggregate, cascaded performance meets system specifications. Mixed signal systems, for example, often utilize digital-to-analog (DAC) converters along with operational amplifiers (OpAmp) to process data. The performance of a product can often be improved by pairing a DAC with an OpAmp of similar performance. That is, the input characteristics of the OpAmp are optimized to match the output characteristics of the DAC. As in the case of the matched set of identical components described above, the component of a matched set of different components are also identified by comparing multi-dimensional arrays of data to each other to identify individual components that perform within acceptable limits relative to each other. Components that are found to exhibit similar behavior under the various input stimuli will form a matched set of different components while components that are found to exhibit dissimilar behavior under the various input stimuli are not placed in a chip collection due to the mismatch. 
     It has been found, however, the certain mismatches are not identified when the components are tested individually. In fact, certain mismatches are not identified until the entire chip collection is assembled and the components are tested together for the first time. As such, some chip collections must be disassembled so that the valuable components may be, for example, packaged as individual components, while other chip collections are simple discarded. 
     Therefore, a need has arisen for an improved method for selection of system components for a matched set. A need has also arisen for such a method that does not require elaborate data reduction of test results from individually tested components. Additionally, a need has arisen for such a method that allows for testing of the individual components together prior to the assembly of the matched set. 
     SUMMARY OF THE INVENTION 
     The present invention disclosed herein provides a chip collection, known as a matched set, that maximizes system performance by selecting well matched integrated circuit chips for assembly together into the matched set. The present invention achieves this result by allowing for testing of the various integrated circuit chips together prior to the assembly of the matched set. This testing utilizes a wafer level interposer that accommodates multiple wafers that contain all of the chips to be included in the matched set. This combination is referred to as a wafer-interposer assembly. In the present invention, this wafer-interposer assembly is diced into a plurality of chip assemblies that are assembled into the matched set. 
     In its broadest form, the present invention provides for the attachment of two semiconductor wafers each having a plurality of integrated circuit chips thereon to the interposer for testing of the integrated circuit chips. The integrated circuit chips of the first wafer may be of the same type as the integrated circuit chips of the second wafer, such as DRAM chips. Alternatively, the integrated circuit chips of the first wafer may be of a different type from the integrated circuit chips of the second wafer. For example, the integrated circuit chips of the first wafer may be amplifiers while the integrated circuit chips of the second wafer may be controllers. Likewise, the integrated circuit chips of the first wafer may carry the same type of signal as the integrated circuit chips of the second wafer, such as analog signals for an amplifier. Alternatively, the integrated circuit chips of the first wafer may carry a different type of signal than the integrated circuit chips of the second wafer. For example, the integrated circuit chips of the first wafer may be mixers that carry RF signals while the integrated circuit chips of the second wafer may be DSPs that carry digital signals. 
     Prior to testing, the two wafers are electrically and mechanically coupling to the interposer such that the wafer-interposer assembly may be connected to a testing apparatus. The testing may include performance tests over a range of temperatures, testing for leakage currents, testing for offset voltages and the like to determine which integrated circuit chips from the first wafer could be included in a matched set with particular integrated circuit chips from the second wafer to achieve optimum performance. Likewise, the testing may include grading of the integrated circuit chips of the first wafer and the second wafer for speed or other performance characteristics such that the integrated circuit chips of the first wafer that receive a particular grade are matched with integrated circuit chips from the second wafer having a similar grade. Additionally, the testing may include testing for non-conformance wherein certain integrated circuit chips of the first wafer may not be matched with any integrated circuit chips of the second wafer. 
     Once testing is complete, the wafer-interposer assembly may be diced into a plurality of chip assemblies having chips of the first wafer and a plurality of chip assemblies having chips of the second wafer. One of the chip assemblies having a chip from the first wafer may them be matched with one of the chip assemblies having a chip from the second wafer, for inclusion in a matched set. This selection is based upon the results of the testing of the integrated circuit chips of the first wafer and the integrated circuit chips of the second wafer. Alternatively, more than one of the chip assemblies having chips from the first wafer may be matched with one or more chip assemblies having chips from the second wafer for inclusion in a matched set. 
     Using this process, all or substantially all of the integrated circuit chips from one wafer may be matched with one or more of the integrated circuit chips of a second wafer based upon the desired performance characteristics of the matched set that will contain these devices. By performing the testing prior to assembly of the matched set, the performance characteristics of each of the matched sets assembled using integrated circuit chips of the first and second wafers are enhanced as is the overall performance of the entire lot of matched set devices. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention along with the accompanying figures in which corresponding numerals in the different figures refer to corresponding parts and in which: 
     FIG. 1 is an exploded view of a wafer-interposer assembly of the present invention including two wafers having chips of the same type; 
     FIG. 2 is an exploded view of a wafer-interposer assembly of the present invention including two wafers having chips of different types; 
     FIGS. 3A-3B are cross sectional views taken respectively along line  3 A— 3 A and  3 B— 3 B of FIG. 2; 
     FIG. 4 is an exploded view of a wafer-interposer assembly of the present invention including two wafers having chips of different types; 
     FIG. 5 is an exploded view of a wafer-interposer assembly of the present invention including four wafers having chips of the same type; 
     FIG. 6 is an isometric view of a wafer-interposer assembly of the present invention, being inserted into a testing apparatus; 
     FIG. 7 is an exploded view of a wafer-interposer assembly of the present invention; 
     FIG. 8 is an isometric view of a plurality of chip assemblies after singulation of a wafer-interposer assembly of the present invention; 
     FIG. 9 is an isometric view of a matched set of chip assemblies of the present invention having chips from different wafers in place on a substrate; 
     FIG. 10 is an isometric view of a plurality of chip assemblies after singulation of a wafer-interposer assembly of the present invention; and 
     FIG. 11 is an isometric view of a matched set of chip assemblies of the present invention including chips of different types in place on a substrate. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts which can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not define the scope of the invention. 
     The general features of a wafer-interposer assembly of the present invention are shown in FIG.  1  and are generally designated  10 . Wafer-interposer assembly  10  includes a multi wafer interposer  12 , an array  14  of conductive attachment elements  16  and an array  18  of conductive attachment elements  20 . Wafer-interposer assembly  10  also includes a wafer  22  and a wafer  24 . Interposer  12  has an array  26  of conductive contact pads  28  and an array  30  of conductive contact pads  32  on the upper surface thereof. Arrays  26  and  30  are each split into sixteen sections separated by dotted lines. The dotted lines represent the locations where interposer  12  will be cut when interposer  12  is diced into chip assemblies, including a section of interposer  12  and an associated chip from either wafer  22  or  24 , as will be described in more detail below. It should be noted that while arrays  26  and  30  of interposer  12  are depicted as having sixteen sections in FIG. 1, this depiction is for simplicity and clarity of description as those skilled in the art will recognize that actual interposes will have several hundred or several thousand sections which correspond to the several hundred or several thousand chips on wafers  22  and  24 . 
     Each of the sixteen sections of array  26  has sixteen contact pads  28  and each of the sixteen sections of array  30  has sixteen contact pads  32  depicted therein. The contact pads  28  and  32  represent the locations where interposer  12  will be electrically connected to a substrate once interposer  12  has been diced into chip assemblies, as will be described in more detail below. It should be noted that while array  26  is depicted as having sixteen contact pads  28  in each section and array  30  is depicted as having sixteen contact pads  32  in each section in FIG. 1, this depiction is for simplicity and clarity of description as those skilled in the art will recognize that the actual number of contact pads  28  and  32  in each section will be several hundred or several thousand contact pads. 
     On the lower surface of interposer  12  there are two similar arrays of conductive contact pads (not picture). In the illustrated embodiment, the contact pads on the lower surface of interposer  12  have the same geometry as contact pads  28  and contact pads  32 . As such, there are two arrays each having sixteen sections with sixteen contact pads on the lower surface of interposer  12 . The contact pads on the lower surface of interposer  12  represent the locations where interposer  12  will be electrically connected to wafers  22  and  24 , as will be described in more detail below. It should be noted that the actual number of sections and the actual number of contact pads in each section on the lower surface of interposer  12  will be several hundred or several thousand instead of sixteen. Also, it should be noted that directional terms, such as “above,” “below,” “upper,” “lower,” etc., are used for convenience in referring to the accompanying drawings as it is to be understood that the various embodiments of the present invention described herein may be utilized in various orientations, such as inclined, inverted, horizontal, vertical, etc., without departing from the principles of the present invention. 
     Array  14  of conductive attachment elements  16  is also split into sixteen sections separated by dotted lines. Each of the sections has sixteen conductive attachment elements  16  that correspond to the contact pads on the lower surface of interposer  12  below array  26 . Similarly, array  18  of conductive attachment elements  20  is split into sixteen sections separated by dotted lines. Each of the sections have sixteen conductive attachment elements  20  that correspond to the contact pads on the lower surface of interposer  12  below array  30 . 
     Conductive attachment elements  16  and  20  may be in the shape of balls, bumps, columns and the like. Conductive attachment elements  16  and  20  may be formed from any suitable electrically conductive material such as solder, including tin based solder, gold based solder, zinc based solder, indium based solder and the like. Alternatively, conductive attachment elements  16  and  20  may be formed from a conductive epoxy, a conductive polymer or the like. Conductive attachment elements  16  and  20  may be attached to interposer  12  by any number of attachment techniques including screening, flowing, molding, reflowing, dipping, electroplating, adhering and the like, depending upon which material is used for conductive attachment elements  16  and  20 . In the illustrated embodiment, conductive attachment elements  16  and  20  are the same size, shape and material. As such, conductive attachment elements  16  and  20  may be attached to interposer  12  using the same process. It should be noted by those skilled in the art that conductive attachment elements  16  may be a different size, a different shape, a different material or may be attached to interposer  12  using a different process than conductive attachment elements  20  without departing from the present invention. 
     After assembly, conductive attachment elements  16  of array  14  electrically connect and mechanically bond contact pads  36  of each chip  34  to the facing contact pads on the lower surface of interposer  12 . Likewise, conductive attachment elements  20  of array  18  electrically connect and mechanically bond contact pads  40  of each chip  38  to the facing contact pads on the lower surface of interposer  12 . These permanent electrical and mechanical connections may be achieved using, for example, a heating method such as reflowing or thermal compression. 
     Wafer-interposer assembly  10  also includes wafers  22  and  24  that are attached to the bottom surface of interposer  12 . Wafer  22  has a plurality of chips  34  depicted thereon having dotted lines therebetween that represent the locations where wafer  22  will be cut when wafer  22  is diced into chip assemblies, as will be described in more detail below. Wafer  22  is depicted as having sixteen chips  34 . This depiction is for simplicity and clarity of description as those, skilled in the art will recognize that actual number of chips  34  on wafer  22  will be several hundred or several thousand. 
     Each chip  34  has a plurality of conductive contact pads  36  on its face. Each chip  34  is depicted as having sixteen contact pads  36 , for simplicity and clarity of description, which correspond with one of the conductive attachment elements  16  in array  14  and represent the locations where chips  34  will be electrically connected to interposer  12 . It should be noted by those skilled in the art that the actual number of contact pads  36  on each chip  34  will be several hundred or several thousand instead of sixteen. 
     Likewise, wafer  24  has a plurality of chips  38  depicted thereon having dotted lines therebetween that represent the locations where wafer  24  will be cut when wafer  24  is diced into chip assemblies, as will be described in more detail below. Wafer  24  is depicted as having sixteen chips  38 . This depiction is for simplicity and clarity of description as those skilled in the art will recognize that actual number of chips  38  on wafer  24  will be several hundred or several thousand. 
     Each chip  38  has a plurality of conductive contact pads  40  on its face. Each chip  38  is depicted as having sixteen contact pads  40 , for simplicity and clarity of description, which correspond with one of the conductive attachment elements  20  in array  18  and represent the locations where chips  38  will be electrically connected to interposer  12 . It should be noted by those skilled in the art that the actual number of contact pads  40  on each chip  38  will be several hundred or several thousand instead of sixteen. 
     As such, wafer-interposer assembly  10  allows for the simultaneous testing of chips  34  of wafer  22  and chips  38  of wafer  24 . Simultaneous testing provides added efficiency to the testing process as numerous aspects of the functionality and performance of chips  34  and chips  38  may be tested. Importantly, this type of simultaneous testing allows for a determination of which chips  34  match up best with one another, which chips  38  match up best with one another and which chips  34  match up best with which chips  38 . This allows for optimization of the overall performance of specific matched sets as well as the overall performance of the lot of matched sets made from chips  34  and  38 . In this embodiment, the matched sets will comprise two or more chips of the same type that may come from either wafer  22  or wafer  24 . For example, these matched sets may include multiple SRAM or DRAM components for use in a digital device, multiple amplifiers components for use in an analog device, multiple mixer, attenuator or circulator components for a RF device and the like. 
     Referring now to FIG. 2, therein is depicted a wafer-interposer assembly  50  of the present invention. Wafer-interposer assembly  50  includes a multi wafer interposer  52 , an array  54  of conductive attachment elements  56  and an array  58  of conductive attachment elements  60 . Wafer-interposer assembly  50  also includes a wafer  62  and a wafer  64 . Interposer  52  has an array  66  of conductive contact pads  68  and an array  70  of conductive contact pads  72  on the upper surface thereof. Arrays  66  and  70  are each split into sixteen sections separated by dotted lines which represent the locations where interposer  52  will be diced. 
     Each of the sixteen sections of array  66  has sixteen contact pads  68  and each of the sixteen sections of array  70  has sixteen contact pads  72  depicted therein. The contact pads  68  and  72  represent the locations where interposer  52  will be electrically connected to a substrate once interposer  52  has been diced. 
     On the lower surface of interposer  52  there are two arrays of conductive contact pads (not picture). In the illustrated embodiment, the contact pads on the lower surface of interposer  52  below array  66  have the same geometry as contact pads  68 . The contact pads on the lower surface of interposer  52  below array  70 , however, do not have the same geometry as contact pads  72 , as will be explained in greater detail below. 
     Array  54  of conductive attachment elements  56  is split into sixteen sections separated by dotted lines. Each of the sections has sixteen conductive attachment elements  56  that correspond to the contact pads on the lower surface of interposer  52  below array  66 . Array  58  of conductive attachment elements  60  is split into sixteen sections separated by dotted lines. Each of the sections have thirty-six conductive attachment elements  60  that correspond to the contact pads on the lower surface of interposer  52  below array  70 . In the illustrated embodiment, conductive attachment elements  56  are depicted as being larger than conductive attachment elements  60  and having a larger pitch. Conductive attachment elements  56  and  60  are of the same shape and preferably are of the same material such that conductive attachment elements  56  and  60  may be attached to interposer  52  using the same process, however, this is not a requirement of the present invention. 
     Wafers  62  and  64  are attached to the bottom surface of interposer  52 . Wafer  62  has a plurality of chips  74  depicted thereon having dotted lines therebetween that represent the locations where wafer  62  will be diced. Each chip  74  has a plurality of conductive contact pads  76  on its face. Each chip  74  is depicted as having sixteen contact pads  76 , which correspond with one of the conductive attachment elements  56  in array  54  and represent the locations where chips  74  will be electrically connected to interposer  52 . 
     Likewise, wafer  64  has a plurality of chips  78  depicted thereon having dotted lines therebetween that represent the locations where wafer  64  will be diced. Wafer  64  is depicted as having sixteen chips  78 . Each chip  78  has a plurality of conductive contact pads  80  on its face. Each chip  78  is depicted as having thirty-six contact pads  80 , which correspond with the conductive attachment elements  60  in array  58  and represent the locations where chips  78  will be electrically connected to interposer  52 . 
     In the illustrated embodiment, chips  74  of wafer  62  are of a different type than chips  78  of wafer  64 . As such, wafer-interposer assembly  50  allows for the simultaneous testing of different types of chips  74  and  78  from the two wafers  62  and  64  which provides significant efficiency gains over prior art testing scenarios. Specifically, the functionality and performance of one or more chips  74  and one or more chips  78  may be tested simultaneously to determine whether specific chips  74  match well with specific chips  78  so that matched sets containing chips  74  and  78  may be assembled. For example, these matched sets may include a controller and multiple amplifiers, a RF mixer and a DSP, an ASIC component and multiple SRAMs as well as enumerable other desirable component combinations. 
     Referring next to FIGS. 3A and 3B, cross sectional views of wafer-interposer assembly  50  taken along lines  3 A— 3 A and  3 B— 3 B are depicted. As best seen in FIG. 3A, interposer  52  includes a plurality of layers having routing lines and vias therein which serve as electrical conductors. One set of conductors, depicted as conductors  90 ,  92  and  94 , pass through interposer  52  and serve to electrically connect pads  76  of chips  74  to the contact pads  68  of interposer  52 . Conductors  90 ,  92  and  94  are selected to have suitable conductivity and may be, for example, copper. Interposer  52  also includes a set of testing conductors, depicted as conductor  96 , that pass through interposer  52  connecting some of the contact pads  76  of chips  74  to a testing apparatus as will be explained in greater detail below. The testing conductors may provide direct electrical connection to the testing apparatus or may pass through a multiplexer or other intervening apparatus (not shown) incorporated into interposer  52 . 
     As seen in FIG. 3A, contact pads  76  of chips  74  and contact pads  68  of interposer  52  have identical geometries. The present invention, however, is by no means limited to having identical geometries. As each die design may have unique pad geometry, one of the advantages of the present invention is that the contact pads on the upper surface of interposer  52  may utilize a geometry that is different from that of the contact pads of the chips. Traditionally, chip designers have been limited in chip layout in that all connections between the elements of a chip and the outside world had to be made either through the peripheral edges of the chip (for wire bonding) or at least through a standard pin or pad layout defined by a standardization body, such as the Joint Electrical Dimensional Electronic Committee (JEDEC). The interconnection requirements, therefore, have traditionally driven the chip layout. Chip designs for use with an interposer of the present invention are not limited by such constraints. 
     For example, as best seen in FIG. 3B, interposer  52  includes a plurality of layers having routing lines and vias therein which serve as electrical conductors. One set of conductors, depicted as conductors  98 ,  100 ,  102  and  104  pass through interposer  52  to electrically connect contact pads  72  on the upper surface of interposer  52  to contact pads  80  on chips  78 . Another set of conductors, depicted as conductors  106  and  108 , are testing conductors that pass through interposer  52  and are used to connect certain pads  80  of chips  78  to a testing apparatus, as will be explained in greater detail below. As such, the geometry of pads  72  on the upper surface of interposer  52  may be different from that of pads  80  on chips  78 . 
     Referring now to FIG. 4, therein is depicted a wafer-interposer assembly  110  of the present invention. Wafer-interposer assembly  110  includes a multi wafer interposer  112 , an array  114  of conductive attachment elements  116  and an array  118  of conductive attachment elements  120 . Wafer-interposer assembly  110  also includes a wafer  122  and a wafer  124 . Interposer  112  has an array  126  of conductive contact pads  128  and an array  130  of conductive contact pads  132  on the upper surface thereof. Array  126  is each split into sixteen sections separated by dotted lines which represent the locations where interposer  122  will be diced. Likewise, array  130  is each split into four sections separated by dotted lines which represent the locations where interposer  122  will be diced. 
     Each of the sixteen sections of array  126  has sixteen contact pads  128 . Each of the four sections of array  130  has thirty-six contact pads  132  depicted therein. The contact pads  128  and  132  represent the locations where interposer  112  will be electrically connected to a substrate once interposer  112  has been diced. 
     On the lower surface of interposer  52  there are two arrays of conductive contact pads (not picture). In the illustrated embodiment, the contact pads on the lower surface of interposer  112  below array  126  have the same geometry as contact pads  128  and the contact pads on the lower surface of interposer  122  below array  130  have the same geometry as contact pads  132 . 
     Array  114  of conductive attachment elements  116  is split into sixteen sections separated by dotted lines. Each of the sections has sixteen conductive attachment elements  116  that correspond to the contact pads on the lower surface of interposer  112  below array  126 . Array  118  of conductive attachment elements  120  is split into four sections separated by dotted lines. Each of the sections have thirty-six conductive attachment elements  120  that correspond to the contact pads on the lower surface of interposer  112  below array  130 . In the illustrated embodiment, conductive attachment elements  120  are depicted as being larger than conductive attachment elements  116  and having a larger pitch. Conductive attachment elements  116  and  120  are of the same shape and preferably are of the same material such that conductive attachment elements  116  and  120  may be attached to interposer  112  using the same process, however, this is not a requirement of the present invention. 
     Wafers  122  and  124  are attached to the bottom surface of interposer  112 . Wafer  122  has a plurality of chips  134  depicted thereon having dotted lines therebetween that represent the locations where wafer  122  will be diced. Each chip  134  has a plurality of conductive contact pads  136  on its face. Each chip  134  is depicted as having sixteen contact pads  136 , which correspond with one of the conductive attachment elements  116  in array  114  and represent the locations where chips  134  will be electrically connected to interposer  112 . 
     Likewise, wafer  124  has a plurality of chips  138  depicted thereon having dotted lines therebetween that represent the locations where wafer  134  will be diced. Wafer  134  is depicted as having four chips  138 . Each chip  138  has a plurality of conductive contact pads  140  on its face. Each chip  138  is depicted as having thirty-six contact pads  140 , which correspond with the conductive attachment elements  120  in array  118  and represent the locations where chips  138  will be electrically connected to interposer  112 . 
     In the illustrated embodiment, chips  134  of wafer  122  are of a different type than chips  138  of wafer  124 . As such, wafer-interposer assembly  110  allows for the simultaneous testing of different types of chips  134  and  138  from the two wafers  122  and  124  which provides significant efficiency gains over prior art testing scenarios. Specifically, the functionality and performance of one or more chips  134  and one or more chips  138  may be tested simultaneously to determined whether specific chips  134  match well with specific chips  138 . 
     Referring now to FIG. 5, therein is depicted a wafer-interposer assembly  150  of the present invention. Wafer-interposer assembly  150  includes a multi wafer interposer  152 , an array  154  of conductive attachment elements  156 , an array  158  of conductive attachment elements  160 , an array  162  of conductive attachment elements  164  and an array  166  of conductive attachment elements  168 . Wafer-interposer assembly  150  also includes wafers  170 ,  172 ,  174  and  176 . Interposer  152  has four arrays  178 ,  180 ,  182  and  184  of conductive contact pads  186 ,  188 ,  190  and  192 , respectively, on the upper surface thereof. Arrays  178 ,  180 ,  182  and  184  are each split into sixteen sections separated by dotted lines which represents the locations where interposer  152  will be diced. 
     Each of the sixteen sections of arrays  178 ,  180 ,  182  and  184  have sixteen contact pads  186 ,  188 ,  190  and  192 , respectively. Contact pads  186 ,  188 ,  190  and  192  represent the locations where interposer  152  will be electrically connected to a substrate once interposer  152  has been diced. 
     On the lower surface of interposer  152  there are four arrays of conductive contact pads (not picture). In the illustrated embodiment, the contact pads on the lower surface of interposer  152  below arrays  178 ,  180 ,  182  and  184  have the same geometries as contact pads  186 ,  188 ,  190  and  192 . 
     Arrays  154 ,  158 ,  162  and  166  of conductive attachment elements  156 ,  160 ,  164  and  168 , respectively, are each split into sixteen sections separated by dotted lines. Each of the sections has sixteen conductive attachment elements therein that correspond to contact pads on the lower surface of interposer  152 . 
     Wafers  170 ,  172 ,  174  and  176  are attached to the bottom surface of interposer  152 . Wafers  170 ,  172 ,  174  and  176  each have a plurality of chips  194 ,  196 ,  198  and  200 , respectively, depicted thereon having dotted lines therebetween that represent the locations where wafers  170 ,  172 ,  174  and  176  will be diced. Each chip  194 ,  196 ,  198  and  200  has a plurality of conductive contact pads  202 ,  204 ,  206  and  208 , respectively, on its face. Each chip  194 ,  196 ,  198  and  200  is depicted as having sixteen contact pads  202 ,  204 ,  206  and  208 , respectively, each of which correspond with one of the conductive attachment elements in arrays  154 ,  158 ,  162  and  166  and represent the locations where chips  194 ,  196 ,  198  and  200  will be electrically connected to interposer  152 . 
     In the illustrated embodiment, each of the chips  194 ,  196 ,  198  and  200  on the various wafers  170 ,  172 ,  174  and  176  are of the same type. As such, wafer-interposer assembly  150  allows for the simultaneous testing chips  194 ,  196 ,  198  and  200  on all four wafers  170 ,  172 ,  174  and  176  which provides significant efficiency gains over prior art testing scenarios. As with the embodiment depicted in FIGS. 2 and 4, it should be understood by those skilled in the art that an interposer that accommodates four wafers could alternatively be used to simultaneously test wafers that have different types of chips thereon. It should also be understood by those skilled in the art that an interposers of the present invention may accommodate and be used to test other numbers of wafers, either greater than or less than that depicted herein without departing from the principles of the present invention. 
     Referring now to FIG. 6, therein is depicted wafer-interposer assembly  10  of FIG. 1 connected to a testing unit  220 . Wafer-interposer assembly  10  interfaces with testing unit  220  through a testing connector  222  the comprising a plurality of testing contacts  224 , shown here as pins. The testing contacts  224  of the testing connector  220  connect with the testing sockets of testing connector  226  of wafer-interposer assembly  10 . 
     After electrical connection to the testing unit  220 , wafer-interposer assembly  10  can be used to run chips  36  and  38  (see FIG. 1) on wafers  22  and  24  through any number of tests including a complete parametric test, a burn-on or whatever subsets thereof are deemed necessary for that particular chip design. During the course of testing, signals may be sent to chips  36  and  38  to test each function of the chips which may ideally occur across a range of conditions, so as to simulate real world operation. Testing unit  220  may incorporate a heating and cooling apparatus for testing the chips across a range of temperatures. Testing unit  220  may also incorporate a device for vibrating or otherwise mechanically stressing chips  36  and  38 . 
     More specifically, wafer-interposer assembly  10  of the present invention may be used to select chips  34  and  38  from each of the wafers  22  and  24  that will be used in a matched set of chips. For example, the testing may include performance tests over a range of temperatures, testing for leakage currents, testing for offset voltages and the like to determine which chips  34  from wafer  22  could be included in a matched set with which chips  38  from wafer  24  to achieve optimum performance. Alternatively, the testing may result in giving chips  34  and  38  of wafers  22  and  24  a grade for speed or other performance characteristics such that chips  34  of a particular grade may be matched with chips  38  of that same grade. Additionally, the testing may result in a non-conformance or mismatch determination wherein certain chips  34  may not be matched with certain chips  38 . Certain chips  34  may alternatively be designated as incompatible with any chips  38 . 
     While FIG. 6 has been described as testing wafer-interposer assembly  10  of FIG. 1 wherein chips  34  and  38  are of the same type, it should be understood by those skilled in the art that the same testing procedures will be followed when the chips of the two wafers are of different types, such as using wafer-interposer assembly  50  of FIG. 2 or wafer-interposer assembly  110  of FIG.  4 . Likewise, it should be understood by those skilled in the art that the same testing procedures will also be followed when more than two wafers are being tested simultaneously, such as when using wafer-interposer assembly  150  of FIG.  5 . 
     Referring next to FIG. 7, wafer-interposer assembly  10  of FIG. 1 is depicted including an array  230  of conductive attachment elements  232  and an array  234  of conductive attachment elements  236 . Array  230  is split into sixteen sections separated by dotted lines. Each of the sections has sixteen conductive attachment elements  232  that correspond to contact pads  28  of array  26  on interposer  12 . Similarly, array  234  of conductive attachment elements  236  is split into sixteen sections separated by dotted lines. Each of the sections have sixteen conductive attachment elements  236  that correspond to contact pads  32  of array  34  on interposer  12 . 
     In the illustrated embodiment, conductive attachment elements  232  and  236  are the same size, shape and material. As such, conductive attachment elements  232  and  236  may be attached to interposer  12  using the same process. It should be noted by those skilled in the art that conductive attachment elements  232  may be a different size, a different shape, a different material or may be attached to interposer  12  using a different process than conductive attachment elements  236  without departing from the present invention. 
     After assembly, conductive attachment elements  232  and  236  will be used to electrically connect and mechanically bond a diced section of wafer-interposer assembly  10 , including a section of interposer  12  and its associated chip  34  or  36  to a substrate as will be explained in more detail below. These permanent electrical and mechanical connections may be achieved using, for example, a heating method such as reflowing or thermal compression. 
     FIG. 8 shows an array  240  of chip assemblies  242  and an array  244  of chip assemblies  246  after singulation of a wafer-interposer assembly of the present invention. Each chip assembly  242  comprises a chip  248 , a section  250  of the interposer and a plurality of conductive attachment elements  252  disposed on conductive contact pads  254  on the exposed surface of chip assemblies  242 . Likewise, each chip assembly  246  comprises a chip  256 , a section  258  of the interposer and a plurality of conductive attachment elements  260  disposed on conductive contact pads  262  on the exposed surface of chip assemblies  246 . Chip assemblies  242  and  246  may, for example, include chips of the same type, such as those diced from wafer-interposer assembly  10  of FIG. 1, or may contain chips of different types such as those diced from wafer-interposer assembly  50  of FIG.  2 . 
     As best seen in FIG. 9, a chip assembly  242  and a chip assembly  246  may be mounted together on a substrate  264  as a matched set. Substrate  264  has a plurality of conductive layers  266  and dielectric layers  268 . Chip assemblies  242  and  246  are electrically and mechanically attached to contact pads on the surface of substrate  264  through conductive attachment elements  252  and  260 , respectively. Assembled as shown, the diced sections  250  and  258  of the interposer provide electrical connection between chips  248  and  256  and substrate  264 . In certain embodiments, substrate  264  may be a traditional FR4 circuit board. Alternatively, substrate  264  may be composed of a higher grade material such as a ceramic, which is typically used in multichip packages. 
     Turning now to FIG. 10, therein is depicted an array  280  of chip assemblies, including chip assemblies  282 ,  284 ,  286  and  288 , after dicing a wafer-interposer assembly of the present invention. An array  290  of chip assemblies  292  is also depicted. Each chip assembly  282 ,  284 ,  286  and  288  includes a chip, a section of the interposer and a plurality of conductive attachment elements disposed on conductive pads on the exposed surfaces thereof. As illustrated, chip assembly  288  includes a chip  294 , a section  296  of the interposer and a plurality of conductive attachment elements  298  disposed on conductive pads  300 . Chip assembly  292  includes a chip  302 , a section  304  of the interposer and a plurality of conductive attachment elements  306  disposed on conductive pads  308 . In the illustrated embodiment, chip assemblies  282 ,  284 ,  286  and  288  contain chips of different type than chip assembly  292  such as those diced from wafer-interposer assembly  110  of FIG.  4 . For example, chip assemblies  282 ,  284 ,  286  and  288  may be amplifiers while chip assembly  292  may be a controller. 
     As best seen in FIG. 11, a matched set of components may be mounted on a substrate  310  that has a plurality of conductive layers  312  and dielectric layers  314 . Specifically, chip assemblies  282 ,  284 ,  286  and  288  may be mounted together on a substrate  310  with chip assembly  292 . Chip assemblies  282 ,  284 ,  286  and  288  are electrically and mechanically attached to contact pads on the surface of substrate  310  through conductive attachment elements  298 . Likewise, chip assembly  292  is electrically and mechanically attached to contact pads on the surface of substrate  310  through conductive attachment elements  306 . Assembled as shown, the diced sections of the interposer provide electrical connection between substrate  310  and chips  294  of chip assemblies  282 ,  284 ,  286  and  288  and chip  302  of chip assembly  292 . 
     While FIGS. 9 and 11 have depicted the matched sets of component as including two chip assemblies and five chip assemblies, respectively, it should be understood by those skilled in the art that any number of chip assemblies may be utilized in such a matched set. The specific number of chip assemblies will be selected based upon the desired functionality of the matched set. The testing process of the present invention provides for each of the components of a matched set, regardless of the number, to be tested together as part of a single wafer-interposer assembly. As such, the components for matched set are selected to be assembled together only after successful testing. 
     While this invention has been described in reference to illustrative embodiments, this description is not, intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.