Abstract:
An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from Indian patent application No. 3539/Del/2005, filed Dec. 30, 2005, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     An embodiment of the invention relates to a low-voltage-to-high-voltage-level converter for digital signals and an integrated circuit comprising the same.  
       BACKGROUND  
       [0003]     Advancements in semiconductor fabrication and manufacturing techniques have led to reduction in operating voltage levels. One of the main reasons for using lower operating voltage levels is to reduce the power consumption in semiconductor chips.  
         [0004]     But in cases where a chip is interfaced with a bus operator according to a standard based on higher voltage levels, typically only the main bulk (core) of the chip is operated at a lower voltage level and its I/O interface is operated at higher voltage levels. In order to implement such a scheme, the chip translates high-voltage I/O signals to low-voltage core signals and low-voltage core signals to high-voltage I/O signals. A problem while translating low-voltage core signals to high-voltage I/O signals is of D.C. current. If a low-voltage signal is used to drive a device operating at higher voltage, it may cause the device to draw D.C. power, since it is neither fully off nor fully on.  
         [0005]     Thus circuitry for translating voltage signals which can minimize D.C. current problems may be used. Also in this present technology, the core is typically manufactured at nanometer technology, which operates at approximately 1.0V. However, most I/O blocks are still operating at 3.3V. So to interface between the I/O blocks and the core a voltage translator that can operate with minimum power dissipation is typically used. Also, often high-speed I/O standards such as LVDS, HSTL etc. are supported to operate at clock speeds of 250 MHz or more and hence voltage translators must satisfy such high frequency requirements in these situations.  FIG. 1  shows one such conventionally used translating circuitry. In this circuit, cross-coupled gates use regenerative feedback to quickly pull the output signal to full voltage.  
         [0006]     A detailed description of the prior art circuitry shown in  FIG. 1  is in U.S. Pat. No. 5,422,523, which is incorporated by reference. The circuitry of  FIG. 1  is the embodiment shown in  FIG. 6  of the referred patent. The output of inverter LV, working at low voltage (VDDL), is connected to the gate of NMOS  103 . Consider the case when IN goes from 0 volts to VDDL, where VDDL is the core voltage which is to be converted to VDDH (I/O Voltage), NMOS  104  is ON which reduces the voltage at line  206 . This makes PMOS  101  ON and the voltage at OUT is increased. The output of LV is 0 volts which makes NMOS  103  OFF. An increase in the voltage at OUT makes PMOS  102  less conducting, which further decreases voltage at  206 . This cycle is repeated until the voltage at OUT rises to VDDH.  
         [0007]     Similarly, when IN goes from VDDL to 0 volts, NMOS  104  goes OFF and NMOS  103  becomes ON, to pull down OUT. Reduction in voltage at OUT makes PMOS  102  slightly ON which in turn increases voltage at line  206 . This decreases the conductivity of PMOS  101  leading to further reduction in voltage at OUT. This recursive feedback ultimately makes OUT equal to 0 volts.  
         [0008]     This translator circuitry gives good results when the voltage difference between VDDH and VDDL is small, but starts malfunctioning and even fails completely when the difference between higher and lower supply voltages is large. For example  FIG. 2  shows the simulation results of the prior art circuitry, for higher supply voltage VCC equal to 3.6V and lower supply voltage equal to 0.8V. In the figure output OUT of translating circuitry is shown for five different operating conditions (mentioned in  FIG. 2  itself).  
         [0009]     It can be seen that for case. 1  (typical process corners), case. 3  (fast process corners) and case. 5  (nmos fast, pmos slow process corners) the output is acceptable but for case. 4  (nmos slow and pos fast process corner) it gets distorted and for case. 2  (both nmos and pmos slow process corners) there is no output (constant low).  
         [0010]     A reason theorized for the failure of the circuit is the cross-coupled gates using regenerative feedbacks. In this circuit of  FIG. 1 , switching is initialized by the input signal IN and finally controlled and concluded by regenerative feedback. Switching initialization by the input IN typically has to endure long enough to ensure some threshold voltage reached at the nodes OUT and Net  206 , before switching is handed over to regenerative feedback. If the initialization process is weak, then the translator may switch late or will not switch and the output ‘OUT’ will get distorted or stuck to one state (high or low).  
         [0011]     The transition times and rise-rise and fall-fall delays may become worse when the difference between lower and higher supply is large say 0.8V to 3.6V. The situation of having a large difference between higher and lower supply voltages frequently arises in case of FPGAs because FPGAs are frequently used for various applications and are therefore interfaced with various devices operating at varied bus standards. Due to vast and diverse field of applications of FPGAs, it is often desirable to have their I/O interface circuits capable of being programmed to operate at various voltage levels. Here I/O operating voltage levels may range from 3.6 V to 1.1 V. On the other hand the main bulk (core) operating voltage can be as low as 0.8 V.  
         [0012]     To overcome these problems, US 2005/0162209 A1, which is incorporated by reference, describes a high-speed voltage translator shown in  FIG. 3 . However, the described translator may result in static power dissipation as all devices in the serial path of components  36 ,  42 ,  70  and  66 , or the serial path of components  40 ,  44 ,  54  and  56  may be ON under certain conditions, resulting static power loss. Also the translator uses many PMOS devices, resulting in a larger silicon area.  
         [0013]     In reference to the above problems, there is a need for a voltage translator that can translate a low core voltage (as low as 0.8V or lower) to a higher I/O voltage (from 1.V to 3.6V or higher) with improved transtition times and delays and with reduced dissipation of static power.  
       SUMMARY  
       [0014]     An embodiment of the invention is a low-voltage to high-voltage level translator.  
         [0015]     Another embodiment of the invention is a voltage translator circuit that does not require feedback.  
         [0016]     Yet another embodiment of the invention is a voltage translator that provides rapid translation of signals from low to high voltage levels.  
         [0017]     An embodiment of the invention is a low-voltage-to-high-voltage level translator comprising:  
         [0018]     a first switching element having its control input connected to an input signal and its input terminal connected to a common terminal of a power supply,  
         [0019]     a low-voltage inverting element having its input connected to the input signal,  
         [0020]     a second switching element having its control input connected to the output of said low-voltage inverting element and its input terminal connected to the common terminal of the power supply,  
         [0021]     a complementary switching element having its output connected to the output of said second switching element and its input terminal connected to a high-voltage power supply,  
         [0022]     a complementary biasing element having its input connected to the high-voltage power supply and its output connected to the control terminal of said complementary switching element,  
         [0023]     a first high-voltage inverting element having its input connected to the output of said second switching element,  
         [0024]     a second high-voltage switching element having its input connected to the output of said first high-voltage switching element and its output available as the final output, and  
         [0025]     a third switching element having its control terminal connected to the output of said first high-voltage inverting element, its input connected to the output of said first switching element and its output connected to the output of said complementary biasing element.  
         [0026]     Further, another embodiment of the invention is a low-voltage-to-high-voltage-level translator comprising:  
         [0027]     a first switching element having its control input connected to an input signal,  
         [0028]     a low-voltage inverting element having its input connected to the input signal,  
         [0029]     a second switching element having its control input connected to the output of said low-voltage inverting element and its input terminal connected to a common terminal of a power supply,  
         [0030]     a complementary switching element having its output connected to the output of said second switching element and its input terminal connected to a high-voltage power supply,  
         [0031]     a complementary biasing element having its input connected to the high-voltage power supply and its output connected to the control terminal of said complementary switching element and the output of said first switching element,  
         [0032]     a first high-voltage inverting element having its input connected to the output of said second switching element,  
         [0033]     a second high-voltage switching element having its input connected to the output of said first high-voltage switching element and its output available as the final output, and  
         [0034]     a third switching element having its control terminal connected to the output of said first high-voltage inverting element, its input connected to the common terminal of the power supply and its output connected to the input of said first switching element.  
         [0035]     An a related embodiment, a second complementary switching element is provided having its control terminal connected to the output of said first high-voltage inverting element, its output connected to the output of said second switching element and its input terminal connected to the high-voltage power supply.  
         [0036]     An embodiment of the present invention is a low-to-high-level-voltage translator that translates the low voltage of the core into a high voltage of the I/O blocks. This translator is useful where the difference between the core and I/O supply voltages is very high, e.g., the core is working at 0.8V and the I/O block is working at 3.6V or higher. Unlike the prior art, the translating circuitry according to an embodiment of the invention does not use cross-coupled gates using regenerative feedback for translating voltages, and it does not have static current problems.  
         [0037]     An embodiment of the present invention also provides improved transition times and delays and can also operate at high frequencies.  
         [0038]     A single proposed circuit with proper sizing can be used for translating 0.8V to 1.2V, 0.8V to 1.5V, 0.8V to 1.8V, 0.8V to 2.5V, or 0.8V to 3.6V or higher according to an embodiment of the invention.  
         [0039]     The same circuit can also provide in-between voltage translation such as from 1.8V to 3.3V, from 1.5V to 2.5V, etc. according to an embodiment of the invention  
         [0040]     Since an embodiment of the proposed circuit does not need feedback during transition, the hardware used in the circuit (total size of PMOS and NMOS) may be less as compared to the prior art. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0041]      FIG. 1  is a schematic diagram of a prior-art voltage-level converter.  
         [0042]      FIG. 2  is a plot of the simulation results of the prior-art circuit of  FIG. 1  under different operating conditions for voltage translation of 0.8V to 3.6V.  
         [0043]      FIG. 3  is a schematic diagram of another prior-art voltage-level translator.  
         [0044]      FIG. 4  is a schematic diagram of a voltage-level converter in accordance with an embodiment of the present invention.  
         [0045]      FIG. 5  is a schematic diagram of a voltage-level converter in accordance with another embodiment of the present invention.  
         [0046]      FIG. 6  is a plot of simulation results for an embodiment of the present invention in different operating conditions for a 0.8V to 3.6V translation.  
         [0047]      FIG. 7  is a schematic diagram of a voltage-level converter in accordance with yet another embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0048]     An embodiment of a proposed circuit shown in  FIG. 4  comprises PMOS transistors P 98  and P 99 . The circuit also comprises NMOSs transistors N 70 , N 71 , and N 72  and three inverters, LV working at the lower power supply, and HV 1  and HV 2  working at the higher supply VDDH. The gate and the drain of P 98  are connected to NET 24 . The source of P 98  is connected to VDDH. The drain and source of P 99  are connected to NET 25  and VDDH respectively. The gate of P 99  is connected to NET 24 . The gate of N 70  is connected to Z and the source and drain of N 70  are connected to NET 26  and NET 24  respectively. The gate of N 71  is connected to IN and the source and drain of N 71  are connected to GND and NET 26  respectively. The input of LV is also connected to IN and the output of LV is connected to the gate of N 72 . The source and drain of N 72  are connected to GND and NET 25  respectively. The input and output of HV 1  are connected to NET 25  and Z respectively. The input and output of HV 2  are connected to Z and OUT respectively.  
         [0049]     Operation of the proposed circuit is to translate the lower-voltage logic level to the corresponding higher-voltage logic level. The proposed circuit can be easily understood by considering an example. Considering that circuit is to translate a signal of 1V to 3.3V. First of all considering IN=0V and OUT=0V. At this point N 71  is OFF as its gate is connected to IN and as OUT=0V, node Z is at 3.3V. This makes N 70  ON and the voltage at NET 24  is VDDH-VT(P 98 ), where VT(P 98 ) is the threshold voltage of P 98 . This weakly turns ON P 99 . The output of inverter LV is 1V as its input is connected to IN (0V). This makes N 72  ON and as N 72  is completely ON and P 99  is weakly ON, NET 25  is pulled down to logic low. The size of P 99  is small, therefore as N 72  becomes ON and NET 25  is pulled down to logic LOW. The trip point of HVI is adjusted at the center point of the swing at NET 25 . This keeps rise and fall delays equal. and similarly the trip point of HV 2  is at 0.5*VDDH.  
         [0050]     Now considering the case where input switches from 0v to 1V, N 71  is turned ON and N 72  is turned OFF. As N 71  becomes ON and also N 70  is conducting, both N 70  and N 71  pull down NET 24 . This makes P 99  more strongly ON (earlier Vsg of P 99  was only VT(P 98 )) and also the gate voltage of N 72  is 0V. This turns N 72  OFF and P 99  pulls up NET 25 . As the voltage at NET 25  crosses the trip point of HV 1 , voltage at Z becomes 0V and makes OUT 3.3V. As Z becomes OV this makes N 70  OFF and the voltage at NET 24  again reaches to VDDH-VT(P 98 ). As N 72  is OFF and P 99  is weakly ON, NET 25  is pulled to VDDH. There is no direct path between VDDH and GND therefore no power dissipation under stable condition IN=1.0V, OUT=3.6V.  
         [0051]     Considering now the transition at IN from 1.0V to 0V. N 71  is turned OFF and this does not affect the voltage at NET 24  since N 70  is already OFF. With voltage transition at IN, N 72  is turned ON and P 99  starts conducting weakly. Hence, NET 25  is pulled down and as the voltage at NET 25  crosses the threshold of HV 1 , the voltage at Z becomes 3.3V making OUT 0V. As Z becomes 3.3V N 70  is turned ON but no current flows through it as N 71  is OFF. There is a small amount of current flow through P 99  as it is weakly ON. The proposed circuit works very well for translating low voltages to higher voltages under all operating conditions because there is no feedback operation during the transition. The proposed circuit also works well for configurable I/O blocks where VDDH changes depending upon the standard supported.  
         [0052]      FIG. 5  shows another embodiment of the invention where the position of the switch transistor N 70  is changed. The drain of N 70  is connected to the source of N 71  while its source is grounded. The gate of N 70  is connected to net Z. The operation of this circuit is the same as the operation of the circuit of  FIG. 4 .  
         [0053]      FIG. 6  is a plot of simulation results for the circuit of  FIG. 4 . The various output waveforms shown under different process corners give valid and acceptable output. Also the transition times and propagation delays, i.e., delays between the input and the output, are also improved as compared to the prior art.  
         [0054]     Thus, an embodiment of the present invention provides a CMOS voltage translator that can translate a lower core voltage, say 0.8V, to a higher IO voltage, say 3.6V, with reduced static power dissipation and reduced hardware as compared to the prior art. This circuit also provides improved transition times and propagation delays.  
         [0055]     Although an embodiment of the present invention is described in reference to FPGAs for translating low-to-high-voltage-swing signals where the voltage difference is large, it may apply to other applications in CMOS ICs where low-to-high voltage-level translation is required. Those of ordinary skill in the art will appreciate that various combinations and arrangements may be employed without departing from the scope of the invention.  
         [0056]      FIG. 7  describes yet another embodiment of the present invention wherein a pmos P 100  is added. P 100  is connected between VDDH and NET 25 . The gate of P 100  is connected to node Z. P 100  is a very weak driver, and its purpose is to maintain the logic level at NET 25 . Consider a stable condition when IN is at logic  1 . This makes NET 25  VDDH while NET 24  remains at VDDH-VT(P 98 ). If there is no P 100  and the voltage at IN remains at logic  1  for a long time, then there is possibility that NET 24  reaches to VDDH. This will result in P 99  being OFF. Hence, NET 25  is left floating and a switching line (not shown in  FIG. 7 ) in the vicinity of NET 25  may generate noise on this line. If the noise is generated in such a direction that it decreases the voltage at NET 25  to such an extant that HVI toggles, this will make Z VDDH. As soon as the voltage at Z starts increasing, N 70  is ON and again pulls down NET 24 , and the connect logic level is restored. During this logic restoration there is a possibility that a spike may be transmitted at the output. To reduce the possibility of this error, P 100  may be connected between VDDH and NET 25 . Initially as IN switches from 0 to 1V, NET 25  becomes logic  1  and voltage at Z becomes 0, and hence P 100  is turned ON. Hence, while IN remains at logic  1 , P 100  drives NET 25  and maintains the proper logic level  1  at OUT. The drive strength of P 100 , alongwith N 72  and P 99 , decides the fall delay (OUT=1→OUT=0) of the circuit.  
         [0057]     One or more of the circuits of  FIGS. 4, 5 , and  7  may be incorporated in an integrated circuit (IC) such as an FPGA, and the IC may be incorporated into an electronic system such as a computer system.  
         [0058]     It is believed that embodiments of the present invention and many of their attendant advantages will be understood by the foregoing description. It is also believed that it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages.