Abstract:
A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V OUT  that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V OUT  signal for providing an error free true data output signal VTO.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates in general to amplitude detection circuits and, more particularly, to a differential amplitude detection circuit with DC offset rejection. 
     In many electronic systems it is often necessary to accurately measure the amplitude of a signal. The amplitude information can be used in many ways. One such way is to regulate a control loop. In regulating control loops, accuracy and common mode rejection are critical, and differential amplitude detection techniques are used. But even with differential techniques, there can be other contributing cources of error. For instance, when circuits are AC coupled and the signal passing between them is unbalanced, a differential offset voltage can be accumulated in the signal. The offset voltage is a result of the unbalanced signal spending more time, on the average, in one level than in the other level. 
     In data comunications systems a transmission line to is typically coupled to a receiver with an isolation transformer for isolation purposes. In some coding techniques where the data transmission signal spends more time in one state than another, the isolation transformer develops a saturation current that creates a DC offset at the receiver on the secondary side of the isolation transformer. If the data signal is high more than it is low, the DC offset creates a differential signal error. In the past, when offset errors were of concern in system performance, attempts were made to alter the structure of the transmitted code. The transmitted coding scheme was designed such that the time data resided in a high state was matched to the time data resides in the low state. Thus the system transmission bandwith had to be increased to accommodate the coding overhead. Therefore, prior art attempts at amplitude detection circuits lack features for compensation of offset errors. 
     Therefore, the detector cannot distinguish between the differential data signal and the differential offset signal. 
     Hence, a need exists to eliminate differential offset from the differential data signal on the received side of a transmission line. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The sole FIGURE illustrates a differential amplitude detection circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to the sole FIGURE, a differential amplitude detection circuit 10 receives signals V IN+   and V IN- . The V IN+   and V IN-  signals are single-ended components of the received differential signal. The V IN+   signal is applied to an input of peak detector circuit 12. Peak detector circuit 12 provides a peak signal V PEAK+   of the V IN+   signal at its output. A holding capacitor 14 is coupled between the output of peak detector circuit 12 at node 15 and power supply conductor 16 operating at ground potential. Current load circuit 18 sinks current I LOAD  from node 15 into power supply conductor 16. The V PEAK+   signal is applied to a non-inverting input of buffer amplifier 20. Buffer amplifier 20 is configured as a voltage follower with the output of buffer amplifier 20 coupled to its inverting input. The output of buffer amplifier 20 is coupled through resistor 22 to output node 24. The V IN-   signal is applied to an input of peak detector circuit 26 that provides a peak signal V PEAK-    of the V IN-  signal at its output. Holding capacitor 28 is coupled between the output of peak detector circuit 26 at node 29 and power supply conductor 16. Current load circuit 30 sinks current I LOAD   from node 29 into power supply conductor 16. The V PEAK-   signal is applied to a non-inverting input of buffer amplifier 32 operating as a voltage follower with its the output of buffer amplifier 32 coupled to its inverting input. The output of buffer amplifier 32 is coupled through resistor 34 to output node 24. Summing circuit 21 includes buffer amplifiers 20 and 32, resistors 22 and 34, and output node 24. 
     The inputs of peak detector circuits 12 and 26 are coupled together through resistors 36 and 38, respectively. Node 37 at the interconnection of resistors 36 and 38 is coupled to a non-inverting input of buffer amplifier 40 that is configured as a voltage follower with its output coupled to its inverting input. The output of buffer amplifier 40 provides the common mode voltage component V CM  of the V IN+   and V IN-   signals at node 23. 
     Subtraction circuit 50 includes amplifier 52 and resistors 54, 56, 58, and 60. Resistor 54 is coupled between node 23 and node 55. The output of amplifier 52 is coupled to resistor 58 at node 62. The signal V TO  appearing at node 62 is the true representation of the differential data input signal of differential amplitude detection circuit 10. V TO  is the resultant signal that excludes the offset error voltage and the common mode component of the differential input voltage. The output of amplifier 52 is fedback through resistor 58 to the negative input node 55 of amplifier 52. The negative input of amplifier 52 is also coupled through resistor 54 to the output V CM  of buffer amplifier 40 at node 23. The positive input of amplifier 52 and resistor 60 are coupled to node 57. Resistor 60 is further coupled to power supply conductor 16. The output V OUT  at node 24 is coupled through resistor 56 to the positive input of amplifier 52. 
     The operation of differential amplitude detection circuit 10 proceeds as follows. Peak detector circuit 12 is coupled for receiving the V IN+  signal. The V IN+   signal is the positive single-ended component of the differential input signal. The V IN+   signal is the sum of the common mode input signal, the incoming data signal and the corresponding offset signal. The V PEAK+   signal from peak detector circuit 12 is stored on holding capacitor 14. The addition of current load circuit 18 allows V PEAK+   to track any decreasing offset component contained in the V IN+   signal. Current load circuit 18 can be a constant current source, a variable current source, or a resistor. Buffer amplifier 32 provides buffering of the V PEAK+   signal from additional loading through resistor 22. 
     Peak detector circuit 26 is coupled for receiving the V IN-   signal. The V IN-   signal is the sum of the common mode input signal, the incoming data signal and the corresponding offset signal. The V PEAK-  signal from peak detector circuit 26 is stored on holding capacitor 28. The addition of current load circuit 30 allows V PEAK-   to track any decreasing offset component contained in the V IN-   signal. Current load circuit 30 can be a constant current source, a variable current source, or a resistor. Buffer amplifier 20 provides buffering of the V PEAK-   signal from additional loading through resistor 34. 
     Summing circuit 21 includes buffer amplifiers 20 and 32, and resistors 22 and 34. The output signals of buffer amplifiers 20 and 32 are added through resistors 22 and 34 respectively to produce signal V OUT  at output node 24. V OUT  is the output of summing circuit 21. 
     The input signals V IN+   and V IN-   to differential amplitude detection circuit 10 are added through resistors 36 and 38, respectively. The resulting signal is buffered through buffer amplifier 40 to produce signal V CM  at node 23. V CM  is the resulting common mode component signal of the inputs V IN+   and V IN- . 
     As a feature of the present invention, the offset component of V PEAK+  is equal and opposite in polarity to the offset component appearing in V PEAK- . Therefore, when the output of buffer amplifier 20 is added to the output of buffer amplifier 32, the offset components of V IN+   and V IN-    are canceled at output node 24 V OUT . However, the resulting signal V OUT  also contains the original component of common mode voltage. 
     The component of common mode voltage can be eliminated from V OUT  by subtracting the signal appearing at V CM  from the signal appearing at V OUT . The resultant V TO  signal contains only the desired signal amplitude of the original data input signal. 
     The operation of differential amplitude detection circuit 10 of the sole figure can also be expressed mathematically as follows. The V IN+   and V IN-   signals can be represented as: 
     
         V.sub.IN+ =V.sub.CM +V.sub.SIGNAL -V.sub.OFFSET            (1) 
    
     
         V.sub.IN- =V.sub.CM -V.sub.SIGNAL +V.sub.OFFSET            (2) 
    
     where: 
     V CM  is the common mode component of the received signal; 
     V SIGNAL  is the true data portion of the received signal; and 
     V OFFSET  is the offset error portion of the received signal. 
     V OFFSET  is the error voltage caused by transmission coding techniques, transmission media, and receiving coupling media. 
     In the sole FIGURE, V PEAK+   and V PEAK-   can be described by the equations: 
     
         V.sub.PEAK+ =Peak (V.sub.CM +V.sub.SIGNAL -V.sub.OFFSET)   (3) 
    
     
         V.sub.PEAK- =Peak (V.sub.CM -V.sub.SIGNAL +V.sub.OFFSET)   (4) 
    
     where: 
     the Peak () function determines the peak values of V IN+   and V IN- . 
     Summing circuit 21 operates on V PEAK+   and V PEAK-   as follows: 
     
         V.sub.OUT =(V.sub.PEAK+ +V.sub.PEAK-)/2                    (5) 
    
     Substituting equations (3) and (4) into equation (5) yields 
     
         V.sub.OUT =(Peak (V.sub.CM +V.sub.SIGNAL -V.sub.OFFSET)+Peak (V.sub.CM -V.sub.SIGNAL +V.sub.OFFSET))/2                           (6) 
    
     and further reducing equation (6) yields 
     
         V.sub.OUT =V.sub.CM +Peak (V.sub.SIGNAL)                   (7) 
    
     The common mode component signal V CM  of V OUT  can be removed with subtraction circuit 50. In subtraction circuit 50, the common mode component of the differential input signal is applied to the negative input of amplifier 52 at node 55. The output signal V OUT  at node 24, which is the sum of the true data signal and the common mode component of the differential signal, supplied to the positive input of amplifier 52 at node 57. The feedback configuration of resistors 54, 56, 58, and 60 is arranged such that the V CM  signal at node 23 is subtracted from V OUT , thus providing an accurate representation of the originally transmitted data signal at node 62. As can be seen from equation (7), the offset error voltage has been eliminated by differential amplitude detection circuit 10. 
     To provide complete cancellation of the offset voltage error at V OUT , the change in voltage with respect to time of current load circuit 18 in conjunction with holding capacitor 14 and the change in voltage with respect to time of current load circuit 30 in conjunction with holding capacitor 28, must equal to or exceed change in offset voltage with respect to time of the differential input signal. In addition, peak detector circuit 12 and peak detector circuit 26 must be chosen such that the respective peak detector circuits 12 and 26 have adequate bandwidth to track the input differential signal. Matching of holding capacitors 14 and 28, current load circuits 18 and 30, resistors 36 and 38, and resistors 22 and 34 respectively, further serves to enhance the offset elimination feature in differential amplitude detection circuit 10. 
     By now it can be appreciated that the present invention provides a circuit and method for eliminating differential offset errors from differential data signals received from a transmission line. The single-ended positive and negative components of the differential data signal are channeled through parallel peak detection paths. The outputs of the peak detectors are furnished with current loads that inhibit an accumulation of voltage at the peak detector output and thus provide an accurate representation of the detected peak voltages. The detected peak voltages are input into a summing circuit that cancels the offset components caused by data transmission media effects. 
     As another advantage of the present invention a circuit is provided to separate the common mode component of the differential signal from the differential signal. The common mode component can then be subtracted from the summed peak voltage signals to provide an error free replica of the originally transmitted data signal. 
     While specific embodiments of the present invention have been shown and described, further modifications and improvements will occur to those skilled in the art. It is understood that the invention is not limited to the particular forms shown and it is intended for the appended claims to cover all modifications which do not depart from the spirit and scope of this invention.