Abstract:
The invention relates to methods and apparatus for demodulating a differentially phase-modulated digital input signal to produce an output signal representing the digital signal corresponding to the transmitted message. 
     The process comprises memorizing the last two digital samples of the input signal received, computing the series of digital sample phases of the input signal, before and after the last change of the input signal&#39;s initial phase, and then substituting for the difference between two phases having the same order number, the corresponding group of output signal bits. 
     Applicable in differentially phase-modulated signal transmission systems.

Description:
TECHNICAL FIELD 
     The present invention relates to method and apparatus for demodulating a differentially phase-modulated digital input signal to obtain an output signal representing the digital data corresponding to the transmitted message. When associated with an analogue-to-digital converter, the invention may also be used to demodulate a differentially phase-modulated analogue signal. 
     BACKGROUND OF THE INVENTION 
     Differential phase-modulation is widely employed to transmit both digital and digitally-encoded analog signals over transmission facilities such as microwave and co-oxial cable. 
     Heretofore, the circuity required to demodulate such signals at the receiving location was complex and expensive. 
     SUMMARY OF THE INVENTION 
     It is thus an object of this invention to provide methods and apparatus for demodulating a differentially phase-modulated digital signal that overcomes the above and other problems. 
     The invention thus comprises a method for demodulating a differentially phase-modulated digital input signal y, comprising a stream of digital samples y j  (n), y k  (n) and y l  (n) representative of sinusoidal signals priorly sampled at frequency F and encoded for example as signals x j , x k  and x l  of frequency f, said samples succeeding each other in time upon each change of the initial phase of an analogue signal x representing the signal y before sampling and encoding, said method demodulating said input signal y to produce an output signal z representing the significant digital value of the transmitted message, characterized by the steps of: 
     (a) memorizing the last two received digital samples y k  (1) and y k  (2) of the input signal y; 
     (b) generating the series u(n) of digital samples of the series y k  (n) from the two digital samples y k  (1) and y k  (2); 
     (c) calculating the series s(n) of the phases of the x k  sinusoidal signal digital samples of initial phase φ k , from the series u(n) of digital samples of the sinusoidal signal x k  ; 
     (d) comparing each digital sample y(n+i) of the input signal y with the digital sample of the same order u(n+i) of the series u(n) and then; 
     (e) (α) if u(n+i) differs from y(n+i), or if y(n+i) is equal to y l  (1): 
     generating the series v(n) of digital samples of series y l  (n) from the two digital samples y l  (1) and y l  (2), while continuing to produce the series u(n) of the digital samples of the series y k  (n); 
     comparing each digital sample of signal y with the digital sample of the same order of the series v(n); 
     computing the series t(n) of digital sample phases of the sinusoidal signal x l  of initial phase φ l  from the series v(n) of the digital samples of sinusoidal signal x l  ; 
     computing the phase difference φ l  -φ k  between (a) each term of the series t(n) of digital sample phases of the sinusoidal signal x l  and (b) the term having the same order number in the series of digital sample phases of the sinusoidal signal x k  ; 
     substituting for the phase difference φ l  -φ k  a group of bits of the output signal z selected to represent the phase difference φ l  -φ k  in accordance with a pre-established law of correspondence; or 
     (β) if u(n+i) is equal to y(n+i), or if y(n+i) is equal to y k  (n+i): 
     computing the phase difference φ k  -φ j  between (a) each term of the series s(n) of digital sample phases of the sinusoidal signal x k  and (b) the term having the same order number of the series t(n) of digital sample phases of the sinusoidal signal x j  ; 
     substituting for the phase difference φ k  -φ j  a group of bits of output signal z selected to represent the phase difference φ k  -φ j  in accordance with the said pre-established law of correspondence. 
     The present invention also discloses illustrative apparatus for implementing the method defined above. 
     The operation of the present invention will be more fully understood from the following description when taken with the appended drawings, in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an illustrative demodulation device in accordance with the invention; 
     FIG. 2 is a block diagram of the first generator which is used in the demodulation device shown in FIG. 1; and 
     FIG. 3 is a block diagram of the first computing device which is used in the demodulation device shown in FIG. 1. 
     FIG. 4 is an example of wave forms of signals y, u and v defined at FIG. 1. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, it is seen that the differentially phase-modulated input signal y is applied to the input terminal of a first memory circuit 2. The input signal y consists of a series of digital samples such as y j  (n), y k  (n) and y l  (n), representative of sinusoidal signals sampled at frequency F and encoded, such as x j , x k  and x l , of frequency f, following each other in time at each change of initial phase of an analogue signal x representing signal y before sampling and encoding. The output terminal of first memory circuit 2 is connected to the input terminal of a second memory circuit 3. These two memories have sufficient capacity to the last two digital samples of the input signal y and are used to initialize either a first generator 4 or a second generator 5 by means of the two digital samples. In a preferred embodiment, the memories 2 and 3 each comprise a shift register. 
     If the first generator 4 has been initialized by means of the two digital samples of order number 1 and 2 of the series y k  (n), i.e. y k  (1) and y k  (2), this generator produces the series u(n) of the digital samples of sinusoidal signal x k  from the two digital samples x k  (1) and y k  (2). The digital samples of the series u(n) are fed to a first computing device 6 which calculates the series s(n) of the digital sample phases of sinusoidal signal x k  from the series u(n) of the digital samples of sinusoidal signal x k . 
     The digital samples of the series u(n) are also fed to a comparison device 7 via a first switching device 8. 
     The comparison device of 7 compares each digital sample u(n+i) of the series u(n) with the digital sample y(n+i) having the same order number of the input signal y. 
     The comparison result appears in the form of three order signals C 1 , C 2  and C 3 , controlling the first switching device 8, initialization of the first generator 4 and initialization of the second generator 5, respectively. 
     If u(n+i) differs from y(n+i), or again if y(n+i) is equal to y l  (1), signal C 3  orders initialization of the second generator 5 by means of the two digital samples of order numbers 1 and 2 of the series y l  (n), i.e. y l  (1) and y l  (2). 
     The order signal C 1  of the first switching device 8 thus switches one of the input terminals of the comparison device 7 from the output terminal of the first generator 4 to the output terminal of the second generator 5. 
     The second generator 5 then produces the series y(n) of digital samples of the sinusoidal signal x l  from the two digital samples y l  (1) and y l  (2), the first generator 4 continuing to produce the series u(n) of digital samples of the sinusoidal signal x k . The digital samples of the series v(n) are fed to a second computing device 9 which calculates the series t(n) of the digital sample phases of the sinusoidal signal x l  from the series v(n) of digital samples of the sinusoidal signal x l . 
     A subtracting circuit 10 generates the difference between each term of the series s(n) of the digital sample phases of the sinusoidal signal x k  calculated by the first computing device 6 and the term having the same order number in the series t(n) of the digital sample phases of the sinusoidal signal x l  calculated by the second computing device 9. Since the terms have the same order number, the phase difference is equal to the initial phase difference between the sinusoidal signals x l  and x k , i.e. φ l  -φ k . 
     A substitution circuit 11 substitutes for the phase difference φ l  -φ k  the group of bits of the output signal z selected for representing the phase difference φ l  -φ k  in accordance with the predetermined law of correspondence. 
     An example of &#34;the predetermined low of correspondence&#34; may be the following 
     
         ______________________________________Δφ      Z______________________________________ 0°        0 0 1 45°       0 0 0 90°       0 1 0135°       0 1 1180°       1 1 1225°       1 1 0270°       1 0 0315°       1 0 1______________________________________ where Δφ is the output signal of the substrat device 10 and Z the output signal of the substitution circuit 11. 
    
     The substitution circuit 11 may consist of a read only memory which is programmed so that when it is addressed with the output signal of the substract device 10 (i.e. with the signal Δφ coded in a digital code), it provides the value Z corresponding to the value Δφ according to the predetermined law of correspondance. 
     If u(n+i) is equal to y(n+i), or again if y(n+i) is equal to y k  (n+i), the subtracting circuit 10 generates the phase difference between each term of the series s(n) of the digital sample phases of the sinusoidal signal x k  calculated by the first computing device 6 and the term having the same order number of the series t(n) of the digital sample phases of the sinusoidal signal x j  calculated by the second computing circuit, the second generator having been previously initialized by means of the digital samples y j  (1) and y j  (2) by means of the control signal C 3  in order to produce the series of digital samples of the sinusoidal signal x j . 
     This phase difference is equal to the initial phase difference between the sinusoidal signals x k  and x j , i.e. φ k  -φ j . 
     The substitution circuit 11 substitutes for the phase difference φ k  -φ j   the group of bits selected for representing the difference φ k  -φ j  in accordance with the predetermined law of correspondence. In a preferred embodiment substitution circuit 11 comprises a read-only memory having stored therein the predetermined law of correspondence. 
     Referring now to FIG. 2, it is seen that the first generator circuit 4 comprises two initialization terminals 12 and 13 and an output terminal 14. This generator is simply a recursive digital filter having the following transfer function, expressed in terms of z: ##EQU1## This circuit possesses a first feedback loop connecting output terminal 14 to a first summing circuit 15 via a first delay device 16 connected in series with a first multiplier circuit 17 of coefficient ##EQU2## This circuit possesses a second feedback loop connecting the junction of the delay device 16 and the multiplier circuit 17 to the summing device 15 via a second delay device 18 connected in series with a second multiply device 19 of coefficient -1. The junction between the delay device 16 and the multiply circuit 17 can be switched by means of a second switching device 20 controlled by the order signal initializing the first generator C 2  to the initialization terminal 12 connected to the output terminal of the first memory 2. 
     The junction between the delay device 18 and the multiplier circuit 19 may be switched by means of a third switching circuit 21 controlled by the order signal C 2  to the initialization terminal 13 connected to the output terminal of the second memory circuit 3. Signal C 2  is such that, by means of the switching circuits 20 and 21, the first and second feedback loops open to allow initialization and close once the first generator has been initialized. 
     In a preferred embodiment, the system including delay device 16 and switching circuit 20 comprises a first shift register having two write inputs connected to the initialization terminal 12 and the output terminal 14, respectively; an input for enabling one of the two write inputs (intended for receiving the order signal C 2 ); and an output connected to the multiplier circuit 17. The system including delay device 18 and switching device 21 comprises a second shift register identical with the first, having two write inputs connected to the initialization terminal 13 and the output of the first register, respectively; an input enabling one of the two write inputs (intended for receiving the order signal C 2 ); and an output connected to the multiplier circuit 19. 
     The series u(n) generated by the first generator is a recurrent series defined by the following formula: ##EQU3## 
     It may be easily demonstrated that such a generator can produce the series of digital samples of a sinusoidal signal having an amplitude A, frequency f and initial phase φ, and sampled at frequency F, from two initial values obtained at the sampling instants ##EQU4## 
     By substituting ##EQU5## the following is obtained: 
     
         u(n-1)=A sin [(n-1)θ+φ] 
    
     
         u(n-2)=A sin [(n-2)θ+φ] 
    
     
         u(n)=2 A cos θ·sin [(n-1)θ+φ]-A sin [(n-2)θ+φ] 
    
     
         u(n)=2 A cos θ·[sin (nθ+φ)·cos θ-sin θ·cos (nθ+φ)]-A [sin (nθ+φ)·cos 2θ-sin 2θ·cos (nθ+φ)] 
    
     
         u(n)=A sin (nθ+φ)[2 cos .sup.2 θ-cos 2θ]+A cos (nθ+φ)[sin 2θ-2 sin θcos θ] 
    
     i.e.: 
     
         u(n)=A sin (nθ+φ) 
    
     or again: ##EQU6## It is thus seen that u(n) represents the sample of a sinusoidal signal having an amplitude A, frequency f and initial phase φ, sampled at frequency F at the sampling instant n/F. 
     The second generator 5 is identical with first generator 4 illustrated in FIG. 2, and operates in the same manner by replacing the initialization order signal C 2  with the initialization order signal C 3 . 
     When a difference is detected at the output of the comparison circuit 7, the order signal C 1  of the first switching circuit 8 becomes active, whilst the order signals C 2  and C 3  of the second switching circuit 20 and of the third switching circuit 21 become active, every other time. 
     Referring now to FIG. 3, it is seen that the first computer 6 comprises firstly a non-recursive digital filter 22 possessing an input terminal 23 connected to the output terminal 14 of the first generator and two output terminals 24 and 25, secondly dividing circuit 26 having two input terminals connected to the two output terminals of the digital filter 22, and thirdly a read-only memory circuit 27 addressed on the one hand by the output signal of the dividing circuit 26 and on the other hand by the output signal of a first sign detector 28 and by the output signal of a second sign detector 29. The first sign detector 28 is fed with the signal present on output terminal 24, whilst the second sign detector 29 is fed with the signal present on output terminal 25. 
     The digital filter 22 has the following transfer function, expressed in terms of z: ##EQU7## and including a second adding circuit 30, a third delay circuit 31, a third multiplier circuit 32 of coefficient ##EQU8## and a fourth multiplier circuit 33 of coefficient ##EQU9## In a preferred embodiment, the third delay circuit 31 comprises a third register identical with the first and second shift registers used in the first and second generators. The real and imaginary parts of the output signal of digital filter 22 are obtained on output terminals 24 and 25 of this filter. 
     Let w 1  (n) and w 2  (n) be the series of digital samples produced on output terminals 24 and 25, respectively, of digital filter 22, u(n) representing the series of digital samples fed to input terminal 23. 
     As described above, u(n) appears in the form: 
     
         u(n)=A sin (nθ+φ) 
    
     It is seen from FIG. 3 that: 
     
         w.sub.1 (n)=u(n)-cos θ·u(n-1) 
    
     or again: 
     
         w.sub.1 (n)=A sin (nθ+φ)-cos θ·A sin [(n-1)θ+φ] 
    
     
         w.sub.1 (n)=A sin (nθ+φ)-A cos θ[sin (nθ+φ)·cos θ-sin θ·cos (nθ+φ)] 
    
     
         w.sub.1 (n)=A sin (nθ+φ)(1-cos.sup.2 θ)+A sin θ·cos θ·cos (nθ+φ) 
    
     
         w.sub.1 (n)=A[sin (nθ+φ) sin.sup.2 θ+sin θ·cos θ·cos (nθ+φ)] 
    
     
         w.sub.1 (n)=A sin θ[sin (nθ+φ)·sin θ+cos θ·cos (nθ+φ)] 
    
     
         w.sub.1 (n)=sin θ·A cos [(n-1)θ+φ] 
    
     It is also seen from FIG. 3 that: 
     
         w.sub.2 (n)=sin θ·u(n-1) 
    
     or again: 
     
         w.sub.2 (n)=sin θ·A sin [(n-1)θ+φ] 
    
     The dividing circuit 26 produces a series of digital samples w 3  (n) such that: ##EQU10## 
     Knowing the signs of w 1  (n) and w 2  (n), and the value of w 3  (n), it is possible to deduce the value of the phase (n-1)θ+φ. For this purpose, read-only memory 27 contains a tangent table and is addressed by the output signals of the dividing circuit 26 and the sign detectors 28 and 29. The series of phases s(n) appears on the output of memory 27. 
     The second computing device 9 producing the series of phases t(n), is identical with the first computing device and operates in the same manner. 
     An example of wave forms of signals y, u and v is given at FIG. 4. The signal y consists for example of a succession of three sinusoidal signals sampled and encoded: y j , y k  and y 1 . The difference between the phase of the sinusoidal signal y k  and the phase of the sinusoidal signal y j  has been chosen equal to 45°. The difference between the phase of the sinusoidal signal y 1  and the phase of the sinusoidal signal y k  has been chosen equal to 135°. These values have been chosen among the values of Δφ given in the predetermined law of correspondance. These three sinusoidal signals have same amplitude and same frequency. 
     While the sinusoidal signals y k  and y 1  are present, the generator 4 (for example) provides a signal u which is a sinusoidal signal, sampled and encoded, identical to the sinusoidal signal, encoded and sampled, y j . While the sinusoidal signals y k  and y 1  are present, the generator 5 provides a signal v which is a sinusoidal signal, sampled and encoded, identical to the sinusoidal signal, sampled and encoded y k . 
     Let the signals u (t) and v (t) be written as follows: 
     
         u(t)=A sin (wt+φ) and 
    
     
         v(t)=A sin (wt+φ+Δφ) 
    
     The corresponding signals s (t) and t (t) will then be written 
     
         s(t)=wt+φ and 
    
     
         t(t)=wt+φ+Δφ 
    
     The signals s and t have not been represented on the diagram but they would be obtained from u (t) and v (t) as follows: 
     
         s(t)=(1/A) Arc sin u(t) and 
    
     
         t(t)=(1/A) Arc sin v(t) 
    
     The signals u (n), v (n), s (n) and t (n) are the signals u (t), v (t), s (t) and t (t) sampled and encoded. 
     The output signal of the substract device 10 has then the value Δφ coded in a digital code. And the signal Z has the digital value corresponding to Δφ in the predetermined law of correspondance. 
     Although the principles of the present invention are described above in relation with practical examples, it should be clearly understood that the said description is given as an example only and does not limit the scope of the present invention.