Abstract:
A CD-ROM reproduction apparatus which allows error correction for both audio data and CD-ROM data using a single error correction circuit with a miniaturized size. The CD-ROM reproduction apparatus comprises, in addition to the single error correction circuit, an error syndrome monitoring circuit to monitor the error syndromes generated upon error correction processing and to detect presence or absence of an error. Depending upon whether error correction is performed for audio data or for CD-ROM data, the internal connection of the error correction circuit is switched so that the error correction circuit performs error correction for audio data or CD-ROM data. Error correction calculation by the error correction circuit is not performed for audio data or CD-ROM data discriminated to include no errors by the error syndrome monitoring circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a CD-ROM reproduction apparatus. 
     2. Description of the Prior Art 
     A CD-ROM (compact disk read only memory) reproduction apparatus conventionally has a general construction as illustrated in FIG. 5. Referring to FIG. 5, a recording signal of a CD-ROM disk 2 is read out by an optical pickup 1 and the signal read from the CD-ROM is transmitted to an audio signal processing section 3, where the signal is first demodulated by EFM demodulation by an EFM demodulation circuit 4 and then stored into an audio data RAM (random access memory) 5. Then, the output signal of the audio data RAM 5 is directed to a de-interleave circuit 6 and an audio data error correction circuit 7, in which C 1  and C 2  errors in the output signal are detected and corrected, and then, the signal is supplied to a CD-ROM signal processing section 8. 
     From the CD-ROM signal processing section 8, the data after correction of the C 1  and C 2  errors is stored into a CD-ROM data RAM 9, and then; P and Q errors in the output signal are detected and corrected by a descrambler 10, a RAM controller 11 and a CD-ROM data error correction circuit 12, and finally the data is sent to an external host computer 14 via an interface 13. The conventional CD-ROM reproduction apparatus further includes a system controller 15 for controlling the operation of the entire system, a spindle motor 16, a CLV control circuit 17, and a focusing and tracking servo circuit 18. 
     The error correction processing of the audio data error correction circuit 7 and the CD-ROM data error correction circuit 12 in the conventional CD-ROM reproduction apparatus will be described below. 
     Audio Data Error Correction 
     Audio data error correction is performed in the error correction circuit 7 using double error correction Reed-Solomon codes of (32, 28) and (28, 24) on GF(2 8 ) called C 1  and C 2 , respectively. 
     First, error syndromes S 0 , S 1 , S 2  and S 3  are calculated in accordance with the following equations: ##EQU1## where n=32 for C 1 , but n=28 for C 2 . 
     Using the above described error syndromes S 0 , S 1 , S 2 , and S 3 , error detectors A, B, and C for the criteria are calculated according to the following equations: 
     
         A=S.sub.0 ·S.sub.2 +S.sub.1.sup.2                 ( 5) 
    
     
         B=S.sub.1 ·S.sub.2 +S.sub.0 ·S.sub.3     ( 6) 
    
     
         C=S.sub.1 ·S.sub.3 +S.sub.2.sup.2                 ( 7) 
    
     Using the error syndromes S 0 , S 1 , S 2 , and S 3  and the error indicators A, B, and C calculated as described above, the number of errors is determined according to the following criteria: 
     A. No error→when S 0  =0, S 3  =0, and A=B=C=0 
     B. Single error→when S 0  ≠0, S 3  ≠0, and A=B=C=0 
     Where the root of the creation polynomial for a Reed-Solomon code is represented by α, the position of the error by i, and the value of the error by ei, 
     
         α.sup.i =S.sub.1 /S.sub.0                            ( 8) 
    
     
         e.sup.i =S.sub.0                                           ( 9) 
    
     where α i  is an exponential representation of the position of the error i, and accordingly, 
     
         i=logα(S.sub.1 /S.sub.0)                             (10) 
    
     C. Double error→when A≠0, B≠0, and C≠0 
     Where the root of the creation polynomials for the Reed-Solomon codes for the two errors is represented by α, the positions of the two errors by i and j and the values of the two errors by ei and ej, 
     
         α.sup.i =D/X                                         (11) 
    
     
         α.sup.j =D/Y                                         (12) 
    
     
         ei=S.sub.0 /Y+S.sub.1 /D                                   (13) 
    
     
         ej=S.sub.0 X+S.sub.1 /D                                    (14) 
    
     where D, E, X, and Y are given by 
     
         D=B/A                                                      (15) 
    
     
         E=C/A                                                      (16) 
    
     
         D.sup.2 /E→X                                        (17) 
    
     
         Y=D.sup.2 /E+X                                             (18) 
    
     Where D 2  /E.X conversion ROM or a like device using a PLA (programmable logic array) of 8 bits is implemented to calculate X. 
     Error correction is thus performed in accordance with the positions and the values of the errors obtained in any case described above. 
     Error Correction of CD-ROM Data 
     Error correction of CD-ROM data is performed by the error correction circuit 12 using P parity and Q parity as shown in FIG. 6 for data of one sector (98 frames) which are each divided into two upper and lower bytes. It is to be noted that P is a (26, 24) Reed-Solomon code on GF(2 8 ) and Q is a (45, 43) Reed-Solomon code on GF(2 8 ). Detection correction of one byte and disappearance correction of 2 bytes can be performed using this P parity and Q parity. 
     A. One Byte Detection Correction 
     Where the root of the creation polynomial for a Reed-Solomon code is represented by α, the syndromes of CD-ROM data by S 0  and S 1  and the position of the error is represented by i and the value of the error by ei, 
     
         α.sup.i =S.sub.1 /S.sub.0                            ( 19) 
    
     
         ei=S.sub.0                                                 ( 20) 
    
     and accordingly, 
     
         i=logα(S.sub.1 /S.sub.0)                             (21) 
    
     B. Two Byte Disappearance Correction 
     Where the root of the creation polynomials for the Reed-Solomon codes for the two errors is represented by α, the positions of the errors known as error pointers are represented by i and j and the values of the errors by ei and ej, 
     
         S.sub.0 ei+ej                                              (22) 
    
     
         S.sub.1 =α.sup.i ei+α.sup.j ej                 (23) 
    
     and accordingly, the values ei and ej of the errors can be obtained by solving the simultaneous equations (22) and (23). 
     In the conventional CD-ROM reproduction apparatus described above, the audio signal processing section 3 and the CD-ROM signal processing section 8 are constructed as separate sections and accordingly the error correction circuit 7 for audio data and the error correction circuit 12 for CD-ROM data are constructed independently of each other, as illustrated in FIG. 5. Consequently, a comparatively large scale circuit is required, and reduction in size of the apparatus is difficult. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a CD-ROM reproduction apparatus which implements error correction for both audio data and CD-ROM data using a single error correction circuit and is minimized in size. 
     In order to attain the object described above, according to the present invention, there is provided a CD-ROM reproduction apparatus, which comprises: a means for reading audio data and CD-ROM data from a CD-ROM, a means for the calculation of error syndromes from the audio data and the CD-ROM data, an error syndrome monitoring means for monitoring the error syndromes to detect presence or absence of an error in the audio data or the CD-ROM data, a single error correction circuit including an audio data error correction function and a CD-ROM data error correction function, a switching means to facilitate the internal selection of the error correction circuit depending upon whether error correction should be performed for the audio data or the CD-ROM data, and a control means disabling calculation of the error criteria by the error calculation circuit for the audio or CD-ROM data when no errors are detected by the error syndrome monitoring means. Preferably, when a request for error correction for the audio data and another request for error correction for the CD-ROM data are inconsistent with each other, the control means causes the error correction circuit to perform error correction for the audio data preferentially. 
     As described above, during the duplication of a CD-ROM disk, error correction for audio data is first performed using C 1  and C 2 , and then error correction for CD-ROM data is performed using P parity and Q parity. The two error correction operations are both performed with Reed-Solomon codes on GF(2 8 ). Accordingly, ROMs for exponent and vector conversion in error correction calculation are the same as each other, and the general calculation flow processes required for decoding are almost identical to each other. 
     Therefore, if a single error correction circuit is implemented and the connections of the internal circuit of the error correction circuit are switched back and forth during the error correction processing between the audio data and the CD-ROM data, in accordance with a required processing flow for audio data or CD-ROM data, then error correction for audio data and CD-ROM data can be performed. The present invention has been made taking advantage of this property. 
     When error correction for audio data CD-ROM data are performed using a single error correction circuit in the manner described above, the signal processing time may possibly be increased because only one error correction circuit is in use. Therefore, according to the present invention, in order to eliminate the potential speed problems, a means of monitoring the error syndromes has been incorporated so that error correction calculation is not performed for audio data or CD-ROM data having no errors. 
     In particular, with the conventional CD-ROM reproduction apparatus described above, A, B and C are calculated after the syndromes S 0  =0 and S 3  =0 are detected, and then presence or absence of an error is discriminated depending on whether A=B=C=0. With the CD-ROM reproduction apparatus according to the new invention, even when audio data or CD-ROM data include no errors, the error correction calculation circuit is still active. However, if S 0  =0, S 3  =0 and A=B=C=0, then S 1  =0 and S 2  =0 must also be the case. Accordingly, if S 0  =S 1  =S 2  =S 3  =0 is confirmed before A, B and C are calculated, no error in data can be discriminated in advance. 
     Therefore, according to the present invention, the means for monitoring the error syndromes is provided to discriminate S 0  =S 1  =S 2  =S 3  =0 so that presence or absence of an error may be detected before the calculation circuit for error correction operates. According to this implementation, the calculation of error correction for data having no error can be eliminated. Consequently, the processing time for error correction is reduced and a high processing rate can be assured while employing the single error correction circuit. 
     Although high rate processing for such error correction is not very important when the data from a CD-ROM is read out at the standard rate (150 Kbytes/sec), it becomes critical when a CD-ROM is read out at a high rate, such as a rate equal to four times the standard rate (600 Kbytes/sec). The CD-ROM reproduction apparatus of the present invention can accommodate such high rates of data output while employing the single error correction circuit, according to the present invention. 
     Further, since error correction for audio data and CD-ROM data can be performed by means of the single error correction circuit, the size of the CD-ROM reproduction apparatus can be reduced. 
     If audio data is not output continuously on the real time basis, by the present invention, then the reproduced sound will be intermittent. Accordingly, when a request for error correction for audio data and CD-ROM data are inconsistent or collide with each other, error correction for audio data is performed preferentially, and thereafter, error correction for CD-ROM data is performed. Accordingly, a smooth error correction processing is realized. 
     The objects, features and advantages of the present invention will be explained by the following description and the attached claims, in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating the basic structure of a CD-ROM reproduction apparatus according to the present invention; 
     FIG. 2 is a block diagram of an error correction circuit employed in the CD-ROM reproduction apparatus of FIG. 1; 
     FIG. 3a and FIG. 3b combine to form a time plot illustrating detection correction operation for CD-ROM data by the error correction circuit of FIG. 2; 
     FIG. 4a and FIG. 4b combine to form a time plot illustrating disappearance correction operation for CD-ROM data by the error correction circuit of FIG. 2; 
     FIG. 5 is a block diagram showing a general construction of a conventional CD-ROM reproduction apparatus; and 
     FIG. 6 is a table showing a format used in an error correction method of a CD-ROM. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring first to FIG. 1, a CD-ROM reproduction apparatus is illustrated incorporating the basic structure of the present invention. Similarly to the conventional CD-ROM reproduction apparatus as described above with reference to FIG. 5, the CD-ROM reproduction apparatus includes an optical pickup 1 for optically reading a CD-ROM disk 2, an audio signal processing section 3, a CD-ROM signal processing section 8, an interface 13 to a host computer 14, a system controller 15, a spindle motor 16, and a focusing and tracking servo circuit 18. The audio signal processing section 3 includes an EFM demodulation circuit 4, audio data RAM (random access memory) 5, a de-interleave circuit 6 and a CLV control circuit 17. The CD-ROM signal processing section 8 includes CD-ROM data RAM 9, a descramble circuit 10 and a RAM controller 11. However, in place of the error correction circuit 7 in the audio signal processing section 3 and the error correction circuit 12 in the CD-ROM signal processing section 8 included in the conventional CD-ROM reproduction apparatus, the CD-ROM reproduction apparatus designed according to the present invention includes a single error correction circuit 19 with an error syndrome monitoring circuit 20 therein. 
     The error syndrome monitoring circuit 20 monitors error syndromes produced by error correction processing to detect presence or absence of an error. The internal connection of the error correction circuit 19 is switched back and forth depending on whether error correction is performed for audio data or for CD-ROM data. When the syndrome monitoring circuit 20 determines that the selected data contains no errors, the error correction circuit 19 performs no error correction operations for the corresponding data. Further, when a request for error correction for audio data and another request for error correction for CD-ROM data are inconsistent with each other, the error correction circuit 19 gives priority to the error correction for audio data. 
     The error correction circuit 19 is shown in more detail in FIG. 2. In FIG. 2, only those circuit elements which are directly necessary for description of the present invention are shown. 
     Referring to FIG. 2, the error correction circuit shown includes an audio data error syndrome calculation circuit 31 connected to the audio signal processing section 3 shown in FIG. 1 for calculating error syndromes of audio data. A CD-ROM data error syndrome calculation circuit 32 is connected to the CD-ROM signal processing section 8 shown in FIG. 1 for calculating error syndromes of CD-ROM data. An audio data error syndrome monitoring circuit 33 and a CD-ROM data error syndrome monitoring circuit 34 make up the syndrome monitoring circuit 20 shown in FIG. 1. 
     The error correction circuit further includes a vector to exponent conversion ROM 38 to convert data in a vector form into data in an exponent form, a D 2  /E to X conversion ROM 51 to convert D 2  /E to X according to equation (17) above, and an exponent to vector conversion ROM 53 to convert data from the exponent form into data with a vector form. The error correction circuit further includes selectors (SEL0 to SEL5) 35, 37, 39, 40, 44 and 52 for input selection, and registers (D1 to D12) 36, 41 to 43, 48, 50, 54, 55 and 57 to 60 for temporary storage of data. The error correction circuit further includes a pair of exclusive OR (EXOR) circuits 45 and 46, a full adder (FA) 47 to multiply or divide by exponents, a half adder (HA) 49 for mod255 calculation on GF(2 8 ), and an adder circuit 56 for addition of the vector form. 
     The elements in the sequence outlined in FIG. 2 beginning with the vector to exponent conversion ROM 38 up to and including the D 2  /E to X conversion ROM 51 constitute an exponent calculation area for multiplication and division in the exponent form. The remaining elements constitute a vector calculation area and execute addition and subtraction in the vector form. 
     Error correction operation for audio data and CD-ROM data according to an embodiment of the present invention as illustrated by the circuit shown in FIG. 2 is described below. 
     Error Correction Operation for Audio Data 
     First, the error syndrome calculation circuit 31 calculates error syndromes S 0  through S 3  from the audio data in accordance with the equations (1) to (4) from above. Then, the error syndrome monitoring circuit 33 discriminates whether the error syndromes thus obtained are all equal to 0, that is, S 0  =S 1  =S 2  =S 3  =0. When S 0  =S 1  =S 2  =S 3  =0, the audio data includes no errors, and accordingly, error correction calculation described below is not performed for the audio data. When the relationship S 0  =S 1  =S 2  =S 3  =0 is not true, the audio data most likely includes an error or errors, and accordingly, error correction calculation described below is performed on the audio data. 
     First, the error syndromes obtained by the calculation described above are converted into data in the exponent form by the vector to exponent conversion ROM 38 and then transmitted to the registers 41 to 43. Error syndrome S 0  is stored in register 41, error syndrome S 1  in register 42, and error syndromes S 2  and S 3  are successively stored in register 43, in accordance with the steps prescribed by the process. The full adder 47 and the half adder 49 are used to calculate S 0  ·S 2  and S 1   2  from the error syndromes, selected by the selector 44, and the resulting values are stored in register 50. 
     The values S 0  ·S 2  and S 1   2  available at register 50 are converted into vector form by the exponent to vector conversion ROM 53 and then stored in registers 54 and 55, respectively. Registers 54 and 55 are added by the adder circuit 56 and the result is stored in register 57, by which A=S 0  ·S 2  +S 1   2  of equation (5) above is obtained. The value of B and C for the equations (6) and (7) above are calculated in a similar manner. 
     The values of variables A, B and C obtained above are routed from the register 57 back to the selector 37 and stored by the selector 37 in registers 41 to 43, respectively. The values of D and E are calculated according to equations (15) and (16) and the results are stored in register 50 in a similar manner as described above. 
     The values of variables D and E are routed from register 50 through the selector 52 back to the selector 40 to calculate D 2  in a similar manner as described above. The value of D 2  is routed back to the selector 40 to calculate D 2  /E. The quantity D 2  /E is calculated and converted into X by the D 2  /E to X conversion ROM 51. The value of X and D 2  /E are added by the adder circuit 56 to calculate the variable Y where Y=D 2  /E+X according to equation (18) and the value calculated is stored in register 57. 
     The steps described above calculate the values of the variables necessary for error correction. These variables are checked with reference to the criteria described above. If the audio data is determined to include a single error, the value of α i  is calculated in the exponent calculation area where α i  =S 1  /S 0  according to equation (8). 
     If the audio is determined to include two errors, the values of the exponential representations of the two error positions α i  and α j  are calculated in the exponent calculation area from the values of S 0 , S 1 , D, X, and Y as determined above according to equations (11) and (12). The values of the errors ei and ej are calculated in a similar manner according to equations (13) and (14). 
     Error Correction Operation for CD-ROM Data 
     When error correction is performed using the CD-ROM data, the selector 35 in FIG. 2 is switched to receive only the CD-ROM data. 
     Error correction for CD-ROM data includes detection correction and disappearance correction as described above. For the detection correction, the value of α i  is calculated in the exponent calculation area where α i  =S 1  /S 0 , according to equation (19). The operation of the error correction circuit during detection correction is illustrated by the time plots in FIG. 3a and FIG. 3b. In these time plots, the α i  is represented by Ai and the error value ei is represented by Ei. Further, the suffix v represents the vector form, and the suffix e represents the exponent form. 
     Because the syndromes S 0  and S 1  and the exponential representations of the two error positions α i  and α j  are provided in advance in disappearance correction, the simultaneous equations (22) and (23) can be solved and the error values ei and ej can be determined. The operation of the error correction circuit during disappearance correction is illustrated by the time plots in FIG. 4a and FIG. 4b. In these time plots the exponential representations of the two error positions α i  and α j  are represented by Ai and Aj, and the error values ei and ej are represented by Ei and Ej, respectively. The suffix v represents the vector form, and the suffix e represents the exponent form. 
     It should be apparent to one of ordinary skill in the art that many changes and modifications can be made to the invention described above without departing from the spirit and scope of the invention as set forth herein.