Abstract:
An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    Not applicable. 
       STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0002]    Not applicable. 
       REFERENCE TO A MICROFICHE APPENDIX 
       [0003]    Not applicable. 
       BACKGROUND 
       [0004]    In telecommunication and data communication, equalization refers to the process of reversing a distortion experienced by a signal transmitted through a channel. Transmission channels, such as radio frequency (RF) channels, electrical wireline channels, and optical channels, may have non-flat frequency responses and non-linear phase responses. Equalizers are commonly employed in receiver frontends to compensate frequency-dependent amplitude and phase distortion in received signals prior to data decoding. 
       SUMMARY 
       [0005]    In one embodiment, the disclosure includes an apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal. 
         [0006]    In another embodiment, the disclosure includes a method comprising obtaining a channel response of a transmission link comprising a low-frequency channel loss in a first frequency range and a high-frequency channel loss in a second frequency range, selecting a first resistance for a first resistor and a first capacitance for a first capacitor according to the second frequency range to compensate the high-frequency channel loss, and selecting a circuit element according to a parasitic capacitance of a transistor and the first frequency range to compensate the low-frequency channel loss. 
         [0007]    In yet another embodiment, the disclosure includes an apparatus comprising a differential amplifier circuit comprising a first circuit branch and a second circuit branch connected to each other in parallel, a first transistor comprising a first gate and a first drain, wherein the first drain is coupled to the first circuit branch, a second transistor comprising a second gate and a second drain, wherein the second drain is coupled to the second circuit branch, a first resistor coupled to the first gate, and a second resistor coupled to the first resistor and the second gate such that the second resistor is positioned between the first resistor and the second gate. 
         [0008]    In yet another embodiment, the disclosure includes an apparatus comprising a power supply, a differential amplifier circuit coupled to the power supply and comprising a first circuit branch, and a second circuit branch connected to the first circuit branch in parallel, a first transistor comprising a first gate, and a first drain coupled to the first circuit branch, a second transistor comprising a second gate, and a second drain coupled to the second circuit branch, a first reference current source coupled to the power supply, a third transistor comprising a third drain coupled to the first reference current source, and a third gate coupled to the first gate, a second reference current source coupled to the power supply, and a fourth transistor comprising a fourth drain coupled to the second reference current source, and a fourth gate coupled to the second gate. 
         [0009]    These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts. 
           [0011]      FIG. 1  is a schematic diagram of a CTLE circuit. 
           [0012]      FIG. 2  is a graph illustrating a channel response of a transmission link. 
           [0013]      FIG. 3  is a graph illustrating a frequency response of the CTLE circuit of  FIG. 1 . 
           [0014]      FIG. 4  is a schematic diagram of a CTLE circuit that compensates both high-frequency channel loss and low-frequency channel loss according to an embodiment of the disclosure. 
           [0015]      FIG. 5  is a graph illustrating a frequency response of the CTLE circuit of  FIG. 4  according to an embodiment of the disclosure. 
           [0016]      FIG. 6  is a schematic diagram of a CTLE circuit that compensates both high-frequency channel loss and low-frequency channel loss according to another embodiment of the disclosure. 
           [0017]      FIG. 7  is a graph illustrating a frequency response of the CTLE circuit of  FIG. 6  according to an embodiment of the disclosure. 
           [0018]      FIG. 8  is a graph comparing performance of the CTLE circuits of  FIGS. 1, 4, and 6  according to an embodiment of the disclosure. 
           [0019]      FIG. 9  is a graph comparing performance of the CTLE circuits of  FIGS. 1, 4, and 6  according to another embodiment of the disclosure. 
           [0020]      FIG. 10  is a flowchart of a method for configuring a CTLE to provide equalization at both high and low frequencies according to an embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    It should be understood at the outset that, although illustrative implementations of one or more embodiments are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents. 
         [0022]    A high-speed signal propagating through a wireline channel is exposed to high-frequency impairments such as reflections, dielectric loss, and loss due to the skin effect. These impairments may generate inter-symbol interference (ISI) and degrade the quality of the signal, causing a receiver to incorrectly decode the signal. In order to reliably decode the signal, a receiver may employ a CTLE circuit at the receiver frontend to compensate the channel loss. 
         [0023]      FIG. 1  is a schematic diagram of a CTLE circuit  100 . The circuit  100  comprises a differential amplifier circuit  110 , a frequency-shaping circuit  120 , and a bias circuit  130 . The differential amplifier circuit  110  comprises two matched n-channel metal-oxide semiconductor (NMOS) transistors  111  and  112 , two matched resistors  113  and  114 , and two matched inductors  115  and  116 . Matched components refer to components comprising matching characteristics. For example, the transistors  111  and  112  comprise about the same current gain and about the same gate-source voltage, the resistors  113  and  114  comprise about the same resistance, and the inductors  115  and  116  comprise about the same inductance. The gates of the transistors  111  and  112  are configured to connect to a pair of differential input terminals VINP and VINM, respectively. The circuit  100  illustrates the positive and the negative components of a differential pair by a letter P and a letter M, respectively. The drains of the transistors  111  and  112  are configured to connect to a pair of differential output terminals VOUTM and VOUTP, respectively. The capacitance seen at the output terminals VOUTP and VOUTM are represented as capacitors  117  and  118 . The resistor  113  and the inductor  115  are connected in series between the drain of the transistor  111  and a power supply voltage shown as V DD . Similarly, the resistor  114  and the inductor  116  are connected in series between the drain of the transistor  112  and the power supply voltage. The differential amplifier circuit  110  amplifies the difference between a pair of differential signals input at VINP and VINM. The inductance of the inductors  115  and  116  are configured, in addition to the value of other components such as the capacitors  117  and  118  at the output terminals VOUTP and VOUTM, to provide a peak in the frequency response of the differential amplifier circuit  110  at a particular frequency to extend the bandwidth of the differential amplifier circuit  110  and the circuit  100 . 
         [0024]    The frequency-shaping circuit  120  is coupled to the differential amplifier circuit  110  at the sources of the transistors  111  and  112 , which are shown as connection nodes SP and SM, respectively. The frequency-shaping circuit  120  comprises a series combination of two matched resistors  121  and  122  and a series combination of two matched capacitors  123  and  124 , where the two series combinations are connected in parallel. The frequency-shaping circuit  120  reshapes the frequency response of the differential amplifier circuit  110 . For example, the frequency-shaping circuit  120  may be configured to provide signal amplification at high frequencies, as described more fully below. As shown, the circuit  100  may be viewed as two symmetrical differential circuit branches  101  and  102  connected in parallel. 
         [0025]    The bias circuit  130  is coupled to the differential amplifier circuit  110  and the frequency-shaping circuit  120  at the nodes SP and SM. The bias circuit  130  comprises three NMOS transistors  131 ,  132 , and  133  and a reference current source  134 . The drains of the transistors  131  and  132  are configured to connect to the sources of the transistors  111  and  112 , respectively. The reference current source  134  is configured to connect between the power supply voltage V DD  and the drain of the transistor  133 . The sources of the transistors  131 ,  132 , and  133  are connected to a ground shown as GND. The gate and the drain of the transistor  133  are connected to each other. The gate of the transistor  133  is further connected to each of the gates of the transistors  131  and  132 . The transistors  131  and  132  operate as current sources to the circuit branches  101  and  102 , respectively. The reference current source  134  controls the current sources provided by the transistors  131  and  132  such that a suitable direct current (DC) bias is provided to each of the circuit branches  101  and  102 . 
         [0026]    In the circuit  100 , the parasitic capacitance of the transistors  131  and  132  also contribute to the frequency shaping in addition to the frequency-shaping circuit  120 . The parasitic capacitances across the gates and drains of the transistors  131  and  132  are represented by capacitors  135  and  136 , respectively. The parasitic capacitance across the gate and drain of a transistor such as the transistors  131  and  132  is referred to as a gate-drain capacitance, which may be fixed at a certain operating region of the transistor. To analyze the frequency shaping, the parasitic capacitances of the transistors  131  and  132  are combined with the resistor-capacitor (RC) network of the frequency-shaping circuit  120 . A differential circuit may be represented as two half-circuits with equal gains and responses, one corresponding to the circuit branch  101  and the other corresponding to the circuit branch  102 . The circuit  140  illustrates the equivalent half RC network across the nodes SP and SM. The circuit  140  comprises a resistor  141 , a capacitor  142 , and a capacitor  143  connected in parallel. When representing the half-circuit in the circuit branch  101 , the resistor  141  and the capacitors  142  and  143  correspond to the resistor  121  and the capacitors  123  and  135 , respectively. When representing the half-circuit in the circuit branch  102 , the resistor  141  and the capacitors  142  and  143  correspond to the resistor  122  and the capacitors  124  and  136 , respectively. The parallel configuration of the resistor  141  and the capacitors  142  and  143  produces a zero in the frequency response of the circuit  140 . 
         [0027]    The transfer function of the circuit  100  may be represented as a function of the components in the circuit  100 . As an example, the resistance of the resistors  121  and  113  are represented as R S  and R D , respectively, the capacitance of the capacitors  123 ,  135 , and  117  are represented as C S , C gd , and C L , respectively, the inductance of the inductor  115  is represented as L, and the transconductance of the transistor  111  is represented as g mD . Thus, the transfer function or frequency response H(s) of the circuit  100  is expressed as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
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         [0000]    where s is the complex number frequency. It should be noted that both the circuit branches  101  and  102  are symmetric, thus comprise the same transfer function H(s). 
         [0028]    As can be seen from Equation (1), the transfer function H(s) comprises a first zero at an intermediate frequency, and a second zero, a real pole, and two conjugate poles at high frequencies. The frequency Z of the first zero at the intermediate frequency is as shown below: 
         [0000]    
       
         
           
             
               
                 
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                   = 
                   
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         [0000]    As shown in Equation (2), the zero is dependent on the resistance of the resistor  121 , the capacitance of the capacitor  123 , and the gate-drain capacitance of the transistor  131 . Thus, R S  and C S  may be selected to produce a certain frequency response for channel equalization. For example, to equalize a channel that attenuates high frequencies above 1 gigahertz (GHz), R S  and C S  may be configured according to C gd  to produce a zero at about 1 GHz. 
         [0029]    As described above, the inductors  115  and  116  extend the bandwidth of the circuit  100 . To extend the bandwidth, the inductance of the inductors  115  and  116  are selected along with other components such as the capacitors  117  and  118  to produce a peak near a Nyquist frequency of an input signal at the differential input terminals VINP and VINM. For example, when the input signal comprises a data date of about 28 gigabits per second (Gbps), the inductances of the inductors  115  and  116  are configured along with the other components to produce two conjugate poles to form a peak at about 14 GHz for both of the circuit branch  101  and the circuit branch  102 . 
         [0030]      FIG. 2  is a graph  200  illustrating a channel response  210  of a transmission link such as an electrical wire. The CTLE circuit  100  may be employed to equalize the channel response  210 . The x-axis represents frequency in units of hertz (Hz) in a logarithmic scale. The y-axis represents gains in units of decibels (dB). The channel response  210  decays with increasing frequencies and the decay is substantially significant above 1 GHz. As shown, the attenuation is at −15 dB at about 14 GHz. The high-frequency attenuation in the frequency range of about 1 GHz and above may cause short-term ISI in a received signal, whereas the low-frequency attenuation in the frequency range between about 100 megahertz (MHz) to about 1 GHz may cause long-term ISI in the received signal. 
         [0031]      FIG. 3  is a graph  300  illustrating a frequency response  310  of the CTLE circuit  100 . The x-axis represents frequency in units of Hz in a logarithmic scale. The y-axis represents gains in units of dB. The frequency response  310  is produced by configuring the circuit  100  to equalize the channel response  210  such that a received signal may comprise a frequency spectrum that is flat in the frequency band of the received signal. The circuit  100  may be located at a frontend of a receiver coupled to the transmission link. For example, the resistances of the resistors  121  and  122  and the capacitances of the capacitors  123  and  124  are configured to produce a zero at about 1 GHz in the frequency response of the circuit  100 . In addition, the inductances of the inductors  115  and  116  are configured to produce two conjugate poles to form a peak at about 14 GHz. As shown, the frequency response  310  comprises a steep slope of about 20 dB/decade above 1 GHz, providing compensation or equalization to the short-term ISI. However, the frequency response  310  is almost flat in the region  320  between about 100 MHz and about 1 GHz, thus providing no compensation or equalization to the long-term ISI. In addition, the frequency response  310  comprises a dip at about 500 MHz, which may be caused by a previous stage in the frontend of the receiver frontend, further degrading the performance of the circuit  100 . Thus, the circuit  100  may not invert the attenuation rate of the channel response  210  at low frequencies. One approach to providing both high- and low-frequency compensation is to employ active feedback technology with a CTLE. However, active feedback technology consumes more power and area, and thus may not be a desirable solution. 
         [0032]    Disclosed herein are embodiments of an efficient CTLE that provides equalization at both low and high frequencies. The disclosed embodiments configure a CTLE circuit to produce at least a first pole, a first zero, and a second zero in a frequency response of the CTLE circuit. The frequency locations of the first pole and the first zero are selected such that the first pole and the first zero may provide a gain to compensate low-frequency channel loss or long-term ISI. The frequency location of the second zero is selected such that the second zero may provide a gain to compensate high-frequency channel loss or short-term ISI. The CTLE circuit comprises a differential amplifier circuit, a frequency-shaping circuit, and a bias circuit. The frequency-shaping circuit is coupled to the differential amplifier circuit to provide frequency-shaping to the differential amplifier circuit. For example, the frequency-shaping circuit may comprise a parallel RC network configured to produce a second zero for compensating the high-frequency channel loss. The bias circuit provides two branches of bias current sources to the differential amplifier circuit. In one embodiment, two resistors are connected between the gates of the two bias current sources, where the resistance of the two resistors are selected to produce a first zero and a first pole for compensating the low-frequency channel loss. In another embodiment, the bias circuit employs two separate reference current sources, each coupled to a diode-connected transistor, to separately bias a pair of differential circuit branches of the differential amplifier circuit, where the transconductances of the diode-connected transistors are selected to produce the first pole and the first zero. The first pole in the embodiments is used to exactly invert the attenuation rate in the low frequency range. The disclosed embodiments are suitable for use in high-speed systems such as optical modules operating up to about 100 Gbps. Although the present disclosure describes the CTLE circuit in the context of metal-oxide-semiconductor field-effect transistors (MOSFETs), other type of transistors such as bipolar junction transistors (BJTs) may also be employed to achieve similar functionalities. 
         [0033]      FIG. 4  is a schematic diagram of a CTLE circuit  400  that compensates both high-frequency channel loss and low-frequency channel loss according to an embodiment of the disclosure. The circuit  400  produces two zeros, one at a low frequency and another at an intermediate frequency, in a frequency response of the circuit  400  instead of a single zero at the intermediate frequency as in the circuit  100 . The additional zero located at the low frequency is to provide low-frequency gain for long-term ISI compensation. The circuit  400  also produces two conjugate poles to form a peak at a Nyquist frequency to provide high-frequency gain for short-term ISI compensation. The circuit  400  further comprises a differential amplifier circuit  410 , a frequency-shaping circuit  420 , and a bias circuit  430 . The differential amplifier circuit  410  comprises two matched NMOS transistors  411  and  412 , two matched resistors  413  and  414 , and two matched inductors  415  and  416 . The gates of the transistors  411  and  412  are provided as differential input terminals VINP and VINM, respectively. The drains of the transistors  411  and  412  are provided as differential output terminals VOUTM and VOUTP, respectively. The capacitance at the output terminals VOUTP and VOUTM are represented as capacitors  417  and  418 . The resistor  413  and the inductor  415  are connected in series between the drain of the transistor  411  and a power supply voltage V DD . Similarly, the resistor  414  and the inductor  416  are connected in series between the drain of the transistor  412  and V DD . The differential amplifier circuit  410  provides signal amplification through the transistors  411  and  412  and bandwidth extension through the inductors  415  and  416 . 
         [0034]    The frequency-shaping circuit  420  comprises a series combination of two matched resistors  421  and  422  connected in parallel with a series combination of two matched capacitors  423  and  424 . The frequency-shaping circuit  420  is coupled to the differential amplifier circuit  410  at the sources of the transistors  411  and  412  shown as connection nodes SP and SM, respectively. The frequency-shaping circuit  420  shapes a frequency response of the differential amplifier circuit  410 . As shown, the circuit  400  may be viewed as two symmetrical differential circuit branches  401  and  402  connected in parallel. 
         [0035]    The bias circuit  430  is coupled to the differential amplifier circuit  410  and the frequency-shaping circuit  420  at SP and SM. The bias circuit  430  comprises three NMOS transistors  431 ,  432 , and  433 , a reference current source  434 , and resistors  437  and  438 . The drains of the transistors  431  and  432  are configured to connect to the sources of the transistors  411  and  412 , respectively. The reference current source  434  is configured to couple between the drain of the transistor  433  and V DD . The sources of the transistors  431 ,  432 , and  433  are connected to a ground shown as GND. The gate and drain of the transistor  433  are connected to each other. The resistors  437  and  438  are connected in series between the gates of the transistors  431  and  432 . The gate of the transistor  433  is further connected to a connection point between the resistors  437  and  438 . The reference current source  434  is configured to provide suitable DC biases to the circuit branches  401  and  402  via the transistors  431  and  432 . 
         [0036]    Similar to the transistors  131  and  132 , the transistors  431  and  432  comprise parasitic capacitances across the gates and the sources. The parasitic capacitances are represented as capacitors  435  and  436 . The circuit  440  illustrates the equivalent half RC network across SP and SM. The circuit  440  comprises resistors  441  and  446  and capacitors  442  and  443 . When representing the half-circuit in the circuit branch  401 , the resistors  441  and  446  and the capacitors  442  and  443  correspond to the resistors  421  and  437  and the capacitors  423  and  435 , respectively. When representing the half-circuit in the circuit branch  402 , the resistors  441  and  446  and the capacitors  442  and  443  correspond to the resistors  422  and  438  and the capacitors  424  and  436 , respectively. The resistor  446  and the capacitor  443  are connected in series. The resistor  441 , the capacitor  442 , and the series combination of the resistor  446  and the capacitor  443  are connected in parallel. The resistor  441  and the capacitor  442  produce a second zero in the frequency response of the circuit  440 . The resistors  441  and  446  and the capacitor  443  produce a first zero and a first pole in the frequency response. 
         [0037]    The transfer function of the circuit  400  may be represented as a function of the components in the circuit  400 . As an example, the resistance of the resistors  421 ,  437 , and  413  are represented as R S , R t , and R D , respectively; the capacitance of the capacitors  423 ,  435 , and  417  are represented as C S , C gd , and C L , respectively; the inductance of the inductor  415  is represented as L; and the transconductance of the transistor  411  is represented as g mD . Thus, the transfer function or frequency response H(s) of the circuit  400  is expressed as follows: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    Since the circuit branches  401  and  402  are symmetric, the circuit branches  401  and  402  comprise the same transfer function H(s). 
         [0038]    As shown in equation (3), the transfer function H(s) comprises a first zero at a low frequency, a second zero at an intermediate frequency, and a pole between the first and the second zeros. The pole between the first and the second zeros may reduce the slope in a frequency range between the low frequency and the intermediate frequency in the frequency response to revert channel loss in the corresponding frequency range. The second zero is located at a frequency Z 2  as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
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                             1 
                             
                               
                                 R 
                                 s 
                               
                                
                               
                                 C 
                                 s 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The first zero is located at a frequency Z 1  as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           Z 
                           1 
                         
                         = 
                           
                          
                         
                           - 
                           
                             1 
                             
                               
                                 
                                   R 
                                   s 
                                 
                                  
                                 
                                   C 
                                   s 
                                 
                               
                               + 
                               
                                 
                                   ( 
                                   
                                     
                                       R 
                                       s 
                                     
                                     + 
                                     
                                       R 
                                       t 
                                     
                                   
                                   ) 
                                 
                                  
                                 
                                   C 
                                   gd 
                                 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         ≈ 
                           
                          
                         
                           - 
                           
                             1 
                             
                               
                                 ( 
                                 
                                   
                                     R 
                                     t 
                                   
                                   + 
                                   
                                     R 
                                     s 
                                   
                                 
                                 ) 
                               
                                
                               
                                 C 
                                 gd 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The first pole is located at a frequency P 1  as follows: 
         [0000]    
       
         
           
             
               P 
               1 
             
             = 
             
               - 
               
                 1 
                 
                   
                     R 
                     t 
                   
                    
                   
                     C 
                     gd 
                   
                 
               
             
           
         
       
     
         [0039]    Thus, the resistance of the resistor  437  may be configured according to the fixed gate-drain parasitic capacitance of the transistor  431  such that Z 1  is at a desired frequency. Similarly, the resistance of the resistor  421  and the capacitance of the capacitor  423  may be configured such that Z 2  is at another desired frequency. The frequency Z 2  is at a higher frequency than Z 1 . As such, the first and second zeros may be placed such that the frequency response of the circuit  400  may provide gains at a low-frequency range of a signal bandwidth for long-term ISI compensation. The circuit  400  also produces two conjugate poles to from a peak at a Nyquist frequency, where the two conjugate poles are contributed by the inductors  415  or  416  in the differential amplifier circuit  410 . For example, to equalize a channel that attenuates signals with increasing frequencies beginning at about 100 MHz and rapidly rolls off at about 1 GHz, R S  and C S  may be configured to produce the second zero at about 1 GHz, and R t  may be configured according to C gd  to produce the first zero at about 100 MHz. 
         [0040]      FIG. 5  is a graph  500  illustrating a frequency response  510  of the CTLE circuit  400  according to an embodiment of the disclosure. The x-axis represents frequency in units of Hz in a logarithmic scale. The y-axis represents gains in units of dB. The frequency response  510  is produced by configuring the circuit  400  to equalize the channel response  210 . For example, the resistance of the resistor  421  and the capacitance of the capacitor  423  are configured to produce a zero at about 1 GHz in the frequency response of the circuit branch  401 . Similarly, the resistance of the resistor  422  and the capacitance of the capacitor  424  are configured to produce a zero at about 1 GHz in the frequency response of the circuit branch  402 . The resistances of the resistors  437  and  438  are configured according to the gate-drain parasitic capacitances of the transistors  431  and  432  to produce a zero at about 100 MHz in the frequency response of the circuit branch  401  and the frequency response of the circuit branch  402 . In addition, the inductance of the inductors  415  and  416 , are configured to produce two conjugate poles to form a peak at about 14 GHz. Comparing the frequency response  510  to the frequency response  310 , in addition to gain or peaking at high frequencies, the frequency response  510  provides gain in the region  520  between about 100 MHz to about 1 GHz. Thus, the circuit  400  may compensate channel loss at both low and high frequencies. Therefore, the circuit  400  may equalize both long-term and short-term ISI instead of only short-term ISI as in the circuit  100 . 
         [0041]      FIG. 6  is a schematic diagram of a CTLE circuit  600  that compensates both high-frequency channel loss and low-frequency channel loss according to another embodiment of the disclosure. Similar to the circuit  400 , the circuit  600  produces two zeros, one at a low frequency and another at an intermediate frequency, in a frequency response of the circuit  600 . However, the circuit  600  comprises two identical reference current sources  637  and  638  instead of a single reference current source  434  as in the circuit  400 . The circuit  600  employs the transconductances of the transistors  631  and  632  to generate the first pole and the first zero instead of resistors such as the resistors  437  and  438 . The circuit  600  comprises a differential amplifier circuit  610 , a frequency-shaping circuit  620 , and a bias circuit  630 . The differential amplifier circuit  610  comprises two matched NMOS transistors  611  and  612 , two matched resistors  613  and  614 , and two matched inductors  615  and  616  arranged in a similar configuration as in the differential amplifier circuit  410 . The gates of the transistors  611  and  612  are provided as input terminals VINP and VINM, respectively. The drains of the transistors  611  and  612  are provided as output terminals VOUTP and VOUTM, respectively. The capacitance at the output terminals VOUTP and VOUTM are represented as capacitors  617  and  618 . The frequency-shaping circuit  620  comprises two matched resistors  621  and  622  and two matched capacitors  623  and  624  arranged in a similar configuration as in the frequency-shaping circuit  420 . The differential amplifier circuit  610  and the frequency-shaping circuit  620  are coupled at connection nodes SP and SM. Similar to the circuit  400 , the circuit  600  may be viewed as two symmetrical differential branches  601  and  602  connected in parallel. 
         [0042]    The bias circuit  630  comprises four NMOS transistors  631 ,  632 ,  633 , and  634  and two matched reference current sources  637  and  638 . The reference current source  637  is coupled between the drain of the transistor  631  and a power supply voltage V DD . The reference current source  638  is coupled between the drain of the transistor  632  and V DD . The drains of the transistors  633  and  634  are connected to the sources of the transistors  611  and  612 , respectively. The gate and drain of the transistor  631  are connected to each other and to the gate of the transistor  633 . The gate and drain of the transistor  632  are connected to each other and to the gate of the transistor  634 . The sources of the transistors  631 - 634  are connected to a ground shown as GND. The reference current source  637  and the transistors  631  and  633  provide a bias current source to the circuit branch  601 . The reference current source  638  and the transistors  632  and  634  provide a bias current source to the circuit branch  602 . 
         [0043]    Similar to the transistors  131 ,  132 ,  431 , and  432 , the transistors  633  and  634  comprise parasitic capacitances across the gates and the sources represented as capacitors  635  and  636 , respectively. The circuit  640  illustrates the equivalent half RC network across the connection nodes SP and SM. The circuit  640  comprises resistors  641  and  646  and capacitors  642  and  643  arranged in a similar configuration as the circuit  440 . When representing the half-circuit in the circuit positive signal branch  601 , the resistor  641  corresponds to the resistor  621 , the resistor  646  represents the transconductance of the transistor  631 , and the capacitors  642  and  643  correspond to the capacitors  623  and  635 , respectively. When representing the half-circuit in the circuit branch  602 , the resistor  641  corresponds to the resistor  622 , the resistor  646  represents the transconductance of the transistor  632 , and the capacitors  642  and  643  correspond to the capacitors  624  and  636 , respectively. The resistor  641  and the capacitor  642  produce a second zero in the frequency response of the circuit  640 . The resistors  641  and  646  and the capacitor  643  produce a first zero and a first pole in the frequency response. 
         [0044]    The transfer function of the circuit  600  may be represented as a function of the components in the circuit  600 . As an example, the resistances of the resistors  621  and  613  are represented as R S  and R D , respectively; the capacitances of the capacitors  623 ,  635 , and  617  are represented as C S , C gd , and C L , respectively; and the transconductances of the transistor  611  and the transistor  631  are represented as g mD  and g mCR . Thus, the transfer function or frequency response H(s) of the circuit  600  is expressed as shown below: 
         [0000]    
       
         
           
             
               
                 
                   
                     H 
                      
                     
                       ( 
                       s 
                       ) 
                     
                   
                   = 
                   
                     
                       - 
                       
                         
                           R 
                           D 
                         
                         
                           R 
                           s 
                         
                       
                     
                      
                     
                       
                         
                           
                             
                               ( 
                               
                                 1 
                                 + 
                                 
                                   s 
                                    
                                   
                                     
                                       
                                         R 
                                         s 
                                       
                                        
                                       
                                         
                                           C 
                                           s 
                                         
                                          
                                         
                                           ( 
                                           
                                             1 
                                             / 
                                             
                                               g 
                                               mCR 
                                             
                                           
                                           ) 
                                         
                                       
                                        
                                       
                                         C 
                                         gd 
                                       
                                     
                                     
                                       
                                         
                                           
                                             
                                               
                                                 R 
                                                 s 
                                               
                                                
                                               
                                                 C 
                                                 s 
                                               
                                             
                                             + 
                                           
                                         
                                       
                                       
                                         
                                           
                                             
                                               ( 
                                               
                                                 
                                                   R 
                                                   s 
                                                 
                                                 + 
                                                 
                                                   1 
                                                   / 
                                                   
                                                     g 
                                                     mCR 
                                                   
                                                 
                                               
                                               ) 
                                             
                                              
                                             
                                               C 
                                               gd 
                                             
                                           
                                         
                                       
                                     
                                   
                                 
                               
                               ) 
                             
                           
                         
                         
                           
                             
                               ( 
                               
                                 1 
                                 + 
                                 
                                   
                                     s 
                                      
                                     
                                       ( 
                                       
                                         
                                           
                                             R 
                                             s 
                                           
                                            
                                           
                                             C 
                                             s 
                                           
                                         
                                         + 
                                         
                                           
                                             ( 
                                             
                                               
                                                 R 
                                                 s 
                                               
                                               + 
                                               
                                                 1 
                                                 / 
                                                 
                                                   g 
                                                   mCR 
                                                 
                                               
                                             
                                             ) 
                                           
                                            
                                           
                                             C 
                                             gd 
                                           
                                         
                                       
                                       ) 
                                     
                                   
                                    
                                   
                                     ( 
                                     
                                       1 
                                       + 
                                       
                                         s 
                                          
                                         
                                           L 
                                           
                                             R 
                                             D 
                                           
                                         
                                       
                                     
                                     ) 
                                   
                                 
                               
                             
                           
                         
                       
                       
                         
                           ( 
                           
                             1 
                             + 
                             
                               
                                 sC 
                                 gd 
                               
                               / 
                               
                                 g 
                                 mCR 
                               
                             
                           
                           ) 
                         
                          
                         
                           ( 
                           
                             1 
                             + 
                             
                               s 
                                
                               
                                 
                                   C 
                                   s 
                                 
                                 
                                   g 
                                   mD 
                                 
                               
                             
                           
                           ) 
                         
                          
                         
                           ( 
                           
                             1 
                             + 
                             
                               
                                 sR 
                                 D 
                               
                                
                               
                                 C 
                                 L 
                               
                             
                             + 
                             
                               
                                 s 
                                 2 
                               
                                
                               
                                 LC 
                                 L 
                               
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0045]    The transfer function H(s) of the circuit  600  comprises a first zero at a low frequency, a second zero at an intermediate frequency and a pole between these two zeros. The pole between the first and the second zeros may reduce the slope in a frequency range between the low frequency and the intermediate frequency in the frequency response to revert channel loss in the corresponding frequency range. The second zero is located at a frequency Z 2  as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           Z 
                           2 
                         
                         = 
                           
                          
                         
                           - 
                           
                             
                               
                                 
                                   R 
                                   S 
                                 
                                  
                                 
                                   C 
                                   S 
                                 
                               
                               + 
                               
                                 
                                   ( 
                                   
                                     
                                       R 
                                       S 
                                     
                                     + 
                                     
                                       1 
                                       / 
                                       
                                         G 
                                         MCR 
                                       
                                     
                                   
                                   ) 
                                 
                                  
                                 
                                   C 
                                   GD 
                                 
                               
                             
                             
                               
                                 R 
                                 S 
                               
                                
                               
                                 
                                   C 
                                   S 
                                 
                                  
                                 
                                   ( 
                                   
                                     1 
                                     / 
                                     
                                       G 
                                       MCR 
                                     
                                   
                                   ) 
                                 
                               
                                
                               
                                 C 
                                 GD 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         ≈ 
                           
                          
                         
                           
                             - 
                             
                               ( 
                               
                                 1 
                                 + 
                                 
                                   
                                     R 
                                     S 
                                   
                                    
                                   
                                     G 
                                     MCR 
                                   
                                 
                               
                               ) 
                             
                           
                            
                           
                             
                               1 
                               
                                 
                                   R 
                                   S 
                                 
                                  
                                 
                                   C 
                                   S 
                                 
                               
                             
                             . 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The first zero is located at a frequency Z 1  as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           Z 
                           1 
                         
                         = 
                           
                          
                         
                           - 
                           
                             1 
                             
                               
                                 
                                   R 
                                   s 
                                 
                                  
                                 
                                   C 
                                   s 
                                 
                               
                               + 
                               
                                 
                                   ( 
                                   
                                     
                                       R 
                                       s 
                                     
                                     + 
                                     
                                       1 
                                       / 
                                       
                                         g 
                                         mCR 
                                       
                                     
                                   
                                   ) 
                                 
                                  
                                 
                                   C 
                                   gd 
                                 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         ≈ 
                           
                          
                         
                           - 
                           
                             
                               1 
                               
                                 
                                   ( 
                                   
                                     
                                       1 
                                       / 
                                       
                                         g 
                                         mCR 
                                       
                                     
                                     + 
                                     
                                       R 
                                       s 
                                     
                                   
                                   ) 
                                 
                                  
                                 
                                   C 
                                   gd 
                                 
                               
                             
                             . 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The first pole is located at a frequency P 1  as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     P 
                     1 
                   
                   = 
                   
                     - 
                     
                       
                         g 
                         mCR 
                       
                       
                         C 
                         gd 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0046]    Thus, the tranconductance of the transistor  631  may be configured according to the fixed gate-drain parasitic capacitance of the transistor  633  such that Z 1  is at a desired frequency. Similarly, the resistance of the resistor  621  and the capacitance of the capacitor  623  may be configured such that Z 2  is at another desired frequency. Z 2  is at a higher frequency than Z 1 . As such, the first and second zeros may be placed such that the frequency response of the circuit  600  may provide gains at a low-frequency range of a signal bandwidth for long-term ISI compensation. The circuit  600  also produces two conjugate poles to form a peak at a Nyquist frequency. For example, to equalize a channel that attenuates signals with increasing frequencies beginning at about 100 MHz and rapidly rolls off at about 1 GHz, R S  and C S  may be configured to produce the second zero at about 1 GHz, and g mCR  may be configured according to C gd  to produce the first zero at about 100 MHz. 
         [0047]      FIG. 7  is a graph  700  illustrating a frequency response  710  of the CTLE circuit  600  according to an embodiment of the disclosure. The x-axis represents frequency in units of Hz in a logarithmic scale. The y-axis represents gains in units of dB. The frequency response  710  is produced by configuring the circuit  600  to equalize the channel response  210 . For example, the resistances of the resistors  621  and  622  and the capacitances of the capacitors  623  and  624  are configured to produce a zero at about 1 GHz corresponding to the gains seen above 1 GHz in the frequency response  710 . The transistors  631  and  632  are configured such that the transconductances of the transistors  631  and  632  and the gate-drain parasitic capacitances of the transistors  633  and  634  produce a zero at about 100 MHz. In addition, the inductances of the inductors  615  and  616  are configured to produce two conjugate poles to form a peak at about 14 GHz. Similar to the frequency response  510 , the frequency response  710  provides low-frequency gain in the low frequency region  720  between about 100 MHz and about 1 GHz and high-frequency gain between about 1 GHz and 14 GHz. Therefore, the circuit  600  may equalize both long-term and short-term ISI as in the circuit  400 . 
         [0048]      FIG. 8  is a graph  800  comparing performance of the circuits  100 ,  400 , and  600  according to an embodiment of the disclosure. The frequency responses  310 ,  510 , and  710  are overlaid for performance comparison. The curve  810  corresponds to the frequency response  310  of the circuit  100 . The curve  820  corresponds to the frequency response  510  of the circuit  400 . The curve  830  corresponds to the frequency response  710  of the circuit  600 . As shown, the curve  820  and  830  are lifted up in the frequency range between about 100 MHz to about 3 GHz, whereas the curve  810  of the circuit  100  is almost flat in the same frequency range. Thus, the circuits  400  and  600  improve equalization performance when compared to the circuit  100 . 
         [0049]      FIG. 9  is a graph  900  comparing performance of the circuits  100 ,  400 , and  600  according to another embodiment of the disclosure. The graph  900  is generated by equalizing a signal transmitted over a transmission link comprising a channel response as shown in the channel response  210 . The curve  940  shows a frequency spectrum of a received signal propagated though the transmission link prior to equalization. The received signal is applied to each of the circuits  100 ,  400 , and  600  at the input terminals VINP and VINM. The curve  910  shows the frequency response of the received signal measured at the output terminals of the circuit  100 . The curve  920  shows the frequency response of the received signal measured at the output terminals of the circuit  400 . The curve  930  shows the frequency response of the received signal measured at the output terminals of the circuit  600 . As shown, the curves  920  and  930  are substantially flat across the signal bandwidth, whereas the curve  910  dips between 100 MHz to about 3 GHz. Thus, the circuits  400  and  600  provide improved equalization performance when compared to the circuit  100 . 
         [0050]      FIG. 10  is a flowchart of a method  1000  for configuring a CTLE to provide equalization at both high and low frequencies according to an embodiment of the disclosure. The method  1000  may be employed to select circuit components for the circuits  400  and  600 . At step  1010 , a channel response of a transmission link comprising a low-frequency channel loss in a first frequency range and a high-frequency channel loss in a second frequency range is obtained. For example, the channel response may be similar to the channel response  210 . Based on the channel response, the placements of poles and zeros may be determined to reverse or compensate the high-frequency channel loss and the low-frequency channel loss. For example, a first pole and a first zero may be placed within the low-frequency range to compensate the low-frequency channel loss and a second zero may be place within the high-frequency range to compensate the high-frequency channel loss. At step  1020 , a first resistance for a first resistor and a first capacitance for a first capacitor are selected according to the second frequency range to compensate the high-frequency channel loss. For example, the first resistor and the first capacitor may correspond to the resistor  421  and the capacitor  423 , the resistor  422  and the capacitor  424 , the resistor  621  and the capacitor  623 , or the resistor  622  and the capacitor  624 . The first resistance and the first capacitance may be selected according to the equation (4). At step  1030 , a circuit element is selected according to a parasitic capacitance of a transistor such as a gate-drain parasitic capacitance and the first frequency range to compensate the low-frequency channel loss. For example, when employing circuit  400 , the circuit element corresponds to the resistor  437  or  438 , which may be selected according to equation (5) and (6). Alternatively, when employing the circuit  600 , the circuit element corresponds to the transistors  631  or  632 , which may be selected according to equation (9) and (10). 
         [0051]    While several embodiments have been provided in the present disclosure, it may be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented. 
         [0052]    In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and may be made without departing from the spirit and scope disclosed herein.