Abstract:
A circuit for determining an initial winding combination for motor startup of a polyphase dc motor having a transistor driver circuit comprising a plurality of high side winding drivers and low side winding drivers operably connected to first and second voltage sources comprises a current mirror circuit and a plurality of sense FETs each operably connected between one of the voltage sources and the gate of one of the winding driver transistors in each phase combination. The sense FETs are operably connected to one side of the current mirror circuit. The mirror circuit compares the current through the sense FET with a current threshold provided on the other side of the current mirror and produces an output signal when the threshold is reached. At the same time, the time to reach the threshold is measured and the phase combination having the longest time is stored. Also when the threshold is reached, the sequencer advances to the next phase combination for measurement until all phase combination have been sequenced. The motor is then started with the phase combination having the longest time measurement energized first.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to the field of polyphase DC motor control circuits, and more particularly to a circuit and method for determining the phase winding combination to energize in a motor such as a disk drive motor prior to startup of the motor. 
     2. Description of the Related Art 
     Polyphase dc motors are widely used in fixed disk drive applications in personal computers. Typically, such a drive utilizes a magnetic medium on a flat circular disk to store binary data on the disk. The disk is spun by the polyphase dc motor, commonly called a spindle motor, at a relatively constant speed. One or more magnetic heads supported on an actuator arm are selectively moved radially inwardly or outwardly over the surface of the spinning disk by an actuator voice coil motor to read and write data from and to selective locations on the disk. When power is removed from the spindle motor, for example, on power off of the personal computer or on a power failure, routines are automatically implemented to physically move the heads to a predetermined parked position on or off of a landing zone adjacent the data portion of the disk surface, and the rotation of the disks is stopped. When the drive is off, the position of the actuator arm and heads is thus known. 
     When power is again restored or the PC is turned on again, the disk drive spindle motor starts. It is desirable that the power consumed and time duration of disk drive startup be minimized. This may be desirable for several reasons, the predominant ones of which are that the user cannot access the drive until the disk is running at constant speed and power consumption should be minimized. However, in order to efficiently start the polyphase dc motor, the correct starting point, i.e. phase combination, for the sequence of winding energizations must be determined. This is typically done by passing a small current sequentially through each of the winding combinations in a predetermined sequence and measuring time it takes for the voltage developed across a common sensing resistor in series with each of the winding combinations to reach a predetermined value. A comparator is then used to determine which winding combination takes the longest time to reach the predetermined voltage value and thus senses the winding combination having the highest reluctance from intersecting the magnetic field generated by the stationary permanent magnet pole pieces of the rotor. Passing drive current through this particular winding combination will provide the most starting torque and therefore will be the optimum combination that should be first energized on motor startup. 
     Typical disk drive spin motor control systems and circuits are described in U.S. Pat. Nos. 5,294,877, 5,317,243, and 5,866,998, which are hereby incorporated herein by reference in their entirety. Hard disk drive spin motors are typically three phase dc motors which have three sets of stator windings, A, B, and C having sets of series coils connected in a Y configuration. The rotor is typically a four pole device. Electrical current is fed through two legs of the &#34;Y&#34; with the third leg left floating in a series of repetitive combinations to cause the rotor to rotate. A sequencer controls a power stage of transistor switches to connect the windings to the voltage sources in the proper order. The six combinations of winding connections are thus AH,BL; AH,CL; BH,CL; BH,AL; CH,AL; and CH,BL; where A, B, C, indicates the winding leg and the &#34;H&#34; and &#34;L&#34; indicates the high side driver transistor, typically a field effect transistor (FET) switch being turned on and the low side driver FET being turned on. 
     Voltage developed across an external sensing resistor is typically utilized to determine which winding combination to energize first on motor startup. This sensing resistor is typically in series with the low side driver FET. In order to accurately determine which winding combination for the sequencer to use, this resistor must be highly accurate and dependable. Consequently, the cost of this high precision, high reliability sense resistor is rather high. In addition, the sense resistor is typically separate and distinct from the driver IC chip. A separate comparator circuit is also required for implementing the voltage comparison. This conventional configuration is relatively expensive. Therefore there is a need for a more economical approach to sensing the position of the rotor for startup of polyphase dc motors. In addition, there is a need for a circuit which eliminates the need for a precision resistor and eliminates the need for a comparator circuit without loss of reliability and accuracy. 
     SUMMARY OF THE INVENTION 
     The present invention meets the above identified needs. The primary object of the invention is to provide a reliable, low cost circuit for sensing polyphase dc motor winding position in advance of motor startup in order to efficiently start up the motor. 
     Another object of the invention is to provide a polyphase motor control circuit which does not utilize precision resistors or a voltage comparator in order to sense rotor position prior to startup. 
     Another object of the invention is to provide a polyphase motor control circuit that utilizes a plurality of sense FETs and a current mirror to determine the appropriate phase sequence for motor startup. 
     A circuit for determining an initial winding combination for motor startup of a polyphase dc motor having a transistor driver circuit comprising a plurality of high side winding drivers and low side winding drivers operably connected to first and second voltage sources in accordance with the present invention comprises a current mirror circuit and a plurality of sense FETs each operably connected between one of the voltage sources and the gate of one of the winding driver transistors and operably connected to one side of the current mirror circuit. Preferably the sense FETs are connected to the control terminals of the low side drivers. The mirror circuit compares the current through the sense FET with a current threshold provided on the other side of the current mirror and produces an output signal when the threshold is reached. The low side driver transistor, preferably a field effect transistor (FET), and the sense FET, in one preferred embodiment, have their gates connected together and their sources connected to a common voltage source. The current mirror is connected to a voltage source, a timer and an winding incremental sequencer. The timer output is connected to a select register which is in turn connected to the winding sequencer. 
     The timer measures the time between initiation of current flow to a winding combination and occurrence of an output signal from the current mirror circuit which occurs when the sense FET current matches a predetermined threshold current supplied to the other side of the current mirror. The select register compares the elapsed time output from the timer to its presently stored time and phase combination and replaces the stored time and phase combination if the current elapsed time output from the timer exceeds the previously stored value. When all phase combinations have been sampled, the timer is disabled and the select register passes its currently stored phase combination to the sequencer as the winding combination to use for motor startup. Motor startup then proceeds in a conventional manner. 
     More particularly, when power is initially applied to the spindle motor, the timer enables the drivers and the increment sequencer enables a first combination of windings. This turns on one high side driver and one low side driver at the same time. When the low side driver FET is turned on, the timer begins counting and winding current begins to flow. A proportionally smaller current in the ratio 1:X flows through the sense FET to the current mirror circuit. When the sense FET current reaches the preset programmable current threshold, a signal is sent to the sequencer to advance to the next phase winding and stop the timer. The elapsed time is sent to the select register. The select register then compares the elapsed time with the previously stored time difference, if any, and overwrites the register if the elapsed time is longer and stores the sequence state for this longest time in the sequencer. At the same time, the sequencer advances to the next winding combination and the timing process repeats. After all six phase combinations have been tested in this manner, the sequence state stored in the select register is then used by the drive controller as the initial sequence state for startup of the spindle motor. 
     Other objects, features and advantages of the present invention will become apparent from a reading of the following detailed description when taken in conjunction with the accompanying drawing wherein a particular embodiment of the invention is disclosed as an illustrative example. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic of a three phase dc disk drive motor power circuit in accordance with one embodiment of the invention. 
     FIG. 2 is a schematic of a three phase dc disk drive motor power circuit in accordance with a second embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following description, like numerals will be utilized for like components wherever possible. Three preferred embodiments are described in detail. It is to be understood that other embodiments are envisioned as within the scope of the invention. For example, the circuit herein described may be utilized in any form of a polyphase motor, e.g., sinusoidal controlled, pulse width controlled, etc. and also is not limited to use in disk drive spin motors. In addition, transistor devices of either N or P type described and shown may be implemented with the other transistor type so long as voltage and current sources and semiconductor type is consistently and appropriately maintained. 
     First Embodiment 
     A simplified diagram of a disk drive motor power circuit 10 in accordance with a first embodiment of the invention is shown in FIG. 1. The circuit 10 drives a &#34;Y&#34; connected three phase dc motor stator 12 and has a mirror circuit 14 connected to a timer 44, to a current threshold 18 and to a three phase driver circuit 20. 
     The driver circuit 20 is composed of three essentially identical phase drivers 20A, 20B, and 20C, each one connected to one end 22 of each winding A, B, or C. The other end of each winding A, B and C is joined together at node 24. The following description is for the driver circuit connected to winding A and applies equally to each of the three transistor driver circuits shown. Each driver circuit has a high side driver FET 26 which has its drain terminal connected to a voltage supply 27 (Vspin) and its source terminal connected to a free end 22 of one of the windings A, B, or C, in this case, winding A. The gate of the driver 26 is connected to the sequencer 42 in a conventional manner. 
     The driver circuit 20 also has a low side driver FET 28 having its source terminal connected to a common voltage reference 30 and its drain terminal connected to the winding end 22 and thus to the source terminal of the high side driver FET 26. The control or gate terminal of the low side driver FET 28 is connected to the control or gate terminal of a sense FET 32 and to the source terminal of a measuring switch FET 34. The gate terminal of the low side driver FET 28 is also connected to the sequencer 42, as indicated by the dashed line, in a conventional manner. 
     The source of the sense FET 32 is connected to the common reference 30. The drain of the sense FET 32 is connected to the collector of a bipolar transistor 38 in the mirror circuit 14 and to the drain of the other two sense FETs 32. 
     The measuring switch FET 34 has its source connected to the gates of the low side driver FET 28 and its sense FET 32. The measuring switch FET 34 drain is connected to the drain of the low side driver FET 28 and thus the one end 22 of the winding A, B, or C. The gate of the measuring switch FET 34 is connected to the output of an AND gate 36. The purpose of the measuring switch FET 34 is to turn the low side driver FET 28 into essentially a diode when the switch FET 34 is turned on. When the measuring switch FET 34 conducts, it shorts the gate and drain of the low side driver 28, effectively making driver FET 28 a diode. 
     The current mirror circuit 14 preferably comprises a pair of bipolar transistors 38 and 40. The collector of transistor 38 is connected to the drains of each of the sense FET 32. The emitters of transistors 38 and 40 are connected through series resistors to a voltage source V which may be any appropriate supply value such as 12, 5, or 3 volts, depending on the particular application. The collector of the other transistor 40 is connected to a programmable current threshold 18 and to an increment sequencer 42 and a timer 44. The drain of a PMOS transistor switch 46 is also connected to the bases of the transistors 38 and 40. The gate of the PMOS transistor 46 is connected to an inductive control line 50 which is in turn connected to the timer 44 and to one side of each of the AND gates 36A, B, C. 
     During normal motor operation, control line 50 is low. Therefore the AND gates 36 are disabled. A phase output combination from the sequencer 42 is fed to the gates of transistors 26 and 28 in a conventional manner to maintain motor rotation. However, prior to motor startup, the exact position of the motor rotor is not known. Therefore, upon receipt of a motor start signal, the control line 50 is turned on or made high for one complete sequence of phase energizations. When this happens, an enable signal is fed to each of the AND gates 36A, B, and C. Simultaneously, the timer 44 begins counting and sends a signal through the select register 52 to the sequencer 42, which issues a &#34;1&#34; to the high side driver and the AND gate for the low side driver, i.e. one of the winding combinations such as AL,BH. Thus, in this example, the AND gate, 36A turns on. This causes Measuring FET 34A to conduct, shorting the gate and drain of low side driver FET 28A. This in turn causes low side driver FET 28A to act as a diode. The control for high side driver FET 26B goes high causing FET 26B to turn on, forming a current path from Vspin, through high side driver 26B, through winding B to node 24 and through winding A, through low side driver 28A to ground or common 30. As current builds up through this path between two voltage sources, i.e. common 30 and Vspin 27 caused by the reluctance generated from the adjacent rotor pole s permanent magnetic flux, current also flows through sense FET 32A to the collector of transistor 38 in the mirror circuit. The amount of current flowing through the sense FET 32A is proportional to the current through the low side driver FET 28A according to the size ratio between these FETs. 
     Preferably the sense FET current is very low compared to the drive current. The size, or gain ratio of FET 32 to FET 28 is 1/x where 100&lt;x&lt;5000 and the ratio is preferably about 2000. Thus, for example, for a driver current of 20 milliamps, if the ratio is 1/2000, or 0.0005, the sense FET current will be 10 microamps. Thus the power used in determining the proper phase sequencing is very small. 
     The sense FET current feeds into the collector of transistor 38, which is one side of the mirror circuit 14. A threshold current 18 is sensed on the other side of this circuit. When the sense current matches the current threshold, an increment output high signal is sent on line 54 to the timer 44 to stop counting and to the sequencer 42 to increment the sequencer to the next phase combination. When the timer 44 is stopped by receipt of this signal, the timer 44 sends the accumulated time value in the timer to the select register 52 if the accumulated time value is greater than the resident contents of the select register 52. 
     At the same time, the sequencer advances to the next phase winding combination, for example AH,CL and the process just described repeats, as follows. Now the high side FET 26A control goes high, causing FET 26A to conduct, and AND gate 36C receives a high and turns on. This in turn causes measuring FET 34C to conduct, shorting the gate and drain of low side driver FET 28C. This in turn causes the low side driver FET 28C to act as a diode. The control for high side driver FET 26A goes high causing FET 26A to turn on, forming a current path from Vspin through high side driver 26A, through winding A to node 24 and through winding C, through low side driver 28C to ground or common 30. As current builds up through this path because of the reluctance due to the adjacent permanent magnet flux, current also flows through sense FET 32C to the collector of transistor 38. The amount of current flowing through the sense FET 32C is proportional to the current through the low side driver FET 28C according to the size ratio between these FETs. When the sense current matches the current threshold, an increment signal is sent on line 54 to the timer 44 to stop counting and to the sequencer 42 to again increment the sequencer 42 to the next phase combination. When the timer 44 is stopped, the timer 44 sends the accumulated time value to the select register 52 if the accumulated time value is greater than the current contents of the select register 52. 
     Once the prestart phase selection process has gone through the six phase combinations, the control line 50 goes low, effectively removing the sense FETs 32 and the current mirror 14 from the power circuit 20 and the increment sequencer 42 begins sequencing for motor startup using the phase combination last resident in the register 52 as the starting combination. 
     Second Embodiment 
     Referring now to FIG. 2, a second embodiment of the circuit in accordance with the present invention is shown. The circuit 110 drives a &#34;Y&#34; connected three phase dc motor stator 12 and has a mirror circuit 14 connected to a timer 44, to a current threshold 18 and to a three phase driver circuit 120. 
     The driver circuit 120 is composed of three essentially identical phase drivers 120A, 120B, and 120C, each one connected to one end 122 of each winding A, B, or C. The other end of each winding A, B and C is joined together at node 124. The following description is for the driver circuit 120A connected to winding A and applies equally to each of the other two transistor driver circuits shown. Each driver circuit has a high side driver FET 126 which has its drain terminal connected to a voltage supply 127 (Vspin) and its source terminal connected to a free end 122 of one of the windings A, B, or C, in this case, winding A. The control or gate terminal of the high side driver FET 126 is also connected to the control or gate terminal of a sense FET 140A and to the source terminal of a measuring switch FET 138A. The gate of the high side driver 126A is connected to the sequencer 42 during normal motor run operation in a conventional manner as indicated by the dashed line AH. The source of the sense FET 140A is connected to the free end 122A of winding A and thus the source of the high side driver 126A. The drain of the sense FET 140A is connected to the collector of a bipolar transistor 38 in the mirror circuit 14 and to the drain of the other two sense FETs 140. 
     The driver circuit 120A also has a low side driver FET 128A having its source terminal connected to a common voltage reference 30 and its drain terminal connected to the winding end 122A and thus to the source terminal of the high side driver FET 126A. The gate terminal of the low side driver FET 128A is connected to the sequencer 42. 
     The measuring switch FET 138A has its source connected to the gates of the high side driver FET 126A and its sense FET 140A. The measuring switch FET 138A drain is connected to the drain of the high side driver FET 126A and thus to Vspin 127. The gate of the measuring switch FET 138A is connected to the output of an AND gate 142A. The purpose of the measuring switch FET 138A is to turn the high side driver FET 126A into essentially a diode when the switch FET 138A is turned on during inductive sensing. When the measuring switch FET 138A conducts, it shorts the gate and drain of the high side driver 126A, effectively making driver FET 126A a diode. 
     The current mirror circuit 14 is the same as above described with reference to the first embodiment and preferably comprises a pair of bipolar transistors 38 and 40. The collector of transistor 38 is connected to the drains of each of the driver circuits 120. The emitters of transistors 38 and 40 are connected through series resistors to a voltage source V which may be any appropriate supply value higher than Vspin. The collector of the other transistor 40 is connected to a programmable current threshold 18 and to an increment sequencer 42 and a timer 44. The drain of a PMOS transistor switch 46 is also connected to the bases of the transistors 38 and 40. The gate of the PMOS transistor 46 is connected to an inductive control line 50 which is in turn connected to the timer 44 and to one side of each of the AND gates 142A, B, C. 
     During normal motor operation, control line 50 is low, and thus the AND gates 142 outputs are low and thus measuring switches 138 are non-functional. Again, prior to motor startup, the exact position of the motor rotor is not known. Therefore, upon receipt of a motor start signal, the control line 50 is turned on or made high. When this happens, an enable signal is fed to each of the AND gates 142A, B, and C. Simultaneously, the timer 44 begins counting and sends a signal through the select register 52 to the sequencer 42, which issues a &#34;1&#34; to one of the low side drivers 128 and the AND gate 142 for one of the high side drivers, i.e. one of the winding combinations such as AL,BH. Thus in this example winding combination, the AND gate, 142B turns on. This causes Measuring FET 138B to conduct, shorting the gate and drain of high side driver FET 126B. This in turn causes the high side driver FET 126B to act as a diode. The control for low side driver FET 128A goes high causing FET 128B to turn on, forming a current path from Vspin, through high side driver 126A, through winding B to node 124 and through winding A, through low side driver 128A to ground or common 30. As current builds up through this path between the two voltage sources, i.e. common 30 and Vspin 127 caused by the reluctance generated from the adjacent rotor pole s permanent magnetic flux, current also flows through sense FET 140B to the collector of transistor 38 in the mirror circuit 14. The amount of current flowing through the sense FET 140B is proportional to the current through the high side driver FET 126B according to the size ratio between these FETs. 
     Preferably the sense FET current is very low compared to the drive current. The size, or gain ratio of FET 140 to FET 126 is 1/x where 100&lt;x&lt;5000 and the ratio is preferably about 2000. Thus, for example, for a driver current of 20 milliamps, if the ratio is 1/2000, or 0.0005, the sense FET current will be 10 microamps. Thus the power used in determining the proper phase sequencing is very small. 
     The sense FET current feeds into the collector of transistor 38, one side of the mirror circuit 14 as previously described with reference to the first embodiment. A threshold current 18 is sensed on the other side of this circuit. When the sense current matches the current threshold, an increment output high signal is sent on line 54 to the timer 44 to stop counting and to the sequencer to increment the sequencer to the next phase combination. When the timer 44 is stopped by receipt of this signal, the timer 44 sends the accumulated time value in the timer to the select register 52 if the accumulated time value is greater than the resident contents of the select register 52. 
     At the same time, the sequencer advances to the next phase winding combination, for example AH,CL and the process just described repeats for this combination, as follows. Now the low side FET 128C control goes high, causing FET 128C to conduct. The AND gate 142A turns on since the AND gate is enabled, causing the measuring FET 138A to conduct, shorting the gate and drain of high side driver FET 126A. This in turn causes the high side driver FET 126A to act as a diode. This forms a current path from Vspin through high side driver 126A, through winding A to node 124 and through winding C, through low side driver 128C to ground or common 30. As current builds up through this path because of the reluctance due to the adjacent permanent magnet flux, current also flows through sense FET 140A to the collector of transistor 38. The amount of current flowing through the sense FET 140A is proportional to the current through the high side driver FET 126A according to the size ratio between these FETs. When the sense current matches the current threshold, an increment signal is sent on line 54 to the timer 44 to stop counting and to the sequencer 42 to again increment the sequencer 42 to the next phase combination. When the timer 44 is stopped, the timer 44 sends the accumulated time value to the select register 52 if the accumulated time value is greater than the current contents of the select register 52. 
     Once the prestart phase selection process has gone through all of the six phase combinations, the control line 50 goes low, effectively removing the sense FETs 140 and the current mirror 14 from the power circuit 120 and the increment sequencer 42 begins sequencing for motor startup using the phase combination last resident in the register 52 as the starting combination. 
     The present invention may be practiced otherwise than as specifically described above. Many changes, alternatives, variations, and equivalents to the various structures shown and described will be apparent to one skilled in the art. For example, the sense FETs need not be all on low or high side drivers. They may be mixed. NMOS and PMOS devices may be substituted in a manner well known in the art. Accordingly, the present invention is not intended to be limited to the particular embodiments illustrated but is intended to cover all such alternatives, modifications, and equivalents as may be included within the spirit and broad scope of the invention as defined by the following claims. All patents, patent applications, and printed publications referred to herein are hereby incorporated by reference in their entirety.