Abstract:
An integrated circuit device controls power up of an external device used for sensing a process variable independently of whether the integrated circuit device is in a low power sleep mode. Once the external device becomes operational the integrated device, even when still in the low power sleep mode, samples the process variable status of the external device. Low power timing circuits operational during the low power sleep mode control the power up of the external device and sampling of the process variable status thereof. After the sample of the process variable status is taken, the integrated circuit device may be brought out of the low power sleep mode to an operational mode when appropriate as determined from the sampled process variable status.

Description:
RELATED PATENT APPLICATION 
     This application claims priority to commonly owned U.S. Provisional Patent Application Ser. No. 61/296,947; filed Jan. 21, 2010; entitled “External Device Power Control During Low Power Sleep Mode Without Central Processing Unit Intervention,” by Michael Simmons and Michael Catherwood, and is hereby incorporated by reference herein for all purposes. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to integrated circuit devices, and more particularly, to power savings of integrated circuit devices when in low power sleep modes. 
     BACKGROUND 
     In current low power modes (Sleep, Deep Sleep, etc.), there are various ways of waking up an integrated circuit device from a low power mode. One such way is through the use an external “wake” signal (often a re-purposed interrupt input). However, this requires that the source of the wake signal be alive while the integrated circuit device is in its low power mode, resulting in an overall system power consumption that is larger than required. 
     SUMMARY 
     The aforementioned problems are solved, and other and further benefits are achieved by periodically waking up an external device(s) without the intervention of main logic circuits, e.g., processor, that may be in a low power, deep sleep mode. This feature may be accomplished with for example, but not limited to, existing low power mode timers, e.g., real time clock and calendar (RTCC), watchdog timer (WDT), Deep Sleep WDT, general purpose timer, etc.) using a simplified 2-channel pulse width modulation (PWM) like function. As such a periodic power-up (wake-up) can be provided to an external device, e.g., temperature sensor, wait for it to start up and become stable, sample its “wake” output signal, and then power it back down, all without ever requiring the main circuit logic in a digital device to leave a low power mode. 
     According to a specific example embodiment of this disclosure, an integrated circuit digital device determines control and status determination of an external device independently of when the digital device is in a low power sleep mode, comprises: a digital processor having a wake-up input, the wake-up input wakes up the digital processor from a sleep mode to an operational mode when at a first logic level is applied thereto and does not wake up the digital processor when a second logic level is applied thereto; a power-up timer coupled to an external device, wherein the power-up timer causes the external device to go into an operational mode during a first time period; a sample timer, wherein the sample timer causes an output from the external device to be applied to the wake-up input of the processor during a second time period, wherein during the second time period if the output of the external device is at the first logic level then the processor wakes up to the operational mode; and if the output of the external device is at the second logic level then the processor remains in the sleep mode. 
     According to another specific example embodiment of this disclosure, an integrated circuit mixed signal device determines control and status of an external device independently of when the mixed signal device is in a low power sleep mode, comprises: a digital processor having a wake-up input, the wake-up input wakes up the digital processor from a sleep mode to an operational mode when at a first logic level is applied thereto and does not wake up the digital processor when a second logic level is applied thereto; a comparator having a first input coupled to an analog output of an external device; a voltage reference having a reference voltage output connected to a second input of the comparator; a power-up timer coupled to the external device, wherein the power-up timer causes the external device to go into an operational mode during a first time period; a sample timer, wherein the sample timer causes an output from the comparator to be applied to the wake-up input of the processor during a second time period, wherein during the second time period if the analog output of the external device is greater than the reference voltage output then the processor wakes up to the operational mode; and if the analog output of the external device is equal to or less than the reference voltage output then the processor remains in the sleep mode. 
     According to yet another specific example embodiment of this disclosure, a method of conserving power and monitoring status of an external device without having to wake up digital circuits of an integrated circuit device from a low power sleep mode, comprises the steps of: applying power to an external device during a first time period from a power-up timer; comparing an output from the external device with a reference value during a second time period from a sample timer, the second time period beginning after the first time period has started; wherein during the second time period if the output of the external device is greater than the reference value then digital circuits of an integrated circuit device wake up to an operational mode; and if the output of the external device is equal to or less than the reference value then the digital circuits of an integrated circuit remain in a sleep mode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the present disclosure thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein: 
         FIG. 1  illustrates a schematic block diagram of a prior technology digital device having a sleep mode and an external device coupled to and adapted for waking up the digital device, and a timing diagram of the external device operation; 
         FIG. 2  illustrates a schematic block diagram of an integrated circuit digital device having a sleep mode, power-up and sample timers, and an external device whose operational on-time and event monitoring are controlled up the digital device, and a timing diagram of the operation thereof, according to a specific example embodiment of this disclosure; 
         FIG. 3  illustrates a schematic block diagram of a integrated circuit mixed signal device having a sleep mode, power-up and sample timers, and an external device whose operational on-time and event monitoring are controlled up the mixed signal device, and a timing diagram of the operation thereof, according to another specific example embodiment of this disclosure; and 
         FIG. 4  illustrates a schematic block diagram of the circuits of  FIGS. 2 and 3  having a power interposing relay controlled by the integrated circuit device and supplying power to the external device, according to the specific example embodiments of this disclosure. 
     
    
    
     While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims. 
     DETAILED DESCRIPTION 
     Referring now to the drawings, the details of a example embodiment is schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix. 
     Referring to  FIG. 1 , depicted is a schematic block diagram of a prior technology digital device having a sleep mode and an external device coupled to and adapted for waking up the digital device, and a timing diagram of the external device operation. A digital device  102  comprises a processor  104 , a memory  106  coupled to the processor  104 , and a low power timer  108 , e.g., watchdog timer (WDT), real time clock and calendar (RTCC), etc. An external device  112  is coupled to the digital device  102  through an external input node  110 , on an integrated circuit package (not shown). 
     The digital device  102  may be returned to an operational mode from a sleep mode by the low power timer  108  and/or a logic level change at the input node  110  from the external device  112 . Either way, the digital device  102  will go back to the higher power usage operational mode. When the low power timer  108  is used to wake up the processor  104  and other necessary logic (e.g., memory  106 ), the processor  104  will sample the logic state of the node  110  to see if an event has been detected or occurred from the external device output logic state, e.g., temperature, pressure, moisture, pH, current, voltage, etc., sensor. Alternately, the processor  104 , et al., may remain in a low power sleep mode until directly awoken by a logic state change at the node  110  from the output of the external device  112 , as shown in the timing diagram (b) of  FIG. 1 . 
     However, using either way of waking up the processor  104  still requires that the external device  112  be kept continuously in an operational power consuming state. Some external devices  112  that may be used as sensors need only indicate monitored data and/or status periodically, e.g., once a minute or longer, etc. Therefore, maintaining operational status of the external device  112  continuously is most wasteful of power consumption. In battery powered applications, power consumption is critical. 
     Referring to  FIG. 2 , depicted is a schematic block diagram of an integrated circuit digital device having a sleep mode, power-up and sample timers, and an external device whose operational on-time and event monitoring are controlled up the digital device, and a timing diagram of the operation thereof, according to a specific example embodiment of this disclosure. A better way of conserving power with the external device  112  is to put it into a sleep mode or turn off operation of it completely, e.g., remove power therefrom, then only periodically activate the external device  112  when appropriate, and thereafter determine if an event monitored by the external device  112  has occurred. This very way is accomplished by the digital device  202  shown in  FIG. 2 . 
     The digital device  202  comprises a digital processor  204 , a memory  206  coupled to the digital processor  204 , a power-up timer  224 , a sample timer  214 , and an AND gate  220 . Operationally, the power-up timer  224  will activate (turn on) the external device  112  by pulling the node  216  to a logic low (V SS ) so that power is applied to the external device  112 . Equally effective would be to apply power (V DD ) directly from the node  216  to the V DD  node of the external device  112 . 
     Once the external device  112  has been powered up, it will do whatever it is intended to do, e.g., measure a process variable: temperature, pressure, vibration, etc. Then a sample of the output state of the external device  112  may be taken with the sample timer  214  once the external device  112  has become fully operational (e.g., after stabilizing, self calibrating, etc.). When this sample is taken, if the output of the external device  112  requires that the digital processor  204  be brought back to an operational mode, then a wake-up signal  212  from the AND gate  220  will be applied to the processor wake-up input, e.g., an interrupt input. The power-up timer  224 , the sample timer  214  and the AND gate  220  may operate independently from any other circuits of the digital device  202  that are in the sleep mode. In addition, the power-up timer  224 , the sample timer  214  and the AND gate  220  may be ultra-low power circuits adapted to operate with a minimum amount of power. The digital device  202  may be a microcontroller, a microprocessor, a digital signal processor, an application specific integrated circuit (ASIC), a programmable logic or gate array, etc. 
     The timing diagram (b) shown in  FIG. 2  depicts the aforementioned sequence of events used for both conserving power of the external device  112  and causing a wake-up of the digital device  202  when appropriate. Power  216  is applied to the external device  112 . Then if an event  210  occurs during the time of the sample  214 , a wake-up signal  212  is applied to an input of the digital processor  204 , and the event so detected is processed according to the software/firmware program in the memory  206 . 
     It is contemplated and within the scope of this disclosure that the sample timer  214  may contemporaneously go active as the power  216  to applied to the external device  112 . If there is no settling or stabilization time required by the external device  112 , e.g., a dry contact switch (limit, pressure, etc.) then delay of the sample timer  214  may not be necessary. Also, there may be an integration or multiple samples taken by the processor  204  such that delayed assertion of the sample timer  214  after initial activation of the external device  112  is not necessary. 
     Referring to  FIG. 3 , depicted is a schematic block diagram of an integrated circuit mixed signal device having a sleep mode, power-up and sample timers, and an external device whose operational on-time and event monitoring are controlled up the mixed signal device, and a timing diagram of the operation thereof, according to another specific example embodiment of this disclosure. A better way of conserving power with the external device  312  is to put it into a sleep mode or turn off operation of it completely, e.g., remove power therefrom, then only periodically activate the external device  312  when appropriate, and thereafter determine if an event monitored by the external device  312  has occurred. This very way is accomplished by the mixed signal device  302  shown in  FIG. 3 . 
     The mixed signal device  302  comprises a digital processor  204 , a memory  206  coupled to the digital processor  204 , a power-up control timer  224 , a sample timer  214 , a comparator  320  and a voltage reference  322 . Operationally, the power-up timer  224  will activate (turn on) the external device  312  by pulling the node  216  to a logic low (V SS ) so that power is applied to the external device  312 . Equally effective would be to apply power (V DD ) directly from the node  216  to the Vdd node of the external device  312 . Optionally, the power-up timer  224  may apply operating voltage to the comparator  320  and/or the voltage reference  322  for a further savings in power usage. The analog output of the external device  312  may have any number of analog values representative of what is being measured. The comparator  320  will compare the analog value (e.g., voltage) from the external device  312  to a voltage from the voltage reference  322 . The reference voltage from the voltage reference  322  may be programmable (not shown) through the digital processor  204 . 
     Once the external device  312  has been powered up, it will do whatever it is intended to do, e.g., measure a process variable: temperature, pressure, vibration, etc. Then a sample of the analog output of the external device  312  may be compared to the reference voltage from the voltage reference  322  with the comparator  320 . An output of the comparator  320  is then enabled by the sample timer  214  once the external device  312  has become fully operational (e.g., after stabilizing, self calibrating, etc.). When this sample is taken, if the sampled analog value from the output of the external device  312  is greater than the reference voltage from the voltage reference  322 , then the digital processor  204  may be brought back to an operational mode. A wake-up signal  212  from the comparator  320  will be applied to the processor wake-up input, e.g., an interrupt input. The power-up timer  224  and the sample timer  214  may operate independently from any other circuits of the mixed signal device  302  that are in the sleep mode. In addition, the power-up timer  224 , the sample timer  214 , the voltage reference  322  and/or the comparator  320  may be ultra-low power circuits adapted to operate with a minimum amount of power. 
     The mixed signal device  302  may be a microcontroller, a microprocessor, a digital signal processor, an application specific integrated circuit (ASIC), a programmable logic or gate array, a digital signal processor (DSP), etc., having both digital and analog circuits. 
     The timing diagram (b) shown in  FIG. 3  depicts the aforementioned sequence of events used for both conserving power of the external device and causing a wake-up of the digital device when appropriate. Power  216  is first applied to the external device  312 . Then an event  210  may occur at the output of the external device  312  during a time of the sample  214 . If an event  210  occurs during the time of the sample  214 , then a wake-up signal  212  is applied to an input of the digital processor  204  and the event so detected is processed according to the software/firmware program in the memory  206 . 
     It is contemplated and within the scope of this disclosure that the sample timer  214  may contemporaneously go active as the power  316  to applied to the external device  312 . For example, integration or multiple samples taken by the processor  204  would not require delayed assertion of the sample timer  214  after activation of the external device  312 . 
     Referring to  FIG. 4 , depicted is a schematic block diagram of the circuits of  FIGS. 2 and 3  having a power interposing relay controlled by the integrated circuit device and supplying power to the external device, according to the specific example embodiments of this disclosure. When the external device  312  requires a power draw that exceeds the power handling capabilities of the device  302  ( 202 ) then a power interposing relay  422  may be used to supply power, V DD , to the external device  312 . The power interposing relay  422  may be an electromechanical or electronic switch, e.g., power transistor. 
     While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.