Abstract:
A storage node structure includes a substrate having thereon a conductive block region; an etching stop layer covering the conductive block region; a conductive layer penetrating the etching stop layer and electrically connecting the conductive block region; an annular shaped conductive spacer on sidewall of the conductive layer, wherein the annular shaped conductive spacer is disposed on the etching stop layer and wherein the annular shaped conductive spacer and the conductive layer constitute a storage node pedestal; and an upper node portion stacked on the storage node pedestal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to a storage node structure of a stack capacitor and fabrication method thereof. 
     2. Description of the Prior Art 
     It has been the trend to scale down the sizes of memory cells to increase the integration level and thus memory capacity of a DRAM chip in the semiconductor industry. As the sizes of DRAM devices are decreased, the capacity of a capacitor in the DRAM devices is correspondingly decreased. One approach to increasing capacity of the capacitor involves increasing the surface area of the storage node. As known in the art, the surface area of a storage node in a capacitor-over-bit-line (COB) structure is mostly increased by increasing the height as the design rule limits the horizontal dimension of the storage node. However, increasing the height of the storage node causes structure instability of the storage node, which is the cause of device failure due to two-bit or multi-bit failure during DRAM operation. 
       FIGS. 1-5  are schematic, cross-sectional diagrams showing a conventional method for fabricating a storage node of a crown-type stacked cell capacitor. As shown in  FIG. 1 , a substrate  10  such as a silicon substrate having thereon conductive blocks  12   a  and  12   b  is provided. A dielectric layer  14  such as silicon nitride and a dielectric layer  16  such as undoped silicate glass (USG) are deposited over the substrate  10 . 
     As shown in  FIG. 2 , a conventional lithographic process and a dry etching process are carried out to define high aspect ratio openings  18   a  and  18   b  in the dielectric layers  14  and  16 . Subsequently, a cleaning process may be performed to remove the etching byproducts or particles from the surfaces of the substrate  10  and from the interior surfaces of the openings  18   a  and  18   b.    
     As shown in  FIG. 3 , a chemical vapor deposition (CVD) process is carried out to form a conformal silicon layer  22  on the surface of the dielectric layer  16  and on the interior surfaces of the openings  18   a  and  18   b . The silicon layer  22  may be doped polysilicon. 
     As shown in  FIG. 4 , a planarization process such as chemical mechanical polishing (CMP) is performed to selectively remove the silicon layer  22  from the surface of the dielectric layer  16 , while leaving the silicon layer  22  on the interior surfaces of the openings  18   a  and  18   b  intact. 
     Subsequently, as shown in  FIG. 5 , a wet etching process involving the use of HF/NH 4 F chemistry or Buffer Oxide Etcher (BOE) is performed to remove the dielectric layer  16 , thereby forming storage nodes  30   a  and  30   b . Typically, the height H of each of the storage nodes  30   a  and  30   b  is approximately equal to the depth of the openings  18   a  and  18   b , which is normally 1.6-1.7 micrometers. 
     One drawback of the above-mentioned prior art method is that when forming the high aspect ratio openings  18   a  and  18   b  it is difficult to obtain a straight sidewall profile. The tapered sidewall profile of the high aspect ratio openings  18   a  and  18   b  leads to small bottom critical dimension A. The small bottom critical dimension A results in so-called storage node bridge phenomenon during subsequent cleaning or drying processes. 
     SUMMARY OF THE INVENTION 
     Therefore, it is one objective to provide an improved storage node structure of a stack capacitor in order to avoid the aforementioned storage node bridge phenomenon. 
     It is another objective to provide a method for fabricating a storage node structure of a stack capacitor to solve the above-mentioned prior art problems. 
     To these ends, according to one aspect of the present invention, there is provided a storage node structure including a substrate having thereon at least one conductive block; an etching stop layer covering the conductive block; a conductive later penetrating through the etching stop layer and electrically connecting with the conductive block; an annular shaped conductive spacer on sidewall of the conductive layer, wherein the conductive layer and the annular shaped conductive spacer constitute a storage node pedestal; and an upper node portion stacked on the storage node pedestal. 
     In one aspect, a method for fabricating a storage node structure of a stack capacitor includes providing a substrate having thereon a conductive block, an etching stop layer covering the conductive layer and a first dielectric layer covering the etching stop layer; etching a first opening into the first dielectric layer and the etching stop layer, thereby exposing a top surface of the conductive block; forming a first conductive layer in the first opening; removing the first dielectric layer; forming an annular shaped conductive spacer on sidewall of the first conductive layer, wherein the annular shaped conductive spacer and the first conductive layer constitute a storage node pedestal; and forming an upper node portion on the storage node pedestal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-5  are schematic, cross-sectional diagrams showing a conventional method for fabricating a storage node of a crown-type stacked cell capacitor. 
         FIG. 6  to  FIG. 14  are schematic, cross-sectional diagrams illustrating a method for fabricating a storage node structure of a stack capacitor in accordance with one embodiment of this invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 6  to  FIG. 14 .  FIG. 6  to  FIG. 14  are schematic, cross-sectional diagrams illustrating a method for fabricating a storage node structure of a stack capacitor in accordance with one embodiment of this invention. As shown in  FIG. 6 , a substrate  100  such as a silicon substrate is provided. A conductive block  112   a  and a conductive block  112   b  are formed in the substrate  100 . A dielectric layer  114  such as silicon nitride is deposited on the substrate  100  and covers the conductive block  112   a  and conductive block  112   b . The dielectric layer  114  acts as an etching stop layer. A dielectric layer  122  such as USG or BSG is then formed on the dielectric layer  114 . According to the embodiment of this invention, the dielectric layer  122  has a thickness of about 0.6-0.8 μm. 
     As shown in  FIG. 7 , a conventional lithographic process and a dry etching process are carried out to define openings  128   a  and  128   b  in the dielectric layers  122  and  114 . The openings  128   a  and  128   b  expose a top surface of the conductive block  112   a  and a top surface of the conductive block  112   b  respectively. Subsequently, a cleaning process may be performed to remove the etching byproducts or particles from the surfaces of the substrate  100  and from the interior surfaces of. Since the dielectric layer  122  is not thick compared to the prior art, after etching the openings  128   a  and  128   b , both the openings  128   a  and  128   b  have a straight vertical sidewall profile. 
     As shown in  FIG. 8 , a chemical vapor deposition (CVD) process and chemical mechanical polishing (CMP) are carried out to fill the openings  128   a  and  128   b  with a silicon layer  130   a  and a silicon layer  130   b  respectively. The silicon layers  130   a  and  130   b  may be doped polysilicon. The silicon layers  130   a  and  130   b  are electrically connected with the underlying conductive blocks  112   a  and  112   b  respectively. 
     As shown in  FIG. 9 , after the formation of the silicon layers  130   a  and  130   b , the dielectric layer  122  is completely removed from surface of the substrate  100 , thereby exposing sidewalls of the silicon layers  130   a  and  130   b . The dielectric layer  122  may be removed by conventional etching methods such as dry etching processes. Thereafter, a conformal conductive layer  140  such as metal is deposited on the top surfaces and the sidewalls of the silicon layers  130   a  and  130   b  and on the surface of the dielectric layer  114 . According to the embodiment of this invention, the conductive layer  140  is composed of metal that has better adhesion property with silicon nitride, preferably, TiN or Ti/TiN. 
     As shown in  FIG. 10 , a dry etching process is carried out to anisotropically etch the conductive layer  140 , thereby forming annular shaped conductive spacers  142   a  and  142   b  on sidewalls of the silicon layers  130   a  and  130   b  respectively. According to the embodiment of this invention, the conductive spacers  142   a  and the silicon layer  130   a  constitute a storage node pedestal  150   a , and the conductive spacers  142   b  and the silicon layer  130   b  constitute a storage node pedestal  150   b . The storage node pedestals  150   a  and  150   b  have a height of about 0.6-0.8 μm. 
     As shown in  FIG. 11 , a CVD process is performed to blanketly deposit a dielectric layer  152  such as USG or BSG over the substrate  100 . Subsequently, a CMP process is performed to planarize the dielectric layer  152  and expose a top surface of the storage node pedestal  150   a  and a top surface of the storage node pedestal  150   b . At this point, the remanent dielectric layer  152  fills the spacing between the storage node pedestals  150   a  and  150   b . It is understood that the CMP process used to planarize the dielectric layer  152  may be omitted or replaced by other suitable planarization means. 
     As shown in  FIG. 12 , a CVD process is carried out to blanket deposit a dielectric layer  162  such as USG or BSG over the substrate  100 . According to the embodiment of this invention, the dielectric layer  162  has a thickness of about 0.6-0.8 μm. 
     As shown in  FIG. 13 , a lithographic process and a dry etching process are performed to etch openings  168   a  and  168   b  into the dielectric layer  162  to expose the top surface of the storage node pedestal  150   a  and top surface of the storage node pedestal  150   b  respectively. A cleaning process may be performed to remove the etching byproducts or particles from the surfaces of the substrate  100  and from the interior surfaces of the openings  168   a  and  168   b . Likewise, since the dielectric layer  162  is not very thick, both the openings  168   a  and  168   b  have a straight vertical sidewall profile. Subsequently, a conformal metal layer  170  such as TiN or TaN is deposited on the interior surfaces of the openings  168   a  and  168   b  and on the top surface of the dielectric layer  162 . 
     As shown in  FIG. 14 , a CMP process is performed to remove a portion of the metal layer  170  that is directly above the dielectric layer  162 , thereby exposing the top surface of the dielectric layer  162  and forming cylindrical upper node portion  172   a  and cylindrical upper node portion  172   b . The cylindrical upper node portion  172   a  and cylindrical upper node portion  172   b  respectively have a height of about 0.6-0.8 μm. After the CMP, an etching process such as a wet etching process is performed to completely remove the dielectric layers  162  and  152 , thereby exposing the sidewalls of the storage node pedestals  150   a  and  150   b . The cylindrical upper node portion  172   a  and the storage node pedestal  150   a  constitute a storage node structure  180   a  and the cylindrical upper node portion  172   b  and the storage node pedestal  150   b  constitute a storage node structure  180   b.    
     To sum up, the present invention provides an improved storage node structure of a stack capacitor that is capable of avoiding the storage node bridge phenomenon. The storage node pedestal having a relatively larger bottom critical dimension is first formed, then the cylindrical upper node portion is stacked directly on the storage node pedestal. The cylindrical upper node portion and the storage node pedestal constitute the storage node structure. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.