Abstract:
The subject of the present invention is a method for processing alerts by an avionic system FWS that makes it possible to optimize the processing of these alerts without unnecessarily consuming “processor time”. The method according to the invention is characterized in that it consists in having processed, on each processing cycle of the processor of the FWS, only the operations relating to alerts for which the result has been modified since the preceding processing cycle.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to an optimized task processing method and device for an FWS (Flight Warning System). 
       BACKGROUND ART 
       [0002]    In the current avionics systems for managing alerts and procedures, commonly called FWS, the consumption of “processor time” (processor occupancy time in processing these alerts) is the same whatever the number of alerts detected. The worst case (presence of a large number of alerts that are unchanged, but processed “without any data” by the processor) is repeated each time, and at the present time there is no solution to this problem. 
       SUMMARY OF THE INVENTION 
       [0003]    The subject of the present invention is a method for processing alerts by an avionic system FWS that makes it possible to optimize the processing of these alerts without unnecessarily consuming “processor time”. 
         [0004]    Also the subject of the present invention is a sequencing device for an aircraft FWS that enables this FWS to provide the same services as the known FWS systems in terms of alert detection latency, pilot action response latency, etc., or to improve them, while consuming as little processor time as possible and which is as inexpensive as possible. 
         [0005]    The method according to the invention is characterized in that it consists in having processed, on each processing cycle of the processor of the FWS, only the operations relating to alerts for which the result has been modified since the preceding processing cycle. 
         [0006]    According to a preferred implementation of the method of the invention, on each alert data refresh cycle, these refreshed data are compared to those received in the preceding cycle, and, if the refreshed datum is different from the preceding datum, a notification is sent to a sequencer which recovers, from a data library, the logical combinations needed to process this alert, performs the corresponding operations and transmits the result to an asynchronous alert display processor. 
         [0007]    The device according to the invention comprises an input data decoding module, a dynamic logic tasks sequencer, a library of logical combinations data, a module for storing results of the logic operations and an asynchronous display processor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The present invention will be better understood on reading the detailed description of an embodiment, taken as a nonlimiting example, and illustrated by the appended drawing, in which: 
           [0009]      FIG. 1  is a simplified block diagram of a system for implementing the method of the invention, 
           [0010]      FIG. 2  is a simplified diagram of an example of sequencing performed by the system according to the present invention, and 
           [0011]      FIG. 3  is a diagram of an exemplary logic circuit used in the system according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0012]    The system  1  diagrammatically represented in  FIG. 1  is intended for the processing of n different FWS alert processes, each of these processes implementing alert data (also here called parameters), of which some are common to at least some of the processes, and others are specific to particular processes. Thus, for example, as represented in  FIG. 1 , the first process PR 1  processes the parameters P 1 , P 2 , . . . Pp, and the process PRn of rank n processes the parameters P 1 , P 2 , . . . Pm. 
         [0013]    The system  1  mainly comprises, for each of the n processes PR 1  to PRn that it processes (in  FIG. 1 , the modules relating to each process are represented on the same row): an input data decoding module (respectively  2 . 1  to  2   n ) producing a state change indicator, a dynamic task sequencer working in real time (respectively  3 . 1  to  3 . n ), a database  4  which comprises a library of models of combinational logic functions, this database being common to all the processes. The sequencers extract therefrom each of the sets of logic functions  5  according to their needs (the database  4 , and the sets  5  form only a part of one of the rows of process processing elements, but have been represented for convenience between rows). This library includes the dependencies between the different parameters processed. Thus, for example, in the diagram of  FIG. 2 , described in more detail below, the dependencies of L 2  are L 3  and L 4 . The system  1  then comprises, for each process, a results storage module (respectively  6 . 1  to  6 . n ). The modules  6 . 1  to  6 . n  receive from the sequencers ( 3 . 1  to  3 . n  respectively) event information items denoted, for example, E 1 , E 2 , . . . , Ef for the process PR 1  and Eg, Eh, . . . , Ex for the process PRn. It should be noted that an event information item comprises its identifier and its value. For example, an alert arriving at an FWS comprises its identifier (of the type XXXX) and signals whether or not it is detected (value information for this alert). The outputs of the different modules (purely software)  6 . 1  to  6 . n  are linked to an aperiodically operating graphics processing computer  7 , which is linked to a display device (not represented) presenting the alerts to the pilot in graphical form. 
         [0014]    In detail, the functions handled by the different modules of the system  1  are as follows: 
         [0015]    Each of the modules  2 . 1  to  2 . n  comprises a memory for storing the alert data and compares its input data, refreshed on each FWS computation cycle, with the data received in the preceding FWS computation cycle. If the refreshed data is different from the preceding one, it sends a notification to the sequencer. 
         [0016]    Each sequencer  3 . 1  to  3 . n  successively carries out the following functions:
   a. On receiving a notification (corresponding to a refreshed datum differing from the preceding datum) from the decoding module which is linked to it, the sequencer extracts, from the library of the database  4 , the set  5  of the logic combinations to be recomputed (set relating to the functions involved in processing the modified alert), their associated priorities for processing by the sequencer and the group to which they belong, this group forming part of predefined groups in the database  4 .   b. It inserts into the list of logic combinations to be executed those that it has just recovered. The position of the logic combinations that have just been inserted into the list depends on their priority and on their sequencing group (these are combination groups having the same priority).   c. It starts executing the logic combination at the top of the list. If the result of this combination is different from the preceding one, the sequencer executes the same sequence as above (at the point a then at the point b) to add the set of logic combinations to be re-executed in the list of logic combinations to be sequenced, and does so for each of the groups, which constitutes a chaining of the execution activities by dependency of the inputs, that is to say that this addition of logic combination happens if, and only if, the combination concerned is not already present in the list.   d. It positions the result of the executions of the logic combinations in the corresponding result module.   
 
         [0021]    A highly simplified example of sequencing is described below with reference to the diagram of  FIG. 2 , in the case where the parameter P 2  of the pathway of the process PR 1  is modified. The different logic combinations implemented are denoted L 1  to L 6 . Even though, to simplify the description, logic gates have been chosen here (in the case of an FWS, such logic functions constitute the great majority of the computation means, but it will be obvious to those skilled in the art how to generalize this reasoning), these logic combinations may be of different sorts: they may rely on real numbers, integers, etc., and be implemented by latches, confirmative circuits (in the latter case, it is obvious that an event must be added which forces the computation of these complex gates), etc. 
         [0022]    The successive steps of this sequencing are:
   1. Step 1
       a. substep 1a: L 2  is extracted from the logic combinations model of the library of the database  4 ,   b. substep 1b: L 2  is added to the list of the logic combinations to be processed sequentially,   c. substep 1c: L 2  is executed (at the top of the list) and it is assumed that the result of this computation is different from the preceding one (the sequencer comprises, like each decoding module, a memory for storing the preceding result)   
       2. Step 2
       a. L 3  and L 4  are extracted from the library of the database  4 ,   b. L 3  and L 4  are added to the list, one behind the other because it is assumed that they are of the same priority and therefore in the same sequencing group   c. L 3  is executed and the result is different from the preceding one.   
       3. Step 3
       a. L 6  is extracted from the library  4 ,   b. L 6  is added to this list, behind L 4  because it is of lower priority.   c. L 4  is executed and the result is different from the preceding one.   
       4. Step 4
       a. L 5  is extracted from the library  4 .   b. L 5  is added to the list, in front of L 6  because it is of higher priority.   c. L 5  is executed and the result is different from the preceding one.   
         5 . Step 4
       a. L 6  is extracted from the library  4 .   b. L 6  is added to the list, the list is not modified because L 6  is already in this list.   c. L 6  is executed and the result is different from the preceding one.   d. The result of L 6  is transmitted to the result module.       
 
         [0044]    If, for example, the parameter P 3  is modified, the sequencing described above becomes:
       a. L 2  is recomputed.   b. The result of L 2  is identical.   c. End of process.       
 
         [0048]    In this second case, a single logic combination has been recomputed instead of six (L 1 , L 2 , L 3 , L 4 , L 5  and L 6 ). 
         [0049]    Library of Logic Combination Models ( 4 ): 
         [0050]    The logic combination models, configurable on design (in the present case, the use of data flows is used to sequence the logic combinations), have, for each input datum, a list of informative triplets. Each triplet consists of:
       an identifier of the logic combination to be added to the processing list of the sequencer, because this combination depends on the result of the comparison of the input datum,   a sequencing priority value for this logic combination,   the group to which this logic combination belongs.       
 
         [0054]    Set of Logic Functions ( 5 ): 
         [0055]    The expression “logic functions” should be understood to mean functions that make it possible to produce different types of events:
       nominal change of operational state of the appliance (for example, entry into the approach phase towards an airport).   abnormal malfunction of greater or lesser gravity (for example, loss of an engine) having to be signalled either by the “flight warning” or by a “display unit” type equipment item.       
 
         [0058]    These events are defined as being the result of a combination of logic operations between one or more of the parameters output by the onboard equipment items or by the sensors of the aircraft.  FIG. 3  diagrammatically represents an example of a circuit  8  implementing an event-producing logic combination (AND logic gate). This circuit  8  comprises, at its input, two OR logic gates  9  and  10  each with two inputs, these inputs receiving, in this example, the parameters P 1  to P 4  respectively. The output of each of these two gates  9  and  10  is linked to an input of an OR logic gate  11 . At the output of the gate  11 , the event E 1  is collected. 
         [0059]    According to one embodiment of the invention, when the logic circuits use time-related conditions as confirmer that an alert has been taken into account, a modification is provided in order to ensure that the times are indeed observed because of the non-static sequencing of these logic combinations. The modification is, for example, one of the following two:
       modification of the library implementing the time cell. According to one implementation, the cell (synchronous) is called on each cycle and stores the expiry date of the confirmer in terms of number of cycles. In the case of an event scheduler, it is preferable to consider arming a confirmation “timer” implemented by a timer-type process A653, which is woken up on each timeout of the confirmer, and whose “handler” propagates the event by being inserted into the queue of the scheduler. The disarming of the timer is triggered by a reset event for the signal to be confirmed.   use of an account running counter to the OS (operating system) of the FWS.       
 
         [0062]    Result Modules ( 6 . 1  to  6 . n ): 
         [0063]    The aim of each of these modules, of buffer memory type, is to recover the results of the different dynamic sequencers in order to then supply them to the asynchronous process of the FWS responsible for graphics processing. 
         [0064]    It must be added that in the worst case (all the parameters are changed, all the alerts are lifted), all the logic functions are computed only once as is in a “conventional” FWS. The excess load in use of the processor linked to the decisions (“should I recompute a logic combination or not?”) is negligible compared to the time needed to compute all the logic combinations. 
         [0065]    Thus, by virtue of the invention, it is possible to have time allotted to the aperiodic process that is much smaller than that allotted in the conventional case and therefore processing time by the processor in rendering the same service is saved.