Abstract:
A mechanism for providing retention mode voltage to a memory storage array includes a resistor coupled between a power supply and a power rail of the storage array. The power rail may distribute an operating current to the bit cells of the storage array. The resistor may provide a path for current to the power rail from the power supply during operation in a retention mode. In addition, a switching device coupled between the power supply and the power rail, in parallel with the resistor, may convey operational current to the power rail from the power supply during operation in a normal mode.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    This disclosure relates to memories, and more particularly to retention mode voltage mechanisms. 
         [0003]    2. Description of the Related Art 
         [0004]    Many memory arrays suffer from the effects of current leakage. Typically, the array bit cells are the largest contributor to leakage. This may be attributed to the transistors that are connected in a cross-coupled inverter configuration in each of the many bit cells of an array. Typically the p-type transistors of each bit cell, when they are turned off, may leak to circuit ground through the conducting n-type transistor. One conventional way to reduce the leakage current of a given memory array is to lower the supply voltage to the array when the memory is not being used or when the device is in a low power or standby mode, for example. 
         [0005]    However, conventional techniques for supplying the voltage to the array have drawbacks. For example, one such conventional circuit is shown in  FIG. 1A . In  FIG. 1A , a memory circuit  10  is shown in which an n-type transistor T 1  is used to provide the retention mode supply voltage from the top level Vdd to the memory storage array  12 , while the p-type transistor T 2  provides the normal mode supply voltage from the top level Vdd to the memory storage array  12 . Thus, during a normal mode, transistor T 2  is conducting, and transistor T 1  is cut off. It is well known that p-type transistors are generally better suited to pass a higher voltage since there is no threshold voltage (V T ) drop from source to drain when the transistor is conducting. It is further well known that n-type transistors are better suited to providing a path to ground because there is a source to drain V T  voltage drop, which can be relatively large. Thus, during a low power or retention mode, transistor T 2  is cut off, and transistor T 1  is conducting. The retention voltage applied to the storage array  12  is Top Level Vdd−V T . This lower retention Vdd may reduce the leakage in the storage array  12 . If the retention voltage is much larger than V T , then this technique may work very well. However, many modern devices may have operating voltages that are close to the V T  of the transistor T 1 . Accordingly, as operating voltages, and thus the top level Vdd gets lower, the retention Vdd available to the storage array  12  may become too low for reliable operation using this technique. 
         [0006]    Another conventional circuit uses a p-type transistor to provide the top-level supply voltage to the storage array and is shown in  FIG. 1B . In  FIG. 1B , a memory circuit  20  is shown in which the top level Vdd is coupled to the storage array  12  through a p-type transistor T 3  and a second p-type transistor T 4  (which is typically bigger than T 3 ). 
         [0007]    As mentioned above, P-type transistors are generally better suited to pass a higher voltage since there is no V T  drop from source to drain when the transistor is conducting. Accordingly, during operation in a normal mode a gate voltage (e.g., zero volts) is provided to cause the transistor T 3  to operate in saturation. However, to obtain a voltage drop suitable for operation in retention mode, the gate voltage applied to transistor T 3  is adjusted to some voltage that is between zero and Vdd, for example, so that transistor T 3  operates in the linear region. In this mode, there is a source to drain voltage drop across transistor T 3 , which effectively lowers the voltage available at the storage array  12 . However, due to process and other variations, the gate voltage necessary to operate the transistor T 3  at the appropriate operating point can be difficult to obtain consistently. In many cases there is active control circuitry that monitors and maintains the retention voltage at the appropriate levels. This circuitry takes up valuable die space and uses power. In addition, in both  FIG. 1A  and  FIG. 1B , the retention transistors T 1  and T 3  require additional control wiring that must be routed. 
       SUMMARY OF THE EMBODIMENTS 
       [0008]    Various embodiments of a memory including a retention mode resistor are disclosed. Broadly speaking, a mechanism for providing retention mode voltage to a memory storage array is contemplated. Since storage arrays may have a large leakage current, it may be beneficial to reduce the voltage to the storage array when it is not in use. Thus during a low power mode, the voltage of the voltage supply coupled to the storage array is reduced to a retention voltage. To provide the retention voltage, a resistor is coupled between the power supply an the storage array power rail in a pull up configuration. During normal operation a switching device may be shunted across the resistor to provide operation current to the storage array. 
         [0009]    In one embodiment, a memory includes a storage array including a number of bit cells and a power rail configured to distribute an operating current to the bit cells. The memory also includes a resistor coupled between a power supply and the power rail. The resistor may provide a path for current to the power rail from the power supply during operation in a retention mode. In addition, a switching device such as a p-type transistor, for example, coupled between the power supply and the power rail may convey operational current to the power rail from the power supply during operation in a normal mode. 
         [0010]    In one specific implementation, the resistor may be a semiconductor material such as polycrystalline silicon, for example, formed in the semiconductor substrate in which the storage array is formed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1A  is a block diagram of a memory including a prior art technique for providing retention voltage to a memory array. 
           [0012]      FIG. 1B  is a block diagram of a memory including another prior art technique for providing retention voltage to a memory array. 
           [0013]      FIG. 2  is a block diagram of one embodiment of a memory including a circuit for providing retention voltage to a memory array. 
           [0014]      FIG. 3  is a block diagram of one embodiment of a system. 
       
    
    
       [0015]    Specific embodiments are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the claims to the particular embodiments disclosed, even where only a single embodiment is described with respect to a particular feature. On the contrary, the intention is to cover all modifications, equivalents and alternatives that would be apparent to a person skilled in the art having the benefit of this disclosure. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. 
         [0016]    As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include,” “including,” and “includes” mean including, but not limited to. 
         [0017]    Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph six, interpretation for that unit/circuit/component. 
         [0018]    The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims. 
       DETAILED DESCRIPTION 
       [0019]    Turning now to  FIG. 2 , a block diagram of one embodiment of a memory including a circuit for providing retention voltage to a memory array is shown. The memory  30  includes a storage array  22  that is coupled to a circuit ground and to a top level Vdd through a p-type transistor T 4 , and a retention resistor RR 1 . 
         [0020]    In one embodiment, during operation in a normal mode, a normal mode signal (e.g., zero volts) is applied to the gate of transistor T 4  causing it to conduct, thereby providing the top level Vdd to the storage array  12 . During operation in the normal mode, because series resistance of the transistor T 4  is small compared to the retention resistor RR 1 , a majority of the operational current will flow through transistor T 4  into the storage array  22 . 
         [0021]    During operation in a low power or retention mode, in one embodiment the normal mode signal may transition to a high logic level, causing transistor T 4  to turn off. Accordingly, rather than current flowing through transistor T 4 , current instead will flow through the retention resistor RR 1  into the storage array. In the retention mode, there are no active wordline signals (not shown), and the memory device is inactive. Thus, the current through the resistor RR 1  is relatively constant at a given process, voltage, and temperature (PVT), and is due to leakage current I L . 
         [0022]    The current through resistor RR 1  causes a voltage drop (VRR 1 ) across resistor RR 1 . Thus the retention voltage available at the storage array  12  may be expressed as top-level Vdd−VRR 1 . Because the leakage current is relatively constant irrespective of the resistance of RR 1 , the resistance value of RR 1  may be calculated based upon the desired retention voltage and the substantially constant leakage current using Ohm&#39;s law. Thus, the resistor RR 1  may be manufactured with a resistance value tolerance according to the manufacturing variability and still provide the appropriate retention voltage to the storage array Vdd rail. The value of the resistor RR 1  may be designed at a worst-case process voltage and temperature. As such, the actual value of the resistor RR 1  at a given PVT may vary, but the variation will thus be accounted for. Having such a tolerance aids in manufacturability. 
         [0023]    In one embodiment, since the leakage current I L  may be known for the storage array  22 , the resistance value of RR 1  may be calculated using Ohm&#39;s law, in which R=V/I. In this case, R corresponds to the resistance of RR 1 , V corresponds to the voltage drop VRR 1  across the resistor, and the current I is I L . The voltage VRR 1  may be determined based upon the worst-case retention voltage supplied to the array Vdd rail. For example, if the top level Vdd is 2.0V, and the worst-case retention voltage is 0.8V, then VRR 1  would be 1.2V. Assuming the leakage current I L  is 20 μA for the storage array  22 , then using Ohm&#39;s law, the resistance value of RR 1  would be 60KΩ. However, to accommodate manufacturing variances, the voltage of VRR 1  could be decreased to provide a resistance range. Accordingly, in this example, the voltage VRR 1  could be decreased by some predetermined amount or percentage to allow for whatever variance is expected in the manufacturing process. More particularly, if the manufacturing variance is 10%, the VRR 1  could be decreased by 10% to 1.08V. Using Ohm&#39;s law, the resulting resistance would be 54KΩ. Accordingly, to keep the retention voltage above the minimum of 0.8V, the resistance may vary between 54KΩ and 60KΩ. It is noted that the above values are merely exemplary and for discussion purposes only. 
         [0024]    In one embodiment, the memory device  30 , and thus the storage array  22  corresponds to an integrated circuit manufactured on a semiconductor substrate. Accordingly, resistor RR 1  may be formed using any of a variety manufacturing techniques that are used to form and trim such resistors. In various embodiments, the resistor RR 1  may be implemented using polycrystalline silicon, metal, or combinations thereof, as desired. 
         [0025]    As described above in conjunction with the embodiment shown in  FIG. 2 , providing the retention mode voltage to the storage array power rail through a resistor may allow for manufacturing variability and no additional monitor and control logic. In addition, since the resistor RR 1 , does not have any gate control signals there are fewer wires to route than in conventional techniques. 
         [0026]    It is noted that the memory  30  shown in the embodiment of  FIG. 2 , may be representative of any type of memory device that may be placed into a retention mode. In one embodiment, the memory device  30  may be implemented as an embedded memory such as a cache memory or a register file within any of a variety of devices such as a processor for example. 
         [0027]    Turning to  FIG. 3 , a block diagram of one embodiment of a system is shown. The system  300  includes at least one instance of an integrated circuit  310  coupled to one or more peripherals  307  and an external system memory  305 . The system  300  also includes a power supply  301  that may provide one or more supply voltages to the integrated circuit  310  as well as one or more supply voltages to the memory  305  and/or the peripherals  307 . 
         [0028]    In one embodiment, the integrated circuit  310  be a system on a chip (SOC) including one or more instances of a processor and various other circuitry such as a memory controller, video and/or audio processing circuitry, on-chip peripherals and/or peripheral interfaces to couple to off-chip peripherals, etc. Accordingly, the integrated circuit  310  may include one or more instances of an embedded memory such as memory  30  of  FIG. 2 . Thus, embodiments that include the memory  30  may also include the retention mode resistor described above in conjunction with the description of  FIG. 2 . 
         [0029]    The peripherals  307  may include any desired circuitry, depending on the type of system. For example, in one embodiment, the system  300  may be included in a mobile device (e.g., personal digital assistant (PDA), smart phone, etc.) and the peripherals  307  may include devices for various types of wireless communication, such as WiFi, Bluetooth, cellular, global positioning system, etc. The peripherals  307  may also include additional storage, including various types of RAM storage, solid-state storage, or disk storage. As such, the peripherals  307  may also include RAM that includes the retention mode resistor described above. The peripherals  307  may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system  300  may be included in any type of computing system (e.g. desktop personal computer, laptop, workstation, net top etc.). 
         [0030]    The external system memory  305  may be representative of any type of memory. For example, the external memory  305  may be in the DRAM family such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.), or any low power version thereof. However, external memory  305  may also be implemented in SDRAM, static RAM (SRAM), or other types of RAM, etc. Accordingly, external system memory  305  may also include the retention mode resistor described above in conjunction with the description of  FIG. 2 . 
         [0031]    Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.