Abstract:
A method of operating a circuitry including a video data signal processing circuitry generating a video data signal and a data clock signal in response to an input video data signal, and a data electrode driver driving a plasma display panel in response to the video data signal. The method is composed of: allowing an initial setting storage unit to output an initial setting data signal representative of an initial setting of the video data signal processing circuitry, placing the video data signal processing circuitry in the initial setting in response to the initial setting data signal, producing a mute signal in response to the initial setting data signal, and disabling and enabling at least one of the video data signal processing circuitry and the data electrode driver in response to the mute signal.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention is related, in general, to a plasma display panel (PDP) and method for operating the same, and more particularly, to fast reliable start-up of a plasma display panel.  
           [0003]    2. Description of the Related Art  
           [0004]    A plasma display panel is one of the most promising display devices. A plasma display panel typically includes an array of light emitting elements, each of which emits light through gas discharge and fluorescence. The gas discharge and fluorescence is achieved by applying pulses on electrodes disposed in the light emitting element array, including a common electrode, scan electrodes and data electrodes. The electrodes are activated in response to a video signal to develop a desired image on the panel.  
           [0005]    [0005]FIG. 1 shows an exemplary plasma display system  100 . The system  100  includes a plasma display panel  102 , a common electrode driver  104 , a scan electrode driver  106 , a data electrode driver  108 , and a video data signal generator  110 .  
           [0006]    The common electrode driver  104  and the scan electrode driver  106  respectively drive a common electrode and an array of scan electrodes disposed in the plasma display panel  102 .  
           [0007]    The video data signal generator  110  provides the data electrode driver  108  with a video data signal VIDEO_OUT and a data clock signal CLK_OUT in response to an input video data signal VIDEO_IN.  
           [0008]    In response to the video data signal VIDEO_OUT, the data electrode driver  108  addresses and drives data electrodes disposed in the plasma display panel  102  in synchronization with the data clock signal CLK_OUT.  
           [0009]    The data electrode driver  108  receives a blanking signal BLANK from an external circuit. In response to the blanking signal BLANK being activated, the data electrode driver  108  is deactivated.  
           [0010]    The common electrode driver  104  and the scan electrode driver  106 , which develops high-voltage pulses to maintain gas discharge in the light emitting elements, operate on a high supply voltage V CCH  provided from a high-voltage power supply (not shown).  
           [0011]    On the other hand, the data electrode driver  108  and the video data signal generator  110 , which do not require high-voltage supply, operate on a logic power supply voltage V CCL  supplied from a logic circuit voltage source (not shown). The logic power supply voltage V CCL  is lower than the high supply voltage V CCH  provided for the common electrode driver  104  and the scan electrode driver  106 .  
           [0012]    [0012]FIG. 2 shows a schematic of the video data signal generator  110 . The video data signal generator  110  includes an initial setting storage circuit  112  and a video data signal processor  114 .  
           [0013]    The initial setting storage circuit  112  stores therein data on an initial setting of the video data signal processor  114 . The initial setting typically includes conditions of sub-field coding and weighting for generating graylevels to be displayed on each light emitting element. The sub-field coding involves defining sub-fields for each field of the input video data signal. One field typically includes eight sub-fields. Weighting for generating graylevels involves determining a number of times of discharge of each light emitting element for each sub-field.  
           [0014]    When the system  100  is started up, the initial setting storage circuit  112  provides an initial setting signal INT_SET representative of the initial setting of the video data signal processor  114 .  
           [0015]    The video data signal processor  114  decodes the input video data signal VIDEO_IN in accordance with the initial setting defined by the initial setting storage circuit  112  to output the video data signal VIDEO_OUT and the data clock signal CLK_OUT to the data electrode driver  108 . When the system  100  is started up, the video data signal processor  114  receives the initial setting signal INT_SET to be placed in the initial setting represented by the initial setting signal.  
           [0016]    The video data signal processor  114  receives a mute signal MUTE from a mute signal generator (not shown). The mute signal MUTE disables the input of the input video data signal VIDEO_IN to the video data signal processor  114 .  
           [0017]    The mute signal MUTE is used for avoiding an undesirable image being displayed on the plasma display panel  102  when the system  100  is started up. The video data signal processor  114  requires a considerable period to complete the initial setting after the start-up of the system  100 , because the video data signal processor  114  needs to receive the initial setting signal INT_SET from the initial setting storage circuit  112 . Outputting the video data signal VIDEO_OUT and the data clock CLK_OUT before the completion of the initial setting results in the display of an undesirable image on the plasma display panel  102 . The mute signal MUTE is activated to disable the input video data signal VIDEO_IN for a predetermined period after the start-up of the system  100 , thereby prevents an undesirable image from being displayed on the plasma display panel  102 .  
           [0018]    [0018]FIG. 3 shows a start-up sequence of the plasma display system  100 . In response to a master electrical switch of the system  100  being turned on, the logic circuit power supply starts to provide the logic circuit supply voltage V CCL  for the video data signal generator  10 . The initial setting storage circuit  112 , which operates on the logic circuit supply voltage V CCL , then starts to provide the initial setting signal INI_SET for the video data signal processor  114 . Then, the high-voltage power supply starts to provide a high supply voltage V CCH  for the common electrode driver  104  and the scan electrode driver  106 .  
           [0019]    In the meantime, the mute signal MUTE is activated in response to the turn-on of the supply voltage V CCL  as shown in FIG. 3C. The mute signal MUTE remains activated for a predetermined period to disable the input video data signal VIDEO_IN. After the predetermined period expires, the mute signal MUTE is then deactivated to allow the video data signal processor  114  to receive the input video data signal VIDEO_IN. The video data signal processor  114  then starts to output the video data signal VIDEO_OUT and the data clock CLK_OUT in response to the input video data signal VIDEO_IN.  
           [0020]    The use of the mute signal MUTE effectively prevents the plasma display panel  102  from displaying an undesirable image thereon. However, the use of the mute signal MUTE increases the period required for the plasma display system  100  to be started up after the master electrical switch is turned on.  
           [0021]    A need exists to provide architecture that facilitates fast reliable start-up of a plasma display system.  
           [0022]    Another factor causing undesirable images to be displayed on the plasma display panel  102  is that sufficiently high supply voltage is not supplied to the common electrode driver  104  and the scan electrode driver  106 . An accidental drop of the high supply voltage may result in displaying undesirable images, such as inhomogeneous images, blinking images and so on. Besides, turn-off of the high supply voltage V CCH  in response to the turn-off of the master electrical switch of the system  100  may results in displaying undesirable images.  
           [0023]    A need exists to provide architecture that avoids undesirable images being displayed when the drivers are not provided with sufficiently high supply voltage.  
           [0024]    A technology which may be related to the present invention is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-140434). The disclosed technology involves the use of a mute signal in an LCD (liquid crystal display) driver for disabling a video signal in response to a period of turn-off of a back light.  
         SUMMARY OF THE INVENTION  
         [0025]    Therefore, an object of the present invention is to provide architecture that facilitates fast reliable start-up of a plasma display system.  
           [0026]    Another object of the present invention is to provide architecture that avoids undesirable images being displayed when the drivers are not provided with sufficiently high supply voltage.  
           [0027]    In an aspect of the present invention, a method is provided for operating a circuitry including a video data signal processing circuitry generating a video data signal and a data clock signal in response to an input video data signal, and a data electrode driver driving a plasma display panel in response to the video data signal. The method is composed of:  
           [0028]    allowing an initial setting storage unit to output an initial setting data signal representative of an initial setting of the video data signal processing circuitry;  
           [0029]    placing the video data signal processing circuitry in the initial setting in response to the initial setting data signal;  
           [0030]    producing a mute signal in response to the initial setting data signal; and  
           [0031]    disabling and enabling at least one of the video data signal processing circuitry and the data electrode driver in response to the mute signal.  
           [0032]    It is advantageous that the allowing includes providing a supply voltage for the initial setting storage circuit, the producing the mute signal includes activating the mute signal in response to turn-on of the supply voltage, and the disabling and enabling includes disabling the at least one of the video data signal processing circuitry and the data electrode driver in response to the mute signal being activated.  
           [0033]    It is advantageous that the producing the mute signal includes:  
           [0034]    monitoring the initial setting signal to detect completion of transfer of the initial setting, and  
           [0035]    deactivating the mute signal in response to the completion of the transfer of the initial setting signal, and that the disabling and enabling includes enabling the at least one of the video data signal processing circuitry and the data electrode driver in response to the mute signal being deactivated.  
           [0036]    The disabling and enabling preferably includes disabling and enabling an input of the input video data signal in response to the mute signal.  
           [0037]    It is also preferable that the disabling and enabling includes disabling and enabling an output of the video data signal in response to the mute signal.  
           [0038]    It is also preferable that the disabling and enabling includes disabling and enabling an output of the data clock signal in response to the mute signal.  
           [0039]    It is also preferably that the disabling and enabling includes disabling and enabling the data electrode driver in response to the mute signal.  
           [0040]    In another aspect of the present invention a method is provided for operating a circuitry including a video data signal processing circuitry generating a video data signal and a data clock signal in response to an input video data signal, a data electrode driver driving a plasma display panel in response to the video data signal and a scan electrode driver operating driving the plasma display panel. The method is composed of:  
           [0041]    providing a first supply voltage for an initial setting storage unit to allow the initial setting storage unit to output an initial setting data signal representative of an initial setting;  
           [0042]    placing the video data signal processing circuitry in the initial setting in response to the initial setting data signal;  
           [0043]    providing a second supply voltage for the scan electrode driver after turn-on of the first supply voltage;  
           [0044]    producing a mute signal in response to the initial setting data signal and the second supply voltage; and  
           [0045]    disabling and enabling at least one of the video data signal processing circuitry and the data electrode driver in response to the mute signal.  
           [0046]    It is preferable that the producing the mute signal preferably includes activating the mute signal in response to the turn-on of the first supply voltage, and the disabling and enabling includes disabling the at least one of the video data signal processing circuitry and the data electrode driver in response to the mute signal being activated.  
           [0047]    It is preferable that the producing the mute signal includes:  
           [0048]    activating a setting completion signal in response to transfer of the initial setting signal being completed,  
           [0049]    activating a voltage ready signal in response to the second supply voltage becoming higher than a predetermined voltage level, and  
           [0050]    deactivating the mute signal in response to both of the setting completion signal and the voltage ready signal being activated, and  
           [0051]    that the disabling and enabling includes enabling the at least one of the video data signal processing circuitry and the data electrode driver in response to the mute signal being deactivated.  
           [0052]    It is advantageous that the producing the mute signal includes activating the mute signal in response to the second supply voltage becoming lower than a predetermined voltage level, and the disabling and enabling includes disabling the at least one of the video data signal processing circuitry and the data electrode driver in response to the mute signal being activated.  
           [0053]    In still another aspect of the present invention, a circuitry for driving a plasma display panel is composed of a video data signal processing circuitry producing a video data signal and a data clock signal in response to an input video data signal, a data electrode driver driving the plasma display panel in response to the video data signal and the data clock signal, an initial setting storage circuit outputting an initial setting signal representative of an initial setting in which the video data signal processing circuitry is to be placed, and a mute signal generator producing a mute signal in response to the initial setting signal, wherein at least one of the video data signal processing circuitry and the data electrode driver is disabled and enabled in response to the mute signal.  
           [0054]    When the circuitry further includes a power supply providing a supply voltage for the initial setting storage circuit, it is preferable that the mute signal generator activates the mute signal in response to turn-on of the supply voltage, and the at least one of the video data signal processing circuitry and the data electrode driver is disabled in response to the mute signal being activated.  
           [0055]    It is preferable that the mute signal generator monitors the initial setting signal to detect completion of transfer of the initial setting signal, and deactivates the mute signal in response to the completion of the transfer of the initial setting, and the at least one of the video data signal processing circuitry and the data electrode driver is enabled in response to the mute signal being deactivated.  
           [0056]    Preferably, the circuitry further includes a logic circuitry disabling and enabling an input of the input video data signal to the video data signal processing circuitry in response to the mute signal.  
           [0057]    It is also preferable that the circuitry further includes a logic circuitry disabling and enabling an output of the video data signal to the data electrode driver in response to the mute signal.  
           [0058]    It is also preferable that the circuitry further includes a logic circuitry disabling and enabling an output of the data clock signal to the data electrode driver in response to the mute signal.  
           [0059]    It is also preferable that the data electrode driver is disabled and enabled in response to the mute signal.  
           [0060]    In yet still another aspect of the present invention, a circuitry for driving a plasma display panel includes a video data signal processing circuitry producing a video data signal and a data clock signal in response to an input video data signal, a data electrode driver driving the plasma display panel in response to the video data signal and the data clock signal, a first power supply providing a first supply voltage, an initial setting storage circuit operating on the first supply voltage to output an initial setting signal representative of an initial setting in which the video data signal processing circuitry is to be placed, a high-voltage power supply providing a second supply voltage after turn-on of the first supply voltage, a scan electrode driver operating on the second supply voltage to drive the plasma display panel, a mute signal generator producing a mute signal in response to the initial setting signal and the second supply voltage. At least one of the video data signal processing circuitry and the data electrode driver is disabled and enabled in response to the mute signal.  
           [0061]    It is preferable that the mute signal generator activates the mute signal in response to the turn-on of the first supply voltage, and the at least one of the video data signal processing circuitry and the data electrode driver is disabled in response to the mute signal being activated.  
           [0062]    It is also preferable that the circuitry further includes a voltage monitor circuit activating a voltage ready signal in response to the second supply voltage becoming higher than a predetermined voltage level, and the mute signal generator includes a setting completion detecting circuit activating a setting completion signal in response to transfer of the initial setting signal being completed, and a logic gate deactivating the mute signal in response to both of the setting completion signal and the voltage ready signal being activated, and the at least one of the video data signal processing circuitry and the data electrode driver is enabled in response to the mute signal being deactivated.  
           [0063]    It is also preferable that the mute signal generator activates the mute signal in response to the second supply voltage becoming lower than a predetermined voltage level, and the at least one of the video data signal processing circuitry and the data electrode driver is disabled in response to the mute signal being activated. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0064]    [0064]FIG. 1 shows a schematic of a conventional plasma display system;  
         [0065]    [0065]FIG. 2 shows a schematic of a video data signal generator disposed in the conventional plasma display system;  
         [0066]    [0066]FIG. 3 is a timing chart illustrating an operation of the conventional plasma display system;  
         [0067]    [0067]FIG. 4 shows a schematic of a plasma display system in a first embodiment in accordance with the present invention;  
         [0068]    [0068]FIG. 5 shows a schematic of a video data signal generator disposed in the plasma display system in the first embodiment;  
         [0069]    [0069]FIG. 6 shows a schematic of a mute signal generator disposed in the plasma display system in the first embodiment;  
         [0070]    [0070]FIG. 7 is a timing chart illustrating an operation of the plasma display system in the first embodiment;  
         [0071]    [0071]FIG. 8 shows a schematic of a video data signal generator in a plasma display system in a second embodiment in accordance with the present invention;  
         [0072]    [0072]FIG. 9 is a timing chart illustrating an operation of the plasma display system in the second embodiment;  
         [0073]    [0073]FIG. 10 shows a schematic of part of a plasma display system in a third embodiment in accordance with the present invention; and  
         [0074]    [0074]FIG. 11 shows a schematic of a mute signal generator disposed in a plasma display system in a fourth embodiment in accordance with the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0075]    The present invention will be described below in detail with reference to the attached drawings.  
       First Embodiment  
       [0076]    In one embodiment, as shown in FIG. 4, a plasma display system  1  includes a plasma display panel  2 , a common electrode driver  4 , a scan electrode driver  6 , a data electrode driver  8 , a video data signal generator  10 .  
         [0077]    The plasma display panel  2  includes light emitting elements arranged in rows and columns. The light emitting elements are activated by a common electrode, scan electrodes, and data electrodes disposed in the plasma display panel  2 .  
         [0078]    The common electrode driver  4  develops common pulses on the common electrode, and the scan electrode driver  6  develops scan pulses on the scan electrodes. The common pulses and the scan pulses allow the light emitting elements to start and maintain discharge therein.  
         [0079]    The common electrode driver  4  and the scan electrode driver  6 , which drives the light emitting elements to maintain gas discharge therein, operates on a high supply voltage V CCH  provided by a high-voltage power supply  18 . The high-voltage power supply  18  includes a voltage monitor circuit  181  monitoring the high supply voltage V CCH . The voltage monitor circuit  181  activates a high-voltage ready signal HV_READY when the high supply voltage V CCH  becomes higher than a predetermined voltage level Vth. The voltage level Vth is determined so that the drive of the plasma display panel  2  is stable.  
         [0080]    The data electrode driver  8  receives a video data signal VIDEO_OUT and a data clock signal CLK_OUT from the video data signal generator  10  to drive the data electrodes disposed in the plasma display panel  2 . The data electrode driver  8  develops data pulses on the data electrodes in response to the video data signal VIDEO_OUT in synchronization with the data clock signal CLK_OUT.  
         [0081]    The data electrode driver  8  and the video data signal generator  10  operate on a logic circuit supply voltage V CCL  provided by a logic circuit power supply  20 . The high supply voltage V CCH  provided for the common electrode driver  4  and the scan electrode driver  6  during normal operation is higher than the logic circuit supply voltage V CCL  provided for the data electrode driver  8  and the video data signal generator  10 . Thus, the aforementioned voltage level Vth is determined to be higher than the logic circuit supply voltage V CCL .  
         [0082]    As shown in FIG. 2, the video data signal generator  10  includes an initial setting storage circuit  12 , a PDP video data signal processing circuitry  14 , and a mute signal generator  16 .  
         [0083]    The initial setting storage circuit  12  stores therein an initial setting of the PDP video data signal processing circuitry  14 . When the system  1  is started up, the initial setting storage circuit  12  provides an initial setting signal INT_SET representative of the initial setting in which the PDP video data signal processing circuitry  14  is to be placed. The initial setting storage circuit  12  may include a nonvolatile memory device, such as EEPROM (Electrically Erasable Programmable Read Only Memory).  
         [0084]    The PDP video data signal processing circuitry  14  includes a video data signal processor  140  and an AND gate  141 .  
         [0085]    The video data signal processor  140  receives an input video data signal VIDEO_IN through the AND gate  141 , and generates the video data signal VIDEO_OUT and the data clock CLK_OUT in response to the input video data signal VIDEO_IN.  
         [0086]    The video data signal processor  140  is responsive to the initial setting defined by the initial setting storage circuit  12 . When the system  1  is started up, the video data signal processor  140  receives the initial setting signal INT_SET from the initial setting storage circuit  12 , and is placed in the initial setting indicated by the initial setting signal INT_SET.  
         [0087]    The AND gate  141  receives the input video data signal VIDEO_IN on a first input and a mute signal MUTE from the mute signal generator  16  on a second inverted input. The AND gate  141  selectively provides the input video data signal VIDEO_IN for the video data signal processor  140  in response to the mute signal MUTE. When the mute signal MUTE is activated, the AND gate  141  disables the input of the input video data signal VIDEO_IN.  
         [0088]    The mute signal generator  16  is responsive to the initial setting signal INT_SET from the initial setting storage circuit  12  and the high-voltage ready signal HV_READY received from the voltage monitor circuit  181  for producing the mute signal MUTE. As described below, generating the mute signal in response to the initial setting signal INT_SET and the high-voltage ready signal HV_READY achieves fast start-up of the system  1  while avoiding an undesirable image being displayed on the plasma display panel  2 .  
         [0089]    [0089]FIG. 3 shows a schematic of the mute signal generator  16 . The mute signal generator  16  includes an initial setting completion detector circuit  161  and an NAND gate  162  and a resister  163 .  
         [0090]    The setting completion detector circuit  161  monitors the initial setting signal INT_SET to detect the completion of transfer of the initial setting from the initial setting storage circuit  12  to the video data signal processor  14 . When the initial setting signal INT_SET stays unchanged for a predetermined continuous period, the setting completion detector circuit  161  activate a setting completion signal COMPLETE to represent that the transfer of the initial setting is completed.  
         [0091]    The NAND gate  162  receives the setting completion signal COMPLETE and the high-voltage ready signal HV_READY to develop the mute signal MUTE on the output. The mute signal MUTE is provided for the AND gate  141  to disable the input of the input video data signal VIDEO_IN to the video data signal processor  140 . The output of the NAND gate  162  is also connected to the logic circuit power supply  20  through the resistor  163 . The resistor  163  allows the output of the NAND gate  162  to be activated in response to the logic circuit power supply  20  being turned on, and to be deactivated in response to the logic circuit power supply  20  being turned off.  
         [0092]    The setting completion detector circuit  161  and the NAND gate  162  operate on the logic circuit supply voltage V CCL  from the logic circuit power supply  20 .  
         [0093]    [0093]FIG. 7 is a timing chart showing operations of the plasma display system  100 . In response to a master electrical switch, typically disposed on a remote control, being turned on, a main power supply of the system  100  is activated. The activation of the main power supply allows the logic circuit supply voltage V CCL  to be turned on.  
         [0094]    In response to the turn-on of the logic circuit supply voltage V CCL , the setting completion detector circuit  161  and the voltage monitor circuit  181  are reset, and thus the setting completion signal COMPLETE and the high-voltage ready signal HV_READY are deactivated (that is, set to logic “L”). In response to the setting completion signal COMPLETE and the high-voltage ready signal HV_READY being deactivated, the NAND gate  162  in the mute signal generator  16  activates the mute signal MUTE when the logic circuit supply voltage V CCL  is turned-on. The activated mute signal MUTE disables the input of the input video data signal VIDEO_IN to the video data signal processor  140 .  
         [0095]    The turn-on of the logic circuit supply voltage V CCL  allows the initial setting storage circuit  12  to start to output the initial setting signal INT_SET to the video data signal processor  140 . The transfer of the initial setting by the initial setting signal INT_SET requires a certain period to be completed. When the completion detector circuit  161  detects the completion of the transfer of the initial setting on the basis of the initial setting signal INT_SET, the completion detector circuit  161  activates the setting completion signal COMPLETE. The activated setting completion signal COMPLETE represents that the video data signal processor  140  is ready to produce the video data signal VIDEO_OUT.  
         [0096]    In the meantime, the high supply voltage V CCH  is turned on by the high-voltage power supply  18 . The voltage monitor circuit  181 , disposed in the high-voltage power supply  18 , monitors the high supply voltage V CCH , and activates the high-voltage ready signal HV_READY when the high supply voltage V CCH  becomes higher than the predetermined voltage level Vth. The activated high-voltage ready signal HV_READY represents that the common electrode driver  4  and the scan electrode driver  6  are ready to drive the plasma display panel  2 .  
         [0097]    In response to both of the setting completion signal COMPLETE and the high-voltage ready signal HV_READY being activated, the mute signal MUTE is deactivated to allow the video data signal processor  140  to provide the video data signal VIDEO_OUT for the data electrode driver  8 . It should be noted that the activation of only one of the setting completion signal COMPLETE and the high-voltage ready signal HV_READY does not allow the mute signal MUTE to be deactivated. Then the common electrode driver  4 , the scan electrode driver  6 , and the data electrode driver  8  starts to drive the plasma display panel  2  to display a desired image thereon.  
         [0098]    The input of the input video data signal VIDEO_IN may start before the transfer of the initial setting is complete or before the high supply voltage V CCH  becomes higher than the predetermined voltage level Vth. However, the architecture thus-described effectively avoids an undesirable image being displayed on the plasma display panel  2 , because the mute signal MUTE is kept activated till the transfer of the initial setting is complete and the high supply voltage V CCH  becomes higher than the predetermined voltage level Vth.  
         [0099]    On the other hand, the architecture thus-described is also effective in fast start-up of the plasma display system  1 . The timing of the deactivation of the mute signal MUTE is determined in response to the setting completion signal COMPLETE and the high-voltage ready signal HV_READY, and thus the mute signal MUTE is deactivated as soon as the transfer of the initial setting is completed and the high supply voltage V CCH  is turned on. The flexible deactivation of the mute signal MUTE facilitates the fast start-up of the plasma display system  1 .  
         [0100]    The architecture thus-described also avoids an undesirable image being displayed on the plasma display panel  2  when the master electrical switch of the plasma display system  1  is turned off.  
         [0101]    When the master electrical switch of the system 1  is turned off, the high-voltage power supply  18  turns off the high supply voltage V CCH . The voltage monitor circuit  181  deactivates the high-voltage ready signal HV_READY when detecting that the high supply voltage V CCH  is turned off, that is, detecting that the high supply voltage V CCH  becomes lower than the predetermined voltage level Vth. The deactivation of the high-voltage ready signal HV_READY causes the NAND gate  162  in the mute signal generator  16  to activate the mute signal MUTE.  
         [0102]    In response to the mute signal MUTE being activated, the AND gate  141  in the PDP video data signal processing circuitry  14  disables the provision of the input video data signal VIDEO_IN for the video data signal processor  140 . This results in that the video data signal processor  140  stops outputting the video data signal VIDEO_OUT. Accordingly, the erroneous display of an undesirable image is avoided after the turn-off of the high supply voltage V CCH .  
         [0103]    Then, the logic circuit power supply  18  turn off the logic circuit supply voltage V CCL . The turn-off of the logic circuit supply voltage V CCL  deactivates the NAND gate  162  and stops the supply of logic circuit supply voltage V CCL  on the output of the NAND gate  162  through the resister  163 . Thus, the mute signal MUTE is deactivated.  
         [0104]    As just described, the architecture in this embodiment effectively avoids an undesirable image being displayed on the plasma display panel  2  while achieving fast start-up of the system  1 . In addition, the architecture in this embodiment effectively avoids an undesirable image being displayed on the plasma display panel  2  when the main power supply of the system  1  is turned off.  
       Second Embodiment  
       [0105]    In a second embodiment, a video data signal generator  10 A shown in FIG. 8 is provided for the plasma display system  1  in place of the video data signal generator  10  used in the first embodiment. The difference between the video data signal generators  10  and  10 A is that the video data signal generator  10 A deactivates the data clock signal CLK_OUT in response to the activation of the mute signal MUTE, instead of disabling the input of the input video data signal VIDEO_IN.  
         [0106]    The architecture of the video data signal generator  10 A is identical to the video data signal generator  10 , except that the video data signal generator  10 A includes a PDP video data signal processing circuitry  14 A in place of the PDP video data signal processing circuitry  14 . The PDP video data signal processing circuitry  14 A produces the video data signal VIDEO_OUT in response to the input video data signal VIDEO_IN. The PDP video data signal processing circuitry  14 A receives the initial setting signal INT_SET from the initial setting storage circuit  12  to be placed in the initial setting indicated by the initial setting signal INT_SET.  
         [0107]    The PDP video data signal processing circuitry  14 A includes a data clock signal generator  142  and an AND gate  143 . The data clock signal generator  142  produces the data clock signal CLK_OUT in response to the input video data signal VIDEO_IN. The AND gate  143  receives the data clock signal CLK_OUT from the data clock signal generator  142  on a first input, and the mute signal MUTE from the mute signal generator  16  on a second inverted input.  
         [0108]    The AND gate  143  selectively outputs the data clock signal CLK_OUT to the data electrode driver  8  in response to the mute signal MUTE. When the mute signal MUTE is deactivated, the AND gate  143  outputs the data clock signal CLK_OUT from its output. On the other hand, the AND gate  143  disables the output of the data clock signal CLK_OUT when the mute signal MUTE is activated.  
         [0109]    [0109]FIG. 9 is a timing chart illustrating the operation of the plasma display system  1  in the second embodiment.  
         [0110]    The generation of the mute signal MUTE in the second embodiment is achieved through the same process as the first embodiment. In response to the turn-on of the logic circuit supply voltage V CCL , the mute signal MUTE is activated by the NAND gate  162  disposed in the mute signal generator  16 .  
         [0111]    The activation of the mute signal MUTE disables the output of the data clock signal CLK_OUT to the data electrode driver  8 . In response to the data clock signal CLK_OUT being disabled, the data electrode driver  8  fails to fetch the video data signal VIDEO_OUT, and thus the erroneous drive of the plasma display panel  2  is avoided.  
         [0112]    The mute signal MUTE is deactivated in response to both of the setting completion signal COMPLETE and the high-voltage ready signal HV_READY being activated. In response to the deactivation of the mute signal MUTE, the AND gate  143  starts to output the data clock signal CLK_OUT to allow the data electrode driver  8  to drive the plasma display panel  2  in response to the video data signal VIDEO_OUT.  
         [0113]    Therefore, the architecture in the second embodiment effectively avoids an undesirable image being displayed when the system  1  is started up. The PDP video data signal circuitry  14 A may start to provide the video data signal VIDEO_OUT in response to the input video data signal VIDEO_IN before the initial setting of the PDP video data signal circuitry  14 A is completed or before the turn-on of the high supply voltage V CCH . However, it does not causes the erroneous display of an undesirable image on the plasma display panel  2 , because the output of the data clock signal CLK_OUT is disabled while any one of the initial setting of the PDP video data signal circuitry  14 A and the turn-on of the high supply voltage V CCH  is not yet completed.  
         [0114]    In addition, in the same way as the first embodiment, the architecture in the second embodiment facilitates fast start-up of the system  1 , because the mute signal MUTE is flexibly deactivated to allow the provision of data clock signal CLK_OUT in response to the activation of the setting completion signal COMPLETE and the high-voltage ready signal HV_READY.  
         [0115]    Furthermore, in the same way as the first embodiment, the architecture in the second embodiment effectively avoids an undesirable image being displayed on the plasma display panel  2  when the master electrical switch of the plasma display system  1  is turned off. When the master electrical switch of the display system  1  is turned off, the mute signal MUTE is activated in response to the turned-off of the high supply voltage V CCH . The activation of the mute signal MUTE effectively avoids an undesirable image being displayed on the plasma display panel  2  after the turn-off of the high supply voltage V CCH .  
         [0116]    In the second embodiment, the AND gate  143  may receive the video data signal VIDEO_OUT instead of the data clock signal CLK_OUT on the first input. In this case, the activation of the mute signal MUTE disables the video data signal VIDEO_OUT. Those who skilled in the art would appreciate that this modification also facilitates fast start-up of the system  1  while avoiding an undesirable image being displayed on the plasma display panel  2 .  
       Third Embodiment  
       [0117]    In a third embodiment, as shown in FIG. 10, the plasma display system  1  is modified as described below. The video data signal generator  10 B is provided for the system  1  in place of the video data signal generator  10 . The video data signal generator  10 B includes the initial setting storage circuit  12  and mute signal generator  16  in the same way as the video data signal generator  10  in the first embodiment.  
         [0118]    The video data signal generator  10 B includes a video data signal processor  14 B to produce the video data signal VIDEO_OUT and the data clock signal CLK_OUT. The video data signal processor  14 B receives the initial setting signal INT_SET to be placed in the initial setting indicated by the initial setting signal INT_SET.  
         [0119]    The plasma display system  1  further includes an OR gate  17 . The OR gate  17  receives the mute signal MUTE, generated by the mute signal generator  16 , on a first input, and the blanking signal BLANK on a second input. The OR gate  17  activates its output when at least one of the mute signal MUTE and the blanking signal BLANK is activated. The output of the OR gate  17  is connected to an blanking terminal  81  of the data electrode driver  8 . In response to the output of the OR gate  17  activated, the data electrode driver  8  is deactivated.  
         [0120]    The generation of the mute signal MUTE in the third embodiment is achieved through the same process as the first embodiment. In response to the turn-on of the logic circuit supply voltage V CCL , the mute signal MUTE is activated by the NAND gate  162  disposed in the mute signal generator  16 .  
         [0121]    In response to the activation of the mute signal MUTE, the output of the OR gate  17  is activated. The activation of the output of the OR gate  17  disables the data electrode driver  8 .  
         [0122]    The mute signal MUTE is deactivated in response to both of the setting completion signal COMPLETE and the high-voltage ready signal HV_READY being activated. In response to the deactivation of the mute signal MUTE, the output of the OR gate  17  is deactivated to allow the data electrode driver  8  to drive the plasma display panel  2  in response to the video data signal VIDEO_OUT and the data clock signal CLK_OUT.  
         [0123]    Therefore, the architecture in the third embodiment effectively avoids an undesirable image being displayed when the system  1  is started up. The PDP video data signal circuitry  14 B may start to provide the video data signal VIDEO_OUT in response to the input video data signal VIDEO_IN before the initial setting of the PDP video data signal circuitry  14 B is completed or before the turn-on of the high supply voltage V CCH . However, it does not causes the erroneous display of an undesirable image on the plasma display panel  2 , because the data electrode driver  8  is disabled while any one of the initial setting of the PDP video data signal circuitry  14 B and the turn-on of the high supply voltage V CCH  is not yet completed.  
         [0124]    In addition, in the same way as the first embodiment, the architecture in the third embodiment facilitates fast start-up of the system  1 , because the mute signal MUTE is flexibly deactivated to allow the provision of data clock signal CLK_OUT in response to the activation of the setting completion signal COMPLETE and the high-voltage ready signal HV_READY.  
         [0125]    Furthermore, in the same way as the first embodiment, the architecture in the second embodiment effectively avoids an undesirable image being displayed on the plasma display panel  2  when the master electrical switch of the plasma display system  1  is turned off. When the master electrical switch of the display system  1  is turned off, the mute signal MUTE is activated in response to the turned-off of the high supply voltage V CCH . The activation of the mute signal MUTE effectively avoids an undesirable image being displayed on the plasma display panel  2  after the turn-off of the high supply voltage V CCH .  
       Fourth Embodiment  
       [0126]    In a fourth embodiment, the mute signal generator  16  is replaced with a mute signal generator  16 C shown in the FIG. 11. T he mute signal generator  16 C may be implemented within the system  1  in any of the first to third embodiments. The mute signal generator  16 C generates the mute signal MUTE in response to the turn-on of the logic circuit supply voltage V CCL  instead of the initial setting signal INT_SET.  
         [0127]    The mute signal generator  16 C, which is provided with the NAND gate  162  and the resistor  163  in the same way as the mute signal generator  16 , includes an initial setting completion detector circuit  161 C instead of the initial setting completion detector circuit  161 .  
         [0128]    The initial setting completion detector circuit  161 C produces the setting complete signal COMPLETE in response to the turn-on of the logic circuit supply voltage V CCL . The initial setting completion detector circuit  161 C activates the setting complete signal COMPLETE upon the turn-on of the logic circuit supply voltage V CCL  till the transfer of the initial setting signal INT_SET is completed. The initial setting completion detector circuit  161 C deactivates the setting complete signal COMPLETE upon the turn-off of the logic circuit supply voltage V CCL .  
         [0129]    In this embodiment, the start-up of the system  1  is achieved as described in the following. In response to the turn-on of the master electrical switch of the system  1 , the logic circuit power supply  20  turns on the logic circuit supply voltage V CCL . In response to the turn-on of the logic circuit supply voltage V CCL , the initial setting completion detector circuit  161 C deactivates the setting completion signal COMPLETE. The NAND gate  162  activates the mute signal MUTE in response to the deactivation of the setting completion signal COMPLETE. The activation of the mute signal MUTE disables one of the input video data signal VIDEO_IN, the output of the data clock signal CLK_OUT, and the video data signal VIDEO_OUT, or disables the data electrode driver  8  to avoid an undesirable image being displayed on the panel  2 .  
         [0130]    In the meantime, the high-voltage power supply  18  is turned on, and the high-voltage ready signal HV_READY is activated by the voltage monitor circuit  181  in response to the turn-on of the high supply voltage V CCH .  
         [0131]    The completion detector circuit  161 C activates the setting complete signal COMPLETE when the transfer of the initial setting signal INT_SET is completed.  
         [0132]    In response to both of the setting complete signal COMPLETE and the high-voltage ready signal HV_READY being activated, the mute signal MUTE is deactivated. The deactivation of the mute signal MUTE allows the data electrode driver  8  to drive the plasma display panel  2  to display a desired image thereon.  
         [0133]    The aforementioned architecture in the fourth embodiment effectively avoids an undesirable image being displayed when the system  1  is started up. The mute signal MUTE is activated upon the turn-on of the logic circuit supply voltage V CCL , and is deactivated after the initial setting of the video data signal processor is completed and the high supply voltage V CCH  is turned on. This effectively avoids the erroneous display of an undesirable image on the plasma display panel  2 , because the data electrode driver  8  is substantially disabled while any one of the initial setting of the PDP video data signal circuitry  14 B and the turn-on of the high supply voltage V CCH  is not yet completed.  
         [0134]    Furthermore, in the same way as the first embodiment, the architecture in the fourth embodiment effectively avoids an undesirable image being displayed on the plasma display panel  2  when the master electrical switch of the plasma display system  1  is turned off. When the master electrical switch of the display system  1  is turned off, the mute signal MUTE is activated in response to the turned-off of the high supply voltage V CCH . The activation of the mute signal MUTE effectively avoids an undesirable image being displayed on the plasma display panel  2  after the turn-off of the high supply voltage V CCH .  
         [0135]    In this embodiment, the setting completion detector circuit  161 C may determine the timing of the deactivation of the setting complete signal COMPLETE by counting the period necessary for the transfer of the initial setting signal INT_SET in synchronization with a clock signal. The necessary period may include a margin.  
         [0136]    Although the invention has been described in its preferred form with a certain degree of particularity, it is understood that the present disclosure of the preferred form has been changed in the details of construction and the combination and arrangement of parts may be resorted to without departing from the spirit and the scope of the invention as hereinafter claimed.