Abstract:
Measurement of load current when a digitally controlled power supply is in a constant voltage mode and of voltage when it is in a constant current mode is achieved by dropping the current represented by the digital current selection signal in one case and the voltage represented by the digital voltage selection signal in the other case until the power supply would change its mode of operation as indicated by comparators. Actual change of mode is prevented by delaying or interrupting the application of the digital selection signals to their respective regulation circuits.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an improved apparatus for measuring the current provided by a digitally controlled power supply when it is operating in a constant voltage mode and/or measuring the voltage provided when it is operating in a constant current mode. When the power supply operates in a constant voltage mode, voltage regulation means maintain the output voltage at a value represented by a digital voltage selection signal in response to the difference between the voltage represented by that signal and the output voltage; and when the power supply operates in a constant current mode, current regulation means maintain the output current at a value represented by a digital current selection signal in response to the difference between the current represented by that signal and the actual output current. As a power supply cannot operate in both modes at the same time, the voltage regulation means disables the current regulation means when the output current is less than that represented by the digital current selection signal, and the current regulation means disables the voltage regulation means when the output voltage is less than that represented by the digital voltage selection signal. The voltage regulation means and the current regulation means each provide a given mode signal when they are in control of the power supply. 
     Measurement of the output current when the power supply is operating in a constant voltage mode may be achieved by an ammeter, which is expensive and cumbersome, or it may be achieved by changing the digital current selection signal so as to reduce the current it represents until the power supply changes to a constant current mode and noting the current represented by the digital current selection signal at that time. Similarly, measurement of the output voltage when the power supply is operating in a constant current mode may be achieved by a voltmeter, which is expensive and cumbersome, or it may be achieved by changing the digital voltage selection signal so as to reduce the voltage it represents until the power supply changes to a constant voltage mode and noting the voltage represented by the digital voltage selection signal at that time. In many applications, changing the mode of operation of the power supply as is required by these methods of measuring current and voltage is highly objectionable. 
     BRIEF DESCRIPTION OF THE INVENTION 
     This invention enables measurement of the output voltage or current of a power supply without voltmeters or ammeters and without changing the mode of operation of the power supply. It also avoids the considerable expense of additional digital-to-analog converters. These results are achieved by provision of a first comparator having its inputs respectively connected so as to respond to a signal corresponding to the output current represented by the digital current selection signal and a signal corresponding to the actual output current. A second comparator is provided having its inputs respectively connected so as to respond to a signal corresponding to the output voltage represented by the digital voltage selection signal and a signal corresponding to the actual output voltage. Thus, when the digital current selection signal is changed so as to represent a current that is less than the output current, the output of the first comparator changes state; and when the digital voltage selection signal is changed so as to represent a voltage that is less than the output voltage, the output of the second comparator changes state. In addition, means are provided for preventing changes in the digital current selection signal that are made so as to measure output current in the manner previously described from affecting the current regulation means so as to cause it to change the mode of operation; and means are provided for preventing changes in the digital voltage selection signal that are made so as to measure output voltage in the manner previously described from affecting the voltage regulation means so as to cause it to change the mode of operation. The current or voltage at which such changes in mode would otherwise occur are indicated by the changes in state of the first and second comparators. 
     In a preferred embodiment of the invention, the operator does not have to indicate whether current or voltage is to be measured but only presses a measurement key so as to produce a measurement signal indicating that one measurement or the other is to be made. Means are provided for changing the digital current selection signal as required to make a current measurement in response to the measurement signal and a mode signal indicating that the power supply is in a constant voltage mode; and means are provided for changing the digital voltage selection signal as required to make a voltage measurement in response to the measurement signal and a mode signal indicating that the power supply is in a constant current mode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a DC power supply utilizing a computer for making current and voltage measurements in accordance with this invention; 
     FIG. 1A is a schematic diagram of an alternative circuit for a portion of FIG. 1; FIGS. 2A and 2B are graphs used in explaining the operation of the power supply when it is measuring output current; 
     FIGS. 3A and 3B are graphs used in explaining the operation of the power supply when it is measuring output voltage; 
     FIG. 4 is a flow chart indicating the steps taken by the microcomputer of FIG. 1 in making a current or voltage measurement; 
     FIGS. 5 and 6 together form a schematic diagram of a DC power supply utilizing a circuit for making current or voltage measurements in accordance with this invention; and 
     FIG. 7 is a series of graphs used in explaining the operation of the circuit of FIG. 5. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Although the invention will now be described in connection with a power supply in which regulation of a DC output voltage or current is achieved by varying the value of a resistive impedance, it will be understood that it could be used with a power supply having a different type of regulation or one that produces a regulated output AC voltage or current. 
     In FIG. 1, a source 2 of unregulated DC voltage which may be derived by rectification of line voltage from a source, not shown, is connected between input terminals 4 and 6. In this particular illustration, a means for reducing the unregulated DC voltage so as to provide regulation is the collector-emitter path of an NPN transistor V R  which is connected in series with a current metering resistor R M  between the terminal 4 and an output terminal 8. A load R L  is connected between the output terminal 8 and an output terminal 10, the latter being connected to the input terminal 6. A bias voltage source shown as being a battery B is connected between the output terminal 8 and the base of the transistor V R  via a current limiting resistor 12. The unregulated DC voltage supplied by the source 2 is larger than any DC voltage that is to appear across the output 8, 10 and is reduced by the voltage drop across the resistance of the transistor V R  so as to produce the desired amount of voltage across the load R L  or cause the desired amount of current to flow through it. 
     When the power supply is operating in a constant voltage mode, the value of the resistance of the collector-to-emitter path of the transistor V R  is controlled by applying a suitable voltage to its base electrode 14 with the following circuitry. The desired value of output voltage is typed or otherwise identified at a controller 16 and supplied via a suitable interface 18 to a computer 20 within the DC supply. The computer 20 provides a corresponding digital voltage selection signal to its voltage register 22, which is shown separately for ease in illustration. A digital-to-analog converter (DAC) 24 that provides an analog voltage selection signal is connected between the output of the voltage register 22 and a non-inverting input of a differential amplifier 26 via a low pass filter 28. Monitoring of the output voltage could be done directly, but in order to make the monitoring voltage have the same range as the analog voltage selection signal with which it is compared, it is customary to obtain a monitored voltage value at the junction J of two resistors 30 and 32 that are connected in series between the output terminals 8 and 10. The junction J is connected to the inverting input of the differential amplifier 26, and its output is connected to the base electrode 14 of the transistor V R  via a diode 34. Whenever the monitored voltage at the junction J is greater than the analog voltage selection signal applied to the non-inverting input of the amplifier 26 via the filter 28, the output of the amplifier 26 is negative so that it can pass through the diode 34 to the base electrode 14 of the transistor V R . The negative output of the amplifier 26 causes the resistance in the collector-to-emitter path of V R  to be sufficient to make the output voltage have the selected value. 
     When the power supply is operating in a constant current mode, the value of the resistance of the collector-to-emitter path of the transistor V R  is controlled by applying a suitable voltage to its base electrode under the control of the following circuitry. The desired value of current is typed or otherwise identified at the controller 16 and placed in digital form in a current register 36 that is usually part of the computer 20 but is shown separately for ease in illustration. A digital-to-analog converter (DAC) 38 that provides an analog current selection signal is connected between the output of the current register 36 and a non-inverting input of a differential amplifier 40 via a low pass filter 42. Monitoring the output current flowing to the load R L  is done by grounding the end of the metering resistor R M  that is connected to the output terminal 8 so that the voltage at the other end is proportional to the output current. This end of the resistor R M  is connected via an amplifier 41 to the inverting input of the differential amplifier 40, and its output is connected to the base electrode 14 of the transistor V R  via a diode 43. When the current produces a monitored voltage across the metering resistor R M  that is greater than the analog current selection signal applied to the non-inverting input, the output of the amplifier 40 is negative so as to pass through the diode 43 to the base electrode 14 of the transistor V R  and cause the resistance of the collector-to-emitter path of V R  to be sufficient to make the output current have the selected value. 
     It is impossible to have constant voltage operation and constant current operation at the same time so that the resistance of the transistor V R  is generally under the control of the differential amplifier 40 or under the control of the differential amplifier 26. Assume, for example, that the power supply of FIG. 1 is operating in a constant voltage mode. For output currents that are less than that corresponding to the analog current selection signal applied to the non-inverting input of the differential amplifier 40, the output of that amplifier is positive so that it cannot pass through the diode 43 to the base 14 of the transistor V R . Thus, only the differential amplifier 26 is controlling the resistance of V R  so as to regulate the output voltage in the manner just described. Now let the current increase to a value such that the monitored current voltage at the inverting input of the differential amplifier 40 is equal to or greater than that corresponding to the analog current selection signal. The output of the differential amplifier 40 becomes negative so that it now passes through the diode 43 to the base electrode 14. This causes the monitored voltage at J to be less than the analog voltage selection signal at the non-inverting input, thereby making the output of the amplifier 26 positive and biasing the diode 34 to cut-off. Thus, only the differential amplifier 40 controls the resistance of V R , thereby keeping the output current at the value determined by the analog current selection signal. An analogous operation takes place if the power supply is operating in a constant current mode and the output voltage increases to a value exceeding that corresponding to the analog voltage selection signal. 
     In order to measure the output current when the power supply is operating in a constant voltage mode, a comparator 44 is provided. Its non-inverting input is connected to the output of the digital-to-analog converter 38 so as to receive the analog current selection signal, and its inverting input is connected to the ungrounded end of the metering resistor R M  so as to receive the output current monitoring voltage. 
     In order that the computer 20 can acquire the required information, the respective mode signals CV and CI of the differential amplifiers 26 and 40 and the outputs of the comparators 44 and 46 are connected to different inputs of a multiplexer 48 which is coupled to the computer 20 in such a manner that the computer can selectively acquire the signal at any of the aforementioned inputs. 
     OPERATION OF FIG. 1 
     The operation of the power supply schematically illustrated in FIG. 1 will now be explained by reference to the graphs of FIGS. 2A, 2B, 3A and 3B as well as to the flow chart for the computer 20 that is shown in FIG. 4. A program that is consistent with the flow chart for a computer including the Texas Instrument microprocessor TMS 9981, a ROM for storing the instructions for the microprocessor, and a RAM for storing data is presented at the end of the specification. 
     Should it be desired to make a measurement, it is not necessary to decide whether the power supply is in a constant voltage or a constant current mode so as to know whether to measure current or voltage. The start key on the controller 16 is simply depressed as indicated at 50 in FIG. 4, and the resulting signal causes a decision to be made, block D 0 , as to whether the power supply is operating in a fault mode, i.e., in neither constant current or constant voltage. If the answer is YES, the measurement process is stopped, block 51. If the answer is NO, a decision, D 1 , is made as to whether or not the power supply is in a constant voltage mode. The computer 20 determines this from the inputs of the multiplexer 48 that are respectively connected to the outputs of the differential amplifiers 40 and 26. If the power supply is in a constant voltage mode, the output CV of the differential amplifier 26 will be negative and the answer from the block D 1  is YES. The current measurement is then started. 
     Before proceeding further along the flow chart of FIG. 4, attention is now called to the graphs of FIGS. 2A and 2B. In FIG. 2A, V S  is the selected output voltage of the supply that corresponds to the digital voltage selection signal provided by the computer 20 at the voltage register 22; I S  is the selected output current of the supply that corresponds to the digital current selection signal provided by the computer 20 at the current register 36; and the dashed vertical line I L  is the actual output current to be measured as determined by the load line 53. In FIG. 2B, the solid line 54 represents various values of the analog current selection signal that will appear at the output of the digital-to-analog converter 38 during the current measurement process. The voltage R S  of the analog current selection signal corresponds to the selected output voltage V S . The current monitoring voltage produced at the ungrounded end of the metering resistor R M  by the current I L   is indicated by the dashed line 55, and the actual voltage applied to the non-inverting input of the differential amplifier 40 because of the action of the low pass filter 42 is indicated by the dash-dot line 56. 
     For reasons that will be explained, the computer 20 changes the value of the digital current selection signal at the current register 36, block 58 of FIG. 4, so as to cause the analog current selection signal 54 to increase to a value such as R 1  which corresponds to I 1  in FIG. 2A. During this time, the state of the comparator 44 is high so that the answer of decision block D 2  is NO. The digital current selection signal is then decreased by one step, block 60, so as to cause the analog current selection signal to decrease to a value R 2 . This loop is repeated so as to lower the analog current selection signal one step at a time through values R 3 , R S  and R 4 . In going from R S  to R 4 , however, the signal 54 crosses below the monitored current voltage 55 at the ungrounded end of R M  so as to cause the output of the comparator 44 to become low and make the answer of D 2  YES. This also happens if the selected value of current is zero. 
     The computer 20 then provides the original digital current selection signal, which has been stored, to the current register 36 so that the analog current selection signal once again has a value R S . Block 64 indicates that the computer 20 then supplies the last programmed digital current selection signal, which corresponds to the analog current selection value R 4  and a current I 4 , to a display 66 or to any other point. I 4  is the measured current. Because of the exaggeration in the stepped changes in the analog current selection signal 54 produced by a unit change in the digital signal, the current I 4   appears to be far from the current I L  that actually exists, but in an actual case the steps would be much smaller so that the measured value of current would be very close to I L . 
     Because the actual analog current selection signal 56 applied to the non-inverting input of the current differential amplifier 40 does not drop below the current monitor voltage 55, the output of the amplifier 40 does not become negative so as to undesirably change the power supply to a constant current mode. It can be seen, however, that if the analog current selection signal were first dropped from R S  to R 4  the analog current selection signal 56 actually applied to the differential amplifier 40 would drop below the current monitor voltage 55 so as to undesirably change the power supply to a constant current mode. 
     As an obvious variation, it should be noted that programmed digital current selection values other than the last one could be used, e.g., the next-to-last value which would correspond to the analog value R S  in which case the measured current would be I S . 
     Should the decision block D 1  indicate that the power supply is not in a constant voltage mode, the output voltage is measured. A similar procedure is followed and blocks at the righthand side of FIG. 4 that correspond in function to the blocks at the lefthand side are indicated by the same designations primed. The original selected values of voltage and current, V S  and I S , are shown in FIG. 3A as being the same as before, but the load line 59 is seen to be such that the power supply is in a constant current mode at the value I S . The actual output voltage to be measured is indicated by the dashed line at V L . In FIG. 3B, the solid line 68 is the analog voltage selection signal at the output of the digital-to analog converter 24, the dashed line 70 is the voltage monitor voltage at the junction J of FIG. 1, and the dash-dot line 72 is the analog voltage selection signal as it appears at the non-inverting input of the voltage differential amplifier 26. The computer 20 first increments the digital voltage selection signal so as to produce the analog voltage selection signal r 1 . The computer 20 then decrements the digital voltage selection signal in minimum units so as to cause the analog voltage selection signal to successively pass through the values r 2 , r 3 , r s , r 4  and r 5  which correspond to the voltages in FIG. 3A having the same subscripts. Between r 4  and r 5 , the analog voltage selection signal 68 drops below the monitor voltage 70 so that the voltage comparator 46 changes state. The digital voltage selection signal is restored to its original value so that the analog voltage selection signal is also restored to its original value r s . Since the last programmed digital value corresponds to the analog value r.sub. 5, the voltage corresponding to it, V 5 , is the value of the measured voltage. The voltage V 4  could also be used. 
     FIG. 1A illustrates another means for preventing the changes in programmed voltage and current required for the measurements of current and voltage from changing the mode of operation of the power supply. Switches S 5  and S 6  are respectively connected between the outputs of the DACs 24 and 38 and the ungrounded sides of capacitors C 1  and C 2  so as to form sample and hold circuits. The outputs of the DACs 24 and 38 are also respectively connected to the non-inverting inputs of the amplifiers 26 and 40. The switches S 5  and S 6  are normally closed. When current is being measured, the computer 20 can open S 6  so as to let the selected current reference voltage across the capacitor C 2  control the current amplifier 40; and when voltage is being measured, the computer 20 can open the switch S 5  so as to let the selected voltage reference across the capacitor C 1  control the voltage amplifier 26. 
     FIGS. 5 and 6 
     Reference is now made to the DC power supply illustrated in FIGS. 5 and 6 wherein a circuit is used in place of the computer 20 of FIG. 1 to perform the functions required to make current and voltage measurements in accordance with this invention. The only difference in function is that the digital current and voltage selection signals, and hence their analog counterparts, are not increased before decreasing them. Components performing the same functions as in FIG. 1 are designated in the same manner. 
     In FIG. 5, a counter U 1  provides the digital current selection signal to the DAC 38 which supplies the analog current selection signal for the desired maximum output current to the differential amplifier 40, FIG. 6, via the low pass filter 42. The output of U 1  is also connected to the input of a latch U 2  so that the output of U 1  can be retained while a current measurement is being made. Similarly, a counter U 3  provides the digital voltage selection signal to the DAC 24 which supplies the analog voltage selection signal for the desired maximum output voltage to the differential amplifier 26 via the loss pass filter 28. The output of U 3  is also connected to the input of a latch U 4  so that the output of U 1  can be retained while a voltage measurement is being made. 
     Selecting the desired output current is achieved by closing a switch S 1  so as to supply clock pulses from a clock 74 to one input of an OR gate U 5 . As will be explained, the other input is low when a desired current is being selected so that the clock pulses pass through the OR gate U 5  to the clock input of the counter U 1  and cause it to count up or down depending on whether the output of a NAND gate U 6 , which is connected to the UP/DOWN input of U 1 , is low or high. As will be explained, one input of U 6  will normally be high so that the +V volts bias applied to the other input via a resistor 75 from a bias supply 76 causes the output of U 6  to be low and make U 1  count up. In order to make it count down, a switch S 2  is provided for grounding the other input of U 6 . 
     Selecting the desired output voltage is achieved in a similar manner. Closing a switch S 3  connects clock pulses from the clock 74 to one input of an OR gate U 7 , and because the other input is low, for reasons that will be subsequently explained, the clock pulses will pass through U 7  to the clock input of U 3 . As before, the output of U 6  is low so that U 3  counts up unless S 2  is closed so as to make it count down. 
     Measuring current or voltage is accomplished by the following circuit. A +V volts is applied via a resistor 77 to an uncoupled input of a NAND gate U 8  that is cross-coupled with a NAND gate U 9  so as to form a flipflop FF. That same input is connected via a one-shot multivibrator 79 to a switch S 4  that has one terminal connected to ground. The uncoupled input of U 9  is connected to the output of a NOR gate U 10  having its inputs respectively connected to the outputs of the comparators 44 and 46. Note that the inputs of the comparators 44 and 46 are connected in a reverse manner from FIG. 1 and that their outputs are respectively connected via inverters 80 and 82 to the load inputs of U 1  and U 3 . A resistor 44&#39; is connected between two inputs of the comparator 44 and a slider in contact with the resistor 44&#39; is connected to a point of voltage -V. Similarly a resistor 46&#39; is connected between two inputs of the comparator 46 and a slider in contact with the resistor 46&#39; is connected to a point of voltage -V. The sliders are respectively adjusted so that the comparators 44 and 46 respectively change state at values of the output current and output voltage that are slightly less than the corresponding analog current and voltage selection signals. 
     The output of U 8  is respectively connected to inputs of AND gates U 11  and U 12  so that as long as the output of U 8  is low, as shown, the outputs of the AND gates will be low. The outputs of U 11  and U 12  are respectively connected to inputs of U 5  and U 7  that, as previously explained, are respectively involved in selection of the output current and voltage of the power supply. One input of each of U 11  and U 12  is connected to the clock 74. A third input of U 11  is connected to the output of the current amplifier 40 so as to receive the mode signal CI, and a third input of U 12  is connected to the output of the voltage amplifier 26 so as to receive the mode signal CV. Thus, if the power supply is in a constant voltage mode, the clock pulses will pass through U 11  to U 5  and through it to the clock input of U 1  ; and if the power supply is in the constant current mode, the clock pulses will pass through U 12  and U 7  to the clock input of U 3 . 
     It should also be noted that the output of U 8  is connected to the clock inputs of U 2  and U 4  so as to cause them to respectively latch the digital current and voltage selection values that correspond to the selected output current and voltage when U 8  goes high. 
     The operation of the circuit of FIGS. 5 and 6 will now be explained with reference to the graphs of FIG. 7. Assume that the power supply is operating in a constant voltage mode. When the switch S 4  is closed, the states in FF reverse from those shown. As seen in graph A, the output of U 8  goes high and, because CI is high, graph B, U 11  is enabled to pass clock pulses via U 5  to U 1 . The clock pulses shown in graph C are applied to the clock input of U 1  as shown in graph D. U 8  going high causes U 2  to latch the digital current selection signal at the output of U 1 . Because the output of the current comparator 44 is low, graph E, this value is not loaded into U 1 . The output of U 9  now being low causes U 6  to make U 1  count down, graph F. When the digital current selection signal at the output of U 1  lowers the analog current selection signal at the output of the DAC 38 sufficiently to cause the comparator 44 to change from a low state to a high state, the digital value at the output of U 1  representing the measured current is transferred to a latch U 13 , and because a low state is applied to the load input of U 1 , the former digital current selection value at the output of U 2  is transferred to the output of U 1  so that the power supply continues to operate in a constant voltage mode and at the same voltage. The duration of the output pulse from the one-shot multivibrator 77 is so short that the reduction in the digital output of U 1  does not change the power supply to a constant current mode because of the previously explained action of the low pass filter 42. 
     Should the power supply be in a constant current mode when S 4  is closed to initiate a measurement, the following sequence of events takes place. U 8  goes high as before so as to cause U 4  to latch the digital voltage selection signal at the output of U 3 . Because CV is high, U 12  will conduct clock pulses from the clock 74 to the clock input of U 3  via U 7 . The output of U 9  goes low, causing U 6  to go high, U 3  to count down, and the analog voltage selection signal at the output of DAC 24 to drop. When this drop causes the output of the comparator 46 to become high, U 14  outputs the digital voltage selection signal then at the output of U 13 . The signal corresponds to the measured output voltage. At the same time, a low state is applied to the load input of U 3  so as to make it transfer the original value of the digital voltage selection signal at the output of U 4  to the DAC 24 so that constant current operation can resume at the same value of current. ##SPC1##