Abstract:
A charge transfer circuit, such as a charge coupled device or other bucket brigade device, which incorporates an amplifier to assist with charge transfer.

Description:
RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 60/809,485, filed on May 31, 2006. The entire teachings of the above application are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by ‘clock’ voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability. 
     Charge-domain circuits are implemented as charge-coupled devices (CCDs), as Metal Oxide Semiconductor (MOS) bucket-brigade devices (BBDs), and as bipolar BBDs. The present invention pertains primarily to MOS BBDs; it also has application to CCDs, in the area of charge-packet creation. Note that all circuits discussed below assume electrons as the signal-charge carriers, and use N-Channel Field Effect Transistors (NFETs) or N-channel CCDs for signal-charge processing. The identical circuits can be applied equally well using holes as charge carriers, by employing PFETs or P-channel CCDs and with reversed signal and control voltage polarities. 
     In MOS BBDs the charge packets are stored on capacitors. Charge transfer from one storage capacitor to the next occurs via a FET connected in common-gate configuration. The process of charge transfer in a BBD is explained with the aid of  FIG. 1  and  FIG. 2 . These figures omit many practical details, but they suffice to show the essential features of charge transfer in conventional BBDs. 
       FIG. 1  shows the essential circuit elements for a BBD-type charge transfer. In  FIG. 1  V X  is an input voltage applied to the first terminal of capacitor  1 . The second terminal of capacitor  1  and the source terminal of FET  2  are connected at node  4 . The gate of FET  2  is connected to a voltage V G , presumed in this discussion to be held constant. The drain of FET  2  and first terminal of load capacitor  3  are connected at node  5 . The other terminal of load capacitor  3  is connected to circuit common (‘ground’). 
       FIG. 2  shows voltage waveforms associated with the circuit of  FIG. 1 . At the beginning of a charge-transfer cycle V X  is at a high voltage  21 ; node  5  has been initialized to a relatively high voltage  23 ; and node  4  to a lower voltage  22 . For this basic explanation, it is assumed that voltage  22  is more positive than V G −V T , where V T  is the threshold of FET  2 . Under these conditions FET  2  is biased below threshold, so no significant current flows through it. 
     The charge transfer is initiated at time t 1  by lowering V X  towards a more negative voltage. Initially, V 4 , the voltage of node  4 , follows VX in a negative direction. At time t 2 , V 4  becomes equal to V G −V T , causing FET  2  to turn on. The resulting current flow through FET  2  limits further negative excursion of V 4 . At time t 3  V X  reaches its lower value  24 . Current continues to flow through FET  2  into capacitor  1 , causing node  4  to charge in a positive direction. As V 4  approaches V G −V T , the current through FET  2  diminishes. V 4  settles towards V G −V T  at a continuously-diminishing rate, reaching voltage  26  at time t 4 . At t 4  V X  is returned to its original voltage. This positive-going transition is coupled through capacitor  1  to node  4 , causing FET  2  to turn off altogether and ending the charge transfer. 
     During the events described, current flows from capacitor  3  through FET  2  into capacitor  1 . The integral of this current flow constitutes the transferred charge, Q T . Q T  can be expressed in terms of the voltage changes and respective capacitances at V X , node  4 , and node  5 . Neglecting the device capacitances of FET  2 , the charge delivered to capacitor  3  can be expressed in terms of the voltage change across it, using the well-known expression Q=CV. Identifying the capacitance of capacitor  3  as C 3  and the voltage change at node  5  as ΔV 5 , we have:
 
 Q   T   =C   3   ΔV   5   Equation 1
 
Note that with the waveforms shown, ΔV 5 =(voltage  25 −voltage  23 ) is negative, so Q T  is negative; i.e., it consists of electrons.
 
     Q T  can also be expressed in terms of the voltage change across capacitor  1 . Using similar notation, we have:
 
 Q   T   =C   1 ( ΔV   X   −ΔV   4 )  Equation 2
 
The relevant voltage changes occur between the beginning and the end of charge transfer; thus, for the waveforms of  FIG. 2 ,
 
 ΔV   X =(voltage 24−voltage 21)  Equation 3
 
and
 
 ΔV   4 =(voltage 26−voltage 22)  Equation 4
 
     For the conditions described, voltage  22  is a constant (it is an initial condition). If node  4  were to settle perfectly to its nominal asymptote V G −V T , which is also a constant, then ΔV 4  would be a constant. In that case, Equation 2 could be re-written as:
 
 Q   T   =C   1   ΔV   X +(constant)  Equation 5
 
This expression represents an idealization of the charge-transfer operation which is perfectly linear. For the realistic case in which settling of node  4  is imperfect, Equation 2 can be re-formulated as:
 
 Q   T   =C   1   [ΔV   X −(voltage 26)]+(constant)  Equation 6
 
From this form it can be seen that any non-linearity or incomplete settling of charge transfer is attributable to voltage  26 , the voltage of node  4  at the end of charge-transfer.
 
     Charge-transfer operation essentially similar to that described above is used in all conventional BBDs. Practical details, such as the means of establishing the described initial conditions, realistic clock waveforms, etc. are not pertinent to the present invention and will not be further described here. The same charge-transfer technique is also used to provide charge-packet input in many CCD signal-processing circuits. (Subsequent charge transfers in CCDs use a different principle, not described here.) 
     The mode of charge-transfer described above will be termed “passive” charge transfer in the following discussion. This term refers to the fact that, during the charge-transfer process, the gate voltage V G  applied to FET  2  is static, not actively controlled in response to the charge being transferred. (In practical BBDs, V G  is typically clocked rather than static, but it is not responsive to the charge being transferred.) This passive charge transfer process is subject to two important error sources. 
     The first error source derives from the nature of the settling of node  4  during the t 3 -to-t 4  interval in  FIG. 2 . During this time, as described above, node  4  is charging in a positive direction, reducing the gate-source voltage of FET  2 . This decreasing gate-source voltage causes a decrease in current through the FET. This declining current in turn results in a declining rate of charging of node  4 . This process is very non-linear in time, and also depends in a non-linear manner on the size of charge packet being transferred. As a result, the residual voltage  26  in  FIG. 2  (and Equation 6) depends non-linearly on Q T , resulting in an overall non-linear charge-transfer operation. Moreover, with practical circuit values, the settling time of node  4  is unacceptably long for high-speed circuit operation. Passive charge-transfer is thus both slow and non-linear; in many applications these limitations degrade speed and accuracy unacceptably. 
     The second error source arises due to the change ΔV 5  in FET drain voltage V 5 . As shown above (Equation 1) this change is proportional to Q T . FETs exhibit a feedback effect, in which a variation in drain voltage causes, in effect, a variation in threshold voltage V T . Thus the “final” voltage V G −V T , towards which V 4  settles, is not in fact a constant (as in the idealized discussion above) but a function of the charge being transferred. This effect is equivalent to a dependency of voltage  26  on the size of Q T : larger |Q T | results in a more-negative value of voltage  26 . This effect amounts to a charge-transfer gain of less than 100%. It typically includes a small non-linear component as well, exacerbating the non-linearity issue discussed above. 
     SUMMARY OF THE INVENTION 
     Embodiments of the present invention provide a charge-transfer circuit in which the effects of the two error sources described above are significantly reduced. In contrast to the passive charge transfer used in conventional BBDs, the charge transfer method of the present invention is termed “boosted”. The performance of a boosted charge-transfer circuit is sufficiently improved over that of the passive circuit that it makes high-speed, high-precision applications feasible. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention. 
         FIG. 1  is a simplified diagram of a charge transfer circuit. 
         FIG. 2  illustrates voltage waveforms associated with  FIG. 1 . 
         FIG. 3  is a boosted charge transfer circuit according to aspects of the invention. 
         FIG. 4  illustrates voltage waveforms for the circuit of  FIG. 3 . 
         FIG. 5  is a boosted charge transfer circuit incorporating a CMOS amplifier. 
         FIG. 6  is another boosted charge transfer circuit using an amplifier that reduces Miller capacitance. 
         FIG. 7  is a boosted charge transfer circuit that uses an NFET as a common gate amplifier. 
         FIG. 8  is a boosted charge transfer circuit that uses resistor elements to dampen the circuit response. 
         FIG. 9  is a boosted charge transfer circuit that provides greater control over start and end of current flow. 
         FIG. 10  is a boosted charge transfer circuit using an FET that controls power consumption. 
         FIG. 11  is a boosted charge transfer circuit that provides a voltage-to-charge sample-and-hold function. 
         FIG. 12  illustrates voltage waveforms associated with the circuit of  FIG. 11  in the case of static input voltage. 
         FIG. 13  illustrates voltage waveforms associated with the circuit of  FIG. 12  in the case of time-varying input voltage. 
         FIGS. 14A and 14B  are a circuit diagram and cross-sectional device structure diagram of a boosted charge transfer circuit which provides input charge to a CCD. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A description of preferred embodiments of the invention follows. 
     The present invention provides a charge-transfer circuit in which the effects of the two error sources described above are significantly reduced. In contrast to the passive charge transfer used in conventional BBDs, the charge transfer method of the present invention is termed “boosted”. The performance of a boosted charge-transfer circuit is sufficiently improved over that of the passive circuit that it makes high-speed, high-precision applications feasible. This boosted charge-transfer technique can be understood with the aid of  FIGS. 3 and 4 , which illustrate the basic features of its operation. 
     The elements of  FIG. 3  are the same as similarly-identified elements of  FIG. 1 , except for the addition of amplifier  36  and its reference voltage V R , and the omission of voltage V G . Capacitor  31  in  FIG. 3  corresponds to capacitor  1  in  FIG. 1 , node  34  to node  4 , etc. The added amplifier  36  is the unique feature of this invention; it has moderate voltage gain (typically 10-100) and very high speed. 
     The operating waveforms of this circuit are shown in  FIG. 4 , using the same naming conventions employed in  FIG. 2  (e.g., the voltage of node  34  is called V 34 , etc.). Initial conditions in  FIG. 4  are similar to those in  FIG. 2 . Input voltage V X  starts at a high value,  41 . Drain node  35  is initialized to a high voltage  43 . Source node  34  is initialized to a lower voltage  42 , which is more positive than V R . Because V 34 &gt;V R , amplifier  36  drives its output, node  37 , to a low voltage  48 . Node  37  is also connected to the gate of FET  32 , so a low value of V 37  assures that FET  32  is initially turned off, and no current flows through it. 
     The charge transfer is initiated at time t 1  by lowering V X  towards a more negative voltage. Initially, V 34  follows V X  in a negative direction. At time t 2 , V 34  becomes more negative than V R , causing amplifier  36  to drive its output node  37  to a high voltage. This high voltage turns on FET  32 ; the resulting current through FET  32  limits the negative excursion of node  34 . Amplifier  36  then operates, by feedback via FET  32 , to maintain V 34  slightly below V R . This balance persists until time t 3  when V X  reaches its lower value  44 . The current flowing through FET  32  then charges node  34  positively until t 4 , when V 34  approaches V R . As its input drive (V 34 −V R ) approaches zero, amplifier  36  drives its output voltage  37  towards a lower value  49 , and the current through FET  32  declines rapidly. Finally, at time t 5 , V X  is returned to its original value; this positive-going transition is coupled through capacitor  31  to node  34 , causing amplifier  36  to again drive its output node  37  to a low voltage, turning FET  32  off and ending the charge transfer. 
     As with the passive charge transfer previously described, the current flowing through FET  32  is integrated by capacitor  33 , resulting in the voltage waveform V 35  at node  35 . This integrated current constitutes the transferred charge, Q T . The charge and voltage on capacitor  33  are related just as in Equation 1:
 
 Q   T   =C   33   ΔV   35   Equation 7
 
Where ΔV 35 =(voltage  45 −voltage  43 ).
 
Similarly,
 
 Q   T   =C   31 ( ΔV   X   −ΔV   34 )  Equation 8
 
And by analogy with Equation 6,
 
 Q   T   =C   31   [ΔV   X −(voltage 46)]+(constant)  Equation 9
 
The asymptote towards which V 34  settles is V R , the reference voltage for amplifier  36 . In  FIG. 4  the value of V 34  at the end of charge transfer (time t 5 ) is voltage  46 . As with the passive charge transfer, any difference between voltage  46  and V R  represents an error in the transferred charge. The key difference between the boosted and passive charge transfer lies in the improved precision and speed with which V 34  approaches V R .
 
     In both passive and boosted charge-transfer circuits, the source voltage of the FET (nodes  4  and  34  in  FIGS. 1 and 3  respectively) is charged positively by the FET current after t 3 . This charging results in decreasing gate-source voltage V GS  and FET current I D , as described above. In the passive circuit of  FIG. 1 , the gate voltage V G  is fixed, so the rate of change of V GS  is simply the negative of that of V 4 :
 
 dV   GS   /dt=−dV   4   /dt=−I   D   /C   1   Equation 10
 
In the boosted charge-transfer circuit of  FIG. 3 , the same equation applies (to V 34  and C 31  respectively). However, the gate of FET  32  is not held at a constant voltage, but driven by the output of amplifier  36 , which responds to the voltage at node  34  with gain A (typically 10-100 as mentioned above). Thus the gate-source voltage of FET  32  is:
 
 V   GS   =V   37   −V   34   =−A ( V   34   −V   R ) −V   34   =A[V   R −(1 +A   −1 ) V   34 ]  Equation 11
 
Since V R  is constant, the rate of change of V GS  for the boosted charge transfer circuit of  FIG. 3  is thus:
 
 dV   GS   /dt =−( A +1) dV   34   /dt =−( A+ 1) I   D   /C   1   Equation 12
 
     Comparing Equation 12 to Equation 10 shows that the rate at which V GS  settles is increased by the gain of amplifier  36  compared to the passive case. The time required after t 3  for settling to any given level of precision is similarly reduced. The non-linearity of the final voltage  46  is similarly reduced by approximately the same factor relative to final voltage  26  in  FIG. 2 . 
     In the preceding material, a number of important circuit details were omitted for the sake of clarity in the basic explanation. These details are described in the following paragraphs. 
     As stated above, the gain of the amplifier in a boosted charge transfer circuit, such as amplifier  36  in  FIG. 3 , needs to be high enough to produce a significant improvement in linearity and speed. Voltage gain in the range of 10-100 produces substantial benefits. Significantly lower gain reduces the linearity improvement, and higher gain results in dynamic problems described in more detail below. Charge-transfer settling time is also related to the speed of the amplifier, as discussed below. Thus design of the amplifier is constrained by the dual requirements of medium gain and very high speed. Several practical circuits which satisfy these constraints are described below. 
       FIG. 5  shows a boosted charge-transfer circuit incorporating a basic CMOS amplifier which provides the needed performance. Elements V X , capacitors  51  and  53 , and charge-transfer FET  52  are arranged just as in  FIG. 3 . The amplifier,  36  in  FIG. 3 , is implemented in  FIG. 5  as common-source-connected NFET  56 , and PFET  58  which is connected as a current source with positive supply V DD  and bias voltage V B . Operation of this circuit is just as described in connection with  FIGS. 3 and 4 . The equivalent in  FIG. 5  of amplifier reference voltage V R  in  FIG. 3  is the voltage at node  54  at which the drain current of NFET  56  balances the drain current of PFET  58 . This voltage is slightly above the threshold of NFET  56 . This type of circuit can have voltage gain in the required range. Its speed can be chosen by scaling FETs  56  and  58  and their operating current: larger FETs and more current result in higher speed, with the limit being characteristic of the particular semiconductor fabrication process. 
     While suitable for some applications, the circuit of  FIG. 5  has a significant performance limitation. All charge-transfer circuits add thermal noise to the transferred charge packet. This added noise is often referred to as “kTC” noise, because in simple cases it obeys the law:
 
 Q   n =( kTC ) 1/2   Equation 13
 
where Q n  is the added noise in coulombs, T=absolute temperature, k=Boltzmann&#39;s constant, and C is the capacitor involved in the charge transfer. Equation 13 applies, for example, to the passive charge-transfer circuit of  FIG. 1 , where the pertinent C is that of capacitor  1 , plus the previously-neglected parasitic capacitances at node  4 . (In some cases the noise added by the circuit of  FIG. 1  may be slightly less than the amount indicated by Equation 13.)
 
     In the circuit of  FIG. 5 , the total capacitance contributing to noise generation includes three significant terms: the explicit value of capacitor  51 ; the gate-input capacitance of amplifier FET  56 ; and the capacitance from node  57  to node  54  multiplied by the gain of the amplifier. This latter capacitance term, which is multiplied by the amplifier gain, is sometimes referred to (for historical reasons) as “Miller” capacitance. In  FIG. 5  it consists of the drain-to-gate capacitance of FET  56  plus the gate-to-source capacitance of FET  52 . Even though the device parasitic capacitances of FETs  52  and  56  may be small compared with the value of capacitor  51 , the fact that the Miller capacitance is multiplied by the amplifier gain can make it a significant noise issue in this circuit. 
       FIG. 6  shows a boosted charge-transfer circuit which improves upon the circuit of  FIG. 5  by reducing the Miller capacitance. The amplifier in the circuit of  FIG. 6  consists of the FETs  66  and  68 , serving the same functions as FETs  56  and  58  in  FIG. 5 . In  FIG. 6  a source-follower PFET  69  is added, supplied by a PFET current-source. Because it provides voltage buffering between node  64  and node  70 , the contribution of the drain-to-gate capacitance of FET  66  to the Miller capacitance is largely eliminated. Thus in  FIG. 6  only the gate-source capacitance of FET  62  contributes significantly to the Miller capacitance. The result is a corresponding reduction of kTC-noise generation relative to the circuit of  FIG. 5 . 
       FIG. 7  shows another boosted charge-transfer circuit with reduced Miller capacitance. This circuit is identical to that of  FIG. 5 , except that the NFET  79  is added between the drain of FET  76  and the amplifier output node  77 . FET  79  acts as a common-gate amplifier, with its gate biased at a constant voltage V B2 . The common-source+common-gate composite of FETs  76  and  79  is the well-known “cascode” configuration. Its effect in this application is primarily to reduce the gain from gate to drain of FET  76  while maintaining or increasing gain from node  74  to node  77 . While the drain-gate capacitance of FET  76  is not reduced, the gain which multiplies it is reduced, thus reducing its contribution to kTC-noise generation. 
     One significant problem with the boosted charge-transfer circuit was alluded to above but not detailed there: the dynamic behavior of the circuits so far discussed may exhibit a type of instability which can disrupt the desired linear charge-transfer. This problem arises especially in the case of relatively high amplifier gain, which is otherwise desirable in order to reduce nonlinearity.
 
This dynamic problem arises during the early part of the charge transfer, between t 2  and t 4  in  FIG. 4 . In this region, the closed loop seen in  FIG. 3  from node  34 , through amplifier  36  to node  37 , through FET  32  back to node  34 , exhibits a 2-pole (second-order) gain characteristic. One pole is due to the g m  of the amplifier and the capacitance at node  37 ; the other is due to the g m  of FET  32  and capacitor  1 . It is apparent that second-order loop gain is intrinsic to this basic circuit topology. Because the current through FET  32  starts at zero before t 2 , rises to a peak, and then decays during the t 3 −t 5  interval to a very small value, the circuit does not have a DC “quiescent point” at which stable conditions can be established. When the FET current drops to a sufficiently low level approaching t 5 , then current through the gate-source capacitance of FET  32  swamps the drain-source current, and the second pole is eliminated. Consequently the final settling of the circuit is unconditionally stable. The second-order response during the middle of the charge transfer can result in ‘overshoot’ at nodes  37  and  34 , causing a non-linear disturbance of Q T .
 
     A solution to this problem is shown in  FIG. 8 . This circuit is identical to the basic boosted charge-transfer circuit of  FIG. 3 , with similarly-identified elements, except that the resistors  88  and  89  are added. When appropriately sized, the sum of these resistors adds a zero which partially cancels the second pole mentioned above, thus providing an adequately damped overall response. If the combined resistance is made larger than necessary, it reduces the speed of the charge-transfer operation, reducing the benefit of the boosted circuit. With practical circuit parameters, a significant range exists for an appropriate choice of resistor values. Either resistor  88  or  89  or a combination can be used to achieve the needed effect. 
     In the discussion of  FIGS. 3-4  the initial voltage at node  34  was chosen to assure that FET  32  was turned off. Thus no current flowed through the FET until after t 1  when V X  began changing. Likewise, current flow ended when V X  returned to its initial value. In some applications of boosted charge transfer it is desirable to control the start and end of current flow by other means. One such means is shown in  FIG. 9 . This circuit is identical to the basic circuit of  FIG. 3 , with similarly-identified elements, except for the addition of NFET  98  which is controlled by a logic voltage signal V OFF . When V OFF  is high, FET  98  is turned on, and drives node  97  to near zero volts. Thus node  94  can assume any initial voltage down to zero (or even slightly below zero) without causing FET  92  to turn on (because V GS  of FET  92  is not significantly positive). When V OFF  is set low, then FET  98  is turned off. In this condition the circuit behaves just like that of  FIG. 3 : amplifier  96  can drive node  97  positive whenever the voltage of node  94  is less than V R , turning FET  92  on and allowing current flow. If V 94 &lt;V R  when V OFF  goes low, then amplifier  96  will immediately begin driving node  97  high, initiating current flow. Similarly, setting V OFF  high will terminate charge-transfer regardless of the state of V 94 . Applications of this capability will be discussed below. 
     Consideration of the detailed amplifier circuits in  FIGS. 5 ,  6 , and  7  shows that a FET connected as shown in  FIG. 9  can also be used in each specific case to achieve the results described for the more abstract circuit of  FIG. 9 . 
     In many applications it is desirable to minimize overall circuit power consumption. In a boosted charge-transfer circuit, charge-transfer typically only happens during part of an overall operating cycle, often 50% or less. In  FIG. 4 , for example, current flows only between t 1  and t 5 . During the remainder of the operating cycle, the amplifier (or a switch FET such as FET  98 , just discussed) holds the common-gate charge-transfer FET in an off state. In this state the amplifier is not required to respond to the input signal (at node  94 , for example). Thus the current source or sources which are part of the amplifier can be disabled, eliminating power consumption. If current-flow control via a signal such as V OFF  is used, the same signal can also be used to control power consumption. 
     An example of such a circuit is shown in  FIG. 10 . This circuit is similar to that of  FIG. 5 , with the addition of NFET  109  and PFET  110 , both controlled by the logic voltage signal V OFF . When V OFF  is high, FET  109  holds node  107  at a low voltage, disabling current flow though FET  102 . At the same time, FET  110  is turned off, so no current flows through current-source FET  108 ; thus power consumption due to the amplifier is extinguished. When V OFF  is set low, then FET  110  turns on, enabling current flow through FET  108 ; and FET  109  turns off, allowing node  107  to rise and turn on FET  102 , permitting signal charge to flow from node  104  to node  105 . 
     The circuits of  FIGS. 6 and 7  can be modified in ways similar to the modification just described, to disable charge transfer and eliminate power consumption by their amplifiers during the time when a control voltage V OFF  is asserted. 
     In all the charge-transfer circuits described above, the input signal V X  is represented as an abstract voltage source. Also, the voltage at the charge-transfer FET&#39;s source, node  4  in  FIG. 1  for example, is described as “initialized to voltage  22 ”. Similar abstract initialization is assumed for the circuit of  FIG. 3 . For purposes of understanding the charge-transfer circuit principles discussed so far, this abstract representation sufficed. In actual applications of boosted charge-transfer circuits, however, these abstractions must be replaced by realistic circuitry. An application example is shown in  FIG. 11 , in which the abstract voltage control is replaced by slightly less-abstract switches. In a fully-developed practical circuit, these switches would each be implemented as an NFET, a PFET, or an NFET-PFET combination known as a ‘transmission gate’. The circuit details for controlling these switches are not considered in this discussion. 
       FIG. 11  shows a boosted charge-transfer circuit similar to that of  FIG. 3 , with three additional elements: switches  119 ,  120 , and  121 . In addition, the node driven by V X  in  FIG. 3  is here labeled node  118 . This circuit provides a voltage-to-charge sample-and-hold function, in which an output charge packet Q T  delivered to capacitor  113  is a linear function of the three input voltages V 1 , V 2 , and V 3 . One mode of operation of this circuit is described with the aid of  FIG. 12 . This operation is very similar to that of the circuit of  FIG. 3 , whose waveforms are shown in  FIG. 4 . 
     In  FIG. 12 , three switch states and two voltages are plotted against time. The switch states S 199 , S 120  and S 121  respectively represent the states of switches  119 ,  120 , and  121  in  FIG. 11 . A high value for a switch state indicates that the switch is on, and a low value indicates off. The voltages of nodes  118  and  114  are plotted below the switch states. Six times t 0 −t 5  are identified. Times t 1 −t 5  correspond to the five times identified in  FIG. 4 , emphasizing the similarity of operation of the circuits of  FIG. 3  and  FIG. 11 . Initially, switches  119  and  121  are on; switch  120  is off. Consequently node  118  is connected to V 2 , whose value is identified as  123  in  FIG. 12 ; and node  114  is connected to V 3 , whose value is identified as  122  in  FIG. 12 . Thus voltages  123  and  122  correspond to initial voltages  41  and  42  in  FIG. 4 . 
     At t 0  switch  121  turns off, leaving node  114  at voltage  122  (since no current is yet flowing through FET  112 ). At t 1  switch  119  turns off and switch  120  turns on, connecting node  118  to V 1 . Node  118  charges towards V 1  with a time constant governed by the on-resistance of switch  120 , eventually reaching a settled voltage  124  equal to V 1 . V 118 &#39;s waveform is similar to that of V X  in  FIG. 4 . Similarly, as with V 34  in  FIG. 4 , V 114  initially follows V 118 , then stops when current flows through FET  112 , and eventually settles to a voltage  126  which is very close to V R . At t 5 , all three switches return to their original states, re-connecting node  118  to V 2  and node  114  to V 3 , and ending the charge transfer process. 
     Following the analysis applied to  FIGS. 3 and 4 , we can write an expression for the resulting output charge Q T  which is collected by capacitor  113 . By analogy with Equation 8:
 
 Q   T   =C   111 (ΔV 118   −ΔV   114 )  Equation 14
 
The relevant voltage changes occur between the beginning and the end of charge transfer; thus, for the waveforms of  FIG. 12 :
 
 ΔV   118 =(voltage 124−voltage 123)=( V   1   −V   2 )  Equation 15
 
and
 
 ΔV   114 =(voltage 126−voltage 122)≈( V   R   −V   3 )  Equation 16
 
where the approximation in Equation 16 consists in neglecting the difference between voltage  126  and V R .
 
Combining these equations, we have:
 
 Q   T   =C   111 [( V   1   −V   2 )−( V   R   −V   3 )]  Equation 17
 
     This expression shows that Q T  depends linearly on the four voltages V 1 , V 2 , V 3  and V R , within the approximation in equation 16. The parasitic capacitance and charge transfer associated with switch  121 , and other parasitic capacitances at node  114 , have been neglected in this analysis. Their effect is to add offsets to the expression for Q T , but the result remains linear in the four voltages. 
     The waveforms in  FIG. 12  are implicitly based on the assumption that all four voltages in Equation 17 were static during the time shown.  FIG. 13  shows what happens if V 2  is time-varying while V 1 , V 3  and V R  remain fixed. In this situation, it will be seen that the circuit of  FIG. 11  generates an output charge Q T  which depends on the value of V 2  at the moment when S 121  turns off. Thus this circuit provides a voltage-to-charge sample-and-hold function. 
     For t&lt;t 0  in  FIG. 13 , switches  119  and  121  are turned on. Switch  121  holds node  114  at voltage  132  (equal to the value of V 3 ) as in the foregoing discussion. Switch  119  connects node  118  to the time-varying voltage source V 2 , so that the voltage of node  118  tracks V 2 . (The time constant of switch  119  and capacitor  111  is assumed short enough to be neglected compared to the rate of change of V 2 .) At t 0  switch  121  turns off. Since node  114  is no longer connected to V 3 , it follows node  118  due to coupling through capacitor  111  (note that in  FIG. 12  node  118  was static, so V 114  did not change at this point). Neglecting parasitic capacitances, the voltage across capacitor  111  remains constant and equal to its value at t 0 . Specifically, taking node  118  as the positive terminal of capacitor  111 :
 
 ΔV   C111 =voltage 133−voltage 132 =V   2   [t   0   ]−V   3   Equation 18
 
with V 2 [t 0 ] being the value of V 2  at time t 0 . This condition persists until time t 1 , when switch  119  turns off and switch  120  turns on. Node  118  is then driven towards voltage V 1  (voltage  134 ) as in  FIG. 12 . As in  FIG. 12 , node  114  initially follows node  118 , then stops when current flows through FET  112 , and eventually settles to a voltage  136  which is very close to V R . As above, charge transfer stops at t 5  when the switches return to their initial state. Node  114  is re-connected to V 3  and returns to its initial value  132 . Node  118  is re-connected to V 2 , and settles to V 2 &#39;s then-current value  139 .
 
The voltage across capacitor  111  at the end of charge transfer (t 5 ) is:
 
 ΔV   C111 =voltage 134−voltage 136 =V   1   −V   R   Equation 19
 
     As with the discussion of Equation 1, we note that the amount of charge delivered by capacitor  111  during charge-transfer is simply the change in its voltage multiplied by its capacitance. The initial voltage (before charge transfer) is given by Equation 18, and the final voltage by Equation 19. Thus:
 
 Q   T   =C   111 [( V   1   −V   R )−( V   2   [t   0   ]−V   3 ) ]=C   111 [( V   1   −V   2   [t   0 ])−( V   R   −V   3 )  Equation 20
 
Equation 20 has exactly the same form as Equation 17, with the static value of V 2  in Equation 17 replaced by the sampled value at t 0  in Equation 20. This is the desired sample-and-hold property.
 
Note that, if V 1 , V 3 , and V R  are constant as assumed above, then the voltage-to-charge transfer function of Equation 20 can be written:
 
 Q   T   =−C   111   V   2   [t   0 ]+(constant)  Equation 21
 
If V 2  is static, this circuit can be used to generate a sequence of charge packets of uniform size controlled by V 2 &#39;s value (together with the values of V 1 , V 3  and V R ). If V 2  is time-varying, then the result is sampling of V 2  under control of a (clock) signal S 121 . As Equation 21 shows, the resulting charge packets contain the sampled charge plus a constant term. This constant term is adjustable by varying the values of V 1 , V 3 , and/or V R .
 
In all of the circuits discussed above, the transferred charge Q T  is collected by an output capacitor, for example C 33  in  FIG. 3 . In another application of the boosted charge-transfer circuit, the transferred charge can instead be collected in a storage well of a charge-coupled device (CCD). As just discussed, this capability can be used either for creating a series of constant (adjustable) charge packets, or for producing a series of charge packets which are proportional to samples of a time-varying voltage signal.
 
       FIG. 14A  shows a boosted charge-transfer circuit similar to that of  FIG. 3 , in which the charge-transfer FET and the output capacitor are replaced with CCD elements. V X , capacitor  141 , node  144 , reference voltage V R , amplifier  146  and amplifier-output node  147  are all precisely analogous to their equivalents in  FIG. 3 . The new feature in  FIG. 14A  is CCD  148 , consisting of an input terminal connected to node  144  and three gates  142 ,  143  and  145 . (In a practical implementation, the CCD would typically have additional gates beyond gate  145 . Three gates suffice to describe the function of this circuit.) 
     A cross-section representation of the device structure of CCD  148  is shown in  FIG. 14B . The input terminal consists of diffusion  149  which has opposite conductivity type to the semiconductor substrate  150 . The three gates  142 ,  143  and  145  are adjacent electrodes, separated from the substrate by a gate dielectric layer, and from each other by dielectric-filled gaps. The CCD schematic symbol used in  FIG. 14A  corresponds feature-for-feature with the structure shown in  FIG. 14B . The structure shown is typical of single-poly CCDs; double-poly and other CCD structures are well-known, and could be used as well in the circuit of  FIG. 14A . 
     In  FIG. 14A  node  144  is connected to the input terminal  149  of CCD  148 . This terminal functions like the source of FET  32  in  FIG. 3 . The first gate,  142 , of CCD  148  is connected to amplifier-output node  147 . This gate functions like the gate of FET  32  in  FIG. 3 , by controlling the flow of current from node  144  into the CCD. Clock voltage Φ 1 , when driven to a high voltage, creates a potential well under gate  143 . This well is analogous to the drain of FET  32  together with capacitor  33  in  FIG. 3 : current flowing under gate  142  collects as charge in the well under gate  143 , just as current flowing through FET  32  in  FIG. 3  collects as charge on capacitor  33 . During charge-transfer, clock voltage Φ 2  biases gate  145  off, preventing current from flowing further along the CCD; thus all current flowing under gate  142  is collected in the potential well under gate  143 . 
     The initial condition for the potential well under gate  143  is zero charge. The operation and timing of the circuit of  FIG. 14A  are identical to those of  FIG. 4 , except for the aforementioned difference in the means of collection of transferred charge. At the end of the charge-transfer operation (t 5  in  FIG. 4 ) the transferred charge Q T  has is accumulated under gate  143 , and gate  142  is driven off by amplifier  146 . Subsequently Q T  can be transferred along CCD  148  by appropriate clocking of Φ 1  and Φ 2  using well-known CCD methods which are not part of this invention. 
     All circuits discussed above are shown in single-ended configurations; that is, all voltages are referred to a common reference (‘ground’), and all charge packets can have only one sign. (In the case of electrons as charge carriers, the charge packets are always negative; the maximum packet, in algebraic terms, is zero.) It is common to employ differential circuits in practical circuit applications, to provide symmetrical means of representing variables with either sign, for suppression of second-harmonic distortion, and for other reasons. The charge-transfer circuits discussed above can all be used in so-called ‘quasi-differential’ configurations using a pair of charge packets. In such configurations, the signal is represented as the difference between the two members of the charge-packet pair; each member of the pair also has a bias- or common-mode charge in addition to the signal component. Such circuit configurations are implemented using pairs of the charge-transfer circuits shown, one such circuit to handle each of the members of the charge-packet pair. 
     While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.