Abstract:
The invention discloses an analog content addressable memory (CAM) that employs analog storage cells with programmable analog transfer function capability. The analog CAM scans and/or compares its memory array contents to determine if an analog voltage applied at Vin matches a value stored in the memory array. If the value applied to Vin matches a value stored in the analog CAM, the analog data stored at a different and corresponding location in an analog storage cell is coupled to the Vout output. An analog content addressable memory, comprising a first array A of analog memory cells for storing and generating a VA voltage; and a comparator having a first input for receiving a Vin voltage, a second input for receiving the VA voltage from the first array A of analog memory cells. Analog-to-Digital and Digital-to-Analog Converters comprising an array of analog memory cells.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This application claims priority from U.S. Provisional Application Ser. No. 60/374,843, filed on Apr. 23, 2002. 

   BACKGROUND INFORMATION 
   1. Field of the Invention 
   The invention relates generally to the field of electronic circuits, and more particularly to analog nonvolatile storage. 
   2. Description of Related Art 
   Analog storage devices provide an attractive alternative to storing electronic information in analog form rather than in digital form. The use of electrically erasable programmable read only memory (EEPROM) cells in an analog storage device avoid the necessity to convert an analog waveform to digital representation, reducing the complexity embodied in an integrated circuit as well as decreasing the die dimension. For additional background information on analog storage for voice recording and playback in EEPROM, the reader is referred to “ A Non - Volatile Analog Storage Device Using EEPROM Technology” , by Trevor Blyth et al., ISSCC91/Session 11/Emerging Circuit Technologies/Paper TP 11.7, 1991, page 192. 
   Applications of an analog storage device have evolved from simple telephone message recordings to the recent development of compensation for the temperature characteristics of laser diodes in CD-ROM burners and high-speed optical communication systems. The latter segments of technologies often require the design of a circuit that compensates for temperature variations. For example, the bias currents and modulation currents required to maintain constant output levels from a laser diode in an optical transmitter vary with temperature. 
   Accordingly, it is desirable to design a system that employs a programmable analog transfer function capability for compensating variations, such as temperature fluctuations, in the system. 
   SUMMARY OF THE INVENTION 
   The invention discloses an analog content addressable memory (CAM) that employs analog storage cells with programmable analog storage capability. The analog CAM scans and/or compares the contents of a first memory array to determine if an analog voltage applied at Vin is contained in the memory array. If the value applied to Vin matches a value stored in the first array, the analog data stored at a different and matching location in an analog storage cell of a second array is coupled to the Vout output. The voltages stored in each location of both memory arrays are independently programmable, thus creating a programmable voltage transfer function between input, Vin, and output, Vout. 
   An analog content addressable memory, comprising a first array A of analog memory cells for storing and generating a VA voltage; and a comparator having a first input for receiving a Vin voltage, and a second input for receiving the VA voltage from the first array A of analog memory cells. 
   The present invention advantageously provides analog storages in a content addressable memory for storing analog voltages with a reduced number of storage cells compared to a digital memory and without the need for analog-to-digital or digital-to-analog conversion. 
   Other structures and methods are disclosed in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram illustrating a first embodiment of an analog content addressable memory in a cell structure in accordance with the present invention. 
       FIG. 2  is a block diagram illustrating an n-deep CAM architecture with expanded cell structures in the first embodiment in accordance with the present invention. 
       FIG. 3  is an architectural diagram illustrating a second embodiment of an analog content addressable memory employing two arrays of analog memory cells in accordance with the present invention. 
       FIG. 4  is an architectural diagram illustrating a third embodiment of an analog content addressable memory employing two arrays of analog memory cells in accordance with the present invention. 
       FIG. 5  is a waveform diagram illustrating the corresponding graphical representations of the comparator in the third embodiment in accordance with the present invention. 
       FIG. 6  is an architectural diagram illustrating a digital-to-analog converter in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1  is a circuit diagram illustrating a first embodiment of an analog content addressable memory (CAM) constructed with a number (n) of CAM cells. Each CAM cell  100  comprises of two programmable analog floating gate memory cells A  120  and B  140 , a comparator C  130  and a transfer device D  150  such as a pass gate, having a Vin input  110  and a Vout output  160 . The transfer device D  150  may be implemented as a transmission gate or an analog buffer with an enable input. 
   The analog floating gate memory cell A  120  is used to store the comparison value to be compared to an input Vin  110  by the comparator C  130 . When the input voltage is sufficiently close to the value programmed on the floating gate A  120 , a match has occurred. In this instance, the transfer device D  150  is turned ON and the content stored on the analog floating gate B  140  appears on the output of the device at Vout  160 . The transfer device D  140  is designed such that if it is not enabled, the transfer device D  140  remains in a high impedance state. 
     FIG. 2  is a block diagram illustrating an n-deep CAM architecture  200  with expanded cell structures in the first embodiment. The n-deep CAM architecture  200  comprises any number of CAM cells(n)  220 ,  230 , and  240  that are connected together in the following manner: all Vin inputs  211 ,  212 , and  213  are connected in parallel to Vin  210 , and all Vout Outputs  251 ,  252 , and  253  are connected in parallel to Vout  250 . When a voltage is applied to the global Vin  210 , the resulting data at the cell containing the value equal to Vin is generated to the output on the global Vout output  250 . 
   When a voltage is applied to the global Vin  210 , all comparators  222 ,  232 , and  242  which have a stored input less than Vin  210  will output a high, logic “1”, level. The CAM cells  220 ,  230 , and  240  which have a stored value greater than Vin  210  will have a comparator output at logic “0”. For a transmission device  224 , such as a pass gate, to be selected, the input to the non-inverting input  226  of the AND gate  225  must be a logic “1” and the inverting input  227  must be at logic “0”. Similarly, for a transmission device  234  to be selected, the input to the non-inverting input  236  of the AND gate  235  must be a logic “1” and the inverting input  237  must be at logic “0”. Thus the CAM cell with stored value which is closest to Vin  210  will have the output transmission device enabled and its stored value in cell B  230  will appear at Vout  250 . The stored voltages in cells A  220  are typically monotonically increasing. 
     FIG. 3  is an architectural diagram illustrating a second embodiment of an analog content addressable memory  300  employing two arrays of analog memory cells. The analog CAM  300  comprises of two arrays A  330  and B  360  of analog memory cells. The output of a counter D  320  selects a memory cell in the array A  330 . The analog voltage VA  335  stored in the selected cell is compared with the input voltage Vin  310  at a comparator C  340 . If the voltages are equal, the counter value is latched in latch L  350 ; if Vin  310  is less than the VA 335 , the counter D  320  is incremented and if Vin  310  is greater than VA  335 , the counter is decremented. The latch output selects a memory cell in array B. The output of array B is buffered and connected to Vout  380 . 
   One of ordinary skill in the art should recognize that various modifications and variations are within the spirits in the present invention. For instance, the counter D  320  continually scans the memory array A  330 . When a comparison with Vin occurs, the address for array is B latched and the corresponding output voltage Vout is obtained. 
     FIG. 4  is an architectural diagram illustrating a third embodiment of an analog content addressable memory  400  employing two arrays of analog memory cells. The analog CAM  400  comprises of two arrays of analog memory cells in array A  440  and array B  482 . The comparator in this implementation, however, is a comparator  460  that asserts its output when the input voltage Vin  451  is greater than the output, VA  450 , of array A  440 . 
   The counter D  420  is clocked continuously such that its output constantly cycles from minimum count to maximum count or from maximum count to minimum count. The output of an address decoder  430  therefore scans the contents of array A  440  and repeats. Each successive memory location in array A  440  holds analog voltages that increase monotonically. 
   The output, VA  450 , of array A  440  is compared with the input voltage, Vin  451 , and the output of the comparator changes state when Vin  451  equals VA  450 , thereby latching the address at which a compare occurred into latch L  480 . The latched address is output as a digital value  492  and also connected to the address input of array B  482  through an address decoder  481 . The selected memory cell in array B  482  outputs its stored voltage to the Vout pin  493 , possibly through a voltage buffer. 
   The function of the device described in  FIG. 4  is to provide a completely programmable voltage transfer function between Vin  451  and Vout  493 . Each analog memory array is independently programmable such that any output voltage (within the dynamic range of the device) can be output for each corresponding input voltage. In other words, the voltages stored in each location of both memory arrays are independently programmable, thus creating a programmable voltage transfer function between input, Vin, and output, Vout. This feature of programming the voltages stored in each location of both memory arrays independently provides the options to program the memory arrays by a manufacturer or an end user. The flexibility to program in-situ or at end of the field programming is beneficial, or even necessary, in technologies such as optical transmission equipment. In an optical transmission system, each laser diode possesses specific characteristics on a unit-by-unit basis that may require programming the memory arrays after final assembly of a finished unit. Therefore, the appropriate time to program the memory arrays is when transducers and laser diodes are connected to a chip. 
     FIG. 5  is a waveform diagram  500  illustrating the corresponding graphical representations of the comparator  460  in the third embodiment. The waveform diagram  500  corresponds to a value of Vin  451  which lies within the range of voltages stored in the input array A  440 . Should Vin  451  be outside the range of stored voltages then the output of comparator C  460  would be a DC level, either high or low depending on whether Vin  451  is below or above the range. The logic block  470  examines the carry output  421  of the counter  420  and the output of the comparator C  460  and asserts either the “over” output  490  or “under” output  491  if the voltage on Vin  451  is out of range. 
   The first, second and third embodiments have several advantages relative to each other. For instance, the first embodiment compares output voltages from analog storage cells  221 ,  231  and  241  in parallel, whereas the second and third embodiments compare the contents of array A  330  and  440  in series. Thus, for a given set of process electrical parameters and sub-circuit characteristics, the first embodiment has a faster response to changing input signals Vin  210  compared to the second and third embodiments. However the die surface area and power consumption of the first embodiment would be greater than embodiments two and three. It is possible to combine some of the characteristics of all three embodiments to create a hybrid approach. For example, instead of using a single comparator C  340  or  360  in the second and third embodiments respectively, multiple comparators can be used while still retaining the general architecture of counters, address decoders and dual analog storage arrays. In this case, the multiple comparators are implemented according to the first embodiment and compare adjacent locations of array A  330  or  440  with Vin  310  or  451 . The multiple-bit digital word output from the comparators is used in combination with the output of counter D  320  or  420  to input a digital value into latch L  350  or  480 . This hybrid approach improves the response time to a changing input signal Vin  310  or  451  but does not necessarily increase die area or power consumption to the same extent as the first embodiment. 
   The second and third embodiments, as shown in  FIGS. 3 and 4  respectively, have digital outputs Dig Out  370  and  492 . It is evident to one of ordinary skill in the art that digital outputs  370  and  492  provide a digital representation of the input signal Vin  310  or  451 . Various types of analog-to-digital conversion in an analog to digital converter (ADC)  305  or ADC  405  can be performed, depending on the programmed contents of analog memory array A  330  or  430 . For example, if the voltages stored in consecutive address locations of array A  330  or  430  are of equally spaced increments, then the analog-to-digital conversion performed between Vin  310  or  451  and Dig Out  370  or  492  is a linear conversion, similar to standard ADCs, as are well known in the art. Alternatively, the stored contents of memory array A  330  or  430  can have a non-linear relationship with the digital address. For example, the stored analog voltages may be programmed to μ-law levels or other non-linear functions. Thus the invention described in the exemplary second and third embodiments can also be used to implement A-to-D converters with a programmable relationship between the analog input and digital output. 
     FIG. 6  shows an implementation of a digital-to-analog converter (DAC)  600  using an array of analog memory cells  640 . A digital input signal Dig In  610  is connected to the input of Address Decoder  630 . The output of  630  selects a location in array  640  and the stored analog voltage at the corresponding location is output at Vout  690 . Similar to the ADCs described in the previous paragraph, the DAC may perform linear or non-linear conversions depending on the actual values stored in the memory locations of array  640 . For example, if the voltage differences between consecutive address locations are equally spaced then the digital to analog conversion is linear and if the voltage differences are non-linear then various non-linear functions (such as a μ-law) can be implemented. The DAC structure  600  exists twice in  FIG. 3  and twice in  FIG. 4 . In  FIG. 3 , the array A  330  receives its input from the counter D  320 . If the counter input is replaced with a separate digital input, such as from separate input pins to the device, then the output VA  335  from the array A  330  can represent the analog conversion of the digital input. Similarly if the input to the array B  360  is connected to a separate digital input instead of to the Dig Out  370  signal from latch L  350 , then output Vout  380  can represent the analog conversion of that separate digital input. In a similar fashion, in  FIG. 4 , the array A  440  and/or array B  482  can be used to implement digital-to-analog converters. 
   The above embodiments are only illustrative of the principles of this invention and are not intended to limit the invention to the particular embodiments described. For example, an array of analog memory cells comprises any types of non-volatile memories, such as floating gate cells (e.g. EEPROM or Flash) or cells which store voltages in trap sites (e.g. MNOS or MONOS). Furthermore, the analog CAM may be implemented by using voltages that are stored without the use of non-volatile memory cells such as impedance dividers implemented with resistors or capacitors. It is apparent of one of ordinary skill in the art that the counter  420  can count up or count down which will wrap around once the counter  420  reaches the end of the count. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the appended claims.