Abstract:
A voltage to frequency converter including a first selector for receiving an input voltage and for generating an input current based on the control signal. The input current is proportional to the input voltage or an inverse polarity input voltage when the control signal designates plus, or minus integration period, respectively. The converter further includes a second selector for generating a reference current such that the reference current is on/off controlled based on the selection signal and a polarity of the reference current is determined by the control signal, and an integrator for integrating a resultant current of the input current and the reference current to obtain an integrated voltage. The integrator integrates the resultant current complementarily in a forward or in a reverse direction. The converter also includes a comparator for comparing the integrated voltage and a reference voltage to generate a comparison output signal, a selection signal generator for generating the selection signal based on the comparison output signal and the control signal, a control signal generator for generating the control signal based on the selection signal, and an output circuit for generating the selection signal as an output signal of the converter having a frequency corresponding to the input voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a voltage to frequency converter, and more particularly to a voltage to frequency converter wherein an input voltage that is used in an electronic watt hour meter or the like is converted to a frequency corresponding to the input voltage. 
     2. Description of the Related Art 
     FIG. 7 shows a prior art example of a voltage to frequency converter that converts an input voltage to a frequency corresponding to the input voltage. FIG. 8 shows the waveforms of the various units of FIG. 7. In FIG. 7, there is provided a selector 8 that obtains a resultant current I3 of a reference current I2 and an input current I1 corresponding to an input voltage E. There is further provided an integrator 1 that obtains an integrated voltage A by integrating resultant current I3 of this selector 8. Next, there is provided a comparator 2 that compares integrated voltage A and a reference voltage AG and outputs low level when this integrated voltage A is higher than reference voltage AG and outputs high level when it is lower. There is further provided a selection signal generator 3 that has a JK flipflop which outputs a selection signal K when a pulse signal CLK changes from low level to high level. This selection signal K controls a switch SW that allows the passage of reference current I2 of selector 8 described above. There is also provided a pulse signal generator 5 for generating pulse signal CLK described above. 
     In such a circuit layout, when output signal K of JK flipflop 31 of selection signal generator 3 is high level at a time t0, switch SW is closed, and resultant current I3 flowing into capacitor C1 of integrator 1 becomes: 
     
         I3=I1-I2 (&lt;0), I2&lt;I2 
    
     and integrator 1 commences integration in the plus direction. When output voltage A of integrator 1 becomes higher than reference potential AG at a time t1, output signal J of comparator 2 becomes low level. When output signal J of comparator 2 becomes low level, the inputs of JK flipflop 31 become: 
     J: low level 
     k: high level (=Q output) 
     with the result that output signal K of JK flipflop 31 becomes low level at the rising edge of pulse signal CLK at a time t2 as shown in FIG. 8. 
     When output signal K of JK flipflop 31 is low level, switch SW is opened, and resultant current I3 flowing into capacitor C1 becomes: 
     
         I3=I1 (&gt;0) 
    
     and integrator 1 commences integration in the minus direction. When output voltage A of integrator 1 becomes lower than reference voltage AG at a time t3, output signal J of comparator 2 becomes high level. The inputs of JK flipflop 31 becomes: 
     J: high level 
     K: low level (=Q output) 
     and output signal K of JK flipflop 31 becomes high level at the rising edge of pulse signal CLK at a time t4 as shown in FIG. 8. When output signal K of JK flipflop 31 is high level, switch SW closes, and returns to the initial condition. 
     Thus when switch SW1 is closed, a quantity of electric charge Q1 stored in capacitor C1 of integrator 1 is: 
     
         Q1=(I2-I1)×T1 
    
     In contrast, when switch SW is open, a quantity of electric charge Q2 discharged from capacitor C1 of integrator 1 is: 
     
         Q2=I1×T2 
    
     Here, T1 is a time period when output signal K is high level and T2 is a time period when output signal K is low level, as shown in FIG. 8. 
     Thus, since the quantity of electric charge Q1 stored and the quantity of electric charge Q2 discharged are equal, we have: 
     
         (I2-I1)×T1=I1×T2 
    
     
         I1×(T1+T2)=I2×T1 
    
     
         1/(T1+T2)=I1/(I2×T1) 
    
     T1 is given by T1=1/fCLK from a frequency fCLK of pulse signal CLK of pulse signal generator 5, and so is constant. 
     If the input offset voltage of an operational amplifier OP1 of integrator 1 is zero, a minus input potential of operational amplifier OP1 is reference potential AG which is usually zero volts. From a minus reference potential VSS and a resistor R2, reference current I2 is fixed at I2=VSS/R2. From a resistor R1 and input voltage E of the voltage to frequency converter, input current I1 is obtained as I1=E/R1. As a result, an output frequency f of the voltage to frequency converter obtained at an output terminal Tout on substitution in the foregoing expression, is as follows: ##EQU1## 
     Thus, output frequency f has a value proportional to input voltage E. 
     Although, in the above explanation, it is assumed that the input offset voltage of operational amplifier OP1 is zero, usually the input offset voltage has a value V. In this case, minus input potential of operational amplifier OP1 is V. An output frequency fE of the voltage to frequency converter in this case is then obtained by the following expression: ##EQU2## 
     In this case, the linearity of input voltage E and output frequency fE of the voltage to frequency converter is poor. The relation between an linear error ERR and input voltage E when operational amplifier OP1 has an input offset voltage V is given by the following expression, and has the characteristic shown in FIG. 9. 
     
         ERR=(fE-f)×100/f [%] 
    
     SUMMARY OF THE INVENTION 
     Accordingly, one object of this invention is to provide a voltage to frequency converter for converting an input voltage to a frequency corresponding to the input voltage, wherein the linearity error is extremely small even if the operational amplifier of the integrator has an input offset voltage. 
     These and other objects of this invention is achieved by providing a voltage to frequency converter including a fist selector for receiving an input voltage and a control signal determining a plus integration period and a minus integration period and for generating an input current based on the control signal such that the input current is proportional to the input voltage when the control signal designates the plus integration period and the input current is proportional to an inverse polarity input voltage whose polarity is an inverse of that of the input voltage when the control signal designates the minus integration period. The voltage to frequency converter further includes a second selector connected to receive the control signal and a selection signal for generating a reference current such that the reference current is on/off controlled based on the selection signal and a polarity of the reference current is determined by the control signal, and an integrator for integrating a resultant current of the input current and the reference current to obtain an integrated voltage. The integrator integrates the resultant current complementarily in a forward direction and in a reverse direction in accordance with a polarity of the selection signal during one of the plus integration period and the minus integration period, respectively. The voltage to frequency converter also includes a comparator for comparing the integrated voltage and a reference voltage to generate a comparison output signal, a selection signal generator for generating the selection signal based on the comparison output signal and the control signal, a control signal generator connected to receive the selection signal for generating the control signal determining the plus integration period and the minus integration period based on the selection signal, and an output circuit for generating the selection signal as an output signal of the voltage to frequency converter having a frequency corresponding to the input voltage. 
     The charge of a resultant current produced by an input voltage and a minus reference voltage is discharged by an input current caused by the input voltage (plus integration period); the charge of a resultant current produced by an inverse polarity input voltage and a plus reference voltage is discharged, by an input current caused by the inverse-polarity input voltage (minus integration period). This plus integration period and minus integration period are repeated a prescribed number of times, in complementary fashion. Since the times required for these charging and discharging processes are directly proportional respective to the input voltage and the inverse-polarity input voltage, the output period of selection signal K obtained by repetition of this operation is directly proportional to the input voltage. By adoption of such means, both the input voltage and the inverse-polarity input voltage can be converted to corresponding frequencies so, even when the operational amplifier of the integrator has an input offset voltage, the linearity error can be made extremely small. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram showing a voltage to frequency converter according to an embodiment of this invention; 
     FIG. 2 is a time chart of the waveforms of the various parts of the embodiment shown in FIG. 1; 
     FIG. 3 is a circuit diagram showing a voltage to frequency converter according to another embodiment of this invention; 
     FIG. 4 is a time chart of the waveforms of the various parts of the embodiment shown in FIG. 3; 
     FIG. 5 is a circuit diagram showing a voltage to frequency converter according to a further embodiment of this invention; 
     FIG. 6 is a time chart of the waveforms of the various parts of the embodiment shown in FIG. 
     FIG. 7 is a circuit diagram showing one example of a conventional voltage to frequency converter; 
     FIG. 8 is a time chart of the waveforms of the various parts of the device shown in FIG. 7; 
     FIG. 9 is a graph showing characteristic plot of linearity error in the device shown in FIG. 7; 
     FIG. 10 is a circuit diagram showing a voltage to frequency converter according to another embodiment of this invention; and 
     FIG. 11 is a circuit diagram showing a voltage to frequency converter according to still another embodiment of this invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, the embodiments of this invention will be described below. 
     FIG. 1 is a circuit diagram showing a voltage to frequency converter according to an embodiment of this invention. In FIG. 1, Tin is a voltage input terminal at which input voltage E to be converted into frequency is applied. 
     Integrator 1 outputs integrated voltage A obtained by integrating the current that is supplied from selector 8A and is constituted of operational amplifier OP1 and capacitor C1. Comparator 2 compares output voltage A of integrator 1 with reference voltage AG and outputs signal B which is of low level when output voltage A of integrator 1 is higher than reference potential AG and is of high level when it is lower than reference potential AG. 
     A selection signal generator 3A is constituted of an XOR gate 32 and JK flipflop 31. XOR gate 32 functions as a non-coincidence detector that detects and outputs non-coincidence of output signal B of comparator 2 with a control signal Sa from a control signal generator 4, to be described. JK flipflop 31 is a JK flipflop whose input signals are respectively: output signal J of non-coincidence detector 32, at an input terminal J; pulse signal CLK from pulse signal generator 5 at an input terminal CK; and output signal K of an output terminal Q at an input terminal K. JK flipflop 31 outputs selection signal K when pulse signal CLK has changed from low level to high level. 
     Control signal generator 4 is a circuit that inputs output signal K of JK flipflop 31 of selection signal generator 3A, and generates control signals Sa, Sb and Sc. Control signal generator 4 is constituted of: an inverter 41 for inverting output signal K of selection signal generator 3A; a D flipflop 42 that inputs at an input terminal CK an output signal of inverter 41 and whose output terminal QN is connected to an input terminal D; and a D flipflop 43, whose input signals are respectively an output signal Sb of D flipflop 42 at an input terminal D and output signal K of selection signal generator 3A at an input terminal CK. Control signals Sa, Sb and Sc are generated at an output terminal QN of D flipflop 43, at an output terminal Q of D flipflop 42, and at an output terminal Q of D flipflop 43, respectively. 
     7 is an inverting amplifier that generates an inverse-polarity input voltage EN obtained by inverting the polarity of input voltage E that is input from voltage input terminal Tin. Inverting amplifier 7 is constituted by an operational amplifier OP3 and resistors R3 and R4. 
     Unlike selector 8 in FIG. 7, selector 8A generates input current I1 by obtaining as input, changed over in a complementary fashion, input voltage E at voltage input terminal Tin and inverse-polarity input voltage EN, which is the output of the inverting amplifier 7, under the control of control signal Sc from control signal generator 4. Selector 8A also generates reference current I2 by connecting either a plus reference voltage VDD or minus reference voltage VSS, as specified by selection signal K from selection signal generator 3A and control signal Sb from control signal generator 4. Selector 8A also supplies resultant current I3 of input current I1 and reference current I2 to integrator 1. 
     Selector 8A is constituted of: an inverter 83 whose input signal is control signal Sb; an AND gate 81 whose input signals are control signals Sb and selection signal K; an AND gate 82 whose input signals are the output signal of inverter 83 and selection signal K; a switch SW1 that is closed or open when the output signal of AND gate 81 is high level or low level; a switch SW2 that is closed or open when the output signal of AND gate 82 is high level or low level; an inverter 84 whose input signal is control signal Sc; a switch SW3 that is closed or open when control signals Sc is high level or low level; a switch SW4 that is closed or open when the output signal of inverter 84 is high level or low level; and resistors R1, R2. Pulse signal generator 5 generates pulse signal CLK with a prescribed period, and is constituted by a crystal oscillator or the like. 
     Next, the operation of the voltage to frequency converter with the circuitry constituted as shown in FIG.1 will be described with reference to the time chart of the waveforms of the various units shown in FIG. 2. Here, the interval for which control signals Sc of control signal generator 4 is high level will be called &#34;a plus integration period&#34;, while the interval for which control signals Sc is low level will be called &#34;a minus integration period&#34;. 
     In the plus integration period, control signals Sc is high level, so switch SW3 of selector 8A is closed, and input voltage E is applied to resistor R1. Furthermore, when output signal K of JK flipflop 31 of selection signal generator 3A is high level, control signal Sb which is the output of D flipflop 42 is high level, so switch SW1 is closed by the output of AND gate 81 in selector 8A. Consequently, minus reference voltage VSS is connected to resistor R2. 
     As a result, current I3 flowing into capacitor C1 of integrator 1 is: 
     
         I3=I1-I2 (&lt;0), I1&lt;I2 
    
     and integrator 1 commences integration in the plus direction after a time t5. 
     When output voltage A of integrator 1 is higher than reference potential AG, output signal B of comparator 2 is low level. When output signal B of comparator 2 is low level, control signal Sa becomes low level, so output signal J of non-coincidence detector 32 becomes low level. As output signal K keeps high level, the inputs of JK flipflop 31 become: 
     J: low level 
     K: high level (=Q output) 
     Thus output signal K of JK flipflop 31 becomes low level at the rising edge of pulse signal CLK at a time t6. When output signal K of JK flipflop 31 becomes low level, switch SW1 is opened. As switch SW2 keeps the open state current I3 flowing into capacitor C1 of integrator 1 becomes: 
     
         I3=I1 (&gt;0) 
    
     so integrator 1 commences integration in the minus direction after time t6. 
     In the plus integration period, 
     
         I1=E/R1 
    
     
         I2=VSS/R2 
    
     Consequently, an output frequency fp of the voltage to frequency converter obtained at output terminal Tout in the plus integration period is given by the following expression: 
     
         fp=1/(T1+T2)=(E×R2×fCLK)/(VSS×R1) 
    
     Here T1 is a time period when output signal K is high level and T2 is a time period when output signal K is low level, as shown in FIG. 2. 
     When output voltage A of integrator 1 becomes lower than reference potential AG at a time t7, output signal B of comparator 2 becomes high level. When output signal B of comparator 2 becomes high level, as control signal Sa is low level, so output signal J of non-coincidence detector 32 becomes high level. As output signal K keeps low level, the inputs of JK flipflop 31 become: 
     J: high level 
     K: low level (=Q output) 
     Thus output signal K of JK flipflop 31 becomes high level at the leading edge of pulse signal CLK at a time t8. At this point, control signal Sc changes from high level to low level, thereby shifting to the minus integration period. 
     In the minus integration period, control signal Sc is low level, so switch SW4 is closed, and inverse-polarity input voltage EN obtained by inverting the polarity of input voltage E in inverting amplifier 7 is applied to resistor R1. When output signal K of JK flipflop 31 is high level, control signal Sb is low level, so switch SW2 is closed by the output of AND gate 82 in selector 8A. Consequently, plus reference potential VDD is connected to resistor R2. As a result, current I3 that flows into capacitor C1 of integration 1 is: 
     
         I3=I1-I2 (&gt;0) I1&gt;I2 
    
     so integrator 1 commences another integration in the minus direction after time t8. When output voltage A of integrator 1 is lower than reference potential AG, output signal B of comparator 2 is high level. When output signal B of comparator 2 is high level, control signal Sa becomes high level, so output signal J of non-coincidence detector 32 becomes low level. As output signal K keeps high level, the inputs of JK flipflop 31 becomes: 
     J: Low level 
     K: high level (=Q output) 
     Thus output signal K of JK flipflop 31 becomes low level at the leading edge of pulse signal CLK at a time t9. When output signal K of JK flipflop 31 becomes low level, switch SW2 is opened. As switch SW1 keeps the open state, current I3 flowing into capacitor C1 of integrator 1 becomes: 
     
         I3=I1 (&gt;0) 
    
     so integrator 1 commences integration in the plus direction after time t9. 
     In the minus integration period, 
     
         I1=EN/R1=-E/R1 
    
     
         I2=VDD/R2=-VSS/R2 
    
     Here, the absolute values of negative reference potential VSS and positive reference potential VDD are usually set to be equal to each other. 
     Consequently, an output frequency fm of the voltage to frequency converter obtained at output terminal Tout in the minus integration period is given by the following expression: 
     
         fm=1/(T1+T2)=(-E×R2×fCLK)/(-VSS×R1) 
    
     when output voltage A of integrator 1 gets higher than reference potential AG at a time t10, output,signal B of comparator 2 becomes low level. When output signal B of comparator 2 becomes low level, as control signal Sa is high level, so the output signal J of non-coincidence detector 32 becomes high level. As output signal K keeps low level the inputs of JK flipflop 31 become: 
     J: high level 
     K: low level (=Q output) 
     Thus output signal K of JK flipflop 31 becomes high level at the leading edge of pulse signal CLK at a time t11. At this point, control signal Sc changes from low level to high level, so there is a shift to the plus integration period. 
     The mean output frequency f of the voltage to frequency converter as obtained by complementary changeover between the plus integration period and minus integration period as described above is then given by the following expression: ##EQU3## 
     As a result, a frequency f that is directly proportional to input voltage E is obtained. 
     Now let us consider the case where operational amplifier OP1 of integrator 1 has an input offset voltage V. In this case, input potential at minus input terminal of operational amplifier OP1 is voltage V. Output frequency fE of the voltage to frequency converter in this case is then given by the following expression: ##EQU4## 
     As can be seen from this expression, by making minus reference potential VSS, and plus reference potential VDD equally, sufficiently greater than input offset voltage V of operational amplifier OP1, the effect of input offset voltage V on output frequency f of the voltage to frequency converter can be made small. 
     Thus, with this embodiment, inverse-polarity input voltage EN obtained by inverting the polarity of input voltage E can be converted to a corresponding frequency fm, similarly, so even if operational amplifier OP1 of integrator 1 has input offset voltage V, an accurate voltage to frequency converter can be obtained which has extremely small linearity error. 
     In the embodiment shown in FIG. 1 and FIG. 2, the plus integration period and minus integration period were changed over every time one pulse was output by signal K, by providing D flipflops 42 and 43 in control signal generator 4. However, this invention is not limited to this embodiment. FIG. 3 and FIG. 4 show a voltage to frequency converter according to another embodiment of this invention, in which the plus integration period and minus integration period are changed over every time two pulses are output by signal K, by providing D flipflops 42, 43 and 44 in control signal generator 4A. 
     Yet a voltage to frequency converter according to a further embodiment of this invention is shown in FIG. 5 and FIG. 6. In the circuit shown in FIG. 5, a changeover signal generator 6 generates a changeover signal CNT with a prescribed period, and is constituted by a frequency divider or the like that outputs high level signal and low level signal alternately every time pulse signal CLK is input a prescribed number of times. Changeover signal CNT is applied to D input of D flipflop 42 of a control signal generator 4B. 
     Control signal generator 4B for generating control signals Sa, Sb, Sc is constituted of: inverter 41 whose input signal is output signal K of selection signal generator 3A; D flipflop 42 whose input signals are respectively output signal CNT of changeover signal generator 6 at input terminal D and output signal of inverter 41 at input terminal CK; and D flipflop 43 whose input signals are respectively output signal Sb of D flipflop 42 at input terminal D, and output signal K of selection signal generator 3A at input terminal CK. 
     In this embodiment, the plus integrating period and minus integrating period are changed over alternately at prescribed time intervals, so the same benefit as the embodiment shown in FIG. 1 can be obtained. 
     In these three embodiments described above, if inverted polarity input voltage EN obtained by inverting the polarity of input voltage E is input, along with input voltage E to voltage to frequency converter inverting amplifier 7 is not needed. 
     In these three embodiments, control signal Sb is applied to the inputs of inverter 83 and AND gate 81 of selector 8A. But this invention is not limited to these embodiments. There can be provided other embodiments wherein control signal Sc in place of control signal Sb is applied to the inputs of inverter 83 and AND gate 81 in these embodiments. 
     In these three embodiments, inverting amplifier 7 is used to obtain inverse-polarity input voltage EN. But, there can be provided other embodiments wherein a differential difference amplifier is used in place of inverting amplifier 7. One of these embodiments corresponding to the embodiment of FIG. 1 is shown in FIG. 10. In FIG. 10, 7A is a differential difference amplifier which generates a voltage corresponding to input voltage E at a plus output terminal and a voltage corresponding to inverse-polarity input voltage EN at a minus output terminal. These voltages are applied to switches SW3 and SW4, respectively. 
     Another embodiment of this invention is shown in FIG. 11 in which a frequency calculator 9 is further provided. Frequency calculator 9 inputs selection signal K and calculates mean output frequency f as in the following expression based on selection signal K, thereby to output mean output frequency f corresponding to input voltage E as an output of voltage to frequency converter. 
     
         f=(fp+fm)/2 
    
     As described above, with this invention, even if an operating amplifier of an integrator has an offset voltage, the voltage signals are input in complementary fashion in plus and minus integration periods respectively, so the offset can be eliminated. A voltage to frequency converter of high accuracy and with very little linearity error can thereby be obtained. 
     Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.