Abstract:
A carrier recovery circuit for use in a demodulator for a 2 n  -phase PSK modulated signal which comprises a phase-locked loop including a voltage-controlled oscillator (7) and an automatic frequency control (AFC) loop for avoiding the false lock phenomenon. The AFC loop is comprised of two differentiating circuits (21, 25), two mixer circuits (22, 26), and a difference circuit (27), and forms a symmetrical structure so as to exclude undesired noise, thereby carrying out a stable AFC operation.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention relates to a carrier recovery circuit for use in a demodulator for a 2 n  -phase (n=1, 2, . . . ) phase-shift keying (PSK) modulated signal. 
     (2) Description of the Prior Art 
     In general, a carrier-recovery circuit is provided in a demodulator of a receiver for 2 n  -phase PSK modulated signals. Such a carrier recovery circuit is already known. For example, in a carrier recovery circuit, according to the IF (Intermediate Frequency) multiplying system, four-phase PSK modulated signals are multiplied by four so as to obtain non-modulated signals, and after that, the non-modulated signals are divided by four so as to recover the carrier in phase synchronization with the received PSK signals. In a carrier recovery circuit according to the demodulation system, the received PSK modulated signals are again modulated by using demodulated output signals. In a carrier recovery circuit according to the baseband processing system, the Costas loop is used. 
     In the baseband processing system, since carrier-waves are recovered directly from the received PSK modulated signals, a phase-locked loop (PLL) circuit is provided. This PLL circuit is preferably locked in the frequency of the carrier waves; however, this PLL circuit may also be locked in the false-lock frequencies: 
     
         f.sub.0 ±f.sub.c /N, f.sub.0 ±2f.sub.c /N, . . . 
    
     where f 0  is the frequency of the carrier waves, f c  is a clock frequency, and N=2 n . In particular, such a false lock phenomenon often occurs in the case of a low capacity digital communication system where the ratio of the clock frequency (f c ) to the carrier wave frequency (f 0 ) is small. 
     In order to avoid the above-mentioned false lock phenomenon, it has been known to use a highly stable voltage-controlled crystal oscillator in the PLL circuit. However, the use of such a crystal oscillator in a carrier recovery circuit is costly, and, in addition, the normal lock-in range for the carrier wave frequency is small. 
     In order to enlarge the normal lock-in range for the PSK modulated signals, it has also been known to add a highly stable crystal oscillator and a sweep circuit to the PLL circuit. In a carrier recovery circuit using a highly stable crystal oscillator and a sweep circuit, the false lock phenomenon is detected by obtaining the frequency difference between the voltage-controlled oscillator of the PLL circuit and the highly stable crystal oscillator. That is, when the frequency difference is larger than a predetermined value, the sweep circuit sweeps the control voltage of the voltage-controlled oscillator so that the PLL circuit is freed from the false lock state and again performs the lock-in operation for the carrier waves. However, even when the PLL circuit is freed from one false lock state, the PLL circuit may be again locked in another false lock state. Therefore, in order to enlarge the lock-in range for the PSK modulated signals, the design of the sweep circuit, including the sweep frequency, and the sweep amplitude must be carefully determined. 
     In order to enlarge the normal lock-in range for the PSK modulated signal frequency, it has been further known to add a simple automatic frequency control (AFC) circuit to the PLL circuit. In a carrier recovery circuit using an AFC circuit, the sine-wave signals or the cosine-wave signals obtained in the PLL circuit are differentiated and, the differentiated signals are supplied to the cosine-wave signals or sine-wave signals to obtain the frequency difference between the received PSK modulated signal and the output signal of the voltage-controlled oscillator. This frequency difference serves as a control voltage for the voltage-controlled oscillator. Therefore, even if the PLL circuit is locked in a false lock state, the PLL circuit is freed from the false lock state by AFC. Thus, enlargement of the normal lock-in range for the carrier waves is economically realized. However, in this recovery circuit, spurious signals are generated due to the asymmetry of the AFC circuit, thereby causing the normal lock-in operation to be unstable. 
     SUMMARY OF THE INVENTION 
     It is a principal object of the present invention to provide a carrier recovery circuit using an AFC circuit enabling the normal lock-in operation to be stable. 
     According to the present invention, there is provided a carrier recovery circuit for use in a demodulator for a 2 n  -phase (n=1, 2, . . . ) PSK modulated signal comprising: voltage-controlled oscillator means for generating first and second signals in phase quadrature; first and second mixing means for mixing the PSK modulated signal with the first and second signals, respectively; baseband processing means for multiplying the output signals of the first and second mixing means by a factor of 2 n  to generate third and fourth signals in phase quadrature; first and second differentiating means for differentiating the third and fourth signals; third mixing means for mixing the output signal of the first differentiating means with the fourth signal; fourth mixing means for mixing the output signal of the second differentiating means with the third signal; means for generating the difference between the output signals of the third and fourth mixing means; first control means for supplying a first control voltage indicative of the third or fourth signal to the voltage-controlled oscillator means; and second control means for supplying a second control voltage indicative of the output signal of the difference-generating means to the voltage-controlled oscillator means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below, contrasting the present invention with the prior art and referring to the accompanying drawings, wherein: 
     FIG. 1 is a block circuit diagram of a first prior art carrier recovery circuit; 
     FIG. 2 is a block circuit diagram of a second prior art carrier recovery circuit; 
     FIG. 3 is a block circuit diagram of a third prior art carrier recovery circuit; 
     FIG. 4 is a block circuit diagram of one embodiment of the carrier recovery circuit according to the present invention; 
     FIG. 5 is a graph of the relationship between frequency difference ω d  and control voltage V AFC  for the circuit of FIG. 4; 
     FIG. 6 is a circuit diagram of the voltage-controlled oscillator 7 of FIG. 4; 
     FIG. 7 is a circuit diagram of the baseband processing circuit 4 of FIG. 4; 
     FIG. 8 is a block circuit diagram of a second embodiment of the carrier recovery circuit according to the present invention; 
     FIG. 9 is a graph for determining the threshold values V 10  and V 20  of FIG. 8; 
     FIG. 10 is a detailed circuit diagram of the determination circuit 28 and the isolated-pulse generator 29 of FIG. 8; and 
     FIGS. 11A, 11B, 11C, 12A, 12B, and 12C are timing diagrams of the signals appearing in the circuit of FIG. 10. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIG. 1, which illustrates a first prior art circuit, a PLL circuit is constructed of a hybrid circuit 1, phase detectors or mixer circuits 2 and 3, a Costas loop-type baseband processing circuit 4, an amplifier 5, a low pass filter 6, a voltage-controlled oscillator 7, and a 90° phase shifter 8. A received four-phase PSK modulated input signal having frequency ω in  passes through the hybrid circuit 1 to mixer circuits 2 and 3 which generate output signals cos (ω d  ·t+θ) and sin (ω d  ·t+θ) in phase quadrature where ω d  and θ are differences in frequency and phase, respectively, between the input signal ω in  and the output signal ω 0  of the voltage-controlled oscillator 7. Baseband processing circuit 4 generates output sin 4(ω d  ·t+θ). Thus, voltage-controlled oscillator 7 is controlled by voltage sin 4(ω d  ·t+θ) so as to generate carrier waves. If the PLL circuit is locked in on the carrier waves, ω d  =0 and θ=0, that is, sin 4(ω d  ·t+θ)=0. However, when enlarging the lock-in range for the carrier waves, a false lock phenomenon often occurs. In this case, sin 4(ω.sub. d ·t+θ)=0 but ω d  ≠0. In order to avoid this false lock phenomenon, it has been proposed to use a highly stable crystal oscillator as the voltage-controlled oscillator 7. Such use, however, makes the circuit costly and the normal lock-in range small. 
     In FIG. 2, which is a second prior art circuit, elements 11 through 16 are added to the elements of FIG. 1. Reference numeral 11 designates a highly stable crystal oscillator having frequency ω r , 12 a mixer circuit, 13 a counter, 14 a determination circuit, 15 a sweep circuit, and 16 a sum circuit. The difference in frequency between voltage-controlled oscillator 7 and crystal oscillator 11 is counted by counter 13. When the frequency difference is larger than a predetermined value, determination circuit 14 intiates the operation of sweep circuit 15 so that the sweep voltage is added to the control voltage of the voltage-controlled oscillator 7, thereby sweeping the oscillating frequency thereof. As a result, the PLL circuit is freed from the false lock state and again performs the normal lock-in operation on the carrier waves. In the circuit of FIG. 2, however, even if the PLL circuit is freed from one false lock state, the circuit may also be locked in another false lock state. Therefore, in order to enlarge the normal lock-in range for the carrier waves, the sweep frequency, the sweep amplitude, and the like must be carefully designed. As a result, it is not easy to manufacture and adjust the circuit of FIG. 2. 
     In FIG. 3 which is a third prior art circuit, elements 21 through 24 are provided to form an AFC loop. Reference numeral 21 designates a differentiating circuit, 22 a mixer circuit, 23 a low pass filter, and 24 an amplifier. Differentiating circuit 21 generates the output ##EQU1## Therefore, mixer circuit 22 generates the output 
     
         -4ω.sub.d sin.sup.2 (ω.sub.d ·t+θ)=-2{ω.sub.d -cos 8(ω.sub.d ·t+θ)} 
    
     That is, a frequency difference of -2ω d  is supplied through the low pass filter 23 and the amplifier 24 to the voltage-controlled oscillator 7 to perform AFC. Thus, voltage-controlled oscillator 7 is controlled by first control voltage V PLL  due to the phase-locked loop and by second control voltage V AFC  due to the AFC loop. As a result, even if the PLL circuit becomes locked in a false lock state, the PLL circuit is freed from the false lock state by the AFC loop and is moved toward the center of the normal lock-in range for the carrier waves. 
     In the circuit of FIG. 3, however, there is a serious problem in that the AFC is unstable due to the AFC circuit being asymmetrical, with the result that control voltage V AFC  is relatively noisy in spite of the presence of low pass filter 23, which eliminates the high frequency component of a signal passing therethrough. Note that usually differentiating circuit 21 creates a large amount of noise. 
     In FIG. 4 which is one embodiment of the present invention, a symmetrical AFC circuit is provided so that a stable AFC operation is performed. That is, a differentiating circuit 25, a mixer circuit 26, and a difference circuit 27 are added to the elements of FIG. 3. 
     As explained above, mixer circuits 2 and 3 generate outputs, cos (ω d  ·t+θ) and sin (ω d  ·t+θ), in phase quadrature supplied to the baseband processing circuit 4, which, in turn, generates two outputs cos 4(ω d  ·t+θ) and sin 4(ω d  ·t+θ) also in phase quadrature. Sine-wave component sin 4(ω d  ·t+θ) is supplied to the PLL while both the cosine-wave and sine-wave components are supplied to the AFC loop. 
     Differentiating circuits 21 and 25 differentiate outputs cos 4(ω d  ·t+θ) and sin 4(ω d  ·t+θ), respectively, of the baseband processing circuit 4 and generate the following differentiating outputs: ##EQU2## 
     Mixer circuit 2 mixes the output of the differentiating circuit 21 with the second output of the baseband processing circuit 4, while mixer circuit 26 mixes the output of the differentiating circuit 25 with the first output of the baseband processing circuit 4. Therefore, the outputs of the mixer circuits 22 and 26 are as follows: 
     
         -4ω.sub.d sin.sup.2 4(ω.sub.d ·t+θ) 
    
     and 
     
         4ω.sub.d cos.sup.2 4(ω.sub.d ·t+θ) 
    
     Difference circuit 27 generates the difference between the outputs of mixer circuits 22 and 26, that is, 4ω d . The output of difference circuit 27 is supplied through low pass filter 23 and amplifier 24 to the voltage-controlled oscillator 7 as control voltage V AFC . Therefore, when frequency difference ω d  between the received PSK input signal and the output of voltage-controlled oscillator 7 locked in a false lock state is detected, voltage-controlled oscillator 7 is controlled so that the frequency difference ω d  becomes zero. Thus, an AFC loop is produced so as to avoid the false lock phenomenon. 
     In addition, output sin 4(ω d  ·t+θ) of baseband processing circuit 4 is supplied through amplifier 5 and low pass filter 6 to voltage-controlled oscillator 7 as the control voltage V PLL . If the frequency difference ω d  equals zero, control voltage V PLL  has a value corresponding to the difference in phase between the received PSK modulated input signal and the output of voltage-controlled oscillator 7 so that a PLL is produced. Accordingly, carrier waves are recovered from the output of voltage-controlled oscillator 7 in synchronization with the phase of the received input signals. 
     It should be noted that, in a PLL, if the frequency difference, ω d  is not zero, V PLL  is not zero either. Therefore, the PLL also serves as another AFC loop. 
     In FIG. 4, even when the outputs of the differentiating circuits 21 and 25 include undesired noise, such undesired noise is excluded by the difference circuit 27. In addition, the high frequency component of the output of the difference circuit 27 is excluded by the low pass filter 23. Thus, control voltage V AFC  of FIG. 4 is more stable than control voltage V AFC  of FIG. 3. 
     FIG. 5 is a graph of the relationship between the frequency difference ω d  and the control voltage V AFC  of voltage-controlled oscillator 7 of FIG. 4. As mentioned above, control voltage V AFC , given by the output of difference circuit 27, controls the voltage-controlled oscillator 7 so that the frequency difference ω d  becomes zero. 
     In FIG. 6, which is a circuit diagram of voltage-controlled oscillator 7 of FIG. 4, reference numeral 71 designates an oscillating circuit, 72 a variable-capacitance diode, 73 a capacitor, and 74 an inductance. The combination of variable-capacitance diode 72, capacitor 73, and inductance 74 determines the oscillating frequency of the oscillating circuit 71. In this case, the oscillating frequency varies in response to the voltage supplied to variable-capacitance diode 72, the voltage being determined by first control voltage V PLL  and second control voltage V AFC . First control voltage V PLL  has a polarity responsive to the positive or negative value of the phase difference θ while second control voltage V AFC  has a positive or negative polarity responsive to the frequency difference ω d . Two kinds of control voltages, V PLL  and V AFC , are superposed on the variable-capacitance diode 72 so as to lessen both the frequency difference ω d  and the phase difference θ. 
     In FIG. 7, which is a block circuit diagram of a baseband processing circuit 4 of FIG. 4, reference numerals 41, 42, 46, 47, 49, 50, 54, and 55 designate absolute value circuits, 43, 45, 48, 51, 53, and 56 designate difference circuits, and 44 and 52 designate sum circuits. It is assumed that α=ω d  ·t+θ. 
     Circuits 41, 42, and 43 are used for generating the output cos 2α. That is, absolute value circuits 41 and 42 generate outputs cos 2  α and sin 2  α, respectively, and difference circuit 43 generates output cos 2  α-sin 2  α=cos 2α. 
     Circuits 44 through 48 are used for generating output sin 2α. That is, sum circuit 44 generates output cos α+sin α, and, therefore, absolute value circuit 46 generates output (cos α+sin α) 2 . In addition, difference circuit 45 generates output cos α-sin α, and, therefore absolute value circuit 47 generates output (cos α-sin α) 2 . The difference circuit 48 generates the output 
     (cos α+sin α) 2  -(cos α-sin α) 2   
     =4 cos α sin α 
     =2 sin 2α 
     ≅sin 2α (after amplitude adjusting). 
     Similarly, circuits 49 through 51, which are the same as circuits 41 through 43, respectively, are used for generating output cos 4α, while circuits 52 through 56, which are the same as circuits 44 through 48, respectively, are used for generating output sin 4α. 
     Thus, signals cos α and sin α are changed to signals cos 4α and sin 4α by the baseband processing circuit 4 of FIG. 4. 
     In FIG. 8, which is another embodiment of the present invention, determination circuit 28 and isolated-pulse generator 29 are added to the elements of FIG. 4. Determination circuit 28 determines whether output level V of the low pass filter 23 is within a predetermined range having maximum level V 10  and minimum level V 20  as shown in FIG. 9. 
     Note that the curve in FIG. 9 is the same as the curve of FIG. 5. In FIG. 9, ω 1  and ω 2  are false lock frequencies, and V 10  and V 20  are output voltages of the low pass filter 23 when the frequency difference ω d  is ω 1  and ω 2 , respectively. Such values V 10  and V 20  are threshold values of determination circuit 28 (FIG. 8). 
     Returning to FIG. 8, determination circuit 28 compares the output V of low pass filter 23 with the high threshold value V 10  to generate digital output V 1 , and, simultaneously determination circuit 28 compares the output of the low pass filter 23 with the low threshold value V 20  to generate a digital output V 2 . 
     When isolated-pulse generator 29 detects the rising of output V 1  of the determination circuit 28, generator 29 generates a positive isolated pulse. On the other hand, when isolated-pulse generator 29 detects the falling of the output V 2  of determination circuit 28, generator 29 generates a negative isolated pulse. Such a positive or negative isolated pulse is supplied to the voltage-controlled oscillator 7 as control voltage V&#39; AFC . This means that an AFC loop is produced so as to avoid the false lock phenomenon. 
     In FIG. 10, which is a detailed circuit diagram of the determination circuit 28 and isolated-pulse generator 29 of FIG. 8, the determination circuit 28 comprises comparators 281 and 282 which compare output V of the low pass filter 23 with threshold values V 10  and V 20 , respectively. Isolated-pulse generator 29 comprises a rising-detection circuit (differentiating circuit) 291, a falling-detection circuit (differentiating circuit) 292, and an OR circuit 293. 
     The waveforms of the signals in FIG. 10 are illustrated in FIGS. 11A, 11B, and 11C and FIGS. 12A, 12B, and 12C. When the output V of the low pass filter 23 becomes higher than the threshold value V 10 , as illustrated in FIG. 11A, comparator circuit 281 pulls up the output V 1 , as illustrated in FIG. 11B, so that the isolated-pulse generator 29 generates a positive isolated pulse P 1 , as illustrated in FIG. 11C. Similarly, when the output V of the low pass filter 23 becomes lower than the threshold value V 20 , as illustrated in FIG. 12A, comparator circuit 282 pulls up the output V 2 , as illustrated in FIG. 12B, so that the isolated-pulse generator 29 generates a negative isolated pulse P 2 , as illustrated in FIG. 12C. 
     Thus, in the second embodiment, when the output of the low pass filter 23, corresponding to frequency difference ω d , exceeds false lock thresholds V 10  and V 20 , corresponding to frequency ω 1  or ω 2 , a positive or negative isolated pulse is supplied to the voltage-controlled oscillator 7, thereby reducing the time period required for separating the PLL circuit from the false lock state. Note that, in this case, freedom of the PLL circuit from the false lock state always carried out by the PLL. 
     The above-mentioned embodiments are related to four-phase modulated waves, however, the present invention can be applied in the recovery of multi-phase modulated carrier waves such as eight-phase waves, sixteen-phase waves, and the like. 
     As explained hereinbefore, according to the present invention, since stable AFC is carried out for the recovery of carrier waves, a normal lock-in operation for carrier waves is carried out at a high speed. In addition, the normal lock-in range can be enlarged.