Abstract:
A gamma correction factor is applied to a video signal without need of the normally used multiplier by forming the logarithm of the logarithm of the video signal and algebraically adding this signal to a second signal representing the logarithm of the correction factor. The anti-log of the anti-log of the resulting signal constitutes the gamma corrected signal. Analog and digital implementations of the circuitry are illustrated.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method of and a circuit arrangement for producing a gamma corrected video signal. 
     2. Description of the Prior Art 
     Display tubes for television introduce a distortion of the picture information due to a non-linear relationship between the applied signal voltage and the resulting screen brightness. This relationship may be approximated by the expression 
     
         Lo-K V.sub.s δ 
    
     where 
     Lo=Light output 
     K=constant 
     V s  =applied signal voltage 
     δ=constant, known as gamma. 
     Typically δ has a value of 2.5 whereas ideally it would be 1.0. 
     To prevent this distortion becoming apparent to the viewer the video signal is transmitted in a modified form by passing the signal through a gamma correction circuit which introduces a complementary distortion. 
     The modification carried out by a gamma corrector may be described by the expression 
     
         V.sub.s =V.sub.i.sup.1 /δ=V.sub.i.sup.G 
    
     where 
     V s  =output signal for transmission 
     V i  =input signal requiring modification 
     δ=constant, as before. 
     In practice the value of δ employed in the gamma correction circuit may not be exactly 2.5 but chosen to give the best subjectively pleasing result. 
     It is sometimes necessary, for example in television cameras, to perform the inverse operation to derive an uncorrected signal from a previously gamma corrected signal. In this specification the term gamma correction is to be understood to include both the correction of an uncorrected signal and the derivation of an uncorrected signal from a corrected signal. 
     Gamma correction is normally achieved by first converting the input signal into its logarithm, then multiplying this signal by the desired correction factor G, and finally applying the resultant signal to an exponential or anti-logarithm converter. Such an arrangement is disclosed in an article entitled &#34;Transistorised Non-Linear Function Generation&#34; by P. Kundu and S. Banerji which was published in Industrial Electronics, January 1964 at pages 35 to 41. 
     If the signals are expressed in digital form, as is increasingly common, the same approach can be followed except that logarithmic and exponential conversion may then be achieved by means of `look-up` tables stored in programmable read only memories (PROMs). Some difficulty is encountered, however, with the multiplication process which must be performed on each digital sample within the sample period, typically 75 ns. The digital signal, after conversion into its logarithm, may be 12 bits wide and the correction coefficient, G, 6 or more bits wide. The multiplication of a 12 bit number by a 6 bit number within 75 ns entails either complex circuitry to form and add partial products, or the use of integrated circuit multipliers which consume considerable power and are relatively expensive. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a method of a gamma correcting a television signal which does not require the use of a multiplier circuit, and to enable the production of a circuit arrangement for performing the method. 
     The invention provides a method of gamma correcting (as hereinbefore defined) a video signal comprising the steps of: forming a first signal representative of the logarithm of the logarithm of the video signal; forming a second signal of representative of the logarithm of the correction factor; forming a third signal representative of the algebraic sum of the first and second signals; and forming a fourth signal representative of the exponential of the exponential of the third signal, the fourth signal being the gamma corrected signal. 
     The invention further provides a circuit arrangement for gamma correcting (as hereinbefore defined) a video signal applied to an input thereof comprising means for forming a first signal representative of the logarithm of the logarithm of the input signal, means for forming a second signal representative of the logarithm of the correction factor, means for forming a third signal representative of the algebraic sum of the first and second signals, means for forming a fourth signal representative of the anti-logarithm of the exponential of the third signal, and means for feeding the fourth signal to an output of the circuit arrangement as the gamma corrected signal. 
     The circuit arrangement may be such that the first signal P is equal to log B  (-log A  V i ) where V i  is the input signal, the second signal Q is equal to log B  G where G is the correction factor, the third signal R is equal to P±Q, and the fourth signal is equal to A exp (-B exp R), where A and B are constants. 
     This method and circuit arrangement enables the multiplier of prior art arrangements to be replaced by an adder or a subtractor as appropriate. Where digital signals are employed adders and subtractors can be fabricated more cheaply than multipliers and can operate more quickly. The sampling rate agreed by the European Broadcasting Union for digital television standards is 13.5 MHz which means that the time available for processing each sample is less than 75 nSecs. 
     When the video signal V i  is in digital form the first, second and third means may comprise programmed digital memory devices which digital memory devices may comprise programmable read only memories. 
     This enables a relatively simple construction from readily available standard integrated circuits. 
     When choosing the bases for the logarithms it is convenient to make A equal to 2 n  where n is the number of bits in each sample of the input signal. B may be conveniently chosen to be equal to 10 x  where x=[log 10  (-log A  A-1/A)]. 
     It may be noted that in a gamma correction circuit which comprises a read only memory code converter is disclosed in a paper entitled &#34;Digital Processing Amplifier and Colour Encoder&#34; by Yoshizumi Eto, Kazuyuki Matsui, Shizuka Ishibashi, and Hiroyuki Terui which was published in SMPTE Journal, Volume 87, January 1978, pages 15 to 19. However the arrangement described therein will only produce a fixed gamma correction it not being possible to alter the correction factor. 
     Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 illustrates in block schematic form the principle of gamma correction according to the invention, 
     FIG. 2 shows in block schematic form a first embodiment of a circuit arrangement for gamma correcting an input video signal according to the invention, 
     FIG. 3 shows in block schematic form a second embodiment of a circuit arrangement for gamma correcting an input video signal according to the invention, and 
     FIG. 4 is a graph of the function y=[log B  (-log A  (x))]. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates the principle used in the invention for producing a modified signal which does not involve the use of multipliers and comprises an input 1 for a video signal V i  which input is connected to a log conversion unit 2 for producing a first output equal to log A  V i . The output of unit 2 is connected to a log conversion unit 3 for producing a second output signal equal to log B  (log A  V i ). The second output signal is applied to a first input of an adder 4. A correction factor G is connected via a second input 5 of the arrangement to a unit 6 which produces a third output signal equal to log B  G, the third output signal being connected to a second input of the adder 4. The adder 4 produces a fourth output signal equal to log B  (log A  V i )+log B  G which is fed to an antilog conversion unit 7 which produces a fifth output signal equal to G log A  V i . The fifth output signal is fed to an antilog conversion unit 8 which produces a sixth output signal equal to V i   G  which sixth output signal is applied to an output terminal 9 of the arrangement. 
     Since in a television signal the black level and peak white level must remain at defined amplitudes it is necessary to define the input signal V i  as being in the range of 0≦V i  ≦1. However, since the logarithm of a number having a value between 0 and 1 is always negative it is not possible to find the second logarithm [log B  (log A  V i )] since, mathematically, there is no logarithm of a negative number. 
     However, in this case, for the purpose of achieving the multiplication function the sign of the multiplicand may be ignored and the multiplicand treated as a positive number even though it is in fact negative. This applies in this case since the multiplicand is always negative and the multiplier G is always positive; consequently the product is always negative. 
     This procedure is shown functionally in FIG. 2 in which those items having the same functions as corresponding items in FIG. 1 have been given the same reference numerals. In the arrangement shown in FIG. 2 a unit 10 is added which multiplies the output of unit 2 by -1 to give an output signal equal to -log A  V i  which means in turn that the first input of the adder 4 receives a signal equal to log B  (-log A  V i ). As a result the output of the adder is equal to log B  (-log A  V i )+log B  G and the output of unit 7 is equal to -G log A  V i . This signal is then multiplied by -1 in a unit 11 to give an output G log A  V i  which is then applied to the unit 8. 
     If the input signal V i  is in analog form the log and antilog conversion units may be realised as amplifiers having logarithmic and exponential characteristics respectively, the units 10 and 11 by inverting amplifiers, and the adder 4 as a summing amplifier. 
     If the input signal V i  is in digital form then the log and antilog conversion units may be formed as programmable read only memories (PROMS) and the units 10 and 11 may be incorporated in the respective PROM since their only effect is to change the sign of the output. In practice, with a digital input signal a further simpliciation can be made as illustrated in FIG. 3. In the arrangement shown in FIG. 3 a PROM 12 replaces units 2, 3 and 10 and a PROM 13 replaces unit 7, 8 and 11. The arrangement then simplifies to three PROMS 6, 12 and 13 and an adder 4. With this arrangement the PROM 12 is programmed to give an output equal to [log B  (-log A  V i )] in response to an input signal V i , the PROM 6 is programmed to give an output equal to log B  G in response to an input signal G, and the PROM 13 is programmed to give an output A exp ]-B exp (R)] where R=P+Q P=log B  (-log A  V i ), and Q=log B  G. 
     The embodiments described may be modified to perform the inverse function, that is to convert a previously gamma corrected signal into an uncorrected signal or V s  =V i   1/G . The only modification required is to replace the adder 4 by a subtractor so that at the output of the subtractor the function log B  (-log A  V i )-log B  G is formed. Such an inverse operation may be useful within television camera circuits or in special effects generators. 
     The choise of logarithm bases A and B is arbitrary but there are certain values which ease implementation. 
     If base A is related to the resolution of the input variable, V i , the dependent variable P can be made positive for all non-zero values of V i . V i  may, for example, be a ten bit binary number representing values in the range ##EQU1## If base A is chosen as 2 10 , that is 1024, then the intermediate variable, I=[-log 1024  (V i )] varies between 0.00014095 and 1.0 as V i  varies between 1023/1024 and 1/1024. 
     The zero value, V i  =(0/1024,) is a special case, discussed hereinafter. 
     The second logarithm base, B, acts as a scaling constant and is conveniently chosen such that ##EQU2## This is achieved by making 
     
         B=10.sup.x 
    
     where x=[log 10  (-log 1024  (1023/1024))] rounded up. For the values given B=7095. 
     The general form of the fuction 
     
         y=[log.sub.B (-log.sub.A (x))] 
    
     is as shown in FIG. 4. 
     By differential calculus it can be shown that the minimum gradient if the function y=[log B  (-log A  (x))] occurs for a value of x=1/e. At this point the gradient of the function is ##EQU3## For each input code to translate to a unique output code the output code must have four times the resolution of the input code. Consequently if the input is defined by ten bits, the output should have twelve bits. If the value of [log B  G] is subtracted instead of added then inverse operation is achieved, i.e. the output signal becomes 
     
         V.sub.S =V.sub.i.sup.(1/δ) 
    
     In practice certain circumstances require special attention when the input value V i  =0 the output V s  must also be zero. This can be done by detecting the zero value of the input code either by a multiple input `NOR` gate having one input for each input bit or by using an extra output from PROM 12. When the zero input code is detected the output code, V s , can be artificially forced to zero. 
     For large values of V i  the adder may overflow. This is readily detected by sensing the `carry-out` output of the adder. In the event of overflow the output, V s , must be artificially forced to unity. Conversely, if inverse operation is being done then the state of `underflow` of the subtractor must be sensed and the output, V s , forced artificially to zero.