Abstract:
One embodiment of the present invention provides a method that maintains status information for several peripheral devices in a status register, which is located within a core logic unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor merely has to read the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the core logic. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices.

Description:
RELATED APPLICATIONS  
       [0001]    The subject matter of this application is related to the subject matter in three co-pending non-provisional applications by the same inventor as the instant application and filed on the same day as the instant application, entitled: “Processor with Internal Register for Peripheral Status,” having serial number TO BE ASSIGNED, and filing date TO BE ASSIGNED (Attorney Docket No. MEI97-138400); “Core Logic Unit with Internal Register for Peripheral Status,” having serial number TO BE ASSIGNED, and filing date TO BE ASSIGNED (Attorney Docket No. MEI97-138401; and “Method for Operating Processor with Internal Register for Peripheral Status,” having serial number TO BE ASSIGNED, and filing date TO BE ASSIGNED (Attorney Docket No. MEI97-138402). Attorney Docket No. MEI- 97 - 01386 . 00  Inventor: Dean A. Klein  
     
    
     
       BACKGROUND  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to peripheral devices in computer systems, and more particularly to a processor with an internal register for maintaining status information for peripheral devices in a computer system.  
           [0004]    2. Related Art  
           [0005]    Computer systems typically include a central processing unit that is coupled to and communicates with a plurality of peripheral devices, typically through a computer system bus. These peripheral devices can include: data storage devices, such as disk drives and tape drives; data input devices, such as a keyboard or a mouse; data output devices, such as a video display or an audio speaker; and communication devices, such as a network interface controller. A peripheral device frequently requires attention from the central processing unit in order to transfer data between the central processing unit and the peripheral device, or to otherwise command and manipulate the peripheral device. This attention is typically triggered by an interrupt, which the peripheral device sends to the central processing unit on order to “interrupt” normal processing by the central processing unit. During an interrupt, the central processing unit temporarily suspends normal processing and executes a piece of code known as an “interrupt service routine” to perform the required service for the peripheral device. Once the interrupt service routine is complete, the central processing unit resumes normal processing.  
           [0006]    Many computer systems use a shared interrupt architecture, in which a plurality of peripheral devices can activate the same interrupt signal. One commonly-used shared interrupt architecture is a daisy-chained structure, in which peripheral devices are “chained” together through one or more interrupt lines. Any peripheral device in the chain can generate an interrupt signal, and this interrupt signal is passed through the chain until it ultimately reaches the central processing unit. In another commonly-used shared interrupt architecture, peripheral devices share a common interrupt bus line; peripheral devices can signal an interrupt to the processor by asserting this interrupt bus line.  
           [0007]    A shared interrupt architecture has certain advantages. It is very simple; typically requiring only a small number of signal lines to carry interrupt signals. It is also expandable, typically allowing additional peripheral devices to be integrated into a computer system without requiring additional lines for interrupt signals.  
           [0008]    However, a shared interrupt architecture suffers from a major disadvantage. It requires the central processing unit to determine which peripheral device requires processing. This is because all of the peripheral devices generate the same interrupt signal, and the central processing unit cannot tell from the interrupt signal which peripheral devices require servicing. Hence, the central processing unit must typically “poll” the peripheral devices in order to determine which peripheral devices require servicing.  
           [0009]    This polling process can be quite time-consuming. The central processing unit may have to poll every peripheral device in the computer system, even though only one peripheral device typically requires servicing at any given time. Polling reduces CPU efficiency, because the CPU must perform multiple bus transactions to poll the peripheral devices, and each bus transaction can require a large number of CPU cycles in a high performance computing system. Polling also ties up the peripheral bus with a large number of polling accesses. Furthermore, polling increases the time required for servicing an interrupt. This may create problems for peripheral devices that require servicing in a timely manner. For example, a network interface controller may require immediate servicing to prevent a buffer of incoming data from overflowing. This immediate servicing may be delayed by polling.  
           [0010]    What is needed is a system for retrieving status information from peripheral devices in a shared interrupt architecture that reduces the amount of time and bus activity required to determine the status of the peripheral devices.  
         SUMMARY  
         [0011]    One embodiment of the present invention provides method for maintaining status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes. In order to update the status register, a peripheral device performs a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor merely has to read the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the CPU. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention can be characterized as a method for managing status information for a plurality of peripheral devices in a computer system. This method includes receiving status information from a peripheral device through a communication channel. In response to this status information, the method updates a status register coupled to a central processing unit. The method also includes receiving an interrupt from the peripheral device at the central processing unit. In response to the interrupt, the method tests the status register to determine which peripheral devices require servicing, and services any peripheral devices that require servicing.  
           [0012]    In one embodiment of the present invention, the method includes communicating, from the peripheral device, status information through the communication channel to the status register, and sending, from the peripheral device, an interrupt to the central processing unit.  
           [0013]    In another embodiment of the present invention, the status information is communicated to the status register by accessing a particular address in a set of reserved addresses, wherein an access to the particular address indicates a specific status for a specific peripheral device.  
           [0014]    In another embodiment of the present invention, receiving the status information includes receiving status information through a computer system bus.  
           [0015]    In a variation on this embodiment, receiving the status information includes receiving status information from a peripheral device through a bus that also carries signals for maintaining coherency between multiple caches in the computer system. In a further variation on this embodiment, receiving the status information includes receiving status information through a processor-to-memory bus.  
           [0016]    In another embodiment of the present invention, updating the status register to indicate the status of the peripheral device includes modifying a bit in the status register. In another embodiment, updating the status register includes updating the status register in the central processing unit. In yet another embodiment, updating the status register includes updating the status register in core logic coupled to the central processing unit.  
           [0017]    In another embodiment of the present invention, receiving an interrupt from the peripheral device includes receiving an interrupt through a daisy-chained interrupt structure coupled between the peripheral devices and the central processing unit.  
           [0018]    In yet another embodiment of the present invention, testing the status register to determine which peripheral devices require servicing includes executing an instruction that examines the status register and jumps to different interrupt service routines to service different peripheral devices based upon information contained in the status register.  
           [0019]    Another embodiment of the present invention can be characterized as a method for managing status information for a plurality of peripheral devices in a computer system. This method includes receiving, at a peripheral device, status information regarding the peripheral device, and communicating the status information through a communication channel to a status register coupled to a central processing unit in the computer system. The method also includes sending, from the peripheral device, an interrupt to the central processing unit. 
       
    
    
     DESCRIPTION OF THE FIGURES  
       [0020]    [0020]FIG. 1 illustrates a prior art computer system, wherein a processor  100  reads status registers  112 ,  122  and  132  located at respective peripheral devices  110 ,  120  and  130 .  
         [0021]    [0021]FIG. 2 illustrates a computer system including a processor  100  with a core logic unit  103  with an internal status register  107  for storing the status of peripheral devices in accordance with an embodiment of the present invention.  
         [0022]    [0022]FIG. 3 illustrates a computer system including multiple processors with a single status register  107  within core logic unit  103  for storing the status of peripheral devices in accordance with an embodiment of the present invention.  
         [0023]    [0023]FIG. 4 illustrates the structure of a processing system in accordance with an embodiment of the present invention.  
         [0024]    [0024]FIG. 5 illustrates the structure of status register  107  in accordance with an embodiment of the present invention.  
         [0025]    [0025]FIG. 6 illustrates how status register updating is accomplished through memory mapping in accordance with an embodiment of the present invention.  
         [0026]    [0026]FIG. 7 illustrates some of the functional units within processor  100  in accordance with an embodiment of the present invention.  
         [0027]    [0027]FIG. 8 illustrates some of the internal structure of north bridge  408  in accordance with an embodiment of the present invention.  
         [0028]    [0028]FIG. 9 illustrates part of the internal structure of status register unit  712  in accordance with an embodiment of the present invention.  
         [0029]    [0029]FIG. 10 is a flow chart illustrating how a peripheral device updates status register  107  in accordance with an embodiment of the present invention.  
         [0030]    [0030]FIG. 11 is a flowchart illustrating how processor  100  uses information from status register  107  to trigger an appropriate interrupt service routine in accordance with an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0031]    The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.  
       Overview of a First Embodiment of Invention  
       [0032]    [0032]FIG. 1 illustrates a prior art computer system, wherein a processor  100  reads status registers  112 ,  122  and  132 , located at respective peripheral devices  110 ,  120  and  130 . Processor  100  is coupled to memory  101  and bus  105  through core logic unit  103 . Processor  100  can access peripheral devices  110 ,  120  and  130  through bus  105 . In response to an interrupt, processor  100  polls status registers  112 ,  122  and  132  in order to determine which of peripheral devices  110 ,  120  and  130  require processing. This polling requires multiple operations over bus  105 .  
         [0033]    [0033]FIG. 2 illustrates a computer system including a processor  100  with a core logic unit  103  with an internal status register  107  for storing the status of peripheral devices in accordance with an embodiment of the present invention. As in the system illustrated in FIG. 1, processor  100  is coupled to memory  101  and bus  105  through core logic unit  103 . Processor  100  can access peripheral devices  110 ,  120  and  130  through bus  105 .  
         [0034]    However, the embodiment illustrated in FIG. 2 differs in a number of respects from the system illustrated in FIG. 1. In FIG. 2, processor  100  references status register  107  during interrupts to determine the status of peripheral devices  110 ,  120  and  130 . This is a very fast operation because status register  107  is internal to core logic unit  103 . A reference to status register  107  by processor  100  requires no accesses across bus  105  to poll peripheral devices  110 ,  120  and  130 .  
         [0035]    Instead, peripheral devices  110 ,  120  and  130  are responsible for updating status information in status register  107 . This updating only needs to occur when the status of a peripheral device changes. In order to update a status register, a peripheral device, such as peripheral device  110 , writes to a reserved memory location in the address space of bus  105 . No memory actually resides in this reserved address space. Instead, logic attached to the status register intercepts references to these reserved locations, and uses these references to appropriately update status registers to reflect the indicated change in status of a peripheral device.  
         [0036]    In an alternative embodiment, processor  100  references status register  107  located within core logic unit  103 . This is not as fast as referencing a status register within processor  100 , but it does not require any special modifications to processor  100  in order to implement it.  
         [0037]    In general processor  100  may be any type of computational engine for a computer system. This includes, but is not limited to, mainframe processors, microprocessors, and micro-controllers. Bus  105  may be any type of communication channel for coupling a processor to other devices in a computer system, including peripheral devices, memory devices and other processors. This includes, but is not limited to, buses such as the PCI bus, and buses that include signals to maintain coherency between multiple caches in a shared memory multiprocessor system. Peripheral devices  110 ,  120  and  130  may be any type of peripheral devices that can coupled to a computer system. These include, but are not limited to: data storage devices, such as disk drives and tape drives; data input devices, such as a keyboard or a mouse; data output devices, such as a video display or an audio speaker; and communication devices, such as a network interface controller.  
         [0038]    [0038]FIG. 3 illustrates a computer system including multiple processors with a single status register  107  within core logic unit  103  for storing the status of peripheral devices in accordance with an embodiment of the present invention. In this embodiment, processors  100 ,  300  and  310  include caches  103 ,  303  and  313 , respectively. Caches  103 ,  303  and  313  store copies of code and data from memory  320  for use by processors  100 ,  300  and  310  respectively. Processors  100 ,  300  and  310  are coupled bus  320 , as is core logic unit  103 . Core logic unit  103  couples bus  320  to memory  101  and bus  105 . Peripheral devices  110 ,  120  and  130  are coupled to bus  105 .  
         [0039]    In this embodiment, bus  320  includes signals to maintain coherency between data stored memory  320  as well as copies of the data stored in caches  103 ,  303  and  313 . Coherence is typically maintained by invalidating an entry in a cache if a copy of the data contained in the entry is modified in another cache or in memory  320 . Processors  100 ,  300  and  310  use “snoop logic” to “snoop” or listen in to a set of signals on bus  320  to determine whether to invalidate an entry in a local processor cache.  
         [0040]    Note that referencing status register  107  within core logic unit  103  is not as fast as referencing a status register located within processor  100 . However, status register  107  does not require any special modifications to a processor in order to implement it.  
       Description of Computer System  
       [0041]    [0041]FIG. 4 illustrates the structure of a processing system in accordance with an embodiment of the present invention. In the illustrated embodiment, CPU  404  is coupled through north bridge  408  to memory  405  and to bus  430 . Memory  405  can be any type of semiconductor memory that can be used in a computer system. Bus  430  can by any type of computer system bus. In one embodiment, bus  430  includes a PCI bus. Bus  430  is coupled to graphics module  414 , which processes graphical images for output to display  416 . Bus  430  is additionally coupled to sound card  415 , which generates audio signals. Sound card  415  is coupled to speaker  417 , so that the audio signals generated by sound card  415  are outputted through speaker  417 .  
         [0042]    In the illustrated embodiment, CPU  404  is additionally coupled with south bridge  410  through north bridge  408 . North bridge  408  and south bridge  410  form part of the “core logic” for the computer system. This core logic ties together and coordinates operations of components in the computer system. South bridge  410  is coupled with disk  406 , which may include any type of non-volatile storage device. This includes, but is not limited to, magnetic, optical, magneto-optical and flash memory storage devices. South bridge  410  is also coupled with bus  432 , which can be any type of computer system bus. In one embodiment, bus  432  includes an ISA bus. Bus  432  allows CPU  404  to communicate with BIOS ROM  412  and modem  422 , which are coupled to bus  432 . Modem  422  may be any type of modem through which a computer system can communicate across a telephone line.  
         [0043]    In FIG. 4, status register  107  is located within north bridge  408 . In another embodiment, status register  107  may include a stand-alone register in the computer system, not within north bridge  408 .  
       Description of Status Register  
       [0044]    [0044]FIG. 5 illustrates the structure of status register  107  in accordance with an embodiment of the present invention. In the illustrated embodiment, status register  107  includes a plurality of bits containing status information for peripheral devices in the computer system. These bits include, status device  1   502 , status device  2   504 , status device  3   506  and status device N  508 . When a status bit is set, this indicates that the corresponding device requires servicing. In other embodiments of the present invention, status register  107  includes more than one bit of status information for each device. These bits contain additional status information for each device, beyond the mere fact that a particular device requires servicing. For example, the status information may specify the type of service the device requires.  
         [0045]    [0045]FIG. 6 illustrates how status register updating is accomplished through memory mapping in accordance with an embodiment of the present invention. In this embodiment, address space  600  is an address space for address lines on a bus, such as bus  105  from FIG. 1. Address space  600  includes a BIOS image  610  at the lower end of address space  600 . BIOS image  610  contains code to implement lower-level operating system functions. Address space  600  additionally includes physical memory  630  at the upper end of address space  600 . Physical memory  630  contains code and data used by a processor to execute programs. A section of address space  600 , between BIOS image  610  and physical memory  630 , is reserved for updating status register  107 . There is no actual memory in these address locations. However, accesses to these locations update the contents of status register  107 . For example, an accesses to address  640  sets the status bit for device  1   502  to indicate that device I requires servicing, and an access to address  642  resets bit  502  to indicate that device  1  does not require servicing. Similarly, accesses to addresses  644 ,  648  and  652  set status bits  504 ,  506  and  508 , respectively, and accesses to addresses  646 ,  650  and  654  reset the same status bits.  
       Description of Status Register Locations  
       [0046]    [0046]FIG. 7 illustrates some of the functional units within processor  100  in accordance with an embodiment of the present invention. In the illustrated embodiment, processor  100  includes integer ALU (arithmetic logic unit)  702  and floating point unit  704 , which perform computational operations. Processor  100  also includes controller  706 , which can coordinate actions of functional units within processor  100 . A number of units within processor  100  are coupled to bus  105 . These include L1 cache  708 , which stores instructions and data used by processor  100  during computational operations. In some embodiments, L1 cache  708  includes separate instruction and data caches. Snoop logic  710  is also coupled to bus  105 . Snoop logic  710  listens to signals on bus  105  that contain “snoop” information. Snoop logic  710  uses this snoop information to invalidate entries within L1 cache  708 . Processor  105  additionally includes registers  712 , which temporarily store data values for computational operations within processor  105 .  
         [0047]    [0047]FIG. 8 illustrates some of the internal structure of north bridge  408  in accordance with an embodiment of the present invention. In this embodiment, status register  107  resides within status register unit  712  within north bridge  408 . North bridge  408  additionally includes a switch  805 , which switches data between CPU  404 , memory  405  and bus  430 . In this embodiment, status register unit  712  listens to accesses on bus  430  to detect accesses to the reserved range of addresses  620 .  
       Description of One Embodiment of Status Register  
       [0048]    [0048]FIG. 9 illustrates part of the internal structure of status register unit  712  in accordance with one embodiment of the present invention. In this embodiment, address lines from bus  105  are monitored by logic within status register unit  712  to detect references to reserved addresses  620 . More particularly, high order address bits from bus  105  feed into inputs of decoder  900 . If the high order address bits  902  specify an address in the reserved addresses  620 , decoder  900  generates a register hit signal  906 , which feeds into an enable input of decoder  910 . In another embodiment, high order address bits  902  feed into a comparator circuit that performs the same address detection function. In general, any commonly known address detection circuitry can be used to detect addresses in the reserved range  620 . Low order address bits  904  feed into inputs of decoder  910 . These low order address bits are used to select various outputs of decoder  910 . These outputs either set or reset bits in status register  107 . In the illustrated embodiment, each bit of status register  107  is stored in a bistable circuit which includes two NAND gates connected circularly as shown in FIG. 9. Each NAND gate pair takes two inputs from decoder  910 . If the top input is asserted low, the bit is set, and if the bottom input is asserted low the bit is reset. For example, an access to address  640  causes the top output of decoder  910  to be asserted low, which causes to corresponding bit to be asserted to a one value. In contrast, an access to address  642  causes the next lower output of decoder  910  to be asserted low, which resets the same bit. Finally, when status read signal  912  is asserted, the attached drivers are activated to read the bits out from status register  107 . This embodiment illustrates one of many possible structures for status register  107 . In general, any other commonly known structure for a register may be used.  
       Description of Operation of Status Register  
       [0049]    [0049]FIG. 10 is a flow chart illustrating how a peripheral device updates status register  107  in accordance with an embodiment of the present invention. In this embodiment, the peripheral device starts at state  1000  and proceeds to state  1002 . In state  1002 , the peripheral device detects a change its status. This change in status may indicate that some servicing is required. For example, data may be ready to be transferred the to processor  100 . The peripheral device then proceeds to state  1004 . In state  1004 , the peripheral device performs a bus master operation on bus  105  to update the status register  107  to indicate that the device requires servicing. The peripheral device then proceeds to state  1006 . In state  1006 , the peripheral device generates an interrupt to indicate to processor  100  that a peripheral device requires servicing. The peripheral device then proceeds to state  1008 , which is an end state.  
         [0050]    [0050]FIG. 11 is a flowchart illustrating how processor  100  uses information from status register  107  to trigger an interrupt service routine in accordance with an embodiment of the present invention. Processor  100  starts in state  1   100  and proceeds to state  1102 . In state  1102 , processor  100  receives an interrupt from one of the peripheral devices coupled to bus  105 . Processor  100  then proceeds to state  1104 , in which processor  100  saves state in order to process the interrupt. Processor  100  then proceeds to state  1106 . In state  1106 , processor  100  fetches interrupt instructions from the location pointed to by an interrupt vector. Processor  100  then proceeds to state  1108 . In state  1108 , processor  100  copies status register  107  to a processor register in order to examine the contents of status register  107 . The system then proceeds to state  1110 .  
         [0051]    In state  1110 , processor  100  branches based upon the contents of status register  107  to various interrupt service routines  1112 ,  1114  and  1116 . This branching may actually require a number of instructions to test status register  107  and to perform appropriate conditional branching. If status register  107  indicates that device  1  requires processing, processor  100  branches to state  1   112 , which is the start of an interrupt service routine to service device  1 . This interrupt service routine generally includes a large number of interrupt service instructions, which are not shown. After the interrupt service routine is complete processor  100  proceeds to state  1118 , which is an end state. If status register  107  indicates that device  2  requires processing, processor  100  branches to state  1114 , which is the start of an interrupt service routine to service device  2 . After this interrupt service routine is complete, processor  100  proceeds to state  1118 , which is an end state. If status register  107  indicates that device N requires processing, processor  100  branches to state  1116 , which is the start of an interrupt service routine to service device N. After this interrupt service routine is complete processor  100  proceeds to state  11   18 , which is an end state.  
         [0052]    In one embodiment of the present invention, the process of mapping peripheral devices to particular bits of status register  107 , and the process of assigning particular interrupt service routines to particular peripheral devices are performed as initialization routines during system initialization. In one embodiment of the present invention, the code to perform these functions resides in a read only memory, which is read during system boot up.  
       Definitions  
       [0053]    Core logic—circuitry within a computer system that interfaces a processor to a memory and a peripheral bus and performs other functions.  
         [0054]    Snoop bus—a bus that carries signals to maintain consistency or coherency between multiple caches in a computer system including multiple processors.  
         [0055]    The foregoing descriptions of embodiments of the invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the invention to the forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in the art.