Abstract:
An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: pushing a first multi-bit data into a data memory; modifying the data memory to remove a condition of frequent transition in the data memory, if the condition of frequent transition is found; establishing a list of indices pointing to data transition of the data memory; and sequentially examining a respective run length of the data indexed by each entry in the list, modifying the associated data to lengthen the respective run length if the respective run length is too short, modifying the associated data to shorten the respective run length if the respective run length is too long, and outputting a second multi-bit data by taking data from the data memory.

Description:
FIELD OF TECHNOLOGY 
       [0001]    This disclosure relates to digital phase equalizer for a serial link receiver. 
       BACKGROUND 
       [0002]    Serial links are used in many applications, for example, optical communications. As depicted in  FIG. 1 , a prior art serial sink  100  comprises a transmitter  110 , a transmission medium  120 , and a receiver  130 . The transmitter  110  transmits onto a first end  121  of the transmission medium  120  a first signal S 1  using a two-level signaling scheme to represent a first serial binary data stream D 1  timed in accordance with a first clock CLK 1 . The first signal S 1  traverses along the transmission medium  120  and evolves into a second signal S 2  as it reaches at a second end  122  of the transmission medium  120 . The second signal S 2 , which is a continuous-time signal, is received by the receiver  130  at the second end  122  of the transmission medium  120 . The receiver comprises: an equalizer  132  for receiving the second signal S 2  and outputting a third signal S 3 , and a CDR (clock data recovery) apparatus  131  for generating a second clock CLK 2  by extracting a timing embedded in third signal S 3  and for using the second clock CLK  2  to sample the second signal S 3  to generate a second serial binary data stream D 2 . When the CDR apparatus  131  functions correctly, the second serial binary data stream D 2  will substantially match the first serial binary D 1 , except for a delay. The purpose of equalizer  132  is to correct a distortion of the second signal S 2  due to dispersion of the transmission medium  120 . 
         [0003]    An exemplary waveform of the first signal S 1 , the second signal S 2 , and the third signal S 3  are shown in  FIG. 2 . The first signal S 1  is a typical NRZ (non-return-to-zero) waveform that is either of a first level (1) or a second level (−1), representing either a binary “1” or a binary “0” data, respectively. Due to distortion of the transmission medium  120 , the second signal S 2  is distorted and thus quite different from the first signal; in particular, it fails to reach the full level when the first signal S 1  undergoes a consecutive sign change, as illustrated by the difference in waveform between  201  and  202 . The equalizer  132  is used to correct the distortion, so that the third signal S 3  can be more like the first signal S 1 , as illustrated by the similarity between  203  and  201 . Equalizer  132 , however, is an analog circuit that is susceptible to variation due to manufacturing process, temperature, and supply voltage of the circuit. 
         [0004]    What is disclosed is a method and apparatus of a digital equalizer for correcting a distortion due to dispersion of the transmission medium. 
       SUMMARY 
       [0005]    In an embodiment, an apparatus comprises: a serial-to-parallel over-sampler for receiving a continuous-time signal and outputting a first multi-bit data, and an equalizer for receiving the first multi-bit data and outputting a second multi-bit data, wherein the equalizer comprises a data memory for storing the multi-bit data, a transition memory for storing indices of data transition, and the following functional blocks: input interface for storing the multi-bit data into the data memory; bubble removal for modifying the data memory to remove a condition of frequent data transition if found; transition detection for detecting a data transition in the data memory and storing an index of the data transition into the transition memory; run-length detection for detecting a respective run length associated with each data transition; a run-length correction for modifying the data memory for either lengthening a short run of data or shortening a long run of data; and output interface for outputting the second multi-bit data from the data memory. 
         [0006]    In an embodiment, a method comprises: receiving a continuous-time input signal; sampling the continuous-time signal at a sampling rate higher than a data rate embedded in the continuous-time input signal to generate a first multi-bit data; pushing the first multi-bit data into a data memory; modifying the data memory to remove a condition of frequent transition in the data memory, if the condition of frequent transition is found; establishing a list of indices pointing to data transition of the data memory; and sequentially examining a respective run length of the data indexed by each entry in the list, modifying associated data to lengthen the respective run length if the respective run length is too short, modifying the associated data to shorten the respective run length if the respective run length is too long, and outputting a second multi-bit data by taking data from the data memory. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  shows a functional block diagram of a serial link. 
           [0008]      FIG. 2  shows exemplary waveforms of the serial link of  FIG. 1 . 
           [0009]      FIG. 3  shows en embodiment of a serial link receiver in accordance with the present invention. 
           [0010]      FIG. 4A  shows an embodiment of S/P over-sampler suitable for the serial link receiver of  FIG. 3 . 
           [0011]      FIG. 4B  shows an exemplary timing diagram for the S/P over-sampler shown in  FIG. 4A . 
           [0012]      FIG. 5A  shows an exemplary ideal waveform for the S/P over-sampler shown in  FIG. 4A . 
           [0013]      FIG. 5B  shows an exemplary actual waveform for the S/P over-sampler shown in  FIG. 4A . 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    The following detailed description refers to the accompanying drawings which show, by way of illustration, various embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense. 
         [0015]    The digital equalizer disclosed in the present invention is based on over-sampling a continuous-time input signal carrying a serial data stream. Over-sampling in a serial link receiver is defined as sampling the continuous-time input signal at a sampling rate higher than a data rate of the serial data stream embedded in the continuous-time signal; an over-sampling ratio is defined as the ratio between the sampling rate and the data rate of the serial data stream. For a receiver of a serial link of one Gigabit per second, for instance, an over-sampling ratio of five is used when sampling the continuous-time input signal at a rate of five Giga-samples per second. A functional block diagram of a serial link receiver  300  using an equalizer in accordance with an embodiment of the present invention is depicted in  FIG. 3 . Serial link receiver  300  comprises: a serial-to-parallel (S/P) over-sampler  310  for receiving a continuous-time input signal S and outputting a first multi-bit data B 1  in accordance with a timing of a first clock CLK 1 ; an equalizer  320  for receiving the first multi-bit data B 1  and outputting a second multi-bit data B 2  in accordance with a timing of a second clock CLK 2 ; and a CDR (clock-data recovery) unit  330  for receiving the second multi-bit data B 2  and outputting a third multi-bit data B 3  in accordance with a timing of a third clock CLK 3 . Detailed descriptions of the serial link receiver  300  are given in the following paragraphs. 
         [0016]    S/P over-sampler  310  converts the continuous-time input signal S into the first data B 1  in accordance with the timing of the first clock CLK 1 . An embodiment  400  suitable for embodying S/P over-sampler  310  of  FIG. 3  is depicted in  FIG. 4A . Embodiment  400  comprises a multi-phase sampler  410  and a synchronizer  420 . A plurality of phases of the first clock CLK 1  is used for the multi-phase sampler  410 . By way of example but not limitation, an over-sampling ratio of five is employed and twenty phases of CLK 1 , labeled as CLK 1  [ 0 ], CLK[ 1 ], CLK[ 2 ], . . . , CLK[ 19 ], are used in embodiment  410 . The multi-phase sampler  410  samples the continuous-time input signal S using twenty DFF (data flip flop)  411 ,  412 ,  413 , . . . ,  414  in accordance with CLK 1 [0], CLK 1 [1], CLK 1 [2], . . . , CLK 1 [19], respectively, resulting in twenty bits Q[0], Q[1], Q[2], . . . , Q[19], respectively. The synchronizer  420  synchronizes the timings of the twenty bits Q[0], Q[1], Q[2], . . . , Q[19] using another twenty DFF  421 ,  422 ,  423 , . . . ,  424  in accordance with one of the twenty clock phases of CLK 1 , in this example CLK 1 [0], resulting in the first multi-bit data B 1  comprising twenty bits, i.e. B 1 [0], B 1 [1], B 1 [2], . . . , B[19]. In this manner, the continuous-time input signal S is converted into a block of multi-bit data B 1 , in this example a block of twenty bits. 
         [0017]    An exemplary timing diagram of CLK 1  is shown in  FIG. 4B . A period of the first clock CLK 1  is T. The twenty phases CLK 1 [0], CLK 1 [1], CLK 1 [2], . . . , CLK 1 [19] are uniformly displaced in time, with a spacing of Δ in time between adjacent phases, where Δ=T/20. In this example of using an over-sampling ratio of five, a unit interval of the binary data stream carried in the continuous-time input signal S is five times of the spacing Δ (i.e. 5·Δ), therefore five samples are generated for every bit of the binary data stream. On the other hand, each block of the twenty-bit data B 1  covers four bits of the data stream embedded in the continuous-time input signal S. 
         [0018]    Equalizer  320  receives the first multi-bit data B 1  and outputs the second multi-bit data B 2  in accordance with a timing of a second clock CLK 2 . Equalizer  320  comprises the following functional units: input interface  321 , transition detection  322 , bubble removal  323 , run-length detection  326 , run-length correction  324 , and output interface  328 . Equalizer  320  also includes a data memory  325  for storing data, and a transition memory  327  for storing indices of data transition. The above mentioned example, wherein the first multi-bit data B 1  is a twenty-bit data resulting from a five-time over-sampling of the continuous-time input signal S, is used to explain these functions in the following paragraphs. 
         [0019]    When the equalizer  320  receives the first multi-bit data B 1 , it stores the multi-bit data B 1  into the data memory  325 , overwriting the previous values stored in the data memory. By way of example but not limitation, in one embodiment, CLK 1  is the same as CLK 2 , B 1  is a twenty-bit data and a forty-bit memory denoted as M[39:0] is used to embody the data memory  325 , and the input interface function  321  is described in an algorithm written in C-language shown below: 
         [0000]    
       
         
               
               
             
               
               
             
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 for (j=0; j&lt;20; j++) { 
               
             
          
           
               
                   
                 M[j] = M[j+20]; 
               
               
                   
                 M[j+20] = B1[j]; 
               
             
          
           
               
                   
                 } 
               
               
                   
                   
               
             
          
         
       
     
         [0020]    That is: the latest twenty bits stored in the data memory are moved to the second-to-latest twenty bits; the twenty-bit data B 1 [19:0] are stored into the latest twenty bits of the data memory. 
         [0021]    Note that the above algorithm is only meant to illustrate the function of input interface  321  and intended for ease of explanation instead of efficiency in embodiment; those of ordinary skills in the art are free to implement the function using whatever algorithm that is applicable, as long as the function is preserved. For instance, one may choose to use two pages of twenty-bit memories, and alternately store the multi-bit data B 1 [19:0] into one of the two memories without physically moving the latest twenty bits of the data memory. 
         [0022]    The binary data stream embedded in the continuous-time input signal S is either binary one (“1”) or binary zero (“0”). If there is no distortion in the continuous-time input signal S, each “1” bit will result in five consecutive “1” bits in the twenty-bit data B 1  due to using five-time over-sampling. Likewise each “0” bit will result in five consecutive “0” bits in the twenty-bit data B 1 . An exemplary ideal waveform of the continuous-time input signal S and the corresponding twenty-bit data B 1  are shown in  FIG. 5A ; there are five consecutive “1” bits B 1 [4:0], followed by ten consecutive “0” bits B 1 [14:5], followed by five consecutive “0” bits. A run of five consecutive “1” bits is said to have a run-length of five. Likewise, a run of ten consecutive “0” bits is said to have a run-length of ten. If there is no distortion in the continuous-time input signal S, the run-length of either “1” or “0” bits in the data obtained from a five-time over-sampling will always be a multiple of five, i.e. five, ten, fifteen, twenty, and so on. 
         [0023]    Due to a distortion, the run-length of the data obtained from the five-time over-sampling may not be exactly a multiple of five. Whenever a run of “1” ends, a transition occurs as the next sample will be “0,” thus ending the run of “1.” Likewise, whenever a run of “0” ends, a transition occurs as the next sample will be “1,” thus ending the run of “0.” The transition detection function  322  tests if two adjacent bits of the multi-bit data B 1  are different, and a transition is detected whenever the two adjacent bits are different. Note that for the first bit B 1 [0], the XOR operation must be applied with the last bit B 1 [19] from the previous sampling period of the first clock CLK 1 . For this reason, a previous value of the last bit B 1 [19] must be saved; that&#39;s why the size of the data memory  325  must be larger than the size of the multi-bit data B 1  so as to be able to at least partly save the old twenty-bit data B 1  from the previous sampling period (of the first clock CLK 1 ) when the new twenty-bit data B 1  from the present sampling period (of the first clock CLK 1 ) are saved into the data memory  325 . 
         [0024]    In one embodiment, transition detection function  322  comprises a plurality of hard-wired XOR gates for effectively embodying the following algorithm written in C-language: 
         [0000]    
       
         
               
               
             
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 for (j=19; j&lt;40; j++) 
               
             
          
           
               
                   
                 X[j] = M[j]{circumflex over ( )} M[j−1]; 
               
               
                   
                   
               
             
          
         
       
     
         [0025]    Here, X[j] is referred to as a transition signal; if X[j] is 1, it indicates at transition occurs from M[j 1] to M[j]. 
         [0026]    Under certain circumstances (for instance, in the presence of distortion and/or additive noise), the transition may occur too often resulting in a “bubble” within the twenty-bit data B 1 . For five-time over-sampling, a bubble is found when there exist more than two transitions within five consecutive samples. A bubble condition  501  is shown in  FIG. 5B , wherein there are two consecutive transitions resulting in M[20:39]=11111111101000011111. In this case, in an embodiment the bubble removal function  323  will remove the bubble by treating the second transition of the three consecutive transitions as invalid and change the data to M[20:39]=11111111100000011111. An algorithm written in C-language for embodying the bubble removal function  323  is shown below: 
         [0000]    
       
         
               
               
             
               
               
             
               
               
             
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 for (j=20; j&lt;38; j++) { 
               
             
          
           
               
                   
                 if (~X[j−1] &amp; X[j] &amp; X[j+1]) 
               
             
          
           
               
                   
                 M[j+1] = M[j]; 
               
             
          
           
               
                   
                 } 
               
               
                   
                   
               
             
          
         
       
     
         [0027]    An algorithm written in C-language suitable for embodying run-length detection function  326  is shown below: 
         [0000]    
       
         
               
               
             
               
               
             
               
               
             
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 Transition[0] = Transition[k] − 20; 
               
               
                   
                 k = 0; 
               
               
                   
                 for (j=20; j&lt;40; j++){ 
               
             
          
           
               
                   
                 if (X[j]==1) 
               
             
          
           
               
                   
                 k++; 
               
               
                   
                 Transition[k] = j; 
               
             
          
           
               
                   
                 } 
               
               
                   
                   
               
             
          
         
       
     
         [0028]    Here, Transition is an array for storing the indices of bits where a transition occurs; 
         [0029]    k is a variable storing a count of transitions. The last transition in last sampling period (of the first clock CLK 1 ) is carried over to the present sampling period in order to calculate the run length of the last transition. Because the last transition occurs in a previous sampling period (of the first clock CLK 1 ), the value must be decremented by 20, the number of bits in one sampling period (of the first clock CLK 1 ). When a transition is detected, k is incremented and the index of the bit where the transition occurs is stored into the Transition array. 
         [0030]    In the exemplary embodiment of five-time over-sampling, ideally every run-length of consecutive “1” or “0” must be a multiple of five. Due to dispersion of the transmission medium, a run length may deviate from a multiple of five. In particular, there are two scenarios that are common: 
         [0031]    Scenario  1 : Short Run Length 
         [0032]    A run length shorter than four needed to be made longer. 
         [0033]    If a run-length of one is detected, for instance M[39:20]=00000000001000000000, in an embodiment, M[39:20] is changed to 00000000111110000000. 
         [0034]    If a run-length of two is detected, for instance M[39:20]=00000000011000000000, in an embodiment, M[39:20] is changed to 00000000111100000000. 
         [0035]    If a run-length of three is detected, for instance M[39:20]=00000000111000000000, in an embodiment, M[39:20] is changed to 00000001111100000000. 
         [0036]    Scenario  2 : Long Run Length 
         [0037]    A long run length, for instance, longer than fifteen, needed to be made shorter. 
         [0038]    For instance, if M[39:0]=1111000000000000000000000000000000000000, in an example, M[39:0] is changed to M[39:0]=1111100000000000000000000000000000000000. 
         [0039]    An algorithm written in C-language suitable for embodying run-length correction function  324  is shown below: 
         [0000]    
       
         
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 for (n=0; n&lt;k; n++) { 
               
             
          
           
               
                   
                 Run_length = Transition[n+1] − Transition[n]; 
               
               
                   
                 if Run_Length==1 { 
               
             
          
           
               
                   
                 M[Transition[n]−1] = M[Transition[n]]; 
               
               
                   
                 M[Transition[n]−2] = M[Transition[n]]; 
               
               
                   
                 M[Transition[n+1]] = M[Transition[n+1] −1]; 
               
               
                   
                 M[Transition[n+1]+1] = M[Transition[n+1] −1];} 
               
             
          
           
               
                   
                 elseif Run_Length&lt;4 { 
               
             
          
           
               
                   
                 M[Transition[n]−1] = M[Transition[n]]; 
               
               
                   
                 M[Transition[n+1]] = M[Transition[n+1] −1]; 
               
             
          
           
               
                   
                 elseif Run_Length&gt;15 { 
               
             
          
           
               
                   
                 M[Transition[n+1]−1] = M[Transition[n+1]]; 
               
             
          
           
               
                   
                 } 
               
               
                   
                   
               
             
          
         
       
     
         [0040]    Note that the criterion of “long run length” depends on the dispersion of the transmission medium used in the serial link. The above algorithm is just an example workable for a certain transmission medium and may not work well for other transition media. In general, if the transmission medium is more dispersive, the criterion for “long run length” is looser (i.e., a shorter run length is qualified as a long run length). 
         [0041]    Output interface  328  is to provide the subsequent CDR  330  to access the data memory  325  so as to obtain the second multi-bit data B 2  (see  FIG. 3 ). In one embodiment where CLK 3  is the same as CLK 2  and B 2  is of the same dimension as B 1 , the output interface function  328  is described in an algorithm written in C-language shown below: 
         [0000]    
       
         
               
               
             
               
               
             
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 for (j=0; j&lt;20; j++){ 
               
             
          
           
               
                   
                 B2[j] = M[j]; 
               
             
          
           
               
                   
                 } 
               
               
                   
                   
               
             
          
         
       
     
         [0042]    If CLK 3  is different from CLK 2 , an elastic buffer is needed for the output interface  328 . The principle of elastic buffer is well known to those of ordinary skill in the art and thus not described in detail here. 
         [0043]    Clock-data-recovery is a function well known in prior art. CDR  330  can be embodied by any embodiment known in prior art and not described in detail here. 
         [0044]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations and variations of the embodiments discussed herein. Various embodiments use permutations and/or combinations of embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description.