Abstract:
A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 89102589, filed Feb. 16, 2000. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating an opening with small critical dimension. 
     2. Description of the Related Art 
     In the fabrication of semiconductor devices, increasing device density on a given die area provides significant advantages such as speed and power efficiency. Openings, such as vias and contacts with sizes as small as about 0.15 to 0.2 micron, are frequently formed by photolithographic patterning of the insulating layer. FIGS. 1A to  1 C illustrate the forming of a via or contact opening using photolithography technique according to the conventional practice. 
     As shown in FIG. 1A, a wafer substrate  100  with a layer of insulation material  102  is provided. A photoresist layer  104 , for example, a negative photoresist, is coated on the surface of the insulation material  102 . 
     Referring to FIG. 1B, a mask layer  106  is precisely aligned and disposed over the substrate  100 . Thereafter, the photoresist layer  104  is exposed to light or other radiation sources through the mask layer  106  and then is developed. 
     Continuing to FIG. 1C, the exposed portion of the insulation material  102  and the photoresist layer  104  are removed, forming a via or contact opening  108  in the insulation material  102 . 
     The photolithography technique can produce very fine resolution on a substrate; however, as the dimensions of a semiconductor device are gradually reduced, the control of the critical dimension in a photolithography process is hindered by the limitations of light resolution and the depth of focus (DOF). Due to the manufacturing constraints associated with the technologies capable of producing extremely high resolution, the development of dies having greater device density and smaller device features is seriously hampered. 
     Presently, deep-UV wavelengths are used for fine-resolution photolithography. Switching to a higher frequency would theoretically allow a greater density and smaller device features, but it would not be very cost effective due to the need to develop new equipments, fabrication techniques, or photoresists appropriates for the shorter wavelengths. 
     Other approaches to reduce the critical dimension of a device usually requires the employment of a more complicated mask, for example, PSM, and to conduct a special exposure technique, for example, an off-axial illumination. The purpose of reducing the critical dimension can be achieved with the above approaches, the manufacturing cost of an integrated circuit, however, is also increased significantly. Furthermore, adjacent areas of the constructive interference are often seen as a single large region, and are not resolved in some cases. 
     The E-beam exposure systems and the X-Ray systems are two other options for forming openings with a width of about 0.1 micron or less. Unfortunately, the E-beam and the X-ray systems are still in the research stage. Furthermore, using the E-beam and the X-ray systems are also not very cost effective. 
     SUMMARY OF THE INVENTION 
     Based on the foregoing, the present invention provides a fabrication method for an ultra-small opening, for example, sub-0.1 micron, using the existing and less expensive technology. 
     As embodied and broadly described herein, the present invention provides a method for producing an opening with small critical dimension, for example, sub-0.1 micron, wherein a first photoresist layer is coated on a semiconductor substrate. A mask layer with a small opening pattern is then accurately aligned with the substrate. After this, the first photoresist layer is exposed to light through the mask layer and is then developed. After removing the unpolymerized portion on the first photoresist layer, an opening is formed in the first photoresist layer. A plasma treatment process is then conducted on the surface of the remaining first photoresist layer, forming free radicals and bridging bonds on the surface of the first photoresist layer. A thin layer of a second photoresist is further conformally coated on the active surface of the first photoresist layer, resulting with an ultra-small opening. 
     Accordingly, the present invention uses well established processes to provide an opening smaller in size, for example, sub-0.1 micron. By performing this surface treatment process on the photoreist layer, an ultra-small opening can be formed without the use of a light source with a shorter wavelength. Furthermore, cheaper methods employing a light source with longer wavelengths can be used without the loss of resolution. The present invention thereby increases the performance of the products by scaling the existing technology in a controllable fashion. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIGS. 1A to  1 C are schematic, cross-sectional views showing the manufacturing of a small opening according to the prior art. 
     FIGS. 2A to  2 F are schematic, cross-sectional views showing the manufacturing of an ultra-small opening according to the preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A method of forming an ultra-small opening using the existing and less expensive techniques is described. 
     Referring to FIG. 2A, a semiconductor substrate  200  with a material layer  202  formed thereon is provided. The substrate  200  may also be one of the layers in a multilevel interconnect, and the material layer  202  is an insulation layer. The material layer  202 , for example, silicon oxide, can be deposited using standard chemical vapor deposition (CVD) method or other applicable techniques. The thickness of the material layer  202  determines the depth of the opening formed in the material layer  202  subsequently. 
     Still referring to FIG. 2A, a photosensitive film, for example, a photoresist layer (PR)  204 , is spin coated on the surface of the material layer  202 . The photoresist layer  204  can either be a positive photoresist in which the portion exposed to light is removed by development, or a negative photoresist in which the portion not exposed to light is removed. For most negative photoresists, the polymer is the polyisoprene type, and the basic positive photoresist polymer is the phenol-formaldehyde type polymer. Both types of photoresists contain unsaturated bonds in their structures. For the purpose of an illustration, a negative photoresist is formed in this preferred embodiment of the present invention. After the deposition of the photoresist layer  204 , a softbake process  206  is conducted to partially evaporate solvents in the photoresist layer  204 , which can interfere with the rest of the processing. 
     Continuing to FIG. 2B, a mask layer  208  with the desired pattern is accurately aligned and disposed over the photoresist layer  204 . An exposure process is then conducted to encode the pattern onto the photoresist layer  204 . In the case with a negative photoresist, the region of the photoresist layer  204  that is exposed to the light source, as illustrate by the crossed region of the photoresist layer  204  in the Figure, was changed from an unpolymerized condition to a polymerized one. 
     As shown in FIG. 2C, removing the unpolymerized portion of the photoresist layer  204  with chemical solvents or developers leaves an opening  214  in the photoresist layer  204  which corresponds to the opaque pattern on the mask layer  208  (as is shown in FIG.  2 B). Following the development of the pattern coded on the photoresist layer  204 , a hard bake process is conducted to additionally evaporate the solvents. 
     Referring to FIG. 2D, a surface treatment process, for example, a plasma treatment using a surface activating gas source (R), is conducted on the photoresist layer  204  to form free radicals and bridging bonds on the surface of the photoresist layer  204 . The surface activating gas source includes fluorine gas (F 2 ), chlorine gas (Cl 2 ), bromine gas (Br 2 ), hydrogen fluoride (HF) gas, hydrogen chloride (HCl) gas, hydrogen bromide (HBr) gas, oxygen (O 2 ) gas, argon (Ar) gas, carbon monoxide (CO) gas, carbon dioxide (CO 2 ) gas, nitrogen (N 2 ) gas, ammonia (NH 3 ) gas, trifluoromethane gas (CHF 3 ) or carbon tetrafluoride (CF 4 ) gas. After the plasma treatment, many free radicals (•) and bridging bonds, for example, PR—R bond, PR•, PR—R•, R•, are formed on the surface of the photoresist layer  204 . These free radicals and the bridging bonds are denoted by the reference number  216 . 
     Continuing to FIG. 2E, a layer of photoresist  218  is conformally coated on the active surface of the photoresist layer  204  and in the opening  214 . The free radicals and the bridging bonds  216  on the surface of the photoresist layer  204  is covalently reacted with the unsaturated bonds or functional group of the photoresist layer  218 . The photoresist layer  218  is preferably the same type of the photoresist as the underlying photoresist layer  204  to prevent aggregation. 
     Referring to FIG. 2F, a thermal treatment is then conducted to accelerate the free radical chain reaction between the photoresist layer  204  and the photoresist layer  218  (as shown in FIG.  2 E). For a negative photoresist, as in the preferred embodiment, the photoresist layer  218  can be developed directly without exposure. In the case with a positive photoresist, the photoresist pattern is developed after an exposure process. The portion of the conformal photoresist layer  218  not covalently bonded is removed in the development process, leaving only a thin conformal photoresist layer  218   a  on the photoreist layer  204 . An ultra-small opening  220  is therebyformed in the photoresist layer  204 . The duration of the thermal treatment determines the extent of the reaction between the photoresist layer  204  and the photoresist layer  218 , and thus also determines the thickness of the photoresist layer  218   a . As a result, the size of the ultra-small opening  220  can be controlled by the thickness of the photoresist layer  218   a.    
     Subsequently (not shown in Figure), the material layer  202  is removed by etching through the opening  220  to forma an opening, such as a via or a contact opening in the material layer  202 . The photoresist layers  204  and  218   a  are further stripped to finish the pattern formation process. 
     According to the preferred embodiment, the present invention is capable of creating very small openings or holes (e.g. sub-0.1 micron). The ultra-small opening of the present invention is formed by surface treating the photoresist layer  204  to form a double-coated photoresist layer  204 . The critical dimension of a small opening is thereby effectively reduced without the loss of resolution by using the cheaper photolithography techniques. Since the duration of the thermal treatment process determines the thickness of the thin conformal layer  218   a , the size of the opening  220  is easily controllable. This method of the present invention can thus provide an improvement in both the integration and the miniaturization of semiconductor devices to meet the industry demand in a cost-effective manner by scaling the existing technology in a controllable fashion. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.