Abstract:
A method and device for providing electrostatic discharge (ESD) protection are disclosed. The method uses the gate-controlled conductivity of field n-channel metal-oxide-semiconductor field effect transistor (field NMOSFET), wherein considerable ESD current can be conducted away when any ESD event beyond range of operation voltage, unlike PMOS ESD protection which is to be turned on at negative voltage. Instead of the traditional two-stage ESD protection (using one ESD protection between open drain output and V SS  and the other ESD protection between V DD  and V SS ), the device can be directly used between open drain output and power source V DD  for the wide range of operation voltage. Unlike the floating-gate field NMOS using punch through current for ESD protection, a controllable triggered voltage by changing the gate threshold voltage supports the device to be a robust ESD protection.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a technology for electrostatic discharge (ESD) protection in semiconductor industry, and more particular for ESD protection method and device between port with open drain output and power source V DD . 
         [0003]    2. Description of the Prior Art 
         [0004]    In a recent field of fabrication process of semiconductor industry, ESD threats always exist in semiconductor integrated circuits (IC) during wafer fabrication, wafer package, chip equipment, and event after-sale operation. The semiconductor integrated circuit devices become sensitive to damages caused by electrostatic discharges. For example, the possibility ESD threats include human body model (HBM), machine model (MM), charge-device model (CDM) and field-induced model (FIM), demonstrate the damage power of a single ESD event. Hundreds and event thousands times electrostatic voltage of normal operation will be discharged at touching moment then destroys an unprotected internal circuit. As shown in  FIG. 1A , an ESD protection therefore has to be placed between any two ports of an internal circuit  110  to prevent a discharge current passing through the internal circuit at ESD event happening. In an exemplary embodiment, an internal circuit  110  has three ports, for major power voltage V DD , for low voltage V SS  (V SS  is lower than V DD  and usually connected to ground), and for input/output (I/O). As ESD event happening, discharge current will flow from high voltage port to low voltage port through the internal circuit  110  and burn the internal circuit, if there is no ESD protection between high voltage port and low voltage port. To protect internal circuit from ESD threat is to set short circuits  120 ,  130  between ports and low voltage port V SS  (ground usually). The short circuit should not function until port voltage is beyond normal operation voltage, and conduct ESD current away as ESD event happening, 
         [0005]    Traditionally, a short circuit to conduct current only on high electrostatic voltage can use a diode or a PNP junction with its reverse bias property which will generate punch through current for ESD shunt as reverse bias larger than punch through voltage; or use a p-channel metal-oxide-semiconductor field effect transistor (PMOS)  241  to be a shunt switch turned on by negative gate-voltage whose gate connected to the power voltage V DD  (please see  FIG. 1B ). 
         [0006]    An ESD protection  140  such as diode string and floating-gate field n-channel metal-oxide-semiconductor field effect transistor (floating-gate field NMOS)  242  can use punch through current to shunt ESD current (please see  FIG. 1C ), nevertheless, the punch through voltage can not be controlled precisely. Because impurity ratio and abruptness of PN junction are varied in every producing, the punch through voltage of diode string and floating-gate field NMOS is varied too. A controllable punch through voltage is very important in order to ensure the internal circuit can be operated normally in known condition. For PMOS  241 , ESD protection can be triggered by a known trigger voltage, a negative gate-voltage. However, also because of the negative trigger voltage, the PMOS ESD protection is used only between I/O port with normal operation voltage less than power voltage V DD  and V DD . 
       SUMMARY OF THE INVENTION 
       [0007]    The invention provides, in a first aspect, a new ESD protection method and device for solving the traditional problems: the restriction of normal I/O operation voltage less power voltage V DD  and an uncontrollable punch through voltage. 
         [0008]    In a second aspect, the invention provides a new ESD protection method and device especially for pin with open drain output in semiconductor element. 
         [0009]    In order to achieve the aforementioned objects, an ESD device according to the invention includes pin with open drain output combined with a proper pull-up resistor which can be attached to different voltage elements, such as a higher I/O voltage than power voltage V DD . 
         [0010]    An ESD protection method according to the invention can shunt ESD current for internal circuit through an n channel of inversion layer below gate field oxide layer of a field n-channel metal-oxide-semiconductor field effect transistor (field NMOS). The n channel can be generated in a depletion layer by a positive ESD voltage on the gate while ESD event happening. 
         [0011]    An embodiment according to the invention is one-directional ESD protection device shunting one-directional ESD current for internal circuit by short of a field NMOS while ESD event happening. 
         [0012]    Another embodiment according to the invention is two-directional ESD protection device shunting two-directional ESD current for internal circuit by short of one of field NMOSs while ESD event happening. 
         [0013]    Other objects, advantages and novel features of this invention will be obvious with the following detailed description when taken in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1A  illustrates a prior art to show the relation between traditional ESD protection circuits and internal circuit. 
           [0015]      FIG. 1B  illustrates a prior art to show the relation between traditional PMOS ESD protection circuit and internal circuit. 
           [0016]      FIG. 1C  illustrates a prior art to show the relation between traditional floating-gate field NMOS ESD protection circuit and internal circuit. 
           [0017]      FIG. 2A  shows a schematic diagram of n channel formation below field oxide layer in a field NMOS according to the invention. 
           [0018]      FIG. 2B  is a schematic diagram to show the relation between poly-gate field NMOS ESD protection device and internal circuit according to the invention. 
           [0019]      FIG. 3A  is a schematic diagram to show the relation between one-directional ESD protection device and internal circuit according to the invention. 
           [0020]      FIG. 3B  is a schematic diagram to show the relation between two-directional ESD protection device and internal circuit according to the invention. 
           [0021]      FIG. 4A  is a top-view layout structure in one embodiment of the one-directional ESD protection device according to the invention. 
           [0022]      FIG. 4B  is a schematic diagram for the cross-section along a-a line on  FIG. 4A . 
           [0023]      FIG. 4C  is a schematic diagram for the cross-section along b-b line on  FIG. 4A . 
           [0024]      FIG. 5A  is a top-view layout structure in one embodiment of the two-directional ESD protection device according to the invention. 
           [0025]      FIG. 5B  is a schematic diagram for the cross-section along c-c line on  FIG. 5A . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0026]    An ESD protection method embodiment according to the invention as shown on  FIG. 2A  protects an internal circuit  110  against ESD effects and harms. The ESD protection method comprises the following steps: (a) accept ESD current through a first ESD port P 1  while an ESD event happens on the internal circuit; (b) discharge the ESD current from a second ESD port P 2  while an ESD event happens on the internal circuit; and, at the same time, (c) utilize voltage differential between the first ESD port P 1  and the second ESD port P 2  to induce an inversion layer in depletion layer below gate field oxide layer of a 1 st  NMOS  151  and shunt the ESD current through the inversion n channel  153  from the first ESD port P 1  to the second ESD port P 2  rapidly. 
         [0027]    An embodiment of one-directional ESD protection device according to the invention as shown on  FIG. 3A  protects an internal circuit  110  against ESD effects and harms in one direction. The one-directional ESD protection device comprises: (a) a first ESD port P 1  with voltage V 1  for ESD current acceptance while an ESD event happens on the internal circuit; (b) a second ESD port P 2  with voltage V 2  for ESD current discharge while an ESD event happens on the internal circuit; and (c) a 1 st  NMOS  310  with its gate connected to the first ESD port P 1 , its drain connected to the first ESD port P 1 , and its source connected to the second ESD port P 2 , wherein a short between its drain and source is formed to shunt ESD current without passing through the internal circuit while voltage differential between the first ESD port P 1  and the second ESD port P 2  is larger and equal than its gate threshold voltage V th  (V 1 −V 2 ≧V th ). In normal operation, voltage differential between the first ESD port P 1  and the second ESD port P 2  is smaller than gate threshold voltage V th  (V 1 −V 2 &lt;V th ) and is small enough to not form a short between drain and source on the 1 st  NMOS. Furthermore, the 1 st  NMOS is operable to be a field n-channel metal-oxide-semiconductor field effect transistor (field NMOS) with a field oxide layer below gate for increasing threshold voltage V th . By choosing the filed NMOS from different semiconductor process, the threshold voltage V th  can be adjusted to fit different operation voltage condition (V 1 −V 2 &lt;V th ). In an exemplary embodiment, a field NMOS with larger V th  can be used between I/O port with open drain output  440  and power voltage V DD  directly as ESD protection. Additionally, an operable poly-gate  410  design on gate of the 1 st  NMOS provides the better ESD protection result. 
         [0028]      FIG. 4A  is a layout structure for the one-directional ESD protection device. The cross-section structure along a-a line and b-b line on  FIG. 4A  are shown on  FIG. 4B  and  FIG. 4C . Increasing/decreasing the width (W) of poly-gate grown on field oxide layer according to the layout on  FIG. 4A  is also to increase/decrease the loading of ESD current in n channel below the poly gate for fitting different requirements of ESD protection. 
         [0029]    An embodiment of two-directional ESD protection device according to the invention as shown on  FIG. 3B  protects an internal circuit against ESD effects and harms in both directions. The two-directional ESD protection device comprises: (a) a first ESD port P 1  with voltage V 1  for ESD current acceptance/discharge while an ESD event happens on the internal circuit; (b) a second ESD port P 2  with voltage V 2  for ESD current discharge/acceptance while an ESD event happens on the internal circuit; (c) a 1 st  NMOS  310  with its gate connected to the first ESD port P 1 , its drain connected to the first ESD port P 1 , and its source connected to the second ESD port P 2 , wherein a short between its drain and source is formed to shunt ESD current without passing through the internal circuit while voltage differential between the first ESD port P 1  and the second ESD port P 2  is larger and equal than its gate threshold voltage V th  (V 1 −V 2 ≧V th ); and (d) a 2 nd  NMOS  320  with its gate connected to the second ESD port P 2 , its drain connected to the second ESD port P 2 , and its source connected to the first ESD port P 1 , wherein a short between its drain and source is formed to shunt ESD current without passing through the internal circuit while voltage differential between the second ESD port P 2  and the first ESD port P 1  is larger and equal than its gate threshold voltage V th  (V 2 −V 1 ≧V th ). In normal operation, the absolute value of voltage differential between the first ESD port P 1  and the second ESD port P 2  is smaller than gate threshold voltage V th  (|V 1 −V 2 |&lt;V th ) and is small enough to not form a short between drain and source on either of the 1 st  NMOS and the 2 nd  NMOS. Furthermore, the 1 st  NMOS is operable to be a field n-channel metal-oxide-semiconductor field effect transistor (field NMOS) with a field oxide layer below gate for increasing threshold voltage V th . By choosing the filed NMOS from different semiconductor process, the threshold voltage V th  can be adjusted to fit different operation voltage condition (V 1 −V 2 &lt;V th ). In an exemplary embodiment, the 1 st  NMOS with a field NMOS having larger V th  can be used between I/O port with open drain output and power voltage V DD  directly as ESD protection. Additionally, an operable poly-gate design on gate of the 1 st  NMOS provides the better ESD protection result. Furthermore, the 2 nd  NMOS is operable to be a field n-channel metal-oxide-semiconductor field effect transistor (field NMOS) with a field oxide layer below gate for increasing threshold voltage V th . By choosing the filed NMOS from different semiconductor process, the threshold voltage V th  can be adjusted to fit different operation voltage condition (V 2 −V 1 &lt;V th ). In an exemplary embodiment, the 2 nd  NMOS with a field NMOS having larger V th  can be used as ESD protection to against ESD event from power voltage V DD . Additionally, an operable poly-gate design on gate of the 2 nd  NMOS provides the better ESD protection result. 
         [0030]      FIG. 5A  is a layout structure for the two-directional ESD protection device. The cross-section structure along c-c line on  FIG. 5A  is shown on  FIG. 5B . Increasing/decreasing the width (W) of poly-gate grown on field oxide layer according to the layout on  FIG. 5A  is also to increase/decrease the loading of ESD current in n channel below the poly gate in for fitting different requirements of ESD protection. 
         [0031]    In an exemplary embodiment, a voltage range of normal operation is between V DD −15V and V DD +15V. A two-directional ESD protection device according to the invention can keep the internal circuit working normally event when the working voltage is negatively near V DD +15V or positively near V DD −15V, and shunt ESD current to against any abnormal discharge beyond the operation range. 
         [0032]    Accordingly, as disclosed by the above description and accompanying drawings, the present invention surely can accomplish its objective to provide ESD protection method and device with known and adjustable trigger voltage, and may be put into industrial use especially for mass product. 
         [0033]    It should be understood that various modifications and variations could be made from the teaching disclosed above by the person familiar in the art, without departing the spirit of the present invention.