Abstract:
The subject invention reveals new three terminal tapped inductor canonical cells for non-isolated power conversion. The canonical cells achieve reduced semiconductor component stresses for applications with limited line voltage range for small step up and step down ratios or for large step up and step down ratios. Some of the canonical cells can be used to form buck, boost, and buck boost converters. Another of the canonical cells is a member of the SEPIC family which can both step up and step down or operate in all four quadrants. Related canonical cells which achieve zero voltage switching and improved electromagnetic compatibility are also revealed. A new more robust floating gate drive control circuit is revealed which operates without magnetic components, without optical coupling, and without high voltage semiconductors is revealed.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of PPA Ser. No. 60/757,561, filed Jan. 7, 2006 by the present inventor. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The subject invention generally pertains to electronic power conversion circuits, and, more specifically, to high frequency, switched mode electronic power converters. The subject matter relates to new non-isolated power conversion networks which provide high efficiency power conversion under special conditions where more conventional power conversion networks do not work well. 
   2. Description of Related Art 
   The solution to the problem of converting power where the input to output or output to input voltage ratio is either very small or very large has traditionally relied upon tapped inductor power converters. An example of a circuit that achieves improved efficiency over the known alternatives for large input to output step down ratios is illustrated in  FIG. 1 .  FIG. 1  is a tapped inductor buck converter. Compared to a simple buck converter the component stress factors for the  FIG. 1  circuit are superior to the simple buck converter. M 1  in  FIG. 1  operates at higher duty cycle and lower current than the high side switch of the simple buck converter and M 2  operates at lower duty cycle and higher current than the low side switch of the simple buck converter. The voltage stress of M 1  is increased over the voltage stress of the high side switch in the simple buck converter and the voltage stress of M 2  is reduced by comparison to the low side synchronous rectifier of the simple buck converter. In the  FIG. 1  circuit the component stresses of M 1  and M 2  are evenly shared, whereas in the simple buck converter the conduction losses are almost all in the low side switch since the duty cycle for the simple buck converter is very small. Also the  FIG. 1  circuit has advantages over the simple buck converter in that the switching losses for the M 1  switch are reduced in the  FIG. 1  circuit, because the current in the M 1  switch is reduced. The switch M 1  in  FIG. 1  experiences an increased voltage stress compared to the high side main switch in a simple buck converter, which offsets some of the advantages of the tapped inductor configuration, yet there is still a net benefit to the tapped inductor approach. The voltage applied to M 1  during its off state is equal to the input voltage plus the L 1  winding voltage. There is a buck derived converter that is useful for high step down ratios wherein the switch voltage stress never exceeds the input voltage, which is illustrated in  FIG. 2 . The  FIG. 2  circuit is not a tapped inductor circuit and does not provide power to the load during the on time of the main switch M 1 , but it does provide isolation. What is needed is a tapped inductor buck converter without a voltage stress penalty for the main switch. 
   A circuit that has grown in popularity in recent years, especially for battery powered circuits is the single ended primary inductor converter (SEPIC), and, particularly, the four switch, dual modulator SEPIC.  FIG. 19  illustrates how the four switch dual modulator SEPIC is synthesized from buck and boost converters connected in cascade. The four transistor dual modulator SEPIC uses a single inductor and can convert an input voltage to an output voltage that is either higher than or lower than the input voltage. In many cases the output voltage is near to the input voltage so that the step up or step down ratio is very small. If the output voltage is always less than the input voltage, then a tapped inductor buck converter would be the best solution. If the output voltage was always greater than the input voltage a tapped inductor boost converter would be the best solution. What is needed is a tapped inductor SEPIC converter for the condition where the step up or step down ratio is small, but which can operate as either a step up or step down converter depending on whether the line voltage is less than or greater than the load voltage, respectively. 
   Both the SEPIC and the tapped inductor buck converter employ a high side switch. A reliable method for driving the high side switch employs a gate drive transformer. As time passes semiconductor solutions are becoming ever cheaper and are smaller than gate drive transformers. Level shifting transistor circuits work well at low voltages, but at high voltages the level shifting circuits are relatively slow and lossy. One semiconductor solution to high side drive is illustrated in  FIG. 29 . The  FIG. 29  circuit achieves an improvement over its prior art by providing positive current feedback around the Schmitt buffer, which rejects changes in the output state of the Schmitt buffer due to small variations in the floating reference voltage (FRV). The positive current feedback achieves an enormous improvement in active clamp circuits where the source voltage of the high side switch varies during the on time of the high side switch. The  FIG. 29  circuit is not immune from large fast changes in the floating reference voltage that can cause changes of state of the Schmitt buffer that are not commanded. For example, when the high side switch is commanded off, usually this would coincide with a command to turn on the low side switch, but, if there is a subsequent command to turn off or keep off the low side switch during the transition, then the floating reference voltage of the high side switch will swing low and then swing back high again. When the floating reference swings high, the input to the Schmitt trigger is pulled low, which results in turning the high side switch on again, which will likely not be the desired result. In order to turn off and keep off the high side switch, an OR gate and opto-coupler can be added to independently disable the high side switch, as illustrated in  FIG. 30 , but this circuit too has some drawbacks. Opto-couplers are relatively slow and the faster opto-couplers draw 10 milliamperes or more of current. They also have physical characteristics that change over time more than other types of semiconductors. They are often disallowed for military, space, and other high reliability applications, because of physical changes with aging. What is needed is a more reliable and faster semiconductor gate drive solution for switches with floating reference voltages, such as the high side switches in the new tapped inductor circuit topologies revealed in the subject application. 
   OBJECTS AND ADVANTAGES 
   An object of the subject invention is to reveal new beneficial circuit topologies for applications with limited line voltage range and either very large or very small step up or step down ratios. 
   Another object of the subject invention is to reveal new beneficial circuit topologies with lower component stress factors for applications with limited line voltage range where the converter must be capable of both small ratio step up and step down operation. 
   Another object of the subject invention is to reveal new improved methods of driving switches with floating reference voltages which can reject changes in state due to changes in the floating reference voltage. 
   Further objects and advantages of my invention will become apparent from a consideration of the drawings and ensuing description. 
   These and other objects of the invention are provided by novel circuit techniques that limit voltage stress of the power converter&#39;s switches and reduce component stress factors and which achieve more reliable high side drive where a floating reference voltage would otherwise create unintended changes in the conduction state of a high side switch. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by reference to the drawings. 
       FIG. 1  illustrates a tapped inductor buck converter for large step down ratio according to the prior art. 
       FIG. 2  illustrates an isolated coupled inductor buck converter according to the prior art. 
       FIG. 3  illustrates a non-isolated tapped inductor buck converter with reduced voltage stress according to the subject invention. 
       FIG. 4(   a ) illustrates the voltage wave form for the M 1  switch of  FIG. 3  according to the subject invention. 
       FIG. 4(   b ) illustrates the voltage wave form for the M 2  switch of  FIG. 3  according to the subject invention. 
       FIG. 4(   c ) illustrates the voltage wave form for the M 3  switch of  FIG. 3  according to the subject invention. 
       FIG. 4(   d ) illustrates the current wave form for the M 1  switch of  FIG. 3  according to the subject invention. 
       FIG. 4(   e ) illustrates the current wave form for the M 2  switch of  FIG. 3  according to the subject invention. 
       FIG. 4(   f ) illustrates the current wave form for the M 3  switch of  FIG. 3  according to the subject invention. 
       FIG. 4(   g ) illustrates the current wave form for the L 1  winding of  FIG. 3  according to the subject invention. 
       FIG. 4(   h ) illustrates the current wave form for the L 2  winding of  FIG. 3  according to the subject invention. 
       FIG. 5  illustrates a power conversion network, based on the  FIG. 3  circuit, which can be configured to form a variety of power conversion circuits according to the subject invention. 
       FIG. 6  illustrates the power conversion network of  FIG. 5  used to form a tapped inductor buck converter for large step down ratio applications according to the subject invention. 
       FIG. 7  illustrates the power conversion network of  FIG. 5  configured to form a tapped inductor boost converter for large step up ratio applications according to the subject invention. 
       FIG. 8  illustrates the power conversion network of  FIG. 5  configured to form a tapped inductor buck boost converter for large step down ratio inverting applications according to the subject invention. 
       FIG. 9  illustrates the power conversion network of  FIG. 5  configured to form a tapped inductor buck converter for small step down ratio applications according to the subject invention. 
       FIG. 10  illustrates the power conversion network of  FIG. 5  configured to form a tapped inductor boost converter for small step up ratio applications according to the subject invention. 
       FIG. 11  illustrates the power conversion network of  FIG. 5  configured to form a tapped inductor buck boost converter for large step up ratio inverting applications according to the subject invention. 
       FIG. 12  illustrates the circuit of  FIG. 3  and the power conversion network of  FIG. 5  with an uncoupled inductance added in series with the L 1  winding to form a tapped inductor buck converter with a zero voltage switching mechanism according to the subject invention. 
       FIG. 13  illustrates the  FIG. 12  circuit with a clamp diode added to eliminate ringing associated with the series inductance L 3  and the intrinsic capacitance, C S3 , of S 3  according to the subject invention. 
       FIG. 14  illustrates the  FIG. 12  circuit with an active clamp network added to eliminate ringing associated with the series inductance L 3  and the intrinsic capacitance of S 3  according to the subject invention. 
       FIG. 15  illustrates a fully clamped zero voltage switching tapped inductor power conversion network according to the subject invention. 
       FIG. 16  illustrates a fully clamped zero voltage switching tapped inductor power conversion network with an alternate series inductance connection that is equivalent to the power conversion network of  FIG. 15  according to the subject invention. 
       FIG. 17  illustrates the power conversion network of  FIG. 15  applied to form a large step down ratio fully clamped zero voltage switching tapped inductor buck converter according to the subject invention. 
       FIG. 18(   a ) illustrates the voltage wave form of the M 1  switch of the  FIG. 17  circuit according to the subject invention. 
       FIG. 18(   b ) illustrates the voltage wave form of the M 2  switch of the  FIG. 17  circuit according to the subject invention. 
       FIG. 18(   c ) illustrates the voltage wave form of the M 3  switch of the  FIG. 17  circuit according to the subject invention. 
       FIG. 18(   d ) illustrates the voltage wave form of the M 4  switch of the  FIG. 17  circuit according to the subject invention. 
       FIG. 18(   e ) illustrates the current wave form of the M 1  switch of the  FIG. 17  circuit according to the subject invention. 
     FIG.  18 (( f ) illustrates the current wave form of the M 2  switch of the  FIG. 17  circuit according to the subject invention. 
       FIG. 18(   g ) illustrates the current wave form of the M 3  switch of the  FIG. 17  circuit according to the subject invention. 
       FIG. 18(   h ) illustrates the current wave form of the M 4  switch of the  FIG. 17  circuit according to the subject invention. 
       FIG. 19  illustrates the transformation of a buck converter followed by a boost converter into a four switch dual modulator SEPIC according to the prior art. 
       FIG. 20  illustrates a tapped inductor four switch dual modulator SEPIC for small step up and step down ratios according to the subject invention. 
       FIG. 21(   a ) illustrates the voltage wave form of the S 1  switch of the  FIG. 20  circuit for the condition in which the input voltage is larger than the output voltage according to the subject invention. 
       FIG. 21(   b ) illustrates the voltage wave form of the S 2  switch of the  FIG. 20  circuit for the condition in which the input voltage is larger than the output voltage according to the subject invention. 
       FIG. 21(   c ) illustrates the voltage wave form of the S 3  switch of the  FIG. 20  circuit for the condition in which the input voltage is larger than the output voltage according to the subject invention. 
       FIG. 21(   d ) illustrates the voltage wave form of the S 4  switch of the  FIG. 20  circuit for the condition in which the input voltage is larger than the output voltage according to the subject invention. 
       FIG. 21(   e ) illustrates the current wave form of the S 1  switch of the  FIG. 20  circuit for the condition in which the input voltage is larger than the output voltage according to the subject invention. 
       FIG. 21(   f ) illustrates the current wave form of the S 2  switch and the L 2  winding of the  FIG. 20  circuit for the condition in which the input voltage is larger than the output voltage according to the subject invention. 
       FIG. 21(   g ) illustrates the current wave form of the S 3  switch and the L 3  winding of the  FIG. 20  circuit for the condition in which the input voltage is larger than the output voltage according to the subject invention. 
       FIG. 21(   h ) illustrates the current wave form of the S 4  switch and the L 1  winding of the  FIG. 20  circuit for the condition in which the input voltage is larger than the output voltage according to the subject invention. 
       FIG. 22(   a ) illustrates the voltage wave form of the S 1  switch of the  FIG. 20  circuit for the condition in which the input voltage is smaller than the output voltage according to the subject invention. 
       FIG. 22(   b ) illustrates the voltage wave form of the S 2  switch of the  FIG. 20  circuit for the condition in which the input voltage is smaller than the output voltage according to the subject invention. 
       FIG. 22(   c ) illustrates the voltage wave form of the S 3  switch of the  FIG. 20  circuit for the condition in which the input voltage is smaller than the output voltage according to the subject invention. 
       FIG. 22(   d ) illustrates the voltage wave form of the S 4  switch of the  FIG. 20  circuit for the condition in which the input voltage is smaller than the output voltage according to the subject invention. 
       FIG. 22(   e ) illustrates the current wave form of the S 1  switch and the L 1  winding of the  FIG. 20  circuit for the condition in which the input voltage is smaller than the output voltage according to the subject invention. 
       FIG. 22(   f ) illustrates the current wave form of the S 2  switch and the L 2  winding of the  FIG. 20  circuit for the condition in which the input voltage is smaller than the output voltage according to the subject invention. 
       FIG. 22(   g ) illustrates the current wave form of the S 3  switch and the L 3  winding of the  FIG. 20  circuit for the condition in which the input voltage is smaller than the output voltage according to the subject invention. 
       FIG. 22(   h ) illustrates the current wave form of the S 4  switch of the  FIG. 20  circuit for the condition in which the input voltage is smaller than the output voltage according to the subject invention. 
       FIG. 23  illustrates a power conversion network based on the  FIG. 19  circuit which can be used to form a variety of power conversion circuits according to the subject invention. 
       FIG. 24  illustrates the power conversion network of  FIG. 23  connected to form a four quadrant converter for large step down ratios according to the subject invention. 
       FIG. 25  illustrates the power conversion network of  FIG. 23  with inductances added in series with L 2  and L 3  in order to achieve zero voltage switching and active clamp networks added to fully clamp each winding of the network according to the subject invention. 
       FIG. 26  illustrates a power conversion network formed from a cascade combination of the tapped inductor buck converter of  FIG. 9  and the tapped inductor boost converter of  FIG. 10  combined in the manner illustrated in  FIG. 19  according to the subject invention. 
       FIG. 27  illustrates the power conversion network of  FIG. 26  with series inductances and active clamp networks added to form a zero voltage switching fully clamped power conversion network according to the subject invention. 
       FIG. 28  illustrates the power conversion network of  FIG. 26  configured to form a four quadrant converter for large step down ratios according to the subject invention. 
       FIG. 29  illustrates a high side drive control circuit with positive current feedback for rejecting small variations of the floating reference voltage according to the prior art. 
       FIG. 30  illustrates the high side drive control circuit of  FIG. 29  with an OR gate and opto-coupler for disabling the circuit on command according to the prior art. 
       FIG. 31  illustrates a high side drive circuit containing a digital logic circuit based on NAND gates that rejects all variations of the floating reference voltage according to the subject invention. 
       FIG. 32  illustrates a high side drive circuit containing a digital logic circuit based on NOR gates that rejects all variations of the floating reference voltage according to the subject invention. 
       FIG. 33  illustrates a high side drive circuit containing a digital logic circuit based on flip flops that rejects all variations of the floating reference voltage according to the subject invention. 
       FIG. 34  illustrates a high side drive circuit containing a generalized digital logic circuit that rejects all variations of the floating reference voltage according to the subject invention. 
       FIG. 35  illustrates a high side drive circuit containing a generalized digital logic circuit that rejects all variations of the floating reference voltage which is similar to the circuit of  FIG. 34  but uses the inverted output of the generalized digital logic circuit and a non-inverting driver to achieve identical results to the  FIG. 34  circuit according to the subject invention. 
       FIG. 36  illustrates a digital logic circuit that generates brief delays in the timing signals used to control the high side drive circuit of  FIG. 34  during the brief transition times according to the subject invention. 
       FIG. 37  illustrates floating gate drive control circuits of  FIG. 34  used to control the two high side switches of  FIG. 3  according to the subject invention. 
       FIG. 38  illustrates floating gate drive control circuits of  FIG. 34  used to control the two high side switches of  FIG. 20  according to the subject invention. 
       FIG. 39(   a ) illustrates a timing signal indicating the status of the floating reference voltage (FRV) of a high side switch according to the subject invention. 
       FIG. 39(   b ) illustrates a PWM timing input signal for a floating gate drive control circuit based on a combination of the circuits of  FIG. 36  and  FIG. 34  according to the subject invention. 
       FIG. 39(   c ) illustrates the output timing signal of the digital logic circuit of  FIG. 36  which also forms the non-inverted input of the  FIG. 34  circuit for a floating gate drive control circuit based on a combination of the circuits of  FIG. 36  and  FIG. 34  according to the subject invention. 
       FIG. 39(   d ) illustrates the node A voltage timing signal for a floating gate drive control circuit based on a combination of the circuits of  FIG. 36  and  FIG. 34  according to the subject invention. 
       FIG. 39(   e ) illustrates the node B voltage timing signal for a floating gate drive control circuit based on a combination of the circuits of  FIG. 36  and  FIG. 34  according to the subject invention. 
       FIG. 39(   f ) illustrates the non-inverted output voltage timing signal for a floating gate drive control circuit based on a combination of the circuits of  FIG. 36  and  FIG. 34  according to the subject invention. 
   

   SUMMARY 
   The subject invention reveals new tapped inductor converter topologies that are useful for power converters with limited line voltage range and either small or large step up or step down load to line voltage ratios. The new circuit topologies achieve lower component voltage stress than prior art circuit topologies. Zero voltage switching variations of the new circuits are also revealed as well as new tapped inductor SEPIC family circuit structures. In addition, a robust semiconductor high side drive control circuit is revealed that achieves full control of a switch with a floating reference voltage without the use of magnetic components, opto-couplers or level shifting circuits. 
   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3  illustrates a minimum voltage tapped inductor buck converter according to the subject invention. In  FIG. 3  a first terminal of a source of dc voltage and power, V IN , is connected to a first terminal of a capacitor, C IN , and a first terminal, X, of a power conversion network. A second terminal of V IN  is connected to a second terminal of capacitor, C IN , a second terminal, Y, of the power conversion network, a first terminal of a capacitor, C OUT , and a first terminal of a load, R LOAD . The terminal, X, of the power conversion network is connected to a first terminal of a capacitor, C 1 , and a first terminal of a switch, M 2 . A second terminal of the capacitor, C 1 , is connected to an undotted terminal of a winding, L 1 , of a coupled inductor. A dotted terminal of the winding, L 1 , is connected to a second terminal of the switch M 2  and to the first terminal of a switch, M 1 . A second terminal of switch M 1  is connected to an undotted terminal of a winding L 2  of the coupled inductor and to a first terminal of a switch M 3 . A second terminal of switch M 3  is connected to terminal Y of the power conversion network. A dotted terminal of winding L 2  is connected to a third terminal Z of the power conversion network. The terminal Z of the power conversion network is connected to a second terminal of the capacitor C OUT , and to a second terminal of the load, R LOAD . 
   For purposes of description and analysis we will assume that the circuit has reached a steady state condition. We will assume that the operation of the switches is break before make and we will assume that the values of capacitors are sufficiently large that the capacitor voltages are invariant over a full cycle of operation. In steady state operation, except for brief transition times between states, there are two operating states of the  FIG. 3  circuit. In a first operating state the switch M 1  is on (conducting) and the switches M 2  and M 3  are off (not conducting). During the first operating state, current flows from V IN  through the X terminal, through C 1 , L 1 , M 1 , L 2  and through the Z terminal through R LOAD  and back to V IN . During the first operating state, stored energy builds in C 1  and the coupled inductor. During the first operating state, energy is transferred from the source V IN  to C 1 , the coupled inductor, and the load R LOAD . At the end of the first operating state the stored energy is a maximum in C 1  and the coupled inductor. At the end of the first operating state M 1  is turned off. At the beginning of the second operating state M 2  and M 3  are turned on. During the second operating state current flows from the first terminal of C 1  through M 2  into the dotted terminal of L 1  and back to the second terminal of C 1 , discharging C 1 . Current in L 1  induces current in L 2  adding to the current flowing out of the dotted terminal of L 2  during the first operating state. The current flowing in L 2  flows through the Z terminal to R LOAD  and through the Y terminal through M 3  back to L 2 . During the second operating state stored magnetic energy in the coupled inductor ramps down. During the second operating state energy is transferred from C 1  to the coupled inductor and from the coupled inductor to the load R LOAD . At the end of the second operating state the switches M 2  and M 3  are turned off and the cycle begins again when M 1  is turned on. 
   The voltages and currents for each of the switches and the currents for each of the windings are illustrated in  FIGS. 4(   a ) through  4 ( h ). 
   The  FIG. 3  circuit comprises a non-isolated voltage step down converter. The output voltage is given by 
               V   OUT     =       D   ⁢           ⁢     V   IN         (     1   +   n     )         ,         
where V OUT  is the load voltage, V IN  is the input dc source voltage, n is the ratio of the number of turns of L 1  to the number of turns of L 2 , and D is the fraction of a cycle that M 1  conducts. The  FIG. 3  circuit is particularly beneficial for applications in which the output voltage is a small fraction of the input voltage. In applications where the output is a small fraction of the input voltage and the output and input share a common return path the  FIG. 3  circuit has a lower component stress factor than a simple buck converter and will be significantly more efficient. Another beneficial feature of the  FIG. 3  circuit is the limited voltage stress of the switches. The maximum voltage stress for M 1  is V IN . The maximum stress for the other two switches is less than the voltage stress for M 1  and will depend on the turns ratio n and V IN .
 
   In the  FIG. 3  circuit M 3  appears as a synchronous rectifier. If a rectifier diode is substituted for M 3  the operation of the circuit will be the same as described above and the  FIG. 3  circuit with M 3  replaced by a diode should be considered an embodiment of the subject invention. 
   Incorporated within the  FIG. 3  circuit is a three terminal power conversion network, as illustrated in  FIG. 5 , wherein the three terminals are X, Y, and Z. This three terminal network of  FIG. 5  can be viewed as a canonical cell with its own transfer function and should be considered as an embodiment of the subject invention. The transfer function for the power conversion network (canonical cell) of  FIG. 5  is 
   
     
       
         
           
             
               
                 
                   V 
                   Z 
                 
                 = 
                 
                   
                     V 
                     Y 
                   
                   + 
                   
                     
                       
                         D 
                         ⁡ 
                         
                           ( 
                           
                             
                               V 
                               X 
                             
                             - 
                             
                               V 
                               Y 
                             
                           
                           ) 
                         
                       
                       
                         ( 
                         
                           1 
                           + 
                           n 
                         
                         ) 
                       
                     
                     . 
                   
                 
               
             
             
               
                 ( 
                 1 
                 ) 
               
             
           
         
       
     
   
   For the  FIG. 3  circuit V Y =0 since Y is a common or ground connection in  FIG. 3  for both the input and output, which we can arbitrarily set to zero without any loss of generality, V X =V IN , and V Z =V OUT . By making the substitutions indicated in equation (1) we obtain the transfer function for  FIG. 3 . 
   The power conversion network of  FIG. 5  can be used to form a set of different power conversion circuits depending on how line, load, and common are connected to the X, Y, and Z terminals.  FIG. 6 , which is the same circuit as  FIG. 3 , illustrates how one can form a buck converter for large step down ratios from the power conversion network of  FIG. 5 .  FIG. 7 , which is another embodiment of the subject invention, illustrates how the power conversion network of  FIG. 5  can be used to form a boost converter for large step up ratios. In  FIG. 7  V Y =0, V Z =V IN , and V X =V OUT . By substituting these values into equation (1) the transfer function for  FIG. 7  is obtained. For  FIG. 7  we obtain 
             V   IN     =     0   +         D   ⁡     (       V   OUT     -   0     )         (     1   +   n     )       .             
Usually the transfer function is solved for the output voltage and, in a boost converter the duty cycle refers to the fraction of a cycle that the lower switch, which is the switch connected to the common or ground, in this case S 3 , is on, but in equation (1) D applies to the duty cycle of the S 1  switch. For the  FIG. 7  circuit we need to replace D by (1−D′), where we now refer to the duty cycle of S 3 , so that
 
             V   OUT     =         (     1   +   n     )     ⁢     V   IN         (     1   -     D   ′       )             
for  FIG. 7 , where D′ is the fraction of a period that S 3  conducts. In the  FIG. 7  circuit the power flow is reversed in the power conversion network by comparison to  FIG. 6  and  FIG. 3 . The operating description provided for the  FIG. 3  circuit applies to the  FIG. 7  circuit, except that the line and load, or input and output, are reversed and the directions of all of the currents are reversed. Also, in the  FIG. 7  circuit S 3  is the main switch and, with its current direction reversed it cannot be implemented with a diode rectifier, however, the S 1  switch, with its reversed current can be implemented with a diode rectifier.
 
     FIG. 8 , which is another embodiment of the subject invention, illustrates a buck boost or non-isolated flyback converter for large voltage step down ratios formed from the power conversion network of  FIG. 5 . For  FIG. 8 , Z is the common terminal so that V Z =0, V X =V IN , and V Y =V OUT . We substitute these values into equation (1) to get the transfer function for  FIG. 8  which yields 
           0   =       V   OUT     +         D   ⁡     (       V   IN     -     V   OUT       )         (     1   +   n     )       .             
Solving for V OUT  yields
 
             V   OUT     =         -   D     ⁢           ⁢     V   IN         (     1   +   n   -   D     )             
for the transfer function of the  FIG. 8  circuit.
 
     FIG. 9 , which is another embodiment of the subject invention, illustrates a buck or step down converter for small step down ratios. For  FIG. 9  V Y =V IN , V X =0, and V Z =V OUT . Making these substitutions into equation (1) yields 
             V   OUT     =       V   IN     +         D   ⁡     (     0   -     V   IN       )         (     1   +   n     )       .             
Solving for V OUT  yields
 
               V   OUT     =         (     1   +   n   -   D     )     ⁢     V   IN         (     1   +   n     )         ,         
but D refers to the duty cycle of the S 1  switch. In common practice in a buck converter D refers to the duty cycle of the upper main buck switch, which is S 3  in  FIG. 9 , so that, to be consistent with common practice we will define D′ to be the duty cycle for the S 3  switch in  FIG. 9 , which requires that we replace D with (1−D′), which changes the transfer function for  FIG. 9  to
 
               V   OUT     =         (     n   +     D   ′       )     ⁢     V   IN         (     1   +   n     )         ,         
where D′ refers to the duty cycle of the S 3  switch.
 
     FIG. 10 , which is another embodiment of the subject invention, illustrates a boost or step up converter for small step up ratios. For  FIG. 10  V Z =V IN , V X =0, and V Y =V OUT . Making the substitutions into equation (1) yields 
             V   IN     =       V   OUT     +       D   ⁡     (     0   -     V   OUT       )         (     1   +   n     )               
for the  FIG. 10  transfer function. Solving for V OUT  yields
 
             V   OUT     =         (     1   +   n     )     ⁢     V   IN         (     1   +   n   -   D     )             
for  FIG. 10 .
 
     FIG. 11 , which is another embodiment of the subject invention, illustrates a buck boost or non-isolated flyback for small step up or step down ratios. The buck boost is an inverting power converter so that the output voltage will always have the opposite sign from the input voltage. For  FIG. 11  V Y =V IN , V Z =0, and V X =V OUT . Making the substitutions into equation (1) yields 
             V   OUT     =           (     D   -   1   -   n     )     ⁢     V   IN       D     .           
The main switch in a buck boost is the upper switch, which in this case would be S 3 , so we will replace D with (1−D′), which changes the transfer function for  FIG. 11  to
 
               V   OUT     =         -     (     n   +     D   ′       )       ⁢     V   IN         (     1   -     D   ′       )         ,         
where D′ refers to the duty cycle of the S 3  switch.
 
     FIG. 12 , which is another embodiment of the subject invention, illustrates the power conversion network of  FIG. 5  used to form a buck converter for large step down ratios, but with an inductance L 3  added in series with the L 1  winding. L 3  may be a separate and distinct discrete inductor or L 3  may be the leakage inductance of the coupled inductor referred to the L 1  winding side of the coupled inductor. L 3  can have the beneficial effect of storing energy to drive a zero voltage turn on transition of the converter&#39;s main switch, which, in this case, would be S 1 . If L 3  is a separate and distinct discrete inductor, then ringing associated with L 3  and the intrinsic capacitance of S 3  can be clamped by a diode, D CLAMP , as illustrated in  FIG. 13 , which is another embodiment of the subject invention. If L 3  is a leakage inductance of the coupled inductor then ringing associated with L 3  can be clamped and eliminated by using an active clamp network comprised of S 4  and C 2 , as illustrated in  FIG. 14 , which is another embodiment of the subject invention. The S 4  switch is operated in synchronization with the switch S 1  in order to provide clamping during the on time of S 1  when it is needed. The capacitor C 2  effectively parallels the C S3  capacitor and swamps its effect by lowering the resonance frequency to a frequency much smaller than the converters switching frequency so that the variation in voltage of C 2  is small during its operation, i.e. while the switch S 4  is conducting. The  FIG. 14  power conversion network has an advantage over the  FIG. 13  network in that any ringing associated with leakage inductance is fully clamped. Even with the clamp diode D CLAMP  of the  FIG. 13  circuit there will still be some leakage inductance which is unclamped in the  FIG. 13  network. Also, by using the leakage inductance to achieve zero voltage switching a second magnetic circuit element for that same purpose is obviated. 
   The components contained within the X, Y, and Z terminals of  FIGS. 12 ,  13 , and  14  constitute power conversion networks which can be used to form converters similar to those described above and illustrated in  FIGS. 6 through 11 , but with the added benefit of zero voltage switching.  FIG. 15 , which is another embodiment of the subject invention, is an example of one of these power conversion networks, which was derived from  FIG. 14 . It is also possible to place an inductor in series with the L 2  winding as an alternative to the placement illustrated in  FIGS. 12 through 15 , as illustrated in  FIG. 16 , which is another embodiment of the subject invention. The  FIG. 16  placement offers no advantage or disadvantage and the operation of the  FIG. 16  network is essentially identical to the operation of the power conversion network illustrated in  FIG. 15 . 
     FIG. 17 , which is another embodiment of the subject invention, is a fully clamped minimum voltage tapped inductor buck converter based on the  FIG. 15  power conversion network. The transfer function for the  FIG. 17  circuit is the same as the transfer function for the  FIG. 3  circuit. The current wave forms of the  FIG. 17  circuit are different from the wave forms for the hard switching circuit illustrated in  FIG. 3 , as illustrated in  FIGS. 18(   a ) through  18 ( h ). The only significant differences are small timing delays and some small differences that appear in the current wave forms which are effected by the presence of the series inductance L 3 . 
     FIG. 20 , which is another embodiment of the subject invention, illustrates a four switch dual modulator tapped inductor SEPIC for small step up and small step down voltage ratios. The SEPIC has been shown to be a cascade combination of a simple buck converter followed by a simple boost converter with the output inductor of the buck converter combined with the input inductor of the boost converter, as illustrated in  FIG. 19 .  FIG. 20  combines a winding of a tapped inductor buck converter with a winding of a tapped inductor boost converter to form a SEPIC with a single tapped inductor with three windings. Referring to  FIG. 20 , S 1 , S 2 , L 1 , and L 2  would, by themselves, form a tapped inductor buck converter for small step down ratios. Again, referring to  FIG. 20 , S 3 , S 4 , L 1 , and L 3  would, by themselves, form a tapped inductor boost converter for small step up ratios. In  FIG. 20  L 1  is shared between the buck stage and the boost stage and all windings occupy a common core. In operation when the input voltage is higher than the output voltage the duty cycle of S 4  is 100%, the duty cycle of S 3  is 0%, and S 1  and S 2  are modulated to regulate the output voltage, as in a conventional buck converter. When the input voltage is equal to the output voltage, the S 1  and S 4  switches have a duty cycle of 100% and the S 2  and S 3  switches have a duty cycle of 0%. When the input voltage is lower than the output voltage the duty cycle of the S 1  switch is 100%, the duty cycle of the S 2  switch is 0%, and the S 3  and S 4  switches are modulated to achieve the desired output voltage. Contained within the  FIG. 20  circuit is a three terminal power conversion network (canonical cell) defined by the terminals X, Y, and Z. The three terminal power conversion network can be used to form a SEPIC, but it can also be used to form other converter types, different than the SEPIC, by changing the connections of the X, Y, and Z terminals to line, load, and common. 
   In the  FIG. 20  circuit a first terminal of a dc source of voltage and power V IN  is connected to a first terminal of a capacitor C IN  and to an X terminal of a power conversion network. A second terminal of V IN  is connected to a second terminal of capacitor C IN , a terminal Y of the power conversion network, a first terminal of a capacitor C OUT , and a first terminal of a load R LOAD . The X terminal is connected to a first terminal of a switch S 1 . A second terminal of switch S 1  is connected to a dotted terminal of a winding L 1  of a coupled inductor and to an undotted terminal of a winding L 2  of the coupled inductor. A dotted terminal of winding L 2  is connected to a first terminal of a switch S 2 . A second terminal of switch S 2  is connected to the Y terminal of the power conversion network and to a first terminal of a switch S 3 . A second terminal of switch S 3  is connected to an undotted terminal of a winding L 3  of the coupled inductor. A dotted terminal of winding L 3  is connected to an undotted terminal of winding L 1  and to a first terminal of a switch S 4 . A second terminal of switch S 4  is connected to a Z terminal of the power conversion network. The Z terminal of the power conversion network is connected to a second terminal of capacitor C OUT  and to a second terminal of load R LOAD . 
   In operation the  FIG. 20  has three operating modes, determined by the input voltage and output voltage. In all three modes the input and output voltages have the same sign or polarity. In a first mode of operation the input voltage is larger in magnitude than the output voltage. In the first mode of operation there are two operating states separated by brief transition times between the two operating states. In a first operating state of the first operating mode switches S 1  and S 4  are on (conducting) and switches S 2  and S 3  are off (non-conducting). During the first operating state of the first operating mode current flows from V IN  to terminal X, through S 1 , through L 1 , through S 4 , through terminal Z, to load R LOAD , and returns to V IN . During the first operating state of the first operating mode stored magnetic energy ramps up in the coupled inductor and magnetizing current ramps up in L 1 . In a second operating state of the first operating mode switches S 2  and S 4  are on and switches S 1  and S 3  are off. During the second operating state of the first operating mode magnetic energy stored in the coupled inductor ramps down and provides power to the load. During the second operating state of the first operating mode, current flows in a loop containing S 2 , L 2 , L 1 , S 4 , terminal Z, load R LOAD , and terminal Y in a clockwise direction in the loop. The current during the second operating state of the first operating mode is significantly less than the current during the first operating state of the first operating mode due to the fact that current flows through two windings during the second operating state of the first operating mode. During the second operating state of the first operating mode current ramps down in magnitude. The circuit&#39;s voltage and current wave forms are illustrated in  FIGS. 21(   a ) through  21 ( h ) for the first operating mode. At the end of the second operating state of the first operating mode switch S 2  is turned off and the cycle begins again. 
   A second operating mode occurs when the input voltage is equal to the output voltage. In the second operating mode there is one operating state. In the second operating mode switches S 1  and S 4  are on and switches S 2  and S 3  are off. Current flows from V IN  to R LOAD  through terminals X and Z, through switches S 1  and S 4 , and through winding L 1 . In the second operating mode there is no change in current and there is no change in the stored magnetic energy in the coupled inductor. 
   A third operating mode occurs when the input voltage magnitude is less than the output voltage magnitude. The third operating mode has two operating states. In a first operating state of the third operating mode switches S 1  and S 3  are on and switches S 2  and S 4  are off. During the first operating state of the third operating mode current flows from V IN  through terminal X, through S 1 , L 1 , L 2 , S 3 , and terminal Y back to V IN . During the first operating state of the third operating mode stored magnetic energy ramps up in the coupled inductor. During the first operating state of the third operating mode current ramps up in the L 1  and L 3  windings. At the end of the first operating state of the third operating mode switch S 3  is turned off. At the beginning of a second operating state of the third operating mode switch S 4  is turned on. During the second state of the third operating mode current ramps down in L 1  and the stored magnetic energy in the coupled inductor ramps down. The current during the second operating state of the third operating mode is significantly larger than the current during the first operating state of the third operating mode since the current flows in only one winding during the second operating state of the third operating mode. Current and voltage wave forms for the third operating mode are illustrated in  FIGS. 22(   a ) through  22 ( h ). At the end of the second operating state of the third operating mode switch S 4  is turned off and the cycle repeats. 
     FIG. 23 , which is another embodiment of the subject invention, illustrates the power conversion network which forms a part of the SEPIC of  FIG. 20 . The  FIG. 23  power conversion network is a canonical cell which can be used to form converter types other than the SEPIC merely by changing the connections between the X, Y, and Z terminals and line, load, and ground. A transfer function for the  FIG. 23  power conversion network can be formed based on the X, Y, and Z terminal voltages. There are three transfer functions for the  FIG. 23  network. There is a different transfer function for each operating mode. For the first operating mode the transfer function is 
                     (       V   X     -     V   Z       )     ⁢     D   1       =         (       V   Z     -     V   Y       )     ⁢     (     1   -     D   1       )         (     1   +   n     )               (   2   )               
where D 1  is the duty cycle of switch S 1  and n is the turns ratio of winding L 2  to winding L 1 . For the second operating mode the transfer function is
 V X =V Z   (3) 
and for the third operating mode the transfer function is
 
                       (       V   X     -     V   Y       )     ⁢     D   2         (     1   +   n     )       =       (       V   Z     -     V   X       )     ⁢     (     1   -     D   2       )               (   4   )               
where D 2  is the duty cycle of switch S 3  and n is the turns ratio of winding L 3  to winding L 1 . For the  FIG. 20  circuit V X =V IN , V Y =0, and V Z =V OUT . Making these substitutions in equations (2), (3), and (4) yields
 
             V   OUT     =         (     1   +   n     )     ⁢     D   1     ⁢     V   IN         (     1   +     n   ⁢           ⁢     D   1         )             
for the transfer function of the first operating mode, V OUT =V IN , for the transfer function of the second operating mode, and
 
             V   OUT     =         (     1   +   n   -     n   ⁢           ⁢     D   2         )     ⁢     V   IN           (     1   -     D   2       )     ⁢     (     1   +   n     )               
for the transfer function of the third operating mode.
 
     FIG. 24 , which is another embodiment of the subject invention, illustrates the power conversion network of  FIG. 23  connected to form a four quadrant converter for large step down ratios. For the  FIG. 24  circuit V X =0, V Y =V IN , and V Z =V OUT . Making these substitutions into equations (2), (3), and (4) yields 
             V   OUT     =         (     1   -     D     1   ⁢                 )     ⁢     V   IN         (     1   +     n   ⁢           ⁢     D   1         )             
for the transfer function of the first operating mode, V OUT =0 for the transfer function of the second operating mode, and
 
             V   OUT     =         -     D   2       ⁢     V   IN           (     1   +   n     )     ⁢     (     1   -     D   2       )               
for the transfer function of the third operating mode.
 
     FIG. 25 , which is another embodiment of the subject invention, illustrates the power conversion network of  FIG. 23  with an inductance placed in series with the L 2  winding and an inductance placed in series with the L 3  winding and with active clamp networks added to fully clamp every winding of the network during every operating state. The series inductances may be either discrete inductors or they may be leakage inductances of the coupled inductor. The series inductances provide a magnetic energy storage mechanism which can be used for achieving zero voltage switching for all switching transitions. S 5  and C 1  form a first active clamp network for eliminating ringing associated with the L 1  winding when S 1  is off, S 6  and C 2  form a second active clamp network for eliminating ringing associated with the L 2  and L 4  windings when S 2  is off, S 7  and C 3  form an active clamp network for eliminating ringing associated with the L 3  and L 5  windings when S 3  is off, and S 8  and C 4  form an active clamp network for eliminating ringing associated with the L 1  winding when S 4  is off. The transfer functions for the  FIG. 25  power conversion network are the same as the transfer functions for the  FIG. 23  network. In practice, the voltage wave forms are nearly identical to those for the  FIG. 23  network, as illustrated in  FIGS. 21 and 22 , but the current wave forms are altered to form ramps of higher slope due to the effects of the series inductances. The differences in the current wave forms between the  FIG. 23  and  FIG. 25  networks are similar to the differences in the current wave forms between the  FIG. 5  and  FIG. 16  networks. 
     FIG. 26 , which is another embodiment of the subject invention, illustrates another variation of the  FIG. 23  power conversion network. The  FIG. 26  network adds a capacitor C 1  in series with winding L 2  and a capacitor C 2  in series with winding L 3 . A switch S 5  is added parallel to the series network of C 1  and L 2  and a switch S 6  is added parallel to the series network of C 2  and L 3 . The addition of the switches S 5  and S 6  and the capacitors C 1  and C 2  to the  FIG. 23  power conversion network results in a reduction of voltage stress of all of the circuit&#39;s switches. The transfer functions for the  FIG. 26  network differ from those of the  FIG. 23  network. The operation of the switches is as indicated in  FIG. 26  except that during the first operating state the duty cycle for S 6  is 0% and the duty cycle for switch S 5  is 0% during the third operating state. For the first operating mode the transfer function is 
                 V   X     -     V   Z       =         [       V   Z     -     V   Y     -     n   ⁡     (       V   X     -     V   Z       )         ]     ⁢     (     1   -     D   1       )           (     1   -   n     )     ⁢     D   1           ,         
for the second operating mode the transfer function is V X =V Z , and for the third operating mode the transfer function is
 
               V   Z     -     V   X       =           [       V   X     -     V   Y     -     n   ⁡     (       V   Z     -     V   X       )         ]     ⁢     D   2           (     1   +   n     )     ⁢     (     1   -     D   2       )         .           
The  FIG. 26  power conversion network can be used to form practical minimum voltage tapped inductor SEPICs for small step up and step down ratios and practical minimum voltage tapped inductor four quadrant converters for large step down ratios.
 
     FIG. 27 , which is another embodiment of the subject invention, illustrates a power conversion network similar to the  FIG. 26  power conversion network but with inductances L 4  and L 5  added in series with L 2  and L 3 , respectively, and with the addition of two active clamp networks. The series inductances can be discrete inductors or leakage inductances of the coupled inductor. An active clamp network comprised of S 7  and C 3  is added in parallel to S 1  to clamp the L 1  winding during the off state of S 1  and an active clamp network comprised of S 8  and C 4  is added in parallel with S 4  to clamp L 1  during the off state of S 4 . The operation of the switches is as indicated in  FIG. 27  except that during the first operating state the duty cycle for S 6  is 0% and the duty cycle for switch S 5  is 0% during the third operating state. With the added series inductances a mechanism exists to provide stored magnetic energy that can be used to achieve zero voltage switching for all of the switches for every transition. The active clamp networks provide full clamping for all of the windings for every operating state so that there is no ringing possible associated with the coupled inductor and circuit parasitic capacitances. 
     FIG. 28 , which is another embodiment of the subject invention, illustrates a minimum voltage tapped inductor four quadrant converter suitable for large step down ratios using the power converter network of  FIG. 26  and implemented with mosfet switches. During the first operating mode switch M 4  is constantly on, switches M 3  and M 6  are constantly off, D 1  has a value between 0% and 100%, and the load voltage at terminal Z is positive with respect to the X terminal voltage which is the circuit&#39;s ground. As D 1  is decreased the voltage at the output rises in magnitude. During a second operating mode switches M 1  and M 4  are constantly on and all of the other switches are off and the output voltage is zero. During a third operating mode switch M 3  is constantly on, switches M 2  and M 5  are constantly off, and the output voltage is negative. As D 2  is increased the output voltage becomes increasingly negative. 
     FIG. 31 , which is another embodiment of the subject invention, illustrates a floating gate drive control circuit for a high side switch or other switch with floating reference voltage compared to the originating timing signals. The originating timing signal is labeled PWM in  FIG. 31  and it appears in both inverted and non-inverted forms as inputs to the floating gate drive control circuit. The desired result is the change of state of the output labeled OUT in both its non-inverted and inverted forms in response to a change in state of the originating PWM signal and the rejection of changes in state due to changes in the floating reference voltage. Suppose that initially the PWM signal is in a high logic state and OUT is also in a high voltage state so that the output of U 2C  is high and the output of U 2D  is low. The node A voltage will be high and the node B voltage will be low in the initial condition. Because the node B voltage is low the U 2B  output will be high and both inputs to U 2A  will be high so that the output of U 2A  will be low. With the U 2A  output low the output of U 2C  will be high and both inputs to U 2D  will be high so the output of U 2D  will be low. With the output of U 2D  low both inputs to U 2C  are low. When the floating reference voltage rises nodes A and B will both go to a low state and the outputs of U 2A  and U 2B  will both go to a high state. This change does not effect inputs to U 2D  since both inputs were initially high, but now one of the inputs to U 2C  is a high, but since the output of U 2D  is still low one of the inputs to U 2C  is low, so the output of U 2C  will remain high during the transition in which the floating reference voltage is rising. When the transition is complete and the floating reference voltage stops rising, the node A voltage will return to its initial high state driven by the output of U 2C  through R 3 . During a fast negative going transition the capacitors C 1  and C 2  must discharge which forces the voltage at nodes A and B to a high state. With the output of U 2A  initially in a low state the U 2B  output will remain in its initial high state so that the U 2A  output will also remain unchanged during the negative going transition of the floating reference voltage. Since there is no change in the outputs of U 2A  and U 2B  there can be no change in the outputs of U 21C  and U 2D . When the negative going transition is complete and the floating reference voltage stops changing the output of U 2D  will force the node B voltage back to its initial low state through R 4 . During a time interval in which the floating reference voltage is relatively steady a change in the PWM signal from high to low will create a low voltage at node A and a high voltage at node B. The low voltage at node A will force the output of U 2A  to a high state. With the node B voltage in a high state and the output of U 2A  high the output of U 2B  will go to a low state. The low state at the output of U 2B  will force the output of U 2D  high so that both of the inputs of U 2C  will be high and the output of U 2C  will go low. Positive current feedback to node A from U 2C  through R 3  helps node A to reject small or slow variations of the floating reference voltage that might otherwise cause the node A voltage to change state. Similarly positive current feedback to node B from U 2D  through R 4  helps node B to reject small of slow variations of the floating reference voltage that might otherwise cause the node B voltage to change state. The digital logic circuit comprising the four 2 input NAND gates and the positive current feedback resistors R 3  and R 4  form a floating gate drive control circuit that responds to fast changes in the originating signals and rejects changes in the floating reference voltage. 
     FIG. 32 , which is another embodiment of the subject invention, shows an alternate method of realizing the same performance as achieved by the  FIG. 31  circuit. The  FIG. 32  circuit uses four 2 input NOR gates instead of the NAND gates of  FIG. 31 . Another alternate method of achieving the same results is illustrated in  FIG. 33 , which is another embodiment of the subject invention, wherein two cascaded flip flops are used in place of the NAND gates. In all of the  FIGS. 31 through 33  when the node A and node B voltages are different then the outputs will change state, but if the node A and node B voltage have the same state then no change in the outputs is allowed. There are likely many digital logic circuits that can achieve the same results as the digital logic circuits illustrated in  FIGS. 31 through 33 .  FIG. 34 , which is another embodiment of the subject invention, illustrates the floating gate drive control circuit with a general digital logic circuit wherein the digital logic circuit may be any of the digital logic circuits illustrated in  FIGS. 31 through 33  or any of a number of other digital logic circuits that generate the same outputs from the same inputs.  FIG. 35 , which is another embodiment of the subject invention, illustrates that the inverting output from the digital logic circuit can be used with a non-inverting gate driver as an alternative to the non-inverting output of the digital logic circuit combined with an inverting gate driver to accomplish gate drive control. 
   In order to accomplish a change in state for the digital logic circuit of the floating gate drive control circuits of  FIGS. 31 through 35  complementary simultaneous fast transitions must be applied to the node A and node B inputs to the digital logic circuits. If the originating signal were to change state during a time interval in which the floating reference voltage is rising or falling rapidly then the desired change in state of the digital logic circuit may not occur because a rapidly rising floating reference voltage will force the node A and node B voltages into a low state regardless of the change in the originating signal and a rapidly falling floating reference voltage will force the node A and node B voltages into a high state regardless of the change in the originating signal.  FIG. 36 , which is another embodiment of the subject invention, illustrates a circuit that delays a change in state of the originating signals to the floating gate drive control circuit for the duration of a time interval in which the floating reference voltage is rapidly changing. With a floating reference voltage that is neither rising nor falling the OR gates in  FIG. 36  will pass through the logic state of the originating signals which will be inverted in the NAND gates, but when the floating reference voltage (FRV) is rising the output of the OR gates will both be high which will disallow any change in state of the NAND gates. R 7  holds the FRV inputs to the OR gates low when the floating reference voltage is steady and D 1  clamps the FRV inputs to the OR gates to ground when the FRV is falling. R 8  limits current into the OR gates so that the OR gates will not be damaged by the C 3  current. When the floating reference voltage is steady the AND gates will pass on the inputs from the outputs of the NAND gates to the NOR gates which perform a second inversion, but if the floating reference voltage is falling then one of the ANDs inputs will be low and the outputs of both AND gates will be low which will disallow any change in state at the outputs of the NOR gates. R 9  holds the FRV inputs to the AND gates high when the FRV is steady and R 10  prevents damage to the FRV inputs to the AND gates from C 4  currents. In summary no change in state is allowed while the floating reference voltage is rising and no change in state is allowed while the floating reference voltage is falling so that any change in state at the outputs of the NOR gates will be delayed while the floating reference voltage is rising or falling. Changes in state commanded by the originating signal are accomplished but are delayed until a time at which the change will effect the output and achieve the desired result. Any change in state of the originating signal will be passed on while the floating reference voltage is steady and unable to effect the voltages at the nodes A and B at the inputs to the digital logic circuit of the floating gate drive control circuit. With the combination of the  FIG. 36  circuit and the  FIG. 34  or  FIG. 35  circuit a floating gate drive control circuit with complete immunity to changes in floating reference voltage is achieved.  FIGS. 39(   a ) through  39 ( f ) illustrate voltages at circuit nodes within the circuits illustrated in  FIGS. 35 and 36 . In  FIG. 39(   a ) FRV refers to the floating reference voltage. The transition times indicated in  FIG. 39(   a ) are much longer than typical transition times in actual practice for purposes of illustrating the operation of the circuit. 
     FIG. 37 , which is another embodiment of the subject invention, illustrates a minimum voltage tapped inductor buck converter for large step down ratios with the switches implemented with mosfets, similar to the  FIG. 3  circuit, illustrating the application of the floating gate drive control circuit to the high side switches with floating reference voltages in the  FIG. 3  circuit. 
     FIG. 38 , which is another embodiment of the subject invention, illustrates a tapped inductor SEPIC for small step down and step up ratios implemented with mosfets as switches wherein the high side switches are controlled by the floating gate drive control circuits of the subject invention. 
   CONCLUSION, RAMIFICATIONS, AND SCOPE OF INVENTION 
   Thus the reader will see that by the addition of a capacitor and a switch to a prior art tapped inductor power conversion network a new tapped inductor power conversion network is formed with reduced component voltage stress and high efficiency. Variations of the new power conversion network which achieve zero voltage switching for all of the switches for every switching transition are revealed including forms which eliminate all ringing associated with series inductance used to provide stored magnetic energy used to drive zero voltage turn on transitions. Other new tapped inductor power conversion networks are revealed which provide reduced component stresses in SEPIC and four quadrant converters, including several new forms that achieve zero voltage switching and lower switch voltage stress than all of the prior art. Also, a capacitor coupled floating gate drive control circuit is revealed which can achieve reliable operation while the reference voltage of a high side switch changes rapidly. New circuit forms which combine the floating gate drive control circuit with tapped inductor power conversion networks to form new beneficial power converters with a minimum of magnetic components are revealed. 
   While my above description contains many specificities, these should not be construed as limitations on the scope of the invention, but rather, as exemplifications or preferred embodiments thereof. Many other variations are possible. For example, in some of the circuits illustrated one can find alternate workable connections of the active clamp networks that accomplish full clamping of the same winding in the same operating state as the active clamp network illustrated in the figures of this application, but these too should be considered embodiments of the subject invention. There are specific digital logic circuits revealed in the subject invention to achieve the results claimed but many other digital logic circuits that can achieve the same outputs with the same inputs should also be considered embodiments of this invention. Circuits similar to the circuits shown but with polarity of the input or output reversed from that illustrated in the figures shall be considered embodiments of the subject invention. Circuits similar to those shown, but having coupled magnetic circuit elements with more than two windings and circuits with more than one output shall be considered embodiments of the subject invention. In many of the circuits shown there are series connected networks. The order of placement of circuit elements in series connected networks is inconsequential in the illustrations shown so that series networks in the illustrated circuits with circuit elements reversed or placed in an entirely different order within series connected networks are equivalent to the circuits illustrated and shall be considered embodiments of the subject invention. Also, most of the embodiments illustrated show simple switches, but the operation revealed and the benefits achieved in the subject invention can also be realized in circuits that implement the switches using N channel mosfets, P channel mosfets, IGBTs, JFETs, bipolar transistors, junction rectifiers, or schottky rectifiers, which should be considered embodiments of the subject invention. 
   Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their legal equivalents.