Abstract:
A circuit arrangement for limiting excessive voltages by a forward delay time of a first diode is described. The first diode is alternately switched in a non-conducting direction and a conducting direction by switching a circuit element. The first diode is series-connected to a first capacitor and a pre-charging circuit is provided for the first capacitor, the pre-charging circuit charging the first capacitor while the first diode is switched in the non-conducting direction. The pre-charging circuit charges the first capacitor more strongly than an excessive voltage of the first diode with regard to the amount.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is the U.S. National Stage of International Application No. PCT/EP2007/063485 filed Dec. 7, 2007, and claims the benefit thereof. The International Application claims the benefits of Austrian Patent Application No. A 110/2007 AT filed Jan. 23, 2007; both of the applications are incorporated by reference herein in their entirety. 
     
    
     FIELD OF INVENTION 
       [0002]    The invention relates to a circuit arrangement for limiting voltage overshoots due to the forward recovery time of a diode which is switched alternately between reverse-biased (non-conducting) and forward-biased (conducting) by switching of a switching element. 
       BACKGROUND OF INVENTION 
       [0003]    Voltage overshoots due to the forward recovery time for diodes are problematic in particular in the case of very fast switching operations. With slow switching operations, the diode is usually made conducting by application of the forward bias voltage, which in the case of silicon diodes is in the region of about 0.7 V. With fast switching times, on the other hand, it already becomes noticeable that the diode becomes conductive only after a finite time has elapsed. In particular when a switch is made from reverse-biased to forward-biased, a certain period of time is required in order to distribute the charge carriers over the entire cross-section of the space charge region and, as it were, to “flood” said region with charge carriers. This finite time is critical in particular when high currents are to be conducted through the diode, when, for instance, the diode is a snubbing diode for inductances. In these cases the diode does not become conducting already at the forward bias voltage, as is critical for slow switching operations, but only at higher voltages. Said higher forward bias voltage during fast switching operations is referred to as voltage overshoot. In this case the voltage overshoot is a function of the current rise rate (mostly specified in Alps) and can be found in the corresponding data sheets for the particular diode. 
         [0004]    These voltage overshoots due to the forward recovery time for diodes are conventionally counteracted by an over-dimensioning of the components requiring protection. A further possibility consists in slowing down the switching operations, although this entails other disadvantages, such as, for instance, additional switching losses in switching components. 
       SUMMARY OF INVENTION 
       [0005]    It is an object of the invention to avoid these disadvantages and to provide a circuit arrangement which limits voltage overshoots due to the forward recovery time for diodes. This object is achieved by a circuit as claimed in the claims. 
         [0006]    A circuit arrangement for limiting voltage overshoots due to the forward recovery time of a first diode which is switched alternately between reverse-biased (non-conducting) and forward-biased (conducting) by switching of a switching element is provided. In this case it is provided that the first diode is connected in series with a first capacitor, and a pre-charging circuit for the first capacitor is provided, said circuit charging the first capacitor while the first diode is switched to reverse bias. The pre-charging at the first capacitor and the voltage associated therewith causes the first diode to start conducting by said voltage value earlier. The voltage overshoot is therefore reduced. If said voltage value exceeds the voltage overshoot of the first diode, the voltage overshoot can be avoided completely. 
         [0007]    The first diode can be connected in series with the first capacitor on the anode side. For this situation, it is proposed that the pre-charging circuit includes a second capacitor connected in parallel with the first diode, and a third diode, the third diode being connected on the anode side to the second capacitor, and on the cathode side to the side of the first capacitor facing the first diode. 
         [0008]    However, the first diode can alternatively also be connected in series with the first capacitor on the cathode side. In this case, a pre-charging circuit can be realized for example such that the pre-charging circuit includes a second capacitor connected in parallel with the first diode, and a third diode, the third diode being connected on the cathode side to the second capacitor, and on the anode side to the side of the first capacitor facing the first diode. 
         [0009]    The first capacitor is connected in parallel with a second diode which is connected co-directionally with the first diode. In this arrangement the second diode takes over the current flowing through the first capacitor as soon as it becomes conducting in relation to the charge state of the first capacitor. The term “connected co-directionally”, in this context, means that when the current flows in the same direction the two diodes are either both switched to reverse-biased (non-conducting) or both switched to forward-biased (conducting). 
         [0010]    A preferred application of the switching arrangement is in transformer circuits such as occur in inverters or switched-mode power supplies. The switching element is connected on the primary side of a transformer circuit in series with the primary winding of a transformer, and primary winding and switching element are connected to a direct-current voltage source, the first diode being connected in the circuit as a snubbing diode for the primary winding. 
         [0011]    Further, a switched-mode power supply having a circuit arrangement as described is provided. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The invention is explained in more detail below with reference to an exemplary embodiment and with the aid of the accompanying figures, in which: 
           [0013]      FIG. 1  shows a first exemplary circuit of the inventive circuit arrangement, and 
           [0014]      FIG. 2  shows a further embodiment variant of the inventive circuit arrangement. 
       
    
    
     DETAILED DESCRIPTION OF INVENTION 
       [0015]      FIG. 1  shows a circuit arrangement having a switching element S 1 , which is typically a semiconductor switch, in particular a power switch. In the exemplary embodiment shown the switching element S 1  is connected on the primary side of a transformer circuit in series with the primary winding W 1  of a transformer T, and primary winding W 1  and switching element S 1  are connected to a direct-current voltage source U S . By periodically opening and closing the switching element S 1  the direct-current voltage of the direct-current voltage source U S  is converted into voltage pulses which are transferred via the transformer T onto the secondary side of the transformer circuit. 
         [0016]      FIG. 1  also shows that a first diode D 1  is connected in the circuit as a snubbing diode for the primary winding W 1 . The first diode Di is switched to reverse-biased in relation to the direct-current voltage source U S . If the switching element S 1  is open, current flows via the intermediate circuit of the first diode D 1 , such that the first diode D 1  is switched alternately between reverse-biased and forward-biased as a function of the switch state of the switching element S 1 . 
         [0017]    In order to limit voltage overshoots due to the forward recovery time of the first diode D 1 , the latter is inventively connected on the anode side in series with a first capacitor C 1 . Provided in addition is a pre-charging circuit for the first capacitor C 1  which positively charges the side of the first capacitor C 1  facing the first diode D 1 , while the first diode D 1  is switched to reverse-biased. The first capacitor C 1  is also connected in parallel with a second diode D 2  which is connected co-directionally with the first diode D 1 . 
         [0018]    In the exemplary embodiment shown in  FIG. 1  the pre-charging circuit includes a second capacitor C 2  connected in parallel with the first diode D 1 , and a third diode D 3 , the third diode D 3  being connected on the anode side to the second capacitor C 2 , and on the cathode side to the side of the first capacitor C 1  facing the first diode D 1 . 
         [0019]    Furthermore, the parallel circuit of first diode D 1  and second capacitor C 2  is connected in series with a parallel circuit of a third capacitor C 3  and a Zener diode. These switching elements are purely optional and simply illustrate one means of protecting the switching element S 1  by building a direct-current counter voltage which protects the switching element S 1  but does not disrupt the normal operation of the transformer T. 
         [0020]    In practice, however, in contrast to the embodiment variant according to  FIG. 1 , an attempt will be made to use the scattered energy in the primary circuit of the transformer T following opening of the switching element S 1 , for instance with the aid of a circuit in which the scattered energy is fed back into a voltage source intermediate circuit. An example of this is shown in  FIG. 2 .  FIG. 2  shows a circuit arrangement in which a further switching element S 1 ′ is connected in series with the primary winding W 1 . The two switching elements S 1 , S 1 ′ are each assigned an intermediate circuit comprising the snubbing diodes D 1  and D 1 ′. The inventive circuit arrangement is used with both snubbing diodes D 1 , D 1 ′, albeit in the form of two different exemplary embodiments, i.e. with an anode-side arrangement of the first capacitor C 1  in relation to the first diode D 1 , and with a cathode-side arrangement of the first capacitor C 1 ′ in relation to the first diode D 1 ′. In the latter case the pre-charging circuit accordingly includes a second capacitor C 2 ′ connected in parallel with the first diode D 1 ′, and a third diode D 3 ′, the third diode D 3 ′ being connected on the cathode side to the second capacitor C 2 ′, and on the anode side to the side of the first capacitor C 1 ′ facing the first diode D 1 ′. 
         [0021]    The switching-related states of the inventive circuit arrangement can be subdivided into four phases and are explained with reference to  FIG. 1 . 
         [0022]    In a first phase, the switching element S 1  is closed and the first diode D 1  is switched to reverse-biased. During the reverse bias phase the first capacitor C 1  is pre-charged via the pre-charging circuit consisting of the second capacitor C 2  and the third diode D 3  with a voltage which advantageously equals a fraction of the reverse voltage at the first diode D 1 . In this case the side of the first capacitor C 1  facing the first diode D 1  is positively charged. 
         [0023]    In a second phase, the switching element S 2  is opened and the voltage at the switching element S 1  becomes more positive until the sum of the voltage at the switching element S 1  and that at the first capacitor C 1  becomes more positive than the sum of the voltages U E  and U Z  (see  FIG. 1 ). 
         [0024]    In a third phase, the first diode D 1  now becomes conducting and the voltage overshoot described in the introduction occurs. Given suitable dimensioning, said voltage overshoot is less than the voltage at the first capacitor C 1 , with the result that in this phase the voltage at the switching element S 1  always remains below the sum of the voltages U E  and U Z . Following the turn-on delay of the first diode D 1  the potential at the anode of the first diode D 1  lies by only a diode threshold above the potential at its cathode. The third phase ends after the voltage at the first capacitor C 1  becomes negative and the second diode D 2  becomes conducting. It should be noted here that voltage overshoots at the second diode D 2  are negligible in practice because the voltage rise at the second diode D 2  is less, and it can be dimensioned with smaller reverse voltages. Thus, the second diode D 2  behaves in a noncritical manner in terms of its forward recovery time. 
         [0025]    In a fourth phase, the second diode D 2  takes over the current that previously flowed through the first capacitor C 1 . The voltage at the switching element S 1  now amounts to the sum of the voltages U E  and U Z  and two diode thresholds. 
         [0026]    Accordingly, voltage overshoots due to the forward recovery time in the case of the first diode D 1  are limited with the aid of the circuit arrangement according to the invention, which is of advantage in particular in the case of very fast switching operations.