Abstract:
A method and circuit are provided for delaying a transition in a digital data stream fed to a write head of a mass storage device by a certain time interval when the transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbol nonlinear interference effects suffered when reading the stored data. The method includes feeding digital data stream to be stored and a clock signal to a first circuit and outputting a pair of digital streams from the first circuit. The first stream assumes a first logic value every time a transition of the input stream occurs during a clock phase not successive to a clock phase during which a transition of the input stream has occurred. The second stream assumes the first logic value every time a transition of the input stream occurs during a clock phase following a clock phase during which a transition has taken place in the input stream. The method also includes feeding the two digital streams and the clock signal to the inputs of a second circuit and outputting the digital data stream from the second circuit directed to the write head. The transitions immediately following a preceding transition are delayed by the pre-established time interval, by sampling the two digital streams with a pair of flip-flops, each of which is respectively timed by clock signals respectively delayed by a certain different time interval.

Description:
FIELD OF THE INVENTION 
     The present invention relates to read/write channels of mass data storage devices, for example of a hard disk drive, and more particularly, to a method and circuit of pre-compensation, during a write phase, of the effects of nonlinear intersymbol interference during a subsequent read phase of the recorded data. 
     BACKGROUND OF THE INVENTION 
     Due to the ever-growing density with which data must be stored on hard disks or similar magnetic media, it is useful, during the write phase of the data, to delay a transition, i.e. the switching of a bit from a low state to a high state or vice-versa, when in the immediately preceding clock phase there has been a transition in the opposite direction. This approach serves to compensate the shift of the physical position of the second transition towards the preceding transition already recorded on the hard disk. This anticipation (during a reading phase) of the second transition is mainly due to the so-called nonlinear intersymbol interference caused by the presence of a demagnetizing field produced by an immediately preceding transition, as well as by the partial data deletion in the transition zone due to the high density of data stored on the hard disk. 
     To implement this pre-compensation, i.e. to delay the transitions that immediately follow another transition, special circuitry is used comprising a delay circuit and a multiplexer to switch from the system clock to a slightly delayed clock to delay the output data stream. This switching is effected by a signal generated by a control circuit that identifies two transitions intervening in the input data stream as consecutive transitions. 
     Due to the generally high system clock frequencies, this type of approach has several drawbacks. A first drawback is that to operate at the system clock frequency, the delay circuit and the control circuit must be realized in ECL technology (Emitter Coupled Logic), with a consequent increase in the complexity and costs of the fabrication process compared to a typically preferred fully CMOS technology (Complementary Metal Oxide Semiconductor). A further drawback is that the multiplexer, operating at a high frequency, generates glitches that reduce the reliability of the device itself. Moreover, the delay circuit may delay the system clock for up to a half period, because greater delays would imply a write error at the instant of the switching from the delayed clock back to the system clock. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a pre-compensation method for overcoming such drawbacks and limitations of the conventional approach and provide an implementing circuit that may be realized in CMOS technology. These and other objects are achieved by the method and circuit of the present invention. 
     The method of the invention is for delaying a transition in a digital data stream directed towards a write head of a mass storage device by a certain time interval when the transition occurs at the clock pulse following the one during which a transition has already occurred, for pre-compensating for the effects of nonlinear intersymbol interference during a reading of the recorded data. The method includes feeding a first circuit with a digital data stream to be recorded and with a clock signal and outputting a pair of digital streams. The first stream assumes a first logic value every time a transition in the input stream occurs at a clock pulse not following a clock pulse during which a transition has taken place. The second stream assumes the first logic value every time a transition in the input stream occurs at a clock pulse that follows a clock pulse during which a transition has taken place. 
     The method also includes feeding the two digital streams and the clock signal to the inputs of a second circuit and outputting from the second circuit, the digital stream of data directed towards the write head. The transitions immediately successive to a preceding transition are delayed by the pre-established time interval, by sampling the two streams by a flip-flop pair, each of which is timed by a clock signal delayed by a respectively different time interval. The temporal difference between the different delay intervals is equal to a pre-established time interval, and the two signals output from the flip-flop pair are re-combined through an XOR logic gate into the output digital stream. Preferably, the two streams are preliminarily resynchronized by way of a first pair of flip-flops, timed by the clock signal, before effecting the sampling with the two diversely delayed clock signals. 
     According to another aspect of the invention, a circuit is provided for delaying each transition that immediately follows a preceding transition in a digital stream of input data. The circuit comprises a control circuit including at least a pair of propagation paths of a digital stream of input data, each path having an output bistable switch timed by a clock signal. The output bistable switch of a first path outputs a first digital stream of transitions nonsuccessive to another transition, and the output bistable switch of the other path outputs a second digital stream of transitions successive to another transition. 
     The circuit further comprises a delay circuit including at least an output XOR logic gate receiving the first and second digital streams whose transitions are independently delayed by different time intervals such that the difference is equal to a prefixed time interval, through respective inputs. The delay circuit outputs a recombined digital stream of selectively delayed data identical to the data of the input stream. The bistable output switches of the two propagation paths of the control circuit may be flip-flops synchronized by the clock signal and the paths may optionally comprise resynchronizing input flip-flops and a combinatory logic circuit identifying first transitions not immediately following a preceding transition and second transitions immediately following a preceding transition. Such a logic circuit may include an XOR layer, an AND layer and another XOR layer. 
     Since the transitions so discriminated of one of the two streams of each pair of propagation paths may be delayed with respect to the transitions of the other stream, of a certain freely programmable time interval, the delay and reconfirmation block of the circuit of the invention allows for the introduction of delays even greater than a half period of clock signal, without causing any write error on the storage support. 
     According to a particularly favorable aspect of the present invention, the control circuit and the delay and recombination circuit may comprise multiple sets of components arranged in a tree-like structure and reciprocally connected by way of a plurality of pairs of propagation paths. In this way and by feeding several distinct input digital streams of fractional clock frequencies, the circuits may function at a reduced (fractional) clock frequency. Therefore, even the most critical parts in terms of speed requirements, as for example the control circuit (discrimination between the two types of transitions), may be realized in CMOS technology with attendant advantages in terms of simplicity of the design and reduced costs. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other advantages and aspects of the present invention will become even more evident to the experts in the field through the ensuing detailed description of several embodiments and by referring to the annexed drawings, wherein: 
     FIG. 1 is a diagram of the delay circuit according to a first embodiment of the present invention; 
     FIG. 2 is a diagram of the control circuit for the embodiment of FIG. 1; 
     FIG. 3 is a diagram of the delay circuit according to a second embodiment of the present invention; 
     FIG. 4 is a diagram of the control circuit for the embodiment of FIG. 3; and 
     FIG. 5 is a diagram of the delay circuit according to a third embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     By referring to FIG. 1, a first embodiment of the circuit of the present invention will be described. The circuit includes a delay circuit DC 1  having an input Ck for receiving a system clock signal, and two data inputs N and R, respectively coupled to a pair of positive edge-triggered, D-type flip-flops FN 1  and FR 1 , synchronized by the clock signal Ck. The flip-flops FN 1  and FR 1  serve to synchronize the two digital streams or input streams N and R whenever they are reciprocally out of phase because of delays that may be introduced by upstream stages. 
     The outputs Q of the flip-flops FN 1  and FR 1 , are coupled to the respective inputs of the pair of positive edge-triggered D-type flip-flops FN 2  and FR 2 . However, these two flip-flops FN 2  and FR 2  are timed by two clock signals which are generally different from the system clock Ck and indeed are two differently delayed replicas of the system clock obtained by way of two delay circuits, respectively DN and DR, which delay the system clock Ck by an independently programmable time interval, respectively Dn and Dr. 
     In particular, one delay circuit DN delays the input clock Ck by a interval Dn, preferably slightly greater than the delay caused by the D-type flip-flops, while the other delay circuit DR delays the input clock Ck by a interval Dr such that the difference between Dr and Dn is substantially equal to the delay that must be introduced in the transitions immediately successive to another transition in the output data stream. The Q outputs of the flip-flops FN 2  and FR 2  are coupled to respective inputs of an XOR logic gate X 1  that outputs (O) a recombined and selectively delayed data stream directed towards the write head of the mass storage device. 
     By referring to FIG. 2, it may be observed that the N and R inputs of the delay circuit DC 1  correspond to the N and R outputs of a control circuit CC 1  which through one of its inputs receives the system clock signal Ck and through another input I, an input data stream directed toward the write head of the mass storage device after having selected and suitably delayed the transitions that follow an immediately preceding transition (obviously in terms of the succession of pulses of the clock signal Ck). Such a control circuit CC 1  comprises a pair of XOR logic gates, X 2  and X 3 , each of which serves to detect the presence of a transition respectively between the last and the second last input bit, as well as between the second last and third last input bit. Such preceding bits originate from a pair of D-type, positive edge-triggered flip-flops FI 1 , FI 2  connected in cascade and synchronized with the clock signal Ck. 
     The logic gate X 2  receives the signals coming from the input I and from the flip-flop FI 1  as input, while the logic gate X 3  receives the signals coming from the flip-flops FI 1  and FI 2  as input. With this arrangement, the output of the logic gate X 2  is high if a transition has just occurred and the output of the logic gate X 3  is high if a transition occurred in the preceding clock phase. The outputs of the logic gates X 2  and X 3  are in turn coupled to a pair of logic AND gates A 1  and A 2 , respectively. While the logic gate A 2  receives the outputs of logic gates X 2  and X 3  as input, the logic gate A 1  receives the output of the logic gate X 2  and the inverted output of the logic gate X 3  as input. In this way, the output of the logic gate A 1  is high if a transition has just occurred and if a transition has not taken place in the preceding clock phase, whereas the output of the logic gate A 2  is high if two consecutive transitions have occurred. 
     Each output of the logic gates A 1  and A 2  outputs to a bistable switch which inverts its output from low to high and vice-versa in presence of a high input signal. According to an embodiment, the bistable are a pair of positive edge-triggered D-type flip-flop, FI 3  and FI 4 , which receive the outputs of two logic XOR gates X 4  and X 5  as input, respectively. These gates receive the Q outputs of the flip-flops FI 3  and FI 4  and the outputs of the logic gates A 1  and A 2  as input. Therefore, the Q outputs of the flip-flops FI 3  and FI 4  coupled to the N and R outputs of the control circuit CC 1 , transmit two signals corresponding to the output of the two bistable switches controlled by the signals of the logic gates A 1  and A 2 . Of course, in other embodiments, the bistable switches may be implemented by different circuits, for example by edge-triggered T-type flip-flops, generally referred to as toggle circuits. 
     The following truth table shows the state of the outputs of the components of the circuits DC 1  and CC 1  during 24 successive periods T, assuming for example, the data stream string of 24 bits “101011100001100101110101” as input, with the predefined state of the flip-flops FI 1  and FI 2  being a low state and the predefined state of the flip-flops FI 3  and FI 4  being a high state, and the parallel delays due to the FN 1 , FN 2 , FR 1  and FR 2  flip-flops being neglected. 
     
       
         
               
             
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 truth table of the DC1 and CC1 circuits 
               
             
          
           
               
                 T 
                 I 
                 FI1 
                 FI2 
                 X2 
                 X3 
                 A1 
                 A2 
                 N 
                 R 
                 O 
               
               
                   
               
               
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
               
               
                 2 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
               
               
                 3 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
               
               
                 4 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
               
               
                 5 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
               
               
                 6 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
               
               
                 7 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
               
               
                 8 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
               
               
                 9 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 10 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 11 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 12 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
               
               
                 13 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
               
               
                 14 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
               
               
                 15 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 16 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
               
               
                 17 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
               
               
                 18 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
               
               
                 19 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
               
               
                 20 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
               
               
                 21 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
               
               
                 22 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
               
               
                 23 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                 24 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
               
               
                   
               
             
          
         
       
     
     As may be observed from the above table, the input and output data stream are equal, however, such a data stream is actually subjected to a decomposition in two parallel digital streams, the transitions of which are delayed by two different time intervals Dn and Dr, before the two streams are recombined in a unique flow of digital data through the logic XOR gate X 1 . In particular, in the embodiment shown, the digital stream to be delayed propagated through the input N on the signal path comprising the delay circuit DN, contains the nonconsecutive transitions of the input stream I, while the digital stream to be delayed, propagated through the input R on the line comprising the delay circuit DR, contains the consecutive transitions of the input stream I. In this way, the two digital streams N and R, suitably delayed by different amounts, may be recombined in the logic gate X 1  thus reconstructing the input data stream wherein the transitions that immediately follow another are delayed by a certain pre-established interval. 
     By referring to FIG. 3, according to another embodiment, the device of the present invention comprises a delay block DC 2  that includes two delay circuits DC 1 ′ and DC 1 ″, each similar to the delay circuit DC 1  of the embodiment described above. The circuits DC 1 ′ and DC 1 ″ receive the RA, NA, RB, NB, signals as input which are similar to the R and N inputs of the delay circuit DC 1  described above. The DC 1 ′ and DC 1 ″ circuits receive a clock signal Ck/2, whose frequency is halved by a dedicated circuit (not shown in the figure). The OA and OB outputs of the delay circuits DC 1 ′ and DC 1 ″ are combined in a logic XOR gate X 6 , which outputs the data stream directed to the write head of the mass storage support. Briefly delayed by the delay circuits DC 1 ′ and DC 1 ″ respectively by the intervals of time Dn and Dr, the lines NA, RA and NB, RB converge towards the output O. 
     With reference to FIG. 4, the NA, RA and NB, RB outputs of the control circuit CC 2  are input to the delay circuit DC 2 . The control circuit CC 2  receives the halved system clock signal Ck/2 and two streams IA and IB, respectively the odd bits and the even bits of the input data stream. It should be noted that the control circuit CC 2  is functionally similar to the control circuit CC 1 , the functional components being connected in a tree-like structure in order to handle two data streams. 
     In particular, the control circuit CC 2  comprises a pair of logic gates X 2 ′, X 3 ′ and a further XOR gate X 3 ″, each of which serves to detect the presence of a transition, between the last odd bit and the last even bit and the second last odd bit and the second last even bit, as well as between the last odd bit and the second last even bit of the input stream. Such preceding bits are derived from a pair of positive edge-triggered D-type flip-flops, FI 1 ′, FI 2 ′, connected in cascade and synchronized by the signal Ck/2. The logic gate X 2 ′ receives the signals from the IA and IB inputs, the logic gate X 3 ′ receives the signals output by the FI 1 ′ and FI 2 ′ flip-flops as input while the logic gate X 3 ′ receives the signals from the IA input and from the FI 2 ′ flip-flop as input. In this way the output of the logic gate X 2 ′ is high if a transition has just occurred, the output of the logic gate X 3 ′ is high if a transition occurred in the preceding clock phase and the output of the logic gate X 3 ″ is high if there has been a transition between the even bit and the odd bit during the preceding clock phase. 
     The outputs of the logic gates X 2 ′, X 3 ′ and X 3 ″ are coupled to two pairs of logic AND gates A 1 ′, A 2 ′ and A 1 ″, A 2 ″, respectively. The gates A 2 ′, A 2 ″ receive the outputs of the gates X 3 ′, X 3 ″ and X 2 ′, X 3 ″ as input, respectively, the logic gates A 1 ′, A 1 ″ receive the output of the gate X 3 ″ and the inverted output of the gate X 3 ′ as input, respectively, and the output of the gate X 2 ′ and the inverted output of the logic gate X 3 ″ as input, respectively. 
     Each output of the logic gates A 1 ′, A 2 ′ and A 1 ″, A 2 ″, is coupled to a bistable switch. In this embodiment, such bistable switches include two pairs of positive edge-triggered D-type flip-flops: FI 3 ′, FI 4 ′ and FI 3 ″, FI 4 ″, which receive the outputs of two pairs of logic XOR gates: X 4 ′, X 4 ″ and X 5 ′, X 5 ″ as input. These gates receive the Q outputs of the FI 3 ″ and FI 4 ″ flip-flops and the outputs of the logic gates X 4 ′, X 5 ′, as well as the outputs of the logic gates A 1 ′, A 2 ′ and A 1 ″, A 2 ″ as input. The Q outputs of the flip-flops FI 3 ′, FI 4 ″ and FI 3 ″, FI 4 ″, respectively coupled to the outputs NA, RA and NB, RB of the control circuit CC 2 , transmit two pairs of digital streams corresponding to the outputs of the two pairs of bistable switches controlled by the signals of the logic gates A 1 ′, A 2 ′ and A 1 ″, A 2 ″. Of course, the bistable switches may also be implemented by similar circuits, for example with edge-triggered T-type flip-flops, usually referred to as toggle circuits. 
     The following truth table shows the output state of the components of the circuits DC 2  and CC 2  in 24 successive clock phases T, assuming, for example, the data stream string of 24 bits “101011100001100101110101” as input, with the predefined state of the FI 1 ′ and FI 2 ′ flip-flops being the low state and the predefined state of the flip-flops FI 3 ′, FI 4 ′ and FI 3 ″, FI 4 ″, being the high state, the parallel delays due to the flip-flops of the delay circuit DC 2  being neglected. In particular, the alternate data streams of the O output, obtained by alternatively combining through the X 6  gate the data stream of the OB output with the data stream of the OA output, are indicated in columns O′ and O″. 
     
       
         
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 truth table of the DC2 and CC2 circuits 
               
             
          
           
               
                 T 
                 IA 
                 IB 
                 FI1′ 
                 FI2′ 
                 X2′ 
                 X3′ 
                 X3″ 
                 A1′ 
                 A2′ 
                 A1″ 
                 A2″ 
                 NA 
                 RA 
                 NB 
                 RB 
                 OA 
                 OB 
                 O′ 
                 O″ 
               
               
                   
               
               
                 1 
                 1 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
               
               
                 2 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
               
               
                 3 
                 1 
                 1 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                 4 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
               
               
                 5 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 0 
               
               
                 6 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 1 
               
               
                 7 
                 1 
                 0 
                 0 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
               
               
                 8 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 1 
               
               
                 9 
                 0 
                 1 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
               
               
                 10 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 1 
               
               
                 11 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                 0 
                 1 
               
               
                 12 
                 0 
                 1 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
               
               
                   
               
             
          
         
       
     
     Also in this embodiment, the input and output data streams are equivalent, though the data stream is subjected to a decomposition in two distinct streams, the transitions of which are differently delayed before recombining the two streams through the logic XOR gate X 6 . 
     FIG. 5 depicts yet another embodiment of the device of the present invention comprising a delay block DC 3  which in turn includes two pairs of delay circuits DC 1 ′, DC 1 ″ and DC 1 ′″, DC 1 ″″, all functionally similar to the circuit DC 1  of the first embodiment. These multiple delay circuits are connected to a plurality of logic XOR gates X 7 , X 7 ′ and X 7 ″ in form of a tree-like structure terminating with the output O which outputs the data stream directed to the write head. The delay circuits DC 1 ′, DC″ and DC 1 ′″, DC″″ receive signals equivalent to those received through the R and N inputs of the delay circuits DC 1  of FIG. 1, through the RA, NA, RB, NB and RA′, NA′, RB′, NB′ inputs, respectively. However, in this embodiment, the input data stream, besides being subdivided in two alternate streams by a control circuit equivalent to the control circuit CC 2  of FIG. 4, is further decomposed and fed through the RA′, NA′, RB′, NB′ inputs for further delaying the transitions that follow a second transition of a series of consecutive transitions. Briefly, after having been delayed by the delay circuits DC 1 ′″ and DC 1 ″″ with additional time intervals Dn′ and Dr′, lower than the Dn and Dr intervals that are introduced by the delay circuits DC 1 ′ and DC″, the input streams NA′, RA′, NB′, RB′ merge at the O output. 
     From the above description of preferred embodiments of the device according to the present invention, it is evident that in similar embodiments, more parallel streams on lines, N and R, may be contemplated with each delayed by a certain time interval different from the other streams, which are then all merged through a plurality of logic XOR gates disposed according to a tree structure, to obtain a recomposed data stream with selected transitions suitably delayed, to be fed to the write head of the mass storage device. Of course, the plurality of parallel streams will be generated by a control circuit comprising a plurality of flip-flops and XOR and AND gates, also functionally arranged in a tree structure. 
     Other variations may be introduced by skilled artisans in the above described embodiments though remaining within the scope of the present invention.