Abstract:
Provided is a voltage regulator configured to suppress overshoot and undershoot so as to output a stabilized voltage. The voltage regulator includes: a high pass filter configured to detect a fluctuation in power supply voltage; a high pass filter configured to detect a fluctuation in output voltage; transistors connected in series, which are each configured to cause a current to flow in accordance with an output of corresponding one of the high pass filters; and a clamp circuit configured to clamp a drain voltage of one of the transistors connected in series. The voltage regulator controls a gate voltage of an output transistor based on a drain voltage of a transistor that includes a gate controlled by the drain voltage of the one of the transistors connected in series.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2013-258394 filed on Dec. 13, 2013, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a voltage regulator capable of stabilizing an output voltage even when a power supply fluctuates. 
         [0004]    2. Description of the Related Art 
         [0005]    A related-art voltage regulator is now described.  FIG. 9  is a circuit diagram illustrating the related-art voltage regulator. 
         [0006]    The related-art voltage regulator includes an error amplifier circuit  103 , a reference voltage circuit  102 , PMOS transistors  901  and  902 , an output transistor  105 , resistors  106 ,  107 , and  903 , a fluctuation detection capacitor  904 , a clamp circuit  905 , a ground terminal  100 , an output terminal  104 , and a power supply terminal  101 . 
         [0007]    The resistors  106  and  107  are connected in series between the output terminal  104  and the ground terminal  100 , and divide an output voltage Vout generated at the output terminal  104 . A voltage generated at a connection point of the resistors  106  and  107  is represented by Vfb. The error amplifier circuit  103  controls a gate voltage of the output transistor  105  so that the voltage Vfb may approach a voltage Vref of the reference voltage circuit  102 , to thereby control the output transistor  105  to output an output voltage Vout from the output terminal  104 . When a power supply voltage VDD of the power supply terminal  101  increases, a current Ix1 is allowed to flow from the power supply terminal  101  to the fluctuation detection capacitor  904 . The current Ix1 is amplified by a current feedback circuit including the PMOS transistors  901  and  902  and the resistor  903 , to thereby generate a current Ix2. The current Ix2 is supplied to a gate of the output transistor  105  to charge a gate capacitance of the output transistor  105 . In this manner, a gate-source voltage VGS of the output transistor  105  is adjusted to an appropriate value even when the power supply voltage VDD corresponding to a source voltage of the output transistor  105  fluctuates, and hence overshoot is suppressed to stabilize the output voltage Vout (see, for example, Japanese Patent Application Laid-open No. 2007-157071). 
         [0008]    However, the related-art voltage regulator has a problem in that, when the power supply voltage continues to fluctuate even after the fluctuation in power supply voltage is detected to suppresses the overshoot of the output voltage, the voltage regulator continues to control the output transistor excessively to generate undershoot or another overshoot. Further, the related-art voltage regulator has another problem in that, when the power supply voltage fluctuates quickly under a heavy load and undershoot is generated after the overshoot of the output voltage is suppressed, the voltage regulator erroneously detects an operation of subsequently increasing the output voltage to control the output transistor, resulting in oscillation. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention has been made in view of the above-mentioned problems, and provides a voltage regulator capable of stabilizing an output voltage even when a power supply voltage continues to fluctuate even after overshoot of the output voltage is suppressed or when overshoot or undershoot is generated due to a power supply fluctuation under a heavy load. 
         [0010]    In order to solve the related-art problem, a voltage regulator according to one embodiment of the present invention has the following configuration. 
         [0011]    The voltage regulator includes: a high pass filter configured to detect a fluctuation in power supply voltage; a high pass filter configured to detect a fluctuation in output voltage; transistors connected in series, which are each configured to cause a current to flow in accordance with an output of corresponding one of the high pass filters; and a clamp circuit configured to clamp a drain voltage of one of the transistors connected in series. The voltage regulator controls a gate voltage of an output transistor based on a drain voltage of a transistor that includes a gate controlled by the drain voltage of the one of the transistors connected in series. 
         [0012]    According to the voltage regulator of one embodiment of the present invention, the overshoot of the output voltage can be suppressed and undershoot that is generated thereafter can be prevented, thereby being capable of stabilizing the output voltage quickly. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a circuit diagram illustrating a voltage regulator according to a first embodiment of the present invention. 
           [0014]      FIG. 2  is a circuit diagram illustrating an exemplary high pass filter. 
           [0015]      FIG. 3  is a circuit diagram illustrating another exemplary high pass filter. 
           [0016]      FIG. 4  is a circuit diagram illustrating still another exemplary high pass filter. 
           [0017]      FIG. 5  is a waveform diagram showing an operation of the voltage regulator according to the first embodiment. 
           [0018]      FIG. 6  is a waveform diagram showing another operation of the voltage regulator according to the first embodiment. 
           [0019]      FIG. 7  is a circuit diagram illustrating a configuration of a voltage regulator according to a second embodiment of the present invention. 
           [0020]      FIG. 8  is a circuit diagram illustrating a configuration of a voltage regulator according to a third embodiment of the present invention. 
           [0021]      FIG. 9  is a circuit diagram illustrating a configuration of a related-art voltage regulator. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0022]    In the following, embodiments of the present invention are described with reference to the drawings. 
       First Embodiment 
       [0023]      FIG. 1  is a circuit diagram of a voltage regulator according to a first embodiment of the present invention. 
         [0024]    The voltage regulator according to the first embodiment includes an error amplifier circuit  103 , a reference voltage circuit  102 , an output transistor  105 , resistors  106  and  107 , high pass filters  111  and  112 , NMOS transistors  113  and  114 , a PMOS transistor  115 , a bias circuit  121 , a ground terminal  100 , an output terminal  104 , and a power supply terminal  101 . 
         [0025]      FIG. 2  is a circuit diagram of the high pass filters  111  and  112 . The high pass filters  111  and  112  each include a capacitor  201 , a resistor  202 , a constant voltage circuit  203 , an input terminal  211 , and an output terminal  212 . 
         [0026]    Next, connections in the voltage regulator according to the first embodiment are described. 
         [0027]    The error amplifier circuit  103  has an inverting input terminal connected to a positive electrode of the reference voltage circuit  102  and a non-inverting input terminal connected to a connection point of one terminal of the resistor  106  and one terminal of the resistor  107 . The reference voltage circuit  102  has a negative electrode connected to the ground terminal  100 . The other terminal of the resistor  107  is connected to the ground terminal  100 , and the other terminal of the resistor  106  is connected to the output terminal  104 . The output transistor  105  has a gate connected to an output terminal of the error amplifier circuit  103 , a source connected to the power supply terminal  101 , and a drain connected to the output terminal  104 . The PMOS transistor  115  has a drain connected to the output terminal of the error amplifier circuit  103 , a source connected to the power supply terminal  101 , and a gate connected to a drain of the NMOS transistor  113  via a node  133 . The bias circuit  121  has one terminal connected to the drain of the NMOS transistor  113  and the other terminal connected to the power supply terminal  101 . The NMOS transistor  113  has a source connected to a drain of the NMOS transistor  114  and a gate connected to the output terminal  212  of the high pass filter  111  via the node  132 . The NMOS transistor  114  has a source connected to the ground terminal  100  and a gate connected to the output terminal  212  of the high pass filter  112  via a node  131 . The input terminal  211  of the high pass filter  111  is connected to the power supply terminal  101 , and the input terminal  211  of the high pass filter  112  is connected to the output terminal  104 . The capacitor  201  has one terminal connected to the input terminal  211  and the other terminal connected to the output terminal  212 . The resistor  202  has one terminal connected to the output terminal  212  and the other terminal connected to a positive electrode of the constant voltage circuit  203 . The constant voltage circuit  203  has a negative electrode connected to the ground terminal  100 . 
         [0028]    Next, an operation of the voltage regulator according to the first embodiment is described. 
         [0029]    When a power supply voltage VDD is input to the power supply terminal  101 , the voltage regulator outputs an output voltage Vout from the output terminal  104 . The resistors  106  and  107  divide the output voltage Vout and output a divided voltage Vfb. The error amplifier circuit  103  compares a reference voltage Vref of the reference voltage circuit  102  and the divided voltage Vfb, and controls a gate voltage of the output transistor  105  so that the output voltage Vout is constant. The bias circuit  121  operates as a clamp circuit, and clamps the gate voltage of the PMOS transistor  115  at the power supply voltage VDD to turn off the PMOS transistor  115 . 
         [0030]    When the output voltage Vout is higher than a predetermined voltage, the divided voltage Vfb is higher than the reference voltage Vref. Hence, an output signal of the error amplifier circuit  103  (the gate voltage of the output transistor  105 ) is increased, and the output transistor  105  is turned off to reduce the output voltage Vout. In addition, when the output voltage Vout is lower than the predetermined voltage, operations opposite to the above-mentioned operations are performed to increase the output voltage Vout. In this way, the voltage regulator operates so that the output voltage Vout is constant. 
         [0031]    Now, the case where the power supply voltage VDD fluctuates is considered.  FIG. 5  shows waveforms representing the fluctuations in voltages of the respective nodes when the power supply voltage VDD increases. When the power supply voltage VDD increases, the high pass filter  111  detects the fluctuation in power supply voltage VDD to increase the voltage of the node  132 . Along with the increase in power supply voltage VDD, the output voltage Vout also increases, and then the high pass filter  112  detects the fluctuation in output voltage Vout to increase the voltage of the node  131 . In this manner, a current I0 flows through the NMOS transistors  113  and  114 . The bias circuit  121  causes a current I1 to flow. When the voltages of the nodes  131  and  132  are further increased so that the current I0 becomes larger than the current I1, the bias circuit  121  decreases the voltage of the node  133 . Then, the PMOS transistor  115  is turned on to increase the gate voltage of the output transistor  105 , thereby controlling the operation of the output transistor  105  to be turned off to suppress overshoot of the output voltage Vout. After the overshoot of the output voltage Vout is suppressed, the power supply voltage VDD continues to increase, but the high pass filter  112  does not detect the fluctuation in output voltage Vout, and hence the voltage of the node  131  does not increase and the NMOS transistor  114  is turned off. Then, the current I0 does not flow, and the PMOS transistor  115  does not operate, and hence the output transistor  105  is not controlled. In this manner, after the control of the overshoot of the output voltage Vout, even when the power supply voltage VDD continues to increase, the output voltage Vout can be maintained to be constant. 
         [0032]      FIG. 6  shows waveforms representing the fluctuations in voltages of the respective nodes when the power supply voltage VDD quickly increases under the state in which a heavy load is connected to the output terminal  104 . When the power supply voltage VDD increases, the high pass filter  111  detects the fluctuation in power supply voltage VDD to increase the voltage of the node  132 . Along with the increase in power supply voltage VDD, the output voltage Vout also increases, and then the high pass filter  112  detects the fluctuation in output voltage Vout to increase the voltage of the node  131 . In this manner, the current I0 flows through the NMOS transistors  113  and  114 . The bias circuit  121  causes the current I1 to flow. When the voltages of the nodes  131  and  132  are further increased so that the current I0 becomes larger than the current I1, the bias circuit  121  decreases the voltage of the node  133 . Then, the PMOS transistor  115  is turned on to increase the gate voltage of the output transistor  105 , thereby controlling the operation of the output transistor  105  to be turned off to suppress overshoot of the output voltage Vout. Because the heavy load is connected to the output terminal  104 , the output voltage Vout abruptly decreases when the output transistor  105  is turned off. Then, the error amplifier circuit  103  controls the output transistor  105  to abruptly increase the output voltage Vout. In response to the increase in output voltage Vout, the high pass filter  112  increases the voltage of the node  131 . However, because the power supply voltage VDD is not increased, the high pass filter  111  does not increase the voltage of the node  132  but turns off the NMOS transistor  113 . Thus, the current I0 does not flow, and the PMOS transistor  115  does not control the output transistor  105 . In this manner, after the control of the overshoot of the output voltage Vout under the state in which the heavy load is connected, even when undershoot is generated due to the heavy load and the error amplifier circuit  103  controls the output voltage Vout so as to be increased, the PMOS transistor  115  does not control the output transistor, and the output voltage Vout can be maintained to be constant. 
         [0033]    Note that, the configuration of the high pass filters is described with reference to  FIG. 2 , but the present invention is not limited to this configuration. A high pass filter having another configuration of  FIG. 3  or  FIG. 4  may be used. With the configuration of  FIG. 3 , when a current I2 of a bias circuit  303  is caused to flow through an NMOS transistor  302 , a voltage can be biased in advance to an output  212  of the high pass filter. Consequently, even when the fluctuation in power supply voltage VDD or in output voltage Vout is small, a current to be caused to flow through the NMOS transistors  113  and  114  can be easily increased, thus increasing the effect of suppressing the overshoot. 
         [0034]    When the configuration of  FIG. 4  is used, which is a source follower configuration in which a current I3 of a bias circuit  403  is caused to flow through an NMOS transistor  402 , a voltage can be biased in advance to the output  212  of the high pass filter based on an output voltage of the source follower. Consequently, even when the fluctuation in power supply voltage VDD or in output voltage Vout is small, a current to be caused to flow through the NMOS transistors  113  and  114  can be easily increased, thus increasing the effect of suppressing the overshoot. 
         [0035]    Further, in the above description, the drain of the NMOS transistor  114  is connected to the source of the NMOS transistor  113 , but the present invention is not limited to this configuration. The arrangement of the NMOS transistors  113  and  114  may be reversed so that the drain of the NMOS transistor  113  may be connected to the source of the NMOS transistor  114 . 
         [0036]    As described above, the voltage regulator according to the first embodiment can stabilize the output voltage even when the power supply voltage continues to fluctuate after the overshoot of the output voltage is suppressed. Further, the voltage regulator according to the first embodiment can stabilize the output voltage even when undershoot is generated after the power supply voltage fluctuates under the state in which a heavy load is connected and the overshoot of the output voltage is suppressed. 
       Second Embodiment 
       [0037]      FIG. 7  is a circuit diagram of a voltage regulator according to a second embodiment of the present invention.  FIG. 7  differs from  FIG. 1  in that the bias circuit  121  is changed to a resistor  701 . The rest is the same as in  FIG. 1 . 
         [0038]    Next, an operation of the voltage regulator according to the second embodiment is described. The operation of maintaining the output voltage Vout to be constant is the same as in the first embodiment. Now, the case where the power supply voltage VDD fluctuates is considered. The operational waveforms are the same as those in the first embodiment.  FIG. 5  shows the fluctuations in voltages of the respective nodes when the power supply voltage VDD increases. When the power supply voltage VDD increases, the high pass filter  111  detects the fluctuation in power supply voltage VDD to increase the voltage of the node  132 . Along with the increase in power supply voltage VDD, the output voltage Vout also increases, and then the high pass filter  112  detects the fluctuation in output voltage Vout to increase the voltage of the node  131 . In this manner, the current I0 flows through the NMOS transistors  113  and  114 . When the current I0 flows through the resistor  701 , the voltage of the node  133  is decreased. Then, the PMOS transistor  115  is turned on to increase the gate voltage of the output transistor  105 , thereby controlling the operation of the output transistor  105  to be turned off to suppress overshoot of the output voltage Vout. After the overshoot of the output voltage Vout is suppressed, the power supply voltage VDD continues to increase, but the high pass filter  112  does not detect the fluctuation in output voltage Vout, and hence the voltage of the node  131  does not increase and the NMOS transistor  114  is turned off. Then, the current I0 does not flow, and the PMOS transistor  115  does not operate, and hence the output transistor  105  is not controlled. In this manner, after the control of the overshoot of the output voltage Vout, even when the power supply voltage VDD continues to increase, the output voltage Vout can be maintained to be constant. 
         [0039]      FIG. 6  shows waveforms representing the fluctuations in voltages of the respective nodes when the power supply voltage VDD quickly increases under the state in which a heavy load is connected to the output terminal  104 . When the power supply voltage VDD increases, the high pass filter  111  detects the fluctuation in power supply voltage VDD to increase the voltage of the node  132 . Along with the increase in power supply voltage VDD, the output voltage Vout also increases, and then the high pass filter  112  detects the fluctuation in output voltage Vout to increase the voltage of the node  131 . In this manner, the current I0 flows through the NMOS transistors  113  and  114 . When the current I0 flows through the resistor  701 , the voltage of the node  133  is decreased. Then, the PMOS transistor  115  is turned on to increase the gate voltage of the output transistor  105 , thereby controlling the operation of the output transistor  105  to be turned off to suppress overshoot of the output voltage Vout. Because the heavy load is connected to the output terminal  104 , the output voltage Vout abruptly decreases when the output transistor  105  is turned off. Then, the error amplifier circuit  103  controls the output transistor  105  to abruptly increase the output voltage Vout. In response to the increase in output voltage Vout, the high pass filter  112  increases the voltage of the node  131 . However, because the power supply voltage VDD is not increased, the high pass filter  111  does not increase the voltage of the node  132  but turns off the NMOS transistor  113 . Thus, the current I0 does not flow, and the PMOS transistor  115  does not control the output transistor  105 . In this manner, after the control of the overshoot of the output voltage Vout under the state in which the heavy load is connected, even when undershoot is generated due to the heavy load and the error amplifier circuit  103  controls the output voltage Vout so as to be increased, the PMOS transistor  115  does not control the output transistor, and the output voltage Vout can be maintained to be constant. 
         [0040]    Note that, the configuration of the high pass filters is described with reference to  FIG. 2 , but the present invention is not limited to this configuration. A high pass filter having another configuration of  FIG. 3  or  FIG. 4  may be used. 
         [0041]    Further, in the above description, the drain of the NMOS transistor  114  is connected to the source of the NMOS transistor  113 , but the present invention is not limited to this configuration. The arrangement of the NMOS transistors  113  and  114  may be reversed so that the drain of the NMOS transistor  113  may be connected to the source of the NMOS transistor  114 . 
         [0042]    As described above, the voltage regulator according to the second embodiment can stabilize the output voltage even when the power supply voltage continues to fluctuate after the overshoot of the output voltage is suppressed. Further, the voltage regulator according to the second embodiment can stabilize the output voltage even when undershoot is generated after the power supply voltage fluctuates under the state in which a heavy load is connected and the overshoot of the output voltage is suppressed. 
       Third Embodiment 
       [0043]      FIG. 8  is a circuit diagram of a voltage regulator according to a third embodiment of the present invention.  FIG. 8  differs from  FIG. 1  in that the bias circuit  121  is changed to a diode-connected PMOS transistor  801 . The rest is the same as in  FIG. 1 . 
         [0044]    Next, an operation of the voltage regulator according to the third embodiment is described. The operation of maintaining the output voltage Vout to be constant is the same as in the first embodiment. Now, the case where the power supply voltage VDD fluctuates is considered. The operational waveforms are the same as those in the first embodiment.  FIG. 5  shows the fluctuations in voltages of the respective nodes when the power supply voltage VDD increases. When the power supply voltage VDD increases, the high pass filter  111  detects the fluctuation in power supply voltage VDD to increase the voltage of the node  132 . Along with the increase in power supply voltage VDD, the output voltage Vout also increases, and then the high pass filter  112  detects the fluctuation in output voltage Vout to increase the voltage of the node  131 . In this manner, the current I0 flows through the NMOS transistors  113  and  114 . When the current I0 flows through the diode-connected PMOS transistor  801 , the voltage of the node  133  is decreased. Then, the PMOS transistor  115  is turned on to increase the gate voltage of the output transistor  105 , thereby controlling the operation of the output transistor  105  to be turned off to suppress overshoot of the output voltage Vout. After the overshoot of the output voltage Vout is suppressed, the power supply voltage VDD continues to increase, but the high pass filter  112  does not detect the fluctuation in output voltage Vout, and hence the voltage of the node  131  does not increase and the NMOS transistor  114  is turned off. Then, the current I0 does not flow, and the PMOS transistor  115  does not operate, and hence the output transistor  105  is not controlled. In this manner, after the control of the overshoot of the output voltage Vout, even when the power supply voltage VDD continues to increase, the output voltage Vout can be maintained to be constant. 
         [0045]      FIG. 6  shows waveforms representing the fluctuations in voltages of the respective nodes when the power supply voltage VDD quickly increases under the state in which a heavy load is connected to the output terminal  104 . When the power supply voltage VDD increases, the high pass filter  111  detects the fluctuation in power supply voltage VDD to increase the voltage of the node  132 . Along with the increase in power supply voltage VDD, the output voltage Vout also increases, and then the high pass filter  112  detects the fluctuation in output voltage Vout to increase the voltage of the node  131 . In this manner, the current I0 flows through the NMOS transistors  113  and  114 . When the current I0 flows through the diode-connected PMOS transistor  801 , the voltage of the node  133  is decreased. Then, the PMOS transistor  115  is turned on to increase the gate voltage of the output transistor  105 , thereby controlling the operation of the output transistor  105  to be turned off to suppress overshoot of the output voltage Vout. Because the heavy load is connected to the output terminal  104 , the output voltage Vout abruptly decreases when the output transistor  105  is turned off. Then, the error amplifier circuit  103  controls the output transistor  105  to abruptly increase the output voltage Vout. In response to the increase in output voltage Vout, the high pass filter  112  increases the voltage of the node  131 . However, because the power supply voltage VDD is not increased, the high pass filter  111  does not increase the voltage of the node  132  but turns off the NMOS transistor  113 . Thus, the current I0 does not flow, and the PMOS transistor  115  does not control the output transistor  105 . In this manner, after the control of the overshoot of the output voltage Vout under the state in which the heavy load is connected, even when undershoot is generated due to the heavy load and the error amplifier circuit  103  controls the output voltage Vout so as to be increased, the PMOS transistor  115  does not control the output transistor, and the output voltage Vout can be maintained to be constant. 
         [0046]    Note that, the configuration of the high pass filters is described with reference to  FIG. 2 , but the present invention is not limited to this configuration. A high pass filter having another configuration of  FIG. 3  or  FIG. 4  may be used. 
         [0047]    Further, in the above description, the drain of the NMOS transistor  114  is connected to the source of the NMOS transistor  113 , but the present invention is not limited to this configuration. The arrangement of the NMOS transistors  113  and  114  may be reversed so that the drain of the NMOS transistor  113  may be connected to the source of the NMOS transistor  114 . 
         [0048]    As described above, the voltage regulator according to the third embodiment can stabilize the output voltage even when the power supply voltage continues to fluctuate after the overshoot of the output voltage is suppressed. Further, the voltage regulator according to the third embodiment can stabilize the output voltage even when undershoot is generated after the power supply voltage fluctuates under the state in which a heavy load is connected and the overshoot of the output voltage is suppressed.