Abstract:
In a circuit for selectively communicating data into and out of a signal path, typically used for diagnosing a data processing unit, a shadow register is used for receiving data from and transferring data to an external source. The shadow register is physically insulated from the signal path by a first state register and a second state register, the first state register transferring data from the signal path to the shadow register, the second state register transferring data between the shadow register and the signal path. Path switching is achieved by a selector connected to the respective outputs of the first and second state registers and responsive to a control signal for releasing output signals from only one of these registers.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to a circuit for communicating data into and out of a signal path in a digital system. Since one particular use of this circuit is for diagnosing faults in digital systems, and more particularly, for diagnosing faults using the serial scan techniques, therefore, this invention also relates to a diagnostic circuit. 
     BACKGROUND OF THE INVENTION 
     A common technique of diagnosing a digital system is by introducing known data patterns into the system and sampling for expected modifications, by the system, of the data patterns at desired nodes. This technique is usually effective in diagnosing a combinational circuit since it involves no memory of preceding states. However, the technique is not as effective in diagnosing a sequential circuit because data at each node is usually dependent upon both the system&#39;s current state and its input, so that if a circuit failure causes unexpected state transitions, the sampled result may be so contaminated by having travelled through a wrong system path that analysis of the sampled result most frequently becomes impossible. 
     In U.S. Pat. No. 4,476,560, which has the same assignee as the present invention, there is disclosed a technique for solving the above identified diagnostic difficulty of a sequential circuit. By providing a circuit that breaks a signal path, with the capability to introduce and remove data signals into and from the signal path, a sequential circuit can then be diagnosed as a plurality of combinatorial circuits. 
     The block diagram of a prior art part &#39;818 diagnostic register circuit is given in FIG. 1. The circuit has a shadow register interfacing with an external device. The shadow register is insulated from the signal path by an output register. This insulation is provided to prevent possible damages to the system which may occur when the diagnostic data is being input into the shadow register. The insulation also prevents the shadow register from interfering with the normal operation of the system during the introduction of diagnostic data into the shadow register. 
     In prior art diagnostic register circuits, signal path switching is performed by a multiplexer connected to the input of the output register. The multiplexer performs signal path switching by selectively switching the input of the output register. A major problem associated with the prior art configurations has been the delay of signal propagation caused by the multiplexer logic. Therefore, there is a need for a circuit whereby the multiplexer can be eliminated. It is also desirable to have a circuit whereby operational and functional compatibility with the &#39;818 part device can be preserved. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention comprises a circuit for selectively communicating data into and out of a signal path. The circuit comprises: first data storage means having input means coupled to said signal path which is responsive to a control signal for storing signals from said signal path; second data storage means having first input means and second input means, and responsive to a control signal for selectively storing signals from said first input means and second input means; and selector means coupled to said first data storage means and said second data storage means, and responsive to a control signal for selectively releasing signals from said first data storage means and second storage means; said first input means of said second storage means being coupled to receive signals released from said selector means, said second input means of said second storage means being coupled to received data from an external source, said data storage means having means for outputting stored signals to an external device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the prior art &#39;818 diagnostic register. 
     FIG. 2 is a block diagram of the circuit according to the present invention. 
     FIG. 3 is a schematic diagram of a preferred implementation of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 is a block diagram illustrating the signal introduction and removal circuit according to the present invention. In the circuit is a register 201 connected to receive signals of signal path at 205. When enabled by control signal 2, signals received by register 201 will be stored and appear at its output. 
     Register block 202 provides an interface to an external device (not shown). According to a preferred implementation of this invention, register block 202 has a shift/storage register which includes parallel input/output means and serial input/output means. The serial input is used for receiving signals from the external source. The received signals from the external source will be output to the signal path via its parallel output. The parallel input is used for receiving signals from the signal path at point 203. The received signals will be output to the external source via its serial output. 
     The parallel output of register 201 and the parallel output of register block 202 are connected to respective inputs of a selector 204 whereby the output of one of these registers will be released as the output of selector 204. The output of selector 204 is connected to the signal path at point 203, which in turn is connected to the parallel input of register block 202. 
     In normal operation, signals from the signal path enter register 201 at 205, and reenter the signal path at point 203 by way of the selector 204. To introduce external signals into the signal path, the external signals are first shifted into the shift register of register block 202. The signals will then enter the signal path by way of the parallel output of register block 202 and the selector 204. To sample the signal path, signals from the signal path are loaded into register 201, received by the parallel input of the shift register of register block 202 by way of the selector 204, and then shifted out of register block 202 to the external source. 
     Referring to FIG. 3, there is shown a preferred embodiment of the present invention implemented to operate with functional and operational compatibility as the &#39;818 part device. 
     State/output register 301 is a parallel input/output register connected to receive signals from the signal path at point 302. The signals will be stored and appear at the parallel output of register 301 with the activation of a clock (CLK) signal. 
     The shadow register 303, according to the preferred embodiment of this invention, is a shift register having parallel input/output and serial input/output. The serial input of the shadow register 303 is used for receiving diagnostic data from an external source (not shown). The parallel output of the shadow register 303 is used for introducing diagnostic data into the signal path. The shadow register 303 receives signals from signal path through its parallel input. The received signals will be transferred to an external source (not shown) through the serial output of shadow register 303. 
     To maintain compatibility with the &#39;818 part device, the parallel output of the shadow register 303 is first received and stored in state/output register 304. The output of register 304 is connected to a set of tri-state buffers 307 whereby the output of register 304 will be released or blocked in response to control signal 308. The released signals enter the signal path at point 315. 
     Similarly, the output of register 301 is connected to another set of tri-state buffers 305 which, responsive to a control signal 306, releases or blocks the output of register 301 to the signal path at point 315. 
     Control signal 306 to tri-state buffers 305 comes from the output of AND gate 309. Control signal 308 of tri-state buffers 307 comes from the outpt of AND gate 310. Each of AND gates 309 and 310 has one input terminal connected to receive an enable signal E. A second input of AND gate 309 is connected to one output of flip-flop 311. A second input of AND gate 310 is connected to the complementary output of flip-flop 311. In this way when one set of the tri-state buffers is enabled to release signals to the signal path, the other set of tri-state buffers would have high impedance, blocking the corresponding signals to the signal path. 
     Input to flip-flop 311 is an externally generated control mode signal (MODE). This MODE signal is clocked into the flip flop 311 by the same CLK signal used to enable the loading of register 301 and register 304. 
     Point 315 of the signal path, which is connected to the output of both tri-state buffers 305 and 307, is connected to the parallel input of shadow register 303. With the application of proper control signals, signals at point 315 will be received and stored in the shadow register 303. Signals stored in the shadow register 303 are shifted out through its serial output to an external source. 
     The operation of the circuit is now described. When clock signal (CLK) is active, output from shadow register 303 is loaded into state/output register 304, signals from the signal path 302 are loaded into state/output register 301, and control mode signal (MODE) is loaded into flip flop 311. 
     When the mode control signal (MODE) is &#34;low&#34;, AND gate 309 will be enabled. Subject to the level of enable signal E, the content of register 301 will be released by tri-state buffers 305 into the signal path at point 315. On the other hand, AND gate 310 will be disabled, and thus regardless of the level of enable signal, E, the signal path will be insulated from the output of register 304. 
     When the control mode signal (MODE) is &#34;low&#34;, input to the serial input of the shadow register 303 will be clocked into the shadow register 303 by the diagnostic clock (DCLK). The above described operations are summarized in the first three rows of table 1. 
     When a &#34;high&#34; control mode (MODE) signal is clocked into flip-flop 311, AND gate 309 will be disabled regardless of the enabled signal E. Thus tri-state buffers 305 will have high impedance and insulating the signal path from the output of register 301. On the other hand, a &#34;high&#34; control mode signal (MODE) will enable AND gate 310 and, when enable signal E is active, tri-state buffers 307 will release the output of register 304 into point 315 of the signal path. 
     When the control mode (MODE) is &#34;high&#34; and the serial data input (SDI) is &#34;low&#34;, signals at the parallel input of shadow register 303 will be clocked by the diagnostic clock (DCLK) into shadow register 303. 
     If the control mode signal (MODE) is &#34;high&#34; and the serial data input signal (SDI) is &#34;low&#34;, and if both the clock signal and the diagnostic clock signal (DCLK) are both active, the output of register 304 will be transferred to point 315 which, in turn, will be loaded into shadow register 303. On the other hand, the output of the shadow register 303 will be loaded into register 304. Effectively, contents of shadow register 303 and register 304 will be swapped. 
     If the control mode signal (MODE) is &#34;high&#34; and the serial data input signal (SDI) is &#34;low&#34;, and if only the diagnostic clock (DCLK) is active, then only the shadow register will be loaded with signals from the signal path. 
     When both the control mode signal (MODE) and the serial data input signal (SDI) are &#34;high&#34;, output of AND gate 312, which is connected to the input of flip flop 313, will be &#34;high&#34;. With the diagnostic clock signal (DCLK) active, the output of AND gate 313 will be loaded into flip flop 312. 
     A &#34;high&#34; signal on the output of flip-flop 313 will cause the tri-state buffers 314 to connect the output of shadow register 303 to the signal path at point 302. As a result, a path is provided from the parallel output of the shadow register 303 to point 302. This path is most frequently used for writeable control store loading. 
     In the above described preferred implementation, two state registers, 301 and 304, are used to replace the output register of the &#39;818 part device. Instead of selecting signal input to the output register as in the &#39;818 part device, the above described implementation uses a state register to hold signals from each signal path, and then control the path selection by enabling the output of the desired state register. In this way, the state register in the parallel data path will have a set up time that is dependent only upon the register itself, and not on the propagation delay of the intervening multiplexer logic. 
     While the invention has been particularly shown and described with reference to the referred embodiment, it would be understood by those skilled in the art that changes in form in details could be made therein without departing from the spirit of the invention. 
     
                                           TABLE 1__________________________________________________________________________  INPUTS    OUTPUTSMODE   SDI     CLK        DCLK            B7-B0                 S7-S0 SDO                          OPERATION__________________________________________________________________________                          Load output register1 L    X     *   Bn → Dn                 HOLD  S7 from input bus                 Sn → Sn-1                          Shift shadow2 L    X  *      HOLD S0 → SD1                       S7 register data                          Load output register                          from input bus while                 Sn → Sn-1                       S7 shifting shadow3 L    X         Bn → Dn                 S0 → SD1                          register data                          Load output register4 H    X     *   Bn → Sn                 HOLD  SDI                          from shadow register                          Load shadow register5 H    L  *      HOLD Sn → Bn                       SDI                          from output bus                          Swap shadow register6 H    L         Bn → Sn                 Sn → Bn                       SDI                          and output register                          Enable D7-D0 outputs                          for writeable control7 H    H  *      HOLD HOLD  SDI                          store loading__________________________________________________________________________ *Clock must be steady or falling   low to high transition