Abstract:
A multidimensional equalizer and cross talk canceller for a communication network that simultaneously removes far end cross talk NEXT) and intersymbol interference (ISI) from a received signal. A multidimensional-pair channel is treated as a single multidimensional channel and a receiver in the communication network equalizes received signals through the use of the multidimensional equalizer. A decision feedback equalizer determines a multidimensional steepest descent gradient to adjust matrix coefficients.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to noise reduction in communication networks. More specifically, this invention relates to simultaneously removing far-end cross talk and inter-symbol interference from signals transmitted over an N-dimensional communication network. 
     2. Description of the Related Art 
     Insatiable demand for bandwidth in LAN applications has motivated the evolution of high-speed 1000BASE-T Ethernet from its predecessors, such as Fast Ethernet 100BASE-T and 10BASE-T. 
     In order to achieve the high throughput of Gigabit Ethernet, impairments such as cable attenuation, echo, near-end cross talk (NEXT), and far-end cross talk (FEXT) over the cable channel(s) must be reduced as much as possible. Another source of errors in baseband communication systems is intersymbol interference (ISI) arising from the dispersive nature of the communications channel, i.e. pulse distortion arising from the non-ideal filtering characteristics of the transmission channel leading to interference between symbols. 
     Attenuation, echo, and NEXT can be controlled through the use of a linear equalizer, a decision feedback equalizer (DFE), echo cancelers, and NEXT cancelers. However, none of these conventional components removes FEXT noise. 
     It is nonetheless desirable to reduce errors introduced in transmitted signals from ISI and FEXT. Although the magnitude of FEXT noise is usually much smaller than NEXT interference, any reduction of FEXT can only improve the performance of a Gigabit Ethernet Transceiver, as well as other communication networks having similar impairments. It is also true that if FEXT and ISI is removed, then the resulting Gigabit Ethernet Transceiver may be usable with cable that is either longer or of inferior quality than specified by industry standards. 
     SUMMARY OF THE INVENTION 
     In one embodiment, a multidimensional equalizer and cross talk canceler for a communication network is provided that simultaneously removes far end cross talk (FEXT) and intersymbol interference (ISI) from a received signal. A multidimensional channel is treated as a single multidimensional channel and a receiver in the communication network equalizes received signals through the use of the multidimensional equalizer. A multidimensional equalizer and cross talk canceler for a communication network that simultaneously removes far end cross talk (FEXT) and intersymbol interference (ISI) from a received signal. A multidimensional-pair channel is treated as a single multidimensional channel and a receiver in the communication network equalizes received signals through the use of the multidimensional equalizer. A decision feedback equalizer determines a multidimensional steepest descent gradient to adjust matrix coefficients that are proportional to estimates of 
           ∂     e   n         ∂     Q   k     i   ,   j           ,       wherein   ⁢           ⁢     Q   k     i   ,   j         ←       (       Q   k     i   ,   j       -     μ   ·     (       ∂     e   n         ∂     Q   k     i   ,   j           )         )     ⁢           ⁢   and           
           ∂     e   n         ∂     Q   k     i   ,   j           =     2   ·     (       Z   n   i     -     X     n   ←   p     i       )     ·       Y     n   -   k     j     .           
 
     The equalizer includes:
         a vector data unit delay operator that passes the received data vector Y n  through a series of unit delay operators to generate successive tap input data Y n , Y n−1 , Y n−2 ;   a first matrix multiplication operator that receives a 1×N matrix Y n−k  from the unit delay operator and multiplies it with the N×1 matrix of scaled vector error data (Z n −X n ) to generate a N×N adjustment matrix;   a matrix summation operator that adds the adjustment matrix to a Q n−k  tap matrix and outputs a corrected tap matrix Q n−k+1 ;   matrix tap unit delay operator that receives the corrected tap matrix Q n−k+1 , and introduces a one cycle delay to generate a Q n−k  tap matrix; and   a second matrix multiplication operator that multiplies the Q n−k  tap matrix from the matrix tap unit delay operator by the Y n−k+1  vector from the vector data unit delay operator.       

     The multidimensional equalizer and cross talk canceler of the present invention exhibits significantly better noise margin compared to multiple scalar equalizers and advantageously permits the use longer cable runs or the use of physical channels that are in some way inferior. 
     The foregoing has outlined rather broadly the objects, features, and technical advantages of the present invention so that the detailed description of the invention that follows may be better understood. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a generic communication channel between a transmitter and a receiver. 
         FIG. 1   a  is a diagram of components typically included in a four channel Gigabit Ethernet network. 
         FIG. 2  is a block diagram of a receiver for signals in an Ethernet network. 
         FIG. 2   a  is a block diagram of a receiver for signals in an Ethernet network in accordance with the present invention. 
         FIG. 3  is a block diagram of a single tap of a four dimensional equalizer and far end cross talk canceller in accordance with the present invention. 
         FIG. 4  is a block diagram of a single tap of a one dimensional equalizer known in the prior art. 
         FIG. 5   a  is a graph of the signal to noise ratio versus convergence time in a four dimensional equalizer in accordance with the present invention. 
         FIG. 5   b  is a graph of the signal pattern versus convergence time in a four dimensional equalizer in accordance with the present invention. 
         FIG. 6   a  is a graph of the signal to noise ratio versus convergence time in a conventional one dimensional equalizer known in the prior art. 
         FIG. 6   b  is a graph of the signal pattern versus convergence time in a four dimensional equalizer known in the prior art. 
     
    
    
     The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items. 
     DETAILED DESCRIPTION 
       FIG. 1  shows a generic model of a baseband transmission system  10 . An incoming binary sequence {b k } of symbols 0 and 1, each of duration T b  is transformed by the pulse amplitude modulator  12  into a sequence of short pulses {a k } of amplitudes +1 and −1. These short pulses are applied to a transmit filter  14  of impulse response g(t) producing the transmitted signal X(t). Note that in 1000BASE-T over a copper channel, the signals on each wire pair are not just 0 or 1, but rather, five different voltage levels (0, ±1 and ±2) are applied. 
     The signal X(t) is modified by transmission through a channel  16  of impulse response h(t) and also has some noise n(t) added to it, producing noisy signal Y(t). At receiver  18 , the noisy signal Y(t) is passed through a receiver equalizer  20  and the resulting filtered output Z(t) is synchronously sampled at intervals of T b . The samples, Z(T), are passed to a threshold decision device  22 , which outputs a 1 if the sample is greater than the threshold 1, and 0 if less than the threshold. 
     Referring now to  FIG. 1   a , an Ethernet network  100  capable of full-duplex 4-channel communication over a copper medium includes four twisted pair cables  102 ,  104 ,  106 ,  108 . One (1) gigabit per second (Gb/s) throughput is achieved using eight transceivers (four at each end)  110  through  124  as shown in  FIG. 1   a . Each transceiver  110  through  124  achieves throughput of 250 Mb/s, but operates at approximately 290 Mb/s to accommodate coding and signaling overhead. 
     Hybrids in transceivers  110  through  124  separate transmit and receive signals on each wire pair. The transmitters (denoted by “TX” in  FIG. 1 ) in transceivers  110  through  124  perform the relatively simple task of outputting packets of data that include the address of a destination receiver. Data received by the receivers in transceivers  110  through  124  is subject to errors due to cable attenuation, echo from the transmitter, near-end cross talk (NEXT) from one or more adjacent transmitters, and far-end cross talk (FEXT) from transmitters at the other end of the cable. 
     Crosstalk is unwanted signals coupled between adjacent wire pairs. Each two-wire pair is affected by crosstalk from the adjacent three pairs. Crosstalk is characterized in reference to the transmitter. NEXT is crosstalk that appears at the output of a wire pair at the transmitter end of the cable. FEXT is crosstalk that appears at the output of a wire pair at the far end of the cable from the transmitter. For example, the receiver in transceiver  110  may be subject to NEXT from transmitters in tranceivers  112 ,  114 , and  116 , while the receivers in transceivers  110 ,  112 ,  114 , and  116  maybe subject to FEXT from transceivers  118 ,  120 ,  122  and  124 . 
     Referring now to  FIG. 2 , receiver  200  receives data, denoted Y n . When a signal, X n  is applied to a channel, ideally it is transmitted only to the far end of that channel (i.e., travels in only one direction). In practice, part of the signal is reflected back toward the transmitter due to impedance discontinuities within the channel. The amount of signal reflected back is characterized by return loss. The greater the return loss, the less the signal is reflected. Return loss becomes more significant at elevated frequencies. To reduce or eliminate errors in transmission, the reflected signal must be small compared to the desired receive signal at all relevant frequencies. Since the desired receive signal is coming from the far end of the cabling, it has been reduced in size by the attenuation of the cabling. The amount of undesired reflected signal may quickly exceed the desired receive signal as frequency increases. This is unacceptable for error free transmission. 
     The effects of the undesired reflected signal is substantially reduced using known digital return loss cancellation, also referred to as “echo cancellation,” techniques in echo canceller  204 . In the known techniques, echo canceller  204  predicts the amplitude and echo response as a function of time. The digital “taps” of a delay line filter are adjusted accordingly, and the predicted echo response is subtracted from the total incoming receive signal to “cancel” the effect of the echo. More specifically, a portion of the signal transmitted from the transceiver end is subtracted, a portion of the previous bit transmitted from the transceiver end is subtracted, a portion of the bit before, etc. The magnitude of the portion subtracted is stored in digital delay line “taps.” It should be noted that the echo is uncorrelated to the desired signal coming from the other end of the cabling. By slowly adjusting the taps, the echo canceller will track only the echo, thus avoiding cancelling the desired receive signal. 
     NEXT canceller  206  uses techniques similar to echo canceller  204  to cancel noise due to near end cross talk. The correlation between the transmit signal applied to one pair and the receive signal on another pair can be determined in terms of magnitude and time delay. Since each receive pair is corrupted with near-end crosstalk noise from three other pairs, each receiver requires its own NEXT canceller  206 . 
     Attenuation refers to the situation where the amplitude of a signal diminishes as it travels down the length of the cable. High frequency signals (the sharp edges of digital pulses) are attenuated more than low frequency signals and this results in distortion or jitter unless it is compensated. 
     Equal level far-end crosstalk (ELFEXT) is FEXT with the cable attenuation removed to provide equal-level comparisons, i.e., crosstalk and receive signals voltages are compared at the end of the cabling opposite the transmitter. Signal equalization compensates for signal distortion introduced by the communication channel  16  (FIG.  1 ). As noted previously, broadband signals are distorted as they pass along the line, causing inter-symbol-interference (ISI). Receiving signals with large ISI is difficult because the receiver  200  cannot tell the difference between the current symbol and the previous one. 
     To compound the problem, feed-forward equalizer  208  increases ISI as it whitens noise. Unlike feed-forward equalizer  208 , decision-feedback equalizer (DFE)  210  does not modify the noise. Therefore, DFE  210  is used to clean up the ISI generated by the channel  202  and the feed-forward equalizer  208 . Feed forward equalizer  208  typically includes a finite impulse response (FIR) filter. DFE  210  includes a feedback equalization filter and provides better signal equalization than feed forward equalizer  208  alone, especially when the transmission medium introduces strong signal attenuation within specific frequency regions. 
     Referring now to  FIG. 2   a , in one embodiment, the present invention provides a four dimensional DFE (4D-EQLFXC)  212  that efficiently reduces FEXT and ISI by simultaneously equalizing the input signal and cancelling FEXT in the four receivers. 
     Receiver  200  detects the signal Y n  at time n. The 4D-EQLFXC  212  of the present invention reduces the effects of ISI and FEXT among each of the four channels  202  and includes feed forward equalizer  208  and 4D-EQLFXC  212  that operate on the {Y n } sequence to determine an estimate of {Z n } and {X n }. It is assumed that feed forward equalizer  208  can be constructed in the form 
           Z   n     =       ∑     k   =   0     N     ⁢       Q   k     ·     Y     n   -   k             ,       
 
(N: tap length)
 
The higher the number of taps that are used, the more noise reduction is achieved, however, a higher number of taps increases power consumption and expense. Therefore, simulations are used to determine the number of taps required to achieve acceptable noise reduction.
 
     For a four dimensional system, i.e., four channels, X n , Y n , and Z n  are four column (channel) vectors, whose coordinates are referenced with superscripts. That is,
 
X n =&lt;X n   1 , X n   2 , X n   3 , X n   4 &gt;
 
Y n =&lt;Y n   1 , Y n   2 , Y n   3 , Y n   4 &gt;
 
Z n =&lt;Z n   1 , Z n   2 , Z n   3 , Z n   4 &gt;
 
and Q k  in general is a 4×4 symmetric matrix representing one tap matrix of 4D-EQLFXC coefficients. There is one tap matrix for each tap; each tap matrix has size K×K where K is the number of channels. Superscripts are again used to designate individual entries. 
         Q   k     =     [           Q   k   1.1           Q   k   1.2           Q   k   1.3           Q   k   1.4               Q   k   2.1           Q   k   2.2           Q   k   2.3           Q   k   2.4               Q   k   3.1           Q   k   3.2           Q   k   3.3           Q   k   3.4               Q   k   4.1           Q   k   4.2           Q   k   4.3           Q   k   4.4           ]         
 
The error, e n , is defined as the distance between Z n  and X n,  which can be determined as follows: 
         e   n     =                Z   n     -     X     n   -   p              2     =       (       ∑     i   =   1     4     ⁢       (       Z   n   i     -     X     n   -   p     i       )     2       )     .           
 
     Where p is an integer greater than or equal to 0, and e n  is defined as the distance between Z n  and X n−p . Typically, p=(N+1)/2 if N is odd, or is chosen close to this value. Values for n, i, j and k are fixed, with 1=i, j=4, and k=N. Applying the least mean square (LMS) algorithm, an estimate of the gradient ∇ n  with coordinates 
         ∂     e   n         ∂     Q   k     i   ,   j             
 
is determined as follows: 
                 ∂     e   n         ∂     Q   k     i   ,   j           =       ⁢       ∂     ∂     Q   k     i   ,   j           ⁢       ∑     i   =   1     4     ⁢       (       Z   n   i     -     X     n   -   p     i       )     2                     =       ⁢     2   ·       ∑     i   =   1     4     ⁢       (       Z   n   i     -     X     n   -   p     i       )     ·       ∂     Z   n   i         ∂     Q   k     i   ,   j                             =       ⁢     2   ·       ∑     i   =   1     4     ⁢         (       Z   n   i     -     X     n   -   p     i       )     ·     ∂     ∂     Q   k     i   ,   j             ⁢       ∑     k   =   0     N     ⁢       ∑     v   =   1     4     ⁢       Q   k     i   ,   v       ∘     Y     n   -   k     v                             =       ⁢     2   ·     (       Z   n   i     -     X     n   -   p     i       )     ·     Y     n   -   k     j                 
 
Note that coordinates with i=j relate to channel equalization while those with i≠j relate primarily to FEXT cancellation.
 
     The present invention uses the steepest descent method to follow the gradient to an optimal solution. The gradient is a vector (in this case in a space of dimension 16N, where N is the number of taps) that points in the direction of maximum increase in the error function. An example of an adaptive steepest descent method for time instance n+1, is represented by: 
         Q   k     i   ,   j       ←     (       Q   k     i   ,   j       -     μ   ·     (       ∂     e   n         ∂     Q   k     i   ,   j           )         )         
 
in which μ is a constant that regulates the step size.
 
     The 4D-EQLFXC  212  initially assigns values to the matrices {Q k :1≦k≦N}. For example, the values can each be set initially to the zero matrix except for the p th  matrix which is set to the identity matrix. For potentially faster convergence, the values can be preloaded by measuring the characteristics of typical channels, or alternatively, from the preceding training sequence. 
     During each cycle of equalizer training, the matrices are updated by a vector amount that is proportional to the gradient, as estimated using the partial derivative of ε n  and e n  which are determined as shown hereinabove. 
     Note that Z n   i  and Y n−k   j  can be measured directly. During training, the X n   i  terms are known to be either 0 or ±2 and so can be determined with reasonable confidence. As previously noted, the computation involved in estimating these partial derivatives can be reduced by assuming that the Q i  are symmetric. 
     After the training period, the X n   i  terms are no longer known to be either 0 or ±2 but they are still known to be 0, ±1 or ±2, as specified in IEEE Std 802.3ab-1999, in tables 40-1, 40-2 and section 40.3.1.3.6. Assuming that the channel impairments are largely removed, the X n   i  terms can still be determined with reasonable confidence. It can be beneficial to continue making the adjustments, although the adjustments can be made less aggressively, i.e., with a smaller constant μ of proportionality applied to the gradient. 
     The present invention for the 4D-EQLFXC  212  is similar to a one-dimensional least mean square equalizer (1D-EQL), but the present invention provides the additional advantage of canceling FEXT by performing vector operations instead of scalar operations used in a 1D-EQL. Each tap of 4D-EQLFXC coefficients becomes a 4×4 symmetric matrix instead of a scalar. The similarity of the tap operation for the two equalizers is illustrated in  FIGS. 3 and 4 . The difference is that the 4D-EQLFXC in  FIG. 3  uses vector and matrix operations where the 1D-EQL in  FIG. 4  uses scalar operations. 
     Referring now to  FIG. 3 , if all of the taps of the 4D-EQLFXC are considered together, the received data vector Y n  is passed through a series of Unit Delay operators  301  so that successive taps see as input data Y n , Y n−1 , Y n−2 , . . . . Matrix Multiplication operator  303  receives the 1×N matrix Y n−k  matrix from unit delay operators  301  and multiplies it with the N×1 matrix of scaled vector error (gradient) data (Z n −X n ) from Vector Error Scaling operator  302 . Matrix Summation operator  304  receives from Matrix Multiplication operator  303  a N×N matrix of adjustments to the matrix Q n−k . Matrix Summation operator  304  adds the adjustment to the Q n−k  matrix and outputs the corrected matrix, Q n−k , to Matrix Tap Unit Delay operator  305 . Matrix Tap Unit Delay operator  305  introduces a one cycle delay so that Q n−k  arrives at matrix Multiplication operator  306  a cycle later when Y n−k+1  arrives from Vector Data Unit Delay operator  306 . 
     The performance of a simulated 4D-EQLFXC in accordance with the present invention is shown in  FIGS. 5   a  and  5   b , while the performance of a simulated 1D-EQL is shown in  FIGS. 6   a  and  6   b . In  FIGS. 5   a  and  6   a , the results of the simulation shows the 4D-EQLFXC having an overall signal to noise ratio (SNR) advantage of 22 dB compared to the 1D-EQL. Note that the SNR is calculated on one result after subtraction between feed-forward equalizer  208  and decision-feedback equalizer  210 , and another result after subtraction between the first result and the signal after decision circuits. 
     A 4D-EQLFXC is computationally more complex than four 1D-EQLs with the same number of taps, so using the same number of taps in each case could be viewed as an uneven comparison. But, the computational complexity, in either case, can be estimated as the number of coefficients that are updated each cycle. 
     In order to compare the two approaches on an even basis, the number of taps has been adjusted so that the 200 coefficients must be updated in each simulation. For the 4D-EQLFXC there are ten such coefficients per tap whereas for the four 1D-EQLs there are only four coefficients per tap. Since 20 taps are used for the 4D-EQLFXC, 50 taps are used for each 1D-EQL. 
     The 4D-EQLFXC of the present invention exhibits significantly better noise margin compared to multiple scalar equalizers and advantageously permits the use longer cable runs or the use of physical channels that are in some way inferior. 
     These present invention can be extended and generalized to provide an “N” dimensional EQLFXC for N-channel full-duplex communication and is applicable to other communications systems in addition to Ethernet networks. 
     While the present invention is described in the context of a communication network, those skilled in the art will appreciate that the present invention is capable of being distributed as a program product in a variety of forms, and that the present invention applies equally regardless of the particular type of signal bearing media used to actually carry out the distribution. Examples of signal bearing media include: recordable type media such as floppy disks and CD-ROM, transmission type media such as digital and analog communications links, as well as other media storage and distribution systems. 
     Additionally, the foregoing detailed description has set forth various embodiments of the present invention via the use of block diagrams, flowcharts, and examples. It will be understood by those within the art that each block diagram component, flowchart step, and operations and/or components illustrated by the use of examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or any combination thereof. In one embodiment, the present invention may be implemented via Application Specific Integrated Circuits (ASICs). However, those skilled in the art will recognize that the embodiments disclosed herein, in whole or in part, can be equivalently implemented in standard Integrated Circuits, as a computer program running on a computer, as firmware, or as virtually any combination thereof and that designing the circuitry and/or writing the code for the software or firmware would be well within the skill of one of ordinary skill in the art in light of this disclosure. While the invention has been described with respect to the embodiments and variations set forth above, these embodiments and variations are illustrative and the invention is not to be considered limited in scope to these embodiments and variations. Accordingly, various other embodiments and modifications and improvements not described herein may be within the spirit and scope of the present invention, as defined by the following claims.