Abstract:
A frequency transfer type phase adjustment apparatus for frequency-transferring a plurality of reception signals derived from arrayed ultrasonic transducer elements into low frequency components by mixing these reception signals with a reference signal, and for applying delays to these low frequency components so as to be summed with each other, comprises small delay circuits for applying very short delays to the respective reception signals before being frequency-transferred; and a quantizing delay circuit for applying delays obtained by multiplying a delay time unit by an integer, to the respective reception signals after being frequency-transferred. A ratio of the delay time unit to one-cycle period of the reference signal is equal to an integer ratio. Phase shifters are inserted into either the output sides or the input sides of the mixers for the respective signal channels used for the frequency transfer operation. These phase shifters are capable of selectable phase shift amounts from a finite number of phase shift amounts which have been prepared for compensating phase differences in the delayed reception signals.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an apparatus for performing either a detection or an examination of an object by way of ultrasonic waves, and more particularly to a phase adjustment apparatus for phasing signals received from a plurality of ultrasonic transducer elements. 
     Ultrasonic apparatuses in which delays are applied to reception signals of ultrasonic waves detected by a plurality of arrayed transducer elements, wave fronts of the ultrasonic waves derived from a desirable azimuth, or a desirable distance are set to be the same phases, and these ultrasonic waves signals are summed with each other to obtain improved azimuth resolution, have been widely utilized in various technical fields such as a flaw examination for an object, and sonar or ultrasonic imaging of a biological body. 
     In JP-A-52-20857 (1977) and U.S. Pat. No. 4,140,022, there have been described such apparatuses that the reception signals are frequency-shifted into the low frequency signals by mixing the respective reception signals with the reference signals, the phases of which have been controlled, and thereafter the delays are applied to the low frequency signals so as to be summed with each other. In these apparatuses, it may be understood that the frequency-shift phasing methods are performed. 
     SUMMARY OF THE INVENTION 
     Even in such apparatuses for employing any of the above-described phasing methods, the delay amounts for the respective signals need to be changed in accordance with variations in the azimuth or distance in order to coincide the phases with each other. In general, to realize such delay amount changes under the limited cost of the apparatus, the delay unit for applying the delays is so constructed that selections are made of delay times analogous to the theoretical values of the delay times as to the reception signals from a limited number of plural delay times. In other words, the delay times are selected from values obtained or defined by multiplying a certain quantizing unit by an integer. 
     In accordance with the above-described frequency-shift phasing methods, even if the quantizing unit of the delay time of the delay unit is greater than the simple phasing method, sufficient azimuth resolution can be obtained. For instance, in one example as described in the above-described JP-A-52-20857 (1977), although the respective reception signals which have been frequency-shifted by way of the mixing process are sampled at a predetermined period, and the delay time amounts which are equal to a value obtained by multiplying this sampling period by an integer are realized, the sampling period can be set to a relatively large period. However, the highly precise phase control for the reference signals to be mixed with the respective reception signals must be performed in accordance with the wave fronts to be phased, and thus it is so difficult to arrange such a frequency shifting unit. 
     An object of the present invention is to provide a phase adjustment apparatus of an ultrasonic measuring device, capable of simplifying a phase control of a reference signal which is used in the frequency shift method, of lowering cost of a frequency shifting unit, and also of performing a correct phasing operation upon use of a short pulse. 
     Another object of the present invention is to provide such a phase adjustment apparatus of an ultrasonic measuring device, capable of adopting a large delay time unit for setting delay times at a main delay circuit after being frequency-shifted, whereby cost of the overall delay circuit can be reduced. 
     A basic construction of the phase adjustment apparatus according to the present invention resides in that small delay circuits are provided in front of the respective frequency shifting units for the reception signals of plural signal channels, and a main delay unit is provided after the frequency shifting-unit. The main delay circuit is a quantized delay circuit capable of selecting delay times for the respective reception signals from a plurality of delay times obtained by multiplying the unit delay time by an integer. The phasing operations of the respective reception signals are executed based on a total amount of the selected delay time and the delay times of the above-described small delay circuits, and then the resultant signals are added with each other, so that azimuth resolution is formed. Here, if the phases of the reference signals employed in the frequency shifting unit are common for all of the reception signal channels, namely the phase controls for the reference signals in accordance with the front waves to be phased are omitted, signal appearing times of the respective signal channels can be coincident with each other at the output of the main delay circuit. However, the phases of these signals do not generally coincide with each other. As a result, a signal for selectively indicating only reflection sound waves from a desirable azimuth or a desirable position cannot be obtained by the addition. Therefore, according to the present invention, the ratio of the delay time unit of the main delay circuit to one-cycle period of the reference signal used in the frequency shifting unit is selected to be an integer ratio. 
     First, if the delay time unit of the main delay circuit is equal to one-cycle period of the reference signal, or to a time unit obtained by multiplying this period by an integer, even when the phase of the reference signal is commonly used for all of the reception signal channels, since the phases of the outputs from the main delay circuit are coincident with each other, the signal for selectively indicating only the reflection sound waves from a desirable azimuth or a desirable position can be obtained with maintaining the above-described basic arrangement. 
     Next, when the ratio of the unit delay time of the main delay circuit to one-cycle period of the reference signal employed in the frequency shifting unit is selected to be an integer ratio of I to L (&#34;L&#34; being greater than or equal to 2), the outputs from the main delay circuit for the respective signal channels become L-sorts of phases as 2 πm/L (m=0 to L-1) in accordance with the delay times selected in the main delay circuit. Accordingly, it is so arranged that the phase shifters capable of selecting the phase shift amount from 2 πm/L (m=0 to L-1) are connected at the output sides or the input sides of the mixers for performing the frequency shift, and a selection for the amount of the phase shift at the phase shifters is made based upon a remainder when the delay time selected in the main delay circuit is divided by one-cycle period of the reference signal, whereby phase differences occurring in the outputs from the main delay circuit is removed. More specifically, when L= 2, in other words, the unit delay time of the main delay circuit is equal to a half-cycle period of the reference signal employed in the frequency shifting unit, or to a value obtained by multiplying this half-cycle period by an odd number, inverters for inverting the signals in response to the delay times selected in the main delay circuit are employed instead of the phase shifters. Alternatively, instead of these circuit arrangements, a reference phase controller may be employed which selects the phases of the reference signals given to the respective mixers of the signal channels from 2 πm/L (m=0 to L-1). Even in this case, the frequency shifting unit can be made simple, since it is possible to employ such an arrangement for selecting the phases of the reference signals supplied to the respective mixers of these signal channels from L-sorts of phases which have been previously prepared, instead of the precise phase controls for the reference signals in response to the wave fronts to be phased, which is required in the conventional frequency shift phasing apparatuses. 
     Other features of the present invention may be apparent from a detailed description of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram for explaining a basic arrangement of a phase adjustment apparatus according to the present invention; 
     FIG. 2 is a schematic block diagram for showing an embodiment of the present invention; 
     FIG. 3 is a schematic block diagram for representing another embodiment; 
     FIG. 4 is a schematic block diagram for showing a further embodiment; 
     FIG. 5 is a schematic block diagram for showing a delay circuit of a still further embodiment; and, 
     FIG. 6 is a schematic block diagram for showing a concrete embodiment of a main delay circuit employed in these embodiments. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 represents a circuit arrangement which will constitute a basic arrangement for various embodiments of the present invention. First of all, an operation of this circuit arrangement will now be considered. Reception signals from arrayed ultrasonic transducer elements TR 1  to TR N  are delayed in small delay circuits SD 1  to SD N , and these delayed signals are multiplied by a reference signal h(t) generated from a reference signal generator RG in mixers M 1  to M N . The reference signals h(t) is a complex signal indicated by: 
     
         h(t)=exp{-jω.sub.d t} 
    
     That is to say, the reference signal corresponds to two sinusoidal signals each having a frequency of Wd and having different phases with each other at 90 degrees. The complex signals represented by low frequency components obtained from multiplication results are delayed respectively in a main delay circuit MD, the setting unit of delay time of which is &#34;τ Q  &#34;; the delayed complex signals are added with each other in an adder AD so that one set of complex signals W(t) which have been phased with respect to either a desirable position, or a desirable azimuth; both a real part of the complex signal W(t) and an imaginary part thereof are squared respectively and then are added with each other; and a desirable reception signal is obtained from an absolute value calculator AV for calculating a square root of the added real and imaginary parts. 
     Assuming now that a transmission signal whose center frequency is ω s  is &#34;s(t)&#34;, this signal s(t) is approximated to: 
     
         s(t)=A(t)exp(jω.sub.S t) 
    
     where symbol A(t) indicates an envelope form of the transmission signal. The reception signal Un(t) caused by this transmission signal at an n-th element of reflection sound wave from the above-described desirable position or desirable azimuth, is expressed as follows, assuming now that propagation time of the sound wave up to the n-th element is &#34;τ n  &#34;; ##EQU1## In the main delay circuit MD, delay times of the respective signal channels are selected from a plurality of delay times that are equal to integer multiplication of a delay time unit &#34;τ Q  &#34;. The delay times Knτ Q  of the respective signal channels are selected in a delay selector DS in such a manner that a total delay time with this delay time and a delay time &#34;τ sn  &#34; caused by the small delay time SD n  becomes: 
     
         k.sub.n τ.sub.Q +τ.sub.sn =τ.sub.n 
    
     As a result, assuming now that a signal obtained by delaying the reception signal Un(t) in the small delay circuit is fn(t), this signal fn(t) is expressed by: 
     
         f.sub.n (t)=A(t+k.sub.n τ.sub.Q)exp{jω.sub.s (t+k.sub.n τ.sub.Q)} 
    
     Furthermore, if the delays Knτ Q  (Kn is an integer) which have been selected as described above, are given to this signal fn(t) in the main delay circuit MD, the reception signals of the respective element channels for the reflected sound waves from the above-explained desirable position or desirable azimuth, are generated at the same time instant of an output side of the main delay circuit MD. However, the reference signal h(t) applied to the mixers of the present circuit arrangement is commonly used for the element channels. As a consequence, a multiplication result &#34;gn(t)&#34; obtained from the mixer Mn is given by: ##EQU2## It should be noted that symbol ω&#39; corresponds to a frequency which is obtained by frequency-shifting the frequency of the reference signal in the mixer, and is expressed by: 
     
         ω.sub.s -ω&#39;=ω.sub.d 
    
     A signal Vn(t) in which this waveform has been delay-processed by the main delay circuit MD with a delay time of &#34;Knτ Q  &#34;, is given by: ##EQU3## It should also be noted that symbol &#34;τd&#34; is period of the reference signal and is expressed by: 
     
         ω.sub.d =2π/τ.sub.d 
    
     With respect to this signal, symbols &#34;kn&#34; are different from each other, depending on the channel number &#34;n&#34;. As a consequence, generally speaking, phases of the respective channel outputs from the main delay circuit MD are not coincident with each other, and amplitude of a resultant output by adding these channel outputs with each other, namely, ##EQU4## In other words, generally speaking, a signal which is not increased selectively represents the reflection signals from the above-described position or desirable azimuth, cannot be obtained from the output of the adder circuit AD. 
     Accordingly, in accordance with the present invention, such an ultrasonic signal processing circuit is proposed even with the basic arrangement constructed of the small delays, mixing, and quantized delays as shown in FIG. 1 in that both timings of generation of output signals from the respective channels are coincident with each other, and also phases of these output signals therefrom are coincident with each other, and a signal for selectively indicating sound waves reflected from either a desirable position, or a desirable azimuth can be obtained by way of an adding method. 
     FIG. 2 represents one embodiment of the present invention. The reception signals from the arranged ultrasonic transducer elements TR 1  to TR N  are delayed in the respective small delay circuits SD 1  to SD N , and then these delayed signals are multiplied by the reference signal h(t) generated from the reference signal generator RG in the mixers M 1  to M N . After the low frequency signal components produced in the respective mixers M 1  to M N  have been shifted by phase shifters PS 1  to PS N , the phase-shifted low frequency signals are delayed respectively in the main delay circuit MD. The delayed low frequency components are added with each other in the adder AD and then the added complex signal is converted into an absolute value signal in the absolute value calculator AV. It should be noted that the signals to be inputted into the small delay circuits SD 1  to SD N  may not be the reception signals directly from the arrayed ultrasonic transducer elements TR 1  to TR N . For instance, reception signals which have been amplified by preamplifiers, or reception signals from each of plural element groups which constitute the arrayed ultrasonic transducer elements may be used. 
     Also in the embodiment shown in FIG. 2, the main delay circuit MD is a quantized delay circuit capable of selecting the delay times of the respective signal channels from a plurality of delay times that are obtained by multiplying the delay time unit &#34;τ Q  &#34; by an integer. In response to a selection control signal derived from a delay and phase shift selector DPS, the delay time of the respective signal channels of the main delay circuit MD is selected in order satisfy the following relationship: 
     
         K.sub.n τ.sub.Q +τ.sub.Sn =τ.sub.n 
    
     Furthermore, in this embodiment, it is so set such a relationship between the delay time unit &#34;τ Q  &#34; of this main delay circuit and the period &#34;τ d  &#34; of the reference signal h(t) when &#34;L&#34; and &#34;I&#34; being integers; 
     
         τ.sub.Q =(I/L)τ.sub.d 
    
     That is to say, a ratio of &#34;τ d  &#34; to &#34;τ Q  &#34; is equal to an integer ratio. As to the frequency &#34;ω d  &#34; of the reference signal h(t), it is given: ##EQU5## At this time, if the phase shifters PS 1  to PS N  were not inserted in the circuit arrangement of this embodiment, the outputs Vn(t) of the respective channels of the main delay circuit MD are given as follows: ##EQU6## That is to say, the phases of the respective channel signals are rotated in a unit of 2π/L corresponding to the value of Kn. Therefore, phase shifters, phase shift amounts of which can be selected to be any of 2 mπ/L (m=0 to L-1), are employed as the phase shifters PS 1  to PS N , and thus the phase shift amounts of the respective phase shifters PS 1  to PS N  are selected in accordance with the delay amounts Knτ Q  (n=1 to N) of the respective channels of the main delay circuit MD. More concretely speaking, the delay/phase shift selector DPS employs the coefficient Kn of the delay amount Knτ Q  for each of the channels of the main delay circuit MD, and calculates a remainder &#34;r n  &#34; when KnI is divided by L. Then, the selection control signals are produced in such a manner that the respective phase shift amounts of the phase shifters PS 1  to PS N  become 2r n  π/L (n= 1 to N) and are supplied to the respective phase shifter. As a consequence, with respect to the reflection signals from the desirable position or the desirable azimuth, output signals Vn&#34;(t) from all channels of the main delay circuit MD may be equal to; 
     
         V.sub.n &#34;(t)=A(t)exp[jω&#39;t] 
    
     As previously described, when both the envelope shapes and phases of the signals in all of the channels are coincident with each other, and the resultant signals are added with each other in the adder AD, a result of this addition W&#34;(t) is expressed by: ##EQU7## whereby amplitudes thereof are grown. In other words, the signal selectively indicative of the reflection signals from either the above-described position, or the desirable azimuth can be obtained. 
     Now, an operation of a specific example of the arrangement shown in FIG. 2 will be described in which L=1, namely the setting unit τ Q  of the delay time of the main delay circuit MD is equal to either the period &#34;τ d  &#34; of the reference signal h(t), or a method obtained by multiplying this period &#34;τ d  &#34; by an integer. A channel output Vn(t) in this case is given by: ##EQU8## In this case, all of the signals have the completely same waveforms without employment of the phase shifters PS 1  to PS N . As a result, W(t) obtained by adding these signals with each other is expressed by: ##EQU9## and the amplitude thereof is greatly grown by the adding operation without receiving variations in the envelope shapes. Consequently, phasing operation can be achieved in the arrangement shown in FIG. 1 from which the phase shifters have been omitted. In the concrete example of the apparatus arrangement under such a condition of L=1, τ Q  =τ d  =100 n sec., the setting unit τ Q  of the delay time of the main delay circuit MD is equal to 100 n sec., and the reference signal&#39;s frequency is 10 MHz in accordance with, for instance, I=L=1. 
     Subsequently, a description will now be made of such a case that L=2. In this case, τ Q  /τ d  =I/L=1/2, 3/2, 5/2, - - - , and I must be an odd number. In other words, the unit delay time &#34;τ Q  &#34; of the main delay circuit MD is equal to a half-cycle period of the reference signal, or a period obtained by multiplying the half-cycle period by an odd number. Outputs Vn(t) of the respective channels of the main delay circuit MD are given by: ##EQU10## As described above, the phases of the respective signals are inverted in case of either an odd number, or an even number, respectively. Accordingly, an arrangement shown in FIG. 3 in which inverters IN 1  to IN N  are employed instead of the phase shifters PS 1  to PS N  represented in FIG. 2, may be employed. When the coefficient Kn of the delay time Knτ Q  of the signal channels of the main delay circuit MD is equal to an even number, a delay/inversion selector DIS causes the inverting operation of the inverter of this signal channel to be interrupted. When the coefficient &#34;Kn&#34; is equal to an odd number, the delay/inversion selector DIS causes the inverting operation of the inverter of this signal channel to be performed, due to such a selective phase inversion, all of the signals V&#39;n(t) become: 
     
         V.sub.n &#39;(t)=A(t)exp[jω&#39;t], 
    
     and then the waveforms of these signals are completely identical to each other. As a result, a summation result W&#39;(t) of these signals is given by: ##EQU11## Accordingly, it is possible to obtain a signals for selectively indicating the reflection sound waves from the desirable position, or desirable azimuth. In the concrete example of the embodiment shown in FIG. 3, for instance, in accordance with L=2 and I=3, τ Q  =120 n sec., τ d  =80 n sec., the set unit of the delay time of the main delay circuit MD is 120 n sec., and the frequency of the reference signal is 12.5 MHz. 
     FIG. 4 represents a further embodiment of the present invention. In this embodiment, instead of the phase shifters PS 1  to PS N  employed in the embodiment shown in FIG. 2, phase shifters PS 21  to PS 2N  are connected to the outputs to SD N . Since the operations of the mixers are linear with regard to the fixed phase angle, the same effects or results are obtained even when the phase shifters provided at the output sides of the mixers M 1  to M N  are moved to the input sides thereof. As a consequence, the phase shifting amounts &#34;φn&#34; selected in the respective phase shifters PS 21  to PS 2N  are 2 mπ/L (m=0 to L-1). A delay and phase shift selector DPS selects delay times &#34;Knτ Q  &#34; of the respective channels of the main delay circuit MD, and also selects a value of φn in accordance with a remainder &#34;r n  &#34; obtained when KnI is divided by L, which is similar to that of the embodiment shown in FIG. 2. It should be noted that a delay line may be employed other than the normal phase shifter as the phase shifters PS 1  to PS N . 
     FIG. 5 represents a still further embodiment of the present invention. In accordance with this embodiment, the phase shifters employed in the embodiment shown in either FIG. 2, or FIG. 4 are omitted, and a phase control of the reference signal hn(t) is performed by a reference signal phase shifter RC, instead of these phase shifters, which is supplied to mixers in the respective channels. 
     The reference signal h(t) produced from a high frequency oscillator RG is given as: 
     
         h(t)=exp{-jω.sub.d t} 
    
     Assuming now that a phase shift amount &#34;φn&#34; of the reference signal supplied to an n-th channel and shifted by the reference signal phase shifter RC is &#34;φn&#34;, the output signal hn(t) of the reference signal phase shifter RC becomes: 
     
         h.sub.n (t)=h(t)exp{-jφ.sub.n } 
    
     As a consequence, assuming now that a multiplication result obtained from the mixer Mn is gn(t), it is given: ##EQU12## A signal Vn(t) obtained by time-delaying this signal waveform by Knτ Q  in a quantized delay circuit QD, is expressed by: ##EQU13## Thus, if the phase shift amount φn of the reference signal phase shifter RS is set as: 
     
         φ.sub.n =2πk.sub.n τ.sub.Q /τ.sub.d 
    
     outputs Vn&#34;(t) of the mixers with respect to all of channels n=1 to N become: 
     
         V.sub.n &#34;(t)=A(t) exp[jω&#39;t] 
    
     All of these outputs have the completely same waveforms. As a result, an adding result W&#34;(t) from the adder AD is expressed by: ##EQU14## Then, a signal for selectively representing the reflection signals from the desirable position, or desirable azimuth can be obtained. Also in this embodiment, if a ratio of the setting unit τ Q  of the delay time for the quantized delay circuit QD, to the period τ d  of the reference signal h(t) is selected to be an integer ratio of I to L, a phase shift amount φn of the reference signal caused by the reference signal control unit RC is given as follows: 
     
         φ.sub.n =2k.sub.n Iπ/L 
    
     Therefore, in this case, the delay and phase shift selector DPS selects the delay times of the respective signal channels for the main delay circuit to be Knτ Q , and also selects the phase shift amount φn of the reference signals of the respective signal channels in the reference signal phase shifter RS in such a manner that the phase shift amount φn is selected to be as follows, in accordance with the remainder &#34;r n  &#34; when knI is divided by L: 
     
         φ.sub.n =2πr.sub.n /L 
    
     As described above, since the phase shift amounts of the reference signal caused by the reference signal phase shifter RS can be selected from L sorts of phase shift amounts, the arrangement of the apparatus can be made simple. 
     In the above-explained various embodiments, the reference signal was the complex signal and all of the respective blocks provided after the mixers handled the complex signals. However, the present invention is not limited such arrangements, but a simple arrangement capable of handling only the real part or the imaginary part of the complex signal may be employed. As previously explained, in such a simple arrangement capable of signal-processing only the real part or imaginary part, the absolute value calculator AC is no longer required. 
     In FIG. 6, it is possible to employ a circuit for realizing a delay in a storage circuit of a sampled signal, since the setting unit of the delay time is quantized in the quantized delay circuits QD in the above various embodiments. FIG. 6 is a concrete circuit example of such a delay circuit. Symbols R 1 , R n , R N  indicate an analog memory having a plurality of storage addresses, and the reception signals of the respective channels (the reception signals which have been processed by the mixers to produce low-frequency components) are sampled respectively and then stored into the respective memories. The storage, namely the sampling timing is performed in synchronization with a clock signal CP having a period &#34;τ c  &#34; which are generated from a clock oscillator CG. Also, the stored signals are read out in synchronization with the clock signal CP. It should be noted that both the storage addresses and the read addresses are sequentially controlled by an address controller AC, and then the delay time is determined, depending upon when the stored information is read out, starting from the first clock. Basically, although it is set to τ c  =τ Q , it may be set to 2τ c  =τ Q  since τ c  must selected to be small, depending upon the signal frequency. 
     As apparent from the foregoing descriptions, the cost of the apparatus can be lowered with correct phasing effects by combining the small delay circuits with the down-frequency mixing and quantizing delay circuits in any of these embodiments. More specifically, a specific attention should be paid to such a fact that assuming now that the ratio of the set unit τ Q  of the delay time in the quantized delay circuit QD, to the period τ d  of the reference signal h(t) is selected to be an integer ratio of I to L, the phase shift amounts which should be prepared in the phase shifters or the reference signal phase shifter employed in the respective channels, become L sorts of delay times. To avoid such a problem that either the phase shifters or the reference signal phase shifter becomes complex, it is preferable to select the values of τ Q  and τ d  in such a manner that &#34;L&#34; does not exceed 16.