Abstract:
A programmable transversal filter (10) utilizes a plurality of programmable multiplying means (M 1  -M 4 ). The result of each multiplication is summed by a summing circuit (7), thus providing an output signal (y(t)). The delay network of this invention comprises a plurality of sample and hold circuits (S 1  -S 4 ) which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods. 
     An analog cross-point switch (51) is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means. By utilizing an analog cross-point switch, a transversal filter having programmable tap weights is constructed wherein the tap weights remain fixed in the multipliers until reprogrammed, without the need for rotating the tap weights among the plurality of multipliers. Furthermore, each input voltage sample is stored in a single sample and hold circuit. Because the transversal filter of this invention does not cycle the tap weights among multipliers, the dynamic range of the output signal of the transversal filter constructed in accordance with this invention is increased over that of prior art programmable transversal filters, with a substantial decrease in fixed pattern noise.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to electronic circuits and, more particularly, to a transversal filter having programmable tap weights. 
     2. Description of the Prior Art 
     FIG. 1 shows a block diagram of a transversal filter. An analog input signal X(t) to be filtered is applied to terminal 11-0. This input signal X(t) is multiplied by tap weight a 0 , and the result of this multiplication is input to summation means 21. The input signal X(t) is also applied to delay means T 1 , thus providing at time t an output signal X(t-1) on node 11-1. This analog signal X(t-1) is multiplied by tap weight multiplier a 1 , and the result is applied to summing means 21. The analog signal X(t-1) available on node 11-1 is also applied to delay means T 2 , thus providing at time t an analog signal X(t-2) on node 11-2. This analog signal X(t-1) is multiplied by tap weight multiplier a 2  and the result is applied to summing means 21. In a similar manner, a plurality of N delay means T 1  through T N  (where N is selected positive integer) are connected as shown in FIG. 1, with the output signal from each delay means being defined as: 
     
         V.sub.j (t)=X(t-j)                                         (1) 
    
     where 
     V j  (t)= the output signal from the jth delay means at time t, where 0≦j≦N; and 
     X(t-j)= the input signal applied to input terminal 11-0 at time (t-j). 
     The output signals from each of the N delay means T 1  through T N  are multiplied by tap weights a 1  through a N , respectively, and the non-delayed input signal X(t) is multiplied by tap weight a 0 . In this manner, the output signal y(t) on output terminal 12 of summing means 21 is equal to: ##EQU1## 
     One such prior art transversal filter is described by Puckette et al. in &#34;Bucket-Brigade Transveral Filters&#34;, IEEE Transactions on Communication, Volume COM-22, No. 7, July 1974, pages 926-934. Puckette et al. describe the use of a bucket brigade delay line in a transversal filter. The Puckette approach taps the delay line with source followers, the desired weighting being established by the appropriate choice of capacitance values within each source follower. 
     Transversal filters have also been implemented utilizing charge-coupled devices (CCDs). Such a CCD transversal filter is described by Brodersen et al. in &#34;A 500-Stage CCD Transversal Filter for Spectral Analysis&#34;, IEEE Journal of Solid-State Circuits, Volume SC-11, No. 1, Feb. 1976, pages 75-83. Broderson et al. show that the tap weights are established by the use of appropriate photomasks for forming the electrical interconnects on the device surface. Another prior art CCD transversal filter is described by Baertsch et al. &#34;The Design and Operation of Practical Charge-Transfer Transversal Filters&#34;, IEEE Journal of Solid-State Circuits, Volume SC-11, No. 1, Feb. 1976, pages 65-73. 
     The above-mentioned prior art transversal filters are not programmable in that the tap weight multipliers, once established, may not be altered to provide a different transversal filter characteristic. Attempts have been made to provide a programmable transversal filter. One such attempt is described by White et al. in &#34;CCD and MNOS Devices for Programmable Analog Signal Processing and Digital Non-Volatile Memory&#34;, IEEE IEDM, Washington, D.C., 1973, pages 130-133. White et al. utilize a programmable MNOS conductance which is programmed with a train of pulses to adjust the threshold voltage. 
     Another programmable transversal filter is described by Haque &amp; Copeland in &#34;An Electrically Programmable Transversal Filter&#34;, International Electron Devices Meeting, Dec. 1976, pages 27-30. This prior art programmable transversal filter operates by cycling the tap weight coefficients in a digital shift register. However, such a technique results in the generation of fixed pattern noise due to inherent irregularities in the capacitance of the capacitors used to fix the tap weights stored in the digital shift register. 
     SUMMARY OF THE INVENTION 
     The programmable transversal filter constructed in accordance with this invention utilizes an analog delay line to provide a plurality of time delayed analog input signals. A plurality of programmable multiplying means are used to multiply each of said time delayed analog signals by a multiplying factor. The result of each mulitplication is summed by a summing circuit, thus providing an output signal from the transversal filter of this invention. 
     In accordance with this invention, the delay network includes a plurality of sample and hold circuits selectively connected to an input bus to which the analog input signal is applied. The sample and hold circuits are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods. 
     Of particular importance in the practice of this invention is the use of an analog cross-point switch, wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means, thereby providing a desired multiplied analog signal for application to the summing means, in order that the desired filter function may be realized. By utilizing an analog cross-point switch, a transversal filter having programmable tap weights is constructed wherein the tap weights remain fixed in the multipliers until reprogrammed, without the need for rotating the tap weights among the plurality of multipliers. Because the transversal filter of this invention does not cycle the tap weights among multipliers, the dynamic range of the output signal of the transversal filter constructed in accordance with this invention is increased over that of prior art programmable transversal filters, with a substantial decrease in fixed pattern noise. This is achieved by not rotating the tap weights through all multipliers. Rotation of tap weights causes noise, as is described in &#34;Distortion in Rotating Tap Weight Transversal Filters&#34;, IEEE Journal of Solid State Circuits, Vol. SC-14, June 1979, pp. 627. 
    
    
     A BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a typical transversal filter; 
     FIG. 2 is a schematic diagram of the transversal filter constructed in accordance with this invention; 
     FIG. 3 is a schematic diagram of a sample and hold circuit utilized in the circuit shown in FIG. 2; and 
     FIG. 4 is a schematic diagram of the multiplying means utilized in the transversal filter shown in FIG. 2. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 shows a schematic diagram of a four stage transversal filter 10 constructed in accordance with this invention. In practice, the programmable transversal filters constructed in accordance with this invention will have a large number of stages, although the following discussion regarding the four stage filter of FIG. 2 will describe the operation of this invention. 
     An analog input signal X(t) is applied to input terminal 9 of transversal filter 10. Switches 11, 12, 13 and 14 selectively connect the input signal X(t) to one of the sample and hold circuits S 1  through S 4 . The operation of switches 11 through 14 is timed to cause the switches 11 through 14 to operate in sequence, such that at time t 1 , X(t 1 ) is stored via closed switch 11 in sample and hold circuit S 1 , at time t 2 , analog signal X(t 2 ) is stored via closed switch 12 in sample and hold circuit S 2 , at time t 3  signal X(t 3 ) is stored via closed switch 13 in sample and hold circuit S 3 , and at time t 4  signal X(t 4 ) is stored via closed switch 14 in sample and hold circuit S 4 . In this manner, at any time t, analog signal X(t), X(t-1), X(t-2), and X(t-3) will be stored in sample and hold circuits S 1  through S 4 , although the location of signal X(t) and the time delayed signals X(t-1), X(t-2) and X(t-3) within sample and hold circuits S 1  through S 4  will vary with time. This is depicted in Table I. 
     The operation of the programmable transversal filter 10 of FIG. 2 is as follows, and will be easily understood in conjunction with Table I. First, the tap weights (i.e., multiplying factors) are loaded into multiplying means M 1  through M 4  (having tap weights of a 1  through a 4 , respectively) in a well-known manner which will be more fully described later. Then, at time t 1 , switch 11 closes and switches 12, 13 and 14 are open, thus storing x(t 1 ) in sample and hold circuit S 1 . At time t 2 , switch 12 closes and switches 11, 13 and 14 are open, thus storing X(t 2 ) in sample and hold circuit S 2 . At time t 3 , switch 13 closes and switches 11, 12 and 14 are open, thus storing X(t 3 ) in sample and hold circuit S 3 . Similarly at time t 4 , switch 14 closes and switches 11, 12 and 13 are open, thus storing X(t 4 ) in sample and hold circuit S 4 . At time t 5 , switch 11 closes and X(t 5 ) is stored in sample and hold circuit S 1 , with the original signal X(t 1 ) stored in sample and hold circuit S 1  being lost. Another way of looking at this storage, technique, is that at time t 5 , sample and hold circuit S 1  has stored X(t 5 ), sample and hold circuit S 4  has stored X(t 4 ), sample and hold circuit S 3  has stored X(t 3 ), and sample and hold circuit S 2  has stored X(t 2 ). 
     The operation of cross-point switch 51 is depicted in FIG. 2. The switches shown in analog cross-point switch 51 are shown as N channel metal oxide silicon (MOS) transistors, although any suitable switch means may be used. Utilizing N channel transistors, a high voltage (logical one) applied to the gate of the transistor causes it to conduct, while a low voltage (logical zero) applied to the gate causes it to turn off. A single logical one is applied to terminals A 0  through A 3  at any one time. 
     As shown in Table I, at time t 1  with a logical one applied to terminal A 0 , and logical zeroes applies to terminals A 1  through A 3 , sample and hold circuit S 1  is connected to multiplier M 1 , sample and hold circuit S 2  is connected to multiplier M 4 , sample and hold circuit S 3  is connected to multiplier M 3 , and sample hold circuit S 4  is connected to multiplier M 2 . 
     At time t 2 , a logical one is applied to terminal A 1 , with terminals A 0 , A 2  and A 3  being held low (logical zero). Thus, sample and hold circuit S 2  is connected to multiplier M 1 , sample and hold circuit S 3  is connected to multiplier M 4 , sample and hold circuit S 4  is connected to multiplier M 3 , and sample and hold circuit S 1  is connected to multiplier M 2 . The address signals applied to terminals A 0  through A 3 , and the resultant connections between sample and hold circuits S 1  through S 4  to multipliers M 1  through M 4 , are shown in Table I for times t 1  through t 4 . 
     Thus, as shown in Table I, the output voltage from multiplier M 1  during each time t 1  through t 4  is equal to a 1  X(t); the output voltage from multiplier M 2  is equal to a 2  X(t-1); the output voltage from multiplier M 3  is equal to a 3  X(t-2); and the output voltage from multiplier M 4  is equal to a 4  X(t-3). Thus, as shown in Table I, at all times t 1  through t 4  the output voltage y(t) from summing means 7 available on terminal 8 is equal to ##EQU2## which is the output voltage desired from a transversal filter. 
     One sample and hold circuit which may be used for sample and hold circuits S 1  through S 4  of FIG. 2 is shown in the schematic diagram of FIG. 3. Sample and hold circuit 211 comprises input terminal 212 which is connected to the input voltage X(t) through switch 11 of FIG. 2, when sample and hold circuit 211 serves as sample and hold circuit S 1  (FIG. 2). Input terminal 212 of sample and hold circuit 211 is connected to the noninverting input lead of operational amplifier 213. The output lead 215 of operational amplifier 213 is connected to transmission gate 216 comprising N channel MOSFET 216a and P channel MOSFET 216b. The state of transmission gate 216 (i.e., conducting or non-conducting) is controlled by sample and hold signal φ s  connected to terminal 222. Sample and hold signal φ s  is connected to the gate of N channel MOSFET 216a, and to inverter 221. Inverter 221 generates on its output lead 230 an inverted sample and hold signal φ s  which is connected to the gate of P channel MOSFET 216b. Thus, with high (positive) φ s  connected to terminal 222, transmission gate 216 conducts, and with a low φ s  transmission gate 216 turns off. In a similar manner, a second transmission gate 217 comprising N channel MOSFET 217a and P channel MOSFET 217b  is controlled by sample and hold signal φ s . 
     During the sample phase, φs goes high, and transmission gates 216 and 217 conduct. The output voltage from operational amplifier 213 is connected through transmission gate 216 to capacitor 218, thus charging capacitor 218 to the output voltage V x  of operational amplifier 213. This output voltage provides gate bias to N channel MOSFET 219, thus causing transistor 219 to turn on, thus providing a voltage V out  on terminal 229. This voltage V out  is also applied through transmission gate 217 to inverting input lead 214 of operational amplifier 213. Because the steady state voltages on the inverter input lead and on the noninverting input lead of an operational amplifier are equal, the voltage V out  is equal to the input voltage V in . In this manner, the output voltage V x  generated on output lead 215 of operational amplifier 213 and stored on capacitor 218 has a magnitude sufficient to bias the gate of transistor 229 in such a fashion as to generate on output terminal 229 a voltage V out  which is exactly equal to the sample input voltage V in . 
     After a time period of approximately 3 microseconds required to achieve a steady state condition in sample and hold circuit 211 such that the output voltage V out  on output terminal 219 is exactly equal to the sampled input voltage V in , the sample signal φ s  goes low, thus turning off transmission gates 216 and 217. Thus, a voltage V x  is stored on capacitor 218, which contains to bias the gate of transistor 219 so as to provide an output voltage V out  on output terminal 229 which is exactly equal to the sampled input voltage V in . Because transistor 219 is a metal oxide silicon (MOS) device, the gate bias provided by capacitor 218 requires virtually no current to be drawn from capacitor 218, thereby preventing the discharge of the voltage V x  stored on capacitor 218. Thus, the voltage V x  stored on capacitor 218 may be used to generate on output terminal 229 a voltage V out  equal to sampled input voltage V in  for long periods of time of the order of several milliseconds. The output voltage V out   provided on output terminal 229 is not affected by the turning off of transmission gate 217 because the very high impedance of inverting lead 214 of operational amplifier 213 draws substantially no current from output terminal 229. 
     When it becomes necessary to sample and store a second input signal V in  &#39;, sample and hold signal φ s  goes high, thus turning on transmission gates 216 and 217. A new voltage V x  &#39; is thus stored on capacitor 218, thereby generating a new voltage V out  equal to V in  &#39; on output terminal 229. 
     One multiplying means which may be used for each multiplier M 1  through M 4  (FIG. 2) is shown in schematic diagram in FIG. 4. Multiplier 96 includes operational amplifier 73 having output terminal 74, non-inverting input lead 76 connected to ground, and inverting input lead 75. Integrating capacitor 72, having a capacitance value C 72 , is connected between inverting lead 75 and output terminal 74. Connected in parallel with capacitor 72 is switch 71, which serves to discharge capacitor 72. Capacitor array 81, comprising a plurality of N capacitors C 1  through C n , is also utilized in the multiplier 96. One plate of each capacitor C 1  through C n  is connected to the inverting input lead 75 of operational amplifier 73. The second plate of each capacitor C 1  through C n  is connected to a pair of switches 1-a through N-a, and 1-b through N-b. The other terminal of switches 1-a through N-a is connected to ground, thus allowing the second plate of capacitors C 1  through C n  to be selectively connected to ground. Similarly, the other terminal of switches 1-b through N-b is connected to input terminal 77 in order that the second plate of each capacitor C 1  through C n  may be selectively connected to the analog input voltage V in  to be multiplied by multiplier 96. Capacitors C 1  through C n  may be of equal value, such that the effective capacitance of capacitor array 81 may range between 0 and NC, where N is the number of capacitors in capacitor array 81, and C is the capacitance value of each of the N capacitors. Alternatively, the capacitors C 1  through C n  of capacitor array 81 may be binary weighted, such that the capacitance value of each capacitor is defined as: 
     
         C.sub.j =2.sup.(j-1) C                                     (4) 
    
     where 
     C j  = the capacitance value of the jth capacitor, 
     j is a positive integer such that 0≦j≦N; and 
     C 1  is the capacitance value of capacitor C 1 . 
     In this manner, by selectively operating switches 1-a through N-a and 1-b through N-b, the effective capacitance of capacitor array 81 is to equal to 
     
         C.sub.81 =FC;                                              (5) 
    
     where 
     C 81  is the effective capacitance of capacitor array 81; and 
     F is an integer such that 0≦F≦(2 N  -1), where N is the number of capacitors in capacitor array 81. 
     The operation of multiplier 96 of FIG. 4 is as follows. If the sign bit of the digital tap weight multiplying factor indicates that the tap weight is positive, switch 71 closes, thus discharging capacitor 72. Switches 1-a through N-a also close, thus discharging capacitors C 1  through C n . Switch 71 then opens. Selected ones of switches 1-b through N-b then close, with the corresponding switches 1-a through N-a opening. For example, if switches 3-b and 7-b close, switches 3-a and 7-a open. The selection of which of switches 1-b through N-b will close is made such that the ratio of the effective capacitance of capacitor array 81 to the capacitance of capacitor 72 is equal to the desired multiplication factor, or tap weight. Thus, 
     
         G.sub.76 =-(C.sub.81 /C.sub.72)                            (6) 
    
     where 
     G 76  = the closed loop gain of operational amplifier 76, and thus equal to the tap weight of multiplier 96. 
     The closing of selected switches 1-b through N-b charges the selected capacitors C 1  through C N  to a voltage equal to V in , thus integrating a charge equal to C 81  V in  on integration capacitor 72. This results in an output voltage V out  on terminal 74 equal to 
     
         V.sub.out =-G.sub.76 V.sub.in.                             (7) 
    
     On the other hand, if the sign bit of the digital tap weight multiplying factor indicates that the tap weight is negative, switch 71 closes, thus discharging capacitor 72. Switches 1-b through N-b then close, thus charging capacitors C 1  through C N  to V in . Switch 71 then opens. Selected ones of switches 1-a through N-a then close, with the corresponding switches 1-b through N-6 opening. For example, if switches 3-a and 7-a close, switches 3-b and 7-b open. 
     The closing of selected switches 1-a through N-a discharges the selected capacitors C 1  through C N , thus integrating a charge equal to -C 81  V in  on integration capacitor 72. This results in an output voltage V out  on terminal 74 equal to 
     
         V.sub.out =G.sub.76 V.sub.in                               (8) 
    
     Thus, multiple 96 is capable of multiplying an analog input signal with a digital tap weight. The analog input signal and the digital tap weight may be either positive or negative. 
     The discussion in this specification is by way of example and is not to be construed as a limitation on the scope of this invention. Many alternate embodiments will become apparent to those skilled in the art in light of this disclosure. 
     
                       TABLE I______________________________________Signal Stored in     AddressSample and Hold Circuits                Signalstime S.sub.1 S.sub.2 S.sub.3                      S.sub.4                            A.sub.3                                 A.sub.2                                      A.sub.1                                           A.sub.0______________________________________T.sub.1X(t)    X(t-3)  X(t-2)                      X(t-1)                            0    0    0    1T.sub.2X(t-1)  X(t)    X(t-3)                      X(t-2)                            0    0    1    0T.sub.3X(t-2)  X(t-1)  X(t)  X(t-3)                            0    1    0    0T.sub.4X(t-3)  X(t-2)  X(t-1)                      X(t)  1    0    0    0T.sub.1X(t)    X(t-3)  X(t-2)                      X(t-1)                            0    0    0    1______________________________________MultiplierConnectedto Sample and        Output VoltageHold Circuits        from Multiplierstime S.sub.1      S.sub.2            S.sub.3                S.sub.4                    M.sub.1                           M.sub.2                                  M.sub.3                                         M.sub.4______________________________________T.sub.1M.sub.1      M.sub.4            M.sub.3                M.sub.2                    a.sub.1 X(t)                           a.sub.2 (X(t-1)                                  a.sub.3 X(t-1)                                         a.sub.4 X(t-3)T.sub.2M.sub.2      M.sub.1            M.sub.4                M.sub.3                    a.sub.1 (X(t)                           a.sub.2 X(t-1)                                  a.sub.3 X(t-2)                                         a.sub.4 X(t-3)T.sub.3M.sub.3      M.sub.2            M.sub.1                M.sub.4                    a.sub.1 X(t)                           a.sub.2 X(t-1)                                  a.sub.3 X(t-2)                                         a.sub.4 X(t-3)T.sub.4M.sub.4      M.sub.3            M.sub.2                M.sub.1                    a.sub.1 X(t)                           a.sub.2 X(t-1)                                  a.sub.3 X(t-2)                                         a.sub.4 X(t-3)T.sub.1M.sub.1      M.sub.4            M.sub.3                M.sub.2                    a.sub.1 X(t)                           a.sub.2 X(t-1)                                  a.sub.3 X(t-2)                                         a.sub.4 X(t-3)______________________________________Output Voltage y(t) from Summingtime Means 7______________________________________T.sub.1a.sub.1 X(t) + a.sub.2 X(t-1) + a.sub.3 X(t-2) + a.sub.4 X(t-3)T.sub.2a.sub.1 X(t) + a.sub.2 X(t-1) + a.sub.3 X(t-2) + a.sub.4 (X(t-3)T.sub.3a.sub.1 X(t) + a.sub.2 X(t-1) + a.sub.3 X(t-2) + a.sub.4 X(t-3)T.sub.4a.sub.1 X(t) + a.sub.2 X(t-1) + a.sub.3 X(t-2) + a.sub.4 X(t-3)T.sub.1a.sub.1 X(t) + a.sub.2 X(t-1) + a.sub.3 X(t-2) + a.sub.4 X(t-3)______________________________________