Abstract:
A method for fabricating a pixel structure of a liquid crystal device is provided. The method comprises providing a substrate defining a thin film transistor (TFT) region and a display region thereon. An opaque conductive layer is formed on the TFT region, and a transparent pixel electrode is formed on the display region. A patterned photoresist passivation layer is formed by backside exposure process on the TFT region, wherein the opaque conductive layer serves as the photo-mask during the backside exposure process. The photoresist passivation layer is subjected to a middle bake process to be reflowed, resulting in a complete covering of the opaque conductive layer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method for fabricating a liquid crystal display and more particularly to a method for fabricating a pixel structure of liquid crystal display. 
     2. Description of the Related Art 
     Thin film transistors (TFT) drive pixels in active matrix liquid crystal displays, active matrix organic light-emitting displays, image sensors and the like. Generally, TFT used in these apparatuses are formed of silicon semiconductor thin film. 
     Large area electronic devices (e.g., LCD (liquid crystal display)) typically include large arrays of thin-film transistors (TFTs) for addressing individual elements of the electronic device (e.g., pixels of the displays). As the demand for larger electronic devices, such as LCD displays, continues to rise, the TFT arrays used in these devices must include increasing numbers of TFTs and more complex interconnect structures. In addition, the need for large display devices complicates the fabrication of these devices using conventional semiconductor processes. In combination, these factors result in ever-increasing TFT array size and complexity. 
     To reduce some of the costs associated with the production of these larger LCD displays, a lift-off process is sometimes used to generate patterned structures that device openings (vias) and gaps between the various structures that make up the TFT array. In a conventional lift-off process, a base layer on which a patterned photoresist layer is formed is blanket-coated with an overlying thin film, typically a metal layer. Then, the patterned photoresist layer is stripped, which removes those portions of the metal layer formed on top of the patterned photoresist layer, leaving a patterned metal layer on the base layer. By eliminating the need for a separate etch process to create the patterned metal layer, the conventional (photoresist-based) lift-off process can simplify the overall production process, thereby reducing production costs. However, patterning the photoresist layer still requires a photolithography process. For cost-reduction purposes, it is generally desirable to minimize the number of photolithography process steps required. This is not only due to the demanding nature of the photolithography process itself, but also due to the time and costs involved in producing the delicate photomasks used in the photolithography process. 
     Accordingly, what is needed is a method for forming patterned structures for large area electronic devices that does not require the need for photolithographic masks (self-aligned) to save time and reduce fabrication cost. An exposure process technique so-called “back exposure” has been proposed to form desired transparent, colored and fine patterns on a transparent substrate by exposure to light from the back of the substrate with an opaque pattern as photo-mask. 
     The back exposure, however, needs numerous and complicated preparations. Further, there is no reference that discloses a method to form a passivation layer by back exposure. Therefore, it is necessary to develop a novel method for forming a passivation layer of LCDs by back exposure without increasing process complexity. 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment a method for fabricating a pixel structure of LCDs comprises: providing a substrate with a predetermined driving element region and a display region; forming a patterned first conductive layer on the substrate to form a gate electrode on the predetermined driving element region of the substrate; sequentially forming a gate dielectric layer, a semiconductor layer, and a second conductive layer on the substrate, and patterning the second conductive layer, the semiconductor layer and the gate dielectric layer to form patterned gate dielectric layer, semiconductor layer, and second conductive layer covering the gate electrode; conformally forming a transparent conductive layer on the patterned second conductive layer and the substrate, and patterning the transparent conductive layer to form a patterned transparent conductive layer covering part of the patterned second conductive layer and the display region of the substrate; etching the patterned second conductive layer over the gate electrode with the patterned transparent conductive layer serving as a mask to form a source electrode and a drain electrode, wherein the source electrode, drain electrode, patterned gate dielectric layer, patterned semiconductor layer, and the gate electrode comprise a thin film transistor (TFT); conformally forming a passivation layer on the TFT and the substrate; and patterning the passivation layer to form a patterned passivation layer on the TFT by back exposure with the patterned first and second conductive layer serving as a mask. 
     According to another embodiment of the invention, a method for fabricating a pixel structure of LCDs comprises: providing a substrate with a predetermined driving element region and a display region; forming a patterned first conductive layer on the substrate to form a plurality of gate lines, a gate electrode on the predetermined driving element region, a bottom electrode, and a gate contact; sequentially forming a gate dielectric layer, a semiconductor layer, and a second conductive layer on the substrate; patterning the second conductive layer, the semiconductor layer and the gate dielectric layer to form a plurality of data lines perpendicular to the gate lines; a top electrode over the bottom electrode separated by the pattern gate dielectric layer, and a patterned second conductive layer on the gate electrode, wherein the top electrode, bottom electrode, and the gate dielectric layer therebetween comprises a capacitor; conformally forming a transparent conductive layer on the substrate; patterning the transparent conductive layer to form a patterned transparent conductive layer on the patterned second conductive layer; a pixel electrode on the display region, and a pad electrically connected to the gate electrode; etching the patterned second conductive layer with the transparent conductive layer serving as a mask to form a source electrode and a drain electrode, wherein the source electrode, drain electrode, gate dielectric layer, patterned semiconductor layer, and the gate electrode comprises a thin film transistor (TFT); conformally forming a passivation layer on the substrate; and patterning the passivation layer to form a patterned passivation layers on the TFT, the capacitor, and a part of the gate contact by back exposure with the patterned first and second conductive layer serving as a mask. 
     An exemplary embodiment of a method for fabricating a pixel structure of LCDs comprises the following steps. A substrate with a predetermined driving element region and a display region is provided. A patterned opaque conductive layer is formed on the predetermined driving element region of the substrate and a transparent pixel electrode is simultaneously formed on the display region of the substrate. A photoresist passivation layer is formed on the substrate. The photoresist passivation layer is patterned by back exposure to form a patterned photoresist passivation layer on the patterned opaque conductive layer with the patterned opaque conductive layer serving as a mask. The photoresist passivation layer is subjected to a middle bake process to be reflowed, resulting in a complete covering of the patterned opaque conductive layer. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIGS. 1   a - 1   d  are top views of a method for fabricating a pixel structure for LCDs according to an embodiment of the invention. 
         FIGS. 2   a - 2   i  are sectional diagrams of  FIGS. 1   a - 1   d  along lines A-A′, B-B′, and C-C′ showing the method for fabricating a pixel structure of LCDs according to an embodiment of the invention. 
         FIGS. 3   a - 3   c  are cross sections of a method for fabricating a pixel structure for LCDs according to another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIGS. 1   a - 1   d  are top views of a method for fabricating a pixel structure for LCDs according to an embodiment of the invention, and  FIGS. 2   a  to  2   i  are sectional diagrams of  FIGS. 1   a - 1   d  along lines A-A′, B-B′ and C-C′, showing the method for fabricating electroluminescent devices. 
     A substrate  10  with a first surface  11  and a second surface  12  is provided, wherein the substrate  10  has a predetermined driving element region  13 , a display region  14 , a predetermined capacitor region  15 , and a peripheral pad region  16 .  FIG. 2   a  is sectional diagram of  FIG. 1   a  along lines A-A′, B-B′ and C-C′, respectively showing the fabrication method of driving element (thin film transistor (TFT)), storage capacitor, and electrode pad. Referring to  FIG. 1 , a first conductive layer (not shown) is formed on the substrate  10  and patterned to form a plurality of gate lines  17 , wherein the gate lines can be categorized by function into a gate electrode  18  on the predetermined driving element region  13 , a bottom electrode  19  on the predetermined capacitor region  15 , a gate line contact  20  on the peripheral pad region  16 . The substrate can be a transparent substrate or plastic substrate, and the first conductive layer can be titanium (Ti), molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), silver (Ag), a multi-layer or alloy thereof. 
     Next, referring to  FIG. 1   b  and  2   b ,  FIG. 1   b  and  2   b  show a gate dielectric layer, a semiconductor layer, an ohmic contact layer, and a second conductive layer on a substrate. The second conductive layer is patterned to form a plurality of data lines  26  and a top electrode  25  is formed on the predetermined capacitor region  15 , wherein the plurality of data lines  26  comprises a patterned second conductive layer  24  formed on the predetermined driving element region  13 . The ohmic contact layer, semiconductor layer, and gate dielectric layer are simultaneously patterned to form a patterned ohmic contact layer  23 , a patterned semiconductor layer  22 , and a gate dielectric layer  21  on the predetermined driving element region  13  and predetermined capacitor region  15 . Particularly, the bottom electrode  19 , the top electrode  25 , and gate dielectric layer  21  formed therebetween comprise a storage capacitor. The ohmic contact layer  23  can be a N+ type doping ohmic contact layer. The gate dielectric layer can be a dielectric material, such as silicon oxide, or silicon nitride. The semiconductor layer  22  can be a polysilicon, or amorphous silicon. Further, the semiconductor layer can be a doped semiconductor layer. The gate dielectric layer  21 , semiconductor layer  22 , ohmic contact layer  23  and second conductive layer are patterned by the same photo-mask and the same etching process. 
     Next, referring to  FIG. 2   c , a transparent conductive layer is conformally formed on the substrate  10 , and the transparent conductive layer is patterned to form a patterned transparent conductive layer  27  on the patterned second conductive layer  24 , a pixel electrode  28  on the display region  14 , and a pad  29  electrically connects to the gate line contact  20 . Next, referring to  FIGS. 1   c  and  2   d , the patterned second conductive layer  24  is etched to form a source electrode  30  and a drain electrode  31  with the patterned transparent conductive layer  27  serving as a mask. The source electrode  30 , drain electrode  31 , patterned gate dielectric layer  21 , semiconductor layer  22 , and the gate electrode  18  comprise a thin film transistor (TFT). Specifically, the aforementioned etching process is a self-alignment etching process. 
     Next, referring to  FIG. 2   e , a transparent passivation layer  32  and a photoresist passivation layer  33  (such as a positive photoresist layer) are conformally formed on the substrate  10 . Next, the photoresist passivation layer  33  is patterned by back exposure (light incident from the side of the first surface  11 ) with the first and second conductive layer (gate lines  17 , data lines  26 , source electrode  30 , drain electrode  31 , gate electrode  18 , top electrode  25 , bottom electrode  19 , and gate line contact  20 ) serving as a mask, referring to  FIG. 2   f . The transparent passivation layer  32  can be a silicon nitride or silicon oxide. 
     Still referring to  FIG. 2   f , since the photoresist passivation layer  33  is a positive photoresist layer, the exposed photoresist passivation layer is removed and the unexposed photoresist passivation layer  33   a  remains. It should be noted that the patterned photoresist passivation layer  33   a  is subjected to a middle bake process to be reflowed. Referring to  FIG. 2   g , the plane area of the reflowed photoresist passivation layer  33   b  is larger than that of the patterned photoresist passivation layer  33   a.    
     Referring to  FIG. 2   h , the transparent passivation layer  32  is patterned with the reflowed photoresist passivation layer  33   b  serving as a mask to form a patterned transparent passivation layer  32   a  completely covering the thin film transistor (TFT) and the storage capacitor. It should be noted that the plane area of the patterned passivation layer  32   a  is also larger than that of the back exposure mask (the first and second conductive layer). Next, referring to  FIGS. 1   d  and  2   i , the reflowed photoresist passivation layer  33   b  is removed, thus fabrication of a pixel structure for LCDs is completed, requiring only four photolithography steps according to the embodiment. Specifically, one of the four photolithography steps is a back exposure process to form the passivation layer, thereby avoiding alignment errors and improving yield and increasing throughput. 
     According to another embodiment of the present invention, the passivation layer can also be a positive photoresist layer. Referring to  FIG. 3   a , after completing the process as described in  FIG. 2   d , a positive photoresist passivation layer  40  is formed on the substrate  10 . Next, positive photoresist passivation layer  40  is patterned with the first and second conductive layer (gate lines  17 , data lines  26 , source electrode  30 , drain electrode  31 , gate electrode  18 , top electrode  25 , bottom electrode  19 , and gate line contact  20 ) serving as a mask, forming a patterned positive photoresist passivation layer  40   a , referring to  FIG. 3   b . Next, referring to  FIG. 3   c , the patterned positive photoresist passivation layer  40   a  is subjected to a middle bake process to be reflowed. It should be noted that the plane area of the reflowed positive photoresist passivation layer  40   b  is larger than that of the back exposure mask (gate lines  17 , data lines  26 , source electrode  30 , drain electrode  31 , gate electrode  18 , top electrode  25 , bottom electrode  19 , and gate line contact  20 ). 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.