Abstract:
A voltage reference circuit is arranged in a CMOS process based technology to provide a configurable voltage reference. The voltage reference includes bipolar transistors that are implemented as parasitic devices in the CMOS process. Two of the bipolar transistors are configured to generate a ΔVbe signal in the voltage reference circuit. An error amplifier cooperates with the two bipolar transistors via a control signal such that the control signal is related to ΔVbe/R. A first current source is coupled to another bipolar device, which is parallel connected to a resistor divider. The output of the resistor divider provides a divided reference signal that is related to the Vbe of the other bipolar device. Another resistor is coupled between a second current source and the output of the resistor divider such that an adjustable/temperature compensated reference signal is provided.

Description:
FIELD OF THE INVENTION 
     The present invention is related to a method and system for generating a reference voltage. More particularly, the present invention is related to a CMOS bandgap reference voltage circuit that operates on low-voltage power supplies with low power consumption. 
     BACKGROUND OF THE INVENTION 
     Bandgap voltage references are used as voltage references in electronic systems. The energy bandgap of Silicon is on the order of 1.2 V, and is independent from temperature and power supply variations. Bipolar transistors have a negative temperature drift with respect to their base-emitter voltage (Vbe decreases as operating temperature increases on the order of −2 mV/deg C.). However, the thermal voltage of a bipolar transistor has a positive temperature drift (Vt=kT/q, thus Vt increases as temperature increases). The positive temperature drift in the thermal voltage (Vt) may be arranged to compensate the negative temperature drift in the bipolar transistor&#39;s base-emitter voltage. Bandgap reference circuits use the inherent characteristics of bipolar transistors to compensate for temperature effects and provide a stable operating voltage over various power supply and temperature ranges. 
     One example bandgap reference circuit includes two bipolar transistors that are arranged with a common base. Two resistors are series connected between the emitter of the first bipolar transistor and a common ground. The emitter of second bipolar transistor is connected to the common point between the two resistors. The two bipolar transistors are arranged to provide a ten-to-one (10:1) current density difference with respect to one another. The ten-to-one current density results in a 60 mV difference between the base-emitter voltages of two bipolar transistors (ΔVbe=Vt*ln(I 1 /I 2 )=26 mV*ln(10)=60 mV, at room temperature). The 60 mV difference appears across the first resistor. The voltage between the base of the bipolar transistors and the ground terminal provides a voltage reference (VREF) that is roughly given as VREF=Vbe+X*Vt, where X is a constant that is used to scale the temperature correction factor. The temperature correction factor (X) is adjusted by the ratio of the resistors. Typical temperature corrected reference voltages of 1.25 V are achieved by this configuration. 
     SUMMARY OF THE INVENTION 
     The present invention is related to a voltage reference that operates from a low power supply voltage. More specifically the present invention is directed to voltage references that operate in the power supply range from approximately 1.2 volts to 6 volts. The bandgap reference is implemented in a CMOS process such that smaller die sizes and power consumption may be decreased. 
     Briefly stated, a voltage reference circuit is arranged in a CMOS process based technology to provide a configurable voltage reference. The voltage reference includes bipolar transistors that are implemented as parasitic devices in the CMOS process. Two of the bipolar transistors are configured to generate a ΔVbe signal in the voltage reference circuit. An error amplifier cooperates with the two bipolar transistors via a control signal such that the control signal is related to ΔVbe/R. A first current source is coupled to another bipolar device, which is parallel connected to a resistor divider. The output of the resistor divider provides a divided reference signal that is related to the Vbe of the other bipolar device. Another resistor is coupled between a second current source and the output of the resistor divider such that an adjustable/temperature compensated reference signal is provided. 
    
    
     A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a CMOS Bandgap reference that is arranged in accordance with the present invention. 
     FIG. 2 is a schematic diagram of an error amplifier for the CMOS bandgap reference that is shown in FIG. 1, in accordance with the present invention. 
     FIG. 3 is a schematic diagram of an IPTAT bias circuit that is used to bias the error amplifier that is shown in FIG. 1, in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active or passive, that are coupled together to provide a desired function. 
     The present invention relates to voltage references that operate from a low power supply voltage. Typically, it is necessary for the power supply voltage to be higher than the reference voltage. In some applications, such as portable devices or other devices that operate on reduced power supply levels, the maximum power supply voltage may be lower than 1.2 Volts. An exemplary implementation of the present invention is a CMOS based temperature compensated reference circuit that operates on power supply levels that are in the range from 1.2 Volts to 6 Volts. Additional CMOS technologies may have minimum power supply voltage requirements that are higher or lower than those used for the above-described example. Namely, typical CMOS circuits have power supply requirements that are determined based on the minimum threshold voltages, and saturation voltages that are required for the specific circuit. However, it is understood and appreciated that the concepts discussed in reference to the present invention may be adapted for use in reference circuits that have other power supply voltage levels. 
     The present invention is implemented in a CMOS process such that the overall die area that is required for an integrated circuit implementation is smaller than that employed in other technologies (e.g., BiCMOS). Also, a pure CMOS implementation ensures that overall current consumption is reduced compared to other technologies. An exemplary circuit that is arranged according to the present invention has been implemented in a pure CMOS process, yielding a 1 mV variation in reference voltage with power supplies from 1.2 V to 6 V, and temperatures from −45 deg C. to 95 deg C. 
     Bandgap Reference Circuit 
     FIG. 1 is a schematic diagram of an exemplary reference circuit ( 100 ) that is arranged in accordance with the present invention. Reference circuit  100  includes MOS transistors M 1 -M 9 , M 1 C-M 3 C, PNP transistors Q 1 -Q 3 , resistors R 1 -R 6 , IPTAT bias circuit  300 , and error amplifier  200 . The PNP transistors (Q 1 -Q 3 ) are implemented as vertical devices in the CMOS process, without any special processing requirements. An exemplary PNP transistor is constructed in a CMOS process as a vertical device that includes: p-type substrate material, n-type well material, and p-type diffusions that is placed in the n-type well. 
     Transistor M 1  includes a source that is connected to VCC, a gate that is connected to CTL, and a drain that is connected to node N 1 C. Transistor M 1 C includes a source that is connected to node N 1 C, a gate that is connected to ground, and a drain that is connected to node N 1 . Transistor M 2  includes a source that is connected to VCC, a gate that is connected to CTL, and a drain that is connected to node N 2 C. Transistor M 2 C includes a source that is connected to node N 2 C, a gate that is connected to ground, and a drain that is connected to node N 2 . Transistor M 3  includes a source that is connected to VCC, a gate that is connected to CTL, and a drain that is connected to node N 3 C. Transistor M 3 C includes a source that is connected to node N 3 C, a gate that is connected to ground, and a drain that is connected to node N 3 . Resistor R 1  is connected between nodes N 1  and N 4 . Resistor R 2  is connected between nodes N 4  and NE 1 . Resistor R 3  is connected between nodes N 1  and NE 2 . Resistor R 4  is connected between node N 2  and VDIV. Resistor R 5  is connected between VDIV and ground. Resistor R 6  is connected between VREF 2  and VDIV. PNP transistor Q 1  includes an emitter that is connected to node NE 1 , and a base and collector that are connected to ground. PNP transistor Q 2  includes an emitter that is connected to node NE 2 , and a base and collector that are connected to ground. PNP transistor Q 3  includes an emitter that is connected to node N 2 , and a base and collector that are connected to ground. Error amplifier  200  includes a non-inverting input (INP) that is connected to node NE 2 , an inverting input (INM) that is connected to node N 4 , an output that is connected to CTL, a bias output signal that is provided to BIASN, and a bias input that is coupled to BGBIAS. IPTAT bias  300  provides a bias signal to BGBIAS. 
     Transistors M 1 -M 3 , M 1 C-M 3 D, Q 1 -Q 3 , error amplifier  200 , IPTAT bias circuit  300 , and resistors R 1 -R 5  comprises a CMOS bandgap reference that is arranged in accordance with the present invention. IPTAT bias circuit  300  provides bias signal BGBIAS to error amplifier  200  that is proportional to absolute temperature. The bias signal cooperates with error amplifier  200  such that transistor M 1  (which is controlled by error amplifier  200  at node CTL) provides a current that is proportional to ΔVbe/R. Transistors M 1 C is are arranged to operate as cascode transistors for the cascode current source that is formed by transistor M 1  and M 1 C such that a current I 1  is provided at node N 1 . Current I 1  is driven into the parallel combination of R 1 , R 2 , Q 1  and R 3 , Q 2 . At steady-state operation, the voltages at node NE 2  and N 4  are approximately the same (ignoring any offsets from the error amplifier). Since transistors Q 1  and Q 2  have different effective emitter areas (10 to 1), the base-emitter voltages will not match exactly. The difference in the base-emitter voltages is provided across resistor R 2  such that the current in resistor R 2  corresponds to ΔVbe/R 2 , where ΔVbe is the difference in emitter voltages of transistors Q 1  and Q 2 . 
     The CMOS bandgap reference includes a bandgap cell that comprises transistors M 2 , M 3 , M 2 C, M 3 C, resistors R 4 -R 6 , and transistor Q 3 . Transistors M 2  and M 2 C form a cascode current source that provides current I 2  to node N 2  in response to the control signal (CTL). Transistors M 3  and M 3 C form another cascode current source that provides current I 3  to node N 3  in response to the control signal (CTL). Similar to current I 1 , the control signal is provided by the error amplifier such that currents I 2  and I 3  are proportional to ΔVbe/R. Transistor Q 3  will have an associated forward bias voltage that serves as a reference voltage (VREF 1 ) at node N 2 . In one example, the forward bias voltage across transistor Q 3  is on the order of 600 mV, and resistors R 4  and R 5  form a voltage divider that divides the forward bias voltage (VREF 1 ) such that VDIV=VREF 1 /(1+(R 4 /R 5 )). For example, when R 4  and R 5  are of equal values, and the forward bias voltage is 600 mV, the potential (VDIV) will be roughly 300 mV (assuming I 3 =0). When I 3  is nonzero, the output of the voltage divider (VDIV) formed by resistors R 4  and R 5  increases. The contribution to from current source I 3 , results in another reference voltage (VREF 2 ) at node N 3 , where VREF 2 =VDIV+I 3 *R 6 . Since I 3  is proportional to ΔVbe/R, the other reference voltage (VREF 2 ) is given by VREF 2 =[VREF 1 /(1+(R 4 /R 5 ))]+[X*(ΔVbe/R)]*R 6 , where X is a scaling factor for current I 3 . When R 4 =R 5 , VREF 2 =(VREF 1 / 2 )+(K*ΔVbe), where K is a constant that is determined by X, R 6  and R, such that a temperature compensation effect is provided to VREF 2 . 
     The temperature coefficient of VREF 2  is determined by the temperature coefficient of the base-emitter voltage of Q 1 , and the temperature coefficient of ΔVbe. Since the temperature coefficient of VBE is a negative number, and the temperature coefficient of ΔVbe is a positive temperature coefficient, then K can be adjusted such that the overall temperature coefficient of VREF 2  is zero at a predetermined temperature level. 
     Transistors M 2  and M 3  are matched to one-another according to a scaling coefficient such that the relative sizes of transistors M 2  and M 3  contribute to constant K. Also, resistor R 6  similarly contributes to the constant K. By adjusting the ration of R 4 /R 5  and by adjusting the constant K, the voltage associated with VREF 2  can range to any desired voltage. The voltage range for VREF 2  is limited by the power supply voltage and the operating range of the current source transistors (M 2 -M 3 , M 2 C-M 3 C). For example, the saturation voltage of transistors M 2  and M 3  may limit the range for currents I 2  and I 3 . 
     The CMOS bandgap reference includes a startup circuit that includes transistors M 4 -M 9 . Transistor M 4  includes a source that is connected to VCC, a gate that is connected to node N 6 , and a drain that is connected to node N 4 . Transistor M 5  includes a source that is connected to VCC, a gate that is connected to node N 6 , and a drain that is connected to node N 5 . Transistor M 6  includes a source that is connected to VCC, a gate and a drain that are connected to node N 6 . Transistor M 7  has a source that is connected to VCC, a gate that is connected to node N 5 , and a drain that is connected to node N 6 . Transistor M 8  includes a source that is connected to ground, a gate that is connected to node N 1 , and a drain that is connected to node N 5 . Transistor M 9  includes a source that is connected to ground, a gate that is connected to BIASN, and a drain that is connected to node N 6 . 
     The exemplary startup circuit that is arranged to initialize the CMOS bandgap circuit to an appropriate operating point during power-up. The startup circuit is enabled when transistor M 9  is active, such that transistor M 6  operates as a forward biased diode. However, transistor M 9  is inactive until the error amplifier is biased into a valid operating range, as indicated by signal BIASN. By maintaining transistor M 9  inactive until the error amplifier is properly biased, then a smooth start-up of the bandgap circuit  100  is possible. Transistors M 4  and M 5  operate as current sources in a current mirror that is formed with transistor M 6 . M 4  is activated by transistor M 6  such that a startup current (Istart) is provided to node N 4 . The startup current continues until the potential at node N 1  is sufficient to activate transistor M 8 . Once transistor M 8  is activated, the gate of transistor M 7  is pulled low (towards ground) and node N 6  is pulled up to VCC such that transistors M 4 -M 6  are deactivated. 
     The startup circuit that is illustrated in FIG. 1 provides for a smooth initialization of bandgap circuit  100 . However, the startup circuit may be replaced by another startup circuit, as may be necessary for a particular system design. In one example, a simple startup circuit may comprise a high value resistive device that is coupled between VCC and node N 4  (alternatively node N 1 , NE 1  or NE 2 ). Another circuit such as a POR (power-on reset) circuit may be used to gate the startup circuit such that the startup circuit is disabled after the bandgap circuit is in proper operation. 
     Error amplifier  200  is biased by BGBIAS as shown in FIG.  1 . By biasing the error amplifier with a PTAT (proportional to absolute temperature) current, higher order temperature effects are minimized so that the temperature coefficient that is associated with VREF 2  is well controlled. However, the IPTAT bias circuit may be replaced with a simple biasing circuit (e.g., a resistor device that is in series with a diode device) when the higher order temperature effects do not detrimentally effect the overall temperature compensation of VREF 2 . 
     Error Amplifier 
     FIG. 2 is a schematic diagram of an exemplary error amplifier ( 200 ) for the CMOS bandgap reference that is shown in FIG. 1, in accordance with the present invention. Error amplifier  200  includes MOS transistors MT, MTC, MIN, MIP, MS 1 , MS 2 , MD 1 -MD 4 , MB 1 -MB 2 , MC 1 -MC 4 , MM 3 -MM 4 , and capacitor C 1 . 
     Transistor MT includes a source that is connected to VCC, a gate that is connected to BGBIAS, and a drain that is connected to node N 204 . Transistor MTC includes a source that is connected to node N 204 , a gate that is connected to ground, and a drain that is connected to node N 203 . Transistor MIN includes a source that is connected to node N 203 , a gate that is connected to an inverting input (−, INN), and a drain that is connected to node N 201 . Transistor MIP includes a source that is connected to node N 203 , a gate that is connected to a non-inverting input (+, INP), and a drain that is connected to node N 202 . Transistor MS 1  includes a source that is connected to ground, a gate that is connected to node N 208 , and a drain that is connected to node N 201 . Transistor MS 2  includes a source that is connected to ground, a gate that is connected to node N 208 , and a drain that is connected to node N 202 . Transistor MD 1  includes a source that is connected to ground, and a gate and drain that are connected to node N 208 . Transistor MB 1  includes a source that is connected to VCC, a gate that is connected to BGBIAS, and a drain that is connected to node N 208 . Transistor MB 2  includes a source that is connected to VCC, a gate that is connected to BGBIAS, and a drain that is connected to node N 207 . Transistor MD 2  includes a source that is connected to ground, and a gate and drain that are connected to node N 207 . Transistor MC 1  includes a source that is connected to node N 201 , a gate that is connected to node N 207 , and a drain that is connected to node N 205 . Transistor MC 2  includes a source that is connected to node N 202 , a gate that is connected to node N 207 , and a drain that is connected to node N 206 . Transistor MD 3  includes a source that is connected to VCC, and a gate and drain that are connected to node N 205 . Transistor MM 3  includes a source that is connected to VCC, a gate that is connected to node N 205 , and a drain that is connected to node N 206 . Transistor MO 1  includes a source that is connected to VCC, a gate that is connected to node N 206 , and a drain that is connected to node N 209 . Transistor MC 3  includes a source that is connected to node N 209 , a gate that is connected to ground, and a drain that is connected to node N 210 . Transistor MD 4  includes a source that is connected to ground, and a gate and drain that are connected to node N 210 . Transistor MM 4  includes a source that is connected to ground, a gate that is connected to node N 210 , and a drain that is connected to OUT. Transistor MC 4  includes a source that is connected to node N 211 , a gate that is connected to ground, and a drain that is connected to OUT (CTL). Transistor MO 2  includes a source that is connected to VCC, a gate that is connected to OUT, and a drain that is connected to node N 211 . Capacitor C 1  is connected between VCC and node N 206 . 
     The error amplifier is arranged as a folded cascode amplifier that is biased with a bias signal (BGBIAS) such that the currents provided by transistors MT, MB 1 , and MB 2  are proportional to ΔVbe/R. The biasing of the error amplifier with ΔVbe/R currents will aid in reducing higher order temperature related effects in the overall system. However, the error amplifier may be biased with another bias signal as previously described above. Additionally, the error amplifier may be employed in another amplifier topology without departing from the spirit of the present invention. 
     MOS transistors MO 1 , MC 3 , MD 4 , MO 2 , MC 4 , and MM 4  form a current mirror circuit that is arranged to provide scaling of the control output signal for other electronic circuits (e.g., the error amplifier). In another embodiment of the present invention, the current mirror circuit (formed by MOS transistors MO 1 , MC 3 , MD 4 , MO 2 , MC 4 , and MM 4 ) is unnecessary and node N 206  is configured to operate as the output node that provides the control output signal (CTL). In still another embodiment, other arrangements of current mirrors may be employed without departing from the spirit of the present invention. 
     IPTAT Bias 
     FIG. 3 is a schematic diagram of an IPTAT bias circuit that is used to bias the error amplifier that is shown in FIG. 1, in accordance with the present invention. The IPTAT Bias circuit includes a ΔVbe generator circuit, a self-biased amplifier circuit, and a startup circuit. 
     The ΔVbe generator circuit includes resistors R 7 -R 9 , PNP transistors Q 4 -Q 5 , and MOS transistors MS 3  and MC 5 . PNP transistor Q 4  includes a base and collector that are connected to ground, and an emitter that is connected to node NE 4 . PNP transistor Q 5  includes a base and collector that are connected to ground, and an emitter that is connected to node NE 5 . Resistor R 7  is connected between nodes N 307  and N 308 . Resistor R 8  is connected between nodes N 308  and NE 4 . Resistor R 9  is connected between nodes N 307  and NE 5 . Transistor MS 3  includes a source that is connected to VCC, a gate that is connected to BGBIAS (OUT), and a drain that is connected to node N 305 . Transistor MC 5  includes a source that is connected to node N 305 , a gate that is connected to ground, and a drain that is connected to node N 307 . 
     The self-biased amplifier circuit includes transistors MIN 3 , MIP 3 , MT 3 , MTC 3 , MD 5 , MM 5 , MO 3 , MC 6 , MBO, resistor R 10 , and capacitors C 2  and C 3 . Transistor MT 3  includes a source that is connected to VCC, a gate that is connected to BGBIAS, and a drain that is connected to node N 304 . Transistor MTC 3  includes a source that is connected to node N 304 , a gate that is connected to ground, and a drain that is connected to node N 303 . Transistor MIN 3  includes a source that is connected to node N 303 , a gate that is connected to node NE 5 , and a drain that is connected to node N 301 . Transistor MIP 3  includes a source that is connected to node N 303 , a gate that is connected to node N 308  and a drain that is connected to node N 302 . Transistor MD 5  includes a source that is connected to ground, and a gate and drain that are connected to node N 301 . Transistor MM 5  includes a source that is connected to ground, a gate that is connected to node N 301 , and a drain that is connected to node N 302 . Transistor MO 3  includes a source that is connected to ground, a gate that is connected to node N 302 , and a drain that is connected to BGBIAS. Transistor MBO includes a source that is connected to VCC, a gate that is connected to BGBIAS, and a drain that is connected to node N 306 . Transistor MC 6  includes a source that is connected to node N 306 , a gate that is connected to ground, and a drain that is connected to BGBIAS. Resistor C 2  is coupled between VCC and BGBIAS. Resistor R 10  and capacitor C 3  are series connected between node N 302  and BGBIAS. 
     Transistors MIN 3  and MIP 3  are configured as a common source differential pair that is biased by a current source that is formed by transistors MT 3  and MTC 3 . Transistors MD 5  and MM 5  are configured as a current mirror circuit. Transistor MO 3  is configured as part of an output stage in the self-biased amplifier. Resistor R 10  and capacitor C 3  are configured as a compensation network such that stable operation of the self-biased amplifier is achieved. Capacitor C 2  is also configured as a filter network. 
     Transistors MC 5 , MTC 3 , and MC 6  are cascode transistors for current source/mirror transistors MS 3 , MT 3 , and MBO, respectively. The cascode transistors increase the output impedance of the current source/mirror transistors. In another example, the cascode transistors may be biased at another potential, or merely eliminated as may be desired. 
     The startup circuit includes transistors MS 4 , MM 6 -MM 7 , and MD 6 -MD 7 . Transistor MS 4  includes a source that is connected to VCC, a gate that is connected to node N 309  and a drain that is connected to node N 307 . Transistor MM 6  includes a source that is connected to VCC, a gate that is connected to node N 309  and a drain that is connected to node N 310 . Transistor MD 6  includes a source that is connected to VCC, and a gate and drain that are connected to node N 309 . Transistor MM 7  includes a source that is connected to node N 307 , a gate that is connected to node N 310 , and a drain that is connected to node N 309 . Transistor MD 7  includes a source that is connected to VCC, and a gate and drain that are connected to node N 310 . 
     In operation, the startup circuit provides a start-up current (Istart 3 ) to node N 307  during a power-up sequence. The start-up current is configured to initialize the self-biased amplifier and the ΔVbe circuit that is shown in FIG.  3 . In one example, node N 307  may initially be at ground, while nodes N 310  and N 309  are at VCC. When the power supply (VCC) increases above the threshold of transistor MD 7 , transistor MM 7  will become active forming a conduction path between transistor MD 6  and ground. Once transistor MD 6  is active, transistor MS 4  will also be active such that startup-current ISTART 3  is driven into node N 307 . After the voltage at node N 307  exceeds a predetermined amount (e.g., node N 310  and node N 307  are less than a threshold voltage apart), transistor MM 7  will be deactivated, resulting in the deactivation of transistors MD 6 , MM 6 , and MS 4 . Another startup circuit may be employed in place of the startup circuit that is shown in FIG. 3 without departing from the spirit of the present invention. 
     As illustrated in FIG. 3, PNP transistor Q 4  has an area that is ten times (10×) the area that is associated with transistor Q 3 . The PNP transistors are configured as diodes. Since transistors Q 4  and Q 5  have a common base connection, the base-emitter voltages of transistors Q 4  and Q 5  differ by an amount that is determined by resistors R 7 -R 9  and the current flow through the resistors. The self-biased amplifier senses the emitter voltage of transistor Q 5  at node NE 5 , the voltage of resistor R 8  at node N 308 , and provides a feedback current through transistors MS 3  and MC 5 . The feedback current is provided to transistors Q 4  and Q 5  via resistors R 7 -R 9 . At steady-state operation, the self-biased amplifier controls the feedback current such that the voltage at node NE 5  and node N 308  are equal. The emitter voltage of transistor Q 4  will be lower than the emitter voltage of transistor Q 5  due to the transistors differences in area. Thus, the difference in the base-emitter voltage (ΔVbe) of transistors Q 4  and Q 5  is provided across resistor R 8 . The current flow in transistors MS 3 , MC 5 , MBO, and MC 5  is thus proportional to absolute temperature (IPTAT), and is determined by ΔVbe/R. 
     The PNP transistors that are illustrated in FIGS. 1-3 are vertical transistor structures that are formed in the substrate of a CMOS process. For example, a PNP transistor is formed in a CMOS process by placing p-type material in an n-type well, where the substrate material is p-type such that the well operates as a base, the p-type material operates as an emitter, and the p-type substrate material operates as a collector. 
     In light of the above description, it is understood and appreciated that the circuits shown in FIG.  1 -FIG. 3 may be arranged to operate with NPN transistors instead of PNP transistors. When NPN transistors are employed, the entire system will be redesigned such that the p-type MOS transistors are replaced with n-type MOS transistors, and vice-versa. For example transistors M 1 , M 2 , and M 3  would be replaced with n-type MOS transistors that are referenced to ground instead of VCC when transistors Q 1 -Q 3  are replaced with NPN type transistors that are referenced to VCC. Additionally, it is understood and appreciated that the design may be further arranged to operate using other field effect transistor types including, but not limited to JFET transistors, GaAsFET transistors, and the like. 
     The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.