Abstract:
A semiconductor device which is sealed with a plastic sealing layer and whose thickness is regulated to be below a given value is known. Since the thickness of the device is small, and the thickness of the upper portion of the plastic sealing layer and the thickness of the lower portion thereof are different from each other, the plastic sealing layer becomes warped, thus causing a crack on the side of the semiconductor chip.  
     To solve this problem, the semiconductor device according to the present invention comprises a semiconductor chip on which a plurality of grooves are defined. Consequently, the thickness of the lower portion of the plastic layer becomes greater, thereby preventing cracks from occurring on the semiconductor chip.

Description:
[0001]    This patent application claims priority based on a Japanese patent application, H10-295817 filed on Oct. 16, 1998, the contents of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a plastic molding seal semiconductor device, and in particular to an LOC (Lead on Chip) type semiconductor.  
           [0004]    2. Description of the Related Art  
           [0005]    Plastic molding seal semiconductor devices for electronic equipment have been widely used. These semiconductor devices are sealed with plastic to protect the semiconductor chips laid in the semiconductor devices. Recently, these semiconductor devices, especially LSIs (Large Scaled Integrated circuits) have increased in size with the enhancement of integration. For example, the storage capacity of memory devices is increasing, so that the memory devices need to become larger. This is demonstrated by 16MB DRAM and 64 MB DRAM, for example.  
           [0006]    On the other hand, appliances tend to be increasingly smaller in size, which requires the semiconductor devices to be smaller. To satisfy these two divergent requirement of integration, LOC (Lead On Chip) type semiconductor devices are employed, in which one end of each of a plurality of leads is arranged overlapping with the semiconductor chip.  
           [0007]    [0007]FIG. 1A shows the inside of the semiconductor device, FIG. 1B is a cross sectional view of the semiconductor device taken along the line A-A of FIG. 1A, and FIG. 1C shows a cross sectional view of the semiconductor device taken along the line B-B of FIG. 1A. As shown in FIG. 1A, since this semiconductor device is of the LOC type, a plurality of leads  92  are arranged directly on the semiconductor chip  91  via a plurality of insulating tapes  93 . Also mounted on the semiconductor chip  91  are a plurality of pads  95 . Each pad  95  serves as an electrode used for connecting one of a plurality of terminals of the semiconductor chip  91  to an external circuit (not shown), wherein each pad  95  for a terminal is connected to a corresponding lead  92  using a bonding wire  96 . The semiconductor chip  91  and most of each lead  92  are molded with a plastic sealing layer  97 , that is to say, a package. The other end of each lead  92 , that is to say, the end that is not molded with the plastic sealing layer  97 , protrudes from the plastic sealing layer  97 , and is connectable to the above-mentioned external circuit.  
           [0008]    In the LOC semiconductor devices, the leads  92  are arranged on the semiconductor chip  91  without using a die-pad for supporting the semiconductor chip  91 . Accordingly, the LOC semiconductor devices are reduced in size compared with other semiconductor devices. In other words, the LOC semiconductor device can accommodate a semiconductor chip whose size is almost 90% of the LOC semiconductor device.  
           [0009]    In the LOC semiconductor devices, in particular the TSOP (Thin Small Outline Package) semiconductor device, the thickness, that is, the distance between the top of the upper portion  97 A of the plastic sealing layer  97  and the bottom of the protruding end of the lead  92  is required to be less than 1.27 mm. Therefore, it is necessary to reduce the thickness of the plastic sealing layer  97 . On the other hand, in these devices it is also required that the upper portion  97 A be thick enough to cover the bonding wire  96 . Consequently, both the length D1 of the upper portion  97 A and the length D2 of the lower portion  97 B of the plastic sealing layer  97  are designed to be thin, and in addition the length D1 is designed to be larger than the length D2, as shown in FIG. 1B.  
           [0010]    The semiconductor chip  91  has a small linear expansivity or shrinkage ratio. On the contrary, the plastic sealing layer  97  has a large linear expansivity or shrinkage ratio. The upper portion  97 A is larger in thickness than the lower portion  97 B, so that the upper portion  97 A shrinks more than the lower portion  97 B. As a result, the plastic sealing layer  97  becomes warped while the semiconductor chip  91  remains flat. This yields a stress around the center of the semiconductor chip  91 , thus causing a crack or fracture  98  in the lateral direction of the semiconductor chip  91  in the bottom side of the semiconductor chip  91  as shown in FIG. 1C.  
           [0011]    On the other hand, the semiconductor chip  91  and the lower portion  97 B could become exfoliated during the operation of the semiconductor equipment due to the difference in linear expansivity between the semiconductor chip  91  and the plastic sealing layer  97 . A partial exfoliation does not cause damage to the semiconductor chip  91 . However, a total exfoliation might yield a crack in the semiconductor chip  91  or in the plastic sealing layer  97 . If water is absorbed in the semiconductor device, the water will vaporize to yield a crack therein.  
           [0012]    As discussed above, the conventional LOC semiconductor device has such drawbacks that there may cause a crack in the semiconductor chip or in the plastic sealing layer.  
         SUMMARY OF THE INVENTION  
         [0013]    Therefore, it is an object of the present invention to provide a semiconductor device which overcomes the drawbacks in the related art. This object is achieved by the combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.  
           [0014]    According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip including a top side and a bottom side; a package including an upper portion provided on the top side of the semiconductor chip and a lower portion provided on the bottom side thereof, the upper portion being thicker than the lower portion; and a resisting member provided on the bottom side of the semiconductor chip, for preventing the semiconductor chip from being bent.  
           [0015]    According to another aspect of the present invention, there is provided a semiconductor device, wherein a plurality of grooves are formed on the bottom side of the semiconductor chip, and the resisting member is defined by the material of the package which lies in the plurality of grooves. The plurality of grooves are preferably arranged in parallel with each other in the longitudinal direction of the semiconductor chip.  
           [0016]    According to still another aspect of the present invention, there is provided a semiconductor device, wherein the bottom side of the semiconductor chip is convex.  
           [0017]    According to still another aspect of the present invention, there is provided a semiconductor device, wherein the resisting member has an adhesive which makes the bottom side of the semiconductor chip adhere to the lower portion of the package. This adhesive preferably includes polyimide resin. The adhesive is preferably provided either on all of the bottom side of the semiconductor chip or on a part of the bottom side of the semiconductor chip. If the adhesive is provided on a part of the bottom of the semiconductor chip, then the adhesive is preferably provided either symmetrically in the longitudinal direction of the semiconductor chip, symmetrically in the lateral direction of the semiconductor chip, or on a plurality of separate areas of the bottom side of the semiconductor chip. The plurality of separate areas preferably either in parallel with each other in the longitudinal direction of the semiconductor chip, or in parallel with each other in the lateral direction of the semiconductor chip. The adhesive preferably includes a polyimide tape, or a polyimide pad, which is made to adhere to the bottom side of the semiconductor chip with a metallic paste. The adhesive preferably lies along the center of the longitudinal axis of the semiconductor chip.  
           [0018]    According to still another aspect of the present invention, there is provided a semiconductor device having a plurality of leads formed on a semiconductor chip comprising: a semiconductor chip including a top side and a bottom side; a package including an upper portion provided on the top side of the semiconductor chip and a lower portion provided on the bottom side thereof, the upper portion being thicker than the lower portion; and a resisting member provided on the bottom side of the semiconductor chip, for preventing the semiconductor chip from being bent.  
           [0019]    According to still another aspect of the present invention, there is provided a semiconductor device, thickness of which is below a given value regulated by a specification of Thin Small Outline Package, comprising: a semiconductor chip including a top side and a bottom side; a package including an upper portion provided on the top side of the semiconductor chip and a lower portion provided on the bottom side thereof, the upper portion being thicker than the lower portion; and a resisting member provided on the bottom side of the semiconductor chip, for preventing the semiconductor chip from being bent.  
           [0020]    According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a semiconductor chip and a package sealing the semiconductor chip, the semiconductor chip having a top side and a bottom side, and a plurality of leads being arranged on the top side of the semiconductor chip, the method comprising: forming a resisting member on the bottom side of the semiconductor chip, for preventing the semiconductor chip from being bent.  
           [0021]    According to still another aspect of the present invention, there is provided a semiconductor device, having a thickness below a given value regulated by a specification of Thin Small Outline Packages, comprising: a semiconductor chip including a top side and a bottom side; a package including an upper portion provided on said top side of the semiconductor chip and a lower portion provided on said bottom side thereof, said upper portion being thicker than said lower portion; and a resisting member provided on said bottom side of said semiconductor chip, for preventing said semiconductor chip from being bent.  
           [0022]    This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]    The present invention will be understood more fully from the detailed description given hereinbelow, in conjunction with the accompanying drawings.  
         [0024]    [0024]FIG. 1A shows the inside of the conventional LOC semiconductor device;  
         [0025]    [0025]FIG. 1B is a cross sectional view taken along the line A-A of the LOC semiconductor device of FIG. 1A;  
         [0026]    [0026]FIG. 1C is another cross sectional view taken along the line B-B of the LOC semiconductor device of FIG. 1A;  
         [0027]    [0027]FIG. 2A is a cross sectional view of the semiconductor device of the first embodiment according to the present invention;  
         [0028]    [0028]FIG. 2B shows the bottom of the semiconductor chip of the semiconductor device of FIG. 2A;  
         [0029]    [0029]FIG. 3A is a cross sectional view of the semiconductor device of the second embodiment according to the present invention;  
         [0030]    [0030]FIG. 3B shows the bottom side of the semiconductor chip mounted in the semiconductor device of the second embodiment;  
         [0031]    [0031]FIG. 4A is a cross sectional view of the semiconductor device of the third embodiment according to the present invention;  
         [0032]    [0032]FIG. 4B shows the bottom side of the semiconductor chip mounted in the semiconductor device of the third embodiment;  
         [0033]    FIGS.  5 A- 5 D show coating patterns of the adhesive of the third embodiment;  
         [0034]    [0034]FIG. 6A is a cross sectional view of the semiconductor device of the fourth embodiment according to the present invention;  
         [0035]    [0035]FIG. 6B shows the bottom side of the semiconductor chip mounted in the semiconductor device of the fourth embodiment;  
         [0036]    [0036]FIG. 7A is a cross sectional view of the semiconductor device of the fifth embodiment according to the present invention; and  
         [0037]    [0037]FIG. 7B shows the bottom side of the semiconductor chip mounted in the semiconductor device of the fifth embodiment. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0038]    The invention will now be described based on the preferred embodiments, which do not intend to limit the scope of the present invention, but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.  
         [0039]    First Embodiment  
         [0040]    The first embodiment of the semiconductor device according to the present invention will now be described. The main feature of the first embodiment is that the bottom side of the semiconductor chip has a groove to increase the thickness of the lower portion of the plastic sealing layer.  
         [0041]    [0041]FIG. 2A is a cross sectional view of the semiconductor device of the first embodiment and FIG. 2B shows the bottom of the semiconductor chip mounted in the semiconductor device.  
         [0042]    The semiconductor device is an LOC (Lead On Chip) semiconductor device, and in particular, a TSOP (Thin Small Outline Package) semiconductor device. Therefore, the thickness of the semiconductor device is required to be below 1.27 mm as explained above.  
         [0043]    The semiconductor device incorporates a semiconductor chip  11 , a plurality of leads  12 , a plurality of insulation tapes  13 , a plurality of electrode pads  15 , a plurality of bonding wires  16 , and a plastic sealing layer  17 . Examples of the materials used for these components are as follows. The insulation tapes  13  are made of a thermoplastic resin, wherein both the top side and the bottom side of the insulation tapes  13  are adhesive. The electrode pads  15  are made of Ni-Fe and Cu. The bonding wires  16  are made of alloy.  
         [0044]    On the top side  11 A of the semiconductor chip  11 , one end of each lead  12  is arranged via an insulation tape  13 . Specifically, each lead  12  is arranged in such a fashion that one end of each lead  12  is directed toward a pad  15 . Around the center of the side  11 A of the semiconductor chip  11 , the plurality of pads  15  are formed in the longitudinal direction of the semiconductor chip  11 . Each pad  15  serves as an electrode for connecting a functional element or terminal formed on the semiconductor chip  11  to an external circuit (not shown) . The plastic sealing layer  17  molds the semiconductor chip  11  and other components. That is, the plastic sealing layer  17  serves as a package for sealing the semiconductor chip  11 .  
         [0045]    One end of each bonding wire  16  is fixed to a lead  12  by a metal plating  14  while the other end of each bonding wire  16  is fixed to the pad  15  facing to the lead  12  through heating with an ultrasonic wave, whereby the lead  12  and the corresponding pad  15  are electrically connected to each other. The internal portion  12 A of each lead  12  is covered by the plastic sealing layer  17  as well as the semiconductor chip  11  while the external portion  12 B of the lead  12  projects from the semiconductor device. The internal portion  12 A and the external portion  12 B serve to transmit and receive signals between the semiconductor chip  11  and the external circuit.  
         [0046]    As discussed above, since in the LOC semiconductor device or the TSOP semiconductor device, the internal portions  12 A of the leads  12  are fixed on the semiconductor chip  11  without the die pad used in other semiconductor devices, this semiconductor device can accommodate a larger semiconductor chip  11  as compared to other semiconductor devices. In other words, this structure of this semiconductor device increases the ratio of the size of the semiconductor chip to the size of the semiconductor. In summary, the plastic sealing layer  17  in semiconductors of this type becomes smaller compared with other types of semiconductors.  
         [0047]    In a TSOP semiconductor having such a structure, a plurality of grooves  11 C are formed in the bottom side  11 B of the semiconductor chip  11 . More specifically, the plurality of grooves  11 C, which act as a resisting member for preventing the semiconductor chip  11  from being warped or bent, are arranged in parallel with each other in the longitudinal direction of the semiconductor chip  11 . As explained above, the upper portion  17 A of the plastic sealing layer  17  is required to be thicker than the lower portion  17 B of the plastic sealing layer  17  so that the upper portion  17 A completely covers the bonding wires  16 . In accordance with the present invention, however, since the plurality of grooves  11 C are formed in the semiconductor chip  11 , the thickness of the lower portion  17 B of the plastic sealing layer  17  is increased at the location of the grooves. Hence, the thickness of the lower portion  17 B of the plastic sealing layer  17  becomes closer to that of upper portion  17 A thereof. Accordingly, the magnitude of the stress in the upper portion  17 A becomes almost the same as the magnitude of the stress in the lower portion  17 B, whereby the warpage of the plastic sealing layer  17  is reduced compared to the conventional art. This decreases the probability of cracks occurring in the semiconductor chip  11 .  
         [0048]    The distance between the surface of the plastic sealing layer.  17  and the far end of the external portion  12 B of the lead  12  is defined as 1.27 mm by the specification of the TSOP semiconductor device; in addition, the thickness of plastic sealing layer  17  is required to be below approximately 1.00 mm while the thickness of the lower portion  17 B ranges from approximately 0.3 mm to approximately 0.4 mm. Therefore, it is preferable that the depth of each groove  11 C ranges from approximately 10 um to approximately 100 um, that is to say, from approximately {fraction (1/40)} of the thickness of the lower portion  17 B to approximately ⅓ thereof. If the depth of the groove  11 C is more than 100 um, the strength of the semiconductor chip  11  itself is reduced such that cracks may easily occur therein.  
         [0049]    Second Embodiment  
         [0050]    The second embodiment of the semiconductor device according to the present invention will now be described.  
         [0051]    [0051]FIG. 3A is a cross sectional view of the semiconductor device of the second embodiment, and FIG. 3B shows the bottom of the semiconductor chip mounted in the semiconductor device of the second embodiment. The principal feature of the second embodiment is that the thickness of the center portion of the semiconductor chip is greater than that of the other portions. In other words, the main feature is that the semiconductor chip has a curved bottom.  
         [0052]    The components of the semiconductor device according to the second embodiment are almost the same as those of the semiconductor device according to the first embodiment; therefore, for ease of explanation, a discuss on the feature of the second embodiment will be made below. In FIG. 3A, the semiconductor chip  11  has a curved or convex shape. The convex portion of the semiconductor chip  11  acts as a resisting member for preventing the semiconductor chip  11  from being warped or bent. More specifically, the thickness of the portion near the center of the semiconductor chip  11  is greater than that of the portion near the edges. Accordingly, the strength of the center portion of the semiconductor chip  11  for resisting the stress of the plastic sealing layer  17  becomes greater than the strength of the other portions of the semiconductor chip  11 .  
         [0053]    In summary, as explained above, in the second embodiment, the center portion of the semiconductor chip  11  is thick compared with the other portions thereof; therefore, the strength of the center of the semiconductor chip  11  for resisting the stress of the plastic sealing layer  17  becomes greater, so as to prevent cracks from occurring on the bottom  11 B of the semiconductor chip  11 .  
         [0054]    Third Embodiment  
         [0055]    The third embodiment of the semiconductor device according to the present invention will now be described in detail.  
         [0056]    [0056]FIG. 4A is a cross sectional view of the semiconductor device of the third embodiment, and FIG. 4B shows the bottom of the semiconductor chip mounted in the semiconductor device. The components of the semiconductor device of the third embodiment are almost the same as those of the semiconductor device of the first embodiment. Therefore, the distinguishing feature of the third embodiment will principally be discussed below.  
         [0057]    The third embodiment is distinguished in that an adhesive  22  is applied between the semiconductor chip  11  and the plastic sealing layer  17 , such that the adhesive  22  serves to prevent the semiconductor chip  11  from being warped or bent. Specifically, the adhesive  22  is made of polyimide resin. In FIGS. 4A and 4B, the entire bottom side of the semiconductor chip  11  is coated with the polyimide resin  22  to avoid exfoliation of the semiconductor chip  11  from the plastic sealing layer  17 . In this way, even if there occurs a warpage in the plastic sealing layer  17 , the adhesion between the semiconductor chip  11  and the plastic sealing layer  17  obtained by the polyimide resin  22  prevents exfoliation of the semiconductor  11  from the plastic sealing layer  17 . Consequently, this prevents cracks from occurring in the bottom side of the semiconductor chip  11 .  
         [0058]    FIGS.  5 A- 5 D show examples of the coating patterns of the polyimide resin  22 . In FIG. 5A, the polyimide resin  22  is coated in the lateral direction of the semiconductor chip  11 . Specifically, the polyimide resin  22  is applied in the lateral direction symmetrically with respect to the lateral axis of the semiconductor chip  11 . In FIG. 5B, the polyimide resin  22  is applied in the longitudinal direction symmetrically with respect to the longitudinal axis of the semiconductor chip  11 .  
         [0059]    In FIGS. 5C and 5D, the polyimide resin  22  includes a plurality of polyimide resin portions. In FIG. 5C, the plurality of polyimide resin portions are in parallel with each other in the lateral direction of the semiconductor chip  11 . Similarly, in FIG. 5D, the plurality of polyimide resin portions are in parallel with each other in the longitudinal direction of the semiconductor chip  11 . All the coating patterns of the polyimide resin  22  ensure the adhesion of the semiconductor chip  11  and the plastic sealing layer  17 , thus preventing exfoliation of the semiconductor chip  11  that cause a crack in the semiconductor chip  11  or in the plastic sealing layer  17 .  
         [0060]    Fourth Embodiment  
         [0061]    The fourth embodiment of the semiconductor device according to the present invention will now be described in detail.  
         [0062]    [0062]FIG. 6A is a cross sectional view of the semiconductor device of the fourth embodiment, and FIG. 6B shows the bottom side of the semiconductor chip mounted in the semiconductor device. The components of the semiconductor device according to the fourth embodiment are almost the same as those of the semiconductor device according to the third embodiment; therefore, the following explanation will focus on the distinguishing feature of the fourth embodiment. The distinguishing feature of this embodiment is that a polyimide tape is pasted or stuck onto the semiconductor chip. More specifically, the polyimide tape  23  is stuck on the entire bottom side of the semiconductor chip  11  to make the semiconductor chip  11  adhere to the plastic sealing layer  17 . This prevents exfoliation of the semiconductor chip  11  from the plastic sealing layer  17 , thus preventing cracks from occurring in the plastic sealing layer  17 .. The polyimide tape  23  is preferably stuck on the entire bottom side  11 B of the semiconductor chip  11 , as shown in FIG. 6B. However, the polyimide tape  23  may be stuck to a part of the bottom side  11 B, as shown in FIGS. 5A and 5B analogously for the case of the above polyimide resin. That is, the polyimide tape  23  may be pasted in the lateral direction symmetrically with respect to the lateral axis of the semiconductor chip  11 , and may be pasted in the longitudinal direction symmetrically with respect to the longitudinal axis thereof.  
         [0063]    Further, the polyimide tape  23  may include a plurality of polyimide tape portions. These polyimide tape portions may be pasted in parallel with each other in the lateral direction of the semiconductor chip  11  as shown in FIG. 5C or in the longitudinal direction of the semiconductor chip  11  as shown in FIG. 5D. All these patterns of the polyimide tape  23  enable the semiconductor chip  11  and the plastic sealing layer  17  to adhere securely to each other, which prevents the exfoliation of the semiconductor chip  11  from the plastic sealing layer  17  so as to prevent the occurrence of cracks in the semiconductor chip  11  or in the plastic sealing layer  17 .  
         [0064]    Fifth Embodiment  
         [0065]    The fifth embodiment of the semiconductor device according to the present invention will now be described in detail.  
         [0066]    [0066]FIG. 7A is a cross sectional view of the fifth embodiment of the semiconductor device, and FIG. 7B shows the bottom of the semiconductor chip mounted in the semiconductor device of FIG. 7B. Like the fourth embodiment, the components of the fifth embodiment are almost the same as those of the third embodiment; therefore, the following discussion will focus on the distinguishing feature of the fifth embodiment. The distinguishing feature of the fifth embodiment is that a polyimide pad is fixed or attached to the semiconductor chip. More specifically, as shown in FIGS. 7A and 7B, the polyimide pad  24  is fixed on the bottom side of the semiconductor chip  11  using a metallic adhesive or a metallic paste  25  to achieve adhesion between the semiconductor chip  11  and the plastic sealing layer  17 . The polyimide pad  24  is, for example, made of glass epoxy resin. The adhesion of the semiconductor chip  11  to the plastic sealing layer  17  prevents exfoliation of the semiconductor chip  11  from the plastic sealing layer  17 , thereby preventing the occurrence of cracks in the semiconductor chip  11  or in the plastic sealing layer  17 .  
         [0067]    In FIG. 7B, the polyimide pad  24  is fixed on the entire bottom of the semiconductor chip  11 ; however, the polyimide pad  24  may be fixed on a part of the bottom of the semiconductor chip  11  analogously to the structures of FIGS.  5 A- 5 D. Specifically, the polyimide pad  24  may be fixed in the lateral direction symmetrically with respect to the lateral axis of the semiconductor chip  11  as shown in FIG. 5A while it may be fixed in the longitudinal direction symmetrically with respect to the longitudinal axis of the semiconductor chip  11  as show in FIG. 5B. In addition, the polyimide pad  24  may include a plurality of polyimide pad portions. The plurality of polyimide pad portions may be arranged in parallel with each other in the lateral direction of the semiconductor chip  11  as shown in FIG. 5C, and they may be arranged in parallel with each other in the longitudinal direction of the semiconductor chip  11  as shown in FIG. 5D. These structures can provide the same effect as when the polyimide pad  24  covers the entirety of the bottom of the semiconductor chip  11 .  
         [0068]    The first through fifth embodiments explained above discuss the application of the present invention to the LOC semiconductor device; however, the present invention can also be applied to, for example, the SOJ (Small Outline J-Leaded Package) semiconductor device or the SOP (Small Outline Package) semiconductor device.  
         [0069]    Although the present invention has been described by way of exemplary embodiments, it should be understood that many changes and substitutions may be made by those skilled in the art without departing from the spirit and the scope of the present invention which is defined only by the appended claims.