Abstract:
With the objective of reducing current consumption of a regulator circuit per se, switches for performing on/off of an operating current are inserted in series with transistors of a reference voltage generating unit and a differential amplifying unit that constitute the regulator circuit. A switch for turning on/off an electrical connection between the reference voltage generating unit and the differential amplifying unit is provided. These switches are periodically on/off-controlled in accordance with a clock signal. Incidentally, when the timing provided to turn on the switch is made faster than the timings provided to turn on the remaining switches, the operation of the differential amplifying unit can be further stabilized.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to a regulator circuit which supplies a predetermined source voltage to a logic circuit or the like, and particularly to a reduction in power consumption. 
         [0002]      FIG. 2  is a configuration diagram of a conventional regulator circuit. 
         [0003]    The regulator circuit generates a constant voltage VREG from a source potential VDD and supplies the same to a logic block  40 . The regulator circuit has a reference voltage generating unit  10 , a differential amplifying unit  20  and a bias voltage generating unit  30 . 
         [0004]    The reference voltage generating unit  10  comprises a P channel MOS transistor (hereinafter called “PMOS”)  11  connected between the source potential VDD and a node N 1 , and a PMOS  12  and an N channel MOS transistor (hereinafter called “NMOS”)  13  diode-connected in the forward direction and series-connected between the node N 1  and a ground potential GND. The gate of the PMOS  11  is supplied with a bias voltage VBa from the bias voltage generating unit  30  and a reference voltage VREF is outputted from the node N 1 . 
         [0005]    The differential amplifying unit  20  has NMOSs  21   a  and  21   b  whose gates are supplied with the reference voltage VREF and an adjusted or regulated voltage VREG respectively. The drains of the NMOSs  21   a  and  21   b  are respectively connected to the source potential VDD through PMOSs  22   a  and  22   b . The sources thereof are commonly connected to a node N 2 . The node N 2  is connected to the ground potential GND through an NMOS  23 . The gates of the PMOSs  22   a  and  22   b  are connected to the drain of the NMOS  21   b , and the drain of the NMOS  21   a  is connected to the gate of a PMOS  24 . 
         [0006]    The source and drain of the PMOS  24  are respectively connected to the source potential VDD and a node N 3 . The drain of an NMOS  25  is connected to the node N 3 , and the source thereof is connected to the ground potential GND. The gates of the NMOSs  23  and  25  are supplied with a bias voltage VBb from the bias voltage generating unit  30  so that a regulated voltage VREG is outputted from the node N 3 , followed by being supplied to the logic block  40 . 
         [0007]    Incidentally, the regulator circuit is used with an external stabilization capacitor  41  corresponding to the maximum load current of the logic block  40  being connected between the node N 3  and the ground potential GND in addition to the logic block  40 . 
         [0008]    In the regulator circuit, a predetermined constant current flows through the PMOS  11  of the reference voltage generating unit  10  and the NMOSs  23  and  25  of the differential amplifying unit  20  according to the bias voltages VBa and VBb supplied from the bias voltage generating unit  30 . Thus, a reference voltage VREF occurs in the node N 1  of the reference voltage generating unit  10 . The reference voltage VREF is supplied to the voltage-follower connected differential amplifying unit  20 , and a voltage VREG regulated so as to assume the same potential as the reference voltage VREF is outputted from the node N 3  corresponding to an output terminal of the differential amplifying unit  20 . The voltage VREG is applied across the smoothing stabilization capacitor  41  and supplied to the logic block  40  as a source voltage. 
         [0009]    The above related art refers to a patent document 1 (Japanese Unexamined Patent Publication No. 2002-268758). 
         [0010]    In the regulator circuit, however, the constant current always flows through the PMOS  11  of the reference voltage generating unit  10  and the NMOSs  23  and  25  of the differential amplifying unit  20  according to the bias voltages VBa and VBb regardless of the load current that flows through the logic block  40 . Therefore, it has interfered with a reduction in power consumption in a microminiaturized portable device such as a clock. 
       SUMMARY OF THE INVENTION 
       [0011]    With the foregoing in view, it is therefore an object of the present invention to reduce current consumption of a regulator circuit per se. 
         [0012]    According to one aspect of the present invention, for attaining the above object, there is provided a regulator circuit comprising a reference voltage generating unit which allows a constant current to flow from a source potential to a ground potential thereby to generate a reference voltage at an internal node, a differential amplifying unit which differential-amplifies the reference voltage of the internal node and an output voltage of an output node thereby to output the same voltage as the reference voltage to the output node, first switch means which on/off-controls a flow of the constant current of the reference voltage generating unit in accordance with a clock signal, second switch means which on/off-controls an amplifying operation of the differential amplifying unit with the same timing as the reference voltage generating unit, and third switch means which on/off-controls a connection between the internal node and the differential amplifying unit with the same timing as the second switch means. 
         [0013]    The present invention includes switch means which periodically on/off-controls operations of a reference voltage generating unit and a differential amplifying unit in accordance with a clock signal. Thus, the present invention brings about the effect that current consumption of a regulator circuit itself can be reduced. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: 
           [0015]      FIG. 1  is a configuration diagram of a regulator circuit showing a first embodiment of the present invention; 
           [0016]      FIG. 2  is a configuration diagram of a conventional regulator circuit; 
           [0017]      FIG. 3  is a configuration diagram of a regulator circuit showing a second embodiment of the present invention; and 
           [0018]      FIG. 4  is a signal waveform diagram showing operations of  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]    Constituting switch means so as to control the operation of a reference voltage generating unit in accordance with a clock signal and to start an amplifying operation of a differential amplifying unit with being delayed from the reference voltage generating unit and stop the operation simultaneously with the reference voltage generating unit makes it possible to stabilize the amplifying operation of the differential amplifying unit and further stabilize the voltage of an output node. 
         [0020]    The above and other objects and novel features of the present invention will become more completely apparent from the following descriptions of preferred embodiments when the same is read with reference to the accompanying drawings. The drawings, however, are for the purpose of illustration only and by no means limitative of the invention. 
       First Preferred Embodiment 
       [0021]      FIG. 1  is a configuration diagram of a regulator circuit showing a first embodiment of the present invention. Constituent elements common to those shown in  FIG. 2  are given common reference numerals respectively. 
         [0022]    The regulator circuit is used in, for example, a clock LSI (Large Scale Integration) or the like. The regulator circuit generates a predetermined voltage VREG from a source potential VDD and supplies the same to a logic block  40 . The regulator circuit has a reference voltage generating unit  10 A, a differential amplifying unit  20 A, a bias voltage generating unit  30  and inverters  31  and  32 . 
         [0023]    In the reference voltage generating unit  10 A, a switch  14  (first switch means) constituted of a PMOS is inserted between the drain side of the PMOS  11  of the reference voltage generator  10  shown in  FIG. 2  and the node N 1 . Further, a transfer gate type switch  15  (third switch means) constituted of a PMOS  15   p  and an NMOS  15   n  is provided between the node N 1  and the differential amplifying unit  20 A. 
         [0024]    That is, the reference voltage generating unit  10 A comprises the PMOS  11  and switch  14  connected in series between the source potential VDD and the node N 1 , a PMOS  12  and an NMOS  13  diode-connected in the forward direction and series-connected between the node N 1  and a ground potential GND, and the switch  15  of which one end is connected to the node N 1  and the other end is connected to the gate of an NMOS  21   a  of the differential amplifying unit  20 A. 
         [0025]    The gate of the PMOS  11  is supplied with a bias voltage VBa from the bias voltage generating unit  30 . The gates of the PMOSs that constitute the switches  14  and  15  are supplied with a signal S 1  generated by inverting a clock signal CLK by the inverter  31 . The gate of the NMOS that constitutes the switch  15  is supplied with a signal S 2  generated by further inverting the signal S 1  by the inverter  32 . A reference clock signal (e.g., 32.768 kHz) for a clock generated within the logic block  40  is used as for the clock signal CLK. When the switches  14  and  15  are turned on, a reference voltage VREF is outputted from the switch  15 . Incidentally, the switch  14  is inserted into the drain side of the PMOS  11  in such a manner that the PMOS  11  is supplied with the normal bias voltage VBa. 
         [0026]    The differential amplifying unit  20 A is equivalent to one provided with switches  27  through  29  (second switch means) for on/off-controlling the amplifying operation of the differential amplifying unit  20  shown in  FIG. 2  in accordance with the clock signal CLK. 
         [0027]    That is, the differential amplifying unit  20 A has NMOSs  21   a  and  21   b  of which the gates are respectively supplied with the reference voltage VREF and the adjusted or regulated voltage VREG through the switch  15 . The drains of the NMOSs  21   a  and  21   b  are connected to the source potential VDD through the PMOSs  22   a  and  22   b , whereas the sources thereof are commonly connected to a node N 2 . The node N 2  is connected to the ground potential GND through a switch  27  constituted to an NMOS and an NMOS  23 . The gates of the PMOSs  22   a  and  22   b  are connected to the drain of the NMOS  21   b , and the drain of the NMOS  21   a  is connected to the gate of the PMOS  24 . 
         [0028]    The source and drain of the PMOS  24  are respectively connected to the source potential VDD and a node N 3 , whereas the gate thereof is connected to the source potential VDD through a switch  29  constituted of a PMOS. The drain of an NMOS  25  is connected to the node N 3  through a switch  28  constituted of an NMOS, whereas the source thereof is connected to the ground potential GND. 
         [0029]    The gates of the NMOSs that constitute the switches  27  and  28 , and the gate of the PMOS that constitutes the switch  29  are supplied with the signal S 2 . A bias voltage VBb is supplied from the bias voltage generating unit  30  to the gates of the NMOSs  23  and  25 , and the regulated voltage VREG is outputted from the node N 3  and supplied to the logic block  40 . Incidentally, the switches  27  and  28  are inserted into the drain sides of the NMOSs  23  and  25  in such a manner that the normal bias voltage VBb is supplied to the NMOSs  23  and  25 . 
         [0030]    The regulator circuit is used with an external stabilization capacitor  41  corresponding to the maximum load current of the logic block  40  being connected between the node N 3  and the ground potential GND in addition to the logic block  40 . 
         [0031]    The operation of the regulator circuit will next be explained. 
         [0032]    When the clock signal CLK is “H”, the signals S 1  and S 2  go “L” and “H” respectively, so that the switches  14 ,  15 ,  27  and  28  are turned on and the switch  29  is turned off. Thus, in the regulator circuit, a predetermined constant current flows through the PMOS  11  of the reference voltage generating unit  10 A and the NMOSs  23  and  25  of the differential amplifying unit  20 A according to bias voltages VBa and VBb supplied from the bias voltage generating unit  30 . Thus, a reference voltage VREF occurs in the node N 1  of the reference voltage generating unit  10 A. The reference voltage VREF is supplied to the voltage-follower connected differential amplifying unit  20 A, and a voltage VREG regulated so as to assume the same potential as the reference voltage VREF is outputted from the node N 3  corresponding to an output terminal of the differential amplifying unit  20 A. The voltage VREG is applied across the smoothing stabilization capacitor  41  to charge the stabilization capacitor  41  to the voltage VREG. Further, the voltage VREG is supplied to the logic block  40  as a source voltage. 
         [0033]    On the other hand, when the clock signal CLK is “L”, the signals S 1  and S 2  are respectively brought to “H” and “L”, so that the switches  14 ,  15 ,  27  and  28  are turned off and the switch  29  is turned on. Thus, all of the currents flowing through the transistors of the reference voltage generating unit  10 A and the differential amplifying unit  20 A are brought into zero so that the operations thereof are stopped, thereby bringing the node N 3  into a high impedance state. Accordingly, the current for the logic block  40  is supplied from the external stabilization capacitor  41 . 
         [0034]    Thus, the reference voltage generating unit  10 A and the differential amplifying unit  20 A alternately repeat their operations and stops in accordance with the clock signal CLK. Since no current flows through these circuits during the period in which the reference voltage generating unit  10 A and the differential amplifying unit  20 A are being deactivated, there is an advantage that the average current consumption of the regulator circuit per se can be reduced. 
         [0035]    Assuming that an operating current that flows through each of the reference voltage generating unit  10 A and the differential amplifying unit  20 A is  100  nA, for example, the average current consumption reaches 50 nA if the duty of the clock signal CLK is defined as 50%. If the duty is defined as 20%, then the average current consumption becomes 20 nA. Since, however, the current for the logic block  40  is supplied from the external stabilization capacitor  41  during the period in which the reference voltage generating unit  10 A and the differential amplifying unit  20 A are being deactivated, the value of the stabilization capacitor  41  needs to be set to a sufficiently larger value (e.g. 0.1 to 0.33 μF) in consideration of the current consumption of the logic block  40 . 
       Second Preferred Embodiment 
       [0036]      FIG. 3  is a configuration diagram of a regulator circuit showing a second embodiment of the present invention. Constituent elements common to those shown in  FIG. 1  are given common reference numerals respectively. 
         [0037]    In the present regulator circuit, timings provided for control signals supplied to switches  14 ,  15  and  27  through  29  are slightly changed as compared with  FIG. 1 . That is, the present regulator circuit includes, in addition to an inverter  31  for generating a signal S 1  obtained by inverting a clock signal CLK, an integration circuit constituted of a resistor  33  and a capacitor  34  for generating a signal S 3  obtained by delaying the signal S 1 , for example, 100 μs or so, a NOR gate  35  which outputs the negative ORing of the signals S 1  and  53  as a signal S 4 , and an inverter  36  which inverts the signal S 4  and outputs a signal S 5 . Then, the signal S 1  is supplied to the switch  14 , the complementary signals S 4  and S 5  are supplied to the switch  15 , and the signal S 4  is supplied to the switches  27  through  29 . 
         [0038]      FIG. 4  is a signal waveform diagram showing operations of  FIG. 3 . The operations shown in  FIG. 3  will be explained below with reference to  FIG. 4 . 
         [0039]    When the clock signal CLK is “L”, the signal S 1  is “H” and the signal S 3  is brought to “H” in a stable state. The signals S 4  and S 5  go “L” and “H” respectively. Thus, the switches  14 ,  15 ,  27  and  28  are off and the switch  29  is on. Hence, currents flowing through transistors of a reference voltage generating unit  10 A and a differential amplifying unit  20 A are all brought to zero so that their operations are stopped, thereby bringing a node N 3  to a high impedance state. Accordingly, the current for a logic block  40  is supplied from an external stabilization capacitor  41 . 
         [0040]    Next, when the clock signal CLK rises from “L” to “H”, the signal S 1  immediately changes to “L” so that the switch  14  is turned on. On the other hand, the signal S 3  is held in a state of “H” for a while because an integration circuit is provided. Accordingly, the signal S 4  is also held in a state of “L” for a while. Thus, only the reference voltage generating unit  10 A starts operating and the differential amplifying unit  20 A remains deactivated. A reference voltage VREF is outputted to a node N 1  by the operation of the reference voltage generating unit  10 A. 
         [0041]    When the clock signal CLK rises and a time of 100 μs or so has elapsed, the signal S 3  corresponding to the output of the integration circuit is brought to “L”. Thus, the signals S 4  and S 5  are brought to “H” and “L” respectively, so the switches  14 ,  15 ,  27  and  28  are turned on and the switch  29  is turned off. Thus, the differential amplifying unit  20 A starts operating and hence the reference voltage VREF of the node N 1  generated at the reference voltage generating unit  10 A is supplied to the differential amplifying unit  20 A. A voltage VREG adjusted so as to assume the same potential as the reference voltage VREF is outputted from a node N 3  corresponding to an output terminal of the differential amplifying unit  20 A. The voltage VREG is applied to the smoothing stabilization capacitor  41  to charge the stabilization capacitor  41  to the voltage VREG. Further, the voltage VREG is supplied to the logic block  40  as a source voltage. 
         [0042]    Thereafter, when the clock signal CLK falls to “L”, the signal S 1  is brought to “H”, the signal S 4  reaches “L” and the signal S 5  goes “H”. Thus, the reference voltage generating unit  10 A and the differential amplifying unit  20 A are deactivated so that the node N 3  is brought into a high impedance state, whereby the current for the logic block  40  is supplied from the external stabilization capacitor  41 . This operation is repeated in accordance with the clock signal CLK. 
         [0043]    As described above, the regulator circuit according to the second embodiment has a timing circuit (including an integration circuit constituted of a resistor  33  and a capacitor  34 , and a NOR gate  35  which outputs the negative ORing of the signals S 1  and S 3  as the signal S 4 ) for firstly allowing the reference voltage generating unit  10 A to start its operation when it starts operating from a halt condition, thereby generating the reference voltage VREF at the node N 1  and thereafter allowing the differential amplifying unit  20 A to start its operation. Thus, the regulator circuit has the advantage of being capable of lessening a reduction in the level of the voltage VREG and outputting a stabler voltage VREG in addition to an advantage similar to the first embodiment since the reference voltage VREF can immediately be supplied to the differential amplifying unit  20 A when the operation of the differential amplifying unit  20 A is started. 
         [0044]    Incidentally, the present invention is not limited to the above embodiments. Various modifications can be made thereto. For example, the configuration of each of the reference voltage generating unit  10 A, the differential amplifying unit  20 A and the timing circuit for controlling the switches can be substituted with another circuit configuration having similar functions.