Abstract:
A voltage controlled oscillator comprises a tank circuit for determining an oscillation frequency, a first circuit for delaying the signal having the oscillation frequency, a second circuit for advancing the signal having the oscillation frequency, the first and second circuit being connected in series, a third circuit interposed between the tank circuit and the series connection of the first and second circuits, the third circuit having the same equivalent circuit of the series connection, a first gain controlled amplifier amplifying the output from the first circuit, a second gain controlled amplifier amplifying the output from the second circuit, an adder for adding outputs from the first and second gain controlled amplifiers, a control circuit controlling the gains of the first and second gain controlled amplifiers, and a feed-back circuit for feeding the output of the adder to the tank circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention: 
     This invention relates to a voltage controlled oscillator, and more particularly to that having an oscillation frequency free from variation in resistance used therein. 
     2. Description of the Prior Art: 
     The voltage controlled oscillator is widely used in PLL (Phase Locked Loop) circuits and so on formed in a semiconductor integrated circuit. The PLL circuit has a wide application such as an FM stereo multiplexer. In the FM stereo multiplexer, a frequency signal of about 76 KHz is generated from a voltage controlled oscillator and is divided to provide a frequency signal of about 19 KHz, the phase of which is compared with a pilot signal of 19 KHz in an FM composite signal. The result of the comparison is derived as a form of voltage which is fed to the voltage controlled oscillator to control the oscillator to exactly oscillate with 76 KHz. 
     The voltage controlled oscillator in the prior art is composed of a C-R time constant circuit charged by a controlled current, a differential amplifier having a first input point receiving the voltage from the C-R time constant circuit, a second input point and a load of current mirror circuit, a first transistor receiving the output signal from the current mirror circuit at its base and feeding its collector output to the first input point of the differential amplifier, and a second transistor receiving the output signal from the current mirror circuit at its base and feeding its collector output to the second input point of the differential amplifier through a voltage divider of resistors. In a semiconductor integrated circuit, all the circuit elements except for the C-R time constant circuit are formed on a semiconductor chip. Especially, the resistances of the resistors in the voltage divider are sensitive to the change in manufacturing condition of the integrated circuit. The variation of the resistances affect the oscillation frequency of the voltage controlled oscillator in the prior art. Thus, the voltage controlled oscillator in the prior art has a drawback that a stable oscillation frequency irrespective of the manufacturing condition cannot be obtained if it is formed in a semiconductor integrated circuit. 
     SUMMARY OF THE INVENTION 
     The primary object of the invention is to provide a voltage controlled oscillator suited for being formed in a semiconductor integrated circuit, and more particularly to provide a voltage controlled oscillator having an oscillation frequency which is not affected from the variation of manufacturing condition. 
     According to the present invention, there is provided a voltage controlled oscillator comprising a tank circuit for determing an oscillation frequency, a first circuit for delaying the phase of the signal having the oscillation frequency, a second circuit for advancing the phase of the signal having the oscillation frequency, the first and second circuits being connected in series, a third circuit interposed between the tank circuit and the series connection of the first and second circuits, the third circuit having the same equivalent circuit as the series connection, a first gain controlled amplifier for amplifying the output from the first circuit, a second gain controlled amplifier for amplifying the output from the second circuit, a means for controlling the gains of the first and second gain controlled amplifiers, an adder for adding the output signals from the first and second gain controlled amplifiers, a means for deriving an output signal from the adder and a means for feeding the output signal of the adder to the tank circuit to form a positive feed-back loop. 
     The voltage controlled oscillator according to the present invention controls the oscillation frequency of the tank circuit by controlling the gains of the gain controlled amplifiers. More specifically, by controlling the gains of the gain controlled amplifiers, the phase of the output signal from the adder is changed. The phase controlled output signal is applied to the tank circuit. The oscillation frequency of the tank circuit changes by the phase of the output signal applied thereto. 
     The first circuit is preferably a resistor. The second circuit is preferably a capacitor. The third circuit is preferably a series connection of a resistor having the same resistance of the resistor in the first circuit and a capacitor having the same capacitance of the capacitor in the second circuit. Therefore, all the circuit elements except for the tank circuit are easily formed in a semiconductor integrated circuit. In such case, if the resistances of the resistors and the capacitances of the capacitors are deviated by unstable manufacturing condition, the time delay across the resistor and the time advance across the capacitor are same in absolute value, because the resistor and capacitor are connected in series. Due to this fact, the change in phase of the output signal from the adder only depends on the gains of the gain controlled amplifiers. This results in that the oscillation frequency is not changed by the deviation of the manufacturing condition of the semiconductor integrated circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram showing a voltage controlled oscillator in the prior art; 
     FIG. 2 is a waveform showing an output from the voltage controlled oscillator in the prior art; 
     FIG. 3 is a block diagram showing a preferred embodiment of the present invention; 
     FIG. 4 is a drawing showing the phase relationship between the inputs and output of the adder used in the preferred embodiment; 
     FIG. 5 is a drawing showing a relationship between the phase of the signal applied to the tank circuit and the oscillation frequency of the tank circuit; and 
     FIG. 6 is a circuit diagram showing a concrete example of the preferred embodiment. 
    
    
     The voltage controlled oscillator in the prior art shown in FIG. 1 has a parallel circuit of a variable resistor R 1  and a capacitor C 1 . The capacitor C 1  is charged by a constant current source I 01 , the constant current of which is variable. The variable resistor R 1  and the capacitor C 1  are circuits elements externally connected to a semiconductor integrated circuit at a terminal A. The terminal A is connected to a base of a transistor Q 1  in the integrated circuit. The transistor Q 1  forms a differential amplifier together with a transistor Q 2  and a constant current source I 02 . The collector of the transistor Q 1  is supplied with a stabilized power voltage V s  from a terminal B. The collector of the transistor Q 2  is connected with a collector and base of a transistor Q 7  which forms a current mirror with a transistor Q 8 . An unstabilized voltage V cc  is supplied to the emitters of the transistors Q 7  and Q 8  from a terminal C. The collector of the transistor Q 8  is connected with bases of transistors Q 5  and Q 6  having collectors connected to the terminal B and is supplied with a current from a constant current source I 03 . The emitter of the transistor Q 5  is connected with the base of the transistor Q 1  to form a positive feed-back loop. The emitter of the transistor Q 6  is grounded through resistors R 2  and R 3 . The connecting point of the resistors R 2  and R 3  is directly connected with the base of the transistor Q 2  on one hand and connected with the terminal B through a resistor R 4  on the other hand. 
     The above-explained voltage controlled oscillator oscillates by repeated switching of the transistors Q 1  and Q 2  which is established by the charging and discharging of the capacitor C 1  and the positive feed-back from the emitter of the transistor Q 5  to the base of the transistor Q 1 . More specifically, at the start of oscillation, the capacitor C 1  is not charged to keep the terminal A at ground. The transistor Q 1  is an off state and the transistors Q 2 , Q 7 , Q 8 , Q 5  and Q 6  are an on state. In this condition, the capacitor C 1  is charged from the emitter of the transistor Q 5  to gradually rising the voltage at the terminal A. When the voltage at the terminal A reaches the voltage (V H ) at the connecting point of the resistors R 2  and R 3 , the transistor Q 1  turns on to turn off the other transistors Q 2 , Q 7 , Q 8 , Q 5  and Q 6 . The charges in the capacitor C 1  discharges through the variable resistor R 1  to gradually decrease the voltage at the terminal A. When the voltage at the terminal A falls to the same voltage as the voltage (V L ) at the connecting point of the resistors R 2  and R 3 , the transistor Q 1  turns on again and the other transistors turn off to continue the above-described operation. 
     Thus obtained wave form at the terminal A is shown in FIG. 2. Now, if the constant current from the constant current source I 01  is assumed as &#34;0&#34;, the high and low levels V H  and V L  and the periods t 1  and t 2  (where t 1  is a period of the rising part and t 2  is a period of the falling part) of the output signal at the terminal A are expressed as follows: ##EQU1## where γ 1  to γ 5  are resistances of the resistors R 1  to R 5 , V CEsat  Q 6  is a saturation voltage between collector and base of the transistor Q 6 . 
     Here, if the saturation voltage V CE  sat Q 6  is neglected, the perios t 1  and t 2  can be transformed as follows: ##EQU2## 
     The frequency f OSC  is as follows: ##EQU3## 
     As apparent from the equations (5) to (7), the oscillation frequency f OSC  has parameters of resistances γ 1  to γ 5 . In other words, the oscillation frequency f OSC  is affected from the change of the resistances γ 1  to γ 5 . Such resistances γ 1  γ 5  of the resistors R 1  to R 5  formed in the semiconductor integrated circuit is very sensitive to the variation of manufacturing condition. Therefore, the voltage controlled oscillator in the prior art has a drawback that the oscillation frequency f OSC  deviates by the manufacturing condition of the integrated circuit. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The preferred embodiment of the present invention is shown in the block diagram of FIG. 3. All the circuit elements except for a tank circuit composed of an inductor L O  and a capacitor C O  are formed in a semiconductor integrated circuit. The tank circuit is connected to the integrated circuit at a terminal E. In the integrated circuit, the terminal E is connected to a series circuit 5 of a resistor R 11  and a capacitor C 11 . The other end of the series circuit 5 is grounded through a resistor R 12  operating as a phase delaying circuit 61 and a capacitor C 12  operating as a phase advancing circuit 62. The resistors R 11  and R 12  have the same resistances and the capacitors C 11  and C 12  have the same capacitances. Therefore, the signal V 2  at the other end of the series circuit 5 has just half voltage of the signal at the terminal E and has the same phase as at the terminal E. The series circuit 5 is inserted to prevent the tank circuit from affecting the phase shift values of the phase delaying and advancing circuits 61 and 62. The signal V 3  across the resistor R 12  has a phase delayed from the signal V 2  and the signal V 4  across the capacitor C 12  has a phase advanced from the signal V 2 . The absolute values of the delay of the signal V 3  and the advance of the signal V 4  are same irrespective of the resistance of the resistor R 12  and the capacitance of the capacitor C 12 . Here, the values of the resistances of the resistors R 11 , R 12 , the capacitances of the capacitors C 11 , C 12 , the inductance l O  of the inductor L O  and the capacitance C O  of the capacitor C O  are selected so as to satisfy the equation (8) defined as follows: ##EQU4## 
     The signal V 3  across the resistor R 12  is applied to a gain controlled amplifier 1, while the signal V 4  across the capacitor C 12  is applied to another gain controlled amplifier 2. The gains of the gain controlled amplifiers 1 and 2 are controlled by applying control voltages through a gain control circuit 4 in response to input signal applied to terminals F and G. The output signals V 5  and V 6  from the gain controlled amplifiers 1 and 2 are added by an adder 7. The added output is fed back to the tank circuit of the inductor L O  and the capacitor C O  through an amplifier 3. The oscillation output signal V 7  is derived from the output of the adder through an output terminal H. 
     The tank circuit of the inductor L O  and the capacitor C O  has a characteristic that the oscillation frequency changes from its center frequency f c  to high and low in accordance with the phase difference of the applied signal from the phase of the oscillation signal at the center frequency f c , as shown in FIG. 5. The phase of the signal to be applied to the tank circuit is controlled by the phase delaying circuit 61, the phase advancing circuit 62, the gain controlled amplifiers 1 and 2 and the adder 7. The phase control will be explained with reference to FIG. 4. Now, the gains of the gain controlled amplifiers 1 and 2 are made equally unity. The phase delayed signal V 3  and the phase advanced signal V 4  are added by the adder 7 to produce an outut signal V 2  having an absolute value of a half of and the same phase as the oscillation signal V 1  from the tank circuit. The added signal V 2  is amplified by the amplifier 3 and then applied to the tank circuit to keep an oscillation at the center frequency f c  (see FIG. 5). If the gains of the gain controlled amplifiers 1 and 2 are equal to a gain larger than the unity, the amplified signals V 5  and V 6  are similarly added by the adder 7 to generate an output signal V 7  having the same phase as the oscillation signal V 1 . The output signal V 7  is fed back to the tank circuit through the amplifier 3 to keep the oscillation of the tank circuit at the center frequency f c . Thus, if the gains of the gain controlled amplifiers 1 and 2 are equal, the whole circuit oscillates at the center frequency f c  which can be expressed as ##EQU5## Now, if the gain of the gain controlled amplifier 1 is made larger than that of the gain controlled amplifier 2, the phase delayed signal V&#39; 5  and the phase advanced signal V&#39; 6  are added to produce an output signal V&#39; 7  having a phase φ delayed with a value according to the difference between the gains of the gain controlled amplifiers 1 and 2. The output signal V&#39; 7  is fed back to the tank circuit through the amplifier 3 to oscillate the tank circuit at a frequency f H  higher than the center frequency f c  in accordance with the phase difference (-φ) of the output signal V&#39; 7  from the undelayed phase φ O , as shown in FIG. 5. On the contrary, if the gain of the gain controlled amplifier 2 is made larger than the gain controlled amplifier 1, the phase delayed output V&#34; 5   and the phase advanced output V&#34; 6  are added to produce an output signal V&#34; 7  having a phase +φ advanced with a value according to the difference between the gains of the gain controlled amplifiers 1 and 2. The output signal V&#34; 7  is fed back to the tank circuit through the amplifier 3 to keep the oscillation of the tank circuit at a frequency f L  lower than the center frequency f c  in accordance with the phase difference (+φ) of the output signal V&#34; 7  from the unadvanced phade φ O , as shown in FIG. 5. 
     Thus, the oscillation frequency is controlled by the gains of the gain controlled amplifiers 1 and 2. Here, since the phase delayed value by the resistor R 12  and the phase advanced value by the capacitor C 12  are equal irrespective of the resistance γ 12  and the capacitance C 12 , the oscillation frequency depends on only the gains of the gain controlled amplifiers 1 and 2. If the resistance γ 12  and the capacitance C 12  deviate from the designed value by variation in the manufacturing condition, the deviations do not affect the oscillation frequency. The oscillation signal of the tank circuit is applied to the phase delaying circuit 61 of the resistor R 12  and the phase advancing circuit 62 of the capacitor C 12  through the circuit 5 which is equivalent to a series circuit of the phase delaying and advancing circuits 61 and 62. Therefore, the impedance of the tank circuit does not affect the phase delaying and advancing circuits 61 and 62, to oscillate the whole circuit stably irrespective of the configuration of the tank circuit. Thus, any kind of tank circuit such as the LC resonator and a ceramic filter can be equally applied to the voltage controlled oscillator. 
     Now, a concrete example of the preferred embodiment shown in FIG. 3 will be explained with reference to FIG. 6. All the circuit elements except for a ceramic filter CF as the tank circuit are formed on a single semiconductor chip having a terminal E, a power terminal J, input terminals F and G and a reference terminal (not shown) held at a grounding potential. The terminal E is externally connected with the ceramic filter CF having a resonant frequency of 608 KHz and internally connected with the circuit 5 which is a resistor R 11  having a resistance of 15 kilo-ohms and a capacitor C 11  having a capacitance of 18 pF. The other end of the circuit 5 is connected to a bias circuit 10 through a resistor R 12  of 15 kilo-ohms as a phase delaying circuit and a capacitor C 12  of 18 pF as a phase advancing circuit. A resistor R 13  are connected in parallel with the series connection of the resistor R 12  and the capacitor C 10 . Both ends of the resistor R 12  are respectively connected to bases of the transistors Q 13  and Q 14  having emitters commonly connected. Similarly, both ends of the capacitor C 12  are respectively connected to bases of the transistors Q 15  and Q 14  having emitters commonly connected. The collectors of the transistors Q 13  and Q 15  are connected to a series connection of a resistor R 14  and a diode D 11  as a load. The collectors of the transistors Q 14  and Q 16  are connected to a series connection of a resistor R 15  and a diode D 12  as another load. The common emitters of the transistors Q 13  and Q 14  are connected to a collector of a transistor Q 11  having a base receiving a gain control signal through the input terminal F and the common emitters of the transistor Q 15  and Q 16  are connected to a collector of a transistor Q 12  having a base receiving another gain control signal through the input terminal G. The emitters of the transistors Q 11  and Q 12  are grounded through a current source I 11 . The transistors Q 11  to Q 16  form the gain controlled amplifiers 1 and 2 and the gain control circuit 4 shown in FIG. 3. 
     The outputs obtained across the series connection of the resistor R 14  and the diode D 11  and across the series connection of the resistor R 15  and the diode D 12  are respectively applied to the bases of transistors Q 17  and Q 18  having emitters commonly connected to the power terminal L through a current source I 12 . The collector of the transistor Q 17  is connected to a diode D 13  as a load, while the collector of the transistor Q 18  is connected to a diode D 14  as another load. The diodes D 13  and D 14  are in turn grounded through a series connection of diodes D 15  and D 16 . The transistors Q 17  and Q 18  operate as the adder 7 of FIG. 3. 
     The collectors of the transistors Q 17  and Q 18  are then applied to bases of the transistors Q 20  and Q 19 , respectively. The emitters of the transistors Q 19  and Q 20  are commonly grounded through a current source I 13 . The collectors of the transistors Q 19  and Q 20  are connected to an active load of a current mirror formed with transistors Q 21  and Q 22 . The transistors Q 19  to Q 22  operates as the amplifier 3 of FIG. 3. The output obtained at the collectors of the transistors Q 20  and Q 22  is supplied to the ceramic filter CF through the terminal E and to the circuit 5. 
     As explained above, the voltage controlled oscillator according to the present invention has an oscillation frequency which depends on the gains of the gain controlled amplifiers and does not depend on variations of resistances of the resistor used in the circuit. In other words, the voltage controlled oscillator according to the present invention has an oscillation frequency which is not affected from the manufacturing condition of the integrated circuit and is most suited for being formed in a form of a semiconductor integrated circuit.