Abstract:
In an embodiment, the invention provides a method for characterizing a threshold voltage of a flash memory cell. The method comprises generating a pulse train signal on flash memory IC, applying the pulse train signal to an external low-pass filter, and applying an output of the low-pass filter to the input of an external gain stage. An analog signal from the output of the gain stage is directed to a control gate of the flash memory cell. An electrical parameter of the flash memory cell is measured by an external tester.

Description:
BACKGROUND  
       [0001]    External reference components are often used to calibrate the performance of an individual circuit on an integrated circuit (IC). These components include but are not limited to passive components such as resistors, capacitors, and inductors. These components also include but are not limited to active components such as op-amps, voltage regulators, current regulators, and precession voltage references. The number of external reference components used to characterize individual circuits on an IC often adds to the cost of producing ICs, components, electrical boards, and computer systems. One method used to reduce the cost of producing ICs is to reduce the number of external reference components used to calibrate or test ICs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0002]      FIG. 1  is a schematic diagram of a side cutaway view of an embodiment of a flash memory cell. 
           [0003]      FIG. 2  is a block diagram of an exemplary embodiment of an IC, a tester, and an analog voltage reference. 
           [0004]      FIG. 3A  is a schematic drawing of a first exemplary embodiment of a low-pass filter. 
           [0005]      FIG. 3B  is a schematic drawing of a second exemplary embodiment of a low-pass filter. 
           [0006]      FIG. 4  is a schematic drawing of an embodiment of a gain stage. 
           [0007]      FIG. 5  is a block diagram of an exemplary embodiment of an IC, a tester, and analog voltage references. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    In a first embodiment of the invention, an analog voltage reference is used to generate an analog signal for measuring the V T  (threshold voltage) of a flash memory cell. The analog voltage reference in this example replaces more complex and costly precession voltage references. As will be described in more detail, the analog voltage reference receives a PWM (Pulse Width Modulated) signal from a pulse train generator on a flash memory IC. The pulse train generator is controlled by a CPU (Central Processing Unit). After receiving the PWM signal, the analog voltage reference generates an analog voltage that is applied to test logic on the flash memory IC. Test logic on the flash memory IC applies the analog voltage generated by the analog voltage reference to a gate of a flash memory cell. A digital output signal based on either a current or a voltage generated by the flash memory cell is sent to an external tester. The digital output signal, in this example, is controlled by the CPU. 
         [0009]    Flash memory stores information in an array of memory cells made from floating-gate transistors. In traditional single-level cell (SLC) devices, each cell stores only one bit of information. Some flash memory, known as multi-level cell (MLC) devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells. 
         [0010]      FIG. 1  is a schematic diagram of a side cutaway view of an embodiment of a flash memory cell. In NOR-gate flash memory, each flash memory cell ( 100 ) resembles a standard MOSFET (metal-oxide semiconductor field-effect transistor) except the transistor has two gates instead of one. On top is the control gate ( 102 ), as in other MOS (metal-oxide semiconductor) transistors, however below the control gate ( 102 ) there is a floating gate ( 104 ) insulated by an oxide layer ( 110 ). The floating gate ( 104 ) is interposed between the control gate ( 102 ) and the MOSFET channel ( 112 ). 
         [0011]    Because the floating gate ( 104 ) is electrically isolated by the oxide layer ( 110 ), any electrons placed on the floating gate ( 104 ) are trapped on the floating gate ( 104 ). Under normal conditions, the floating gate ( 104 ) will not discharge for many years. When the floating gate ( 104 ) retains charge, it screens (partially cancels) the electric field from the control gate ( 102 ), which modifies the V T  of the cell. During read-out, a voltage is applied to the control gate ( 102 ), and the MOSFET channel ( 112 ) will become conducting or remain insulating, depending on the V T  of the cell, which is in turn controlled by charge on the floating gate ( 104 ). 
         [0012]    If the MOSFET channel ( 112 ) becomes conducting, current flows through the MOSFET channel ( 112 ) from the drain ( 106 ) to the source ( 108 ). The absence or the presence of current flowing through the MOSFET channel ( 112 ) may be sensed forming a binary code wherein stored data may be reproduced. 
         [0013]    In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the floating gate ( 104 ). 
         [0014]      FIG. 2  is a block diagram of an exemplary embodiment of an IC, a tester, and an analog voltage reference. A pulse train generator ( 202 ), internal to an integrated circuit ( 200 ) generates a pulse train signal ( 232 ). A CPU ( 244 ) controls the pulse train signal ( 232 ) through a control signal  246 . The pulse train signal ( 232 ) generated may, for example, be a PWM (Pulse lo Width Modulated) signal. The pulse train signal ( 232 ) is connected to the input ( 208 ) of a low-pass filter ( 206 ). The low-pass filter ( 206 ) is external to the IC ( 200 ). The low-pass filter ( 206 ) removes high-frequency components in the pulse train signal ( 232 ). A low-pass filter ( 206 ) may be created in a number of ways as shown below. 
         [0015]    In  FIG. 2 , the low-pass filter ( 206 ) is connected to a gain stage ( 212 ). The gain stage ( 212 ) is external to the IC ( 200 ). The gain stage ( 212 ) increases the voltage ( 234 ) received from the output ( 210 ) of the low-pass filter ( 206 ). The gain stage ( 212 ) creates an analog signal ( 236 ) at its output ( 216 ). The gain stage ( 212 ) may, for example, be created using an op-amp and two resistors as shown below. The combination of the low-pass filter ( 206 ) and the gain stage ( 21 ) creates an analog voltage reference ( 242 ). 
         [0016]    The analog signal ( 236 ) is connected to an input ( 220 ) of test logic ( 218 ). The test logic ( 218 ) is internal to the IC ( 200 ). An output ( 222 ) of the test logic connects the analog signal ( 236 ) to an input ( 226 ) of at least one circuit in the plurality of circuits ( 224 ). The plurality of circuits may, for example, be flash memory cells of a flash memory IC. In addition, the plurality of circuits may, for example, be ADCs (Analog-to-Digital Converters). These two examples are discussed in more detail below. 
         [0017]    An output ( 228 ) from the plurality of circuits ( 224 ) is connected to an external tester ( 230 ). The external tester ( 230 ), for example, receives a digital output signal ( 240 ) based on either a current or a voltage generated by a flash memory cell. The digital output signal ( 240 ) is controlled by the CPU ( 244 ) through signal  248 . The external tester ( 230 ) may also receive a digital output signal ( 240 ) based on either a current or a voltage generated by an ADC. 
         [0018]      FIG. 3A  shows a schematic drawing of a first exemplary embodiment of a low-pass filter ( 300 ). The input ( 304 ) of the low-pass filter ( 300 ) is connected to a first node of resistor R 1 . A second node ( 308 ) of resistor R 1  is connected to a first node of capacitor C 1  and a first node of resistor R 2 . A second node of capacitor C 1  is connected to ground. A second node of resistor R 2  is connected to a first node of capacitor C 2  and the output ( 318 ) of the low-pass filter ( 300 ). A second node of capacitor C 2  is connected to ground. 
         [0019]      FIG. 3B  shows a schematic drawing of a second exemplary embodiment of a low-pass filter ( 302 ). The input ( 320 ) of the low-pass filter ( 302 ) is connected to a first node of inductor L 1 . A second node ( 324 ) of inductor L 1  is connected to a first node of capacitor C 1  and a first node of inductor L 2 . A second node of capacitor C 1  is connected to ground. A second node of inductor L 2  is connected to a first node of capacitor C 2  and the output ( 332 ) of the low pass filter ( 302 ). A second node of capacitor C 2  is connected to ground. 
         [0020]    Other types of low-pass filters may be used such as first order, second order, third order, and fourth order low-pass filters. 
         [0021]      FIG. 4  shows a schematic drawing of a gain stage ( 400 ). The gain stage ( 400 ) in  FIG. 4  includes an op-amp ( 408 ) and two resistors, R 1  and R 2 . The op-amp ( 408 ) includes a positive input ( 402 ), a negative input ( 406 ), and an output ( 404 ). A first node of the first resistor R 1 , the negative input ( 406 ) of the op-amp ( 408 ), and a first node of the second resistor R 2  are connected to node  410 . A second node of the first resistor R 1  is connected to ground. The second node of the second resistor R 2  and the output ( 404 ) of the op-amp ( 408 ) are connected at V OUT . The input (V IN ) of the gain stage ( 400 ) is connected to the positive input ( 402 ) of the op-amp ( 408 ). The gain (V OUT V IN ) of the gain stage ( 400 ) is determined as follows: 
         [0000]        V   OUT   /V   IN =1+( R 2/ R 1) 
         [0022]    In a first embodiment of the invention, the integrated circuit ( 200 ) is a flash memory integrated circuit and the plurality of circuits ( 224 ) contains at least flash memory cells. The pulse train generator ( 202 ), located on the flash memory IC ( 200 ), generates a pulse train signal ( 232 ). The pulse train signal ( 232 ) is controlled by a signal ( 246 ) from a CPU ( 244 ). In this exemplary embodiment, the pulse train signal ( 232 ) is a PWM signal. The duty cycle of the PWM signal may be varied in order to create a specific analog value at the output ( 210 ) of the low-pass filter ( 206 ). The amplitude of the PWM signal may also be varied in order to create a specific analog value at the output ( 210 ) of the low-pass filter ( 206 ). The control of the PWM signal is not limited to controlling the duty cycle or the amplitude of the PWM signal. 
         [0023]    In the first embodiment of the invention, the output ( 210 ) of the external low-pass filter ( 206 ) is connected to the input ( 214 ) of the external gain stage ( 212 ). The output voltage ( 216 ) is determined by the gain of the external gain stage ( 212 ). The analog signal ( 236 ) created by the external gain stage ( 212 ) is connected to the input ( 220 ) of the test logic ( 218 ). The test logic ( 218 ) located on the flash memory IC ( 200 ) applies the analog signal lo ( 236 ) to a gate ( 102 ) of a flash memory cell ( 100 ). 
         [0024]    An output ( 228 ) from the plurality of circuits ( 224 ) is connected to an external tester ( 230 ). The external tester ( 230 ), for example, receives a digital output signal ( 240 ) based on either current or voltage generated by one or more flash memory cells. The digital output signal ( 240 ) is controlled by a signal  248  from the CPU ( 244 ). 
         [0025]    In a second embodiment of the invention, the plurality of circuits ( 224 ) contains at least ADCs. The pulse train generator ( 202 ), located on the IC ( 200 ), generates a pulse train signal ( 232 ). In this exemplary embodiment, the pulse train signal ( 232 ) is a PWM signal. The pulse train signal ( 232 ) is controlled by a signal ( 246 ) from a CPU ( 244 ). The duty cycle of the PWM signal may be varied in order to create a specific analog value at the output ( 210 ) of the low-pass filter ( 206 ). The amplitude of the PWM signal may also be varied in order to create a specific analog value at the output ( 210 ) of the low-pass filter ( 206 ). The control of the PWM signal is not limited to controlling the duty cycle or the amplitude of the PWM signal. 
         [0026]    In the second embodiment of the invention, the output ( 210 ) of the external low-pass filter ( 206 ) is connected to the input ( 214 ) of the external gain stage ( 212 ). The output voltage ( 216 ) is determined by the gain of the external gain stage ( 212 ). The analog signal ( 236 ) created by the external gain stage ( 212 ) is connected to the input ( 220 ) of the test logic ( 218 ). The test logic ( 218 ) located on the IC ( 200 ) applies the analog signal ( 236 ) to an input of an ADC. 
         [0027]    An output ( 228 ) from the plurality of circuits ( 224 ) is connected to an external tester ( 230 ). The external tester ( 230 ), for example, receives a  1 o digital output signal ( 240 ) based on either current or voltage generated by one or more ADCs. The digital output signal ( 240 ) is controlled by a signal  248  from the CPU ( 244 ). 
         [0028]      FIG. 5  is a block diagram of an exemplary embodiment of an IC, a tester, and analog voltage references. In a third embodiment of the invention, three pulse train generator ( 502 ,  504 , and  506 ) create three impulse train signals ( 524 ,  526 , and  528 ). In this exemplary embodiment, the pulse train signals ( 524 ,  526 , and  528 ) are PWM signals. The pulse train signals ( 524 ,  526 , and  528 ) are controlled by a signal ( 522 ) from a CPU ( 518 ). The duty cycle of the PWM signals may be varied in order to create a specific analog value at the outputs of the low-pass filters. The amplitude of the PWM signals may also be varied in order to create specific analog values at outputs of low-pass filters. The control of the PWM signals is not limited to controlling the duty cycle or the amplitude of the PWM signals. 
         [0029]    In the third embodiment of the invention, the pulse train signals ( 524 ,  526 , and  528 ) are connected to analog voltage references ( 508 ,  510 , and  512 ) respectively. These analog voltage references ( 508 ,  510 , and  512 ) may be created using a low-pass filter ( 206 ) and a gain stage ( 212 ) as shown in  FIG. 2 . The analog signals ( 530 ,  532 , and  534 ) created by the analog voltages references ( 508 ,  510 , and  512 ) are connected to test logic ( 514 ). The test logic ( 514 ) located on the IC ( 200 ) applies the analog signals ( 530 ,  532 , and  534 ) to inputs of flash memory cells. 
         [0030]    Digital outputs signals ( 544 ,  546 , and  548 ) from the plurality of circuits ( 516 ) are connected to an external tester ( 520 ). The external tester ( 520 ), for example, receives digital output signals ( 544 ,  546 , and  548 ) based on either current or voltage generated by flash memory cells. The digital output signals ( 544 ,  546 , and  548 ) are controlled by a signal  542  from the CPU ( 518 ). In this example, three flash memory cells may be tested concurrently reducing the time required to test all the flash memory cells in the flash memory IC ( 500 ). In this example where three pulse train generators ( 502 ,  504 , and  506 ) and three analog voltage references ( 508 ,  510 , and  512 ) are is described for illustrative purposes. It is understood that more flash memory cells may be tested concurrently by adding more internal pulse train generators and more external analog voltage generators. 
         [0031]    In addition to testing more flash memory cells concurrently on an individual flash memory IC as in  FIG. 5 , one or more individual flash memory ICs may be tested concurrently (not shown.) In this case, each individual flash memory IC has at least one pulse train generator internal to the flash memory IC and at least one analog voltage reference external to the flash memory IC. One or more digital outputs signals from the individual flash memory ICs are connected to an external tester. As result of this configuration, the time required to test flash memory ICs is reduced. Other individual ICs may also be tested concurrently. 
         [0032]    The foregoing description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The exemplary embodiments were chosen and described in order to best explain the applicable principles and their practical application to thereby enable others skilled in the art to best utilize various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments except insofar as limited by the prior art.