Abstract:
A transflective LCD. The transflective LCD includes multiple pixels. Each pixel includes a reflective cell and a transmission cell. The reflective cell has a first storage capacitor and a first active device, receiving a first driving voltage and coupling to the first capacitor. The transmission cell has a second storage capacitor and a second active device, receiving a second driving voltage and coupling to the second capacitor. Different from only single driving voltage in conventional transflective LCD, the first driving voltage and the second voltage are generated according to a reflective gamma curve and a transmission gamma curve respectively.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a transflective LCD, and particularly to a transflective LCD driven by bi-gamma curve. 
     2. Description of the Related Art 
     A pixel of the conventional transflective LCD has a transmission region and a reflective region. Unavoidably, the reflective region has a nearly double phase difference nearly double that of the transmission region. Reduction of cell gap of the reflective region to approach that of the transmission region has been adopted in the past to address this issue. FIG. 7A shows a perspective diagram of a pixel of a conventional transflective LCD. The pixel includes a reflective region  10  and a transmission region  20 . The reflective region  20  has a reflective film  12  and a cell gap d 1 . The transmission region  20  has a cell gap d 2 . 
     An equivalent circuit is shown in FIG.  7 B. The reflective region  10  and the transmission region  20  are both coupled to a storage capacitor Cs and a TFT (thin-film-transistor) transistor T 1 . Thus, only driving voltage is afford to supply. The anti-inversion approach adjusts the cell gap d 1  and the cell gap d 2  to the same phase difference. The cell gap d 1  and d 2  must be optimized to fit the LCD&#39;s operation mode, an approach that is difficult to adjust. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a transflective LCD that achieves optimal reflectivity and transmittance. 
     To achieve the above objects, the present invention provides a pixel with reflective region and transmission regions. The reflective region and the transmission region both have a storage capacitor and a TFT transistor for different driving voltages. The driving voltage for the reflective region can have any phase difference in cell gap such as half wave or quarter wave. The driving voltage for the transmission region can have any phase difference in cell gap such as half wave or quarter wave. 
     A driving method for the transflective LCD scans all reflective regions first in a frame period, with all transmission regions are scanned later. 
     Another driving method for the transflective LCD scans all reflective regions of one row first in the row&#39;s active period, and all transmission regions of one row thereof latter. 
     Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aforementioned objects, features and advantages of this invention will become apparent by referring to the following detailed description of the preferred embodiments with reference to the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: 
     FIG. 1A shows a perspective diagram in a pixel&#39;s structure of a transflective LCD of the present invention. 
     FIG. 1B shows an equivalent circuit of the pixel in FIG.  1 A. 
     FIG. 2A shows a reflectivity gamma curve RV 1  for quarter wave phase difference in the transmission region. 
     FIG. 2B shows a transmittance gamma curve TV 1  for quarter wave phase difference in the transmission region. 
     FIG. 2C shows a reflectivity gamma curve RV 1  for half wave phase difference in the transmission region. 
     FIG. 2D shows a transmittance gamma curve TV 1  for half wave phase difference in the transmission region. 
     FIG. 3A shows a schematic diagram of a pixel P 22  in FIG.  3 B. 
     FIG. 3B shows a block diagram of a LCD in the first embodiment. 
     FIG. 3C shows a diagram of all waveforms in FIG.  3 B. 
     FIG. 3D shows a diagram of all waveforms in FIG.  3 B. 
     FIG. 3E shows another block diagram of a LCD in the first embodiment. 
     FIG. 4A shows a schematic diagram of a pixel P 22  in FIG.  4 B. 
     FIG. 4B shows a block diagram of a LCD in the second embodiment. 
     FIG. 4C shows a diagram of all waveforms in FIG.  4 B. 
     FIG. 4D shows a diagram of all waveforms in FIG.  4 B. 
     FIG. 4E shows another block diagram of a LCD in the second embodiment. 
     FIG. 5A shows a schematic diagram of a pixel P 22  in FIG.  5 B. 
     FIG. 5B shows a block diagram of a LCD in the third embodiment. 
     FIG. 6 shows a block diagram of a LCD in the fourth embodiment. 
     FIG. 7A shows a prospective diagram of a pixel of a conventional transflective LCD. 
     FIG. 7B shows an equivalent circuit of the pixel in FIG.  7 A. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1A shows a perspective diagram in a pixel&#39;s structure of a transflective LCD of the present invention. The pixel includes a reflective region  10  and a transmission region. The reflective region  10  has a reflective film  12  and a cell gap d 1 . The transmission region  20  has a cell gap d 2 . The layer under the reflective film  12  is a layer  13  which is coupled to a storage capacitor Cs 1  and a storage capacitor Cs 2 . FIG. 1B shows an equivalent circuit of the pixel. In the reflective region  10 , an equivalent capacitor of the reflective region  10  is represented by Clc 1 , a storage capacitor is Cs 1 , and a TFT transistor is T 1 . In the transmission region  20 , an equivalent capacitor of the transmission region  10  is represented by Clc 2 , a storage capacitor is Cs 2 , and a TFT transistor is T 2 . The TFT transistor T 2  and T 1  can be disposed under the reflective film  12 . 
     Operating in quarter wave phase difference of the transmission region  20 , a reflectivity gamma curve RV 1  showing reflectivity versus driving voltage VR of the reflective region  10  is shown in FIG.  2 A. Because the phase difference through the reflective region  10  is twice that of the transmission region  20 , the maximum reflectivity occurs in half wave. A transmittance gamma curve TV 1  showing transmittance versus driving voltage VT of the transmission region  10  is shown in FIG. 2B, and the maximum transmittance occurs in quarter wave. 
     Operating in half wave phase difference of the transmission region  20 , a reflectivity gamma curve RV 2  showing reflectivity versus driving voltage VR of the reflective region  10  is shown in FIG.  2 C. Because the phase difference through the reflective region  10  is twice that of the transmission region  20 , the maximum reflectivity occurs in half wave. When the phase difference exceeds half wave, the reflectivity decrease with driving voltage VR. A transmittance gamma curve TV 2  showing transmittance versus driving VT of the transmission region  10  is shown in FIG. 2D, and the maximum transmittance occurs in half wave. 
     Because the pixel in the present invention has two TFT transistors T 1  and T 2 , and two storage capacitors Cs 1  and Cs 2 , to control driving voltage VR and VT respectively, the reflective region  10  and transmission region  20  achieve the same phase difference without adjusting the cell gap d 1  and d 2 . The driving voltage VR for the reflective region  10  can be driven by the quarter wave gamma curve RV 1  or by half wave gamma curve RV 2 . The driving voltage VT for the transmission region  20  can be driven by the quarter wave gamma curve TV 1  or by half wave gamma curve TV 2 . The reflective region  10  and the transmission region  20  are corrected by reflectivity and transmittance gamma curve respectively to meet requirements. 
     In power down mode, only the reflective regions  10  are or the transmission regions  20  are powered. As well as turning off back lamps, driving circuits for transmission regions  20  can be turned off for more power saving. 
     The first embodiment 
     FIG. 3B shows a block diagram of a LCD in the first embodiment. The LCD includes a TFT transistor array  300 , an image-signal driving circuit  100 , a scan-signal driving circuit  200 , and a scan-signal driving circuit  220 . FIG. 3A shows a schematic diagram of a pixel P 22  in FIG.  3 B. Other pixels in FIG. 3B have the same schematic as shown in FIG.  3 A. The pixel P 22  has a reflective region  10  and a transmission region  20 , and thus requires two sets of TFT transistors and storage capacitors. 
     The TFT transistor T 1  is disposed at the intersection of row G 2 A and column D 2 A. A gate of the TFT transistor T 1  is coupled to row G 2 A, a drain of the TFT transistor T 1  is coupled to column D 2 A, and a source of the TFT transistor T 1  is coupled to Clc 1  and storage capacitor Cs 1 . The TFT transistor T 2  is disposed at the intersection of row G 2 B and column D 2 A. A gate of the TFT transistor T 1  is coupled to row G 2 B, a drain of the TFT transistor T 1  is coupled to column D 2 A, and a source of the TFT transistor T 2  is coupled to Clc 2  and storage capacitor Cs 2 . All Pixels in the TFT transistor array  300  have the same wiring structure. 
     The scan-signal driving circuit  200  generates scan signals fed to gates of TFT transistors T 1  via rows G 1 A-G 4 A. The scan-signal driving circuit  220  generates scan signals fed to gates of TFT transistors T 2  via rows G 1 B-G 4 B. The image-signal driving circuit  100  generates image signals corresponding to scan signals fed to reflective region Clc 1  or transmission region Clc 2  via columns D 1 A-D 4 A and TFT transistor array  300 . 
     A driving method in the first embodiment scans all reflective regions first, and all transmission regions later. FIG. 3C shows a diagram of all waveforms in FIG.  3 B. The GAMMA 1  can select the reflectivity gamma curve RV 1  or RV 2 , thereby transferring the image signals. The GAMMA 2  can select the transmittance gamma curve TV 1  or TV 2 , thereby transferring the image signals. As shown in FIG. 3C, a frame period fd 1  is divided into a GAMMA 1  period TG 1  and a GAMMA 2  period TG 2 . In GAMMA 1  period TG 1 , the image-signal driving circuit  100  feeds image signals to reflective regions Clc 1  and storage capacitors Cs 1  via columns D 1 A-D 4 A in periods TA 1 , TA 2 , TA 3 , and TA 4 , rows G 1 A-G 4 A respectively. In GAMMA 2  period TG 2 , the image-signal driving circuit  100  feeds image signals to transmission regions Clc 2  and storage capacitors Cs 2  via columns D 1 A-D 4 A in periods TB 1 , TB 2 , TB 3 , and TB 4 , activating rows G 1 B-G 4 B respectively. 
     Another driving method in the first embodiment scans all reflective regions of one row first in one row&#39;s active period, and all transmission regions of one row later in one row&#39;s active period. FIG. 3D shows a diagram of all waveforms in FIG.  3 B. As shown in FIG. 3D, in a frame fd 1 , GAMMA 1  is active in periods TGA 1 , TGA 2 , TGA 3 , TGA 4 , and GAMMA 2  is active in periods TGB 1 , TGB 2 , TGB 3 , and TGB 4 . Rows active in sequence periods G 1 A-G 1 B-G 2 A-G 2 B-G 3 A-G 3 B-G 4 A-G 4 B corresponding to the sequence periods TGA 1 -TGB 1 -TGA 2 -TGB 2 -TGA 3 -TGB 3 -TGA 4 -TGB 4  that GAMMA 1  and GAMMA 2  are active alternatively. In periods TGA 1 , TGA 2 , TGA 3 , and TGA 4 , the image-signal driving circuit  100  feeds image signals to reflective region Clc 1  and storage capacitor Cs 1  via columns D 1 A-D 4 A in periods that rows G 1 A-G 4 A are active respectively. In periods TGB 1 , TGB 2 , TGB 3 , and TGB 4 , the image-signal driving circuit  100  feeds image signals to reflective region Clc 2  and storage capacitor Cs 2  via columns D 1 A-D 4 A in periods when rows G 1 B-G 4 B are active respectively. 
     The driving method in FIG. 3E is the same as that in  3 B. The scan-signal driving circuit  200  and  220  are replaced by the scan-signal driving circuit  200  and a multiplex  250 . The multiplex  250  switches between rows G 1 A-G 4 A and rows G 1 B-G 4 B. 
     The second embodiment 
     FIG. 4B shows a block diagram of a LCD in the second embodiment. The LCD includes a TFT transistor array  300 , an image-signal driving circuit  100  and  120 , and a scan-signal driving circuit  200 . FIG. 4A shows a schematic diagram of a pixel P 22  in FIG.  4 B. Other pixels in FIG. 4B have the same schematic as shown in FIG.  4 A. The pixel P 22  has a reflective region  10  and a transmission region  20 , and thus requires two sets of TFT transistors and storage capacitors. 
     The TFT transistor T 1  is disposed at the intersection of row G 2 A and column D 2 A. A gate of the TFT transistor T 1  is coupled to row G 2 A, a drain of the TFT transistor T 1  is coupled to column D 2 A, and a source of the TFT transistor T 1  is coupled to Clc 1  and storage capacitor Cs 1 . The TFT transistor T 2  is disposed at the intersection of row G 2 A and column D 2 B. A gate of the TFT transistor T 1  is coupled to row G 2 A, a drain of the TFT transistor T 2  is coupled to column D 2 B, and a source of the TFT transistor T 2  is coupled to Clc 2  and storage capacitor Cs 2 . All Pixels in the TFT transistor array  300  have the same wiring structure. 
     The scan-signal driving circuit  200  generates scan signals fed to gates of TFT transistors T 1  or T 2  via rows G 1 A-G 4 A. The image-signal driving circuit  100  generates image signals corresponding to scan signals fed to reflective region Clc 1  via columns D 1 A-D 4 A and TFT transistor array  300 . The image-signal driving circuit  120  generates image signals corresponding to scan signals fed to transmission region Clc 2  via columns D 1 B-D 4 B and TFT transistor array  300 . 
     A driving method in the second embodiment scans all reflective regions first, and all transmission regions later in a frame periods fd 1 . FIG. 4C shows a diagram of all waveforms in FIG.  4 B. The GAMMA 1  can select the reflectivity gamma curve RV 1  or RV 2 , thereby transferring the image signals. The GAMMA 2  can select the transmittance gamma curve TV 1  or TV 2 , thereby transferring the image signals. As shown in FIG. 4C, a frame period fd 1  is divided into a GAMMA 1  period TG 1  and a GAMMA 2  period TG 2 . In GAMMA 1  period TG 1 , the image-signal driving circuit  100  feeds image signals to reflective region Clc 1  and storage capacitor Cs 1  via columns D 1 A-D 4 A in periods TA 1 , TA 2 , TA 3 , and TA 4 , when rows G 1 A-G 4 A are active respectively. In GAMMA 2  period TG 2 , the image-signal driving circuit  120  feeds image signals to transmission regions Clc 2  and storage capacitors Cs 2  via columns D 1 B-D 4 B in periods TB 1 , TB 2 , TB 3 , and TB 4 , when rows G 1 A-G 4 A are active respectively. 
     Another driving method in the second embodiment scans all reflective regions of one row first in the row&#39;s active period, and all transmission regions of the row later in the row&#39;s active period. FIG. 4D shows a diagram of all waveforms in FIG.  4 B. As shown in FIG. 4D, in a frame fd 1 , GAMMA 1  is active in periods TGA 1 , TGA 2 , TGA 3 , TGA 4 , and GAMMA 2  is active in periods TGB 1 , TGB 2 , TGB 3 , and TGB 4 . Rows are active in sequence periods G 1 A-G 2 A-G 3 A-G 4 A. Row G 1 A is active in periods TGA 1 , TGB 1  corresponding to GAMMA 1  and GAMMA 2  becoming active alternatively. Row G 2 A is active in periods TGA 2 , TGB 2  corresponding to GAMMA 1  and GAMMA 2  becoming active alternatively. Row G 3 A is active in periods TGA 3 , TGB 3  corresponding to GAMMA 1  and GAMMA 2  becoming active alternatively. Row G 4 A is active in periods TGA 4 , TGB 4  corresponding to GAMMA 1  and GAMMA 2  becoming active alternatively. In periods TGA 1 , TGA 2 , TGA 3 , and TGA 4 , the image-signal driving circuit  100  feeds image signals to reflective region Clc 1  and storage capacitor Cs 1  via columns D 1 A-D 4 A in periods that rows G 1 A-G 4 A are active respectively. In periods TGB 1 , TGB 2 , TGB 3 , and TGB 4 , the image-signal driving circuit  120  feeds image signals to reflective region Clc 2  and storage capacitor Cs 2  via columns D 1 B-D 4 B in periods when rows G 1 A-G 4 A are active respectively. 
     The driving method in FIG. 4E is the same as that in  4 B. The image-signal driving circuit  100  and  120  are replaced by the image-signal driving circuit  100  and a multiplex  150 . The multiplex  150  switches between columns D 1 A-D 4 A and columns D 1 B-D 4 B. 
     The third embodiment 
     FIG. 5B shows a block diagram of a LCD in the first embodiment. The LCD includes a TFT transistor array  300 , an image-signal driving circuit  100 , 120 , and a scan-signal driving circuit  200 , 220 . FIG. 5A shows a schematic diagram of a pixel P 22  in FIG.  5 B. Other pixels in FIG. 5B have the same schematic as shown in FIG.  5 A. The pixel P 22  has a reflective region  10  and a transmission region  20 , and thus requires two sets of TFT transistors and storage capacitors. 
     The TFT transistor T 1  is disposed at the intersection of row G 2 A and column D 2 A. A gate of the TFT transistor T 1  is coupled to row G 2 A, a drain of the TFT transistor T 1  is coupled to column D 2 A, and a source of the TFT transistor T 1  is coupled to Clc 1  and storage capacitor Cs 1 . The TFT transistor T 2  is disposed at the intersection of row G 2 B and column D 2 B. A gate of the TFT transistor T 1  is coupled to row G 2 B, a drain of the TFT transistor T 1  is coupled to column D 2 B, and a source of the TFT transistor T 2  is coupled to Clc 2  and storage capacitor Cs 2 . All Pixels in the TFT transistor array  300  have the same wiring structure. 
     The scan-signal driving circuit  200  generates scan signals fed to gates of TFT transistors T 1  via rows G 1 A-G 4 A. The scan-signal driving circuit  220  generates scan signals fed to gates of TFT transistors T 2  via rows G 1 B-G 4 B. The image-signal driving circuit  100  generates image signals corresponding to scan signals fed to reflective region Clc 1  via columns D 1 A-D 4 A and TFT transistor array  300 . The image-signal driving circuit  120  generates image signals corresponding to scan signals fed to transmission region Clc 2  via columns D 1 B-D 4 B and TFT transistor array  300 . 
     A driving method in the third embodiment scans all reflective regions first in a frame period fd 1 , and all transmission regions later. FIG. 3C shows a diagram of all waveforms in FIG.  5 B. The GAMMA 1  can select the reflectivity gamma curve RV 1  or RV 2 , thereby transferring the image signals. The GAMMA 2  can select the transmittance gamma curve TV 1  or TV 2 , thereby transferring the image signals. As shown in FIG. 3C, a frame period fd 1  is divided into a GAMMA 1  period TG 1  and a GAMMA 2  period TG 2 . In GAMMA 1  period TG 1 , the image-signal driving circuit  100  feeds image signals to reflective regions Clc 1  and storage capacitors Cs 1  via columns D 1 A-D 4 A in periods TA 1 , TA 2 , TA 3 , and TA 4 , when rows G 1 A-G 4 A are active respectively. In GAMMA 2  period TG 2 , the image-signal driving circuit  100  feeds image signals to transmission regions Clc 2  and storage capacitors Cs 2  via columns D 1 A-D 4 A in periods TB 1 , TB 2 , TB 3 , and TB 4 , when rows G 1 B-G 4 B are active respectively. 
     Another driving method in the third embodiment scans all reflective regions of one row first in the row&#39;s active period, and all transmission regions of one row scanned later in the row&#39;s active period. FIG. 3D shows a diagram of all waveforms in FIG.  5 B. As shown in FIG. 3D, in a frame fd 1 , GAMMA 1  is active in periods TGA 1 , TGA 2 , TGA 3 , TGA 4 , and GAMMA 2  is active in periods TGB 1 , TGB 2 , TGB 3 , and TGB 4 . Rows are active in sequence in periods G 1 A-G 1 B-G 2 A-G 2 B-G 3 A-G 3 B-G 4 A-G 4 B corresponding to the sequence periods TGA 1 -TGB 1 -TGA 2 -TGB 2 -TGA 3 -TGB 3 -TGA 4 -TGB 4  GAMMA 1  and GAMMA 2  becoming active alternatively. In periods TGA 1 , TGA 2 , TGA 3 , and TGA 4 , the image-signal driving circuit  100  feeds image signals to reflective region Clc 1  and storage capacitor Cs 1  via columns D 1 A-D 4 A in periods when rows G 1 A-G 4 A are active respectively. In periods TGB 1 , TGB 2 , TGB 3 , and TGB 4 , the image-signal driving circuit  120  feeds image signals to reflective region Clc 2  and storage capacitor Cs 2  via columns D 1 B-D 4 B when rows G 1 B-G 4 B are active respectively. 
     The fourth embodiment 
     FIG. 6B shows a block diagram of a LCD in the first embodiment. The LCD includes a TFT transistor array  300 , an image-signal driving circuit  100 , a scan-signal driving circuit  200 , and multiplex  150 ,  250 . FIG. 5A shows a schematic diagram of a pixel P 22  in FIG.  6 B. Other pixels in FIG. 6B have the same schematic as shown in FIG.  5 A. 
     The scan-signal driving circuit  200  generates scan signals fed to gates of TFT transistors T 1  via rows G 1 A-G 4 A selected by the multiplex  250  or to gates of TFT transistors T 2  via rows G 1 B-G 4 B selected by the multiplex  250 . The image-signal driving circuit  100  generates image signals corresponding to scan signals fed to reflective region Clc 1  via columns D 1 A-D 4 A selected by the multiplex  150  and TFT transistor array  300  or to transmission region Clc 2  via columns D 1 B-D 4 B selected by the multiplex  150  and TFT transistor array  300 . 
     A driving method in the fourth embodiment scans all reflective regions first in a frame period fd 1 , and all transmission regions later. FIG. 3C shows a diagram of all waveforms in FIG.  6 B. The GAMMA 1  can select the reflectivity gamma curve RV 1  or RV 2 , thereby transferring the image signals. The GAMMA 2  can select the transmittance gamma curve TV 1  or TV 2 , thereby transferring the image signals. As shown in FIG. 3C, a frame period fd 1  is divided into a GAMMA 1  period TG 1  and a GAMMA 2  period TG 2 . In GAMMA 1  period TG 1 , switches S 2  of the multiplex  250  are at position  3 , switches S 1  of the multiplex  150  are at position  1 , and the image-signal driving circuit  100  feeds image signals to reflective region Clc 1  and storage capacitor Cs 1  via columns D 1 A-D 4 A in periods TA 1 , TA 2 , TA 3 , and TA 4  that rows G 1 A-G 4 A are active respectively. In GAMMA 2  period TG 2 , switches S 2  of the multiplex  250  are at position  4 , switches S 1  of the multiplex  150  are at position  2 , and the image-signal driving circuit  100  feeds image signals to transmission region Clc 2  and storage capacitor Cs 2  via columns D 1 B-D 4 B in periods TB 1 , TB 2 , TB 3 , and TB 4  when rows G 1 B-G 4 B are active respectively. 
     Another driving method in the fourth embodiment scans all reflective regions of one row first in the row&#39;s active period, and all transmission regions later in the row&#39;s active period. FIG. 3D shows a diagram of all waveforms in FIG.  6 B. As shown in FIG. 3D, in a frame fd 1 , GAMMA 1  is active in periods TGA 1 , TGA 2 , TGA 3 , TGA 4 , switches S 1  of the multiplex  150  are at position  1 , and switches S 2  of the multiplex  250  are at position  3 . In a frame fd 1 , GAMMA 2  is active in periods TGB 1 , TGB 2 , TGB 3 , and TGB 4 , switches S 1  of the multiplex  150  are at position  2 , and switches S 2  of the multiplex  250  are at position  4 . Rows are active in sequence periods G 1 A-G 1 B-G 2 A-G 2 B-G 3 A-G 3 B-G 4 A-G 4 B corresponding to the sequence periods TGA 1 -TGB 1 -TGA 2 -TGB 2 -TGA 3 -TGB 3 -TGA 4 -TGB 4  when GAMMA 1  and GAMMA 2  are active alternatively. In period TGA 1 , TGA 2 , TGA 3 , and TGA 4 , the image-signal driving circuit  100  feeds image signals to reflective region Clc 1  and storage capacitor Cs 1  via columns D 1 A-D 4 A in periods when rows G 1 A-G 4 A are active respectively. In period TGB 1 , TGB 2 , TGB 3 , and TGB 4 , the image-signal driving circuit  100  feeds image signals to reflective region Clc 2  and storage capacitor Cs 2  via columns D 1 B-D 4 B in periods that rows G 1 B-G 4 B are active respectively. 
     Although the present invention has been described in its preferred embodiments, it is not intended to limit the invention to the precise embodiments disclosed herein. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.