Abstract:
A metal oxide semiconductor field effect transistor (MOSFET) cascode current mirror circuit architecture capable of operating at a low power supply voltage and with only one input reference number while maintaining a high dynamic signal range.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to current mirror circuits, and in particular, to metal oxide semiconductor field effect transistor (MOSFET) cascode current mirror circuits. 
   2. Description of the Related Art 
   Current mirror circuits, in general, are well-known in the art and are used in many applications. As is well-known, in a conventional current mirror circuit, an input current source drives one of a pair of transistors interconnected in such a manner that such input current is substantially replicated, or mirrored, at the output of the second transistor. As is also well-known, the relative sizes, or scaling, of the respective transistor dimensions can be designed to establish the desired ratio between the input current and the output, or mirrored, current. Accordingly, one important factor in designing such a current mirror circuit is matching the input and output currents according to the desired proportion or ratio. 
   Current mirror circuits found in present day integrated circuits (ICs) tend to be implemented using MOSFETs. As ICs have become increasingly dense, in terms of transistor count versus die size, channel lengths of the MOSFETs have also become shorter. Such decreased channel lengths result in decreased output impedances for current mirror circuits. Accordingly, it has become increasingly necessary to provide cascode output circuits to maintain or increase output impedances. 
   Cascode output stages often exhibit limited voltage ranges in terms of possible biasing voltage for the cascode output stage, as well as possible power supply voltages. With respect to possible power supply voltages, this has become increasingly critical as operating power supply voltages have decreased to 3.3 volts and below. 
   Referring to  FIG. 1 , for example, a conventional MOSFET cascode current mirror circuit  10  intended to provide an output current IOUT with an associated output voltage having a high dynamic range relative to its power supply voltage, while also operating with a minimum power supply voltage VDD (relative to the circuit reference or ground potential VSS/GND) is implemented using reference current sources  12 ,  14  and N-MOSFETs M 1 , M 2 , M 3 , M 4 , M 5 , M 10 , M 11 , all interconnected substantially as shown. (The reference current sources,  12 ,  14  can be implemented in a number of well-known ways such that the operating voltage across each current source  12 ,  14 , when implemented with MOSFETs, is equal to the drain-to-source saturation voltage VDSAT.) 
   Diode-connected transistor M 1 , driven by current source  14 , establishes a bias voltage V 10  at the gate terminal of transistor M 2 . In turn, transistor M 2  sinks the current provided by current source  12  and provides a bias voltage V 3  at the gate terminal of transistor M 3 . The current through transistor M 3  drives diode-connected transistor M 5  as the input to a current mirror circuit formed by transistors M 5  and M 4 . This biasing arrangement results in the equal reference current IREF of current sources  12  and  14  to be mirrored as the channel currents through transistors M 3  and M 5 , and establishing the biasing voltages V 10 , V 11  for the gate terminals of output transistors M 10  and M 11 . Cascode output transistor M 10  helps maintain a high output impedance for the output current IOUT at its drain terminal. 
   Transistors M 2  and M 4  serve as reference devices in helping to establish the mirrored current and biasing voltages V 10 , V 11 . Transistor M 1  has a channel width (e.g., 4 microns) which is approximately equal to or less than the channel widths of the reference M 2 , M 4  and output M 10 , M 11  transistors (e.g., 20 microns) so as to maintain the minimum biasing potential for the output transistors M 10 , M 11  (discussed in more detail below). The source follower configuration of transistors M 3  and M 5  establish the minimum power supply voltage (VDD−VSS/GND) as the sum of two threshold voltages VT (the minimum gate-to-source voltage VGS at which an inversion layer is formed and channel conduction, and therefore drain current flow, begins) plus one MOSFET drain-to-source saturation voltage VDSAT (2*VT+VDSAT). 
   As power supply voltages continue to decrease, it would be desirable to have a minimum operating power supply voltage less than that offered by the circuit of FIG.  1 . Further, it would be desirable to accomplish this without requiring a second current source to generate the biasing voltage for the cascode output transistor. 
   SUMMARY OF THE INVENTION 
   In accordance with the presently claimed invention, a metal oxide semiconductor field effect transistor (MOSFET) cascode current mirror circuit architecture is provided which is capable of operating at a low power supply voltage and with only one input reference current while maintaining a high dynamic signal range. 
   In accordance with one embodiment of the presently claimed invention, MOSFET cascode current mirror circuitry includes reference circuitry, feedback circuitry and cascode output circuitry. The reference circuitry includes a plurality of N telescopically coupled MOSFETs having a plurality of like corresponding channel dimensions and is responsive to reception of a reference current and at least one feedback voltage by providing a reference voltage, wherein N is an integer greater than unity. The feedback circuitry is coupled to the reference circuitry, includes at least one scaled MOSFET, and is responsive to reception of the reference voltage by providing the at least one feedback voltage in relation to the reference voltage. One of the at least one scaled MOSFET has a channel dimension approximately equal to or less than 1/N 2  of a corresponding one of the first plurality of reference circuitry MOSFET channel dimensions and is responsive to the reference voltage. The cascode output circuitry is coupled to the reference circuitry and the feedback circuitry, and is responsive to reception of the reference voltage and the at least one feedback voltage by providing a cascode output current related to the reference current. 
   In accordance with another embodiment of the presently claimed invention, MOSFET cascode current mirror circuitry includes reference circuitry, feedback circuitry and cascode output circuitry. The reference circuitry includes a plurality of N telescopically coupled MOSFETs having a plurality of like corresponding channel dimensions and is responsive to reception of at least one reference current and at least one feedback voltage by providing at least one reference voltage, wherein N is an integer greater than unity. The feedback circuitry is coupled to the reference circuitry, includes at least one scaled MOSFET, and is responsive to reception of one of the at least one reference voltage by providing the at least one feedback voltage in relation to the one of the at least one reference voltage. At least one of the at least one scaled MOSFET has a channel dimension approximately equal to or less than 1/N 2  of a corresponding reference circuitry MOSFET channel dimension and is responsive to the one of the at least one reference voltage. The cascode output circuitry is coupled to the feedback circuitry, includes a second plurality of N telescopically coupled MOSFETs, and is responsive to reception of the at least one feedback voltage by providing a cascode output current related to one or more of the at least one reference current. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a conventional MOSFET cascode current mirror circuit. 
       FIG. 2  is a schematic diagram of a MOSFET cascode current mirror circuit in accordance with one embodiment of the presently claimed invention. 
       FIG. 3  is a schematic diagram of a MOSFET cascode current mirror circuit in accordance with another embodiment of the presently claimed invention. 
       FIG. 4  is a schematic diagram of a MOSFET cascode current mirror circuit in accordance with another embodiment of the presently claimed invention. 
       FIG. 5  is a schematic diagram of a MOSFET cascode current mirror circuit in accordance with another embodiment of the presently claimed invention. 
       FIG. 6  is a schematic diagram of a MOSFET cascode current mirror circuit in accordance with another embodiment of the presently claimed invention. 
       FIG. 7  is a schematic diagram of a MOSFET cascode current mirror circuit in accordance with another embodiment of the presently claimed invention. 
   

   DETAILED DESCRIPTION 
   The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
   Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
   In conformance with the discussion herein, it will be appreciated and understood by one of ordinary skill in the art that a MOSFET current mirror circuit with a cascode output in accordance with the presently claimed invention can be implemented with a P-MOSFET current mirror circuit and N-MOSFET biasing and cascode output circuit as discussed herein, or alternatively, with an N-MOSFET current mirror circuit and P-MOSFET biasing and cascode output circuitry with appropriate reversals in drain and source terminal connections and power supply voltage polarity to provide an output current source rather than an output current sink circuit, all in accordance with well known conventional circuit design techniques. 
   Referring to  FIG. 2 , a MOSFET cascode current mirror circuit  100   a  in accordance with one embodiment of the presently claimed invention includes a reference current source  112  (which can be implemented in a conventional manner such that, when implemented with MOSFETs, has an operating output voltage across its terminals equal to a MOSFET output saturation voltage VDSAT), a current mirror circuit formed by P-MOSFETs P 10  and P 11 , a biasing circuit formed by N-MOSFETs N 1 , N 2 , N 10 , N 11 , and a cascode output circuit formed by N-MOSFETs N 20 , N 21 , all interconnected substantially as shown between the power supply terminals VDD, VSS/GND. The reference current IREF from current source  112  is provided to the drain and gate terminals of diode-connected transistor N 1 , thereby producing a bias voltage V 20  at the gate terminals of transistors N 1 , N 10  and N 20 . The resulting drain current through transistor N 10  drives the current mirror input transistor P 10 , thereby being mirrored by transistor P 11  and provided to the drain and gate terminals of diode-connected transistor N 11 . Transistor N 11  is designed to have a channel width equal to that of transistor N 2 . 
   A negative feedback loop is formed by the interaction of transistors N 1 , N 10 , P 10 , P 11 , N 1  and N 2 . The associated DC biasing points of this loop force the drain current of transistor N 2  to be equal to the input reference current IREF. Similarly, the drain currents through the circuit branches formed by transistors P 10  and N 10  and transistors P 11  and N 11  are also equal to the input reference current IREF. 
   In accordance with a well-known circuit design technique (e.g., see U.S. Pat. No. 4,583,037, the disclosure of which is incorporated herein by reference), the dimensions of transistor N 10  are scaled in proportion to the corresponding dimensions of the reference transistors N 1 , N 2 , and in particular, the channel width of transistor N 10  is designed to be approximately equal to or, preferably, less than the channel widths of the reference transistors N 1 , N 2 . Accordingly, the gate-to-source voltage VGS of transistor N 10  is maintained as equal to the sum of the gate-to-source voltage VGS of transistor N 1  plus the drain-to-source saturation voltage VDSAT of transistor N 2 . 
   This can be demonstrated in accordance with well-known MOSFET circuit operating characteristics. As is well-known, drain currents ID 1  and ID 2  of transistors N 1  and N 10 , respectively, can be computed based upon the majority carrier mobility u, the gate capacitance per unit area Cox, the channel width W, channel length L, threshold voltage VT, transistor scaling factor N and the respective gate-to-source voltages VGS 1  (transistor N 1 ), VGS 2  (transistor N 10 ), as follows: 
             Equation   ⁢           ⁢   1   ⁢     :               id   1     =           u   ·   Cox     2     ·       N   ·   W     L       ⁢       (       VGS   1     -   VT     )     2                   Equation   ⁢           ⁢   2   ⁢     :               id   2     =           u   ·   Cox     2     ·     W   L       ⁢       (       VGS   2     -   VT     )     2                 
 
Setting these currents equal to each other (id 1 =id 2 ) produces Equation 3, which can be simplified and reduced as follows, for scaling factors of N=4 and N=9: 
       Equation   ⁢           ⁢   3   ⁢     :         
               u   ·   Cox     2     ·       N   ·   W     L       ⁢       (       VGS   1     -   VT     )     2       =           u   ·   Cox     2     ·     W   L       ⁢       (       VGS   2     -   VT     )     2           
  N ( VGS   1   −VT ) 2 =( VGS   2   −VT )  Equation 4
 
√{square root over ( N )}( VGS   1   −VT )=( VGS   2   −VT )  Equation 5
 
 VGS   2   =√{square root over (N)} ( VGS   1   −VT )+ VT   Equation 6
 
 VGS   2   −VGS   1   =√{square root over (N)} ( VGS   1   −VT )+ VT−VGS   1   Equation 7
 
 VGS   2   −VGS   1   =√{square root over (N)} ( VGS   1   −VT )−( VGS   1   −VT )  Equation 8
 
 VGS   2   −VGS   1 =(√{square root over ( N )}- 1 )( VGS   1   −VT )  Equation 9
 
Example: N =4, VGS   2   −VGS   1 =( VGS   1   −VT )= VDSAT   1   Equation 10
 
Example: N =9, VGS   2   −VGS   1 =2( VGS   1   −VT )=2 VDSAT   1   Equation 11
 
   Based upon the foregoing, because transistors N 2  and N 1  are scaled to have equal channel widths and lengths, they will have equal gate-to-source voltages VGS. Accordingly, the source terminal of transistor N 1  will be one output saturation voltage VDSAT above circuit ground VSS/GND, thereby maintaining transistor N 2  in saturation. As a result, this circuit  100   a  is capable of operating with a power supply voltage as low as the sum of one threshold voltage VT (transistor N 1 ) plus two output saturation voltages VDSAT (transistor N 2  and current source  112 ), i.e., VT+2VDSAT, while requiring only one input reference current source  112  and still providing a cascode output. Additionally, with the high impedance node of the feedback loop located at one of the outputs of the circuit, i.e., the drain terminal of transistor N 1 , compensation for maintaining good phase margin for the feedback loop is easily achieved. 
   Referring to  FIG. 3 , the principles discussed above in connection with the circuit  100   a  of  FIG. 2  can be scaled to include multiple cascode output devices as shown in this circuit  100   b . In this circuit  100   b , an additional cascode device, transistor N 22 , is inserted into the output circuit, along with corresponding reference N 3  and biasing N 12  transistors. As before, the biasing voltage V 20  produced at the gate terminal of transistor N 10  generates the reference current IREF through transistors P 10  and N 10 , which is mirrored in current mirror output transistors P 11  and P 12 . These same reference currents IREF are sunk by diode-connected biasing transistors N 11  and N 12  to produce the biasing voltages V 21 , V 22  for output transistors N 21  and N 22 , respectively. In accordance with the example equations provided above, transistor N 10  is scaled to have a channel width approximately equal to or less than 1/N 2  ({fraction (1/9)} in this example) of the channel widths of the reference transistors N 1 , N 2 , N 3  (where N equals the number of reference transistors). Similarly, transistor N 12 , since it drives a reference transistor N 3  which is lower in the stack of reference transistors N 1 , N 3 , N 2 , is scaled to have a channel width approximately equal to or less than 1(N- 1 ) 2  (¼ in this example) of the channel widths of the reference transistors N 1 , N 2 , N 3 . 
   Referring to  FIG. 4 , a MOSFET cascode current mirror circuit  200   a  in accordance with another embodiment of the presently claimed invention is a variation of the circuit  100   a  of FIG.  2 . In this circuit  200   a , the output biasing voltages V 20 , V 21  are provided such that the final cascode output biasing voltage V 20  is decoupled from the high impedance node present at the drain terminal of reference transistor N 1 . Accordingly, the reference voltage V 10  which biases the scaled transistor N 10  at the input to the current mirror circuit P 10 /P 11 /P 12  is decoupled from biasing of the cascode output transistor N 20 . 
   Referring to  FIG. 5 , a circuit  200   b  in accordance with another embodiment of the presently claimed invention is a variation on the circuit  200   a  of FIG.  4 . In this circuit  200   b , the number of cascode output transistors has been increased from one to two. The diode-connected transistors N 12 , N 13  responsible for biasing the cascode output transistors N 22 , N 20  are scaled in a manner similar to that discussed above for the circuit  100   b  of FIG.  3 . 
   Referring to  FIG. 6 , a circuit  200   c  in accordance with another embodiment of the presently claimed invention shares some similarities with the circuits  100   a ,  200   a  discussed above for  FIGS. 2 and 4 . For example, the high impedance node present at the drain terminal of reference transistor N 1  is decoupled from the cascode output transistor N 20 , similar to the circuit  200   a  of  FIG. 4 , while diode-connected transistor N 4  provides the biasing voltage V 20  for the cascode output transistor N 20 , similar to the circuit  100   a  of FIG.  2 . However, this circuit  200   c  does require an additional reference current source  114 . 
   Referring to  FIG. 7 , a circuit  200   d  in accordance with another embodiment of the presently claimed invention is a variation on the circuit  200   a  of FIG.  4 . For example, the high impedance node present at the drain terminal of reference transistor N 1  is decoupled from the biasing circuit for the cascode output transistor N 20 . Unlike the circuit  200   a  of  FIG. 4 , however, the biasing voltages V 20 , V 22  for the cascode output transistors N 20 , N 22  are provided by diode-connected, scaled transistors N 4 , N 5  which are biased by separate reference current sources  114 ,  116 . In conformance with the discussion above, transistors N 10 , N 14  and N 5  are scaled in terms of their respective channel widths to provide appropriate biasing with respect to the reference transistors N 1 , N 2 , N 3  and output transistors N 20 , N 21 , N 22 . 
   various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope of the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.