Abstract:
Apparatus and method for programmably phase shifting an audio tone is disclosed for use in a cellular communications system. A digital phase lock loop (PLL) includes a programmable phase shift therewithin and an audio output, phase-shifted from an input audio tone, is extracted from the thus programmed PLL. The apparatus of the present invention is particularly designed to be realized using digital circuits capable of integration into a monolithic CMOS IC.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to the field of phase shifting circuits for processing electrical signals. It has particular application to cellular communications systems and in particular to apparatus and method for programmably phase shifting a supervisory audio tone in such a system. 
     Cellular communications systems are growing in popularity and complexity. A cellular communications system comprises a plurality of cells each cell including at least one master station which is in communication with any number of mobile stations within the cell (typically via a fixed remotely controlled transceiver site within or adjacent the cell). A mobile station within the cell communicates to the master station which transfers the communication to conventional land telephone lines for routing the communication to the desired destination. As a mobile station moves from one cell to another, it must cease communication with the remote station of the cell from which it is departing and establish communication with a similar station in the cell which it is entering. In order to synchronize communications between the various stations and the mobile station, the fixed station emits a Supervisory Audio Tone (SAT). The mobile station must be capable of receiving the SAT and retransmitting this tone to the fixed station such that the retransmitted tone has a phase error of less than or equal to plus or minus 20 degrees. 
     Since each mobile station contains a transmitter-receiver which may impart a different value of phase error to any transmission, and since the mobile stations move with a speed which may affect the phase error of the retransmitted tone, each mobile station must be capable of adjusting the phase of the retransmitted tone in order to produce a retransmitted tone with a phase error of less than or equal to plus or minus 20 degrees with respect to the SAT. 
     Therefore, a need exists to provide circuitry in each mobile station which can adjustably phase shift the retransmitted audio tone. Moreover, to mass produce such a circuit each one must be capable of providing a different phase adjustment corresponding to the particular radio equipment in each mobile station. 
     Circuits are known which can phase shift the audio tone by analog means. Such circuitry is necessarily large and expensive to manufacture. This large circuitry takes up a great deal of room in the mobile station thus increasing the cost of the mobile station and making it more difficult to place the mobile station conveniently inside a vehicle. 
     Thus a need exists for an audio tone phase shift circuit which uses mostly digital circuits, could be manufactured at a reduced cost and in a miniaturized package. Such a digital circuit would have to be adjustable in order to provide the various phase shift adjustments required in different mobile stations. A programmable digital phase shift circuit capable of being integrated into integrated circuits would be most advantageous--and such a circuit is provided by this invention. 
     SUMMARY OF THE INVENTION 
     The present invention provides apparatus and method for programmably adjusting the phase shift of a relatively low frequency supervisory audio &#34;tone&#34; (SAT) (e.g. 5970 Hz, 6000 Hz or 6030 Hz in some current cellular radio systems). 
     The SAT is received and is phase locked to a reference tone by means of a phase lock loop (PLL). An oscillator is conventionally provided in the phase lock loop for generating a high frequency signal which is frequency divided to provide the reference tone. However, the phase of the reference signal may be adjusted by an amount corresponding to a programming digital signal input. Thus, the reference tone is capable of being phase adjusted with respect to the oscillator even while it is being phase locked to the SAT as part of the PLL. The oscillator of the phase lock loop thus outputs a high frequency signal which is adjustably &#34;phase locked&#34; to the lower frequency SAT (i.e. actually to a similar lower frequency sub-multiple of the oscillator output which is adjustably phase-shifted). This phase adjusted high frequency signal may be &#34;extracted&#34; and frequency divided and/or otherwise output to a sine wave generator which thus provides an output tone having a phase which is similarly adjusted with respect to the incoming SAT. In such a fashion, a transmitted output tone is generated having a phase error which may be adjusted (e.g. under control of a properly programmed control circuit) so as to be less than or equal to plus or minus 20 degrees with respect to the incoming SAT. 
     The operation and construction of circuit will be made more clear with respect to the following description of the preferred embodiment. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of one embodiment of the present invention. 
     FIG. 2 is a schematic diagram of an alternative embodiment of the present invention. 
     FIG. 3 is a schematic diagram of the presently most preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 depicts a schematic diagram of one embodiment of the present invention. The SAT is received at a conventional radio receiver discriminator (not shown). The discriminator (e.g. an FM discriminator) provides the received demodulated signal to a conventional bandpass filter 11 which may, for instance, comprise a switched capacitor filter. The use of a switched capacitor bandpass filter in such a circuit is advantageous in that it provides good input tone selectivity and it provides a square wave input &#34;tone&#34; with a given frequency and phase to a first input 13a of a conventional phase detector 13. Voltage controlled oscillator (VCO) 15 (or any other suitably controlled oscillator) is controlled by the output of phase detector 13 (e.g. through a conventional PLL loop filter 23) to generate an output at 15a having a frequency which is 2 n  times the frequency of the input tone because the PLL includes a 2 n  frequency divider (e.g. counter) 17. 
     Each state of the counter 17 (a state corresponds to a unique n-bit digital word) thus represents a 360/2 n  degree phase shift of the PLL fundamental input frequency. The output of the counter may be taken from the least significant bit (LSB) and thus provides a square wave at the fundamental frequency (i.e. the LSB always goes low at state zero and high at state 2.sup.(n-1)). Thus, without decoder 19 and latch 21, a conventional digital PLL circuit is provided wherein the highest frequency of PLL operation is determined by the number of cyclic counter states (i.e. 2 n ). 
     However, decoder 19 is used to insert a controlled phase shift into the PLL loop. A digital programming signal may be used with a conventional 2 n  state decoder circuit so as to decode and thus effectively select as a pseudo &#34;starting&#34; counter state any one of the 2 n  possible states of the cyclically occurring n-bit words. For example, decoder 19 may have a decode &#34;1&#34; output and a decode &#34;2&#34; output which cause latch 21 to toggle at the desired fundamental frequency or rate--but which are controllably phased with respect to the VCO output and counter 17. 
     For example, when decoder 19 receives a digital programming signal (e.g. an n-bit word) indicating that the PLL should be adjusted to a given phase, this particular programming signal commanding (e.g. a decade &#34;1&#34; upon detecting counter state M) will be used to generate an accordingly phase adjusted output signal. The decode &#34;1&#34; output will go high when the programmed counter state M is detected among the plurality of n-bit words cyclically received from counter 17. Decode &#34;2&#34; is programmed to go high on detection of state M+2.sup.(n-1) modulo n (which should occur one-half a fundamental frequency output cycle later than when the decode &#34;1&#34; signal goes high). In actual implementation, the second decode may only require one additional gate since all of the counter bits except the MSB are identical for M and M+2.sup.(n-1) and the MSB is always inverted for state M+2.sup.(n-1) the desired time. For example, if M is chosen to equal decimal state 5, the programming signal input will be 000101 in binary. State M+2.sup.(n-1) will thus equal M+32 which equals 37 (in decimal) which, in turn, equals 100101 in binary. 
     These two decoded outputs are allowed to toggle latch 21 so as to produce a square wave which goes low at state M and high at M+2.sup.(n-1). This square wave may thus provide the reference &#34;tone&#34; which is input at 13b into phase detector 13. 
     Phase detector 13, in this embodiment, receives two square wave inputs and produces a difference signal which corresponds to the phase difference between these input tones. The difference signal is provided to a conventional low pass loop filter 23 which thus, provides a filtered (i.e., averaged over a short time) varying control signal input to control VCO 15 which generates a 2 n  times higher frequency signal which is adjustably &#34;phase locked&#34; to the input SAT tone. 
     Since the output of VCO 15 has a controlled phase shift with respect to the incoming SAT, it may be used to generate a phase controlled transponded SAT (i.e. transmitted back to a fixed cellular station) which is, within specified limits, equal in phase to the incoming SAT. In the embodiment of FIG. 1, this desired output is obtained by use of a conventional sine wave generator 25 which is controlled by counter 17 which is, of course, already synchronized with the output of VCO 15. For example, some or all of the bits from each one of the plurality of n-bit words cyclically generated by counter 17 may be used by sine wave generator 25 to produce an output tone at the fundamental frequency having a phase which is locked and adjusted with respect to the received input SAT tone. Alternatively, other suitable conventional output waveform generator may be directly driven by the VCO output (as indicated by dashed lines) as will be understood by those in the art. 
     All of the components depicted in FIG. 1 are capable of integration into an integrated circuit, with the possible exception of loop filter 23 and the frequency determining components of VCO 15 (e.g. resistor 27 and capacitor 29). Thus, the circuit can, for the most part, be integrated into a CMOS IC with ease. Such an integrated circuit could be mass produced and each one, in use in a particular mobile transceiver, is then provided with a separate programming signal input (e.g. as supplied from a ROM specially programmed at the factory for that particular transceiver) as suitably determined from the requirements unique to that particular mobile station. If desired, such requirements can be continuously or repetitively automatically determined by suitable control circuits to maintain the programming signal at the proper value for existing conditions. 
     FIG. 2 is a schematic diagram of one alternative embodiment of the present invention where like components are designated by like reference numerals with respect to the embodiment of FIG. 1. 
     The construction and method of operation of the FIG. 2 embodiment is essentially the same as the FIG. 1 embodiment except that instead of a latch 21 and a phase detector 13, a conventional edge-sensitive phase detector 31 is provided. Edge sensitive phase detector 31 detects the leading edge of one programmed output of decoder 19. This leading edge corresponds to programmed state M. Thus, edge sensitive phase detector 31 directly compares the square wave reference tone with the square wave input tone to provide the difference signal to loop filter 23. 
     Those skilled in the art will recognize that counter 17 may itself be controlled to skip some counting states (when so commanded) and to thus make its MSB output equivalent to the phase shifted output of decoder 19. There are no doubt other ways to introduce controlled phase shift into the PLL circuit so as to achieve the desired result. 
     FIG. 3 is a schematic diagram of the presently most preferred embodiment of the invention. Again, like components are designated by like reference numerals with respect to FIG. 1. 
     The SAT is received from a discriminator (not shown) which feeds the received tone through a switched capacitor bandpass filter 39. In most cellular communication operations, the SAT is transmitted at a frequency of 5970 Hz, 6000 Hz, or 6030 Hz. Thus, switched capacitor bandpass filter 39 provides a square wave input tone to phase detector 13 having a corresponding one of these frequencies (i.e. approximately 6000 Hz). VCO 15 generates a 2 n  times higher frequency (e.g. 2 n  =64) signal (e.g. having a frequency of approximately 384 kHz). This higher frequency signal is conventionally frequency divided by a factor of 2 6  =64 by counter 17 to produce the desired approximately 6000 Hz fundamental frequency. To avoid potential timing problems, the time least significant bit portions of counter 17 preferably comprise a conventional 2-bit synchronous counter while the remaining (e.g. four) more significant bit stages comprise a simple ripple counter. 
     A conventional programmable n-bit state decoder 19 is connected to the counter 17 and can be set to provide a decoded output upon occurrence of any desired one(s) of the 2 n  states. The desired decoding state(s) programming is conventionally provided through a programming input by means of a suitable 6-bit programming signal. For example, when state M is chosen, the decode &#34;1&#34; output may be caused to go &#34;high&#34; when the 6-bit counter word corresponding to state M is detected. Decode &#34;2&#34; will go high when the 6-bit counter word corresponding to state M+2.sup.(n-1) modulo n is detected. Thus, complementary signals are provided on decode &#34;1&#34; and decode &#34;2&#34; which correspond to a phase adjusted signal (with respect to actual VCO output) operating at the fundamental incoming SAT frequency. The decode &#34;1&#34; and decode &#34;2&#34; signals are provided to an RS latch including NOR gates 45. As can be seen from FIG. 3, the output of the RS latch 21 will be a square wave reference tone having an adjusted phase and a frequency equal to the fundamental frequency. This reference tone is then fed to phase detector 13 where its phase is compared to the phase of the input tone. A difference signal corresponding to the phase difference is then provided through loop filter 23 to control VCO 15. 
     Conventional Walsh function circuit 25 may receive the three least significant bit outputs from the 6-bit counter 17. 
     While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is understood that the invention is not to be limited to the disclosed embodiments but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit of the appended claims which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures.