Abstract:
The code error detecting method uses the code error detecting apparatus which comprises a sector buffer memory for storing various kinds of data, an adder circuit for performing exclusive OR addition of data, a CRC generator/checker for producing error check parities by dividing a result of addition performed in the adder circuit by a predetermined generator polynomial, a temporary memory for storing the error check parities, and an error correction circuit for calculating error correction parities which are used to correct an error of the data. At the time of recording, the data incorporating various parities produced in the code error detecting apparatus is recorded on an optical disk, and, at the time of reproducing, the data reproduced and stored in the sector buffer memory is corrected by using the reproduced error correction parities, and the error check parities are obtained by using the CRC generator/checker. Then, the error check parities thus obtained are compared with the reproduced error check parities stored in the sector buffer memory to thereby detect a code error of the data.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a code error detecting method of correcting data in a data file apparatus employing an optical disk of a write once type or an erasable type. 
     DESCRIPTION OF THE PRIOR ART 
     Recently, an optical disk having a characteristic capable of recording a great amount of data with a high recording density in a non-contact fashion has attracted attention in the field of memories including an auxiliary storage of a computer. As an application of the optical disk, there have been data files of a write once type in which data can be only once additionally written and of an erasable type in which data can be rewritten as many times as necessary. Efforts have been made for the development of recording methods as well as servo methods in various manufacturers and institutes. 
     In a data file using an optical disk, the optical disk has a diameter of 5 1/4 (5.25) or 3.5 inches and tracks in a concentric or spiral form with a track pitch of about 1.6 micrometers (μm). A track is subdivided into a plurality of sectors constituting a circumference thereof such that a plurality of data items including symbols each comprising eight bits are written in the sector. For example, in a case of a 5.25 inch optical disk, there are disposed 18,750 tracks, a track includes 17 sectors, and the data capacity of each sector available for the user is 1024 bytes. In a data file having such an optical disk, the rotary speed of the disk is a constant angular speed of from about 1800 rpm to about 3600 rpm, and a semiconductor laser associated with a wavelength of about 830 nanometers (nm) is adopted as a light source. With a light beam of which a light spot is focused to at most about 1 μm, data are recorded on the tracks in the form of projected or depressed portions (of the write once type) or according to directions of magnetization perpendicular to a disk surface of the optical disk (of the erasable type). In an operation to record or to reproduce data on or from the optical disks as described above, if there exists any dust, fingerprint, or damage on the disk surface, data cannot be correctly written thereon or data previously correctly written thereon cannot be appropriately read out therefrom in some cases, which is in general referred to as a code error. To cope with this code error, there are added redundant data, namely, parity data other than the data utilized by the user so as to detect a code error for error correction so that the correct data can be read even if such a code error takes place. In the data reproduction, with the error correction processing employing the above error correction code, the inherent code error data of 10 -4  to 10 -5  of reproduced data on an optical disk can be reduced to at most 10 -12  after the error correction processing is effected. According to this method, there is developed the same performance as that of the hard disk conventionally used. In the data file employing an optical disk of this kind, since the minimum unit of data treated by the user is a byte, the Reed-Solomon code is used in many cases in which the error correction can be achieved in byte unit and a lot of data can be corrected with reduced redundancy. Although the Reed-Solomon code enables error detection and correction to be efficiently accomplished, it has been known that mis-detection and mis-correction of an error occur with a certain probability. Consequently, in order to increase the reliability of reproduced data with respect to the error, in addition to the error correction codes described above, there are added several bytes of error detection codes only for all data in a sector which can be used by the user, for example, 1024 bytes. The several bytes are almost ignorable as a redundancy measure. With the duplicated error detection countermeasurements, for example, even when mis-detection and mis-correction of an error occur in a error correction processing of the first stage, the code error can be appropriately detected by a code error detection processing of the second stage, thereby retaining high reliability. 
     As an example of the data error correction and detection method for a data file employing the optical disk, the proposal under the title of &#34;ENCODING SPECIFICATION FOR THE X3B11-APPROVED EDAC CODE FOR 5 1/4 INCH OPTICAL STORAGE DEVICES&#34;, Nov. 4, 1986 was submitted to the standardization committee for optical disk devices, ANSI X3B11. 
     According to this method, in a recording operation, a sector of user data including 1024 symbols and control data symbols are arranged in a memory area to configure a rectangular form with 10 vertical symbols ×104 horizontal symbols in which four symbols including the last data symbol in the 104-th row are assigned as the parity data for the error check of the user data. The error check parity data of this example is generated as follows. First, ten data symbols in each column among the data symbols in byte units arranged in the first column through the 103th column are subjected to exclusive OR addition. Further, in the 104-th column, exclusive OR addition of data of six symbols excepting the error check parity is performed, thereby generating, in total, 104 error check data in byte units. An error check information polynomial is constituted by the 104 data symbols in byte unit. The error check information polynomial is divided by a generator polynomial comprising four predetermined symbols of the Reed-Solomon code so as to use a residue or remainder resulting from the division as the error check parity and to assign the error check parity to the last four symbols in the 104-th column. This type of error detection method is known as the cyclic redundancy check code (CRC), and it is described in detail, for example, in Elwyn R. Berkelamp: &#34;ALGEBRAIC CODING THEORY&#34;, Chapter 5, pages 119-145, McGraw-Hill Book Company and in W. Wesley Peterson and E. J. Weldon, Jr.: &#34;ERROR-CORRECTING CODES&#34;, Second Edition, Chapter 8, pages 206-268. 
     In the prior art example, in a reproducing operation, the data are arranged, like in the case of the recording operation, in the form having 10 vertical symbols ×104 horizontal symbols. In the respective data symbols in byte unit arranged in the first column through the 103rd column, an exclusive OR addition of data of ten symbols in each column is performed. In the 104-th column, an exclusive OR addition of data of six symbols excepting the symbols for the error check parity is performed. Thus, an error check information polynomial for the total 104 data symbols in byte unit is obtained. The information polynomial is divided by the generator polynomial used in the recording operation so as to obtain a residue or remainder. The remainder is then compared with the error detection parity of the 104-th column added in the recording operation and corrected in the reproducing operation, thereby detecting the presence or absence of the error. In this method, for the generation of the information polynomial, an exclusive OR addition of data of ten or six symbols in each column is performed. Consequently, there arises a disadvantage that even when a plurality of errors occur in the respective columns, there may possibly be obtained a result identical to the result computed when there does not exist any error. For example, even when two data items having the same bit constitution are included in a column and the same error occurs on bits located at the same positions of the respective data items, it is natural that the same result of the exclusive OR addition of ten symbols is attained for this column in this case and in a case where there does not exist any error in the data item. However, in the error correction method of the data file utilizing the optical disk of this kind, there are provided error correction codes other than those adopted in the error detection method described above so as to correct an error of each data in advance, thereby greatly minimizing the chance of the operation in which the error described above is not appropriately detected. In the method of the prior art example, with respect to the error correction and the CRC error detection code, the generator polynomial differs, however, the Reed-Solomon code in byte unit of the same primitive polynomial is used, and hence various error detection methods can be considered by combining the error correction code with the CRC error detection code. In the proposal to ANSI X3B11 already described, however, the error detection method has not been presented. In general, the error detection is accomplished in the prior art example as follows. Namely, as described above, in the reproducing operation, firstly, the reproduced data and the error correction parity are arranged in the form having ten vertical symbols ×120 horizontal symbols like in the recording operation, by using 16 parity data items additionally disposed in advance for the error correction of the data associated with 104 user data symbols in a horizontal row, a maximum of eight errors are corrected for each row, and, for each data in byte unit in a range from the first column to the 103rd column, an exclusive OR addition of ten symbols in each column is effected and an exclusive OR addition six-symbol data of the 104-th column excepting the error detection parity so as to obtain an error check information polynomial for the total 104 data symbols in byte unit. The information polynomial is divided by the same generator polynomial used in the recording operation so as to compare the residue with the error correction parity in the 104-th column. If the residue is equal to the parity, it is judged that there does not exist any error. Otherwise, the existence of an error is determined. As the error detection method, there has been adopted a method in which all data items are written in the memory during the reproducing operation as shown in FIG. 1 and thereafter an error correction processing is performed on the data such that the same error detection processing is effected when the data thus corrected are transferred to the user side, for example, a host computer. 
     In this method, however, a result of the error detection is attained after all data items corrected are entirely transferred to the host computer, which causes a disadvantage in some cases. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide an error detection method of detecting a code error in a data file employing an optical disk in which, during a reproducing operation, an error location and an error pattern obtained in an error correction processing are used to correct the data constituting an information polynomial or a reception polynomial, thereby completing the error detection before the data are transferred to the user (host computer). 
     In order to achieve the above object, there is provided a method according to the present invention in which, in a recording operation, data including user data and control data representing addresses of an optical disk where the data are to be written is arranged in a form with n vertical symbols ×m horizontal symbols, an exclusive OR addition is effected on n symbols in each vertical column ranging from the first column to the (m-1)-th column, and an exclusive OR addition is achieved on (n-t) symbols of the m-th column excepting t symbols including the last symbols, thereby establishing an information polynomial of data including the m symbols thus obtained. The information polynomial is then divided by a generator polynomial prepared beforehand for error detection and a residue obtained as a result of the division is arranged as an error detection parity in the t-byte location In a reproducing operation, if a code error is found in the data of the m symbols of a horizontal row selected from the data constituted with n vertical symbols ×m horizontal symbols or in data of (m-1) symbols excepting the control data, an error correction is accomplished by using an error correction code separately determined and a correction is carried out on the error detecting information polynomial for the data subjected to the error correction based on a location and a pattern associated with the error data obtained in the error correction, thereby detecting an error according to the result of the correction. 
     In the above configuration, when the error correction is completed on the data in a sector, a code error detection on the corrected data is also completed almost at the same time, and hence the code error detection can be carried out before the data are transferred to the user (host computer) and all processing can be completely effected within a period of time associated with the sector. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a block diagram showing a conventional system which performs code error detection on a data file using an optical disk; 
     FIG. 2 is a block diagram showing a system of an embodiment of the present invention which performs code error detection on a data file using an optical disk; and 
     FIG. 3 is an explanatory diagram showing a data arrangement for performing code error detection in an embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The illustration of FIG. 2 includes a host computer 1, an interface 2, a digital modulation circuit 3, a digital demodulation circuit 4, a sector buffer memory 5, an adder 6 for performing an addition of exclusive OR results of ten symbol data or 6 symbol data used in making code error check, a code error detection code (CRC) generator/checker 7, an error correction circuit 8, an encode/decode change-over switch 9, a data bus 10, an optical disk 11, and a temporary memory 12. 
     Furthermore, in the data arrangement of FIG. 3, Di,j (0≦i≦9, 0≦j≦103) designates user data and control data, Ei,k (0≦k≦15) denotes the error correction parity, Cu (0≦u≦3) indicates the error check parity, Pv (0≦v≦103) stands for data constituting an error check information polynomial, and Ri,s (0≦s≦3) designates data constituting the residue polynomial of each row. 
     The denotation of symbols used in the respective cases are shown hereunder by taking the error correction parity symbol C as an example: 
     In the case of recording, &#34;C&#34; is used simply; in the case of reproducing, &#34;C&#34; is used; in the error correction, &#34;C&#34; is used; and when obtained by calculation, &#34;C&#34; is used. 
     First, in a recording operation, from the host computer 1, the user data and control data Di,j are supplied as symbols in byte unit via the interface 2 and the data bus 10 to the sector buffer memory 5 in the order of D 0 ,103, D 1 ,103, D 2 ,103, . . . , D 9 ,103, D 0 ,102, . . . D 9 ,102, . . . , D 0 ,1, D 1 ,1, D 2 ,1, . . . , D 9 ,1, D 0 ,0, D 1 ,0, D 2 ,0, D 3 ,0, D 4 ,0, and D 5 ,0 so as to be stored in the form with ten vertical symbols ×104 horizontal symbols as shown in FIG. 3. At the same time, the data items are supplied to the adder circuit 6, which in turn effects an addition of exclusive OR results as follows. ##EQU1## 
     These data items represented by Pv (0≦v≦103) are inputted to the CRC generator/checker 7 in the order of P 103 , P 102 , . . . , P 0  so as to be divided by a predetermined four-symbol generator polynomial G(x). A residue R(x) resulting from the division is produced as error check parity data symbols C 3  to C 0 , which are then written in the sector buffer memory 5. Subsequently, data items of a horizontal row including D 0 ,j, D 1 ,j, . . . , D 5 ,j (0≦j≦103); D 6 ,j and C 3 ,D 7 ,j and C 2 , D 8 ,j and C 1 , D 9 ,j and C 0  (1≦j≦103) are read out from the sector buffer so as to compute the error correction parity Ei,k in the error correction circuit 8 and the parity Ei,k is then written in the sector buffer memory 5. Finally, the data items of the sector buffer memory 5 are read out in the order of D 0 ,103, D 1 ,103, D 2 ,103, . . . , D 9 ,103, D 0 ,102, D 1 ,102, D 2 ,102, . . . , D 9 ,102, . . . , D 0 ,1, D 1 ,1, D 2 ,1, . . . , D 9 ,1, D 0 ,0, D 1 ,0, D 2 ,0, . . . , D 5 ,0, C 3 , C 2 , C 1 , C 0 , E 0 ,15, E 1 ,12, E 2 ,15, . . . , E 9 ,15, E 0 ,14, E 1 ,14, E 2 ,14, . . . , E 9 ,14, . . . , E 0 ,0, E 1 ,0, E 2 ,0, . . . , E 9 ,0 so as to be supplied via the encode/decode switch 9 to the digital modulation circuit 3, which in turn adds signals such as a synchronization signal and records the resultant data items on the optical disk 11. 
     On the other hand, in a reproducing operation, data items read from the optical disk 11 are demodulated by the digital demodulation circuit 4 and are supplied via the encode/decode switch 9 to the sector buffer memory 5. The data items are written therein in the form with ten vertical symbols ×120 horizontal symbols, like in the recording operation, as shown in FIG. 3. At the same time, the data items are inputted to the adder 6, which then performs an addition of exclusive OR results as follows. ##EQU2## Where,   indicates that the data bearing this mark appear in a reproducing operation. These data Pv (0≦v≦103) are written in a temporary memory 12. Next, the data D 0 ,j (0≦j≦103) and E 0 ,k (0≦k≦15) are sequentially read out in the direction from the left side to the right side in FIG. 3 and are supplied to the error correction circuit 8. In the error correction circuit 8, a location and a pattern of the error are computted. Then, data corresponding to the error location are read from the sector buffer memory 5 and are inputted to the error correction circuit 8. Thereafter, an exclusive OR addition is effected for the error pattern and the above data, and the resultant data are written again in the sector buffer memory 5 at the original address, thereby effecting the error correction. Subsequently, Pv corresponding to the error location is read from the temporary memory 12 and is then supplied to the error correction circuit 8. An exclusive OR addition is effected for the error pattern and the above data, and the resultant data are written again in the temporary memory 12 at the original address. Then, the above operation is repeated for i (1≦i≦9) and thus it is repeated ten times in total. Finally, the data are read from the temporary memory 12 in the order of P 103 , P 102 , . . . , P 1 , and P 0  and are inputted to the CRC generator/checker 7, which conducts a division thereof by a predetermined generator polynomial G(x) that has also been used in the recording operation. An explanation of the mark   soon follows. As a result, the residue R(x) is attained as C 3  to C 0 , which are compared with the error correction parity R(x) subjected to the error correction, namely, C 3  to C 0  read from the sector buffer memory 5 and supplied to the CRC generator/checker 7. If a matching condition results, the system determines that there does not exist any error. Otherwise, the existence of an error is assumed. When the error is not found in this judgement, from the sector buffer memory 5, the user data Di,j are transferred via the data bus 10 and the interface 2 to the host computer 1. When the error is assumed, an error message is transmitted to the host computer 1. In the above description, the mark   designates data that have been subjected to error correction in the reproducing operation, and the mark · indicates data obtained through a computation after the error correction. In this case, as the generator polynomial G(x) of the error check parity, the following is used when the primitive element of the finite field or Galois field obtained through a primitive polynomial m(x)=x 8  +x 4  +x 3  +x 2  +1 is assumed to be α. ##EQU3## Alternatively, as the generator polynomial G(x) of the error check parity, the following is used when the primitive element of the finite field or Galois field obtained through a primitive polynomial m(x)=x 8  +x 5  +x 3  +x 2  +1 is assumed to be α. ##EQU4## Here, the generator polynominal G(x) is in byte unit. However, the generator polynominal G(x) need not be necessarily associated with the byte unit, for example, there may also be employed G(x)=x 32  +x 23  +x 21  +x 11  +x 2  +1 associated with the binary unit. In a case where the byte-unit generator polynominal is used, the error check parity Cu is here computed so as to satisfy the following expression. ##EQU5## 
     When using a binary-unit generation polynomial the residue is obtained in the same way as the conventional method on assumption that the 8 bit data including ##EQU6## are continuous bit streams, respectively, and then the result need only be divided into 8 bit units. 
     In addition, in place of the operation as described above in which the error check parity R(x), namely, C 3  to C 0  that are computed and are added in the recording operation and that are subjected to the error correction processing are compared with R(x), namely, C 3  to C 0  attained through a computation in the reproducing operation so as to judge the presence or absence of the error, it is possible to supply the CRC generator/checker 7 with Pu from the temporary memory 12 and R(x) from the sector buffer memory 5 in the sequence of P 103 , P 102 , . . . , P 0 , C 3 , C 2 , C 1 , and C 0  so as to be divided by the generator polynomial G(x), thereby determining the presence or absence of an error from the fact that the residue is not 0 or 0, respectively. 
     Next, a second embodiment of this invention will be explained. 
     In the first embodiment, the data items constituting the error check information polynomial are beforehand generated through an addition of exclusive OR results of the ten byte or 6 byte reproduction data in the column direction of FIG. 3 and thereafter by using the error location and the error pattern obtained during the error correction associated with each row, a correction is also effected on the data items constituting the information polynomial so as to accomplish the error detection. In contrast with the first embodiment, according to the second embodiment, an error correction is first performed on data in an N-th row of FIG. 3, and an addition of exclusive OR results of the data of the N-th row thus corrected and the data of the (N+1)-th row not corrected is conducted for each symbol located in the same column so as to generate data items constituting a provisional information polynomial. Subsequently, error corrections are repeatedly performed on the data of the (N+1)-th row and the data items associated with the provisional information polynomial so as to effect a correction of the information polynomial, thereby carrying out the error detection. In this situation, the operation to record the data is the same as that of the first embodiment. In the recording operation, data read from the optical disk 11 are demodulated by the digital demodulation circuit 4 and are then written via the encode/decode change-over switch 9 in the sector buffer memory 5 in the data arrangement, like in the recording operation, constituted by ten vertical symbols ×120 horizontal symbols as shown in FIG. 3. Next, the data and the error correction parity including D 0 ,103, D 0 ,102, . . . , D 0 ,0, E 0 ,15, . . . , and E 0 ,0 of the upper-most row of FIG. 3 are read from the sector buffer memory 5 and are then supplied to the error correction circuit 8. At the same time, data items D 0 ,103, D 0 ,102, . . . , and D 0 ,0 are written in the temporary memory 12. In the error correction circuit 8, the location and the pattern of the error are computed for the error correction. Thereafter, the error data corresponding to the error location are read from the temporary memory 12 and are delivered to the error correction circuit 8 which then effects an exclusive OR addition of the error pattern and the data thus read out, thereby performing the error correction. The resultant data are written again in the temporary memory 12 at the original address. In this operation, in the error correction circuit 8, the data D 0 ,103 is inputted to an input terminal of a syndrome generator and to an input terminal of an exclusive OR circuit. At the same time, the corrected data D 0 ,103 is read from the temporary memory 12 and is supplied to the other input terminal of the exclusive OR circuit of the error correction circuit 8, and then a computation of P 103  =D 0 ,102 ⊕D 0 ,103 is accomplished, and the obtained data are written again in the temporary memory 12 at the original address. Subsequently, in a similar way, while D 0 ,102, D 0 ,101, . . . , and D 0 ,0 are sequentially supplied to the syndrome generator and the exclusive OR circuit, computations of P 102  =D 0 ,102 ⊕D 0 ,102, P 101  =D 0 ,101, ⊕D 0 ,101, . . . , and P 0  =D 0 ,0 +D 0 ,0 are effected and the resultant data items are written again in the temporary memory 12 at the respective original addresses. After these operations are completed, the error location and the error pattern are computed for the data and the error check parity in the second row of FIG. 3. Data corresponding to the error location are read from the sector buffer memory 5 and are then delivered to the error correction circuit 8, which turn effects an exclusive OR addition of the error pattern and the data thus read out, thereby achieving the error correction. The resultant data are written again in the sector buffer memory 5 at the original address. Subsequently, Pu corresponding to the error location are read from the temporary memory 12 and are fed to the error correction circuit 8, which in turn effects an exclusive OR addition of the error pattern and the data of Pu thus read out, thereby performing the error correction. The resultant data are written again in the temporary memory 12 at the original address. Following this operation, for the data from the third row to the tenth row, the similar processing is repetitiously carried out. When the error correction and the correction of data items constituting the information polynomial for the CRC computation are completed for the data of tenth row, there are obtained in the temporary memory 12 the data items constituting the information polynomial for the CRC computation which data items are identical to those of the first embodiment. 
     Next, a third embodiment of the present invention will be explained. 
     In the third embodiment different from the first and second embodiments, in a reproducing operation, the data read from the optical disk 11 are written in the sector buffer memory 5, like in the recording operation, to form a shape constituted by ten vertical symbols ×120 horizontal symbols. Next, the data and the error correction parity of the first horizontal row of the upper-most line of FIG. 3 including D 0 ,103, D 0 ,102, . . . , D 0 ,0, E 0 ,15, . . . , and E 0 ,0 are read from the sector buffer memory 5 and are then inputted to the error correction circuit 8, which in turn effects an error correction for the received data and parity. The corrected data are thereafter written again in the sector buffer memory 5 at the original address. Subsequently, the corrected data D 0 ,103, D 0 ,102, . . . , and D 0 ,0 are read from the sector buffer memory 5 so as to be supplied to the CRC generator/checker 7, which divides the data by a predetermined generator polynomial G(x) to obtain a residue R 0  (x), namely, C.sub. 0,3, C 0 ,2, C 0 ,1, and C 0 ,0 to be stored in the temporary memory 12. Similarly, for the rows ranging from the second row to the sixth row, there is obtained a residue for each column, namely, R 1  (x) to R 5  (x) including C 1 ,3, C 1 ,2, C 1 ,1, C 1 ,0, . . . , C 5 ,3, C 5 ,2, C 5 ,1, C 5 ,0, which are then written in the temporary memory 12. 
     In the almost similar fashion, the residue is obtained for each of the rows ranging from the seventh row to the tenth row, which is different from that of each of the rows ranging from the first row to the sixth row. Namely, as can be seen from FIG. 3, the number of data items of each row is smaller than that of each row associated with the rows ranging from the first row to the sixth row by one symbol and hence the computation is carried out on assumption that .0. data exists in that location. In this fashion, there are obtained the residues R 6  (x)-R 9  (x), namely, C 6 ,3, C 6 ,2, C 6 ,1, C 6 ,0 to C 9 ,3, C 9 ,2, C 9 ,1, C 9 ,0. Finally, an addition of the exclusive OR results is effected on R 0  (x) to R 9  (x) as follows. ##EQU7## The error detection after this point is identical to that described in conjunction with the second embodiment. 
     It is necessary here to prove that the residues of the first and embodiment are equal to those of the third embodiment. For simplification of the description, it is assumed that there does not exist any error in a reproducing operation. Naturally, the essential properties are not lost by the above assumption. 
     In the embodiment of FIG. 3, the following expressions are obtained by assuming that the information polynominal and the generator polynominal of the first row of FIG. 3 are Mi(x) and G(x), respectively, and that the quotient polynominal and the residue polynominal obtained by dividing the information polynominal Mi(x) by the generator polynominal G(x) are Qi(x) and Ri(x), respectively. ##EQU8## 
     Assume here that an addition of the data R 0  (x) to R 9  (x) is represented by Rc(x), namely, ##EQU9## where, ##EQU10## 
     Here, the following relationship is satisfied in the first embodiment. ##EQU11## Consequently, the error check parity, namely, the residue polynominal of the first embodiment is expressed as follows. 
     
         R.sub.D (x)=x.sup.4 ·M(x)+Q.sub.D (x) G(x) 
    
     Let us check whether or not Rc(x)=R D  (x) is satisfied. ##EQU12## 
     Assuming here that G(x) is a polynominal of t degree, the expression on the left side is a polynominal of t-1 degree at most. On the other hand, if ##EQU13## the expression on the right side becomes a polynomial of degree t or more, which is inconsistent with the t-1 degree on the left side. Consequently, ##EQU14## must be satisfied. As a result, Rc(x)=R D  (x) is attained. That is, the error check parity of the first embodiment is identical to that of the third embodiment. 
     According to the third embodiment, after the error correction is performed on the data of each horizontal row of FIG. 3 so as to obtain the error check parity of each horizontal row, an addition of exclusive OR results is effected for the error check parity obtained for each horizontal row so that the result of the addition is compared with the error check parity obtained in the recording operation, thereby detecting the presence or absence of the error. Consequently, a relatively long period of time is required to accomplish the computation. Next, an embodiment for improving the above operation will be described. 
     In this embodiment, the data of a horizontal row of FIG. 3 are transferred from the sector buffer memory 5 to the error correction circuit 8, and then after the error correction is completed, the corrected data are written again in the sector buffer memory 5 at the original address Subsequently, the data of the second row are transferred from the sector buffer memory 5 to the error correction circuit 8, and then after the error correction is completed, the corrected data are written again in the sector buffer memory 5 at the original address. According to the error correction procedure in this embodiment, a syndrome is computed by using the data first transferred from the sector buffer memory 5. Next, based on the syndrome thus obtained, the error location polynomial and error evaluator polynomial are computed so as to obtain the error location and the error pattern therefrom. Error data corresponding to the error location are read from the sector buffer memory 5 and then an addition of exclusive OR results is effected between the error data and the error pattern so as to perform the error correction, thereby writing again the corrected data in the sector buffer memory 5 at the original address. In this operation, the sector buffer memory 5 is accessed only when the data of a horizontal row are transferred to the error correction circuit 8 to obtain the syndrome, when the error data are read out, and when the corrected data are rewritten. Namely, since the sector buffer memory 5 is not accessed when the error correction circuit 8 is computing the error location and the error pattern, this period of time is allocated to an operation to read from the sector buffer memory 5 the corrected data of the first row of FIG. 3 including D 0 ,103, D 0 ,102, . . . , and D 0 ,0, which are then inputted to the CRC generator/checker 7. In the CRC generator/checker 7, the data items are subdivided by the generator polynomial G(x) and the residue R 0  (x) is obtained as C 0 ,3, C 0 ,2, C 0 ,1, and C 0 ,0 so as to be written in the temporary memory 12. In the similar fashion, the error correction up to the tenth row is effected and C 1 ,3, C 1 ,2, C 1 ,0, . . . , C 8 ,3p, C 8 ,2, C 8 ,1 and C 8 ,0 as the residues R 1  (x) to R 8  (x) up to the ninth row are obtained, and they are written in the temporary memory 12. 
     Finally, the corrected data items D 9 ,103, D 9 ,102, . . . , D 9 ,0 of the tenth row are read from the secton buffer memory 5 so as to be supplied to the CRC generator/checker 7. In the CRC generator/checker 7, the residue R 9  (x) is obtained as C 9 ,3, C 9 ,2, C 9 ,1, and C 9 ,0. Next, the residues R 0  (x) to R 9  (x) are read from the temporary memory and are then inputted to the error correction circuit 8, which performs an addition of exclusive OR results of the residues R 0  (x) to R 9  (x) to thereby obtain the final error check parity data C 3 , C 2 , C 1 , and C 0 . These error check parity data are compared with the error check parity data C 3 , C 2 , C 1 , and C 0  which have been added to the 104-th column shown in FIG. 3 in the recording operation and for which error correction has been effected in the reproducing operation, thereby accomplishing the error detection. In an error correction code system, like that discussed in the present invention, which deals with an error correction code whose minimum inter-code distance is as great as 17, the processing to compute the error location and the error pattern requires relatively a long period of time. That is, the period of time associated with the processing above is sufficient for the system to read the data of a horizontal row from the sector buffer memory 5 and to transfer the data to the CRC generator/checker 7 so as to effect the processing. Furthermore, this method is of course applicable to the error check parity generation in the recording operation, if it is assumed that any error does not exist exactly in the reproducing operation. 
     Now, as already described with respect to the prior art example, in the method of producing an information polynomial by performing an addition of exclusive OR results of ten vertical symbols in each column among the data arranged in the form having ten vertical symbols and 104 horizontal symbols, if an even number of errors should occur at the same bit positions of the data having the same bit structure in a column, an addition of exclusive OR results of the ten vertical symbols in the column becomes completely identical to that obtained when there exists no error. Similarly, in an error detection method in which error correction is performed for each horizontal row so as to obtain an information polynomial by using data resulting therefrom, the information polynomial thus obtained is then divided by a generator polynomial to obtain a residue polynomial for each row, and finally the residue polynomials for respective rows are added together to effect error detection, for example, if all data in two rows are identical with each other and identical errors should occur at the same positions thereof, the two resultant residue polynomials become completely identical with each other, namely, an exclusive OR addition therefrom becomes identical to that obtained when there does not exist any error. In these cases, it results that the existence of such errors is overlooked. Although it is considered that such cases stand generally with low probability, if two separate code error detection methods are used in parallel to decide the existence of an error and if the existence of an error is detected by any one of the two methods, it is possible to assure high reliability. 
     While the present invention has been described with reference to the particular embodiments, it is not restricted by those embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change and modify the embodiments without departing from the scope and spirit of the present invention.