Abstract:
A cascaded integrator comb filter includes a first integrator that receives an input signal x[n] and provides an integrated signal, and a fractional integrator that also receives the input signal x[n] and provides a fractional integrated signal. A summer sums the integrated signal and the fractional integrated signal and provides a summed signal indicative thereof to a second integrator, which receives and integrates the summed signal to provide a second integrator output signal. A decimator unit receives the second integrator output signal and provides a decimated signal to a differentiator that receives the decimated signal and provides a differentiated signal.

Description:
PRIORITY INFORMATION 
     This patent application claims priority from German patent application 10 2007 046 181.1 filed Sep. 26, 2007, which is hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     The invention relates to a cascaded integrated comb (CIC) filter. 
     CIC filters are also known as moving time average (MTA) filters. An example of where CIC filters are employed is for sampling rate reduction, for example, to reduce the bandwidth while simultaneously decreasing the sampling rate by a whole-number factor R. In the simplest case, a CIC filter for decimating an input-side signal clock speed comprises an accumulator, which sums R samples and outputs the result every R clock cycle, and whose contents are thereupon set to zero. This can be formally described as a series circuit of an integrator, a decimation stage and a differentiator, an input signal being supplied to the integrator and being made available, on the output side thereof, to the decimation stage. The decimation stage reduces the signal clock speed by a factor of R so that f out =f in /R, and supplies the reduced-clock-speed signal to the differentiator. The differentiator processes the reduced-clock-speed signal and makes it available on the output side. A higher-order CIC filter contains additional integrators on the input and additional differentiators on the output. A disadvantage of such CIC filters is that a clock speed reduction is possible only for whole-number values of R, that is, that every R-th input-side sample value is made available by the decimation stage on the output side. 
     For symbol clock speed controls in purely digital demodulators for communications systems, it is advantageous to implement sampling of the input-side signal at the proper symbol time points, for example, even in between two sample values. At this time, however, no signal values are available. 
     It is known from the prior art to obtain intermediate values by interpolation. 
     Fractional interpolation has been accomplished with polyphase FIR filters in which every polyphase approximates an all-pass filter, for example, a filter in which every n-th sample value of the impulse response of the net filter is employed. A control device always chooses the polyphase that corresponds to a desired phase offset of the signal at each output value. This method, however, has the disadvantage that the coefficients need a relatively high resolution in bits in order to achieve adequate damping. This high resolution necessitates large multipliers for filter implementation. A further disadvantage is that a plurality of such multipliers are needed for such a filter and the storage of coefficients is inconvenient. 
     More recently, use of interpolating FIR (IFIR) filters has increased in which the number of polyphases is reduced by using polynomials to interpolate the final interpolation coefficients between distinct polyphases. While this reduces the storage requirement for the coefficients, it increases the necessary computing power and complicates the control of the filter. 
     There is a need for a CIC filter such that a fractional decimation of the sampling rate is possible in a simple and an efficient fashion. 
     SUMMARY OF THE INVENTION 
     According to an aspect of the invention, a cascaded integrator comb (CIC) filter includes a first integrator that receives an input signal x[n] and provides an integrated signal, and a fractional integrator that also receives the input signal x[n] and provides a fractional integrated signal. A summer sums the integrated signal and the fractional integrated signal and provides a summed signal indicative thereof to a second integrator, which receives and integrates the summed signal to provide a second integrator output signal. A decimator unit receives the second integrator output signal and provides a decimated signal to a differentiator that receives the decimated signal and provides a differentiated signal. 
     The first integrator which integrates in a well-defined time interval, may be analyzed in analog fashion. Consequently, the result of the first integration can be enlarged by a fractional increment. 
     In one embodiment, the fractional integrator contains an interpolation circuit that receives a fractional time increment from a timer circuit. This allows the fractional integrator to integrate a signal waveform over the fractional time increment between two sample values. Thus, it is possible to append a fractional integration increment to the time-discrete integration of the first integrator. 
     The interpolation circuit may be fashioned as a circuit for constant interpolation by holding of the value (“sample and hold”). This makes it possible to approximate the signal waveform and perform fractional integration with just one additional multiplier in the signal path. This multiplier is supplied with the input sample as well as the output signal of the timer circuit. The fractional integration increment is the result of the multiplication and is added onto the last result of the discrete integrator. 
     In another embodiment, a sampler determines and samples the output-side signal of the parallel circuit at time points determined by the timer circuit and makes it available on the output-side. With such a sampler, which can also be implemented for example as a sample and hold circuit, the output values after fractional integration has been performed are made available at the proper symbol time points and supplied, for example, to a further integrator. Such a procedure is meaningful because the further integrators of the CIC filter may operate at a whole-number multiple of the sampling rate of the output signal, independently of the first integrator. 
     These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  are block diagram illustrations of prior art CIC filters for decimating a symbol clock speed; 
         FIGS. 2A and 2B  are block diagram illustrations of integrator embodiments used in the CIC filters illustrated in  FIGS. 1A and 1B ; 
         FIG. 2C  is a block diagram illustration of a differentiator used in the CIC filters illustrated in  FIGS. 1A and 1B ; 
         FIG. 3  is a block diagram illustration of a CIC filter according to an aspect of the invention; 
         FIG. 4  is a block diagram illustration of the first integrator in the CIC filter in  FIG. 3 ; 
         FIG. 5  is a plot of a signal sequence of the CIC filter of  FIG. 3 ; 
         FIG. 6  is a block diagram illustration of an alternative embodiment CIC filter based on linear interpolation according to an aspect of the invention; and 
         FIG. 7  is a plot of a signal sequence of the CIC filter of  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIGS. 1A and 1B  illustrate prior art CIC filters  100 ,  120  respectively. Such prior art CIC filters generally include a series circuit of N integrators (e.g.,  102 - 104 ), a decimation stage  106  and N differentiators (e.g.,  108 - 110 ). If desired, the inner combination of integrator, decimation stage and differentiator can be implemented as a resettable accumulator. Referring to  FIG. 1A  the CIC filter  100  for symbol clock speed decimation includes three integrators, a decimation stage and three differentiators. An input signal x[n] on a line  112  is integrated three times by the series-connected integrators  102 - 104  and supplied to the decimation stage  106 . The output signal of the decimation stage  106  is supplied to the cascaded differentiators  108 - 110 , and output as an output signal y[n] on line  114 . This prior art CIC filter  100  with the decimation stage  106  has the disadvantage that only the input-side signal x[n], determined only from discrete sampling times, is available for decimation of the symbol clock speed. The decimation stage  106  can create a reduction of the symbol clock speed only by making, for example, every third sample value of the input signal x[n] available to the differentiator chain. 
       FIG. 2A  illustrates the integrator  102  as used in the prior art CIC filter  100  according to  FIGS. 1A and 1B . The discrete integrator  102  includes an analog adder  202  and a delay stage  204 . The analog adder  202  is supplied with the input signal x[n] as well as output signal y[N−1] delayed by one symbol clock cycle, so that its function can be described by the formula
   y[n]=y[n− 1]+ x[N]   
The transfer function H i (z) of the integrator  102  is accordingly
   H   I ( z )=1:(1− z   −1 ). 
     Referring to  FIG. 2B , the delay element  204  is positioned in the signal path, so that an advantage is achieved in terms of circuitry with regard to the path length in the circuit design. Accordingly, the transfer function of the integrator illustrated in  FIG. 2B  is
 
 H   I ( z )= z   −1 :(1− z   −1 ).
 
       FIG. 2C  illustrates an example of the discrete differentiator  108  that includes an analog adder  206  and a delay stage  208 . The adder  206  receives the input signal x[n] and input signal x[n−M] delayed by M clock cycles, and provides an output signal y[n] having the function
   Y   [n]=x[n]−x[n−M].    
The transfer function H c (z) of the differentiator  108 , in reference to the clock speed of integrators, which is a factor of R greater than that of the differentiators, is
   H   C ( z )=1− z   −RM . 
     In these formulas, M denotes the number of delay cycles and is as a rule 1 or 2, and R represents the decimation factor of the decimation stage. 
       FIG. 3  is a block diagram illustration of a CIC filter  300  according to an aspect of the invention having, for example, three integrators  302 - 304 , a decimation stage  306  and, for example, three differentiators  308 - 310 . The CIC filter  300  also includes a fractional integrator  312  connected in parallel with the first input-side integrator  302 . 
       FIG. 4  illustrates a more detailed circuit block diagram of a first circuit portion of the CIC filter  300  illustrated in  FIG. 3 , namely the parallel circuit of the first integrator  302  and the fractional integrator  312 . The input signal x[n] is supplied to the first integrator  302  and to the fractional integrator  312  connected in parallel. The fractional integrator  312  in this example is based on a sample and hold interpolation, such that it is built up from a multiplier  314 . The multiplier  314  receives the input signal and a fractional time increment α on a line  320 . A timer circuit  318  provides the fractional time increment α on a line  320 , which represents the deviation of the desired sampling time from the symbol clock speed. Thus the multiplier  314  provides a fractional integration increment on a line  322  that corresponds, in a graphical presentation, to a rectangle having the height of the last signal value and having a width α. This fractional integration increment and the output signal of the first integrator  302  are summed by adder  404 . This sum is made available on line  416  to the downstream integrator  303  ( FIG. 3 ), for example through a sampler  418  controlled by the timer circuit  318 . The sampler  418  advantageously does not forward to the downstream circuit parts all samples in which the timer circuit has separated a whole-number increment from the new fractional time increment α. 
       FIG. 5  illustrates an example of the output values y[n] of the integrator. If, for the decimation of the symbol clock speed, input-side signal x[n] is to be sampled at times when no discrete signal is present, no correct value for output signal y[n] of the integrator exists. In the present example, constant interpolation using a sample and hold (S&amp;H) circuit is employed for calculating an interpolated intermediate value for the integral. In the graphical presentation, for a sampling time point n+α, a fractional increment F=x[n]·α, for example the shaded rectangle, is added to the last valid output value  y [n] of the integrator. This procedure generates a further valid output value for the integral, which depending on the interpolation method is a good approximation to the actual value of the integral at this time. Higher interpolation methods, for example linear interpolation, are also meaningful depending on the properties of the input signal. 
       FIG. 6  illustrates an embodiment of a CIC fractional integration filter  600  based on linear interpolation. The embodiment of  FIG. 6  is substantially the same as the embodiment of  FIG. 4 , with the principal exception that the fractional interpolator  702  is provided for linear interpolation. The input signal x[n] is provided to a delay stage  704  and to a difference unit  706  that provides a signal indicative of the difference between the delayed input signal x[n−1] and the input signal x[n]. The difference signal on line  708  is multiplied by the fractional time increment α and then added to the output signal of the delay stage  704 . The sum is once more multiplied by the fractional time increment α by multiplier  710 , and the product is output to the adder  404 . 
       FIG. 7  illustrates the linear interpolation illustrated in  FIG. 6  with reference to a sequence of sample values. 
     Although the present invention has been illustrated and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail, may be made therein, without departing from the spirit and scope of the invention.