Abstract:
A method of controlling an inverter includes receiving a target waveform for output voltage of an inverter phase, calculating a phase bias for an inverter phase using the target waveform, biasing the target waveform using the phase bias, and generating a switching device command signal by comparing the biased target waveform to a carrier waveform. The switching device command signal has a switching patter that reduces midpoint current in an inverter input lead and common mode voltage in an inverter output lead.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to power conversion, and more particularly to inverters for converting direct current power into alternating current power. 
         [0003]    2. Description of Related Art 
         [0004]    Aircraft power systems commonly include power converters to convert power of one type to a type suitable for power-consuming devices coupled to the aircraft power distribution system. For example, rectifiers are generally employed to convert alternating current (AC) power into direct current (DC) power. Inverters are typically employed to convert DC power into AC power. One type of inverter commonly employed is such applications is the neutral-point-clamped (NPC) inverter. Neutral-point-clamped inverters are generally coupled to a DC power source with a DC link having a source lead and a return lead. An additional midpoint lead is created by the series connection of capacitors to the power source. The voltage differential between the source and returns leads and midpoint lead is generally about half the potential difference across the power source, thereby reducing the voltage rating of components required for the inverter. 
         [0005]    Some multilevel inverters can exhibit voltage imbalance across DC link leads. DC link capacitors are commonly employed to reduce voltage imbalance, generally with a first capacitor connected between the DC source lead and the midpoint lead and a second capacitor disposed between the DC return lead and the midpoint lead. The DC link capacitors are typically sized according to the voltage imbalance characteristic of a specific application. 
         [0006]    Such conventional methods and systems have generally been considered satisfactory for their intended purpose. However, there is still a need in the art for improved power converters. The present disclosure provides a solution for this need. 
       SUMMARY OF THE INVENTION 
       [0007]    A method of controlling an inverter includes receiving a target waveform for output voltage of an inverter phase, calculating a phase bias for an inverter phase using the target waveform, biasing the target waveform using the phase bias, and generating a switching device command signal by comparing the biased target waveform to a carrier waveform. The switching device command signal has a switching pattern that reduces midpoint current in an inverter input lead and common mode voltage in the inverter output leads. 
         [0008]    In certain embodiments biasing the target waveform further can include generating first and second reference signals using the target waveform. The method can also include adding the phase bias to the first reference signal and subtracting the phase from the second reference signal. The switching command signal can be an upper switch command signal for an upper switch of a phase leg of the inverter, and generating the upper switch command signal by comparing the first switching command signal to a first carrier wave. 
         [0009]    It is contemplated that an intermediate lower switch command signal can be generated using an inverse of the output of the first switching command signal and first carrier wave comparison, an intermediate upper switch command signal can be generated by comparing the second switching command signal to a second carrier wave, and a lower switch command signal can be generated using an inverse of the output of the second switching command signal and second carrier wave comparison for switches of the phase leg. 
         [0010]    In accordance with certain embodiments the target waveform can be one of a plurality of target waveforms for the inverter. For example, the inverter can be a three-phase inverter, the waveform can be an A-phase waveform, and the method can include receiving B-phase and C-phase target waveforms. The phase bias can be an A-phase bias, and the method can include calculating a B-phase bias and a C-phase bias. 
         [0011]    It is also contemplated that, in accordance with certain embodiments, calculating the phase bias further can include comparing an uncompensated midpoint duty cycle to a target midpoint duty cycle for a phase of the inverter. The uncompensated midpoint duty cycle for a phase of the inverter can be calculated by subtracting a 0 min function of the target waveform from a 0 max function of the target waveform. The target midpoint duty cycle for a phase of the inverter can be calculated by subtracting from one a maximum of an absolute value of the target waveform. 
         [0012]    A controller for an inverter includes a processor and memory. The memory is communicative with the processor and has recorded thereon instructions that, when read by the processor, cause the processor to receive a target waveform representative of output voltage of an inverter phase, calculate a phase bias for an inverter phase using the target waveform, bias the target waveform using the phase bias, and generate a switching device command signal by comparing the biased target waveform to a carrier waveform, wherein the switching device command signal reduces midpoint current in an inverter input lead and common mode voltage in the inverter output leads. 
         [0013]    These and other features of the systems and methods of the subject disclosure will become more readily apparent to those skilled in the art from the following detailed description of the preferred embodiments taken in conjunction with the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    So that those skilled in the art to which the subject disclosure appertains will readily understand how to make and use the devices and methods of the subject disclosure without undue experimentation, embodiments thereof will be described in detail herein below, wherein: 
           [0015]      FIG. 1  is a schematic view of an exemplary embodiment of a power system constructed in accordance with the present disclosure, showing a power converter with a controller; 
           [0016]      FIG. 2  is a schematic view of the converter of  FIG. 1 , showing the converter switches; 
           [0017]      FIG. 3  is a block diagram of the controller of the power converter of  FIG. 1 , showing the modules, module inputs, and module outputs used for generating the switch command signals; 
           [0018]      FIG. 4  is a logic flow diagram for the bias value generator module of the controller of  FIG. 3 , showing how the bias value generator module generates the bias values; 
           [0019]      FIG. 5  shows uncompensated midpoint duty cycle waveforms, a desired midpoint duty cycle waveform, and phase bias value waveforms generated by the bias value generator; 
           [0020]      FIG. 6  is a logic flow diagram for the reference signal generator of  FIG. 3 , showing how the reference signal generator generates separate upper and lower reference signals; 
           [0021]      FIG. 7  shows the phase voltage reference signal, the phase bias signal, and the upper and lower reference signals generated by the reference signal generator; 
           [0022]      FIG. 8  is a logic flow diagram for the switch command signal generator of  FIG. 3 , showing how the switch command signal generator produced switch command signals; 
           [0023]      FIG. 9  shows the reference signals overlaying carrier signals for generating pulse width modulated switch command signals produced by the switch command signal generator; and 
           [0024]      FIG. 10  shows the converter A-phase reference signal multiplied by one-half the DC input voltage, A-phase output voltage relative to the DC midpoint, common mode voltage of the converter, converter phase output currents, and DC midpoint lead current. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0025]    Reference will now be made to the drawings wherein like reference numerals identify similar structural features or aspects of the subject disclosure. For purposes of explanation and illustration, and not limitation, a partial view of an exemplary embodiment of an inverter controller in accordance with the disclosure is shown in  FIG. 1  and is designated generally by reference character  100 . Other embodiments of inverters and method of controlling inverters accordance with the disclosure, or aspects thereof, are provided in  FIGS. 2-10 , as will be described. The systems and methods described herein can be used for power conversion systems, such as inverters for converting direct current (DC) power into alternating current (AC) power such as in aircraft power distribution systems. 
         [0026]    Referring now to  FIG. 1 , power distribution system  10  is shown. Power distribution system  10  includes a DC power source  12 , a converter  14 , and an electrical load  16 . A DC link  18  with a plurality of leads couples DC power source  12  to converter  14 . An AC link  20  connected converter  14  with electrical load  16 . In the illustrated exemplary power system, electrical load  16  is a three-phase AC load connected to converter  14  with an A-phase lead  22 , a B-phase lead  24 , and a C-phase lead  26 . Exemplary converter  14  is a multilevel neutral-point-clamped inverter connected to DC power source  12  with a DC positive lead  28 , and a DC negative lead  32 . A first balancing capacitor C 1  is connected in series between DC positive lead  28  and a DC midpoint lead  30 . A second balancing capacitor C 2  is connected in series between DC negative lead  32  and DC midpoint lead  30 . 
         [0027]    In some applications, non-idealities in the operation of the some types of neutral-point clamped inverters can cause current flow through the DC midpoint lead to oscillate. One approach to address midpoint lead current oscillation is to increase the size of the balancing capacitors employed on the DC link. While suitable for its intended purpose, this approach may increase the weight of the power conversion system. An alternative approach is change the operation of the converter. However, this approach can impose a low-frequency common mode voltage at the inverter output (e.g., a voltage between the terminal illustrated with a ‘C’ in  FIG. 1  and ground), which can require larger weight capacitors and inductors within the common mode filter associated with the phase leads. Converter  14  includes a controller operatively associated with converter  14  to reduce (or cancel) both midpoint current and common mode voltage. 
         [0028]    With reference to  FIG. 2 , converter  14  is shown. Exemplary converter  14  generally includes a plurality of solid-state switches connected in series with one another and having freewheeling diodes connected in parallel with each switch. Clamping diodes are also arranged in series between phase legs and DC midpoint lead  30 . In this respect an A-phase leg  40  includes an upper switch  42 , a mid-upper switch  44 , a mid-lower switch  46 , and a lower switch  48  that each connected in series with one another between DC positive lead  28  and DC negative lead  32 . A first clamping diode  50  is connected in series between upper switch  42  and DC midpoint lead  30 , and a second clamping diode  52  is connected is series between lower switch  48  and DC midpoint lead  30 . A-phase lead  22  is connected between mid-upper switch  44  and mid-lower switch  46 . B-phase leg  54  and C-phase leg  56  are similar in arrangement as A-phase leg  40  with the distinction that B-phase leg  54  is connected to B-phase lead  24  and C-phase leg  56  is connected to C-phase lead  26 . 
         [0029]    Controller  100  is operatively connected to each of the solid-state switching devices of converter  14  for selectively connecting each of AC phase leads (i.e. A-phase lead  22 , B-phase lead  24 , and C-phase lead  26 ) with one of the DC leads (i.e. DC positive lead  28 , DC midpoint lead  30 , and DC negative lead  32 ) at a given moment in time for synthesizing AC power with predetermined frequency using constant frequency DC power. In this respect, command signals generated by controller  100  are used to control the AC output voltages generated by converter  14 . For example, controller  100  selectively connects each AC output voltage to positive DC lead  28 , DC negative lead  32 , or DC midpoint lead  30  as required in order to generate the desired AC output waveforms. 
         [0030]    Proper selection of the control signals allows controller  100  to reduce or eliminate midpoint current and common-mode voltages otherwise generated by power inverter  36 . In this way, midpoint current oscillation that could otherwise occur on DC midpoint lead  30  and/or common mode voltage that could otherwise occur at node ‘C’ with respect to ground within electrical load  16  are prevented. 
         [0031]    With reference to  FIG. 3 , a block diagram of an exemplary embodiment of controller  100  is shown. In the illustrated embodiment, controller  100  includes a bias value generator  102 , a reference signal generator  104 , a switch command signal generator  106 , and a carrier wave generator  108 . Controller  100  provides a method of simultaneously reducing or eliminating common-mode voltage and reducing (or eliminating) oscillations in the midpoint current flowing through DC midpoint lead  30 . Components included within controller  100  may be implemented as circuitry, software, or a combination of software and circuitry. 
         [0032]    Bias value generator  102  receives target waveforms (e.g., V A   _   REF , V B   _   REF , and V C   _   REF ) that represent predetermined output voltage targets for converter  14  (shown in  FIG. 2 ). The target waveforms may be generated by a motor control algorithm (e.g., field oriented control) that receives one or more feedback signals used to control the generation of the AC outputs. Examples of feedback signals include monitored AC output current, monitored AC output frequency, monitored DC link voltage, monitored DC link current, or a combination thereof. 
         [0033]    Bias value generator  102  generates bias value waveforms (e.g., A BIAS , B BIAS , and C BIAS ) that are associated with each phase of converter  14  (shown in  FIG. 2 ), and provides the bias value waveforms to reference signal generator  104 . Reference signal generator  104  receives the bias value waveforms and the target waveforms. Using the target waveforms and the bias waveforms, the reference signal generator generates a pair of reference signal waveforms (e.g., A_UP_REF and A_DWN_REF) for each of the phase legs of converter  14 , and provides the reference signal waveforms to switch command signal generator  106 . 
         [0034]    Switch command signal generator  106  receives reference signal waveforms. Switch command signal generator also receives first and second carrier waveforms (e.g. UP_CARRIER and DWN_CARRIER), and compares each of the reference signal waveforms to the carrier waveforms using a pulse width (PWM) comparison engine to generate command signals (e.g. A-Phase Switch Command Signals) for each of the switches of the phase legs of converter  14  (shown in  FIG. 2 ). The carrier waves may be triangle waves. The command signal may be a binary high-low signal that closes and opens the switch receiving the signal. 
         [0035]    With reference to  FIG. 4 , a logic flow diagram for bias value generator  102  is shown. Bias value generator  102  includes a low saturation block  110 , a high saturation block  112 , a consolidation block  114 , and a subtraction block  116 . Bias value generator  102  also includes an absolute value block  118 , a maximum value block  119 , and an invert and bias block  121 . 
         [0036]    Bias value generator  102  receives the phase target waveforms, e.g. V A   _   REF , V B   _   REF , and V C   _   REF , at low saturation block  110 , high saturation block  112 , and absolute value block  118 . Absolute value block  118 , maximum value block  119 , and invert and bias block  121  cooperatively generate a desired midpoint duty cycle waveform for all phases and provide the desired midpoint duty cycle waveform to subtraction block  116 . 
         [0037]    Low saturation block  110  generates a positive amplitude waveform corresponding to the received phase target waveforms by replacing negative waveform values with zeros, and provides the resulting waveforms, e.g. V A   _   0   _   MIN , V B   _   0   _   MIN , and V c   _   0   _   MIN , to consolidation block  114 . High saturation block  112  generates a negative amplitude waveform for corresponding to inverter phase by replacing positive values within each of the received target waveforms with zeros. This produces two waveforms per inverter phase. 
         [0038]    The positive amplitude and negative amplitude waveforms for each phase are provided to consolidation block  114 . For each phase, consolidation block subtracts the positive amplitude waveform output of low saturation block  110  and adds the negative amplitude waveform of high saturation block  112  to a constant value of  1 . The waveforms calculated by consolidation block  114  are thereafter provided as uncompensated midpoint duty cycle waveforms associated with each phase to subtraction block  116 . 
         [0039]    Subtraction block  116  subtracts the uncompensated midpoint duty cycle waveform for each phase from the desired midpoint duty cycle for each phase, the difference forming the phase bias for the phase.  FIG. 5  shows the exemplary uncompensated midpoint duty cycle waveform in chart A, the exemplary desired midpoint duty cycle waveform for all phases in chart B, and the exemplary phase bias waveforms in chart C. 
         [0040]    With reference to  FIG. 6 , a logic flow diagram for reference signal generator  104  is shown. Reference signal generator  104  includes a first low saturation block  120 , a difference block  124 , and a second low saturation block  130 . Reference signal generator  104  also includes a first high saturation block  122 , a summing block  126 , a second high saturation block  132 , and a divider-gain block  129 . 
         [0041]    For each phase of converter  14  (shown in  FIG. 2 ), reference signal generator receives the phase target output voltage waveform (e.g., V A   _   REF ) at both first low saturation block  120  and first high saturation block  122 . First low saturation block  120  replaces negative waveform values with zero, and provides the resulting waveform to difference block  124 . First high saturation block  122  replaces positive values in the phase target output voltage waveform with zero, and provides the resulting waveform to summing block  126 . Divider-gain block  129  also receives bias waveform (e.g. A-phase bias) from bias value generator  102  (shown in  FIG. 3 ), divides the waveform by 2, and provides the halved bias waveform to both difference block  124  and summing block  126 . 
         [0042]    Difference block  124  subtracts the halved bias waveform from the waveform received from first low saturation block  120  and provides the resultant waveform to second low saturation block  130 . Second low saturation block  130  replaces negative waveform values with zero and provides the resulting waveform to switch command signal generator  106  as a first reference signal (e.g., A_UP_REF) representative of a desired duty cycle for another switch of the converter phase leg. 
         [0043]    Summing block  126  adds the halved bias waveform from the waveform received from first high saturation block  122  and provides the resultant waveform to second high saturation block  132 . Second high saturation block  132  replaces negative waveform values with zero and also provides the resulting waveform to switch command signal generator  106  as a second switch reference signal (e.g., A_DWN_REF) representative of a desired duty cycle for another switch of the converter phase leg.  FIG. 7  shows an exemplary target phase output voltage waveform in chart D, an exemplary phase bias waveform in chart E, an exemplary first switch reference signal in chart F, and an exemplary second switch reference in chart G. 
         [0044]    With reference to  FIG. 8 , a logic diagram for switch command signal generator  106  is shown. Switch command signal generator  106  includes a first comparator block  134  and a second comparator block  136  for each phase of converter  14  (shown in  FIG. 2 ). First comparator block  134  and second comparator block  136  cooperate with one another to generate pulse width modulated command signals for the switches of the converter phase legs using first and second carrier waves and the reference signal waveforms provided by reference signal generator  104  (shown in  FIG. 3 ). 
         [0045]    First comparator block  134  receives both a first carrier waveform (e.g., UP_CARRIER) from a carrier waveform generator  108  (shown in  FIG. 3 ) and a phase first reference waveform (e.g. A_UP_REF). As illustrated if  FIG. 3 , the first carrier waveform is a triangle waveform. When the phase first reference waveform is greater than the first carrier waveform, an upper switch command signal toggles high and a mid-lower switch command signal toggles low, closing an upper switch of a phase leg of the converter (e.g., upper switch  42 , shown in  FIG. 2 ) and opening a mid-lower switch of the converter phase leg (e.g., mid-lower switch  46 , shown in  FIG. 2 ). 
         [0046]    Second comparator block  136  receives both a second carrier waveform (e.g., DWN_CARRIER) from carrier waveform generator  108  (shown in  FIG. 3 ) and a phase second reference waveform (e.g. A_DWN_REF). As illustrated in  FIG. 3 , the second carrier waveform is a also triangle waveform. When the phase second reference waveform is greater than the second carrier waveform, a mid-upper switch command signal toggles high and a lower switch command signal toggles low. This closes a mid-upper switch of the converter phase leg (e.g., mid-upper switch  44 , shown in  FIG. 2 ) and opens a lower switch of the converter phase leg (e.g., lower switch  48 , shown in  FIG. 2 ). 
         [0047]      FIG. 9  shows exemplary first reference and first carrier waveforms compared to one another in a chart H, an exemplary upper switch command signal in chart I, exemplary second reference and second carrier waveforms compared to one another in a chart J, and an exemplary mid-upper switch command signal in chart K. As will be appreciated, the mid-lower switch command signal is the inverse of the upper switch command signal. As will also be appreciated, the lower switch command signal is the inverse of the mid-upper switch command signal. 
         [0048]      FIG. 10  graphically shows output lead common mode voltage and DC midpoint lead current for converter  14  (shown in  FIG. 2 ). While each of the phase legs of the converter are inverting received DC power into a synthesized output three-phase AC current as shown in chart N, both common mode voltage and DC midpoint lead current are shown in charts M and O, respectively. In exchange for this performance, inverter controllers and methods of controlling inverter switches may employ greater switching frequencies that conventional inverter controllers and conventional methods of controlling inverter switches. For example, whereas conventional neutral-point clamped inverters typically switch for about one-half of the inverter fundamental period, embodiments of methods described herein may switch for more than one-half the inverter fundamental period. In certain embodiments, the inverter switching occurs throughout more than 80% of the inverter fundamental period, as illustrated in Chart L (shown in  FIG. 10 ). Thus, increased switching losses may be experienced to conventional inverter controller and inverter switch control methods. 
         [0049]    In embodiments described herein, inverter controllers and methods of controlling inverter switches can control power converters such that the integral of the DC midpoint lead current in a switching cycle is substantially equal to zero amps. This potentially prevents the DC link voltage balancing capacitors from the charging or discharging at different rates, and allows the capacitor voltages to remain balanced. 
         [0050]    In certain embodiments, the duty cycles of each phase leg conducting to the DC midpoint lead can be substantially equivalent. The sum of the currents flowing from and to the DC midpoint lead can also substantially zero, allowing the DC midpoint lead current to average zero in each switching cycle. 
         [0051]    In embodiments, the duty cycle for phase legs conducting to the DC midpoint lead can be reduced while maintaining the desired output voltages by increasing the duration intervals during of conduction to the DC positive and negative lead by equal amounts. This allows for the DC midpoint current flow average to be substantially zero, allowing for reduction in the size (e.g. weight) of DC link balancing capacitors typically required for a given application. Similarly, since little (or none) common mode low-frequency voltage is added, the size (weight) of the common mode inductors incorporated into the load can be also be reduced in size. 
         [0052]    The methods and systems of the present disclosure, as described above and shown in the drawings, provide for power converters with superior properties including reduced (or eliminated) DC midpoint lead current and common mode voltage on the AC output leads. While the apparatus and methods of the subject disclosure have been shown and described with reference to preferred embodiments, those skilled in the art will readily appreciate that changes and/or modifications may be made thereto without departing from the scope of the subject disclosure.