Abstract:
Disclosed is a pipelined motion estimation system and method. The pipelined motion estimation system includes a current frame input storage means for storing contents of a current frame and a previous frame input storage means for storing contents of one or more previous frames. A sum-of-absolute differences calculation module concurrently determines a best fit motion vector from a plurality of potential motion vectors where each of the plurality of potential motion vectors is based upon a pixel-based search pattern. A sum-of-absolute differences (SAD) logic block concurrently determines a minimum residual value from the plurality of motion vectors. The motion vector having the minimum residual value is used as a component in encoding video data.

Description:
TECHNICAL FIELD 
     The present disclosure related generally to video encoding, and more particularly to techniques for estimating motion in video compression systems. 
     BACKGROUND ART 
     Video images have become an increasingly important part of communications in general. The ability to nearly instantaneously transmit still images, and particularly, live moving images, have greatly enhanced global communications. 
     In particular, videoconferencing systems have become an increasingly important business communication tool. These systems facilitate meetings between persons or groups of persons situated remotely from each other, thus eliminating or substantially reducing the need for expensive and time-consuming business travel. Since videoconference participants are able to see facial expressions and gestures of remote participants, richer and more natural communication is engendered. In addition, videoconferencing allows sharing of visual information, such as photographs, chars, and figures, and may be integrated with personal computer applications to produce sophisticated multimedia presentations. 
     To provide cost-effective video communication, the bandwidth required to convey video must be limited. The typical bandwidth used for videoconferencing lies in the range of 128 to 1920 kilobits per second (Kbps). Problems associated with available videoconferencing systems as these systems attempt to cope with bandwidth limitations include slow frame rates, which results in a non-lifelike picture having an erratic, jerky motion; use of small video frames or limited spatial resolution of a transmitted video frame; and a reduction in the signal-to-noise ratio of individual video frames. Conventionally, if solutions such as reduced video frame size or limited spatial resolutions are not employed, higher bandwidths are required. 
     At 768 Kbps, digital videoconferencing, using state-of-the-art video encoding methods, produces a picture that may be likened to a scene from analog television. Typically, for most viewers, 24 frames per second (fps) are required to make video frames look fluid and give the impression that motion is continuous. As the frame rate is reduced below 24 fps, an erratic motion results. In addition, there is always a tradeoff between a video frame size required and available network capacity. Therefore, lower bandwidth requires a lower frame rate and/or reduced video frame size. 
     A standard video format used in videoconferencing, defined by resolution, is Common Intermediate Format (CIF). The primary CIF format is also known as Full CIF or FCIP. The International Telecommunications Union (ITU), based in Geneva, Switzerland (www.itu.ch), has established this communications standard. Additional standards with resolutions higher and lower than CIF have also been established. Resolution and bit rate requirements for various formats are shown in Table I below. The bit rates (in megabits per second, Mbps) shown are for uncompressed color frames where 12 bits per pixel is assumed. 
     
       
         
               
             
               
               
               
               
             
               
               
               
               
             
           
               
                 TABLE I 
               
             
             
               
                   
               
               
                 Resolution and bit-rates for various CIF formats 
               
               
                 Bit Rate at 30 fps 
               
             
          
           
               
                   
                   
                 Resolution 
                   
               
               
                   
                 CIF Format 
                 (in pixels) 
                 Mbps 
               
               
                   
               
             
          
           
               
                   
                 SQCIF (Sub Quarter CIF) 
                 128 × 96  
                 4.424 
               
               
                   
                 QCIF (Quarter CIF) 
                 176 × 144 
                 9.124 
               
               
                   
                 CIF (Full CIF, FCIF) 
                 352 × 288 
                 36.50 
               
               
                   
                 4CIF (4 × CIF) 
                 704 × 576 
                 146.0 
               
               
                   
                 16CIF (16 × CIF) 
                 1408 × 1152 
                 583.9 
               
               
                   
               
             
          
         
       
     
     Video compression is a means of encoding digital video to take up less storage space and reduce required transmission bandwidth. Compression/decompression (CODEC) schemes are frequently used to compress video frames to reduce required transmission bit rates. Overall, CODEC hardware or software compresses digital video into a smaller binary format than required by the original (i.e., uncompressed) digital video format. 
     H.263 is a document which described a common contemporary CODEC scheme, requiring a bandwidth from 64 to 1920 Kbps. H.263 is an ITU standard for compressing video and is generically known as a lossy compression method. Lossy coding assumes that some information can be discarded, which results in a controlled degradation of the decoded signal. The lossy coding method is designed to gradually degrade as a progressively lower bit rate is available for transmission. Thus, the use of lossy compression methods results in a loss of some of the original image information during the compression stage and, hence, the lost original image information becomes unrecoverable. For example, a solid blue background in a video scene can be compressed significantly with little degradation in apparent quality. However, other frames containing sparse amount of continuous or repeating image portions often cannot be compressed significantly without a noticeable loss in image quality. 
     Many video compression standards, including MPEG, MPEG-2, MPEG-4, H.261, and H.263 utilize a block-based Discrete Cosine Transform (DCT) operation on data blocks, 8×8 samples in size. A set of coefficients for each block is generated through the use of a two-dimensional DCT operation. Such coefficients relate to a spatial frequency content of the data block. Subsequently, the 64 DCT coefficients (one for each sample) in a block are quantized. For H.263, one quantizer step size is applied to every DCT coefficient in a data block and is part of the information that must be transmitted to a H.263 decoder. The quantization process is defined as a division of each DCT coefficient by the quantization step size followed by rounding to the nearest integer. An encoder applies variable uniform quantization to DCT coefficients to reduce the number of bits required to represent them. Compression may be performed on each of the pixels represented by a two-by-two array of blocks containing luminance samples and two blocks of chrominance samples. This array of six blocks is commonly referred to as a macroblock. The four luminance and two chrominance data blocks in a macroblock combine to represent a 16×16 pixel array. 
     In an H.263 encoder, variable uniform quantization is applied by means of the quantization parameter that provides quantization step sizes that may the values of DCT coefficients to a smaller set of values called quantization indices. In the H.263 decoder, DCT coefficient recovery is performed, roughly speaking, by multiplying the recovered quantization indices by the inverse quantization step size. The decoder then calculates an inverse DCT using the recovered coefficients. 
     Although the DCT and other methods have proven somewhat effective in utilizing spatial redundancy to limit the bit rate required to represent an image, there remains a need to improve video quality in a computationally-effective way. Video sequences tend to contain a large amount of temporal redundancy; in other words, areas of the current image are very likely to be similar to areas of a subsequent image. In any video compression method, motion estimation takes advantages of the temporal redundancy to reduce the required bit rate. Motion estimation is commonly performed between a current image frame and a previous image—the reference image frame. The motion estimation method typically uses an integer pixel grid, typically a macroblock for the current frame and a larger search space containing a co-located macroblock of the previous frame. A portion of the search area may be sampled to reduce the computational complexity of comparisons. A vector is generated to estimate temporal differences between where a macroblock appears in the current image and where the best representation appears in the reference image search area. The generated vector is a motion vector. 
     Contemporary video motion estimation methods have a trade-off between accuracy and computational cost (i.e., computation power and memory requirements). If a search algorithm requires a large number of comparisons to cover the search area, a great deal of computational power and time is required which can reduce the overall frame rate and thereby produce a jerky or erratic picture. If a small search area or small comparison set is used, a resulting picture may suffer from blocking defects. Consequently, there is a need for a system and method for computationally-efficient means of producing and evaluating motion vectors in a video frame. 
     SUMMARY 
     Motion estimation is crucial to the quality of a compressed video stream and is also the most computationally intensive step in any video encoding process. Many contemporary implementations for real-time encoding of a video stream sacrifice the quality of the motion estimation and resulting video stream by reducing both search ranges (e.g., a search pattern size) and total numbers of motion vectors evaluated. The pipelined architecture disclosed herein evaluates a greater number of motion vectors in a computationally efficient manner that is executed quickly. Redundancies that may exist in neighboring areas of the video image are utilized to compute proximate motion vectors concurrently. 
     In one exemplary embodiment, the present invention is a pipelined motion estimation system. Inputs to the pipelined motion estimation system include a current frame input storage means for storing contents of a current frame and a previous frame input storage means for storing contents of one or more previous frames. A sum-of-absolute differences (SAD) calculation module concurrently determines a best fit motion vector from a plurality of potential motion vectors where the plurality of potential motion vectors are based upon a pixel-based search pattern. The pixel-based search pattern may be programmable. A sum-of-absolute difference logic block concurrently determines a minimum residual value from the plurality of motion vectors. The motion vector having the lowest residual value across one or more search patterns may be used as a component of a video encoding scheme. 
     In another exemplary embodiment, the present invention is a pipelined motion estimation system. Inputs to the pipelined motion estimation system include a current frame input storage means for storing contents of a current frame and previous frame input storage means for storing contents of a plurality of previous frames. A motion command stage stores user-based parameters of a size and shape of pixel-based search patterns to define a search algorithm that covers an intended search area. A sum-of-absolute differences calculation module concurrently determines a best fit motion vector from a plurality of potential motion vectors where the plurality of potential motion vectors are based upon the pixel-based search pattern. A sum-of-absolute differences logic block concurrently determines a minimum residual value from the plurality of motion vectors. 
     Another exemplary embodiment of the present invention is also a method for estimating motion within a video system. The method includes providing input from one or more previous frames of data, providing input from a current frame of data, and selecting a pixel-based search pattern within the search area from the one or more previous frames of data. A sum-of-absolute differences is concurrently computed for a motion vector from each pixel within the pixel-based search pattern and a minimum residual value is computed for each of the motion vectors by comparing partial contents of the one or more previous frames of data with partial contents of the current frame of data. A single motion vector for the search pattern is selected based on the minimum residual value. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing an exemplary embodiment of a pipelined motion estimation module of the present invention. 
         FIG. 2  is a macroblock portion of a video frame indicating various configurations and search patterns for potential motion vectors. 
         FIG. 3  is a flow diagram of an exemplary embodiment of the pipelined motion estimation module of  FIG. 1 . 
         FIG. 4  is an exemplary block diagram showing details of the previous frame (PFRM) read, pixel shuffle, and vertical adder stages of the pipelined motion estimation module of  FIG. 1 . 
         FIG. 5  is an exemplary block diagram of the current frame (CFRM) pixel load stage of the pipelined motion estimation module of  FIG. 1 . 
         FIG. 6  is an exemplary sum-of-absolute difference calculation module of the pipelined motion estimation module in  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     The present invention is a high-performance hardware pipeline for processing image data. A unique ability of this pipelined architecture is to process and deliver high quality images at a low cost and high speed by applying programmable search pattern sizes, generating motion vectors for pixels within the search pattern, and evaluating a best-fit motion vectors in a highly-parallel process. Evaluation of motion vectors at high speed is possible due to the use of pipelining (i.e., parallel processing of various calculations concurrently). The subsystem described herein, in one embodiment, consists of hardware blocks to facilitate high throughput and high-performance operations. However, the subsystem maintains a significant degree of programmability allowing digital camera and videoconference manufacturers to implement specific modifications while still retaining the high speed advantages described herein. 
     With reference to  FIG. 1 , an exemplary motion estimation system  100  includes a portion of a current frame (CFRM) memory  101  undergoing a comparison with portions of four previous frame (PFRM) memories  103  to determine a best-fit motion vector appropriate for a search pattern within a search area in the PFRM memory  103 . The exemplary motion estimation system  100  further includes a motion command memory module  105  and a motion estimation module  107 . The motion estimation module  107  includes a control module  109 , a motion core module  111 , and a sum-of-absolute difference (SAD) comparator module  113 . Each of the modules will be described in greater detail below. The motion estimation module  107  functions as a pipelined processor and produces a best-fit motion vector and a corresponding SAD residual value as outputs. 
     The motion command memory module  105  stores user-defined parameters that control search parameters (described in more detail with reference to  FIG. 2 , below). By programming the parameters in the motion command memory, the user can create one or more algorithms that are wither exhaustive or progressive and searches as mush of the search space as is needed. The programmed parameters include a line and pixel offset option, a search pattern size option, a line skipping option, and an offset from best option. 
     The line and pixel offset option allows a programmed offset to be applied to a search pattern from an initial starting location or from a best fit motion vector. The search pattern size option, described in more detail below, allows the user to select a 1×8, a 2×4, or a half-pel search pattern. The line skipping option allows the user to program a traverse of a macroblock in which one ore more lines are skipped at a time. Generally, no more than three lines are skipped at a time although three is not an inherent limit in the system. An increase in the number of lines skipped improves the speed of a search with a concomitant decrease in search accuracy. The offset from best option allows a user to program any line and/or pixel offsets from either an initial start location or from a best fit motion vector identified earlier in the motion estimation search. The offset from best option is useful for progressive and hierarchy searching. 
     Overall, the motion estimation module  107  compares contents of the CFRM memory  101  to contents of the PFRM memory  103  and determines a best-fit motion vector within a search area. The determination of the best-fit motion vector is accomplished by computing a SAD residual value for each of the motion vectors within the search pattern. The smallest SAD residual value across a combination of sample patterns results in the best-fit motion vector for the search area. 
     In  FIG. 2 , a portion  200  of a macroblock within the PFRM memory  103  indicates various exemplary search patterns considered herein. Although specific search pattern sizes are described, the same techniques are readily extensible to smaller and larger search pattern sizes. A 1×8 search pattern  201  is selected to allow computation of a SAD for each of eight motion vectors on a single line. A 2×4 search pattern  203  is selected to allow computation of a SAD for each of four motion vectors on two line (i.e., eight total vectors evaluated concurrently). Additionally, half-pixel (half-pel) resolution of a search pattern may be implemented. A half-pel search pattern  205  is selected to allow computation of a SAD for each of eight motion vectors within a single pixel (e.g., eight half-pels around a selected full pixel). An “A” in each of the three search patterns  201 ,  203 ,  205  indicates a pixel selected as a starting location within the search pattern chosen. A particular search algorithm is programmable in terms of search pattern size, starting location within the search pattern, and a direction in which the search pattern is traversed. 
     A search algorithm is used in determining a search pattern size, a starting location within the search pattern, and how the search pattern is traversed. The search algorithm is stored in the motion command memory module  105  ( FIG. 1 ). For each command stored in the motion command memory module  105 , the motion estimation module  107  will search and compare the SAD for each of the eight possible candidate motion vectors simultaneously (i.e., in parallel). A comparison is performed on each of the SAD calculations to determine a best-fit motion vector. The best-fit motion vector thus occurs when a difference between the previous data and the current data is the smallest. The simultaneous search and computation results in a highly parallel search routine, thus increasing throughput and significantly reducing an amount of time in determining a best-fit motion vector. Consequently, with an eight pixel or eight half-pel window, a full SAD computation for a 256 pixel macroblock may be performed in just over eight cycles per motion vector. 
     With reference to  FIG. 3 , the pipelined exemplary motion estimation system  100  of  FIG. 1  is illustrated and various pipelined stages are defined in detail. In this exemplary embodiment, the PFRM memory  103  is a bank of four 32-bit memories. Each pixel is eight bits wide allowing four pixels concurrently in each of the four PFRM memory  103  arrays. An “A-series” register bank  301  includes four 32-bit registers, A 0 -A 3 , (128 total bits or 16 pixels per cycle). Consequently, 4 pixels from each of the PFRM memory  103  arrays may be read concurrently into the first stage. 
     A second stage includes a pixel shuffle and vertical combination logic block  303 . The pixel shuffle and vertical combination logic block  303  includes a shuffle pixel block  305  and a vertical adder  307 . The shuffle pixel block  305  accounts for the starting location “X” within the chosen search pattern  201 ,  203 ,  205  ( FIG. 2 ) as described above to prevent an misinterpretation of a location of the motion vector. 
     To calculate half-pel values from full pixel values as described with reference to the half-pel search pattern  205  of  FIG. 2  above, the data must be interpolated in horizontal, vertical, and diagonal directions. The vertical adder  307  thus adds pixels from adjacent lines for vertical interpolations. Requirements for adding pixel values are described in further detail below. 
     A “B-Series” register bank  309  stores a version of the pixels contained in the A-series register bank  301  that has been shuffled in the pixel shuffle and vertical combination logic block  303  such that the pixels are in the correct order for a subsequent difference operation. Detailed operations of the B-series register bank  309  are presented below with reference to  FIG. 4 . 
     A copy/store stage retains a copy of the plurality of the data stored in the B-series register bank  309  in a “C-series” register bank  311 . As discussed briefly above with reference both to the half-pel search pattern  205  of  FIG. 2  and the vertical adder  307 , a shift left and divide by two stage  313 A,  313 B or a shift left and divide by four stages  315  may be used. (The two shift left and divide by two stages  313 A,  313 B are provided for clarity and do not necessarily represent two physically unique stages.) For horizontal interpolations, two adjacent values from pixels that are side-by-side are added and divided by two. For vertical interpolations, two pixels from adjacent lines are added together and divided by two. For diagonal interpolations, four full pixels surrounding a candidate half-pel are added and divided by four. Therefore, divide by two and divide by four functions allow half-pel interpolation by effectively averaging neighboring values. Horizontal and vertical interpolation each involve adding two full pixel values and dividing by two to arrive at an average value. Similarly, diagonal interpolation involves adding four full pixel values and dividing by four. If the motion estimation module  107  is not operating in half-pel mode, then the division functions of the shift left and divide by two stage  313 A,  313 B and the shift left and divide by four stage  315  are not necessary. Thus, if a half-pel search pattern  205  is not used, then the plurality of the data stored in the second register bank  308  will be used without modification. 
     With reference to the “shift-left” component of these stages, recall that candidate motion vectors can be anywhere in the search space. However, lines of data are brought into the PFRM memory  103  from external memory sources in blocks of four pixels. If, for example, the left-most pixel of the starting vector does not line up on the same boundary as the memory, the pixels must be shifted so that the desired pixels line up with the registers. Consequently, the left shift operation aligns pixels by shifting out unnecessary pixels. 
     Contents from the shift left and divide by two stage  313 A,  313 B are stored in an “D-series” register bank  317  and an “E-series” register bank  318 . Contents from the shift left and divide by four stage  315  are stored in an “F-series” register bank  319 . Additionally, a CFRM read stage provides a storage location for the CFRM memory  101  into a “G-series” register bank  321 . 
     The G-series register bank  321  contain data that have been received from the CFRM memory  101 . Each of the G-series registers is a 32-bit register. The CFRM memory  101  is a single 32-bit memory. Consequently, each address of the CFRM memory  101  stores four pixels. When data form the CFRM memory  101  are fetched, they are stored alternately in either storage register G 0  or G 1 . Once a SAD value is computed using these pixels, the pixels are written back to storage registers G 2 -G 5 . 
       FIG. 4  presents details of the B-series register bank  309  of  FIG. 3 . On alternating clock cycle, a switch  401  changes directions. An effect of the switch  401  is that, on the first cycle, the B-series register bank  309  contain the shuffled data from the A-series register bank  301 . On the next cycle, the B-series register bank  309  contains the shuffled data from the line above added with the shuffled data from the current line. This operation provides the vertical combination when half-pel mode is selected. When using either a 1×8 or a 2×4 search pattern, the vertical combination is unused. 
     With reference to  FIG. 5  and continued reference to  FIG. 3 , registers G 2 -G 5  contain data received from an entire previous line from CFRM memory  101 . The previous line of data are re-used during a half-pel operation to calculate differences between the line and the bottom left, bottom middle, and bottom right half-pels. Details of these calculations are provided with reference to  FIG. 6 , below. Concurrent with these calculations, a new line from CFRM memory  101  is being loaded into registers G 0  and G 1 . Consequently, half-pel calculations are performed simultaneously. 
     With reference to  FIG. 6  and continued reference to  FIG. 3 , values from the selected sample search pattern are used in the actual SAD determination. Various types of SAD calculators are known in the art. Hence, the SAD calculator depicted with reference to  FIGS. 3 and 6  is provided for illustration purposes and is merely exemplary. 
     A plurality of multiplexers  601  accepts inputs from various registers. In this exemplary embodiment, each of the plurality of multiplexers  601  has a 32-bit output. Output from the B-series register bank  309  is 9-bit per word (i.e., 36-bit registers, see  FIG. 4 ) and the C-series register bank  311  is 8-bit per word (i.e., 32-bit registers). In either a 1×8 or a 2×4 search pattern mode, the C-series register bank  311  is selected. In a half-pel search mode, an output of a multiplexer is an interpolation of two lines. As discussed above, the lines are combined using the vertical adder  307  which feeds into the B-series register bank  309 . Before feeding these data into the vertical adder  307 , the least significant bit (LSB) of each 9-bit word is dropped, effectively resulting in a divide-by-two to complete the interpolation. 
     Inputs to the plurality of multiplexers  601  is selected based on which search mode is selected. Table II, below, summarizes inputs based on each of the three search pattern modes (1×8, 2×4, half-pel). Each mode utilizes data from pixels of reference data (D, E, and F register banks) and pixels of current data (G register bank). 
     
       
         
               
             
               
               
               
             
               
             
               
               
               
             
               
             
               
               
               
             
               
             
               
               
               
             
           
               
                 TABLE II 
               
             
             
               
                   
               
               
                 Inputs for various search modes 
               
             
          
           
               
                   
                 COMBINATION OF 8 PIXELS 
                 ALTERNATE 
               
               
                 LOCATION 
                 SELECTED FROM 
                 SELECTIONS 
               
               
                   
               
             
          
           
               
                 1 × 8 SEARCH PATTERN 
               
             
          
           
               
                 Single Row 
                 D 0 , D 1 , D 2   
                 G 0 , G 1   
               
             
          
           
               
                 2 × 4 SEARCH PATTERN 
               
             
          
           
               
                 Upper Row 
                 D 0 , D 1 , D 2   
                 G 0 , G 1   
               
               
                 Lower Row 
                 D 0 , D 1 , D 2   
                 G 2 -G 5   
               
             
          
           
               
                 HALF-PEL SEARCH PATTERN 
               
             
          
           
               
                 Upper Left 
                 F 0 , F 1 , F 2 , F 3   
                 G 0 , G 1   
               
               
                 Upper Middle 
                 D 0 , D 1 , D 2 , D 3   
                 G 0 , G 1   
               
               
                 Upper Right 
                 F 0 , F 1 , F 2 , F 3   
                 G 0 , G 1   
               
               
                 Middle Left 
                 E 0 , E 1 , E 2 , E 3   
                 G 0 , G 1   
               
               
                 Middle Right 
                 E 0 , E 1 , E 2 , E 3   
                 G 0 , G 1   
               
               
                 Lower Left 
                 F 0 , F 1 , F 2 , F 3   
                 G 2 -G 5   
               
               
                 Lower Middle 
                 D 0 , D 1 , D 2 , D 3   
                 G 2 -G 5   
               
               
                 Lower Right 
                 F 0 , F 1 , F 2 , F 3   
                 G 2 -G 5   
               
               
                   
               
             
          
         
       
     
     Outputs from pairs of the plurality of multiplexers are combined in an eight-bit subtracter  323  and an absolute value is taken of the result. Each of the absolute value is stored in an “H-series” bank of registers  325 . Data from the H-series bank of registers  325  are loaded into a pair of eight-bit adders  327 . A plurality of nine-bit adders  329  accepts results from each pair of eight-bit adders  327 . Results from the plurality of nine-bit adders are loaded into a plurality of ten-bit adders/accumulators  331 . Each of the ten-bit adders has a 15-bit accumulator. The sum-of-absolute differences for each of the eight search patterns is output from the plurality of ten-bit adders/accumulators  331 . Each of the H-series bank of registers  325  contains four words that represent an absolute difference between pixels in the current block and the reference block. The eight-bit adders  327  and the nine-bit adders  329  are two-stage adders to combine the four words. As the engine progresses through processing an entire macroblock, the SAD values are accumulated in the plurality of ten-bit adders/accumulators  331 . 
     Each of the eight outputs is ten evaluated for a determination of a lowest SAD residual value in a minimum of eight logic block  333  ( FIG. 3 ). The minimum of eight logic block  333  may be comprised of, for example, a hardware-based comparator. The best-fit motion vector is selected as having the lowest SAD residual value. In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as et forth in the appended claims. For example, skilled artisans will appreciate that various and additional registers may be used. Also, certain shift and divide stages made be eliminated depending upon particular types or search patterns chosen. Complete embodiments or portions of embodiments of the present invention may be implemented in hardware with various types of controllers, processors, and/or microprocessors. They may also be implemented in software, firmware, or a combination of hardware, software, and firmware. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.