Abstract:
A flip chip assembly, and methods of forming the same, including a single layer or multilayer substrate in which via holes serve as connections between a semiconductor chip and the substrate. The assembling steps comprise attaching a chip to a substrate having a plurality of via holes for connecting respective traces on the substrate with respective input/output terminal pads of the chip. The via holes are aligned with and placed on top of the pads so that the pads are exposed through the opposite side of the substrate. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the pads to provide electrical connections between the pads and the traces. Electrically conductive materials include electroless plated metals, electrochemical plated metals, solders, epoxies and conductive polymers.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a divisional of U.S. application Ser. No. 09/120,408 filed on Jul. 22, 1998, which claims priority to Singapore application Ser. No. 9800994-7 filed on May 2, 1998. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to integrated circuit assemblies, and in particular, to the electrical connection of integrated circuits to substrate circuitry, printed circuit board, and interconnect components. Most specifically, the invention relates to a flip chip assembly which includes a single or multi-layered substrate in which via holes are electrically and mechanically connected to the input/output terminal pads of the integrated circuit through direct metallization. 
     2. Related Art 
     Recent developments of semiconductor packaging suggest an increasingly critical role of the technology. New demands are coming from requirements for more leads per chip and hence smaller input/output terminal pad pitch, shrinking die and package footprints, and higher operational frequencies that generate more heat, thus requiring advanced heat dissipation designs. In addition to these demands, the more stringent electrical requirements must not be compromised by the packaging. All of these considerations must be met and, as usual, placed in addition to the cost that packaging adds to the semiconductor-manufacturing food chain. 
     Conventionally, there are three predominant chip-level connection technologies in use for integrated circuits, namely wire bonding, tape automated bonding (TAB) and flip chip (FC) to electrically or mechanically connect integrated circuits to leadframe or substrate circuitry. Wire bonding has been by far the most broadly applied technique in the semiconductor industry because of its maturity and cost effectiveness. However, this process can be performed only one wire bond at a time between the semiconductor chip&#39;s bonding pads and the appropriate interconnect points. Furthermore, because of the ever increasing operational frequency of the device, the length of the interconnects needs to be shorter to minimize inductive noise in power and ground, and also to minimize cross-talk between the signal leads. An example of such a method is disclosed in U.S. Pat. No. 5,397,921 to Karnezos. 
     Flip chip technology involves mounting of an unpackaged semiconductor chip with the active side facing down to an interconnect substrate through contact anchors such as solder, gold or organic conductive adhesive bumps. The major advantage of flip chip technology is the short interconnects which, therefore, can handle high speed or high frequency signals. There are essentially no parasitic elements such as inductance. Not only is the signal propagation delay slashed, but much of the waveform distortion is also eliminated. Flip chip also allows an area array interconnecting layout that provides more I/O than a perimeter interconnect with the same die size. Furthermore, it requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space is used. An example of such a method is disclosed in U.S. Pat. No. 5,261,593 to Casson et al. 
     FIG. 1 is a schematic cross-sectional view of a prior art flip chip assembly in which an integrated circuit chip  101  is attached to a substrate  102  through electrically conductive bumps  103 . These bumps  103  make electrical connection between bond pads  104  formed on the chip  101  and conductive traces  105  formed on the surface of the substrate  102 . These traces  105  further extend to the other side of the substrate  102  through via holes  107  that are formed within the substrate  102 . In the dielectric substrate, a via hole connects two or multiple layers of circuitry in a substrate. A via hole links both sides of the finished substrate, whereas a blind via links one side to one or multiple internal layers and a buried via links internal layers without being visible on the surface of the board. These via holes are typically metallized on the sidewall with copper by electroless plating and electroplating. Underfilled material  106  is typically applied between integrated circuit chip  101  and substrate  102  in order to reduce the stress due to thermal characteristic mismatch of the chip  101  and substrate  102 . Conductive traces  105  formed on the top of the substrate  102  extend from the via holes to specific contacting pads or balls  108  and therefore connect to the external circuitry. 
     While flip chip technology has tremendous advantages over wire bonding, its cost and technical limitations are significant. First of all, flip chip technology must confront the challenge of forming protruded contact anchors or bumps to serve as electrical connections between the integrated circuit chip and substrate circuitry. A variety of bumping processes have therefore been developed. These include vacuum deposition of an intermediate underbump layer which serves as an adhesive and diffusion barrier. This barrier layer is composed of a film stack which can be in the structure of chromium/copper/gold. Bumping materials such as solder are subsequently deposited onto this intermediate layer through evaporation, sputtering, electroplating, solder jetting or paste printing methods followed by a reflow step to form the solder contacts. 
     Techniques for fabricating the intermediate under-bump barrier layer as well as the bump material utilizing electroless plating are also known. In these attempts, as shown in FIG. 2, the input/output terminal pads  201  of the integrated circuit chip  200  are firstly activated by a catalytic solution which will selectively activate the pad material through chemical reactions and form a thin layer of catalyst  202 . This thin layer of catalyst  202  is typically composed of zinc or palladium. When electroless plating is executed thereafter, material such as nickel, gold, palladium or their alloys can be selectively initiated and continuously deposited on the pads to form the bumps  203 . In the above-described electroless plating process, hypophosphate or boron hydride are commonly used as the reducing agent in the nickel plating solution. This electroless plated bump not only provides the protruding contact anchor but also serves as the diffusion barrier and provides sealing. Contacting material such as solder, conductive adhesive or polymer is subsequently applied onto these bumps by techniques such as solder dipping, solder jetting, evaporation, screen printing or dispensing. An example of such a method is described in the U.S. Pat. No. 5,583,073 to Lin et al. 
     Although the electroless technique provides an economical, simple and effective method for fabricating the under bump barrier layer, contacting material such as solder or adhesive is still required for assembling. Solder dipping or screen printing of solder paste onto these bumps has been explored but with very limited success due to solder bridging and non-uniform deposition of solder on the metal bumps. This process also suffers from poor process control as the input/output terminal pad spacing gets smaller. Additional problems have been encountered with tin/lead solder due to its increase in electrical resistance over time. Moreover, the solder contacts are easily fatigued by thermo-mechanical stressing. 
     Organic contacts which utilize conductive adhesive to replace solder joints are described in U.S. Pat. No. 5,627,405 to Chillara. Generally speaking, the conductive adhesive, which is made by adding conductive fillers to polymer binders, holds a number of technical advantages over soldering such as environmental compatibility, lower-temperature processing capability, fine pitch and simplified processes. However, conductive adhesive does not normally form a metallurgical interface in the classical sense. The basic electrical pathway is through conductive particles of the adhesive that are in contact with one another and reach out to the two contact surfaces of the components. Under certain environments, this interconnect system may cause problems because the penetration of moisture through the polymer may induce corrosion and oxidation of the conducting metal particles which results in unstable electrical contacts. Furthermore, failure of the joints can also occur due to degradation of the polymer matrix as well as degradation of the metal parts. Since the electrical and mechanical performance are independent of each other, good mechanical performance is no assurance of electrical integrity. 
     In view of the limitations in the currently available integrated circuit assembling methods, a high-performance, reliable and economical method which interconnects integrated circuits to the external circuitry would be greatly desirable. 
     SUMMARY OF THE INVENTION 
     According to the invention, a flip chip assembly is provided to address high density, low cost and high performance requirements of electronics products. It involves the direct interconnection of an integrated circuit chip to substrate circuitry through direct metallization of via holes and bond pads without the need for bumps, wire bonds, or other media. 
     To achieve the foregoing and in accordance with the invention, the assembly includes a rigid or flexible dielectric substrate having a plurality of electrically conductive circuitry traces, one or more integrated circuit chips having a plurality of input/output terminal pads, and a plurality of via holes formed in the dielectric substrate for electrically connecting respective traces of the substrate with respective pads of the integrated circuit chip. Preferably, a metallic film is formed on the sidewalls of the via holes. The metallic film may include copper, nickel, palladium or gold. The surface of the integrated circuit chip and the dielectric substrate may be arranged in substantially mutually parallel planes. The orientation of the contact is in such a manner that the via holes in the dielectric substrate are aligned with the top of the pads of the integrated circuit chip so that these pads can be totally or partially exposed through the opposite side of the substrate. After the alignment, the connecting step may include attaching the integrated circuit chip to the dielectric substrate through mechanical or chemical techniques to form an assembly. The attachment may be provided by an adhesive film, a liquid adhesive or mechanical clamping. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the input/output terminal pads of the integrated circuit chip to provide electrical and mechanical connections between the terminal pads and the traces of the dielectric circuitry. After the via holes are connected to the terminal pads, the mechanical and chemical means that provided the chip and substrate attachment can be removed or left as an integral part of the assembly since the via hole connections also provide mechanical support. 
     In a method aspect of the invention, the connection is provided by electroless plating. The electroless plating initiates and continuously deposits electrically conductive material such as copper, nickel, palladium, gold and their alloys on the via hole sidewalls as well as input/output terminal pads of the integrated chip. As the plating process continues, the metallic surface of the via hole sidewalls and terminal pads will extend out and contact each other and finally join together and become an integrated part. These simultaneously electrolessly plated joints provide effective electrical and mechanical connections between the integrated circuit chip and the dielectric circuitry. 
     In another method aspect of the invention, the connection may take the form of electrochemical plating. In this method, metallized via holes in the dielectric substrate are electrically connected to an external power source and serve as one electrode for plating. This plating process can be carried out on the sidewalls of via holes as well as other areas that receive electricity from the power source and are exposed to the electrochemical plating solution. In the initial stage, the terminal pads of the integrated circuit chip do not receive electroplating due to lack of electrical contact with the power source. However, as the via hole sidewall plating process continues, the metallizing surface will extend out and finally contact and provide electricity to the terminal pads and subsequently initiate electroplating on them. These simultaneously electroplated parts join together and provide effective electrical and mechanical connections between the chip and the dielectric circuitry. 
     According to a further aspect of the invention, the connection may take the form of solder paste, liquid solder, solder particles, epoxy or conductive polymer which is reflowable and bondable to the integrated circuit chip terminal pads and via hole walls after the application of heat or an energy source such as a laser or infrared light. In this method, the filling material can be filled into the via holes through selective printing, jetting or ball placement techniques. As the external energy such as heat or a laser is applied to the filling material, the original form of the material will melt and change its shape, enlarge the contacting areas, and adhere to the wettable surfaces thus providing effective electrical and mechanical contacts between pre-metallized via hole sidewalls and input/output terminal pads of the integrated circuit chip. In some embodiments, these input/output terminal pads are pre-treated or coated with a thin protective layer if the material is vulnerable to corrosion or dissolution through reactions by the joint material such as solder. 
     According to the invention, via holes of the substrate can be formed by various techniques including mechanical drilling, mechanical punching, plasma etching or laser drilling. They are formed in the substrate at locations where electrical circuitry on one side of the substrate can be connected to the opposite side of the surface on which the semiconductor chip or chips are mounted and their input/output terminal pads can be exposed through these holes. 
     According to the invention, dielectric layers of the rigid substrate can be either organic or inorganic material. An organic substrate is preferable for lower cost and superior dielectric property whereas an inorganic substrate is preferable when high thermal dissipation and matched coefficient of expansion are desired. Suitable dielectrics include plastics, ceramics and flexible films. 
     If the finished product is, for instance, a ball grid array, solder balls can be formed on the traces. This finished package can be connected to a printed circuit board by reflowing the solder balls to form an attachment to the conductors on the surface of the printed circuit board. 
     In summary, using via hole direct connection of an integrated circuit chip and dielectric substrate circuitry instead of anchoring solder or a conductive adhesive bump allows a high reliability, low profile, and high performance assembly to be achieved. In particular, a small via hole formed by laser drilling or other techniques allows a very fine pitch terminal pad to be interconnected, which can significantly enhance the capability of packaging future high I/O semiconductor chips. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 (prior art) is a diagrammatic cross-sectional view of a conventional flip chip package with solder bumps. 
     FIG. 2 (prior art) is a diagrammatic cross-sectional view of a conventional electroless plated nickel bump structure. 
     FIGS. 3A to  3 D are diagrammatic cross-sectional views showing the steps involved in the manufacturing of an integrated circuit assembly by electroless plating according to an embodiment of the invention. 
     FIGS. 4A to  4 E are diagrammatic cross-sectional views showing the steps involved in the manufacturing of an integrated circuit assembly by electroless via fill according to another embodiment of the invention. 
     FIGS. 5A to  5 E are diagrammatic cross-sectional views showing the steps involved in the manufacturing of an integrated circuit assembly by electroplating according to another embodiment of the invention. 
     FIGS. 6A to  6 D are diagrammatic cross-sectional views showing the steps involved in the manufacturing of an integrated circuit assembly by solder via fill according to another embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention will be illustrated further by the following examples. These examples are meant to illustrate and not to limit the invention, the scope of which is defined solely by the appended claims. 
     EXAMPLE 1 
     FIGS. 3A through 3D illustrate a process for producing an embodiment of the flip chip assembly according to the present invention. Referring initially to FIG. 3A, an integrated circuit chip  301  in which various types of transistors, wiring and the like are formed (not shown) has a plurality of exposed input/output terminal pads  302 . These pads  302  are firstly cleaned by dipping the integrated circuit chip  301  in a phosphoric acid solution at room temperature with an immersion time of 10 minutes to remove the surface oxide film. This chip is next dipped in a diluted catalytic solution Enthone “Alumon EN” (trademark) at 25 degrees C. for 20 seconds to form a thin zinc film  303  on the surface of the aluminum alloy terminals  302 , followed by a thorough distillated water rinse to ensure there is no residue left on the surface of integrated circuit chip  301 . 
     FIG. 3B shows a double-sided or multi-layer dielectric substrate  304  having a plurality of electrically conductive circuitry traces  305  attached to the integrated circuit chip. The traces  305  on one surface of the substrate  304  extend to a plurality of via holes  306  of the dielectric substrate  304 . The metallic film  307  on the sidewall of the via holes is formed by conventional techniques including electroless plating, sputtering or evaporation or a combination of these techniques. These holes  306  are arranged in such a manner that the terminal pads  302  of the integrated circuit chip  301  can be totally or partially exposed when integrated circuit chip  301  is mounted on the substrate  304 . These holes  306  serve as electrically connecting channels for respective traces  305  on the top surface of the substrate  304  with respective terminal pads  302  of the integrated circuit chip  301 . The metallic film on the sidewalls of via holes  306  is activated by immersing in a palladium chloride solution (0.05 M) for readily initiating electroless plating. 
     Now referring to FIG. 3C, after chip  301  is securely attached to the substrate  304 , the chip assembly is immersed in the electroless plating solution Shipley “NIPOSIT 468” (trademark) at 65 degrees C. The electroless plating initiates and continuously deposits a thin layer of nickel film  308  containing phosphorus (to be referred to as a nickel film hereafter) on the pre-activated metal film  307  and nickel film  309  on the input/output terminal pads  302  of the integrated circuit chip  301 . 
     FIG. 3D shows the metallic surface of the via hole sidewalls and input/output terminal pads finally contact and join together to become an integrated part  310  as the plating process continues. These simultaneously plated joints  310  provide effective electrical and mechanical connections between the input/output terminal pads and the traces of the dielectric circuitry. 
     Though only one integrated circuit chip  301  is shown, it is to be understood that additional integrated circuit chips, as well as passive components such as resistors or capacitors, can also be mounted on substrate  304 . 
     EXAMPLE 2 
     FIGS. 4A through 4E illustrate a process for producing another embodiment of the flip chip assembly according to the present invention. Referring now to FIG. 4A, an integrated circuit chip  401  similar to that in example 1 is cleaned in an alkaline solution containing 0.02 M sodium hydroxide at room temperature (25 degrees C) with an immersion time of 1 minute. This chip  401  is next dipped in a catalytic solution Shipley “DURAPREP 40” (trademark) at 25 degrees C. with an immersion time of 2 minutes to form an activation layer  403  on the surface of the terminal pads  402 . After a thorough rinse in distilled water, the integrated circuit chip is immersed in a Shipley “NIPOSIT 468” (trademark) electroless plating bath for 2 minutes, at 65 degrees C. A thin layer of nickel film  404  containing phosphorus (to be referred to as a nickel film hereafter) precipitates on and around the terminal pads  402 . 
     FIG. 4B shows a dielectric substrate  405  having a sheet of copper  406  on the top of the surface and covered by a layer of insulating film  407 . A plurality of via holes  408  are drilled and arranged in such a manner that the input/output terminal pads  402  of the integrated circuit chip  401  can be totally or partially exposed when integrated circuit chip  401  is mounted on the substrate  405 . There is no activation layer or metallized film on the via hole sidewalls. 
     FIG. 4C shows the integrated circuit chip  401  securely attached to the substrate  405 , the integrated circuit chip assembly is then immersed in the electroless plating solution Shipley “NIPOSIT 468” (trademark) at 65 degrees C. The electroless plating initiates and continuously deposits nickel pillar  409  on the top of the pre-deposited nickel film  404  (shown in phantom lines) of the integrated circuit chip  401 . 
     FIG. 4D shows that the plated nickel  409  has reached the dielectric edge of the hole  408  and contacts the top layer of copper sheet  406 . The insulating film  407  is stripped off after the nickel via-fill reaches the copper sheet. These plated joints provide effective electrical and mechanical connections between the input/output terminal pads and the top surface of the dielectric circuitry. 
     FIG. 4E shows a plurality of copper circuitry traces  410  formed on the surface of the substrate by conventional etching techniques. These traces  410  extend from a plurality of electroless nickel-filled holes  408  of the dielectric substrate  405  and serve as electrically connecting channels with respective input/output terminal pads  402  to the external circuitry. 
     EXAMPLE 3 
     FIGS. 5A through 5E illustrate a process for producing another embodiment of the flip chip assembly according to the present invention. Referring now to FIG. 5A, an integrated circuit chip  501  similar to that in example 1 is cleaned in an alkaline solution containing 0.05 M phosphoric acid at room temperature (25 degrees C) with immersion time of 1 minute. The chip is then thoroughly rinsed in distillated water to ensure there is no residue left on the surface of integrated circuit chip. A multi-layered thin film  503  having the structure of chromium (500 A)/copper (700 A)/gold (1000 A), respectively, is selectively deposited on the terminal pads  502  to serve as a barrier and adhesive layer. 
     FIG. 5B shows a dielectric substrate  504  having a sheet of copper  505  on the top of the surface and covered by a layer of insulating film  506 . A plurality of via holes  507  having a thin copper film  508  on the sidewalls is arranged in such a manner that the input/output terminal pads  502  of the integrated circuit chip  501  can be totally or partially exposed when it is mounted on the substrate  504 . 
     FIG. 5C show the assembly immersed in the copper plating solution Sel-Rex “CUBATH M” (trademark) at 25 degrees C. An electric power source is connected to the copper  505  on the top surface of the dielectric substrate. The electroplating reaction initiates and continuously deposits copper  509  on the sidewalls of the via holes. As the plating process proceeds, the sidewall copper  509  continually grows. 
     FIG. 5D shows the plated copper forming on the gold surface of the thin film  503  of the terminal pads to provide electrical contacts to the terminal pads and initiate plating copper thereon. These electroplated joints  510  provide effective electrical and mechanical connections between the input/output terminal pads and the top surface of the dielectric circuitry. The insulating layer  506  is stripped off. 
     FIG. 5E shows a plurality of copper circuitry traces  511  formed on the surface of the substrate by conventional etching techniques. These traces  511  extend from a plurality of electroplated copper via holes  507  of the dielectric substrate  504  and serve as electrically connecting channels with respective input/output terminal pads  502  to the external circuitry. 
     EXAMPLE 4 
     FIGS. 6A through 6D illustrate a process for producing another embodiment of the flip chip assembly according to the present invention. Referring now to FIG. 6A, an integrated circuit chip  601  similar to that in example 1 has a plurality of input/output terminal pads  602  exposed. These pads  602  are firstly cleaned by dipping the integrated circuit chip  601  in a phosphoric acid solution at room temperature with an immersion time of 10 minutes to remove the surface oxide film. This chip is next dipped in a diluted catalytic solution Enthone “Alumon EN” (trademark) at 25 degrees C. for 20 seconds to form a thin zinc film  603  on the surface of aluminum alloy terminal pads  602  followed by a thorough distillated water rinse to ensure there is no residue left on the surface of integrated circuit chip. The integrated circuit chip is then immersed in a Shipley “NIPOSIT 468” (trademark) electroless plating bath for 2 minutes at 65 degrees C. A thin layer of nickel film  604  containing phosphorus is deposited on and around the terminal pads  602 . 
     FIG. 6B shows a double-sided or multi-layer dielectric substrate  605  having a plurality of copper circuitry traces  606 . The traces  606  on one surface of the substrate extend to a plurality of via holes  608  which are pre-metallized with gold plated copper film  607  on the sidewalls. These holes  608  are arranged in such a manner that the terminal pads  602  of the integrated circuit chip  601  can be totally or partially exposed when integrated circuit chip  601  is mounted on the substrate  605 . These holes  608  serve as electrically connecting channels for respective traces  606  on the top surface of the substrate  605  with respective input/output terminal pads  602  of the integrated circuit chip  601 . 
     FIG. 6C shows the integrated circuit chip  601  securely attached to the substrate  605 . Tin-lead solder balls  609  are placed into these via holes  608  by a conventional ball placement machine. Enough solder balls  609  should be placed to fill the via holes without exceeding the total volume. 
     As shown in FIG. 6D, heat is applied to the assembly. When the temperature reaches 350 degrees C. for 1 minute, the solder balls melt and fill the lower part of the via holes. When the heat is removed, solder columns  610  adhere to the sidewalls of the via holes as well as the input/output terminal pads  602  of the integrated circuit chip  601  thus providing effective electrical and mechanical contacts.