Abstract:
Signal distortions are avoided without the assistance of external component parts in an integrated circuit arrangement for voltage control of the gain of a field effect transistor having at least first and second gate electrodes. The first gate electrode forms the signal input and the second gate electrode forms the DC voltage control input. An integrated control circuit arrangement is provided which sets the voltage at the first gate electrode of the field effect transistor dependent on a variable voltage at the second gate electrode thereof, whereby the source potential remains unaltered.

Description:
BACKGROUND OF THE INVENTION 
     The invention is directed to an integrated circuit arrangement for voltage control of the gain of a field effect transistor having at least two gate electrodes. The first gate electrode forms the signal input and the second gate electrode forms the DC voltage control input. 
     Field effect transistors (FETs) having two gate electrodes (FET tetrodes) are utilized in controllable amplifier circuits (cascade circuits). The first gate electrode G1 is employed as signal input and the second gate electrode G2, by contrast, is employed as a DC voltage control input. In a circuit arrangement having fixed source and G1 potentials, only the drain current drops greatly with G2 given gain regulation, and operating points occur which lead to great signal distortions. 
     As may be seen from FIG. 2, this disadvantage can be avoided in a traditional way in that the source terminal of a field effect transistor T 1  comprising two gate electrodes G 1  and G 2  is only grounded in terms of alternating current (C S ), but has its DC voltage potential shifted in current-dependent manner, namely on the basis of a current divider having R 1  and R 2 . Given regulation over the second gate electrode G 2 , the drain current drops and thus the voltage drop-off via R 2 , i.e. the source potential, drops. During regulation, the voltage difference between the first gate electrode G 1  and the source electrode S is thereby modified such that operating points that lead to non-linear signal distortions are largely avoided. Simultaneously, the lowering of the drain current is thereby opposed. The applied operating voltage is referenced U B  and the control voltage is referenced U R . The signal input is provided with reference numeral 1 and the signal output is provided with reference numeral 2. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to create an integrated circuit arrangement of the type initially cited wherein the operating points are set such that signal distortions are avoided, namely without external component parts that serve as auxiliary means, and whereby the manufacturing tolerances of the signal-carrying field effect transistor are largely compensated. 
     According to the invention, an integrated circuit arrangement is provided for voltage control of the gain of a field effect transistor having at least two gate electrodes. With such a field effect transistor, the first gate electrode forms the signal input and the second gate electrode forms a DC voltage control input. The integrated circuit arrangement sets the voltage at the first gate electrode of the field effect transistor dependent on a variable voltage at the second gate electrode thereof, whereby the source potential remains unaltered. 
     The advantages achieved with the invention are particularly that the circuit arrangement can be realized in an adequately self-blocking MOS technique since one need not work with negative auxiliary voltages. The first, signal-carrying field effect transistor itself is not contained in any internal control circuit because the second field effect transistor, as a controlling component, contains (i.e., &#34;knows&#34;) the electrical properties of the first FET as completely as possible. Compared to the first, signal-carrying FET, the second FET thus forms an identical, although &#34;miniaturized&#34;, component. Moreover, the gate electrode and the source electrode of the second (control) FET are respectively connected to the same terminal of the first (signal) FET such that identical potential relationships prevail. So that the similarity of the characteristics of both transistors is not lost, it is expedient that the drain/source voltage of the control transistor does not become significantly lower than that of the signal transistor. Since the drain current dare not drop greatly initially, even given a G2 regulation, this is impressed with a current source. The drop-off of the drain current given great regulation thus necessarily occurs because of the finite operating voltage from which the current source is supplied. In order to close the control loop of the control transistor, a feedback from the drain electrode thereof onto the first gate electrode is provided. The current in the feedback branch is thus low in comparison to the drain current to be impressed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic illustration of a circuit arrangement according to the invention; 
     FIG. 2 is a prior art circuit arrangement; and 
     FIGS. 3 through 6 are exemplary embodiments of the circuit arrangement of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the circuit arrangement shown in FIG. 1, a second transistor T 2  similar to the signal-carrying or operating transistor T 1 , and likewise having at least two gate electrodes G 1  and G 2 , is inventively added. The source S, gate G 1  and gate G 2  thereof are respectively coupled in terms of DC voltage to the corresponding elements of the first transistor T 1 . A nearly constant direct current via the current source I is impressed on this second or control transistor T 2  at the drain electrode D. The drain voltage occurring is fed back onto the gate G 1  --after voltage division or voltage subtraction--in order to set the required gate 1 voltage. A direct connection of drain D and gate 1 of the control transistor T 2  is also possible in embodiments having a high, required gate 1 voltage. 
     Due to the similarity of the two field effect transistors T 1  and T 2 , the control curve impressed on the control transistor T 2  is projected onto the operating transistor T 1 . With decreasing gate 2 voltage (control voltage U R ), thus the gate 1 voltage rises at both transistors T 1 , T 2 . After the gate 2 voltage has been lowered to a defined extent, the drain current can no longer be impressed on the control transistor T 2 . However, the gate 1 voltage continues to rise up to an embodiment-dependent final value. 
     The second or control transistor T 2  can be designed smaller than the first or signal or operating transistor T 1  by a defined factor k=W 2  /W 1 . W 1  denotes the gate width of the signal transistor T 1 . W 2  denotes the gate width of the control transistor T 2  given nearly identical gate lengths of the two transistors. Correspondingly, the impressed constant current I must then be selected lower by the factor k than that desired at the signal transistor T 1 . 
     The other properties such as, for example, channel length and doping, are to be expediently coincidentally selected at both field effect transistor T.sub. and T 2  because the second or control transistor T 2  is then automatically matched to the first or signal-carrying transistor T 1 . 
     Nonetheless, versions are also fundamentally conceivable wherein the control behavior of the control transistor T 2  is reproduced in a form deviating from the signal transistor T 1 . In addition to differences in channel length and doping, this can thereby be a matter of a voltage divider between the control and the signal transistor. 
     For example, the current I impressed on the second or control transistor T 2  can derive from an additional, self-conducting FET triode in drain circuitry, or can be taken via a resistor from a voltage source whose voltage is adequately higher than the required drain-source voltage of the control transistor T 2 . Due to the size and constancy or reproducibility of this current source I, the behavior of the entire circuit arrangement is co-defined. The design of the feedback between drain and gate G 1  of the control transistor T 2  also plays a part therein. 
     For example, the circuit arrangement can be very simply realized with self-blocking dual gate FETs. 
     The circuit arrangement, however, is also functional with self-conducting FETs, for example by supplying a current via a resistor from a negative auxiliary voltage source into the gate 1 divider. 
     A circuit arrangement of the invention can thus be applied to field effect transistors having at least two gate electrodes in MIS (for example, Si-MOS) or MES (for example, GaAs barrier layer) technology. 
     A preferred application of the circuit arrangement is the monolithic integration of control (T 2 ) transistor and signal (T 1 ) transistor in the same manufacturing process. A constant current source can also be co-integrated. 
     The coupling of the gate electrodes of the second or control transistor T 2  to those of the signal-carrying, first transistor T 1  can occur in high-impedance fashion, particularly so as not to attenuate the input signal supplied to gate 1 of the operating transistor T 1 . The supply of the current source from the control voltage or the drain voltage of the signal transistor T 1  is also potentially conceivable as versions of the circuit arrangement given integration (eliminating a terminal leg). 
     Furthermore, given integration of a plurality of signal transistors T 1  on the same chip, such transistors can preferably be operated in common with a single control transistor T 2 . 
     In FIGS. 1 through 6, the signal input is referenced 1 and the signal output is referenced 2. U R  respectively denotes the control voltage, U V  denotes the supply voltage, and U B  denotes the operating voltage. 
     As an exemplary embodiment, FIG. 3 shows the realization of the circuit arrangement of the invention in MOS technology and with an ohmic voltage divider between drain electrode D and first gate electrode G 1  of the second field effect or control transistor T 2 . 
     FIG. 4 shows a further possible realization of the circuit arrangement in MOS technology, namely with voltage subtraction (diode flow voltages) between first gate electrode G 1  and drain electrode D of the control transistor or second field effect transistor T 2 . 
     FIG. 5 shows an exemplary embodiment of the circuit arrangement of the invention in MES technology and with negative auxiliary voltage U H  given a self-conductive property of the two transistors T 1  and T 2 . 
     In the circuit arrangement without external wiring shown in FIG. 6, the current source is realized with a bipolar transistor. The feedback, moreover, occurs here by use of non-linear resistors, namely with further bipolar transistors. 
     Although various minor changes and modifications might be proposed by those skilled in the art, it will be understood that I wish to include within the claims of the patent warranted hereon all such changes and modifications as reasonably come within my contribution to the art.