Abstract:
A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.

Description:
BACKGROUND OF THE INVENTION 
     I. Field of the Invention 
     The present invention relates generally to dynamic random access memory (DRAM). More specifically, the present invention relates to an improved memory device, which permits increased memory size with reduced power requirements. 
     II. Description of the Related Art 
     Improved manufacturing techniques are constantly being developed to increase the memory capacity of DRAM. These techniques have increased the possible number of transistors and other components on a single silicon chip. However, with increased capacity, the need for reduced power requirements still exists. This is most readily apparent in mobile devices which utilize memory, e.g., laptop computers, cellular telephones, etc. 
     New DRAM device bus architectures have also increased the speed of DRAM access. However, this increased speed results in greater power consumption and heat generation, which may cause overheating problems. For example, a Rambus DRAM SIMM (single in-line memory module) typically contains a heat sink as an effort to address the overheating problem. Therefore, a DRAM architecture that reduces power consumption would also help alleviate overheating associated with these new faster DRAM devices. Accordingly, there is a need for a memory device having increased memory size, yet reduced power consumption. 
     SUMMARY OF THE INVENTION 
     The present invention provides a device and method that permits the use of modern techniques to increase DRAM memory size while reducing power consumption. The present invention utilizes the internal memory sub array partitioning of a DRAM device and provides the capability of independently powering down each internal memory sub array thereby reducing power consumption when memory sub arrays are not being used for a period of time. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other advantages and features of the invention will become more apparent from the detailed description of preferred embodiments of the invention which are provided below with reference to the accompanying drawings in which: 
     FIG. 1 is a diagram of a DRAM device employing memory sub arrays in accordance with the present invention; 
     FIG. 2 is a diagram of a DRAM device employing memory sub arrays which uses an external memory controller in accordance with the present invention; 
     FIG.  3 ( a ) is a flow chart of a method for reducing power consumption of the DRAM device of FIG. 2 by powering down unneeded addresses; 
     FIG.  3 ( b ) illustrates a cross sectional view of the substrate upon which the DRAM device resides; 
     FIG. 4 is a flow chart of a method for reducing power consumption of the DRAM device of FIG. 2 by activating needed addresses; 
     FIG.  5 ( a ) is a flow chart of a method for reducing power consumption of the DRAM device of FIG. 2 by using a “variable persistence” technique; 
     FIG.  5 ( b ) is an illustration of a table used to employ the “variable persistence” technique of FIG.  5 ( a ); 
     FIG. 6 is an illustration of a processor-based system employing the reduced power consumption device and method of the present invention; and 
     FIG. 7 is an illustration of a memory module employing the reduced power consumption device and method of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring now to the drawings, where like reference numerals designate like elements, there is shown in FIGS. 1 and 2 a relevant portion of a memory device  100  for providing and storing data for data driven devices, e.g., computers, cellular telephones, etc. Memory device  100  includes a power supply  102 , an internal DRAM control logic  104 , address register  106 , power distribution terminal  108  and a plurality of memory array sectors  110 . Each memory array sector  110  contains of a plurality of memory sub arrays  118 . Memory device  100  may command the memory array sectors  110  itself, as in FIG. 1, or receive memory commands and corresponding memory addresses from an external memory controller  112 , as depicted in FIG.  2 . 
     FIG.  3 ( a ) illustrates in a first exemplary embodiment of the operation of the memory devices  100  shown in FIGS. 1 and 2 with particular reference to the external memory controller embodiment in FIG.  2 . The external memory controller  112  sends a memory command at step  300  to internal DRAM control logic  104  via data control bus  114 . A memory command can be a WRITE, READ, etc. Simultaneously with sending the memory command, the external memory controller  112  also sends a range of unneeded addresses for the memory command over address bus  116  to the address register  106  at step  300 . The address register  106  simply provides an interface for address information. The address register  106  passes the range of unneeded addresses at step  302  to internal DRAM control logic  104  in the form of data which identifies the range of addresses which require power for execution of the memory command. Given the range of unneeded addresses at step  302 , the remaining memory sub arrays  118  are those which are needed for the memory command. The internal DRAM control logic  104  receives and maps (translates) the data indicating the address range(s) of the needed addresses at operational steps  304  and  306 . The internal DRAM control logic  104  maps the needed addresses to memory sub arrays  118  which contain the needed addresses. That is, those sub arrays  118  which are needed for the memory operation are identified. The internal DRAM control logic  104 , having translated which addresses in the range of addresses correspond to needed memory sub arrays  118  at step  306 , sends control signals, via control signal bus  130 , to the power distribution terminal  108  at step  308 . The control signals instruct the power distribution terminal  108  to power down all sub arrays  118  not designated as needed by the memory command. For purpose of this disclosure, power, which is distributed by the power distribution terminal  108 , includes both a source positive voltage (Vcc) and a negative voltage (Vbb). Both Vcc and Vbb are partitioned for each memory sub array  118 . It is necessary to partition Vcc and Vbb to isolate each memory sub array  118  on the n-rail and p-rail of the substrate on which the memory device  100  resides, respectively. FIG.  3 ( b ) shows a cross sectional view of a substrate upon which the memory device  100  resides including Vcc terminals  380 ,  384  and Vbb terminals  382 ,  386 . When power distribution terminal  108  powers down a memory sub-array  118 , both a Vcc terminal and a Vbb terminal, for the corresponding memory sub-array  118 , are grounded (0 volts). 
     This is one way in which power consumption is reduced. In addition, the internal DRAM control logic  104  discontinues sending a REFRESH command, which is normally sent via REFRESH bus  132 , to the unneeded memory sub arrays  118 , that is, the memory sub arrays  118  which are not designated as needed for the memory operation at step  310 . In this way overall memory system power consumption is reduced. 
     For simplicity of explanation, it has been assumed that the memory device  100  is operating in a single tasking environment. In a multi-tasking environment the internal DRAM control logic  104  would check if any other memory commands are using the unneeded memory sub arrays  118  before powering them down. The internal DRAM control logic  104  could complete such a task with a simple truth table which is updated on each clock cycle indicating if a memory sub array  118  is being used by a memory command initiated in a previous clock cycle. 
     In another operational embodiment, depicted in FIG. 4, all memory sub arrays  118  are initially powered off as a default condition by the internal DRAM control logic  104  at step  400 . At this step the power distribution terminal  108  is instructed, through a control signal sent via control signal bus  130 , to cease supplying power to all memory sub arrays  118 . In addition, as a consequence of all memory sub arrays  118  not being supplied power, the internal DRAM control logic  104  does not send the REFRESH command, which is normally sent via REFRESH bus  132 , to any memory sub arrays  118 . When a memory function is needed, the external memory controller  112  sends a memory command, which effectuates the desired memory function, on data control bus  114  at step  404 . Simultaneously with sending the memory command, the external memory controller  112  also sends a range of addresses needed for the memory command over address bus  116  to the address register  106  at step  404 . The address register  106  simply provides an interface for address information. The address register  106  receives and passes the range of needed addresses to internal DRAM control logic  104  at step  406  in the form of data which identifies the range of addresses which require power for execution of the memory command. After receiving the memory command and data identifying the range of needed addresses in step  408 , the internal DRAM control logic  104  maps (translates) the address range of the needed addresses to memory sub arrays  118  which contain the needed addresses in step  410 . That is, those sub arrays  118  which are needed for the memory operation are identified. The internal DRAM control logic  104 , having translated which addresses in the range of addresses correspond to needed memory sub arrays  118 , sends control signals to the power distribution terminal  108  at step  412 . The control signals instruct the power distribution terminal  108  to power up the memory sub arrays  118  needed for the memory command at step  412 . In addition, the internal DRAM control logic  104  begins sending the REFRESH command only for the needed memory sub arrays  118  at step  414 . 
     FIG.  5 ( a ) illustrates yet another exemplary embodiment of operation which employs a “variable persistence” technique. When a memory function is needed the external memory controller  112  sends a memory command, which effectuates the desired memory function, on data control bus  114  at step  500 . Simultaneously with sending the memory command, the external memory controller  112  also sends a range of addresses needed for the memory command over address bus  116  to the address register  106  at step  500 . The address register  106  simply provides an interface for address information. The address register  106  receives and passes the range of needed addresses to internal DRAM control logic  104  at step  502  in the form of data which identifies the range of addresses which require power for execution of the memory command. After receiving the memory command and data identifying the range of needed addresses in step  504 , the internal DRAM control logic  104  maps (translates) the address range of the needed addresses to memory sub arrays  118  which contain the needed addresses in step  506 . That is, those sub arrays  118  which are needed for the memory operation are identified. The internal DRAM control logic  104 , having translated which addresses in the range of addresses correspond to needed memory sub arrays  118 , under this “variable persistence” technique, updates a “variable persistence” table at step  508 . The “variable persistence” table, shown in FIG.  5 ( b ), is maintained by the internal DRAM control logic  104 . The table includes a counter for each memory sub array  118 , which corresponds to a memory address range, indicating the number of memory clock cycles which have passed since each memory sub array  118  was last accessed, e.g. to perform a READ, WRITE operation, etc. When the counter for a memory sub array  118  reaches a predetermined memory clock cycle number, e.g.,  1000 , then the memory sub array  118  in question will be powered down since it is not being used at step  512 . The predetermined number can be, for example, the number of clock cycles equivalent to one minute, where one could fairly assume a memory sub array  118  is not going to be used in the immediate future if it has been idle for one minute. Prior to instructing the power distribution terminal  108  to power down those memory sub arrays  118  which have exceeded the allowable time on the counter and discontinuing the REFRESH function at steps  512  and  514 , the internal DRAM control logic  104  will cause the data from those memory sub arrays  118  to be written back to a non-volatile storage device, e.g. hard drive at step  510 . In the alternative, the internal DRAM control logic  104  can power those memory sub array  118  to less than full power and maintain its REFRESH function. While the later technique does not conserve as much power as the previous technique, it allows for a quicker response time as data may not need to be written and then re-retrieved from a non-volatile storage device, which is typically slower then a volatile memory device such as memory device  100 . 
     FIG. 6 illustrates a processor system  600 , including memory device  612  constructed in accordance with the present invention as described above with reference to FIGS. 2-5. The processor system  600  may be a computer system, a process control system or any other system employing a processor and associated memory devices. The processor system includes a central processing unit (CPU)  602 , e.g., microprocessor, that communicates with input/output devices  608 ,  610 , floppy drive  604 , memory device  614  and CD ROM drive  606  over a bus  620 . The CPU  602  and memory device  612  may be provided on a single integrated circuit chip. 
     FIG. 7 shows a memory module  700  having memory chips  60 - 68  with semiconductor memory devices constructed in accordance with the present invention as described above with reference to FIGS. 2-5. Memory module  700  is a SIMM (single in line memory module) having nine memory chips (IC&#39;s)  60 - 68  aligned on one side of a printed circuit board substrate. Memory chips  60 - 68  employ the reduced power consumption structure and method of the present invention. 
     It is to be understood that the above description is intended to be illustrative and not restrictive of the invention. Many variations to the above-described device and method including substitution of equivalent steps and structures will be readily apparent to those having ordinary skill in the art. Accordingly, the present invention is not to be considered as limited by the specifics of the particular devices and methods, which have been described and illustrated, but is only limited by the scope of the appended claims.