Abstract:
A circuit for operating a consumer comprises a current source, a first switch connected in parallel with the consumer and actuated potentially separate, whereby opening and closing the first switch transmits power to the consumer in the form of square wave current pulses. The negative branch includes a potentially separately actuated second switch connected in parallel with the first switch and in series with the consumer, as well as a first load connected in parallel with the first switch and in series with the consumer. The positive branch includes a potentially separately actuated third switch connected in parallel with the first switch and in series with the consumer and second switch, as well as a second load connected in parallel with the first switch and in series with the consumer and the second switch. The second and third switches are opened and closed in anti-phase manner to the fist switch.

Description:
BACKGROUND OF THE INVENTION 
     The present invention concerns a circuit for controlling the power supply of a consumer, as well as a method of operating a circuit. The present invention especially concerns a low-interference power supply of a consumer with current pulses. 
       FIGS. 1-3  show a circuit as it is currently known. A known circuit  100  comprises a switch mode current source  1  SMC. The current source  1  is controlled by means of a control system  2 , so that it is possible to maintain the power I 1  supplied by the current source  1 . Here the control system comprises a current measuring device via a resistor  3  in order to guarantee a respective control of the current source. 
     Furthermore, the circuit  100  comprises inductance  4 , as well as a consumer  10  that is supplied with power by means of the current source. In an exemplary manner the consumer  10  is depicted as a diode operating in forward direction. 
     Parallel to the consumer  10 , the circuit  11  comprises a first switch  7  which is controlled via a first driver unit  6 . For this purpose, the first driver unit  6  is supplied with a pulse control signal  5  consisting of pulses and pulse intervals so that during the pulse interval the switch  7  is conductively controlled via a driver unit  6 , and during a pulse the switch is suddenly block controlled. 
     The functionality of the known circuit is divided in three phases P 1 , P 2  and P 3 , depending on the pulse control signal  5 .  FIGS. 1-3  provide a schematic picture of the three phases, whereas  FIG. 1  shows the first phase,  FIG. 2  the second phase, and  FIG. 3  the third phase. 
     The pulse control signal consists of pulses and intermediate pulse intervals. In the present description the first pulse interval is denoted with P 1 , a subsequent pulse with P 2 , and a second pulse interval following pulse P 2  is denoted with P 3 . 
     In the currently known circuit a second switch  13  has been provided which is connected in series to the consumer  10  and parallel to the first switch  7 . This second switch  13  is actuated anti-phase to the first switch, which means that during the process of closing the first switch the second switch is opened and vice versa. In the context of the present invention, the term “closing” a switch means that the switch is conductively controlled by the respective driver unit. Similarly, the term “opening” a switch means that the switch is block controlled by the respective driver. Furthermore, a load  14  has been provided which is arranged in series to the consumer  10  and parallel to the first switch  6  and which comprises high load voltage. In this way it is possible to reduce considerably the fall time. 
     Subsequently, by means of  FIGS. 1 ,  2  and  3 , the functionality of the known circuit  100  is explained.  FIG. 1  depicts the first phase P 1  of the pulse control signal  5 ,  FIG. 2  the second phase P 2  of the pulse control signal  5 , and  FIG. 3  the third phase P 3  of the pulse control signal  5 . 
       FIG. 1  shows a pulse inverter  15  which inverts the pulse control signal  5  and transmits it to a second driver unit  12 . In its functionality, the second driver unit  12  corresponds to the first driver unit  6  and is used to actuate the second switch  13 . The load  14  is connected in parallel to the second switch  13 . 
       FIG. 1  provides a schematic picture of the first phase P 1  of the pulse control signal  5 . During the pulse interval, the first switch  7  is conductively controlled and the second switch  13  is block controlled. The adjusted power I 1 , which has been impressed by the current source  1 , flows through the inductance  4  and the first switch  7  back to the current source  1 . The consumer  10 , the load  14  and the second switch  13  are currentless. 
       FIG. 2  provides a schematic picture of the second phase P 2 , namely the pulse signal. By means of the pulse signal the first switch  7  is suddenly block controlled and, at the same time, the second switch  13  is conductively controlled so that the power I 1  impressed via the current source  1  no longer flows through the first switch  7  but, because of the behavior of the current source  1  and inductance  4 , said power flows back with a short rise time to the current source  1  in the form of pulses and square waves through the consumer  10  and the second switch  13 . 
       FIG. 3  provides a schematic picture of the third phase P 3 , namely the pulse signal. Also in this pulse interval the first switch  7  is conductively controlled and, at the same time, the second switch  13  is block controlled. In this way the consumer  10  becomes currentless the same as the second switch  13  and the impressed power I 1  and flows again back to the current source  1  via the inductance  4  and the first switch  7 . 
     At the start of the third phase P 3  power I 2  flows through the consumer  10  because of the magnetic energy stored in the circuit inductances  8 ,  9  during the second phase P 2 . At the start of the third phase P 3  the power I 2  has the same value as power I 1 . 
     However, as time increases, the power is reduced until it reaches zero. 
     For this purpose, parallel to the second switch  13 , a load  14  has been provided which can be a Zener diode with high Zener voltage. At the load  14  the decaying power I 2  generates a load voltage U L  which together with the secondary voltage U V  of the consumer  10  forms an overall voltage with regard to the fall time t of the power I 2 . The load  14  is designed in such a way that it produces high load voltage U L , resulting in a very short fall time of the power I 2 . 
     If the secondary voltage U V  and the load voltage U L  are not power-dependent, the following applies to the fall time t of the power I 2 : 
     
       
         
           
             t 
             = 
             
               
                 
                   I 
                   1 
                 
                 ⁡ 
                 
                   ( 
                   
                     
                       L 
                       1 
                     
                     + 
                     
                       L 
                       2 
                     
                   
                   ) 
                 
               
               
                 
                   U 
                   V 
                 
                 + 
                 
                   U 
                   L 
                 
               
             
           
         
       
     
     For example, in case of a circuit inductance of respectively 50 nH, a load current of 100 A, a secondary voltage U V  of 2V, and a load voltage U L  of 100 V, the fall time results in: 
     
       
         
           
             t 
             = 
             
               
                 
                   100 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     A 
                     · 
                     
                       ( 
                       
                         50 
                         + 
                         50 
                       
                       ) 
                     
                     · 
                     
                       10 
                       
                         - 
                         9 
                       
                     
                   
                   ⁢ 
                   H 
                 
                 
                   
                     2 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                   + 
                   
                     100 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                 
               
               = 
               
                 
                   98 
                   · 
                   
                     10 
                     
                       - 
                       9 
                     
                   
                 
                 ⁢ 
                 s 
               
             
           
         
       
     
     Because of the anti-phase actuation of both switches the power I 2  can be directed to zero via a load with high load voltage within a short period of time. 
     In a known circuit the switch mode current source in particular can cause high frequency interferences in the control unit. As shown in  FIG. 4 , the control system  2  can be coupled with the ground  19 , i.e., with the housing and/or the earth, in order to reduce these high frequency interferences. The coupling with the ground can take place in galvanic or capacitive manner or at high frequency by means of a capacitor  18  so that the ground (Gnd) of the control system  2  is connected with a metallic housing which, in turn, is electrically connected with earth  19 . 
       FIG. 4  shows that, besides the circuit inductances  8 ,  9 , the known circuit comprises a first line capacity  16  and a second line capacity  17  to the earth, which line capacities are shown in the equivalent circuit diagram in  FIG. 4  as capacitors  16 ,  17 . 
     By means of the circuit shown in  FIG. 4 , it is possible to minimize the high frequency interferences. However, the circuit shows several disadvantages. The known circuit has especially the disadvantage that in the various phases of the pulse control signal  5  power flows through the ground  19 , i.e., through the housing or the earth. Subsequently, by means of  FIGS. 4-8 , this is explained in more detail. 
       FIG. 4  shows the first phase P 1 , which is the pulse interval. During the first phase P 1 , the first switch  7  is conductively controlled, whereas the second switch  13  is block controlled. The adjusted power I 1 , which has been impressed by the current source  1 , flows through the inductance  4  and the first switch  7  in the line between D and C back to the current source  1 . 
       FIG. 5  shows the time period between the end of phase P 1  and the start of the second phase P 2  of the pulse control signal  5 . At this the first switch  7  is suddenly block controlled and, at the same time, the second switch  13  is conductively controlled. The voltage at the first switch  7  jumps to very high values, for example, several 100 V, because the current source  1  and especially the inductance  4  make an attempt to maintain the current flow I 1 . However, at first, both circuit inductances  8 ,  9  prevent a current flow through the consumer  10 . Therefore, the current now flows suddenly via the first line capacity  16 , through the metallic housing  19  or through the earth  19  and via the capacitor  18  back to the current source  1 . 
     In this phase considerable high frequency interferences occur and, at the same time, a high frequency interference voltage occurs in the line between D and C, because this line is suddenly supplied with power. 
     A further disadvantage is the fact that, at the moment of the voltage jump at the first switch  7 , the potential at point A in reference to earth jumps to a positive value corresponding to the voltage at the first switch  7 . On the other hand, because of the galvanic or high frequency grounding of the control system  2 , the potential at point B remains completely or nearly at earth potential. In case the circuit inductances  8 ,  9  values are equal, the potential at the consumer  10  in reference to earth jumps to half the value of the potential at point A. 
     If the consumer  10  is not adequately insulated to ground  19 , it can result in a breakdown or destruction of the consumer  10 . 
       FIG. 6  shows the second phase P 2 . In this phase further high frequency interferences can occur if, as shown in  FIG. 6 , the consumer  10  has assumed the power I 1 , because now there suddenly no power flows any longer via the first line capacity  16 , through the metallic housing or through the earth  19  and via the capacitor  18  and, at the same time, the line between D and C is suddenly supplied again with the power I 1 . 
       FIG. 7  shows the time period between the end of the second phase P 2  and the start of the third phase P 3  of the pulse control signal  5 . Here, the first switch  7  is suddenly conductively controlled and, at the same time, the second switch  13  is block controlled. The power I 1  now flows again via the first switch  7  back to the current source  1 . At the same time, because of the energy stored in the circuit inductances  8 ,  9 , an impressed power I 2  continues to flow through the consumer  10 . Since the second switch  13  is blocking, power I 2  flows (as shown in  FIG. 7 ) suddenly back in the line between C and D, via the second line capacity  17 , through the metallic housing or through the earth  19  and via the capacitor  18 . 
     At this considerably high frequency interferences occur and, at the same time, a high frequency interference voltage occurs in the line between C and D because the line supplied with the power I 1  is severely interrupted by the power I 2 . 
     Furthermore, the second line capacity  17  is quickly charged with the power I 2 . If the voltage at the second line capacity  17  has reached the breakdown voltage U LI  of the load  14  which is, for example, depicted as a Zener diode, the load  14  suddenly assumes the power I 2 , as shown in  FIG. 8 . 
     This again results in high frequency interferences because the metallic housing or the earth  19  is suddenly without power I 2 . At the same time a considerably high frequency interference voltage occurs in the line between C and D because the line is now also suddenly without power I 2 . 
     A further disadvantage is the fact that the potential at point B in reference to earth  19  jumps to a positive value corresponding to the load voltage U LI . On the other hand, because of the conductively controlled first switch  7  and the galvanic or high frequency grounding of the control system  2  via the capacitor  18 , the potential at point A remains completely or nearly at earth potential. In case the circuit inductances  8 ,  9  values are equal, the potential at the consumer  10  in reference to earth jumps to half the value of the potential at point B. If the consumer  10  is not adequately insulated to ground  19 , it can result in a breakdown or destruction of the consumer  10 . 
     SUMMARY OF THE INVENTION 
     It is therefore the objective of the present invention to resolve the disadvantages of the known circuit. In particular the invention has the objective of providing a circuit for controlling the power supply of a consumer, as well as a method for operating a circuit which allows for short rise times, as well as short fall times and which, at the same time, reduces interferences. Furthermore, it is the objective of the present invention to provide a secure circuit in which a possible housing that houses the circuit is not supplied with power. In addition it is the objective of the present invention to reduce the danger of destroying the components of the circuit. 
     This objective is achieved by means of the characteristics of the independent claims. Advantageous embodiments are discussed in the sub-claims. 
     The present invention concerns a circuit for controlling the power supply of a consumer comprising a current source for providing power supply to a consumer, a first switch which is connected in parallel with the consumer and actuated potentially separate. By opening and closing the first switch the power is transmitted to the consumer in the form of square wave current pulses, in the negative branch a second switch actuated potentially separate, connected in parallel with the first switch and connected in series with the consumer, as well as a first load connected in parallel with the first switch and connected in series with the consumer, and in the positive branch a third switch actuated potentially separate, connected in parallel with the first switch and in series with the consumer and to the second switch, as well as a second load connected in parallel with the first switch and connected in series with the consumer and with the second switch, whereas the second switch and the third switch are opened and closed in anti-phase manner to the first switch. 
     Preferably, the current source is a DC current source. 
     In a first embodiment, the first load is connected in parallel with the second switch and the second load is connected in parallel with the third switch. 
     In this first embodiment, the first load and/or the second load can comprise a resistor, a voltage-dependent resistor, a capacitor, a diode, a Zener diode, a suppressor diode, a semi-conductor with controlled avalanche behavior or a combination herefrom. 
     In a second to seventh embodiment, the second switch and the first load are combined in a component and the third switch and the second load are combined in a component. 
     Preferably, the load and the associated switch are combined in a semi-conductor switch with controlled avalanche behavior. 
     Advantageously, the controlled avalanche behavior of the semi-conductor switch can be produced by means of the characteristics of the semi-conductor. 
     Alternatively, the controlled avalanche behavior of the semi-conductor can be produced by means of external wiring of the semi-conductor. 
     In a third embodiment a first protective diode is connected in parallel with the consumer. 
     In a fourth embodiment a second protective diode in the negative branch is connected in series with the consumer and a third protective diode is connected in series with the consumer in the positive branch. 
     In a fifth embodiment a first resistor is connected in parallel with the second switch and a second resistor is connected in parallel with the third switch. 
     In a sixth embodiment a first constant current load is connected in parallel with the second switch and a second constant current load is connected in parallel with the third switch. 
     In a seventh embodiment a system for current measurement has been provided and by means of a suitable arrangement a signal is supplied to the second switch and the third switch in such a way that the second switch and the third switch are again conductively controlled below a specific power. 
     Further characteristics, advantages and features of the present invention are explained by means of the figures of the accompanying drawings and the detailed description of the embodiments. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  a first phase of a first known circuit, 
         FIG. 2  a second phase of a first known circuit, 
         FIG. 3  a third phase of a first known circuit, 
         FIG. 4  a first phase of a second known circuit, 
         FIG. 5  the transition from the first to a second phase of a second known circuit, 
         FIG. 6  a second phase of a second known circuit, 
         FIG. 7  the transition from the second to a third phase of the second known circuit, 
         FIG. 8  a third phase of a second known circuit, 
         FIG. 9  a first phase of a first embodiment of the present invention, 
         FIG. 10  a second phase of a first embodiment of the present invention, 
         FIG. 11  a third phase of a first embodiment of the present invention, 
         FIG. 12  a first phase of a first embodiment of the present invention, 
         FIG. 13  the transition from the first phase to a second phase of a first embodiment of the present invention, 
         FIG. 14  a second phase of a first embodiment of the present invention, 
         FIG. 15  the transition from the second to a third phase of a first embodiment of the present invention, 
         FIG. 16  a third phase of a first embodiment of the present invention, 
         FIG. 17  the third phase of a second embodiment of the present invention, 
         FIG. 18  the third phase of a third embodiment of the present invention, 
         FIG. 19  the third phase of a fourth embodiment of the present invention, 
         FIG. 20  the third phase of a fifth embodiment of the present invention, 
         FIG. 21  the third phase of a sixth embodiment of the present invention, 
         FIG. 22  the third phase of a seventh embodiment of the present invention, 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIGS. 9-22  show the different embodiments of the present invention. The same components are depicted with the same reference numerals. A circuit  11  according to the present invention comprises a current source  1  which is preferably a switch mode current source  1  SMC. The current source  1  is controlled by means of a control system  2  so that the power I 1  provided by the current source  1  can be maintained. The control system comprises a current measuring device by means of a resistor  3  in order to guarantee that the current source is appropriately actuated. 
     Furthermore, the circuit  11  comprises a first inductance  4  in the positive branch, a second inductance  20  in the negative branch, as well as a consumer  10  which is supplied with power by means of the current source  1 . In the embodiment shown, the consumer  10  is depicted in an exemplary manner as a diode operating in forward direction. However, the consumer  10  is not restricted to the embodiment shown and can be applied to any other consumer  10  which is operated with current pulses. 
     Parallel to the consumer  10 , the circuit  11  comprises a switch  7  which is actuated potentially separate by a first driver unit  6  depicted in  FIGS. 9-11 , for example, as a vector. For this purpose, the first driver unit  6  is supplied with a pulse control signal  5  consisting of pulses and pulse intervals so that during the pulse interval the switch  7  is conductively controlled via a driver unit  6 , and during a pulse said switch is suddenly block controlled. 
     As previously explained, the present description depicts a first pulse interval with P 1 , a subsequent pulse with P 2  and a second pulse interval following the pulse P 2  with P 3 . Although the present description is restricted to explaining three pulse phases P 1 , P 2  and P 3 , it is obvious that this phase is followed by a succession of several pulses and pulse intervals. Especially the phases P 2  and P 3  are repeated. 
     As previously explained, in the known circuit, it has been arranged that a first switch  7  is located parallel to the consumer  10 , and in the negative branch a second switch  13  is connected in parallel with the first switch  7  and in series with the consumer  10 . According to a first embodiment, a load  14  is connected in parallel with the second switch  13  which features high load voltage and reduces the fall time of the power. 
     Moreover, according to the present invention, the second switch  13  is actuated potentially separate via the driver unit  12 , which is depicted in  FIGS. 9-22 , for example, as a vector. Furthermore, a third switch  22  has been provided in the positive branch and said switch is connected in series with the consumer  10  and in parallel with the first switch  7 . The third switch  22  is actuated potentially separate via the driver unit  21 , which is depicted in  FIGS. 9-22 , for example, as a vector. According to the first embodiment, a second load  23  has been provided in parallel with the third switch and said load also features high load voltage. 
     The term potentially separate actuation in the sense of the present invention means that the pulse control signal  5  is separated in galvanic manner from the driver units and thus it is separated in galvanic manner also from the three switches. Accordingly, the driver units are depicted in  FIGS. 9-22 , for example, as vectors. However, the drivers can be separated in galvanic manner from the pulse control signal  5  also by means of an optocoupler. Since the driver units are separated in galvanic manner from the pulse control signal  5 , the switches are also separated in galvanic manner from the pulse control signal  5 . This is necessary because, depending on the phase of the pulse control signal  5 , the switches are located on different potentials. Without galvanic isolation from the pulse control signal  5 , the switches could not assume different potentials. The isolation allows the switches to float. 
     In this first embodiment, the first load  14  and the second switch  13 , as well as the second load  23  and the third switch  22  are separated components. As subsequently shown by means of further embodiments, it is possible to combine the second switch and the first load in one component. The third switch and the second load can also be combined in one component. 
     The functionality of the invention-based circuit  11  is subsequently explained by means of the first embodiment depicted in  FIGS. 9-11 .  FIG. 9  shows the first phase P 1  of the pulse control signal  5 ,  FIG. 10  shows the second phase P 2  of the pulse control signal  5 , and  FIG. 11  shows the third phase P 3  of the pulse control signal  5 . 
       FIG. 9  depicts a pulse inverter which inverts the pulse control signal  5  and transmits the inverted signal to the second driver unit  12  and a third driver unit  21 . In their functionality, the second driver unit  12  and the third driver unit  21  correspond to the first driver unit  6 , respectively, and they are used to actuate the second switch  13  or the third switch  22 . In this first embodiment, the first load  14  is connected in parallel with the second switch  13 , and the second load  23  is connected in parallel with the third switch  22 . 
       FIG. 9  depicts the first phase P 1  of the pulse control signal  5 . During the pulse interval, the first switch  7  is conductively controlled, and the second switch  13  and the third switch  22  are block controlled. The adjusted power I 1 , which has been impressed by the current source  1 , flows through the first inductance  4 , the first switch  7  and the second inductance back to the current source  1 . The consumer  10 , the second switch  13 , the third switch  22 , as well as the first load  14  and the second load  23  are currentless. 
       FIG. 10  provides a schematic picture of the second phase P 2 , namely the pulse signal. By means of the pulse signal, the first switch  7  is suddenly block controlled and, at the same time, the second switch  13  and the third switch  22  are conductively controlled so that the power I 1  impressed via the current source  1  no longer flows through the first switch  7  but, because of the behavior of the current source  1 , the first inductance  4  and the second inductance  20 , said power flows back with a short rise time to the current source  1  in the form of pulses and square waves through the consumer  10 , as well as the second switch  13  and the third switch. 
       FIG. 11  provides a schematic picture of the third phase P 3 . In this pulse interval, the first switch  7  is again conductively controlled and, at the same time, the second switch  13  and the third switch  22  are block controlled. In this way, the consumer  10 , as well as the second switch  13  and the third switch  22  become currentless, and the impressed power I 1  flows again back to the current source  1  via the inductances  4 ,  20  and the first switch  7 . 
     At the start of the third phase P 3 , power I 2  flows through the consumer  10  because of the magnetic energy stored during the second phase P 2  in the circuit inductances  8 ,  9 . At the start of the third phase P 3 , power I 2  has the same value as the power I 1 . However, with increasing time, the power is reduced until it finally reaches zero. 
     In the first embodiment at hand, a first load  14  has been provided parallel to the second switch, and a second load  23  parallel to the third switch  22 . In the embodiment at hand, said load can represent a Zener diode with high Zener voltage, respectively. At this, the decaying power I 2  generates a first load voltage U L1  or a second load voltage U L2  at the first load  14  and at the second load  23 , which together with the secondary voltage U V  of the consumer  10  forms an overall voltage with regard to the fall time of the power I 2 . Advantageously, the first load  14  and the second load  23  are designed in such a way that it produces high load voltage U L1  and U L2 , resulting in a very short fall time of the power I 2 . 
     If the secondary voltage U V  and the two load voltages U L1  and U L2  are not current-dependent, the following applies to the fall time t of the power I 2 : 
     
       
         
           
             t 
             = 
             
               
                 
                   I 
                   1 
                 
                 ⁡ 
                 
                   ( 
                   
                     
                       L 
                       1 
                     
                     + 
                     
                       L 
                       2 
                     
                   
                   ) 
                 
               
               
                 
                   U 
                   V 
                 
                 + 
                 
                   U 
                   
                     L 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 + 
                 
                   U 
                   
                     L 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
               
             
           
         
       
     
     In the previously mentioned example with a circuit inductance of 50 nH, respectively, a load current of 100 A, a secondary voltage U V  of 2V, and a load voltage U L  of 100 V, respectively, the fall time results in: 
     
       
         
           
             t 
             = 
             
               
                 
                   100 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     A 
                     · 
                     
                       ( 
                       
                         50 
                         + 
                         50 
                       
                       ) 
                     
                     · 
                     
                       10 
                       
                         - 
                         9 
                       
                     
                   
                   ⁢ 
                   H 
                 
                 
                   
                     2 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                   + 
                   
                     100 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                   + 
                   
                     100 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                 
               
               = 
               
                 
                   49 
                   · 
                   
                     10 
                     
                       - 
                       9 
                     
                   
                 
                 ⁢ 
                 s 
               
             
           
         
       
     
     By means of the present invention in which the first switch  7  is actuated potentially separate, and by means of providing a second switch which is actuated potentially separate and a third switch which is actuated potentially separate, as well as providing a further inductance  20 , it is still possible to achieve short fall times and short rise times, the same as in the known circuit. In addition, the present invention allows for low-interference operation. Even in case the control system  2  is coupled with the ground it is possible to provide low-interference operation. Subsequently, in  FIGS. 13-16 , this aspect is explained in more detail. Here again, the first embodiment is represented in an exemplary manner with a load which is connected in parallel with the second and third switch, respectively. However, the following designs can also be applied to other embodiments. 
     At this, as in the known circuit, the control system  2  is coupled with the ground  19 . This can be achieved either by means of a galvanic connection or in capacitive manner or at high frequency by means of a capacitor  18 . In this way, it is possible to reduce high frequency interferences in the control unit, which are mainly caused by the switch mode current source  1 . At the same time, each of the two lines to the consumer  10  comprise a line capacity to the earth  19 , which are represented in  FIGS. 13-16  with a first capacitor  16  and a second capacitor  17  in the equivalent circuit diagram. Even in the case that the control system is not coupled with the ground, the present circuit allows for low interference operation. 
       FIGS. 4-8  already discussed the different phases in the known circuit. Subsequently, the same phases in the case of the invention-based circuit are explained by means of  FIGS. 12-16 , emphasizing the advantages of the present invention. 
       FIG. 12  shows the first phase P 1  of the pulse control signal  5 . During the pulse interval, the first switch  7  is conductively controlled, the second switch  13  and the third switch  22  are block controlled. The adjusted power I 1 , which has been impressed by the current source  1 , flows through the first inductance  4 , the first switch  7  and through the second inductance  20  back to the current source  1 . The consumer  10  is currentless. 
       FIG. 13  shows the time period between the end of the first phase P 1  and the start of the second phase P 2  of the pulse control signal  5 . If the first switch  7  is suddenly block controlled and, at the same time, the second switch  13  and the third switch  22  are conductively controlled, the voltage at the first switch  7  jumps to very high values, for example, several 100 V, because the current source  1  and especially the inductances  4  and  20  make an attempt to maintain the current flow I 1 . However, at first, both circuit inductances  8 ,  9  prevent a current flow through the consumer  10 . 
     In contrast to the known circuit, which is described in  FIG. 5 , given the same values of the inductances  4 ,  20  at the moment of the voltage jump at the first switch  7 , the potential at point A in reference to earth jumps to a positive value corresponding to half the voltage at the first switch  7 . The potential at point B in reference to earth  19 , however, jumps to a negative value corresponding to half the voltage at the first switch  7 . Consequently, the impressed power I 1  flows via the first line capacity  16 , the second line capacity  17  and via the inductance  20  back to the current source  1 . As a result, no power flows through the metallic housing or through the earth  19  and via the capacitor  18  back to the current source  1 , thus not causing any high frequency interferences. Also in the line between D and C, no high frequency interference voltage occurs because the power I 1  in this line remains unchanged. Furthermore, the present circuit guarantees high safety standards, because no power flows through the housing in which such a circuit could be housed. 
     A further advantage involves the fact that in case of equally high circuit inductances  8 ,  9  the potential from the consumer  10  to the earth remains unchanged. Consequently, the consumer has almost earth potential and therefore the consumer does not have to be isolated to earth with high proof voltage. As a result, it is less likely that certain components of the present circuit  11  fail. In addition, the structure of the housing, in which the circuit is housed, can be simplified because no special isolation is required. In contrast to the known circuit, there are also no high frequency interferences if, as shown in  FIG. 14 , the consumer has assumed the power I 1  in the second phase P 2 . 
       FIG. 15  shows the time period between the end of the second phase P 2  and the start of the third phase P 3  of the pulse control signal  5 . The first switch  7  is suddenly conductively controlled and, at the same time, the second switch  13  and third switch  22  are block controlled. Again the power I 1  flows back to the source via the first switch  7 . Simultaneously, because of the energy stored in the circuit inductances  8  and  9 , an impressed power I 2  continues to flow through the consumer  10 . Since the second switch  13  and the third switch  22  are blocked, the power no longer flows like in the known circuit (shown in  FIG. 7 ) suddenly via the second line capacity  17  through the metallic housing or through the earth  19  and via the capacitor  18  back in the line between D and C, but it flows back (as shown in  FIG. 15 ) via the second line capacity  17  and the first line capacity. 
     In contrast to the known circuit  100 , no high frequencies interferences occur in this case, because no power flows through the metallic housing or through the earth  19 . High frequency interference voltage does not even occur in the line between D and C because the power I 1  in this line remains unchanged. As shown in  FIG. 15 , the power I 2  very quickly charges the line capacities  16  and  17 . If the voltage at the line capacities  16  and  17  has reached the breakdown voltage U L1  of the first load  14  and the breakdown voltage U L2  of the second load  23 , the loads  14 ,  23  suddenly assume in the third phase P 3  (as shown in  FIG. 16 ) the power I 2 . In contrast to the known circuit, this again does not result in high frequency interferences because no power flows through the metallic housing or through the earth  19 , 
     High frequency interference voltage also does not occur in the line between D and C because the power I 1  in this line remains unchanged. Also in contrast to the known circuit, the potential at point B to earth  19  jumps to a positive value corresponding to the voltage U L2 . The potential at point A, on the other hand, jumps to a negative value corresponding to the voltage U L2 . In case the values of the circuit inductances  8 ,  9  are equal, the consumer  10  remains almost at earth potential and therefore the consumer does not have to be isolated to earth with high proof voltage. 
     Consequently, by means of the present invention, high frequency interferences are prevented. At the same time, high safety standards are guaranteed because no power flows through the housing or through the earth. What is more, the functionality of the circuit, which guarantees short fall times of the power I 2 , is not affected but is actually further improved by an additional load. 
     The principle of the present invention has been described by means of a first embodiment, which is shown in  FIGS. 9-16 . Here a load with high load voltage has been connected in parallel with the second switch  13  and the third switch  22 , respectively. 
       FIG. 17  shows a second embodiment according to the circuit  11  of the present invention. The second switch  24  used in the embodiment shown in  FIG. 17  is a semi-conductor switch with controlled avalanche behavior, which provides this switch with the additional function of a load. The third switch  25  is also a semi-conductor switch with controlled avalanche behavior, which provides the third switch  25  also with the additional function of a load. Consequently, it is not required to have, as in the first embodiment, an additional load which is connected in parallel with the respective switch. The avalanche behavior of both switches  24 ,  25  can be produced through the characteristics of the semi-conductor itself or through suitable external wiring of the semi-conductor. At the start of the third phase P 3 , while the second switch  24  and the third switch  25  are block controlled, the power I 2  generates at the switches such high voltage that said switches reach the avalanche breakthrough and keeps the present voltage at the value of breakdown voltage until the power I 2  has reached zero. If a semi-conductor with high breakdown voltage is selected for the second and third switch  24 ,  25 , the fall time of the power I 2  is very short. 
       FIGS. 18-22  show further embodiments of the present invention-based circuit  11 , in which the second switch  24  and the third switch  25  each are a semi-conductor switch with controlled avalanche behavior. In the embodiments shown, the second switch  24  and the third switch  25  have a parasitic parallel capacity (drain-source capacity), which are displayed in the diagram as capacitors  26  and  27 . At the start of the third phase P 3 , when the power I 2  approaches the zero point, the second switch  24  and the third switch  25  transfer, while the breakdown voltage is present, from the avalanche breakthrough to the blocking state. At this the parallel capacities remain unwantedly loaded at a voltage value of U C2  or U C3 , corresponding to the values of the breakdown voltage of the second switch  24  and the third switch  25 . These voltages U C2  or U C3  are directed in such a way that they rest inversely against the consumer  10 . If, for example, a diode with low blocking voltage is used as consumer  10 , it would be destroyed as a result of the present inverse voltage. In the following embodiments this problem is avoided. 
       FIG. 18  shows a third embodiment of the present invention, in which a first protective diode  28  is connected in parallel with the consumer  10 , thus avoiding an inverse voltage at the consumer  10 . 
       FIG. 19  shows a fourth embodiment of the invention-based circuit  11 , in which a second protective diode  29  in the negative branch is connected in series with the consumer  10  and in which a third protective diode  30  in the positive branch is connected in series with the consumer  10 , also in this case avoiding an inverse voltage at the consumer  10 . 
       FIG. 20  shows a fifth embodiment, in which a first resistor  31  is connected in parallel with the second switch  24 , thus discharging the parasitic parallel capacity  26  of the switch  24 . Similarly, a second resistor  32  has been provided in parallel with the third switch  25  which discharges the parasitic parallel capacity  27  of the switch  25 . Here the resistors are dimensioned in such a way that at the time in which the power I 2  has reached zero also the voltages U C2  or U C3  at the second or third switch  24 ,  25  have reached zero. Consequently, the capacities have been discharged and inverse voltage at the consumer  10  has been avoided. 
       FIG. 21  shows a sixth embodiment of the invention-based circuit  11 , in which a first constant current load  33  is connected in parallel with the second switch  24  and a second constant current load  34  is connected in parallel with the third switch  25 , thus discharging the capacities of the capacitors  26 ,  27 . Here the constant current loads  33 ,  34  are dimensioned in such a way that at the time in which the power I 2  has reached zero also the voltages U C2  or U C3  at the second or third switch  24 ,  25  have reached zero. Consequently, the capacities have been discharged and inverse voltage at the consumer has been avoided. 
       FIG. 22  shows a seventh embodiment of the invention-based circuit, in which the power I 2  is measured via a third resistor  35  which is connected in series with the second switch  24 , and the measuring signal is supplied to the second switch  24  via a suitable arrangement in the driver circuit  12  in such a way that said switch is again conductively controlled below a specific current value I 2  and thus the capacity of the parasitic capacitor  26  is discharged if the power I 2  has reached zero. A similar arrangement is also displayed with a fourth resistor  36 , which is connected in series with the third switch  25 . Thus no inverse voltage occurs at the consumer  10 . Instead of performing a current measurement by means of a resistor, it is also possible to use any other type of current measurement in order to conductively control again the second switch  24  and the third switch  25  below a specific current value I 2 . For example, the current measurement can also be performed by means of a current transformer. 
     The possibilities mentioned in the embodiments two to seven with regard to providing the consumer  10  with a protection against inverse voltage can also be applied to the first embodiment. 
     The present invention is not restricted to the embodiments shown. For example, it is possible to design one of the two switches  24 ,  25  as a switch with a separate load connected in parallel, and the other switch as a combined component consisting of switch and load. In particular, the load can comprise a resistor, a voltage-dependent resistor, a capacitor, a diode, a Zener diode, a suppressor diode, a semi-conductor with controlled avalanche behavior or a combination herefrom. 
     Furthermore, the present invention is not restricted to the embodiment in which the control system  2  is coupled with the ground  19 . Rather the provision of three potentially separately actuated switches generally allows for a low interference operation with short rise and fall times.