Abstract:
The present invention discloses an electrostatic discharge protection circuit, comprising a diode and a N-type metal-oxide-semiconductor (NMOS) transistor. The diode locating on a N-well comprises an high P-doping concentration region and an nonadjacent high N-doping concentration region. The NMOS transistor, locating on a P-well, comprises a drain, a source and a gate, and the drain and the source are formed by the high N-doping concentration region. Wherein the P-well further comprises a high P-doping concentration region near the source, the drain of the NMOS is electrically connected to the high N-doping concentration region of the diode, the source of the NMOS and the adjacent high P-doping concentration region are electrically connected to a ground, the gate of the NMOS transistor electrically connected to a trigger point. Accordingly, the electrostatic discharge protection circuit has a low parasitic capacitance, wide operating voltage range and high electrostatic discharge (ESD) capability for resolving the problems about the ESD of the RX pins.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an electrostatic discharge protection circuit, and in particular to an electrostatic discharge protection circuit using a silicon controlled rectifier (SCR), which provides a low stray capacitance, a low trigger voltage, a wide operating voltage range, and a high electrostatic discharge (ESD) capability. 
         [0003]    2. Background 
         [0004]    To avoid the damage of integrated circuit (IC) suffered from electrostatic discharge (ESD) during the processes of construction, production and operation, therefore, ESD protection circuit must be added on all connected path of bonding wire to conduct ESD current. 
         [0005]    In general, the protection circuit can be divided into: diode, metal oxide semiconductor (MOS) transistor, silicon controlled rectifier (SCR), etc. Wherein, the SCR exhibits the highest ESD capability under the same condition. However, the trigger voltage of conventional SCR was high to operate. For instance, Lateral SCR (LSCR) exhibits high ESD capability, but still did not be utilized frequently due to the high trigger voltage. 
         [0006]    In order to decrease the trigger voltage, modified circuits of SCR were presented frequently. U.S. Pat. No. 4,896,243 discloses a modified lateral SCR (MLSCR). U.S. Pat. No. 4,939,616 discloses a low voltage triggering SCR (LVTSCR). Mergens propose a dual triggered SCR as reference “Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides,” in IEEE int. Electron Devices Meeting (IEDM) Tech. Dig., Washington, D.C., 2003, pp.  21.3.1-21.3.4.    
         [0007]    In general, the total parasitic capacitance of connection pins between the circuit and ESD protection circuit must be smaller than 200 fF, or the high-speed transmission signal will be distorted by the delay of parasitic capacitances and cause poor circuit characteristics. For the design of high-speed transmission signal, MOS transistors are not suitable for ESD protection elements due to large parasitic capacitances. In addition, some researches proposed ESD protection elements based on small capacitances, such as H. Feng, K. Gong, and A. Z. Wang, “A comparison study of ESD protection for RFIC&#39;s: performance vs. parasitics,” in IEEE MTT-S int. Microwave Symp. Dig., Boston, Mass., 2000, pp. 143-146. C. Y. Lin and M. D. Ker, “Dual SCR with low-and-constant parasitic capacitance for ESD protection in 5-GHz RF intergrated circuits,” in IEEE in conf. Solid-State Integrated Circuit Tech. (ICSICT), Shanghai, 2010, pp. 707-709. M. H. Tsai , S. H. Hsu , F. L. Hsueh and C. P. Jou, “A multi-ESD-path low-noise amplifier with a 4.3-A TLP current level in 65-nm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 12, pp. 4004-4011, 2010. M. P. J. Mergens , C. C. Russ, K. G. Verhaege, J. Armer, P. C. Jozwiak, R. P. Mohn, B. Keppens, and C. S. Trinh, “Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 532-542, 2005. As above discussion, all these ESD protection circuits were formed based on SCR due to the high conducting capability of ESD current per unit area. Therefore, a compact layout size could be used to minimize parasitic capacitances with a basic ESD resistance. 
         [0008]      FIG. 1  shows fail circuit diagram for TC 9003F31 RX pin receiving terminal. The ESD structure protects upper circuit by a diode with high P doping concentration/N-well (P+/NW), and protects lower circuit by a diode with high N doping concentration/P-well (N+/PW). When the pins are bombarded by an operation of ESD PS-mode (i.e. PS-mode means that V SS  terminal connects with ground, a positive ESD voltage occurs at the pins and discharges the current of V SS  terminal. At this moment, V DD  terminal and the other pins are floating), in an ideal situation, the ESD current should flow through the upper P+/NW diode and be led to the ground by the power clamp circuit. In fact, when voltage (V 1 ) is higher than the threshold voltage of M 1  MOS transistor, and the M 1  MOS transistor will break down. Therefore, the ESD current flows through the lower circuit and burns M 1  MOS transistor.  FIG. 2  is the measured curve of the transmission line pulse (TLP). Moreover, M 1  MOS transistor is formed based on 55 nm process, which utilizes an operated voltage of 1.2V, leading to lower breakdown voltage of M 1  MOS transistor. 
         [0009]    In the ESD protection of the RF circuit, in addition to adjust the matching circuit (including the capacitor and the inductor), uses of diodes and SCR are better methods for ESD protection. However, diodes as the ESD protection circuit can merely provide forward ESD current protection, leading to diodes broken due to the voltage overflow. With the minimization of process, the breakdown voltage of the elements becomes small and the design difficulty thus increases. 
         [0010]    Furthermore, the RX pin has a swing signal, which will cause a carrier effect. Therefore, the trigger voltage must be higher. 
         [0011]    According to the disadvantage of the prior art, the inventors disclose an ESD protection circuit with a low capacitor, a wide operating voltage range, and a high ESD capability for resolving the problems about the ESD of the RX pins. 
       BRIEF SUMMARY OF THE INVENTION 
       [0012]    It is an objective of the present invention to provide an electrostatic discharge (ESD) protection circuit with a low capacitor, a wide operating voltage range, and a high electrostatic discharge capability for resolving the problems about the ESD of the RX pins. 
         [0013]    To achieve the above objective, the present invention provides an ESD protection circuit, formed by a diode and a metal-oxide-semiconductor (MOS) transistor set on a semiconducting substrate, comprising: a first well, having a first conducting mode; a second well, locating adjacent to the first well and having a second conducting mode; a first high doping concentration region, locating in the first well and having a second conducting mode, the first high doping concentration region electrically connected to a connected pad; a second high doping concentration region, locating in the first well and having a first predetermined distance from the first high doping concentration region, having a first conducting mode; a third high doping concentration region, locating in the first well and having a first conducting mode; a fourth high doping concentration region, locating in the second well and having a second predetermined distance from the third high doping concentration region, having a first conducting mode, the fourth high doping concentration region electrically connected to a ground pad; a fifth high doping concentration region, locating in the second well and locating adjacent to the fourth high doping concentration region, having a second conducting mode, the fifth high doping concentration region electrically the ground pad; and an electrode, locating on a surface of the second well between the third high doping concentration region and the fourth high doping concentration region, the electrode electrically connected to a trigger point; wherein the second high doping concentration region is electrically connected to the third high doping concentration region. 
         [0014]    According to the feature of the present invention, the first conducting mode is N-type, and the second conducting mode is P-type. 
         [0015]    According to the feature of the present invention, a parasitic effect between the first high doping concentration region, the first well and the second well forms a first bipolar transistor, the first high doping concentration region forms as a collector of the first bipolar transistor, the first well forms as a base of the first bipolar transistor, the second well forms as an emitter of the first bipolar transistor. 
         [0016]    According to the feature of the present invention, the second high doping concentration region and the third high doping concentration region are electrically connected to a point with high voltage. 
         [0017]    To achieve the above objective, the present invention provides an ESD protection circuit, comprising: a diode, locating on a N-well, including a high P-doping concentration region and a nonadjacent high N-doping concentration region; a N-type metal-oxide-semiconductor (NMOS) transistor, locating on a P-well, including a drain, a source and a gate, the drain and the source formed by the high N-doping concentration region; wherein the P-well further comprises a high P-doping concentration region adjacent to the source, the drain of the NMOS is electrically connected to the high N-doping concentration region of the diode, the source of the NMOS and the adjacent high P-doping concentration region are electrically connected to a ground, the gate of the NMOS transistor electrically connected to a trigger point. 
         [0018]    According to the feature of the present invention, the drain of the NMOS transistor and the high N-doping concentration region of the diode are electrically connected to a point with high voltage. 
         [0019]    According to the feature of the present invention, a parasitic effect between the high P-doping concentration region of the diode, the N-well, the P-well and the source of the NMOS transistor forms a SCR. 
         [0020]    To sum up the above arguments, the electrostatic discharge protection circuit according to the invention presents the advantages including of: 
         [0021]    Having a low parasitic capacitor for resolving the problems about the ESD of the RX pins. 
         [0022]    Having a wide operating voltage range and high electrostatic discharge (ESD) capability. 
         [0023]    These and many other advantages and features of the present invention will be readily apparent to those skilled in the art from the following drawings and detailed descriptions. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    All the objects, advantages, and novel features of the invention will become more apparent from the following detailed descriptions when taken in conjunction with the accompanying drawings. 
           [0025]      FIG. 1  shows a fail circuit diagram for TC 9003F31 RX pin receiving terminal; 
           [0026]      FIG. 2  the measured curve of the transmission line pulse (TLP); 
           [0027]      FIG. 3  shows a layout circuit of the ESD protection for a first embodiment of the present invention, wherein top part is top view and bottom part is cross section view; 
           [0028]      FIG. 4  shows (a) a parasitic SCR circuit diagram and (b) a circuit schematic of the ESD protection for the first embodiment of the present invention; 
           [0029]      FIG. 5  shows a schematic of a discharging path of the ESD protection circuit for the first embodiment of the present invention; 
           [0030]      FIG. 6  shows a layout circuit of the ESD protection for a second embodiment of the present invention, wherein top part is top view and bottom part is cross section view; 
           [0031]      FIG. 7  shows (a) a parasitic SCR circuit diagram and (b) a circuit schematic of the ESD protection for the second embodiment of the present invention; and 
           [0032]      FIG. 8  shows a schematic of a discharging path of the ESD protection circuit for the second embodiment of the present invention; 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0033]    Although the invention has been explained in relation to several preferred embodiments, the accompanying drawings and the following detailed descriptions are the preferred embodiment of the present invention. It is to be understood that the following disclosed descriptions will be examples of present invention, and will not limit the present invention into the drawings and the special embodiment. 
         [0034]      FIG. 3  shows a layout circuit of the electrostatic discharge (ESD) protection for a first embodiment of the present invention. Top part is top view and bottom part is cross section view. The ESD protection circuit  10  comprises a diode and a MOS transistor which is set on a semiconducting substrate. The ESD protection circuit  10  comprises: a first well  20 , a second well  30 , a first high doping concentration region  21 , a second high doping concentration region  22 , a third high doping concentration region  31 , a fourth high doping concentration region  32 , a fifth high doping concentration region  33 , an electrode  34 . The first well  20  has a first conducting mode. The second well  30  has a second conducting mode, and is located adjacent to the first well  20 . The first high doping concentration region  21  is located in the first well  20  and has a second conducting mode, and the first high doping concentration region  21  is electrically connected to a connected pad  41 . The second high doping concentration region  22  is located in the first well  21  and has a first conducting mode, and the second high doping concentration region  22  has a first predetermined distance from the first high doping concentration region  21 . The third high doping concentration region  31  is located in the second well  30  and has a first conducting mode. The fourth high doping concentration region  32  is located in the second well  30  and has a first conducting mode. The fourth high doping concentration region  32  has a second predetermined distance from the third high doping concentration region  32 , and is electrically connected to a ground pad  42 . The fifth high doping concentration region  33  is located in the second well  30  and has a second conducting mode. The fifth high doping concentration region  33  is located adjacent to the fourth high doping concentration region  32  and is electrically the ground pad  42 . The electrode  34  is located on a surface of the second well  30  between the third high doping concentration region  31  and the fourth high doping concentration region  32 , and the electrode  34  is electrically connected to a trigger point  35 . Wherein the second high doping concentration region  22  is electrically connected to the third high doping concentration region  32 . 
         [0035]      FIG. 4  shows (a) a parasitic SCR circuit diagram and (b) a circuit schematic of the ESD protection circuit for the first embodiment of the present invention.  FIG. 5  shows a schematic of a discharging path of the ESD protection circuit for the first embodiment of the present invention. A parasitic effect between the first high doping concentration region  21 , the first well  20  and the second well  30  forms a first bipolar transistor  51 , the first high doping concentration region  21  forms as a collector of the first bipolar transistor  51 , the first well  20  fauns as a base of the first bipolar transistor  51 , the second well  30  forms as an emitter of the first bipolar transistor  51 . 
         [0036]    A parasitic effect between the fourth high doping concentration region  33 , the first well  20  and the second well  30  forms a second bipolar transistor  52 , the fourth high doping concentration region  33  forms as a collector of the second bipolar transistor  52 , the second well  30  forms as a base of the second bipolar transistor  52 , the first well  20  formed as an emitter of the second bipolar transistor  52 . 
         [0037]    According to the above description, a parasitic effect between the first high doping concentration region  21 , the fourth high doping concentration region  32 , the first well  20  and the second well  30  forms a silicon controlled rectifier (SCR)  11 . 
         [0038]    Furthermore, an isolating layer having a thickness is located between the electrode  34  and the surface of the second well  34 . The third high doping concentration region  31 , the fourth high doping concentration region  32  and the electrode  34  forms as a metal-oxide-semiconductor (MOS) field-effect transistor (FET), the electrode  34  forms as a gate of the FET. It is also noted the FET is a metal-oxide-semiconductor (MOS) FET. The fifth high doping concentration region  33  is located closer to the junction of the first well  20  and the second well  30 , the fourth high doping concentration region  32  located farther to the junction of the first well  20  and the second well  30 , the fifth high doping concentration region  33  is used to adjust a trigger voltage of the trigger point  35 . 
         [0039]    In a prefer embodiment, the first conducting mode is N-type, and the second conducting mode is P-type. Namely, the ESD protection circuit  10  can be regarded as an ESD protection structure which consists of a P+/NW diode and a NMOS transistor. A parasitic SCR between the two elements is used as the main path for the discharge of ESD current. 
         [0040]    Namely, the P+/NW diode, locating on a N-well, includes an high P-doping concentration region and an nonadjacent high N-doping concentration region. 
         [0041]    The N-type metal-oxide-semiconductor (NMOS) transistor, locating on a P-well, includes a drain, a source and a gate. The drain and the source are formed by the high N-doping concentration region. 
         [0042]    The P-well further includes a high P-doping concentration region near the source, the drain of the NMOS is electrically connected to the high N-doping concentration region of the diode, and the source of the NMOS and the adjacent high P-doping concentration region are electrically connected to a ground, and the gate of the NMOS transistor is electrically connected to a trigger point. 
         [0043]    As shown in  FIG. 5 , the parasitic effect between the high P-doping concentration region of the diode, the N-well, the P-well and the source of the NMOS transistor forms a SCR  11 . 
         [0044]    A parasitic effect between the high P-doping concentration region of the diode, the N-well and the P-well forms a first bipolar transistor, and the N-well forms as a base of the first bipolar transistor. A parasitic effect between the source of the NMOS transistor, the N-well and the P-well forms a second bipolar transistor, and the P-well forms as a base of the second bipolar transistor, and the first bipolar transistor and the second bipolar transistor form as a SCR  11 . 
         [0045]    Wherein, the high P-doping concentration region of the P+/NW diode is electrically connected to the connected pad  41 , and N+pin connects with the drain of the NMOS transistor, and the source and bulk of the NMOS transistor connect to the ground, and the poly gate of the electrode  34  connects to the trigger point  35 . 
         [0046]      FIG. 5  shows a schematic of a discharging path of the ESD protection circuit for the first embodiment of the present invention. When the integrated circuit is operated in general, the trigger point  35  decreases it voltage. Therefore, the NMOS transistor will turn off and eliminate the leakage current. 
         [0047]    When the integrated circuit is bombarded by the ESD, the trigger point  35  increase it voltage. Therefore, the NMOS transistor will turn on and drive the leakage current through the first parasitic bipolar transistor  51  (PNP), and passing through the channel of the NMOS transistor to the ground pad  42 . Due to the current of the first parasitic bipolar transistor  51  (PNP), a voltage is created at the base of the second bipolar transistor  52  (NPN). Therefore, the second parasitic bipolar transistor  51  (NPN) turns on, and driving most ESD current to the ground pad  42  through the SCR path. The trigger point  35  can be set up by a signal of a power clamp  60  instead of additional trigger circuits, as shown in  FIG. 5 . The Power clamp  60  is mainly connected between the high voltage terminal  43  (VDD) and the ground pad  42 , which consists of capacitors (or the parasitic capacitors), resistors and transistors. When the high voltage terminal  43  exhibits a large offset and creates a leakage current, the leakage current can be derived to the power clamp circuit and then charge the capacitors. When the voltage becomes stable, the resistors can be used to discharge the capacitors. 
         [0048]      FIG. 6  shows a layout circuit of the electrostatic discharge (ESD) protection for a second embodiment of the present invention. Top part is top view and bottom part is cross section view.  FIG. 7  shows (a) a parasitic SCR circuit diagram and (b) a circuit schematic of the ESD protection for the second embodiment of the present invention. The circuit structure of the second embodiment of the present invention is similar to the circuit structure of the first embodiment of the present invention. The diversity between the first embodiment and the second embodiment is that the high N-doping concentration region of the P+/NW diode is electrically connected to the drain of the NMOS transistor and the voltage terminal  43  (VDD) simultaneously. Namely, both of the second high doping concentration region  22  and the third high doping concentration region  31  are electrically connected to a high voltage terminal  43 . Therefore, an ESD protection is pulled up, and a SCR is used as the protection element resulted from the parasitic effect between the connected pad  41  and the ground pad  42 . In addition, a low parasitic capacitance is obtained according to a comparison with another embodiment. 
         [0049]      FIG. 8  shows a schematic of a discharging path of the ESD protection circuit for the second embodiment of the present invention. When the integrated circuit is operated in general, the trigger point  35  decreases it voltage. Therefore, the NMOS transistor will turn off and eliminate the leakage current. 
         [0050]    When the integrated circuit is bombarded by the PD mode ESD, the current can be derived based on a forward biasing path of the P+/NW diode. When the integrated circuit is bombarded by the PS mode ESD, the current can be derived based on two paths. For the first path, the current is derived to the high voltage terminal  43  through the P+/NW diode, and then passes the power clamp  60  into the ground pad  42 . For the second path, the power clamp  60  is used to create a trigger signal to the trigger point  35 , and turns on the parasitic SCR  11  for the demand of driving the current. When the integrated circuit is bombarded by the ND and NS mode ESD, the current can be derived based on the power clamp  60  and the parasitic diode of the NMOS transistor. 
         [0051]    Wherein, PS-mode means that low voltage terminal V SS  connects with ground, a positive ESD voltage occurs at the pins and discharges the current to the low voltage terminal V SS . At this moment, the high voltage terminal V DD  terminal and the other pins are floating. 
         [0052]    NS-mode means that low voltage terminal V SS  connects with ground, a negative ESD voltage occurs at the pins and discharges current to the low voltage terminal V SS . At this moment, the high voltage terminal V DD  terminal and the other pins are floating. 
         [0053]    PD-mode means that high voltage terminal V DD  connects with ground, a positive ESD voltage occurs at the pins and discharges current to the high voltage terminal V DD . At this moment, the low voltage terminal V SS  terminal and the other pins are floating. 
         [0054]    ND-mode means that high voltage terminal V DD  connects with ground, a negative ESD voltage occurs at the pins and discharges current to the high voltage terminal V DD . At this moment, the low voltage terminal V SS  terminal and the other pins are floating. 
         [0055]    The present invention satisfies the requirement of low capacitances for RF ESD protection. In addition, the low SCR trigger voltage and the improved tolerance of the voltage operation is accomplished. Namely, the leakage current is eliminated effectively during the operation. 
         [0056]    Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.