Abstract:
A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film.

Description:
The entire disclosure of Japanese Patent Application No. 2007-068961, filed Mar. 16, 2007 is expressly incorporated by reference herein. 
     BACKGROUND 
     1. Technical Field 
     The present invention relates to a method for manufacturing a semiconductor device and to a semiconductor device in which an element isolation film is embedded in a silicon substrate. In particular, the invention relates to a method for manufacturing a semiconductor device and to a semiconductor device which, in the etching process of a silicon oxide film subsequent to formation of an element isolation film, can suppress a surface of the element isolation film from being etched. 
     2. Related Art 
       FIGS. 7A to 7C  and  8 A are sectional views for explaining a related method for manufacturing a semiconductor device.  FIG. 8B  is a sectional view of the semiconductor device taken along plane A-A′ in the state as shown in  FIG. 8A . The semiconductor device manufactured according to the method shown by these diagrams has a first transistor located in a first element region  100   c  and a second transistor located in a second element region  100   d.  A gate insulating film  103   d  of the second transistor is thicker than a gate insulating film  103   c  of the first transistor. 
     First, as shown in  FIG. 7A , a groove is formed in a silicon substrate  100 . Next, a thermally-oxidized film  102   a  is formed on the side surface and the bottom surface of the groove. Further, an element isolation film  102  is embedded in the groove. The element isolation film  102  is a silicon oxide film which is formed by vapor-phase synthesis method. The element isolation film  102  separates the first element region  100   c  and the second element region  100   d  respectively from other regions. Next, the silicon substrate  100  is thermally oxidized. As a result of this, the gate insulating film  103   d  is formed in a second element region  100   d,  and a thermally-oxidized film  103   a  is formed in the first element region. In the state as shown in this diagram, the gate insulating film  103   d  does not have the necessary thickness. 
     Next, as shown in  FIG. 7B , a resist film  150  is formed on and around the silicon substrate  100  located in the second element region, and wet etching is performed using the resist film  150  as a mask. As a result of this, the thermally-oxidized film  103   a  is removed. In this process, the surface of the element isolation film  2  located around the first element region is etched, and a concave section  102   b  is formed in the silicon substrate  100  located around the first element region (see JP-A-2002-9144 (sixth paragraph) is an example of related art). 
     Subsequently, as shown in  FIG. 7C , the resist film  150  is removed. Next, the silicon substrate  100  is thermally oxidized. As a result of this, the gate insulating film  103   c  is formed in the first element region, and the thickness of the gate insulating film  103   d  increases to the necessary thickness. 
     Next, as shown in each of  FIGS. 8A and 8B , a gate electrode  104   c,  a side wall  105   c,  a low-concentration impurity region  106   c  and an impurity region  107   c  which serves as source and drain of the first transistor are formed. At the same time, a gate electrode  104   d,  a side wall  105   d,  a low-concentration impurity region  106   d,  and an impurity region  107   d  which will serve as source and drain of the second transistor are formed. 
     As described in the example of related art, the concave section  102   b  is formed in the first element region. Accordingly, a section located on the concave section  102   b  is thinner compared to other sections in the gate insulating film  103   c  of the first transistor. As a result, a threshold voltage of the first transistor drops in the section located on the concave section  102   b.    
     In the case of a structure in which an element isolation film is embedded in a semiconductor substrate as described above, when the surface of the element isolation film is etched in the etching process of a silicon oxide film which is performed subsequent to formation of the element isolation film, a concave section located around the element isolation film is formed in the semiconductor substrate. Accordingly, a threshold voltage of a transistor drops in the section located on the concave section. 
     SUMMARY 
     An advantage of the invention is to provide a method for manufacturing a semiconductor device, which, in the etching process of a silicon oxide film subsequent to formation of an element isolation film, can suppress the surface of the element isolation film from being etched. 
     According to a first aspect of the invention, a method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film. 
     According to the first aspect of the invention, the oxidized silicon nitride film is formed on the surface of the element isolation film. Accordingly, in the etching process of a silicon oxide film subsequent to formation of the element isolation film, the method can suppress the surface of the element isolation film from being etched. 
     In this case, in embedding the element isolation film, a first element region in which a first transistor is formed and a second element region in which a second transistor having a higher drive voltage than the first transistor is formed may be separated from each other. The method may further include subsequent to removing the silicon nitride film: forming a gate insulating film of the second transistor on the silicon substrate located in the second element region and forming a thermally-oxidized film on the silicon substrate located in the first element region through thermal oxidation of the surface of the silicon substrate; removing the thermally-oxidized film by wet etching; and increasing the thickness of the gate insulating film of the second transistor located in the second element region and forming a gate insulating film of the first transistor on the silicon substrate located in the first element region, through thermal oxidation of the surface of the silicon substrate. 
     A method for manufacturing a semiconductor device according to a second aspect of the invention includes: forming a groove in a silicon substrate and embedding an element isolation film made of a silicon oxide film formed by a vapor-phase synthesis method in the groove; forming a thermally-oxidized film on the surface of the silicon substrate; forming a silicon nitride film on the thermally-oxidized film and on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film. 
     In this case, in embedding the element isolation film, a first element region in which a first transistor is formed and a second element region in which a second transistor having a higher drive voltage than the first transistor is formed may be separated from each other. The method may further include: subsequent to removing the silicon nitride film, removing the thermally-oxidized film; forming a gate insulating film of the second transistor on the silicon substrate located in the second element region and forming a second thermally-oxidized film on the silicon substrate located in the first element region through thermal oxidation of the surface of the silicon substrate; removing the second thermally-oxidized film by wet etching; and increasing the thickness of the gate insulating film of the second transistor located in the second element region and forming a gate insulating film of the first transistor on the silicon substrate located in the first element region, through thermal oxidation of the surface of the silicon substrate. 
     A method for manufacturing a semiconductor device according to a third aspect of the invention includes: separating a first element region in which a MONOS nonvolatile memory is formed from other regions, by forming a groove in a silicon substrate and embedding an element isolation film made of a silicon oxide film formed by vapor-phase synthesis method in the groove; forming a thermally-oxidized film on the surface of the silicon substrate; forming a silicon nitride film and a second silicon oxide film on the thermally-oxidized film and on the element isolation film in this order; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and forming a storage section of the MONOS nonvolatile memory in the first element region, by removing the silicon nitride film and the second silicon oxide film which are located on the element isolation film and by selectively removing a laminated film consisting of the thermally-oxidized film, the silicon nitride film and the second silicon oxide film which are located on the silicon substrate. 
     In this case, in embedding the element isolation film, a second element region in which a first transistor is formed and a third element region in which a second transistor having a higher drive voltage than the first transistor is formed may be respectively separated from other regions. In this case, the method may further include, subsequent to removing the silicon nitride film: forming a gate insulating film of the second transistor on the silicon substrate located in the third element region and forming a second thermally-oxidized film on the silicon substrate located in the second element region through thermal oxidation of the surface of the silicon substrate; forming a mask film on the storage section; removing the second thermally-oxidized film by wet etching using the mask film as mask; removing the mask film; and increasing the thickness of the gate insulating film of the second transistor and forming a gate insulating film of the first transistor on the silicon substrate located in the second element region, through thermal oxidation of the surface of the silicon substrate. 
     In this case, the method may further include: between embedding the element isolation film and forming the silicon nitride film, thermal treating the element isolation film in an atmosphere containing ammonium. 
     A semiconductor device according to a fourth aspect of the invention includes: an element isolation film which is embedded in a silicon substrate and which separates an element region from other regions; and a transistor which is formed in the element region. The element isolation film includes a silicon oxide film and an oxidized silicon nitride film located on the surface of the silicon oxide film, and the oxidized silicon nitride film has the highest nitrogen concentration on the surface thereof. 
     A semiconductor device according to a fifth aspect of the invention includes: an element isolation film which is embedded in a silicon substrate and which separates a first element region and a second element region respectively from other regions; a first transistor which is formed in the first element region; and a second transistor which is formed in the second element region and which has a thicker gate insulating film than the first transistor. The element isolation film includes a silicon oxide film and an oxidized silicon nitride film located on the surface of the silicon oxide film, and the oxidized silicon nitride film has the highest nitrogen concentration on the surface thereof. 
     A semiconductor device according to a sixth aspect of the invention includes: an element isolation film which is embedded in a silicon substrate and which separates a first element region, a second element region and a third element region respectively from other regions; a MONOS nonvolatile memory which is formed in the first element region; a first transistor which is formed in the second element region; and a second transistor which is formed in the third element region and which has a thicker gate insulating film than the first transistor. The element isolation film includes a silicon oxide film and an oxidized silicon nitride film located on the surface of the silicon oxide film, and the oxidized silicon nitride film has the highest nitrogen concentration on the surface thereof. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements. 
         FIGS. 1A to 1D  are sectional views for explaining a method for manufacturing a semiconductor device according to a first embodiment. 
         FIG. 2A  is a sectional view for explaining the process subsequent to the processes of  FIG. 1 , and  FIG. 2B  is a sectional view of the semiconductor device shown in  FIG. 2A  cut along plane A-A′. 
         FIGS. 3A to 3D  are sectional views for explaining a method for manufacturing a semiconductor device according to a second embodiment. 
         FIGS. 4A to 4C  are sectional views for explaining a method for manufacturing a semiconductor device according to a third embodiment. 
         FIGS. 5A and 5B  are sectional views for explaining the process subsequent to the processes of  FIG. 4 . 
         FIGS. 6A to 6C  are sectional views for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. 
         FIGS. 7A to 7C  are sectional views for explaining a method for manufacturing a semiconductor device according to a related art. 
         FIG. 8A  is a sectional view for explaining the process subsequent to the processes of  FIG. 7 , and  FIG. 8B  is a sectional view of the semiconductor device shown in  FIG. 8A  cut along plane A-A′. 
     
    
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Embodiments of the invention will now be described with reference to the drawings.  FIGS. 1A to 1D  and  FIG. 2A  are sectional views for explaining a method for manufacturing a semiconductor device according to a first embodiment of the invention.  FIG. 2B  is a sectional view of the semiconductor device in the state as shown in  FIG. 2A  cut along plane A-A′. In the semiconductor device manufactured by the present embodiment, a silicon oxynitride layer is formed on the surface of each element isolation film  2  embedded in a silicon substrate  1 . 
     First, as shown in  FIG. 1A , a pad oxide film  10  is formed on the silicon substrate  1  by thermal oxidation method. Next, a silicon nitride film  11  is formed on the pad oxide film  10 . Next, a resist pattern (which is not shown) is formed on the silicon nitride film  11 , and the silicon nitride film  11  is etched using the resist pattern as mask. As a result of this, an opening pattern is formed on the silicon nitride film  11 . Subsequently, the resist pattern is removed. 
     Next, the pad oxide film  10  is etched using the silicon nitride film  11  as mask. Further the silicon substrate  1  is etched using the silicon nitride film  11  as mask. As a result of this, a groove l a  is formed in the silicon substrate  1 . Next, the silicon substrate  1  is selectively thermally oxidized using the silicon nitride film  11  as mask. As a result of this, a thermally-oxidized film  2   a  is formed in the bottom surface and the side wall of the groove  1   a.    
     Next, as shown in  FIG. 1B , a silicon oxide film is formed in the groove  1   a  and on the silicon nitride film  11  by CVD method. Next, the silicon oxide film located on the silicon nitride film  11  is removed by CMP method. As a result of this, the element isolation film  2  is embedded in the groove l a,  and an element region  1   b  in which a transistor is formed is separated from other regions. Subsequently, the silicon nitride film  11  and the pad oxide film  10  are removed by wet etching. 
     Next, as shown in  FIG. 1C , a silicon nitride film  12  is formed on the silicon substrate  1  and on the element isolation film  2  by CVD method. The thickness of the silicon nitride film  12  is, for example, not smaller than 2 nm and not greater than 10 nm. 
     Next, as shown in  FIG. 1D , the silicon nitride film  12 , the element isolation film  2  and the silicon substrate  1  are thermally treated in nitrogen atmosphere or in oxidizing atmosphere. The thermal treatment temperature at this time is not lower than 650° C. and not higher than 900° C. As a result of this, a part of nitrogen contained in the silicon nitride film  12  diffuses and penetrates into the surface of the element isolation film  2 , and a silicon oxynitride layer  2   b  (oxidized silicon nitride film) is formed on the surface of the element isolation film  2 . The nitrogen concentration is the highest on the surface of the silicon oxynitride layer  2   b,  and the concentration is lower in the center thereof. Since the diffusion speed of nitrogen in the silicon substrate  1  is lower than the diffusion spend of nitrogen in the element isolation film  2  formed by vapor-phase synthesis method, a nitrided layer is not formed on the surface of the silicon substrate  1 . 
     Subsequently, as shown in  FIGS. 2A and 2B , the silicon nitride film  12  and the pad oxide film  10  are removed. Next, a sacrificial oxide layer (which is not shown) is formed through thermal oxidation of the silicon substrate  1  located in the element region  1   b,  and the sacrificial oxide layer is removed by wet etching. As described above, since the silicon oxynitride layer  2   b  is formed on the surface of the element isolation film  2 , the surface of the element isolation film  2  is suppressed from being etched in the process of removing the sacrificial oxide layer. Accordingly, formation of a concave section in the silicon substrate located around the element isolation film  2  is suppressed. 
     Next, a gate insulating film  3  is formed through thermal oxidation of the silicon substrate  1  located in the element region  1   b.  Next, a polysilicon film is formed on the gate insulating film  3  and on the element isolation film  2 , and the polysilicon film is selectively removed. As a result of this, a gate electrode  4  located on the gate insulating film  3  is formed. Next, an impurity is introduced into the silicon substrate  1  using the gate electrode  4  and the element isolation film  2  as mask. As a result of this, a low-concentration impurity region  6  is formed on the silicon substrate  1  located in the element region  1   b.  Next, an insulating film is formed on the entire surface including on the gate electrode  4 , and the insulating film is etched back. As a result of this, a side wall  5  is formed on the side wall of the gate electrode  4 . Next, an impurity is introduced into the silicon substrate  1  using the side wall  5 , the gate electrode  4  and the element isolation film  2  as mask. As a result of this, an impurity region  7  which will serve as source and drain is formed on the silicon substrate  1  located in the element region  1   b.    
     In this way, a transistor is formed on the silicon substrate  1 . 
     According to the first embodiment of the invention as described above, the silicon oxynitride layer  2   b  is formed on the surface of the element isolation film  2  through formation of the silicon nitride film  11  on the element isolation film  2  and diffusion of nitrogen from the silicon nitride film  11  to the surface of the element isolation film  2 . Accordingly, the surface of the element isolation film  2  is suppressed from being etched in the process of wet etching the silicon oxide film which is performed subsequent to formation of the element isolation film  2  (for example, in the process of removing the sacrificial oxide layer formed on the silicon substrate  1  by wet etching). As a result, formation of a concave section in the silicon substrate located around the element isolation film  2  is suppressed, and a threshold voltage of the transistor is suppressed from dropping in the section located in the vicinity of the element isolation film  2 . 
     Alternatively, a method of forming a silicon oxynitride layer on the surface of the element isolation film  2  through ion implantation is also conceivable. The nitrogen concentration is the highest in a rather internal section of the silicon oxynitride layer which is formed according to this method. Accordingly) the surface of the silicon oxynitride layer is etched in the process of etching the silicon oxide film. On the other hand, the nitrogen concentration is the highest on the surface of the silicon oxynitride layer  2   b  which is manufactured by the embodiment. Accordingly, in the process of etching the silicon oxide film, the surface of the silicon oxynitride layer  2   b  is suppressed from being etched. 
       FIGS. 3A to 3C  are sectional views for explaining a method for manufacturing a semiconductor device according to a second embodiment of the invention. Hereinafter, identical numerals as those of the first embodiment will be used for structures identical to those of the first embodiment, and the explanation thereof will be omitted. 
     First, as shown in  FIG. 3A , a groove l a  and a thermally-oxidized film  2   a  are formed on a silicon substrate  1 , and an element isolation film  2  is embedded in the groove  1   a.  These processes are the same as those of the first embodiment. Next, the silicon nitride film  11  and the pad oxide film  10  shown in  FIG. 1  are removed, and subsequently the silicon substrate  1  is thermally oxidized. The thermal treatment temperature at this time is not lower than 650° C. As a result of this, a pad oxide film  13  is formed on the silicon substrate  1  located in the element region  1   b.  The thickness of the pad oxide film  13  is, for example, not less than 1 nm and not more than 5 nm. 
     Next, as shown in  FIG. 3B , a silicon nitride film  12  is formed on the element isolation film  2  and on the pad oxide film  13 . Further, a silicon oxynitride layer  2   b  is formed. The methods of forming the silicon nitride film  12  and the silicon oxynitride layer  2   b  are the same as those of the first embodiment. Since the diffusion speed of nitrogen in the pad oxide film  13  which serves as the thermally-oxidized film is lower than the diffusion speed of nitrogen in the element isolation film  2  formed by vapor-phase synthesis method, a nitrided layer is not formed on the surface of the silicon substrate  1 . 
     Next, as shown in  FIG. 3C , the silicon nitride film  12  and the pad oxide film  13  are removed by wet etching. Since the silicon oxynitride layer  2   b  is formed on the surface of the element isolation film  2 , the surface of the element isolation film  2  can be suppressed from being etched in the process of removing the pad oxide film  13 . 
     Next, as shown in  FIG. 3D , a gate insulating film  3 , a gate electrode  4 , a side wall  5 , a low-concentration impurity region  6  and an impurity region  7  are formed, The methods of forming these are the same as those of the first embodiment. 
     As described above, the present embodiment can provide the same advantageous effects as the first embodiment. Furthermore, since the pad oxide film  13  is formed between the silicon nitride film  12  and the silicon substrate  1 , stress acting on the silicon nitride film  12  can be reduced. 
       FIGS. 4A to 4C  and  FIGS. 5A and 5B  are sectional views for explaining a method for manufacturing a semiconductor device according to a third embodiment of the invention. The semiconductor device manufactured by the present embodiment has a first transistor in a first element region  1   c  and has a second transistor in a second element region  1   d.  The drive voltage of the second transistor is higher than the drive voltage of the first transistor. Accordingly, a gate insulating film  3   d  of the second transistor is thicker than a gate insulating film  3   c  of the first transistor. Hereinafter, identical numerals as those of the first embodiment will be used for structures identical to those of the first embodiment, and the explanation thereof will be omitted. 
     First, as shown in  FIG. 1A , a groove  1   a  and a thermally-oxidized film  2   a  are formed on a silicon substrate  1 , and an element isolation film  2  is embedded in the groove  1   a.  The methods of forming these are the same as those of the first embodiment. In the present embodiment, the element isolation film  2  separates a first element region  1   c  and ae second element region  1   d  respectively from other regions. Next, a silicon nitride film  12  is formed on the element isolation film  2  and on the silicon substrate  1 . Further a silicon oxynitride layer  2   b  is formed on the surface of the element isolation film  2 . The methods of forming these are the same as those of the first embodiment. 
     Subsequently, as shown in  FIG. 4B , the silicon nitride film  12  is removed. Next, a sacrificial oxide layer (which is not shown) is formed through thermal oxidation of the silicon substrate  1 , and the sacrificial oxide layer is removed by wet etching. As described above, since the silicon oxynitride layer  2   b  is formed on the surface of the element isolation film  2 , formation of a concave section in the silicon substrate located around the element isolation film  2  is suppressed. 
     Next, the silicon substrate  1  is thermally oxidized. As a result of this, the gate insulating film  3   d  of the second transistor is formed on the silicon substrate  1  located in the second element region  1   d,  and a thermally-oxidized film  3   a  is formed on the silicon substrate  1  located in the first element region  1   c.  The gate insulating film  3   d  does not have the necessary thickness in the state as shown in this diagram. 
     Next, as shown in  FIG. 4C , a resist film  50  is formed on the entire surface of the second element region  1   d.  Next, the silicon oxide film is wet etched using the resist film  50  as mask. As a result of this, the thermally-oxidized film  3   a  located in the first element region  1   c  is removed. As described above, the silicon oxynitride layer  2   b  is formed on the surface of the element isolation film  2 . Accordingly, the surface of the element isolation film  2  located around the first element region  1   c  is suppressed from being etched in the present process. As a result, formation of a concave section in the silicon substrate located around the element isolation film  2  is suppressed in the first element region  1   c,  and a threshold voltage of the first transistor is suppressed from dropping in a section located in the vicinity of the element isolation film  2 . 
     Subsequently, as shown in  FIG. 5A , the resist film  50  is removed. Next, the silicon substrate  1  is thermally oxidized. As a result of this, the gate insulating film  3   c  is formed on the silicon substrate  1  located in the first element region  1   c,  and the thickness of the second element region  1   d  located in the gate insulating film  3   d  increases to the necessary thickness. 
     Next, as shown in  FIG. 5B , a polysilicon film is formed on the entire surface including on the gate insulating films  3   c,    3   d  and on the element isolation film  2 , and then the polysilicon film is selectively removed. As a result of this, a gate electrode  4   c  located on the gate insulating film  3   c  and a gate electrode  4   d  located on the gate insulating film  3   d  are formed. Next, an impurity is introduced into the silicon substrate  1  using the gate electrodes  4   c,    4   d  and the element isolation film  2  as mask. As a result of this, a low-concentration impurity region  6   c  is formed on the silicon substrate  1  located in the first element region  1   c,  and a low-concentration impurity region  6   d  is formed on the silicon substrate  1  located in the second element region  1   d.  Next, an insulating film is formed on the entire surface including on the gate electrodes  4   c,    4   d,  and then the insulating film is etched back. As a result of this, side walls  5   c,    5   d  are respectively formed on the side walls of the gate electrodes  4   c,    4   d.  Next, an impurity is introduced into the silicon substrate  1  using the side walls  5   c,    5   d,  the gate electrodes  4   c,    4   d  and the element isolation film  2  as mask. As a result of this, a impurity region  7   c  which will serve as source and drain of the first transistor is formed on the silicon substrate  1  located in the first element region  1   c,  and an impurity region  7   d  which will serve as source and drain of the second transistor is formed on the silicon substrate  1  located in the second element region  1   d.    
     In this way, the first and second transistors are formed on the silicon substrate  1 . 
     According to the third embodiment of the invention as described above, the silicon oxynitride layer  2   b  is formed on the surface of the element isolation film  2 . Accordingly, the surface of the element isolation film  2  located around the first element region  1   c  is suppressed from being etched in the process of removing the sacrificial oxide layer. In addition, the surface of the element isolation film  2  located around the first element region  1   c  is suppressed from being etched also in the process of removing the thermally-oxidized film  3   a.  As a result, formation of a concave section on the silicon substrate  1  located around the element isolation film  2  is suppressed in the first element region  1   c.  Therefore, the threshold voltage of the first transistor is suppressed from dropping in the section located in the vicinity of the element isolation film  2 . 
     In the present embodiment, as is the case with the second embodiment, the silicon oxynitride layer  2   b  may be formed using a pad oxide film  13  (as shown in  FIG. 3 ). 
       FIGS. 6A to 6C  are sectional views for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the invention. The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment has a similar structure as the semiconductor device manufactured by the third embodiment, except that the semiconductor device has a MONOS nonvolatile memory in a third element region  1   e.  Hereinafter, identical numerals will be used for structures identical to those of the third embodiment, and the explanation thereof will be omitted. 
     First, as shown in  FIG. 6A , a groove l a  and a thermally-oxidized film  2   a  are formed on a silicon substrate  1 , and an element isolation film  2  is embedded in the groove  1   a.  The methods of forming these are the same as those of the first embodiment. In the present embodiment, the element isolation film  2  separates a first element region  1   c,  a second element region  1   d  and the third element region  1   e,  respectively, from other regions. 
     Next, a thermally-oxidized film  21  is formed through thermal oxidization of the silicon substrate  1 . Next, a silicon nitride film  22  and a silicon oxide film  23  are laminated in this order on the element isolation film  2  and on the thermally-oxidized film  21  by CVD method. The thickness of the thermally-oxidized film  21  is, for example, not less than 1 nm and not more than 5 nm. Thickness of both the silicon nitride film  22  and the silicon oxide film  23  is, for example, not less than 2 nm and not more than 10 nm. 
     Next, the silicon substrate  1 , the element isolation film  2 , the thermally-oxidized film  21 , the silicon nitride film  22  and the silicon oxide film  23  are thermally treated. As a result of this, nitrogen contained in the silicon nitride film  22  diffuses into a superficial surface of the element isolation film  2 , and a silicon oxynitride layer  2   b  is formed on the surface of the element isolation film  2 . Since the diffusion speed of nitrogen in the thermally-oxidized film  21  is lower than the diffusion speed of nitrogen in the element isolation film  2  formed by vapor-phase synthesis method, a nitrided layer is not formed on the surface of the silicon substrate  1 . 
     Next, as shown in  FIG. 6B , a resist pattern (which is not shown) is formed on the silicon oxide film  23 , and the silicon oxide film  23 , the silicon nitride film  22  and the thermally-oxidized film  21  are etched in this order using the resist pattern as mask. As a result of this, the silicon oxide film  23 , the silicon nitride film  22  and the thermally-oxidized film  21  are removed except the section which serves as a storage section  24  of the MONOS nonvolatile memory. Subsequently, the resist pattern is removed. 
     Next, as shown in  FIG. 6C , a gate insulating film  3   c  of a first transistor and a gate insulating film  3   d  of a second transistor are formed. The methods of forming these are the same as those of the third embodiment. Furthermore, as is the case with the third embodiment, formation of a concave section on the silicon substrate located  1  around the element isolation film  2  is suppressed in the first element region  1   c.  In addition, a threshold voltage of the first transistor is suppressed from dropping in the section located in the vicinity of the element isolation film  2 . In this process, a thermally-oxidized film (which is not shown) is formed also in a region of the silicon substrate  1  located in the third element region  1   e  in which the storage section  24  of the MONOS nonvolatile memory is not formed. 
     Next, the gate insulating films  3   c,    3   d  are formed. The methods of forming these are the same as those of the third embodiment. Next, a resist film (which is not shown) is formed on the third element region  1   e  and on the element isolation film  2  located around it. Next, an impurity is introduced into the silicon substrate  1  using the resist film, the gate electrodes  4   c,    4   d  and the element isolation film  2  as mask. As a result of this, a low-concentration impurity region  6   c  is formed on the silicon substrate  1  located in the first element region  1   c,  and a low-concentration impurity region  6   d  is formed on the silicon substrate  1  located in the second element region  1   d.  Subsequently, the resist film is removed. 
     Next, a resist film (which is not shown) is formed on the first element region  1   c,  on the second element region  1   d,  and on the element isolation film  2  located around them. Next, an impurity is introduced into the silicon substrate  1  using the resist film and the storage section  24  as mask. As a result of this, a low-concentration impurity region  6   e  is formed on the silicon substrate  1  located in the third element region  1   e.  Subsequently, the resist film is removed. 
     Next, an insulating film is formed on the entire surface including on the gate electrodes  4   c,    4   d,  and on the storage section  24 , respectively, and then the insulating film is etched back. As a result of this, side walls  5   c,    5   d,    5   e  are respectively formed on the side walls of the gate electrodes  4   c,    4   d  and of the storage section  24 . In this process, the thermally-oxidized film formed in the third element region  1   e  is removed. 
     Next, an impurity is introduced into the silicon substrate  1  using the side walls  5   c,    5   d,    5   e,  the gate electrodes  4   c,    4   d,  the storage section  24  and the element isolation film  2  as mask. As a result of this, impurity regions  7   c,    7   d  are formed. In addition, an impurity region  7   e  which will serve as source and drain of the MONOS nonvolatile memory is formed on the silicon substrate  1  located in the third element region  1   e.    
     In this way, the first and the second transistors and the MONOS nonvolatile memory are formed on the silicon substrate  1 . 
     The present embodiment can also provide the same advantageous effects as the third embodiment. Furthermore, since the silicon oxynitride layer  2   b  is formed using the silicon nitride film  23  which will serve as the storage section  24  of the MONOS nonvolatile memory, there is no need to form a silicon nitride film only for the purpose of forming the silicon oxynitride layer  2   b.  Therefore, increase in the number of the processes can be suppressed. 
     The invention is not limited to the embodiments as described above, and various modifications are possible within the scope of the summary of the invention. For example, in each of the embodiments as described above, the invention may have a process of thermally treating the element isolation film  2  in an atmosphere containing ammonium after the element isolation film  2  is formed and before the silicon nitride films  12 ,  22  are formed on the element isolation film  2 . The thermal treatment temperature is, for example, not lower than 600° C. and not higher than 700° C. Such modification nitrides the surface of the element isolation film  2 , which facilitate permeation of nitrogen from the silicon nitride films  12 ,  22 .