Abstract:
A reference signal generator circuit for an analog-to-digital converter, the circuit having a signal-generation stage to generate a first reference signal on a first reference terminal, and a filtering circuit arranged between the generator stage and the analog-to-digital converter to determine a filtering of disturbance present on the first reference signal and supply at output on a second reference terminal a second filtered reference signal, the filtering circuit having a switching circuit to connect the first reference terminal to the second reference terminal directly during startup of the reference signal generator circuit and then through the filtering circuit once the startup step is terminated.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a reference signal generator circuit for an analog-to-digital converter, in particular of an acoustic transducer, for example a MEMS (microelectromechanical system) capacitive microphone, to which the ensuing description will make explicit reference without implying any loss of generality; the present disclosure moreover relates to a method for generating the reference signal. 
         [0003]    2. Description of the Related Art 
         [0004]    As is known, an acoustic transducer of a capacitive type, for example, a MEMS microphone, generally includes a mobile electrode, provided as diaphragm or membrane, set facing a fixed electrode, to provide the plates of a variable-capacitance detection capacitor. The mobile electrode is generally anchored by means of a perimetral portion thereof to a substrate, whilst a central portion thereof is free to move or bend in response to the pressure exerted by incident sound waves. The mobile electrode and the fixed electrode form a capacitor, and bending of the membrane that constitutes the mobile electrode causes a variation of capacitance of the capacitor. In use, the variation of capacitance, which is a function of the acoustic signal to be detected, is transformed into an analog electrical signal that is supplied as output signal of the acoustic transducer. 
         [0005]    The analog electrical signal is generally converted into a digital signal so as to be appropriately processed. The operation of conversion is performed by means of an analog-to-digital (A/D) converter and is based, as is known, upon the comparison of the analog electrical signal at an input to the A/D converter with a reference voltage signal V REF , generated by an appropriate circuit external to the A/D converter and supplied on an input terminal of the latter. 
         [0006]    The resolution with which the analog-to-digital converter carries out the operation of conversion is strictly dependent upon the noise superimposed on the reference signal V REF . It is hence fundamental, in order to guarantee a high signal-to-noise ratio, to have available a reference voltage V REF  with low noise. 
         [0007]    To overcome the limitation, a circuit solution has been proposed, illustrated in  FIG. 1 , in which a lowpass filter  1 , in RC configuration, is connected to an output of the reference signal generator circuit  2  via an input terminal  3  of its own, and to an input of the analog-to-digital converter  4  via an output terminal  5  of its own, and has the function of filtering the reference signal V REF  so as to attenuate the noise components thereof. 
         [0008]    In particular, the lowpass filter  1  is provided with a filter resistor  6 , connected between the input terminal  3  and the output terminal  5 , and a filter capacitor  8  connected between the output terminal  5  and a ground terminal GND. 
         [0009]    It has, however, been shown that, in order for the action of lowpass filtering to be effective, it is convenient for the lowpass filter  1  to present a pole at a frequency lower than the audio band (indicatively included between 20 Hz and 20 kHz), preferably a frequency equal to or lower than 1 Hz. 
         [0010]    For this purpose, filter capacitors  8  are generally used, which have a high value of capacitance (for example, in the 100 nF-10 μF range) and, typically, cannot be integrated, as described, for example, in US 2008/0224759. 
         [0011]    Alternatively, it is possible to use extremely high values of resistance of the filter resistor  6 , included, for example, between 100 GΩ and 100 TΩ. 
         [0012]    As is known, since it is not feasible in the technology of integrated circuits to produce resistors with such high values of resistance, use of nonlinear devices able to provide the high values of resistance required has been proposed. For example, there has been proposed for this purpose the use of a pair of diodes in antiparallel configuration, which provide a resistance sufficiently high when there is a voltage drop thereon of contained value (depending upon the technology of fabrication of the diodes, for example less than 100 mV). 
         [0013]    As illustrated in  FIG. 2 , the filter resistor  6  can hence be provided by a respective pair of diodes in antiparallel configuration. 
         [0014]    In particular, the filter resistor  6  is provided by a first diode  6   a , with its anode connected to the input terminal  3  and its cathode connected to the output terminal  5 , and by a second diode  6   b , with its anode connected to the output terminal  5  and its cathode connected to the input terminal  3 . 
         [0015]    The main problem of circuit architectures of the above sort is represented by the long start-up time required for supply of a stable reference signal V REF  to the A/D converter  4 , on account of the presence of the pair of diodes  6   a ,  6   b  connected in antiparallel configuration and of the high value of resistance provided thereby. The settling time of a configuration of this sort may be of minutes or even hours; before the end of the settling time, i.e., throughout the period of start-up of the circuit, proper functioning of the lowpass filter  1  cannot be guaranteed, just as likewise a stable reference voltage V REF  cannot be guaranteed. 
         [0016]    During the start-up time, there hence occurs inevitably an even marked degradation in the performance of the A/D converter and of the corresponding MEMS microphone. 
         [0017]    Only at the end of the long start-up time, does the voltage on the output terminal  5  stabilize at the desired reference value. 
         [0018]    Clearly, such long delay times cannot be for example accepted in the common situations of use of the MEMS microphone, when instead it is necessary to guarantee the nominal performance with extremely short delays, both upon switching-on of a generic electronic device incorporating the MEMS microphone and upon return from a so-called “power-down” condition (during which the device itself is partially turned off to provide a condition of energy saving). 
       BRIEF SUMMARY 
       [0019]    The present disclosure provides a reference signal generator circuit for an analog-to-digital converter, in particular an acoustic transducer, that will enable the above-referenced drawbacks to be overcome. 
         [0020]    In accordance with one aspect of the present disclosure, a reference signal generator circuit for an analog-to-digital converter is provided. The circuit includes a signal-generation stage structured to generate a first reference signal on a first reference terminal; a filtering circuit arranged between the first reference terminal and a second reference terminal and structured to be connected to the analog-to-digital converter, the filtering circuit structured to determine a filtering of disturbance present on the first reference signal and to supply at output on the second reference terminal a filtered reference signal; the reference signal generator circuit comprising a switch circuit structured to be actuated so as to connect the first reference terminal to the second reference terminal directly during startup of the reference signal generator circuit and then through the filtering circuit once startup is terminated. 
         [0021]    In accordance with another aspect of the present disclosure, an electronic device is provided that includes an analog-to-digital converter and a reference signal generator circuit structured to supply a filtered reference signal to a reference input of the analog-to-digital converter, the reference signal generator circuit structured as described in the preceding paragraph. 
         [0022]    In accordance with yet a further aspect of the present disclosure, a method for generating a reference signal adapted for use in an analog-to-digital converter is provided. The method includes the steps of generating a first reference signal on a first reference terminal; and filtering any disturbance present on the first reference signal by a filtering circuit arranged between the first reference terminal and a second reference terminal and structured to be connected to the analog-to-digital converter for supplying at output on the second reference terminal a filtered reference signal; connecting the first reference terminal to the second reference terminal directly during a step of startup of the generation of the reference signal; and connecting the first reference terminal to the second reference terminal through the filtering circuit once the startup step is terminated so as to enable the step of filtering of disturbance present on the first reference signal. 
         [0023]    In accordance with yet another aspect of the present disclosure, a circuit is provided that includes a signal generator that generates a first reference signal at a first node; a filter circuit that receives the first reference signal at the first node and generates a filtered reference signal at a second node; and a switch circuit coupled to the filter circuit and structured, in response to a first control signal, to selectively connect the signal generator directly to the second node to bypass the filter circuit during a startup of the circuit and then to connect the filter circuit to the first and second nodes to filter the first reference signal following the startup of the circuit. 
         [0024]    In accordance with another aspect of the foregoing circuit, a buffer circuit is provided that is coupled to the second node to receive the filtered reference signal at a single-stage amplifier in voltage-follower configuration in the buffer and to drive at output a capacitive load coupled in parallel to a compensation capacitor. 
         [0025]    In accordance with still yet another aspect of the foregoing circuit, the filter circuit includes a first transistor coupled between the first and second nodes and structured to be actuated in a first operative condition of low-impedance conduction between the first and second nodes and in a second operative condition of high impedance between the first and second nodes, the filter circuit further comprising a second transistor in diode configuration coupled between the first and second nodes, and a control circuit coupled to the first transistor and structured to bias alternatingly a control terminal of the first transistor with a ground signal or the first reference signal to provide alternatingly the low-impedance connection or the high-impedance connection between the first and second nodes. 
         [0026]    In accordance with yet another aspect of the foregoing circuit, the control circuit includes a comparator and a logic block, the comparator receiving on a first input the filtered reference signal and on a second input a comparison signal correlated to the first reference signal to define a threshold, and to supply at output a result of a comparison between the comparison signal and the filtered reference signal that is received at the logic block, the logic block structured to also receive the first control signal and to supply at output a second control signal to drive the first transistor in low-impedance conduction when the filtered reference signal drops below the threshold. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0027]    For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the annexed drawings, wherein: 
           [0028]      FIG. 1  shows a lowpass filter of a known type, designed to filter a noisy reference signal for an analog-to-digital converter generated by a reference signal generator circuit; 
           [0029]      FIG. 2  shows an embodiment of a known type of the lowpass filter of  FIG. 1 ; 
           [0030]      FIG. 3  shows an embodiment of a reference signal generator circuit having an integrated lowpass filter according to one embodiment of the present disclosure; 
           [0031]      FIG. 4  shows an embodiment of the lowpass filter of the reference signal generator circuit of  FIG. 3 ; 
           [0032]      FIG. 5  shows an embodiment of a diode-connected transistor of the lowpass filter of  FIG. 4 ; 
           [0033]      FIG. 6  shows an equivalent scheme of operation of the lowpass filter of  FIG. 5 ; 
           [0034]      FIG. 7  shows the reference signal generator circuit of  FIG. 3  further having a driver buffer for a capacitive load; 
           [0035]      FIG. 8  shows the reference signal generator circuit of  FIG. 7  further having a feedback loop for stabilization of the reference signal; 
           [0036]      FIG. 9  shows a block diagram of a MEMS microphone, which includes the reference signal generator circuit of  FIG. 7  or  FIG. 8 ; and 
           [0037]      FIG. 10  shows an electronic device in which the reference signal generator circuit according to the present disclosure can be used. 
       
    
    
     DETAILED DESCRIPTION 
       [0038]    In  FIG. 3  an improved reference signal generator circuit  11  is provided in accordance with one aspect of the present disclosure and which includes a filter  10  of a lowpass type in RC configuration. Elements of the filter  10  that are similar to elements already described with reference to  FIGS. 1 and 2  are designated by the same reference numbers. The filter  10  is configured for receiving on the input terminal  3  a noisy reference signal V REF  and for generating at output on the output terminal  5  a filtered reference signal V REF     —     FIL . 
         [0039]    The noisy reference signal V REF  can be generated by a reference signal generator circuit  2  of a known type, for example a generator of a band-gap type. In this case, the filter  10  is connected via its own input terminal  3  to the output of the reference signal generator circuit  2 . 
         [0040]    Unlike filters of a known type (such as the one illustrated in  FIG. 1 ), the embodiment of the filter  10  envisages use of a turning-on switch  12 , connected in parallel to the filter resistor  6 , and can be actuated selectively to provide a low-impedance direct connection between the input terminal  3  and the output terminal  5  of the filter  10 . In particular, the turning-on switch  12 , receives an appropriate control signal  51  from a control logic (not shown), for example having appropriate counters or timers, in such a way as to be closed during a step of start-up of the filter  10 , thus guaranteeing a rapid settling of the voltage values of the output terminal  5 , and in such a way as to be open during a next step of normal operation of the filter  10 , thus guaranteeing proper operation of filtering of the noisy reference signal V REF . The start-up step terminates when the output terminal  5  of the filter  10  has reached the desired voltage, i.e., when the filter capacitor  8  is completely charged. 
         [0041]    It has been found that, in order to limit the introduction of noise or parasitic signals by the filter  10 , it is expedient not to introduce parasitic junctions connected to the output terminal  5 . A parasitic junction connected, for example, between the output terminal  5  and the ground terminal GND could in fact shift significantly the working point of the filter  10 , causing a variation of the voltage value of the noisy reference signal V REF  and/or a variation of the cutoff frequency. 
         [0042]      FIG. 4  shows a circuit diagram of a possible embodiment of the filter  10  of  FIG. 3  in a completely integrated form. 
         [0043]    The filter  10  includes an inverter stage  20 , which includes a transistor T 1 , for example a P-type MOSFET, and a transistor T 2 , for example an N-type MOSFET. The transistors T 1  and T 2  are driven in conduction and inhibition by means of the control signal S 1 . In greater detail, the transistor T 1  is connected, via its own source terminal, to the input terminal  3  and, via its own drain terminal, to a drain terminal of the transistor T 2 . The source terminal of the transistor T 2  is, instead, connected to the ground terminal GND. 
         [0044]    The filter  10  further includes a pair of transistors T 3  and T 4 , in diode configuration, i.e., having a gate terminal of their own connected to a source terminal of their own. In particular, the gate terminal of the transistor T 4  is connected to the source terminal of the transistor T 4  itself via the transistor T 1 . 
         [0045]    In greater detail, the transistors T 3  and T 4  include a respective source terminal connected to the input terminal  3  and a respective drain terminal connected to the output terminal  5 . The transistors T 3  and T 4  are consequently connected in parallel to one another. 
         [0046]    Finally, the filter capacitor  8  is connected between the output terminal  5  and the ground terminal GND, thus providing the lowpass filter. 
         [0047]    Whereas the transistors T 1 , T 2  and T 4  can be generic transistors, in order to eliminate (or in any case limit considerably) parasitic junctions between the output terminal  5  and the ground terminal GND, the transistor T 3  advantageously includes an insulation layer, which is biased at a voltage value Vdd, for example included between 1 V and 5 V, preferably equal to 1.8 V, and is designed to electrically insulate the transistor T 3  from the substrate in which the transistor (as well as, in general, the components of the filter  10  described) are formed.  FIG. 5  shows a cross-sectional view of a transistor T 3 , of a MOSFET type, designed for this purpose. 
         [0048]    As illustrated in  FIG. 5 , the transistor T 3  includes: a substrate  21 , of a P type, connected to the ground terminal GND; an insulation region  22 , of an N type, set in contact with the substrate  21  and electrically connected to a biasing terminal  23 , configured for biasing the insulation region  22  at the voltage Vdd; a well region  24 , of a P type, insulated from the substrate  21  via the insulation region  22 ; a source region  25 , of an N type, formed in the well region  24  and connected to the input terminal  3 ; a drain region  26 , of an N type, formed in the well region  24  and connected to the output terminal  5 ; and a gate region  27 , connected to the input terminal  3  and insulated from the well region  24  by means of a dielectric region  28 . 
         [0049]    As may be noted in  FIG. 5 , the diode configuration envisages that the gate region  27 , the source region  25 , and the well region  24  are connected together. 
         [0050]    To return to  FIG. 4 , during the step of start-up of the filter  10 , the control signal S 1  drives in conduction the transistor T 2  and in inhibition the transistor T 1 . In this way, the transistor T 4 , of a P type, is biased in conduction by the signal coming from the ground terminal GND, setting in direct connection at low impedance the input terminal  3  with the output terminal  5  so as to charge the filter capacitor  8 . 
         [0051]    When the voltage value of the filtered reference signal V REF     —     FIL  on the output terminal  5 , i.e., the voltage on the filter capacitor  8 , equals the voltage value of the noisy reference signal V REF  (for this purpose, if the time necessary to charge the filter capacitor  8  is known, it may be advantageous to use a digital timer), the control signal S 1  switches, driving the transistor T 1  in conduction and the transistor T 2  in inhibition. Consequently, the voltages V GS  between the gate terminal and the source terminal of the transistor T 4  and of the transistor T 3  are substantially the same as one another and equal to 0 V, and the transistors T 3  and T 4  are both turned off and provide the first diode  6   a  and the second diode  6   b . Note therefore that the transistor T 4  provides, in use, both the turning-on switch  12  and the second diode  6   b.    
         [0052]      FIG. 6  shows an equivalent scheme during a functioning step of the filter of  FIG. 4  in which a first parasitic element  30  and a second parasitic element  31 , in particular two parasitic diodes, generated inside the transistors T 3  and T 4 , are shown. 
         [0053]    The transistor T 4 , of a known type, is formed by a substrate of a P type, common to the substrate  21  of the transistor T 3  of  FIG. 5  and hence connected to the ground terminal GND, and by a well region thereof of an N type, in which the drain and source regions of the transistor T 4  are formed. The well region hence forms with the substrate a PN junction connected between the input terminal  3  and the ground terminal GND. The PN junction is indicated in  FIG. 6  as a first parasitic element  30 . 
         [0054]    Likewise, with reference to  FIG. 5 , the insulation region  22  and the well region  24  of the transistor T 3  provide a PN junction connected between the input terminal  3  and the biasing terminal  23 . The PN junction is represented in  FIG. 6  as a second parasitic element  31 . 
         [0055]    The first and second parasitic elements  30 ,  31  are consequently advantageously connected to the input terminal  3  of the filter  10  and not to the output terminal  5 , without causing in this way the problems discussed previously in this regard. 
         [0056]    By appropriately sizing the transistors T 3  and T 4 , it is possible to define precisely at what frequency to introduce the pole of the filter  10 . For example, if the channel length L of the transistors T 3  and T 4  is fixed, it is possible to vary the channel width W. In particular, by increasing the value of channel width W, the transistors T 3  and T 4  are more conductive, and the pole of the filter shifts to higher frequencies; instead, by reducing the channel width W, the transistors T 3  and T 4  are less conductive, and the pole of the filter shifts to lower frequencies. 
         [0057]    If the filtered reference signal V REF     —     FIL  generated by the reference signal generator circuit  11  is used for charging the capacitances, as for example occurs in the case where the reference signal generator circuit  11  is connected to an A/D converter  4 , the latter being provided with the switched-capacitor technique, it is expedient to set a buffer circuit between the reference signal generator circuit  11  and the A/D converter  4  in order to be able to drive the capacitive load. 
         [0058]    The buffer circuit is advantageously provided in such a way as to have an input impedance higher than that of the filter  10  in order not to degrade the performance of the latter, in particular in terms of noise and hence of precision of the reference voltage value achieved. 
         [0059]      FIG. 7  shows a reference signal generator circuit  11  having a buffer circuit  40 , in turn having an amplifier device  42 , for example a single-stage amplifier in CMOS technology. The amplifier device has an inverting terminal  42 ′ and a non-inverting terminal  42 ″. The non-inverting terminal  42 ″ is connected to the output terminal  5  of the filter  10 , whilst the inverting terminal  42 ′ is connected to the output terminal of the amplifier device  42 , in voltage-follower configuration. 
         [0060]    In general, a buffer circuit introduces noise on the signal that it generates at output; in particular, the voltage noise introduced by a buffer circuit having a single-stage amplifier, such as, for example, the buffer circuit  40 , is given by formula (1): 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     NOISE_BUFF 
                   
                   = 
                   
                     
                       
                         2 
                          
                         
                           KT 
                           · 
                           γ 
                         
                       
                       
                         C 
                         LOAD_TOT 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where γ is the noise factor of the MOSFETs of the amplifier device  42 , K is Boltzmann constant, T is the temperature expressed in Kelvin, and C LOAD     —     TOT  is the total capacitance seen at output from the amplifier device  42 . 
         [0061]    Hence, it is clear that by increasing the capacitive load it is possible to reduce further the noise introduced, typically at the expense of a higher current consumption. 
         [0062]      FIG. 7  shows an input stage of the A/D converter  4  represented schematically as a generic switched-capacitance capacitive load, driven by the buffer circuit  40  and having: a first load switch  46 , having a first terminal  46 ′ and a second terminal  46 ″, and connected to the output of the amplifier device  42  via the first terminal  46 ; a load capacitor  47 , having value of capacitance C LOAD , connected between the second terminal  46 ″ of the first load switch  46  and the ground terminal GND; and a second load switch  48 , connected in parallel to the load capacitor  47 . 
         [0063]    On the basis of formula (1), in order to reduce the voltage noise introduced by the buffer circuit  40 , the buffer circuit  40  further includes a compensation capacitor  50 , having a value of capacitance C COMP , connected between the output of the amplifier device  42  and the ground terminal GND. The value of capacitance C LOAD     —     TOT  according to formula ( 1 ) is consequently given by C LOAD     —     TOT =C COMP +C LOAD . 
         [0064]    Consequently, as emerges from formula (I) above, by choosing appropriately the value of capacitance C COMP  it is possible to keep the noise generated by the buffer circuit  40  within the desired limits. There exists, however, a problem of capacitive coupling between the input and the output of the amplifier device  42 . When the first load switch  46  is driven in conduction, the output voltage of the buffer circuit  40  goes to a voltage lower than the voltage value of the filtered reference signal V REF     —     FIL  on account of the charge partition between the compensation capacitor  50  and the load capacitor  47 , and then returns to the value of the voltage of the filtered reference signal V REF     —     FIL  after a period of transient that depends upon the characteristics of the amplifier device  42 . This disturbance appears, attenuated, also at the input of the buffer circuit  40 , on account of the capacitive coupling between the inputs  42 ′ and  42 ″ of the amplifier device  42 . The effect of the coupling is, however, the smaller, the greater the value of capacitance of the filter capacitor  8 . 
         [0065]    During a transient period, following upon closing of the first load switch  46 , the compensation capacitor  50  discharges; on account of the capacitive coupling also the filter capacitor  8  discharges, and the load capacitor  47  charges; consequently, the first and second diodes  6   a  and  6   b  of the filter  10  are subjected to a voltage such as to cause a current to flow through them, which charges the filter capacitor  8  again. On account of the combined action of the buffer circuit  40 , which tends to re-establish the voltage on its output at the value prior to closing of the load switch  46 , and on account of the charge that flows to the filter capacitor  8  via the first and second diodes  6   a  and  6   b , during the period of transient, the voltage value of the filtered reference signal V REF     —     FIL  increases beyond the voltage value of the noisy reference signal V REF , until a point of equilibrium is reached in which the mean transfer of charge through the diodes  6   a  and  6   b  is zero. This effect, which is undesirable, can be reduced by increasing one or all from among the value of capacitance C COMP  of the compensation capacitor  50 , the value of capacitance C LOAD  of the load capacitor  47 , and the passband of the buffer circuit  40  (by increasing the current supplied to the amplifier device  42 ) or in any case by speeding up its settling time, in a way in itself known. 
         [0066]    A particularly advantageous implementation envisages the use of a single-stage amplifier, functioning in class AB (for example, of the type illustrated and described in A. J. Lòpez-Martin, S. Baswa, J. Ramirez-Angulo, R. G. Carvajal, “Low-VoltageSuper Class AB CMOS OTA Cells With Very High Slew Rate and Power Efficiency”, IEEE Journal of Solid-State Circuits, but other single-stage amplifiers of a known type can be used). It is thus possible to contain the noise on the reference and at the same time minimize the effects of the kick-back voltage of the load, which occurs in several A/D converters, with a reduced current consumption. 
         [0067]    In this way, it is moreover possible to provide a filter  10  with a drop across it in the region of a few millivolts, which in percentage terms does not present a marked impact upon the performance of the system in which the filter  10  operates, provided that the reference voltage is sufficiently high (for example 1V or more). 
         [0068]    Finally, as illustrated in  FIG. 8 , it is possible to add to the reference signal generator circuit  11   a  control loop  51 , having a comparator device  52  and an OR logic  53 , capable of resetting the filter  10  in the case where the voltage value of the filtered reference signal V REF     —     FIL  on the output of the filter  10  drops below a certain limit, for example by a value included between 1% and 10% of the voltage value of the reference signal V REF . 
         [0069]      FIG. 8  shows a reference signal generator circuit  11  in which the reference signal generator circuit  2  is represented schematically by showing exclusively an output stage of a bandgap circuit of a known type, and includes: a supply terminal  54 , supplied at a supply voltage V AL ; a transistor  56 , belonging to a current mirror of the output stage of the bandgap circuit, having a first terminal of its own connected to the supply terminal  54  and a second terminal of its own connected to the input terminal  3  of the filter  10 ; a first reference resistor  58 , having a first terminal of its own connected to the input terminal  3  of the filter  10 ; and a second reference resistor  59 , having a first terminal of its own connected to a second terminal of the first reference resistor  58  and a second terminal of its own connected to the ground terminal GND, the first and second reference resistors  58 ,  59  hence providing a resistive divider. 
         [0070]    The comparator device  52  of the control loop  51  receives on a first input thereof the filtered reference signal V REF     —     FIL  (as present on the output terminal  5  of the filter  10 ) and on a second input thereof a comparison voltage V 1 , correlated to the noisy reference voltage V REF , and in particular obtained by taking the partition voltage present on the first terminal of the second reference resistor  59 . The comparison voltage V 1  is consequently lower than the noisy reference voltage V REF , and its value (for example included in the 10-100 mV range) depends upon the value of resistance chosen for the first and second reference resistors  58 ,  59 . 
         [0071]    After the comparator device  52  has performed the operation of comparison between the voltage value of the noisy reference signal V REF  and the comparison voltage V 1 , it generates at output a binary signal, which is supplied on a first input of the OR logic  53 . The OR logic  53  receives on a second input thereof the control signal S 1 , which is, for example, also of a binary type, and generates at output a further control signal S 2 . 
         [0072]    In normal operating conditions, the control signal S 1  has a low logic value, the voltage value of the filtered reference signal V REF     —     FIL  does not drop below the threshold value defined by the comparison voltage V 1  and the logic value of the control signal S 2  is equal to the logic value of the control signal S 1 . With reference to  FIG. 3 , in this condition the turning-on switch  12  is driven in inhibition. If the voltage value of the filtered reference signal V REF     —     FIL  drops below the threshold value defined by the comparison voltage V 1 , the signal generated by the comparator device  52  has a high logic value, and consequently also the control signal S 2  acquires a high logic value. In this case, the transistor T 4  (i.e., with reference to  FIG. 3 , the turning-on switch  12 ) is driven in conduction, and the voltage on the filter capacitor  8  (i.e., the voltage on the output terminal  5  of the filter  10 ) is brought to the appropriate value by means of the low-impedance connection with the input terminal  3 . 
         [0073]    It is evident that, by varying the value of resistance of the first and second reference resistors  58 ,  59 , it is possible to vary the comparison voltage value V 1 , consequently varying the comparison threshold of the comparator device  52 . 
         [0074]    The characteristics previously listed render use of the reference signal generator circuit  11  within a MEMS microphone  90  particularly advantageous. 
         [0075]    As illustrated in  FIG. 9 , a MEMS microphone  90  includes two different blocks: a mechanical block  91 , basically constituted by the sensor sensitive to the acoustic stimuli (provided by at least two electrodes, one of which is mobile), and a signal-processing block  92  (ASIC) configured for biasing correctly the sensor and for appropriately processing the electrical signal generated by the sensor so as to produce on an output of the MEMS microphone  90  a digital signal that can be processed, for example, by a microcontroller (not shown), designed for the purpose. 
         [0076]    The signal-processing block  92  in turn includes a plurality of functional sub-blocks. In particular, the signal-processing block  92  includes: a charge pump  93 , which enables generation of an appropriate voltage for biasing the sensor of the mechanical block  91 ; a preamplifier  94 , designed to amplify the electrical signal generated by the sensor; the analog-to-digital converter  4 , for example, of a sigma-delta type, configured for receiving the electrical signal amplified by the preamplifier  94 , of an analog type, and convert it into a digital signal; the reference signal generator circuit  11  according to the present disclosure, connected to the analog-to-digital converter  4 ; and a driver  95 , designed to function as interface between the analog-to-digital converter  4  and an external system, for example a microcontroller. 
         [0077]    Furthermore, the MEMS microphone  90  can include a memory  96  (either volatile or nonvolatile), for example, programmable from outside so as to enable use of the MEMS microphone  90  according to different configurations (for example, of gain). 
         [0078]    The characteristics previously listed render use of the reference signal generator circuit  11  and of the MEMS microphone  90  in which the reference signal generator circuit  11  is implemented particularly advantageous in an electronic device  100 , as illustrated in  FIG. 10  (the electronic device  100  can possibly include further MEMS microphones, in a way not illustrated). The electronic device  100  is preferably a mobile-communication device, such as for example a cellphone, a PDA, a notebook, but also a voice recorder, a reader of audio files with voice-recording capacity, etc. Alternatively, the electronic device  100  can be a hydrophone, capable of working under water, or else a hearing-aid device. 
         [0079]    The electronic device  100  includes a microprocessor  101  and an input/output interface  103 , for example provided with a keyboard and a video, which is also connected to the microprocessor  101 . The MEMS microphone  90  communicates with the microprocessor  101  via the signal-processing block  92 . Furthermore, a loudspeaker  106  may be present, for generating sounds on an audio output (not shown) of the electronic device  100 . 
         [0080]    From an examination of the characteristics of the present disclosure the advantages that it affords are evident. 
         [0081]    In particular, the reference signal generator circuit  11  according to the present disclosure has a reduced switching-on time, of the order of approximately 10 ms, a contained consumption, and supplies at output a filtered reference signal V REF     —     FIL  (which can, for example, be used as reference signal for an analog-to-digital converter) characterized by low noise, in particular in the audio band, and with driver capacity (for example for a switched-capacitance load). 
         [0082]    In addition, since it has a reduced area, the circuit can be completely integrated in CMOS technology. 
         [0083]    The characteristics hence render use of the reference signal generator circuit  11  particularly advantageous in an analog-to-digital converter of a sigma-delta type. 
         [0084]    However, the present disclosure can be used with an analog-to-digital converter of any type. 
         [0085]    Finally, it is clear that modifications and variations may be made to what has been described and illustrated, herein without thereby departing from the sphere of protection of the present disclosure, as defined in the annexed claims. 
         [0086]    In particular, it is evident that the reference signal generator  11  according to the present disclosure can be used for other applications in which the use of a filtered reference signal having the characteristics highlighted previously is required, and moreover that the analog-to-digital converter, which uses the reference signal generator, can be used in other applications and in combination with other electronic circuits and devices, in which the noise must be attenuated in a band that does not include d.c. 
         [0087]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent application, foreign patents, foreign patent application and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, application and publications to provide yet further embodiments. 
         [0088]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.