Abstract:
The purpose of the present invention is to provide a method for switching devices that enables the prediction of when a reverse current condition will occur regardless of voltage-mode or current-mode switching regulator. According to the present invention, the reverse current reduction technique is realized by implementing a circuit which takes in the PWM signal, switching regulator&#39;s output signal and the Supply Voltage, before outputting a logic signal to indicate the start of reverse current flow; an OR gate, which outputs a logic signal to control the turning ON/OFF of the PMOS buffer at the output.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of Invention 
         [0002]    Switching devices are now being used in almost everywhere around the globe. The main reasons cited are due to the low power consumed and the longer lifespan of such devices. Examples of switching devices are switching regulators and Class D power amplifiers. 
         [0003]    2. Description of Related Art 
         [0004]    A switching regulator can operate in 2 modes: 1) discontinuous conduction mode (DCM) and 2) continuous conduction mode (CCM). However, even though a switching regulator is designed to operate in CCM, it can go into DCM when load condition is small. The description of operation of both modes will be explained in subsequent paragraphs. 
         [0005]    When designing switching regulator, most of the time synchronous switching is used. Synchronous switching uses 2 power switches (refer to  FIGS. 1A and 1B ) that can improve the efficiency. The 2 power switches in  FIG. 1A  are P 1  and N 1 , whereas the 2 power switches in  FIG. 1B  are P 2  and N 2  respectively. Efficiency is a very important factor when dealing with portable devices where efficiency determines the battery life. 
         [0006]    However, small load condition becomes a problem when synchronous switching regulator is used. Switching regulator always remains in CCM operation even though the load condition is small. Referring to  FIGS. 2A ,  2 B and  2 C, we notice that there is reverse current (negative current in the inductor) that flows back from output capacitor. As shown, this phenomenon occurs for both Buck and Boost modes. This reverse current or ‘always CCM’ operation can cause serious problems to a switching regulator, which will be described in the following paragraph. 
         [0007]    One of the common problems associated with reverse currents is that the efficiency is badly affected during light load condition even though synchronous switching is used. Another problem is that the boost converter is not able to boost to very high output voltage when using ‘always CCM’ operation due to reverse current. For boost converter to achieve high output voltage, it is necessary to have very high duty cycle (during CCM). However, this increases the risk of going into instability (limitation of boost converter). Hence boost regulator is usually designed with non-synchronous switching that can operate in DCM to achieve high output voltage. As a result, efficiency cannot be high as non-synchronous switching is used. 
         [0008]    To solve reverse current or always CCM operation issue when using synchronous switching regulator, reverse current detection is designed. Conventional method used is to design a comparator that detects reverse current (or 0V detection with small voltage offset). This is as shown in  FIGS. 3A and 3B , for a buck and boost configurations respectively. Using  FIG. 3B  as reference, Reverse Current Detection comparator, RDET, is used to monitor the potential across the terminals of the PMOS transistor P 2 . Hence, essentially, the direction of flow of current across PMOS transistor P 2  is monitored. When a reverse current condition occurs, the potential difference across PMOS transistor P 2  is of the opposite polarity of the initial condition when the current is flowing in the forward direction towards the load. When such a condition happens, RDET will output a signal to turn off the PMOS transistor P 2 , hence stopping any further reverse current flow. The same principle applies for the operation of RDET used for the buck converter (as shown in  FIG. 3A ). 
         [0009]    However the implementation of such a comparator to detect reverse current can be very difficult due to many reasons mentioned below. 
         [0010]    Power NMOS transistor N 1  ( FIG. 3A ) or Power PMOS transistor P 2  ( FIG. 3B ) ON resistance cannot be too small because it is hard to detect small voltage across it. A small ON resistance would also mean that the reverse current need to be very large before there is any successful detection. However, deliberate increasing of the ON resistance of NMOS or PMOS for easy detection is not a wise move as it will affect efficiency (due to larger potential drop, and hence power loss, across the larger ON resistance). 
         [0011]    Another alternative is to decrease the inductor size for easier detection so that ripple current amplitude is larger (rate of change in inductor current is faster). However larger current ripple means more current stress to power devices. Therefore size of power devices need to increase to handle the larger resultant peak current. This is also not a good method. 
         [0012]    Another problem about this method is that the switching node has high voltage swing. It will generate too much noise to the input of the comparator. Sometimes it will create a wrong detection signal! 
         [0013]    A high speed comparator is necessary especially for high switching frequency regulator. The ON time of the NMOS transistor N 1  ( FIG. 3A ) or PMOS transistor P 2  ( FIG. 3B ) can be so short until it is only ON for a few hundreds of nano-sec before any successful detection due to slow comparator. 
         [0014]    For boost converter ( FIG. 3B ), output voltage is higher than input voltage. As such, detection comparator needs to have level shifter or protection circuit to protect against high voltage breakdown. Additions of such circuit will also slow down the speed of detection. 
         [0015]      FIG. 4  is a diagram of a circuit for power supply control according to prior art US2006/0113980. The circuit comprise of a reverse current detection system that detects the number of times a reverse current condition has occurred. Once the pre-determined number of times of such detections has been reached, the circuit sends a signal to turn off the switching device (e.g. a switching regulator, a class D power amplifier, etc). Thus the reverse current condition is temporarily stopped. The problem with this method is that it allows the reverse current condition to happen, and only turns off the switching device after a pre-determined number of hits occur. 
         [0016]    The present invention is intended to solve the problems mentioned above, and it is an object of the present invention to provide a protection for the circuit elements in a switching device, by predicting when a reverse current will occur, and hence turning off the NMOS in Buck converter design or PMOS in Boost converter design to prevent a reverse current from flowing into the circuit. The present invention can also apply to Buck-Boost converter. 
       SUMMARY OF THE INVENTION 
       [0017]    The purpose of this invention is to provide a method for switching devices that enables the prediction of when a reverse current condition will occur regardless of voltage-mode or current-mode switching regulator. 
         [0018]    According to the present invention, the reverse current reduction technique is realized by implementing a circuit which takes in the PWM signal, switching regulator&#39;s output signal and the Supply Voltage, before outputting a logic signal to indicate the start of reverse current flow; an OR gate, which outputs a logic signal to control the turning ON/OFF of the PMOS buffer at the output. 
         [0019]    For buck converter: a relationship made between the ON times of NMOS transistor N 1  and PMOS transistor P 1  may be easily obtained. Through this relationship, we will be able to know when the current flowing through the NMOS transistor N 1  is expected to start flowing in the reverse direction. 
         [0020]    For boost converter: a relationship made between the ON times of NMOS transistor N 2  and PMOS transistor P 2  may be easily obtained. Through this relationship, we will be able to know when the current flowing through the PMOS transistor P 2  is expected to start flowing in the reverse direction. 
         [0021]    The present invention does not occupy large mask area or involve complex design. And it can be applied to all sorts of switching regulator that uses synchronous switching and has the possibility of having reverse current. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0022]      FIG. 1A  is a prior art drawing of a typical output stage of a synchronous buck converter configuration. 
           [0023]      FIG. 1B  is a prior art drawing of a typical output stage of a synchronous boost converter configuration. 
           [0024]      FIG. 2A  is a prior art drawing of a typical output stage of a synchronous buck converter configuration, showing the forward and reverse current directions. 
           [0025]      FIG. 2B  is a prior art drawing of a typical output stage of a synchronous boost converter configuration, showing the forward and reverse current directions. 
           [0026]      FIG. 2C  is a prior art drawing of a typical inductor current waveform under DCM operation, with reverse current shaded. 
           [0027]      FIG. 3A  is a prior art drawing of a typical output stage of a synchronous buck converter configuration, with a prior art implementation of a reverse current detection circuit. 
           [0028]      FIG. 3B  is a prior art drawing of a typical output stage of a synchronous boost converter configuration, with a prior art implementation of a reverse current detection circuit. 
           [0029]      FIG. 4  is a prior art drawing of US20060113980 A1, implementing a reverse current detection system. 
           [0030]      FIG. 5A  is a block diagram showing a typical configuration of a Voltage Mode switching regulator. 
           [0031]      FIG. 5B  is yet another block diagram showing a typical configuration of a Current Mode switching regulator. 
           [0032]      FIG. 6A  shows a typical output stage of a synchronous boost converter, with a first preferred embodiment according to the present invention. 
           [0033]      FIG. 6B  shows a typical output stage of a synchronous boost converter, with a second preferred embodiment according to the present invention. 
           [0034]      FIG. 6C  shows a typical output stage of a synchronous boost converter, with a third preferred embodiment according to the present invention. 
           [0035]      FIG. 7  shows waveforms of selected important nodes based on the present invention. 
           [0036]      FIG. 8  shows waveforms of selected important nodes based on the present invention, when used under a CCM operation. 
           [0037]      FIG. 9A  shows a generic implementation of Timer for a synchronous boost converter based on the fourth preferred embodiment. 
           [0038]      FIG. 9B  shows one example of circuit implementation of Timer for a synchronous boost converter based on the fifth preferred embodiment. 
           [0039]      FIG. 9C  shows waveforms of selected important nodes based on the present invention. 
           [0040]      FIG. 10A  shows a typical output stage of a synchronous buck converter, with a sixth preferred embodiment according to the present invention. 
           [0041]      FIG. 10B  shows a typical output stage of a synchronous buck converter, with a seventh preferred embodiment according to the present invention. 
           [0042]      FIG. 10C  shows a typical output stage of a synchronous buck converter, with a eighth preferred embodiment according to the present invention. 
           [0043]      FIG. 11  shows waveforms of selected important nodes based on the present invention. 
           [0044]      FIG. 12  shows waveforms of selected important nodes based on the present invention, when used under a CCM operation. 
           [0045]      FIG. 13A  shows a generic implementation of Timer for a synchronous buck converter based on the ninth preferred embodiment 
           [0046]      FIG. 13B  shows one example of circuit implementation of Timer for a synchronous buck converter based on the tenth preferred embodiment. 
           [0047]      FIG. 13C  shows waveforms of selected important nodes based on the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0048]      FIG. 5A  is a block diagram showing a typical configuration of a Voltage Mode switching regulator, in which the present invention is typically used.  FIG. 5B  is yet another block diagram showing a typical configuration of a Current Mode switching regulator, in which the present invention may be alternatively be used. As shown in  FIG. 5A , the DCDC Controller will generate PWM signal PWMO to determine how much time to turn ON and OFF the power transistors. The DCDC Converter block  101  shows an example of an implementation of the present invention, relative to the voltage mode switching regulator system. 
         [0049]      FIG. 6A  shows a typical output stage of a synchronous boost converter, with a first preferred embodiment  104  according to the present invention, as implemented in the DCDC Converter block  101 . We shall name the first preferred embodiment as the Intelligent Timing Block  104 . Block  104  outputs a signal to the input of driver  107  so as to control the ON and OFF state of PMOS M 2 . Block  104  obtains as inputs: A VOUT signal or a switching node signal LX, a power supply voltage VB, and the PWM signal PWMO or any of its derivatives (e.g. inverted PWMO, delayed PWMO, etc). Block  104  will process the inputs and hence turn ON or OFF the PMOS M 2  so as to prevent any reverse current from occurring. An exemplary operation of the first embodiment according to the present invention is explained as follows: 
         [0050]    A case when PWM signal PWMO is high: 
         [0051]    The following explanation makes reference to  FIG. 6A  and selected important waveforms in  FIG. 7 . The output signal of driver  106  will be equal to its input. Hence, the gate terminal of NMOS M 1 , NGATE, will be logic signal high. Thus, NMOS M 1  is ON. The period when NMOS M 1  is ON shall be referred to as period NTON. At the same time, Intelligent Timing Block  104  is configured so that the input of driver  107  is also high. The resultant high driver output will thus cause the gate terminal of PMOS M 2 , PGATE, to be high. Thus, PMOS M 2  will be OFF. As a result, Inductor  105  will be charged up (current rising) during this time. 
         [0052]    A case when PWM signal PWMO is low: 
         [0053]    The following explanation makes reference to  FIG. 6A  and selected important waveforms as shown in  FIG. 7 . The output signal of driver  106  will be equal to its input. Hence, the gate terminal of NMOS M 1  will be low. Thus, NMOS M 1  is OFF. At the same time, Intelligent Timing Block  104  is configured so that the input of driver  107  is also low. The resultant low driver  107  output will thus cause the gate terminal of PMOS M 2  to be low. Thus, PMOS M 2  will be ON. The period when PMOS M 2  is ON shall be referred to as period PTON. Inductor  105  will be discharged (current falling) during this time. 
         [0054]    After a certain time (this timing will be further explained later), Block  104  will output a logic high. Thus, input of driver  107  being equal to its output, PGATE will thus be at a logic signal high. Thus, PMOS M 2  is OFF. During this OFF time, both NMOS M 1  and PMOS M 2  are OFF. This state is known as dead-time. Any current left in inductor will be discharged through parasitic diode. PMOS M 2  remains OFF until PWM signal PWMO goes high again to turn ON NMOS M 1  again. 
         [0055]      FIG. 6B  shows a second preferred embodiment according the present invention. The present invention comprises of the following elements: a Timer  102  which determines the ON time of PMOS M 2  and a logic block  103 . Together, these 2 elements shall collectively comprise the Intelligent Timing Block  104 . Next we shall explain the working of the second preferred embodiment according the present invention. 
         [0056]    A case when PWM signal PWMO is high: 
         [0057]    The following explanation makes reference to  FIG. 6B  and selected important waveforms as shown in  FIG. 7 . The output signal of driver  106  will be equal to its input. Hence, the gate terminal of NMOS M 1  will be logic signal high. Thus, NMOS M 1  is ON. The period when NMOS M 1  is ON is equal to NTON. At the same time, Intelligent Timing Block  104  is configured so that the input of driver  107  is also high. The resultant high driver output will thus cause the gate terminal of PMOS M 2  to be high. Thus, PMOS M 2  will be OFF. As a result, Inductor  105  will be charged up (current rising) during this time. 
         [0058]    A case when PWM signal PWMO is low: 
         [0059]    The following explanation makes reference to  FIG. 6B  and selected important waveforms in  FIG. 7 . The output signal of driver  106  will be equal to its input. Hence, the gate terminal of NMOS M 1  will be low. Thus, NMOS M 1  is OFF. At the same time, Intelligent Timing Block  104  is configured so that the input of driver  107  is also low. The resultant low driver  107  output will thus cause the gate terminal of PMOS M 2  to be low. Thus, PMOS M 2  will be ON. The period when PMOS M 2  is ON is equal to PTON. Inductor  105  will be discharged (current falling) during this time. 
         [0060]    The default signal at node PTIME is logic signal low or a first unique signal S A . The Timer  102  will give a logic signal high or a unique signal S B , via node PTIME after a certain time (this timing will be further explained later). PTIME at logic signal high or upon receiving S B , will cause the resultant output of logic block  103  to be high. Thus, input of driver  107  being equal to its output, PGATE will thus be at a logic signal high. Thus, PMOS M 2  is OFF. During this OFF time, both NMOS M 1  and PMOS M 2  are OFF. This state is known as dead-time. Any current left in inductor will be discharged through parasitic diode. PMOS M 2  remains OFF until PWM signal PWMO goes high again to turn ON NMOS M 1  again. 
         [0061]      FIG. 6C  shows a third preferred embodiment according the present invention. Logic block  103  may be implemented using an OR gate. 
         [0062]    Above is the case for DCM operation. Under the CCM operation, the invention does not cause any undesirable effects. The explanation is as follows: 
         [0063]    Referring to  FIGS. 6B and 8 , if NMOS M 1  turns ON again before Timer  102  can give a logic signal high, there is no instance where both NMOS M 1  and PMOS M 2  are OFF (no dead-time). Moreover, reverse current does not occur for a CCM operation. This means that the Timer  102  will not give a logic signal high or a unique signal S B , via node PTIME. Hence, the Intelligent Timing Block  104 , according to the present invention, does not have any effect on the CCM operation. 
         [0064]    An explanation of the time duration to determine the sequence of turning ON to OFF of PMOS M 2  shall be given as follows: 
         [0065]    Referring to  FIG. 7 , for a boost converter type of DCDC converter, current ripple across inductor is calculated based on NMOS and PMOS ON times as follows: 
         [0000]      Δ I =(( VB−LX )× NT ON)/ L out( NMOS ON)  (1) 
         [0000]      Δ I =(( V OUT− LX−VB )× PT ON)/ L out( PMOS ON)  (2) 
         [0066]    where
       NTON=time for which NMOS M 1  is turned ON;   PTON=time for which PMOS M 2  is turned ON;   ΔI=Inductor current rise/fall as a result of PWMO signal turning ON/OFF NMOS M 1 ;   LX=switching node potential;   VB=power supply voltage;   VOUT=boost converter output voltage.       
 
         [0073]    Equating together, we get: 
         [0000]      ( VB−LX )× NT ON=( V OUT− LX−VB )× PT ON  (3) 
         [0074]    Based on this relationship, with NTON (from PWM signal), VB and VOUT (input and output voltage sensing) known, we are able to turn OFF PMOS M 2  once Timer  102  has reached PTON, where PTON is given by: 
         [0000]        PT ON=(( VB−LX )× NT ON)/( V OUT− LX−VB )  (4) 
         [0075]    Note that LX can be ignored if the voltage across M 1  and M 2  are significantly small. 
         [0076]    Hence, for a case where the voltage across M 1  and M 2  are significantly small, 
         [0000]        PT ON=( VB×NT ON)/( V OUT− VB ) 
         [0077]    The above case applies for cases where the delay times to turn ON and OFF of NMOS M 1  and PMOS M 2  are insignificant. For cases where delay times are significantly large, these delay times need to be considered in the timing estimation. 
         [0078]    Case 1: Delay time to turn ON M 1  is significantly larger than delay time to turn ON M 2 . 
         [0079]    For this case, with the delay times known, just add the time difference to PTON. Hence, if delay time difference=T D1 , that means the formula shall now be: 
         [0000]        PT ON 1 ={( VB×NT ON)/( V OUT− VB )}+ T   D1   (5) 
         [0080]    Case 2: Delay time to turn ON M 1  is significantly smaller than delay time to turn ON M 2 . 
         [0081]    For this case, with the delay times known, just add the time difference to PTON. Hence, if delay time difference=T D2 , this means the formula shall now be: 
         [0000]        PT ON 1 ={( VB×NT ON)/( V OUT− VB )}− T   D2   (6) 
         [0082]    The formulae (5) and (6) above are meant to give more accurate timing estimations. Nevertheless, even if there is difference in timing estimation from actual, parasitic diode will be activated to discharge any remaining charges in the inductor  105 . Thus, depending on a case by case basis, the formulae need not be necessary to be implemented. 
         [0083]      FIG. 9A  shows a generic implementation  200  of the formula (4) based on the fourth preferred embodiment according to the present invention, whereby after a period of PTON defined by the above said formula, a signal PTIME is outputted to logic block  103 . 
         [0084]      FIG. 9B  shows one example of circuit implementation of the generic implementation  200  of Timer  102  for a synchronous boost converter based on the fifth preferred embodiment according to the present invention. During NTON, LOGICA closes switch  203  via line  206  and capacitor  205  will be charged up from VREF by Sense 1  block  201 . Sense 1  block is a typical V-I converter that sources a current proportional to VB. After NTON, LOGICA opens switch  203  via line  206  and closes switch  204  via line  207 . Capacitor  205  will be discharged by Sense 2  block  202 . Sense 2  block is a typical V-I converter that sinks a current proportional to (VOUT−VB). Once capacitor  205  has been discharged till VREF level, PTIME will go high or output a unique signal S B  to turn off the PMOS M 2 . LOGICA resets node VX to VREF via line  208 , to ensure the voltage level at VX is equal to VREF. 
         [0085]    Referring to  FIG. 9C , the operation of the circuit implementation of  FIG. 9B  shall be explained: 
         [0086]    When PWM signal, PWMO goes from low to high, correspondingly, NGATE goes to high, and node VX is charged up gradually from VREF by Sense 1  block  201 . After a period of NTON ends, the potential at node VX reduces due to discharge by Sense 2  block  202 . Once the node VX potential is reduced back to VREF, the comparator  209  will hence output a LOW signal, as an indication of its occurrence. Once LOGICA receives this LOW signal, LOGICA will output a PTIME high, causing both M 1  and M 2  to be off. At the next rising edge of PWMO, LOGICA causes PTIME to go back to logic signal LOW. The whole cycle then repeats. 
         [0087]    As mentioned, the above relationships apply for the case of a boost converter type of DCDC converter. For other DCDC converter types, the same principle may be used, but the relationships differ. 
         [0088]    We shall now describe the case for a synchronous buck converter. 
         [0089]      FIG. 10A  shows a typical output stage of a synchronous buck converter, with a sixth preferred embodiment  304  according to the present invention, as implemented in the DCDC Converter block  301 . We shall name the first preferred embodiment as the Intelligent Timing Block 2   304 . Block  304  outputs a signal to the input of driver  307  so as to control the ON and OFF state of NMOS M 4 . Block  304  obtains as inputs: A VOUT signal, a power supply voltage VB, and the PWM signal PWMO or any of its derivatives (e.g. inverted PWMO, delayed PWMO, etc). Block  304  will process the inputs and hence turn ON or OFF the NMOS M 4  so as to prevent any reverse current from occurring. An exemplary operation of the sixth embodiment according to the present invention is explained as follows: 
         [0090]    A case when PWM signal PWMO is high: 
         [0091]    The following explanation makes reference to  FIG. 10A  and selected important waveforms in  FIG. 11 . The driver  306  is actually an inverter. Hence, the output signal of driver  306  will be an inversion of its input. Hence, the gate terminal of PMOS M 3 , PGATE′, will be logic signal low. Thus, PMOS M 3  is ON. The period when PMOS M 3  is ON shall be referred to as period PTON′. At the same time, Intelligent Timing Block 2   304  is configured so that the input of driver  307  is low. The resultant low driver  307  output will thus cause the gate terminal of NMOS M 4 , NGATE′, to be low. Thus, NMOS M 4  will be OFF. As a result, Inductor  305  will be charged up (current rising) during this time. 
         [0092]    A case when PWM signal PWMO is low: 
         [0093]    The following explanation makes reference to  FIG. 10A  and selected important waveforms as shown in  FIG. 11 . The output signal of driver  306  will be an inversion of its input. Hence, the gate terminal of PMOS M 3  will be high. Thus, PMOS M 3  is OFF. At the same time, Intelligent Timing Block 2   304  is configured so that the input of driver  307  is also high. The resultant high driver  307  output will thus cause the gate terminal of NMOS M 4  to be high. Thus, NMOS M 4  will be ON. The period when NMOS M 4  is ON shall be referred to as period NTON′. Inductor  305  will be discharged (current falling) during this time. 
         [0094]    After a certain time (this timing will be further explained later), Block  304  will output a logic low. Thus, input of driver  307  being equal to its output, the gate of NMOS M 4  will thus be at a logic signal low. Thus, NMOS M 4  is OFF. During this OFF time, both PMOS M 3  and NMOS M 4  are OFF. This state is known as dead-time. Any current left in inductor will be discharged through parasitic diode. NMOS M 4  remains OFF until PWM signal PWMO goes low again to turn ON PMOS M 3  again. 
         [0095]      FIG. 10B  shows a seventh preferred embodiment according the present invention. The present invention comprises of the following elements: a Timer  302  which determines the ON time of NMOS M 4  and a logic block  303 . Together, these 2 elements shall collectively comprise the Intelligent Timing Block 2   304 . Next we shall explain the working of the seventh preferred embodiment according the present invention. 
         [0096]    A case when PWM signal PWMO is high: 
         [0097]    The following explanation makes reference to  FIG. 10B  and selected important waveforms as shown in  FIG. 11 . The output signal of driver  306  will be an inversion of its input. Hence, the gate terminal of PMOS M 3  will be logic signal low. Thus, PMOS M 3  is ON. The period when PMOS M 3  is ON is equal to PTON′. At the same time, Intelligent Timing Block 2   304  is configured so that the input of driver  307  is low. The resultant low driver output will thus cause the gate terminal of NMOS M 4  to be low. Thus, NMOS M 4  will be OFF. As a result, Inductor  305  will be charged up (current rising) during this time. 
         [0098]    A case when PWM signal PWMO is low: 
         [0099]    The following explanation makes reference to  FIG. 10B  and selected important waveforms in  FIG. 11 . The output signal of driver  306  will be an inversion of its input. Hence, the gate terminal of PMOS M 3  will be high. Thus, PMOS M 3  is OFF. At the same time, Intelligent Timing Block 2   304  is configured so that the input of driver  307  is high. The resultant high driver  307  output will thus cause the gate terminal PGATE of NMOS M 4  to be high. Thus, NMOS M 4  will be ON. The period when NMOS M 4  is ON is equal to NTON′. Inductor  305  will be discharged (current falling) during this time. 
         [0100]    The default signal at node PTIME′ is logic signal low or a first unique signal S A . The Timer  302  will give a logic signal high or a unique signal S B , via node PTIME′ after a certain time (this timing will be further explained later). PTIME′ at logic signal high or upon receiving S A , will cause the resultant output of logic block  303  to be low. Thus, input of driver  307  being equal to its output, PGATE will thus be at a logic signal low. Thus, NMOS M 4  is OFF. During this OFF time, both PMOS M 3  and NMOS M 4  are OFF. This state is known as dead-time. Any current left in inductor will be discharged through parasitic diode. NMOS M 4  remains OFF until PWM signal PWMO goes high again to turn ON PMOS M 3  again. 
         [0101]      FIG. 10C  shows a eighth preferred embodiment according the present invention. Logic block  303  may be implemented using a NOR gate. 
         [0102]    Above is the case for DCM operation. Under the CCM operation, the invention does not cause any undesirable effects. The explanation is as follows: 
         [0103]    Referring to  FIGS. 10B and 12 , if PMOS M 3  turns ON again before Timer  302  can give a logic signal high, there is no instance where both PMOS M 3  and NMOS M 4  are OFF (no dead-time). Moreover, reverse current does not occur for a CCM operation. This means that the Timer  302  will not give a logic signal high or a unique signal S B , via node PTIME′. Hence, the Intelligent Timing Block 2   304 , according to the present invention, does not have any effect on the CCM operation. 
         [0104]    An explanation of the time duration to determine the sequence of turning ON to OFF of NMOS M 4  shall be given as follows: 
         [0105]    Referring to  FIG. 11 , for a buck converter type of DCDC converter, current ripple across inductor is calculated based on NMOS and PMOS ON times as follows: 
         [0000]      Δ I =(( VB−LX−V OUT)× PT ON′)/ L out( PMOS ON)  (7) 
         [0000]      Δ I =(( V OUT− LX )× NT ON′)/ L out( NMOS ON)  (8) 
         [0106]    Equating together, we get: 
         [0000]      ( V OUT− LX )× NT ON′=( VB−LX−V OUT)× PT ON′  (9) 
         [0107]    where
       NTON′=time for which NMOS M 4  is turned ON;   PTON′=time for which PMOS M 3  is turned ON;   ΔI=Inductor current rise/fall as a result of PWMO signal turning ON/OFF PMOS M 3 ;   VB=power supply voltage;   VOUT=buck converter output voltage.       
 
         [0113]    Based on this relationship, with PTON′ (from PWM signal), VB and VOUT (input and output voltage sensing) known, we are able to turn OFF NMOS M 4  once Timer  302  has reached NTON′, where NTON′ is given by: 
         [0000]        NT ON′=(( VB−LX−V OUT)/( V OUT− LX ))× PT ON′  (10) 
         [0114]    Note that LX can be ignored if the voltage across M 3  and M 4  are significantly small. 
         [0115]    Hence, for a case where the voltage across M 3  and M 4  are significantly small, 
         [0000]        NT ON′=(( VB−V OUT)/ V OUT)× PT ON′ 
         [0116]    The above case applies for cases where the delay times to turn ON and OFF of PMOS M 3  and NMOS M 4  are insignificant. For cases where delay times are significantly large, these delay times need to be considered in the timing estimation. 
         [0117]    Case 1: Delay time to turn ON M 3  is significantly larger than delay time to turn ON M 4 . 
         [0118]    For this case, with the delay times known, just add the time difference to NTON′. Hence, if delay time difference=T D3 , this means the formula shall now be: 
         [0000]        NT ON′=(( VB−V OUT)/ V OUT)× PT ON′+ T   D3   (11) 
         [0119]    Case 2: Delay time to turn ON M 3  is significantly smaller than delay time to turn ON M 4 . 
         [0120]    For this case, with the delay times known, just add the time difference to NTON′. Hence, if delay time difference=T D4 , this means the formula shall now be: 
         [0000]        NT ON′=(( VB−V OUT)/ V OUT)× PT ON′− T   D4   (12) 
         [0121]    The formulae (11) and (12) above are meant to give more accurate timing estimations. Nevertheless, even if there is difference in timing estimation from actual, parasitic diode will be activated to discharge any remaining charges in the inductor  305 . Thus, depending on a case by case basis, the formulae need not be necessary to be implemented. 
         [0122]      FIG. 13A  shows a generic implementation  400  of the formula (10) based on the ninth preferred embodiment according to the present invention, whereby after a period of NTON′ defined by the above said formula, a signal PTIME′ is outputted to logic block  303 . 
         [0123]      FIG. 13B  shows one example of circuit implementation of Timer  302  for a synchronous buck converter based on the tenth preferred embodiment according to the present invention. During PTON′, LOGICB closes switch  403  via line  406  and capacitor  405  will be charged up from VREF by Sense 1  block  401 . Sense 1  block is a typical V-I converter that sources a current proportional to (VB−VOUT). After PTON′, LOGICB opens switch  403  via line  406  and closes switch  404  via line  407 . Capacitor  405  will be discharged by Sense 2  block  402 . Sense 2  block is a typical V-I converter that sinks a current proportional to (VOUT). Once capacitor  405  has been discharged till VREF level, PTIME′ will go high or output a unique signal S B  to turn off the NMOS M 4 . LOGICB resets node VX to VREF via line  408 , to ensure the voltage level at VX is equal to VREF. 
         [0124]    Referring to  FIG. 13C , the operation of the circuit implementation of  FIG. 13B  shall be explained: 
         [0125]    When PWM signal, PWMO goes from low to high, correspondingly, PGATE goes to low, and node VX is charged up gradually from VREF by Sense 1  block  401 . After a period of PTON′ ends, the potential at node VX reduces due to discharge by Sense 2  block  402 . Once the node VX potential is reduced back to VREF, the comparator  409  will hence output a LOW signal, as an indication of its occurrence. Once LOGICB receives this LOW signal, LOGICB will output a PTIME′ will go high, causing both M 3  and M 4  to be off. At the next rising edge of PWMO, LOGICB causes PTIME′ to go back to logic signal LOW. The whole cycle then repeats. 
         [0126]    The above-described disclosure of the invention in terms of the presently preferred embodiments is not to be interpreted as intended for limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art to which the invention pertains, after having read the disclosure. As a corollary to that, such alterations and modifications apparently fall within the true spirit and scope of the invention. Furthermore, it is to be understood that the appended claims be intended as covering the alterations and modifications.