Abstract:
A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.

Description:
GOVERNMENT SUPPORT 
       [0001]    This invention was made with government funds under contract number 11-D-5309 awarded by the Department of Defense and contract number FA8650-11-2-5507 awarded by the United States Air Force. The U.S. Government may have rights in this invention. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The present disclosure relates to semiconductor devices including one or more film layers configured to reduce stress in the device. 
       BACKGROUND 
       [0003]    Semiconductor devices generally include multiple film layers. Often, differing material properties of the separate film layers generate stress in the semiconductor device, which may lead to a decrease in performance or even failure of the device. One form of stress in semiconductor devices is generated when film layers that are placed adjacent to one another have different thermal coefficients. In such a case, as the ambient temperature changes, one film layer may expand and/or contract more than an adjacent layer, thereby causing undesirable cracking, buckling, wafer bowing, or piezo-electric effects in the semiconductor device. 
         [0004]      FIG. 1  shows a conventional semiconductor device  10  including a substrate  12 , a dielectric crossover layer  14 , and an encapsulation layer  16 . The substrate  12  includes a first surface  18 , which is used to support and connect one or more electrical components (not shown). The dielectric crossover layer  14  is located between the first surface  18  of the substrate  12  and the encapsulation layer  16 . The dielectric crossover layer includes a dielectric surface  20 , which is used to support a number of crossovers  22 , such as a first crossover  22 A and a second crossover  22 B. 
         [0005]    The first crossover  22 A may include the dielectric crossover layer  14 , a first conductive trace  24 , and a second conductive trace  26 . The second crossover  22 B may include the dielectric crossover layer  14 , the second conductive trace  26 , and a third conductive trace  28 . In the first crossover  22 A, the first conductive trace  24  may be a crossover trace, while the second conductive trace  26  may be a surface trace, such that the first conductive trace  24  crosses over the second conductive trace  26  on the dielectric surface  20  of the dielectric crossover layer  14 . In the second crossover  22 B, the second conductive trace  26  may be a crossover trace, while the third conductive trace  28  may be a surface trace, such that the second conductive trace  26  crosses over the third conductive trace  28  on the dielectric surface  20  of the dielectric crossover layer  14 . The solid lines shown in  FIG. 1  represent the portion of the first conductive trace  24  and the second conductive trace  26  located on the dielectric surface  20  of the dielectric crossover layer  14 , while the dotted lines represent the portions of the first conductive trace  24 , the second conductive trace  26 , and the third conductive trace  28  located below the dielectric surface  20  of the dielectric crossover layer  14 . 
         [0006]      FIG. 2  shows details of the first crossover  22 A, which includes a portion of the dielectric crossover layer  14 , the first conductive trace  24 , and the second conductive trace  26 . As discussed above, the first conductive trace  24  is a crossover trace, which crosses over the second conductive trace  26  on the dielectric surface  20  of the dielectric crossover layer  14 , while the second conductive trace  26  is a surface trace, which runs under the first conductive trace  24  on the first surface  18  of the substrate  12 . Specifically, the first conductive trace  24  is partially disposed on the first surface  18  of the substrate  12  and the dielectric surface  20  of the dielectric crossover layer  14 , such that the first conductive trace  24  crosses over the second conductive trace  26  on the dielectric surface  20 . Notably, the dielectric crossover layer  14 , which separates the first conductive trace  24  and the second conductive trace  26  to prevent contact between the two, is a blanket layer that substantially extends over the periphery of the first surface  18  of the substrate  12 . Accordingly, the solid lines shown in  FIG. 2  represent the portion of the first conductive trace  24  located on the dielectric surface  20  of the dielectric crossover layer  14 , while the dotted lines represent the portions of the first conductive trace  24  and the second conductive trace  26  located below the dielectric surface  20  of the dielectric crossover layer  14 . 
         [0007]    Although effective at supporting the first crossover  22 A and the second crossover  22 B in the conventional semiconductor device  10 , the dielectric crossover layer  14  often generates stress in the semiconductor device. This may be, for example, due to the fact that the dielectric crossover layer  14  and the encapsulation layer  16  are blanket layers that often have divergent thermal coefficients. As discussed above, the dielectric crossover layer  14  or the encapsulation layer  16  may thus expand and/or contract more than the other, thereby leading to undesirable cracking, buckling, wafer bowing, or piezo-electric effects in the semiconductor device which may lead to a decrease in performance or even failure of the device. 
         [0008]    As feature sizes in semiconductor devices decrease and wafer sizes increase, stress in the semiconductor device becomes increasingly problematic. Accordingly, there is a need for a semiconductor device with reduced stress between the film layers therein. 
       SUMMARY 
       [0009]    The present disclosure relates to a semiconductor device configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device. 
         [0010]    By providing a discontinuous dielectric layer that is broken into one or more dielectric sections, stress between the substrate and the dielectric layer, as well as stress between the encapsulation layer and the dielectric layer, is localized to each one of the dielectric sections, thereby reducing the overall stress in the semiconductor device. 
         [0011]    According to one embodiment, the dielectric layer is a dielectric crossover layer for supporting one or more crossovers in the semiconductor device. 
         [0012]    According to one embodiment, the semiconductor device includes a substrate and one or more crossovers. Each one of the crossovers may include a surface trace on a first surface of the substrate, a dielectric crossover section covering a portion of the surface trace and having a dielectric surface opposite the first surface of the substrate, and a crossover trace partially disposed on a portion of the surface of the substrate and a portion of the dielectric surface, such that the crossover trace crosses over the surface trace on the dielectric surface. Notably, each dielectric crossover section of each of the one or more crossovers forms a discontinuous dielectric crossover layer in order to reduce stress in the semiconductor device. 
         [0013]    According to one embodiment, the first surface of the substrate and the crossovers are covered by a substantially continuous encapsulation layer. 
         [0014]    According to one embodiment, a method of manufacturing the semiconductor device begins by providing a substrate. A surface trace is then provided on a first surface of the substrate. A dielectric crossover layer is provided over the first surface of the substrate and the surface trace, and subsequently etched to form one or more dielectric crossover sections having a dielectric surface opposite the first surface of the substrate, such that each of the one or more dielectric crossover sections forms a discontinuous dielectric crossover layer. Finally, a crossover trace is provided on a portion of the first surface of the substrate and the dielectric surface of one of the dielectric crossover sections, such that the crossover trace crosses over the surface trace on the dielectric surface. 
         [0015]    According to one embodiment, the first surface of the substrate and the crossovers are covered by a substantially continuous encapsulation layer. 
         [0016]    Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         [0017]    The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
           [0018]      FIG. 1  shows a three-dimensional representation of a conventional semiconductor device including one or more film layers. 
           [0019]      FIG. 2  shows an expanded view of a conventional crossover shown in the conventional semiconductor device of  FIG. 1 . 
           [0020]      FIG. 3  shows a three-dimensional representation of a semiconductor device according to one embodiment of the present disclosure. 
           [0021]      FIG. 4  shows a flow diagram illustrating a method for manufacturing the semiconductor device of  FIG. 3  according to one embodiment of the present disclosure. 
           [0022]      FIG. 5  shows an expanded view of a crossover shown in the semiconductor device of  FIG. 3 . 
           [0023]      FIG. 6  shows a three-dimensional representation of a semiconductor device according to an additional embodiment of the present disclosure. 
           [0024]      FIG. 7  shows a cross-sectional representation of a semiconductor device according to an additional embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0026]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0027]    It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
         [0028]    Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
         [0029]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0030]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0031]    Turning now to  FIG. 3 , a semiconductor device  30  is shown according to one embodiment of the present disclosure. The semiconductor device  30  includes a substrate  32 , a discontinuous dielectric crossover layer  34 , and an encapsulation layer  36 . The substrate  32  includes a first surface  38 , which is used to support and connect one or more electrical components (not shown). The discontinuous dielectric crossover layer  34  is located between the first surface  38  of the substrate  32  and the encapsulation layer  36 . Further, the discontinuous dielectric crossover layer  34  is broken into a number of dielectric crossover sections  42 , each of which includes a dielectric surface  40  opposite the first surface  38  of the substrate  32  and used to support one or more crossovers  44 , such as a first crossover  44 A and a second crossover  44 B. 
         [0032]    The first crossover  44 A may include a first dielectric crossover section  42 A, a first conductive trace  46 , and a second conductive trace  48 . The second crossover  44 B may include the second conductive trace  48 , a second dielectric crossover section  42 B, and a third conductive trace  50 . In the first crossover  44 A, the first conductive trace  46  may be a crossover trace, while the second conductive trace  48  may be a surface trace, such that the first conductive trace  46  crosses over the second conductive trace  48  on the dielectric surface  40  of the first dielectric crossover section  42 A. In the second crossover  44 B, the second conductive trace  48  may be a crossover trace, while the third conductive trace  50  may be a surface trace, such that the second conductive trace  48  crosses over the third conductive trace  50  on the dielectric surface  40  of the second dielectric crossover section  42 B. 
         [0033]    The first conductive trace  46 , the second conductive trace  48 , and the third conductive trace  50  may form or connect one or more electrical components (not shown) on the first surface  38  of the substrate  32 . Although only three conductive traces are shown in  FIG. 1 , those of ordinary skill in the art will appreciate that the principles of the present disclosure are applicable to a semiconductor device having any number of conductive traces. 
         [0034]    In some embodiments, each of the dielectric crossover sections  42  of the discontinuous dielectric crossover layer  34  are confined to the immediate vicinity of the crossover which they support, as will be discussed in further detail below. By breaking the discontinuous dielectric crossover layer  34  into a plurality of dielectric crossover sections  42 , stress caused by the interaction between the substrate  32  and the discontinuous dielectric crossover layer  34  or between the encapsulation layer  36  and the discontinuous dielectric crossover layer  34  is localized to each one of the dielectric crossover sections  42 . Accordingly, the overall stress within the semiconductor device  30  is substantially reduced. 
         [0035]      FIG. 4  is a flow diagram illustrating a method for manufacturing a dielectric crossover, such as the first crossover  44 A shown in  FIG. 3 . First, a substrate (such as the substrate  32 ) is provided (step  100 ). Next, a surface trace (such as the first conductive trace  46 ) is provided on a first surface of the substrate (step  102 ). This may be done, for example, by providing a metal layer on the first surface of the substrate, then etching the metal layer to form the surface trace. A dielectric crossover layer (such as dielectric crossover layer  34 ) is then provided over the surface trace and the first surface of the substrate (step  104 ). The dielectric crossover layer is then etched to form one or more dielectric crossover sections (such as dielectric crossover section  42 A). Each dielectric crossover section may include a dielectric surface opposite the first surface of the substrate (step  106 ). Finally, a crossover trace (such as the second conductive trace  48 ) is provided on a portion of the first surface of the substrate and a portion of the dielectric surface of one of the dielectric crossover sections, such that the crossover trace crosses over the surface trace on the dielectric surface. 
         [0036]      FIG. 5  shows details of the first crossover  44 A shown in  FIG. 3  according to one embodiment of the present disclosure. The first crossover  44 A includes the first dielectric crossover section  42 A, the first conductive trace  46 , and the second conductive trace  48 . As discussed above, the first conductive trace  46  is a crossover trace, which crosses over the second conductive trace  48  on the dielectric surface  40  of the first dielectric crossover section  42 A, while the second conductive trace  48  is a surface trace, which runs under the first conductive trace  46  on the first surface  38  of the substrate  32 . Specifically, the first conductive trace  46  is partially disposed on the first surface  38  of the substrate  32  and the dielectric surface  40  of the first dielectric crossover section  42 A, such that the first conductive trace  46  crosses over the second conductive trace  48  on the dielectric surface  40 . Notably, the first dielectric crossover section  42 A, which separates the first conductive trace  46  and the second conductive trace  48  to prevent contact between the two, is a discrete section that is confined to the immediate vicinity of the first crossover  44 A. Accordingly, the solid lines shown in  FIG. 5  represent the portion of the first conductive trace  46  and the second conductive trace  48  located outside of the first dielectric crossover section  42 A, while the dotted lines represent the portion of the second conductive trace  48  covered by the first dielectric crossover section  42 A. 
         [0037]    According to one embodiment, the first dielectric crossover section  42 A is defined by a termination length  52 A and a termination width  52 B, which extend less than 15 microns beyond the confines of the area where the first conductive trace  46  crosses over the second conductive trace  48 . By confining each one of the dielectric crossover sections  42  to the immediate vicinity of the crossover  44  supported by the dielectric crossover section  42 , stress generated between the substrate  32  and the discontinuous dielectric crossover layer  34 , as well as stress generated between the encapsulation layer  36  and the discontinuous dielectric crossover layer  34 , is effectively localized to the area of each one of the dielectric crossover sections  42 , thereby substantially reducing the overall stress in the semiconductor device  30 . 
         [0038]    According to one embodiment, the discontinuous dielectric crossover layer  34  occupies less than 10% of the area of the first surface  38  of the substrate  32 . According to an additional embodiment, the discontinuous dielectric crossover layer  34  occupies less than 5% of the area of the first surface  38  of the substrate  32 . By reducing the total area occupied by the discontinuous dielectric crossover layer  34 , stress generated between the substrate  32  and the discontinuous dielectric crossover layer  34 , as well as stress generated between the encapsulation layer  36  and the discontinuous dielectric crossover layer  34 , is localized to the regions where the substrate  32  and the encapsulation layer  36  contact the discontinuous dielectric crossover layer  34 , thereby substantially reducing the overall stress in the semiconductor device  30 . 
         [0039]    According to one embodiment, the substrate  32  comprises silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like. The discontinuous dielectric crossover layer  34  may comprise polyimide or a similar dielectric material suitable for supporting the one or more crossovers  44 . The encapsulation layer  36  may comprise ceramic or a similar material suitable for protecting the semiconductor device  30  from one or more environmental conditions. 
         [0040]    While only two conductive traces are shown in the first crossover  44 A, those of ordinary skill in the art will appreciate that each one of the dielectric crossover sections  42  may support any number of crossover traces or surface traces without departing from the principles of the present disclosure, as illustrated in detail below. Further, although the concepts of the present disclosure are described above with reference to a substrate  32 , a discontinuous dielectric crossover layer  34 , and an encapsulation layer  36 , those of ordinary skill in the art will appreciate that the principles of the present disclosure may be applied to any semiconductor layer capable of generating stress in the device. 
         [0041]      FIG. 6  shows a semiconductor device  54  according to an additional embodiment of the present disclosure. The semiconductor device  54  includes a substrate  56 , a discontinuous dielectric crossover layer  58 , and an encapsulation layer  60 . The substrate  56  includes a first surface  62 , which is used to support and connect one or more electrical components (not shown). The discontinuous dielectric crossover layer  58  is located between the first surface  62  of the substrate  56  and the encapsulation layer  60 . Further, the discontinuous dielectric crossover layer  58  is broken into a number of dielectric crossover sections  64 , each of which includes a dielectric surface  66  opposite the first surface  62  of the substrate  56  and used to support one or more crossovers  68 , such as a first crossover  68 A and a second crossover  68 B. 
         [0042]    As discussed above, each one of the dielectric crossover sections  64  may support a plurality of conductive traces. To illustrate this fact, the first crossover  68 A is shown including a first dielectric crossover section  64 A, a first conductive trace  70 , a second conductive trace  72 , and a third conductive trace  74 . The second crossover  68 B may include a second dielectric crossover section  64 B, the third conductive trace  74 , and a fourth conductive trace  76 . In the first crossover  68 A, the first conductive trace  70  and the second conductive trace  72  may be crossover traces, while the third conductive trace  74  may be a surface trace, such that that first conductive trace  70  and the second conductive trace  72  cross over the third conductive trace  74  on the dielectric surface  66  of the first dielectric crossover section  64 A. Accordingly, the first dielectric crossover section  64 A supports more than one crossover trace in the present embodiment. In the second crossover  68 B, the third conductive trace  74  may be a crossover trace, and the fourth conductive trace  76  may be a surface trace, such that the third conductive trace  74  crosses over the fourth conductive trace  76  on the dielectric surface  66  of the second dielectric crossover section  64 B. 
         [0043]    According to one embodiment, the first dielectric crossover section  64 A extends less than 15 microns beyond the confines of the area wherein the first conductive trace  70  and the second conductive trace  72  cross over the third conductive trace  74 . By confining each one of the dielectric crossover sections  64  to the immediate vicinity of the crossover  68  supported by the dielectric crossover section  64 , stress generated between the substrate  56  and the discontinuous dielectric crossover layer  58 , as well as stress generated between the encapsulation layer  60  and the discontinuous dielectric crossover layer  58 , is effectively localized to the area of each one of the dielectric crossover sections  64 , thereby substantially reducing the overall stress in the semiconductor device  54 . 
         [0044]    According to one embodiment, the discontinuous dielectric crossover layer  58  occupies less than 10% of the area of the first surface  62  of the substrate  56 . According to an additional embodiment, the discontinuous dielectric crossover layer  58  occupies less than 5% of the area of the first surface  62  of the substrate  56 . By reducing the total area occupied by the discontinuous dielectric layer, stress generated between the substrate  56  and the discontinuous dielectric crossover layer  58 , as well as stress generated between the encapsulation layer  60  and the discontinuous dielectric crossover layer  58 , is effectively localized to the area of each one of the dielectric crossover sections  64 , thereby substantially reducing the overall stress in the semiconductor device  54 . 
         [0045]    According to one embodiment, the substrate  56  comprises silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like. The discontinuous dielectric crossover layer  58  may comprise polyimide or a similar dielectric material suitable for supporting the one or more crossovers  68 . The encapsulation layer  60  may comprise ceramic or a similar material suitable for protecting the semiconductor device  54  from one or more environmental conditions. 
         [0046]    While only three conductive traces are shown in the first crossover  68 A, those of ordinary skill in the art will appreciate that each one of the dielectric crossover sections  64  may support any number of crossover traces or surface traces without departing from the principles of the present disclosure. Further, although the concepts of the present disclosure are described above with reference to a substrate  56 , a discontinuous dielectric crossover layer  58 , and an encapsulation layer  60 , those of ordinary skill in the art will appreciate that the principles of the present disclosure may be applied to any semiconductor layer capable of generating stress in the device. 
         [0047]      FIG. 7  shows a semiconductor device  78  according to an additional embodiment of the present disclosure. The semiconductor device  78  includes a substrate  80 , a discontinuous dielectric crossover layer  82 , and an encapsulation layer  84 . The substrate  80  includes a first surface  86 , which is used to support and connect one or more electrical components, such as a spiral inductor  88 . The discontinuous dielectric crossover layer  82  is broken into a number of dielectric crossover sections  90 , each of which includes a dielectric surface  92  opposite the first surface  86  of the substrate  80  and used to support one or more crossovers  94 , such as a first crossover  94 A and a second crossover  94 B. 
         [0048]    In the embodiment shown in  FIG. 7 , a first conductive trace  96  and a second conductive trace  98  form the spiral inductor  88  on the first surface  86  of the substrate  80 . Accordingly, the first conductive trace  96  may be arranged in a spiral configuration, with the second conductive trace  98  forming an interconnect between the innermost portion of the spiral and an external connection point, such that a first dielectric crossover section  90 A supports the second conductive trace  98  as it crosses over each one of the spiraling portions of the first conductive trace  96 . The first conductive trace  96  and the second conductive trace  98  may further cross over a third conductive trace  100 . Accordingly, a second dielectric crossover section  90 B may support the first conductive trace  96  and the second conductive trace  98  as they cross over the third conductive trace  100 . 
         [0049]    According to one embodiment, the first dielectric crossover section  90 A extends less than 15 microns beyond the confines of the area wherein the second conductive trace  98  crosses over the first conductive trace  96 . By confining each one of the dielectric crossover sections  90  to the immediate vicinity of the crossover  94  supported by the dielectric crossover section  90 , stress generated between the substrate  80  and the discontinuous dielectric crossover layer  82 , as well as stress generated between the encapsulation layer  84  and the discontinuous dielectric crossover layer  82 , is effectively localized to the area of each one of the dielectric crossover sections  90 , thereby substantially reducing the overall stress in the semiconductor device  78 . 
         [0050]    According to one embodiment, the discontinuous dielectric crossover layer  82  occupies less than 10% of the area of the first surface  86  of the substrate  80 . According to an additional embodiment, the discontinuous dielectric crossover layer  82  occupies less than 5% of the area of the first surface  86  of the substrate  80 . By reducing the total area occupied by the discontinuous dielectric crossover layer  82 , stress generated between the substrate  80  and the discontinuous dielectric crossover layer  82 , as well as stress generated between the encapsulation layer  84  and the discontinuous dielectric crossover layer  82 , is effectively localized to the area of each one of the dielectric crossover sections  90 , thereby substantially reducing the overall stress in the semiconductor device  78 . 
         [0051]    According to one embodiment, the substrate  80  comprises silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like. The discontinuous dielectric crossover layer  82  may comprise polyimide or a similar dielectric material suitable for supporting the one or more crossovers  94 . The encapsulation layer  84  may comprise ceramic or a similar material suitable for protecting the semiconductor device  78  from one or more environmental conditions. 
         [0052]    Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.