Abstract:
A protection circuit for protecting a dimmer circuit controlling an inductive load including an imbalance detector for detecting an asymetrical operation in the load and circuit control means for causing the dimmer circuit to reduce a DC component in the load upon detection of the asymetrical operation. A load imbalance detector is also disclosed having a load DC component detector, a comparator and a signal generating means for generating means for generating a circuit shut down signal if the DC component exceeds a pre-set DC threshold.

Description:
TECHNICAL FIELD  
       [0001]     This invention relates to circuit arrangements for controlling the power provided to a load and in particular, to dimmer circuits for controlling, for example, the luminosity of a light or the speed of a fan.  
       BACKGROUND TO THE INVENTION  
       [0002]     Dimmer circuits are used to control the power provided to a load such as a light or electric motor from a power source such as mains. Such circuits often use a technique referred to as phase controlled dimming. This allows power provided to the load to be controlled by varying the amount of time that a switch connecting the load to the power source is conducting during a given cycle.  
         [0003]     For example, if voltage provided by the power source can be represented by a sine wave, then maximum power is provided to the load if the switch connecting the load to the power source is on at all times. In this way the, the total energy, of the power source is transferred to the load. If the switch is turned off for a portion of each cycle (both positive and negative), then a proportional amount of the sine wave is effectively isolated from the load, thus reducing the average energy provided to the load. For example, if the switch is turned on and off half way through each cycle, then only half of the power will be transferred to the load. Because these types of circuits are often used with resistive loads and not inductive loads, the effect of repeatedly switching on and off power will not be noticeable as the resistive load has an inherent inertia to it. The overall effect will be, for example in the case of a light, a smooth dimming action resulting in the control of the luminosity of the light. This technique will be well understood by the person skilled in the art.  
         [0004]     A power semiconductor in the form of a triac is typically the principal load controlling device in phase control dimming applications. Such a device offers advantages of relatively low conduction losses and high robustness, but has the disadvantage of operating sensitivity to load type.  
         [0005]     When controlling magnetically saturable inductive load types including electric fan motors and particularly iron core transformer based low voltage lighting, asymmetrical dimmer conduction may result. With these load types triac latching into the conducting state mar occur only in one half cycle polarity due to the presence of magnetic asymmetry in the load. Once this condition has commenced, it is generally sustained as the asymmetric load impedance condition becomes exacerbated. A severe reduction in load inductance for one half cycle polarity results in a corresponding high level DC current component. This can rapidly lead to overheating of primary windings of the transformer.  
         [0006]     Generally, dimmer units specified for use with inductive loads require the use of very sensitive triacs so that the likelihood of asymmetrical operation is reduced. Sensitive triacs axe comparatively less robust and therefore not as suitable for universal dining applications.  
         [0007]     It is therefore an object of the present invention to provide an alternative method and apparatus for addressing load imbalance conditions.  
       SUMMARY OF THE INVENTION  
       [0008]     According to a first aspect of the present invention, there is provided a protection circuit for protecting a dimmer circuit controlling an inductive load, the protection circuits including: an imbalance detector for detecting an asymmetrical operation in the load; and circuit shut-off means for causing the dinner circuit to stop operating upon detection of the asymmetrical operation.  
         [0009]     According to a second aspect of the present invention, there is provided a load imbalance detector for use in a dimmer circuit controlling an inductive load, including: a load DC component detector to detect a DC component in the load; a comparator for comparing a magnitude of the DC component detected by the load DC component detector with a reference voltage; and a signal generating means for generating a circuit shut-own signal if the DC component exceeds a pre-set DC voltage threshold above the referenced voltage.  
         [0010]     Preferably, the load DC component detector detects a DC sub-component in a positive cycle and detects a DC sub-component in a negative cycle and wherein said magnitude of the DC component is the difference between the respective DC sub-components.  
         [0011]     Preferably, the load DC component detector includes a first resistor divider chain for detecting said DC sub-component in the positive cycle and a second resistor divider chain for detecting said DC sub-component in the negative cycle and wherein a divider junction of the first chain is connected to a first side of a capacitor and a divider junction of the second cha is connected to a second side of the capacitor, a voltage across which provides said magnitude of the DC component.  
         [0012]     Preferably, the comparator includes a first pnp transistor having its base connected to said first side of said capacitor and its emitter connected to said second side of said capacitor and a second pnp transistor having its base connected to said second side of said capacitor and its emitter connected to said first side of said capacitor and each respective collector connected to an input of said signal generating means.  
         [0013]     Alternatively, the imbalance detector detect a difference between the conduction period of consecutive positive and negative half cycles. Preferably, the imbalance detector will register a load imbalance if the difference between the consecutive positive and negative half cycles exceeds a preset threshold.  
         [0014]     Preferably, the circuit control means causes the dimmer circuit to shut down.  
         [0015]     Optionally, the circuit control means causes the dimmer circuit to reduce a conduction angle of the dimmer circuit to a point where the DC component reduces to below a preset threshold.  
         [0016]     The invention therefore eliminates the need for traditional methods of attempting to reduce the likelihood of load imbalance using expensive components. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]      FIG. 1  shows a first embodiment of the dimmer circuit of the present invention;  
         [0018]      FIG. 2  shows an alternative arrangement of the triac control circuit portion of  FIG. 1 ;  
         [0019]      FIG. 3  shows a current switch control circuit which may be used as a alternative to the voltage switch control circuit of  FIGS. 1 and 2 ;  
         [0020]      FIG. 4  shows a simplified block diagram of the circuit of  FIG. 1 ; and  
         [0021]      FIG. 5  shows an alternative arrangement for the impedance load imbalance detector portion of  FIG. 1 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0022]     A preferred circuit design of a 2-wire, leading edge phase control light dimmer/fan speed controller is shown in  FIG. 1 . The design shown in  FIG. 1  is particularly effective in that it is electromagnetic compatible (EMI compliant). This refers to the amount of electromagnetic interference EMI) that is generated by the circuit. The amount of radiation generated by dimming circuits due to the high frequency switching of the circuit is heavily regulated and such circuits must not exceed the regulated level of EMI.  
         [0023]     The circuit design of  FIG. 1  controls the level of EMI generated by the circuit via active control of the rate of rise of load voltage at each main half cycle. A power semiconductor in the form of an IGBT is used for this function. The IGBT and associated drive control circuitry is connected to the DC side of a diode bridge to allow control of polarities of mains voltage.  
         [0024]     A power triac is used to handle the load current once the IGBT has performed the required slow switching function. This reduces power dissipation to a minimum since it has an on-state voltage lower than that of the IGBT/bridge conduction voltage.  
         [0025]     The IGBT circuit of  FIG. 1  can be separated into the following blocks: 
        low voltage DC power rail     main voltage zero cross detector     power up drive inhibit     control timing     IGBT gate drive        
 
         [0031]     Power for the IGBT control circuit is derived from mains via the load, in each half cycle during the time period before IGBT operation commences, ie. while mains voltage appears across the dimmer. Overall current consumption is long enough to allow the use of a relatively low dissipation resistive chain provided by R 1 , R 2 , R 4  and R 5 . A smoothing capacitor, C 9  stores enough charge provided at the start of each half cycle to provide circuit current for the remaining period, with relatively low ripple voltage. Excess supply current is shunted by voltage regulating zener diode DZ 1  with the resultant of nominal DC power rail of 15 volts. This arrangement provides the low voltage DC power rail block referred to above.  
         [0032]     The mains voltage zero cross detector resets the control timing circuit (described in more detail below) in each half cycle after load current commences. Timing is allowed to start again when mains voltage reappears across the circuit in the following half cycle. For resistive loads this will correspond to mains voltage zero crossing. For inductive loads however, this corresponds to load current zero crossing, which occurs later than mains voltage zero crossing.  
         [0033]     Transistor Q 2  with its emitter connected to the DC rail, has its base driven by the power supply voltage dropping resistor chain described above. The collector pulls “sync” high whenever the voltage across the dimmer circuit is below the DC rail voltage. Conversely, when mains voltage exists across the dimmer circuit, transistor Q 2  base emitter junction is reverse biased, preventing the collector from pulling up. During this time supply current is delivered to the DC rail via base-emitter shunting diode D 4 .  
         [0034]     Reset of the controlled timing capacitor C 7  is performed by discharge transistor Q 12 , which is driven by limiting resistor R 21  from “sync” output of Q 2 . Transistor Q 12  has base-emitter bypassed resistor R 22  and capacitor C 6  to reduce off-state leakage and to enhance EFT immunity.  
         [0035]     The function of the power-up drive inhibit block is to inhibit the operation of the dimmer circuit for the first few main half cycles at power-up by temporarily by-passing passing the control timing capacitor C 7  charging current. This is required to enable correct operation of the soft-start mechanism, which relies on an established DC voltage reference to function. A small capacitor C 1 , effectively connected to the DC rail, provides a current via diode D 3  to drive discharge transistor Q 12  during the period while the rail is rising at power-up. Blocking diode D 3  isolates C 1  from Q 12  drive circuit once C 1  has become completely charged after the power-up event. Resistor R 8  thereafter serves to hold C 1  in the fully charged state, in addition to providing a discharge path at power off.  
         [0036]     The control timing block is used to provide the dimmer circuit with immunity to mains voltage ripple injection.  
         [0037]     At the start of each half cycle, timing capacitor C 7  charges via mains/load through current limiting resistors R 6  and R 7 . A reference voltage determined by zener diode DZ 4 , sourced by resistor R 39 , is used as a charge threshold level for terminating the timing process. The voltage on the positive side of C 7  must always reach a level of approximately two diode drops above this reference level, as determined by series connected diode D 5  and transistor Q 4 , in order to initiate IGBT operation. At the pre-defined threshold voltage, the timing capacitor charging current is diverted to transistor Q 4  in order to operate the IGBT drive control stage.  
         [0038]     Adjustment of control firing angle is facilitated by a variable control voltage source connecting to the negative side of the timing capacitor. This control volt is derived from zener diode DZ 4  referenced voltage using main dimmer control, potentiometer VR 1 . An RC filter made up of R 28  and C 13  provides a soft-start feature at power up due to the zero initial capacitor voltage condition. Buffering of the filtered control voltage is performed by cascaded transistors Q 3  and Q 15  to provide a low impedance source voltage. Resistor R 36  bypasses the base-emitter of transistor Q 15  to reduce leakage effects.  
         [0039]     At the maximum control voltage (for maximum dimmer conduction angle), the required timing capacitor charging voltage is at its lowest. The minimum required timing capacitor char voltage is equal to one forward voltage diode drop, as determined by diode D 5 , in addition to a small voltage across resistor R 11 . This level is independent of the absolute value of the zener diode DZ 4  reference voltage. Consequently, the maximum conduction angle is inherently limited, being largely independent of component parameters, thus ensuring sufficient current is always available to supply the DC rail. Resistor R 11  is included to further restrict the maximum dimmer conduction angle.  
         [0040]     PTC 1  is placed in series (on the reference voltage side) with VR 1  to provide automatic reduction of conduction angle in the event of dimmer over-temperature due to over loading of the product Trimpot VR 2  is placed in series (circuit common side) with VR 1  to allow adjustment of the minimum conduction angle, by raising the minimum control voltage.  
         [0041]     The IGBT gate drive control circuit is provided by transistors Q 16 , Q 17  and Q 5 . The circuit behaves as a non-retriggerable monostable and provides controlled gate drive current to the IGBT to achieve the desired slow switching outcome. Transistor Q 5 , connected to the DC rail, acts as a switch to source IGBT gate current via timing resistor R 38  at turn on Transistor Q 17 , connected to circuit common, acts as a switch for rapid discharge of IGBT gate charge at turn off.  
         [0042]     Base drive current for input transistor Q 16  is sourced by Q 4  from the control timing circuit. The base-emitter is bypassed by resistor R 27  and capacitor C 4  to reduce off-state leakage and to enhance EFT immunity. When transistor Q 16  is not driven, transistor Q 17  is sufficiently biased via resistors R 3 , R 13 , R 35  and R 48 , so that the collector holds the IGBT gate in the discharged (off) state. In this condition, transistor Q 5  is not sufficiently biased to operate. When transistor Q 16  is driven, resistor R 35  provides sufficient bias to operate transistor Q 5 , which provides temporary regenerative base drive for transistor Q 16  via RC network R 37  and CB. This result in monostable action (approximately 300 micro seconds output duration). During this active condition, bias is removed from transistor Q 17 .  
         [0043]     The combination of IGBT series gate current limiting resistor R 38  and parallel gate capacitor gate C 14  provides the required slow turn-on characteristic for EMC control at IGBT turn on. The values selected are specifically suited to the IGBT used, in this case IRG 4  BC 20 S.  
         [0044]     The triac control circuit is shown in  FIG. 1  in the circuit block on the AC side of the diode bridge. The primary function of this circuit is to trigger the triac Q 23  once the IGBT has completed the slow-witching EMC on reduction operation, on a per half-cycle basis. An essentially symmetrical circuit is used to provide a triac gate drive pulse in quadrants  1  and  3  (gate drive polarity follows polarity).  
         [0045]     Additional functions performed by the triac control circuit include over-current protection and dimmer over-voltage protection. Either of these conditions result in immediate triac triggering. During over-current conditions (for example incandescent inrush current), the triac shunts current away from the IGBT. During over-voltage conditions (for example mains transients), the triac shunting action transfers the transient potential to the load.  
         [0046]     The triac control circuit derives its power from the mains via the load, in each half cycle during the time period before IGBT operation commences, that is while mains voltage appears across the dimmer. Average current consumption is long enough to allow the use of a relatively low dissipation resistive chain made up of R 16 , R 17 , R 18  and R 19 . During each mains half-cycle, current provided by the resistor chain is used to charge the capacitor C 10  to a voltage with polarity determined by the mains. The voltage developed across capacitor C 10  is limited to approximately 20 volts for each polarity, as defined by shunting zener diodes DZ 2  and DZ 3 . The sequence of operation of the drive circuit for each half cycle polarity is as follows: 
        reservoir capacitor C 10  is charged while is voltage is present.     A 100 micro second time delay circuit (R 24  and C 3 ) is initiated after the dimmer voltage falls below approximately 20 volts due to IGBT operation.     At the end of the time delay, the triac Q 23  gate is supplied with c from capacitor C 10  via limiting resistor R 41 .        
 
         [0050]     In the positive mains half cycle, reservoir capacitor C 10  is charged to approximately 20 volts from mains through limiting resistors R 16 , R 17 , R 18  and R 19  via the base-emitter junction of transistor Q 18 . When dimmer terminal voltage drops below the 20 volts at old, transistor Q 6  provides charging current via current limiting resistor R 24  for time-delay capacitor C 3 . When the voltage across capacitor C 3  reaches approximately 0.6 volts, transistor Q 13  operates, which in turn provides basic current drive for output transistor Q 1  via current limiting resistor R 10 . Some regenerative feedback from the collector of transistor Q 1  to the base of transistor Q 13  via resistor R 12  speeds up the switching action. The collector of transistor Q 1  drives the triac gate via steering diode D 7 A and gate current limiting resistor R 41 . The function of diode D 7 A is to isolate the triac gate circuit during charging of reservoir capacitor C 10  during the negative half mains half cycle. This is necessary because the base-collector junction of output transistor Q 1  is forward biased in period.  
         [0051]     Capacitor C 3  has the additional role of enhancing EFT immunity for transistor Q 13 , while resistor R 26  reduces transistor leakage. Similarly, resistor R 9  reduces leakage of output transistor Q 1  which would consequently affect the C 3  timing period.  
         [0052]     The operation of the circuit for the negative mains half cycle is the same as described above but uses the mirrored set of components.  
         [0053]     Applications utilising isolated PWM control for dimming level require that both the IGBT (Q 22 ) and triac (Q 23 ) together with associated drive circuitry is permanently connected to mains. This differs from the manually controlled two-wire modular dimmer application where a series mains interrupting switch is always used for load on/off control.  
         [0054]     Generally in the dimmer circuit design, triac Bring operation commences as the dimmer terminal voltage falls below a threshold level as a consequence of IGBT operation.  
         [0055]     A modification to this method of operation is required for the isolated control interface dimer which has permanent mains connection. In this case it is necessary to disable triac triggering which would otherwise be initiated near the end of every mains half cycle. Although the load is effectively in the off state, due to the very low prevailing triac conduction angle and hence load voltage, the resulting line conducted EMC emission levels would be quite large due to such triac operation.  
         [0056]     To address tis situation, additional circuitry has been incorporated which differentiates between the rate of change of mains voltage due to IGBT operation during dimming and that due to normal mains voltage waveform when the IGBT is not activated via the isolated control interface.  
         [0057]     In dimming operation, the triac drive circuit is normally disabled and is only enabled for a short period after detection of the relatively fast rate of change of load terminal voltage due to IGBT operation. During load off state conditions, the triac drive circuit is not enabled by the relatively slow rate of fall of mains voltage near the end of each half cycle.  
         [0058]     Some important design considerations for is additional circuitry axe that a high immunity to mains transients and mains ripple control signals is maintained.  
         [0059]      FIG. 2  shows a modified circuit of the triac control circuit of  FIG. 1  as described above, in which common elements are identified accordingly.  
         [0060]     A description of circuit operation with reference to  FIG. 2  for one half-cycle polarity follows.  
         [0061]     A clamping transistor, Q 300  is used to disable the triac drive circuit from operating by shunting the charging current for the triac firing time delay capacitor, C 3 . A filter capacitor, C 300  is normally charged from the ±20V rail via resistive divider elements, R 300  &amp; R 301  with such polarity as to maintain the bias to the clamping transistor.  
         [0062]     During IGBT, Q 22  operation, the resulting bridge voltage dv/dt produces sufficient current through a small mains coupling capacitor, C 301  to rapidly discharge the filter capacitor in order to reverse bias the clamping transistor base-emitter junction. The clamping transistor remains biased off long enough to allow normal charging of the triac firing time delay capacitor, due to the filter capacitor/bias resistors time constant.  
         [0063]     Immunity to mains ripple injection is achieved through the low-pass-filter action of the capacitor and bias resistors.  
         [0064]     Without IGBT operation the relatively low dv/dt associated with the mains voltage waveform is insufficient to remove the bias voltage on the filter capacitor. Thus the clamping transistor continues to bypass charging of the triac firing delay capacitor, preventing possibility of triac operation.  
         [0065]     A series resistor element, R 302  for the mains coupling capacitor provides current limiting protection under ins surge/transient conditions.  
         [0066]     A reverse connected diode, D 300 A is required across the collector-emitter junction of the clamping transistor, Q 300  in order to prevent the transistor from interfering with correct operation of the associated transistor, Q 301  in the opposite half cycle. In opposite half cycle, the collector-base junction of Q 300  becomes forward biased and can source sufficient bias current to operate the associated transistor, Q 301 . The parallel diode, D 300 A works by limiting the collector voltage to only one forward diode drop, therefore limiting base drive voltage for associated transistor, Q 301  to approx. zero volts.  
         [0067]     The above voltage driven triac control circuit may equally be replaced by a current driven triac control circuit as shown in  FIG. 3 . Once again, the primary function of this circuit is to trigger the triac once the IGBT has completed the slow-switching EMC emission reduction operation, on a per half-cycle basis. The circuit is essentially symmetrical and is used to provide a triac gate drive pulse in quadrants  1  and  3  (gate drive polarity follows polarity).  
         [0068]     In operation, a current sense resistor, R 32 , is used to derive drive potential for the entire triac drive circuit. After a defined load current threshold is achieved, sufficient for triac gate requirements, excess current is by-passed by series connecting diodes D 3  and D 4 . The developed sense voltage begins charging a time delay network made up of resistor R 33  and capacitor C 9 . A comparator transistor, Q 14 , is driven via resistor R 35  once the timing circuit output voltage reaches a threshold level. This level is determined by the voltage at the junction of voltage divider resistors R 34  and R 37  (sourced by the initial sense voltage), in addition to the base-emitter icon voltage of transistor Q 14 .  
         [0069]     The operation of transistor Q 14  results in simultaneous application of base drive for transistors Q 10  and Q 11 , via respective base current limiting resistors R 26  and R 28 . Transistor Q 11 , referenced to the sense voltage, proceeds to drive transistor Q 15  via resistor R 36 . Operation of transistor Q 15  reduces the comparative threshold voltage by lowering transistor Q 14  emitter potential. This positive feedback process is regenerative to speed up the switching action. The application of the triac gate drive current is via output transistor Q 10  and current limiting resistor R 41 . Resistors R 27  and R 38  are required to prevent possible adverse effects from leakage and transistors Q 10 , Q 11  and Q 15 .  
         [0070]     The operation of the circuit for the negative mains half cycle is the same as described above, using the mirrored set of components.  
         [0071]     During IGBT over-current conditions, sufficient voltage is developed across current sense resistor R 40  to bias on transistor Q 18 . This in turn provides base current drive for upward transistor Q 10 , immediately operating the triac, to divert curt away from the IGBT circuit. Resistor R 39  limits transistor Q 18  base current drive to a safe level under these conditions. This provides an inbuilt circuit protection mechanism.  
         [0072]     At dimmer over-voltage currents, the triac gate is directly driven by series connector tranzorbs BZ 1  and BZ 2 . Capacitor C 10  is placed across the triac gate-MT 1  terminals in order to enhance the triac immunity to dv/dt triggering from mains transients.  
         [0073]     Inductor L 1  limits the rate of transfer of load current from the IGBT circuit to the triac on order to control line conducted EMI emission levels. The amount of inductance required for this function is related to the difference between the triac on-state voltage and the voltage across the IGBT circuit current above just prior to triac operation. The presence of current sense resistor R 32  in the IGBT circuit curt path introduces additional voltage differential, there by influencing the amount of inductance required. An additional means of controlling line conducted EMI emission levels is via shunt capacitor C 11  which works in conjunction with L 1  to form a second order low-pass-filter.  
         [0074]     A particular advantage of the present circuit is the ability of the triac control circuit (whether it would be voltage driven or current driven) to be controlled directly by the IGBT circuit rather than via a third centralised control block as in prior systems.  
         [0075]     In the case of the voltage driven drive circuit, this essentially monitors the diode bridge voltage, under control of the operational IGBT in order to determine when triac firing should occur. The necessary charge required for triac gate drive is accumulated from the available mains voltage in the period of the half-cycle before commencement of IGBT conduction. The triac is essentially fired when the diode bridge voltage is reduced below a minimum set threshold. This minimum set threshold is determined by zener diodes DZ 2  and DZ 3  which in the present example, said a minimum threshold of 20 volts (for the positive and negative cycles). The voltage at the diode bridge is sensed by transistor Q 6  and resistor network R 17 , R 16 , R 18  and R 19  as would be understood by the person skilled in the art. The minimum voltage threshold is determined by the components used (in this case the zener diodes DZ 2  and DZ 3 ) and is generally set to exceed by a suitable margin the conduction voltage for the IGBT circuit.  
         [0076]     In the case of the current driven drive circuit, this essentially monitors the diode bridge current under control of the operational IGBT, in order to determine when triac firing should occur. The necessary current required for triac gate drive is derived from the load current result at IGBT conduction in the half cycle. Again, the triac is fired when the diode bridge current rises above a minimum threshold which in this case, is set by resistor R 32 .  
         [0077]     In this way, the circuit configuration is far simpler than prior aft designs which require a separate centralised control block monitoring electrical parameters of the IGBT circuit, determining when the triac should be fired in relation to those sensed parameters and providing control signals to the triac control circuit. Alternately, the centralised control block sometimes provides control signals to both the IGBT and triac control circuits independently of each other, based on pre-set timing parameters.  
         [0078]     A simplified block diagram of this circuit arrangement is shown in  FIG. 4 , in which element  10  represents the first control circuit (IGBT control), element  20  represents a first switch (IGBT), element  30  represents the rectifying circuit (eg. Diode bridge), and element  40  represents the second control circuit (triac control), which obtains its control signals from first control circuit  10 , via rectifying circuit  30 . Element  50  represents the second switch (triac), which is controlled by second control circuit, and element  60  represents the load.  
         [0079]     In practice, the voltage driven triac driven control circuit is preferred over the current driven triac drive circuit. However, each has advantages and disadvantages. The voltage driven triac drive circuit allows minimal size of EMC filter components which results in highest overall product efficiency. The voltage driven circuit however requires voltage dropping elements to derive a power source from the mains, therefore introducing local power dissipation problems (only at low conduction angle settings, where total overall dissipation is low). Further more, additional components are required to disable the triac drive when no IGBT drive is present to achieve off-state conditions (only required for applications without series manually-operated switch).  
         [0080]     In contrast, the current driven circuit does not require a power source connection to the mains, and therefore no local power dissipation issues are encountered. Further more, the triac drive is one hundred percent disabled when there is no IGBT drive to achieve the of state (this is an advantage only for application without a series manually-operated switch). The current drive circuit however suffers from the disadvantage that the presents of current sense components necessitates larger EMC, filter components, and lower overall efficiency is achievable.  
         [0081]     Another circuit block provides circuit protection from over current conditions which may arise from IGBT operation. During such conditions, sufficient voltage is developed across current sense resistor R 42  to bias on transistor Q 14 . This in turn provides base current drive for output transistor Q 1 , immediately operating the triac, to divert current away from the IGBT circuit on the DC side of the diode bridge. Resistor R 40  limits transistor Q 14  base current drive to a safe level under these conditions.  
         [0082]     At dimmer over-voltage occurrences the triac gate is directly driven via series connected tranzorbs D 1  and D 2  and current limiting resistor R 20 . Capacitor C 11  is placed across the triac gate MT 1  terminals order to enhance the triac immunity to dv/dt triggering from mains transients.  
         [0083]     In this dimmer design topology, it is not necessary to incorporate an inductor to achieve the required RF emission level limits. A relatively small inductor may however by required to provide some degree of di/dt protection for the triac di IGBT over sent conditions. In normal operation, the voltage appearing across the triac just prior to firing is of the order of a few volts, depending on the actual load current magnitude. This voltage is a function of the IGBT saturation voltage and diode bridge forward voltage characteristics. At such low operating voltage levels, the triac switching action is more gradual than in standard high voltage triac applications. This results in an inherent smooth transfer of current from IGBT to the triac, with low associated RF emission levels. The addition of the inductor L 1  however, slightly increases the RF emission component associated with transfer of current from the IGBT to the triac. This corresponds to the ail introduced current wave form discontinuity at the point when the IGBT current drops to zero.  
         [0084]     Additionally, at the end of each mains half cycle where the triac naturally commutates off, a burst of RF emission occurs, due to the discontinuity in the load current wave form. Attenuation of this emission is achieved by a capacitor C 15  place across the dimmer terminals. An important additional role of his capacitor is in improving the entire dimmer circuit immunity to EFT.  
         [0085]     Another circuit block is an inductive load imbalance detector. The function of the circuit bloc is to shut down dimmer control in the case of excessively asymmetrical operation, which may be the result of connection to an unloaded iron-core LV lighting transformer. Dimming operation is suspended if the average voltage across the dimmer terminals for the positive and negative half cycles are not similar.  
         [0086]     Alternatively, the dimmer circuit is caused to reduce its conduction angle until a DC component is reduced to below a threshold causing the onset of the DC component itself. Although possible, this technique is not preferred as it would typically result in oscillation between symmetric and no asymmetric conditions.  
         [0087]     Referring back to  FIG. 11  two resistor divider made up of resistors R 43 , R 44 , R 29  and R 45 , R 46  and R 30  are used to sense the mains voltages appearing at the active and load terminals respectively. When referenced to the bridge common (negative) terms, these voltages represent opposite polarities of the mains voltage across the dimmer. The divider junction of each is connected to opposite sides of capacitor C 12 , to produce a differential voltage proportional to the difference in half cycle voltages. Two transistors, Q 9  and Q 10  are used to produce a common-referenced signal if the differential voltage exceeds a threshold of approximately 0.6 volts. A latch circuit made up of transistors Q 11  and Q 20  and resistors R 32  and R 34  has input driven by the imbalance detector output. A transistor Q 21 , wired as a low leakage diode, directs latch output from transistor Q 11  collector to “sync”, ie. to drive the timing control bypass transistor Q 12 .  
         [0088]     Transistor Q 21  acts as a blocking diode to prevent any latch operation by the zero crossing detector. Base-emitter bypass resistors R 31  and R 33  are required to minimise leakage in the respective transistors. Similarly, capacitors C 5  and C 16  are present to enhance EFT immunity of the latch circuit. In addition, capacitor C 5  provides rejection for any high frequency signal component from the imbalanced detector output.  
         [0089]     When operating inductive loads, the dimmer circuit incorporates a moderately sensitive triac assist in achieving an acceptable level of performance, particularly in terms of operating symmetry with worst case load types, ie. low value VA, highly inductive loads such as exhaust fan motors.  
         [0090]     In normal dimming operation, the IGBT initially operates followed by firing of the triac after a fixed time delay. During this pre-triac conduction delay time period, the inductive load current has an opportunity to develop in magnitude. This delay time therefore also increases the ability of the triac to operate successfully with such difficult loads.  
         [0091]     At very low conduction angle settings however, there may be insufficient load current available for reliable triac latching. In this case, a low level load DC component will be stained by the dimmer in combustion with the non-linear load inductance. Under these conditions, there is no danger of damage to the load due to the relatively low rms current magnitude. If load DC component levels become excessive operation of the imbalance detector will automatically shut down the dimmer control.  
         [0092]     In general, capacitive input electronic LV transformers are not generally suitable for leading edge phase control dimmers owing to the additional resulting dimmer power dissipation. The high capacitor charging current pulses increase line conducted EMC emission levels and may produce repetitive high frequency ring bursts on the mains voltage waveform.  
         [0093]     The dimmer circuit of  FIG. 1  incorporates load-over current sensing applicable during the IGBT conduction period. Dimmer connection to such capacitive loads result in sustained operation of the over-current mechanism, producing even higher EMC emission levels. In addition, the high frequency and amplitude ringing current waveform which typically present for the first few hundred micro seconds may result in commutation of the triac. If this condition prevails, the imbalanced protector may cause the dimmer control to shut down. For electronic transformers with maximum rated load connected, this condition is far less likely to occur.  
         [0094]     An alternative circuit configuration for the inductive load imbalance detector of  FIG. 1  as described above is now described with reference to  FIG. 5 , which shows an alternative circuit arrangement for the IGBT control of  FIG. 1 .  
         [0095]     The general operation of the imbalance detection process is described as follows. A capacitor, used to represent conduction time, is repetitively charged from zero to a level determined by the prevailing half cycle conduction period. The voltage developed on this “conduction time detection” capacitor is used to set the peak voltage on a second capacitor, to represent peak conduction time. This “peak conduction time” capacitor is simultaneously discharged with a constant dc current sink. The resulting “peak conduction time” capacitor voltage waveform comprises two components. (1) A dc component exists with magnitude proportional to half cycle conduction period. (2) An AC component exits in the form of a sawtooth, with magnitude determined by fixed parameters ie. capacitor value, magnitude of dc current sink and repetition frequency (2×mains freq.).  
         [0096]     If sufficient difference in alternate polarity half cycle conduction periods exist, the resulting AC voltage waveform associated with the “peak conduction time” capacitor has double the normal amplitude, at only half the repetition frequency (mains freq.). A simple amplitude threshold detector, with dc blocking properties, is used to activate a latching circuit in order to disable dimmer operation when the condition is detected as a steady state.  
         [0097]     A more detailed description with reference to actual components involved follows: During load conduction period of dimming cycle, transistor Q 2  collector can source current via limiting resistor R 203  to “conduction time detection” capacitor C 201 . When dimmer reverts to the non-conducting state, at the end of each half cycle, diode D 200  isolates any current associated with charging of main timing capacitor C 7 .  
         [0098]     Transistor Q 200  is used to reset C 201  to zero volts at the start of each half cycle conduction period. Associated pulsed base drive for Q 200  is provided by capacitor C 200  in series with resistor R 201 . Diode D 201  in conjunction with resistor R 200  provides the necessary discharge path for C 200  in preparation for next mains half cycle event Resistor R 202  bypasses base-emitter of Q 20  to reduce device off-state leakage, during charging period of C 201 .  
         [0099]     Transistor Q 201  is configured as an emitter follower, so that the voltage across capacitor C 202  must follow the peak voltage of C 201 , during brief period where Q 201  base-emitter input is forward biased. Transistor Q 202  in conjunction with bias resistors R 204 , R 205  &amp; R 206  is configured as a current sink for C 202 .  
         [0100]     The sawtooth voltage waveform across C 202  is AC coupled to the base of “threshold detection” transistor Q 203  via diodes D 202 /D 203  and capacitor C 203 . Series connected diode D 203  functions to provide enough signal voltage drop so that Q 203  is not driven under symmetrical dimer operating conditions, where input signal amplitude is normally low. Resistor R 207  reduces Q 203  device off-state leakage, in addition to providing a reverse charge path for C 203 . Diode D 202  also forms part of the reverse charge path for C 203 .  
         [0101]     Under asymmetric dimmer operating conditions, Q 203  is operated in pulse mode, at a low duty cycle. An RC network comprising R 208  and c 204  is used to provide an averaging function for the resulting pulse train Transistor Q 204  form part of a latch circuit, which is trigged when the voltage across C 204  reaches a critical level—as defined by voltage divider resistors R 209  &amp; R 210  in conjunction with Q 204  base-emitter threshold potential. Transistor Q 205  in conjunction with resistors R 211 &amp; R 212  forms the remaining part of the latching circuit.  
         [0102]     At mains power-up or at initial activation of PWM dimmer control drive, it is necessary to ensure that the latching circuit is cleared to the unlatched state for a number of complete mains cycles. This function is performed by RC network comprising R 213  and C 205 , which initially holds the base drive voltage for Q 205  at a level less than the emitter reference level.  
         [0103]     It will be appreciated that the above has been described with reference to a preferred embodiment and that many variations and modifications are possible as would be understood by the person skilled in the art.