Abstract:
A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
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     FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
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     BACKGROUND 
     The present disclosure relates generally to memory subsystems of computer systems and more specifically to systems, devices, and methods for improving the performance and the memory capacity of memory subsystems or memory “boards,” particularly memory boards that include dual in-line memory modules (DIMMs). 
     Certain types of computer memory subsystems include a plurality of dynamic random-access memory (DRAM) or synchronous dynamic random access memory (SDRAM) devices mounted on a printed circuit board (PCB). These memory subsystems or memory “boards” are typically mounted in a memory slot or socket of a computer system, such as a server system or a personal computer, and are accessed by the processor of the computer system. Memory boards typically include one or more memory modules, each with a plurality of memory devices (such as DRAMs or SDRAMs) in a unique configuration of rows, columns, and banks, which provide in a total memory capacity for the memory module. 
     The memory devices of a memory module are generally arranged as ranks or rows of memory, each rank of memory generally having a bit width. For example, a memory module in which each rank of the memory module is 64 bits wide is described as having an “x64” or “by 64” organization. Similarly, a memory module having 72-bit-wide ranks is described as having an “x72” or “by 72” organization. 
     The memory capacity of a memory module increases with the number of memory devices. The number of memory devices of a memory module can be increased by increasing the number of memory devices per rank or by increasing the number of ranks. Rather than referring to the memory capacity of the memory module, in certain circumstances, the memory density of the memory module is referred to instead. 
     During operation, the ranks of a memory module are selected or activated by control signals that are received from the processor. Examples of such control signals include, but are not limited to, rank-select signals, also called chip-select signals. Most computer and server systems support a limited number of ranks per memory module, which limits the memory density that can be incorporated in each memory module. 
     The memory space in an electronic system is limited by the physically addressable space that is defined by the number of address bits, or by the number of chips selected. In general, once the memory space is defined for an electronic system, it would not be feasible to modify the memory space without an extensive design change. This is especially true for the case in which a memory space is defined by a consortium, such as JEDEC. A problem arises when a user&#39;s application requires a larger addressable memory space than the memory space that the current electronic system is designed to support. 
     In developing a memory subsystem, consideration is always given to memory density, power dissipation (or thermal dissipation), speed, and cost. Generally, these attributes are not orthogonal to each other, meaning that optimizing one attribute may detrimentally affect another attribute. For example, increasing memory density typically causes higher power dissipation, slower operational speed, and higher costs. 
     Furthermore, the specifications of the memory subsystem may be guided by physical limitations associated with these attributes. For example, high thermal dissipation may limit the speed of the operation, or the physical size of the memory module may limit the density of the module. 
     These attributes generally dictate the design parameters of the memory module usually requiring that the memory system slow down operation speed if the memory subsystem is populated with more memory devices to provide higher density memory cards. 
     Currently there are two major methods of increasing memory space. The first method is based on an address decoding scheme. This method is very widely adopted in the electronics industry in designing Application-Specific Integrated Circuit (ASIC) and System-On-Chip (SOC) devices to expand system memories. The second method increases the addressable memory space without extensive alteration of the software or hardware of an existing electronics system. This method combines chip select signals with an address signal to double the number of physically addressable memory spaces. These methods have several shortcomings. For example, since these methods increase the addressable memory space by directly adding memory chips, a heavier load is presented to the system controller outputs and the memory device outputs, resulting in a slower system. Also, increasing the number of memory devices also results in higher power dissipation. In addition, since an increase in the number of memory devices on each memory card alters the physical property of the memory card while the system board remains the same, the overall signal (transmission line) wave characteristics deviate from the original design intent or specification. Furthermore, especially when registered DIMMs (RDIMMs) are used, the increase in the number of the memory devices translates to an increase in the distributed RC load on the data paths, but not on the address and control paths, thereby introducing uneven signal propagation delay between the data signal paths and address and control signal paths. 
       FIGS. 1 and 2  illustrate the prior art approach of increasing the number of memory devices. Specifically,  FIG. 1  shows a standard memory subsystem  100  with at least one JEDEC standard two-rank memory module  110  (e.g., a registered dual in-line memory module, or “RDIMM,” only one of which is shown for clarity), wherein each module comprises a plurality memory devices  112  (e.g., DRAMs or SDRAMs). This subsystem requires each data line of an array of data lines  150  from a system memory controller  120  to be connected to a memory device  112  in each rank in each memory module  110 . A register  130  receive a plurality of address and control lines  140  from the controller  120 . Therefore, the system memory controller  120  see all the memory devices  112  as its load during a write operation, and each memory device  112  also sees multiple other memory devices  112 , as well as the system memory controller  120 , as its load during a read operation.  FIG. 2  is a schematic view of a standard memory subsystem  100 ′ with at least one JEDEC standard four-rank memory module  160  (only one of which is shown), each comprising a plurality of memory devices  162 . Each memory module  160  presents four fanouts to the data outputs of the system memory controller  120 ′, which is connected to each of the memory devices by means of a register  130 ′ receiving a plurality of address and control lines  140 ′, and by means of an array of data lines  150 ′. Therefore, as with the two-rank module shown in  FIG. 1 , the system memory controller  120 ′ sees all the memory devices  162  as its load during a write operation, while each memory device  162  sees multiple other memory devices  162  and the system memory controller  120 ′ as its load during a read operation. 
     Therefore, these prior art techniques not only reduce the speed of the memory systems, but they also require hardware modifications to minimize any deviation of the transmission line wave characteristics from the original design specification 
     SUMMARY 
     The present disclosure relates broadly to a load-reducing memory module, including a printed circuit board having a plurality of memory devices, such as DRAMs or SDRAMs. The devices are organized into ranks that may be accessed simultaneously for the full data bit-width of the memory module. 
     One embodiment provides a memory module including: a plurality of memory devices; a controller configured to receive control information from a system memory controller and produce module control signals; and a switching circuit for isolating the plurality of memory devices from the system memory controller, where the switching circuit is configured to drive write data from the system memory controller to the plurality of memory devices and is configured to merge read data from the plurality of memory devices to the system memory controller, and where the switching circuit drives or merges data in response to the module control signals. 
     Within the memory module, the plurality of memory devices may include a first group of the plurality of memory devices in a first rank and a second group of the plurality of memory devices in a second rank. The memory module may be configured to combine the first rank and the second rank into one logical memory rank. The plurality of memory devices may further include a third group of the plurality of memory devices in a third rank and a fourth group of the plurality of memory devices in a fourth rank, and where data lines of the first rank are connected to data lines of the first rank and to the switching circuit, and data lines of the second rank are connected to data lines of the fourth rank and to the switching circuit. 
     Within the memory module with first and second ranks, the switching circuit may include: a data terminal for coupling to the system memory controller; a first memory terminal coupled to the first group of the plurality of memory devices; and a second memory terminal coupled to the second group of the plurality of memory devices, and wherein, when the switching circuit drives write data, the data terminal is coupled to the first memory or to the second memory terminal, and when the switching circuit merges read data, the first memory terminal or the second memory terminal is coupled to the data terminal. The switching circuit may further include: a read buffer configured to conditionally drive the data terminal; a first tristate buffer configured to conditionally drive the first memory terminal; and a second tristate buffer configured to conditionally drive the second memory terminal. The switching circuit may further include: a write buffer configured to receive data signals from the data terminal and to supply the received data signals to the first tristate buffer and the second tristate buffer; a multiplexer configured to receive data signals from the first memory terminal and data signals from the second memory terminal and supply data signals selected from the data signals received from the first memory terminal and the data signals received from the second memory terminal to the read buffer. 
     The memory module may be a dual in-line memory module. The memory devices may include synchronous dynamic random access memories. The bi-directional switch may be configured to reshape a signal waveform. The controller may include a register for latching address and control signals from the memory controller. 
     Another embodiment provides a method of operating a memory module, the method including: providing a load-reducing switching circuit on a data line between a computer system memory controller and a plurality of memory devices; during a write operation, enabling the load-reducing switching circuit to drive a data signal from the computer system memory controller on one of a plurality of paths to memory devices of the memory module; and during a read operation, enabling the load-reducing switching circuit to merge a plurality of data signals from the memory devices of the memory module and driving the merged data signal to the computer system memory controller. 
     Within the method, the enabling the load-reducing switching circuit may include extracting control information from the computer system memory controller to provide an enable control signal to the load-reducing switching circuit. 
     Within the method, the enabling the load-reducing switching circuit, during a write operation, to drive a data signal from the computer system memory controller on one of a plurality of paths to memory devices of the memory module may include performing a regenerative buffer function on the data signal. 
     Within the method, the enabling the load-reducing switching circuit, during a read operation, to merge a plurality of data signals from the memory devices of the memory module and driving the merged data signal to the computer system memory controller may include performing a multiplex function on data signals from the memory devices of the memory module. 
     The method may further include combining two or more physical memory ranks into one logical memory rank. The two or more physical memory ranks may be accessible with a single chip select signal from the computer system memory controller. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A complete understanding of the present invention may be obtained by reference to the accompanying drawings, when considered in conjunction with the subsequent, detailed description, in which: 
         FIG. 1  is a schematic representation of a conventional memory subsystem populated with JEDEC standard two-rank memory modules; 
         FIG. 2  is a schematic representation of a conventional memory subsystem populated with JEDEC standard four-rank memory modules; 
         FIG. 3  is a schematic representation of a memory subsystem in accordance with an embodiment of the disclosure; 
         FIG. 4  is a schematic representation of an exemplary embodiment of a load-reducing switching circuit of the type employed in the memory subsystem of  FIG. 3 ; and 
         FIG. 5  is an exemplary timing diagram illustrating operation of the memory system of  FIGS. 3 and 4 . 
     
    
    
     For purposes of clarity and brevity, like elements and components bear like designations and numbering throughout the figures. 
     DETAILED DESCRIPTION 
       FIG. 3  schematically illustrates an exemplary memory subsystem  200  with load-reduced memory modules in accordance with embodiments described herein. The memory subsystem  200  is designed, for example, to deliver higher speed and higher memory density with lower thermal dissipation as compared with conventional memory subsystems. 
     As shown in  FIG. 3 , the memory subsystem  200  is coupled to a memory controller  201 , of any type well-known in the art. The memory subsystem  200  typically includes a plurality of memory modules  202 , such as DIMMs or RDIMMs, details of which are shown only for one for clarity. Components of the memory modules  202  may be mounted on or in printed circuit boards (PCBs)  400 , which may be arranged in a vertical stack (as shown), or in a back-to-back array. Each module  202  includes a plurality of memory devices  204  (such as DRAMs or SDRAMs). The memory devices  204  may advantageously be arranged in a plurality of rows or ranks. In the embodiment illustrated in  FIG. 3 , the memory devices  204  are arranged in four ranks, designated A, B, C, and D, although embodiments with less than or more than four ranks may be employed. 
     Each memory module  202  is includes one or more load-reducing switching circuits  216 . The load-reducing switching circuits  216  bidirectionally buffer data signals between the memory controller  201  and the memory devices  204 . In the exemplary embodiment of this disclosure, each of the load-reducing switching circuits  216  is connected to one memory device  204  in each of the four ranks, A, B, C, and D. For the sake of this disclosure the devices in rank A are designated  204 A; those in rank B are designated  204 B; those in rank C are designated  204 C; and those in rank D are designated  204 D. In the embodiment of  FIG. 3 , each load-reducing switching circuit  216  has the same bit width for example 8 bits, as the associated memory devices  204 . In other embodiments, the bit widths of the load-reducing switching circuits  216  and the memory devices  204  may be different. For example, the load-reducing switching circuits  216  may have a bit width of 16 and the memory devices  204  may have bit width of 8 with each load-reducing switching circuit  216  connected to two memory devices  204  in each rank. 
     Each memory module  202  includes a module controller  220 . The module controller  220  is coupled to address and control lines  240  (e.g., bank address signals, row or rank address signals, column address signals, address strobe signals, and chip-select signals) from the system memory controller  201 . The module controller  220  registers address and control lines  240  in a manner functionally comparable to the address register of a convention RDIMM. The registered address and control lines  240  are supplied to the memory devices  204 . Additionally, the module controller  220  supplies control signals for the load-reducing switching circuits  216 . The control signals indicate, for example, the direction of data flow, that is, to or from the memory devices. The module controller  220  may produce additional chip select signals or output enable signals based on address decoding. 
     In certain embodiments, the memory modules  202  may include electrical components that are electrically coupled to one another. The electrical components may be surface-mounted, through-hole mounted, or otherwise connected to the PCB  400 . These electrical components may include, but are not limited to, electrical conduits, resistors, capacitors, inductors, and transistors. In certain embodiments, at least some of these electrical components are discrete, while in other certain embodiments, at least some of these electrical components are constituents of one or more integrated circuits. 
     Various types of memory modules  202  are compatible with embodiments described herein. For example, memory modules having memory capacities of 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, as well as other capacities, are compatible with embodiments described herein. In addition, memory modules having widths of 4 bytes 8 bytes, 9 bytes, 16 bytes, 32 bytes, or 32 bits, 64 bits, 72 bits, 128 bits, 256 bits, as well as other widths (in bytes or in bits), are compatible with embodiments described herein. Furthermore, memory modules compatible with embodiments described herein include, but are not limited to, single in-line memory modules (SIMMs), dual in-line memory modules (DIMMs) small-outline DIMMs (SO-DIMMs), unbuffered DIMMs (UDIMMs), registered DIMMs (RDIMMs), fully-buffered DIMMs (FBDIMMs), mini-DIMMs, and micro-DIMMs. 
     In some embodiments, the PCBs  400  are mountable in module slots (not shown) of the computer system. The PCBs  400  of some such embodiments have a plurality of edge connections (not shown) configured to make electrical contact with corresponding contacts of the module slots and to the various components of the memory modules on the PCBs, thereby providing electrical connections between the computer system and the components of the memory module. 
     Memory devices  204  compatible with embodiments described herein include, but are not limited to, random-access memory (RAM), dynamic random-access memory (DRAM), synchronous DRAM (SDRAM), and double-data-rate DRAM (e.g., DDR, DDR2, DDR3, etc). In addition, memory devices having bit widths of 4, 8, 16, 32, as well as other bit widths, are compatible with embodiments described herein. Memory devices  204  compatible with embodiments described herein have packaging which include, but are not limited to, thin small-outline package (TSOP), ball-grid-array (BGA), fine-pitch BGA (FBGA), micro-BGA (μBGA), mini-BGA (mBGA), and chip-scale packaging (CSP). 
     In some embodiments, the load-reducing switching circuits  216  may include one or more functional devices, such as a programmable-logic device (PLD), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a custom-designed semiconductor device, or a complex programmable-logic device (CPLD). In some embodiments, the load-reducing switching circuits  216  may be custom devices. In some embodiments, the load-reducing switching circuits  216  may include various discrete electrical elements; while in other embodiments, the load-reducing switching circuits  216  may include one or more integrated circuits. 
     Each of the load-reducing switching circuits  216 , in accordance with an embodiment of this disclosure, is inserted into one or more of the data lines  218  connected to one memory device in each of the ranks A, B, C, D. Thus, each load-reducing switching circuit  216  is connected to one each of the memory devices  204 A,  204 B,  204 C, and  204 D. Each data line  218  thus carries data from the system memory controller  201 , through the load-reducing switching circuits  216 , to the memory devices  204 A,  204 B,  204 C,  204 D connected to each of the load-reducing switching circuits  216 . The load-reducing switching circuits  216  may be used to drive each data bit to and from the memory controller  201  and the memory devices  204  instead of the memory controller  201  and the memory devices  204  directly driving each data bit to and from the memory controller  201  and the memory devices  204 . Specifically, as described in more detail below, one side of each load-reducing switching circuit  216  is coupled to a memory device in each rank, while the other side of the load-reducing switching circuit  216  is coupled to the corresponding data line  218  of the memory controller  201 . 
     To reduce the memory device loads seen by the system memory controller  201 , the load-reducing switching circuit  216  is advantageously configured to be recognized by the system memory controller  201  as a single memory load. This advantageous result is desirably achieved in certain embodiments by using the load-reducing switching circuit  216  to electrically isolate the memory devices  204  from the memory controller  201 . Therefore, in the example of  FIG. 3 , each data bit from the system memory controller  201  sees, for one memory module  202 , a single load, which is presented by one load-reducing switching circuit  216 , instead of the four memory devices  204 A,  204 B,  204 C,  204 D to which the load-reducing switching circuit  216  is coupled. In comparison to the standard JEDEC four rank DIMM configuration (see  FIG. 2 ), the memory system  200  may reduce the load on the system memory controller  201  by a factor of four. 
       FIG. 4  schematically illustrates an exemplary load-reducing switching circuit  216  compatible with embodiments described herein. In one embodiment, the load-reducing switching circuit  216  includes control logic circuitry  302  used to control the various components of the load-reducing switching circuit, which may include buffers, switches, and multiplexers among other components. The illustrated embodiment is 1-bit wide and switches a single data line  218  between the memory controller  201  and the memory devices  204 . In other embodiments, the load-reducing switching circuit  216  may be multiple bits wide, for example, 8 bits, and switch a corresponding number of data lines  218 . In a multiple bit wide embodiment, the control logic circuitry  302  may be shared over the multiple bits. 
     As a part of isolating the memory devices  204  from the system memory controller  201 , in one embodiment, the load-reducing switching circuits  216  allow for “driving” write data and “merging” read data. In the operational embodiment shown in  FIG. 4 , in a write operation, data entering a load-reducing switching circuit  216  via a data line  218  is driven onto two data paths, labeled path A and path B, preferably after passing through a write buffer  303 . The ranks of memory devices  204  are likewise divided into two groups with one group associated with path A and one group associated with path B. As shown in  FIG. 3 , rank A and rank C are in the first group, and rank B and rank D are in the second group. Accordingly, the memory devices  204 A,  204 C of rank A and rank C are connected to the load-reducing switching circuits  216  by a first one of the two data paths, and the memory devices  204 B,  204 D of rank B and rank D are connected to the load-reducing switching circuits  216  by a second one of the two data paths. In other embodiments, the driving of write data and merging of read data may be performed over more than two data paths. 
     As is known, Column Address Strobe (CAS) latency is a delay time which elapses between the moment the memory controller  201  informs the memory modules  202  to access a particular column in a selected rank or row and the moment the data for or from the particular column is on the output pins of the selected rank or row. The latency may be used by the memory module to control operation of the load-reducing switching circuits  216 . During the latency, address and control signals pass from the memory controller  201  to the module controller  220  which produces controls sent to the control logic circuitry  302  which then controls operation of the components of the load-reducing switching circuit  216 . 
     For a write operation, during the CAS latency, the module controller  220 , in one embodiment, provides enable control signals to the control logic circuitry  302  of each load-reducing switching circuit  216 , whereby the control logic circuitry  302  selects either path A or path B to direct the data. Accordingly when the control logic circuitry  302  receives, for example, an “enable A” signal, a first tristate buffer  304  in path A is enabled and actively drives the data value on its output, while a second tristate buffer  306  in path B is disabled with its output in a high impedance condition. In this state, the load-reducing switching circuit  216  allows the data to be directed along path A to a first terminal Y 1 , which is connected to and communicates only with the first group of the memory devices  204 , i.e., those in ranks A and C. Similarly, if an “enable B” signal is received, the first tristate  304  opens path A and the second tristate  306  closes path B, thus directing the data to a second terminal Y 2 , which is connected to and communicates only with the second group of the memory devices  204 , i.e., those in ranks B and D. 
     For a read operation, the load-reducing switching circuit  216  operates as a multiplexing circuit. In the illustrated embodiment, for example, data signals read from the memory devices  204  of a rank are received at the first or second terminals Y 1 , Y 2  of the load-reducing switching circuit  216 . The data signals are fed to a multiplexer  308 , which selects one to route to its output. The control logic circuitry  302  generates a select signal to select the appropriate data signal, and the selected data signal is transmitted to the system memory controller  201  along a single data line  218 , preferably after passing through a read buffer  309 . The read buffer  309  may be a tristate buffer that is enabled by the control logic circuitry  302  during read operations. In another embodiment, the multiplexer  308  and the read buffer  309  may be combined in one component. In yet another embodiment, the multiplexer  308  and the read buffer  309  operations may be split over two tristate buffers, one to enable the value from Y 1  to the data line  218  and another to enable the value from Y 2  to the data line  218 . 
     The load-reducing switching circuits  216  present a load on the data lines  218  from the write buffer  303  and the read buffer  309 . The write buffer  303  is comparable to an input buffer on one of the memory devices  204 , and the read buffer  309  is comparable to an output buffer on one of the memory devices  204 . Therefore, the load-reducing switching circuits  216  present a load to the memory controller  201  that is substantially the same as the load that one of the memory devices  204  would present. Similarly, the load-reducing switching circuits  216  present a load on the first and second terminals Y 1 , Y 2  from the multiplexer  308  and the first tristate buffer  304  (on the first terminal Y 1 ) and the second tristate buffer  306  (on the second terminal Y 2 ). The multiplexer  308  is comparable in loading to an input buffer on the memory controller  201 , and the first and second tristate buffers  304 ,  306  are each comparable to an output buffer on the memory controller  201 . Therefore, the load-reducing switching circuits  216  present a load to the memory devices  204  that is substantially the same as the load that the memory controller  201  would present. 
     Additionally, the load-reducing switching circuits  216  operate to ameliorate quality of the data signals passing between the memory controller  201  and the memory devices  204 . Without the load-reducing switching circuits  216 , waveforms of data signals may be substantially degraded or distorted from a desired shape between source and sink. For example, signal quality may be degraded by lossy transmission line characteristics, mismatch between characteristics of transmission line segments, signal crosstalk, or electrical noise. However, in the read direction, the read buffer  309  regenerates the signals from the memory devices  204  thereby restoring the desired signal waveform shapes. Similarly, in the write direction, the first tristate buffer  304  and the second tristate buffer  306  regenerate the signals from the memory controller  201  thereby restoring the desired signal waveform shapes. 
     Referring again to  FIG. 3  when the memory controller  201  executes read or write operations, each specific operation is targeted to a specific one of the ranks A, B, C, and D of a specific module  202 . The load-reducing switching circuit  216  on the specifically targeted one of the memory modules  202  functions as a bidirectional repeater/multiplexor, such that it drives the data signal when connecting from the system memory controller  201  to the memory devices  204 . The other load-reducing switching circuits  216  on the remaining memory modules  202  are disabled for the specific operation. For example, the data signal entering on data line  218  entering into load-reducing switching circuit  216  is driven to memory devices  204 A and  204 C or  204 B and  204 C depending on which memory devices are active and enabled. The load-reducing switching circuit  216  then multiplexes the signal from the memory devices  204 A,  204 B,  204 C,  204 D to the system memory controller  201 . The load-reducing switching circuits  216  may each control, for example, a nibble-wide data path or a byte-wide-data path. As discussed above, the load-reducing switching circuits  216  associated with each module  202  are operable to merge data read signals and to drive data write signals, enabling the proper data paths between the system memory controller  201  and the targeted or selected memory devices  204 . Thus, the memory controller  201 , when there are four four-rank memory modules, sees four load-reducing switching circuit loads, instead of sixteen memory device loads. The reduced load on the memory controller  201  enhances the performance and reduces the power requirements of the memory system, as compared with, for example, the conventional systems described above with reference to  FIGS. 1 and 2 . 
     Operation of a memory module using the load-reducing switching circuit  216  may be further understood with reference to  FIG. 5 , an illustrative timing diagram of signals of the memory module  202 . The timing diagram includes first through eighth time periods  501 - 508 . When the memory devices  204  are synchronous memories, each of the time periods  501 - 508  may correspond to one clock cycle of the memory devices  204 . 
     The first, second, and third time periods  501 - 503  illustrate write operations with data passing from the memory controller  201  to the memory module  202 . The fourth time period  504  is a transition between the write operations and subsequent read operations. The timing diagram shows a write operation to the first group of memory devices  204 A,  204 C connected to the first terminals Y 1  of the load-reducing switching circuits  216  and a write operation to the second group of memory devices  204 B,  204 D connected to the second terminals Y 2  of the load-reducing switching circuits  216 . Recalling the CAS latency described above, each write operation extends over two time periods in a pipelined manner. 
     The write to the first group of memory devices  204 A,  204 C appears in the first time period  501  when system address and control signals  240  pass from the memory controller  201  to the module controller  220 . The module controller  220  evaluates the address and control signals  240  to determine that data is to be written to memory devices  204 A,  204 C in the first group. During the second time period  502 , the module controller  220  supplies control signals to the control logic circuitry  302  to enable the first tristate buffer  304  and to disable the second tristate buffer  306  and the read buffer  309 . Thus, during the second time period  502 , data bits pass from the data lines  218  to the first terminal Y 1  and on to the memory devices  204 A,  204 C. 
     Similarly, the write to the second group of memory devices  204 A,  204 C appears in the second time period  502  when system address and control signals  240  pass from the memory controller  201  to the module controller  220 . The module controller  220  evaluates the address and control signals  240  to determine that data is to be written to memory devices  204 B,  204 D in the second group. During the third time period  503 , the module controller  220  supplies control signals to the control logic circuitry  302  to enable the second tristate buffer  306  and to disable the first tristate buffer  304  and the read buffer  309 . Thus, during the third time period  503 , data bits pass from the data lines  218  to the second terminal Y 2  and on to the memory devices  204 B,  204 D. 
     The fifth, sixth, seventh, and eighth time periods  505 - 508  illustrate read operations with data passing to the memory controller  201  from the memory module  202 . The timing diagram shows a read operation from the first group of memory devices  204 A,  204 C connected to the first terminals Y 1  of the load-reducing switching circuits  216  and a read operation from the second group of memory devices  204 B,  204 D connected to the second terminals Y 2  of the load-reducing switching circuits  216 . Recalling the CAS latency described above, each read operation extends over two time periods in a pipelined manner. 
     The read from the first group of memory devices  204 A,  204 C appears in the fifth time period  505  when system address and control signals  240  pass from the memory controller  201  to the module controller  220 . The module controller  220  evaluates the address and control signals  240  to determine that data is to be read from memory devices  204 A,  204 C in the first group. During the sixth time period  506 , the module controller  220  supplies control signals to the control logic circuitry  302  to cause the multiplexer  308  to select data from the first terminal Y 1 , to enable the read buffer  309 , and to disable the first tristate buffer  304  and the second tristate buffer  306 . Thus, during the sixth time period  506 , data bits pass from the memory devices  204 A,  204 C via the first terminal Y 1  to data lines  218  and on to the memory controller  201 . 
     The read from the second group of memory devices  204 B,  204 D appears in the seventh time period  507  when system address and control signals  240  pass from the memory controller  201  to the module controller  220 . The module controller  220  evaluates the address and control signals  240  to determine that data is to be read from memory devices  204 B,  204 D in the second group. During the eighth time period  508 , the module controller  220  supplies control signals to the control logic circuitry  302  to cause the multiplexer  308  to select data from the second terminal Y 2 , to enable the read buffer  309 , and to disable the first tristate buffer  304  and the second tristate buffer  306 . Thus, during the eighth time period  506 , data bits pass from the memory devices  204 B,  204 D via the second terminal Y 2  to data lines  218  and on to the memory controller  201 . 
     Since other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art, the invention is not considered limited to the example chosen for purposes of disclosure. Accordingly, this disclosure encompasses all changes and modifications that do not constitute departures from the true spirit and scope of the subject matter of this disclosure.