Abstract:
The storage cell comprises a bistable element formed from two channel P MOS transistors called first and second transistors, and two channel N MOS transistors, called third and fourth transistors, a fifth and a sixth channel N MOS transistor being used for controlling the bistable element, the different transistors of the cell being electrically interconnected in such a way that the interconnection lines used for connecting them do not cross.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a CMOS static storage cell. It can be used in the microelectronics field for producing random access memories, particularly for storing binary information. 
     CMOS (complementary metal-oxide-semiconductors) static memories or stores, constituted solely by MOS transistors with a N channel and MOS transistors with a P channel have the advantage of consuming very little electric power and of having a high immunity to interference, particularly that of an electrical nature. However, they have a relatively low integration density. 
     This low integration density is particularly due to the presence in each storage cell of several electric contact holes necessary for the interconnections of the various transistors forming a storage cell. These contact holes are formed in an insulating layer, particularly of silicon oxide, deposited on the complete circuit. A further problem is caused by the guards necessary for the positioning of these contact holes. This is illustrated by the attached FIGS. 1 and 2, which respectively show the electrical diagram of a CMOS storage cell according to the prior art, and in plan view the organization of the various layers constituting this cell. 
     The storage cell comprises a bistable element or flip-flop 2 formed from two MOS transistors T 1  and T 2  with a P channel and two MOS transistors T 3  and T 4  with a N channel, which are electrically interconnected. 
     This storage cell also comprises two MOS transistors T 5  and T 6  with a N channel constituting the transistors for operating the bistable element 2 of the cell. 
     As shown in FIGS. 1 and 2, the sources S 1  and S 2  of transistors T 1  and T 2  are interconnected by means of an interconnection line 4, diffused in the substrate on which the cell is formed, and are raised to a positive potential V supplied by a not shown, electric power source. Moreover, the gates of transistors T 1  and T 3 , designated G 1  and G 3  (FIG. 1) are electrically interconnected, and so are gates G 2  and G 4  of transistors T 2  and T 4 . 
     The connection of the gates of transistors T 1  and T 3  is brought about by means of an interconnection line 6 and the connection of the gates of transistors T 2  and T 4  by means of interconnection line 8, said lines 6 and 8 being formed (FIG. 2) in an etched conductive layer 9, generally of polycrystalline silicon, which also is used for producing the various gates. 
     Moreover, as shown in FIG. 1, the drain D 1  of transistor T 1  is electrically connected to drain D 3  of transistor T 3 , as well as to the gates G 2  and G 4  of transistors T 2  and T 4 . 
     These connections, as shown in FIG. 2, are obtained by means of three electric contact holes 10, 12, 14, formed in an insulating material layer particularly silicon oxide (not shown). An interconnection line 16 formed in the more particularly aluminum conductive layer 18 ensures the connection between the drain D 1  of transistor T 1  and the drain D 3  of transistor T 3 , said line 16 being respectively in contact with drain D 1  and drain D 3  by means of electric contact holes 10 and 14, as well as an interconnection line 19 formed in the etched conductive layer 9 which ensures the connection of active zones D 1  and D 3  to the gates of transistors T 2  and T 4 , said line 19 being in contact with line 16 as a result of contact hole 12 made in said line 16. 
     In the same way as shown in FIG. 1, the drain D 2  of transistor T 2  is electrically connected by drain D 4  of transistor T 4  as well as to gates G 1  and G 3  of transistors T 1  and T 3 . 
     As shown in FIG. 2, these connections are produced by means of three electric contact holes 20, 22, 24, formed in the insulating material layer. An interconnection line 26 formed in conductive layer 18 ensures the connection between drain D 2  of transistor T 2  and drain D 4  of transistor T 4 , said line 26 being respectively in contact with drain D 2  and drain D 4  as a result of electric contact holes 20, 24, as well as an interconnection line 28 formed in the conductive layer 9 and ensuring the connection between active zones D 2 , D 4  and the gates of transistors T 1 , T 3 , said line 28 being in contact with line 26 as a result of the contact hole 22 formed in said line 26. 
     Furthermore, sources S 3 , S 4  of transistors T 3 , T 4  are raised to earth potential (FIG. 1). These connections are assured by means of interconnection lines 30, 32, formed in the conductive coating 18, which are respectively in contact with sources S 3 , S 4  of transistors T 3 , T 4  via electric contact holes 34, 36 (FIG. 2), formed in the insulating layer. 
     As shown in FIG. 1, the activation of bistable element 2 of the storage cell is brought about by transistor T 5 , connected by its drain D 5  to drain D 3  of transistor T 3 , to drain D 1  of transistor T 1  and to gates G 2 , G 4  of transistors T 2 , T 4 , or by transistor T 6 , whose drain D 6  is connected to drain D 4  of transistor T 4 , to drain D 2  of transistor T 2  as well as to gates G 1 , G 3  of transistors T 1 , T 3 . 
     The connection between drain D 5  of transistor T 5  and drain D 3  of transistor T 3  is, as shown in FIG. 2, assured by an interconnection line 38 diffused in the substrate, whilst the connection between drain D 6  of connection T 6  and D 4  of transistor T 4  is assured by an interconnection line 40 diffused in the substrate. The other connections of drains D 5 , D 6  of transistors T 5 , T 6  are, as hereinbefore, provided by electric contact holes respectively 10, 12, 14 and 20, 22, 24 and the interconnection lines respectively 16, 19, 8, and 26, 28, 6. 
     The electric signals used for the selection of the storage cell are transmitted to gates G 5 , G 6  of transistors T 5 , T 6 , which are electrically interconnected by interconnection line 42, formed in conductive layer 9, whilst the information to be stored in the selected storage cell or to be removed from said cell are transmitted by sources S 5  and S 6  of transistors T 5  and T 6 . This information is carried by lines 44, 46 formed in the conductive layer 18 and in contact respectively with sources S 5 , S 6  of transistors T 5 , T 6 , via electric contact holes 48, 50 (FIG. 2) and in the insulating layer and a second, more particularly aluminum conductive layer (not shown). 
     The presence of these six electric contact holes 10, 12, 14, 20, 22 and 24, which are necessary for producing the internal connections of the CMOS storage cell, bearing in mind the organization of the different layers constituting this cell, and particularly the crossing of the interconnection lines formed in the conductive layers 9, 18, limits the integration density of the storage cell. 
     SUMMARY OF THE INVENTION 
     The present invention relates to a CMOS static storage cell having an organization different from that of the prior art storage cells and which makes it possible to eliminate all the electric contact holes used for the internal connections of storage cells according to the prior art, so that the integration density of such cells can be increased. 
     More specifically the present invention invention relates to a CMOS static storage cell comprising in per se known manner a bistable element, formed from two channel P MOS transistors, called the first and second transistors, as well as two channel N MOS transistors, called the third and fourth transistors, a fifth and sixth channel MOS transistors being used for controlling the bistable element. It is characterized in that the different transistors of the cell are electrically interconnected in such a way that the interconnection lines for connecting these do not cross. 
     As a result of the non-crossing of the interconnections lines of the various transistors forming the cell, it is possible to eliminate all the electric contact holes within the cell and thus increase the integration density. 
     Advantageously, the connections of the transistors of the bistable element of the cell according to the invention are realized in such a way that: 
     the gates of the first and third transistors are interconnected, 
     the gates of the second and fourth transistors are interconnected, 
     the sources of the first and second transistors are connected to one another and to an electric power supply, 
     the sources of the third and fourth transistors are connected to earth, 
     the drain of the first transistor is connected to the gate of the second transistor, 
     the drain of the second transistor is connected to the gates of the first and third transistors, as well as to the drain of the fourth transistor, and 
     the drain of the third transistor is connected, in the bistable element, to the gate of the fourth transistor. 
     According to a preferred embodiment of the storage cell according to the invention, the drains of the fifth and sixth transistors are respectively connected to the gate of the third transistor and to the gate of the fourth transistor, the gates of the fifth and sixth transistors, which are interconnected, being used for carrying the cell selection signals and the sources of these fifth and sixth transistors are used for carrying the information to be stored or read. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is described in greater detail hereinafter relative to non-limitative embodiments and the attached drawings, wherein show: 
     FIG. 1, already described, the electric diagram of a prior art CMOS static storage cell. 
     FIG. 2 already described, in plan view the organization of the various layers constituting the cell of FIG. 1. 
     FIG. 3 the electric diagram of a CMOS static storage cell according to the invention. 
     FIG. 4 in plan view, the organization of the various layers constituting the cell of FIG. 3. 
     FIG. 5 to 8 in longitudinal section, the various stages of a process for producing a storage cell according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With a view to the simplification and the good understanding of the following description, the elements of the storage cell according to the invention as shown in FIGS. 3 and 4 and which remain unchanged with respect to the prior art described with reference to FIGS. 1 and 2, will carry the same references. 
     As hereinbefore, the cell according to the invention comprises a bistable element or flip-flop 2 formed from two channel P MOS transistors T 1  and T 2 , and two channel N MOS transistors T 3  and T 4 , which constitute the control transistors of the cell, together with two transistors T 5 , T 6  for activating the bistable element and which are constituted by channel N MOS transistors. 
     As in the prior art cells, sources S 1  and S 2  of transistors T 1  and T 2  are electrically interconnected by means of an interconnection line 4 diffused in the substrate in which the cell is formed, and which are raised to a positive potential V supplied by an electric power supply. Moreover, the gates G 1  and G 3  of transistors T 1  and T 3  are electrically interconnected by means of interconnection line 6 and the gates G 2 , G 4  of transistors T 2 , T 4  are also interconnected by means of interconnection line 8, whereby, as hereinbefore, lines 6 and 8 are formed in the etched conductive layer 9, which more particularly of polycrystalline silicon, used for producing the gates of the transistors of the cell according to the invention. 
     Moreover, as in the prior art, sources S 3  and S 4  of transistors T 3  and T 4  are raised to earth potential (FIG. 3). These connections are provided by means of interconnection lines 30, 32, formed in the in particular aluminum conductive layer 18 and which are respectively in contact with sources S 3 , S 4  via electric contact holes 34 and 36 (FIG. 4), formed in the more particularly silicon oxide insulating layer (not shown). 
     Finally, as in the prior art, gates G 5 , G 6  of transistors T 5 , T 6  by which the storage cell selection signals arrive are electrically interconnected (FIG. 3) by means of interconnection line 42, formed in the conductive layer 9 and sources S 5 , S 6  of said transistors T 5 , T 6  respectively to interconnection lines 44, 46, which are used for carrying the information to be stored or to be extracted from the storage cell. Lines 44 46 formed in the conductive layer 18 are respectively in contact with sources S 5 , S 6  via electric contact holes 48, 50 (FIG. 4). 
     According to the invention, drain D 1  of transistor T 1  is connected to gate G 2  of transistor T 2  (FIG. 3) by the uninsulated interconnection line 52, which is in direct contact with drain D 1  and with an extension 53 of gate G 2  formed in conductive layer 9 (FIG. 4). In the same way, drain D 3  of transistor T 3  is connected to the gate of transistor T 4  (FIG. 3) by means of an uninsulated interconnecting line 54, with direct contact with drain D 3  and an extension 55 of gate G 4 , formed in layer 9 (FIG. 4). 
     Moreover, drain D 2  of transistor T 2  is connected to drain D 4  of transistor T 4 , as well as to gates G 1 , G 3  of transistors T 1 , T 3  (FIG. 3). These connections are provided by means of an uninsulated interconnection line 56, which is in direct contact with drain D 2  and drain D 4 , as well as with extension 58 of the interconnection line 6 connecting the gates of transistors T 1 , T 3  (FIG. 4). 
     Moreover, according to the invention, the activation of bistable element or flip-flop 2 by transistors T 5 , T 6  takes place either through drain D 5  of transistor T 5  connected to gate G 3  of transistor T 3  (FIG. 3) by means of uninsulated interconnection lines 60 in direct contact with drain D 5  and gate G 3  of the corresponding transistors, or through drain D 6  of transistor T 6  connected to gate G 4  of transistor T 4  by means of the insulated interconnection line 62, which is in direct contact with drain D 6  and gate G 4  of the corresponding transistors (FIG. 4). 
     The uninsulated interconnection lines 52, 54, 56, 60 and 62 are formed in the same conductive layer, which is more particularly formed from a titanium - tungsten alloy. Their production process will be described hereinafter. 
     As shown in FIGS. 3 and 4, the different internal connections of storage cell according to the invention never cross. In particular, the uninsulated interconnection lines never cross the interconnection lines diffused in the substrate, or the interconnection lines formed in conductive layer 9, in which the gates are formed. 
     The organization of the static storage cell according to the invention makes it possible, as a result of the formation of the internal connections thereof without employing an insulating layer, to eliminate all the electric contact holes normally used for the connection of transistors of the prior art cell. 
     One of the processes making it possible to electrically interconnect the transistors of the storage cell, without producing electric contact holes, formed in an insulating material layer and which in particular makes it possible to produce interconnection lines 52, 54, 56, 60, 62 has been described in French Pat. No. 2,564,443 in the name of the present Applicant. This process will be described with reference to FIGS. 5 to 8 which, in longitudinal section, show the different stages of the process. 
     In order to simplify the description, this will be done in order to permit the connection of drain D 2  of transistor T 2  to drain D 4  of transistor T 4 , by means of line 56. However, this process is obviously also applicable to all uninsulated connections, i.e. without an electric contact hole, of the storage cell according to the invention. 
     In FIGS. 5 to 8, reference 72, 74 respectively correspond to the source and drain of the type N channel transistor T 4 , formed in a type P silicon substrate 76, whilst reference 78 corresponds to the gate of said transistor, more particularly made from a polycrystalline silicon. 
     In the same way, reference 82, 84 respectively represent the drain and the source of the channel P transistor T 2 , e.g. formed in a type N silicon substrate 86, whilst reference 88 represents the gate of transistor T 2 , particularly formed from polycrystalline silicon. 
     Moreover, reference 90 represents the field oxide separating transistors T 2 , T 4  from one another. 
     According to this process, the interconnection of drain 74 of transistor T 4  and drain 82 of transistor T 2  is brought about by directly depositing on the complete integrated circuit following the formation of the field oxide gates, drains, and sources of the said transistors, a layer 92 of a conductive material, e.g. an alloy of titanium and tungsten, as shown in FIG. 5, followed by the etching of said layer 92 in order to produce the desired connection 92a (FIG. 8). 
     This layer 92 can be etched by firstly depositing on said layer 92 a layer 94 of another material, more particularly of aluminum. Then, as shown in FIG. 6, a resin mask 96 is produced and this represents the image of connection 92a to be formed. This is followed by eliminating that part of layer 94 not covered by mask 96, e.g. by using an anisotropic etching process. 
     Then, as shown in FIG. 7, that part of layer 92 not covered by the remainder 94a of layer 94 is eliminated e.g. by using an anisotropic etching process, the remainder 94a of layer 94 serving as a mask for this etching operation. 
     Finally, as shown in FIG. 8, the resin mask 96 is eliminated. 
     Layer 92, which is more particularly an alloy of titanium and tungsten, when etched in this way makes it possible to connect drain 74 of the channel N transistor T 4  to drain 82 of the channel P transistor T 2 . 
     Apart from its function as a mask for etching layer 92, the use of an aluminum layer 94 makes it possible to avoid, during subsequent operations, the oxidation of the titanium - tungsten alloy layer. 
     This process for connecting the drain of transistor T 2  to the drain of transistor T 4  is obviously applicable for obtaining all the internal connections of the storage cell according to the invention, without insulation, and particularly for obtaining connection 52 between the drain of transistor T 1  and the gate of transistor T 2 , the connection 56 of the drain of transistor T 2 , the drain of transistor T 4  and the gates of transistors T 1  and T 3 , the connection 54 and 62 of the drain of transistor T 3  to the gate of transistor T 4  and to the drain of transistor T 6 , as well as the connection 60 between the drain of transistor T 5  and the gate of transistor T 3 . 
     The aforementioned connection process makes it possible, through eliminating the electric contacts within the storage cell according to the invention, to increase the integration density by 27% compared with the prior art cells. 
     It is possible to further increase the integration density of the storage cell by using a process making it possible to obtain an autoalignment or autopositioning of the uninsulated interconnection lines, on active zones and/or the gates to be interconnected, the process described hereinbefore not being an autoaligned process. 
     As an autoaligned or autopositioned process, it is in particular possible to use that described in French Pat. No. 2,562,327, filed in the name of the Applicant. 
     Moreover, contrary to the prior art cells, it is possible to increase the integration density by decreasing the distance separating the active zones of the different transistors of the cell to be connected, as a result of the absence of electric contact holes in said cell. This can be brought about by using an insulation process between the different transistors of the cell by an isolation trench, like that described in the article IEDM-82, published by IEEE, 1982, pp. 237 to 240, and entitled &#34;Deep Trench Isolated CMOS Devices&#34;, by R. D. Rung, H. Momose and Y. Nagakubo instead of using a local field oxide.