Abstract:
A method of detecting and correcting errors in a memory subsystem of a computer is described. The method includes beginning a write operation of N data bits to a memory, generating M check bits from the N data bits, writing the N data bits and the M check bits to the memory, reading the N data bits and M check bits from the memory, generating X syndrome bits from the N data bits and the M check bits, and using the X syndrome bits to detect and correct errors. Preferably, the M check bits are generated also from A address bits corresponding to the location in memory to which the N data bits and M check bits are to be written.

Description:
FIELD OF THE INVENTION 
     The invention relates to error correction for a computer. 
     BACKGROUND OF THE INVENTION 
     The memory subsystems of today&#39;s computers are under ever-increasing demands for capacity and speed. As speed increases, memory subsystems become increasingly vulnerable to errors caused by transient electrical and electromagnetic phenomena. Therefore, although a well-designed memory subsystem is extremely reliable, even the best memory subsystem has the possibility of a memory device failure. 
     Memory device failures fall generally into two categories. The first is a soft error, which refers to those errors where data stored at a given memory location change, but where subsequent accesses can store the correct data to the same location with no more likelihood of returning incorrect data than from any other location. Soft errors of this type are generally caused by loss of charge in the DRAM cell. The second type of error is a hard error, which refers to those errors in which data can no longer reliably be stored at a given memory location. Either of these types of errors can lead to catastrophic failure of the memory subsystem. 
     In an effort to minimize failures due to memory subsystem errors, various error checking schemes have been developed to detect, and in some cases correct, errors in data read from memory. The most simple of the error checking schemes is parity. In a byte-wide parity system, one extra parity bit is appended to every eight bits of data. For &#34;even parity&#34; systems, the parity bit is set such that the total number of ones in the nine-bit word is even. For &#34;odd parity&#34; systems, the parity bit is set to make the total number of ones odd. When data is read from memory, if one of the nine bits changes from one to zero or vise versa, the parity will be incorrect and the error will be detected. This system is limited, however, because there is no way to know which of the nine bits changed. Therefore, single bit errors can only be detected, not corrected. Also, if two bits change, the parity will again be correct and no error will be detected. Parity therefore is capable of detecting only odd numbers of bit errors. 
     While detection of errors is very useful, it also is desirable to be able to correct certain errors. Error correcting codes (&#34;ECCs&#34;) have been developed that both detect and correct certain errors. Generally speaking, the goal of an ECC is to correct the largest possible number of errors with the smallest possible overhead (in terms of extra bits and wait states) to the system. 
     The &#34;Hamming codes&#34; constitute one well-known class of ECCs and are widely used for error control in digital communications and data storage systems. A detailed description of the Hamming Codes is found in Lin et al., &#34;Error Control Coding, Fundamentals and Applications&#34;, Chapter 3 (1982). One subclass of the Hamming codes that is particularly well-suited for memory subsystems includes the single-error-correcting and double-error detecting (SEC-DED) codes. In these codes, the check bits are generated prior to data being written to memory using a parity-check matrix implemented in ECC hardware. In the (72, 64) Hamming code, 8 check bits are generated for 64 bits of data. The check bits are then stored in memory together with the data. When a memory read occurs, the ECC hardware retrieves both the data and the corresponding check bits from memory. The ECC hardware then applies the parity check matrix to the data and the check bits, producing &#34;syndrome bits&#34;. If the syndrome bits are all zeros, this indicates there are no errors. If the syndrome bits contain ones, the data are possibly invalid. In the case of a single bit error, the syndrome bits will indicate which bit is in error, and thus allow correction. In the case of double bit errors, the error will be detected, but correction is not possible. A complete description of the SEC-DED Hamming codes is found in Lin et al, supra, chapter 16. 
     Another well-known ECC is the &#34;Reed-Solomon code&#34;, widely used for error correction in the compact disk industry. A detailed description of this ECC is found in Hove et al., &#34;Error Correction and Concealment in the Compact Disc System&#34;, Philips Technical Review, Vol. 40 (1980), No. 6, pages 166-172. The Reed-Solomon code is able to correct two errors per code word. Other conventional ECCs include the b-adjacent error correction code described in Bossen, &#34;b-Adjacent Error Correction&#34;, IBM J. Res. Develop., pp. 402-408 (July, 1970), and the odd weight column codes described in Hsiao, &#34;A Class of Optimal Minimal Odd Weight Column SEC-DED Codes&#34;, IBM J. Res. Develop., pp. 395-400 (July, 1970). The Hsiao codes, like the Hamming codes, are capable of detecting double bit errors and correcting single bit errors. The Hsiao codes uses the same number of check bits as the Hamming codes (e.g., 8 check bits for 64 bits of data), but are superior in that hardware implementation is simplified and the speed of error-detection is improved. 
     One ECC that is particularly advantageous for application to computer memory subsystems is described in co-pending and commonly assigned U.S. Pat. No. 5,490,155, titled &#34;ERROR CORRECTION SYSTEM FOR N BITS USING ERROR CORRECTION CODE DESIGNED FOR FEWER THAN N BITS&#34;, the disclosure of which is hereby incorporated by reference. The ECC described in this prior application, when coupled with a particular data distribution architecture, obtains the advantages of the Hamming codes (SEC-DED) with the same overhead (8 check bits for 64 bits of data), but also is able to correct any single 4-bit wide error. Thus, for a memory subsystem implemented using four-bit dynamic random access memories (X4 DRAMS), the subsystem can withstand complete failure of a single X4 DRAM device with full data correction capability. 
     SUMMARY OF THE INVENTION 
     The present invention includes a method of detecting and correcting errors in a computer, comprising the steps of: beginning a write operation of N data bits to a memory; generating M check bits from the N data bits; writing the N data bits and the M check bits to the memory; reading the N data bits and M check bits from the memory; generating X syndrome bits from the N data bits and the M check bits; and using the X syndrome bits to detect and correct any single bit error within the N data bits and the M check bits, to detect any double bit error within the N data bits and the M check bits, and to detect any four bit error within four adjacent bits of the N data bits. 
     Another aspect of the invention includes a method of detecting and correcting errors in a computer, comprising the steps of: beginning a write operation of N data bits to a memory at a location designated by A address bits; generating M check bits from the N data bits and the A address bits; writing the N data bits and the M check bits to the location; reading the N data bits and M check bits from the location; generating X syndrome bits from the N data bits, the M check bits, and the A address bits; and using the X syndrome bits to detect any single bit error within the A address bits. 
     A further aspect of the invention includes an error detecting and correcting apparatus for a computer having a CPU and a memory, comprising a means for generating M check bits from N data bits upon initiation of a write operation of the N bits from the CPU to the memory; a means for writing the N data bits and the M check bits to the memory; a means for generating X syndrome bits from the N data bits and the M check bits upon initiation of a read operation of the N bits and the M check bits from the memory; and a means for using the X syndrome bits to detect and correct any single bit error within the N data bits and the M check bits, to detect any double bit error within the N data bits and the M check bits, and to detect any four bit error within four adjacent bits of the N data bits. 
     A further aspect of the invention includes an error detecting and correcting apparatus for a computer having a CPU and a memory, which comprises a means for generating M check bits from N data bits and A address bits upon initiation of a write operation from the CPU a location in the memory designated by the A address bits, a means for writing the N data bits and the M check bits to the location in memory, a means for generating X syndrome bits from the N data bits, the M check bits, and the A address bits upon initiation of a read operation from the location in the memory; and a means for using the X syndrome bits to detect any single bit error within the A address bits. 
     Another aspect of the invention includes an error detecting and correcting apparatus for a computer having a CPU and a memory, which comprises a means for generating M check bits from N data bits upon initiation of a write operation of the N bits from the CPU to the memory, a means for writing the N data bits and the M check bits to the memory, a means for generating X syndrome bits from the N data bits and the M check bits upon initiation of a read operation of the N bits and the M check bits from the memory, a means for using the X syndrome bits to detect errors within the N data bits. This means for generating the M check bits and the means for generating the X syndrome bits comprise a first ECC module and a second ECC module, the first ECC module generating one half of the M check bits and the X syndrome bits and the second ECC module generating the other half of the M check bits and the X syndrome bits. This means further comprises a means for communicating partially generated check bits and syndrome bits between the first and second ECC modules. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram of a conventional memory subsystem; 
     FIG. 2 is a block diagram of a processor and memory system in accordance with the invention; 
     FIG. 3 is a block diagram of an ECC system in accordance with FIG. 2; 
     FIG. 4 is a block diagram showing interconnection between the ECC modules of FIG. 3; 
     FIG. 5 is a parity-check matrix in accordance with one embodiment of the invention; 
     FIG. 6 is a syndrome table in accordance with the embodiment of FIG. 5; 
     FIG. 7 is a parity-check matrix in accordance with another embodiment of the invention; 
     FIG. 8 is a syndrome table in accordance with the embodiment of FIG. 7; 
     FIG. 9 is a parity-check matrix in accordance with yet another embodiment of the invention; 
     FIG. 10 is a syndrome table in accordance with the embodiment of FIG. 9. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments will now be described with reference to the accompanying figures. 
     FIG. 1 is a block diagram representation of a conventional memory subsystem 11 for a computer 3. The computer 3 is associated with a display 5, a keyboard 7, and a disk drive 9 in a conventional fashion. The memory subsystem 11 communicates with a central processing unit (CPU) 13 having an address bus 15 and a data bus 17. The address bus 15 is connected to a cache and memory control (CMC) application specific integrated circuit (ASIC) 19. The data bus 17 is connected to cache memory 21 and to a data memory control (DMC) 23. CMC 19 has an address bus 25 that communicates with a peripheral component interface (PCI) 27 and a memory address bus 29 that communicates with memory 31. CMC 19 communicates with cache 21 via bus 33 and with DMC 23 via bus 35. DMC 23 also communicates with memory 31 via data bus 37. 
     FIG. 2 is a block diagram representation of a processor and memory system in accordance with the present invention. The system comprises a CPU 41, which is preferably the P54C processor available from Intel. A companion CPU socket is also provided for dual processor implementations, and is preferably the P54CM socket available from Intel. Both CPU 41 and companion CPU socket 43 communicate with a debug port 45 via a debug signal line 46 and with an interrupt controller 47 via a non-maskable interrupt (NMI) line 49. 
     On-board cache 51 is provided, preferably 512K L2 cache, which communicates with CPU 41 via processor data (PD) bus 53 and processor address (PA) bus 55. The PD bus 53 is 72 bits wide, and is also applied to two special purpose data path ASICs called &#34;BINERs&#34; (57A, 57B). CMC 59 communicates with PA bus 55 and also with processor control bus 61. CMC provides BINER control line 63 to BINERs 57A, 57B and also memory control line 65 to memory 67. Memory 67 comprises eight 72 bit SIMMs, SIMM 1-SIMM 8. A basecamp processor connector 69 provides peripheral interface for both the PCI bus 71 and APIC bus 73. Additional control signals are provided from the CMC 59 to the connector 69 via sideband signal line 75. A clock 77 provides system timing. 
     Referring now to FIG. 3, an ECC module is implemented within each of BINER 57A, 57B. The modules are identical, but one is designated as master (79A) and the other as slave (79B). Modules 79A, 79B together provide 64 bits of data and eight check bits to memory 67, implemented in the form of 18 X4 DRAM devices (81). For the sake of simplicity, only five of the DRAM devices are shown in FIG. 3 (DRAM 81(0), 82(1), and 81(15-17)). ECC master module 79A provides memory data bits 0-15 and 32-47 to X4 DRAMs 81(0-7), respectively. Module 79A also provides memory check bits 4-7 to X4 DRAM device 81(17). ECC slave module 79B provides memory data bits 16-31 and 48-63 to X4 DRAM devices 81(8-15), respectively, and also provides memory check bits 0-3 to X4 DRAM device 81(16). 
     FIG. 4 is another diagram illustrating the interplay between ECC slave module 79B and ECC master module 79A. Master module 79A receives processor data bits 0-15 and 32-47 from the PD bus 53. ECC slave module 79B receives processor data bits 16-31 and 48-63, also from PD bus 53. The 32 bits of the PCI bus 71 are also split between the two modules, with bits 0-15 going to master module 79A and bits 16-31 going to slave module 79B. In order to generate the correct syndrome code in accordance with the embodiments described in detail below, each ECC module decodes a total of 32 bits of data and four check bits. In addition, each module needs to provide the other with its own four check bits. Therefore, as shown in FIG. 4, each module drives the partial four check bits via PEGOUT&lt;3:0&gt; and receives the four partial check bits via PEGIN&lt;3:0&gt;. A total of eight pins are used to transfer partial check bits to generate proper syndrome/check bits. When an error is detected and is correctable, a total of eight syndrome bits must be transferred between the two modules. The syndrome bits are driven via PECOUT&lt;7:0&gt; and received via PECIN&lt;7:0&gt;. 
     This transfer of partial check bits and syndrome codes between the two modules, and the division of labor between the two modules, can be avoided if an ASIC package is used of sufficient capacity to implement all of the ECC logic in a single chip. The choice of whether to use two modules or a single ASIC is driven primarily by cost considerations and the availability of large scale ASICs. Clearly, if a single ASIC is used, the design is simplified and there is some reduction in overhead due to the exchange of partial check bits and syndrome codes no longer being necessary. 
     FIG. 5 illustrates the parity-check matrix for an error correction code in accordance with one embodiment of the invention. As with the (72, 64) Hsiao codes, and the codes described in the prior U.S. Pat. No. 5,490,153 the ECC in accordance with this embodiment is able to correct random single bit errors and detect random double bit errors. In addition, the ECC in accordance with this embodiment is able to detect all three and four bit errors within the same nibble without requiring additional check bits. 
     In this embodiment, a pair of check bits and data bits are mixed into the same nibble to ensure that the multiple-bit syndrome codes are not mapped into the same syndrome codes of the single-bit errors. There are 72 distinct syndrome codes assigned for the single-bit correctable errors. Thus, there are only 183 possible syndrome codes to use for detecting a total of 2646 cases of multiple-bit errors (2556 cases for the random double-bit errors, 72 cases for the 3-bit errors, and 18 cases for the 4-bit per nibble errors). Therefore, most of the multiple-bit syndrome codes are shared by several error conditions. 
     To generate the check bits from 64 data bits, an exclusive OR (XOR) operation is performed on the data bits in the locations of each row in the matrix of FIG. 5 having ones. Implementation of the XOR function within an ASIC using Boolean logic is straightforward, and will not be described herein in detail. Performing this operation for each of the 8 rows produces the 8 check bits. In accordance with the implementation shown in FIGS. 3 and 4, it will be understood that this operation is actually performed in two halfs, one by each ECC module. For the sake of simplicity in the following discussion, however, the ECC process will be described as a single operation. 
     The 64 bits of data and 8 check bits are then written to memory 31. In order to detect 4-bit errors, all 4-bits from each X4 DRAM device must connect to the same ECC module with correct ordering, as described above with reference to FIG. 3. 
     When a read operation occurs, the 64 data bits and 8 check bits are read from memory, and the XOR operation is again performed on each row, this time including all 72 bits. By performing this operation on each of the 8 rows of the matrix of FIG. 5, 8 syndrome bits S(0-7) are produced. 
     FIG. 6 illustrates the syndrome table corresponding to this embodiment. As indicated in the upper left hand corner of the table, if all 8 syndrome bits are all zero (00 in hex), no error is detected. If the syndrome bits contain ones, either a single bit (DB), check bit (CB) or multiple bit error (MBE) is detected. As is apparent from FIG. 6, if the error is a single bit error, i.e., either a single data bit error or a single check bit error, the bit in error is determined by the syndrome table and can be corrected. For multiple bit errors, the error is detected but not corrected, and preferably a report of the error is made to the operating system. 
     For some applications, having check bits and data bits grouped in the same nibble may increase hardware requirements by limiting the choice of certain types of DRAMS, or may add an additional wait state. For such applications, a second embodiment of the invention has been developed wherein the check bits are grouped together and are separated from the data bits. This embodiment maintains the advantages of the embodiment described above, however, the three-bit error detection is no longer applied to the check bits (nibbles 16 and 17). Any three-bit error of the check bits will cause a mis-correction of one of data bits 12-15 or 32-35. 
     The parity-check matrix for the second embodiment of the invention is shown in FIG. 7, and its corresponding syndrome table is shown in FIG. 8. Coding and decoding in accordance with this embodiment is identical to that described above with respect to the first embodiment, and will not be repeated. 
     In both the first and second embodiments, the parity-check matrices are optimized by having the same number of ones (27) in each row. In addition, the total number of ones in the matrices is minimized to reduce hardware requirements. 
     The first and second embodiments of the invention described above apply error checking to the memory data bus only. However, the error correction code of the invention can also be applied advantageously to the address portion without requiring additional check bits. If one were to try to apply an error detection scheme directly to the memory address bus, even a simple scheme like parity, the hardware cost of the extra bit most likely would be prohibitive. Even if one could afford the cost of an extra bit for parity, only odd numbers of bit errors could be detected. In accordance with the present invention, available syndrome codes can be employed to detect all random single and double bit errors on the address bus without requiring additional bits. Thus error detection capabilities are realized on both processor and memory address buses at essentially zero cost in terms of overhead. 
     The parity-check matrix for this third embodiment of the invention is shown in FIG. 9, where &#34;x&#34; indicates addresses that are not covered (the first 3 address bits are excluded because the memory word size is 64 bits wide; the last 4 address bits are excluded because in this embodiment the maximum supported memory size is 256 MB). The corresponding syndrome table is shown in FIG. 10, where &#34;UNCER&#34; refers to an un-correctable error. Generation of the check bits and syndrome bits is the same as that described above with respect to the first embodiment, and will not be repeated. However, because the address bits are also coded in this embodiment, the CMC 59 must transfer the address information to the BINERs for encoding and decoding purposes during CPU read or writeback cycles. One option for achieving this transfer is to transfer all of the address bits from the CMC 59 to the BINERs 57A, 57B via line 63. This is the most direct approach, but as a practical matter pin limitations (typically 4 bits) may result in an excessive number of clock cycles being needed to transfer all 25 address bits. These extra clock cycles could degrade CPU performance. 
     Another approach is to generate the syndrome bits for the address portion within the CMC 59, and then transfer these 8 partial syndrome bits to the BINERs for encoding or decoding. This requires only two clock cycles, which will not add additional overhead to the normal memory cycles. This approach does, however, require some additional logic in the CMC 59. 
     For the address portion, the error correction code of this embodiment detects, but does not correct, single and double-bit errors. Correction on the address bus is not possible because a single bit error on the address bus will result in invalid data being returned--thus making it impossible to generate the syndrome bits. Detection of single and double-bit errors is, however, both adequate and highly advantageous because, when errors are detected on the memory address bus, the CMC can terminate and abort the current cycle without returning the data to the requester. Accordingly, further corruption is prevented. Also, information regarding the errors, both on the address bus and on the data bus, can be reported to the operating system or to a special archive. 
     Reporting of errors is a very useful function because it provides important information about the faults to the users or to service personnel. This allows faults to be easily isolated, thus minimizing the system&#39;s down time. In accordance with the invention, any error that is detected or corrected can be reported to the operating system or stored in a special archive for later use during servicing. 
     Various embodiments of the invention have been described above in detail with reference to the accompanying figures. However, the invention is not so limited. One of ordinary skill in the art will recognize that the error correction methods, hardware, and codes described may be applied to different memory and data communication systems, different processors with various bit widths, and in various combinations and permutations. Accordingly, the invention is not limited to the described embodiments, but rather is limited only by the scope of the appended claims.