Abstract:
In order to further develop a circuit arrangement ( 100 ) as well as a method for generating at least one drive signal for at least one synchronous rectification switch of at least one flyback converter in such way that an improved and simpler thermal management can be combined with a significant cost reduction as well as with a higher efficiency, it is proposed to generate the drive signal for said synchronous rectification switch as a function of at least one oscillating signal controlling the synchronous rectification switch, of at least one constant delay time, of at least one variable delay time, and of at least one Boolean OR function.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a circuit arrangement for generating drive signals for a synchronous rectification switch of a flyback converter. The present invention further relates to a method for generating at least one drive signal for at least one synchronous rectification switch of at least one flyback converter, in particular at least one actively clamped bidirectional flyback converter. 
     BACKGROUND OF THE INVENTION 
     An actively clamped bidirectional flyback converter is disclosed in the article “Experimental Analysis Of A Flyback Converter With Excellent Efficiency” as presented by U. Boeke, D. Itzenga, K. Rigbers, and R. W. De Doncker in Proceedings of Applied Power Electronic Conference (APEC) from Mar. 19 to 23, 2006, in Dallas, Tex. 
     This actively clamped bidirectional flyback converter is based on the reference document “Actively-Clamped Bidirectional Flyback Converter” by Gang Chen, Yim-Shu Lee, S. Y. Ron Hui, Dehong Xu, Yousheng Wang, IEEE Transactions on Industrial Electronics, volume 47, number 4, August 2000, pages 770 to 779. This converter does not include any current sensors. The on-time of the synchronous rectifier switch is taken from the pulse-width-modulator in combination with a “turn-on delay” sub-circuit. 
     EP 1 148 624 A1 describes an integrated circuit to drive a power M[etal-]O[xide-]S[emiconductor]F[ield]E[ffect]T[ransistor] acting as synchronous rectifier (cf. also Fabrizio Librizzi, and Pietro Scalia, “STSRx family: Mixed-signal ICs to drive synchronous rectifiers in isolated SMPSs”, STMicroelectronics, application note AN1288, July 2000). 
     U.S. Pat. No. 6,462,965 B1 discloses a sub-circuit to drive a power MOSFET as synchronous rectifier switch by means of one current transformer per output. 
     US 2003/0090914 A1 reveals a circuit including a special sub-circuit to drive a power MOSFET as synchronous rectifier by means of a second current shunt sensor. 
     Texas Instruments&#39; integrated control circuit type UCC2891 and UCC2897 includes only two time delay functions to control the on-time of the two power semiconductors on the primary converter side (cf. Texas Instruments, UCC2891 Current Mode Active Clamp PWM Controller, data sheet, July 2004; Texas Instruments, UCC2897, Current Mode Active Clamp PWM Controller, data sheet, April 2005). The use of synchronous rectifier switches is only illustrated for the application of a forward converter and does not include control circuits for the timing of the synchronous rectifier switches. 
     The use of delayed turn on time signals to turn on both power semiconductors of a flyback converter with synchronous rectification is disclosed in the article “High efficiency flyback converter using synchronous rectification” by I. D. Jitaru, Proceedings of Applied Power Electronics Conference (APEC) from Mar. 10 to 14, 2002 in Dallas, Tex., pages 867 to 871. This converter does not use the active clamping principle. Thus, the two switches of this converter are explicitly never turned on at the same time. 
     U.S. Pat. No. 6,888,728 B2 includes timing circuits on the secondary side of the transformer. The timing circuits include a comparator requiring an additional supply voltage on the secondary side of the power converter. This overall effort of sub-circuits to drive the synchronous rectifier switches on the secondary side of the transformer is very high and generates significant costs. The greatest disadvantage of U.S. Pat. No. 6,888,728 B2 is the higher component effort meaning also higher cost. 
     JP 2005-198438 A describes a load resonant half-bridge converter with synchronous rectification. The component count of this known circuit is very high; apart from that, the load resonant converter includes a second power transformer plus a shunt resistor both generating additional power losses and thus increasing the thermal management effort. The greatest disadvantage of JP 2005-198438 A is the use of a second power transformer to monitor the input current of the load resonant circuit on the secondary side of transformer; this generates significant loss in the second power transformer. 
     Regarding the technological background of the present invention, reference can finally be made to U.S. Pat. No. 5,057,986 as well as U.S. Pat. No. 5,402,329. 
     SUMMARY OF THE INVENTION 
     It is, inter alia, an object of the invention to provide an improved generation of drive signals for a synchronous rectification switch of a flyback converter. The invention is defined by the independent claims. Advantageous embodiments are defined by the dependent claims. 
     Particular embodiments may result in an improved and simpler thermal management combined with a significant cost reduction as well as with a higher efficiency. 
     Advantageous embodiments of the present invention are principally based on the idea to control a synchronous rectifier, more particularly to provide a control circuit for at least one actively clamped bidirectional flyback converter with a synchronous rectifier and with a transformer isolation making use of an oscillating signal which controls the synchronous rectification switch. 
     According to a particular refinement of the present invention, at least part of the flyback converter can be turned-off with a variable delay time. The delay time interval is a function of the relative converter power level with minimum delay, which is independent of the power level. 
     In a preferred embodiment of the present invention, at least one voltage sensor can measure the drop across the low side switch on the primary side which gives a digital “high” output in case the sensed drain-source voltage of said low side switch is negative due to the fact that the current in said low side switch is flowing from source to drain. 
     Preferably, this digital output of the voltage sensor is ORed with at least one second signal to drive the synchronous rectifier switch. Said second signal is a delayed signal of at least one inverse P[ulse-]W[idth]M[odulation] signal. 
     Advantageous embodiments of the present invention have the advantage of a minimum effort to sense electrical signals. 
     A further advantage of certain embodiments of the present invention is that the cost of the circuit to drive the synchronous rectifier MOSFET can be significantly reduced; in addition thereto, also the power losses of the actively clamped bidirectional flyback converter with synchronous rectification can be reduced. The latter advantage can be used to reduce the effort for thermal management, i.e. to transfer the heat out of the preferably closed housing of the circuit arrangement of the present invention. 
     Apart from that, advantageous embodiments of the present invention
         enable an improved design freedom for flat displays, such as for L[iquid]C[rystal]D[isplay] T[ele]V[ision]s,   enable compact L[ight-]E[mitting]D[iode] lamp drivers with low cooling effort, and   improve the functionality of power conversion modules.       

     Embodiments of the present invention can be applied in order to improve electronic circuits in consumer products, such as in L[iquid]C[rystal]D[isplay] T[ele]V[ision]s or in L[iquid]C[rystal]D[isplay] computer monitors, in L[ight-]E[mitting]D[iode] lamp drivers, in battery chargers and in battery dischargers. 
     These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically shows a principle diagram of a preferred embodiment of a circuit arrangement according to the present invention being operated according to the method of the present invention; and 
         FIG. 2  schematically shows a principle diagram of qualitative time functions in steady state, referring to the method of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
       FIG. 1  shows a block diagram of a preferred embodiment of the circuit arrangement  100  according to the present invention. The circuit arrangement  100  comprises an actively clamped bidirectional flyback converter with four power semiconductors Q 1 , Q 2 , Q 3 , Q 4 ; each of these power semiconductors Q 1 , Q 2 , Q 3 , Q 4  is implemented as a transistor unit, in particular as a metal-oxide semiconductor (MOS) or as a metal-oxide semiconductor field effect transistor (MOSFET). 
     Two of these transistors, namely the first transistor Q 1  and the third transistor Q 3  are located on the primary side of a power transformer Tr 1 ; the other two of these transistors, namely the second transistor Q 2  and the fourth transistor Q 4  are located on the secondary side of the power transformer Tr 1 . The second transistor Q 2  acts as synchronous rectifier; the fourth transistor Q 4  is a semiconductor switch or active clamping switch designed to actively confine or to actively delimit the voltage load of the synchronous rectification switch Q 2 . 
     As will be explained in more detail below, a single control circuit generates the driver signals to turn-on and to turn-off all four transistors Q 1 , Q 2 , Q 3 , Q 4  of the flyback converter. In this context, it will be appreciated by a man skilled in the art that only the flyback power converter is addressed because such addressing is the most cost-effective circuit topology being a key feature for the dominant range of applications. 
     The so-called power transformer Tr 1  in the flyback converter is practically a coupled inductor; that, and some other functions, is the reason why the flyback converter does not have the disadvantages of switched mode power supplies derived from the forward-based converter topology; the disadvantages of forward-based topologies is the key objective of U.S. Pat. No. 6,888,728 B2 to effectively prevent the generation of through currents in the two series connected synchronous rectifier switches. 
     Contrary thereto, the circuit arrangement  100  according to the present invention has a significant lower effort to generate drive signals for the synchronous rectifier switches being realized by the second transistor Q 2  as well as by the fourth transistor Q 4 . These are practically the gate drive transformer Tr 2  (with at least one preconnected driver IC 4 ) and the optocoupler IC 5  on the secondary side of the transformer Tr 1 . 
     It will be appreciated by a man skilled in the art that neither any timing circuit nor any comparator orr any amplifier is required on the secondary side of the flyback converter; all required timing and logic functions are on the primary side of the flyback converter where they can be integrated in one single control I[ntegrated]C[ircuit]. 
     A voltage sensor VS is implemented as a comparator for measuring the voltage drop of the first transistor Q 1 . The voltage sensor VS generates a logic output signal V I1  
         being “1” if the voltage sensor VS measures a negative drain-source voltage of the first transistor Q 1 , and   being “0” if the voltage sensor VS measures a vanishing or positive drain-source voltage of the first transistor Q 1 .       

     In this way, the voltage sensor VS can detect a negative drain-source current at the first transistor Q 1 . A negative current I 1 (t) (cf.  FIG. 2 ) is present at least in the time interval from t 3  to t 5  (cf.  FIG. 2 ) because of the active clamping principle. 
     Assigned to said voltage sensor unit VS,  FIG. 1  depicts a first integrated circuit IC 1 , namely a high voltage driver for power metal-oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT) driver with independent high and low side referenced output channels; the proprietary high voltage insulator coating (HVIC) technology as well as the latch immune complementary metal oxide semiconductor (CMOS) technology enable a ruggedized monolithic construction of said first integrated circuit IC 1 . 
     The logic output signal V I1  from the voltage sensor VS as well as the delayed time signal V PWM.Q2  are the two input signals of a logic unit L 5 , said logic unit L 5  comprising an OR function. The difference of the output signal of this OR function minus the output signal of a third integrated circuit IC 3  providing a positive quadruple 2-input AND function (=the difference between the voltage of the output signal of the logic unit L 5  and the voltage of the output signal of the third integrated circuit IC 3 ) is the signal V GS.Q2  (cf.  FIG. 2 ) being the drive signal to turn-on and to turn-off the second transistor Q 2 . 
     In other words, the voltage sensor VS can measure the voltage drop across the low side switch Q 1  on the primary side which will give a digital “high” output (V I1 =“1”) if the sensed drain-source voltage of the low side switch Q 1  is negative due to the fact that the current in the low side switch Q 1  is flowing from the source of the low side switch Q 1  to the drain of the low side switch Q 1 . 
     This digital output V I1  of the voltage sensor VS is ORed with a second signal to drive the synchronous rectifier switch Q 2  wherein this second signal is a delayed signal of the inverse P[ulse-]W[idth]M[odulation] signal; the inverse P[ulse-]W[idth]M[odulation] signal is generated by an inverse P[ulse-]W[idth]M[odulation] unit PWMi being a component of a second integrated circuit IC 2 , namely of a monolithic timing circuit. 
     Accordingly, it is a further advantage of the converter circuit  100  according to the present invention that a shunt resistor is not required to generate the timing signals of the synchronous rectifier switches Q 2 , Q 4 . Instead, the negative drain-source voltage of the first transistor Q 1  is additionally monitored with the voltage sensor to finally determine the on-time of rectifier switch Q 2 . 
     As can be further taken from  FIG. 1 , a sixth integrated circuit IC 6 , namely a three-terminal programmable shunt regulator diode is arranged at the output stage of the circuit arrangement  100 . This monolithic IC 6  voltage reference operates as a low temperature coefficient zener diode being programmable from reference voltage to 36 Volt with at least one external resistor, preferably with two external resistors. 
     Close to said sixth integrated circuit IC 6 , a seventh integrated circuit IC 7  comprising an optocoupler is arranged behind an eighth integrated circuit IC 8 . 
     With reference to  FIG. 2 , the second transistor Q 2  works as synchronous rectification switch which is turned-off at time point t 3  with the falling edge of the output signal of the inverse P[ulse-]W[idth]M[odulation] unit PWMi. At this time point t 3 , the third transistor Q 3  is also turned-off, and the changing voltage V DS.Q1  (cf.  FIG. 2 ) changes the slope of the current in the second transistor Q 2 , with said changing voltage V DS.Q1  becoming slightly negative between in the time interval from t 4  to t 5  (cf.  FIG. 2 ) because of the active clamping principle. 
     The second transistor Q 2  is turned-off with a variable delay time. The delay time interval is a function of the relative converter power level. A minimum delay time is adjusted with the second resistor R 2  in a time delay circuit TDC in  FIG. 1 . This time delay is in the order of some percentage of the time period t 7 =1/fs (cf.  FIG. 2 ) wherein fs is the switching frequency. This time delay is independent from the power level. 
     Assigned to said time delay circuit TDC,  FIG. 1  depicts the monolithic timing circuit IC 2 
         providing full compatibility with complementary metal oxide semiconductor (CMOS), transistor-transistor logic (TTL), and metal oxide semiconductor (MOS) logic and   operating at frequencies up to two Megahertz.       

     The respective third integrated circuit IC 3  providing positive quadruple 2-input AND function is arranged
         between the first integrated circuit IC 1  and the time delay circuit TDC as well as   behind the time delay circuit TDC.
 
The outputs of this positive quadruple 2-input AND function are fully buffered for highest noise immunity and for pattern insensitivity of output impedance.
       

     The above-identified control technique does not prevent a conduction of the inverse diode of the second transistor Q 2  for example from time point t 5  to time point t 6  in  FIG. 2 . However, it has been found from measurements that such conduction of the inverse diode of the second transistor Q 2  does not influence the power losses of the flyback converter if the relative power level is between zero percent and ninety percent. 
     Only for power levels between ninety percent and hundred percent, a further reduction of losses in the second transistor Q 2  can be achieved. However, this requires a much higher component effort as given in documents EP 1 148 624 A1, U.S. Pat. No. 6,462,965 B1, or US 2003/0090914 A1. 
     All in all, a special control technique generates the drive signal of the synchronous rectifier power semiconductor to be used in the actively clamped bidirectional flyback converter according to the present invention. This control technique requires a minimum effort to sense electrical signals. 
     In the claims, the first power semiconductor (Q 1 ) may in particular be at least one first transistor unit, for example at least one first metal-oxide semiconductor (MOS) or at least one first metal-oxide semiconductor field effect transistor (MOSFET). The second power semiconductor (Q 2 ) may in particular be at least one second transistor unit, for example at least one second metal-oxide semiconductor (MOS) or at least one second metal-oxide semiconductor field effect transistor (MOSFET). The third power semiconductor (Q 3 ) may in particular be at least one third transistor unit, for example at least one third metal-oxide semiconductor (MOS) or at least one third metal-oxide semiconductor field effect transistor (MOSFET). The fourth power semiconductor (Q 4 ) may in particular be at least one fourth transistor unit, for example at least one fourth metal-oxide semiconductor (MOS) or at least one fourth metal-oxide semiconductor field effect transistor (MOSFET). The transformer unit (Tr 1 ) may in particular be at least one power transformer. The drive signal for the synchronous rectification switch may be generated as a function of at least one oscillating signal controlling the synchronous rectification switch, of at least one constant delay time, of at least one variable delay time, in particular of the detection of the current I 1 (t) in the primary winding of the transformer unit (Tr 1 ) generating the variable delay time, and of at least one Boolean OR function, in particular provided by at least one logic unit (L 5 ). The first integrated circuit (IC 1 ) may in particular be at least one high voltage driver of power metal-oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT) driver. The second integrated circuit (IC 2 ) may in particular be at least one timing circuit, for example at least one monolithic timing circuit. The fourth integrated circuit (IC 4 ) may in particular be at least one diode or driver, for example by at least one rectification diode. The fifth integrated circuit (IC 5 ) may in particular be at least one optocoupler unit. The sixth integrated circuit (IC 6 ) may in particular be at least one programmable shunt regulator diode, for example at least one three-terminal programmable shunt regulator diode. The seventh integrated circuit (IC 7 ) may in particular be at least one optocoupler. 
     It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim. The word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and/or by means of a suitably programmed processor. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. 
     List of Reference Signs 
     
         
           100  circuit arrangement comprising actively clamped bidirectional flyback converter 
         IC 1  first integrated circuit, in particular high voltage driver of power metal-oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT) driver with independent high and low side referenced output channels 
         IC 2  second integrated circuit, in particular timing circuit, for example monolithic timing circuit 
         IC 3  third integrated circuit, in particular providing positive quadruple 2-input AND function 
         IC 4  fourth integrated circuit, in particular diode or driver, for example rectification diode 
         IC 5  fifth integrated circuit, in particular optocoupler 
         IC 6  sixth integrated circuit, in particular programmable shunt regulator diode, for example three-terminal programmable shunt regulator diode 
         IC 7  seventh integrated circuit, in particular optocoupler or optocoupling unit 
         IC 8  eighth integrated circuit 
         I 1 (t) first current 
         I 2 (t) second current 
         L 1  first logic unit, in particular comprising AND function 
         L 2  second logic unit, in particular comprising AND function 
         L 3  third logic unit, in particular comprising AND function 
         L 4  fourth logic unit, in particular comprising AND function 
         L 5  fifth logic unit, in particular comprising OR function 
         OS oscillator unit 
         PWM P[ulse-]W[idth]M[odulation] unit 
         PWMi inverse P[ulse-]W[idth]M[odulation] unit 
         Q 1  first power semiconductor, in particular first transistor unit, for example first metal-oxide semiconductor (MOS) or first metal-oxide semiconductor field effect transistor (MOSFET), of flyback converter 
         Q 2  second power semiconductor, in particular second transistor unit, for example second metal-oxide semiconductor (MOS) or second metal-oxide semiconductor field effect transistor (MOSFET), of flyback converter 
         Q 3  third power semiconductor, in particular third transistor unit, for example third metal-oxide semiconductor (MOS) or third metal-oxide semiconductor field effect transistor (MOSFET), of flyback converter 
         Q 4  fourth power semiconductor, in particular fourth transistor unit, for example fourth metal-oxide semiconductor (MOS) or fourth metal-oxide semiconductor field effect transistor (MOSFET), of flyback converter 
         R 1  first resistor unit 
         R 2  second resistor unit 
         TDC time delay circuit 
         Tr 1  first transformer unit, in particular power transformer 
         Tr 2  second transformer unit, in particular gate drive transformer 
         V dd  supply voltage 
         V DS.Q1  changing voltage changing slope of current in second power semiconductor Q 2   
         V GS.Q2  output signal of fifth logic unit L 5   
         V I1  output signal, in particular logic output signal, of voltage sensor unit VS 
         VIB voltage isolation barrier 
         V in  input voltage 
         V out  output voltage 
         V PWM.Q2  delayed time signal 
         VS voltage sensor unit, in particular comparator unit