Abstract:
A voltage level translator for digital logic circuits provides high level to low level voltage translation with equal rise and fall delays. The voltage level translator may include an input high voltage logic inverter (operating at the high voltage level) and connected to an output low voltage logic inverter operating at the low voltage level via a voltage reduction circuit. A related method for providing high level to low voltage translation may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Furthermore, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 10/460,044, filed Jun. 12, 2003, which is hereby incorporated herein in its entirety by reference. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates to the field of digital electronic circuits and, more particularly, to voltage level translators for translating high voltage levels to low voltage levels in digital integrated circuits.  
         BACKGROUND OF THE INVENTION  
         [0003]    Many modern digital electronic integrated circuits are designed with multiple sections. Some of these sections may operate at different operating voltages based on functional requirements, etc. These different sections interface with one another using voltage translators for providing signal level compatibility. Yet, the ever-decreasing size of integrated circuit chips has necessitated a reduction in operating voltages to avoid latch-up and other operational problems such as electro-magnetic interference (EMI), etc. As a result, the spacing between the conductors internal to the device have correspondingly decreased.  
           [0004]    The use of lower operating voltages also reduces power consumption as well as the amount of heat generated from power dissipation, which can be particularly acute for relatively small device sizes. At the same time, functional requirements for interfacing with other devices typically require signal levels to be at significantly higher voltage levels, have minimum rise and fall times, and low average and peak power dissipation.  
           [0005]    Referring to FIG. 1, a typical voltage translator  1  in accordance with the prior art for translating a high voltage input level to a lower voltage output is illustratively shown. The circuit includes two cascaded inverters. The pull-down NMOS transistors NH 1 , NH 2  of both inverters are connected to a common ground. The pull-up transistor PH 1  of the input inverter is a high threshold voltage PMOS transistor connected to the higher voltage level V DD     —     HIGH , and the pull-up transistor PH 2  of the output inverter is connected to the lower voltage level V DD     —     LOW .  
           [0006]    The above-described architecture does not provide equal delays and transition times for rising and falling edges. This is because the PMOS transistor of the output inverter requires the voltage at its gate to drop from V DD     —     HIGH  to (V DD     —     LOW −V T     —     LOW ). Yet, the NMOS transistor requires its input voltage to rise from 0 to only V T     —     LOW .  
           [0007]    Simulation results for a 3.3V to 1.2V translation using the voltage translator of FIG. 1 are shown in FIG. 2. As may be seen, the rise and fall delays and transition times are unequal. Similarly, the simulation results for a 2.5V to 1.2V translation using the voltage translator of FIG. 1 are shown in FIG. 3. Once again, the rise and fall delays and transition times may be observed to be unequal.  
           [0008]    U.S. Pat. No. 5,422,523 provides an example of a device for translating low voltages to high voltages. Even so, this method is generally unsuitable for converting from high voltages to low voltages.  
           [0009]    Furthermore, U.S. Pat. No. 6,236,256 discloses a device for translating high voltages to low voltages. As shown in FIG. 4 thereof, the &#39;256 patent describes a converter including an input sampler for sampling an input signal, a storage node for temporarily storing the sampled value, and precharge circuitry for precharging and discharging internal storage node capacitances. A latch is also included for retaining the sensed logic level, and an output low voltage inverter provides the output signal.  
           [0010]    The invention described in the &#39;256 patent does not provide equal rise and fall times for the output signal. In fact, the rise and fall times are likely to be significantly different. This is because the high-to-low transition of the output depends on the resistance of the SAMPLE switch and input signal rise-time, while the low-to-high transition depends only on the PRECHARGE value. This method is also relatively complex and expensive to implement.  
         SUMMARY OF THE INVENTION  
         [0011]    An object of the invention is to provide a device and method for providing voltage translation for signals from a circuit operating at a higher voltage level to a circuit operating at a lower voltage level.  
           [0012]    Another object of the invention is to provide high-to-low voltage translation in a device having a relatively small device size.  
           [0013]    A further object of the invention is to provide high-to-low voltage translation with equal rise and fall delays and equal rise and fall transition times.  
           [0014]    Yet another object of the invention is to provide a high-to-low voltage translator with reduced propagation delay.  
           [0015]    Another object of the invention is to provide a high-to-low voltage translator with reduced power dissipation.  
           [0016]    These and other objects, features, and advantages of the invention are provided by a digital electronic circuit for providing high level to low level voltage translation with equal rise and fall delays and equal rise and fall transition times. In particular, the electronic circuit may include an input high voltage logic inverter operating at the high level voltage. The input high voltage logic inverter may be connected to an output low voltage logic inverter operating at the low voltage level through a voltage degradation circuit.  
           [0017]    The voltage degradation circuit may include a plurality of series-connected transistors each biased to provide a fixed voltage drop. The voltage degradation circuit may provide a voltage that is greater than one threshold voltage below the low voltage level in the high state. This advantageously reduces output leakage current as well as the possibility of “crowbar” conduction. Further, the voltage degradation circuit may also provide a voltage that does not exceed a specified upper voltage rating of the low voltage transistors to reduce the possibility of transistor breakdown. An additional transistor may also be connected to feedback the output of the low level inverter to its input to further reduce output leakage current and the possibility of crowbar conduction.  
           [0018]    Additionally, the voltage degraduation circuit may include a low voltage transistor having a common terminal connected to the low voltage supply, and an output terminal connected to the output terminal of a second transistor. The second transistor may have a control terminal connected to the input of the voltage translation circuit, and a common terminal providing the complementary output from the voltage translation circuit. The two complementary outputs may drive the control terminals of the two transistors in the output low voltage inverter.  
           [0019]    A method aspect of the invention is for providing high level to low-level voltage translation with equal rise and fall delays and equal rise and fall transition times. More particularly, the method may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Further, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    [0020]FIG. 1 is a schematic circuit diagram of a voltage converter in accordance with the prior art.  
         [0021]    [0021]FIG. 2 is a simulated timing diagram of the prior art voltage converter of FIG. 1 for the case where V DD     —     HIGH =3.3V and V DD     —     LOW =1.2V (i.e., a voltage difference of 2.1V).  
         [0022]    [0022]FIG. 3 is a simulated timing diagram of the prior art voltage converter of FIG. 1 for the case where V DD     —     HIGH =2.5V and V DD     —     LOW =1.2V (i.e., a voltage difference of 1.3V).  
         [0023]    [0023]FIG. 4 is a schematic circuit diagram of a first embodiment of the voltage converter in accordance with the present invention.  
         [0024]    [0024]FIG. 5 is a simulated timing diagram for the voltage converter of FIG. 4 where V DD     —     HIGH =3.3V and V DD     —     LOW =1.2V (i.e., a voltage difference 2.1V).  
         [0025]    [0025]FIG. 6 is a schematic circuit diagram of a second embodiment of the voltage converter in accordance with the present invention.  
         [0026]    [0026]FIG. 7 is a simulated timing diagram for the voltage converter of FIG. 6 where V DD     —     HIGH =2.5V and V DD     —     LOW =1.2V (i.e., a voltage difference 1.3 V).  
         [0027]    [0027]FIG. 8 is a graph comparing the simulated timing diagrams of a prior art voltage converter and a voltage converter in accordance with the present invention where V DD     —     HIGH =3.3V and V DD     —     LOW =1.2V.  
         [0028]    [0028]FIG. 9 is a graph comparing the simulated timing diagrams of a prior art voltage converter and a voltage converter in accordance with the present invention where V DD     —     HIGH =2.5V and V DD     —     LOW =1.2V.  
         [0029]    [0029]FIG. 10 is a schematic circuit diagram of a third embodiment of the voltage converter in accordance with the present invention.  
         [0030]    [0030]FIG. 11 is a schematic circuit diagram of a fourth embodiment of the voltage converter in accordance with the present invention.  
         [0031]    [0031]FIG. 12 is a schematic circuit diagram of a fifth embodiment of the voltage converter in accordance with the invention in which the voltage translation circuit is implemented with a logic block.  
         [0032]    [0032]FIG. 13 is a schematic circuit diagram of the embodiment of FIG. 12 illustrating the logic block thereof in greater detail.  
         [0033]    [0033]FIG. 14 is a schematic circuit diagram of a voltage translator similar to that of FIG. 13 but providing an output signal having the same polarity as the input signal.  
         [0034]    [0034]FIG. 15 is a schematic circuit diagram of another voltage translator in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0035]    Turning now to FIG. 4, a first embodiment of the voltage translator or converter  2  in accordance with the invention is illustratively shown. The voltage translator  2  includes a high voltage input inverter illustratively including high threshold transistors PH 20  and NH 20 . The first conducting end of transistor PH 20  in the high voltage inverter is connected to the high voltage supply V DD     —     HIGH . The second conducting end of transistor PH 20  drives the first conducting end of the transistor NH 20 , which is also the output of the inverter. The second conducting end of the transistor NH 20  is grounded.  
         [0036]    The output of the high voltage inverter is connected to a series pass transistor NH 21 , the control terminal of which is raised to V DD     —     HIGH . The other conducting terminal of the series pass transistor NH 21  is connected to the shorted drain and gate of a second pass transistor NH 22 . The source of the transistor NH 22  is connected to the drains of a low threshold voltage transistor NL 20  and a high threshold voltage transistor NH 23 . The gate of the transistor NH 23  is controlled by the input signal, while its source is grounded.  
         [0037]    The gate of the transistor NL 20  is connected to the lower supply voltage V DD     —     LOW , while its source is connected to the input of a low voltage inverter including low threshold voltage transistors PL 20  and NL 21 . The source terminals of the transistors PL 20  and NL 21  are connected to V DD     —     LOW  and ground, respectively. The drains of the transistors PL 20  and NL 21  are connected together to form the output terminal OUT.  
         [0038]    The above-described configuration provides improved performance since the lower threshold transistors are connected to the lower supply voltages only, whereas the higher threshold transistors are supplied by the higher voltage only. Also, the higher voltages are brought down sufficiently before application to the lower threshold transistors, thus producing approximately equal rise and fall delays.  
         [0039]    When the input is HIGH, the inverter formed by the transistors PH 20  and NH 20  outputs a LOW signal that tristates the transistor NH 22 . When the input is HIGH, the transistor NH 23  turns ON and passes the LOW level to the drain of the transistor NL 20 , which passes it to the gates of the transistors PL 20  and NL 21 . This causes the transistor NL 21  to turn OFF while the transistor PL 10  is turned ON, thus pulling the OUT terminal to V DD     —     LOW . In this manner the HIGH input signal at V DD     —     HIGH  is converted to V DD     —     LOW .  
         [0040]    Similarly, when the input is LOW, the transistor NH 20  is turned OFF and the transistor PH 20  is turned ON. This passes V DD     —     HIGH  to the drain of NH 21 . The transistor NH 21  provides a threshold voltage drop (V thn ) and passes a voltage of V DD     —     HIGH −V thn  to the gate and drain of the transistor NH 22 . This transistor introduces a second threshold voltage drop, bringing the input signal down to V DD     —     HIGH −2V thn  at the drain of the transistor NL 20 . Since the input is LOW, the transistor NH 23  is OFF, allowing the transistor NL 20  to pass the voltage V DD     —     LOW −V tln  to the gates of the transistors PL 20  and NL 21 , where Vtln is the threshold voltage of low threshold NMOSs.  
         [0041]    Normally, the threshold voltage of PMOS transistors is greater than that of NMOS transistors. Therefore, the transistor PL 20  is OFF while the transistor NL 21  is ON, thus bringing the output terminal to a LOW logic level. In this manner, the gate-to-source voltage (V gs ) and the gate-to-drain voltage (V gd ) of the lower threshold transistor are kept smaller than V DD     —     LOW +Vtln (i.e., by introducing the transistors NH 21  and NH 22 ). These transistors drop the high voltage V DD     —     HIGH  by 2V thn  before appearing at the transistor NL 20  to ensure the safety of the low threshold transistors. Since PMOS transistors threshold voltages are usually greater than NMOS transistors threshold voltage, no crowbar current flows in the circuit.  
         [0042]    The simulated timing diagram for the voltage translator  2  for V DD     —     HIGH  of 3.3V and V DD     —     LOW  of 1.2V is illustratively shown in FIG. 5. Upon comparing the timing diagram of FIG. 5 with that of FIG. 2 it will be seen that the device of the present invention produces better results than the prior art.  
         [0043]    A second embodiment of a voltage translator  3  in accordance with the present invention for the case when V DD     —     HIGH  is 2.5V and V DD     —     LOW  is 1.2V is illustrated in FIG. 6. Here, pass transistors NH 22  and NH 23  are eliminated, as a single pass transistor NH 31  is sufficient to protect the lower threshold transistor NL 30 . The remaining operation of the circuit is similar to that discussed above for the first embodiment of the invention.  
         [0044]    Referring to FIG. 7, the simulated timing diagram for the voltage translator  2  for the V DD     —     HIGH  of 2.5V and V DD     —     LOW  of 1.2V is shown. Again, comparing the timing diagrams of FIG. 8 and FIG. 3 shows that the circuit arrangement of the present invention produces shorter rise and fall delays and rise and fall transition times than the conventional voltage translator of the prior art.  
         [0045]    Simulation results for the operation of voltage converts in accordance with the present invention and the prior art where V DD     —     HIGH  is 3.3V and 2.5V and V DD     —     LOW  is 1.2V are illustrated in FIGS. 8 and 9, respectively. Here, VOUT is from the output OUT shown in the illustrated first and second embodiments of the present invention for V DD     —     HIGH  of 3.3V and 2.5V, respectively, whereas V OUT     —     prior  is the output of the prior art voltage translator  1  of FIG. 1. The simulated results are for a worst-worst case, i.e., when temperature, supply voltage, and/or process parameters are at their worst or slowest. From the illustrated comparison it will be appreciated that the present invention returns better results than those of the prior art device.  
         [0046]    A third embodiment  4  of the invention is illustratively shown in FIG. 10. In this example, an intermediate voltage V DDINT  is introduced at the control terminal of a pass transistor NH 40 . For translating 3.3V to 1.2V, the intermediate voltage V DDINT  is selected as 1.8V, whereas for a 5V to 2.5V conversion V DDINT  may be 3.3V, for example. The use of V DDINT  again reduces the likelihood of a crowbar current in the circuit.  
         [0047]    Referring to FIG. 11, a fourth voltage translator embodiment  5  in accordance with the invention is illustratively shown. In this embodiment, feedback is taken from the output through PL 51  so that transistors PL 50 , PL 51  and PL 50  form a half latch. This half latch is used to restore the HIGH logic level and V DD     —     LOW  at the gates of the transistors PL 50  and NL 50 . This approach again reduces the possibility of a crowbar current in the circuit.  
         [0048]    Yet another implementation of a voltage translator in accordance with the invention is shown in FIG. 12. The signal IN at the terminal IN 51  has to swing from 0V to a high voltage level of VDD HIGH (e.g., 3.3V). The terminal IN 51  is directly connected to the gate NG 53  of NMOS transistor NL 55 . The source of NMOS transistor NL 55  is connected to ground GND, and the drain is connected to a terminal OUT 57 . The terminal OUT 57  is the low voltage output of the circuit for loads operating at the lower voltage VDD LOW (e.g., 1.2V) providing a voltage swing at the terminal OUT 57  from 0V to 1.2V.  
         [0049]    Since the NMOS transistor NL 55  has an input swing of 3.3V, it preferably uses 3.3V device NMOS transistors having a higher gate length and thicker gate oxide to be compatible with 3.3V operation. The transistor NL 55  provides desired performance for Vgs=3.3V. When the signal at the input terminal IN 51  is at logic 0, it provides a voltage of 0V which turns off the transistor NL 55 . When the signal at the terminal IN 51  is at logic 1, it provides a voltage of 3.3V at the gate NG 53  of the transistor NL 55 , which turns it on. When the transistor NL 55  is on, its Vgs=3.3V. This enables good sinking capability and provides a rapid falling edge of the signal at the terminal OUT 57 .  
         [0050]    A PMOS transistor PL 54  has its drain connected to the terminal OUT 57 , while its source is connected to power supply VDD LOW, which is 1.2V. Its gate is coupled to a node PG 52 , which is the output of the logic block  100 . Since the source voltage of the PMOS transistor PL 54  is only at 1.2V, the PMOS transistor PL 54  is preferably a 1.2V device to provide desired rise-time performance. That is, this device preferably has a shorter gate length and thinner gate oxide compared to that of 3.3V-rated transistors. Also, the voltage swing at the gate of the transistor PL 54  is preferably limited to 1.2V to prevent oxide break down.  
         [0051]    The logic circuit  100  connected between the terminal IN 51  and the node PG 52  accomplishes the foregoing by taking the input from the terminal IN 51  with a voltage swing of 0V to 3.3V and providing an output at the node PG 52  with a voltage swing of 0V to 1.2V. The output of the logic block  100  is non-inverting. A 0V input generates a 0V output, while a 3.3V at the terminal IN 51  generates a 1.2V output at the node PG 52 . The functioning of logic block  100  is such that it allows a 0V input to pass through itself, but when the signal at the terminal IN 51  rises above 0V the output at the node PG 52  follows the input signal until it reaches 1.2V, after which the voltage level saturates.  
         [0052]    The logic block  100  maintains the output at the node PG 52  at 1.2V until the signal at the terminal IN 51  starts decreasing from 3.3V and reaches 1.2V, after which the output at the node PG 52  again follows the terminal IN 51  down to 0V. In this manner the voltage swing of 0V to 3.3V at the terminal IN 51  is translated to 0V to 1.2V swing at the node PG 52  by the logic block  100 .  
         [0053]    One advantageous embodiment of the logic block  100  is illustratively shown in FIG. 13. The logic block  100  includes an inverter  200  having an NMOS transistor NH 202  and a PMOS transistor PH 201 . The gate of the NMOS transistor NH 202  is connected to the input terminal IN 51 . Further, its drain is connected to the node  204 , and its source is connected to ground. The gate of the PMOS transistor PH 201  is also connected to the input terminal IN 51 , while its drain is connected to the node  204  and its source is connected to the higher supply voltage VDD HIGH.  
         [0054]    Since the inverter  200  experiences an input swing from 0V to VDD HIGH and operates from the higher power supply VDD, higher voltage devices are preferably used for the NMOS transistor NH 202  and PMOS transistor PH 201 . The gate of the NMOS transistor NL 102  is connected to the node  204 , while its drain is connected to the node PG 52  and its source is connected to the input terminal IN 51 . Since the swing at the source and gate of the NMOS transistor NL 102  is from 0 to the higher voltage level VDD HIGH it is preferably a high voltage device. The gate of the PMOS transistor PL 103  is connected to the node  204 , while its drain is connected to the node PG 52  and its source is connected to the lower voltage level VDD LOW. Since the voltage swing at the gate of the transistor PL 103  is from 0 to the higher voltage level VDD HIGH, it is preferably a high voltage device.  
         [0055]    When the signal at the input terminal IN 51  is at 0V, the gate of NMOS transistor NL 55  is at 0V, causing it to turn off. This produces a VDD HIGH level at the node  204  of the inverter  200 . VDD HIGH at the node  204  turns NMOS transistor NL 102  on and turns off PMOS transistor PL 103 . Since the NMOS transistor NL 102  is on, it passes 0V from input terminal IN 51  to its output at the node PG 52 , causing the PMOS transistor PL 54  to turn on. This provides a signal of VDD LOW at the terminal OUT 57 .  
         [0056]    When the signal at the input terminal IN 51  starts increasing from 0V, the gate voltage of the NMOS transistor NL 55  follows the terminal IN 51 . The width of the transistors PH 201  and NH 202  are selected to adjust the trip point of the inverter  200  to a level equal to VDD LOW. Therefore, as the signal at the terminal IN 51  reaches VDD LOW, it trips the inverter  200 , causing 0V to appear at the node  204 . A value of 0V at the output node  204  turns off the NMOS transistor NL 102  and isolates the node PG 52  from the terminal IN 51 . This stops further propagation of the signal from the terminal IN 51  to the node PG 52 . Also, 0V at the node  204  turns on the PMOS transistor PL 103 , thus connecting the node PG 52  to the VDD LOW supply voltage.  
         [0057]    The presence of the VDD LOW voltage at the node PG 52  turns off the PMOS transistor PL 54 . When the voltage at the terminal IN 51  increases from 0V to a value equal to the threshold voltage of the NMOS transistor NL 55 , it turns on the transistor and applies 0V at the terminal OUT 57 . In this manner the input swing of 0V to VDD HIGH at the terminal IN 51  is converted to a voltage swing of 0V to VDD LOW at the terminal OUT 57 , but with a polarity opposite to the polarity of the input of the circuit. Since the load for the logic block  100  is limited to the small gate capacitance of the PMOS transistor PL 54 , the required size for the NMOS transistor NL 102  is small. Further, the slew rate at the node PG 52  is approximately the same as at terminal IN 51 .  
         [0058]    Referring now to FIG. 14, a voltage translator with an output signal having the same polarity as that of the input signal is illustratively shown. To achieve the same polarity an inverter  300  is connected at the output terminal OUT 57 . A PMOS transistor PL 301  of the inverter  300  has its gate connected to the output terminal OUT 57 , its drain connected to the terminal OUT 58 , and its source connected to the VDD LOW supply. Since the input swing for the PMOS transistor PL 301  is 0 to VDD HIGH, and its supply voltage is VDD LOW, it is preferably a VDD LOW device.  
         [0059]    The NMOS transistor NL 302  of the inverter  300  has its gate connected to the terminal OUT 57 , its drain is connected to the terminal OUT 58 , and its source is connected to ground. The input swing for the NMOS transistor NL 302  is from 0V to VDD LOW and the voltage which appears at its input is VDD LOW, thus it is preferably a VDD LOW device.  
         [0060]    The sizes of the PMOS transistor PL 301  and NMOS transistor NL 302  are adjusted according to the load at the terminal OUT 58 , to get the required slew rates at terminal OUT 58  and to get better delays. In this manner the desired driving capability is achieved by increasing the driving capability of the inverter  300 . In addition, by sizing the width of the NMOS transistor NL 302  and PMOS transistor PL 301 , the rise delays and fall delays can be made equal and the slew rates can be adjusted as required. Since its load is limited to that of the inverter  300 , the size of the PMOS transistor PL 54  can be as low as 1/2.5 times the size of the inverter  300 . This reduces the loading for the signal at the terminal IN 51  and for the NMOS transistor NL 102 , which thus reduces the propagation delay.  
         [0061]    An embodiment of a complete voltage translator with the output signal at the terminal OUT 57  having the same polarity as the input signal at the terminal IN 60  is illustratively shown in FIG. 15. In this circuit an inverter  400  is connected before the terminal IN 51 . A PMOS transistor PH 401  of the inverter  400  has its gate connected to the input terminal IN 60 , while its drain is connected to the terminal IN 51  and its source is connected to the VDD HIGH power supply. An NMOS transistor NH 402  has its gate connected to the input terminal IN 60 , while its drain is connected to the terminal IN 51  and its source is connected to ground. Since both the NMOS and PMOS transistors have an input signal swing of VDD HIGH at their gates and operate off a VDD HIGH power supply, both are preferably VDD HIGH devices.  
         [0062]    It will be apparent to those skilled in the art that the foregoing embodiments are merely illustrative of the present invention, and are not intended to be exhaustive or limiting. These embodiments have been presented by way of example only, and various modifications may be made within the scope of the above invention. For instance, the number of series-connected transistors may be varied. Similarly, the intermediate voltage levels may be different from those described above. Such changes and modifications are understood to be included within the scope of the present invention as set forth in the following claims.