Abstract:
A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.

Description:
This application is a continuation of application Ser. No. 08/012,800, filed Feb. 2, 1993 (abandoned) which is a continuation of Ser. No. 07/523,425, filed May 15, 1990 (abandoned). 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device. 
     FIG. 1 shows the construction of a prior art semiconductor memory device. In FIG. 1, bit line pairs b1, b1 to bn, bn are respectively connected to sense amplifiers SA1 to SAn. When one of a plurality of word lines, for example, a word line W1 is selected to assume a high level, data in memory cells MC&#39;s selected by the word line W1 are read onto the bit lines b1 to bn. Subsequently, a sense amplifier power supply control circuit PLC activates a power supply line VL and a ground line GL provided for the sense amplifiers SA1 to SAn so that the sense amplifiers SA1 to SAn initiate sensing operation. Data stored in the selected memory cells are amplified sufficiently by these sense amplifiers and then transferred to latch circuits LAT1 to LATn, and thereafter control lines SWC1 to SWCn for switch elements SW1, SW1 to SWn, SWn are sequentially selected by means of a column decoder CO to assume a high level so that the data may be transferred to a pair of data lines D and D. The storage data now transferred to the data line pair D and D are further amplified by main amplifiers and then transferred to an output circuit from which the data are read sequentially. The semiconductor memory device having the construction described above is disclosed in &#34;A 256K Dual Port Memory&#34; by S. Ishimoto et al, ISSCC Digest of Technical Papers, 1985, pp. 38-39. Operation timings in the semiconductor memory device shown in FIG. 1 are illustrated in FIG. 2. As shown in FIG. 1, data amplified by the sense amplifiers SA1 to SAn are latched by the latch circuits LA1 to LAn, thus allowing the sense amplifiers SA1 to SAn to end read operation of the data and to make ready for the next read operation, and therefore incessant data transfer can be insured. 
     However, the number of the sense amplifiers SA1 to SAn is so large that the value of n amounts approximately up to 1K to 4K and disadvantageously, when the data are transferred to the latch circuits LAT1 to LATn at a time, transient current occurring during the transfer becomes excessively large. To cope with this problem, another prior art semiconductor memory device as shown in FIG. 3 has been proposed wherein the data line pair D, D is divided into four data line pairs which connect to a parallel/serial converter circuit P/S. The sense amplifiers SA1 to SAn are sorted into four groups and data amplified in each group are transferred to data line pairs D1, D1 to D4, D4 and sent to the parallel/serial converter circuit. The semiconductor memory device having the above construction is disclosed in &#34;A 1 Mb DRAM with 33 MHz Serial I/O Ports&#34; by K. Ohta et al, ISSCC Digest of Technical Papers, 1986, pp. 274-275. After being subjected to parallel/serial conversion, the data are sent to the output circuit and delivered therefrom. FIG. 4 illustrates a construction of the parallel/serial converter circuit shown in FIG. 3. Referring to FIG. 4, data transferred to the data lines D1, D1 to D4, D4 are amplified in main amplifiers MA1 to MA4. Subsequently, a signal on a latch circuit control line LAC is rendered to be high level so that the data are latched by latch circuits LA1 to LAn and thereafter transferred sequentially to the output circuit through switch elements PSW1 to PSW4. Operation timings in this semiconductor memory device are illustrated in FIG. 5. As will be seen from FIG. 5, data are delivered incessantly and because of the number of circuits to be operated being small, transient current during the data transfer can be suppressed. However, an interval of time between the falling of a word line following read out of data associated with this word line and the rising of the succeeding word line is so small that as the data read speed increases, incessant delivery of data becomes difficult to achieve. 
     As described above, the prior art semiconductor memory devices have disadvantages that when stored data are sequentially and incessantly read out, transient current during operation is excessively large and besides the incessant delivery of data becomes difficult to achieve as the data read speed increases. With the existing construction, semiconductor memory devices of satisfactorily high performance can not be obtained. 
     SUMMARY OF THE INVENTION 
     The present invention has been implemented with the foregoing backgrounds and an object of this invention is to provide a semiconductor memory device capable of reading and writing data incessantly at high rates while suppressing transient currents during operation. 
     To accomplish the above object, according to one aspect of the present invention a semiconductor memory device comprises a memory array unit in which memory cells are arranged in matrix, and sense amplifiers arranged exteriorly of the memory array unit wherein in the memory array unit, a plurality of bit line pairs are disposed to be selected by column addresses and a plurality of word lines are disposed to be selected by row addresses, each of the plurality of word lines being divided into a plurality of divisional word lines, the plurality of bit line pairs are connected to the respective sense amplifiers, output signals of sense amplifiers corresponding to the column address selection are transferred to respective data lines, the divisional word lines are sequentially activated on time division basis in correspondence to the row address selection such that the activation of one of any two sequential divisional word lines overlaps with the activation of the other for a predetermined time. 
     According to an embodiment, another aspect of the present invention, the plurality of sense amplifiers are sorted into a plurality of groups, respective sense amplifiers in each group have a common column address and each sense amplifier transfers output signals to a respective different data line pair when the common column address is selected, and the plurality of data line pairs are connected to a serial/parallel converter circuit and/or a parallel/serial converter circuit. 
     With the above construction, the number of circuits to be operated at a time can be reduced and data can be inputted and outputted regardless of timings of the rise and fall of word line signals and consequently, the semiconductor memory device according to the present invention can perform incessant data input/output operations at high rates while suppressing transient currents during operation. Further, in accordance with the aforementioned construction, the number of circuits, which can be operated simultaneously, can be increased within a range of permissible transient current, thereby further increasing the data input/output speed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram schematically showing the construction of a prior art semiconductor memory device wherein latch circuits are connected between sense amplifiers and switch elements; 
     FIG. 2 is a timing chart showing the operation of the prior art FIG. 1 semiconductor memory device; 
     FIG. 3 is a circuit diagram schematically showing the construction of another prior art semiconductor memory device wherein a data line pair is divided into four pairs and a parallel/serial converter circuit is provided; 
     FIG. 4 is a circuit diagram showing an example of the construction of the prior art parallel/serial converter circuit; 
     FIG. 5 is a timing chart showing the operation of the prior art FIG. 3 semiconductor memory device; 
     FIG. 6 is a circuit diagram schematically showing the construction of a semiconductor memory device according to a first embodiment of the invention; 
     FIG. 7 is a timing chart showing the operation of the FIG. 6 semiconductor memory device; 
     FIG. 8 is a circuit diagram of a circuit for generating control signals BSL A  and BSL B  shown in FIGS. 6 and 7; 
     FIG. 9 is a timing chart showing the operation of the FIG. 8 circuit; 
     FIG. 10 is a circuit diagram schematically showing the construction of a semiconductor memory device according to a second embodiment of the invention wherein a data line pair in the FIG. 6 semiconductor memory device are divided into four pairs and a parallel/serial converter circuit is provided; and 
     FIG. 11 is a timing chart showing the operation of the FIG. 10 semiconductor memory device. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     (Embodiment 1) 
     An embodiment of a semiconductor memory device according to the invention will now be described with reference to FIGS. 6 and 7. FIG. 6 shows the construction of a semiconductor memory device according to a first embodiment of the invention. In FIG. 6, bit line pairs b1, b1 to bn, bn are respectively connected to sense amplifiers SA1 to SAn, and complementary outputs of the individual sense amplifiers SA1 to SAn are connected, through switch elements SW1 to SWn, to data lines D and D connected to main amplifiers. The switch elements SW1 to SWn are open/close controlled by signals delivered from column decoders CO A  and CO B  to switch element open/close control signal lines SWC1 to SWCn. The sense amplifiers SA1 to SAn are sorted into two groups, of which one includes sense amplifiers SA1 to SAn/2 and the other includes sense amplifiers SAn/2+1 to SAn, and similarly the bit lines, switch elements and switch open/close control signal lines are sorted into the above two groups. The former group is defined as A block and the latter group as B block. A sense amplifier power supply control circuit PLC, a row decoder ROW and a column decoder CO comprised in one group are independent of those comprised in the other group. In addition, word lines W are also sorted into the two groups so that each of the word lines is divided into two divisional word lines. With the above construction, time difference is set between activation of word lines in one group and that of word lines in the other group and the sense amplifier power supply control circuits PLC&#39;s are operated in compliance with the activation of the word lines of the respective groups, thus making it possible to produce data outputs incessantly. 
     More specifically, in accordance with the present embodiment, block selection signals BSL A  and BSL B  have a time difference therebetween and control the sense amplifier power supply control circuits PLC&#39;s and row decoders ROW&#39;s in the respective blocks. 
     An embodiment of a circuit adapted to generate the block selection signals BSL A  and BSL B  is illustrated in FIG. 8. Referring to FIG. 8, an input signal φB is supplied from an input terminal INP and fall of the input signal is detected by a fall edge detector circuit comprised of inverters INV1 to INV6 and a NAND circuit NAND1 to provide a set signal for an RS flip-flop circuit 1 comprised of NAND circuits NAND2 and NAND3, which flip-flop circuit 1 is set by the set signal to produce at output terminal OUTP1 the output signal BSL A  which is at high level. Similarly, the rise of the input signal φB is detected by a rise edge detector circuit comprised of inverters INV7 to INV11 and a NAND circuit NAND4 to provide a set signal for an RS flip-flop circuit 2 comprised of NAND circuits NAND5 and NAND6, which flip-flop circuit is set by the set signal to produce at output terminal OUTP2 the output signal BSL B  which is at high level. An output signal of the rise edge detector circuit is delayed by a predetermined time through a delay element DELAY2 and then applied as a reset signal to the RS flip-flop circuit 1 to make the output signal BSL A  low level. Similarly, an output signal of the fall edge detector circuit is delayed by a predetermined time through a delay element DELAY1 and then applied as a reset signal to the RS flip-flop circuit 2 to make the output signal BSL B  low level. The above-described relation between the input signal φB and each of the output signals BSL A  and BSL B  is depicted in FIG. 9. With the semiconductor memory device shown in FIG. 6, data are read sequentially in accordance with operation timings as shown in FIG. 7. The operation timings will now be described. Firstly, a word line WA1 in the block A controlled by the block selection signal BSL A  is raised to read data stored in memory cells MC&#39;s onto the bit line pairs b1, b1 to bn/2, bn/2. Subsequently, the sense amplifier power supply control circuit PLC A  is operated to maintain a sense amplifier power supply line VL A  at high level and a sense amplifier ground line GL A  at low level, activating the sense amplifiers to cause them to sense and amplify the data. The thus sensed and amplified data are sequentially transferred to the data lines D and D through the switch elements SW1 to SWn/2 and then sent to the main amplifiers. In accordance with the present embodiment, before all data associated with the word line WA1 have been read out, a word line WB1 in the block B controlled by the block selection signal BSL B  is raised to activate the sense amplifiers SAn/2+1 to SAn in anticipation of permitting data associated with the word line WB1 to be transferred any time to the data lines D and D. Thus, as soon as the data associated with the word line WA1 have all been read out, reading of the data associated with the word line WB1 is initiated. Thereafter, a word line WA2 is raised while the data associated with the word line WB1 are read out and in this manner the ensuing word lines are sequentially raised, thereby ensuing that the delivery of data can be achieved incessantly regardless of the rising and falling of word line and the time for sensing and amplifying data and besides the magnitude of transient current during operation can be suppressed. By using part of the row address as the block selection signals BSL A  and BSL B , these block selection signals need not be generated internally and internal control can be facilitated. The present embodiment has been described by way of data read operation, but by transferring input data to the data lines D and D, data can be written in a similar manner. 
     (EMBODIMENT 2) 
     The semiconductor memory device shown in FIG. 6 can afford to deliver data incessantly but the data lines D and D have a large capacity and this makes it difficult to transfer data at a sufficiently high rate. In a second embodiment of the semiconductor memory device according to the invention as shown in FIG. 10, the data line pair in the semiconductor memory device shown in FIG. 6 are divided into four data line pairs with the view of increasing the transfer rate and these four data line pairs are connected to a parallel/serial converter circuit. In the FIG. 10 semiconductor memory device, D1, D1 to D4, D4 designate data line pairs and MCA A  and MCA B  designate memory cell arrays which are constructed of the same sense amplifiers, word lines, memory cells, row decoders and sense amplifier power supply control circuits as those in FIG. 6 and operate as in the case of the semiconductor memory device shown in FIG. 6. In this embodiment, the circuit shown in FIG. 8 may also be used to generate the block selection signals BSL A  and BSL B . The parallel/serial converter circuit P/S operates in the same way as the one shown in FIG. 3 and may be realized with the same circuit as that shown in FIG. 4. To describe the operation of the parallel/serial converter circuit shown in FIG. 4, data sent from data lines D1, D1 to D4, D4 are amplified in main amplifiers MA1 to MA4 and then transferred to latch circuits LA1 to LA4. These latch circuits LA&#39;s are controlled by a signal on signal line LAC so that the latch circuits LA1 to LA4 latch the data at a time. Subsequently, transfer gates PSW1 to PSW4 are sequentially turned on, beginning with the transfer gate PSW1, to sequentially supply the data to an output circuit. The above operation is repeated to complete parallel/serial conversion. Operation timings covering the switch elements SW1 to SWn and the parallel/serial converter circuit are illustrated in FIG. 11. As is clear from FIG. 11, the data can be delivered out of the parallel/serial conversion circuit at a rate which is four times as large as the rate of occurrence of the control signals SWC1 to SWCn for the switch elements SW1 to SWn. In accordance with this embodiment, the speed-up feature is achieved by the provision of the parallel/serial converter circuit but the number of simultaneously operated circuits is sufficiently small to suppress transient current during operation. By taking the construction described previously, incessant delivery of data at a high rate can be ensured while suppressing the transient currents during operation and besides the speed-up can be promoted by subjecting data sent from an increased number of divided data lines to parallel/serial conversion. Thus, the number of divisions of the data line pairs may be determined so as to be optimized for the data delivery rate and the magnitude of transient current during operation. The second embodiment has also been described by way of reading of data but by adding a serial/parallel converter circuit for inverse operation to that of the parallel/serial converter circuit, a write operation can be performed incessantly at a high rate as in the case of the read operation. Preferably, in order to permit high-rate and incessant performance in both the read and write operations, both of the parallel/serial converter circuit and serial/parallel converter circuit may be employed. 
     As is clear from the foregoing description, the semiconductor memory device according to the present invention can afford to perform high-rate and incessant data input/output operation while suppressing the transient current during operation and therefore can be designed easily, with less labor and time, for a large capacity semiconductor memory device especially used for realization of image memories.