Abstract:
The method and apparatus provides a parity bit for every m multiples of b bits, a group of b bits being the smallest number of bits that can be manipulated by the CPU. The parity bit is computed for the entire m x b bits during a write operation, even if only a subset of the m multiples of b bits is being stored. The write operation is implemented as a read-modify-write operation of the entire m x b bits, with parity error reporting suppressed for the read portion of the operation. However, the parity bit is set factoring in whether a parity error is detected during the read portion of the operation. The parity bit for the entire m x b bits is checked during a read operation, even if only a subset of the m multiples of b bits is needed. Any detected parity error is reported to the CPU. As a result, hardware cost is substantially reduced with minimal degradation to data integrity. Furthermore, the method and apparatus is completely transparent to the CPU and the operating system.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to the field of computer systems. More particularly, the present invention is a method and apparatus for providing non-atomic level parity protection for storing data in a random access memory. 
     2. Art Background 
     Traditionally, the smallest amount of data stored in the random access memory (RAM) 16 that can be manipulated directly by the central processing unit (CPU) (not shown) of a computer system 10, is a byte, i.e. eight bits, 22a, 22b, 22c or 22d (FIG. 1a), even though there are machine instructions available for a programmer to read or write in bytes, half-words, i.e. two bytes, full-words, i.e. four bytes, or double-words, i.e. eight bytes. That is why, typically parity protection provided for storing data in the RAM 16 is provided at this atomic level, i.e. the byte level. An additional ninth bit, 24a, 24b, 24c, or 24d is provided for every byte 22a, 22b, 22c, or 22d, to be used as the parity bit. Thus, for a &#34;thirty-two bit computer system&#34;, the data path 18 between the RAM 16 and the RAM controller 14 is typical thirty-six bits, even though the four parity bits 24a, 24b, 24c, or 24d are not accessible to the user. 
     The parity bit of each byte is set or reset by the random access memory controller during each write operation. Typically the RAM controller receives the data from the CPU, block 32 (FIG. 1b). The RAM controller determines which byte or bytes need to be written, block 34. The RAM controller then generates the corresponding parity bits for the bytes to be written, block 36. Each parity bit is set or reset so that the total number of 1 bits for each byte is always odd or even, depending on whether odd parity or even parity is used by the computer system. After generating the parity bits, the RAM controller writes the appropriate byte or bytes into the RAM along with their parity bits, block 38. 
     The parity bit in turn is checked by the RAM controller during each read operation. Typically, the RAM controller retrieves the whole word from the RAM, block 42 (FIG. 1c). The RAM controller determines which byte or bytes are being fetched 44 and returns only what is needed to the CPU 46. At the same time, the RAM controller checks the parity bit of each byte being returned for error 48, and reports the parity error to the CPU 49 if detected. 
     The traditional way of providing parity protection is costly, particularly in terms of hardware space for microcomputers. One ninth of the random access memory is used for parity protection. As will be discussed, the present invention overcomes the disadvantage of the prior art and provides a method and apparatus for providing non-atomic level parity protection for storing data in random access memory. 
     SUMMARY OF THE INVENTION 
     A method and apparatus for providing non-atomic level parity protection for storing data in a random access memory is disclosed. The method and apparatus substantially reduces hardware cost with minimal degradation to data integrity. Furthermore, the method and apparatus is completely transparent to the CPU and the operating system. 
     The preferred embodiment of the method and apparatus of the present invention provides a parity bit for every m multiples of b bits, a group of b bit being the smallest number of bits that can be manipulated by the CPU. The parity bit is computed for the entire m x b bits during a write operation, even if only a subset of the m multiples of b bits is being stored. The write operation is implemented as a read-modify-write operation of the entire m x b bits, with parity error reporting suppressed for the read portion of the read-modify-write operation. However, the parity bit is set factoring in whether a parity error is detected during the read portion of the read-modify-write operation. The parity bit for the entire m x b bits is checked during a read operation, even if only a subset of the m multiples of b bits is needed. Any detected parity error is reported to the CPU. 
     For example, for a 32-bit computer system, the method and apparatus of the present invention provides a parity bit for every full word. The parity bit is computed for the entire full word during a write operation, even if only a byte or half-word is being stored. The write operation is implemented as a read-modify-write operation for the entire full word as outlined above. Similarly, the parity bit for the entire full word is checked during a read operation, even if only a byte or half-word is needed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiment of the invention with references to the drawings in which: 
     FIGS. 1a-1c show block diagrams illustrating atomic level parity protection for storing data in a random access memory of the prior art. 
     FIG. 2 shows a block diagram illustrating a physical view of the hardware elements of the preferred embodiment of the apparatus of the present invention. 
     FIG. 3 shows a block diagram illustrating a logical view of the write algorithm used by the method of the present invention. 
     FIG. 4 shows a block diagram illustrating a logical view of the read algorithm used by the method of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A method and apparatus for providing non-atomic level parity protection for storing data in a random access memory (RAM) is disclosed. In the following description for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well known systems are shown in diagrammatical or block diagram form in order not to obscure the present invention unnecessarily. 
     Referring now to FIG. 2, a block diagram illustrating a physical view of the hardware elements of the preferred embodiment of the apparatus of the present invention is shown. The preferred embodiment of the apparatus of the present invention 70 is shown in the context of a RAM controller 54 coupled to a central processing unit (CPU) (not shown), and a plurality of RAM arrays 56, of an exemplary 32-bit computer system 50. The data paths 58 and 60 between the RAM controller 54 and the CPU, and between the RAM controller 54 and the RAM arrays 56, are thirty-two bits and thirty-three bits wide respectively. The CPU writes and reads in one byte, half-word, full word or double word. Data writing and data reading are performed asynchronously. 
     Additionally, the RAM arrays 56 comprises a plurality of memory data locations (four shown, 62a-62d) referenced by a plurality of memory addresses for storing a plurality of data bytes, and a plurality of corresponding memory parity locations (one shown, 64) for storing a plurality of parity bits. For this exemplary 32-bit computer system, one parity bit is provided for every four data bytes stored. The memory data locations and the corresponding memory parity locations are initialized by the RAM controller 54 to a plurality of initial data bytes and a plurality of corresponding initial parity bits respectively, at the beginning of operation. 
     Continuing reference to FIG. 2, the preferred embodiment of the apparatus of the present invention 70 comprises a plurality of interfaces, 72 and 74, a plurality of registers, 76, 78 and 80, and a plurality of logic circuitry 82, 84, 86 and 88. The plurality of interfaces comprise a central processing unit (CPU) interface 72 coupled with the CPU, and a RAM interface 74 coupled with the RAM arrays 56. The plurality of registers comprises a data register A 76 coupled to the CPU interface 72, a data register B 78 coupled to the RAM interface 74, and an address register 80 coupled to the CPU interface 72 and the RAM interface 74. The plurality of logic circuitry comprise a data modifying circuitry 82 coupled to the data registers A and B, 76 and 78, and the address register 80, a data extracting circuitry 84 coupled to the data registers A and B, 76 and 78, and the address register 80, a parity error checking circuitry coupled to the data register B 78, and the CPU, and a parity bit generating circuitry 88 coupled to the data register B 78 and the parity error checking circuitry 86. 
     The CPU interface 72 is for interfacing with the CPU to write data into the RAM arrays 56 and to read data from the RAM arrays 56. During a write operation, the CPU interface 72 receives a write signal, a plurality of target memory addresses and a plurality of data bytes to be written from the CPU as inputs. The target memory addresses received indicates a plurality of target memory data locations where the plurality of data bytes are to be written. In response, the CPU interface 72 outputs the target memory addresses and the data bytes received into the data register A 76 and the address register 80 respectively. 
     During a read operation, the CPU interface 72 receives a read signal, and a plurality of source memory addresses from the CPU as inputs. The source memory addresses indicates a plurality of source memory data locations where a plurality of data bytes are to be read. In response, the CPU interface 72 outputs the source memory addresses received into the address register 80. The CPU interface 72 also subsequently detects the presence of the plurality of retrieved data bytes in the data register A 76, during the read operation. In response, the CPU interface 72 outputs the plurality of retrieved data bytes for the CPU. 
     The RAM interface 74 interfaces with the RAM arrays 58 to write data into the RAM arrays 58 and to read data from the RAM arrays 58. During a writing operation, the RAM interface 74 detects the presence of the plurality of target memory addresses in the address register. In response, if the target memory addresses indicate less than a full word is being written, the RAM interface 74 retrieves a full word and its parity bit from the RAM arrays 58 and outputs the retrieved full word and its parity bit into the data register B 78; otherwise, the RAM interface 74 takes no action. If retrieved, the full word and its parity bit are retrieved from the four memory data locations that comprise the memory data locations being referenced by the target memory addresses and the corresponding memory parity location. 
     During the write operation, the RAM interface 74 also subsequently detects the presence of a full word and its parity bit to be written into the RAM arrays 56 in data register B 78. The full word to be written comprises the plurality of data bytes to be written. In response, the RAM interface 74 writes the full word and its parity bit into four memory data locations that comprise the memory data locations being referenced by the target memory addresses and the corresponding memory parity location. 
     During the read operation, the RAM interface 74 detects the presence of the plurality of source memory addresses in the address register 80. In response, the RAM interface 74 retrieves a full word and its parity bit from the RAM arrays 58 and outputs the retrieved full word and the retrieved parity bit into the data register B 78 respectively. The full word and its parity bit are retrieved from the four memory data locations that comprise the memory data locations being referenced by the source memory addresses and the corresponding memory parity location. 
     The data modifying circuitry 82 processes the data bytes to be written into the RAM arrays 58 and prepares them for writing into the RAM arrays 58. During the write operations, the data modifying circuitry 82 detects the data bytes to be written in the data register A 76 and outputs the data bytes to be written into the appropriate byte positions of data register B 78. If less than a full word is being written, the data bytes being written are effectively merged into the full word stored in the data register B 78. 
     The data extracting circuitry 84 processes data bytes being read for return to the CPU and prepares them for return to the CPU. During the read operations, the data extracting circuitry 84 detects the data bytes to be read and return to the CPU in the data register A 76, extracts the data bytes to be read from the data register B 78, and outputs them into data register A 76. 
     The parity error checking circuitry 86 checks for parity error and reports them during the data writing and the data reading operations. During the write operations, the parity error checking circuitry 86 detects the presence of the retrieved full word and the retrieved parity bit in the data register B 78 and conditionally outputs a signal for input to the parity bit generating circuitry 88 if a parity error is detected. The parity error checking is performed immediately after the retrieved full word and its parity bit are stored into the data register B 78 and before the data bytes being written are stored into the data register B 78. 
     During the read operation, the parity error checking circuitry 86 detects the presence of the retrieved full word in the data register B 78 and the retrieved parity bit in the data register B 78. In response, the parity error checking circuitry 86 conditionally outputs a signal for the CPU if a parity error is detected. The parity error checking is performed substantially simultaneous with the extraction and returning of the data bytes to be read to the CPU. 
     The parity bit generating circuitry 88 generates the parity bit associated with the full word to be written into the RAM arrays 56. During a write operation, the parity bit generating circuitry 88 detects the presence of the full word to be written in the data register B 78 generates the parity bit and outputs the generated parity bit into the data register B 78. The parity bit is generated in a standard manner using well known parity generating techniques. However, if a parity error is detected for the retrieved full word and its parity bit, the generated parity bit is inverted before being stored into the data register B 78. The parity bit is generated immediately after the data bytes to be written are stored into the data register B 78 and before the full word to be written are written into the RAM arrays 56. 
     Referring now to FIG. 3, a block diagram illustrating a logical view of the write algorithm used by the method of the present invention is shown. Initially, data to be written and target memory addresses for their storing memory data locations are received from the CPU, block 92. The data to be written are checked to determine if less than m multiples of b bits are being written, block 94. Data are being manipulated by the CPU in multiples of b bits, where a group of b bits is the smallest number of data bits that can be manipulated by the CPU. M is a pre-determined constant. 
     If the data to be written is not less than m multiples of b bits, branch 94a, a parity bit for the m multiples of b bits to be written is generated block 96. The parity bit is generated in a standard manner as previously described. Then, at block 98, the m multiple of b bits to be written and the corresponding parity bit are respectively stored into the memory data locations referenced by the target memory addresses received and the memory parity location corresponding to the referenced memory data locations. 
     If the data to be written is less than m multiples of b bits, branch 94b, m multiples of b bits and the corresponding parity bit are retrieved from the RAM arrays, block 100. The m multiple of b bits and their parity bit are retrieved from m memory data locations referenced by m memory addresses and the corresponding memory parity location. The m memory addresses comprise the target memory addresses received, and the m memory data locations comprises the memory data locations referenced by the target memory addresses received. The retrieved m multiple of b bits and their parity bit is checked for parity error, block 102. 
     If a parity error is not detected, branch 102a, the multiples of b bits to be written are merged into the retrieved m multiple of b bits, block 104a, as previously described, and a parity bit is generated for the merged m multiples of b bits, block 106. The parity bit is generated in a standard manner as previously described. The merged m multiple of b bits and their parity bit are subsequently stored into the memory data locations and the corresponding memory parity location respectively, where the pre-merged m multiple of b bits and their parity bit were previously retrieved, block 98. 
     If a parity error is detected, branch 102b, the multiples of b bits to be written are merged into the retrieved m multiple of b bits, block 104b, as previously described, and a parity bit is generated for the merged m multiples of b bits, block 108. The parity bit is generated in a standard manner and then inverted as previously described. Once the parity bit is generated, at block 98, the merged m multiple of b bits and the corresponding parity bit are stored into the memory data locations and the corresponding memory parity location respectively, where the pre-merged m multiple of b bits and their parity bit were previously retrieved. 
     Referring now to FIG. 4, a block diagram illustrating a logical view of the read algorithm used by the method of the present invention is shown. Initially, m multiples of b bits and their parity bit are retrieved from the RAM arrays after receiving a plurality of source memory addresses from the CPU, block 112. The m multiples of b bits and the corresponding parity bit are retrieved from m memory data locations referenced by m memory addresses and the corresponding memory parity location. The m memory addresses comprise the source memory addresses received, and the m memory data locations comprise the memory data locations referenced by the source memory addresses received. As described earlier, data are being manipulated by the CPU in multiples of b bits, where a group of b bits is the smallest amount of data bits that can be manipulated by the CPU and m is a pre-determined constant. 
     At block 116, the multiples of b bits to be read are extracted from the m multiples of b bits retrieved, block 114, and returned to the CPU. The retrieved m multiples of b bits and the corresponding parity bit are checked for parity error, block 118. If detected, the parity error is reported to the CPU, block 119. As described earlier, the parity error is checked substantially simultaneous with the extraction and returning of the multiples of b bits to be read. 
     It will be appreciated that the method and apparatus of the present invention is completely transparent to the CPU and the operating system. Furthermore, the degradation in data integrity is minimal. If the data value is never read back, the user never suffers from the effect of the parity error. If the parity error is a &#34;soft&#34; error, e.g. an alpha hit, the data value will be read back correctly in subsequent reads. If the parity error is a &#34;hard&#34; error, the parity error will be detected again in subsequent read just like the atomic level protection. The only error case that is less likely to be detected with the present invention is if multiple bits in multiple atomic bit groups are in error, e.g. two different bits from two different bytes. 
     While the apparatus of the present invention has been described in the context of an exemplary thirty-two bit computer system, those skilled in the art will recognize that the invention is not limited to the exemplary 32-bit computer system referenced, particularly in view if the description of the method of the present invention. The method and apparatus of the present invention can be practiced with modification and alteration within the spirit and scope of the appended claims.