Abstract:
A vertical four-quadrant triac wherein the gate region, arranged on the side of a front surface, includes a U-shaped region of a first conductivity type, the base of the U lying against one side of the structure, the main front surface region of the second conductivity type extending in front of the gate region and being surrounded with portions of the main front surface region of the first conductivity type.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority benefit of French patent application number 10/60326, filed on Dec. 9, 2010, entitled FOUR-QUADRANT TRIAC, which is hereby incorporated by reference to the maximum extent allowable by law. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a triac, and more specifically to a triac having similar sensitivities in the four triggering quadrants. 
         [0004]    2. Discussion of Related Art 
         [0005]    Vertical triacs, that is, triacs comprising, on a so-called rear surface, a first main electrode (A 2 ) and, on the opposite or front surface, a second main electrode (A 1 ) and a gate electrode (G), are considered herein. Generally, a triac comprises, side-by-side, PNPN and NPNP structures forming two head-to-tail thyristors. A portion of the front surface is dedicated to the trigger or gate structure and enables, when a voltage is applied between the gate electrode and the main front surface electrode, to trigger the thyristor, which is properly biased for the applied voltage. 
         [0006]    Currently, triacs are formed within a substantially square contour, the PNPN and NPNP thyristors substantially taking up half of the useful surface area, and a small portion of this surface area being dedicated to the triggering structure, which is generally arranged in a corner of the square. 
         [0007]    Four triggering quadrants are generally distinguished according to the voltages present on the main electrodes and on the gate electrode. Calling A 2  the main rear surface electrode and A 1  the main front surface electrode, and considering that main electrode A 1  which is used as a reference for the gate is at a zero voltage, the four quadrants, Q 1 , Q 2 , Q 3 , Q 4  are defined as follows 
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         [0008]      FIGS. 1A ,  1 B, and  1 C respectively show a top view, a cross-section view along line B-B, and a cross-section view along line C-C of  FIG. 1A  of a conventional corner gate triac. Reference will be made hereafter to all these drawings. 
         [0009]    The structure is built from a lightly-doped N-type semiconductor substrate  1 . It comprises a P-type well  3  on the front surface side and a P-type layer  5  on the rear surface side. A first NPNPP +  thyristor between main electrode A 1  and main electrode A 2  comprises a heavily-doped N-type region  7  formed in P well  3  and regions  3 ,  1 , and  5 , as well as a more-heavily doped P-type region  9  on the rear surface side. The second P + PNPN thyristor between main electrode A 1  and main electrode A 2  comprises a P +  region  11  formed in the upper portion of P well  3  in contact with electrode A 1  and, on the rear surface side, a heavily-doped N-type region  13  in contact with electrode A 2 . These two thyristors generally have substantially equal surface areas. 
         [0010]    The triggering structure is formed in P well  3 . It comprises a heavily-doped N-type region  15  generally having a specific shape of the type shown in  FIG. 1A , surrounded with a heavily-doped P-type region  17 . The gate metallization is in contact with these two regions  15  and  17 . It should be noted, by observing  FIGS. 1A and 1B , that a P-type well region  18 , which is not overdoped, exists between gate regions  15 ,  17  and main regions  7 ,  11  of the front surface electrode. In  FIG. 1A , the contour of main electrode A 1  is indicated by dotted lines and the contour of gate electrode G is also indicated by dotted lines. A heavily-doped N-type region  19  is formed under the gate area, on the rear surface side. 
         [0011]    An N + -type channel stop layer  20  has been formed at the periphery of the front surface of the triac. Different types of peripheries may be used, especially according to whether the triac is of planar or mesa type. These peripheries will not be detailed herein since they are well known by those skilled in the. 
         [0012]    As known, in order for the triggering to occur favorably, many conditions should be complied with, and many gate topologies, as well as many shapes of N region  19  placed on the rear surface in front of the gate, have been devised. Similarly, it should be noted that, generally, the doping of well  3  (and thus of layer  5 ) is selected according to compromises between the sensitivity and the immunity to parasitic triggerings of the triac. P +  layers  11 ,  17 , and  9 , which are necessary to provide an ohmic contact with the electrodes, will have optimized shapes to improve the triac sensitivity. 
         [0013]    Still, those skilled in the art have to make a compromise. If the auxiliary thyristor is made too sensitive, the triac has strong dV/dt triggering risks, that is, it risks triggering when the voltage between its main terminals varies abruptly while no gate voltage is applied. 
         [0014]    As an inevitable result, in all corner-gate structures of the type shown in  FIG. 1 , current I GT  which should flow between the gate and main electrode A 1  to trigger the thyristor is much greater in quadrant Q 4  than in the other quadrants and the dV/dt parasitic triggering characteristic for all operating modes of the triac is not optimal. 
         [0015]    Many other alternative embodiments of triacs are known by those skilled in the art. In particular, generally, so-called emitter short-circuit holes are provided in main N +  front surface and N +  rear surface regions  7  and  13 . This means that each of the N +  layers is locally interrupted so that the P region in which it is formed makes flush at the level of these interrupts. 
         [0016]    The triggering mode of this structure in mode Q 4  (A 2 &lt;0, G&gt;0) is the following. When a positive voltage is applied to the gate with respect to main electrode A 1 , a current flows from gate metallization G into P region  17  and travels to P +  region  11 . The flowing of this current, especially through region  18  along N +  region  7 , creates a voltage drop greater than 0.6 V and makes the junction between P well  3  and N +  region  7  conductive. This results in a carrier generation under the gate region and this strong injection carrier generation modifies the naturally blocking behavior of the junction between P well  3  and substrate  1 . The auxiliary thyristor comprising regions  17 - 3 - 1 - 5 - 19  turns on and its turning-on causes the turning-on of main thyristor  11 - 3 - 1 - 5 - 13 . 
         [0017]      FIG. 1A  shows the area in which the triggering starts in quadrant Q 4  (reference Q 4 ). The starting area in quadrants Q 1  and Q 2  (reference Q 1 ,Q 2 ) and the starting area in quadrant Q 3  (reference Q 3 ) have been similarly shown. It should be noted that the triggering areas are clearly separate, which enables to better understand the difficulty of balancing the triggering sensitivities in the various quadrants. 
       SUMMARY OF THE INVENTION 
       [0018]    An object of embodiments is to overcome the disadvantages of known triac structures, and especially to improve the triggering symmetry of a triac in the four quadrants while providing a triac with a strong immunity to parasitic dV/dt triggerings. 
         [0019]    In one embodiment, it is suggested to modify the position of the gate area and, instead of arranging this gate area in the corner as usually done in current triacs, or centrally as in triacs manufactured many years ago, to arrange it substantially in the middle of one side of the structure. 
         [0020]    More specifically, an embodiment provides a vertical four-quadrant triac wherein the gate region, arranged on the side of a front surface, comprises a U-shaped region of a first conductivity type, the base of the U lying against one side of the structure, the main front surface region of the second conductivity type extending in front of the gate region and being surrounded with portions of the main front surface region of the first conductivity type. 
         [0021]    According to an embodiment, the two main front surface regions of the first conductivity type join in an area of the first conductivity type separating the gate region of the second conductivity type from the main region of the second conductivity type. 
         [0022]    According to an embodiment, the main rear surface region of the first conductivity type extends under the main front surface region of the second conductivity type and under a portion of the gate region of the second conductivity type. 
         [0023]    According to an embodiment, a lightly-doped region of the second conductivity type is maintained in the vicinity of said area of the first conductivity type, on the gate side. 
         [0024]    According to an embodiment, the first conductivity type is type N and the second conductivity type is type P. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]    The foregoing and other objects, features, and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
           [0026]      FIGS. 1A ,  1 B,  1 C respectively are a top view and cross-section views of a conventional triac; 
           [0027]      FIG. 2A  is a top view of a triac according to an embodiment of the present invention and  FIGS. 2B and 2C  are cross-section views of the triac of  FIG. 2A ; and 
           [0028]      FIGS. 3A ,  3 B,  3 C,  4 A,  4 B,  4 C,  5 A,  5 B,  5 C, and  6 A,  6 B,  6 C respectively correspond to  FIGS. 2A ,  2 B,  2 C and illustrate the triggering paths of the triac of  FIG. 2  in each of the four quadrants. 
       
    
    
       [0029]    For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of integrated circuits, the various drawings are not to scale. 
       DETAILED DESCRIPTION 
       [0030]      FIGS. 2A ,  2 B,  2 C respectively show a top view, a cross-section view along direction BB, and a cross-section view along direction CC of  FIG. 2A  of a triac. 
         [0031]    This triac comprises the same periphery as the previously shown conventional triac but, as already noted, many variations may be adapted and many types of peripheries may be used, especially according to whether a triac of planar type or of mesa type is desired to be formed. 
         [0032]    This triac comprises the same layers and regions as the previously-described triac but they are distributed and arranged differently to optimize the flowing of the triggering currents. It especially comprises lightly-doped N-type substrate  1 , P-type well  3  formed on the front surface side, and P-type layer  5  formed on the rear surface side, as well as overdoped portion  9  of layer  5 . In well  5 , the main N +  front surface region is arranged symmetrically, is substantially H-shaped and comprises two main elements  21  and  22  corresponding to the two arms of the H and a central bar  23 . Main P +  front surface region  25  is arranged between the arms of the H (at the top of the drawing) and takes up a surface area substantially equal to that of N +  regions  21 ,  22 ,  23  altogether. A first main electrode A 1  covers all of regions  21 ,  22 ,  23 , and  25 . The gate region is arranged between the two arms of the H (at the bottom of the drawing) and comprises a heavily-doped N-type (N + ) U-shaped region  27  and, inside of the U, also in contact with the gate electrode, a heavily-doped P-type region  29 . As illustrated in  FIGS. 2A and 2B , there preferably remains a non-overdoped region  28  of P-type well  3 , between gate regions  27 ,  29  and bar  23 , of the main front surface region. 
         [0033]    Contour  30  of main rear surface N +  region has been shown with dotted lines in the top view. This region extends in front of P +  region  25  and at least a portion of gate area  27 ,  29 . 
         [0034]    The triggering paths in the four quadrants of the above triac will now be described.  FIGS. 3 to 6  reproduce  FIG. 2  and indicate with arrows the current flow during the various triggering phases. 
         [0035]      FIGS. 3A ,  3 B,  3 C relate to quadrant Q 1 , (main electrode A 2  is at a positive voltage and gate electrode G is at a positive voltage, main electrode A 1  being at a zero voltage). In this case, when a control voltage is applied between G and A 1 , a current tends to flow from P +  gate region  29  to P +  main region  25 . This current flows in the direction indicated by arrows F 1  all around N +  regions  21  and  22  and in the direction indicated by arrow F 2  under N +  arm  23 . Current F 2  in  FIG. 3B  has also been indicated. This causes the conduction of the PN junction between the P well and N +  regions  21 ,  22 ,  23 . Then, a current tends to flow in the direction indicated by arrows F 3  visible in  FIGS. 3B and 3C . The starting of the conduction of the junction between P well  3  and regions  21 ,  22 ,  23  causes the generation of carriers in well  3 , thus lowering the naturally blocking barrier of the junction between this well and substrate  1 . As a result, the thyristor formed between electrodes A 2  and A 1  by regions  9 - 5 - 1 - 3 -( 21 , 22 ) triggers, as indicated by double arrows F 4 . 
         [0036]      FIGS. 4A ,  4 B, and  4 C illustrate the triggering in quadrant Q 2 , that is, when A 2  is positive and G is negative with respect to A 1 . At the beginning of the triggering, current flows F 1 , F 2  are present, but in reverse direction with respect to  FIGS. 3A ,  3 B,  3 C. This starts the conduction of the PN junction between P well  3  and N +  gate region  27 . Thus, a current tends to flow in the direction indicated by arrows F 13 . The starting of the conduction of the junction between P well  3  and N +  gate region  27  causes the generation of carriers in well  3 , thus lowering the naturally blocking barrier of the junction between this well and substrate  1 . This results in the triggering of gate thyristor  9 - 5 - 1 - 3 - 27  (arrows F 14 ), and then of main thyristor  9 - 5 - 1 - 3 -( 21 , 22 ) (arrows F 4 ). 
         [0037]      FIGS. 5A ,  5 B, and  5 C illustrate a triggering in quadrant Q 3 , and  FIGS. 6A ,  6 B, and  6 C illustrate a triggering in quadrant Q 4 . In quadrants Q 3  and Q 4 , main P + PNPN thyristor  25 - 3 - 1 - 5 - 30  is likely to turn on. The same turn-on current flows as in the triggerings in the first and second quadrants can be found. The events occur in order F 1 -F 2 , F 3 , F 15  for quadrant Q 3  and F 1 -F 2 , F 3 , F 17 , F 15  for quadrant Q 4 . 
         [0038]    The turn-on regions in each of quadrants Q 1  to Q 4  have been indicated in each of  FIGS. 3A to 6A . 
         [0039]    Thus, this provides a significant advantage of the device according to the present invention, which is that the current paths leading to the triggering of the triac are very similar, with a possible inversion of the current direction in the four quadrants. Further, the turn-on areas are the same in quadrants Q 1  and Q 2 , on the one hand, and in quadrants Q 3  and Q 4 , on the other hand, and the turn-on areas in the four quadrants are close to one another. As a result, and as proved by experimentations, the sensitivity is the same in all four quadrants. No specific measures need to be taken to favor one quadrant over the others. 
         [0040]    Experimentations have shown that, when the auxiliary gate thyristor triggers first, this triggering is very rapidly followed by the triggering of the main thyristor and occurs close to the end of the branches of the U. The provision of a significant penetration of the rear surface N +  region under the gate is thus not necessary, which increases the immunity of the triac to dV/dt parasitic triggerings. Thus, comparative studies between the triac of  FIGS. 2A-2C  and a prior art triac such as shown in  FIGS. 1A-1C  show that the triac described herein turns on in all four quadrants with the same gate current as the current useful to the triggering in quadrants Q 1 , Q 2 , Q 3  of the conventional triac. Further, an almost ten times greater immunity to dV/dt parasitic triggerings has been observed. 
         [0041]    Of course, the drawings are all relatively simplified, and while the various regions have been shown with square corners, in practice, conventionally, these corners will be rounded to avoid various parasitic phenomena. 
         [0042]    An overdoped P-type region, noted P +  (regions  9 ,  25 ,  29 ) has been shown each time a contact had to be formed between a P-type layer or well and an electrode. It should be noted that in certain embodiments, such overdoped regions may be omitted, if the doping of the well or layer is sufficient and/or the metal-silicon contacts are improved. Further, all conductivity types may be inverted. 
         [0043]    Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.