Abstract:
The invention relates to remotely powered circuitry, and in particular to telephones. The circuit of the invention uses a counter to measure or compare the duration of power supply interruptions on the remote power supplying line to cause the remotely powered circuitry to be initialized whenever the duration of such an interruption becomes greater than or less than a specified duration. Advantageously, comparators are used so as to be able to take a plurality of durations into consideration. Thus, each time the power supply on the remote power line is interrupted, if the interruption is not of an acceptable duration, then the remotely powered circuitry is initialized.

Description:
This is a continuation of application Ser. No. 07/720,026, filed Jun. 24, 1991, now abandoned. 
    
    
     FIELD OF THE INVENTION 
     The invention relates to a circuit for conditional initialization of a remotely powered circuit. In particular, it enables the circuitry of a telephone set or of an alarm system for monitoring private houses to be initialized conditionally. 
     BACKGROUND OF THE INVENTION 
     Remotely powered circuits do not have a local power supply: i.e. battery, or power supply unit. The energy they require is conveyed to them over the transmission lines to which they are connected. 
     For a telephone, the energy is conveyed by the telephone line. Depending on the type of telephone, i.e. whether it uses tone dialing or pulse dialing, energy is not always present on the line. With tone telephones, dialing is done by frequency modulation, i.e. by modulating the current on the telephone line. Energy is always present on the line. 
     For telephones using pulse dialing, each digit (0 to 9) is represented by a corresponding number of pulses, each having a certain duration or a certain characteristic on the telephone line. 
     A pulse is obtained by short-circuiting the telephone line, which has the effect of making energy unavailable during each pulse. These power supply interruptions are of fixed duration since they satisfy the characteristics required for dial pulses. 
     The invention is particularly applicable to pulse dialing. The circuitry of the telephone must be capable of accepting power supply interruptions of fixed duration corresponding to dialing. However it should not tolerate power supply interruptions that do not correspond to dial pulse characteristics: e.g., faulty operation, line breaks, etc. Under such circumstances it must be reinitialized. That is why the term &#34;conditional initialization&#34; is used: initialization is conditional on an interruption of power supply lying outside an acceptable range. 
     The circuitry of such a digital telephone set essentially comprises two electronic portions: a bipolar logic portion for controlling the interface between the telephone set and the telephone line; and a microprocessor for controlling the telephone keypad, in particular, and for sending instructions to the bipolar logic. 
     In addition, it is the bipolar logic that performs the voltage regulation function for the microprocessor and which controls conditional initialization of the microprocessor (by controlling a reset pin thereof). 
     During dialing, the bipolar logic short-circuits the telephone line for each dial pulse and for a predetermined length of time, and it puts the output of its voltage regulator into a high impedance state so as to decouple the voltage regulator from the microprocessor. The microprocessor is then powered by discharging a back-up capacitor. 
     In contrast, the reset pin will be subjected to fluctuations relating to the state of the telephone line. Since it is necessary to prevent the microprocessor (and the telephone circuitry in general) from being reset during dialing, and since it is also necessary to reset the microprocessor during power supply interruptions that do not correspond to dialing, it is the practice to use a set of discrete components, capacitors, diodes, resistance networks, and transistors, for the purpose of stabilizing the state of the reset pin during power supply interruptions of acceptable characteristics (dialing). 
     This stabilization circuit is bulky and is installed between the bipolar logic and the microprocessor. An object of the invention is to omit this additional stabilization circuit, thereby eliminating problems of bulk and of calibrating the values of its components. Another object of the invention is to make use of items that are programmable so as to provide a conditional initialization circuit that is flexible and adaptable. 
     SUMMARY OF THE INVENTION 
     The present invention therefore provides a conditional initialization circuit for circuitry that is remotely powered over a transmission line for transmitting pulses obtained by short-circuiting the transmission line for specific durations, with short-circuiting of the transmission line causing the power supply to the remotely powered circuitry to be interrupted, with power to the remotely powered circuit being maintained by means of a capacitor during such a short-circuit, wherein the conditional initialization circuit includes a counter for measuring the duration of a short-circuit, and means for comparing the duration of a short-circuit with at least one specified duration, to cause the remotely powered circuitry to be initialized if the duration of a short-circuit is less than or greater than a specified duration. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other characteristics and advantages of the invention are described by way of the non limiting examples in the following description which is made with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram showing the internal functions of a conditional initialization circuit constituting a first embodiment of the invention; 
     FIG. 2 is a timing diagram showing the operation of the conditional initialization circuit constituting the first embodiment of the invention; 
     FIG. 3 is a block diagram showing the internal functions of a conditional initialization circuit constituting a second embodiment of the invention; 
     FIG. 4 is a timing diagram showing the operation of the second embodiment of the conditional initialization circuit of the invention; and 
     FIG. 5 shows one example of the pulse characteristics that can be accepted by the conditional initialization circuit constituting the second embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram of the internal functions of a conditional initialization circuit constituting a first embodiment of the invention. In this circuit the initialization condition is simple: if the duration d of a pulse present on the line being monitored is less than or greater than, e.g. greater than, a duration d0 corresponding to a determined characteristic, then initialization takes place. For a telephone, the line being monitored is the telephone line and the single characteristic (d0) could correspond to dial pulse duration. 
     The conditional initialization circuit 1 has an input pin B which is connected to the remote power supply line being monitored (e.g. a telephone line). It includes a counter CO provided with a presettable register R, a clock input H, an initialization input C (for &#34;clear&#34;) and a pulse output Q. A circuit 2 for controlling circuit initialization provides a general initialization command RAZG for the circuitry as a whole. The circuit 2 has an input connected to receive the output RAZE from the initialization circuit. It may receive other inputs: for example in a telephone application it receives a flag signal COMB indicating that the telephone is &#34;off-hook&#34;. The output RAZG constitutes, in particular, an initialization signal for the conditional initialization circuit 1. 
     In this first embodiment, an OR gate OU has one input connected to receive the signal B that is being monitored and another input connected to receive the general initialization signal RAZG, and it produces an output signal G. 
     This signal G is connected to the clear input C of the counter CO. The inverse thereof, /G, is connected to one input of an AND gate ET. The other input of the AND gate ET is connected to receive a clock signal CLOCK. The output from the AND gate ET constitutes the clock input H to the counter. 
     The presettable register R of the counter is initialized on clearing to a value n presented on inputs D0-D7 of the counter, for example. The value n may be presented by a memory register MEM. It could also be presented by a microprocessor. 
     The Q output from the counter and the inverted output /G from the above-described OR gate OU constitute inputs to an AND gate ET&#39;. The output from the AND gate ET&#39; constitutes the output RAZE of the conditional initialization circuit 1. 
     In addition, in this embodiment, the following conventions are used concerning the active levels of the various signals: 
     the signal B is active low: in the present case, a low level on B corresponds to a power supply interruption; 
     the beginning of the interruption thus corresponds to a falling edge and the end of the interruption to a rising edge; 
     the signal RAZG is active high: a high level of the signal causes general initialization of the circuit to take place; 
     the signal C is active high, i.e. a high level on C clears the counter; 
     on receiving a rising edge on its clock input H, the counter decrements its register R by unity; 
     the signal Q is active high and the Q output is a pulse output: when the register R passes through 0, a &#34;positive&#34; pulse appears on the Q output; and 
     the signal RAZE follows the same convention as the signal Q. 
     Such a circuit thus operates as follows: 
     General initialization of the circuit caused by RAZG taking up a high level (RAZG=1) causes the counter to be cleared. In particular, the presettable register R is initialized when the signal RAZG takes up a high state (rising edge) to a value n which is present on the inputs D0-D7 of the counter. In addition, while the signal RAZG is at 1, the signal /G is at 0 and prevents the clock signal CLOCK from being transmitted to the clock input H of the counter: the counter is stopped. It may be observed that the signal B taking up the 1 state has the same effects. 
     When RAZG is 0, if the signal B goes to 0, i.e. in the present example when there is a power supply interruption on the telephone line, the signal /G goes to 1 and thus allows CLOCK to be transmitted to the clock input H. On each clock pulse, e.g. on each rising edge applied to the clock input H, the register R is decremented by unity. If the register R began by containing the value n, then after n clock pulses it would contain the value zero: i.e. after a certain time lapse t r  =n/f h , where f h  is the frequency of the clock, the register contains the value zero. At the end of this time lapse t r , which is referenced relative to a time t0 when the signal B switched to the low level (a falling edge in B), a positive pulse appears at the Q output of the counter. 
     If the signal B is still at zero, then the negative pulse on B is longer than the time lapse t r  counted by the counter: the rising edge in the signal RAZE causes a general initialization of the circuit to occur. 
     If the signal B switches back to 1 before the register R reaches 0, or at the same moment as the register R switches to 0, then general initialization does not take place and RAZE remains at 0. The counter is reinitialized as described above by the rising edge in B. 
     The operation described above is defined by the following equations: 
     
         H=NOT(B OR RAZG)AND CLOCK 
    
     
         C=(B OR RAZG) 
    
     
         RAZE=NOT(B OR RAZG) AND Q 
    
      AND Q 
     This operation is also illustrated by the timing diagram of FIG. 2 which corresponds to a power supply interruption of duration d greater than the designed duration d0=n/f h . 
     This first embodiment of a conditional initialization circuit thus serves to initialize the circuitry whenever an interruption on the remote power supply line lasts longer than a determined duration d0, and it does this by using a counter having a clock frequency f h , which counter is started on the appearance of the interruption, with the determined duration d0 being calculated by counting down from the value n loaded into the counter such that d0=n/f h . 
     Unfortunately, although this circuit has the advantage of being simple, it is capable of taking in account one pulse characteristic only. 
     In a telephone application, the condition for acceptable pulses may comprise a set of characteristics as shown in FIG. 5: starting from a reference instant t0, any pulse of duration lying in the range (t1-t0; t2-t0) or in the range (t3-t0; t4-t0) may be acceptable, while pulses of durations lying outside these ranges require general initialization of the circuitry. 
     A second embodiment of a conditional initialization circuit as shown in FIG. 3 makes it possible to implement such complex conditions. 
     The conditional initialization circuit 1&#39; of FIG. 3 includes a counter C1. As in the preceding circuit, the counter is cleared by the signals B or RAZG. In this case, when the counter is cleared, its count register is reset to zero. The register is incremented by clock pulses applied to the clock input H of the counter. The state of the counter is made accessible on counter output pins D0-D7. In this case, the clock signal CLOCK is transmitted to the clock input H of the counter under the control of the signal B, only. If B is at 1, the clock is not transmitted, whereas if B is at 0, transmission takes place. This constitutes a possible variant on the first embodiment of the conditional initialization circuit. 
     The output pins D0-D7 of the counter are connected to inputs A0-A7 of comparators. In this example there are four comparators 10, 20, 30, and 40. Each comparator compares its inputs A0-A7 with other inputs B0-B7 connected to a memory register associated with the comparator: 
     MEM (N1) for the comparator 10 
     MEM (N2) for the comparator 20 
     MEM (N3) for the comparator 30 
     MEM (N4) for the comparator 40 
     In the example, this comparison takes place on a permanent basis, since the state of the counter count register and the contents of the memory registers are permanently available on the inputs A0-A7 and B0-B7. The outputs 11, 21, 31, and 41 of the comparators 10, 20, 30, and 40 respectively are then used to generate various different conditions for causing initialization to take place. 
     In this example, a complex set of conditions is chosen as represented in above-described FIG. 5. 
     Relative to reference time t0, which corresponds to the signal B going to the low level, if the rising edge of the pulse on B appears earlier than t1, or between t2 and t3, or after t4, where t1&lt;t2&lt;t2&lt;t4, then initialization must take place. 
     Thus, in the example, three conditions CN1, CN2, and CN3 give rise to general initialization. Let p be the contents of the count register corresponding to the duration d of the pulse on B multiplied by the clock frequency f h , i.e. p=d.f h . Let Ni=(ti-t0)×f h  for i=1 to 4, for each of the times ti of the complex characteristic chosen (FIG. 5). Then: 
     CN1 corresponds to p&lt;N1; 
     CN2 corresponds to p&gt;N2 AND p&lt;N3; and 
     CN3 corresponds to p&gt;N4. 
     All pulses whose rising edges occur between t1 and t2 or between t3 and t4 are acceptable and do not give rise to initialization. The conditions CN1, CN2, and CN3 are generated from the outputs of the comparators and by means of logic AND, OR, and NOT gates. In the example, the comparator 10 provides a true output if p&lt;N1, the comparator 20 if p&gt;N2, the comparator 30 if p&lt;N3 and the comparator 40 if p&gt;N4. By convention, the output of the comparator is at a 1 state when the comparison performed by the comparator is true. Under these conditions, CN1 is obtained by taking the output 11 from the comparator 10, CN2 by combining the outputs 21 and 31 of comparators 20 and 30 in a logic AND gate; and CN3 by taking the output 41 of comparator 40. 
     The conditions CN1, CN2, and CN3 are thus true if they are at the high level. It thus suffices to apply the three conditions CN1, CN2, and CN3 as inputs to a logic OR gate in order to obtain a general initialization-provoking condition CNG. 
     Nevertheless, the comparison which is of interest is the one which takes place when signal B terminates, i.e. when a rising edge appears on signal B. Unfortunately, the comparators in the present example compare on a continuous basis. The condition CNG should therefore only be taken into account on the rising edge in B. This can be done merely by using a storage component which stores the condition CNG on said rising edge. In the example, a D-type bistable is used, with the signal CNG being applied to the D input thereof and the signal B being applied to the CLK input thereof. When a rising edge appears on B, then the signal CNG is transmitted to the output Q. It is this output Q that then causes initialization to take place. 
     For the comparison with the longest duration (condition p&gt;N4), a simple improvement makes it possible to avoid waiting for the end of the pulse on B: in this example the output CN3 is combined in a logic OR gate with the Q output from the bistable. 
     The output RAZE from the OR gate is connected to the input of the initialization control circuit 2 which delivers the general initialization control signal RAZG. When RAZG is activated, it also serves to reset the D-type bistable to 0. A timing diagram corresponding to the circuit 1&#39; is given in FIG. 4, for the case where p&gt;N2 and p&lt;N3. 
     The circuit 1&#39; has as many comparators as are required for implementing the general initialization condition corresponding to a determined characteristic. There are no particular limits thereon. 
     It is quite possible to trigger comparison only on the rising edge in B. However the comparison time would then be longer than in the example described which uses &#34;tracking&#34; comparators that compare on a permanent basis. 
     In any event, this digital circuit is easily implemented by a microprocessor. In particular, it can easily be integrated in a microprocessor dedicated to telephone applications. 
     Some functions of the device may be performed by microprograms, e.g. the comparison and generation of the general condition in the circuit constituting the second embodiment of the invention (FIG. 3). 
     All of these variants remain within the scope of the invention. In a telephone application, since the conditional initialization circuit can be an integrated circuit or may be implemented by the microprocessor, there is no longer an analog circuit between the bipolar circuit and the microprocessor. Nor is there any need to adjust component values (resistances, capacitances) and the use of such a circuit is more flexible because it can be programmed (by changing the values loaded into the counter, the values loaded into the comparators, and the signs of the comparisons).