Abstract:
A digital frequency synthesizer comprises a programmable frequency divider, an analog-to-digital converter for converting an analog program control signal into a digital signal, and a digital storage medium for storing the digital signal to control the frequency division ratio of the programmable frequency divider in accordance with the digital value of the stored signal.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a digital frequency synthesizer which is immune to small variations of an analog program control signal to maintain the frequency division ratio constant when the variations lie within a predetermined range. 
     Conventional frequency synthesizers of the type which employs a programmable frequency divider make use of an analog-to-digital converter for converting an analog program control signal into a digital signal for controlling the frequency division ratio of the programmable frequency divider. However, the inherent small variation of the analog control signal tends to adversely affect the frequency division ratio. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the invention is to overcome the aforesaid problem by incorporating a memory device for storing the digital signal to maintain the program input constant regardless of the presence of insignificant variations of the analog control signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be further described by way of example with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a prior art frequency synthesizer; 
     FIG. 2 is a block diagram of a frequency synthesizer of the invention; 
     FIGS. 3a to 3m are a waveform diagram useful for describing the operation of the embodiment of FIG. 2 in cases where insignificant variations occur in the analog control signal; 
     FIGS. 4a to 4m are a waveform diagram useful for describing the operation of the embodiment of FIG. 2 in cases where the analog control signal is varied manually for changing the frequency division ratio; 
     FIG. 5 in an illustration of details of the digital-analog converter of FIG. 2; and 
     FIG. 6 is an illustration of details of the digital comparator of FIG. 2. 
    
    
     DETAILED DESCRIPTION 
     Before describing the present invention reference is first made to FIG. 1 in which a prior art frequency demultiplier or divider is illustrated. In FIG. 1, reference numeral 1 is an inverter, which together with a crystal quartz oscillator element 2, resistance 3 and capacitors 4 and 5 constitutes an oscillator. An inverter 6 is provided which serves as a buffer amplifier whose output is connected to the clock input terminal 7a of a flip-flop 7. To the output terminal 7b of the flip-flop 7 is connected an input terminal of an Exclusive-OR gate 8, and to the complementary output terminal 7c of the flip-flop 7 is connected the clock input terminal 9a of a flip-flop 9. To the true output terminal 9b of the flip-flop 9 is connected an input terminal of an Exclusive-OR gate 10 and to the complementary output 9c of the flip-flop 9 is connected the clock input terminal 11a of a flip-flop 11. To the true output terminal 11b of the flip-flop 11 is connected an input terminal of an Exclusive-OR gate 12 and to the complementary output terminal 11c of the flip-flop 11 is connected the clock input terminal 13a of a flip-flop 13. To the true output terminal 13b of the flip-flop 13 is connected an input terminal of an Exclusive-OR gate 14 and to the complementary output 13c of the flip-flop 13 is connected the clock input terminal 15a of a flip-flop 15. To the complementary output 15c of the flip-flop 15 is connected the clock input terminal 16a of a flip-flop 16 whose complementary output 16c is connected to the clock input terminal 17a of a flip-flop 17. 
     Furthermore, another input terminal of each of the Exclusive-OR gates 8, 10, 12 and 14 is connected to program input terminals A, B, C and D, respectively. The output terminals of these Exclusive-OR gates and the true output terminals 15b, 16, and 17b of flip-flops 15, 16 and 17 are connected to respective input terminals of an AND gate 18 whose output terminal is connected to the set input terminals of flip-flops 7, 9, 13 and 15 and also to the reset input terminals of flip-flops 11, 16 and 17, and further to an output terminal E of the frequency divider. 
     Each of the flip-flops 7, 9, 11, 13, 15, 16 and 17 is designed to switch to logic &#34;1&#34;, which appears as a high voltage level at the true output terminal, in response to the leading or positive edge of an input clock pulse when the set and reset input terminals are both at logic &#34;0&#34; or low voltage level, and also switch to logic &#34;1&#34; when each flip-flop receives a logic &#34;1&#34; signal at its set input terminal regardless of the binary state of its clock input terminal, and switch to logic &#34;0&#34; level whenever a logic &#34;0&#34; signal is applied to the reset input regardless of the binary state of the clock input terminal. 
     Assuming that a set of binary signals &#34;0000&#34; is applied to the program input terminals, D, C, B and A, each flip-flop generates a logic &#34;1&#34; output, so that the output of the AND gate 18 is switched to logic &#34;1&#34;, causing flip-flops 17, 16, 15, 13, 11, 9 and 7 to reset to logic levels &#34;0 0 1 1 0 1 1&#34;, respectively. In other words, the output terminal E is preset to a set of binary states &#34;0011011&#34; which is a decimal value of &#34;27&#34; when all the flip-flops are at logic level &#34;1 1 1 1 1 1 1&#34; equivalent to a decimal value of &#34;127&#34;, whereby the frequency divider changes its binary state in 100 discrete steps starting from the decimal value 27 to the decimal value 127. Therefore the output frequency of the driver is 1/100 of the input frequency. 
     Assuming next that the program input is changed to &#34;0001&#34;, the flip-flops will be reset to &#34;0 0 1 1 0 1 1&#34; as counted from flip-flop 17 down to flip-flop 7 when these flip-flops are at logic levels &#34;1 1 1 1 1 1 0&#34;, respectively. In this case, the frequency divider is preset to a division ratio of 1/99. In the same manner, a program signal of &#34;1111&#34; will produce a set of logic levels &#34;1 1 1 0 0 0 0&#34; which cause the flip-flops to change to &#34;0 0 1 1 0 1 1&#34;, presetting the frequency divider to a ratio of 1/85. As seen from Table I, as the program input is varied with a step of binary digit &#34;1&#34; from decimal &#34;0&#34; to decimal &#34;10&#34;, for example, with corresponding frequency division ratios from 1/100 to 1/90 and the input frequency is set at 100 kHz, the output frequency varies from 1000 Hz to 1111 Hz with a variation ranging from +0.000 to +11.111%. 
     
                       TABLE I______________________________________PROGRAMINPUT                   OUTPUT      VARIA-    BINARY   DIVISION  FREQUENCY TIONDECIMAL  &#34;DCBA&#34;   RATIO     (Hz)      (%)______________________________________0        0000      1/100    1000      +0.0001        0001     1/99      1010      +1.0102        0010     1/98      1020      +2.0413        0011     1/97      1031      +3.0934        0100     1/96      1042      +4.1675        0101     1/95      1053      +5.2636        0110     1/94      1064      +6.3837        0111     1/93      1075      +7.5278        1000     1/92      1087      +8.6969        1001     1/91      1099      +9.89010       1010     1/90      1111      +11.111______________________________________ 
    
     If the digital frequency synthesizer of FIG. 1 is employed as a standard variable frequency source in a radio tuner or motor control system, It is desirable that the output frequency be instantly varied in response to the control signal and that the control data be not lost even when power is turned off. 
     For this purpose the use of an analog-to-digital converter may be employed to convert a voltage developed across a variable resistor into a digital value and the latter is used as a control signal for altering the frequency division ratio. However, the voltage developed across the variable resistor tends to fluctuate in response to noise or aging of the variable resistor. This introduces an error in the analog control value which results in an error of at least one digital count. 
     For example, if the user makes and adjustment to the analog control value so that the output frequency of the system of FIG. 1 undergoes a frequency shift of 2%, the corresponding digital control value may fluctuate between &#34;0 0 0 1&#34; and &#34;0 0 1 0&#34; or between &#34;0 0 1 0&#34; and &#34;0 0 1 1&#34;, and as a result the output frequency discretely varies between 1% and 2% values or between 2% and 3% values as seen from Table I. In other words, the system as a whole has a low degree of precision due to the inherent fluctuation factors which are present in the interface between analog and digital systems, even though a high precision type frequency oscillator such as crystal controlled oscillator is employed as a standard frequency source. 
     The present invention will now be described with reference to FIG. 2. The system of FIG. 2 comprises a programmable frequency divider 20 which receives input clock pulses from a clock source or any external signal source 19 and delivers frequency-divided output signal on terminal 20a depending on a set of binary states of its input terminals A, B, C and D arranged in the order from the least significant bit to the most significant bit. A frequency divider 21 is provided which divides the frequency of the input signal source 19 with a fixed division ratio and supplies its output to an input terminal 22a of a 6-bit down counter 22 and also to an input terminal 23a of a control circuit 23. The signal supplied from the divider 21 is used as a clock signal of the system of FIG. 3 and the 6-bit down counter 22 increments its count in response to this frequency divided clock pulse and delivers a set of 64 different combinations of binary states on its output terminals 22b, 22c, 22d, 22e, 22f and 22g arranged in the order of the least significant bit to the most significant bit. Therefore, the terminal 22g, which is the most significant bit terminal, remains at high voltage level during the first half of the counter cycle and remains at low voltage level during the second half cycle. The output terminals 22b to 22f of the down counter 22 are connected respectively to data input terminals D1 to D5 of a latch circuit 24 whose inverted output terminals Q1 to Q5 are connected to respective terminals of a digital comparator 26 and whose Q2 to Q5 terminals are connected respectively to terminals A to D of the programmable divider 20. The digital comparator 26 receives its other input signals from the down counter 22 through its terminals 22b to 22f to compare the input and output binary data of the latch 24 and delivers a logic &#34;1&#34; to an input terminal 23c of the control circuit 23 when there is a coincidence between them. 
     The output terminals 22b to 22f of the down counter 22 are also coupled to a digital-to-analog converter 25 wherein the latch input binary data is converted into an analog voltage which is applied to the noninverting input of a voltage comparator 29. The voltage comparator 29 compares it with a setting voltage derived from a tap 28b of a potentiometer 28 which is connected between a voltage stabilizer 27 and ground. The D-A converter 25 is also powered from the voltage stabilizer 27 to minimize the effect of source voltage fluctuation by cancelling it in the comparator 29. The output of this comparator is at low voltage level when the analog voltage from the D-A converter 25 is lower than the setting level, presented at its inverting input, and switches to a high voltage condition in response to the analog voltage exceeding the setting level and supplies its output signal to an input terminal 23d of the control circuit 23. 
     The control circuit 23 comprises generally a 2-bit counter 70 including flip-flops 47 and 48 and a NAND gate 49 having its one input coupled to the Q output of flip-flop 48 and its other input connected to the Q output of flip-flop 47 to generate a low level output when the counter 70 has received two input pulses supplied through terminal 23a and through a NAND gate 46 and inhibits the latter in response to that low level output. An edge detector 71 is provided which comprises three NAND gates 52, 53 and 58 to generate a low level pulse in response to the voltage applied to terminal 23d changing from low to high voltage levels, that is, when the analog voltage from converter 25 exceeds the setting level. Another edge detector 72 includes three NAND gates 56, 57 and 60 which are similar in operation to the edge detector 71 and receives its input signal from terminal 22g of down counter 22 through input terminal 23b, and applies its low level output pulse through an inverter 61 for purposes of resetting the flip-flops 47 and 48 of the 2-bit counter 70. The control circuit 23 further includes a flip-flop 73 comprised of two NAND gates 54 and 59 each having the output terminal connected to an input of the other NAND gate. The NAND gate 54 receives its another signal from the digital comparator 26 through terminal 23c and delivers a high voltage output to an input of an Exclusive-OR gate 51 whose other input is connected to the output of voltage comparator 29 through terminal 23d. The NAND gate 59 receives its other input signal from the output of NAND gate 56 of edge detector 72 for purposes of resetting the flip-flop 73, that is, the output of NAND gate 54. 
     As will be described later in detail, the down counter 22 generates all &#34;1&#34;s binary data initially and decrements it in response to each input clock pulse received at terminal 22a until all &#34;0&#34;s appear at its terminals 22b to 22f and on the other hand, the D-A converter 25 provides inversion of the binary decreasing input data and generates an analog voltage which increases with time until the contents of the down counter 22 become all &#34;0&#34;s. Thus, if the voltage setting at the potentiometer 28 should deviate from the initial setting level to which the binary contents of the latch circuit 24 correspond, there will be a difference in voltage level between the output of voltage comparator 29 and the output of flip-flop 73, causing a high voltage output to appear at the output of Exclusive-OR gate 51 to activate an AND gate 55 when the latter is enabled in the presence of a high voltage signal from the terminal 22g of the down counter 22. During the time when the AND gate 55 is activated the flip-flops 47 and 48 of the 2-bit counter 70 are enabled to initiate counting operation. 
     The control circuit 23 further includes an OR gate 50 which takes its inputs from the terminal 22g of the down counter 22, the output of NAND gate 49 of counter 70 and from the output of edge detector 71 to generate a low level pulse when its inputs are all at logic &#34;0&#34;s for purposes of resetting the latch circuit 24 through terminal 23e to store the binary count of down counter 22. Since the output of 2-bit counter 70 remains at high output state if it receives only one clock pulse, the contents of latch circuit 24 remain unchanged if the fluctuation of the voltage at the terminal 28b of the analog setting potentiometer 28 remains within a range which corresponds to a range of ±1 clock pulse or discrete variation of ±1 binary digit in down counter 22. The latch 24 is reset only if the voltage deviation exceeds an amount corresponding to a range of ±2 clock pulses. 
     This will be explained in more detail with reference to FIG. 3. Suppose that the logic states of the memory latch 24 are &#34;1 1 1 0 0&#34; which are the digital representation of the voltage given by the potentiometer 28, the inverted logic states &#34;0 0 0 1 1&#34; appear at the Q5, Q4, Q3, Q2 and Q1 output terminals, respectively, so that the logic states of the program terminals D, C, B and A of the frequency divider 20 are respectively &#34;0 0 0 1&#34; which corresponds to a frequency division ratio of 1/99 (see Table I). FIG. 3a shows the digital value of the down counter 22 in analog form. A decrement of the down counter to a level corresponding to &#34;1 1 1 0 0&#34; which is now stored in latch 24 will cause the digital comparator 26 to produce a logic &#34;0&#34; pulse (FIG. 3b) which is coupled to terminal 23c to cause NAND gate 54 to deliver a logic &#34;1&#34; to Exclusive-OR gate 51. If there is no voltage drift on the potentiometer terminal 28b, the voltage comparator 29 will deliver a logic &#34;1&#34; almost at the same instant as the output from the digital comparator 26, so that the output of Exclusive-OR gate 51 will remain unchanged. If the potentiometer 28 has a voltage drift &#34;e&#34; (FIG. 3c) which corresponds to one clock pulse count, the analog comparator 29 will produce a high level output 29-1 a one clock period later than the time the output from the digital comparator 26 is delivered (FIGS. 3d and 3e) and Exclusive-OR gate 51 will produce an output pulse 51-1 (FIG. 3g) in the presence of a high voltage state of the MSB terminal 22g of the down counter 22 (FIG. 3f). As a result, AND gate 55 is activated (FIG. 3h) to enable the 2-bit counter 70 to receive one clock pulse through NAND gate 46 (FIG. 3l). Therefore, the logic &#34;0&#34; output state of the counter 70 remains unchanged (FIG. 3m) and the OR gate 50 also remains disabled (FIG. 3k) to prevent delivery of a latch resetting pulse 52-2 to the latch 24 which is generated by NAND gate 52 of edge detector 71 in response to the leading edge of the output 29-2 from the voltage comparator 29 (FIG. 3i) when the MSB terminal 22g of the down counter changes to logic &#34;0&#34; state during the second half period of the counter cycle. The logic state of the latch 24 thus remains unchanged regardless of a setting voltage variation if it lies within a range of analog equivalents of ±1 clock pulse count. 
     Assume that the potentiometer 28 is readjusted to a new value which corresponds to a digital value of &#34;1 1 0 1 0&#34;. As illustrated in FIG. 4d, the voltage comparator 29 produce an output 29-3 in response to the analog equivalent of the digital output from the down counter 22 coinciding with the voltage at terminal 28b when the down counter 22 decrements to logic state &#34;1 1 0 1 0&#34; at a point in time delayed by the period of two clock pulses from the time of delivery of an output 26-1 from digital comparator 26 (FIG. 4b), so that Exclusive-OR gate 51 produce a high voltage pulse 51-2 of two-clock-pulse period to allow the 2-bit counter 70 to count two clock pulses, thus resulting in a low output voltage at the output of the counter 70 (FIGS. 4l and 4m). An output pulse 29-4 generated by the voltage comparator 29 during the second half period of the down counter cycle will cause a logic &#34;0&#34; output 52-4 to be present at the output of NAND gate 52 of edge detector 71. Since OR gate 50 is enabled by the low level output from the counter 70, it produces a latch resetting pulse 50-1 in response to the pulse 52-4 to reset the latch 24 to the logic state &#34;1 1 0 1 0&#34; and shifts the frequency division ratio to 1/98. 
     FIG. 5 illustrates details of the D-A converter 25 which includes a plurality of CMOS inverters 30 to 34 connected to receive binary signals through terminals 22b to 22f of the down counter 22, respectively, having their positive power supply terminals connected together to a terminal 25a which is connected to the stabilized voltage source 27. The respective output terminals of the inverters 30 to 34 are connected to a digital-analog conversion resistance network generally known as R-2R network. The output voltage developed between lead 25x and ground is approximately 2 Es/3 when all the input voltages to the inverters 30 to 34 are logic &#34;0&#34;s, where Es is the voltage at terminal 25a, and is zero when all the input voltages are logic &#34;1&#34;s. Therefore, the voltage at lead 25x varies 32 discrete steps in a range between zero and 2Es/3 in response to each clock pulse. The circuit including transistors 35 to 39 serves to multiply the voltage at point 25x by 3/2 so that the voltage at a circuit point 25g discretely varies between zero and Es. More specifically, transistor 35 forms a constant current source which together with transistors 36, 37 and amplifier transistor 38 forms a voltage comparator whose output is supplied to a supply voltage control transistor 39 so that the voltage at a circuit point 25y varies stepwisely in a range between zero and 2Es/3 and in response to this the voltage at point 25g varies in the range of from zero to Es. 
     FIG. 6 is an illustration of details of the digital comparator 26 which, as shown, comprises a plurality of Exclusive-OR gates 40 to 44 each having their one input terminals connected respectively to the Q terminals of the latch 24 and have their another input terminals connected to the outputs of down counter 22 respectively. The output terminals of these Exclusive-OR gates are connected to a NAND gate 45 whose output is connected to terminal 23c of the control circuit 23. The NAND gate 45 thus delivers a logic &#34;0&#34; output when coincidence occurs between the logic states of the latch 24 and the logic states of the down counter 22. 
     The clock signal used to control the program input to the programmable frequency divider 20 may also be obtained from a suitable source independent from the input signal source 19. The operating frequency of the latch 24 and its associated circuitry is selected at a value much lower than the frequency of the standard frequency source 19. This allows the frequency divider 21 to be advantageously employed to reduce the standard frequency to the selected value. To minimize power consumption if the system is to be constructed of LSI circuitry, it is preferred that the operating frequency be as low as possible since the power consumption increases in proportion to the upper limit of the operating frequency. 
     The use of latch circuit 24 as a memory unit permits visual display of the output frequency value by operating the D-A converter 25, down counter 22, control circuit 23 and voltage comparator 29 on a time-sharing basis, and such time sharing operation would permit the counter 22 to be used for other purposes with a resultant decrease in number of the system components and a reduction of power consumption and manufacturing cost. 
     Another feature of the invention resides in the use of the stabilized voltage source 27 which supplies constant voltage to the D-A converter 25 and to the voltage setting potentiometer 28. Any voltage variation that occurs in the voltage stabilizer 27 will cause the voltages at the input terminals of the comparator 29 to vary by equal amounts so that such variations are cancelled out at the output of the comparator 29. 
     The foregoing description shows only preferred embodiment of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention. For example, a frequency multiplier may be constructed of a phase locked loop including the programmable frequency divider of the invention and a voltage controlled oscillator, whereby the output frequency of the voltage controlled oscillator varies in proportion to the adjustment of a potentiometer to derive a frequency-multiplied output. Therefore, the embodiment shown and described is only illustrative, not restrictive.