Abstract:
A multi-range measuring circuit for measuring a flow of electrical current between a first node and a second node. A measurement resistor is connected to the first node to develop a voltage having a high range output. A summing node connected in series with the measurement resistor acts as an input to an amplifier for developing a second voltage having a low range output having a higher scale factor than the high range output. If the capacity of the amplifier to maintain the low range as a linear function is exceeded, a bypass circuit bypasses excess current flow to the second node.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
         [0001]    Not Applicable  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a multiple range current measuring system and more particularly to a current measuring system having a low power loss, fast settling time and low common mode voltage error.  
           [0004]    2. Description of the Related Art  
           [0005]    Conventional dual range current measurement circuits include a parallel shunt and a series shunt configuration, as shown in FIGS. 1 and 2, respectively. These configurations have several disadvantages that warrant the need for an alternate topology to perform multiple range current measurements. These conventional circuits will be discussed along with their relative disadvantages.  
           [0006]    Referring to FIG. 1, a current I 1  is produced by an external source of current and is directed through measurement shunt resistance RH or RL by closing switch SH or SL. Switches SH and SL are independently operated by external controls, which are not shown. Where a high range measurement is desired, switch SH is closed allowing current I 1  to flow through RH to circuit common. With switch SH closed, a voltage drop develops across RH at the noninverting (+) and inverting (−) input terminals of high input impedance, fixed gain instrumentation amplifier U 2 . The gain of amplifier U 2  is set to obtain a convenient volt per amp scale factor output voltage versus input current I 1 . Given the direction of current flow and the orientation of the input terminals of the amplifier U 2  as shown in FIG. 1, a positive voltage (ImonH), with reference to circuit common, will result at the output of the instrumentation amplifier U 2 .  
           [0007]    Switching from a high range measurement to a low range measurement in a minimally disruptive way requires closing switch SL in a make before break fashion and then opening switch SH. By measuring a voltage drop across shunt RL with instrumentation amplifier U 1 , a voltage, I monitor low (ImonL) is developed with respect to the circuit common. Capacitor CL connected in parallel with relatively high value shunt resistance RL, serves to filter noise and to provide a low dynamic impedance between the external source of current and circuit common. Using this measurement scheme, the value of shunt RL will be greater than the value of shunt RH to allow for more sensitive measurements of low level currents. In the arrangement of FIG. 1, either ImonH or ImonL is available, but not both simultaneously.  
           [0008]    The series shunt arrangement operates in a manner somewhat similar to the operation of the parallel shunt configuration shown in FIG. 1. Referring now to FIG. 2, a current I 1  flows from an external source through a resistor RH where a voltage drop is developed. This voltage drop is impressed upon the inverting (−) and non-inverting (+) terminals of the high input impedance, fixed gain instrumentation amplifier U 2  producing the ImonH voltage with reference to the circuit common. With ImonH active and ImonL not active a switch SL is closed across a shunt resistance RL, allowing large currents to flow without a substantial voltage drop. To perform a low range measurement, the switch SL is opened allowing current flow through the shunt resistance RL, permitting a low range measurement in a manner similar to the parallel arrangement of FIG. 1. During a low range measurement, current is also flowing through the resistor RH, and thus the signal ImonH is always available.  
           [0009]    An alternate arrangement of the series shunt topology is shown with broken lines in FIG. 2. In the alternate arrangement, the switch SL is not used and a dual polarity shunt regulator SR 1  is placed across RL. A simple example of such a shunt regulator is shown as diodes D 1  and D 2 . The configuration of FIG. 2 provides a bypass for RL without external switch control.  
           [0010]    The series and parallel shunt configurations share disadvantages that warrant a need for a new topology. In both the series and parallel shunt arrangements, the insertion impedance of the measurement circuit may be larger than desired and the insertion impedance will change abruptly as various shunts are switched in and out of the circuit. Switching between measurement shunts contributes to settling time problems in the measuring circuit and causes disturbances in the external current flow due to the change in impedance of the measuring circuit.  
           [0011]    The use of either solid state or mechanical relays in the circuits of FIG. 1 and FIG. 2 presents several areas of concern. In particular, complex switch control is required to change from one-measurement range to another. Switch control does not occur automatically and can result in shunts being overpowered if a high current is not diverted around the shunt RL. In addition, if mechanical switches are used, contact bounce and lifetime become an issue. Solid state switches are prone to leakage and surge currents can damage solid state or mechanical switches.  
           [0012]    The capacitor CL, which is placed in parallel with the resistor RL in both topologies, results in a long settling time constant, increasing the time required to take an accurate reading of the ImonL voltage signal. The capacitor CL may also cause measurement errors by leaking current around the shunt resistor RL which is in parallel with the capacitor CL in the circuits of FIGS. 1 and 2.  
           [0013]    In the case of the series shunt arrangement that utilizes the shunt regulator SR 1 , significant power may be dissipated in the resistor RL and shunt regular SR 1 , especially for high values of current. Additionally, leakage currents in the shunt regulator SR 1  can cause measurement errors in the ImonL signal.  
         SUMMARY OF THE INVENTION  
         [0014]    The present invention is a multi-range measuring circuit for measuring a flow of electrical current. An in-line sensor outputs a first signal proportional to the current and having a first scale factor. An amplifier circuit is serially connected with the in-line sensor and outputs a second signal having a second scale factor proportional to the current. A bypass circuit bypasses a portion of the input current around the amplifier circuit at values of the input current where the amplifier circuit is non-linear. The in-line sensor may be a resistor.  
           [0015]    The bypass circuit comprises one of a P-type MOSFET, an N-type MOSFET or a P-type MOSFET parallel connected with an N-type MOSFET. The amplifier circuit comprises an inverting amplifier serially connected with a non-inverting amplifier and the non-inverting amplifier outputs the second signal. A control signal to operate the bypass circuit is output by a deadband circuit which is connected to the inverting amplifier. The deadband circuit is interposed between the output of the inverting amplifier and the bypass circuit. The deadband circuit passes the control signal where a value of the control signal is greater than a first predetermined value or less than a second predetermined value and rejects the control signal where the value of the control signal is intermediate the first and second predetermined values. The inverting amplifier operates in a first control loop where the deadband circuit rejects the control signal and operates in a second control loop where the deadband circuit passes the control signal.  
           [0016]    The amplifier circuit comprises a summing node which receives the input current and the inverting amplifier is connected to the summing node. The non-inverting amplifier is connected to an output of the inverting amplifier and a feedback resistor is connected between an output of the non-inverting amplifier and the summing node, to regulate the second signal to be proportional to the current and according to the second scale factor. The deadband circuit comprises, for example, a diode network which determines the respective predetermined positive and negative values and the diode network comprises a plurality of series connected junction diodes. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    The present invention will become more apparent and more readily appreciated from the following description of the various embodiments, taken in conjunction with the accompanying drawings in which:  
         [0018]    [0018]FIG. 1 is a schematic diagram of a conventional parallel shunt dual range measuring circuit;  
         [0019]    [0019]FIG. 2 is a schematic diagram of a conventional series shunt dual range measuring circuit;  
         [0020]    [0020]FIG. 3 is a schematic diagram of a unipolar embodiment of the present invention;  
         [0021]    [0021]FIG. 4 is a schematic diagram of a bipolar embodiment of the present invention;  
         [0022]    [0022]FIG. 5 is a is a partial schematic showing an input offset nulling circuit;  
         [0023]    [0023]FIG. 6 is a plot of various voltages versus input current I 1 ,  
         [0024]    [0024]FIG. 7 is a schematic of the deadband circuit shown in FIG. 4;  
         [0025]    [0025]FIG. 8 is a plot of the transfer characteristic of the deadband circuit of FIG. 7; and  
         [0026]    [0026]FIG. 9 is a schematic of an arrangement that provides additional measurement ranges. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]    Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.  
         [0028]    Referring now to FIG. 3, a unipolar multiple range current measuring cirsuit is illustrated. The measurement circuit of FIG. 3 operates by transitioning through five primary modes of operation as a current It increases from zero. Each of these modes will be discussed in detail with reference to the schematic of FIG. 3 and the input-output plots shown in FIG. 6. The input-output plots shown in FIG. 6 are also applicable to results for the bipolar current measurement system of FIG. 4. In order to simplify the explanations of the systems, system operation will be explained with reference to the unipolar measuring system of FIG. 3. The operation of the bipolar measurement of FIG. 4 and the portions of the input-output plots of FIG. 6 associated with the bipolar measurement system of FIG. 4 will be readily understood based on the explanations of the unipolar measurement system of FIG. 3.  
         [0029]    The current I 1 , shown in FIG. 3, is produced by an external source of current and flows through the unipolar multiple range current measuring system and returns via a return node or terminal that is connected to circuit common. The current I 1 , flowing through a resistor RH, produces a voltage difference across the inverting (−) and noninverting (+) input terminals of a high input impedance instrumentation amplifier U 2 . Given the direction of current flow as indicated by I 1  and the orientation of the instrumentation amplifiers inputs as shown in FIG. 3, a positive voltage, I monitor high (ImonH) with reference to circuit common will result at the output of the amplifier U 2 . Assuming that the current I 1  does not does not produce a voltage drop across RH large enough to clip instrumentation amplifier U 2 , the voltage ImonH is always proportional to the current I 1 , independently of the operating region of the remainder of the measuring circuit. In general, since the ImonH voltage is optimized to measure larger currents, there will be insufficient accuracy when attempting to measure low values of current. Hence, a low range measurement circuit is necessary.  
         [0030]    Referring now to FIGS. 3 and 6, the operation of the circuit of FIG. 3, will be explained in conjunction with the various regions shown in FIG. 6. In FIG. 3, a node  41  operates as a summing junction for the current I 1  flowing from the external current source and a feedback current I 2  flowing through a resistor R 12 . During operation in Region  1 , the ImonL output of an amplifier U 4  is given by:  
         
       I 
       monL 
       =−I 
       2 
       R 
       12  
     
         [0031]    where the ImonL output is linearly related to I 1  and I 2  is substantially equal to I 1 . This is true as long as the current I 1  is less than a value which is given by:  
         I   1     &lt;            I     m                 o                 n                 L                 C                 l                 ipp                 e                 d         R   12                                  
 
         [0032]    where ImonLClipped is the maximum possible output voltage of amplifier U 4 . With the circuit operating in Region  1 , P-channel MOSFFET Q 1  is off and the voltage (Vin) at node  41  is held at approximately zero, resulting in a value of I 3  essentially equal to zero. Any value of I 3  present in the Region  1  of operation would be due to an input bias current of operational amplifier U 3 . Thus:  
         [0033]    The non-inverting input (+) of amplifier U 3  is biased relative to circuit common through resistor R 26 . The input offset voltage of amplifier U 3  may be trimmed out by using an adjusting circuit, such as for example, the potentiometer R 28  and the resistor R 27  connected as shown in FIG. 5.  
         [0034]    The current  12  flowing through resistor R 12  produces a voltage I monitor low (ImonL) relative to circuit common. The current  12  enters the output stage of amplifier U 4 , returning to circuit common through a VS 2  bias supply connection which completes a dc path to the external source of current. A resistor R 13  and a capacitor C 12  are connected between the output of amplifier U 4  and the inverting input of amplifier U 3  to create an AC summing junction at the inverting input of amplifier U 3 . In Region  1 , the resistor R 13  and the capacitor C 12  provide frequency compensation for stability and increased phase margin. The resistor R 13  and the capacitor C 12  control bandwidth and settling time. Compensation resistor R 13  and capacitor C 12  are not placed across R 12  due to the presence of a capacitor C 14  between the node  41  and the circuit common because such a connection would add an additional pole to the open loop gain of the system. The impedance of R 11  serves to isolate or separate the AC summing junction at the inverting input of the amplifier U 3  and the effective “DC” summing junction at the node  41 .  
         [0035]    Amplifier U 4  is an operational amplifier which is configured as a non-inverting amplifier using resistors R 16  and R 17  and has a non-inverting fixed dc gain given by:  
           R   16       R   17       +   1                         
 
         [0036]    The amplifier U 4  is used in conjunction with the amplifier U 3  to increase the overall gain of the loop and to limit the power dissipation in the amplifier U 3 . A high loop gain allows the measuring system of FIG. 3 to overcome several of the limitations found in both the parallel and series shunt configurations of FIGS. 1 and 2. Specifically, high loop gain reduces the dc insertion impedance of the circuit in the linear Region  1 . Assuming R 22  to be large, negative feedback causes the dc insertion impedance between the measurement nodes, indicated as Input and Return in each of FIGS. 3, 4 and  9 , of the circuit to be:  
         R     D                 C       ≈         (     R   12     )       1   +       (   A1   )          (   A2   )           +     R   H                             
 
         [0037]    where A 1  is the closed loop dc gain of the amplifier U 4  and A 2  is the open DC loop gain of the amplifier U 3 .  
         [0038]    The amplifier U 3  is selected to have a high open loop gain resulting in a dc insertion impedance that is greatly reduced from the value of R 12  alone. At mid frequencies the insertion impedance rises due to a decrease in the open loop gain of U 3 , but still maintains a low value. At high frequencies capacitor C 14  reduces the insertion impedance once again, as the open loop gain eventually falls to a low level.  
         [0039]    In the linear region of operation of ImonL (Region  1 ), the voltage between node  41  and common is maintained approximately at the input offset voltage Vos of amplifier U 3 , assuming R 22 &gt;&gt;R 11 . This offset voltage can be trimmed to zero using a circuit comprising a potentiometer R 28  and a resistor R 27  as shown in FIG. 5. With zero volts across MOSFET Q 1  and capacitor C 14 , any leakage current is eliminated and I 3  is kept at a very low value determined primarily by the input bias current of U 3 . For example, by using an amplifier with a field effect transistor (FET) input stage, the input bias current can be reduced to an extremely low value, which can be considered essentially zero. Thus for all practical purposes,  
         I 2 =I 1   
         [0040]    and ImonL very accurately reflects the input current I 1 .  
         [0041]    With the offset voltage trimmed to common, node  41 , the source of the MOSFET Q 1 , is maintained at zero volts because a dead band circuit, comprising diodes D 12 , D 13 , D 14 , and D 15  and resistors R 18  and R 19 , is not conducting and the inverting input to amplifier U 3  is maintained at circuit common, thus, both nodes of R 22  are maintained at zero volts with respect to circuit common. Resistor R 24  serves to bypass any small reverse leakage current through diode D 12 . Amplifier U 3  is selected to have a high impedance input stage requiring a small input bias current. In order to smoothly proceed through the five regions of operation shown in FIG. 6, without any hysteresis effects, the effective offset voltage at the inverting input of amplifier U 3  must satisfy the following condition:  
              V     O                 S                 E                 F                 F            &lt;            V     S                 G                 T                 (       R   11       R   22       )                             
 
         [0042]    where VSGT is the source to gate threshold voltage of the MOSFET Q 1 . (See also the discussion below regarding Region  3 .) Where the nulling circuit shown in FIG. 5 is used, VOSEFF is equal to the trimmed voltage at the inverting input of amplifier U 3 . If the nulling circuit shown in FIG. 5 is not used, VOSEFF is equal to the input offset VOS of the amplifier U 3 .  
         [0043]    The circuit of FIG. 3 will continue to operate in Region  1  as long as the magnitude of the potential at node  42  (Vout), which is calculated as:  
         V     o                 u                 t       =       I     m                 o                 n                 L         1   +       R   16       R   17                                 
 
         [0044]    is below a voltage threshold VDBTH of the dead band circuit attributed to the forward voltage drop across diodes D 12 , D 13 , D 14  and D 15 . As the current It increases, the voltage ImonL will increase in the negative sense until I 2 max is reached. Where I 2 max is defined as:  
         I     2      max       =         I     m                 o                 n                 L                 c                 l                 ipp                 e                 d         R   12       .                           
 
         [0045]    To further clarify the change in potential of key points in the circuit, a plot of the voltage Vout (node  42 ) versus current I 1 , a plot of the voltage of ImonL versus current I 1  and a plot of the voltage Vin (node  41 ), are shown in FIG. 6 for the various regions of operation. It is noted that Region  1  is the most useful operating region in that the ImonL output signal is linear and ImonL accurately indicates the value of I 1 .  
         [0046]    As I 1  continues to increase, the operation mode moves from Region  1  to Region  2  where amplifier U 4  and voltage ImonL are clipped. Where amplifier U 4  clips, the voltage Vout at node  42  rises (in the negative sense). The voltage ImonL will remain at a clipped value regardless of increases in I. In this Region, I 3  is no longer zero, but flows through R 11 , R 22 , diodes D 12 , D 13 , D 14 , D 15  and back to circuit common through the bias supply connection VS 2  of amplifier U 3 . The MOSFET Q 1  source current is still zero since Vgs of the MOSFFET Q 1  is below a threshold value. The dc impedance at node  41  is equivalent to the parallel combination of R 12  and R 11 , hence the slope of Vin in Region  2  of FIG. 6.  
         [0047]    Further increases in the current I 1  cause the operation mode to transition to Region  3 . During operation in Region  3 , the MOSFET Q 1  is in saturation:  
         
       V 
       in 
       −V 
       G 
       =V 
       SGT  
     
         [0048]    and R 21  and C 13  are used to assure closed loop stability. In order to insure low impedance at node  41 , the MOSFET Q 1  is effectively configured as a shunt regulator source follower. This arrangement is utilized because the source follower configuration has an inherently low output resistance.  
         [0049]    In Region  3  of FIG. 6, the voltage Vin versus I 1  rises along with a corresponding change in the voltage Vout versus I 1 . It should be noted that the slight slope seen on the Vin verses I 1  curve for Region  3  is related to the gm of the MOSFET Q 1  and, assuming a high open loop DC gain of amplifier U 3 , the slope is calculated as:  
           R   12     //     R   11       //       [       1     g   m         (     1   +       R   22       R   11         )       ]     .                           
 
         [0050]    A schematic of a dead band circuit for a bipolar current measuring system is shown in FIG. 7 and a diagram of the transfer characteristic of the dead band circuit is shown in FIG. 8. With the P-Channel MOSFET Q 1  conducting the current I 3  which is in excess of I 2 max, the current I 3  is determined as:  
         I   3     =           (     -     V   G       )          (     R   11     )           (     R     o                 n                 v       )          (     R   22     )         +       (     -     V   G       )       R   22                               
 
         [0051]    where the MOSFET Q 1  is treated as a variable resistor given by Ronv. In Region  3 , the MOSFET Q 1  resistance is above the minimum achievable Ron resistance value.  
         [0052]    Further increasing I 1  forces MOSFET Q 1  to leave saturation and operate in the linear region of the MOSFET Q 1  where the drain to source resistance of MOSFET Q 1  has dropped to the minimum value, Ron. The incremental increase in Vin is given by:  
         Δ V   in =(Δ I   3 )( R   on   //R   12   //R   11 ).  
         [0053]    Since generally, Ron&lt;&lt;(R 12 //R 11 ) the ΔV in  of the MOSFET Q 1  may be approximated as:  
         Δ V   in ≈(Δ I   3 )( R   on ).  
         [0054]    In Region  3 , amplifier U 3  is operating linearly and Vout (node  42 ) is not clipped.  
         [0055]    The deadband circuit has an incremental gain of 1 (see FIG. 7) when driven beyond a threshold value determined by the forward drop of diodes D 12 , D 13 , D 14  and D 15 . Therefore the slope of the Vout versus I 1  curve in Region  4  of FIG. 6 is:  
         S                 l                 o                 pe     ≈     -           (     R   22     )          (     R     o                 n       )         R   11       .                             
 
         [0056]    As I 1  and Vin continue to increase, amplifier U 3  output voltage Vout increases negatively to maintain linear operation. However, the maximum negative output voltage of amplifier U 3  is limited by supply voltage VS 2 . In FIG. 6, the transition of Vout from Region  4  to Region  5  occurs at a point where amplifier U 3  saturates and ultimately limits Vout. The slope of the Vin verses I 1  curve in Region  5  is given by:  
           R   on   //R   12 //( R   11   +R   22 )≈ R   on .  
         [0057]    which equation is valid as long as I 1  is less than I 1 max and the MOSFET Q 1  resistance remains at Ron. Both I 1 max and the saturation region are shown in FIG. 6. Input currents in excess of I 1 max will drive the MOSFET Q 1  into the saturation region, with a corresponding rapid increase of Vin at node  41 . Proper selection of Q 1  will prevent operation in this non-preferred region. As I 1  decreases, operation of the circuit will progress through the regions discussed in the reverse sequence of the order discussed above.  
         [0058]    Referring now to FIG. 4, a bipolar multiple range current measuring system is illustrated. The bipolar measuring system shown in FIG. 4 is similar to the unipolar measurement system shown in FIG. 3. The bipolar measuring system shown in FIG. 4 additionally comprises an N channel MOSFET Q 2  and diodes D 16 , D 17 , D 18 , and D 19 , resistors R 31  and R 32 . Diodes D 12 , D 13 , D 14 , D 15 , D 16 , D 17 , D 18  and D 19 , resistors R 18 , R 19 , R 31  and R 32  comprise a bipolar deadband circuit  50 . The arrangement of the deadband circuit and the interconnections thereof with VS!, VS 2  and circuit common are shown in FIG. 7. The deadband circuit  50  is connected into the circuits of FIGS. 4 and 9 according to the designations A and B shown in FIGS. 4, 7 and  9 . Diodes D 16 , D 17 , D 18  and D 19 , resistors R 31  and R 32  and MOSFET Q 2  allow the measurement systems of FIGS. 4 and 9 to operate with current I 1  flowing in either the positive (as shown) or the negative direction (opposite that shown). Where the direction of current I 1  is negative, the voltage ImonL, and the potential at node  42  (Vout), with respect to common, will be positive. As the current I 1  increases negatively, amplifier U 4  will clip in a positive direction and the potential at node  42  (Vout) will increase in a positive direction. This will cause diodes D 16 , D 17 , D 18 , and D 19  to conduct and apply an increasingly positive voltage to the gate of MOSFET Q 2 , causing MOSFET Q 2  to enter saturation. Further increasing the value of I 11  in the negative direction will cause the circuit to analogously follow the same sequence of events discussed in relation to FIG. 3. It will be readily understood that the voltage plots of FIG. 6 and the discussion regarding FIG. 3 analogously apply to negative currents, by simply reversing the polarities shown on FIG. 6 for each of +Volts, −Volts and I 1 .  
         [0059]    The present embodiment overcomes each of the problem areas of the series and parallel shunt measurement systems. In the prior art, the insertion impedance of the measurement system is often high and changes drastically as various shunts are switched on and off. This can disturb the external current flow due to changes in the impedance of the measuring circuit. The present system minimizes the insertion impedance RDC of the measurement circuit at all frequencies and modes of operation by dividing the shunt impedance R 12  according to the equation:  
           R     D                 C       =         R   12       1   +       (   A1   )          (   A2   )           +     R   H         ,                         
 
         [0060]    where A 1  is the closed loop gain of the amplifier U 4  and A 2  is the open loop DC gain of the amplifier U 3 , and by using low R on  MOSFETS for higher currents in Regions  2 ,  3 ,  4 , and  5 . The low Ron MOSFETS also not only reduce power dissipation but also reduce the common mode voltage applied between amplifier U 2  input and common, which reduces measurement errors in the ImonH circuit. Using the nulling circuit shown in FIG. 5, zero volts can be maintained across the bypass MOSFETS Q 1  and Q 2  to prevent leakage current from flowing. The present invention greatly improves DC measurement accuracy compared with a conventional differential amplifier and shunt configuration.  
         [0061]    The concepts of this invention may be extended to allow for an arbitrary number of current measurement ranges. FIG. 9 is a schematic diagram which illustrates how the circuits of FIG. 3 and FIG. 4 are altered for measurements in an additional mid current range. To accomplish this switches S 1  and S 2  are added to direct the current to flow through an appropriate feedback resistor and compensation nertwork. The measurement voltage ImonM or ImonL is taken in a manner to avoid a measurement error due to the resistance of the respective switch. Capacitor C 15  and resistors R 34  and R 35  perform similar functions as capacitor C 12  and resistors R 12  and R 13 , respectively, perform in the measurement system discussed with reference to FIGS. 3 and 4. Otherwise the circuit of FIG. 9 operates in a similar manner as the circuit of FIG. 4.  
         [0062]    Switches S 1  and S 2  are activated by suitable means such as for example, user selection to select one of ImonM and ImonL as a desired range. Switches S 1  and S 2  should be operated in a make-before-break fashion to provide for minimum disruption. As in the embodiments shown in FIGS. 3 and 4, the shunts cannot be over powered because excessive current is automatically shunted away from the high value measurement resistors by the bypass transistors Q 1  and Q 2 .  
         [0063]    In summary, the prior art parallel shunt circuit of FIG. 1 requires complex switch control of the measurement shunts in order to perform the make-before-break switching operation, which does not occur automatically. This can result in disruption of external current flow and in the measurement shunts being momentarily overpowered. The prior art series shunt circuit of FIG. 2 has the disadvantages of power dissipation and leakage in the shunt regulator SR 1  or problems with the control and lifetime of switch SL if the shunt regulator SR 1  is not used. In the present invention measurement range changes occur automatically without the use of mechanical relays to change measurement shunts. Elimination of mechanical relays alleviates concerns regarding contact bounce and contact lifetime.  
         [0064]    In the present invention, excess current is automatically shunted away from lower range measurement components via the bypass MOSFETS. As the measurement current increases, the lower range measurements will clip in a manner which does not affect measurement accuracy or cause harm to the circuit  
         [0065]    Although preferred embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principle and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.