Abstract:
In a CMOS logic circuit destined to function at a relatively high supply voltage such as to require the formation of graded diffusions in the structure of N-MOS transistors, a NAND configuration is used which comprises a staked pair of N-MOS transistors. This permits to restrict the number of graded diffusions to be formed in N-MOS structures only to the drain regions which are directly connected to an output node. In clocked CMOS circuitry where transfer transistors are normally used between gates, the advantages in terms of enhanced speed and ability of the circuit to be compacted by cutting the number of N-MOS structures necessarily provided with drain extension regions as in prior art circuits, are remarkable.

Description:
TECHNICAL FIELD 
     The present invention relates to CMOS logic circuits and, more particularly, to a way to solve the problems of protecting N-MOS transistors from aging and/or failure caused by the phenomenon of impact ionization which occurs under particular conditions of operation at relatively high voltage in CMOS logic gates. 
     BACKGROUND OF THE INVENTION 
     The mechanism of the aging and/or failure of N-MOS transistors caused by the phenomenon of impact ionization taking place under particular bias conditions of the gate of the transistor versus its source while the drain is biased at a relatively high voltage in respect to the source potential, is well known and debated in literature. 
     This problem occurs every time a N-MOS transistor having its drain biased at the supply voltage by a preceding switching on of the P-MOS transistor portion of a CMOS inverter, switches on as a consequence of a raising of the gate voltage. The flow of electrons crossing the channel region of the transistor is accelerated by a synergistic combination of electric fields due to the &#34;summing&#34; of the effects of the V GS  and V DS  voltages. This causes additional carriers to be driven to the drain coming from electron-hole pairs generated by the impact of high kinetic energy electrons with orbitant electrons of the atoms of the crystal lattice in the drain region. This mechanism generates an additional current known as &#34;substrate current&#34; which adds to the drain-source current. This additional current is highly dangerous because even if a low level (in the order of few |A) may produce locally a direct biasing of the substrate in respect to the source region of the transistor, thus triggering on a parasitic bipolar transistor in parallel to the real N-MOS. The V DS  voltage to which this parasitic bipolar transistor switches on is known in literature as the snap-back voltage. This phenomenon may be destructive for the metallic connections (contacts) of the N-MOS, which must convey a far augmented current than the design current. Even where complete failure is avoided, the mechanism at the base of the snap-back phenomenon is such as to cause in time a degradation of the electrical characteristics of the N-MOS transistor. This degradation (aging) due to the presence of high energy electrons in the channel, is cumulative in time, thus producing a progressive loss of functionality of the N-MOS transistors which is even more feared than an instantaneous failure, because the &#34;microscopic&#34; behavior of the integrated circuit varies with time due to the alterations which have occurred at the level of single N-MOS devices, the threshold voltage (V th ) and transconductance (gm) of which tend to subtly change with time. 
     It is known that impact ionization and its negative effects may be countered by forming graded drain diffusions (known also as drain extensions). These graded drain diffusions may be obtained by forming a second diffused region having a lower dopant concentration than that commonly used for the drain region proper. The use of drain extensions results in increasing the V DS  voltage to which the snap-back phenomenon takes place and reducing the aging process caused by impact ionization, by creating, during the switching on the N-MOS transistor, an electric field of reduced intensity near the drain region of the transistor by virtue of the graded diffusion. Frequently in certain circuit applications, it is necessary for the same prevention reasons, to also form the source diffusion in a similarly graded manner, i.e., provide the N-MOS transistor with &#34;bilateral&#34; (drain) extensions. 
     The raising of the snap-back voltage causes a reduction of the electrical performance of the N-MOS transistor that is provided with drain extensions, in terms of reduced speed and increased ON-resistance. 
     Moreover, under the aspect of the fabrication technology of these devices, the necessary use of a dedicated &#34;drain extension&#34; mask, beside complicating the fabrication process, makes the N-MOS transistors more cumbersome in terms of layout and more sensitive to misalignment problems and therefore more difficult to be reduced in size through compacting technologies, also known as &#34;shrinkage processes,&#34; toward which any circuit evolves in time for exploiting the improvements that the photolithographic techniques and apparatuses constantly go through. 
     Thus, while using drain and source extensions solve some problems, it creates new problems, including reduced speed performance and increased power requirement. 
     All the above-mentioned problems are most frequently encountered in mixed analog-digital integrated CMOS circuits, wherein two different supply voltages are normally present: a low supply voltage (5 V) for the internal logic circuitry which interfaces with the analog portions of the integrated circuit operating at such a higher supply voltage in order to ensure a large dynamic voltage swing. 
     The logic circuits operating at high supply voltage are therefore potentially sensitive to said snap-back problems constitute parts of the integrated circuit which, because of the large use of graded junctions, raise remarkable problems of increased criticality when attempting a compacting of the integrated circuit for exploiting at best improved fabrication techniques which may have become available. 
     Therefore, there is a need of logic circuits, i.e., for CMOS logic gates, capable of operating at a relatively high supply voltage and wherein the need of forming graded diffusions in the structure of N-MOS transistors be minimized in order to maintain characteristics of high speed for the propagation of data through the logic gates and ensuring a low internal ON-resistance of the same transistors. 
     The present invention provides an effective solution to this specific technical problem. 
     SUMMARY OF THE INVENTION 
     According to the present invention, a CMOS logic gate, i.e., any CMOS logic circuit, which is designed to operate at a high supply voltage, include two stacked (i.e., connected in electrical series) N-MOS transistors and only the N-MOS transistor whose drain is connected to an output terminal of the logic gate is provided with a graded diffusion, solely in the drain region thereof. 
     The invention is particularly helpful in circuits whose supply voltage is so high as to require the formation of graded diffusions in the structures of N-MOS transistors in order to increase the voltage between source and drain (V DS ) at which the switching on of the intrinsic parasitic bipolar transistor in parallel to each real N-MOS transistor takes place. 
     By employing NAND configured logic gates which comprise two stacked N-MOS transistors and taking advantage of the attendant substrate (body) effect, it is possible to build a circuit which uses graded diffusions only in the N-MOS transistor whose drain is connected to an output terminal of the logic gate and limited to the drain region of one transistor, i.e., making the respective source diffusion and all other diffusions in a normal manner without grading them. 
     Using the structure of the present invention, the speed of propagation of data through the logic gate is not appreciably reduced because there is only a single graded junction of the drain region of the N-MOS transistor and the whole logic circuit may be more easily compacted through so-called &#34;shrinkage techniques&#34; exploiting advanced fabrication processes. 
     The present invention takes advantage of the substrate or body effect of an N-MOS transistor whose source is not connected to the substrate to provide a new structure having numerous advantages not possible with the prior art. 
     The different aspects and advantages of the invention will become more evident through the following description of several embodiments and reference to the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a common CMOS inverter circuit with a transfer device made according to a known prior art technique. 
     FIG. 2 is a schematic functional illustration of an N-MOS transistor illustrating the function of the present invention. 
     FIG. 3 is a schematic functional illustration of a NAND configured gate comprising two stacked N-MOS transistors illustrating the function of the present invention. 
     FIG. 4 shows a functionally equivalent circuit of the inverter with a transfer device of FIG. 1 except made according to the present invention and thus having significant advantages over the prior art of FIG. 1. 
     FIG. 5 is a cross-sectional view of the input transistors of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In FIG. 1, a typical inverter circuit with transfer transistor, which is widely used in logic circuits, is shown. The use of an N-MOS transistor as a transfer device requires the formation of graded implantations of both the diffused drain and source junctions because drain and source are substantially interchangeable in the charging/discharging processes of the output/input capacitances. In the circuit of FIG. 1, the junctions requiring graded diffusions for enabling the circuit to work at a relatively high supply voltage (V CC ), are identified by the letters DE. The strong penalization on the transfer speed characteristics of the circuit due to the large number of graded junctions is evident. 
     The technical solution provided by the present invention as an alternative to a burdensome use of grated diffusions in the structure of N-MOS transistors for countering the aging mechanism thereof, has a great utility especially in the case of logic circuits employing shift registers and more in general in logic circuits wherein the output is sampled by means of a transfer transistor. 
     FIG. 4 illustrates a circuit according to the present invention, which is functionally equivalent to the circuit of FIG. 3 but it may be realized by employing a NAND configuration which comprises two stacked N-MOS transistors, N1 and N2, respectively, for the first inverter and N3 and N4, respectively, for the second inverter, while forming a graded diffusion only in the drain region which is connected to the output of the respective inverter, of the two pairs of N-MOS transistors, i.e., N1 and N3. 
     The operation of the invention and how the body effect of the substrate is advantageously used will now be explained with respect to FIGS. 2 and 3. It is known that the ability of a MOS transistor to transfer a signal is tied to its threshold voltage. The latter is in turn a function of the substrate voltage with respect to the source voltage. By referring to a functional illustration of a N-MOS transistor shown in FIG. 2, the threshold voltage of the transistor is given by: ##EQU1## where: φ F  =Fermi&#39;s potential, V tho  =the extrapolated threshold in the linear region of the characteristic curve, and K BE  =√2q e  ε Si  N B  /C ox   
     where: 
     E Si  is the dielectric constant; N B  is the dopant concentration in number of dopant atoms per cm 3  in the substrate; C OX  is the capacitance of the sandwich formed by the polycrystalline silicon gate/the silicon dioxide gate isolation layer/the semiconductor (substrate); V S  is the source voltage; 
     and where V S  =V BS  (i.e., the reverse bias voltage of the substrate, positive in an N-MOS transistor). 
     In practice the following mechanism may be assumed for the two possible states, low or high, respectively: 
     low state (0): the capacitance associated with the drain region of the transistor charges to the voltage V D  which coincides with the supply voltage (V CC ). 
     The gate voltage V GS  =OV, therefore the N-MOS transistor T1 is OFF and the capacitance C2 has no charge (ground). 
     high state (1): the gate voltage V GS  raises in time from OV up to a maximum value: V GS  =V CC . The N-MOS transistor T1 switches on and the capacitance C2 charges to a voltage V s&#39; , the end value of which is a function of the threshold voltage of the N-MOS transistor, according to the following expression: ##EQU2## Therefore it may be said that the ability of the N-MOS transistor to transfer a voltage signal is a function of the bias voltage of the substrate. 
     Vice versa, in a NAND type configuration of two N-MOS transistors connected in series, that is circuitally &#34;stacked&#34; one on top of the other, as depicted in FIG. 3, the voltage V S  (which coincides with the drain voltage of the transistor T2) is reduced in respect to the voltage V S  of the circuit of FIG. 1, by a quantity given by the following expression: ##EQU3## 
     Therefore, when the transistor T2 is forced to commute by the voltage V GS2  passing from 0 V to V CC&#39; , its drain voltage will no longer reach the dangerous level V D  =V CC&#39; , which would otherwise make it necessary to form graded junctions (i.e. drain extension regions), vice versa because of the voltage level reaction due to the body effect, the transistor T2 may be designed without graded junctions. 
     In other words, the source of transistor T 1  is not connected to the substrate voltage. This creates a substrate effect, sometimes called body effect, so that the drain of transistor T 2  will not reach the dangerously high voltage and need not have a graded drain diffusion. Thus, the body effect which is considered a problem in some circuits is advantageously used to provide a circuit with a reduced number of graded junctions, as will now be described in more detail. 
     The circuit of FIG. 4, made according to the present invention, requires that only two N-MOS transistors have a single graded drain junction. By contrast, the circuit of FIG. 1, according to the prior art, required two N-MOS transistors provided with bilateral graded junctions (both source and drain regions) and two N-MOS transistors provided with at least a graded drain junction. The advantages in terms of enhanced performance and ability to be more easily compacted of the circuit made in accordance with the present invention compared with the equivalent circuit according to the prior art are evident. 
     As shown in FIG. 5, the first set of transistors P1, P2, N1 and N2 are shown in silicon cross-section. The drain 10 of the first transistor P1 is coupled to VCC, as is the N-well 24. (As will be appreciated by those of skill in the art, the substrate 28 could be N-type with only a P-well 26 formed, or alternatively, it could be P-type with only an N-well 24 formed.) The source of P1 and drain of P2 are a common diffusion 12. The source of P2 is electrically coupled to the drain 16 of N1, thus possibly subjecting this drain 16 to a high voltage. The transistor N1 is thus provided with a lightly doped drain 18, or graded drain extension 18. The source of N1 and drain on N2 are in a common diffusion 20, which diffusion 20 is not electrically connected to the substrate (the P-well 26 in this example). The P-well 26 is grounded and is thus at a different voltage than the source/drain diffusion 20. As previously explained and shown by the equations, the body effect on transistor N1 will reduce the voltage that is applied to the drain of transistor N2, thereby making it possible to not use either a graded drain on N2 or a graded source diffusion on N1. The source of N2 is coupled to ground as in the substrate, P-well 26. The clock and its complement are coupled to the gates of N1 and P2, respectively. The input is applied to the gates P1 and N1 and the output is taken from the electrical connection between the source of P2 and the drain of N1. 
     The present invention is useful both for designing logic circuits destined to operate at a relatively high supply voltage integrated in a P-type substrate (P-well) as well as in circuits integrated in an N-type substrate (N-well). In fact, in both cases, the logic circuit realized in accordance with the present invention offers advantages both in terms of reduced area requirement, speed, and may be easily compacted.