Abstract:
A refresh control circuit and method generates a refresh signal in response to one of a plurality of clock signals and a temperature signal. The clock signals and temperature signal may be synchronized to prevent an incomplete refresh operation at a trip point of a temperature sensor. In one embodiment, a pulse generator may generate a temperature sensor enable signal in response to the clock signals when the clock signals are synchronized. In other embodiments, the temperature signal may be latched to prevent a transition in the refresh signal during a refresh operation. The temperature signal may be latched in response to one of the clock signals or the refresh signal.

Description:
[0001]     This application claims priority from Korean Patent Application No. 10-2005-0115887, filed on Nov. 30, 2005, in the Korean Intellectual Property Office, which is incorporated by reference.  
       BACKGROUND  
       [0002]     1. Field of Invention  
         [0003]     The inventive principles of this patent disclosure relate to a semiconductor memory device, and more particularly, to a circuit and method to provide stable refresh control at the trip point of a temperature sensor.  
         [0004]     2. Description of the Related Art  
         [0005]     Semiconductor devices have operational characteristics that vary with changes in temperature. Typical operational characteristics of semiconductor devices include current consumption and operating speed. As the temperature increases, the operating speed decreases. As the temperature decreases, current consumption increases.  
         [0006]     These temperature characteristics are of great importance to volatile memory devices such as dynamic random access memories (DRAMs). Since DRAM cells experience increasing leakage current as temperature rises, data maintenance characteristics deteriorate due to charge loss, which reduces data maintenance time. Therefore, DRAMs require faster refresh operations at temperature increases.  
         [0007]     Developments in electronic technologies have enabled portable electronic devices such as beepers, cellular phones, MP 3  players, calculators, laptop computers, personal digital assistants (PDAs), etc., to be designed and manufactured cost-effectively. These portable electronic devices require direct current (DC) power which is supplied by at least one battery as an energy source.  
         [0008]     It is most important that battery operated systems minimize power consumption. To this end, many devices have a sleep mode for saving power in which circuit components embedded in the battery operated systems are turned off. However, DRAMs embedded in battery operated systems must periodically refresh data stored in DRAM cells in order to continuously maintain the DRAM cell data.  
         [0009]     The refresh period for a DRAM must be changed depending on temperature to reduce power consumption. For example, at lower temperatures where the current consumption increases, the refresh period is increased to reduce the relative number refresh operations so as to reduce the power consumption of the DRAM.  
         [0010]      FIG. 1  is a block diagram of a conventional refresh control circuit  100 . Referring to  FIG. 1 , the refresh control circuit  100  comprises a counter  110 , a pulse generator  120 , a temperature sensor  130 , a refresh master block  140 , and a wordline enable unit  150 .  
         [0011]     The counter  110  receives an oscillator clock signal (OSC) and generates a plurality of clock signals Q 0 , Q 1 , Q 2 , . . . Q n . The counter  110  will now be in detail described with reference to  FIG. 2 .  
         [0012]      FIG. 2  is a block diagram of the counter  110  illustrated in  FIG. 1 . Referring to  FIG. 2 , the counter  110  comprises a plurality of serially connected divider circuits  201 ,  202 ,  203 ,  204 , and  205 . The first divider circuit CNT 0  divides the OSC and generates the first clock signal Q 0 . The second divider circuit CNT 1  divides the first clock signal Q 0  and generates the second clock signal Q 1 . The third divider circuit CNT 2  divides the second clock signal Q 1  and generates the third clock signal Q 2 . The n+1 st  divider circuit CNTn divides the n th  clock signal Q n−1  and generates the n+1 st  clock signal Q n . The n+1 st  clock signal Q n  has the longest clock period.  
         [0013]      FIG. 3  is a circuit diagram of the pulse generator  120  illustrated in  FIG. 1 . Referring to  FIG. 3 , the pulse generator  120  comprises a delay unit  310  that receives the n+1 st  clock signal Q n  of the counter  110  and delays the n+1 st  clock signal Q n , a NAND gate  320  that receives an output of the delay unit  310  and the n+1 st  clock signal Q n , and first and second inverters  330  and  340  that receive an output of the NAND gate  320  and generates a temperature sensor enable signal PTENB. The first and second inverters  330  and  340  form a buffer. The temperature sensor enable signal PTENB is a pulse signal having a logic low section corresponding to a delayed time of the delay unit  310 .  
         [0014]     The temperature sensor  130  senses a present temperature of a DRAM chip in response to the temperature sensor enable signal PTENB. The temperature sensor  130  can have a plurality of trip points. For example, the temperature sensor  130  has two trip points and generates first and second temperature signals T 45  and T 85  according to the sensed temperature. The first temperature signal T 45  is logic high when the sensed temperature is above 45° C., and is logic low when the sensed temperature is below 45° C. The second temperature signal T 85  is logic high when the sensed temperature is above 85° C., and is logic low when the sensed temperature is below 85° C.  
         [0015]     The refresh master block  140  selects one of the clock signals Q 0 , Q 1 , Q 2 , . . . Q n  generated by the counter  110  in response to PTENB and the first and second temperature signals T 45  and T 85 . The refresh master block  140  generates a refresh control signal SRFHP according to the selected clock signal, and generates a refresh signal PREF in response to the refresh control signal SRFHP. The wordline enable unit  150  enables wordlines (not shown) of memory cells in response to the refresh signal PREF.  
         [0016]     The refresh control circuit  100  changes the frequency of refresh operations in response to the temperature of the surrounding DRAM chip based on the trip point of the temperature sensor  130 .  FIG. 4  illustrates a section of the temperature range in which erroneous refresh operations tend to occur. Referring to  FIG. 4 , an erroneous refresh operation section is around 45° C. An erroneous refresh operation will now be described in detail with reference to  FIG. 5 .  FIG. 5  is a timing diagram of the operation of the reference period control circuit  100 .  
         [0017]     Referring to  FIG. 5 , a Q i  clock signal, a Q j  clock signal, and a Q n  clock signal are shown among the clock signals Q 0 , Q 1 , Q 2 , . . . Q n . The Q i  clock signal is selected according to an initially sensed chip temperature. The refresh control signal SRFHP is generated according to the Q i  clock signal ({circle around (1)}). The refresh signal PREF having a logic high pulse is generated in response to a falling edge of the refresh control signal SRFHP ({circle around (2)}).  
         [0018]     The temperature sensor enable signal PTENB is logic low in response to a rising edge of the Q n  clock signal having the longest clock period ({circle around (3)}). The temperature sensor  130  is operated to sense a present temperature of the DRAM chip during a time when the temperature sensor enable signal PTENB is logic low.  
         [0019]     When the temperature sensor enable signal PTENB changes from logic low to logic high ({circle around (4)}), the temperature sensor  130  selects the Q j  clock signal according to the changed temperature. At this time, when a logic level of the presently selected Q j  clock signal is different from that of the previously selected Q i  clock signal, the refresh control signal SRFHP has a logic low level according to the Q i  clock signal ({circle around (5)}), and has a logic high level according to the Q j  clock signal ({circle around (6)}), thereby causing a short logic low pulse. The refresh signal PREF having a short logic high pulse is generated in response to the refresh control signal SRFHP having the short logic low pulse ({circle around (7)}).  
         [0020]     The refresh signal PREF having the short logic high pulse cannot enable wordlines (not shown) and refresh the memory cells connected to the wordlines. Therefore, a refresh operation is not complete, which causes a failure in the wordlines.  
       SUMMARY  
       [0021]     Some of the inventive principles of this patent disclosure relate to a refresh control circuit having logic to synchronize clock signals and a temperature signal to prevent a transition in a refresh signal during a refresh operation. An embodiment may include a counter to generate a plurality of clock signals in response to an oscillator clock signal; a pulse generator to generate a temperature sensor enable signal in response to the clock signals; a temperature sensor to sense a current temperature of a chip and generate a temperature signal in response to the temperature sensor enable signal; a refresh master block to select one of the clock signals in response to the temperature sensor enable signal and the temperature signal, and to generate a refresh signal in response to the selected clock signal; and logic to synchronize the clock signals and temperature signal to prevent a transition in the refresh signal during a refresh operation.  
         [0022]     In one embodiment, the logic may be implemented in the pulse generator to generate the temperature sensor enable signal when the clock signals are synchronized. In another embodiment, the logic may be implemented as a latch circuit to latch and synchronize the temperature signal.  
         [0023]     Some additional inventive principles of this patent disclosure relate to a refresh control circuit including: a counter to generate a plurality of clock signals in response to an oscillator clock signal; a pulse generator to generate a temperature sensor enable signal in response to the clock signals when the clock signals are synchronized; a temperature sensor to sense a current temperature of a chip and generate a temperature signal in response to the temperature sensor enable signal; and a refresh master block to select one of the clock signals in response to the temperature sensor enable signal and the temperature signal, and to generate a refresh signal in response to the selected clock signal.  
         [0024]     The pulse generator may include: a synchronizer to synchronize the clock signals based on a clock signal having the longest period among the clock signals; and a logic unit to generate the temperature sensor enable signal in response to an output of the synchronizer. The synchronizer may include: an inverter to receive the clock signal having the longest period among the clock signals; and a plurality of NAND gates to receive an output of the inverter and at least two of the other clock signals. The logic unit may include: a NOR gate to receive outputs of the NAND gates; and an inverter to outputting the temperature sensor enable pulse in response to an output of the NOR gate.  
         [0025]     Some additional inventive principles of this patent disclosure relate to a refresh control circuit including: a counter to generate a plurality of clock signals in response to an oscillator clock signal; a pulse generator to generate a temperature sensor enable signal having a pulse in response to one of the clock signals; a temperature sensor to sense a current temperature of a chip and generate a temperature signal in response to the temperature sensor enable signal; and a latch circuit to latch and synchronize the temperature signal; and a refresh master block to select one of the clock signals in response to the temperature sensor enable signal and the latched temperature signal, and to generate a refresh signal in response to the selected clock signal.  
         [0026]     The latch circuit may latch and synchronize the temperature signal in response to one of the clock signals. The latch circuit may alternatively latch and synchronize the temperature signal in response to the refresh signal. The latch circuit may latch the temperature signal when the refresh signal is deactivated.  
         [0027]     Some additional inventive principles of this patent disclosure relate to a refresh control method including: generating a plurality of clock signals in response to an oscillator clock signal; generating a temperature signal in response to a current temperature of a chip; generating a refresh signal in response to the plurality of clock signals and the temperature signal; and synchronizing the clock signals and the temperature signal to prevent a glitch that causes an incomplete refresh operation.  
         [0028]     Synchronizing the clock signals and the temperature signal may include: synchronizing the clock signals to generate a temperature sensor enable signal based on a clock signal having the longest period among the clock signals; and generating the temperature signal in response to the temperature sensor enable signal. Synchronizing the clock signals and the temperature signal may include latching the temperature signal in response to one of the clock signals. Synchronizing the clock signals and the temperature signal may include latching the temperature signal in response to the refresh signal.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]      FIG. 1  is a block diagram of a conventional refresh control circuit;  
         [0030]      FIG. 2  is a block diagram of a counter illustrated in  FIG. 1 ;  
         [0031]      FIG. 3  is a circuit diagram of a pulse generator illustrated in  FIG. 1 ;  
         [0032]      FIG. 4  illustrates section of a temperature range where an erroneous refresh operation occurs;  
         [0033]      FIG. 5  is a timing diagram of the operation of a control circuit of  FIG. 1 ;  
         [0034]      FIG. 6  is a block diagram of an embodiment of a refresh control circuit according to some of the inventive principles of this patent disclosure;  
         [0035]      FIG. 7  is a circuit diagram of an embodiment of a pulse generator according to some of the inventive principles of this patent disclosure;  FIG. 8  is a timing diagram illustrating an embodiment of a refresh operation according to some of the inventive principles of this patent disclosure;  
         [0036]      FIG. 9  is a block diagram of another embodiment of a refresh control circuit according to some of the inventive principles of this patent disclosure; and  
         [0037]      FIG. 10  is a block diagram of another embodiment of a refresh control circuit according to some of the inventive principles of this patent disclosure. 
     
    
     DETAILED DESCRIPTION  
       [0038]      FIG. 6  is a block diagram of an embodiment of a refresh control circuit  600  according to some of the inventive principles of this patent disclosure. Referring to  FIG. 6 , the refresh control circuit  600  includes a counter  110 , a pulse generator  620 , a temperature sensor  130 , a refresh master block  140 , and a wordline enable unit  150 . The refresh control circuit  600  is the same as the conventional refresh control circuit  100  illustrated in  FIG. 1  except for the pulse generator  620 . A description of the same constituents will be skipped.  
         [0039]     An embodiment of the pulse generator  620  will now be described with reference to  FIG. 7 . The pulse generator  620  includes a synchronizer  710  that receives the clock signals Q 0 , Q 1 , Q 2 , . . . Q n  of the counter  110 , and a logic unit  720  that generates the temperature sensor enable signal PTENB in response to outputs of the synchronizer  710 .  
         [0040]     The synchronizer  71   0  includes an inverter  712  that receives the n+1 st  clock signal Q n , a first NAND gate  712  that receives the first clock signal Q 0  and the second clock signal Q 1 , a second NAND gate  716  that receives the third clock signal Q 2  and the n−1 st  clock signals Q 2 , Q n−2 , and a third NAND gate  718  that receives the n th  clock signal Q n−1 , and an output of the inverter  712 .  
         [0041]     The logic unit  720  includes a NOR gate  722  that receives outputs of the first, second, and third NAND gates  714 ,  716 , and  718  and an inverter  724  that receives an output of the NOR gate  722  and outputs the temperature sensor enable signal PTENB.  
         [0042]     An operation of the pulse generator  620  will now be described with reference to  FIG. 8 . When the n+1 st  clock signal is logic low, if the first through n th  clock signals Q 0  through Q n−1  are logic high, the temperature sensor enable signal PTFNB is logic low. When the n+1 st  clock signal Q n  is logic high or any one of the first through n th  clock signals Q 0  through Q n−1  is logic low, the temperature sensor enable signal PTENB is logic high.  
         [0043]     The temperature sensor enable signal PTENB is provided to the temperature sensor  130  illustrated in  FIG. 6  to sense the current temperature of the DRAM chip. The temperature sensor  130  senses the current temperature of the DRAM chip in response to the temperature sensor enable signal PTENB in a logic low state and generates the first and second temperature signals T 45  and T 85 .  
         [0044]     The refresh master block  140  illustrated in  FIG. 6  selects one of the clock signals Q 0 , Q 1 , Q 2 , . . . Q n−1  generated by the counter  110  in response to the temperature sensor enable signal PTENB in the logic low state and the first and second temperature signals T 45  and T 85 . The refresh master block  140  generates the refresh control signal SRFHP according to the selected clock signals Q 0 , Q 1 , Q 2 , . . . Q n−1 . Since the selected clock signals Q 0 , Q 1 , Q 2 , . . . Q n−1  are logic high, the logic level of the refresh control signal SRFHP does not change.  
         [0045]     For example, the refresh master block  140  generates the refresh control signal SRFHP according to the i th  clock signal Q i  and an initially sensed chip temperature ({circle around (a)}). The refresh master block  140  senses the chip temperature in response to the temperature sensor enable signal PTENB in the logic low state ({circle around (b)}), and selects the j th  clock signal Q j  according to a change in the chip temperature. Since the i th  clock signal Q i  and the j th  clock signal Q j  have the same logic level (i.e., logic high), the refresh master block  140  generates the refresh control signal SRFHP according to the j th  clock signal Q j  without a glitch in the logic low level ({circle around (c)}). The refresh master block  140  generates the refresh control signal SRFHP having a logic high pulse in response to the falling edge of the refresh control signal SRFHP ({circle around (d)}).  
         [0046]     Therefore, since the refresh control circuit  600  senses the chip temperature when the plurality of clock signals Q 0 , Q 1 , Q 2 , . . . Q n−1  are synchronized and selects one of the clock signals Q 0 , Q 1 , Q 2 , . . . Q n−1 , the refresh master block  140  generates the refresh control signal SRFHP and the refresh signal PREF without a glitch and sufficiently refreshes the memory cells connected to the corresponding wordlines.  
         [0047]      FIG. 9  is a block diagram of another embodiment of a refresh control circuit  900  according to some of the inventive principles of this patent disclosure. Referring to  FIG. 9 , the refresh control circuit  900  includes a counter  110 , a latch circuit  935 , a pulse generator  120 , the temperature sensor  130 , a refresh master block  140 , and a wordline enable unit  150 . The refresh control circuit  900  is the same as the conventional refresh control circuit  100  illustrated in  FIG. 1  except for the latch circuit  935 . A description of the same constituents will be skipped.  
         [0048]     The latch circuit  935  synchronizes the first and second temperature signals T 45  and T 85  generated by the temperature sensor  130  in response to a k th  clock signal Q k  generated by the counter  110 . The latch circuit  935  latches the first and second temperature signals T 45  and T 85  in response to the k th  clock signal Q k  and transfers the latched first and second temperature signals T 45 ′ and T 85 ′ to the refresh master block  140 .  
         [0049]     The refresh master block  140  selects one of the clock signals Q 0 , Q 1 , Q 2 , . . . Q n−1  generated by the counter  110  in response to the latched first and second temperature signals T 45 ′ and T 85 ′ and the temperature sensor enable signal PTENB. Since the refresh master block  140  selects one of the clock signals Q 0 , Q 1 , Q 2 , . . . Q n−1  using the first and second temperature signals T 45 ′ and T 85 ′ which are synchronized and latched to the k th  clock signal Q k , the refresh master block  140  generates the refresh control signal SRFHP according to the selected clock signals Q 0 , Q 1 , Q 2 , . . . Q n−1  without a glitch.  
         [0050]      FIG. 10  is a block diagram of another embodiment of a refresh control circuit according to some of the inventive principles of this patent disclosure. Referring to  FIG. 10 , the refresh control circuit  1000  includes the counter  110 , a latch circuit  1035 , a pulse generator  120 , a temperature sensor  130 , a refresh master block  140 , and a wordline enable unit  150 . In comparison with the refresh control circuit  900  illustrated in  FIG. 9 , the latch circuit  1035  synchronizes the first and second temperature signals T 45  and T 85  generated by the temperature sensor  130  in response to the refresh signal PREF. The latch circuit  1035  latches the first and second temperature signals T 45  and T 85  in response to an inactivation of the refresh signal PREF and transfers the latched first and second temperature signals T 45 ′ and T 85 ′ to the refresh master block  140 .  
         [0051]     The refresh master block  140  does not receive the first and second temperature signals T 45  and T 85  generated by the temperature sensor  13  during a refresh operation according to an activation of the refresh control PREF. Therefore, the refresh master block  140  is not affected by a change in the temperature sensed by the temperature sensor  130  but stably generates the refresh control signal SRFHP.  
         [0052]     In the embodiment of  FIG. 10 , although the temperature signals are described as being latched in response to PREF, they may also be described as being latched in response to one of the clock signals, since the refresh signal PREF is based on SRFHP which is essentially a selected one of the clock signals. Thus, the temperature signal latching operation is synchronized to the clock signals, and transitions in the refresh signal PREF are synchronized to the clock signals to prevent transitions that interfere with a refresh operation.  
         [0053]     While the inventive principles of this patent disclosure have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the inventive principles as defined by the following claims.