Abstract:
A DC converter has a transformer with loosely coupled primary and secondary windings, a main switch connected in series with the primary winding of the transformer, and a series circuit connected to ends of one of the primary winding and main switch. The series circuit includes a clamp capacitor and an auxiliary switch. The main and auxiliary switches are alternately turned on/off so that a voltage of the secondary winding of the transformer is synchronously rectified with synchronous rectifiers and is smoothed with smoothing elements, to provide a DC output. The DC converter also includes a tertiary winding tightly coupled with the primary winding of the transformer, a voltage source to supply a voltage lower than a voltage generated by the tertiary winding of the transformer, and clamp diodes to clamp the voltage generated by the tertiary winding with the use of the voltage source. The clamp diodes provide voltage-clamped signals to drive the synchronous rectifiers.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a highly efficient DC (direct current) converter.  
         [0003]     2. Description of the Related Art  
         [0004]      FIG. 1  is a circuit diagram showing a DC converter according to a related art. The DC converter shown in  FIG. 1  is a forward converter provided with active clamps. The DC converter includes a DC power source Vin and a main switch Q 1  such as a MOSFET (field effect transistor) connected to the DC power source Vin through a primary winding P 1  (having the number of turns of n 1 ) of a transformer Ta.  
         [0005]     Ends of the primary winding P 1  are connected Tao series circuit that consists of an auxiliary switch Q 2  such as a MOSFET and a clamp capacitor C 2 . The series circuit consisting of the switch Q 2  and clamp capacitor C 2  forms an active clamp circuit, which may be connected in parallel with the switch Q 1 .  
         [0006]     A diode D 1  is connected between the drain and source of the switch Q 1 , and a diode D 2  is connected between the drain and source of the switch Q 2 . The diodes D 1  and D 2  may be parasitic diodes of the switches Q 1  and Q 2  if the switches Q 1  and Q 2  are MOSFETs containing the parasitic diodes. A capacitor C 3  is a voltage resonance capacitor and is connected between the drain and source of the switch Q 1 . The capacitor C 3  may be a parasitic capacitance of the switch Q 1 .  
         [0007]     The switches Q 1  and Q 2  have a dead time during which they are both turned off by a control circuit  11 . The control circuit  11  conducts PWM control to alternately turn on/off the switches Q 1  and Q 2 .  
         [0008]     The primary winding P 1  and a secondary winding S 1  (having the number of turns of n 2 ) of the transformer Ta are wound to generate in-phase voltages. In  FIG. 1 , a filled circle represents a winding start of each of the primary winding P 1  and secondary winding S 1  of the transformer Ta.  
         [0009]     A leakage inductance LS is produced between the primary winding P 1  and the secondary winding S 1  of the transformer Ta. Through the leakage inductance LS, a first end of the secondary winding S 1  is connected to the cathode of a diode D 10 . A second end (indicated with the filled circle) of the secondary winding S 1  is connected to the cathode of a diode D 11 . The anode of the diode D 11  is connected to the anode of the diode D 10 .  
         [0010]     The ends of the diode D 10  are connected to the drain and source of a switch Q 10 , which may be a MOSFET serving as a synchronous rectifier for rectification. The ends of the diode D 1  are connected to the drain and source of a switch Q 11 , which may be a MOSFET serving as a synchronous rectifier for current circulation. The gate of the switch Q 10  is connected to the second end (indicated with the filled circle) of the secondary winding S 1 . The gate of the switch Q 11  is connected through the leakage inductance LS to the first end of the secondary winding S.  
         [0011]     The diodes D 10  and D 11  may be parasitic diodes of the switches Q 10  and Q 11  if the switches Q 10  and Q 11  are MOSFETs containing the parasitic diodes. The elements D 10 , D 11 , Q 10 , and Q 11  form a synchronous rectifying circuit. The synchronous rectifying circuit rectifies voltage (on/off-controlled pulse voltage), which is generated by the secondary winding S 1  of the transformer Ta in synchronization with on/off operation of the switch Q 1 , and outputs the rectified voltage.  
         [0012]     The ends of the diode D 10  are connected to a series circuit including a resistor R 20  and a capacitor C 20 . The ends of the diodes D 11  are connected to a series circuit including a resistor R 21  and a capacitor C 21 . These two series circuits are CR snubber circuits to attenuate surge voltage during recovery of the diodes D 10  and D 11 .  
         [0013]     The ends of the switch Q 11  are connected in series with a smoothing reactor L 1  (corresponding to a smoothing element) and a smoothing capacitor C 10  (corresponding to a smoothing element), to form a smoothing circuit. The smoothing circuit smoothes the rectified output of the synchronous rectifying circuit and provides a DC output to a load  50 .  
         [0014]     Based on an output voltage of the load  50 , the control circuit  11  generates a pulse control signal to turn on/off the switches Q 1  and Q 2 , and at the same time, controls the duty factor of the control signal so as to bring the output voltage to a predetermined value.  
         [0015]     The DC converter also includes a low-side driver  13  and a high-side driver  15 . The low-side driver  13  applies a gate signal Q 1   g  from the control circuit  11  to the gate of the switch Q 1 , to thereby drive the switch Q 1 . The high-side driver  15  applies a gate signal Q 2   g  from the control circuit  11  to the gate of the switch Q 2 , to thereby drive the switch Q 2 .  
         [0016]     Operation of the DC converter of the above-mentioned configuration will be explained with reference to a timing chart of  FIG. 2 . In  FIG. 2 , Q 1   g  is a gate signal to the switch Q 1 , Q 2   g  a gate signal to the switch Q 2 , Q 1   v  a drain-source voltage of the switch Q 1 , Q 1   i  a drain current of the switch Q 1 , Q 2   i  a drain current of the switch Q 2 , C 3   i  a current tote capacitor C 3 , Q 10   v  a drain-source voltage of the switch Q 10 , D 10   i  a current to the diode D 10 , Q 10   i  a drain current of the switch Q 10 , Q 11   v  a drain-source voltage of the switch Q 11 , D 11   i  a current to the diode D 11 , and Q 11   i  a drain current of the switch Q 11 .  
         [0017]     Before t0, the switch Q 1  is OFF and the switch Q 2  ON. On the primary side of the transformer Ta, a current passes through a path along Q 2 , P 1 , C 2 , and Q 2 . The primary winding P 1  of the transformer Ta receives a voltage VC 2  from the clamp capacitor C 2 , and the potential of the winding end of the primary winding P 1  is positive. Accordingly, a terminal voltage of the secondary winding S 1  is expressed by VC 2 ·(n 2 /n 1 ) and the potential of the winding end of the secondary winding S 1  is positive.  
         [0018]     As a result, the voltage Q 10   v  of the switch Q 10  is equal to VC 2 ·(n 2 /n 1 ) and the gate voltage of the switch Q 11  is expressed by VC 2 ·(n 2 /n 1 ) and is positive. This turns on the switch Q 11 . On the secondary side of the transformer Ta, a current passes through a route of L 1 , C 10 , Q 11 , and L 1 . The voltage Q 11   v  is substantially zero and the switch Q 10  is OFF.  
         [0019]     At t 0  of period T 1 , the switch Q 2  changes from ON to OFF and the current passing through the path along Q 2 , P 1 , C 2 , and Q 2  becomes zero. Instead, a current passes through a path along P 1 , Vin, C 3 , and P 1 , to discharge the capacitor C 3  and drop the voltage Q 1   v  of the switch Q 1 . When the voltage Q 1   v  drops, the terminal voltage of the primary winding P 1  decreases to decrease the terminal voltage of the secondary winding S 1 . This results in decreasing the voltage Q 10   v  of the switch Q 10 .  
         [0020]     At t 1  of period T 2 , the voltage Q 10   v  of the switch Q 10  decreases to a gate threshold voltage Vth 11  of the switch Q 11 , to turn off the switch Q 11 . The current Q 11   i  of the switch Q 11  becomes zero, and the current to the switch Q 11  starts to pass through the diode D 11 .  
         [0021]     At t 2  of period T 3 , the voltage Q 1   v  of the switch Q 1  reaches the voltage of the DC power source Vin. The terminal voltage of the primary winding P 1  becomes zero, and therefore, the terminal voltage of the secondary winding S 1  becomes zero. This drops the voltage Q 10   v  of the switch Q 10  to zero. The voltage Q 1   v  of the switch Q 1  further decreases to apply positive potential to the winding start of the primary winding P 1 , and therefore, positive potential is applied to the winding start of the secondary winding S 1 . At t 3 , the voltage Q 1   v  of the switch Q 1  becomes zero. Then, the terminal voltage of the primary winding P 1  becomes Vin and the terminal voltage of the secondary winding S 1  becomes Vin·(n 2 /n 1 ). In the period T 3 , the terminal voltage of the primary winding P 1  changes from zero to Vin with the winding start of the primary winding P 1  being positive. At this time, the terminal voltage of the secondary winding S 1  changes from zero to Vin·(n 2 /n 1 ) with the winding start of the secondary winding S 1  being positive.  
         [0022]     Accordingly, a current ILS(t) passing through the leakage inductance LS increases as following expression: 
 
 ILS ( t )=( VS 1( t )/ LS )· t    (1), 
 
 where VS 1 (t) is a terminal voltage of the secondary winding S 1 , LS is a leakage inductance value, and t is time. The current passing through the leakage inductance LS is equal to the current of the diode D 10 , and therefore, the current D 10   i  of the diode D 10  increases in the period T 3 . By an increment of the current D 10   i  of the diode D 10 , the current D 11   i  of the diode D 11  decreases. During the period T 3  on the secondary side of the transformer Ta, a current passes through a route of L 1 , C 10 , D 11 , and L 1  and another current passes through a route of L 1 , C 10 , D 10 , LS, S 1 , and L 1 . The latter current increases according to the expression (1), and the former current decreases thereby. 
 
         [0023]     At t 3  of period T 4 , the capacitor C 3  completely discharges, the voltage Q 1   v  of the switch Q 1  becomes zero, the current passing through the path along P 1 , Vin, C 3 , and P 1  changes its direction to a path along P 1 , Vin, D 1  (Q 1 ), and P 1 , and the switch Q 1  turns on in response to the gate signal Q 1   g.    
         [0024]     In the period T 4 , the voltage Q 1   v  of the switch Q 1  is substantially zero and the terminal voltage of the primary winding P 1  is Vin. The terminal voltage VS 1 (t) of the secondary winding S 1 , therefore, is expressed as Vin·(n 2 /n 1 ). The current ILS(t) passing through the leakage inductance LS increases as following expression:  
                     ILS   ⁡     (   t   )       =         (     VS   ⁢           ⁢   1   ⁢       (   t   )     /   LS       )     ·   t     +     ILS   ⁡     (     t   ⁢           ⁢   3     )                       =         (     Vin   ·       (     n   ⁢           ⁢     2   /   n     ⁢           ⁢   1     )     /   LS       )     ·   t     +     ILS   ⁡     (     t   ⁢           ⁢   3     )           ,                 (   2   )             
 
 where ILS(t 3 ) is a current passing through the leakage inductance LS at t 3 . By an increment of the current passing through the leakage inductance LS, the current D 11   i  of the diode D 11  decreases and reaches at t 4  a current passing through the smoothing reactor L 1 . Then, the current ILS(t) becomes equal to the current of the smoothing reactor L 1 , the current D 11   i  of the diode D 11  becomes zero, and the diode D 11  passes a reverse current due to a recovery current of the diode D 11 . The current Q 1   i  of the switch Q 1  is proportional to a current passing through the secondary winding S 1  at the ratio of the numbers of turns. The current Q 1   i  of the switch Q 1 , therefore, increases and reaches at t 4  a value of n 1 /n 2  (the ratio of the numbers of turns) times a current passing through the smoothing reactor L 1 . 
 
         [0025]     At t 4  of period T 5 , the recovery current of the diode D 11  decreases, and the voltage Q 11   v  of the switch Q 11  increases. When the voltage Q 11   v  of the switch Q 11  reaches a gate threshold voltage Vth 10  of the switch Q 10 , the switch Q 10  turns on so that a current passing through the diode D 10  changes its direction to the switch Q 10 . The voltage Q 11   v  of the switch Q 11  oscillates due to the joint capacitance of the leakage inductance LS and diode D 11  and the output capacitance of the switch Q 11 . The oscillation gradually attenuates, and the voltage Q 11   v  of the switch Q 11  settles to be Vin·(n 2 /n 1 ).  
         [0026]     If the voltage Q 11   v  of the switch Q 11  oscillates to cross the gate threshold voltage Vth 10  of the switch Q 10 , the switch Q 10  repeatedly turns on and off to cause chattering as shown in an operational waveform of  FIG. 6  involving large ringing. To suppress such oscillation, the CR snubber circuit consisting of the resistor R 21  and capacitor C 21  may be added. Since the primary winding P 1  and secondary winding S 1  are loosely coupled to increase the leakage inductance LS, the amplitude of the oscillation is large and the frequency thereof is low. This results in increasing a loss of the CR snubber circuit and deteriorating efficacy.  
         [0027]     At t 5  of period T 6 , the gate signal Q 1   g  of the switch Q 1  falls to zero, thereby zeroing the current Q 1   i  of the switch Q 1 . The current passing through the route of Vin, P 1 , Q 1 , and Vin starts to change to a route of Vin, P 1 , C 3 , and Vin, to increase the voltage of the capacitor C 3 . As a result, the voltage Q 1   v  of the switch Q 1  increases and the voltage Q 11   v  of the switch Q 11  decreases.  
         [0028]     At t 6  of period T 7 , the voltage Q 11   v  of the switch Q 11  decreases to the gate threshold voltage Vth 10  of the switch Q 10 . The switch Q 10  turns off to zero the current Q 10   i  of the switch Q 10 , and the current passing through the switch Q 10  changes its direction to the diode D 10 .  
         [0029]     At t 7  of period T 8 , the voltage Q 1   v  of the switch Q 1  reaches Vin. The terminal voltage of the primary winding P 1  becomes zero and the terminal voltage of the secondary winding S 1  also becomes zero to zero the voltage Q 11   v  of the switch Q 11 . The voltage Q 1   v  of the switch Q 1  further increases to apply positive potential to the winding end of the primary winding P 1 . The winding end of the secondary winding S 1  also receives positive potential. At t 8 , the voltage Q 1   v  of the switch Q 1  reaches level of Vin+VC 2 . As a result, the terminal voltage of the primary winding P 1  becomes VC 2  and that of the secondary winding S 1  becomes VC 2 ·(n 2 /n 1 ). In the period T 8 , the terminal voltage of the primary winding P 1  with its winding end receiving positive potential changes from zero to VC 2 . At this time, the terminal potential of the secondary winding S 1  with its winding end receiving positive potential changes from zero to a level of VC 2 ·(n 2 /n 1 ). Accordingly, the current ILS(t) passing through the leakage inductance LS decreases as following expression: 
 
 ILS ( t )= ILS ( t 7)−( VS 1   ( t )/ LS )· t    (3), 
 
 where VS 1 (t) is the terminal voltage of the secondary winding S 1  and ILS(t 7 ) is a current passing through the leakage inductance LS at t 7 . The current passing through the leakage inductance LS is equal to the current passing through the diode D 10 , and therefore, the current D 10   i  of the diode D 10  decreases in the period T 8 . By a decrement in the current D 10   i  of the diode D 1 , the current D 11   i  of the diode D 11  increases. 
 
         [0030]     In the period T 8  on the secondary side of the transformer Ta, a current passes through the route of L 1 , C 10 , D 10 , LS, S 1 , and L 1  and another current passes through the route of L 1 , C 10 , D 11 , and L 1 . The former current decreases according to the expression (3), and the latter current increases by the decrement of the former current.  
         [0031]     At t 8  of period T 9 , the capacitor C 3  is completely charged, the voltage Q 1   v  of the switch Q 1  is substantially a level of Vin+VC 2 , and the terminal voltage of the primary winding P 1  is VC 2 . Accordingly, the terminal voltage VS 1 (t) of the secondary winding S 1  is a level of VC 2 ·(n 2 /n 1 ) and the current ILS(t) passing through the leakage inductance LS decreases as following expression:  
                     ILS   ⁡     (   t   )       =       ILS   ⁡     (     t   ⁢           ⁢   8     )       -       (     VS   ⁢           ⁢   1   ⁢       (   t   )     /   LS       )     ·   t                     =       ILS   ⁡     (     t   ⁢           ⁢   8     )       -       (     VC   ⁢           ⁢     2   ·       (     n   ⁢           ⁢     2   /   n     ⁢           ⁢   1     )     /   LS         )     ·   t         ,                 (   4   )             
 
 where ILS(t 8 ) is a current passing through the leakage inductance LS at t 8 . In this way, the current passing through the leakage inductance LS decreases, and by this decrement, the current D 11   i  of the diode D 11  increases. At t 9 , the current D 10   i  of the diode D 10  becomes zero, and the diode D 10  passes a reverse current due to a recovery current. The current D 11   i  of the diode D 11  becomes equal to a current passing through the smoothing reactor L 1 . The current Q 2   i  of the switch Q 2  is proportional to a current passing through the secondary winding S 1  at the ratio of the numbers of turns. Namely, the current Q 2   t  of the switch Q 2   i  increases and becomes an excitation current of the primary winding P 1  at t 9 . 
 
         [0032]     At t 9  of period T 10 , the recovery current of the diode D 10  decreases and the voltage Q 10   v  of the switch Q 10  increases. The voltage Q 10   v  reaches the gate threshold voltage Vth 11  of the switch Q 11  to turn on the switch Q 11 . Then, a current passing to the diode D 11  changes its direction to the switch Q 11 .  
         [0033]     The voltage Q 10   v  of the switch Q 10  oscillates due to the joint capacitance of the leakage inductance LS and diode D 10  and the output capacitance of the switch Q 10 . The oscillation of the voltage Q 10   v  gradually attenuates and reaches a level of VC 2 ·(n 2 /n 1 ).  
         [0034]     If the voltage Q 10   v  of the switch Q 10  oscillates to cross the gate threshold voltage Vth 11  of the switch Q 11 , the switch Q 11  repeatedly turns on and off to cause chattering as shown in an operational waveform of  FIG. 6  involving large ringing. To suppress such oscillation, the CR snubber circuit consisting of the resistor R 20  and capacitor C 20  may be added. Since the primary winding P 1  and secondary winding S 1  are loosely coupled to increase the leakage inductance LS, the amplitude of the oscillation is large and the frequency thereof is low. This results in increasing a loss of the CR snubber circuit and deteriorating efficacy.  
         [0035]     In this way, driving the synchronous rectifiers by the secondary winding S 1  according to the related art passes a current to the diode D 10  in the periods T 3 , T 4 , T 7 , T 8 , and T 9  and a current to the diode D 11  in the periods T 2 , T 3 , T 4 , T 8 , and T 9 . Namely, during these periods, no current passes through the synchronous rectifiers (switches Q 10  and Q 11 ). Instead, the currents pass through the diodes D 10  and D 11  during the periods, thereby deteriorating the efficiency of synchronous rectification and the efficiency of a power source. In addition, the diodes D 10  and D 11  connected in parallel with the synchronous rectifiers produce recovery currents that repeatedly turn on/off the synchronous rectifiers. This results in causing the chattering of the synchronous rectifiers and deteriorating efficiency. Adding the CR snubber circuits to suppress the chattering will increase losses and deteriorate efficiency.  
         [0036]      FIG. 3  is a circuit diagram showing a DC converter according to a second related art. In  FIG. 3 , the primary side of a transformer Tb employs an active clamp circuit and is the same as the primary side of the transformer Ta of  FIG. 1 , and therefore, the explanation thereof is omitted. The transformer Tb has a primary winding (having the number of turns of n 1 ), a first secondary winding S 1  (having the number of turns of n 2 ) very loosely coupled with the primary winding P 1 , and a second secondary winding S 2  (having the number of turns of n 3 ) loosely coupled with the primary winding P 1 . A first end of the first secondary winding S 1  is connected to a first end of the second secondary winding S 2 . The ends of the first secondary winding S 1  are connected through a leakage inductance L 1  to a saturable reactor LH. The saturable reactor LH is formed with the use of the saturation characteristic of a core of the transformer Tb.  
         [0037]     A second end (indicated with a filled circle) of the second secondary winding S 2  is connected through a leakage inductance LS to the cathode of a diode D 11 . The first end of the second secondary winding S 2  is connected to the cathode of a diode D 10 . The anode of the diode D 10  is connected to the anode of the diode D 11 .  
         [0038]     The ends of the diode D 10  are connected to the drain and source of a switch Q 10  such as a MOSFET. The ends of the diode D 11  are connected to the drain and source of a switch Q 11  such as a MOSFET. The gate of the switch Q 11  is connected to the first end of the second secondary winding S 2 . The gate of the switch Q 10  is connected through the leakage inductance LS to the second end of the second secondary winding S 2 . The second end of the first secondary winding S 1  is connected through the leakage inductance L 1  to a first end of a capacitor C 10 . A second end of the capacitor C 10  is connected to a node between the anode of the diode D 10  and the anode of the diode D 11 .  
         [0039]     The leakage inductance LS exists between the loosely coupled primary winding P 1  and second secondary winding S 2 . The leakage inductance L 1  between the very loosely coupled primary winding P 1  and first secondary winding S 1  serves as a smoothing reactor of the forward converter and accumulates energy when a switch Q 1  is ON. When the switch Q 1  is OFF, the second secondary winding S 2  returns the energy accumulated in the leakage inductance L 1  to the secondary side of the transformer Tb.  
         [0040]     The leakage inductance LS stores energy accumulated when the switch Q 1  is ON into a clamp capacitor C 2 , to drop a core around which the first secondary winding S 1  is wound to the third quadrant and saturate the same.  
         [0041]      FIG. 4  is a view showing the structure of the transformer Tb of the DC converter according to the second related art.  FIG. 5  is an equivalent circuit diagram showing the transformer of  FIG. 4 . In  FIG. 4 , the transformer Tb has a core  30  having a rectangular external shape. The core  30  has spaces  35   a  and  35   b  extending in parallel to each other in a longitudinal magnetic path direction, to form magnetic paths  32   a ,  32   b , and  32   c . Around a core part  30   a  of the core  30 , the primary winding P 1  and second secondary winding S 2  are wound adjacent to each other. This produces the slight leakage inductance LS between the primary winding P 1  and the second secondary winding S 2 . The core  30  has a path core  30   c  and a gap  31 . Around a peripheral core, the first secondary winding S 1  is wound. The path core  30   c  works to very loosely couple the primary winding P 1  and first secondary winding S 1  with each other, thereby increasing the leakage inductance L 1 .  
         [0042]     On the peripheral core and between the primary winding P 1  and the second secondary winding S 2 , a recess  30   b  is formed. The recess  30   b  reduces the sectional area of a part of a magnetic path of the core so that only the part may saturate. This configuration can reduce a core loss. The part that saturates is used as the saturable reactor LH. Forming the recess  30   b  at a part of the core  30  where the first secondary winding S 1  is wound results in saturating the part, increasing an excitation current, and producing a voltage resonance. Black dots shown in  FIG. 5  indicate the winding starts of the primary winding P 1 , first secondary winding S 1 , and second secondary winding S 2  of the transformer Tb.  
         [0043]     Operation of the DC converter of  FIG. 3  will be explained with reference to a timing chart of  FIG. 7 .  
         [0044]     Before t0, the switch Q 1  is OFF and the switch Q 2  ON. On the primary side of the transformer Tb, a current passes through a route of Q 2 , P 1 , C 2 , and Q 2 . On the secondary side of the transformer Tb, a current passes through a route of L 1 , C 10 , Q 11 , LS, S 2 , S 1 , and L 1 . A voltage Q 11   v  of the switch Q 11  is substantially zero. The switch Q 10  is OFF. The primary winding P 1  of the transformer Tb receives a voltage VC 2  from the clamp capacitor C 2 , and the potential of the winding end of the primary winding P 1  is positive. Accordingly, a terminal voltage of the second secondary winding S 2  is a level of VC 2 ·(n 3 /n 1 ) and the potential of the winding end of the second secondary winding S 2  is positive.  
         [0045]     The voltage of the first secondary winding S 1  (including the leakage inductance L 1 ) is a level of VC 2 ·(n 3 /n 1 )−Vout and the potential of the winding end of the first secondary winding S 1  is positive. The voltage Q 10   v  of the switch Q 10 , therefore, is positive and is equal to a level of VC 2 ·(n 3 /n 1 ). Namely, the gate voltage of the switch Q 11  is positive, and therefore, the switch Q 11  is ON.  
         [0046]     At t 0  of period T 1 , the switch Q 2  changes from ON to OFF and a current passing through the path along Q 2 , P 1 , C 2 , and Q 2  becomes zero. Instead, a current passes through a path along P 1 , Vin, C 3 , and P 1 , to discharge a capacitor C 3  and drop the voltage Q 1   v  of the switch Q 1 . When the voltage Q 1   v  drops, the terminal voltage of the primary winding P 1  decreases to decrease the terminal voltage of the second secondary winding S 2 . This results in decreasing the voltage Q 10   v  of the switch Q 10 .  
         [0047]     At t 1  of period T 2 , the voltage Q 10   v  of the switch Q 10  decreases to a gate threshold voltage Vth 11  of the switch Q 11 , to turn off the switch Q 11 . A current Q 11   i  of the switch Q 11  becomes zero, and the current to the switch Q 11  starts to pass through the diode D 11 .  
         [0048]     At t 2  of period T 3 , the voltage Q 1   v  of the switch Q 1  reaches Vin. The terminal voltage of the primary winding P 1  becomes zero, and therefore, the terminal voltage of the second secondary winding S 2  becomes zero. This drops the voltage Q 10   v  of the switch Q 10  to zero. The voltage Q 1   v  of the switch Q 1  further decreases to apply positive potential to the winding start of the primary winding P 1 , and therefore, positive potential is applied to the winding start of the second secondary winding S 2 . At t 3 , the voltage Q 1   v  of the switch Q 1  becomes zero. Then, the terminal voltage of the primary winding P 1  becomes Vin and the terminal voltage of the second secondary winding S 2  becomes a level of Vin·(n 3 /n 1 ). In the period T 3 , the terminal voltage of the primary winding P 1  changes from zero to Vin with the winding start of the primary winding P 1  being positive. At this time, the terminal voltage of the second secondary winding S 2  changes from zero to a level of Vin·(n 3 /n 1 ) with the winding start of the second secondary winding S 2  being positive.  
         [0049]     Accordingly, a current ILS(t) passing through the leakage inductance LS decreases as following expression: 
 
 ILS ( t )= ILS ( t 2)−( VS 2( t )/ LS )· t    (5), 
 
 where VS 2 (t) is a terminal voltage of the second secondary winding S 2  and ILS(t 2 ) is a current passing through the leakage inductance LS at t 2 . The current passing through the leakage inductance LS is equal to the current of the diode D 11 , and therefore, the current D 11   i  of the diode D 11  decreases in the period T 3 . 
 
         [0050]     By a decrement of the current D 11   i  of the diode D 11 , the current D 10  of the diode D 10  increases. During the period T 3  on the secondary side of the transformer Tb, a current passes through a path along L 1 , C 10 , D 11 , LS, S 2 , S 1 , and L 1  and another current passes through a path along L 1 , C 10 , D 10 , S 1 , and L 1 . The former current decreases according to the expression (5), and the latter current increases thereby.  
         [0051]     At t 3  of period T 4 , the capacitor C 3  completely discharges, the voltage Q 1   v  of the switch Q 1  becomes zero, the current passing through the path along P 1 , Vin, C 3 , and P 1  changes its direction to a path along P 1 , Vin, D 1  (Q 1 ), and P 1 , and the switch Q 1  turns on in response to a gate signal Q 1   g.    
         [0052]     In the period T 4 , the voltage Q 1   v  of the switch Q 1  is substantially zero and the terminal voltage of the primary winding P 1  is Vin. The terminal voltage VS 2 (t) of the second secondary winding S 2 , therefore, is a level of Vin·(n 3 /n 1 ). The current ILS(t) passing through the leakage inductance LS decreases as following expression:  
                     ILS   ⁡     (   t   )       =       ILS   ⁡     (     t   ⁢           ⁢   3     )       -       (     VS   ⁢           ⁢   2   ⁢       (   t   )     /   LS       )     ·   t                     =       ILS   ⁡     (     t   ⁢           ⁢   3     )       -       (     Vin   ·       (     n   ⁢           ⁢     3   /   n     ⁢           ⁢   1     )     /   LS       )     ·   t         ,                 (   6   )             
 
 where ILS(t 3 ) is a current passing through the leakage inductance LS at t 3 . By a decrement of the current passing through the leakage inductance LS, the current D 10   i  of the diode D 10  increases. At t 4 , the current D 10   i  of the diode D 10  reaches a current passing through the leakage inductance L 1 . Then, the current D 11   i  of the diode D 11  becomes zero and the diode D 11  passes a reverse current due to a recovery current of the diode D 11 . 
 
         [0053]     The current Q 1   i  of the switch Q 1  is proportional to a current passing through the second secondary winding S 2  at the ratio of the numbers of turns. The current Q 1   i  of the switch Q 1 , therefore, increases and reaches at t 4  the ratio of the numbers of turns times the current passing through the leakage inductance L 1 .  
         [0054]     At t 4  of period T 5 , the recovery current of the diode D 11  decreases, and the voltage Q 11   v  of the switch Q 11  increases. When the voltage Q 11   v  of the switch Q 11  reaches a gate threshold voltage Vth 10  of the switch Q 10 , the switch Q 10  turns on so that the current passing through the diode D 10  changes its direction to the switch Q 10 . The voltage Q 11   v  of the switch Q 11  oscillates due to the joint capacitance of the leakage inductance LS and diode D 11  and the output capacitance of the switch Q 11 . The oscillation gradually attenuates, and the voltage Q 11   v  of the switch Q 11  settles to a level of Vin·(n 3 /n 1 ).  
         [0055]     If the voltage Q 11   v  of the switch Q 11  oscillates to cross the gate threshold voltage Vth 10  of the switch Q 10 , the switch Q 10  repeatedly turns on and off to cause chattering as shown in the operational waveform of  FIG. 6  involving large ringing. To suppress such oscillation, a CR snubber circuit consisting of a resistor R 21  and a capacitor C 21  may be added. Since the primary winding P 1  and second secondary winding S 2  are loosely coupled to increase the leakage inductance LS, the amplitude of the oscillation is large and the frequency thereof is low. This results in increasing a loss of the CR snubber circuit and deteriorating efficacy.  
         [0056]     At t 5  of period T 6 , the gate signal Q 1   g  of the switch Q 1  falls to zero, to zero the current Q 1   i  of the switch Q 1 . The current passing through the path along Vin, P 1 , Q 1 , and Vin starts to change to the route of Vin, P 1 , C 3 , and Vin, to increase the voltage of the capacitor C 3 . As a result, the voltage Q 1   v  of the switch Q 1  increases and the voltage Q 11   v  of the switch Q 11  decreases.  
         [0057]     At t 6  of period T&amp;, the voltage Q 11   v  of the switch Q 11  decreases to the gate threshold voltage Vth 10  of the switch Q 10 . The switch Q 10  turns off to zero the current Q 10   i  of the switch Q 10 , and the current passing through the switch Q 10  changes its direction to the diode D 10 .  
         [0058]     At t 7  of period T 8 , the voltage Q 1   v  of the switch Q 1  reaches Vin. The terminal voltage of the primary winding P 1  becomes zero and the terminal voltage of the second secondary winding S 2  also becomes zero to zero the voltage Q 11   v  of the switch Q 11 . The voltage Q 1   v  of the switch Q 1  further increases to apply positive potential to the winding end of the primary winding P 1 . The winding end of the second secondary winding S 2  also receives positive potential. At t   8 ,  the voltage Q 1   v  of the switch Q 1  reaches a level of Vin+VC 2 . As a result, the terminal voltage of the primary winding P 1  becomes VC 2  and that of the second secondary winding S 2  becomes a level of VC 2 ·(n 3 /n 1 ).  
         [0059]     In the period T 8 , the terminal voltage of the primary winding P 1  with its winding end receiving positive potential changes from zero to VC 2 . At this time, the terminal potential of the second secondary winding S 2  with its winding end receiving positive potential changes from zero to a level of VC 2 ·(n 3 /n 1 ). Accordingly, the current ILS(t) passing through the leakage inductance LS increases as following expression: 
 
 ILS ( t )=( VS 2( t )/ LS )− t    (7), 
 
 where VS 2 (t) is the terminal voltage of the second secondary winding S 2 . The current passing through the leakage inductance LS is equal to the current passing through the diode D 11 , and therefore, the current D 11   i  of the diode D 11  increases in the period T 8 . By an increment in the current D 11   i  of the diode D 11 , the current D 10   i  of the diode D 10  decreases. 
 
         [0060]     In the period T 8  on the secondary side of the transformer Tb, a current passes through the route of L 1 , C 10 , D 10 , S 1 , and L 1  and another current passes through the route of L 1 , C 10 , D 11 , LS, S 2 , S 1 , and L 1 . The latter current increases according to the expression (7), and the former current decreases by the increment of the latter current.  
         [0061]     At t 8  of period T 9 , the capacitor C 3  is completely charged, the voltage Q 1   v  of the switch Q 1  is substantially a level of Vin+VC 2 , and the terminal voltage of the primary winding P 1  is VC 2 . Accordingly, the terminal voltage VS 2 (t) of the second secondary winding S 2  is a level of VC 2 ·(n 3 /n 1 ) and the current ILS (t) passing through the leakage inductance LS increases as following expression:  
                     ILS   ⁡     (   t   )       =       ILS   ⁡     (     t   ⁢           ⁢   8     )       +       (     VS   ⁢           ⁢   2   ⁢       (   t   )     /   LS       )     ·   t                     =       ILS   ⁡     (     t   ⁢           ⁢   8     )       +       (     VC   ⁢           ⁢     2   ·       (     n   ⁢           ⁢     3   /   n     ⁢           ⁢   1     )     /   LS         )     ·   t         ,                 (   8   )             
 
 where ILS(t 8 ) is a current passing through the leakage inductance LS at t 8 . In this way, the current passing through the leakage inductance LS increases, and by this increment, the current D 10   i  of the diode D 10  decreases. At t 9 , the current D 10   i  of the diode D 10  becomes zero, and the diode D 10  passes a reverse current due to a recovery current. The current D 11   i  of the diode D 11  becomes equal to a current passing through the leakage inductance L 1 . The current Q 2   i  of the switch Q 2  is proportional to a current passing through the second secondary winding S 2  at the ratio of the numbers of turns. Namely, the current Q 2   i  of the switch Q 2  increases and becomes an excitation current of the primary winding P 1  at t 9 . 
 
         [0062]     At t 9  of period T 10 , the recovery current of the diode D 10  decreases and the voltage Q 10   v  of the switch Q 10  increases. The voltage Q 10   v  reaches the gate threshold voltage Vth 11  of the switch Q 11  to turn on the switch Q 11 . Then, a current passing through the diode D 1  changes its direction to the switch Q 11 . The voltage Q 10   v  of the switch Q 10  oscillates due to the joint capacitance of the leakage inductance LS and diode D 10  and the output capacitance of the switch Q 10 . The oscillation of the voltage Q 10   v  gradually attenuates and reaches a level of VC 2 ·(n 3 /n 1 ).  
         [0063]     If the voltage Q 10   v  of the switch Q 10  oscillates to cross the gate threshold voltage Vth 11  of the switch Q 11 , the switch Q 11  repeatedly turns on and off to cause chattering as shown in the operational waveform of  FIG. 6  involving large ringing. To suppress such oscillation, a CR snubber circuit consisting of a resistor R 20  and a capacitor C 20  may be added. Since the primary winding P 1  and second secondary winding S 2  are loosely coupled to increase the leakage inductance LS, the amplitude of the oscillation is large and the frequency thereof is low. This results in increasing a loss of the CR snubber circuit and deteriorating efficacy.  
       SUMMARY OF THE INVENTION  
       [0064]     The DC converter of the second related art of  FIG. 3  has problems similar to the DC converter of the first related art of  FIG. 1 . Namely, driving the synchronous rectifiers by the second secondary winding S 2  passes a current to the diode D 10  in the periods T 3 , T 4 , T 7 , T 8 , and T 9  and a current to the diode D 11  in the periods T 2 , T 3 , T 4 , T 8 , and T 9 . Namely, during these periods, no current is passed through the synchronous rectifiers (switches Q 10  and Q 11 ). Instead, currents are passed through the diodes D 10  and D 11  during the periods, thereby deteriorating the efficiency of synchronous rectification and the efficiency of a power source. In addition, the diodes D 10  and D 11  connected in parallel with the synchronous rectifiers produce recovery currents that repeatedly turn on/off the synchronous rectifiers. This results in causing the chattering of the synchronous rectifiers and deteriorating efficiency. Adding the CR snubber circuits to suppress the chattering will increase losses and deteriorate efficiency.  
         [0065]     An object of the present invention is to provide a DC converter capable of stably driving synchronous rectifiers and improving efficiency.  
         [0066]     In order to accomplish the object, a first technical aspect of the present invention provides a DC converter having a transformer with loosely coupled primary and secondary windings, a main switch connected in series with the primary winding, and a series circuit connected to ends of one of the primary winding and main switch, the series circuit including a clamp capacitor and an auxiliary switch. The main and auxiliary switches are alternately turned on/off so that a voltage of the secondary winding of the transformer is synchronously rectified with synchronous rectifiers and is smoothed with smoothing elements, to provide a DC output. The DC converter also includes a tertiary winding tightly coupled with the primary winding of the transformer, a voltage source to supply a voltage lower than a voltage generated by the tertiary winding of the transformer, and clamp diodes to clamp the voltage generated by the tertiary winding with the use of the voltage source. The clamp diodes provide voltage-clamped signals to drive the synchronous rectifiers. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0067]      FIG. 1  is a circuit diagram showing a DC converter according to a first related art;  
         [0068]      FIG. 2  is a timing chart showing signals at various parts of the DC converter according to the first related art;  
         [0069]      FIG. 3  is a circuit diagram showing a DC converter according to a second related art;  
         [0070]      FIG. 4  is a view showing the structure of a transformer installed in the DC converter according to the second related art;  
         [0071]      FIG. 5  is an equivalent circuit diagram showing the transformer of  FIG. 4 ;  
         [0072]      FIG. 6  is a timing chart showing signals at various parts of the DC converter according to the second related art;  
         [0073]      FIG. 7  is a timing chart showing signals at various parts of the DC converter according to the second related art;  
         [0074]      FIG. 8  is a circuit diagram showing a DC converter according to an first embodiment of the present invention;  
         [0075]      FIG. 9  is a timing chart showing signals at various parts of the DC converter according to the first embodiment;  
         [0076]      FIG. 10  is a timing chart showing signals at the various parts of  FIG. 9  with a clamp diode D 20  producing a large amount of recovery current;  
         [0077]      FIG. 11  is a timing chart showing signals at the various parts of  FIG. 9  when clamp diodes D 20  and D 22  producing a large amount of recovery current;  
         [0078]      FIG. 12  is a circuit diagram showing a DC converter according to an second embodiment of the present invention;  
         [0079]      FIG. 13  is a circuit diagram showing a DC converter according to an third embodiment of the present invention;  
         [0080]      FIG. 14  is a view showing the structure of a transformer installed in the DC converter according to the third embodiment;  
         [0081]      FIG. 15  is an equivalent circuit diagram showing the transformer of  FIG. 14 ; and  
         [0082]      FIG. 16  is a timing chart showing signals at various parts of the DC converter according to the third embodiment. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0083]     DC converters according to embodiments of the present invention will be explained in detail with reference to the drawings.  
       First Embodiment  
       [0084]      FIG. 8  is a circuit diagram showing a DC converter according to the first embodiment of the present invention. The first embodiment will be mainly explained in connection with parts that are different from those of the DC converter of  FIG. 1 .  
         [0085]     A transformer Tc has a primary winding P 1  (having the number of turns of n 1 ), a secondary winding S 1  (having the number of turns of n 2 ) loosely coupled with the primary winding P 1 , and a tertiary winding S 3  (having the number of turns of n 4 ) tightly coupled with the primary winding P 1 . The tertiary winding S 3  is connected in series with a resistor R 22 . Ends of a smoothing capacitor C 10  are connected to a series circuit including clamp diodes D 20  and D 21 , as well as to a series circuit including clamp diodes D 22  and D 23 . A first end of the resistor R 22  is connected to a node between the clamp diodes D 20  and D 21  and to the gate of a switch Q 10 . A first end of the tertiary winding S 3  is connected to a node between the clamp diodes D 22  and D 23  and to the gate of a switch Q 11 . A second end of the resistor R 22  is connected to a second end of the tertiary winding S 3 .  
         [0086]     To turn on the switch Q 10  when a switch Q 1  is ON, the winding start of the tertiary winding S 3  is connected through the resistor R 22  to the gate of the switch Q 10 . To turn on the switch Q 11  when the switch Q 1  is OFF, the winding end of the tertiary winding S 3  is connected to the gate of the switch Q 11 .  
         [0087]     The smoothing capacitor C 10  provides an output voltage Vout serving as a voltage source (herein after referred to as “clamp voltage source”) . The output voltage Vout is lower than a voltage generated by the tertiary winding S 3 . The clamp voltage source may be a discrete power source.  
         [0088]     The clamp diodes D 20 , D 21 , D 22 , and D 23  clamp a winding voltage generated by the tertiary winding S 3  at the output voltage Vout, i.e., the clamp voltage source. The resistor R 22  limits a clamp current passing through the clamp diodes when the winding voltage is clamped at the clamp voltage.  
         [0089]     Recovery currents of the clamp diodes D 20 , D 21 , D 22 , and D 23  are used so that voltage signals clamped by the clamp diodes D 20 , D 21 , D 22 , and D 23  may drive the gates of the switches Q 10  and Q 11  serving as synchronous rectifiers. This operation extends the ON period of each synchronous rectifier and improves the efficiency of synchronous rectification. More precisely, the clamp diodes D 20  and D 21  clamp a signal D 21   v  that serves as a drive signal for driving the gate of the switch Q 10 . The clamp diodes D 22  and D 23  clamp a signal D 23   v  that serves as a drive signal for driving the gate of the switch Q 11 .  
         [0090]     Driving the synchronous rectifiers with the tertiary winding S 3  realizes stable operation of the synchronous rectifiers and improves efficiency because the synchronous rectifiers are never repeatedly turned on and off to cause chattering due to oscillation caused by recovery currents of rectifying diodes that are connected in parallel with the synchronous rectifiers.  
         [0091]     The tertiary winding S 3  is tightly coupled with the primary winding P 1 , and therefore, has the same voltage waveform as that of the primary winding P 1 . The DC converter according to the first embodiment, therefore, can extend the ON period of each synchronous rectifier and improve the efficiency thereof. The DC converter employs the tertiary winding S 3  tightly coupled with the primary winding P 1 , to drive the synchronous rectifiers, i.e., the switches Q 10  and Q 11 . This prevents the synchronous rectifiers from repeatedly turning on and off to cause chattering due to oscillation caused by recovery currents of the rectifying diodes D 10  and D 11  connected in parallel with the synchronous rectifiers. Namely, the DC converter of this embodiment can stably drive the synchronous rectifiers and improve the efficiency thereof.  
         [0092]     Compared with the DC converter of  FIG. 1 , the DC converter of  FIG. 8  has no CR snubber circuits (the resistors R 20  and R 21  and capacitors C 20  and C 21 ).  
         [0093]     Operation of the DC converter according to the first embodiment will be explained with reference to a timing chart of  FIG. 9 . In addition to the signals shown in  FIG. 2 ,  FIG. 9  includes currents D 20   i , D 21   i , D 22   i , and D 23   i  passing through the clamp diodes D 20 , D 21 , D 22 , and D 23 , respectively, a drive signal D 21   v  for driving the gate of the switch Q 10 , and a drive signal D 23   v  for driving the gate of the switch Q 11 .  
         [0094]     Before t0, the switch Q 1  is OFF and a switch Q 2  ON. On the primary side of the transformer Tc, a current passes through a path along Q 2 , P 1 , C 2 , and Q 2 . The primary winding P 1  of the transformer Tc receives a voltage VC 2  from the clamp capacitor C 2 , and the potential of the winding end of the primary winding P 1  is positive. Accordingly, the potential of the winding end of the tertiary winding S 3  is positive, and a current passes through a path along S 3 , D 22 , C 10 , D 21 , R 20 , and S 3 . The voltage D 23   v  is substantially equal to the clamp voltage (output voltage Vout), and therefore, the gate voltage of the switch Q 11  is positive to turn on the switch Q 11 . The voltage D 21   v  is substantially at a ground voltage GND, and therefore, the switch Q 10  is OFF. The clamp diodes D 21  and D 22  pass the currents D 21   i  and D 22   i  that are expressed as following expression: 
 
 D 21 i=D 22 i =( Vc 2·( n 4/ n 1)− V out)/ R 22. 
 
         [0095]     On the secondary side of the transformer Tc, a current passes through a path along L 1 , C 10 , Q 11 , and L 1 .  
         [0096]     At t 0  of period T 1 , the switch Q 2  changes from ON to OFF and the current passing through the path along Q 2 , P 1 , C 2 , and Q 2  becomes zero. Instead, a current passes through a path along P 1 , Vin, C 3 , and P 1 , to discharge the capacitor C 3  and drop a voltage Q 1   v  of the switch Q 1 . When the voltage Q 1   v  drops, the terminal voltage of the primary winding P 1  decreases to decrease the terminal voltage of the tertiary winding S 3 . This results in decreasing the currents D 21   i  and D 22   i . At the same time, the terminal voltage of the secondary winding S 1  decreases to decrease the voltage Q 10   v  of the switch Q 10 .  
         [0097]     At t 2  of period T 3 , the voltage Q 1   v  of the switch Q 1  reaches a level of Vin. The terminal voltage of the primary winding P 1  becomes zero, and therefore, the terminal voltage of the tertiary winding S 3  becomes zero to zero the currents D 21   i  and D 22   i . The terminal voltage of the secondary winding S 1  also becomes zero to zero the voltage Q 10   v  of the switch Q 10 . The voltage Q 1   v  of the switch Q 1  further decreases to apply positive potential to the winding start of the primary winding P 1 , and therefore, positive potential is applied to the winding start of the tertiary winding S 3 . A current flows through a path along S 3 , R 22 , D 20 , C 10 , D 23 , and S 3  to make the clamp diodes D 20  and D 23  conductive. As a result, the voltage D 23   v  becomes substantially zero, the switch Q 11  turns off, and the current passing through the switch Q 11  changes its direction to the diode D 11 .  
         [0098]     The voltage D 21   v  becomes substantially the clamp voltage to turn on the switch Q 10 . The winding start of the secondary winding S 1  receives positive potential. At t 3 , the voltage Q 1   v  of the switch Q 1  becomes zero. Then, the terminal voltage of the primary winding P 1  becomes Vin and the terminal voltage of the secondary winding S 1  becomes a level of Vin·(n 2 /n 1 ). In the period T 3 , the terminal voltage of the primary winding P 1  changes from zero to Vin with the winding start of the primary winding P 1  being positive. At this time, the terminal voltage of the secondary winding S 1  changes from zero to a level of Vin·(n 2 /n 1 ) with the winding start of the secondary winding S 1  being positive.  
         [0099]     Accordingly, a current ILS(t) passing through a leakage inductance LS increases as following expression: 
 
 ILS ( t )=( VS 1( t )/ LS ) t    (9), 
 
 where VS 1 (t) is the terminal voltage of the secondary winding S 1 . The current passing through the leakage inductance LS is equal to the current of the diode D 10 , and therefore, the current Q 10   i  of the switch Q 10  increases in the period T 3 . By an increment of the current Q 10   i  of the switch Q 10 , the current D 11   i  of the diode D 11  decreases. 
 
         [0100]     During the period T 3  on the secondary side of the transformer Tc, a current passes through a path along L 1 , C 10 , D 11 , and L 1  and another current passes through a path along L 1 , C 10 , Q 10 , LS, S 1 , and L 1 . The latter current increases according to the expression (9), and the former current decreases thereby.  
         [0101]     At t 3  of period T 4 , the capacitor C 3  completely discharges, the voltage Q 1   v  of the switch Q 1  becomes zero, the current passing through the path along P 1 , Vin, C 3 , and P 1  changes its direction to a route of P 1 , Vin, D 1  (Q 1 ), and P 1 , and the switch Q 1  turns on in response to the gate signal Q 1   g.    
         [0102]     In the period T 4 , the voltage Q 1   v  of the switch Q 1  is substantially zero and the terminal voltage of the primary winding P 1  is a level of Vin. The terminal voltage VS 1 (t) of the secondary winding S 1 , therefore, is a level of Vin·(n 2 /n 1 ). The current ILS(t) passing through the leakage inductance LS increases as following expression:  
                     ILS   ⁡     (   t   )       =         (     VS   ⁢           ⁢   1   ⁢       (   t   )     /   LS       )     ·   t     +     ILS   ⁡     (     t   ⁢           ⁢   3     )                       =         (     Vin   ·       (     n   ⁢           ⁢     2   /   n     ⁢           ⁢   1     )     /   LS       )     ·   t     +     ILS   ⁡     (     t   ⁢           ⁢   3     )           ,                 (   10   )             
 
 where ILS(t 3 ) is a current passing through the leakage inductance LS at t 3 . By an increment of the current passing through the leakage inductance LS, the current D 11   i  of the diode D 11  decreases and reaches at t 4  a current passing through the smoothing reactor L 1 . Then, the current ILS(t) becomes equal to the current of the smoothing reactor L 1 , the current D 11   i  of the diode D 11  becomes zero, and the diode D 11  passes a reverse current due to a recovery current of the diode D 11 . 
 
         [0103]     The current Q 1   i  of the switch Q 1  is proportional to a current passing through the secondary winding S 1  at the ratio of the numbers of turns. The current Q 1   i  of the switch Q 1 , therefore, increases and reaches at t 4  the current passing through the smoothing reactor L 1  times the ratio of the numbers of turns.  
         [0104]     The currents D 20   i  and D 23   i  of the clamp diodes D 20  and D 23  passing through the path along S 3 , R 22 , D 20 , C 10 , D 23 , and S 3  are expressed as following expression:  
         [0105]     D 20   i =D 23   i =(Vin·(n 4 /n 1 )−Vout)/R 22 .  
         [0106]     At t 4  of period T 5 , the recovery current of the diode D 11  decreases, and the voltage Q 11   v  of the switch Q 11  increases. The voltage Q 11   v  of the switch Q 11  oscillates due to the joint capacitance of the leakage inductance LS and diode D 11  and the output capacitance of the switch Q 11 . The oscillation gradually attenuates, and the voltage Q 11   v  of the switch Q 11  settles to a level of Vin·(n 2 /n 1 ). Even if the oscillation becomes larger, the tertiary winding S 3  that drives the switches Q 10  and Q 11 , i.e., the synchronous rectifiers and is tightly coupled with the primary winding P 1  is never affected thereby. Accordingly, the switch Q 10  is not repeatedly turned on and off to cause the chattering observed in the operational waveforms of the related art shown in  FIG. 6 .  
         [0107]     At t 5  of period T 6 , the gate signal Q 1   g  of the switch Q 1  falls to zero the current Q 1   i  of the switch Q 1 . The current passing through the path along Vin, P 1 , Q 1 , and Vin starts to change to the path along Vin, P 1 , C 3 , and Vin, to increase the voltage of the capacitor C 3 . As a result, the voltage Q 1   v  of the switch Q 1  increases, the terminal voltage of the primary winding P 1  decreases, and the terminal voltage of the tertiary winding S 3  decreases to decrease the currents to the clamp diodes D 20  and D 23 . At the same time, the voltage of the secondary winding S 1  decreases to drop the voltage Q 11   v  of the switch Q 11 .  
         [0108]     At t 7  of period T 8 , the voltage Q 1   v  of the switch Q 1  reaches Vin. The terminal voltage of the primary winding P 1  becomes zero and the terminal voltage of the tertiary winding S 3  becomes zero to zero the currents D 20   i  and D 23   i  of the clamp diodes D 20  and D 23 . At the same time, the terminal voltage of the secondary winding S 1  becomes zero to zero the voltage Q 11   v  of the switch Q 11 . The voltage Q 1   v  of the switch Q 1  further increases to apply positive potential to the winding end of the primary winding P 1 . The winding end of the tertiary winding S 3  also receives positive potential. Then, a current passes through a path along S 3 , D 22 , C 10 , D 21 , R 22 , and S 3  to make the clamp diodes D 21  and D 22  conductive. The voltage D 21   v  becomes nearly zero, the switch Q 10  turns off, and the current passing through the switch Q 10  changes its direction to the diode D 10 . The voltage D 23   v  becomes nearly equal to the clamp voltage to turn on the switch Q 11 . The winding end of the secondary winding S 1  also receives positive potential. At t 8 , the voltage Q 1   v  of the switch Q 1  reaches a level of Vin+VC 2 . As a result, the terminal voltage of the primary winding P 1  becomes VC 2  and that of the secondary winding S 1  becomes a level of VC 2 ·(n 2 /n 1 ).  
         [0109]     In the period T 8 , the terminal voltage of the primary winding P 1  with its winding end receiving positive potential changes from zero to VC 2 . At this time, the terminal potential of the secondary winding S 1  with its winding end receiving positive potential changes from zero to a level of VC 2 ·(n 2 /n 1 ). Accordingly, the current ILS(t) passing through the leakage inductance LS decreases as following expression: 
 
 ILS ( t )= ILS ( t 7)−( VS 1( t )/ LS ) t    (11), 
 
 where VS 1 (t) is the terminal voltage of the secondary winding S 1  and ILS(t 7 ) is a current passing through the leakage inductance LS at t 7 . The current passing through the leakage inductance LS is equal to the current passing through the diode D 10 , and therefore, the current D 10   i  of the diode D 10  decreases in the period T 8 . By a decrement in the current D 10   i  of the diode D 10 , the current Q 11   i  of the switch Q 11  increases. In the period T 8  on the secondary side of the transformer Tc, a current passes through a path along L 1 , C 10 , D 10 , LS, S 1 , and L 1  and another current passes through the path along L 1 , C 10 , Q 11 , and L 1 . The former current decreases according to the expression (11), and the latter current increases by the decrement of the former current. 
 
         [0110]     At t 8  of period T 9 , the capacitor C 3  is completely charged, the voltage Q 1   v  of the switch Q 1  is substantially a level of Vin+VC 2 , and the terminal voltage of the primary winding P 1  is VC 2 . Accordingly, the terminal voltage VS 1 (t) of the secondary winding S 1  is a level of VC 2 ·(n 2 /n 1 ) and the current ILS(t) passing through the leakage inductance LS decreases as following expression:  
                     ILS   ⁡     (   t   )       =       ILS   ⁡     (     t   ⁢           ⁢   8     )       -       (     VS   ⁢           ⁢   1   ⁢       (   t   )     /   LS       )     ·   t                     =       ILS   ⁡     (     t   ⁢           ⁢   8     )       -       (     VC   ⁢           ⁢     2   ·       (     n   ⁢           ⁢     2   /   n     ⁢           ⁢   1     )     /   LS         )     ·   t         ,                 (   12   )             
 
 where ILS(t 8 ) is a current passing through the leakage inductance LS at t 8 . In this way, the current passing through the leakage inductance LS decreases, and by this decrement, the current Q 11   i  of the switch Q 11  increases. At t 9 , the current passing through the leakage inductance LS becomes zero, and the current Q 11   i  of the switch Q 11  becomes equal to a current passing through the smoothing reactor L 1 . 
 
         [0111]     The current Q 2   i  of the switch Q 2  is proportional to a current passing through the secondary winding S 1  at the ratio of the numbers of turns. Namely, the current Q 2   i  of the switch Q 2  increases and becomes an excitation current of the primary winding P 1  at t 9 .  
         [0112]     The currents D 21   i  and D 22   i  of the diodes D 21  and D 22  passing through the path along S 3 , D 22 , C 10 , D 21 , R 22 , and S 3  are expressed as following expression: 
 
 D 21 i=D 22 i =( VC 2·( n 4/ n 1)− V out)/ R 22. 
 
         [0113]     At t 9  of period T 10 , a recovery current of the diode D 10  decreases and the voltage Q 10   v  of the switch Q 10  increases. The voltage Q 10   v  oscillates due to the joint capacitance of the leakage inductance LS and diode D 10  and the output capacitance of the switch Q 10 . The oscillation gradually attenuates and the voltage Q 10   v  becomes a level of VC 2 ·(n 2 /n 1 ). Even if the oscillation becomes larger, the tertiary winding S 3  that drives the switches Q 10  and Q 11 , i.e., the synchronous rectifiers and is tightly coupled with the primary winding P 1  is never affected thereby. Accordingly, the switch Q 11  is never repeatedly turned on and off to cause the chattering observed in the operational waveforms of the related art shown in  FIG. 6 .  
         [0114]     In this way, the first embodiment employs the output voltage Vout that is lower than a voltage generated by the tertiary winding S 3 , to clamp the voltage generated by the tertiary winding S 3  at the clamp diodes D 20  to D 23 . The clamp diodes D 20  to D 23  provide voltage-clamped signals to drive the gates of the switches Q 10  and Q 11 , i.e., the synchronous rectifiers. As a result, the ON period of the switch Q 10  is extended from a range of t 4  to t 6  to a range of t 2  to t 7 , thereby elongating a period to pass the current Q 10   i  to the switch Q 10 . Also, the ON period of the switch Q 11  is extended from a range of t 9  to t 1  to a range of t 7  to t 2 , thereby elongating a period in which the current Q 11   i  is passed to the switch Q 11 . Consequently, the DC converter according to the first embodiment is highly efficient.  
         [0115]     Oscillation due to the recovery currents of the rectifying diodes D 10  and D 11  connected in parallel with the switches Q 10  and Q 11 , i.e., the synchronous rectifiers never repeatedly turn on and off the switches Q 10  and Q 11  to cause chattering. As a result, the DC converter according to the first embodiment can stably and efficiently drive the synchronous rectifiers.  
         [0116]     Operation of the DC converter with the clamp diode D 20  involving a large amount of recovery current will be explained.  
         [0117]      FIG. 10  is a timing chart showing signals at different parts of the DC converter of the first embodiment shown in  FIG. 8  with the clamp diode D 20  involving a large amount of recovery current. With the clamp diode D 20  involving a large amount of recovery current, the voltage D 21   v  is substantially equal to the clamp voltage during a period of t 7  to t 8   a  in which the clamp diode D 20  passes the recovery current. As a result, the OFF timing of the gate signal to the switch Q 10  is delayed up to t 8   a , to extend the ON period of the switch Q 10  longer than that shown in  FIG. 9 . This further improves the efficiency of the DC converter.  
         [0118]     The details of operation of the DC converter with the clamp diode D 20  involving a large amount of recovery current will be explained with reference to  FIG. 10 .  
         [0119]     In  FIG. 10 , actions before t 0  and in the periods T 1 , T 3 , T 4 , T 5 , T 6 , and T 10  are the same as those shown in the timing chart of  FIG. 9 , and therefore, will not be explained. Operation in the periods T 8  and T 9  will be explained.  
         [0120]     At t 7  of the period T 8 , the voltage Q 1   v  of the switch Q 1  reaches a level of Vin. The terminal voltage of the primary winding P 1  becomes zero and the terminal voltage of the tertiary winding S 3  also becomes zero to zero the currents of the clamp diodes D 20  and D 23 . The terminal voltage of the secondary winding S 1  also becomes zero, and therefore, the voltage Q 11   v  of the switch Q 11  becomes zero. The voltage Q 1   v  of the switch Q 1  further increases to apply positive potential to the winding end of the primary winding P 1 . The winding end of the tertiary winding S 3  also receives positive potential.  
         [0121]     Since the clamp diode D 20  involves a large amount of recovery current, the clamp diode D 20  still passes the recovery current through a path along S 3 , D 22 , D 20 , R 22 , and S 3 . As a result, the clamp diode D 22  is conductive, the voltage D 23   v  is substantially equal to the clamp voltage, and the switch Q 11  turns on. Due to the recovery current passing through the clamp diode D 20 , the clamp diode D 21  is nonconductive, the voltage D 21   v  is equal to the clamp voltage, and the switch Q 10  is continuously ON. The winding end of the secondary winding S 1  receives positive potential. At t 8 , the voltage Q 1   v  of the switch Q 1  reaches a level of Vin+VC 2 . As a result, the terminal voltage of the primary winding P 1  becomes VC 2  and that of the secondary winding S 1  becomes a level of VC 2 ·(n 2 /n 1 ).  
         [0122]     In the period T 8 , the terminal voltage of the primary winding P 1  with its winding end receiving positive potential changes from zero to VC 2 . At this time, the terminal potential of the secondary winding S 1  with its winding end receiving positive potential changes from zero to a level of VC 2 ·(n 2 /n 1 ). Accordingly, the current ILS(t) passing through the leakage inductance LS decreases according to the above-mentioned expression (11) in which VS 1 (t) is the terminal voltage of the secondary winding S 1  and ILS (t 7 ) is a current passing through the leakage inductance LS at t 7 . The current passing through the leakage inductance LS is equal to the current passing through the switch Q 10 , and therefore, the current Q 10   i  of the switch Q 10  decreases in the period T 8 . By a decrement in the current Q 10   i  of the switch Q 10 , the current Q 11   i  of the switch Q 11  increases. In the period T 8  on the secondary side of the transformer Tc, a current passes through the path along L 1 , C 10 , Q 10 , LS, S 1 , and L 1  and another current passes through the path along L 1 , C 10 , Q 11 , and L 1 . The former current decreases according to the expression (11), and the latter current increases by the decrement of the former current.  
         [0123]     At t 8  of period T 9 , the capacitor C 3  is completely charged, the voltage Q 1   v  of the switch Q 1  is substantially a level of Vin+VC 2 , and the terminal voltage of the primary winding P 1  is VC 2 . Accordingly, the terminal voltage VS 1 (t) of the secondary winding S 1  is a level of VC 2 ·(n 2 /n 1 ) and the current ILS(t) passing through the leakage inductance LS decreases according to the expression (12).  
         [0124]     At t 8   a , the recovery current of the clamp diode D 20  disappears, and the clamp diode D 21  becomes conductive. The current passing through the path along S 3 , D 22 , D 20 , R 22 , and S 3  changes its direction to the route of S 3 , D 22 , C 10 , D 21 , R 22 , and S 3 . As a result, the voltage D 21   v  becomes substantially zero, the switch Q 10  is turned off, and the current passing through the switch Q 10  changes its direction to the diode D 10 . The current ILS(t) passing through the leakage inductance LS of the expression (12) is equal to the current of the switch Q 10  or diode D 10 . Accordingly, by a decrement in the current of the switch Q 10  or diode D 10  according to the expression (12), the current Q 11   i  of the switch Q 11  increases. At t 9 , the current D 10   i  of the diode D 10  becomes zero and the current Q 11   i  of the switch Q 11  becomes equal to a current passing through the smoothing reactor L 1 .  
         [0125]     The current Q 2   i  of the switch Q 2  is proportional to a current passing through the secondary winding S 1  at the ratio of the numbers of turns. Namely, the current Q 2   i  of the switch Q 2  increases and becomes an excitation current of the primary winding P 1  at t 9 .  
         [0126]     The currents D 21   i  and D 22   i  of the diodes D 21  and D 22  passing through the path along S 3 , D 22 , C 10 , D 21 , R 22 , and S 3  are expressed as following expression: 
 
 D 21 i=D 22 i =( VC 2·( n 4/ n   1)−   V out)/   R 22. 
 
         [0127]     In this way, this embodiment employs the tertiary winding S 3  tightly coupled with the primary winding P 1 , to drive the switches Q 10  and Q 11 , i.e., the synchronous rectifiers. In addition, this embodiment employs a diode involving a large amount of recovery current as the clamp diode D 20  of the DC converter of  FIG. 8 . The clamp diode D 20  involving a large amount of recovery current enables the voltage D 21   v  to be substantially equal to the clamp voltage during the period from t 7  to t 8   a . This substantial clamp voltage serves as a delay signal to delay the OFF timing of the gate signal to the switch Q 10  from t 7  to t 8   a.    
         [0128]     This results in extending the ON period of the switch Q 10  longer than that of  FIG. 9 . Namely, the ON period of the switch Q 10  is extended from the related art of t 4  to t 6  to the period of t 2  to t 8   a  of this embodiment. In this way, the clamp diode D 20  with a large amount of recovery current can extend a period in which a current is passed through the switch Q 10  serving as a synchronous rectifier.  
         [0129]     Operation of the DC converter with both the clamp diodes D 20  and D 22  involving a large amount of recovery current will be explained.  
         [0130]      FIG. 11  is a timing chart showing signals at different parts of the DC converter of the first embodiment shown in  FIG. 8  with the clamp diodes D 20  and D 22  involving a large amount of recovery current. With the clamp diodes D 20  and D 22  involving a large amount of recovery current, the voltage D 21   v  is substantially equal to the clamp voltage (delay signal) during a period from t 7  to t 8   a  in which the clamp diode D 20  passes a recovery current, and the voltage D 23   v  is substantially equal to the clamp voltage (delay signal) during a period from t 2  to t 3   a  in which the clamp diode D 22  passes a recovery current.  
         [0131]     This embodiment delays the OFF timing of the gate signal to the switch Q 10  from t 7  to t 8   a , and also, the OFF timing of the gate signal to the switch Q 11  from t 2  to t 3   a . This results in extending the ON periods of the switches Q 10  and Q 11  longer than those of  FIG. 8 , thereby improving the efficiency of the DC converter.  
         [0132]     Operation of the clamp diode D 22  involving a large amount of recovery current is the same as that of the clamp diode D 20  involving a large amount of recovery current already explained, and therefore, the explanation thereof is omitted.  
       SECOND EMBODIMENT  
       [0133]      FIG. 12  is a circuit diagram showing a DC converter according to the second embodiment of the present invention. The second embodiment of  FIG. 12  employs a first buffer circuit that includes transistors Q 20  and Q 21  and is connected between a node between clamp diodes D 20  and D 21  and the gate of a switch Q 10  serving as a synchronous rectifier. The second embodiment also employs a second buffer circuit that includes transistors Q 22  and Q 23  and is connected between a node between clamp diodes D 22  and D 23  and the gate of a switch Q 11  serving as a synchronous rectifier.  
         [0134]     The transistor Q 20  has a base connected to the node between the clamp diodes D 20  and D 21 , a collector connected to an output voltage Vout, and an emitter connected to the gate of the switch Q 10 . The transistor Q 21  has a base connected to the node between the clamp diodes D 20  and D 21 , a collector connected to the source of the switch Q 10  and the anode of the clamp diode D 21 , and an emitter connected to the gate of the switch Q 10 .  
         [0135]     The transistor Q 22  has a base connected to the node between the clamp diodes D 22  and D 23 , a collector connected to the output voltage Vout, and an emitter connected to the gate of the switch Q 11 . The transistor Q 23  has a base connected to the node between the clamp diodes D 22  and D 23 , a collector connected to the source of the switch Q 11  and the anode of the clamp diode D 23 , and an emitter connected to the gate of the switch Q 11 .  
         [0136]     Operational waveforms of various signals of the DC converter having the clamp diodes D 20 , D 21 , D 22 , and D 23  are similar to those of  FIG. 9 , and operation of the DC converter of  FIG. 12  is the same as that explained with reference to  FIGS. 8 and 9 . Accordingly, the explanation of operation of the DC converter according to the second embodiment is omitted.  
         [0137]     In  FIG. 12 , the clamp diode D 20  may be omitted. In this case, the switch Q 10  turns on when the winding start of a tertiary winding S 3  of a transformer Tc is at positive potential. When the switch Q 11  is OFF, a current to the tertiary winding S 3  passes through a path along S 3 , R 22 , Q 20  (base), Q 20  (collector), C 10 , D 23 , and S 3 .  
         [0138]     Namely, the current passes from the base to the collector, i.e., a p-n junction of the transistor Q 20 . As a result, recovery is slow as if the clamp diode D 20  involving a large amount of recovery current is employed. Due to this, operational waveforms of this example are the same as those of  FIG. 10  with the current D 20   i  of the clamp diode D 20  of  FIG. 10  being replaced with a current Ibc (Q 20 ) of the p-n junction diode between the base and collector of the transistor Q 20 . Accordingly, operation of this example is the same as that explained with reference to  FIG. 10 .  
         [0139]     The additional buffer circuits of the second embodiment of  FIG. 12  are capable of driving the switches Q 10  and Q 11  even if they are of large capacity.  
         [0140]     In  FIG. 12 , the clamp diodes D 20  and D 22  may be removed. In this case, the same operation as that with the clamp diodes D 20  and D 22  involving a large amount of recovery current is achieved. Namely, the same operational waveforms as those shown in  FIG. 11  will be demonstrated, provided that the current D 20   i  of the clamp diode D 20  of  FIG. 11  is replaced with a current Ibc (Q 20 ) of the p-n junction diode between the base and collector of the transistor Q 20  and the current D 22   i  of the clamp diode D 22  of  FIG. 11  is replaced with a current Ibc (Q 22 ) of the p-n junction diode between the base and collector of the transistor Q 22 . Operation of this configuration is the same as that explained with reference to  FIG. 11 .  
       THIRD EMBODIMENT  
       [0141]      FIG. 13  is a circuit diagram showing a DC converter according to the third embodiment of the present invention. Parts of the third embodiment that are different from those of the related art of  FIG. 3  will be explained.  
         [0142]     A transformer Td has a primary winding (having the number of turns of n 1 ), a first secondary winding S 1  (having the number of turns of n 2 ) very loosely coupled with the primary winding P 1 , a second secondary winding S 2  (having the number of turns of n 3 ) loosely coupled with the primary winding P 1 , and a tertiary winding S 3  (having the number of turns of n 4 ) tightly coupled with the primary winding P 1 . The tertiary winding S 3  is connected in series with a resistor R 22 . Ends of a smoothing capacitor C 10  are connected to a series circuit of clamp diodes D 20  and D 21  and a series circuit of clamp diodes D 22  and D 23 . A first end of a resistor R 22  is connected to a node between the clamp diodes D 20  and D 21  and to the gate of a switch Q 10  through a buffer circuit BUF 20 . A first end of the tertiary winding S 3  is connected to a node between the clamp diodes D 22  and D 23  and to the gate of a switch Q 11  through a buffer circuit BUF 21 . A second end of the resistor R 22  is connected to a second end of the tertiary winding S 3 .  
         [0143]     To turn on the switch Q 10  when a switch Q 1  is ON, the winding start of the tertiary winding S 3  is connected through the resistor R 20  and buffer circuit BUF 20  to the gate of the switch Q 10 . To turn on the switch Q 11  when the switch Q 1  is OFF, the winding end of the tertiary winding S 3  is connected through the buffer circuit BUF 21  to the gate of the switch Q 11 .  
         [0144]     The smoothing capacitor C 10  provides an output voltage Vout that is lower than a voltage generated by the tertiary winding S 3  and is used as a clamp voltage source. The clamp voltage source may be a separate power source.  
         [0145]     The clamp diodes D 20 , D 21 , D 22 , and D 23  clamp a winding voltage generated by the tertiary winding S 3  at the output voltage Vout, i.e., the clamp voltage source. The resistor R 22  limits a clamp current passing through the clamp diodes when the winding voltage is clamped at the clamp voltage.  
         [0146]     Recovery currents of the clamp diodes D 20 , D 21 , D 22 , and D 23  are used so that voltage signals clamped by the clamp diodes D 20 , D 21 , D 22 , and D 23  may drive the gates of the switches Q 10  and Q 11  serving as synchronous rectifiers. This operation extends the ON period of each synchronous rectifier and improves the efficiency of synchronous rectification. More precisely, the clamp diodes D 20  and D 21  clamp a signal D 21   v  that serves as a drive signal for driving the gate of the switch Q 10 . The clamp diodes D 22  and D 23  clamp a signal D 23   v  that serves as a drive signal for driving the gate of the switch Q 11 .  
         [0147]     Driving the synchronous rectifiers with the tertiary winding S 3  realizes stable operation of the synchronous rectifiers and improves efficiency because the synchronous rectifiers are never repeatedly turned on and off to cause chattering due to oscillation caused by recovery currents of rectifying diodes that are connected in parallel with the synchronous rectifiers.  
         [0148]     The tertiary winding S 3  is tightly coupled with the primary winding P 1 , and therefore, has the same voltage waveform as that of the primary winding P 1 . The DC converter according to the third embodiment, therefore, can extend the ON period of each synchronous rectifier and improve the efficiency thereof. The DC converter employs the tertiary winding S 3  tightly coupled with the primary winding P 1 , to drive the synchronous rectifiers, i.e., the switches Q 10  and Q 11 . This prevents the synchronous rectifiers from repeatedly turning on and off to cause chattering due to oscillation caused by recovery currents of the rectifying diodes D 10  and D 11  connected in parallel with the synchronous rectifiers. Namely, the DC converter of this embodiment can stably drive the synchronous rectifiers and improve the efficiency thereof.  
         [0149]     Compared with the DC converter of  FIG. 3 , the DC converter of  FIG. 13  has no CR snubber circuits (the resistors R 20  and R 21  and capacitors C 20  and C 21 ).  
         [0150]      FIG. 14  is a view showing the structure of the transformer Td installed in the DC converter according to the third embodiment, and  FIG. 15  is an equivalent circuit diagram showing the transformer of  FIG. 14 . In  FIG. 14 , the transformer Td has a core  30  having a rectangular external shape. The core  30  has spaces  35   a  and  35   b  extending in parallel to each other in a longitudinal magnetic path direction, to form magnetic paths  32   a,    32   b,  and  32   c.  Around a core part  30   a  of the core  30 , the primary winding P 1 , tertiary winding S 3 , and second secondary winding S 2  are wound adjacent to each other. This produces a slight leakage inductance (LS of  FIG. 15 ) between the primary winding P 1  plus the tertiary winding S 3  and the second secondary winding S 2 . The core  30  has a path core  30   c  and a gap  31 . Around a peripheral core, the first secondary winding S 1  is wound. The path core  30   c  works to very loosely couple the primary winding P 1  and first secondary winding S 1  with each other, thereby increasing a leakage inductance (L 1  of  FIG. 15 ).  
         [0151]     On the peripheral core and between the primary winding P 1  and the second secondary winding S 2 , a recess  30   b  is formed. The recess  30   b  reduces the sectional area of a part of a magnetic path of the core so that only the part may saturate. This configuration can reduce a core loss. The part that saturates is used as a saturable reactor (LH of  FIG. 15 ). Forming the recess  30   b  at a part of the core  30  where the first secondary winding S 1  is wound results in saturating the part, increasing an excitation current, and producing a voltage resonance.  
         [0152]      FIG. 16  is a timing chart showing signals at various parts of the DC converter of the third embodiment. Basic operation of the third embodiment is substantially the same as that of the related art shown in  FIG. 3 , and operation of the tertiary winding S 3  and clamp diodes D 20  to D 23  is substantially the same as that of the DC converter of  FIG. 8 . Accordingly, the detailed explanation of the operation of the third embodiment is omitted.  
         [0153]     If the clamp diode D 20  of the third embodiment involves a large amount of recovery current, operational waveforms thereof will be similar to those of  FIG. 10 . In this case, a period in which the clamp diode D 20  passes a recovery current is from t 7  to t 8   a . During this period, a voltage B 20   v  of the buffer circuit BUF 20  is substantially equal to the clamp voltage, to delay the OFF timing of a gate signal to the switch Q 10  until t 8   a . As a result, the ON period of the switch Q 10  is extended longer than that of  FIG. 9 , to further improve the efficiency of the DC converter.  
         [0154]     If the clamp diodes D 20  and D 22  each involve a large amount of recovery current, operational waveforms thereof will be like those of  FIG. 11 . In this case, a period in which the clamp diode D 20  passes a recovery current is from t 7  to t 8   a . During this period, the voltage B 20   v  of the buffer circuit BUF 20  is substantially equal to the clamp voltage. A period in which the clamp diode D 22  passes a recovery current is from t 2  to t 3   a . During this period, a voltage B 21   v  of the buffer circuit BUF 21  is substantially equal to the clamp voltage. As a result, the OFF timing of a gate signal to the switch Q 10  is delayed until t 8   a , and the OFF timing of a gate signal to the switch Q 11  is delayed until t 3   a . With them, the ON periods of the switches Q 10  and Q 11  are extended longer than those of  FIG. 9 , to further improve the efficiency of the DC converter.  
         [0155]     The buffer circuits BUF 21  and BUF 20  may employ transistors as shown in  FIG. 12 , and in addition, the clamp diode D 20  may be omitted. In this case, when the winding start of the tertiary winding S 3  is at positive potential, the switch Q 10  is ON, the switch Q 11  is OFF, a current to the tertiary winding S 3  passes through a path along S 3 , R 20 , Q 20  (base), Q 20  (collector), C 10 , D 23 , and S 3 .  
         [0156]     Since the current passes through a p-n junction of the transistor Q 20  from the base to the collector thereof, recovery is slow as if the clamp diode D 20  involving a large amount of recovery current is employed. In this case, the same operational waveforms as those of  FIG. 10  will appear. The additional buffer circuits are effective when the synchronous rectifiers are of large capacity.  
         [0157]     The clamp diodes D 20  and D 22  may be omitted. In this case, the same operation as that with the clamp diodes D 20  and D 22  involving a large amount of recovery current is achieved. Namely, the same operational waveforms as those of  FIG. 11  will appear.  
         [0158]     In summary, a DC converter according to the present invention employs clamp diodes that clamp a voltage generated by a tertiary winding of a transformer with the use of a voltage source that supplies a voltage lower than the voltage generated by the tertiary winding. The clamp diodes provide voltage-clamped signals to drive synchronous rectifiers. This configuration extends the ON period of each synchronous rectifier and improves the efficiency thereof.  
         [0159]     By driving the synchronous rectifiers with the tertiary winding, the DC converter prevents the synchronous rectifiers from repeatedly turning on and off to cause chattering due to oscillation caused by recovery currents of rectifying diodes that are connected in parallel with the synchronous rectifiers. The DC converter, therefore, can operate stably and improve efficiency.  
         [0160]     The present invention is applicable to switching power sources such as DC-DC converters and AC-DC converters.  
         [0161]     This application claims benefit of priority under 35USC §119 to Japanese Patent Applications No. 2005-051706, filed on Feb. 25, 2005, the entire contents of which are incorporated by reference herein. Although the invention has been described above by reference to certain embodiments of the invention, the invention is not limited to the embodiments described above. Modifications and variations of the embodiments described above will occur to those skilled in the art, in light of the teachings. The scope of the invention is defined with reference to the following claims.