Abstract:
A digital-to-digital converter is arranged to provide &#34;decimated&#34; output samples at rate f 0 , each of which represent a group of input samples received at a rate m times greater. Each output is generated using overlapped triangularly weighted accumulation on an interval including 2m preceding input samples. The samples near the beginning and end of each accumulation interval receive the smallest weight, and the samples at the middle of the interval receive the greatest weight. The converter is achievable in integrated circuit form using first and second serially connected accumulators, the first accumulating m input samples without weighting and the second being used to weight the samples so that the first receives m times the weight of the last sample. The output of the first accumulator is increased in scale by the factor &#34;m&#34; and the output of the second accumulator subtracted therefrom. The difference is delayed so that the next m samples may be accumulated. The output of the second accumulator is then combined with the delayed subtractor output to yield the desired overlapped, triangularly weighted accumulation.

Description:
TECHNICAL FIELD 
     The present invention relates to code converters generally and, in particular, to a digital-to-digital converter in which a sequence of multi-bit words sampled at a rate mf 0  is converted to a corresponding series of multi-bit words at a rate f 0  using overlapping, triangular weighted accumulation. 
     BACKGROUND OF THE INVENTION 
     For reasons of efficiency, ease of implementation and noise reduction, it has been suggested that an analog-to-digital converter include an input stage in which the analog signal is converted to a coarsely quantized digital representation at a sample rate many times greater than the Nyquist rate. Thereafter, the digital representation is &#34;decimated&#34; by combining groups of high rate samples into corresponding digital values which occur at the desired slower rate. This output may then be used directly, or filtered further prior to application to a utilization device. A general description of oversampled A/D encoding, and its features and advantages, is contained in an article by D. J. Goodman entitled &#34;The Application of Delta Modulation to Analog-to-Digital PCM Encoding&#34;, Bell System Technical Journal, Vol. 48, February 1969, pp. 321-343. 
     In the decimation process described above, due care must be taken to reduce or eliminate the noise (distortion) introduced during the coarse quantization, and to avoid aliasing by which noise is introduced into the final digital signal during subsequent processing. One technique for decimation filtering is a unique weighted accumulation procedure described in U.S. Pat. No. 4,032,914 issued to J. C. Candy and Y. Ching (Candy being one of the inventors herein) on June 28, 1977. In that patent, the m coarsely quantized sample values for each desired output sample interval are combined using triangular or trapezoidal weighting. By this, it is meant that sample values near the beginning and end of the interval are given lower weight, relative to value, near the middle of the interval. Thus, in triangular weighting for m=8 samples X 0 , X 1 . . . X 7 , a summation might be taken such that the output is proportional to 0X 0  +1X 1  +X 2  +3X 3  +4X 4  +3X 5  +2X 6  +1X 7 . In trapezoidally weighted accumulation, the same eight samples might be weighted such that the output varies with 0 X   0  +1X 1  +2X 2  +3X 3  +3X 4  +3X 5  +2X 6  + 1X 7 . If the coefficient values are plotted against time for the two examples given, the first would form a triangle and the second a trapezoid. 
     The technique just described, implemented using a serially connected pair of accumulators, is somewhat successful in reducing quantizing noise, as desired. However, aliasing effects still persist, to a degree, and the frequency response characteristic of the circuit does not meet all system requirements. Accordingly, it is the broad object of the present invention to provide an improved digital-to-digital converter or decimator having desired transfer characteristics. Specific objects include reduction in aliasing and simplification of circuit implementation, particularly using integrated circuit fabrication techniques. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a digital-to-digital converter (decimating filter) is arranged to receive a series of input samples at rate mf 0   and to generate a corresponding series of output samples at rate f 0 , using overlapping triangular accumulation. By this it is meant that to generate an output sample for each group of m input samples the n=2m samples X 0 , X 1 . . . X n-2 , X n-1 , are accumulated such that the first sample X 0  is given no weight, the second and last samples X 1  and X n-1  are given least weight, the next inner samples X 2  and X n-2  are given increased weight, and the middle sample X m  is given the most weight. Of these n samples, m are in the next interval and m are in the previous interval. The overlapping triangular accumulation is achieved by applying the input samples to a series connected pair of accumulators, the first of which sums each group of m samples without weighting, and the second of which sums the samples in the first accumulator such that the first sample receives m times the weight of the last, and intermediate samples receive proportional weights between those extremes. 
     The output of the second accumulator is subtracted from a version of the output from the first accumulator which has been increased in scale by a factor of m, and the difference is delayed by one interval of m samples. The desired output is obtained by combining the output of the sECMjd accumulator with the output of the delay means. This implementation achieves the desired transfer characteristics with an arrangement that is simple and easily impleDEnted in integrated circuit form. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more fully appreciated by consideration of the following detailed description when read in light of the accompanying drawing in which: 
     FIG. 1 is a block diagram of a prior art analog-to-digital encoder which uses a decimator or digital-to-digital code converter of the type provided by the present invention; 
     FIG. 2 is a diagram illustrating ordinary triangularly weighted accumulation heretofore used in prior art decimators; 
     FIG. 3 illustrates overlapped triangular weighting used in accordance with the present invention; 
     FIG. 4 is another illustration of overlapped, triangular accumulation; 
     FIGS. 5 and 6 compare the transfer functions of prior art ordinary triangular accumulation (FIG. 5) and overlapped triangular accumulation (FIG. 6) in accordance with the present invention; 
     FIG. 7 is a block diagram of a digital-to-digital converter or decimator constructed in accordance with the principles of the present invention; and 
     FIGS. 8-12 graphically illustrate weighted sums computed by various functional portions of the decimator of FIG. 7. 
    
    
     DETAILED DESCRIPTION 
     One primary use for the present invention is put in perspective by reference to FIG. 1, which shows an embodiment of an oversampled voiceband analog-to-digital converter in block diagram form. In this embodiment, an analog input signal I(t) having a frequency range of 0-4 KHZ is applied to an interpolating modulator 101 arranged to produce a series of 9-bit output words at a rate of 256×10 3  words per second (256 KW/s). The internal arrangement of modulator 101 may be identical to coder 19 of the above-cited U.S. Pat. No. 4,032,914, wherein a stored error value (for a previous sample) is coarsely quantized, subtracted from the input, and integrated to form the error value for the next sample. 
     The output of interpolating modulator 101 is applied to decimator 102, which forms the subject of the present invention. The purposes of decimation in this embodiment is to provide 15-bit output words at a rate of 32 KW/s, which means that one output is provided for every eight input samples. In this case, m=8 and n=16. Decimation does not simply involve dropping 7 and using each 8 th  input word to form each output word. Instead, in accordance with the invention, and still using the frequencies of present example, each output word is formed as a weighted sum of the preceding 16 input words. 
     The output of decimator 102 is applied to a low pass filter 103, usually implemented as a fourth or higher order digital filter, in cascade with a digital high pass filter 104, both of which operate on 16-bit words at the Nyquist rate of 8 KW/s. By interposing decimator 102 in the A/D encoder, the operating speed and power requirements of filters 103 and 104 are advantageously reduced, enabling practical implementation using integrated circuit technology. 
     In the prior art decimator circuit shown in FIG. 1 of the above-cited U.S. Pat. No. 4,032,914, triangularly weighted accumulation is used to obtain each output sample from the preceding m input samples, where the input frequency mf 0  is m times greater than the output frequency f 0 , and m is assumed to be even. FIG. 2 shows a series of input samples X 0 , X 1 , X 2 , X 3 . . . which occur every 1/mf 0  second, every m th  sample, X m , X 2m , X 3m , . . . shown crosshatched, constituting the end of an accumulation interval of 1/f 0  seconds. The weighting factors A 0  -A m-1  used to weight corresponding samples X 0  -X m-1  are shown graphically in FIG. 2 to form a triangular shape, such that factor A 0  is zero, the factors A 1  and A m-1  for samples at the beginning and end of each interval are smallest and factor A m/ .sbsb.2 at the middle of each interval is the largest, and the intervening factors have proportionally tapering values. The value of output sample Y 0  is the weighted sum of the input samples in the interval, such that Y 0  =ΣA 0  X 0  +A 1  X 1 . . . A m-1  X m-1 . The next output sample Y 1  is similarly weighted, so that Y 1  =ΣA 0  X m  +A 1  X m+1 . . . A m-1  X 2m-1 . Using integral values for the weighting coefficients of A 0  =0, A 1  =A m  =1, A 2  =A m-1  =2, A 3  =A m-2  =3, . . . A m/ .sbsb.2 =m/2, the decimator output Y i  (i=0, 1, 2, 3 . . . ) is expressed as: ##EQU1## 
     The advantages of triangularly weighted accumulation of the type just described, as well as other details concerning its mathematical basis and implementation are discussed in a paper by J. C. Candy et al entitled &#34;Using Triangularly Weighted Interpolation to Get 13-Bit PCM From A Sigma-Delta Modulator&#34;, IEEE Transactions on Communcations, November 1976, pp. 1268-1275. In the title of that paper, the term &#34;interpolation&#34; is used synonomously with &#34;accumulation&#34;, it being noted that both terms are used to identify a characteristic of converters of the type being described herein. 
     While triangularly weighted accumulation is nearly ideal for reducing the quantization noise produced by modulator 101 of FIG. 1, the aliasing problem still exists. As shown in FIG. 5, the transfer characteristic curve 501 for triangular accumulation with an input frequency of f 1  of 256 KW/s and an output frequency of f 2  of 32 KW/s is mathematically expressed as: 
     
         |H(f)|=|sinc(f/2f.sub.2)/sinc(f/f.sub.1).vertline..sup.2,                                                  (2) 
    
     and exhibits an attenuation of about 7 dB at f=32 KW/s. When the output of the decimator 102 is thereafter subsampled at 32 KW/s, in filters 103 and 104, any noise in the band around 32 KW/s is &#34;folded&#34; around and falls within the baseband, causing distortion. This problem is alleviated, in accordance with the present invention, by utilizing overlapped triangular accumulation, described more fully below. For this type of accumulation, the transfer characteristic curve 601 in FIG. 6 is mathematically expressed as: 
     
         H(f)=|sincf/f.sub.2 /sincf/f.sub.1 |.sup.2, (3) 
    
     and exhibits very high attenuation near 32 KW/s, producing little or no aliasing after subsequent subsampling. 
     FIGS. 3 and 4 graphically illustrate overlapped triangular accumulation in accordance with the present invention, using a scale enabling easy comparison with FIG. 2. The input samples X 0 , X 1 , X 2 . . . are the same, occurring at intervals of 1/mf 0  seconds, and the output pulses Y 0 , Y 1 , Y 2 . . . occur every 1/f 0  seconds. However, twice as many input samples are used to make up the accumulated value to which each output value is proportional, and each of the input samples contributes to two output samples. Specifically, the first output sample Y 0  is formed using the summation: 
     
         Y.sub.0 =A.sub.0 X.sub.0 +A.sub.1 X.sub.1 +A.sub.2 X.sub.2 +. . . +A.sub.(2m-1) X.sub.(2m-1).                               (4) 
    
     The next output same Y 1  is formed by summing: 
     
         Y.sub.1 =A.sub.0 X.sub.m +A.sub.1 X.sub.m+1 +A.sub.2 X.sub.m+2 +. . . +A.sub.(2m-1) X.sub.(3m-1).                               (5) 
    
     Thus, each output sample uses inputs from two sample intervals, and each input sample is used twice. For integral coefficient values, A 0  -A n-1  are as follows: ##EQU2## Again, it is to be noted that n=2m. 
     FIG. 4 also illustrates the overlapped, triangular shaped weighting used in accordance with the present invention. The weighting coefficients A 0 , A 1  . . . A m  . . . A 2m-1  form a series of triangles 401 through 404 which overlap each other such that each input sample will be used as part of two accumulations to form two output samples. 
     The general expression for the output samples Y i  (i=0, 1, 2, . . . ) of a decimator using overlapped triangular accumulation with the foregoing coefficients is: ##EQU3## For an input sample rate mf 0  of 256 KHZ, where m=8,  the z-transform of the decimator is:  and the corresponding frequency response is: ##EQU4## 
     When the decimator is cascaded with a modulator having a transfer function: 
     
         H.sub.m (f/f.sub.0)=|sinc(f/f.sub.0)|,   (10) 
    
     the overall transfer function becomes: ##EQU5## At 28 and 36 KHZ resampling, equation (11) yields an overall response of -34.1 and -38.3 dB, respectively, assuring adequate protection against aliasing. 
     For input samples of frequency mf 0  and a desired output frequency of f 0 , a block diagram of a decimator arranged to accumulate 2m input samples using overlapped, triangular weighting in accordance with the present invention is shown in FIG. 7. The circuit of FIG. 7 preferably uses parallel arithmetic and comprises four adders 701 through 704, four registers 711 through 714, each holding one sample word, and a multiply-by-m circuit 715 that can simply be a shift circuit when m is a power of 2 (e.g., a 3-bit shift for m=8). Adder 701 together with register 711 and adder 702 with register 712 each perform an accumulate and dump function. The registers 711 and 712 are clocked at mf 0  and cleared at f 0  KHZ, under control of a clock source, not shown. Registers 713 and 714 are clocked at f 0  KHZ at the same time registers 711 and 712 are cleared. Register 713 provides a delay equal to the interval 1/f 0  between output pulses, and register 714 simply acts as an output holding register. 
     The operation of the decimator of FIG. 7 is easily understood from the expressions for signals at the points A, B, C and D in FIG. 7 at the time the f 0  clock is applied. Namely, ##EQU6## D i  is the desired output, as seen from equation (7). 
     The operation of the decimator of FIG. 7 can be further understood by considering the operation of its functional parts in connection with the diagrams of FIGS. 8 through 12. Adder 701 together with register 711 constitute an &#34;unweighted&#34; accumulator. The register is cleared at the beginning of each m-sample interval by a pulse on line 720 at frequency f 0 . Each time a clock pulse at frequency mf 0  is applied on line 721, an input sample is added to the present contents of register 711 and the sum read into and stored in the register. This procedure is repeated for each of the m input samples occurring between each output sample. All of the sample values are treated equally, essentially being multiplied by a unity weight factor, as illustrated in FIG. 8. 
     By applying the output of the first accumulator (on line 730) to a second accumulator (consisting of adder 702 and register 712), the accumulation performed on the input samples becomes non-uniformly weighted. Register 712 is cleared at the beginning of each m-sample interval by a pulse on line 722 at frequency f 0 . Each time a clock pulse at frequency mf 0  is applied on line 723, the contents of register 712 are added to the output of the first accumulator, and the results read into and stored in the register. The accumulation is repeated m times, at the occurrence of each input sample. Thus, the first sample in each interval receives m times the weight of the last sample in the interval, and intermediate samples are uniformly distributed or proportionately weighted. The weighting progression of the sample in each interval, from m, m-1, m-2 . . . 1, is illustrated in FIG. 9. 
     The magnitude of the output from the first accumulator (taken from adder 701 on line 730) is increased &#34;m&#34; times by multiplier circuit 715. This may be accomplished by a simple shift of the multibit value on line 730 when m is a power of 2. The output from multiplier circuit 715, shown in FIG. 10, is similar to that shown in FIG. 8, but &#34;m&#34; times greater. 
     The output of the second accumulator (taken from adder 702 on line 731) is subtracted from the output of multiplier circuit 715, using subtractor 703. The result, shown in FIG. 11, is nonlinear accumulation, wherein the final sample has m-1 times the weight of the second sample, and intermediate samples are proportional, running from 1, 2, 3 . . . m-1. The first sample in the interval has zero weight. 
     The output of subtractor 503 is held or delayed for the time interval 1/f 0  between successive output samples by register 513 which receives clock pulses on line 724 at the rate f 0 . This delay has the effect of &#34;freezing&#34; the subtractor output (FIG. 11) such that when the output of register 713 is combined in adder 705 with the output from the second accumulator on line 731 the former includes m samples in the first interval and the latter includes m samples in the next interval. As shown in FIG. 12, the overall accumulation is triangularly weighted, samples at the beginning and end of the accumulation period receiving least weight and samples near the middle of the period receiving most weight. the samples lying between the extremes are uniformly distributed or proportionately weighted, as is desired. 
     The output of adder 704 may be used directly or held between each output sample in register 514, which receives clock pulses on line 725 at the output rate f 0 . The output from the decimator on line 740 may also be scaled down, if desired, to normalize the output with respect to the input level. Advantageously, if the value of m is a power of 2, the sum of the weighting coefficients will likewise be a power of 2, and a simple shift may be used to accomplish the scale change. For example, if m=8, the coefficients are: ##EQU7## The sum of the coefficients is 64, and a shift of 5-bit positions will normalize the output of the accumulator with respect to the input. 
     Various modifications and adaptations of the present invention may be made by those skilled in the art, and for this reason it is intended that the invention be limited only by the appended claims.