Abstract:
A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a circuit for translating a voltage level. Such a circuit may be used in input/output interfaces of an integrated circuit. Indeed, in integrated circuits, the data may have very low voltage levels, which may need to be increased for the processing by the circuits external to the integrated circuits, which operate under high voltages. 
         [0003]    2. Description of the Related Art 
         [0004]      FIG. 1  shows a conventional voltage-level translator circuit  1 . 
         [0005]    Circuit  1  comprises an input data-IN receiving input data from an integrated circuit. The data are digital data, with their two states respectively corresponding to a zero voltage (ground GND) and to a positive voltage VDD. Input data-IN is connected to the gate of an NMOS transistor M 0 . The source of transistor M 0  is connected to a node M connected to ground GND. The drain of transistor M 0  is connected to a node A. 
         [0006]    Circuit  1  also comprises a PMOS transistor M′ 0  having its drain connected to node A. The source of transistor M′ 0  is connected to a node N connected to a supply terminal having a voltage V+ higher than voltage VDD. The gate of transistor M′ 0  is connected to a node B. 
         [0007]    Circuit  1  also comprises an input  data -IN which receives inversion data  data  that are inversions of the input data. Input  data -IN drives the gate of an NMOS transistor M 1 . The source of transistor M 1  is connected to node M. The drain of transistor M 1  is connected to node B. 
         [0008]    Circuit  1  also comprises a PMOS transistor M′ 1  having its drain connected to node B. The source of transistor M′ 1  is connected to node N. The gate of transistor M′ 1  is connected to node A. 
         [0009]    Node B is connected to an output DATA-OUT which issues output data corresponding to the input data. Output data have a high level, also called high state or state or level  1 , corresponding to voltage V+ and a low level, also called low state or state or level  0 , corresponding to zero. Node A is connected to an output  DATA -OUT which provides the inverse of output data. 
         [0010]    The operation of the circuit of  FIG. 1  will be discussed in relation with  FIGS. 2   a  to  2   f  which schematically illustrate various timing diagrams of variables involved in circuit  1 . 
         [0011]    At time t=0, the input data ( FIG. 2   a ) are at a low state and the voltage at input data-IN is equal to zero. Transistor M 0  is off and, neglecting a leakage current, the drain-source current IDS(M 0 ) running through transistor M 0  ( FIG. 2   d ) is zero. At time t=0, data  data  ( FIG. 2   b ) are at a high state and the voltage at input  data -IN is equal to voltage V DD . Transistor M 1  is then on and voltage V B  at node B is (substantially) zero ( FIG. 2   e ). The voltage at node B being zero, transistor M′ 0  is on and voltage V A  at node A ( FIG. 2   c ) is equal to V+. The gate of transistor M′ 1  being at voltage V+, transistor M′ 1  is off and the drain-source current IDS(M 1 ) running through transistor M 1  ( FIG. 2   f ) is zero (neglecting its leakage current). 
         [0012]    At time t=t 1 , the input data switch from the low state to the high state and data  data  switch from the high state to the low state. Transistor M 0  turns on and the voltage at node A will decrease. This decrease is not instantaneous and the voltage at node A reaches 0 at time t′ 1 . Difference t′ 1 -t 1  corresponds to the switching time and, between times t 1  and t′ 1 , current IDS(M 0 ) increases, crosses a threshold, then decreases back to recover value 0 at time t′ 1 . As concerns node B, transistor M 1  turns off at time t 1  and the voltage at node B rises from the time when transistor M′ 1  starts conducting. At the end of the transition, at time t′ 1 , node A is 0, node B is at V+, transistors M 0  and M′ 1  are on, and transistors M 1  and M′ 0  are off. 
         [0013]    At time t 2 , the input data switch from state  1  to state  0  and data  data  switch from state  0  to state  1 . Transistor M 0  turns off and transistor M 1  turns on. The voltage at node A increases to reach value V+ at time t′ 2  and the voltage at node B decreases to reach value 0 at time t′ 2 . During the transition, the current in transistors M 1  and M′ 1  first increases, then decreases, while the voltage at node B decreases and the voltage at node A increases. After time t′ 2 , transistors M 1  and M′ 0  are on, and transistors M 0  and M′ 1  are off. 
         [0014]    The circuit of  FIG. 1  has disadvantages. The current tendency in the art is to have increasingly small voltages VDD, which results in increasing switching times. Thus, when voltage VDD comes close to the threshold of transistors M 0  and M 1 , said transistors operate with a low gate/source voltage, which limits their saturation current and the state of nodes A and B cannot change fast. 
         [0015]    A solution to decrease switching times would be to increase the saturation current of transistors M 0  and M 1  by increasing the size of transistors M 0  and M 1 . However, in this case, the required silicon surface area risks being incompatible with the desired application. Further, this solution would increase the stray capacitance and the leakage current of transistors M 0  and M 1 . 
       BRIEF SUMMARY 
       [0016]    One embodiment provides a level translator circuit using a small silicon surface area, a circuit enabling short switching times, a circuit with a small stray capacitance, a circuit requiring no external biasing, a circuit with transistors likely to have small leakage currents, a circuit enabling to work at low voltage VDD, a circuit enabling to work with strong differences between VDD and V+, etc. 
         [0017]    Thus, one embodiment provides a voltage-level translator circuit comprising:
       at least one first MOS transistor, of a first type, having a gate capable of receiving input data likely to vary between a first voltage level and a second voltage level, smaller than the first voltage level, having its source coupled to a first node and having its drain coupled to a second node;   at least one second MOS transistor, of the first type, having a gate capable of receiving the inverse of the input data, having its source coupled to the first node, and having its drain coupled to a third node;   at least one third MOS transistor, of the second type, having its gate coupled to the third node, having its source coupled to a fourth node, and having its drain coupled to the second node;   at least one fourth MOS transistor, of the second type, having its gate coupled to the second node, having its source coupled to the fourth node, and having its drain coupled to the third node,       
 
         [0022]    the third node being capable of issuing output data corresponding to the input data and the second node being capable of issuing the inverse of the output data, the output data being likely to vary between a third voltage level and the second voltage level, the third voltage level being greater than the first voltage level; 
         [0023]    wherein the circuit comprises:
       at least one first and one second branches between the second node and the fourth node, the second branch exhibiting a smaller impedance than the first branch;   at least one third and one fourth branches between the third node and the fourth node, the fourth branch exhibiting a smaller impedance than the third branch; and   a selection unit capable of activating the second branch and of deactivating the fourth branch before the second node switches from the second voltage level to the third voltage level and capable of deactivating the second branch and of activating the fourth branch before the second node switches from the third voltage level to the second voltage level.       
 
         [0027]    In one embodiment the first MOS transistor type corresponds to NMOS transistors and the second transistor type corresponds to PMOS transistors, and the first node is coupled to ground and the fourth node is coupled to a positive supply voltage. 
         [0028]    In one embodiment the selection unit is coupled to the second node and/or to the third node. 
         [0029]    In one embodiment the second or the fourth branch comprises a PMOS transistor with a high saturation current. 
         [0030]    In one embodiment the first or the third branch comprises a PMOS transistor with a low saturation current. 
         [0031]    In one embodiment the first or the third branch comprises a resistor. 
         [0032]    In one embodiment the circuit comprises: 
         [0033]    a first and a second paths connected in parallel between the second and the fourth node, the first path comprising a first PMOS transistor series-connected with a high-impedance element and the second path comprising a second PMOS transistor series-connected with a low-impedance element; 
         [0034]    a third and a fourth paths connected in parallel between the third and the fourth node, the third path comprising a third PMOS transistor series-connected with a high-impedance element and the fourth path comprising a fourth PMOS transistor series-connected with a low-impedance element. 
         [0035]    In one embodiment the selection circuit comprises one or several logic gates and inverters. 
         [0036]    Specific embodiments will be discussed in detail in the following non-limiting description in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0037]      FIG. 1 , previously described, shows a conventional structure of a voltage level translator circuit. 
           [0038]      FIG. 2 , previously described, shows timing diagrams  2   a  to  2   f  for explaining the operation of  FIG. 1 . 
           [0039]      FIG. 3  shows one embodiment of a translator circuit. 
           [0040]      FIGS. 4 to 6  show other embodiments of a translator circuit. 
           [0041]      FIG. 7  schematically shows a selection unit. 
       
    
    
     DETAILED DESCRIPTION 
       [0042]      FIG. 3  shows a circuit  10  illustrating one embodiment. 
         [0043]    In  FIG. 3 , circuit  10  comprises an NMOS transistor M 0  and an NMOS transistor M 1  of same structure and of same operation as in the circuit of  FIG. 1 . Circuit  10  also comprises, as in  FIG. 1 , nodes A, B, M, and N. Generally, any reference letter or numeral common to  FIGS. 1 and 3  corresponds to element of same type and of same function, which will not be specifically described again. 
         [0044]    In  FIG. 3 , circuit  10  further comprises a PMOS transistor M″ 0  having its source connected to node N and having its drain connected to a node C. The gate of transistor M″ 0  is connected to node B. Circuit  10  also comprises a PMOS transistor M 2  having its source connected to node C and its drain connected to node A. The gate of transistor M 2  is connected to data input data-IN. Circuit  10  also comprises a PMOS transistor M 3  having its source connected to node C and its drain connected to node A. The gate of transistor M 3  is connected to a selection unit  20 . As will be seen hereafter, transistor M 2  corresponds to a high-impedance branch and transistor M 3  corresponds to a low-impedance branch, transistor M 2  having a low saturation current and transistor M 3  having a high saturation current. 
         [0045]    In  FIG. 3 , circuit  10  also comprises a PMOS transistor M″ 1  having its source connected to node N and having its drain connected to a node D. The gate of transistor M″ 1  is connected to node A. Circuit  10  also comprises a PMOS transistor M 4  having its source connected to node D and having its drain connected to node B. The gate of transistor M 4  is connected to inverse data input  data -IN. Circuit  10  also comprises a PMOS transistor M 5  having its source connected to node D and having its drain connected to node B. The gate of transistor M 5  is connected to selection unit  20 . As will be seen hereafter, transistor M 4  corresponds to a high-impedance branch and transistor M 5  corresponds to a low-impedance branch, transistor M 4  having a low saturation current and transistor M 5  having a high saturation current. 
         [0046]    In the embodiment of  FIG. 3 , selection unit  20  is coupled, on the one hand, to data output DATA-OUT and, on the other hand, to inverse data output  DATA -OUT. As will be seen hereafter, selection unit  20  may be connected to a single one of these outputs. Selection unit  20  may also be connected to data input data-IN or to inverse data input  data -IN, or to both inputs simultaneously. 
         [0047]    A function of selection unit  20  is to control transistors M 3  and M 5 . Unit  20  is provided to turn on transistor M 3  and to turn off transistor M 5  when node A must switch from level  0  to level  1  and, accordingly, when node B must switch from level  1  to level  0 . Unit  20  is also provided to turn off transistor M 3  and turn on transistor M 5  when node A must switch from level  1  to level  0  (and node B must switch from  0  to  1 ). 
         [0048]    The practical forming of selection unit  20  is within the abilities of those skilled in the art based on the function to be implemented. For instance, unit  20  will be connected to at least one of terminal data-IN, DATA-OUT,  data -IN or  DATA -OUT, or to another circuit location, having a voltage in relation with one of the above terminals. Selection unit  20  will comprise one or several logic gates associated with combinational logic. For example, unit  20  will comprise detectors of the level of signals DATA and  DATA , as well as delay elements so that the level translator circuit has time to fully settle between two state switchings. The signals provided by the detectors of the level of DATA and  DATA  may be logically combined to generate the output signals of selection unit  20  to turn transistors M 3  or M 5  on or off. The level detectors and the delay elements may be formed by means of inverters. A possible diagram of selection unit  20  will be described in relation with  FIG. 7 . 
         [0049]    The operation of the circuit of  FIG. 3  will now be described. 
         [0050]    Assume that input data-IN is at level  0 . Transistor M 0  is off. Transistor M″ 0  is on. Transistor M 2  is on and node A is at level  1 . Transistor M 3  is indifferently on or off, selection unit  20  only having to provide for transistor M 3  to be off at the time when the input data switch to level  1  in one embodiment. When input data-IN is at level  0 , transistor M 1  is on. Transistor M″ 1  is off and node B is at level  0 . Transistor M 5  is indifferently on or off, selection unit  20  only having to provide for transistor M 5  to be turned on at the time when the input data switch to level  1  in one embodiment. Transistor M 4  is nearly off, but not totally since its gate is at a low voltage (VDD). 
         [0051]    At the time when the input data switch from level  0  to level  1  (from voltage  0  to voltage VDD), transistor M 0  turns on. Since the voltage (VDD) between the gate and the source of transistor M 0  is low and close to the threshold of transistor M 0 , the current running through transistor M 0  is low. Transistor M″ 0  is still on. Transistor M″ 0  is likely to provide a significant current since it operates with a high gate-source voltage, close to V+. 
         [0052]    The gate-source voltage of transistor M 2 , which remains on, is decreased by voltage VDD, which decreases its saturation current. Given that transistor M 2  has been designed to provide a low current, since the branch formed by transistor M 2  is provided to exhibit a high impedance, the current running through transistor M 2  is low. Transistor M 3  is off since it has been turned off before the input data switch to level  1  by selection unit  20 . 
         [0053]    Since transistor M 3  is off, transistor M 2  limits the current provided by transistor M″ 0 . Thus, the current flowing from node N to node A is smaller than what it would have been without the presence of transistors M 2  and M 3  and the voltage of node A reaches level  0  faster than in the absence of transistor M 2 . In an embodiment, transistor M 2  is sized so that the current that it conducts is as small as possible, while remaining greater than the leakage current of transistor M 0 . 
         [0054]    Regarding the circuit behavior at node B when the input data switch from level  0  to level  1 , transistor M 1  turns off. Transistor M″ 1  will rapidly turn on since the voltage at node A lowers rapidly. Transistor M 5  is on since it has been turned on by selection unit  20  before the data switch to level  1 . Transistors M″, and M 5  being likely to provide a significant current, the voltage at node B will increase rapidly and reach level  1  rapidly. Transistor M 4  turns on, but this transistor has little influence since it has a low saturation current. 
         [0055]    As a conclusion, the presence of transistor M 2 , that is, of a high-impedance branch between nodes A and C, has enabled the level of node A to decrease rapidly and the presence of transistor M 5 , that is, of a low-impedance branch between nodes B and D, has enabled node B to increase rapidly. Thus, the circuit of  FIG. 3  enables a fast transition when the data switch from level  0  to level  1 . 
         [0056]    The circuit behavior when the input data switch from level  1  to level  0  can be deduced from its behavior when the data switch from level  0  to level  1 . Thus, on switching of the input data from level  1  to level  0 , transistor M 0  turns off and transistor M 1  turns on. Transistor M″ 0  remains off and transistor M″ 1  remains on. Transistor M 4  is slightly conductive since its gate-source voltage is decreased by voltage VDD and transistor M 5  is off since it has been turned off before the switching to level  0  of the data by selection unit  20 . The current running through branch NB is limited by the fact for transistor M 5  to be off and the voltage at node B rapidly decreases, which causes a fast turning-on of transistor M″ 0 . Since transistor M 3  has been turned on by selection unit  20  before the switching to 0 of the data, transistors M″ 0  and M 3  provide a strong current which will enable node A to rapidly reach its high level (V+). Here again, the presence of the parallel high- and low-impedance paths has enabled a faster switching than in prior art. 
         [0057]    In one embodiment, transistor M 4  is sized so that the current that it conducts is as low as possible, while remaining greater than the leakage current of transistor M 1 . 
         [0058]    As a conclusion, the presence of the high-impedance branches between nodes A and C on the one hand and between nodes B and D on the other hand, associated with low-impedance branches likely to be activated or deactivated has enabled to decrease switching times. It should be noted that the high-impedance branches, in addition to limiting the saturation current of transistors M″ 0  and M″ 1 , may also be used to compensate for the leakage current of transistors M 0  and M 1  when these transistors are off. 
         [0059]    As for the low-impedance branches, they enable the flowing of the saturation current of transistors M″ 0  and M″ 1  when they are activated. 
         [0060]    Selection unit  20  may operate in various ways. What matters is for it to have adequately activated or deactivated the low-impedance branches between the end of a transition and the beginning of the next transition. 
         [0061]    In one embodiment, selection unit  20  acts on the low-impedance branches just after each transition. In this case, when, for example, node A has just switched to level  0  and node B has just switched to level  1 , selection unit  20  operates to turn on transistor M 3  and to turn off transistor M 5 , which will be operational for the next transition. Delays may be provided to ensure for the levels of nodes A and B to have properly settled. It may also be provided, knowing the data frequency, for selection unit  20  to operate just before each transition. 
         [0062]    It should be noted that transistors M 3  and M″ 0  (respectively M 5  and M″ 1 ) are not necessarily identical. Indeed, their gate-source voltage is not the same and transistors M 3  and M″ 0  (respectively, M 5  and M″ 1 ) may be designed to have the same saturation current. It should be noted that transistors M 2  and M 4  may have very low saturation currents, which may be of the same order of magnitude as the leakage currents of transistors M 0  and M 1 . Regarding voltages, it is known that, according to the current tendency, voltages within integrated circuits keep on decreasing (for example, they may currently be 0.9 volt) while the external circuit is provided for greater voltages (for example, from 1.8 volts to 5 volts). The transistors of the circuit of  FIG. 3  may be designed to withstand all the maximum voltages to which they may be submitted. A circuit according to one embodiment may be usable in a wide frequency range. For example, it is used for data frequencies ranging from less than 10 MHz to more than 500 MHz. 
         [0063]    Those skilled in the art may modify the circuit of  FIG. 3  without departing from the framework of the embodiment. 
         [0064]    Thus,  FIGS. 4 to 6  illustrate examples of modifications of  FIG. 3  which comprise other embodiments. 
         [0065]      FIG. 4  shows the portion of circuit  10  of  FIG. 3  located between nodes N and A on the one hand, and N and B on the other hand. In  FIG. 4 , a resistor R 1  located between nodes C and A replaces transistor M 2  of  FIG. 3 . Resistor R 1  plays the same role as transistor M 2  of  FIG. 3  (holding of node A to 1 (V+) by compensating for the leakage current of M 0 ; fast switching of node A to zero). Since resistor R 1  belongs to the high-impedance path, its ohmic value will preferably be high. Similarly, in  FIG. 4 , a resistor R 2 , preferably of high value, is located between nodes D and B. Resistor R 2  replaces transistor M 4  of  FIG. 3  and plays the same role. In  FIG. 4 , transistors M 3  and M 5  are of course controlled in the same way as in  FIG. 3 . 
         [0066]      FIG. 5  shows an embodiment in which the two parallel paths at high and low impedance are located between node N and a node E. Transistor M″ 0  is located between node E and node A. Similarly, two branches, one at low impedance and the other one at high impedance, are located between node N and a node F. Transistor M″ 1  is located between node F and node B. Of course, in  FIG. 5 , resistors R 1  and R 2  may be replaced with transistor M 2  and M 4  of  FIG. 3 . The operation of the circuit of  FIG. 5  is similar to that of  FIG. 3  and will not be described any further. 
         [0067]    In  FIG. 6 , the high and low impedance paths connect nodes N and A on the one hand, and node N and B on the other hand. Transistor M″ 0  is duplicated in a transistor M″ 0-1 , in series with transistor M 2 , and a transistor M″ 0-2 , in series with transistor M 3 . Transistors M″ 0-1  and M″ 0-2  both have their gate connected to node B. Symmetrically, node N is connected to node B by two paths in parallel, one containing a transistor M″ 1-2  in series with transistor M 5  and one comprising a transistor M″ 1-1  in series with transistor M 4 . 
         [0068]    Transistors M″ 0-1  and M″ 0-2  need not be identical. Transistor M″ 0-1  in series with transistor M 2  may be a resistive transistor (small value of ratio W/L) while transistor M″ 0-2  in series with transistor M 3  may have a low resistivity. 
         [0069]    Different variations and modifications will occur to those skilled in the art. In particular, according to the implementation of one embodiment, one or several of the transistors of the described circuits may be duplicated. Also, it is possible not to ground the low voltage level, node M then being connected to a voltage V−different from zero. As has already been indicated, selection unit  20  may be formed in various ways.  FIG. 7  provides an embodiment of unit  20 , which will be briefly described hereafter. 
         [0070]    In  FIG. 7 , selection unit  20  has an input  22  connected to terminal DATA-OUT of  FIG. 3 , and an input  24  connected to terminal  DATA -OUT. Input  22  is connected to an input of a two-input NAND gate  26 . Input  24  is connected to the second input of gate  26  via an inverter I 1 . The output of gate  26  drives three inverters in series I 2 , I 3 , and I 4 . The output of inverter I 4  is connected to a terminal  28 , which controls the gate of transistor M 5 . The output of inverter  14  is also connected to the input of an inverter  15 , having its output connected to a terminal  30  which controls the gate of transistor M 3 . In the circuit of  FIG. 7 , the propagation delay in NAND gate  26  and inverters I 2 , I 3 , and I 4  should be greater than the switching time of the level translator circuit. 
         [0071]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.