Abstract:
An apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. The apparatus generally includes a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal, a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock, and a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to the synchronization of multiple circuits or integrated circuit chips. In particular, the present invention relates to an apparatus and method for ensuring that multiple circuits or chips generate system clocks that are in phase with one another. 
     2. Related Art 
     A problem often arises when multiple circuits, or chips, or combinations thereof, are coupled together as a synchronized system, but are each driven by their own phase locked loop (PLL). If each circuit or chip requires the PLL output frequency to be divided down to a lower frequency to generate its operating (i.e., system) clock frequency, then the possibility exists that, after a reset, and the individual PLLs each acquire lock, the circuits or chips could start operating with clocks that are out of phase with each other. This problem may exist even when the PLLs of the individual circuits or chips are driven by the same input oscillator source. 
     The above-referenced problem is illustrated in greater detail with reference to FIGS. 1 and 2. 
     A system  10  comprising two chips  12 A,  12 B, each containing a PLL  14 A,  14 B, is illustrated in FIG.  1 . Each PLL  14 A,  14 B, is driven by a 30 MHz input clock signal  16  produced by a 30 MHz oscillator (not shown), and is configured to provide an output frequency of 120 MHz . If each chip  12 A,  12 B, has a required operating frequency (i.e., system clock) of 40 MHz , the output clock signal  18 A,  18 B, of each PLL  14 A,  14 B, must be divided by a factor of three in order to generate a system clock signal  20 A,  20 B, having the desired clock frequency. In this example, a divide-by-three circuit  22 A,  22 B, is provided in each chip  12 A,  12 B, to furnish the necessary frequency division. 
     After a reset signal  24  is provided to the PLLs  14 A,  14 B, each PLL  14 A,  14 B, will take some period of time to become locked. A typical system, e.g., system  10 , uses this lock indication to begin propagating the system clock signal  20 A,  20 B, to the internal logic of the chips  12 A,  12 B. Since both PLLs  14 A,  14 B, are driven by a common input clock signal  16 , the output clock signals  18 A,  18 B of the PLLs  14 A,  14 B, once locked, are guaranteed to be in phase. However, since the example system  10  includes a divide-by-three circuit  22 A,  22 B, on the output of each PLL  14 A,  14 B, the exact startup time of each divide-by-three circuit  22 A,  22 B, will affect the phase relationship of the resultant system clock signals  20 A,  20 B. The timing diagram shown in FIG. 2 illustrates how, if each PLL  14 A,  14 B, becomes locked at a slightly different time, the resultant system clock signals  20 A,  20 B, will be out of phase. 
     To compound this problem, some PLL configurations, based on the amount of jitter present on the input clock signal, may momentarily lose lock even though continuing to produce acceptable output clock signals. This causes the interruption of system clock generation for those systems that use the locked indicator as a gating condition. Further, it is also possible that one or more PLLs in the system do not achieve lock at all. 
     A need therefore exists for a solution which addresses both the problem of synchronization of multiple circuits or chips, as well as the problem of momentary (or permanent) deactivation of the PLL locked indication. 
     SUMMARY OF THE INVENTION 
     The present invention provides an apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. 
     Generally, the present invention provides an apparatus comprising: 
     a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal; 
     a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock; and 
     a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal 
     In addition, the present invention provides a method comprising: 
     providing a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal; 
     generating an All-Locked signal in response to all of the PLLs achieving lock; and 
     synchronizing the system clock signals of the plurality of chips in response to receipt of the All-Locked signal, wherein the system clock signals are in phase. 
     The foregoing and other features of the invention will be apparent from the following more particular description of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the present invention will best be understood from a detailed description of the invention and embodiments thereof selected for the purpose of illustration and shown in the accompanying drawings in which: 
     FIG. 1 illustrates a two-chip synchronized system of the related art; 
     FIG. 2 is a timing diagram corresponding to the system of FIG. 1, wherein the resultant system clock signals are out of phase; 
     FIG. 3 illustrates a two-chip synchronized system in accordance with the present invention; 
     FIG. 4 is a detailed circuit diagram of the startup control block within each chip of FIG. 3; 
     FIG. 5 is a timing diagram corresponding to the system of FIG. 3, wherein the resultant system clock signals are in phase; and 
     FIG. 6 illustrates a two-chip synchronized system in accordance with another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The features of the present invention are illustrated in detail in the accompanying drawings, wherein like reference numerals refer to like elements throughout the drawings. 
     A system  100  comprising two chips  112 A,  112 B, each containing a PLL  114 A,  114 B, in accordance with the present invention, is illustrated in FIG.  3 . While only two chips are shown, it should be apparent from the following description that any number of chips (or alternately circuits and/or combinations of chips and circuits) could be present within the system  100 . Each PLL  114 A,  114 B, is driven by an input clock signal  116  produced by an oscillator (not shown), and is configured to provide an output clock signal  118 A,  118 B, having an output frequency which is a multiple (e.g., 4×) of the frequency of the input clock signal  116 . 
     Depending upon the required operating frequency (i.e., system clock) of each chip  112 A,  112 B, the output clock signal  118 A,  118 B, of each PLL  114 A,  114 B, is typically divided (or multiplied) by a predetermined amount in order to generate a system clock signal  120 A,  120 B, having the desired clock frequency. In the timing diagram of FIG. 5, for example, which corresponds to the system  100  of FIG. 3, the output clock signal  118 A,  118 B, of each PLL  114 A,  114 B, is divided by three (e.g., using a divide-by three circuit) in order to generate a system clock signal  120 A,  120 B, having a clock frequency that is one-third that of its respective PLL output clock signal. 
     Each PLL  114 A,  114 B, generates a lock signal  130 A,  130 B, indicating the lock status of the PLL after reset. In this example, a lock is represented as a logic ‘1’, while a no-lock is represented as a logic ‘0’. Each lock signal  130 A,  130 B, is fed through an inverter  132 A,  132 B. The output  134 A,  134 B, of each inverter  132 A,  132 B, is coupled to the Enable input of a bi-directional driver/receiver device  136 A,  136 B. Thus, bi-directional driver/receiver device  136 A is enabled as long as PLL  114 A does not achieve lock, and bi-directional driver/receiver device  136 B is enabled as long as PLL  114 B does not achieve lock. A logic ‘0’ value is presented to the Data input of each bi-directional driver/receiver device  136 A,  136 B. Accordingly, the D output of each bi-directional driver/receiver device  136 A,  136 B, is driven to logic ‘0’ as long as its corresponding PLL  114 A,  114 B, fails to achieve lock. 
     The D outputs of the bi-directional driver/receiver devices  136 A,  136 B, are coupled in parallel by a wire  138  to Vdd through a pull-up resistor  140 . The signal on the wire  138  is hereafter referred to as the All-Locked signal. In this configuration, the All-Locked signal on wire  138  is driven to logic ‘0’ as long as either (or both) of the PLLs  114 A,  114 B, fail to achieve lock. In other words, the All-Locked signal on wire  138  is the logical AND of the PLL lock signals produced by PLLs  114 A,  114 B (i.e., the PLL lock signals are effectively “wire-ANDed” together. 
     When PLL  114 A achieves lock, the output  134 A of inverter  132 A provides a logic ‘0’ to the Enable input of the bi-directional driver/receiver device  136 A, thereby disabling the bi-directional driver/receiver device  136 A (i.e., the bi-directional driver/receiver device  136 A enters a high impedance tri-state mode). Similarly, when PLL  114 B achieves lock, the output  134 B of inverter  132 B provides a logic ‘0’ to the Enable input of the bi-directional driver/receiver device  136 B, thereby disabling the bi-directional driver/receiver device  136 B. 
     The pull-up resistor  140  connecting the All-Locked signal on wire  138  to Vdd will pull the All-Locked signal to a logic ‘1’ once both of the bi-directional driver/receiver devices  136 A,  136 B, have been tri-stated, indicating that the PLLs  114 A,  114 B, in both of the chips  112 A,  112 B, have achieved PLL lock. As the final PLL achieves lock, both of the chips  112 A,  112 B, in the system  100  simultaneously see a transition from logic ‘0’ to logic ‘1’ on the All-Locked signal on wire  138 . As detailed below with reference to FIG. 4, the logic ‘1’ All-Locked signal is latched by the external oscillator in each chip  112 A,  112 B, and the latched output is used to start up the divide circuitry in each chip in phase with the other chips in the system  100 , thereby providing system clock signals  120 A,  120 B that are in phase with each other (see the timing diagram of FIG.  5 ). The logic ‘1’ All-Locked signal on wire  138  is passed through each bi-directional driver/receiver device  136 A,  136 B, from its D input to its R output, and is provided to a startup control circuit  150 A,  150 B. 
     An exemplary startup control circuit  150  is illustrated in detail in FIG.  4 . Initially, a reset signal is asserted (i.e., logic ‘1’), and the complement  152  of the reset signal (i.e., logic ‘0’) is supplied as an input to AND gates  154  and  156 . The output  158  of AND gate  154  is coupled to the D input of flip-flop  160 . The output  162  of AND gate  156  is coupled to the D input of flip-flop  164 . The resultant logic ‘0’ provided to the D inputs of flip-flops  162  and  164  sets the output Q of each flip-flop to logic ‘0’. The output Q of flip-flop  160  is fed back to an input of OR gate  166 , and is also coupled to an input of AND gate  156 . The All-Locked signal is provided to an input of OR gate  166 . After the reset signal is deasserted, (i.e., the complement  152  of the reset signal is at logic ‘1’), the All-Locked signal is initially at logic ‘0’, thereby indicating that at least one of the PLLs  114 A,  114 B in chips  112 A,  112 B (see FIG.  3 ), has not yet achieved PLL lock. 
     The startup control circuit  150  monitors the All-Locked signal. When the All-Locked signal transitions to logic ‘1’, thereby indicating that both of the PLLs  114 A,  114 B in chips  112 A,  112 B, have achieved PLL lock after system reset, the output of flip-flop  160  is set to logic ‘1’ on the next rising edge of the PLL input clock signal  116 . Input clock signal  116  is the clock feeding the oscillator input of each PLL  114 A,  114 B, (FIG.  3 ), and is typically driven by an off-chip crystal oscillator (not shown). Once flip-flop  160  has been set to logic ‘1’, it will hold the logic ‘1’ value until the corresponding chip (e.g.,  112 A,  112 B) is reset again. This makes the startup control circuit  150  insensitive to subsequent deassertions in the All-Locked signal. 
     Once flip-flop  160  has been set to logic ‘1’, this value will transfer to the D input of flip-flop  164 , through AND gate  156 , at the next rising edge of the PLL output reference clock (this is usually at the same frequency as the PLL input clock signal  116 , and is used by the PLL as a feedback clock). This effectively transfers the All-Locked indication into the clock domain associated with the PLL output. Note that the PLL output reference clock and the PLL input clock signal  116  are of the same frequency, but will differ in phase, thus necessitating the transfer of the All-Locked indication into the PLL output domain prior to using the signal to start the clock divider circuit  168 . 
     Once flip-flop  164  is set to logic ‘1’, it signals the clock divider circuitry  168  to begin dividing and generating the system clocks  120 A,  120 B (FIG.  3 ). Since each chip  112 A,  112 B, in system  100  sees the transition of the All-Locked signal from logic ‘0’ to logic ‘1’ at the same time, the start control block  150  of each chip  112 A,  112 B, will cycle at the same time through the above-described operations, resulting in system clocks  120 A,  120 B on each chip  112 A,  112 B, that are in phase as shown in FIG.  5 . 
     In another embodiment of the present invention, as illustrated in FIG. 6, the wire  138  may alternately be tied to ground through a pull-down resistor  141 . In this embodiment, a logic ‘1’ value is presented to the Data input of each bi-directional driver/receiver device  136 A,  136 B. Accordingly, the D output of each bi-directional driver/receiver device  136 A,  136 B, is driven to logic ‘1’ as long as its corresponding PLL  114 A,  114 B, fails to achieve lock. 
     When PLL  114 A achieves lock, the output  134 A of inverter  132 A provides a logic ‘0’ to the Enable input of the bi-directional driver/receiver device  136 A, thereby disabling the bidirectional driver/receiver device  136 A (i.e., the bi-directional driver/receiver device  136 A enters a high impedance tri-state mode). Similarly, when PLL  114 B achieves lock, the output  134 B of inverter  132 B provides a logic ‘0’ to the Enable input of the bi-directional driver/receiver device  136 B, thereby disabling the bi-directional driver/receiver device  136 B. 
     The pull-down resistor  141  connecting wire  138  to ground will pull the signal on wire  138  to a logic ‘0’ once both of the bi-directional driver/receiver devices  136 A,  136 B, have been tri-stated, indicating that the PLLs  114 A,  114 B, in both of the chips  112 A,  112 B, have achieved PLL lock (i.e., the PLL lock signals are effectively “wire-ORed” together). As the final PLL achieves lock, both of the chips  112 A,  112 B, in the system  100  simultaneously see a transition from logic ‘1’ to logic ‘0’ on the wire  138 . 
     The logic ‘0’ value on wire  138  is passed through each bi-directional driver/receiver device  136 A,  136 B, from its D input to its R output, and is inverted by an inverter  143 A,  143 B, thereby providing the All-Locked signal to startup control circuit  150 A,  150 B. As detailed above with regard to FIG. 4, the All-Locked signal is used to start up the divide circuitry in each chip in phase with the other chips in the system  100 , thereby providing system clock signals  120 A,  120 B that are in phase with each other (see, e.g., the timing diagram of FIG.  5 ). 
     The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and many modifications and variations are possible in light of the above teaching. For instance, if the PLL lock signal of a chip is not a stable signal or does not exist, but a lock time is defined, an alternate signal can be used as the equivalent of PLL lock. The equivalent PLL lock signal may be generated by the chip itself, or external to the chip. In either case, the equivalent PLL lock signal is generated externally from the PLL itself. The equivalent PLL lock signal may be used in lieu of the lock signal generated by the PLL, or may be used in conjunction with the lock signal, using suitable circuitry. For example, as illustrated in phantom in chip  112 A of FIGS. 3 and 6, an OR gate  145 , having the PLL lock signal  130 A and an equivalent PLL lock signal Lock EQ  as inputs, may be coupled to the inverter  132 A. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of this invention.