Abstract:
A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    This application is a continuation-in-part of application Ser. 14/158,496, filed Jan. 17, 2014, titled “Semiconductor Memory Apparatus And Temperature Control Method Thereof”, which claims priority under 35 U.S.C. 119(a) to Korean application No. 10-2013-0126026, filed on Oct. 22, 2013, the Korean intellectual property Office. The disclosure of each of the foregoing applications is incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Various embodiments of the inventive concept relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and a temperature control method thereof. 
         [0004]    2. Related Art 
         [0005]    With demands in low power semiconductor memory devices, next generation semiconductor memory devices with non-volatility and non-memory refresh have been researched. A phase-change random access memory device (PCRAM), which is one of the next generation semiconductor memory devices, stores data using a resistance difference between an amorphous state and a crystalline state of a phase-change material. The phase-change material changes between the amorphous state and the crystalline state by an electrical pulse applied thereto. 
         [0006]    Germanium (Ga)-antimony (Sb) tellurium (Te)-based material (hereinafter, referred to as GST), which is a chalcogenide, has been most widely used as a phase-change material of a general PCRAM. This is because the GST material has a fast phase-change rate and good oxidation resistance and is stable. 
         [0007]    The GST material has a characteristic that its resistance value is changed under an effect of an external temperature. In other words, the resistance of the GST material is reduced in a high temperature and increased in a low temperature, regardless of phase-change, 
         [0008]    Thus, when the resistance of the GST material is measured by applying a certain voltage regardless of a temperature of the GST material, a measured resistance value of the GST material is different depending on temperature change. Specifically, in a multi-level cell, resistance values of multi-levels may not be accurately distinguished and thus a data error occurs. 
       SUMMARY 
       [0009]    According to an exemplary embodiment of the inventive concept, there is provided a semiconductor system including a memory device including a semiconductor substrate and a memory cell formed on the substrate, a control block for controlling the memory device a temperature adjustment unit suitable for adjusting a temperature of a memory cell and formed over the memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result, and formed in the control block. 
         [0010]    According to another exemplary embodiment of the inventive concept, there is provided a semiconductor system including a memory device including a semiconductor substrate and a memory cell formed on the substrate, a control block for controlling the memory device, a temperature adjustment unit suitable for adjusting a temperature of a memory cell; and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result, and formed in the control block, wherein memory device includes a word line region formed on the semiconductor substrate, a switching device formed on the word line region, a data storage region formed on the switching device and a bit line formed on the data storage region and wherein the temperature adjustment unit is formed in a rear surface of the semiconductor substrate, 
         [0011]    According to another exemplary embodiment of the inventive concept, there is provided a semiconductor system including a memory device including a semiconductor substrate, a plurality of memory cells formed on the semiconductor substrate and a temperature adjustment unit for adjusting a temperature of the memory cells, and a control block including a temperature control unit for controlling and verifying the temperature of the memory cells, wherein the temperature control unit includes a temperature sensing which includes a memory cell being same with the memory cell of the memory device and a temperature adjust unit being same with the temperature adjust unit of the memory device. 
         [0012]    These and other features, aspects and embodiments are described below in the section entitled “DETAILED DESCRIPTION”. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0014]      FIG. 1  is a block diagram illustrating a configuration of a semiconductor memory apparatus according to an embodiment of the inventive concept; 
           [0015]      FIG. 2  is a cross-sectional view illustrating a memory cell of a semiconductor memory apparatus according to an embodiment of the inventive concept; 
           [0016]      FIG. 3  is a cross-sectional view illustrating a memory cell of a semiconductor memory apparatus according to an embodiment of the inventive concept; 
           [0017]      FIG. 4  is a flowchart sequentially illustrating a method of manufacturing a memory cell of a semiconductor memory apparatus according to an embodiment of the inventive concept; 
           [0018]      FIG. 5  is a flowchart sequentially illustrating a method of manufacturing a memory cell of a semiconductor memory apparatus according to an embodiment of the inventive concept; 
           [0019]      FIG. 6  is a circuit diagram illustrating a temperature sensing unit of a semiconductor memory apparatus according to an embodiment of the inventive concept; and 
           [0020]      FIG. 7  is a flowchart illustrating a temperature control method of a semiconductor memory apparatus according to an embodiment of the inventive concept. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Hereinafter, exemplary embodiments will be described in greater detail with reference to the accompanying drawings. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity, Like reference numerals in the drawings denote like elements. It is also understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other or substrate, or intervening layers may also be present. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence. 
         [0022]    Although a few embodiments of the inventive concept will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these exemplary embodiments without departing from the principles and spirit of the inventive concept. 
         [0023]      FIG. 1  is a block diagram illustrating a configuration of a semiconductor memory apparatus according to an embodiment of the inventive concept. 
         [0024]    Referring to  FIG. 1 , the semiconductor system according to an embodiment of the inventive concept may be divided into a memory device  100  and a control block  200 . The memory device  100  and the control block  200  are formed in one chip. Further, the memory device  100  is formed in a first chip and the control block  200  is formed in a second chip. The first chip and the second chip may be stacked. 
         [0025]    The memory device  100  may include a plurality of memory cells (not shown) and a temperature adjustment unit  110 , and the temperature adjustment unit  110  may receive current from a current supply unit  230  of the control block  200  and adjust/maintain temperatures of the memory device  100  to be constant. A detailed configuration of the memory device  100  will be described in detail with reference to  FIG. 2  or  3 . 
         [0026]    The control block  200  may include a circuit (not shown) for controlling the memory device  100  and a temperature control unit  205  including a temperature sensing unit  210 , a control unit  220 , and the current supply unit  230 . 
         [0027]    The temperature sensing unit  210  may sense a temperature of the memory device  100 . The temperature sensing unit  210  transmit a temperature sensing result to the control unit  220 . The temperature sensing unit  210  may be formed of the same structure of the memory cell of the memory device  100 . Therefore, the temperature sensing unit  210  may include a same condition with the memory cell of the memory device  100 . 
         [0028]    The control unit  220  compares the temperature sensing result transmitted from the temperature sensing unit  210  with a preset reference temperature range. When the temperature sensing result is smaller than the reference temperature range, the control unit  220  controls the current supply unit  230  to supply current to the temperature adjustment unit  110  and controls a temperature of the memory device  100  to be within the reference temperature range. 
         [0029]    The current supply unit  230  supplies the current to the temperature adjustment unit  110  in response to a control command transmitted from the control unit  220 . 
         [0030]      FIG. 2  is a cross-sectional view illustrating a memory cell of a semiconductor memory apparatus according to an embodiment of the inventive concept. 
         [0031]    Referring to  FIG. 2 , a memory cell  100 A of the semiconductor memory apparatus according to an embodiment of the inventive concept may include a word line region  130  formed on a semiconductor  120 , a switching device  140  formed on the word line region  130  and including an N type region  141  and a P type region  142 , a bottom electrode  150  formed on the switching device  140 , a data storage unit  160  formed on the bottom electrode  150 , an top electrode  170  formed on the data storage unit  160  a first metal line region  181  formed on the top electrode  170 . A buffer layer  190  is formed on the first metal line region  181 , a temperature adjustment unit  110  is formed on the buffer layer  190 , and a second metal line region  182  is formed on the temperature adjustment unit  110 . The data storage unit  160  may include a phase-change layer formed of a phase-change material, for example, GST. The reference numerals  135 ,  145 , and  155  denote a first insulating layer, a second insulating layer, and a third insulating layer. Further, the temperature adjustment unit  110  may be formed of a material of which resistance is reduced or increased when a temperature thereof is increased. The material of which the resistance is reduced when the temperature thereof is increased may be oxide containing nickel (Ni) and manganese (Mn) and the material of which the resistance is increased when the temperature thereof is increased may be a BiTiO 3  compound or a PbTiO 3  compound. The buffer layer  190  may be oxide. For example, the first metal line region  181  may be a bit line. Further, the temperature adjustment unit  110  may be electrically connected to the second metal line region  182  and the temperature adjustment unit  110  may receive a current for changing the resistance thereof from the second metal line region  182 . For example, the second metal line region  182  may be connected to the current supply unit  230  of the control block  200 . 
         [0032]    The temperature sensing unit  210  may be formed to may include the same structure as the memory cell  102 . Thus, the temperature adjustment unit  110  and the temperature sensing unit  210  may be formed in the same process at the same time. Therefore, process cost and process time of the semiconductor system may be reduced. 
         [0033]      FIG. 3  is a cross-sectional view illustrating a memory cell of a semiconductor memory apparatus according to an embodiment of the inventive concept. 
         [0034]    Referring to  FIG. 3 , the cell  100 B of the memory device  100  apparatus according to another embodiment of the inventive concept may include a first buffer layer  115  formed on a rear surface of a semiconductor substrate  120 , a temperature adjustment unit  110  formed on the first buffer layer  115 , and a second buffer layer  105  formed on the temperature adjustment unit  110  to protect the temperature adjustment unit  110 . The cell  100 B may further include a contact via  125  formed between the temperature adjustment unit  10  and a metal line region  180 , a word line region  130  formed on the semiconductor  120 , a switching device  140  formed on the word line region  130  and including an N type region  141  and a P type region  142 , a bottom electrode  150  formed on the switching device  140 , a data storage unit  160  formed on the bottom electrode  150 , an top electrode  170  formed on the data storage unit  160 , and the metal line region  180  formed on the top electrode  170 . The data storage unit  160  may include a phase-change layer formed of a phase-change material, for example, GST. The reference numerals  135 ,  145 , and  155  denote a first insulating layer, a second insulating layer, and a third insulating layer. Further, the first buffer layer  115  and the second buffer layer  105  may be formed of the same material, for example, oxide, The temperature adjustment unit  110  is electrically connected to the metal line region  180  by the contact via  125 . Further, the metal line region  180  may be a bit line. Although not shown in  FIG. 3 , the contact via  125  may include a conductive material and the contact via  125  should be insulated from the word line region  130 . 
         [0035]    As described in  FIG. 2 , the temperature adjustment unit  110  may include a material of which resistance is reduced or increased when a temperature thereof is increased. Since the memory cell  100 B and the temperature sensing unit  210  of the control block  200  are formed to have the same structure, the temperature sensing unit  210  may foresee a temperature of the cell  100 B. Further, the temperature adjustment unit  110  and the temperature sensing unit  210  may be formed in the same process at the same time. Therefore, process cost and process time of the semiconductor system may be reduced. 
         [0036]      FIGS. 2 and 3  illustrate that the switching device  140  is a PN diode including the N type region  141  and the P type region  142 , but the switching device is not limited thereto. The switching device  140  may be a shottky diode. Alternatively, the switching device may be a MOS transistor or OTS (ovonic threshold switch) device other than the diode. 
         [0037]      FIG. 4  is a flowchart sequentially illustrating a method of manufacturing a semiconductor memory apparatus according to an embodiment of the inventive concept. 
         [0038]    Referring to  FIG. 4 , the method of manufacturing a semiconductor system according to an embodiment of the inventive concept may include providing the semiconductor substrate  120  (S 410 ), and forming the word line region  130  by implanting N type impurities into an upper portion of the semiconductor substrate  120  (S 415 ). 
         [0039]    The first insulating layer  135  including a hole is formed on the word line region  130  (S 420 ), and the switching device  140  including the N type region  141  and the P type region  142  is formed in the hole (S 425 ). 
         [0040]    The second insulating layer  145  including a hole exposing an upper surface of the switching device  140  is formed on the first insulating layer  135  in which the switching device  140  is formed (S 430 ), and the bottom electrode  150  is formed in the hole (S 435 ). 
         [0041]    The third insulating layer  155  including a hole is formed on the second insulating layer  145  in which the bottom electrode  150  is formed (S 440 ), and the data storage unit  160  is formed in the hole, and the top electrode  170  is formed on the data storage unit  160  (S 445 ). The data storage unit  160  may be a phase-change layer formed of a phase-change material, for example, GST. The data storage unit  160  may be formed by forming the hole in the third insulating layer  155 , and forming the data storage unit  160  in the hole, but the method of forming the data storage unit  160  is not limited thereto. Alternatively, the data storage unit  160  may be formed by depositing a phase-change material for the data storage unit  160  and etching the phase-change material. 
         [0042]    The first metal line region  181  is formed on the third insulating layer  155  in which the data storage unit  160  and the top electrode  170  are formed (S 450 ), and the buffer layer  190  is formed on the first metal line region  181  (S 455 ). The temperature adjustment unit  110  is formed on the buffer layer  190 , and the second metal line region  182  is formed on the temperature adjustment unit  110  (S 460 ). Therefore, the semiconductor system according to an embodiment of the inventive concept is completed. Although not shown in  FIG. 4 , when the temperature adjustment unit  110  is formed on the buffer layer  190 , the temperature sensing unit  210  of the control block  200  may be simultaneously formed of the same material as the temperature adjustment unit  110 . 
         [0043]      FIG. 5  is a flowchart sequentially illustrating a method of manufacturing a semiconductor system according to another embodiment of the inventive concept. 
         [0044]    Referring to  FIG. 5 , the method of manufacturing a semiconductor memory apparatus according to an embodiment of the inventive concept may include providing the semiconductor substrate  120  (S 510 ), and forming the first buffer layer  115  on a rear surface of the semiconductor substrate  120  (S 515 ). 
         [0045]    The temperature adjustment unit  110  is formed on the first buffer layer  115  (S 520 ). When the temperature adjustment unit  110  is formed on the first buffer layer  115 , the temperature sensing unit  210  of the control block  200  may be simultaneously formed of the same material as the temperature adjustment unit  110 . 
         [0046]    The second buffer layer  105  that may protect the temperature adjustment unit  110  is formed on the temperature adjustment unit  110  (S 525 ). 
         [0047]    The word line region  130  is formed by implanting N type impurities into an upper portion of the semiconductor substrate  120 , that is, a front surface of the semiconductor substrate  120  (S 530 ). 
         [0048]    The first insulating layer  135  including a hole is formed on the word line region  130  (S 535 ), and the switching device  140  including the N type region  141  and the P type region  142  is formed in the hole (S 540 ). 
         [0049]    The second insulating layer  145  including a hole exposing an upper surface of the switching device  140  is formed on the first insulating layer  135  in which the switching device  140  is formed (S 545 ), and the bottom electrode  150  is formed in the hole (S 550 ). 
         [0050]    The third insulating layer  155  including a hole is formed on the second insulating layer  145  in which the bottom electrode  150  is formed (S 555 ), and the data storage unit  160  is formed in the hole, and the top electrode  170  is formed on the data storage unit  160  (S 560 ). The data storage unit  160  may be a phase-change layer formed of a phase-change material, for example, GST. The data storage unit  160  may be formed by depositing a phase-change material for the data storage unit on the second insulating layer  145 , and etching the phase-change material. 
         [0051]    The semiconductor substrate  120 , the first buffer layer  115 , the first insulating layer  135 , the second insulating layer  145 , and the third insulating layer  155  are etched to form the contact via  125  on a portion of an upper surface of the temperature adjustment unit  110  (S 565 ). The contact via  125  may include a heating wire that may adjust/maintain a temperature of the memory cell  100 B to be constant. 
         [0052]    The metal line region  180  is formed on the third insulating layer  155  in which the data storage unit  160  and the top electrode  170  are formed (S 570 ). Therefore, the semiconductor memory apparatus according to another embodiment of the inventive concept is completed. 
         [0053]      FIG. 6  is a circuit unit illustrating a temperature sensing unit of a semiconductor memory apparatus according to an embodiment of the inventive concept. 
         [0054]    Referring to  FIG. 6 , the temperature sensing unit  210  according to an embodiment of the inventive concept may include a thermistor Rth that may sense a temperature of the temperature adjustment unit  110  disposed in the memory cell  100 A or  100 B. The thermistor Rth has properties in which a resistance value is reduced or increased when a temperature is increased. The material in which the resistance value is reduced when a temperature is increased may include, for example, oxide containing Ni and Mn, and the material in which the resistance is increased when the temperature is increased may include, for example, a BiTiO 3  compound or a PbTiO 3  compound. 
         [0055]    The temperature sensing unit  210  may include a comparator OP that may receive a voltage value of the thermistor Rth as an input signal compare the input signal with a preset reference voltage range, and output a temperature sensing signal OUT. 
         [0056]    The temperature sensing signal OUT outputted from the comparator OP is transmitted to the control unit  220  to control the temperature of the memory device according to an embodiment of the inventive concept to be described later. 
         [0057]      FIG. 7  is a flowchart illustrating a temperature control and verify method of a semiconductor system according to an embodiment of the inventive concept. 
         [0058]    Referring to  FIG. 7 , a temperature of the temperature adjustment unit  110  of the memory cell  100 A or  100 B is measured (S 710 ), and it is determined whether or not the measured temperature is within a preset reference temperature range (S 720 ). 
         [0059]    When the measure temperature is within the preset reference temperature range, the temperature control operation is terminated, and when the measure temperature is not within the preset reference temperature range, it is determined again whether or not the measured temperature is smaller than the preset reference temperature range (S 730 ). 
         [0060]    As a determination result, when the measured temperature is smaller than the preset reference temperature range, a control signal is inputted to the current supply unit  230 , and the temperature adjustment unit  110  is heated (S 740 ). When the measured temperature is larger than the preset reference temperature range, it is not necessary to heat the temperature adjustment unit  110 , and thus the temperature control method is terminated. 
         [0061]    It is determined whether or not a heating time reaches a reference setting time (S 750 ), and when the heating time is reaches the reference setting time, the temperature of the temperature adjustment unit  110  is measured again (S 710 ). When it is determined that the heating time does not reach the reference setting time, the temperature adjustment unit  110  is heated again for a preset time (S 740 ). 
         [0062]    It is determined again whether or not the measured temperature of the temperature adjustment unit  110  is within the preset reference temperature range (S 720 ), and when the measured temperature is within the preset reference temperature range, the temperature control method is terminated. 
         [0063]    The semiconductor system and the temperature control method thereof according to an embodiment of the inventive concept maintain a temperature of a phase-change material to be constant, and thus prevent a data error due to change of an external temperature and improve reliability of the semiconductor system. 
         [0064]    The embodiment of the inventive concept has exemplarily described the PCRAM among semiconductor memory apparatuses, but the inventive concept is not limited thereto. Technology for adjusting/maintaining a certain temperature of a temperature adjustment unit by sensing its temperatures may be applied to improve refresh properties of a dynamic random access memory (DRAM). 
         [0065]    The above embodiment of the present invention is illustrative and not limitative, Various alternatives and equivalents are possible. The invention is not limited by the embodiment described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.