Abstract:
An apparatus and method provides the foundation for designing reconfigurable electronic computing systems. The invention relies on an ability to change the resistance state of a memristor device to achieve an optimal voltage at specific circuit nodes, whereby this dynamically and autonomously causes the circuit to reconfigure itself and produce a different output for the same input relative to the circuit&#39;s initial state. The circuit&#39;s state remains constant until the memristor&#39;s resistance is changed, at which point the circuit&#39;s function is “reprogrammed”.

Description:
STATEMENT OF GOVERNMENT INTEREST 
     The invention described herein may be manufactured and used by or for the Government for governmental purposes without the payment of any royalty thereon. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates generally to the field of electronic circuit design. More specifically, this invention relates to electronic circuits which have a reprogrammable function. 
     Current, conventional digital computing architectures rely solely on the field effect transistor (FET) which is a four terminal device (drain, gate, source, and body). However, during operation for storing or retrieving information the FET device needs to be powered continuously. In addition, high charge leakage issues in the device require continuous refreshing of the processed information during standby and operation. This continuous need for power creates limitations on the system&#39;s power consumption and form factor scale. 
     One potential solution for computing architectures that eliminates the need for constant refreshing may lie within the realm of non-volatile, passive devices. One such device is the memristor, a non-volatile passive electronic device which only consumes power during operation and reconfiguration. To the extent only that memristors are not available is the reason why passive reconfigurable electronics are not available today. The fact that the memristor is a nonvolatile memory device could eventually mean that any standby power utilization of computing systems will be minimized or altogether eliminated. 
     The memristor device postulated in 1971 by Leon Chua [1] as the fourth basic circuit element has received much attention in the research community since the publication of Strukov&#39;s 2008 paper titled “The missing memristor found” [5]. The memristor name is a contraction for memory resistor [1] because that is exactly its function: to remember its history [3]. The memristor is a two terminal passive device whose resistance state depends on its previous state and present electrical biasing conditions, and combined with transistors in a hybrid chip, memristors could radically improve the performance of digital circuits without the necessity to shrink transistors [3]. Given their two terminal structural simplicity and electronic passivity, the applications for memristor technology range from non-volatile memory, instant on computers, reconfigurable electronics and neuromorphic computing [4],[3]. According to Chua [4], the memristor behaves like a linear resistor with memory. 
     What is lacking in the prior art, however, is the method and/or means by which passive memory devices such as memristors can be adapted to computing circuits so as to render the latter reconfigurable and eliminate the need for standby power consumption to maintain the reconfigured state. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method and apparatus that permits extremely low power consumption computing architectures by eliminating the need for refreshing the state of a computer processor or memory. 
     It is another object of the present invention, then, to provide a method and apparatus that provides for electronic circuitry having both a reconfigurable and non-volatile state. 
     Briefly stated, the present invention provides an apparatus and method as a fundamental building block for the designing of reconfigurable electronic computing systems. The invention relies on an ability to change the resistance state of a memristor device to achieve an optimal voltage at specific circuit nodes, whereby this dynamically and autonomously causes the circuit to reconfigure itself and produce a different output for the same input relative to the circuit&#39;s initial state. The circuit&#39;s state remains constant until the memristor&#39;s resistance is changed, at which point the circuit&#39;s function is “reprogrammed”. 
     The above, and other objects, features and advantages of the present invention will become apparent from the following description read in conjunction with the accompanying drawings, in which like reference numerals designate the same elements. 
     REFERENCES 
     
         
         [1] (Chua 1971) L. Chua, “Memristor—The Missing Circuit Element,” IEEE Transactions on Circuits Theory (IEEE) 18 (5) (1971) 507-519. 
         [2] R. Pino and J. W. Bohl, “Simple Compact Method for Modeling and Simulation of Chalcogenide Based Memristor Devices,” Invention Disclosure, December 2009. 
         [3] (Williams 2008) R. Stanley Williams, “How We Found the Missing Memristor,” IEEE Spectrum, vol 45 (12) (2008) p 28-35. 
         [4] (Chua 1976) L. Chua and S. M. Kang, “Memristive Device and Systems,” Proceedings of IEEE Vol 64 (2) (1976) p 209-223. 
         [5] (Strukov 2009) Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart and R. Stanley Williams, “The missing memristor found,” Nature vol 453 (2008) p 80-83. 
         [6] U.S. patent application Ser. No. 12/657,262, entitled “Method and Apparatus for Modeling Memristor Devices”, by Robinson Pino, et al, filed Jan. 6, 2010. 
       
    
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a schematic of a reconfigurable electronic circuit based on a memristor. 
         FIG. 2   a  depicts the simulation results and reconfigurability properties of the reconfigurable circuit of  FIG. 1 , specifically the input voltage at node D. 
         FIG. 2   b  depicts the simulation results and reconfigurability properties of the reconfigurable circuit of  FIG. 1 , specifically, the output pattern of the reconfigurable circuit at node O. 
         FIG. 3   a  depicts the transition points of the reconfigurable circuit of  FIG. 1 , specifically, the output voltage transition from high to low. 
         FIG. 3   b  depicts the transition points of the reconfigurable circuit of  FIG. 1 , specifically, the change in memristor resistance over time corresponding to an output voltage transition from high to low. 
         FIG. 3   c  depict the voltage oscillations at node n 1  and the Vp reconfiguring pulse enveloping the oscillating n 1  node voltage corresponding to an output voltage transition from high to low. 
         FIG. 3   d  depicts the transitions points of the reconfigurable circuit of  FIG. 1 , specifically, the output voltage transition from low to high. 
         FIG. 3   e  depicts the transitions points of the reconfigurable circuit of  FIG. 1 , specifically, the change in memristor resistance over time corresponding to an output voltage transition from low to high. 
         FIG. 3   f  depicts the voltage oscillations at node n 1  and the Vp reconfiguring pulse enveloping the oscillating n 1  node voltage corresponding to an output voltage transition from low to high. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention provides an apparatus and method for reprogrammable electronic circuit. The present invention employs a memristor-based approach within an innovative CMOS circuit biasing architecture to achieve autonomous electronic reconfigurability or reprogramming ability from a determined desired output and input signals. Simulation results performed on a hybrid CMOS and memristor device circuit demonstrate that a hardware realization of such electronic reconfigurable or reprogrammable system employing chalcogenide-based memristors and existing CMOS technologies is possible. The present invention represents the primitive building block for high density, small form-factor, and ultra-low power computing architectures. 
     The present invention leverages recent technological advances and discoveries namely the nonvolatile memory resistor device or “memristor” for short [1] and recent inventions in memristor modeling methodology [2], [6]. 
     An important challenge in working with memristor devices is the modeling of the time-domain hysteresis electronic behavior. Thus, no large scale or accurate circuit simulations can be performed since behavioral models do not exist. However, a recently developed invention provides a compact model and method for modeling and simulating memristor devices [2], [6]. The compact model developed models the electronic time and voltage domain characteristic behavior of chalcogenide-based memristor devices. This model, the first of its kind, enables the accurate modeling and simulation of memristor-based reprogrammable electronic circuits. Accordingly, the disclosure of the present invention incorporates by reference the disclosure of U.S. patent application Ser. No. 12/657,262, entitled “Method and Apparatus for Modeling Memristor Devices”, by Robinson Pino, et al, filed Jan. 6, 2010. 
     Referring to  FIG. 1  depicts the reconfigurable electronic circuit schematic of the present invention. From the circuit schematic, Q 1   110  and Q 4   190  represent thresholding gates (nFET transistors) whose output is directly proportional to the voltage applied to the gate node respectively. During our simulation, we assume the threshold voltage of Q 1   110  and Q 4   190  are 100 mV. The resistors R 1   160  and R 2   130  are biasing resistors to obtain the appropriate voltage biasing conditions to control the signal strength at the gate node, n 1   180 , of transistor Q 4   190 . Thus, the voltage at node n 1   180  is given by 
                     V   ⁡     (     n   ⁢           ⁢   1     )       =     Vc   ⁡     (         R   ⁢           ⁢   1     +     M   ⁢           ⁢   1           R   ⁢           ⁢   1     +     R   ⁢           ⁢   2     +     M   ⁢           ⁢   1         )               (   1   )               
where Vc  300  is the voltage at the drain node of nfet transistor Q 1   110 , R 1   160  and R 2   130  are regular resistors, and M 1  is the resistance state of the memristor device  170 . This is a first order calculation ignoring any parasitic additional resistance, capacitance, and inductance effects. Thus, if the resistance state of M 1   170  is high V(n 1 ), the voltage at node n 1   180 , will be high and if M 1   170  is low, V(n 1 ) will be low. The input signal A  100  represents the input signal to transistor Q 1   110  which if greater than the threshold voltage (100 mV) will cause Q 1   110  to output Vc  300 , connected its drain node. Otherwise, if the input signal A  100  is lower than 100 mV, then the output of Q 1   110  will be low or 0V. The transistor Q 2   270  is a safe gate (pFet transistor with threshold voltage of 0V) which prevents any perturbation to the memristor device M 1   170  whenever the              150  node is greater than 0V. The voltage source Vp  240  corresponds to the reconfiguring pulse signal voltage used to reprogram M 1   170  (the memristor) based on the electrical device characteristics described elsewhere [2]. The D node  290  is the desired output that we want the circuit to be and it is used to initiate the circuit reconfiguration process. The XOR 1  logic gate  200  compares the circuit&#39;s output O  260  to the desired output D  290  and whenever D  290  and O  260  are different the output of XOR 1  will be 1 otherwise it will be 0 given its standard Boolean logic functionality. The output of XOR 1   200  is defined at the           node  230 . The node E  280  is the programming enable mechanism that whenever greater than Q 5 &#39;s  210  threshold voltage (100 mV), it will connect the output of XOR 1   200 , T node  230 , to the gate of Q 6   220 . Anytime nodes            230  and E  280  are greater then 100 mV, the reconfiguring pulse Vp  240  will be allowed into the circuit to reconfigure or reprogram the M 1   170  the memristor device as determined by its electronic characteristics [2]. The transistor Q 3   140  is a safe gate (100 mV threshold voltage) that prevents the reconfiguring pulse Vp  240  to perturb the memristor M 1   170  whenever the input signal A  100  is zero.

     Simulation Results 
     Referring to  FIG. 2  displays the simulation results and reconfigurability properties of our reconfigurable circuit. To simulate the operation of the circuit, we employed the compact model for chalcogenide-based memristor described elsewhere [2].  FIG. 2   a , the top pattern, corresponds to the input voltage at node D ( 290 ,  FIG. 1 ), and  FIG. 2   b  corresponds to the output pattern of the reconfigurable circuit at node O ( 260 ,  FIG. 1 ). During this particular simulation results nodes A ( 100 ,  FIG. 1 ) and E ( 280 ,  FIG. 1 ) were set to high (1V). From the results we, can observe how the circuit&#39;s output node O ( 260 ,  FIG. 1 ) follows the desired training input D ( 290 ,  FIG. 1 ). The figure also shows that during the transition points from high to low and low to high outputs, the circuit oscillates until autonomous reconfigurability of the memristor M 1 ( 170 ,  FIG. 1 ) is achieved to obtain the appropriate voltage at node n 1  ( 180 ,  FIG. 1 ) to cause the output of Q 4  ( 190 ,  FIG. 1 ) to be either high (Vc) or low (0V). 
     Referring to  FIG. 3  describes in detail the electronic reconfigurable circuit transition points from high to low output  FIGS. 3   a ,  3   b , and  3   c  and low to high output  FIGS. 3   d ,  3   e , and  3   f  transitions.  FIGS. 3   a  and  3   d  show the voltage transition oscillations,  FIGS. 3   b  and  3   e  show the change in the memristor M 1 ( 170 ,  FIG. 1 ) resistance change overtime, and  FIGS. 3   c  and  3   f  show the voltage oscillations at node n 1  ( 180 ,  FIG. 1 ) and the Vp ( 240 ,  FIG. 1 ) reconfiguring pulse enveloping the oscillating n 1  ( 180 ,  FIG. 1 ) node voltage. In addition, the results,  FIGS. 3   b  and  3   e , show how the memristor device, M 1 ( 170 ,  FIG. 1 ), resistance state changes during reconfiguration (along with the memristor effective reconfiguring or “biasing” voltage Vp in  FIGS. 3   c  and  3   f  until the appropriate value is autonomously obtained by the reconfigurable circuit. Once the circuit output, O ( 260 ,  FIG. 1 ), matches the desired input value, D ( 290 ,  FIG. 1 ), the output of the XOR 1  logic gate ( 200 ,  FIG. 1 ) will be zero and the path of the training pulse, Vp ( 240 ,  FIG. 1 ), will be blocked (meaning transistor Q 6  ( 220 ,  FIG. 1 ) will be in the off state), stopping the reconfiguration process. 
     Having described preferred embodiments of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.