Abstract:
An amplifier including the transistors of a first set operates by a power source VCC 2 , and amplifies the input signal, changing in the voltage range of the power source VCC 2 , in the voltage range of the power source VCC 2 . The output of this amplifier operates using a power source VCC 1  with a converting portion including the transistors of a second set, and the output of the amplifier is converted into an output within the voltage range of the power source VCC 1 . The two output amplifiers amplify the output of this converting portion based on a (½) VCC 1  reference. The converting portion performs the conversion using a plurality of transistors with the power source VCC 2  taken as a power source and a plurality of transistors  7  with the power source VCC 1  taken as a power source, as current mirrors.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   The disclosure of Japanese Patent Application No. 2007-332998 filed on Dec. 25, 2007 including specification, claims, drawings, and abstract is incorporated herein by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   1.Field of the Invention 
   The present invention relates to a level shift circuit for shifting the voltage level of a current signal. 
   2.Description of the Related Art 
   In imaging equipment such as a video camera and a digital still camera, there is a requirement for preventing a video image from becoming degraded due to the occurrence of blur in a subject image by vibration and the like, such as by hand shake, and a vibration measurement mechanism is provided. This vibration measurement mechanism detects the vibration of the imaging equipment with respect to the subject, and it is known that, in response to vibration, an optical system (lens) and the like is shift-corrected by a motor and the like (see Japanese Patent Laid-Open Publication No. Hei 07-23277 etc.). 
   As this motor for correction, a voice coil motor and the like are used, and to make the driving of this voice coil effective, a power source of preferably high voltage is used. 
   Hence, after performing the amplification of the signal for driving with an internal reference voltage, the power source voltage is level-shifted to a battery power source, and as a result the circuit and the like for outputting the signal to the voice coil is adopted as a drive circuit of the voice coil. 
   Further, as related literature, Japanese Patent Laid-Open Publication No. 2000-244306 can be cited. 
   Here, the battery power source is lowered with use. Depending on the kind of the battery, there are cases where the lowering of the voltage is considerably large. In this case, when the reference voltage internally used is made undependable on the battery power source and unalterable, the reference voltage and the battery power source are sometimes reversed. 
   In general, the level-shift circuit is configured such that the relation of magnitude between two power sources that are the object of conversion is fixed, and the relation is not assumed to be reversed. Hence, when the relation of two power source voltages is reversed, there is a problem that the circuit is unable to perform an expected operation. 
   SUMMARY OF THE INVENTION 
   According to the present invention, since the conversion of the power source voltages is performed by a current mirror, the level shift of the signal can be performed regardless of the magnitude of both of the power source voltages. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
       FIG. 1  is a view showing the configuration of a level-shift circuit of the embodiment. 
   

   DESCRIPTION OF PREFERRED EMBODIMENTS 
   An embodiment of the present invention will be described below with reference to the drawing. 
     FIG. 1  shows a circuit according to the embodiment. An input signal Vin is inputted to the base of a PNP transistor Q 1  via a buffer amplifier BAO. The emitter of this transistor Q 1  is connected with the collector of a PNP transistor Q 2 , and the emitter of this transistor Q 2  is connected to a power source VCC 2 . The base of the transistor Q 2  similarly has the emitter connected with the power source VCC 2  and connected with the base of a transistor Q 3 , whose collector and base are short-circuited. The collector of this transistor Q 3  is connected to the collector of an NPN transistor Q 4 . The transistor Q 4  has the emitter connected to ground, and has the base connected to the base of a transistor Q 5  at the current mirror input side, whose collector and base are short-circuited. 
   This current mirror input side transistor Q 5  causes a fixed current I 0  to flow, and all transistors constituting this transistor Q 5  and the current mirror cause this fixed current I 0  to flow. Consequently, all the transistors Q 4 , Q 3 , and Q 2  cause the current I 0  to flow. 
   The collector of the transistor Q 1  is connected with the collector of an NPN transistor Q 6 , and this transistor Q 6  has the collector and base short-circuited and has the emitter connected to ground. The base of the transistor Q 6  is connected with an NPN transistor Q 7 , whose emitter is connected to ground, and the collector of this transistor Q 7  is connected to the collector of a PNP transistor Q 8 . The transistor Q 8  has the emitter connected to a power source VCC 1 , and has the base and collector short-circuited. Consequently, the transistor Q 8  causes the same current as that of the transistor Q 7  to flow. The base of the transistor Q 8  is connected with a PNP transistor Q 9 , whose emitter is connected to the power source VCC 1 , and the transistors Q 8  and Q 9  constitute the current mirror. The collector of the transistor Q 9  is connected with the collector of an NPN transistor Q 10 , and the emitter of this transistor Q 10  is connected to ground. 
   Consequently, the transistor Q 9  causes the current (I 1 ) flowing through the transistor Q 1  to flow. The difference between the current flowing through the transistor Q 9  and the current flowing through the transistor Q 10  is obtained at a node A 1  which is a connection point of the collector of the transistor Q 9  and the collector of the transistor Q 10 , and this is outputted. 
   On the other hand, the signal of a fixed value of (½) VCC 2  is inputted to the base of a PNP transistor Q 21 . The emitter of this transistor Q 21  is connected with the collector of a PNP transistor Q 22 , and the emitter of this transistor Q 22  is connected to the power source VCC 2 . The base of the transistor Q 2  similarly has the emitter connected with the power source VCC 2 , and is connected with the base of a transistor Q 23 , whose collector and base are short-circuited. The collector of this transistor Q 23  is connected to the collector of an NPN transistor Q 24 . The transistor Q 24  has the emitter connected to ground, and has the base connected to the base of the current mirror input side transistor Q 5 , whose collector and base are short-circuited. 
   This current mirror input side transistor Q 5  causes the fixed current I 0  to flow, and all transistors constituting this transistor Q 5  and the current mirror cause this fixed current I 0  to flow. Consequently, all of the transistors Q 24 , Q 23 , and Q 22  cause the current I 0  to flow. 
   The collector of the transistor Q 21  is connected with the collector of an NPN transistor Q 26 , and this transistor Q 26  has the collector and base short-circuited, and has the emitter connected to ground. The base of the transistor Q 26  is connected with an NPN transistor Q 27 , whose emitter is connected to ground, and the collector of this transistor Q 27  is connected to the collector of a PNP transistor Q 28 . The transistor Q 28  has the emitter connected to a power source VCC 1 , and has the base and collector short-circuited. Consequently, the transistor Q 28  causes the same current as that of the transistor Q 27  to flow. The base of the transistor Q 28  is connected with a PNP transistor Q 29 , whose emitter is connected to the power source VCC 1 , and the transistors Q 28  and Q 29  constitute the current mirror. The collector of the transistor Q 29  is connected with the collector of an NPN transistor Q 30 , and the emitter of this transistor Q 30  is connected to ground. 
   Consequently, the current (I 2 ) flowing through the transistor Q 21  flows into transistor Q 29 . The difference between the current flowing through the transistor Q 29  and the current flowing through the transistor Q 30  is obtained at a node B 1  which is a connection point of the collector of the transistor Q 29  and the collector of the transistor Q 30 , and this is outputted. 
   Here, the base of the transistor Q 10  is connected to the base of the transistor Q 26 . Consequently, these transistors Q 26  and Q 10  constitute the current mirror, and the transistor Q 10  causes the same current as that of the transistor Q 26  to flow. Since the transistor Q 26  causes the current I 2  flowing through the transistor Q 21  to flow, the current flowing through the node A 1  becomes the current I 1 -I 2 . Further, the base of the transistor Q 30  is connected to the base of the transistor Q 6 . Consequently, these transistors Q 6  and Q 30  constitute the current mirror, and the transistor Q 30  causes the same current as that of the transistor Q 6  to flow. Since the transistor Q 6  causes the current I 1  flowing through the transistor Q 1  to flow as it is, the current flowing through the node B 1  becomes the current I 2 -I 1 . 
   The connection point of the emitter of the transistor Q 21  and the collector of the transistor Q 22  is connected with one end of a resistor R 11 , and the other end of this resistor R 11  is connected to the collector of an NPN transistor Q 11 . This transistor Q 11  has the emitter connected to ground and the base connected to the base of the transistor Q 5 , and causes the current I 0  to flow. 
   The collector of the transistor Q 11  is connected with the emitter of an NPN transistor Q 12  and the other end of the resistor R 11 , and the base of this transistor Q 12  is connected with an output of a buffer amplifier BA 0 , and here, the input signal Vin is inputted. The collector of the transistor Q 12  is connected with the collector of a PNP transistor Q 13 . The emitter of the transistor Q 13  is connected to the power source VCC 2 , and the base and collector are short-circuited. The base of the transistor Q 13  is connected with the base of a PNP transistor Q 14 , whose emitter is connected to the power source VCC 2 , and the transistors Q 13  and Q 14  constitute the current mirror. The collector of the transistor Q 14  is connected to the collector of an NPN transistor Q 15 . The transistor Q 15  has the emitter connected to ground, and has the base and collector short-circuited, and causes the same current as that of the transistor Q 14  to flow. The base of the transistor Q 15  is connected with the base of an NPN transistor Q 16 , whose emitter is connected to ground. The transistors Q 15  and Q 16  constitute the current mirror. 
   The collector of the transistor Q 16  is connected with the collector of a PNP transistor Q 17 , and here it becomes a node A 2 . The transistor Q 17  has the emitter connected with the power source VCC 1  and the base connected with a PNP transistor Q 18 . The transistor Q 18  has the emitter connected with the power source VCC 1  and has the base and collector short-circuited. Consequently, the transistors Q 18  and Q 17  constitute the current mirror, and the transistor Q 17  causes the same current as that of the transistor Q 18  to flow. The collector of the transistor Q 18  is connected with the collector of an NPN transistor Q 19 , whose emitter is connected to ground. 
   The connection point of the emitter of the transistor Q 1  and the collector of the transistor Q 2  is connected with one end of a resistor R 12 , and the other end of this resistor R 12  is connected to the collector of an NPN transistor Q 31 . This transistor Q 31  has the emitter connected to ground and the base connected to the base of the transistor Q 5 , and causes the current I 0  to flow. 
   The collector of the transistor Q 31  is connected with the emitter of an NPN transistor Q 32  and the other end of the resistor R 12 , and the base of this transistor Q 32  is connected with the power source (½) VCC 2 . The collector of the transistor Q 32  is connected with the collector of a PNP transistor Q 33 . The emitter of the transistor Q 33  is connected to the power source VCC 2 , and has the base and collector short-circuited. The base of the transistor Q 33  is connected with the base of a PNP transistor Q 34 , whose emitter is connected to the power source VCC 2 , and the transistors Q 33  and Q 34  constitute the current mirror. The collector of the transistor Q 34  is connected with the collector of the NPN transistor Q 35 . The transistor Q 35  has the emitter connected to the ground, and has the base and collector short-circuited, and causes the same current as that of the transistor Q 34  to flow. The base of the transistor Q 35  is connected with the base of an NPN transistor Q 36 , whose emitter is connected to ground. The transistors Q 35  and Q 36  constitute the current mirror. 
   The collector of the transistor Q 36  is connected with the collector of a PNP transistor Q 37 , and here it becomes a node B 2 . The transistor Q 37  has the emitter connected with the power source VCC 1  and the base connected with a PNP transistor Q 38 . The transistor Q 38  has the emitter connected with the power source VCC 1  and has the base and collector short-circuited. Consequently, the transistors Q 38  and Q 37  constitute the current mirror, and the transistor Q 37  causes the same current as that of the transistor Q 38  to flow. The collector of the transistor Q 38  is connected with the collector of an NPN transistor Q 39 , whose emitter is connected to ground. 
   Here, the base of the transistor Q 39  is connected with the base of the transistor Q 15 , and the transistors Q 15  and Q 39  constitute the current mirror. Further, the base of the transistor Q 19  is connected with the base of the transistor Q 35 , and the transistors Q 35  and Q 19  constitute the current mirror. 
   The transistor Q 15  causes a current identical to that in the transistor Q 12  to flow, and on the other hand, the transistor Q 35  causes the same current as that of the transistor Q 32  to flow. Here, the emitter of the transistor Q 12  is connected with the other end of the resistor R 11 . A current that is derived by adding up the current flowing through the transistor Q 12  and the current flowing from the resistor R 11  flows into the transistor Q 11 , and this current flowing into the transistor Q 11  is the same as the current I 0  flowing through the transistor Q 5 . One end of the resistor R 11  is connected to the collector of the transistor Q 22 , and this transistor Q 22  causes the current I 0  to flow, similarly to the transistors Q 24  and Q 23 . Since the current I 2  flows through the transistor Q 21 , the current (I 0 -I 2 ) flows through the resistor R 11 . Consequently, the current I 2 , which derived by subtracting the current I 0 -I 2  flowing in the resistor R 11  from the current I 0  flowing through the transistor Q 11 , is assumed to flow through the transistor Q 12 . If the current I 2  flows through this transistor Q 12 , the current I 2  also flows through the transistor Q 15 , and the current I 2  also flows through the transistor Q 39 . Consequently, the current I 2  flows through the transistor Q 37 . 
   The transistor Q 35  causes current identical to that of the transistor Q 32  to flow. On the other hand, the transistor Q 35  causes the same current as that in the transistor Q 32  to flow. Here, the emitter of the transistor Q 32  is connected with the other end of the resistor R 12 . A current derived by adding up the current flowing into the transistor Q 32  and the current flowing from the resistor R 12  flows into the transistor Q 31 , and the current flowing into the transistor Q 31  is the same as the current I 0  flowing through the transistor Q 5 . One end of the resistor R 12  is connected to the collector of the transistor Q 2 , and this transistor Q 2  causes the current I 0  to flow, similarly to the transistors Q 24  and Q 23 . Since the current I 1  flows into the transistor Q 1 , the current (I 0 -I 1 ) flows into the resistor R 12 . Consequently, the current I 1 , which is derived by subtracting the current I 0 -I 1  flowing in the resistor R 12  from the current I 0  flowing through the transistor Q 31 , is assumed to flow through the transistor Q 32 . If the current I 1  flows through this transistor Q 32 , the current I 1  also flows through the transistor Q 35 , and the current I 1  also flows through the transistor Q 19 . Consequently, the current I 1  flows through the transistor Q 17 . The resistance values of the resistors R 11  and R 12  are usually set as R 11 =R 12 =R. 
   In this manner, the transistors Q 1  and Q 32  cause the current I 1  to flow, and the transistors Q 21  and Q 12  cause the current I 2  to flow. The input signal Vin is fed to the bases of the PNP transistor Q 1  and the NPN transistor Q 12 , and (½) VCC 2  is fed to the bases of the PNP transistor Q 21  and the NPN transistor Q 32 . Consequently, the voltage applied to both ends of the resistor R 11  is {(½) VCC 2 +1VBE}−(Vin−1VBE)={(½) VCC 2 −Vin}+2VBE, and the voltage applied to both ends of the resistor R 12  is {Vin+1VBE}−((½) VCC 2 −1VBE)={Vin−(½)VCC 2 }2VBE. With these voltages, the currents (I 0 -I 2 ) and (I 0 -I 1 ) flowing through the resistors R 11  and R 12  are decided, and eventually, the current I 1  flows through the transistors Q 1 , Q 9 , Q 17 , Q 30 , and Q 36 , the current (½)VCC 2  flows through the transistors Q 21 , Q 29 , Q 37 , Q 10 , and Q 16 , the current (I 1 -I 2 ) flows through the nodes A 1  and A 2 , and the current (I 2 -I 1 ) flows through the nodes B 1  and B 2 . That is, the transistors Q 1  and Q 21  operate as a differential transistor, and the voltage inputted to the transistor Q 21  is the fixed voltage (½) VCC 2 , the nodes A 1  and A 2  obtain the input signal Vin and the signal of an reverse polarity (reversed-phase signal), and the nodes B 1  and B 2  obtain a signal (in-phase signal) of the same polarity as the input signal. 
   Further, the node A 1  and the node A 2  are connected, and after the signals thereof are added, they are inputted to the positive input end of an operational amplifier OP 1 . This positive input end of the operational amplifier OP 1  is connected to the power source (½) VCC 1  via a resistor RL 1  and a buffer amplifier BA 01 . Further, the negative input end of the operational amplifier OP 1  is connected with the power source (½) VCC 1  via a resistor Rs 1 , and the output end of the operational amplifier OP 1  is connected via a resistor Rf 1 . Further, the operational amplifier OP 1  is provided with the power source VCC 1  as an operational power source. Consequently, the reversed-phase signal is amplified by this operational amplifier OP 1 , and outputted with VCC 1  as the power source. 
   Further, the node B 1  and the node B 2  are connected, and after the signals thereof are added, they are inputted to the positive input end of an operational amplifier OP 2 . This positive input end of the operation amplifier OP 2  is connected to the power source (½) VCC 1  via a resistor RL 2 . Further, the negative input end of the operational amplifier OP 2  is connected with the power source (½) VCC 1  via the buffer amplifier BA 01  and a resistor Rs 2 , and the output end of the operational amplifier OP 1  is connected via a resistor Rf 2 . Further, the operational amplifier OP 2  is fed with the power source VCC 1  as an operational power source. Consequently, the in-phase signal is amplified by this operational amplifier OP 2 , and outputted with VCC 1  as a power source. 
   Here, assuming that the resistance value of each resistor is RL 1 =RL 2 =RL, Rs 1 =Rs 2 =Rs, Rf 1 =Rf 2 =Rf, the gain of the level shift from VCC 2  to VCC 1  becomes (4×RL)÷R, and the gain as a BTL amplifier outputted from the operational amplifiers OP 1  and OP 2  becomes 2×(1+Rf/Rs). 
   That is, the level shift from the input signal Vin with (½) VCC 2  as a center to the output signal with (½) VCC 1  as a center becomes a ratio of R which is the resistance value of the resistors R 11  and R 12  disposed between an input route of the input signal Vin and an input route of the reference signal, and a load resistance RL 1 =RL 2 =RL disposed with (½) VCC 1  in the output side, and since this ratio exists at four places in total, they are added to become (4×RL)÷R. On the other hand, gain of each of the operational amplifiers OP 1  and OP 2  becomes 1+Rf/Rs with the resistance value of the input resistor as Rs and the resistance value of feedback resistor as Rf, and becomes 2×(1+Rf/Rs) by adding the gains of the in-phase side and the reversed phase side. 
   In this manner, in the present embodiment, the power source of a differential amplifier inputted with the input signal Vin is taken as VCC 2 , and the output thereof is converted into a power source VCC 1  reference by the current mirror. Consequently, there is no problem regardless of whether the power source VCC 1  or the power source VCC 2  is high voltage. In general, as the circuit for generating a control signal, a reference power source (generated by a fixed voltage circuit and the like from a battery power source) VCC 2  of a relatively low voltage and having small variation is used, whereas the output of the amplifier is a voltage for driving a coil, and uses the battery power source VCC 1  as it is preferable to use high voltage. However, when the battery power source fluctuates or the battery is consumed, the voltage is sometimes lowered considerably. In that case, it is also conceivable that the power source VCC 1  will become lower than the power source VCC 2 . In the present embodiment, even in such a case also, no problem occurs in the operation itself. 
   Further, since the present embodiment is of the type in which two outputs are generated in one phase and are added, the output signal becomes double. 
   In the above description, while it is described that all the current mirrors have the same emitter area, and cause the same current to flow, the emitter area may be appropriately changed and a mirror ratio may be changed. Further, while the input signal to the transistor Q 21  is taken as a fixed voltage, it may be taken as a reversed signal of the input signal Vin.