Abstract:
A stacked printed circuit board memory module in which a plurality of daughter circuit boards can be stacked onto a primary circuit board. The primary board and each of the plurality of daughter boards have electronic memory ICs mounted on the respective surfaces. The primary board and each of the daughter boards have mounted connectors so that the boards can be electronically and mechanically interconnected with another board.

Description:
RELATED APPLICATIONS  
       [0001]    This application is a continuation of prior U.S. patent application Ser. No. 09/231,613, entitled “STACKED PRINTED CIRCUIT BOARD MEMORY MODULE” which was filed on Jan. 14, 1999, and issued as U.S. Pat. No. 6,324,071 on Nov. 27, 2001. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The invention relates to high density memory systems for high-speed computer and network systems, and more particularly to an improved high density memory module.  
         DESCRIPTION OF THE RELATED ART  
         [0003]    With the introduction of network servers and work stations that can utilize memory in the gigabyte range and can operate at speeds of 100 Mhz or higher, fast and high density memory modules are needed to reach these memory capacities and speeds. Present day computer systems typically include hundreds of discrete components mounted on printed circuit boards (PCBs) interconnected with wiring on the board. The PCBs may also include sockets and connectors for receiving additional components, component modules and multichip modules, and connectors to other PCBs.  
           [0004]    Computer memory often consists of one or more memory modules which plug into connectors on main printed circuit boards in computers (motherboards). The PCB memory module connector sockets are interconnected by a common set of address, data and control lines. Generally, there are several memory module connectors and when the memory requirements increase, additional modules may be added onto the motherboards. However, as computer system speeds and memory requirements have continued to increase and more integrated devices are incorporated onto PCBs, traditional memory packaging schemes have become inadequate. A constant goal in designing integrated circuit (IC) modules is to pack more integrated circuitry into the same or less space. This may be accomplished by physically scaling down the electrical components, such as decreasing transistor size at the substrate level, thereby increasing transistor density on semiconductor chips. Another possibility has been to increase the number of integrated circuits on the PCB. With present PCB technology, ICs may be mounted on both surfaces (front and back) of the PCB using surface mount techniques. However, the PCBs generally cannot be increased in length or height due to space limitations imposed by available areas on motherboards and within computer housings thereby limiting the amount of PCB real estate available for additional memory ICs.  
           [0005]    As the density requirements of modules increase, solutions are needed to meet these requirements. There are currently three solutions to meet the requirements. First, the individual PCB can be made larger to accommodate more memory chips, this includes folding the PCB in half using a flex circuit. However, increasing the number of chips on individual boards consequently increases the length of the traces between chips and other PCBs. The increase in the trace length has cause a deviation from standards which require certain lengths to be maintained in order to prevent skew among clock, address, and data signals. Other transmission line problems occur when these high speed signals are transmitted over traces that are too long. Such problems include reflections, cross-talk, and electromagnetic induction. Therefore, placement of memory ICs on PCBs is critical to design considerations when trying to increase memory capacity and density.  
           [0006]    The second solution to increase memory density is to decrease semiconductor die size to fit more memory in the same semiconductor package. However, decreasing die size while increasing memory density leads to greater costs. The industry norm is a 64 Megabit die. There have been increases to a 128 Megabit and 256 Megabit die but with a corresponding increase in cost of approximately five to six times.  
           [0007]    The third solution to increasing memory density is to stack semiconductor die in the same package. While this solution increases the memory density, heat dissipation becomes a problem. Each of the individual ICs become hot and the heat cannot be properly dissipated from the PCB. The increased heat causes the performance of the memory module to decrease and often fail. As a result, the memory modules cannot be run at full performance. Often clock speeds and data transfers have to be decreased to reduce heat generated by the modules. Moreover, heat generation problems limit the number of memory modules that can be populated on a PCB, degenerating performance. Therefore, the number of memory ICs that can be placed on any given PCB memory module is limited due to heat dissipation and other considerations.  
         SUMMARY OF THE INVENTION  
         [0008]    In an implementation of the invention, a memory module is provided that can stand alone as a primary board for insertion into a motherboard of a computer. The primary board has capability to receive additional daughter printed circuit boards on either surface. These additional daughter printed circuit boards provide additional memory to the computer without taking up an additional memory module socket. Additional daughter boards may be inserted to the daughter boards already connected to the primary board, without taking up any additional slots on the motherboard. The connectors between the primary board and each additional daughter board provide the electronic coupling necessary for the motherboard to send and receive data and address information. These connectors are placed so as to shorten the overall trace length of the memory module. Open air channels at the upper end of each of the primary and daughter boards aid in heat dissipation thereby increasing overall performance of the module.  
           [0009]    Other features and advantages will be readily apparent from the following detailed description, the accompanying drawings and the claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1A is a front view of a primary circuit board.  
         [0011]    [0011]FIG. 1B is a rear view of a primary circuit board.  
         [0012]    [0012]FIG. 1C is a front view of a daughter circuit board.  
         [0013]    [0013]FIG. 1D is a rear view of a daughter circuit board.  
         [0014]    [0014]FIG. 2 is a perspective view of the stacked printed circuit board memory module showing the primary board (center) and two daughter boards (front and back).  
         [0015]    [0015]FIG. 3A is a side view of a primary circuit board and three daughter circuit boards before insertion.  
         [0016]    [0016]FIG. 3B is a side view of two stacked printed circuit board memory modules having a primary board and two daughter boards, each module inserted into a motherboard.  
         [0017]    [0017]FIG. 4A is a front view of a primary circuit board showing a female connector.  
         [0018]    [0018]FIG. 4B is a rear view of a primary circuit board having no connector.  
         [0019]    [0019]FIG. 4C is a front view of a daughter circuit board having a male connector.  
         [0020]    [0020]FIG. 4D is a rear view of a daughter circuit board having no connector.  
         [0021]    [0021]FIG. 4E is a side view of a stacked printed circuit board memory module including a primary board and a daughter board.  
         [0022]    [0022]FIG. 5A is a bottom view of a stacked printed circuit board memory module including a primary circuit board and three daughter circuit boards.  
         [0023]    [0023]FIG. 5B is a bottom view of a stacked printed circuit board memory module including a primary circuit board and a daughter circuit board. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0024]    Referring to FIG. 1A, there is shown a front view of a primary circuit board  10  with the first surface  1   a  facing forward. Electronic components  2   a  are mounted on the first surface  1   a.  Only four individual electronic components  2   a  are shown in the figure for the purpose of clarity. Additional components may be added in other implementations of the invention. In an implementation of the invention electronic components  2   a  may be Synchronous Dynamic Random Access Memory (SDRAM) ICs. Vias  6  are present on the surface  1   a  of the primary circuit board  10  in order to provide access to couple the electronic components  2   a  on the first surface of the primary board  1   a  to the other side of the board. Only one via  6  is shown in the figure. Via conductors  7  provide the electric coupling to components on the other side of the board. Only via conductor  7  is shown in the figure. Primary connectors  3   a  are also mounted on first surface  1   a.  In an implementation of the invention, female-type primary connectors may be mounted on the first surface  1   a.  Only a few conductive leads are shown for the purpose of clarity. Connectors  3   a  are adapted to receive connectors on a daughter circuit board. Conductive leads  4  define control connectors of a control connector which run along a connecting edge  8  of the primary board in order to electrically couple with a motherboard. Conductive leads carry the signals from the control and address lines of a control motherboard. Connecting edge  8  is designed to be received by a motherboard for mechanical support. Conductive paths  5   a  are mounted on the surface  1   a  in order to couple the electronic components  2   a  with the primary connectors  3   a  and with the conductive leads  4 . Only a couple of conductive paths  5   a  are shown in the figure.  
         [0025]    Referring now to FIG. 1B, there is shown a rear view of primary circuit board  10 . Additional electronic components  2   b  are mounted on the surface  1   b.  Via  6  gives access to the front surface  1   a  and electronic components  2   a  of the primary board  10 . Via conductor  7  couples electronic components  2   a,    2   b.  Primary connectors  3   b  are adapted to receive daughter connectors from a daughter circuit board. Conductive paths  5   b  couple electronic components  2   b  with primary connectors  3   b  and conductive leads  4 .  
         [0026]    Referring now to FIG. 1C, there is shown a front view of a daughter circuit board  11 . Electronic components  13   a  are mounted on the surface  12   a.  Via  16  allows electric coupling access to the other side of the daughter circuit board  11 . Via conductor  17  allows electric coupling to electronic components on the other side of the daughter board  11 . Daughter connectors  14   a  are mounted on the surface  12   a.  In an implementation of the invention, daughter connectors  14   a  may be male-type connectors. The make-type connectors  14   a  are adapted to mechanically and electrically couple with primary connectors  3   a.  Connectors  14   a  may also mechanically and electrically couple with primary connectors  3   b.  Conductive paths  15   a  electrically couple daughter connectors  14   a  with electronic components  13   a.    
         [0027]    Referring now to FIG. 1D, there is a rear view of daughter circuit board  11 . Electronic components  13   b  are mounted on the surface  12   b.  Via  16  allows electrical access to the first surface  12   a  of the daughter circuit board  11 . Via conductor  17  allows electric coupling between electronic components  13   b  and electronic components  13   a.  Daughter connectors  14   b  are mounted to the surface  12   b.  In an implementation of the invention, daughter connectors  14   b  are female-type connectors. Daughter connectors  14   b  are adapted to receive additional daughter connectors on addition daughter circuit boards. Conductive paths  15   b  electrically couple electronic components  13   b  and daughter connectors  14   b.    
         [0028]    Although male/female-type connectors have been shown in the figures, other types of connectors to interconnect the primary board  10  and daughter board  11  would be suitable. For example, Zero Insertion Force (ZIF) connectors would be suitable to interconnect the primary board  10  and the daughter board  11 .  
         [0029]    Referring now to FIG. 2, there is shown a perspective view of a primary circuit board  10 , daughter circuit board  11 , and daughter circuit board  20 . Daughter circuit board  20  has corresponding elements as daughter board  11 . In an implementation of the invention, the connectors  3   a  shown as female-type connectors on primary board  10  receive the daughter connectors  14   a  on daughter board  20 . In an implementation, the daughter connectors  14   a  on daughter board  20  are male-type connectors so as to couple with female-type primary connectors  3   a.  In the same implementation, male-type connectors  14   a  on daughter board  11  may be coupled with female-type connectors  3   b  on primary board  10 .  
         [0030]    Referring now to FIG. 3A, there is shown a side view of primary board  10 , daughter board  11 , daughter board  38  and daughter board  30 . In an implementation, the female-type connector  3   a  on primary board  10  may be mechanically and electrically coupled with male-type connector  14   a  on daughter board  38 . The female primary connector  3   b  may be mechanically and electrically coupled with male-type connector  14   a  on daughter board  11 . Female-type connector  14   b  on daughter board  38  may be coupled with male-type connector  14   a  on daughter board  39 .  
         [0031]    Referring now to FIG. 3B, there is shown a side view of two stacked printed circuit board memory modules  33   a,    34   a  mounted on a motherboard  30 . Module  33   a  is mounted on motherboard  30  by motherboard connector  31 . Module  34   a  is mounted on motherboard  30  by motherboard connector  32 . Module  33   a  includes a primary board  33   c  coupled with two daughter boards  33   b  and  33   d.  Module  34   a  includes a primary board  34   c  coupled with two daughter boards  34   b  and  34   d.  Female-type connector  14   b  on daughter board  33   b  may receive an additional male-type connector from an additional daughter circuit board. Female-type connector  14   b  on daughter board  34   d  may receive an additional male-type connector from an additional daughter circuit board. Upper air channels  35  run along the board between electronic components  13   a,    13   b  between daughter circuit boards  33   b,    33   d,    34   b,    34   d,  as well as between electronic components  2   a,    2   b  on primary circuit board  33   c,    34   c  and electronic components  14   a,    14   b  on daughter boards  33   b,    33   d,    34   b,    34   d.  Upper air channels  35  allow for better heat dissipation from the memory modules  33   a,    34   a  thereby increasing overall performance.  
         [0032]    The interconnection of the primary connectors  3   a,    3   b  and the daughter connectors  14   a,    14   b,  as well as the interconnection between daughter connectors  14   a,    14   b  allows the daughter circuit boards  33   b,    33   d,    34   b,    34   d,  and primary boards  33   c,    34   c  to be electrically and mechanically coupled in a substantially spaced and parallel relation. The orientation of the daughter boards  33   b,    33   d,    34   b,    34   d  and primary boards  33   c,    34   c  is such that all daughter connectors  14   a,    14   b  and all primary connectors  31 ,  3   b  are aligned in a straight line that runs perpendicular to daughter boards  33   b,    33   d,    34   b,    34   d  and primary boards  33   c,    34   c.    
         [0033]    The linear interconnection between daughter connectors  14   a,    14   b  and primary connectors  3   a,    3   b  at a lower end of the modules  33   a,    34   a,  close to motherboard connectors  31  and  32  allow a decrease in the conductive path (trace length) that address, control and data signals must travel from motherboard  30  to modules  33   a,    34   a.  This decrease in the trace length decreases skew among clock, control and data signals, as well as other transmission line problems such as reflections, cross-talk, and electromagnetic induction.  
         [0034]    In an implementation of the invention, primary board  33   c  may be connected to motherboard connector  31  and primary board  34   c  may be connected to motherboard connector  32  as standalone memory modules. In other implementations, daughter circuit boards  33   b,    33   d,    34   b,    34   d  may be stacked on primary boards  33   c,    34   c.  In further implementations, additional daughter circuit boards (not shown) may be stacked onto daughter boards  33   b,    34   d  through daughter connectors  14   a,    14   b.    
         [0035]    Referring now to FIG. 4A, there is shown a front view of an implementation of a primary circuit board  40 . Electronic components  42   a  are mounted on surface  41   a.  Primary connectors  43  are mounted to the surface  41   a.  In an implementation of the invention, only surface  41   a  of the primary circuit board has primary connectors  43 . Conductive leads  44   a  run along connecting edge  44   b  at an edge of primary circuit board  40 . Conductive paths  440  electrically couple electronic components  42   a,  primary connectors  43  and conductive leads  44   a.  Vias  400  provide electrical access to the other side of primary circuit board  40 . Via conductors  410  provide electrical coupling to electronic components on the other side of primary circuit board  40 .  
         [0036]    Referring now to FIG. 4B, there is shown a rear view of primary circuit board  40 . Electronic components  42   b  are mounted to the surface  41   b.  Vias  400  provide electrical access to the front side of the primary circuit board  40 . Via conductors provide electrical coupling between electronic components  42   a  and  42   b.  In an implementation of the invention, the rear surface  41   b  has no primary conductors mounted on it.  
         [0037]    Referring now to FIG. 4C, there is shown a front view of a daughter circuit board  45 . Electronic components  47   a  are mounted on surface  46   a.  Vias  420  provide electrical access to the other side of the daughter circuit board. Via conductor  430  provides electrical coupling to electronic components on the other side of the daughter circuit board  45 . Daughter connectors  48  are mounted on the surface  46   a.  In an implementation of the invention, daughter connectors  48  are mounted only on the front surface  46   a.  Conductive paths  450  electrically couple electronic components  47   a  and daughter connectors  48 .  
         [0038]    Referring now to FIG. 4D, there is shown a rear view of daughter circuit board  45 . Electronic components  47   b  are mounted to the surface  46   b.  Via  420  allows electrical access to the front side of the daughter board  45 . In an implementation of the invention, no daughter connectors are mounted to surface  46   b.    
         [0039]    Referring now to FIG. 4E, there is shown a sideview of a stacked printed circuit board memory module  49 . In an implementation of the invention, a primary connector  43  on a primary board is electrically and mechanically coupled to a daughter connector  48  on a daughter circuit board  45 . There are no other connectors on either the primary or daughter circuit board. Upper air channel  460  runs along the top of the stacked printed circuit board memory module  49  and provides airflow between electronic components  42   a  on the primary board  40  and the electronic components  47   a  on the daughter board  45 . Improved airflow in this manner improves overall performance of the module  49 .  
         [0040]    Referring now to FIG. 5A, there is shown a bottom view of a stacked printed circuit board memory module  50  including a primary board  10  and three daughter boards  11 ,  38 ,  39 . Shown are various daughter connectors  14   a,    14   b  and primary connectors  3   a,    3   b.  The bottom view of the stacked printed circuit board memory module  50  shows that lower air channels  51  are created when the primary connectors  3   a,    3   b  interconnect with the daughter connectors  14   a,    14   b.  Lower air channels  51  allow air to flow to and from lower air channels  51  to upper air channels  35 . This airflow allows for improved heat dissipation in the memory module thereby increasing overall performance.  
         [0041]    Referring now to FIG. 5B, there is shown a bottom view of an implementation of the stacked printed circuit board memory module  55 . A primary board  40  and a daughter circuit board  45  are connected by daughter connectors  48  and primary connectors  43 . A lower air channel  52  is created when daughter connectors  48  and primary connectors  43  are interconnected. The lower air channel  52  allows for airflow to and from lower air channel  52  and upper air channel  460 . This airflow allows for improved heat dissipation in the memory module thereby increasing overall performance.  
         [0042]    Other implementations are within the scope of the following claims.