Abstract:
A power amplifier output stage that provides multiple power states and mechanisms for enhancing the efficiency of each of its power states. A power amplifier output stage according to the present techniques includes a first output device for driving a load in a first power state and a second output device for driving the load in a second power state along with a matching network for the first power state and a circuit for adapting the matching network to the second power state.

Description:
BACKGROUND 
     Power amplifiers may be employed in a wide variety of electronic systems. For example, power amplifiers may be employed in transmitters to generate transmit signals. Transmitters may be employed in a wide variety of electronic systems including mobile communication devices. 
     A power amplifier may be characterized by an output power and an efficiency. The efficiency of a power amplifier may be defined as a ratio of the output power of the power amplifier and an amount of DC power consumed at an output of the power amplifier. 
     It may be desirable in a variety of electronic systems to employ a power amplifier having a relatively high efficiency. For example, a high efficiency power amplifier for a transmitter in a mobile communication device may reduce power consumption and increase battery life. 
     It may also be desirable in a variety of electronic systems to vary the output power of a power amplifier. For example, it may be desirable in a mobile communication device to increase the strength of a transmit signal when the mobile communication device is far away from a base station and to decrease the strength of the transmit signal when the mobile communication device is close to a base station. 
     A power amplifier having a variable amount of output power may exhibit its maximum efficiency at a predetermined amount of output power. For example, a power amplifier in a transmitter for a mobile communication device may be designed for maximum efficiency at its maximum output power. Unfortunately, an amplifier designed for maximum efficiency at its maximum output power may exhibit a substantially reduced efficiency at lower amounts of output power. A lower efficiency at low power may waste the DC supply power in an electronic device and decrease battery life in a mobile device. 
     SUMMARY OF THE INVENTION 
     A power amplifier output stage is disclosed that provides multiple power states and mechanisms for enhancing the efficiency of each of its power states. A power amplifier output stage according to the present techniques includes a first output device for driving a load in a first power state and a second output device for driving the load in a second power state along with a matching network for the first power state and a circuit for adapting the matching network to the second power state. 
     Other features and advantages of the present invention will be apparent from the detailed description that follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is described with respect to particular exemplary embodiments thereof and reference is accordingly made to the drawings in which: 
         FIG. 1  shows a power amplifier output stage according to the present teachings; 
         FIG. 2  shows one embodiment of a power amplifier output stage; 
         FIG. 3  shows another embodiment of a power amplifier output stage. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a power amplifier output stage  10  according to the present teachings. The power amplifier output stage  10  includes a pair of output devices  16  and  18 , a matching network  12 , and an adapting circuit  14 . The power amplifier output stage  10  drives a load that is represented by a load resistor R 1 . 
     The output devices  16  and  18  drive the load resistor R 1  in a high power state and a low power state, respectively, of the power amplifier output stage  10 . The output devices  16  and  18  may be field-effect transistors or bipolar junction transistors. The size of the output device  16  is preferably substantially larger than the size of the output device  18  and is preferably biased to a proportionally higher electrical current operating point. 
     The output device  16  drives the load resistor R 1  via the matching network  12  in the high power state. The matching network  12  provides impedance matching between an output node  20  of the output device  16  and the load resistor R 1 . The matching network  12  is tuned to optimize the efficiency of the power amplifier output stage  10  in the high power state by transforming R 1  to the desired impedance at the output node  20  given the DC supply voltage to the output device  16 . 
     The output device  18  drives the load resistor R 1  via the adapting circuit  14  and the matching network  12  in the low power state. The adapting circuit  14  adapts the impedance matching at the output node  20  provided by the matching network  12  to that needed at an output node  22  of the output device  18  to optimize the efficiency of the power amplifier output stage  10  in the low power state. 
       FIG. 2  shows one embodiment of the power amplifier output stage  10 . The output devices  16  and  18  are embodied as a pair of field-effect transistors Q 1  and Q 2 . The transistor Q 1  is substantially larger than the transistor Q 2  and is used in the high power state. The transistor Q 2  is used in the low power state. 
     The adapting circuit  14  includes a field-effect transistor Q 3  for switching the power amplifier output stage  10  between its high and low power states. The transistor Q 3  is switched on, i.e. closed, in the high power state and switched off, i.e. opened, in the low power state. In other embodiments, the transistor Q 3  may be a bipolar junction transistor or a mechanical switch or a PIN diode device. 
     The adapting circuit  14  includes a capacitor C 2  and an inductor L 1 . The values of the capacitor C 1  and the inductor L 1  are selected to transform the impedance at the output node  20  to a desired impedance at the output node  22 . The adapting circuit  14  also includes a capacitor C 1  that blocks DC current flow through the transistor Q 3 . 
     In the high power state, the transistor Q 3  is closed, the transistor Q 1  is driven with an input waveform, and the transistor Q 2  is not driven. The closed transistor Q 3  shorts out the capacitor C 2  and the inductor L 1  appears as a shunt on the output node  20 . The closed transistor Q 3  effectively removes the transistor Q 2  from the circuit and the matching network  12  appears in parallel with the inductor L 1  at the output node  20 . The matching network  12  is tuned to absorb the inductance of the inductor L 1  in order to properly load the output node  20  of the transistor Q 1  for efficiency in the high power state. 
     In the low power state, the transistor Q 3  is open, the transistor Q 2  is driven with an input waveform, and the transistor Q 1  is not driven. The capacitor C 2  and the inductor L 1  transform the impedance at the output node  20  up to a desired impedance at the output node  22 . As a consequence, the transistor Q 2  delivers a lower power output signal to a higher impedance load, thereby increasing efficiency in the low power state. 
     The value of the inductor L 1  may be limited to have only a minor effect on the operation of the power amplifier output stage  10  in the high power state. Similarly, the loss associated with the transistor Q 3  has only a minor effect on the operation of the power amplifier output stage  10  in the high power state. The power amplifier output stage  10  does not cause power to flow through switching devices and thereby avoids the insertion loss that may occur in prior power amplifiers. 
       FIG. 3  shows an embodiment of the power amplifier output stage  10  that includes an inductor L 2  between the source of the transistor Q 3  and ground. The value of the capacitor C 2  is relatively large so that it appears as a short circuit. As a consequence, when the transistor Q 3  is closed the inductor L 2  appears to be across the capacitor C 2 . The value of the inductor L 2  is selected so that it resonates with the capacitor C 2  when the transistor Q 3  is closed. The net result is an open circuit between the output node  22  and ground. This effectively removes the inductor L 1  from the circuit in the high power state and prevents the inductor L 1  from loading the output node  20 . 
     The power amplifier output stage  10  in this embodiment also includes a resistor R 2  placed in parallel with the capacitor C 1 . The resistor R 2  has a relatively large value, e.g. 5k ohms. The resistor R 2  enables a DC bias voltage to be maintained at a channel terminal (e.g. drain or source) of the transistor Q 3  when the transistor Q 3  is off, i.e. in the low power state. The DC bias voltage at the channel terminal of the transistor Q 3  helps keep the transistor Q 3  off to maintain the low power state linearity. This avoids a negative voltage on the drain that might switch the transistor Q 3  on and disrupt the low power state. The DC bias voltage at the output node  22  shifts the low voltage peaks of an output waveform from the transistor Q 2  away from a level that might otherwise switch on the transistor Q 3 . 
     The inductor L 2  preferably has a relatively high Q factor. The inductor L 2  may be implemented as a gold wire that is bonded to an underlying ground plane using thermal compression. It may be desirable to keep the on resistance of the transistor Q 3  relatively low because the effective Q of inductor L 2  takes into account the on resistance of the transistor Q 3 . 
     The inductor L 2  in other embodiments may be placed anywhere in the circuit branch from the capacitor C 1  to the transistor Q 3  to ground. In addition, the source and drain of the transistor Q 3  may be flipped in other embodiments. 
     The foregoing detailed description of the present invention is provided for the purposes of illustration and is not intended to be exhaustive or to limit the invention to the precise embodiment disclosed. Accordingly, the scope of the present invention is defined by the appended claims.