Abstract:
An arrangement by which a sinusoidal wave is modulated in phase and amplitude in response to groups of bits includes an input (1) for receiving the groups of bits, a phase shifting circuit (5, 7) for producing two phase-shifted components of the wave and a modulating circuit for modulating the amplitude of the two components as a function of the groups. The modulating circuit includes a ROM (25), addressed by part of the n bits of the bit groups for producing an initial amplitude value, and a calculating unit (30) for obtaining final amplitude values by changing original values according to the remaining part of the bits of the bit groups.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a modulating arrangement for phase and amplitude modulation of a wave, the arrangement comprising an input for receiving groups of bits, a phase shifting circuit for producing two phase-shifted components of the said wave and a modulating circuit for modulating the amplitude of the two components as a function of the said groups. 
     Such arrangements find important applications, specifically in modems, and similar equipment used for data transmission. 
     Currently, ever higher transmission rates are required whereas the pass-bands of the transmission channels remain limited. A means for harmonising these contradictory requirements consists of using a combined amplitude and phase modulation of a carrier wave. To each amplitude-phase combination there corresponds a group of bits so that for obtaining high rates a large number of combinations has to be used. For example, Recommendation V.33 of the CCITT indicates, for a rate of 14,400 bits per second, the use of 128 combinations, each of which representing a group of 7 bits. 
     It will be evident that that for making these combinations, memories which are addressed by the said groups and produce the phase and amplitude information signals of the carrier in response thereto, are preprogrammed. However, it is estimated that the size of such a memory, especially for fulfilling the above Recommendation, is too large because this arrangement is a component of an integrated modem. This type of modem uses a signal processor as described in the article by L. MARY &#34;Processeur de signaux: capacite et performances&#34; published in the journal TOUTE L&#39;ELECTRONIQUES No. 527, October 1987, pages 52-60. The processors are often associated with rather small-sized memories on the same chip, so that it is impossible to store many combinations. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a modulating arrangement of the type mentioned in the preamble, which is particularly intended for being inserted in a modem of the integrated type and which thus does not require a large memory for storing many combinations. 
     Therefore, such a modulating arrangement is characterized in that the modulating circuit comprises storage means addressed by part of the bits of the bit groups for producing an original (or initial) amplitude value, and calculating means for obtaining the final amplitude values by changing the original values according to the remaining part of the bits of the bit groups. 
     BRIEF DESCRIPTION OF THE DRAWING 
     With the following description accompanied by the annexed drawings, all this given by way of a non-limiting example, it will be better understood how the invention can be realised, in which: 
     FIG. 1 shows an embodiment of a modulating arrangement according to the invention, 
     FIG. 2 shows a constellation of amplitude-phase combinations relating to the normal transmission rate according to Recommendation V.33, 
     FIG. 3 shows the preferred embodiment of a modulating arrangement in accordance with the invention, 
     FIG. 4 shows a constellation relating to the speed of the transmission foldback still according to Recommendation V.33, 
     FIG. 5 shows a flowchart representing the operation of the arrangement of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1 the reference 1 shows a register intended for containing a group of 7 bits Y0, Y1, Y2, Q3, Q4, Q5 and Q6; 128 amplitude-phase combinations of one carrier wave will correspond with these 7 bits. These 128 combinations are shown in the form of the transmission constellation of FIG. 2. All this is in accordance with Recommendation V.33 mentioned hereinbefore. In order to obtain these combinations, it is possible to modulate the amplitude of two quadrature components of the carrier. In FIG. 1, the oscillator 5 produces a component Re and a phase shifter 7 shifting this component by π/2 for producing a second component Im. Two amplitude modulators 8 and 10 modulate these two respective components. By discretely acting on these different amplitudes the 128 points of the FIG. 2 will be obtained of which each point represents a combination of amplitude and phase. The Table I shown hereinafter provides the value of the groups GR: Q6, Q5, Q4, Q3, Y2, Y1 and Y0 with respect to each of these points and the amplitudes of the components Im and Re. An adder 12 adds up these values in order to provide them at output 13. 
     
                       TABLE I______________________________________  GR            Re     Im______________________________________P1       0000110         -2     +9P2       0001110         +2     +9P3       0000011         -3     +8P4       1001111         -1     +8P5       0001011         +1     +8P6       1000111         +3     +8P7       1100100         -4     +7P8       1001010         -2     +7P9       1110100          0     +7P10      1000010         +2     +7P11      1010100         +4     +7P12      1011101         -5     +6P13      1100001         -3     +6P14      1111101         -1     +6P15      1110001         +1     +6P16      1101101         +3     +6P17      1010001         +5     +6P18      1010110         -6     +5P19      1011000         -4     +5P20      0010110         -2     +5P21      1111000          0     +5P22      0011110         +2     +5P23      1101000         +4     +5P24      1011110         +6     +5P25      1010011         -7     +4P26      1101111         -5     +4P27      0010011         -3     +4P28      0101111         -1     +4P29      0011011         +1     +4P30      0100111         + 3    +4P31      1011011         +5     +4P32      1100111         +7     +4P33      1000100         -8     +3P34      1101010         -6     +3P35      0100100         -4     +3P36      0101010         -2     +3P37      0110100          0     +3P38      0100010         +2     +3P39      0010100         +4     +3P40      1100010         +6     +3P41      0000100         +8     +3P42      0001101         -9     +2P43      1000001         -7     +2P44      0011101         -5     +2P45      0100001         -3     +2P46      0111101         -1     +2P47      0110001         +1     +2P48      0101101         +3     +2P49      0010001         +5     +2P50      1001101         +7     +2P51      0000001         +9     +2P52      0001000         -8     +1P53      1101110         -6     +1P54      0011000         -4     +1P55      0110110         -2     +1P56      0111000          0     -1P57      0111110         +2     +1P58      0101000         +4     +1P59      1111110         +6     +1P60      1001000         +8     +1P61      1110011         -7      0P62      1111111         -5      0P63      0110011         -3       0P64      0111111         -1      0P65      111011          +1      0P66      110111          +3      0P67      111011          +5      0P68      110111          +7      0P69      00100           -8     -1P70      111010          -6     -1P71      101100          -4     -1P72      111010          -2     -1P73      111100           0     -1P74      110010          +2     -1P75      011100          +4     -1P76      110010          +6     -1P77      001100          +8     -1P78      000101          -9     -2P79      001001          -7     -2P80      010101          -5     -2P81      0101001         -3     -2P82      0110101         -1     -2P83      0111001         +1     -2P84      0100101         +3     -2P85      0011001         +5     -2P86      1000101         +1     -2P87      0001001         +9     -2P88      0000000         -8     -3P89      1100110         -6     -3P90      0010000         -4     -3P91      0100110         -2     -3P92      0110000          0     -3P93      0101110         +2     -3P94      0100000         + 4    -3P95      1101110         +6     -3P96      1000000         +8     -3P97      1100011         -7     -4P98      1011111         -5     -4P99      0100011         -3     -4 P100    0011111         -1     -4 P101    0101011         +1     -4 P102    0010111         +3     -4 P103    1101011         +5     -4 P104    1010111         +7     -4 P105    1011010         -6     -5 P106    1101100         -4     -5 P107    0011010         -2     -5 P108    1111100          0     -5 P109    0010010         +2     -5 P110    1011100         +4     -5 P111    1010010         +6     -5 P112    1010101         -5     -6 P113    1101001         -3     -6 P114    1110101         -1     -6 P115    1111001         +1     -6 P116    1100101         +3     -6 P117    1011001         +5     -6 P118    1010000         -4     -7 P119    1000110         -2     -7 P120    1110000          0     -7 P121    1001110         +2     -7 P122    1100000         +4     -7 P123    1000011         -3     - 8 P124    0001111         -1     -8 P125    1001011         +1     -8 P126    0000111         +3     -8 P127    0001010         -2     -9 P128    0000010         +2     -9______________________________________ 
    
     In accordance with the invention the modulating arrangement comprises a memory 25 addressed by the bits Q6, Q5 and Q4 and produces in a binary form original (or initial) amplitude values with respect to the components Re, Im; these amplitude values &#34;x&#34; and &#34;y&#34; are shown for simplicity in the decimal system used in the Table II below and may be viewed as a stored constellation of eight points which are indicated as circles in FIG. 2 centered about eight points in the normal transmission constellation with which they coincide. 
     
                       TABLE II______________________________________Q6        Q5    Q4           x    y______________________________________0         0     0            -8   -30         0     1            -4   -30         1     0            +4   -30         1     1             0   -31         0     0            +8   -31         0     1            -4   -71         1     0            +4   -71         1     1             0   -7______________________________________ 
    
     The arrangement according to the invention expands the stored constellation into the transmission constellation utilizing a calculating unit 30 for obtaining the final amplitude values Re and Im by modifying the values &#34;x&#34; and &#34;y&#34; as a function of the bits Q3, Y2, Y1 and Y0. This unit 30 first comprises a multiplexer 40 which provides at its output the value Y1 which either has the initial value &#34;y&#34; or the value -y-2; the latter value is obtained by means of an inverter 41 and an adder 42 which adds &#34;-2&#34; to the value produced by the inverter 41. It should be recognized by examining FIG. 2 that a shifting of points in the stored constellation by 2 units along a coordinate will cause them to coincide with various other points in the transmission constellation. The position of the multiplexer 40 is determined by the bit Q3 in a manner such that the values x1 and y1 established on the basis of x and y can be written as: 
     If Q3=0 then x1=x and y1=y 
     If Q3=1 then x1=x and y1=-y-2. 
     Two further multiplexers 50 and 52 are provided for supplying at their respective outputs the values x2 and y2. The value x2 can be either the value x1 (or x) or the value -x1+1 which is obtained by means of an inverter 56 and an adder 58 adding &#34;+1&#34; to the value produced by the inverter 56. The value y2 may be either the value y1 or the value -y1-1 which is obtained by means of an inverter 66 and an adder 68; this adder 68 adds the value &#34;-1&#34; to the value produced by the inverter 66. It should be recognized by again examining FIG. 2 that a shifting of points in the stored constellation along both coordinates simultaneously by one unit will cause them to coincide with still further points in the transmission constellation. The position of the multiplexers 50 and 52 is determined by the logic value of a signal appearing at the output of an &#34;EXCLUSIVE-OR&#34; gate 59 so that the following may be written: 
     If Y1.sup.⊕ Y0=0 then x2=x1   y2=y1 
     If Y1.sup.⊕ Y0=1 then x2=-x1+1   y2=-y1-1 
     In order to produce the final values xF and yF which determine the amplitude of the components Re and Im, two multiplexers 60 and 62 having four positions are provided which receive at their inputs the values x2, y2, -x2 and -y2 whereas the negative values are obtained via the inverters 65 and 66 respectively. The positions of these multiplexers are determined by the bits Y2 and Y1. The Table III shown hereinbelow provides the values xF and yF as a function of Y2 and Y1 which corresponds to selectively rotating a vector having the components X2, Y2, clockwise about the origin of an X, Y plane by 0°, 90°, 180° or 270°. 
     
                       TABLE III______________________________________Y2      Y1             xF     yF______________________________________0       0               x2     y20       1               y2    -x21       0              -x2    -y21       1              -y2     x2______________________________________ 
    
     FIG. 3 shows the preferred embodiment of an arrangement according to the invention. It is built around a microprocessor set 50 comprising a random access memory (RAM) and a memory containing the operation program as well as data specifically those indicated in Table III (ROM), as well as the actual microprocessor (μP). This set communicates with external lines via a data line BUSD for receiving the data specifically from the register 1 and supplying them to final registers 60 and 61 which contain the final values xF and yF respectively. A line BUSA enables to select these different registers 1, 60 and 61 as well as a register 65. This register comprises a foldback indication. In fact, when referring to Recommendation V.33, it is provided to transmit data at a foldback rate which is 12,000 bits/s instead of the rate of 14,400 bits/s as implied by the constellation represented in FIG. 2. The foldback rate thus implies a different constellation represented in FIG. 4. The Table IV shows groups of foldback bits Q5, Q4, Q3, Y2, Y1 and Y0 as a function of final values xF and yF. 
     
                       TABLE IV______________________________________             xF   yF______________________________________R1       010100         -7     +7R2       010001         -5     +7R3       111110         -3     +7R4       000111         -1     +7R5       011100         +1     +7R6       011001         +3     +7R7       110110         +5     +7R8       010111         +7     +7R9       110101         -7     +5R10      110000         -5     +5R11      111011         -3     +5R12      000010         -1     +5R13      100101         +1     +5R14      100000         +3     +5R15      110011         +5     +5R16      010010         +7     +5R17      011110         -7     +3R18      100111         -5     +3R19      001100         -3     +3R20      001001         -1     +3R21      101110         +1     +3R22      001111         +3     +3R23      111100         +5     +3R24      111001         +7     +3R25      011011         -7     +1R26      100010         -5     +1R27      101101         -3     +1R28      101000         -1     +1R29      101011         +1     +1R30      001010         +3     + 1R31      000101         +5     +1R32      000000         +7     +1R33      000100         -7     -1R34      000001         -5     -1R35      001110         -3     -1R36      101111         -1     -1R37      101100         +1     -1R38      101001         +3     -1R39      100110         +5     -1R40      011111         +7     -1R41      111101         -7     -3R42      111000         -5     -3R43      001011         -3     -3R44      101010         -1     -3R45      001101         +1     -3R46      001000         +3     -3R47      100011         +5     -3R48      011010         +7     -3R49      010110         -7     -5R50      110111         -5     -5R51      100100         -3     -5R52      100001         -1     -5R53      000110         +1     -5R54      111111         +3     -5R55      110100         +5     -5R56      110001         +7     -5R57      010011         -7     -7R58      110010         -5     -7R59      011101         -3     -7R60      011000         -1     -7R61      000011         +1     -7R62      111010         +3     -7R63      010101         +5     -7R64      010000         +7     -7______________________________________ 
    
     The operation of the preferred embodiment of the invention will now be explained with the aid of the flowchart of FIG. 5. 
     The structure of the program shown by means of this flowchart starts with the box K1 which indicates a test of the value RP. This value RP contained in the register 65 indicates, if the value is &#34;1&#34;, that transmission is to take place at the foldback rate and if not, that this transmission is to take place at the normal rate. 
     If the normal rate has to be used, box K2 is proceeded to where it is indicated that 7 bits to be transmitted Q6, Q5, Q4, Q3, Y2, Y1, Y0 are read. As a function of the bits Q6, Q5, Q4, values are given to x and y in accordance with the Table of box K3 which is identical with the Table II. Then, at box K4, the value of the bit Q3 is tested. If this is equal to &#34;1&#34; the value of y is determined: this new value is -y-2 as is indicated in box K5. In box K6 the result of the &#34;EXCLUSIVE-OR&#34; operation performed with the elements Y0 and Y1 is tested. If the result is &#34;0&#34; a part called PPC of the program is proceeded to. If the result of the operation is &#34;1&#34; then a transformation is performed as is indicated in box K7, that is to say, that x assumes the value -x+1 and y the value -y-1. Finally, the part called PPC of the program is proceeded to. 
     If the result of the test of box K1 is positive, box K10 is proceeded to where the bits Q5, Q4, Q3, Y2, Y1 and Y0 used for the foldback rate are read. As a function of the elements Q4 and Q3 whose values may be 00, 01, 10 and 11 the values 7, 3, 7, -1 are associated to x (see box K11) and the values 1, -3, -7 and -7 are associated to y, these values being viewable as a further stored constellation of four points, applicable to the foldback transmission rate, which are indicated as circles centered about four points on the foldback transmission constellation of FIG. 4. Then, at box K12, the value of the bit Q5 is tested. If this value is &#34;0&#34; box K13 is proceeded to; if this is &#34;1&#34; the value y+2 is substituted for the value x and the value x-2 is substituted for the value y. This is indicated at box K14. At box K13 the result of the EXCLUSIVE-OR operation performed with the bits Y0 and Y1 is tested. If the result is &#34;0&#34; the part called PPC of the program is proceeded to. If the result is &#34;1&#34; a transformation as indicated at box K15 is effected, that is to say, that the value x assumes the value -x+2 and that y assumes the opposite value -y and that the part PPC of the program is proceeded to. 
     This part of the program is implemented both for the processing at the normal rate and at the foldback rate and it should be observed that this is advantageous because in this manner efficient use is made of the program lines which have to be introduced into the ROM memory of the set 50. 
     This part of the program is commenced in box K20 where the value Y2, Y1 is tested; if this is different from &#34;01&#34;, box K21 is proceeded to, if it is equal to &#34;01&#34; box K23 is proceeded to where the values of x and y become y and -x respectively. At box K21 it is tested whether the value of Y2, Y1 is identical with &#34;10&#34;; if there is no identity, box K22 is proceeded to; if there is identity, box K24 is proceeded to where the values of x and y become -x and -y respectively. At box K22 it is tested whether the value Y2, Y1 is identical with &#34;11&#34;; if there is no identity, box K26 is proceeded to where the values of x and y are stored in the registers 60 and 61. If there is identity, box K25 is proceeded to which indicates a change of x and y into -y and x. From box K25 one proceeds to box K26.