Abstract:
Apparatus for generating a plurality of pilot signals is disclosed. First and second sets of timers are fed by a common system clock. Each timer of both the first and second sets of timers is adapted to generate a gating pulse a predetermined time period after the initiation of a timing cycle in accordance with a timing characteristic peculiar to each timer. The timing characteristic of the timers in both the first and second sets are chosen such that at least one of the timers in the first set generates a gating pulse at the same time that at least one of the timers in the second set generates a gating pulse. The gating signals generated by each of the first set of timers are applied to one input of each of a plurality of two input pilot signal gates. The gating signal generated by each of the second set of timers is applied to the remaining input of a different one of the plurality of two input pilot signal gates. Each of the pilot signal gates generates a pilot signal whenever a gating signal is applied to each of its inputs.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a system for the distribution of pilot signals, particularly distribution of electrical energy. 
     Known systems for distribution of electrical energy in offices, plants, hospitals, residences, etc., are normally based on one of two typical schemes: firstly, the electrical energy required for supplying the equipment to be operated is controlled by switches arranged at the most convenient locations for use; and secondly, the electrical energy required for supplying the equipment is controlled by suitable relays operated through suitable electric circuits by control pushbuttons. The wiring required in both of the above systems are substantially complex. As a result, the material and labor costs of installation are high. Additionally the prior art systems are highly rigid since it is difficult to modify the number of wires and the location of the equipment being controlled and the controls controlling the system. This is particularly true because of the commonly established practice of having such circuits in proper walled canalizations. 
     It is the object of the present invention to provide a novel system for general distribution of pilot signals, and particularly distribution of electrical energy, enabling to provide a saving both in the amount of required wires and installation labor, as well as a large use flexibility, so that either the number or the location of the operation equipments and control members can be readily modified. 
     BRIEF SUMMARY OF THE INVENTION 
     According to the invention, the foregoing objects are obtained by a pilot signal distributing system comprising a high frequency pulse generator; first and second pluralities of timing circuits that are connected to the input of a pulse distributing line for cyclical and concurrent operation; each of the circuits being capable of providing a gating signal, after some time peculiar to each circuit, from operation starting; the gating signals provided by the timing circuits of the first plurality being supplied through respective normally open switches, as operated by an operator, to a common gating signal transmission line; at least one timing circuit of the first plurality having the same characteristic time as at least one timing circuit of the second plurality, whereby operative couplings are provided between the circuits of said first and second pluralities; and further comprising a plurality of receiver devices which at one input are connected to the output of a timing circuit of said second plurality to receive a first gating signal, and at another input to said transmission line to receive a further gating signal and at the output to an operating circuit which is energized by a pilot signal when the gating signals are simultaneously applied to the input of the receiver device; the arrangement being such that a pilot signal is provided at the output of said receiver device(s) when the latter have the input thereof supplied with gating signals from the timing circuits of said first and second pluralities having the same characteristic times. 
    
    
     BRIEF DESCRIPTION OF THE INVENTION 
     By mere way of example, the present system will now be described with reference to some preferred embodiments as shown in the accompanying drawings, in which: 
     FIG. 1 is a block diagram for a system constructed in accordance with the principles of the present invention; 
     FIG. 2 shows a first embodiment for the system of FIG. 1; 
     FIG. 3 is an operation diagram of the embodiment shown in FIG. 2; 
     FIG. 4 shows a second embodiment for the system of FIG. 1; 
     FIG. 5 is an operation diagram of the embodiment shown in FIG. 4; 
     FIG. 6 shows a third embodiment for the system of FIG. 1; 
     FIG. 7 shows an operation diagram of the embodiment shown in FIG. 6; 
     FIG. 8 shows a fourth embodiment for the system of FIG. 1; and 
     FIG. 9 shows an embodiment for an end portion of a timing circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the general scheme of FIG. 1, CK designates a high frequency pulse generator (clock) which generates a time period indicating pulse at the initiation of each of a plurality of system timing periods. LD designates distribution line which receivers time period initiation pulses, and T 1 , T 2  . . . T K  and T 1  &#39;, T 2  &#39;. . . T K  &#39;, respectively, designate a first and a second plurality of timing circuits whose inputs are connected to line LD such that each of the timing circuits are cyclically and simultaneously operated responsive to each of the time periods indicating pulses. The timing circuits generate a signal, hereinafter referred to as &#34;gating signal&#34;, a given time interval ΔT 1 , ΔT 2 , . . . ΔT K  after the initiation of each of the system timing periods. A particular time interval ΔT 1 , ΔT 2 , . . . ΔT K  is peculiar to each circuit. The gating signals generated by the first plurality of timing circuits T 1 , T 2 , . . . T K  are supplied to a common gating signal transmission line LT through respective switches I 1 , I 2 , . . . I K , which are normally open and which close on an operator&#39;s command. These switches reopen as soon as the command is cut off. 
     One or more timing circuits of the first plurality of timing circuits have the same characteristic time interval as one or more timing circuits of the second plurality of timing circuits, so that operative couplings between the circuits of said first and second plurality of timing circuits can be provided. As used herein, the term &#34;operatively coupled&#34; timing circuits are those circuits in the first and second sets of timing circuits which have the same characteristic time intervals. 
     In the example disclosed, the characteristic time interval ΔT 1  associated with both timing circuits T 1  and T K  is the same as that for timing circuit T 1  &#39;; the characteristic time interval ΔT 2  for timing circuit T 2  is the same as that for timing circuits T 2  &#39; and T K  &#39;; the characteristic time interval ΔT 3  for T 3  is the same as that for timing circuit T 3  &#39; and the characteristic time interval ΔT 4  for timing circuit T 4  is the same as that for timing circuit T 4  &#39; to provide for operative coupling of the following circuits: T 1  and T K  with T 1  &#39;; T 2  with T 2  &#39; and T K  &#39;; T 3  with T 3  &#39;; and T 4  with T 4  &#39;. 
     Still referring to FIG. 1, R 1 , R 2 , . . . R K  designate a plurality of receiver devices, and U 1 , U 2 , . . . U K  designate a plurality of operating devices supplied by line LA, which may be an electric, pneumatic or the like line. As shown, supply for U 1 , U 2 , . . . U K  can be provided through respective control devices DC 1 , DC 2 , . . . DC K  under the control of receivers R 1 , R 2 , . . . R K . An input 1 of each of the receivers receives a gating signal from the output of a different one of the timing circuits T 1  &#39;, T 2  &#39;, . . . T K  &#39;. An input of each receiver device receives another gating signal from line LT. The output 3 of each receiver is coupled to a respective control device DC 1 , DC 2 , . . . DC K . A pilot signal is generated by each receiver device when a gating signal appears at both inputs to the receiver. As a result, each operating device is activated only when gating signals from operatively coupled timing circuits of said first and second plurality of timing circuits are simultaneously applied to both inputs of the receiver device associated with the particular operating device. For example, operating device U 4  is supplied only when switch I 4  is operated and devices U 2  and U K  are simultaneously supplied only when switch I 2  is operated. 
     Timing circuits T 1 , T 2 , T K  and T 1  &#39;, T 2  &#39;, . . . T K  &#39; can be provided in different ways, as far as capable of operating as above described; accordingly, the pulses emitted from clock CK are of a type which can be detected by the type of timing circuit selected so that the timing circuits selected can be simultaneously and cyclically operated responsive to each time period initiating pulse generated by the clock CK. Moreover, depending on the type of timing circuits selected, it is possible to utilize separate transmission and pulse distribution lines LT and LD (as shown in FIG. 1), or a single line for both signals (see FIGS. 6 and 8). 
     Receivers R 1 , R 2 , . . . R K  and control devices DC 1 , DC 2 , . . . DC K , respectively, can be simple logical gates and electromagnetic relays or electrovalves; switches I 1 , I 2 , . . . I K  can be simple pushbuttons, electronic switches or the like, as required. Such switches should, however, be capable of remaining in a closed condition for a sufficient time interval. 
     When having predetermined the installation location for each of the timing circuits, the above shown system makes it possible to minimize the length of line LD (and also line LT) which has only to meet the requirement of interconnecting all of said circuits. Similarly, the length of supply line LA can be minimized. For example, the lines could be combined, whereby the whole installation can be arranged in a single cable and in a single canalization. 
     Additionally, since each of the timing circuits and each of the operating devices can be placed in any desired location, the desired flexibility is provided; it being possible to modify the location for each of the devices without altering the system operation. 
     It is a further advantage of the present system that all of the timing circuits are identical, the only difference residing in the different formulation for providing the different characteristic time intervals. The receiving circuits are also identical. 
     The system will now be disclosed as provided with two types of timing circuits, one of which uses monostable multivibrators (FIGS. 2 and 3), and the other of which uses electronic counters (FIGS. 4 to 8). In both cases, the receivers are made with AND gates. 
     In the embodiment shown in FIG. 2, each of the timing circuits comprise a monostable multivibrator and a firing circuit. The first and second plurality of timing circuits are designated at MVM 1  -CI 1M , MVM 2  -CI 2M  and MVM 1  &#39;-CI 1M  &#39;, MVM 2  &#39;-CI 2M  &#39;, respectively. 
     For purposes of illustration, it will be assumed that timing circuit MVM 1  -CI 1M  is operatively coupled with MVM 1  &#39;-CI 1M  &#39;, and timing circuit MVM 2  -CI 2M  is operatively coupled with MVM 2  &#39;-CI 2M  &#39;. Multivibrators MVM 1 , MVM 2 , MVM 1  &#39; and MVM 2  &#39; are connected to line LD (which is separated from line LT) and receive the time period initiation pulses (FIG. 3a) provided by clock CK 1 . 
     Each firing circuit CI 1M , CI 2M , CI 1M  &#39; and CI 2M  &#39; provides a gating signal at its end of the conducting state of the respective multivibrators; the length of said conducting state defining the characteristic time for it respective timing circuit. In accordance with the above assumption, the conduction time for multivibrator MVM 1  is the same as that for MVM 1  &#39;, and conduction time for multivibrator MVM 2  is the same as that for MVM 2  &#39;. FIG. 3b shows the output signal generated by multivibrators MVM 1  and MVM 1  &#39;. FIG. 3c shows the gating signal generated by firing circuits CI 1M  and CI 1M  &#39;. As shown in FIG. 3c, each gating signal is generated by firing circuits CI 1M  and CI 1M  &#39; ΔT 1M  seconds after the initiation of the new system timing period as defined by the time interval initiation pulses generated by clock CK 1 . It, after a time interval ΔT 1M  from the generation of time interval indication pulse, switch I 1  is closed for a sufficient time, inputs 1 and 2 of gate P 1  &#39; will have simultaneously applied thereto the two gating signals; one applied to input 1 directly by firing circuit CI 1M  &#39; and one applied to input 2 through line LT by firing circuit CI.sub. 1M. In such a case, a pilot signal will be generated at output 3 of gate P 1  &#39; operating its respective operating device (not shown). 
     Similarly, FIGS. 3d and 3e illustrate, respectively, the outputs of multivibrators MVM 2  and MVM 2  &#39; and the gating signals generated by firing circuits CI 2M  and CI 2M  &#39; following the time interval ΔT 2M . 
     Should switch I 2  be closed for a sufficient time, after the termination of time periods ΔT 2M  inputs 1 and 2 of gate P 2  &#39; will have simultaneously applied thereto the two gating signals provided by firing circuits CI 2M  &#39; and CI 2M , respectively. Should such a condition occur, a pilot signal will appear at the output of gate P 2  &#39;. 
     FIG. 3f shows the gating signals appearing on line LT under the following opening and closing conditions for the two switches I 1  and I 2  : 
     I 1  and I 2  open: no signal appears on line LT; 
     I 1  closed and I 2  open: those signals appear as shown in FIG. 3c; 
     I 1  open and I 2  closed: those signals appear as those shown in FIG. 3e; 
     I 1  and I 2  closed: both signals of FIG. 3c and FIG. 3e appear, but time separated. 
     FIGS. 3g and 3h show the pilot signals at the output of gates P 1  &#39; and P 2  &#39;, respectively, under the above mentioned conditions of opening and closing for switches I 1  and I 2 . 
     From the foregoing, it is apparent that a pilot signal appears at the output of any given gate only when the switch associated with that gate is closed. 
     In the embodiment shown in FIG. 4, each of the timing circuits comprise an electronic counter and a comparing circuit. The timing circuits defining the first and second plurality of timing circuits are designated C 1  -CS 1 , C 2  -CS 2  and C 1  &#39;-CS 1  &#39;, C 2  &#39;-CS 2  &#39;, respectively. For purposes of illustration, it will be assumed that timing circuit C 1  -CS 1  is operatively coupled with C 1  &#39;-CS 1  &#39; and timing circuit C 2  -CS 2  with C 2  &#39;-CS 2  &#39;. That is, it will be assumed that the characteristic times for C 1  -CS 1  and C 1  &#39;-CS 1  &#39; are identical while the characteristic times for C 2  -CS 2  and C 2  &#39;-CS 2  &#39; are identical. 
     The inputs of counters C 1 , C 2 , C 1  &#39; and C 2  &#39; are connected to line LD (which is separated from line LT), either directly or through zeroing devices DA 1 , DA 2 , DA 1  &#39; and DA 2  &#39;, for receiving both the counting pulses (see positive pulses of FIG. 5a) and time interval initiating pulses (see negative pulses of FIG. 5a) supplied by clock CK 2 . 
     Comparing circuits CS 1 , CS 2 , CS 1  &#39; and CS 2  &#39; compare a characteristic value of their own with the count in its associated counter. Since C 1  -CS 1  is operatively coupled to C 1  &#39;-CS 1  &#39;, the characteristic value of circuit CS 1  is the same as that of circuit CS 1  &#39;. Similarly, the characteristic value of circuit CS 2  is the same as that of circuit CS 2  &#39;. The characteristic value of each of the comparing circuits define the characteristic time interval following which, from counter zeroing or resetting (i.e. the initiation of each system timing period), each of the timing circuits generates a gating signal. 
     In FIG. 5b, there is shown at N 1  the characteristic value of circuits CS 1  and CS 1  &#39;, which is compared with the count level of counters C 1  and C 1  &#39;, and at ΔT 1C  the characteristic time of the coupled timing circuits C 1  -CS 1  and C 1  &#39;-CS 1  &#39;. In the example, value N 1  is cyclically attained after time interval ΔT 1C  defined by three counter counting pulses. 
     If switch I 1  is closed for a sufficient time after the termination of each time interval ΔT 1C , inputs 1 and 2 of gate P 1  &#39; will have simultaneously applied thereto the two gating signals supplied directly from circuit CS 1  &#39; and through line LT from circuit CS 1 , of which one is shown in FIG. 5c. Then, at output 3 of gate P 1  &#39;, a pilot signal will appear for operation of the respective operating device. 
     Similarly, at N 2  larger than N 1 , there is shown the characteristic value of circuits C 2  and C 2  &#39;, and at ΔT 2C  larger than ΔT 1C  the characteristic time of the coupled timing circuits C 2  -CS 2  and C 2  &#39;-CS 2  &#39;. See FIGS. 5d and 5a. In the example, value N 2  is cyclically attained after interval time ΔT 2C  by five counter counting pulses. 
     Should switch I 2  be closed for a sufficient time after the termination of time interval ΔT 2C , inputs 1 and 2 of gate P 2  &#39; would have simultaneously applied thereto the two gating signals supplied from circuits CS 2  and CS 2  &#39;, of which one is shown in FIG. 5e. In such a case, a pilot signal will appear at output 3 of gate P 2  &#39;. As to FIGS. 5f, 5g and 5h, the same is true as explained in connection with FIGS. 5c, 5d and 5e. 
     In the embodiments shown in FIGS. 6 and 8, comprising two variants or modifications to the embodiment of FIG. 4, only line LD is used. In these embodiments, line LD serves to distribute both the pulses of clock CK3, and to transmit the gating signals. In both embodiments, the counter zeroing or resetting device has been omitted and the three types of signals (that is, counting pulses, time period initiation pulses and gating signals) to be supplied on the single line are suitably differentiated. To this end, and referring to FIG. 7, the count signals may be positive pulses, the time period initiator pulses may be negative pulses (see FIG. 7a), and the gating signals may be positive pulses having a duration which is longer than that of the count pulses but which are of less duration less than the interval between two clock consecutive pulses (see FIGS. 7f and 7g). Again, such signals are provided by firing circuits having the function of forming circuits. 
     FIG. 6 shows the firing-signal forming circuits CI 1C  and CI 2C  connected between the comparing circuits CS 1  and CS 2  and switches I 1  and I 2 . FIGS. 7h, 7i and 7l, respectively, show the signals appearing on line LD and at the output of gates P 1  &#39; and P 2  &#39; under the several opening and closing conditions of switches I 1  and I 2 . Of course, gates P 1  &#39; and P 2  &#39; are nonresponsive to the pulses of clock CK 3 . FIGS. 7b, 7c, 7d and 7e correspond to FIGS. 5b, 5c, 5d and 5e. 
     Similarly, in the embodiment of FIG. 8, CI 1a , CI 1b , CI 2a  and CI 2b  respectively denote the firing-signal forming circuits at the output of comparing circuits CS 1a , CS 1b , CS 2a  and CS 2b . In this embodiment, the comparing circuits compare their respective characteristic value with the count level of a common counter. In the example, circuits CS 1a , CS 1b , CS 2a  &#39; and CS 2b  &#39; compare the output of counter CC 1  and circuits CS 2a , CS 2b , CS 1a  &#39; and CS 1b  &#39; compare the output of counter CC 2 . 
     In the foregoing discussion, it was referred by way of example to such comparing circuits as to provide a comparison between two quantities, that is the count level of the counter and the characteristic level of the comparing circuit. 
     However, it is evident that the foregoing is also true where the comparison is effected between logical networks, in which case the gating signal is emitted when the logical configuration of the comparing circuits is coincident with that of the counter. 
     FIG. 9 illustrates a simple embodiment for a comparing circuit CS made of logical networks and connected to the end stage SF of an electronic counter having three binary stages, each of which comprising a bistable circuit (flip-flop) B a , B b  and B c . Each of said flip-flops are provided with two transistors T ao  -T a1 , T bo  -T b1  and T co  -T c1 , having the emitters thereof grounded, the collectors comprising the outputs connected to power supply +E 1  through respective resistors, and the bases connected to the remaining part of the counter circuit, not shown. 
     Comparing circuit CS comprises three diodes D a , D b  and D c , the cathode of which are respectively connected both to the collectors of transistors T ao , T bo  and T co  through disconnectable connections H ao , H bo  and H co  and to the collectors of transistors T a1 , T b1  and T c1  through disconnectable connections H a1 , H b1  and H c1 , and the anodes of which, as connected to form output U, are supplied through a common resistor R from supply +E 2 . 
     Connections H ao , H a1 , H bo , H b1 , H co  and H c1  are connections or jumpers that are variously cut off depending on the logical combination by which the logical combination of the counters is to be compared. 
     Assume that after the counter resetting pulse, the logical configuration at outputs U ao  -U a1 , U bo  -U b1  and U co  -U c1  of flip-flops B a , B b  and B c  is 01, 01, 01, it results that the configurations at said outputs will be 10, 10, 01 at the third count pulse, and 10, 01, 10 at the fifth count pulse. 
     Therefore, it is apparent that when desiring to provide for the gating signal of FIGS. 5c and 7c, it will be required to break or cut off connections H a1 , H b1  and H co  so that no diode has its cathode grounded, while just at the third pulse a positive signal is provided at output U. 
     Similarly, when desiring to provide for the gating signal of FIGS. 5e and 7e, connections H a1 , H bo  and H cl  will have to be cut off so that no diode has its cathode grounded, while just at the fifth pulse a positive signal is provided at output U. 
     Cut off of the connections can be mechanically or electrically accomplished; in this latter case, the connections comprise fuses and cut off is provided by applying a suitable voltage supply to output U, after prearranging the outputs of flip-flops at the logical configuration corresponding to the desired logical combination. 
     Reference was made to a three-diode type of comparing circuit CS, but it is apparent that diodes and associated connections would vary depending on the amount of bistable circuits or flip-flops of the end stage of the counter. 
     The advantage of said comparing circuit is that the some can be provided in series, and can be subsequently coded depending on requirements by merely cutting off the connections.