Abstract:
An infrared radiation detection device utilizing an array of metal electrodes deposited on the insulated surface of a suitable semiconductor material such as an indium antimonide substrate. The detector electrodes are read out by discharging each electrode to a preselected voltage through an integrating capacitor. The charge accumulated on each integrating capacitor is related to the charge collected at the insulator substrate interface under each detector electrode due to interaction of the infrared radiation with the indium antimonide substrate. The integrating capacitors and related charging and switching circuitry are located on a silicon substrate. The integrating capacitors and related circuitry on the silicon substrate are connected to the detector electrodes on the indium antimonide substrate by means of an array of metal tabs fabricated on the silicon substrate and deflected to contact the detector electrodes by electrostatic attraction. Each detector electrode and associated metal tab is isolated from the switching and charging circuitry and row connectors by a metal-oxide-semiconductor-field-effect transistor fabricated adjacent to each tab on the silicon substrate. The isolation provided by the MOSFETs avoids cross-talk between the various detectors in the array and avoids the diminution of the signals from the elements by the capacitance associated with row and/or column connectors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention pertains to semiconductor infrared radiation detectors. More particularly, this invention pertains to metal-insulator-semiconductor (MIS) radiation detectors which detect infrared radiation by collecting charges generated within the semiconductor by the interaction of the radiation with the semiconductor. 
     2. Description of the Prior Art 
     Infrared radiation detection by means of metal-insulator-semiconductors and a technique for obtaining the outputs from the individual detectors in an array by a method referred to as the charge-injection device (&#34;CID&#34;) technique have been described in U.S. Pat. No. 4,079,422 and by Burke and Michon, &#34;Charge Injection Imaging: Operating Techniques and Performance Characteristics,&#34; IEEE Journal of Solid-State Circuits, pp. 121-128, vol. SC-11, No. 1, February 1976. A method for integrating the outputs of the detectors using the CID technique is described in U.S. Pat. No. 4,338,633. The integration of the outputs reduces the relative amount of noise associated with the output of each element in an array of radiation detectors while, at the same time, avoiding saturation of the individual detectors. 
     The readout of the outputs of an array of MIS detectors by means of the CID technique suffers from a number of problems which arise from the interactions or cross-talk between the elements in the array of detectors. The cross-talk is due to electrical connections between the elements of each row and between elements of each column in the array, which electrical connections are an integral part of the CID readout technique. In addition, capacitive coupling between the row and column conductors used in the CID technique causes additional cross-talk. The capacitance of the row and column connectors also significantly reduces the signal level of the outputs of the capacitor pairs that are used in the CID technique. 
     An additional practical problem occurs in the devices of the prior art. As described in U.S. Pat. No. 4,338,633, the rows and columns used for the readout of the array typically are connected by ordinary wire connections to the companion array of integrators. For an array having a significant number of elements, the difficulty in connecting the rows and columns of the array and the integrators by means of individual wires is significant. 
     SUMMARY OF THE INVENTION 
     The present invention uses a new and different method for obtaining the output from each semiconductor infrared radiation detector, which method does not depend upon the transfer of charge between pairs of capacitors connected respectively to row and column conductors. In the present invention, after the capacitor on the semiconductor substrate has been exposed to radiation, the amount of radiation incident upon each MIS capacitor is read directly by measuring the amount of charge that must be transferred to each individual capacitor in order to discharge the capacitor to the extent that its voltage is reduced to a predetermined level. The measure of charge obtained from the discharge of the MIS capacitor is accumulated in an integrating capacitor over a number of such discharges. The accumulated (integrated) measure of the output of each MIS capacitor then is read out to provide an output from the array of detectors. The electrical elements and circuitry described herein provide a means for reading out, and integrating the amount of radiation detected by each detector and for reinitializing each radiation detector in the array of radiation detectors also described herein. 
     The array of integrating capacitors and associated control circuitry is fabricated on a silicon substrate using MOS technology and is connected to the array of MIS radiation detectors on the semiconductor substrate by means of an array of metal tabs. The metal tabs are fabricated on the silicon substrate by deposition and etching techniques. Each metal tab is isolated from row and column interconnections on the silicon substrate by means of a metal-oxide-semiconductor-field-effect transistor (MOSFET) located adjacent to the tab and connecting the tab to the row connectors. The MOSFET isolates the tab and the associated MIS radiation detector from the capacitance of the row connector on the silicon substrate and isolates the detector from interactions with other detectors attached to the same row connector. 
     After the substrates have been cooled to the desired operating temperature, typically 77° K., the array of metal tabs are electrostatically deformed to make the electrical interconnections between the integrating capacitors on the silicon substrate and the MIS detectors on the semiconductor substrate. By making these connections after the substrates have cooled to the operating temperature, the invention avoids the problem of maintaining registration between dissimilar substrates over wide ranges of temperature. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts a typical MIS detector on a semiconductor substrate; 
     FIG. 2 depicts the relationship between ΔQ EN  and Q n  for specified values of Q BN  ; 
     FIG. 3 depicts a simplified circuit for the readout of a MIS detector; 
     FIGS. 4 through 7 depict the tabs that are used to interconnect the detectors and the integrating capacities; 
     FIG. 8 shows the readout and frame integrated circuitry for a 4×4 detector array; 
     FIG. 9 depicts a &#34;D&#34;, &#34;S&#34; and &#34;L&#34; module together with certain ancillary circuitry; 
     FIGS. 10 through 15 are reproductions of FIG. 9 which have been marked to show the &#34;on&#34; and &#34;off&#34; states of certain transistors and the paths of the current flow within the circuitry at various stages of operation of the system; 
     FIGS. 16 and 17 depict the timing and control signals and their relationship; 
     FIG. 18 shows the layout of a &#34;D&#34; module; 
     FIG. 19 depicts the layout of the detector array; and 
     FIG. 20 depicts the layout of an &#34;S&#34; module; 
     FIG. 21 is a floor plan of the entire chip. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 illustrates the structure of the basic MIS infrared radiation detector of the preferred embodiment. An array of metal squares, of which electrode 1 in FIG. 1 is representative, is fabricated by means of vacuum deposition on an insulating layer 2 at the surface of an n-type semiconductor substrate 3. Substrate 3 is connected to ground, that is to the zero reference potential for the system. When a negative voltage is impressed on electrode 1, the negative voltage creates a depletion layer 4 beneath electrode 1 in substrate 3. The negative voltage on electrode 1, repels mobile electrons within the substrate leaving a layer of bound positive charges within the depletion layer. 
     In operation as a detector, after creation of the depletion layer, electrode 1 is &#34;floated&#34; electrically and the substrate then is exposed to infrared radiation. The radiation passes through electrode 1, which is substantially transparent to the radiation, and into the substrate. The radiation interacts with the substrate and generates mobile pairs of holes and electrons within the depletion layer. Although the radiation also generates a few electron-hole pairs elsewhere, most of the radiation is absorbed within the depletion layer and most of the generation occurs within this layer. The holes are attracted by the negative potential of electrode 1 and migrate to the boundary surface 5 between insulator 2 and substrate 3. The accumulation of positive changes along the surface 5 of insulator 2 reduces the potential of electrode 1 relative to substrate 3 and, as a consequence, reduces the extent of depletion layer 4. Electrode 1 is separated from its neighbor by a guard ring 6 which is maintained at a positive potential relative to substrate 3. The positive potential creates accumulation regions of electrons beneath the guard rings which accumulation regions serve to isolate the detectors from one another. FIGS. 19A and 19B depict an array of detector electrodes 7, of which electrode 1 (in FIG. 1) is representative, that is deposited on an insulating layer (S i  O2 typically) on the top of the substrate. The guard ring 6, depicted in FIG. 1, is seen in FIG. 19 to constitute, in the aggregate, a mask that isolates each electrode in the array of electrodes from the adjacent electrodes. 
     The voltage on electrode 1 relative to substrate 3 is given by the equation ##EQU1## where Q E  --electrode charge per unit area (a negative number) 
     C o  --electrode insulator capacitance per unit area 
     N D  --donor impurity density in semiconductor 
     e--electron charge (a positive number) 
     ε--permittivity of semiconductor 
     X--depletion depth 
     Furthermore, 
     
         Q.sub.E +Q=-eN.sub.D X                                     (2) 
    
     where 
     Q=photon-generated positive charge per unit area beneath electrode at insulator-semiconductor interface 
     eN D  X=semiconductor space charge per unit area in depletion region 
     Substituting for X in equation (1), one obtains ##EQU2## 
     When the depletion region 4 is first established (by changing the electrode voltage from zero to some negative voltage), Q is equal to zero and V is given by the expression ##EQU3## As Q increases with time because of incident radiation, the quantity (Q E  +Q) decreases and V increases (i.e., V becomes less negative). Because electrode 1 is floating, the collection of the positive charges generated by the infrared radiation causes the absolute magnitude of the voltage, V, to decrease with continuing exposure to radiation. When Q E  +Q=0, the depletion region vanishes and the detector &#34;saturates&#34;. The corresponding voltage at saturation is given by the expression V=Q E  /C o . 
     The detector is read out by measuring the amount of charge, Q E  that must be placed on the detector electrode to discharge the detector partially to a preselected voltage. By appropriate selection of the initial electrode voltage and of the voltage to which the electrode is partially discharged, a nearly linear relationship can be obtained between the charge which is transferred to the electrode to reduce the voltage to the preselected level, and the amount of charge which is accumulated at the surface 5 of insulator 4 due to incident radiation. 
     The voltage change ΔV associated with a change ΔQ E  in electrode charge is given by the equation ##EQU4## To simplify notation, the following quantities are defined: ##EQU5## Subtracting equations (4) and (5) and expressing the result in terms of the quantities above, one obtains 
     
         ΔQ.sub.EN.sup.2 -2(P+1-Q.sub.N) ΔQ.sub.EN +(2PQ.sub.BN +Q.sub.N.sup.2 -2Q.sub.N)=0                               (10) 
    
     Solving for ΔQ EN  one obtains ##EQU6## For the preferred embodiment having a SiO 2  insulator and an InSb semiconductor, typical parameter values are: 
     
         E=1.5×10.sup.-12 F/cm 
    
     
         N.sub.D =2×10.sup.14 /cm.sup.3 
    
     
         C.sub.o =3×10.sup.-8 F/cm.sup.2 
    
     
         e=1.6×10.sup.-19 C 
    
     
         Q.sub.E =-1.8×10.sup.-8 C/cm.sup.2 
    
     Substituting these values in equation (4) and (8), one finds that 
     V=3.975 
     P=0.089 
     If one arranges for the quantity under the square root sign in equation (11) to be zero by selection of Q BN  then 
     
         ΔQ.sub.EN =P+1-Q.sub.N =1.089-QN                     (12) 
    
     Thus, ΔQ EN  (the normalized change in electrode charge associated with an electrode voltage change of ΔV) can be used as a measure of the normalized charge Q N  generated by photons. The normalized charge Q N  generated by photons can range from zero to one which would result in the normalized change in electrode charge Q N  ranging between 0.089 to 1.089. Thus, ΔQ EN  (which results from photon-generated charge Q and a change in electrode voltage ΔV) is a perfectly satisfactory measure of Q N . 
     One can calculate the required voltage change ΔV to achieve this result by setting the quantity under the square root sign in equation (11) equal to zero and by solving for Q BN . ##EQU7## Using the previously-calculated value for P, one finds that Q is given by 
     
         Q.sub.BN =6.66-Q.sub.N                                     (14) 
    
     To realize the linear relationship betwen ΔQ EN  and Q N  given by equation (12), Q BN  would range from 5.66 to 6.66. Because one has no prior knowledge of Q N  one must therefore select some constant value of Q BN  and to assure a real solution for Q N  in terms of Q EN , one must choose the lowest value in the range for Q BN , i.e. 5.66. 
     Plots of ΔQ EN  as a function of Q N  for the ideal case where Q BN  is given by equation (14) and the practical situation where Q BN  =5.66 are shown in FIG. 2. The latter case is very nearly linear so long as one does not approach detector saturation (Q N  =1) too closely. 
     One may then determine what the value of 5.66 for Q BN  corresponds to in terms of electrode voltage change ΔV. From equation (9) and the previously-given parameter values, ΔV=3.396 volts. Thus, if the electrode is discharged from -3.975 volts to -3.975+3.396=-0.579 volts, the quantity of charge transferred, ΔQ EN , will be related to the photon-generated charge Q N  by the lower curve in FIG. 2. 
     It is then apparent how to devise a circuit for determining the accumulated photon-generated charge Q collected under the detector electrode by measuring the amount of charge ΔQ E  that must be transferred to the cell electrode to reduce the voltage to 0.579 volts. 
     The essence of the circuit is shown in FIG. 3. At readout time the electrode of the MIS detector is connected through an N-type MOSFET 8 and a integrating capacitor 9 to a large positive voltage. Current immediately begins to flow from the positive supply to the detector and continues until the voltage on the detector electrode 1 reaches -0.579 volts, at which point the MOSFET&#39;s gate-to-source voltage equals the threshold voltage and MOSFET 8 cuts off. A charge equal to the charge ΔQ E  that has been transferred to the detector electrode also now resides on capacitor 9. Thus, the change in voltage across capacitor 9 which is due to the change in the charge on the capacitor is a measure of ΔQ E  and also of the photon-generated charge Q in the detector after being offset by 1.089 Q E  (see equation (12) and the definitions of ΔQ EN  and Q N ). 
     By repeating, a number of times, the process described above, one finds that the ΔQ E  s are summed on capacitor 9 so that the circuit also provides the means for accomplishing the integration process as part of the readout of the detector. 
     Unfortunately the semiconductor materials that are suitable for infrared radiation detectors are not suitable vehicles for integrated circuitry. Accordingly, in the preferred embodiment of this invention, two substrates made of different materials are used. For example, an indium antimonide (InSb) semiconductor uctor substrate having an insulating surface layer of silicon dioxide (SiO 2 ) could be used as the substrate and the insulating layer for the infrared radiation detectors. A silicon substrate is used for the fabrication of the integrating capacitors and for the fabrication of the field effect transistors on the silicon substrate (MOSFETS) that are used as switches in the integrating, control and readout circuitry. 
     In order to connect the integrating capacitors and readout circuitry located on the silicon substrate to the array of radiation detectors located on the indium antimonide substrate, the preferred embodiment utilizes an array of metal tabs that are fabricated on the silicon substrate. A technique for the fabrication of an array of thin metal tabs on a silicon substrate has been described by Kurt E. Petersen in &#34;Dynamic Micromechanics on Silicon: Techniques and Devices&#34;, IEEE Transactions on Electron Devices, Vol. ED-25, No. 10, October 1978, pp. 1241 et seq. One end of each tab is attached to the silicon substrate while the remainder of the tab is free to bend away from the substrate. The tabs are fabricated by deposition of metal on the substrate and then by undercutting the portions of the tabs which are to be movable by the etching processes described by Petersen. FIG. 4 depicts one tab 10 of the array of tabs that are used for connecting each of the MOSFETS on the the silicon substrate 12 to each detector electrode 1 on the indium antimonide substrate. The end 11 of tab 10 remains attached to the silicon substrate 12. When a positive voltage with respect to tab 10 is applied to guard ring 6, the moveable portion of each tab 10 is attracted electrostatically toward the guard ring, thus causing each tab to bend towards, and come into electrical contact with, the extended portion 13 of its associated electrode 1. FIG. 7B depicts a side view of one of the tabs 10. FIG. 5A is a top view of one of the tabs 10 showing the orientation of the tab relative to the underlying electrode 1. As depicted in FIGS. 5A and 5B, a window 14 is etched in silicon substrate 12 over each tab 10 and is oriented above detector electrode 1 so that infrared radiation may pass through the window to reach the electrode. Silicon substrate 12 actually has an array of such windows 14 arranged to coincide with the array of tabs and with the array of detector electrodes on the underlying indium antimonide substrate 3. FIG. 5 further depicts the contact 16 to active area of the silicon substrate upon which the MOSFET Transistor 8 is fabricated, which transistor (depending on its gate voltage), either connects tab 10 to, or isolates tab 10 from, connections on substrate 15 that run to the associated switching and integrating circuitry. FIG. 5B depicts the sequence of depositing the layers of material on the silicon substrate in connection with the fabrication of the active elements, the conductors and the tabs on the substrate. After fabrication of the tabs and the active areas on the silicon substrate, the windows 14 are etched through the substrate from the opposite side of the substrate. 
     FIG. 6 depicts the method by which the detector array on the silicon antimonide substrate 3 is attached to the silicon substrate. Substrate 3 is attached to mounting platform 17 by means of a central &#34;dot&#34; of cement 16. For the purpose of matching thermal expansion coefficients, mounting platform 17 also is made of silicon. Mounting platform 17, in turn, is attached at its edges by mounting blocks 18 to the silicon substrate 12 upon which the readout circuitry and tabs are fabricated. By attaching substrate 3 at its center to mounting platform 17, the detector array substrate 3 is free to expand and contract with temperature change. In order to have the tabs that are located on substrate 12, register properly with the detector electrodes on substrate 3, the entire structure is first cooled to the operating temperature (typically 77° K.) before a voltage is applied to the guard ring 6 on the detector substrate to cause the tabs to deflect from the silicon substrate and into contact with the electrodes. 
     An array of 256 by 256 detectors is used in the preferred embodiment. The dimensions of the tabs in the preferred embodiment are shown in FIGS. 7A and 7B and typical values for these dimensions are given in Table I. 
     
                       TABLE I______________________________________b = 3 × 10.sup.-6 mh = 0.2 × 10.sup.-6 mA = 126 × 10.sup.-12 m.sup.2d = 2 × 10.sup.-6 ml.sub.1 = 15 × 10.sup.-6 ml.sub.2 = 22 × 10.sup.-6 ml.sub.3 = 25 × 10.sup.-6 mε.sub.0 = 8.854 × 10.sup.-12 F/m (permittivity of freespace)E = 7 × 10.sup.10 N/m.sup.2 (Young&#39;s modulus for Al)______________________________________ 
    
     For the values given in Table I, a voltage of approximately 13 volts on the guard rings relative to tab voltage is just sufficient to cause deflection of the tabs. Accordingly, a voltage of approximately 25 volts gives a sufficient margin of safety to operate the tabs. 
     The readout and frame integrator circuitry, based on the simple circuit illustrated in FIG. 3, is illustrated in FIG. 8 for a 4×4 detector array. In the preferred embodiment, the configuration illustrated in FIG. 8 is expanded to an array of 256×256 elements. The central area of FIG. 8 depicts an array of &#34;D&#34; type modules numbered by the row and column in which they are located. The capacitor 19 in module D11 denotes an MIS detector cell. Adjacent capacitor 20 terminated with a &#34;square&#34; denotes the capacitance between the guard ring 6 depicted in FIG. 1 and FIG. 19A and the tabs 10, which capacitance provides the electrostatic means for deflecting the tabs from silicon substrate 12 to come into contact with the detector electrodes 1 on substrate 3. 
     Associated with each &#34;D&#34; module on a one-to-one basis is an &#34;S&#34; module--also numbered by the row and column in which it is located. The five-MOSFET, one capacitor &#34;S&#34; module performs the functions described with respect to the single capacitor and MOSFET shown in the simplified illustration in FIG. 3. 
     Associated with each row of &#34;D&#34; and &#34;S&#34; modules are identical &#34;L&#34; and &#34;R&#34; modules. The &#34;D&#34; and &#34;S&#34; modules for the left half of the array are connected to the &#34;L&#34; module and those for the right half of the array are connected to the &#34;R&#34; module. The &#34;L&#34; and &#34;R&#34; modules provide the means for reading out the integrating capacitors in the &#34;S&#34; modules to the outside world. 
     An understanding of the overall operation of the readout and frame integration circuitry is best accomplished by first examining the operations that occur in associated &#34;D&#34;, &#34;S&#34;, and &#34;L&#34; (or &#34;R&#34;) modules. 
     The &#34;D&#34;, &#34;S&#34; and &#34;L&#34; modules located in the first row and first column are shown in FIG. 9 together with certain ancillary circuitry included in FIG. 9 to facilitate the description of the circuit operation. The dashed capacitors CS, CR, and CG represent stray capacitance associated with the buses connecting the rows and columns of elements. The detector readout, the integration function that occurs as a result of many detector readouts, and the readout of the integrated charge transfers are accomplished in six steps which take place during a time interval of 1.6 μs. 
     Step 1--Biasing of Stray Capacitance Prior to Detector Readout (FIG. 10)--0 to 0.2 μs 
     Non-conducting MOSFETS are marked with &#34;X&#39;s&#34;. All other MOSFETS are conducting and the paths of current flow are indicated by the heavy lines and arrows. 
     The stray capacitance CS and CR associated with the left bus which interconnects left-side &#34;D&#34; and &#34;S&#34; modules with the &#34;L&#34; module is charged to voltage VB which typically is -0.6 volts. 
     Step 2--Detector Readout (FIG. 11)--0.2 to 0.8 μs 
     The charge required to discharge the detector is accumulated of the integrating capacity in the &#34;S11&#34; module. MOSFET No. 3 should have as high a width-to-length (W/L) ratio as possible in order to minimize the discharge time of the detector. A ratio of 12 is used in the preferred embodiment, MOSFET No. 4 (W/L=1) serves to inflate the large source-to-substrate capacitance of MOSFET No. 3 from the bus that interconnects the &#34;S&#34; and &#34;D&#34; modules. MOSFET No. 4 is fully turned on and therefore does not significantly affect the discharge time of the detector. 
     It should be noted that the readout of the detector array proceeds column by column and that all detectors in a column are read out simultaneously. 
     Step 3--Biasing of Stray Capacitance Prior to Integrating Capacitor Readout (FIG. 12)--0.8 to 1.0 μs 
     Step 3 marks the beginning of the integrating-capacitor readout process. The stray capacitance associated with the left bus is charged to VB. The stray capacitance associated with the output bus is charged to VN. 
     Step 4--Integrating Capacitor Readout; Detector Charge Dump (FIG. 13)--1.0 to 1.2 μs 
     The integrating capacitor in module &#34;S11&#34; is charged to the voltage to which the left bus was charged in Step 3. The appropriate charge voltage is obtained by adjusting the turn-on-voltage of MOSFET 2 in the &#34;L&#34; module. In order to achieve the lowest practical charge time, MOSFET 2 has a very large W/L value of 70. MOSFETS 1 and 3 with W/L values of approximately one are placed on either side of MOSFET 2 in order to isolate the large source and drain capacitances of MOSFET 2 from the left bus and from the output bus. The fully turned-on MOSFETS 1 and 3 do not significantly affect the charge time. 
     The amount of charge required to charge the integrating capacitor is accumulated on the storage capacitor CB. The size of capacitor CB is adjusted relative to the integrating capacitor so that the charging of a fully-discharged integrating capacitor does not result in a voltage on CB greater than the charge voltage on the integrating capacitor. For the voltages given in FIG. 13 and for the preferred embodiment, the sum of CB and CG is made twice as large as the integrating capacitor. If this condition is not met, the integrating capacitor would not completely charge under some circumstances. 
     A second operation, which is independent of the integrating-capacitor readout, but which proceeds in parallel with the readout operation, begins at Step 4 and prepares the just-discharged detectors to collect radiation-created charge again. The step shown in FIG. 13 raises the voltage on the detector to the &#34;flatband&#34; voltage near zero and thereby causes electrons to flood the substrate and recombine with the photon-generated holes; i.e., the holes collected in the detector storage region are &#34;dumped&#34;. 
     Step 5--Integrated Capacitor Readout; Detector Charging (FIG. 14)--1.2 to 1.4 μs 
     The readout operation involving the integrating capacitor and CB that began in Step 4 continues. The detector is readied for operation by charging it to a negative voltage VC. 
     Step 6--Integrating Capacitor Discharged (FIG. 15)--1.4 to 1.6 μs 
     The readout operation involving the integrating capacitor that takes place during Steps 4 and 5 leaves the integrating capacitor charged. In order to prepare the integrating capacitor for the next integration cycle, it is discharged by applying the voltage VI to the upper plate. 
     It should be noted that the operations involved in reading out an integrating capacitor to CB is accomplished for only one capacitor at a time. 
     Sampling the output voltage of the source follower at the end of Step 5 provides a measure of the charge that was read out from the integrating capacitor. 
     FIG. 16 illustrates how the operations outlined in FIGS. 10-15 translate to the operation of an array. 
     For simplicity, the detector readout (R) is represented as taking place during the first half of a time period and integrating capacitor charge transfer (T) as taking place during the second half although actually in some overlap in these operations. FIG. 16, depicts how the timing of readout and charge transfer is affected by the number of frames integrated. Note how a column of detectors are all read out at one time, while charge transfer involves only one integrating capacitor at a time. The patterns shown in FIG. 16 for a 4×4 array provide the insight necessary to derive the timing pattern for larger arrays. 
     The control signals for a 4×4 array (see FIG. 8) which implement the operations outlined in FIGS. 10-15 are shown in FIG. 17. The number of frames integrated is four in the example shown. In FIG. 17, when the control signal is &#34;high&#34;, the MOSFET is turned on and when the control signal is &#34;low&#34;, the MOSFET is turned off. Where the voltage level in FIG. 17 is shown as a dotted line, the turn-on voltage has been adjusted so as to achieve automatic turn-off when the source reaches a particular voltage level. 
     Circuit Layout (FIG. 18) 
     The circuit layout for the &#34;D&#34; module is shown in FIG. 18 for 3-um minimum feature dimensions. The scale of the circuit is indicated by the dimensions shown on the Figure. The outlines of the detector cells and guard rings are shown to provide orientation. A portion of the detector array is shown in FIG. 19. The heavy croshatched areas represent insulator over semiconductor. All other areas represent metal over insulator over semiconductor. The area of the detector cell is 643.5 μm 2 . The area within the window that is not shadowed by the switch is 437 sq. μm. The dimensions of the &#34;D&#34; module are 42 μm×42 μm. 
     The layout of the &#34;S&#34; module is shown in FIG. 20. The size of the module is 46 μm×112 μm. The area of the integrating capacitor is 2100 μm 2  (approximately 1 pF of capacitance). 
     For the configuration of the &#34;D&#34; and &#34;S&#34; modules are shown in FIG. 21, a chip has the dimensions of 22000 μm×25000 μm. This total area is allocated as follows: 
     
         ______________________________________65,536 lpF capacitors @ 2100 μm.sup.2 /cap. =                   137 × 10.sup.6 μm.sup.265,536 windows @ 1019 μm.sup.2 /detector =                    67 × 10.sup.6 μm.sup.2400,000 MOSFETS and interconnections =                   346 × 10.sup.6 μm.sub.2TOTAL                   550 × 10.sub.6 μm.sub.2______________________________________