Abstract:
An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to electrically erasable and programmable read-only memory (EEPROM) devices and more particularly to an improved EEPROM cell and its method of use having smaller layout size, lower program/erase voltage requirements and higher read, erase and programming speeds and better endurance than conventional EEPROMS. 
     The semiconductor community faces increasingly difficult challenges as it moves into production of semiconductor devices at feature sizes approaching 0.1 micron. Cell designs for typical semiconductor devices must be made more durable, smaller (i.e., scalable), cost effective to manufacture, faster in reading and capable of operating at lower voltages and power to enable manufacturers to compete in the semiconductor industry. 
     One of the more recent generation of memories facing those challenges, EEPROMS allow their program contents to be electrically programmed bit-by-bit and electrically erased. Conventional erasable programmable read-only memories (EPROMS), by way of contrast, are generally erased in bulk and by the frequently inconvenient technique of exposure to ultraviolet light. EEPROM cells have been recently extensively used in programmable logic devices (PLD&#39;s). 
     Most conventional EEPROM cells are formed of three transistors: a write transistor, a read transistor and a sense transistor. The EEPROM cell is programmed and erased by removing electrons from, or adding electrons to, a floating gate of one of the transistors. In conventional EEPROM cells the read transistor and the sense transistor are connected to the same data (bitline). As a result, when the read transistor is turned on, the sense transistor is effectively used as the storage cell of the EEPROM. 
     FIG. 1 shows an array of four identical conventional EEPROM memory cell structures designated A, B, C and D which form a portion of a larger array composed of identical memory cell structures. The voltage lines to the other cells in the larger array not depicted in the figure have the symbol “!” as a prefix, just as is the case for cells B, C and D, unless those lines to the other cells are the same lines as are attached to cell A. The EEPROM memory cell A consists of a write transistor  12   a , a read transistor  14 , a sense transistor  16 , a control gate capacitor C and a tunnel diode TD. Each of the three transistors has drain and source regions marked D and S, respectively. The operation of the conventional EEPROM memory cell A is summarized in Table 1 below. 
     
       
         
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                   
                 SUB- 
               
               
                   
                 WBL 
                 ACG 
                 WL 
                 PT 
                 PTG 
                 WLR 
                 STRATE 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Program 
                 V pp   
                 0 
                 V pp  + V t   
                 HiZ 
                 0 
                 V cc   
                 0 
               
               
                 Erase 
                 0 
                 V pp  + V t   
                 V cc   
                 HiZ 
                 V pp   
                 V cc   
                 0 
               
               
                 !Program 
                 V pp   
                 0 
                 0 
                 HiZ 
                 0 
                 0 
                 0 
               
               
                 (row) 
               
               
                 !Program 
                 0 
                 [?0][V pp  + V t ?] 
                 0 
                 HiZ 
                 0 
                 0 
                 0 
               
               
                 (col) 
               
               
                 Read 
                 0 
                 0 
                 V cc   
                 V pt   
                 0 
                 V cc   
                 0 
               
               
                   
               
             
          
         
       
     
     When programming the memory cell A, an intermediate pumped programming voltage V pp  (typically about 11-12 V) is applied to the bitline WBL of the write transistor  12   a  and a relatively high voltage V pp +V t  (typically between 13-15 V) is applied to its wordline WL in order to pass V pp  through the tunnel diode TD to the sense transistor  16 . Under this bias condition, a voltage drop is present between V d  and the floating gate FG. Due to the drop, electrons tunnel from the floating gate to V d , thereby reducing or eliminating the negative charge on the floating gate of the sense transistor  16  and thus turning on the sense transistor. 
     When erasing the memory cell A, the relatively high voltage V pp +V t  is applied to the capacitor C from array control gate line ACG. Under this bias condition, a voltage drop is present between the floating gate FG and V d . As a result, electrons tunnel from V d  to floating gate FG, thereby negatively charging FG and turning off the sense transistor  16 . 
     When reading the contents of the memory cell A, zero volts is applied to the bitline of the write transistor  12   a . A voltage, V cc  of about 1.8 V, is applied to the wordline WL and a voltage V pt  of about 0.6-1.4 V is applied to the drain of the read transistor  14 . 
     For each operation (read, program, erase), the substrate of the cell (not shown) is held at ground potential. The high voltage V pp  +V t  can be generated through an additional circuit (not shown). However, the higher the voltage V pp +V t  needed, the more complex the semiconductor process and circuitry required. 
     While programming the memory cell A, voltages are applied to the write transistors  12   b ,  12   c  of memory cells B and C. In some cases the same voltages as are applied in cell A are applied to nodes in cells B and C corresponding to nodes in cell A because the voltage lines are shared. In other cases different voltages are applied. For example, bit line WBL applies a voltage V pp  to the drain of cell B&#39;s write transistor  12   b  while word line !WL applies a zero voltage to the gate of that write transistor. As a result, the write transistor of memory cell B experiences a voltage of V pp  over the oxide of that transistor. The large size of V pp , about 11 V, requires that that oxide be thick, about 150 Å, to prevent gate leakage by tunneling across the oxide which could damage the oxide. Similarly, in memory cell C, word line WL applies a high voltage of V pp +V t  to the gate of that cell&#39;s write transistor  12   c  while bit line !WBL applies a voltage of zero to the drain of that write transistor, producing a voltage of V pp +V t  across the oxide of that write transistor. As was true of the write transistor  12   b  in cell B, the large size of V pp +V t , about 12-14 V, also requires that the oxide of the write transistor  12   c  in cell C be thick. A thick oxide, as is well known in the art, renders difficult the scaling down of the transistor of which it is a component, in this case the write transistor. 
     The non-scalability of the write transistors prevents the scaling down of the entire EEPROM memory cell. The inability to scale down the memory cell size is undesirable because the trend in the electronics industry is to have smaller and smaller memory cells to enable an array of the same physical size to store larger and larger amounts of data. 
     Another drawback associated with the conventional EEPROM structure is that the thick oxide slows down the speed with which the EEPROM cell can be programmed, erased and read. This problem conflicts with the industry trend of manufacturing faster PLDs. 
     Thus, there is a need to provide an EEPROM memory cell structure and operating method which provide scalability and faster operating speeds while at the same time using smaller program/erase voltages, thereby increasing the endurance of the EEPROM memory cell. 
     BRIEF SUMMARY OF THE INVENTION 
     By way of introduction only, an improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. 
     An advantage of the present invention is the ability to scale down the size of the EEPROM memory cell. 
     Another advantage of the present invention is that it requires smaller voltages to program and erase the memory cell. 
     A feature of the present invention is that because of the smaller gate oxide thicknesses, the overall transistor size can be reduced, thus allowing for faster program, erase and reading speeds. 
     Another advantage of the present invention is that the gate leakage and damage to the oxide, usually resulting from smaller gate oxide thickness, is avoided. 
     Another advantage of the present invention is that the source of the write transistor is at a higher voltage, allowing faster programming time. 
     These and other advantages and features of the present invention will become apparent from the description of the embodiments below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a portion of an array of conventional EEPROM memory cells. 
     FIG. 2 is a schematic diagram showing a portion of an array of the EEPROM memory cells according to the present invention. 
     FIG. 3 is a composite of cross sectional views of an EEPROM memory cell structure according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     FIG. 2 illustrates a schematic diagram of an array of four identical enhanced EEPROM memory cell structures according to the present invention and designated A, B, C and D which form a portion of a larger array composed of identical memory cell structures. The voltage lines to the other cells in the larger array not depicted in the figure have the symbol “!” as a prefix, just as is the case for cells B, C and D, unless those lines to the other cells are the same lines as are attached to cell A. As shown in FIG. 2, the EEPROM memory cell A of the present invention incorporates a depletion type write transistor  22   a , an enhancement mode read transistor  32 , a partial depletion type sense transistor  42   a  with a threshold voltage of about zero, a control gate capacitor C and a tunnel diode TD. The gate capacitor couples the ACG voltage to the sense transistor  42   a , thereby affecting the voltage on the floating gate, FG. The cell of the present invention has different programming and erase voltage values than that of the conventional EEPROM memory cell depicted in FIG.  1 . 
     FIG. 3 shows a cross sectional side view of one of the four identical EEPROM structures depicted in FIG.  2 . (As more fully described below, FIG. 3 actually shows a composite of two cross-sectional side views.) In FIG. 3, a P-type semiconductor substrate  50  has 5 N+ type regions formed on and below its surface by standard diffusion techniques. These 5 N+ type regions correspond to the source and drain regions of the three transistors which make up the EEPROM memory cell depicted in FIG.  2 . 
     A depletion type write transistor  22  comprises a drain  24 , a source  26 , a channel region  23  between the drain  24  and the source  26 , a gate oxide  71  forming a portion of oxide layer  27  having a thickness of about 90 Å and a gate  28  formed on top of gate oxide  71 . Bitline WBL is connected to the drain  24 , while a first wordline WL is connected to the gate  28  of the transistor. 
     Tunnel diode  52  has as a first terminal a program junction N+ region  53  and as a second terminal  81  a portion of a polysilicon layer  48 . The program junction region is an extension of source  26  of the write transistor but descends deeper into the substrate  50  to an extent variable with different embodiments as is appreciated by those skilled in the art. A portion of the oxide layer  27  over the program junction  53  serves as a tunnel diode oxide layer  55 . 
     Enhancement mode read transistor  32  comprises a drain  36 , a source  34 , and a channel region  33  between the drain  36  and source  34 . A gate oxide  72  forming a portion of the oxide layer  27  extends over the channel region  33 . Formed on top of the gate oxide  72  is a gate  38 . The gate is coupled to a second wordline WLR while the drain of the read transistor  36  is coupled to a product term line PT. 
     The partial depletion type sense transistor  42  comprises a source  44 , a drain  34  (which is also the source  34  of the read sense transistor  32 ), and a channel region  43  between the drain  34  and a source  44 . A gate oxide  73 , forming a portion of the oxide layer  27 , extends over channel region  33 , source  44  and drain  34  and serves in one of the alternative embodiments of the present invention described below as a tunnel region  46 . The polysilicon layer  48  extends into the sense transistor  42  and overlies the source  44 . The floating gate  82  is a region of the polysilicon layer  48  and overlies channel region  43  so that when sufficient voltage is present on the floating gate  82 , the channel  43  will conduct current between the source  34  and the drain  44  of the depletion type sense transistor  42 . 
     Field oxide layer  49 , a shallow trench isolation, insulates the floating gate  82  from the underlying substrate  50  and separates the sense transistor  42  and the write transistor  22 . The thickness of the field oxide layer  49  is approximately 4000 Å. 
     In one alternative embodiment of the present invention, the oxide layer has a thickness greater than the order of 90 Å, while in another alternative embodiment of the present invention, the oxide layer has a thickness less than the order of 90 Å. 
     As mentioned above, FIG. 3 for clarity actually shows a composite of two cross-sectional views. One of ordinary skill in the art will appreciate that the three transistors and the tunnel diode depicted in FIG.  3 . may not lie in a single plane. One of that skill will appreciate that according to the embodiments of the present invention described herein, the write transistor  22 , the tunnel diode  52 , a portion of the polysilicon layer  48 , and a portion of the field oxide layer  49  lie in a first plane and that a more accurate depiction would show that plane in a single cross-section. By contrast, one of ordinary skill in the art will also appreciate that the sense transistor  42 , the read transistor  32 , a portion of the polysilicon layer  48 , and a portion of the field oxide layer  49  lie in another plane generally disposed parallel to and above the first plane and that a more accurate depiction would show that other plane in a second cross-section. The portions of the polysilicon layer  48  and of the field oxide layer  49  in both planes are connected by a polysilicon layer and a field oxide layer not depicted. 
     Operation of the array of four identical EEPROM memory cells of the present invention will now be described with reference to Table 2 below and FIGS. 2 and 3. 
     
       
         
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                   
                 SUB- 
               
               
                   
                 WBL 
                 ACG 
                 WL 
                 PT 
                 PTG 
                 WLR 
                 STRATE 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Program 
                 V pp   
                 0 
                 V pp   
                 HiZ 
                 0 
                 V cc   
                 0 
               
               
                 Erase 
                 0 
                 V pp  or V pp  + V t   
                 V cc   
                 HiZ 
                 V pp  or 
                 V cc   
                 0 
               
               
                   
                   
                   
                   
                   
                 V pp  + V t   
               
               
                 !Program 
                 V pp   
                 0 
                 V pp  − V max   
                 HiZ 
                 0 
                 V cc   
                 0 
               
               
                 (row) 
               
               
                 !Program 
                 V pp  − V max   
                 V pp  − V max   
                 V pp   
                 HiZ 
                 HiZ 
                 V cc   
                 0 
               
               
                 (col) 
               
               
                 Read 
                 0 
                 0 
                 V cc   
                 V pt   
                 0 
                 V cc   
                 0 
               
               
                   
               
             
          
         
       
     
     The three operations of the EEPROM memory cell are read, program, and erase. The various voltages applied to the circuit depicted in FIG. 2 are presented in Table 2. 
     When programming the memory cell A of the present invention, V pp  (about 11-12 V) is supplied on both the bitline WBL of the write transistor  22   a  and the wordline WL coupled to write transistor  22   a . The lower voltage level can be used on the WL because the write transistor  22   a  is a depletion type transistor. The product term voltage PT provided on the bitline of the read transistor  32  is left floating, i.e., is at HiZ. The wordline WLR supplied to the gate of the read transistor  32  is V cc , about 1.8 V. The PTG line to the source of the sense transistor  42   a , and the substrate  50  are all tied to ground. 
     While programming the memory cell A, voltages are applied to the write transistors of memory cells B and C. In some cases the same voltages as are applied in cell A are applied to nodes in cells B and C corresponding to nodes in cell A because the voltage lines are shared. In other cases different voltages are applied. For example, bit line WBL applies a voltage V pp  to the drain of cell B&#39;s write transistor  22   b  while word line !WL applies a voltage V pp −V max  to the gate of that write transistor where V max  is the maximum voltage allowable over the 90 Å thick oxide of that transistor without causing large leakage or oxide damage. In the present embodiment V max  is numerically about 10 V. As a result, the write transistor of memory cell B experiences a voltage of V max  over the 90 Å thick gate oxide of that transistor. At this voltage level no gate leakage by tunneling across the oxide will occur, thus avoiding the risk of damage in the prior art noted above. Further, because the voltage at the drain of the transistor  22   b  is Vpp while the voltage on the gate of transistor  22   b  is V pp −V max , the voltage at the second terminal of the tunnel diode TD in memory cell B is limited to about V pp −V max , i.e., about 2 V. However, the second terminal of the tunnel diode is coupled directly to the floating gate of sense transistor  42   b . This small a voltage on that floating gate, when compared to the zero voltage applied to the source of that sense transistor by line PTG, is insufficient to place charge on that floating gate. As a result, no disturb problem arises. 
     Similarly, in memory cell C, word line WL applies a high voltage of V pp  to the gate of that cell&#39;s write transistor  22   c  while bit line !WBL applies a voltage of V pp −V max  to the drain of that write transistor, producing a voltage of V max  across the gate oxide of that write transistor. At that voltage there will be minimal leakage by tunneling across the oxide, thus similarly avoiding the risk of damage in the prior art noted above. Further, the voltage at the floating gate of the sense transistor in cell C is limited to V pp −V max  or about 2 V because line !ACG supplies V pp −V max  to the capacitor and V pp −V max  is applied to the drain of the write transistor in that cell. This small a voltage applied to the floating gate of that sense transistor is insufficient to place charge on that gate. As a result, no disturb problem arises. 
     Another feature of the present embodiment is the more efficient passthrough of the write transistor&#39;s ( 22   a ) drain voltage to that transistor&#39;s source during programming. Because the write transistor is a depletion type, its threshold voltage V th =−|V th |. Because during programming the write transistor is on, its gate source voltage V gs  must equal or exceed V th . As a result, V s ≦V g +|V th | or V s ≦V pp +|V th |. 
     Erasing the EEPROM memory cell A of the present invention is provided by supplying a zero voltage to the bitline WBL of that cell&#39;s write transistor  22   a ; supplying a voltage V cc  to the wordline WL of the write transistor and to the wordline WLR of that cell&#39;s enhancement mode read transistor  32 ; and providing V pp , or alternatively V pp +V t , to ACG, where V t  is about 0.5-2 V. The product term PT coupled to the drain of the read transistor, floats at HiZ while PTG is supplied with V pp  or V pp +V t . The substrate  50  is held at ground potential. 
     When reading information stored in the EEPROM memory cell A of the present invention, zero volts is applied to the bitline WBL of that cell&#39;s write transistor  22   a . V cc  is applied to the wordline WLR of that cell&#39;s read transistor  32  and voltage V pt  of about 0.5-2 V is applied to the drain of the read transistor  32  over line PT. The substrate  50  and line PTG to the source of that cell&#39;s sense transistor are held at ground potential. A zero voltage is supplied to line ACG. Under this bias condition, current flows between the drain of the read transistor and the source of the sense transistor  42   a  if the depletion type sense transistor is on, indicating a logic 1. If the depletion type sense transistor is off, current does not flow, indicating a logic 0. 
     In one alternative embodiment of the present invention, the sense transistors  42   a, b, c  and  d  of all the memory cells may be enhancement mode transistors. With an enhancement mode transistor acting as the sense transistor of memory cell A, V cc  would be applied to ACG during the read operation In an alternative embodiment of the present invention, erasing of memory cell A can be performed in a different fashion. This operation of memory cell A will now be described with reference to Table 3. This technique of erasing is provided by supplying the voltage V pp  to the bitline WBL and to the wordline WL of that cell&#39;s write transistor  22   a ; supplying the voltage V cc  to the wordline WLR of that cell&#39;s read transistor  32 ; and providing V pp  to ACG. The product term PT coupled to the drain of the read transistor, PTG and the substrate  50  are held at ground potential Under this bias condition, electrons tunnel through the gate oxide of that cell&#39;s depletion type sense transistor  42   a  from that transistor&#39;s channel region  43  to that transistor&#39;s floating gate. 
     
       
         
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                   
                 SUB- 
               
               
                   
                 WBL 
                 ACG 
                 WL 
                 PT 
                 PTG 
                 WLR 
                 STRATE 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Program 
                 V pp   
                 0 
                 V pp   
                 HiZ 
                 0 
                 V cc   
                 0 
               
               
                 Erase 
                 V pp   
                 V pp   
                 V pp   
                 0 
                 0 
                 V cc   
                 0 
               
               
                 !Program 
                 V pp   
                 0 
                 V pp  − V max   
                 HiZ 
                 0 
                 V cc   
                 0 
               
               
                 (row) 
               
               
                 !Program 
                 V pp  − V max   
                 V pp  − V max   
                 V pp   
                 HiZ 
                 HiZ 
                 V cc   
                 0 
               
               
                 (col) 
               
               
                 Read 
                 0 
                 0 
                 V cc   
                 V pt   
                 0 
                 V cc   
                 0 
               
               
                   
               
             
          
         
       
     
     The embodiments and operation described are manufactured and operated using well known techniques, and their method of manufacture and operation would be obvious to those skilled in the art. The foregoing description of the embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, modification and variation of the invention are possible in light of the above teaching. It is therefore intended in the appended claims to cover all such variations and modifications which fall within the true spirit and scope of the invention.