Abstract:
A series-parallel scan, IR, focal plane array which uses small InSb CID  mles. The CID is used to premultiplex photocurrent through a preamplifier before the photosignal is introduced into a Si CCD TDI signal processor.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to infrared (IR) charge-injection devices and especially to two-dimensional, infrared, charge-injection-device arrays used in a series-parallel scan mode. 
     The development of charge-coupled device (CCD) and charge-injection device (CID) area-imaging arrays for λ &lt;1 μ m has encouraged the infrared community to examine the application of these technologies to infrared focal planes. For terrestial applications the interest is primarily in the development of new kinds of thermal imagers for the 3-5 μm and 8-12 μm atmospheric windows. It is expected that the use of the CCD&#39;s at or near focal plane will permit the use of thousands of IR detectors in a focal plane at reasonable cost with good signal-to-noise ratios. 
     CCD and CID structures can be fabricated in materials sensitive to infrared radiation; however CCD and CID structures which are appropriate for the visible and very near infrared are not necessarily appropriate for thermal imaging systems. Because of the low contrast thermal imagery, a DC-coupled starting sensor would have difficulty distinguishing between variations in detector responsivity and variations in image irradiance. For example, net detector-to-detector responsivity uniformity in an unscanned array would need to be better than 0.35% in the 3.4-5.1 μm band in order not to compete with apparent target-temperature differences of 0.1° C. 
     The use of two-dimensional arrays in a mechanically scanned series-parallel configuration using time delay and integration (TDI) and an effective AC coupling of the detector with the image avoids these stringent uniformity requirements. Also TDI provides built-in redundancy in that a few dead detectors can be tolerated without significantly degrading the imagery. 
     The technical approach to a high-packing-density array for series-parallel scan, which do date has received the most investigation, mates conventional InSb photodiodes with a SI CCD chip to form a InSb photodiode-Si CCD sandwich focal-plane module. Such a module is shown and described in U.S. Pat. No. 3,883,437, issued May 13, 1975. Several modules would be used to form a focal plane of thousands of detectors. With this approach each detector is individually connected to a direct-injection input circuit which inputs photocurrent into a silicon TDI CCD register. This method of inputting photocurrent into a Si CCD requires a connection for each detector and has certain signal-to-noise limitations. Preamplifiers between the detector and the CCD have not been used to data due to packing density considerations. 
     SUMMARY OF THE INVENTION 
     An alternative to the sandwich/direct-injection focal-plane-array structure discussed above is the series-parallel scan, 2-dimensional CID array shown in FIG. 1 which is based on the CID in InSb developed by Kim. (For details, see J. C. Kim, &#34;InSb MIS Structures for Infrared Imaging Device,&#34; Techncal Digest, 1973, IEDM, Washington, D.C., p. 419, which is incorported herein be reference). The CID in effect premultiplexes the photocurrent through a preamplifier before it is inserted into a Si CCD TDI register. High transfer efficiency in the CID array is not required since an x-y readout can be implemented. Connections must be made to the x-y readout lines on the CID module but, for the 384 detector module size suggested in FIG. 1, this is only 0.1 interconnect per detector. The CID modules must be read out more than once per dwell time, leading to high clock frequencies, but the premultiplexing feature allows the use of a small number of high-quality preamplifiers before introduction of the signal current into the CCD TDI signal processor. This can lead to improved signal-to-noise performance over direct injection. &#34;Background rejection&#34; equivalent to A.C. coupling is provided at the TDI output as with the sandwich/direct-injection structure. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an embodiment of a series-parallel scan, two-dimensional, focal-plane array and associated circuits and devices in accordance with the present invention. 
     FIG. 2 is a partial block diagram of a CID module and a signal processor which is useful for an understanding of the operation of the invention. 
     FIG. 3 is a block diagram illustrating the signal flow through one branch of the present device. 
     FIG. 4 is a block diagram in schematic form showing some components of a somewhat different version of the embodiment of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows an embodiment of the invention which is useful in an infrared (IR) imager or search set. A plurality of IR-sensitive CID modules 10 which may have detector elements 12 fabricated from InSb, for example, are arranged horizontally substantially in a row, in the focal plane of an IR image which is formed by optical means (not shown) such as lenses or mirrors. The optical means provided with means 11 to move the image down relative to the modules so that the scan direction is up, as shown. Alternately, of course, the module array could be moved in the upward direction. 
     CID module has one or more associated horizontal and vertical scan shift registers, or readout means, 14, which may be fabricated from silicon, and wiring to provide an x-y scan and readout of the charge in the detector elements. One way of doing this is to read out each element successively in the bottom row from left to right, then shift to the next higher row and readout each element from left to right, and so on, until the topmost row is read out. An entire module is read out in the time the image moves a distance y/2 on the focal plane, where y is the detector element center-to-center spacing. Integration occurs in each element since photocurrent from its associated IR-sensitive element (not shown) keeps adding to the charge in the element during the time between each readout of the element. 
     The serial-pulse multiplexed output from a module 10 is fed to a preamplifier 16. (There may actually be more than one preamplifier in serial connection). The amplified signal is passed to a signal processor 18 which performs demultiplexing, time delay and integration (TDI), background rejection and A.C. coupling functions. The processor 18 is a CCD, which may be fabricated in silicon, for example. It contains a plurality of gates 20, register packages 22, high-pass filters 24 and an output multiplexer 26. Each gate 20 is switched open at the proper time to pass the incoming signal from its associated preamplifier 16 to a register package 22. The output from the register package 22 goes through a high-pass filter 24 which provides background rejection and A.C. coupling and the outputs of all high-pass filters in the module 18 are then multiplexed once more by an output multiplexer 26. The multiplexed outputs of all the module multiplexers 26 are then fed to a final multiplexer 19 which forms them into a serial-pulse multiplexed output. This chain of output pulses is fed to a sample and hold means 21 and to video means 23 for display. 
     The register packages 22 in each signal processor module 18 consists of a sandwich of a first CCD shift register 28 to which the incoming signal from a preamplifier is fed, a set of parallel transfer gates 30 and a tapered TDI register 32. The registers 28 and 32 and the output multiplexer 26 are CCD devices. 
     The scan and shifting operations of the CID and CCD modules 10 and 18 and the structure of the registers 28, 32 are better understood from FIG. 2. Only 5 elements are shown, rather than 16, for the sake of clarity. 
     When detector 5A is read out, gate A° is opened and the amplified signal charge is fed into CCD well 1A&#39;. When detector 5B is read out, gate B° is opened and amplified charge is fed into CCd well 1B&#39;. Before detector 4A is read out, the charge in 1A&#39; is transferred to 2A&#39; to make room for the charge 4A. This process continues until the entire CID module is read out and an amplified replica of the signal from detector 1A, 2A, 1B, 2B, etc., is stored in CCD wells 1A&#39;, 2A&#39;, 1B&#39;, 2B&#39;. At that point, the transfer gates are opened and the charge in 1A&#39; is transferred to 1a at the same time that charge 2A&#39; is transferred to 3a, etc. After this parallel transfer, charge in 1a is moved to 2a the charge in 3a to 4a, the charge in 1b to 2b, etc., and the readout process is repeated. With the design shown in FIG. 2, integration occurs after the third readout when the charge in 2A&#39; is added to the charge from 2a which originated two readout sequences ago from detector 1A and is now in register element 3a. A smaller ratio of sampling time to dwell time can be obtained by interleaving more CCD bits. The register 1a, 2a, etc. is tapered in width to be able to accomodate the increasingly large integrated charge. 
     The reason for having two storage bins in the tapered register for every bin in the first register is to provide for interlacing of the charges in the odd bins (1a, 3a, etc.) with the charges in the even bins (2a, 4a, etc.). 
     The time delay is inserted because of the time required to insert charge into each element in the first shift register 28, transfer it to the tapered shift register 32 and shift it down through the various storage bins therein to the output. (An illustration of a TDI device and an explanation of its operation are provided in the CCD Applications Conference Proceedings, September 1973, sponsored by the Naval Electronics Laboratory Center, San Diego, CA. in the article entitled &#34;Buried Channel CCD&#39;s for IR Applicatons,&#34; by Erb and Nummedal, pp. 157-167). 
     Since the scan rate and the clock frequency are synchronized, the signals from the same point on the image from all the detectors in a column will add coherently. The noise adds incoherently so that TDI provides a √n improvement in signal-to-noise where n is the number of detectors in a column (16 as shown in FIG. 1). The Si signal processor chip used with the CID premultiplexer would be similar in design to that used with the sandwich approach except that, since it is removed from the focal plane, it can be much larger than the detector area, relieving packing density and CCD well-saturation limitations inherent in the sandwich approach. 
     Performance of the CID IR focal plane is shown in FIG. 3. Signal and background photons are converted into charge in the CID. The CID detectors all integrate this charge for a time T s , after which the integrated charge is sampled by the readout process, converted into a voltage, and amplified by the preamplifier which has an output bandwidth B. The amplified voltage is resampled before being reconverted into charge for input into the CCD signal processor. The signal processor performs TDI and outputs a number of pulse trains corresponding to the photosignal seen by each column of the CID as the image is scanned over the module. 
     The input signal is reconstructed by a sample-and-hold process on these pulse trains. At point 3 after the sample-and-hole, the signal will have the appearance of a staircase function, for the case of uniform focal plane irradiance. The variation of signal height represents noise. 
     The outputs of the CCD modules 18 are multiplexed and fed to sample-and-hold means 21 from which they can be read out and displayed by the video means 23 which may include a television-type screen for display of the scanned IR-image. 
     FIG. 4 shows a slightly different version of the embodiment of FIG. 1. In this embodiment, all detector elements 12 of a single column of CID module 10 are read out simultaneously starting, for example, with the column at the extreme right side of the module and then proceeding to the adjacent column at its left until the column on the extreme left is reached. Each row, then, is connected to its own preamplifier 16 and each preamplifier 16 to its own gate 20 and CCD register 22. Note that only one CID module and signal processor is shown and that there would also be other modules, signal processors, final multiplexer, etc. 
     Obviously many modifications and variations of the present invention are possible in light of the above teaching. It is therefore to be understood that within the scope of the appended claims the invention be practiced otherwise than as specifically described.