Abstract:
Upon applying a discharge voltage between opposed electrodes of a plasma display panel, all electrodes other than a selected electrode are clamped at a fixed potential. To that end, a toggled voltage is supplied from a toggled voltage source and applied via a first switching circuit, to one ends of a plurality of second switching circuits in common. The other ends of the second switching circuits are respectively connected to panel electrodes and to one end of third switching circuits. The other ends of the third switching circuits are respectively held at a fixed potential. The second and third switching circuits may be driven synchronously in such manner that when one is ON, the other is OFF and vice versa when a toggled voltage is not brought to a panel electrode, that panel electrode is clamped at a fixed potential. Such a first switching circuit and a group of second switching circuits are combined into one set. There are provided a plurality of such sets, in which the other ends of the corresponding second switching circuits in the respective sets are connected in common, via blocking diodes, to one end of the corresponding third switching circuit. Thereby a compact switching matrix circuit can be formed. By means of the aforementioned driving circuit, generation of an induction voltage was prevented and the operating voltage range was broadened.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a driving system for a plasma display panel, and more particularly to a driving system for an X-Y matrix type plasma display panel employing an alternate current (A.C.) driving system. 
     In one example of an A.C.-driven X-Y type plasma display panel, a plurality of parallel, thin, linear electrodes are densely formed on a pair of insulator plates comprising of transparent glass plates or the like, respectively. The surfaces of these linear electrodes are coated with a transparent dielectric film. These respective insulator plates are placed with spacers between them in an opposed relation, with a discharge space sandwiched therebetween, so that the respective linear electrode groups may cross each other at right angles, in a matrix form. The outer periphery of the discharge space is air-tightly sealed with flint glass, and after evacuation, inert gas such as neon is filled in the space. If an A.C. voltage is applied between a pair of electrodes selected respectively from the respective groups of linear electrodes, then gas discharge occurs at the cross-point between these selected electrodes, thereby effecting a desired luminescent display. 
     For applying an A.C. voltage, a method is known in which a scanning voltage is applied to either the row electrode or the column electrode and a signal voltage which corresponds to a signal to be displayed, is applied to the other electrode. For instance, if the scanning voltage is sequentially applied to the successive row electrodes, data voltages corresponding to the characters are simultaneously applied to the column electrodes. 
     It is one object of the present invention to provide a driving system having a broad operating voltage range to be used with a plasma display panel. 
     Another object of the present invention is to provide a driving system for a plasma display panel, which has a high reliability but which does not generate false firings even under aging effects. 
     Still another object of the present invention is to provide a driving system for a plasma display panel, in which a number of driving circuits can be reduced even when there are a large number of scanning electrodes. 
     According to one feature of the present invention, there is a driving system for a plasma display panel, in which an independent driving voltage is fed to each driving output terminal by means of a switching circuit commonly connected, via respective diodes, to a plurality of driving output terminals. The voltage is fed when the driven output terminal to be driven is not clamped at a fixed voltage. 
     According to one particular feature of the present invention, a driving system provides a type of plasma display panel which is constructed so that a pair of insulator plates having linear electrodes thereon, as coated with dielectrics, are disposed in an opposed relation. In this way, the linear electrodes on the respective insulator plates may cross each other and voltages having opposite polarities are applied to the individual electrodes on the respective insulator plates. This effects a gas discharge at the cross-points between said individual electrodes. A driving circuit comprises first and second NPN transistor groups each consisting mainly of NPN transistors. The first NPN transistor group is constructed in such manner that a base of a first NPN transistor is connected to the collector of the first transistor via a resistor. The emitter and base of the first transistor are connected through a first diode with the anode side of the first diode facing to the emitter side of the first transistor. The base of the first transistor is connected to an anode side of a second diode, and the cathode side of the second diode is connected to a collector of second NPN transistor. The second NPN transistor group is constructed in such manner that the collector of the second NPN transistor is connected to cathodes of a plurality of second diodes, and the emitter of the second transistor is grounded. A driving voltage applied to the collector of the first transistor is controlled by a signal applied to the base of the second transistor in order to derive the driving voltage from the emitter of the first transistor in response to said signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram for explaining a diode matrix circuit in the prior art; 
     FIG. 2 is a circuit diagram for explaining the principle of the present invention with respect to the case of four output terminals, 
     FIG. 3 is an equivalent circuit diagram of a driving circuit for column scanning electrodes in a display panel which comprises a row of eleven characters, each consisting of five columns of discharge dots according to one preferred embodiment of the present invention; 
     FIGS. 4A to 4D are time charts for the preferred embodiment illustrated in FIG. 3; 
     FIG. 5A shows, in combination, a schematic plan view of a matrix or orthogonal electrode array in a display panel which comprises a single row of twenty characters, each consisting of a ten rows×five columns array of discharge dots, and a block diagram of a driving circuit for data electrodes which is also constructed according to the present invention; 
     FIG. 5B shows a block diagram of a driving circuit for scanning electrodes in the display panel illustrated in FIG. 5A: and 
     FIGS. 6A to 6G are time charts showing input waveforms appearing at various points in the circuit shown in FIGS. 5A and 5B. 
    
    
     Heretofore, in this type of display device, a diode matrix circuit (as disclosed in U.S. Pat. No. 4,100,461 assigned to the same assignee as this application) has been used as a scanning voltage generator circuit. An outline of a part of the diode matrix circuit is illustrated in FIG. 1. 
     In this figure, the emitters of PNP transistor 11 and NPN transistor 21 are connected to a D.C. power supply having a discharge voltage Vo and a ground potential, respectively. Identical toggled input signals are applied to the bases of the transistors 11 and 21, thereby alternately turning the transistor 11 and transistor 21 &#34;ON&#34; and &#34;OFF&#34; or &#34;OFF&#34; and &#34;ON,&#34; respectively. As a result, the discharge voltage Vo and the ground potential can be alternately derived from an output terminal P1, which is connected via diodes to the collectors of the transistors 11 and 21, in response to the toggled input signal. Then, the other transistors are all held &#34;OFF.&#34; In such a state the output terminal P1 has been selected. 
     When the transistor 11 is &#34;ON,&#34; a potential at an output terminal P2 is clamped at discharge voltage Vo. During the period when the transistor 11 is &#34;OFF,&#34; the output terminal P2 is not brought to the ground potential because the transistor 22 is maintained &#34;OFF.&#34; Since the output terminal P2 is &#34;floating&#34; with respect to the matrix circuit, an induction voltage is generated by a so-called &#34;floating capacity,&#34; such as inter-line or inter-electrode capacities in the circuit and in the plasma display panel. 
     Accordingly, the potential at the output terminal P2 has a rippled voltage change which is determined by the discharge voltage Vo and the induction voltage. If such a rippled induction voltage and a data voltage are applied between opposed electrodes at a discharge dot, a false firing may possibly occur even at an unselected dot, depending upon the magnitude of the discharge voltage Vo (around 160 V). Therefore, such a diode matrix circuit has disadvantages because there is a narrow range of applied voltages which can provide a normal picture without generating a false firing. Thus, the operating voltage range becomes narrow. The aforementioned disadvantage leads to difficulties because one can hardly see the variations of a discharge voltage of a plasma display panel, becuase of the aging effects. Because of this, the device lacks reliability as a display. 
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Now, the principle of the present invention will be described with reference to FIG. 2. In this figure, reference characters Q 1  to Q 10  designate NPN transistors; characters D 1  to D 4  designate diodes for isolating the transistors Q 4  to Q 8  from each other, characters T 1 , T 2 , t 1  and t 2  designate input terminals for selecting one of output terminals P1 to P4; and character I designates an input terminal for a toggled voltage V t  which is derived from a selected one of the ouput terminals P1 to P4 for driving the display panel. 
     At first, in order to derive the toggled voltage V t  from only the output electrode or terminal P1, a low-level signal (L) is applied to the input terminal T 1  while a high-level signal (H) is applied to the input terminal T 2 , to derive the toggled voltage V t  from the emitter of a first switch or the transistor Q 1 , while the emitter of the other first switch or transistor Q 2  is held at a fixed reference or ground voltage. At this moment, if a low-level floating signal is applied to the input terminal t 1  while a high-level floating signal is applied to the input terminal t 2 , then a second switch or the transistor Q 4  is turned &#34;ON&#34; because a third switch or transistor Q 9  is turned to &#34;OFF&#34;. The toggled voltage V t  then appears at the output electrode or terminal P1. The diodes: D 1  and D 3  prevent interference between the output terminals P1 and P3. The output terminal P 3  is held at the emitter potential of the transistor Q 2 , that is, at the ground potential. In addition, since the input terminal t 2  is at a high level, the transistor Q 10  is &#34;ON&#34;, and accordingly the output terminals P2 and P4 are also held at the ground potential. 
     In order to derive the toggled voltage V t  from the output terminal P 4 , it is only necessary to apply a high-level signal to the input terminal T 1 , a low-level signal to the input terminal T 2 , a high-level signal to the input terminal t 1  and a low-level signal to the input terminal t 2 . In a similar manner, the output condition at the output terminals P1 to P4 can be arbitrarily selected by adopting an appropriate combination of high and low levels at the input terminals T 1 , T 2 , t 1  and t 2 . 
     In this way, non-selected output terminals can always be clamped at the ground level, as described above. Hence, the generation of induction voltages would not occur, as it does with a conventional driving circuit. 
     The following example of a driving system according to the present invention will refer to FIGS. 3 and 4 in order to explain column scanning electrodes in a display panel which comprises a row of eleven characters, each consisting of five columns of discharge dots. In FIG. 3, transistors Q T1  and Q T2  correspond to the transistors Q 5  and Q 6 , respectively, in FIG. 2. In a similar manner, transistors Q T1&#39;  and Q T2&#39;  correspond to the transistors Q 1  and Q 2 , transistors Q X1  and Q X2  to the transistors Q 4  and Q 5 , transistors Q t1  and Q t2  to the transistors Q 9  and Q 10 , and transistors Q X6  and Q X7  to the transistors Q 7  and Q 8 , respectively. 
     The time charts shown in FIGS. 4A to 4D illustrate, by way of example, the case where fifty-five (5×11) output terminals P1 to P55 are sequentially selected. With reference to these figures, when the signal voltages are respectively applied to the input terminals I (FIG. 4A), t 1  to t 5  (FIG. 4B) and T i1  to T i11  (FIG. 4C), toggled voltages as shown in FIG. 4D are derived from the ouput terminals P1 to P55. 
     Both of the NPN transistors Q t1  to Q t2  are successively turned &#34;OFF&#34; for a time period of t by applying low-level signals to the signal input terminals t 1  to t 5 . The applied low-level signals have a pulse width of t in successive phase relationships. These signals successively scan the NPN transistors Q t1  to Q t5 , switching them &#34;OFF&#34;. Other low-level signals, having a pulse width of 5t, are repeatedly applied to the signal input terminals T 1  to T 11 . These signals successively scan the NPN transistors Q t1  to Q t11 , switching them &#34;OFF&#34;. More particularly, the operation is such that during only the first scanning for the transistors Q t1  to Q t5  is the transistor Q T1  turned &#34;OFF&#34;, during only the second scanning for the same transistors Q t1  to Q t5  is the transistor Q T2  turned &#34;OFF&#34;, and so on. 
     The respective collectors of the transistors Q T1&#39;  to Q T11&#39;  are commonly connected to the input terminal I, whereto the toggled voltage V t  is applied. The toggled voltage V t  alternately takes the discharge voltage V o  and the ground level G as shown at (I) in FIG. 4A. 
     At first, in order to output the waveform shown at (P1) in FIG. 4D at the output terminal P1, a low-level signal is applied to the terminal t 1  while high-level signals are applied to the terminals t 2  to t 5 , and a low-level signal is applied to the terminal t i1  as synchronized with the low-level signal at the terminal t 1 . At the same time, high-level signals are respectively applied to the terminal T i2  to T i11 . In response to the aforementioned input signals, only the transistors Q t1  and Q T1  are turned &#34;OFF.&#34; Hence, the transistors Q T1&#39; , Q X1 , Q X6 , Q X11 , . . . , Q x51  are turned &#34;ON&#34;. Accordingly, the applied toggled voltage V t  at the input terminal I is passed from the emitter of the transistor Q T1&#39;  through the collector-emitter path of the transistor Q X1  and is derived from the output terminal P1. The duration of the output signal is determined by the period t of the low-level signal applied to the terminal t 1 . It is to be noted that although the transistors Q X6 , Q X11 , . . . , Q X51  are also turned &#34;ON&#34;, the output terminals P6, P11, . . . , P51 are held at the ground potential. This occurs both because the output terminals P6, P11, . . . , P51 are blocked from the output signal at the output terminal P1 by means of the diodes D6, D11, . . . , D51, and because the transistors Q T2  to Q T11  are held &#34;ON&#34;. In addition, since the transistors Q t2  to Q t5  are all held &#34;ON&#34;, all the output terminals other than the output terminal P1 are, after all, held at the ground level. 
     Secondly, in order to derive the toggled voltage V t  from the output terminal P2, it is only necessary to apply high-level signals to the input terminals t 1  and t 3  to t 5  and to apply a low-level signal to the input terminal t 2 . At this moment, the output potential at the output terminal P1 is held at the ground level. Since the transistor Q t2  is turned &#34;OFF&#34;, the transistor Q X2 , which has been &#34;OFF&#34; up to this moment, is turned &#34;ON&#34;. Furthermore, an output signal can be generated at the output terminal P6 by applying low-level signals to the input terminal t 1  and T i2 , and high-level signals to the input terminals t 2  to t 5 , T i1  and T i3  to T i5 , respectively. 
     As understood from the above operation, the toggled voltage V t  is only derived from one output terminal while the other output terminals are all held at the ground level. This enables a resolution of the problem of generating induction voltages, and broadening the operating voltage range. For instance, in the heretofore known driving circuit employing a diode matrix, the operating voltage range for a display panel comprising eleven characters in each row was about 20 V (155 V-135 V) whereas, according to the present invention, it has been greatly broadened to 40 V (175 V-135 V). 
     FIGS. 5A and 5B illustrate another preferred embodiment of the present invention, as applied to a driving circuit for scanning electrodes, as well as to a driving circuit for data electrodes, in a plasma display panel which comprises a single row of twenty characters, each of which consists of a ten rows × five columns array of discharge dots. 
     As shown in FIG. 5A, the row electrodes in the plasma display panel are separated severed into two sections at the center, thereby forming a plurality of orthogonal arrays or matrices. The respective sections of the electrodes are led out from the left and right edges of the plasma display panel. In this circuit diagram, blocks A and B are used for simplicity of the diagram. These blocks represent the circuit portions encircled by single-dot chain line frames A and B, respectively, in FIG. 3. This driving circuit employs the method for selecting desired dots by connecting a column electrode X1 to a column electrode X51, a column electrode X2 to a column electrode X52, and so on until a column electrode X50 is connected to a column electrode X100. The outputs of each block A are used for two column electrodes, and input data signals d 1  to d 10  are distributed to row electrodes Y1 to Y10 for the ten left-side characters, and to row electrodes Y11 to Y20 for the ten right-side characters. 
     Accordingly, for the column electrode scanning circuit, only ten blocks A and the single block B suffice. On the other hand, for the electrodes Y1 to Y10 and the electrodes Y11 to Y20, four blocks A are required, that is, two groups of two blocks A, with the respective groups being connected in common to two blocks B. Terminals T o  1 to T o  10 connected independently to the respective blocks A in FIG. 5B, correspond to the terminals T o1  to T o11  in FIG. 3 with only the terminal T o11  removed. Accordingly, as will be apparent from FIG. 4C, toggled voltages having a duration 5t and a peak value V o  are repeatedly applied to the respective terminals T o  1 to T o  10, at a period of 50t in a successive phase relation-ship. In addition, terminals t 1  to t 5  of a block B, connected in common to the respective block A, correspond to the terminals t 1  to t 5  in FIG. 3. Hence, it can be readily seen that by applying the input signals shown in FIGS. 4B and 4C, respectively, to the terminals t 1  to t 5  and the terminals To1 to To10, the toggled voltage is successively generated with a duration t at the column electrodes X1 to X50 and at the column electrodes X51 to X100. 
     For convenience of illustration, the time (horizontal) axis in FIG. 6A is reduced in scale by a factor of 1/5 with respect to the time axis in FIGS. 4A to 4D. Moreover, for the purpose of clarifying the timing relation between the toggled voltage in FIG. 6A and the input waveforms at the input terminals t 1  to t 5 , the time axis in FIG. 6B is also reduced in scale by a factor of 1/5 with respect to the time axis in FIG. 4B. As examples of the output waveforms on the column electrodes X1 to X50 and X51 to X100, waveforms appearing on the column electrodes X6(X56) and X51(X1) are illustrated in FIG. 6C. FIG. 6C and FIG. 4D are depicted on the same scale of time axis. As will be seen from these figures, a toggle X-driving voltage has a duration t. A period 50t appears repeatedly on the column electrode X6(X56) as controlled by the waveform at the terminal To2 and the timing signal at the terminal t 2 , and on the column electrode X51(X1) as controlled by the waveform at the terminal To1 and the timing signal at the terminal T 1 . 
     At first, in order to make the cross-point CP1 (FIG. 5A) between the linear electrodes X6 and Y1 fire, pulses having a polarity opposite to the polarity of toggled X-driving voltage applied to X-electrode (column electrodes) are also applied to the row electrode Y1, as synchronized with the timing when the toggled X-driving voltage shown in FIG. 6C appears on the column electrode X6. To that end, toggled voltages φ 1  and φ 2  (FIG. 6E) having a polarity opposite to the polarity of the toggled voltage V t  in FIG. 4A and a duration 50t are alternately applied to the blocks A connected to the electrodes Y1 to Y10 and to the other blocks A connected to the electrodes Y11 to Y20. In this way, the toggled Y-driving voltage may be applied to the electrode Y1 during only the period synchronized with the toggled X-driving voltage on the electrode X6. 
     Accordingly, a low-level signal is applied to the data input terminal d 1  for the block B (which terminal corresponds to the electrode Y1 as synchronized with a low-level signal at the terminal t 2  which is in turn synchronized with the toggle driving voltage on the column electrode X6 as shown in FIG. 6D). Then, a toggled Y-driving voltage having both a polarity opposite to the polarity to the toggled X-driving voltage on the column electrode X6 and a duration t, appears on the electrode Y1 as shown in FIG. 6F. Therefore, the potential difference between the electrodes X6 and Y1 becomes 2 V o . Thus, a visible discharge will occur at the cross-point CP1 (FIG. 6G). At this moment, although the electrode X56 also receives the same toggled X-driving voltage that was applied to the electrode X6, the toggled voltage φ 2  applied to the opposite electrode Y11 is held at a fixed level V o . Therefore, a visible discharge will not occur at the cross-point between the column and row electrodes X56 and Y11. 
     The toggled pulses in FIGS. 6E and 6F are illustrated as being of a polarity which is opposite the polarity applied to the toggled pulses in FIG. 6A. However, even if they are of the same polarity, a similar result can be octained by shifting the toggle pulses in FIGS. 6E and 6F by one pulse width (t/10). Then the output pulses shown in FIG. 6G will be pulses swinging, between V o  and -V o , about the ground level G. 
     Now, in order to fire the cross-point CP2 (FIGS. 5A) which lies between the electrodes X51 and Y11 as in the above-described operation, it is only necessary to apply pulses to the row electrode Y11. Those pulses should have a polarity which is opposite that of the toggled X-driving voltage, and should be synchronized with the time period when the toggled X-driving voltage shown in FIG. 6C, appears on the column electrodes X51 and X1. Then, the cross-point between the column electrode X1 and the row electrode Y1 does not fire, because, as previously described, the row electrode Y1 is held at a fixed potential (V o ), at this moment. 
     In the circuit construction according to the present invention, the unselected panel electrodes are always held at the ground level. Thus, the previously described problem of generating induction voltages has been resolved, and a broad operating voltage range has been realized. For instance, in the heretofore known driving circuit, mainly consisting of a diode matrix, an operating voltage range for a display panel comprising a single row of twenty characters is about 15 V, whereas according to the above-described embodiment of the present invention, it is greatly broad-ended, up to 40 V. 
     Therefore, the present invention, realizes, a broad operating, driving voltage range, a high durability against effects, and a high reliability, each of which is described above. Moreover, by manufacturing the five circuits represented by blocks A and B in FIG. 3 in a hybrid IC, additional practical advantages can be obtained. The labor cost is reduced, the reliability is enhanced, and the space occupied by the circuit is reduced with respect to the conventional diode matrix circuit. 
     In connection with the above-discussed operation of the driving circuit, it is necessary to take the following points into consideration. First, to provide a non-flickering display utilizing a time division drive, it is necessary to refresh each electrode of the group involved with a voltage pulse train having a frequency in the order of 50 Hz or more. The repetition frequency of the low-level signal applied to the terminals T i1  to T i10  should therefore be 5 KHz (50 Hz×100 columns) or more in FIG. 5. Second, to provide a sufficiently bright display, it is necessary to supply each electrode of the relevant group with 2000 or more pulses during each second. The repetition frequency of the pulse train of the toggled voltage V t  should therefore the approximately 200 KHz (2 KHz×100 columns) or more in FIG. 5. It has been confirmed that the embodiment illustrated in FIG. 5 is stably operable at a frequency as high as 500 KHz. When the frequency of the toggled voltage V t  is 500 KHz, a sufficient brightness requires 20 microseconds or more of t in FIG. 6. This insures brightness because the number of pulses applied to each column electrode at one time is ten or more. For a non-flickering display, on the other hand, the upper limit of the above period t is 200 microseconds at operation of 500 KHz.