Abstract:
A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit ( 103 ) for down-converting an internal clock (Φ 1 ) of a LSI ( 101 ) is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit ( 102 ).

Description:
CLAIM OF PRIORITY  
       [0001]     The present application claims priority from Japanese application JP2004-303648, filed on Oct. 19, 2004, the content of which is hereby incorporated by reference into this application.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to semiconductor integrated circuits, and more particularly to a circuit for converting (down-converting) a frequency of a system clock (high-speed internal clock of LSI) to a lower frequency to control a storage circuit (more specifically, a content addressable memory (CAM) circuit). In addition, it relates to an image processing system using the same.  
         [0004]     2. Description of the Related Arts  
         [0005]     Heretofore, system LSIs (large-scale semiconductor integrated circuits) each having a built-in content addressable memory have been provided. One of such system LSIs is configured to generate a CAM control timing signal from a system clock. For example, refer to Japanese Patent  
       SUMMARY OF THE INVENTION  
       [0006]     Heretofore, since the frequency of a system clock has been at the same level as the internal operating frequency of a content addressable memory (about from 125 to 250 MHz), it has been possible to control input/output signals of the content addressable memory by use of the system clock without causing problems.  
         [0007]     However, in recent years, the frequency of a system clock is made higher (500 MHz) with the objective of improving the throughput and performance. On the other hand, a search control signal is still kept at 125 MHz. Because the operating frequency of search control largely depends on an electric current of a memory cell, it is not easy to speed up the operating frequency in question relative to surrounding logic parts.  
         [0008]     In the configuration disclosed in  FIG. 2  of Japanese Patent Laid-open No. 6-349284 described above, if a system clock is speeded up, it becomes impossible to load a coincidence line node ( 24 ) into a latch circuit ( 22 ) by a clock signal ( 26 ). This is because a response to the fall time of the coincidence line node ( 24 ) is slow, making it impossible to follow the system clock.  
         [0009]      FIG. 5  is a diagram illustrating a configuration of an image processing LSI examined by the inventor prior to the proposal of the present invention.  FIG. 6  illustrates a timing chart of the image processing LSI. A LSI clock Φ 1  whose frequency is 500 MHz is divided into four to generate a clock Φ 2  whose frequency is 125 MHz. A CAM macro is controlled by use of the clock F 2 . The table search ( 111 ) is started on the rising edge of the clock Φ 1  ( 1 ). At this time, a SEARCH enable signal for controlling the CAM macro is loaded by use of the divided clock. On the rising edge of the clock Φ 1  ( 5 ), more specifically, on the rising edge of the second cycle of the divided clock, an address output control signal is generated. The judgment/processing ( 112 ) are started at this point of time. Although the judgment/processing ( 112 ) ends in two cycles, the next control of the CAM macro can be started on the rising edge of the clock Φ 1  ( 9 ), more specifically, on the rising edge of the third cycle of the divided clock. Here, the SEARCH enable signal is inputted again to perform table update ( 113 ). As a result, the number of cycles required for the search processing becomes 12 cycles. In this configuration, because the system clock is simply divided into four to use the divided clock as the internal clock, the internal clock is subject to constraints by the system clock. As a result, for example, in a case where the number of cycles required for the processing from the table search to the table update is given by a request from the system side, the number of times of obtaining enable signals per unit cycle cannot be sufficiently achieved. This poses a problem in that it is not possible to sufficiently achieve the speedup.  
         [0010]     A typical example of the present invention will be described below.  
         [0011]     To be more specific, according to one aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a content addressable memory circuit; and a control circuit for, if an operating frequency of a control signal for controlling input/output signals of the content addressable memory circuit differs from an operating frequency of a LSI internal clock, adjusting the timing thereof.  
         [0012]     According to the means described above, in the semiconductor integrated circuit that operates with a high-speed system clock, it is possible to achieve the speedup without constraints by the system clock by controlling the content addressable memory circuit that operates at a lower speed, using the clock that is down-converted by the control circuit for adjusting the timing.  
         [0013]     One of the typical effects of the present invention including the above means is an improvement in throughput and performance.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is a diagram illustrating a configuration of a system LSI to which the present invention is applied;  
         [0015]      FIG. 2  is a diagram illustrating a configuration of a system LSI in which a plurality of content addressable memory macros are controlled;  
         [0016]      FIG. 3  is a diagram illustrating as an example a configuration of a clock control circuit shown in  FIG. 1 ;  
         [0017]      FIG. 4  is a diagram illustrating a configuration of a content addressable memory macro shown in  FIG. 1 ;  
         [0018]      FIG. 5  is a block diagram schematically illustrating a configuration of an image processing LSI to be controlled with a divided clock;  
         [0019]      FIG. 6  is a timing chart of  FIG. 5 ;  
         [0020]      FIG. 7  is a block diagram schematically illustrating a configuration of an image processing LSI to which the present invention is applied, and which uses a clock control circuit; and  
         [0021]      FIG. 8  is a timing chart of  FIG. 7 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]     Preferred embodiments of the present invention will be described in detail with reference to drawings below.  
       First Embodiment  
       [0023]      FIG. 1  illustrates a system LSI according to a first embodiment, which is an example of a semiconductor integrated circuit device to which the present invention is applied. One CAM macro  102  is placed on the system LSI  101  on which a clock control circuit according to this embodiment is placed. This embodiment is applied to, for example, LSIs for image processing.  
         [0024]     In  FIG. 1 , reference numeral  103  denotes a clock control circuit for controlling a content addressable memory macro  102   a . The clock control circuit  103  is built into the CAM macro  102 . This configuration produces effects of reducing man-hours required for mounting on LSI, and also facilitating the timing alignment between the content addressable memory macro  102   a  and the clock control circuit  103 . Signals inputted from external pins clock Φ 0 ,  104 ,  105 ,  106  are connected to the clock control circuit  103 . A buffer may also be added between each of the external pins and the clock control circuit  103 . The clock control circuit  103  receives signals from the external pins  104 ,  105 ,  106  in synchronization with the clock Φ 1  so as to generate a control signal for controlling the content addressable memory macro  102   a . In this case, a frequency of the generated signal is converted from a frequency (500 MHz) of LSI internal clock Φ 1  to a lower frequency (250 MHz/125 MHz). Each signal of address input control, data input control, address output control, and data output control is directed from the clock control circuit  103  to the content addressable memory macro  102   a . Further, an address input pin, an address output pin, a data input pin, and a data output pin are connected to the content addressable memory macro  102   a.    
         [0025]      FIG. 4  is a diagram illustrating a configuration of the content addressable memory macro  102   a . An address input end is connected to a FF 10  through a buffer. The FF 10  is controlled by address input control; and an output end of the FF 10  is connected to a decoder circuit. A data input end is connected to a FF 11  through a buffer. The FF 11  is controlled by data input control; and an output end of the FF 11  is connected to an input control circuit. The decoder circuit and the input control circuit are connected to a CAM array. The CAM array is connected to an output control circuit and an encoder circuit. An output end of the output control circuit is connected to a FF 12 ; and the FF 12  is controlled by data output control. An output of the FF 12  is output through a buffer to data output. An output end of the encoder circuit is connected to a FF 13 ; and the FF 13  is controlled by address output control. An output of the FF 13  is output through a buffer to address output.  
         [0026]     Next, operation will be specifically described. In the case of read operation, when an address is inputted, the address is loaded into the FF 10  by an address input control signal. From the loaded address, the decoder generates a signal used to select a desired memory cell of the CAM array. Next, the output control circuit reads out information stored in the selected memory cell. The information is then loaded into the FF 12  by a data output control signal. The data loaded into the FF 12  is output from the data output.  
         [0027]     In the case of write operation, an address is loaded in a manner similar to that of the read operation. Write data is loaded in parallel with the loading of the address. The write data is inputted from the data input end, and is then loaded into the FF 11  by a data input control signal. Through the input control circuit, the data is written to a memory cell selected by the address input.  
         [0028]     In the case of search operation, inputted search data is compared with information stored in the CAM array. The search data is inputted from the data input end, and is then loaded into the FF 11  by a data input control signal. The loaded data is transferred through the input control circuit to the CAM array. The transferred search data is compared with all pieces of information stored in the CAM array. The result of comparison is inputted into the encoder circuit. After that, the result of encoding is loaded into the FF 13  by an address output control signal, and is then output as an address output.  
         [0029]      FIG. 3  is a configuration diagram illustrating as an example a configuration of the clock control circuit  103 . Input signals include a READ enable signal, a WRITE enable signal, a SEARCH enable signal, and a clock Φ 1 . Output signals include an address input control signal, an address output control signal, a data input control signal, and a data output control signal. Flip-flops FF 1 , FF 2 , FF 3  are serially connected between the READ enable signal end and the data output control signal end. A flip-flop FF 4  is connected to the WRITE enable signal end. Flip-flops FF 5 , FF 6 , FF 7 , FF 8 , FF 9  are serially connected between the SEARCH enable signal end and the address output control signal end. A signal that is obtained by ORing RE 1  with WE 1  is equivalent to the address input control signal. A signal that is obtained by ORing WE 1  with SE 1  is equivalent to the data input control signal.  
         [0030]     Operation performed when each of the enable signals is inputted will be specifically described below. In principle, exclusive control must be performed for each enable signal. When it is inputted, the READ enable signal is loaded into the FF 1  by the clock Φ 1 . The READ enable signal is usually kept in a “0” state. At the time of read operation, “1” is inputted. A period of time during which “1” is inputted corresponds to a length of time during which the FF 1  is allowed to input using one cycle of the clock Φ 1 . In addition, because the read operation is performed at a frequency of 250 MHz, the READ enable signal must be inputted at intervals of at least two cycles of the clock F 1 . An output signal RE 1  of the FF 1  becomes a signal having a width of about 200 ps, which is calculated from the frequency of the clock Φ 1  (500 MHz). The output signal RE 1  is then output as an address input control signal. Moreover, the output signal RE 1  is successively loaded into the flip-flops FF 2 , FF 3  that are serially connected to each other. Then, the output signal RE 1  is output as the data output control signal after a lapse of two cycles from the rising edge of the address input control signal. This signal also has a width of about 200 ps.  
         [0031]     When the WRITE enable signal is inputted, the WRITE enable signal is loaded into the flip-flop FF 4  by the clock Φ 1 . The WRITE enable signal is usually kept in the “0” state. At the time of write operation, “1” is inputted. A period of time during which “1” is inputted corresponds to a length of time during which the FF 4  is allowed to input using one cycle of the clock Φ 1 . In addition, because the write operation is performed at a frequency of 250 MHz, the WRITE enable signal must be inputted at intervals of at least two cycles of the clock Φ 1 . An output signal WE 1  of the FF 4  becomes a signal having a width of about 200 ps, which is calculated from the frequency of the clock Φ 1  (500 MHz). The output signal WE 1  is then output as an address input control signal and a data input control signal.  
         [0032]     When it is inputted, the SEARCH enable signal is loaded into the flip-flop FF 5  by the clock F 1 . The SEARCH enable signal is usually kept in the “0” state. At the time of search operation, “1” is inputted. A period of time during which “1” is inputted corresponds to a length of time during which the FF 5  is allowed to input using one cycle of the clock Φ 1 . In addition, because the search operation is performed at a frequency of 125 MHz, the SEARCH enable signal must be inputted at intervals of at least four cycles of the clock Φ 1 . An output signal SE 1  of the FF 5  becomes a signal having a width of about 200 ps, which is calculated from the frequency of the clock Φ 1  (500 MHz). The output signal SE 1  is then output as a data input control signal. Moreover, the output signal SE 1  is successively loaded into the flip-flops FF 6 , FF 7 , FF 8 , FF 9  that are serially connected to each other. Then, the output signal SE 1  is output as the address output control signal after a lapse of four cycles from the rising edge of the data input control signal. This signal also has a width of about 200 ps.  
         [0033]     The clock control circuit  103  ensures the desired timing of each control signal by serially connecting the flip-flops (FF). In this method, centralizing locations at which the flip-flops are placed makes it possible to ensure the desired timing relatively easily. Additionally, even if the operating frequency of a storage circuit to be controlled is changed, it is possible to easily cope with the change by adjusting the number of stages of flip-flops to be serially connected. Moreover, each control signal is a control signal used to control the loading into the flip-flops. Accordingly, it is necessary to ensure the setup time and the hold time that enable the loading. An adjustment circuit for ensuring the setup time and the hold time is obtained by inserting a delay circuit thereto. The delay circuit may be configured with the even number of inverter circuits that are serially connected to each other.  
         [0034]      FIG. 7  is a diagram schematically illustrating a configuration of an image processing LSI that is controlled by the clock control circuit. The LSI  101  includes a CAM macro  102 , and an image processing logic for controlling the CAM macro  102 . In addition, the LSI  102  includes a built-in clock control circuit  103 . The clock control circuit  103  and the image processing logic are controlled by an internal clock Φ 1 . Next, a control example in which a CAM macro of an image processing system is used will be described. First of all, table search ( 111 ) is performed in four cycles by use of the CAM macro, and then the result of the table search is judged/processed ( 112 ) in the image processing logic. Further, table update ( 113 ) is performed in four cycles by use of the CAM macro. It is to be noted that although the judgment/processing are performed at least in two cycles, the number of cycles can be arbitrarily increased depending on a kind of system.  
         [0035]      FIG. 8  is a time chart illustrating signals observed when the clock control circuit included in the LSI shown in  FIG. 7  is used. The table search ( 111 ) is started on the rising edge of the clock Φ 1  ( 1 ). At this time, a SEARCH enable signal for controlling the CAM macro is inputted on the rising edge of the clock Φ 1  ( 1 ). Next, in response to the rising ( 5 ) of the clock Φ 1 , an address output control signal is generated. The judgment/processing ( 112 ) are started at this point of time. The judgment/processing ( 112 ) end in two cycles. Accordingly, on the rising edge of the clock Φ 1  ( 7 ), a SEARCH enable signal is inputted to start the table update ( 113 ). As a result, the number of cycles required for the search processing becomes 10 cycles. Accordingly, as compared with the method shown in  FIG. 5 , it is possible to decrease the number of cycles by two cycles, which enables an improvement in throughput.  
       Second Embodiment  
       [0036]      FIG. 2  illustrates a second embodiment. A plurality of CAM macros  102  are placed on a system LSI  101  on which a clock control circuit according to this embodiment is placed. This embodiment is applied to LSIs used for a network whose search bit width is large. The LSIs include, for example, IPv6. In this case, one clock control circuit  103  is used to control a plurality of CAM macros. This makes it possible to achieve an improvement in throughput, and also to reduce the chip area.  
         [0037]     In  FIG. 2 , reference numeral  103  denotes a clock control circuit for controlling a CAM macro  102 . The clock control circuit  103  is located on the LSI. With the increase in the number of CAM macros  102  to be controlled, the area efficiency increases. Signals inputted from external pins (clock F 0 ,  104 ,  105 ,  106 ) are connected to the clock control circuit  103 . A buffer may also be added between each of the external pins and the clock control circuit  103 . The clock control circuit  103  receives signals from the external pins  104 ,  105 ,  106  in synchronization with the clock F 1  so as to generate a control signal for controlling a content addressable memory macro  102   a . An address input control signal, an address output control signal, a data input control signal, and a data output control signal, which are generated, are directed from the clock control circuit  103  to the content addressable memory macro  102   a  through bus wiring on the LSI. Further, an address input pin, an address output pin, a data input pin, and a data output pin are connected to the content addressable memory macro  102   a.    
         [0038]     The invention made by the present inventor has been specifically described as above on the basis of the embodiments. However, the present invention is not limited to the above embodiments. As a matter of course, the present invention can be changed in various ways within the range without departing from the gist thereof. For example, how to configure the clock control circuit shown in  FIG. 1  is not limited to the configuration shown in  FIG. 3 . Any configuration may also be used so long as the clock control circuit has the same function.  
         [0039]     In addition, it is also possible to adopt a configuration that uses in combination the method according to the first embodiment in which the CAM macro  102  including the built-in clock control circuit is used, and the method according to the second embodiment in which the clock control circuit is located on a chip to control a plurality of content addressable memories. As a result, the present invention can also be applied even in a case where CAM macros whose operating frequencies differ from each other are placed on the same LSI.  
         [0040]     In the above description, the invention made by the present inventor has been mainly applied to the semiconductor integrated circuit having the built-in content addressable memory that is included in a field relating to the background on which the present invention is made. However, the present invention is not limited to this. The present invention can also be applied to a semiconductor integrated circuit having other kinds of built-in memories, for example, RAM or ROM.  
         [0041]     Incidentally, the reference numerals used in the diagrams of the application concerned will be listed as below. 
     101  . . . System LSI      102  . . . CAM macro      102   a  . . . Content addressable memory macro      103  . . . Clock control circuit      104  . . . READ enable signal      105  . . . WRITE enable signal      106  . . . SEARCH enable signal