Abstract:
An electronic circuit comprising an amplifier includes an output terminal (OUT) for supplying an output signal (V out ) to a load, the amplifier comprising an output transistor (N 2 , P 1 ) having a first main terminal coupled to a supply voltage terminal (V SS , V DD ) of the amplifier, a second main terminal coupled to the output terminal (OUT), and a control terminal. In order to avoid that the output transistor (N 2 , P 1 ) can enter its linear state which would cause the amplifier to act unacceptably slow for some purposes, the electronic circuit further comprises a controller adapted to prevent the output transistor (N 2 , P 1 ) to enter its linear state whereby the controller is arranged for reducing a control voltage (V cntrl ) between the control terminal and the first main terminal when an output voltage (V out ) between the second main terminal and the first main terminal is below a defined level.

Description:
BACKGROUND AND SUMMARY 
     The invention relates to an electronic circuit comprising an amplifier comprising an output terminal for supplying an output signal to a load, the amplifier comprising an output transistor having a first main terminal coupled to a supply voltage terminal of the amplifier, a second main terminal coupled to the output terminal, and a control terminal. 
     Such an electronic circuit is known from the general state of the art as shown in FIG.  1 . The known circuit comprises an amplifier having an amplifying complementary (class-AB) output stage driven by a class-A amplifying stage. The output stage may be followed by a unity-voltage-gain (follower-type) output stage (not drawn). Such an amplifier is e.g. used in integrated drivers for CRT&#39;S. 
     A high-side output branch includes n-type transistor N 1  in common-drain configuration and p-type transistor P 1  in common gate configuration. The gate of P 1  is coupled to the positive supply voltage by means of a bias voltage source E 1  of appropriate value. In almost every technology the speed of the p-type transistor is worse than than of the n-type transistor, among others due to the difference in carrier mobility&#39;s. In applications, where the speed is at the edge of what the technology offers, the p-type transistor is preferably used in common-gate configuration, as the bandwidth of the transfer from source signal current to drain signal current approaches the transistor&#39;s transition frequency f T . A low-side output transistor N 2  is biased in common-source configuration. The amplifying stage consists of differential transconductor (shown as a box g m  in the lower part) loaded by two current sources J 1  and J 2 . The differential transconductor converts the differential input voltage V in+ −V in−  to a differential output current I out+ −I out− =g m  (V in+ −V in− ), in which g m  is the transconductance. The bias current value of both current sources J 1  and J 2  is controlled by a common-mode control loop (not shown), which essentially controls the quiescent current in the output transistors N 1 , P 1  and N 2 . 
     The voltage gain of output transistors P 1  and N 2  can be large provided that they are biased in saturation and not in the linear region. Clamping circuits can monitor the drain-to-gate voltage and take appropriate action whenever these voltages tend to enter the linear region. 
     FIG. 2 shows a known clamp circuit. This type of clamp circuit is generally denoted as a “Baker” clamp. In normal operation the collector-base junction is reverse biased, diode D 1  is reversed biased and diode D 2  is forward biased. Whenever the collector voltage tends to drop to below the base voltage the diode D 1  is forward biased. The bipolar transistor N 1  then operates at near-zero collector-base voltage and the excess base drive current is bypassed via D 1 . As a results the bipolar transistor N 1  is kept out of saturation. The “Baker” clamp principle can also be applied to MOS transistors. 
     FIG. 3 shows a generalized form of the clamp circuit according to FIG.  2 . The source of transistor NN is connected to the drain of the output transistor N 2 . The gate of NN is connected to an appropriate voltage level, here symbolized by E b1 . In normal operation transistor NN is cut off. Whenever N 2 &#39;s drain voltage decreases to more than a threshold voltage below NN&#39;s gate voltage, transistor NN becomes conductive and its increasing drain current can be used in the driving circuit DRV to reduce the gate drive of output transistor N 2  to keep N 2  in saturation. 
     FIG. 4 shows another generalized form of the clamp circuit according to FIG.  2 . The gate of transistor PP senses the drain voltage of output transistor N 2 . In normal operation the transistors NN and PP are cut off. Whenever N 2 &#39;s drain voltage decreases too much (to be set by the value of E b1  and threshold voltages of NN and PP) the transistor pair NN/PP becomes conductive and its increasing channel current can be used in driving circuit DRV to reduce the gate drive of output transistor N 2 . Contrary to the circuit principle of FIG. 3 the clamping current is not conducted by the output transistor N 2 . 
     FIG. 5 shows an input signal attenuator, known from U.S. Pat. No. 5,304,865. It comprises a MOS transistor NN and a resistor R 3 , to be used in conjunction with a comparator. The source node of the MOS transistor NN can be used to sense the drain voltage. As long as this voltage is higher than the gate voltage, the MOS transistor is in saturation and the channel is cut off. The source voltage is approximately equal to the gate voltage. If the drain voltage falls below the gate bias voltage, the MOS transistor NN is rendered conductive in the linear range and the source voltage follows the drain voltage. 
     For some applications it can (unintentionally) occur that the output voltage V out  at the output terminal OUT is so low that the transistor N 2  enters its linear operating state. This causes the amplifier to react relatively slow. A similar situation, with regard to the combined transistor pair N 1 /P 1 , occurs when the output voltage V out  becomes too high. The former situations can occur when the amplifier is for instance used as a CRT-cathode-driving amplifier. High voltages characterize it: the applied supply voltage E sup  and the required output voltage V out  swing exceed the allowable gate-source voltage of for instance the transistor N 2  (some 20V) by far. The supply voltage E sup  can range between 50V and 250V and the required peak-to-peak output voltage V out  swing ranges from 40V (monochrome monitors), via 100-150V (color television) to 200V (color projection television). These applications require a speed (bandwidth, slew rate, rise time etc.) which is at the edge of what technology offers. It therefore is of prime importance that the parasitic capacitances at the gates of N 1  and N 2  in FIG. 1 are minimized. 
     In order to get the highest speed as possible it is necessary to avoid the output voltage V out  to become too high or too low, so that the transistor N 2  and the combined transistor pair N 1 /P 1  are kept in their normal state of operation. In prior art circuits this is accomplished by the application of, for instance, one of the circuits as shown in FIGS. 2-4. Further the requirements for a low power consumption dictates low bias currents. 
     In the “Baker” clamp of FIG. 2 the clamping diode D 1  needs to withstand a reverse-bias voltage far exceeding 10V. This implies that the shallow-p (SP) to n-epitaxial layer must be used. In a junction-isolated technology forward biasing of the SP-epi junction has the disadvantage that a parasitic substrate pnp transistor is activated: the SP region acts as emitter, the epilayer as base and the p-type substrate as collector. To reduce the pnp current gain the SP-epi junction has to be surrounded as much as possible by high-dope n-type material (buried-n and deep-n diffusions). The consequences are severe: the allowable reverse-bias voltage across the diode D 1  is reduced, and the layout size and thus parasitic capacitances are increased. For high reverse-bias voltages a series connection of more diodes might be needed, which increases layout size and parasitic capacitances even more. Thus the “Baker” clamp of FIG. 2 offers too high parasitic capacitance and cannot be applied if a high speed is important. 
     The generalized “Baker” clamp principles of FIG.  3  and FIG. 4 cannot be be applied, because the clamping transistors are tied to the high-voltage-swing node with their gate or their source, which is not allowed in normal IC-processes. (The transistors can be damaged). 
     For detecting whether the output voltage V out  is too low (or too high), the circuit shown in FIG. 5 can be used (in which the source voltage of the MOS-transistor NN forms an input voltage for a comparator). 
     It is an object of the invention to provide an electronic circuit provided with an amplifier having a high (transient) speed irrespective whether the amplifier is applied in a low, medium, or high voltage electronic system. 
     To this end, according to the invention, an electronic circuit is provided comprising: 
     an amplifier comprising an output terminal for supplying an output signal to a load, the amplifier comprising an output transistor having a first main terminal coupled to a supply voltage terminal of the amplifier, a second main terminal coupled to the output terminal, and a control terminal; and 
     control means for avoiding the output transistor to enter its linear state, the control means being arranged to reduce a control voltage between the control terminal and the first main terminal when an output voltage between the second main terminal and the first main terminal is below a defined level. 
     The invention is based on the insight that if the voltage across the output transistor becomes too low, as a consequence of which the output transistor unintentionally enters its linear operating state, this is in fact caused by a too high control voltage at the output transistor. Thus by reducing the control voltage, when the voltage across the main current path of the output transistor tends to become too low, the voltage across the said main current path will no longer decrease. (In fact a negative feedback loop is created) Thus the output transistor stays in its normal state of operation thereby avoiding the amplifier to react with reduced speed. 
     In an embodiment of a circuit according to the invention the control means comprises level detection means for, during operation of the electronic circuit, supplying a substantial change in voltage difference when the output voltage becomes lower than the defined level, and transconductor means for supplying a control current to the amplifier for reducing the control voltage on respond to the control current. Due to the fact that the level detection means delivers a substantial, thus not a very small, change in voltage difference it is assured that the control voltage is only adapted when needed, and not by an undesired offset-voltage, which may for instance be in the transconductor means. This makes the circuit easier to design (less sensitive to design parameters) and more reliable. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further advantageous embodiments of the invention are specified in dependent claims. 
     The invention will be described in more detail with reference to the accompanying drawing, in which: 
     FIG. 1 is a circuit diagram of a known amplifier; 
     FIG. 2 is a circuit diagram of a known clamp circuit; 
     FIG. 3 is a circuit diagram of a generalized form of the clamp circuit according to FIG. 2; 
     FIG. 4 is a circuit diagram of another generalized form of the clamp circuit according to FIG. 2; 
     FIG. 5 is a circuit diagram of a circuit for detecting whether a certain voltage is too low; 
     FIG. 6 is a circuit diagram of a first embodiment of an electronic circuit according to the invention; 
     FIG. 7 is a circuit diagram of a second embodiment of an electronic circuit according to the invention; 
     FIG. 8 is a circuit diagram of a third embodiment of an electronic circuit according to the invention; 
     FIG. 9 is a circuit diagram of a fourth embodiment of an electronic circuit according to the invention; 
     FIG. 10 is a circuit diagram of a fifth embodiment of an electronic circuit according to the invention; 
     FIG. 11 is a circuit diagram of a sixth embodiment of an electronic circuit according to the invention; 
     FIG. 12 is a circuit diagram of a seventh embodiment of an electronic circuit according to the invention; 
     FIG. 13 is a circuit diagram of an eighth embodiment of an electronic circuit according to the invention; and 
     FIG. 14 is a circuit diagram of a ninth embodiment of an electronic circuit according to the invention. 
    
    
     In these figures parts or elements having like functions or purposes bear the same reference symbols. 
     DETAILED DESCRIPTION 
     FIG. 6 shows schematically an amplifier having a driving circuit DRV (input stage) and an output stage. Only output transistor N 2  is shown in the output stage. In fact the amplifier can be implemented in many ways, for instance in the way as shown in FIG.  1 . The circuit further comprises level detection means implemented by sensing transistor N 3  and resistor R 3 , and transconductor means GM. The operation of the circuit is as follows: 
     The gate of N 3  is biased at an appropriate DC voltage, here symbolized by voltage E b1  with respect to the source of N 2 . The size of transistor N 3  may be small, which minimizes the parasitic capacitive load. The source of sensing transistor N 3  is connected to the input of the transconductor GM. In normal operation of output transistor N 2  (at sufficiently high drain voltage) sensing transistor N 3  is in saturation and is cut off, and its source voltage is approximately constant and approximately equal to E b1 . Transconductor GM is designed such that under these circumstances it is not activated, so it has a negligible output current I cntrl . 
     When N 2 &#39;s drain voltage decreases, the drain-to-source voltage of sensing transistor N 3  also decreases. As long as N 3  is in saturation, its source voltage is approximately constant, though. Finally N 3  enters the linear region and N 3 &#39;s source voltage will decrease approximately linearly with the drain voltage. This will activate the transconductor GM to produce an output current I cntrl . The transconductor GM output current is applied in the driving circuit DRV to reduce the gate drive V cntrl  for output transistor N 2  such that N 2  is kept in its saturation region. In fact this takes place in an analogue feedback loop. Sensing transistor N 3  enters its linear region essentially before the output transistor N 2  would do in the known circuit. 
     FIG. 7 shows an alternative implementation of a circuit according to the invention. Compared to FIG. 6 the resistor R 3  is removed and the sensing transistor N 3  is biased by a current source J b1 . In normal operation of output transistor N 2  sensing transistor N 3  is in saturation and conducts a current of value J b1 . Contrary to the circuit of FIG. 6 the source voltage will be lower than the gate bias voltage E b1 . Transconductor GM is designed such that its output current I cntrl  is negligible in these circumstances. 
     Whenever N 3  enters the linear region its source voltage decreases and the transconductor GM is activated. In analogy to the circuit principle of FIG. 6, the analogue clamping feedback loop, which is formed with the driving circuit DRV, keeps output transistor N 2  in its saturation region. 
     FIG. 8 shows the circuit of FIG. 7 in which the transconductor GM is implemented by transconductor transistor P 4 . In normal operation sensing transistor N 3  is in saturation, and bias voltage source E b6  is chosen such that transistor P 4  is cut off. When N 3  enters the linear region its gate-source voltage increases, which activates P 4  to convert its gate-source voltage change to an output current change. 
     The transconductor GM can also be implemented with a complementary pair of transistors N 4 /P 4 , as shown in FIG.  9 . The gate of N 4  is coupled to the gate of N 3 , e.g. by means of a direct connection, as shown in FIG.  9 . In normal operation sensing transistor N 3  is in saturation and its gate-source voltage is smaller than the sum of threshold voltages of the complementary pair N 4  and P 4 , such that N 4  and P 4  are cut off. When N 3  enters the linear region its gate-source voltage increases and finally goes beyond the sum of threshold voltages of N 4  and P 4 . The complementary pair N 4 /P 4  is activated and behaves as a transconductor, converting an input voltage difference to an output current change I cntrl . 
     In FIG. 6, FIG. 7, FIG.  8  and FIG. 9 the gate voltage of the sensing transistor N 3  is coupled to N 2 &#39;s source voltage by means of bias voltage source E b1 , but it can also be coupled to the output transistor&#39;s gate voltage. In FIG. 10 the invention is applied to the high-side complementary output pair N 1 /P 1  of FIG.  1 . The current in N 5 /P 5  can be used in the driving circuit DRV to close the feedback loop to keep output transistor P 1  in its saturation region. 
     The circuits and clamping principles of FIG. 8, FIG.  9  and FIG. 10 can be combined with the amplifier of FIG. 1, as shown in FIG.  11 . In FIGS. 11-14 GM and GM 2  have similar functions. This is also true with respect to I cntrl  and I 2   cntrl  Preferably, parasitic capacitances at the gates of N 1  and N 2  are minimized. The output currents of the transistors P 4  respectively N 5  therefore are inserted at the sources of common-gate-biased transistors. P-type transistors P 6  and P 7  serve as cascode transistors to the common-mode current sources J 1  and J 2 . Their gates are biased by bias voltage source E b4 . N-type transistor N 6  serves as cascode transistor for the differential-mode transconductor GM at the amplifier inputs, and is biased by bias voltage source E b5 . Transistor N 5  is activated when the output voltage rises too much, and draws a current from the left amplifier branch at the source of P 6 . Transistor P 4  is activated when the output voltage decreases too much, and delivers a current into the left branch at the source of N 6 . Whenever either one of the transistors P 4  or N 5  is activated the common-mode control loop (which is not shown in the figures, it is however generally known that differential amplifiers having differential outputs do need such control loops) is influenced. It therefore is better to insert differential mode currents, as shown in FIG.  12 . 
     The complementary pair N 5 /P 5  is activated when the output voltage V out  rises too much, and draws a current I 2   cntrl  from the left amplifier branch (at the source of P 6 ) and delivers it into the right branch (into the source of N 7 ). 
     The complementary pair N 4 /P 4  is activated when the output voltage V out  decreases too much, and draws a current I cntrl  from the right amplifier branch (at the source of P 7 ) and delivers it into the left branch (into the source of N 6 ). 
     Both clamping mechanisms produce differential-mode currents counteracting the differential-mode current from the differential-mode transconductor g m . Thus the common-mode current is unaltered and either one of the clamping circuits does not influence the common-mode control loop. 
     Another example is shown in FIG.  13 . NPN transistors N 8  and N 9  together with resistor R 89  form the input differential transconductor, biased by current sources J b8  and J b9 . The drain currents of P-type MOS transistors P 4  and P 5  are inserted at the emitters of the input transistors N 8  and N 9 . 
     Normally the amplifiers are applied in negative feedback configuration with a signal voltage attenuator from output to inverting input (not shown). The attenuator usually consists of resistors and/or capacitors. This offers the opportunity to use the inverting input for clamping purposes as well: the channel current of the transconductor N 5 /P 5  (or N 4 /P 4 ) 3  need not necessarily be applied to the driving electronics in differential form. FIG. 14 shows an amplifier in which the drain of the n-type transistor N 5  is tied to the positive supply voltage and the drain of the p-type transistor P 5  is tied to the inverting input of the amplifier. Thus again, the common-mode control loop, which controls the values of current sources J 1  and J 2 , is not influenced when the complementary pair N 5 /P 5  is activated. 
     There are many more ways to feed back the channel currents of the transconductor (e.g. N 4 /P 4  or N 5 /P 5 ) into the driving electronics, and close the clamping feedback loop. The way it is done may have consequences for the stability and bandwidth of the clamping feedback loop, which in fact has to overrule the normal signal path whenever either one of the output transistors has to be clamped. For that reason it is mandatory that the clamping feedback loop has at least the same bandwidth as the normal signal path, but preferably has a higher bandwidth. In that sense the circuit of FIG. 13 is to be preferred above the circuit of FIG.  14 : the clamping feedback loop encloses less transistors in FIG.  13  and thus has less poles, which in general favors stability. 
     In the figures most transistors are shown as field effect transistors by way of example. They can however, be replaced party or wholly by bipolar transistors. Further in FIG. 13 the input transistors N 8  and N 9  can be replaced by MOS transistors. 
     Further P-type and N-type transistors can be replaced by N-type and P-type transistors.