Abstract:
An edge-triggered latch is disclosed which has a low setup time and almost no metastability problem. It comprises a dynamic sensing means for detecting the voltage level of the data signal and at least one dynamic buffer for amplifying said detected voltage level into one of two logic levels recognizable by a static latch wherein the sampled result is stored.

Description:
TECHNICAL FIELD 
     This invention relates to edge-triggered latches. More particularly, this invention relates to apparatus and method for decreasing the setup time of an edge-triggered latch, as well as the probability of its having a metastability problem. 
     BACKGROUND OF THE INVENTION 
     Edge-triggered latches have commonly been used in electronic systems for sampling externally generated signals. In most applications, such signals would arrive asynchronously with respect to the system clock which controls a system&#39;s internal operations. A signal input is usually sampled with the edge of the system clock which triggers a latch to register the state of the signal. Ideally, the input signal should be sampled only when it is in either one of two bistable states, each representing a binary value. Unfortunately, there often exists a high probability that, at any sampling instant, the signal level is at the metastable state of the latch, i.e. at a level where the state is indeterminable. 
     To lower the probabilty of metastability, conventional edge-triggered latches are required to have a setup time, which is the minimum duration in which the input signal has been settled in one of the bistable states before the occurrence of the sampling pulse. When high speed signal processing is required, however, an edge-triggered latch having low setup time and decreased metastability problem is desired. 
     U.S. Pat. No. 4,227,699 discloses a latch circuit operable as a D-type edge trigger which is basically formed by combining two polarity latches with other logic circuits. Although the latch can conform to LSSD design rules, it nevertheless suffers from long setup time and metastability problem. 
     It is an object of this invention to provide apparatus and method for reducing the setup time of an edge-triggered latch. 
     It is also an object of this invention to provide apparatus and method for eliminating a metastability problem in an edge-triggered latch. 
     SUMMARY OF THE INVENTION 
     In one aspect, the present invention is an apparatus for producing an edge-triggered signal based upon detecting the logic state of a data signal input. The apparatus comprised a dynamic sensing means receiving the data signal and a trigger signal for detecting the voltage level of the data signal; and at least one dynamic buffer coupled to said sensing means for amplifying said detected voltage level into one of two logic levels recognizable by a static latch. 
     In another aspect, this invention is a method for detecting the logic state of a data signal input being sampled by an edge-triggered latch. The method comprises the steps of: detecting the voltage level of the data signal using a dynamic sensing means; and amplifying the detected voltage level using at least one dynamic buffer into one of two logic levels recognizable by said static latch. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic circuit diagram of one implementation of the present invention. 
     FIG. 2 is a schematic diagram of a circuit which generates a one-shot pulse from the rising edge of a clock signal. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, there is shown a schematic diagram of a preferred implementation of the present invention. A first dynamic buffer, comprises a first pair of cross-coupled p-channel Field Effect Transistors (FETs), T 11  and T 12 , is connected between nodes V 1  and V 2 . A dynamic buffer is characterized by its not being able to enter into a metastable state. A second dynamic buffer, comprises a second pair of cross-coupled n-channel FETs, T 13  and T 14 , is also connected between nodes V 1  and V 2  in parallel with the first dynamic buffer. The two dynamic buffers amplify voltage signals across these two nodes into full logic level. 
     Both T 11  and T 12  are enabled by the negative phase of sampling clock φ (i.e. -φ) which controls the gate of p-channel FET T 10 . Both T 13  and T 14  are enabled by the positive phase of the sampling clock φ which controls the gate of n-channel FET T 2 . 
     A dynamic sensing device is connected to node V 1  for receiving a differential input of the signal to be sampled. This dynamic device comprises two n-channel FETs, T 16  and T 18 , connected in series. Similarly, at node V 2  is conneced another dynamic sensing device for receiving the opposite differential input of the signal to be sampled, This dynamic device comprises two serially connected n-channel FETs, T 15  and T 17 . 
     Between nodes V 1  and V 2  is a precharging FET, T 1 , which provides a path between these nodes. When T 1  conducts, nodes V 1  and V 2  connect and their voltage levels are equalized, thereby allowing them to switch faster. The gate of T 1  is controlled by the negative phase of the sampling clock φ (i.e. -φ). 
     Each of the differential outputs of the dynamic buffer DL is transferred to respective input devices, T 5  and T 6 , of static latch SL. SL consists of n-channel FETs T 20 , T 21 , T 22 , and T 23 . The differential output at node V 1  is transferred to T 5  via a n-channel FET T 3 . The differential output at node V 2  is transferred to T 6  via a p-channel FET T 4 . The gates of both T 4  and T 3  are controlled by a clock φ&#39; which is a time delayed pulse of φ. One method of generating φ&#39; is by delaying the rising edge (the triggering edge) of clock φ. A circuit for accomplishing such purpose is illustrated in FIG. 2. 
     Let T=0 be the sampling time. Before T=0, clock 100  would be &#34;low&#34; and its inverted clock -φ would be &#34;high&#34;. Devices T 10  and T 2  are thereby cut off while device T 1  opens. The opening of device T 1  equalizes node voltages V 1  and V 2  at T&lt;0. Moreover, since devices T 3  and T 4  are cut off, static latch SL is not affected. 
     At the sampling instant, T=0, φ goes up. Precharging device T 1  is disabled. The differential inputs of the signal being sampled, received at T 17  and T 18 , are gated by devices T 15  and T 16  to nodes V 1  and V 2 . Devices T 10  and T 2  set the latch quickly. The output at nodes V 1  and V 2  are then sent to input devices, T 5  and T 6  respectively, of the static latch SL. The pass gates T 3  and T 4  a re controlled by φ&#39; which goes up with φ at a delay so that the dynamic latch can be set without too much load. Also, φ&#39; is generated as a one shot clock following the rising edge of φ so that the outputs of the static latch SL stays constant until the next trigger time. 
     Although the circuit is implemented with particular semiconductor device type, it will be understood by those skilled in the art that other devices having the same characteristics can be used. For example, p-channel FETs can be replaced by n-channel FETs in the circuits if corresponding changes on other parts of the circuits are made. Thus, while the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set forth and described above, without departing from the spirit, scope and teaching of the invention.