Abstract:
A write path scheme in a synchronous DRAM having: a data converter unit to convert serial input data to parallel output data, a multiplexer to output data from the data converter unit depending on a first mode selection signal and a second mode selection signal, and a data input/output sense amplifier having a plurality of sense amplifiers to separately operate the plurality of sense amplifiers depending on the first mode selection signal and the second mode selection signal to sense data from the multiplexer and then load the data on a global input/output line. Also included is a write driver to load data from the global input/output line on a local input/output line.

Description:
BACKGROUND 
   1. Technical Field of the Invention 
   The present patent relates to a write path scheme in a synchronous dynamic random access memory (DRAM) and, more particularly, to a write path scheme in a DDR II SDRAM. 
   2. Discussion of Related Art 
   As a DDR I SDRAM has been replaced with a DDR II SDRAM, new regulations for write latency have been applied in order to increase efficiency of buses. According to the new regulations, column operations are defined on two-clock basis, and specification for interrupt operations is defined not to be stringent. 
     FIG. 1  is a block diagram showing a conventional write path scheme. Referring to  FIG. 1  input data DIN are input to a data input buffer  10  in a serial manner. Such serial input data are latched in a data converter unit which includes first to seventh latches  20  to  80  depending on the rising and the falling edge signals dsrp 4  and dsfp 4  of a data strobe signal DQS from a DQS buffer  80 . Then, four-by-four aligned data (i.e., Algn — dinr 0 , Algn — dinf 0 , and Algn — dinr 1 , Algn — dinf 1 ) are simultaneously input to a Din multiplexer  100  in a parallel manner depending on the rising and the falling edge signals dsrp 4  and dsfp 4  of the data strobe signal DQS. The Din multiplexer  100  outputs 16, 32, or 64 data din — algn — data to a data input/output sense amplifier  110  depending on X 4 , X 8 , or X 16  mode. The data input/output sense amplifier  110  is constructed with 64 sense amplifiers, which outputs the data sensed in the data input/output sense amplifier  110  through 64 global input/output lines GIO to a write driver  120  depending on a control signal dinstbp generated from a data input strobe signal generator  90 . 
   The write driver  120  is separately operated depending on X 4  and X 8  mode selection signals to load input data on local input/output lines LIO and LIOB. 
   For the conventional write path scheme described above, 64 sense amplifiers in the data input/output sense amplifier unit are arranged to be operated irrespective of X 4 , X 8 , or X 16  mode, so that 64 global input/output lines are toggled. As a result, since the global input/output lines, which are not used in the X 4  or X 8  mode, are also toggled, there is a problem with how much power consumption is needed. 
   SUMMARY 
   Accordingly, the disclosed embodiments are directed to provide a write path scheme in a synchronous DRAM capable of remedying the above shortcomings. 
   A second aspect is directed to reduce the power consumption by separately operating the data input/output sense amplifier depending on the mode selection signals. 
   Accordingly, a write path scheme in a synchronous DRAM includes a data converter unit for converting serial input data to parallel output data; a multiplexer for outputting data from the data converter unit depending on a first mode selection signal and a second mode selection signal; a data input/output sense amplifier, having a plurality of sense amplifiers, for separately operating the plurality of sense amplifiers depending on the first mode selection signal and the second mode selection signal to sense data from the multiplexer and then load the data on a global input/output line; and a write driver for loading data from the global input/output line on a local input/output line. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aforementioned aspects and other features of the disclosed embodiments will be explained in the following description, taken in conjunction with the accompanying drawings, wherein: 
       FIG. 1  is a block diagram showing a conventional write path scheme; 
       FIG. 2  is a block diagram showing an exemplary embodiment of a data input/output sense amplifier according to the present invention; 
       FIGS. 3A and 3B  are detailed circuit diagrams showing the first to fourth enable circuits shown in  FIG. 2 ; 
       FIG. 4A  is a detailed circuit diagram showing a first coding unit shown in  FIG. 3A ; 
       FIG. 4B : is a detailed circuit diagram showing a second coding unit shown in  FIG. 3A ; 
       FIG. 4C  is a detailed circuit diagram showing a third coding unit shown in  FIG. 3A ; 
       FIG. 5  is an exemplary timing chart; 
       FIGS. 6A and 6B  show the results of an IDD4W simulation comparing the disclosed embodiments to the conventional arts; and 
       FIG. 7  is a graph for showing effects of the IDD4W reduction. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The disclosed embodiments will be described in detail with reference to the accompanying drawings, in which like reference numerals are used to identify the same or similar parts. 
   The data input/output sense amplifier of  FIG. 1  is adapted to separately operate depending on the mode selection signal in a write path structure. Because other parts are similar to those of the conventional art, the following description will be related with only the data input/output sense amplifier. 
     FIG. 2  is a block diagram showing an embodiment of an exemplary data input/output sense amplifier. 
   Typically, the data input/output sense amplifier comprises 64 sense amplifiers S 1  to S 64 . The data din — algn — data from the Din multiplexer  100  are input to each of the sense amplifiers S 1  to S 64 , and the corresponding inverted data din — algn — datab are input to each of the sense amplifier S 1  to S 64 . 
   The 1st to 64th amplifiers S 1  to S 64  can be classified into 4 blocks. 
   The 1st to 16th sense amplifiers S 1  to S 16  come to be in an enable state depending on the output din — iosa 1  from the first enable circuit  130 . The 17th to 32nd sense amplifiers S 17  to S 32  come to be in an enable state depending on the output din — iosa 2  from the second enable circuit  140 . The 33rd to 48th sense amplifiers S 33  to S 48  come to be in an enable state depending on the output din — iosa 3  from the third enable circuit  150 . The 49th to 64th sense amplifiers S 49  to S 64  come to be in an enable state depending on the output din — iosa 4  from the fourth enable circuit  160 . 
   Each output of the 1st to 4th enable circuits  130  to  160  is generated depending on the control signals (i.e., dinstb, enable — din 0 , enable — din 1 , enable — din 2 , and enable — din 3 ). How to generate the control signals (enable — din 0 , enable — din 1 , enable — din 2 , and enable — din 3 ) will be described with reference to  FIGS. 3A and 3B . 
   The coding unit  300  in  FIG. 3A  includes first to third coding units  170  to  190 . 
   The first coding unit  170  generates the coding signal xa 13   — wt based on the row address x — add&lt; 13 &gt;, the control signals F&lt; 0 : 3 &gt; and E&lt; 0 : 3 &gt;, the mode selection signals X 4  and X 8 , and the power-up signal pwrup. 
   The second coding unit  180  generates the coding signal ya 11   — wt based on the column address y — add&lt; 11 &gt;, the control signal F&lt; 0 : 3 &gt;, the mode selection signal X 4 , and the power-up signal pwrup. 
   The third coding unit  190  generates the control signal enable — din&lt; 0 : 3 &gt; based on the output ya 11   — wt of the second coding unit  180 , the output xa 13   — wt of the first coding unit  170 , and the mode selection signals X 4  and X 8 . 
     FIG. 3B  is a detailed circuit diagram showing first to fourth enable circuits  130  to  160  shown in  FIG. 2 . The output enable — din&lt; 0 : 3 &gt; of the third coding unit  190  and the output dinstb of the data input strobe signal generator in  FIG. 1  are input to the NAND gate G 1 . The output of the NAND gate G 1  is inverted by the inverter G 2  to generate the control signals din — iosa 1 , din — iosa 2 , din — iosa 13 , and ding — iosa 4 . 
   For reference, the control signal E&lt; 0 : 3 &gt; is created by a logical AND operation of a bank addresses and pulses generated at an active state. 
   If a bank&lt; 0 &gt; is in active state, E&lt; 0 &gt; comes to be at a high level, and E&lt; 1 &gt;, E&lt; 2 &gt;, and E&lt; 3 &gt; comes to be at a low level. If a bank&lt; 1 &gt; is in an active state, E&lt; 1 &gt; comes to be at a high level, and E&lt; 0 &gt;, E&lt; 2 &gt;, and E&lt; 3 &gt; come to be at a low level. If a bank&lt; 2 &gt; is in an active state, E&lt; 2 &gt; comes to be at a high level, and E&lt; 0 &gt;, E&lt; 1 &gt;, and E&lt; 3 &gt; come to be at a low level. If a bank&lt; 3 &gt; is in an active state, E&lt; 3 &gt; comes to be at a high level, and E&lt; 0 &gt;, E&lt; 1 &gt;, and E&lt; 2 &gt; come to be at a low level. 
   In addition, the control signal F&lt; 0 : 3 &gt; is generated by a logical AND operation of a bank address and a signal activated when a write operation is performed. 
   If a write operation starts to be performed for a bank&lt; 0 &gt;, F&lt; 0 &gt; comes to be at a high level, and F&lt; 1 &gt;, F&lt; 2 &gt;, and F&lt; 3 &gt; come to be at a low level. If a write operation starts to be performed for a bank&lt; 1 &gt;, F&lt; 1 &gt; comes to be at a high level, and F&lt; 0 &gt;, F&lt; 2 &gt;, and F&lt; 3 &gt; come to be at a low level. If a write operation starts to be performed for a bank&lt; 2 &gt;, F&lt; 2 &gt; comes to be at a high level, and F&lt; 0 &gt;, F&lt; 1 &gt;, and F&lt; 3 &gt; come to be at a low level. If a write operation starts to be performed for a bank&lt; 3 &gt;, F&lt; 3 &gt; comes to be at a high level, and F&lt; 0 &gt;, F&lt; 1 &gt;, and F&lt; 2 &gt; come to be at a low level. 
     FIG. 4A  is a detailed circuit diagram showing a first coding unit. The row address X — add&lt; 13 &gt; is latched in the latches L 1  and L 4  depending on operations of the transfer gates T 1  to T 4 . The transfer gates T 1  to T 4  are turned on depending on the control signal E&lt; 0 : 3 &gt;. The outputs of the latches L 1  to L 4  are inverted by the inverters G 3  to G 6 , respectively. 
   Each of the outputs of the inverter G 3  to G 6  is transferred to a node K depending on operations of the transfer gates T 5  to T 8  and then latched in the latch L 5 . The transfer gates T 5  to T 8  are turned on depending on the control signal F&lt; 0 : 3 &gt;. 
   The output of the latch L 5  is inverted by the inverter G 6 . Then, a NOR operation is performed on the mode selection signals X 4  and X 8  by the NOR gate G 7 . The output of the NOR gate G 7  is inverted by the inverter G 8 . A NAND operation is performed on the outputs of the inverters G 6  and G 8  by the NAND gate G 9 . The output of the NAND gate G 9  is inverted by the inverter G 10 , thereby generating the coding signal xa 13   — wt. Meanwhile, the power-up signal pwr — up is used to set up an initial value. 
     FIG. 4B  is a detailed circuit diagram of the second coding unit. 
   The column address Y — add&lt; 11 &gt; is transferred to a node H depending on operations of the transfer gates T 9  to T 12 , and then latched in the latch L 6 . The transfer gates T 9  to T 12  are turned on depending on the control signal F&lt; 0 : 3 &gt;. 
   The output of the latch L 6  is inverted by the inverter G 12 . A NAND operation is performed on the outputs of inverter  12  and the mode selection signal X 4  by the NAND gate G 13 . The output of the NAND gate G 13  is inverted by the inverter G 14 , thereby generating the code signal ya 11   — wt. Meanwhile, similarly to  FIG. 4A , the power-up signal pwrup is used to set up an initial value. 
     FIG. 4C  is a detailed circuit diagram of the third coding unit. The mode selection signal X 4  passes through the inverters G 16  and G 17  and then is input to the NAND gate  18 . A NAND operation is performed on the output of the inverter G 17  and the coding signal ya 11   — wt by the NAND gate G 18 , thereby generating an output A. A NAND operation is performed on the output of the NAND gate G 18  and the output of the inverter G 17  by the NAND gate G 19 , thereby generating an output B. 
   A NOR operation is performed on the mode selection signals X 4  and X 8  by the NOR gate G 20 , and then inverted by the inverter G 21 . A NAND operation is performed on the output of the inverter G 21  and the coding signal xa 13   — wt, thereby generating an output C. A NAND operation is performed on the output C of the NAND gate G 22  and the output of the inverter G 21  by the NAND gate G 23 , thereby generating an output D. 
   A NAND operation is performed on the outputs A and C by the NAND gate G 24 , and then its output is transferred to a node P after passing through the inverter G 25 . 
   A NAND operation is performed on the outputs B and C by the NAND gate G 26 , and then its output is transferred to the node P after passing through the inverter G 27 . A NAND operation is performed on the outputs A and D by the NAND gate G 28 , and then its output is transferred to the node P after passing through the inverter G 29 . A NAND operation is performed on the outputs B and D by the NAND gate G 30 , and then its output is transferred to the node P after passing through the inverter G 31 . Finally, a control signal enable — din&lt; 0 : 3 &gt; is output from the node P. 
   The disclosed embodiments can be applied to a GC 512M DDR II SDRAM. In the first coding unit, a coding operation is performed by using the row address x — add&lt; 13 &gt; if the X 8  mode is executed, and the row address x — add&lt; 13 &gt; and the column address y — add&lt; 11 &gt; if the X 4  mode is executed. The control signal E&lt; 0 : 3 &gt; contains information of an active state and a bank address. The data of the row address x — add&lt; 13 &gt; is latched at the time that the control signal E&lt; 0 : 3 &gt; is activated if Bank 0 , Bank  3 , Bank 1 , and Bank 2  are in an active state, respectively. If the signal F&lt; 0 : 3 &gt;, which contains information of a bank address and information that a write operation has been accomplished, is in an enable state, the transfer gate is opened to generate the coding signal xa 13   — wt. 
   Since the signal F&lt; 0 : 3 &gt; also activates the column address y — add&lt; 11 &gt;, the column address y — add&lt; 11 &gt; has the same transfer timing for a coding as the row address x — add&lt; 13 &gt; has if the X 4  mode is executed. 
   A control of the signal dinstb for a domain crossing is carried out depending on the signal enable — din&lt; 0 : 3 &gt; that is generated by a combination of the signals x — add&lt; 13 &gt; and y — add&lt; 11 &gt; resulted from the coding. 
   The domain crossing means the transition of the input data from a DQS domain to a clock domain. For a DDR, after the input data that are aligned with a DQS signal are input, they are internally transited to a clock domain. In other words, the data input/output sense amplifier starts to operate to load the input data on the inverter G 10  when the control signal dinstb comes to be a high level. 
   Only the data input/output sense amplifier selected by the coding of the row address x — add&lt; 13 &gt; and the column address y — add&lt; 11 &gt; can operate in an X 4  mode, whereas only the data input/output sense amplifier selected by the row address xy — add&lt; 13 &gt; can operate in an X 8  mode. 
   For a timing margin or a limitation of tCK, a control signal enable — din&lt; 0 : 3 &gt; should be generated to safely wrap up the control signal dinstbp. For this purpose, the enable timing of the F&lt; 0 : 3 &gt; should be fixed to “internal write latency—0.5tCK” as shown in  FIG. 5 . This is can be accomplished by loading the information of the bank address and the information that the write operation has been performed on the signal, which is activated at the time of “internal write latency—0.5tCK.” In case of an x 4  mode, the column address y — add&lt; 11 &gt; needs to arrive in advance of this signal F&lt; 0 : 3 &gt;, which can be accomplished by latching and outputting of the address buffer at the time of “internal write latency—1tCK”. 
   The timing chart in  FIG. 5  shows the case that a burst length is set to 4 and the write command is input in a gapless manner. 
   The enable timing of the control signal enable — din that is generated by a combination of the X 4  and X 8  mode coding signals xa 13   — wt and ya 11   — wt becomes “internal write latency—0.5tCK,” and the disable timing of the control signal enable — din becomes “internal write latency—1.5tCK.” This is because a 4-bit pre-fetch is used in a DDR II, and thus each packet is composed of 4 bits. Therefore, an interrupt operation is not assisted at BL=4. In other words, this means 4 bits are always maintained. For this reason, at least 2tCK can be maintained for the control signal enable — din (i.e., if burst length=4 in a gapless operation, or if burst length=8 in an interrupt operation, 2tCK can be maintained). The control signal dinstbp, which is a strobe signal of the data input/output sense amplifier, is activated at the time of internal write latency. Thus, the timing margin of this signal is sufficient. 
     FIG. 6A  shows the result of an IDD4W simulation according to the conventional art, while  FIG. 6B  shows the result according to the disclosed embodiments. 
     FIG. 7  is a graph for showing the result of the simulation of the IDD4W currents on the conditions of slow or fast processes, voltages, and temperatures. As described above, the power consumption in a DRAM according to the disclosed embodiments can be reduced by 23% in comparison to the conventional art. 
   According to the disclosed embodiments it is possible to reduce the power consumption in a DRAM. In addition, because not all global lines, but only 16 or 32 global lines, are toggled in an X 4  or X 8  mode, it is possible to reduce the defect that its polarity is changed due to the coupling with neighboring global lines. 
   Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood that changes and modifications of the present invention may be made by those of ordinary skill in the art without departing from the spirit and scope of the present invention and appended claims.