Abstract:
A circuit for an electronic device translates logic-low and logic-high voltage levels into other voltage levels suitable for digital intercommunication between the host electronic device and external devices, and between different external devices. The circuit comprises a power supply, a processing module, a communicating module, and a voltage converting module. The power supply provides a first voltage, a second voltage, and a pulse voltage with a predetermined duty cycle. The voltage level converting module converts incoming or outgoing logic voltage levels between a first mode and a second or more modes.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to an electronic device with a voltage level converting circuit. 
         [0003]    2. Description of Related Art 
         [0004]    Electronic devices include a voltage level converting chip for converting internal logic levels (such as transistor-transistor logic (TTL)) to standard interface line levels (such as RS-232 voltage levels) for transmitting through a serial port. For example, in the TTL logic mode, the logic voltage level of “1” is a voltage ranging from 3.6˜5V, and the logic voltage level “0” is a voltage ranging from 0˜2.4V; in the RS-232 logic mode, the logic voltage level “0” is a voltage ranging from 3˜15V, and the logic voltage level “1” is a voltage ranging from −3˜15V. The voltage level converting chip is an integrated circuit, a complicated circuit with a plurality of electronic parts. However, a new chip is needed when one of internal electronic parts in the chip is damaged. 
         [0005]    Therefore, there is room for improvement in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout two views. 
           [0007]      FIG. 1  is a block diagram of an electronic device in accordance with one embodiment. 
           [0008]      FIG. 2  is a circuit diagram of the electronic device of  FIG. 1  in accordance with one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at “least one.” 
         [0010]      FIG. 1  shows an electronic device  100  of one embodiment of the present disclosure. The electronic device  100  includes a power supply  10 , a processing module  20 , a communicating module  30 , and a voltage level converting circuit  40 . The electronic device  100  is capable of converting between logic voltage levels, from a first mode to a second mode and vice versa. In the embodiment, the electronic device  100  can be a computer or a TV, for example; the first mode is an internal logic level mode, such as the TTL mode, and the second mode is a standard interface line level mode, such as the RS-232 voltage level mode. 
         [0011]    The power supply  10  provides a first voltage, a second voltage, and a pulse voltage with a predetermined duty cycle to the voltage level converting circuit  40  when the electronic device  100  is powered on. The first voltage is higher than the second voltage. In the embodiment, the power supply  10  is an internal battery. 
         [0012]    The processing module  20  is capable of generating or receiving logic voltage levels in the first mode. 
         [0013]    The communicating module  30  is capable of outputting logic voltage levels in the second mode. In the embodiment, the communicating module  30  is a serial port, such as a RS232 port. 
         [0014]    The voltage level converting circuit  40  is connected between the processing module  20  and the communicating module  30  and receives the first voltage, the second voltage, and the pulse voltage from the power supply  10 . The voltage level converting circuit  40  converts the logic voltage levels between the first mode and the second mode. The voltage level converting circuit  40  comprises a voltage converting module  41 , a first converting module  43 , and a second converting module  45 . The voltage converting module  41  converts the received pulse voltage into a third voltage. 
         [0015]    The first converting module  41  converts the logic voltage levels in the first mode generated by the processing module  20  into the logic voltage levels in the second mode based on the first voltage, the second voltage, and the third voltage, and transmits the logic voltage levels in the second mode to the communicating module  30 . The second voltage is larger than the third voltage. 
         [0016]    The second converting module  45  converts the logic voltage levels in the second mode received through the communicating module  30  into the logic voltage levels in the first mode based on the second voltage, and transmits logic voltage levels in the first mode to the processing module  20 . 
         [0017]    Referring to  FIG. 2 , the power supply  10  includes a first voltage terminal V 1 , a second voltage terminal V 2 , and a pulse voltage terminal Vp. The first voltage terminal V 1  outputs the first voltage, the second voltage terminal V 2  outputs the second voltage, and the pulse voltage terminal Vp outputs the pulse voltage. In the embodiment, the first voltage is 5V, the second voltage is 3.3V, the logic high voltage level of the pulse voltage is 5V, and the logic low voltage level of the pulse voltage is 0V. 
         [0018]    The processing module  20  includes an input terminal I 1  and an output terminal O 1 . The input terminal I 1  is connected to the second converting module  45 , and the output terminal O 1  is connected to the first converting module  43 . 
         [0019]    The communicating module includes an input pin P 1  and an output pin P 2 . The input pin P 1  is connected to the output terminal O 1  through the second converting module  43 , and the output pin P 2  is connected to the input terminal I 1  through the first converting module  45 . 
         [0020]    The voltage converting module  41  includes a first transistor Q 1 , a first pull-up resistor R 1 , a first resistor Ra, a first capacitor C 1 , a second capacitor C 2 , an electrolytic capacitor C 3 , a first diode D 1 , a second diode D 2 , and a node A 1 . A base of the first transistor Q 1  is connected to the pulse voltage terminal Vp through the first resistor Ra. An emitter of the first transistor Q 1  is grounded. A collector of the first transistor Q 1  is connected to the first voltage terminal V 1  through the first pull-up resistor R 1 . An anode of the first diode D 1  is connected to the collector of the first transistor Q 1  through the first capacitor C 1 . A cathode of the first diode D 1  is connected to the emitter of the first transistor Q 1 . An anode of the second diode D 2  is connected to the first converting module  43 . A cathode of the second diode D 2  is connected to the collector of the first transistor Q 1  through the first capacitor C 1 . Opposite terminals of the second capacitor C 2  are connected to the anode of the second diode D 2  and the emitter of the first transistor Q 1 . An anode of the electrolytic capacitor C 3  is connected to the emitter of the first transistor Q 1 , and a cathode of the electrolytic capacitor C 3  is connected to the anode of the second diode D 2  through the node A 1 . In the embodiment, the first transistor Q 1  is an npn type bipolar junction transistor; the capacitance of the electrolytic capacitor C 3  is ten times more than the capacitance of the first capacitor C 1 . 
         [0021]    The first converting module  43  includes a MOSFET (metal oxide semiconductor field effect transistor) T 1 , a second transistor Q 2 , a second pull-up resistor R 2 , a third pull-up resistor R 3 , a fourth pull-up resistor R 4 , and second resistor Rb. A gate of the MOSFET T 1  is connected to the second voltage terminal V 2 . A source of the MOSFET T 1  is connected to the output terminal O 1 . A drain of the MOSFET T 1  is connected to the first voltage terminal V 1  through the second pull-up transistor R 2 . A base of the second transistor Q 2  is connected to the drain of the MOSFET T 1  through the second resistor Rb. An emitter of the second transistor Q 2  is connected to the first voltage terminal V 1 . A collector of the second transistor Q 2  is connected to the input pin P 1 . Opposite ends of the fourth pull-up transistor R 4  are respectively connected to the anode of the second diode D 2  and the collector of the second transistor Q 2 . In the embodiment, the MOSFET T 1  is an n-channel enhancement type metal oxide semiconductor field effect transistor; the second transistor Q 2  is a pnp type bipolar junction transistor. 
         [0022]    The second converting module  45  includes a third transistor Q 3 , a fifth pull-up resistor R 5 , and a third resistor Rc. A base of the third transistor Q 3  is connected to the output pin P 2  through the third resistor Rc. An emitter of the third transistor Q 3  is grounded. A collector of the third transistor Q 3  is connected to the input pin P 1 . Opposite terminals of the fifth pull-up resistor R 5  are connected to the collector of the third transistor Q 3  and the second voltage terminal V 2 . In the embodiment, the third transistor Q 3  is an npn type bipolar junction transistor. 
         [0023]    When the pulse voltage is in a low level, the difference between the base and the emitter of the first transistor Q 1  is less than 0.7V, and the first transistor Q 1  is turned off. The first diode D 1  is turned on and the second diode D 2  is turned off. The first pull-up resistor R 1 , the first capacitor C 1 , the first diode D 1 , and the electrolytic capacitor C 3  form a charging path to charge the electrolytic capacitor C 3 . Based on the first voltage, the voltage difference between the anode and the cathode of the electrolytic capacitor C 3  is 5V when the charging processing is ended. As the anode of the electrolytic capacitor C 3  is grounded, the voltage at node A 1 , i.e. the third voltage, is −5V. When the pulse voltage is at the high level, the difference between the base and the emitter of the first transistor Q 1  is more than 0.7V, the first transistor Q 1  is turned on and the voltage at the collector of the transistor Q 1  is almost 0V. The first diode D 1  is turned off and the second diode D 2  is turned on. The electrolytic capacitor C 3 , the second diode D 2 , the first capacitor C 1 , the collector of the first transistor Q 1 , and the emitter of the first transistor Q 2  form a discharging path. The cathode of the electrolytic capacitor C 3  provides the third voltage to the first converting module  43  through the node A 1 . Based on the pulse voltage of the predetermined duty cycle, the third voltage will always be −5V. 
         [0024]    When the output terminal O 1  generates a logic high voltage level in the first mode, the different between the gate and the source of the MOSFET T 1  is less than 0.7V, and the MOSFET T 1  is turned off. The voltage at the base of the second transistor Q 2  is equal to the first voltage outputted by the first voltage terminal V 1 . The difference between the base and the emitter of the second transistor Q 2  is less than 0.7V, thus the second transistor Q 2  is turned off. The voltage of the input pin P 1  is equal to the third voltage, as a logic high voltage level in the second mode. When the output terminal  01  generates a logic low voltage level in the second mode, the difference between the gate and the source of the MOSFET T 1  is more than 0.7V, and the MOSFET T 1  is turned on. The base of the second transistor Q 2  is grounded, thus the difference between the base and the emitter of the second transistor Q 2  is more than 0.7V. The second transistor Q 2  is turned on. The voltage of the input pin P 1  is equal to the first voltage outputted by the first voltage terminal V 1 , as a logic low voltage level in the second mode. Thus, the logic voltage levels in the first mode generated by the output terminal O 1  are converted into the logic voltage levels in the second mode received by the input pin P 1 . 
         [0025]    When the output pin P 2  generates a logic high voltage level in the second mode, the different between the base and the emitter of the third transistor Q 3  is less than 0.7V, thus the third transistor Q 3  is turned off. The voltage of the input terminal I 1  is equal to the second voltage outputted by the second voltage terminal V 2 , as the logic high voltage level in the first mode. When the output pin P 2  generates a logic low voltage level in the second mode, the difference between the base and the emitter of the third transistor Q 3  is more than 0.7V, and the third transistor Q 3  is turned on. The input terminal I 1  is grounded, as a logic low voltage level in the first mode. Thus, the logic voltage levels in the second mode generated by the output pin P 1  are converted into the logic voltage levels in the first mode which is received by the input terminal I 1 . 
         [0026]    When any internal parts of the voltage level converting circuit  40  are damaged, only the damaged/non-functioning part(s) must be replaced, there is no need to replace the whole voltage level converting circuit  40 . Therefore, the voltage level converting circuit  40  is simpler, and the cost for repairing a voltage level converting circuit  40  is reduced. 
         [0027]    It is to be understood, however, that even though information and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the present embodiments, the disclosure is illustrative only; and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the present embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.