Abstract:
An R-C relaxation oscillator having two comparators and a silicon controlled rectifier dissipates very low average power without resulting in frequency instabilities due to circuit propagation delays. A timing capacitor C T  is charged through a timing resistor R T . The first comparator compares the voltage across the timing capacitor with an upper threshold voltage V TH . When the voltage across the timing capacitor crosses the upper threshold voltage, the comparator turns on the silicon controlled rectifier, which causes the capacitor to discharge the voltage that it has stored. The second comparator turns off the silicon controlled rectifier when the voltage across the timing capacitor falls below a lower threshold voltage V TL . The silicon controlled rectifier also provides boosted comparator bias current during the discharge phase, enabling the second comparator to respond quickly to the lower threshold voltage crossing and allowing fast capacitor discharge (therefore narrow clock pulses) and increasing frequency stability.

Description:
FIELD OF THE INVENTION 
     This invention relates to the field of relaxation oscillators. More particularly, this invention relates to the field of R-C relaxation oscillators. 
     BACKGROUND OF THE INVENTION 
     The block diagram of a basic dual-comparator R-C relaxation oscillator is shown in FIG. 1. The circuit consists of three functional sub-blocks: (i) the comparators X 1  and X 2  for detecting the threshold voltages V TH  and V TL , set by the resistive divider network including the resistors R A , R B  and R C  ; (ii) the timing components including the resistor R T , the capacitor C T  and the resistor R D  ; and (iii) an R-S latch X 3  for controlling the discharge of the capacitor C T  through the npn transistor Q D  and the resistor R D . 
     Assuming that the output Q of the R-S latch X 3  is at a logical low and the transistor Q D  is turned off initially, the resistor R T  will charge the capacitor C T  towards the upper threshold voltage V TH . The upper threshold voltage V TH  is set by the resistive divider as ##EQU1## 
     The output of the comparator X 1  rises from a logical low to a logical high when the voltage across the capacitor C T  crosses the upper threshold voltage V TH  and the positive input of the comparator X 1  becomes greater than its negative input. Once the output of the comparator X 1  switches to a logical high, the input S of the R-S latch X 3  will also be raised to a logical high and the output Q of the R-S latch X 3  will rise from a logical low to a logical high. The transistor Q D  will then turn on and saturate. If the value of the resistor R D  is properly chosen, the transistor Q D  and the resistor R D  will discharge the voltage across the capacitor C T  towards the lower threshold voltage V TL  set again by the resistive divider network as ##EQU2## 
     As the voltage across the capacitor C T  is discharged below the upper threshold voltage V TH  and the positive input of the comparator X 1  becomes less than the negative input, the output of the comparator X 1  will drop from a logical high to a logical low. When the voltage across the timing capacitor C T  falls below the lower threshold voltage V TL  so that the negative input of the comparator X 2  is less than the positive input, the output of the comparator X 2  will rise to a logical high and the R-S latch X 3  will reset. When the R-S latch X 3  is reset the output Q of the R-S latch will drop to a logical low turning the transistor Q D  off and ending the discharge cycle. The resistor R T  will then charge the timing capacitor C T  and the cycle will repeat. The timing diagram of the oscillator of FIG. 1 is shown in FIG. 2. It can be shown that the charging time T C  and the discharging time T D  of the timing capacitor C T  are equal to ##EQU3## respectively. 
     Equations (3) and (4) represent the ideal charging and discharging times of the timing capacitor C T  in the absence of a propagation delay time. The effect of circuit propagation delays on the oscillator waveform is illustrated in FIG. 2. The time taken to turn on the transistor Q D  and discharge the capacitor C T  from the instant that the voltage across the capacitor C T  rises above the upper threshold voltage V TH  is represented by the time period t pd1 . Likewise the time period t pd2  represents the propagation delay time for the comparator X 2  and the R-S latch X 3  to turn off the transistor Q D  from the time that the voltage of the capacitor C T  crosses the lower threshold voltage V TL . The propagation time delays t pd1  and t pd2  will cause the oscillator period to deviate from its ideal value of the charging time period T C  plus the discharging time period T D . Good oscillator frequency stability requires that the time periods t pd1  and t pd2  be kept to a small fraction of the total time period. Usually the comparators X 1  and X 2  and the R-S latch X 3  are designed for fast responses and are biased with sufficient quiescent current to shorten the propagation delay time. 
     If the value of the resistor R D  is chosen to be much lower than the value of the resistor R T , the discharging time period T D  will be much shorter than the charging time period T C . Due to the higher rate of change in the timing capacitor C T  voltage during discharge, the propagation delay time t pd2  of the comparator X 2  causes a larger capacitor C T  voltage undershoot V US  than the capacitor C T  voltage overshoot V OS  (FIG. 2). The voltage undershoot can be defined as the difference between the voltage at the point that the capacitor C T  begins charging and the lower threshold voltage V TL . Correspondingly, the voltage overshoot can be defined as the difference between the voltage at the point that the capacitor C T  begins discharging and the upper threshold voltage V TH . The time t RCV2  taken for the capacitor C T  voltage to recover from its undershoot is much longer than the propagation delay time t pd2  for the comparator X 2  because the capacitor C T  charging rate is much lower than its discharging rate. It can also be seen from FIG. 2 that the overshoot recovery time period t RCV1  is less than the propagation delay time periods t pd1  and t pd2 , which are much less than the undershoot recovery time period t RCV2 . Since the propagation delay time t pd2  of the comparator X 2  varies with temperature and the integrated circuit fabrication process, the undershoot recovery time period t RCV2  causes by far the highest frequency instability in the type of relaxation oscillator shown in FIG. 1. In micro power circuit design, comparator quiescent current is usually kept low. However, this approach has the consequence of prolonging the propagation delay time periods t pd1  and t pd2 . 
     What is needed is a relaxation oscillator which minimizes the undershoot recovery time period t RCV2  and therefore also minimizes the frequency instability of the circuit. What is also needed is a relaxation oscillator which minimizes the propagation delay times and consumes low power. 
     SUMMARY OF THE INVENTION 
     An R-C relaxation oscillator having two comparators and an R-S latch dissipates very low average power without resulting in frequency instabilities due to circuit propagation delays. The timing capacitor C T  is charged through a timing resistor R T . The first comparator compares the voltage across the timing capacitor with the upper threshold voltage V TH . When the voltage across the timing capacitor crosses the upper threshold voltage, the comparator turns on a silicon controlled rectifier, which causes the capacitor to discharge the voltage that it has stored. The second comparator turns off the silicon controlled rectifier when the voltage across the timing capacitor falls below the lower threshold voltage V TL . The silicon controlled rectifier also provides boosted comparator bias current during the discharge phase, enabling the second comparator to respond quickly to the lower threshold voltage crossing and allowing fast capacitor discharge (therefore narrow clock pulses) and increasing frequency stability. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a schematic of a basic dual-comparator R-C relaxation oscillator of the prior art. 
     FIG. 2 illustrates a timing diagram of the oscillator of FIG. 1. 
     FIG. 3 illustrates a micro power relaxation oscillator of the present invention. 
     FIG. 4 illustrates the timing diagram of the oscillator of FIG. 3 and its improvement in undershoot recovery. 
     FIG. 5 illustrates an alternate embodiment of the oscillator of the present invention with an additional resistor R 6 . 
     FIG. 6 illustrates an alternate embodiment of the oscillator of the present invention with an additional resistor R 6  and without the resistor R 1 . 
     FIG. 7 illustrates another alternate embodiment of the oscillator of the present invention with a current sink coupled to ensure the transistor Q 11  remains off completely during a charging phase. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The micro power oscillator of the present invention is shown in FIG. 3. The schematic of the relaxation oscillator of the present invention is illustrated in FIG. 3. The resistor R T1  has a first and a second terminal. The first terminal of the resistor R T1  is coupled to the power supply V CC . The capacitor C T1  has a first and a second terminal. The second terminal of the resistor R T1  is coupled to the first terminal of the capacitor C T1  and the second terminal of the capacitor C T1  is coupled to the ground. The resistor R A1  has a first and a second terminal. The first terminal of the resistor R A1  is coupled to the power supply V CC . The resistor R B1  has a first and a second terminal. The second terminal of the resistor R A1  is coupled to the first terminal of the resistor R B1  forming the node V TH1  where the upper threshold voltage is measured from. The resistor R C1  has a first and a second terminal. The second terminal of the resistor R B1  is coupled to the first terminal of the resistor R C1  forming the node V TL1  where the lower threshold voltage is measured from. The second terminal of the resistor R C1  is coupled to the ground. 
     The transistors Q 1  and Q 2  form a first differential pair which is biased by the current source transistor Q 14 . The npn transistor Q 1  has a base, a collector and an emitter. The base of the transistor Q 1  is coupled to the node V TH1  and the collector of the transistor Q 1  is coupled to the power supply V CC . The npn transistor Q 2  has a base, a collector and an emitter and the npn transistor Q 14  has a base, a collector and an emitter. The emitter of the transistor Q 1  is coupled to the emitter of the transistor Q 2  and the collector of the transistor Q 14 . The base of the transistor Q 14  is coupled to the biasing voltage V BN  and the emitter of the transistor Q 14  is coupled to the ground. 
     The transistors Q 5  and Q 6  form a second differential pair. The pnp transistor Q 5  has a base, a collector and an emitter and the pnp transistor Q 6  has a base, a collector and an emitter. The base of the transistor Q 5  is coupled to the base of the transistor Q 2 , the second terminal of the resistor R T  and the first terminal of the capacitor C T1 . The pnp transistor Q 3  has a base, a collector and an emitter and the npn transistor Q 4  has a base, a collector and an emitter. The base of the transistor Q 6  is coupled to the base of the transistor Q 3  and to the lower threshold voltage node V TL1 . The collector of the transistor Q 3  is coupled to the ground. The transistor Q 15  has a base, an emitter, a first collector and a second collector. The base of the transistor Q 15  is coupled to the biasing voltage V BP  and the emitter of the transistor Q 15  is coupled to the power supply V CC . The second collector of the transistor Q 15  is coupled to the base of the transistor Q 4  and the emitter of the transistor Q 3 . The collector of the transistor Q 4  is coupled to the power supply V CC  and the emitter of the transistor Q 4  is coupled to the base of the transistor Q 5 , the second terminal of the resistor R T1  and the first terminal of the capacitor C T1 . The first collector of the transistor Q 15  is coupled to the emitter of the transistor Q 5  and the emitter of the transistor Q 6 . 
     The npn transistor Q 7  has a base, a collector and an emitter and the npn transistor Q 8  has a base, a collector and an emitter. The collector of the transistor Q 7  is coupled to the collector of the transistor Q 5  and the emitter of the transistor Q 7  is coupled to the ground. The collector of the transistor Q 8  is coupled to the collector of the transistor Q 6  and the emitter of the transistor Q 8  is coupled to the ground. The base of the transistor Q 7  is coupled to the base of the transistor Q 8  and the collector of the transistor Q 6 . The transistor Q 9  has a base, a collector, and an emitter. The base of the transistor Q 9  is coupled to the collector of the transistor Q 5  and the collector of the transistor Q 7  and the emitter of the transistor Q 9  is coupled to the ground. 
     The transistor Q 10  has a base, an emitter, a first collector, a second collector, a third collector and a fourth collector. The emitter of the transistor Q 10  is coupled to the power supply V CC . The base of the transistor Q 10  is coupled to the fourth collector of the transistor Q 10  and the collector of the transistor Q 2 . The first collector of the transistor Q 10  is coupled to the first collector of the transistor Q 15 , the emitter of the transistor Q 5  and the emitter of the transistor Q 6 . The second collector of the transistor Q 10  is coupled to the third collector of the transistor Q 10  and to the collector of the transistor Q 9 . 
     The resistor R D1  has a first terminal and a second terminal. The first terminal of the resistor R D1  is coupled to the emitter of the transistor Q 4 , the second terminal of the resistor R T1 , the first terminal of the capacitor C T1 , the base of the transistor Q 2  and the base of the transistor Q 5 . The transistor Q 12  has a base, a collector and an emitter. The collector of the transistor Q 12  is coupled to the second terminal of the resistor R D1  and the emitter of the transistor Q 12  is coupled to the ground. 
     The resistor R 1  has a first terminal and a second terminal. The first terminal of the resistor R 1  is coupled to the base and the fourth collector of the transistor Q 10  and to the collector of the transistor Q 2 . The transistor Q 11  has a base, a collector and an emitter. The base of the transistor Q 11  is coupled to the collector of the transistor Q 9  and to the second and third collectors of the transistor Q 10 . The collector of the transistor Q 11  is coupled to the second terminal of the resistor R 1 . 
     The resistor R 2  has a first terminal and a second terminal, the resistor R 3  has a first terminal and a second terminal and the resistor R 4  has a first terminal and a second terminal. The emitter of the transistor Q 11  is coupled to the first terminal of the resistor R 2 , the second terminal of the resistor R 3  and the first terminal of the resistor R 4 . The first terminal of the resistor R 3  is coupled to the base of the transistor Q 12  and the second terminal of the resistor R 2  is coupled to the ground. 
     The resistor R 5  has a first terminal and a second terminal. The first terminal of the resistor R 5  is coupled to the power supply V CC . The transistor Q 13  has a base, a collector and an emitter. The base of the transistor Q 13  is coupled to the second terminal of the resistor R 4 , the collector of the transistor Q 13  is coupled to the second terminal of the resistor R 5  and the emitter of the transistor is coupled to the ground. The logic signal output clk is taken from the junction of the second terminal of the resistor R 5  and the collector of the transistor Q 13 . The oscillator upper and lower voltage thresholds V TL  and V TH  are set up by the resistive divider network which includes the resistors R A1 , R B1  and R C1 . The timing components include the resistor R T1 , the capacitor C T1  and the resistor R D1 . The current source transistor Q 14  biases the differential pair including the transistors Q 1  and Q 2 . The base terminal of the transistor Q 1  is coupled to the upper threshold voltage V TH1  of the resistive divider network and the base of the transistor Q 2  is coupled to the capacitor C T1 . The transistors Q 1  and Q 2  function as the upper threshold crossing comparator (X 1  in FIG. 1). Similarly, the pnp current source transistor Q 15  biases the pnp input stage including the transistors Q 5  and Q 6  of the lower threshold crossing comparator (X 2  in FIG. 1). The transistors Q 7  and Q 8  convert the differential output currents from the transistors Q 5  and Q 6  into a single-ended voltage at the base of the transistor Q 9 . The comparator output is taken at the collector of the transistor Q 9 . A silicon controlled rectifier (SCR) includes the transistors Q 10 , Q 11 , and the resistor R 1 . The silicon controlled rectifier is used as the R-S latch (X 3  in FIG. 1). The output Q of the latch is taken at the emitter of the transistor Q 11 . The transistor Q 12  discharges the capacitor C T1  through the resistor R D1 . The resistor R 4  and the transistor Q 13  convert the logic signal at the emitter of the transistor Q 11  into a CMOS-compatible logic signal at the collector of the transistor Q 13 . The resistor R 6  is used as the load for the transistor Q 13  . The pnp transistor Q 3  functions as a level-shifter with its emitter current supplied from the transistor Q 15 . The npn transistor Q 4  shortens the undershoot recovery interval by providing a high charging current as long as the timing capacitor C T1  voltage is below the lower threshold voltage V TL1 . 
     During the timing capacitor C T1  charging phase, the SCR is cut off. No current flows through the resistor R 2 . Both of the transistors Q 12  and Q 13  are off. The output logic signal clk is at a logic high level. Since the output logic signal clk is at the same voltage level as the supply voltage V CC  during the entire charging phase of the oscillator, the average dc current through the transistor Q 13  can be kept at a very low level if the discharging time period T D1  is designed to be a small fraction of the total time period. The quiescent biasing currents for both comparators can also be kept at a very low level. 
     If the transistor Q 10  leaks current, the transistor Q 11  may not remain off completely during a charging phase. To overcome this deficiency, a bleed resistor can be coupled between the base of the transistor Q 11  and ground. In the alternative, as shown in FIG. 7 the bleed resistor can be substituted by an npn current source Q 17  with its base tied to the base and collector of a diode connected npn Q 16 , its emitter tied to ground and its collector tied to the base of the transistor Q 11 . The base and collector of the diode connected npn Q 16  are coupled to one of the emitters of the transistor Q 15  and its emitter is coupled to ground. Such a bleed resistor or current source will sink to ground the current leaked by the transistor Q 10  thereby allowing the transistor Q 11  to remain fully off during a charging phase. 
     In this design, the transistor Q 14  conducts a current of 0.25 μA and each collector of the transistor Q 15  conducts a current of 0.5 μA. The transistor Q 2  starts to conduct as the voltage across the timing capacitor C T1  approaches the upper threshold voltage V TH . The collector current of the transistor Q 2 , is drawn into the diode-connected portion of the transistor Q 10 . If each collector of the transistor Q 10  is sized equally, then a current having twice the value of the current through the transistor Q 12  will flow into the base of the transistor Q 11  (note that the transistor Q 9  is cut off when the voltage across the capacitor C T1  is near the upper threshold voltage V TH1 ). The transistor Q 11  will then start to conduct and its collector current will have a value equal to the common-emitter current gain β multiplied by two times the collector current of the transistor Q 2 . The collector current of the transistor Q 11  is doubled (due to the transistor Q 10 ) and forced into the base of the transistor Q 11 . The current in the transistor Q 11  quickly multiplies from the low initial trigger current to a value limited by the resistor R 1 . Meanwhile, the bias current for the differential pair including the transistors Q 5  and Q 6  is also increased to the level of the collector current through the transistor Q 11 . The resistor R 1  is chosen such that the current-limited SCR current is much higher than the quiescent bias current of the differential pair of the transistors Q 5  and Q 6 . Therefore, the switching speed of the lower threshold voltage V TL1  sensing comparator is increased during the discharging phase. The time periods t pd2  and t RCV2  and the undershoot voltage V US  are all reduced as is the frequency sensitivity of the oscillator due to switching delays. Once the SCR turns on, the transistors Q 12  and Q 13  conduct. The transistor Q 12  discharges the capacitor C T1  through the resistor R D1 . The transistor Q 13  pulls the output logic signal clk low. As the voltage across the timing capacitor C T1  is discharged to a level below the lower voltage threshold V TL1 , the transistor Q.sub. 9 turns on which shunts the base drive of the transistor Q 11  to the ground and cuts off the SCR. The transistors Q 12  and Q 13  also turn off. The output logic signal clk rises to a logical high and the discharge phase ends. The resistor R T1  now charges the timing capacitor C T1  and the cycle repeats itself. 
     The oscillator will dissipate very little dc power if the discharging time T D  is made much shorter than the charging time T C , i.e. if the resistor R D1  is designed to have a much lower resistance value than the resistor R T1 . The SCR and the transistor Q 13  conduct significant pulsed current only during the discharge of the voltage across the timing capacitor C T1 . This current pulse is reduced to a low average value by the duty ratio of the output logic signal clk. 
     The transistor Q 4  clamps the valley voltage of the timing capacitor C T1  ramp and offers further improvement in the undershoot recovery time period t RCV2  as illustrated in FIG. 4. In the absence of boosted tail current from the SCR, the comparator consisting of the transistors Q 5 , Q 6 , Q 7 , Q 8  and Q 9  is slow to respond to the lower threshold voltage V TL1  crossover. The transistor Q 4  pulls the capacitor C T1  up towards the lower voltage threshold V TL1 . This may result in a very small differential voltage across the transistors Q 5  and Q 6  and may actually make the switching response worse. Referring to FIG. 2, the rising edge of the logic input Y 2  is postponed and the output logic signal clk probe width cannot be reduced below a certain minimum value. 
     The oscillator described exhibits high frequency stability while consuming extremely low power. The transistor Q 4  serves to minimize the undershoot recovery and thus the recovery time period t RCV2 . Instead of the output signal clk being driven high during the discharge time period T D1  as the output signal of the prior art circuit of FIG. 1, the circuit of the present invention turns on the silicon controlled rectifier and drives the output signal clk low only during the short discharge time period T D1 . The power dissipated in the entire oscillator is kept low because the pulsed current during the discharge of the capacitor C T  averages out to a low average value. The silicon controlled rectifier supplies additional bias current to the lower threshold voltage V TL  comparator to speed up the switching time and minimize the recovery time period t RCV2 . 
     The circuit of FIG. 5 illustrates a first alternate embodiment including a resistor R 6  in the emitter circuit of the transistor Q 11  which limits current in the silicon controlled rectifier. The circuit of FIG. 6 illustrates a second alternate embodiment which limits current in the silicon controlled rectifier. The circuit of FIG. 6 includes the resistor R 6  in the emitter circuit of the transistor Q 11  but does not include the resistor R 1  in the collector circuit of the transistor Q 11 .