Abstract:
A method and system for clock synchronization of semiconductor devices. The method uses a master-slave configuration to designate a semiconductor device with the lowest rate clock source as a master device and zero all clock sources inside the semiconductor device in order to output the zeroing lowest rate clock source to slave devices for clock synchronization of all clock sources respectively in the slave devices, and further implements a phase checker in each semiconductor device to ensure clock synchronization inside and between the semiconductor devices, so required clock signals are precisely provided to next internal circuits of the semiconductor devices.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates to a clock synchronization mechanism, more particularly to a method and system for clock synchronization of semiconductor devices, which uses a master-slave configuration in conjunction with a phase checker, such that semiconductor devices synchronize the clocks and thus precisely output clock demands to ensure reliability during operation.  
           [0003]    2. Description of the Related Art  
           [0004]    At present, for clock synchronization, most designs focus on a single chip, as described in U.S. Pat. No. 5,999,025 and U.S. Pat. No. 6,304,582. The former (U.S. Pat. No. 5,999,025) essentially describes a synchronization of an external clock and an on-chip voltage controlled oscillator (VCO) clock. The latter (U.S. Pat. No. 6,304,582) essentially describes a synchronization of an oscillator clock and clocks in a chip. As cited, these clock synchronization means for multiple chips lack effectiveness with semiconductor devices in which delay locked loop (DLL) or digital clock manager (DCM) is used as a clock source.  
         SUMMARY OF THE INVENTION  
         [0005]    An object of the present invention is to provide a method and system for clock synchronization of semiconductor devices, which uses a master-slave configuration to align all clock sources from delay locked loops (DLLs) or digital clock managers (DCMs), such that semiconductor devices synchronize the clocks and thus precisely output clock demands to ensure reliability during operation.  
           [0006]    The present invention is generally directed to a method and system for clock synchronization of semiconductor devices, which uses a master-slave configuration to designate one semiconductor device with the lowest rate clock as a master element and other semiconductor devices as slave elements, use a phase checker in the master element to calibrate all clocks of the master element, use an external phase checker to respectively synchronize clocks in corresponding slave elements with the lowest rate clock and use an internal phase checker to respectively synchronize all clocks in the slave elements, thereby accurately outputting clocks required by circuits inside the semiconductor devices. 
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0007]    The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which:  
         [0008]    [0008]FIG. 1 is a block diagram of a clock synchronization of semiconductor devices with a master-slave configuration according to the invention;  
         [0009]    [0009]FIG. 2 is a block diagram of the interior of a master element of FIG. 1 according to the invention;  
         [0010]    [0010]FIG. 3 is a block diagram of the interior of a slave element of FIG. 1 according to the invention;  
         [0011]    [0011]FIG. 4 is a block diagram of the interior of a delay locked loop (DLL) clock generator according to FIG. 2 or  3  of the invention;  
         [0012]    [0012]FIG. 5 is an example of a phase checker according to the invention;  
         [0013]    [0013]FIG. 6 is a timing of an external phase checker according to the invention;  
         [0014]    [0014]FIG. 7 is a timing of an internal phase checker according to the invention;  
         [0015]    [0015]FIG. 8 is a flowchart of an operating method according to the invention;  
         [0016]    [0016]FIG. 9 is a flowchart of a synchronization of clock sources inside the master element according to FIG. 8 of the invention;  
         [0017]    [0017]FIG. 10 is a flowchart of a clock synchronization between the master and slave elements according to FIG. 8 of the invention; and  
         [0018]    [0018]FIG. 11 is a flowchart of a synchronization of clock sources inside the slave elements respectively according to FIG. 8 of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    [0019]FIG. 1 is a block diagram of a clock synchronization of semiconductor devices with a master-slave configuration according to the invention. In this case, four Field Programmable Gate Arrays (FPGAs) are embodied, without limiting the embodiment, for better explanation. For example, ten Application Specific Integrated Circuits (ASICS) can be used.  
         [0020]    As shown in FIG. 1, each Field Programmable Gate Array (FPGA) includes two major functional blocks, respectively to phase checkers  111 ,  121 ,  131 ,  141  and clock generators  112 ,  122 ,  132 ,  142 . Each clock generator  112 ,  122 ,  132 , or  142  internally include delay locked loops (DLLs) or digital clock managers (DCMs) as required clocks. Each phase checker checks rising or falling edges of the clocks for alignment. If any clock is not aligned, a reset is issued. In this case, reset signals reset 11 -reset 14  are output to reset corresponding clock generators for clock re-generation. For clock synchronization, a master-slave configuration is implemented by designating a semiconductor device with the lowest rate clock as a master element, in this case,  11 , and other semiconductor devices as slave elements, in this case,  12 - 14 . After other clocks in the master element are calibrated by the lowest rate clock (zeroing), all clocks in the slave elements are synchronized respectively by a reference clock CLKREF from the master element. The cited clock calibration and synchronization are further described in connection with delay locked loops (DLLs).  
         [0021]    [0021]FIG. 2 is a block diagram of the master element  11  of FIG. 1. In FIG. 2, the element  11  has a clock generator consisting of multiple DLLs. As shown in FIG. 2, in the master element  11 , at first, zeroing is performed by a phase checker to check if all rising or falling edges of clock sources CLKREF and clkf 1 -clkf n  are aligned. If any edge is not aligned, the phase checker  111  sends a reset signal reset 11  such that the clock generator  112  re-generates clock sources until clock sources are aligned on every rising or falling edge. At this point, zeroing is complete and an aligned clock Phase-OK is sent by the phase checker  111 . Additionally, the lowest clock source aligned is referred to as a reference clock source CLKREF and sent to the phase checker  121 ,  131  and  141  for calibrating slave devices. The clock sources are thus synchronized when the slave devices are calibrated by means of the source CLKREF. Other clock sources are applied in use of internal circuit  10  connecting with a respective slave FPGA.  
         [0022]    [0022]FIG. 3 is a block diagram of an internal circuit of any slave device according to FIG. 1 of the invention. In FIG. 3, any slave device  12 ,  13  or  14  includes a clock generator  33  formed by a plurality of DLLs all devices, and a phase checker  121 ,  131  or  141  formed by an external checker  31  and internal phase checkers  32 . As shown in FIG. 3, any slave device  12 ,  13  or  14  has two checkers  31 ,  32 . The external phase checker  31  first synchronizes a local lowest clock source clkf lowest  and the lowest clock source CLKREF and then sends a calibrated signal Phase-In-OK to the internal phase checker  32 . The internal phase checker  32  aligns other clock sources clkf 1 -clkf n  based on the calibrated signal Phase-In-OK and results in clock synchronization. Therefore, all clock sources generated by the DLLs are accurately provided to next FPGA internal circuits. However, if the local lowest clock source clkf lowest  does not synchronize with the lowest clock source CLKREF, the external phase checker  31  sends a reset signal Reset 31  to a clock generator  331  with the local lowest clock source clkf lowest  to re-generate required clock signals. If the signal Phase-In-OK does not synchronize with the local clock sources clkf 1 -clkf n , the internal phase checker  32  sends a reset signal Reset 32  to clock generators  332  with the local clock sources to re-generate required clock signals.  
         [0023]    [0023]FIG. 4 is a block diagram of a DLL interior in FIGS. 2 and 3. As shown in FIG. 4, the DLL essentially includes a variable delay line  41 , a clock distribution network  42  and a control logic  43 . The variable delay line  41  delays an external input clock CLK for a certain time and then outputs a resulting clock CLKOUT. The network  42  converts the clock CLKOUT into required rate clock sources Base-fn for corresponding circuits and a feedback signal CLKFB is sent to the control logic  43 . The control logic  43  compares rising edges of the signals CLK and CLKFB to determine if all edges of the signals CLK and CLKFB are aligned. The comparison result CMP is sent to the delay line  41  for adjustment until the alignment is complete and the DLL is locked. As such, the clock delay effect between the input clock CLK and the load is eliminated, so clock synchronization is obtained. The variable delay line can be a voltage controlled delay.  
         [0024]    [0024]FIG. 5 is an example of a phase checker according to the invention. In FIG. 5, for simple description, the phase checker only has two D-type flip-flops (D-FFs)  51 ,  52  and a finite state machine (FSM)  53 . In practice, the D-FF number used depends on required clock frequencies, generally with one-to-one relation. As shown in FIG. 5, when clock line is logic 0, a clock signal fn and a lowest clock signal f lowest  are respectively transmitted to the devices  51 ,  52  to output sampling signals CLKSAMPLE 1 , CLKSAMPLE 2  to the device  53  for phase check. In the phase checker of the master device, the lowest clock signal f lowest  represents the signal CLKREF and the signal phase-ok represents the zeroing signal Phase-OK. In the external phase checker of a slave device, the lowest clock signal f lowest  represents the signal CLKREF and the signal phase-ok represents the calibrating signal Phase-In-OK. In the internal phase checker of the slave device, the lowest clock signal f lowest  represents the local lowest clock signal clkf lowest  of the slave device and the signal phase-ok represents the zeroing signal Phase-OK. In the following, further description of timings of external and internal phase checkers is given.  
         [0025]    [0025]FIG. 6 is a timing diagram of the external phase checker of a slave device. FIG. 7 is a timing diagram of the internal phase checker of the slave device. As shown in FIG. 6, in each falling edge of input clock signal CLK, the external phase checker synchronously checks each pair of falling edges of the lowest clock signals (circle mark) CLKREF, clkf lowest  of the master device and the slave device to determine if the two have the same value. If not, a reset signal Reset is sent to re-input the two lowest clock signals for re-alignment. Two lowest clock signals having the same value indicates that the master device  11  is calibrated or the slave devices connected to the master device  11  are aligned. At this point, as shown in FIG. 7, the external checker refers to the local lowest clock signal (aligned clkf lowest ) as an aligned signal Phase-In-OK, inputting to the internal phase checker to perform aligning steps described in FIG. 6. Thus, all local clock sources required by the internal circuits of the Field Programmable Gate Array (FPGA) are aligned, in this case, f 1 -f 3 , to obtain clock synchronization of all semiconductor devices.  
         [0026]    [0026]FIG. 8 is an operating flowchart of the invention. As shown in FIG. 8, multiple clock sources are generated by clock generators inside a plurality of semiconductor devices (S 1 ). When the multiple clock sources are stable, one semiconductor device having a clock source with the lowest rate clock signal is designated as a master device and other devices are designated as slave devices (S 2 ). The lowest rate clock signal of the master device is designated as a reference clock source (S 3 ). According to the reference clock source, a phase-aligned check is performed on other clock sources in the master device, such that other clock sources of the master device are synchronized with the reference clock source to generate a zeroing signal (S 4 ). According to the zeroing signal, a phase-aligned check is respectively performed on a local lowest rate clock source in each slave device, such that all local lowest rate clock sources of the slave devices are synchronized with the lowest rate clock signal of the master device to respectively generate an aligning signal (S 5 ). According to the aligning signal, a phase-aligned check is respectively performed on other clock sources in each slave device, such that other clock sources of each slave device are separately synchronized with the local lowest rate clock signal of the respective slave devices (S 6 ). Therefore, clock synchronization for the plurality of semiconductor devices is complete.  
         [0027]    Step S 4  is further divided into the steps of FIG. 9, including that by means of rising or falling edges of an external input clock source, a phase checker in the master device is triggered to sample the clock sources inside the master device for phase alignment comparison (S 41 ); when all phases are aligned, the signal Phase-OK is output to concurrently signal each slave device (S 42 ); and otherwise, a reset signal reset is output to re-generate multiple clock sources for re-alignment operation (S 43 ).  
         [0028]    Step S 5  is further divided into the steps of FIG. 10, including that an external phase checker in each slave device respectively checks the lowest rate clock source of the master device to determine if the zeroing signal has been sent (S 51 ); when the zeroing-signal is received and all clock sources in each slave device are stable, each external phase checker performs a phase-aligned check on its respective slave device (S 52 ); when all phases are aligned, the aligning signal Phase-In-OK is respectively sent to indicate a phase alignment and clock synchronization for the lowest rate clock signal of the master device and the local lowest rate clock signal of the respective slave device (S 53 ); and otherwise, a reset signal reset is sent to re-generate the local lowest rate clock signal of the respective slave device and then repeat the aforementioned steps (S 54 ).  
         [0029]    Step S 6  is further divided into the steps of FIG. 11, including, when the aligning signal is received and all clock sources in each slave device are stable (S 61 ), an internal phase checker in each slave device performing the phase-aligned check on its respective slave device (S 62 ); when all phases are aligned, the aligning signal Phase-In-OK is sent to indicate a phase alignment for the clock sources in the respective slave device and of the clock synchronization for the semiconductor devices (S 63 ); and otherwise, a reset signal reset is sent to respectively re-generate the multiple clock sources, except the local lowest rate clock source, of the respective slave device and then repeat the aforementioned steps (S 64 ).  
         [0030]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.