Abstract:
Methods for forming a copper interconnect of a semiconductor device are disclosed. A disclosed method comprises forming a lower metal interconnect; sequentially depositing a capping layer, a first insulating layer, and a second insulating layer on the lower metal interconnect; forming a via hole by etching the first insulating layer and the second insulating layer; forming a trench and terraces by etching the second insulating layer; and exposing at least a portion of the top surface of the lower metal interconnect by etching the capping layer.

Description:
FIELD OF THE DISCLOSURE  
       [0001]     The present disclosure relates generally to semiconductor devices and, more particularly, to methods for forming a copper interconnect of a semiconductor device using a dual damascene process.  
       BACKGROUND  
       [0002]     Since efforts to improve a copper etching method have proven unsuccessful, a copper dual damascene process, which inlays copper in an interconnect line, has been developed as an alternative. The copper dual damascene process has been verified as an excellent process in terms of process affinity and cost reduction; although it had been confronted with practical barriers in terms of manufacturing apparatus due to completely different structures and across-the-board changes.  
         [0003]      FIGS. 1   a  through  1   c  are cross-sectional views illustrating a conventional process of forming a copper interconnect of dual damascene structure of a semiconductor device. Referring to  FIG. 1   a , a lower metal interconnect  11  is formed through an insulating layer on a substrate (not shown) having at least one structure. A capping layer  12  is deposited on the substrate including on the lower metal interconnect  11 . The capping layer  12  is made of silicon nitride. A first insulating layer  13  is then deposited on the capping layer  12 . The first insulating layer  13  is made of fluorinated silica glass (FSG) with a low dielectric constant. An etch-stop layer  14  is formed on the first insulating layer  13 . The etch-stop layer  14  is made of silicon nitride. A second insulating layer  15  is then deposited on the etch-stop layer  14 .  
         [0004]     Referring to  FIG. 1   b , a via hole  16  is formed through the first insulating layer  13  by photolithographic and etching processes. The photoresist pattern for forming the via hole  16  is then removed. Next, by performing another photolithography process and another etching process using the etch-stop layer  14  as a mask, a trench  17  for an upper metal interconnect is formed through the second insulating layer  15 .  
         [0005]     Referring to  FIG. 1   c , some portion of the capping layer  12  is removed by using a dry etching process to form an opening  18  on the lower metal interconnect  11 . The trench  17 , the via hole  16 , and the opening  18  are then filled with copper to complete a dual damascene interconnect connected to the lower metal interconnect  11 .  
         [0006]     In the above-described conventional process of forming a copper interconnect having a dual damascene structure, the via hole  16  is formed by sequentially dry-etching the second insulating layer  15 , the etch-stop layer  14  and the first insulating layer  13 . Therefore, a size difference between the upper part and the lower part of the etch-stop layer  14  is caused due to the etching selectivity between the etch-stop layer  14  and the second insulating layer  15 . Such a size difference may cause void formation in a copper via line when the via hole  16  and the trench  17  are filled with copper by a copper plating process. Furthermore, although the etching rate to the etch-stop layer  14  has been made substantially equal to the etching rate to the second insulating layer  15  by improving the dry etching process, overhang may occur when a barrier metal layer of Ta/TaN and a copper seed layer are deposited in the trench  17  and the via hole  16  because the width of the trench  17  is larger than the width of the via hole  16 . This overhang may cause void formation in a copper via line, thereby deteriorating the device characteristics. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]      FIGS. 1   a  through  1   c  are cross-sectional views illustrating a conventional process of fabricating a copper interconnect having a dual damascene structure.  
         [0008]      FIGS. 2   a  through  2   c  are cross-sectional views illustrating an example process of fabricating a copper interconnect having dual damascene structure performed in accordance with the teachings of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0009]      FIGS. 2   a  through  2   c  are cross-sectional views illustrating an example process of fabricating a copper interconnect for a semiconductor device. The interconnect of the illustrated example has a dual damascene structure.  
         [0010]     Referring to  FIG. 2   a , a lower metal interconnect  21  is formed through an insulating layer on a substrate (not shown) having at least one active or passive structure (e.g., a transistor or resistor). A capping layer  22  is deposited on the substrate including the lower metal interconnect  21 . The capping layer  22  prevents materials contained in an insulating layer to be formed by a later process (e.g., fluorine (F) or phosphorus (P)) from being diffused into the lower metal interconnect  21 . In the illustrated example, the capping layer  22  is preferably made of silicon nitride and has a thickness between about 200 Å and about 400 Å. A first insulating layer  23  is then deposited on the capping layer  22 . In the illustrated example, the first insulating layer  23  is preferably made of FSG which has a low dielectric constant and has a thickness between about 7000 Å and about 10000 Å. A second insulating layer  24  is then deposited on the first insulating layer  23 . In the illustrated example, the second insulating layer  24  is preferably made of phospho-silicate glass (PSG), and, thus, differs from the first insulating layer  23 .  
         [0011]     Referring to  FIG. 2   b , a photoresist pattern (not shown) is formed on the second insulating layer  24  by a photolithography process. A first dry etching process is then performed while using the photoresist pattern as a mask to remove some portion(s) of the second insulating layer  24  and the first insulating layer  23 . The photoresist pattern is then removed by an ashing process to complete a via hole  25  through the first insulating layer  23 . The illustrated example process does not use an etch-stop layer. In other words, the second insulating layer  24  is directly deposited on the first insulating layer  23  without the deposition of an etch-stop layer on the first insulating layer  23 . Therefore, the illustrated example process overcomes the size difference between the upper part and the lower part of the via hole which is present in the conventional process described above due to an etching selectivity between the etch-stop layer and the insulating layers.  
         [0012]     Next, a bottom antireflection coating (BARC) (not shown) is deposited on the resulting structure. The BARC completely fills the via hole  25 . A photoresist pattern (not shown) is formed on the BARC by a photolithography process. A second dry etching process is then performed while using the photoresist pattern as a mask to remove some portion(s) of the second insulating layer  24 . The photoresist pattern and the BARC are then removed by an ashing process to complete a trench  26  through the second insulating layer  24 . In the illustrated example, the trench  26  preferably has a depth between about 3000 Å and about 5000 Å. By performing the second dry etching process, both edge portions of the upper part of the via hole  25  are removed to form terraces  27 .  
         [0013]     In the illustrated example, the second dry etching process is performed by an etching apparatus using a dual plasma source. The etching apparatus of the illustrated example uses a source power between about 1000 W and about 1500 W, and a bias power between about 500 W and about 1000 W. In this example, the etching chamber has a volume between about 30 L and 40 L, and the internal pressure of the etching chamber is between about 20 mTorr and about 100 mTorr.  
         [0014]     In the illustrated example. the second dry etching process uses CHF 3 , CF 4 , Ar and o 2  as etching gases. The CHF 3  gas of this example is supplied at a rate between about 20 sccm (standard cubic centimeter per minute) and about 50 sccm, and the CF 4  gas is supplied at a rate between about 50 sccm and 100 sccm. Further, the Ar gas is supplied at a rate between about 100 sccm and about 400 sccm, and the o 2  gas is supplied at a rate between about 5 sccm and about 15 sccm.  
         [0015]     In the illustrated example, the depth of the trench  26  formed by the second dry etching process has a uniformity of about 3%.  
         [0016]     Further, the illustrated example terraces  27  are formed so that the inclined plane of each terrace  27  is at an angle between about 60° and about 80° from the contact surface between the trench  26  and the via hole  25 . By forming the terraces  27 , the illustrated example process achieves a metal interconnect having a substantially uniform thickness even though an etch-stop layer is not deposited on the first insulating layer  23 . Furthermore, by altering the right-angled edges between the via hole  25  and the trench  26  into the terraces  27 , the example process obviates overhang which may occur during later Ta/TaN and copper deposition processes.  
         [0017]     Referring to  FIG. 2   c , some portion(s) of the capping layer  22  are removed by a third dry etching process to form an opening  28  on the lower metal interconnect  21 . The opening  28  exposes at least a portion of the top surface of the lower metal interconnect  21 . Because the third dry etching process is performed without an etch-stop layer, the exposed portion(s) of the terraces formed by the second etching process are removed to form a complete terrace structure. In other words, both upper edges of the via hole  25  are etched more rapidly than the lower part of the trench  26  due to the intrinsic property of the etchant and, therefore, the terrace structure becomes more apparent.  
         [0018]     In the illustrated example, the third dry etching process for making the opening  28  is performed by an etching apparatus using a dual plasma source. In such an example, the etching apparatus uses a source power between about 1500 W and about 2000 W, and a bias power between about 1000 W and about 1500 W. In the illustrated example, the etching chamber has a volume between about 25 L and about 30 L, and the internal pressure of the etching chamber is between about 20 mTorr and about 40 mTorr. The third dry etching process of the illustrated example uses CHF 3 , CF 4 , and Ar as etching gases. In the illustrated example, the CHF 3  gas is supplied at a rate between about 20 sccm and about 30 sccm, the CF 4  gas is supplied at a rate between about 10 sccm and about 200 sccm, and the Ar gas is supplied at a rate between about 200 sccm and about 300 sccm. The etching selectivity of the capping layer to the insulating layers is preferably less than 1 to 0.7. The inclined plane of each of the illustrated terraces  27 , which are formed by the third dry etching process, is preferably at an angle between about 60° and about 70° from the contact surface between the trench  26  and the via hole  25 .  
         [0019]     From the foregoing, persons of ordinary skill in the art will appreciate that the above-described methods of forming a copper interconnect of a semiconductor device prevent void formation in the copper interconnect by etching insulating layers without using an etch-stop layer, thereby improving the electrical characteristics of the copper interconnect. Moreover, the described methods form terraces in the upper part of a via hole by removing the right-angled edges of the via hole, thereby enhancing the reliability of a dual damascene copper interconnection.  
         [0020]     It is noted that this patent claims priority from Korean Patent Application Serial Number 10-2003-0101322, which was filed on Dec. 31, 2003, and is hereby incorporated by reference in its entirety.  
         [0021]     Although certain example methods, apparatus and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.