Abstract:
To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born.

Description:
CLAIM OF PRIORITY 
       [0001]    This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 61/086,267 filed Aug. 5, 2008. 
     
    
     TECHNICAL FIELD OF THE INVENTION 
       [0002]    The technical field of this invention is clock signal generation on integrated circuits. 
       BACKGROUND OF THE INVENTION 
       [0003]    In most modern electronic devices activities inside the integrated circuits are coordinated by on-chip clock signals of various frequencies. This is especially true for large System-on-Chip (SoC) integrated circuits where large numbers of functions are integrated inside a single chip and each function has its unique clock frequency requirement. The on-chip frequencies are usually generated by Phase Lock Loop (PLL). The PLLs is the heart of the integrated circuit controlling all operations. PLLs have known disadvantages. The frequencies synthesisable by PLLs are limited. PLLs have high design complexity including heavy analog content. PLLs have response speed that is not instantaneous. 
         [0004]    Flying-Adder architecture is a novel technique for generating clock signals on an integrated circuit. This architecture can solve many difficult problems in various commercial projects. The character of this architecture can be summarized as a circuit level enabler which enables system level innovations. 
         [0005]    The information is collected through the sensors which converts the real world physical phenomena generally into voltage or current. An analog-to-digital converter (ADC) is employed to transfer the information into digital format for processing. After processing, the signal is converted back to voltage or current via a digital-to-analog converter (DAC) to control the real world activities. In this approach, the magnitude of the signal in voltage or current is the information. ADC and DAC are used to quantify the information. Many real world phenomena are more naturally suitable for rate of switching representation. Using this representation requires a frequency-to-digital converter (FDC) and a digital-to-frequency converter (DFC). A FDC is easily constructed using known techniques. This invention provides a circuit level enabler for a DFC. 
       SUMMARY OF THE INVENTION 
       [0006]    To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0008]      FIG. 1  illustrates a generic waveform of clock signal typically used in electronic devices; 
           [0009]      FIG. 2  illustrates the clock generation circuit of this invention; 
           [0010]      FIG. 3  illustrates the flying-adder frequency synthesizer illustrated in  FIG. 2 ; 
           [0011]      FIG. 4  illustrates an example of the clock signal produced by the flying-adder frequency synthesizer of  FIG. 3 ; 
           [0012]      FIG. 5  illustrates modulation of the input control word FREQ according to this invention; 
           [0013]      FIG. 6  is an example of a random number modulation function; 
           [0014]      FIG. 7  is an example of a saw tooth wave modulation function; 
           [0015]      FIG. 8  is an example of a triangle wave modulation function; 
           [0016]      FIG. 9  illustrates a comparison of circuits used in magnitude signal representation and circuits used in rate-of-switching signal representation; 
           [0017]      FIG. 10  illustrates a comparison of magnitude signal representation and in rate-of-switching signal representation; and 
           [0018]      FIG. 11  illustrates a system using rate-of-signal representation depicting the significance of the digital-to-frequency converter as a circuit-level enabler. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0019]      FIG. 1  illustrates a generic waveform of clock signal  100  typically used in electronic devices. The waveform of the clock signal has a defined pattern which repeats itself indefinitely. This defined pattern has two, and only two, distinguishable voltage levels. This first voltage level is regarded as high and the second voltage level is regarded as low. The defined pattern has one rising edge  101  which is an intermediate state when the signal transits from its low voltage level to high voltage level. The defined pattern also has one falling edge  102  that is the intermediate state when the signal transits from high to low level. 
         [0020]    Within a given time interval, such as one second, the number of times that the defined pattern repeats is defined as the frequency of this clock signal f. The time required to complete one such defined pattern is the period  110  of this clock signal T. By definition T=1/f. 
         [0021]    The rising edge  101  and the falling edge  102  are often called events. Their occurrences indicate something has happened within the electronic system. In most of modern electronic systems of the type known as synchronous systems, all internal activities are coordinated by these clock events, either rising edge  101 , falling edge  102  or both. The clock signals  100  are usually generated by on-chip component called PLL. This PLL produces other frequencies from a reference frequency. Generation of clock signal  100  is referred as frequency synthesis. 
         [0022]    A key requirement of clock generation, implied by the above definition, is that all the active patterns (called cycles) must have same period T. In VLSI circuit design practice, this feature can ease the chip implementation task greatly. However, this requirement also makes the clock generation circuitry (PLL) one of the most difficult components to design and built. 
         [0023]    As mentioned above, the requirement of all the clock cycles  100  must have the same period T has made clock circuitry design difficult. If this requirement could be removed, it can lead to a completely new direction. This invention uses the concept of time-average-frequency. The waveform of the clock signal is composed of infinite number of cycles. This first voltage level is regarded as high and the second voltage level is regarded as low. The defined pattern has one rising edge  101  and one falling edge  102 . Within a given time interval, such as one second, the number of cycles is the time-average-frequency of this clock signal f. Between any two adjacent rising edges  101  or falling edges  102 , the time is defined as the instant period T. The magnitude of the instant period T of each cycle is either controllable or known by the designer. 
         [0024]    This definition does not require repeatability. Thus every cycle need not have the same period. However, both definitions define the frequency of the clock signal. In traditional clock definition, the frequency is the number of repeatable pattern within one second. In the alternative definition, the frequency is the number of cycles within one second. Structurally, each cycle contains one rising edge  101  and one falling edge  102 . When used as a trigger signal within an electronic system, they both achieve the same end result of coordinating the activities inside the chip. 
         [0025]    On comparing the two clock signal definitions, clock signal having a repeatable pattern is ideal for driving an electronic system. This is due to the fact that every rising edge  101  and falling edge  102  is predictable. This can greatly simplify chip implementation. On the other hand, cycle of time-average-frequency is less effective when used as the driver of electronic system since it lacks the predictability. If constructed carefully with controlled predictability, the alternative cycle can be safely used in electronic systems. 
         [0026]    When clock signal is used in electronic systems, its frequency controls the number of operations carried out within the time interval of one second. As long as the specified number of operations per second is guaranteed, the electronic system cannot tell the difference between frequency and time-average-frequency. 
         [0027]      FIG. 2  illustrates the clock generation circuit of this invention. This clock generation circuit includes PLL  210 . PLL  210  includes phase detector (PFD)  211 , charge pump (CP)  212 , filter  213 , voltage controlled oscillator (VCO)  214  and divider  215  which divides by N. Divider  215  adjusts the frequency relationship between an input reference frequency f r  and the output frequency f o  of VCO  214 . Input reference frequency f r  is generally determined by a piezoelectric crystal frequency oscillator. PFD  211  compares the phases of input reference frequency f r  and the /N signal from divider  215  and produces an error signal. CP  212  and filter  213  generate a control signal for VCO  214  from the phase error signal output from PFD  211 . Feedback of an output signal from VCO  215  enables phase locked loop  210  to reliably generate an output signal having a stable frequency relationship to the input reference frequency f r . 
         [0028]    As better illustrated in  FIG. 3 , VCO  215  generates a plurality of signals L preferably equally spaced in phase. It is typical to generate these signals L using a chain of delays. Flying-adder synthesizer  220  receives the plural signals L and a digital control word FREQ. Flying-adder synthesizer  220  generates an output signal fs that depends both upon the frequency of plural signals L and the value of digital control word FREQ. This output signal fs supplies the clock driven process of the electronic circuit. 
         [0029]      FIG. 3  illustrates an example flying-adder synthesized such as used in this invention. Piezoelectric crystal  301  provides a stable frequency standard for VCO/PLL  210  illustrated in  FIG. 3 .  FIG. 3  illustrates VCO/PLL  210  producing N equally spaced output signals having a phase spacing of Δ. These N equally spaces output signals correspond to plural signals L illustrated in  FIG. 3 . 
         [0030]    These equally spaced output signals supply respective inputs of N to 1 multiplexer  321 . The selection made by N to 1 multiplexer  321  is controlled by integer part  322   a  of register  322 . The selected output of N to 1 multiplexer  321  supplies the clock input of flip-flop  324 . Each positive going edge of this output toggles flip-flop  324  to an opposite digital output producing a square wave signal CLKOUT having a controlled frequency. Inverter  325  is coupled to flip-flop  324  to retain its state between clock pulses. 
         [0031]    Accumulator  323  adds the current contents of register  322  including an integer part stored in integer part register  322   a  and a fractional part stored in fractional part register  322   b  to the digital control word FREQ. If the sum overflows, the most significant bit is discarded. The sum produced by accumulator  323  is stored in register  322  at a time controlled by CLKOUT from flip-flop  324 . Each time the sum is loaded into register  322  the number stored in integer part  322   a  selects an input to N to 1 multiplexer  321 . The repeated selection of inputs to N to 1 multiplexer  321  and flip-flop  324  produce the desired clock signal CLKOUT. 
         [0032]    The flying-adder synthesizer operates as follows. Suppose the digital value FREQ equals N, the number of inputs to N to 1 multiplexer  321 . Then every addition within accumulator  323  will over flow to the same integral part. Thus the same input to N to 1 multiplexer  321  will be selected repeatedly. According the frequency of CLKOUT will equal the input frequency from VCO/PLL  210  with a phase dependent upon the initial condition of register  322 . If the digital control word FREQ is larger than N, the input selected will tend to move within N to 1 multiplexer  321  selecting a phase with a longer delay each cycle. This produces a longer pulse period and hence a lower frequency. If the digital control word FREQ is smaller than N, the input selected will tend to move within N to 1 multiplexer  321  selecting a phase with a shorter delay each cycle. This produces a shorter pulse period and hence a higher frequency. The fractional part of FREQ provides additional resolution. Assuming the value of FREQ is constant, continual addition of the fractional causes periodic over flow into the integer part. This causes the input of N to 1 multiplexer  321  to dither between two adjacent intervals as illustrated in  FIG. 4 . As shown in  FIG. 4 , the clock generation circuit produces pulses  401  having a period T A  for cycles where the factional part addition does not overflow into the integral part. The clock generation circuit produces pulses  402  having a period T B  for cycles where the factional part addition overflows into the integral part. The rate of selection of the two adjacent intervals corresponds to the magnitude of the fractional part. A small fractional part near 0 will most often select the smaller interval  401  and select the larger interval  402  infrequently. A large fractional part near 1 will select the larger interval  402  more often than selecting the smaller interval  401 . A change in the digital value of control word FREQ will be immediately reflected in the next input of N to 1 multiplexer  321 . Thus there is no delay in changing frequencies. 
         [0033]    Since one type-B cycle occurs once in each time-window of T m , T m =1/f m =2π/ω m  can also be viewed as modulation frequency if this problem is treated as a carrier frequency being modulated by a modulation frequency. In other words, type-B (or type-A) cycle modulates the synthesizer&#39;s output signal at the rate of f m . In some applications the spurious signals can cause concerns on system operation. In most of those cases, converting spurs to noise can clear the application issue. This invention performs this task using the Flying-Adder architecture. This invention adds modulation into the fraction part of the frequency control word FREQ. 
         [0034]      FIG. 5  illustrates this aspect of the invention. An input control word FREQ includes integral part I and fractional part r. Modulation function  331  generates a time varying modulation function. This time varying modulation function is updated at the rate of an updating clock uclk. Adder  332  adds the input control word FREQ and the output of modulation function  331 . This produces a dithered control word input to flying-adder frequency synthesizer  320  as illustrated in  FIG. 3 . The modulation function could be a random number, a saw tooth function or a triangular function. 
         [0035]    The random number technique generates a random number between [-r, r] and adds it to FREQ at a predetermined clock rate uclk.  FIG. 6  is an example of random numbers generated by a random number generator for r=0.1. The random numbers have been added to the FREQ at the rate of uclk=f out /2. Other uclk rates are feasible and provide similar results. 
         [0036]      FIG. 7  is the saw tooth function that may be applied to FREQ. There are three tunable variables for this saw tooth function. These are: the update clock rate uclk; the step size of the saw tooth function; and the full size (height) of the saw tooth function. The saw tooth function may be realized by a k-bit counter. The step size is r/(2 k −1). 
         [0037]      FIG. 8  is triangular wave that may be applied to FREQ. Triangular waves have tunable variables similar to saw tooth waves. 
         [0038]    In all the three modulation methods, the DC component of the modulation function should be zero to not alter the average frequency. Further, the clock waveform still only contains two types of cycles: type-A of I*Δ and type-B of (I+1)*Δ such that it behaves the same as the un-modulated signal when driving digital circuit. However, the pattern of type-B cycle occurrences changes. Without modulation, type-B cycles will occur regularly as the result of addition which happens at the regular rate. With random numbers added, these events are randomized. 
         [0039]    For the cases of a saw tooth wave and a triangular-wave, the original pattern of type-B cycle occurrence is also altered in a controlled way. There are three control variables: the full size of the counter for the modulation function which does not have to be the fractional part r; the step size; and the update rate. 
         [0040]    Another benefit of these methods (random, saw tooth, and triangular) in real circuit design practices is that they can help to cure some problems caused by unknown problems. For example, if the end system is found to bear some unwanted spurs whose cause is unknown reasons (such as layout mismatch inside the chip, interference from neighbors or board issue), a controlled noise can be added on FREQ to convert the spurs to noise. No costly hardware modification is needed; it only requires software adjustment to turn it on. 
         [0041]    Spread spectrum is a very important subject in modern electronic system design. The key issue in this problem is to spread the highly concentrated clock energy to a slightly boarder range so that the electromagnetic interference between the electronic devices can be reduced. This issue is important because our life is filled with more and more electronic devices (cell phone, iPod, TV, computer and etc). This issue is difficult because the goal of spreading clock energy directly conflicts with the repeatability required in clock definition. As a result, large amount of research and design work has been carried out in this area to cope with this hard problem. Prior art techniques either modulate the VCO or dither the divider to alter the output frequency. This process is a mainly analog process and is very difficult to work because the VCO is one of the most complicated analog components. Thus the prior art spread spectrum techniques have two main drawbacks difficult construction and inaccurate result. 
         [0042]    The modulate control word technique illustrated in  FIG. 5  is readily adaptable for the spread spectrum application. Using a time-average-frequency can ease the clock generation (frequency synthesis) task. This invention naturally spreads the clock energy. Flying-Adder architecture is the tool which turns this theoretically superior idea into reality. Using Flying-Adder architecture in a spread spectrum clock simplifies the implementation and provides much better performance. Key parameters in constructing a spread spectrum clock include modulation depth (percentage) and modulation method (down spread, center spread, etc). Unlike conventional approaches, these parameters can all be precisely controlled through modulation magnitude, modulation rate of Flying-Adder modulator since they are digital values. And more importantly these digital values influence on the output frequency is linear in the case of Flying-Adder architecture. Moreover, the VCO is always used in fixed state. This permits a significant reduction in the design complexity. Furthermore, when Flying-Adder spread spectrum modulator is used, the resulting clock signal only has two types of cycle: type-A and type-B. Its impact on the driven digital circuitry is known and easily controlled. In other words, this is the controlled noise. The traditional approaches of adding noise is generally uncontrollable in construction and unpredictable in application. Spread spectrum function can by employed using the above described techniques using a larger modulation magnitude. 
         [0043]    The Flying-Adder spread spectrum clock generator is so powerful that even a software version can be workable. That is, the digital modulation pattern can be applied by on-chip processor through software changes to control word FREQ. Technically, the modulation pattern can be applied by interrupts to CPU. 
         [0044]    The Flying-Adder architecture and the time-average-frequency are support a Digital-to-Frequency Converter (DFC).  FIG. 9  illustrates the importance of the DFC.  FIG. 9(   a ) illustrates an analog-to-digital converter (ADC) which receives an analog input signal and produces a corresponding digital output signal.  FIG. 9(   b ) illustrates a digital-to-analog converted (DAC) which receives digital value input and produces a corresponding analog output signal.  FIGS. 9(   c ) and  9 ( d ) illustrate similar circuits with frequency or rate or switching.  FIG. 9(   c ) illustrates a frequency-to-digital converter which receives a frequency input signal and produces a corresponding digital output.  FIG. 9(   d ) illustrates a digital-to-frequency converter which receives a digital value input and produces an output signal having a corresponding frequency. The difference between the ADC/DAC pair and the FDC/DFC pair is in the corresponding real world signal. One is analog voltage while the other is frequency. The FDC illustrated in  FIG. 9(   c ) is a mature component. A FDC can be realized using a counter or Time-to-Digital Converter. This parallelism between ADC/DAC and FDC/DFC opens up the door to a new arena for information processing, which can possibly create a new generation of engineering miracles in electronic designs. 
         [0045]    Most electronic systems are designed to process information. The information is first collected through the sensors which convert the information associated with real world physical phenomena into voltage or current. Then, ADC is employed to transfer the information into digital format for processing. After processing, the signal is converted back to voltage or current by a DAC to control the real world activities. 
         [0046]      FIG. 10(   a ) illustrates this technique. In  FIG. 10(   a ) the magnitude of the signal in voltage or current represents the information. ADC and DAC are the tools used to quantify this information enabling digital data processing and control or real systems. Some real world phenomena are naturally more suitable for representation in frequency or rate-of-switching of voltage or current. In the later case, the real world information is quantified in rate-of-switching rather than magnitude as illustrated in  FIG. 10(   b ). In such cases the rate of zero-crossing in the information. In such cases, more efficient system could be built by using the DFC/FDC technique. This avoids any need for sophisticated analog components used for signal amplification, conditioning and processing. 
         [0047]    The DFC is a circuit-level enabler for this system-level innovation. It can be utilized in two ways to help building better electronic systems. This first way is for it to be used as the clock circuitry (PLL), which is the driver of the information processing chips. The other way is to use the DFC to represent the information itself. For certain applications, this new approach could result in more efficient implementation.  FIG. 11  depicts the significance of the DFC as a circuit-level enabler. The new system includes FDC  1101  constructed according to known technique converting a rate-of-switching input f in  into a digital value. Digital signal processor (DSP)  1102  performs data processing operations on the input digital value and produces an output digital value. DFC  1103 , constructed as described herein, converts this digital value into a rate-of-switching output f out . 
         [0048]    Utilizing the Flying-Adder&#39;s instantaneous response speed, Smart-DSP, Self-Adjust DSP (SA-DSP) or Power-Aware DSP (PA-DSP) can be created. Based on the load, DSP  1102  can adjust its operating speed (frequency) dynamically, resulting in minimum power usage. This is the so-called Dynamic Frequency Scaling (DFS). This is doable since Flying-Adder PLL has instantaneous response speed. 
         [0049]    Unlike conventional PLL which does not have any flexibility, the Flying-Adder frequency synthesizer of this invention has superior programmability. It gives high degree of control to software programmers in the field. Involvement of software engineers generally produces innovations at the product level. Further, the software/application engineers in customer side can have the option to create their own, more differentiated, products.