Abstract:
A beamforming system including a multiplier stage for providing a plurality of steered signal terms, each term being a product of an input signal term and a steering signal term. A filter multiplies the steered signal terms by a plurality of respective filter weights to provide a plurality of weighted products. The weighted products are summed to provide an output beam directionally responsive to the steering signal. A microprocessor provides the steering signal terms and the filter weights in response to the input signal and/or user input. In the preferred embodiment, the filter is a reconfigurable, general purpose matched filter configured to multiply a plurality of delayed representations of a respective one of the steered signal terms by a plurality of the weights to provide a plurality of intermediate weighted product terms. The filter further includes a summing circuit for accumulating the intermediate weighted product terms to provide a respective one of the plurality of weighted products. The inventive beamforming system cancels unwanted interference, while forming a beam to allow a desired signal to be received with a maximum signal-to-interference-plus-noise ratio (SINR). Through a data-capture RAM, the system allows interference samples to be collected and passed to a microprocessor to calculate the optimum filter weights. The received beam may be steered to any desired direction to form an optimal space-time adaptive matched filter.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to radar receivers. More specifically, the present invention relates to beamforming and interference cancellation systems used in high performance digital radar receivers. 
     2. Description of the Related Art 
     Sophisticated high performance military and commercial digital radar receivers detect and process signals in complicated environments that include broadband clutter, interference sources (intentional and unintentional), echoes, and receiver noise. These receivers perform some or all of the following functions: synthesis of in-phase (I) and quadrature (Q) components from high-speed sampled signals, formation of video filters, notch DC components, decimation of data, provision of channel-to-channel equalization, digital range correlation, beam steering and interference cancellation. 
     Currently, these tasks are performed by Hilbert filters, digital video filters, equalization filters, discrete Fourier transform filters, decimating filters, convolvers, correlators, and general purpose cascadable FIR filters implemented in commercial off-the-shelf hardware (COTS) and customized hardware in embedded systems. 
     Unfortunately, digital radar receivers implemented in accordance with conventional teachings often require several hundred signal processing chips. As a result, conventional digital radar receivers are typically heavy, bulky, and expensive to develop and manufacture. In addition, these receivers typically consume considerable power and generate much heat. 
     Hence, there was a need in the art for a unique receiver architecture that would be highly flexible, scalable, and reconfigurable that could perform the numerous functions mentioned above. The need in the art was addressed by copending application entitled GENERAL PURPOSE FILTER, filed Jun. 14, 2000, by L. C. Cox et al. (Atty. Docket No. PD R98027-1), the teachings of which are incorporated by reference. This application disclosed and claimed a signal processor design including a plurality of filters which were selectively interconnected to provide a variety of digital signal processing functions. In the illustrative embodiment, each filter was adapted to multiply input data by a coefficient. Specifically, each filter was adapted to multiply input data by coefficients to form digital products which were combined to accumulate the sum of the products. The coefficients are provided by a microprocessor and configure the logic to a particular function, such as a general purpose filter, a Hilbert filter, a finite impulse response filter, an equalizer, a convolver, a correlator, or an application specific integrated circuit by way of example. When interconnected in accordance with the teachings provided therein, these circuits may be used to provide a digital receiver. 
     The digital receiver would comprise a plurality of general purpose filters constructed in accordance with the referenced teachings. Each filter would have a plurality of filter banks, switching circuitry to interconnect the filter banks, and programmability provided by an external processor. The processor would configure the filter banks, to provide a delay element, a first decimating filter and a first equalizer in a first channel of a first general purpose filter and a Hilbert transform, a second decimating filter and a second equalizer in a second channel of the first general purpose filter. A first range correlator would be provided in a first channel of a second general purpose filter and a second range correlator would be provided in a second channel of a second general purpose filter. The first channel of the first general purpose filter would be connected to the first channel of the second general purpose filter and the second channel of the first general purpose filter would be connected to the second channel of the second general purpose filter. 
     An external processor would program the general purpose filter to configure the filter banks to simultaneously provide the functions found in most digital receivers (e.g., Hilbert transforms, video filters, equalizers, range correlation, and general purpose video filters). 
     The versatile, flexible and reusable features of the general purpose filter architecture allows analog and digital receivers to be built using a single chip type. Accordingly, the receivers would be much smaller and lighter in weight then conventional systems and have lower associated power dissipation, thermal heating, and development and manufacturing cost. 
     While the teachings of the referenced patent application substantially addressed the need in the art, a need remains for a system and technique for implementing beamforming and interference cancellation in a digital radar receiver using a general purpose filter architecture. 
     SUMMARY OF THE INVENTION 
     The need in the art is addressed by the beamforming system of the present invention. In a most general sense, the inventive beamforming system includes a multiplier stage for providing a plurality of steered signal terms, each term being a product of an input signal term and a steering signal term. A filter is provided for multiplying the steered signal terms by a plurality of respective filter weights to provide a plurality of weighted products. The weighted products are summed to provide an outer beam directionally responsive to the steering signal. A microprocessor provides the steering signal terms and the filter weights in response to the input signal and/or user input. 
     In a specific implementation, the multiplier stage includes a plurality of multipliers. Each multiplier being configured to multiply one of the input signal terms with a respective one of the steering signal terms to provide a respective one of the steered signal terms. In the preferred embodiment, the filter is a reconfigurable, general purpose matched filter configured to multiply a plurality of delayed representations of a respective one of the steered signal terms by a plurality of the weights to provide a plurality of intermediate weighted product terms. The filter further includes a summing circuit for accumulating the intermediate weighted product terms to provide a respective one of the plurality of weighted products. 
     In the illustrative embodiment, the filter includes the first plurality of multipliers and a plurality of channels, one for each quadrant of the associated antenna. Each channel includes a plurality of multipliers and delay elements configured to provide the intermediate weighted product terms. 
     The inventive beamforming system cancels unwanted interference, while forming a beam to allow a desired signal to be received with a maximum signal-to-interference-plus-noise ratio (SINR). Through a data-capture RAM, the system allows interference samples to be collected and passed to a microprocessor to calculate the optimum filter weights. The received beam may be steered to any desired direction to form an optimal space-time adaptive matched filter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the general purpose filter of the present invention along with associated control circuitry. 
     FIG. 2 is a schematic diagram of a portion of the general purpose filter of FIG. 1; 
     FIG. 3 is a block diagram of the FIR filter utilized in the general purpose filter of the present invention. 
     FIG. 4 is a block diagram of an FIR filter sub-module utilized in the general purpose filter of the present invention. 
     FIG. 5 is a block diagram of an individual FIR filter cell utilized in the general purpose filter of the present invention. 
     FIG. 6 is an illustrative functional timing for a microprocessor read operation from the general purpose filter of the present invention. 
     FIG. 7 is an illustrative functional timing for a microprocessor write operation to the general purpose filter of the present invention. 
     FIG. 8 is an illustrative functional timing diagram for the Hilbert Transform Mode of the general purpose filter of the present invention. 
     FIG. 9 is a block diagram of a digital receiver incorporating the beamforming system of the present invention. 
     FIG. 10 is a block diagram of the beamforming system of the present invention in greater detail. 
     FIG. 11 is a graph of the output of the beamforming system of FIG.  10 . 
    
    
     DESCRIPTION OF THE INVENTION 
     Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantages teachings of the present invention. 
     While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility. 
     FIG. 1 is a block diagram of a general purpose filter constructed in accordance with the teachings of the above-referenced and incorporated application filed by Cox et al. along all associated control circuitry. The system  10  consists of the general purpose filter  20 , a microprocessor  50 , a user interface  60 , a coefficient memory  70 , an interface and control circuit  80 , and a data collection memory  90 . The filter  20  includes first, second and third combiners  22 ,  32  and  42  which allow the microprocessor  50  to selectively interconnect a plurality of 16 tap finite impulse response (FIR) filters  24 - 30  and  34 - 40  (even numbers only) therebetween via a bus (not shown). Tap filters  24 - 30  provide a first filter bank. A between the first and second combines  22  and  32 , respectively. Tap filters  34 - 42  provide a second filter bank B between the second and third combiners  32  and  42 , respectively. Note that the outputs of the first three filters in each bank are fed back to the inputs thereof. Those skilled in the art will recognize that the teachings of the present invention are not limited to FIR filter implementations. The present teachings may be implemented with infinite impulse response (IIR) filters as well. 
     A user selects a function to be implemented via a user interface  60 . As discussed more fully below and in accordance with the present teachings, in response to the user input, the microprocessor  50  selectively interconnects the tap filters via the combiners as necessary to implement the desired function. Much of the signal processing required to implement digital radar receivers can be implemented with a plurality of digital filters properly weighted. Accordingly, in the present invention, the filters are interconnected and provided with tap weight coefficients by the microprocessor as necessary for the desired functionality. The coefficients are provided by a coefficient memory  70 . In the illustrative embodiment, an interface and control circuit  80  provides timing and control. 
     FIG. 2 is a schematic diagram of a portion of the general purpose filter of FIG.  1 . In the illustrative embodiment, the system  10  is implemented as a general purpose digital filter (GPF) chip with 128 multiply-add filter cells fabricated in 0.35 micron CMOS technology. Using current technology and the present teachings, the chip  10  may be designed by one of ordinary skill in the art, to operate at rates up to 60 MHz with an asynchronous master reset. In the preferred embodiment, the chip  10  has two 16 bit input channels, two 32 bit output channels, a chip enable and a microprocessor interface. 
     In the illustrative embodiment, two input ports I and Q allow 128 filter cells to be shared between two data paths. This allows the input data to processed as two separate pieces of data or as complex data. Each path may be configured as a 16 tap arbitrary phase filter, a 32 tap filter or a 128 tap single channel filter. As discussed below, coefficient double buffering and clock synchronization logic permit the user to switch between coefficient sets without causing any undesirable effects in the filter&#39;s operation. 
     A microprocessor compatible bus  80 , (consisting of a 16 input address bus, a 16-bit bi-directional data bus, a read/write bit, and a control select), is connected to each element in the system  10  and provides read/write access to programmable internal registers therein. As discussed below, these internal registers are double buffered (see FIG. 5) to allow the chip to switch to new settings upon receipt of an external sync pulse. Consequently, a one clock update cycle is required to update the new settings. 
     The system  10  is partitioned into 8 functional blocks: a Random Number Generator (RNG)  44 , a Data Selector &amp; Interface (DSI)  46 , a Saturation &amp; Peak Detector (SPD),  48 , a DC Offset Compensation (DOC)  49 , a Finite Impulse Response filter (FIR)  50 , a Data Decimator &amp; Interface (DCI)  52 , a Timing &amp; Control Interface (TCI)  80 , and a Data Capture Memory (DCM)  90 . Each of these elements is of conventional design. 
     Banks of registers  54  and  56  are disposed along the data path in order to insure proper alignment of input data, sum data and data enable signals. In addition, the General Purpose Filter Chips may be “chained” together to create a larger multi-tap FIR without requiring additional external buffering. 
     The RNG  44  is a programmable pseudo-random number generator that allows for a known sequence of numbers to be inserted into the front-end of the data path for self-test purposes. The data sequence for each of the channels is based on the mode and seed values programmed into the number generator. The RNG  44  allows for 12, 14 or 16 bit operation and the data output can either be a constant value, a pseudo random pattern, DCM data or input data. 
     The DSI  46  is a programmable module that provides data selection and decimation. It provides odd/even data samples and has independent decimation rates for the data path channels and the DCM  90 . 
     The SPD  48  is a general purpose, dual channel, programmable saturation and peak detector. Separate saturation counters, saturation flags, threshold values and peak value data registers are provided for each channel. A saturation occurs when the absolute value of said channel data is greater than that channel&#39;s programmed threshold value. The peak data, over the specified sample period, is determined by identifying the maximum squared value of non-saturated channel data. When a channel&#39;s peak value is identified, data for both channels is stored in memory. 
     The DOC  49  allows for a DC offset value to be calculated over a specified number of samples and then, if enabled, have the offset term removed from the input data stream. In the illustrative embodiment, valid data sample sizes for DC offset calculations are powers of 2, ranging from 2 to 256. 
     FIG. 3 is a block diagram of the FIR filter  50 . As illustrated in FIG. 3, the FIR  50  includes the following 3 sub-modules: FIRA  100 , DCF  200 , and FIRB  300 . FIRA and FIRB are identical FIR sub-modules. It is important to note that data from the I/O is pipelined prior to the FIRB block. This is necessary to maintain data alignment along the data path. 
     FIG. 4 is a block diagram of an FIR sub-modules  100 . Each FIR sub-module  100  is a programmable transposed canonical FIR filter. The sub-module can be configured as a two channel, 16 tap delay Hilbert Transform filter followed by a 16 tap filter, a 32 tap FIR filter, a 64 tap single channel FIR filter, or a 2 channel, 16 tap cross-coupled FIR filter. There is a rounding option between the two filters. The type of FIR filter (i.e. low pass, band pass, high pass) is determined by the coefficient values. The programmable coefficients are double buffered to allow the user to switch between coefficients without affecting the filter&#39;s operation. 
     FIG. 5 is a block diagram of an individual 16-tap FIR filter cell  24 . It should be noted that FIG. 5 shows only 2 of the filter&#39;s 16 taps. The first tap  140  includes a multiplexer  142  having an output connected to the input of a buffer register  144 . The input to the multiplexer is a coefficient supplied by the microprocessor  50  of FIG.  1 . The output of a buffer register  144  is connected to an operational register  148 . As mentioned above, the double buffering arrangement allows the chip to switch to new settings upon receipt of an external sync pulse. Consequently, a single clock update cycle is required to update the new settings. The output of the operational register  148  is supplied to a multiplier  152  which provides a product of the coefficient input to the buffer register  144  and input data to a summer  154  where it is added to any accumulated sum from previous taps and/or filters. The output of the summer  154  is input to a third register  158  from which it is selectively supplied to a second summer  160  under control of the timing circuit  80 . The second summer adds the sum of the product provided by the second tap  150 . The second tap  150  is identical to the first tap  140 . The output of the second summer  160  is stored in the third register  174  for output. 
     Returning to FIG. 3, the DCF is a decimator and control for finite impulse response filters. In addition to allowing for data decimation to occur between FIRA and FIRB, the DCF provides decimated FIRA data to the DCM. The decimation rate is programmable and allows for separate rates to be specified for FIRB and the DCM. 
     Returning to FIG. 2, the DCI  52  is a programmable, dual channel, data decimator that serves as an interface for the FIR  50  to the DCM  90  and external I/O. In non-bypass mode, the input data can be decimated, and presented to the output channel. The decimation rate for data output is independent of the decimation rate for RAM data. In the bypass mode, the data is not decimated and appears at the outputs unmodified. In this mode, the lower 16 bits are set to zero. There is a rounding option available at the data output stage. 
     The DCM  90  is a programmable memory module that allows input or output data from both channels to be captured. There are three points along the data path where data can be captured. The DSI  46 , DCF  200  and DCI  52  all provide the DCM  90  with data. In the illustrative embodiment, the DCM&#39;s memory is configured as two 512×16 RAMs and has a maximum input data rate of 30 MHz. These samples can be read by the microprocessor  50  (FIG.  1 ). Data can be externally or internally triggered with or without a delay from the trigger to the time data is captured. 
     The TCI  80  handles the general timing, control, and interface requirements for the GPF. The 4 major functions of the TCI are a microprocessor interface, data path control, AGC timing control and equalization timing control. In addition to each module&#39;s enable and data strobe signals, the TCI allows information to be sent over the microprocessor compatible bus. The bus has a 16-bit data I/O port, a 16 bit address port, a read/write bit, and a control select strobe. The control registers, coefficient registers, and DCM RAM are memory mapped into the 16 bit address space. 
     On chip diagnostic circuits are provided to simplify system debug and maintenance. The GPF has IEEE 1149.1 compliant boundary scan for bound level test, scan for internal fault isolation, and Built-In Self Test (BIST) for internal memory verification. The boundary scan interface allows shifting of test data to and from the chips on a board for testing the integrity of the I/O. Scan circuitry provides access and visibility to internal registers, allowing for easy testing of combinatorial logic and checking register integrity. BIST verifies internal memory by writing and reading various patterns. 
     Signal Description and Memory Map 
     In the illustrative embodiment, the address bus is 16 bits wide and is partitioned as follows: the 4 MSBs make up the base address which identifies a particular GPF functional block, 1 bit is for growth and the 10 LSBs are for local addressing. An illustrative description of the input and output signals is shown in Table 1. (Note: The signal description provided in Table 1 is copyrighted by the present assignee and provided for the purpose of illustration only. A copying or creation of a derivative work from the signal description in Table 1 without the prior express written permission of the present assignee is expressly published under U.S. and International Copyright Laws.) 
     An illustrative memory map is shown in Table 2. (Note: The memory map provided in Table 2 is copyrighted by the present assignee and provided for the purpose of illustration only. A copying or creation of a derivative work from the memory map in Table 2 without the prior express written permission of the present assignee is expressly prohibited under U.S. and International Copyright Laws.) 
     Functional Timing 
     Illustrative functional timing for a microprocessor read operation from the GPF is shown in FIG.  6 . The enable signal ceIn indicates the beginning of a processor read/write cycle. After the address bus addressIn and wrLowIn are decoded, data from the memory location is put onto the data bus dataBi during the period when ceIn is active. 
     Illustrative functional timing for a microprocessor write operation to the GPF is shown in FIG.  7 . The enable signal ceIn indicates the beginning of a processor read/write cycle. After the address bus addressIn and wrLowIn are decoded, the location is written to on the rising edge of clockIn during the period when dsIn is active. 
     Illustrative functional timing for the Hilbert Transform Mode is shown in FIG.  8 . 
     Beamforming and Interference Cancellation System 
     FIG. 9 is a block diagram of a digital receiver incorporating the beamforming system of the present invention. The receiver  400  includes an IF receiver section  500  and a beamforming system  600  implemented in accordance with the teachings of the present invention. The IF receiver  500  includes a four quadrant phased array antenna  510 , which feeds a low noise amplifier  520 . The output of the amplifier  520  is fed to a first local oscillator  530 . The output of the local oscillator  530  is provided to a first band pass filter  540 . The output of the first band pass filter  540  is provided to a second local oscillator  550  which feeds a second band pass filter  560 . The output of the second band pass filter is input to a third local oscillator  570 . The output of the third local oscillator  570  is provided to a low pass filter  580 . The low pass filter  580  feeds an analog to digital (A/D) converter  590 . 
     The output of the A/D converter  590  is input to a multiplier stage  620  of a general purpose filter  610  constructed in accordance with the present teachings. The output of the A/D converter is also input to a data capture memory  630  of the filter  610 . In the best mode, the filter  610  is constructed in accordance with the teachings of copending application entitled GENERAL PURPOSE FILTER, filed Jun. 14, 2000 by Cox et al., (Atty. Docket No. PD R98027-1) the teachings of which are incorporated herein by reference. The data capture memory provides samples of a received and down-converted IF input signal having a direction vector U to a microprocessor  640 . In accordance with the present teachings, the microprocessor  640  calculates a steering vector u* and weights for a matched filter  650  to achieve beam steering and matched filtering as described more fully below. The outputs of the matched filter  650  are combined in a summing circuit  660  to yield a directional beam. 
     FIG. 10 is a block diagram of the beamforming system of the present invention in greater detail. In the best mode, the multiplier stage  620  is implemented within the filter  610  and includes four multipliers  622 - 628  (even numbers only) one for each quadrant of the four quadrant phased array antenna  510 . Each multiplier receives a digitized term of the received signal (having a direction vector ‘u’) of the form Se −j2πτn +noise, where S is the desired signal component, the sum of the terms e −j2πτn  where n=1 to 4 is the direction vector of S and τn is sample number ‘n’ where n is the channel number. Each multiplier also receives a digitized term of the steering vector U=u* from the microprocessor of the form e +j2πτn  where τn is sample number ‘n’ where n is the channel number. Those of ordinary skill in the art will appreciate that since: 
     
       
           u•u*= 1   [1] 
       
     
     then 
     
       
         (Se −j2πτn +noise)•e +j2πτn =S+noise•e +j2πτn    [2] 
       
     
     Hence, the multipliers  622 - 628  (even numbers only) output a steered signal which is corrected for direction. To reduce the noise component, the directionally corrected or ‘steered’ outputs of each of the four multipliers are input to an associated one of four identical channels  652 - 658  (even numbers only) of the matched filter  650 , respectively. Inasmuch as the channels are identical, only one will be described in detail herein. The first channel  652  of the matched filter  650  has a bank of multipliers  660 - 663  which receives a set of coefficients a 0  through a 3 , respectively, from the microprocessor  640 . The filter weights are given by equation [3] below: 
     
       
         Filter Weights=β(A H A) −1 U   [3] 
       
     
     where β is the filter gain scale factor, A is the sample matrix for the filter taps, H indicates matrix bermitian (conjugate transpose), and u is the steering vector. 
     In the illustrative embodiment, the coefficients are selected in accordance with the signal description and memory map of Table 1 and 2 provided herein. (Those skilled in the art will appreciate that the teachings of the present invention are not limited to the signal descriptions and memory allocations described herein. Other signal descriptions and memory allocations may be utilized without departing from the scope of the present teachings.) 
     Likewise, the multipliers of channels  654 ,  656  and  658  receive coefficients b 0  through b 3 , c 0  through d 3 , respectively, from the microprocessor  640 . The first multiplier  660  of each channel receives the steered output of the associated multiplier  622  from the multiplier stage  620 , multiplies it by the coefficient a 0  and provides an intermediate weighted product. Each subsequent multiplier  661 - 663  multiplies a coefficient a 1  through a 3 , respectively, provided by the microprocessor  640  with a delayed version of the steered output of the multiplier stage  622 . The second multiplier  661  receives the output from the multiplier  622  delayed by one clock cycle by a delay element  664 . The third multiplier  662  receives the output from the multiplier  622  delayed by two clock cycles by delay elements  664  and  665 . The fourth multiplier  663  receives the output from the multiplier  622  delayed by three clock cycles by delay element  664 ,  665  and  667 . 
     The intermediate weighted products terms output by the multipliers for each channel are combined by a digital summing element  668 , which, in turn, outputs a weighted product term for each channel. 
     The weighted product terms output by each channel of the matched filter  650  are combined by the summing circuit  670  to provide the desired output signal S=y(n) which is matched to reduce the noise component noise•e +j2πτn  of equation [2] above. 
     FIG. 11 is a graph of the output of the beamforming system of FIG.  10 . Those skilled in the art will appreciate that by changing the steering vector U, the mainlobe, sidelobes and nulls of the output signal depicted in FIG. 11 may be shifted right or left to avoid an interfering signal or send a null in the direction of same. 
     Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof. 
     It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention. 
     
       
         
               
             
               
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Signal I/O Description 
               
             
          
           
               
                 PIN NAME 
                 SIZE 
                 TYPE 
                 FUNCTION 
               
               
                   
               
             
          
           
               
                 ch1SumIn(31:0) 
                 32 
                 Input 
                 Input sum for channel 1 
               
               
                 ch2SumIn(31:0) 
                 32 
                 Input 
                 Input sum for channel 2 
               
               
                 chlDataIn(15:0) 
                 16 
                 Input 
                 Input data for channel 1 
               
               
                 ch2DataIn(15:0) 
                 16 
                 Input 
                 Input data for channel 2 
               
               
                 dataEnLowIn 
                 1 
                 Input 
                 ch1, ch2 data input rate strobe 
               
               
                   
                   
                   
                 (from DOC) 
               
               
                 ExtDataEnLowIn 
                 1 
                 Input 
                 ch1, ch2 data input rate strobe 
               
               
                   
                   
                   
                 (from I/O) 
               
               
                 outputEnLowIn 
                 1 
                 Input 
                 Chip output enable 
               
               
                 dmaEnLowIn 
                 1 
                 Input 
                 Enabtes the Data Capture 
               
               
                   
                   
                   
                 RAM Memory 
               
               
                 cpiLowIn 
                 1 
                 Input 
                 Coherent processing interval 
               
               
                   
                   
                   
                 input 
               
               
                 pdiLowIn 
                 1 
                 Input 
                 Pulse detection interval 
               
               
                 ceLowIn 
                 1 
                 Input 
                 Chip Enable 
               
               
                 spdEnLowIn 
                 1 
                 Input 
                 Disable Saturation &amp; Peak 
               
               
                   
                   
                   
                 Detection 
               
               
                 spdDumpLowIn 
                 1 
                 Input 
                 Dump data from Saturation &amp; 
               
               
                   
                   
                   
                 Peak Detection 
               
               
                 dcCompEnLowIn 
                 1 
                 Input 
                 Enable dc compensation 
               
               
                 dcCalcEnLowIn 
                 1 
                 Input 
                 Enable dc offset calculation 
               
               
                 gblAddressIn 
                 16 
                 Input 
                 Global address from external 
               
               
                   
                   
                   
                 processor 
               
               
                 gblWrLowIn 
                 1 
                 Input 
                 Global bus read/Write strobe 
               
               
                 gblOeLowIn 
                 1 
                 Input 
                 Global bus output enable 
               
               
                 gblDsLowIn 
                 1 
                 Input 
                 Global data strobe 
               
               
                 gblCeLowIn 
                 1 
                 Input 
                 Global chip select strobe 
               
               
                 resetLowIn 
                 1 
                 Input 
                 Power up reset for asic 
               
               
                 clockIn 
                 1 
                 Input 
                 60 MHz clock 
               
               
                 testEnIn 
                 1 
                 Input 
                 Test - LSI Logic required for 
               
               
                   
                   
                   
                 setting bi - directionals to in- 
               
               
                   
                   
                   
                 puts and tri - states off 
               
               
                 tdiIn 
                 1 
                 Input 
                 Test - boundary scan data 
               
               
                   
                   
                   
                 input 
               
               
                 tmsIn 
                 1 
                 Input 
                 Test - boundary scan mode 
               
               
                   
                   
                   
                 select 
               
               
                 tckIn 
                 1 
                 Input 
                 Test - boundary scan clock 
               
               
                 trstIn 
                 1 
                 Input 
                 Test - boundary scan asyn- 
               
               
                   
                   
                   
                 chronous reset 
               
               
                 bistModeIn 
                 2 
                 Input 
                 Test - enable the memory 
               
               
                   
                   
                   
                 BIST 
               
               
                 scanEnIn 
                 1 
                 Input 
                 Test - scan mode enable for 
               
               
                   
                   
                   
                 test 
               
               
                 scan1In 
                 1 
                 Input 
                 Test - scan input #1 
               
               
                 scan2In 
                 1 
                 Input 
                 Test - scan input #2 
               
               
                 scan3In 
                 1 
                 Input 
                 Test - scan input #3 
               
               
                 scan4In 
                 1 
                 Input 
                 Test - scan input #4 
               
               
                 procMonEnIn 
                 1 
                 Input 
                 Test - Enable the parametric 
               
               
                   
                   
                   
                 nand tree 
               
               
                 ch1SatLowOut 
                 1 
                 Output 
                 Output indicates saturation 
               
               
                 ch2SatLowOut 
                 1 
                 Output 
                 Output indicates saturation 
               
               
                 spdDumpOut 
                 16 
                 Output 
                 Saturation &amp; peak detection 
               
               
                   
                   
                   
                 module data dump 
               
               
                 spdDumpEnLowOut 
                 1 
                 Output 
                 Saturation &amp; peak detection 
               
               
                   
                   
                   
                 module data dump enable 
               
               
                 spdDumpDoneLowOut 
                 1 
                 Output 
                 Saturation &amp; Peak detection 
               
               
                   
                   
                   
                 module data dump done 
               
               
                 ch1DataOut(31:0) 
                 32 
                 Output 
                 Output sum data for channel 1 
               
               
                 ch2DataOut(31:0) 
                 32 
                 Output 
                 Output sum data for channel 2 
               
               
                 dataEnLowOut 
                 1 
                 Output 
                 Ch1 &amp; ch2 output data valid 
               
               
                 dataEnLowDlyOut 
                 1 
                 Output 
                 Ch1 &amp; ch2 output data valid 
               
               
                   
                   
                   
                 (program delay) 
               
               
                 dmaDataOut 
                 16 
                 Output 
                 Output capture of data 
               
               
                 dmaDavLowOut 
                 1 
                 Output 
                 Indicates each dma data 
               
               
                   
                   
                   
                 sample valid 
               
               
                 dmaRdyLowOut 
                 1 
                 Output 
                 Indicates dma capture mem- 
               
               
                   
                   
                   
                 ory full and ready to clock 
               
               
                   
                   
                   
                 data out 
               
               
                 dmaDoneLowOut 
                 1 
                 Output 
                 Indicates capture of data 
               
               
                   
                   
                   
                 complete 
               
               
                 calcDoneLowOut 
                 1 
                 Output 
                 Indicates DOC calculation 
               
               
                   
                   
                   
                 complete 
               
               
                 gblRdyLowout 
                 1 
                 Output 
                 Indicates end of read/write 
               
               
                   
                   
                   
                 cycle 
               
               
                 tdoOut 
                 1 
                 Output 
                 Test - boundary scan output 
               
               
                 scanlOut 
                 1 
                 Output 
                 Test - scan output #1 
               
               
                 scan2Out 
                 1 
                 Output 
                 Test - scan output #2 
               
               
                 scan3Out 
                 1 
                 Output 
                 Test - scan output #3 
               
               
                 scan4Out 
                 1 
                 Output 
                 Test - scan output #4 
               
               
                 bistDoneOut 
                 1 
                 Output 
                 Test - BIST output done when 
               
               
                   
                   
                   
                 high 
               
               
                 bistErrorOut 
                 1 
                 Output 
                 Test - BIST error occurs when 
               
               
                   
                   
                   
                 low 
               
               
                 procMonOut 
                 1 
                 Output 
                 Test - parametric nand tree 
               
               
                   
                   
                   
                 output 
               
               
                 tstDcmFsmQut 
                 5 
                 Output 
                 Test - DCM state machine 
               
               
                 tstDocCalcStateOut 
                 2 
                 Output 
                 Test - DOC DC offset com- 
               
               
                   
                   
                   
                 pensation state machine 
               
               
                 gblDataBi 
                 16 
                 Bidirect 
                 16 bit bi - directional global 
               
               
                   
                   
                   
                 data bus to external processor 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
               
               
             
               
               
               
               
               
               
               
               
             
               
               
               
             
               
               
               
               
               
               
               
               
             
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 Memory Map 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 15-12 bits 
                 11 bit 
                 10-0 bits 
               
               
                   
                 Base Address 
                 Growth 
                 Address Field 
               
             
          
           
               
                 Base Addr 
                 Offset Addr 
                 Item 
                 Module 
                 Access 
                 Data Size (bits) 
                 Initial Value 
                 Description 
               
               
                   
               
               
                 0000h 
                 0h 
                 LFSR modeB 
                 RNG 
                 R/W 
                  2 
                 0h 
                 Determines LFSR &amp; RNG mode 
               
               
                   
                   
                   
                   
                   
                   
                   
                 (Buffered) 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Tactical 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Data from DCM 
               
               
                   
                   
                   
                   
                   
                   
                   
                 2h =&gt; LFSR enabled to count 
               
               
                   
                   
                   
                   
                   
                   
                   
                 3h =&gt; LFSR outputs constant value (seed) 
               
               
                   
                 1h 
                 Seed 1B 
                 RNG 
                 R/W 
                 16 
                 0h 
                 Channel 1 LFSR seed (Buffered) 
               
               
                   
                 2h 
                 Seed 2B 
                 RNG 
                 R/W 
                 16 
                 0h 
                 Channel 2 LFSR seed (Buffered) 
               
               
                   
                 3h 
                 Data WidthB 
                 RNG 
                 R/W 
                  2 
                 2h 
                 Input Data Width (Buffered) 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; 12 bit input data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; 14 bit input data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 2h =&gt; 16 bit input data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 3h =&gt; 12 bit input data 
               
               
                   
                 4h 
                 LFSR mode 
                 RNG 
                 R 
                  2 
                 0h 
                 Determines LFSR &amp; RNG mode 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Tactical 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Data from DCM 
               
               
                   
                   
                   
                   
                   
                   
                   
                 2h =&gt; LFSR enabled to count 
               
               
                   
                   
                   
                   
                   
                   
                   
                 3h =&gt; LFSR outputs constant value (seed) 
               
               
                   
                 5h 
                 Seed 1 
                 RNG 
                 R 
                 16 
                 0h 
                 Channel 1 LFSR seed 
               
               
                   
                 6h 
                 Seed 2 
                 RNG 
                 R 
                 16 
                 0h 
                 Channel 2 LFSR seed 
               
               
                   
                 7h 
                 Data Width 
                 RNG 
                 R 
                  2 
                 2h 
                 Input Data Width 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; 12 bit input data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; 14 bit input data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 2h =&gt; 16 bit input data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 3h =&gt; 12 bit input data 
               
               
                 1000h 
                 0h 
                 Data Dec Rate Buf 
                 DSI 
                 R/W 
                 12 
                 1h 
                 Data path decimation rate out of DSI 
               
               
                   
                   
                   
                   
                   
                   
                   
                 block (Buffered) 
               
               
                   
                 1h 
                 RAM Dec Rate Buf 
                 DSI 
                 R/W 
                 12 
                 1h 
                 DCM data decimation rate out of DSI 
               
               
                   
                   
                   
                   
                   
                   
                   
                 block (Buffered) 
               
               
                   
                 2h 
                 Transform Select Buf 
                 DSI 
                 R/W 
                  1 
                 0h 
                 Data select, Odd/Even or true 2 channel 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data (Buffered) 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Samples from Channels 1 &amp; 2 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Odd/even samples from Channel 1 
               
               
                   
                 3h 
                 Data Dec Rate 
                 DSI 
                 R 
                 12 
                 1h 
                 Data path decimation rate out of DSI 
               
               
                   
                   
                   
                   
                   
                   
                   
                 block 
               
               
                   
                 4h 
                 RAM Dec Rate 
                 DSI 
                 R 
                 12 
                 1h 
                 DCM data decimation rate out of DSI 
               
               
                   
                   
                   
                   
                   
                   
                   
                 block 
               
               
                   
                 5h 
                 Transform Select 
                 DSI 
                 R 
                  1 
                 0h 
                 Data select, Odd/Even or true 2 channel 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Samples from Channels 1 &amp; 2 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Odd/even samples from Channel 1 
               
               
                 2000h 
                 0h 
                 ThresholdB 
                 SPD 
                 R/ 
                 16 
                 7FFFh 
                 Buffered Threshold Value 
               
               
                   
                 1h 
                 Sat1CountB 
                 SPD 
                 R 
                 16 
                 0h 
                 Buffered Number of Channel 1 Saturated 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Samples 
               
               
                   
                 2h 
                 Sat2CountB 
                 SPD 
                 R 
                 16 
                 0h 
                 Buffered Number of Channel 2 Saturated 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Samples 
               
               
                   
                 3h 
                 Pk1Ch1ValB 
                 SPD 
                 R 
                 16 
                 0h 
                 Buffered Channel 1 Peak Value 
               
               
                   
                 4h 
                 Pk1Ch2ValB 
                 SPD 
                 R 
                 16 
                 0h 
                 Buffered Channel 2 Associated Value 
               
               
                   
                 5h 
                 Pk2Ch1ValB 
                 SPD 
                 R 
                 16 
                 0h 
                 Buffered Channel 1 Associated Value 
               
               
                   
                 6h 
                 Pk2Ch2VaBl 
                 SPD 
                 R 
                 16 
                 0h 
                 Buffered Channel 2 Peak Value 
               
               
                   
                 7h 
                 Sat1Count 
                 SPD 
                 R/W 
                 16 
                 0h 
                 Number of Channel 1 Saturated Samples 
               
               
                   
                 8h 
                 Sat2Count 
                 SPD 
                 R/W 
                 16 
                 0h 
                 Number of Channel 2 Saturated Samples 
               
               
                   
                 9h 
                 Pk1Ch1Val 
                 SPD 
                 R/W 
                 16 
                 0h 
                 Channel 1 Peak Value 
               
               
                   
                 Ah 
                 Pk1Ch2Val 
                 SPD 
                 R/W 
                 16 
                 0h 
                 Channel 2 Associated Value 
               
               
                   
                 Bh 
                 Pk2Ch1Val 
                 SPD 
                 R/W 
                 16 
                 0h 
                 Channel 1 Associated Value 
               
               
                   
                 Ch 
                 Pk2Ch2Val 
                 SPD 
                 R/W 
                 16 
                 0h 
                 Channel 2 Peak Value 
               
               
                   
                 Dh 
                 Threshold 
                 SPD 
                 R/W 
                 16 
                 7FFFh 
                 Threshold Value 
               
               
                 3000h 
                 0h 
                 Sample Size Buffered 
                 DOC 
                 R/W 
                  9 
                 2h 
                 Buffered DC compensation sample size 
               
               
                   
                 1h 
                 Sample Size 
                 DOC 
                 R 
                  9 
                 2h 
                 DC compensation sample size 
               
               
                   
                 2h 
                 Ch1 Comp 
                 DOC 
                 R 
                 16 
                 0h 
                 Channel 1 DC compensation value 
               
               
                   
                 3h 
                 Ch2 Comp 
                 DOC 
                 R 
                 16 
                 0h 
                 Channel 2 DC compensation value 
               
               
                 4000h 
                 00-07h 
                 Buf Coefficients 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered Module 0 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 0 
               
               
                   
                 08-0Fh 
                 Buf Coefficients 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered Module 1 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 1 
               
               
                   
                 10-17h 
                 Buf Coefficients 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered Module 2 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 2 
               
               
                   
                 18-1Fh 
                 Buf Coefficients 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered Module 3 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 3 
               
               
                   
                 20-27h 
                 Buf Coefficients 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered Module 4 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 4 
               
               
                   
                 28-2Fh 
                 Buf Coefficients 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered Module 5 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 5 
               
               
                   
                 30-37h 
                 Buf Coefficients 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered Module 6 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 6 
               
               
                   
                 38-3Fh 
                 Buf Coefficients 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered Module 7 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 7 
               
               
                   
                 40h 
                 Buf FIRA Mode Reg 1 
                 FIRA 
                 R/W 
                 16 
                 0h 
                 Buffered FIRA Control Register 1 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bits 1-0 ch1DataMuxEnSig, 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch1ABDataMuxEnSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Mux selects ch1CascadeDataIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Mux selects ch1ABCascadeDatIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 2h =&gt; Mux selects ch1DataIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 3h =&gt; Mux selects zero 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bits 3-2 = ch2DataMuxEnSig, 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2ABDataMuxEnSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Mux selects ch2CascadeDataIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Mux selects ch2ABCascadeDatIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 2h =&gt; Mux selects ch2DataIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 3h =&gt; Mux selects zero 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 4 = ch1MultEnSig; Enables Ch1 phase 
               
               
                   
                   
                   
                   
                   
                   
                   
                 shifting. 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Disabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Enabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 5 = ch2MultEnSig; Enables Ch2 phase 
               
               
                   
                   
                   
                   
                   
                   
                   
                 shifting. 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Disabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Enabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 6 = ch1RndEnSig; Enables Ch1 
               
               
                   
                   
                   
                   
                   
                   
                   
                 rounding. 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Disabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Enabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 7 = ch2RndEnSig; Enables Ch2 
               
               
                   
                   
                   
                   
                   
                   
                   
                 rounding. 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Disabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Enabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 8 = ch1DataMux2EnSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Mux selects data from Ch1 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Rnd/Mult 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Mux selects data from Ch1 data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 mux 1 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 9 = ch1SumMux2EnSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Mux selects data from FIR1 
               
               
                   
                   
                   
                   
                   
                   
                   
                 sumOut 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Mux selects data from 
               
               
                   
                   
                   
                   
                   
                   
                   
                 sumMuxEnSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 10 = ch2DataMux2EnSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Mux selects data from Ch2 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Rnd/Mult 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Mux selects data from Ch2 data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 mux 1 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 11 = ch2SumMux2EnSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Mux selects data from FIR3 
               
               
                   
                   
                   
                   
                   
                   
                   
                 sumOut 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Mux selects data from FIR3 sumIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 12 = crossCoupleSelSig; Enables cross 
               
               
                   
                   
                   
                   
                   
                   
                   
                 coupling of data out of 16 tap FIRs. 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Disabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Enabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 13 = sumEnSig; Enables Ch1 &amp; Ch2 
               
               
                   
                   
                   
                   
                   
                   
                   
                 sum input data. 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Disables 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Enables 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 14 = dataEnSelSig; 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Mux selects extDataEnLowIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Mux selects dataEnLowIn 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 15 = allTapMuxEnSig; Allows sum 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output from FIR2 to be used as sum input 
               
               
                   
                   
                   
                   
                   
                   
                   
                 to FIR3 and combiner outputs sum data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 from FIR4 for Ch1 and zeros for Ch2. 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Disabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Enabled 
               
               
                   
                 80h 
                 Buf. FIRA Mode 
                 FIRA 
                 R/W 
                  1 
                 0h 
                 Buffered FIRA Control Register 2 
               
               
                   
                   
                 Reg 2 
                   
                   
                   
                   
                 Bit 15 = Synchronous FIR clear 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h =&gt; Clear disabled 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h =&gt; Clear enabled 
               
               
                 4000h 
                 100-107h 
                 Coefficients Mod 0 
                 FRA 
                 R 
                 16 
                 0h 
                 Module 0 Tap 0-7 coefficients 
               
               
                   
                 108-10Fh 
                 Coefficients Mod 1 
                 FRA 
                 R 
                 16 
                 0h 
                 Module 1 Tap 0-7 coefficients 
               
               
                   
                 110-117h 
                 Coefficients Mod 2 
                 FRA 
                 R 
                 16 
                 0h 
                 Module 2 Tap 0-7 coefficients 
               
               
                   
                 118-11Fh 
                 Coefficients Mod 3 
                 FRA 
                 R 
                 16 
                 0h 
                 Module 3 Tap 0-7 coefficients 
               
               
                   
                 120-127h 
                 Coefficients Mod 4 
                 FRA 
                 R 
                 16 
                 0h 
                 Module 4 Tap 0-7 coefficients 
               
               
                   
                 128-12Fh 
                 Coefficients Mod 5 
                 FRA 
                 R 
                 16 
                 0h 
                 Module 5 Tap 0-7 coefficients 
               
               
                   
                 130-137h 
                 Coefficients Mod 6 
                 FRA 
                 R 
                 16 
                 0h 
                 Module 6 Tap 0-7 coefficients 
               
               
                   
                 138-13Fh 
                 Coefficients Mod 7 
                 FRA 
                 R 
                 16 
                 0h 
                 Module 7 Tap 0-7 coefficients 
               
               
                   
                 140h 
                 Mode Register 1 
                 FRA 
                 R 
                 16 
                 0h 
                 Mode 1 Control register 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 0; Read ch1DataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 1; Read ch1ABDataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 2; Read ch2DataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 3; Read ch2ABDataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 4; Read ch1MultEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 5; Read ch2MultEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 6; Read ch1RndEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 7; Read ch2RndEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 8; Read ch1MuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 9; Read ch1SumMux2EnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 10; Read ch2MuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 11; Read ch2SumMux2EnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 12 Read crossCoupledEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 13; Read sumEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 14; Read dataEnSelRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15; Read allTapMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15; allTapMuxEnRSig 
               
               
                   
                 180h 
                 Mode Register 2 
                 FRA 
                 R 
                 16 
                 0h 
                 Mode 2 Control register 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 0-14; No function 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15 = 1; Read firClr 
               
               
                 5000h 
                 0h 
                 Data Dec Rate Buf 
                 DCI 
                 R/W 
                 12 
                 1h 
                 buffered decimation rate for the output 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data 
               
               
                   
                 1h 
                 Ram Dec Rate Buf 
                 DCI 
                 R/W 
                 12 
                 1h 
                 buffered decimation rate for the RAM data 
               
               
                   
                 2h 
                 Bypass Mode Buf 
                 DCI 
                 R/W 
                  1 
                 0h 
                 buffered mode select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0h = non-bypass; Data passed through 
               
               
                   
                   
                   
                   
                   
                   
                   
                 unchanged 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1h = bypass; Bypass date (16) is passed 
               
               
                   
                   
                   
                   
                   
                   
                   
                 directly and concatenated with zeros based 
               
               
                   
                   
                   
                   
                   
                   
                   
                 on the scale format selected. 
               
               
                   
                 3h 
                 Output Data Format 
                 DCI 
                 R/W 
                  1 
                 0h 
                 buffered data format select 
               
               
                   
                   
                 Buf 
                   
                   
                   
                   
                 data not rounded = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data rounded to 16 bits = 1h 
               
               
                   
                 4h 
                 RAM Data Format Buf 
                 DCI 
                 R/W 
                  1 
                 0h 
                 buffered RAM data format select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data not rounded = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data rounded to 16 bits = 1h 
               
               
                   
                 5h 
                 Scale Format Buf 
                 DCI 
                 R/W 
                  3 
                 0h 
                 buffered scale format for output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 30:16 = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 29:15 = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 28:14 = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 27:13 = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 26:12 = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 25:11 = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 24:10 = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 23:9 = 7h 
               
               
                 5000h 
                 6h 
                 RAM Scale Format 
                 DCI 
                 R/W 
                  3 
                 0h 
                 buffered scale format for RAM data 
               
               
                   
                   
                 Buf 
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 30:16 = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 29:15 = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 28:14 = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 27:13 = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 26:12 = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 25:11 = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 24:10 = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 23:9 = 7h 
               
               
                   
                 7h 
                 Data Enable Delayed 
                 DCI 
                 R/W 
                  4 
                 1h 
                 buffered data enable delayed 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 2 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 3 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 4 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 5 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 6 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 7 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 7h 
               
               
                   
                 8h 
                 Data Dec Rate 
                 DCI 
                 R 
                 12 
                 1h 
                 current decimation rate for the output data 
               
               
                   
                 9h 
                 Ram Dec Rate 
                 DCI 
                 R 
                 12 
                 1h 
                 current decimation rate for the RAM data 
               
               
                   
                 Ah 
                 Bypass Mode 
                 DCI 
                 R 
                  1 
                 0h 
                 current mode select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 non-bypass = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 bypass mode = 1h 
               
               
                   
                 Bh 
                 Output Data Format 
                 DCI 
                 R 
                  1 
                 0h 
                 current data format select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data not rounded = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data rounded to 16 bits = 1h 
               
               
                   
                 Ch 
                 Ram Data Format 
                 DCI 
                 R 
                  1 
                 0h 
                 current RAM data format select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data not rounded = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data rounded to 16 bits = 1h 
               
               
                 5000h 
                 Dh 
                 Scale Format 
                 DCI 
                 R 
                  3 
                 0h 
                 current scale format for output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 30:16 = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 29:15 = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 28:14 = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 27:13 = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 26:12 = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 25:11 = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 24:10 = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 23:9 = 7h 
               
               
                   
                 Eh 
                 RAM Scale Format 
                 DCI 
                 R 
                  3 
                 0h 
                 current scale format for RAM data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 30:16 = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 29:15 = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 28:14 = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 27:13 = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 26:12 = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 25:11 = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) dala Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 24:10 = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 23:9 = 7h 
               
               
                   
                 Fh 
                 Data Enable Delayed 
                 DCI 
                 R 
                  4 
                 1h 
                 current data enable delayed 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 2 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 3 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 4 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 5 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 6 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 7 clock cycle delay from output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 enable = 7h 
               
               
                 6000h 
                 000-1FFh 
                 Ch1 Mem 
                 DCM 
                 R/W 
                 16 
                 NA 
                 Channel 1 capture memory 
               
               
                   
                 200-3FFh 
                 Ch2 Mem 
                 DCM 
                 R/W 
                 16 
                 NA 
                 Channel 2 capture memory 
               
               
                   
                 400h 
                 Buffered Control 
                 DCM 
                 R/W 
                 16 
                 0h 
                 Buffered Data capture control register 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 0 = 1 - Capture On Sync 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 1 = 1 - Snapshot Burst Out 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 2 = 1 - Snapshot Feedback 
               
             
          
           
               
                   
                 Bits 4, 5 - 
                 Capture select 00b = DSI, 
               
               
                   
                   
                 01b = DCI, 10b = DCF 
               
             
          
           
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 11 = 1 - Capture Complete 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 15 = 1 - Reset (Note: Read back at 0b 
               
               
                   
                   
                   
                   
                   
                   
                   
                 after you write a 1b) 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bits 3, 6, 7, 8, 9, 10, 13, 14 - No function 
               
               
                   
                 401h 
                 Dly_BHi 
                 DCM 
                 R/W 
                  4 
                 0h 
                 Delay Counter Buffered High Byte 
               
               
                   
                 402h 
                 Dly_BLo 
                 DCM 
                 R/W 
                 16 
                 1h 
                 Delay Counter Buffered Low Byte 
               
               
                   
                 404h 
                 Control 
                 DCM 
                 R 
                 16 
                 0h 
                 Data capture control register 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 0 = 1 - Capture On Sync 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 1 = 1 - Snapshot Burst Out 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 2 = 1 - Snapshot Feedback 
               
             
          
           
               
                   
                 Bits 4, 5 - 
                 Capture select 00b = DSI, 
               
               
                   
                   
                 01b = DCI, 10b = DCF 
               
             
          
           
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 11 = 1 - Capture Complete 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 15 = 1 - Reset (Note: Read back at 0b 
               
               
                   
                   
                   
                   
                   
                   
                   
                 after you write a 1b) 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bits 3, 6, 7, 8, 9, 10, 13, 14 - No function 
               
               
                   
                 405h 
                 Dly_Hi 
                 DCM 
                 R 
                  4 
                 0h 
                 Delay Counter High Byte 
               
               
                   
                 406h 
                 Dly_Lo 
                 DCM 
                 R 
                 16 
                 1h 
                 Delay Counter Low Byte 
               
               
                 7000h 
                 0h 
                 Sync control 
                 TCI 
                 R/W 
                 16 
                 0h 
                 Sync control for all modules 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 0 - Sync Select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = CPU 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1b = External 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 1 = Sync Source 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = CPI 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1b = PDI 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 2 = Sync on/off 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Of 
               
               
                   
                   
                   
                   
                   
                   
                   
                 1b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 3 = Sync Mode Change 
               
               
                   
                 1h 
                 SPD control 
                 TCI 
                 R/W 
                 16 
                 0h 
                 Bits 0, 1 = SPD Sync Source 
               
               
                   
                   
                   
                   
                   
                   
                   
                 00b - NOP, 01b - CPU 
               
               
                   
                   
                   
                   
                   
                   
                   
                 10b - Delay, 11b - External 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 8 - CPU Dump Control 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Off, 01b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 10 - CPU Enable Control 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Off, 01b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 12 - Armed 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Off, 01b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 15 - SPD timing reset 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Off, 01b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bits 2, 3, 4, 5, 6, 7, 9, 11, 13, 14 
               
               
                   
                   
                   
                   
                   
                   
                   
                 No function 
               
               
                   
                 2h 
                 SPD Delay High 
                 TCI 
                 R/W 
                  4 
                 0h 
                 SPD delay counter high byte 
               
               
                   
                 3h 
                 SPD Delay Low 
                 TCI 
                 R/W 
                 16 
                 1h 
                 SPD delay counter low byte 
               
               
                   
                 4h 
                 SPD Enable High 
                 TCI 
                 R/W 
                  4 
                 0h 
                 SPD enable counter high byte 
               
               
                   
                 5h 
                 SPD Enable Low 
                 TCI 
                 R/W 
                 16 
                 1h 
                 SPD enable counter low byte 
               
               
                   
                 6h 
                 DOC control 
                 TCI 
                 R/W 
                 16 
                 0h 
                 Bits 0, 1 = DOC Sync Source 
               
               
                   
                   
                   
                   
                   
                   
                   
                 00b - NOP, 01b - CPU 
               
               
                   
                   
                   
                   
                   
                   
                   
                 10b - Delay, 11b - External 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 8 - CPU Dump Control 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Off, 01b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 10 - CPU Enable Control 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Off, 01b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 12 - Armed 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Off, 01b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bit 15 - SPD timing reset 
               
               
                   
                   
                   
                   
                   
                   
                   
                 0b = Off, 01b = On 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Bits 2, 3, 4, 5, 6, 7, 9, 11, 13, 14 
               
               
                   
                   
                   
                   
                   
                   
                   
                 No function 
               
               
                   
                 7h 
                 DOC Delay High 
                 TCI 
                 R/W 
                  8 
                 0h 
                 DOC delay counter high byte 
               
               
                   
                 8h 
                 DOC Delay Low 
                 TCI 
                 R/W 
                 16 
                 1h 
                 DOC delay counter low byte 
               
               
                   
                 9h 
                 DOC Enable High 
                 TCI 
                 R/W 
                  8 
                 0h 
                 DOC enable counter high byte 
               
               
                   
                 Ah 
                 DOC Enable Low 
                 TCI 
                 R/W 
                 16 
                 1h 
                 DOC enable counter low byte 
               
               
                 8000h 
                 0h 
                 Data Dec Rate Buf 
                 DCF 
                 R/W 
                 12 
                 1h 
                 buffered decimation rate for the output 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data 
               
               
                   
                 1h 
                 Ram Dec Rate Buf 
                 DCF 
                 R/W 
                 12 
                 1h 
                 buffered decimation rate for the RAM data 
               
               
                   
                 2h 
                 Bypass Mode Buf 
                 DCF 
                 R/W 
                  1 
                 0h 
                 buffered bypass mode or data path select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data path = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 bypass mode = 1h 
               
               
                   
                 3h 
                 Output Data Format 
                 DCF 
                 R/W 
                  2 
                 0h 
                 buffered data format select 
               
               
                   
                   
                 Buf 
                   
                   
                   
                   
                 data not rounded = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 round to 16 bits = 1h 
               
               
                   
                 4h 
                 Ram Data Format Buf 
                 DCF 
                 R/W 
                  1 
                 0h 
                 buffered RAM data format select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data not rounded = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 round to 16 bits = 1h 
               
               
                   
                 5h 
                 Scale Format Buf 
                 DCF 
                 R/W 
                  3 
                 0h 
                 buffered scale format for output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 30:16 = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 29:15 = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 28:14 = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 27:13 = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 26:12 = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 25:11 = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 24:10 = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 23:9 = 7h 
               
               
                 8000h 
                 6h 
                 RAM Scale Format 
                 DCF 
                 R/W 
                  3 
                 0h 
                 buffered scale format for RAM data 
               
               
                   
                   
                 Buf 
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 30:16 = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 29:15 = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 28:14 = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 27:13 = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 26:12 = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 25:11 = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 24:10 = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 23:9 = 7h 
               
               
                   
                 8h 
                 Data Dec Rate 
                 DCF 
                 R 
                 12 
                 1h 
                 current decimation rate for the output data 
               
               
                   
                 9h 
                 RAM Dec Rate 
                 DCF 
                 R 
                 12 
                 1h 
                 current decimation rate for the RAM data 
               
               
                   
                 Ah 
                 Bypass Mode 
                 DCF 
                 R 
                  1 
                 0h 
                 current bypass mode or data path select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data path = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 bypass mode = 1h 
               
               
                   
                 Bh 
                 Output Data Format 
                 DCF 
                 R 
                  2 
                 0h 
                 current data format select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data not rounded = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 round to 16 bits = 1h 
               
               
                   
                 Ch 
                 RAM Data Format 
                 DCF 
                 R 
                  1 
                 0h 
                 current RAM data format select 
               
               
                   
                   
                   
                   
                   
                   
                   
                 data not rounded = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 round to 16 bits = 1h 
               
               
                 8000h 
                 Dh 
                 Scale Format 
                 DCF 
                 R 
                  3 
                 0h 
                 current scale format for output data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 30:16 = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 29:15 = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 28:14 = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 27:13 = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 26:12 = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 25:11 = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 24:10 = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 23:9 = 7h 
               
               
                   
                 Eh 
                 RAM Scale Format 
                 DCF 
                 R 
                  3 
                 0h 
                 current scale format for RAM data 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 30:16 = 0h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 29:15 = 1h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 28:14 = 2h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 27:13 = 3h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 26:12 = 4h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 25:11 = 5h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 24:10 = 6h 
               
               
                   
                   
                   
                   
                   
                   
                   
                 output is input (round 16) data Bit 31, Bit 
               
               
                   
                   
                   
                   
                   
                   
                   
                 23:9 = 7h 
               
               
                 9000h 
                 00-07h 
                 Buf Coefficients 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Module 0 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 0 
               
               
                   
                 08-0Fh 
                 Buf Coefficients 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Module 1 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 1 
               
               
                   
                 10-17h 
                 Buf Coefficients 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Module 2 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 2 
               
               
                   
                 18-1Fh 
                 Buf Coefficients 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Module 3 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 3 
               
               
                   
                 20-27h 
                 Buf Coefficients 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Module 4 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 4 
               
               
                   
                 28-2Fh 
                 Buf Coefficients 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Module 5 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 5 
               
               
                   
                 30-37h 
                 Buf Coefficients 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Module 6 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 6 
               
               
                   
                 38-3Fh 
                 Buf Coefficients 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Module 7 Tap 0-7 coefficients 
               
               
                   
                   
                 Mod 7 
               
               
                   
                 40h 
                 Buf Mode Register 1 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Mode 1 Control register 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 0 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2DataMuxEhRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 1 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2ABDataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 2 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2DataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 3 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2ABDataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 4 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch1MultEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 5 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2MultEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 6 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch1RndEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 7 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2RndEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 8 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch1MuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 9 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch1SumMux2EnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 10 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2MuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 11 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 ch2SumMux2EnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 12 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 crossCoupledEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 13 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 sumEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 14 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 dataEnSelRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 allTapMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15 = 1; Enable 
               
               
                   
                   
                   
                   
                   
                   
                   
                 allTapMuxEnRSig 
               
               
                   
                 80h 
                 Buf. Mode Register 2 
                 FRB 
                 R/W 
                 16 
                 0h 
                 Buffered Mode 2 Control register 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 0-14; No function 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15 = 1; Enable firClr 
               
               
                 9000h 
                 100-107h 
                 Coefficients Mod 0 
                 FRB 
                 R 
                 16 
                 0h 
                 Module 0 Tap 0-7 coefficients 
               
               
                   
                 108-10Fh 
                 Coefficients Mod 1 
                 FRB 
                 R 
                 16 
                 0h 
                 Module 1 Tap 0-7 coefficients 
               
               
                   
                 110-117h 
                 Coefficients Mod 2 
                 FRB 
                 R 
                 16 
                 0h 
                 Module 2 Tap 0-7 coefficients 
               
               
                   
                 118-11Fh 
                 Coefficients Mod 3 
                 FRB 
                 R 
                 16 
                 0h 
                 Module 3 Tap 0-7 coefficients 
               
               
                   
                 120-127h 
                 Coefficients Mod 4 
                 FRB 
                 R 
                 16 
                 0h 
                 Module 4 Tap 0-7 coefficients 
               
               
                   
                 128-12Fh 
                 Coefficients Mod 5 
                 FRB 
                 R 
                 16 
                 0h 
                 Module 5 Tap 0-7 coefficients 
               
               
                   
                 130-137h 
                 Coefficients Mod 6 
                 FRB 
                 R 
                 16 
                 0h 
                 Module 6 Tap 0-7 coefficients 
               
               
                   
                 138-13Fh 
                 Coefficients Mod 7 
                 FRB 
                 R 
                 16 
                 0h 
                 Module 7 Tap 0-7 coefficients 
               
               
                   
                 140h 
                 Mode Register 1 
                 FRB 
                 R 
                 16 
                 0h 
                 Mode 1 Control register 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 0; Read ch2DataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 1; Read ch2ABDataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 2; Read ch2DataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 3; Read ch2ABDataMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 4; Read ch1MultEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 5; Read ch2MultEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 6; Read ch1RndEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 7; Read ch2RndEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 8; Read ch1MuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 9; Read ch1SumMux2EnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 10; Read ch2MuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 11; Read ch2SumMux2EnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 12; Read crossCoupledEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 13; Read sumEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 14; Read dataEnSelRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15; Read allTapMuxEnRSig 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15; allTapMuxEnRSig 
               
               
                   
                 180h 
                 Mode Register 2 
                 FRB 
                 R 
                 16 
                 0h 
                 Mode 2 Control register 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 0-14; No function 
               
               
                   
                   
                   
                   
                   
                   
                   
                 Data Bit 15 = 1; Read firClr 
               
               
                   
               
             
          
         
       
     
     Accordingly,