Abstract:
A memory control method, a memory controller, and a memory device implementing the method are provided. The memory controller controls the memory device comprising a plurality of banks, and a first row in a bank is activated for access. The memory controller receives a request for access of a second row in the bank and delivers a special command to the memory device. The memory device deactivates the first row and activates the second row upon receipt of the special command.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to memory device, and in particular, to a control method for synchronous dynamic random access memory (SDRAM). 
   2. Description of the Related Art 
     FIG. 1   a  shows a conventional memory control timing sequence. In a SDRAM, a memory controller receives data access requests such as requests for reading/writing a specific address, and delivers corresponding commands to a memory device storing the requested data. A memory device typically comprises four or eight banks. A bank is a storage array formed by rows and columns with data bits stored therein. In each bank, only one row can be activated at a specific time, therefore, at most a total of eight rows are simultaneously activated in a memory device comprising eight banks. To active a row in a bank, the memory controller delivers an ACTIVE command to the memory device through a command bus comprising CS/RAS/CAS/WE wires, with the row address delivered through an address bus simultaneously. An activation typically consumes three clock cycles. After the row activation, the memory device delivers a READ/WRITE command to access the data according to a column address delivered through the address bus at the same time. The accessed row remains activated until another row in the same bank is requested for access. A PRECHARGE command is utilized to deactivate the first row before activating the second row, which typically consumes three clock cycles. 
   As shown in  FIG. 1   a , a plurality of commands are delivered through the command bus RAS/CAS/WE sequentially, with corresponding row addresses and column addresses delivered through an address bus. At time T 1 , a PRECHARGE command  110  is delivered to deactivate a first row in a bank BA 0 . In the meantime, a don&#39;t care signal  100  is delivered through the address bus. Thereafter, at time T 4 , an ACTIVE command  112  is delivered to activate a second row in the bank BA 0 , with a second row address  116  delivered through the address bus. At time T 7 , a READ command  114  is delivered to read a column in the activated row of the bank BA 0 , with the column address  118  delivered through the address bus. At time T 8 , another PRECHARGE command  120  deactivates a third row in bank BA 1 , and similarly, the corresponding ACTIVE command  122  and READ command  124  are delivered at time T 11  and T 14  to read data from the bank BA 1 . In this way, a command bus consumes fourteen cycle times to deliver six commands in which eight cycle times are idle, thus the bus utility is inefficient. 
     FIG. 1   b  shows another conventional memory command timing sequence. The bus utility is enhanced by interleaving different bank commands to avoid idle states. The PRECHARGE command  120  for bank BA 1  is delivered at time T 2 , and the PRECHARGE command  130  for bank BA 2  is delivered at time T 3 . Similarly, times T 5  and T 6  deliver ACTIVE commands for banks BA 1  and BA 2 , and times T 8  and T 9  deliver READ commands for banks BA 1  and BA 2 . In this way, the bus is fully utilized during time T 1  to T 9 . At time T 10 , however, the access for a bank BA 3  still comprise idle cycle times, for example, T 11 , T 12 , T 14 , and T 15  in  FIG. 1   b . Thus, at most three banks (BA 0 , BA 1  and BA 2 ) can be accessed in succession. 
     FIG. 2  is a flowchart of conventional memory control. In step  202 , the memory controller is initialized by receiving data access requests. In step  204 , the memory controller determines whether the bank containing the requested data is activated. If not, the process proceeds to step  206  to activate the bank and perform a read/write operation in step  214 . If the bank is activated in step  204 , the process proceeds to step  208  to determine whether the requested row is same as the previously activated row. If yes, The read/write operation is directly performed in step  214 . If not, the process proceeds to step  210  to send a PRECHARGE command to deactivate the previously activated row, and then send an ACTIVE command to activate the currently requested row in step  212  followed by step  214 . The memory control operation ends with step  216 . 
   In this way, a previously activated row must be deactivated before activating a currently requested row in the same bank, thus two commands are required to complete the operation, a PRECHARGE command for the previously activated row and an ACTIVE command for the currently requested row. 
   BRIEF SUMMARY OF THE INVENTION 
   An exemplary embodiment of a memory control method is provided. A memory controller controls a memory device comprising a plurality of banks, and a first row in a bank is activated for access. The memory controller receives a request for access of a second row in the bank and delivers a special command to the memory device. The memory device deactivates the first row and activates the second row upon receipt of the special command. 
   The memory controller and the memory device are coupled by a command bus and an address bus. The special command is transferred through the command bus, and the second row address is synchronously transferred through the address bus with the delivery of the special command. 
   Upon receipt of the special command, the memory device deactivates the first row in the bank. Three clock cycles after the first row deactivation, the memory device activates the second row in the bank. 
   A memory controller implementing the memory control method is also provided. The memory controller comprises an address table, a control logic and a command generator. The address table records all activated row addresses in each bank, including the first row address. The control logic enables a special command when receiving a request for access of a second row in the first bank. The command generator delivers the special command to the memory device when enabled. The memory device deactivates the first row and activates the second row in the first bank when receiving the special command. 
   The memory device implementing the memory control method is also provided, comprising a plurality of banks, and a command decoder decoding command signals delivered from the memory controller. When access to a second row in the first bank is requested, the memory controller delivers a special command to the command decoder, and the memory device deactivates the first row and activates the second row in the first bank accordingly. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which: 
       FIG. 1   a  shows a conventional memory control timing sequence; 
       FIG. 1   b  shows another conventional memory command timing sequence; 
       FIG. 2  is a flowchart of conventional memory control; 
       FIG. 3  shows an embodiment of the memory control timing sequence; 
       FIG. 4  is an exemplary flowchart of the memory control; and 
       FIG. 5  shows an exemplary memory system according to the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   A detailed description of the invention is provided in the following. 
     FIG. 3  shows an embodiment of the memory control timing sequence. Conventionally in one bank, a PRECHARGE command for the previously activated row and an ACTIVE command for the currently requested row are required when the two rows are different. In the invention, a special command is provided to operate equivalently as combination of the two conventional commands, thus the utility of command bus can be reduced. As shown in  FIG. 3 , the special command is referred to as a “PRECHARGE with ACTIVE” command PRA. For example, in time T 1 , a PRA command  302  for bank BA 0  is delivered with a row address  306 , thus the bank BA 0  is acknowledged to deactivate the previously activated row therein, and activate the currently requested row according to the row address  306 . In this embodiment, a PRA command utilizes the command bus one cycle time, and requires six wait times for the memory device to complete the corresponding operation. Six cycle times later, in time T 7 , when the row in the bank BA 0  is ready, a READ command  304  with column address  308  is delivered to perform the read operation in the activated row of bank BA 0 . The memory controller makes use of the remaining cycle times to access other banks. For example, at Time T 2  and T 8 , a PRA command  312  and READ command  314  are delivered to access bank BA 1 , time T 3  and T 9  for bank BA 2 , and time T 4  and T 10  for bank BA 3 . In this way, at maximum of six banks can be successively accessed within 12 cycle times T 1  to T 12  whereas a conventional method has at most only three banks accessed in the same situation. 
     FIG. 4  is an exemplary flowchart of the memory control. In step  402 , the memory controller is initialized by receiving data access requests. In step  404 , the memory controller determines whether the bank containing the requested data is activated. If not, the process proceeds to step  408  to activate the bank and performs a read/write operation in step  412 . If the bank is activated in step  404 , step  406  determines whether the requested row is same to the previously activated row. If yes, a read/write operation is directly performed in step  412 . If not, step  410  sends a special command to the memory device. Six cycle times later, after the previously activated row is deactivated and the currently requested row is activated, step  412  is proceeded. The memory control operation ends in step  414 . 
     FIG. 5  shows an exemplary memory system according to the invention. The memory system comprises a memory controller  510  and a memory device  520 . The memory controller  510  comprises a command generator  512 , a scheduler  514  and a page table  516 . Data requests corresponding to a specific address are sent to the memory controller  510 , and in response, data DQ is obtained from the memory device  520  under the access control provided by the memory controller  510 . The memory device  520  comprises four or eight banks  524 , and the page table  516  in the memory controller  510  keeps a record of the bank statuses, registering every currently activated row. The scheduler  514  determines which command to deliver based on the page table  516  and the data requests, respectively generating a control signal to the command generator  512 . The command generator  512  accordingly generates and delivers the command to the memory device  520  via the command bus CS/RAS/CAS/WE, along with corresponding addresses delivered through the address bus. The commands comprise conventional READ, WRITE, REFRESH, PRECHARGE, ACTIVE, and the special command proposed in the invention, PRECHARGE with ACTIVE. The special command is delivered when the bank status and data request meet the condition that a currently requested row for a bank is different from the previously activated row in the same bank. 
   The memory device  520  also comprises a command decoder  522 , an address latch  526  and a data pad  528 . The command decoder  522  receives the commands delivered from the command generator  512 , and send corresponding control signal to the banks  524 . The address latch  526  is coupled to the memory device via the address bus, receiving addresses sent along with the commands for operations in the banks  524 . The data pad  528  operates as an input/output port for the banks  524 , controlled by a bank selection signal sent from the address latch  526  to sent/receive data. The command decoder  522  is capable of recognizing the special command to perform equivalent operation as a combination of the conventional PRECHARGE and ACTIVE commands. Upon receipt of the special command, the command decoder  522  sends a control signal to deactivate the previously activated row in the selected bank. Three clock cycles after the previous row deactivation, the command decoder  522  sends another control signal to activate the requested row in the same bank. Through the command decoder  522 , the activation and deactivation in the banks  524  are not different from conventional operations, thus, benefits of full compatibility are realized. 
   While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.