Abstract:
A frequency offset correction system includes a phase shift estimation unit and correction unit. The phase shift estimation unit estimates a pilot phase shift from pilot signal data for a plurality of bits, and estimates a data phase shift of data from the pilot phase shift for each bit when the frequency offset of a received signal having data of an in-phase component whose bit rate is variable, and pilot signal data of a quadrature component is small. The correction unit sequentially adds data phase shifts and pilot phase shifts estimated by the phase shift estimation unit, and performs frequency offset correction of the received signal using a phase shift obtained by selectively inserting the estimated pilot phase shifts in the added estimated data phase shifts. A frequency offset correction method is also disclosed.

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates to an AFC (Auto Frequency Control) circuit and, more particularly, to a frequency offset correction system and correction method used in the AFC circuit of a CDMA (Code Division Multiple Access) receiver. 
   As shown in  FIG. 5 , a conventional CDMA receiver comprises a down converter  11  for receiving an RF (Radio Frequency) signal and converting it into an IF (Intermediate Frequency) signal, a despread unit  12  for spectrum-despreading the IF signal output from the down converter  11 , and a demodulator  13  for demodulating an output signal from the despread unit  12  to generate received data. 
   A CDMA received signal is a signal prepared by modulating a signal into BPSK (Binary Phase Shift Keying) signals by data and pilot signal data of I-Channel (In-phase component) and Q-Channel (Quadrature component), superimposing these signals to modulate them into QPSK (Quadrature Phase Shift Keying) signals, and modulating the resultant signals by a spread code. 
     FIGS. 6A  to  6 D show the frame structure of CDMA received data. As shown in  FIG. 6A , one frame of CDMA received data is constituted by Frame#1, Frame#2, Frame #3, . . . , Frame#72, and has one period T Super =720 ms. As shown in  FIG. 6B , Frame#3 is comprised of Slot#1, Slot #2, Slot#3, . . . , Slot#15, and has one period Tf=10 ms. 
   As shown in  FIGS. 6C and 6D , Slot#3 is made up of I-channel and Q-Channel, and has one period Ts=0.666 ms. I-Channel has N data -bit data, and Q-Channel has N pilot -bit pilot signal data. 
   Table 1 shows the relationship between the bit rates and the number of bits of I-Channel and Q-Channel in  FIGS. 6C and 6D . 
   
     
       
             
             
             
             
             
           
             
             
             
             
             
           
             
             
             
             
             
           
         
             
                 
               TABLE 1 
             
           
           
             
                 
                 
             
             
                 
               I-Channel 
                 
               Q-Channel 
                 
             
           
        
         
             
               Channel 
                 
               Channel 
                 
                 
             
             
               Bit Rate 
               N data   
               Bit Rate 
               N pilot   
               n/m = 
             
             
               (kbps) 
               (bits) 
               (kbps) 
               (bits) 
               N data /N pilot   
             
             
                 
             
           
        
         
             
               15 
               10 
               15 
               10 
               1 
             
             
               30 
               20 
               15 
               10 
               2 
             
             
               60 
               40 
               15 
               10 
               4 
             
             
               120 
               80 
               15 
               10 
               8 
             
             
               240 
               160 
               15 
               10 
               16 
             
             
               480 
               320 
               15 
               10 
               32 
             
             
               960 
               640 
               15 
               10 
               64 
             
             
                 
             
           
        
       
     
   
   As shown in Table 1, the channel bit rate of Q-Channel is fixed to, e.g., 15 kbps, and the number (N pilot ) of bits of pilot signal data is also fixed to, e.g., 10. To the contrary, the channel bit rate of I-Channel is variable, and takes, e.g., 15, 30, 60, 120, 240, 480, and 960 kbps. In correspondence with them, the number (N data ) of bits of data is also variable, and takes, e.g., 10, 20, 40, 80, 160, 320, and 640. 
   The AFC circuit of a COMA demodulator comprises a frequency offset correction apparatus for correcting the frequency offset of a received signal. The frequency offset correction apparatus stores pilot signal data (fixed bit rate) of Q-Channel and data (variable bit rate) of I-Channel for one slot. The AFC circuit estimates the frequency offset value from the stored pilot signal data of Q-Channel, and corrects the frequency offset of the received signal at the bit rate of the pilot signal data. 
   Frequency offset correction of removing a frequency offset from a received signal and performing modulation and the like is used not only in the CDMA but also in another system, as disclosed in Japanese Patent Laid-Open No. 6-30070. To increase the precision of frequency offset correction for a received signal, there is proposed a method of correcting the frequency offset at the bit rate of data of I-Channel using the frequency offset value of estimated pilot signal data. 
   In the conventional frequency offset correction method, when the channel bit rate of data of I-Channel is higher than that of pilot signal data of Q-Channel, e.g., the truncation error of the frequency offset in obtaining a phase shift Δθ per bit increases. 
   This will be described in detail. To perform integrating operation for a frequency offset estimated from pilot signal data, phase shifts Δθ are added within one slot. As the channel bit rate of data of I-Channel is higher, the number of channel bits is larger. Thus, the number of phase shifts Δθ added within one slot increases, and the influence of the error of the frequency offset caused by integrating operation increases. 
   In the conventional frequency offset correction method, when the frequency offset of pilot signal data decreases, the change amount of the phase shift per symbol decreases. Particularly when the angular frequency of pilot signal data of Q-Channel is processed at a fixed point, the truncation error of the frequency offset further increases. 
   SUMMARY OF THE INVENTION 
   It is an object of the present invention to provide a frequency offset correction system and method for increasing the precision of frequency offset correction. 
   To achieve the above object, according to the present invention, there is provided a frequency offset correction system comprising phase shift estimation means for estimating a pilot phase shift from pilot signal data for a plurality of bits, and estimating a data phase shift of data from the pilot phase shift for each bit when a frequency offset of a received signal having data of an in-phase component whose bit rate is variable, and pilot signal data of a quadrature component is small, and correction means for sequentially adding data phase shifts and pilot phase shifts estimated by the phase shift estimation means, and performing frequency offset correction of the received signal using a phase shift obtained by selectively inserting the pilot phase shifts in the added data phase shifts. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram showing a frequency offset correction apparatus according to an embodiment of the present invention; 
       FIGS. 2A  to  2 E are timing charts showing selection control operation of a processing rate controller  7  shown in  FIG. 1  when the bit rate of data of I-Channel is high; 
       FIGS. 3A  to  3 E are timing charts showing section control operation of the processing rate controller shown in  FIG. 1  when the frequency offset (phase shift Δθ 2 ) of pilot signal data of Q-Channel is small; 
       FIG. 4  is a flow chart for explaining selection control operation of the processing rate controller  7  shown in  FIG. 1 ; 
       FIG. 5  is a block diagram showing the schematic arrangement of a conventional CDMA receiver; and 
       FIGS. 6A  to  6 D are views showing the frame structure of CDMA received data. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENT 
   The present invention will be described in detail below with reference to the accompanying drawings. 
     FIG. 1  shows a frequency offset correction apparatus according to an embodiment of the present invention. As shown in  FIG. 1 , the frequency offset correction apparatus of this embodiment comprises adders  1 - 1  and  1 - 2 . The adder  1 - 1  receives a phase shift (phase change amount) Δθ 1  of data of I-Channel (in-phase component), and adds phase shifts in units of bits. The adder  1 - 2  receives a phase shift (phase change amount) Δθ 2  Of pilot signal data of Q-Channel (quadrature component), and adds phase shifts in units of bits. 
   The output ports of the adders  1 - 1  and  1 - 2  are respectively connected to flip-flops (F/Fs)  2 - 1  and  2 - 2 . The output port of the flip-flop  2 - 2  is connected to one input port of the adder  1 - 2 . The output port of the flip-flop  2 - 1  is connected to a selector  3  for selecting one of the outputs of the flip-flops  2 - 1  and  2 - 2 . The output port of a switch  3 - 1  is connected to one input port of the adder  1 - 1 . 
   The output port of the switch  3 - 1  is connected to a complex multiplier  5  via a frequency converter  4 . The output port of the complex multiplier  5  is connected to a phase shift estimation unit  6  for estimating the phase shifts Δθ 1  and Δθ 2  per bit. One output port of the phase shift estimation unit  6  is connected to the other input port of the adder  1 - 1 , whereas the other output port is connected the other input port of the adder  1 - 2 . 
   The phase shifts Δθ 1  and Δθ 2  correspond to frequency offsets Δf(=Δθ/2πT) per bit of data of I-Channel and pilot signal data of Q-Channel. T is a time per bit (1/bit rate), and Δf is a frequency offset per bit. 
   The other output port of the phase shift estimation unit  6  is connected to a processing rate controller  7 . The processing rate controller  7  receives update information of the phase shift Δθ 1  by the phase shift Δθ 2  on the basis of the relationship in magnitude between the bit rate and frequency offset of data of I-Channel obtained from the phase shift estimation unit  6 , and performs switching control of the switch  3 - 1  of the selector  3 . 
   The adder  1 - 1  and flip-flop  2 - 1  add a previous phase shift θ+(n−1)Δθ 1  to the phase shift Δθ 1  per bit, and execute integrating operation at a timing corresponding to the channel bit rate. The adder  1 - 2  and flip-flop  2 - 2  add a previous phase shift θ+(m−1)Δθ 2  to the phase shift Δθ 2  per bit, and execute integrating operation at a timing corresponding to the channel bit rate. 
   The switch  3 - 1  of the selector  3  alternatively selects one of output signals from the flip-flops  2 - 1  and  2 - 2 , i.e., integrated signals θ+nΔθ 1  and θ+mΔθ 2  in accordance with a selection signal (SEL) from the processing rate controller  7 , and outputs the selected signal as a selector output θ+nΔθ to the frequency converter  4 . Note that a selector output θ+mΔθ 2  is input as a previous sum to the adder  1 - 1 . 
   The frequency converter  4  performs frequency conversion for the selector output θ+nΔθ, and outputs an in-phase component cos(θ+nΔθ) and quadrature component sin(θ+nΔθ) to the complex multiplier  5 . The complex multiplier  5  executes complex multiplication of the output signal cos(θ+nΔθ) and sin(θ+nΔθ) from the frequency converter  4  by a CDMA received signal (I and Q) to perform frequency offset correction of the received signal (I and Q), and outputs the corrected received signal (I c  and Q c ). 
   Note that the CDMA received signal (I and Q) having a frequency offset is a signal prepared by primary-modulating the BPSK signals of data and pilot signal data of I-Channel and Q-Channel, and further secondary-modulating the QPSK signals by a spread code. 
   Complex multiplication by the complex multiplier  5  is executed by
 
 I   c   +jQc =( I+jQ )exp [ j (θ+ nΔθ )]
 
 I   c   =I  cos( θ+n Δθ)− Q  sin(θ+ n Δθ) 
 
 Q   c   =I  sin(θ+ n Δθ)+ Q  cos(θ+ n Δθ)  (1) 
 
   The phase shift estimation unit  6  performs estimation processing of the phase shifts Δθ 1  and Δθ 2  per bit as follows. The two phase shifts Δθ 1  and Δθ 2  per bit estimated from a received signal by the phase shift estimation unit  6  are given by
 
Δθ=2 πΔf·T   (2) 
 
   There are various methods of calculating the frequency offset using pilot signal data, and one method will be exemplified. The phase shift Δθ 2  corresponding to the frequency offset of the channel bit rate (15 kbps) of pilot signal data is obtained using the pilot signal data. 
   More specifically, as given by equation (3), an average is calculated for (N pilot −1) from a received signal (I c  and Q c ) and the theoretical values (PL i  and PL q ) of pilot signal data, thereby obtaining a frequency shift vector Θ per bit of pilot signal data:
 
Θ=Σ( D   k   ×U   k   + )( D   k-1   ×U   k-1   + ) + 
 
 D   k   =PLi+jPLq  
 
 U   k   =I   c   +jQ   c   (3) 
 
where  +  is the complex conjugate.
 
   As given by equation (4), Δθ 2 (p) corresponding to the frequency offset per bit of pilot signal data can be attained based on the inverse tangent of the in-phase component and quadrature component of the frequency offset vector:
 
Δθ 2 ( p )=Δθ 2 ( p− 1)+ A  TAN( Im[Θ]/Re[Θ] )  (4) 
 
where p is an integer.
 
   On the other hand, as given by equation (5), Δθ 1 (P) corresponding to the frequency offset per bit of a data signal can be obtained by a right shift of log 2(N data /N pilot ) of Δθ 2 (p):
 
Δθ 1 ( p )=Δθ 2 ( p )&gt;&gt;log 2( N   data   /N   pilot )  (5) 
 
   In equation (5), when processing is done at a fixed decimal point under the constraints of the hardware arrangement and the like, Δθ 1 (p) truncates lower bits of Δθ 2 (p) to decrease the precision. This becomes more prominent at a higher channel bit rate of data of I-Channel. If the frequency offset decreases, the phase change amount per bit (symbol) decreases, and an error increases particularly upon processing at each frequency. For this reason, as the bit rate of data of I-Channel increases, the phase offset Δθ 1  is partially switched by the phase shift Δθ 2 . 
   To increase the phase change amount as the frequency offset decreases, phase change amounts (2Δθ 2 , 3Δθ 2 , . . . ) for a plurality of bits (symbols) are obtained for pilot signal data of Q-Channel. The phase change amount Δθ 1  per bit of data of I-Channel is calculated from the phase change amounts for a plurality of bits (symbols) obtained for the pilot signal data of Q-Channel. 
   The processing rate controller  7  outputs based on the phase shift Δθ 2  the selection signal SEL for controlling switching of the switch  3 - 1  of the selector  3  (to be described later). Letting θ be the initial phase, the selector  3  selects a signal θ+nΔθ 1  or θ+mΔθ 2  by the selection signal SEL, and outputs θ+nΔθ. 
   A correction unit  10  is constituted by the adders  1 - 1  and  1 - 2 , flip-flops  2 - 1  and  2 - 2 , selector  3 , frequency converter  4 , complex multiplier  5 , and processing rate controller  7 . 
     FIGS. 2A  to  2 E show the timings of selection control operation of the processing rate controller  7  when the bit rate of data of I-Channel is high. In the following description, N data /N pilot =4, the phase shift Δθ 2  is selected when a time T is n mod 4=0 (mod is an operator for calculating a remainder), and otherwise, the phase shift Δθ 1  is selected. 
   The time (T) shown in  FIG. 2A  is a time per bit (1/bit rate) when the channel bit rate of I-Channel in Table 1 is 60 kbps. As shown in  FIG. 2B , an output n Δθ 1  from the flip-flop  2 - 1  is represented every time T as θ, θ+Δθ 1 , θ+2Δθ 1 , θ+3Δθ 1 , θ+4Δθ 1 , θ+5Δθ 1 , θ+6Δθ 1 , θ+7Δθ 1 , θ+8Δθ 1 , θ+9Δ74  1 , . . . . As shown in  FIG. 2C , an output mΔθ 2  from the flip-flop  2 - 2  is represented every bit of pilot signal data as θ, θ+Δθ 2 , θ+2Δθ 2 , . . . . 
   As shown in  FIG. 2D , the processing rate controller  7  generates a signal SEL at a Q-Channel bit rate of 15 kbps. The signal SEL selects the output nΔθ 1  from the flip-flop  2 - 1  for “0”, and the output mΔθ 2  from the flip-flop  2 - 2  for “1”. As shown in  FIG. 2E , an output nΔθ from the switch  3 - 1  of the selector  3  is represented every time T as θ, θ+Δ 74   1 , θ+2Δθ 1 , θ+3Δθ 1 , θ+Δθ 2 , θ+Δθ 2 +Δθ 1 , θ+Δθ 2 +2Δθ 1 , θ+Δθ 2 +3Δθ 1 , θ+2Δθ 2 , θ+2Δθ 2 +Δθ 1 , . . . . 
   Hence, the processing rate controller  7  inserts, every 4 T time, selection of the phase shift of Q-Channel in selection of the phase shift for each bit rate of I-Channel. 
   Note that the signal SEL is generated at 15 kbps. When the bit rate of data is low, the signal SEL may be generated at 15 kbps or less, and the bit rate of the signal SEL may be increased with an increase in the bit rate of data in order to suppress an increase in error by more frequently correcting the phase shift of pilot signal data as the bit rate of data increases. 
     FIGS. 3A  to  3 E show the timings of section control operation of the processing rate controller  7  when the frequency offset (phase shift Δθ 2 ) of pilot signal data of Q-Channel is small. As shown in  FIG. 3A , the channel bit rate of I-Channel is 60 kbps, similar to FIG.  2 A. 
   When the frequency offset (phase shift Δθ 2 ) of pilot signal data is small, and the phase shift estimation unit  6  estimates the pilot signal data every 2 bits, the processing rate controller  7  changes the bit rate of Q-Channel to 7.5 kbps, and generates a signal SEL, as shown in FIG.  3 D. As shown in  FIG. 3B , the output nΔθ 1  from the flip-flop  2 - 1  is represented every time T as θ, θ+Δθ 1 , θ+2Δθ 1 , θ+3Δθ 1 , θ+4Δθ 1 , θ+5 Δθ 1 , θ+6Δθ 1 , θ+7Δθ 1 , θ+8Δθ 1 , θ+9Δθ 1 , . . . . 
   As shown in  FIG. 3C , the output mΔθ 2  from the flip-flop  2 - 2  is represented every 2 bits of pilot signal data as θ, θ+2Δθ 2 , . . . . As shown in  FIG. 3E , the output nΔθ from the switch  3 - 1  of the selector  3  is represented every time T as θ, θ+Δθ 1 , θ+2Δθ 1 , θ+3Δθ 1 , θ+4Δθ 1 , θ+5Δθ 1 , θ+6Δθ 1 , θ+7Δθ 1 , θ+2Δθ 2 , θ+2Δθ 2 +Δθ 1 , . . . . 
   The processing rate controller  7  inserts, every 8 T time, selection of mΔθ 2  of Q-Channel in selection of the phase shift nΔθ 1  for each bit rate of I-Channel. 
   Processing operation of the processing rate controller  7  will be explained with reference to FIG.  4 . In step S 1 , the processing rate controller  7  calculates N data /N pilot  on the basis of frame data shown in  FIGS. 6A  to  6 D. For example, N data /N pilot =4. As shown in Table 1, since the number of bits of pilot signal data of Q-Channel is constant  10 , the channel bit rate is fixed to 15 kbps. 
   To the contrary, the bit rate of data of I-Channel increases to 15, 30, 60, 120, 240, 480, and 960 kbps as the number of bits of data increases to 10, 20, 40, 80, 160, 320, and 640. Thus, a possible value N data /N pilot  is N data /N pilot =1, 2, 4, 8, 16, 32, and 64. 
   In step S 2 , the processing rate controller  7  checks whether the frequency offset (phase shift Δθ 2 ) is smaller than a predetermined value “1”. If NO in step S 2 , the processing rate controller  7  shifts to step S 4 ; and if YES, to step S 3 . In step S 3 , the processing rate controller  7  sets N data /N pilot =2N data /N pilot  (=8), and then shifts to step S 5 . Note that N data /N pilot =2N data /N pilot  is merely an example, and N data /N pilot  is not limited to this and may be increased to N data /N pilot = 3 N data /N pilot , 4N data /N pilot , . . . as the frequency offset decreases. 
   In step S 4 , the processing rate controller  7  checks whether N data /N pilot  is larger than a predetermined value “2”. If YES in step S 4 , i.e., the bit rate of data is high, the processing rate controller  7  advances to step S 5 ; and if NO, to step S 11 . In step S 5 , the processing rate controller  7  checks whether n mod(N data /N pilot )=0 is established. 
   If YES in step S 5 , the processing rate controller  7  selects in step S 6  mΔθ 2  shown in  FIG. 2C  when the frequency offset is large, and mΔθ 2  shown in  FIG. 3C  when the frequency offset is small. If NO in step S 5 , the processing rate controller  7  selects in step S 7  nΔθ 1  shown in  FIG. 2B  when the frequency offset is large, and nΔθ 1  shown in  FIG. 3B  when the frequency offset is small. After the processing rate controller  7  selects mΔθ 2 , it increments m. After processing in steps S 6  and S 7 , the processing rate controller  7  shifts to step S 8 . 
   In step S 8 , the processing rate controller  7  controls the switch  3 - 1  of the selector  3  so as to output nΔθ shown in  FIG. 2E  when the frequency offset is large, and nΔθ shown in  FIG. 3E  when the frequency offset is small. 
   In steps S 9  and S 10 , the processing rate controller  7  determines whether to continue processing. If NO in step S 9 , the processing rate controller  7  increments n. 
   If YES in step S 4 , i.e., the frequency offset is large and the bit rate of data is low, the processing rate controller  7  selects nΔθ 1  ( FIGS. 2B and 3B ) in step S 11 , like the prior art, because of no influence of the truncation error. In steps S 12 , S 13 , and S 14 , the processing rate controller  7  determines whether to continue processing. If NO in step S 13 , the processing rate controller  7  increments n. 
   According to the present invention, when the bit rate of data of I-Channel is high, the ratio (frequency) of switching the phase shift of data of I-Channel to the phase shift of pilot signal data of Q-Channel is increased. When the frequency offset is small, the phase shift of data of I-Channel is calculated from a phase shift estimated for each of a plurality of bits of pilot signal data of Q-Channel, and the phase shift of the data is switched to the phase shift of each of a plurality of bits of the pilot signal data. 
   Selection insertion of the phase shift of pilot signal data decreases the frequency offset value per bit when the channel bit rate of data of I-Channel is high. This can prevent an increase in truncation error. This is because, as the bit rate of data of I-Channel is higher, the number of channel bits is larger, and the number of bits added within one slot increases to prevent an increase in the influence of an error. 
   At the same time, when the frequency offset with respect to pilot signal data of Q-Channel decreases, the phase change amount per bit (symbol) is changed to the phase change amount of a plurality of bits to increase the phase change amount. This can prevent an increase in error especially when the angular frequency is processed at a fixed decimal point. 
   Particularly when the bit rate of data is high, and the frequency offset is small, the phase shift estimation unit  6  may estimate the phase shift of pilot signal data for a plurality of bits by giving priority to the case wherein the frequency offset is small. This is because an increase in the error of the phase shift of pilot signal data increases the error of the phase shift of data. 
   As has been described above, according to the present invention, an error by integrating operation of the frequency offset is decreased when the channel bit rate of data of the in-phase component of a signal is high. Further, the truncation error of the frequency offset is decreased when the frequency offset of pilot signal data of the quadrature component is small. Accordingly, the correction precision of the frequency offset increases. 
   When the bit rate of data is high, the sum of errors of the data phase shift is corrected by the pilot phase shift, and the phase shift of a pilot data signal at a small frequency offset is estimated in units of a plurality of bits. The truncation error can be decreased, and the correction precision of the frequency offset can be increased. 
   As the frequency offset decreases, the estimated phase shift of pilot signal data per bit decreases. Not only the truncation error of the estimated phase shift of pilot signal data increases, but also the truncation error of the estimated phase shift of data increases. However, as the frequency offset decreases, the number of bits is increased to increase the estimated phase shift of pilot signal data. Accordingly, the error can be decreased. 
   As the bit rate of data increases, a larger number of truncation errors of the estimated phase shift of data are added. However, the sum is corrected by the estimated phase shift of pilot signal data, so that the error can be decreased. 
   In addition, the error is decreased by giving priority not to a case wherein the bit rate of data is high, but to a case wherein the frequency offset is small. This is because, if the error of the phase shift of pilot signal data increases, the error of the phase shift of data also increases.