Abstract:
A memory device comprises an array of memory cells arranged in rows and columns, a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows, a dummy column of dummy memory cells substantially identical to the memory cells, precharge means for precharging the columns and the dummy column at a precharge potential when no row is selected, and programming means for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means for presetting the dummy memory cells in a first logic state when no row is selected, dummy column programming means for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state, and first detector means for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of the gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from the first logic state to the second logic state.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of integrated memory circuits. More particularly, the invention relates to integrated Random Access Memories (RAMs), for example static RAMs. 
     2. Discussion of the Related Art 
     Conventionally, a memory device such as a static RAM includes four main circuit blocks: a bidimensional array of readable and writable memory cells arranged in rows and columns, a row decoder circuit block for selecting the desired rows inside the array, a column decoder circuit block for selecting the desired columns of the array, and read/write circuits. 
     In general, the memory cell array includes n rows and m columns. Usually, an information word of p bits is stored in the memory cells belonging to a same row. When the memory device is operated in active mode (for reading or programming), the row decoder circuits select one row of the array (i.e., m memory cells are simultaneously selected) and the column decoder circuit selects the desired p columns among the m columns of the array; hence, m memory cells are selected but only a subset p of them is actually accessed. 
     In active mode, the current consumption of the memory array is therefore given by: 
     
         I.sub.ddr =m×C.sub.b ×ΔV.sub.r 
    
     for the read operation, where ΔV r  is the voltage swing of the columns, and 
     
         I.sub.ddw =p×C.sub.b ×ΔV.sub.w +(m-p)×C.sub.b ×ΔV.sub.r 
    
     for the write (programming) operation, where C b  is the capacitance of each column, ΔV w  is the voltage swing of the p columns of the memory cells to be programmed, and ΔV r  is the voltage swing of the remaining unselected columns. 
     The most common approach to reduce the current consumption involves reducing the column capacitance C b . 
     Another approach which can be used, also in combination with the previous one, involves partitioning the memory cell array into multiple blocks that are selectively activated. In this way, the number m of cells connected to each row is reduced. 
     Still another technique provides for limiting the voltage swing ΔV r  by controlling the width of the time pulse during which a row is selected. This technique, however, is used only for the read operation. 
     In view of the state of the art described, it is an object of the present invention to provide a memory device having a low current consumption when it is accessed in write mode. 
     SUMMARY OF THE INVENTION 
     According to the present invention, this and other objects are attained by a memory device comprising an array of memory cells arranged in rows and columns, a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows, a dummy column of dummy memory cells substantially identical to the memory cells, precharge means for precharging the columns and the dummy column at a precharge potential when no row is selected, and programming means for setting selected columns at respective programming potentials. The memory device further includes dummy memory cell preset means for presetting the dummy memory cells in a first logic state when no row is selected, dummy column programming means for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state, and first detector means for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling the plurality of gates. Each of the gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from the first logic state to the second logic state. 
     The memory device of the present invention has a lower current consumption than conventional devices; in fact, when the memory device is programmed, the desired row remains selected for only a short time necessary for the memory cells of the selected columns to switch to the desired state. The dummy memory cells are used to monitor the switching time of the memory cells. By reducing the time that a row is enabled, the unselected columns are thus not completely discharged, therefore reducing overall current consumption. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other features and advantages of the present invention will be made apparent by the following detailed description of a particular embodiment, illustrated by way of a non-limiting example in the accompanying drawings, wherein: 
     FIG. 1 is a schematic block diagram of a memory device; 
     FIG. 2 is a more detailed circuit diagram of the memory device of FIG. 1, showing several features of the present invention; 
     FIG. 3 shows the circuit diagram of a memory cell; 
     FIG. 4 is a schematic circuit diagram of a precharge and programming circuit for a memory cell column of the memory device shown in FIG. 2; 
     FIG. 5 is a schematic circuit diagram of a precharge and programming circuit for a dummy column of the memory device of FIG. 2; and 
     FIG. 6 is a time diagram of some signals of the circuit of FIG. 2. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 schematically shows the main circuit blocks of a memory device according to the present invention, for example, a static RAM (SRAM). The memory device includes a bidimensional array 1 of readable and programmable memory cells 2. Conventionally, within the array 1, the memory cells 2 are arranged in n rows R1-Rn and m columns C1-Cm. 
     A row decoder circuit 3 is supplied with row address signals X1-Xk and selects one row R1-Rn of the array, depending on the specific logic value of signals X1-Xk. Similarly, a column decoder circuit 4 is supplied with column address signals Y1-Yh and selects a desired group of p columns of the array, according to the logic value of signals Y1-Yh. In the schematic diagram of FIG. 1, block 4 also includes the sensing circuits necessary for reading the selected memory cells 2 and for outputting read data Q1-Qp. Block 4 also includes programming circuits for programming the memory cells of the selected columns according to the logic states of data signals D1-Dp. A control circuit 5 is provided for controlling blocks 3 and 4 in accordance with the particular operation mode of the memory device. 
     FIG. 2 shows in more detail the structure of the memory array 1 when the memory device is a static RAM. Each column C1-Cm includes a pair of complementary bit lines BL and BL&#39;. The memory cells 2 may be, for example, six transistor memory cells (6T memory cells). 
     The known circuit structure of the 6T memory cells 2 is shown in FIG. 3 (prior art). The memory cell 2 conventionally includes two inverters I1 and I2, for example, of the CMOS type. Inverter I1 includes a P-channel pull-up MOSFET P1 and an N-channel pull-down MOSFET N1 connected in series between a voltage supply VDD and ground. Inverter 12 similarly includes a P-channel pull-up MOSFET P2 and an N-channel pull-down MOSFET N2 connected in series between VDD and ground. An output node A of inverter I1 is connected to the input node of inverter I2 (i.e., to the gates of P2 and N2); similarly, an output node B of inverter I2 is connected to an input node of inverter I1 (i.e., to the gates of P1 and N1). The memory cell further includes first and second selection transistors N3 and N4, formed, for example, by N-channel MOSFETs. Transistor N3 couples node A to a first input/output node O of the memory cell 2, while N4 couples node B to a second, logically complemented, input/output node O&#39; of the memory cell. Node O is connected to a first bit line BL of the pair of complementary bit lines of a generic column Ci of the memory array, and node O&#39; is connected to a second bit line BL&#39; of the pair. The gates of the selection transistors N3 and N4 are both connected to a generic row Rk of the memory array. 
     Referring now again to FIG. 2, the memory array 1 includes, in addition to rows R1-Rn and columns C1-Cm, a dummy row DR and a dummy column DC of memory cells. The dummy column DC includes (n+1) dummy memory cells DMC0-DMCn, each of which are similar to the memory cells 2. The dummy memory cells include two cross-coupled inverters I3 and I4 (for example, of the CMOS type) and two selection transistors N5 and N6 for coupling the output nodes A and B of the inverters to a pair of complementary dummy bit lines DBL and DBL&#39; of the dummy column. The gates of the selection transistors N5 and N6 of dummy memory cell DMC0 are connected to the dummy row DR and the gates of the selection transistors N5 and N6 of dummy memory cells DMC1-DMCn are connected to a respective one of rows R1-Rn of the memory array. Each dummy memory cell DMC0-DMC1 further includes a pre-set P-channel MOSFET P3 that couples node A to the voltage supply VDD. For dummy memory cell DMC0, the gate of the preset transistor P3 is connected to the dummy row DR, and for dummy cells DMC1-DMCn, the gate of transistor P3 is connected to a respective one of the rows R1-Rn. The dummy row DR includes the dummy memory cell DMC0 and m memory cells 2. 
     As shown in FIG. 2, the row decoder circuit 3 includes a predecoder 6 supplied by the row address signals X1-Xk, having n output signals RS1-RSn that are individually activated to select one of the n rows R1-Rn of the array. The row decoder circuit 3 further includes n row drivers RD1-RDn, each controlling the selection of a respective row R1-Rn. Each driver includes an AND gate having a first input supplied with a respective one of signals RS1-RSn, a second input supplied with an enable signal EN generated by the control circuit 5, and a third input supplied with a respective signal RES1-RESn taken from node A of the dummy cell DMC1-DMCn belonging to the respective row. The row decoder circuit 3 also includes a dummy row driver DRD substantially formed by an AND gate having a first input supplied with signal EN and a second input connected to VDD. 
     The control circuit 5 is supplied with a clock signal CK, and is further supplied with a signal SBW generated by a first level detector DET1 detecting the voltage level of the dummy bit line DBL of the dummy column DC, and with a signal ENDW generated by a second level detector DET2 detecting the voltage level of node A of the dummy cell DMC0 belonging to the dummy row DR. The control circuit 5 generates, in addition to signal EN, a precharge signal PRE and a write signal WE supplied to the column decoder circuit 4. Signals PRE and WE are also supplied to a write and precharge circuit 4&#39; for the dummy column DC. 
     FIG. 4 schematically shows the circuit structure of a write and precharge circuit of the column decoder circuit 4. There are m such circuits provided in the column decoder circuit, each one associated to a respective column Ci of the memory array. Signal PRE controls first switching means, formed for example by P-channel MOSFETs P4 and P5, for selectively connecting the complementary bit lines BL and BL&#39; of the column to VDD. Second switching means are also provided, for example represented by N-channel MOSFETs N7 and N8, for selectively connecting the bit lines BL and BL&#39; of the column Ci to a data signal Dj and, respectively, to the logic complement thereof, data signal Dj is one of the p data signals D1-Dp shown in FIG. 1. N-channel MOSFETs N7 and N8 are controlled by an AND gate 7 supplied with signal WE and with a column selection signal CSi. Signal CSi is activated to select the respective column Ci and is generated by a column predecoder (not shown), included in the column decoder circuit 4, that is supplied with the columns address signals Y1-Yh, as shown in FIG. 1. The column decoder circuit 4 further includes, in addition to the m write and precharge circuits of FIG. 4 and the predecoder circuit, sensing circuits for reading the information stored in the selected memory cells. 
     FIG. 5 schematically shows the structure of the dummy write and precharge circuit 4&#39; for the dummy column DC. Similarly to the circuit of FIG. 4, first switching means formed by P-channel MOSFETs P6 and P7, controlled by signal PRE, are provided to selectively connect the complementary dummy bit lines DBL and DBL&#39; to VDD. Second switching means, formed by N-channel MOSFETs N9 and N10 and controlled by signal WE, are provided for selectively connecting bit line DBL to ground, and bit line DBL&#39; to VDD. 
     The operation of the circuits previously described will be now explained with the help of the timing diagram of FIG. 6. 
     Before the start of a write operation of the memory device, signal PRE is activated (&#34;0&#34;) and signal WE is deactivated (&#34;0&#34;). Signal EN is also deactivated (&#34;0&#34;), so as to keep all of the rows R1-Rn of the array deactivated (i.e., at the ground potential). As a result, transistors N3 and N4 of all of the memory cells 2 are off and nodes A and B of the memory cells are disconnected from the bit lines BL and BL&#39;. Transistors P4 and P5 in the write and precharge circuits, as well as transistors P6 and P7 in the dummy write and precharge circuit 4&#39;, are activated, and all of the bit lines BL and BL&#39; and the dummy bit lines DBL and DBL&#39; are connected to (and precharged at) VDD. Transistors N5 and N6 of the dummy memory cells DMC0-DMCn are off, and nodes A and B of the dummy cells are disconnected from the dummy bit lines DBL and DBL&#39;; however, the pre-set transistors P3 are on, and nodes A of the dummy memory cells are connected to VDD. In this manner, the dummy memory cells are preset in the state A=&#34;1&#34;, B=&#34;0&#34;. 
     At the rising edge of clock signal CK (FIG. 6) signal PRE is deactivated (&#34;1&#34;). Transistors P4 and P5 in the write and precharge circuits of the columns are turned off, so that all of the bit lines BL and BL&#39; of the array are disconnected from VDD. The same holds true for the dummy column; P6 and P7 in the dummy write and precharge circuit are turned off and the dummy bit lines DBL and DBL&#39; are disconnected from VDD. 
     Subsequently, control circuit 5 activates signal WE (&#34;1&#34;) to start the write operation. In the write and precharge circuits associated with the selected columns (CSi=&#34;1&#34;), N7 and N8 are turned on. According to the logic value of Dj, the bit lines BL and BL&#39; of a selected column Ci are either kept at VDD or are discharged; for example, if in column Ci Dj=&#34;0&#34;, the bit line BL of that column is discharged. If instead Dj=&#34;1&#34;, it is the bit line BL&#39; that is discharged. The bit lines of the unselected columns (CSi=&#34;0&#34;) remain charged at VDD. 
     The activation of signal WE always causes the dummy bit line DBL of the dummy column DC to be discharged. 
     The discharge time of DBL is substantially identical to the discharge time of a generic bit line BL or BL&#39; of the array. When the potential of DBL falls below a threshold of level detector DET1, signal SBW is activated to inform control circuit 5 that the bit lines of the array to be discharged have reached the desired voltage. Control circuit 5 then activates signal EN (&#34;1&#34;), so that the potential of the addressed row Rq (FIG. 6) of the memory array (i.e. the row for which the respective selection signal RS1-RSn is activated) is driven high by the respective driver RD1-RDn; also, activation of signal EN causes the selection of the dummy row DR. 
     Selection of the addressed row Rq causes the activation of transistors N3 and N4 in all the memory cells 2 and transistors N5 and N6 in the dummy cell DMC belonging to the row; similarly, selection of the dummy row causes the activation of transistors N5 and N6 of the dummy memory cell DMC0 belonging to the dummy row. 
     During the precharge phase, before the rising edge of CK, the dummy memory cells DMC0-DMCn are all preset in the condition A=&#34;1&#34;, B=&#34;0&#34; (by means of the presetting transistors P3). Also, the dummy write and precharge circuit 4&#39; is designed such that the potential of bit line DBL is set to &#34;0&#34;, upon the actuation of the write signal WE. As a result, after the selection of the addressed row R1-Rn and of the dummy row DR, the data stored in the dummy memory cells DMC of the dummy column DC must change from A=&#34;1&#34;, B=&#34;0&#34; to A=&#34;0&#34;, B=&#34;1&#34;. At the same time, those memory cells 2 of the selected row and belonging to the selected columns which store a datum opposite to that which is desired to be programmed must change their state. In the unselected columns, one of the two complementary bit lines BL or BL&#39; will always be discharged. 
     The dummy memory cell DMC1-DMCn belonging to the selected row serves to monitor the change of the state of the memory cells 2 which are to be programmed. As soon as signal RES1-RESn (the potential of node A of the dummy cell) falls below the threshold voltage of the NAND gate RD1-RDn of the respective row driver circuit, it is assumed (since the dummy memory cell is substantially identical to the other memory cells 2 of the row) that also the other memory cells 2 of the row have changed their programming state. The row selection signal R1-Rn is thus deactivated by RES1-RESn, and the transistors N3 and N4 of all the memory cells 2 of the row are turned off. In this way, the bit lines BL or BL&#39; of the unselected columns are not completely discharged, because the row remains selected only for a time sufficient to cause the memory cells to be programmed to change their state. 
     The change of state of the dummy memory cell DMC0 of the dummy row cause the level detector DET2 to activate signal ENDW, which in turn causes the control circuit 5 to reset by deactivating signals EN and WE and activating signal PRE. By providing the dummy column DC physically adjacent to the row driver circuits RD1-RDn of the row decoder circuit, the disabling of the row driver after the change of state of the respective dummy memory cell is almost instantaneous; signal ENDW instead propagates a greater distance from the dummy row to the control circuit, so that a suitable delay is provided between the activation of one of signals RES1-RESn and the deactivation of signal EN by control circuit 5. 
     In this way, as shown by curves 100 and 100&#39; in FIG. 6, the voltage swing ΔV s  of unselected bit lines (curve 100) is much less than the voltage swing ΔV of unselected bit lines in the prior art circuits (curve 100&#39;), because the time interval during which the accessed row Rq remains enabled is shorter. 
     In another embodiment of the present invention, it is possible to omit the dummy row shown in FIG. 2. Signal ENDW, used for resetting the control circuit 5, is provided, for example, by OR-ing together all the signals RES1-RESn. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements are intended to be within the scope and spirit of the invention. Accordingly, the foregoing description is by way of example only, and it is not intended as limiting. The invention&#39;s limit is defined only in the following claims and the equivalent thereto.