Abstract:
A data storage apparatus comprises a memory circuit including 2 n1 ·n2 memories for storing binary information. Data of N bits from the row direction and column direction can be written and read out in parallel, and, also, such data of N bits reduced with a data reduction rate of an exponential power of 2 can be written and read out in parallel. The apparatus is used, for example, for displaying data on a display by fetching the data from common file servers connected to a private network or the like.

Description:
BACKGROUND OF THE INVENTION 
     In connection with storage of data, a method has been proposed in which data can be written in and read out in bit-parallel relation of N bits from independently operable N=2 n .sbsp.1 memories in the row direction and column direction and in which, when the data reduction rate is an exponential power of 2, reduced data can be written in and read out from the N memories in bit-parallel relation of 2 n .sbsp.1 bits in the row direction and column direction. The proposed method is such that all the data are divided into blocks each including 2 n .sbsp.1 +n .sbsp.2 bits in the row direction and 2 n .sbsp.1 +n .sbsp.2 bits in the column direction, where 2 n .sbsp.2 is the maximum data reduction rate, and each of the blocks composed of 2 n .sbsp.1 +n .sbsp.2 ×2 n .sbsp.1 +n .sbsp.2 bits is used as a unit to be processed. According to the proposed method, the data are allocated to the N memories capable of making independent parallel operation so that the data in each of individual groups may not be allocated to the same memory when the results of sampling of the data in the same row and same column in the block at a bit interval of 2 h  (0≦h≦n 2 ) are grouped into groups of N bits. 
     To explain the above method in which all the data in the individual groups can be allocated to the different memories when the results of sampling of the data in the same row and same column in the block at the bit interval of 2 h  (0≦h≦n 2 ) are grouped into the groups of N=2 n .sbsp.1 bits, suppose, for example, the case where N=8 and n 2  =1. According to the proposed method, the former 8 bits of the data in an i-th row (i=1-8) in the block are subjected to an (i-1)-bit cyclic shift to be stored at an address (32k 0  +i-1) in the memories m 1  to m 8  respectively; the latter 8 bits of the data in the i-th row (i=i-8) are subjected to an i-bit cyclic shift to be stored at an address (32k 0  +i+7) in the respective memories m 1  to m 8  ; the former 8 bits of the data in an i-th row (i=9-16) are subjected to an (i-8)-bit cyclic shift to be stored at an address (32k 0  +i+7) in the respective memories m 1  to m 8  ; and the latter 8 bits of the data in the i-th row (i=9-16) are subjected to an (i-7)-bit cyclic shift to be stored at an address (32k 0  +i+15) in the respective memories m 1  to m 8 . FIG. 1 shows the numbered data of 16×16 bits, and FIG. 2 shows that the data shown in FIG. 1 are allocated to and stored at the individual addresses in the memories m 1  to m 8  according to the proposed method. 
     FIG. 3 shows the less-significant address values applied to the memories m 1  to m 8  during data writing and reading in the column direction when the data are allocated to the memories in the manner shown in FIG. 2. It will be apparent from FIG. 3 that 1 is added to the less-significant address values during data writing and reading in the column direction. (For example, when i (0≦i≦7) is the less-significant address value applied to the memory m 1 , a less-significant address value given by the remainder of division of (i+j-1) by 8 is applied to a memory m j . The same applies also to the reading of data with a data reduction rate of 1/2. Thus, in the proposed method, the addresses applied to the memories must be converted by processing in the manner above described. Therefore, the prior art method is defective in that the scale of the address conversion processing circuit increases in proportion to the number N of the memories. 
     SUMMARY OF THE INVENTION 
     It is a primary object of the present invention to provide a data storage apparatus which includes independently operable N=2 n .sbsp.1 memories, in which data can be written and read in bit-parallel relation of N bits in both the column direction and the row direction, in which data reduced with a data reduction rate of an exponential power of 2 can also be read in bit-parallel relation of N bits in both the row direction and the column direction, and in which the mode of processing for conversion of the addresses applied to the memories is simplified. 
     The present invention which attains the above object provides a data storage apparatus which includes, when the number of data to be handled in parallel is N=2 n .sbsp.1 and the maximum data reduction rate during data reading is 2 n .sbsp.2, a memory circuit including independently operable 2 n .sbsp.1 memories m 1 , m 2 , . . . , m 2   n .sbsp.1 ; n 1  address inputs a 0 , a 1 , . . . , a n .sbsb.i -i connected to each of the memories in such a relation that common address inputs a l  are connected to memories m 2  l+1.sub.·i-2.sbsp.l -j  (0≦l≦n 1-1 , 1≦i≦2 n .sbsp.1-1-l, 0≦j≦2 l  -1) and common address inputs a l  are connected to memories m 2 .sbsp.l+1.sub.·i-j ; n 2  address inputs b 0 , b 1 , . . . , b n .sbsp.2 -1  connected to the memories in such a relation that common address inputs b s  are connected to memories m 2 .spsb. t+1 .sub.·p-2.spsb.t -q  (0≦s≦n 2  -1, 1≦p≦2 n .sbsp.1.sup. +1+t, 0≦q≦2 t  -1, t: remainder of division of s by n 1 ) and common address inputs b s  are connected to memories m 2 .spsb.t-1.sub.·p-q ;n 2  address inputs c 0 , c 1 , . . . , c n .sbsb.2 -1  connected to the memories in such a relation that common address inputs c s  are connected to the memories m 2 .spsb.t+1.sub.·p-2.spsb.t -q  and common address inputs c s  are connected to the memories m 2 .spsb.t-1.sub.·p-q, so that address values corresponding to the positions of data during writing and reading are applied to the memories. For the purpose of storing data in the memories, a block composed of data of 2 n .sbsp.1 +n .sbsp.2 ×2 n .sbsp.1 +n   2  bits is divided into groups each including 2 n .sbsp.1 bits in the row direction and column direction respectively to provide 2 n .sbsp.2 ×2 n .sbsp.2 sub-blocks each of which is composed of data of 2 n .sbsp.1 ×2 n .sbsp.1 bits, and the input data of 2 n .sbsp.1 bits in the row direction (or column direction) of each of the subblocks are permutated under sequential correspondence between the positions of the input data in the sub-block and the row (column) numbers of the input data in the sub-block, such permutated data being allocated to be stored in the memories. 
     Thus, the present invention provides the following meritorious effects: 
     (1) In a memory circuit including independentntly operable 2 n .sbsp.1 memories m 1 , m 2 , . . . , m 2 .spsb.n 1  for storing permutated input data, n 1  address inputs a 0 , a 1 , . . . , a n .sbsb.1 -1  are connected to each of the 2 n .sbsp.1 memories in such a relation that common address inputs a l  to memories m 2 .spsb.l+1.sub.·i-2.spsb.l -j  (0≦l≦n 1  -1, i≦i≦2 n .sbsp.1 -1-l , 0≦j≦2 l  -1) apply an address value u l  and common address inputs a l  to memories m 2 .sbsp.l+1.sub..i-j apply an address value v l  ; n 2  address inputs b 0 , b 1 , . . . , b n .sbsb.2 -1  are connected to each of the 2 n .sbsp.1 memories in such a relation that common address inputs b s  to memories m 2 .spsb.t+1.sub. .p-2.spsb.t -q  (0≦s≦n 2  -1, 1≦p≦2 n .sbsp.1 -1-t , 0≦q≦2 t  -1, t: remainder of division of s by n 1 ) apply an address value x s  and common address inputs b s  to memories m 2 .spsb.t+1.sub.·p-q apply an address value y s  ; and n 2  address inputs c 0 , c 1 , . . . , c n .sbsb.2 -1  are connected to each of the 2 n .sbsp.1 memories in such a relation that common address inputs c s  to the memories m 2 .spsb.t+1.sub..p-2.spsb.t -q  apply an address value w s  and common address inputs c s  to the memories m 2 .spsb.t+1.sub..p-q apply an address value z s . In the present invention, depending on whether the address values are applied to the memories from the row direction or column direction and depending on the rate of reduction of the input data, the address values u l  and v l , x s  and y s , and w s  and z s  (0≦l≦n 1  -1, 0≦s≦n 2  -1) are controlled to be the same as or an inverted equivalent of the other respectively, so that management or processing of the addresses is facilitated. 
     (2) Even when the number N=2 n .sbsp.1 of data handled in parallel increases, the circuit scale required for the address management or processing increases merely in proportion to n 1  (=log 2  N). 
     (3) Even when the maximum data reduction rate of 1/2n 2  increases, the circuit scale required for the address management or processing increases merely in proportion to 2n 2 . 
     (4) Since an inverse permutation of a permutation Pk (0≦k≦n 1  -1) for permutating data is also Pk, a data permutation circuit for data writing purpose can be designed to be the same as a data permutation circuit for data reading purpose. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block composed of 16×16 bits of numbered data. 
     FIG. 2 shows a prior art manner of allocation of such data to memories. 
     FIG. 3 shows address values applied to the individual memories in the column direction for allocation of the data to the memories in the prior art manner. 
     FIG. 4 shows division of a block composed of 16×16 bits of data into numbered four sub-blocks. 
     FIG. 5 shows numbered data in each of the sub-blocks. 
     FIG. 6 is a block diagram of a preferred embodiment of the data storage apparatus of the present invention. 
     FIG. 7 shows in detail the structure of the memory circuit shown in FIG. 6. 
     FIG. 8(a) and 8(b) shown in detail the structure of the data permutation circuit 2 (3) shown in FIG. 6. 
     FIG. 9 shows the correspondence between the control signals s 0  to s 2  shown in FIG. 6 and the permutation Pk (0≦k≦7) and shows also the data permutated by application of the permutation Pk. 
     FIG. 10 shows in detail the structure of the selector 4 shown in FIG. 6. 
     FIG. 11 shows in detail the structure of the selector 5 shown in FIG. 6. 
     FIG. 12 shows inverse-shuffled data. 
     FIG. 13 shows in detail the structure of the inverse shuffle circuit shown in FIG. 6. 
     FIG. 14(I) and 14(II) show how the data in the block shown in FIG. 4 are allocated to the memories. 
     FIG. 15 shows address values applied to the memories during handling of the data in the column direction. 
     FIG. 16 shows address values applied to the memories when the data reduced with a reduction rate of 1/2 are read out in the row direction. 
     FIG. 17 shows the data reduced with the reduction rate of 1/2 and read out in the column direction and shows also the data permutated in the data permutation circuit 3. 
     FIG. 18 shows address values applied to the memories when the odd-numbered data in the individual columns are extracted to read out the data of 8 bits reduced with the reduction rate of 1/2. 
     FIG. 19 shows the data of 8 bits obtained by extraction of the odd-numbered data in the individual columns to be reduced with the reduction rate of 1/2 and shows also the data permutated in the data permutation circuit 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will now be described in detail. As in the prior art case, it is supposed that the number N of bits handled in parallel is N=8, and the rate of data reduction is up to 1/2. A block composed of 16×16 bits of data is divided into four sub-blocks each of which is composed of 8×8 bits of data. FIG. 4 shows how these sub-blocks are numbered, and FIG. 5 shows how the data in each of the sub-blocks composed of 8×8 bits are numbered. 
     FIG. 6 is a block diagram of an embodiment of the data storage apparatus according to the present invention. 
     Referring to FIG. 6, the data storage apparatus comprises a memory circuit 1 including eight memories m 1  to m 8  which are operable independently of one another. 
     Each of the memories m 1  to m 8  constituting the memory circuit 1 has three address inputs a 0 , a 1  and a 2 . The connection is such that the address inputs a 0  specifying an address value u 0  are connected in common to the memories m 1 , m 3 , m 5  and m 7  ; the address inputs a 0  specifying an address value v 0  are connected in common to the memories m 2 , m 4 , m 6  and m 8  ; the address inputs a 1  specifying an address value u 1  are connected in common to the memories m 1 , m 2 , m 5  and m 6  ; the address inputs a 1  specifying an address value v 1  are connected in common to the memories m 3 , m 4 , m 7  and m 8  ; the address inputs a 2  specifying an address value u 2  are connected in common to the memories m 1 , m 2 , m 3  and m 4  ; and the address inputs a 2  specifying an address value v 2  are connected in common to the memories m 5 , m 6 , m 7  and m 8 . Each of the memories m 2  to m 8  has another address input b 0 . The connection is such that the address inputs b 0  specifying an address value x 0  are connected in common to the memories m 1  ; m 3 , m 5  and m 7  ; and the address inputs b 0  specifying an address value y 0  are connected in common to the memories m 2 , m 4 , m 6  and m 8 . Each of the memories m 1  to m 8  has another address input c 0 . The connection is such that the address inputs c 0  specifying an address value w 0  are connected in common to the memories m 1 , m 3 , m 5  and m 7  ; and the address inputs c 0  specifying an address value z 0  are connected in common to the memories m 2 , m 4 , m 6  and m 8 . Remaining address inputs n 0  are connected in common to all of the memories m 1  to m 8 . FIG. 7 shows in detail the address input connections in the memory circuit 1. 
     Data permutation circuits 2 and 3 make permutation of data. Permutation of the 1st and 2nd data, the 3rd and 4th data, the 5th and 6th data, and the 7th and 8th data in the orderly arranged 8 data is called a permutation P 1 . Permutation of the 1st and 3rd data, the 2nd and 4th data, the 5th and 7th data, and the 6th and 8th data is called a permutation P 2 . Permutation of the 1st and 5th data, the 2nd and 6th data, the 3rd and 7th data, and the 4th and 8th data is called a permutation P 4 . Making the permutation P 2  after attainment of the permutation P 1  is called a composed permutation P 3 . Making the permutation P 4  after attainment of the permutation P 1  is also called a composed permutation P.sub. 5. Making the permutation P 4  after attainment of the permutation P 2  is also called a composed permutation P 6 . Making the permutation P 4  after attainment of the permutation P 3  is also called a composed permutation P 7 . Making no data permutation is called an identity permutation P 0 . Under control of external control signals s 0  to s 2 , the data permutation circuits 2 and 3 execute a selected one of the permutations P 0  to P 7  for the desired permutation of the data. FIG. 8(a) shows in detail the structure of each of the data permutation circuits 2 and 3 composed of unit cells, and FIG. 8(b) shows in detail the structure of each unit cell. FIG. 9 shows the correspondence between the control signals s 0  to s 2  and the permutations Pk (0≦k≦7) executed by the data permutation circuits 2 and 3 and shows also the results of permutation of the data which have been initially arranged orderly from 1 to 8. 
     Referring to FIG. 8(a), the control signals s 0  to s 2  are selectively applied to control signal input terminals e of the cells 21--1 to 21--12. Depending on the level of the control signals s 0  to s 2 , an input data applied to a terminal a appears at a terminal c of a selected cell, and an input data applied to a terminal b appears at a terminal d of the selected cell, or the input data applied to the terminal b appears at the terminal c of the selected cell and the input data applied to the terminal a appears at the terminal d of the selected cell. 
     Referring to FIG. 8(b), each of the cells includes buffer gates 22--1 to 22--4. When the control signal of &#34;L&#34; level is applied to the control signal input terminal e of the buffer gate 22--1, an input data applied to the terminal a appears at the terminal c. while, when the control signal of &#34;H&#34; level is applied, no output appears from the buffer gate 22--1. Also, when the control signal of &#34;H&#34; level is applied to the control signal input terminal e of the buffer gate 22-2, an input data applied to the terminal b appears at the terminal c, while, when the control signal of &#34;L&#34; level is applied, no output appears from the buffer gate 22--2. The buffer gates 22--3 and 22--4 are similar to the buffer gates 22--2 and 22--1 respectively in their operation mode. 
     When, for example, all the control signals s 0  to s 2  are in their &#34;L&#34; level in FIG. 8(a), that is, when s 0  =s 1  =S 2  =0 as shown in FIG. 9, a data train {1, 2, 3, 4, 5, 6, 7, 8} applied to the input terminals i 1  to i 8  appears intact as the original data train {1, 2, 3, 4, 5, 6, 7, 8} at the output terminals 0 1  to 0 8  in FIG. 8(a). On the other hand, when s 2  =1 and s 0  =S 1  =0, the data train {1, 2, 3, 4, 5, 6, 7, 8} applied to the input terminals i 1  to i 8  appear as a permutated data train {5, 6, 7, 8, 1, 2, 3, 4} at the output terminals o 1  to o 8 . 
     Selectors 4 and 5 change over or select the address inputs applied to the memory circuit 1. Depending on whether data to be handled are applied from the row direction or column direction, the selector 4 selects the address values of v 0  =u 0 , v 1  =u 1  and v 2  =u 2  ; or v 0  =u 0 , v 1  =u 1  and v 2  u 2  and applies such address values to the memories m 1  to m 8  shown in FIG. 7. 
     FIG. 10 shows in detail the structure of the selector 4. Referring to FIG. 10, the selector 4 includes an inverter gate 23, an OR gate 24 and buffer gates 25--1 to 25--6. A control signal t 1  is applied through the inverter gate 23 to the OR gate 24. When the OR gate 24 generates its output signal of &#34;H&#34; level, an input signal u 0  applied to the buffer gate 25--1 appears as an output signal v 0 , while, when the output of the OR gate 24 is in its &#34;L&#34; level, no output appears from the buffer gate 25--1. On the other hand, when the OR gate 24 generates its output signal of &#34;L&#34; level, an input signal u 0  applied to the buffer gate 25--2 appears as an inverted output signal v 0  =u 0 , while, when the output of the OR gate 24 is in its &#34;H&#34; level, no output appears from the buffer gate 25--2. 
     Another control signal t 0  is applied directly to the OR gate 24 and buffer gates 25--3 to 25--6. When the control signal t 0  is in its &#34;H&#34; level, input signals u 1  and u 2  applied to the buffer gates 25--3 and 25--5 appear as output signals v 1  and v 2  respectively, while, when the control signal t 0  is in its &#34;L&#34; level, no outputs appear from these buffer gates 25--3 and 25--5. On the other hand, when the control signal t 0  is in its &#34;L&#34; level, input signals u 1  and u 2  applied to the buffer gates 25--4 and 25--6 appear as inverted output signals v 1  =u 1  and v 2  =u 2  respectively, while, when the control signal t 0  is in its &#34;H&#34; level, no outputs appear from these buffer gates 25--4 and 25--6. 
     Depending on whether reduced data are to be handled or data to be handled are applied from the row direction or column direction, the selector 5 selects the address values of y 0  =x 0  and z 0  =w 0  ; or y 0  =x 0  and z 0  =w 0  ; or y 0  =x 0  and z 0  =w 0  and applies such address values to the memories m 1  to m 8  shown in FIG. 7. 
     FIG. 11 shows in detail the structure of the selector 5. Referring to FIG. 11, the selector 5 includes an inverter gate 26, OR gates 27--1, 27--2 and buffer gates 28--1 to 28--4. The control signal t 0  is applied through the inverter gate 26 to the OR gate 27--1 and directly to the OR gate 27--2, while the control signal tl is applied directly to the OR gates 27--1 and 27--2. When the OR gate 27--2 generates its output signal of &#34;H&#34; level, an input signal x 0  applied to the buffer gate 28--1 appears as an output signal y 0 , while, when the output of the OR gate 27--2 is in its &#34;L&#34; level, no output appears from the buffer gate 28--1. On the other hand, when the OR gate 27--2 generates its output signal of &#34;L&#34; level, an input signal x 0  applied to the buffer gate 28--2 appears as an inverted output signal y 0  =x 0 , while, when the output of the OR gate 27--2 is in its &#34;H&#34; level, no output appears from the buffer gate 28--2. The buffer gates 28--3 and 28--4 are similar in operation to the buffer gates 28--1 and 28--2 respectively. 
     When data reduced to 1/2 of original data are read out, 8 data are arranged in a shuffled crder. An inverse shuffle circuit 6 is provided so that such 8 data arranged in the shuffled order can be re-arranged into the original order. In the read mode with data reduction, inverse-shuffled 8 data as shown in FIG. 12 appear from the inverse shuffle circuit 6. On the other hand, in the read mode without data reduction, non-inverse-shuffled 8 data appear at the output of the inverse shuffle circuit 6. 
     FIG. 13 shows in detail the structure of the inverse shuffle circuit 6. Referring to FIG. 13, the inverse shuffle circuit 6 includes buffer gates 29--1 to 29--16. When the control signal tl is in its &#34;H&#34; level, an input signal α 1  applied to the buffer gate 29--1 appears as an output signal β 1 , while, when the control signal t 1  is in its &#34;L&#34; level, no output appears from the buffer gate 29--1. On the other hand, when the control signal t 1  is in its &#34;L&#34; level, an input signal α 1  applied to the buffer gate 29--9 appears as an output signal β 1 , while, when the control signal t 1  is in its &#34;H&#34; level, no output appears from the buffer gate 29--9. Similarly, when the control signal t is in its &#34;H&#34; level, an input signal α 2  applied to the buffer gate 29--2 appears as an output signal β 2 , while, when the control signal t 1  is in its &#34;L&#34; level, no output appears from the buffer gate 29--2. On the other hand, when the control signal t 1  is in its &#34;L&#34; level, an input signal α 3  applied to the buffer gate 29--10 appears as an output signal β 2 , while, when the control signal t 1  is in its &#34;H&#34; level, no output appears from the buffer gate 29--10. The buffer gates 29--3 to 29--8 are similar in operation to the buffer gates 29--1 and 29--2. The buffer gates 29--11 to 29--16 are similar in operation to the buffer gates 29--9 and 29--10. 
     For example, when the control signal t 1  is in its &#34;H&#34; level, and the input signal train {α 1 , α 2 , α 3 , α 4 , α 5 , α 6 , α 7 , α 8  } applied to the inverse shuffle circuit 6 is represented by {a, e, b, f, c, g, d, h}, the output signal train {β 1 , β 2 , β 3 , β 4 , β 5 , β 6 , β 7 , β 8  } is represented by {a, e, b, f, c, g, d, h}. On the other hand, when the control signal t 1  is in its &#34;L&#34; level, and the input signal train {β 1 , α 2 , α 3 , α 4 , α 5 , α 6 , α 7 , α 8  } is represented by {a, e, b, f, c, g, d, h}, the output signal train {β 1 , β 2 , β 3 , β 4 , β 5 , β 6 , β 7 , β 8  } is now represented by {a, b, c, d, e, f, g, h} as shown in FIG. 12. 
     Suppose now that data of 8 bits in the row direction of each sub-block composed of 8×8 bits are arranged in order from the 1st to the 8th column, and data of 8 bits in the column direction are also arranged in order from the 1st to the 8th row. How to write data from the row direction in the block in such a case will be first described. 
     Input data of 8 bits are permutated in the data permutation circuit 2 depending on the positions of the data in the sub-blocks and the row numbers in the sub-blocks. The control signals s 0  to s 2  are applied to the data permutation circuit 2 so that, for the data belonging to the sub-blocks &lt;1, 1&gt; and &lt;2, 2&gt;, the input data are permutated by making sequential correspondence between the aforementioned permutations P 0 , P 1 , P 2 , . . . , P 7  orderly arranged from P 0  and the row numbers of the input data in the sub-blocks, while, for the data belonging to the sub-blocks &lt;1, 2&gt; and &lt;2, 1&gt;, the input data are permutated by making sequential correspondence between the re-arranged permutations P 1 , P 0 , P 3 , P 2 , P 5 , P 4 , P 7 , P 6  obtained by applying the permutation P 1  to the permutations P 0 , P 1 , P 2 , . . . , P 7  orderly arranged from P 0  and the row numbers of the input data in the sub-blocks. The data permutated in the data permutation circuit 2 are stored in the memories m 1  to m 8  in the permutated order. 
     The address inputs n 0  connected in common to all of the memories m 1  to m 8  specify the block and provide a fixed address value of data in the block. The address inputs a 0  to a 2  provide the address values u 0 , u 1  and u 2  respectively. The address values u 0  to u 2  are applied to the memory circuit 1 to specify that an address value given by u 2  u 1  u 0  =i-1 (a decimal representation of u 2  u 1  u 0 ) corresponds to data in an i-th row in the sub-blocks. Further, as each of the address values v 0  to v 2 , v j  =u j  (0≦j≦2) is supplied to the memory circuit 1 by applying the control signal t 0  of &#34;H&#34; level to the selector 4. 
     The address inputs b 0  and c 0  provide address values x 0  and w 0  respectively. Address values applied to the memory circuit 1 are x 0  =0, w 0  =0 for the sub-block &lt;1, 1&gt;; x 0  =1, w 0  =0 for the sub-block &lt;1, 2&gt;; x 0  =0, w 0  =1 for the sub-block &lt;2, 1&gt;; and x 0  =1, w 0  =1 for the sub-block &lt;2, 2&gt;. Further, as the address values y 0  and z 0 , y 0  =x 0  and z 0  =w 0  are applied to the memory circuit 1 by applying the control signal t 1  of &#34;H&#34; level to the selector 5. 
     The data in the block numbered in the manner shown in FIGS. 4 and 5 are stored in the memories m 1  to m 8  in a state as shown in FIG. 14. The addresses shown in FIG. 14 are specified by the less-significant 5 bits provided by the address inputs c 0 , b 0 , a 2 , a 1  and a 0 . 
     In the case of data writing from the column direction, input data of 8 bits are permutated in the data permutation circuit 2 depending on the positions of the data in the sub-blocks and the column numbers in the sub-blocks. As in the case of data writing from the row direction, the control signals s 0  to s 2  are applied to the data permutation circuit 2 so that, for the data belonging to the sub-blocks &lt;1, 1&gt; and &lt;2, 2&gt;, the input data are permutated by making sequential correspondence between the aforementioned permutations P 0 , P 1 , P 2 , . . . , P 7  orderly arranged from P 0  and the column numbers of the input data in the sub-blocks, while, for the data belonging to the sub-blocks &lt;1, 2&gt; and &lt;2, 1&gt;, the input data are permutated by making sequential correspondence between the permutations P 1 , P 0 , P 3 , P 2 , P 5 , P 4 , P 7 , P 6  attained by applying the permutation P 1  to the permutations P 0 , P 1 , P 2 , . . . , P 7  orderly arranged fro P 0  and the column numbers of the input data in the sub-blocks. The data permutated in the data permutation circuit 2 are stored in the memories m 1  to m 8  in the permutated order. The address values u 0  to u 2  provided by the address inputs a 0  to a 2  are applied to the memory circuit 1 to specify that an address value given by u 2  u 1  u 0  =i-1 (a decimal representation of u 2  u 1  u 0 ) corresponds to data in an i-th column in the sub-blocks &lt;1, 1&gt; and &lt;2, 2&gt;. In the case of the data belonging to the sub-blocks &lt;1, 2&gt; and &lt;2, 1&gt;, address values are permutated in the order of 1, 0, 3, 2, 5, 4, 7, 6 by applying the aforementioned permutation P 1  to 0, 1, 2, . . . 7 which are orderly arranged from 0 and which indicate decimal representations of u 2  u 1  u 0 . Such address values making sequential correspondence with the column numbers of the input data in the sub-blocks are applied to the memory circuit 1. Further, as each of the address values v 0  to v 2 , v j  =u j  (0≦j≦2) is applied to the memory circuit 1 by applying the control signal t 0  of &#34;L&#34; level to the selector 4. The other address values are the same as those described with reference to the case of data writing from the row direction. FIG. 15 shows the relation between the column numbers in the sub-blocks &lt;1, 1° to &lt;2, 2&gt; and the corresponding address values c 0  b 0  a 2  a 1  a 0  (decimal representations of c 0  b 0  a 2  a 1  a 0 ) applied to the memories m 1  to m 8 . Thus, when the data are stored in the memories in the manner above described in the case of data writing from the column direction, the data can be allocated and stored in the memories in entirely the same manner as the data allocation and storage shown in FIG. 14 representing the case of data writing from the row direction. 
     Description will now be directed to reading of data from the memories m 1  to m 8 . Suppose first the case where data of 8 bits arranged in the row direction are read out without any data reduction or in a standard mode. Since the data in the block shown in FIGS. 4 and 5 are stored as shown in FIG. 14, the manner of applying the address values to the memories m 1  to m 8  is the same as that of data writing from the row direction, thereby reading out the data from the memories m 1  to m 8 . 
     In the data read out from the memories m 1  to m 8 , the data arrangement has been changed as a result of data permutation depending on the sub-block number and the row number of the data in the sub-block. Therefore, the data are permutated into the original order in the data permutation circuit 3. When the data permutated according to the aforementioned permutation P k  (0≦k≦7) are subjected to the same permutation P k , the data arrangement is restored to the original arrangement (P k  ·P k  =P 0 ). Thus, the control signals s 0  to s 2  are applied to the data permutation circuit 3 so that, for the data belonging to the sub-blocks &lt;1, 1&gt; and &lt;2, 2°, sequential correspondence between the permutations P 0 , P 1 , P 2 , . . . , P 7  orderly arranged from P 0  and the row numbers of the read-out data in the sub-blocks can permutate the data into the original arrangement, while, for the data belonging to the sub-blocks &lt;1, 2° and &lt;2, 1&gt;, sequential correspondence between the permutations P 1 , P 0 , P 3 , P 2 , P 5 , P 4 , P 7 , P 6  arranged in the above order and the row numbers of the read-out data in the sub-blocks can permutate the data into the original arrangement. The output data from the data permutation circuit 3 appear intact through the inverse shuffle circuit 6. 
     Suppose then the case where data of 8 bits arranged in the column direction are read out without any data reduction or in a standard mode. The manner of applying address values to the memories m 1  to m 8  is to the same as that of data writing from the column direction, thereby reading out the data from the memories m 1  to m 8 . 
     In the data read out from the memories m 1  to m 8 , the data arrangement has been changed as a result of data permutation depending on the sub-block number and the column number of the data in the sub-block. Therefore, the data are permutated into the original order in the data permutation circuit 3. When the data permutated according to the aforementioned permutation P k  (0≦k≦7) are subjected to the same permutation P k , the data arrangement is restored to the original arrangement (P kl  ·P k  =P 0 ). Thus, the control signals s 0  to s 2  are applied to the data permutation circuit 3 so that, for the data belonging to the sub-blocks &lt;1, 1&gt; and &lt;2, 2&gt;, sequential correspondence between the permutations P 0 , P 1 , P 2 , . . . , P 7  orderly arranged from P 0  and the column numbers of the read-out data in the sub-blocks can permutate the data into the original arrangement, while, for the data belonging to the subblocks &lt;1, 2&gt; and &lt;2, 1°, sequential correspondence between the permutations P 1 , P 0 , P 3 , P 2 , P 5 , P 4 , P 7 , P 6  arranged in the above order and the column numbers of the read-out data in the sub-blocks can permutate the data into the original arrangement. The output data from the data permutation circuit 3 appear intact through the inverse shuffle circuit 6. 
     Suppose then the case where data of 8 bits arranged in the row direction are read out with a data reduction rate of 1/2, that is, for example, the oddnumbered data in each row are read out. The address inputs n 0  connected in common to all of the memories m 1  to m 8  specify the block and provide a fixed address value in the block. The address values u 0  to u 2  provided by the address inputs a 0  to a 2  are applied to the memory circuit 1 to specify that an address value given by u 2  u 1  u 0  =i 0  (a decimal representation of u 2  u 1  u 0 , i 0  : remainder of division of i-1 by 8) corresponds to data in an i-th row (1≦i≦16) in the block. Further, as each of address values v 0  to v 2 , v j  =u j  (0≦j≦2) is supplied to the memory circuit 1, while applying the control signal t 0  of &#34;H&#34; level to the selector 4. 
     The address inputs b 0  and c 0  provide address values x 0  and w 0  respectively. Address values applied to the memory circuit 1 are x 0  =0, w 0  =0 for reading out the data in the odd-numbered rows between the 1st and 8th rows in the block; x 0  =1, w 0  =0 for reading out the data in the even-numbered rows between the 1st and 8th rows in the block; x 0  =1, w 0  =1 for reading out the data in the odd-numbered rows between the 9th and 16th rows in the block; and x 0  =0, w 0  =1 for reading out the data in the even-numbered rows between the 9th and 16th rows in the block. The control signal t 0  applied to the selector 5 is in its &#34;H&#34; level, since the control signal t 0  applied to the selector 4 is in its &#34;H&#34; level. As addresses values values y 0  and z 0 , y 0  =x 0  and z 0  =w 0  are applied to the memory circuit 1 while applying the control signal t 1  to &#34;L&#34; level. FIG. 16 shows the address values c 0  b 0  a 2  a 1  a 0  (decimal representations of c 0  b 0  a 2  a 1  a 0 ) applied to the memories m 1  to m 8  when the odd-numbered data in each row are extracted to read out data of 8 bits reduced with the data reduction rate of 1/2. 
     The data read out from the memories m 1  to m 8  are permutated in the data permutation circuit 3 according to the row number in the block. The control signals s 0  to s 2  are applied to the data permutation circuit 3 so that the lst and 10th rows in the block shown in FIG. 16 correspond to the permutation P 0  ; the 2nd and 9th rows correspond to the permutation P 1  ; the 3rd and 12th rows correspond to the permutation P 2  ; the 4th and 11th rows correspond to the permutation P 3  ; the 5th and 14th rows correspond to the permutation P 4  ; the 6th and 13th rows correspond to the permutation P 5  ; the 7th and 16th rows correspond to the permutation P 6  ; and the 8th and 15th rows correspond to the permutation P 7 . FIG. 17 shows the data of 8 bits provided as a result of extraction of the odd-numbered data in the individual rows, hence, as a result of reduction of the data with the data reduction rate of 1/2 and shows also the.data permutated in the data permutation circuit 3. 
     The control signal t 1  applied to the inverse shuffer circuit 6 is in the &#34;L&#34; level which is the same as that applied to the selector 5, and the output data from the inverse shuffle circuit 6 are inverse shuffled as shown in FIG. 12. In the manner described above, extracted odd-numbered data of 8 bits appear from the frame inverse shuffle circuit 6. 
     Suppose then the case where data of 8 bits arranged in the column direction are read out with a data reduction rate of 1/2, that is, for example, the odd-numbered data in each column are read out. The address inputs n 0  connected in common to all of the memories m 1  to m 8  specify the block and provide a fixed address value in the block. The address values u 0  to u 2  provided by the address inputs a 0  to a 2  are applied to the memory circuit 1 to specify that an address value given by u 2  u 1  u 0  =2 * [(i-1)/2] (a decimal representation of u 2  u 1  u 0 , [A]: a maximum integer not larger than A) corresponds to data in an i-th row (1≦i≦16) in the block. Further, as address values v 0  to v 2 , v 0  =u 0 , v 1  =u 0  and v 2  =u 2  are applied to the memory circuit 1 while applying the control signal t 0  of &#34;L&#34; level and control signal t 1  of &#34;L&#34; level to the selector 4. 
     The address inputs b 0  and c 0  provide address values x 0  and w 0  respectively. Address values applied to the memory circuit 1 are x 0  =0, w 0  =0 for reading out the data in the odd-numbered rows between the 1st and 8th rows in the block; x 0  =0, w 0  =1 for reading out the data in the even-numbered rows between the 1st and 8th rows in the block; x 0  =1, w 0  =1 for reading out the data in the odd-numbered rows between the 9th and 16th rows in the block; and x 0  =1, w 0  =0 for reading out the data in the even-numbered rows between the 9th and 16th rows in the block. The control signals t 0  of &#34;L&#34; level and t 1  to &#34;L&#34; level applied to the selector 4 are also applied to the seclector 5. As address values y 0  and z.sub. 0, y 0  =x 0  and z 0  =w 0  are applied to the memory circuit 1. FIG. 18 shows the address value c 0  b 0  a 2  a 1  a 0  (decimal representations of c 0  b 0  a 2  a 1  a 0 ) applied to the memories m 1  to m 8  when the odd-numbered data in each column are extracted to read out data of 8 bits reduced with the data reduction rate of 1/2. 
     The data read out from the memories m 1  to m 8   are permutated in the data permutation circuit 3 according to the column number in the block. The control signals s 0  to s 2  are applied to the data permutation circuit 3 so that the 1st and 10th columns in the block shown in FIG. 18 correspond to the permutation P 0  ; the 2nd and 9th columns correspond to the permutation P 1  ; the 3rd and 12th columns correspond to the permutation P 2  ; the 4th and 11th columns correspond to the permutation P 3  ; the 5th and 14th columns correspond to the permutation P 4  ; the 6th and 13th columns correspond to the permutation P 5  ; the 7th and 16th columns correspond to the permutation P 6  ; and the 8th and 15th columns correspond to the permutation P 7 . FIG. 19 shows the data of 8 bits provided as a result of extraction of the odd-numbered data in the individual columns, hence, as a result of reduction of the data with the data reduction rate of 1/2 and shows also the data permutated in the data permutation circuit 3. 
     The control signal t 1  applied to the inverse shuffle circuit 6 is in its &#34;L&#34; level which is the same as that applied to the selector 4, and the output data from the inverse shuffle circuit 6 are inverse shuffled as shown in FIG. 12. In the manner described above, extracted odd-numbered data of a bits appear from the inverse shuffle circuit 6. 
     Writing of data from the row direction, writing of data from the column direction, standard reading of data and 1/2-reduced reading of data can be carried out in 8-bit parallel relation in the manner described above. 
     In the aforementioned embodiment of the present invention, odd-numbered data are read out when data are extracted with the data reduction rate of 1/2. However, even-numbered data can be similarly extracted by changing the address values applied to the memory circuit 1. 
     When it is desired to write and read all the data in 8-bit parallel relation at the same processing speed from both the row direction and column direction, all the data are preferably divided into blocks of 16×16 bits having 16 bits in each of the row and column directions, and the operation described with reference to the aforementioned embodiment is preferably carried out for each of the blocks. 
     Reading of data with a data reduction rate of 1/2 h (h≦2) can be similarly attained utilizing an expansion of the principle of the operation described with reference to the aforementioned embodiment.