Abstract:
A method of preventing formation of stringers adjacent a side of a CMOS gate stack during the deposition of mask and poly layers for the formation of a base and emitter of a bi-polar device on a CMOS integrated circuit wafer. The stringers are formed by incomplete removal of a hard mask layer over an emitter poly layer over a nitride mask layer. The method includes overetching the hard mask layer with a first etchant having a higher selectivity for the emitter poly material than for the material of the hard mask, determining an end point for the overetching step by detection of nitride in the etchant and applying a poly etchant that is selective with respect to nitride to remove any residual emitter poly.

Description:
The present invention relates to manufacturing processes for semiconductor integrated circuits and more particularly to a method for preventing the formation of silicon dioxide and silicon oxi-nitride stringers during formation of a bi-polar base and emitter structure in BiCMOS processing. 
   BACKGROUND OF THE INVENTION 
   In the manufacture of vertical bipolar transistors in a BiCMOS integrated circuit, Typically, the emitter of the bi-polar device is formed after certain CMOS type devices have been created. Accordingly, the one or more layers with which the emitter are formed overlay the prior created CMOS devices, such as, for example, a gate stack formed over a drain and source region. Exemplary descriptions of the various processes for forming a BiCMOS device and the various steps in its manufacture are disclosed in U.S. Pat. Nos. 6,359,317; 6,797,580 and 5,422,290 which are incorporated herein by reference. A typical manufacturing sequence involves the deposition of an oxide layer, followed by depositing a polysilicon layer, then a hard mask layer such as silicon nitride and an overlayer such as a TEOS deposited silicon oxide. Then photoresist is deposited and patterned to define an emitter window. Following nitride spacer formation and selective growth of a SiGe base, a silicon nitride is deposited and etched to form a second nitride spacer. Subsequently, a layer of doped polysilicon is deposited to form the emitter. Another hard mask layer may then be deposited over the polysilicon layer followed by a photoresist mask. At this point, the process involves systematic removal of the layers of material over the surface of the wafer other than the regions in which the bi-polar devices are formed, e.g., the CMOS regions. 
   One result of the above described deposition sequence is that the layers of deposited material create a surface that is not flat, i.e., because the surface may have various vertically extending features such as a CMOS gate stack. As subsequent layers are formed above the semiconductor wafer, they extend over these vertically oriented features and appear as sidewall layers along the sides of the devices. Quite often, these sidewalls, when measured perpendicularly to the wafer surface, are thicker than the layers along relatively flat surface regions of the wafer. As a result, when the layers are later removed, the process of removal for each layer may terminate before the vertically formed layer is completely removed. These remaining portions are typically referred to as stringers and have required additional processing for their removal thus contributing to a slower throughput in wafer processing. 
   Commonly, stringers that are left after formation of the bi-polar emitter and removal of the unused portions of the deposited layer may be formed of SiO 2  (silicon dioxide) and SiO x N y  (silicon oxi-nitride). In the past, removal of the SiO 2  and SiO x N y  stringers on or near the vertical sidewalls of a CMOS gate structure has been effected by overetching during hard mask removal to selectively remove the stringers. The overetching should avoid significant etching into the polysilicon layer that is used to form the bi-polar device emitter. The emitter is then defined using an etch chemistry which is selective with respect to SiO 2 . This limits the amount of silicon dioxide stringer removal. The combination of the hard mask etch and emitter etch, is self limiting with regard to the amount of stringer that can be removed. More particularly, the hard mask etch is limited by the process selectivity of silicon oxide to polysilicon while the poly emitter etch is typically selective toward silicon dioxide, only removing a limited amount of the stringer left over from the hard mask etch step. As a result, some bumps and/or stringers are left after etching, particularly in the tight spaces of the CMOS gate stack. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a representation of a cross-section of a CMOS gate stack after a prior art etch; 
       FIG. 2  is a cross-sectional representation of a BiCMOS structure prior to deposition of layers for the bi-polar device; 
       FIG. 3  shows the structure of  FIG. 2  after deposition of a TEOS layer; 
       FIG. 4  shows the structure of  FIG. 3  after deposition of a nitride layer and second TEOS layer; 
       FIG. 5  shows the structure of  FIG. 4  following an initial etch and base growth; 
       FIG. 6  shows the structure of  FIG. 5  following a nitride etch; 
       FIG. 7  shows the structure of  FIG. 6  following deposition of a TEOS layer and another nitride layer; 
       FIG. 8  shows the structure of  FIG. 7  following an etch process to remove the last deposited nitride layer and TEOS layer to provide sidewall protection; 
       FIG. 9  illustrates the end product of the inventive process with formation of stringers being inhibited. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Referring first to  FIG. 1 , there is shown a schematic representation of a cross-sectional view of a CMOS gate stack  10  on a substrate  12  after deposition of various layers of oxide, nitride and poly to create a base-emitter structure for a bi-polar device on an integrated circuit wafer designed for and containing a plurality of CMOS devices. In this simplified view, an oxide layer  14  extends over the gate stack  10  and is covered by a base poly layer  16 . A silicon nitride layer  18  can also be seen on the poly layer  16 . The cross-section of  FIG. 1  is taken subsequent to a conventional poly emitted etch process. What is noticeable about this view is the formation of bumps or stringers  20  on each side of the gate stack  10 . These stringers  20  are formed as a result of the prior etch steps not be effective in completely removing the vertically extending portions of the various mask and poly layers during the etch processes. As will become apparent, applicants&#39; inventive processes remove the vertical sidewall formations and prevent the formation of such stringers. 
   Creation of a bi-polar device in a CMOS structure and elimination of stringers will be better understood from the following description of  FIGS. 2-9 . Considering  FIG. 2 , there is shown a partial cross-sectional illustration of a wafer structure  22  having a substrate  24  in which have been formed by means well known in the art a collector region  26  for a bi-polar device and a source and a drain region  28  for a CMOS device  32 . A gate stack for the CMOS device is indicated at  34 . At this stage of formation, only an initial oxide layer  36  of TEOS (tetraethylorthosilicate) typically about 180 Å in thickness has been deposited on the substrate  24  and does not cover the CMOS gate stack  34 . In  FIG. 3 , an additional TEOS spacer layer  38  has been deposited over the wafer surface, including the gate stack  34 , and an amorphous silicon poly layer  40  is deposited over the spacer layer  38 . The layer  40  is commonly referred to as the base poly layer. 
   In  FIG. 4 , a silicon nitride layer  42  (typically, Si3N4,) has been deposited over the base poly layer  40 . The nitride layer  42  is typically about 1800 Å and is then covered by another TEOS layer  44  of about 180 Å thickness. The surface is then covered with photoresist  45  and exposed through a mask in preparation for forming the emitter window  46 . Once the window  46  has been etched, the photoresist is removed and another silicon nitride layer  48  is deposited over the TEOS layer  44  and into the window  46  as shown in  FIG. 5 . The layer  48  is used to provide sidewall masking within the window  44  and is much thinner than the layer  42 , generally about 400 Å. The layer  48  is then etched from the wafer surface down to the TEOS layer  44 , leaving a thin nitride layer protecting the inner sidewalls of the window  46 . At this time, the base  50  for the bi-polar device is epitaxially grown in the window  46 , extending into the TEOS layers  36 , 38  under the poly base layer  40  as shown in  FIGS. 5 and 6 .  FIG. 6  shows the initial sidewall formation within the window  46  after etching and removal of the nitride layer  48 . Following formation of the base  50 , another TEOS layer  52  is deposited over the nitride layer  42  and another silicon nitride layer  54  is deposited over the TEOS layer  52  resulting in the structure as shown in  FIG. 7 . This nitride layer  54  is then removed by plasma etching followed by removal of the TEOS layer  52 . The result is to create a sidewall barrier within window  46  that comprises a pair of nitride layers spaced by a TEOS layer as shown in  FIG. 8 , which Fig. also shows the emitter poly layer  56 . Layer  56  is a doped poly deposited using conventional techniques. 
   At this time in the process, the bi-polar device has been completed and it is now necessary to remove all the deposited layers from the other surfaces of the wafer without disturbing the formed base-emitter stack for the bi-polar device. The first step to protect the device is to deposit a hard mask layer  58 , typically USG (undoped silica glass), over the wafer followed by coverage with photoresist. Using standard photoresist processes, the bi-polar device is protected as shown in  FIG. 8 . In this final form, it can be seen that the various layers have segments at  60 ,  62  that extend away from the plane of the wafer surface  64  as the layers pass over such elements on the surface as the gate stack  34 . Considering the wafer surface as lying in a horizontal plane, the vertically extending segments  60 ,  62  have a thickness in the vertical direction that is substantially greater than the thickness of the layers lying on the horizontal wafer surface. Consequently, when etching is performed, the horizontal portion of a layer will be removed prior to the time that the vertical segments are removed. The failure to remove these vertical segments results in the formation of the stringers  20  that were illustrated in  FIG. 1 . Accordingly, applicants&#39; inventive process is directed to complete removal of these vertical segments in order to prevent the formation of such stringers. 
   The first etch step removes the USG hard mask  58  from all areas except over the bi-polar emitter stack that is protected by the PR layer  66 . The conventional etching process for the removal of the hard mask layer  58  uses a plasma etchant mixture of CHF 3  and CF 4  (a carbon/flouride plasma with high Carbon to Flourine ratio) that is selective to the poly of layer  56 . CHF 3  is sometimes referred to as flouroform while CF 4  is sometimes referred to as fluorocarbon. Once the mask layer  58  is removed, the conventional process switches to a poly etch process using a different etchant typically in a different tool. This requires removing the wafer from one tool and placing it in another and consumes valuable process time. Applicants have found that the SiO 2  plasma etch chemistry can be used to etch the poly layer. More particularly, applicants have found that the SiO 2  plasma etching chemistry etches the sidewalls or segments  60 ,  62  formed by the oxide layer  58  adjacent perpendicular structures, such as the CMOS gate stack  34 , from 3 to 5 times faster than the poly layer  56  so that when the poly layer etching is completed, the sidewalls  60 ,  62  of USG have been etched 3 to 5 times the height of the poly layer. In practice, the inventive etch step may be carried out as part of an in situ etch process in which a poly emitter hard mask and antireflective coating (ARC) layers, a poly emitter and a base isolation nitride layer are all etched. In addition, the hard mask photoresist  66  is removed during the process. 
   In practicing the etch process as taught by applicants, the USG layer  58 , which is chemically SiO 2 , is removed using a mixture of CF4 and CHF3, where the ratio of CHF3 to CF4 is chosen to provide a desired selectivity of the oxide to the polysilicon layer  56 . The typical chemistry can be expressed as SiO 2 +CF 4 +CHF3→SiF 4 +HF+CO 2 . Complete removal of the oxide layer  58  can be detected using conventional end point detection of CO 2 , i.e., the lack of CO 2  in the effluent from the plasma etch indicates that the oxide layer has been exhausted. In the inventive process, the fluorocarbon plasma is continued and used to remove the poly layer. While this etch process using the oxide etch plasma may not be as efficient as a conventional poly etch process, the oxide etch plasma will effectively remove the poly, although at a slower etch rate than for the oxide. However, the advantage of this inventive process is that it gives the etchant time to completely remove the oxide at segments  60 , 62  that have been the cause for stringer formation in conventional etch processes. 
   The invention uses the hard mask etch chemistry having from 3:1 to 5:1 SiO 2  to emitter poly selectivity. However, instead of doing a conventional amount of etching needed for this process, the invention uses essentially a 200% over etch combined with endpoint detection to etch all the poly emitter layer. More particularly, an endpoint for the oxide plasma etch can be detected by monitoring for cyanide (CN) in the effluent from the etch tool, i.e., when the fluorocarbon plasma reaches the nitride layer  42  which is generally Si 3 N 4 , the carbon ions will bond with nitrogen ions to create cyanide. 
   In a typical structure, the poly emitter layer is about 2000 angstroms thick while the CMOS gate stack is about 5000 angstroms high. To remove the stringers along the side of the gate stack requires removing the 5000 angstroms of SiO 2  when the 2000 angstroms of poly emitter layer is removed. This requires about a 3:1 selectivity of SiO 2  to polysilicon to make sure that the full height of the stringers is removed when the poly emitter etch is complete. 
   After removal of the poly with the oxide etch, a poly over etch can then be performed to make sure that there are no residuals on the wafer surface or gate stack sidewalls. The poly over etch is performed with a conventional poly etch process and chemistry which is selective to oxide and nitride, i.e., it does not remove the oxide or nitride and, if such layer segments were not removed by another etch process, would result in the creation of the stringers. The poly overetch is typically a timed etch since it does not effect the nitride layer. The time can be set long enough to assure that any poly stringers are removed before proceeding to a nitride etch process. One of the advantages of the present invention is that the chemistry for both the oxide etch and poly etch can be carried out in the same tool so that the wafer does not have to be removed until these first two processes are completed. In the manufacturing process, once the oxide and poly have been removed, the wafer can be transferred to another tool for nitride etch using conventional processes and endpoint detection such as the absence of cyanide in the effluent. An in-situ process to selectively remove this nitride layer over the base poly could be used to further simplify the manufacturing process. 
   By way of example, for an etch process of a wafer having the parameters set forth above, i.e., emitter poly of about 2000 Angstroms, the process parameters are as follows: 
   
     
       
             
             
           
             
             
             
             
             
             
           
         
             
                 
             
             
                 
               SiO 2  Type Chemistry for Poly 
             
             
               Typical Poly Etch Chemistry 
               Emitter Etch 
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               Source Power: 
               200 
               watts 
                 
               700 
               watts 
             
             
               Bias Power: 
               40 
               watts 
                 
               120 
               watts 
             
             
               Pressure: 
               5 
               mtorr 
                 
               6 
               mtorr 
             
             
               HBr flow: 
               60 
               sccm 
               CHF3 flow: 
               60 
               sccm 
             
             
               He/30% O 2  flow: 
               10 
               sccm 
               CF4 flow: 
               20 
               sccm 
             
             
                 
                 
                 
               Ar flow: 
               10 
               sccm 
             
             
                 
             
           
        
       
     
   
   Using the etch process described herein for the removal of stringers on a BiCMOS gate stack assures complete removal of the stringers and improves device yield. In a typical application for the illustrative bi-polar device, the oxide etch takes approximately 80 seconds while removal of the poly layer takes about another 150 seconds with the SiO 2  etch chemistry. The final poly etch using poly etch chemistry takes about another 85 seconds. These times are only illustrative and will vary with the chemistry and physical settings in the tool and the thickness of the layers. 
     FIG. 9  illustrates the end point for the illustrative process set forth above showing that the bi-polar device has been completed and the gate stack  34  is finished without formation of stringers. 
   As noted above, the advantages of the inventive process are that the oxide hard mask and poly layers may both be removed in the same tool and the stringers are removed during the etch process without having to make adjustments after removal of the poly. Further, while the examples given are for the purpose of explaining the invention, it will be recognized that the etch chemistry may be varied to achieve different results or to etch layers having different elements. 
   While the invention has been described in what is presently considered to be a preferred embodiment, various modifications and improvements will become apparent to those skilled in the art. It is intended therefore that the invention not be limited to the specific disclosed embodiment but be interpreted within the full spirit and scope of the appended claims.