Abstract:
A method for determining the capacitance of an analog/mixed signal circuit, comprising the steps of (A) acquiring a capacitance at a plurality of different input slope rates, (B) verifying each acquired capacitance, (C) determining an average capacitance of said plurality of different input slope rates over a partial average range and (D) determining an accuracy of the capacitance.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method and/or software for accurate capacitance acquisition generally and, more particularly, to a method and/or software for determining the capacitance of an analog/mixed signal circuit. 
     BACKGROUND OF THE INVENTION 
     There are several conventional methods for CMOS cell input pin capacitance acquisition. Bipolar junction transistor BJT-CML technology requires additional special characteristics in order to determine the capacitance. The characteristics for determining the capacitance in BJT-CML technology is not clear. The conventional methods for CMOS cell capacitance acquisition is not suitable for BJT-CML cell capacitance acquisition. Currently, conventional approaches are not available for BJT-CML cell input pin capacitance acquisition. 
     Referring to FIG.1, a conventional circuit  10  that is used for pin capacitance acquisition is shown. The voltages across the pin capacitance are defined by the following equation EQ1: 
       v=V (1 −e   −t/RC )  EQ1 
     By definition, the RC time constant τ is the product of R and C and is defined by the following equation EQ2: 
     
       
         τ= RC   EQ2 
       
     
     At time t=τ the voltage v is defined by the following equation EQ3: 
     
       
           v=V (1 −e   −t/RC )=0.63 V   EQ3 
       
     
     Using a known value of R and measuring the value of t at which the charging voltage v is 0.63 V, the pin capacitance is found by the following equation EQ4: 
     
       
           C=t/R   EQ4 
       
     
     Referring to FIG. 2, a graph illustrating voltage versus time of the circuit  10 . The circuit  10  is sensitive to the value of R. The acquired capacitance by this method for the same pin could have 100% to 1000% variation with different values R. 
     Another conventional method for CMOS cell capacitance acquisition, a so-called an imaginary current method, may be defined by the following equations: 
       V/l   m =1/( WC ) 
     
       
           W =2 πf   
       
     
     
       
           C=l   m /(2 πfV ) (when  V =1 v ) 
       
     
     
       
         = l   m /(2 πf ) 
       
     
     Using a known value of stimulus frequency f, and measuring the value of imaginary current l m , the pin capacitance can be acquired. However, the imaginary current method is very sensitive to the choice of the stimulus frequency f. The acquired capacitance by this method for the same pin could have up to 1000% variation based on different values of the stimulus frequency f. 
     Another conventional approach for CMOS cell capacitance acquisition, a so-called impedance method, may be defined by the following equations: 
     
       
           Z =( R   2 +( WC ) −2 ) ½   
       
     
     
       
           Z   2   =R   2 +( WC ) −2 ( W =2 πf ) 
       
     
     
       
           C   2 =(1/(2 πf·Z )) 2 ·(( WCR ) 2 +1) 
       
     
     
       
         tan φ=(1/( WCR )) 
       
     
     
       
           C =(1/(2 πf·Z ))·((tan φ) −2 +1) ½   
       
     
     When R is small, WCR&lt;&lt;1, 
     
       
           C =(1/(2 πf·Z )) 
       
     
     
       
         
           Z=V 
           rms 
           /l 
           rms 
         
       
     
     Using a known value for the stimulus frequency f, and measuring the value of V rms  and l rms , the pin capacitance can be acquired. The impedance method is also very sensitive to the choice of the stimulus frequency f. The acquired capacitance calculated by the impedance method for the same pin could have up to 1000% variation based on different values of f. 
     Another conventional method for CMOS cell capacitance acquisition is a so-called I/(DV/DT) method. By definition, capacitance C is defined by the following equation: 
     
       
         
           C=dQ/dV 
         
       
     
     On the other hand, 
     
       
         
           dQ=I·dt 
         
       
     
     
       
         
           dQ=C·dV=I·dt 
         
       
     
     
       
           C=I /( dV/dt ) 
       
     
     where V is input stimulus voltage. If a linear source voltage is used, dV/dt is a constant. 
     
       
         
           K=dV/dt 
         
       
     
     
       
         
           C=I/K 
         
       
     
     Take average in the range T, 
     
       
         (∫ o   T   Cdt )/ T =((∫ o   T   Idt )/ T )·(1 /K ) 
       
     
     
       
         Avg( C )=Avg( I )/ K   
       
     
     Measure Avg(I)→Avg(C)→C 
     FIG. 3 is a graph illustrating voltage as an input and current as an output, each versus time for the I/(DV/DT) method. The I/(DV/DT) method is still sensitive to input slope rate K for analog signals (BJT-CML), but may provide better tolerance (e.g., −50% to 50%) than other conventional methods. 
     None of the conventional methods described is targeted to bi-cmos technology. Additionally, the conventional methods described are not normally accurate enough for input pin capacitance acquisition. 
     SUMMARY OF THE INVENTION 
     The present invention concerns a method for determining the capacitance of an analog/mixed signal circuit, comprising the steps of (A) acquiring a capacitance at a plurality of different input slope rates, (B) verifying each acquired capacitance, (C) determining an average capacitance of said plurality of different input slope rates over a partial average range and (D) determining an accuracy of the capacitance. 
     The objects, features and advantages of the present invention include providing a method and/or software that may allow for (i) capacitance acquisition of BJT-CML cells, and/or (ii) characterization of a BJT-CML cell library. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a conventional circuit for CMOS cell input capacitance acquisition; 
     FIG. 2 is a graph of voltage versus time of the circuit of FIG. 1; 
     FIG. 3 is a graph of voltage as an input and current as an output, each versus time of another conventional circuit for CMOS cell input capacitance; 
     FIGS.  4 ( a )-( b ) are circuit diagrams illustrating a context for a preferred embodiment of the present invention; 
     FIG. 5 is a graph of voltage as an input and current as an output, each versus time of the circuits of FIGS.  4 ( a )-( b ); 
     FIG. 6 is a flow diagram illustrating the operation of the circuit of FIG. 4; and 
     FIG. 7 is a diagram illustrating an implementation of the present invention in the context of an integrated circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIGS. 4 a  and  4   b , block diagrams of a circuit  100   a  and a circuit  100   b  are shown in accordance with a preferred embodiment of the present invention. 
     In general, a partial T average range performs better than the T average range described in connection with FIG.  3 . In one example, the partial T average range may be a ½T range. However, other partial T averages, such as greater than ½T, or more preferably greater than ½T and less than T, may be selected accordingly to meet the design criteria of a particular implementation. For example, a ½T, ¾T, 3/5T (½T+a fraction less than ½), etc. may each be implemented in accordance with the present invention. A passive load capacitance Ca from FIG. 4A is generally used to verify an active load capacitance Cb from FIG. 4 b . The partial T average range results may be better than the results of T average range as defined by the following equation EQ5: 
     
       
         Avg( l )=(∫ o   ½T   ldt )/½ T   EQ5 
       
     
     In general, the relative error for the acquired capacitance using the present invention is in the range −20% to 20%. 
     The present invention may still be sensitive to input slope rate K. As a result, the present invention may also provide analysis of a wide variety of ranges. All the capacitances Cb acquired at the M different slope rates K are generally verified with a passive load in the whole input slope range, after which the N best values of capacitance are selected. 
     The following steps outline the general operation of the present invention: 
     1. Capacitance Cb acquisition at M input slope rates. 
     Input slope sweeps m points (i.e., 0.05e-09, 0.2e-09, 0.5e-09, 1.0e-09, 2.0e-09, 3.0e-09, etc. dv/dt). M capacitances Cb may be acquired in M simulations. 
     2. Verifying each acquired capacitance Cb with N input slope rates applied to M passive capacitances Ca. 
     The delays (e.g., DELAY −passive ) from the M·N passive load simulations of FIG. 4 a  are compared with an additional N delays (e.g., DELAY −active ) from the active load simulations of FIG. 4 b . Totally, M·N+N simulations may be performed at the N input slope rates. 
     Delay −active -Delay −passive )/Delay −active  is the criteria to pick up the N best capacitances. At each of the N input slope rates, a Delay −passive  may be picked to make the criteria smallest. 
     3. Taking an average. Then take an average of the N capacitances associated with the N picked delays: 
     
       
         Avg( C )=( C   1   +C   2   +···+C   n )/ N.   
       
     
     Checking the above relative delay criteria at each of the N input slope rates based on the average capacitance Avg(C). In most cases, the average variance is less than 5%. 
     The modified I/(dv/dt) method of the present invention (e.g., ½T average range method) may provide a suitable method for BJT-CML cell input pin capacitance acquisition among the above four methods. The relative variance based on the acquired capacitance for this method is about 5%. 
     Referring to FIG. 5, a graph (or plot) of voltage as an input and current as an output, both versus time, is shown. In general, the plot shows an average that somewhat approximates the straight line  120 . 
     Referring to FIG. 6, a flow diagram illustrating the operation of the present invention is shown. The flow diagram  200  generally comprises an acquiring step  202 , a verifying step  204 , an averaging step  206 , a double checking step  208  and an accuracy check step  210 . Provided the accuracy check is within tolerance, the method  200  proceeds to the final step  212 . If the accuracy is not within tolerances, the method changes the value of M and returns to the acquiring step  202 . In general, the acquiring step  202  acquires the capacitances Cb at M different slope rates (e.g., dv/dt). The verifying step  204  generally acquires a delay at N different slope rates for each of the M capacitances. The verifying step also picks the best delay value and associated capacitance at each of the N input slope rates. The averaging step  206  generally takes the average of the best values of capacitance divided by N. The double checking step  208  verifies the average capacitance. 
     The function performed by the flow diagram of FIG. 6 may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). 
     The present invention may also be implemented by the preparation of ASICs, FPGAs, or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
     The present invention thus may also include a computer product which may be a storage medium including instructions which can be used to program a computer to perform a process in accordance with the present invention. The storage medium can include, but is not limited to, any type of disk including floppy disk, optical disk, CD-ROM, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions. 
     Referring to FIG. 7, a diagram illustrating an implementation of the present invention in the context of an integrated circuit  300  is shown. The integrated circuit  300  is shown having a pin (e.g., PIN_ 1 ) that may be connected to the circuit  100 . The circuit  100  may be used to determine the capacitance of the pin PIN_ 1 . 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.