Abstract:
PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a Phase/Frequency Detector (PFD), and more particularly, to a PFD with precise phase determination. 
   2. Description of the Prior Art 
   Generally, the Phase Locked Loop (PLL) comprises a PFD, a voltage controller, and a Voltage Control Oscillator (VCO). The VCO generates a clock signal according to a voltage V X , and feeds the clock signal back to the PFD. The PFD compares the phase of the fed-back clock signal with the phase of a reference clock signal. If the phase of the reference clock signal is ahead of the phase of the fed-back clock signal, the PFD outputs a rising signal (UP) S UP  to the voltage controller for pulling up the voltage V X  so as to increase the frequency of the fed-back clock signal. If the phase of the reference clock signal falls behind the phase of the fed-back clock signal, the PFD outputs a falling signal (DOWN) S DN  to the voltage controller for pulling down the voltage V X  so as to decrease the frequency of the fed-back clock signal. 
   Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional PFD  100 . As shown in  FIG. 1 , the PFD comprises two flip-flops  1  and  2 , and a NAND gate  3 . The flip-flops  1  and  2  receive the reference clock signal CLK REF  and the fed-back clock signal CLK FB , respectively, and output the rising signal S UP  and the falling signal S DN , respectively. The two input ends of the NAND gate  3  receive the rising signal S UP  and the falling signal S DN , respectively, and a reset signal S RESET  is generated accordingly in order to reset the flip-flops  1  and  2 . 
   Please refer to  FIG. 2 .  FIG. 2  is a timing diagram illustrating the operation of the PFD  100 . As shown in  FIG. 2 , when the first rising edge E REF1  of the reference clock signal CLK REF  inputs to the flip-flop  1 , after a delay period T D1 , the rising signal S UP  is pulled up to be logic “1”; when the first rising edge E FB1  of the fed-back clock signal CLK FB  inputs to the flip-flop  2 , after the delay period T D1 , the falling signal S DN  is pulled up to be logic “1”. When both of the signals S UP  and S DN  are logic “1”, after a delay period T D2 , the reset signal S RESET  is triggered to reset the flip-flops  1  and  2 . The shortest period of the reset signal S RESET  is T RESET  because of the delay. Consequently, when the phases of the reference clock signal CLK REF  and the fed-back clock signal CLK FB  are too close, the conventional PFD  100  tends to determine incorrectly. As shown in  FIG. 2 , the phase of the reference clock signal CLK REF  is ahead of the phase of the fed-back clock signal CLK FB . However, since the period of the reset signal S RESET  is so long that the second rising edge E REF2  of the reference clock signal CLK REF  is ignored, causing that the PFD  100 , in the next time, determines the phase of the fed-back clock signal CLK FB  is ahead of the reference clock signal CLK REF , which is incorrect. More particularly, in  FIG. 2 , the phase of the reference clock signal CLK REF  is ahead of the fed-back clock signal CLK FB , so that the frequency of the fed-back clock signal CLK FB  should be increased. However, it is shown in  FIG. 2  that the rising signal S UP , triggered by the rising edge E REF3 , has shorter period than the falling signal S DN , triggered by the rising edge E FB2 , which is, the voltage V X  is pulled down. That means the frequency of the fed-back signal CLK FB  is decreased instead. Thus, the conventional PFD  100 , is limited by the period of the reset signal S RESET , and tends to lock the phase of the fed-back signal in an incorrect direction. 
   Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating the relationship between the phase difference and the output voltage of the PLL utilising the conventional PFD  100 . It is assumed that the clock of the reference clock signal CLK REF  is T. As shown in  FIG. 3 , when the phase of the reference clock signal CLK REF  is ahead of the fed-back clock signal CLK FB  by the range from 0 to (T RESET /T), the output voltage of the voltage controller of the PLL keeps rising and positive. That is, the frequency of the fed-back clock signal CLK FB  would be increased. However, when the phase of the reference clock signal CLK REF  is ahead of the fed-back clock signal CLK FB  by the range from (T RESET /T) to 2π, the output voltage of the voltage controller of the PLL, instead, becomes negative. That is, the frequency of the fed-back clock signal CLK FB  would be decreased so that the phase of the fed-back clock signal CLK FB  is locked to the incorrect direction. When the phase of the reference clock signal CLK REF  falls behind the fed-back clock signal CLK FB  by the range from 0 to (−T RESET /T), the output voltage of the voltage controller of the PLL keeps falling and negative. That is, the frequency of the fed-back clock signal CLK FB  would be decreased. However, when the phase of the reference clock signal CLK REF  falls behind the fed-back clock signal CLK FB  by the range from (−T RESET /T) to −2π, the output voltage of the voltage controller of the PLL, instead, becomes positive. That is, the frequency of the fed-back clock signal CLK FB  would be increased so that the phase of the fed-back clock signal CLK FB  is locked to the incorrect direction. 
   SUMMARY OF THE INVENTION 
   The present invention provides a Phase/Frequency Detector (PFD). The PFD comprises a rising signal module for generating a rising signal according to a second reference clock signal and a rising reset signal; a falling signal module for generating a falling signal according to a second fed-back clock signal and a falling reset signal; and a reset signal module, comprising a rising reset signal module, comprising a first NAND gate, comprising a first input end for receiving a pre-trigger fed-back signal; a second input end for receiving the falling signal; and an output end for outputting result of NAND operation on signals received on the first and the second input ends of the first NAND gate; a first OR gate, comprising a first input end for receiving an inverted signal of the rising signal; a second input end for receiving an inverted signal of the falling signal; and an output end for outputting result of OR operation on signals received on the first and the second input ends of the first OR gate; a second NAND gate, comprising a first input end coupled to the output end of the first NAND gate; a second input end coupled to the output end of the first OR gate; and an output end for outputting result of NAND operation on signals received on the first and the second input ends of the second NAND gate as the rising reset signal; and a falling reset signal module, comprising a third NAND gate, comprising a first input end for receiving a pre-trigger reference signal; a second input end for receiving the rising signal; and an output end for outputting result of NAND operation on signals received on the first and the second input ends of the third NAND gate; a second OR gate, comprising a first input end for receiving an inverted signal of the rising signal; a second input end for receiving an inverted signal of the falling signal; and an output end for outputting result of OR operation on signals received on the first and the second input ends of the second OR gate; a fourth NAND gate, comprising a first input end coupled to the output end of the third NAND gate; a second input end coupled to the output end of the second OR gate; and an output end for outputting result of NAND operation on signals received on the first and the second input ends of the fourth NAND gate as the falling reset signal; and 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram illustrating a conventional PFD. 
       FIG. 2  is a timing diagram illustrating the operation of the PFD. 
       FIG. 3  is a diagram illustrating the relationship between the phase difference and the output voltage of the PLL utilizing the conventional PFD. 
       FIG. 4  is a diagram illustrating the PFD of the present invention. 
       FIG. 5  is a diagram illustrating the reference clock signal control module of the present invention. 
       FIG. 6  is a diagram illustrating the fed-back clock signal control module. 
       FIG. 7  is a diagram illustrating the relationship between the pre-trigger reference signal and the reference clock signal. 
       FIG. 8  is a diagram illustrating the relationship between the pre-trigger fed-back signal and the fed-back clock signal. 
       FIG. 9  is a diagram illustrating the operation of the PFD of the present invention when the phases of the reference clock signal and the fed-back clock signal are very close. 
       FIG. 10  is a diagram illustrating the relationship between the output voltage of the PLL utilizing the PFD of the present invention and the phase difference. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 4 ,  FIG. 5 , and  FIG. 6  together.  FIG. 4  is a diagram illustrating the PFD  400  of the present invention.  FIG. 5  is a diagram illustrating the reference clock signal control module  500  of the present invention.  FIG. 6  is a diagram illustrating the fed-back clock signal control module  600 . The PFD  400  comprises a rising signal module, a falling signal module  420 , and a reset signal module  430 . 
   The rising signal module  410  can be realized with a flip-flop. The rising signal module  410  is disposed for receiving the reference clock signal CLK REF  and accordingly outputting the rising signal S UP , and for resetting the rising signal S UP  according to the rising reset signal S RESETR . The rising signal module  410  comprises a first-level rising signal circuit  411 , a second-level rising signal circuit  412 , and an inverter INV 1 . 
   The first-level rising signal circuit  411  comprises three transistors Q 1 , Q 2 , and Q 3 . The first end of the transistor Q 1  is coupled to a voltage source V DD ; the second end of the transistor Q 1  is coupled to the first end of the transistor Q 2 ; the control end of the transistor Q 1  receives the rising reset signal S RESETR . The first end of the transistor Q 2  is coupled to the second end of the transistor Q 1 ; the second end of the transistor Q 2  is coupled to the first end of the transistor Q 3 ; the control end of the transistor Q 2  receives the reference clock signal CLK REF . The second end of the transistor Q 3  is coupled to a voltage source V SS  (ground); the first end of the transistor Q 3  is coupled to the second end of the transistor Q 2 ; the control end of the transistor Q 3  receives the rising reset signal S RESETR . The first-level rising signal circuit  411  outputs the first-level rising signal S UP1  at the second end of the transistor Q 2  according to the reference clock signal CLK REF  and the rising reset signal S RESETR . 
   The second-level rising signal circuit  412  comprises three transistors Q 4 , Q 5 , and Q 6 . The first end of the transistor Q 4  is coupled to the voltage source V DD ; the second end of the transistor Q 4  is coupled to the first end of the transistor Q 5 ; the control end of the transistor Q 4  is coupled to the second end of the transistor Q 2  for receiving the first-level rising signal S UP1 . The first end of the transistor Q 5  is coupled to the second end of the transistor Q 4 ; the second end of the transistor Q 5  is coupled to the first end of the transistor Q 6 ; the control end of the transistor Q 5  receives the reference clock signal CLK REF . The second end of the transistor Q 6  is coupled to the voltage source V SS  (ground); the first end of the transistor Q 6  is coupled to the second end of the transistor Q 5 ; the control end of the transistor Q 6  is coupled to the second end of the transistor Q 2  for receiving the first-level rising signal S UP1 . The second-level rising signal circuit  412  outputs the second-level rising signal S UP2  at the second end of the transistor Q 4  according to the reference clock signal CLK REF  and the first-level rising signal S UP1 . 
   The input end of the inverter INV 1  is coupled to the second end of the transistor Q 4  for receiving the second-level rising signal S UP2  and accordingly outputting the inverted second-level rising signal as the rising signal S UP . 
   The falling signal module  420  can be realized with a flip-flop. The falling signal module  420  is disposed for receiving the fed-back clock signal CLK FB  and accordingly outputting the falling signal S DN , and for resetting the falling signal S DN  according to the falling reset signal S RESETF . The falling signal module  420  comprises a first-level falling signal circuit  421 , a second-level falling signal circuit  422 , and an inverter INV 2 . 
   The first-level falling signal circuit  421  comprises three transistors Q 7 , Q 8 , and Q 9 . The first end of the transistor Q 7  is coupled to the voltage source V DD ; the second end of the transistor Q 7  is coupled to the first end of the transistor Q 8 ; the control end of the transistor Q 7  receives the falling reset signal S RESETF . The first end of the transistor Q 8  is coupled to the second end of the transistor Q 7 ; the second end of the transistor Q 8  is coupled to the first end of the transistor Q 9 ; the control end of the transistor Q 8  receives the fed-back clock signal CLK FB . The second end of the transistor Q 9  is coupled to the voltage source V SS  (ground); the first end of the transistor Q 9  is coupled to the second end of the transistor Q 8 ; the control end of the transistor Q 9  receives the falling reset signal S RESETF . The first-level falling signal circuit  421  outputs the first-level falling signal S DN1  at the second end of the transistor Q 8  according to the fed-back clock signal CLK FB  and the falling reset signal S RESETF . 
   The second-level falling signal circuit  422  comprises three transistors Q 10 , Q 11 , and Q 12 . The first end of the transistor Q 10  is coupled to the voltage source V DD ; the second end of the transistor Q 10  is coupled to the first end of the transistor Q 11 ; the control end of the transistor Q 10  is coupled to the second end of the transistor Q 8  for receiving the first-level falling signal S DN1 . The first end of the transistor Q 11  is coupled to the second end of the transistor Q 10 ; the second end of the transistor Q 11  is coupled to the first end of the transistor Q 12 ; the control end of the transistor Q 11  receives the fed-back clock signal CLK FB . The second end of the transistor Q 12  is coupled to the voltage source V SS  (ground); the first end of the transistor Q 12  is coupled to the second end of the transistor Q 11 ; the control end of the transistor Q 12  is coupled to the second end of the transistor Q 8  for receiving the first-level falling signal S DN1 . The second-level falling signal circuit  422  outputs the second-level falling signal S DN2  at the second end of the transistor Q 10  according to the fed-back clock signal CLK FB  and the first-level falling signal S DN1 . 
   The input end of the inverter INV 2  is coupled to the second end of the transistor Q 10  for receiving the second-level falling signal S DN2  and accordingly outputting the inverted second-level falling signal as the falling signal S DN . 
   Additionally, the transistors Q 1 , Q 2 , Q 4 , Q 7 , Q 8 , and Q 10  are P channel Metal Oxide Semiconductor (PMOS) transistors; the transistors Q 3 , Q 5 , Q 6 , Q 9 , Q 11 , and Q 12  are NMOS transistors. 
   The reset signal module  430  comprises a rising reset signal module  431 , and a falling reset signal module  432 . 
   The rising reset signal module  431  comprises a fed-back clock signal control module  600  (as shown in  FIG. 6 ), two NAND gates NAND 1  and NAND 2 , and an OR gate OR 1 . 
   The fed-back clock signal control module  600  comprises an inverting delay module  610 , an inverter INV 4 , and an AND gate AND 2 . 
   The inverting delay module  610  is disposed for delaying an original fed-back clock signal CLK FBO  by a predetermined period T P  and inverting the delayed fed-back clock signal in order to generate the clock signal CLK FBDI . The inverting delay module  610  can be realized with N inverters coupled in series, and the number N is an odd number. Each of the inverters has the same delay period, and therefore the sum of the delay period of the N inverters equals to the predetermined period T P . The predetermined period T P  equals to the minimum of the reset signal S RESET  required by the conventional PFD  100 , and equals to the reaction period required by the signal being reset from the rising signal module  410  in the present invention. 
   The inverter INV 4  is coupled to the output end of the inverting delay module  610  for inverting the clock signal CLK FBDI  and accordingly generating the fed-back clock signal CLK FB . 
   The first input end of the AND gate AND 2  is coupled to the output end of the inverting delay module  610  for receiving the clock signal CLK FBDI ; the second end of the AND gate AND 2  receives the original fed-back clock signal CLK FBO ; the output end of the AND gate AND 2  outputs the pre-trigger fed-back signal CLK PFB . The AND gate AND 2  operates AND calculation on the clock signals CLK FBDI  and CLK FBO  and outputs the result as the pre-trigger fed-back signal CLK PFB . 
   The first input end of the NAND gate NAND 3  is coupled to the output end of the AND gate AND 2  for receiving the pre-trigger fed-back signal CLK PFB ; the second input end of the NAND gate NAND 3  is coupled to the output end of the inverter INV 1  for receiving the rising signal S UP ; the output end of the NAND gate NAND 3  outputs the pre-trigger rising reset signal S PRESETR . The NAND gate NAND 3  operates NAND calculation on the pre-trigger fed-back signal CLK PFB  and the rising signal S UP  and outputs the result as the pre-trigger rising reset signal S PRESETR . 
   The first input end of the OR gate OR 1  is coupled to the output end of the second-level rising circuit  412  (the second end of the transistor Q 4 ) for receiving the second-level rising signal S UP2 ; the second input end of the OR gate OR 1  is coupled to the output end of the second-level falling circuit  422  (the second end of the transistor Q 10 ) for receiving the second-level falling signal S DN2 ; the output end of the OR gate OR 1  is coupled to the second input end of the NAND gate NAND 1 . The OR gate OR 1  operates OR calculation on the second-level rising signal S UP2  and the second-level falling signal S DN2  and outputs the result to the second end of the NAND gate NAND 1 . 
   The first input end of the NAND gate NAND 1  is coupled to the output end of the NAND gate NAND 3  for receiving the pre-trigger rising reset signal S PRESETR ; the second input end of the NAND gate NAND 1  is coupled to the output end of the OR gate OR 1 ; the output end of the NAND gate NAND 3  outputs the rising reset signal S RESETR . The NAND gate NAND 3  operates NAND calculation on the signals received on the first and the second input ends of the NAND gate NAND 3  and outputs the result as the rising reset signal S RESETR . 
   The falling reset signal module  432  comprises a reference clock signal control module  500  (as shown in  FIG. 5 ), two NAND gates NAND 2  and NAND 4 , and an OR gate OR 2 . 
   The reference clock signal control module  500  comprises an inverting delay module  510 , an inverter INV 3 , and an AND gate AND 1 . 
   The inverting delay module  510  is disposed for delaying an original reference clock signal CLK REFO  by a predetermined period T P  and inverting the delayed reference clock signal in order to generate the clock signal CLK REFDI . The inverting delay module  510  can be realized with N inverters coupled in series, and the number N is an odd number. Each of the inverters has the same delay period, and therefore the sum of the delay period of the N inverters equals to the predetermined period T P , which is same as the inverting delay module  610 . 
   The inverter INV 3  is coupled to the output end of the inverting delay module  510  for inverting the clock signal CLK REFDI  and accordingly generating the reference clock signal CLK REF . 
   The first input end of the AND gate AND 1  is coupled to the output end of the inverting delay module  510  for receiving the clock signal CLK REFDI ; the second end of the AND gate AND 1  receives the original reference clock signal CLK REFO ; the output end of the AND gate AND 1  outputs the pre-trigger reference signal CLK PREF . The AND gate AND 1  operates AND calculation on the clock signals CLK REFDI  and CLK REFO  and outputs the result as the pre-trigger reference signal CLK PREF . 
   The first input end of the NAND gate NAND 4  is coupled to the output end of the AND gate AND 1  for receiving the pre-trigger reference signal CLK PREF ; the second input end of the NAND gate NAND 4  is coupled to the output end of the inverter INV 2  for receiving the falling signal S DN ; the output end of the NAND gate NAND 4  outputs the pre-trigger falling reset signal S PRESETF . The NAND gate NAND 4  operates NAND calculation on the pre-trigger reference signal CLK PREF  and the falling signal S DN  and outputs the result as the pre-trigger falling reset signal S PRESETF . 
   The first input end of the OR gate OR 2  is coupled to the output end of the second-level falling circuit  422  (the second end of the transistor Q 10 ) for receiving the second-level falling signal S DN2 ; the second input end of the OR gate OR 2  is coupled to the output end of the second-level rising circuit  412  (the second end of the transistor Q 4 ) for receiving the second-level rising signal S UP2 ; the output end of the OR gate OR 2  is coupled to the second input end of the NAND gate NAND 2 . The OR gate OR 2  operates OR calculation on the second-level rising signal S UP2  and the second-level falling signal S DN2  and outputs the result to the second end of the NAND gate NAND 2 . 
   The first input end of the NAND gate NAND 2  is coupled to the output end of the NAND gate NAND 4  for receiving the pre-trigger falling reset signal S PRESETF ; the second input end of the NAND gate NAND 2  is coupled to the output end of the OR gate OR 2 ; the output end of the NAND gate NAND 2  outputs the falling reset signal S RESETF . The NAND gate NAND 2  operates NAND calculation on the signals received on the first and the second input ends of the NAND gate NAND 2  and outputs the result as the falling reset signal S RESETF . 
   Please refer to  FIG. 7  and  FIG. 8  together.  FIG. 7  is a diagram illustrating the relationship between the pre-trigger reference signal and the reference clock signal.  FIG. 8  is a diagram illustrating the relationship between the pre-trigger fed-back signal and the fed-back clock signal. As shown in  FIG. 7 , the pre-trigger reference signal CLK PREF  rises up to logic “1” by the period T RESET  (equals to T P ) before each rising edge of the reference clock signal CLK REF . As shown in  FIG. 8 , the pre-trigger fed-back signal CLK PFB  rises up to logic “1” by the period T RESET  (equals to T P ) before each rising edge of the fed-back clock signal CLK FB . 
   Please refer to  FIG. 9 .  FIG. 9  is a diagram illustrating the operation of the PFD of the present invention when the phases of the reference clock signal and the fed-back clock signal are very close. As shown in  FIG. 9 , the fed-back clock signal CLK FB  falls behind the reference clock signal CLK REF , and the first rising edge E FB1  of the fed-back clock signal CLK FB  is very close to the second rising edge E REF2  of the reference clock signal CLK REF . In such condition, the conventional PFD decreases the frequency of the fed-back clock signal CLK FB  in order to lock the phase equal to the phase of the reference clock signal CLK REF , which is incorrect. In fact, in such condition, the frequency of the fed-back clock signal CLK FB  should be increased to be in-phase with the reference clock signal CLK REF . In  FIG. 9 , when the first rising edge E REF1  of the reference clock signal CLK REF  occurs, after the reaction time T D1 , the rising signal S UP  is triggered to be logic “1”. When the second rising edge E REF2  of the reference clock signal CLK REF  occurs, the corresponding pre-trigger reference signal CLK PREF  and the rising signal S UP  being logic “1” at the time are inputted to the falling reset signal module  432 . After the logic calculation of the falling reset signal module  432 , the falling reset signal S RESETF  is outputted by logic “1” (logic “1” represents reset) and remains for the period T RESET . When the first rising edge E FB1  of the fed-back clock signal CLK FB  occurs, since it falls within the range of the resetting duration of the falling reset signal S RESETF , the falling signal module  420 , at the time, is being reset. Therefore, the falling signal S DN  keeps at logic “0” and consequently the fed-back clock signal CLK FB  is not decreased. In this way, the phase determining problem generated from the conventional PFD can be avoided. 
   Please refer to  FIG. 10 .  FIG. 10  is a diagram illustrating the relationship between the output voltage of the PLL utilizing the PFD  400  of the present invention and the phase difference. It is assumed that the period of the reference clock signal CLK REF  is T. As shown in  FIG. 10 , when the phase of the reference clock signal CLK REF  is ahead of the fed-back clock signal CLK FB  by the range from 0 to (T RESET /T), the output voltage of the voltage controller of the PLL keeps rising and positive. That is, the frequency of the fed-back clock signal CLK FB  would be increased. When the phase of the reference clock signal CLK REF  is ahead of the fed-back clock signal CLK FB  by the range from (T RESET /T) to 2π, the output voltage of the voltage controller of the PLL keeps constant and still positive. That is, the frequency of the fed-back clock signal CLK FB  would be still increased so that the phase of the fed-back clock signal CLK FB  is not locked to the incorrect direction. When the phase of the reference clock signal CLK REF  falls behind the fed-back clock signal CLK FB  by the range from 0 to (−T RESET /T), the output voltage of the voltage controller of the PLL keeps falling and negative. That is, the frequency of the fed-back clock signal CLK FB  would be decreased. When the phase of the reference clock signal CLK REF  falls behind the fed-back clock signal CLK FB  by the range from (−T RESET /T) to −2π, the output voltage of the voltage controller of the PLL keeps constant and still negative. That is, the frequency of the fed-back clock signal CLK FB  would be decreased so that the phase of the fed-back clock signal CLK FB  is not locked to the incorrect direction. 
   To sum up, the PFD provided by the present invention, comprises reset signal module utilizing pre-trigger reference signal and the pre-trigger fed-back signal, for resetting the rising signal module and the falling signal module, respectively. In this way, the incorrect phase determination due to the reaction time of the reset signal can be avoided, providing great convenience. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.