Abstract:
A multi-state indicator comprises a voltage generator, for generating M voltages, with M being an integer larger than 3; and a multi-state detector, coupled to the voltage generator, for receiving M voltages, having a voltage input end for receiving an input voltage to generate an indication signal whereby the indication signal is capable of indicating the input voltage with reference to the M voltages. Unlike the prior art, a multi-state detector having level shifters according to the present invention alleviates problems of static currents and over-large areas for circuits implementing typical differential comparators.

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATION 
     This patent application is based on Taiwan, R.O.C. patent application No. 099129972 filed on Sep. 3, 2010. 
     FIELD OF THE INVENTION 
     The present invention relates to an indicator, and more particularly, to a multi-state indicator. 
     BACKGROUND OF THE INVENTION 
     Generally, a multi-state indicator is used to represent a voltage of a voltage input end in the digital format. Please refer to  FIG. 1(   a ) and  FIG. 1(   b ).  FIG. 1(   a ) and  FIG. 1(   b ) are schematic diagrams of operational segments and circuits of a three-state indicator  100  according to the prior art. When the three-stage indicator  100  is applied to a circuit having a voltage distributed from V ss  to V dd  (V dd &gt;V ss ), the three-stage indicator  100  determines that an input voltage V in  is V dd , V M , or V ss , and puts the input voltage V in  into a two-bit indication signal (V out2 , V out1 ), i.e., the indication signal (V out2 , V out1 ) is represented in the digital indication signal output “1/0” format, so as to be provided to subsequent circuits. 
     Please refer to  FIG. 1(   a ), a voltage segment from V dd  to V ss  is divided into two voltage segments—a first voltage segment I formed between V M  and V ss  and a second voltage segment II formed between V dd  and V M . A first reference voltage V ref1  is selected from the first voltage segment I, and a second reference voltage V ref2  is selected from the second voltage segment II. As shown in  FIG. 1(   b ), the first reference voltage V ref1  and the second reference voltage V ref2  are generated by a reference voltage generator  101 , and the voltages V dd , V ref2 , V ref1 , and V ss  are provided to the three-state detector  103 . The above voltages are compared with the input voltage V in  in the three-state detector  103 , and the input voltage V in  is determined to be one of the voltages according to the indication signal (V out2 , V out1 ). 
       FIG. 2(   a ) is a schematic diagram of a differential comparator  2 . When an input voltage V in2  at a positive input end of the differential comparator  2  is larger than an input voltage V in1  at a negative input end, a digital indication signal “1” is generated at an output end V out  of the differential comparator  2 . On the contrary, when the input voltage V in2  at the positive input end of the differential comparator  2  is smaller than the input voltage V in1  at the negative input end, a digital indication signal “0” is generated at the output end V out  of the differential comparator  2 . 
     Please refer to  FIG. 2(   b ).  FIG. 2(   b ) is a schematic diagram of a three-state indicator implemented with two differential comparators in the prior art. The three-state detector  103  of the three-state indicator  100  is composed of a first differential comparator  21  and a second differential comparator  22 . The first differential comparator  21  has a positive input end for receiving an input voltage V in , a negative input end for receiving a first reference voltage V ref1 , and an output end for generating the first bit V out1  of the indication signal (V out2 , V out1 ). The second differential comparator  22  has a positive input end for receiving the input voltage V in , a negative input end for receiving a second reference voltage V ref2 , and an output end for generating the second bit V out2  of the indication signal (V out2 , V out1 ). 
     It can be seen that when the input voltage V in  is at the first level V ss , the indication signal (V out2 , V out1 ) is (0, 0); when the input voltage V in  is at the second level V M , the indication signal (V out2 , V out1 ) is (0, 1); when the input voltage V in  is at the third level V dd , the indication signal (V out2 , V out1 ) is (1, 1). As shown in  FIG. 2(   b ), since power of the first differential comparator  21  and the second differential comparator  22  is supplied by V dd  and V ss , the logic “1” of the first differential comparator  21  and the second differential comparator  22  is V dd , while the logic “0” is V ss . 
     The approach of implementing the three-state indicator  100  with the differential comparator  2  in the prior art can also be applied to other multi-state indicators. Please refer to  FIG. 2(   c ) and  FIG. 2(   d ) at the same time.  FIG. 2(   c ) and  FIG. 2(   d ) are schematic diagrams of operation segments and circuits of a four-state indicator  200 . 
     As shown in  FIG. 2(   c ), voltage differences of four voltages V ss , V ML , V MH , and V dd  (where V ss &lt;V ML &lt;V MH &lt;V dd ), used for comparison by the four-state indicator  200 , are divided into three voltage segments I, II, and III. The first reference voltage V ref1  is selected from the first voltage segment I, the second reference voltage V ref2  is selected from the second voltage segment II, and the third reference voltage V ref3  is selected from the third voltage segment III. As shown in  FIG. 2(   d ), in addition to the three reference voltages V ref1 , V ref2 , and V ref3  outputted by the reference voltage generator  201 , V dd  and V ss , are supplied to the voltage input end of the four-state detector  203 , which comprises three differential comparator circuits  23 ,  24 , and  25 . Besides taking V in  as input voltages of positive input ends, the differential comparator circuits  23 ,  24 , and  25  respectively take reference voltages V ref1 , V ref2 , and V ref3  as input voltages of negative input ends, and comparison results of the differential comparator circuits  23 ,  24 , and  25  are taken as an indication signal (V out3 , V out2 , V out1 ) generated by the four-state indicator  200 . Since power of the differential comparator circuits  23 ,  24 , and  25  is supplied by V dd  and V ss , the logic “1” outputted by the differential comparator circuits  23 ,  24 , and  25  is V dd , while the logic “0” outputted by differential comparator circuits  23 ,  24 , and  25  is V ss . 
     However, circuit design of the conventional differential comparator is rather complex. Once the number of to-be-identified states increase, accordingly, the circuit design complexity increases greatly, resulting in difficulties in the circuit design. An area of the differential comparator is excessively large, causing a significant increment in production cost. In addition, the circuit design of the differential comparator has a static current problem, causing additional power consumption. 
     SUMMARY OF THE INVENTION 
     In view of the above issues, one object of the present invention is to provide a multi-state detector realized by a level shifter circuit so as to solve the above problems of static currents and the over-large area prevalent in the prior art. 
     According to an embodiment of the present invention, a three-state indicator comprises a voltage generator, for generating a first voltage, a second voltage, and a third voltage; and a three-state detector, coupled to the voltage generator, for receiving the first voltage, the second voltage and the third voltage, with the three-state detector having a voltage input end for selectively receiving the first voltage, the second voltage or the third voltage to generate an indication signal whereby the indication signal is capable of indicating an input voltage at the voltage input end. 
     According to another embodiment of the represent invention, a multi-state indicator comprises a voltage generator, for generating M voltages, with M being an integer larger than 3; and a multi-state detector, coupled to the voltage generator, for receiving M voltages, having a voltage input end for receiving an input voltage to generate an indication signal whereby the indication signal is capable of indicating the input voltage with reference to the M voltages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following description and figures are disclosed to gain a better understanding of the advantages of the present invention. 
         FIG. 1(   a ) and  FIG. 1(   b ) are respectively a schematic diagram of voltage segments of an output voltage of the conventional third-state indicator and a block diagram of a conventional third-state indicator. 
         FIG. 2(   a ) is a schematic diagram of a conventional differential comparator. 
         FIG. 2(   b ) is a schematic diagram of a conventional three-state indicator implemented by two differential comparators. 
         FIG. 2(   c ) is a schematic diagram of operation segments of a conventional four-state indicator. 
         FIG. 2(   d ) is a schematic diagram of a conventional four-state detector implemented by three differential comparators. 
         FIG. 3(   a ) is a schematic diagram of a first type sub-detector module in accordance with an embodiment of the present invention. 
         FIG. 3(   b ) is a schematic diagram of relationships of an input voltage of the first type sub-detector module corresponding to nodes and an output voltage with associated indication signal bits. 
         FIG. 3(   c ) is a schematic diagram of a second type sub-detector module in accordance with an embodiment of the present invention. 
         FIG. 3(   d ) is a schematic diagram of relationships of an output voltage of the second type sub-detector module corresponding to nodes and an output voltage with associated indication signal bits. 
         FIG. 3(   e ) is a schematic diagram of a third type sub-detector module in accordance with an embodiment of the present invention. 
         FIG. 3(   f ) is a schematic diagram of relationships of an output voltage of the third type sub-detector module corresponding to nodes and an output voltage with associated indication signal bits. 
         FIG. 4(   a ) and  FIG. 4(   b ) are respectively a block diagram of a three-state indicator and a schematic diagram of voltage segments of an output voltage of the three-state indicator in accordance with an embodiment of the present invention. 
         FIG. 4(   c ) is a schematic diagram of detailed circuits of a three-state detector in accordance with an embodiment of the present invention. 
         FIG. 4(   d ) is a schematic diagram of an output voltage of a three-state detector circuit corresponding to an indication signal in accordance with an embodiment of the present invention. 
         FIG. 5(   a ) and  FIG. 5(   b ) are respectively a block diagram of a four-state indicator and a schematic diagram of voltage segments of an output voltage of the four-state indicator in accordance with an embodiment of the present invention. 
         FIG. 5(   c ) is a schematic diagram of detailed circuits of a four-state detector in accordance with an embodiment of the present invention. 
         FIG. 5(   d ) is a schematic diagram of an output voltage of a four-state detector circuit corresponding to an indication signal in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Each of the above multi-state indicators includes a reference voltage generator (the reference voltage generator  101  or the reference voltage generator  201 ) and a multi-state detector (e.g., the three-state detector  103  or the four-state detector  203 ) mainly having differential comparators. Since circuits of the differential comparators have problems of static currents and over-large area, a multi-state detector mainly having level shifters according to the present invention is thereby developed to solve the above problems. Since the multi-state detector in accordance with the embodiments of the present invention uses no differential comparators, the conventional reference voltages V ref1  and V ref2  need not be provided to the three-state detector  103  or the four-state detector  203  for comparison. 
     Three types of sub-detector modules and timings are described as follows. 
     Please refer to  FIG. 3(   a ).  FIG. 3(   a ) is a schematic diagram of circuits of a first type sub-detector module  310 , which has an input voltage V in  and a digital output voltage V out . Circuits between the input voltage V in  and the output voltage V out  can be roughly divided into three stages—two inverters I 31 , I 32  and a first type level shifter M 31 . 
     The inverter I 31  comprises a P-channel metal-oxide-semiconductor field effect transistor (MOSFET) P 311 , and an N-channel MOSFET N 311 . The P-channel MOSFET P 311  has a source (i.e., a first end) coupled to V M , a gate (i.e., a control end) coupled to the voltage input end V in , and a drain (i.e., a second end) coupled to a drain (i.e., a second end) of the N-channel MOSFET N 311 . The N-channel MOSFET N 311  has a gate (i.e., a control end) coupled to the voltage input end V in , and a source (i.e., a first end) coupled to V ss . 
     The inverter I 32  comprises a P-channel MOSFET P 312  and an N-channel MOSFET N 312 . The P-channel MOSFET P 312  has a source coupled to V M , a gate coupled to an output end of the inverter I 31 , and a drain coupled to a drain of the N-channel MOSFET N 312 . The N-channel MOSFET N 312  has a gate coupled to an output end of the inverter I 31 , and a source coupled to V ss . For brevity, the output ends of the inverters I 31  and I 32  are respectively defined as a node S 311  and a node S 312 . 
     The first type level shifter M 31  comprises two P-channel MOSFETs P 313  and P 314 , and two N-channel MOSFETs N 313  and N 314 . Sources of the two P-channel MOSFETs P 313  and P 314  are coupled to V dd , and sources of the two N-channel MOSFETs N 313  and N 314  are coupled to V ss . A gate of the P-channel MOSFET P 313 , a drain of the N-channel MOSFET N 314 , and a drain of the P-channel MOSFET P 314  are connected to a node S 314 . A gate of the P-channel MOSFET P 314 , a drain of the N-channel MOSFET N 313  and a drain of the P-channel MOSFET P 313  are connected to a node S 313 . A gate of the N-channel MOSFET N 313  is connected to the node S 312  (i.e., the output end of the inverter I 32 ). A gate of the N-channel MOSFET N 314  is connected to the node S 311  (i.e., the output end of the inverter I 31 ). The node S 314  is connected to the output voltage V out  of the first type sub-detector module  310 . The input voltage V in  is one of V dd , V M , and V ss , wherein V dd &gt;V M &gt;V ss . 
       FIG. 3(   b ) is a table of the input voltage V in  of the first type sub-detector module  310  corresponding to voltages of the nodes S 311 , S 312 , S 313 , and S 314  and the output voltage V out . The nodes S 311 , S 312 , S 313 , and S 314  in a row are defined as above. Each row in  FIG. 3(   b ) represents cases of the input voltage V in  equal to V dd , V M , and V ss , respectively. Take the input voltage V in  equal to V dd  as an example, the voltage of the node S 311  is V ss , the voltage of the node S 312  is V M , the voltage of the node S 313  is V ss , and the voltage (i.e., the output voltage V out ) of the node S 314  is V dd . 
     As shown in  FIG. 3(   b ), the voltages of the nodes of the inverters I 31 , I 32 , and the first type level shifter M 31  are respectively enclosed by dashed lines, for denoting the voltages of the nodes of each module when the input voltage V in  changes, so as to make clear that when the input voltage V in  of the first type sub-detector module  310  is V dd  or V M , the output voltage V out  is V dd , i.e., the digital indication signal bit is “1”; when the input voltage V in  is V ss , the output voltage V out  is V ss , i.e., the digital indication signal bit is “0”. 
     The inverters I 31  and I 32  in a steady state do not generate any static current. When the N-channel MOSFET N 313  of the first type level shifter M 31  receives V M  at its gate, it is determined that the P-channel MOSFET P 313  is completely turned off. When the N-channel MOSFET N 314  receives V ss  at its gate, it is determined that the N-channel MOSFET N 314  is completely turned off. Therefore, the first type sub-detector module  310  in the steady state does not generate any static current. 
       FIG. 3(   c ) is a schematic diagram of circuits of a second type sub-detector module  320 , which has an input end coupled to a voltage input end for inputting an input voltage V in , and an output end for outputting a digital output voltage V out . Two inverters I 33  and I 34  and a second type level shifter M 32  are circuits between the voltage input end for inputting the input voltage V in  and the output end for outputting the digital output voltage V out . The second type sub-detector module  320  comprises four P-channel MOSFETs P 321 , P 322 , P 323  and P 324 , and four N-channel MOSFETs N 321 , N 322 , N 323  and N 324 . The detailed connections are illustrated in  FIG. 3(   c ) and are omitted herein. 
       FIG. 3(   d ) is a table of the input voltage V in  of the second type sub-detector module  320  corresponding to voltages of nodes S 321 , S 322 , S 323 , and S 324  and the output voltage V out . The node S 321  in  FIG. 3(   c ) is an output node of the inverter I 33 , the node S 322  is an output node of the inverter I 34 , and the nodes S 323  and S 324  are nodes of the second type level shifter M 32 . 
     It can be seen from  FIG. 3(   d ) that when the input voltage V in  is V dd , the corresponding output voltage V out  is V dd , and when the input voltage V in  is V M  or V ss , the corresponding output voltage V out  is V ss . In other words, when the input voltage V in  of the second type sub-detector module  320  is V dd , the output voltage V out  is V dd , i.e., the digital indication signal bit is “1”; when the input voltage V in  is V M  or V ss , the output voltage V out  is V ss , i.e., the digital indication signal bit is “0”. 
     The inverter I 33  and I 34  in the steady state do not generate any static current. When the P-channel MOSFET P 323  of the second type level shifter M 32  receives V dd  at its gate, the P-channel MOSFET P 323  is completely turned off; when the P-channel MOSFET P 324  receives V M  at its gate, the N-channel MOSFET N 324  is completely turned off. Therefore, the second type sub-detector module  320  in the steady state does not generate any static current. 
       FIG. 3(   e ) illustrates a schematic diagram of circuits of a third type sub-detector module  330 , which comprises two inverters I 35 , I 36 , a third type level shifter M 33 , and a fourth type level shifter M 34 . The third type sub-detector module  330  inputs an input voltage V in  to an input end of the inverter I 35 , and generates an output voltage V out  at an output end of the fourth type level shifter M 34  as an indication signal. 
     The inverter I 35  comprises a P-channel MOSFET P 331  and an N-channel MOSFET N 331 , and an output end thereof is designated node S 331 . The inverter I 36  comprises a P-channel MOSFET P 332  and an N-channel MOSFET N 332 , and an output end thereof is designated node S 332 . Power of the inverters I 35  and I 36  is supplied by V ML  and V MH . 
     The third type level shifter M 33  of the third type sub-detector module  330  comprises two P-channel MOSFETs P 333  and P 334 , and two N-channel MOSFETs N 333  and N 334 . The P-channel MOSFET P 333  and the N-channel MOSFET N 333  are connected at a node S 333 , and the P-channel MOSFET P 334  and the N-channel MOSFET P 334  are connected at a node S 334 . Power of the third type level shifter M 33  is supplied by V MH  and V ss . 
     The fourth type level shifter M 34  of the third type sub-detector module  330  comprises two P-channel MOSFET P 335  and P 336 , and two N-channel MOSFET N 335  and N 336 . The P-channel MOSFET P 335  and the N-channel MOSFET N 335  are connected at a node S 335 , and the P-channel MOSFET P 336  and the N-channel MOSFET N 336  are connected at a node S 336 . Power of the fourth type level shifter M 34  is supplied by V dd  and V ss . The input voltage V in  is one of V dd , V MH , V ML , and V ss , wherein V dd &gt;V MH &gt;V mL &gt;V ss . 
     Please refer to  FIG. 3(   f ).  FIG. 3(   f ) is a table of the input voltage V in  of the third type sub-detector module  330  corresponding to the nodes S 331 , S 332 , S 333 , S 334 , S 335 , and S 336  and the output voltage V out . For clarity,  FIG. 3(   f ) shows the circuit modules comprising the nodes S 331 , S 332 , S 333 , S 334 , S 335 , and S 336  are enclosed by circular dashed lines, respectively. 
     Each row of the table in  FIG. 3(   f ) respectively represents situations of the input voltage V in  being V dd , V MH , V ML , and V ss  in sequence. When V dd , V MH , V ML , and V ss  are respectively inputted as the input voltage V in  to the third type sub-detector module  330 , the corresponding output voltage V out  is respectively V dd , V dd , V ss , and V ss , as shown in the table. In other words, when the input voltage V in  of the third type sub-detector module  330  is V dd  or V MH , the output voltage V out  is V dd , i.e., the digital indication signal bit is “1”; when the input voltage V in  of the third type sub-detector module  330  is V ML  or V ss , the output voltage V out  is V ss , i.e., the digital indication signal bit is “0”. 
     The inverters I 35  and I 36  in a steady state do not generate any static current. Further, when the P-channel MOSFET P 333  of the third type level shifter M 33  receives V MH  at its gate, the P-channel MOSFET P 333  is completely turned off; when the P-channel MOSFET P 334  receives V ML  at its gate, the N-channel MOSFET N 334  is completely turned off. 
     When the N-channel MOSFET N 335  of the fourth type level shifter M 34  receives V MH  at its gate, the P-channel MOSFET P 335  is completely turned off; when the N-channel MOSFET N 336  receives V ss  at its gate, the N-channel MOSFET N 336  is completely turned off. Therefore, the third type level shifter M 33  and the fourth type level shifter M 34  of the third type sub-detector module  330  in the steady state do not generate any static current. 
       FIG. 4(   a ) and  FIG. 4(   b ) are schematic diagrams of a three-state indicator  400  according to an embodiment of the present invention. The three-state indicator  400  comprises a reference voltage generator  401  and a three-state detector  403 . The reference voltage generator  401  outputs three types of voltages V dd , V M , and V ss  to the three-state detector  403 . An input voltage V in  of the three-state detector  403  can be one of V dd , V M , and V ss , and an indication signal (V out2 , V out1 ) is generated for identifying the input voltage V in . The reference voltage generator  401  only needs to input the voltages V dd , V M , and V ss  into the three-state detector  403 . For example, the reference voltage generator  401  generates V dd , V M , and V ss  via voltage dividing of resistors. 
     Please refer to  FIG. 4(   c ).  FIG. 4(   c ) is a schematic diagram of circuits of the three-state detector  403  according to an embodiment of the present invention. The three-state detector  403  is designed based on the above first type sub-detector module  310  and the second type sub-detector module  320 . For brevity, the inverters I 33 , I 34 , I 31 , and I 32  of the three-state detector  403  are directly marked as basic units, and detailed narrations of circuits thereof are omitted herein. 
     Besides the inverters, the three-state detector  403  further comprises a first type level shifter M 31  and a second type level shifter M 32 . Power of the inverters I 31  and I 32  is supplied by V M  and V ss . Power of the inverters I 33  and I 34  is supplied by V dd  and V M , and power of the first type level shifter M 31  and the second type level shifter M 32  is supplied by V dd  and V ss . 
     Please refer to  FIG. 4(   d ).  FIG. 4(   d ) is a table of an indication signal (V out2 , V out1 ) respectively corresponding to V dd , V M , and V ss  as the input voltage V in  of the three-state detector  403  in  FIG. 4(   c ). When the indication signal (V out2 , V out1 ) is (1, 1), i.e., (V dd , V dd ), the input voltage V in  is V dd . When the indication signal (V out2 , V out1 ) is (0, 1), i.e., (V ss , V dd ), the input voltage V in  is V M . When the indication signal (V out2 , V out1 ) is (0, 0), i.e., (V ss , V ss ), the input voltage V in  is V ss . 
     Please refer to  FIG. 5(   a ) and  FIG. 5(   b ).  FIG. 5(   a ) and  FIG. 5(   b ) are schematic diagrams of a four-state indicator  500  according to an embodiment of the present invention. The four-state indicator  500  comprises a reference voltage generator  501  and a four-state detector  503 . The reference voltage generator  501  outputs four voltages V dd , V MH , V ML , and V ss  to the four-state detector  503 . An input voltage V in  of the four-state detector  503  can be one of the four voltages V dd , V MH , V ML , and V ss , which is identified according to an indication signal (V out3 , V out2 , V out1 ). 
       FIG. 5(   c ) is a schematic diagram of detailed circuits of the four-state detector  503  according to an embodiment of the present invention. The four-state detector  503  comprises the above first type sub-detector module  310 , the second type sub-detector module  320  and the third type sub-detector module  330 . The three voltages received by the first type sub-detector module  310  are V dd , V ML , and V ss , and three voltages received by the second type sub-detector module  320  are V dd , V MH , and V ss . 
     For brevity, inverters I 33 , I 34 , I 31 , I 32 , I 35 , and I 36  of the four-sate detector  503  are directly marked as basic units, and detailed narrations of circuits thereof are omitted herein. The four-state detector  503  further comprises a first type level shifter M 31 , a second type level shifter M 32 , a third type level shifter M 33 , and a fourth type level shifter M 34 . The above sub-detector modules are implemented by the inverters and the level shifters. 
     Please refer to  FIG. 5(   d ).  FIG. 5(   d ) is a table of the indication signal (V out3 , V out2 , V out1 ) corresponding to V dd , V MH , V ML , and V ss  as the input voltage V in  of the four-state detector  503  in  FIG. 5(   c ). When the indication signal (V out3 , V out2 , V out1 ) is (1, 1, 1), i.e., (V dd , V dd , V dd ), the input voltage V in  is V dd . When the indication signal (V out1 , V out2 , V out1 ) is (0, 1, 1), i.e., (V ss , V dd , V dd ), the input voltage V in  is V MH . When the indication signal (V out3 , V out2 , V out1 ) is (0, 0, 1), i.e., (V ss , V ss , V dd ), the input voltage V in  is V ML . When the indication signal (V out3 , V out2 , V out1 ) is (0, 0, 0), i.e., (V ss , V ss , V ss ), the input voltage V in  is V ss . 
     The present invention significantly eliminates the static current by implementing inner circuits of a multi-state indicator with level shifters, and has an advantage because a level shifter occupies less area than a differential comparator. Please note that formations of the level shifter are diversified, and the present invention is not limited to the above level shifters while implementing the detector, that is to say, other types of level shifters are also applicable. 
     Although the embodiments according to the present invention merely take three-state indicators and four-state indicators as examples, for illustrating a conception of implementing a multi-indicator with level shifters, similar approaches evolved from the conception are capable of implementing circuit modules of level shifters in circuit designs of other multi-state indicators. 
     In order to eliminate static currents and over-large circuit area of a multi-state indicator with a differential comparator, a level shifter is implemented to realize the multi-state indicator. A design adopting the level shifter is capable of avoiding penetration currents when an output end of an open circuit is connected to a high-voltage power supplier, so as to reduce power consumption and noises. On the other hand, since complexity of a level shifter circuit is lower than that of a differential comparator, the level shifter design also outruns while reduction of circuit area is considered. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not to be limited to the above embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.