Abstract:
A charge pump which can operate at low supply voltages is provided. The charge pump recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices. Charge recirculation is used to compensate for threshold voltage drops associated with diodes or diode-configured transistors used to implement the charge pump. As a result, voltage amplification can occur in the charge pump even for small power supply values.

Description:
TECHNICAL FIELD 
     This invention relates generally to analog circuits requiring operating voltages greater than available power supply voltages, and more particularly, to charge pump circuits. 
     BACKGROUND ART 
     Analog circuits are typically being designed to operate at low power supply voltages such as five volts. Although five volts is a commonly found power supply voltage level, power supply voltages of three volts and less are more desirable for battery operated circuits where power consumption is critical. Even in automotive applications where higher supply voltages are typically present, three volt power supply operation is desirable due to the wide variation of battery voltage which is possible. Typical analog circuits including analog switches however require a voltage greater than three volts to be operational. Therefore, a charge pump which functions to boost the level of the power supply for predetermined portions of a circuit must be utilized. Conventional charge pump circuits utilize diodes which are typically implemented by diode configured N-channel transistors in MOS circuits. A disadvantage with previous charge pump circuits results from a threshold voltage drop which is present across a diode or diode configured transistor. The threshold voltage drop decreases the output voltage of the charge pump by the threshold voltage value and may drastically reduce the efficiency of the charge pump. The reduced efficiency may be a critical factor when supply voltages of three volts or less are used because the threshold voltage of a diode becomes a significant portion of the power supply voltage. As a result, known charge pump circuits are not reliable for power supply potentials of three volts and less. 
     BRIEF DESCRIPTION OF THE INVENTION 
     Accordingly, an object of the present invention is to provide an improved charge pump circuit. 
     Another object of the present invention is to provide an improved charge pump circuit for use with power supply voltages less than five volts. 
     Yet another object of the present invention is to provide an improved CMOS recirculating charge pump which substantially eliminates the effects of undesirable threshold voltage drops. 
     In carrying out the above and other objects of the present invention, there is provided, in one form, a circuit for increasing a power supply voltage from a power supply source and providing a boosted output voltage at an output terminal. A diode is coupled between a supply terminal for receiving the power supply voltage and the output terminal. The diode has a predetermined threshold voltage drop associated therewith and prevents current flow from the output terminal to the power supply source. Charge storage means are selectively coupled via a coupling device also having a threshold voltage drop to the output terminal. The charge storage means selectively store the power supply voltage and a boost voltage to provide the boosted output voltage. Compensation means are coupled to the diode, to the coupling device and to the charge storage means for providing compensation for the threshold voltage drops. Therefore, the threshold voltage drops do not degrade the performance of the charge pump. 
     These and other objects, features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates in partial schematic form a charge pump circuit in accordance with the present invention; and 
     FIG. 2 illustrates in schematic form voltage waveforms associated with the circuit of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Shown in FIG. 1 is a charge pump 10 generally comprising diode portion 13, pump portions 15, 16 and 17 and clock portion 18. It should be understood that although specific N-channel and P-channel MOS devices are shown, charge pump 10 may be implemented by completely reversing the processing techniques (e.g. N-channel to P-channel) or by using other types of transistors. 
     Diode portion 13 generally comprises a diode configured N-channel transistor 26 having both a gate and a drain connected to power supply V DD . It should also be apparent that other known semiconductor structures which function as a diode may be used in place of a diode configured MOS transistor. 
     Pump portion 15 generally comprises a capacitor 28 having a first electrode connected to a node 30. A second electrode of capacitor 28 is connected to a complement of a clock signal. An N-channel transistor 34 has a drain connected to power supply V DD , a gate connected to a node 35, and a source connected to node 30. An N-channel transistor 36 has a drain connected to power supply V DD , a gate connected to node 30, and a source connected to node 35. 
     Pump portion 16 generally comprises a capacitor 38 having a first electrode connected to node 35, and a second electrode connected to a clock signal labeled &#34;CLOCK 2&#34;. An N-channel transistor 39 has a drain and a gate connected together to node 35. A source of transistor 39 is connected to a first electrode of a capacitor 40 at a node 41. A second electrode of capacitor 40 is connected to a complement of the clock signal. A first electrode of a capacitor 42 is connected to node 35, and a second electrode of capacitor 42 is connected to a node 43. An N-channel transistor 45 has a source connected to node 35, and both a gate and a drain connected together to node 43. A source of an N-channel transistor 47 is connected to node 43, and both a gate and a drain of transistor 47 are connected to the first electrode of capacitor 40 at node 41. 
     Pump portion 17 generally comprises a capacitor 49 having a first electrode connected to a node 50, and a second electrode connected to the complement of the clock signal. An N-channel transistor 52 has a drain and a gate connected together to node 50, and a source connected to a first electrode of a capacitor 53. A second electrode of capacitor 53 is connected to a clock signal labeled &#34;CLOCK 1&#34;. A first electrode of a capacitor 54 is connected to node 50, and a second electrode of capacitor 54 is connected to a node 56. An N-channel transistor 58 has a source connected to node 50, and both a gate and a drain connected together to node 56. An N-channel transistor 60 has a source connected to node 56, and both a drain and a gate connected together and coupled to the first electrode of capacitor 53. 
     An N-channel transistor 63 has a drain connected to node 35, a gate connected to node 43 and a source connected to node 50. An N-channel transistor 64 has a drain connected to node 50, a gate connected to node 56 and a source connected to an output terminal 66. A capacitor 67 has a first electrode connected to output terminal 66 and a second electrode connected to a second supply voltage, say V SS  . In the illustrated form, supply voltage V SS  is less positive than supply voltage V DD . 
     Clock portion 18 generally comprises an inverter 70 having an input for receiving a clock signal labeled &#34;CLOCK&#34; and an output connected to an input of an inverter 71. An output of inverter 71 provides the &#34;CLOCK 1&#34; signal and is connected to the second electrode of capacitor 53 at a node 72 and is connected to an input of an inverter 73. An output of inverter 73 is connected to a first input of a NOR gate 75 at node 74. A second input of NOR gate 75 is connected to an output of inverter 70. An output of NOR gate 75 is connected to an input of an inverter 76 which has an output connected to an input of an inverter 77. An output of inverter 77 provides the &#34;CLOCK 2&#34; to the second electrode of capacitor 38. 
     Referring to associated waveforms in FIG. 2, the operation of charge pump 10 may be more readily understood. The waveforms of FIG. 2 represent steady state circuit conditions and do not illustrate initial start-up voltage conditions. Effects of parasitic capacitance are also not illustrated in the FIG. 2 waveforms but will be discussed below. A square wave clock signal which oscillates between zero volts or ground potential and the power supply voltage V DD  is coupled to the input of clock portion 18 at the input of inverter 70. For the purpose of explanation, assume that charge pump 10 is in a steady state of operation and that the clock signal is initially at a high logic level (i.e. the inverse clock is at zero volts) before transitioning to the zero volt potential. Since the inverse of the clock signal potential is coupled to capacitor 28, capacitor 28 charges to the supply voltage V DD  potential during this time period because node 30 is at the V DD  potential and the clock signal is at zero volts. Therefore, in addition to other circuit conditions to be explained below, the voltage at node 30 denoted as &#34; V 30  &#34; in FIG. 2 is initially at V DD . However, the voltage at node 30 will be equal to 2V DD  volts as shown in FIG. 2 during low cycles of the clock signal. The voltage 2V DD  occurs at node 30 during low clock cycles in the following way. Simultaneous to the charging of capacitor 28 to V DD , node 35 is being boosted above V DD  volts toward 2V DD  by capacitor 38 and the CLOCK 2 signal. The threshold voltage drops associated with all of the diode configured transistors of charge pump 10 are each presumed substantially equal and each is designated by V T . Therefore, node 35 is at a potential of approximately 2V DD . When the clock signal transitions to V DD , the lower or second electrode of capacitor 28 is coupled to ground and node 30 initially transitions to V DD  volts. A very short delay period later, the CLOCK 2 signal is coupled as a high level signal to capacitor 38. In response, node 35 transitions from nearly V DD  to substantially 2V DD . The voltage potential at node 35 makes transistor 34 conductive which couples V DD  to node 30. Since node 35 is at a higher voltage than node 30, transistor 36 is nonconductive. When the clock signal transitions again to a low level signal, the voltage at node 30 is increased by V DD  volts and returns to 2V DD  volts. Simultaneously, node 35 drops V DD  volts to a potential of V DD . Node 35 is pulled all the way to V DD  as a result of transistor 36 becoming conductive to directly couple the V DD  power supply terminal to node 35. The next half clock cycle when V DD  is coupled to the second electrode of capacitor 38, the node 35 potential approaches 2V DD . Therefore, capacitors 28 and 38 and transistors 34 and 36 function in combination to eliminate the effect of the threshold voltage drops between V DD  and node 35 and between V DD  and node 30. Transistor 26 functions to allow start-up of operation of transistors 34 and 36 and capacitors 28 and 38. The resulting voltage at node 35 varies between a full V DD  potential and a boosted 2V DD  potential. 
     In operation, the boosted voltage of 2V DD  at node 35 is selectively coupled to node 50 via coupling transistor 63 where the voltage is boosted another V DD  by capacitor 49. The voltage at node 50 is desired to vary between 2V DD  and 3V DD  and is selectively coupled to capacitor 67 when the voltage is 3V DD . Therefore, the output voltage is charged onto capacitor 67 and provided as a constant 3V DD . However, when the voltage at node 35 is coupled to node 50, the voltage at node 35 would be reduced by the threshold voltage drop of transistor 63 if transistor 63 were connected in a conventional diode configuration. Therefore, transistors 39, 45 and 47 and capacitors 40 and 42 function in combination to substantially eliminate the threshold voltage drop of transistor 63 so that the full potential of 2V DD  is coupled to node 50. 
     In the illustrated form, the voltage at node 41 varies between four distinct voltage potentials as the complement clock signal varies between zero and V DD  volts. Assume that the CLOCK 2 signal is initially at V DD  and the complement clock signal at node 74 is at zero volts. The voltage potential of 2V DD  at node 35 charges capacitor 40 via transistor 39 which is conductive. Therefore, the voltage at node 41 is (2V DD  -V T ). When the CLOCK 2 signal transitions to zero volts and the complement clock signal is at V DD , node 35 transitions to V DD  and node 41 is boosted to (3V DD  -V T ). A voltage of substantially (2V DD ) minus a threshold voltage drop (V T ) exists across transistors 45 and 47. Capacitor 40 is therefore discharged via transistors 45 and 47 until node 41 reaches (V DD  +2V T ) and node 43 reaches (V DD  +V T ). 
     It should be readily apparent that a threshold voltage has been charged onto capacitor 42 when the clock signal is at zero volts. Since capacitor 42 is connected between the gate and drain of transistor 63, capacitor 42 pre-biases transistor 63 with a threshold voltage. Transistor 63 therefore functions as a diode configured transistor with no threshold voltage drop. If transistor 45 is fabricated with the same control electrode dimensions as transistor 63, transistors 45 and 63 have substantially the same threshold voltage. Therefore, the threshold voltage of transistor 45 which is stored onto capacitor 42 provides the correct bias across the gate and source of transistor 63 to cancel the threshold voltage drop of transistor 63. As a result, the voltage at node 50 will vary substantially between 2V DD  and 3V DD  as the lower or second electrode of capacitor 49 varies between zero and V DD  volts. Coupling transistor 64 has a threshold voltage drop associated therewith which is compensated in an analogous manner by transistors 52, 58 and 60 and capacitors 53 and 54. The transistor dimensions of transistors 45, 63 and 58, 64 may be adjusted for less drive voltage to reduce reverse leakage current through transistors 63 and 64. The present invention provides a significant advantage over previous charge pumps in that large output voltages may be provided from supply voltages of less than five volts. Knowing that the voltage differential between node 35 and node 41 must be equal to at least two threshold voltage drops, a theoretical minimium value of V DD  may be readily determined. Since 
     
         V.sub.41(max) -V.sub.35(min) ≧2V.sub.T 
    
     must be satisfied in order to charge a compensating threshold voltage onto capacitor 42, it follows that the minimum value for V DD  is: 
     
         V.sub.DD ≧(3/2) V.sub.T. 
    
     For supply voltage values less than (3/2) V T , the threshold voltage drop across transistor 63 cannot be cancelled completely and the output voltage of charge pump 10 will be reduced from the intended value. However, for MOS processes in which a transistor threshold voltage varies between one and two volts, charge pump 10 is fully functional for supply voltages as low as between two and three volts. 
     In one form, the output voltage may be limited by connecting node 50 to power supply voltage V DD  via a conventional diode clamp (not shown) such as two series connected diode configured N-channel MOS transistors. The purpose of such a diode clamp would be to limit the output voltage to a predetermined maximum value if the power supply value is subject to wide variation. 
     Clock portion 18 functions to coordinate the switching of the charge boosting of nodes 30, 35 and 50. A transition of a clock signal is initially reflected by CLOCK 1 which affects the charging and discharing of capacitor 53. When the complement clock signal transitions, the voltage at nodes 30, 41 and 50 changes in direct response. After the bias voltage of transistor 36 is established, the CLOCK 2 signal transitions to change the voltage at node 35. It should be apparent that many other types of clock logic circuits could be used to effect the required switching. A significant aspect of the clock timing provided by clock portion 18 is the fact that transistor 36 should be made nonconductive before capacitor 38 is charge boosted so that the charge on capacitor 38 does not leak back to the V DD  power supply. Additionally, the second electrodes of capacitors 40 and 53 should be clocked before nodes 35 and 50 are clocked, respectively. By first clocking capacitors 40 and 53, circulation of charge thru transistors 39, 45 and 47 and capacitor 42 begins immediately after a clock signal transition. Otherwise, the charging and discharging action of capacitors 38 and 49 by other coupled devices in charge pump 10 could inhibit charge circulation thru transistors 39, 45 and 47 and capacitor 42. 
     By now it should be apparent that a charge pump has been provided which operates at low supply voltages below five volts as well as at higher voltages. The present invention may be practised with one or more pump stages such as stage 16 depending upon an actual value of output voltage desired. Although the detailed description of the present invention does not acknowledge the effects of parasitics associated with the various nodes of pump 10, pump 10 remains effective in providing an accurate amplified output voltage at node 66 even when charge sharing of the nodal voltages occurs with parasitic capacitance. 
     While an embodiment has been disclosed using certain assumed parameters, it should be understood that certain obvious modifications to the circuit or the given parameters will become apparent to those skilled in the art, and the scope of the invention should be limited only by the scope of the claims appended hereto.