Abstract:
A method of assembling a package having an exposed die comprising the following steps. A die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to fabrication of semiconductor devices, and more specifically to packaging integrated circuits.  
         BACKGROUND OF THE INVENTION  
         [0002]    Packaged integrated circuit (IC) having plastic, epoxy or resin packages encapsulating the die (semiconductor chip) and a portion of the lead frame and leads are produced using a variety of methods.  
           [0003]    U.S. Pat. No. 5,891,377 to Libres et al. describes lead frames, mold chases and mold flashes in a dambarless leadframe process.  
           [0004]    U.S. Pat. No. 4,615,857 to Baird describes an encapsulating method for reducing flash.  
           [0005]    U.S. Pat. No. 6,309,916 B1 to Crowley et al. describes a method of molding a plastic body of a semiconductor package.  
           [0006]    U.S. Pat. No. 5,949,132 to Libres et al. describes a method and apparatus for encapsulating an integrated circuit die and leadframe assembly using dambarless leadframes.  
         SUMMARY OF THE INVENTION  
         [0007]    Accordingly, it is an object of the present invention to provide a improved method of assembling an integrated circuit package with an exposed die back.  
           [0008]    Other objects will appear hereinafter.  
           [0009]    It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:  
         [0011]    [0011]FIGS. 1 and 2 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention and illustrating non-collapsible copper pillars and optional solders.  
         [0012]    [0012]FIG. 3 schematically illustrates in cross-sectional representation an alternate embodiment of the present invention and illustrating non-collapsible pillars and optional solders.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0013]    Initial Structure  
         [0014]    As shown in FIG. 1, a encapsulated package  30  includes a die  20  having a backside  22  and attached to a substrate  10  by connectors  15 . Encapsulate  12  surrounds the die  20 .  
         [0015]    Die  20  is preferably a wafer comprised of silicon (Si), germanium (Ge), a semiconductor chip or silicon-on-insulator (SOI) and is more preferably a semiconductor chip, such as a flip-chip, comprised of silicon.  
         [0016]    Substrate  10  may be a leadframe, preferably such as a metal leadframe, flex, PCB, tape, or a laminate substrate.  
         [0017]    Connectors  15  may comprise, for example, pillars  14 , or pillars  14  and underlying solders  16 . Pillars are preferably comprised of a conductive metal such as copper and are more preferably copper. Solders  16  are preferably comprised of a tin composition such as a tin/lead composition or a lead-free solder material.  
         [0018]    In one option of the preferred embodiment, connectors  15  comprise non-collapsible pillars  14  with underlying solders  16 . Non-collapsible pillars, as the name implies, do not collapse or are not compressed during fabrication and processing of the encapsulated package  30  so that the minimum thickness of the connectors  15  are known and constant during the processing of the present invention which allows for a much tighter tolerance and thus a smaller backside exposure process  24  removal tolerance is achievable as the thickness of the die  20  and substrate  10  are precisely known.  
         [0019]    U.S. patent application Ser. No. 09/564,382, filed Apr. 27, 2000, entitled “Improved Pillar Connections For Semiconductor Chips And Method of Manufacture” describes formation of a non-collapsible pillar and is incorporated by reference herein.  
         [0020]    Encapsulate  12  is preferably comprised of a mold compound or an epoxy material and is more preferably a mold compound.  
         [0021]    Exposing the Backside  22  of Die  20   
         [0022]    As shown in FIG. 2, the backside  22  of die  20  is exposed using backside exposure process  24  that also removes at least the portion of the encapsulate  12  overlying die  20  and provides for a fine polished surface  22 ′ (Ra) to improve the reliability by reducing die cracking. Backside exposure process  24  is preferably a mechanical backside exposure process, a chemical backside exposure etching process, a laser backside exposure etching process or a plasma backside exposure etching process. Regardless of which specific backside exposure process  24  is used, it exposes a generally thinned die  20 ′ backside  22 ′.  
         [0023]    The mechanical backside exposure process  24  preferably uses mechanical grinding of the encapsulated package  30  overlying the backside  22  of the die  20  to at least expose the backside  22  of the die  20  and preferably also removing a portion of the die  20  to form a thinner encapsulated package  30 ′ having a thinner die  20 ′. The mechanical grinding backside exposure process  24  preferably uses a grinding machine for polishing of the parts with different grades of sandpaper. When the desired thickness is approached, a fine grade of sandpaper is used to give a fine polished surface  22 ′ of the bottom die  20 ′.  
         [0024]    If a chemical backside exposure etching process  24  is used, it is preferably a chemical that will etch/react with the mold compound and silicon chip and will remove the mold compound at about the same rate as the silicon ship.  
         [0025]    If a laser backside exposure etching process  24  is used, it is preferably employs a short wavelength laser, e.g. a green laser, that will not damage the electrical properties of the chip.  
         [0026]    If a plasma backside exposure etching process  24  is used, it is preferably employs a bombardment and etch-type process.  
         [0027]    The backside exposure process  24  continues until the die  20 /package  30  achieves the desired thickness.  
         [0028]    Regardless of which specific backside exposure process  24  is used, the rate of removal of the encapsulate  12  and the rate of removal of the die  20  are about the same and the desired thickness of the thinned package  30 ′ is preferably from about 0.3 to 0.7 mm and more preferably from about 0.5 to 0.7 mm that includes a substrate  10  thickness of preferably from about 0.13 to 0.20 mm, a connector  15  thickness of preferably about 0.10 mm, a die  20  thickness of from about 0.10 to 0.3 mm and more preferably from about 0.15 to 0.2 mm.  
         [0029]    In any event, the thinned die  20 ′ is thinned to not less than about 0.10 mm.  
         [0030]    The exposure of the thinned backside  22 ′ of the thinned die  20 ′ provides better thermal performance.  
         [0031]    Use of Heatsink  26 —FIG. 3  
         [0032]    As shown in FIG. 3, in an alternate embodiment, a heatsink  26  may then be affixed to the thinned exposed backside  22 ′ of the thinned die  20 ′ to provide for even better heat dissipation performance. Heatsink may include optional fins  30  as shown in FIG. 3.  
         [0033]    Heatsink  26  is preferably comprised of a good conductive heat material. Heatsink  26  can be grounded if necessary, depending upon the electrical design of the chip, along with the die to provide electrical grounding of the die. Heatsink  26  may be grounded using a ground bond or a ground bond cable (both represented as at  32  in FIG. 3) bonded to the heatsink  26  (as shown in FIG. 3) or to the optional fins  30 , if used.  
       ADVANTAGES OF THE INVENTION  
       [0034]    The advantages of one or more embodiments of the present invention include:  
         [0035]    1) it is not necessary to back grind the wafer as thinning of the wafer can be done in the same processes;  
         [0036]    2) there is not need to have a tailor-made mold chase to form the encapsulate over the die so as to expose the die backside;  
         [0037]    3) no extra processes or materials (such as tape) are required to expose the die backside;  
         [0038]    4) there are no remaining mold flashes or bleed on the exposed top of the die that must be removed as the backside exposure process also removes any mold flashes or bleed;  
         [0039]    5) the package reliability is improved;  
         [0040]    6) a thinner package may be achieved;  
         [0041]    7) better thermal performance is achieved;  
         [0042]    8) die cracking is reduced; and  
         [0043]    9) electrical grounding of the die is possible.  
         [0044]    While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.