Abstract:
A delay circuit that is insensitive to variations in an input signal voltage level has a voltage clamp at its input terminal to fix the input voltage level so as to remove the sensitivity of the delay circuit to the variations in the input signal voltage level and the power supply voltage source. A voltage independent delay circuit is composed of a first inverter circuit, a voltage clamping circuit, a delay capacitor, and a second inverter circuit. The first inverter circuit has an input terminal and an output terminal. A first output signal at the output terminal is an inverse of an input signal at the input terminal. The voltage clamping circuit is connected between the output terminal and the input terminal of the first inverter circuit to fix a voltage swing of input signal to a first voltage level. The delay capacitor connected to the output terminal of the first inverter to establish a transition time of the first output signal. The second inverter has an input terminal connected to the output terminal of the first inverter circuit and an output terminal. A second output signal at the output terminal of the second inverter is delayed from the input signal and the delay is independent of a final voltage level of the input signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to delay circuits within an integrated circuit placed within a signal path to compensate for a delay difference of the signal path with another signal path to appropriately align arrival of signals on the separate signal paths. More particularly, this invention relates to delay circuits that have delays that are generally independent of the voltage level of the signals on the signal path. 
     2. Description of the Related Art 
     An integrated circuit is formed of many circuits performing sets of interdependent functions. For instance, in a Dynamic Random Access Memory (DRAM) the address signals arrive at a decode function to select the desired memory cell or cells to be read from or written to. At appropriate timing intervals the control signals, such as Row Address Strobe (RAS), Column Address Strobe (CAS), Chip Enable (CE), and clock, arrive at a control function that will generate the appropriate timing signals necessary to gate the word-line activation signals (WL n ) to place a word-line signal on a desired row of an array of memory cells. The row of memory cells is activated, and in a read operation, a charge present within the memory cell flows to an attached bit-line. The voltage level present on the bit-line is determined by the level of charge within the memory cell. To sense the voltage level on a bit-line a sense amplifier must be activated at the correct time to sense the voltage level of the bit-line to determine the state of the data retained in the memory cell. The signals that activate the word-line decoder and the bit-line sense amplifier have a common initiation, but must occur at separate times. The timing for the two paths becomes critical. 
     One of the factors that influence the relative occurrence of the two signals is the voltage level of each signal. In one instance, the delay for one path, for example, the word-line decode and word-line activation, may be naturally insensitive to the voltage level of the signals traversing the path. However, the delay of the second path, in this case the sense line activation signal, may be dependent upon the voltage level of the signal. 
     Refer now to FIG. 1 for a general discussion of the impact of the differences in delay of two signals. In FIG. 1, a first signal V 1  traverses a first delay circuit DC 1 , and a second signal V 2  traverses a second delay circuit DC 2 . The delayed version of the first signal V 1 d and the delayed version of the second signal V 2 d are combined in the functional block F 1  according to the function V 0 =H(V 1 , V 2 ). Any variations in the delay of the first delay circuit DC 1 , or second delay circuit DC 2  due to voltage variations (either the power supply voltage level or the voltage levels of the first signal V 1  or the second signal V 2  affect the results of the output voltage V 0  of the functional circuit F 1 . 
     Refer to FIG. 2 for further explanation of this effect. In FIG. 2, the delay of the first delay circuit DC 1  is designated d 1  and the delay of the second delay circuit DC 2  is designated d 2 . If the first delay is essentially dependent only on such parameters as the line resistance and parasitic capacitances such as for the word-lines and bit-lines of a DRAM memory array, the delay is relatively constant and can be accounted for. However, if the second delay circuit DC 2  is an active delay circuit used to compensate in the differences in time between the first signal V 1 , and the second signal V 2 , the second delay d 2  as explained hereinafter has a dependency on the voltage level of the second signal V 2 . When the variation in the voltage level of the second signal V 2  is too great, the delay d 2  of the second delay circuit may vary so as to corrupt the output voltage V 0 . In the example of a DRAM, the second delay circuit is an active delay circuit used to delay the sense amplifier activation signal until the voltage level on the bit-lines is set to indicate the level of charge present on the memory cell. If the voltage level of the original sense amplifier activation signal varies, then the magnitude of the delay time d 2  varies and the sense amplifier may sense the incorrect data. 
     Refer now to FIG. 3 for a description of an active delay circuit. The basic active delay circuit consists of two inverters connected serially with the output of the first inverter I 1  connected to the input of the second inverter I 2 . The capacitor C 1  is connected to the junction of the output of the first inverter I 1  and the input of the second inverter I 2 . The input of the first inverter I 1 , receives the input signal V IN . The output A of the first inverter I 1  provides a voltage signal that is the inverse of the input signal V IN  The transition time of the output A of the first inverter I 1 , is determined by the value of the capacitor C 1 . 
     The voltage level of the output V 0  at the second inverter I 2  is the inverse of the voltage level at the input of the second inverter I 2 . The threshold at which the output V OUT  of the second inverter transitions between voltage levels is thus delayed by the change in transition time determined by the value of the capacitor C 1 . 
     The inverters I 1  and I 2  of FIG. 3 a  are generally structured as shown in FIG. 3 b . The input terminal of the inverter is connected to the gates of the p-type metal oxide semiconductor (MOS) transistor P 1  and n-type (MOS) transistor N 1 . The source of the p-type MOS transistor P 1  is connected to the power supply voltage source V DD , and the source of the n-type MOS transistor N 1  is connected to the ground reference point. The drains of the p-type MOS transistor P 1  and the n-type MOS transistor N 1  are connected together to form the output terminal of the inverter. The output terminal is connected to a load capacitor C L  that simulates the wiring capacitances and input capacitances of subsequent circuits. 
     The output voltage V CL  at the output terminal during a transition from a low voltage level to a high voltage level is determined by the formula:          V   CL     =       Q     C   L       =       t   *     I   DSP         C   L                                
     where: 
     Q is the charge present on the load capacitor. 
     C L  is the value of the load capacitor. 
     t is the time of the transition of the output signal. 
     I DSP  is the drain-to-source saturation current of the p-type MOS transistor P 1  and is proportional to the square of the input voltage V IN . That is: 
     
       
         I DSN =(V DD −V IN(L) ) 2 . 
       
     
     Likewise, the voltage V CL  at the output terminal during a transition from a high voltage level to a low voltage level is determined by the formula:          V   CL     =       Q     C   L       =       t   *     I   DSN         C   L                                
     where: 
     I DSN  is the drain-to-source saturation current of the n-type MOS transistor N 1  and is also proportional to the square of the input voltage V IN . That is: 
     I DSN =V IN(L)   2 =V DD   2    
     because V in =V DD  when V in  high. 
     FIG. 4 illustrates the plots of the waveforms at the input terminal V IN  of the first inverter I 1 , the output A of the first inverter I 1  and the output V OUT  of the second inverter I 2 . As described above, the output A of the first inverter I 1  has a transition from a high voltage level to a low voltage level that is proportional to the drain-to-source saturation current of the n-type MOS transistor N 1  and thus proportional to the square of the input voltage level V IN . A variation in the voltage level of the input voltage V IN  causes a variation in the delay d 3  between the transition of the input voltage level V IN  and the output voltage level V OUT . 
     Likewise, the output A of the first inverter I 1  has a transition from a low voltage level to a high voltage level that is proportional to the drain-to-source saturation current of the p-type MOS transistor P 1  and thus proportional to the square of the difference between the power supply voltage source V DD  and the input voltage level V IN . Also, as stated above, any variation in the voltage level of the input voltage level V IN  causes a variation in the delay between the transition of the input voltage level V IN  and the output voltage level V OUT . 
     As described in FIG. 1, any variation in the delays d 3  and d 4  will affect the output signal of the functional circuit F 1  and thus may cause error conditions. In a DRAM this error, condition may be a misreading of the data transferred from a memory cell. 
     U.S. Pat. No. 5,317,219 and U.S. Pat. No. 5,175,452 (Lupi, et al.) each describe a programmable compensated digital delay circuit. A signal-to-be-delayed is provided to a group of time delay cells which, are selectively capable of being interconnected, thus forming one or more delay configurations. In each delay cell, selectable capacitive elements are arrayed in a weighted manner and a memory programmably selects the capacitive elements by switching differently rated capacitive elements into and out of the circuit. Selectable current sources are arrayed in a weighted manner, and another memory programmably selects the current sources by switching differently rated current sources into and out of the circuit. The delay circuit includes internal compensation and uses a ring oscillator for temperature and power supply compensation. A pulse-width distortion compensation device is provided to compensate the delay line for switching non-linearities. The pulse-width compensation portion of the device serially connects an even number of complementary delay elements to cancel transfer function deviations. 
     U.S. Pat. No. 5,300,837 (Fischer) teaches a delay compensation technique for buffers. An integrated circuit has a signal path including a first circuit that introduces a propagation delay that decreases with circuit conditions and process speed in series with a second circuit that introduces a propagation delay that increases with circuit conditions and process speed. The circuit conditions and process speed are sensed and the duration of the propagation delay of the second circuit varied such that the total propagation delay remains within a predetermined range over circuit condition and process speed variations. 
     U.S. Pat. No. 5,315,550 (Tobita) describes a dynamic random access memory having sense amplifier activation delayed based on operation supply voltage. The dynamic random access memory operates with different power supply voltages and provides sufficient operating margin for each rated voltage. The dynamic random access memory comprises a circuit for generating a signal for defining operation speed/timing of a sense amplifier depending on the operation supply voltage, and a circuit for driving the sense amplifier in response to an output of a defining signal generating circuit. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a delay circuit that is insensitive to variations in a power supply voltage level. 
     Another object of this invention is to provide a delay circuit having a voltage clamp at its input terminal to fix the input voltage level so as to remove the sensitivity of the delay circuit to variations in the power supply voltage level. 
     Further, another object of this invention is to provide an integrated circuit having multiple functional circuits connected by signal paths to other functional circuits where the delay of one signal path is generally insensitive to the voltage level of the signal on that path and a second path contains a delay circuit that is also insensitive to the voltage level of the signal of the second path. 
     To accomplish these and other objects a voltage independent delay circuit is composed of a first inverter circuit, a voltage clamping circuit, a delay capacitor, and a second inverter circuit. The first inverter circuit has an input terminal and an output terminal. A first output signal at the output terminal is an inverse of an input signal at the input terminal. The voltage clamping circuit is connected between the output terminal and the input terminal of the first inverter circuit to fix a voltage swing of input signal to a first voltage level. The delay capacitor connected to the output terminal of the first inverter to establish a transition time of the first output signal. The second inverter has an input terminal connected to the output terminal of the first inverter circuit and an output terminal. A second output signal at the output terminal of the second inverter is delayed from the input signal and the delay is independent of a final voltage level of the input signal and the power supply voltage source level. 
     To provide a delay that is independent of the final voltage for an transition of the input signal from a first voltage level to a second voltage level, the voltage clamping circuit is composed of diode connected first and second MOS transistors of a first conductivity type and a gating third MOS transistor of the first conductivity type. The gate and drain of the first MOS transistor of the first conductivity type are connected to the output terminal of the first inverter. The source of the first MOS transistor is connected to the gate and drain of the second MOS transistor of the first conductivity type The drain of the third MOS transistor of the first conductivity type is connected to a source of the second MOS transistor of the first conductivity type. The third MOS transistor of the second conductivity type has a gate connected to the output terminal of the first inverter, and a source connected to a reference voltage terminal. 
     The voltage clamping circuit may optionally contain a diode connected first MOS transistor of a second conductivity type. The first MOS transistor of the second conductivity typed has a gate and drain connected together connected to the connection of the source of the second MOS transistor of the first conductivity type and the drain of the third MOS transistor of the first conductivity type, and a source connected to the output terminal of the first inverter. The first MOS transistor of the second conductivity type provides compensation for a MOS transistor of the second conductivity type connected to the output terminal of a circuit providing the input signal. 
     To provide a delay that is independent of the final voltage for a transition of the input signal from the second voltage level to the first voltage level, the voltage clamping circuit is composed of diode connected second and third MOS transistors the second conductivity type and a gating fourth MOS transistor of the second conductivity type. The second MOS transistor of the second conductivity type has a gate and drain connected together and to the input terminal of the first inverter. The third MOS transistor of the second conductivity type has a gate and drain connected together and connected to a source of the second MOS transistor of the second conductivity type. The fourth MOS transistor of the second conductivity type has a drain connected to a source of the third MOS transistor of the second conductivity type, a gate connected to the output terminal of the first inverter, and a source connected to a power supply voltage terminal. 
     The voltage clamping circuit may optionally have a diode connected fourth MOS transistor of the first conductivity type. The fourth MOS transistor of the first conductivity type has a gate and drain connected together and connected to the connection of the source of the third MOS transistor of the second conductivity type and the drain of the fourth MOS transistor of the second conductivity type, and a source connected to the output terminal of the first inverter. 
     A second embodiment of the voltage clamping circuit is composed of diode connected fifth and sixth MOS transistors of the second conductivity type, and a gating fifth MOS transistor of the first conductivity type. The fifth MOS transistor of the second conductivity type has a gate and drain connected together, and a source connected to the input terminal of the first inverter. The sixth MOS transistor of the second conductivity type having a gate and drain connected together, and a source is connected to the gate and drain of the fifth MOS transistor of the second conductivity type. The gating fifth MOS transistor of a first conductivity type has a drain connected to the gate and drain of the sixth MOS transistor of the second conductivity type, a gate is connected to the output terminal of the first inverter, and a source connected to a reference voltage terminal. 
     The second embodiment of the voltage clamping circuit is optionally composed of a diode connected sixth and seventh MOS transistor of the first conductivity type, and a gating seventh MOS transistor of the second conductivity type. The sixth MOS transistor of the first conductivity type has a gate and drain connected together, and a source connected to the input terminal of the first inverter. The seventh MOS transistor of the first conductivity type has a gate and drain connected together, and a source connected to gate and drain of the sixth MOS transistor of the first conductivity type. The seventh MOS transistor of the second conductivity type has a drain connected to gate and drain of the seventh MOS transistor of the first conductivity type, a gate connected to the output terminal of the first inverter, and a source connected to a power supply voltage terminal. 
     An alternate embodiment of the voltage independent delay circuit is to delay a first transition of a primary input signal while not delaying a second transition of the primary input signal. To accomplish this the voltage independent delay circuit additionally has a third and fourth inverter and the second inverter is replaced with a logic gate. A first input of the logic gate is connected to the output of the first inverter. The third inverter has an input connected to receive the primary input signal and an output terminal connected to a second input terminal of the logic gate. The second transition of the primary input signal causes the output signal to transition with minimum delay, while the first transition of the primary input signal is delayed in time to form the delayed transition of the output signal. The third inverter has an input terminal connected to the output terminal of the second inverter and an output terminal connected to the input terminal of the first inverter whereby the first input signal is an inverse of an output of the second inverter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of signal paths connected to a functional circuit on an integrated circuit. 
     FIG. 2 is a plot of the waveforms showing delays in signals experienced on the signal paths to the functional circuit. 
     FIG. 3 a  is a schematic diagram of a delay circuit of the prior art. 
     FIG. 3 b  is a schematic diagram of an inverter of the delay circuit of the prior art. 
     FIG. 4 is a plot of the waveforms of the signals in the delay circuit of FIG. 3 a.    
     FIG. 5 is a schematic diagram of a voltage independent delay circuit of this invention. 
     FIG. 6 is a plot of the waveforms of the signals in the delay circuit of FIG.  5 . 
     FIG. 7 is a schematic diagram of a first embodiment of a voltage independent delay circuit of this invention. 
     FIG. 8 is a schematic diagram of a second embodiment of a voltage independent delay circuit of this invention. 
     FIG. 9 is a plot of the voltage waveforms of the signals within the first embodiment of a voltage independent delay circuit of FIG.  7 . 
     FIG. 10 is a schematic diagram of a third embodiment of a voltage independent delay circuit of this invention. 
     FIG. 11 is a schematic diagram of an integrated circuit DRAM illustrating a voltage independent delay circuit of this invention. 
     A fourth embodiment of the delay circuit of this invention is illustrated in 
     FIG. 12 is a schematic diagram of a fourth embodiment of a voltage independent delay circuit of this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Refer now to FIG. 5 to discuss the function and structure of a voltage independent delay circuit of this invention. The inverters I 3  and I 4  are serially connected output to input with the output of inverter I 3  being connected to the input of inverter I 4 . The inverter I 3  receives and inverts the input signal V IN  to form the signal at the interconnection B. The signal at the interconnection B is then received and inverted by the inverter I 4  to form the output signal V OUT . 
     The capacitor C 1  is placed between the interconnection B and the ground reference point and causes the transition of the signal present at the interconnection B to decrease or slow similarly to that described in FIG.  1 . The voltage clamping circuit is placed between the output and the input of the first inverter I 3 . The voltage clamping circuit fixes or clamps the voltage level of the input signal V IN  to a fixed level and prevents the maximum amplitude that is possible for the input signal V IN  from being present at the input of the inverter I 3 . 
     When the output signal of the first inverter I 3  has traversed the threshold voltage of the second inverter I 4 , thus causing the output voltage V OUT  to transition from one voltage level to a second voltage level, the voltage clamping circuit is disabled, preventing any power dissipation when the input signal V IN  is at a steady state. 
     For a more detailed view of the operation of the voltage clamping circuit, refer now to FIG.  6 . As the input signal level V IN  rises from a low voltage level V L  to a high voltage level V H , the voltage clamping circuit activates and fixes or clamps the input voltage V IN  to the first clamp voltage level V clampLH . The output voltage level V B  of the inverter I 3  begins to transition from the high voltage level V H  to the low voltage level V L . As described in FIG. 3, the slope of the transition, and thus the delay d 5 , is determined by the value of the capacitor C 1  and the magnitude of the drain-to-source saturation current I DSN  of the n-type MOS transistor N 1 . As explained, the drain-to-source saturation current I DSN  is proportional to the square of the input voltage level V IN  which is equal to the power supply voltage source V DD . Clamping or fixing the voltage level of the input signal V IN  prevents any variations in the voltage level V H  from previous stages or the power supply voltage source V DD  from having an impact on the magnitude of the delay d 5  of the delay circuit. 
     At the time t 1 , which is subsequent to the transition of the voltage level V B  at the interconnection B exceeding the threshold level of the voltage clamping circuit, the voltage clamping circuit is disabled. Disabling the voltage clamping circuit prevents dissipation of power in the voltage clamping circuit when the input signal V IN  has achieved the high voltage level V H . 
     When the input signal V IN  falls from the high voltage level V H  to the low voltage level V L , the voltage clamping circuit now activates and fixes or clamps the input voltage level V IN  to a second clamp voltage level V CLAMP HL . The output voltage level V B  of the inverter I 3  begins to transition from the low voltage level V L  to the high voltage level V H . Again, as described in FIG. 3, the slope of the transition, and thus the delay d 6 , is determined by the value of the capacitor C 1  and the magnitude of the drain-to-source saturation current I DSP  of the p-type MOS transistor P 1 . As explained, the drain-to-source saturation current I DSP  is proportional to the square of the difference between the power supply voltage source V DD  and the input voltage level V IN . Clamping or fixing the voltage level of the input signal V IN  prevents any variations in the voltage level V H  from previous stages or the power supply voltage source V DD  level from causing an impact on the magnitude of the delay d 6  of the delay circuit. 
     At the time t 2 , which is subsequent to the transition of the voltage level V B  at the interconnection B exceeding the threshold level of the inverter I 4 , the voltage clamping circuit is disabled. Disabling the voltage clamping circuit prevents dissipation of power in the voltage clamping circuit when the input signal V IN  has achieved the low voltage level V L . 
     In certain applications, the delay of the output signal V OUT  from the input signal V IN  is necessary for only one transition of the signal. The second transition of the output signal V OUT  is required to occur with minimal delay from the input signal V IN . FIG. 7 illustrates a first embodiment of this invention where the transition of the output signal V OUT  from a low voltage level V L  to a high voltage level V H  is delayed from the transition of the input signal V IN . The delay circuit has the inverters I 5 , I 6 , and I 7  connected serially output to input. The input of the inverter I 5  is connected to receive the input voltage signal V IN . The output of the inverter I 5  is connected to the input of the inverter I 6  to form the interconnection E. The output of the inverter I 7  is connected to the input of the inverter I 7  to form the interconnection C. The output of the inverter I 7  is connected to the first input of the logic gate U 1  to form the interconnection D. 
     The inverters I 5  and I 6  act as buffer circuits for the input voltage signal V IN . The inverter I 7  and the logic gate perform the functions of the inverters I 3  and I 4  of FIG. 5 described above. The capacitor C 1  is formed from the gate-to-bulk capacitance of an n-type MOS transistor. The source and drain terminals of the n-type MOS transistor are connected to the bulk to add the gate-to-source and the gate-to-drain capacitances to the gate-to-bulk capacitance to form the capacitor C 1 . 
     The voltage clamping circuit is connected between the interconnection D at the output of the inverter I 7  and the interconnection C at the input of the inverter I 7 . Refer to FIG. 9 during the discussion of the operation of the delay circuit of FIG. 7 to understand the voltage and timing of the operation of the delay circuit of FIG.  7 . The voltage clamp fixes or clamps the voltage V C  at the interconnection C, as described above in FIG. 5, for a transition of the voltage level from a low level to a high level. 
     The voltage clamping circuit is formed of the diode connected n-type MOS transistors N 2  and N 3 , the gating n-type MOS transistor N 4 , and the optionally diode connected p-type MOS transistor P 2 . The gate and drain of the n-type MOS transistor N 2  and the source of the p-type MOS transistor P 2  are connected to the interconnection C. The gate and drain of the n-type MOS transistor N 3  are connected to the source of the n-type MOS transistor N2. The gate and drain of the p-type MOS transistor P 2  and the source of the n-type MOS transistor N 3  are connected to the drain of the gating n-type MOS transistor N 4 . 
     As is known in the art, the gate-to-source voltage of the diode connected n-type MOS transistors N 2  and N 3  and the p-type MOS transistor P 2  is a function of the device dimensions and the current through the diode connected n-type MOS transistors N 2  and N 3  and the p-type MOS transistor P 2 . Thus, the clamping voltage at the interconnection C is set by the design of the device dimensions of the diode connected n-type MOS transistors N 3  and N 4  and the diode connected p-type MOS transistor P 2 . 
     As the input voltage level V C  at the input of the inverter I 7  transitions from the low voltage level V L  to the clamping voltage level, the output voltage level V D  at the interconnection D decreases in manner, as described in FIG. 3 a , discharging the capacitor C 1 . Once the voltage level at the interconnection D reaches the threshold voltage V T  of the n-type MOS transistor N 4 , the n-type MOS transistor N 4  turns off and the voltage level at the interconnection C continues to rise to the maximum high voltage level V H . 
     The second input of the logic gate U 1  is connected to the output of the inverter I 5  at the interconnection E. As the voltage level of the input voltage signal V IN  rises from the low voltage level V L  to the high voltage level V H , the voltage level V E  at the interconnection E falls from the high voltage level V H  to the low voltage level V L . In the preferred embodiment, the logic gate U 1  is a logical NOR, thus making the output voltage level V OUT  dependent on the first input connected interconnection D when the voltage level V E  of the second input is at the low voltage level V L . This allows the delay of the delay circuit to be applied to the transition of the output voltage signal V OUT  from a low voltage level V L  to a high voltage level V H  to be delayed from the transition of the input voltage level V IN . However, when the transition of the input voltage signal V IN  traverses from the high voltage level V H  to the low voltage level V L , the voltage level V E  at the interconnection E traverses from the low voltage level V L  to the high voltage level V H , causing the output voltage signal V OUT  to traverse from the high voltage level V H  to the low voltage level V L  with minimum delay. This delay is independent of the delay circuit described above. 
     The optional diode connected p-type MOS transistor P 2  is incorporated in the clamping circuit to provide for variation in the semiconductor process during construction of the p-type MOS transistor P 1  of FIG. 3 b  in the inverter I 6 . A second embodiment to also compensate for the variations of the p-type MOS transistor P 1  in the inverter I 6  is shown in FIG.  8 . 
     The structure and function of the delay circuit of FIG. 8 except the voltage clamping circuit now consists of the diode connected p-type MOS transistors P 3  and P 4  and the gating n-type MOS transistor N 5 . The source of the diode connected p-type MOS transistor P 3  is connected to the interconnection C. The gate and drain of the diode connected p-type MOS transistor P 3  are connected to the source of the p-type MOS transistor P 4 . The gate and drain of the p-type MOS transistor P 4  are connected to the drain of the gating n-type MOS transistor N 5 . The gate of the gating n-type MOS transistor N 5  is connected to the output of the inverter I 7  and the source of the gating n-type MOS transistor N 6  is connected to the ground reference point. 
     As described above, the gate-to-source voltage V gs  of the diode connected p-type MOS transistors P 3  and P 4  is a function of the physical dimensions (W/L) and the current through them. Thus, the clamping voltage level at the interconnection C is determined by the structure of the diode connected p-type MOS transistors P 3  and P 4 . 
     The voltage clamping circuit operates similar to that described in FIG.  7 . If the voltage level of the input voltage signal V IN  is at the low voltage level V L , the voltage level V D  of the interconnection D is at the high voltage level V H , thus turning on the gating n-type MOS transistor N 5 . As the voltage level of the input voltage signal V IN  rises, the voltage level V C  at the interconnection C rises until it reaches the clamping voltage level. This level is greater than the threshold voltage level of the inverter I 7 , but less than the high voltage level VH. This forces the transition time of the voltage at the interconnection D to remain essentially constant and independent of the voltage level of the input voltage signal V IN . When the voltage level V D  has fallen below the threshold voltage V T  of the n-type MOS transistor N 5 , the n-type MOS transistor N 5  turns off and the voltage clamping circuit is disabled to prevent dissipation of power in the voltage clamping circuit when the voltage level of the input voltage signal V IN  is at a steady state. 
     A third embodiment of the delay circuit of this invention is illustrated in FIG.  10 . This embodiment illustrates the structure of the general description of FIG.  5 . The low-to-high voltage clamping circuit V CLAMP LH  provides the necessary delay d 5  of FIG. 6 for a transition of the input voltage signal V IN  from the low voltage level V L  to the high voltage level V H , whereas the high-to-low voltage clamping circuit V CLAMP HL  provides the delay d 6  of FIG. 6 for a transition of the input voltage signal V IN  from the high voltage level V H  to the low voltage level V L . 
     The input of the inverter I 1  is connected to receive the input voltage signal V IN . 
     The output of the inverter I 1  is connected to the input of the inverter I 2  to form the interconnection B. The output of the inverter I 2  transfers the output voltage signal V OUT  to subsequent circuitry. The capacitor C 1  is structured and connected as shown in FIG.  5 . The low-to-high voltage clamping circuit is constructed and functions as the clamping circuit of FIG.  7 . 
     The high-to-low voltage clamping circuit is formed of the diode connected p-type MOS transistors P 5  and P 6 , the gating p-type MOS transistor P 7  and the optional diode connected n-type MOS transistor N 6 . The gate and drain of the diode connected p-type MOS transistor P 5  is connected to the input of the inverter I 1 . The gate and drain of the diode connected p-type MOS transistor P 6  is connected to the source of the p-type MOS transistor P 5 . The source of the p-type MOS transistor P 6  is connected to the drain of the gating p-type MOS transistor P 7 . The source of the gating p-type MOS transistor P 7  is connected to the power supply voltage source. The gate of the p-type MOS transistor P 7  is connected to the output of the inverter I 1 . 
     The gate and drain of the diode connected n-type MOS transistor N 6  are connected to the drain of the gating p-type MOS transistor P 7 . The source of the diode connected n-type MOS transistor N 6  is connected to the input of the inverter I 1 . The diode connected n-type MOS transistor N 6  is used to compensate for variations in process of the n-type MOS transistor N 1  of a circuit generating the input voltage signal V IN . The circuit generating the input voltage signal V IN  is structured similar to that shown in FIG. 3 b.    
     Refer to FIG.  6 . When the voltage level of the input voltage signal V IN  is at the high voltage level V H , the voltage level at the interconnection B is at the low voltage level VL 7  thus turning on the gating p-type MOS transistor P 7 . As the voltage signal of input voltage signal V IN  traverses from the high voltage level V H  to the low voltage level V L , the voltage level V B  at the interconnection B begins to rise as the capacitor C 1  charges. 
     The voltage level of the input voltage signal V IN  only achieves the voltage level V CLAMP HL . This voltage level is fixed and sets the drain-to-source saturation current I DSP  of the p-type MOS transistor P 1  of the inverter I 1  to maintain the delay time d 6  independent of the voltage level of the input voltage signal V IN . 
     When the voltage level V B  of the interconnection B exceeds the threshold voltage V T  of the gating p-type MOS transistor P 7  the p-type MOS transistor P 7  is turned off and the voltage level of the input voltage signal V IN  achieves the high voltage level V H . 
     When the gating p-type MOS transistor P 7  is turned off, the high-to-low voltage clamping circuit is deactivated to prevent dissipation of power during the period of time that the voltage level of the input voltage signal V IN  is at the low voltage level V L . 
     A fourth embodiment of the delay circuit is delay circuit of this invention is illustrated in FIG.  12 . This embodiment illustrates a second version of the structure of the general description of FIG.  5  and function as described above. The low-to-high voltage clamping circuit is constructed and functions as the clamping circuit of FIG.  8 . 
     The high-to-low voltage clamping circuit is formed of the diode connected n-type MOS transistors N 7  and N 8  and the gating p-type MOS transistor P 8 . The source of the diode connected n-type MOS transistor N 7  is connected to the input of the inverter  11 . The gate and drain of the diode connected n-type MOS transistor N 7  is connected to the source of the n-type MOS transistor N 8 . The gate and drain of the p-type MOS transistor P 6  are connected to the drain of the gating p-type MOS transistor P 8 . The source of the gating p-type MOS transistor P 8  is connected to the power supply voltage source. The gate of the p-type MOS transistor P 8  is connected to the output of the inverter I 1 . 
     Refer to FIG.  6 . When the voltage level of the input voltage signal V IN  is at the high voltage level V H , the voltage level at the interconnection B is at the low voltage level V L , thus turning on the gating p-type MOS transistor P 8 . As the voltage signal of input voltage signal VIN traverses from the high voltage level V H to the low voltage level V L , the voltage level V B  at the interconnection B begins to rise as the capacitor C 1 , charges. 
     The voltage level of the input voltage signal V IN  only achieves the voltage level V CLAMP HL . This voltage level is fixed and sets the drain-to-source saturation current I DSP  of the p-type MOS transistor P 1  of the inverter I 1  to maintain the delay time d 6  independent of the voltage level of the input voltage signal V IN . 
     When the voltage level V B  of the interconnection B exceeds the threshold voltage V T  of the gating p-type MOS transistor P 8 , the p-type MOS transistor P 8  is turned off and the voltage level of the input voltage signal V IN  achieves the high voltage level V H . 
     When the gating p-type MOS transistor P 7  is turned off, the high-to-low voltage clamping circuit is deactivated to prevent dissipation of power during the period of time that the voltage level of the input voltage signal V IN  is at the low voltage level V L . 
     It is well known in the art, that the coincidence in timings of address selection and activation of the data sensing circuits within arrays of random access memories are critical to performance of random access memories such as DRAM and static random access memory (SRAM). FIG. 11 illustrates an integrated circuit containing a DRAM incorporating a delay circuit of this invention to minimize the delay variations in an access and activation path of the DRAM. 
     The DRAM circuit has an array of memory cells arranged in rows and columns. The structure of the memory cells is well known in the art. Each row of memory cells is connected to one word-line WL 0 -WLi and each column of memory cells is connected to the bit-lines BL 0 -BLm. 
     The word-lines WL 0 -WLi are connected to the row decoder. A word-line WL 0 -WLi is energized to select a row of memory cells to be activated. The bit-lines lines BL 0 -BLm are connected to sense amplifiers to sense the change in voltage that occurs when a charge from an activated memory cell flows to a bit-line BL 0 -BLm. 
     The row addresses RADDO-RADDK are decoded in the row decoder to choose which of the word-lines WL 0 -WLi is to be activated. The sense amplifier control circuitry provides the activation signals to turn on the sense amplifiers to detect the data stored in the selected memory cells. The timing and control circuits receive the row address strobe (RAS) and the column address strobe (CAS), and generates a select activation signal V S . The control and timing circuit is connected to the row decoder and the sense amplifier control circuit to transfer the select activation signal V S . The select activation signal V S  stimulates the activation of the word-lines WL 0 -WLi and the sense amplifiers. However, to ensure error-free detection of the data from the selected memory cells, the sense amplifiers must be activated at the appropriate time after the activation of the word-lines WL 0 -WLi. A delay circuit is placed between the sense amplifier control and the sense amplifiers to equalize the delays and ensure proper sensing of the data. The propagation delay from the activation of the selected word-line WL 0 -WLi to the arrival of the charge from the memory cell to the sense amplifier is basically independent of the amplitude of the select activation signal V S . However, the propagation delay of the sense amplifier control circuit and the delay circuits would be sensitive to the amplitude of the select activation signal V S  if employing delay circuits of the prior art. The delay circuit employed in the DRAM of FIG. 11 is as shown in FIG.  7  and alternatively in FIG.  8 . The activation of the sense amplifiers must be timed to be delayed to ensure correct sensing of the data. However, the deactivation of the sense amplifiers must occur promptly at the deselecting transition of the select activation signal V S . The delay circuits of FIGS. 7 or  8  provide this feature. 
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.