Abstract:
There is provided a bitline driving circuit and its driving method for minimizing a leakage current flowing between a wordline and a bitline in a power down mode and a self-refresh mode. The bitline driving circuit for reducing a leakage current in a semiconductor memory device includes a main driving block for precharging a bitline pair connected to a sense amplifier with a same voltage level, controlled by a main bitline equalizing signal; a sub driving block for equalizing a voltage level of a bitline pair connected to a cell array voltage in a precharge mode, controlled by a sub bitline equalizing signal; and a bitline isolation block for electrically disconnecting the main driving block and the sub driving block, controlled by a bitline isolation signal.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a semiconductor memory device; and more particularly, to a bitline driving circuit in a semiconductor memory device and its driving method for minimizing a leakage current flowing between a wordline and a bitline in a power down mode and a self-refresh mode. 
   DESCRIPTION OF RELATED ART 
     FIG. 1  is a block diagram of a conventional semiconductor memory device. 
   Referring to  FIG. 1 , the conventional semiconductor memory device  1  includes a control signal input terminal  10  for receiving a control signal such as a column address strobe (CAS) bar signal/CAS, a row address strobe (RAS) bar signal/RAS, a write enable bar signal/WE and an output enable bar signal/OE or the like, an address input terminal  12  for receiving address signals A 1  to An where n is a positive integer, and a data input terminal  14  for transferring input/output data DQ 1  to DQi where i is a positive integer. 
   The conventional semiconductor memory device  1  further includes a control circuit  20 , a memory cell array  30 , an address buffer  35 , a row decoder  40 , a column decoder  45 , a sense amplifier circuit  50 , an input/output circuit  60 , an input buffer  70 , and an output buffer  75 . 
   The control circuit  20  controls whole the operations of the semiconductor memory device  1  in response to the control signal inputted to the control signal input terminal  10 . 
   The memory cell array  30  is provided with a plurality of memory cells arranged in a matrix shape. A wordline is allocated in every row and a bitline is allocated in every column in the memory cell array so that each of the memory cells is arranged at every intersection of the wordline and the bitline. 
   The address buffer  35  supplies the address signal inputted from an exterior to the row decoder  40  and the column decoder  45 , selectively. The row decoder  40  drives at least one wordline among the plurality of the wordlines in response to the row address signal supplied from the address buffer  35 . The column decoder  45  drives at least one bitline among the plurality of the bitlines in response to the column address signal supplied from the address buffer  35 . The sense amplifier circuit  50  incorporates therein a plurality of sense amplifiers. One sense amplifier is provided for every two bitline pair so as to amplify a voltage difference generated between the bitline pairs. 
   The input/output circuit  60  supplies a voltage level of the bitline pair selected by the column decoder  45  to the output buffer  75 . The output buffer  75  amplifies the supplied voltage level so as to output it as the output data DQ 1  to DQi to an exterior. The input buffer  70  amplifies the input data DQ 1  to DQi when the input data DQ 1  to DQi is supplied from an exterior. The input/output circuit  60  receives an amplified input data DQ 1  to DQi and supplies then to the bitline pair selected by the column decoder  45 . 
   As the semiconductor memory device becomes highly integrated and employs a micronized process, there are many difficulties in configuring each pattern on the device. One of the difficulties is a bridge phenomenon between the wordline and the bitline, which incurs a leakage current flowing between the wordline and the bitline. Although there occurs a defect, the semiconductor memory device has relief circuits therein to replace the corresponding wordline and the bitline by the other circuits, to thereby enable the semiconductor memory device to perform a normal operation. However, though the normal operation is enabled in this case, there still exists the leakage current. 
     FIG. 2  is a circuit diagram setting forth a conventional sense amplifier circuit, and  FIG. 3  is a timing diagram of a sense amplifier control signal according to the conventional sense amplifier circuit. 
   (1) In Active Mode (ACT) 
   In case that an upper wordline WL_up is enabled in an active mode (ACT), a bitline isolation high signal BISH becomes in logic high level and a bitline isolation low signal BISL becomes in logic low level, so that a sense amplifier Sense Amp amplifies a data of an upper cell cell_up connected to the upper wordline WL_up. 
   Similarly, in case that a lower wordline WL_down is enabled, the bitline isolation high signal BISH becomes in logic low level and the bitline isolation low signal BISL becomes in logic high level, so that the sense amplifier Sense Amp amplifies a data of a lower cell cell_down connected to the lower wordline WL 13  down. 
   (2) In Precharge Mode (PRE) 
   The bitline isolation high signal BISH and the bitline isolation low signal BISL for isolating each cell cell_up and cell_down from the sense amplifier Sense Amp keep in logic high levels in a precharge mode. In addition, a bitline equalizing signal BLEQ for applying a voltage with the same level to a bitline pair BL and BLB keeps in logic high level. Thus, the bitline pair BL and BLB maintains a predetermined voltage level, i.e., Vcore/2. 
   Meanwhile, though there exists the leakage current Ileak flowing between the wordline and the bitline during the active mode, the amount of the leakage current Ileak is too small in comparison with total amount of active current. However, the bitline pair BL and BLB keeps the predetermined voltage level of Vcore/2 in a standby mode, i.e., the precharge mode in which the bitline equalizing signal BLEQ is in logic high level as depicted as time periods of a, b and c in  FIG. 3 . In this case, the wordline maintains a ground voltage level. Therefore, there occurs a current path from one of the bitline pair BL and BLB to the wordline if there is any error in the process. 
   However, as demands for mobile devices have been increased in company with demands for a high integration of the semiconductor device, the amount of current needed in the power down mode and the self-refresh mode becomes an important issue. That is, since the semiconductor memory device for the mobile device requires a predetermined current for the power down or the self-refresh of which the amount of current is about one-tenth of the current required for the normal semiconductor memory device, the leakage current flowing between the wordline and the bitline becomes a quite amount of current, which can not be neglected, in the semiconductor memory device for the mobile devices. Therefore, it is very important to reduce this leakage current. 
   SUMMARY OF THE INVENTION 
   It is, therefore, an object of the present invention to provide a bitline driving circuit and its driving method for minimizing a leakage current flowing between a wordline and a bitline in a power down mode and a self-refresh mode of a semiconductor memory device. 
   In accordance with an aspect of the present invention, there is provided a bitline driving circuit including: a main driving block for precharging a bitline pair connected to a sense amplifier with a same voltage level, controlled by a main bitline equalizing signal; a sub driving block for equalizing a voltage level of a bitline pair connected to a cell array voltage in a precharge mode, controlled by a sub bitline equalizing signal; and a bitline isolation block for electrically disconnecting the main driving block and the sub driving block, controlled by a bitline isolation signal. 
   In accordance with another aspect of the present invention, there is provided a method for driving a bitline, including the steps of: precharging a bitline pair connected to a sense amplifier with a same voltage level in a power down mode or a self-refresh mode, controlled by a main bitline equalizing signal; applying the same voltage level to a bitline pair connected to a cell array in a precharge mode, controlled by a sub bitline equalizing signal; and electrically disconnecting the bitline pair connected to the sense amplifier and the bitline pair connected to the cell array, controlled by a bitline isolation signal. 
   In accordance with further another aspect of the present invention, there is provided a semiconductor memory device, configured with a plurality of cell array blocks and a plurality of sense amplifiers for amplifying a readout data from the plurality of the cell array blocks, the bitline circuit including: a sub driving block for equalizing a voltage level of a bitline pair connected to the plurality of cell array blocks in a precharge mode, controlled by a sub bitline equalizing signal; a bitline isolation block for electrically disconnecting the main driving block and the sub driving block, controlled by a bitline isolation signal, wherein the sub driving block in the other cell array block among the plurality of the cell array blocks except the cell array block selected for a refresh operation is turned off so that the bitline pair is electrically isolated from cells of the other cell array block in the self-refresh mode, controlled by the sub bitline equalizing signal. 
   In accordance with still further another aspect of the present invention, there is provided a method for driving a bitline in a semiconductor memory device, the semiconductor memory device being configured with a plurality of cell array blocks and a plurality of sense amplifiers for amplifying a readout data from the plurality of the cell array blocks, the method including the steps of: precharging a bitline pair connected to a sense amplifier to a same voltage level in a self-refresh mode, controlled by a main bitline equalizing signal; turning off the sub driving block in the other cell array block among the plurality of the cell array blocks except the cell array block selected for a refresh operation, wherein the sub driving block is controlled by a sub bitline equalizing signal in the self-refresh mode; and c) electrically disconnecting the bitline pair and a cell in the other cell array block, controlled by a bitline isolation signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram of a conventional semiconductor memory device; 
       FIG. 2  is a circuit diagram of a conventional sense amplifier circuit; 
       FIG. 3  is a timing diagram of a sense amplifier control signal according to the conventional sense amplifier circuit; 
       FIG. 4  is a circuit diagram of a sense amplifier circuit in accordance with an embodiment of the present invention; 
       FIG. 5  is a timing diagram of a sense amplifier control signal of  FIG. 4 ; 
       FIG. 6  is a timing diagram illustrating a control operation of a plurality of sense amplifiers in a self-refresh mode in accordance with the embodiment of the present invention; and 
       FIG. 7  is a circuit diagram of a control signal generator in accordance with the embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, which is set forth hereinafter. 
     FIG. 4  is a circuit diagram of a sense amplifier circuit in accordance with the present invention. 
   Referring to  FIG. 4 , a sense amplifier of the present invention includes a main bitline equalizer  410  and sub bitline equalizers  420  and  430 . 
   The main bitline equalizer  410  is controlled by a main line equalizing signal BLEQ_m enabled in a power down mode or a self-refresh mode, as similar to the prior art, so as to precharge a bitline pair BL and BLB connected to the sense amplifier, to a Vcore/2 voltage. 
   The sub bitline equalizers  420  and  430  are controlled by sub bitline equalizing signals BLEQ_up and BLEQ_down which are disabled in the power down mode so as not to apply the Vcore/2 voltage to the bitline pair BL and BLB. Meanwhile, in order to prevent data loss caused by the leakage current in the self-refresh mode, an active operation and a precharge operation are periodically performed for each cell in a block. Therefore, this is similarly applied to a sub bitline equalizer in the other blocks except the selected block for refresh in the self-refresh mode. 
   A first and a second bitline isolation units  470  and  480  are controlled in coincidence with the sub bitline equalizers  420  and  430  respectively, and electrically isolate the main bitline equalizer  410  from an upper and a lower cells cell_up and cell 13  down. This is similarly applied to a first and a second bitline isolation unit in the other blocks except the selected block for refresh in the self-refresh mode. 
   However, the bitline pair BL and BLB should not only be in a floating state but also keep the Vcore/2 voltage, in order that the cell data may be normally amplified at the sense amplifier when the wordline is enabled. 
   Therefore, it is preferable that whole the bitline pairs BL and BLB in the semiconductor memory device should be precharged to the Vcore/2 voltage by turning on the sub bitline equalizers  420  and  430  and the first and the second bitline isolation units  470  and  480  in case of exiting from a precharge power down mode. 
   Furthermore, in accordance with the embodiment of the present invention, the bitline pair BL and BLB is precharged for every unit block in the self-refresh mode. That is, the bitline equalizer that the refresh operation is not performed is turned off, whereas the bitline equalizer that the refresh operation is performed is turned on. 
     FIG. 5  is a timing diagram of a sense amplifier control signal of  FIG. 4 . 
   The power down mode shown in  FIG. 5  is a case of entering the power down mode from the precharge mode and the case of exiting from the power down mode. 
   (1) i Period 
   When the clock enable signal CKE is transited to a logic low level from a high level to enter the precharge power down mode, the first and the second bitline isolation signals BISH and BISL are transited to logic low levels from high levels to be disabled. As a result, an upper bitline pair BL 13  up and BLB_up and a lower bitline pair BL_down and BLB_down are isolated from the sense amplifier. The sub bitline equalizing signals BLEQ_up and BLEQ_down are transited to logic low levels from high levels to be disabled, which results in turning off the sub bitline equalizers  420  and  430  so that it is possible to prevent the leakage current flowing between the bitline pair and the wordline pair. 
   At this time, the main bitline equalizing signal BLEQ 13  m still keeps in logic high level as similar as the normal precharge mode, to maintain the bitline pair connected to the sense amplifier to have the Vcore/2 voltage. 
   (2) ii Period 
   In case of exiting from the precharge power down mode, the semiconductor memory device can be precharged by controlling the clock enable signal CKE without a precharge command. 
   (3) iii Period 
   The first bitline isolation signal BISH keeps in logic high level to turn on the first bitline isolation unit  470 , and the second bitline isolation signal BISL is transited to a logic low level to turn off the second bitline isolation unit  480 , to thereby readout the data of the upper cell cell_up. 
   (4) iv Period 
   The main and the sub bitline equalizers  410 ,  420  and  430  are wholly enabled in the precharge operation to precharge the bitline pair BL and BLB to the Vcore/2 rapidly. 
   (5) v Period 
   The first bitline isolation signal BISH is transited to a logic low level to turn off the first bitline isolation unit  470 , and the second bitline isolation signal BISL keeps in logic high level to turn on the second bitline isolation unit  480 , to thereby readout the data of the lower cell cell_down. 
     FIG. 6  is a timing diagram illustrating a control operation of a plurality of sense amplifiers in a self-refresh mode in accordance with the embodiment of the present invention. 
   Referring to  FIG. 6 , the sub bitline equalizing signals BLEQ_up and BLEQ_down and the first and the second bitline isolation signals BISH and BISL, which do not perform the refresh operation, are disabled. On the contrary, the sub bitline equalizing signals BLEQ_up and BLEQ_down and the first and the second bitline isolation signals BISH and BISL, which perform the refresh operation, are enabled. 
   In accordance with another embodiment of the present invention, after the wordline enabling operation is completed to a last wordline in the block where the refresh operation is performed, the refresh operation for a next block begins to be performed. In particular, in case that the refresh operation for the next block is followed by the refresh operation for a previous block, the sense amplifier and the bitline pairs in all the banks are precharged by using a block selection address signal, which is denoted as a ‘D’ region in  FIG. 6 . 
     FIG. 7  is a circuit diagram of a control signal generator in accordance with the embodiment of the present invention. 
   Referring to  FIG. 7 , the control signal generator in accordance with the embodiment of the present invention, which is located in the control circuit of  FIG. 1 , may generate a control signal IND required at the ‘D’ region of  FIG. 6 . 
   The control signal generator is provided with a multiplexer  500  for generating an output signal after a last wordline of a predetermined block is selected by receiving the block selection address signal and a wordline selection address signal, a first AND gate  510  for performing a logic AND operation to a self-refresh mode signal SREF and the output of the multiplexer  500 , an OR gate  520  for performing a logic OR operation to a clock enable signal CKE and an output of the first AND gate, and a second AND gate  530  for performing a logic AND operation to the sub bit equalizing signal and an output of the OR gate  520 . 
   Herein, detail descriptions for each signal will be set forth as followings. An in signal of  FIG. 7  may be the sub bitline equalizing signals BLEQ_up and BLEQ_down or the first and the second bitline isolation signals BISH and BISL generated in accordance with the embodiment of the present invention. The clock enable signal CKE is for embodying the precharge power down mode operation and an exit operation for the self-refresh mode. The self-refresh mode signal SREF is a signal having information with regard to the self-refresh mode. The multiplexer  500  generates the output signal after the last wordline of the predetermined block is selected by using the block selection address signal and the wordline selection address signal within a bank. That is, after the last wordline of the predetermined block is selected, all the blocks are precharged. 
   In accordance with the present invention, it is possible to minimize the leakage current flowing between the wordline and the bitline in a standby mode. 
   The present application contains subject matter related to Korean patent application No. 2005-24509, filed in the Korean Intellectual Property Office on Mar. 24, 2005, the entire contents of which is incorporated herein by reference. 
   While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.