Abstract:
A digital-analog converter electrically effecting sequential switching between a reference voltage point and each of the connection points formed in a circuit network composed of serially connected impedance elements for taking out desired analog quantity such as signal voltage level, impedance value or the like in response to the application of control pulses, which comprises in combination memory circuits such as R-S flip-flops, gate circuits such as NAND gates and delay circuit such as integration circuits, capacitors and the likes. The provision of the delay circuits, in particular, advantageously facilitates the setting for the initial operation state and the preparation for the sequential switching.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an apparatus for the digital control of an analog signal and, in particular, to a circuit arrangement for varying an analog quantity such as voltage, an impedance or the like. 
     Adjustments of the audio volume, color saturation, contrast, brightness and the like in various receivers such as a television receiver are sometimes performed by the use of a remote control apparatus instead of manually operating each of the adjustment knobs provided as part of a receiver. In such a remote control adjustment, a transmitter and a receiver are usually employed for the remote control. The transmitter may be operated by a viewer and the receiver is incorporated in the cabinet of a television receiver proper. The transmitter of the remote control apparatus is manipulated by the television viewer to send instruction signals, which are aerially transmitted as ultrasonic waves or as electric waves or the transmission directly may be through wire means to the television receiver. Corresponding to the types of the instruction signals, the receiver of the remote control apparatus generates pulse-shaped control signals and applies these control signals to the circuits to be controlled such as a volume control circuit, a color saturation control circuit and the like. Since the above described circuits to be controlled are adapted to operate in such a manner that they vary their analog output such as a voltage, an impedance or the like in accordance with the number of pulses in the control signals, a digital control is conventionally used for controlling such circuits. The digital control devices of this type employed so far, are adapted to count and store the a number of pulses by means of an up-down counter, and to effect a switching among the electronic switches provided in a resistor circuit network in response to the counted output to thereby provide voltages from said resistor circuit network corresponding to said counted pulses. The digital control devices of the type described are, however, expensive and hence not suited for use in apparatus used in the home such as television receivers. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a simplified circuit for varying an analog quantity such as the voltage level of an AC current signal, a DC voltage level, an impedance value or the like. 
     Another object of this invention is to provide a circuit arrangement which is economical and suited for the mass production by the use of IC components. 
     A further object of this invention is to provide a circuit arrangement which is suitable for the remote control of the adjustment for the audio volume, the color saturation, the brightness or the like of a television receiver. 
     In this invention, for attaining the foregoing objects, a circuit network having a plurality of impedance elements, for instance, serially connected resistor elements, is connected to a further plurality of memory circuits, for example, composed of R-S flip-flops which correspond to each of the connection points between said impedance elements so as to apply a reference voltage or a ground potential to any one of said connection points. The memory circuits are adapted so that a &#34;set&#34; input signal is always applied to a set input terminal of the first memory circuit when a first control signal arrives and a reset input signal is always applied to the reset input terminal of the final memory circuit when a second control signal arrives. The set input terminals and the reset input terminals of other memory circuits are controlled by gate circuits. A voltage generated at one output terminal of a pair of output terminals of a memory circuit, is applied through a delay circuit to a gate circuit at the reset input of the succeeding memory circuit. A voltage generated at the other output terminal of said pair of output terminals is applied through a similar delay circuit to a gate circuit at the reset input of the preceeding memory circuit thereby providing input signals for each of the gates. The memory circuits of a plurality of stages are divided into two group. Each group is provided with optional stages including delay circuits for delaying the &#34;set&#34; input signals to the memory circuits of the group including the memory circuit of the first stage. Each group is further provided with delay circuits for delaying the &#34;reset&#34; inputs to the memory circuit of the group including the memory circuit of the final stage. These features establish the initial operation condition of the digital control circuit. 
    
    
     DESCRIPTION OF THE ACCOMPANYING DRAWINGS 
     FIG. 1 is a circuit diagram of a preferred embodiment of this invention; 
     FIG. 2 and FIG. 3 are truth tables for showing the operation conditions of the circuit in each of their stabilized stages; 
     FIG. 4 is a circuit diagram of another preferred embodiment of this invention; and 
     FIG. 5 and FIG. 6 are examples for the circuit connections of the impedance circuit network for use in the circuit shown in FIG. 1 or in FIG. 2. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to the circuit shown in FIG. 1, a terminal A 1  is an input terminal to which an audio signal voltage is applied for example. Resistors R 1  through R 5  are connected in series between the input terminal A 1  and ground. To each of the connection points J 1  to J 4  formed between adjacent resistors connected in series, is connected the respective terminal of the output terminals Q 11 , Q 21 , Q 31  and Q 41  of the circuits enclosed by dashed lines denoted as F 1  to F 4 . Each of the circuits F 1  to F 4  has a similar construction and includes a well known R-S flip-flop. Referring to the construction of the flip-flops taking F 1  as a representative, the circuit comprises NAND gates N 11  and N 12 . The output terminal Q 11  of the NAND gate N 11  is connected to one of the input terminals of the NAND gate N 12  and the output terminal Q 12  of said NAND gate N 12  is connected to one of the input terminals of the NAND gate N 11 . The input terminal S 1  of the NAND gate N 11  forms a set terminal of the flip-flop F 1 . The input terminal r 1  of the NAND gate N 12  forms a reset terminal. When the set input terminal S 1  has a low voltage level, a stabilized state, that is, a set state is established wherein the output terminal Q 11  provides a high voltage level and the output terminal Q 12  provides a low voltage level. When the reset terminal r 1  is set at a low voltage level, a reset state is attained wherein the output terminals Q 11  and Q 12  respectively provide a voltage opposite to the foregoing state. 
     The set terminal S 1  of the flip-flop F 1  is connected with an output terminal of a gate circuit G 11  and the reset terminal r 1  is connected with an output terminal of a gate circuit G 12 . The gate circuit G 11  is connected of a NAND gate and has a gate input terminal g 11  and a set input terminal s 11 . Each of the gate circuits G 21 , G 22 , G 31 , G 32 , G 41  and G 42  has a similar construction. A circuit T 11  including a resistor R 11  and a capacitor C 11   connected in series, is connected between the output terminal Q 11  of the flip-flop F 1  and ground. The connection point between the resistor R 11  and the capacitor C 11  is connected to the gate terminal g 21  of the gate circuit G 21 . The circuit T 11  is an integration circuit and constitutes a delay circuit which delays the output signals of the output terminal Q 11  and applies the delayed output signals to the terminal g 21  as an input signal. The circuits having the same function as that of the delay circuit T 11  are shown as blocks T 21 , T 31 , T 22 , T 32  and T 42 . The delay circuit T 21  is connected between the output terminal Q 21  of the flip-flop F 2  and the input terminal g 31  of the gate circuit G 31 . The delay circuit T 31  is connected between the output terminal Q 31  of the flip-flop F 3  and terminal g 41  of the gate circuit G 41 . The delay circuit T 22  is connected between the output terminal Q 22  of the flip-flop F 2  and the terminal g 12  of the gate circuit G 12 . The delay circuits T 32  and T 42  are connected respectively in a similar manner between the output terminals Q 32  and Q 42  of the flip-flops F 3  and F 4  and the terminals g 22  and g 32  of the gate circuits G 22  and G 32  respectively, as illustrated in the drawing. The input terminals g 11 , s 11 , s 21 , s 31  and s 41  of the gate circuits G 11 , G 21 , G 31  and G 41  are connected to a common terminal U 1 . The input terminals s 12 , s 22 , s 32 , s 42  and g 42  of the gate circuits G 12 , G 22 , G 32  and G 42  are connected to the other common terminal D 1 . A capacitor C 1  for delaying a high level input voltage when the same is applied, is connected between the set input terminal s 1  of the flip-flop F 1  and ground. Capacitors C 2 , C 3  and C 4  which may have the same capacitance value, are respectively connected between the reset terminals r 2 , r 3  and r 4  of the other flip-flop circuits and ground. 
     The terminal U 1  is an input terminal to which a control signal P 1  is applied and the terminal D 1  is an input terminal to which another control signal P 2  is applied. The control signals P 1  and P 2  are respectively composed of voltage pulses and are added solely or sequentially as desired. As can be seen from the description of the operation to be made later, the voltage level of the audio signal at the output terminal A 2 , is increased by the application of the pulse P 1  and lowered by the application of the pulse P 2 . The time constants of the capacitors C 1 , C 2 , C 3  and C 4  should be within such a range that the pulse voltage generated by the application of the pulse P 1  or P 2  to the output terminals of the gate circuits G 11 , G 22 , G 32  and G 42 , can be used as set or reset input signals for flip-flop circuits with no substantial decays. Each of the time constants of the delay circuits T 11  · T 21  · T 31  · T 22  · T 32  and T 42  should be selected sufficiently greater than the pulse time width t 1  and sufficiently shorter than the pulse repeating interval t 2 . 
     The operation of the circuit will now be described with reference to FIG. 1. The circuit operation can be understood by considering each of its typical states, that is, an initial state when a voltage from a power source is first supplied and the stabilized conditions are attained, a state after the arrival of the control signal P 1  at the terminal U 1  and the succeeding state when the control signal P 2  arrives at the terminal D 1 . Since the voltages appearing at each of the terminals are either at a high level or a low level, they are referred to herein as &#34;H&#34; and &#34;L&#34; for the sake of simplicity. 
     (1) Initial state when only the power source voltage is applied 
     All of the gate inputs and the set inputs for each of the gate circuits are set at the &#34;L&#34; state and all of the outputs are at the &#34;H&#34; state. However, since a capacitor C 1  is connected between the output terminal of the gate circuit G 11  and ground, the voltage at the set input terminal s 1  of the flip-flop F 1  does not instantly reach the &#34;H&#34; state but remains at &#34;L&#34; until the capacitor C 1  is fully charged. On the other hand, the voltage at the reset input terminal r 1  immediately assumes the &#34;H&#34; state. Thus, the flip-flop F 1  establishes a set state wherein the output terminal Q 11  is at the &#34;H&#34; state. 
     In the flip-flop F 2 , the reset terminal r 2  is also set at the &#34;L&#34; state by the delay function of the capacitor C 2 . The output terminal Q 22  thus takes &#34;H&#34; and the other output terminal Q 21  takes &#34;L&#34; to thereby establish a reset state. In the similar manner as described above, the flip-flop circuits F 3  and F 4  also establish the reset state as the flip-flop circuit F 2 . Thus, connection points J 1  becomes &#34;H&#34; and the other connection points J 2 , J 3  and J 4  are at ground potential by way of the flip-flop circuits F 2 , F 3  and F 4 . Therefore, the audio signals applied through an input terminal A 1  is divided and taken off from an output terminal A 2  at a level divided by the ratio between the resistance values of the resistor R 1  and the resistor R 2 . The voltage developed at the output terminal Q 11  is delayed in the delay circuit T.sub. 11 and then applied to the gate terminal g 21  of the gate circuit G 21  to set a &#34;H&#34; voltage on said terminal g 21 . Since other flip-flop circuits assume the reset state and the output terminals Q 22 , Q 32  and Q 42  thereof assume an &#34;H&#34; state. The gate terminals g 12 , g 22  and g 32  also assume an &#34;H&#34; voltage or state after a delay in the delay circuits T 22 , T 32  and T 42 . 
     (2) A state when a first pulse P 1  is applied to the terminal U 1   
     In the gate G 11 , both of the gate terminal g 11  and the set terminal s 11  are set at an &#34;H&#34; state to thereby develop a &#34;L&#34; voltage at the output thereof, which renders the voltage at the set input terminal of the flip-flop F 1  to &#34;L&#34;. In the gate circuit G 12 , the output terminal assumes &#34;H&#34; since the gate terminal g 12  is set to &#34;H&#34; as described above and the set terminal s 12  remains at &#34;L&#34;. Therefore, the flip-flop F 1  establishes its set state, that is, the same state as set forth in item (1) above where the set terminal s 1  has a &#34;L&#34; voltage and the reset input terminal r 1  has a &#34;H&#34; voltage. In the gate circuit G 21 , the gate terminal g 21  is kept at &#34;H&#34; and a pulse capable of setting the set terminal s 21  to &#34;H&#34; arrives at said terminal thereby rendering the output thereof &#34;L&#34;. Since the reset terminal r 2  remains &#34;H&#34;, the flip-flop F 2  establishes the set state when the set input is rendered &#34;L&#34; as described above, wherein the output terminal Q 21  takes &#34;H&#34; and the output terminal Q 22  takes &#34;L&#34;. In the gate circuit G 31 , since the gate terminal g 31  is set to &#34;L&#34;, the output thereof remains &#34;H&#34; even when a pulse is applied to cause the set terminal s 31  to assume an &#34;H&#34; state. The gate circuit G 32  keeps its output at &#34;H&#34; since no pulses arrive at the set terminal s 32  and the gate terminal g 32  remains &#34;H&#34;. As the flip-flop F 3  has been kept at its reset state since the application of the power source voltage, there is no change in the operational states. Because the output terminal Q 21  of the flip-flop F 2  at the preceeding stage now changes to &#34;H&#34;, a &#34;H&#34; voltage is going to be applied to the gate g 31 . However, since the delay circuit T 21  is interposed, the gate terminal g 31  is set &#34;H&#34; not immediately but after the pulse P 1  applied to said terminal s 31 , has ended. As the result, the output of the gate circuit G 31  remains &#34;H&#34; to thereby keep the flip-flop F 3  from establishing the set state. Finally, in the gate circuit G 41 , the gate terminal g 41  remains &#34;L&#34; and the set terminal s 41  becomes &#34;H&#34; at the arrival of the pulse to thereby cause the output to assume an &#34;H&#34; state. Thus, the flip-flop F 4  also remains at its reset state. As the result of the above successive operations, the connection points J 1  and J 2  take &#34;H&#34; and the connection points J 3  and J 4  take &#34;L&#34;. The audio signal applied through the terminal A 1  is taken off from the terminal A 2  divided by the ratio between the resistance value of R 1  and that of the resistors R 2  and R 3 . Therefore, the signal level at the terminal A 2  becomes higher than that obtained in the state described in item (1) above. 
     (3) A state when the second pulse is applied to the terminal U 1   
     The circuit operations are similar as those described in item (1) above, and the flip-flops F 1 , F 2  and F 3  are set while only the flip-flop F 4  remains reset. Therefore, only the terminal J 4  is grounded and the voltage level of the signal applied to the input terminal A 1  is divided by the ratio between the resistance value of R 1  and that of the sum of the resistors R 2 , R 3  and R 4 . 
     (4) A state when the third pulse is applied to the terminal U 1   
     The flip-flop F 4  turns into the set state and thus all of the flip-flops are now brought into the set state. Therefore, the signal applied through the input terminal A 1 , is divided by the ratio between the resistance value of R 1  and that of R 2 , R 3 , R 4  and R 5 . Thereafter, the above set state is kept even when further pulses are applied to the terminal U 1 . 
     (5) A state when a first pulse P 2  is applied to the terminal D 1   
     When a pulse P 2  arrives at the terminal D 1  under the state wherein all of the flip-flops are kept set, both of the set input terminal s 42  and the gate terminal g 42  in the gate circuit G 42  are set to &#34;H&#34; to develop an output signal at the &#34;L&#34; level at its output terminal. The gate circuit G 41 , develops a &#34;H&#34; output since the set input terminal s 41  is again &#34;L&#34; although the gate terminal g 41  remains &#34;H&#34;. Therefore, the flip-flop F 4  turns into the reset state. The outputs of the gate circuits G 32 , G 22  and G 12  remain &#34;H&#34; in spite of the application of the pulse because each of the gate terminals g 32 , g 22  and g 12  remains at the &#34;L&#34; level. Thus, the flip-flops F 1 , F 2  and F 3  maintain their set state and, as the result, only the connection point J 4  is grounded. After the pulse P 2  has ended, the voltage at the &#34;H&#34;  level developed at the terminal Q 3  is applied via the delay circuit T 42  to the gate terminal g 32  of the gate circuit G 32  to attain the same condition as described in item (3) above. 
     (6) A state when the second pulse P 2  is applied to the terminal D 1   
     The set terminal S 32  and the gate terminal g 32  of the gate circuit G 32  are set &#34;H&#34; to turn the output thereof to &#34;L&#34;. Therefore, the flip-flop F 3  turns into the reset state. Since other flip-flops, F 1 , F 2  and F 4  remain with their states unchanged, the connection points J 3  and J 4  are now grounded. After the end of the pulse P 2 , the gate terminal g 41  of the gate circuit G 41  assumes the &#34;L&#34; state and the gate terminal g 22  of the gate circuit G 22  becomes &#34;H&#34;, which is the same state as described in item (2) above. 
     (7) A state when the third pulse P 2  is applied to the terminal D 1   
     The output of the gate circuit G 22  is set to &#34;L&#34; to turn the flip-flop F 2  to the reset state. The other flip-flops F 1 , F 3  and F 4  are kept in the preceeding states. Therefore, the connection point J 2  is grounded. After the end of the pulse, the gate terminal g 31  is set to &#34;L&#34; and the gate terminal g 12  is set to &#34;H&#34;, which is the same as the initial state described in item (1) attained after the application of the power supply voltage. 
     (8) A state when the fourth pulse P 2  is applied to the terminal D 1   
     Since the gate terminal g 12  remains &#34;H&#34; and the set terminal s 12  is now set to &#34;H&#34;, the gate circuit G 12  provides an output signal of the &#34;L&#34; level to thereby turn the flip-flop F 1  into the reset state. Accordingly, the terminal Q 11  becomes &#34;L&#34; and the connection point J 1  is grounded. Thus, the audio signal applied at the terminal A 1  is grounded and does not appear at the terminal A 2 . This state is continued, thereafter, even when further pulses P 2  are applied to the terminal D 1 . 
     The circuit operation has been described with reference to respective states set forth in each of the items (1) through (8). The output states of the flip-flops as described in each of the items are shown as a truth table in FIG. 2 and the states of the voltages set at each of the gate terminals and set terminals in the gate circuits where the operation of each of the flip-flops is stabilized, are illustrated in FIG. 3. It will easily be understood referring to FIG. 2 and FIG. 3, how the circuit shown in FIG. 1 changes its state from a certain established condition to another by way of the successive arrival of the pulses P 1  or P 2 . 
     In the circuit illustrated in FIG. 1, a capacitor C 1  is connected between the set input terminal s 1  and ground, and the capacitors C 2 , C 3  and C 4  are connected between each of the reset input terminals r 2 , r 3  and r 4  of other flip-flops F 2 , F 3  and F 4  and ground respectively. The capacitor C 1  thus connected, establishes an initial state wherein the flip-flop F 1  is preferably brought into the set state when the power source voltage is applied. In a modified circuit, the capacitor C 2  may be connected between the set input terminal s 2  and ground in a similar manner as the capacitor C 1  thereby preferably bringing both of the flip-flops F 1  and F 2  into the set state after the application of the power source voltage. In such a modified circuit, in other words, the audio signal applied to the terminal A 1  is at first taken off from the terminal A 2  as a level divided by the ratio between the resistance value of R 1  and that of the resistors R 2  and R 3 . The audio signal to be taken off after the application of the power source voltage can thus be set at an intermediate level. This circuit is very convenient for a viewer because when applying the same to a volume control circuit in a television receiver, the volume can be controlled at the intermediate level when the power switch is turned to &#34;on&#34;. 
     The circuit shown in FIG. 1 may be altered as shown in FIG. 4. The circuit will be described only with respect to the differences in comparison to the embodiment of FIG. 1. The audio signal is applied to a terminal A 11  and taken off from a terminal A 12 . Since a further resistor R 55  is connected in the series, the signal level taken off from the output terminal A 12  is always kept at a certain level without decreasing to zero even when all of the connection points J 11  through J 14  are grounded. Transistors Tr 1 , Tr 2 , Tr 3  and Tr 4  are respectively connected between each of the output terminals Q 11 , Q 21 , Q 31  and Q 41  of the flip-flops and the connection points J 11 , J 12 , J 13  and J 14  corresponding thereto. These transistors operate as switching devices with each of their base electrodes being controlled by the output voltage of the flip-flops. The set input terminal s 1  of the flip-flop F 1  is directly connected to a common terminal D 1 . No gate means are interposed therebetween and the reset terminal r 4  of the flip-flop F 4  is directly connected to the common terminal U 1  also with no gate means interposed therebetween. A gate circuit G 12  has a transistor Tr 12  the base of which is used as a gate terminal s 12 , the emitter of which is used as a set terminal s 12  and the collector of which is used as an output terminal and supplied with a voltage B +  via a resistor R 72 . The other gate circuits G 21 , G 22 , G 31 , G 32 , and G 41  have the same construction as the gate circuit G 12 . The control signals P 11  and P 12  to be applied to input the terminals U 1  and D 1  are the respective pulses which have opposite polarities to those of the pulses P 1  and P 2  shown in FIG. 1. In the circuit shown in FIG. 4, capacitors C 1  and C 2  are respectively connected between the set input terminals s 1  and s 2 , and the ground, and capacitors C 3  and C 4  are respectively connected between the reset input terminals r 3  and r 4  and ground. In the initial state where only the power source voltage is applied, the flip-flops F 1  and F 2  attain the set state and the flip-flops F 3  and F 4  attain the reset state, whereby the transistors Tr 1  and Tr 2  have a &#34;H&#34; base voltage and become saturated to conduct. On the other hand, the transistors Tr 3  and Tr 4  remain non-conductive. This means that the connection points J 11  and J 12  are grounded. Therefore, the audio signal applied through the terminal A 11  is taken off from the terminal A 12  divided by the ratio between the resistance value of the resistors R 53 , R 54 , R 55  and R 56  at a predetermined intermediate level in the range to be controlled. After the power source voltage is applied, each of the controlling operations of the circuit is started from the above described initial state. 
     Although the operation of the circuits shown in FIG. 1 and FIG. 4, has been described with reference to the audio signal as an example of the signal to be controlled, the signal may be any other AC current signal or may be a DC voltage. Also, reference has been made to for providing the resistors connected in series the connection points in the series with ground level or with certain reference voltage levels it will be appreciated that impedance elements having a capacitance and/or an inductance may be used instead of the resistors. 
     FIG. 5 shows a part of a circuit diagram in which impedance elements connected in series shown as blocks 1 to 4 are used instead of the resistors connected in series. The terminal A 1  in this embodiment is connected to a circuit which requires an impedance control. 
     FIG. 6 shows a part of a circuit diagram of another embodiment wherein a ladder type circuit network comprising impedance elements 11 to 19, is applied to the circuit shown in FIG. 1. 
     Although this invention has thus been described referring to the preferred embodiments thereof, it will be understood that it is intended to cover all modifications and equivalents within the scope of the appended claims.