Abstract:
A multi-tone display matrix display device including a matrix display panel having a matrix having plural X and Y direction signal lines lying at right angles to each other, intersecting points on the matrix being pixels of an image, an X direction driving section for sequentially scanning X direction signal lines to provide image signals, a Y direction driving section for driving the Y direction signal lines in synchronism with the scanning of the X direction signal lines to sequentially provide select signals to the Y direction signal lines, an A-D converter section for converting an analog signal into a digital signal, a voltage generating section for generating signals at plural voltage levels, and a selector section for selecting an output signal from the voltage generating section based on the output from A-D converter section and providing to output to the X direction driving section as an image signal.

Description:
[0001]     The present application is a divisional application of application Ser. No. 11/087,498, filed Mar. 24, 2005; which is a continuation of application Ser. No. 09/625,542, filed Jul. 25, 2000; which is a continuation of application Ser. No. 09/188,901, filed Nov. 10, 1998, now U.S. Pat. No. 6,191,765; which is a continuation of application Ser. No. 08/466,188, filed Jun. 6, 1995, now U.S. Pat. No. 6,191,767; which is a continuation of application Ser. No. 08/164,563, filed Dec. 10, 1993, now abandoned; which is a continuation of application Ser. No. 07/844,965, filed Feb. 28, 1992, now U.S. Pat. No. 5,298,912; which is a continuation-in-part of application Ser. No. 07/475,849, filed Feb. 6, 1990, now abandoned. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a matrix display device, and more particularly to a device for displaying an image in plural tones in response to an analog image signal.  
         [0003]     In recent years, matrix display devices including a liquid crystal display, a plasma display, an EL (electroluminescence), etc. have been developed as display devices in place of CRT display devices.  
         [0004]     The display screen of the matrix display device has plural X signal lines arranged in a horizontal (X) direction of the screen, and plural Y signal lines in a vertical (Y) direction thereof; each of picture cells (pixels) is displayed at each of intersecting points of the X and Y signal lines. The X signal lines are supplied with image signals (luminance or color signals), whereas the Y signal lines are supplied with selective signals for scanning lines.  
         [0005]     Several techniques of the display for the matrix display device, which can make the display with multi color and multi-tone as in the CRT display device, have been developed. For example, in the liquid crystal matrix display device, different tones can be exhibited in terms of different integration values of transmission light beams for liquid crystal cells. The different integration values of transmission light beams can be exhibited by thinning out image signals for each frame of the image display, or pulse-width modulating the image signals supplied to the X signals. In these techniques, the difference in time-integration values of image signals are converted into different tones. On the other hand, if the liquid crystal devices which continuously vary in their transmissivity in accordance with varying applied voltages is used, it is possible to exhibit the tone by controlling the applied voltage.  
         [0006]     JP-A-62-195628 filed on Jan. 13, 1986 by HITACHI, LTD. in Japan discloses a liquid crystal display device which provides monochrome or 8 (eight) color display in accordance with input signals which are binary digital signals. JP-A-61-75322 filed on Sep. 20, 1984 by FUJITSU GENERAL Co. Ltd., discloses a system which provides tone display by changing signal levels between adjacent fields. JP-A-59-78395 filed Oct. 27, 1982 by SUWA SEIKOSHA Co. Ltd., discloses a multi-tone display system using pulse-width modulation.  
         [0007]     Now referring to  FIGS. 1 and 2 , the operation of a liquid crystal matrix display device which does not have the function of tone display will be explained. An input signal for this matrix display device is a binary digital signal represented by the value of “0” or “1”.  
         [0008]     In  FIG. 1, 1  is a liquid crystal display device (or liquid crystal display module, hereinafter referred to as LCM) provided with a matrix shape liquid crystal panel  17  the pixels of which are selected by X signal lines and Y signal lines.  18  is display data in which display ON (white) is represented by “1” and display OFF (black) is represented by “0”.  3  is a latch clock in synchronism with the display data  18 .  4  is a horizontal clock indicative of the period during which the amount of display data corresponding to one horizontal display is sent.  5  is a head line signal.  19  is a voltage generating section.  20  is a display ON voltage.  21  is a display OFF voltage.  13  is a selected voltage.  14  is a non-selected voltage. These voltages are generated by the voltage generating section.  22  is an X driving section for driving X-signal lines which is reset by the trailing edge of the horizontal clock, takes in the display data  18  corresponding to one horizontal display, converts the display data taken into a display ON voltage for the data “1” and into a display OFF voltage for the data “0”, and finally outputs the converted voltage in accordance with the next trailing edge of the horizontal clock  4 . X 1 -X 640  are panel data which are output voltages from the X driving section.  16  is a Y driving section for driving  20  Y signal lines. Y 1 -Y 200  are scanning signals. The Y driving section  16  takes; in the head line signal in accordance with the trailing edge of the horizontal clock  4 , initially takes the scanning signal Y 1  as the selected voltage  13 , and shifts the selected voltage  13  in the order of scanning signals Y 2 , Y 3 , . . . Y 200  (each of the scanning signals other than the scanning signal which is a selected voltage  13  is a non-selected voltage  14 ). The liquid crystal panel  17  displays data on the line corresponding to the scanning signal Y 1  which is at the level of the selected voltage in accordance with the panel data X 1 -X 640  which are X-signal-line driving voltages X 1 -X 640  generated from the X driving section  22 .  
         [0009]      FIG. 2  is a timing chart for explaining the operation of the LCM- 1 .  
         [0010]     In  FIG. 1 , the X driving section  22  successively takes in the display data for each one line in synchronism with the latch clock  3  and in accordance with the subsequent horizontal clock  4 , outputs as panel data X 1 -X 640 , the display ON voltage  20  or the display OFF voltage selected by “1” or “0” of each data. As shown in  FIG. 2 , therefore, the X driving section  22  outputs the voltage selected by the data for a 200-th line which is a last line while taking in a first line data, and outputs the voltage selected by the first line data while taking in a second line data. Namely, the output of display data lags by one line from the take-in thereof. Then, in order that the scanning signal on the line to be output by the X driving section  22  is the selected voltage, the Y driving section  16  takes in the head line signal  5  at the timing of the horizontal clock  4 , takes the scanning signal Y 1  as the selected voltage  13  and thereafter shifts the selected voltage  13  in accordance with the horizontal clock  4 . In accordance with the voltage of each of the panel data X 1 -X 640 , the display panel  17  displays “white”, on the line corresponding to the scanning line which is the selected voltage, when it is the display ON voltage and displays “black” when it is the display OFF data.  
         [0011]     Color display (8 color display) can be made by arranging color filters of red, green and blue in the direction of lines (Y direction) or the direction of dots (X direction), and additively mixing three dots (3 bit data) constituting one dot (pixel) of visible information through display ON or OFF thereof.  
         [0012]     Meanwhile, development of multi-color and multi-tone display in accordance with the demand for multi-color display and multi-tone display gave rise to a problem of interface between information processing devices such as between a liquid crystal panel and a personal computer. More specifically, if 4096 colors are to be displayed, signal lines corresponding to 4 bits are required for each of R (red), G (green) and B (blue) so that a. total of 12 signal lines are required. Further, if 32768 colors are to be displayed, signal lines corresponding to 5 bits (total of 15 signal lines) are required for each of R, G and B. Increase in the number of signal lines will complicate the interface between e.g., the display panel and the personal computer and give rise to unnecessary radiation. This can be prevented by using analog input signal lines.  
       SUMMARY OF THE INVENTION  
       [0013]     An object of the present invention is to provide a new matrix display device in a multi-tone display system which is different from the conventional matrix display systems.  
         [0014]     In the display device according to an embodiment of the present invention, an analog signal is used as an input signal. The analog signal is A-D converted into a digital signal. A voltage generating device is provided to generate plural voltages in accordance with tones to be displayed. An output voltage from the voltage generating device is selected in accordance with the value represented by the digital signal. The selected voltage is applied to a display element to display a desired tone.  
         [0015]     A matrix display device according to an embodiment of the present invention comprises a matrix display panel having a matrix composed of plural X direction signal lines and plural Y direction signal lines lying at right angles thereto, intersecting points on the matrix being pixels of an image to be displayed, an X direction driving section for sequentially scanning the X direction signal lines to provide image signals, a Y direction driving section for the Y direction signal lines in synchronism with the scanning of the X direction signal lines to sequentially provide select signals to the Y direction signal lines, an A-D converter section for receiving an analog signal and converting it into a digital signal, a voltage generating section for generating signals at plural voltage levels, and a selector section for selecting an output signal from the voltage generating section in accordance with the output from A-D converter section and providing it to the X direction driving section as an image signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]      FIG. 1  is a block diagram of a liquid crystal matrix display device for displaying an image in response to a digital signal input;  
         [0017]      FIG. 2  is a waveform chart for explaining the operation of the display device of  FIG. 1 ;  
         [0018]      FIG. 3  is a block diagram of a liquid crystal matrix display device according to a first embodiment of the present invention;  
         [0019]      FIG. 4  is a block diagram of an example of the X driving section of  FIG. 3 ;  
         [0020]      FIG. 5  is a block diagram of an embodiment of a liquid crystal matrix display device (LCM) for color display according to the present invention;  
         [0021]      FIG. 6  is a block diagram of the main part of LCM according to the second embodiment of the present invention;  
         [0022]      FIG. 7  is a timing chart for explaining the operation of the serial-parallel converter means of  FIG. 6 ;  
         [0023]      FIG. 8  is a block diagram of an input part of the parallel X driving section of  FIG. 6 ; and  
         [0024]      FIG. 9  is a block diagram of the main part of another embodiment of a liquid crystal matrix display device for color display according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0025]     Now referring to  FIGS. 3 and 4 , an embodiment of a multi-tone display LCM is illustrated according to the present invention. In this embodiment, it should be noted that an analog display data or signal (stepwise analog signal)  2  having different voltage levels corresponding to the number N of tones to be displayed is input to the display device. For simplicity of explanation, it is assumed that N=4, the analog input signal is represented by the voltage levels corresponding to 4 (four) tones. The analog signal is sent from an image display output of e.g., a personal computer. In  FIG. 3, 6  is an A-D converter section;  7  is a digital display data. The A-D converter section  6  converts the analog display data  2  as an input into the digital display data which is represented by 2 bits; more specifically, four value voltage levels of the analog display data are converted into (0,0), (0,1), (1,0), and (1, 1) from the lower levels.  8  is a multi-voltage-level output generating circuit for generating constant voltages at plural levels in accordance with tones to be displayed, e.g. voltages at four different levels since this embodiment is directed to 4 tone display. The signal at the voltage level corresponding to tone  0  is output to a signal line  9 . The signals at voltage levels corresponding to tone  1 , tone  2  and tone  3  are output to signal lines  10 ,  11 , and  12  respectively.  15  is an X driving section which takes in 2 bit digital data  7  sequentially one line at a time in synchronism with the latch clock  3 , selects one of the four tone voltages output to the signal lines  9 ,  10 ,  11  and  12  in accordance with the decoded value of data for each dot and outputs it as panel data X 1 -X 640 . The remaining reference numbers denote like parts in  FIG. 1 .  
         [0026]      FIG. 4  shows an example of the X driving section shown in  FIG. 3 . In  FIG. 4, 23  is a latch selector and S 1 -S 640  are select signals. The latch selector  23  is cleared by latch clock  3  and sequentially boosts the select signals S 1 , S 2 , . . . S 640  “high” in synchronism with the succeeding clocks  3 .  24  is a latch circuit which serves to latch the digital display data  7  in blocks (latch  1 -latch  640 ) in which the select signal is “high”.  25  to  28  are outputs from the respective blocks of the latch circuit  24 , i.e. 2 bit latch data  1  to  640 .  29  is a horizontal latch circuit which latches the latched data  1  to  640  in horizontal latches  1  to  640  in synchronism with the horizontal clock  4 .  30  to  33  are outputs from the respective blocks of the horizontal latch circuit  29 , i.e. 2 bit horizontal data  1  to  640 .  34  is a decoder which serves to decode the horizontal data  1  to  640  by the corresponding decoder blocks (decoders  1  to  640 ). Numerals  35  to  38  are outputs from the decoder blocks, i.e., decoded values  1  to  640 . Numeral  39  indicates a voltage selector which serves to select one of the tone voltages in accordance with the decoded values  1 - 640 .  
         [0027]     Now referring to  FIGS. 3 and 4 , the operation of the multi-tone display LCM  1  shown in  FIG. 3  will be explained. In  FIG. 3 , the analog display data  2  is converted into the 2 bit digital data  7  by the A-D converter section  6 ; the 2 bit digital display data  7  is input to the X driving section  15 . The X driving section  15  takes the display digital data  7 , in synchronism with the latch clock  3  ( FIG. 2 ) in one latch block of the latch circuit  24  to which a “high” select signal is being input. The latch selector  23  shifts the “high” state of the select signal each time the latch clock  3  is input. The latch circuit  24  takes in the sequentially sent digital display data  7  in the latch blocks  1 ,  2 , . . .  640 . When the latch circuit  24  has taken in the digital display data  7  corresponding to one line, i.e., up to latch block  640 , the horizontal clock ( FIG. 2 ) is applied to the X driving section  15  to clear the latch selector  23 ; then the X driving section stands by for next take-in of the digital display data  7 . The data latched by the latch circuit  24  is sent to the horizontal latch circuit  29  which latches the data from the latch circuit  24  in synchronism with the horizontal clock  4  ( FIG. 2 ). The horizontal data  30  to  33  which are outputs from the horizontal latch circuit  29  are sent to the decoder  34  and decoded by the decoder blocks  1  to  640  thereof; the decoded values  35  to  38  are output from the decoder  34 . In the voltage selector  39 , the selector blocks  1  to  640 , in accordance with the decoded values, selects tone  0  voltage  9  if the decoded value is “0”, tone  1  voltage  10  if it is “1”, tone  2  voltage  11  if it is “2”, and tone  3  voltage  12  if it is “3”. The tone voltages output from the voltage selector blocks are sent to the liquid crystal panel  17  as panel data X 1  to X 640 . Thus, the four value voltages output from the X driving section  15  are applied to the liquid crystal elements corresponding to the line selected by the Y driving section  16  in response to the select voltage  13  sent from the voltage generating circuit  8 . In this way, the LCM  1  shown in  FIG. 3  can realize four tone display.  
         [0028]     Although the four tone display has been adopted in this embodiment, 2 N  tone display can be realized. More specifically, if the input analog display data is represented by 2 N  (N is an integer of 1 or more) levels, it is converted into N bit digital data by the A-D converter section  6 , the data width in the internal circuits in the X driving circuit  15  is set at N bits, and 2 N  kinds of tone voltage are supplied to the X driving section  15  to display 2 N  tones.  
         [0029]     Now referring to  FIG. 5 , one embodiment of the LCM for multi-color display will be explained. The multi-color display can be realized by arranging color filters of R (red), G (green) and B (blue) in the direction of dots on the liquid crystal panel  17 , providing A-D converter sections  43 ,  44  and  45  for R 40 , G 41  and B 42  as input analog display data, and applying the outputs from the R, G and B A-D converter sections  43 ,  44  and  45  to a color X driving section  46 . In this case, the color X driving section  46  has three columns of the arrangement shown in  FIG. 4  and thus the corresponding panel data are RX 1 -RX 640 , GX 1 -GX 640  and BX 1 -BX 640 .  
         [0030]     With reference to FIGS.  6  to  8 , another embodiment of the multi-tone LCM will be explained. In this embodiment, it should be noted that a parallel input of M (M is a positive integer) dots are applied to the X driving section, and it is assumed that M=2.  
         [0031]     In  FIG. 6 , like reference numerals denote like elements in  FIG. 3 .  47  is a serial-parallel converter section.  48  is a first dot digital data, and  49  is a second dot digital data. The serial-parallel converter section  47  converts 2 bit serial digital data  7  from the A-D converter section  6  into a parallel data consisting of the first dot digital data  48  and the second dot digital data  49 , each data consisting of 2 bits.  50  is a timing correction section.  51  is a parallel clock.  52  is a correction horizontal clock.  53  is a correction head line signal. In response to the latch clock  3 , the timing correction section  50  generates a parallel clock  51  in synchronism with the parallel data consisting of the first dot digital data  48  and the second dot digital data  49 . Further, in order to correct the phase deviation of data due to the serial-parallel conversion of the display data, the timing correction section  50  corrects the horizontal clock  4  and the head line signal  5  using the latch clock  3  to provide a corrected horizontal clock  52  and a corrected head line signal  53 .  54  is a parallel X driving section which serves to sequentially take in the 2 bit parallel display data in synchronism with the parallel clock  51 .  
         [0032]      FIG. 7  is a timing chart showing the operation of the serial-parallel conversion section  47 .  FIG. 8  is a block diagram of the parallel X driving section  54 . In  FIG. 8, 55  is parallel latch select which is cleared by the corrected horizontal clock  52  and thereafter sequentially boosts select signals  81 ,  82 , . . .  8320  to “high”.  56  is a parallel latch circuit; the latch block thereof for which the select signal is “high” latches simultaneously the first dot digital data  48  and second dot digital data  49  at the timing of the parallel clock  51 . The other reference numerals in  FIG. 8  denote like elements in  FIG. 4 .  
         [0033]     The operation of the multi-tone LCM shown in  FIG. 6  will be explained. The analog display data  2  having four value voltage levels is the 2 bit digital display data  7  by the analog-digital converter section  6 . This digital display data  7  is converted into 2 bit parallel data, as shown in  FIG. 7 , to provide the first dot digital data  48  and second dot digital data  49  which are in synchronism with the parallel clock  51 . Then, as shown in  FIG. 7 , owing to the serial-parallel conversion, the phase of the output data lags the input data by 2 (two) latch clocks  3 . In order to correct this lag, the timing correction section  50  also causes the horizontal clock  4  and the head line signal  5  to lag by 2 latch clocks  3 . The resulting corrected horizontal clock  52  and corrected head timing signal  53  are applied to the X driving section  54  and the Y driving section  16 . As seen from  FIG. 8 , the X driving section  54  takes the first dot digital data  48  and the second dot digital data  49 , in synchronism with the parallel clock  51 , into its one block to which the “high” select signal is applied from the parallel latch select  55 . The parallel latch select  55  is cleared by the corrected horizontal clock  52  and thereafter sequentially boosts the select signals S 1  to S 320  to “high”. Thus, the parallel latch circuit  52  also latches the data in the order of latch blocks  1 ,  2 , . . .  320  to finally latch the data corresponding to one line. The outputs from the blocks of the parallel latch circuit  56  are latched in the horizontal latch circuit  52  at the timings of the corrected horizontal clock  52 . The following operation is the same as that in  FIG. 4 . Thus, parallel data X 1  to X 640  are provided as panel data.  
         [0034]     As understood from the above explanation, two dots can be used as an input to the X driving section  46  by providing the serial-parallel conversion section  47 , causing the internal port of the X driving section  46  to simultaneously latch two dots and providing the timing correction section for correcting the phase lag due to the serial-parallel conversion. This can enhance the operation speed of the circuits successive to the A-D converter section  6 .  
         [0035]     In another embodiment of the invention, the timing correction section  50  is not required when the input timing is determined in consideration of the phase delay in the serial-parallel conversion section  47  (two latch clocks  3 ) so that the horizontal clock  4  and the head line signals can be directly used without correction. Incidentally, although in this embodiment, the input to the X driving was 2 bits for each of 2 dots, the input of N bites) (N is an integer of 1 or more) for each of M dots (M is an integer of 2 or more) can be realized in the same way.  
         [0036]     A second embodiment of the LCM for color display as shown in  FIG. 9  can be realized by providing R, G and B serial-parallel converter sections  57 ,  58  and  59 , and providing a color parallel X driving section  60  with three columns of the arrangement of  FIG. 8 .  
         [0037]     Further, although the explanation hitherto made was directed to a liquid crystal display device, the same idea can be also applied to the other display devices such as a plasma display, EL display, etc.  
         [0038]     In accordance with the present invention, an LCM for multi-tone display or multi-color can be realized thereby to decrease the number of input lines to LCM. Moreover, by using an analog input to decrease the number of data bits, noise to be generated can be reduced. Further, by carrying the parallel operation of the X driving section, the operation speed can be enhanced. Furthermore, since the voltages in accordance with N bit decoded values can be selected as outputs from the X driving section, tone voltage with less fluctuation can be provided.  
                                   APPENDIX A                       ATTY. DKT. NO.   INVENTOR   SERIAL NO.   FILING DATE   RECORDATION DATE   REEL/FRAME                   500.31108CC6   A. TANAKA   10/610,759   2-Jul-03   24-Mar-93   6075/602       500.31108X00   A. TANAKA   07/859,850   30-Mar-92   24-Mar-93   6075/602       500.31108CC2   A. TANAKA   08/895,886   17-Jul-97   24-Mar-93   6075/602       500.31108CC3   A. TANAKA   08/895,986   17-Jul-97   24-Mar-93   6075/602       500.31108CC4   A. TANAKA   09/162,444   29-Sep-98   24-Mar-93   6075/602       500.31108CC5   A. TANAKA   09/712,171   15-Nov-00   24-Mar-93   6075/602       500.31108CX1   A. TANAKA   08/534,841   27-Sep-95   24-Mar-93   6075/602       500.28503CC5   H. MANO   09/625,542   25-Jul-00   6-Feb-90   5229/108       500.28503CC6   H. MANO   11/087,498   24-Mar-05   6-Feb-90   5229/108       500.28503CC4   H. MANO   09/188,901   10-Nov-98   6-Feb-90   5229/108       500.28503CX3   H. MANO   08/466,188   6-Jun-95   6-Feb-90   5229/108       500.28503CX1   H. MANO   07/844,965   28-Feb-92   6-Feb-90   5229/108       500.37074CX2   A. KANO   10/843,482   12-May-04   7-Apr-99   9924/0489       500.37074X00   A. KANO   09/287,376   7-Apr-99   7-Apr-99   9924/0489       500.37074CX1   A. KANO   10/096,455   13-Mar-02   7-Apr-99   9924/0489       500.32392X00   T. NISHIYAMA   08/117,326   7-Sep-93   7-Sep-93   6730/504       500.32392CX1   T. NISHIYAMA   08/375,409   18-Jan-95   7-Sep-93   6730/504       500.32392CC2   T. NISHIYAMA   08/956,787   23-Oct-97   7-Sep-93   6730/504       500.32392CC3   T. NISHIYAMA   09/285,050   2-Apr-99   7-Sep-93   6730/504       500.32392CC4   T. NISHIYAMA   09/579,473   26-May-00   7-Sep-93   6730/504       500.32392CC5   T. NISHIYAMA   09/984,610   30-Oct-01   7-Sep-93   6730/504       500.32392CC6   T. NISHIYAMA   10/441,064   May 20, 2003   7-Sep-93   6730/504       500.31164x00   S. KOIZUMI   07/872,773   23-Apr-92   23-Apr-92   6103/0237       500.31164VX1   S. KOIZUMI   08/487,899   7-Jun-95   23-Apr-92   6103/0237       500.31164CV2   S. KOIZUMI   08/831,180   2-Apr-97   23-Apr-92   6103/0237       500.31164VV3   S. KOIZUMI   09/080,241   18-May-98   23-Apr-92   6103/0237       500.31164CC5   S. KOIZUMI   09/222,954   30-Dec-98   23-Apr-92   6103/0237       500.31164CV6   S. KOIZUMI   10/762,373   23-Jan-04   23-Apr-92   6103/0237       500.31833X00   H. ITOH   08/001,248   6-Jan-93   6-Jan-93   6405/641       500.31833CX1   H. ITOH   08/667,583   24-Jun-96   6-Jan-93   6405/641       500.31833CC2   H. ITOH   08/975,054   20-Nov-97   6-Jan-93   6405/641       500.31833CC3   H. ITOH   09/407,840   29-Sep-99   6-Jan-93   6405/641       500.31833CC4   H. ITOH   10/285,447   1-Nov-02   6-Jan-93   6405/641       500.31833CC5   H. ITOH   10/659,292   11-Sep-03   6-Jan-93   6405/641       500.33470X00   T. YAMAGUCHI   08/371,376   11-Jan-95   11-Jan-95   7315/0126       500.33470CC2   T. YAMAGUCHI   08/948,071   9-Oct-97   11-Jan-95   7315/0126       500.33470CC3   T. YAMAGUCHI   09/638,027   15-Aug-00   11-Jan-95   7315/0126       500.33470CC4   T. YAMAGUCHI   09/963,473   27-Sep-01   11-Jan-95   7315/0126       500.33470CC5   T. YAMAGUCHI   10/337,321   7-Jan-03   11-Jan-95   7315/0126       500.33470CC6   T. YAMAGUCHI   10/963,508   14-Oct-04   11-Jan-95   7315/0126       500.33718CX4   R. Hattori   10/336,796   6-Jan-03   3-May-98   7475/778       500.33718X00   R. Hattori   08/434,291   3-May-95   3-May-98   7475/778       500.33718VX1   R. Hattori   09/106,291   29-Jun-98   3-May-98   7475/778       500.33718VX2   R. Hattori   09/518,147   3-Mar-00   3-May-98   7475/778       500.33718VX3   R. Hattori   10/082,185   26-Feb-02   3-May-98   7475/778       500.37943X00   Y. NAKANO   09/452,172   1-Dec-99   1-Dec-99   010432/0607       500.37943CX1   Y. NAKANO   10/242,441   13-Sep-02   1-Dec-99   010432/0607       500.37943CX2   Y. NAKANO   10/725,454   3-Dec-03   1-Dec-99   010432/0607       500.33152X00   O. NISHII   08/301,887   7-Sep-94   7-Sep-94   7141/0420       500.33152CX1   O. NISHII   08/815,600   12-Mar-97   7-Sep-94   7141/0420       500.33152CX2   O. NISHII   09/188,902   10-Nov-98   7-Sep-94   7141/0420       500.33152CX3   O. NISHII   09/641,913   21-Aug-00   7-Sep-94   7141/0420       500.33152R00   O. NISHII   10/290,367   8-Nov-02   7-Sep-94   7141/0420       500.33218X00   Y. TONOMURA   08/314,373   28-Sep-94   28-Sep-94   7315/004       500.33218CX1   Y. TONOMURA   08/670,774   20-Jun-96   28-Sep-94   7315/004       500.33218CR2   Y. TONOMURA   09/625,508   25-Jul-00   28-Sep-94   7315/004       500.38010X00   T. TAKAHASHI   09/461,192   15-Dec-99   15-Dec-99   010465/0117       500.38010CX1   T. TAKAHASHI   10/834,044   29-Apr-04   15-Dec-99   010465/0117       500.36680X00   T. HIRATA   09/179,091   27-Oct-98   27-Oct-98   9551/0444       500.36680CX1   T. HIRATA   09/793,970   28-Feb-01   27-Oct-98   9551/0444       500.36680CX2   T. HIRATA   10/893,990   20-Jul-04   27-Oct-98   9551/0444       500.31715X00   K. KITAMURA   07/977,249   16-Nov-92   10-Oct-95   7699/937       500.31715PX1   K. KITAMURA   08/483,885   7-Jun-95   10-Oct-95   7699/937       500.33678X00   M. SAITO   08/421,249   13-Apr-95   9-Jun-95   7507/141       500.33678VX1   M. SAITO   09/167,498   7-Oct-98   9-Jun-95   7507/141       500.33678VC2   M. SAITO   10/342,272   15-Jan-03   9-Jun-95   7507/141       500.33678CV3   M. SAITO   10/965,847   18-Oct-04   9-Jun-95   7507/141       500.36365X00   T. SEKIGUCHI   09/107,388   30-Jun-98   30-Jun-98   9303/0621       500.36365CX1   T. SEKIGUCHI   09/858,492   17-May-01   30-Jun-98   9303/0621       500.36365CC2   T. SEKIGUCHI   10/861,482   7-Jun-04   30-Jun-98   9303/0621       500.35522X00   S. HAMAMOTO   08/887,123   2-Jul-97   8-Jul-97   8685/0560       500.35522CX1   S. HAMAMOTO   09/472,838   28-Dec-99   8-Jul-97   8685/0560       500.35522CX2   S. HAMAMOTO   10/175,496   20-Jun-02   8-Jul-97   8685/0560       500.35522CX3   S. HAMAMOTO   10/175,494   20-Jun-02   8-Jul-97   8685/0560       500.35522CX4   S. HAMAMOTO   10/175,361   20-Jun-02   8-Jul-97   8685/0560       500.40511X00   C. OKAMOTO   09/931,251   17-Aug 01   9-Oct-01   012248/0372       500.42702X00   R. KANAZAWA   10/417,195   17-Apr-03   25-Jun-03   014213/0298       500.37036X00   T. KOMACHIYA   09/254,956   22-Mar-99   22-Mar-99   010442/0368       500.37036CX1   T. KOMACHIYA   10/123,404   17-Apr-02   22-Mar-99   010442/0368       500.36167X00   T. NAOKI   09/050,064   30-Mar-98   30-Mar-98   9078/0669       500.36167CX1   T. NAOKI   09/496,465   2-Feb-00   30-Mar-98   9078/0669       500.36167CX4   T. NAOKI   10/915,566   11-Aug-04   30-Mar-98   9078/0669       500.36167CX2   T. NAOKI   09/662,161   14-Sep-00   30-Mar-98   9078/0669       500.36167CX3   T. NAOKI   10/095,058   12-Mar-02   30-Mar-98   9078/0669       500.35819X00   K. SAKAMOTO   08/970,159   13-Nov-97   13-Nov-97   8912/0350       500.35819CX1   K. SAKAMOTO   09/411,655   4-Oct-99   13-Nov-97   8912/0350       500.35819CX2   K. SAKAMOTO   09/638,028   15-Aug-00   13-Nov-97   8912/0350       500.35819CX3   K. SAKAMOTO   09/906,677   18-Jul-01   13-Nov-97   8912/0350       500.35819CX4   K. SAKAMOTO   10/894,060   20-Jul-04   13-Nov-97   8912/0350       500.43813X00   T. KUSAMA   01/834,839   30-Apr-04   21-Jul-04   015589/0904       500.43809X00   T. NAKAMURA   10/834,837   30-Apr-04   21-Jul-04   015589/0938       500.40609X00   H. ITO   09/942,873   31-Aug-01   3-Dec-01   012342/0874       500.40609CX1   H. ITO   10/317,113   12-Dec-02   3-Dec-01   012342/0874       500.40609CX2   H. ITO   10/725,455   3-Dec-03   3-Dec-01   012342/0874       500.43259X00   T. MAEDA   10/699,735   4-Nov-03   12-Feb-04   014976/0898       500.42884X00   T. ENDO   10/608,209   30-Jun-03   30-Jun-03   014247/0030       500.42881X00   J. YOSHIDA   10/608,208   30-Jun-03   30-Sep-03   014540/0899       500.38297X00   S. KOBAYASHI   09/518,214   3-Mar-00   25-May-00   010811/0190       500.37485X00   H. KAZUO   09/383,370   26-Aug-99   26-Aug-99   010210/0606       500.37485CX1   H. KAZUO   10/412,388   14-Apr-03   26-Aug-99   010210/0606       500.37485CX2   H. KAZUO   10/412,232   14-Apr-03   26-Aug-99   010210/0606       500.42662X00   T. YOSHIMOTO   10/405,616   3-Apr-03   3-Apr-03   013941/0046       500.38485X00   H. MOTOAKI   09/553,762   21-Apr-00   12-Jul-00   010917/0296       500.38485CX1   H. MOTOAKI   09/812,781   15-Mar-01   12-Jul-00   010917/0296       500.38485CC2   H. MOTOAKI   10/395,249   25-Mar-03   12-Jul-00   010917/0296       500.42278X00   H. MURAMATSU   10/304,077   26-Nov-02   12-Sep-03   014487/0486       500.42379X00   T. SHINODA   10/339,314   10-Jan-03   6-Mar-03   013825/0584       500.42212X00   T. YANO   10/287,676   5-Nov-02   8-Jan-03   013646/0948       500.42042X00   K. SATOSHI   10/233,572   4-Sep-02   12-Nov-02   013490/0887       500.42047X00   K. ICHIKAWA   10/233,573   4-Sep-02   3-Mar-03   013807/0178       500.35873X00   S. TAKASHIMIZU   08/986,074   5-Dec-97   5-Dec-97   8912/0959       500.35873CX1   S. TAKASHIMIZU   10/470,635   23-Jan-01   5-Dec-97   8912/0959       500.35873CX2   S. TAKASHlMlZU   09/851,196   9-May-01   5-Dec-97   8912/0959       500.35873CX3   S. TAKASHIMIZU   10/164,614   10-Jun-02   5-Dec-97   8912/0959       500.35873CX4   S. TAKASHIMIZU   10/435,248   12-May-03   5-Dec-97   8912/0959       500.42704X00   I. YAGISAWA   10/419,096   21-Apr-03   4-Aug-03   014350/497       500.42704CX1   I. YAGISAWA   10/962,623   13-Oct-04   4-Aug-03   014350/497       500.42704CX2   I. YAGISAWA   10/962,599   13-Oct-04   4-Aug-03   014350/497       500.42704CX3   I. YAGISAWA   10/988,495   16-Nov-04   4-Aug-03   014350/497       500.42704CX4   I. YAGISAWA   10/988,496   16-Nov-04   4-Aug-03   014350/497       500.42704CX5   I. YAGISAWA   10/988,704   16-Nov-04   4-Aug-03   014350/497       500.42704CX6   I. YAGISAWA   10/988,564   16-Nov-04   4-Aug-03   014350/497       500.35527X00   T. SHIBA   08/875,182   21-Jul-97   21-Jul-97   008712/0963       500.35527CX1   T. SHIBA   09/558,373   26-Apr-00   21-Jul-97   008712/0963       500.35527CX2   T. SHIBA   10/730,003   9-Dec-03   21-Jul-97   008712/0963       500.41928X00   T. SAITO   10/206,935   30-Jul-02   30-Jul-02   013154/0582       500.41163X00   N. TAKAOKA   10/066,676   6-Feb-02   6-Feb-02   012560/0771       500.36700X00   E. MATSUMURA   09/188,245   9-Nov-98   9-Nov-98   9590/0198       500.36700CX2   E. MATSUMURA   10/417,267   17-Apr-03   9-Nov-98   9590/0198       500.42045X00   H. SOMEYA   10/233,513   4-Sep-02   19-Nov-02   013507/0374       500.42000X00   M. HIRABAYASHI   10/230,277   29-Aug-02   7-Nov-02   013470/0839       500.36144X00   D. MORI   09/046,704   24-Mar-98   24-Mar-98   9057/0019       500.36144CX1   D. MORI   09/519,746   6-Mar-00   24-Mar-98   9057/0019       500.36144CX2   D. MORI   10/152,835   23-May-02   24-Mar-98   9057/0019       500.41713X00   M. HARA   10/147,888   20-May-02   20-May-02   012921/0626       500.41715X00   K. IWADE   10/147,879   20-May-02   20-May-02   012921/0644       500.41657X00   T. KUSAMA   10/140,981   9-May-02   17-Jul-02   013104/0240       500.41684X00   M. HIRAYAMA   10/137,448   3-May-02   29-Jul-02   013135/0095       500.41659X00   H. YUI   10/128,284   24-Apr-02   17-Jun-02   013009/0102       500.41083X00   D. WATANABE   10/046,167   16-Jan-02   2-Dec-98   9650/0845       500.41083CX1   D. WATANABE   10/124,577   18-Apr-02   2-Dec-98   9650/0845       500.41758X00   M. SAKATSUME   10/160,087   4-Jun-02   29-Aug-02   013246/0258       500.41411X00   T. TANAKA   10/096,861   14-Mar-02   14-Mar-02   012704/0060       500.41164X00   S. SEKIGUCHI   10/066,660   6-Feb-02   17-Jun-02   013001/0765       500.25179X00   Y. SAKURAI   07/096,011   14-Sep-87   14-Sep-87   004777/0869       500.25179PX1   S. TANABE   07/645,491   24-Jan-91   24-Jan-91   5592/019       500.25179CP1   S. TANABE   08/438,959   11-May-95   24-Jan-91   5592/019       500.25179CP2   S. TANABE   08/838,950   23-Apr-97   24-Jan-91   5592/019       500.25179CX1   Y. SAKURAI   07/654,590   13-Feb-91   14-Sep-87   004777/0869       500.25179CX3   Y. SAKURAI   08/435,960   5-May-95   14-Sep-87   004777/0869       500.25179CX2   Y. SAKURAI   08/435,961   5-May-95   14-Sep-87   004777/0869       500.25179CX4   Y. SAKURAI   08/903,176   30-Jul-97   14-Sep-87   004777/0869       500.25179CX5   Y. SAKURAI   09/373,596   13-Aug-99   14-Sep-87   004777/0869       500.25179CX6   Y. SAKURAI   09/373,599   13-Aug-99   14-Sep-87   004777/0869       500.25179CX7   Y. SAKURAI   09/873,280   5-Jun-01   14-Sep-87   004777/0869       500.25179CX8   Y. SAKURAI   10/102,912   22-Mar-02   14-Sep-87   004777/0869       500.25179CP3   S. TANABE   09/340,139   28-Jun-99   24-Jan-91   5592/019       500.25179CP4   S. TANABE   09/467,213   20-Dec-99   24-Jan-91   5592/019       500.25179CP5   S. TANABE   10/040,466   9-Jan-02   24-Jan-91   5592/019