Abstract:
A nonvolatile memory device is operated by receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    Priority to Korean patent application number 10-2009-0059151 filed on Jun. 30, 2009, the entire disclosure of which is incorporated by reference herein, is claimed. 
       BACKGROUND 
       [0002]    Exemplary embodiments relate generally to a method of operating a nonvolatile memory device, and more particularly to a method of operating a nonvolatile memory device which is capable of reading two planes at the same time. 
         [0003]    Electrically programmable and erasable nonvolatile memory devices which do not require refresh function of rewriting data at specific intervals are increasingly in demand. 
         [0004]    A nonvolatile memory device typically includes a plane having a number of memory blocks. However, nonvolatile memory devices having a multi-plane structure having a number of planes are increasingly more in use. 
         [0005]    Several operations are performed in a nonvolatile memory device such as: a program operation for writing data in a memory cell, a read operation for reading data stored in a memory cell, an erase operation for erasing data stored in a memory cell, and so on. 
         [0006]    A multi-level cell (hereinafter referred to as “the MLC”) program method is a program method of storing information of 2 bits or more in one cell. In a single level cell (hereinafter referred to as “the SLC”) program method, two states with different threshold voltages are produced by a program operation. In the MLC program method, however, the above program operation is repeatedly performed to store information of 2 bits or more. In the MLC program operation, a least significant bit (hereinafter referred to as “the LSB”) program operation and a most significant bit (hereinafter referred to as “the MSB”) program operation are performed. 
         [0007]    When data is read from two planes at the same time, a read operation is performed on the two planes only when the same program operation has been performed on the two planes. That is, only when the MSB program operation has been performed on the two planes or the LSB program operation has been performed on the two planes, the read operation is performed on the two planes at the same time. After the program operation is performed on the two planes so that they have the same program states, the read operation is then performed on the two planes. This presents many problems one of which, inter alia, is that, if the two planes have different program states, the read operation cannot be performed on the two planes at the same time. 
       BRIEF SUMMARY 
       [0008]    Exemplary embodiments relate to a method of operating a nonvolatile memory device, which is capable of performing a read operation on two planes in the case in which the two planes are programmed to have different MSB program states. 
         [0009]    A method of operating a nonvolatile memory device according to an aspect of the present disclosure comprises receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data. 
         [0010]    Checking whether an MSB program operation has been performed on each of the first and second planes is performed based on information read from a flag cell of each of the first and second planes. 
         [0011]    The method further comprises, after receiving the MSB read address, performing the read operation on the first and second planes on the basis of a first read voltage for reading memory cells having a lowest threshold voltage distribution, from among memory cells on which an MSB program operation has been performed, and storing the read data in respective page buffers of the first and second planes. 
         [0012]    Performing the read operation on the first and second planes according to a result of the check and outputting the read data comprises resetting the data stored in the page buffers and outputting the reset data, if, as a result of the check, the MSB program operation has not been performed on both the first and second planes. 
         [0013]    Performing the read operation on the first and second planes according to a result of the check and outputting the read data comprises performing the read operation on the first and second planes on the basis of a number of read voltages other than the first read voltage, if, as a result of the check, the MSB program operation has been performed on both the first and second planes. 
         [0014]    Performing the read operation on the first and second planes according to a result of the check and outputting the read data comprises performing the read operation on the second plane on the basis of a number of read voltages other than the first read voltage, outputting the read data, resetting the data stored in the page buffer of the first plane, and outputting the reset data, if, as a result of the check, the MSB program operation has not been performed on the first plane, but has been performed on the second plane. 
         [0015]    Performing the read operation on the first and second planes according to a result of the check and outputting the read data comprises performing the read operation on the first plane on the basis of a number of read voltages other than the first read voltage, outputting the read data, resetting the data stored in the page buffer of the second plane, and outputting the reset data, if, as a result of the check, the MSB program operation has been performed on the first plane, but has not been performed on the second plane. 
         [0016]    A method of operating a nonvolatile memory device according to an aspect of the present disclosure comprises receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an LSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data. 
         [0017]    Checking whether an MSB program operation has been performed on each of the first and second planes is performed based on information read from a flag cell of each of the first and second planes. 
         [0018]    The method further comprises, after receiving the LSB read address, performing the read operation on the first and second planes on the basis of a second read voltage for reading data of LSB components from memory cells on which an MSB program operation has been performed and storing the read data in respective page buffers of the first and second planes. 
         [0019]    Performing the read operation on the first and second planes according to a result of the check and outputting the read data comprises performing the read operation on the first and second planes on the basis of a read voltage for reading memory cells on which an LSB program operation has been performed and outputting the read data, if, as a result of the check, the MSB program operation has not been performed on both the first and second planes. 
         [0020]    Performing the read operation on the first and second planes according to a result of the check and outputting the read data comprises outputting the data stored in the page buffers of the first and second planes, if, as a result of the check, the MSB program operation has been performed on both the first and second planes. 
         [0021]    Performing the read operation on the first and second planes according to a result of the check and outputting the read data comprises performing the read operation on the first plane on the basis of a read voltage for reading memory cells on which an LSB program operation has been performed, outputting the read data, and outputting the data stored in the page buffer of the second plane, if, as a result of the check, the MSB program operation has not been performed on the first plane, but has been performed on the second plane. 
         [0022]    Performing the read operation on the first and second planes according to a result of the check and outputting the read data comprises the read operation on the second plane on the basis of a read voltage for reading memory cells on which an LSB program operation has been performed, outputting the read data, and outputting the data stored in the page buffer of the first plane, if, as a result of the check, the MSB program operation has been performed on the first plane, but has not been performed on the second plane. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a block diagram of a nonvolatile memory device according to an embodiment of this disclosure; 
           [0024]      FIG. 2  is a diagram showing the distributions of the threshold voltages of memory cells according to an embodiment of this disclosure; 
           [0025]      FIG. 3  is a flowchart illustrating a method of operating the nonvolatile memory device according to an embodiment of this disclosure; and 
           [0026]      FIG. 4  is a flowchart illustrating a method of operating the nonvolatile memory device according to another embodiment of this disclosure. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0027]    Hereinafter, some exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to allow those having ordinary skill in the art to understand the scope of embodiments of the disclosure. 
         [0028]      FIG. 1  is a block diagram of a nonvolatile memory device according to an embodiment of this disclosure. 
         [0029]    Referring to  FIG. 1 , the nonvolatile memory device according to an embodiment of this disclosure includes a first plane  110 , a second plane  120 , a first page buffer unit  130 , a second page buffer unit  140 , a first X decoder  150 , a second X decoder  160 , a controller  170 , a voltage generator  180 , a first data I/O unit  190 , a second data I/O unit  200 , and an input buffer  210 . 
         [0030]    Program, read, and erase operations are performed on the first plane  110  by the first page buffer unit  130  coupled to the first plane  110 . Likewise, program, read, and erase operations are performed on the second plane  120  by the second page buffer unit  140  coupled to the second plane  120 . Each of the first plane  110  and the second plane  120  includes a number of memory blocks. The first plane  110  is illustrated to include, for example, a first memory block B 1  in  FIG. 1 . The memory block includes memory cells for storing data and flag cells for storing information indicative of whether an MSB program has been performed. Oblique lines as shown in  FIG. 1  in the first plane  110  and the second plane  120  indicate the flag cells. 
         [0031]    The controller  170  controls a variety of operations of the nonvolatile memory device such as the program operation, the read operation, the erase operation, and so on. More particularly, the controller  170  receives an external address ADD via the input buffer  210 , outputs a first row address RADD 1  to the first X decoder  150 , outputs a second row address RADD 2  to the second X decoder  160 , outputs a first column address CADD 1  to the first page buffer unit  130 , and outputs a second column address CADD 2  to the second page buffer unit  140 . 
         [0032]    Further, the controller  170  receives an external command CMD via the input buffer  210  and controls the voltage generator  180  so that it supplies high voltages for the various operations of the first plane  110  and the second plane  120 . 
         [0033]    The first data I/O unit  190  functions to transfer external input data to the first page buffer  130  or to output data stored in the first page buffer  130  externally. 
         [0034]    The second data I/O unit  200  functions to transfer external input data to the second page buffer  140  or to output data stored in the second page buffer  140  externally. 
         [0035]      FIG. 2  is a diagram showing the distributions of the threshold voltages of memory cells according to an embodiment of this disclosure. 
         [0036]    Referring to  FIG. 2 , in an LSB program operation, two distributions with different program states are produced by the program operation. More particularly, a distribution of the threshold voltages of memory cells programmed with higher than a first read voltage VR 1  is referred to as a second state, and a distribution of the threshold voltages of memory cells programmed with less than the first read voltage VR 1  is referred to as a first state. 
         [0037]    In the state in which the LSB program operation has been performed as described above, an MSB program operation is performed. Distributions of the threshold voltages with four different program states, for example, third to sixth states, are produced by the MSB program operation. Here, the distributions of the threshold voltages are higher in the order of the third state, the fourth state, the fifth state, and the sixth state as shown in  FIG. 2 . The distribution of the threshold voltages having the sixth state is produced using a read voltage higher than a third read voltage VR 3 . The distribution of the threshold voltages having the fifth state is produced using a read voltage higher than a second read voltage VR 2 , but less than the third read voltage VR 3 . The distribution of the threshold voltages having the fourth state is produced using a read voltage higher than a first read voltage VR 1 , but less than the second read voltage VR 2 . The distribution of the threshold voltages having the third state is produced using a read voltage less than a first read voltage VR 1 . 
         [0038]    In an embodiment of the present disclosure, to check whether only an LSB program operation or only an MSB program operation has been performed on a programmed page, the flag cell is used. Data indicating whether the MSB program operation has been performed on the corresponding page is stored in the flag cell. For example, during the LSB program operation, a program operation may not be performed on the flag cell, but during the MSB program operation, the program operation may be performed on the flag cell. Accordingly, whether the MSB program operation has been performed can be checked by reading data stored in the flag cell. 
         [0039]      FIG. 3  is a flowchart illustrating a method of operating the nonvolatile memory device according to an embodiment of this disclosure. The method of operating the nonvolatile memory device is described below with reference with  FIG. 3  together with  FIGS. 1 and 2 . 
         [0040]    A dual plane read command for reading the first plane  110  and the second plane  120  at the same time is received at step S 301 . For example, the dual plane read command can be received through the input buffer  210 , and the controller  170  can perform the read operation on the first plane  110  and the second plane  120  in response to the dual plane read command. 
         [0041]    An MSB read address for reading data stored in MSB-programmed memory cells is received at step S 303 . For example, the MSB read address can be received through the input buffer  210 . In an embodiment of the present disclosure, the MSB read address has a larger number of bits than an LSB read address. Thus, the controller  170  can determine whether a received address is the MSB read address or the LSB read address, for example, on the basis of the number of bits of the received address. 
         [0042]    The controller  170  performs the read operation on the first plane  110  and the second plane  120  on the basis of a first read voltage VR 1  at step S 305 . The read data is stored in the first page buffer unit  130  and the second page buffer unit  140 . 
         [0043]    It is determined whether an MSB program operation has been performed on the first plane  110  at step S 307 . It is determined whether an MSB program operation has been performed the second plane  120  at steps S 309  and S 311 . In an embodiment of this disclosure, whether the MSB program operation has been performed can be checked by reading data stored in the flag cells of the first plane  110  and the second plane  120 . 
         [0044]    The following four cases are then possible according to whether the MSB program operation has been performed on the first plane  110  and/or the second plane  120 . 
         [0045]    The first case (S 313 , S 315 ) corresponds to a state in which the MSB program operation has not been performed on both the first plane  110  and the second plane  120 . In this case, the data stored in the first page buffer unit  130  of the first plane  110  and the data stored in the second page buffer unit  140  of the second plane  120  are reset at step S 313 . The pieces of reset data are output through the first data I/O unit  190  and the second data I/O unit  200 , respectively, at step S 315 . For example, the data stored in the first page buffer unit  130  and the second page buffer unit  140  can be reset to 1 and then outputted. 
         [0046]    The second case (S 317 , S 319 , S 321 ) corresponds to a state in which the MSB program operation has not been performed on the first plane  110  but has been performed on the second plane  120 . In this case, the read operation is performed on the second plane  120  on the basis of a second read voltage VR 2  and a third read voltage VR 3  at step S 317 . The data stored in the first page buffer  130  of the first plane  110  is reset at step S 319 . The data stored in the first page buffer unit  130  and the data stored in the second page buffer unit  140  are respectively outputted through the first data I/O unit  190  and the second data I/O unit  200  at step S 321 . 
         [0047]    The third case (S 323 , S 325 , S 327 ) corresponds to a state in which the MSB program operation has been performed on the first plane  110  but has not been performed on the second plane  120 . In this case, the read operation is performed on the first plane  110  on the basis of a second read voltage VR 2  and a third read voltage VR 3  at step S 323 . The data stored in the second page buffer  140  of the second plane  120  is reset at step S 325 . The data stored in the first page buffer unit  130  and the data stored in the second page buffer unit  140  are respectively outputted through the first data I/O unit  190  and the second data I/O unit  200  at step S 327 . 
         [0048]    The fourth case (S 329 , S 331 ) corresponds to a state in which the MSB program operation has been performed on both the first plane  110  and the second plane  120 . In this case, the read operation is performed on both the first plane  110  and the second plane  120  on the basis of a second read voltage VR 2  and a third read voltage VR 3  at step S 329 . The data stored in the first page buffer unit  130  and the data stored in the second page buffer unit  140  are respectively outputted through the first data I/O unit  190  and the second data I/O unit  200  at step S 331 . 
         [0049]      FIG. 4  is a flowchart illustrating a method of operating the nonvolatile memory device according to another embodiment of this disclosure. 
         [0050]    A dual plane read command for reading the first plane  110  and the second plane  120  at the same time is received at step S 401 . For example, the dual plane read command can be received through the input buffer  210 , and the controller  170  can perform the read operation on the first plane  110  and the second plane  120  in response to the dual plane read command. 
         [0051]    An LSB read address for reading data of LSB components is received at step S 403 . For example, the LSB read address can be received through the input buffer  210 . In an embodiment of the present disclosure, the LSB read address has the number of bits smaller than an MSB read address. Thus, the controller  170  can determine whether a received address is the MSB read address or the LSB read address on the basis of the number of bits of the received address. 
         [0052]    The controller  170  performs the read operation on the first plane  110  and the second plane  120  on the basis of a second read voltage VR 2  at step S 405 . The read data is stored in the first page buffer unit  130  and the second page buffer unit  140 . 
         [0053]    It is determined whether the MSB program operation has been performed on the first plane  110  at step S 407 . It is determined whether the MSB program operation has been performed the second plane  120  at steps S 409  and S 411 . In an embodiment of this disclosure, whether the MSB program operation has been performed can be checked, for example, by reading data stored in the flag cells of the first plane  110  and the second plane  120 . 
         [0054]    The following four cases are then possible according to whether the MSB program operation has been performed on the first plane  110  and the second plane  120  according to an embodiment of this disclosure. 
         [0055]    The first case (S 413 , S 415 ) corresponds to a state in which the MSB program operation has not been performed on both the first plane  110  and the second plane  120 . In this case, the read operation is performed on the first plane  110  and the second plane  120  on the basis of a first read voltage VR 1 , and the read data is stored in the first page buffer unit  130  and the second page buffer unit  140  at step S 413 . The data stored in the first page buffer unit  130  and the data stored in the second page buffer unit  140  are respectively outputted through the first data I/O unit  190  and the second data I/O unit  200  at step S 415 . 
         [0056]    The second case (S 417 , S 419 ) corresponds to a state in which the MSB program operation has not been performed on the first plane  110  but has been performed on the second plane  120 . In this case, the read operation is performed on the first plane  110  on the basis of a first read voltage VR 1  and the read data stored in the first page buffer  130  at step S 417 . The data stored in the first page buffer unit  130  and the data stored in the second page buffer unit  140  are respectively outputted through the first data I/O unit  190  and the second data I/O unit  200  at step S 419 . At step S 419 , the second page buffer unit  140  coupled to the second plane  120  stores the data read by the read operation on the basis of the second read voltage VR 2  and output the stored data. Since the MSB program operation has been performed on the second plane  120 , the second page buffer unit  140  stores the data of LSB components and outputs the stored data. 
         [0057]    The third case (S 421 , S 423 ) corresponds to a state in which the MSB program operation has been performed on the first plane  110  but has not been performed on the second plane  120 . In this case, the read operation is performed on the second plane  120  on the basis of a first read voltage VR 1 , and the read data is stored in the second page buffer  140  at step S 421 . The data stored in the first page buffer unit  130  and the data stored in the second page buffer unit  140  are respectively outputted through the first data I/O unit  190  and the second data I/O unit  200  at step S 423 . At step S 423 , the first page buffer unit  130  coupled to the first plane  110  stores the data read by the read operation on the basis of a second read voltage VR 2  and outputs the stored data. Since the MSB program operation has been performed on the first plane  110 , the first page buffer unit  130  stores the data of LSB components and outputs the stored data. 
         [0058]    The fourth case (S 425 ) corresponds to a state in which the MSB program operation has been performed on both the first plane  110  and the second plane  120 . In this case, the data stored in the first page buffer unit  130  and the data stored in the second page buffer unit  140  are respectively outputted through the first data I/O unit  190  and the second data I/O unit  200  at step S 425 . At step S 425 , the first page buffer unit  130  coupled to the first plane  110  and the second page buffer unit  140  coupled to the second plane  120  store the pieces of data read by the read operation on the basis of a second read voltage VR 2  and output the data. Since the MSB program operation has been performed on the first plane  110  and the second plane  120 , the first page buffer unit  130  and the second page buffer unit  140  store the data of LSB components and output the stored data. 
         [0059]    In accordance with embodiments of the present disclosure, the read operation for reading two planes at the same time can be performed irrespective of whether an MSB program operation has been performed on each of the planes. Accordingly, malfunctions are prevented which can occur because two planes on which a read operation will be performed have different MSB program operation states.