Abstract:
PN junction structure including a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provided.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to PN junctions and to their fabrication. More specifically, the invention concerns PN junction structures that must sustain high reverse voltages without breaking down. 
     2. Discussion of the Related Art 
     Breakdown in a PN junction is due to two different phenomena, depending on the dopant concentrations of the junction&#39;s regions: avalanche breakdown and Zener breakdown. 
     If the dopant concentration of the junction&#39;s doped regions is low, avalanche breakdown takes place. If the dopant concentration is high, Zener breakdown occurs. 
     In both cases, however, junction breakdown occurs when the maximum electric field reaches a critical value. The critical value of the electric field depends on the voltage applied to the junction, as well as on the dopant concentration of the doped regions thereof. To increase the breakdown voltage of a junction it is therefore necessary to decrease the dopant concentration of the doped regions thereof. 
     On the other hand, a lower dopant concentration makes it necessary to have thicker P and N regions, because the depletion region spreads out. The extension of the depletion region, the concentration of dopants in the silicon and the voltage applied to the junction are linked by the Poisson&#39;s equations. 
     Thicker silicon regions have, however, higher on resistances. 
     Normally, in power semiconductor devices designed for high voltages, the junctions are of the PIN (P-Intrinsic-N) type, so as to reduce the silicon thickness and thus decreasing the on resistance value. Nevertheless, in these devices the junction area must be augmented to achieve reasonable (i.e., rather low) forward-bias voltage drops. This problem is exacerbated in unipolar conduction devices, where no modulation of conductivity exists. 
     An object of the present invention is to provide a PN junction structure having a high breakdown voltage. 
     SUMMARY OF THE INVENTION 
     According to the present invention, this and other objects are achieved by a PN junction structure comprising a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provided. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will be made apparent by the following detailed description of some embodiments thereof, illustrated by way of non-limiting examples only in the annexed drawings, wherein: 
     FIG. 1 shows in cross-section along a vertical plane a PN junction structure according to the present invention; 
     FIGS. 2A,  2 B and  2 C shows, in cross-section along line II—II of FIG. 1, three different embodiments of the present invention; 
     FIG. 3 is a cross-section along a vertical plane of a MOS-gated power device incorporating a PN junction structure according to the present invention; 
     FIG. 4 is a diagram showing the dopant concentration in the doped regions of the MOS-gated power device of FIG. 3, and an electric field distribution along line a—a in FIG. 3; 
     FIG. 5 is a diagram showing the dopant concentration and the electric field distribution along line b—b in FIG. 3; 
     FIG. 6 shows an enlarged detail of FIG. 3, with equipotential lines; 
     FIGS. 7 to  14  show some steps of a fabrication process according to one embodiment of the present invention; and 
     FIGS. 15 to  20  show some steps of a fabrication process according to another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     With reference to FIG. 1, a PN junction structure according to the present invention is shown. 
     Even if the invention applies in general to PN junctions, the structure shown by way of example is that of a PIN junction. A PIN junction comprises a P junction region, an N junction region and, interposed between the N and P regions, a near intrinsic or lightly doped region. In the shown example, the PIN junction has an N type region or layer  1 , a P type region or layer  2 , a lightly doped N− region or layer  3  interposed between the P and N regions or layers  1 ,  2 . An N+ region or layer  4  is provided at the N type region or layer  1  side. A metal layer  5  contacts the P type region or layer  2 . 
     Substantially at the interface between the N type region or layer  1  and the N− region or layer  3 , a grid of buried silicon dioxide regions  6  is provided. It should be noted that even if the location of the grid of buried silicon dioxide regions  6  at the interface between the N type region or layer  1  and the N− region or layer  3  is preferable, it is not a limitation of the invention. The grid of buried silicon dioxide regions could as well be located in any other position from the interface between regions or layers  1 ,  3 , to the interface between regions or layers  3 ,  2 . 
     FIGS. 2A,  2 B and  2 C show three possible embodiments of the grid of oxide regions  6 . The grid can be in the form of small isolated pillars  6 A, as in FIG. 2A, or in the form of oxide stripes  6 B, as in FIG. 2B, or even in the form of a mesh of crossing oxide stripes  6 C extending along two orthogonal directions in the plane. Other shapes for the grid of oxide regions  6  are conceivable, the specific shape not being a limitation of the present invention. 
     The grid of buried oxide regions  6 , whatever the form thereof, acts as a field stopper. The high dielectric strength of the oxide is exploited to block the spreading of the depletion region of the junction. A good thermally-grown oxide is capable of sustaining electric fields up to 1000 V/micron. 
     The buried oxide regions  6  must form a grid, in order to allow flow of current in the forward conduction state. Between the buried oxide regions  6  high-conductivity silicon or polysilicon are preferably provided. The distance between the buried oxide regions  6 , i.e. the size of the grid, needs to be properly dimensioned: it must not be too small, so as not to excessively reduce the conduction area, and at the same time it must not be too large, so as not to alter the local distribution of the electric field. 
     FIG. 3 shows in cross-section a MOS-gated power device provided with a PN junction structure according to the present invention. In particular, the structure is that of a power MOS, with an N+ substrate  7  over which an N− drift layer  8  is provided. P type body regions  9  are formed in the N− drift layer. The P type body regions can either be polygonal cells or stripes. Inside the P type body regions  9 , N type source regions  10  are formed. A polysilicon gate  11  is insulatively disposed over the N− drift layer  8  between adjacent P type body regions  9 . The polysilicon gate  11  is covered by a dielectric layer  12 , and a source metal plate contacts all of the P type body regions  9  and N type source regions  10 . A drain metal plate  12  contacts the back surface of N+ substrate  7 . 
     Substantially at the interface between the N+ substrate  7  and the N− drift layer  8 , a grid of buried oxide regions  60  are formed according to the present invention. The grid of buried oxide regions  60  can have in principle any shape, for example those shown in FIGS. 2A,  2 B,  2 C. The holes  13  between the buried oxide regions  60  are preferably located under the polysilicon gate. 
     FIG. 4 is a diagram showing, curve A, the dopant concentration along line a—a of FIG. 3 and, dash-and-dot curve B, the electric field E along the same line a—a. The dopant concentration in the holes  13  between the buried oxide regions  60  is preferably higher than that of the drift layer  8 ; this assures a good current conduction, and makes it possible to withstand high electric fields. Curve B relates to a case in which the body/drain junction is reverse biased at 500 V. The grid of buried oxide regions acts as a field stopper, blocking the extension of the electric field of the junction P type body regions/drift layer towards the substrate. This is visible in curve B, where the value of the electric field in the holes  13 , and thus in the buried oxide regions  60 , is significantly higher compared to a situation in which no buried oxide regions are provided. This derives from the fact that silicon dioxide has a relative dielectric constant equal to ⅓ that of silicon. As a result, the thickness of the drift layer can be significantly reduced, with a great benefit for the device&#39;s “on” resistance (Ron). As is known, in power devices, and especially in the unipolar ones, the main contribution to the Ron comes from the resistance of the drift layer. The higher the resistivity and the thickness of the drift layer, the higher the device&#39;s Ron. In the present structure, the device&#39;s Ron is the sum of R 1 +R 2 , where R 1  is the resistance of the drift layer  8  above the buried oxide regions  60 , and R 2  is the resistance of the holes  13  between the buried oxide regions  60 . R 2  depends on the ratio between the area of the holes  13  and the overall area of the device. Assuming by way of example only that such a ratio is equal to 0.35, and assuming also the following: 
     drift layer thickness: 9×10 −4  cm 
     drift layer resistivity: 9 Ωcm 
     buried oxide thickness: 18×10 −4  cm 
     resistivity inside holes  13 : 2.4 Ωcm 
     an Ron of approximately 20 mΩ is obtained. In contrast, a conventional device having the same breakdown voltage, an Ron of approximately 28 mΩ is obtained, that is 40% higher than in the structure according to the invention. 
     FIG. 5 shows, similarly to FIG. 4, the dopant concentration (solid curve C) and the electric field E (dash-and-dot curve D) along line b—b in FIG.  3 . In this diagram it is possible to note the discontinuity of the electric field between silicon and the oxide: this is due to the higher dielectric constant of silicon compared to that of the oxide (approximately three times), so the electric field in the oxide is three times that in the silicon. It is also possible to note that in the drift layer  8  the slope of the electric field curve D increases near the oxide. As known, in a plane junction, the electric field in the depletion region decreases linearly if the dopant concentration is constant. In the present case, instead, the change in slope in the drift layer  8  is due to the presence of a transverse component of the electric field that increases near the oxide. The presence of a transverse component of the electric field also explains why the electric field in the oxide decreases even if the charge in the oxide is zero. 
     FIG. 6 clearly shows that, by properly dimensioning the size of the holes  13  between the buried oxide regions  60 , the equipotential lines are not distorted. Larger holes  13  increase the distortion of the equipotential lines: this causes an increase in the electric field at the corners of the buried oxide regions  60 , and a corresponding decrease in the breakdown voltage. 
     A first embodiment of a manufacturing process for obtaining the PN junction structure according to the invention will be now described making reference to FIGS. 7 to  14 . 
     Starting from an N− silicon layer  20  having for example a resistivity of 10 to 40 Ωcm, as shown in FIG. 7, an N+ layer  21  of, for example, 0.5 Ωcm, is formed, e.g. by means of epitaxial growth, on a first surface of layer  20  to obtain the structure shown in FIG.  8 . Layer  21  should preferably have a thickness equal to the thickness of the buried oxide regions which are to be formed, for example from 2 to 3 μm. 
     Then, a layer of silicon nitride is formed over the free surface of layer  21 . More specifically, before forming the silicon nitride layer, an oxide layer (“pad oxide”) is conventionally formed over the free surface of layer  21 . The silicon nitride layer is then selectively removed to obtain silicon nitride regions  22 , as shown in FIG.  9 . 
     A thermal oxidation is then performed (Local Oxidation or “LOCOS”) to form oxide regions  23  between the silicon nitride regions  22 , as shown in FIG.  10 . 
     After the thermal oxidation, the residual silicon nitride regions  22  are removed, and a planarization process is performed to obtain a planar surface  24 , as shown in FIG.  11 . 
     A conventional N+ substrate  25  (FIG. 12) having, for example, a resistivity of less than 25 Ωcm is bonded at one surface thereof to the planar surface  24 , for example by means of the conventional Silicon Direct Bonding (SDB) technique, so that the structure of FIG. 13 is obtained. 
     Then, layer  20  is reduced in thickness at the second surface  26  thereof, now the free surface, till the desired thickness is reached, for example 10 to 100 μm. The structure of FIG. 14 is thus obtained. Buried oxide regions  23  are provided at the interface between the N+ substrate  25  and the N− layer  20 . 
     From this point on, the process continues with the conventional steps of any known process, depending on the kind of device to be fabricated. For example, in the case of a power MOS as shown in FIG. 3, layer  20  will form the drift layer of the device, and body regions such as the body regions  9  of FIG. 3 will be formed in the drift layer  20  at the surface  26  thereof. 
     The process according to the embodiment previously described is suitable, in particular, when the buried oxide regions do not need to be very thick. When thicker buried oxide regions are desired, a more suitable manufacturing process is the one which will be now described. 
     As in the previous case, an N+ layer  27  is epitaxially grown over an N− layer  28  (FIG.  15 ). Even in this case, the thickness of the N+ layer  27  is approximately equal to the thickness of the buried oxide regions which have to be formed. 
     Then, groups  30  of rather closely spaced trenches  29  are formed in the N+ layer  27 . The trenches  29  reach the N− layer  28 , as shown in FIG.  16 . 
     An oxidation process is then carried out, so that in each trench, the oxide layers grown on the walls thereof completely fill the trench, and also the portions of silicon between contiguous trenches are converted into silicon dioxide so to form substantially continuous oxide regions  31 , as shown in FIG.  17 . 
     Then, the free surface  32  of layer  27  is planarized (FIG.  18 ), and an N+ substrate  33  is bonded to layer  27  at surface  32  by means of SDB technique (FIG.  19 ). 
     Similarly to the previous embodiment, after bonding to the N+substrate  33  the free surface  34  of layer  28  is submitted to a thickness reduction to attain the desired thickness (FIG.  20 ), and the process can follow in any of the conventional ways, depending on the device to be integrated. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.