Abstract:
The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application is a non-provisional patent application claiming priority to Netherlands Patent Application No. 2017206 filed Jul. 21, 2016, the contents of which are hereby incorporated by reference. 
       TECHNICAL FIELD 
       [0002]    The present disclosure relates to a radio frequency (RF) power amplifier package. It further relates to a mobile telecommunications base station comprising such an RF power amplifier package, and to an integrated passive die suitable for such an RF power amplifier package. 
       BACKGROUND 
       [0003]    RF power amplifier packages may comprise a package and a semiconductor die, and the die may be arranged inside the package and provided with an RF power transistor. The RF power transistor may have an output capacitance and may be configured to amplify signals at an operational frequency. An impedance network may be arranged inside the package for providing impedance matching and/or filtering. These packages may be used in base stations for the mobile communications market. 
         [0004]    The evolution of the mobile communications market is essentially driven by a continuously increasing amount of data and transmission speed, resulting in a need for an increasingly larger instantaneous signal bandwidth. To linearly amplify wide band signals and minimize the memory effects, it may be useful to terminate the second order intermodulation distortion (IMD) products occurring at relatively low frequencies with very low impedances. If the impedance seen by an RF power transistor at these frequencies is too high, the amplitude of the undesired signal components may increase, and the biasing of the transistor may be affected by feedback of the low-frequency IMD products into the biasing circuitry. 
         [0005]    Another aspect of RF power amplifiers is the ability to deliver the output signal at the desired power level. To that end, it may be useful for the RF power transistor to be appropriately impedance matched. In particular, the effective load seen by the RF power transistor should only have a small reactive part. In practice however, most RF power transistors may have a considerable output capacitance. As an example, a laterally diffused metal-oxide-semiconductor (LDMOS) transistor, configured to provide output powers in the range of 150 Watts, may have a drain-source capacitance of approximately 50 pF. In the frequency band of interest, which in the mobile base station market ranges from 600 MHz to 3.5 GHz and more, this capacitance strongly influences the impedance seen at the drain of the LDMOS. 
       SUMMARY OF THE DISCLOSURE 
       [0006]      FIG. 1A  illustrates a circuit topology that addresses the abovementioned influence of the output capacitance. This capacitance is denoted by Cds and is present between the drain (d) and source (s) of the FET. In  FIG. 1A , a series resonance circuit formed by L 1  and C 1  is connected to the drain of the FET. Zload models the load that is presented to the FET, and Lfeed models the feed inductance of the biasing circuit. 
         [0007]    Due to its relatively large capacitance value, C 1  may be configured to act as a ground for signals at the RF operational frequency of the FET. L 1  may be chosen such that it will resonate with Cds at or close to the operational frequency. This may allow the reactive part of the impedance seen by the FET to be sufficiently small at the operational frequency. However, at the same time, C 1  may resonate with the feed inductance Lfeed of the biasing circuitry at low frequencies. This may introduce a peak in the impedance seen at the drain of the FET, as illustrated in  FIG. 1B . 
         [0008]    To mitigate this problem, a different topology may be used, which is illustrated in  FIG. 2A . This topology differs from the topology in  FIG. 1A  in that a further inductance L 2  and a further capacitance C 2  have been included. C 2  has a terminal electrically connected to L 2  and another terminal electrically connected to ground. 
         [0009]    Similar to  FIG. 1A , C 2  may be very large, even substantially larger than C 1 , and may act as a ground at RF and lower frequencies. For simplicity, the same component values for L 1 , Cds, and C 1  may be used in the topologies in  FIGS. 1A and 2A . 
         [0010]    Similar to  FIG. 1B , the circuit in  FIG. 2A  may show a first resonance occurring at a relatively low first resonance frequency related to the resonance between C 2  and Lfeed, albeit at a lower frequency due to the influence of L 2  and C 1 . However, a second resonance may occur at an intermediate second resonance frequency related to the resonance of L 2  and C 1 . L 2  and Clform a parallel resonance circuit that will display a transition between a high positive and high negative reactive part near the resonance frequency of L 2  and C 1 . This reactive part will produce the second resonance shown in  FIG. 2B . 
         [0011]    As can be seen by comparing  FIG. 1B  and  FIG. 2B , the first resonance frequency may be shifted to lower frequencies. This, in combination with the second resonance frequency, may allow a better control of the impedance at the frequencies that are associated with the second order modulation. 
         [0012]    To further improve the abovementioned impedance behavior, damping can be introduced. For example, a damping resistor can be placed in series with L 2 . This resistance may dampen the resonance at the first and second resonance frequencies. At the operational frequency, the combination of L 2  and C 1  may inhibit RF signals from being dissipated in the resistance, such that the impact of the resistance at the operational frequency may be minimal. 
         [0013]    A practical implementation of C 2  will include some energy losses. The quality factor of a parallel resonance circuit may generally decrease when its capacitance is increased. This may, in turn, reduce the peak height of the impedance at the first resonance frequency. Hence, to reduce the IMD products, C 2  may be chosen to be as large as possible. 
         [0014]    The first capacitance C 1  may also be arranged inside the package. As this capacitance may have a non-negligible influence on the RF behavior, it may be desirable for the losses of this capacitor to also be minimized. 
         [0015]    The available space inside the package may be limited. Consequently, increasing C 2  may result in less space being available for C 1 . This may be particularly true when C 1  and C 2  are integrated on the same die. For instance, a highly doped substrate of the die may form one of the electrodes, and the electrode may be connected to the flange of the package that acts as ground. Hence, when C 2  is increased, less space may be available for grounding C 1 , which in turn may increase its losses. Therefore, in some approaches, a trade off may be found between increasing control of the impedance at the second-order IMD frequencies and the overall efficiency of the power amplifier. 
         [0016]    Embodiments of the present disclosure may provide a circuit topology in which the abovementioned trade-off can be improved. 
         [0017]    This may be achieved using the topology as claimed in claim  1 , which is characterized in that the second terminal of the first capacitive element is electrically connected to the second capacitive element. For example, the second capacitive element may have a second terminal connected to ground and a first terminal connected to the second terminal of the first capacitive element and to a second terminal of the second inductor. Contrary to the topology of  FIG. 2A , the first capacitive element is not directly connected to ground but is connected to the second capacitive element. 
         [0018]    As the capacitance of the second capacitive element may be much larger than the capacitance of the first capacitive element, the second capacitive element may have larger electrodes. Furthermore, the second capacitive element may act as a ground at those frequencies for which the losses of the first capacitive element are relevant. By arranging the first capacitive element in series with the second capacitive element, the first capacitive element can use the relatively large electrode of the second capacitive element as an efficient ground connection, thereby avoiding the increased resistance observed in other approaches where the capacitance of the second capacitive element is increased at the expense of the grounding of the first capacitive element. 
         [0019]    The first inductive element can be configured to resonate with the output capacitance at or close to the operational frequency. Furthermore, the RF power transistor can be configured to be fed using a feed inductance, and the second capacitive element can be configured to resonate with the feed inductance at a first resonance frequency that is substantially smaller than the operational frequency. The second inductive element can be configured to resonate with the first capacitive element at a second resonance frequency. Here, the first resonance frequency may be substantially smaller than the second resonance frequency, and the second resonance frequency may be substantially smaller than the operational frequency. 
         [0020]    The various resonance frequencies mentioned above may differ, to a small extent, from the resonance frequencies associated with the impedance seen at the output of the RF power transistor. For example, the impedance seen at the output of the RF power transistor may comprise a parallel contribution of the output capacitance, the impedance of impedance network, and the impedance associated with a matching network connected to the RF power transistor. A resonance in the overall impedance seen at the output of the RF power transistor can be achieved when the impedance of the impedance network forms an open together with the other impedance contributions. As the impedance of the impedance network near a parallel resonance frequency varies strongly between a large positive value and a large negative value, such a match can be found for a frequency close to the parallel resonance frequency. 
         [0021]    The first and/or second inductive element may comprise an integrated inductor and/or a bond wire. An integrated inductor may comprise a spiral conductor and/or a transmission line realized on a substrate, such as a semiconductor die. This die may correspond to the die on which the RF power transistor is located. Alternatively, a separate die may be used on which at least one or all of the abovementioned inductive and capacitive elements are integrated. 
         [0022]    The resonance circuit may comprise a resistive element for damping the first and second resonances. This resistive element may be arranged in series with the second inductive element or can be integrated therewith. By appropriately choosing the inductance and capacitance values, the RF performance at the operational frequency may be unaffected or hardly affected by this resistive element. 
         [0023]    The first and/or second capacitive element may comprise an integrated capacitor. Such a capacitor may be realized on a substrate, such as the first semiconductor die. Alternatively, the first and second capacitive elements may be integrated on a second die, such as a semiconductor die, and the second die may also be arranged inside the package. The package may comprise a flange and an output lead, wherein the first and/or second die is mounted to the flange, perhaps using a die-bonding technique. 
         [0024]    When the package is mounted in a final product, such as on a printed circuit board of a base station amplifier, the flange may be connected to ground. By connecting the dies on the flange, a ground connection can be obtained. In some cases, the first and/or second die may comprise a highly doped substrate allowing a low resistance path through the substrate. Alternatively, vias that extend through the substrate may be used to achieve a ground connection between the upper region of the dies and the bottom region that is connected, in a low-ohmic manner, to the flange. 
         [0025]    Examples of integrated capacitors include interdigitated capacitors, fringe capacitors, deep trench capacitors, and metal-insulator-metal capacitors, although the present disclosure does not exclude other types of capacitors. In an example embodiment, the second capacitive element may comprise a deep trench capacitor, and the first capacitive element may comprise a metal-insulator-metal capacitor. 
         [0026]    The first capacitive element may comprise a first and a second electrode having a first dielectric arranged therebetween. Furthermore, the second capacitive element may comprise a first and a second electrode having a second dielectric arranged therebetween, wherein the first electrode of the first capacitive element is electrically connected to the first inductive element, and wherein the second electrode of the first capacitive element is electrically connected to the first electrode of the second capacitive element. Here, the second electrode of the second capacitive element can be electrically connected to ground. As the second capacitive element may be substantially larger than the first capacitive element, in such a manner that at the operational frequency the second capacitive element acts as ground, the first capacitive element can use the relatively large first electrode of the second capacitive element as an efficient ground plane. 
         [0027]    The first and second dies may be elongated in a first direction, wherein the deep trench capacitor may comprise a plurality of trenches extending in the first die, the second dielectric may be arranged inside the trenches, a top electrode may be arranged over the second dielectric, and a metal contact layer may be arranged on the top electrode, and wherein the metal contact layer may comprise a plurality of slots along the first direction. The second capacitive element may extend a first distance in the first direction, and the slots may extend along a second distance in the first direction, wherein the second distance may be substantially equal to the first distance. 
         [0028]    When using a second die, which may be generally located in between the first die and the output lead of the package, return currents may flow through the relatively thin metal contact layer of the deep trench capacitor instead of the flange of the package or the semiconductor substrate. Such current may introduce losses that deteriorate RF performance. By arranging slots that extend in a direction perpendicular to the direction of the RF return current, the RF current can be forced to flow through the flange, which may present a much smaller resistance to the RF return current. 
         [0029]    As described above, a resistive element can be used in the resonance unit to dampen the first and second resonances. This resistive element may be integrated on the second die, for example, in the form of a thin film resistor. 
         [0030]    The first semiconductor die may comprise an output bond pad assembly, which may be bar-shaped, that is electrically connected to the output. Furthermore, the second die may comprise a first bond pad assembly that is electrically connected to the first capacitive element, and the RF power amplifier package may comprise a first plurality of bond wires that electrically connect the output bond pad assembly to the first bond pad assembly. In this case, the first plurality of bond wires may substantially form the first inductive element, although the present disclosure does not exclude embodiments in which these bond wires cooperate with an integrated inductor, arranged on the first and/or second die, to form the first inductive element. 
         [0031]    The RF power amplifier package may comprise a second plurality of bond wires that electrically connect the output bond pad assembly to the output lead. Here, the second plurality of bond wires may form a series inductance between the output of the RF power transistor and the output lead. This inductance may be part of an impedance matching network that is at least partially arranged inside the package. It may also be used as part of an impedance inverter for an integrated Doherty amplifier. In such a case, the RF power amplifier package may comprise at least one other RF power transistor. The plurality of RF power transistors may be biased differently, such that one transistor acts as a main amplifying stage and the other transistor(s) as a peak amplifying stage. Depending on the topology used, the second plurality of bond wires may be used to connect the main or peak amplifying stage to the output lead. It will be understood that other arrangements of Doherty amplifiers that include at least a portion of the impedance inverters and/or signal combiners located inside the package are possible and contemplated herein. 
         [0032]    The RF power amplifier package may further comprise a third inductive element and a third capacitive element arranged in series between the output lead and one of the flange, the second die, and/or the second capacitive element. This series combination can be used to perform in-package matching. The third capacitive element may in these cases, at least at the operational frequency, be effectively electrically connected to ground. The flange or the second capacitive element can be used for this purpose. Alternatively, if the second die comprises a highly doped substrate, an electrical connection between the second capacitive element and this substrate could be realized to achieve the ground connection. 
         [0033]    The third capacitive element may be integrated on the second die, and the second die may further comprise a second bond pad assembly electrically connected to a terminal of the third capacitive element. In this case, the RF power amplifier package may further comprise a third plurality of bond wires extending from the second bond pad assembly to the output lead. This third plurality of bond wires may at least partially form the third inductive element. Again, the bond wires may be combined with integrated inductors arranged on the second die. The other terminal of the third capacitive element can be electrically connected to one of the flange, the second die, and the second capacitive element. 
         [0034]    Alternatively, the second die may comprise a second bond pad assembly, and an integrated third capacitive element having one terminal electrically connected to the second bond pad assembly and another terminal to one of the flange, the second die, and the second capacitive element. The RF power amplifier package may comprise a third plurality of bond wires electrically connecting the second bond pad assembly to the output lead. The RF power amplifier package may further comprise a second plurality of bond wires electrically connecting the second bond pad assembly and the output bond pad assembly. 
         [0035]    The third inductive element and the third capacitive element may be configured for providing an impedance match at the operational frequency. The third capacitive element may comprise a deep trench or a metal-insulator-metal capacitor. 
         [0036]    The package may further comprise a bias lead and a fourth plurality of bond wires extending from the bias lead to the first bond pad assembly. This may eliminate the need for Lfeed and may provide significant space reduction on the external printed circuit board. 
         [0037]    The first resonance frequency may lie in the range of 5 MHz to 20 MHz, the second resonance frequency in the range of 300 MHz to 650 MHz, and the operational frequency in the range of 800 MHz to 3.5 GHz and above. 
         [0038]    The first semiconductor die may comprise a Silicon die or a suitable substrate, such as Silicon, Silicon Carbide, or Sapphire, having Gallium Nitride grown epitaxially thereon. The RF power transistor may comprise at least one of a laterally diffused metal-oxide-semiconductor transistor or a field-effect transistor. 
         [0039]    According to a further aspect, the disclosure further provides an integrated passive die that is suitable for an RF power amplifier package as above, wherein the integrated passive die comprises the second die as described above. 
         [0040]    According to an even further aspect, the disclosure provides a mobile telecommunications base station comprising the RF power amplifier package as described above. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0041]      FIG. 1A  illustrates a circuit topology for an RF power amplifier, according to an example embodiment. 
           [0042]      FIG. 1B  illustrates an impedance as a function of frequency of the circuit topology depicted in  FIG. 1A , according to an example embodiment. 
           [0043]      FIG. 2A  illustrates a circuit topology for an RF power amplifier, according to an example embodiment. 
           [0044]      FIG. 2B  illustrates an impedance as a function of frequency of the circuit topology depicted in  FIG. 2A , according to an example embodiment. 
           [0045]      FIG. 3A  illustrates a circuit topology for an RF power amplifier, according to an example embodiment. 
           [0046]      FIG. 3B  illustrates an impedance as a function of frequency of the circuit topology depicted in  FIG. 3A , according to an example embodiment. 
           [0047]      FIG. 4A  illustrates a circuit topology for an RF power amplifier, according to an example embodiment. 
           [0048]      FIG. 4B  illustrates a circuit topology for an RF power amplifier, according to an example embodiment. 
           [0049]      FIG. 4C  illustrates a circuit topology for an RF power amplifier, according to an example embodiment. 
           [0050]      FIG. 4D  illustrates a circuit topology for an RF power amplifier, according to an example embodiment. 
           [0051]      FIG. 5A  illustrates a circuit topology for an RF power amplifier, according to an example embodiment 
           [0052]      FIG. 5B  illustrates an arrangement of an RF power amplifier package, according to an example embodiment. 
           [0053]      FIG. 6A  illustrates a semiconductor die for use in the RF power amplifier package depicted in  FIG. 5B , according to an example embodiment. 
           [0054]      FIG. 6B  illustrates a semiconductor die for use in the RF power amplifier package depicted in  FIG. 5B , according to an example embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0055]      FIG. 3A  illustrates a general topology in accordance with the present disclosure. 
         [0056]    When comparing this topology with the topology in  FIG. 2A , it can be seen that C 1  is no longer directly connected to ground but is instead connected to C 2 . This latter capacitor, being substantially larger than C 1 , may act as a ground at the operational frequency of the RF power transistor. In addition, a resistive element R is arranged in series with L 2 . 
         [0057]    Similar to the topology of  FIG. 2A , a first resonance can be observed in the impedance seen looking away from the FET illustrated in  FIG. 3B , which can be attributed to the parallel resonance of C 2  and Lfeed. At this resonance frequency, the impedance of the series connection of L 2  and R may be substantially smaller than the impedance of C 1 . As such, the effective capacitance that is arranged in parallel to Lfeed may be roughly equal to C 2 . Moreover, the currents at this frequency may flow through R, causing damping of the resonance peak in the impedance. 
         [0058]    A second resonance peak can be observed in  FIG. 3B , which can be attributed to the parallel resonance of C 1  and L 2 , similar to the resonance in the topology of  FIG. 2A . Also, in this case, current may flow through R, causing damping of the resonance peak in the impedance. 
         [0059]    At the operational frequency, L 2  may substantially block the RF current, causing the larger part thereof to flow through C 1  and C 2 . Consequently, the impact of the ohmic losses in R may be negligible at these frequencies. Moreover, at these frequencies, the effective capacitance to ground of the resonance unit may be substantially equal to C 1 , as C 1  and C 2  are arranged in series. L 1  and C 1  may be chosen such that, at or close the operational frequency, the resonance circuit acts as an inductance having a value substantially equal to L 1 . This effective inductance may resonate with Cds to mitigate the impact of Cds at the operational frequency. At this frequency, the RF power transistor may see only the desired impedance realized by the combination of the matching network, which is at least partially arranged outside the package, and the external load. 
         [0060]    The description above provides a description of the functionality of the components Cds, L 1 , L 2 , R, C 1 , and C 2 . It is understood that the values for these components may depend on, inter alia, the desired operational frequency, the size of the RF power transistor and the type of this transistor, the desired impedance behavior of the impedance at the second order IMD frequencies, and the desired bandwidth of the RF power amplifier made using the RF power amplifier package. The disclosure is therefore not limited to a particular range of values of these components. 
         [0061]      FIGS. 4A-4D  show further topologies in accordance with the present disclosure. Here, an additional capacitor C 4  can be identified that models the parasitic capacitance seen at the output lead of the package. Moreover, component C 3  and L 3  are added to perform an impedance matching inside the package at the operational frequency, for example to perform a downward impedance transformation for transforming the impedance at the output lead when looking at the external load to a lower value seen by the RF power transistor. 
         [0062]      FIGS. 4A-4D  differ in how C 3  and L 3  are connected. Depending on the desired functionality of L 3 , different implementations can be identified. For example, if L 3  is intended solely for impedance matching, the following matching stages can be identified at the operational frequency: 
         [0063]    For the  FIGS. 4A and 4B  topology, a first stage may comprise a series inductance L 4  and a shunt capacitance equal to C 3 , where C 4  may be much smaller than C 3 , and C 3  may be much smaller than C 2 . 
         [0064]    For the  FIGS. 4C and 4D  topology, a first stage may comprise a series inductance L 3  and a shunt capacitance equal to C 3 , and a second stage may comprise a series inductance L 4  and a shunt capacitor equal to C 4 . 
         [0065]    Alternatively, L 3  can be part of an impedance inverter, for instance when the RF power amplifier package is to be used in a Doherty amplifier, wherein the RF power amplifier package comprises an RF power transistor acting as a main amplifying stage and an RF power transistor acting as a peak amplifying stage. Referring to  FIG. 4A , for example, an equivalent pi-network can be formed by the resonance network, Cds, L 3 , C 3 , and L 4 . These components may perform a 90 degrees phase shift, or multiples thereof, at the operational frequency. In such applications, the resonance unit may be designed such that, at the operational frequency, a residual capacitance exists to form the first shunt capacitor of the pi-network for the impedance inverter. 
         [0066]    In  FIGS. 4A and 4C , C 3  is grounded directly. In practical implementations, C 3  may be realized as a discrete capacitor that is mounted to the flange separately from the first and second dies. Alternatively, C 3  may be integrated on the first or second die. In this latter case, C 3  can be connected to the conducting substrate, which, in turn, can be connected to the flange. When C 3  is integrated in the second die, it can be connected to C 2 , as illustrated in  FIGS. 4B and 4D . 
         [0067]      FIG. 5A  illustrates an embodiment according to the present disclosure, wherein the feed line, modeled by Lfeed, is integrated in the package and connected to the second die, and more specifically to the first capacitor. This may allow for substantial reduction of the total size of the power amplifier and ease of use of the RF power transistor. 
         [0068]      FIG. 5B  illustrates an implementation of the embodiment of  FIG. 5A .  FIG. 5B  shows a package comprising a flange  1 , an output lead  2 , and a bias lead  3 . A pair of semiconductor dies  4  are mounted on the flange  1 . On these semiconductor dies  4 , RF power transistors  5  are arranged, which are only schematically illustrated. In this example, the RF power transistors  5  are formed as LDMOS transistors arranged on a highly doped substrate. 
         [0069]    The gate input of one of the RF transistors  5  is connected to a bar-shaped bond pad assembly  6 . A plurality of bond wires  7  are used to connect to the gate of the RF transistor  5 . 
         [0070]    The drain output of the RF transistor  5  is connected to a bar-shaped bond pad assembly  8 . A plurality of bond wires  9 , forming L 4 , connect the drain output to output lead  2 . A second plurality of bond wires  10 , forming L 1 , connect the drain output to a U-shaped bond pad assembly  11  that is arranged on a second die  18 . This assembly is electrically connected to the common point of L 2  and C 1 . A further plurality of bond wires  12 , partially forming Lfeed, connects bias lead  3  to bond pad assembly  11 . Bond wires  12 ′ relay the bias to the other RF power transistor  5 . 
         [0071]    Bond wires  13 , forming L 3 , connect output lead  2  to a bar-shaped bond pad assembly  14  that is electrically connected to a terminal of C 3 . The other terminal of C 3  is connected to the top electrode of C 2  (not illustrated). Bond wires  15 , forming L 2 , connect bond pad assembly  11  to a bond pad  16  that is electrically connected to a thin film resistor R that is located at a buried position  17 . 
         [0072]    Die  18  may comprise a highly doped Silicon substrate on which C 2  is distributed as a deep trench capacitor. The top electrode of C 2  is connected to the bottom electrode of C 1 . The other electrode of C 2  is formed by the highly doped substrate. The top electrode of C 1  is connected to bond pad assembly  11 . 
         [0073]    The embodiment in  FIG. 5B  illustrates two separate dies  4 ,  18  on which the various components can be realized. However, the present disclosure does not exclude embodiments where only a single die is used on which both the active and passive components are integrated. 
         [0074]    As can be seen in  FIG. 5B , bond wires  9  carry the output current to output lead  2  across die  18 . A return current may be associated with this current. This current is schematically illustrated in  FIG. 6A .  FIG. 6A  illustrates the flange  1  on which the die  18  is arranged.  FIG. 6A  also shows the top electrode of C 2 , which, in this example, is formed as a 1 micrometer thick metal layer  19 . The resistance associated with the metal layer  19  may be much higher than the resistance associated with flange  1 . In some scenarios, unwanted losses may be introduced at the operational frequency. The embodiment shown in  FIG. 6B  may address such scenarios. 
         [0075]    As shown in  FIG. 6B , to direct the return current, slots  20  can be arranged in the metal layer  19  that extend perpendicular to the flow of the return current in  FIG. 6A . Generally, C 2  may be distributed over the entire die  18 , thereby having an elongated structure extending in a first direction. Slots  20  may be arranged along this first direction and may extend over substantially the entire length of the metal layer  19 . Using slots  20 , the return current may be forced to flow through the flange  1 , thereby reducing the losses at the operational frequency. 
         [0076]    Although the present disclosure has been described using detailed embodiments thereof, it is understood that the present disclosure is not limited thereto, but that various modifications can be made to these embodiments without departing from the scope of the disclosure which is defined by the appended claims.