Abstract:
A memory cell of the one-time-programmable type is programmed by application of a programming voltage having a value sufficient to obtain a breakdown of a dielectric of a capacitor within the cell. A programming circuit generates the programming voltage as a variable voltage that varies as a function of a temperature (T) of the cell. In particular, the programming voltage varies based on a variation law decreasing as a function of the temperature.

Description:
PRIORITY CLAIM 
       [0001]    This application claims priority to French Application for Patent No. 1500786 filed Apr. 15, 2015, the disclosure of which is incorporated by reference. 
       TECHNICAL FIELD 
       [0002]    Various embodiments of the invention and their implementation relate to the non-volatile memory cells of the one-time-programmable type, known by those skilled in the art under the acronym OTP (One Time Programmable) and, more particularly, the programming of such memory cells. 
       BACKGROUND 
       [0003]    Conventionally, a memory cell of the one-time-programmable type operates as a fuse or an anti-fuse whose state is modified in an irreversible manner, for example by breakdown of a dielectric, by applying a high programming voltage to the memory cell, in such a manner that the memory cell goes from a non-conducting state to a conducting state, which amounts to changing its resistance. 
         [0004]    For example, a memory cell of the one-time-programmable type in the form of an anti-fuse generally comprises a capacitor having a layer of dielectric between its two electrodes. This capacitor may be formed by a MOS transistor whose source and drain are connected. Depending on the applied programming voltage and the programming time, a conducting channel can be obtained which passes completely through the layer of dielectric of the capacitor, a phenomenon known by those skilled in the art under the term “Hard Breakdown”. 
         [0005]    As a result, this conducting channel changes definitively the state of the capacitor which goes from non-conducting to conducting, in other words this structure defines a resistor of the memory cell whose resistance is modified by programming. The logical value of the memory cell, for example initially equal to “0”, then becomes “1” when the conducting channel created passes completely through the layer of dielectric of the capacitor. 
         [0006]    In order to minimize the power consumption and to maximize the programming efficiency, the programming voltage is applied within a very short lapse of time of the order of tens of nanoseconds and the value of the programming electric field may go as high as 35 MV/cm. 
         [0007]    However, the applied programming voltage is generally chosen for a worst case scenario and remains constant during the whole programming process irrespective of the temperature of the integrated circuit containing the memory cells. The applied programming voltage is therefore often higher than that needed to break down the layer of dielectric of the capacitor within a given programming time. 
         [0008]    This consequently results in a high leakage current once the conducting channel is under formation then completely created during the programming operation. 
         [0009]    Furthermore, circuits around the memory cells that need to be preserved are de facto subjected to a high stress during the application of the programming voltage which risks damaging them. 
         [0010]    This phenomenon is even more critical for high densities of memory cells which is the case for advanced CMOS technologies. 
       SUMMARY 
       [0011]    According to one embodiment and its implementation, an improvement in the efficiency of programming of memory cells of the OTP type is provided, while at the same time limiting as far as possible the stress suffered by components close to these memory cells. 
         [0012]    In this respect, the inventors have observed, notably by measurement, that for a given programming time, the programming voltage to be applied to a memory cell of the OTP type in order to break down its dielectric follows a law of decreasing variation with temperature owing to the thermal activation. 
         [0013]    More precisely, it has been observed that this variation law could be advantageously approximated by a decreasing affine voltage-temperature law. 
         [0014]    The inventors have furthermore observed that such an affine law formed a good approximation to the 1 st  order of a model of time dependency of the breakdown of a dielectric, commonly known by those skilled in the art under the acronym TDDB (for Time Dependent Dielectric Breakdown) but which needs to be adapted for high-voltage applications. 
         [0015]    Thus, according to one aspect, a method is provided for programming of at least one memory cell of the one-time-programmable type comprising a capacitor, comprising the generation of a programming voltage and the application of this programming voltage to the at least one memory cell in such a manner as to obtain a breakdown of the dielectric of the capacitor. 
         [0016]    According to a general feature of this aspect, the method comprises a variation of the programming voltage as a function of the temperature of the at least one memory cell based on a decreasing variation law as a function of the temperature. 
         [0017]    The variation law may be a decreasing affine voltage-temperature law which is, for example, an approximation of a relationship between a voltage applied to the dielectric, the temperature and the time after which the breakdown of the dielectric occurs, the relationship being taken from a model of time dependency of the breakdown of a dielectric. 
         [0018]    This variation law may be advantageously obtained using a band-gap voltage source generating a band-gap voltage and, internally, a current proportional to the absolute temperature of the memory cell. 
         [0019]    According to another aspect, an integrated circuit is provided comprising an electronic device designed to program at least one memory cell of the one-time-programmable type comprising a capacitor, comprising a module configured for generating a programming voltage designed to break down the dielectric of the capacitor. 
         [0020]    According to a general feature of this other aspect, the module is configured for generating a programming voltage varying with the temperature of the memory cell according to a decreasing variation law as a function of the temperature. 
         [0021]    The module may advantageously be configured for generating the programming voltage varying according to the variation law which is an approximation of a relationship between a voltage applied to the dielectric, the temperature and the time after which the breakdown of the dielectric occurs, the relationship being taken from a model of time dependency of the breakdown of a dielectric. 
         [0022]    Furthermore, the module is, for example, configured for generating the programming voltage varying according to the variation law which is a decreasing affine voltage-temperature law. 
         [0023]    According to one embodiment, the module comprises generation means configured for generating an intermediate reference voltage varying according to the variation law, and a charge pump configured for generating the programming voltage starting from the intermediate reference voltage. 
         [0024]    Since the intermediate reference voltage follows the variation law, the programming high voltage generated by the charge pump follows the same variation law. 
         [0025]    One particularly advantageous way of generating a decreasing affine voltage-temperature variation law is, as indicated hereinbefore, to use a band-gap voltage source which allows a band-gap voltage to be delivered that is constant with respect to temperature (which will allow the constant coefficient of the affine law to be obtained) and which furthermore contains an internal core generating a current proportional to temperature (which will allow the coefficient of proportionality of the affine law to be obtained after processing). 
         [0026]    Thus, according to one embodiment, the generation means comprise: a band-gap voltage source configured for generating a band-gap voltage and a first current proportional to the absolute temperature of the memory cell, an output stage connected to the band-gap voltage source and configured for generating a first elementary current independent of the absolute temperature from the band-gap voltage and a second elementary current proportional to the absolute temperature starting from the first current, subtraction means configured for subtracting the second elementary current from the first elementary current so as to obtain a second current inversely proportional to the absolute temperature, and means for transforming the second current into the intermediate reference voltage. 
         [0027]    The integrated circuit can advantageously incorporate a memory plane of cells of the one-time-programmable type and decoding means for selectively applying the programming voltage to at least one cell of the memory plane. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    Other advantages and features of the invention will become apparent upon examining the detailed description of non-limiting embodiments and their implementation, and the appended drawing in which: 
           [0029]      FIGS. 1 to 6  relate to embodiments and their implementation. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    In  FIG. 1 , an integrated circuit IC is illustrated very schematically comprising a non-volatile memory device of the one-time-programmable type MPU. 
         [0031]    This memory device MPU comprises a matrix memory plane PM comprising N rows and M columns of memory cells CEL. 
         [0032]    Each memory cell is connected to a word-line WL and to a bit-line BL. 
         [0033]    As shown schematically on the right-hand side of  FIG. 1 , each cell comprises a capacitor C having an electrode E 2  that is designed to be connected to ground, and another electrode E 1  that is designed to receive a programming voltage V G  for a given programming time in such a manner as to break down the dielectric DL. 
         [0034]    Of course, as is well known to those skilled in the art, each memory cell is in fact accessible via an access transistor, typically an NMOS access transistor whose gate is connected to the word-line WL, whose drain is connected to the electrode E 2  and whose source is connected to the bit-line BL. However, for the sake of simplification, this access transistor is not shown on the right-hand side of  FIG. 1 . 
         [0035]    The decoding of the word-lines WL is carried out by a row decoder RDC and the decoding of the bit-lines BL is carried out by a column decoder CDC. 
         [0036]    The matrix memory plane PM is furthermore connected to a programming voltage source STP which supplies the programming voltage V G  for the memory cells CEL. A charge pump is often provided within the programming voltage source STP in order to obtain a high programming voltage V G . 
         [0037]    Depending on the desired granularity, the memory plane may be programmed by bit, or else by word (several cells of the same row and situated over several bit-line columns form a digital word), or alternatively by “memory page” (several memory words simultaneously). 
         [0038]    As illustrated in  FIG. 2 , for a given programming time T BD  and a given surface area of the capacitor, the programming voltage V G  decreases as a function of the temperature of the memory cell. Three variation curves CV 1 , CV 2 , CV 3  are shown in this figure for three different values of the programming time T BD  (10 −5  s, 10 −6  s, 10 −7  s). Although these curves were able to be obtained by physical measurements on a memory cell, it can be seen that these curves also correspond to simulation results associated with a model of time dependency of the breakdown of a dielectric adapted to high voltages. 
         [0039]    More precisely, according to the model, the programming voltage VG to be applied for the time T BD  to break down the dielectric varies as a function of temperature according to the variation law: 
         [0000]    
       
         
           
             
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         [0040]    in which: 
         [0041]    lnA1 is a constant representing the ordinate at the origin in the logarithmic coordinate system; 
         [0042]    β is a variability parameter (slope of the Weibull distribution of the times to the breakdown, called form parameter); 
         [0043]    V ref  the reference voltage at which this variation law is calibrated; 
         [0044]    S is the gate surface area of an MOS capacitor; 
         [0045]    S ref  is the reference surface area at which this variation law has been calibrated; 
         [0046]    T ref  is the reference temperature at which the variation law has been calibrated; 
         [0047]    k is the Boltzmann&#39;s constant; and 
         [0048]    a, b, A, B and K are constants extracted by linear regression. 
         [0049]    By an approximation of the 1 st  order, this variation law may be considered as a decreasing affine voltage-temperature law (V G =−C1T+C2). 
         [0050]    With regard to the above, a programming voltage source STP will now be described in order to take into account this decreasing affine variation law of the programming voltage as a function of the temperature. 
         [0051]      FIG. 3  illustrates schematically the structure of the programming voltage source STP. It comprises, for example, generation means MG configured for generating an intermediate reference voltage V refi  which varies according to the decreasing affine variation law, and a charge pump PC configured for generating the programming voltage V G  starting from the intermediate reference voltage V refi . 
         [0052]    As illustrated in  FIG. 4 , the generation means MG advantageously comprise a band-gap voltage source STBI configured for generating a band-gap voltage V BI  at the output and, internally, a first current I 2  proportional to the absolute temperature of the memory cell. 
         [0053]    The band-gap voltage source STBI illustrated in  FIG. 4  comprises for example a conventional core circuit CR with a reference band-gap voltage arranged so that, when the voltages V 1  and V 2  at its two terminals BE 1  and BE 2  are equalized, one of its branches has the internal current I 2  flowing through it which is proportional to the absolute temperature, well known by those skilled in the art under the acronym I ptat  (“Proportional To Absolute Temperature”). 
         [0054]    The core circuit CR here comprises a first NPN bipolar transistor, referenced TB 1 , configured as a diode and connected in series between the input terminal BE 1  and a terminal BM connected to a reference voltage, here ground. 
         [0055]    The core circuit CR further comprises a second NPN bipolar transistor, referenced TB 2 , configured as a diode and connected in series with a first resistor R 1  between the input terminal BE 2  and the terminal BM connected to ground. 
         [0056]    The input terminals BE 1  and BE 2  are respectively connected to the output terminal BS CR  via a second resistor R 2 . 
         [0057]    The band-gap voltage source STBI furthermore comprises an operational amplifier OP 1  having its negative and positive inputs respectively connected to the terminals BE 1  and BE 2  in order to equalize the voltages V 1  and V 2 , and its output connected to the output terminal BS CR  through transistor TM 1 . 
         [0058]    When the voltages V 1  and V 2  are equalized by means of the operational amplifier OP 1 , as is well known by those skilled in the art, the internal current I 2  flowing through the resistor R 1  is proportional to the absolute temperature and equal to kTln(Q 1 /Q 2 )/qR 1 , where k represents Boltzmann&#39;s constant, T the absolute temperature, q the charge of an electron, Q 1  the size of the bipolar transistor TB 1 , Q 2  the size of the bipolar transistor TB 2 , and ln the Napierian logarithmic function. 
         [0059]    It should be noted that the size Q 1  and the size Q 2  are different and their ratio Q 1 /Q 2  is chosen in such a manner that the density of current flowing through the transistor TB 1  is different from the density of current flowing through the transistor TB 2 , whereas the current I 1  flowing through the transistor TB 1  is equal to the current I 2  flowing through the transistor TB 2 . It would of course be equally possible to use a transistor TB 2  and x transistors TB 1  in parallel (where x is an integer), all of the same size as that of the transistor TB 2 . 
         [0060]    The output voltage V BI  is equal to the sum of the voltage on the resistor R 2  and the base-emitter voltage V BE1  of the transistor TB 1 . As the current I 1  is equal to the current I 2 , the voltage on the resistor R 2  is equal to R 2 *ΔV BE /R 1  which is proportional to the temperature. As regards the voltage V BEI , it contains a constant term equal to the band-gap voltage (around 1.205 volts) and another term inversely proportional to the temperature. 
         [0061]    As a consequence, by correctly choosing the ratio R 2 /R 1 , the term dependent on the temperature of the voltage V BI  can be cancelled. The voltage V BI  is equal to the band-gap voltage 1.205 volts and considered as independent of the absolute temperature. 
         [0062]    As illustrated in  FIG. 4 , the generation means MG may further comprise an output stage ES connected to the band-gap voltage source STBI via the output terminal BS CR . 
         [0063]    This stage ES is configured for generating a first elementary current I e1  independent of the absolute temperature starting from the band-gap voltage V BI  and a second elementary current I e2  proportional to the absolute temperature from the first current I 2 . 
         [0064]    The means MG also comprise subtraction means MS configured for subtracting the second elementary current I e2  from the first elementary current I e1  in such a manner as to obtain a second current I refi  inversely proportional to the absolute temperature. 
         [0065]    Means M refi  are also provided for transforming the second current I refi  into the intermediate reference voltage V refi . 
         [0066]    The output stage ES comprises a first current copying means comprising two transistors PMOS TM 1  and TN 1  having their sources mutually connected to the power supply voltage V DD , their gates mutually connected to the output of the operational amplifier OP 1 . The drain of the transistor TM 1  is connected to the output terminal BS CR  and the drain of the transistor TN 1  is connected to the input terminal BE 3  of the subtraction means MS. 
         [0067]    The drain current It of the transistor TM 1  is equal to the sum of the currents I 1  and I 2 . The elementary current I e2  coming from the transistor TN 1  is proportional to the current I t  according to the equation I 2 =I t *N1/M1, where N1 and M1 are the ratios of channel width and length of the transistors TN 1  and TM 1 . 
         [0068]    As a consequence, the elementary current I e2  is also proportional to the temperature as are I 1  or I 2 . 
         [0069]    The output stage ES furthermore comprises an operational amplifier OP 2 , configured as a follower, whose inverting input is connected to the output terminal BS CR . The non-inverting input is connected to a terminal BE 4  connected to ground via a resistor R 3  and the output of the amplifier OP 2  is connected to the gates of the transistors PMOS TN 2  and TM 2  which form a second current copying means. 
         [0070]    The sources of the transistors TN 2  and TM 2  are mutually connected to the voltage V DD . The drains of the transistors TN 2  and TM 2  are respectively connected to the output terminal BS MS  of the subtraction means MS and to the terminal BE 4 . 
         [0071]    As was described hereinbefore, the voltage V BI  is configured to be constant and independent of the temperature. By virtue of the amplifier OP 2 , the voltage on the terminal BE 4  is equal to V BI  and is also constant and independent of the temperature. 
         [0072]    As a consequence, the current I 3  flowing through the resistor R 3 , equal to V BI /R 3 , is also independent of the temperature. 
         [0073]    Thus, an elementary current Ie 1  may be obtained on the drain of the transistor TN 2  starting from the band-gap voltage V BI  which is equal to I 3 *N2/M2, where N2 and M2 are the ratios of width and of length of channel of the transistors TN 2  and TM 2 . This current I e1  is de facto independent of the absolute temperature. 
         [0074]    The subtraction means MS comprise, for example, a current mirror comprising two transistors NMOS TS 1  and TS 2 . The drains of the transistors TS 1  and TS 2  are respectively connected to the input terminal BE 3  and to the output terminal BS MS  and their sources are mutually connected to ground. The gates of the transistors TS 1  and TS 2  are mutually connected to the drain of the transistor TS 1 . 
         [0075]    Accordingly, the current flowing in the transistor TS 2  towards ground is equal or substantially equal to the current I e2  and the output current I refi  delivered at the output terminal BS MS  is therefore equal to I e1 −I e2 . 
         [0076]    Since the current I e1  is constant and the current I e2  is proportional to the temperature, the intermediate reference current I refi  is inversely proportional to the temperature and is equal to −A1T+A2. 
         [0077]    The values of the coefficients A1 and A2 are adjustable via the sizes N1, N2, M1 and M2 of the transistors TN 1 , TN 2 , TM 1  and TM 2 . 
         [0078]    The intermediate reference current I refi  is subsequently delivered to the means M refi , which comprise for example a resistor R, for transforming the current I refi  into the intermediate reference voltage V refi , which is decreasing as a function of temperature according to an affine law: V refi =−A1RT+A2R. 
         [0079]    In order to generate the programming voltage V G  as a high voltage for the breakdown of the dielectric of the memory cells CEL, a charge pump PC is used within the programming voltage source STP and is illustrated in  FIGS. 5 and 6 . 
         [0080]    The structure of a charge pump is conventional and known per se and  FIGS. 5 and 6  only illustrate one non-limiting exemplary embodiment. 
         [0081]    The intermediate reference voltage V refi  is delivered to the positive input of a operational amplifier OP 3 . The negative input of this operational amplifier OP 3  is connected to an input terminal BE 5 . Two resistors R 4  and R 5  are respectively connected between the output terminal BS TE  of the charge pump PC and the terminal BE 5  and between the terminal BE 5  and ground. The output of the operational amplifier OP 3  is connected to an input of a multiplier MUL which furthermore receives a clock signal CLK in order to deliver an internal clock signal to the charge pump stages. 
         [0082]    The pump stages EP_i receive the power supply voltage V DD  and the internal clock signal CLK_INT as input signals for generating the programming voltage V G  equal to V refi *(R 4 +R 5 )/R 5  at the output terminal BS TE . 
         [0083]      FIG. 6  illustrates a pump stage EP_i. 
         [0084]    In a first phase φ1, controlled by the internal clock signal, the input voltage Vin_i of the pump stage EP_i (which is equal to the output voltage of the preceding pump stage) charges a pump capacitor. For the first pump stage EP, the input voltage is the power supply voltage V DD . 
         [0085]    In a second phase φ2, also controlled by the internal clock signal CLK_INT, the capacitor is connected between the power supply voltage VDD and the output of the stage. If the leakage of the capacitor is ignored, the output voltage of each pump stage EP is increased by the voltage due to the discharging of the capacitor. 
         [0086]    By multiplying the pump stages EP_i, a high voltage can be obtained at the output of the pump stages EP_i. 
         [0087]    The last stage delivers the programming voltage V G  which is inversely proportional to the absolute temperature T of the memory cells CEL and follows a decreasing affine voltage-temperature law. 
         [0088]    Depending on the desired programming time and on the corresponding affine law V G =−C1T+C2, the source STP will be calibrated accordingly by an adjustment of the various aforementioned parameters in order to obtain the desired values of the coefficients C1 and C2. 
         [0089]    The invention thus advantageously allows the voltage for programming cells OTP of an integrated circuit installed in a product whose temperature can vary in operation to be modulated in real time.