Abstract:
A control interface for the bit rate of digital data to be recorded as well as a control interface for the bit rate of digital data emanating from a reading device, particularly when the digital data constitutes a high bit rate uninterrupted data stream such as a video data stream in the MPEG II format. Each control interface comprises a memory circuit for storing the data to be recorded or to be read and a device for storing the data to be recorded or read in the memory circuit so as to fill the memory circuit to a predetermined level. The storing device includes a gauge for generating an information item giving the fill level of the memory.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to the recording and/or reading of a digital data stream. 
     The invention applies more particularly to the case where the data stream is a high bit rate uninterrupted stream such as, for example, a data stream in the MPEG II format. 
     The recording and reading of digital data can be performed either with the aid of digital recorders, or with the aid of digital video recorders. 
     As will become apparent in the remainder of the description, the invention finds a particularly advantageous application with regard to the recording and reading of digital data with the aid of digital video recorders. However, the invention applies equally to the recording and reading of digital data with the aid of digital recorders. 
     SUMMARY OF THE INVENTION 
     Thus, the invention relates to an interface for controlling the bit rate of digital data to be recorded. The control interface comprises at least one memory circuit for storing the data to be recorded and means whereby the data to be recorded can be stored in the memory circuit in such a way as to fill the memory circuit to a predetermined level under the action of a write command, of a read command and of a reset to zero command for a level indicator of the memory circuit, these commands being applied to the memory circuit. 
     Similarly, the invention relates to an interface for controlling the bit rate of digital data emanating from a reading device. The control interface comprises at least one memory circuit for storing the data to be read and means whereby the data to be read can be stored in the memory circuit in such a way as to fill the memory circuit to a predetermined level under the action of a write command, of a read command and of a reset to zero command for a fill level indicator for the memory circuit, these commands being applied to the memory circuit. 
     The invention also relates to a digital data recording system consisting of a control interface for the bit rate of data to be recorded and of a device for recording the digital data emanating from the control interface. The interface for controlling the bit rate of the data to be recorded is an interface such as that according to the invention mentioned above. 
     The invention also relates to a digital data reading system consisting of a device for reading digital data and a control interface for the bit rate of the digital data emanating from the reading device. The control interface for the bit rate of the digital data emanating from the reading device is a control interface such as that according to the invention mentioned above. 
     The invention also relates to a digital data recording/reading system comprising a control interface for the bit rate of digital data to be recorded, a recording/reading device and a control interface for the bit rate of digital data emanating from the recording/reading device. The control interface for the bit rate of digital data to be recorded is a control interface such as that according to the invention mentioned above and the control interface for the bit rate of the digital data emanating from the recording/reading device is an interface such as that according to the invention mentioned above. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     So as not to unnecessarily burden the description, the invention will be described with the aid of a single FIGURE representing a recording/reading system according to the preferred embodiment of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The recording/reading system according to the invention consists of a recording/reading device  1 , a control interface  2  for the data to be recorded and a control interface  3  for the data read emanating from the recording/reading device. 
     According to the invention, the recording/reading device is a digital recorder or a digital video recorder. Preferably, the recording/reading device is a digital video recorder. 
     According to the preferred embodiment of the invention, the digital data recorded or read are video data in the MPEG II format. However, more generally the invention relates to a recording/reading system for digital data of any type of format. 
     The control interface  2  for the data to be recorded is composed of an FIFO-type memory  5 , a gauge  6 , a control circuit  7 , a clock device  8  and a formatting device  9 . 
     The digital video data VE to be recorded travel over a databus BE which, as is known to a person skilled in the art, additionally conveys the clock signal CLK BE  accompanying the video data VE. 
     The video data VE are transferred to the input of the FIFO-type memory  5  and the clock signal CLK BE  is applied to the control circuit  7  which, consequently, is synchronized with the video data stream VE. 
     The device  8  generates a clock signal CLK 1  which is applied to the gauge  6  and to the control circuit  7 . The clock CLK 1  is the internal clock of the control interface  2 . The application of the clock signal CLK 1  to the gauge  6  and to the control circuit  7  is intended to ensure synchronous operation of the gauge  6  and of the control circuit  7 . 
     By way of example, for video data in the 4:2:2 format, the frequency of the clock signal CLK 1  is substantially equal to 27 MHz. 
     The control circuit  7  generates  3  control signals W 1 , R 1  and RST 1  which are applied, on the one hand, to the memory  5  and, on the other hand, to the gauge  6 . The signal W 1  is a command which enables the writing of the data VE to the memory  5 . The signal R 1  is a command which enables the extraction of the data stored in the memory  5 . The signal RST 1  is a command for resetting the pointer of the memory  5  to zero. As is known to a person skilled in the art, the pointer of an FIFO-type memory is an indicator of the fill level of the memory. 
     The operation of the control device  2  comprises two phases: a transient phase and a steady-state phase. 
     During the transient phase, the signal RST 1  sets to zero the pointer of the memory  5  and the level indicator of the gauge  6 . 
     After setting the pointer of the memory  5  to zero, the write command W 1  applied to the memory  5  enables the writing of the data VE to the memory  5  so that the latter reaches a predetermined fill level N 1 . 
     According to the preferred embodiment of the invention, for which the video data VE are data in the MPEG II format, in the case where, for example, the memory capacity of the FIFO-type memory  5  is 32 N kbytes, the predetermined fill level N 1  of the memory  5  is substantially equal to half the memory capacity of the memory  5 . 
     Having reached the predetermined fill level, the transient phase is complete and the steady-state phase begins. 
     The steady-state phase consists in permitting the data contained in the memory  5  to be transmitted from the memory  5  to the formatting device  9  provided that the fill level of the memory  5  remains substantially the predetermined fill level mentioned earlier. 
     To this end, the gauge  6  generates an information item I N1 , the purpose of which is to give the fill level N 1  of the memory  5  accurately. The information item I N1  is a binary word. Preferably, the information item I N1  is a binary word of 15 bits. The number of different combinations which the binary word I N1  may take is then equal to 32 kbytes. Advantageously, the state of fill of the memory  5  can then be given with the greatest possible accuracy. 
     The information item I N1  is applied to the control circuit  7 . 
     Under the action of the information item I N1 , the control circuit  7  makes it possible, with the aid of commands W 1  and R 1  which it generates, for the fill level of the memory  5  to remain substantially equal to the predetermined fill level. 
     When the control circuit is made to halt the reading of the data, the recording device  1  records dummy data blocks. The dummy data make it possible to ensure the continuity of the signal to be transmitted. 
     The term dummy data should be understood to mean data which contain no useful video information item to be recorded. By way of examples, the dummy data may be either self-test data, in the case in which a self-test function is provided in order to verify that the recording conditions are correct, or data which reproduce the latest recorded data emanating from the memory  5 . In order to be recognized during reading, the dummy data blocks include a particular header. 
     According to the preferred embodiment of the invention, the recording device  1  is a digital video recorder which records the data in the form of successive frames. 
     When the number of kbytes representing an image frame has been recorded, the digital video recorder records blocks of dummy data such as the data mentioned above. 
     The gauge  6  is, for example, a forward/backward counting circuit: the command W 1  initiates forward counting, the command R 1  initiates backward counting and the command RST 1  initiates resetting to zero of the counter. 
     The formatting device  9  makes it possible to put the data D 1  emanating from the memory  5  into the format of the recording device  1 . The data D 2  emanating from the formatting device  9  are then transmitted to the recording device  1 . By way of example, a recording format may be the 4:2:2 format. 
     The control interface  3  for the recorded data emanating from the recording/reading device  1  comprises a deformatting and validation device  10 , an FIFO-type memory  11 , a gauge  12 , a clock device  13 , a control circuit  14 , a microprocessor  15  and a circuit  16  for controlling the playing speed of the medium read by the recording/reading device  1 . 
     As mentioned earlier, the recorded data are put into the format required by the recording device  1 . Conversely, the data D 3  emanating from the recording/reading device  1  are deformatted by the device  10 . 
     According to the invention, the purpose of the device  10  is also to select the valid data contained in the data stream D 3 . The valid data are selected on the basis of their header. 
     The deformatted data validated as useful data D 4  emanating from the device  10  are transmitted to the memory  11 . 
     The clock device  13  generates the clock signal CLK BS  accompanying the video data VS emanating from the memory  11 . The video data VS and the clock signal CLK BS  travel over the output bus BS. 
     The clock signal CLK BS  is applied to the control circuit  14 . 
     The clock signal CLK 2  of the control interface  3  is applied to the control circuit  14  and to the gauge  12 . Preferably, the clock signal CLK 2  emanates from the recording/reading device  1 . By way of example, for video data in the 4:2:2 format, the frequency of the clock signal CLK 2  is substantially equal to 27 MHz. 
     The control circuit  14  generates  3  control signals W 2 , R 2  and RST 2  which are applied, on the one hand, to the memory  11 , and, on the other hand, to the gauge  12 . 
     The signal W 2  is a command which enables the writing of the data D 4  to the memory  11 . The signal R 2  is a command which enables the extraction of the data stored in the memory  11 . The signal RST 2  is a command allowing the pointer of the memory  11  to be reset to zero. 
     Just like the control device  2 , the control device  3  operates according to a transient phase and a steady-state phase. 
     During the transient phase, the signal RST 2  sets to zero the pointer of the FIFO-type memory  11  and the level indicator of the gauge  12 . 
     After setting the pointer of the memory  11  to zero, the write command W 2  applied to the memory  11  enables the writing of the data D 4  to the memory  11  so that the latter reaches a predetermined fill level N 2 . 
     According to the preferred embodiment of the invention, the memory capacity of the memory  11  is identical to the memory capacity of the memory  5 . It follows that the predetermined fill level N 2  is, preferably, substantially equal to half the memory capacity of the memory  11 . 
     When the predetermined fill level is reached, the steady-state phase begins. In the steady state, the data D 4  are written to the memory  11  at the frequency of the clock signal CLK BS  emanating from the clock device  13 . Preferably, the frequency of the clock signal CLK BS  is identical to the frequency of the clock signal CLK BE . 
     The gauge  12  is, for example, a forward/backward counting circuit: the command W 2  initiates forward counting, the command R 2  initiates backward counting and the command RST 2  initiates resetting to zero of the counter. 
     The gauge  12  generates an information item I N2  which gives the state of fill of the memory  11 . Like the information item I N1 , the information item I N2  is preferably a binary word of 15 bits allowing the greatest possible accuracy for the state of fill of the memory  11 . The changes in the state of fill of the memory  11  can then be followed with very high accuracy. 
     The information item I N2  is applied to the microprocessor  15  in a sampled manner at regular time intervals. Preferably, the application of the information item I N2  to the microprocessor  15  is performed in tempo with the frame period. It follows that each frame of order k has its bit rate controlled on the basis of the calculated bit rate for the frame of order k- 1 . 
     The microprocessor  15  calculates the mean value of the bit rate of the data VS emanating from the memory  11  on the basis of the sampled information item I N2 . 
     The microprocessor  15  has a set-point value CS in memory which represents the desired nominal bit rate for the data VS. 
     The microprocessor  15  compares the calculated mean value of the bit rate of the data VS with the set-point value CS and calculates a correction signal CR which is applied to the circuit  16  for controlling the playing speed of the medium read by the recording/reading device  1 . 
     Under the action of the correction signal CR, the circuit  16  for controlling the playing speed of the medium read generates a control signal CD which is applied to the circuit which controls, inside the device  1 , the playing speed of the medium read. 
     Advantageously, the speed of reading the medium is then controlled directly via the bit rate of the stream of data VS emanating from the control interface  3 . 
     A medium which has been recorded at a place where the local clock CLK 1  which regulated the recording of the data has a substantially different frequency from the local clock CLK 2  which regulates reading, can then be read without distortion. By way of example, the margin within which the frequency of the clocks CLK 1  and CLK 2  may vary is plus or minus 10 ppm, i.e. plus or minus 270 Hz around 27 MHz. 
     Moreover, on account of the very high accuracy with which the state of fill of the memory  11  can be followed, the control loop for the speed of the reading system advantageously exhibits very high stability. 
     According to an enhancement of the invention, the correction signal CR is also applied to the clock device  13 . 
     Generally, the frequency of the clock signal CLK BS  is fixed using a quartz oscillator. According to the enhancement mentioned above, the control of the playing of the read medium can be enhanced by modifying the frequency of the clock CLK BS  under the action of the signal CR applied to the device  13 . To this end, the clock device  13  comprises means whereby the frequency of the clock signal CLK BS  may be modified. These means are means known to a person skilled in the art. It is therefore unnecessary to recall them here. 
     Preferably, modification of the frequency of the clock signal CLK BS  under the action of the correction signal CR is implemented in the case where the filling or emptying of the memory  11  is such that the data bit rate can no longer be correctly ensured solely under the action of the control signal CD applied to the control circuit internal to the recording/reading device.