Abstract:
In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     Not Applicable 
     STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT 
     Not Applicable 
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to semiconductor package technology, and more particularly to a unique manufacturing methodology for a semiconductor package wherein singulation is accomplished by etching as opposed to mechanical cutting (e.g, sawing or punching). 
     Integrated circuit dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and an underlying substrate such as printed circuit board (PCB). The elements of such a package include a metal leadframe, an integrated circuit die, bonding material to attach the integrated circuit die to the leadframe, bond wires which electrically connect pads on the integrated circuit die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package often referred to as the package body. In a cavity type semiconductor package, the package body is substituted with a prefabricated cavity which is formed on the leadframe, the die being positioned within the cavity and sealed therein by a lid or similar structure which is attached to the cavity. 
     The leadframe is typically the central supporting structure of a semiconductor package. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant package body or the prefabricated cavity. Portions of the leads of the leadframe extend externally from the package or are partially exposed within the package body or cavity for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die pad of the leadframe also remains exposed within the package body for use as a heat sink. 
     For purposes of high volume, low cost production of semiconductor packages, a current industry practice is to etch or stamp a thin sheet of metal material to form a panel or strip which defines multiple leadframes. A single strip may be formed to include multiple arrays, with each such array including a multiplicity of leadframes in a particular pattern. In a typical semiconductor package manufacturing process, integrated circuit dies are mounted and wire bonded to respective ones of the leadframes, with the encapsulant material then being applied to the strip so as to encapsulate the integrated circuit dies, bond wires, and portions of each of the leadframes in the above-described manner. The hardening of the encapsulant material facilitates the formation of a mold cap upon the leadframes. 
     Upon the hardening of the encapsulant material, the leadframes within the strip are cut apart or singulated for purposes of producing the individual semiconductor packages. Such singulation is typically accomplished via a saw singulation process or a mechanical punching operation. In the saw singulation process, a saw blade is advanced along “saw streets” which extend in prescribed patterns between the leadframes as required to facilitate the separation of the leadframes from each other in the required manner. The advancement of the saw blade along the saw streets currently cuts the molded plastic mold cap, thus facilitating the formation of the above-described molded plastic package body upon each of the separated leadframes. With particular regard to cavity type semiconductor packages, the saw blade is advanced along the saw streets which typically extend between the various cavities formed on the strip. 
     One of the drawbacks associated with the saw singulation process used in relation to the manufacture of semiconductor packages is that the saw blade used in the saw singulation process cuts through copper (i.e., the metal material typically used to fabricate the strip) usually most of the time. As will be recognized, this level of sawing through copper as occurs as a result of the configuration of the strip often results in the premature wear of the costly saw singulation blades. Another drawback of the saw singulation process is that the same also typically results in the burring of the leads of the separated leadframes. Saw generated burrs at the leads often adversely affect solder mounting and joint reliability. In current semiconductor package fabrication methodologies, lead burrs are often controlled by limiting the feed rate of the saw blade along the saw streets and by using specifically developed, high cost saw blades. However, as will be recognized, the use of the high cost saw blades is undesirable due to the resultant increase in production cost, with the reduced feed rates needed to control burring also adversely affecting production speed, and thus efficiency. With particular regard to the punch singulation process, one of the drawbacks associated with the use of such process is the tendency for the hardened encapsulant material or package body of the semiconductor package to chip or crack as a result of the punching operation. As will be recognized, such chipping or cracking of the package body can result in the accelerated failure thereof as a result of, among other things, moisture permeation to the embedded integrated circuit die. Further, punch singulation is typically not preferred for applications using mechanically sensitive die due to the perceived risk associated with impact vibration (e.g., MEMS). 
     The present invention addresses the above-described drawbacks by providing a semiconductor package having structural attributes which are uniquely tailored such that the singulation process is achieved using etching techniques. Advantageously, etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques (e.g., sawing, punching) as highlighted above. These, and other advantages of the present invention, will be discussed in more detail below. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques. 
     The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These as well as other features of the present invention will become more apparent upon reference to the drawings wherein: 
         FIG. 1  is a cross-sectional view of a semiconductor package constructed in accordance with one embodiment of the present invention; 
         FIGS. 2A and 2B  illustrate an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package shown in  FIG. 1 ; 
         FIG. 3  is a cross-sectional view of a semiconductor package constructed in accordance with another embodiment of the present invention. 
         FIG. 4  is a cross-sectional view of a semiconductor package constructed in accordance with yet another embodiment of the present invention; 
         FIGS. 5A-5E  illustrate an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package shown in  FIG. 4 ; 
         FIG. 6  is a top plan view of a patterned leadframe strip used to facilitate the simultaneous fabrication of multiple semiconductor packages each having the structural attributes shown in  FIG. 4 ; and 
         FIGS. 7A-7E  illustrate an exemplary sequence of steps which may be used to facilitate the fabrication of a semiconductor package constructed in accordance with yet another embodiment of the present invention. 
     
    
    
     Common reference numerals are used throughout the drawings and detailed description to indicate like elements. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings where the showings are for purposes of illustrating various embodiments of the present invention only, and not for purposes of limiting the same,  FIG. 1  illustrates a semiconductor package  10  constructed in accordance with one embodiment of the present invention. The semiconductor package  10  comprises a leadframe  12  which is preferably fabricated from a conductive metal material (e.g., copper). The leadframe  12  includes a die pad  14  which has a generally quadrangular (e.g., square, rectangular) configuration and defines opposed, generally planar top and bottom surfaces. In addition to the die pad  14 , the leadframe  12  includes a plurality of leads  16 . The leads  16  are typically segregated into multiple sets, with the leads  16  of each set extending along and in spaced relation to a respective one of the peripheral edge segments defined by the die pad  14 . In this regard, the leadframe  12  of the semiconductor package  10  may be provided with one or more sets of leads  16 , each such set extending along and in spaced relation to a respective peripheral edge segment of the die pad  14 . Each of the leads  16  of the leadframe  12  is formed to define opposed, generally planar top and bottom surfaces. 
     In the semiconductor package  10 , the bottom surfaces of the die pad  14  and each of the leads  16  each preferably include a plating layer  18  which is applied to at least a portion thereof. Each plating layer  18  may be fabricated from any one of a number of suitable conductive metal materials through the implementation of any suitable, currently known plating technique. However, it is contemplated that any material or combination of materials used to facilitate the formation of the plating layers  18  will be impervious to etching through the use of chemicals suited to the etching or removal of copper, for reasons which will be described in more detail below. 
     As further seen in  FIG. 1 , the semiconductor package  10  also includes a first semiconductor die  20  which is mounted to the top surface of the die pad  14  through the use of, for example, an adhesive. The pads of terminals of the semiconductor die  20  are electrically connected to the top surfaces of respective ones of the leads  16  through the use of conductive wires  22 , though it is also contemplated that a flip chip interconnection may alternatively be used to facilitate the electrical connection of the semiconductor die  20  to the leads  16 . In addition to the first semiconductor die  20 , the semiconductor package  10  includes a second semiconductor die  24  which is stacked upon and attached to the first semiconductor die  20 . The pads or terminals of the second semiconductor die  24  are electrically connected to corresponding pads or terminals of the first semiconductor die  20  through conductive wires  22  as well, though a flip chip interconnection may also be employed to facilitate the electrical connection of the second semiconductor die  24  to the first semiconductor die  20 . Those of ordinary skill in the art will recognize that the number and arrangement of semiconductor dies within the semiconductor package  10  may be varied in accordance with a particular application therefore, the depiction of the first and second semiconductor dies  20 ,  24  in the semiconductor package  10  being exemplary only. In this regard, it is contemplated that one or more passive devices may also be integrated into the semiconductor package  10  in addition or as an alternative to the second semiconductor die  24 . 
     Also included in the semiconductor package  10  is a package body  26  which is preferably fabricated from a hardened plastic encapsulant material. The package body  26  is formed to cover or encapsulate the first and second semiconductor dies  20 ,  24 , as well as the conductive wires  22  and the exposed portions of the top and bottom surfaces of the die pad  14  and leads  16 . As will be recognized, those portions of the bottom surfaces of the die pad  14  and leads  16  which are exposed are those, if any, not covered by respective ones of the plating layers  18 . Due to the manner in which the package body  26  is preferably formed, the bottom surfaces of the plating layers  18  are exposed in and may be substantially flush with a generally planar bottom surface  28  defined by the body  26 . The outer ends of the leads  16  (i.e., those ends of the leads  16  disposed furthest from the die pad  14 ) are recessed inwardly relative to a side surface  30  of the package body  26  for reasons which will also be discussed in more detail below. 
     Having thus described the structural attributes of the semiconductor package  10 , a preferred method of fabricating the same will now be described with particular reference to  FIGS. 2A and 2B . In fabricating the semiconductor package  10 , a leadframe strip  32  is initially provided, a portion of such strip being shown in  FIG. 2A . The strip  32  typically has a generally rectangular configuration, and defines a multiplicity of the above-described leadframes  12  which are arranged in a prescribed pattern. Within the leadframe strip  32 , the leads  16  of each set within each individual leadframe  12  typically extend inwardly from a respective one of a multiplicity of connecting bar portions  34  which are defined by the leadframe strip  32 , one such connecting bar portion  34  being shown in  FIG. 2A . Additionally, within the leadframe strip  32 , the leads  16  of each leadframe  12  typically extend about a central opening in which the die pad  14  is positioned and suspend via multiple tie bars (not shown) which extend to corresponding, adjacent connecting bar portions  34 . The individual leadframes  12  within the leadframe strip  32  are typically formed through the completion of an etching or a stamping process. 
     As is further seen in  FIG. 2A , the leadframe strip  32  including the individual leadframes  12  is subjected to a plating process wherein the die pad  14  and leads  16  of each leadframe  12  within the leadframe strip  32  are plated with the above-described plating layers  18 . More particularly, bottom surfaces of the die pad  14  and leads  16  of each leadframe  12  are selectively pre-plated to include respective ones of the plating layers  18 . As seen in  FIG. 2A , in the plating process, the plating layer  18  formed on the bottom surface of the die pad  14  of each leadframe  12  is preferably sized relative to the die pad  14  so as to terminate inwardly relative to the peripheral edge segments thereof. Similarly, the plating layer  18  formed on the bottom surface of each lead  16  of each leadframe  12  is preferably sized relative to the lead  16  so as to terminate inwardly from the inner end thereof which is disposed closest to the corresponding die pad  14 . As such, the die pad  14  of each leadframe  12  and the corresponding plating layer  18  applied to the bottom surface thereof collectively defined a recessed shelf which extends about the periphery of the die pad  14 . Similarly, each lead  16  of each leadframe  12  and the corresponding plating layer  18  applied thereto collectively define a recessed shelf which extends along at least the inner end of the lead  16 . 
     After the plating layers  18  have been applied to the die pad  14  and leads  16  of each leadframe  12  within the leadframe strip  32  in the above-described manner, a die attach process is completed wherein the first semiconductor dies  20  are attached to the top surfaces of respective ones of the die pads  14 , and the second semiconductor dies  24  (if any) are attached to the exposed top surfaces of respective ones of the underlying first semiconductor dies  20 . Thereafter, a wire bonding process is completed wherein the first semiconductor dies  20  are electrically connected to the top surfaces of one or more of the leads  16  of the corresponding leadframe  12  through the use of the conductive wire(s)  22 , and each second semiconductor die  24  (if included) is electrically connected by at least one conductive wire  22  to the corresponding, underlying first semiconductor die  20  and/or directly to one or more of the leads  16  of the corresponding leadframe  12 . 
     Subsequent to the completion of the wire bonding process, a molding process is completed wherein individual package bodies  26  are formed upon the leadframe strip  32  in the manner shown in  FIG. 2A . More particularly, each package body  26  is formed such that the exposed surfaces of the die pad  14  and leads  16  of the corresponding leadframe  12  are covered thereby, as are the first and second semiconductor dies  20 ,  24  and conductive wires  22  mounted to the corresponding leadframe  12 . Each package body  26  is further formed such that the generally planar bottom surfaces of the plating layers  18  formed on the corresponding leadframe  12  are exposed in the bottom surface  28  of the package body  26 . The bottom surfaces of the plating layers  18  will typically be substantially flush with the bottom surface  28  of the package body  26 , though they may protrude slightly therefrom. Importantly, since the plating layers  18  are sized to cover less area than the corresponding bottom surfaces of the die pad  14  and leads  16  to which they are applied as described above, the encapsulant material used to form each individual package body  26  effectively underflows into the aforementioned recessed shelves collectively defined by the die pad  14 , leads  16  and plating layers  18 . Such underflow effectively creates a locking feature which assists in maintaining a firm mechanical interlock between the die pad  14  and leads  16  of each leadframe  12  and the corresponding package body  26  of the resultant semiconductor package  10 . 
     Upon the complete formation of the individual package bodies  26  thereon, the leadframe strip  32  is subjected to a chemical etching process wherein a suitable chemical etchant is applied to the exposed connecting bar portions  34  of the leadframe strip  32 . The etching may be performed using wet chemical or another etching technique. Wet etching can be performed using either immersion or spray methods. Importantly, the plating layers  18  applied to the die pad  14  and leads  16  of each leadframe  12  within the leadframe strip  32  effectively serve as an etch mask, with the removal of the connecting bar portions  34  effectuated by the application of the chemical etchant thereto effectively separating the individual semiconductor packages  10  from each other within the leadframe strip  32 . In this regard, the etchants are adapted to be selective over the pre-plated finish material used for the plating layers  18 . 
     As is seen in  FIGS. 1 and 2B , as a result of the singulation of the leadframe strip  32  through the completion of the chemical etching process, some undercut in the leads  16  of each leadframe  12  occurs as a result of such etching. More particularly, the outer end of each lead  16  is recessed slightly inwardly from the side surface  30  of the corresponding package body  26 . The outer end of each lead  16  is also recessed slightly inwardly from the outer end of the corresponding plating layer  18  applied thereto, such plating layer  18  being unaffected by the etchant. It is contemplated that such undercut in each of the leads  16  may be minimized by using a leadframe strip  32  in the fabrication process wherein the individual leadframes  12  thereof are already subjected to a half-etching process for purposes of forming recessed shelves within the die pad  14  and leads  16  thereof as needed to create firm mechanical interlocks to the corresponding package body  26 . The undercuts, if present in the resultant semiconductor package  10 , may serve as solder fillets, thus enhancing the solder joint reliability between the semiconductor package  10  and an underlying substrate such as a printed circuit board when the semiconductor package  10  is mounted thereto. Further, since the plating layers  18  applied to the die pad  14  and leads  16  of each leadframe  12  serve as an etch resist, the etching of the connecting bar portions  34  may occur from either or both sides of the leadframe strip  32 . 
     Referring now to  FIG. 3 , there is shown a semiconductor package  36  constructed in accordance with another embodiment of the present invention. The semiconductor package  36  is substantially similar in construction to the semiconductor package  10 , with the primary distinction being that the package body  26  in the semiconductor package  10  is substituted with a cavity  38  in the semiconductor package  36 . The cavity  38  is formed to include portions which extend between and thus fill the gaps or voids defined between the leads  16  and between the leads  16  and the die pad  14  of the corresponding leadframe  12 . Thus, the generally planar bottom surfaces of the plating layers  18  formed on the bottom surfaces of the die pad  14  and leads  16  are exposed in and typically substantially flush or continuous with the generally planar bottom surface of the cavity  38 . In the semiconductor package  36 , the first semiconductor die  20 , the second semiconductor die  24  (if included) and the conductive wire(s)  22  are each disposed within the interior of cavity  38 . The points of connection between the conductive wires  22  and the corresponding pads or terminals of the first and second semiconductor dies  20 ,  24  are covered with a layer  40  of protective material. A lid is attached to the upper rim of the cavity  38 , with the first and second semiconductor dies  20 ,  24  and conductive wires  22  thus being enclosed and sealed within the interior chamber collectively defined by the leadframe  12 , cavity  38  and lid  42 . 
     The manufacturing process for the semiconductor package  36  is similar to that described above in relation to the semiconductor package  10 , with the primary being distinction being that the molding step used to facilitate the formation of the package bodies  26  upon the leadframe strip  32  is substituted with a molding step wherein the individual cavities  38  are formed upon respective ones of the leadframes  12  of the leadframe strip  32  in the manner shown in  FIG. 3  and described above. Subsequent to the formation of the individual cavities  38  upon each of the leadframes  12  of the leadframe strip  32 , the die attach and the wire bonding processes described above in relation to the semiconductor package  10  are completed, with the layer  40  of protective material then being applied to the first and second semiconductor dies  20 ,  24  and conductive wires  22  mounted to each leadframe  12 . The lids  42  are then attached to respective ones of the cavities  38  for purposes of enclosing the corresponding first and second semiconductor dies  20 ,  24  therein. The above-described etching process is then completed to effectively separate the semiconductor packages  36  from each other. As in the semiconductor package  10  described above, the completion of the etching process in relation to the semiconductor packages  36  results in each of the leads  16  of each semiconductor package  36  including the aforementioned undercut, i.e., the outer end of each lead  16  of the semiconductor package  36  is slightly recessed inwardly relative to the outer surface or wall  44  of the corresponding cavity  38 . 
     Referring now to  FIG. 4 , there is shown a semiconductor package  46  constructed in accordance with yet another embodiment of the present invention. The semiconductor package  46  comprises a leadframe  48  preferably fabricated from a conductive metal material. The leadframe  48  includes a die pad  50  which has a generally quadrangular (e.g., square, rectangular) configuration and defines opposed, generally planar top and bottom surfaces. In addition to the die pad  50 , the leadframe  48  includes a plurality of leads  52 . The leads  52  are typically segregated into multiple sets, with the leads  52  of each set extending along and in spaced relation to a respective one of the peripheral edge segments defined by the die pad  50 . In this regard, the leadframe  48  may be provided with one or more sets of leads  52 , each such set extending along and in spaced relation to a respective peripheral edge segment of the die pad  50 . Each of the leads  52  of the leadframe  48  is formed to define opposed, generally planar top and bottom surfaces. 
     As further seen in  FIG. 4 , the semiconductor package  46  also includes a semiconductor die  54  which is mounted to the top surface of the die pad  50  through the use of, for example, an adhesive. The pads of terminals of the semiconductor die  54  are electrically connected to the top surfaces of respective ones of the leads  52  through the use of conductive wires  55 . 
     Also included in the semiconductor package  46  is a cavity  56  which is preferably fabricated from a hardened plastic encapsulant material such a liquid crystal polymer (LCP). As seen in  FIG. 4 , the cavity  56  is uniquely configured such that portions  56   a  thereof extend within and thus fill the gaps or voids which are normally defined between the leads  52 , and between the leads  52  and the die pad  50 . In this regard, the cavity  56  is formed to cover the outer end of each of the leads  52  (i.e., the end disposed furthest from the die pad  50 ) as well as an outer end portion of the top surface of each of the leads  52 . Also covered by the cavity  56  is the opposite inner end of each of the leads  52 , the peripheral edge of the die pad  58 , the peripheral portion of the top surface of the die pad  50 , and an inner end portion of the top surface of each of the leads  52 . Though not shown, the side edges of each of the leads  52  and portion of the top surfaces of each of the leads  52  extending along the side edges thereof may also be covered by the cavity  56 . The cavity  56  defines an angled or sloped outer surface  58 , and a generally planar bottom surface  60  which is typically substantially flush or continuous with the generally planar bottom surfaces of the leads  52  and die pad  50  of the leadframe  48 . 
     In the semiconductor package  46 , the exposed portions of the top surfaces of the leads  52  and die pad  50  of the leadframe  48 , the semiconductor die  54 , and the conductive wires  55  may be covered by an epoxy fill layer  62  which effectively protects the same. Attached to the upper rim of the cavity  56  is a lid  64  which effectively encloses and seals the semiconductor die  54  and conductive wires  55  (which are covered by the layer  62 ) in the interior chamber collectively defined by the leadframe  48 , cavity  56  and lid  64 . Though not shown, in the event the semiconductor package  46  is intended to have pressure sensing capabilities, it is contemplated that the layer  62  may be formed as a gel having a low modulus which is capable of transmitting pressure, the lid  64  being vented to allow for the application of varying pressure levels to the layer  62 . 
     Having thus described the structural attributes of the semiconductor package  46 , a preferred method of fabricating the same will now be described with particular reference to  FIGS. 5A-5E . In fabricating the semiconductor package  46 , a solid base strip  66  which is preferably fabricated from copper is initially provided ( FIG. 5A ). The base strip  66  is subjected to a plating process wherein the die pad  50  and leads  52  of the leadframe  48  are formed on the generally planar top surface of the base strip  66  ( FIG. 5B ). More particularly, it is contemplated that the die pad  50  and leads  52  will be formed by plating up Au/Pd/Ni/Cu/Ni/Pd/Au to a total thickness in the range of approximately 50-200 microns. 
     Upon the completion of the plate up process to form the die pad  50  and leads  52  of the leadframe  48 , a molding process is completed to facilitate the formation of the cavity  56  upon the leadframe  48  and base strip  66  in the above-described manner ( FIG. 5C ). As indicated above, portions of the cavity  56  are formed between and thus fill the gaps or voids defined between the leads  52  and between the leads  52  and die pad  50 . 
     After the cavity  56  has been formed on the leadframe  48  and base strip  66  in the above-described manner, a die attach process is completed wherein the semiconductor die  54  is attached to the top surface of the die pad  50  ( FIG. 5D ). Thereafter, a wire bonding process is completed wherein the semiconductor die  54  is electrically connected to the top surfaces of one or more of the leads  52  through the use of the conductive wire(s)  55 . Subsequent to the completion of the wire bonding process, the layer  62  of die encapsulant (e.g., an epoxy fill or gel) is placed into the cavity  56  so as to effectively cover the semiconductor  54  and conductive wires  55  in the manner also shown in  FIG. 5D . The lid  64  is then attached to the upper rim of the cavity  56  thereby effectively sealing the semiconductor die  54  and conductive wires  55  within the interior chamber collectively defined by the leadframe  48 , cavity  56  and lid  64 . 
     Subsequent to the attachment of the lid  64  to the cavity  56 , the base strip  66  is subjected to a chemical etching process wherein a suitable chemical etchant is applied thereto. The etching may be performed using wet chemical or another etching technique. Wet etching can be performed using either immersion or spray methods. The application of the etchant to the base strip  66  effectively removes the same its entirety, thus completing the formation of the semiconductor package  46  ( FIG. 5E ). The metal material used to form the die pad  50  and leads  52  of the leadframe  48  and plastic material used to form the cavity  56  are unaffected by the etchant used to remove the base strip  66 , thus resulting in the generally planar bottom surfaces of the die pad  50  and leads  52  being exposed in and substantially flush or continuous with the generally planar bottom surface  60  of the cavity  56  as shown in  FIGS. 4 and 5E . 
     Referring now to  FIG. 6 , though the fabrication of only a single semiconductor package  46  is shown in  FIGS. 5A-5E , it is contemplated that the manufacturing process for the semiconductor package  46  as described above will be conducted in a manner adapted to facilitate the simultaneous formation of multiple semiconductor packages  46 . In this regard, the base strip  66  will be provided in a size sufficient to allow for the formation of multiple leadframes  48  thereon in the manner shown in  FIG. 6 . The subsequent assembly steps for the semiconductor packages  46  are completed in the same manner described above, the cavities  56  being formed on corresponding leadframes  48  of the enlarged base strip  66 . The singulation step accomplished by the ultimate removal of the enlarged base strip  66  through the application of the chemical etchant thereto effectively separates the completed semiconductor packages  46  from each other. 
     Referring now to  FIGS. 7A-7E  there is shown a sequence of steps which may be used to facilitate the fabrication of a semiconductor package  70  (shown in its completed state in  FIG. 7E ) constructed in accordance with yet another embodiment of the present invention. The semiconductor package  70  comprises a leadframe  72  preferably fabricated from a conductive metal material. The leadframe  72  includes a die pad  74  which has a generally quadrangular (e.g., square, rectangular) configuration and defines opposed, generally planar top and bottom surfaces. In addition to the die pad  74 , the leadframe  72  includes a plurality of leads  76 . The leads  76  are typically segregated into multiple sets, with the leads  76  of each set extending along and in spaced relation to a respective one of the peripheral edge segments defined by the die pad  74 . In this regard, the leadframe  72  may be provided with one or more sets of leads  76 , each such set extending along and in spaced relation to a respective peripheral edge segment of the die pad  74 . Each of the leads  76  of the leadframe  72  is formed to define opposed, generally planar top and bottom surfaces. The semiconductor package  70  also includes a semiconductor die  78  which is mounted to the top surface of the die pad  74  through the use of, for example, an adhesive. The pads of terminals of the semiconductor die  78  are electrically connected to the top surfaces of respective ones of the leads  76  through the use of conductive wires  80 . 
     Also included in the semiconductor package  70  is a package body  82  which is preferably fabricated from a hardened plastic encapsulant material such a liquid crystal polymer (LCP). The package body  82  fills the gaps or voids which are normally defined between the leads  76 , and between the leads  76  and the die pad  74 . More particularly, the package body  82  covers the exposed portions of the top surfaces of the die pad  74  and the leads  76 , the peripheral edge of the die pad  74 , and the inner end (closest to the die pad  74 ) and opposed side edges of each of the leads  76 . The package body  82  defines a generally planar top surface  84 , a generally planar bottom surface  86  which is typically substantially flush or continuous with the generally planar bottom surfaces of the leads  76  and die pad  74  of the leadframe  72 , and an angled or sloped outer surface  88  which extends between the top and bottom surfaces  84 ,  86 . In the semiconductor package  70 , the semiconductor die  78  and the conductive wires  80  are also covered by the package body  82 . 
     In fabricating the semiconductor package  70 , a solid base strip  90  which is preferably fabricated from copper is initially provided ( FIG. 7A ). The base strip  90  is subjected to a plating process wherein the die pad  74  and leads  76  of the leadframe  72  are formed on the generally planar top surface of the base strip  90  ( FIG. 7B ). More particularly, it is contemplated that the die pad  74  and leads  76  will be formed by plating up Au/Pd/Ni/Cu/Ni/Pd/Au to a total thickness in the range of approximately 50-200 microns. 
     Upon the completion of the plate up process to form the die pad  74  and leads  76  of the leadframe  72 , a die attach process is completed wherein the semiconductor die  78  is attached to the top surface of the die pad  74  ( FIG. 7C ). Thereafter, a wire bonding process is completed wherein the semiconductor die  78  is electrically connected to the top surfaces of one or more of the leads  76  through the use of the conductive wire(s)  80 . A molding process is then completed to facilitate the formation of the package body  82  upon the leadframe  72  and base strip  90  in the above-described manner ( FIG. 7D ). 
     Subsequent to formation of the package body  82 , the base strip  90  is subjected to a chemical etching process wherein a suitable chemical etchant is applied thereto. The etching may be performed using wet chemical or another etching technique. Wet etching can be performed using either immersion or spray methods. The application of the etchant to the base strip  90  effectively removes the same its entirety, thus completing the formation of the semiconductor package  70  ( FIG. 7E ). The metal material used to form the die pad  74  and leads  76  of the leadframe  72  and plastic material used to form the package body  82  are unaffected by the etchant used to remove the base strip  90 , thus resulting in the generally planar bottom surfaces of the die pad  74  and leads  76  being exposed in and substantially flush or continuous with the generally planar bottom surface  86  of the package body  82 . 
     Though the fabrication of only a single semiconductor package  70  is shown in  FIGS. 7A-7E , it is contemplated that the manufacturing process for the semiconductor package  70  as described above will be conducted in a manner adapted to facilitate the simultaneous formation of multiple semiconductor packages  70 . In this regard, the base strip  90  will be provided in a size sufficient to allow for the formation of multiple leadframes  72  thereon in the manner identical to that shown in  FIG. 6 . The subsequent assembly steps for the semiconductor packages  70  are completed in the same manner described above, the package bodies  82  being formed on corresponding leadframes  72  of the enlarged base strip  90 . The singulation step accomplished by the ultimate removal of the enlarged base strip  90  through the application of the chemical etchant thereto effectively separates the completed semiconductor packages  70  from each other. 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process, may be implemented by one skilled in the art in view of this disclosure.