Abstract:
Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a STI region and an active region. The approach also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The approach further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region.

Description:
[0001]    The invention relates to a method and test structure for capacitive measurement of a divot formed in semiconductor devices, and more particularly, to a method and test structure for inline signal divot monitoring for process control feedback. 
       BACKGROUND 
       [0002]    The trend in semiconductor device fabrication towards increasing density of circuit components requires that smaller areas of the circuit be devoted to isolation of the circuit components and capacitive storage devices. The need to reduce the surface area used for circuit components such as isolation structures and large area capacitor devices has resulted in the development of structures vertically oriented with respect to the plane of the substrate surface. These vertical structures typically consist of some type of trench structure in the semiconductor substrate and positioned between charge carrying components of adjacent transistors. The utilization of a trench structure enables the formation of a structure having large volume while minimizing the amount of surface area consumed. 
         [0003]    The formation of vertically oriented isolation structures does not eliminate the possibility of current leakage paths. Accordingly, various isolation techniques have been developed and are used in advanced integrated circuitry to electrically isolate the various devices in the semiconductor substrate. One example of such an isolation technique is shallow trench isolation (STI), which is used in IC chips to provide higher device densities and better planarity than other isolation methods. In this technique, a STI area is defined to form isolation trenches surrounded by areas of wafer having a pad oxide layer and a polish-stop nitride layer on the surface. The isolation trench is then thermally oxidized to form a thin oxide layer on the isolation trench surfaces. A thin nitride layer is often deposited inside the isolation trench surfaces to prevent stress during the subsequent oxidation steps because the stress causes dislocations in the silicon wafer. Then, the isolation trench is filled with a chemical vapor deposited (CVD) oxide and chemically mechanically polished (CMP) back to the polish-stop nitride layer to form a planar surface. The polish-stop nitride layer is then removed. At this time, if there is a nitride liner, exposed areas of the nitride liner are etched back as well, which creates a divot. Even without a nitride liner, a divot can still form in the gate surface adjacent to the silicon due to stress. The pad oxide is then removed by a wet etch, which may cause the divot to grow. The gate oxide is then grown on the silicon wafer surface, and hi-k dielectric gate material is deposited. When the dielectric gate material is deposited, it will fill the divot, causing extra capacitance and possibly generating an out of control “foot short”. If a foot short is generated due to a divot filled with gate material, yields may plummet. 
       SUMMARY 
       [0004]    In a first aspect of the invention, there is a method which includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a shallow trench isolation (STI) region and an active region. The method also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The method further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region. 
         [0005]    In another aspect of the invention, there is a test structure which includes a first contact at a first region where at least one gate line crosses over a boundary junction between a shallow trench isolation (STI) region and an active region of a substrate for measuring a first capacitance. The test structure also includes a second contact at a second region where at least one second gate line crosses over the active region of the substrate for measuring a second capacitance. 
         [0006]    In another aspect of the invention, there is a method which includes providing a first contact at a first region of a substrate where an outer pair of electrically connected gates crosses over a boundary junction between a shallow trench isolation (STI) region and an active region. The method further includes providing a second contact at a second region of the substrate where an inner pair of electrically connected gates cross over the active region. The method also includes measuring a first capacitance at the first contact and a second capacitance at the second contact. The method further includes calculating a divot capacitance of a divot location based on a different between the first capacitance at the first contact and the second capacitance at the second contact. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  shows a schematic view of a semiconductor structure with a divot that can be measured in accordance with aspects of the invention. 
           [0008]      FIG. 2  shows a top schematic view of  FIG. 1 . 
           [0009]      FIG. 3  shows an example of a foot short that can be measured in accordance with aspects of the invention. 
           [0010]      FIG. 4  shows a flow diagram of a method in accordance with aspects of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    The invention relates to a method and test structure for capacitive measurement of a divot formed in semiconductor devices, and more particularly, to a method and test structure for inline signal divot monitoring for process control feedback. In embodiments, the test structure can determine dimensions, e.g., measuring a depth-calibrated capacitive signal on the semiconductor device. 
         [0012]    More specifically, the present invention relates to a method and structure of determining a depth of a shallow trench isolation (STI) divot. The structure can be implemented using the method comprising providing an active silicon region surrounded by STI isolation and forming an inner pair of electrically connected gates crossing the active silicon region. The method further comprises forming an outer pair of electrically connected gates crossing the boundary between the STI and active silicon region, wherein the outer pair surrounds the inner pair. The method further comprises forming electrical contacts to the active silicon region between the inner pair of gates and the outer pair of gates respectively. The depth of the STI divot can be determined from a difference in measured gate capacitances from the inner gates to active silicon region and the outer gates to active silicon region at a set of voltages. In this way, unlike current destructive testing (e.g., TEM cross sections, cleave at wafer level, etc.), embodiments of the invention provide a non-destructive testing method, which includes providing an inline signal for divot monitoring and providing quick process control feedback. Further, embodiments of the invention allow for characterizing divot depth earlier in the manufacturing process than known methods and structures. Thus, embodiments of the invention allow for a test structure to be placed on the kerf of the semiconductor device to allow for an inline signal to determine divot depth. 
         [0013]      FIG. 1  shows a schematic view of a semiconductor device with a divot that can be measured in accordance with aspects of the invention. Specifically,  FIG. 1  shows a semiconductor device  10  which includes a substrate  100 , polysilicon (PC)  140   a  and  140   b  lines of gate material, and a divot  160 . For example, the substrate  100  may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Further, the substrate  100  comprises a RX region  120  (i.e., an active region) and a shallow trench isolation (STI) region  110  (i.e., an isolated region). Further, a STI boundary  130  is at an edge of the STI region  110  and the RX region  120 . PC  140   a  and  140   b  lines of gate material have a length Lpoly  150 , as shown in  FIG. 1 . 
         [0014]    In the semiconductor device of  FIG. 1 , the divot  160  may be formed during a number of different clean and etch processes (e.g., clean and etch processes can occur during a channel sige process). For example, the divot  160  may be formed when oxide is etched at a top corner of the STI boundary  130 . Further, the divot  160  may be filled with hi-k gate material or metal gate material during a deposition process. Other process steps, such as carbon implantation, may further erode the STI boundary  130 . However, since PFET and NFET have different vertical channel levels, overfilling the STI region  110  will not solve the erosion problem at the STI boundary  130 . As shown on the left side of  FIG. 1 , the STI boundary  130  is under a PC  140   b  in a tucked position. 
         [0015]    The length of the divot  160  may vary in different semiconductor devices, but is typically around 2-20 nm. In embodiments, any divot  160  below 5 nm is defined as a basic variation that is used as a reference point and will most likely occur when the PC  140  is completely over the RX region  120 , as shown on the right side of  FIG. 1 . Further, any divot  160  below 5 nm may not cause any shorts or yield problems during the semiconductor device manufacturing process. A divot  160  above 5 nm, which can be detected and measured, can form a metal stringer and form a short from the gate to source/drain contact region. If the divot  160  causes a short in semiconductor devices, yield rates will plummet. 
         [0016]    In any event, in order to determine a depth of a divot, first contact  210  and second contact  220  may be placed on the semiconductor device  10 . The first contact  210  and second contact  220  may each be a set of electrical contacts. Specifically, as shown in  FIG. 1 , the first contact  210  may be placed at a first region where a PC  140   b  line of gate material crosses over a STI boundary  130  between an edge of the STI region  110  and the RX region  120 . The first contact  210  may be used for measuring a first capacitance at the first region. Further, as shown in  FIG. 1 , the second contact  220  may be placed at a second region where a PC  140   a  line crosses over only the RX region  120 . The second contact  220  may be used for measuring a second capacitance at the second region. Moreover, the first contact  210  and second contact  220  may be part of a test structure for characterizing a divot depth. 
         [0017]    Although  FIG. 1  shows first contact  210  and second contact  220  placed directly in an active area on the semiconductor device  10 , alternate embodiments are included herein. For example, first contact  210  and second contact  220  may be placed on the kerf of the semiconductor product to allow for an inline signal to determine divot depth. 
         [0018]      FIG. 2  shows a top schematic view of the semiconductor device of  FIG. 1 , with the test structures implementing the measurements in accordance with aspects of the invention. In  FIG. 2 , PC  140   a  lines are completely covering the RX region  120 ; whereas, PC  140   b  lines only partially cover the RX region  120 . As shown in  FIG. 2 , the length of RX is L RX    170  and the width of RX is W RX    180 . Further, in embodiments, W RX    180  is greater than L RX    170 . In embodiments shown in  FIG. 2 , a first capacitance  200  (on the right side of  FIG. 2 ), in which two PC lines  140   b  partially cover the RX region  120 , is measured as C 1 . Further, a second capacitance  190  (on the left side of  FIG. 2 ), in which two PC  140   a  lines completely cover the RX region  120 , is measured as 2C 0 . On the right side of  FIG. 2 , the first capacitance  200  is measured as C 1  because the capacitance is approximated as ½ component for each PC  140   b  (i.e., only approximately half of each PC  140   b  covers the RX region  120 ). 
         [0019]    As shown in  FIG. 2 , the first contact  210  may be placed at a first region where a PC  140   b  line of gate material crosses over a STI boundary  130  between an edge of the STI region  110  (not shown) and the RX region  120 . The first contact  210  may be used for measuring the first capacitance  200  at the first region. Further, as shown in  FIG. 2 , the second contact  220  may be placed at a second region where a PC  140   a  line crosses over only the RX region  120 . The second contact  220  may be used for measuring the second capacitance  190  at the second region. The first contact  210  and second contact  220  may each be a set of electrical contacts. Moreover, first contact  210  and second contact  220  may be part of a test structure for characterizing a divot depth. 
         [0020]      FIG. 3  shows an example of a foot short which can be measured in accordance with aspects of the invention. In  FIG. 3 , for example, a fail region  300  of a device is illustrated with a TiN foot  310 . In  FIG. 3 , the divot in the fail region  300  of the device becomes an out of control “foot short”, which reduces yield of semiconductor devices. In this implementation, a test structure may be used to determine the depth of the out of control foot short. The test structure may include a first contact which is placed at a first region where a PC line of gate material crosses over a STI boundary between an edge of an STI region and an RX region. The test structure may also include a second contact which is placed at a second region where a PC line of gate material crosses over only the RX region. The first contact and second contact may be used for measuring a first capacitance at the first region and a second capacitance at the second region, respectively. Further, in another embodiment, the test structure may be placed on the kerf of a semiconductor device to allow for an inline signal to determine divot depth. 
         [0021]      FIG. 4  shows an exemplary flow diagram for performing aspects of the present invention. The steps of  FIG. 4  may be implemented on the structures shown in  FIGS. 1-3 . The flow diagram illustrates the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products as already described herein in accordance with the various embodiments of the present invention. 
         [0022]      FIG. 4  shows a flow diagram of a method in accordance with aspects of the invention. In  FIG. 4 , at step  400 , a first capacitance (e.g., the first capacitance  200  of  FIG. 2 , or C 1 ) of a PC (e.g., the PC  140   b  line of  FIG. 2 ) which is partially covering over RX (e.g., the RX region  120  of  FIG. 2 ) is measured by a first contact (e.g., a set of electrical contacts) at the first region. The first region is a region where a PC crosses over a STI boundary between an edge of a STI region and a RX region. Then, at step  405 , a second capacitance (e.g., the second capacitance  190  of  FIG. 2 , or  2 C 0 ) of a PC (e.g., the PC  140   a  line of  FIG. 2 ) which is completely covering over RX (e.g., the RX region  120  of  FIG. 2 ) is measured by a second contact (e.g., a set of electrical contacts) at a second region. The second region is a region where a PC line completely crosses over only the RX region. The measurements in Steps  400  and  405  are shown below, respectively: 
         [0000]      First Capacitance=Capacitance Measurement of 2 PC  that straddle boundary of  RX/STI  Junction= C 1. 
         [0000]      Second Capacitance=Capacitance Measurement of 2 PC  completely covering over  RX= 2 C 0. 
         [0023]    In  FIG. 4 , at step  410 , measurements for Lpoly are made and delta correction measurements are made for STI (L RX , L RX, target ). For example, if the STI region (e.g., the STI region  110  in  FIG. 1 ) is larger or smaller than an approximation of ½ component (i.e., STI region  110  in  FIG. 1  under PC  140   b  being larger or smaller than ½ component), delta corrections (i.e., adjustments) will have to be made to L RX . The measurements in step  410  are shown below, respectively: 
         [0000]      Delta Correction for Length of  RX=L   RX   L   RX,target . 
         [0000]      Length of  PC=L poly. 
         [0024]    In  FIG. 4 , at step  415 , divot capacitance (e.g., Cdivot) is calculated. At step  415 , there are several intermediate calculations that are made, including C 1   RX  and C 1 . The measurements in step  415  are shown below, respectively: 
         [0000]        C 1 RX =Portion of  C 1 over  RX=C 0+( L   RX   −L   RX,target )* C 0 /L poly. 
         [0000]        C 1= C 1 RX   +C divot= C 0+( L   RX   −L   RX,target )* C 0 /L poly+ C divot. 
         [0000]        C divot=Portion over  STI=C 1 −C 0−( L   RX   −L   RX,target )* C 0 /L poly.
 
         [0025]    In view of the above measurements and calculations, the divot capacitance (e.g., Cdivot) is measured. As described herein, the divot capacitance may be used to estimate divot depth because there is a correlation between divot capacitance and divot depth. 
         [0026]    In simulations, for an average FET, +1 nm gate length variation and +1/−1 nm spacer variation was provided. Further, divots greater than 5 nm can be detected above the background noise in accordance with the processes of the present invention. Moreover, when running simulations, Cdivot was calculated to be approximately 120 aF, the divot depth was calculated to be approximately 20 nm (i.e., gate signal is approximately 0.3 fF/um depending on the length). 
         [0027]    The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
         [0028]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.