Abstract:
A signal generator  600  includes oscillator circuitry for generating first and second signals having a selected phase relationship and an interpolator  610  for interpolating between a phase of the first signal and a phase of the second signal to generate a third signal having a phase between the phases of the first and second signals.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to electronic circuits and systems and in particular clock generation circuits, systems and methods employing phase interpolation. 
     2. Description of the Related Art 
     Many digital and mixed digital-analog circuits and systems operate from a set of clocks derived from a single master clock. Typically, these clocks are generated using a programmable phase-locked loop (PLL) including a phase detector, charge pump, loop filter, ring oscillator, frequency dividers, and associated control circuitry. However, notwithstanding their wide use, traditional PLLs are significantly limited in their capacity to generate signals with precise phase relationships. 
     Since many state-of-the-art circuits and system require the generation of clock signals with more precise phase relationships than those produced by traditional PLLs, new techniques are required. Among other things, circuits, systems and methods are needed for the generation of signals with precise phase relationships. Moreover, such circuits, systems and methods should be programmable with fine or very fine phase resolution. 
     SUMMARY OF THE INVENTION 
     According to one embodiment of the principles of the present invention, a signal generator is disclosed which includes oscillator circuitry for generating first and second signals having a selected phase relationship. An interpolator interpolates between the phase of the first signal and the phase of the second signal to generate a third signal having a phase between the phases of the first and second signals. 
     The principles of the present invention support the generation of clock signals having a more precise phase relationship than those produced by traditional phase locked loops. In addition to enhanced precision, the inventive principles are also embodied in circuits, systems and methods which allow phase programmability of a given signal with fine or very fine phase resolution. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a high level functional block diagram of an exemplary mass storage subsystem, such as a disk drive subsystem, suitable for describing preferred embodiments of the principles of the present invention; 
     FIG. 2 is a more detailed block diagram of read/write channel; 
     FIG. 3 is a timing diagram of an exemplary write operation; 
     FIG. 4 is a timing diagram illustrating the continuous power mode; 
     FIG. 5 shows an exemplary timing diagram of servo mode operation; 
     FIG. 6 is a more detailed functional block of write precompensation circuit block and its interconnection with the data synthesizer portion of synthesizer block; 
     FIG. 7A illustrates the preferred embodiment of oscillator which employs four oscillator stages (Osc 0 -Osc 3 ); 
     FIG. 7B A illustrates in particular detail a pair of stages, namely stages Osc 1  and Osc 2 ; 
     FIG. 8A illustrates that for each WPC phase Phi x , the currents output from taps  703   a,b  are passed to a cardinal switch; 
     FIG. 8B is a more detailed diagram of a selected one of the cardinal switches of FIG. 8A; 
     FIG. 9 shows each of these two currents being split is turn into 6 equal amplitude currents by a corresponding current splitter; and 
     FIG. 10 graphically depicts phase interpolation in accordance with the illustrated embodiment. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in FIGS. 1-10 of the drawings, in which like numbers designate like parts. 
     FIG. 1 is a high level functional block diagram of an exemplary mass storage subsystem, such as a disk drive subsystem  100 , suitable for describing preferred embodiments of the principles of the present invention. Mass storage system  100  operates in conjunction with a magnetic disk or platter which stores bits of data as a sequence of magnetic state transitions. Platter  101  stores one channel of data per side, with each side divided into concentric circles or tracks which are in turn divided into sectors. As platter  101  rotates on a spindle, a read/write head  102  attached to a moveable arm over the surfaces of the platter, read or write bits of data as a function of magnetic flux. Typically, data is stored in a sequence which includes a sector number, a gap, the actual data including an error correction code, followed by a gap and the sector number for the next sector. Data are typically stored using a run-length limited (RLL) code. 
     Analog data being transmitted to and from read/write head  102  pass through preamplifier  103  which amplifies the voltage of the respective signals. In turn, data being exchanged with read/write head  102  passes through a read/write channel  200 , which will be discussed further below in conjunction with FIG.  2 . Read/write channel  200  operates in conjunction with a disk drive controller  104 , and in some embodiments, additionally in conjunction with a microprocessor  105 . 
     The preferred embodiment of read/write channel is best described by considering the read, write and servo modes of operation and the detailed block diagram of FIG.  2 . 
     Consider first a typical write operation to platter  101 , as illustrated in the timing diagram of FIG.  3 . During the write operation, a data synthesizer clock generated in servo and data frequency synthesizers block  201  is used to time the transitions. Data and control signals are received from the disk controller through disk controller interface  202 . The inputs to disk controller interface  202  include a write gate (WG*) which enables the write data path, a read gate (RG) which enables the read data path and the servo gate (SG) which enables the servo read path. 
     When the write gate WG* transitions to a logic low, the data controller first writes a predetermined number of zeros equal to the preamble length minus the write path latency to controller interface  202 . Read/write channel  200  then outputs the preamble pattern to read/write head  102 . This is followed by a transmission to interface  202  by the disk controller of a data synch byte, followed by a number of placeholder bytes. Read/write channel  200  next writes the data synch mark (DSM) pattern through write precompensation interface  203   a , while ignoring the placeholder bytes received at its NRZ port from the disk controller. 
     The output port of write precompensation interface  203   a  includes a pair of pseudo-ECL differential analog outputs WDON and WDOP, and an associated write gate WG_PRE, for transmitting data to preamplifier  103 . 
     Following the synchronization bytes, disk controller  104  transfers the data bytes along with a pad through disk controller interface  202 . A data randomizer  204 , when enabled, randomizes the data received from the disk controller to equalize the probability of occurrence of worst-case pattern. The output from data randomizer  204  is passed to a an RLL encoder  205  for encoding before their transmission to read/write compensation circuitry  203 . In turn, write precompensation circuitry  203  includes a pseudo-ECL (PECL) write data interface for driving data to the write path through preamplifier  103 . 
     Write precompensation circuitry  203   a  adjusts the timing of the transfer of information to preamplifier  103  in response to the bit pattern output from the RLL encoder  205 . When bits are closely recorded on the media, the transitions of one bit can affect the preceding bit, causing the apparent time of the earlier bit to lengthen (that is, to shift). Write precompensation is used to correct for this nonlinear bit shift. To correct for the sift, the write precompensation circuit anticipates the shift based upon the pattern output from the RLL encoder  205 . Then, the timing of the rising and falling edges of the earlier bit is intentionally shifted so that, after the subsequent bit is written, the previous bit actually appears at the correct time. 
     Now consider an exemplary read operation from platter  101  through read/write channel  200  to disk controller  105 . During a disk read, the read byte clock (RCLK) output from interface  202  is used to clock data to disk controller  104  and additionally is used by disk controller  103  to generate the write byte clock (WCLK), used to clock data from the disk controller to interface  202  during a write. 
     Data from preamplifier  103  is received at the inputs (INP, INN) of a digitally controlled variable gain amplifier (VGA)  206 , under the control of gain control loop  207  and thermal asperity detector (TAD)  208 . VGA  206  maintains a constant signal amplitude at the inputs to the following analog-to-digital converter stage. 
     The output from VGA  206  is passed through MR asymmetry compensation (MRA) block, which compensates for typical distortions(asymmetries) that can occur with certain MR and GMR read heads. 
     After offset compensation is applied by summer  211 , the analog data is passed through tunable analog low pass filter (LPF)  212  which shapes the read-back signal being passed to the inputs of analog to digital converter  213 . In the preferred embodiment, analog to digital converter  213  is a 6-bit flash analog to digital converter which generates digital samples in response to the timing base provided by the data synthesizer. The digitized signal is then passed through a 10-tap digital finite impulse response (FIR) equalization filter  214 . Among other things, FIR filter  214  compensates for changing equalization needs from head to head and zone to zone. 
     Interpolated timing recovery (ITR) filter  215  shifts the phase of the samples output from FIR filter  214  using time varying coefficients which are generated a function of the current phase of the FIR filter output. ZPR block  216  is used to determine the initial phase used by ITR filter  215  using the first  16  valid samples output from A to D converter  213 . 
     Gain control loop  207  adjusts the VGA gain such that a constant amplitude signal is seen at the output of either A to D converter  213  or ITR filter  215 , as selected in register. Additionally, the output from A to D converter  213  can have a significant DC offset due to residual analog error in VGA  206 , offsets in low pass filter  212 , or offsets generated in A to D converter  213  itself. Offset control loop  209  cancels these offsets on a real time basis. 
     Both the gain control and offset control loops require information about the channel-bit sequence and/or polarity. This information is provided by setting the thresholds in slicer  218  such that the slicer admits +1 for non-negative samples and −1 for negative samples. Soft address mark detector  219  detects the soft address mark on platter  101  for performing an auto zero sequence. Additionally, soft address mark detector  219  is used at spin-up and to recover orientation after two or more servo sync mark detection failures. 
     A target sequence detector (DET)  220  reconstructs the channel bit stream from the analog filtered and digitally equalized samples output from ITR filter  215 . 
     The output from sequence detector  220  is switched to synch mark detector  221 . When a synch mark is detected, the signal FSMD* is asserted and transmitted to the disk controller. RLL decoder  222  decodes the read data being transmitted to disk drive control  104 . 
     Channel quality circuitry  223  measures the nature and quality of data passing through the channel such as sampling errors, pr 4  confidence metrics, detector residuals, and phase errors. Thermal asperity block  208  is provided to counter large transient dc offsets which are produced when an MR head encounters a physical obstruction at or near the surface of platter  101 . 
     In the preferred embodiment, the control loops of read/write channel  200  operate in either an acquisition mode or tracking mode. In the acquisition mode, which is automatically entered when valid samples become available after the signal at the RG* pin transitions active, the control loops are preferably programmed to respond quickly in order to allow fast acquisition. In the tracking mode, the control loops are preferably programmed to respond more slowly in order to minimize the effect of offset, gain, and phase errors. The change in response characteristics between the two modes is controlled by the switching of the loop filter coefficients. 
     In the servo mode of operation, read/write channel  200  operates in a manner similar to that described above for a read operation. An exemplary timing diagram of servo mode operation is shown in FIG.  5 . In this case, the operations controlled by the servo gate (SG) servo data decoder is used in place of RLL decoder  222 . Following synchronous servo data detection and decoding, asynchronous servo burst demodulation is performed. Servo burst area detector (DEMOD)  224  monitors the output of analog to digital converter  213  and detects servo burst amplitude by sampled area detection. The disk drive servo system uses the detected information for estimating fractional track position. Additionally, in the servo mode, the requisite clocks are generated by the servo frequency synthesizer of block  201 . Servo burst data is emitted on the 8-pin NRZ (UBUS) port in the servo mode. 
     Microprocessor interface  228  provides the interface to an external microprocessor, when used. The BUSMODE port is used to select between the Serial and Unified Bus (UBUS) interface modes. Interface  228  and disk controller interface  202  share an 8-bit unified bus interface UBUS in the UBUS mode. The UBUS port also provides the NRZ data interface to the disk controller as well as the address/data interface for the microprocessor. In the serial interface mode may be selected, the UBUS port is used exclusively as interface to the external disk controller. 
     The RD*/SDAT port exchanges address and data synchronized with the serial clock (SCLK) in the serial mode and receives a read strobe RD*, which, along with the chip select signal CS*, allowing internal registers to be accessed via the UBUS in the UBUSmode. Addresses on the UBUS are latched-in with the signal ALE. In the serial mode, the serial data enable signal SDEN enables the serial microcontroller interface. The reset signal RST* stops all read/write channel operations, deasserts all outputs and sets all bidirectional ports to a high impedance state. 
     With respect to the NRZ data interface, the RCLK pin receives a byte rate clock from the disk controller and is synchronous with data on the UBUS. When enabled, the ERR port allows read/write channel  200  to transmit error pointers to the disk controller. 
     FIG. 6 is a more detailed functional block of write precompensation circuit block  202  and its interconnection with the data synthesizer portion of synthesizer block  201 , shown generally at  600 . Write precompensation circuitry delays the writing of certain logic “1s” to counter nonlinear bit shifting which can occur, for example, when a “11” pattern is being written in d=0 RLL code. In this case, the second transition can be subjected to a nonlinear bit shift which is compensated for by WPC  203 . 
     In the preferred embodiment, the reference clock REFCLK is divided in block  601  by divisor N, which is set for a read operation in register  602   a  (N_R_D) and for a write operation in register  602   b  (N_W_D). The resulting frequency is passed to the phase detector (or alternatively a phase-frequency detector)  603  where it is compared against the frequency divided from block  604  in the feedback loop. The frequency dividend M is set for a read in register  605   a  (M_R_D) and for a write in register  605   b  (M_W_D). The frequency of the data clock is therefore:          F   OSC     =       M_D   N_D     ·     F   REF                              
     The output from phase detector is passed to loop filter  606 , which is also programmable in register, with register  607   a  (LOOPF_R_D) setting the read synthesizer update frequency and register  607   b  (LOOPF_W_D) setting the write synthesizer update frequency. The operating range of loop filter  606  is adjusted to match the update rate of phase detector  603 . 
     The Channel Data Rate operating range is controlled by CDR register  609 , which sets the center operating frequency of variable frequency oscillator  608 . Four phases are tapped from oscillator  608  and presented to interpolator  610 . Interpolator  610  and oscillator  609  will be discussed in further detail below, but generally interpolator  610  includes a reference interpolator cell and three programmable interpolator cells controlled by the contents of Delay Register set  611 . Depending on the mode and mapping selected, each data “1” is written from one of these interpolation (delay) cells. 
     The phases generated by interpolator  610  are sent to WPC controller  612 , which selects one phase to clock out the current data ENDATA received from the RLL decoder while accounting for non-linear bit shift. 
     FIG. 7A illustrates the preferred embodiment of oscillator  608  which employs four oscillator Stages (Osc 0 -Osc 3 )  701   a - 701   d . A pair of stages, namely stages Osc 1  and Osc 2  are shown in particular detail in FIG.  7 B. 
     At each pair of differential outputs (Out x +, OUT x −) of each stage  701  is a set of switched capacitors  702   a  or  702   b  which are used to set the Channel Data Rate (CDR)in accordance with the contents of CDR control register  609 . Each of the differential pair of stage outputs is associated with a set of voltage-to-current taps  703   a  or  703   b . As a result, each differential output voltage pair is converted to four differential current pairs Ioutx−&lt;y&gt; and Ioutx+&lt;y&gt;, where x is the stage number from 0 to 3 and y is the tap number from 0 to 3. 
     The four differential current pairs output from each stage  701  are equal in magnitude. The phase difference between the output currents of adjacent stages however is 180/n degrees, where n is the number of stages in the oscillator ring. In the present case, where the ring has four stages, the currents from adjacent stages differ in phase by 45 degrees. Hence, taking the currents Iout 0 &lt;y&gt; output from Stage  0  to be the reference (phase  0 ), currents Iout 1 &lt;y&gt; are shifted 45 degrees from the reference, currents Iout 2 &lt;y&gt; shifted 90 degrees from the reference, and currents Iout 3 &lt;y&gt; shifted 135 degrees from the reference. 
     For each WPC phase Phi Y , the currents output from taps  703   a,b  of each oscillator stage are passed to a corresponding cardinal switch  801 , one of which is shown in FIG.  8 A. Cardinal switches  801  select which of the outputs are used to accomplish the phase interpolation. For an N stage differential ring, the cardinal switches select between  2 N possible taps. 
     In FIG. 8A, where the clock phase Phi 1  is being generated, the differential current pair Ioutx+/−&lt; 1 &gt; is passed to the cardinal switch  801  inputs from the corresponding oscillator stages  701 . By programming corresponding registers WPC_PLUSy&lt; 3 : 0 &gt; and WPC_MINUSy&lt; 3 : 0 &gt;, two differential current pairs are selected as eveny+, eveny−, oddy+and oddy−, again where y is the clock phase number, are switched to weights  802 , and thereafter to comparator  803 . In the example shown in FIG. 8A, the corresponding cardinal switch  801  can select between taps Iout 0 /−&lt; 1 &gt; and Iout 2 +/−&lt; 1 &gt; to generate the even components eveny+/− and between taps Iout 1 +/−&lt; 1 &gt; and Iout 3 +/−&lt; 1 &gt; to generate the odd components odd+/−. 
     FIG. 8B is an electrical schematic diagram of the cardinal switches controlling one pair of voltage-to-current taps  702  at the output of oscillator stage  1 . Here, the corresponding tap from group  703   a  comprises a transistor  804   a  having a gate controlled by the -output from the oscillator stage and a resistor  805   a  for setting the current level. Similarly, the corresponding tap from group  703   b  comprises transistor  804   b , controlled by the +output from oscillator stage  1  and resistor  805   b . Transistors  806   a,b  comprise the cardinal switches, with signals Card 1 − and Card 1 + respectively selecting how currents from transistors  804   a,b  can be injected into nodes odd+ and odd−. 
     As shown in FIG. 9, each of these two currents is turn split into 6 equal-amplitude currents by a corresponding current splitter  901   a - 901   d . After splitting, the resulting currents are selectively switched by associated sets of weight switches  902   a - 902   d  to the inputs of summers  903   a  and  903   b . After summing, the resulting currents are converted back into a pair of differential voltages by circuit blocks  904   a  and  904   b  which then a appear at the inputs of comparator  803 . The output from comparator  905  is the clock signal of phase Phi Y  for the stage. 
     The interpolated phase of Phi Y  is directly proportional to the currents switched to the summers  903 . Phase interpolation is graphically depicted in FIG.  10 . Accordingly, consider for discussion purposes the case where Phi 1  is being generated by selecting the phase  1  currents from Stage  0  and Stage  1  (i.e. Iout 0 +/−&lt; 1 &gt; and Iout 1 +/−&lt; 1 &gt; through the corresponding switch  801 . Again, Stage  0  outputs currents at the reference phase of 0 degrees and Stage  1  currents with a phase shift of 45 degrees. Using weight switches  802 , the phase of Phi 1  can be stepped in approximately 7.5 degree increments in accordance with Table 1. It should be noted that unselected currents are simply dumped. 
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Number of 
                 Number of 
                 Number of 
                 Number of 
                   
               
               
                 Stage 0 
                 State 1 
                 Stage 0 
                 Stage 1 
               
               
                 Currents 
                 Currents 
                 Currents 
                 Currents 
               
               
                 Used 
                 Used 
                 Dumped 
                 Dumped 
                 Phase Phi1 
               
               
                   
               
             
             
               
                 0/6 
                 6/6 
                 6/6 
                 0/6 
                 45° 
               
               
                 1/6 
                 5/6 
                 5/6 
                 1/6 
                 37.5° 
               
               
                 2/6 
                 4/6 
                 4/6 
                 2/6 
                 30° 
               
               
                 3/6 
                 3/6 
                 3/6 
                 3/6 
                 22.5° 
               
               
                 4/6 
                 2/6 
                 2/6 
                 4/6 
                 15° 
               
               
                 5/6 
                 1/6 
                 1/6 
                 5/6 
                 7.5° 
               
               
                 6/6 
                 0/6 
                 0/6 
                 6/6 
                 0° 
               
               
                   
               
             
          
         
       
     
     Although the invention has been described with reference to a specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
     It is therefore, contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.