Abstract:
An amplifier is disclosed. In accordance with some embodiments of the present disclosure, an amplifier may comprise a differential pair comprising a first transistor and a second transistor, wherein the first transistor comprises a first portion and a second portion, a first compensation circuit comprising a first terminal coupled to the first portion of the first transistor and a second terminal coupled to the second transistor, and a second compensation circuit comprising a first terminal coupled to the second portion of the first transistor and a second terminal coupled to the second transistor and the second terminal of the first compensation circuit.

Description:
TECHNICAL FIELD 
     The present disclosure relates generally to electronic circuits and, more particularly, to frequency compensation of amplifiers. 
     BACKGROUND 
     Operational amplifiers are used in a wide variety of integrated circuit applications. For example, low-dropout (LDO) voltage regulators may include an amplifier as part of a scheme to provide a power supply from which other circuits may be powered. LDO voltage regulators typically implement an amplifier with a feedback loop. A critical performance parameter of circuits involving a feedback loop, including an LDO voltage regulator, is the stability of the feedback loop. In order to remain stable, a feedback loop must have a sufficient amount of phase margin at its unity gain frequency. Further, to ensure proper operation across a range of potential operating conditions, a sufficient amount of phase margin must be maintained across factors such as supply voltage, temperature, and semiconductor process variation. 
     SUMMARY 
     In accordance with some embodiments of the present disclosure, an amplifier may comprise a differential pair comprising a first transistor and a second transistor, wherein the first transistor comprises a first portion and a second portion, a first compensation circuit comprising a first terminal coupled to the first portion of the first transistor and a second terminal coupled to the second transistor, and a second compensation circuit comprising a first terminal coupled to the second portion of the first transistor and a second terminal coupled to the second transistor and the second terminal of the first compensation circuit. 
     Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a schematic diagram of an example voltage regulator; and 
         FIG. 2  illustrates a schematic diagram of an example amplifier with a multiple zero-pole pairs in one stage. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure may refer to the “size” of various types of transistors, including an n-type metal-oxide semiconductor field-effect transistor (NMOS), and a p-type metal-oxide semiconductor field-effect transistor (PMOS). Unless otherwise specified, the description of a transistor&#39;s size, as used herein, describes the size parameter that affects the transconductance of the transistor. For example, for PMOS and NMOS devices, “size” may refer to the width-to-length ratio of the gate and/or of the conducting channel of the device. Accordingly, a device that is described as being sized at a ratio as compared to another device may have a transconductance that is larger or smaller at that ratio as compared to the transconductance of the other device. 
     Further, the present disclosure may refer to a transistor as a “mirror” of another transistor. A transistor that “mirrors” another reference device may have a gate coupled to the gate of the reference device and a source that is coupled to the same node as the source of the reference device. Accordingly, the mirror device may be configured to source or sink a current that mirrors (i.e., duplicates) the current in the reference device at a ratio that is dependent on the respective sizes of the mirror device and the reference device. 
     Further, the term “equivalent” may be used to describe two or more currents or two or more voltage potentials that may be designed to be approximately equal to each other. Though they may be designed to be approximately equal to each other, “equivalent” voltages, “equivalent” currents, or other “equivalent” items may include some variation due to factors including, but not limited to, device matching imperfections, semiconductor processing imperfections, and/or imbalanced operating conditions. 
       FIG. 1  illustrates a schematic diagram of an example voltage regulator  100 . Voltage regulator  100  may include a voltage reference generator  110 , an amplifier  120 , an output transistor  130 , and a feedback network  140 . 
     Voltage reference generator  110  may generate a stable reference voltage at its output. In some embodiments, the voltage reference generator may comprise a bandgap circuit. In some embodiments, the voltage reference generator may include a zener diode and/or any other device or circuit suitable to output a stable reference voltage. The output of the voltage reference generator  110  may be coupled to a positive input terminal of amplifier  120 . Amplifier  120  may amplify the difference in the voltage potential between its positive input terminal and its negative input terminal. Output transistor  130  may have a gate coupled to the output of amplifier  120 . In some embodiments, output transistor  130  may be an NMOS transistor with a drain coupled to a high potential power supply, referred to herein as “VDD,” and a source coupled to a feedback network  140  and any load that may be coupled to the voltage regulator&#39;s  100  output (“V reg     —     out ”). In such embodiments, V reg     —     out  may equal the amplifier output voltage minus the gate-to-source voltage of output transistor  130 , and accordingly, output transistor  130  may be referred to as operating in source-follower mode. 
     Feedback network  140  may comprise a resistor  141  and a resistor  142 . Resistor  141  may be coupled from V reg     —     out  to a feedback node (“V fb ”), and resistor  142  may be coupled from V fb  to a low potential power supply, referred to herein as “GND.” V fb  may be coupled to the negative input terminal of amplifier  120 . Accordingly, amplifier  120  may drive the output transistor to a voltage potential such that V fb , coupled to the negative output terminal of amplifier  120 , may be approximately equivalent to the reference voltage at the positive input of amplifier  120 . Thus, V reg     —     out  may be driven to a voltage potential that may be represented by the following equation: 
               V     reg   ⁢           ⁢   _   ⁢           ⁢   out       ≈     Reference   ⁢           ⁢   Voltage   ×         R   141     +     R   142         R   142               
where R 141  represents the resistance of resistor  141 , and R 142  represents the resistance of resistor  142 .
 
     As described above, a critical performance parameter of circuits involving a feedback loop is the stability of the feedback loop, i.e., the feedback loop&#39;s phase margin at its unity gain frequency. To ensure stability across a range of potential operating conditions, a sufficient amount of phase margin must be maintained across factors such as supply voltage, temperature, and semiconductor process variation. For feedback loops in some integrated circuit applications, it may be desired to increase the open-loop phase around the unity gain frequency of a loop by implementing a zero-pole pair in order to improve that loop&#39;s phase margin. In some circuits, multiple zero-pole pairs may be desired to achieve a desired phase margin. However, traditional loop-compensation schemes require a separate amplifier stage to implement each zero-pole pair. Thus, in traditional loop-compensation schemes there are costs associated with implementing more than one zero-pole pair, including additional devices, current consumption, and layout area. 
       FIG. 2  illustrates a schematic diagram of an example amplifier  120  with a multiple zero-pole pairs in first stage  210 . Amplifier  120  may include an NMOS  10 , a first stage  210 , and a second stage  220 . NMOS  10  may have a source coupled to GND and a gate that may be coupled to its drain and further coupled to a reference current input, I ref . Accordingly, NMOS  10  may be referred to as being biased by the reference current received at the I ref  input, and the voltage potential at the gate of NMOS  10  may be used to drive the gates of other NMOS devices that mirror the current of NMOS  10 . 
     First stage  210  may include a split NMOS  11 , an NMOS  12 , a split NMOS  21 , an NMOS  22 , a PMOS  31 , and a PMOS  32 . Instances of transistors may include multiple individual transistors. For example, NMOS transistors may include multiple individual NMOS devices. For the purposes of this disclosure, one or more individual NMOS devices coupled to each other in parallel may be referred to as a “portion” of an NMOS. 
     In some embodiments, NMOS  11  may be split into two portions, NMOS  11   a  and NMOS  11   b . NMOS  11   a  may have a gate coupled to the gate of NMOS  10 , a source coupled to GND, and a drain coupled to path  61   a . Accordingly, NMOS  11   a  may mirror the reference current in NMOS  10 . NMOS  11   b  may have a gate coupled to the gate of NMOS  10 , a source coupled to GND, and a drain coupled to path  61   b . Accordingly, NMOS  11   b  may mirror the reference current in NMOS  10 . NMOS  11   a  may be sized at any suitable ratio as compared to the size of NMOS  11   b . Accordingly, the current of NMOS  11   a  may be at any suitable ratio as compared to the current of NMOS  11   b . In some embodiments, NMOS  11   a  and NMOS  11   b  may be configured to have equivalent sizes, and in such embodiments, NMOS  11   a  and NMOS  11   b  may accordingly have currents that are equivalent to each other. 
     NMOS  12  may be configured such that each individual NMOS device in NMOS  12  may be coupled together in parallel, i.e., their respective gates may be coupled together, their respective drains may be coupled together, and their respective sources may be coupled together. NMOS  12  may have a gate coupled to the gate of NMOS  10 , a source coupled to GND, and a drain coupled to path  62 . Accordingly, NMOS  12  may mirror the reference current in NMOS  10 . NMOS  12  may have a size that is equivalent to the total combined size of NMOS  11   a  and NMOS  11   b . Accordingly, NMOS  12  may sink a current from path  62  that is equivalent to the sum of the current that is sunk by NMOS  11   a  from path  61   a  and by NMOS  11   b  from path  61   b.    
     In some embodiments, NMOS  21  may be split into two portions, NMOS  21   a  and NMOS  21   b . NMOS  21   a  may have a gate coupled to the positive input terminal of amplifier  120 , a source coupled to the drain of NMOS  11   a  via path  61   a , and a drain coupled to the gate and drain of PMOS  31 . NMOS  21   b  may have a gate coupled to a positive input terminal of amplifier  120 , a source coupled to the drain of NMOS  11   b  via path  61   b , and a drain coupled to the gate and drain of PMOS  31 . NMOS  21   a  may be sized at any suitable ratio as compared to the size of NMOS  21   b . Accordingly, the current steered by NMOS  21   a  may be at any suitable ratio as compared to the current of NMOS  21   b . Further, the ratio of the size and current of NMOS  21   a  as compared to NMOS  21   b  may be equivalent to the ratio of the size and current of NMOS  11   a  as compared to NMOS  11   b . In some embodiments, NMOS  21   a  and NMOS  21   b  may be configured to have the same sizes as each other, and in such embodiments, NMOS  21   a  and NMOS  21   b  may accordingly be configured to steer equivalent currents. 
     NMOS  22  may be configured such that each individual NMOS device in NMOS  22  may be coupled together in parallel, i.e., their respective gates may be coupled together, their respective drains may be coupled together, and their respective sources may be coupled together. NMOS  22  may have a gate coupled to a negative input terminal of amplifier  120 , a source coupled to the drain of NMOS  12  via path  62 , and a drain coupled to the drain of PMOS  32 . NMOS  22  may have a size that is equivalent to the total combined size of NMOS  21   a  and NMOS  21   b . Accordingly, NMOS  22  may be configured to steer a current that is equivalent to the total combined currents of NMOS  21   a  and NMOS  21   b.    
     PMOS  31  may have a source coupled to VDD and a gate and a drain that may be coupled to each other and further coupled to the respective drains of NMOS  21   a  and NMOS  21   b . Accordingly, PMOS  31  may be biased by the sum of the currents in NMOS  21   a  and NMOS  21   b . PMOS  32  may have a source coupled to VDD and a gate coupled to the gate of PMOS  31 . Accordingly, PMOS  32  may be configured to mirror the current in PMOS  31 . 
     Compensation circuit  40  may have a first terminal coupled to the source of NMOS  21   a  and second terminal coupled to the source of NMOS  22 . In some embodiments, compensation circuit  40  may include a resistor  41  including a first terminal coupled to the source of NMOS  21   a  and a second terminal coupled to the source of NMOS  22 , and a capacitor  42  including a first terminal coupled to the source of NMOS  21   a  and a second terminal coupled to the source of NMOS  22 . 
     Compensation circuit  45  may have a first terminal coupled to the source of NMOS  21   b  and second terminal coupled to the source of NMOS  22 . In some embodiments, compensation circuit  45  may include a resistor  46  including a first terminal coupled to the source of NMOS  21   b  and a second terminal coupled to the source of NMOS  22 , and a capacitor  47  including a first terminal coupled to the source of NMOS  21   b  and a second terminal coupled to the source of NMOS  22 . 
     Second stage  220  may include an NMOS  13 , a PMOS  51 , a PMOS  52 , and a PMOS  53 . NMOS  13  may have a gate coupled to the gate of NMOS  10  and a source coupled to GND. Accordingly, NMOS  13  may be configured to mirror the reference current in NMOS  10 . PMOS  51  may have a source coupled to VDD, and a gate and a drain that may be coupled together and further coupled to the drain of NMOS  13 . Accordingly, PMOS  51  may be biased by current sunk by NMOS  13 . PMOS  52  may have a source coupled to VDD and a gate coupled to the gate of PMOS  51 . Accordingly, PMOS  52  may be configured to mirror the current of PMOS  51 . 
     PMOS  53  may have a source coupled to the drain of PMOS  52 , a drain coupled to GND, and a gate coupled to the drain of PMOS  32  and the drain of NMOS  22 , which may be the output of first stage  210 . Accordingly, PMOS  53  may be configured to operate in a source-follower mode, where the voltage potential at its source tracks the voltage potential at its gate plus the gate-to-source voltage of PMOS  53  at the current provided by PMOS  52 . Thus, the output of amplifier  120 , V out , which may be coupled to the source of PMOS  53 , may be equivalent to the output of the first stage  210  plus the gate-to-source voltage of PMOS  53 . 
     Referring back to the first stage  210 , the gate of NMOS  21  may be coupled to the positive input terminal of amplifier  120 , and the gate of NMOS  22  may be coupled to the negative input terminal of amplifier  120 . NMOS  21  and NMOS  22  may operate as a differential pair. For example, if the voltage at the gate of NMOS  21  is higher than the voltage at the gate of NMOS  22 , then the voltage at the source of NMOS  21   a  and the voltage at the source of NMOS  21   b  may be higher than the voltage at the source of NMOS  22 , and accordingly, current may flow across resistor  41  and resistor  46  from path  61   a  and path  61   b  to path  62 . Accordingly, NMOS  21  may steer more current than NMOS  22 . During such operation, the current mirrored and sourced by PMOS  32  may be larger than the drain current of NMOS  22 , and accordingly, the voltage potential at the drain of NMOS  22  (i.e., the output of first stage  210 ) may rise. Accordingly, the output of amplifier  120  may also rise and, via the feedback network  140  depicted in  FIG. 1 , the negative input of the amplifier may be forced to rise to a level approximately equivalent to the positive input terminal of amplifier  120 , and amplifier  120  may return to balanced operation. 
     Alternatively, if the voltage gate of NMOS  21  is lower than the voltage at the gate of NMOS  22 , then the voltage at the source of NMOS  21   a  and the voltage at the source of NMOS  21   b  may be lower than the voltage at the source of NMOS  22 , and accordingly, current may flow across resistor  41  and resistor  46  from path  62  to path  61   a  and path  61   b . During such operation, the current mirrored and sourced by PMOS  32  may be less than the drain current of NMOS  22 , and accordingly, the voltage potential at the drain of NMOS  22  (i.e., the output of first stage  210 ) may fall. Accordingly, the output of amplifier  120  may also fall and, via the feedback network  140  depicted in  FIG. 1 , the negative input of the amplifier may be forced to fall to a level approximately equivalent to the positive input terminal of amplifier  120 , and amplifier  120  may return to balanced operation. 
     For the example embodiment depicted in  FIG. 2 , the open-loop gain (OLG) of the amplifier can be described as: 
             OLG   ≈         R   141         R   142     +     R   141         ×     r   32     ⁢            r   22     ×     g     m   ⁢           ⁢   21       ×     (           r     11   ⁢   a       ⁢          r     21   ⁢   a               r     11   ⁢   a       ⁢            r     21   ⁢   a       +       R   41     ⁢          1     sC   42                   +         r     11   ⁢   b       ⁢          r     21   ⁢   b               r     11   ⁢   b       ⁢            r     21   ⁢   b       +       R   46     ⁢          1     sC   47                     )                 
where: R 141  represents the resistance of resistor  141 ; R 142  represents the resistance of resistor  142 ; r 32 ∥r 22  represents the impedance looking into the drain of PMOS  32  parallel to the impedance looking into the drain of NMOS  22 , i.e., the impedance at the output of the first stage  210 ; g m21  represents the transconductance of NMOS  21 , i.e., the total transconductance of NMOS  21   a  and NMOS  21   b ; r 11a ∥r 21a  represents the impedance looking into the drain of NMOS  11   a  parallel to the impedance looking into the source of NMOS  21   a ; R 41 ∥1/sC 42  represents the resistance of resistor  41  in parallel to the impedance of capacitor  42  as a function of frequency; r 11b ∥r 21b  represents the impedance looking into the drain of NMOS  11   b  parallel to the impedance looking into the source of NMOS  21   b ; and R 46 ∥1/sC 47  represents the resistance of resistor  46  in parallel to the impedance of capacitor  47  as a function of frequency.
 
     In amplifier  120 , compensation circuit  40  and compensation circuit  45  may provide frequency compensation to ensure that the loop formed by voltage regulator  100  has sufficient phase margin at its unity gain frequency to operate in a stable manner. Compensation circuit  40  may provide a first zero-pole pair at a first set of frequencies, and compensation circuit  45  may provide a second zero-pole pair at a second set of frequencies. Splitting NMOS  11  into two portions (NMOS  11   a  and NMOS  11   b ) and splitting NMOS  21  into two portions (NMOS  21   a  and NMOS  21   b ) may allow two zero-pole pairs to be implemented by compensation circuit  40  and compensation circuit  45  within first amplifier stage  120 . 
     Though the example embodiment illustrated in  FIG. 2  shows NMOS  11  and NMOS  21  as split into two portions to correspond to two compensation circuits  40  and  45 , NMOS  11  and NMOS  21  may be split into any suitable number of portions to correspond to any suitable number of compensation circuits. For example, in some embodiments, NMOS  11  and NMOS  21  may each be split into three or more portions to facilitate three or more compensation circuits. Consistent with the description above, the portions of NMOS  11  may be sized at any suitable ratio as compared to each other, and the portions of NMOS  21  may be sized at any suitable ratio as compared to each other, where the ratio of the NMOS  11  portions matches the ratio of the corresponding NMOS  21  portions. 
     Though the example embodiment illustrated in  FIG. 2  shows NMOS  11  and NMOS  21  as split into multiple portions to correspond to multiple compensation circuits  40  and  45 , the opposing branch of first stage  120  may be split into multiple portions to correspond to multiple compensation circuits. For example, in some embodiments, NMOS  11  and NMOS  21  may include a single portion while NMOS  12  and NMOS  22  are split into multiple portions corresponding to multiple compensation circuits. In such embodiments, the first terminals of the respective compensation circuits may each be coupled to the single source of the single portion of NMOS  21 , and the second terminals of the respective compensation circuits may be respectively coupled to the multiple sources of the multiple portions of NMOS  22 . 
     Further, in some embodiments, both branches of first stage  120  may be split into multiple portions to correspond to multiple compensation circuits. For example, in some embodiments, NMOS  11  and NMOS  21  as well as NMOS  12  and NMOS  22  may be split into multiple portions corresponding to multiple compensation circuits. In such embodiments, the first terminals of the respective compensation circuits may be respectively coupled to the multiple sources of the multiple portions of NMOS  21 , and the second terminals of the respective compensation circuits may be respectively coupled to the multiple sources of the multiple portions of NMOS  22 . 
     As described above, second stage  220  may include PMOS  53  configured to operate in source-follower mode. In the example embodiment illustrated in  FIG. 2 , second stage  220  may have a substantially insignificant impact on the open-loop gain of amplifier  120  because of the operation of PMOS  53  in source-follower mode with no substantially significant gain. Second stage  220  may, however, buffer the high gain of first stage  210  from a large capacitive load that may be coupled to the output, V out , of amplifier  120 , and thus may prevent the large capacitive load from generating a dominant pole. For example, referring back to  FIG. 1 , voltage regulator  100  may include an output transistor  130 , that may be configured with a large size capable or driving a large current load at the V reg     —     out  output. Accordingly, output transistor  130  may have a large gate capacitance. Driving the large gate capacitance of output transistor with a relatively low impedance source-follower PMOS  53  may push the pole caused by the large capacitance beyond the unity gain frequency of amplifier  120  where it does not substantially impact the stability of amplifier  120 . 
     Though the example embodiment illustrated in  FIG. 2  includes amplifier  120  including a second stage  220  with a low impedance output as described above, some embodiments of amplifier  120  may include a high impedance output. Such embodiments may include either a single stage with a high impedance output or multiple stages where the last stage may include a high impedance output. Such embodiments may be configured to drive a load with a large capacitance (e.g., output transistor  130 ) and may include a corresponding dominant pole at a frequency within the unity gain frequency of amplifier  120 . In such embodiments, the parameters affecting the dominant pole may be designed in conjunction with compensation circuit  40  and compensation circuit  45  such that the amplifier has sufficient phase margin at its unity gain frequency to maintain stable feedback loop operation. 
     Though the example embodiment illustrated in  FIG. 2  includes a first stage  210  including a NMOS current references (NMOS  11  and NMOS  12 ), an NMOS differential pair (NMOS  21  and NMOS  22 ), and a PMOS current mirror (PMOS  31  and PMOS  32 ), some embodiments may include a first stage including PMOS current references, a PMOS differential pair, and an NMOS current mirror, with multiple compensation circuits configured between the respective drains of the portions of the first differential pair PMOS and the drain of the second differential pair PMOS.