Abstract:
A differential amplifier for amplifying an input signal at a constant amplification rate regardless of fluctuation in the center voltage of the input signal. The differential amplifier includes a first differential pair operated when a complementary input signal is greater than or equal to an intermediate level between power supplies. A second differential pair is operated when the complementary input signal is less than or equal to an intermediate level of the power supplies. A current synthesizing circuit synthesizes output currents of the first and second differential pairs to generate output voltage. An output current offset circuit offsets a current corresponding to the output current of one of the differential pairs based on the complementary input signal so that the output voltage becomes the output current of one of the first and second differential pairs.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-048315, filed on Feb. 24, 2004, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor device, and more particularly, to a semiconductor device incorporating a rail-to-rail amplifier (differential amplifier) used as an interface circuit complying with IEEE 1394.b. 
     In an interface circuit complying with IEEE 1394.b, if the input voltage range is 0 to 3.0 V, for example, it is determined that a signal does not exist when an input signal has an amplitude of less than 80 mV, and determined that a signal exists when an input signal has an amplitude of 200 mV or greater. To satisfy such a specification, a rail-to-rail amplifier is used in an input stage circuit of an interface circuit. The rail-to-rail amplifier includes a differential pair operated when an input signal has a relatively high potential in an input voltage range and a further differential pair operated when an input signal has a low potential in the input voltage range. Thus, the rail-to-rail amplifier functions stably when an input voltage fluctuates between a high potential power supply and a low potential power supply. 
       FIG. 1  is a circuit diagram showing a prior art rail-to-rail amplifier (amp)  100 . An input differential pair is configured by n-channel MOS transistors Tr 1  and Tr 2 . An input signal Vin 1  is provided to the gate of the transistor Tr 1 , and an input signal Vin 2  is provided to the gate of the transistor Tr 2 . 
     Further, an input differential pair is configured by p-channel MOS transistors Tr 3  and Tr 4 . The input signal Vin 2  is provided to the gate of the transistor Tr 3 , and the input signal Vin 1  is provided to the gate of the transistor Tr 4 . Referring to  FIG. 3A , the input signals Vin 1  and Vin 2  are complementary signals having amplitudes of about, for example, 80 mV. 
     The sources of the transistors Tr 3  and Tr 4  are connected to a current source  1 , which is further connected to a power supply VDD. Accordingly, operation currents Ip 1  and Ip 2  corresponding to the input signals Vin 2  and Vin 1  flow through the transistors Tr 3  and Tr 4 , respectively. 
     The sources of the transistors Tr 1  and Tr 2  are connected to a current source  2 , which is further connected to a power supply Vss. The drain of the transistor Tr 1  is connected to the drain and gate of a p-channel MOS transistor Tr 5 . The source of the transistor Tr 5  is connected to the power supply VDD. The drain of the transistor Tr 2  is connected to the drain and gate of a p-channel MOS transistor Tr 6 . The source of the transistor Tr 6  is connected to the power supply VDD. Accordingly, operation currents In 1  and In 2  corresponding to the input signals Vin 1  and Vin 2  flow through the transistors Tr 1  and Tr 2 , respectively. 
     The gate of the transistor Tr 5  is connected to the gate of a p-channel MOS transistor Tr 7 . The source of the transistor Tr 7  is connected to the power supply VDD. The drain of the transistor Tr 7  is connected to the drain and gate of an n-channel MOS transistor Tr 9 . The drain of the transistor Tr 9  is connected to the drain of the transistor Tr 3 . The source of the transistor Tr 9  is connected to the power supply Vss. 
     The gate of the transistor Tr 6  is connected to the gate of a p-channel MOS transistor Tr 8 . The source of the transistor Tr 8  is connected to the power supply VDD. The drain of the transistor Tr 8  is connected to the drain and gate of an n-channel MOS transistor Tr 10 . The drain of the transistor Tr 10  is connected to the drain of the transistor Tr 4 . The source of the transistor Tr 10  is connected to the power supply Vss. 
     Accordingly, the transistors Tr 5  and Tr 7  and the transistors Tr 6  and Tr 8  perform a current mirror operation. The drain current of the transistor Tr 7  flows through the transistor Tr 9 , and the drain current of the transistor Tr 8  flows through the transistor Tr 10 . 
     Referring to  FIG. 2 , in the rail-to-rail amp  100 , when the center voltage of the input signals Vin 1  and Vin 2  is near the power supply VDD, the input differential pair configured mainly by the n-channel MOS transistors, or the transistors Tr 1  and Tr 2 , is operated. Current corresponding to the operation currents In 1  and In 2  associated with the transistors Tr 1  and Tr 2  flow through the transistors Tr 9  and Tr 10  as output currents Io 1  and Io 2 , respectively. 
     When the center voltage of the input signals Vin 1  and Vin 2  is near the power supply Vss, the input differential pair configured mainly by the p-channel MOS transistors, or the transistors Tr 3  and Tr 4 , is operated. Current corresponding to the operation currents Ip 1  and Ip 2  associated with the transistors Tr 3  and Tr 4  flow through the transistors Tr 9  and Tr 10  as the output currents Io 1  and Io 2 , respectively. 
     For example, based on the size of the transistors Tr 9  and Tr 10  and the size of other transistors, the amplification rate may be set to “2”. In such a case, when the rail-to-rail amp  100  is supplied with the input signals Vin 1  and Vin 2  having amplitudes of 80 mV as shown in  FIG. 3A , output signals Vout 1  and Vout  2  having amplitudes of 160 mV are output from the drains of the transistors Tr 9  and Tr 10 , respectively. In this manner, the transistors Tr 5  and Tr 7  (current mirror circuit), the transistors Tr 6  and Tr 8  (current mirror circuit), and the transistors Tr 9  and Tr 10  synthesize the operation current of each input differential pair and function as a current synthesizing circuit that generates the output voltages Vout 1  and Vout 2 . 
     As the center voltage of the input signals Vin 1  and Vin 2  approaches an intermediate level between the power supply VDD and the power supply Vss, the transistors Tr 1  and Tr 2  in addition to the transistors Tr 3  and Tr 4  are operated. Thus, the output currents Io 1  and Io 2  flowing through the transistors Tr 9  and Tr 10  increase. When the center voltage of the input signals Vin 1  and Vin 2  reach the intermediate level between the power supply VDD and the power supply Vss, the transistors Tr 1  and TR 2  and the transistors Tr 3  and Tr 4  are operated in a substantially saturated state. Thus, referring to  FIG. 2 , the maximum output currents Io 1  and Io 2  flow through the transistors Tr 9  and Tr 10 . In this case, the amplitudes of the output voltages increases to 320 mV, as shown in  FIG. 3C , even though the amplitudes of the input signals Vin 1  and Vin 2  is 80 mV. 
     In this manner, the amplification rate of the rail-to-rail amp  100  increases when the center voltage of the input signals Vin 1  and Vin 2  is near the intermediate level between the power supply VDD and the power supply Vss. Accordingly, in this case, even if the amplitudes of the input signals Vin 1  and Vin 2  are less than 80 mV, due to the increase in the amplitudes of the output voltages Vout 1  and Vout 2 , the circuit in the following stage may determine that a signal exists based on the output voltages Vout 1  and Vout 2  respectively corresponding to the input signals Vin 1  and Vin 2 , which are less than 80 mV. 
       FIG. 4  is a circuit diagram of an input stage circuit  200  which includes a means for suppressing output voltage fluctuation with respect to fluctuations of the center voltage of the input signals Vin 1  and Vin 2 . In the input stage circuit  200 , n-channel MOS transistors Tr 11  and Tr 12  configure an input differential pair, and p-channel MOS transistors Tr 13  and Tr 14  configure a further input differential pair. The transistors Tr 11  and Tr 12  are supplied with operation current from a current source  3 . The transistors Tr 13  and Tr 14  are supplied with operation current from a current source  4 . 
     Transistors Tr 15  to Tr 18  and resistors R 1  to R 4  configure an output circuit that synthesizes the operation currents of the input differential pairs and generate an output voltage Vout. The input stage circuit  200  further includes a tail current controller provided with an n-channel MOS transistor Tr 19  and a p-channel MOS transistor Tr 20 , each of which functions as a current switch, constant voltage sources  5  and  6 , and current mirror circuits  7  and  8 . The tail current controller suppresses fluctuation of the output voltage Vout relative to fluctuations in the power supply voltage of the input signals Vin 1  and Vin 2 . 
     The transistor Tr 20  is activated and the current mirror circuit  8  is operated when the center voltage of the input signals Vin 1  and Vin 2  reaches a level close to the power supply VDD. The size of n-channel MOS transistors Tr 21  and Tr 22 , which configure the current mirror circuit  8 , is set at 1:3. Thus, current that is three times greater than the drain current flowing through the transistor Tr 21  flows through the transistor Tr 22 , or the transistors Tr 11  and Tr 12 . 
     The transistor Tr 19  is activated and the current mirror  7  is operated when the center voltage of the input signals Vin 1  and Vin 2  reaches a level close to the power supply Vss. The size of p-channel MOS transistors Tr 23  and Tr 24 , which configure the current mirror circuit  7 , is set at 1:3. Thus, current that is three times greater than the drain current flowing through the transistor Tr 23  flows through the transistor Tr 24 , or the transistors Tr 13  and Tr 14 . Such operation levels the operation current flowing through the transistors Tr 11  to Tr 14  with respect to fluctuations in the center voltage of the input signals Vin 1  and Vin 2 . This suppresses fluctuation of the output voltage Vout. 
     Japanese Laid-Open Patent Publication No. 2002-43871 describes a rail-to-rail amp that prevents deficient operations resulting from fluctuations in the input signal and that suppresses fluctuation of the output voltage relative to fluctuations in the center voltage of the input signal if there is no potential difference between input signals provided to a differential pair. 
     SUMMARY OF THE INVENTION 
     In the rail-to-rail amp of  FIG. 1 , the amplitudes of the output voltages Vout 1  and Vout 2  fluctuate when the center voltage of the input signals Vin 1  and Vin 2  fluctuate between the power supply VDD and the power supply Vss. Accordingly, even if an input signal has an amplitude that should result in a determination that a signal does not exist, an increase in the amplitude of the output voltage would cause an input signal having that output voltage to result in a determination that a signal exists. 
     In the input stage circuit shown in  FIG. 4 , regardless of fluctuations in the center voltage of the input signals Vin 1  and Vin 2 , the operation current flowing through an input differential pair is leveled to suppress transconductance fluctuation. However, the size ratio of the transistors configuring the current mirror circuit is predetermined. Thus, the operation current flowing through the current mirror circuit cannot be completely leveled. Accordingly, fluctuations in the output voltage relative to fluctuations in the center voltage of the input signal cannot be completely suppressed. Further, the current supplied from the current mirror circuit to the input differential pair is set in accordance with the current value obtained when the center voltage of the input signals Vin 1  and Vin 2  is equal to the intermediate level of the power supplies VDD and Vss, that is, when the total sum of the operation currents flowing through the input differential pair is maximum. Accordingly, the operation current flowing through the input differential pair constantly increases. This increases current consumption. 
     Further, Japanese Laid-Open Patent Publication No. 2002-43871 does not describe suppressing amplitude fluctuations of the output voltage based on fluctuations of the voltage level of the input signal. 
     The present invention provides a differential amplifier that amplifies an input signal by a constant amplification rate regardless of fluctuations in the center voltage of the input signal. 
     One aspect of the present invention is a differential amplifier including a first differential circuit for generating a first operation current in response to an input signal. A second differential circuit generates a second operation current in response to the input signal. A current synthesizing circuit, connected to the first and second differential circuits, synthesizes the first and second operation currents and generates output voltage. An output current offset circuit, connected to the current synthesizing circuit, offsets a current corresponding to one of the first and second operation currents based on the input signal. 
     Another aspect of the present invention is a differential amplifier including a first differential circuit for generating a first operation current in response to an input signal. A second differential circuit generates a second operation current in response to the input signal. A current synthesizing circuit, connected to the first and second differential circuits, synthesizes the first and second operation currents and generates output voltage. A third differential circuit generates a third operation current corresponding to the second operation current in response to the input signal. A current supplying circuit, connected to the first differential circuit and the third differential circuit, supplies the first differential circuit with the third operation current and offsets the first operation current with the third operation current. 
     A further aspect of the present invention is a differential amplifier including a first differential circuit for generating a first operation current in response to an input signal. A second differential circuit generates a second operation current in response to the input signal. A current synthesizing circuit, connected to the first and second differential circuits, synthesizes the first and second operation currents and generates output voltage. A third differential circuit generates a third operation current corresponding to the first operation current in response to the input signal. A current supplying circuit, connected to the second differential circuit and the third differential circuit, supplies the second differential circuit with the third operation current and offsets the second operation current with the third operation current. 
     A further aspect of the present invention is a semiconductor device including a differential amplifier for amplifying an input signal. The differential amplifier includes a first differential circuit for generating a first operation current in response to the input signal. A second differential circuit generates a second operation current in response to the input signal. A current synthesizing circuit, connected to the first and second differential circuits, synthesizes the first and second operation currents and generates output voltage. An output current offset circuit, connected to the current synthesizing circuit, offsets a current corresponding to one of the first and second operation currents based on the input signal. 
     A further aspect of the present invention is a semiconductor device including a differential amplifier for amplifying an input signal. The differential amplifier includes a first differential circuit for generating a first operation current in response to the input signal. A second differential circuit generates a second operation current in response to the input signal. A current synthesizing circuit, connected to the first and second differential circuits, synthesizes the first and second operation currents and generates output voltage. A third differential circuit generates a third operation current corresponding to the second operation current in response to the input signal. A current supplying circuit, connected to the first differential circuit and the third differential circuit, supplies the first differential circuit with the third operation current and offsets the first operation current with the third operation current. 
     A further aspect of the present invention is a semiconductor device including a differential amplifier for amplifying an input signal. The differential amplifier includes a first differential circuit for generating a first operation current in response to the input signal. A second differential circuit generates a second operation current in response to the input signal. A current synthesizing circuit, connected to the first and second differential circuits, synthesizes the first and second operation currents and generates output voltage. A third differential circuit generates a third operation current corresponding to the first operation current in response to the input signal. A current supplying circuit, connected to the second differential circuit and the third differential circuit, supplies the second differential circuit with the third operation current and offsets the second operation current with the third operation current. 
     Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
         FIG. 1  is a circuit diagram of a rail-to-rail amp in the prior art; 
         FIG. 2  is a graph showing the relationship between the center voltage of an input signal and the operational current in the rail-to-rail amp of  FIG. 1 ; 
         FIG. 3A  is a chart showing an input voltage waveform; 
         FIGS. 3B and 3C  are charts showing an output voltage waveform; 
         FIG. 4  is a circuit diagram showing an input stage circuit in the prior art; 
         FIG. 5  is a circuit diagram of a differential amplifier according to a first embodiment of the present invention; and 
         FIG. 6  is a circuit diagram of a differential amplifier according to a second embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the drawings, like numeral are used for like elements throughout. 
     A differential amplifier (rail-to-rail amp)  300  according to a first embodiment of the present invention will now be discussed with reference to  FIG. 5 . The differential amplifier  300  is used as an interface circuit incorporated in a semiconductor device. Transistors Tr 1  to Tr 10  and current sources  1  and  2  are identical to those shown in  FIG. 1 . The output transistors Tr 9  and Tr 10 , which function as a current synthesizing circuit, are connected between an input differential pair, which is configured by the p-channel transistors Tr 3  and Tr 4 , and a power supply Vss (low potential power supply). The differential amplifier  300  includes an output current offset circuit, which maintains the output current flowing through the output transistors Tr 9  and Tr 10  at a constant value regardless of fluctuations in the center voltage of an input signal. The output current offset circuit includes p-channel MOS transistors Tr 31  and Tr 32  and a control signal generation circuit  11   a.    
     The source of the p-channel MOS transistor Tr 31  is connected to a power supply VDD (high potential power supply), and the drain of the transistor Tr 31  is connected to the drain of the transistor Tr 5 . Accordingly, the transistor Tr 31  is connected parallel to the transistor Tr 5 . The source of the p-channel MOS transistor Tr 32  is connected to the power supply VDD, and the drain of the transistor Tr 32  is connected to the drain of the transistor Tr 6 . Accordingly, the transistor Tr 32  is connected parallel to the transistor Tr 6 . 
     The gate of the transistor Tr 31  is provided with a control signal CL 1  from the control signal generation circuit  11   a . The gate of the transistor Tr 32  is provided with a control signal CL 2  from the control signal generation circuit  11   a . When the center voltage of the input signals Vin 1  and Vin 2  reaches the vicinity of an intermediate level between the power supplies VDD and Vss, this would increase the output currents Io 1  and Io 2  flowing through the output transistors Tr 9  and Tr 10 . The control signals CL 1  and CL 2  are generated to offset such current increase. 
     The control signal generation circuit  11   a  will now be discussed. The sources of p-channel MOS transistors Tr 33  and Tr 34  are connected to a current source  12 , which is further connected to the power supply VDD. The gate of the transistor Tr 33  is provided with the input signal Vin 2 , and the gate of the transistor Tr 34  is provided with the input signal Vin 1 . 
     The drain of the transistor Tr 33  is connected to the drain and the gate of an n-channel MOS transistor Tr 35  and to the gate of an n-channel MOS transistor Tr 37 . The sources of the transistors Tr 35  and Tr 37  are connected to the power supply Vss. The transistors Tr 35  and Tr 37  function as a current mirror circuit. The size of the transistor Tr 33  is substantially the same as that of the transistor Tr 3 . When the input signal Vin 2  is applied to the gates of the transistors Tr 3  and Tr 33 , an operation current Ipr 1 , which is substantially the same as the operation current Ip 1  flowing through the transistor Tr 3 , flows through the transistors Tr 33 , Tr 35 , and Tr 37 . 
     The drain of the transistor Tr 37  is connected to the drain and the gate of a p-channel MOS transistor Tr 38 . The source of the transistor Tr 38  is connected to the power supply VDD. Accordingly, the operation current Ipr 1  is supplied to the transistor Tr 37  from the transistor Tr 38  in accordance with the operation of the transistor Tr 37 . 
     The gate of the transistor Tr 38  is connected to the gate of the transistor Tr 31 . Accordingly, the gate voltage of the transistor Tr 38  is supplied as the control signal CL 1  to the transistor Tr 31 , and the transistors Tr 38  and Tr 31  perform a current mirror operation. Due to this configuration, when the operation current Ipr 1  flows through the transistor Tr 33  in response to the input signal Vin 2 , the current mirror operation of the transistors Tr 35  and Tr 37  causes the same operation current Ipr 1  to flow through the transistor Tr 38 . As a result, the current mirror operation of the transistors Tr 38  and Tr 31  cause an operation current Ipc 1 , which is substantially equivalent to the operation current Ipr 1 , to flow through the transistor Tr 31 . 
     The drain of the transistor Tr 34  is connected to the drain and the gate of an n-channel MOS transistor Tr 36  and to the gate of an n-channel MOS transistor Tr 39 . The sources of the transistors Tr 36  and Tr 39  are connected to the power supply Vss. The transistors Tr 36  and Tr 39  function as a current mirror circuit. The size of the transistor Tr 34  is substantially the same as that of the transistor Tr 4 . When the input signal Vin 1  is applied to the gates of the transistors Tr 4  and Tr 34 , an operation current Ipr 2 , which is substantially the same as the operation current Ip 2  flowing through the transistor Tr 4 , flows through the transistors Tr 34 , Tr 36 , and Tr 39 . 
     The drain of the transistor Tr 39  is connected to the drain and the gate of a p-channel MOS transistor Tr 40 . The source of the transistor Tr 40  is connected to the power supply. VDD. Accordingly, the operation current Ipr 2  is supplied to the transistor Tr 39  from the transistor Tr 40  in accordance with the operation of the transistor Tr 39 . 
     The gate of the transistor Tr 40  is connected to the gate of the transistor Tr 32 . Accordingly, the gate voltage of the transistor Tr 40  is supplied as the control signal CL 2  to the transistor Tr 32 , and the transistors Tr 40  and Tr 32  perform a current mirror operation. Due to this configuration, when the operation current Ipr 2  flows through the transistor Tr 34  in response to the input signal Vin 1 , the current mirror operation of the transistors Tr 36  and Tr 39  causes the same operation current Ipr 2  to flow through the transistor Tr 40 . As a result, the current mirror operation of the transistors Tr 40  and Tr 32  cause an operation current Ipc 2 , which is substantially equivalent to the operation current Ipr 2 , to flow through the transistor Tr 32 . 
     The transistors Tr 33  and Tr 34  function as an offset current generation circuit, and the control signal generation circuit  11   a  excluding the transistors Tr 33  and Tr 34 , that is, the transistors Tr 31 , Tr 32 , and Tr 35  to Tr 40  function as an offset current supplying circuit together with the transistors Tr 31  and Tr 32 . 
     The operation of the differential amplifier  300  will now be discussed. 
     When the center voltage of the input signals Vin 1  and Vin 2  is at the intermediate level between the power supply VDD and the power supply Vss, the input differential pair configured by the transistors Tr 1  and Tr 2  and the input differential pair configured by the transistors Tr 3  and Tr 4  operate in a saturated state. Further, the operation currents In 1  and In 2  of the transistors Tr 1  and Tr 2  and the operation currents Ip 1  and Ip 2  of the transistors Tr 3  and Tr 4  are saturated. 
     In this state, the operation currents Ipr 1  and Ipr 2  respectively flowing through the transistors Tr 33  and Tr 34  are saturated currents, and the same operation currents Ipr 1  and Ipr 2  respectively flow through the transistors Tr 38  and Tr 40 . As a result, the same operation currents Ipc 1  and Ipc 2  (offset current) respectively flow through the transistors Tr 31  and Tr 32 . The operation currents Ipc 1  and Ipc 2  are substantially the same as the operation currents In 1  and In 2  respectively flowing through the transistors Tr 1  and Tr 2 . This increases the potential at the gates of the transistors Tr 5  and Tr 7  (first current mirror circuit) and the gates of the transistors Tr 6  and Tr 8  (first current mirror circuit). Thus, drain current does not flow through each of the first current mirror circuits. As a result, only the operation current Ip 1 , which flows through the transistor Tr 3 , flows as the output current Io 1  through the transistor Tr 9 , which generates the output voltage Vout 1 . Further, only the operation current Ip 2 , which flows through the transistor Tr 4 , flows as the output current Io 2  through the transistor Tr 10 , which generates the output voltage Vout 2 . 
     When the center voltage of the input signals Vin 1  and Vin 2  decreases and becomes less than the intermediate level between the power supply VDD and the power supply Vss, the transistors Tr 33  and Tr 34  are maintained in a saturation range, currents substantially equal to the currents In 1  and In 2  flow through the transistors Tr 31  and Tr 32 , and null operation current flows through the transistors Tr 7  and Tr 8 . Accordingly, only the operation current Ip 1 , which flows through the transistor Tr 3 , flows as the output current Io 1  through the transistor Tr 9 . Further, only the operation current Ip 2 , which flows through the transistor Tr 4 , flows as the output current Io 2  through the transistor Tr 10 . 
     When the center voltage of the input signals Vin 1  and Vin 2  increases and becomes greater than the intermediate level between the power supply VDD and the power supply Vss, the transistors Tr 33  and Tr 34  are operated in a non-saturation range. Further, the transistors Tr 1  and Tr 2  are operated in a saturation range. As a result, operation currents Ipr 1  and Ipr 2  (i.e., operation currents Ipc 1  and Ipc 2 ), which are smaller than the operation currents In 1  and In 2  of the transistors Tr 1  and Tr 2 , respectively flow through the transistors Tr 33  and Tr 34  (i.e., transistors Tr 31  and Tr 32 ). Therefore, operation current (In 1 -Ipc 1 ) flows through the transistors Tr 7 , and operation current (In 2 -Ipc 2 ) flows through the transistor Tr 8 . Further, the operation currents Ip 1  and Ip 2  of the transistors Tr 3  and Tr 4  become substantially equal to the operation currents Ipc 1  and Ipc 2 , respectively. Accordingly, only the current that corresponds to the operation current In 1  flowing through the transistor Tr 1  flows as the output current Io 1  through the transistor Tr 9 . Further, only the current that corresponds to the operation current In 2  flowing through the transistor Tr 2  flows as the output current Io 2  through the transistor Tr 10 . 
     The differential amplifier  300  has the advantages described below. 
     (1) Even if the center voltage of the input signals Vin 1  and Vin 2  fluctuate in the range between the power supply VDD and the power supply Vss, the output currents Io 1  and Io 2  respectively corresponding to the operation currents In 1  and In 2  of the transistors Tr 1  and Tr 2  or the operation currents Ip 1  and Ip 2  of the transistors Tr 3  and Tr 4  flow through the output transistors Tr 9  and Tr 10 . Accordingly, the amplification rate of the output voltages Vout 1  and Vout 2  is maintained at a constant value regardless of the center voltage of the input signals Vin 1  and Vin 2 . 
     (2) When the center voltage of the input signals Vin 1  and Vin 2  is the intermediate level between the power supply VDD and the power supply Vss, the control signal generation circuit  11   a  and the operation of the transistors Tr 31  and Tr 32 , which are responsive to the control signals CL 1  and CL 2  from the control signal generation circuit  11   a , prevent the operation currents of the n-channel transistors Tr 1  and Tr 2  from flowing through the output transistors Tr 9  and Tr 10 . That is, the operation currents of the transistors Tr 1  and Tr 2  are offset by the operation currents Ipc 1  and Ipc 2  respectively flowing through the transistors Tr 31  and Tr 32 . This prevents the amplitude of the output voltage Vout 1  and Vout 2  from being increased. 
     (3) When the center voltage of the input signals Vin 1  and Vin 2  is less than the intermediate level between the power supply VDD and the power supply Vss, the operation currents of the transistors Tr 1  and Tr 2  are offset. Further, the output voltages Vout 1  and Vout 2  are generated based on only the operation currents Ip 1  and Ip 2  flowing through the p-channel side input differential transistors Tr 3  and Tr 4 . 
     (4) When the center voltage of the input signals Vin 1  and Vin 2  is greater than the intermediate level between the power supply VDD and the power supply Vss, the operation currents of the p-channel side input differential transistors Tr 3  and Tr 4  are offset. Further, the output voltages Vout 1  and Vout 2  are generated based on only the currents corresponding to the operation currents In 1  and In 2  flowing through the n-channel side input differential transistors Tr 1  and Tr 2 . 
     (5) The size of the p-channel MOS transistor and the size of the n-channel MOS transistor configuring the control signal generation circuit  11   a  are substantially equal to the size of the p-channel MOS transistors and the size of the n-channel MOS transistors excluding the output transistors Tr 9  and Tr 10 . Accordingly, a current offsetting operation is surly and easily performed. 
     (6) The operation currents Ipr 1  and Ipr 2  consumed by the control signal generation circuit  11   a  increases only when the center voltage of the input signals Vin 1  and Vin 2  fluctuates within a range from the power supply Vss to the intermediate level between the power supply VDD and the power supply Vss. This reduces current consumption in comparison with the prior art example shown in  FIG. 4 . 
       FIG. 6  is a circuit diagram of a differential amplifier (rail-to-rail amp)  400  according to a second embodiment of the present invention. In the second embodiment, a current synthesizing circuit is arranged between an n-channel side input differential pair and the power supply VDD. Further, an input differential pair of a control signal generation circuit  11   b  is configured by n-channel MOS transistors in correspondence with the current synthesizing circuit. 
     The sources of transistors Tr 1  and Tr 2  are connected to a current source  2 . The current source  2  is connected to a power supply Vss. The sources of transistors Tr 3  and Tr 4  are connected to a current source  1 . The current source  1  is connected to a power supply VDD. The drain of the transistor Tr 3  is connected to the drain and the gate of a p-channel MOS transistor Tr 40 . The source of the transistor Tr 40  is connected to the power supply Vss. The drain of the transistor Tr 4  is connected to the drain and the gate of an n-channel MOS transistor Tr 42 . The source of the transistor Tr 42  is connected to the power supply Vss. 
     The gate of the transistor Tr 40  is connected to the gate of an n-channel MOS transistor Tr 41 . The source of the transistor Tr 41  is connected to the power supply Vss. The drain of the transistor Tr 41  is connected to the drain and the gate of an output transistor Tr 44 , which is configured by a p-channel MOS transistor. The drain of the transistor Tr 44  is connected to the drain of the transistor Tr 1 , and the source of the transistor Tr 44  is connected to the power supply VDD. 
     The gate of the transistor Tr 42  is connected to the gate of an n-channel MOS transistor Tr 43 . The source of the transistor Tr 43  is connected to the power supply Vss. The drain of the transistor Tr 43  is connected to the drain and the gate of an output transistor Tr 45 , which is configured by a p-channel MOS transistor. The drain of the transistor Tr 45  is connected to the drain of the transistor Tr 2 , and the source of the transistor Tr 45  is connected to the power supply VDD. 
     The pair of the transistors Tr 40  and Tr 41  and the pair of the transistors Tr 42  and Tr 43  each perform a current mirror operation. The drain current of the transistor Tr 41  flows through the transistor Tr 44 . The drain current of the transistor Tr 43  flows through the transistor Tr 45 . Output voltages Vout 1  and Vout 2  are respectively output from the drains of the transistors Tr 44  and Tr 45 . 
     An output current offset circuit configured by n-channel MOS transistors Tr 46  and Tr 47  and the control signal generation circuit  11   b  will now be discussed. 
     The source of the n-channel MOS transistor Tr 46  is connected to the power supply Vss. The drain of the transistor Tr 46  is connected to the drain of the transistor Tr 40 . Accordingly, the transistor Tr 46  is connected parallel to the transistor Tr 40 . The source of the n-channel MOS transistor Tr 47  is connected to the power supply Vss. The drain of the transistor Tr 47  is connected to the drain of the transistor Tr 42 . Accordingly, the transistor Tr 47  is connected parallel to the transistor Tr 42 . The gate of the transistor Tr 46  is provided with a control signal CL 3 , which is generated by the control signal generation circuit  11   b . The gate of the transistor Tr 47  is provided with a control signal CL 4 , which is generated by the control signal generation circuit  11   b.    
     In the control signal generation circuit  11   b , the sources of n-channel MOS transistors Tr 48  and Tr 49  are each connected to a current source  13 . The current source  13  is connected to the power supply Vss. The gate of the transistor Tr 48  is provided with an input signal Vin 1 . The gate of the transistor Tr 49  is provided with an input signal Vin 2 . 
     The drain of the transistor Tr 48  is connected to the drain and the gate of a p-channel MOS transistor Tr 50  and to the gate of a p-channel MOS transistor Tr 52 . The sources of the transistors Tr 50  and Tr 52  are connected to the power supply VDD. Accordingly, the transistors Tr 50  and Tr 52  operate as a current mirror circuit. Further, the size of the transistor Tr 48  is the same as that of the transistor Tr 1 . In response to the input signal Vin 1 , operation current Inr 1 , which is substantially equivalent to the operation current In 1  that flows through the transistor Tr 1 , flows through the transistors Tr 48 , Tr 50 , and Tr 52 . 
     The drain of the transistor Tr 52  is connected to the drain and the gate of an n-channel MOS transistor Tr 53 . The source of the transistor Tr 53  is connected to the power supply Vss. Accordingly, based on the operation of the transistor Tr 52 , the operation current Inr 1  flows from the transistor Tr 52  to the transistor Tr 53 . The gate of the transistor Tr 53  is connected to the gate of the transistor Tr 46 . Thus, the gate voltage of the transistor Tr 53  is provided as the control signal CL 3  to the gate of the transistor Tr 46 , and the transistors Tr 53  and Tr 46  perform a current mirror operation. 
     When the operation current Inr 1  flows through the transistor Tr 48  in response to the input signal Vin 1 , the current mirror operation of the transistors Tr 50  and Tr 52  cause the same operation current Inr 1  to flow through the transistor Tr 53 . Then, the current mirror operation of the transistors Tr 53  and Tr 46  cause the operation current Inc 1 , which is substantially the same as the operation current Inr 1 , to flow through the transistor Tr 46 . 
     The drain of the transistor Tr 49  is connected to the drain and the gate of a p-channel MOS transistor Tr 51  and to the gate of a p-channel MOS transistor Tr 54 . The sources of the transistors Tr 51  and Tr 54  are connected to the power supply VDD. Accordingly, the transistors Tr 51  and Tr 54  operate as a current mirror circuit. Further, the size of the transistor Tr 49  is the same as that of the transistor Tr 2 . In response to the input signal Vin 2 , operation current Inr 2 , which is substantially equivalent to the operation current In 2  that flows through the transistor Tr 2 , flows through the transistors Tr 49 , Tr 51 , and Tr 54 . 
     The drain of the transistor Tr 54  is connected to the drain and the gate of an n-channel MOS transistor Tr 55 . The source of the transistor Tr 55  is connected to the power supply Vss. Accordingly, based on the operation of the transistor Tr 54 , the operation current Inr 2  flows from the transistor Tr 54  to the transistor Tr 55 . The gate of the transistor Tr 55  is connected to the gate of the transistor Tr 47 . Thus, the gate voltage of the transistor Tr 55  is provided as the control signal CL 4  to the gate of the transistor Tr 47 , and the transistors Tr 55  and Tr 47  perform a current mirror operation. 
     When the operation current Inr 2  flows through the transistor Tr 49  in response to the input signal Vin 2 , the current mirror operation of the transistors Tr 51  and Tr 54  cause the same operation current Inr 2  to flow through the transistor Tr 55 . Then, the current mirror operation of the transistors Tr 55  and Tr 47  cause operation current Inc 2 , which is substantially the same as the operation current Inr 2 , to flow through the transistor Tr 47 . 
     The transistors Tr 50  and Tr 51  function as an offset current generation circuit, and the control signal generation circuit  11   b  excluding the transistors Tr 50  and Tr 51 , that is, the transistors Tr 48 , Tr 49 , and Tr 52  to Tr 55  function as an offset current supplying circuit together with the transistors Tr 46  and Tr 47 . 
     The operation of the differential amplifier  400  will now be discussed. 
     When the center voltage of the input signals Vin 1  and Vin 2  is at the intermediate level between the power supply VDD and the power supply Vss, the input differential pair configured by the transistors Tr 1  and Tr 2  and the input differential pair configured by the transistors Tr 3  and Tr 4  operate in a saturated state. Further, the operation currents In 1  and In 2  of the transistors Tr 1  and Tr 2  and the operation currents Ip 1  and Ip 2  of the transistors Tr 3  and Tr 4  are saturated. 
     In this state, the operation currents Inr 1  and Inr 2  respectively flowing through the transistors Tr 48  and Tr 49  become saturated currents, and the same operation currents Inr 1  and Inr 2  respectively flow through the transistors Tr 53  and Tr 55 . As a result, the same operation currents Inc 1  and Inc 2  (offset current) respectively flow through the transistors Tr 47  and Tr 46 . The operation currents Inc 1  and Inc 2  are substantially the same as the operation currents Ip 1  and Ip 2  respectively flowing through the transistors Tr 3  and Tr 4 . This decreases the potential at the gates of the transistors Tr 40  and Tr 41  and the gates of the transistors Tr 42  and Tr 43 . Thus, drain current does not flow through each of the transistors. As a result, only the operation current In 1 , which flows through the transistor Tr 1 , flows as the output current Io 1  through the transistor Tr 44 . Further, only the operation current In 2 , which flows through the transistor Tr 2 , flows as the output current Io 2  through the transistor Tr 45 . 
     When the center voltage of the input signals Vin 1  and Vin 2  increases and becomes greater than the intermediate level between the power supply VDD and the power supply Vss, the transistors Tr 48  and Tr 49  are maintained in a saturation range, currents substantially equal to the currents Ip 1  and Ip 2  flow through the transistors Tr 46  and Tr 47 , and null operation current flows through the transistors Tr 41  and Tr 43 . Accordingly, only the operation current In 1 , which flows through the transistor Tr 1 , flows as the output current Io 1  through the transistor Tr 44 . Further, only the operation current In 2 , which flows through the transistor Tr 2 , flows as the output current Io 2  through the transistor Tr 45 . 
     When the center voltage of the input signals Vin 1  and Vin 2  becomes less than the intermediate level between the power supply VDD and the power supply Vss and the transistors Tr 48  and Tr 49  are operated in a non-saturation range, the transistors Tr 3  and Tr 4  are operated in a saturation range. As a result, operation currents Inr 1  and Inr 2  (i.e., operation currents Inc 1  and Inc 2 ), which are smaller than the operation currents Ip 1  and Ip 2  of the transistors Tr 3  and Tr 4 , respectively flow through the transistors Tr 48  and Tr 49  (i.e., the transistors Tr 46  and Tr 47 ). Therefore, operation current (Ip 1 -Inc 1 ) flows through the transistors Tr 41 , and operation current (Ip 2 -Inc 2 ) flows through the transistor Tr 43 . Further, the operation currents In 1  and In 2  of the transistors Tr 1  and Tr 2  become substantially equal to the operation currents Inc 1  and Inc 2 , respectively. Accordingly, only the current that corresponds to the operation current Ip 1  flowing through the transistor Tr 3  flows as the output current Io 1  through the transistor Tr 44 . Further, only the current that corresponds to the operation current Ip 2  flowing through the transistor Tr 4  flows as the output current Io 2  through the transistor Tr 45 . 
     Due to such operations, the differential amplifier  400  has the same advantages as the differential amplifier  300  of the first embodiment. 
     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, the differential amplifiers  300  and  400  of the above embodiments may be configured by bipolar transistors. Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.