Abstract:
Disclosed is a test system having circuitry for reducing off-chip driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit chip. The integrated circuit chip has a plurality of input terminals for receiving an electrical test pattern from the tester. The integrated circuit chip also includes a plurality of output driver circuits having outputs connected to the tester. The test system is characterized in that the integrated circuit chip includes a driver sequencing network under control of the tester for sequentially conditioning the off-chip driver circuits for possible switching.

Description:
BACKGROUND OF THE INVENTION 
     1. Related U.S. Patent Application 
     U.S. patent application Ser. No. 540,072 Oct. 7, 1983, now U.S. Pat. No. 4,553,043, entitled &#34;Oscillation Prevention During Testing of Integrated Circuit Logic Chips&#34; by C. W. Cha, granted Nov. 12, 1985 as U.S. Pat. No. 4,553,049. 
     2. Technical Field 
     This invention relates to testing of integrated circuit logic chips and more particularly to excessive noise (Delta I) prevention during the testing thereof. 
     During application of functional test patterns on VLSI devices electrical noise is generated on either the power supply or I/O lines such that the internal logic state of the device becomes unpredictable and the test measurement fails. Electrical noise of significant magnitude is generated in two fashions by the switching of off chip drivers as more fully described below. 
     When many off chip drivers switch simultaneously a large change in power supply current results (delta I). This delta I current path flows from the driver output wire, through the driver, through the unbypassed inductance and resistance of the power supply distribution network, through the bypass capacitor and back to the tester ground. The voltage that is generated across the unbypassed inductance and resistance is expressed as follows, V=LdI/dt+RdI, where V is the generated voltage, L is the unbypassed inductance, R is resistance, dI is delta I and dI/dt is the rate of change of the current I with respect to time. DI and dI/dt relate directly to the driver type and the number of drivers concurrently switching, as does the noise magnitude. 
     Voltage and Current signals which change as a driver changes state also couple through mutual inductance and mutual capacitance into nearby I/O paths. Mutual inductance and mutual capacitance coupling may contribute, or solely, result in false switching and test failures. The voltage and current due to coupling is expressed by the equations V=MdI/dt and I=CdV/dt, where M is the mutual inductance, C is the mutual capacitance between the paths, and dV/dt is the rate of change of voltage with respect to time. Again the noise magnitude relates directly to the driver type (speed) and the number of drivers coupling noise into a nearby I/O path. 
     Alternative Solutions: 
     (A) Modify the tester. This has been done. However sophisticated electrical noise still appears. The product design cycle is fast outstripping the testers ability to compensate. 
     (B) Pre-Charge Output Lines. This technique allows as many drivers to switch as the pattern dictates, but does not allow them to switch until the tester precharges all of the output lines to their expected state before switching occurs. Once switched, each output termination by the tester must be returned to its proper value before the outputs can be measured. This method is useful, but has three main drawbacks: 
     (1) Test time increases considerably; (2) 
     The performance and real estate overhead is high for the chip designer; (3) The expected output states must be known at the time of execution of each pattern. This is inconsistent with the self test philosophy which logs output states for each pattern and compares them to expected states long after pattern execution is complete. 
     (C) Test pattern control of the number of outputs switching--This assumes the part number will allow itself to be limited to a specific number of drivers switching and still be able to achieve greater than 99.5% test coverage. The greater problem however, is that the simulator must apply patterns in the exact fashion the tester employs them. Most test machines apply all input changes serially which would cause excessive simulation time for software control of driver switching. 
     (D) The employment of an on-chip (or device contained) Driver Sequencing Network in accordance with applicants&#39; invention is fully disclosed hereinafter. 
     Reference is made to U.S. Pat. No. 4,441,075 entitled &#34;Electric Chip-In Place Test (ECIPT) Structure and Method&#34; granted Apr. 3, 1984 to P. Goel et al. The specification and drawings of U.S. Pat. No. 4,441,075 is incorporated herein by reference to the full and same extent as though it was incorporated herein word for word. 
     3. Prior Art 
     A number of test techniques, testers and test circuitry for testing integrated circuit devices are known to the art. It is to be appreciated with reference to the subject invention, that the following art is not submitted to be the only prior art, the best prior art, or the most pertinent prior art. 
     BACKGROUND ART 
     U.S. Patents 
     U.S. Pat. No. 3,599,161 entitled &#34;Computer Controlled Test System And Method&#34; granted Aug. 10, 1971 to A. M. Stoughton et al. 
     U.S. Pat. No. 3,694,632 entitled &#34;Automatic Test Equipment Utilizing A Matrix of Digital Differential Analyzer Integrators To Generate Interrogation Signals&#34; granted Sept. 26, 1972 to D. J. Bloomer. 
     U.S. Pat. No. 3,784,910 entitled &#34;Sequential Addressing Network Testing System&#34; granted Jan. 8, 1974 to T. P. Sylvan. 
     U.S. Pat. No. 3,848,188 entitled &#34;Multilayer Control System For A Multi-Array Test Probe Assembly&#34; granted Nov. 12, 1974 to F. J. Ardezzone et al. 
     U.S. Pat. No. 3,873,818 entitled &#34;Electronic Tester For Testing Devices Having A High Circuit Density&#34; granted Mar. 25, 1975 to J. D. Barnard. 
     U.S. Pat. No. 3,924,144 entitled &#34;Method For Testing Logic Chips and Logic Chips Adapted Therefor&#34; granted Dec. 2, 1975 to G. Hadamard. 
     U.S. Pat. No. 3,961,251 entitled &#34;Testing Embedded Arrays&#34; granted June 1, 1976 to W. J. Hurley et al. 
     U.S. Pat. No. 3,976,940 entitled &#34;Testing Circuit&#34; granted Aug. 24, 1976 to Y. B. Chau. 
     U.S. Pat. No. 4,066,882 entitled &#34;Digital Stimulus Generating And Response Measuring Means&#34; granted Jan. 3, 1978 to C. M. Esposito. 
     U.S. Pat. No. 4,070,565 entitled &#34;Programmable Tester Method And Apparatus&#34; granted Jan. 24, 1978 to R. N. Borrell. 
     U.S. Pat. No. 4,125,763 entitled &#34;Automatic Tester For Microprocessor Board&#34; granted Nov. 14, 1978 to R. B. Drabing et al. 
     U.S. Pat. No. 4,180,203 entitled &#34;Programmable Test Point Selector Circuit&#34; granted Dec. 25, 1979 to H. M. Masters. 
     U.S. Pat. No. 4,216,539 entitled &#34;In-Circuit Digital Tester&#34; granted Aug. 5, 1980 to D. W. Raymond et al. 
     U.S. Pat. No. 4,298,980 entitled &#34;LSI Circuitry Comforming to Sensitive Scan Design (LSSD) Rules and Method of Testing Same&#34; granted Nov. 3, 1981 to J. Hajder et al. 
     U.S. Pat. No. 4,334,310 entitled &#34;Noise Suppressing BiLevel Data Signal Driver Circuit Arrangement&#34; granted June 8, 1982 to G. A. Maley. 
     U.S. Pat. No. 4,348,759 entitled &#34;Automatic Testing Of Complex Semiconductor Components With Test Equipment Having Less Channels Than Those Required by The Component Under Test&#34; granted Sept. 7, 1982 to H. D. Schnurmann. 
     U.S. Pat. No. 4,398,106 entitled &#34;On-Chip Delta-I Noise Clamping Circuit&#34; granted Aug. 9, 1983 to E. E. Davidson et al. 
     U.S. Pat. No. 4,441,075 entitled &#34;Electrical Chip-In-Place Test (ECIPT) Structure &amp; Method&#34; granted Apr. 3, 1984 to P. Goel et al. 
     U.S. Pat. No. 4,494,066 entitled &#34;Method of Electrically Testing a Packaging Structure Having N Interconnected Integrated Circuit Chips&#34; granted Jan. 15, 1985 to P. Goel et al. 
     U.S. Pat. No. 4,504,784 entitled &#34;Method Of Electrically Testing A Packaging Structure Having N Interconnected Integrated Circuit Chips&#34; granted Mar. 12, 1985 to P. Goel et al. 
     IBM Technical Disclosure Bulletin Publications 
     &#34;Logic Structure For Testing Tri-State Drivers&#34; by S. DasGupta and C. E. Radke, Vol. 21, No. 7, Dec. 1978, pages 2796-7. 
     &#34;Driver Power Distribution&#34; by A. E. Barish and R. Ehrlickman, Vol. 22, No. 11, Apr. 1980, pages 4935-7. 
     &#34;Functionally Independent A.C. Test For Multi-Chip Package&#34; by P. Goel and M. T. McMahon, Vol. 25, No. 5, October 1982, pages 2308-10. 
     &#34;Chip Partitioning Aid&#34; by M. C. Graf and R. A. Rasmussen, Vol. 25, No. 5, October 1982, pages 2314-5. 
     &#34;Driver Sequencing Circuit&#34; by D. C. Banker, F. A. Montegari and J. P. Norsworthy, Vol. 26, No. 7B, December 1983, pages 3621-2. 
     SUMMARY OF THE INVENTION 
     The Invention may be summarized as a driver sequencing network on the device, or chip, to be tested which gives the tester (machine) control of the timing between the switching of groups of driver circuits so that more than a predetermined number of driver circuits concurrently switching state is precluded. The driver sequencing network is such that no one group of driver output pins can create enough delta I or coupled noise to cause a test failure. The driver sequencing network may be disabled to give full control of the driver outputs to the device being tested. In a normal application, i.e. intended purpose, or function of the device, the driver sequencing network is disabled. The function of the driver sequencing network is to control off chip driver switching during test. 
     These and other features and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention as illustrated in the accompanying drawings. 
     (1) A primary object of the invention is to improve the efficiency and reliability of the testing of integrated circuit devices and/or chips. 
     (2A primary object of the invention is to provide a driver sequencing network on an integrated circuit device, or chip, which permits a test machine to control the switching time of driver circuits (or groups of driver circuits) of the integrated circuit device, or chip, under test. 
     (3) A primary object of the invention is to improve the efficiency and reliability of the testing integrated circuit logic chips by significantly if not totally obviating the &#34;delta I&#34; problem due to simultaneous switching of drivers during test. 
     (4) An object of the invention is to provide a driver sequencing network on a logic chip, or the like, to sequence, under tester control, the switching of drivers, or groups of drivers, during test. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIG. 1 illustrates, in accordance with the prior art, the delta I current path from the driver output wire, through the driver, through the unbypassed inductance and resistance of the power supply distribution network, through the by pass capacitor and back to the tester ground. 
     FIG. 2 is comprised of FIGS. 2A, 2B and 2C. 
     FIG. 2A depicts the voltage waveform imposed on the driver output wire by the off chip driver during switching. 
     FIG. 2B depicts the delta I waveform which occurs on the delta I path shown in the circuitry of FIG. 1. 
     FIG. 2C depicts the voltage generated across the unbypassed inductance and resistance of the prior art circuitry of FIG. 1. 
     FIG. 3 is comprised of FIGS. 3A, 3B and 3C. 
     FIG. 3A depicts the coupled voltage V=MdI/dt of the prior art circuitry of FIG. 1. 
     FIG. 3B depicts the coupled current I=Cdv/dt of the prior art circuit of FIG. 1. 
     FIG. 3C depicts the combined voltage noise waveform at the output of the prior art circuitry of FIG. 1. 
     FIG. 4 discloses a representative driver sequencing network in accordance with the invention. 
     FIG. 5 discloses a preferred embodiment of the invention wherein an integrated circuit chip under test includes a driver sequence network (DSN). FIG. 6 illustrates a representative driver circuit having three logic inputs, an inhibit input and an output. 
     FIG. 7 discloses a block diagram of the driver circuit of FIG. 6. 
     FIG. 8 discloses a timing diagram to be reviewed in conjunction with the explanation of operation of applicants invention as illustrated in FIG. 5 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     When many off chip drivers switch simultaneously a large change in power supply current results (delta I). FIG. 1 shows this delta I and its path from the driver output wire, through the driver, through the unbypassed inductance and resistance of the power supply distribution network, through the bypass capacitor and back to the tester ground. FIG. 2C shows the voltage that is generated across the unbypassed inductance and resistance as expressed by V=LdI/dt +RdI. DI and dI/dt relate directly to the driver type and the number of drivers switching together, as does the noise. 
     Voltage and current signals which change as a driver changes state can also couple into nearby I/O paths to the extent that false switching and test failures occur. FIG. 3 shows the voltage and current that can be coupled as expressed by the equations V=MdI/dt and I=CdV/dt, where M is the mutual inductance and C is the mutual capacitance between the paths. Again the noise relates directly to the driver type (speed ) and the number of drivers coupling noise into a nearby I/O path. 
     FIG. 4 shows an example of a driver sequencing network. Inputs labeled &#34;+Inhibit,&#34; &#34;Shift In,&#34; &#34;L1 Clock,&#34; and &#34;L2 Clock&#34; are controlled by the tester. Outputs &#34;+Inhibit Group 1&#34; through &#34;+Inhibit Group 4&#34; continue on the chip as the inhibit control lines for the respective off chip driver groups. The driver sequencing network shown is on the chip. 
     The latches in FIG. 4 labeled &#34;L1 Latch&#34; and &#34;L2 Latch&#34; are chained together into the commonly known shift register configuration. Data applied at the &#34;Shift In&#34; input will be sequentially passed to successive latches as the L1 clock and L2 clock are alternately applied. The OR blocks shown allow either the &#34;+Inhibit Input&#34; or the shift register contents to control the four &#34;+Inhibit Group&#34; outputs. The &#34;+Shift Out&#34; output is available to the tester for testing of the shift register string. 
     In the operation then; (1) let &#34;+Inhibit&#34;=&#34;logical 1 state&#34; thereby inhibiting all off chip drivers by setting a &#34;logical 1&#34; on all &#34;+Inhibit Group&#34; lines. (2) Now the shift register can be preset to a known state (all latch outputs =&#34;logical 1)&#34; without worrying about off chip driver switching. (3) Next, change &#34;+Inhibit&#34; =&#34;logical 0&#34;. The off chip drivers are still inhibited by the latch contents. (4) Finally let &#34;Shift In&#34; =&#34;logical 0&#34; and sequentially shift the &#34;logical 0&#34; (by alternating L1 and L2 Clocks) until all latch outputs are a &#34;logical 0&#34;. In doing this we have sequentially enabled the groups of drivers with a separation between the groups equal to the separation between the L1 clock and the L2 clock. (5) To sequentially disable the off chip drivers, set Shift In =&#34;logical 1&#34; and then sequentially shift the &#34; logical 1&#34; onto all four latch outputs. In system operation both &#34;+Inhibit&#34; and &#34;Shift In&#34; must be a logical 0. The L1 Clock and L2 Clock must both be kept at their active logic level so that the Shift In data (&#34;logical 0&#34;) will be kept on the latch outputs. The off chip drivers will always be enabled in this case. 
     It should be noted that adding latches to the shift string, and corresponding `OR` gates, allows control over a greater number of off chip driver groups. For example: 
     Assume 240 off chip drivers on the chip 
     Assume 12 groups are formed (by design) Therefore 20 drivers per group are allowed and 6 L1 latches 6 L2 latches and 12 OR gates are required to control the 12 groups. 
     No additional connections are required to the tester. 
     A latent ability exists which would allow selective enabling of off chip drivers by.presetting the shift register while the drivers are inhibited, then changing+Inhibit to &#34;0&#34; to allow the preset shift register to enable the driver groups selected. 
     The advantages and disadvantages of the driver sequencing network (DSN) are: 
     (1) Flexible--The DSN can be employed or ignored as desired. Problem part numbers may require the DSN to be used whenever a test pattern called for the drivers to be enabled. The drivers will be sequence enabled, measured, and then sequence inhibited for each such pattern. 
     (2) Driver Groups--Each group may be designed to minimize both coupled and power supply noise through physical selection of the driver placement for each group. In addition, troublesome drivers can be restricted to a specific number per group, instead of just by the group size. 
     (3) Easily Implemented--Requires no new test hardware and relatively small changes to test generation. 
     (4) Tester controlled sequencing--The tester has full control of the time separation between groups of switching drivers. 
     (5) Low overhead--Low circuit count in DSN and no performance penalty for the user of the device. 
     (6) Compatible--The DSN is compatible with electronic chip in place testing (ECIPT) (ECIPT is Electronic Chip In Place Testing and is fully disclosed in U.S. Pat. No. 4,504,784 entitled &#34;Method of Electronically Testing A Packaging Structure Having Integrated Circuit Chips&#34;, and granted Mar. 12, 1985 to P. Goel et al.), partitioning driver inhibit pin techniques, and self test concepts. 
     (7) Shipped Product Quality Level (SPQL)--Since the DSN is uniquely a testing aid, it need not be tested for full fault coverage. The small circuit count and minimal interface to the device logic makes the DSN a negligible contributor to device yield loss and SPQL. 
     (8) The DSN is not readily useable at the next level of packaging. DSN&#39;s are mainly needed at wafer, chip and single chip module testing. 
     (9) The DSN may require only 3 to 5 I/O pins or contacts depending on the embodiment. 
     (10) Unique DSN inputs can be defined at wafer test for devices intended for multi-chip modules (MCM&#39;s). Contact pads not normally useable at the next level of assembly can be used as DSN inputs. 
     A preferred embodiment of the invention employing the driver sequence network can be seen in FIG. 5. The logic function internal to the chip is fed by a plurality of logical input receivers R5 through R54. The chip&#39;s logic function output is passed back to the tester through off chip drivers D2 through D102. Each driver D3 through D102 has a driver inhibit input which, when active, blocks (inhibits) the logic state coming into the driver and forces the driver output to a known or high impedance state. Driver D2 does not get inhibited in any circumstance. D2 is the commonly known shift register output of a Level Sensitive Scan Design (LSSD) register string. The LSSD register string is utilized in the chip logic function and enhances testability of that logic. FIG. 6 shows an example of a driver circuit with three logic inputs and an inhibit input. 
     All of the items listed above are fabricated on the chip and are normal or conventional to a VLSI chip. To embody a Driver Sequence Network, additional receivers, drivers and logic is required. A representative DSN is shown enclosed within a broken line bearing the legend &#34;Driver Sequencing Network&#34; at the lower right of FIG. 5. The off chip drivers D3 through D102 are divided into groups of ten drivers each. Each group shares a common inhibit line so that there are ten separate group inhibit lines, one for each driver group. Again, D2 does not get inhibited because it provides the shift register output function. The group inhibit lines may all be set to the inhibiting state simultaneously by the &#34;+Inhibit&#34; control line or each group inhibit line may be brought up sequentially by using the `Sequence Scan In`, `+L1 Clock`, and `+L2 Clock` to shift a logical `1` through the ten shift register latches (L1 through L10). Likewise the &#34;+Inhibit&#34; line may allow all group inhibit lines to go to the enable state simultaneously, or each line may be enabled sequentially by shifting a logical `0` through the ten latches (See FIG. 8 for a timing diagram of the shift operation). Driver D1 facilitates testing of the sequencing shift register of the DSN by providing a shift register output to the tester. 
     With this embodiment the following test execution steps can be used to prevent too many off chip drivers from switching simultaneously. 
     1. Apply a logic `l` on the &#34;+Inhibit&#34; line of the tester to receiver R4 of the driver sequencing network. 
     2. Power up the chip from the tester (not shown) Note: Off-Chip drivers D3-D102 are inhibited 
     3. Apply a logic `l` on the &#34;Sequence Scan-In&#34; line of the tester to receiver R3 of the &#34;Driver Sequencing Network&#34;. Concurrently impress alternate clock pulses (+L1 clock and +L2 clock) on receivers R2 and Rl of the &#34;Driver Sequencing Network&#34; five times to load the shift register (L1 through L10) with logic `l`s. 
     4. Utilizing the &#34;+Inhibit Line&#34; apply a logic `0` to receiver R4 of the &#34;Driver Sequencing Network&#34; Note: Drivers D3-D102 are still inhibited by L1-L10. Steps 1 to 4 are only used for power on initialization. 
     5. Apply logical inputs from the tester (stimulus 5-54) to the on-chip receivers R5-R54 to test the chip logic for faults. 
     6. Apply a logical `0` via the &#34;Sequence Scan-In&#34; line to receiver R3. Concurrently utilize the +L1 and the +L2 clock to provide alternative clock pulses to R2 and R1 five times to sequentially load logic 0&#39;s into latches L1-L10. This action sequentially enables each of the ten groups of drivers. 
     7. Use the tester to measure the output states of drivers D3-D102 and compare them against the expected states to verify a fault free test. 
     8. Apply a logic `1` on the &#34;Sequence Scan-In&#34; of the tester to receiver R3. Concurrently utilize the +L1 clock and the +L2 clock to provide alternate clock pulses to receivers R2 and Rl five times to sequentially load logic 1&#39;s into latches L1-L10. This action sequentially inhibits each of the ten groups of drivers. (As shown in FIG. 8.) 
     9. Apply tester stimulus to on-chip receivers R5-R54 in order to shift out data captured in the LSSD shift register (not shown) of the logic chip. 
     Measure each data bit shifted out through off-chip driver D2 and compare against the expected bit string to verify a fault free test. 
     Repeat steps 5 to 9 until all desired tests have been made. 
     During sequencing of the driver groups (inhibit or enable) further noise reduction is possible by increasing the pulse separation between the +L1 clock pulse and the +L2 clock pulse. 
     A key assumption has been made that ten off chip drivers may switch simultaneously without disturbing a test. This `group size` (ten drivers per group) should be determined conservatively because it can be sensitive to many parameters including driver speed and logic noise margins. Reducing the group size is not costly. For each additional group created the cost is one new latch (i.e. L1l) and one new `OR` gate. No additional I/O connections are needed. 
     While the invention has been particularly described with reference to the preferred embodiment, it will be understood by those skilled in the art that the foregoing and other changes and details may be made therein without departing from the spirit and scope of the invention.