Abstract:
A sense circuit for multi-level flash memory cell includes a control signal generator for generating a plurality of voltage control signals, a clock signal having constant period and a plurality of control pulses according to a sense amplifier enable signal; a control voltage generator for generating multi-steps voltage according to the clock signal and the plurality of voltage control signals, sequentially supplying the multi-steps voltage to a program gate of the memory cell, generating a reference voltage according to the sense amplifier enable signal and supplying the reference voltage to a program gate of a reference cell; and a sense amplifier for sequentially comparing a plurality of data stored in the memory cell and a data of the reference cell, storing the result according to the control pulse and converting it into binary data.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a sense circuit of a flash memory device and, in particular, to a sense circuit of a flash memory device which sense, according to a clock signal having a constant period and a plurality of control signal, data on a flash memory cell capable of storing multi-level, and transforms it to binary data. 
     2. Related Prior Art 
     In general, in case of sensing information stored in a memory cell, sensing is done by comparing an amount of current flowing through the memory cell and that flowing through the reference memory cell. 
     A conventional memory cell is designed to store only one data and also a sense amplifier sensing such cell is designed to sense only one data. However, there is a problem in that storing only one data to one cell requires a plurality of memory cells in proportion to the amount of data and degrades the high-density integration of a device. To solve such problem, a memory cell which can store multi-level is developed. Accordingly, the memory cell has become to be able to store one or more data, and development of a sense amplifier which can precisely sense data stored in such cell has become necessary. 
     SUMMARY OF THE INVENTION 
     Therefore, the object of the present invention is to provide a sense circuit of a flash memory device which can sense, according to a clock signal having a constant period and a plurality of control signals, data on a flash memory cell capable of storing multilevel, trans form it to binary data. 
     A sense circuit according to the present invention to accomplish the above described object comprises a control signal generator for generating a plurality of voltage control signals, a clock signal having constant period and a plurality of control pulses according to a sense amplifier enable signal, a control voltage generator for generating multi-steps voltage according to the clock signal and the plurality of voltage control signals, sequentially supplying the multi-steps voltage to a program gate of the memory cell, generating a reference voltage according to the sense amplifier enable signal and supplying the reference voltage to a program gate of a reference cell; and a sense amplifier for sequentially comparing a plurality of data stored in the memory cell and a data of the reference cell, storing the result according to the control pulse and converting it into binary data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above object and other advantages of the present invention will become more apparent by describing in detail the preferred embodiment of the present invention with reference to the attached drawings in which: 
     FIG. 1 is a block diagram showing a sense circuit for a multi-level flash memory cell according to the present invention; 
     FIG. 2 is a detailed circuit diagram of a control signal generator FIG. 1; 
     FIG. 3 is a detailed circuit diagram of a control voltage generator of FIG. 1; 
     FIG. 4 is a detailed circuit diagram of a sense amplifier; and 
     FIG. 5 is a waveform diagram to illustrate an operation of a sense circuit according to the present invention. 
    
    
     Similar reference characters refer to similar parts in the several views of the drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention will be described in detail with reference to the accompanying drawings. 
     FIG. 1 is a block diagram showing a sense circuit for multi-level flash memory cell according to the present invention. 
     A sense amplifier enable signal SAENb is input to a control signal generator  11  to read multi data stored on a multi-level flash memory cell  14 . A clock signal CLKb having constant period, a first, a second and a third voltage control signals VCCR 1 , VCCR 2  and VCCR 3  generated by the control signal generator  11  are supplied to a control voltage generator  12 . A first, second and third pulses CLK 1 , CLK 2  and CLK 3  and an output enable signal OUTEN generated by the control signal generator  11  are supplied to a sense amplifier  13 . The control voltage generator  12  generates a reference voltage VCC_REF and a read-out voltage VCCR. The reference voltage VCC_REF is supplied to a program gate of a reference cell  15  and the read-out voltage VCCR is supplied to a program gate of the flash memory cell  14 . The read-out voltage VCCR varies according the first to third voltage control signals. That is, according to the clock signal CLKb, the sequentially changed read-out voltage VCCR is supplied to the memory cell  14 . The sense amplifier  13  sequentially compares the currents flowing through the memory cell  14  and the reference cell  15 . The multi-data stored in the memory cell  14  is read out by this operation and converted into binary data. 
     Referring to FIGS. 2 to  4 , a case where three data are stored in one memory cell will be explained in detail. 
     FIG. 2 is a detailed circuit diagram of the control signal generator  11  of FIG.  1 . The operation of FIG. 2 will be explained with reference to FIG.  5 . 
     The clock signal CLKb generated by a clock signal generator  201  according to the sense amplifier enable signal SAENb is input to a clock terminal CLK of a first latch  202   a  of a clock signal counter  202 . The clock signal counter  202  is composed of a first to third latches  202   a  to  202   c,  counts the clock signal CLKb and generates a plurality of output signals Q 0 , Q 1  and Q 2 . The three output signals Q 0 , Q 1  and Q 2  generated by the clock signal counter  202  are input to a multiplexer  203 . The multiplexer  203  sequentially outputs the signals CLK 1  to CLK 3 , VCCR 1  to VCCR 3  and OUTEN as shown in Table 1. 
     
       
         
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Q0 
                 Q1 
                 Q2 
                 OUTPUT OF MULTIPLEXER 
               
               
                   
               
             
             
               
                 1 
                 0 
                 0 
                 VCCR1 
               
               
                 0 
                 1 
                 0 
                 VCCR1 and CLK1 
               
               
                 1 
                 1 
                 0 
                 VCCR2 
               
               
                 0 
                 0 
                 1 
                 VCCR2 and CLK2 
               
               
                 1 
                 0 
                 1 
                 VCCR3 
               
               
                 0 
                 1 
                 1 
                 VCCR3 and CLK3 
               
               
                 1 
                 1 
                 1 
                 OUTEN 
               
               
                   
               
             
          
         
       
     
     FIG. 3 is a detailed circuit diagram of the control voltage generator of FIG.  1 . The operation of FIG. 3 will be explained with reference to FIG.  5 . 
     The clock signal CLKb is inverted by an inverter G 1  and input to a first transistor M 1  acting as a capacitor. The supply voltage VCC is supplied to a first node N 1  via a second transistor M 2 . The first node N 1  is boosted to a level higher than the supply voltage VCC according to the clock signal CLKb supplied through the first transistor M 1 . The boosted voltage is input to a first to third regulators  100  to  300  through a third transistor M 3 . A capacitor C 1  is connected between the inputs of the regulators and the ground. 
     The first to third regulators  100  to  300  are enabled according the first to third voltage control signals VCCR 1  to VCCR 3 . That is, if the first voltage control signal VCCR 1  is at high state, the first regulator  100  is enabled, if the second voltage control signal VCCR 2  is at high state, the second and third regulators  200  and  300  are enabled, and if the third voltage control signal VCCR 3  is at high state, the first to third regulators  100  to  300  are enabled, so that an output node VCCR is applied with a first, second or third voltage VCR 1 , VCR 2  or VCR 3 . In addition, a reference regulator  400  generates a stabilized reference voltage VCCR_REF according to the sense amplifier enable signal SAENb. The first, second or third voltage VCR 1 , VCR 2  or VCR 3  is supplied to the program gate of the memory cell  14  and the reference voltage VCCR_REF is supplied to the program gate of the reference cell  15 . 
     FIG. 4 is a detailed circuit diagram of the sense amplifier of FIG.  1 . The operation of FIG. 4 will be described in detail with reference to FIG. 5. A first operational amplifier OP 1 , which is enabled according to the sense amplifier enable signal SAENb and to for example a non-inverting terminal(+) of which the voltage of 2V is supplied, controls a fifth transistor M 5  so that a node N 10  maintains 2V. Similarly, a second operational amplifier OP 2 , which is enabled according to the sense amplifier enable signal SAENb and to for example a non-inverting terminal (+) of which the voltage of 2V is supplied, controls a seventh transistor M 7  so that a node N 20  maintains 2V. The fourth and sixth transistors M 4  and M 6  are always turned on since they are supplied with the supply voltage Vcc, and supply a constant current to the fifth and seventh transistors, respectively. The node N 10  is connected to the drain of the memory cell  14 , and the node N 20  is connected to the drain of the reference cell  15 , the sources of the two cells being grounded. As previously explained, since the constant reference voltage VCCR_REF is supplied to the program gate of the reference cell  15 , a node N 40  maintains the constant voltage. However, since the memory cell  14  is programmed to multi-level and the voltage supplied to the program gate thereof is variable, the potential of the node N 30  varies according the program condition of memory cell  14 . The potential difference between the node N 30  and node N 40  is finally compared at a third operational amplifier OP 3 . The output of the third operational amplifier OP 3  is stored in one of the fourth, fifth and sixth latches  41   a,    41   b  and  41   c  in latch block  41  according to the first to third pulses CLk 1  to CLK 3 . The output of the third operational amplifier OP 3  is stored to the fourth latch  41   a  in case the first clock CLK 1  is at high state, to the fifth latch  41   b  in case the second clock CLK 2  is at high state, and to the sixth latch  41   c  in case the third clock CLK 3  is at high state. The data stored in the fourth, fifth and sixth latches  41   a,    41   b,    41   c  are input to a mixer  42  acting as an encoder according to the output enable signal OUTEN, then converted to binary data and output through the output terminal OUT. 
     FIG. 5 is a waveform diagram to illustrate the operation of the sense circuit according to the present invention. 
     In the interval t 1  to t 2 , as the sense amplifier enable signal SAENb becomes low state, the clock signal CLKb having a constant period is generated from the clock signal generator ( 201  of FIG.  2 ). The clock signal CLKb is input to the control signal generator( 11  of FIG. 1) and the control voltage generator( 12  of FIG.  1 ). The output terminal Q 0  to Q 2  of clock signal counter ( 202  of FIG. 2) in the control signal generator ( 11  of FIG. 1) to which the clock signal CLKb is input becomes for example “100”. In this case, the multiplexer ( 203  of FIG. 2) outputs the first voltage control signal VCCR 1 . Therefore, since the first regulator  100  is enabled by the first voltage control signal VCCR 1 , the VCCR node becomes the first voltage VCR 1 . Accordingly, the potential of the program gate of the memory cell  14  becomes the first voltage VCR 1 . 
     In the period t 2  to t 3 , if the clock signal counter ( 202  of FIG. 2) outputs ‘010’, the multiplexer ( 203  of FIG. 2) outputs the first pulse CLK  1  and the second voltage control signal VCCR 2 . The fourth latch ( 41   a  of FIG. 4) is enabled by the first pulse CLK 1 . At this time, the program gate maintains the first voltage VCR 1 . 
     In the period t 3  to t 4 , if the clock signal counter ( 202  of FIG. 2) outputs ‘110’, the multiplexer ( 203  of FIG. 2) outputs the second voltage control signal VCCR 2 . Accordingly, the second and third regulators  200  and  300  of FIG. 3 are enabled, therefore, the VCCR node is boosted to the second voltage VCR 2  higher than the first voltage. Therefore, the potential of the program gate PG of the memory cell  14  is boosted to the second voltage VCR 2 . 
     In the period t 4  to t 5 , if the clock signal counter ( 202  of FIG. 2) outputs ‘001’, the multiplexer ( 203  of FIG. 2) outputs the second voltage control signal VCCR 2  and the second pulse CLK 2 . Accordingly, the fifth latch  41   b  of FIG. 4 is enabled and the second and third regulators  200  and  300  of FIG. 3 are enabled, therefore the VCCR node maintains the second voltage VCR 2 . Therefor, the potential of program gate PG of memory cell  14  maintains the second voltage VCR 2 . 
     In the period t 5  to t 6 , if the clock signal counter ( 202  of FIG. 2) outputs ‘101’, the multiplexer ( 203  of FIG. 2) outputs the third voltage control signal VCCR 3 . Therefore, since the first, second and third regulators  100 ,  200  and  300  of FIG. 3 are enabled, the VCCR node is boosted to the third voltage VCR 3  higher than the second voltage. Therefore, the potential of the program gate PG of the memory cell  14  is boosted to the third voltage VCR 3 . 
     In the period t 6  to t 7 , if the clock signal counter ( 202  of FIG. 2) outputs ‘011’, the multiplexer ( 203  of FIG. 2) outputs the third voltage control signal VCCR 3  and the third pulse CLK 3 . Accordingly, since the sixth latch  41   c  of FIG. 4 is enabled and the first, second and third regulators  100 ,  200  and  300  of FIG. 3 are enabled, the VCCR node maintains the third voltage VCR 3 . Therefore, the potential of program gate PG of the memory cell  14  maintains the third voltage VCR 3 . 
     In the period t 7  to t 8 , the sense amplifier enable signal SAENb is in high state and no more clock is generated. At this time, the clock signal counter ( 202  of FIG. 2) outputs data ‘111’ and the multiplexer  203  outputs the output enable signal OUTEN. According to the output enable signal OUTEN, the data of the fourth to sixth latches ( 41   a  to  41   c  of FIG. 4) are input to the mixer ( 42  of FIG.  4 ). Now the program gate of the memory cell returns to the potential condition which was initially maintained, and the data which is input to the mixer ( 42  of FIG. 4) is converted to binary data. 
     Effect of the Invention 
     As described above, the present invention has the effect that it can raise the degree of integrity and precisely sense the data stored in cell by sensing in multi-step a plurality of data stored in memory cell which can store multi-level, mixing it, converting it into binary data and outputting it. 
     The foregoing description, although described in its preferred embodiment with a certain degree of particularity, is only illustrative of the principles of the present invention. It is to be understood that the present invention is not to be limited to the preferred embodiments disclosed and illustrated herein. Accordingly, all expedient variations that may be made within the scope and spirit of the present invention are to be encompassed as further embodiments of the present invention.