Abstract:
A data control unit is used to proved program, erase and verify signals to a non-volatile metal-oxide3-nitride-oxide-semiconductor (MONOS) memory. The data control unit comprises a plurality of sub-units that each contains a sense amplifier, two bi-directional flip-flop latches coupled in series and a program, erase and verify circuit. The two flip-flop latches each perform a task as a master latch or a slave latch depending on the memory operation. The program, erase and verify circuit in each sub-unit are connected together in a serial fashion such that multiple verification results are accumulated into one final result. Control signals are exchanged between a chip control unit and the data control unit to perform specified memory operations.

Description:
This application claims priority to Provisional Patent Application Ser. No. 60/424,778, filed on Nov. 8, 2002, which is herein incorporated by reference. 

   BACKGROUND OF THE INVENTION 
   1. Field of Invention 
   The present invention relates to semiconductor memory and more specifically to non-volatile memory. 
   2. Description of Related Art 
   Data is stored as electrons in floating gates of non-volatile memory cells. In high density, low voltage and high-speed applications, a metal-oxide-nitride-oxide-semiconductor (MONOS) can be used where the floating gates are in the form of an oxide-nitride-oxide (ONO) composite layer located under a control gate. There are two separate and independently programmable ONO layers under a single control gate that provides a memory density improvement, as discussed in U.S. Pat. No. 6,549,463 (Ogura et al.). Electrons are stored separately under separate control in the two ONO layers so that two independent memory sites are located under a single control gate. This leads to an increase in storage density. 
   U.S. Pat. No. 6,248,633 (Ogura et al) is directed to the device structure and operation of a twin MONOS flash memory. In U.S. Pat. No. 6,075,727 (Morton et al.) a method is directed to writing and verifying bits in a non-volatile memory using a three-transistor memory cell. Data in a write latch is compared to data in a cell to determine if the cell has been programmed or erased. U.S. Pat. No. 6,031,760 (Sakui et al.) is directed to a non-volatile semiconductor memory, which includes sense amplifier circuits, each having a latch connected to the sense node. The sense amplifier contains first and second data-latching transistors that are used in a program and verify operation. U.S. Pat. No. 6,009,015 (Sugiyama) is directed to a program verify circuit for a nonvolatile memory array with multi-level stored data. The program verify circuitry contains a latch circuit connected between a bit line and a source/drain of a variable threshold transistor. 
   The prior art circuits described above are suitable for NAND flash applications in which all memory cells connected to a word line should be programmed at the same time. This simultaneous program is needed because the WL voltage during program is raised to a high voltage, e.g. 20V, creating a very high program disturb condition should there be any unselected cells. Thus, in a NAND flash, since every BL (or every other BL) requires a sense amplifier/verify circuit, the layout is a difficult space challenge, and the circuits must be small and simple. 
   A Twin MONOS cell and as well as additional kinds of split gate memory cells use the WL as a select gate, which does not require high voltage. So it is possible to selectively decode 1 in 2, 4, 8, etc cells such that several bit lines will share a single sense amplifier/data/verify circuit. Small area size is still important, but additional functionality can be easily included. Also, the sensing circuit itself can be made more sensitive so that sensing time can be reduced. 
   SUMMARY OF THE INVENTION 
   It is an objective of the present invention to provide a data control unit comprising a plurality of sub-units to control the program, read, verify and erase operations for a Metal-oxide-nitride-oxide-semiconductor (MONOS). 
   It is also an objective of the present invention for each sub-unit to comprise a bi-directional master flip-flop latch and a bi-directional slave flip-flop latch used transfer data between a sense amplifier coupled to bit line decoder and data input/output (I/O) lines connected to and I/O interface unit. 
   It is yet an objective of the present invention to couple the sub-units together in a serial fashion starting with the first sub-unit coupled to the second sub-unit and continuing to the next to last-sub-unit coupled to the last sub-unit. 
   It is still yet an objective of the present invention for each sub-unit to contain a sense amplifier, a first flip-flop latch, a second flip-flop latch and a program-erase-verify circuit. 
   It is further an objective of the present invention for the first and second flip-flop latches to be b-directional. 
   It is still further an objective of the present invention for the first flip-flop latch to perform as a master latch and the second flip-flop latch perform as a slave latch during a read operation, and the second flip-flop latch perform as a master latch and the first flip-flop latch perform as a slave latch during a program operation. 
   In the present invention a MONOS non-volatile memory array is coupled to and controlled by a control gate decoder, word line decoder, a bit line decoder. A memory chip control unit controls the operations of the decoders, a data control unit and an I/O interface unit. The data control unit interfaces between the bit line decoder and I/O data lines connected to the I/O interface unit, and comprises a plurality of sub-units, each further comprising a sense amplifier coupled to the bit line decoder, a first and second flip-flop latch coupled between the sense amplifier and the I/O data lines and a program-erase-verify circuit. Each sub-unit is connected in a serial fashion beginning with the program-erase-verify circuit of the first sub-unit coupled to the program-verify-erase-verify unit of the second sub-unit through to the program-erase-verify circuit of the next to last sub-unit coupled to the program-verify-erase-verify unit of the last sub-unit. 
   The first flip-flop latch performs as a master latch during a read operation receiving data from the bit line decoder while the second flip-flop latch performs as a slave latch during the read operation coupling data to the I/O interface unit. The second flip-flop latch performs as a master latch during a program operation receiving data from the I/O interface unit while the first flip-flop latch performs as a slave latch during the program operation coupling data to the sense amplifier. Data that is first placed into the master latch is coupled to the slave latch for further processing. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This invention will be described with reference to the accompanying drawings, wherein: 
       FIG. 1  is a block diagram of a memory device of the present invention, 
       FIG. 2  is a block diagram of data control sub-units of the present invention, 
       FIG. 3  is a circuit diagram of a data control sub-unit of the present invention, 
       FIG. 4  is a signal diagram of a read operation of the present invention, and 
       FIG. 5  is a signal diagram of a program and verify operation of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1  shows a schematic diagram of a non-volatile memory  30  of the present invention. A memory array  13  containing metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells  17  is coupled to a control gate decoder  10 , a word line decoder  11  and a bit line decoder  12 . Interfacing between the bit line decoder  12  and an input/output (I/O) interface unit  16  is a data control unit  14 . A memory chip control unit  15  controls the operation of the memory chip  30  and is coupled to the control gate decoder  10 , the word line decoder  11 , the bit line decoder  12 , the data control unit  14  and the I/O interface unit. Contained within the data control unit  14  are a plurality of sub-units. Control signals are coupled to the sub-units from the chip control unit  15 . A program-erase-verify signal  23  contained within the nth sub-unit is coupled from the nth sub-unit to the chip control unit  15 . The plurality of sub-units are serially connected starting  19  with sub-unit  1  and continuing until sub-unit n−1 is coupled to sub-unit n. Each sub-unit of the data control unit  14  is coupled to the I/O interface unit  16  through data I/O lines  20 . 
   Continuing to refer to  FIG. 1 , the chip control unit  15  delivers specified addresses to the control gate decoder  10 , the word gate decoder  11 , and the bit line decoder  12 . The control gate decoder  10  is coupled to the control gates of the memory array, and during program, erase, and read operations the control gate decoder  10  selects a memory page in accordance with address supplied by the chip control unit  15 . The chip control unit  15  supplies all control signals and high voltages required for the various memory operations. The word line decoder  11  is coupled to the word gates of the memory array, and during program, erase and read operations the word line  11  decoder selects a memory word line in accordance with address supplied by the chip control unit  15 . The bit line decoder  12  is coupled to bit lines of the memory array, and during program, erase and read operations the bit line decoder  12  selects a memory bit line in accordance with address supplied by the chip control unit  15 . The bit line decoder  12  couples data from the bit lines to the data control unit  14 . The data control unit  14  senses and amplifies the bit line signals and transfers the amplified bit line signals to the I/O interface circuit  16  in a read operation. 
   Continuing to refer to  FIG. 1 , during a Program operation the data control unit  14  receives data from the I/O interface circuit and produces a program voltage or a program inhibit voltage depending upon the received data. After a program operation has been applied to a memory cell, the data control unit  14  senses and verifies the state of the selected memory cell. During an erase operation the data control unit  14  applies erase signals to the selected memory cells, after which the data control unit  14  reads the selected memory cells for the purpose of verifying the erase operation. 
   In  FIG. 2  is shown a block diagram of a data control sub-unit  71  within the data control unit  14  and connected to other sub-units  70  and  72 . Within each sub-unit  71  is a sense amplifier  50 , a first flip-flop latch  52 , a second flip-flop latch  53  and a program-erase-verify circuit  54 . The sense amplifier is coupled to the memory bit lines through the bit line decoder  12 . The first flip-flop latch  52  coupled to the sense amplifier  50  acts as a master latch during a read operation and the second flip-flop latch  53  coupled to the first flip-flop latch  52  acts as a master latch during a program operation. During a read operation, the amplified signal the sense amplifier  50  is stored in the first flip-flop  52  latch, which is acting as a master latch. When the first flip-flop latch  52  is a master latch, data is transferred to the second flip-flop latch  53 , which acts as a slave latch. During a program operation a signal from the data I/O lines  20  coupled to the data I/O unit  16  is stored in the second latch  53 , which is acting as a master latch. Upon programming a selected memory cell, the sense amplifier  50  reads the program state of the selected cell and stores the amplified signal of the program state of the selected memory cell into the first flip-flop latch. It should be noted that the first flip-flop latch  52  has switched from being a slave latch during the preceding program operation to a master latch during the verify operation that is performing a read of the selected memory cell. The program-erase-verify circuit  54  reads the data of the verify operation from the first flip-flop latch  52  and produces a program condition voltage, or a program inhibit voltage, on a signal line  60  connected to the bit line decoder. The program condition voltage can be the voltage applied to the source BL in order to allow current to flow to the cell, this is usually a voltage close to 0V. The program inhibit voltage is any voltage applied to the BL that can prevent current from flowing to the cell. It can be any voltage greater than the word gate voltage minus the threshold voltage of the word gate, or simply VDD or VDD-Vt. When the second flip-flop latch  53  is a master latch, data is transferred to the first flip-flop latch  52 , which acts as a slave latch. Both the first and second latches are bi-directional. 
   Continuing to refer to  FIG. 2 , during an erase operation the sense amplifier senses and amplifies a signal from the selected memory cell, which is outputted to the first flip-lop latch  52  acting as a master latch. The program-erase-verify circuit  54  reads the data stored in the first latch  52  and reads the output the data  63  from the previous sub-unit  70 . The program-erase-verify circuit  54  then produces a combined verification result and outputs the combined verification result  19  to the next sub-unit  72 . If either the results from the first latch or the previous sub-unit indicates that a cell has not been erased, then that result is passed on to the chip control unit  15 . All cells must be erased before the signal passed to the chip control unit  15  from the nth sub-unit before the erase operation is completed. The chip control unit  15  ( FIG. 1 ) receives the final verification  23  from the nth sub-unit. If all cells are verified to be erased, the erase operation is terminated; otherwise, additional erase operations are performed until the output of the nth sub-unit to the chip control unit shows that all memory cells have been erased. 
   In  FIG. 3  is shown a schematic diagram of a data control sub-unit. The sense amplifier  50  comprises a PMOS transistor P 1  and an NMOS transistor N 1 , which are controlled by signals “Pre” and “Bias” and is connected to the bit line decoder  12  through the NMOS transistor N 1 . “Pre” is the voltage used to control the precharge voltage of the BL through the source follower NMOS transistor. “Bias” is the voltage used to control the sensing signal margin. As a general rule, “Pre” is greater than “Bias”. If 200 mV sensing margin is desired, then “Pre”−“Bias” is roughly 200 mV. 
   Continuing to refer to  FIG. 3 , the sense amplifier  50  is coupled to VDD as are other circuits within the sub-unit  71 . It should be noted that a “P” indicates PMOS transistors and an “N” indicates NMOS transistors. Two clocked inverter latches are used for the first and the second flip-flop latch  52  and  53 . The first flip-flop latch  52  comprises a first clocked inverter containing transistors P 2 , P 3 , N 2 , and N 3  a second clocked inverter containing transistors P 4 , P 5 , N 4  and N 5 . The first clocked inverter is clocked with DL and DL_b clock signals and the second clocked inverter is clocked with SVE and SVE_b clock signals. The second flip-flop latch  53  comprises a third clocked inverter containing transistors P 6 , P 7 , N 6 , N 7  and a fourth clocked inverter containing transistors P 8 , P 9 , N 8  and N 9 . The third clocked inverter is clocked with Dl and Dl_b clock signals and the fourth clocked inverter is clocked with DO and DO_b clock signals. The first and second flip-flop latches  52  and  53  are bi-directional where the output of one inverter contained within the latch is an input for the other inverter contained within the latch. 
   Continuing to refer to  FIG. 3 , the program-erase-verify circuit  54  is shown in two sections on  FIG. 3 , an erase verify circuit  54   e  and a program verify circuit  54   p . A fifth clocked latch is contained within the program-erase-verify circuit  54   e , which comprises transistors P 20 , P 21 , N 20  and N 21  and clocked with clock signals PGM and PGM_b. The output of the fifth clocked latch is coupled to the bit line decoder, and the input is coupled to the first flip flop latch  52  and an input of a NAND circuit A 20 . A second input  63  to the NAND circuit A 20  is from the previous sub-unit  70 . The output of the NAND circuit drives an inverter circuit INV 20 , and the output  19  of the inverter circuit INV 20  couples to the following sub-unit  72  as shown in  FIG. 2 . The NAND A 20  and the inverter circuit INV 20  are used for the erase verify circuit. The program verify circuit  54   p  comprises two NMOS transistors N 22  and N 23 . The gate of transistor N 22  is driven by signal VE, and the gate of transistor N 23  is connected to the sense node SN of the sense amplifier  50 . The program verify circuit senses the BL signal in a verify operation. If the cell has been programmed, the latch resets and the program inhibit voltage (in this case VDD) is applied to the BL through the BL decoder. 
   Continuing to refer to  FIG. 3 , a transistor N 10  couples the sense node SN of the sense amplifier  50  to the first flip-flop latch  52  under the control of signal SE. A transistor N 11  couples the first flip-flop latch  52  to the second flip-flop latch  53  under the control of signal DT. A transistor N 12 , under the control of a decoded signal through a NAND circuit A 10  and an Inverter circuit INV 10  and with a gate signal DE, couples the second flip-flop latch to data I/O lines  20 . 
   In  FIG. 4  is shown a signal diagram of the present invention for a read operation. The read operation begins with by resetting the master flip-flop (the first flip-flop latch) and pre-charging the selected bit lines during the time T 1 –T 3 . At time T 4  the control gate decoder  10  the word line decoder  11  are turned on by the signal shown on  FIG. 4  as “Word &amp; CG”. Depending upon whether the selected cell is programmed or erased the bit line voltage “bit line” remains unchanged or begins to fall. At time T 5  the “bias” signal is turned on along with the signal SE on the gate of the coupling transistor N 10  and the clock SVE of the first flip-flop latch  52 . The sense node SN remains the same or falls to lower voltage, 0.5V for example, depending on whether the selected cell has been programmed or is erased. At time T 7  the coupling transistor N 11  is turned on by signal DT and the data stored in the first flip-flop latch  52  is clocked (signal DO) into the second flip-flop latch  53 . At time T 9  the gate of the coupling transistor N 12  is applied with a signal DE from a decoder signal through the NAND circuit A 10  and the inverter circuit INV  10 . The signal DE turns on transistor N 12  coupling the read data in the second flip-flop latch  53  to the I/O data lines  20 . 
   In  FIG. 5  is shown a signal diagram for a program and verify operation. A program operation begins by transferring data from the I/O interface circuit  16  at T 1  time to the second flip-flop latch  53  designated as the master flip-flop during a program operation. The control signal DE connects the second flip-flop latch  53  to the data I/O lines and the clock signal Dl clocks the data into the second flip-flop latch  53  (master). At T 2  time the data D 1  is transferred to the first flip-flop latch  52  (slave) by transistor N 11  controlled by signal DT and clocked into the first flip-flop latch  53  by clock signal DL. When the PGM control signal is turned on at T 3 , the program-erase-verify circuit  54   e  couples to the bit line decoder  12  a supply voltage VDD for program inhibit, or ground for programming the data stored in the first flip-flop latch  52 . During the programming of a memory cell, the next data D 2  is transferred from the I/O data lines to the second flip-flop latch  53  (master). After a program operation on the selected cell T 7 , program verification is performed starting at T 8  similar to the read operation previously discussed, where the signals for the verify operation in  FIG. 5  are similar to those of  FIG. 4 . When the signal of a selected memory cell is sensed, the verification control signal VE is turned on at T 11  instead of the sense control signal SE that was used in the read operation. If the selected memory is programmed, the voltage of the data node DN of the first flip-flop latch  52  goes to a low voltage state and the program-erase-verify circuit  54   e  produces a supply voltage VDD that inhibits programming in the next program cycle. If the selected memory cell is not programmed, the voltage of data node DN remains in a high voltage state and the program-erase-verify circuit  54   e  produces a ground voltage to program the selected memory cell in the next program cycle starting at T 13  and ending at T 15  in the subsequent verify cycle. 
   After an erase operation is executed on a memory block verification is perform similarly to that of a read operation. If all data selected memory cell are erased, all data nodes DE of the first flip-flop latch circuit  52  are at a high voltage causing the program-erase-verify circuit  54   e  to producer a low voltage state indicating all selected memory cells are erased. If one of the memory cells is not completely erased, the data node DN will be at a low voltage and the output of the program-erase-verify circuit  54   e  will be at a high voltage state indicating that all the selected memory cells are erased. 
   While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.