Abstract:
The present invention provides the voltage generator comprises providing a binary weight digital-to-analog converter (DAC) including an R-2R ladder network, and control switches, and an operation amplifier (OP) with a feedback resistance, and providing a plurality of voltages, from an input of said ladder network, in a positive polarity and a negative polarity, wherein said positive polarity and negative polarity are determined by a reference voltage, and each of said switches is switched between a connection to said OP and said reference voltage.

Description:
BACKGROUND OF THE PRESENT INVENTION 
       [0001]    1. Field of Invention 
         [0002]    The present invention relates to a D/A Converter (digital-to-analog converter), more particularly to a D/A Converter for the display driver. 
         [0003]    2. Description of Related Arts 
         [0004]    For the conventional gamma voltage generator for the display driver of an LCD, a resister string is used. And in the display driver, there are multiple decoders for selecting the needed gamma voltages. The resister string and the decoders occupy a lot of area, and, therefore, there is a need to provide a new design to reduce the area of the gamma voltage generator. 
       SUMMARY OF THE PRESENT INVENTION 
       [0005]    The objective of the present invention is to reduce the area of a gamma voltage generator. 
         [0006]    An digital-to-analog converter for converting a digital signal into an analog voltage corresponding to a polarity signal, comprising: an operational amplifier having a first input node, a second input node and a output node for outputting the analog voltage, wherein the second input node receives a reference voltage; and an R-2R ladder network having a first node, a second node and a third node, the first node connected to the first input node of the operational amplifier, the second node receiving a reference voltage, and the third node selectively connected to a first voltage or a second voltage corresponding to the polarity signal, wherein the R-2R ladder network further comprises: a plurality of first resistors connected with a plurality of second resistors, said first resistors having a first resistance, and a said plurality of second resistors with having a second resistance, said second resistance is having a double value of said first resistance; and a plurality of switches respectively connecting the corresponding second resistors to the first input node of the operational amplifier, or to the reference voltage selectively, controlled by the digital signal. 
         [0007]    Another applied circuit structure of digital-to-analog converter for converting a digital signal into an analog voltage corresponding to a polarity signal, comprising: an operational amplifier having a first input node, a second input node and a output node for outputting the analog voltage, wherein the second input node receives a reference voltage; an R-2R ladder network having a first node, a second node and a third node, the first node connected to the first input node of the operational amplifier, the second node receiving a reference voltage, and the third node selectively connected to a first voltage or a second voltage corresponding to the polarity signal, wherein the R-2R ladder network further comprises: a plurality of first resistors connected with a plurality of second resistors, the first resistor having a first resistance and a plurality of second resistors with a second resistance, said second resistance is having a double value of said first resistance; and a plurality of switches respectively connecting the corresponding second resistors to the first input node of the operational amplifier, or to the reference voltage selectively, controlled by the LSB of the digital signal; and a thermometer-type circuit for processing the MSB of the digital signal, comprising: a reference current generator for generating a reference current based on the polarity signal; a plurality of transistors for generating the reference current; and a plurality of switches selectively connecting the transistors to the operational amplifier or the reference voltage, controlled by the MSB of the digital signal. 
         [0008]    One or part or all of these and other features and advantages of the present invention will become readily apparent to those skilled in this art from the following description wherein there is shown and described a preferred embodiment of this invention, simply by way of illustration of one of the modes best suited to carry out the invention. As it will be realized, the invention is capable of different embodiments, and its several details are capable of modifications in various, obvious aspects all without departing from the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  illustrates an embodiment of a D/A Converter of the present invention. 
           [0010]      FIG. 2  illustrates the relation of the input voltages and the output voltages. 
           [0011]      FIG. 3  illustrates the other embodiment of a D/A Converter of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0012]    Referring to  FIG. 1 , it is an embodiment of an n-bit digital-to-analog converter (DAC) with a R-2R ladder network. The DAC  100  in this embodiment is exemplified as a 6-bit DAC for converting a digital signal [b 5  . . . b 0 ] into an analog voltage Vout, based on a polarity signal P. The DAC  100  includes an operational amplifier  110 , and a R-2R ladder network  101 . The operational amplifier  110  has a first input node, a second input node and an output node for outputting the analog voltage. The DAC  100  also includes a resistor Rf connected between the first input node and output node of the operational amplifier  110 . Further, the DAC  100  may optionally include a capacitor Cf connected with the resistor Rf in parallel. The second input node receives a reference voltage Vref. The first input node of the operational amplifier is an inverting input node, and the second input node of the operational amplifier is a non-inverting input node. 
         [0013]    The R-2R ladder network  101  (inside an electric equipment&#39;s circuit) has a first node  151 , a second node  152  and a third node  153 . The first node  151  is connected to the first input node of the operational amplifier  110 , the second node  151  receives the reference voltage Vref, and the third node  153  is selectively connected to a first voltage V 1  or a second voltage V 2  via a switch SWP corresponding to the polarity signal P. In one embodiment, the first voltage V 1  is the power voltage VDD minus a threshold voltage, and the second voltage V 2  is the ground voltage VSS plus a threshold voltage. The threshold is 0.3V for example. 
         [0014]    The R-2R ladder network  101  further comprises a plurality of first resistors with a first resistance, denoted as R, and a plurality of second resistors with a second resistance, denoted as 2R. The plurality of first resistors connects with the plurality of corresponding second resistors. The second resistance is the double of the first resistance. 
         [0015]    The plurality of switches SW 0 -SW 5 , controlled by the digital signal [b 5  . . . b 0 ], selectively connect the corresponding second resistors to the first node of the operational amplifier  110  or the reference voltage Vref. 
         [0016]      FIG. 2  is a diagram of the input of the DAC versus the output of the DAC. While an output with a positive polarity is required, the DAC  100  outputs the analog voltage Vout in the range from VDD to Vref. While an output with a negative polarity is required, the DAC  100  outputs the analog Vout in the range from Vref to VSSA. Specifically, while an output with the negative polarity is required, the switch SWP connects the R-2R ladder network  101  to the first voltage V 1 , such that the output of the DAC  100  is: 
         [0000]    
       
         
           
             
               Vout 
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         [0000]    which has a negative polarity since V 1  is the power voltage VDDA minus the threshold, and the reference voltage Vref is the average of the power voltage VDDA and the ground voltage VSS. While an output with a positive polarity is required, the switch SWP connects the R-2R ladder network  101  to the second voltage V 2 , such that the output of the DAC  100  is: 
         [0000]    
       
         
           
             
               Vout 
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         [0000]    which has a positive polarity since V 2  is the ground voltage VSSA plus the threshold voltage. 
         [0017]      FIG. 3  is showing a circuit diagram of a DAC according to a second embodiment of the invention. The DAC  300  includes an operational amplifier  310 , a R-2R ladder network  301  for processing the LSB (least significant bits) of the digital signal, and a thermometer-type circuit  302  for processing the MSB (most significant bits) of the digital signal. In this embodiment, the LSB of the digital signal is [b 3  . . . b 0 ], and the MSB of the digital signal is [b 5 , b 4 ]. 
         [0018]    The operational amplifier  310  has a first input node  351 , a second input node  352  and a output node for outputting the analog voltage Vout. The DAC  300  also includes a resistor Rf connected between the first input node and output node of the operational amplifier  310 . Further, the DAC  300  may optionally include a capacitor connected with the resistor Rf in parallel. The second input node of the operational amplifier  310  receives a reference voltage Vref. The first input node of the operational amplifier  310  is an inverting input node, and the second input node of the operational amplifier  310  is a non-inverting input node. 
         [0019]    The R-2R ladder network  301  is connected to the first input node of the operational amplifier  310 . The R-2R ladder network  301  includes a plurality of first resistors with a first resistance, denoted as R, and a plurality of second resistors with a second resistance, denoted as 2R. The second resistance has the double value of the first resistance. The plurality of first resistors connects with the plurality of corresponding second resistors. 
         [0020]    The plurality of switches SW 0 -SW 3 , controlled by the digital signal [b 3  . . . b 0 ], selectively connect the corresponding second resistors to the first node of the operational amplifier  310  or the reference voltage Vref. 
         [0021]    The thermometer-type circuit  302  includes transistors Q 0 -Q 4 , switches SW 4 -SW 6 , a buffer  312  and a thermo code generator  314 . The first input of the buffer  312  selectively receives a first voltage V 1  or a, second voltage V 2  via the switch SWP controlled by a polarity signal P, and the output of the buffer  312  controls the gates of the transistors Q 0 -Q 4 . The transistors Q 0 -Q 4  respectively connects to resistors, each having the resistance of 2R. The transistor Q 4  is used as a reference current generator selectively controlled by the first voltage V 1  or the second voltage V 2  via the polarity switch SWP to generate a reference current such that the current flow through each of the transistors Q 0 -Q 3  is constant. 
         [0022]    The thermo code generator  314  generates codes M 1 , M 2  and M 3  according to the MSB of the digital signal [b 5 , b 4 ]. While [b 5 ,b 4 ]=[0,1], M 1  is asserted; while [b 5 ,b 4 ]=[1,0], M 1  and M 2  are asserted; while [b 5 ,b 4 ]=[1,1], M 1 , M 2  and M 3  are asserted. The switches SW 4 -SW 6  are respectively controlled by the codes M 1 -M 3  for selectively connects the transistors Q 1 -Q 3  to the first input node of the operational amplifier  310 , or to the reference voltage Vref. 
         [0023]    Specifically, suppose the current through the switch SW 0  is I, then the currents through the switches SW 1 , SW 2 , SW 3  are respectively 2I, 4I, and 8I, such that the current through transistor Q 0  is 16I. Since the currents respectively through transistors Q 0 -Q 4  should be the same, the current through each of transistors Q 0 -Q 4  is 16I. For a digital signal [011000], the code M 1  is asserted and the switch SW 3  connects the corresponding second resistor to the operational amplifier  310 , such that the current through the resistor Rf is 16I+8I=24I, and then Vout can be generated correspondingly. 
         [0024]    Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof. 
         [0025]    One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting. 
         [0026]    The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.