Abstract:
Disclosed is a voltage level shifter, including a pull-up circuit, a voltage drop circuit and a pull-down circuit. Through the voltage level shifter, an input voltage is transformed into an output voltage having a different level as compared to that of the input voltage. With the voltage drop circuit, voltages received by the pull-down circuit are reduced and thus transistors of thinner gates may be used, effectively improving switching speed of transistors in the pull-down circuit. As such, noise and jiggle of the output voltage are reduced.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention pertains to a circuit. More particularly, the present invention pertains to a voltage level shifter. 
   2. The Prior Arts 
   For a currently used integrated circuit (IC) system, a core logic unit and an input/output unit therein are generally supplied with different voltages. For example, the core logic unit is typically supplied with a voltage of 1.2 volts while the input/output devices with a voltage of 3.3 volts in a device fabricated by 0.13 μm manufacturing process. Since the voltages supplied to the core logic unit and input/output unit are not identical to each other, a conversion circuit is required to be provided between the two units. Such conversion circuit is generally termed as “voltage level shifter”. 
     FIG. 1  shows a conventional voltage level shifter. The voltage level shifter  10  includes PMOS transistors PG 1  and PG 2 , NMOS transistors NG 1  and NG 2  and an inverter INV. Herein, the PMOS transistors PG 1  and PG 2  are regarded as pull-up transistors while the NMOS transistors NG 1  and NG 2  are regarded as pull-down transistors. Now, assuming a supply voltage VccH is 3.3 volts and an input voltage Vin at an input I is between 0 and 1.2 volts of rectangular wave. When the input voltage Vin transits from a low level (ex. 0 volt) to a high level (ex. 1.2 volts), the NMOS transistor NG 1  is turned on and the PMOS transistor PG 2  is also turned on since a gate of the PMOS transistor PG 2  is driven to low level. Hence, a high level voltage (i0e. 3.3 volt) is presented at an output node O of the voltage level shifter  10 . Therefore, the voltage level shifter  10  is capable of shifting the input voltage Vin (i.e. 1.2 volts) into the output voltage Vout (i.e. 3.3 volts). However, since a specific period is required for a voltage of 0 volt being shifted into 1.2 volts, the PMOS and NMOS transistors PG 1 ,PG 2 ,NG 1  and NG 2  may not function as desired in the voltage level shifter  10  when their gate voltages are too low (lower than a threshold voltage, about 0.8 volts). In addition, during the time when the PMOS transistor PG 2  and NMOS transistor NG 2  are approaching to on (or off) and off (or on), contribution of the transistors PG 2 , NG 2  on the output voltage Vout compete. As such, the output voltage Vout is later in speed in reaching the low level, compared with only either of the PMOS transistor PG 2  and NMOS transistor NG 2  is present, causing distortion of the output wave. 
     FIG. 2  is provided to explain such case. When the input voltage Vin transits from the low level to the high level, the output voltage Vout is pulled to the high level after a delay time Tr. Also, when the input voltage Vin transits from the high level to the low level, the output voltage Vout decreases to the low level after a delay time Tf. 
   When noises of different levels are present on the input voltage Vin and thus the real input voltage Vin may not be maintained constant, distortion amount caused from the competition varies, leading to a shift on the transition time of the output voltage Vout, which is called “jiggle”. It is generally desirable to reduce such jiggle so as to have a better fidelity of the output wave with respect to the input wave. In addition, the output wave may vary as the noise amount on the input wave varies since the transistors in the voltage level shifter may function differently at this time as compared to that when no noise is present. It is desired to reduce such output wave deviation. 
   In addition, since the NMOS transistors NG 1 , NG 2  have a high voltage to endure, which is about 2.5 volts at its maximum, the gates thereof have to be thicker, thus leading to a higher threshold voltage. In this case, the NMOS transistors NG 1 , NG 2  have to have more time to switch from low to high. Therefore, it is desired to have a thinner gate for the pull-down transistors NG 1 , NG 2  so that they may have a faster switching speed. 
   SUMMARY OF THE INVENTION 
   A voltage level shifter having reduced noises and jiggle at an output thereof is provided. 
   The voltage level shifter includes a pull-up circuit, a voltage drop circuit and a pull-down circuit. The voltage drop circuit is used to reduce voltages which the pull-down circuit endures, making gate thickness of the pull-down transistors of the pull-down circuit allowed to be reduced. 
   The voltage level shifter includes a pull-up circuit, a voltage drop circuit, a path division circuit and a pull-down circuit. The path division circuit isolates a current between the pull-up and pull-down circuits at a time when an input voltage of the voltage level shifter transits from one level to the other level. Therefore, competence between the pull-up and pull-down circuits does not appear and thus noise amount and jiggle on an output voltage of the voltage level shifter are reduced. 
   The above and other objects, advantages and principle will be further explained below taken from the preferred embodiments with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawings disclose an illustrative embodiment of the present invention which serves to exemplify the various advantages and objects hereof, and are as follows: 
       FIG. 1  is a schematic diagram of a conventional voltage level shifter; 
       FIG. 2  is a schematic diagram of a waveform of the voltage level shifter shown in  FIG. 1 ; 
       FIG. 3  is a schematic diagram of a voltage level shifter according to an embodiment of the present invention; 
       FIG. 4  is a schematic diagram of the voltage level shifter according to another embodiment of the present invention; 
       FIG. 5   a  is a schematic diagram of a main conversion stage of the voltage level shifter according to still another embodiment of the present invention; 
       FIG. 5   b  is a schematic diagram of an input buffer stage of the voltage level shifter according to the embodiment, shown in  FIG. 5   a  of the present invention; 
       FIG. 5   c  is a schematic diagram of an output buffer stage of the voltage level shifter according to the embodiment, shown in  FIG. 5   a  of the present invention; and 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   A voltage level shifter having reduced noises and jiggle at an output thereof is provided in the invention. 
   Referring to  FIG. 3 , a voltage level shifter according to an embodiment of the present invention is shown therein. As shown, the voltage level shifter  30  includes a pull-up circuit  31 , a voltage drop circuit  33  and a pull-down circuit  34 . The pull-up circuit  31  has two PMOS transistors P 1  and P 2 . The voltage drop circuit  33  has four NMOS transistors N 1 , N 2 , N 3 , and N 4 . The pull-down circuit  34  has two NMOS transistors N 5  and N 6 . In this embodiment, a direct current (DC) voltage V PPIN  and a DC voltage source VDDIN are provided for the voltage level shifter  30 . The NMOS transistors N 5  and N 6  are connected to ground GND. In this configuration, an input voltage Vin is shifted into an output voltage Vout at node NT 1 . The DC voltage V PPIN  is 3.3 volts, the DC voltage V DDIN  is 1.2 volts, the input voltage Vin has a rectangular wave between 0 and 1.2 volts, and the output voltage Vout is a corresponding wave between 0 and 3.3 volts. In addition, the voltage level shifter  30  further includes an inverter INV (not shown) for providing a inversed input voltage Vinb, the inverse voltage of the input voltage Vin, and outputting a inversed output voltage Voutb at NT 2 . 
   When the input voltage Vin is transiting from high level to low level and the inversed input Vinb is transiting from low level to high level. At this time, the NMOS transistor NMOS is turned on while the NMOS transistor N 6  is turned off. However, such switch is not immediately finished. When a gate voltage of the NMOS transistors N 5 , N 6  do not exceed a threshold voltage (about 0.7 volts), the NMOS transistors N 5 , N 6  can not be turned on or off. At this time, the output voltage Vout is transiting from high level to low level and the PMOS transistor P 2  is turned on. On the other hand, the inversed output Voutb is transiting from low level to high level and the PMOS transistor P 1  is turned off. When the NMOS transistor N 5  becomes really turned on, the output Vout is reduced to low, enabling the PMOS transistor P 2  to be turned on. On the other hand, when the NMOS transistor N 6  is really turned off, the inversed output Voutb is pulled high, enabling the PMOS transistor P 1  to be turned off. Therefore, when the input voltage Vin is at the low level (ex. 0 volt), the output voltage Vout is also at the low level (i.e. 0 volt). When the inversed input voltage Vinb is at the high level (ex. 1.2 volts), the inverse output voltage Voutb is also at the high level (i.e. 3.3 volts). As such, the purpose of voltage shifting is achieved. 
   In addition, in the voltage drop circuit  33 , the NMOS transistors N 1 , N 2  has a thicker gate (corresponding to a threshold voltage about 0.8 volts), while the NMOS transistors N 3 , N 4  has a thinner gate (corresponding to a threshold voltage about 0.7 volts). Hence, the voltage provided by the pull-up circuit  31  is reduced by about 1.5 volts by the voltage drop circuit  33  when the NMOS transistors N 5 , N 6  are turned off; otherwise, there is no voltage drop when the NMOS transistors N 5 , N 6  are turned on. Consequently, the gate of the NMOS transistors N 5 , N 6  may be thinner and may be turned on by the input voltage Vin at an initial stage (when the input voltage Vin is still lower) when the input voltage Vin transits from low level to high level. Hence, the NMOS transistors N 5 , N 6  may be turned on in a relatively short time. Alternatively, the NMOS transistors N 1 , N 2 , N 3 , and N 4  may each be replaced with a diode (not illustrated) since the diode may also provide a voltage drop, which makes no difference with the NMOS transistors N 1 , N 2 , N 3 , and N 4 . 
   Referring to  FIG. 4 , the voltage level shifter according to another embodiment of the present invention is shown therein. In this embodiment, all elements of and DC voltages supplied for the voltage level shifter are the same with those for the embodiment shown in  FIG. 3  except that a path division circuit  42  is additionally provided. The path division circuit  42  is connected between the pull-up circuit  31  and the voltage drop circuit  33  and for isolating a current path between the pull-up circuit  31  and the pull-down circuit  34 . The path division circuit  42  includes PMOS transistors P 3  and P 4 . When the input voltage Vin transits from low level to high level, the NMOS transistor N 6  is turned on, the PMOS transistor P 1  is also turned on and the PMOS transistor P 3  is turned off. When the input voltage Vin rises sufficiently to turn off the PMOS transistor P 3 , a current path between the PMOS transistor P 1  and the NMOS transistor N 5  is isolated. Thus, the PMOS transistor P 1  cannot pull up the output voltage Vout any more but the NMOS transistor N 5  keeps pulling down the output voltage Vout. That is, the PMOS P 1  transistor does not compete with the NMOS transistor N 5  again when the current path is isolated. At this time, the output voltage Vout may be rapidly decreased to low level when the PMOS transistor P 3  is turned off. As such, the voltage level shifter may have reduced jiggle of transition time at the output end owing to an unstable input voltage Vin. 
   Referring to  FIG. 5   a ,  FIG. 5   b  and  FIG. 5   c , the voltage level shifter according to another embodiment of the present invention is shown therein. In this embodiment, the voltage level shifter  50  is composed of the voltage level shifter shown in  FIG. 3  and  FIG. 4  ( FIG. 5   a ) and an input stage buffer circuit  51  ( FIG. 5   b ) and an output stage buffer circuit  52  ( FIG. 5   c ). As shown, the input stage buffer circuit  51  includes PMOS transistors P 5  and P 6  and NMOS transistors N 7  and N 8 , wherein the PMOS transistor P 5  and the NMOS transistor N 7  constitute a first CMOS transistor, and the PMOS transistor P 6  and the NMOS transistor N 8  constitute a second CMOS transistor The output stage buffer circuit  52  includes a first output buffer circuit  52 ′ and a second output buffer circuit  52 ″. The first output buffer circuit  52 ′ includes PMOS transistors P 7 , P 8  and NMOS transistors N 9 , N 10 , wherein the PMOS transistor P 7  and the NMOS transistor N 9  constitute a third CMOS transistor, and the PMOS transistor P 8  and the NMOS transistor N 10  constitute a fourth CMOS transistor. The second output buffer circuit  52 ″ includes PMOS transistors P 9 , P 10  and NMOS transistors N 11 , N 12 , wherein the PMOS transistor P 9  and the NMOS transistor N 11  constitute a fifth CMOS transistor, and the PMOS transistor PlO and the NMOS transistor N 12  constitute a sixth CMOS transistor. In the voltage level shifter  50 , the input stage buffer circuit  51  and output stage buffer circuit  52  is provided to facilitate measurement of the output voltage Vout and inverse output voltage Voutb shown in  FIG. 3  and  FIG. 4 . In the voltage level shifter  50 , the first input buffer circuit  52 ′ and second output buffer circuit  52 ″ may be replaced with two inverters connected in series. As such, a buffered input voltage Vin 2  and buffered output voltages Voutb and Vout may also be obtained. In addition, the output voltage Voutb is obtained from a voltage presented at a node NT 2 , which is buffered at the first output buffer circuit  52 ′. Similarly, the output voltage Vout is obtained from a voltage presented at a node NT 1 , which is buffered at the second output buffer circuit  52 ″. 
   Many changes and modifications in the above described embodiment of the invention can, of course, be carried out without departing from the scope thereof. Accordingly, to promote the progress in science and the useful arts, the invention is disclosed and is intended to be limited only by the scope of the appended claims. For example, the transistors mentioned above may be replaced with tri-terminal switches. The essential principle of the invention may also be applied onto a voltage level shifter which has a lower output as compare to its input. In this case, the voltage drop transistors are not required and the applied DC voltages should be adjusted in such a manner that the voltage level shifter may operate properly. In this regard, the scope of the invention should be otherwise defined by the claims provided below.