Abstract:
A semiconductor wafer is diced utilizing a method that etches down to the top surface of the semiconductor wafer a number of times, such as during and following the formation of the metal interconnect structure, and then thins the semiconductor wafer from the back side until the semiconductor wafer singulates.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method of dicing a semiconductor wafer and, more particularly, to a method of dicing a semiconductor wafer that substantially reduces the width of the saw street. 
   2. Description of the Related Art 
   The final back-end processing of a semiconductor wafer typically includes the step of back grinding the wafer (removing a portion of the back side of the wafer to reduce the thickness of the wafer). In addition, the processing also commonly includes the step of bumping the wafer (adding solder bumps to the pads formed on the top surface of the wafer). 
   The last wafer processing step is the dicing or cutting of the wafer to form a large number of individual die. Each die is then placed in a package, such as a flip-chip package when the die has been bumped, to form a semiconductor chip. The wafer is typically diced to form the large number of individual die by using a wafer saw that physically cuts completely through the wafer to form openings, known as “saw streets,” between the individual die. 
   Current-generation wafer saws provide a minimum street width of two mils (50.8×10 −6  m) between adjacent die. Since a large number of die are formed when the wafer is diced or cut, the cumulative amount of wafer real estate lost to saw streets is significant. As a result, there is a need for a method of dicing a semiconductor wafer that consumes less area than a saw street. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a plan view illustrating an example of a semiconductor wafer  100  at an initial processing step in accordance with the present invention. 
       FIGS. 2A–2J  are cross-sectional views taken along line  2 — 2  of  FIG. 1  that illustrate an example of a method of dicing wafer  100  in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  shows a plan view that illustrates an example of a semiconductor wafer  100  at an initial processing step in accordance with the present invention.  FIGS. 2A–2J  show cross-sectional views taken along line  2 — 2  of  FIG. 1  that illustrate an example of a method of dicing wafer  100  in accordance with the present invention. 
   As shown in  FIGS. 1 and 2A , semiconductor wafer  100  includes a top surface  110 , a bottom surface  112 , and rows and columns of die regions  114  that contact top surface  110 . The die regions  114  have substantially equivalent semiconductor structures such that, at the end of the fabrication process, each die region  114  realizes the same circuit. 
   For example, as shown in  FIG. 2A , each die region  114  can have an identically-located MOS transistor  116 , and a shallow trench isolation region STI that surrounds MOS transistor  116 . MOS transistor  116 , in turn, has spaced-apart n+ source and drain regions  120 A and  120 B that are formed in a p-type semiconductor material, and a channel region  122  of the p-type material that lies between each source and drain region  120 A and  120 B. MOS transistor  116  also has a layer of oxide  124  that is formed on the top surface  110  of semiconductor wafer  100 , and a conductive gate  126  that is formed on the layer of oxide  124  over channel region  122 . 
   The method of the present invention begins by depositing a layer of isolation material  132 , such as a layer of oxide, on the top surface  110  of semiconductor wafer  100  over the die regions  114  and the transistors  116 . Following this, an etch mask  134  is formed and patterned on the layer of isolation material  132 . 
   Next, as shown in  FIG. 2B , the exposed regions of isolation material  132  are etched until the layer of isolation material  132  has been removed from the top surface  110  of semiconductor wafer  100 . The etch forms a large number of contact openings within each die region  114 , as represented by a pair of contact openings  136 A and  136 B that expose the source and drain regions  120 A and  120 B, respectively, in each die region  114 . 
   The etch of the exposed regions of isolation material  132  also forms a street opening  136 C that exposes a street region on the top surface  110  of wafer  100  that lies between adjacent die regions  114 . Further, the etch that forms street opening  136 C also vertically weakens wafer  100  along a stress line  138  that extends from the street region vertically down towards the bottom surface  112  of wafer  100 . Mask  134  is then removed. 
   After mask  134  has been removed, a layer of contact material is deposited onto the top surface of isolation material  132  to fill up the contact openings, such as openings  136 A and  136 B, and the street opening  136 C. As shown in  FIG. 2C , the layer of contact material is then planarized to remove the layer of contact material from the top surface of isolation material  132 , thereby forming contacts  140  in the contact openings, such as openings  136 A and  136 B, and a contact grid  142  in the street opening  136 C. Next, a layer of metal  144 , which can include aluminum or copper, is deposited on the top surface of isolation material  132 . An etch mask  146  is then formed and patterned on the layer of metal  144 . 
   Following this, as shown in  FIG. 2D , the exposed regions of the layer of metal  144  are etched to remove the layer of metal  144  from the top surface of isolation material  132 . The etch forms a large number of metal-1 traces within each die region  114 , as represented by metal-1 traces  148 A and  148 B. 
   The etch also removes the layer of metal  144  from over contact grid  142 , and continues until contact grid  142  is removed from the top surface  110  of wafer  110 . The removal of contact grid  142  reopens street opening  136 C which, in turn, again exposes the top surface  110  of semiconductor wafer  100 . In addition, the etch that reopens street opening  136 C further vertically weakens wafer  100  along stress line  138 . Mask  146  is then removed. 
   As shown in  FIG. 2E , after mask  146  has been removed, a layer of isolation material  152  is deposited onto the top surface of isolation material  132  and the metal-1 traces, such as metal-1 traces  148 A and  148 B. Following this, an etch mask  154  is formed and patterned on the layer of isolation material  152 . 
   Next, as shown in  FIG. 2F , the exposed regions of isolation material  152  are etched until the layer of isolation material  152  has been removed from the top surface  110  of semiconductor wafer  100 . The etch forms a large number of via openings within each die region  114 , as represented by a pair of via openings  156 A and  156 B, that expose a corresponding number of regions on the metal-1 traces in each die region  114 . 
   The etch of the exposed regions of isolation material  152  also reopens street opening  136 C and again exposes the top surface  110  of semiconductor wafer  100 . Further, the etch through isolation material  152  to reopen street opening  136 C additionally vertically weakens wafer  100  along stress line  138 . Mask  154  is then removed. 
   After mask  154  has been removed, a layer of inter-metal material is deposited onto the top surface of isolation material  152  to fill up the via openings, such as openings  156 A and  156 B, and the street opening  136 C. As shown in  FIG. 2G , the layer of inter-metal material is then planarized to remove the layer of inter-metal material from the top surface of isolation material  152 , thereby forming vias  160  in the via openings, such as openings  156 A and  156 B, and a via grid  162  in street opening  136 C. Next, a layer of metal  164 , which can include aluminum or copper, is deposited on the top surface of isolation material  152 . An etch mask  166  is then formed and patterned on the layer of metal  164 . 
   Following this, as shown in  FIG. 2H , the exposed regions of the layer of metal  164  are etched to remove the layer of metal  164  from the top surface of isolation material  152 . The etch forms a large number of metal-2 traces within each die region  114 , as represented by metal-2 traces  168 A and  168 B. 
   The etch also removes the layer of metal  164  from over via grid  162 , and continues until via grid  162  is removed from the top surface  110  of wafer  110 . The removal of via grid  162  reopens street opening  136 C which, in turn, again exposes the top surface  110  of semiconductor wafer  100 . In addition, the etch that reopens street opening  136 C further vertically weakens wafer  100  along stress line  138 . Mask  166  is then removed. 
   The above steps can be repeated as necessary to form as many layers of metal as are required. For purposes of illustration, only two metal layers are shown. Thus, after mask  166  has been removed, a layer of insulation material  172  is deposited onto the top surface of isolation material  152  and the metal-2 traces, such as metal-2 traces  168 A and  168 B. 
   Once the layer of insulation material  172  has been deposited, an etch mask  174  is then formed and patterned on the layer of insulation material  172 . Next, as shown in  FIG. 2I , the exposed regions of the layer of insulation material  172  are etched until the layer of insulation material  172  has been removed from the top surface  110  of semiconductor wafer  100 , thereby again exposing street opening  136 C and again weakening wafer  100  along vertical stress line  138 . 
   Mask  174  is then removed. After mask  174  has been removed, a layer of adhesive tape  176  is attached to the top surface of insulation material  172 . Following this, as shown in  FIG. 2J , semiconductor wafer  100  is thinned by removing a portion of the bottom surface  112  of wafer  100 . 
   Semiconductor wafer  100 , in turn, can be thinned using conventional approaches, such as back grinding and polishing. Current-generation back grinding processes can reduce the thickness of a wafer to approximately six mils (152.4×10 −6  m), while current-generation polishers can further reduce the thickness of the wafer to less than three mils (76.2×10 −6  m). 
   In accordance with the present invention, semiconductor wafer  100  is thinned until wafer  100  singulates along vertical stress line  138 , thereby forming a large number of individual die  180 . As noted above, when street opening  136 C is formed and the top surface  110  of semiconductor wafer  100  is exposed, the etch process used to form street opening  136 C vertically weakens wafer  100  along stress line  138 , which lies below the street region that lies between the adjacent die regions  114 . 
   Each subsequent time street opening  136 C is reopened and the top surface  110  of semiconductor wafer  100  is exposed, the etch process used to reopen street opening  136 C further vertically weakens wafer  100  along stress line  138  by increasing the vertical stress placed on stress line  138 . 
   In accordance with the present invention, by etching down to expose the top surface  110  of semiconductor wafer  100  a number of times during the fabrication process, sufficient cumulative stress can be placed in semiconductor wafer  100  to vertically weaken wafer  100  along stress line  138  such that wafer  100  can singulate when the thickness of wafer is reduced to, for example, less than three mils. 
   Returning to the present method, after wafer  100  has been singulated, adhesive tape  176 , which has an elastic quality, is stretched slightly to separate the individual die  176 . Following this, a pick and place machine can individually pick a die  176  from tape  176 , and place the die  176  in a package. 
   One of the advantages of the present invention is that the present invention provides a significant reduction in the area required by a saw street. For example, in a conventional case where a physical saw is utilized, assume a die size of 20 mils (508×10 −6  m) and a 2 mil (50.8×10 −6  m) saw street. In this case, the area of a wafer required by a die is 22 mils (558.8×10 −6  m) square (or 484 square mils of area). 
   On the other hand, in the present invention, assume a die size of 20 mils (508×10 −6  m) and a 0.01 mil (0.244×10 −6  m) wide saw street. (Smaller street widths can also be used.) In this case, the area of the wafer required by the die is only 20.01 mils (508.244×10 −6  m) square (or 400.4 square mils of area). As a result, the present invention provides a 17% reduction in area when a 0.01 mil (0.244×10 −6  m) wide street is used. Thus, by utilizing the process of the present invention, significantly more dice can be obtained from a single semiconductor wafer. 
   Another advantage of the present invention is that the present invention eliminates the wafer sawing step required by conventional fabrication processes. The time and cost required to conventionally dice a semiconductor wafer can rival the time and cost required to fabricate the dice. Thus, by eliminating the need to physically saw a semiconductor wafer, a significant amount of time and cost can be saved. 
   It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.