Abstract:
Implementations related to systems, devices, and methods that make use of a master slave arrangement are described.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority to, and the benefit of, U.S. Provisional Application No. 60/939,264 filed May 21, 2007, titled “Asymmetric Master Slave Interface,” the entire contents of which are incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    Many systems and architectures involve communication of high bandwidth information between a mainstream technology-based analog front-end, containing an analog-to-digital (AD) converter, and a high end technology based System-On-Chip (SOC). Previous implementations facilitated this communication through use of a slow parallel bus interface or by applying a different architecture in which the AD conversion is implemented on the SOC. 
         [0003]    Parallel bus implementations become physically unmanageable and expensive for high bandwidths. Typically, such a wide bus must be implemented with single ended signaling, which is critical for Electromagnetic Emission (EME) in an application where the analog front-end is sensitive. 
         [0004]    When AD conversion is implemented on the SOC, the increasing use of lower supply voltages and deeper submicron technologies make the use and design of implementable AD converters very challenging, and it is difficult for the analog design to keep up with fast shrinking technologies used for SOC development. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0005]    The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items. 
           [0006]      FIG. 1   a  shows an exemplary mobile device operable to wirelessly communicate with various communication devices. 
           [0007]      FIG. 1   b  is a schematic representation of a device having master and slave devices. 
           [0008]      FIG. 2  is a block diagram illustrating a master device interfaced with a slave device. 
           [0009]      FIG. 3  illustrates a schematic diagram including a master device interfaced with a slave device. 
           [0010]      FIG. 4  shows an exemplary method of reducing overall power consumption in a master-slave system. 
       
    
    
     DETAILED DESCRIPTION  
       [0011]    Disclosed herein are systems, devices and techniques in which a master device is configured to generate a clock signal and a slave device is coupled to the master device and configured to receive the clock signal. The clock signal may control data behavior associated with the master device and the slave device. 
         [0012]    At least one implementation described herein enables the communication of information between a slave device having a first power consumption rate and a master device having a second power consumption rate that is lower than the first power consumption rate. The master device may be a deep submicron technology based device and the slave device may be an analog front-end technology based device. As used herein, a deep submicron technology based device refers to a device that is manufactured by processing techniques that are more complex (e.g., at a 45 nm level, a 65 nm level, and so forth) than the processing techniques (e.g., at a 90 nm level, a 130 nm level, and so forth) used to manufacture the front-end technology based device. 
         [0013]    In accordance with one implementation, the master device is coupled to the slave device and the master device includes a clock generating unit to generate a clock signal. The slave device is configured to receive and use the clock signal generated by the first device to control data behavior. More particularly, in at least one implementation, the slave device does not incorporate a clock generating unit, which reduces overall power consumption. 
       Exemplary Environment 
       [0014]      FIG. 1   a  shows a wireless device  100  that is operable to send and receive signals  102  in multiple modes. The multiple modes (e.g., GSM, UMTS, and so forth) may be utilized for communication with communications points such as a base station  104 , a satellite  106 , a wireless access point (WAP)  108 , Bluetooth (BT) headset  110 , and/or other commutation devices through the use of wireless signals  102 , which may be, for example, radio signals. 
         [0015]    The wireless device  100  may be a cellular phone, wireless media device, or other device capable of receiving and/or transmitting a radio or other wireless signal  102 . For example, the wireless device  100  may be a personal digital assistant (PDA), a portable computing device capable of wireless communication, a media player device, a portable gaming device, a personal computer, a wireless access point (WAP) and/or any other suitable device. 
         [0016]    The wireless device  100  includes one or more antennas  112  that may be configured for communication with the base station  104 , satellite  106 , WAP  108 , BT headset  110 , and so forth. For example, the wireless device  100  may communicate using a GSM or UMTS mode with the base station  104  as part of a cellular network, in which the base station  104  represents a cellular phone tower or other device capable of transmitting and/or receiving one or more radio or other wireless signals  102  within a cell of a cellular network. The wireless device  100  may also communicate with the BT headset  110  using a BT mode for transmitting and receiving. The wireless device  100  may additionally or alternatively communicate with other communication points using the one or more antennas  112 , which may be configured as a multiple-input multiple-output (MIMO), multiple-input single-output (MISO), and/or single-input multiple-output (SIMO) system to transmit and/or receive one or more signals  102  in one or more modes. 
       Exemplary Device 
       [0017]      FIG. 1   b  shows an exemplary wireless device  100 , including a master device  130  and one or more slave devices  132 . The wireless device  100  may be a cellular phone, wireless media device, personal computer or other electronic device. For example, the wireless device  100  may be a personal digital assistant (PDA), a media player device, a portable gaming device, a GPS device, a wireless access point (WAP) and/or any other suitable device. 
         [0018]    The master device  130  may include a processor; the slave device  132  may include signal processing components. The signal processing components of slave device  132  process signals received from various sources associated with device  100  including, but not limited to, a master device  130 , an antenna  134 , memory  136 , a user interface  138 , and so forth. The slave device  132  may include one or more components to perform analog-to-digital conversion, such as for example an analog to digital converter (ADC)  140 . 
         [0019]    It will be appreciated by one skilled in the art that  FIG. 1   a  is an exemplary schematic. Thus, certain details of the device  100 , including ADC  140 , have been omitted for simplicity of discussion. 
       Exemplary System 
       [0020]      FIG. 2  shows a block diagram of an example of a master-slave system  200 . Exemplary master-slave system  200  comprises a master device  210  coupled to or interfaced with a slave device  220 . One of more data lines  212  may be implemented from master device  210  to slave device  220 , and one or more data lines  214  may be implemented from slave device  220  to master device  210 . Master-slave system  200  may be implemented in single multiple-chip package, multiple single-chip packages, multiple multiple-chip packages, or other types of packages and/or configurations. 
         [0021]    Master device  210  comprises, in one embodiment, a deep submicron technology based device, such as a system-on-chip (SOC) or microcontroller device. Slave device  220  may be an analog front-end device such as a remote sensor or an actuator. Slave device  220  may include an Analog to Digital Converter (ADC)  222 . 
         [0022]    The exemplary master-slave system  200  may also be part of a wireless communications device such as the wireless device  100  shown in  FIGS. 1   a  and  1   b . For example, master device  210  may be a processor, microcontroller, or baseband device that operates generally in the digital realm. Slave device  220  may be a signal processing component such as a digital subscriber line (DSL) driver device, a virtual local area network (VLAN) interface, a Universal Mobile Telecommunications System (UMTS) interface, remote sensor, remote actuator, or a Global System for Mobile Communications (GSM) interface. 
         [0023]    Master device  210  may be implemented using deep submicron technology (e.g., 45 nm, 65 nm, and so forth) and slave device  220  may be implemented using technologies of less complexity (e.g., 90 nm, 130 nm, and so forth) as that of master device  210 . The different technologies used to implement the devices may result in master device  210  being more power efficient than slave device  220 . In one embodiment, slave device  220  operates at a first power consumption rate, and master device  210  operates at a second power consumption rate that is lower than the first power consumption rate. To reduce overall power consumption of the master-slave system, the clock generating unit may be incorporated in master device  210 . More particularly, in at least one implementation, the slave device  220  does not incorporate a clock generating unit. The clock generating unit in the master device  210  generates a clock signal  230  to control data behavior associated with master device  210  and slave device  220 . Clock signal  230  is transported from the master device  210  to slave device  220 , hereinafter referred to as the forwarded clock. 
         [0024]    The slave device  220  may transmit data associated therewith back to master device  210  by directly using the forwarded clock  230  it receives from master device  210 . Slave device  220  may directly sample the data received from master device  210  using the forwarded clock  230 . Further, slave device  220  may generate and transmit to master device  210  phase error information to adjust or pre-skew the forwarded clock  230  to achieve correct data sampling. 
         [0025]    The master-slave system  200  illustrated in  FIG. 2  may also perform clock and data recovery on a duty cycled basis to reduce average circuit activity. Furthermore, the system  200  may include a digital filter sublayer  224  to perform pre-filtering of the phase error information in the slave device  220  before passing phase error information back to master device  210  in-band. The digital filter sublayer  224  may comprise filter circuits (e.g., equalizer) to improve data sampling and/or transmission. In addition, the system may perform local clock or data recovery techniques in master device  210  based on the phase error information received from slave device  220 . Interface sublayers  226   a  and  226   b  may be utilized to facilitate communication between the master device  210  and the slave device  220 . 
         [0026]    The exemplary system  200  may utilize high speed differential signaling to reduce the number of chip pins required, with equalization in the receiver to compensate for band limitation in the connecting channel. System  200  may also implement asymmetric clock architecture to take advantage of the low power capability of the deeper submicron technology in master device  210 . The system is capable of transmitting a full rate (e.g., 3 gigahertz (GHz) for 3 gigabits per second (Gbps) links) forwarded clock  230  from master device  210  to slave device  220 . The full rate clock allows simple use of the clock in the slave device  220 . Clock and data ranges of about 1 to 10 GHz and 1 to 10 Gbps, respectively, are also possible with the illustrated system. Higher or lower clock and data ranges than those given are also possible depending on technologies used to implement the system. 
         [0027]      FIG. 3  illustrates one specific implementation of the master-slave system  200 . Master device  210  and slave device  220  communicate information via interconnect links  310   a - c . Interconnect links  310   a - c  comprise, for example, data links  310   a - b  and forwarded clock link  310   c . Data information is transmitted between master device  210  and slave device  220  via data links  310   a - b . Although four data links  310   a  from master device  210  to slave device  220  and four data links  310   b  from slave device  220  to master device  210  are shown, it is understood that any other number of data links are also useful. The data links may transmit information at a high speed of about, for example, 1 to 10 Gbps. Other communication speeds are also possible. The data links may be implemented with low swing, ground reference differential signaling. 
         [0028]    In one embodiment, a clock generating unit, such as a phase locked loop (PLL)  315 , is incorporated in the master device  210 . Although a PLL  315  is shown, it is understood that the clock signal may be generated by other types of clock signal generating units. PLL  315  generates a clock signal  230  to control data behavior associated with master device  210  and slave device  220 . Clock signal  230  may comprise a frequency of about 1 to 10 GHz. Other clock frequencies are also possible. Clock signal  230  is transmitted to slave device  220  as a forwarded clocked signal  230  via forwarded clock link  310   c.    
         [0029]    The forwarded clock signal  230  may be used directly in the slave device  220 . Alternatively, the frequency of the forwarded clock signal  230  may be increased (e.g., doubled) in the slave device before being used to control data behavior. In addition, slave device  220  may use the forwarded clock signal  230  directly to sample or transmit data received from the master device or other devices. Either or both of the rising or falling edges of the forwarded clock signal  230  may be used to control data behavior. Slave device  220  may also include small duty cycle correction circuitry for use in conjunction with the forwarded clock. 
         [0030]    As shown in  FIG. 3 , the forwarded clock signal  230  drives or enables latches  311 - 314  to transmit information between master device  210  and slave device  220  via data links  310   a - b . For example, when enabled by clock signal  230 , latches  311  in master device  210  transmit received data through respective buffers  305  and data links  310   a  to latches  313  in slave device  220 . Similarly, latches  314  in slave device  220  transmit received data through respective buffers  305  and data links  310   b  to latches  312  in master device  210 . Latches  311  to  314  may be enabled by either the rising or falling edge of the forwarded clock signal  230 . 
         [0031]    In one implementation, slave device  220  further includes a clock and data recovery (CDR) unit  320   a . Master device  210  may also further include a CDR unit  320   b . CDR unit  320   b  provides control signals  342  to control phase generators  318 . CDR unit  320   b  may be configured to control phase generators  318  independently. Phase generators  318  operate to adjust the phase of the clock signal  230  produced by clock generation unit  315 . This is done so as to, for example, ensure correct sampling of data received in master device  210 . 
         [0032]    In one implementation, phase generators  318  phase-shift clock signal  230  to produce pre-skew clock signals  340   a - h  to clock or enable local circuit elements such as latches  311  and  312 . Latches  311  and  312  respectively transmit data to and receive data from the slave device  220 . Pre-skew clock signals  340   a - h  may be generated by the phase generators  318  using various types of methods, including using a phase interpolation technique or a delay-locked loop (DLL) and multiplexer. 
         [0033]    CDR unit  320   a , associated with slave device  220 , generates phase error information to correct the clock signal  230  in the master device  210 . In one implementation, CDR unit  320   a  compares data input signals and determines if there are any phase errors. For example, it may perform an XOR based early/late phase detection using data signal edge samples. Other types of phase detection methods or architectures may also be used. This early/late phase information may be filtered to generate phase error information at a slow rate. The phase error information may be periodically transmitted back to the master device  210  in-band. In one embodiment, the slave device  220  includes multiplexers  333  that multiplex the phase error information with received data bits into a composite data stream. The composite data stream is transmitted via latches  314 , buffers  305  and second data links  310   b  to latches  312  in the master device  210 . 
         [0034]    Master device  210 , after initialization, is aware of the time division multiplexing and extracts this phase error information using, for example, demultiplexers  322 . The phase error information is then used by second CDR unit  320   b  to adjust the phase generators  318  accordingly. Second CDR unit  320   b  may also generate phase error information by, for example, performing XOR based phase detection, and filtering. However, the phase error information is directly used to steer the sampling clock locally. 
         [0035]    Master device  210  may further include filter circuits, such as an equalizer (not shown). The equalizer compensates for distortion of the data signals that may occur during high speed transmission. The equalizer may be, for example, a decision feedback equalizer, which is well understood by one skilled in the art. In one implementation, the equalizer provides a pre-equalizer function. The pre-equalizer function can be, for example, an infinite impulse response filter function or any other suitable function. The coefficients of the pre-equalizer function may be determined based on decision feedback from the slave device. 
       Exemplary Process 
       [0036]    An exemplary process in accordance with the present disclosure will now be described. For simplicity, the process will be described with reference to the exemplary environment  100  and the exemplary system  200  described above with reference to  FIGS. 2 through 3 . 
         [0037]      FIG. 4  shows one exemplary implementation of a process  400  for reducing overall power consumption in a master-slave system. The method may be implemented utilizing system  200  as shown in  FIGS. 2 and 3  and may be applied to operation of transmitting or receiving signals. The master-slave system includes a master device having a first power consumption rate and a slave device having a second power consumption rate, the first power consumption rate being lower than the second power consumption rate. 
         [0038]    At  402 , the master device generates a clock signal. Clock generation is performed in the master device, which is more power efficient than the slave device, in order to reduce overall power consumption of the master-slave system. 
         [0039]    At  404 , the master device transmits the clock signal to the slave device. The clock signal may be transmitted at a full rate of, for example, about 1 to 10 GHz. 
         [0040]    At  406 , the slave device uses the clock signal from the master device to control data behavior. The clock signal may be used directly by the slave device, without any modification. Alternatively, the frequency of the clock signal may be increased or decreased before using it to control data behavior. The slave device transmits or receives data from, for example, the master device in response to the clock signal. The slave device uses either or both of the rising and falling edge of the clock signal to control, sample or transmit the data. 
         [0041]    At  408 , the slave device generates phase error information of the clock signal and transmits the error information to the master device. The phase error information may be generated using samples of data signals using, for example, XOR based early/late phase detection techniques. This phase error information may be periodically transmitted back to the master device in-band. In one embodiment, the slave device multiplexes the phase error information with the data information to produce a composite data stream. The composite data stream is then transmitted to the master device. 
         [0042]    At  410 , the master device adjusts the phase of the clock signal in response to the phase error information. This is done, for example, to ensure accurate data sampling. The master device may first extract the phase error information from the composite data stream, such that it can use the phase error information to adjust the clock signal accordingly. In one implementation, the master device also generates phase error information for adjusting the clock signal locally. 
         [0043]    Although specific details of exemplary methods have been described above, it should be understood that certain acts need not be performed in the order described, and may be modified, and/or may be omitted entirely, depending on the circumstances. Moreover, the acts described may be implemented by a computer, processor or other computing device based on instructions stored on one or more computer-readable media. The computer-readable media can be any available media that can be accessed by a computing device to implement the instructions stored thereon. 
       Conclusion 
       [0044]    For the purposes of this disclosure and the claims that follow, the terms “coupled” and “connected” may have been used to describe how various elements interface. Such described interfacing of various elements may be either direct or indirect. Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.