Abstract:
A level shifter consisting of first to fifth transistors is provided. First ends of the first and second transistors are coupled to a first supply voltage. Control ends of third and fourth transistors respectively receive first and second input signals. First ends of the third and fourth transistors are respectively coupled to control ends of the second and first transistors, and are respectively coupled to second ends of the first and second transistors. Second ends of the third and fourth transistors are coupled to a second supply voltage. The first ends of the third and fourth transistors respectively output first and second output signals. A first end and a control end of the fifth transistor are coupled to the control ends of one and the other of the first and second transistors. A second end of the fifth transistor is coupled to the second supply voltage.

Description:
[0001]    This application claims the benefit of Taiwan application Serial No. 97112337, filed Apr. 3, 2008, the subject matter of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates in general to a level shifter and a circuit using the same, and more particularly to a level shifter with the low current consumption and the low complexity, and a circuit using the same. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 1  (Prior Art) is a circuit diagram showing a conventional level shifter  100  with a front-stage inverter and a post-stage inverter. Referring to  FIG. 1 , the level shifter  100  includes two N-type metal-oxide semiconductor (NMOS) transistors  110  and  120 , and two P-type metal-oxide semiconductor (PMOS) transistors  130  and  140 . The level shifter  100  is driven by a supply voltage VH. The gates of the transistors  110  and  120  respectively receive input signals A and A′. The input signals A and A′ are respectively an input and an output of a front-stage inverter  150 . In a normal state, the input signals A and A′ have inverse phases. The sources of the transistors  110  and  120  are grounded. The drains of the transistors  110  and  120  are respectively coupled to the drains of the transistors  130  and  140 , respectively coupled to the gates of the transistors  140  and  130 , and respectively output output signals B′ and B. In the normal state, the output signals B and B′ have inverse phases. The sources of the transistors  130  and  140  receive the supply voltage VH. The output signal B is outputted to a post-stage inverter  160 , which is a complementary metal-oxide semiconductor (CMOS) inverter and includes a PMOS transistor  161  and an NMOS transistor  162 . The post-stage inverter  160  generates an output signal x, which is an inverse of the output signal B. 
         [0006]    The front-stage inverter  150  is driven by a supply voltage VL, which is lower than the supply voltage VH and is generated by a voltage generator according to the supply voltage VH. The supply voltage VH is generated before the supply voltage VL is generated. The level shifter  100  receives the input signals A and A′ with the lower levels, and outputs the output signals B and B′ with the higher levels. 
         [0007]    However, the supply voltage VH has been generated in an initial state, and the input signals A and A′ are at the low levels when the supply voltage VL has not been generated. So, the transistors  110  and  120  are turned off, and the output signals B and B′ are pulled up to the intermediate levels (VH-Vthp) with the increase of the supply voltage VH, wherein Vthp is the threshold voltage of the transistors  130  and  140 . 
         [0008]    Thus, the output signal B at the intermediate level causes the two transistors  161  and  162  of the post-stage inverter  160  to turn on simultaneously so that high currents simultaneously flow through the transistors  161  and  162 . Thus, the voltage source of the supply voltage VH has the high current consumption. More seriously, the supply voltage VH cannot be kept at the correct level so that the supply voltage VL also cannot be kept at the correct level. 
         [0009]    On the other hand, when the supply voltages VH and VL are changed from the normal state to a power-saving state, the supply voltage VL stops supplying the electric power. At this time, the input signals A and A′ of the level shifter  100  are turned into the low levels so that the transistors  110  and  120  are turned off. At this time, the output signal, which is originally kept at the low level, is pulled up to the intermediate level. Thus, the post-stage inverter  160  has the malfunction, and the voltage source of the supply voltage VH has the high current consumption. 
       SUMMARY OF THE INVENTION 
       [0010]    The invention is directed to a level shifter, which can operate normally in an initial state, a normal state and a power-saving state and has the properties of the low circuit complexity and the low power consumption. 
         [0011]    According to a first aspect of the present invention, a level shifter consisting of first to fifth transistors is provided. First ends of the first and second transistors are coupled to a first supply voltage. Control ends of the third and fourth transistors respectively receive a first input signal and a second input signal. A first end of the third transistor is coupled to a control end of the second transistor. A first end of the fourth transistor is coupled to a control end of the first transistor. The first ends of the third and fourth transistors are respectively coupled to second ends of the first and second transistors. Second ends of the third and fourth transistors are coupled to a second supply voltage. The first end of the third transistor is for outputting a first output signal. The first end of the fourth transistor is for outputting a second output signal. The fifth transistor has a first end coupled to the control end of one of the first and second transistors, a control end coupled to the control end of the other of the first and second transistors, and a second end coupled to the second supply voltage. 
         [0012]    According to a second aspect of the present invention, a circuit consisting of a logic unit, a complementary metal-oxide semiconductor (CMOS) inverter, a level shifter and a voltage generator is provided. The logic unit generates a first input signal and a second input signal. The level shifter has an output end and includes first to fifth transistors. First ends of the first and second transistors are coupled to a first supply voltage. Control ends of the third and fourth transistors respectively receive the first input signal and the second input signal. A first end of the third transistor is coupled to a control end of the second transistor. A first end of the fourth transistor is coupled to a control end of the first transistor. The first ends of the third and fourth transistors are respectively coupled to second ends of the first and second transistors. Second ends of the third and fourth transistors are coupled to a second supply voltage. The first end of the third transistor is for outputting a first output signal. The first end of the fourth transistor is for outputting a second output signal to a second inverter. The first end of the fourth transistor or the first end of the third transistor serves as the output end. The fifth transistor has a first end coupled to the control end of one of the first and second transistors, a control end coupled to the control end of the other of the first and second transistors, and a second end coupled to the second supply voltage. The voltage generator receives the first supply voltage and generates a third supply voltage inputted to the logic unit. When the logic unit is driven by the third supply voltage, the first and second input signals have inverse phases, and a higher one of levels of the first input signal and the second input signal is substantially equal to the level of the third supply voltage. When the logic unit is not powered by the third supply voltage, the first and second input signals outputted by the logic unit have low levels. The output end of the level shifter is electrically connected to the CMOS inverter. 
         [0013]    The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  (Prior Art) is a circuit diagram showing a conventional level shifter with a front-stage inverter and a post-stage inverter. 
           [0015]      FIG. 2  is a circuit diagram showing a level shifter and its logic unit according to an embodiment of the invention. 
           [0016]      FIG. 3  shows an example of waveforms of a supply voltage and output signals of  FIG. 2  in an initial state. 
           [0017]      FIG. 4  shows an example of waveforms of the supply voltage and the output signals of  FIG. 2  in a power-saving state. 
           [0018]      FIG. 5  shows another example of waveforms of the supply voltage and the output signals of  FIG. 2  in the power-saving state. 
           [0019]      FIG. 6  is a circuit diagram showing a level shifter and its logic unit according to another embodiment of the invention. 
           [0020]      FIG. 7  (Prior Art) is a circuit diagram showing another conventional level shifter and its logic unit. 
           [0021]      FIG. 8  (Prior Art) is a circuit diagram showing still another conventional level shifter and its logic unit. 
           [0022]      FIG. 9  shows a circuit using the level shifter of this embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0023]      FIG. 2  is a circuit diagram showing a level shifter  200  and its logic unit according to an embodiment of the invention. Referring to  FIG. 2 , the level shifter  200  is consisted of transistors P 1 , P 2 , N 3 , N 4  and N 5 . The first ends of the transistors P 1  and P 2  are coupled to a first supply voltage VccH. 
         [0024]    The control ends of the transistors N 3  and N 4  respectively receive input signals IN and IN′. The first end of the transistor N 3  is coupled to the control end of the transistor P 2 . The first end of the transistor N 4  is coupled to the control end of the transistor P 1 . The first ends of the transistors N 3  and N 4  are respectively coupled to the second ends of the transistors P 1  and P 2 . The second ends of the transistors N 3  and N 4  are coupled to a second supply voltage. In this embodiment, the second supply voltage is a ground voltage. The first end of the transistor N 3  outputs an output signal OUT′. The first end of the transistor N 4  outputs an output signal OUT. 
         [0025]    The first end of the transistor N 5  is coupled to the control end of the transistor P 1 , the control end of the transistor N 5  is coupled to the control end of the transistor P 2 . The second end of the transistor N 5  is coupled to the second supply voltage. 
         [0026]    As for a metal-oxide semiconductor (MOS) transistor, the control end of the transistor is the gate, and the first and second ends of the transistor are respectively one and the other of the drain and the source. 
         [0027]    In this embodiment, the input signals IN and IN′ are generated by a logic unit  300 , which is an inverter, for example. When the logic unit  300  is driven by a supply voltage VccL, the input signals IN and IN′ outputted by the logic unit  300  have inverse phases. When the logic unit  300  is not powered by the supply voltage VccL, the input signals IN and IN′ outputted by the logic unit  300  have the low levels. 
         [0028]    In this embodiment, the first supply voltage VccH has been initially generated while the supply voltage VccL has not been generated in an initial state so that the input signals IN and IN′ have the low levels. In a normal state, the first supply voltage VccH and the supply voltage VccL have been generated to respectively and normally drive the level shifter  200  and the logic unit  300 . After the normal state is changed to a power-saving state, the first supply voltage VccH still continuously supplies the electric power. In the power-saving state, the supply voltage VccL stops supplying the electric power and the logic unit  300  is not powered by the supply voltage VccL so that the input signals IN and IN′ have the low levels. 
         [0029]    The operations of the level shifter according to this embodiment of the invention in the initial state, the normal state and the power-saving state will be respectively described in the following.  FIG. 3  shows an example of waveforms of the supply voltage VccH and the output signals OUT and OUT′ of  FIG. 2  in the initial state. As shown in  FIGS. 2 and 3 , the supply voltage VccL has not yet been generated in the initial state. Thus, the transistors N 3  and N 4  are turned off. The supply voltage VccH is increased with time. In the period when the supply voltage VccH is increased, the subthreshold currents of the transistors P 1  and P 2  increase the levels of the output signals OUT and OUT′. 
         [0030]    When the levels of the output signals OUT and OUT′ are higher than the threshold voltage of the transistor N 5 , the transistor N 5  is turned on. Thus, the level of the output signal OUT is pulled down to the ground voltage. Thus, the transistor P 1  is turned on, and the level of the output signal OUT′ is pulled up to the level of the supply voltage VccH. Consequently, in the initial state when the supply voltage VccH has been generated and the supply voltage VccL has not been generated, the output signals OUT and OUT′ respectively have the low level and the high level. 
         [0031]    Compared with the conventional level shifter, which generates the input signal with the intermediate level in the initial state, the level shifter  200  of this embodiment does not cause the post-stage logic unit, such as an inverter, to malfunction. In addition, the voltage source of the supply voltage VccH for the level shifter  200  of this embodiment does not generate high current consumption in the initial state during power-on period. 
         [0032]    In the normal state, the supply voltages VccH and VccL respectively and normally drive the level shifter  200  and the logic unit  300 . The logic unit  300  generates the input signals IN and IN′, which have inverse phases, to the level shifter  200 . When the input signal IN has the high level (i.e., the level of the supply voltage VccL) and the input signal IN′ has the low level, the transistor N 3  is turned on and the transistor N 4  is turned off. Because the transistor N 3  is turned on, the level of the output signal OUT′ is pulled down to the ground voltage. Thus, the transistor P 2  is turned on and the transistor N 5  is turned off. After the transistor P 2  is turned on, the level of the output signal OUT is pulled up to the level of the supply voltage VccH. 
         [0033]    Thus, when the input signal IN has the high level and the input signal IN′ has the low level, the level shifter  200  generates the output signal OUT′ with the low level, and the output signal OUT with the high level. 
         [0034]    Oppositely, when the input signal IN has the low level and the input signal IN′ has the high level in the normal state, the level shifter  200  pulls up the level of the output signal OUT′ to the level of the supply voltage VccH, and the output signal OUT has the low level. In this case, the operations of the level shifter  200  are similar to those mentioned hereinabove, so detailed descriptions thereof will be omitted. 
         [0035]    Because the level of the supply voltage VccL is lower than that of the supply voltage VccH, the level shifter of this embodiment receives the input signal with the lower level, and can output the output signal with the higher level. 
         [0036]      FIG. 4  shows an example of waveforms of the supply voltage VccH and the output signals OUT and OUT′ of  FIG. 2  in the power-saving state. As shown in  FIGS. 2 and 4 , the supply voltage VccH still normally drives the level shifter  200  in the power-saving state, and the supply voltage VccL stops supplying the electric power and does not drive the logic unit  300 . In this example, before the supply voltage VccL stops supplying the electric power, it is assumed that the input signal IN has the low level, and the input signal IN′ has the high level. At this time, the output signal OUT has the low level, and the output signal OUT′ has the high level. 
         [0037]    After the supply voltage VccL stops supplying the electric power, it is assumed that the input signal IN has the low level and the input signal IN′ is also decreased to the low level. Therefore, the transistors N 3  and N 4  are turned off. However, the transistor N 5  is still turned on, the output signal OUT is pulled down to the low level so that the transistor P 1  is turned on. Thus, the output signal OUT′ is pulled up to the level of the supply voltage VccH. Thus, the transistor N 5  is still turned on, and the transistor P 2  is turned off. Thus, the output signals OUT and OUT′ are respectively kept at the low level and the high level, as shown in  FIG. 4 . 
         [0038]    Thus, before the state is changed to the power-saving state, the output signal OUT has the low level and the output signal OUT′ has the high level when the input signal IN has the low level and the input signal IN′ has the high level. After the state is changed to the power-saving state, the output signals OUT and OUT′ are still respectively kept at the low level and the high level, as shown in  FIG. 4 . 
         [0039]      FIG. 5  shows another example of waveforms of the supply voltage VccH and the output signals OUT and OUT′ of  FIG. 2  in the power-saving state. As shown in  FIGS. 2 and 5  of this example, before the supply voltage VccL stops supplying the electric power, it is assumed that the input signal IN has the high level and the input signal IN′ has the low level. At this time, the output signal OUT has the high level, and the output signal OUT′ has the low level. 
         [0040]    When the normal state is changed to the power-saving state, the input signal IN is decreased down to the low level. Thus, the transistor N 3  is turned off. Because the output signal OUT has the high level, the transistor P 1  is turned off. However, the subthreshold current of the transistors P 1  and N 3  generated according to the supply voltage VccH increases the level of the output signal OUT′. When the output signal OUT′ is pulled up and exceeds the threshold voltage of the transistor N 5 , the transistor N 5  is turned on. Thus, the output signal OUT is pulled down to the low level so that the transistor P 1  is turned on. Thus, the output signal OUT′ is pulled up to the high level. 
         [0041]    Thus, before the state is changed to the power-saving state, the output signal OUT has the high level and the output signal OUT′ has the low level when the input signal IN has the high level and the input signal IN′ has the low level. After the state is changed to the power-saving state, the output signal OUT is pulled up to the high level, and the output signal OUT′ is pulled down to the low level, as shown in  FIG. 5 . 
         [0042]    As mentioned hereinabove, it is obtained that when the output signals OUT and OUT′ have either the high levels or the low levels before the state is changed to the power-saving state, the output signal OUT always has the low level and the output signal OUT′ always has the high level after the state is changed to the power-saving state. 
         [0043]    Compared with the conventional level shifter  100 , in which the output signal, kept at the low level, in the output signals B and B′ is pulled up to the intermediate level when the normal state is changed to the power-saving state, the level shifter  200  of this embodiment can make the output signal have the high level or the low level instead of the intermediate level in the power-saving state. Such an output signal will not make the post-stage logic unit, such as the CMOS inverter, to malfunction, and also will not make the post-stage logic unit generate the abnormally high current consumption. 
         [0044]    In this embodiment, the transistors P 1  and P 2  are preferably PMOS transistors, and the transistors N 3  to N 5  are preferably NMOS transistors. 
         [0045]      FIG. 6  is a circuit diagram showing a level shifter  600  and its logic unit according to another embodiment of the invention. As shown in  FIG. 6 , what is different from the level shifter  200  is that the connections of a transistor N 5 ′ of the level shifter  600  are different from those of the transistor N 5  of the level shifter  200 . The first end of the transistor N 5 ′ is coupled to the control end of the transistor P 2 . The control end of the transistor N 5 ′ is coupled to the control end of the transistor P 1 . The second end of the transistor N 5 ′ is coupled to the ground voltage. The operations of the level shifter  600  are similar to those of the level shifter  200 , so detailed descriptions thereof will be omitted. 
         [0046]    The level shifter of this embodiment will be compared with other conventional level shifters.  FIG. 7  (Prior Art) is a circuit diagram showing another conventional level shifter and its logic unit, as disclosed in U.S. Pat. No. 6,781,413. The conventional level shifter of  FIG. 7  includes a transistor P 31  for pre-charging. The first end of the transistor P 31  is coupled to the supply voltage VccH, the control end of the transistor P 31  is coupled to the second end of the transistor P 31 , and the second end of the transistor P 31  is coupled to the second end of the transistor P 5 . 
         [0047]    When the conventional level shifter of  FIG. 7  is in the initial state, the transistor P 31  is turned on so that the level of the output signal  B  is pulled up to the level of the supply voltage VccH. Consequently, the transistor N 30  is turned on so that the output signal B is pulled down to the ground voltage. Thus, the drawbacks of the conventional level shifter  100  in the initial state may be improved. 
         [0048]    In the conventional level shifter of  FIG. 7 , however, if the input signal A has the high level in normal operation state, the transistor P 31  is still turned on so that the high current flows through the transistor P 31  and the high power consumption is generated. Thus, compared with the conventional level shifter of  FIG. 7 , the level shifters  200  and  600  of the embodiments of the invention further have the power-saving effect. In addition, compared with the conventional level shifter of  FIG. 7 , in which six transistors are used, each of the level shifters  200  and  600  according to the embodiments of the invention only uses five transistors. Thus, the level shifter according to each embodiment of the invention has the lower circuit complexity and the lower manufacturing cost. 
         [0049]      FIG. 8  (Prior Art) is a circuit diagram showing still another conventional level shifter and its logic unit, as disclosed in U.S. Pat. No. 6,809,544. Referring to  FIG. 8 , the control ends of the transistors N 23  and N 24  respectively receive the input signals transmitted by the logic unit  27  and the logic unit  28 . Before the normal state is changed to the power-saving state, the output signal on the node  26  has the low level and the output signal on the node  25  has the high level if the input signal received by the transistor N 23  has the low level and the input signal received by the transistor N 24  has the high level. After the state is changed to the power-saving state, the output signals on the nodes  26  and  25  are still respectively kept at the low level and the high level. Oppositely, before the state is changed to the power-saving state, the output signal on the node  26  has the high level and the output signal on the node  25  has the low level if the input signal received by the transistor N 23  has the high level and the input signal received by the transistor N 24  has the low level. After the state is changed to the power-saving state, the output signals on the nodes  26  and  25  are still respectively kept on the high level and the low level. 
         [0050]    Thus, in the power-saving state, the output signals on the nodes  25  and  26  of the conventional level shifter of  FIG. 8  are kept at the levels before the power-saving state is entered. Therefore, the level of the output signal of the conventional level shifter of  FIG. 8  is determined according to the level before the power-saving state is entered. In the power-saving state, if the post-stage logic unit has to receive a signal with a specific level to achieve the power-saving effect, the conventional level shifter of  FIG. 8  must receive a specific input signal to generate the output signal with the specific level so that the post-stage logic unit can enter the power-saving state. 
         [0051]    Compared with the prior art, when the input signals IN and IN′ received by the level shifters  200  and  600  have either the high levels or the low levels before the state is changed to the power-saving state in the two embodiments of the invention, the output signal OUT always has the low level, and the output signal OUT′ always has the high level after the state is changed to the power-saving state. Thus, when the power-saving mode is entered, the post-stage logic unit can directly enter the power-saving mode without the first provision of the input signals IN and IN′ having the specific levels. So, each of the level shifters  200  and  600  according to the two embodiments of the invention has the advantages that the operation is easy and the circuit design is easy. 
         [0052]    In addition, compared with the conventional level shifters of  FIGS. 7  and  8 , in which six transistors are used, each of the level shifters  200  and  600  according to the embodiments of the invention only uses five transistors. Thus, the level shifter according to each embodiment of the invention has the lower circuit complexity and the lower manufacturing cost. 
         [0053]    In addition, the level shifter  200  may be applied to the circuit of  FIG. 9 , for example. The circuit of  FIG. 9  includes a voltage generator  910 , a logic unit  920 , the level shifter  200  and a CMOS inverter  930 . The voltage generator  910  receives the supply voltage VccH and generates the supply voltage VccL, which is inputted to the logic unit  920 . 
         [0054]    The logic unit  920  generates the input signals IN and IN′ serving as the inputs of the level shifter  200 . In this embodiment, the logic unit  920  is an inverter, for example. The output end OUT of the level shifter  200  is electrically connected to the CMOS inverter  930 . 
         [0055]    When the logic unit  920  is powered by the supply voltage VccL, the input signals IN and IN′ have inverse phases. The level of the input signal which is of the high level is substantially equal to the level of the supply voltage VccL. When the logic unit  920  is not powered by the supply voltage VccL, the input signals IN and IN′ outputted by the logic unit  920  have the low levels. 
         [0056]    In the initial state, the voltage generator  910  has not outputted the supply voltage VccL to the logic unit  920 . In the normal state, the voltage generator  910  normally outputs the supply voltage VccL to the logic unit  920 . In the power-saving state, the voltage generator  910  stops outputting the supply voltage VccL to the logic unit  920 . 
         [0057]    Although the level shifter in the circuit of  FIG. 9  is the level shifter  200 , the level shifter  200  may be replaced with the level shifter  600 . 
         [0058]    Using the level shifter of each embodiment of the invention, the circuit of  FIG. 9  can normally operate in the initial state, the normal state and the power-saving state, and is free from the high current consumption of the CMOS inverter  930  in the initial state and the power-saving state. Thus, the circuit of  FIG. 9  has the advantages of the low current consumption and the low complexity. 
         [0059]    While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.