Abstract:
A metastableproof flip-flop receives an input value on a flip-flop input. The flip-flop holds an output value on a flip-flop output. In response to a transition of a clock signal, a transition in the output value occurs. The new output value is the input value formerly received by the flip-flop. In order to make the flip-flop metastableproof, the transition in the output value is delayed when the input value is in a metastable state. When the input value is no longer in the metastable state, then the transition in the output value is allowed to complete.

Description:
BACKGROUND 
     The present invention concerns the design of a flip-flop and pertains particularly to the design of a flip-flop which is metastableproof. 
     When utilizing circuits which include flip-flops, it is generally necessary to insure against a metastable state being established within a flip-flop. A metastable state can occur, for example, when data is not synchronized with the clock signal for the flip-flop. In such a case, the data signal may be in transition between values at approximately the same time as a transition occurs in the clock signal. In this case, the voltage of the data signal may not yet be at a valid voltage level when it is captured by the flip-flop. 
     One solution used to avoid metastable states in a circuit is to connect several flip-flops in series. If a metastable state occurs in the first flip-flop, there is a low probability that the metastable state will propagate to a second flip-flop. Thus a metastable state in a first flip-flop will generally settle to a static state by the time the signal has propagated through one, or perhaps two more flip-flops. 
     One problem with the above solution is that a clock cycle is required to propagate a data signal through each flip-flop in series. This can add a significant delay to propagation of the data signal in a circuit. In addition, there is the possibility that even with the flip-flops connected in series, a metastable state could still propagate through all the flip-flops. 
     SUMMARY OF THE INVENTION 
     In accordance with the preferred embodiment of the present invention, a metastableproof flip-flop is presented. The flip-flop receives an input value on a flip-flop input. The flip-flop holds an output value on a flip-flop output. In response to a transition of a clock signal, a transition in the output value occurs. The new output value is the input value formerly received by the flip-flop. In order to make the flip-flop metastableproof, the transition in the output value is delayed when the input value is in a metastable state. When the input value is no longer in the metastable state, then the transition in the output value is allowed to complete. 
     In the preferred embodiment of the present invention, test circuitry is used to monitor the input value to determine when the input value is in a metastable state. When the input value is not in a metastable state, the test circuit asserts a data valid signal, which allows a delayed transition in the output value to complete. 
     The present invention provides a flip-flop in which no metastable state occurs. This alleviates the necessity of connecting together a series of flip-flops when data is not synchronized between a clock signal and a flip-flop. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows an implementation of a flip-flop in accordance with the prior art. 
     FIG. 2 shows an implementation of a metastableproof flip-flop in accordance with a preferred embodiment of the present invention. 
     FIG. 3 shows an implementation of test circuitry within the metastableproof flip-flop shown in FIG. 2 in accordance with a preferred embodiment of the present invention. 
     FIG. 4 shows an implementation of a clock buffer circuit in accordance with the prior art. 
     FIG. 5 shows an implementation of a flip-flop in accordance with the prior art. 
     FIG. 6 shows an implementation of a metastableproof flip-flop in accordance with another preferred embodiment of the present invention. 
     FIG. 7 shows an implementation of test circuitry within the metastableproof flip-flop shown in FIG. 6 in accordance with a preferred embodiment of the present invention. 
     FIG. 8 is a timing diagram which illustrates operation of a preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a CMOS implementation of a flip-flop in accordance with the prior art. A D input 10 of the flip-flop is used to capture a data value placed on D input 10. A Q output 11 holds a flip-flop output value. A clock signal (Clk) 21 and an inverted clock signal (|Clk) 22 are used to clock a pass gate 12, a pass gate 13, a pass gate 14 and a pass gate 15 within the flip-flop. The flip-flop additionally includes an inverter 16, an inverter 17, an inverter 18, an inverter 19, an inverter 20 and an inverter 23, connected as shown. A voltage reference node 24 is also shown. 
     FIG. 2 shows a CMOS implementation of a metastableproof flip-flop in accordance with a preferred embodiment of the present invention. A D input 30 of the flip-flop is used to capture a data value placed on D input 30. A Q output 31 holds a flip-flop output value. A clock signal (Clk) 41 and an inverted clock signal (|Clk) 42 are used to clock a pass gate 32, a pass gate 33, a pass gate 34 and a pass gate 35 within the flip-flop. The flip-flop additionally includes an inverter 36, an inverter 37, an inverter 38, an inverter 39, an inverter 40 and an inverter 43, connected as shown. 
     Test circuitry 60 within the metastableproof flip-flop generates a data valid signal on a line 61 and an inverted data valid signal on a line 62. As long as the voltage of the signal on a node 63 is invalid, e.g., between 1.5 volts and 3.5 volts, the valid signal on line 61 is deasserted (e.g., driven low) and the inverted data valid signal on line 62 is asserted (e.g., driven high). 
     When the voltage of the signal on node 63 is valid (e.g., less than 1.5 volts or greater than 3.5 volts), the valid signal on line 61 is asserted (e.g., driven high) and the inverted data valid signal on line 62 is deasserted (e.g., driven low). 
     The valid signal on line 61 and the inverted data valid signal on line 62 are used to control a pass gate 52, a pass gate 53, a pass gate 54 and a pass gate 55 within the metastableproof flip-flop. Pass gates 52 through 55 are placed in the metastableproof flip-flop to prevent the metastableproof flip-flop from latching on a value of the input signal on D input 30 when the value of the input signal on D input 30 is not at a valid voltage (e.g., is not between 1.5 volts and 3.5 volts). 
     Operation of the metastableproof flip-flop shown in FIG. 2 is identical to the operation of the flip-flop shown in FIG. 1 except for the case where the rising edge of clock signal (Clk) 41 occurs when the input signal on D input 30 is not at a valid voltage (e.g., is not between 1.5 volts and 3.5 volts). In this case, pass gates 52 through 55 will delay the capture of the data value on D input 30 until the input signal on D input 30 is at a valid voltage (e.g., the voltage on D input 30 is less than 1.5 volts or more than 3.5 volts). This prevents metastable states from occurring in the metastableproof flip-flop. 
     FIG. 3 shows an implementation of test circuitry 60. A transistor 67, a transistor 68, a transistor 69, a transistor 74, a transistor 74, and a transistor 75 function together as an inverter with a threshold of 3.5 volts. A transistor 70, a transistor 71, a transistor 72, a transistor 76, a transistor 77, and a transistor 78 function together as an inverter with a threshold of 1.5 volts. Test circuitry 60 also includes an inverter 79, an inverter 80 and a logical NOR gate 81 connected as shown. Inverter 79 and inverter 80 each have a voltage threshold of, for example, 2.5 volts. A VDD signal 65 (e.g., 5 volts) and a ground signal 66 (e.g., 0 volts) are also utilized by the test circuitry. 
     FIG. 4 and FIG. 5 shows another implementation of a flip-flop, including a clock buffer circuit, as is in the prior art. 
     FIG. 4 shows implementation of the clock buffer. An original clock signal is placed on a line 85. A transistor 88 and a transistor 89 serve as an inverter to generate an inverted clock signal placed on a line 86. A transistor 90 and a transistor 91 serve as an inverter to generate a buffered clock signal placed on a line 87. 
     FIG. 5 shows the CMOS implementation of the flip-flop. A D input 95 of the flip-flop is used to capture a data value placed on D input 95. A Q output 96 holds a flip-flop output value. Each of transistor pairs 102 and 112, 104 and 114, 105 and 115, 107 and 117, 109 and 119, 110, and 120, and 111 and 121 function as an inverter. The buffered clock signal placed on line 87 is used to control a transistor 101, a transistor 108, a transistor 116 and a transistor 118. The inverted clock signal placed on line 86 are used to control a transistor 103, a transistor 106, a transistor 113 and a transistor 122. 
     FIG. 6 shows how the flip-flop shown in FIG. 5 can be modified to produce a metastableproof flip-flop in accordance with a preferred embodiment of the present invention. A data valid signal on a line 141 is used to control a transistor 131, a transistor 134, a transistor 136 and a transistor 137. The data valid signal after being inverted is placed on a line 142 and is used to control a transistor 132, a transistor 133, a transistor 135 and a transistor 138. Transistor 131, transistor 134, transistor 136, transistor 137, transistor 132, transistor 133, transistor 135 and transistor 138 are placed in the metastableproof flip-flop to prevent the metastableproof flip-flop from latching on a value of the input signal on D input 95 when the value of the input signal on D input 95 is not at a valid voltage (e.g., is not between 1.5 volts and 3.5 volts). 
     Operation of the metastableproof flip-flop shown in FIG. 6 is identical to the operation of the flip-flop shown in FIG. 5 except for the case where the rising edge of the buffered clock signal placed on line 87 occurs when the input signal on D input 95 is not at a valid voltage (e.g., is not between 1.5 volts and 3.5 volts). In this case, transistor 131, transistor 134, transistor 136, transistor 137, transistor 132, transistor 133, transistor 135 and transistor 138 will delay the capture of the data value on D input 95 until the input signal on D input 95 is at a valid voltage (e.g., the voltage on D input 30 is less than 1.5 volts or more than 3.5 volts). This prevents metastable states in the metastableproof flip-flop. 
     FIG. 7 shows an implementation of test circuitry which generates the data valid signal on line 141 and the (inverted) data valid signal on line 142. A transistor 167, a transistor 168, a transistor 169, a transistor 174, a transistor 174, and a transistor 175 function together as an inverter with a threshold of 3.5 volts. A transistor 170, a transistor 171, a transistor 172, a transistor 176, a transistor 177, and a transistor 178 function together as an inverter with a threshold of 1.5 volts. Test circuitry 160 also includes a transistor pair 151 and 155 which functions as an inverter, and a transistor pair 154 and 157 which also functions as an inverter. A transistor 152, a transistor 153, a transistor 155 and a transistor 156 are connected so as to function as a logic NOR gate. FIG. 8 is a timing diagram which compares operation of a metastableproof flip-flop with a conventional flip-flop. A clock signal 201 represents a clock signal for a flip-flop, for example, clock signal (Clk) 21 of the flip-flop shown in FIG. 1 or clock signal (Clk) 41 of the metastableproof flip-flop shown in FIG. 2. A data signal 202 represents a signal on a D input of a flip-flop, for example, on D input 10 of the flip-flop shown in FIG. 1 or on D input 30 of the metastableproof flip-flop shown in FIG. 2. At a time 210, data signal 202 transitions to a voltage which is less than 3.5 volts and is greater than 1.5 volts. At a time 211, clock signal 201 transitions from a low voltage state (0 volts) to a high voltage state (5 volts). At a time 212, signal 202 transitions from the voltage which is less than 3.5 volts and is greater than 1.5 volts to a low voltage state (0 volts). 
     A reference node signal 203 shows a voltage of a reference node within a conventional flip-flop, for example at reference node 24 of the flip-flop shown in FIG. 1. When clock signal 201 transitions from a low voltage state (0 volts) to a high voltage state (5 volts) at time 211, data signal 202 is at a voltage which is less than 3.5 volts and is greater than 1.5 volts. The result is that the captured data value is unknown and possibly metastable, as represented by uncertain region 213. 
     A Q output signal 205 shows a voltage of a Q output of a conventional flip-flop, for example at Q output 11 of the flip-flop shown in FIG. 1. When clock signal 201 transitions from a low voltage state (0 volts) to a high voltage state (5 volts) at time 211, data signal 202 is at a voltage which is less than 3.5 volts and is greater than 1.5 volts and the voltage captured at reference node 24 is unknown and possibly metastable, as discussed above. When this voltage is gated to Q output 11 of the flip-flop, at time 211, the Q output signal is also unknown and possibly metastable, as represented by uncertain region 214. 
     A reference node signal 204 shows a voltage of a reference node within a metastableproof flip-flop, for example at node 63 of the metastableproof flip-flop shown in FIG. 2. When clock signal 201 transitions from a low voltage state (0 volts) to a high voltage state (5 volts) at time 211, pass gates 52 through 55 will delay the capture of the data value on D input 30 until the input signal on D input 30 is at a valid voltage (e.g., the voltage on D input 30 is less than 1.5 volts or more than 3.5 volts). This prevents metastable states in the metastableproof flip-flop. At time 212, when signal 202 transitions from the voltage which is less than 3.5 volts and is greater than 1.5 volts to a low voltage state (0 volts), the metastableproof flip-flop captures a valid voltage. 
     A Q output signal 206 shows a voltage at a Q output of a metastableproof flip-flop, for example, at Q output 31 of the metastableproof flip-flop shown in FIG. 2. When clock signal 201 transitions from a low voltage state (0 volts) to a high voltage state (5 volts) at time 211, pass gates 52 through 55 will delay the capture of the data value on D input 30 until the input signal on D input 30 is at a valid voltage (e.g., the voltage on D input 30 is less than 1.5 volts or more than 3.5 volts). As discussed above, this prevents metastable states in the metastableproof flip-flop. At time 212, when signal 202 transitions from the voltage which is less than 3.5 volts and is greater than 1.5 volts to a low voltage state (0 volts), the metastableproof flip-flop captures a valid voltage. This captured voltage is passed through, at time 212 to Q output 31, as illustrated by Q output signal 206. 
     The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.