Abstract:
A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of semiconductor fabrication; more specifically, it relates to a method for forming recessed polysilicon contacts in semiconductor devices. 
     BACKGROUND OF THE INVENTION 
     During manufacture of semiconductor chips, transistors, diodes, capacitors and resistors along with other devices formed in the silicon portion of the chip must be interconnected to one another to form circuits. Modern semiconductor chips utilize planer technology for these interconnections. In planer interconnect technology, an insulating layer is formed on the chips surface, a trench is formed in the insulator, filled with conductor and the insulator and conductor co-planarized flat. This may be repeated many times to build up the necessary level of device interconnections required in a modern semiconductor chip. 
     In certain cases, it is desirable for the conductive wires to be formed from materials that are detrimental to the active devices. In these cases, the trench is filled with polysilicon. Filling the trench with polysilicon can lead to high contact resistance. Therefore recessed polysilicon contact technology has been developed. In recessed polysilicon technology the upper portion of the polysilicon is removed from the trench before the conductive wires are formed. However, as the depth to width aspect ratio of polysilicon contacts has increased, mainly due to increasing density and decreasing contact widths, several types of defects have occurred which can cause yield and reliability failures. 
     The first defect type is a void in the polysilicon. Voids may reach so deep into the recessed polysilicon contact that the conductive wire may contact the active device directly or they may simply increase the resistance of the contact because there is less material. Another type of defect is a polysilicon spike. Spikes are regions of polysilicon reaching up into the conductive wire and can increase the resistance of the contact. 
     Thus, there is a need for a method of forming recessed polysilicon contacts in which void and spike defects are greatly reduced or eliminated. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention is a method of forming a recessed polysilicon contact, comprising: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench. 
     A second aspect of the present invention is a method of forming a recessed polysilicon contact, comprising: forming a trench in an insulating layer down to a conductive layer; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to form a polysilicon contact in the trench to the conductive layer, a top surface of the polysilicon contact co-planer with a top surface of the insulating layer; oxidizing the a top surface of the polysilicon contact using plasma oxidation; and removing an upper portion of the polysilicon contact from the trench to form the recessed polysilicon contact to the conductive layer. 
     A third aspect of the present invention is a recessed polysilicon contact prepared by the process comprising: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIGS. 1 through 3 are partial cross-sectional views illustrating the initial steps for fabricating a recessed polysilicon contact that will result in void or spike and void defects in the completed contact; 
     FIG. 4 is a blow up view of the central portion of the polysilicon filled trench of FIG. 3 after planarization by a reactive ion etch (RIE) process; 
     FIG. 5 is a blow up view of the central portion of the polysilicon filled trench of FIG. 3 after planarization by a chemical-mechanical-polish (CMP) process; 
     FIG. 6 is a partial cross-sectional view after recessing the polysilicon fill, when the planarization step is performed using an RIE process, illustrating a void defect; 
     FIG. 7 is a partial cross-sectional view after recessing the polysilicon fill, when the planarization is performed using a CMP process, illustrating a spike and void defect; and 
     FIGS. 8 through 13 are partial cross-sectional views illustrating the fabrication of a recessed polysilicon contact according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1 through 3 are partial cross-sectional views illustrating the initial steps of fabricating a recessed polysilicon contact that will result in void or spike and void defects in the completed contact. In FIG. 1, formed on a conductor  100  is an insulating layer  102  having a top surface  105 . In one example, insulating layer  102  is silicon dioxide, silicon nitride, tetraethoxysilane (TEOS) oxide or high-density plasma (HDP) oxide and conductive layer  100  is doped (diffused) silicon or polysilicon. From top surface  105  a trench  110  has been formed by well known photolithographic and RIE methods, and extends a distance “D” into insulating layer  100 . Trench  110  has a width “W.” In one example, “D” is about 0.5 microns or more and “W” is 0.25 microns or less. 
     In FIG. 2, a polysilicon layer  115  of sufficient thickness to fill trench  110  is deposited by well-known chemical vapor deposition (CVD) or low-pressure vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) methods. Attributes of the polysilicon fill process include formation of a dip  120  and a seam  125  in polysilicon layer  115 . Dip  120  is caused by the presence of trench  110 . Seam  125  is formed when polysilicon depositing on sidewalls  127  of trench  110  reach a sufficient thickness to meet in the approximate middle of the width of the trench. Dip  120  does not extend into now filled trench  110  and ends a distance “D 1 ” above surface  105  of insulating layer  100 . However, under certain circumstances (such as a thinner than required polysilicon layer  110 ), dip  120  may extend into trench  110  and larger defects may be expected. On the other hand, seam  125  does extend into trench  110 . In one example, for a trench having a depth of 0.5 to 1.0 microns polysilicon layer  115  is about 2000 to 4500 Å thick and “D 1 ” is about 1000 to 4500 Å. 
     In FIG. 3, a planarization process is performed, removing excess polysilicon from top surface  105  of insulating layer  100  and forming polysilicon contact  130  to conductive layer  100 . A top surface  132  of polysilicon contact  130  is coplanar with top surface  105  of insulating layer  102  except in a dip  120 A. Dip  120 A is a replication by the planarization process of dip  120  illustrated in FIG.  2  and described above. Dip  120 A extends a distance “D 2 ” into polysilicon contact  130 . In one example, “D 2 ” is about 200 to 800 Å. There are two well-known planarization methods and while FIG. 3 accurately illustrates the gross structure of polysilicon contact formed by either method. FIGS. 4 and 5 provide additional detail. 
     FIG. 4 is a blow up view of the central portion of the polysilicon filled trench of FIG. 3 after planarization by an RIE planarization process. An RIE planarization process removes material equally from all exposed surfaces. The RIE planarization process is designed to be selective to polysilicon over the insulating material of insulating layer  102 . The RIE planarization process removes material by both mechanical means (ion bombardment dislodging atoms from the surface of the material being etched) and chemical means (conversion of atoms on the surface into a readily vaporizable compound). In a polysilicon RIE planarization process, any thin oxides that may be present on surface  132  of polysilicon contact  130  are removed or prevented from forming. 
     FIG. 5 is a blow up view of the central portion of the polysilicon filled trench of FIG. 3 after planarization by a CMP process. A CMP process utilizes slurries to remove material by mechanical abrasion of particles from the surface of the material being polished and then chemically dissolving the particles. The surface is also smoothed by direct chemical reaction dissolving the material. Polysilicon CMP slurries chemically oxidize silicon. Therefore, a main difference between RIE planarization and CMP planarization of polysilicon films is the formation of a substantial SiO 2 film on exposed surfaces of polysilicon in the CMP process. In FIG. 5, a SiO 2  layer  135  is formed on top surface  132  of polysilicon contact  130 . In one example, SiO 2  layer  135  is about 15 to 25 Å thick. In one example, CMP polishing slurry comprises silica particles suspended in a KOH solution. 
     FIG. 6 is a partial cross-sectional view after recessing the polysilicon fill, when the planarization step is performed using an RIE planarization process, illustrating a void defect. In FIG. 6, a recess RIE is performed to form recessed polysilicon contact  140 . A surface  145  of recessed polysilicon contact  140  is recessed a distance “R” from top surface  105  of insulating layer  102 . In one example, “R” is about 0.15 to 0.45 microns. In one example, the RIE recess etch process uses a flow of about 10 to 40 sccm of SF 6  at a pressure of about 3 to 20 millitorr and a forward power of about 80-200 watts. A dip  120 B is present is surface  145  and is a replication of dip  120 A illustrated in FIG.  3 . Also, at least a portion of seam  125  (see FIG. 3) is opened up into a void  150  during the RIE recess etch process. 
     FIG. 7 is a partial cross-sectional view after recessing the polysilicon fill when the planarization step is performed using a CMP planarization process illustrating a spike and void defect. In FIG. 7, an RIE recess is performed to form recessed polysilicon contact  140 . A surface  145  of recessed polysilicon contact  140  is recessed a distance “R” from top surface  105  of insulating layer  102 . In one example, “R” is about 0.15 to 0.45 microns. In one example, the RIE recess etch process uses a flow of about 10 to 40 sccm of SF 6  at a pressure of about 3 to 20 millitorr and a forward power of about 80 to 200 watts. A polysilicon spike  160  is present on surface  145  in the location corresponding to dip  120 A illustrated in FIG.  3 . Polysilicon spike  160  is primarily caused by SiO 2  layer  135  illustrated in FIG.  5 . Also, at least a portion of seam  125  (see FIG. 3) is opened up into a void  155  during the RIE recess etch process. 
     FIGS. 8 through 12 are partial cross-sectional views illustrating the fabrication of a recessed polysilicon contact according to the present invention. The processes steps illustrated in FIGS. 8 through 10 and described below are essentially the same as those illustrated in FIGS. 1 through 3 and described above. In FIG. 8, formed on a conductor  200  is an insulating layer  202  having a top surface  205 . In one example, insulating layer  202  is silicon dioxide, silicon nitride, TEOS oxide or HDP oxide and conductive layer  200  is doped (diffused) silicon or polysilicon. From top surface  205  a trench  210  has been formed by well known photolithographic and RIE methods, a distance “D” into insulating layer  202 . Trench  210  has a width “W.” In one example, “D” is about 0.5 microns or more and “W” is 0.25 microns or less. 
     In FIG. 9, a polysilicon layer  215  of sufficient thickness to fill trench  210  is deposited by well known CVD, LPCVD or PECVD methods. Attributes of the polysilicon fill process include formation of a dip  220  and a seam  225  in polysilicon layer  215 . Dip  220  is caused by the presence of trench  210 . Seam  225  is formed when polysilicon depositing on sidewalls  227  of trench  210  reach a sufficient thickness to meet in the approximate middle of the trench. Dip  220  does not extend into now filled trench  210  and ends a distance “D 1 ” above surface  205  of insulating layer  200 . Seam  225  extends into trench  210 . In one example, for a trench having a depth of 0.5 to 1.0 microns, polysilicon layer  215  is about 2000 to 4500 Å thick, and “D 1 ” is about 1000 to 2500 Å. 
     In FIG. 10, a polysilicon RIE planarization process is performed, removing excess polysilicon from top surface  205  of insulating layer  202  and forming polysilicon contact  230  to conductive layer  200 . A top surface  232  of polysilicon contact  230  is coplanar with top surface  205  of insulating layer  202  except in a dip  220 A. Dip  220 A is a replication of dip  220  illustrated in FIG.  9  and described above. Dip  220 A extends a distance “D 2 ” into polysilicon contact  230 . In one example, “D 2 ” is about 200 to 800 Å. The polysilicon RIE planarization process removes any thin oxides that may be present on surface  232  of polysilicon contact  230  and prevents oxide layers from forming. In one example, the polysilicon RIE planarization process uses a flow of about “20 to 100 sccm of SF 6  at a pressure of about 3 to 20” millitorr and a forward power of about 400 to 800 watts and is performed in an AMT 5200 DPS (decoupled plasma system) manufactured by Applied Materials Corp. of Santa Clara, Calif. 
     In FIG. 11, a plasma oxidation process is performed to oxidize top surface  235  of polysilicon contact  230 . The plasma oxidation process converts a portion of top surface  232  of polysilicon contact  230  into an ultra-thin SiO x  layer  235 . In one example, the plasma oxidation process uses a flow of about 5 to 20 sccm of O 2  at a pressure of about 3 to 20 millitorr and a forward power of about 80 to 200 watts for about 2 to 8 seconds and is performed in a AMAT 5200 DPS tool manufactured by Applied Materials, Santa Clara. Ultra-thin SiO x  layer  235  is illustrated in FIG.  12  and discussed below. 
     FIG. 12 is a blow up view of the central portion of the polysilicon fill of FIG. 11, after plasma oxidation. In FIG. 12, ultra-thin SiO x  layer  235  is formed in top surface  232  of polysilicon contact  230 . In one example, ultra thin SiO x  layer  235  is about 3 to 10 Å thick. In a second example, ultra thin SiO x  layer  235  is about 1 to 3 SiO x  monolayers thick. 
     In FIG. 13, a recess RIE is performed to form recessed polysilicon contact  240 . A top surface  245  of recessed polysilicon contact  240  is recessed a distance “R” from top surface  205  of insulating layer  200 . Top surface  245  of recessed polysilicon contact  240  is substantially flat. In one example, “R” is about 0.15 to 0.45 microns. In one example, the RIE recess etch process uses a flow of about 1 to 40 sccm of SF 6  at a pressure of about 3 to 20 millitorr and a forward power of about 80 to 200 watts and is performed in an AMAT 5200 DPS manufactured by Applied Materials Corp of Santa Clara, Calif. Note the absence of a dip, void or spike in recessed polysilicon contact  230 . This is a relatively unexpected result and is due to the plasma oxidation process illustrated in FIG.  11  and described above. That this result is unexpected is supported by the fact that the SiO 2  layer of about 15 to 20 Å formed by CMP planarization caused significant defect formation, namely spikes while the ultra-thin SiO x  layer formed by the plasma oxidation step does not cause void or spike defect formation. 
     A conductive layer such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride or combinations thereof may now be used to fill the remaining space of the trench and provide interconnection to other portions of the semiconductor device. 
     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.