Abstract:
A method of fabricating a semiconductor device and a semiconductor device fabricated by the same method are disclosed. The method includes: depositing a silicon layer containing amorphous silicon on a substrate using any one of a plasma enhanced chemical vapor deposition (PECVD) method and a low pressure chemical vapor deposition (LPCVD) method; annealing the silicon layer in an H 2 O atmosphere at a certain temperature to form a polycrystalline silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; forming impurity regions in the polycrystalline silicon layer to define source and drain regions; and activating the impurity regions. Thus, it is possible to provide a semiconductor device, in which the substrate is prevented from being bent and polycrystalline silicon constituting a semiconductor layer is excellent.

Description:
[0001]     This application claims priority to and the benefit of Korean Patent Application No. 2004-50863, filed Jun. 30, 2004, the contents of which are hereby incorporated herein by reference in their entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device by which a substrate may be prevented from being bent, and a semiconductor device fabricated by the same method.  
         [0004]     2. Description of Related Art  
         [0005]     Polycrystalline silicon is used in an active device for an organic light emitting display device, normally, thin film transistors (TFTs), which is used to supply current to pixel regions and peripheral driving regions.  
         [0006]     In general, the polycrystalline silicon is formed by crystallization of amorphous silicon.  
         [0007]     Normally, methods for the crystallization may be largely classified into a low-temperature crystallization method and a high-temperature crystallization method depending on a crystallization temperature, for example, with reference to about 500° C.  
         [0008]     An excimer laser annealing (ELA) method using an excimer laser is mainly used as the low-temperature crystallization method. The eximer laser annealing method may use a glass substrate since it is carried out at a crystallization temperature of about 450° C. However, manufacturing cost is high and the substrate is constrained in an optimal size, thereby increasing total cost to fabricate a display device.  
         [0009]     The high-temperature crystallization method includes a solid phase crystallization method, a rapid thermal annealing method, and the like. A low-cost annealing method is widely used as the high-temperature crystallization method.  
         [0010]     However, since the solid phase crystallization method requires heating at a temperature of more than 600° C. for 20 or more hours for crystallization, many crystal defects are included in the crystallized polycrystalline silicon. Accordingly, sufficient electric field mobility cannot be obtained, the substrate is prone to deform during an annealing process, i.e., a heat treatment process, and lowered crystallization temperature degrades productivity. Because the solid phase crystallization method is also performed at high crystallization temperature, the glass substrate is not allowed to use.  
         [0011]     Meanwhile, although the rapid thermal annealing (RTA) method may be accomplished in relatively short time, the substrate is prone to deform due to severe thermal shock and the crystallized polycrystalline silicon has poor electrical characteristics.  
         [0012]     Consequently, a low-cost high-temperature annealing method may be required to be used upon the crystallization in order to reduce cost to fabricate the active device. Moreover, there is a need for a high-temperature annealing method using an inexpensive glass substrate, by which the glass substrate is not bent and crystallinity is excellent.  
       SUMMARY OF THE INVENTION  
       [0013]     The present invention, therefore, solves aforementioned problems associated with conventional devices by providing a method of fabricating a semiconductor device which is capable of crystallizing polycrystalline silicon with excellent crystallinity and preventing a substrate from being bent due to a high crystallization temperature upon crystallization, and a semiconductor device fabricated by the same method.  
         [0014]     In an exemplary embodiment of the present invention, a method of fabricating a semiconductor device includes: depositing a silicon layer containing amorphous silicon on a substrate using a plasma enhanced chemical vapor deposition (PECVD) method or a low pressure chemical vapor deposition (LPCVD) method; annealing the silicon layer in an H 2 O atmosphere at a predetermined temperature to form a polycrystalline silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; forming impurity regions in the polycrystalline silicon layer; and activating the impurity regions.  
         [0015]     In another exemplary embodiment of the present invention, a method of fabricating a semiconductor device includes: depositing a silicon layer containing amorphous silicon on a substrate using a plasma enhanced chemical vapor deposition (PECVD) method or a low pressure chemical vapor deposition (LPCVD) method; doping the silicon layer with impurity ions to define source and drain regions; patterning the amorphous silicon to form a semiconductor layer; forming a gate insulating layer on the semiconductor layer over the substrate; forming a gate electrode on the gate insulating layer, the gate electrode corresponding to a channel region of the semiconductor layer; and annealing the amorphous silicon in an H 2 O atmosphere at predetermined temperature to crystallize the amorphous silicon and activate the impurity ions.  
         [0016]     In yet another exemplary embodiment of the present invention, a method of fabricating a semiconductor device includes: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode over the substrate; depositing a silicon layer containing amorphous silicon on the gate insulating layer using a plasma enhanced chemical vapor deposition (PECVD) method or a low pressure chemical vapor deposition (LPCVD) method; doping impurity ions into the silicon layer using photoresist to define source and drain regions; and removing the photoresist and then annealing the amorphous silicon in an H 2 O atmosphere at a certain temperature to crystallize the amorphous silicon and to activate the impurity ions.  
         [0017]     In still another exemplary embodiment of the present invention, a semiconductor device fabricated by the method, wherein the semiconductor device is a thin film transistor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The above and other features of the present invention will be described in reference to certain exemplary embodiments thereof with reference to the attached drawings in which:  
         [0019]      FIGS. 1A  to  1 E sequentially illustrate a method of fabricating a semiconductor device according to a first embodiment of the present invention;  
         [0020]      FIGS. 2A  to  2 E sequentially illustrate a method of fabricating a semiconductor device according to a second embodiment of the present invention;  
         [0021]      FIGS. 3A  to  3 D sequentially illustrate a method of fabricating a semiconductor device according to a third embodiment of the present invention; and  
         [0022]      FIG. 4  illustrates FWHM of a polycrystalline silicon thin film fabricated by embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. In the drawings, the thickness of the layers and regions are exaggerated for clarity.  
         [0024]      FIGS. 1A  to  1 E sequentially illustrate a method of fabricating a semiconductor device according to a first embodiment of the present invention.  
         [0025]     Referring to  FIG. 1A , amorphous silicon, or a silicon layer  12  containing a great quantity of amorphous silicon is deposited on a substrate  10 . At this time, a normally used insulating and transparent glass substrate is used as the substrate  10 .  
         [0026]     A typical deposition method, such as a plasma enhanced chemical vapor deposition (PECVD) method or a low-pressure chemical vapor deposition (LPCVD) method, is used to deposit the silicon layer  12 . The PECVD method is performed using SiH 4 +Ar and/or H 2  under a pressure of 1 to 1.5 Torr at a temperature of about 330 to about 430° C. Further, the LPCVD is performed using Si 2 H 6 +Ar under a pressure of 0.2 to 0.4 Torr at a temperature of about 400 to about 500° C.  
         [0027]     Further, a buffer layer such as a silicon nitride (SiNx) layer or a silicon oxide (SiO 2 ) layer may be further formed on the substrate prior to depositing the amorphous silicon layer, in order to prevent contaminants or the like created in the substrate from diffusing into the silicon layer or enhance interface characteristics between the silicon layer and the substrate.  
         [0028]     The amorphous silicon, or the silicon layer  12  that contains a great quantity of amorphous silicon is then annealed, as shown in  FIG. 1B . At this time, when the silicon layer is heated, the amorphous silicon is melt. At the same time, the amorphous silicon is cooled and crystallized into the polycrystalline silicon. The polycrystalline silicon is then patterned to form a semiconductor layer  12   a.    
         [0029]     In the present invention, a rapid thermal annealing (RTA) process or a typical high-temperature annealing process in a furnace is used as the annealing process. Conventional annealing is carried out in an inert N 2  or O 2  atmosphere while the annealing in the present invention is carried out in an H 2 O atmosphere.  
         [0030]     The annealing in the H 2 O atmosphere shortens annealing time under a condition of the same temperature and reduces annealing temperature under a condition of the same time, compared to the annealing in the N 2  or O 2  atmosphere.  
         [0031]     In particular, a conventional glass substrate that is a transparent insulting substrate is bent due to a high temperature while the substrate in the present invention is not bent because the annealing temperature may be lowered.  
         [0032]     In the present invention, the annealing temperature is preferably in the range of 550 to 750° C. More preferably, the annealing temperature is in the range of 600 to 710° C. because excellent polycrystalline silicon may be achieved with a proper annealing time. Crystallization may not be achieved when the annealing temperature is less than 550° C., and the substrate may be bent when it is more than 750° C.  
         [0033]     Further, it is preferable that the pressure of H 2 O is in the range of 10,000 Pa to 2 MPa. A crystallization rate is proportional to the pressure and thus when the pressure is too low, the crystallization rate becomes low and the annealing time becomes longer, affecting the substrate. On the other hand, too high pressure may cause explosion. For these reasons, the pressure of 10,000 Pa to 2 MPa is desirable for annealing.  
         [0034]     Meanwhile, it is preferable to deposit the silicon layer to a thickness of less than 2,000. Small thickness facilitates crystallization. However, too small thickness may affect the device characteristics when the polycrystalline silicon is used to form a thin film transistor. Accordingly, it is more preferable to deposit the silicon layer to a thickness of 300 to 1,000.  
         [0035]     As shown in  FIG. 1C , a gate insulating layer  14  is formed of SiO 2  or SiNx on the semiconductor layer  12   a.  A gate electrode  16  is formed corresponding to an active channel region  100   c  of the semiconductor layer  12   a,  as shown in  FIG. 1D .  
         [0036]     Ions are doped into the semiconductor layer  12   a  using the gate electrode  16  as a mask to form source and drain regions  100   a  ad  100   b.  The semiconductor layer  12   a,  doped with the ions, is activated by an excimer laser annealing (ELA) process, an RTA process or an annealing process in a furnace, preferably the RTA or annealing process in the furnace, as shown in  FIG. 1E .  
         [0037]     Subsequently, an interlayer insulating layer, such as SiO 2  or SiNx, is formed on the gate electrode  16  over the entire surface of the substrate. The interlayer insulating layer is then patterned to expose the source and drain regions  100   a  and  100   b  and source and drain electrodes are formed, thus completing a semiconductor device.  
         [0038]      FIGS. 2A  to  2 E sequentially illustrate a method of fabricating a semiconductor device according to a second embodiment of the present invention. The second embodiment of the present invention will be described with reference to  FIGS. 2A  to  2 E.  
         [0039]     Referring to  FIG. 2A , amorphous silicon, or a silicon layer  22  containing a great quantity of amorphous silicon is deposited on a substrate  20 . At this time, a normally used insulating and transparent glass substrate is used as the substrate  20 .  
         [0040]     A typical deposition method, such as a plasma enhanced chemical vapor deposition (PECVD) method or a low-pressure chemical vapor deposition (LPCVD) method, is used to deposit the silicon layer. The PECVD method is performed using SiH 4 +Ar and/or H 2  under a pressure of 1 to 1.5 Torr at a temperature of 330 to 430° C. Further, the LPCVD method is performed using Si 2 H 6 +Ar under a pressure of 0.2 to 0.4 Torr at a temperature of about 400 to 500° C.  
         [0041]     Further, a buffer layer such as SiNx or SiO 2  may be further formed on the substrate prior to depositing the amorphous silicon layer, in order to prevent contaminants or the like created in the substrate from diffusing into the silicon layer or enhance interface characteristics between the silicon layer and the substrate.  
         [0042]     Photoresist is then coated on a channel region  200   c  in the silicon layer  22 , not regions that will correspond to source and drain regions  200   a  and  200   b  later, and impurity ions are implanted into the silicon layer  22 .  
         [0043]     The photoresist is removed by, for example, photolithography and etching processes and then the silicon layer  22  doped with the impurity is patterned, as shown in  FIG. 2B .  
         [0044]     A gate insulating layer  24  is then formed of an inorganic insulating layer such as SiO 2  or SiNx on the patterned silicon layer  22 , as shown in  FIG. 2C .  
         [0045]     Subsequently, as shown in  FIG. 2D , a gate  26  is formed in a region corresponding to the channel region  200   c  and annealing is carried out.  
         [0046]     During the annealing process, the impurity ions doped into the source and drain regions  200   a  and  200   b  are activated and concurrently the silicon layer  22  containing the amorphous silicon is crystallized into the polycrystalline silicon layer  22   a.    
         [0047]     In the present invention, a typical high-temperature annealing process such as a rapid thermal annealing (RTA) process is used as the annealing process. Conventional annealing is carried out under an inert N 2  or O 2  atmosphere while the annealing in the present invention is carried out in an H 2 O atmosphere.  
         [0048]     The annealing in the H 2 O atmosphere shortens annealing time under a condition of the same temperature and reduces annealing temperature under a condition of the same time, compared to the annealing in the N 2  or O 2  atmosphere.  
         [0049]     In particular, a conventional glass substrate that is a transparent insulting substrate is bent due to a high temperature while the substrate in the present invention is not bent because the annealing temperature may be lowered.  
         [0050]     In the present invention, the annealing temperature is preferably in the range of 550 to 750° C. More preferably, the annealing temperature is in the range of 600 to 710° C. because excellent polycrystalline silicon may be achieved with a proper annealing time. Crystallization may not be achieved when the annealing temperature is less than 550° C., and the substrate may be bent when it is more than 750° C.  
         [0051]     Further, it is preferable that the pressure of H 2 O is in the range of 10,000 Pa to 2 MPa. A crystallization rate is proportional to the pressure and thus when the pressure is too low, the crystallization rate becomes low and the annealing time becomes longer, affecting the substrate. On the other hand, too high pressure may cause explosion. For these reasons, the pressure of 10,000 Pa to 2 MPa is desirable for annealing.  
         [0052]     Meanwhile, it is preferable to deposit the silicon layer  22  to a thickness of less than 2,000. Small thickness facilitates crystallization. However, too small thickness may affect the device characteristics when the polycrystalline silicon is used to form a thin film transistor. Accordingly, it is more preferable to deposit the silicon layer to a thickness of 300 to 1,000.  
         [0053]     Although the above-described processes suffice to obtain the polycrystalline silicon, the present invention may further include an annealing process to reduce defects in the formed polycrystalline silicon.  
         [0054]     The further annealing process may be performed by an excimer laser annealing process or heating in a furnace.  
         [0055]     Subsequently, as shown in  FIG. 2E , an interlayer insulating layer  28  is formed on the gate electrode  26  over the entire surface of the substrate, and both the interlayer insulating layer  28  and the gate insulating layer  24  are etched to form contact holes so that the source and drain regions  200   a  and  200   b  are open. Metal is filled into the contact holes to form source and drain electrodes  29   a  and  29   b,  thus completing the thin film transistor.  
         [0056]      FIGS. 3A  to  3 D sequentially illustrate a method of fabricating a semiconductor device according to a third embodiment of the present invention. The method of fabricating the semiconductor device according to the third embodiment of the present invention will be described with reference to  FIGS. 3A  to  3 D.  
         [0057]     Referring to  FIG. 3A , patterning is carried out to form a gate electrode  36  on a substrate  30 . At this time, a normally used insulating and transparent glass substrate is used as the substrate  30 .  
         [0058]     Further, a buffer layer such as SiNx or SiO 2  may be formed on the substrate  30  in order to prevent contaminants or the like created in the substrate from diffusing into the electrode or enhance interface characteristics between the substrate and the electrode.  
         [0059]     A gate insulating layer  34  is then formed of an inorganic insulating layer such as SiO 2  or SiNx on the gate electrode  36  over the entire surface of the substrate  30 .  
         [0060]     Subsequently, amorphous silicon, or a silicon layer  32  containing a great quantity of amorphous silicon is deposited on the gate insulating layer  34 , as shown in  FIG. 3B .  
         [0061]     A typical deposition method, such as a plasma enhanced chemical vapor deposition (PECVD) method or a low-pressure chemical vapor deposition (LPCVD) method, is used to deposit the silicon layer  32 . The PECVD method is performed using SiH 4 +Ar and/or H 2  under a pressure of 1 to 1.5 Torr at a temperature of 330 to 430° C. Further, the LPCVD method is performed using Si 2 H 6 +Ar under a pressure of 0.2 to 0.4 Torr at a temperature of about 400 to 500° C.  
         [0062]     Photoresist is then coated on a channel region  300   c  in the silicon layer  32 , not regions that will correspond to source and drain regions  300   a  and  300   b  later, and impurity ions are implanted into the silicon layer  32 , as shown in  FIG. 3C .  
         [0063]     Subsequently, annealing is carried out. During the annealing process, the impurity ions doped into the source and drain regions  300   a  and  300   b  are activated and concurrently the silicon layer  32  containing the amorphous silicon is crystallized into the polycrystalline silicon layer  32   a.    
         [0064]     In the present invention, a typical high-temperature annealing process such as a rapid thermal annealing (RTA) process is used as the annealing process. Conventional annealing is carried out under an inert N 2  or O 2  atmosphere while the annealing in the present invention is carried out in an H 2 O atmosphere.  
         [0065]     The annealing in the H 2 O atmosphere shortens annealing time under a condition of the same temperature and reduces annealing temperature under a condition of the same time, compared to the annealing in the N 2  or O 2  atmosphere.  
         [0066]     In particular, a conventional glass substrate that is a transparent insulting substrate is bent due to a high temperature while the substrate according to the present invention is not bent because the annealing temperature may be lowered.  
         [0067]     In the present invention, the annealing temperature is preferably in the range of 550 to 750° C. More preferably, the annealing temperature is in the range of 600 to 710° C. because excellent polycrystalline silicon may be achieved with a proper annealing time. Crystallization may not be achieved when the annealing temperature is less than 550° C., and the substrate may be bent when it is more than 750° C.  
         [0068]     Further, it is preferable that the pressure of H 2 O is in the range of 10,000 Pa to 2 MPa. A crystallization rate is proportional to the pressure and thus when the pressure is too low, the crystallization rate becomes low and the annealing time becomes longer, affecting the substrate. On the other hand, too high pressure may cause explosion. For these reasons, the pressure of 10,000 Pa to 2 MPa is desirable for annealing.  
         [0069]     Meanwhile, it is preferable to deposit the silicon layer  32  to a thickness of less than 2,000. Small thickness facilitates crystallization. However, too small thickness may affect the device characteristics when the polycrystalline silicon is used to form a thin film transistor. Accordingly, it is more preferable to deposit the silicon layer to a thickness of 300 to 1,000.  
         [0070]     Although the above-described processes suffice to obtain the polycrystalline silicon, the present invention may further include an annealing process to reduce defects in the formed polycrystalline silicon.  
         [0071]     The further annealing process may be performed by an excimer laser annealing process or heating in the furnace.  
         [0072]     Subsequently, as shown in  FIG. 3D , metal is deposited and patterned on the polycrystalline silicon layer  32   a  over the entire surface of the substrate to form source and drain electrodes  39   a  and  39   b,  thereby fabricating a semiconductor device.  
         [0073]     In the present invention, it is desirable that the semiconductor device is a thin film transistor. The thin film transistor may be either a top gate thin film transistor in which the gate electrode  36  is formed on the polycrystalline silicon layer  32   a,  or a bottom gate thin film transistor in which the gate electrode  36  is formed under the polycrystalline silicon layer  32   a.    
         [0074]     Hereinafter, exemplary examples of the present invention are suggested. However, the examples described below are only intended to assist in understanding the present invention and not limit to the present invention.  
       EXAMPLES 1 to 3  
       [0075]     An amorphous silicon layer was deposited to a thickness of 500 on a substrate. As the deposition method, a low pressure chemical vapor deposition (LPCVD) method was used in Example 1, a plasma enhanced chemical vapor deposition (PECVD) method containing 2% or less of hydrogen was used in Example 2, and a plasma enhanced chemical vapor deposition (PECVD) method containing 10% or more of hydrogen was used in Example 3. The amorphous silicon layer was annealed and crystallized using a rapid thermal annealing (RTA) process at about 710° C. for less than 10 minutes. The annealing was performed using an O 2  or N 2  carrier gas in an H 2 O atmosphere. Raman spectrum of the formed polycrystalline silicon is shown in  FIG. 4 .  
         [0076]     Referring to  FIG. 4 , it may be seen that the polycrystalline silicon obtained by annealing the amorphous silicon according to Examples 1 to 3 of the present invention has excellent crystallinity because full width at half maximum (FWHM) of a Raman peak is in the range of 4.5 to 7.5 cm −1 . Considering that polycrystalline silicon fabricated by a typical method has the Raman peak of more than 8.0 cm −1 , it may be seen that the crystallinity in the present invention becomes excellent by depositing the amorphous silicon using a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method and then crystallizing the deposited amorphous silicon by an RTA process in an H 2 O atmosphere.  
         [0077]     The fabricated polycrystalline silicon thin film is applicable to a thin film transistor, and in turn the thin film transistor may be utilized in a flat panel display device, such as an organic light emitting display device or a liquid crystal display device.  
         [0078]     As described above, according to the present invention, it is possible to reduce the annealing time and the annealing temperature by utilizing the H 2 O annealing atmosphere when the amorphous silicon is deposited using the LPCVD or PECVD method and crystallized using the solid phase crystallization method, thereby preventing process defects such as a bent substrate and improving the crystallinity of the polycrystalline silicon.  
         [0079]     Although the present invention has been described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that a variety of modifications and variations may be made to the present invention without departing from the spirit or scope of the present invention defined in the appended claims, and their equivalents.