Abstract:
A trace function method for microprocessors is provided. The method is operable with a microprocessor comprising an execution unit operable in one or a plurality of contexts. The method comprises: providing a memory coupled to the execution unit, utilizing the memory to store trace data during a trace operation; and providing hardware utilizable during a trace operation to assist in the trace operation.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention pertains to microprocessors, in general, and to a microprocessor debug feature that provides trace capability, in particular. 
       BACKGROUND OF THE INVENTION 
       [0002]    To debug micro-processor code it is desirable to provide trace functionality. A call trace involves providing the target of every call instruction and return instruction. This provides basic program flow data to the user for program analysis. 
         [0003]    A branch trace involves providing the target of every branch instruction in addition to the calls and returns. This provides detail to the user for program analysis. 
         [0004]    In addition to call and branch data, it is desirable to provide context switch and interrupt data for user. For a context switch, it is desirable to provide the context number. 
         [0005]    The mechanism for obtaining this data on a standard microprocessor is to instrument the customer&#39;s code, libraries, etc. Problems with this approach include the fact that code is modified in order to capture the data necessary for the analysis. 
         [0006]    Some micro-processors provide a trace feature that does not have a performance overhead. Such micro-processors require a dedicated trace interface on the micro-processor chip and a dedicated hardware tool connected to the micro-processor any time the trace function is to be used. 
       SUMMARY OF THE INVENTION 
       [0007]    In accordance with the principles of the invention, a method for providing trace functionality for a microprocessor comprising an execution unit comprises: providing a memory coupled to the execution unit, utilizing the memory to store trace data during a trace operation; and providing hardware utilizable during a trace operation to assist in the trace operation. 
         [0008]    In accordance with the principles of the invention the method is operable with a microprocessor comprising an execution unit operable in one or a plurality of contexts. The method comprises: providing a buffer memory coupled to the execution unit. The buffer memory is utilized to store trace data during operation of the execution unit. The method includes providing a trace control coupled to the execution unit and to the buffer memory; providing a breakpoint control coupled to the execution unit, the trace control and the buffer memory; providing a plurality of sets of programmable registers, and each set comprising a base address register, a data register, a data mask register and a control register; and providing in the trace control a programmable trace control register and a programmable base write address register, the trace control register being programmable to determine one of a plurality of trace functions. 
         [0009]    In accordance with an aspect of the invention the buffer may be filled with data trace rather than code execution trace. In this case the user specifies a memory location or range of locations and, optionally, a data mask to filter the contents of writes to the memory, when a write occurs to the specified location(s) the data written is mirrored to the trace buffer. An example application would be to trace on all data received over a UART to try to debug associated driver code. 
         [0010]    In accordance with another aspect of the invention, a timed trace function is also provided. In accordance with the timed trace, in addition to writing data to the trace buffer, the contents of a timer register are also written out. This provides a timestamp for each value/address written to the buffer, giving the user detailed execution timing for either code or a communications interface. 
     
    
     
       DESCRIPTION OF THE DRAWING 
         [0011]    The invention will be better understood from a reading of the following detailed description of an illustrative embodiment of the invention in conjunction with the drawing figures in which: 
           [0012]      FIG. 1  illustrates a register layout in the illustrative embodiment; 
           [0013]      FIG. 2  illustrates a second register layout in the illustrative embodiment; 
           [0014]      FIGS. 3A ,  3 B,  3 C, and  3 D illustrate the layouts of a series of registers in accordance with the principles of the invention; 
           [0015]      FIGS. 4 through 8  are flow diagrams of trace functions in accordance with the principles of the invention; 
           [0016]      FIG. 9  is a block diagram of a microprocessor in accordance with the principles of the invention; 
           [0017]      FIG. 10  is a block diagram of a Trace Control portion of the microprocessor of  FIG. 9 ; and 
           [0018]      FIG. 11  is a block diagram of a Point Control portion of the microprocessor of  FIG. 9 . 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    A feature of the debug environment in accordance with the principles of the invention is that trace is saved to the standard address space. That is, the user can enable call trace or branch trace, and the results are written to any memory in the system as specified by the user. 
         [0020]    For example, if a user enables call trace into external RAM, then each time that an instruction that causes a subroutine call is executed, the address of the routine being called is written to the memory range specified when setting up the trace function. When a return from subroutine instruction is executed, the address that is returned to is written into the trace buffer. These two elements enable a user with the help of appropriate tools to examine program flow after the fact by dumping and inspecting the trace buffer. 
         [0021]    A branch trace involves storing the target of every branch instruction in addition to the calls and returns described above. This provides additional detail to a user for analysis. 
         [0022]    In addition to calls and branches, context switches and interrupt data are stored so that a user can know about these kinds of changes of code flow as well. On a context switch, the context number is also stored. 
         [0023]    As noted above one mechanism for obtaining trace data on a standard microprocessor is to instrument the customer&#39;s code, libraries, etc., but a problem with this approach is that that code is modified in order to capture the data necessary for the analysis. In accordance with the principles of the invention no modification of the code or reloading of code is necessary. In addition the inventive approach also entails less overhead on the processor. 
         [0024]    A block diagram of a microprocessor in accordance with the principles of the invention that provides the trace functionalities described above is shown in  FIG. 9 . Execution unit  901  can be the microprocessor described in United States Patent Application Publication Nos. US-2006-0168426-A1, US-2006-0168428-A1, US-2006-0168420-A1, and US-2006-0168421-A1. The entireties of the disclosures of each of those Publication Nos. are incorporated herein by reference. 
         [0025]    Execution unit  901  has connections to a memory interface  903 . The connections include Write and Read control lines, Address and Data buses. The memory interface  903  provides connections to any existing memory utilized by execution unit  901  including a trace buffer memory, that may be a designated portion of an existing memory or a separate trace buffer memory. 
         [0026]    A memory  911  is shown coupled to memory interface  903 . Memory  911  may be a memory existing on the same chip as the execution unit  901 , another memory associated with execution unit  901  or a separate memory dedicated as a trace buffer. 
         [0027]    The Write and Read control lines, Address and Data buses are coupled to a Trace Control  905  and a Breakpoint Control  907 . 
         [0028]      FIG. 10  shows Trace Control  905  in greater detail. Trace Control  905  includes the Trace Control Register  101  shown in detail in  FIG. 1  and the Base Write Address Register  201  shown in detail  FIG. 2 . Trace Control Register  101  and Base Write Address Register  201  are both coupled to Trace Control Logic  1001 . In addition, a Timer Register  1003  is coupled to Trace Control Logic  1001 . Timer Register may be driven by any timer source associated with the Execution Unit  901  or may be driven by another timer source that is relevant to the timing of operation of the Execution Unit  901 . 
         [0029]      FIG. 11  shows Breakpoint Control  907  in greater detail. Breakpoint Control  907  includes the sets of registers  301 ,  303 ,  305 ,  307  shown in detail  FIGS. 3A ,  3 B,  3 C, and  3 D, i.e., Break Point Address/Watch Point Base Address Register  301 , Watch Point Data Register  303 , Watch Point Data Mask Register  305  and the Break/Watch Point Control Registers  307 . The sets of registers  301 ,  303 ,  305 ,  307  are coupled to Point Control Logic  1101 . 
         [0030]    Trace data can be written to memory in one of three ways:
       1. Single address. In this approach a single word of memory space is used as the target for all data written out. This assumes an external device (such as a logic analyzer) to capture the data for later analysis.   2. Single-shot buffer. A buffer of programmable length is established in memory  911 . Data is written to the buffer from beginning to end. When the buffer is full the tracing operation is stopped.   3. Circular buffer. A buffer of programmable length is established in memory. Data is written to the buffer memory  911  from beginning to end. When the buffer memory  911  fills data writes are wrapped to the beginning of the buffer and the process is started again. By reading the trace control registers the user can determine where the buffer ‘begins’ and ‘ends’ (i.e. where the interface between the oldest data and the newest data is in the buffer), as well as whether the buffer has wrapped over yet or not.       
 
         [0034]    Another option for using the buffer memory  911  is to fill it with data trace rather than code execution trace. In this case the user specifies a memory location or range of locations and, optionally, a data mask to filter the contents of writes to the memory  911 , when a write occurs to the specified location(s) the data written is mirrored to the trace buffer. An example application would be to trace on all data received over a UART to try to debug associated driver code. 
         [0035]    The trace feature is controlled by a group of registers shown in  FIGS. 1 ,  2 ,  3 A,  3 B,  3 C,  3 D. 
         [0036]    One register is the Trace Control Register  101 . The Trace Control Register  101  shown in  FIG. 1  includes nine register fields: 
         [0037]    The Enable field is a one bit field enabled by software, break/watch point and disabled by software, break/watch point or when the trace buffer memory is full. The two states that this field defines are:
       0=Disable   1=Enable       
 
         [0040]    The Full Flag field comprises one bit that is used by simple buffer mode. The bit is set when the buffer fills and is cleared by software writing a 1 to this bit. If the bit is set, hitting break/watch point will not re-enable tracing. 
         [0041]    The Timing Mode field is a one bit field. When the bit=0, the Timing is disabled; when the bit=1, the Timing is enabled. This enables a timer value to be written out for each write to buffer (A 7 ). 
         [0042]    The Trace Mode field is a two-bit field that defines four states by the binary code:
       00=reserved   01=Call Tracing Mode   10=Branch Tracing Mode   11=Data Tracing Mode       
 
         [0047]    The Buffer Mode field specifies a trace buffer mode. Three of the codes are used as follows:
       00=single address mode   01=circular buffer mode   10=simple buffer mode       
 
         [0051]    The Size field is a four bit field used to define the buffer size (used in the case of the buffer modes). The codes and associated sizes are:
       0000=32 bytes   0001=64 bytes   0010=128 bytes   0011=256 bytes   0100=512 bytes   0101=1K bytes   0110=2K bytes   0111=4K bytes   1000=8K bytes   1001=16K bytes   1010=32K bytes   1011=64K bytes   1100=128K bytes   1101=256K bytes   1110=512K bytes   1111=1M bytes       
 
         [0068]    A Base Address Register  201  is provided as a 32 bit register as shown in  FIG. 2 . The base address is a multiple of the size. Hardware treats the least significant n bits as zeros. There are two modes for this feature—a single address mode and a buffer mode. The buffered modes require base to be on size boundary. 
         [0069]    For a Single address mode, all data is written to the same address. This would likely be captured by a logic analyzer and post processed as needed. 
         [0070]    For a Circular Buffer mode, data is written to a memory buffer and when the memory buffer is full, it loops around to the beginning. The Base Address Register  201  always points to the next location to be written, i.e., it is incremented as the buffer is written, then the lower bits are cleared when the end of the buffer is reached. In circular buffer mode, when the end of the buffer is reached, a Full Flag is set and remains set until cleared by software. 
         [0071]    For a Simple Buffer mode, once the buffer is filled to capacity, tracing is disabled, i.e., the Enable bit is cleared, and break/watch points cannot re-enable until the Full Flag is cleared. 
         [0072]    The contents of the Base Address Register  201  always points to the next location to be written to, i.e., it is incremented as the buffer is written, then the lower bits are cleared when the end of the buffer is reached. In Simple Buffer mode, when the end of the buffer is reached, the Full Flag is set and remains set until cleared by software. 
         [0073]    A set of hardware break/trace registers shown in  FIG. 3A ,  3 B,  3 C, and  3 D. The set is repeated a plurality of times, once for each break/watch point. In the illustrative embodiment, the set is repeated eight times. 
         [0074]    The break/watch Point Control Register  307  shown in  FIG. 3D  has eight fields. The two states that this field defines are:
       0=Disable   1=Enable.       
 
         [0077]    The R/W field specifies a watch point memory cycle type. The four states that this field defines are:
       00=Read or Write   01=Write   10=Read   11=Reserved.       
 
         [0082]    The Context Aware field is a two bit field. The two states that this field defines are:
       0=Any context will do.   1=Specified context only.       
 
         [0085]    A three bit Context field is used if break/watch points are context specific. 
         [0086]    A Type field is a one bit field that defines the functionality type. The two states that this field defines are:
       0=Breakpoint   1=Watchpoint       
 
         [0089]    A Mode field is a two bit field that defines an operational mode. The four states that this field defines are:
       00=Disable trace (disable currently running trace)—Added for A 16     01=Enable trace-mode defined by DebugTraceBufferRegisters.   10=Break Point   11=Chain, enable next breakpoint/watchpoint, last one in chain triggers break or trace.       
 
         [0094]    A Block Size field is a four bit field. The watch point will “watch” memory in the block sizes:
       0000—1 Byte   0001—2 Bytes   0010—4 Bytes   0011—8 Bytes   0100—16 Bytes   0101—32 Bytes   0110—64 Bytes   0111—128 Bytes   1000—256 Bytes   1001—512 Bytes   1010—1024 Bytes   101—2048 Bytes   1100—4096 Bytes   1101—8192 Bytes   1110—16384 Bytes   1111—32768 Bytes       
 
         [0111]    To enable call trace a user sets up registers as follows:
       Base Write Address of  FIG. 2  set to provide a base address for buffer (user selected)—in internal user RAM or external SRAM or SDRAM.   Trace Control Register of  FIG. 1 :
           Enable=Enabled   Trace Mode=Call Tracing Mode   Buffer Mode/Buffer Size=user selectable   
               
 
         [0117]    Once this is set up, the following behaviors are enabled:
       Execution of a BSR (Branch to Subroutine) or JSR (Jump to Subroutine) instruction will cause the 32-bit address of the called subroutine to be written out to the trace buffer.   Execution of a RTS (Return from Subroutine) or RTD (Return and Deallocate) instruction will cause the 32-bit address of the instruction returned to be written out to the trace buffer.   Execution of an exception (interrupt or fault) will cause the 32-bit address of the exception handler to be written out to the trace buffer.   Execution of a RTE (Return from Exception) instruction will cause the 32-bit address of the instruction returned to be written out to the trace buffer.       
 
         [0122]    A Change of hardware context will cause the number of the new context to be written to the trace buffer (as a 32-bit integer). 
         [0123]    To enable branch trace the user would set up registers as follows:
       Base Write Address Register  201  of  FIG. 2  is set to a base address for a user selected buffer—an internal user RAM or external SRAM or SDRAM.       
 
         [0125]    The Trace Control Register of  FIG. 1  is set up as follows:
           Enable=Enabled   Trace Mode=Branch Tracing Mode   Buffer Mode/Buffer Size=user selectable           
 
         [0129]    Once the registers are set up, the following behaviors are enabled: 
         [0130]    All behaviors activated during Call Trace (see above);
       Execution of an Unconditional Branch instruction (JMP, BRA) will cause the address branched to be written to the trace buffer;   Execution of a Conditional Branch instruction (Bcc, DBcc, where ‘cc’ is a specific condition, e.g., EQ, NE, PL) will cause the next address to be executed to be written to the trace buffer. That is, if the branch is taken, then the address of the branch target will be written; if the branch is not taken, then the address of the instruction following the branch instruction will be written.       
 
         [0133]    A Data Trace requires the setup of both the Trace Control Register  101  of  FIG. 1  and at least one set of Break/Watchpoint Registers  301 ,  303 ,  305 ,  307  of  FIGS. 3A ,  3 B,  3 C,  3 D. The Trace Control Register  101  of  FIG. 1  controls where the data gets written out, the Break/Watchpoint registers  301 ,  303 ,  305 ,  307  of  FIGS. 3A ,  3 B,  3 C,  3 D determine what data gets written out. The Registers  101 ,  201   301 ,  303 ,  305 ,  307  are setup as follows: 
         [0134]    The Base Write Address Register  201  of  FIG. 2  is set to the base address for the trace buffer by the user. The base address may be for internal user RAM or external SRAM or SDRAM. 
         [0135]    Trace Control Register  101  of  FIG. 1  is set as follows:
       Enable field is set to enable;   Trace Mode is set to the Data Tracing Mode; and   Buffer Mode/Buffer Size is selected by the user.       
 
         [0139]    The Break Point Address/Watch Point Base Address Register  301  of  FIG. 3A  is set to the address of data to be traced 
         [0140]    The Watch Point Data Register  303  of  FIG. 3B  is optionally set to a data pattern to be traced. 
         [0141]    The Watch Point Data Mask Register  305  of  FIG. 3C  is set to define what portions of a 32-bit word are to be compared to the Watch Point Data Register. For example, all zeros means trace on any data pattern. 
         [0142]    The Break/Watch Point Control Register  307  of  FIG. 3D  is set as follows:
       Enable=Enabled   R/W=User selectable (trace only reads, only writes, or reads and writes).   Context Aware=User selectable (trace all contexts or only one)   Context=User selection   Type=Watchpoint   Mode=Enable Trace   Block Size=User selection       
 
         [0150]    With the above register arrangement, when a memory access meets the parameters set up in the Watchpoint registers  301 ,  303 ,  305 ,  307  of  FIGS. 3A ,  3 B,  3 C,  3 D, the data written/read to/from the traced address range will be copied into the trace buffer. 
         [0151]    For any of the trace modes, i.e., Call Trace, Branch Trace, or Data Trace, if the timing field flag of the Trace Control Register  101  of  FIG. 1  is set, the trace behavior is changed such that prior to writing out the data/address as usual, a 32-bit timer value is written out first. This gives a trace buffer organized as:
       Time   Data   Time   Data   Time   Data.       
 
         [0158]    Where “Data” is either an address in Call Trace or Branch Trace mode or the data captured in Data Trace. This allows the user to determine what the timing is on various accesses including the time spent in a given subroutine or other program. 
         [0159]    The timer value can come from a number of sources of different periods or precision. 
         [0160]    Using the breakpoint registers described above, either in breakpoint mode or data trace mode, tracing can be enabled or disabled by various system events. 
         [0161]    By way of example, in the register setups set out above if the enable flag in the Trace Control Register  101  of  FIG. 1  is disabled and a breakpoint is in the mode field of the Break/Watchpoint Control Register  307  of  FIG. 3D  is set to enable trace, when the event defined in the break/watch point occurs the trace begins, rather than breaking code execution. 
         [0162]    Similarly, if the mode of the Break/Watchpoint Control Register  307  of  FIG. 3D  is set to disable trace, a breakpoint can be used to disable a trace that is currently executing. Using this approach, trace can be set to start on some event, or some sequence of events using the chaining feature of the breakpoints, and end on another event, tracing only the portion of execution that the user is interested in. 
         [0163]    Turning now to  FIG. 4 , the trace function for a call instruction is shown. When a call instruction is identified at step  401 , the subroutine address is calculated at step  403 . At step  405 , a determination is made as to whether or not the Trace Control Register  101  is set to enable either a Call or Branch Trace. If not, the instruction is completed at step  413 . If it is determined that the Trace Control Register  101  is set to enable either a Call or Branch Trace at step  405 , then a determination is made at step  407  as to whether or not the Trace Timing mode is called out by the Trace Control Register  101 . If not, the subroutine address is written to the Trace Buffer  911  at step  411 . If Trace Timing is called for at step  407 , then at step  409  the timer value is written to Trace Buffer  911  and then the subroutine address is written to the Trace Buffer at step  411 . After the subroutine address is written to the Trace Buffer  911 , the instruction is completed at step  413 . 
         [0164]    Turning now to  FIG. 5 , the trace function for a branch instruction is shown. When a call instruction is identified at step  501 , the next instruction address is calculated at step  503 . At step  505 , a determination is made as to whether or not the Trace Control Register  101  is set to enable a Branch Trace. If not, the instruction is completed at step  513 . If it is determined that the Trace Control Register  101  is set to enable a Branch Trace at step  505 , then a determination is made at step  507  as to whether or not the Trace Timing mode is called out by the Trace Control Register  101 . If not, the next address is written to the Trace Buffer  91  lat step  511 . If Trace Timing is called for at step  507 , then at step  509  the timer value is written to Trace Buffer  911  and then the address is written to the Trace Buffer  911  at step  511 . After the subroutine address is written to the Trace Buffer  911 , the instruction is completed at step  513 . 
         [0165]    Turning now to  FIG. 6 , the trace function for a return instruction is shown. When a return instruction is identified at step  601 , a return address is obtained at step  603 . At step  605 , a determination is made as to whether or not the Trace Control Register  101  is set to enable either a Call or Branch Trace. If not, the instruction is completed at step  613 . If it is determined that the Trace Control Register  101  is set to enable either a Call or Branch Trace at step  605 , then a determination is made at step  607  as to whether or not the Trace Timing mode is called out by the Trace Control Register  101 . If not, the return address is written to the Trace Buffer  911  at step  611 . If Trace Timing is called for at step  607 , then at step  609  the timer value is written to Trace Buffer  911  and then the return address is written to the Trace Buffer  911  at step  611 . After the subroutine address is written to the Trace Buffer  911 , the instruction is completed at step  613 . 
         [0166]    Turning now to  FIG. 7 , the trace function for when contexts are switched is shown. When an exception is identified at step  701 , a determination is made at step  703  as to whether or not a context switch is required. If a context switch is required, a switch is made to the new context at step  705 . Then a determination is made at step  707  as to whether or not the Trace Control Register  101  is set to enable either a Call or Branch Trace. If it is determined that the Trace Control Register  101  is set to enable either a Call or Branch Trace then the Context number is written to the Trace Buffer  911  at step  709 . 
         [0167]    After the context number is written to the Trace Buffer  911  at step  709 , or if at step  703  it is determined that a context switch is not required, or if at step  707  it is determined that the Trace Control Register  101  is not set to enable a Call or Branch trace, then a vector address for a new context/interrupt is obtained at step  711 . After obtaining a vector address for the new context/interrupt at step  711 , a determination is made at step  713  as to whether a Call Trace or a Branch Trace is enabled. 
         [0168]    If it is determined at step  713  that neither a Call Trace nor a Branch Trace is enabled for that context, then the exception execution is completed at step  721 . If, at step  713 , it is determined that a Call Trace or Branch Trace is enabled, then a determination is made at step  715  as to whether or not the Trace Timing mode is called out by the Trace Control Register  101 . If not, the target address is written to the Trace Buffer  911  at step  719 . If Trace Timing is called for at step  715 , then at step  717  the timer value is written to Trace Buffer  911 . After the target address is written to the Trace Buffer, the exception execution is completed at step  721 . 
         [0169]    Turning now to  FIG. 8 , the Memory Access Trace function is shown. At step  801 , any instruction that affects memory is identified. At step  803 , the basic instruction is executed. At step  805  it is determined whether or not the Memory Access Trace function is enabled in Trace Control Register  101 . If not, the instruction is completed at step  813 . If it is determined that the Memory Access Trace function is enabled, then a determination is made to determine if Trace Timing is called for at step  807 . If trace timing is called for, then at step  809  the timer value is written to Trace Buffer  911 . The memory data is written to the Trace Buffer  911  at step  811  and then the instruction is completed at step  813 . 
         [0170]    The invention has been described in conjunction with the illustrative embodiment. As will be appreciated by those skilled in the art, the invention is not limited to the specific embodiment shown. Various changes and modifications may be made to the embodiment without departing from the spirit or scope of the invention. It is intended that the invention be limited only by the claims appended hereto. It is further intended that the claims be given the broadest scope to which they are permitted.