Abstract:
Design structure for memory array repair where the repair logic cannot operate at the same operating condition as the memory array is presented. In one embodiment, a test is run with the memory array configured in a first operating condition that repair logic for the memory array cannot achieve, and test data is accumulated from the test in the memory array. The memory array is then read with the memory array configured in a second operating condition that the repair logic can achieve using the test data from the test at the first operating condition. As a result, repairs can be achieved even though the repair logic is incapable of operating at the same condition as the memory array. A method, test unit and integrated circuit implementing the testing are presented.

Description:
This application relates to U.S. Ser. No. 11/275,540, filed Jan. 13, 2006, currently pending 
   BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The invention relates generally to memory array analysis, and more particularly, to a memory array repair where repair logic cannot operate at the same operating condition as the memory array. 
   2. Background Art 
   Testing and repair of memory arrays prior to release to a customer is a common practice during integrated circuit (IC) and/or memory array fabrication. For example, ICs oftentimes include embedded memory arrays such as an embedded dynamic random access memory (DRAM) array, which requires testing and repair. These embedded memory arrays are analyzed by the fabricator using a built-in-self-test (BIST) unit that is included on the IC or using separate, stand alone testing units. 
   One challenge during testing is addressing situations where the memory array can operate at an operating condition that the repair logic, used to evaluate and repair the embedded memory array, cannot achieve. Repair logic may be any system, such as a redundancy analyzer, used to capture memory cell failures and repair and/or replace memory cell assignments to ensure proper operation of the embedded memory. For example, one operating condition at which a memory array may operate and the repair logic may not be able to achieve is a higher speed. For example, a memory array may run at, for example, 500 MHz, while the repair logic may only be able to run at, for example, 100-200 MHz. In this case, when the test unit runs with the memory array configured for the higher speed, i.e., 500 MHz, it is impossible for the repair logic to repair all faults at the higher speed. Another operating condition at which a memory array may operate and the repair logic may not be able to achieve is a higher latency. For example, a discrete DRAM array may have different amounts of latency. For instance, a conventional discrete DRAM array may have a 20 ns latency, i.e., 50 MHz, which is allowed to be broken into 4 separate clocks of 5 ns each, so that the memory array operates at 200 MHz. That is, once testing is started, data can be acquired every 5 ns, just not from the same address. Repair logic, however, is typically not sophisticated enough to handle latency with 4 clocks. In this case, an address input to the DRAM array during testing will be read out in such a way that it is always off by some parameter, e.g., a number of addresses. That is, the data read out of the memory array by the repair logic is always late by 3-4 cycles such that the address that exists in the repair logic is continuously trailing the memory array. As a result, the repair logic places repair data in the wrong DRAM array address, and proper repair cannot be achieved. 
   The above-described situation is especially problematic where repair logic is embedded with the memory array because it is generally impracticable to provide repair logic that operates at all of the operating conditions, e.g., higher speed, lower latency, etc., that the memory array can achieve because it uses up too much valuable silicon space. It also should be understood that this situation occurs for all types of memory arrays, embedded or discrete, and for BIST units and stand alone test units. 
   There is a need in the art for a way to repair a memory array where the repair logic is incapable of operating at the same condition as the memory array. 
   SUMMARY OF THE INVENTION 
   Design structure for memory array repair where the repair logic cannot operate at the same operating condition as the memory array is disclosed. In one embodiment, a test is run with the memory array configured in a first operating condition that repair logic for the memory array cannot achieve, and test data is accumulated from the test in the memory array. The memory array is then read with the memory array configured in a second operating condition that the repair logic can achieve using the test data from the test at the first operating condition. As a result, repairs can be achieved even though the repair logic is incapable of operating at the same condition as the memory array. A method, test unit and integrated circuit implementing the testing are disclosed. 
   A first aspect of the invention provides a method of testing a memory array, the method comprising the steps of: running a test with the memory array configured in a first operating condition that a repair logic for the memory array cannot achieve, and accumulating test data from the test in the memory array; reading the test data from the memory array with the memory array configured in a second operating condition that the repair logic can achieve; and repairing the memory array using the repair logic and the test data. 
   A second aspect of the invention provides a test unit for a memory array including repair logic, the test unit comprising: a tester for testing the memory array configured in a first operating condition that the repair logic cannot achieve, and accumulating test data from the tester in the memory array; and a controller for allowing the repair logic to read and repair the memory array with the memory array configured in a second operating condition that the repair logic can achieve using the test data created by the test at the first operating condition. 
   A third aspect of the invention provides an integrated circuit including an embedded memory array including repair logic for the embedded memory array, the integrated circuit comprising: a built-in-self-test (BIST) unit for the embedded memory array, the BIST unit including: a tester for testing the memory array configured in a first operating condition that the repair logic cannot achieve, and accumulating test data from the test in the memory array; and a controller for allowing the repair logic to read and repair the memory array with the memory array configured in a second operating condition that the repair logic can achieve using the test data created by the tester at the first operating condition. 
   A fourth aspect is directed to a design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising: a test unit for a memory array including repair logic, the test unit comprising: a tester for testing the memory array configured in a first operating condition that the repair logic cannot achieve, and accumulating test data from the test in the memory array; and a controller for allowing the repair logic to read and repair the memory array with the memory array configured in a second operating condition that the repair logic can achieve using the test data created by the tester at the first operating condition. 
   A fifth aspect is directed to a design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising: an integrated circuit including an embedded memory array including repair logic for the embedded memory array, the integrated circuit comprising: a built-in-self-test (BIST) unit for the embedded memory array, the BIST unit including: a tester for testing the memory array configured in a first operating condition that the repair logic cannot achieve, and accumulating test data from the test in the memory array; and a controller for allowing the repair logic to read and repair the memory array with the memory array configured in a second operating condition that the repair logic can achieve using the test data created by the tester at the first operating condition. 
   The illustrative aspects of the present invention are designed to solve the problems herein described and/or other problems not discussed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which: 
       FIG. 1  shows a schematic diagram of one embodiment of a memory array repair structure according to the invention. 
       FIG. 2  shows a schematic diagram of another embodiment of a memory array repair structure according to the invention. 
       FIG. 3  shows a flow diagram of one embodiment of a memory array repairing according to the invention. 
       FIG. 4  shows a block diagram of an example design flow. 
   

   It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings. 
   DETAILED DESCRIPTION 
   Referring to the drawings,  FIG. 1  shows a schematic diagram of one embodiment of a memory array repair structure according to the invention. As shown in  FIG. 1 , in one embodiment, memory array repair according to the invention can be applied to an integrated circuit  10  (IC) including, inter alia, a built-in self test (BIST) unit  12  that is mated with one or more embedded memory arrays  14  along with each memory array&#39;s corresponding repair logic  26 . It should be recognized that other physical layouts are also possible and considered within the scope of the invention. For example,  FIG. 2  shows another embodiment in which memory array testing according to the invention is applied to a discrete memory array  114 , separate from an IC  10  ( FIG. 1 ), and a stand alone test unit  112  is used. As illustrated, repair logic  26  is part of test unit  112 , however, this is not necessary. In addition, stand alone test unit  112  could be used with an embedded memory array  14  ( FIG. 1 ) within an IC  10  ( FIG. 1 ). Test unit  12 ,  112  and memory arrays  14 ,  114  each may include appropriate interfaces  16 . 
   As used herein, “memory array” refers to any now known or later developed data storage device that functions like an electronic checkerboard, with each memory element holding one unit (e.g., one byte) of data or instruction, e.g., DRAM, static random access memory (SRAM), etc. Each memory element has a separate address and can be manipulated independently. Each memory array  14 ,  114  may include a specific design of a plurality of general memory elements  18  and a set of redundant memory elements  20 . General memory elements  18  are initially intended for operation, and redundant memory elements  20  are provided to replace failing memory elements, general or redundant. “Replace” means a redundant memory element  20  is swapped for or exchanged for the failing memory element. Alternatively, each memory array  14 ,  114  may take the form of a compilable (or customizable) memory design in which the number of the plurality of memory elements  18  and the set of redundant memory elements  20  can be user selected. 
   Repair logic  26  may include any system, such as a redundancy analyzer  28 , used to analyze memory element  18 ,  20  failures and repair and/or replace memory element  18 ,  20  assignments to ensure proper operation of memory array  14 ,  114 . Repair logic  26  may also include a conventional set of failing address registers (FAR)  30  and other control logic  32 . As shown in  FIG. 2 , repair logic  26  may be provided as part of stand alone test unit  112 , or, as shown in  FIG. 1 , a group of memory arrays  14  may share a single repair logic  26 . Alternatively, in  FIG. 2 , each memory array  114  may include corresponding repair logic  26 . Although repair logic  26  is shown as a separate entity in  FIG. 1 , it should be recognized that repair logic  26  may be provided as part of a memory array  14 . 
   BIST unit  12  and test unit  112  (collectively referred to hereafter as “test unit”) each include, inter alia, a state machine  22  that includes, inter alia, a tester  24  and a controller  40 . Collectively, tester  24  and controller  40  allow repair logic  26  of a respective memory array  14 ,  114  to analyze test data  42  created at an operating condition of the respective memory array  14 ,  114  that repair logic  26  cannot achieve. In particular, referring to first step S 1  in  FIG. 3 , tester  24  tests memory array  14 ,  114  configured in a first operating condition that repair logic  26  cannot achieve, and accumulates test data  42  from the test, not in repair logic  26  as is conventional, but in memory array  14 ,  114 . The “operating condition” can be any state of memory array  14 ,  114  at which repair logic  26  cannot achieve the same functioning. For example, the operating condition can include at least one of: a speed, a temperature, a voltage, an operation mode and a latency. Tester  24  implements a test of memory array  14 ,  114  at the first condition in which values are written to enable memory elements  18 ,  20  and then stored in memory array  14 ,  114 . Tester  24  may implement common test functions such as write pattern selects, data generators, address counters, etc., to carry out the test. 
   Next, as shown as step S 2  in  FIG. 3 , controller  40  allows repair logic  26  to read test data  42  (created by the test at the first operating condition) from memory array  14 ,  114  with memory array  14 ,  114  configured in a second operating condition that repair logic  26  can achieve. In one embodiment, first and second operating conditions are the same type of condition, i.e., speed and speed, temperature and temperature, etc. However, this is not necessary. Next, as shown in step S 3  of  FIG. 3 , controller  40  allows repair logic  26  to repair memory array  14 ,  114  using test data  42 . For example, repair logic  26  may invoke redundancy analyzer  28  to determine whether a failure exists by comparing the test data  42  with the values written thereto by test unit  12 ,  112 . If test data  42  and the value written do not match, a fail signal is activated (generated) by redundancy analyzer  28  and the failing memory element is replaced with a redundant memory element  20 . 
   One operating condition for which the above-described embodiment can be employed is speed. For example, tester  24  may test memory array  14 ,  114  with the first operating condition being a higher speed than the second operating condition. In this example, tester  24  may configure memory array  14 ,  114  to operate at a speed of, for example, 500 MHz, and accumulate test data  42  in memory array  14 ,  114 . Repair logic  26  may not be able to achieve the 500 MHz speed, so typically it would not be able to repair memory array  14 ,  114  at that speed without use of the invention. Controller  40  may then allow repair logic  26  to analyze memory array  14 ,  114  using test data  42  at the second operating condition of, for example, 100 MHz. In this fashion, repair logic  26  need not be modified to accommodate all of the different operating conditions of memory array  14 ,  114  and can analyze memory array  14 ,  114  at operating conditions that repair logic  26  cannot achieve. Where the test unit includes a BIST unit  12 , it may be used during packaging and may be enabled in the function of the final product. 
   A BIST unit  12 , test unit  112  or IC  10 , which may be referred to herein as a design structure, is created in a graphical computer programming language, and coded as a set of instructions on machine readable removable or hard media (e.g., residing on a graphical design system (GDS) storage medium). That is, design structure(s) is embodied in a machine readable medium used in a design process. (The design structure(s) may interface with any part of a machine readable media). The design structure(s) may include a netlist, which describes BIST unit  12 , test unit  11  and/or IC  10 , and may include test data files, characterization data, verification data, or design specifications. If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design structure by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities as a foundry, directly or indirectly. The stored design is then converted into the appropriate format (e.g., graphic design system II (GDSII)) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed. 
     FIG. 4  shows a block diagram of an example design flow  900 . Design flow  900  may vary depending on whether BIST unit  12 , test unit  11  and/or IC  10  is being designed. For example, a design flow  900  for building an application specific IC (ASIC) may differ from a design flow  900  for designing a component, e.g., a BIST unit  12 . Design structure  920  is preferably an input to a design process  910  and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure  920  comprises BIST unit  12 , test unit  11  and/or IC  10  in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure  920  may be contained on one or more machine readable medium. For example, design structure  920  may be a text file or a graphical representation of an IC  172  including transistor  170 . Design process  910  preferably synthesizes (or translates) BIST unit  12 , test unit  11  and/or IC  10  into a netlist  980 , where netlist  980  is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist  980  is resynthesized one or more times depending on design specifications and parameters for the circuit. 
   Design process  910  may include using a variety of inputs; for example, inputs from library elements  930  which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications  940 , characterization data  950 , verification data  960 , design rules  970 , and test data files  985  (which may include test patterns and other testing information). Design process  910  may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process  910  without deviating from the scope and spirit of the disclosure. The design structure of the disclosure is not limited to any specific design flow. 
   Design process  910  preferably translates an embodiment of the disclosure as shown in  FIGS. 1  and/or  2 , along with any additional integrated circuit design or data (if applicable), into a second design structure  990 . Design structure  990  resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Design structure  990  may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the disclosure as shown in  FIGS. 1-2 . Design structure  990  may then proceed to a stage  995  where, for example, design structure  990 : proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc. 
   The design structure, structures and methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
   The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.