Abstract:
A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, each electrode including a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer; and forming a plurality of electrodes of transistors of the circuitry each including a first dielectric layer and a first conductive layer. The method also includes forming first coating spacers on the side walls of the gate electrodes of the memory cell and second coating spacers on the side walls of the gate electrodes of the circuitry, the second spacers being wider than the first spacers.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method for manufacturing non-volatile memory devices integrated on a semiconductor substrate.  
         [0003]     More specifically, the invention relates to a method for manufacturing non-volatile memory devices integrated on a semiconductor substrate comprising a matrix of non-volatile memory cells and associated circuitry, the manufacturing method comprising the following steps: 
        forming a plurality of gates of the matrix memory cells, comprising a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer,     forming a plurality of gates of high voltage (HV) transistors of said circuitry,     coating, with at least one protection dielectric layer, said gates of the matrix and of the circuitry.        
 
         [0007]     The invention particularly, but not exclusively, relates to a method for realizing spacers of different lengths in memories of the EPROM, EEPROM, flash EEPROM type and the following description is made with reference to this field of application by way of illustration only.  
         [0008]     2. Description of the Related Art  
         [0009]     As it is well known, non-volatile memory electronic devices, for example of the EPROM and Flash EEPROM type, integrated on semiconductor, comprise a plurality of non-volatile memory cells organized in a matrix.  
         [0010]     Each single non-volatile memory cell comprises a MOS transistor having a gate electrode, arranged above the channel region, that is floating, i.e., it as a high impedance in DC towards all the other terminals of the same cell and of the circuit wherein the cell is inserted. Generally, this floating gate electrode is realized by means of a polysilicon layer.  
         [0011]     The cell also comprises a second electrode, called control gate electrode, which is capacitively coupled to the floating gate electrode through an intermediate dielectric layer, so called interpoly. Generally, the control electrode is realized by means of a polysilicon layer. This second electrode is driven through suitable control voltages. The other terminals of the transistor are the usual drain and source regions.  
         [0012]     The matrix of memory cells is associated with control circuitry comprising a plurality of MOS transistors, each comprising a source region and a drain region separated by a channel region. A gate electrode is then formed on the channel region and insulated therefrom by means of a gate oxide layer. Moreover, insulating spacers are provided on the side walls of the gate electrode.  
         [0013]     However, in new generation memory devices, in the circuitry associated with the memory matrix both MOS HV transistors suitable to sustain high voltages and MOS low voltage (LV) transistors suitable to sustain low voltages are integrated, which, together with the memory cells, have different specifications for the realization of the spacers.  
         [0014]     To make the problems related to the realization of these spacers clearer, the known process steps are now described to form differential spacers in a conventional memory device comprising a matrix  2  of non-volatile memory cells and associated circuitry  3  comprising both HV transistors suitable to sustain high voltages and LV transistors suitable to sustain low voltages.  
         [0015]     With reference to FIGS.  1  to  5 , a portion of a semiconductor substrate  1  is shown where the memory cells of the memory matrix  2  and the HV transistors of the circuitry  3  are realized, while the portion of a semiconductor substrate  1  where the LV transistors are realized is not shown.  
         [0016]     In particular, as shown in  FIG. 1  on a semiconductor substrate  1  after having defined active areas for the memory matrix  2  and for the circuitry  3 , in the memory matrix  2  a plurality of floating gates  4  of the memory cells is formed, each gate comprising a first gate dielectric layer  5 , called tunnel oxide, a first conductive layer  6 , for example of polysilicon, a second interpoly dielectric layer  7 , which can be an oxide layer or the overlapping of more layers, for example ONO (oxide/nitride/oxide) and a second conductive layer  8 , for example of polysilicon.  
         [0017]     In these known configurations, pairs of adjacent memory cells share the same source region.  
         [0018]     In the circuitry  3  a plurality of gates  9  of the HV transistors is instead formed. Each gate  9  of the HV transistors comprises, for example, a gate dielectric layer  7 ′ and a conductive layer  8 ′ of the circuitry  3 . Advantageously, the gate dielectric layer  7 ′ of the circuitry  3  and the conductive layer  8 ′ of the circuitry  3  are formed, respectively, by the interpoly dielectric layer  7  and by the second conductive layer  8  used in the matrix  2 .  
         [0019]     After having carried out an oxidation step forming a protective film  9 ′ on all the devices present on the semiconductor substrate  1 , a first oxide layer  10  is then deposited. This first oxide layer  10  has the function of reducing the stress generated by the deposition of a successive nitride layer  11  on the gates  4  and  9 . Moreover, the first oxide layer  10  serves as “stopping layer” in the etching step of the successive nitride layer  11 .  
         [0020]     The nitride layer  11  is then deposited on the whole semiconductor substrate  1  which will be used for the formation of spacers of the LV transistors of the circuitry  3  and of spacers of the matrix  2  cell. This nitride layer  11  completely fills the space present between pairs of memory cells in correspondence with the shared source region.  
         [0021]     On the nitride layer  11  a second oxide layer  12  is also deposited which will be used for the formation of differential spacers, those of the HV transistors in the circuitry  3 .  
         [0022]     As shown in  FIG. 2 , an etching step in plasma blanket is carried out of the second oxide layer  12 , selective with respect to the nitride layer  11  to form oxide spacers  13  above the nitride layer  11  aligned with the side walls of the gates  4 ,  9 .  
         [0023]     In particular in the matrix  2 , since the source region shared by two adjacent cells is completely covered by the nitride layer  11 , the spacers  13  are formed only on the side walls of pairs of gates  4  of memory cells.  
         [0024]     As shown in  FIG. 3 , by means of a conventional photo-lithographic technique a first mask  14  is formed for the differential spacers  13 . This mask  14  for the differential spacers completely covers the HV transistors of the circuitry  3 .  
         [0025]     As shown in  FIG. 4 , a removal step of the differential spacers  13  is then carried out in the areas left exposed by the mask  14 , for example in the matrix  2  and in the LV transistors of the circuitry, to which a removal step of this mask  14  for the differential spacers follows.  
         [0026]     With this process step the spacers  13  are completely removed from the matrix  2  and from the LV transistors of the circuitry, but the spacers  13  remain for the HV transistors of the circuitry  3 .  
         [0027]     As shown in  FIG. 5 , an etching step in plasma blanket of the nitride layer  11  is carried out. In particular this etching step is highly selective with respect to the first oxide layer  10 .  
         [0028]     With this etching step, short first nitride differential spacers  15  are formed on the side walls of the electrodes  9  in the matrix  2  and in the portion of circuitry  3  where the LV transistors are realized, while long second nitride differential spacers  16  are formed in the portion of circuitry  3  where the HV transistors are realized.  
         [0029]     The HDD implants are then carried out in circuitry and if necessary in matrix.  
         [0030]     At this point of the process as shown in  FIG. 6 , a pre-silicidation cleaning step is carried out for the removal of oxide layers  9 ′,  10 , if present.  
         [0031]     A cobalt silicide layer is finally formed. In particular the silicide layer is formed in the matrix  2  in correspondence with the drain regions between the spacers  15  of corresponding pairs of memory cells.  
         [0032]     The process is completed in a conventional way by means of the deposition of a borderless nitride layer and of the pre-metal dielectric layer, to which the definition and the formation of contacts is made follow.  
         [0033]     Although advantageous under several aspects, this method shows some drawbacks.  
         [0034]     In fact the continuous reduction of the sizes of memory devices involves the continuous decrease of the size of the cell drain and thus of the effective area for the drain contact in case devices are processed under alignment conditions close to the required specification limits and with a flow with borderless contacts wherein, thus, contacts can be self-aligned with the spacers.  
         [0035]     This problem is generally complicated due to the need to form the spacers to define some source and drain regions of both Low Voltage (LV) and High Voltage (HV) transistors. The shape of the spacers in the matrix is, on the other hand, critical since it affects the deposition of the pre-metal dielectric risking to originate passing voids which would put the drain contacts in short. The size of the spacers is instead even more critical in the matrix since it reduces the size of the drain wherein the contacts are to be defined: in case of misalignment between contact mask and gate definition mask, the effective contact area is particularly reduced originating cell read/program problems due to the increase of the contact resistance. This problem is particularly evident in those process flows wherein nitride spacers and a borderless nitride layer are used under the pre-metal oxide to avoid the breaking of the field oxide in cases of misalignment of the contacts with respect to the active area. In this case the contact self-aligns to the spacer and thus in case of misalignment with respect to the gate definition mask, the contact area is particularly reduced.  
       BRIEF SUMMARY OF THE INVENTION  
       [0036]     One embodiment of the present invention is a method for increasing the space available for the cell drain contact also in case of misalignment mask contacts towards the cell definition mask leaving however a dielectric layer to protect the cell wall, overcoming the drawbacks still limiting the processes realized according to the prior art of the method does so reducing the length of the spacers in matrix.  
         [0037]     One embodiment of the invention is directed to method for manufacturing non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: 
        forming a plurality of gates of the matrix memory cells and a plurality of gates of transistors of the circuitry,     coating, with at least one protection dielectric layer, the gates of the matrix and of the circuitry;     coating, with a first coating layer, the gates of the matrix and of the circuitry, the first coating layer being highly selective with respect to the protection dielectric layer;     forming an intermediate dielectric layer on the first coating layer;     forming a second coating layer on said intermediate dielectric layer, the second coating layer being highly selective with respect to said intermediate dielectric layer;     carrying out a first blanket etching step of the second coating layer, selective with respect to the intermediate dielectric layer, to form first coating spacers on the intermediate dielectric layer respectively aligned with side walls of the gates of the memory cells and second coating spacers on the intermediate dielectric layer respectively aligned with side walls of the gates of the circuitry;     shielding the gates of the transistors of the circuitry with a photo-lithographic mask;     carrying out a selective removal step of the second coating layer in areas left exposed by the photo-lithographic mask to completely remove the first coating spacers of the matrix;     removing the mask;     carrying out a blanket etching step of the intermediate dielectric layer until the first coating layer, covering an upper portion of the gates, is uncovered so as to form first dielectric spacers in the matrix and second dielectric spacers in the circuitry;     carrying out an etching step in plasma of the coating layers and of the second coating spacers, until the dielectric layers covering the gates on top are uncovered;     carrying out HDD implants in the circuitry;     carrying out a blanket etching step of the protection dielectric layer until upper portions of the gates are uncovered and the second dielectric spacers are removed and thus uncovering third coating spacers on the side walls of the gates of the memory cells and fourth coating spacers on the side walls of the gates of the circuitry, the fourth spacers being wider than the third spacers.        
 
         [0051]     The characteristics and advantages of the device according to the invention will be apparent from the following description of an embodiment thereof given by way of indicative and non limiting example with reference to the annexed drawings. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0052]     In these drawings:  
         [0053]     FIGS.  1  to  6  are respective section schematic views of a portion of integrated circuit during the successive manufacturing steps of a known method,  
         [0054]     FIGS.  7  to  13  are respective section schematic views of a portion of integrated circuit during the successive manufacturing steps of a method according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0055]     With reference to the figures, a method is described for manufacturing non-volatile memory devices integrated on a semiconductor substrate  1  and comprising a matrix  2  of non-volatile memory cells  25  and associated circuitry  3 .  
         [0056]     The process steps described hereafter do not form a complete process flow for the manufacturing of integrated circuits. The present invention can be put into practice together with the techniques for manufacturing integrated circuits currently used in the field, and only those process steps being commonly used and necessary for the comprehension of the present invention are included.  
         [0057]     The figures showing cross sections of portions of an integrated circuit during the manufacturing are not drawn to scale but they are instead drawn so as to show the important characteristics of the present invention.  
         [0058]     In particular, the figures show a portion of a semiconductor substrate  1  where memory cells  25  of the memory matrix  2  and the HV transistors  26  of the circuitry  3  are realized, while the portion of a semiconductor substrate  1  where the LV transistors are realized is not shown.  
         [0059]     As shown in  FIG. 7 , on a semiconductor substrate  1  after having defined active areas for the memory matrix  2  and for the circuitry  3 , in the memory matrix  2  a plurality of floating gates  4  of the memory cells is formed each comprising a first gate dielectric layer  5 , called tunnel oxide, a first conductive layer  6 , for example of polysilicon, a second interpoly dielectric layer  7 , which can be an oxide layer or the overlapping of more layers, for example ONO (oxide/nitride/oxide) and a second conductive layer  8 , for example of polysilicon.  
         [0060]     After forming the gates  4 , 9 , the substrate  1  is doped according to known steps to form drain regions  27  and shared source regions  28 . In an embodiment of the invention, as shown in the figures, pairs of adjacent memory cells share the same source region  28 .  
         [0061]     In the circuitry  3  a plurality of gates  9  of the HV transistors is instead formed. Each gate  9  of the HV transistors comprises, for example, a gate dielectric layer  7 ′ and a conductive layer  8 ′ of the circuitry  3 . Advantageously, the gate dielectric layer  7 ′ of the circuitry and the conductive layer  8 ′ of the circuitry  3  are formed, respectively, by the interpoly dielectric layer  7  and by the second conductive layer  8  used in the matrix  2 . After forming each gate  9 , the method continues with doping of the substrate  1  to form source/drain regions  29  of the HV transistors, which may be performed simultaneously with the formation of the drain and source regions  27 ,  28  of the memory cells  25 .  
         [0062]     If the process needs it, all the devices present on the semiconductor substrate  1  are coated by a dielectric film  16  obtained by means of an oxidation step and by a protection dielectric layer  17 , for example formed by means of deposition.  
         [0063]     According to one embodiment of the invention a first coating layer  18  is then formed, for example of nitride, on the whole surface of the semiconductor substrate  1 . This first coating layer  18  acts as “stopping layer” in the etching step of a layer which will be successively deposited.  
         [0064]     Advantageously, the first coating layer  18  covers the gates  4  of the memory cells and of the circuitry  3 , i.e. it does not completely fill the space comprised between pairs of adjacent gates sharing the same source region. However, in an alternative embodiment, this coating layer  18  fills it completely.  
         [0065]     A further dielectric layer  19  is then formed, for example by means of deposition, on the whole semiconductor substrate  1  which will be used for the formation of spacers of the LV transistors of the circuitry  3  and of spacers of the matrix cells  25 .  
         [0066]     If the coating layer does not completely fill the space comprised between pairs of memory cells in correspondence with the shared source region, this further dielectric layer  19 , for example of oxide, fills it completely.  
         [0067]     A second coating layer  20 , for example of nitride, is then formed, for example by means of deposition, which will be used for the formation of differential spacers, those of the HV transistors  26  in the circuitry  3 .  
         [0068]     As shown in  FIG. 8 , a first etching step in plasma blanket of the second coating layer  20  is carried out, selective with respect to the dielectric layer  19 , to form spacers  20   a  and  20   b  on the dielectric layer  19  respectively aligned with the side walls of the gates of the memory cells  25  and of the circuitry transistors.  
         [0069]     These spacers  20   a  are not formed on the side walls of the gates of the memory cells  25  which are aligned with the shared source region  28 . In fact the space between the gates  4  and above the shared source region  28  is completely filled by the dielectric layer  19 .  
         [0070]     As shown in  FIG. 9 , by means of a conventional photo-lithographic technique, a mask  21  for the differential spacers is formed. This mask  21  completely covers the HV transistors  26  of the circuitry  3 .  
         [0071]     As shown in  FIG. 10 , a removal step of the coating layer  20  is then carried out in the areas left exposed by the mask  21  for the differential spacers. During this step the spacers  20   a  are completely removed from the matrix  2  and from the LV transistors of the circuitry  3  which are not covered by the mask  21 , but the spacers  20   b  are left intact.  
         [0072]     The mask  21  for the differential spacers is then removed.  
         [0073]     As shown in  FIG. 11  an etching step in plasma blanket is carried out of the dielectric layer  19  until the first coating layer  18  which covers the gates  4 ,  9  is uncovered. In particular, this etching step is highly selective with respect to the first coating layer  18 .  
         [0074]     With this etching step, short first dielectric spacers  19   a  are formed in the matrix  2  and in the portion of circuitry  3  where the LV transistors are realized, while long second oxide differential spacers  19   b  are formed in the portion of circuitry  3  where the HV transistors  26  are realized. In fact the dielectric layer  19 , in the circuitry  3 , is partially shielded by the spacers  20   b  of the coating layer and thus the oxide layer below these spacers  20   b  is not removed, forming longer spacers  19   b  compared to the spacers  19   a.    
         [0075]     As shown in  FIG. 12  an etching step in plasma blanket is then carried out of the coating layers  18  and of the spacers  20   b , until the dielectric layers  16  and  17  covering the gates  4 ,  9  are uncovered. Such etching leaves spacers  18   a ,  18   b  on the side walls of the gates  4 ,  9  of the memory cells  25  and HV transistors  26 , respectively.  
         [0076]     Dopant implanting then carried out to form HDD implants  30  in circuitry  3  and if necessary in matrix  2 .  
         [0077]     At this point of the process as shown in  FIG. 13 , a pre-silicidation cleaning step is carried out for the removal of dielectric layers  16 ,  17  and the spacers  19   a ,  19   b.    
         [0078]     By means of this step the upper portion of the gates  4  and  9  is uncovered and spacers  18   a  and  18   b  remain uncovered on the side walls of the gates  4  and  9 .  
         [0079]     Thus with the method described above, in matrix coating spacers  18   a  are formed being shorter with respect to the spacers  18   b  formed in circuitry  3 .  
         [0080]     A cobalt silicide layer  31  is finally formed. In particular the silicide layer  31  is formed in the matrix  2  in correspondence with the drain region between one spacer  18   a  and the other.  
         [0081]     The process is completed by means of the deposition of a borderless nitride layer covering the whole structure formed up to this process step, and of the pre-metal dielectric layer so as to insulate the cells of the matrix from one another.  
         [0082]     According to the method described above, the silicide contacts  31  are no more self-aligned with the oxide spacers  15   a  as in the prior art, but they are realized adjacent to the coating spacers  18   a  which are much narrower in the matrix, thus the active area on the basis of the drain region contact is wide enough so as to have a good contact resistance.  
         [0083]     In conclusion, the method allows one to reduce the length of the spacers in matrix so as to reduce the marginality of the drain contact area causing a minimal impact on the source and drain regions of the cell and of the circuitry transistors.  
         [0084]     The process can be advantageously applied for example to memories of the EPROM, EEPROM, flash EEPROM type, but, more in general, it is applied to each type of process with differential spacers, i.e. to all the CMOS processes for advanced applications of the “system on chip” type.  
         [0085]     All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheetare incorporated herein by reference, in their entirety.  
         [0086]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.