Abstract:
A circuit including a first element sampling noise from and discharging noise to a signal line in response to an input signal transitioning on selected edges of a clock signal. A second element samples noise from and discharges noise to the signal line in response to another input signal transitioning on other edges of the clock signal differing from the selected edges of the clock signal such that noise coupled into substrate and supply are independent of the input signal.

Description:
FIELD OF THE INVENTION 
   The present invention relates in general to mixed—signal circuits and methods and in particular to low—noise data conversion circuits and methods and systems using the same. 
   BACKGROUND OF INVENTION 
   Noise and harmonic distortion in mixed-signal circuitry, such as digital to analog and analog to digital converters (DACs and ADCs), comes from a number of sources. For example, the voltages at the summing nodes in some operational amplifier circuits do not completely settle after switching operations, resulting in high frequency noise on the corresponding signal lines. This high frequency noise is then sampled onto the parasitic capacitance within the circuitry and subsequently folded-back into the signal baseband during later switching operations. Unacceptable noise and distortion can also be the result of an inadequate power supply rejection ratio (PSRR) within the various circuits and current “kicks” on the signal lines caused by the switching of unbalanced loads. 
   In noise sensitive applications, including audio processing, the minimization of distortion and noise are critical design factors, since often their ultimate effect is perceptible to the end-user. However, designing to minimize noise and harmonic distortion presents significant challenges, especially when other design factors must be considered, such as circuit complexity, chip area, and power consumption. 
   SUMMARY OF INVENTION 
   The principles of the present invention generally provide noise reduction techniques suitable for applications such as data converters with significant out of band noise and similar circuitry. According to one particular embodiment of these principles, a circuit is disclosed including a first element sampling noise from and discharging noise to a signal line in response to an input signal transitioning on selected edges of a clock signal. A second element samples noise from and discharges noise to the signal line in response to another input signal transitioning on other edges of the clock signal differing from the selected edges of the clock signal such that the sampling and discharging frequency on the signal line is independent on the of the input signal and the other input signal. 
   In another embodiment of the inventive principles, a data conversion element selectively switches a parasitic capacitance to the signal line in response to the input signal. An associated dummy circuit switches a matching parasitic capacitance to the signal line in response to the complement of the input signal. 
   In a further embodiment of the inventive principles, a dummy conversion element selectively switches a parasitic capacitance to the signal line in response to the another input signal. A dummy circuit switches a matching parasitic capacitance to the signal line in response to the complement of the another input signal. 
   By utilizing a dummy conversion element, which switches a matching load to the signal line on clock edges differing from the clock edges timing the switching of the load of the data conversion element to the signal line, the sampling transitions due to parasitic capacitance become independent of the input signal. The mixing of high frequencies on the signal lines due to sampling is more controlled, such that fold back of noise into the signal baseband can be minimized. 
   Switching a parasitic capacitance, matched to the parasitic capacitance of the data conversion element to the signal line in response to the complement of the input signal improves the power supply rejection ratio, lowers the differential “kick” on the signal line, and makes the load on the signal line independent of the input data. A similar technique is advantageously applied to the dummy conversion element using the complement of the other input signal. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a diagram of a typical audio system suitable for describing the utilization of a digital-to-analog converter subsystem (DAC) according to the principles of the present invention; 
       FIG. 2  is an electrical schematic diagram of an exemplary DAC subsystem embodying the principles of the present invention; 
       FIG. 3A  is a more detailed block diagram of the current DAC shown in  FIG. 2 ; 
       FIG. 3B  is a timing diagram of exemplary signals controlling the operation of the current DAC shown in  FIGS. 2 and 3A ; 
       FIG. 4A  is an electrical schematic illustrating in further detail a digital to analog conversion element of the current-based DAC array shown in  FIG. 3A  and associated level—shifting circuitry; 
       FIG. 4B  is an electrical schematic diagram of exemplary control signal generation circuitry suitable for generating the chopping control signals shown in  FIG. 3A ; and 
       FIG. 5  is an electrical schematic diagram of an exemplary dummy element shown in  FIG. 3A . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in  FIGS. 1-5  of the drawings, in which like numbers designate like parts. 
     FIG. 1  is a diagram of a typical audio system  100  suitable for describing the utilization of a digital-to-analog converter subsystem (DAC)  101  according to the principles of the present invention. In this example, DAC subsystem  101  forms part of an audio component  102 , such as a compact disk (CD) player, digital audio tape (DAT) player, or digital versatile disk (DVD) unit. A digital media drive  103  recovers the digital data from the given storage media and passes those data, along with clocks and control signals, to DAC subsystem  101 . The resulting analog (audio) signal undergoes further processing in analog/audio processing block  104  prior to amplification in audio amplification block  105 . Audio amplification block  105  then drives a set of conventional speakers  106   a  and  106   b , or a headset (not shown). 
   Multi-bit digital audio data is received by DAC subsystem  100  serially through the  SDATA  pin timed by the serial clock ( SCLK ) signal. The left and right channel data are alternately processed in response to the left-right clock ( LRCK ) signal, which is normally at the sampling rate. In system  100 , the external master clock ( EMCK ) signal is received by DAC subsystem  101  from digital media drive  103 . 
     FIG. 2  is a block diagram of a digital to analog converter (DAC)  200  embodying the principles of the present invention, and which forms a portion of DAC subsystem  101  of  FIG. 1 . In the illustrated embodiment, DAC  200  receives a channel of digital audio data  AUDIO IN  and outputs an analog audio output signal  ANALOG AUDIO OUT . Although, the illustrated embodiment of DAC  200  is suitable for such applications as digital audio system  100  of  FIG. 1 , its utilization is not limited to audio systems, and therefore DAC  200  may be utilized in a range of systems applications requiring the conversion of digital data into analog form. 
   The digital stream  AUDIO IN  is input into a low voltage current-based (continuous-time) digital to analog converter (IDAC)  201 . The differential outputs of IDAC  201 , after the voltage level shifting discussed further below, drive corresponding inverting (−) and noninverting (+) low voltage inputs of an operational amplifier stage  202 . Operational amplifier  202  also includes differential inverting (−) and non-inverting (+) outputs, with the noninverting (+) output of operational amplifier  202  driving analog output (AOUT) pad  203  through resistor  204 . 
   Operational amplifier  202  operates around an input common mode voltage of approximately one (1) volt. The common mode output voltage for operational amplifier  202  is approximately 4 volts and is controlled by common mode amplifier  205 . The voltage at the inverting (−) input to common mode amplifier  205  is set by a voltage divider formed by resistors  206  and  207  bridging the noninverting (+) and inverting (−) outputs of operational amplifier  202 . The noninverting (+) input to common mode amplifier  205  is tied to the common mode voltage (VCM) reference pad  208 . 
   Differential operational amplifier  202  is associated with two feedback loops, one, which couples the inverting (−) input and the noninverting (+) output of operational amplifier  202 , includes a feedback resistor  209   a  and a feedback capacitor  210   a . The second feedback loop, which couples the noninverting (+) input and the inverting (−) output of operational amplifier  202 , includes a feedback resistor  209   b  and a feedback capacitor  210   b . A level shift generator  211  ensures that an approximately three (3) volt voltage drop exists across resistors  209   a  and  209   b  such that the inputs to operational amplifier  202  remain within a safe operating voltage range, since low voltage differential input transistors are utilized in operational amplifier  202  to save chip area. Generally, a low voltage n-type metal oxide semiconductor [NMOS] transistor has a channel length approximately eight or nine times shorter than that of a high voltage NMOS transistor. Additionally, low voltage MOS transistors typically help reduce total harmonic distortion, since the gate voltage swing is lower, and have better overall noise performance. 
   A clamp transistor  212  at analog output (AOUT) pad  203  clamps the voltage at output pad  203 , in response to the control signal  CLAMP , to reduce glitches when powering—up opamp  202 . The remaining external load presented to analog output (AOUT) pad  203  is represented in  FIG. 2  by filtering resistors  214  and  215  and a filtering capacitor  216 . 
   Isolation transistors  217   c  and  217   d  under the control of regulated gate drive  218  respectively isolate the inverting (−) and noninverting (+) inputs of operational amplifier  202  from output pad (AOUT)  203  during the power down operations. Specifically, isolation transistors  217   c  and  217   d  prevent current flow from external AC coupling cap  213  and thereby prevent the generation of a large voltage spike, and consequently an audible pop, in the signal  ANALOG AUDIO OUT . Pulldown transistors  217   a  and  217   b , also under the control of regulated gate drive  218 , respectively pull the inverting (−) and noninverting (+) inputs of operational amplifier  202  to a known voltage, in the illustrated embodiment to ground, after isolation transistors  217   c  and  217   d  turn-off. 
   Common mode reference generator  219  generates a common mode reference voltage at VCM pad  208  and the noninverting (+) input of common mode amplifier  205 . Common mode reference generator  219  powers down after operational amplifier  202 . During power-down, currents through output (AOUT) pad  203  and VCM pad  208  are controlled by ramp down current generator  220  of  FIG. 2 . 
   Returning to  FIG. 2 , power down of IDAC  202  is controlled by the control  SIGNAL POWER DOWN  IDAC as delayed by delay  222 . The control signal  POWER DOWN REFERENCE , as delayed through delay  223 , controls power-down of bandgap reference  224 , which provides the bias currents to IDAC  201  and operational amplifier  202 . Level shifters  225  and  226  shift the low level control signals  DRIVER POWER DOWN \ and  POWER DOWN VCM \, generated from a low voltage power supply, to the higher levels required by the circuitry of VCM generator  219  and regulated gate drive  218 . To prevent pops in the audio output, the outputs of level shifters  226  and  225  go to a known state and shutdown operational amplifier  202 , if the low voltage supply is removed before the high voltage supply. 
     FIG. 3A  is a block diagram showing an N-element embodiment of IDAC array  201  of  FIG. 2 . In the illustrated embodiment, complementary input data streams DIN and DINB from the quantizer of a delta-sigma modulator are shifted through a set of one-bit shift register (SR) elements  301   a , . . . ,  301 N by the master clock signal  MCK , in which N is an integer index. The output of each shift register element  301   a , . . . ,  301 N drives a corresponding DAC element  301   a , . . . ,  301 N. The resulting overlapping analog output signals drive signal lines  INN  and  INP  to the summing nodes at the inputs of opamp  202  of  FIG. 2 . 
   A second set of dummy one-bit shift register elements  303   a , . . . ,  303 N shift complementary dummy input data streams  DIND  and  DINDB  in response to the  MCK  signal.  FIG. 3B  illustrates a selected number of cycles of the  MCK, DIN  and  DIND  signals for an embodiment where N is equal to eight. Dummy data streams DIND and  DINB  are generated relative to the input data streams  DIN  and  DINB  such that for every rising edge of the  MCK  signal, a corresponding edge (rising or falling) occurs on either input data stream  DIN  or dummy data stream  DIND . The outputs from shift register elements  303   a , . . . ,  303 N drive a corresponding set of dummy conversion elements  304   a , . . . ,  304 N coupled to signal lines  INN  and  INP . Each dummy conversion element  304   a , . . . ,  304 N has a capacitance matched to the capacitance of a corresponding DAC element  302   a , . . . ,  302 N. 
     FIG. 4A  shows one exemplary current DAC element  302   a , . . . , N from IDAC array  201  of  FIGS. 2 and 3A , along with a more detailed electrical schematic diagram of level shifter  211  of  FIG. 2 . 
   The exemplary current element depicted in  FIG. 4A  includes a pair of low voltage PMOS transistors  401   a  and  401   b  respectively biased by the bias voltages  VBP  and  VBPC . In the illustrated embodiment, low voltage PMOS transistors  401   a  and  401   b  are formed in an isolated well of n-type semiconductor (N-well), to minimize substrate noise coupling into IDAC  201 , and save chip area. The current through PMOS transistors  401   a  and  401   b  from the voltage rail Vdda feed the current paths of NMOS transistors  402   a  and  402   b . The gates of NMOS transistors  402   a - 402   b  are respectively driven by corresponding complementary digital data input bits  DIN   x  and  DINB   x  from the outputs of the corresponding shift register element  301   a , . . . , N of  FIG. 3A , in which x is an integer index from 0 to N. The sources of NMOS transistors  402   a  and  402   b  are coupled to the outputs  INN  and  INP  of IDAC  201  of  FIG. 2 . The remaining DAC elements  302   a , . . . , N of IDAC  201  (not shown) are similarly configured and similarly coupled to the outputs  INN  and  INP , which are in turn connected to the inverting (−) and non-inverting (+) summing nodes of operational amplifier  202  of  FIG. 2 . 
   The voltage level shifting operations of voltage level generator  211 , discussed above in conjunction with  FIG. 2 , are implemented by a pair of identical NMOS current source transistors  403   a  and  403   b , biased by the bias voltage  VBN . The current through NMOS current source transistors  403   a  and  403   b  is set, in the illustrated embodiment, to produce a voltage drop of approximately three (3) volts across operational amplifier feedback transistors  209   a  and  209   b  of  FIG. 2 . Any noise in the bias signal  VBN  is advantageously attenuated by the internal common mode feedback loop within operational amplifier  202 . 
   Current source transistors  403   a  and  403   b  operate in conjunction with a pair of NMOS cascode transistors  404   a  and  404   b , biased by the bias voltage  VBNC , and a chopper circuit  405 . Chopper circuit  405  includes a pair of NMOS transistors  406   a  and  406   b  switching in response to the control signal  CHOP  and a pair of NMOS transistors  407   a  and  407   b  operating in response to the complementary control signal  CHOPB.    
     FIG. 4B  illustrates one exemplary circuit suitable for generating the non-overlapping control signals  CHOP  and  CHOPB . In the illustrated embodiment of  FIG. 4B , the chopping control signal  CHOP  and  CHOPB  are generated from a high frequency clock  CHOP   —   CLK  which is generated from the clock driving the digital data being converted. The circuitry of  FIG. 4B  includes an input inverter  408 , a pair of cross-coupled NAND gates  409   a  and  409   b , and a set of inverter/drivers  410   a - 410   d.    
   Current source transistors  403   a  and  403   b  of  FIG. 4A  generate intrinsic low frequency flicker (1/F) noise, which generally has a power spectral density which is inversely proportional to frequency. According to the principles of the present invention, chopping circuitry  405  chops the NMOS current source transistors  403   a  and  403   b  at a high frequency and therefore shifts (modulates) the flicker noise spectrum to much higher out-of-band frequencies. Consequently, the overall noise generated by level shifting circuitry  211  within the signal band of the output signal  ANALOG AUDIO OUT  of  FIG. 2  is reduced. 
   Each DAC element  302   a , . . . ,  302 N of  FIG. 3A  is associated with a corresponding dummy circuit  411 , as shown in  FIG. 4A . In the illustrated embodiment, each dummy circuit  411  includes a PMOS transistor  412 , with the gate shorted to the source, and a pair of NMOS transistors  413   a  and  413   b , having gates controlled by the complementary data bits  DIN   x  and  DINB   x . The sources of NMOS transistors  413   a  and  413   b  are respectively coupled to the signal lines  INP  and  INN  and cross-coupled to the sources of NMOS transistors  402   a  and  402   b  of the corresponding DAC element  302   a , . . . ,  302 N. The parasitic capacitances at nodes n 3  of DAC element  302   a , . . . ,  302 N and n 4  of corresponding dummy circuit  411  of  FIG. 4A  are matched. 
   The dummy element  411  associated with each DAC element  302   a , . . . ,  302 N makes the load on signal lines  INN  and  INP  independent of the corresponding input bits  DIN   x  and  DINB   x , reduces the instantaneous differential current change (“kick”) on signal lines  INN  and  INP , and improves the power supply rejection ratio (PSRR) on the input bits  DIN   x  and  DINB   x . For example, when data bit  DIN   x  is high and the complementary bit  DINB   x  is low, the parasitic capacitance at node n 3  of exemplary DAC element  302   a , . . . , N of  FIG. 4A  is coupled to the  INN  signal line through transistor  402   a  while the matched capacitance at node n 4  of dummy cell  411  is coupled to the INP signal line through transistor  413   a . Consequently, the capacitive load on signal lines  INN  and  INP  is independent of the states of DIN x  and  DINB   x , and the resulting instantaneous differential current change on signal lines  INN  and  INP  is reduced. Furthermore, noise associated with the input bits  DIN   x  and  DINB   x  is coupled to both signal lines  INN  and  INP  by transistors  402   a - 402   b  and  413   a - 413   b  as common mode noise, which is subsequently zeroed—out by the common mode loop internal to opamp  202  of  FIG. 2 . 
     FIG. 5  is an electrical schematic diagram of a representative dummy element  304   a , . . . ,  304 N shown in  FIG. 3A . Each dummy element  304   a , . . . ,  304 N includes a pair of PMOS transistors  501   a  and  501   b  having gates and sources coupled together and to the supply voltage Vdda. The drain of transistor  501   a  is coupled to the drains of a pair of NMOS transistors  502   a  and  502   b  having gates respectively controlled by the dummy data bits  DIND   x  and  DINDB   x  from the corresponding dummy shifter register element  303   a , . . . ,  303 N of  FIG. 3A . The drain of transistor  501   b  is coupled to the drains of NMOS transistors  503   a  and  503   b , which have gates respectively controlled by the dummy bits  DINDB   x  and  DIND   x . The sources of transistors  502   a  and  502   b  are then cross-coupled with the sources of transistors  503   a  and  503   b  and the signal lines  INN  and  INP . The parasitic capacitance at nodes n 5  and n 6  match the capacitance at nodes n 3  and n 4  of a corresponding DAC element  302   a , . . . , N, of  FIG. 4A . 
   Returning to  FIG. 2 , in the illustrated embodiment of digital to analog converter  200 , the voltages at the inverting (−) and noninverting (+) inputs of operational amplifier  202  do not completely settle during data conversion operations. Chopping circuitry  405  of  FIG. 4A  is disposed between NMOS current source transistors  403   a  and  403   b  and NMOS cascode transistors  404   a  and  404   b . The gain of cascode transistors  404   a  and  404   b  advantageously reduces the effects of the non-settled voltage at the inverting and non-inverting inputs of operations amplifier  202  during charging and discharging of the parasitic capacitance at the chopping nodes n 1  and n 2  of  FIG. 4A . As a result, the process of chopping the flicker noise generated by NMOS current source transistors  403   a  and  403   b  is independent of the non-settled voltage at the  INN  and  INP  nodes. 
   In the illustrated embodiment, the data bits  DIN   x  and  DINB   x  output from each shift register  301   a , . . . ,  301 N of  FIG. 3A  overlap to ensure that transistors  402   a  and  402   b  shown in  FIG. 4A  for DAC elements  302   a , . . . ,  302 N do not simultaneously turn-off and thereby cause a glitch on the  INN  and  INP  data lines and the inputs of opamp  202  of  FIG. 2 . Instead, during the overlap period of bits  DIN   x  and  DINB   x , both transistors  402   a  and  402   b  turn-on, which results in a short between the sources of transistors  402   a - 402   b  in  FIG. 4A . Specifically, since the voltages at the inputs to opamp  202  of  FIG. 2  do not settle completely, the remaining voltage between  INN  and  INP  is sampled onto the parasitic capacitance on nodes n 3  and n 4 . Subsequently, on the following rising edges of bits  DIN   x  and  DINB   x , the high frequency noise stored on nodes n 3  and n 4  are mixed through transistors  402   a  and  402   b  on to the signal lines  INN  and  INP , as noise and distortion folding into the audio signal baseband. 
   According to the principles of the present invention, overlapping dummy bits  DIND   x  and  DINDB   x  of  FIG. 5 , generated from dummy data streams  DIND  and  DINDB  of  FIGS. 3A and 3B , ensure that, for each DAC element  302   a , . . . ,  302 N which does not switch for a given rising edge of the  MCK  signal, the corresponding dummy element  304   a , . . . ,  304 N does switch, and vice-versa. For that dummy element  304   a , . . . ,  304 N, the parasitic capacitances at nodes n 5  and n 6 , shown in  FIG. 5 , are impressed with the time-dependent signal. During the subsequent transitions of  DIND   x  and  DINDB   x , the signal impressed on the capacitances of nodes n 5  and n 6  are transferred to the  INN  and  INP  signal lines through transistors  503   a - 503   b  and  502   a - 502   b , depending on the polarity of  DIND   x  and  DINDB   x . During the overlap period of bits DIND x  and DINDB x , both transistors  502   a - 502   b  turn on, which results in a short between the sources of transistors  502   a - 502   b . This results in a charge transfer between INN and INP data lines. 
   Overall, the total contribution of noise and distortion on signal lines  INN  and  INP  becomes dependent on the  MCK  signal rather than on the data signals  DIN  and  DINB . In the illustrated embodiment, the noise transfer function of delta—sigma modulator  305  is then designed to have a minimum noise floor with respect to the known frequency of the  MCK  signal such that the mixing of high frequencies on the signal lines is more controlled and the fold back of noise into the signal baseband can be minimized. 
   While a particular embodiment of the invention has been shown and described, changes and modifications may be made therein without departing from the invention in its broader aspects, and, therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of the invention.