Abstract:
A wideband low noise amplifier (LNA) includes a correction circuit added to compensate for third order intermodulations. A version of the third order nonlinearities created in the main LNA is created in an auxiliary, low power scaled version of the LNA, phased appropriately using a current mirror, and subtracted from the main signal path by summing, thus providing a cancellation of the third order intermodulation (IM) terms in the main signal path leaving a signal remaining which is significantly more spectrally pure than the signal produced by the LNA before correction.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority from U.S. Provisional Patent Application No. 60/837,818 filed Aug. 15, 2006. 
     
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to the field of signal amplifiers. More particularly, this invention relates to the field of single-ended high dynamic range amplifiers having distortion nulling. 
         [0004]    2. Description of Related Art 
         [0005]    There is a need in the industry for extending the dynamic range of existing low noise amplifier (LNA) architectures without degrading the noise figure (NF) or increasing the direct current (DC) power consumption. The existing LNA topologies&#39; dynamic range is constrained by the physical limitations of the particular topology. The fine line, submicron geometries of present day integrated circuit (IC) processes allow circuit designers to take advantage of the available bandwidth of these technologies to resultantly create new novel circuit solutions at radio frequency (RF) frequencies, that were previously not feasible as a result of device F T s, and allow the possibility for enhancing the performance of the existing topologies. 
       SUMMARY OF THE INVENTION 
       [0006]    According to the present invention, a version of the third order nonlinearities created in the main LNA is first created in an auxiliary scaled version of the LNA, then phased appropriately and subtracted from the main signal path by summing, thus providing a cancellation of the third order intermodulation (IM) terms in the main signal path leaving a spectrally pure signal remaining. This allows the LNA to extend the existing achievable dynamic range. Additionally, the scaled version of the LNA contributes minimally to the NF of the uncorrected LNA. The scaled version of the LNA dissipates only a small fraction of the DC power dissipated in the main LNA. Thus, the overall dynamic range of the LNA is extended without impacting other nominal performance parameters for the circuit. 
         [0007]    Several different embodiments of LNA circuits that implement the single ended intermodulation distortion nulling of the present invention are disclosed. In each embodiment the circuit is composed of a main amplifier stage and an IM cancellation stage. 
         [0008]    The first and second embodiments apply the distortion nulling of the present invention to wideband amplifiers having common source (or common emitter) architectures. The first embodiment incorporates NPN bipolar transistors in a common emitter arrangement. The second embodiment uses CMOS transistors in a common source arrangement. Both designs are single ended amplifiers customized for low noise performance. The IM cancellation circuit in both designs will produce and inject an in-phase signal into the main amplifier. This signal current of the auxiliary LNA will have low level fundamental tones, but will have third order terms which should be in the same order of magnitude as the main amplifier stage. This summation of the main signal current and the injected signal current will produce a subtraction of IM terms which will result in improved intermodulation distortion. This will be accomplished without a significant reduction in the main signal current. Also, there will not be a significant increase in the overall noise performance or DC power consumption. 
         [0009]    Additional embodiments apply the distortion nulling concept to tuned amplifiers, and to common gate (or common base) tuned amplifiers. 
         [0010]    Exemplary embodiments of the invention will be further described below with reference to the drawings, in which like numbers refer to like parts. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a prior art NPN/BiCMOS LNA; 
           [0012]      FIG. 2  is a prior art CMOS LNA; 
           [0013]      FIG. 3  is block diagram of the distortion nulling concept according to the present invention; 
           [0014]      FIG. 4  is a NPN/BiCMOS LNA with distortion nulling according to the present invention; 
           [0015]      FIG. 5  is a CMOS LNA with distortion nulling according to the present invention; 
           [0016]      FIG. 6  is a plot of a simulation result showing the performance of the prior art CMOS LNA of  FIG. 2 ; 
           [0017]      FIG. 7  is a plot of a simulation result showing the performance of the CMOS LNA of  FIG. 5  according to the present invention; 
           [0018]      FIG. 8  is a prior art tuned CMOS LNA; 
           [0019]      FIG. 9  is a tuned CMOS LNA with distortion nulling according to the present invention; 
           [0020]      FIG. 10  is a prior art common gate CMOS LNA; 
           [0021]      FIG. 11  is a common gate CMOS LNA with distortion nulling according to the present invention; 
           [0022]      FIG. 12  is a prior art inductively degenerated bipolar LNA; 
           [0023]      FIG. 13  is a schematic of a tuned bipolar LNA with distortion nulling and process variation compensation according to the present invention; 
           [0024]      FIG. 14  is a plot of a simulation result of the circuit of  FIG. 13 , showing before and after trim current for a nominal process; 
           [0025]      FIG. 15  is a plot of a simulation result of the circuit of  FIG. 13  showing OIP 3  versus DAC 1  trim current for a slow process; and 
           [0026]      FIG. 16  is a simulation result showing the noise figure for a nominal process for the circuit of  FIG. 13 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0027]    Intermodulation (IM) is a result of extra product terms produced from the main amplifier signal. For example, when a signal having frequency components f 1  and f 2  is applied to an amplifier, undesired product terms such as  2   f   1 ,  2   f   2 , f 1 +f 2  are produced. These product terms degrade the quality of the signal being amplified. This degradation is referred to as intermodulation distortion, and is related to the single tone third harmonic and the DC third order nonlinearity of the device. The most important products to consider when analyzing third order intermodulation distortion are the products located at  2   f   1 -f 2  and  2   f   2 -f 1 . These terms are the most important since they are the closest to the fundamental tones (f 1 , f 2 ). The IM cancellation circuits of the present invention decrease the IM tones at frequencies  2   f   1 -f 2  and  2   f   2 -f 1 , essentially nulling these terms out in the main signal path. In a recent publication entitled “A +10 dBm IIP3 SiGe Mixer With IM3 Cancellation Technique”, by S. Otaka, M. Ashida, M. Ishii, and T. Itakura, IEEE Journal of Solid State Circuits, Vol. 39, No. 12, December 2004, IM cancellation purportedly was achieved in bipolar differential circuits. However, in designs with ultra low noise performance, such as LNAs that interface to antennas or channel select filters for receivers, single ended amplifiers are preferred in order to achieve the lowest possible input noise. The consequence of using a single ended amplifier is that differential IM cancellation techniques cannot be used to improve distortion. The differential cancellation approach, when applied to a single-ended topology requires single-ended to differential conversion. The resultant architecture causes significant gain errors in the process, does not track well over process and temperature, and thus the error correction is not very effective. Single ended IM cancellation circuits are disclosed herein in order to improve distortion while maintaining low input noise and low DC power. 
         [0028]    I. Wideband Amplifiers 
         [0029]    Prior art bipolar/BiCMOS LNA and CMOS LNA amplifiers shown in  FIGS. 1 and 2 , respectively. For existing LNA topologies, the two tone IM distortion can be shown to be related to the DC third order nonlinearity of the device. For the example of an NPN LNA in  FIG. 1 , the third order nonlinearity of a bipolar device can be described classically using a Taylor series expansion of the I-V characteristic. The third order nonlinear signal current for the bipolar device is: 
         [0000]        I   NL3 =( G   M )( V   T )/(Δ i/I ) 3    
         [0030]    where
       G M  is the transconductance of the device=I/V T ,   V T  is the thermal voltage for the device,   Δi is the signal current in the device, and   I is the DC bias current in the device.       
 
         [0035]    Based on the above equations, for a given output signal current, the only way to reduce the third order nonlinearities&#39; contribution to the output signal is to increase the DC current I. This would cause an increase in DC power consumption, and therefore is not a desirable solution to the problem. 
         [0036]    The concept of distortion nulling, which reduces the third order nonlinearities&#39; contribution to the output signal without significantly increasing the DC current draw of the circuit, is presented in  FIG. 3 . The main amplifier, which is the prior art, generates a main signal current Δi and a third order nonlinear current I NL3a , as described above. A novel correction circuit, which is added to the existing LNA according to the present invention, produces a scaled version of the main signal current kΔi, and a third order nonlinear current I NL3b  which is on the order of the nonlinear current in the main amplifier. The signal and nonlinear currents in the correction circuit are then directed through a current mirror circuit to be properly phased, and the output current of the mirror is then summed together with the currents in the main signal path. The resultant output current terms are: 
         [0000]      Δ i   signal   =Δi−kΔi =(1 −k )Δ i  where k is very small (&lt;0.1-0.2) 
         [0000]    
       
      
       I 
       NL3(signal) 
       =I 
       NL3a 
       −I 
       NL3b  
      
     
         [0037]    Now, if the correction circuit is designed properly, the two nonlinear currents can be made close in magnitude and phase, such that an improvement in IM distortion by a factor of 2-10 is possible. A further challenge is to ensure that the correction circuit will work over process variations and temperature. It is also possible to have digitally programmable currents in the LNA to allow the current in the LNA to change as a function of process variations, and then these current settings would be required to work over the full temperature range for a given process variation. 
         [0038]    A. Common Emitter (Bipolar/BiCMOS) Configuration 
         [0039]      FIG. 4  illustrates a series-shunt feedback bipolar LNA, with IM correction circuitry used to implement the distortion nulling concept. This type of amplifier architecture is designed for a wideband match. This means that the input and output resistances are equal to approximately 50Ω over a wide range of frequencies. The input signal is applied to Q 7  and is buffered to Q 1 . From Q 7  to Q 1  there is unity voltage gain. Q 7  provides an isolation stage between the input terminal and the base current of the output stage transistor Q 1 . Q 1  and Q 7  need to be large area devices in order to achieve a low base resistance which results in lower input noise. The large area for Q 1  introduces a large capacitance which can limit the output bandwidth of Q 1 . This capacitance is referred to as the Miller capacitance. In order to reduce the Miller effect and achieve high bandwidth, Q 2  is connected above Q 1 . This configuration is referred to as cascode transistor. Emitter follower Q 6  is provided to better isolate the feedback network from the output load resistor. R 9  and C 1 , along with the gain of the amplifier, set the input and output resistance of this amplifier. This type of amplifier can be designed to have equal output and input resistances. A small value degeneration resistance R 1  is applied in order to achieve linearity for the main amplifier stage. The addition of R 1  allows for higher linearity since there is less VBE modulation across Q 1 . I 2  is trickling current provided to give more voltage headroom for Q 2 , while reducing the distortion created in Q 1  by increasing the current in that transistor. For the IM correction stage, Q 3  taps off the base of Q 1 . The signal voltage at the base of Q 1  generates signal current in Q 3 . This signal current is then pushed into Q 5 . Transistors Q 5  and Q 4  form a current mirror. Since Q 5  is a diode connected transistor, the signal and the DC current in Q 5  creates an equal VBE voltage across the two transistors Q 5  and Q 4 . This VBE voltage will force Q 4  to pull a current, equal to Q 5 &#39;s, from the Q 1 , Q 2  connection. The mirror circuit of Q 4  and Q 5  provide a phase inversion for the signal and nonlinear currents created in Q 3 . This allows the correct signal currents to be summed into the Q 1 , Q 2  connection. It is at this sum node where the signal current from the main amplifier stage and the signal current generated by the current mirror get summed. The summation of these signal currents produces a subtraction of nonlinear IM terms. It is particularly advantageous to sum the signals from the main stage and the IM cancellation stage at the connection between Q 1  and Q 2  since there is a small voltage swing at this intersection. There is a small voltage swing there as a result of the effective resistance at the intersection of Q 1  and Q 2 . In order to achieve optimal IM cancellation, I 3 , the current in transistor Q 3 , and R 2  have to be calculated in terms of I 1  and R 1 , and the small signal parameters of both stages. The analysis of calculating R 2  and I 3 , the current in transistor Q 3 , is shown below. As described previously, we want the I NL3a  nonlinear term of the main amplifier stage to be equal to the I NL3b  nonlinear term of the cancellation circuit in order to null the third order nonlinear terms. Since the bipolar LNA requires local degeneration in order for the cancellation to work properly, the G M  transconductance of the main and correction LNAs must be calculated taking this into account: 
         [0000]        G   M1   ′=G   M1 /(1+ G   M1   *R   1 ), G   M2   ′=G   M2 /(1 +G   M2   *R   2 ) 
         [0040]    We want the I NL3a  nonlinear term of the main amplifier stage to be equal to the I NL3b  nonlinear term of the cancellation circuit. Thus, for IM cancellation we want: 
         [0000]      ( G   M1 ′)( V   T )(Δ i   1   /I   1 ) 3 =( G   M2 ′)( V   T )(Δ i   2   /I   3 ) 5    
         [0041]    where
       G M1  is the transconductance of the main bipolar device=I 1 /V T ,   G M2  is the transconductance of the correction bipolar device=I 3 /V T ,   Δi 1  is the signal current in the main bipolar device=G M1 ′Δv IN ,   Δi 2  is the signal current in the correction bipolar device=G M2 ′Δv IN ,   I 1  is the DC bias current in the main bipolar device Q 1 , and   I 3  is the DC bias current in the correction bipolar device Q 3 .       
 
         [0048]    Now, using these definitions, and simplifying the equality: 
         [0000]      ( G   M1 ′)( G   M1   ′/I   1 ) 3 =( G   M2 ′)( G   M2   ′/I   3 ) 3    
         [0049]    Substituting for G M1 ′ and G M2 ′ and rearranging: 
         [0000]      [ G   M1 /(1 +G   M1   *R   1 )] 4 /( I   1 ) 3   =[G   M2 /(1 +G   M2   *R   2 )] 4 /( I   3)   3    
         [0000]      But: 
         [0000]        G   M1   =I   1   /V   T  and 
         [0000]    
       
      
       G 
       M2 
       =I 
       3 
       /V 
       T  
      
     
         [0050]    so these relationships allow further simplification: 
         [0000]        I   1 /(1+ G   M1   *R   1 ) 4   =I   3 /(1+ G   M2   *R   2 ) 4    
         [0051]    Now, I 1  and R 1  are set in the main amplifier design (i.e., the prior art). These values provide a base line distortion performance for the LNA. The variables for design are I 3  and R 2  and their values are limited to the constraints of the equation above. In  FIG. 4 , the applied DC voltage at the base of the main amplifier transistor Q 1  is the same voltage applied to the transistor Q 3  in the correction circuit. The collector current I 3  can be determined and this will allow the value of R 2  to be calculated as shown in the equation below, based on the above equation: 
         [0000]        R   2 =( I   3   /I   1 ) 1/4 *[(1 +G   M1   *R   1 )−1]/( G   M2 ) 
         [0052]    Now, based on the values of I 2  and R 2 , the biasing of transistor Q 3  in the correction circuit does not set up properly. This is because the DC base voltage for Q 3  is fixed by the main LNA bias network. However, using the calculated value for R 2  in the circuit causes the DC current I 2  to be incorrect as a result of the applied DC bias voltage. Thus, an offset current source is required to be summed at the emitter of Q 3 . Summing in this current allows the correct value for R 2  and the proper current I 3  for the transistor Q 3  to be realized. R 6  in  FIG. 4  provides this offset current such that Q 3  has the correct DC current. Another way to provide for the proper biasing in the correction network is to have a separate bias network for the correction circuit transistor Q 3 , and AC couple the input signal to the correction network. An example of this implementation concept is shown for the CMOS LNA in  FIG. 5 . 
         [0053]    B. Common Source (CMOS) Configuration 
         [0054]      FIG. 5  illustrates a CMOS cascode amplifier with R 4  and C 1  in the feedback path. It should be noted here that there are many ways to implement the concept shown in  FIG. 3 , and  FIG. 4  and  FIG. 5  are only two such ways. This would be recognized by someone skilled in the art. Similar to the NPN LNA of  FIG. 4 , the CMOS LNA of  FIG. 5  is a wideband match. The input and output resistances can be obtained by dividing R 4  by the gain of the amplifier stage. This CMOS LNA uses a cascode configuration in order to achieve high output bandwidth and remove the channel length modulation effect on the main transistor M 1 . M 2  is provided to remove the Miller effect and allow for large output bandwidth. R 2  and R 3  provide cascode device M 2  with a gate bias voltage. In this configuration, the correction stage is composed of both NMOS and PMOS devices. Such use of both n and p type devices could not be implemented in the NPN LNA since typically PNP transistors exhibit low operating frequency range and poor current gain (Beta). However, if high frequency PNPs are available, then they could be used equivalently in the bipolar LNA. Also, care must be taken if PMOS devices are used in the mirror for the IM correction stage in the NPN LNA since PMOS transistors exhibit higher 1/f noise than bipolar transistors. The IM cancellation circuit starts with M 3  tapping off the gate of M 1  through an AC coupling capacitor C 2 . In this implementation, as described earlier, M 3  has its own bias network. This allows the input signal to be coupled to the correction transistor M 3 , to generate the signal current, but does not force VGS of M 3  to be the same as M 1 . Thus, the proper bias and aspect ratio (W/L) for M 3  can be created in order to create the correct IM nonlinear terms. For the CMOS LNA, degeneration resistance is not required to generate the correction currents. Therefore, offset current sources cannot be used. This, then, puts too many constraints on the bias and aspect ratio of M 3 , thereby requiring it to have its own bias network. The signal current created by M 3  is pulled down from M 4  and creates a VGS across M 4  and M 5  in the mirror circuit created by M 4  and M 5 . This VGS will force M 5  to push the same signal current into the connection between M 1  and M 2 . Again, the mirror circuit takes the signal and nonlinear currents from M 3  and creates the proper phase for them to be summed into M 1 /M 2 . It should be noted that although the mirror is implemented using PMOS transistors, it can also be implemented with NMOS devices. The aspect ratio of the devices M 4  and M 5  must be sized properly so that the parasitic capacitance of the mirror does not affect the IM nonlinear current term created in M 3 . If it does, then the distortion nulling is not as effective, due to the added nonlinear current term created. Thus, the signal current generated by the correction stage gets summed with the signal current in the amplifier stage. Since the signal current generated by the IM cancellation circuit is out of phase with the signal current in M 1 , the result is the IM terms get subtracted from one another. Hence the circuit exhibits improved intermodulation distortion, which means that the amplifier has resultantly lower distortion. In order to calculate the aspect ratio and the current needed in M 3 , a Taylor series expansion of the MOS I-V characteristic must be performed. The detailed analysis is presented in “Frequency-Dependent Harmonic-Distortion Analysis of a Linearized Cross-Coupled CMOS OTA and its Application to OTA Filters” by J. Chen, E. Sanchez-Sinencio, and J. Silva-Martinez, IEEE Transactions on Circuits and Systems—I Regular Papers, Vol. 53, No. 3, March 2006. The results are summarized as follows for a single MOS device: 
         [0000]        I   NL3 =( G   M )(Δ v )/8( V   DSAT   2 ) 
         [0055]    where
       G M  is the transconductance of the device=2(βI) 1/2      β=(μ N )(C OX )(W/L) for the MOS device   Δv is the signal voltage at the gate-source of the device   I is the DC bias current in the device   V DSAT  is the saturation voltage for the MOS device   V DSAT =V GS −V TH          
 
         [0062]    where V GS  is the DC gate-source voltage of the device, and V TH  is the threshold voltage of the device. Equivalently, V DSAT  can be written as: 
         [0000]    
       
      
       V 
       DSAT 
       =V 
       GS 
       −V 
       TH  
      
     
         [0000]    
       
      
       V 
       DSAT 
       =I/β 
      
     
         [0063]    Now, in order for the third order nonlinearity in M 1  to be equal and opposite to the nonlinear term in M 3 , the third order nonlinear signal currents must be the same: 
         [0000]      ( G   M1 )(Δ v   3 )/8( V   DSAT1   2 )=( G   M2 )(Δ v   3 )/8( V   DSAT   2 ) 
         [0064]    Substituting in for the expression above, and canceling like terms, this simplifies to: 
         [0000]      [( W   2   /L   2 )/( W   1   /L   1 )] 3 =( I   2   /I   1 ) 
         [0065]    Again, as with the bipolar LNA, (W 1 /L 1 ) and I 1  are fixed for the prior art design. If one DC bias were used, then M 3  cannot be designed properly, so a separate bias is used for transistors M 1  and M 3 . Thus, once (W 2 /L 2 ) is chosen, the equation above can be used to determine the correct DC bias current I 2  for M 3  in order to provide the correct nonlinear signal current to cancel the nonlinear IM current created in the main amplifier. 
         [0066]    As an example of the effectiveness of the distortion nulling, simulations have been performed for the CMOS LNA topology shown in  FIG. 5 , using the design equations presented. The two tone IMDs for input frequencies of 1.0 GHz and 1.1 GHz for the prior art base line LNA in  FIG. 2  are shown in  FIG. 6 . The P OUT  of the fundamental tone is −13.5 dBm and the third order IM term is −91.8 dBm. In order to determine the output third order intercept for the LNA, the following equation is used: 
         [0000]        OIP 3=[ P   OUT +( SFDR/ 2)] dBm    
         [0000]    where P OUT  is the output power of each of the two tones and SFDR is the spur free dynamic range for the LNA, or the Δ (in dB) between the fundamental tone and a neighboring IM term. Using the above expression, the OIP 3  can be calculated to be 25.65 dBm for the base line, prior art LNA. A simulation result for the distortion nulling concept, implemented in  FIG. 5 , is shown in  FIG. 7 . From  FIG. 7 , the improved OIP 3  is calculated to be 31.95 dBm, thus showing an improvement of 13.8 dB in SFDR over the existing prior art LNA. From the figure, as pointed out earlier, it can be seen that the power of the fundamental has been reduced by 0.6 dB, as a result of the fact that some of the main signal current is reduced as a result of the correction. This reduction in signal current is very small, relative to the benefits of the improved distortion performance. 
         [0067]    The sensitivity of the effectiveness of the distortion nulling was investigated over process variations and temperature. Table 1 below summarizes the performance of the CMOS LNA of  FIG. 5  at 1.0 GHz. 
         [0000]    
       
         
               
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                 Temperature 
                 Prior Art OIP3 
                 With Distortion Nulling 
               
               
                 Process 
                 (° C.) 
                 (dBm) 
                 (dBm) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Nominal 
                 20 
                 25.65 
                 31.95 
               
               
                 Nominal 
                 80 
                 24.66 
                 28.6 
               
               
                 Slow 
                 80 
                 25.3 
                 27.8 
               
               
                   
               
             
          
         
       
     
         [0068]    Although it can be seen from Table 1 above that the error correction network for the distortion nulling is sensitive to process and temperature, the performance of the correction over process and temperature is still superior to the performance of the prior art for all conditions. As described previously, it is possible to maintain performance over process using digital calibration techniques in the correction stage. This allows the IM current cancellation to be maintained independent of process variations. Additional impacts of the distortion nulling correction circuit which should be considered include how well the correction holds up over frequency. With regards to device mismatches, the signal devices used in the main and correction circuits should be interleaved when routed in the layout. This will minimize the effect of device mismatch and resultant offset between the signal transistors in the main and correction circuits. With respect to frequency, any error correction circuit has finite bandwidth limitations, beyond which the correction network actually degrades the prior art performance. In other words, there is a point in frequency at which the LNA IM performance is better without error correction than with it. This is a result of phase shifts in the correction network. For many of the frequency ranges of interest for present radio applications, however, error correction can be taken advantage of to improve the overall LNA performance. 
         [0069]    Thus, a distortion nulling concept has been developed, verified mathematically, and implemented. The concept can be applied to any process technology. It has been shown to be robust to temperature and process variations. It provides a solution to extend the dynamic range of future receivers without degrading the front end NF or DC power consumption. 
         [0070]    II. Tuned Amplifiers 
         [0071]    A. Tuned CMOS Amplifiers 
         [0072]    The distortion nulling concept has been applied above to broadband amplifiers in the common source (emitter) configuration. The concept works equally as well for tuned amplifier designs. The application to tuned amplifier designs will be illustrate with reference to common base or common gate tuned LNAs. 
         [0073]      FIG. 8  shows a prior art CMOS tuned amplifier. This is a common source LNA that uses inductive degeneration, an inductive input match, and an output inductive load that also acts as a DC choke. There are several advantages of this design approach. The first is dynamic range. The output load brings the drain connection of the cascode device to the rail, increasing both the DC and dynamic VDS of the device. This extra headroom allows for the consideration of potentially not needing a trickle current source, as is required in the broadband design. Additionally, the inductor in the source allows for degeneration impedance on the noise sources of the main transistor at the frequencies of interest, without the noise penalty of a real resistor. Also, there is no loss of DC headroom for use of this inductor. The inductor on the gate allows for a 50Ω impedance match at the frequency band of interest without the need for feedback, as is the case for the broadband design. Thus, there are many benefits of a tuned LNA design. One of the most important features is the noise figure (NF) achievable with a tuned LNA design. The drawback is that the gain response is a band-pass function, and all of the LNA parameters are “tuned” for a fairly narrow frequency band of interest, as opposed to the broadband design. Depending on the application, therefore, there may be a benefit to using one LNA topology over another. 
         [0074]      FIG. 9  shows a tuned amplifier provided with distortion nulling according to the present invention. The equations for the distortion correction network are the same as those developed for the broadband CMOS LNA. 
         [0075]    Simulations have been performed on the prior art and the new corrected LNA to verify the performance. The design was tuned for a 2 GHz center frequency. At 2 GHz, the two tone OIP 3  was simulated to be +21.1 dBm for the prior art LNA. For the corrected LNA, the OIP 3  was simulated to be 26.1 dBm, producing a 10 dB increase in dynamic range for the intermodulation distortion products of the LNA. The NF at 2 GHz degraded slightly as a result of the added error correction, but this can be further improved by adding inductive degeneration in the correction network. 
         [0076]    The concept of distortion nulling can be applied equally to a common gate (base) configuration as well as the common source (emitter) configuration. The prior art for this concept is shown in  FIG. 10  for the broadband common gate configuration. Those skilled in the art can easily extend the concept to common base. In  FIG. 10 , the common gate amplifier can be designed in several ways. The input impedance can be set by the impedance looking into the source, or it can be set by a resistor, with the resultant source impedance of the transistor being very low impedance relative to the resistor value. Thus, the Z 1  in the prior art can either be a resistor or a capacitor, depending on how the input impedance is set. 
         [0077]    Now, in  FIG. 10 , with an applied input voltage, there is a nonlinear voltage generated at the source of the common gate transistor as result of the device nonlinearity. Thus, assuming Z 1  is a resistor R 1 , the resulting signal current into the source of the device can be written as: 
         [0000]      Δ i   IN =( V   IN   −V   NL3a )/ R   1    
         [0078]    where V NL3a  is the third order nonlinearity of the NMOS device. 
         [0079]    Using the previous expression for I NL3a , we can determine V NL3a : 
         [0000]        I   NL3a =( G   M1 )(Δ v   3 )/8( V   DSAT1   2 ) 
         [0000]        I   NL3a =( G   M1 )( V   NL3a ) 
         [0000]      Therefore: 
         [0000]        V   NL3a =(Δ v   3 )/8( V   DSAT1   2 ) 
         [0080]      FIG. 11  is a schematic diagram showing the distortion nulling of the present invention applied to the common gate CMOS LNA. In the figure, for the correction network, if Z 2  is a resistor of value R 2 , then in order for the correction network to work, it would require the following relationship: 
         [0000]    
       
      
       V 
       NL3a 
       /R 
       1 
       =V 
       NL3b 
       /R 
       2  
      
     
         [0000]      and 
         [0000]        V   NL3b =(Δ v   3 )/8( V   DSAT2   2 ) 
         [0000]      Using the relationship 
         [0000]      ( V   DSAT ) 2   =I/β   
         [0000]    we can simplify the equality to 
         [0000]      ( W   1   /L   1 )/( I   1   R   1 )=( W   2   /L   2 )/( I   2   R   2 ). 
         [0081]    The values for (W 1 /L 1 ), I 1 , and R 1  are already set in the prior art design. Thus, there is freedom to determine (W 2 /L 2 ), I 2 , and R 2  in the correction circuit. R 2  is determined by the amount of signal loss that will occur. Typically, as described earlier, that will be a few tenths of a dB. The prior art should have a (W 1 /L 1 ) that is a multiple of the (W 2 /L 2 ) for the correction circuit, created by using multiple parallel devices, each with an aspect ratio of (W 2 /L 2 ). This will allow for the best tracking between main and auxiliary devices. This will then determine what I 2  is in order for the correction to work. This concept will also work for tuned common gate designs. This is well known by those skilled in the art, and it is a straight-forward procedure to apply the analysis to a tuned common gate LNA design, as was developed above for the common source amplifier. 
         [0082]    B. Tuned Bipolar Amplifiers 
         [0083]    In CMOS LNA applications, the transconductance of the device is low. This means that very large resistive degeneration is needed in order to improve the IP 3  of the LNA. However a large resistive degeneration leads to a high noise figure (NF). For bipolar LNA&#39;s, the transconductance is much larger than the CMOS example. Hence, small values of resistive degeneration can be used to extend IP 3  of the LNA without severely degrading the NF. Resultantly, a limitation of resistively degenerated bipolar LNA is the NF possible for a given IP 3 . The resistive degeneration generates Johnson noise which contributes to the overall NF. In some applications low NF (e.g., &lt;2 dB) is desirable, which calls for a low value for degeneration, or no degeneration at all. Resultantly, a smaller degeneration resistor results in lower IP 3  which can be fixed by increasing the DC power in the amplifier thereby increasing IP 3 . Increasing the DC power is undesirable for low power, low noise applications. 
         [0084]    Another possibility, shown in  FIG. 12 , is to increase the degeneration to achieve higher IP 3  and not sacrifice NF. The inductively degenerated bipolar LNA shown in the figure allows the noise to be low since the degeneration resistor is replaced with an inductor. Q 1  and Q 2  form the cascoded Common Emitter amplifier stage. L 1  is the inductive emitter degeneration that has a real and imaginary resistance at the frequency of interest. At the frequency of interest, the magnitude of the inductance provides a noiseless degeneration for the transistor, which allow for higher IP 3  without the DC power and noise penalty. L 2  is provided to cancel the imaginary part of the input impedance created by L 1 . L 3 , C 1 , and R 1  provide a resonance load at the frequency of interest. Q 6  establishes a DC bias voltage for Q 1 . The input/output impedance is designed to be 50 ohms at a specified frequency. The architecture allows the noise to be very low at the expense of sacrificing dynamic range. The reason for this is without resistive degeneration the noise source is eliminated but the bipolar device is inherently nonlinear. By adding an inductor at the emitter of Q 1 , the magnitude of the impedance provides a noiseless degeneration at resonance. Although the noise is low for this tuned LNA, it would be desirable to improve the IP 3  without increasing the DC power. 
         [0085]    Thus, this is the motivation for the extension of the single ended distortion nulling concept to the tuned bipolar LNA shown in  FIG. 13 . The ideal way the correction stage would function would be to use a scaled version of the main inductor (L 1 ) in the correction network. This would be an impractical solution for several reasons. One reason is since the correction stage is a scaled low power version of the main stage, the inductance needed in the correction stage would be an order of magnitude larger than L 1 . This inductance value would have a resonant frequency that is much lower in frequency than the resonant frequency of the main inductor L 1 . Hence, the solution is to use multiples of L 1  to create the inductor in the correction stage. This is not practical either. Thus, the practical solution is to use a resistor in the correction stage and deal with the resulting issues, which are addressed in the text. As in  FIG. 12 , Q 1  and Q 2  form the cascode amplifier. L 1  is the inductive degeneration; L 2  cancels the imaginary part of the resistance created by L 1 . M 1  and M 2  are PFET current sources for the main and correction stage of the amplifier. Transistors Q 3 , Q 4 , and Q 5  form the cancellation circuit used to cancel the IM terms created by Q 1 . It should be noted that Q 4  and Q 5  which form the mirror in the correction stage, must have a signal bandwidth on the order of the input signal bandwidth. If Q 4  and Q 5  have small bandwidths the phase of the correction stage will not be 180 degrees out of phase from the main stage. The result will be that the output IM terms will not optimally cancel each other. Hence the IP 3  will not be as good as in the case where Q 4  and Q 5  have sufficient bandwidth. DAC 1  and DAC 2  are used to add or subtract DC current from the main and correction stages. The current trimming process is described below. R 2  is the emitter degeneration of the cancellation circuit. R 2  must be calculated in relation to DC biasing conditions and L 1 . The equation to determine the degeneration resistor value is given below. C 2  is placed between the main and correction stages so that the correction stage could be independently biased. This is done so that DC current in Q 3  can be varied independently of the biasing of Q 1 . Using a separate bias for the correction stage allows the degeneration resistor to be determined without the need for an offset current source tied to the emitter of Q 3 . The offset current source would be required if the correction stage was directly DC coupled to main stage. An offset current source is required if the correction stage is directly DC coupled to the main stage, as a result of the fact that one bias network would be used for both the main and correction stages, as opposed to using separate bias networks for each. Resultantly, the DC bias in the correction network would not be correct, since the correction stage is biased off of the same bias network as the input stage. Thus, the offset current source would be needed to properly bias the correction stage. 
         [0086]    Using a resistive degeneration in the correction circuit creates some design challenges, specifically, getting the correction stage to function over temperature and process. The DC bias network can be designed to work over temperature, process variation, and devices mismatches. Another important practice is to use one type of resistor in the bias circuits and in the main and correction stages. Also the current density in the main and correction stages should be the same for proper tracking. There are cases in which the DC current in this circuit needs to be digitally trimmed in order to achieve higher IP 3 . In the case of voltage offsets or resistor mismatches, the current in the correction and the main stage must be digitally programmable. This programmability is achieved through a digital to analog converters (DACs) DAC 1  and DAC 2  shown in  FIG. 13 . A resistor mismatch can cause the correction stage to have a different current which can degrade the overall performance. Current trimming can be used to correct the DC current in the correction stage or trim out any voltage offset in the correction circuit in order for the correction stage to properly function. The programmable digital to analog converters therefore provide a programmable correction for voltage offsets or resistor mismatches in order to achieve higher IP 3 . 
         [0087]      FIG. 14  shows a simulation that demonstrates this issue. In the simulation, a 2 mv offset was injected into the correction stage at the base of the correction transistor. The plot shows the effects of the offset and the result after trim current was applied. Process variations can also cause the correction stage to not function properly. Through simulations it can be shown that for the slow process case, more current is needed in the main stage of  FIG. 13  in order to get optimal IM cancellation. 
         [0088]      FIG. 15  shows OIP 3  versus DAC 1  trim current for the slow process. The current variation is achieved via DAC 1  that adds or takes away DC current to the DC bias circuit that provides the DC operating point to the main stage. As stated above, low NF is also desirable. 
         [0089]      FIG. 16  shows a noise floor for the circuit in  FIG. 13 , assuming a nominal process and a temperature of 27° C. 
         [0090]    A significant limitation of the prior art solutions is that the prior art trades off performance for the noise versus dynamic range. Either one of these parameters is optimized at the expense of the other. All of the mathematics previously developed in the preceding sections applies to this section as well. The emitter degenerated inductor L 1  has a real and imaginary part. In order for the correction stage to properly cancel IM terms, the magnitude of the L 1 &#39;s impedance must be related to the degeneration resistor R 2  in the correction as: 
         [0000]        R 2=( I 2/ I 1) 1/4 *[((1 +Gm 1 *ZL 1)+1)/( Gm 2)] 
         [0000]        ZL 1=Magnitude(2* π*f*L 1) where f is the operating frequency. 
         [0091]    In the corrected circuit of the present invention the issue becomes matching R 2  to the magnitude of L 1  over temperature and process. The bias in the main and correction stage should be optimized such that correction can be maintained over temperature. Simulations were run to analyze the OIP 3  as a function of temperature at nominal process. These simulations, summarized in Table 2 below, demonstrated that for a nominal process, no trimming is needed to maintain OIP 3  performance over temperature. 
         [0000]    
       
         
               
               
               
             
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Temperature 
                   
               
               
                   
                 (° C.) 
                 OIP3 (dBm) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 0 
                 25.0 
               
               
                   
                 25 
                 27.7 
               
               
                   
                 80 
                 26.5 
               
               
                   
                   
               
             
          
         
       
     
         [0092]    For other issues like process or device mismatch, it will be a requirement to have a digitally programmable current in order to maintain the distortion performance. This is accomplished through the use of a DAC to adjust the DC bias current in the correction stage or in the main stage. From the above equation, all the parameters except Gm 2  are known. The proper current for the correction stage can therefore be calculated. It must also be noted that the mirror circuitry in the correction stage must have signal bandwidth on the order of the input signal bandwidth in order for the correction to properly cancel IM terms. 
         [0093]    Table 3 below presents some of the simulation data for the performance of the circuit of  FIG. 13 . 
         [0000]    
       
         
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 Process 
                 OIP3 (dBm) 
                 Trim Adjustment 
               
               
                   
               
             
             
               
                 Nominal 27 
                 27.8 dBm 
                 No trim 
               
               
                 Fast 27 
                 27.5 dBm 
                 No trim 
               
               
                 Slow 27 
                 20.3 dBm 
                 No trim. 
               
               
                 Slow 27 
                 22.3 dBm 
                 With +330 uA trim current added to main 
               
               
                   
                   
                 stage (DAC2 trimmed only) 
               
               
                 Slow 27 
                 24.8 dBm 
                 With +660 uA trim current added to main 
               
               
                   
                   
                 stage (DAC2 trimmed only) 
               
               
                   
               
             
          
         
       
     
         [0094]    From the table above, it is shown that even though the magnitude of the inductive degeneration does not track the resistive degeneration of the correction circuit over process, through current trimming the OIP 3  can be maximized. Through simulations it was also shown that in the nominal and fast cases, current trimming was not needed when device mismatch was not considered. Thus the concept of single ended distortion nulling has been extended to the case of the inductively degenerated bipolar LNA. The extension of the single ended distortion nulling concept to the inductively degenerated bipolar LNA provides for unparalleled performance for NF and IP 3  in the same architecture, when compared to the existing state-of-the-art performance in the industry. 
         [0095]    It will be appreciated that the term “present invention” as used herein should not be construed to mean that only a single invention having a single essential element or group of elements is presented. Similarly, it will also be appreciated that the term “present invention” encompasses a number of separate innovations which can each be considered separate inventions. Although the present invention has thus been described in detail with regard to the preferred embodiments and drawings thereof, it should be apparent to those skilled in the art that various adaptations and modifications of the present invention may be accomplished without departing from the spirit and the scope of the invention. Accordingly, it is to be understood that the detailed description and the accompanying drawings as set forth hereinabove are not intended to limit the breadth of the present invention, which should be inferred only from the following claims and their appropriately construed legal equivalents.