Abstract:
A mock wordline timing scheme is used in a memory device having a plurality of memory cells arranged in array blocks. The array blocks are further arranged in groups, with each array block being located between a pair of corresponding sense amplifier banks. Each array block has at least one mock wordline, and each sense amplifier bank is shared by the array blocks located on either side of the sense amplifier bank, except the sense amplifier banks located on the ends of the group of array blocks. Each sense amplifier bank has a corresponding sense timing control circuit coupled to receive an enable signal and a timing signal. In response to an address, a row decoder is configured to be selected to drive the addressed word line. In conjunction with the row decoder, the enable and timing signals of the sense amplifier bank adjacent to the array block containing the addressed memory cell are asserted. The row decoder causes the timing signal to be propagated through a mock wordline that is not in the same array block as the addressed memory cell. Thus, memory cells in the active array are not disturbed, which could result in incorrect sensing and data corruption. Further, unlike some conventional schemes, the selected mock wordline is in an inactive array block even if the active array block is at an end of the bank of array blocks.

Description:
FIELD OF THE INVENTION 
     The present invention relates to integrated circuit memories and, more particularly, to timing control circuits for sensing the state of memory cells of integrated circuit memories. 
     BACKGROUND INFORMATION 
     Integrated circuit memories typically have an architecture in which memory cells are arranged in array blocks, with the array blocks being organized into banks. Each memory cell is accessed by appropriate activation of bitlines and wordlines. FIG. 1 is a simplified block diagram illustrative of a group 10 of the layout of an exemplary integrated circuit memory. Group 10 includes array blocks 11 0  -11 N ) with shared sense amplifier banks 12 0  -12 N+1  disposed between array blocks 11 0  -11 N . Group 10 also includes a row decoder 14, wordline driver blocks 15 0  -15 N  corresponding to array blocks 11 0  -11 N , and sense timing and control circuits 17 0  -17 N+1  corresponding to sense amplifier banks 12 0  -12 N+1 . 
     A brief summary of the operation of group 10 during a memory access operation is set forth below. The summary is not intended to completely describe the operation of the integrated circuit memory, which is generally well known in the art, but rather to illustrate one of the timing parameters that designers generally seek to optimize. 
     A &#34;row&#34; portion of the memory address is received by row decoder 14, which then activates the appropriate wordline driver of wordline driver blocks 15 0  -15 N  corresponding to the address. Typically, decoded address signals are received by the wordline driver blocks, which are then triggered by a row enable signal RE. That is, in a given cycle, the addressed wordline is not activated until row enable signal RE is asserted. Generally, the mapping of the memory addresses to memory cells is defined so that, depending on the number of array blocks, the most significant bits select one of memory arrays 11 0  -11 N , and the lower order bits select one of the wordlines within the selected array block. Thus, only one of array blocks 11 0  -11 N  is selected at a time, with only one wordline within the selected array block being activated. 
     At about the time that the wordline of the selected array block is being activated, a corresponding sense amplifier bank for the selected memory cell is also activated. As shown in FIG. 1, sense timing control circuits 17 0  -17 N+1  provide control signals to the sense amplifier banks 12 0  -12 N+1  in response to sense enable signals SE 0  -SE N+1 . The timing between the activation of the sense amplifier bank and the availability of data from the selected memory cell is important with regard to access time and data detection, as described below. FIG. 2 illustrates the relationship between row enable signal RE, the bitline data signal and the corresponding sense enable signal. As shown in FIG. 2, row enable signal RE is represented by a a waveform 20, the bitline data signal is represented by a waveform 22 and the sense enable signal is represented by a waveform 24. As indicated by an arrow 20 1 , in response to row enable signal RE being asserted, the appropriate wordline driver is activated, which allows the memory cells connected to the activated wordline to drive their corresponding bitlines to the stored data levels. The accessing of the memory cell results in charge sharing differential on the bit line, as indicated by an arrow 22 1 . 
     In addition, as indicated by an arrow 20 2 , assertion of row enable signal RE is also involved in the assertion of the appropriate sense enable signal (indicated herein as signal SE Z , with Z representing an integer between zero and N+1, inclusive). The assertion of the sense enable signal causes activation of the corresponding sense amplifier bank, which amplifies the bitline signal. If the timing of signal SE Z  is such that the leading edge of signal SE Z  is relatively early (as illustrated by leading edge 25), then the corresponding sense amplifier bank SA Z  can be activated before the corresponding selected memory cell can fully develop the data onto the selected bitline. As a result, the data could be sensed incorrectly and result in data corruption. 
     On the other hand, if the timing of signal SE Z  is such that the leading edge of signal SE Z  is relatively late (as illustrated by leading edge 26), then the corresponding sense amplifier bank SA Z  can be activated a relatively long time after the corresponding selected memory cell fully develops data onto the corresponding bitline. Although the data will most likely be sensed correctly, the unneeded delay undesirably increases the minimum access time of the memory device. Accordingly, it is desirable to design the timing of signal SE Z  such that the leading edge of signal SE Z  occurs so as to activate the corresponding sense amplifier SA Z  as soon as the selected memory cell develops the data on the bitlines, thereby allowing accurate sensing of the data while minimizing the access time. This is illustrated by leading edge 27 in FIG. 2. 
     FIG. 3 is a simplified block diagram illustrative of a group 30 of an integrated circuit memory that uses delay blocks 34 0  -34 N+1  to help control the timing of the sense amplifier activation. For clarity, the same reference numbers are used between drawings to indicate elements having the same or similar structure or function. Also, the row decoder and wordline driver blocks are omitted from the figure for clarity. Delay blocks 34 0  -34 N+1  are connected to receive row enable signal RE. Each delay block is designed to approximate the timing of the wordline activation in its corresponding array blocks. Also, sense timing control circuit 17 0  -17 N+1  are connected to receive the output signals of delay blocks 34 0  -34 N+1 , respectively. Otherwise, group 30 is similar to group 10 (FIG. 1) in architecture. 
     One problem with this scheme is that the timing can be relatively inaccurate. More specifically, due to the physical layout of sense amplifier banks 12 0  -12 N+1 , the propagation delay of row enable signal RE to the each of delay blocks 34 0  -34 N+1  will be different. Delay blocks 34 0  -34 N+1  are typically implemented with a series of inverters and, thus, may not accurately track varying propagation delays due to process variations. For example, wordlines are commonly implemented using polysilicon, which may have resistances that can vary for different process runs. Because the propagation delay of the wordlines can account for a significant portion of the delay between assertion of row enable signal RE and availability of the corresponding data on the bitlines, the timing of when data signals are available on the bitlines can vary significantly. 
     A refinement of this scheme is to place a block of unused memory cells near array blocks 11 0  -11 N  to serve as delay block 32. This scheme may use boundary memory cells (i.e., not used for storage) that may already be present. The delay of this version of delay block 32 would be provided by the wordlines in this block of unused memory cells. This approach still does not address the differences in propagation delay due to the physical layout of sense amplifier banks 12 0  -12 N+1  and the extra unused memory cells and, in addition, may undesirably use a significant amount of chip area. 
     FIG. 4 is a simplified block diagram illustrative of a group 40 of an integrated circuit memory that uses selectively activated wordline drivers 42 0  -42 N  along with mock wordlines 44 0  -44 N  to control the activation of sense amplifier banks 12 0  -12 N+1 . In this example, mock wordlines 44 0  -44 N  are local boundary wordlines located on the left side of array blocks 11 0  -11 N , respectively, and are essentially identical to the normal wordlines of these array blocks. In FIG. 4, mock wordline drivers 42 0  -42 N  are shown for driving mock wordlines 44 0  -44 N , respectively. As will be appreciated by those skilled in the art of integrated circuit memories, wordline drivers 42 0  -42 N  are part of wordline driver blocks 15 0  -15 N  (FIG. 1), with the other wordline drivers for the normal wordlines being omitted for clarity. 
     In this scheme, when a sense timing control circuit 17 Z  (Z being an integer between zero and N, inclusive) is to be activated, the mock wordline in array block 11 Z  (i.e., the array block to the right of the sense amplifier bank to be activated in this example circuit) is used to propagate the activation signal. In this example, mock wordlines 44 0  -44 N  are connected to corresponding wordline drivers 42 0  -42 N , respectively. Wordline drivers 42 0  -42 N  are connected to the output leads of NAND gates 46 0  -46 N , which are all also connected to receive row enable signal RE as an input signal. In addition, in this example, NAND gates 46 0  -46 N-1  are connected to receive enable signals SE 0  -SE N-1 , respectively, as another input signal. NAND gate 46 N  is connected to receive the logical OR of sense enable signals SE N  and SE N+1 . Mock wordlines 44 0  -44 N  are connected to sense timing control circuits 47 0  -47 N , respectively. Sense timing control circuits 47 0  -47 N  are substantially similar to sense timing control circuits 17 0  -17 N  (FIG. 1), except that sense timing circuits 47 0  -47 N  are selectively activated by the signal propagated by mock wordlines 44 0  -44 N , respectively. 
     Through the operation of NAND gates 46 0  -46 N  in response to the sense enable signals and row enable signal RE, the appropriate mock wordline is selected to activate the appropriate sense amplifier bank. For example, in a typical folded or segmented bitline architecture, when a wordline near the right side on array block 11 0  is activated in a memory access operation, sense enable signal SE 1  is typically asserted by conventional address decode circuitry (not shown) so as to activate sense amplifier bank 12 1 . As a result, mock wordline 44 1  is selected by NAND gate 46 1  and inverting wordline driver 42 1 , in response to signal SE 1  and the row enable signal RE. The signal propagated by the activated mock wordline then activates sense timing control circuit 47 1 . Because the selected mock wordline is relatively close to the activated normal wordline, the timing in activating the appropriate sense amplifier bank is more accurate compared to the previously described conventional methods. 
     However, this method still has problems in that activating the sense amplifier banks on either end of the array blocks (i.e., sense amplifier banks 12 0  and 12 N+1 ) may undesirably cause a mock wordline within the activated array block to be activated. For example, when a wordline near the right side of array block 11 N  is activated in a memory access operation, sense enable signal SE N+1  is typically asserted so as to activate sense amplifier bank 12 N+1 . However, in this example architecture, mock wordline 44 N  is used to enable sense timing control circuit 47 N+1  to activate sense amplifier bank 12 N+1 . Consequently, the activated mock wordline (i.e., wordline 44 N ) is undesirably in the activated array block (i.e., array block 11 N ). As a result, the activated mock wordline may disturb and/or reduce the voltage differential between the selected bitlines by accessing a row of boundary memory cells simultaneously with the accessing of a row of memory cells by the activated normal wordline. The simultaneous accessing of two rows of memory cells in array block 11 N  can result in sense margin reduction or data corruption in array block 11 N . This type of problem also occurs when a wordline near the left side of array block 11 0  is activated in a memory access operation. 
     Accordingly, there is a need for a timing scheme that accurately tracks the propagation delay in developing data on a bitline during a memory access operation without accessing other memory cells in the activated array block. 
     SUMMARY 
     In accordance with the present invention, an improved mock wordline timing scheme is provided for use in a memory device having a plurality of memory cells arranged in array blocks. The array blocks are further arranged in groups, with each array block being located between a pair of corresponding sense amplifier banks. In one embodiment, each array block has at least one mock wordline, and each sense amplifier bank is shared by the array blocks located on either side of the sense amplifier bank (except, of course, the sense amplifier banks located on the ends of the group of array blocks). 
     Each sense amplifier bank has a corresponding sense timing control circuit coupled to receive an enable signal and a timing signal. In response to an address, a row decoder is selected and subsequently drives a wordline. In conjunction with the row decoder, the enable and timing signals are generated to activate the sense amplifier bank adjacent to the array block containing the addressed memory cell (i.e., the active array block). In particular, the row decoder causes the timing signal to be propagated through a mock wordline that is not in the same array block as the addressed memory cell (i.e., the selected mock wordline is in an inactive array block). In this way, memory cells in the active array are not disturbed, which could result in incorrect sensing and data corruption. Further, unlike some conventional schemes, the selected mock wordline is in an inactive array block even if the active array block is at an end of the group of array blocks. 
     In one embodiment, each array block contains two mock wordlines, one on either side of the array block. In addition to being in an inactive array block as described above, the row decoder is also configured to select the mock wordline that is closest to the sense amplifier bank to be activated. For most addresses, this mock wordline is adjacent to the sense amplifier bank to be activated. That is, for these addresses, the selected mock wordline is in the array block located on the side of the sense amplifier bank that is opposite from the active array block. However, when the address corresponds to a memory cell that is to be sensed using the sense amplifier bank that is at an end of the bank of array blocks, there is no inactive array block on the other side of the sense amplifier bank to be activated. For these addresses, the selected mock wordline is in the one array block next to the active array block. Metal interconnect is used to connect the mock wordline to the sense amplifier bank, thereby reducing the delay caused by the extra distance that the sense amplifier timing signal must travel to the &#34;end&#34; sense amplifier bank. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated by reference to the following detailed description, when taken in conjunction with the accompanying drawings listed below. 
     FIG. 1 is a simplified block diagram illustrative of part of the layout of an exemplary integrated circuit memory. 
     FIG. 2 is a timing diagram illustrative of timing between activation of a wordline and the activation of the corresponding sense amplifier in an integrated circuit memory. 
     FIG. 3 is a simplified block diagram illustrative of a conventional scheme to control the timing of the sense amplifier activation using a delay block. 
     FIG. 4 is a simplified block diagram illustrative of another conventional scheme to control the timing of the sense amplifier activation using mock wordlines. 
     FIG. 5 is a simplified block diagram illustrative of a portion of an integrated circuit memory having an improved mock wordline architecture, according to the present invention. 
     FIG. 6 is a schematic diagram illustrative of a sense timing control circuit, according to one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 5 is a simplified block diagram illustrative of a group 50 of an integrated circuit memory having an improved mock wordline architecture. Group 50 is similar to group 40 (FIG. 4) except that: (a) inverter 42 0  and NAND gate 46 0  are omitted; and (b) group 50 includes sense timing control circuits 52 0  -52 N+1  instead of sense timing control circuits 47 0  -47 N . Sense timing control circuits 52 0  -52 N+1  have two activation input leads are described further below in conjunction with FIG. 6. In addition, group 50 includes mock wordlines 54 0  -54 N  disposed on the right side of array blocks (AB) 11 0  -11 N , respectively, and also includes additional NAND gates 56 0  -56 N-1  connected to mock wordlines 54 0  -54 N-1  through wordline drivers 58 0  -58 N-1 . Mock wordlines 44 0  and 54 N  are connected to the ground bus. 
     As shown in FIG. 5, mock wordlines 44 0  and 54 N  are the outer-most mock wordlines of group 50 and, according to the symmetrical layout of the bank, would be expected to be connected to sense timing control circuits 52 0  and 52 N+1 , respectively. However, in another aspect of this embodiment, mock wordlines 44 0  and 54 N  are connected to the ground bus instead, with sense timing control circuits 52 0  and 52 N+1  being connected to mock wordlines 44 1  and 54 N-1 , respectively. In this embodiment, metal interconnects 59 are used to electrically connect sense timing control circuits 52 0  and 52 N+1  to mock wordlines 44 1  and 54 N-1 , respectively, to reduce resistance. 
     NAND gates 56 0  -56 N-1  are each connected to receive row enable signal RE and are also connected to receive sense timing signals ST 1L  -ST NL , respectively. As shown in FIG. 5, sense timing signals ST 1L  -ST NL  are the sense timing signals that are asserted to activate mock wordlines to the left of the selected sense amplifier bank. Similarly, NAND gates 46 1  -46 N  are connected to receive sense timing signals ST 1R  -ST NR , respectively, instead of sense enable signals SE 0  -SE N  as in group 40 (FIG. 4). As shown in FIG. 5, sense timing signals ST 1R  -ST NR  are the sense timing signals that are asserted to activate mock wordlines to the right of the selected sense amplifier bank. Sense timing control circuits 52 0  -52 N+1  are substantially similar to sense timing control circuits 47 0  -47 N+1  (FIG. 4), except that each of sense timing control circuits 52 0  -52 N+1  has two activation input leads for activating the sense timing control circuit. Each sense timing control circuit 52 Z  of sense timing control circuits 52 1  -52 N  (i.e., not including array blocks 52 0  and 52 N+1  that are at the ends of group 50) has one activation input lead connected to the mock wordline of the array block on the left of the sense timing control circuit, and the other activation input lead connected to the mock wordline of the array block to the right of the sense timing control circuit. That is, each sense timing control circuit 52 Z  has one activation input lead connected to mock wordline 54 Z-1  and another connected to mock wordline 44 Z . 
     In contrast, sense timing control circuit 52 0  has one activation input lead connected to the ground bus and the other activation input lead connected to mock wordline 44 0 . Similarly, sense timing control circuit 52 N+1  has one activation input lead connected to the ground bus and the other activation input lead connected to mock wordline 54 N . 
     For each of sense timing control circuits 52 0  -52 N+1 , when enabled by its corresponding sense enable signal, assertion of a signal received on either activation input lead causes the sense timing control circuit to be activated. In an alternative embodiment, sense timing control circuits 52 0  -52 N+1  can be replaced by sense timing control circuits 47 0  -47 N+1  with each sense timing control circuit 47 0  -47 N+1  being connected to a corresponding two-input OR gate. Each of these OR gates has its output lead connected to the single activation input lead of its corresponding sense timing control circuit. In addition, the two input leads of each OR gate serve as the two activation input leads for its corresponding sense timing control circuits 47 0  -47 N+1 . 
     In another alternative embodiment, sense timing control circuits 52 0  and 52 N+1  may be replaced with conventional single-input sense timing control circuits such shown in FIG. 4 because the sense timing control circuits 52 0  and 52 N+1  each have only one activation input lead connected to a mock wordline (i.e., the other activation input lead is connected to the ground bus). 
     Sense timing signals ST 1R  -ST NR  and ST 1L  -ST NL  are generated by a conventional row decoder (not shown) so that, in response to the address of the memory access operation, the appropriate sense timing signal is asserted to activate the appropriate mock wordline. The appropriate mock wordline is the mock wordline (of a non-active array block in group 50) that is nearest to the sense amplifier bank corresponding to the particular memory cell being accessed. In particular, the row decoder (not shown) is configured to assert a predetermined one of sense timing signals ST 1R  -ST NR  so as to activate the mock wordline that is both: (i) in a non-active array block, and (ii) nearest the sense amplifier bank to be activated. In light of the present disclosure, those skilled in the art of integrated circuit memories can, without undue experimentation, implement and configure the row decoder (not shown) so that the address of each memory cell is mapped to the appropriate mock wordline. 
     In this embodiment when memory cells of &#34;end&#34; array blocks 11 0  or 11 N  are being accessed, the corresponding &#34;end&#34; sense amplifier banks 12 0  or 12 N+1  would be activated, respectively. Consequently, the nearest non-active array block would be array block 11 1  or 11 N-1 , respectively. In these cases, the row decoder (not shown) is configured to activate mock wordlines 44 1  or 54 N-1 , respectively, by asserting signals SE 1R  or SE NL , respectively. Although mock wordlines 44 1  and 54 N-1  are located relatively far away from sense amplifier banks 12 0  and 12 N+1 , respectively, metal interconnects 59 used to electrically connect these mock wordlines to sense timing control circuits 52 0  and 52 N+1  incur only a relatively small amount of extra propagation delay, which is typically insignificant in comparison to the propagation delay from the polysilicon mock wordlines. 
     In a further refinement, mock wordlines 44 1  and 54 N-1  can be tapped anywhere along their lengths by metal interconnect 59 to equalize the total propagation delay of the path to the sense amplifier bank, relative to the normal wordline path to the memory cell. 
     Some examples are described below to further illustrate the operation of this embodiment. When a memory cell on the left side of array block 11 N  is to be accessed, the row decoder (not shown) is configured to assert both sense enable signal SE N  and sense timing signal ST NL . As a result, sense timing control circuit 52 N  is enabled by sense enable signal SE N , while sense timing signal ST NL  is received at one input lead of NAND gate 56 N-1  When row enable signal RE is asserted, sense timing control circuit 52 N  is then activated by NAND gate 56 N-1  and wordline driver 58 N-1 , in response to the output signal of wordline driver 58 N-1  propagating through mock wordline 54 N-1  in adjacent array block 11 N-1 . Because the activated mock wordline is in a non-activated array block, the activated mock wordline avoids disturbing memory cells in the array block of the addressed memory cell. In addition, being on the right side of array block 11 N-1 , mock wordline 54 N-1  is relatively closer to the addressed normal wordline in array block 11 N , compared to the aforementioned conventional scheme that has mock wordlines only on the left side of the array blocks. Thus, this scheme provides more accurate tracking of the actual timing of the memory cell access. 
     On the other hand, when a memory cell on the right side of array block 11 N  is to be accessed, the row decoder (not shown) is configured to assert sense enable signal SE N+1  and sense timing signal ST NL . As a result, sense timing control circuit 52 N+1  is enabled by sense enable signal SE N+1 , while sense timing signal ST NL  is received at one input lead of NAND gate 56 N-1 . When row enable signal RE is asserted, sense timing control circuit 52 N+1  is then activated by NAND gate 56 N-1  and wordline driver 58 N-1 , in response to the output signal of wordline driver 58 N-1  propagating through mock wordline 54 N-1  in adjacent array block 11 N-1  and metal interconnect 59. Unlike in the conventional scheme of group 40 (FIG. 4), the activated mock wordline is in a non-activated array block, thereby avoiding disruption of memory cells in the array block of the addressed memory cell. As described above, metal interconnect 59 significantly reduces the extra propagation delay due to the farther difference between mock wordline 54 N-1  and sense timing control circuit 52 N+1 . Thus, this situation still results in accurate tracking of the actual timing of the memory cell access without disturbing unaddressed memory cells in the active array block. 
     Similar to the first example, when a memory cell on the right side of array block 11 N-1  is to be accessed, the row decoder (not shown) is configured to assert both sense enable signal SE N  and sense timing signal ST NR . As a result, sense timing control circuit 52 N  is enabled by sense enable signal SE N , while sense timing signal ST NR  is received at one input lead of NAND gate 56 N . When row enable signal RE is asserted, sense timing control circuit 52 N  is then activated by NAND gate 56 N  and wordline driver 58 N , in response to the output signal of wordline driver 58 N  propagating through mock wordline 44 N  in adjacent array block 11 N  Again, the activated mock wordline is in a non-activated array block and is relatively close to the active normal wordline of the addressed memory cell. Thus, memory cells in the array block of the addressed memory cell are not unnecessarily disturbed and the timing of the memory cell access is accurately tracked. 
     FIG. 6 is a schematic diagram illustrative of a sense timing control circuit 52 Z , according to one embodiment of the present invention. This embodiment of sense timing control circuit 52 Z  includes input circuits 60 1  and 60 2 , NAND gates 61 1  and 61 2 , a programmable delay circuit 62, a programmable delay output buffer circuit 63 and a buffer 64. Input circuits 60 1  and 60 2  are essentially identical, being configured to invert the received signal with a delayed high-to-low output signal transition. Input circuit 60 1  is connected to receive signal ST ZL  (via NAND gate 56 Z-1  and wordline driver 58 Z-1 ) and input circuit 60 2  is connected to receive signal ST ZR  (via NAND gate 46 Z  and wordline driver 42 Z ). Two-input NAND gate 61 1  is connected to receive the output signals from input circuits 60 1  and 60 2 . 
     The output lead of NAND gate 61 1  is connected to the input lead of programmable delay circuit 62 through a node 65. Node 65, the output lead of programmable delay circuit 62 and the output lead of buffer 64 are connected to the input leads of three-input NAND gate 61 2 , with buffer 64 being connected to receive sense enable signal SE Z . The output lead of NAND gate 61 2  is connected to the input lead of programmable delay output buffer 63, which generates several sense amplifier timing signals as a function of the output signal from NAND gate 61 2 . Programmable delay output buffer 63 is conventional, generating one or more sense amplifier timing signals (with the number of timing signals depending on the design of the sense amplifiers). In one embodiment, programmable delay output buffer 63 generates two differential timing signals from the output signal of NAND gate 61 2 , with varying amounts of delay between the two sets of signals. 
     Programmable delay circuit 62 and programmable delay output buffer 63 have delay elements (not shown) that can be programmably connected into the signal propagation path. In one embodiment, standard metal option techniques are used to adjust the delay as desired. In alternative embodiments, the delay elements may be programmably connected into the signal propagation path by fuses, antifuses, laser techniques, etc. The delay elements (not shown) are typically implemented with an even number of inverting stages. 
     Input circuit 60 1  includes a P-channel transistor 66 and three N-channel transistors 67 1  -67 3 . P-channel transistor 66 has its source connected to the VDD supply bus, its gate connected to receive sense timing signal ST ZL  (via mock wordline 54 Z-1 , NAND gate 56 Z-1  and wordline driver 58 Z-1 ), and its drain connected to an output lead 68 1 . Output lead 68 1  is also connected to one input lead of NAND gate 61 1 . N-channel transistor 67 1  has its drain connected to output lead 68 1 , and has its gate connected to the gates of transistors 66 and 67 2 , and has its source connected to a node 69. N-channel transistor 67 2  has its source connected to the ground bus and its drain connected to node 69. N-channel transistor 67 3  has its source connected to node 69, it gate connected to output lead 68 1 , and its drain connected to the VDD supply bus. Output lead 68 1  is connected to one of the input leads of NAND gate 61 1 . Input circuit 60 2  is substantially similar to input circuit 60 1 , except that input circuit has an output lead 68 2  connected to the other input lead of NAND gate 61 1 . 
     Sense timing control circuit 52 Z  operates as follows. Input circuits 601 and 60 2  form, in effect, conventional CMOS inverters, with an extra delay mechanism to slow down high-to-low output signal transitions. For example, when sense timing signal ST ZL  is at a logic low level, P-channel transistor 66 is turned on while N-channel transistors 67 1  and 67 2  are turned off. As a result, the voltage at output lead 68 1  is pulled up to a logic high level. This logic high level at output lead 68 1  causes N-channel transistor 67 3  to be turned on, thereby causing the voltage at node 69 to be about a threshold voltage (of N-channel transistor 67 3 ) below the level of the VDD supply voltage (i.e., VDD-V tn ). Then, when sense timing signal ST ZL  transitions to a logic high level, P-channel transistor 66 begins to turn off and N-channel transistor 67 2  begins to turn on. 
     However, because the voltage at node 69 has a value that is about equal to VDD-V tn , N-channel transistor 67 1  does not turn on at the same time as N-channel transistor 67 2 . Instead, N-channel transistor 67 1  begins to turns on (to start pulling down the voltage at output lead 68 1 ) when the voltage level of sense timing signal ST ZL  reaches a relatively high level about equal to a threshold voltage above the voltage level at node 69. The voltage level at node 69, at the start of the high-to-low transition of the output signal, was about equal to a threshold voltage below the VDD supply voltage, but would be slightly lower than this level due to N-channel transistor 67 2  being turned on. As a result of the operation of N-channel transistor 67 3 , high-to-low transitions of the output signal at output lead 68 1  are relatively slow. 
     Then when sense timing signal ST ZL  transitions from a logic high level to a logic low level (i.e., causing a low-to-high output signal transition), P-channel transistor 66 begins to turn on while N-channel transistors 67 1  and 67 2  begin to turn off. Although the gate capacitance of N-channel transistor 67 3  tends to slow down P-channel 66 in pulling up the voltage at output lead 68 1 , this delay is significantly less than the delay provided by N-channel transistor 67 3  during a high-to-low output signal transition. 
     Input circuit 60 2  has one P-channel transistor and three N-channel transistors (not shown) that are interconnected in an identical manner as input circuit 60 1 , except for receiving sense timing signal ST ZR  (via mock wordline 44 Z , NAND gate 46 Z  and wordline driver 42 Z ) and generating the output signal on output lead 68 2 . Consequently, input circuit 60 2  operates in substantially the same manner as input circuit 60 1 . 
     When sense timing signals ST ZL  and ST ZR  are both deasserted (i.e., at logic low levels in this embodiment), input circuits 60 1  and 60 2  both generate logic high output signals that are received by NAND gate 61 1 . Thus, NAND gate 61 1  outputs a logic low signal to programmable delay circuit 62 and NAND gate 61 2 . As a result, NAND gate 61 2  outputs a logic high level signal to programmable delay output buffer 63. In response to a logic high level signal from NAND gate 61 2 , programmable delay output buffer 63 is configured to deassert the timing signals provided to the corresponding sense amplifier bank. 
     On the other hand, if sense timing signal ST ZL  (or sense timing signal ST ZR ) are asserted, then input circuit 60 1  (or input circuit 60 2 ) will output a logic low signal to NAND gate 61 1 , which then will output a logic high signal to programmable delay circuit 62 and NAND gate 61 2 . Ordinarily, the row decoder (not shown) will have already asserted sense enable signal SE Z  by the time sense timing signal ST ZL  (or sense timing signal ST ZR ) has propagated through the mock wordline from the mock wordline&#39;s corresponding NAND gate and wordline driver. Thus, when the logic high signal from NAND gate 61 1  propagates through programmable delay circuit 62, NAND gate 61 2  will have logic high signals at all three of its input leads. As a result, NAND gate 61 2  will output a logic low level signal to programmable delay output buffer 63, which in response thereto, asserts the timing signals to the corresponding sense amplifier bank. It will be appreciated by those skilled in the art of integrated circuit memories that the programmable delays of programmable delay circuit 62 and programmable delay output buffer 63 may be programmably adjusted to achieve the desired timing. In an alternative embodiment, NAND gate 61 2  may be a two-input NAND gate having its input leads respectively connected to the output leads of programmable delay circuit 62 and buffer 64, provided appropriate one-sided delays are added in another part of the circuit. 
     It will also be appreciated by those skilled in the art of integrated circuit memories that if sense enable signal SE Z  is not asserted (i.e., at a logic high level), NAND gate 61 2  will continue to output a logic high level signal to programmable delay output buffer 63. This situation may occur with the sense timing control circuits at the ends of group 50 (FIG. 5). For example, referring to FIG. 5, mock wordline 54 N-1  is used for both sense timing control circuits 52 N  and 52 N+1 . Thus, for example, if sense timing control circuit 52 N  is to be activated, then sense enable signal SE N+1  may not be asserted, even though the sense timing signal from mock wordline 54 N-1  is asserted and received by sense timing control circuit 52 N+1 . In this way, sense amplifier bank 12 N  is activated while, advantageously, sense amplifier bank 12 N+1  is not. 
     The embodiments of the regulator system described above are illustrative of the principles of the present invention and are not intended to limit the invention to the particular embodiments described. For example, those skilled in the art of integrated circuit memories, in light of this disclosure, can implement, without undue experimentation, other embodiments of the logic circuits of the sense amplifier timing control circuit that are different from the logic described but still achieve the same function. Further, if more delay is needed between the assertion of the row enable signal and the sense timing signals, a common delay block can be inserted. Accordingly, while the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.