Abstract:
The present invention provides a current controlled oscillator comprising a first section providing a first differential output and a second section providing a second differential output. A loading structure comprised of resistive and reactive elements electrically connects the first differential output with the second differential output. The resistive and reactive elements have values chosen such that the resistive elements substantially extend the linear operating frequency range of the current controlled oscillator. Transistors of the loading structure have which are tied to a power supply rejection ratio compensation section for compensating for variations in power supply voltage.

Description:
FIELD OF THE INVENTION 
   The present invention relates to current-controlled oscillators and more particularly to a low voltage 3-stage current-controlled oscillator with extended linear gain and low sensitivity to process and temperature variation. 
   BACKGROUND OF THE INVENTION 
   In recent years the telecommunications industry has increased its demand for improved performance from current controlled oscillators (CCO). For example, when designing phase locked loops (PLL) for frequency synthesizers and clock recovery circuits, it helps to have a CCO with linear gain to allow better modeling during system design. Better modeling during system design helps avoid possible instability problems. 
   Additionally, it is important to reduce the CCO&#39;s power consumption and reduce the design margin. This can be achieved by designing the CCO to have low process and temperature sensitivity. 
   Conventional 3-stage ring oscillators of the prior art can have a wide tuning range, but the CCO gain is sensitive to process and temperature variation. The CCO gain is much higher when it works under low temperature, fast-fast (FFL) conditions than it works under high temperature, slow-slow (SSH) conditions. In order to make a conventional CCO oscillate over a certain frequency range, a much larger tuning range is required because of the process and temperature variations. Another problem with conventional CCO&#39;s is that the gain will drop, or become flat, at high frequencies, rather than increasing linearly, because of velocity saturation. 
     FIG. 1  illustrates a prior art circuit  7  comprising a conventional CCO fully differential inverter cell and its loading. Four pMOS transistors  9 ,  11 ,  13 ,  15  have their drains tied to the voltage Vdd. The gates of the transistors  9  and  15  are both tied to a voltage Vb  19 . The voltabe Vb  19  is generated from a voltage Vbn  18  through a replica bias. Here, Vbn  18  is the control voltage for controlling the current I control . The gate of transistor  11  is tied to the sources of the transistors  9  and  11  as well as to the output  8  of the differential outputs  10  and  8 . The gate of transistor  13  is similarly tied to the sources of the transistors  13  and  15  as well as to the output  8  of the differential outputs  10  and  8 . A capacitor  16  is connected between the differential outputs  10  and  8 . This capacitor actually reduces the output frequency of the CCO  7 , however, it is necessary for improving the jitter performance. 
   The nMOS transistors  12 ,  14  have gates supplied by current supply inputs  2  and  3  which are connected to the output of the previous stage of the inverter cell as illustrated in  FIG. 9 . The sources of the transistors  12 ,  14  are connected to the sources of the transistors  9 ,  11  and  13 ,  15 , respectively. The source of the transistor  12  also leads to the differential output  8 . Connected to the drains of the transistors  12 ,  14  is the source of another nMOS transistor  16  having its gate supplied by a voltage  18 . The transistor  16  has its drain grounded. 
     FIG. 6  illustrates the CCO gain of the prior art circuit  7  of  FIG. 1 . Control current (in amps) is plotted along the x-axis while frequency (in Hertz) is plotted along the y-axis. There are separate curves for different design process corners and temperatures. The curves represent the SSH (slow-slow, high temperature), normal and FFL (fast-fast, low temperature) conditions. The curves, especially for the SSH condition tend to flatten when the control current becomes large. This is because the transistors  9 ,  15  enter the velocity saturation and their g m  value does not continue to increase with control current. 
   An example of a prior art CCO design providing temperature variation compensation is presented in the paper entitled, “A 622-MHz Interpolating Ring VCO with Temperature Compensation and Jitter Analysis”, by Wing-Hong Chan, published in the IEEE International Symposium on Circuits and Systems, Jun. 9-12, 1997, Hong Kong. However, the method this paper can only provide compensation at one fixed frequency and cannot compensate for process variation. In addition, it requires many additional circuits resulting in greater power consumption, size and cost. 
   Another example of a prior art CCO design is presented in “Low-Jitter Process-Independent DLL and PLL Based on Self-Bias Techniques&#39;, IEEE J. Solid-State Circuits, vol. 31, No. 11, November 1996 by John G. Maneatis. However, this prior art CCO does not sufficiently extend the linear region of the CCO gain or minimize the process and temperature sensitivity. 
   It would therefore be desirable to provide a CCO with extended linear gain over a broad tuning range, greater stability, reduced size and power consumption and reduced sensitivity to process and temperature variation. Additionally, it would be desirable to provide a CCO with these features while maintaining a good power supply rejection ratio (PSRR). 
   SUMMARY OF THE INVENTION 
   The present invention provides a CCO with extended linear gain over a broad tuning range, high stability, reduced size, reduced power consumption and reduced sensitivity to process and temperature variation. These features are achieved in the present invention by utilizing a 3-stage CCO processed in a CMOS. The CCO achieves low sensitivity to process variation and linear gain over a broad frequency range by utilizing an RC//C loading structure. The power supply rejection ratio is also improved using a power supply rejection ratio (PSRR) compensation section comprising a current source and diode electrically connected to the loading structure. 
   In general terms, the invention is for a current controlled oscillator comprising a first section providing a first differential output and a second section providing a second differential output. A loading structure comprised of resistive and reactive elements electrically connects the first differential output with the second differential output. The resistive and reactive elements have values chosen such that the resistive elements substantially extend the linear operating frequency range of the current controlled oscillator. Transistors of the loading structure have gates which are tied to a power supply rejection ratio compensation section for compensating for variations in power supply voltage. 

   
     BRIEF DESCRIPTION OF THE FIGURES 
     Further preferred features of the invention will now be described for the sake of example only with reference to the following figures, in which: 
       FIG. 1 . illustrates a conventional CCO fully differential inverter cell and its loading. 
       FIG. 2  illustrates a stage of the 3-stage CCO of the present invention utilizing an RC//C loading structure. 
       FIG. 3  shows a stage of the CCO as in  FIG. 2 , but including a power supply rejection ratio (PSRR) compensation section. 
       FIGS. 4(   a ) and  4 ( b ) are equivalent circuit models of the circuits in  FIG. 1  and  FIG. 2 , respectively. 
       FIG. 5  is a pole zero diagram for the circuit of  FIG. 4(   b ). 
       FIG. 6  plots the CCO gain of the circuit of  FIG. 1  for three different process and temperature conditions. 
       FIG. 7  plots the CCO gain of the gain compensated circuit of  FIG. 2  for three different process and temperature conditions. 
       FIG. 8  plots the CCO gain of the PSRR compensated circuit of  FIG. 3  for two different power supply voltages and for each of three different process and temperature conditions. 
       FIG. 9  shows the three stages of the CCO. 
   

   DETAILED DESCRIPTION OF THE EMBODIMENTS 
     FIG. 2  illustrates a circuit  21  of a 3-stage CCO processed in a C 11 N digital CMOS.  FIG. 9  shows the entire 3-stage CCO  51  where the circuit  21  would be positioned as the stage  53 . The circuit achieves low sensitivity to process variation and linear gain over a broad frequency range by utilizing an RC//C loading structure  23 . The difference between the prior art circuit of  FIG. 1  and the inventive circuit of  FIG. 2  is the loading. The source of a pMOS transistor  25  is connected in series to the drain of a pMOS transistor  27  through a capacitor  29 . The series connection is connected between the differential outputs  10  and  8  parallel with the capacitor  16 . Both gates of the transistors  25  and  27  are tied to ground. 
   As compared to the CCO design of the Maneatis reference, the CCO of the present invention has a linear region of CCO gain extended by over 50% and the process and temperature sensitivity of the CCO gain is reduced by between 33% and 75% at an output frequency range of 500 MHz to 1.25 GHz. 
     FIG. 4(   a ) illustrates an equivalent circuit diagram  41  of the loading of the conventional CCO circuit of  FIG. 1  and  FIG. 4(   b ) illustrates an equivalent circuit diagram  43  of the inventive CCO circuit of  FIG. 2 . 
   In  FIG. 4(   a ) a resistance R 1   48  is connected to a capacitance C 1   45 . Here R 1 ≈1/g m7  and C 1  45 equals the sum of the capacitor C  16  and the loading capacitor C gs  of next stage of the CCO (see  FIG. 9) . Here, gm7 is the equivalent gm of a symmetrical load, i.e. transistor pair  9 ,  11  or  13 ,  15 . Also, C gs  of next stage is the Cgs of the transistors  12 ,  14  in  FIG. 2 . This circuit has one dominant pole located at: 
                   P   1     =       1       R   1     ⁢     C   1         =       g   m7       C   1                 (   1.1   )               
The oscillation frequency of this CCO is:
 
   
     
       
         
           
             
               
                 
                   f 
                   osc 
                 
                 = 
                 
                   
                     1 
                     
                       6 
                       ⁢ 
                       
                         R 
                         1 
                       
                       ⁢ 
                       
                         C 
                         1 
                       
                     
                   
                   = 
                   
                     
                       g 
                       m7 
                     
                     
                       6 
                       ⁢ 
                       
                         C 
                         1 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 1.2 
                 ) 
               
             
           
         
       
     
   
   As a tuning current  55  changes, the value of g m7  also changes, thus changing the output frequency. 
   In  FIG. 4(   b ) the RC//C loading structure  23  of  FIG. 2  is represented by an additional series connection between a resistance R 2   42  and a capacitance C 2   44  added in parallel with the capacitance C 1   45 . R 1 ,C 1  has the same value as in  FIG. 4(   a ). Note that there is an always-on pMOS transistor and a capacitor C 2    44  connected serially in this circuit, resulting in more complex loading of the circuit  21 . Calculations show that this loading has 2 poles and 1 zero located at: 
                   P   1     =         -     (       τ   1     +     τ   2     +       R   1     ⁢     C   2         )       +           (       τ   1     +     τ   2     +       R   1     ⁢     C   2         )     2     -     4   ⁢     τ   1     ⁢     τ   2               2   ⁢     τ   1     ⁢     τ   2                 (   1.3   )                 P   2     =         -     (       τ   1     +     τ   2     +       R   1     ⁢     C   2         )       -           (       τ   1     +     τ   2     +       R   1     ⁢     C   2         )     2     -     4   ⁢     τ   1     ⁢     τ   2               2   ⁢     τ   1     ⁢     τ   2                 (   1.4   )                 Z   1     =     1       R   2     ⁢     C   2                 (   1.5   )               
Where τ 1 =R 1 C 1  and τ 2 =R 2 C 2 .
 
   The formula is complex, so for better understanding of the pole zero movement on the S plane, an assumption is made that C 1 =C 2 , and that the resistor R 2    42  is the only variable. Three extreme cases are considered. 
   
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           P 
                           2 
                         
                         = 
                         
                           - 
                           
                             1 
                             
                               τ 
                               2 
                             
                           
                         
                       
                       , 
                       
                         
                           P 
                           1 
                         
                         = 
                         
                           - 
                           
                             1 
                             
                               τ 
                               1 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                           
                       
                       ⁢ 
                       
                         
                           τ 
                           2 
                         
                         ⪢ 
                         
                           τ 
                           1 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 1.6 
                 ) 
               
             
           
           
             
               
                 
                   
                     
                       
                         
                           P 
                           2 
                         
                         = 
                         
                           
                             - 
                             
                               
                                 3 
                                 + 
                                 
                                   5 
                                 
                               
                               2 
                             
                           
                           ⁢ 
                           τ 
                         
                       
                       , 
                       
                         
                           P 
                           1 
                         
                         = 
                         
                           
                             - 
                             
                               
                                 3 
                                 - 
                                 
                                   5 
                                 
                               
                               2 
                             
                           
                           ⁢ 
                           τ 
                         
                       
                     
                   
                   
                     
                       
                           
                       
                       ⁢ 
                       
                         
                           τ 
                           2 
                         
                         = 
                         
                           
                             τ 
                             1 
                           
                           = 
                           τ 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 1.7 
                 ) 
               
             
           
           
             
               
                 
                   
                     
                       
                         
                           P 
                           2 
                         
                         = 
                         
                           - 
                           
                             1 
                             
                               τ 
                               2 
                             
                           
                         
                       
                       , 
                       
                         
                           P 
                           1 
                         
                         = 
                         
                           - 
                           
                             1 
                             
                               2 
                               ⁢ 
                               
                                 τ 
                                 1 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                           
                       
                       ⁢ 
                       
                         
                           τ 
                           2 
                         
                         ⪡ 
                         
                           τ 
                           1 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 1.8 
                 ) 
               
             
           
         
       
     
   
   The pole zero diagram of  FIG. 5  shows the movement of the poles and zero in equation 1.6-1.8. P 1  starts at 
             -     1       R   1     ⁢     C   1           ,         
moving toward 0 and stopping at
 
             -     1     2   ⁢     R   1     ⁢     C   1           ,         
while P 2  moves from 0 to negative infinity. Z 1  starts from 0 and stops at P 2 /2.
 
   From  FIG. 5 , an interesting finding is that if the pole and zero are set at the location in the box labeled “optimum point”, the oscillation frequency is determined by P 2 , rather than P 1 , thus increasing the oscillation frequency. Thus, by properly selecting the transistor sizes of the transistors  25  and  27  in  FIG. 2 , the resistance of these transistors can dominate the oscillation frequency at the high frequency range and compensate the flat portion of the curves in  FIG. 6 , thereby extending the linear range. 
   As mentioned before, the relationship between g m7  (resistor R 1 ) and the tuning/control current I ctrl  is not linear. Due to the velocity saturation, g m7  will become a constant value after the control current reaches a certain value. In the circuit  7  of  FIG. 1 , the CCO gain will become ‘flat’ at high frequency. (As shown in  FIG. 6 ). However, in the circuit  21  of  FIG. 2 , the linear range of CCO gain is extended. 
     FIG. 4   b , illustrates how the always-on pMOS transistor and capacitance C 2   44  form an RC branch. During operation, because of the oscillation, the voltage swings at node A  46 . The capacitor C 2    44  is continuously charged and discharged. The relationship between the average charge and discharge current and the oscillation frequency f osc  is determined by equation 1.9 
                     1     2   ⁢     f   osc         ·     I   c       =       C   2     ⁢   Δ   ⁢           ⁢   V             (   1.9   )               
Where I c  is the average charge-discharge current and ΔV  49  is the voltage variation across the capacitor C 2    44 . If ΔV  49  remains unchanged, I c  is proportional to oscillation frequency f osc . The resistance value of the always-on pMOS transistor (R 2    42 ) is not a constant, it will increase with the charge current I c . In the present invention, the transistor size is selected so that the pole generated by resistor R 2    42  dominates the oscillation frequency at the flat potion of CCO gain curve in  FIG. 6 . It compensates the flat portion of curve and extends the linear range. The simulation results of CCO gain by using the circuits  7  and  21  of  FIG. 1  and  FIG. 2  are shown in  FIG. 6  and  FIG. 7 , respectively.  FIG. 7 , like  FIG. 6 , illustrates the CCO gain, but this time for the circuit  21  of  FIG. 2 . Control current (in Amps) is plotted along the x-axis while frequency (in Hertz) is plotted along the y-axis. There are separate curves for different design process corners and temperatures. The curves represent the SSH (slow-slow, high temperature), normal and FFL (fast-fast, low temperature) conditions.
 
     FIG. 7  shows that the spread of the CCO gain curves between different operating conditions becomes smaller for the circuit  21  of the present invention. This is because for the FFL condition, the variation of the resistance value of R 2    42  (the resistance value of the transistors  25 ,  27 ) is small and for the SSH condition, the resistor value of R 2    42  is large. Thus, R 2    42  has more effect on the SSH case than the FFL case, causing the curve for the SSH case to move towards the curve for the FFL case, thus reducing the CCO gain sensitivity due to process variation. For the same reason, the SSH curve actually overlaps the curve for nominal case at high frequency. 
     FIG. 3  illustrates another embodiment of the present invention including a power supply rejection ratio (PSRR) compensation section  31 . The transistors  25 ,  27  of the circuit  21  in  FIG. 2  act as resistors. A change in the power supply voltage Vdd changes the resistance value of the transistors  25 ,  27  and therefore the frequency behavior. The transistors  25 ,  27  act in a non-differential way and can therefore degrade the power supply rejection ratio (PSRR). Rather than tying the gates of the transistors  25 ,  27  to ground as in  FIG. 2 , the gates are attached to the PSRR compensation section  31  which tracks variation of a power supply. The voltage at a node  35  tracks the supply voltage Vdd at 17. The PSRR compensation includes a diode  59 , a current source  37  and a current mirror  57 . The voltage potential Vpsrr and the CCO output have the same variation relative to the power supply. Therefore, the resistances of the transistors  25 ,  27  of  FIG. 3  become independent of power supply variation. 
     FIG. 8 , like  FIGS. 6 and 7 , illustrates the CCO gain, but this time for the circuit  33  of  FIG. 3 . Control current (in amps) is plotted along the x-axis while frequency (in Hertz) is plotted along the y-axis. There are separate curves for different design process corners and temperatures. The curves represent the SSH (slow-slow, high temperature), normal and FFL (fast-fast, low temperature) conditions. Also, in order to illustrate PSRR performance, curves are plotted for two different Vdd&#39;s (1.65 V and 1.35 V) for each set of process corners and temperatures. From  FIG. 8  it can be seen that the circuit  33  has good PSRR performance. 
   Returning to  FIG. 9 , the cell  53  can be circuit  21  or  33  of the present invention. 
   In another alternative embodiment, the gates of the transistors  25 ,  27  can be connected to different potentials to get other advantages such as better PSRR, better TC (temperature coefficient) etc. 
   In the illustrated embodiments, other combinations of impedances can be serve as the loading structure  23  and the PSRR compensation section  31 . Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to a skilled reader.