Abstract:
A DC-AC converter has two half-bridge circuits using an input feedback signal and an input clock signal together with time delay circuits, wherein one of the half-bridge circuits drives one pair of corresponding FETs and the other half-bridge circuit drives the other pair of corresponding FETs. The DC-AC converter includes: a Direct Current (DC) power source; a switching unit which includes a plurality of Field Effect Transistors (FETs) for changing paths of Direct Current (DC), so as to convert the DC to Alternating Current (AC); a transformer for transforming a voltage input from the switching unit; a load unit connected to the transformer; and a signal control unit for simultaneously parallel control of the FETs in the switching unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to and the benefit of Korean Patent Application No. 10-2006-0001515 filed in the Korean Intellectual Property Office on Jan. 5, 2006, the entire contents of which are incorporated herein by reference. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to a Direct Current to Alternating Current (DC-AC) converter, and more particularly to a DC-AC converter employing a parallel operation scheme, which has two half-bridge circuits using an input feedback signal and an input clock signal together with time delay circuits, wherein one of the half-bridge circuits drives one pair of corresponding FETs and the other half-bridge circuit drives the other pair of corresponding FETs. 
       BACKGROUND OF THE INVENTION 
       [0003]    As generally known in the art, a Cold Cathode Fluorescent Lamp (CCFL) has various advantages including low power consumption, small heat radiation, high luminance, long lifespan, etc. because it can be operated by low current. The CCFL is now widely used as a backlight of a Liquid Crystal Display (LCD). A high Alternating Current (AC) voltage of 1 to 2 KV is necessary in order to turn on such a CCFL, and a DC-AC converter is usually used in order to provide such a high AC voltage. 
         [0004]      FIG. 1  illustrates a circuit of a conventional DC-AC converter. 
         [0005]    As shown, the conventional DC-AC converter includes a transformer TX 1 , a Direct Current (DC) power source  21 ′, a bias/reference voltage generator  23 ′ for generating bias and reference voltages necessary for internal operation from the DC power source  21 ′, a switching unit  28 ′ including four Field Effect Transistors (FETs) from switch A to switch D for providing current paths within the transformer TX 1  by switching the voltage V 1  according to driving signals, an LCD panel  22 ′ including a CCFL operated by the transformer TX 1 , a protection circuit unit  26 ′ for detecting an output voltage OVP and providing a sweeping stop signal when the detected output voltage exceeds a reference voltage, a frequency sweeper  27 ′ for generating a rectangular pulse of 50% duty-cycle by performing frequency sweeping until the output voltage OVP exceeds the reference voltage before the step signal is input from the protection circuit unit  26 ′ in an open lamp state, a feedback control unit  24 ′ for comparing the feedback voltage from the protection circuit unit  26 ′ with the reference voltage and controlling switch-on time of the switching unit based on a result of the comparison, and a driving circuit unit  25 ′ for providing a driving signal to the switching unit  28 ′ according to the rectangular pulse of the frequency sweeper  27 ′ and a switch-on time control signal of the feedback control unit  24 ′. 
         [0006]    The protection circuit unit  26 ′ includes a comparator  26 A′, a timer  26 B′, and an electric current sensor  26 C′. The comparator  26 A′ determines if the lamp open or not by comparing the CMP signal and a voltage signal from the LCD panel  22 ′ with the reference signal and provides a stop signal to the frequency sweeper  27 ′. The timer  26 B′ has a time out period set in advance and is started when the detected voltage exceeds the reference voltage. When the timer has been operated during the time out period, the comparator  26 A′ provides the stop signal. The electric current sensor  26 C′ controls the frequency sweeper  27 ′. 
         [0007]    U.S. Pat. No. 6,259,615 discloses a detailed example of such a DC-AC converter as described above. 
         [0008]    The conventional DC-AC converter having the construction as described above employs a phase-shift scheme, i.e. a serial operation scheme, according to which a pair of switches including switch A and switch B are first sequentially operated by using the signal from the frequency sweeper, and the other pair of switches including switch C and switch D are then sequentially operated by using the feedback signal thereof. 
         [0009]    However, such a conventional DC-AC converter requires a complicated control method and uses a 50% pulse frequency sweeper. Therefore, the conventional DC-AC converter requires complicated design and high manufacturing costs. 
         [0010]    Further, most manufacturers currently produce DC-AC converters employing the phase-shift scheme or similar schemes, which thus have a high possibility of patent conflict occurring between them. Therefore, there has been a request for a DC-AC converter, which can be controlled by a simple control method, can be designed in a simple manner, and requires small manufacturing costs, while avoiding patent conflict. 
       SUMMARY OF THE INVENTION 
       [0011]    Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a DC-AC converter employing a parallel operation scheme, which has two half-bridge circuits using an input feedback signal and an input clock signal together with time delay circuits, wherein one of the half-bridge circuits drives one pair of corresponding FETs and the other half-bridge circuit drives the other pair of corresponding FETs. 
         [0012]    In order to accomplish this object, there is provided a Direct Current to Alternating Current (DC-AC) converter including: a Direct Current (DC) power source; a switching unit which includes a plurality of Field Effect Transistors (FETs) for changing paths of Direct Current (DC), so as to convert the DC to Alternating Current (AC); a transformer for transforming a voltage input from the switching unit; a load unit connected to the transformer; and a signal control unit for simultaneously parallel control of the FETs in the switching unit. 
         [0013]    The FETs in the switching unit may include a first P channel FET and a first N channel FET, which are interconnected in series and connected in parallel to the DC power source, and a second P channel FET and a second N channel FET, which are interconnected in series and connected in parallel to the DC power source. 
         [0014]    The DC-AC converter may further include a feedback control unit connected between the switching unit and the load unit, so as to generate and output a predetermined signal by using a feedback signal from the load unit and a clock signal from the oscillator. 
         [0015]    The signal control unit outputs four control signals by using the predetermined signal from the feedback control unit and the clock signal of the oscillator, so as to simultaneously control the first P channel FET, the first N channel FET, the second P channel FET, and the second N channel FET in parallel. 
         [0016]    The DC-AC converter may further include a FET driver unit which includes a first driver and a second driver, wherein the first driver receives two control signals from the signal control unit and then outputs driving signals to the first P channel FET and the first N channel FET of the switching unit, and the second driver receives the other two control signals from the signal control unit and then outputs driving signals to the second P channel FET and the second N channel FET of the switching unit. 
         [0017]    The transformer includes a first coil and a second coil, the first coil has one end connected to a line between the second P channel FET and the second N channel FET of the switching unit and has the other end connected to a line between the first P channel FET and the first N channel FET, and both ends of the second coil are connected to the load unit while one end of the second coil is connected to the second N channel FET of the switching unit. 
         [0018]    The signal control unit forms a first current path through the first coil by turning on the first P channel FET P 1  and the second N channel FET together during a predetermined time interval, and then forms a second current path through the first coil by turning on the second P channel FET and the first N channel FET together during a predetermined time interval, the first current path being opposite to the second current path. 
         [0019]    The signal control unit controls a time interval for simultaneous turning-on of both the first P channel FET and the second N channel FET and a time interval for simultaneous turning-on of both the second P channel FET and the first N channel FET based on a reference signal from the feedback control unit. 
         [0020]    The signal control unit includes a first half-bridge circuit for controlling the first P channel FET and the first N channel FET and a second half-bridge circuit for controlling the second P channel FET and the second N channel FET. 
         [0021]    In order to control the first P channel FET, the signal control unit may include: a toggle switch to which a clock signal of the oscillator is input; a first AND gate to which the reference signal output from the feedback control unit and the clock signal output from the toggle switch are input; a time delay unit which delays a signal from the first AND gate for a predetermined time interval and then outputs a delayed signal; a first inverter for inverting a signal from the time delay unit and outputting an inverted signal; a second AND gate to which a signal from the first AND gate and the inverted signal from the first inverter are input; and a second inverter to which a signal from the second AND gate is input. 
         [0022]    In order to control the first N channel FET, the signal control unit may include: a toggle switch to which a clock signal of the oscillator is input; a first AND gate to which the reference signal output from the feedback control unit and the clock signal output from the toggle switch are input; a first inverter for inverting a signal from the first AND gate and outputting an inverted signal; a time delay unit which delays a signal from the first inverter for a predetermined time interval and then outputs a delayed signal; a second inverter for inverting a signal from the time delay unit and outputting an inverted signal; a second AND gate to which the inverted signal from the first inverter and the inverted signal from the second inverter are input; a third inverter to which a signal from the second AND gate is input; and a fourth inverter to which a signal from the third AND gate is input. 
         [0023]    In order to control the second P channel FET, the signal control unit may include: a toggle switch to which a clock signal of the oscillator is input; a first inverter to which a signal output from the toggle switch is input; a first AND gate to which the reference signal output from the feedback control unit and a signal output from the first inverter are input; a time delay unit which delays a signal from the first AND gate for a predetermined time interval and then outputs a delayed signal; a second inverter for inverting a signal from the time delay unit and outputting an inverted signal; a second AND gate to which a signal from the first AND gate and a signal from the second inverter are input; and a third inverter to which a signal from the second AND gate is input. 
         [0024]    In order to control the second N channel FET, the signal control unit may include: a toggle switch to which a clock signal of the oscillator is input; a first inverter to which a signal output from the toggle switch is input; a first AND gate to which the reference signal output from the feedback control unit and a signal output from the first inverter are input; a second inverter for inverting and outputting a signal from the first AND gate; a time delay unit which delays a signal from the second inverter for a predetermined time interval and then outputs a delayed signal; a third inverter for inverting a signal from the time delay unit and outputting an inverted signal; a second AND gate to which a signal from the second inverter and a signal from the third inverter are input; a fourth inverter to which a signal from the second AND gate is input; and a fifth inverter to which a signal from the fourth inverter is input. 
         [0025]    The time delay unit may include: a P channel FET, a gate voltage of which is controlled by an input signal; a static current source connected to a drain of the P channel FET; a comparator having an inverting node connected to a line between the P channel FET and the static current source and a non-inverting node connected to a reference voltage source; and a capacitor connected to a line between a grounding node and the non-inverting node of the comparator. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]    The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0027]      FIG. 1  is a circuit diagram illustrating a conventional DC-AC converter; 
           [0028]      FIG. 2   a  is a block diagram illustrating a DC-AC converter according to the present invention; 
           [0029]      FIG. 2   b  is a block diagram illustrating a feedback control unit, a signal control unit, and an FET driver in the DC-AC converter of  FIG. 2   a;    
           [0030]      FIG. 3  is a circuit diagram of a logic circuit for a signal control unit of a DC-AC converter according to an embodiment of the present invention; 
           [0031]      FIG. 4   a  illustrates waveforms of signals by each FET of a conventional DC-AC converter; and 
           [0032]      FIG. 4   b  illustrates waveforms of signals by each FET of a DC-AC converter according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0033]    Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description on the same or similar components will be omitted. 
         [0034]      FIG. 2   a  is a block diagram illustrating a DC-AC converter according to the present invention, and  FIG. 2   b  is a block diagram illustrating a feedback control unit, a signal control unit, and an FET driver in the DC-AC converter of  FIG. 2   a.    
         [0035]    As shown, the DC-AC converter  100  according to the present invention includes a DC power source  110 , a switching unit  120 , a transformer  130 , a load unit  140 , a feedback control unit  150 , a signal control unit  160 , and an FET driver unit  170 . 
         [0036]    The DC power source  110  outputs a predetermined DC voltage V 1 . 
         [0037]    The switching unit  120  may include four FETs. In the switching unit  120 , a first P channel EFT P 1  and a first N channel FET N 1  are connected in series to each other, while a source of the first P channel EFT P 1  is connected to a plus node of the DC power source  110  and a source of the first N channel EFT N 1  is connected to a minus node of the DC power source  110 . Further, a second P channel EFT P 2  and a second N channel FET N 2  are connected in series to each other, while a source of the second P channel EFT P 2  is connected to the first P channel FET P 1  and a source of the second N channel EFT N 2  is connected to the first N channel FET N 1 . Moreover, both of the first P channel FET P 1  and the second P channel FET P 2  has a body diode in a direction from drain to source, and both of the first N channel FET N 1  and the second N channel FET N 2  has a forward body diode in a direction from source to drain. 
         [0038]    The transformer  130  may include a first coil  131  and a second coil  132 . The first coil  131  has one end connected to the line between the second P channel FET P 2  and the second N channel FET N 2  of the switching unit  120  and has the other end connected through a capacitor C 1  to the line between the first P channel FET P 1  and the first N channel FET N 1 . Further, both ends of the second coil  132  are connected to the load unit  140 , while one end of the second coil  132  is connected to the source of the second N channel FET N 2 . 
         [0039]    The load unit  140  is connected in parallel to the second coil  132  of the transformer  130 . The load unit  140  includes a CCFL  141  mounted in an LCD panel  142 . Further, the load unit  140  includes capacitors C 2 , C 3  and C 4 , a resistor R 1 , and a diode D 1 , to which the construction of the invention is not limited, though. It is possible to obtain the feedback signal FB of the load unit  140  from the line between the resistor R 1  and the capacitor C 4 . 
         [0040]    The feedback control unit  150  includes an error amplifier  151 , a comparator  152 , and an oscillator  153 . The feedback signal FB from the load unit  140  is input to the inverting node of the error amplifier  151 , and the reference voltage is applied to a non-inverting node of the error amplifier  151 . Further, a signal CMP from the error amplifier  151  is input to a non-inverting node of the comparator  152 , and a clock signal of the oscillator  153  is input to an inverting node of the comparator  152 . In addition, a signal Comp from the comparator  152  together with the clock signal of the oscillator  153  is output to the signal control unit  160 . 
         [0041]    The signal control unit  160  receives two signals from the feedback control unit  150 , which include the signal Comp output from the comparator  152  and the clock signal from the oscillator  153 , and outputs predetermined control signals p 1   in , n 1   in , p 2   in , and n 2   in  for parallel control of the four FETs in the switching unit  120 . 
         [0042]    Specifically, by the control signals p 1   in , n 1   in , p 2   in , and n 2   in  output from the signal control unit  160 , both the second P channel FET P 2  and the first N channel FET N 1  are turned on together so as to form a first current path through the first coil  131  during a predetermined time interval, and both the first P channel FET P 1  and the second N channel FET N 2  are turned on together so as to form a second current path (which is opposite to the first current path) through the first coil  131  during a predetermined time interval. It goes without saying that the first P channel FET P 1  and the first N channel FET N 1  are not simultaneously turned on by the signal control unit  160 . Also, the second P channel FET P 2  and the second N channel FET N 2  are not simultaneously turned on by the signal control unit  160 , either. 
         [0043]    Further, the signal control unit  160  can change the electric power supplied to the load unit  140  by controlling the time interval for the turning-on of both the second P channel FET P 2  and the first N channel FET N 1  and the time interval for the turning-on of both the first P channel FET P 1  and the second N channel FET N 2  based on the signal from the feedback control unit  150 , specifically, based on the feedback signal from the load unit  140 . 
         [0044]    The FET driver unit  170  includes a first driver  171  and a second driver  172 . The first driver  171  receives two control signals p 1  in and n 1  in from the signal control unit  160 , and then drives the first P channel FET P 1  and the first N channel FET N 1  of the switching unit  120 . The second driver  172  receives the other two control signals p 2  in and n 2  in from the signal control unit  160 , and then drives the second P channel FET P 2  and the second N channel FET N 2  of the switching unit  120 . Specifically, the first driver  171  outputs signals P 1 Out and N 1 Out, and the second driver  172  outputs signals P 2 Out and N 2 Out. 
         [0045]      FIG. 3  is a circuit diagram of a logic circuit for a signal control unit of a DC-AC converter according to an embodiment of the present invention. 
         [0046]    As shown, the signal control unit  160  according to the present invention includes a first half-bridge circuit  161  for control of the first P channel FET P 1  and the first N channel FET N 1  and a second half-bridge circuit  162  for control of the second P channel FET P 2  and the second N channel FET N 2 . The first half-bridge circuit  161  and the second half-bridge circuit  162  simultaneously operate, so that the four FETs are simultaneously controlled according to a parallel operation scheme instead of the phase-shift scheme (serial operation scheme). 
         [0047]    The first half-bridge circuit  161  includes logic circuits for controlling the first P channel FET P 1 , which include a toggle switch TG to which a clock signal of the oscillator  153  is input, a first AND gate  1  to which the signal Comp output from the feedback control unit  150  and a signal output from the toggle switch TG are input, a time delay unit TD 1  which delays a signal from the first AND gate  1  for a predetermined time interval and then outputs the delayed signal, a first inverter  11  for inverting a signal from the time delay unit TD 1  and outputting the inverted signal, a second AND gate  12  to which a signal from the first AND gate  1  and a signal from the first inverter  11  are input, and a second inverter  13  to which a signal from the second AND gate  12  is input. 
         [0048]      FIG. 4   b  illustrates waveforms of signals which include the signal CMP output from the error amplifier  151  by the feedback signal in the feedback control unit  150 , the signal CT input to the oscillator  153  and the comparator  152 , the signal Comp output from the comparator  152  and then input to the signal control unit  160 , and the clock signal Clock output from the oscillator  153  and then input to the signal control unit  160 . 
         [0049]    Further, it is noted from  FIG. 4   b  that, in the logic circuit for controlling the first P channel FET P 1 , the signal output from the time delay unit TD 1  shows a delay of a predetermined time interval when it shifts down from the high state to the low state (see P 1  waveform). 
         [0050]    The first half-bridge circuit  161  further includes logic circuits for controlling the first N channel FET N 1 , which include a toggle switch TG to which a clock signal of the oscillator  153  is input, a first AND gate  1  to which the signal Comp output from the feedback control unit  150  and a signal output from the toggle switch TG are input, a first inverter  21  for inverting and outputting the signal from the first AND gate  1 , a time delay unit TD 2  which delays a signal from the first inverter  21  for a predetermined time interval and then outputs the delayed signal, a second inverter  22  for inverting a signal from the time delay unit TD 2  and outputting the inverted signal, a second AND gate  23  to which a signal from the first AND gate  1  and a signal from the second inverter  22  are input, a third inverter  24  to which a signal from the second AND gate  23  is input, and a fourth inverter  25  to which a signal from the third inverter  24  is input. 
         [0051]    It is noted from  FIG. 4   b  that, in the logic circuit for controlling the first N channel FET N 1 , the signal output from the time delay unit TD 2  shows a delay of a predetermined time interval when it shifts down from the high state to the low state (see N 1  waveform). 
         [0052]    As noted from the above description, in the first half-bridge circuit  161 , the first N channel FET N 1  is turned on during a relatively long time period while the first P channel FET P 1  is turned on during a relatively short time period which does not overlap with the relatively long time period for the turning-on of the first N channel FET N 1  (see waveform of P 1 +N 1 ). 
         [0053]    The second half-bridge circuit  162  includes logic circuits for controlling the second P channel FET P 2 , which include a toggle switch TG to which a clock signal of the oscillator  153  is input, a first inverter  2  to which a signal output from the toggle switch TG is input, a first AND gate  3  to which the signal Comp output from the feedback control unit  150  and a signal output from the first inverter  2  are input, a time delay unit TD 3  which delays a signal from the first AND gate  3  for a predetermined time interval and then outputs the delayed signal, a second inverter  31  for inverting a signal from the time delay unit TD 3  and outputting the inverted signal, a second AND gate  32  to which a signal from the first AND gate  3  and a signal from the second inverter  31  are input, and a third inverter  33  to which a signal from the second AND gate  32  is input. 
         [0054]    Also, it is noted from  FIG. 4   b  that, in the logic circuit for controlling the second P channel FET P 2 , the signal output from the time delay unit TD 3  shows a delay of a predetermined time interval when it shifts down from the high state to the low state (see P 2  waveform). 
         [0055]    The second half-bridge circuit  162  further includes logic circuits for controlling the second N channel FET N 2 , which include a toggle switch TG to which a clock signal of the oscillator  153  is input, the first inverter  2  to which a signal from the toggle switch TG is input, a first AND gate  3  to which the signal Comp output from the feedback control unit  150  and a signal output from the first inverter  2  are input, a second inverter  41  for inverting and outputting the signal from the first AND gate  3 , a time delay unit TD 4  which delays a signal from the second inverter  41  for a predetermined time interval and then outputs the delayed signal, a third inverter  42  for inverting a signal from the time delay unit TD 4  and outputting the inverted signal, a second AND gate  43  to which a signal from the second inverter  41  and a signal from the third inverter  42  are input, a fourth inverter  44  to which a signal from the second AND gate  43  is input, and a fifth inverter  45  to which a signal from the fourth inverter  44  is input. 
         [0056]    It is also noted from  FIG. 4   b  that, in the logic circuit for controlling the second N channel FET N 2 , the signal output from the time delay unit TD 4  shows a delay of a predetermined time interval when it shifts down from the high state to the low state (see N 2  waveform). 
         [0057]    As noted from the above description, in the second half-bridge circuit  162 , the second N channel FET N 2  is turned on during a relatively long time period while the second P channel FET P 2  is turned on during a relatively short time period which does not overlap with the relatively long time period for the turning-on of the second N channel FET N 2  (see waveform of P 2 +N 2 ). 
         [0058]    As noted from the waveform of P 1 N 2 +P 2 N 1 , by the first half-bridge circuit  161  and the second half-bridge circuit  162  as described above, both the first P channel FET P 1  and the second N channel FET N 2  are simultaneously turned on during a predetermined time interval, and both the second P channel FET P 2  and the first N channel FET N 1  are then simultaneously turned on during a predetermined time interval. Of course, such turning on and off is repeated in an alternating manner. 
         [0059]    Therefore, it is noted that the waveform of P 1 N 2 +P 2 N 1  shown in  FIG. 4   b  is equal to the waveform f of  FIG. 4   a , that is, the waveform of B&amp;C and A&amp;D, which is a waveform of the prior art. That is, the waveform finally obtained by the present invention is the same as that of the prior art. Further, it is noted that the turning on time of the FET serves as a power control means to determine the electric power. 
         [0060]    However, as described above, the signal control unit  160  according to the present invention includes two half-bridge circuits  161  and  162 , wherein the first half-bridge circuit  161  controls the first P channel FET P 1  and the first N channel FET N 1  and the second half-bridge circuit  162  controls the second P channel FET P 2  and the second N channel FET N 2 . That is, in controlling four FETs, the present invention employs a parallel operation scheme instead of the phase shift scheme or the serial operation scheme, which is used in the prior art. Therefore, the present invention simplifies the control scheme and reduces the number of elements. 
         [0061]    Further, according to the present invention, as in the prior art, the feedback signal FB from the load unit  140  causes a change in the signal CMP from the error amplifier  151  of the feedback control unit  150 , which results in change of the time for simultaneous turning-on of the first P channel FET P 1  and the second N channel FET N 2  and the time for simultaneous turning-on of the second P channel FET P 2  and the first N channel FET N 1 , thereby controlling the output power through the transformer  130 . 
         [0062]    Further, each of the time delay units TD 1 , TD 2 , TD 3 , and TD 4  includes a P channel FET, a gate voltage of which is controlled by an input signal, a static current source connected to a drain of the P channel FET, a comparator having an inverting node connected to a line between the P channel FET and the static current source and a non-inverting node connected to a reference voltage source, and a capacitor connected to a line between a grounding node and the non-inverting node of the comparator. Therefore, the delay time by each of the time delay units TD 1 , TD 2 , TD 3 , and TD 4  is determined by the capacitance of the capacitor in each of the time delay units TD 1 , TD 2 , TD 3 , and TD 4 , so that it is possible to determine the time delay in the actual output waveform by controlling the capacitance of the capacitor in each of the time delay units TD 1 , TD 2 , TD 3 , and TD 4 . 
         [0063]    In the DC-AC converter according to the present invention as described above, the switching unit includes first and second P channel FETs and first and second N channel FETs, wherein one of two drivers controls the first P channel FET and the first N channel FET and the other of the two drivers controls the first P channel FET and the first N channel FET, while both of the two drivers are controlled in parallel by one signal control unit. 
         [0064]    That is, according to the present invention, one half-bridge controls one pair of corresponding FETs, and another half-bridge controls another pair of corresponding FETs. 
         [0065]    In other words, the present invention controls a plurality of FETs according to a parallel control scheme instead of a serial control scheme. Therefore, the present invention does not require circuits including a 50% frequency sweeper, which are indispensable in the prior art. 
         [0066]    Therefore, the present invention provides a DC-AC converter which employs a simplified control scheme and includes simplified elements while having the same efficiency as that of a conventional DC-AC converter. 
         [0067]    Further, the present invention can avoid possible patent conflict in advance with the current phase shift type converters manufactured by the most converter providers. 
         [0068]    Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.