Abstract:
The present invention provides an LMS adaptive filter, by which signal distortion due to time interval is compensated and by which a filter size can be minimized. The present invention includes a first multiplier alternately outputting a value calculated by multiplying a first delayed signal and an error signal together and a value calculated by multiplying a second delayed signal and the error signal together, an adder adding a signal outputted from the first multiplier to a previous coefficient, a first delayer receiving a signal outputted from the adder and outputting a first new coefficient by synchronization with a first clock, a second delayer receiving the signal outputted from the adder and outputting a second new coefficient by synchronization with a reference clock, a second multiplier alternately outputting a value calculated by multiplying the first new coefficient and the input signal and a value calculated by multiplying the second new coefficient and a third delayed signal, and a third delayer outputting a signal outputted from the second multiplier by synchronization with a second clock.

Description:
[0001]     This application claims the benefit of the Korean Application No. P2003-60219 filed on Aug. 29, 2003, which is hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an LMS (least mean square) adaptive filter applicable to an equalizer, noise remover, and the like of a digital TV.  
         [0004]     2. Discussion of the Related Art  
         [0005]     Generally, a least mean square (hereinafter abbreviated LMS) adaptive filter is a filter keeping updating a coefficient using TMS adaptive algorithm. The LMS adaptive filter is operative in compensating a signal distortion caused by channels or a system itself.  
         [0006]      FIG. 1  is a structural diagram of an LMS adaptive filter according to a related art.  
         [0007]     Referring to  FIG. 1 , a first delayer D 1  receives an input signal x 0  and outputs a delayed signal x 1 . A second delayer D 2  receives the delayed signal x 1  and outputs a delayed signal x 2 . A third delayer D 3  receives a delayed signal xd 0  and outputs a delayed signal xd 1 . And, a fourth delayer D 4  receives the delayed signal xd 1  and outputs a delayed signal xd 2 .  
         [0008]     The delayed signals xd 0 , xd 1 , and xd 2  are signals delayed from the signals x 0 , x 1 , and x 2  by prescribed delay times, respectively. And, the delay times are variable according to a circuit design. For instance, ‘x 0 ’ is passed through one delayer D 1  to provide ‘xd 0 ’. Yet, ‘x 0 ’ can be passed through at least two delayers D 1  and D 2  to provide ‘xd 0 ’. Such a procedure is applicable to ‘xd 1 ’ or ‘xd 2 ’ as well.  
         [0009]     A first tap unit T 1  receiving the signals x 0  and xd 0  to output an output signal y 0  and a second tap unit T 2  receiving the signals x 1  and xd 1  to output an output signal y 1  are provided. The first tap unit T 1  has the same configuration of the second tap unit T 2 .  
         [0010]     The first tap unit T 1  consists of a first multiplier M 1  multiplying the delayed signal xd 0  by an error ‘e’, a first adder A 1  adding an operational result of the first multiplier M 1  to a previous coefficient, a fifth delayer D 5  synchronized with a unit cycle signal to store an output result of the first adder A 1  and to output a new coefficient c 0 , and a second multiplier M 2  producing an output signal y 0  for a first tap by multiplying the coefficient c 0  outputted from the fifth delayer D 5  by the input signal x 0 .  
         [0011]     The second tap unit T 2  consists of a third multiplier M 3  multiplying the delayed signal xd 1  by an error ‘e’, a second adder A 2  adding an operational result of the third multiplier M 3  to a previous coefficient, a sixth delayer D 6  synchronized with a unit cycle signal to store an output result of the second adder A 2  and to output a new coefficient c 1 , and a fourth multiplier M 4  producing an output signal y 1  for a second tap by multiplying the coefficient c 1  outputted from the sixth delayer D 6  by the delayed signal x 1 .  
         [0012]     A coefficient update process in the LMS adaptive filter is explained as follows.  
         [0013]     First of all, the delayed signal xd 0  is multiplied by the error ‘e’ in the first multiplier M 1  of the first tap unit T 1 . A multiplied result is added to the previous coefficient by the first adder A 1 . A value computed by the first adder A 1  is synchronized with the unit cycle signal to be stored in the fifth delayer D 5 . And, the coefficient c 0  is updated with this value.  
         [0014]     Simultancously, the delayed signal xd 1  is multiplied by the error ‘e’ in the third multiplier M 3  of the second tap unit T 2 . A multiplied result is added to the previous coefficient by the second adder A 2 . A value computed by the second adder A 2  is synchronized with the unit cycle signal to be stored in the sixth delayer D 6 . And, the coefficient c 1  is updated with this value.  
         [0015]     Subsequently, the input signal x 0  is multiplied by the coefficient c 0  in the second multiplier M 2  to generate the output signal y 0  of the first tap T 1 . And, the delayed signal x 1  is multiplied by the coefficicnt c 1  in the fourth multiplier M 4  to generate the output signal y 1  of the second tap T 2 .  
         [0016]     Thus, each tap of the LMS adaptive filter needs one multiplier and one adder for coefficient update and one multiplier for generating the output signal.  
         [0017]     For the smooth broadcast reception via channel having distortion (long-term fading) due to time interval in the recent terrestrial TV, the distortion needs to be compensated. In order to effective compensate the distortion due to the time interval, the filter used in the equalizer or noise-remover should be provided with many taps.  
         [0018]     However, the related filter having many taps has difficult in implementation since a size of the filter should be increased to include many taps therein.  
       SUMMARY OF THE INVENTION  
       [0019]     Accordingly, the present invention is directed to an LMS (least mean square) adaptive filter that substantially obviates one or more problems due to limitations and disadvantages of the related art  
         [0020]     An object of the present invention is to provide an LMS adaptive filter, by which signal distortion due to time interval is compensated and by which a filter size can be minimized.  
         [0021]     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
         [0022]     To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, an adaptive filter according to the present invention includes a first multiplier alternately outputting a value found by multiplying a first delayed signal and an error signal together and a value found by multiplying a second delayed signal and the error signal together wherein each of the first and second delayed signals is delayed behind an input signal, an adder adding a signal outputted from the first multiplier to a previous coefficient, a first delayer receiving a signal outputted from the adder to output a first new coefficient by synchronization with a first clock, a second delayer receiving the signal outputted from the adder to output a second new coefficient by synchronization with a reference clock, a second multiplier alternately outputting a value found by multiplying the first new coefficient by the input signal and a value found by multiplying the second new coefficient by a third delayed signal, and a third delayer synchronizing a signal outputted from the second multiplier with a second clock to output.  
         [0023]     Preferably, the first clock is delayed by ½ cycle more than the reference clock. And, the second clock is delayed by ¼ cycle more than the reference clock.  
         [0024]     In another aspect of the present invention, an adaptive filter includes a first multiplexer outputting either a first delayed input signal delayed behind an input signal or a second delayed signal according to a selection signal, a first multiplier multiplying a signal outputted from the first multiplexer by an error signal, an adder adding a signal outputted from the first multiplier to a previous coefficient, a first delayer receiving a signal outputted from the adder to output a first new coefficient by synchronization with a first clock, a second delayer receiving the signal outputted from the adder to output a second new coefficient by synchronization with a reference clock, a second multiplexer outputting either the first new coefficient outputted from the first delayer or the second new coefficient outputted from the second delayer to the adder according to the selection signal, a third multiplexer outputting either the input signal or a third delayed signal delayed behind the input signal according to the selection signal, a second multiplier multiplying a coefficient outputted from the second multiplexer by a signal outputted from the third multiplexer, and a third delayer synchronizing a signal outputted from the second multiplier with a second clock to output.  
         [0025]     Preferably, the first new coefficient includes the first delayed signal, the error signal, and the previous coefficient. And, the second new coefficient includes the second delayed signal, the error signal, and the previous coefficient.  
         [0026]     Preferably, the adaptive filter further includes a delayer receiving the first delayed signal to output the second delayed signal delayed behind the first delay signal. And, the delayer synchronizes the second delayed signal with the reference clock to output.  
         [0027]     Preferably, the adaptive filter further includes a delayer receiving the input signal to output the third delayed signal delayed behind the input signal. And, the delayer synchronizes the third delayed signal with the reference clock to output.  
         [0028]     It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:  
         [0030]      FIG. 1  is a structural diagram of an LMS adaptive filter according to a related art;  
         [0031]      FIG. 2  is a block diagram of an LMS adaptive filter according to a first embodiment of the present invention;  
         [0032]      FIG. 3  is a block diagram of an LMS adaptive filter according to a second embodiment of the present invention; and  
         [0033]      FIG. 4  and  FIG. 5  are timing diagrams of an LMS adaptive filter according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0034]     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.  
         [0035]     First Embodiment  
         [0036]      FIG. 2  is a block diagram of an LMS adaptive filter according to a first embodiment of the present invention.  
         [0037]     Referring to  FIG. 2 , a first delayer D 11  receives a signal xd 0  delayed by a prescribed time behind an input signal x 0  and outputs a signal xd 1  delayed more than the delayed signal xd 0 . A second delayer D 12  receives the delayed signal xd 1  and outputs a signal xd 2  delayed more than the delayed signal xd 1 . A third delayer D 13  receives the input signal x 0  and outputs a signal x 1  delayed more than the input signal x 0 . And, a fourth delayer D 14  receives the delayed signal x 1  and outputs a signal x 2  delayed more than the delayed signal x 1 . The first to fourth delayers D 11  to D 14  are synchronized with a reference clock signal elk to output the delayed signals xd 1 , xd 2 , x 1 , and x 2 , respectively. Each of the delayed signals xd 1 , xd 2 , x 1 , and x 2  is delayed more than the input signal x 0 . Each delay time of the delayed signals xd 1 , xd 2 , x 1 , and x 2  can be varies according to a circuit design. The input signal x 0  is passed through one delayer to provide the delayed signal xd 0 . Besides, the input signal x 0  may be passed through at least two delayers to provide the delayed signal xd 0 .  
         [0038]     A first multiplexer MUX 1  receives the two delayed signals xd 0  and xd 1  and selectively outputs one of the delayed signals xd 0  and xd 1  according to a logic value or level of an selection signal sel inputted from outside. For instance, if the selection signal sel indicates a low level, the first multiplexer MUX 1  outputs the delayed signal xd 0 . If the selection signal sel indicates a high level, the first multiplexer MUX 1  outputs the delayed signal xd 1 .  
         [0039]     A first multiplier M 11  receives the signal outputted from the first multiplexer MUX 1  and an error signal ‘c’ and multiplies the two received signals together. An adder A 11  adds a signal outputted from the first multiplier M 11  to a previous coefficient outputted from a second multiplexer MUX 2 . A signal (coefficient) ‘c’ outputted from the adder A 11  includes the delayed signals xd 0  and xd 1 , the error signal ‘e’, and the previous coefficient.  
         [0040]     A fifth delayer D 15  stores the signal (coefficient) ‘c’ outputted from the first adder A 11  and outputs a signal c 0  delayed more than the signal ‘c’. The delayed signal c 0  includes the delayed signal xd 0 , the error signal ‘e’, and the previous coefficient. The fifth delayer D 15  outputs the signal c 0  by synchronization with a first clock signal clk 1 . In doing so, a phase of the first clock signal clk 1  is exactly opposite to that of the reference clock signal clk. Namely, the first clock signal clk 1  is delayed by ½ cycle more than the reference clock cycle clk. Hence, if the reference clock signal clk indicates high level, the first clock signal clk 1  becomes low level. If the reference clock signal clk indicates low level, the first clock signal clk 1  becomes high level.  
         [0041]     A sixth delayer D 16  receives the signal ‘c’ outputted from the first adder A 11  and outputs a signal c 1  delayed more than the received signal ‘c’. The sixth delayer D 16  outputs the delayed signal c 1  by synchronization with the reference clock signal clk. The delayed signal c 1  includes the delayed signal xd 1 , the error signal ‘e’, and the previous coefficient.  
         [0042]     A second multiplexer MUX 2  receives the two delayed signals c 0  and c 1 , i.e., a pair of new coefficients, from the fifth and sixth delayers D 15  and D 16 , respectively and then selectively outputs one of the delayed signals c 0  and c 1  according to a logic value or level of the selection signal sel inputted from outside. For instance, if the selection signal sel indicates a low level, the second multiplexer MUX 2  outputs the delayed signal c 0 . If the selection signal sel indicates a high level, the second multiplexer MUX 2  outputs the delayed signal c 1 .  
         [0043]     A third multiplexer MUX 3  receives the input signal x 0  and the delayed signal x 1  and selectively outputs one of the signals x 0  and x 1  according to a logic value or level of the selection signal sc 1  inputted from outside. For instance, if the selection signal sel indicates a low level, the third multiplexer MUX 3  outputs the input signal x 0 . If the selection signal sel indicates a high level, the third multiplexer MUX 3  outputs the delayed signal x 1 .  
         [0044]     A second multiplier M 12  receives signals outputted from the second and third multiplexers MUX 2  and MUX 3  and multiplies the two received signals together. A signal ‘y’ outputted from the second multiplier M 12  includes the new coefficients c 0  and c 1 , the input signal x 0 , and the delayed signal x 1 .  
         [0045]     A seventh delayer D 17  receives the signal ‘y’ outputted from the second multiplier M 12  and outputs a signal y 0  delayed more than the signal ‘y’ by synchronization with a second clock signal clk 2 . The second clock signal clk 2  is a clock delayed by ¼ cycle more than the reference clock cycle clk.  
         [0046]     A process of updating a coefficient in the LMS adaptive filter according to the present invention is explained as follows.  
         [0047]     If a logic value of the selection signal sel, as shown in  FIG. 4 , inputted to the first multiplexer MUX 1  is ‘ 1 ’, the first multiplexer MUX 1 y outputs the delayed signal xd 0 . The first multiplier M 11  multiplies the delayed signal xd 0  by the error signal ‘e’ to output ‘e × xd 0 ’. When the selection signal sel is inputted to the first multiplexer MUX 1 , the selection signal sel is inputted to the second multiplexer MUX 2  as well. Hence, the second multiplexer MUX 2  outputs the previous coefficient c 0 . The adder A 11  receives ‘e × xd 0 ’ from the first multiplier M 11  and the previous coefficient c 0  from the second multiplexer MUX 2 . And, the adder A 11  adds ‘e × xd 0 ’ to the previous coefficient c 0  to output the coefficient ‘c’. In this case, the coefficient ‘c’ is ‘c 0 +(e×xd 0 )’ 
         [0048]     If the logic value of the selection signal sel inputted to the first multiplexer MUX 1  is ‘1’, the first multiplexer MUX 1  outputs the delayed signal xd 1 . The first multiplier M 11  then multiplies the delayed signal xd 1  by the error signal ‘e’ to output ‘e × xd 1 ’. As the selection signal sel having the logic value ‘1’ is inputted to the second multiplexer MUX 2 , the second multiplexer MUX 2  outputs the previous coefficient c 1 . The adder A 11  receives ‘e × xd 1 ’ from the first multiplier M 11  and the previous coefficient c 1  from the second multiplexer MUX 2 . And, the adder A 11  adds ‘e × xd 1 ’ to the previous coefficient c 1  to output the coefficient ‘c’. In this case, the coefficicnt ‘c’ is ‘c 1 +(e×xd 1 )’.  
         [0049]     The fifth delayer D 15  receives the coefficient ‘c’ outputted from the adder A 11  and outputs the new coefficient c 0  at a rising edge of the first clock signal clk 1 . The new coefficient c 0  keeps being outputted until a next rising edge of the first clock signal clk 1 .  
         [0050]     The sixth delayer D 16  receives the coefficient ‘c’ outputted from the adder A 11  and outputs the new coefficient c 1  at a rising edge of the reference clock signal clk. The new coefficient c 1  keeps being outputted until a next rising edge of the reference clock signal clk.  
         [0051]     The second multiplexer MUX 2  outputs the new coefficient c 0  if the logic value of the selection signal sel is ‘0’. The second multiplexer MUX 2  outputs the new coefficient c 1  if the logic value of the selection signal sel is ‘1’. The third multiplexer MUX 3  outputs the input signal x 0  if the logic value of the selection signal sel is ‘0’. The third multiplexer MUX 3  outputs the delayed signal x 1  if the logic value of the selection signal sel is ‘1’.  
         [0052]     The second multiplier M 12  receives the signals outputted from the second and third multiplexers MUX 2  and MUX 3  and multiplies the two received signals together. For instance, if the logic value of the selection signal sc 1  is ‘0’, the second multiplier M 12  multiplies the new coefficient c 0  by the input signal x 0 . If the logic value of the selection signal sel is ‘1’, the second multiplier M 12  multiplies the new coefficient c 1  by the delayed signal x 1 . Hence, the second multiplier M 12 , as shown in  FIG. 5 , repeatedly outputs ‘c 0 ×x 0 ’ and ‘c 1 ×x 1 ’.  
         [0053]     And, the seventh delayer D 17  receives the signal ‘y’ outputted from the second multiplier M 12  and outputs ‘c 0 ×x 0 ’ at a rising edge of the second clock signal clk 2 . The signal y 0  outputted from the seventh delayer D 17  keeps being outputted until a next rising edge of the second clock signal clk 2 .  
         [0054]     Therefore, the LMS adaptive filter according to the present invention, as shown in  FIG. 5 , enables to simultaneously output the two signals ‘c 0 ×x 0 ’ and ‘c 1 ×x 1 ’ during a summation period of the reference clock signal.  
         [0055]     Second Embodiment  
         [0056]      FIG. 3  is a block diagram of an LMS adaptive filter according to a second embodiment of the present invention.  
         [0057]     Referring to  FIG. 3 , a first delayer D 21  receives an input signal x 0  and outputs a signal x 1  delayed by a prescribed time behind the input signal x 0 . A second delayer D 22  receives the delayed signal x 1  and outputs a signal x 2  delayed more than the delayed signal x 1 . The first and second delayers D 11  and D 12  are synchronized with a reference clock signal clk to output the delayed signals x 1  and x 2 , respectively.  
         [0058]     A first multiplexer MUX 11  receives the two delayed signals xd 0  and xd 1 . In this case, the delayed signals xd 0  and xd 1  are the signals x 1  and x 2  outputted from the first and second delayers D 21  and D 22 , respectively. The first multiplexer MUX 11  selectively outputs one of the delayed signals xd 0  and xd 1  according to a logic value or level of a selection signal sel inputted from outside.  
         [0059]     A first multiplier M 21  receives the signal outputted from the first multiplexer MUX 11  and an error signal ‘e’ and then multiplies the two received signals together. An adder A 21  adds a signal outputted from the first multiplier M 11  to a previous coefficient outputted from a second multiplexer MUX 12 . A signal (coefficient) ‘c’ outputted from the adder A 21  includes the delayed signals xd 0  and xd 1 , the error signal ‘e’, and the previous coefficient.  
         [0060]     A third delayer D 23  stores the signal (coefficient) ‘c’ outputted from the first adder A 21  and outputs a signal c 0  delayed more than the signal ‘c’. The delayed signal c 0  includes the delayed signal xd 0 , the error signal ‘c’, and the previous coefficient The third delayer D 23  outputs the signal c 0  by synchronization with a first clock signal clk 1 . In doing so, the first clock signal clk 1  is delayed by ½ cycle more than the reference clock cycle clk Hence, if the reference clock signal clk indicates high level, the first clock signal clk 1  becomes low level. If the reference clock signal clk indicates low level, the first clock signal clk 1  becomes high level.  
         [0061]     A fourth delayer D 24  receives the signal ‘c’ outputted from the first adder A 21  and outputs a signal c 1  delayed more than the received signal ‘c’. The fourth delayer D 24  outputs the delayed signal c 1  by synchronization with the reference clock signal clk. The delayed signal c 1  includes the delayed signal xd 1 , the error signal ‘e’, and the previous coefficient.  
         [0062]     A second multiplexer MUX 12  receives the two delayed signals c 0  and c 1 , i.e., a pair of new coefficients, from the third and fourth delayers D 23  and D 24 , respectively and then selectively outputs one of the delayed signals c 0  and c 1  according to a logic value or level of the selection signal sel.  
         [0063]     A third multiplexer MUX 13  receives the input signal x 0  and the delayed signal x 1  and then selectively outputs one of the signals x 0  and x 1  according to a logic value or level of the selection signal sel. For instance, if the selection signal sel indicates a low level, the third multiplexer MUX 13  outputs the input signal x 0 . If the selection signal sel indicates a high level, the third multiplexer MUX 3  outputs the delayed signal x 1 .  
         [0064]     A second multiplier M 22  receives signals outputted from the second and third multiplexers MUX 12  and MUX 13  and multiplies the two received signals together. A signal ‘y’ outputted from the second multiplier M 22  includes the new coefficients c 0  and c 1 , the input signal x 0 , and the delayed signal x 1 .  
         [0065]     A fifth delayer D 25  receives the signal ‘y’ outputted from the second multiplier M 22  and outputs a signal y 0  delayed more than the signal ‘y’ by synchronization with a second clock signal clk 2 . The second clock signal clk 2  is a clock delayed by ¼ cycle more than the reference clock cycle clk.  
         [0066]     Therefore, the LMS adaptive filter according to the present invention need not to be provided with the multipliers and adders as many as those of the related art filter, thereby decreasing in size 0.7 times less than that of the related art filter.  
         [0067]     Accordingly, the present invention reduces the number of the multipliers and adders for the coefficient update, thereby enabling to decrease the filter size up to about 30%.  
         [0068]     It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.