Abstract:
A charge-splitting device and method include a plurality of charge cells coupled to receive a charge in response to being simultaneously clocked into a charge receiving state by an applied clock signal. The received charge is split into predetermined charge portions among the plurality of charge cells in proportions dependent upon the total number of cells, their relative capacitance and the magnitude and timing of the applied clock signal. The charge portions are again split and selectively summed to obtain highly accurate charge splitting ratios.

Description:
This is a continuation of application Ser. No. 678,277, filed Apr. 19, 1976, now abandoned. 
    
    
     BACKGROUND AND SUMMARY 
     Shift registers constructed by serially coupling a plurality of charge cells in cascade to form an array are known in the art. Charge is typically transferred from cell to cell in the array in response to clock signals applied to cells of the array. 
     A received charge can be split among several cells by coupling a plurality of cells to receive the charge and simultaneously clocking selected cells into a charge receiving state. 
     With such an approach, the splitting ratio is influenced by the cell gate areas. If charge is to be split into two halves, for example, the charge receiving cells should have identical gate areas. Splitting inaccuracy results if the areas are mismatched. The split charges can be expressed as follows: 
     Charge in cell A = pQ =(Q/2)(1 - ε) 
     Charge in cell B = rQ = (Q/2)(1 + ε), 
     where ε represents a splitting error caused, for example, by layout or processing. 
     An improved charge splitting device made in accordance with the invention brings a quantity of charge Q into a splitting cell and splits the charge Q into two charge portions pQ and rQ, p and Q being splitting coefficients where p = 1/2(1 - ε) and r = 1/2(1 + ε ), ε being the error in charge splitting. The charge portion rQ is stored and the charge portion pQ is again divided by splitting cell into charge portions p 2  Q and prQ. The charge portion prQ is equal to (Q/4)(1 - ε 2 ). The charge portions p 2  Q and r 2  Q are summed to produce the quantity (Q/2)(1 + ε 2 ). The charge portions (Q/4)(1 - ε 2 ) and (Q/2)(1 + ε 2 ) are more highly accurate representations of Q/4 and Q/2 than representations heretofore available by devices having an ε &lt; 1. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a drawing of a cross section of a conventional Charge Coupled Device shift register having a linear row of charge-coupled cells. 
     FIG. 2 is a diagrammatic top view of the charge-coupled device shift register of FIG. 1. 
     FIG. 3 is a diagrammatic top view of a charge-branching cell in combination with two shift registers. 
     FIG. 4 is a diagrammatic top view of a charge-summing cell in combination with two shift registers. 
     FIG. 5 is a timing diagram of clock pulse signals φ 1  φ 2 . 
     FIG. 6 is a diagrammatic top view of a charge-splitting cell in combination with two shift registers. 
     FIG. 7 is a diagrammatic top view of an improved charge splitting cell made in accordance with the invention. 
     FIG. 8 is a timing diagram illustrating appropriate clock signals for use with the embodiment depicted in FIG. 7. 
     FIG. 9 is a digital to analog converter utilizing charge splitting cells constructed as shown in FIG. 7. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIGS. 1 and 2, a conventional Charge Coupled Device (CCD hereinafter) shift register is shown. The register depicted is, for example, a two-phase device having directionality of charge transfer as described for example by J. E. Carnes and W. F. Kosonocky in the Apr. 1974 issue of Solid State Technology at pages 67-77 comprising a plurality of charge-coupled cells 12, 14 and 16 operated by a two-phase clock producing clock pulse signal φ 1  and φ 2 . The CCD shift register is typically constructed of a silicon substrate 2 doped with a p-type impurity. The silicon substrate is covered by a first layer 4 of S i  O 2 . On top of the S i  O 2  layer are deposited first gate electrodes 6 of, for example, polysilicon, and second gate electrodes 8 of, for example, aluminum, isolated from each other by a second layer 10 of S i  O 2 . The second gate electrodes overlap the gaps between the first gate electrodes. Adjacent first and second electrodes are interconnected as shown and the interconnections are alternately coupled to receive clock phase signals φ 1  and φ 2 . FIG. 2 illustrates charge transfer cells 12, 14 and 16 formed thereby. 
     Referring to FIG. 3, a diagrammatic top view of a charge-branching cell in combination with two CCD shift registers is shown. Conventional CCD cells 18, 20, 22 and 24 are coupled in cascade in a first linear array similar to known CCD shift registers. The charge-branching cell comprises cells 20, 22 and 26. Conventional CCD cells 26, 28 and 30 are coupled in cascade in a second linear array similar to known CCD shift registers. Cell 20, however, is coupled to two adjacent cells 22 and 26, cell 22 being in the first array and cell 26 being in the second array. Gate electrodes of cells 18, 20, 24, 28 and 30 are connected to receive clock pulses φ 1  and φ 2  as in the conventional shift registers illustrated in FIGS. 1 and 2. Cells 22 and 26 have their first and second gate electrodes coupled to receive one of two conditional clock pulses. Aφ 1  and Aφ 1  by means of logic 32 and 34, respectively. Aφ 1  is, for example, representative of a logic AND function of the logic variable A with the phase signal φ.sub. 1. Similarly, Aφ 1  is, for example, representative of a logic AND function of the logic variable A with the phase signal φ 1 . Copending U.S. patent applications entitled &#34;Charge Coupled Analog to Digital Converter&#34; and Ser. No. 677,944, now abandoned, and &#34;Charge Coupled Digital to Analog Converter&#34; Ser. No. 677,955, now allowed by Thomas Hornak describe suitable logic and said patent applications are hereby fully incorporated by reference. For A = logic zero, the conditional clock phase signal Aφ 1  is zero and no clock phase φ 1  pulses are applied to the gate electrodes of cell 22. Since A = logic zero, A = logic one and cell 26 does receive clock phase signal φ 1 . The charge residing in cell 20 will therefore be clocked into cell 26. No charge will enter cell 22 as long as its first and second gates are kept at zero voltage. Further clock pulses φ 1  and φ 2  propagate charge from cell 26 down the array formed by cells 28 and 30. 
     For A = logic one and A = logic zero, cell 26 has a zero gate voltage and will not receive any charge from cell 20. The gates of cell 22 will, however, be clocked positively by clock pulses φ 1  and cell 22 will receive charge from cell 20. Charge 36 applied to the left of the first linear array in FIG. 3 is selectively branched to the second linear array or to the first linear array by application of the logic variables A and A. 
     The charge-branching cell comprising cells 20, 22 and 26 thereby provides selective branching of charge. Although branching to only two arrays has been described, extension to a larger plurality of branching is possible. 
     Referring to FIG. 4, a diagrammatic top view of a charge-summing cell is shown. CCD cells 38, 40 and 42 are coupled in cascade in a first linear array similar to that of a conventional CCD shift register. Similarly, CCD cells 44, 46, 48 and 50 are coupled in cascade and form a second array. Cell 46 is coupled to receive charge from cell 42 in the first array and from cell 44 in the second array. Referring to FIG. 5, timing diagrams for clock pulses φ 1  and φ 2  are shown which can be used for the devices illustrated in FIGS. 1 through 4. With reference to FIG. 4, assume that at time t 3  indicated in FIG. 5 cells 42 and 44 are each holding charge and that the gate electrodes of cell 46 are at zero volts. At time t 4  the three gate electrodes of cell 46 are driven positive by clock pulse signal φ 1 , with cell 46 still not containing charge. Between time t 4  and t 5  clock pulse signal φ 2  goes to zero volts while clock pulse signal φ 1  remains high. The charges from cells 42 and 44 are both transferred into cell 46 and thereby summed in cell 46. The summed charge is then clocked into cell 48 when clock signal φ 1  goes to zero volts between times t 6  and t 7  shown in FIG. 5. Although a charge-summing cell is described for summing charge from two sources, extension to larger pluralities is within the scope of the invention. 
     Referring to FIG. 6, a charge-splitting cell is shown in combination with two CCD shift registers. The charge-splitting cell comprises CCD cells 58, 60 and 64. A first CCD shift register comprises cells 52, 54, 56 and 68 are coupled in cascade, a second shift register comprises cells 60 and 62, coupled in cascade, and a third shift register comprises cells 64 and 66. Cell 58 receives charge from cell 56. The charge residing in cell 58 at time t 1  indicated in FIG. 5 is transferred to cells 60 and 64 between times t 2  and t 3  in response to cells 60 and 64 being simultaneously clocked into a charge receiving state by clock pulse signal φ 2 . The distribution of charge between cells 60 and 64 is proportional among other things to the gate area ratios of cells 60 and 64. If, for example, cells 60 and 64 are substantially identical, the charge will be equally split between cells 60 and 64. 
     Different splitting ratios can be achieved by coupling a greater plurality of cells to cell 58, for example, three identical cells provide a splitting ratio of 1/3. Variations can be achieved by varying cell gate area size in combination with varying the plurality and also by cascading charge-splitting cells as described in referenced and fully incorporated copending applications entitled &#34;Charge Coupled Analog to Digital Converter&#34; and &#34;Charge Coupled Digital to Analog Converter&#34; by Thomas Hornak. 
     Referring to FIG. 7, an improved charge splitting device is shown. A charge Q to be split is applied to cell 70. The charge Q is transferred to cell 73 and from there split into cells 74 and 78 as two portions, the first portion being pQ, p equal to a quantity 1/2(1 - ε), and the second portion being rQ, r equal to a quantity 1/2(1 + ε), and ε being representative of proportional splitting error due to masking or processing errors and the like. The charge portion pQ is transferred from cell 74 to cell 80 and the charge portion rQ is transferred from cell 78 to cell 73 and split into cells 74 and 78 as charge portions r 2  Q and prQ, respectively; the charge portion pQ is recalled from cell 80 and split into a second charge portion prQ and a charge portion p 2  Q by cells 73, 74, 78, and the charge portions p 2  Q and r 2  Q summed in cell 82 to produce the charge portion (Q/2)(1 + ε 2 ) as described more fully below. 
     Referring to the timing diagram shown in FIG. 8 and the diagram of the preferred embodiment depicted in FIG. 7, at time t 1  the charge Q is underneath gate φ 1 . 
     At t 2  gate φ 3  is ready to accept charge Q but charge Q is still confined under gate φ 1 . 
     At t 3  charge Q is transferred from underneath gate φ 1  to underneath gate φ 3 . 
     At t 4  gates φ 5  and φ 9  are ready to accept charge but charge Q is still confined under gate φ 3 . 
     At t 5  a charge portion pQ equal to (Q/2)(1 - ε) is transferred from gate φ 3  of cell 73 to gate φ 5  of cell 74 and a charge portion rQ equal to (Q/2(1 + ε) is transferred from gate φ 3  of cell 73 to gate φ 9  of cell 78. 
     At t 6  gate φ 7  of cell 80 is ready to accept charge from gate φ 5  of cell 74 and gate φ 3  of cell 73 is ready to accept charge from gate φ 9  of cell 78. 
     At t 7  charge portion pQ is transferred from cell 74 to cell 80 and charge portion rQ is transferred from cell 78 to cell 73. 
     At t 8  gate φ 5  of cell 74 and gate φ 9  of cell 78 are ready to accept charge from gate φ 3  of cell 73 but charge portions pQ and rQ are still underneath gates φ 7  and φ 3 . 
     At t 9  charge portion rQ is split into charge portions r 2  Q underneath gate φ 9  of cell 78 and the first charge portion prQ underneath gate φ 5  of cell 74. 
     At t 10  gate φ 13  of cell 84 and gate φ 11  of cell 82 are ready to accept the first charge portion prQ from gate φ 5  of cell 74 and charge portion r 2  Q from gate φ 9  of cell 78, respectively. The first charge portion prQ is stored underneath gate φ 5 , R 2  Q is stored underneath gate φ 9  and pQ is stored underneath gate φ 7 . 
     At t 11  the first portion prQ equal to (Q/4)(1 - ε 2 ) is transferred from gate φ 5  of cell 74 to gate φ 13  of cell 84 and made available as a first output 90. Charge portion r 2  Q is transferred from gate φ 9  of cell 78 to gate φ 11  of cell 82. Charge portion pQ is still stored under φ 7 . 
     At t 12  gate φ 5  of cell 74 is ready to accept charge portion pQ from gate φ 7  of cell 80 and the first charge portion prQ and charge portion  2  Q are still stored under gates φ 13  and φ 11 . 
     At t 13  charge portion pQ is transferred from under gate φ 7  of cell 80 to under gate φ 5  of cell 74. 
     At t 14  gate φ 3  of cell 73 is ready to accept charge from gate φ 5  of cell 74. 
     At t 15  charge portion pQ is transferred from gate φ 5  of cell 74 to gate φ 3  of cell 73. 
     At t 16  gates φ 5  of cell 74 and φ 9  of cell 78 are ready to accept charge from gate φ 3  of cell 73. 
     At t 17  charge portion pQ is split into charge portions p 2  Q and a second prQ, p 2  Q being underneath gate φ 5  of cell 74, the second prQ underneath gate φ 9  of cell 78. The first charge portion prQ is still stored under gate φ 13  and charge portion r 2  Q is still stored under gate φ 11  (see t 11 ). 
     At t 18  gate φ 15  of cell 86 is ready to accept prQ from gate φ 9  of cell 78 and gate φ 3  of cell 73 is ready to accept p 2  Q from gate φ 5  of cell 74. 
     At t 19  the second charge portion prQ equal to (Q/4)(1 - ε 2 ) is transferred from gate φ 9  of cell 78 to gate φ 15  of cell 86 and is available as a second output 92. Charge portion p 2  Q is transferred from gate φ 5  of cell 74 to gate φ 3  of cell 73. 
     At t 20  gate φ 9  of cell 78 is ready to accept charge portion p 2  Q from gate φ 3  of cell 73. 
     At t 21  charge portion p 2  Q is transferred from under gate φ 3  of cell 73 to under gate φ 9  of cell 78. Gate φ 1  of cell 70 can now accept a new charge to be split. 
     At t 22  gate φ 11  of cell 82 is still storing charge portion r 2  Q (since t 11 ) and is now ready to accept in addition charge portion p 2  Q from gate φ 9  of cell 78. Gate φ 3  of cell 73 is ready to accept a new charge from gate φ 1  of cell 70. 
     At time t 23  charge portion p 2  Q is transferred from underneath gate φ 9  of cell 78 to underneath gate φ 11  of cell 82 where it is summed with charge portion r 2  Q. The sum equals (Q/4)(1 - ε) 2  + (Q/4)(1 + ε) 2  = (Q/2)(1 + ε 2 ) and is available as a third output 94. If ε is less than one, the charge portions available as outputs 90, 92 and 94 are therefore more accurate representations of Q/4, Q/4, and Q/2, respectively: (Q/4)(1 - ε 2 ), (Q/4)(1 - ε 2 ) and (Q/2)(1 + ε 2 ), than can be obtained from a given splitting cell. 
     Referring to FIG. 9, a digital to analog converter utilizing the embodiment of FIG. 7 in the manner taught by the copending patent application titled &#34;Charge Coupled Digital to Analog Converter&#34; by Thomas Hornak is shown.