Abstract:
A semiconductor integrated circuit device is comprised of: an internal voltage step-down power supply circuit having a first area generating a predetermined internal power supply voltage and a second area wherein an internal power supply voltage is increased at a predetermined rate in accordance with a rise in an external power supply voltage; an internal circuit operated from an internal power supply generated in the first area of the power supply circuit; a first amplifier which is operated from the internal power supply and receives and amplifies data read from a memory cell; a second amplifier which is operated from an external power supply, and receives and amplifies data of an internal power supply voltage level output from the first amplifier, then converts it to data of an external power supply voltage level; and an output driver which is operated from the external power supply and outputs the data of the external power supply voltage level.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a configuration of an output data voltage level conversion circuit in a semiconductor memory circuit device wherein an internal circuit is driven by an internal power supply, while an output driver is driven by an external power supply.  
           [0003]    2. Description of the Related Art  
           [0004]    In recent years, increasing miniaturization in design standards has brought a tendency toward decreasing a withstand voltage of a memory cell in a semiconductor circuit device. Therefore, in a general semiconductor memory device, an internal circuit is driven by an internal power supply (IVCC: Internal VCC) having the voltage thereof reduced to a lower voltage than an external power supply (EVCC: External VCC), and an output driver is driven by the external power supply EVCC. In such a semiconductor memory circuit device, the output driver and other internal circuits use power supplies of different voltages; therefore, it is necessary to convert data voltage levels from internal power supply voltage levels to external power supply voltage levels before transferring read data from an internal circuit to an output driver. Conversion of data voltage levels is performed by, for example, using a level shifter circuit.  
           [0005]    The conventional semiconductor memory circuit device, however, converts a data voltage level from an internal power supply level to an external power supply level by using a level shifter circuit provided in a stage before the stage for transferring read data from an internal circuit to an output driver as described above. This results in a data access delay due to multiple stages of the level shifter circuit and a specific operation of the level shifter circuit. The access delay caused by the specific operation of the level shifter circuit may be improved by increasing the current. However, this may lead to a further disadvantage of an increase in current drain, or generation of unexpected noises.  
           [0006]    Furthermore, in order to cope with the increasingly accelerating tendency toward higher integration of semiconductor memory circuit devices, it is highly expected to achieve a semiconductor memory circuit configuration obviating the need of a level shifter circuit provided in a stage preceding the output driver, thus rendering another advantage of reserving extra space on a chip.  
         SUMMARY OF THE INVENTION  
         [0007]    An object of the invention is to provide a semiconductor memory circuit configuration eliminating a level shifter circuit which is conventionally provided in a stage immediately before an output driver.  
           [0008]    To this end, accordinng to the present invention, there is provided a semiconductor integrated circuit device composed of: an internal voltage step-down power supply circuit having a first area generating a predetermined internal power supply voltage and a second area wherein an internal power supply voltage is increased at a predetermined rate in accordance with a rise in an external power supply voltage; an internal circuit operated from an internal power supply generated in the first area of the power supply circuit; a first amplifier which is operated from the internal power supply and receives and amplifies data read from a memory cell; a second amplifier which is operated from an external power supply and receives and amplifies data of an internal power supply voltage level output from the first amplifier, then converts it to data of an external power supply voltage level; and an output driver which is operated from the external power supply and outputs the data of the external power supply voltage level. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects, features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:  
         [0010]    [0010]FIG. 1 is a circuit diagram showing a first embodiment according to the present invention.  
         [0011]    [0011]FIG. 2 is a timing chart showing the operation of the first embodiment according to the present invention.  
         [0012]    [0012]FIG. 3 is a circuit diagram showing a second embodiment according to the present invention.  
         [0013]    [0013]FIG. 4 is a timing chart showing the operation of the second embodiment according to the present invention.  
         [0014]    [0014]FIG. 5 is a circuit diagram showing a third embodiment according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]    First Embodiment  
         [0016]    [0016]FIG. 1 is a circuit diagram showing a first embodiment according to the present invention. FIG. 2 is a timing chart showing the operation according to the first embodiment. The semiconductor memory circuit shown in FIG. 1 includes a current mirror type amplifier  2  which amplifies the data read onto a data bus  1  from a memory cell by selecting a column line (not shown), a differential amplifier  3  further amplifying the data output from the current mirror type amplifier  2 , a data latch circuit  4  latching the data output from the differential amplifier  3  in accordance with a data latch signal DATAL, and an output driver  5  outputting the data output from the data latch circuit  4  to an external source.  
         [0017]    The current mirror type amplifier  2  uses an internal power supply IVCC as its power supply, and amplifies the data appearing at nodes n 1  and n 1 B on the data bus  1  in accordance with a read amplifier active signal RAC. A differential amplifier  3  includes four PMOS transistors P 1  through P 4 , three NMOS transistors N 1  through N 3 , and two inverters of M 1  and M 2 . The differential amplifier  3  while using an external power supply EVCC as its power supply, amplifies the data appearing at output nodes n 2  and n 2 B on the current mirror type amplifier  2  according to a row address enable signal RAE. Since the power supply used by the differential amplifier  3  is an external power supply EVCC, the data potential levels at output nodes n 4  and n 4 B of the differential amplifier  3  have been converted into signals with external power supply voltage levels (EVCC levels).  
         [0018]    An external power supply voltage level EVCC is used for the “High” level of the read amplifier active signal RAC, the row address enable signal RAE, and the data latch signal DATAL. The row address enable signal RAE is a signal composed of a read amplifier active signal RAC that has been delayed by using two stages of inverters M 3  and M 4 .  
         [0019]    The operation will now be described. The data on the data bus  1  is amplified upon a change in the level of the read amplifier active signal RAC from “Low” to “High”. At this time, the output nodes n 2  and n 2 B of the current mirror type amplifier  2  start to diverge to the “High” and “Low” levels. The data appearing at the output nodes n 2  and n 2 B is further amplified by the differential amplifier  3  in the following stage upon a change in the level of the row address enable signal RAE from “Low” to “High”, and output from an inverter M 2 . In the data latch circuit  4  provided in the subsequent stage, the data appearing at the output node  4 n of the differential amplifier  3  is latched upon a change in the level of the data latch signal DATAL, which is a one-shot pulse signal, from “Low” to “High”. The output data from the data latch circuit  4  is then supplied to an external source from the output driver  5  in the subsequent stage.  
         [0020]    According to this embodiment, the internal power supply IVCC is used for the current mirror type amplifier  2  in the first stage, and an external power supply EVCC is used for the differential amplifier  3  in the subsequent stage, realizing a semiconductor memory circuit device configuration wherein a level shifter circuit, which is conventionally provided in the stage preceding the output driver, is eliminated. Thus, data can be accessed at a higher speed in a semiconductor memory circuit.  
         [0021]    Second Embodiment  
         [0022]    [0022]FIG. 3 is a circuit diagram showing a second embodiment of the present invention. The second embodiment is different from the first embodiment in that an NMOS transistor N 3  configuring a differential amplifier  13  on the side of a ground voltage VSS is divided into N 4  and N 5 , and a control circuit  16  is provided which inputs a signal based on an output from the differential amplifier  13  to a control gate of an NMOS transistor N 4  and a row address enable signal RAE to a control gate of the NMOS transistor N 5 . This control circuit  16  controls switching between conduction and non-conduction of the NMOS transistors N 4  and N 5 . In this embodiment, an example where NMOS transistor N 3  is divided into two is described. The division of the transistor, however, is not limited to two; the transistor may be dividied into three or more.  
         [0023]    The semiconductor memory circuit according to this embodiment has the same configuration as shown in FIG. 1 and described in the first embodiment, except that a control circuit  16  is connected to the differential amplifier  13 . Therefore, the same numerals will be used, and the description thereof will be omitted. The differential amplifier  13  includes four PMOS transistors of P 1  through P 4 , four NMOS transistors of N 1 , N 2 , N 4  and N 5 , and two inverters of Ml and M 2 . The differential amplifier  13  uses an external power supply EVCC as its power supply, and amplifies the data appearing at output nodes n 2  and n 2 B of the current mirror type amplifier  2  in accordance with a row address enable signal RAE. Since the power supply used by the differential amplifier  13  is an external power supply EVCC, the data potential levels at output nodes n 4  and n 6  of the differential amplifier  13  have been converted into external power supply voltage levels (EVCC levels).  
         [0024]    The control circuit  16  includes two stages of inverters of M 3  and M 4  to generate a row address enable signal RAE from a read amplifier active signal RAC and output the generated signal, and a three-input NOR circuit M 5  using two signals appearing at the two output nodes n 4  and n 6  of the differential amplifier  13  and a signal appearing at an output node n 7  of the inverter M 3  as its inputs. The output side of the three-input NOR circuit M 5  is connected to the control gate of the NMOS transistor N 4 , and the output side of the inverter M 4  (row address enable signal RAE) is connected to the control gate of the NMOS transistor N 5 .  
         [0025]    The operation according to the second embodiment will now be described. The operation already described in the first embodiment will not be repeated herein; the operation of the differential amplifier  13  which is a constituent characterizing the second embodiment will be described. FIG. 4 is a timing chart showing the operation of the second embodiment according to the present invention. When a read amplifier active signal RAC is at the “Low” level (when the differential amplifier  13  is not in operation), an output node n 8  of the three input NOR circuit M 5  goes to the “Low” level since an output node n 7  of the inverter M 3  is at the “High” level. Thus, the NMOS transistors of N 4  and N 5  are both turned off. On the other hand, when a read amplifier active signal RAC is at the “High” level (when the differential amplifier  13  is in operation), the output node n 8  of the three-input NOR circuit M 5  goes to the “High” level since the output node n 7  of the inverter M 3  is at the “Low” level, and the output nodes n 4  and n 6  are at the “low” level when starting the operation of the differential amplifier  13 . At this time, since the row address enable signal RAE is also at the “High” level, both the NMOS transistors N 4  and N 5  both turn on.  
         [0026]    Then, either of the output nodes of n 4  or n 6  goes to the “high” level upon amplification of data by the differential amplifier  13 . As a result, the level of the output node n 8  of the three-input NOR circuit M 5  switches from “High” to “Low”, so that the NMOS transistor N 4  goes off. The read amplifier active signal RAC goes to the “Low” level, and the NMOS transistor N 4  is reset once and maintained in the off state until the read amplifier active signal RAC goes to the “High” level again.  
         [0027]    As in the case of the first embodiment, the “High” levels in the read amplifier active signal RAC, the row address enable signal RAE, and the data latch signal DATAL used in this embodiment all employ the external power supply voltage level (EVCC level).  
         [0028]    With this embodiment, a faster data access operation of a semiconductor memory circuit can be achieved, and the current drain of the differential amplifier  13  can be reduced at the point when the output data of the differential amplifier  13  is fixed, as in the case of the first embodiment. This advantage can be understood from FIG. 4. FIG. 4 shows that an active period B of the differential amplifier  13  according to this embodiment is reduced, compared with an active period A of a conventional amplifier. This shortened active period of the differential amplifier has achieved reduced current drain. Furthermore, no incorrect operation due to noise or the like will occur, since the differential amplifier  13  is not completely turned off, i.e., no internal node of the differential amplifier  13  is placed in a floating state.  
         [0029]    Third Embodiment  
         [0030]    [0030]FIG. 5 is a circuit diagram showing a third embodiment according to the present invention. The third embodiment is different from the first embodiment in that NMOS transistors N 6  and N 7  are connected in parallel to the ground voltage VSS of a differential amplifier  23 , and that a control circuit  26  is provided which inputs a signal based on a burn in signal BI to a control gate of an NMOS transistor N 6  and inputs a row address enable signal RAE to the control gate of an NMOS transistor N 7 . This control circuit  26  controls switching between conduction and non-conduction of the NMOS transistors N 6  and N 7 . In this embodiment, an example wherein two NMOS transistors are connected in parallel to a ground voltage VSS is described. The number of NMOS transistors, however, is not limited to two; three or more NMOS transistors may be connected in parallel.  
         [0031]    The semiconductor memory circuit according to this embodiment has the same configuration as that shown in FIG. 1 for the first embodiment except that a control circuit  26  is connected to the differential amplifier  23 ; therefore, the same numerals will be used and the description thereof will not be repeated. The differential amplifier  23  has four PMOS transistors P 1  through P 4 , four NMOS transistors N 1 , N 2 , N 6  and N 7 , and two inverters M 1  and M 2 . The differential amplifier  23  uses an external power supply EVCC as the power supply therefor, and amplifies the data appearing at output nodes n 2  and n 2 B of the current mirror type amplifier  2  in accordance with a row address enable signal RAE. As the power supply used by the differential amplifier  13  is the external power supply EVCC, the data of the potential levels at output nodes n 4  and n 6  of the differential amplifier  13  has been converted to the external power supply voltage level (EVCC level) signals.  
         [0032]    The control circuit  26  is composed of two stages of inverters M 3  and M 4  which generate a row address enable signal RAE from a read amplifier active signal RAC and output the generated signal, and a two-input NOR circuit M 6  using a burn in signal BI and a signal appearing at the output node n 6  of the inverter M 3  as its inputs. The output side of the two-input NOR circuit M 6  is connected to the control gate of NMOS transistor N 6 , and the output side of the inverter M 4  (a row address enable signal RAE) is connected to the control gate of the NMOS transistor N 7 .  
         [0033]    The operation according to the second embodiment will be described now. The operation already described in the first embodiment will be omitted; the operation of the differential amplifier  23  in a burn in test, which is a characteristic of the second embodiment, will be described. In a burn in test, a burn in signal BI switches from the “Low” level to the “High” level, causing the output node n 7  of the two-input NOR circuit M 6  to be switched to the “Low” level. As a result, the NMOS transistor N 6  goes off to prevent current from flowing, which reduces the current passing through the differential amplifier  23 , and the differential amplifier  23  operates slower than in normal operation. The burn in test is a type of acceleration test for a semiconductor device, wherein a device is operated with a relatively loose cycle under a high temperature and high voltage environment.  
         [0034]    With this embodiment, like the first embodiment, a higher data access operation of a semiconductor memory circuit can be achieved, while a slower operation of the differential amplifier  23  than in the normal operation thereof is allowed since the current passing through the differential amplifier  23  is reduced. This permits a suppressed rise of a peak current caused by high voltage, thus preventing malfunctions of a memory circuit due to power supply noises during a burn in test.  
         [0035]    As in the first and the second embodiments, the external power supply voltage level (EVCC level) is used for the “High” level of all the read amplifier active signal RAC, the row address enable signal RAE, and the data latch signal DATAL in this embodiment. The external power supply voltage level (EVCC level) is also used for the “High” level of the burn in signal BI.  
         [0036]    As described above in detail, the present invention allows the implementation of a semiconductor memory circuit device configuration that obviates the need of a level shifter circuit conventionally provided in a stage preceding an output driver. Thus, a faster data access operation in a memory circuit can be implemented, and the absence of a level shifter circuit provides an extra space on a chip. According to another aspect of the present invention, current drain can be reduced and malfuctions due to noises can be prevented.