Abstract:
Current limiting using capacitor charge measurement to limit the supply current or load current of a circuit, or the current flowing through a device or switch, to prevent the time average current in the switch from exceeding a certain safe level. A replica circuit is used to provide a scaled version of the current in the main switch. The current output of the replica circuit is used to charge a capacitor during the first period of the clock signal so that the capacitor voltage, at any time during the on time, is proportional to the time integral of the current output of the replica circuit, and thus, the time integral of the current in the main circuit. The capacitor voltage, in turn, is compared with a known voltage to determine whether the charge that has flowed through the main switch has exceeded a predetermined maximum. The output of the comparator may be used in various ways, including as a control of the clock duty cycle to limit the on time of the main switch. Various embodiments are disclosed.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of current limiting circuits. 
     2. Prior Art 
     Current limiting circuits of various types are well known in the prior art. Such circuits are commonly used to limit the maximum current delivered to a circuit or through a circuit component to avoid excessive heating in the circuit or circuit component and/or an excessive load and/or overheating in the power supply itself. Of particular importance to the present invention, however, are circuits using clocked switches, such as various types of voltage converters. 
     In the case of switching converters using inductors, energy from a power supply is alternately stored in an inductor and then delivered to the output of the converter. In the case of the energy storage cycle, the current in the inductor will increase at a rate equal to the voltage applied across the inductor divided by the inductance of the inductor. The peak current must be limited, however, to avoid saturation of the inductor, as once the inductor saturates, the inductance drops drastically, resulting in high current spikes, excessive heating of the associated components, high loads on the power supply, etc. In the prior art, a sense resistor is commonly used in series with the inductor, with the voltage drop across the sense resistor being used to limit the current through the inductor. As shall subsequently be seen, the present invention offers an alternative to the use of the sense resistor, particularly in integrated switching converters which include the main switching transistor as part of the integrated circuit. 
     In the case of charge pump converters and inverters, the switch currents have different characteristics. By way of example, in the case of a voltage doubler, a capacitor is first switched across the input to the doubler to charge the capacitor to the input voltage. The capacitor is then switched so that the capacitor lead previously connected to the low side of the input is now connected to the high side of the input, so that the second lead of the capacitor providing the output of the doubler is now at twice the voltage of the doubler input. 
     A voltage inverter is similar in operation to a voltage doubler, though is different in the capacitor connection during the second phase of operation. A schematic representation of such a voltage inverter may be seen in FIG. 1, which is representative of such devices as the MAX828/MAX829 devices, manufactured by Maxim Integrated Products, Inc., assignee in the present invention. As with a voltage doubler, during the first phase of operation the capacitor C 1  is connected between the input voltage V IN  and ground by closing switches S 1  and S 3  to charge capacitor C 1  to the input voltage. Then switches S 1  and S 3  are opened and switches S 2  and S 4  are closed, connecting the side of the capacitor that was originally connected to the input to the circuit ground, so that the opposite side of the capacitor originally connected to circuit ground will be at the voltage −V IN . Capacitor C 2  provides smoothing and charge storage for the output voltage, with inverter I 1  providing the alternate switch closings in response to a clock signal. In that regard, the alternate switch closed waveforms are non-overlapping to avoid momentary shorting of the input or the output to ground. 
     In the case of a charge pump voltage inverter illustrated in FIG. 1, switches S 3  and/or S 4  may be diodes rather than switches. Similarly, in a voltage doubler, two of the four devices may be diodes rather than switches, diodes simplifying the circuits but increasing the power dissipation and decreasing the voltage (positive or negative) obtained. In that regard, all four devices are rectifying devices in the sense that current only flows through each device in one direction, though two of the four devices must also at times be blocking devices, even though the same remain forward biased. Thus two of the four rectifying devices can be diodes, though the other two devices must have a switching capability. Of course, voltage doublers and inverters are merely exemplary of the many various circuits in which charge pumps are used, many charge pump circuits being used to obtain different voltages, both higher and lower, than merely doubling or inverting a supply voltage. 
     In the case of a charge pump circuit such as a voltage doubler or voltage inverter, the output of the circuit will have a finite impedance dependent upon the effective resistance of the pumping or fly capacitor, the resistance of the switches and the inverse of the product of the clock frequency and capacitance of the fly capacitor. In essence, the capacitor pumps a charge to the output on each clock cycle to provide the load current until the next clock cycle. Consequently, the fly capacitor (capacitor C 1  of FIG. 1) must be sufficiently large for a given clock frequency to deliver the required charge to the output on each cycle without an excessive voltage drop on the capacitor during the second phase of operation of the circuit when the capacitor is coupled to the output. By way of example, assume a 5 volt inverter is to provide a −5 volt output with a 100 millivolt droop in the output due to the output load (−4.9 volts out). During start-up, however, when the output capacitor (capacitor C 2  of FIG. 1) is discharged, capacitor C 1  will be nearly fully discharged on each of the first few cycles of operation, resulting in switch currents which are approaching 50 times the current required for steady state operation. In the case of a fault condition wherein the output of the circuit is shorted, these extraordinary switch currents may persist indefinitely. While on start-up, switch resistances will limit the peak current and the short time required for start-up will limit the total energy dissipated in the switches and power supply, a short circuit condition for any length of time can cause excessive heating in switches, leading to possible failure of the circuit, as well as drawing excessive power from the power supply. 
     BRIEF SUMMARY OF THE INVENTION 
     Current limiting using capacitor charge measurement to limit the supply current or load current of a circuit, or the current flowing through a device or switch, to prevent the time average current in the switch from exceeding a certain safe level. A replica circuit is used to provide a scaled version of the current in the main switch. The current output of the replica circuit is used to charge a capacitor during the first period of the clock signal so that the capacitor voltage, at any time during the on time, is proportional to the time integral of the current output of the replica circuit, and thus, the time integral of the current in the main circuit. The capacitor voltage, in turn, is compared with a known voltage to determine whether the charge that has flowed through the main switch has exceeded a predetermined maximum. The output of the comparator may be used in various ways, including as a control of the clock duty cycle to limit the on time of the main switch. Various embodiments are disclosed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a switched capacitor voltage inverter. 
     FIG. 2 a  is a block diagram of an exemplary embodiment of the present invention current limiter. 
     FIG. 2 b  presents waveforms for the clock signal CLK and reset signal Reset for normal operation and for operation with an overload. 
     FIG. 3 is an exemplary circuit diagram for an embodiment in accordance with FIGS. 2 a  and  2   b.    
     FIG. 4 is an exemplary diagram illustrating the use of a sense resistor in the generation of a replica current. 
     FIG. 5 is a schematic diagram illustrating the use of the embodiment of the present invention current limiter of FIG. 2 in a switched capacitor voltage inverter like that of FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention comprises a method and apparatus for current limiting in clocked switches, such as are used in charge pump circuits to avoid excessive power dissipation in the charge pump circuit and excessive load on the power supply. As shall subsequently be seen, current limiting is achieved not by limiting maximum current, but by limiting the time that the high currents can flow. This assures adequate current flow during circuit start-up and after short circuit conditions to assure timely recovery of the circuit output, when the short circuit is removed. At the same time, this limits power dissipation in the relevant switch, as well as any companion switches, or other circuit elements conducting the same or a related current, and of course also limits the power required from the power supply under extraordinary operating conditions. 
     Now referring to FIG. 2 a,  a block diagram of one embodiment of the present invention may be seen. The specific block diagram shown in FIG. 2 a  applies to current limiting for a switch coupled to the positive power supply input, such as by way of example, switch S 1  in FIG. 1 (see, for example, FIG.  5 ). However, the principles illustrated by the Figure and the description thereof could readily be applied to other switches, such as by way of example, switch S 3  of FIG. 1, by effectively inverting FIG. 2 a.  As shown in that Figure, the main device S 1  is coupled between the input voltage V IN  and the switch output I OUT , with the control line for the main device being clocked by the clock signal CLK. In the specific embodiment to be subsequently described, the main device is a p-channel transistor, though other types of transistors, such as a pnp transistor, may also be used. Because the main device in the exemplary embodiment is a p-channel device, the main device will be on when the clock signal CLK is low and off when the clock signal CLK is high, as illustrated by the waveforms of FIG. 2 b.  In addition to the main device of FIG. 2, a replica device is provided, coupled in parallel with the main device. In the specific embodiment to be described with respect to FIG. 3, the main device is a p-channel transistor and accordingly, the replica device would also be a p-channel transistor, with the gates of the main device and replica device connected together. If the main device and replica device were junction transistors instead, such as pnp transistors, the bases of the transistors would be connected together. In either event, the drains or collectors of the main device and replica device are connected to a circuit which forces the drain or collector of the replica device to the same voltage as the drain or collector of the main device. The main device is typically N times the size of the replica device, where N is typically large, such as, by way of example, on the order of 10,000. The current in the replica device is mirrored by a current mirror to a capacitor C, with the voltage across the capacitor being compared to a reference voltage VBG by a comparator Comp. The output of the comparator, in turn, controls a clock generator, which provides a clock signal CLK and a reset signal Reset. The clock signal CLK is used to control the main device and the replica device, with the reset signal controlling a reset device to controllably discharge the capacitor C. 
     FIG. 2 b  provides three exemplary waveforms for the embodiment of FIG. 2 a,  and the embodiment of FIG. 3 to be subsequently explained. The first waveform, for the no overload condition, shows the waveform for the clock signal CLK for normal operation. The second waveform, for the overload condition, shows the waveform for the clock signal CLK for a representative overload condition. The third waveform shows the reset signal waveform for the exemplary embodiment, which waveform is applicable to both the no overload and overload conditions of the circuit. 
     As shown in the waveforms of FIG. 2 b,  in a no overload condition, the clock signal CLK has an approximately 50% duty cycle. By way of example, switch S 1  of FIG. 1 would be on for approximately 50% of the time while capacitor C 1  is charged to the input voltage V IN , and off 50% of the time while the capacitor is connected to the output to deliver charge thereto. At the beginning of a full clock cycle, the clock signal CLK will go low. This turns on both the main device and the replica device. The current in the replica device (which is proportional to the current in the main device) is mirrored to charge capacitor C. This causes the voltage (node A) on the negative input to the comparator Comp to decline at a rate proportional to the mirrored current, in effect providing a voltage across the capacitor proportional to the integral of the current in the main device. In the no overload condition, the voltage V IN −V C , where V C  is the voltage across the capacitor, will remain above the reference voltage VBG on the positive input to the comparator throughout the half-period of the clock cycle. In an overload condition, however, such as caused by a short or other excessive current load on the output of the switch, or during the first few cycles of operation as the circuit in which the main switch is used comes up to normal operating conditions, the higher current in the main switch will cause a proportionally higher current being mirrored to the capacitor. This will cause the voltage on the negative input of the comparator to swing below the voltage on the positive input to the comparator before the end of the half-period of the clock cycle, driving the comparator output high. As is shown in the second waveform of FIG. 2 b,  this causes the clock signal CLK to immediately go high, remaining high until the next full clock cycle begins. 
     The voltage on node A at time t during each clock cycle, assuming t=0 when the main and replica devices are turned on, may be expressed as:          V   nodeA     =       V   IN     -       1   NC            ∫   0   t              I   S1          (   t   )               t                                    
     where: 
     N is equal to the current in the main device divided by the current in the replica device, as mirrored to node A 
     I s1 (t) is the instantaneous current in switch S 1   
     The average output current I OUT  is: 
     
       
         
           I 
           OUT 
           =I 
           S1 
           D 
         
       
     
     Where D is the duty cycle of switch S 1 , normally 50% and I S1  is the current in switch S 1  averaged over the on time of the switch 
     In an overload condition, the main and replica devices will turn off when the voltage V C  across the capacitor is:          V   C     =         1   NC            ∫   0   t              I   S1          (   t   )               t           =   VBG                            
     But          ∫   0   t              I   S1          (   t   )               t                              
     is equal to the charge delivered to the switch output during that clock cycle. Consequently, when clocking the switch at a frequency f, the average current I OUT  delivered to the switch output is:          I   OUT     =       f          ∫   0   t              I   S1          (   t   )               t           =     fNC        (   VBG   )                                
     Thus the net result is that the average switch current in an overload condition is limited by certain parameters, thereby limiting the power dissipation in the switch and elsewhere in the circuitry and power supply. This is accomplished by limiting the charge transferred through the switch on each clock cycle to a predetermined maximum. 
     Now referring to FIG. 3, a circuit diagram for an exemplary circuit implementing the system of FIGS. 2 a  and  2   b  may be seen. In this circuit, p-channel transistors are designated by a transistor number preceded by the letter P, whereas n-channel transistors are designated by a transistor number preceded by the letter N. The circuit also includes two pnp transistors, each identified by an appropriate number preceded by the letter Q. In addition to the circuit connections corresponding to those of FIG. 2 a,  the circuit of FIG. 3 also is provided with an on signal ON and an off signal OFF, each being the complement of the other. 
     In normal operation, the on signal ON is high, holding transistor P 4  off, and the off signal OFF is low, holding transistor N 2  off. When the clock signal CLK is high (see FIG. 2 b ), transistor P 1 , which is the main device of FIG. 2 a,  and transistor P 2 , which is the replica device of FIG. 2 a,  are both off. During this time, the reset signal Reset will go low and then return high, momentarily turning on transistor P 6  to discharge capacitor C, bringing node A to the input voltage V IN . Then, in the second phase of the clock signal, when signal CLK goes low, transistors P 1  and P 2  are both turned on. The average current through transistor P 1 , the main device, is the output current I OUT . The current through transistor P 2  also flows through transistor Q 1  and transistor N 1 , being mirrored by transistor N 1  to transistors N 3 , N 4  and N 8 . The current mirrored to transistor N 3  also flows through transistor Q 2 , setting the base voltage of both transistors Q 1  and Q 2  at one VBE (base-emitter voltage) below the voltage of the output line providing the current I OUT . The drain of transistor P 2 , like the drain of transistor P 1 , is at a voltage one VBE above the bases of transistors Q 1  and Q 2 , and thus the voltages on the drains of transistors P 1  and P 2  are substantially identical. Consequently, with the operating conditions of transistors P 1  and P 2  being the same (same source voltage, same gate voltage and same drain voltage), the current through transistor P 2  will equal the current through transistor P 1  divided by N, where N is the width of transistor P 1  divided by the width of transistor P 2 , assuming transistors P 1  and P 2  have equal lengths. Typically, N will be large, so that the rest of the circuit will require little power in comparison to the output provided by transistor P 1 . 
     The current mirrored to transistor N 4  is in turn mirrored by transistors P 3  and P 5  to transistors N 5  and N 6 . Transistors N 5  and N 6  generate a cascode voltage for transistor N 7 . The cascode transistor N 7  allows transistor N 8  to more accurately reflect the current in transistor N 1 . The cascode is not required, but does improve the accuracy of the current mirroring if used. Thus, the resulting pull-down current at node A is equal to (or proportional to, depending on transistor area ratios) the current through transistor P 2 , which in turn is 1/N times the current in transistor P 1 . Thus, the specific circuit shown in FIG. 3 functions as described for the block diagram system shown in FIG. 2 a,  with the waveforms thereof shown in FIG. 2 b.    
     In the circuit of FIG. 3, if the circuit is turned off, the off signal OFF will go high and the on signal ON will go low. The off signal OFF going high turns on transistor N 2 , turning off transistors N 1 , N 3 , N 4  and N 8  to shut off the current flow through these transistors. The on signal ON going low similarly turns on transistor P 4 , turning off transistors P 3  and P 5  to further shutdown current flow through these transistors. 
     In addition to the circuit elements of the exemplary embodiment just described, FIG. 3 further includes current sources I 1 , I 2  and I 3 . Current source I 2  provides a pull-down current at the base of transistors Q 1  and Q 2  to assure startup for the self-biased loop formed by transistors Q 1 , Q 2 , N 1  and N 3 . If this current is not provided and the base of Q 1  and Q 2  is at a high voltage (e.g. V IN ) initially, the circuit will not startup. Current sources I 1  and I 3  are used to cancel the error introduced by current source I 2  in terms of equalizing the mirrored current values. Current sources I 1 , I 2  and I 3  should all be equal or proportional to each other. Current sources I 1  and I 3  may not be required if current source I 2  can be made low enough. It may also be possible to turn off all three current sources once startup has been achieved. 
     In the circuit of FIG. 3, MOS transistors have been used for all transistors except transistors Q 1  and Q 2 , though p-channel transistors could be used for these transistors also. Further, the system described with respect to FIGS. 2 a  and  2   b  and the circuit shown in FIG. 3 are shown for use, by way of example, in place of switch S 1  of FIG. 1, namely, a switch referenced to the high side of the input. The same principles may be applied, instead, to current limiting in a switch referenced to the low side of the input, such as, by way of example, switch S 3  in FIG.  1 . This may be accomplished by essentially turning the circuit of FIG. 3 upside down, changing all p-channel transistors to n-channel transistors, n-channel transistors to p-channel transistors and the two pnp transistors to npn transistors (together with appropriate inversion of waveforms). Also, the circuits could be realized with all junction transistors or any mix of transistors desired, provided that the main device and the replica device (FIG. 2) are of the same type. Any such circuits could also be used in switching power supplies using inductors, if desired. 
     Further, while FIG. 3 shows transistors P 1  and P 2  as well as transistors P 3  and P 5  and capacitor C being connected to the input voltage V IN , it should be noted that it is not a requirement for this common connection. In particular, the sources of transistors P 3  and P 5  and capacitor C might be connected to a positive power supply voltage, with the sources of transistors P 1  and P 2  being connected to some other, possibly time-varying, voltage, provided that when transistors P 1  and P 2  are turned on, that time-varying voltage gave sufficient headroom (sufficient voltage above ground for circuit operation) to allow mirroring of the current through transistor P 2  to the rest of the circuit. Further, whether the current through transistor P 2  is mirrored to provide a pull-down current for the capacitor C, as shown in FIG. 3, or mirrored to provide a pull-up current for a capacitor coupled to the ground line GRD, is a matter of choice. In that regard, mirroring to the capacitor could be eliminated, by way of example, by replacing transistor N 3  of FIG. 3 with a resistor, and using the collector current in transistor Q 1  as a pull-up current to charge capacitor C (and changing the inputs to the comparator Comp accordingly). While this will put different currents through transistors Q 1  and Q 2 , resulting in the VBEs of the transistors being slightly different, the difference will only be a few millivolts and would have little effect on the ratio of currents between the main device and the replica device. 
     In the preferred embodiment, the current through the transistor switch is replicated in a replica switch, both when the transistor switch is on and when it is off. However, when the transistor switch is off, the replica device does not necessarily need to be off, provided the capacitor is in the reset condition when the transistor switch is turned back on. 
     Also in the preferred embodiment, the current through a transistor switch is replicated in a replica switch. However, other techniques for replicating the switch current may be used if desired. By way of example, FIG. 4 illustrates a switch current replication circuit using a current sense resistor R S . In this circuit amplifier A controls the base of transistor Q 3  to hold the differential input to the amplifier at zero. While not necessary to the operation of the circuit, it is convenient to make resistors R 1 , R 2  and R 3  all equal (R 1 =R 2 =R 3 =R), and all much larger in resistance than the sense resistor, normally a very low value (R&gt;&gt;R S ). With these assumptions, the voltage drop across the resistor R 1  must equal the voltage drop across the sense resistor, namely IR S , where I is the switch current (all other currents in the circuit being very low in comparison). Since the current into the inverting input to the amplifier is zero, the voltage drop across resistor R 2  must also be IR S , and the current through resistor R 2  is IR S /R 2 . Consequently the voltage drop across resistor R 3  is also IR S , and the current through resistor R 3 =IR S /R 3 . The current in the emitter of transistor Q 3  and the current I replica  in the collector of transistor Q 3  (the base current of transistor Q 3  is assumed to be very low and is neglected) is the sum of the currents in resistors R 2  and R 3 , namely: 
       I   replica =2 IR   S   /R   
     where: 
     I=the switch current 
     R S =the resistance of the sense resistor 
     R=R 1 =R 2 =R 3 , and 
     R&gt;&gt;R S    
     The foregoing circuit is exemplary only. The specific circuit shown could be readily adapted to any switch, referenced to the positive or negative circuit voltages. Similarly the sense resistor could be on either side of the switch, and the transistor could be a MOS device. The circuit illustrates that the replica current may be derived by use of a replica switch, or by replicating the switch current by other means, such as through the use of another device in series with the switch. 
     Relating the circuit of FIG. 4 to the circuit of FIG. 3, the switch schematically illustrated in FIG. 4 would be transistor P 1  of FIG.  3 . Replica transistor P 2  and transistors Q 1 , Q 2  and N 3  would be eliminated, and the replica current I replica  of FIG. 4 would be mirrored to transistors N 4  and N 8  by transistor N 1 , the rest of the circuit of FIG. 3 operating as previously described. 
     The foregoing are only exemplary of the many various ways of practicing the invention. Thus, while the present invention has been disclosed and described with respect to various embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail might be made therein without departing from the spirit and scope of the invention.