Abstract:
The invention comprises a weather radar system in which a magnetron transmitter is controlled in frequency by injecting therein a low power locking signal from a stable frequency source. Frequency lock between the source and the magnetron is maintained without requiring injection signals of excessive power by an automatic frequency control (AFC). The AFC determines the frequency and phase error between the injection signal and the magnetron output and adjusts the frequency of the source so as always to be within a narrow band of frequencies centered about the natural frequency of the magnetron. Over the long term, therefore, the frequency of the source will vary by an amount equal to the change in the natural frequency of the magnetron occurring during that time. Over the short term, however, the difference in frequency between the injection signal and the magnetron output is zero, while the phase difference is less than 90°. The frequency source controlling the magnetron also serves as a frequency source for generating the several local oscillator frequencies required by the system receiver. Thus, the pulse to pulse transmitted signals, return signals and receiver i.f. signals all possess a high degree of phase coherence, readily permitting detection and determination of the doppler frequencies contained in the return signals.

Description:
The present invention relates broadly to radar systems. More particularly, it relates to an airborne weather radar system having an injection-locked magnetron transmitter and chain-related heterodyne oscillators for coherent detection of weather phenomena. 
     The majority of weather radar systems presently in service employ pulse-type transmitters and receivers designed for non-coherent detection of weather return signals. Such systems display the range and bearing of weather phenomena relative to the location of the transmitter, the area affected thereby and the intensity of activity therein, based upon the amplitude of the return signals. Generally, higher amplitude returns are associated with higher precipitation rates. An area displaying a high precipitation rate may be assumed to include highly turbulent winds, but it is known that areas of light precipitation may also involve dangerous turbulence. 
     The wind velocities within a storm cell are detectable by measurement of the doppler frequencies contained in the radar returns from the cell. The process for detecting such doppler frequencies requires a high degree of pulse to pulse phase coherence in the transmitted signals and in the receiver local oscillator signals. The majority of weather radar systems use pulsed magnetrons for the generation of transmitter signals at microwave frequencies, selected on the basis of cost, power output and reliability considerations. Magnetron transmitters, because of inadequate frequency stability, require exceptionally complicated receivers if the system is to be used for coherent detection of return signals. 
     Efforts have been made to stabilize the frequency of a magnetron by injecting therein, at the start of oscillation, a low power signal from a highly stable frequency source. Such a frequency stabilized magnetron would enable coherent detection of return signals by a receiver of uncomplicated design. It was found, however, that as the free-running or natural frequency of oscillation of the magnetron drifted away from the frequency of the injected signal, it was necessary to increase the power of the injected signal drastically to maintain the magnetron frequency equal to that of the injected signal. As a consequence, efforts to control the frequency of a magnetron by injection locking to a stable frequency source largely have been abandoned. Instead, transmitters of the oscillator-amplifier type have been favored in weather radar systems capable of turbulence detection. 
     In an oscillator-amplifier system, the oscillator is designed to operate at a sub-microwave frequency with high frequency stability. One or more frequency multipliers increase the oscillator frequency to the microwave band and the output of the frequency multipliers is amplified in a solid state microwave amplifier for radiation as the transmitter carrier. The oscillator also provides a frequency reference for one or more local oscillators of the receiver, thereby greatly simplifying the design of the receiver for coherent detection of return signals. 
     The disadvantages of an oscillator-amplifier transmitter, as compared with a magnetron transmitter, include much lower attainable power levels for the transmitter output signal and much higher costs, both in materials and in the labor of assembly and tuning adjustment. 
     In order to gain the advantages of high power output, high reliability and comparatively low cost of a magnetron transmitter together with the advantage of a relatively uncomplicated receiver design for coherent detection of return signals, it is an object of the present invention to provide a means for stabilizing the frequency of the output signal of a magnetron microwave generator. 
     It is a further object of the invention to provide a weather radar system in which the transmitter and local oscillators of the receiver are all referenced in frequency to a single, highly stable frequency source. 
     It is still another object of the invention to provide a magnetron oscillator controlled in frequency by injection locking means capable of maintaining frequency control throughout the normal magnetron frequency band with injection signals of substantially constant, moderate power levels. 
     Other objects and advantages will become apparent as an understanding of the invention is gained from the following description and accompanying drawings. 
     BRIEF DESCRIPTION 
     Briefly, the invention comprises a weather radar system in which a magnetron transmitter is controlled in frequency by injecting therein a low power locking signal from a stable frequency source. Frequency lock between the source and the magnetron is maintained without requiring injection signals of excessive power by an automatic frequency control (AFC). The AFC determines the frequency and phase error between the injection signal and the magnetron output and adjusts the frequency of the source so as always to be within a narrow band of frequencies centered about the natural frequency of the magnetron. Over the long term, therefore, the frequency of the source will vary by an amount equal to the change in the natural frequency of the magnetron occurring during that time. Over the short term, however, the difference in frequency between the injection signal and the magnetron output is zero, while the phase difference is less than 90°. The frequency source controlling the magnetron also serves as a frequency source for generating the several local oscillator frequencies required by the system receiver. Thus, the pulse to pulse transmitted signals, return signals and receiver i.f. signals all possess a high degree of phase coherence, readily permitting detection and determination of the doppler frequencies contained in the return signals. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of a radar system incorporating the injection locked magnetron of the invention; 
     FIG. 2 is a chart showing the frequencies at various points in the system of FIG. 1; 
     FIG. 3 is a functional block diagram showing the system of FIG. 1 in greater detail; and 
     FIG. 4 is a functional block diagram of the automatic frequency control shown in block form in FIGS. 1 and 3. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 broadly illustrates the invention. A magnetron 10 is pulse modulated by a modulator 12 to generate microwave energy preferably at X-band frequencies. The output of magnetron 10 is fed through a duplexer 14 to an antenna 16 for radiation. The pulses transmitted by antenna 16 which encounter reflecting targets are returned to the antenna whence the return signals enter duplexer 14 and are passed on to a pre-amplifier 18. Duplexer 14 performs the usual function of allowing pulses from magnetron 10 to pass to antenna 16 but not to pre-amplifier 18 and of allowing return signals from antenna 16 to pass to pre-amplifier 18 but not to magnetron 10. Pre-amplifier 18 amplifies the return signals without converting the frequency of the carrier wave thereof and supplies the amplified return signals to one input of a first mixer 20. 
     The frequency of the carrier wave generated by magnetron 10 is controlled by a low level microwave signal injected therein from an amplifier 22, the output of which is applied to magnetron 10 through cascaded isolators 23, 23&#39;. Isolators 23, 23&#39; permit signal flow from amplifier 22 to magnetron 10 but block signal flow in the reverse direction, thereby preventing the high level magnetron output signal from entering amplifier 22 and causing damage thereto or pulling the frequency of the output signal thereof. 
     Amplifier 22 is pulsed &#34;on&#34; simultaneously with the application of an energizing pulse to magnetron 10 by modulator 12. When activated, amplifier 22 amplifies for injection into magnetron 10 an input signal received from a first frequency multiplier 24 which, in turn, receives input from a stable frequency source 25 at frequency f o  and multiplies such frequency by a constant K 1  to the microwave frequency F 1  at which the frequency of the carrier of the magnetron output is to be controlled. 
     The return signals at the output of preamplifier 18 have frequencies of F 1  ±Δ, where Δ is the doppler variation in the frequency F 1  due to relative motion between the antenna 16 and the reflecting targets. The output from preamplifier 18 is mixed with the output of a first local oscillator 27 to generate the input to a first intermediate frequency (i.f.) amplifier 28. First local oscillator 27 is a frequency multiplier which receives input at frequency f o  from source 25 and multiplies the frequency thereof by a constant K 2  to produce input to mixer 20 at frequency F 2  =K 2  f o . The first i.f. amplifier is tuned to a center frequency of F 2  -F 1  with a band width adequate to cover the band of doppler frequencies ±Δ present in the target return signals. 
     The output of first i.f. amplifier 28 is mixed with the output of a second local oscillator 29 in a second mixer 31. Second local oscillator 29 is a frequency multiplier which receives input at frequency f o  from source 25 and multiplies the frequency thereof by a constant K 3  to produce an output signal at frequency F 3  =K 3  f o . The frequency of the output of second mixer 31 is F 3  -[F 2  -(F 1 ±Δ)]. The output of second mixer 31 is amplified by a second i.f. amplifier 32, tuned to the frequency of the mixer output and furnishing one input to a third mixer 33. 
     Third mixer 33 receives a second input from a third local oscillator 34. Local oscillator 34 is a frequency multiplier producing an output at frequency F 4  =K 4  f o , where f o  is the frequency of the input thereto from source 25. Third mixer 33 generates an output having a frequency F 3  -[F 2  -(F 1  ±Δ)]-F 4 . The output of mixer 33 is amplified in a third i.f. amplifier 34 tuned to the frequency of the mixer output, then detected in a video detector for application to a display indicator (not shown). 
     Except for the facts that all local oscillator signals are derived from a single frequency source 25, and that the frequency of the magnetron is also controlled by source 25, the invention as thus far described corresponds to a conventional pulse radar with a triple conversion receiver. The control of the magnetron frequency by the source 25 and the derivation of all local oscillator signals therefrom insures pulse to pulse phase coherence in the transmitted and return signals thereby preserving the turbulence information in the doppler content of the return signals. 
     The doppler content of the return signals is detected by beating the output of second i.f. amplifier 32 against the output of a fourth local oscillator 36. Fourth local oscilator 36 is a frequency multiplier which receives input at frequency f o  from source 25 and multiplies the frequency thereof by a constant K 5  to produce an output at frequency F 5  equal to the frequency to which second i.f. amplifier is tuned, i.e. F 5  =F 3  +F 1  -F 2 . 
     A portion of the output from fourth local oscillator 36 is passed through a 90° phase shifter 37 and applied as one input to a first doppler mixer 38. Another portion of the output of local oscillator 36 is applied, without phase shift, as one input to a second doppler mixer 39. Mixers 38 and 39 each receive second input signals from second i.f. amplifier 32. The output Q of mixer 38 is a spectrum of quadrature components of the doppler content of the return signals stripped of the carrier of the returns. The output I of mixer 39 is a spectrum of the in-phase components of such doppler content, likewise stripped of carrier. 
     The Q and I outputs of mixers 38, 39 are sampled by separate analog to digital (A/D) converters 41 and 42 controlled by a doppler processor 43 which receives, stores and mathematically processes the digitized samples, utilizing known techniques, to generate display signals indicative of the location and intensity of turbulence of weather phenomena. 
     Frequency source 25 produces an output f o  which is highly stable in frequency. However, the frequency f o  does not remain constant over the long term. In order to maintain magnetron frequency locked to the frequency F 1  of the injection signal from amplifier 22 at relatively low power levels for the amplifier output, the frequency F 1  must always be within a very small amount of the free-running frequency F o  the magnetron. 
     Typically, the free running frequency F o  of a magnetron having a nominal operating frequency of 9345 MHz may vary by ±25 MHz while the frequency F 1  of the injection signal must be within ±2.5 MHz of F o , i.e. F 1  =F o  ±2.5 MHz to achieve satisfactory frequency lock. 
     Frequency source 25 is a frequency synthesizer controlled by an automatic frequency control 44 to produce an output f o  which is variable in steps such that F 1  will always be within 2.5 MHz of F o . In one specific embodiment of the invention the following values were selected for the constants K 1  -K 5  : 
     K 1  =118.8 
     K 2  =121.5 
     K 3  =3.0 
     K 4  =1/3.5=0.2857 
     K 5  =0.3 
     The magnetron of the specific embodiment had a nominal free-running frequency of 9405 MHz with a range of variation of approximately ±20 MHz. 
     FIG. 2 is a chart showing the frequencies at various location of FIG. 1 for the specified example. 
     The variation in the free-running frequency F o  of the magnetron of approximately 40 MHz requires that the frequency source output frequency be variable through a range of 0.333 MHz. It should also be noted that the specified values for the constants K 1  -K 4  yield maximum variations in the frequencies of the first I.F. amplifier 28, second I.F. amplifier 32 and third I.F. amplifier 34 of, respectively, 0.9 MHz, 0.1 MHz and 4.8 KHz. Consequently, adjustment of the tuning of the receiver portion of the system is not required during operation. 
     FIG. 3 is a block diagram showing the system of FIG. 1 in greater detail. Frequency source 25 is a frequency synthesizer producing a signal having a frequency which is variable through the range required of f o , the stability of which is controlled by a crystal oscillator 70. The frequency of the output from oscillator 70 is divided by four in a frequency divider 71, divided by thirty two in a frequency divider 72 and multiplied by four in a frequency multiplier 73. 
     The multiplied frequency of the output of multiplier 73 is divided by N in a programmable divider 74, the output of which is furnished as one input to a mixer 75. The divisor N of programmable divider 74 is controlled by AFC 44, later described. In the specific embodiment referred to in connection with FIG. 2, N is an integer having a value of from 160 to 205, depending on the frequency f o  required. 
     Mixer 75 adds the outputs of dividers 72 and 74 to produce an output at the sum frequency of the inputs which is then passed through a bandpass filter 76 to an input of mixer 77. Mixer 77 receives a second input from divider 77 and produces an output at the sum frequency of the inputs. The output of mixer 77 is passed through bandpass filter 78 to an input of mixer 79. Mixer 79 receives a second input from oscillator 70 and produces output at the sum frequency of the inputs. After filtering in bandpass filter 80, the output of mixer 79 appears at the output of synthesizer 25 as the frequency f o . 
     In the specified embodiment, the frequency of oscillator 70 was selected as 60.735 MHz. Then numerically, the output of divider 74 is selectable between the frequencies of 4×60.735/205 and 4×60.735/160, i.e. from 1.185 to 1.518 MHz. 
     The output frequency of mixer 75 is 60.735/32 plus from 1.185 to 1.518, which is from 3.083 to 3.416 MHz. 
     The output frequency from mixer 77 is 60.735/4 plus from 3.083 to 3.416 which is from 18.267 to 18.600 MHz. 
     Finally, the frequency of the output from mixer 79, and the output frequency f o  of synthesizer 25, is 60.735 plus from 18.267 to 18.600, which is from 79.002 to 79.335 MHz. The band of possible output frequencies from source 25 will be seen to cover the band of f o  frequencies appearing in Column Two of FIG. 2. 
     Frequencies F 1  and F 2  involving multiplying factors K 1  and K 2  are generated as follows. 
     The output f o  of source 25 is applied to a times-two frequency multiplier 50, a divide-by-four frequency divider 51 and a divide-by-five frequency divider 52. The outputs of multiplier 50 and divider 52 are added together in a mixer 53. The resultant output of mixer 53 is further increased in frequency by a times-nine frequency multiplier 54 and a following times-six frequency multiplier 55, the output of which is a signal at frequency F 1 . Numerically, F 1  =f o  [(2+0.2)×9×6]=118.8 f o  =K 1  f o . 
     The outputs of multiplier 50 and divider 51 are added together in a mixer 56. The frequency of the resultant output of mixer 56 is further increased by a times-nine frequency multiplier 57 and a times-six frequency multiplier 58 is cascade therewith to produce an output signal at frequency F 2 . Numerically, F 2  =[(2+0.25)×9×6]=121.5 f o . 
     Frequency F 3  is straightforwardly produced by a times-three frequency multiplier 60. Frequency F 4  is generated by dividing the double frequency output of multiplier 50 in a divide-by-seven frequency divider 61. This permits use of a frequency divider having an integer divisor. Numerically, F 4  =(2/7)f o  =(1/3.5)f o  =K 4  f o . 
     Frequency F 5  has the same value as the frequency of the output of second i.f. amplifier 32, except for the doppler frequency content of the latter. 
     The second i.f. center frequency is: 
     
         F.sub.3 -[F.sub.2 -F.sub.1 ]=F.sub.5 =K.sub.3 f.sub.o -K.sub.2 f.sub.o +K.sub.1 f.sub.o =(3-121.5+118.8)f.sub.o =0.3f.sub.o =K.sub.5 f.sub.o. 
    
     A mixer 62 adds together output at frequency f o  from source 25 and output from divide-by-five frequency divider 52 to produce output at frequency 1.2f o . The frequency of the output signal from mixer 32 is divided in a divide-by-four frequency divider 63 to yield output at frequency F 5 . Numerically, F 5  =1.2f o  /4=0.3f o . 
     The outputs of mixers 38 and 39, comprising the Q and I components of the doppler frequency content of the return signals, are passed through low-pass filters 64, 65 prior to conversion to digital form in converters 41, 42. 
     The automatic frequency control 44 is shown schematically in FIG. 4. Referring first to FIG. 3, a phase comparator 82 receives one input signal at frequency F 1  from coupler 83 attached to the output of amplifier 22 and a second input signal at frequency F o  from coupler 84 attached to the output of magnetron 10. When frequencies F o  and F 1  differ from one another, the output of phase comparator 82 is an r.f. signal. When frequencies F o  and F 1  are equal but differ in phase, the output of phase comparator is a d.c. signal which is positive or negative, depending on whether the phase of F 1  lags or leads F o . 
     Referring now to FIG. 4, the output of phase comparator 82 is applied to an r.f. amplifier 85, which amplifies any a.c. components of the phase comparator output. The output of phase comparator 82 is also applied to a filter 86 which removes any a.c. components from the comparator output and passes the positive or negative d.c. component remaining therein to a high comparator 87 and to a low comparator 88. If the d.c. component of the phase comparator output exceeds a small positive level, high comparator 87 will produce an output; if more negative than a low negative level, low comparator 88 will produce an output. If the d.c. component of the phase comparator 82 lies within the positive and negative thresholds of comparators 87 and 88, neither comparator 87 or 88 will produce an output. The output of amplifier 85, if present, is detected in a detector 89 to produce a positive d.c. output. 
     The outputs of comparators 87 and 88 and detector 89 are present only for the duration of a transmitter pulse. To preserve these outputs as d.c. levels for the duration of an interpulse period, they are applied to a latch 90. Modulator 12 provides on line 93 a delayed PRF pulse which appears shortly after the beginning of a transmitter pulse and, on line 94, a pre-PRF pulse which appears shortly before the beginning of a transmitter pulse. 
     AFC 44 operates to produce an output number varying between 0 and 48 which is used to vary the value of the divisor N of programmable divider 74 (FIG. 3) between the values of 160 and 208. An output from high comparator 87 indicates that the frequency or phase of F 1  is higher than or leads F o , thus requiring an increase in N to reduce the frequency of F 1 . 
     AFC 44 includes two cascaded 4-bit up-down counters which generate a 6-bit output on lines A0-A5 varying between binary 0000 0000 and 0011 0000 (0-48) to control the divisor. Depending upon the states of the control inputs to counters 95 and 96, the output of counters 95 and 96 will remain constant, increment one count or decrement one count during the interpulse period following each transmitter pulse. 
     If no outputs are present from any of comparators 87, 88 or detector 89, frequency F 1  is equal to F o  and the phase difference between the two is sufficiently small that no adjustment of the output of counters 95, 96 is required. 
     If an output is present only at high comparator 87, frequencies F 1  and F o  are equal but the phase of F 1  is leading that of F o  excessively indicating a tendency of the natural frequency of the magnetron to drift downward thus requiring a downward adjustment in the locking signal frequency F 1 . 
     If an output is present only at low comparator 88, the opposite conditions of F 1  and F o  prevail, requiring an upward adjustment in F 1 . 
     If outputs are present at detector 89, counters 95 and 96 are caused to sweep count from 0 to 48 or from 48 to 0 until frequency F 1  becomes equal to F o  and the phase difference between the two is sufficiently small. 
     Control of counters 95 and 96 by the outputs of detector 89 and comparators 87, 88 will next be described. 
     Shortly after the beginning of a transmitter pulse, latch 90 is clocked by a pulse on line 93 and any inputs present on latch inputs 1B-3D are latched into outputs 1Q-3Q. An output from detector 89 is latched on output 3Q (SWP). An output from comparator 87 is latched on output 1Q (H.COMP) and an output from comparator 88 is latched on output 2Q (L.COMP). Outputs SWP and H. COMP are combined in an OR gate 97 to provide on line 98 an SWP+H. COMP logic signal. Signal on line 98 is applied to the U/D inputs of counters 95,96. If SWP or H. COMP is high, counters 95, 96 are steered to count up. If neither SWP or H.COMP is high, counters 95, 96 count down. The logic signal on line 98 and L.COMP are combined in OR gate 99 the output of which is inverted by inverter 101 to produce on line 102 a logic signal (SWP+H.COMP+L.COMP)&#39;=SWP. H.COMP. L.COMP. Line 102 is connected to the ENP inputs of counters 95, 96. If SWP, H.COMP and L.COMP are all low (no output from detector 89, comparator 87 and comparator 88) line 102 is high and neither counter 95, 96 will increment or decrement upon the appearance of a clock pulse. The values of counter outputs AO-A5 remain constant at the values existing. If any one of SWP, H.COMP or L.COMP is high, line 102 is low and counters 95, 96 will increment or decrement when clocked to change outputs A0-A5 up or down. 
     Counters 95, 96 are preset to 0000 0000(0) or 0011 0000 (48) by the following logic. SWP+H.COMP on line 98 is combined with the inverted Q output of a D-type flip-flop 103 in OR gate 104. SWP+H.COMP from line 98 is inverted by inverter 105 to produce an output (SWP+H.COMP)&#39;=SWP H.COMP. The output of inverter 105 is combined with the inverted Q output of a flip-flop 106 in OR gate 107 to provide a logic outut SWP. H.COMP+Q 106. (Since the Q output is inverted, that output will be the same state as the Q output). 
     The outputs of gates 104 and 107 are combined in an AND gate to provide on line 109 [SWP+H.COMP+Q 103][SWP.  H.COMP+Q 106]. Either SWP or H.COMP must be high and Q 106 high; or SWP or H.COMP must both be low and Q 103 high to produce a high on line 109. Line 109 is connected to the load control LD of counters 95, 96. If line 109 is high, the outputs A0-A5 of counters 95, 96 are set to the values on the A-D inputs thereof. Inputs A-D of counter 96 are grounded as are inputs C, D of counter 95. Inputs A, B of counter 95 are supplied by outputs 1Y, 2Y of a data selector 110. Data selector 110 is controlled by line 111 to select for outputs 1Y, 2Y the data on inputs 1A, 2A (if line 111 is low) or the data on inputs 1B, 2B (if line 111 is high). 
     Outputs A4 and A5 of counter 95 are combined in an AND gate 112 to provide A4.A5 as the D input of flip-flop 106. Outputs A0-A3 of counter 96 are combined in a NOR gate 113 to provide (A0+A1+A2=A3)&#39;=A0.A1.A2.A3. Outputs A4-A5, QC, QD of counter 95 are combined in a NOR gate 114 to provide (A4+A5+QC+QD)&#39;=A4.A5.QC.QD. The outputs of gates 113 and 114 are combined in AND gate 115 to provide on line 116 [A0.A1.A2.A3].[A4.A5.QC.QD]. Thus, all outputs A0-A5, QC, QD of counters 95, 96 must be low for line 116 to be high. 
     At start up, all outputs of counters 95, 96 are low, line 116 will be high and the output of the inverted Q output of flip-flop 103 will be toggled high upon the appearance of a pulse on line 93. SWP and H.COMP are both low, therefore line 109 is high, causing outputs A0-A5 of counters 95, 96 to be set to the values on inputs A-D thereof. Also, at start-up, inputs A4, A5 of gate 112 are both low, providing a low D input to flip-flop 106. A pulse on line 93 sets the Q output of flip-flop 106 low, thereby selecting the high data of inputs 1A, 2A of data selector 110 for outputs 1Y, 2Y thereof. Outputs A0-A5 of counters 95, 96 will accordingly be set to 0011 0000 (48). Divisor N of programmable divider 74 is then set to the highest value, resulting in the lowest frequency output of synthesizer 25 for the next transmitter pulse. 
     Prior to the next transmitter pulse, SWP, H.COMP and L.COMP are all low, resulting in a high on line 102. Counters 95 and 96 will not then be enabled to changed count when the pre-PRF pulse appears on line 94, prior to the next transmitter pulse. 
     After the next transmitter pulse, SWP and L.COMP are high and H.COMP is low. Inputs A4 and A5 to gate 112 are high. When the delayed PRF pulse appears on line 93, the Q output of flip-flop 106 is triggered high. Inputs A4 and A5 to gate 114 are high, resulting in a low on line 116, the inverted Q output of flip-flop 103 will be triggered low. With Q 103 low and Q 106 high, line 109 is high, causing counters to load the data on outputs 1Y, 2Y of data selector 110. Both 1Y and 2Y will then be low because line 106 is high, selecting the B inputs to data selector 110. During subsequent pulse transmissions, with SWP and L.COMP high, line 102 will be low, enabling counters 95, 96 to increment count until such time as SWP, H.COMP and L.COMP all become low. 
     Outputs A0-A5 of counters 95, 96 do not directly determine the divisor N of programmable divider 74. Instead, they are used as address inputs to a memory device (not shown) in divider 74 which sets the actual value of N. For instance, if A0-A5=0011 0000, N will be set to 208.