Abstract:
A fan test device to connect a motherboard and a fan includes a power terminal, a first diode, a second diode, a control chip, a first connector, a second connector, a first electronic switch and a second electronic switch. The control chip is connected to signal pins and sensing pins of the first and second connectors. The first electronic switch is connected between the control chip and a power pin of the first connector. The second electronic switch is connected between the control chip and a power pin of the second connector. The control chip outputs different signals corresponding to the connection of the first and second connectors.

Description:
FIELD  
       [0001]    The present disclosure relates to a fan test device. 
       BACKGROUND  
       [0002]    Typically, a fan test device has a first connector to connect to a motherboard and a second connector to connect a fan. The first and second connectors look similar to each other which may cause confusion. The fan test device may be damaged when the connections are incorrect. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING  
         [0003]    Many aspects of the present disclosure can be better understood with reference to the following drawing. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. 
           [0004]    The FIGURE is a circuit diagram of an embodiment of a fan test device of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION  
       [0005]    The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.” The reference “a plurality of” means “at least two.” 
         [0006]    The FIGURE shows an embodiment of a fan test device  10  of the present disclosure. 
         [0007]    The fan test device  10  can comprise a first connector J 1 , a second connector J 2 , a first electronic switch Q 1 , a second electronic switch Q 2 , a control chip U 1 , a resistor R 1 , a resistor R 2 , a diode D 1 , a diode D 2 , an alarm module  20 , a first power terminal V, a fuse FS 1 , and a fuse FS 2 . 
         [0008]    As illustrated, a first terminal of the first electronic switch Q 1  can be connected to a control pin RC 5  of the control chip U 1 . A power pin  1  of the first connector J 1  is connected to a second terminal of the first electronic switch Q 1 . A third terminal of the first electronic switch Q 1  is connected to a cathode of the diode D 1 . An anode of the diode D 1  is coupled to the power pin  1  of the first connector J 1  through the fuse FS 1 . A signal pin  2  of the first connector J 1  is coupled to a signal pin TACH 1  of the control chip U 1  through the resistor R 1 . A sensing pin  3  of the first connector J 1  is connected to a sensing pin SENSE 1  of the control chip U 1 . A ground pin  4  of the first connector J 1  is grounded. 
         [0009]    A first terminal of the second electronic switch Q 2  is connected to a control pin RC 4  of the control chip U 1 . A power pin  1  of the second connector J 2  is connected to a second terminal of the second electronic switch Q 2 . A third terminal of the second electronic switch Q 2  is connected to the first power terminal V. The third terminal of the second electronic switch Q 2  is also connected to a cathode of the diode D 2 . An anode of the diode D 2  is coupled to the power pin  1  of the connector J 2  through the fuse FS 2 . A signal pin  2  of the second connector J 2  is coupled to a signal pin TACH 2  of the control chip through the resistor R 2 . A sensing pin  3  of the second connector J 2  is connected to a sensing pin SENSE 2  of the control chip U 1 . A ground pin  4  of the second connector J 2  is grounded. The fuse FS 1  and the fuse FS 2  are used to prevent damage from excess current. 
         [0010]    When the first connector J 1  is connected to a motherboard and the second connector J 2  is connected to a fan, the motherboard outputs a first signal to the sensing pin SENSE 1  of the control chip U 1  through the sensing pin  3  of the first connector J 1 . The control chip U 1  outputs a low level signal, such as logic 0, to the first terminal of the first electronic switch Q 1 . The first electronic switch Q 1  is turned off. A voltage from the motherboard is output to the first power terminal V through the power pin  1  of the first connector J 1 , the fuse FS 1 , the anode of the diode D 1 , and the cathode of the diode D 1  in that order. The fan outputs a second signal to the sensing pin SENSE 2  of the control chip U 1  through the sensing pin  3  of the second connector J 2 . The control chip U 2  outputs a high level signal, such as logic 1, to the first terminal of the second electronic switch Q 2  through the control pin RC 4 . The second electronic switch Q 2  is turned on. The voltage from the motherboard is input to the power pin  1  of the second connector J 2  through the first power terminal V. Thus, the motherboard supplies power to the fan. The control chip U 1  receives a third signal of a speed of the fan through the signal pin  2  of the second connector J 2  and the signal pin TACH 2 . The control chip U 1  outputs the third signal to the motherboard through the signal pin TACH 1  and the signal pin  2  of the first connector J 1  when the control chip U 1  determines that the speed of the fan is abnormal. 
         [0011]    When the first connector J 1  is connected to the fan and the second connector J 2  is connected to the motherboard, the motherboard outputs the first signal to the sensing pin SENSE 1  of the control chip U 1  through the sensing pin  3  of the second connector J 2 . The control chip U 1  outputs a low level signal to the first terminal of the second electronic switch Q 2 . The second electronic switch Q 2  is turned off. The motherboard outputs the voltage to the first power terminal V through the power pin  1  of the second connector J 2 , the fuse FS 2 , the anode of the diode D 2 , and the cathode of the diode D 2  in that order. The fan outputs the second signal to the sensing pin SENSE 1  of the control chip U 1 . The control chip U 1  outputs a high level signal to the first terminal of the first electronic switch Q 1 . The first electronic switch Q 1  is turned on. The motherboard supplies power to the fan. The control chip U 1  receives the third signal through the signal pin  2  of the first connector J 1  and the signal pin TACH 1 . The control chip U 1  outputs the third signal to the motherboard through the signal pin TACH 2  and the signal pin  2  of the second connector J 2  when the control chip U 1  determines that the speed of the fan is abnormal. 
         [0012]    The alarm module  20  comprises a resistor R 3  and a light emitting diode (LED) D 3 . An anode of the LED D 3  is connected to a second power terminal P 5 V. The second power terminal P 5 V is used to input a high level signal. In the embodiment, the second power terminal P 5 V is connected to the first power terminal V. When the control chip U 1  determines that the speed of the fan is abnormal, the control chip U 1  outputs a low level signal through the alarm pin Alarm. When the control chip U 1  determines that the speed of the fan is normal, the control chip U 1  outputs a high level signal through the alarm pin Alarm. 
         [0013]    In the embodiment, the first and second electronic switches Q 1  and Q 2  are both n-channel filed effect transistors (FETs). 
         [0014]    The fan test device operates normally either when the first connector J 1  is connected to the motherboard and the second connector J 2  is connected to the fan or when the first connector J 1  is connected to the fan and the second connector J 2  is connected to the motherboard. 
         [0015]    While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.