Abstract:
Provided is a transconductor circuit for compensating distortion of an output current without reducing the size of chips and operation speed characteristics. The transconductor circuit includes a main circuitry which is a differential pair with source degeneration and to which a predetermined input voltage is applied, an auxiliary circuitry which is connected to nodes of the main circuitry to compensate the distortion of the output current, a variable voltage supply which controls a depth or degree of a distortion compensation operation for the output current, and a current source which supplies the main circuitry with constant bias.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     This application claims the priority of Korean Patent Application No. 2003-95399, filed on Dec. 23, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.  
         [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a transconductor circuit, and more particularly, to a transconductor circuit including metal oxide semiconductor (MOS) transistors so as to prevent an output current from being distorted.  
         [0004]     2. Description of the Related Art  
         [0005]     In general, transconductors are circuits that convert a voltage into a current to process an electric signal. In other words, when a predetermined voltage is applied to the transconductors, the transconductors output a current value. Such a transconductor is generally used in an analog signal processor such as a filter, a gain variable amplifier, or the like.  
         [0006]     The transconductor is processed by a highly integrated analog signal and includes MOS or complementary MOS (CMOS) transistors that are generally driven at a low voltage. The MOS transistors have merits in that an input gate current does not flow, power consumption is low, and integration is high.  
         [0007]      FIG. 1  is a circuit diagram of a conventional transconductor circuit. Referring to  FIG. 1 , a transconductor circuit  10  includes an input unit  20 , an output unit  30 , and current sources  40 .  
         [0008]     The input unit  20  is a differential pair and includes first and second MOS transistors M 1  and M 2  and a resistor R 1 . First and second input voltages Vinn and Vinp are applied to gates of the first and second MOS transistors M 1  and M 2 , respectively. A source of the first MOS transistor M 1  is electrically connected to a source of the second MOS transistor M 2  via the resistor R 1 . Here, the input unit  20  serves as a main circuitry of the transconductor circuit  10 . Since the input unit  20  is the differential pair and includes a pair of the first and second MOS transistors M 1  and M 2  as above-mentioned, the input unit  20  is advantageous to operation speed characteristics. Here, an output current is less distorted when the resistor R 1  exists than when the resistor R 1  does not exist.  
         [0009]     The output unit  30  is a cascode amplifier in which gates of third and fourth MOS transistors M 3  and M 4  are commonly connected. A source of the third MOS transistor M 3  is connected to a drain of the first MOS transistor M 1 , and a source of the fourth MOS transistor M 4  is connected to a drain of the second MOS transistor M 2 . Predetermined electric loads (not shown) are connected to drains of the third and fourth MOS transistors M 3  and M 4  so as to allow the output current to flow through the transconductor circuit  10 . A power voltage Vdc is applied to gates of the third and fourth MOS transistors M 3  and M 4 .  
         [0010]     The current sources  40  are respectively connected between the first MOS transistor M 1  and ground and between the second MOS transistor M 2  and ground to supply the first and second MOS transistors M 1  and M 2  with constant bias.  
         [0011]     It preferable that a gate-source voltage Vgs of the first and second MOS transistors M 1  and M 2  is low and transconductances gm of the first and second MOS transistors M 1  and M 2  are high in order to drive the transconductor circuit  10  at a low voltage. Also, it is preferable that gate-drain capacitances Cgd of the first and second MOS transistors M 1  and M 2  are low to improve fast operation characteristics. Moreover, the first and second MOS transistors M 1  and M 2  are preferably designed so that channel lengths are short and ratios of channel widths to channel lengths are great.  
         [0012]     A transconductance Gm of the transconductor circuit  10  is a variation in the output current with respect to an input voltage and can be represented as in Equation:  
             Gm   =       ⅆ     (   Iout   )         ⅆ     (   Vin   )                 (   1   )             
 
 wherein lout denotes the output current that is a difference (Iop-Ion) between a second current Iop and a first current Ion, and Vin denotes the input voltage that is a difference (Vinp-Vinn) between the second input voltage Vinp and the first input voltage Vinn. 
 
         [0013]     In the transconductor circuit  10 , the first and second input voltages Vinn and Vinp applied to the first and second MOS transistors M 1  and M 2  of the input unit  20  vary the first and second currents Ion and Iop. Here, the output unit  30  is connected to an output node of the input unit  20  to increase entire output resistance in the transconductor circuit  10 .  
         [0014]     The transconductance Gm of the transconductor circuit  10  must be constant regardless of the intensity of the input voltage Vin. However, as shown in  FIG. 2 , the transconductance Gm of the transconductor circuit  10  gradually decreases when an absolute value of the input voltage Vin increases to a constant voltage or more. This means that the output current lout of the transconductor circuit  10  is distorted.  
         [0015]     The distortion of the output current lout is generally caused by the nonlinear characteristics of the first and second MOS transistors M 1  and M 2  resulting from a power voltage and a bias current value generated from the power voltage. The distortion of the output current lout may be considerably reduced by increasing the magnitude of the resistor R 1  of the input unit  20 .  
         [0016]     However, the increase in the magnitude of the resistor R 1  results in increasing the size of semiconductor chips and parasitic capacitance, which deteriorates integration density and operation speed.  
         [0017]     Although the magnitude of the resistor R 1  increases, the nonlinear characteristics of the first and second MOS transistors M 1  and M 2  and the current sources  40  do not vary. Also, as shown in  FIG. 2 , as the input voltage Vin of the transconductor circuit  10  gets close to a maximum input voltage Vmax, the distortion of the output current lout becomes more serious. Furthermore, when the output current lout is distorted, a region in which the output current lout linearly increases is reduced.  
       SUMMARY OF THE INVENTION  
       [0018]     According to an aspect of the present invention, there is provided a transconductor circuit for compensating distortion of an output current.  
         [0019]     The transconductor circuit includes a main circuitry which is a differential pair with source generation and to which a predetermined input voltage is applied, an auxiliary circuitry which is connected to nodes of the main circuitry to compensate the distortion of the output current, a variable voltage supply which controls a depth or degree of a distortion compensation operation for the output current, and a current source which supplies the main circuitry with constant bias. When an absolute value of a total input voltage of the transconductor circuit is less than a constant voltage, the auxiliary circuitry includes MOS transistors that operate in sub-threshold regions. When the absolute value of the total input voltage is more than the constant voltage, the auxiliary circuitry includes MOS transistors that operate in saturation regions. The auxiliary circuitry contributes to compensating distortion of a total output current of the transconductor circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0021]      FIG. 1  is a circuit diagram of a conventional transconductor circuit;  
         [0022]      FIG. 2  is a graph for showing transconductance of the transconductor circuit of  FIG. 1 ;  
         [0023]      FIG. 3  is a circuit diagram of a transconductor circuit, according to an embodiment of the present invention;  
         [0024]      FIG. 4  is a graph for showing transconductance of the transconductor circuit of  FIG. 3 ;  
         [0025]      FIG. 5  is a circuit diagram of a transconductor circuit, according to another embodiment of the present invention;  
         [0026]      FIG. 6  is a graph for showing the results of a simulation for transconductance of the transconductor circuit of  FIG. 5 ;  
         [0027]      FIG. 7  is a graph for showing the results of a simulation for the distortion characteristics of an output current of a transconductor circuit according to the present invention;  
         [0028]      FIG. 8  is a circuit diagram of a transconductor circuit, according to still another embodiment of the present invention; and  
         [0029]      FIG. 9  is a circuit diagram of a transconductor circuit, according to yet another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]     The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.  
         [0031]      FIG. 3  is a circuit diagram of a transconductor circuit, according to an embodiment of the present invention. Referring to  FIG. 3 , a transconductor circuit  100  includes a main circuitry  110 , an auxiliary circuitry  120 , a variable voltage supply  130 , and a current source  140 .  
         [0032]     The main circuitry  110  is a differential pair with source degeneration and includes first through fourth MOS transistors M 1  through M 4  and first and second resistors R 1  and R 2 .  
         [0033]     First and second input voltages Vinn and Vinp are applied to gates of the first and second MOS transistors M 1  and M 2 , respectively. Sources of the first and second MOS transistors M 1  and M 2  are electrically interconnected via the first and second resistors R 1  and R 2 .  
         [0034]     Gates of the third and fourth MOS transistor M 3  and M 4  are interconnected. A source of the third MOS transistor M 3  is connected to a drain of the first MOS transistor M 1 , and a source of the fourth MOS transistor M 4  is connected to a drain of the second MOS transistor M 2 . Predetermined electric loads (not shown) are connected to drains of the third and fourth MOS transistors M 3  and M 4  to allow an output current to flow through the transconductor circuit  100 . The magnitude of the first and second resistors R 1  and R 2  may be arbitrarily controlled by a designer, for example, may be about several Ω to millions Ω. An input voltage Vin of the transconductor circuit  100  is a difference between the second input voltage Vinp and the first input voltage Vinn, and an output current lout of the transconductor circuit  100  is a difference between a second output current Iop and a first output current Ion.  
         [0035]     The auxiliary circuitry  120  includes fifth and sixth MOS transistors M 5  and M 6  and third and fourth resistors R 3  and R 4 . In more detail, a gate of the fifth MOS transistor M 5  is connected to the drain of the first MOS transistor M 1 , a source of the fifth MOS transistor M 5  is connected to an end of the third resistor R 3 , and a drain of the fifth MOS transistor M 5  is connected to the drain of the fourth MOS transistor M 4 . The other end of the third resistor R 3  is connected to the source of the first MOS transistor M 1  of the main circuitry  110 . A gate of the sixth MOS transistor M 6  is connected to the drain of the second MOS transistor M 2 , a source of the sixth MOS transistor M 6  is connected to an end of the fourth resistor R 4 , and a drain of the sixth MOS transistor M 6  is connected to a drain of the third MOS transistor M 3 . The other end of the fourth resistor R 4  is connected to the source of the second MOS transistor M 2  of the main circuitry  110 .  
         [0036]     As another aspect, in the circuit diagram of  FIG. 3 , the drain of the fifth MOS transistor M 5  may be connected to the source of the fourth MOS transistor M 4 , and the drain of the sixth MOS transistor M 6  may be connected to the source of the third MOS transistor M 3 .  
         [0037]     The magnitude of the third and fourth resistors R 3  and R 4  may be arbitrarily controlled by a designer, for example, may be several Ω to millions Ω. Here, V 1  denotes a gate voltage of the fifth MOS transistor M 5 , and V 2  denotes a gate voltage of the sixth MOS transistor M 6 . The auxiliary circuitry  120 , particularly the fifth and sixth MOS transistors M 5  and M 6 , substantially serve to prevent an output current of the main circuitry  110  from being distorted.  
         [0038]     The variable voltage supply  130  is a voltage source for supplying a direct current (DC) voltage Vdc and is connected between a node to which gates of the third and fourth MOS transistors M 3  and M 4  are commonly connected and a node to which the first and second resistors R 1  and R 2  are commonly connected.  
         [0039]     The current source  140  includes first and second constant current sources Idc 1  and Idc 2 . The first constant source Idc 1  is connected between the source of the first MOS transistor M 1  and a ground node to supply the first MOS transistor M 1  with predetermined bias. The second constant current source Idc 2  is connected between the source of the second MOS transistor M 2  and a ground node to supply the second MOS transistor with predetermined bias.  
         [0040]     There will now be explained the bias status of the entire transconductor circuit  100  when the input voltage Vin is “0”. The first and second constant current sources Idc 1  and Idc 2  supply the first through fourth MOS transistors M 1  through M 4  with constant bias so that the first through fourth MOS transistors M 1  through M 4  operate in saturation regions. The variable voltage supply  130  sets the DC voltage Vdc so that all of the first through fourth MOS transistors M 1  through M 4  operate in the saturation regions and simultaneously the fifth and sixth MOS transistors M 5  and M 6  operate in sub-threshold regions. In other words, gate-source voltages Vgs of the fifth and sixth MOS transistors M 5  and M 6  are slightly lower than a threshold voltage Vth.  
         [0041]     The operation of the transconductor circuit  100  will now be explained.  
         [0042]     As shown in  FIGS. 3 and 4 , when an absolute value of the input voltage Vin of the transconductor circuit  100  is smaller than a constant voltage Va, the first through fourth MOS transistors M 1  through M 4  of the main circuitry  110  operate in their saturation regions, and the fifth and sixth MOS transistors M 5  and M 6  of the auxiliary circuitry  120  operate in the sub-threshold regions. A current of fine intensity then flows through the third and fourth resistors R 3  and R 4 . As a result, a current flowing through the fifth and sixth MOS transistors M 5  and M 6  hardly affects an entire output current of the transconductor circuit  100 .  
         [0043]     When the input voltage Vin is greater than the constant voltage Va, the second input voltage Vinp increases more than the first input voltage Vinn. Thus, a current flowing through the first MOS transistor M 1  is reduced, which boosts a drain voltage of the first MOS transistor M 1 . As a result, the gate-source voltage Vgs of the fifth MOS transistor M 5  increases, and thus the fifth MOS transistor M 5  enters the saturation region. A drain current of the fifth MOS transistor M 5  in the saturation region increases more than when the input voltage Vin is “0”. Thus, the output current lout of the transconductor circuit  100  increases more than when the auxiliary circuitry  120  does not exist. As a result, transconductance Gm of the transconductor circuit  100  remains constant, and thus the distortion of the output current lout is compensated. Here, the sixth MOS transistor M 6  operates in the stronger sub-threshold region and a current flowing through the sixth MOS transistor M 6  is very fine, which hardly affects the entire output current.  
         [0044]     In other words, as marked with “C3” of  FIG. 4 , the transconductance Gm of the conventional transconductor circuit  10  is considerably reduced when the input voltage Vin is greater than the constant voltage Va. However, in the present invention, when the auxiliary circuitry  120  is connected to the main circuitry  110  and the input voltage Vin of the transconductor circuit  100  is greater than the constant voltage Va, the transconductance Gm of the transconductor circuit  100  remains almost constant as marked with “C1” of  FIG. 4 . As a result, the distortion of the output current is compensated.  
         [0045]     When the magnitude of the third and fourth resistors R 3  and R 4  is relatively low, i.e., several Ω, channel lengths of the fifth and sixth MOS transistors M 5  and M 6  are too short, and the absolute value of the input voltage Vin is greater than the constant voltage Va, drain currents of the fifth and sixth MOS transistors M 5  and M 6  vary sharply. This may cause the output current to be distorted as marked with “C2” of  FIG. 4 . Therefore, the channel lengths and channel widths of the fifth and sixth MOS transistors M 5  and M 6  and the magnitude of the third and fourth resistors R 3  and R 4  must be determined in consideration of the magnitude of the transconductance Gm.  
         [0046]     When the input voltage Vin increases in a positive direction to be greater than a maximum input voltage Vmax, all bias currents supplied by the current source  140  flow through the second and fifth MOS transistors M 2  and M 5 , and currents do not flow through the first and sixth MOS transistors M 1  and M 6  any longer. Thus, the transconductance Gm, which is a variation in the output current, approaches “0”. When the input voltage Vin increases in a negative direction, the similar results may be obtained.  
         [0047]     Here, the voltage supplied by the variable voltage supply  130  satisfies both the following two cases. When the absolute value of the input voltage Vin is smaller than the constant voltage Va, the voltage supplied by the variable voltage supply  130  is set so that the fifth and sixth MOS transistors M 5  and M 6  operate in the sub-threshold regions. When the absolute value of the input voltage Vin is greater than the constant voltage Va, the voltage supplied by the variable voltage supply  130  is set so that at least one of the fifth and sixth MOS transistors M 5  and M 6  necessarily operates in the saturation region.  
         [0048]     Here, the constant voltage Va can be represented relative to the variable voltage supply  130  as in Equation 2: 
 
 Vdc+Gm·Va·R   1 = Vgs   3 + Vth   5    (2) 
 
 wherein Vgs 3  denotes a gate-source voltage of the third MOS transistor M 3  when the input voltage Vin of the transconductor circuit  100  is equal to the constant voltage Va and Vth 5  denotes a threshold voltage of the fifth MOS transistor M 5 . Here, since each of the main and auxiliary circuitries  110  and  120  is composed of a differential amplifier type, the first resistor R 1  has the same magnitude as the second resistor R 2 , and the third resistor R 3  has the same magnitude as the fourth resistor R 4 . In a simulation according to an aspect of the present invention, the constant voltage Va is about ⅔ of the maximum input voltage Vmax when the distortion of the entire output current is minimum. 
 
         [0049]      FIG. 5  is a circuit diagram of a transconductor circuit, according to another embodiment of the present invention. Referring to  FIG. 5 , a voltage controller  150  includes a seventh MOS transistor M 7  and a current source Ic. The seventh MOS transistor M 7  is a p-channel MOS (PMOS) transistor, a gate of which is connected to a node to which the third and fourth resistors R 3  and R 4  are commonly connected and a drain of which is grounded. The current source Ic is connected between a source of the seventh MOS transistor M 7  and a power voltage VDD. The current source Ic supplies the seventh MOS transistor M 7  with bias and the fifth and sixth MOS transistors M 5  and M 6  with the gate-source voltages Vgs.  
         [0050]     In other words, when the input voltage Vin is greater than a negative constant voltage −Va and smaller than the positive constant voltage Va, the current source Ic supplies the fifth and sixth MOS transistors M 5  and M 6  of the auxiliary circuitry  120  with bias so that the fifth and sixth MOS transistors M 5  and M 6  operate in the sub-threshold regions.  
         [0051]     Even when the variable voltage supply  130  of  FIG. 3  is constituted as the voltage controller  150  including the current source Ic and the PMOS transistor, the same effect can be achieved.  
         [0052]     As an aspect of the present invention, the first through sixth MOS transistors M 1  through M 6  of the transconductor circuit  100  of  FIG. 3  are n-channel MOS (NMOS) transistors. However, as another aspect, the first through sixth MOS transistors M 1  through M 6  may be PMOS transistors as shown in  FIG. 8 . In this case, polarities of the first and second constant current sources Idc 1  and Idc 2 , the voltage Vdc of the variable voltage supply  130 , and voltage supply sources (the power voltage VDD and ground) must be changed into opposite polarities.  
         [0053]     As an aspect of the present invention, the first through sixth MOS transistors M 1  through M 6  of the transconductor circuit  100  of  FIG. 5  are NMOS transistors, and the seventh MOS transistor M 7  is the PMOS transistor. However, as another aspect, the first through sixth MOS transistors M 1  through M 6  may be PMOS transistors, and the seventh MOS transistor M 7  may be an NMOS transistor as shown in  FIG. 9 . In this case, the polarities of the first and second constant current sources Idc 1  and Idc 2 , the current source Ic of the voltage controller  150 , and the voltage supply sources (the power voltage VDD arid ground) must be changed into opposite polarities.  
         [0054]     As another aspect, all of current sources of  FIGS. 3 and 5  may be simple MOS transistors.  
         [0055]      FIG. 6  is a graph for showing the results of a simulation for transconductance of the transconductor circuit  100 . The simulation was carried out in conditions that a power voltage of 1.8V was applied and an input voltage of the transconductor circuit  100  was biased by about 0.9V. A curve of the transconductance Gm of  FIG. 6  has the almost same shape as a curve of the transconductance Gm of  FIG. 4 . This indicates that the auxiliary circuitry  120  prevents the output current lout from being distorted.  
         [0056]      FIG. 7  is a graph for showing the results of a simulation for the distortion characteristics of the transconductor circuit  100 . In the simulation, an input frequency was set to 5 MHz, and a differential sine wave was input between the first and second input voltages Vinn and Vinp. The distortion characteristics will be described with total harmonic distortion (THD) of an output current that was analyzed in a frequency domain under the above conditions. As can be seen in  FIG. 7 , as the input voltage Vin increases, the transconductance Gm of the transconductor circuit  100  according to the present invention has a smaller THD value than the transconductance Gm of the conventional transconductor circuit  10 . This indicates that the distortion of the output current of the transconductor circuit  100  is reduced.  
         [0057]     As described above, in a transconductor circuit according to the present invention, an auxiliary circuitry is connected to an output node of a main circuitry that is a differential pair with source degeneration.  
         [0058]     The auxiliary circuitry includes a pair of MOS transistors and a pair of resistors and is designed so as to operate in a sub-threshold region at less than a constant input voltage and in a saturation region at more than the constant input voltage. Thus, a reduction in the linearity of an output current of the main circuitry can be compensated at more than the constant input voltage. As a result, the distortion of an output current of the transconductor circuit be prevented and a section in which the output current linearly increases can increase. Moreover, since the auxiliary circuitry includes the pair of MOS transistors and/or the pair of resistors, the auxiliary circuitry can have a quite simple structure. Thus, chips cannot occupy the large area and an operation speed cannot be lowered.  
         [0059]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.