Abstract:
A method and system is disclosed for demodulating multiple waveforms, with different modulation formats, in the same hardware by providing a software-configurable demodulator that configures itself in response to varying input waveform types. The system reconfigures its logic to accommodate the format of the signals being received and further allows for reconfiguration of demodulator functional block interfaces to remove downtime during multiple waveform processing.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to modulators and demodulators and, more particularly, to a method and apparatus for switching between multiple waveforms. 
   2. Description of Related Art 
   In recent years due to the rapid development of multimedia, digital, audio, and video communications applications, there is a necessity for efficient and reliable signal modulation and demodulation techniques to accommodate different modulation formats based on the media over which the signals are to be transmitted. For instance, with respect to high definition television, and in fact other types of advanced television transmissions, program material in video, data, or audio form is formatted by a channel encoder to be transmittable by Vestigial Side Band modulation or VSB which is typical for over-the-air television transmissions. Quadrature Amplitude Modulation or QAM is typically used for cable transmissions, whereas Quadrature Phase Shift Keying or QPSK is generally used in satellite communication. For radio communications Time-Division Multiplexing (TDM) modulation and error correction formats are utilized. Finally, discrete multitone or DMT techniques are typically used for telephone landline signaling such as with Asymmetric Digital Subscriber Lines or ADSL. It will be appreciated that when a video source at the transmit side is encoded through a source coding unit, the source coding unit is set up to code the video source material in one of the four above-mentioned modulation formats. Likewise, on the receive side in order for a receiver to decode all of the above mentioned formats discrete VLSI chips or detectors can be provided in parallel, with the outputs going to source decoding. 
   It is apparent that receivers utilized for processing multiple modulation formats utilize a series of demodulators each configured to demodulate a particular format. This duplication of demodulators is costly and may suffer technical problems such as switching transients and cross modulation between different demodulators. 
   Furthermore, in a radio (modem) application, where characteristics such as modulation type, data rate, error correction coding, etc, are required to change quickly during operation, prior art methods of processing multiple-modulation formats can result in loss of data and dataflow. 
   It will be thus appreciated that any parallel processing solution to the problem of multiple modulation formats generally involves increased hardware complexity and increased cost. 
   It is therefore an object of the present invention to provide a receiver capable of demodulating multiple modulation formats without losing data or interrupting dataflow, the receiver containing a single demodulator with re-configurable logic therein. 
   It is a further object of the present invention to provide a method for demodulating multiple waveforms of different characteristics, in a software defined demodulator, without losing data or interrupting dataflow. 
   It is still a further object of subject invention to demodulate multiple waveforms in the same hardware by providing a re-configurable software defined demodulator that reconfigures itself in response to varying input waveform configuration parameters. 
   SUMMARY OF THE INVENTION 
   The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings. 
   In accordance with one embodiment of the present invention a method for switching between multiple waveforms in a software defined receiver is provided. The method includes demodulating a plurality of input waveforms within a first and second demodulator period, respectively, within software configurable hardware. The software configurable hardware is defined by a plurality of functional blocks having input nodes, output nodes, and feedback nodes. The method includes receiving a first input waveform and determining the modulation format type of the first input waveform. The method also includes generating a first configuration instruction based upon the modulation format type to the software configurable hardware. Next, the method configures the software configurable hardware in accordance the configuration instruction. The method also includes receiving a second input waveform and determining a second modulation format type of the second input waveform. The method then generates a second configuration instruction based on second modulation format type and configures the software configurable hardware in accordance with the configuration instruction. The method determines if the software configurable hardware contains a feedback node; and opens the feedback node during the second demodulator period if the first configuration instruction is different from the second configuration instruction. 
   In accordance with one embodiment of the present invention, a system in which information is transmitted from a send side to a receive side over a communications channel is provided. The receive side includes software configurable logic circuits and feedback loops with means for determining a modulation format type; and means for demodulating the transmitted information. The means for demodulating includes generating instructions including modulation format configuration data based on the modulation format configuration data and feedback loops. 
   The invention is also directed towards a program storage device tangibly embodying a program of instructions executable by the machine for demodulating multiple waveforms within software configurable hardware. The software configurable hardware defined by a plurality of functional blocks, having input nodes, output nodes, and feedback nodes: the feedback nodes defining feedback loops within the hardware. The instructions include determining a modulation format type of a first input signal during a first demodulation period and generating a first configuration instruction to the software configurable hardware during the first demodulation period, based on the modulation format type. The instructions also include configuring the software configurable hardware during the first demodulation period to the modulation format type specified by the first configuration instruction. The software configurable hardware includes logic elements whose functionality is capable of being changed in software. The instructions also include determining a modulation format type of a second input signal during a second demodulation period and generating a second configuration instruction to the software configurable hardware during the second demodulation period, based on the second modulation format type. The instructions configure the software configurable hardware during the second demodulation period to the modulation format type specified by the second configuration instruction. Finally, the instructions determining if said software configurable hardware at said second demodulator time frame contains a feedback node; and opens the feedback node during the second demodulator period if the first configuration instruction is different from the second configuration instruction. 
   In accordance with another embodiment of the present invention, a demodulation system for fast demodulation of a first waveform and a second waveform is provided. The demodulation system includes a plurality of programmable functional units, each of the plurality of programmable functional units adapted to process the second waveform upon completion of processing the first waveform. The demodulation system also includes a waveform configuration controller coupled to the plurality of programmable functional units. 
   The invention is also directed towards an integrated circuit (IC) for demodulating a first waveform and a second waveform. The IC includes a programmable demodulator, having a plurality of programmable functional units programmable to process the second waveform upon completion of processing the first waveform. The IC also includes at least one waveform configuration controller adapted to reconfigure each of the plurality of programmable functional units in accordance with the first waveform or the second waveform. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and other features of the present invention are explained in the following description, taken in connection with the accompanying drawings, wherein: 
       FIG. 1  is a pictorial diagram of a communication system incorporating features of the present invention; 
       FIG. 2  is a block diagram of a communications system implementing subject invention within a Modulator/Demodulator (MODEM); 
       FIG. 3  is a block diagram of a communications system with the receiver side of  FIG. 2  (illustrated in broken lines) showing the utilization of a configuration controller, configuration RAM and a configurable demodulator; 
       FIG. 4  is a detailed view of the demodulator of subject invention shown within broken lines  40 ; and 
       FIG. 5  is a hardware configuration timeline illustrating the method of waveform switching of subject invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Overview 
   Generally, local and remote computers communicate over a transmission medium by way of computer modems. Referring to  FIG. 1 , a modem/demodulator  12   c   4  is contained in a hub communication system  12  or a modem/demodulator  14   c   4  in a spoke communication system  14  as shown in  FIG. 1  communication system  10 . An information source  15  generating digital or analog images, video, or speech, is converted into a bit stream by source encoder  20  and data compressed prior to being input to channel encoder  25  of modem  10 . Channel encoder  25  introduces redundancy in the binary information sequence that can be used at the receiver to overcome the effects of noise and interference encountered in the transmission of the signal over communications channel  35 . The added redundancy serves to increase the reliability of the received data and is introduced through convolutional codes, turbo codes, and interleaving for channels with burst errors. The binary sequence is next input to digital modulator  30  for conversion into a signal waveform suitable for output over communications channel  35 . This channel includes free space for wireless communications or physical media, such as telephone lines, for communication over telephone channels. 
   At the receiving end, digital demodulator  40  reduces the modulated signal waveform to a binary sequence for input to channel decoder  45  which reconstructs the original signal sequence from knowledge of the codes used by the channel encoder  25  and the redundancy contained in the received data. Source decoder  50  decompresses the original signal for output  55 . 
   Referring to  FIG. 3 , receiver circuitry including digital demodulation circuit  40  is illustrated within dotted lines  40 A. It is understood that the receiver circuitry  40 A may be implemented in a Field Programmable Gate array (FPGA) that can be programmed to support demodulation of multiple waveforms. This software-defined demodulation utilizes mirrored RAMs and Registers to store the “current” and “next” waveform parameters during the demodulation process. As different waveforms enter the receive side  40 A the switching from mode to mode (or waveform to waveform) occurs gradually throughout the demodulator  40 , the demodulator  40  processing and delaying the control signals throughout the demodulation process. 
   In one embodiment, a software configurable demodulator is implemented using a general purpose microprocessor and is software-reconfigured in accordance with the output of a configuration RAM. 
   In summary, a method and apparatus for switching between multiple waveforms has a software configurable demodulator which accommodates different modulation formats such as those associated with terrestrial, cable, phone line, satellite and wireless communications to be received through a single device which has configurable logic to accommodate the format of the signals being received. The system detects the modulation format of the incoming signal and reconfigures the logic of its software-configurable demodulator to output demodulated digital data for further processing. The incoming signal is A/D converted, with a host processor utilized to detect the type of modulation associated with the incoming signal and through a configuration controller configures a random access memory, which is coupled to the software-configurable demodulator. 
   Referring to  FIG. 4 , as multiple waveforms pass through the demodulation stage  40 , functional blocks  70  through  110  are reconfigured or switched to utilize configuration parameters necessary to demodulate the current waveform. Functional blocks  70  through  110  are individually reconfigured to utilize new parameters when the last sample from the current waveform exits the block and the first sample from the next waveform enters the block. Feedback loops are also reconfigured (opened and closed) to support the processing of the current and next waveforms throughout the demodulation. 
   Waveforms such as AEHF, multi-mode, and frequency hopped require several very different demodulation characteristics to support them. Implementing a software defined demodulation method in an FPGA requires minimal hardware, and provides enhanced data integrity by minimizing loss of data, timing and downtime. 
   Referring now to  FIG. 1 , there is shown a block diagram of a communication system that can advantageously incorporate features of the present invention.  FIG. 1  shows a full-duplex system  10  that is suitable for practicing this invention. Specifically, the system  10  employs direct sequence spread spectrum based techniques over an air link to provide data transfer between HUB  12  and SPOKE  14 . The forward link (FL) from HUB  12  to SPOKE  14  contains a spread spectrum waveform, with the PN code being composed of even-length and/or maximal length codes. In a similar manner, the return link (RL) from SPOKE.  14  to HUB  12  contains a spread spectrum waveform that is similar, or identical, to that of the FL. 
   Still referring to  FIG. 1 , HUB  12  includes a Spread Spectrum Modulator/Demodulator Modem (SSM)  12   b ; the SSM  12   b  generates a desired spread spectrum waveform at a desired RF frequency. The SSM  12   b  also provides a Tx clock  12   d  that is used to clock the Tx Data  12   e  into the SSM  12   b . The SSM  12   b  then combines the Tx data  12   e  with a spread spectrum PN code to produce the desired spread spectrum waveform. HUB  12  also includes an antenna  12   a , which may transmit at any suitable RF frequency. 
   The signal generated by HUB  12  and transmitted by antenna  12   a  via the FL is received by SPOKE  14  via antenna  14   a . Spoke  14  includes a spread spectrum correlator  14   c   1 , PN generator  14   c   2 , clock generator  14   c   3 , and spread spectrum demodulator (SSD)  14   c   4 . The received signal is then demodulated by SSD  14   c   4 . Once the signal is acquired and the SPOKE  14  is tracking the received signal, the Rx Clock  14   g  and Rx Data  14   f  are output to the intended receiver circuitry. 
   Similarly, SPOKE  14  generates a Tx Clock  14   d  and Tx Data  14   e  using the Spread Spectrum Modulator  14   b  in a similar fashion described earlier for HUB. Likewise, HUB  12  may receive the RL signal via antenna  12   a , and demodulate and track the signal as described earlier with receiver  12   c  to provide Rx Data  12   f  and Rx Clock  12   g  to the intended user. 
   Referring also to  FIG. 2 , modem  12   b  contained in communication system such as shown in  FIG. 1 , is further illustrated within broken lines, and described herein. An information source  15  generating digital or analog images, video, or speech, is converted into a bit stream by source encoder  20  and data compressed prior to being input to channel encoder  25  of modem  10 . Channel encoder  25  introduces redundancy in the binary information sequence that can be used at the receiver to overcome the effects of noise and interference encountered in the transmission of the signal. The added redundancy serves to increase the reliability of the received data and is introduced through convolutional codes, turbo codes, and interleaving for channels with burst errors. The binary sequence is next input to digital modulator  30  for conversion into a signal waveform suitable for output over communications channel  35 . This channel includes free space for wireless communications or physical media, such as telephone lines, for communication over telephone channels. 
   In receive mode, digital demodulator  40  reduces the modulated signal waveform to a binary sequence for input to channel decoder  45  which reconstructs the original signal sequence from knowledge of the codes used by the channel encoder  25  and the redundancy contained in the received data. Source decoder  50  decompresses the original signal for input to output transducer  55 . 
   Referring to  FIG. 3 , the receiver  40 A of subject invention is illustrated within broken lines  40 A. The receiver  40 A, which is software-reconfigurable, has as an input to front end  40 B a signal having a unique modulation format. The primary purpose of the front end is level adjustment, amplification, and filtering of the incoming modulated signals  30 . The output of front end  40 B is coupled to A/D converter  40 C, and thence to a software-configurable demodulator  40 . In one embodiment, the header of the input signal is stripped off and provided to a host processor  40 D, which determines from flags in the header the modulation format type. 
   The output of host processor  40 D specifies the modulation format to configuration controller  40 F, which then selects from configuration RAM  40 E the appropriate demodulation mode to be downloaded to demodulator  40 . It is understood that other methods for determining modulation format type that are known in the art may be utilized in subject invention. Demodulator  40  also provides feedback to host processor  40 D of demodulator  40  interface and configuration status necessary for reconfiguration of the demodulator to support multiple waveform processing described in the following paragraphs. 
   Referring also to  FIG. 4 , digital demodulator  40  (see  FIG. 2 ) is illustrated within broken lines. The demodulator circuit  40  is illustrative of a typical demodulator used in the art, however, subject invention may utilize various demodulator circuits containing various functional blocks and loops. A typical demodulator circuit  40  includes various functionality such as digital down conversion  70 , filter/decimation  75 , timing recovery  80 , matched filtering  80 A, timing error detecting  85 , loop filtering  90 ,  105 , numerically controlled oscillating  95 , 110  and phase error detecting  100 . Referring to  FIG. 4 , demodulator  40  is illustrated within broken lines and includes phase and frequency recovery loop  41  and symbol timing recovery loop  42 . 
   As multiple waveforms pass through the demodulator  40 , functional blocks  70  through  110  shown in demodulator  40  are reconfigured or switched to demodulate multiple waveforms. Functional blocks  70  through  110  are individually reconfigured via waveform configuration controller  40   z  to utilize suitable demodulation parameters when the last sample from the current waveform exits each functional block  70  through  110  and the first sample from the next waveform enters each functional block,  70  through  110 . Blocks  70  through  110  process and delay waveform control signals as multiple waveforms pass through demodulator  40 . 
   Feedback loops are also reconfigured (opened and closed) to support the processing of the current and next waveforms throughout the demodulation. In one embodiment, demodulator  40  is provided with an array of gates, arithmetic logic units or ALUs, registers and other circuit blocks, elements or modules to provide a circuit to recover the associated carrier. 
   In alternate embodiments, at a higher level, the demodulator may be configured in layers, with each layer containing gates and logic as well as filtering to provide a circuit specially tailored for carrier recovery of a different modulation format type. The configuration RAM  40 E shown in  FIG. 3  selects which of the layers is to be activated, thereby taking advantage of embedded demodulation logic in each of the layers. 
   Referring also to  FIG. 5  there is shown a waveform-timing diagram illustrating features of the present invention. At time T, waveform “A” is illustrated as passing through Demodulator  40 . Configuration RAM  40 E has downloaded the appropriate Demodulation mode parameters to all Demodulator  40  functional blocks through Configuration RAM  40 E. At time T+1 waveform “B” enters Digital Down Converter  70  with Configuration RAM  40 E loading waveform “B” demodulation parameters for Digital Down Converter  70  only. At this point, two waveforms are being demodulated concurrently in Demodulator  40  and previous demodulator functional block settings for waveform “A” remain unchanged. Demodulator  40  feeds back demodulator configuration settings from Demodulator Functional Blocks  70 , 75 ,  41 ,  42 , and  80 A into host processor  40 D at each time period T+N (where N=0, 1, 2, 3 . . . ). 
   Host processor  40 D then processes the current and next demodulator settings information and determines demodulation format settings for output to configuration controller  40 F. Furthermore, host processor  40 D utilizes the current and next demodulator program settings to control the opening and closing of loops in the system, thereby allowing concurrent processing of multiple waveforms. At time T+2, waveform “B” enters Decimation Filter  75  and Configuration RAM  40 E, via command from host processor  40 D, loads waveform “B” parameters into decimation filter  75  only. At time T+3, waveform “B” enters phase/frequency loop  41  and configuration RAM  40 E, via command from host processor  40 D, loads waveform “B” parameters into the functional blocks contained within loop  41 , then opens loop  41 . Loop  41  is opened to prevent waveform “A” and “B” data from processing in the same loop. Blocks  70  through  110  process and delay waveform control signals as multiple waveforms pass through demodulator  40 . 
   The feedback information from demodulator  40  includes the current waveform parameter settings and allows host processor to compare current and next waveform parameters. If host processor detects different waveforms in the same loop it will open the loops for a time period sufficient enough to allow the current waveform to pass through, then close the loop for the next waveform processing. At Time T+4, waveform “B” data enters symbol timing loop  42  and configuration RAM  40 E, via command from host processor  40 D, loads waveform “B” parameters into loop  42  functional blocks then opens loop  42  to prevent waveform “A” and “B” data from processing in the same loop. At time T+5, host processor detects that waveform “A” has exited both loops  41  and  42 , and commands configuration RAM  40 E to close loops  41  and  42 . 
   At time t+5 waveform “A” has been demodulated with only waveform “B” currently being processed in demodulator  40 . The method of reconfiguring the demodulator would continue for subsequent waveform “C”, “D”, etc., inputs into receiver  40 A. 
   It is understood that the present invention might be embodied in many alternate forms of embodiments, e.g., MODEMS, receiver&#39;s etc. In addition, it should be understood that the teachings herein may apply to any group or assembly of receivers, including those that are fixed in place; vehicle mounted; and/or hand carried. 
   In addition, in alternate embodiments features of the present invention may be implemented in a programmable device such as an integrated circuit (IC). It will be further appreciated that the IC may be a field programmable gate array (FPGA), an application specific IC (ASIC), or a function of firmware. The operation of the ICs or firmware may be defined by a suitable programming language such as a Very High Speed Integrated Circuit (VHSIC) Hardware Description (VHDL) Language file. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances that fall within the scope of the appended claims.