Abstract:
There is disclosed herein an apparatus for verifying the correct placement of a wire wrap tool on a wire wrap pin in an array of pins. An outside source of pin and condition data such as a human operator operating switches or a mechanical sequential state machine or a hand wired logic sequential state machine supplies binary data indicating the correct pin and the expected electrical condition to be found on the correct pin. A wire check system interface means in combination with a wire wrap tool, a strip switch and a number of HDMUG logic boards then subject the correct pin to the expected electrical condition and compare the electrical condition on the pin actually touching the wire wrap tool to the expected electrical condition and signals the correctness or incorrectness of placement of the wire wrap tool.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates generally to the field of electrical computers and data processing systems and more particularly to the field of computerized testing and evaluation of performance for quality control purposes. 
     It is believed by the applicant that the disclosed apparatus is the first of its kind to be developed. Other wire wrap aids have been developed but none perform the functions of the invention described herein with respect to verifying that the operator is on the right pin. For example, the WWM-380 wire wrapping machine manufactured by Standard Logic, Inc. will, by alphanumeric display, tell the operator what pins to wrap wires from and to but will not verify that the right pins have been wrapped. This is of some assistance to wire wrap operators in relieving them of the necessity of averting their eyes from a very complicated and dense array of pins to a prolix and densely packed wire list. The prior art system allows the operator to see only one line at a time from the wire list in a large brightly lit alphanumeric display, but no verification of placement of the wire wrap tool on the right pin is provided as in the disclosed invention. The pin verification and board test functions of the disclosed invention represent major advances in the state of the art. 
     SUMMARY OF THE INVENTION 
     Broadly speaking, the system comprises a first means for supplying binary pin data indicating which pin in an array of wire wrap pins is the correct pin for one operation in a particular wiring transaction and for supplying condition data indicating a predetermined expected electrical condition (such as ground or +5 volts potential or some voltage in between) on the pin touched by the operator. A second means then decodes the binary data indicating the correct pin and subjects the correct pin to a predetermined electrical condition. It then compares the expected electrical condition as derived from the condition data from the first means to the electrical condition on the pin actually touched and generates a signal indicative of whether the pin touched was correct. 
     In the preferred embodiment, the first means is a programmed digital computer which retrieves binary pin and condition data from a magnetic storage media or other memory and sends it to the second means. However, in other embodiments the pin and condition data could be supplied from any outside source of data such as a human operator pushing buttons, a mechanical sequential machine or a hard wired, clocked, sequential state logic device. Other embodiments might also subject only the correct pin to the predetermined electrical condition instead of a periodically spaced cluster of pins one of which is the correct pin. Still other embodiments might subject the cluster or correct pin to a predetermined electrical condition such as a voltage or current and then compare this to a fixed standard as opposed to comparison with the condition data supplied from the microprocessor in the preferred embodiment. 
     More specifically, the system consists of a microprocessor or other digital computer (CPU) linked in combination with a cassette tape handler, a printer, a terminal and a Wire Check System Interface which serves to link the wire wrap tool, strip switch and the board to be verified to the CPU. The gist of the invention lies in the Wire Check System Interface in combination with the CPU, the wire wrap tool having a wrapping element made of electrically conductive material, the strip switch, and the board under test. It is this interface which allows the microprocessor to verify that the wire wrap tool has been placed on the proper pin and that completed boards are properly wired. Three specially designed interface boards accomplish this task as follows. 
     The wire wrapped backplane which is to be updated or wired from scratch consists of a large board having a wire wrap pin side and a logic board side. The various logic boards comprising the computer have edge connectors which are inserted into sockets on the logic board side of the backplane. The logic board side is divided into ten &#34;buckets&#34;, each bucket holding ten logic boards. The buckets are divided evenly between an &#34;A&#34; and a &#34;B&#34; side. 
     The other side or wire wrap pin side of the backplane contains hundreds of wire wrap pins which are connected to the sockets holding the logic boards. Wires connect the wire wrap pins of the various buckets thereby linking the various logic boards together to complete the circuitry of the computer. 
     The invention substitutes a number of HDMUG boards for the logic boards of a computer normally inserted in the card slots in the logic board side of the backplane. Each HDMUG board is the same and consists of a diode matrix. Individual card and bucket addresses are assigned to each HDMUG board by the use of jumpers. The purpose of the HDMUG boards is to connect a selected cluster of pins to ground through a resistor when so directed by the microprocessor during a wire transaction. 
     Another interface board in the microprocessor, MMUGS, serves to convert the binary information on the microprocessor data bus to binary card, bucket, and cluster information when addressed by the microprocessor. 
     A SUGS2 board decodes the card, bucket, and cluster information and generates single line signals to select the HDMUG board in the desired card and bucket location embracing one pin involved in the wire transaction to be verified and it grounds the appropriate cluster of pins. 
     Finally, a SUGS1 board serves to compare the voltage sensed on a particular pin by the tip of the wire wrap tool with an analog signal supplied by the microprocessor through a digital to analog converter. If the voltage on the pin is as it should be, the microprocessor lights a green LED on the wire wrap gun. If not, then a red LED is lit. 
     The software in the microprocessor also causes it to display data needed for each wire transaction and print various reports. 
     The advantages of elimination or substantial reduction in wire wrap errors and substantial cost reduction in manufacturing, updating, and debugging of wire wrapped backplanes inherent in use of the present invention should be readily apparent. A more detailed understanding of how these advantages are achieved may be had by consideration of the following drawings and detailed description of the preferred embodiment. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a drawing of the logic board side of the backplane. 
     FIG. 1B is a drawing of the wire wrap pin side of the backplane. 
     FIG. 2 is a block diagram of the overall system. 
     FIGS. 3A and 3B are logic diagrams of the MMUGS interface board. 
     FIG. 4 is a logic diagram of the SUGS2 interface board. 
     FIG. 5 is a logic diagram of the SUGS1 interface board. 
     FIG. 6 is a logic diagram of the HDMUG interface board. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIGS. 1A and 1B illustrate the wire wrap pin side (1B) and the logic card side (1A) of the backplane to be verified. FIG. 1A shows the logic card side to be divided into ten &#34;buckets&#34; 100 through 109. Each bucket has ten card slots 110 as typically illustrated for bucket 100. Each card slot has numerous electrical contacts each of which is connected to a wire wrap pin on the reverse side of the backplane. These wire wrap pins are arranged typically in a matrix as shown in FIG. 1B. Each electrical contact in the card slots makes contact with another electrical contact on the backplane edge of a logic card of the end product computer unit. However, in the present invention in order to verify the proper wire wrapping of the subject backplane, 100 HDMUG boards, illustrated in FIG. 6, are inserted into the 100 card slots of the ten buckets. 
     Each of these HDMUG boards has an individual card and bucket address, however they are all wired the same and jumpers are used, as shown in FIG. 6, to give each HDMUG board a unique card and bucket address. The purpose of these HDMUG boards is to decode binary pin data i.e. cluster selection signals or cluster data sent over cables AA and AB from the Wire Check System Interface (WCSI). WCSI merely passes this binary cluster information through from the CPU from which it was originally part of the binary pin data comprised of card, bucket and cluster data. The cluster data is passed to the HDMUG board having the proper card and bucket address specified in the original binary pin data. The HDMUG board then uses the decoded binary cluster data to subject a particular cluster of pins, one of which is the proper pin for one operation in a wire transaction to a predetermined electrical condition. In the preferred embodiment, this electrical condition is grounding through a 1K resistor. The card and bucket information on cables AA and AB pick the bucket and card contacting one of the pins involved in the particular wire transaction one pin at a time first for the &#34;from&#34; pin then for the &#34;to&#34; pin. The software in the preferred embodiment is set up so that when the operator is ready to verify he or she merely depresses strip switch 111 (in FIG. 2). The condition of the strip switch is relayed to the WCSI, 112 in FIG. 2, along line 113 in FIGS. 2 and 5. 
     Line 113 goes to the SUGS1 board of the WCSI illustrated in FIG. 5. It is seen there that the strip switch 111 serves to float or ground point 115 causing line 113 to be in either the logical one or zero state because of the presence of pull-up resistor 114. Inverters 116 and 117 and line driver 118 prepare this logical one or zero for transmission along line 119 to the MMUGS board plugged into the backplane of microprocessor 120 in FIG. 2. Depression of the strip switch lowers line 119 and release thereof raises the line. 
     Line 119 enters Port B of PPI 121 of the MMUGS board illustrated in FIG. 3B. It also is connected to two &#34;one shots&#34;. When the strip switch 111 is depressed, the lowering of line 119 clears the one microsecond one shot 123 at the clear input 124. When the strip switch is released, the rising edge on line 119 triggers the fifty millisecond one shot, 122, at the positive going input 125. One shot 122 then sends a positive going pulse of fifty millisecond duration out from the Q output. This Test Sw. Dly. signal on line 126 is connected to the negative transition input of one shot 123 and, when line 126 returns low, causes one shot 123 to send a negative going pulse of one microsecond duration out from the Q output as the Test Sw. $ signal on line 127. This low going pulse sets an interrupt bit in Port C of PPI 121 signaling the microprocessor 120 that the strip switch has been depressed and a pin needs to be verified. 
     The software is set up to service these interrupts by accessing the data for a particular wire transaction and emitting a data word on data bus 128 in FIG. 3A. This data word will be written to an address such that address bus lines 10 through 15, 129 in FIG. 3A, are decoded by decoder 130 to cause the DADR-B4 line to go low. Prior to this write operation, decoder 130 had held both the DADR-B4 and DADR-Bφ lines high. When DADR-B4 goes low on line 135, the ENB-Iφ signal on line 136 goes high since the DADR-Bφ input to gate 131 is still high. Prior to this write, line 136 had been low, keeping line 137 high and bus drivers 133 and 134 in the high-Z state. The lowering of line 137 enables these bus drivers and, in conjunction with the IOR signal on line 138 from the microprocessor control bus, causes transfer of the data word to I/O DAT lines 0-7 in FIGS. 3A and 3B. These lines enter the data bus port of PPI&#39;s 121 and 139. 
     This data must be directed somewhere. DADR-B4 on line 135 and address bus lines 8 and 9 serve this purpose. With DADR-B4 low and address bus lines 8 and 9 both low, PPI 139 is selected and the data is directed to the A port to become the card and bucket binary addresses. 
     Referring now to the logic diagram of the SUGS2 board shown in FIG. 4, it is seen that the card and bucket information enters SUGS2 via cable 140. The information is decoded in several decoders (which can be 74LS145&#39;s) and is sent out over cable AA or AB to select the proper HDMUG board connected to the pin in question. 
     As noted earlier, each HDMUG board has a unique card and bucket address. Referring to FIG. 6, it is seen that the unique address is provided for each HDMUG board by changing the connections of jumpers 141 and 142. FIG. 6 as drawn shows jumper connections for card zero in bucket zero on the &#34;A&#34; side of the backplane. A similar address exists for card zero and bucket zero on the &#34;B&#34; side of the backplane except the card Bφ and bucket Bφ lines from cable BB would be jumpered to the Card Sel and Bucket Sel lines. In FIG. 6 it is seen that when the card Aφ and bucket Aφ lines go low, the Card Sel and Bucket Sel lines go low causing OR gate 143 to drive the ENB DCDR line low. When this happens, decoder 144 is enabled such that binary cluster information reaching it on the cluster A*, B* and C* lines may be decoded into a low signal on any of the cluster 1, 2, 3, 4 or 5 lines. A low on any one of these lines causes the relay coil (145 or 146 or 147 or 148 or 149) connected to the line (155-159) to energize, closing the corresponding relay contact (150-154) responsive to the energized coil. When one of these relay contacts closes, the corresponding diode cluster connected to one of the five output lines 155-159 is connected to ground through the relay contact and a one thousand ohm resistor such as 161. 
     Referring again to FIG. 4, the TEST ENB and BUCKET D lines combine in OR gates 162 and 163 to create the ENB GRPA and ENB GRP B signals. ENB GRPA goes low when both BUCKET D and TEST ENB go low, which occurs under software control when the proper data words are written into ports A and C of PPI 139 in preparation for testing a pin. When ENB GRPA goes low, the A side bucket decoder 164 is enabled as are the A side cluster gates 165-7. The software then can write the proper data word into port B of PPI 139 in FIG. 3B to select the cluster embracing the pin to be verified. The pin data i.e. bucket, card and cluster data, is derived from a data base record taken from cassette player 168 in FIG. 2, which is compiled from a wire list drawing which lists the wire adds and deletes for a particular job. 
     The cluster concept is used in the preferred embodiment since the system is designed only to verify that the operator has placed the wire wrap gun on the correct pin and not to find the pin in the first place. This concept assumes that the operator can get close to the correct pin using human senses and relies on the operator&#39;s ability to get within a few pins horizontally and a few pins vertically of the correct pin. Other embodiments might use circuitry to subject only the correct pin to the predetermined electrical condition. 
     To illustrate let us refer to FIG. 1B, where a selection of a cluster of pins is illustrated by &#34;X&#39;s&#34; on the pins. For example, every fifth pin may be selected. If it is assumed that the WD section of pins is the first section, cluster zero can start at pin zero thereof and consist of every fifth pin, e.g., pins 00, 05, 10, etc. Likewise, cluster one can start at pin 01 and include every fifth pin, e.g., 01, 06, 11, etc. Therefore, it is seen that for the operator to get a &#34;correct pin&#34; green LED when she was actually on the wrong pin would require a compound mistake of being either one pin over and several pins up or down from the correct pin or in the right row but five pins off. 
     When the operator is ready to test her placement of the wire wrap gun, she presses strip switch 111. As noted earlier in conjunction with the discussion of FIGS. 5 and 3B, depression of the strip switch causes a negative going pulse from one shot 123 to propagate down the Test Sw. $ line in FIG. 3B to PC6 of port C of PPI 121. PPI 121 was initialized by the software at power up to make port A an output and port B an input port. A control word was also written in the bit set/reset format for the Intel 8255 to set INTE A inside the port by setting PC 6 . PC 5  on pin 12 was initially set at logical one to cause inverter 169 to present a logical zero at one input to NAND gate 170 thereby preventing interrupts during the power up period while the ports are in the high Z state prior to initialization. PC 5  is set at zero and stays there as soon as PPI 121 is initialized thereby enabling interrupts. The ENB TEST INT signal from PC 3  is under control of PPI 121 and goes high when Test SW $ goes low thereby causing NAND gate 170 to interrupt the microprocessor via the TEST INT on line 171. 
     When the microprocessor (CPU) is interrupted, it enters a subroutine to service the test request. This subroutine can be programmed in many different ways but its function is to supply the condition data in the form of the DAC 0-7 signals to the WCSI to inform it of the electrical condition expected to be seen by the WCSI on the pin touched by the operator. WCSI then compares the expected electrical condition to that actually found on the pin touched by the operator in SUGS1 and generates an output signal, Sense Bit 173, from SUGS1 indicative of whether the condition found was as expected. The subroutine then reads the output from SUGS1, SENSE BIT, PPI 121, FIG. 3B. In the preferred embodiment the expected electrical condition takes the form of a voltage. The subroutine lights a green LED on line 250 if the voltage on the pin corresponds to the correct voltage as determined by digital to analog conversion of the condition data word from the data base on the DAC 0-7 lines. If the voltage on the pin is not correct, the red LED will be lit. Whether the voltage was correct or not is determined by the microprocessor which reads the Sense Bit signal coming into port B on line 173. One digital state indicates a correct reading and the other an incorrect reading. The TEST SW input to pin 25 of port B on line 119 enables the software to read the state of the switch at any desired time in the program. 
     SUGS1, illustrated in FIG. 5, functions to make the voltage comparison noted above. Digital to analog converter 174 receives the data word through lines DAC 0-7 and converts it to a current signal the magnitude of which indicates the level of voltage which should be seen at the pin by the metal probe of the wire wrap tool. Operational amplifier 175 serves to convert the current signal from the D/A converter 174 into an output voltage on line 178. Operational amplifier 176 serves as a unity gain isolation amplifier to transmit the voltage at junction 180, representing the pin signal to line 179. The voltage at junction 180 will be approximately 2.5 volts if the wire wrap gun 177 is on one of the pins of the cluster selected by the HDMUG board. Recall from the discussion of FIG. 6 that when a cluster is selected, all the pins therein are connected to ground through a one thousand ohm resistor thereby forming a voltage divider with resistor 201 and dividing the +5 Volts in half. 
     Comparator 181 serves to compare the voltages on lines 178 and 179 and has an open collector output connected by line 182 to pull-up resistor 183 and a positive five volt supply. Comparator 181 grounds line 182 when one of its inputs exceeds the other. The Sense Bit signal on line 173 is derived from the signal on line 182 through line driver 185. As noted earlier, the Sense Bit signal goes to port B of the MMUGS board for analysis by the microprocessor. In other embodiments an output signal from SUGS1 might be used to light the red or green LEDS. 
     The circuitry connected to pins 1, 2, 14 and 15 of the digital to analog converter 174, which can be a Motorola MC1408C, is used to provide a precise current reference source to the digital to analog converter 174. Resistors 185 on the DAC side of D/A converter 174 serve as pull-up resistors for open collector line drivers at the MMUGS board (not shown in FIG. 3A or 3B). 
     Two comparisons are made for each pin test. In the first, a high value of voltage is written onto line 178 by D/A converter 174 and the voltage on line 179 is checked to see if it is less. Another comparison is made when the D/A converter writes a low voltage onto line 178 to ensure that the voltage on line 179 is greater. In this way a bracketing of the pin voltage is obtained and a wiring error can be prevented if a voltage outside the brackets is sensed. 
     Although the invention has been described in terms of a preferred embodiment, those skilled in the art may devise other equivalent means of performing the same function using any of a number of new products appearing on the market periodically. It is intended that these equivalent embodiments be included.