Abstract:
A temperature-compensated current source includes a first arm fixing a reference voltage, a second arm fixing a reference current, and a third arm providing an output current obtained by copying the reference current in a first current mirror. A second current mirror copies, in the voltage reference arm, the reference current while a voltage copying circuit copies the reference voltage at a node of the second arm connected to ground by a first resistor series-connected with n parallel-connected diodes. A second resistor is parallel-connected with the assembly formed by the first resistor series-connected with the n parallel-connected diodes.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to temperature-compensated current sources, and more particularly, to the optimization of a current reference circuit providing temperature compensation for the generated current.  
         BACKGROUND OF THE INVENTION  
         [0002]    The possibility of obtaining transistors with practically identical characteristics has given rise to a new generation of current sources known as current mirrors. A rise in the temperature leads especially to the following results: an increase in the leakage currents of the transistors used in such current reference circuits, an increase in the stored charge, and an increase in gain, etc.  
           [0003]    These phenomena, among others, involve a modification of the intrinsic characteristics of the transistors implemented in the current sources, resulting in the copied currents not being accurate. The current generated in such a current source is therefore dependent on the temperature variations. It is difficult to obtain a current reference source giving a constant current that is not sensitive to variations in temperature. To illustrate this phenomenon, referring now to FIG. 1, we shall look at the drawing of a standard prior art current source using complementary metal oxide semiconductor (CMOS) technology.  
           [0004]    The prior art current source includes three arms: b 1 , b 2  and b 3 . The middle arm b 2  is a current reference arm whose role is to fix a reference current. The third arm b 3  is an output arm in which the reference current Iref is copied. The role of the first arm b 1  is to fix a reference voltage V 1 .  
           [0005]    The current reference arm b 2  comprises a first MOS transistor M 2  whose source electrode is connected to a voltage supply terminal VDD, and whose gate electrode and drain electrode are connected to each other. The MOS transistor M 2  therefore makes it possible to fix a reference current in the first and third arms b 1  and b 3 .  
           [0006]    The drain electrode of the first MOS transistor M 2  is connected to the source electrode of a second MOS transistor M 5 , whose drain electrode is connected at a node N to the potential V 2  grounded by a first resistor R 1 . The first resistor R 1  is series-connected with a set of n parallel-connected elements Q 2  enabling a voltage V 3  to be fixed, with n being an integer at least equal to two. According to a preferred embodiment of the invention, each parallel-connected element Q 2  is formed by a diode. More precisely, it is a MOS transistor whose parasitic bipolar effects are used to form the diode.  
           [0007]    The output arm b 3  of the current source includes a MOS transistor M 3  whose source is connected to the power supply terminal VDD, and whose gate is connected to the gate of the MOS transistor M 2  of the current reference arm b 2 . Thus, by copying the reference current fixed by the current reference arm (b 2 ) into the current mirror M 2 , M 3 , the output current Iref of the current source is provided at the drain of the transistor M 3 .  
           [0008]    The arm b 1  of the current source comprises a first MOS transistor M 1  whose source electrode is connected to the supply terminal VDD. The gate electrode of the transistor M 1  is connected to the gate electrode of the transistor M 2  of the current reference arm b 2  of the current source, thus forming a second current mirror. The current generated in the current reference arm b 2  is copied in the arm b 1 , and the currents flowing in the arm b 1  and in the arm b 2  are thus equal. The drain electrode of the MOS transistor M 1  is connected to the source electrode of a second MOS transistor M 4 , whose gate electrode is connected to the gate electrode of the MOS transistor M 5  of the current reference arm b 2 . Furthermore, the gate electrode of the transistor M 4  is connected to its source electrode.  
           [0009]    Finally, the drain electrode of the transistor M 4  is grounded by an element Q 1  that is used to fix the voltage V 1 , and is identical to each of the n parallel-connected elements Q 2  of the arm b 2 . Thus, according to a preferred embodiment, Q 1  is a MOS transistor whose stray bipolar effects are used to form a diode.  
           [0010]    The MOS transistors M 4  and M 5  make it possible for the first and second arms to be symmetrical, respectively b 1  and b 2 , and form a voltage copying circuit which permits the copying of the reference voltage V 1  fixed by the diode Q 1  at the node N at the potential V 2  of the arm b 2 , so that V 2 =V 1 .  
           [0011]    The configuration of the MOS transistors M 1 , M 2 , M 4  and M 5  as described above therefore makes it possible to obtain equal currents I 1  and I 2  respectively flowing in the arms b 1  and b 2  of the current source, as well as equal voltages V 1  and V 2 , according to a well-known principle of operation that needs no detailed description herein.  
           [0012]    Consequently, the difference in potential ΔV at the terminals of the resistor R 1  may be expressed as follows:  
                 Δ                 V     =            V2   -   V3                 =            V1   -   V3                  
                           
 
           [0013]    According to a standard equation governing operation of the bipolar transistors, we have:  
           V 1 = VT *ln(I 1 /Is 1 ), and  
           V 3 = VT *ln(I 2 / n *Is 2 )  
           [0014]    Is 1  and Is 2  are the saturation currents of the diode-mounted transistors Q 1  and Q 2 , and VT is the thermal voltage which physically corresponds to the ratio between the coefficient of diffusion of the charges and the mobility of the charges, and can be expressed as follows:  
       VT   =       k   *   T     q                           
 
           [0015]    The variable k is Boltzman&#39;s constant, T is the temperature (in degrees Kelvin) and q is the elementary charge.  
           [0016]    Numerically, k=1,381*10 −23  J*K −1  (Joules per Kelvin) and q=1,602*10 −19  C (coulombs). Consequently:  
         Δ                 V     =         k   *   T   *   ln     q            [   I1     Is1     *         n   *   Is2     ]     I2                             
 
           [0017]    The diode-mounted transistors Q 1  and Q 2  are advantageously designed to be identical so as to present the same physical properties, hence Is 1 =Is 2 . Furthermore, we have already seen above that, by current copying, the currents I 1  and I 2  are identical. The potential difference ΔV at the terminals of the resistor R 1  can then be expressed as follows:  
         Δ                 V     =         k   *   T     q     *     ln        (   n   )                               
 
           [0018]    The current I 2 , generated by the potential difference ΔV at the terminals of the resistor R 1  and flowing through the arm b 2 , is expressed conventionally by the following relationship:  
       I2   =       Δ                 V     R1                           
 
           [0019]    Now, by copying the current in the MOS transistor M 3 , the currents Iref and I 2  are identical. Consequently:  
             Iref   =         k   *   T     q     *       ln        (   n   )       /   R1               (   1   )                               
 
           [0020]    Here we can understand the value of placing n transistors Q 2  in parallel since, without this characteristic and through simplifying the equations, the output current Iref of the current reference source would be theoretically zero.  
           [0021]    The above relationship (1) clearly shows that the current Iref varies linearly with the temperature T (in the ideal case where the value of the resistor R 1  does not vary with the temperature), and the variation of the current Iref as a function of the temperature is expressed according to the following expression:  
           δ                 Iref       δ                 T       =       k   q     *       ln        (   n   )       /   R1                             
 
           [0022]    A prior art current source of this kind therefore raises a problem of stability of the reference current given in relation to the temperature. This aspect may prove to be an inherent defect in many applications.  
         SUMMARY OF THE INVENTION  
         [0023]    An object of the present invention to overcome the drawbacks of the prior art by improving the current sources of the type described in FIG. 1 so that the given reference current is independent of the temperature.  
           [0024]    This and other objects, advantages and features according to the present invention are provided by implementation of a current reference circuit whose temperature-related stability depends directly on a ratio of resistances, enabling compensation for the temperature-related variations in the reference current based upon the respective resistance values.  
           [0025]    The invention therefore relates to a temperature-compensated current source comprising a first arm fixing a reference voltage by using a diode, a second arm fixing a reference current, and a third arm providing a temperature-stable output current. The temperature-stable output current is obtained by copying, in a first current mirror, the current fixed by the second current reference arm.  
           [0026]    A second current mirror is designed for copying, in the first voltage reference arm, the current fixed by the second current reference arm, while a voltage copying circuit copies the reference voltage fixed by the first arm at the level of a node of the second arm connected to ground by a first resistor.  
           [0027]    The first resistor is series-connected with n parallel-connected diodes. The current source is characterized in that the second current reference arm furthermore comprises a second resistor parallel-connected with the assembly formed by the first resistor series-connected with the n parallel-connected diodes so that the variations of the reference current are compensated based upon the respective values of the first and second resistors. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    Other features and advantages of the present invention shall appear more clearly from the following description, given by way of an illustration that in no way restricts the scope of the invention and made with reference to the appended drawings, of which:  
         [0029]    [0029]FIG. 1 is a schematic drawing of a current source according to the prior art;  
         [0030]    [0030]FIG. 2 is a schematic drawing of a temperature-compensated current source according to the present invention;  
         [0031]    [0031]FIG. 3 is a schematic drawing illustrating a particular embodiment of the temperature-compensated current source in FIG. 2; and  
         [0032]    [0032]FIG. 4 is a schematic drawing illustrating another particular embodiment of the temperature-compensated current source in FIG. 2. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]    [0033]FIG. 2 illustrates the temperature-compensated current source according to the present invention. The description of the structural and functional characteristics already made above with reference to FIG. 1 illustrating a prior art current source can be applied to the circuit of FIG. 2. A difference between the current source according to the invention and the prior art circuit of FIG. 1 is in the addition of a resistor R 2  that is parallel-connected with the arm formed by the resistor R 1 , which is series-connected with n parallel-connected diodes. The additional arm formed by the resistor R 2  is connected between ground and the node N at the potential V 2 , and conducts a current I 3 .  
         [0034]    A physical approach may be implemented in a first stage. This reasoning is based on the currents flowing in the different arms of the circuit, and their variations as a function of the temperature. According to a known characteristic of bipolar transistors, an increase in the temperature T prompts a reduction of the voltage at the terminals of a bipolar transistor, and more specifically, of the base-emitter voltage. This reduction of the voltage at the terminals of a bipolar transistor with respect to the temperature is about −2 mV/° C. (millivolts per degree Celsius).  
         [0035]    Thus, an increase in the temperature T causes a reduction of the potential V 1 . The potential V 1  is fixed by the diode Q 1 , which is formed by using the parasitic bipolar effects of a MOS transistor, which are used as a diode. Since the potential V 1  serves as a reference for the potential V 2 , the latter also falls when the temperature T rises. Thus, the difference in potential at the terminals of the resistor R 2  diminishes. This leads to a reduction in the current  13  flowing through the arm formed by the resistor R 2  by the application of Ohm&#39;s law.  
         [0036]    In the other parallel-connected arm formed by the resistor R 1  series-connected with the n parallel-connected diodes Q 2 , an increase in the temperature T leads to an increase in the value of the current I 2  traveling through this arm. The current I 2  is linked to the temperature T by the relationship (1) provided above with reference to FIG. 1. According to this relationship, I 2 =[(k*T)/q]*ln(n)/R 1 .  
         [0037]    Setting aside the variations in the value of the resistance with the temperature, which are not taken into account here, the current I 2  therefore varies linearly with the temperature, and in the same sense as the temperature. In view of the respective variations in the currents I 2  and I 3  as a function of the temperature, it can be seen that, by properly sizing the resistors R 1  and R 2 , it is possible to obtain a constant-temperature total current I 2 +I 3  through the transistors M 2  and M 5 , and therefore, by copying through the MOS transistor M 3 , a constant-temperature reference current Iref.  
         [0038]    The result (1) has made it possible to establish the following relationship:  
         I   2     =         k   *   T     q     *       ln        (   n   )       /     R1   .                               
 
         [0039]    It can be determined therefrom that the current variation I 2  as a function of the temperature T is set up as follows:  
           δ                 I2       δ                 T       =       k   q     *       ln        (   n   )       /     R1   .                               
 
         [0040]    It is recalled here that, with reference to FIG. 2 illustrating the preferred embodiment of the invention, the variations in the resistance values as a function of the temperature T are not taken into account. Also, in considering the arm formed by the resistor R 2 , the current I 3  may be expressed as follows:  
       I3   =       V2   R2     =     VBE1   R2                             
 
         [0041]    VBE 1  corresponds to the base-emitter voltage of the parasitic bipolar of the MOS transistor used to form the diode Q 1 .  
         [0042]    Given that, as seen above, for a bipolar transistor we have δVBE/δT=−2 mV/° C., the variation of the current I 3  as a function of the temperature may be expressed as:  
           δ                 I3       δ                 T       =       -   2     *       10     -   3       /     R2   .                               
 
         [0043]    Since the reference current Iref is equal to the sum of the currents I 2  and I 3  by copying through the MOS transistor M 3 , the relationship expressing the variation of the reference current as a function of the temperature can then be established as follows:  
                 σ                 Iref       σ                 T       =         k   q     *       ln        (   n   )       /   R1       -     2   *       10     -   3       /     R2   .                   (   2   )                               
 
         [0044]    The ratio δIref/δT must then be made zero to ensure the consistency of the reference current Iref with respect to the temperature. To do this, it is necessary to properly size the respective resistors R 1  and R 2  so as to obtain an adequately sized ratio between the two respective resistors R 1  and R 2 , thus enabling the cancellation of the above expression (2). For example, for n=8, namely eight diode-mounted transistors Q 2  in parallel, the ratio obtained is R 2 =11*R 1 . This ratio between the two resistors R 1  and R 2  must necessarily be applied in the implementation of the current source to obtain the constancy in temperature of the reference current Iref.  
         [0045]    The invention therefore proposes a straightforward, low-cost approach to optimize the prior art current reference circuit as described in reference to FIG. 1, and thus make it possible, by the addition of only one element, to obtain a temperature-stable circuit. By setting the respective values of the resistors R 1  and R 2 , the temperature-related current variations may be compensated for so that they can provide a temperature-stable reference current. The current source according to the present invention is first, independent of the temperature, and second, very stable with respect to the variations in the manufacturing method since its stability depends on a ratio of resistances.  
         [0046]    [0046]FIG. 3 shows a particular embodiment of the invention that is designed particularly for adaptation to the non-ideal case where the variations in the resistance values as a function of temperature are taken into account. This type has the direct consequence of introducing second-order terms into the equation (2). The approach described above with reference to FIG. 2 does not permit compensating for these second-order terms. The stability of the current source is therefore lowered when these second-order terms are considered.  
         [0047]    To overcome this problem, the particular embodiment of the invention referred to in FIG. 3 includes the addition of the second resistor R 2  to the current reference arm b 2  directly in parallel with the set of n diode-mounted transistors Q 2  in parallel. This particular configuration advantageously gives a substantial reduction in the second-order temperature drift of the reference current given by the source according to the invention, as above, based upon the ratio of the resistors R 1  and R 2 . Since the theoretical modeling of this approach is done by a non-linear system of equations, it is not presented here, given the complexity of the computations to be performed.  
         [0048]    However, again considering a system that takes account of the variations in the resistance values as a function of the temperature, a higher stability of the current may further be obtained with respect to the second-order drift in temperature through the configuration of FIG. 4. FIG. 4 illustrates another particular embodiment of the invention.  
         [0049]    In this embodiment, the current reference arm b 2  described with reference to FIG. 3 is cascaded. In other words, an additional arm b 2 ′ is interposed between the arm b 2  and the output arm b 3  of the current source according to the invention. The additional arm b 2 ′ has exactly the same structure as the current reference arm b 2 , and therefore comprises the same elements connected in the same way.  
         [0050]    Thus, the arm b 2 ′ has a first MOS transistor M 2 ′ whose source electrode is connected to the supply VDD, and whose gate electrode and drain electrode are connected to each other. The gate electrode of M 2 ′ is also connected to the gate electrode of the MOS transistor M 3  so as to copy the current I 2 ′ generated in the arm b 2 ′ at the drain electrode of the transistor M 3  with Iref=I 2 ′.  
         [0051]    The drain electrode of the transistor M 2 ′ is connected to the source electrode of a second MOS transistor M 5 ′, whose gate electrode is connected to the gate electrode of the transistor MS of the arm b 2 . Finally, the drain electrode of the second transistor M 5 ′ of the additional arm is connected to a node N′ grounded by a first resistor R 1 ′ series-connected with a set of n/2 diode-mounted MOS transistors Q 2 ′ in parallel, to which a second resistor R 2 ′ is directly connected in parallel.  
         [0052]    In this configuration, the resistor R 2 ′ is therefore positioned directly in parallel with the set of n/2 diodes Q 2 ′ just as, in the arm b 2 , the resistor R 2  is positioned directly in parallel with a set of n/2 diodes Q 2 . Since efficient compensation is achieved for different ratios R 2 /R 1  and R 2 /R 1 ′, the principle of this approach compensates for the two arms in opposite ways so as to stabilize the current in terms of the temperature. The resistor R 2 ′ can then be optional.