Abstract:
A circuit board structure comprising a composite layer, a fine circuit pattern and a patterned conductive layer is provided. The fine circuit pattern is inlaid in the composite layer, and the patterned conductive layer is disposed on a surface of the composite layer. After fine circuit grooves are formed on the surface of the composite layer, conductive material is filled into the grooves to form the fine circuit pattern inlaid in the composite layer. Since this fine circuit pattern has relatively fine line width and spacing, the circuit board structure has a higher wiring density.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 97117556, filed on May 13, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a circuit structure and a manufacturing process for a circuit board. More particularly, the present invention relates to a circuit structure and manufacturing process for a circuit board having higher wiring density. 
     2. Description of Related Art 
     A conventional circuit board is mainly formed by alternately stacking a plurality of patterned conductive layers and a plurality of dielectric layers, wherein the patterned conductive layers are electrically connected through a plurality of conductive vias. Discriminated based on fabrication processes of the circuit boards, the fabrication processes mainly include a laminating process and a build-up process. Generally, the circuit boards with lower wiring density are mainly fabricated based on the laminating process, and the circuit boards with higher wiring density are mainly fabricated based on the build-up process. 
       FIGS. 1A-1G  are profile flowcharts illustrating a conventional fabrication process for a circuit board. Referring to  FIG. 1A , conductive layers  110   a  and  110   b  are respectively disposed on two opposite surfaces of a dielectric layer  100 , wherein material of the dielectric layer  100  can be epoxy resin or epoxy resin containing glass fiber, and material of the conductive layers  110   a  and  110   b  is copper. 
     Referring to  FIG. 1B , a plurality of through holes  112  (only one is illustrated) is formed in the dielectric layer  100  and the conductive layers  110   a  and  110   b , and the way of forming the through holes  112  can be mechanical drilling or laser ablating. 
     Referring to  FIG. 1C , a conductive wall is formed on the surface of the through holes  112  by electroplating, so as to form a conductive through via  114 , and meanwhile an electroplating layer is respectively formed on the surfaces of the conductive layers  110   a  and  110   b , and the two electroplating layers are respectively belonged to the conductive layers  110   a  and  110   b.    
     Referring to  FIG. 1D , the conductive layers  110   a  and  110   b  are patterned by a photolithography and etching process, so as to form the circuit patterns. 
     Referring to  FIG. 1E , dielectric layers  120   a  and  120   b  are respectively formed on the patterned conductive layers  110   a  and  110   b , and openings  116   a  and  116   b  are fabricated on the dielectric layers  120   a  and  120   b  by mechanical drilling or laser ablating. 
     Referring to  FIG. 1F , conductive material is filled in the openings  116   a  and  116   b  by electroplating, so as to form a plurality of conductive micro via  118   a  and  118   b,  and meanwhile conductive layers  130   a  and  130   b  are respectively formed on the dielectric layers  120   a  and  120   b , wherein the conductive micro via  118   a  and  118   b , and the un-patterned conductive layers  130   a  and  130   b  are formed by electroplating. 
     Referring to  FIG. 1G , the un-patterned conductive layers  130   a  and  130   b  are patterned by the photolithography and etching process. Next, a patterned solder mask  140   a  is formed on the patterned conductive layer  130   a , and a plurality of joint pads  142  of the patterned conductive layer  130   a  is exposed. Moreover, a patterned solder mask  140   b  is formed on the patterned conductive layer  130   b , and a plurality of joint pads  143  of the patterned conductive layer  130   b  is exposed. Finally, fabrication of a circuit board structure  150  is finished. 
     According to the above conventional fabrication process of the circuit board, the circuit board is formed by alternately stacking a plurality of the patterned conductive layers and a plurality of the dielectric layers. However, due to limitation of the conventional fabrication process for the circuit board, i.e. limitation of line width and spacing of a fine circuit, a wiring density of the circuit board fabricated based on the aforementioned method cannot be increased. Moreover, during fabrication of the circuit board, the wiring density of the circuit board is directly related to a possible arranging density of the joint pads provided by the circuit board, wherein function of the joint pads is to lap-joint pins of chips, and function as a medium for signal transmission and power supply. Therefore, with gradually increasing trend for number and density of the pins of an integrated circuit (IC) chip, how to provide a higher wiring density on the circuit board has become one of the major R&amp;D directions in fabrication of the circuit boards. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a circuit board structure and a fabrication process thereof, which may increase a wiring density of a circuit board. The technical knowledge of the present invention is uniquely challenging or difficult for one of ordinary skill in the conventional art. 
     The present invention provides a circuit board structure including a dielectric layer, a fine circuit pattern and a patterned conductive layer, wherein the fine circuit pattern is inlaid to a surface of the dielectric layer, and the patterned conductive layer is disposed on another surface of the dielectric layer. 
     The present invention provides a fabrication process for a circuit board. The fabrication process includes following steps. First, a dielectric layer is provided. Next, a fine circuit groove is formed on a surface of the dielectric layer. Next, conductive material is filled in the fine circuit groove to form a fine circuit pattern, and a patterned conductive layer is formed on another surface of the dielectric layer. 
     The present invention provides a circuit board structure including a composite layer, a fine circuit pattern and a second patterned conductive layer. The composite layer at least includes two dielectric layers and a first patterned conductive layer, wherein the first patterned conductive layer is disposed between the two dielectric layers. Moreover, the fine circuit pattern is inlaid in a surface of the composite layer, and the second patterned conductive layer is disposed on another surface of the composite layer. 
     The present invention provides a fabrication process for a circuit board. The fabrication process includes following steps. First, a composite layer is provided, wherein the composite layer at least includes two dielectric layers and a first patterned conductive layer, and the first patterned conductive layer is disposed between the two dielectric layers. Next, a fine circuit groove is formed on a surface of the composite layer. Next, conductive material is filled in the fine circuit groove to form a fine circuit pattern, and a second patterned conductive layer is formed on another surface of the composite layer. 
     In an embodiment of the present invention, while the fine circuit groove is formed, at least one opening is also formed on the dielectric layer where the fine circuit groove is about to be formed, and a portion of the first patterned conductive layer is exposed. While the conductive material is filled in the fine circuit groove, the conductive material is also filled in the openings, so as to form a conductive micro via. 
     In an embodiment of the present invention, the step of filling the conductive material in the fine circuit groove and the opening includes electroplating. 
     Accordingly, while the fine circuit pattern is inlaid in the dielectric layer or the composite layer, since a conductive circuit having a fine line width and spacing can be fabricated, wiring density of the circuit board structure can be increased. 
     In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, an embodiment accompanied with figures is described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIGS. 1A-1G  are profile flowcharts illustrating a conventional fabrication process for a circuit board. 
         FIGS. 2A-2F  are profile flowcharts illustrating a fabrication process for a circuit board according to a first embodiment of the present invention. 
         FIGS. 3A-3F  are profile flowcharts illustrating a fabrication process for a circuit board according to a second embodiment of the present invention. 
         FIGS. 4A-4F  are profile flowcharts illustrating a fabrication process for a circuit board according to a third embodiment of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     First Embodiment 
     In the first embodiment of the present invention, fabrication process of a circuit board with double conductive layers is described.  FIGS. 2A-2F  are profile flowcharts illustrating a fabrication process for a circuit board according to a first embodiment of the present invention. 
     Referring to  FIG. 2A , a plate utilized in the beginning of the fabrication process can be a dielectric layer  200 , and the material thereof can be epoxy resin or epoxy resin containing glass fiber. 
     Referring to  FIG. 2B , fine circuit grooves  200   a  are formed on a surface of the dielectric layer  200  by for example, laser ablating, and at least one through hole  212  is formed in the dielectric layer  200  by mechanical drilling or the laser ablating. 
     Referring to  FIG. 2C , the conductive material (for example, copper) is filled in the fine circuit grooves  200   a  by for example, electroplating, so as to form a fine circuit pattern  210  inlaid in the surface of the dielectric layer  200 . Moreover, while the conductive material is filled by electroplating, a conductive layer  220   a , a conductive layer  220   b  and a conductive via  222  are formed on surfaces of the dielectric layer  200  and the through hole  212 . In the present embodiment, the conductive via  222  does not fill up the whole through hole  212 , but forms a hollow cylinder. 
     Referring to  FIG. 2D , the conductive layer  220   a  is removed by for example, grinding, and the required fine circuit pattern  210  is remained. 
     Referring to  FIG. 2E , the un-patterned conductive layer  220   b  is patterned by for example, a photolithography and etching process, so as to form a patterned conductive layer  220   b.    
     Referring to  FIG. 2F , a patterned solder mask  230   a  is formed on the fine circuit pattern  210 , and a plurality of joint pads  232   a  on the fine circuit pattern  210  is exposed. Moreover, a patterned solder mask  230   b  is further formed on the patterned conductive layer  220   b , and a plurality of joint pads  232   b  on the patterned conductive layer  220   b  is exposed. Finally, fabrication of a circuit board structure  240  is finished. 
     In the first embodiment, formation of the patterned conductive layer  220   b  is based on a subtractive process, and in other embodiments of the present invention, formation of the patterned conductive layer can also be based on an additive process or a semi-additive process. 
     Second Embodiment 
     In the second embodiment of the present invention, fabrication process of a circuit board with double conductive layers is described.  FIGS. 3A-3F  are profile flowcharts illustrating a fabrication process for a circuit board according to a second embodiment of the present invention. 
     Referring to  FIG. 3A , a plate utilized in the beginning of the fabrication process can be a dielectric layer  300 , and the material thereof can be epoxy resin or epoxy resin containing glass fiber. 
     Referring to  FIG. 3B , fine circuit grooves  300   a  are formed on a surface of the dielectric layer  300  by for example, laser ablating, and at least one through hole  312  is formed in the dielectric layer  300  by mechanical drilling or the laser ablating. 
     Referring to  FIG. 3C , the conductive material (for example, copper) is filled in the fine circuit grooves  300   a  by for example, electroplating, so as to form a fine circuit pattern  310  inlaid in the surface of the dielectric layer  300 . Moreover, while the conductive material is filled by electroplating, a conductive layer  320   a , a conductive layer  320   b  and a conductive via  322  are formed on surfaces of the dielectric layer  300  and the through hole  312 . In the present embodiment, the conductive via  322  fills up the whole through hole  312 , and forms a solid cylinder. 
     Referring to  FIG. 3D , the conductive layer  320   a  is removed by for example, grinding, and the required fine circuit pattern  310  is remained. 
     Referring to  FIG. 3E , the un-patterned conductive layer  320   b  is patterned by for example, a photolithography and etching process, so as to form a patterned conductive layer  320   b.    
     Referring to  FIG. 3F , a patterned solder mask  330   a  is formed on the fine circuit pattern  310 , and a plurality of joint pads  332   a  on the fine circuit pattern  310  is exposed. Moreover, a patterned solder mask  330   b  is further formed on the patterned conductive layer  320   b , and a plurality of joint pads  332   b  on the patterned conductive layer  320   b  is exposed. Finally, fabrication of a circuit board structure  340  is finished. 
     In the second embodiment, formation of the patterned conductive layer  320   b  is based on the subtractive process, and in other embodiments of the present invention, formation of the patterned conductive layer can also be based on the additive process or the semi-additive process. 
     Third Embodiment 
     In the third embodiment of the present invention, fabrication process of a circuit board with multiple conductive layers (in the present embodiment, four conductive layers are applied) is described.  FIGS. 4A-4F  are profile flowcharts illustrating a fabrication process for a circuit board according to a third embodiment of the present invention. 
     Referring to  FIG. 4A , a plate utilized in the beginning of the fabrication process can be a composite layer  400  including three dielectric layers  401 ,  402  and  403 , two patterned conductive layers  404  and  405 , and at least one conductive via  406 . Material of the dielectric layers  401 ,  402  and  403  can be epoxy resin or epoxy resin containing glass fiber, etc., and material of the patterned conductive layers  404  and  405  can be coppers, etc. The conductive via  406  electrically connects the patterned conductive layers  404  and  405 , and has a shape of a hollow cylinder shown in  FIG. 4A  or a solid cylinder which is not shown. Since fabrication method of the composite layer  400  is similar to that in the conventional technique, and therefore detailed description thereof will not be repeated. 
     Referring to  FIG. 4B , fine circuit grooves  401   a  are formed on a surface of the composite layer  400  by the laser ablating, at least one opening  401   b  is formed in the dielectric layer  401 , and at least one opening  403   b  is formed in the dielectric layer  403  by mechanical drilling or the laser ablating. 
     Referring to  FIG. 4C , the conductive material (for example, copper) is filled in the fine circuit grooves  401   a  by for example, electroplating, so as to form a fine circuit pattern  410  inlaid in the surface of the composite layer  400 . Moreover, while the conductive material is filled by electroplating, a conductive layer  420   a , a conductive layer  420   b , a conductive micro via  412  and a conductive micro via  413  are formed on the surface of the composite layer  400 . 
     Referring to  FIG. 4D , the conductive layer  420   a  is removed via for example, grinding, and the required fine circuit pattern  410  is remained. 
     Referring to  FIG. 4E , the un-patterned conductive layer  420   b  is patterned by for example, a photolithography and etching process, so as to form a patterned conductive layer  420   b.    
     Referring to  FIG. 4F , a patterned solder mask  430   a  is formed on the fine circuit pattern  410 , and a plurality of joint pads  432   a  on the fine circuit pattern  410  is exposed. Moreover, a patterned solder mask  430   b  is further formed on the patterned conductive layer  420   b , and a plurality of joint pads  4332   b  on the patterned conductive layer  420   b  is exposed. Finally, fabrication of a circuit board structure  440  is completed. 
     In the third embodiment, formation of the patterned conductive layer  420   b  is based on the subtractive process, and in other embodiments of the present invention, formation of the patterned conductive layer can also be based on the additive process, wherein the additive process includes a full additive process and a semi-additive process. 
     In summary, according to the present invention, the fine circuit grooves are pre-formed on the surface of the dielectric layer (or the composite layer) by for example, the laser ablating, and then the conductive material is filled in the fine circuit grooves to form the fine circuit pattern. Next, the fine circuit pattern is taken as a patterned conductive layer of the circuit board and is electrically connected to other patterned conductive layers by the through holes or micro via. Therefore, the fabrication method of the present invention can be applied to the circuit board having two or more conductive layers. 
     Moreover, according to the present invention, the fine circuit pattern is formed on one side of the circuit board for providing a higher wiring density, and a general patterned conductive layer is formed on the other side of the circuit board for providing a general wiring density. Therefore, when the circuit board functions as a carrier (carrier board) for IC chips, the IC chips is disposed on only one side of the circuit board, and the fine circuit pattern can be formed on the same side for providing the higher wiring density, and the general conductive layer can be formed on other side of the circuit board for providing the general wiring density. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.