Abstract:
A test and measurement Instrument samples an input digital logic signal to produce logic samples, compresses the logic samples into compression codes, and stores the compression codes into acquisition memory. Compression includes parsing the logic samples into groups and assigning compression codes to those groups, and is performed so as not to lose information about the input digital logic signal&#39;s activity. The instrument converts the stored compression codes into a waveform image in display memory and displays the stored waveform image on a display device.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates generally to test and measurement instruments for digital logic signals, and more specifically to methods of compressing logic samples for storage.  
       BACKGROUND OF THE INVENTION  
       [0002]     Test and measurement instruments such as logic analyzers and mixed signal oscilloscopes are used to measure the logic values of digital logic signals. These instruments sample the logic values of an input digital logic signal at time instants specified by a sampling clock, store the logic samples in an acquisition memory, convert the stored logic samples into a waveform image in display memory, and display the waveform image on a display device.  
         [0003]     One limitation of these instruments is their finite acquisition memory capacity. The acquisition memories are standard commercially available random access memories and, as such, are available in fixed capacities such as 64, 128, or 256 Mbytes. For example, the TLA7000 Series Logic Analyzer available from Tektronix, Inc. of Beaverton, Oreg. supports up to 256 Mbytes of acquisition memory.  
         [0004]     Users are occasionally interested in observing the behavior of the input digital logic signal over a time interval that exceeds the instrument&#39;s acquisition memory capacity. For example, consider a user interested in the behavior of a signal over three seconds, but the user&#39;s instrument is acquiring logic samples at 256 Mbytes/sec and has 256 Mbytes of acquisition memory. To display three seconds requires 3×256 Mbytes=768 Mbytes of acquisition memory, three times more than is available. In this situation, instruments typically “decimate” or discard some of the acquired samples to avoid overflowing the memory. For example, the instrument may decimate by a factor of three, storing only one of every three acquired samples and discard the remaining two. The resulting display is “aliased” in that it no longer contains all the sample data, but nonetheless it still provides useful information to the user. However, if the discarded samples contain important information about the signal (e.g. logic transitions) the decimated display misleads the user.  
         [0005]     Decimation is a very simple compression method, with the loss of information being a potential user trap. U.S. Pat. No. 6,473,700 to Holaday et al. for an “Apparatus for Use in a Logic Analyzer for Compressing Digital Data for Waveform Viewing” describes a more elaborate compression method. Holaday teaches conditioning a large number of logic samples stored in acquisition memory, for example, 256 Mbytes, for display on a raster scan type display with, for example, 1024 columns. Holaday&#39;s compression method parses the logic samples into groups (e.g. 256 Mbytes÷1024=250 k bytes per display column) and assigns each group a compression code based on whether the logic samples in the group were “always high”, “always low”, or “changed.” Holaday&#39;s compression method, unlike decimation, does not alias information. That is, in compressing 250 k samples into one display column Holaday does not preserve all of the details of the logic activity, but if, for example, a region contains logic transitions, Holaday accurately reports that the signal “changed,” as opposed to decimation which may show that the signal did not change. One might be led to think that Holaday could be applied in place of decimation to solve the memory capacity problem. However, because Holaday&#39;s purpose is to condition logic samples already stored in acquisition memory for display on a raster scan display device, Holaday relies on memory addresses corresponding to stored logic samples, and applies those memory addresses to comparators in order to parse the logic samples. In order to alleviate the problem of limited acquisition memory capacity, the logic samples must be compressed before they are stored in acquisition memory, and so Holaday is not applicable.  
         [0006]     What is needed is a compression method capable of operating on logic samples as they are acquired, in real time, before they are stored in acquisition memory, thereby allowing an instrument to store more information about an input digital logic signal than finite memory capacity ordinarily allows, without losing important information about the signal activity.  
       SUMMARY OF THE INVENTION  
       [0007]     Accordingly, in the present invention a test and measurement instrument samples an input digital logic signal to produce logic samples, compresses the logic samples into compression codes, and stores the compression codes into acquisition memory. Compression includes parsing the logic samples into groups and assigning compression codes to those groups, and is performed so as not to lose information in the input digital logic signal&#39;s activity. The instrument converts the stored compression codes into a waveform image in display memory and displays the stored waveform image on a display device.  
         [0008]     The advantages and novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawing. 
     
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0009]      FIG. 1  is a simplified high-level block diagram illustrating an instrument architecture that implements the present invention.  
         [0010]      FIG. 2  is an illustration showing an input digital logic signal, logic samples, compression codes, and a waveform image displayed on a display device in accordance with the present invention.  
         [0011]      FIG. 3  is a simplified high-level block diagram of an instrument architecture that uses a divider circuit to parse logic samples into groups in accordance with a second embodiment of the present invention.  
         [0012]      FIG. 4  is a timing diagram showing a relationship between a sample clock and the divider circuit output of  FIG. 2  for compression by a factor of three, useful for understanding the invention.  
         [0013]      FIG. 5  shows, in simplified schematic form, a circuit that implements the compression circuit of  FIG. 3 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]     Referring to  FIG. 1 , acquisition circuit  105  samples an input digital logic signal to produce logic samples by applying the input digital logic signal to one input of a comparator, the other input receiving a voltage corresponding to a decision threshold, and latching the output of the comparator at time instants specified by a sampling clock, as is well known in the art. Compression circuit  110  compresses the logic samples into compression codes, as described below. Acquisition memory  115  stores the compression codes. Waveform drawing circuit  120  produces a waveform image representative of the stored compression codes, which is stored in display memory  125 , and then displayed on display device  130 . Not shown are a sample clock (distributed to all elements as necessary), control circuitry, and circuitry that stores logic samples into acquisition memory without compression, as is well known in the art. The present invention compresses logic samples before their storage in acquisition memory  115 , rather than afterward, as is the case with Holaday, thereby allowing the instrument to overcome the fundamental limitation of its finite acquisition memory capacity.  
         [0015]     To avoid aliasing, compression circuit  110  must accurately report the input digital logic signal activity, but may sacrifice some information about the precise timing of that activity and even the nature of the activity, depending on the amount of compression used. This behavior can be accomplished using many different compression methods. One such method is to parse the logic samples into groups and assign each group a compression code based on the logic activity of the logic samples in the group. Four such assignments (and their binary representations) are “always high” (01), “always low” (00), “changed once” (10), or “changed multiple times” (11).  FIG. 2  illustrates how this method converts logic samples  210  (corresponding to an input digital logic signal  205  and decision threshold  270 ) in groups of three into compression codes  215 . For example, the first group of logic samples  235  (000) is represented by compression code  240  “always low.” The second group of logic samples  250  (011) corresponding to rising edge  225  is represented by compression code  255  “changed once.” At the first falling edge  275 , logic samples  280  (111) and  285  (000) could be assigned “always high” followed by “always low,” however the absence of the necessary “single transition” between them is misleading. To provide a more informative display, compression circuit  110  considers not only the logic samples in the immediate group but also the final logic value of the previous group. In this manner, since the last logic state before logic samples  285  (the final logic state of logic samples  280 ) is a logic one, compression circuit  110  assigns compression code  295  “single transition.” Likewise, since the last logic state before logic samples  280  is a logic one, compression circuit  110  assigns compression code  290  “always high.” The region of high signal activity  230  is assigned compression code  297  “changed multiple times” since logic samples  296  (010) change logic state more than once.  
         [0016]     To convert compression codes  215  into waveform image  220 , waveform drawing circuit  120  (implemented in either dedicated circuitry or software running on a processor) produces images representative of the logic activity indicated by the compression codes. For example, compression code  240  “always low” may be represented graphically by waveform image  245  representing a series of logic zeros, with the waveform image in this case being a 10×3 pixel image for simplicity. To produce a waveform image representing compression code  255  “changed once”, waveform drawing circuit  120  considers the final logic state of compression code  240  “always low” to determine that waveform image  260  should be rising edge. When a “changed once” group follows a “changed multiple times” group, the information has been lost as to whether the edge should be rising or falling so waveform drawing circuit  120  produces a “changed multiple times” waveform image, as in waveform image  270 .  
         [0017]     At the first rising edge  225  the compression method loses some information about the precise timing of the signal activity, in that the user is no longer able to discern in between which of the three logic samples  250  the transition occurred, only that it occurred somewhere within that group of three. Likewise, in the region of high signal activity  230  the compression method loses information about the exact nature of the signal transitions. That is, waveform image  265  does not indicate precisely what logic activity occurred, but the user is nonetheless able to discern that the input signal changed more than once.  
         [0018]     In  FIG. 2 , for each group of three logic samples, the instrument uses only two bits of acquisition memory to store the corresponding compression codes, rather than using three bits to store each group of logic samples directly, allowing a 33% reduction in memory usage. For greater memory savings, one may increase the amount of compression by increasing the number of samples in each group.  
         [0019]     The compression method of the present invention differs from that employed by Holaday because it recognizes the advantage of including an additional assignment, “changed state multiple times.” The additional assignment distinguishes between groups of samples in which many logic transitions occurred and groups of samples in which only one transition occurred, which provides a more useful display for the user. The present compression method is not inherently limited to four assignments, but can be extended to include more assignments.  
         [0020]     The present compression method may also be further re-applied to the compression codes after they have been stored in acquisition memory, if necessary, for the purpose of conditioning the stored compression codes for display on a display device.  
         [0021]     One advantage of the present compression method is that its simplicity makes it straightforward to implement in circuitry that operates at the sample rate of the instrument.  FIG. 3  illustrates a simplified high-level block diagram of instrument architecture  300  based on instrument architecture  100  that uses a divider circuit  335  to parse the logic samples into groups. Referring to  FIG. 4 , divider circuit  335  divides down a sample clock  400  to produce a divided sample clock  405  that is high for one clock cycle and low for a number of cycles, with the time interval between rising edges of the divided clock defining a “compression interval.” For compression by a factor of N, the divider output is high for one cycle and then low for N-1 cycles. For example, for compression by a factor of three, the divider circuit output is high for one cycle and then low for two cycles.  
         [0022]     Referring again to  FIG. 3 , each time divider circuit  335  produces a high output, compression circuit  310  starts forming a compression code. Compression circuit  310  continues to develop the compression code, examining the logic samples with every sample clock, while the output of the divider circuit  335  remains low. When divider circuit  335  produces another high output signal the compression code appears at the output of compression circuit  310 , causing acquisition memory  315  to accept the compression code and store it at a memory address specified by an address generator  340 . Address generator  340  then advances the memory address so that the next compression code is placed into the next memory address.  
         [0023]      FIG. 5  shows a detailed view, in schematic form, of compression circuit  310 . Not shown is a sample clock (distributed to all elements as necessary). Compression circuit  310  includes an inverter  505  which inverts the divided system clock and applies it to a first input of an AND-gate  530  and to a first input of an AND-gate  535 . The output of AND-gate  530  is connected to a first input of OR-gate  510 , and the output of AND-gate  535  is connected to a first input of OR-gate  520 . The output of OR-gate  510  is connected to the D of flip-flop  515 , and the output of OR-gate  520  is connected to the D of flip-flop  525 . The Q of flip-flop  515  is connected a second input of AND-gate  530  and the “11” input of priority encoder  560 . The Q of flip-flop  525  is connected a second input of AND-gate  535 , the “10” input of priority encoder  560 , and a first input of AND-gate  540 . Logic samples are applied to the D of flip-flop  545 . The Q of flip-flop  545  is applied to a first input of XOR-gate  555  and the D of flip-flop  550 . The Q output of flip-flop  550  is applied to a second input of XOR-gate  555  and the “01” input of priority encoder  560 . The output of XOR-gate  555  is applied to a second input of OR-gate  520  and a second input of AND-gate  540 . The output of AND-gate  540  is applied to a second input of OR-gate  510 . Priority encoder  560  produces a 2-bit value equal to its highest asserted input.  
         [0024]     In operation, when the divided sample clock goes high, flip-flop  515  and flip-flop  525  are forced low, which causes priority encoder  560  to assign “00” to the compression interval. When logic samples (clocked into compression circuit  310  on every sample clock) change state, the output of XOR-gate  555  goes high, which causes the flip-flop  525  to go high (and remain high for the remainder of the compression interval), which causes priority encoder  560  to assign “10” to the compression interval. If the logic samples change a second time during the compression interval, flip-flop  515  goes high (and remains high for the remainder of the compression interval), which causes priority encoder  560  to assign “11” to the compression interval. If the logic samples are high during the entire compression interval, priority encoder  560  assigns “01” to the compression interval.  
         [0025]     Thus, the present invention compresses logic samples as they are acquired, in real time, before they are stored in acquisition memory, thereby allowing an instrument to store more information about an input digital logic signal than its finite memory capacity ordinarily allows, without losing important information about the signal activity.