Abstract:
Graphene FETs exhibit low power consumption and high switching rates taking advantage of the excellent mobility in graphene deposited on a rocksalt oxide (111) by chemical vapor deposition, plasma vapor deposition or molecular beam epitaxy. A source, drain and electrical contacts are formed on the graphene layer. These devices exhibit band gap phenomena on the order of greater than about 0.5 eV, easily high enough to serve as high speed low power logic devices. Integration of this construction technology, based on the successful deposition of few layer graphene on the rocksalt oxide (111) with SI CMOS is straightforward.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The subject matter of this patent application was developed without Federal or State funding. Although the inventor named herein is the beneficiary of support from various corporate organizations, and is employed by a University at which he works on subject matter including the development and characterization of materials formed by the direct growth of graphene on various substrates, no University time, compensation or apparatus was employed, involved or relied on in the development of the subject matter disclosed and claimed herein. Thus, this invention and the claims presented herein reflect work done by the inventor without funding or support on the development of field effect transistors formed by graphene deposition. 
     Background of the Technology 
     Graphene displays electronic properties, including high room temperature carrier mobilities, long carrier mean free paths, [1-3]  polarizeability in proximity to a magnetic substrate [4]  and long spin diffusion lengths [5]  with exciting potential for charge or spin-based device applications. A critical step in practical device development, however, is the direct, controlled growth, by industrially feasible and scalable methods, of high quality single or few layer graphene films on dielectric substrates. Methods such as chemical or physical vapor deposition (CVD, PVD) or molecular beam epitaxy (MBE) are of interest, but must occur at growth temperatures allowing integration with Si CMOS or other device materials. Most reports, however, have involved graphene/substrate interfaces formed by one of two approaches: (a) physical transfer of graphene sheets—grown by CVD on metal substrates [6,7]  or taken from HOPG; [1,2]  or (b) the growth of graphene layers by high temperature evaporation of Si from SiC(0001). [8-10]  The former method presents significant problems for practical device production, including formation of nanoscale interfacial electronic inhomogeneities. [11]  The second method appears limited to SiC(0001) substrates. Recent reports of MBE graphene growth on SiC(0001) [12,13]  are also limited to SiC substrates. The ability to grow single or few layer graphene on oxides or other dielectric substrates of choice would not only enhance graphene integration with Si CMOS, but also facilitate the development of novel multifunctional non-volatile devices [14,15]  that exploit substrate functionality and graphene/substrate interactions. 
     SUMMARY OF THE INVENTION 
     This patent application describes a pathway to make faster, lower power field effect transistors using graphene deposited directly on a (111)-oriented oxide with the rocksalt structure. Previous studies 1-3  have shown that graphene grown directly on MgO(111) by free radical assisted chemical vapor deposition or by physical vapor deposition displays a band gap of ˜0.5 eV-1 eV, suitable for logic device applications. See, U.S. patent application Ser. No. 12/980,763, incorporated herein-by-reference. Specifically, a single layer of graphene on MgO(111) displays XPS evidence of strong bonding to the oxide substrate 2,3 . The LEED data shows that this layer displays three-fold, (C3V) rather than six-fold symmetry, as shown in  FIG. 1 . DC transport data for this (first carbon) layer shows semiconducting behavior with an estimated band gap at room temperature of ˜0.6 eV. This is corroborated by spectroscopic ellipsometry data showing the lack of a π→π* resonance common to graphene/SiO 2  or graphene/SiC 4 . Thus, the first layer of C(111) on MgO is NOT true graphene, in that the π system has been significantly affected by substrate interactions and (probably) rehybridization of the carbon atoms to something like sp x  where 2&lt;x&lt;3. 
     Importantly, the evidence for C3V symmetry implies that the graphene/MgO interface is commensurate. If it were not commensurate, then the A sites and B sites on the graphene lattice would each sample an ensemble of substrate environments, yielding equivalent A site/B site average environments. In contrast, a commensurate interface would have A site carbon atoms (e.g.) on atop oxygen sites of the MgO substrate, and with B carbon sites over (e.g.) hollow sites on the substrate. Such a scheme is shown schematically in  FIG. 2 , and is consisted with the XPS and LEED data. Since the lattice O—O nearest neighbor distance for both MgO(111) and Co3O4(111) is 2.8-2.9 Å, vs. the graphene lattice constant of 2.46 Å, the commensurate nature of the graphene/MgO(111) surface indicates oxide and or C(111) reconstruction. It is known that MgO(111) and other rocksalt oxide (111) surfaces (e.g., NiO(111)) are unstable and prone to reconstruction, especially upon metallization 5 . 
     The second layer of C(111) on MgO(111) appears to be graphene like, as indicated by the observation of π/π* and σ/σ* features in the photoemission/inverse photoemission 1, and this data also indicates a band gap of 0.5-1 eV, consistent with the first layer transport measurements. Thus, the second layer of C(111) on MgO should possess graphene-like properties but the first layer will not. Secondly, graphene on other (111) rocksalt oxide surfaces may also undergo similar interactions. However, graphene grown on (111) oxides which do not reconstruct and have a larger O—O nearest neighbor distance than 2.5 Å (e.g., Co304(111) 6 should be incommensurate, as observed for graphene grown by MBE on Co3O4(111) 4 
     Methods for the manufacture of FETs prepared by the deposition of thin films of graphene on rocksalt oxides that are compatible with CMOS integration are set forth. The resulting FETs are described by characteristics and applications. Importantly, the band gap phenomena observe are at values consistent with other materials designed to serve in logic devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate exemplary embodiments of the invention, and, together with the general description given above and the detailed description given below, serve to explain the features of the invention. 
         FIG. 1  reflects C(1s) and LEED spectra for formation of an ordered carbon monolayer on MgO (111). (a) XPS C(1s) spectrum of a multiplayer adventitious carbon film observed immediately after the insertion of the MgO crystal into UHV at room temperature (no LEED pattern is observed); (b) XPS C(1s) spectrum after annealing at 700 K in UHV in the presence of O 2 ; the XPS-derived average carbon layer thickness is 1 ML; (c) the corresponding LEED pattern exhibits C symmetry; (d) XPS after anneal of the film in (b) to 1000K in the presence of C 2 H 4  (5×10 −7  Torr, 25 min); the XPS derived C thickness remains 1 ML; (e) corresponding complex LEED pattern; (f) close-up of the pattern in (e) with integrated, background-subtracted intensities (arbitrary units) for ‘A’ and ‘B’ spots (circled). The A spots have an average intensity of 18.7±3, while the B spots have an average intensity of 12.9±1. The uncertainties are the standard deviations. Other spots in the image are weaker and are attributed to multiple diffraction. The LEED patterns were acquired at 80 eV beam energy. The XPS spectra binding energies are referenced to a MgO lattice oxygen O(1s) binding energy of 530.0 e 11 . 
         FIG. 2  is a schematic of a band gap formation due to (left) commensurate graphene/substrate interface lifting A site/B site chemical equivalence and therefore the HOMO/LUMO degeneracy at the Dirac point, consistent with C3V LEED symmetry. (Right) An incommensurate graphene interface results in graphene A and B sites sampling an ensemble of substrate interactions, and therefore retaining chemical equivalence, C6V LEED symmetry and therefore no band gap at the Dirac point. 
         FIG. 3  is a schematic of a graphene-FET structure on Si(100). 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The graphene based FETs of the invention are described herein below both in terms of the method of formation of the FETs and their resulting characteristics. Examples recited herein are not intended to be limiting unless those examples are reflected in the claims set forth below. 
     Construction of a Graphene/Rocksalt Oxide (111) FET—a Charge-Based Device—on Si(100) or Si(111) 
     Deposit a MgO(111) Film on Si(100) or on Si(111). 
     Formation of (100) textured MgO(111) on Si(100) by PLD has been reported 7  and by CVD 8 . The formation of (111) oxides on Si(111) may be easier, but the formation of (111) vs. (110) or (100) texture on Si(100) appears to be highly temperature-dependent. Other rocksalt (111) oxides of interest in this application, e.g., NiO(111) can be grown readily on Ni(111). Methods in the art report that NiO (111) can be grown directly on Si(100) and offer a different alternative for proceeding. In addition to magnesium and nickel oxides, other rock salt (110 films may be formed. 
     Graphene Growth on the MgO(111) or Other Oxide(111) Surface. 
     Previous studies indicate that CVD using thermally-cracked ethylene at ˜600 K, followed by annealing in UHV to 1000 K, yields a 2-3 ML graphene surface 1 . In contrast, PVD at room temperature, followed by annealing in UHV at 1000 K yields a 1-2 ML graphene surface (first layer not really graphene, see above) 2,3 . Experience with other oxides (e.g., Co3O4(111)) suggests that MBE from a solid carbon source at 1000 K in UHV may yield controllable layer-by-layer growth. Current information suggests that the MBE method may be the preferred route for controlled growth. This is set forth, for example, in U.S. Provisional Patent Application Ser. No. 61/522,600, the entirety of which is incorporated herein by reference. 
     Deposition of Gate Oxide. 
     The gate oxide should form a non-chemically bonded (i.e., no metal carbide formation) interface with the graphene in order to maintain the graphene π network intact. Reports in the literature 9  suggest that ALD of alumina on graphene will give good results, but other possibilities including MgO 10  or HfO2 11  may also work. Highly energetic oxide deposition processes (e.g. PVD, PECVD) may disrupt the graphene π network. However, CVD and ALD are preferred. 
     Deposition of Source, Drain and Gate Contacts. 
     Metallization procedures will involve metal evaporation (e beam deposition, or possible PVD) to make source, drain and metal contacts. Good results 11  on physically transferred graphene sheets have been obtained using Cr/Au contacts. Recent experience suggests that Au may do as well (private communication). A schematic of the final structure is displayed in  FIG. 3  wherein the substrate of Si is reference character  1000 , the rocksalt oxide layer (e.g. NiO or MgO) is  1002 , the graphene film is  1004 , the top gate is indicated by  1006  and source and drain are  1008  and  1010 , with gate contact  1012  provided on the top gate. 
     The advantages of a device as in  FIG. 3  relative to existing advanced Si CMOS include faster frequencies and lower operating power due to the superior mobility of graphene relative to Si. The presence of a band gap gives important advantages relative to devices made of graphene/SiC 12 . These devices may exhibit impressive operating frequencies, but undoubtedly have poor on/off ratios to small or non-existent band gaps for the graphene/SiC system. 
     In the device set forth in  FIG. 3  the oxide can be MgO(111) or another (111)-oriented rocksalt structure oxide. The gate oxide could be alumina or hafnia, and the contacts could be Au or Cr/Au. In addition to Si(100) (as shown), Si(111) may be used. 
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     While the present invention has been disclosed with references to certain embodiments, numerous modification, alterations, and changes to the described embodiments are possible without departing from the sphere and scope of the present invention, as defined in the recited embodiments. Accordingly, it is intended that the present invention not be limited to the described embodiments, but that it has the full scope defined by the language of the description and equivalents thereof.