Abstract:
An electrical circuit is disclosed that is capable of improving the power supply rejection ratio of a standard bandgap reference while maintaining the temperature coefficient of the standard design. One embodiment of the circuit comprises a bandgap reference voltage generator, an operational amplifier, a transistor, a voltage divider, a startup network, and a self-biasing network that provide a voltage reference with improved characteristics.

Description:
FIELD OF THE INVENTION 
   The present invention relates to electronics in general, and, more particularly, to a circuit for providing a bandgap voltage reference. 
   BACKGROUND OF THE INVENTION 
   Applications for portable, battery-operated equipment or systems employing complex, high-performance electronic circuitry have increased with the widespread use of cellular telephones, laptop computers, and other systems. Maintaining the accuracy of many of these circuits is directly dependent on the stability of a reference voltage. A bandgap reference generator produces such a reference voltage. The reference voltage produced is approximately equal to the band gap voltage of silicon, which is approximately 1.2 volts. It is desirable that such a bandgap reference voltage be substantially immune to temperature variations, power supply variations, and noise. 
     FIG. 1  depicts a schematic diagram of a bandgap reference architecture in the prior art. Power supply  101  feeds an unregulated (i.e., fluctuating) signal to biasing network  103  and bandgap reference  105 . Biasing network  103  provides a biasing signal via lead  115  to bandgap reference  105 . Power supply  101 , biasing network  103 , and bandgap reference  105  are tied together via common lead  113 , which is grounded. Bandgap reference  105  provides a reference signal, V out , via lead  117 . 
     FIG. 2  depicts a schematic diagram of the same bandgap reference in the prior art as is depicted in  FIG. 1 , but at the circuit (i.e., lower) level of abstraction. M 90  through M 93  comprise a biasing network, the output of which, labeled  115 , is fed to the gate of transistor M 9 . M 9  acts as a current source for an error, or operational, amplifier comprising M 9  through M 13 . The error amplifier senses the voltage levels at the gates of M 10  and M 11  and controls the currents through M 5  and M 6 . The voltages at the gates of M 10  and M 11  are approximately equal due to the negative feedback of R 1 , R 3 , M 5 , and M 6 . Q 1  through Q 4  provide about twice the bandgap voltage of silicon, or 2.4 Volts. The bandgap transistors Q 1  through Q 4  also have canceling positive and negative temperature coefficients, so that the reference voltage output at  117 , also the output of the error amplifier, is constant with temperature. Having two transistors cascaded as in Q 1 /Q 2  or Q 3 /Q 4  pairs reduces the offset voltage of the error amplifier, improving the accuracy of the output voltage. If R 1 =R 3 , the output voltage of the overall bandgap reference of the prior art can be expressed as:
   V   out   =V   be(Q1)   +V   be(Q2) +2 *V   t   *In ( n )*( R 2+ R 3)/ R 3  (Eq. 1) 
Where V t  is the threshold voltage of bipolar transistors (Q 1  through Q 4 ) and n is the emitter area ratio of Q 1  and Q 3 . The emitter ratio of Q 1 /Q 3  is equal to the emitter ratio of Q 2 /Q 4  because Q 1 =Q 2  and Q 3 =Q 4 .
 
   Although this circuit is well known and widely used, it is disadvantageous in that it suffers from, among other things, a poor power supply rejection ratio (PSRR). 
   SUMMARY OF THE INVENTION 
   The present invention provides a mechanism for improving the characteristics of a reference circuit, while avoiding many of the costs and restrictions associated with prior techniques. Specifically, embodiments of the present invention adds a self-biasing network to enable an improved power supply rejection ratio while maintaining temperature coefficient characteristics. The sub-circuits comprising the illustrative embodiment are a bandgap reference voltage generator, an operational amplifier, a transistor, a voltage divider, a startup network, and a self-biasing network. 
   An illustrative embodiment of the present invention comprises: a first transistor having a gate, a source, and a drain; a second transistor having a gate, a source, and a drain, wherein the gate of the second transistor is electrically connected to the gate of the first transistor, and wherein the source of the first transistor is electrically connected to the source of the second transistor; a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is electrically connected to the drain of the first transistor; a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is electrically connected to the drain of the first transistor; a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is electrically connected to the drain of the second transistor; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is electrically connected to the drain of the second transistor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  depicts a schematic diagram of a bandgap reference architecture in the prior art. 
       FIG. 2  depicts a schematic diagram of a bandgap reference circuit in the prior art. 
       FIG. 3  depicts a schematic diagram of a bandgap reference architecture in accordance with the illustrative embodiment of the present invention. 
       FIG. 4  depicts a schematic diagram of a bandgap reference circuit in accordance with the illustrative embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 3  depicts a schematic diagram of a bandgap reference architecture in accordance with the illustrative embodiment of the present invention. Power supply  301  feeds an unregulated signal in well-known fashion to bandgap reference  303 , operational amplifier  305 , transistor M 35 , and startup network  315  via lead  321 . 
   Startup network  315  ensures an initial biasing voltage to pull the error amplifiers constituting bandgap reference  303  in working state. Startup network  315  does so by outputting a signal on lead  326  used by self-biasing network  311 . Self-biasing network  311  takes the signal on lead  326  and outputs a biasing signal on lead  322  that is used by bandgap reference  303  and operational amplifier  305 . 
   Bandgap reference  303  is a voltage generator. Bandgap reference  303  provides a reference signal via lead  324  to operational amplifier  305  by using input signals on leads  321  and  322 . Operational amplifier  305  inputs the raw reference signal on lead  324 , together with the signals on leads  321 ,  322 , and  326 , and outputs an amplified reference signal on lead  325 . 
   Transistor M 35  comprises a gate, a source, and a drain, and is a p-type metal oxide semiconductor (PMOS) device. The signal on lead  321  is fed into the source. The signal on lead  325  is fed into the gate. The drain of transistor M 35  ties into lead  326 . 
   Voltage divider  309  takes the signal on lead  326  and outputs the proper voltage reference signal on lead  328 . 
   Power supply  301 , bandgap reference  303 , operational amplifier  305 , voltage divider  309 , and self-biasing network  311  are tied together via common lead  323 , which is also tied to ground. 
     FIG. 4  depicts a schematic diagram of the same bandgap reference, but at the circuit level, in accordance with the illustrative embodiment of the present invention. Power supply  301  comprises voltage source V 1  with positive voltage applied to lead  321 . Startup network  315  comprises transistors M 60  and M 61 , interconnected as shown. The signal on lead  321  is fed into the source of transistor M 61 . The drain of transistor M 60  ties into lead  326 . 
   Self-biasing network  311  comprises transistors M 50  through M 52  and capacitor C 5 , interconnected as shown. In self-biasing network  311 , the voltage present on lead  328  is divided by three and provided via lead  322  to the tail transistors M 9  and M 30  of the error amplifiers within bandgap reference  303  and operational amplifier  305 , respectively. By providing the reduced voltage, the dependence of the error amplifiers&#39; biasing voltages on power supply  301  is reduced, consequently improving the power supply rejection ratio. At the same time, the temperature coefficient of the design is maintained. The source of transistor M 52  is connected to lead  326 . The gate of transistor M 52  is connected to the drain of transistor M 52 . The source of transistor M 51  is connected to the drain of transistor M 52 . The gate of transistor M 51  is connected to the drain of transistor M 51 . The source of transistor M 50  is connected to the drain of transistor M 51 . The gate of transistor M 50  is connected to the drain of transistor M 50 . The drain of transistor M 50  is connected to lead  323 . Transistors M 50  through M 52  are PMOS devices. Capacitor C 5  lies between leads  322  and  323 . 
   Bandgap reference  303  comprises: transistors Q 1  through Q 4 , transistors M 9  through M 13 , transistors M 5  and M 6 , resistors R 1  through R 3 , and capacitors C 1  and C 2 , interconnected as shown. Transistors M 9  through M 13  constitute the error amplifier within bandgap reference  303 . The drain of transistor M 9  is tied to lead  323 . The sources of transistors M 5 , M 6 , M 12 , and M 13  are tied to lead  321 . The gates of transistors M 5  and M 6  are tied to each other. The drain of transistor M 5  is tied to resistor R 1  and capacitor C 1 . The drain of transistor M 6  is tied to resistor R 3  and capacitor C 2  at lead  324 . Capacitor C 2  lies between leads  323  and  324 . 
   In accordance with the illustrative embodiment, the value of resistor R 1  equals the value of resistor R 2 , and the value of capacitor C 1  equals the value of capacitor C 2 . 
   Operational amplifier  305  comprises transistors M 30  through M 34  operating as an error amplifier and capacitor C 3 , interconnected as shown. The bias signal on lead  322  is fed into transistor M 30 . The drain of transistor M 30  is tied to lead  323 . The signal on lead  321  is fed into the sources of transistors M 33  and M 34 . The signal on lead  324  as provided by bandgap reference  303  is fed into the gate of transistor M 32 . The drain of transistor M 34  is tied to lead  325 . Capacitor C 3  lies between lead  323  and  326 . 
   Voltage divider  309  comprises transistors M 40  through M 43  and capacitor C 4 , interconnected as shown. Voltage divider  309  provides reference signal V out  on lead  328  at a voltage level that is three-fourths of the voltage level present on lead  326 . 
   Capacitors C 1  through C 5  further assist in damping the effect of power supply variation the signal on lead  324 . 
   The output voltage of the illustrative embodiment, V out , is equal to: 
                   V   out     =       3   ⁡     [         V   be     ⁡     (     Q   1     )       +       V   be     ⁡     (   Q2   )       +     2   ⁢     V   t     ⁢     ln   ⁡     (   n   )       ⁢     (         R   2     +     R   3         R   3       )         ]       4             (     Eq   .           ⁢   2     )               
wherein V be (Q 1 ) is the base-emitter voltage in transistor Q l , V be (Q 2 ) is the base-emitter voltage in transistor Q 2 , V t  is the threshold voltage of Where V t  is the threshold voltage of bipolar transistors (Q 1  through Q 4 ) and n is the emitter area ratio of Q 1  and Q 3 . The emitter ratio of Q 1 /Q 3  is equal to the emitter ratio of Q 2 /Q 4  because Q 1 =Q 2  and Q 3 =Q 4 .
 
   It is to be understood that the above-described embodiments are merely illustrative of the present invention and that many variations of the above-described embodiments can be devised by those skilled in the art without departing from the scope of the invention. It is therefore intended that such variations be included within the scope of the following claims and their equivalents.