Abstract:
A loop bandwidth control apparatus applied to a phase locked loop (PLL) includes a first loop filter module, a second loop filter module, a control module, a first switching module, and a second switching module. The first filter module and the second loop filter module output a first voltage and a second voltage, respectively. The second loop filter module has a bandwidth different from that of the first loop filter module. According to one of the first voltage and the second voltage, the control module generates a bandwidth control signal. According to the bandwidth control signal, the first switching module forms a path between a charge pump and one of the first loop filter module and the second loop filter module, and the second switching module forms a path between a voltage-controlled oscillator (VCO) and one of the first loop filter module and the second loop filter module.

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATIONS 
       [0001]    This patent application claims priority from Taiwan Patent Application No. 098133340, filed in the Taiwan Patent Office on Oct. 1, 2009, entitled “Bandwidth Control Apparatus for Phase Lock Loop and Method Thereof”, and incorporates the Taiwan patent application in its entirety by reference. 
       TECHNICAL FIELD 
       [0002]    The present disclosure relates to a phase locked loop (PLL), and more particularly, to a loop bandwidth control apparatus applied to a PLL and a method thereof. 
       BACKGROUND OF THE PRESENT DISCLOSURE 
       [0003]    A PLL can be regarded as a feedback circuit system that compares to an inputted phase with a feedback phase to adjust a outputted phase, i.e., the PLL used in a transmitter is inputted with a low-frequency (LF) periodic signal to output a high-frequency (HF) periodic signal, with a certain constant phase relationship between the inputted signal and the outputted signal. The PLL mainly comprises a phase frequency detector (PFD), a charge pump, a loop filter and a voltage controlled oscillator (VCO). In practice, the PLL is widely applied to electronic and communication products, e.g., memories, microprocessors, hard disk driving apparatuses, radio frequency (RF) transceivers, and fiber optic transceivers. 
         [0004]      FIG. 1  shows a block diagram of a conventional PLL. A PLL  1  comprises a phase frequency detector (PFD)  10 , a charge pump  12 , a loop filter  14 , a voltage controlled oscillator (VCO)  16  and a frequency divider  18 . The charge pump  12  is coupled between the PFD  10  and the loop filter  14 , the loop filter  14  is coupled to the VCO  16 , and the frequency divider  18  is coupled between the PFD  10  and the VCO  16 . 
         [0005]    Upon receiving a reference clock CKR and a feedback clock CKV, the PFD  10  compares the reference clock CKR with the feedback clock CKV to generate a phase difference ΔΦ that is transmitted to the charge pump  12 . The feedback clock CKV is generated by the frequency divider  18  from frequency dividing an output frequency f out  of the VCO  16  with a predetermined divisor. According to the phase difference ΔΦ, the charge pump  12  generates a corresponding charge pump current I that is outputted to the loop filter  14 . Upon receiving the charge pump current I, the loop filter  14  converts the charge pump current I into a control voltage V via its impedance, and outputs the control voltage V to the VCO  16 . After that, the VCO  16  generates a corresponding output frequency f out  according to the control voltage V. 
         [0006]    The loop filter  14  is one of most critical components of the PLL  1 . Considering cost and efficiency, the PLL  1  is commonly realized by a second-order low-pass filter composed of resistors and capacitors. Generally speaking, the PLL  14  has several important parameters, e.g., phase margin, loop bandwidth, and loop filter topology, and the loop bandwidth needed for eliminating noises and determining a locking time is the most critical parameter. 
         [0007]    When the loop frequency of the loop filter  14  is small, although the loop filterer  14  can effectively eliminate noises created by inputting the reference frequency and switching the charge pump  12  as well as reducing undesirable effects caused by jitter, a disadvantage that the loop filter  14  requires a long locking time is incurred since the locking time is directly proportional to the loop bandwidth. On the contrary, when the loop bandwidth of the loop filter  14  is enlarged, the locking time is reduced; nevertheless, the PLL  14  can not restrain the foregoing noises. 
         [0008]    Therefore, one object of the present disclosure is to provide a loop bandwidth control apparatus applied to a PLL and a method thereof to solve the foregoing problem. 
       SUMMARY OF THE PRESENT DISCLOSURE 
       [0009]    According to an embodiment of the present disclosure, a loop bandwidth control apparatus is applied to a phase locked loop (PLL) that comprises a phase frequency detector (PFD), a charge pump, and a voltage controlled oscillator (VCO). The loop bandwidth control apparatus comprises a first loop filter module, a second loop filter module, a control module, a first switching module, and a second switching module. The first loop filter module and the second loop filter module respectively output a first voltage and a second voltage, and a bandwidth of the second loop filter module is different from that of the first loop filter module. The control module generates a bandwidth control signal according to the first voltage or the second voltage. According to the bandwidth control signal, the first switching module forms a path between the charge pump and one of the first loop filter module and the second loop filter module, and the second switching module forms a path between the VCO and one of the first loop filter module and the second loop filter module. 
         [0010]    According to another embodiment of the present disclosure, a loop bandwidth control method is applied to a PLL that comprises a loop bandwidth control apparatus, a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator (VCO). The loop bandwidth control apparatus comprises a first loop filter module and a second loop filter module, and a bandwidth of the second loop filter module is different from that of the first loop filter module. The loop bandwidth control method comprises generating a bandwidth control signal according to a first voltage outputted by the first loop filter module or a second voltage outputted by the second loop filter module; and forming a path between the charge pump and a VCO via the first loop filter module or the second loop filter according to the bandwidth control signal. 
         [0011]    According to yet another embodiment of the present disclosure, a phase locked loop (PLL) comprises a phase frequency detector (PFD), a charge pump, a voltage controlled oscillator (VCO), a frequency divider, and a loop bandwidth control apparatus. The loop bandwidth control apparatus comprises a first loop filter module, a second loop filter module, a control module, a first switching module, and a second switching module. The PFD generates a phase difference according to a reference clock and a feedback clock. The charge pump generates an output current according to the phase difference. The VCO generates an output frequency according to a control voltage. The frequency divider generates the feedback clock according to the output frequency. The first loop filter module and the second loop filter module respectively generate a first voltage and a second voltage according to the output current. A bandwidth of the second loop filter module is larger than that of the first loop filter module. The control module monitors the first voltage and the second voltage to generate a bandwidth control signal according to the first voltage and the second voltage. According to the bandwidth control signal, the first switching module forms a path between the charge pump and the first loop filter module or the second loop filter module, and the second switching module forms a path between the VCO and the first loop filter module or the second loop filter module. 
         [0012]    In conclusion, according to a loop bandwidth control apparatus and a method thereof provided by the present disclosure, by switching between loop filter modules of different bandwidths, a PLL under a VCO calibration mode is given a large loop bandwidth, such that a time for calibrating a control voltage of the VCO is significantly reduced to solve the foregoing problem. In addition, when the PLL operates under a normal operation mode, the loop bandwidth of the PLL recovers to normal instead of being too large, so that noise eliminating capabilities of the PLL are preserved. 
         [0013]    The advantages and spirit related to the present disclosure can be further understood via the following detailed description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a block diagram of a conventional PLL. 
           [0015]      FIG. 2  is a block diagram of a PLL in accordance with a first embodiment of the present disclosure. 
           [0016]      FIG. 3  is a schematic diagram of the PLL in  FIG. 2  in accordance with an embodiment of the present disclosure. 
           [0017]      FIG. 4  is a schematic diagram of a second loop filter module in  FIG. 3  in accordance with an embodiment of the present disclosure. 
           [0018]      FIG. 5  is a schematic diagram of detailed operations of a PFD and a charge pump in  FIG. 3 . 
           [0019]      FIG. 6  is a schematic diagram of different locking times from paths formed between a VCO and loop filter modules of different bandwidths. 
           [0020]      FIG. 7  is a flow chart of a loop bandwidth control method in accordance with a second embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0021]    According to an embodiment of the present disclosure, a PLL is provided.  FIG. 2  shows a block diagram of a PLL  2 . The PLL  2  mainly comprises a PFD  20 , a charge pump  22 , a loop bandwidth control apparatus  24 , a VCO  26 , and a frequency divider  28 . The loop bandwidth control apparatus  24  comprises a first loop filter module  240 , a second loop filter module  242 , a buffer module  244 , a first switching module  245 , a second switching module  246 , and a control module  248 . 
         [0022]    The PFD  20  is coupled to the charge pump  22 . The first switching module  245  is coupled to input ends of the first loop filter module  240  and the second loop filter module  242 , and the charge pump  22 . The buffer module  244  is coupled to output ends of the first loop filter module  240  and the second loop filter module  242 . The control module  248  is coupled to the charge pump  22 , the first switching module  245 , the second switching module  246 , the buffer module  244  and the VCO  26 . The second switching module  246  is coupled to the output ends of the first loop filter module  240  and the second loop filter module  242 , and the VCO  26 . The frequency divider  28  is coupled to the PFD  20  and the VCO  26 . 
         [0023]    In this embodiment, upon receiving a reference clock CKR and a feedback clock CKV, the phase bandwidth detector  20  compares the reference clock CKR with the feedback CKV to generate a phase difference Φ that is transmitted to the charge pump  22 . The feedback clock CKV is obtained by the frequency divider  28  from dividing an output frequency f out  outputted by the VCO  26  with a predetermined divisor. After that, the charge pump  12  generates a corresponding charge pump current I p  according to the received phase difference Φ, and outputs the charge pump current I p  to the first loop filter module  240  or the second loop filter module  242  via the first switching module  245 . The first loop filter module  240  or the second loop filter module  242  generates a first voltage V 1  or a second voltage V 2  according to the charge pump current I p . The control module  248  monitors the first voltage V 1  or the second voltage V 2 , and generates a bandwidth control signal according to either the first voltage V 1  or the second voltage V 2 . More specifically, the control module  248  compares a reference voltage with the first voltage V 1  or the second voltage V 2 , and determines whether an absolute value of a difference between the reference voltage and the first voltage V 1  or the second voltage V 2  is smaller than a predetermined value. When a determination result of the control module  248  is negative, it means that calibration of the output frequency f out  of the VCO  26  is not yet completed, such that the control module generates a VCO control signal S VCO  for adjusting a VCO curve of the VCO  26 . When the determination result of the control module  248  is positive, it means that calibration of the output frequency f out  is completed, such that the control module  248  generates a bandwidth control signal S BC  for switching loop modules and adjusting the charge pump current I p . In practice, the reference voltage is related to the VCO curve of the VCO  26 . For example, the reference voltage is, but not limited to, a V c1  between V c1 (max) and V c1 (min) in  FIG. 6 . 
         [0024]    It is to be noted that, in the loop bandwidth control apparatus  24 , a bandwidth of the second loop filter module  242  is larger than that of the first loop filter module  240 . In order to eliminating a charge sharing effect between the first loop filter module  240  and the second loop filter module  242 , the buffer module  244  drives the first loop filter module  240  having the smaller bandwidth, so that the first voltage V 1  outputted by the first loop filter module  240  approximately equalizes the second voltage V 2  outputted by the second loop filter module  242  having the larger bandwidth. 
         [0025]    In practical applications, the control module  248  is not limited to simultaneously switching the first switching module  245  and the second switching module  246  to the first loop filter module  240  or the second loop filter module  242  from monitoring the first voltage V 1  or the second voltage V 2 . The control module  248  also could receive a setting signal S c  to simultaneously switch the first switching module  245  and the second switching module  246  to the first loop filter module  240  or the second loop filter module  242 , so as to correspond to different applications of the PLL  2 . 
         [0026]    For example, when the PLL  2  is applied to a transmitting end Tx, the control module  248  simultaneously switches the first switching module  245  and the second switching module  246  to the first loop filter module  240 ; when the PLL  2  is applied to a receiving end Rx, the control module  248  simultaneously switches the first switching module  245  and the second switching module  246  to the first loop filter module  242 . In another embodiment, when the PLL  2  is applied to a Bluetooth wireless transmission apparatus, the control module  248  simultaneously switches the first switching module  245  and the second switching module  246  to the first loop filter module  240 ; when the PLL  2  is applied to a WiFi wireless transmission apparatus, the control module  248  simultaneously switches the first switching module  245  and the second switching module  246  to the first loop filter module  242 . However, the present disclosure is not limited to the foregoing embodiments. 
         [0027]      FIG. 3  shows a schematic diagram of the PLL  2  in  FIG. 2  in accordance with an embodiment of the present disclosure. In this embodiment, the buffer module  244  applies a negative feedback operational amplifier (OA) circuit, which has an output end connected to its negative input end. A first voltage V 1  outputted by the first loop filter module  240  is coupled to the output end of the OA, and a second voltage V 2  outputted by the second loop filter module  242  is coupled to a positive end of the OA, so as to maintain the first voltage V 1  to be equal to the second voltage V 2 . The control module  248  determines whether an absolute value of a difference between the reference voltage and the first voltage V 1  or the second voltage V 2  is smaller than a predetermined value to generate a determination result, and generates a bandwidth control signal S BC  and a VCO control signal S VCO  according to the determination result. 
         [0028]    The control module  248  controls the charge pump  22  to adjust an output current according to the bandwidth control signal S BC , and simultaneously switches the first switching module  245  and the second switching module  246  to the first loop filter module  240  or the second loop filter module  242  according to the bandwidth control signal S BC , such that a path between the charge pump  22  and the VCO  26  is formed via the first loop filter module  240  or the second loop filter module  242 . In addition, the control module  248  adjusts a VCO curve of the VCO  26  according to the VCO control signal S VCO . 
         [0029]    When the path between the charge pump  22  and the VCO  26  is formed via the first loop filter module  240 , a control voltage V c  received by the VCO  26  is the first voltage V 1  outputted by the first loop filter module  240 . When the path between the charge pump  22  and the VCO  26  is formed via the second loop filter module  242 , the control voltage V c  received by the VCO  26  is the second voltage V 2  outputted by the second loop filter module  242 . 
         [0030]    Through the foregoing switching approach, when the PLL  2  operates under a VCO calibration mode, the path between the charge pump  22  and the VCO  26  is formed via the second loop filter module  242  having the larger bandwidth to enlarge the loop bandwidth of the PLL  2 , so as to reduce a locking time needed by the PLL  2  for calibrating the VCO curve of the VCO  26 . Since the control voltage V c  approximates the reference voltage when calibration of the VCO curve of the VCO  26  is completed, it is determined whether the VCO completes the calibration according to the control voltage V c . In practice, the reference voltage is a predetermined value or is user-defined according to actual requirements. 
         [0031]    At this point, since the second loop filter module  242  with the larger bandwidth may decrease its noise eliminating capabilities, i.e., the PLL  2  operated under the normal operation mode only needs a normal loop bandwidth. Accordingly, the first switching module  245  and the second switching module  246  simultaneously switch to the first loop filter module  240  having the smaller bandwidth so as to form the path between the charge pump  22  and the VCO  26  via the first loop filter module  240 , such that the PLL is given higher noise eliminating capabilities under the normal operation mode. 
         [0032]    In addition, referring to  FIG. 3 , the charge pump  22  is also coupled to the control module  248 , and adjusts an output charge pump current I p  according to the bandwidth control signal S BC  outputted by the control module  248 . 
         [0033]    In practical applications, the first loop filter module  240  and the second loop filter module  242  may be second-order low-pass filter circuits comprising variable resistors and variable capacitors.  FIG. 4  shows a schematic diagram of the second loop filter module  242  in accordance with an embodiment of the present disclosure. The second loop filter module  242  comprises, but not limited to, a variable resistor R and variable capacitors C 1  and C 2 . The variable resistor R connected in series to the variable capacitor C 1  is connected in parallel to the variable capacitor C 2  to form a second-order low-pass filter circuit. The first loop filter module  240  may be adjusted to different structures according to actual requirements, and details thereof shall not be described for brevity. 
         [0034]      FIG. 5  shows a schematic diagram of detailed operations of the PFD  20  and the charge pump  22  in  FIG. 3 . In the PLL  2 , a main function of the charge pump  22  is to pump in or pump out charges in the subsequent first loop filter module  240  or the second loop filter module  242 . The PFD  20  opens or closes charge switches S 1  and S 2  via its two output signals Q A  and Q B . When the output signal Q A  represents “ON” and the output signal Q B  represents “OFF”, the charge pump  22  pumps charges into the first loop filter module  240  or the second loop filter module  242  to increase a control voltage V c  of the VCO  26 ; when the output signal Q A  represents “OFF” and the output signal Q B  represents “ON”, the charge pump  22  pumps out charges from the first loop filter module  240  or the second loop filter module  242  to reduce the control voltage V c  of the VCO  26 . Supposing that I 1 =I 2 =I, and the charge switches are simultaneously opened, the amount of the pumped-in charges equalizes that of pumped-out charges of the charge pump  22 , such that no charges are stored in the first loop filter module  240  or the second loop filter module  242  to effectively reduce the undesirable effects of the first loop filter module  240  or the second loop filter module  242 . 
         [0035]      FIG. 6  shows a schematic diagram of different locking times t s1  and t s2  from two paths formed between the VCO  26  and the first loop filter module  240  and the second loop filter module  242  of different bandwidths f 1  and f 2 . When the PLL  2  operates under a normal operation mode and the path between charge pump  22  and the VCO  26  is formed via the first loop filter module  240  having the smaller bandwidth f 1 , the PLL  2  has a normal loop bandwidth, and a locking time for calibrating a control voltage V c  of the VCO  26  is t s1 , i.e., it takes the locking time t s1  for a control voltage V c  of the VCO  26  approximating a reference voltage V c1 . When the PLL  2  operates under the VCO calibration mode and the path between charge pump  22  and the VCO  26  is formed via the first loop filter module  242  having the larger bandwidth f 2 , the PLL  2  has a relatively large loop bandwidth, and thus the locking time t s2  for calibrating the control voltage V c1  of the VCO  26  is shorter than the locking time t s1 . 
         [0036]    According to a second embodiment of the present disclosure, a method for loop bandwidth control is applied to a PLL that comprises a loop bandwidth control apparatus, a PFD, a charge pump and a VCO. The loop bandwidth control apparatus comprises a first loop filter module and a second loop filter module, and a bandwidth of the second loop filter module is greater than that of the first loop filter module.  FIG. 7  shows a flow chart of the method for loop bandwidth control. 
         [0037]    When the PLL operates under a VCO curve calibration mode, a path between the VCO and the charge pump is formed via the second loop filter module. The method begins with Step S 10  in which a reference voltage is compared with a second voltage outputted by the second loop filter module. In Step S 12 , it is determined whether an absolute value of a difference between the reference voltage and the second voltage is smaller than a predetermined value. For example, the predetermined value is a predetermined value of an overall system or is user-defined according to actual requirements. When a determination result from Step S 12  is negative, it means that calibration of an output frequency of the VCO is not yet completed, and the method proceeds to Step S 15  in which a VCO control signal S VCO  is generated. In Step S 20 , the VCO  26  adjusts a VCO curve according to the VCO control signal S VCO . The foregoing operations are iterated until the determination result of Step  12  is positive, which means that calibration of the output frequency of the VCO is completed, and the method proceeds to Step S 14  in which a bandwidth control signal S BC  is generated to switch the PLL to a normal operation mode. In Step S 16 , a loop module is switched from the second loop filter module having a larger bandwidth to the first loop filter module having a smaller bandwidth according to the bandwidth control signal, such that the path between the charge pump and the VCO is formed via the first loop filter module. More specifically, under the VCO calibration mode, the path between the charge pump and the VCO is formed via the second loop filter module having the larger bandwidth to enlarge the loop bandwidth of the PLL, thus reducing a time needed for calibrating the VCO. When the control voltage of the VCO approximates a reference voltage, it means that the calibration of the VCO is completed, and accordingly the loop module is switched to form the path between the charge pump and the VCO via the first loop filter module having the smaller bandwidth. At this point, the PLL under the normal operation mode has a normal loop bandwidth. 
         [0038]    In addition, in Step S 18 , an output current of the charge pump is adjusted according to the bandwidth control signal. Detailed operations of the loop bandwidth control method can be easily appreciated with reference to associated descriptions and diagrams of the first embodiment, and shall not be described for brevity. 
         [0039]    Compared to the prior art, according to a loop bandwidth control apparatus and a method thereof, by switching between loop filter modules of different bandwidths, a PLL under a VCO calibration mode has a large loop bandwidth to significantly reduce a time for calibrating a VCO, thus overcome disadvantages of the prior art. In addition, when the PLL operates under a normal operation mode, the loop bandwidth of the PLL recovers to normal without compromising noise eliminating capabilities of the loop filter modules due to a rather-large loop bandwidth. 
         [0040]    While the present disclosure has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the present disclosure needs not to be limited to the above embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.