Abstract:
A method of forming a device feature using an extreme ultraviolet (EUV) imaging layer (or a sub-deep ultraviolet imaging layer) and one or more other masks layers. The method includes forming a device feature layer; forming a photoresist layer over the device feature layer; forming a contact mask layer (CML) over the photoresist layer; forming an extreme ultraviolet (EUV) imaging layer over the CML; forming a first opening through the EUV imaging layer to expose a first underlying region of the CML; forming a second opening through the CML to expose a second underlying region of the photoresist layer, wherein the second opening is situated directly below the first opening; forming a third opening through the photoresist layer to expose a third underlying region of the device feature layer, wherein the third opening is situated directly below the second opening; forming a fourth opening through the device feature material layer, wherein the fourth opening is situated directly below the third opening.

Description:
FIELD  
         [0001]    This disclosure relates generally to semiconductor processing, and in particular, to a method of transferring a pattern formed on an extreme ultraviolet (EUV) imaging layer by way of a flood exposure of a contact mask layer (CML).  
         BACKGROUND  
         [0002]    The semiconductor industry continually reduces the size of the smallest transistor features in order to increase transistor density and to improve transistor performance. This requirement has driven a concomitant reduction in the wavelength of light used in photolithographic techniques to define these features in photoresist. Extreme Ultraviolet lithography (EUVL) is one such advanced technique, using a wavelength of approximately 11-15 nanometers (nm).  
           [0003]    Because of the relatively short wavelength, EUV photoresist can be exposed to define relatively small features. This can be done using an EUV exposure tool comprised of an EUV source, a number of reflective EUV optics (or mirrors), and a stage for holding a (resist-coated) silicon wafer. However, one drawback of EUV lithography is that due to the relatively poor reflectivity of EUV mirrors (approximately 67%), relatively little light reaches the wafer surface. This requires relatively long exposure times, limiting the throughput of an EUVL tool.  
           [0004]    Since organic photoresist materials are, in general, highly absorptive to EUV, the exposure dose will be a function of the photoresist thickness. The use of an ultra thin photoresist imaging layer will decrease the required patterning dose.  
           [0005]    Another advantage of thin photoresist films is that the side wall angle, which is a function of the resist absorbance, can be improved by the use of ultra thin photoresist imaging layer.  
           [0006]    In addition, photoresist collapse is becoming a significant problem as the dimensions of the targets dimensions continue to shrink, because the capillary forces that cause collapse are inversely proportional to the spacing between photoresist structures. The use of ultra thin film imaging will reduce the problem of photoresist collapse.  
           [0007]    However, an ultra thin layer of photoresist may not act as an effective mask to enable the patterned etching of the substrate. But this may be solved by transferring the lithographic pattern to a thicker underlying photoresist. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    FIGS.  1 A-F illustrates a side cross-sectional view of a semiconductor device at various stages of a method of forming a device feature in accordance with an embodiment of the invention; and  
         [0009]    FIGS.  2 A-F illustrates a side cross-sectional view of a semiconductor device at various stages of another method of forming a device feature in accordance with another embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0010]    [0010]FIG. 1A illustrates a side cross-sectional view of a semiconductor device  100  at a stage of a method of forming a device feature in accordance with an embodiment of the invention. The semiconductor device  100  comprises a substrate  102 , a device feature layer  104  deposited over the substrate  102 , a photoresist layer  106  deposited over the device feature layer  104 , a contact mask layer (CML)  108  deposited over the photoresist layer  106 , and an extreme ultraviolet (EUV) imaging layer  110  deposited over the CML  108 .  
         [0011]    The substrate  102  could be made of any substrate material which needs to be pattered as part of the manufacturing process, such as a silicon, silicon dioxide, silicon-germanium, gallium-arsenide (GaAS), indium-phosphide (InP), etc. The device feature layer  104  could be used to form any device feature such as a gate structure, emitter structure, base structure, an isolation structure, a spacer, a contact, etc. The photoresist layer  106  is a spun-on material that can be exposed with a relatively inexpensive deep ultraviolet (DUV) radiation (e.g. ˜248 nm wavelength) exposure tool or other non-DUV radiation exposure tool.  
         [0012]    The CML  108  should be such that the etching thereof should be substantially selective to that of the EUV imaging layer  110 . Depending on the relative thickness of the layers, the etch selectivity between the CML  108  and the EUV imaging layer  110  would be approximately greater than a factor of two (2). The CML  108  may be comprised of a spun-on organic material having a DUV reflective/absorptive coating, and having a thickness of approximately ½ wavelength of the exposing radiation (e.g. ˜100 nm). The CML  108  may also have an extinction coefficient (k) of approximately two (2) or greater and an index of refraction (n) of approximately 2.5. In such case, the CML  108  would absorb approximately 50 percent of the DUV radiation.  
         [0013]    Another example of a suitable CML  108  is a spun-on sacrificial light-absorbing material (SLAM) or the like (e.g. a spun-on glass). As discussed above, depending on the relative thickness of the layers, the etch selectivity between the SLAM CML  108  and the EUV imaging layer  110  would be approximately a factor of two or greater. The SLAM CML  108  may have a thickness of approximately 150 nm with an EUV absorption of approximately 82 percent. Such material, when properly dyed, could absorb a similar amount of DUV radiation. The SLAM CML  108  could be made thinner than 150 nm, which would require a decreased etch selectivity between the CML  108  and the EUV imaging layer  110 .  
         [0014]    Yet another example of a suitable CML  108  is a relatively thin layer of silicon which would have a desirable DUV reflective/absorptive property. For instance, the silicon CML  108 , having an index of refraction (n) of approximately 1.58, an extinction coefficient (k) of approximately 3.60, and a thickness of approximately 10 nm, would have a reflection of approximately 68 percent and an absorption of approximately 84 percent at a wavelength of 248 nm. Depending on the relative thickness of the layers, the etch selectivity between the silicon CML  108  and the EUV imaging layer  110  would be approximately a factor of two or greater.  
         [0015]    The EUV imaging layer  110  may have a thickness of approximately 50 nm. In this example, the EUV imaging layer  100  is spun-on over the CML  108 . Although an EUV imaging layer  110  is used to illustrate an embodiment of the invention, it shall be understood that other sub-DUV imaging layers may be used in place thereof. Sub-DUV imaging layer means an imaging layer which is responsive for lithography purposes to radiation having a wavelength of about 157 nm or less.  
         [0016]    [0016]FIG. 1B illustrates a side cross-sectional view of a semiconductor device  100  at a subsequent stage of a method of forming a device feature in accordance with an embodiment of the invention. According to the method, the EUV imaging layer  110  is patterned and developed to form a pattern  112  (e.g. an opening) that exposes an underlying region of the CML  108 . In this example, the EUV imaging layer  110  is exposed using an EUV exposure tool which uses an exposure radiation having a wavelength of approximately 13.5 nm. The remaining EUV imaging layer  110 ′ serves as a mask for the following patterning of the underlying CML  108 .  
         [0017]    [0017]FIG. 1C illustrates a side cross-sectional view of a semiconductor device  100  at a subsequent stage of a method of forming a device feature in accordance with an embodiment of the invention. According to the method, the CML  108  is etched to transfer the pattern of the EUV imaging layer  110 ′ to the CML  108  (e.g. forming an opening  114  that exposes an underlying region of the photoresist  106 ). In the case where the CML  108  is an organic material, the etching of the CML  108  may be performed by an oxygen (O 2 ) based reactive ion etching (RIE). In the case where the CML  108  is a SLAM, spun-on glass, or the like material, the etching of the CML  108  may be performed by etching in a sulfur hexafluoride (SF6) and argon (Ar) environment (other fluorinated chemistries could also be used, e.g. CH 2 F 2 ). In the case where the CML  108  is silicon, the etching of the CML  108  may be performed by suitable etching techniques. In all of these cases as well as other cases, the etching of the CML  108  should be selective with respect to the remaining EUV imaging layer  110 ′. The remaining CML  108 ′ serves as a mask for the following flood exposure and development of the photoresist  106 .  
         [0018]    [0018]FIG. 1D illustrates a side cross-sectional view of a semiconductor device  100  at a subsequent stage of a method of forming a device feature in accordance with an embodiment of the invention. According to the method, the remaining EUV imaging layer  110 ′ is removed. Then, the semiconductor device  100  is subjected to a flood exposure and then the photoresist  106  is developed to transfer the pattern of the CML  108 ′ to the photoresist  106  (e.g. to form opening  116  that exposes the underlying region of the device feature layer  104 ). In this example, the exposure of the photoresist  106  may be performed with a relatively inexpensive DUV flood exposure tool (i.e. not requiring the use of imaging optics). In general, the flood exposure wavelength, CML material, and photoresist ( 106 ) material would be matched for optimal performance, i.e. the flood exposure does not necessarily need to be done with DUV.  
         [0019]    [0019]FIG. 1E illustrates a side cross-sectional view of a semiconductor device  100  at a subsequent stage of a method of forming a device feature in accordance with an embodiment of the invention. According to the method, the remaining CML  108 ′ is removed. Then, the remaining photoresist  106 ′ is subjected to a thermal cycle, known as a “hard bake,” to harden the material, enabling it to serve as a mask for the final etch of the underlying substrate.  
         [0020]    [0020]FIG. 1F illustrates a side cross-sectional view of a semiconductor device  100  at a subsequent stage of a method of forming a device feature in accordance with an embodiment of the invention. According to the method, the etching of the device feature layer  104  is performed to form device features  104 ′ according to the original pattern formed on the EUV imaging layer  110 . Following the formation of the device feature  104 ′, the hardened photoresist  106 ′ is removed.  
         [0021]    The following method of forming a device feature in accordance with another embodiment is a variation of the method previously described. The following method eliminates the use of the CML layer. Accordingly, the EUV imaging layer is deposited over the photoresist. As will be discussed, the photoresist is developed in a manner that the etch selectivity of the photoresist is greater than the EUV imaging layer such that the EUV imaging layer does not sufficiently degrade in the patterning and development of the photoresist.  
         [0022]    [0022]FIG. 2A illustrates a side cross-sectional view of a semiconductor device  100  at a stage of an alternative method of forming a device feature in accordance with another embodiment of the invention. The semiconductor device  200  comprises a substrate  202 , a device feature layer  204  deposited over the substrate  202 , a photoresist layer  206  deposited over the device feature layer  204 , and a extreme ultraviolet (EUV) imaging layer  208  (i.e. a sub-DUV imaging layer) deposited over the photoresist layer  206 .  
         [0023]    [0023]FIG. 2B illustrates a side cross-sectional view of a semiconductor device  200  at a subsequent stage of the alternative method of forming a device feature in accordance with another embodiment of the invention. According to the method, the EUV imaging layer  208  is patterned and developed to form a pattern  210  (e.g. an opening) that exposes an underlying region of the photoresist layer  206 . In this example, the EUV imaging layer  208  is exposed using an EUV exposure tool which uses an exposure radiation having a wavelength of approximately 11-15 nm. The remaining EUV imaging layer  208 ′ serves as a mask for the following patterning and developing of the underlying photoresist layer  206 .  
         [0024]    [0024]FIG. 2C illustrates a side cross-sectional view of a semiconductor device  200  at a subsequent stage of the alternative method of forming a device feature in accordance with another embodiment of the invention. According to the method, the semiconductor device  200  is subjected to a flood exposure and then the photoresist  206  is developed to transfer the pattern of the EUV imaging later  208 ′ to the photoresist layer  206  (e.g. to form opening  212  that exposes the underlying region of the device feature layer  204 ). In this example, the exposure of the photoresist  206  may be performed with a relatively inexpensive DUV flood exposure tool (i.e. not requiring the use of imaging optics) or with a non-DUV flood exposure tool. The developing of the photoresist  206  is performed in a manner that does not substantially degrade the remaining EUV imaging layer  208 ′.  
         [0025]    [0025]FIG. 2D illustrates a side cross-sectional view of a semiconductor device  200  at a subsequent stage of the method of forming a device feature in accordance with an embodiment of the invention. According to the method, the remaining EUV imaging layer  208 ′ is removed. Then, the remaining photoresist  208 ′ is subjected to a hard bake.  
         [0026]    [0026]FIG. 2E illustrates a side cross-sectional view of a semiconductor device  200  at a subsequent stage of the alternative method of forming a device feature in accordance with an embodiment of the invention. According to the method, the etching of the device feature layer  204  is performed to form device features  204 ′ according to the original pattern formed on the EUV Imaging later  208 . Following the formation of the device feature  104 ′, the hardened photoresist  206 ′ is removed as shown in FIG. 2F.  
         [0027]    In the foregoing specification, the disclosure has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.