Abstract:
Methods and circuits for chain ring oscillators having a constant delay time over variations of temperature and variations of semiconductor manufacturing process while requiring low operating voltage only have been disclosed. A system current source includes a constant voltage circuit generating a constant voltage and hence a constant current via a resistance element. Main parts of the constant voltage circuit are an operational amplifier and a bandgap reference circuit. Using a series of current mirrors the constant currents are mirrored to current sources contained in each of n-inverter stages of the chain ring oscillator.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     (1) Field of the Invention  
         [0002]     This invention relates generally to ring oscillator circuits and relates more particularly to a ring oscillator with almost constant delay time even if the operating voltage drops down.  
         [0003]     (2) Description of the Prior Art  
         [0004]     Ring oscillators are used for a variety of purposes. Usually ring oscillators are used as an internally generated clocking source, or as a stage in a more complex system such as a voltage controlled oscillator (VCO) or a phase locked loop (PLL). They are often used to issue a refresh command for e.g. DRAM memory devices.  
         [0005]     For many applications, e.g. memory circuit design, a circuit having a constant delay is very important.  
         [0006]      FIG. 1  prior art shows a circuit diagram of a 5-stage CMOS inverter chain ring oscillator. Normally the number of stages is an odd number (3, 5, 7, or . . . ) with the output of the cascade fed back to the input of the inverter chain. An oscillator provides an output at a specific frequency with no input signal required.  
         [0007]     All these five inverter stages IN 1  to IN 5  have an identical circuit configuration. The first stage IN 1  is equipped with a CMOS inverter INV 1  comprising a PMOS transistor PI 1  and an NMOS transistor NI 1 . Furthermore a PMOS transistor PN 1  and a NMOS transistor NN 1  provide a current source for this inverter stage IN 1 . The other stages IN 2  to IN 5  are equipped identically.  
         [0008]     The output of the last stage IN 5  is the input INP 1  of the first inverter INV 1 . This input INP 1  is connected to the gates of the CMOS transistors PI 1  and NI 1 . The output OUT 1  of the first inverter INV 1  is connected to the drain of PMOS transistor PI 1 , to the drain of NMOS transistor NI 1  and the input of the second inverter stage IN 2 .  
         [0009]     The PMOS transistor PI 1  has its source connected to the operating voltage VCC via PMOS transistor PN 1 . The NMOS transistor NI 1  has its source connected to VSS voltage via NMOS transistor NN 1 .  
         [0010]     The current I 1  from voltage VCC to VSS through PMOS transistor P 1 , resistor R 1  and NMOS transistor N 1  follows the equation  
           I   ⁢           ⁢   1     =       VP   -   VN       R   ⁢           ⁢   1         ,       
 
 wherein VP is the voltage at the drain of transistor P 1  and VN is the voltage at the drain of transistor N 1 . The current I 1  is mirrored to the first inverter stage via the current mirrors P 1 /PN 1  and N 1 /NN 1 . Accordingly current I 1  is mirrored to the other inverter stages as well. In case the operating voltage VCC drops down, the voltage difference VP-VN becomes very small. Especially in the light of new semiconductor technologies (most fabs moved for the most advanced ICs from 0.18 micron to 0.13 microns) the typical operating voltages used to turn the transistors on and off have been reduced from e.g. 2.5 volts to 1.8 volts, the circuits are becoming more sensitive in case of variations during the manufacturing process or in case of changing temperatures. Even if all devices are within manufacturing specifications PMOS devices have a higher speed than normal if the threshold voltage is lower than normal and vice versa the speed of NMOS devices is lower than normal if their threshold voltage is higher than normal. 
 
         [0011]     This means that in case the threshold voltage of the PMOS or NMOS devices is higher than normal the difference of voltages VP and VN will be smaller. Vice versa the difference of voltages VP and VN will be larger if the threshold voltage of the PMOS or NMOS devices is lower than normal. Furthermore the semiconductor devices and resistor R 1  depend in their performance upon changes of temperature. Therefore the current I 1  and, by mirroring, the currents through the inverter stages IN 1  to IN 5  will be not constant but vary dependent upon the temperature and upon manufacturing process variations. Thus the delay time of the prior art ring oscillator will vary upon different temperatures and different manufacturing process parameters, even if these parameters are within specifications and even if the operating voltage VCC is regulated.  
         [0012]     Since voltage VP&gt;VN and voltage VP equals 
 
 VP=VCC−|V   THP1 |, 
 
 wherein |V THP1 | is the threshold voltage of P 1 , and voltage 
 
VN≅V THN1 , 
 
 wherein V THN   1  is the threshold voltage of N 1 , the following equation is valid: 
 
 VCC=|V   THP1   |+V   THN1   +I 1× R 1. 
 
 Accordingly the ring oscillator shown in  FIG. 1  prior art can only work precisely if the voltage difference I 1 ×R 1  is much larger than the sum of the threshold voltages |V THP1 |+V THN1  
 
         [0013]     There are known patents to control the delay time of ring oscillators:  
         [0014]     U.S. Pat. No. 6,813,210 to Okamoto et al. teaches a semiconductor memory device including a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.  
         [0015]     U.S. Pat. No. (6,188,293 to Miyagi et al.) discloses a low-power consumption integrated ring oscillator capable of stable operation throughout a wide voltage range without undergoing a large frequency change including a first constant voltage generating circuit having an enhancement mode P-MOS transistor and a depletion mode N-MOS transistor and a second constant voltage generating circuit having a depletion mode N-MOS transistor and an enhancement mode N-MOS transistor. A first constant voltage generated by the first constant voltage circuit is applied to a gate electrode of a P-MOS transistor of transmission gates connected between respective cascaded inverters of the ring oscillator. A second constant voltage generated by the second constant voltage generating circuit is connected to the gate electrode of an N-MOS transistor of the transmission gates. By this construction, current consumption is reduced and battery lifetime can be increased. The boosting circuit for writing and erasing an EEPROM circuit may be formed with the low power ring oscillator.  
         [0016]     U.S. Pat. No. (5,898,343 to Morgan) discloses a refresh circuit of a memory device including a ring oscillator with a frequency stabilizing circuit. The frequency stabilizing circuit produces compensated voltage signals in response to changes in supply voltage and temperature to modify the conductances of field-effect transistors of the frequency stabilizing circuit to compensate the conductive path of the discharge current of a capacitor from the ring oscillator in order to stabilize the oscillation frequency.  
       SUMMARY OF THE INVENTION  
       [0017]     A principal object of the present invention is to achieve a ring oscillator having a constant delay time requiring a low operating voltage.  
         [0018]     In accordance with the objects of this invention a method to achieve a constant delay time of ring oscillators requiring a low operating voltage has been accomplished. The method invented comprises, first, the provision of a chain ring oscillator comprising a system current source circuit comprising three branches, wherein a first branch comprises a constant voltage circuit and a resistance element and each of the second and third branches comprises two transistors, a system voltage supply VCC, and n stages, wherein each of the stages of said ring oscillator has a first and a second current source and an inverter circuit. The following steps of the method invented are to use said constant voltage circuit to generate in said first branch a first constant current, which is defined by the voltage generated by said constant voltage circuit and said resistance element, to mirror said first constant current to a first transistor of said second branch of said system current source circuit in order to generate a second constant current, and to mirror said second constant current to a second transistor of said third branch in order to generate a third constant current and to each of said second current sources of each of said stages of said ring oscillator. The last step is to mirror said third constant current to each of said first current sources of each of said stages of said ring oscillator.  
         [0019]     In accordance with the objects of this invention a chain ring oscillator having a constant delay time requiring a low operating voltage has been accomplished. The chain ring oscillator comprises, first, n identical cascaded stages of inverters, wherein each stage comprises a first and a second stage current source, wherein each of said stage current sources receives a current from a system current source, and an inverter circuit. Furthermore the circuit comprises a system supply voltage, and said system current source generating for each of said two current sources of all said n inverter stages a constant current, wherein said system current source comprises a constant voltage circuit.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     In the accompanying drawings forming a material part of this description, there is shown:  
         [0021]      FIG. 1  prior art shows a circuit diagram of a chain ring oscillator  
         [0022]      FIG. 2  shows a circuit diagram of a preferred embodiment of a chain ring oscillator according the present invention.  
         [0023]      FIG. 3  shows a flowchart of a method invented to achieve a constant delay time of a ring oscillator having a low operating voltage.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]     The preferred embodiments disclose methods and circuits for a CMOS chain ring oscillator having a constant delay time over variations of temperature and of manufacturing process variations.  
         [0025]      FIG. 2  shows a circuit diagram of a preferred embodiment of the present invention. This preferred embodiment shows a ring oscillator having five inverter stages S 1  to S 5 . It has to be understood that the ring oscillator shown in  FIG. 2  is a non-limiting example. The present invention supports any ring oscillators having any odd number (3, 5, 7, etc . . . ) of inverter stages.  
         [0026]     The present invention is characterized by having a system current source being constant upon different temperatures and upon different manufacturing process variations. In the preferred embodiment of  FIG. 2 a  constant system current source is implemented using a constant voltage circuit. This constant voltage circuit is based on the bandgap V bgref  of a semiconductor; this is a well-known physical value.  
         [0027]     The constant voltage circuit comprises an operational amplifier  20  having a positive and a negative input port. The bandgap reference voltage V bgref , which is generated from a bandgap reference circuit, not shown in  FIG. 2 , is the negative input of the operational amplifier  20 ; the voltage at node N 1  is the positive input port of the operational amplifier  20 . The output of the operational amplifier  20  is connected to the gate of PMOS transistor MP 1 . The source of the PMOS transistor MP 1  is connected to the operating voltage VCC, the drain of MP 1  is connected to the node N 1  and thus to the positive input of the operational amplifier  20 . The operational amplifier controls the voltage at node N 1  to the level of the bandgap reference voltage V bgref . Thus the current  12  flowing through PMOS transistor MP 1  is according to the equation:  
         I   ⁢           ⁢   2     =         N   ⁢           ⁢   1       R   ⁢           ⁢   2       =         V   bgref       R   ⁢           ⁢   2       .           
 
 The current  12  is constant over variations of transistor threshold voltages values and variations of temperature because resistor R 2  and the bandgap reference voltage V bgref  have constant values. The resistor R 2  must have a constant resistance over variations of temperature. In a preferred embodiment of the invention a salicide resistor has been selected for R 2 . 
 
         [0028]     The current through PMOS transistor MP 1  is mirrored to PMOS transistor MP 2 . In the preferred embodiment described transistor MP 2  has the same size as transistor MP 1 ; this means the channel width of MP 1  divided by the channel length of MP 1  is equal to channel width of MP 2  divided by the channel length of MP 2 . Usually both transistors MP 1  and MP 2  are identical. Thus in the preferred embodiment shown in  FIG. 2  the same current I 2  is flowing through PMOS transistor MP 2  and NMOS transistor MN 1  as through PMOS transistor MP 1  and resistor R 2 .  
         [0029]     It has to be understood that current mirror ratios other than 1.1 can be used for current mirror MP 1 /MP 2  and for current mirror MN 1 /MN 2 . The current, which mirrors to transistor PN 1 , is not necessarily equal to the current that mirrors to transistor NN 1 . Even though the currents may be different they are constant currents.  
         [0030]     The current through transistors MP 2  and MN 1  is mirrored again from transistor MN 1  to MN 2  and to NMOS transistors NN 1  to NN 5 . In the preferred embodiment described here the current mirror ratio is 1:1 again, i.e. transistors MN 1 , MN 2  and NN 1  to NN 5  have a same size. It has to be understood that transistors MN 2  and NN 1  to NN 5  can also have a different size than transistor MN 1 .  
         [0031]     The constant current I 2  through PMOS transistor MP 3  and NMOS transistor MN 2  is mirrored from transistor MP 3  to stage current sources PN 1  to PN 5  and respective the constant current through transistor MN 1  is mirrored to stage current sources NN 1  to NN 5 . Therefore a constant current is flowing through all inverter stages.  
         [0032]     Thus the delay time of the circuit invented is, by regulating the voltage at both node N 1  and at VCC level to constant levels, almost constant over variations of manufacturing process parameters or over variations of temperature.  
         [0033]     The tracking nodes VPN and VNN shown in  FIG. 2  have a much larger voltage range than the nodes VP and VN shown in  FIG. 1  prior art. Therefore the circuit of the present invention can work precisely under lower operating voltage. The circuit invented can work precisely if the operating voltage VCC is larger than VPN+V DSMIN  (minimum drain-source voltage) of NMOS transistor MN 2  or if VCC is larger than VNN+V DSMIN  of PMOS transistor MP 2 , depending on which of both values is larger.  
         [0034]     It has to be understood that the provision of a constant voltage and of constant currents according to the present invention applies for any kind of chain ring oscillators having any odd number of stages.  
         [0035]      FIG. 3  illustrates a flowchart of a method to achieve an almost constant delay time of a ring oscillator. Step  30  illustrates the provision of a chain ring oscillator comprising a system current source circuit comprising three branches, wherein a first branch comprises a constant voltage circuit and a resistance element and each of the second and third branches comprises two transistors, a system voltage supply VCC, and n stages, wherein each of the stages of said ring oscillator has a first and a second current source and an inverter circuit. Any resistance element, having a constant resistance over temperature changes, could be used instead of a resistor. In a preferred embodiment of the invention a salicide resistor has been selected for this resistance element. Step  31  describes the usage of said constant voltage circuit to generate in said first branch a first constant current, which is defined by the voltage generated by said constant voltage circuit and said resistance element. In step  32  said first constant current is mirrored to a first transistor of said second branch of said system current source circuit in order to generate a second constant current. In step  33  said second constant current is mirrored to a second transistor of said third branch in order to generate a third constant current and to each of said second current sources of each of said stages of said ring oscillator. In the last step  34  said third constant current is mirrored to each of said first current sources of each of said stages of said ring oscillator.  
         [0036]     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.