Abstract:
A drive circuit, for a display apparatus, capable of preventing the occurrence of malfunctions, when the power is turned on, and the destruction of an output device. The drive circuit comprises an edge pulse generation circuit for generating a front edge pulse and a back edge pulse of an input signal, a first level shift circuit for converting the front edge pulse, a second level shift circuit for converting the back edge pulse, a logic circuit, a flip-flop circuit, a setup resistor connected to a signal line in the flip-flop circuit or in the post stage of the flip-flop circuit, an output amplifier circuit connected to the post stage of the setup resistor, and an output device connected to the output amplifier circuit, wherein a capacitive load of the display apparatus is driven by the output device and the setup resistor is connected between the power supply signal line of the output amplifier circuit and the signal line.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to a drive circuit for a display apparatus and to a plasma display apparatus and, more particularly, to an improvement in the timing of a drive signal for causing a sustain discharge to occur.  
         [0002]     The plasma display apparatus has been put into practical use as a flat display and is expected to act as a thin display with high luminance.  FIG. 1  is a diagram showing the general configuration of a conventional three-electrode AC-driven type plasma display apparatus. As shown schematically, the plasma display apparatus comprises a plasma display panel (PDP)  1  constituted of two substrates having a plurality of X electrodes (X 1 , X 2 , X 3 , . . . , Xn) and a plurality of Y electrodes (Y 1 , Y 2 , Y 3 , . . . , Yn) arranged adjacently, a plurality of address electrodes (A 1 , A 2 , A 3 , . . . , Am) arranged in the direction perpendicular to that of the X and Y electrodes, and phosphors arranged at the crossings of the electrodes, wherein a discharge gas is sealed in between the two substrates, an address driver  2  that applies an address pulse to the address electrode, an X electrode drive circuit  3  that applies a sustain discharge pulse to the X electrode, a scan driver  4  that applies a scan pulse sequentially to the Y electrode, a Y electrode drive circuit  5  that supplies a sustain discharge pulse to be applied to the Y electrode to the scan driver  4 , and a control circuit  6  to control each part, wherein the control circuit  6  further comprises a display data control section  7  including a frame memory and a drive control section constituted of a scan driver control section  9  and a common driver control section  10 . The X electrode drive circuit  3  and the Y electrode driver circuit  5  are provided with a sustain circuit that outputs a sustain pulse and the sustain circuit has a sustain output device. As the plasma display apparatus is widely known, a more detailed description of the whole apparatus is not given here but only the X electrode drive circuit  3  and the Y electrode drive circuit  5  relating to the present invention are further explained. The X electrode drive circuit, the scan driver, and the Y electrode drive circuit of the plasma display apparatus are disclosed in, for example, European Patent No. 1139323. U.S. Pat. No. 5,502,412 discloses a power transistor drive circuit and an IC, which integrally incorporates the power transistor drive circuits into one chip, to be used in such a driver.  
         [0003]      FIG. 2  is a block diagram showing the general configuration of a power transistor drive circuit disclosed in U.S. Pat. No. 5,502,412, and as shown by the broken line, the whole is provided in an IC  11 . In the plasma display apparatus, the power transistor drive IC shown in  FIG. 2  is used as a pre-drive circuit for driving the sustain output device. The power transistor drive IC  11  shown in  FIG. 2  amplifies a high-level input signal HIN in an input circuit  21 , converts the signal into a voltage on the basis of a high-level reference voltage Vr in a high-level shift circuit  22 , and outputs the voltage as a high-level output voltage HO via an output amplifier circuit  23 . Moreover, the power transistor drive IC amplifies a low-level input signal LIN in an input amplifier circuit  24  and, after inputting the signal to an output amplifier circuit  26  via a delay circuit  25  and amplifying the signal therein, outputs the signal as a low-level output voltage LO. Reference numerals  12  and  13  denote the input terminals of the high-level input signal HIN and the low-level input signal LIN, reference numerals  16  and  19  denote the output terminals of the high-level output voltage HO and the low-level output voltage LO, reference numeral  15  denotes the supply terminal of a high-level power supply voltage Vc, reference numeral  17  denotes the supply terminal of the high-level reference voltage Vr, reference numeral  18  denotes the supply terminal of a low-level power supply voltage Vd, and reference numeral  20  denotes the ground terminal.  
         [0004]     In the power transistor drive IC shown in  FIG. 2 , the delay circuit  25  serves to adjust a difference tdLH (HO) in rise time between the high-level input signal HIN and the high-level output voltage HO so as to be equal to a difference tdLH (LO) in rise time between the low-level input signal LIN and the low-level output voltage LO. Further, the delay circuit  25  serves also to adjust a difference tdHL (HO) in fall time between the high-level input signal HIN and the high-level output voltage HO so as to be equal to a difference tdHL (LO) in fall time between the low-level input signal LIN and the low-level output voltage LO.  
         [0005]     When the power transistor drive IC shown in  FIG. 2  is used as a pre-drive circuit in a plasma display apparatus, sustain output devices such as a power MOSFET or an IGBT (Insulated Gate Bipolar Transistor) are connected to the output terminals  16  and  19  thereof. In the plasma display apparatus (PDP apparatus), a sustain pulse is generated by turning on/off the sustain output device and the generated sustain pulse is supplied to the X electrode and the Y electrode of the plasma display panel (PDP).  
         [0006]     In  FIG. 2 , reference symbol C 21  denotes a parasitic capacitor between the output terminal of the high-level shift circuit  22  and the power supply terminal (line) of the output amplifier circuit  23  and reference symbol C 22  denotes a parasitic capacitor between the output terminal of the high-level shift circuit  22  and the reference voltage terminal (line) of the output amplifier circuit  23 . These parasitic capacitors are formed by the devices used to constitute the output section of the high-level shift circuit  22  and the input section of the output amplifier circuit  23 . Reference symbol R 3  denotes a setup resistor for turning the output voltage to the “low (L)” level (that is, the voltage between the terminals  16  and  17  is about 0 V) when the power is turned on.  
         [0007]     In the conventional circuit, a setup resistor R 3  is realized by a diffused resistor.  FIG. 3  show a sectional view of a diffused resistor formed on the IC substrate. As shown in  FIG. 3 , an N-type diffused layer  28  is provided on a P-type substrate  27  and a P-type diffused resistor layer  29  is provided thereon. Terminals T 1  and T 2  are provided at two separate points on the P-type diffused resistor layer  29  as terminals of the resistor. As the N-type diffused layer  28  is connected to the power supply voltage line Vc, a parasitic capacitor Cr is formed between the power supply voltage terminal Vc and the P-type diffused resistor layer  29  (diffused resistor).  
         [0008]     Therefore, if the diffused resistor is used as the setup resistor R 3  shown in  FIG. 2 , the parasitic capacitor Cr of the diffused resistor is connected between the output section of the high-level shift circuit  22  and the power supply voltage line Vc, that is, in parallel to a capacitor C 1 , as shown in  FIG. 2 .  
         [0009]      FIG. 4  shows the detail of the conventional circuit configuration in which the setup resistor R 3  constituted of the diffused resistor is provided between the high-level shift circuit and the output amplifier section shown in  FIG. 2 . In the circuit shown in  FIG. 4 , an edge pulse generation circuit  31  detects the front edge of an input signal V 1  and generates a front edge pulse that rises at the front edge and has a predetermined pulse width. The front edge pulse is inputted to a transistor Q 1 , converted into a signal VS 1 , and then is supplied to a logic circuit  32 . The edge pulse generation circuit  31  further detects the back edge of the input signal V 1  and generates a back edge pulse that rises at the back edge and has a predetermined pulse width. The back edge pulse is inputted to a transistor Q 2 , converted into a signal VR 1 , and then is supplied to the logic circuit  32 . The transistors Q 1  and Q 2  are referred to as first and second level shift circuits, respectively.  
         [0010]     The logic circuit  32  generates a set signal VS 2  that rises at the front edge of the signal VS 1  and falls at the front edge of the signal VR 1  and a reset signal VR 2  that falls at the front edge of the signal VS 1  and rises at the front edge of the signal VR 1 . Moreover, the logic circuit  32  has a simultaneously active output preventing function that prevents the signals VS 1  and VR 1  from turning to the H level simultaneously.  
         [0011]     The set signal VS 2  and the reset signal VR 2  are inputted to a flip-flop circuit  33 . The flip-flop circuit  33  comprises inverter circuits INV 1  and INV 2 , and NAND circuits NAND 1  and NAND 2 , and generates a signal VB that rises at the rise edge of the set signal VS 2  and falls at the rise edge of the reset signal VR 2 .  
         [0012]     In the circuit shown in  FIG. 4 , the transistors Q 1  and Q 2  (the first and second level shift circuits) are required to be on only while the front edge pulse and the back edge pulse generated by the edge pulse generation circuit  31  and having the predetermined pulse width exist, therefore, the time during which the transistors Q 1  and Q 2  are on can be shortened when the level shift operation is carried out. Due to this, the power loss caused by the transistors Q 1  and Q 2  and the resistors R 1  and R 2  can be reduced.  
         [0013]     U.S. Pat. No. 5,514,981 describes a circuit similar to that shown in  FIG. 4 .  
         [0014]     European Patent No. 1139323 describes a sustain circuit of a plasma display apparatus using the circuit configuration shown in  FIG. 2  and  FIG. 5  is a diagram showing an example thereof.  
       SUMMARY OF THE INVENTION  
       [0015]     In the case where the circuit shown in  FIG. 2  is used in the sustain circuit shown in  FIG. 5 , when the power of the circuit is turned on, the output voltage HO is fixed to the “high (H)” level and an abnormal current flows through an output device CU or an output device LU in the sustain circuit shown in  FIG. 5 , and it has been found that there is the possibility that the output device CU or the output device LU may be destroyed. This is because a rush of current flows through the parasitic capacitor Cr of the diffused resistor used as the setup resistor R 3  and the capacitor C 21  in the circuit shown in  FIG. 2  and  FIG. 4  when the power is turned on, and the current causes a voltage to develop across both ends of the setup resistor R 3  and, therefore, the output voltage HO is fixed to the H level.  
         [0016]     In the circuit shown in  FIG. 5 , therefore, in order to prevent malfunctions caused by the rush of current when the power is turned on, the wide-band high-frequency capacitive device C 1  is connected in parallel to a low-frequency high-capacitance capacitive device C 11  such as an electrolytic capacitor and the power supply voltage Vc is prevented from rising sharply to avoid malfunctions.  
         [0017]     Also when a voltage Vcp to be supplied to the plasma display panel changes sharply toward the negative direction, there is the possibility that the output voltage HO is set to the H level. Therefore, in order to prevent the voltage Vcp from changing sharply toward the negative direction, a protective diode D 7  is provided.  
         [0018]     The first object of the present invention is to prevent output devices from being destroyed by avoiding malfunctions when the power is turned on.  
         [0019]     The second object of the present invention is to make it possible to prevent the output devices from being destroyed by the malfunctions without using the high-frequency capacitive device C 1  and the protective diode D 7  and to dispense with the use of the high-frequency capacitive device C 1  and the protective diode D 7 .  
         [0020]     In order to attain the above-mentioned objects, a drive circuit for a display apparatus according to a first aspect of the present invention is characterized in that when a diffused resistor is connected as a setup resistor, the resistor is connected between a power supply voltage line of an output amplifier circuit and a signal line. It is necessary that the output voltage returns to the L level when the part of the signal line to which the setup resistor is connected returns to the H level.  
         [0021]     If connection is done as in the first aspect, the parasitic capacitor due to the diffused resistor is connected in parallel to the setup resistor between the power supply voltage line of the output amplifier circuit and the signal line and, as a result, the rush of current when the power is turned on is made to bypass the setup resistor and flow through the parasitic capacitor formed by the diffused resistor. Due to this, the voltage that develops across both ends of the setup resistor because of the rush of current can be reduced and it is more surely possible to set the H level by the current that flows through the parasitic capacitor formed by the diffused resistor.  
         [0022]     In order to attain the above-mentioned objects, a drive circuit for a display apparatus according to a second aspect of the present invention is characterized in that the capacitance between the output terminal of a flip-flop circuit and the power supply voltage line of the output amplifier circuit is smaller than the capacitance between the output terminal of the flip-flop circuit and the power supply voltage line that supples an output reference voltage.  
         [0023]     In the second aspect, the capacitor C 1  between the output terminal of the flip-flop circuit and the power supply voltage line of the output amplifier circuit and a capacitor C 2  between the output terminal of the flip-flop circuit and the power supply voltage line that supplies the output reference voltage are connected in series and when the power is turned on, a rush of current flows through C 1  and C 2  connected in series. The voltage of the output terminal of the flip-flop circuit due to this is determined by the ratio of the capacitance of C 1  to that of C 2  and, therefore, if the capacitance of C 2  is made greater than that of C 1 , the voltage that develops across both ends of C 2  due to the rush of current can be reduced and malfunctions can be avoided. The capacitances of the capacitors C 1  and C 2  may be set by adjusting the size of the transistors in the post stage and the chip size of devices constituting the inverter circuit, or by connecting capacitive devices so that the conditions are satisfied.  
         [0024]     In order to attain the above-mentioned objects, a drive circuit for a display apparatus according to a third aspect of the present invention is characterized in that a setup resistor is constituted of a polysilicon resistor.  
         [0025]     According to the third aspect, the setup resistor is constituted of a polysilicon resistor. As the polysilicon resistor is formed on the N-type diffused layer connected to the reference voltage line, there is no parasitic capacitor between the polysilicon resistor and the power supply voltage line. Therefore, the occurrence of malfunction can be suppressed.  
         [0026]     In order to attain the above-mentioned objects, a drive circuit for a display apparatus according to a fourth aspect of the present invention is characterized in that a reset delay circuit is connected to the previous or post stage of a second NAND circuit in the configuration having the flip-flop circuit shown in  FIG. 4 .  
         [0027]     In the circuit according to the fourth aspect, the output of the second NAND circuit is delayed by the reset delay circuit compared to the output of a first NAND circuit and, therefore, the output of the second NAND circuit determines the output of the flip-flop circuit. As a result, the output of the flip-flop circuit turns to the L level without fail, the output voltage also turns to the L level without fail, and thus malfunctions can be prevented.  
         [0028]     If the above-mentioned drive circuit is used in the sustain circuit of a plasma display apparatus, the second object can be attained. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     The features and advantages of the invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which:  
         [0030]      FIG. 1  is a diagram showing the general configuration of a plasma display apparatus.  
         [0031]      FIG. 2  is a diagram showing a conventional power transistor drive IC.  
         [0032]      FIG. 3  is a sectional configuration of a diffused resistor used in a conventional case.  
         [0033]      FIG. 4  is a diagram showing a detailed configuration of a high-level shift circuit and an output amplifier circuit in a conventional case.  
         [0034]      FIG. 5  is a diagram showing the configuration of a sustain circuit in a conventional case.  
         [0035]      FIG. 6  is diagram showing the configuration of a high-level shift circuit and an output amplifier circuit in a first embodiment of the present invention.  
         [0036]      FIG. 7  is diagram showing the configuration of a high-level shift circuit and an output amplifier circuit in a second embodiment of the present invention.  
         [0037]      FIG. 8  is diagram showing the configuration of a high-level shift circuit and an output amplifier circuit in a third embodiment of the present invention.  
         [0038]      FIG. 9A  and  FIG. 9B  are diagrams showing sectional configurations of a diffused resistor used in the third embodiment.  
         [0039]      FIG. 10  is diagram showing the configuration of a high-level shift circuit and an output amplifier circuit in a fourth embodiment of the present invention.  
         [0040]      FIG. 11  is a diagram showing another configuration example of a reset delay circuit in the fourth embodiment.  
         [0041]      FIG. 12  is diagram showing the configuration of a high-level shift circuit and an output amplifier circuit in a fifth embodiment of the present invention.  
         [0042]      FIG. 13  is diagram showing the configuration of a high-level shift circuit and an output amplifier circuit in a sixth embodiment of the present invention.  
         [0043]      FIG. 14  is a diagram showing the configuration of a sustain circuit to which the configuration of the high-level shift circuit and the output amplifier circuit according to the second embodiment of the present invention is applied.  
         [0044]      FIG. 15  is a diagram showing another example of a power transistor drive IC to which the configuration of the high-level shift circuit and the output amplifier circuit according to the second embodiment of the present invention is applied.  
         [0045]      FIG. 16  is a diagram showing the configuration of a sustain circuit using the IC shown in  FIG. 15 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0046]     Embodiments of the present invention are described below with reference to drawings.  
         [0047]      FIG. 6  is a diagram showing the configuration of a level shift circuit and an output amplifier circuit in a drive circuit for a display apparatus in a first embodiment of the present invention, corresponding to  FIG. 4 . As is obvious from comparison with  FIG. 4 , while, in a conventional case, a setup resistor R 3 , which is a diffused resistor, is connected between the output of a first NAND circuit NAND  1  of a flip-flop  33  and a reference voltage line Vr, in the circuit in the first embodiment, a setup resistor R 4 , which is a diffused resistor, is connected between the connection point of a first inverter circuit INV 1  of the flip-flop  33  and the first NAND circuit NAND  1  and a power supply voltage line Vc.  
         [0048]     In the circuit in the first embodiment, when the output signal of INV 1  is at the H level, an output voltage HO turns to the L level. In the circuit shown in  FIG. 6 , a parasitic capacitor Cr, when a diffused resistor is used for the setup resistor R 4 , is connected in parallel with the setup resistor R 4 . Because of this, a rush of current that flows through the parasitic capacitor Cr when the power is turned on bypasses the setup resistor R 4 . As a result, it is possible not only to suppress the voltage that develops across both ends of the setup resistor R 4  due to the rush of current when the power is turned on but also to more surely return the output voltage of INV 1  to the H level because of the rush of current that flows through the parasitic capacitor Cr, therefore, it is possible to surely return the output voltage HO to the L level.  
         [0049]     As a result, when the circuit shown in  FIG. 6  is applied to the drive circuit shown in  FIG. 2  to drive the output device of the sustain circuit shown in  FIG. 5 , a problem of circuit destruction can be avoided, which may occur when a conventional circuit is used because the output voltage HO is fixed to the H level when the power is turned on and the output device in the post stage is brought into the on state to cause an over current to flow.  
         [0050]      FIG. 7  is a diagram showing the configuration of a level shift circuit and an output amplifier circuit in a drive circuit for a display apparatus in a second embodiment of the present invention. As is obvious from comparison with the circuit in the first embodiment shown in  FIG. 6 , the circuit differs from that in the first embodiment in that an inverter circuit INVA for inverting the output signal of the flip-flop circuit  33  is provided, INV  3  is eliminated, an N-type transistor Q 3  is replaced with a P-type transistor Q 5 , R 4  is eliminated, and a setup resistor R 5 , which is a diffused resistor, is connected between the output terminal of INVA and the power supply voltage line Vc. A transistor Q 6  is of as N-type, the same as the transistor Q 4 .  
         [0051]     In the circuit in the second embodiment, when the gate voltage of Q 5  is at the H level, Q 5  turns off and Q 6  turns on and the output voltage HO turns to the L level. Therefore, when a diffused resistor is used for the setup resistor R 5 , the parasitic capacitor Cr is connected in parallel to the setup resistor R 5 , as a result. Because of this, as in the first embodiment, even when the rush of current flows when the power supply voltage Vc is turned on, the gate voltage of Q 5  turns to the H level and the output voltage HO turns to the L level. Therefore, it is unlikely that the output device connected to the post stage is fixed in the on state and that the output device is destroyed by the over current.  
         [0052]      FIG. 8  is a diagram showing the configuration of a level shift circuit and an output amplifier circuit in a drive circuit for a display apparatus in a third embodiment of the present invention, corresponding to  FIG. 4 . As is obvious from comparison with  FIG. 4 , the configuration is similar to that of the circuit shown in  FIG. 4  but the difference lies in that a polysilicon resistor is used for the setup resistor R 3 .  
         [0053]      FIG. 9A  is a sectional view of a polysilicon resistor formed on an IC substrate and  FIG. 9A B is a top view of a resistor pattern. As shown in  FIG. 9A , a P-type diffusion layer  52  is provided on a P-type substrate  51  and a polysilicon layer  53  is provided thereon. The polysilicon layer  53  has a pattern  54  as shown in  FIG. 9B  and terminals T 1  and T 2  are provided on both ends of the pattern  54  as the terminals of the resistor. The resistance is determined based on the length of the pattern  54 . Here, the P-type diffusion layer  52  is connected to the reference voltage line Vr but not to the power supply voltage line Vc, therefore, a parasitic capacitance is unlikely to occur between the polysilicon layer  53  and the power supply voltage line Vc (or is so small as to be negligible). In other words, if a polysilicon resistor is used, the parasitic capacitor Cr, that is generated when a diffused resistor is used, can be eliminated. As a result, the rush of current that may flow via the parasitic capacitor Cr when the power supply voltage Vc is turned on can be reduced. Therefore, the voltage that develops across both ends of the setup resistor R 3  when the power supply voltage Vc is turned on can be reduced. As a result, the output voltage HO is fixed to the H level, the output device in the post stage enters the on state, and the problem of destruction of the output device by the over-current can be avoided.  
         [0054]     In the third embodiment, when the capacitance of a parasitic capacitor C 22  is greater than the capacitance of a parasitic capacitor C 21 , even if the resistor R 3  is eliminated, the output voltage HO is fixed to the H level, the output device in the post state enters the on state, and the problem of destruction of the output device by the over current can be avoided. This is explained below.  
         [0055]     In  FIG. 8 , in a state in which the setup resistor R 3  is eliminated, the parasitic capacitor C 21  is connected between the output terminal of the first NAND circuit of the first flip-flop  33  and the power supply voltage line Vc and the parasitic capacitor C 22  is connected between the output terminal of the first NAND circuit of the first flip-flop  33  and the reference voltage line Vc. Here, it is assumed that an attempt is made to realize a desired capacitance by connecting capacitive devices to the parts of the parasitic capacitors C 21  and C 22 , respectively. In this case, the capacitance is the combined capacitance of the parasitic capacitor and the capacitive device. Here, a description is given below on the assumption that the combined capacitor is the capacitors C 21  and C 22 . When the power supply voltage Vc is turned on, the rush of current flows to the capacitor C 2  via the capacitor C 21 . At this time, the voltage VB is determined by the division ratio of the capacitance of the capacitor C 21  to the capacitance of the capacitor C 22 . Therefore, if the capacitance of the capacitor C 22  is set greater than the capacitance of the capacitor C 21 , the voltage applied across both ends of the capacitor C 22  by the of rush current can be reduced.  
         [0056]     The above-mentioned condition may be realized by using only the parasitic capacitor without using the capacitive device. In such a case, the capacitances of the capacitors C 21  and C 22  can be set by adjusting the chip size of the device to be used for the transistor Q 3  and in the inverter INV  3  in the post stage.  
         [0057]     As described above, in the configuration shown in  FIG. 8 , by appropriately setting the capacitance of the capacitors C 21  and C 22 , it is possible to set the output voltage HO to the L level at the time of setup even if the setup resistor R 3  is not provided and thus a malfunction when the power supply voltage Vc is turned on can be avoided.  
         [0058]      FIG. 10  is a diagram showing the configuration of a level shift circuit and an output amplifier circuit in a drive circuit for a display apparatus in a fourth embodiment of the present invention. As is obvious from comparison with the circuit in the second embodiment shown in  FIG. 7 , the circuit in the present embodiment differs from the circuit in the second embodiment in that a reset delay circuit  33  constituted of inverter circuits INVB and INVC is further provided.  
         [0059]     In the circuit in the fourth embodiment, a signal VR 3  is generated by delaying a reset signal VR 2  output from a logic circuit  32  and the signal VR 3  is inputted to the flip-flop circuit  33 . As a result, the output signal of a second NAND circuit NAND  2  (the input signal of the first NAND circuit NAND  1 ) is delayed compared to the signal inputted to the first NAND circuit NAND  1  from the set signal VS 2  output from the logic circuit  32  via INV 1  by the amount according to the time to pass through the reset delay circuit  35 . Therefore, the time at which an output signal VB of the flip-flop circuit  33  is set by the set signal VS 2  is ahead of the time at which the output signal VB is reset by the reset signal VR 2 . Because of this, even if the set signal VS 2  and the reset signal VR 2  are output simultaneously such as when the power supply voltage Vc is turned on, the reset signal VR 2  to be inputted later determines the voltage level of the output signal VB of the flip-flop circuit  33 , therefore, the signal VB turns to the L level and the output voltage HO also turns to the L level.  
         [0060]     Similarly, even if the set signal VS 2  and the reset signal VR 2  are output simultaneously, such as when the noise pulse in the negative direction is added to the output reference voltage Vr, the reset signal VR 2  to be inputted later is effective for the level setting of the voltage VB because of being inputted later. Therefore, even if the set signal VS 2  and the reset signal VR 2  are output simultaneously such as when the noise pulse in the negative direction is added to the output reference voltage Vr, the voltage VB returns to the L level and the output voltage HO also returns to the L level.  
         [0061]     When the reset delay circuit  35  is provided, it is possible to prevent malfunctions when the power supply voltage Vc is turned on even if the setup resistor R 5  is eliminated. However, it is possible to more securely prevent malfunctions when the power supply voltage Vc is turned on by providing both the reset delay circuit  35  and the setup resistor R 5 .  
         [0062]     In the example described above, the inverter circuits INVB and INVC are connected in series in the reset delay circuit  35  but, preferably, the number of inverter circuits to be connected is set appropriately. Moreover, the reset delay circuit  35  can be realized by using circuits other than inverter circuits and, for example, can be realized by using a time constant circuit in which a resistor RR 3  and a capacitor CR 3  are connected, as shown in  FIG. 11 .  
         [0063]      FIG. 12  is a diagram showing the configuration of a level shift circuit and an output amplifier circuit in a drive circuit for a display apparatus in a fifth embodiment of the present invention. As is obvious from comparison with the circuit in the second embodiment shown in  FIG. 7 , the circuit in the present embodiment differs from the circuit in the second embodiment in that the reset delay circuit  35  constituted of a capacitor CRR is further provided.  
         [0064]     In the circuit in the fifth embodiment, the capacitor CRR of the reset delay circuit  35  delays the output signal of the second NAND circuit NAND  2 . As a result, the output signal (the input signal of NAND  1 ) is delayed compared to the signal inputted to NAND from the set signal VS 2  output from the logic circuit  32   1  via INV 1  by the amount corresponding to the passing through the reset delay circuit  35 . Therefore, the time at which the output signal VB of the flip-flop circuit  33  is set by the set signal VS 2  is ahead of the time at which the output signal VB is reset by the reset signal VR 2 . Because of this, even if the set signal VS 2  and the reset signal VR 2  are output simultaneously such as when the power supply voltage Vc is turned on, the reset signal VR 2  to be inputted later determines the voltage level of the output signal VB of the flip-flop circuit  33 . As a result, even if the set signal VS 2  and the reset signal VR 2  are output simultaneously such as when the power supply voltage Vc is turned on, the signal VB turns to the L level and the output voltage HO also turns to the L level.  
         [0065]     Similarly, even if the set signal VS 2  and the reset signal VR 2  are output simultaneously such as when the noise pulse in the negative direction is added to the output reference voltage Vr, the voltage VB turns to the L level and the output voltage HO also turns to the L level.  
         [0066]     As in the fourth embodiment, when the reset delay circuit  35  is provided, it is possible to prevent malfunctions when the power supply voltage Vc is turned on even if the setup resistor R 5  is eliminated. However, it is possible to more securely prevent malfunctions when the power supply voltage Vc is turned on by providing both the reset delay circuit  35  and the setup resistor R 5 .  
         [0067]      FIG. 13  is a diagram showing the configuration of a shift level circuit and an output amplifier circuit in a drive circuit for a display apparatus in a sixth embodiment of the present invention. As is obvious from comparison with the circuit in the fifth embodiment shown in  FIG. 12 , the circuit in the present embodiment differs from the circuit in the fifth embodiment in that the inverter circuits INV 1  and INV 2  are used as the reset delay circuit  35 .  
         [0068]     The reset delay circuit  35  in the sixth embodiment utilizes the input capacitance of the inverter circuits INV 1  and INV 2 . As a result, as in the fifth embodiment, the output signal of NAND  2  is delayed. Here, the two inverter circuits INV 1  and INV 2  are connected but if the capacitance is sufficient, INV 2  can be eliminated. Moreover, the number of inverter circuits can be further increased. The delay time provided by the reset delay circuit  35  can be adjusted by adjusting the number of inverter circuits provided in the reset delay circuit  35 . As the operation of the circuit of the sixth embodiment is the same as that of the fifth embodiment, no description is given here.  
         [0069]      FIG. 14  is a diagram showing the configuration when the configuration of the high-level shift circuit and the output amplifier circuit in the second embodiment shown in  FIG. 7  is applied to the X electrode drive circuit  3  and the Y electrode drive circuit  5  of the plasma display apparatus shown in  FIG. 1 , corresponding to  FIG. 4 . Power transistor drive ICs  11 A and  11 B have the configuration shown in  FIG. 2  to which the configuration in the second embodiment shown in  FIG. 7  is applied. In other words, the setup resistor R 3  is removed, the inverter circuit INVA to be connected to the output terminal in the high-level shift circuit  22  is provided, the resistor R 5  is connected between the output terminal of INVA and the power supply voltage line Vc, and the N-type transistor Q 3  is replaced with the P-type transistor Q 5 . By using the above-mentioned power transistor drive ICs  11 A and  11 B, the output devices CU, CD, LU, and LD are driven. As described above, in the configuration in the second embodiment, the output signal HO is unlikely to be fixed to the H level due to the rush of current when the power is turned on and, therefore, in the circuit shown in  FIG. 14 , the problem of destruction of the output devices CU and LU can be avoided, which is caused by malfunctions that may occur when the power supply voltage, which is supplied to the output amplifier circuit  23 , is turned on (the drive pulse to be supplied to the output devices CU and LU is fixed to the H level) and by similar malfunctions that may occur when the noise in the negative direction is added to the reference voltage (source voltage of the output devices CU and LU) of the output amplifier circuit  23 .  
         [0070]     Moreover, in the circuit shown in  FIG. 14 , the protective diode D 7  provided in the conventional case shown in  FIG. 5  can be eliminated because of the reason described above. In  FIG. 14 , a wide-range high-frequency capacitive device C 1  is shown and this can also be eliminated. However, in the circuit shown in  FIG. 14 , operations become more stable by the provision of the protective diode D 7  and the wide-range high-frequency capacitive device C 1 .  
         [0071]     In the application example described above, the configuration in the second embodiment is applied to the X electrode and Y electrode drive circuits (sustain circuits) of the plasma display apparatus but the configuration in  FIG. 1  and  FIG. 3  to  FIG. 6  can also be applied to the sustain circuit similar to the second embodiment. Moreover, in the application example described above, the case where the second embodiment is applied to the inside of the power transistor drive IC is explained, however, the same effect can also be obtained when the second embodiment is applied to a drive circuit that is not in the form of an IC.  
         [0072]      FIG. 15  is a diagram showing another configuration example of the power transistor drive IC to which the configuration in the second embodiment is applied. The IC is a 2-channel-input and 2-channel-output IC, which differs from the IC shown in  FIG. 2  and  FIG. 14  in that both channels have high-level shift circuits  42  and  45 . Each channel has the configuration in the second embodiment shown in  FIG. 7 . Because the two channels have the same circuit configuration, the variations in input/output delay time between the two channels (the respective differences between the respective front edges of input signals IN 1  and IN 2  and the respective front edges of output signals OUT 1  and OUT 2 ) can be further reduced compared to the IC shown in  FIG. 2  and  FIG. 14 .  
         [0073]      FIG. 16  is a diagram showing the configuration when the power transistor drive IC shown in  FIG. 15  is applied to the X electrode drive circuit  3  and the Y electrode drive circuit  5  of the plasma display apparatus, corresponding to  FIG. 14 . Power transistor drive ICs  31 A and  31 B are the IC shown in  FIG. 15 . In this circuit, in addition to the effect that can be obtained from the circuit shown in  FIG. 14 , the difference in delay time between the drive pulses supplied to the output devices CU and CD and the difference in delay time between the drive pulses supplied to the output devices LU and LD can be reduced. As a result, the timing of switching operation can be set more precisely to enable operations at a higher speed and therefore the number of sustain pulses can be increased and the display luminance can be improved.  
         [0074]     It is also possible to apply the configuration explained in the first and third to sixth embodiments to the IC shown in  FIG. 15  and to the sustain circuit shown in  FIG. 16 .  
         [0075]     As described above, according to the present invention, it is possible to prevent the destruction of output devices by preventing malfunctions when the power is turned on.  
         [0076]     Moreover, according to the present invention, as the normal operation can be attained without the high-frequency capacitive device connected to the power supply terminal in the output amplifier circuit and the protective diode connected to the reference voltage terminal in the output amplifier circuit, these devices can be eliminated.  
         [0077]     Still moreover, by applying the drive circuit for a display apparatus according to the present invention to a plasma display apparatus, it is possible to provide a plasma display apparatus with high reliability that does not cause malfunctions when the power is turned on.