Abstract:
Systems, methods, and computer products for evaluating robustness of a list scheduling framework. Exemplary embodiments include a method for evaluating the robustness of a list scheduling framework, the method including identifying a set of compiler benchmarks known to be sensitive to an instruction scheduler, running the set of benchmarks against a heuristic under test, H and collect an execution time Exec(H[G]), where G is a directed a-cyclical graph, running the set of benchmarks against a plurality of random heuristics H rand [G] i , and collect a plurality of respective execution times Exec(H rand [G]) i , computing a robustness of the list scheduling framework, and checking robustness check it against a pre-determined threshold.

Description:
TRADEMARKS 
       [0001]    IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to compilers, and particularly to systems, methods, and computer products for evaluating robustness of a list scheduling framework. 
         [0004]    2. Description of Background 
         [0005]    Performance problems in compilers are generally difficult to identify and diagnose. Newly introduced performance regressions could go unnoticed for extended periods of time unless great care is taken with performance regression testing. In practice, however, unmanned automated performance regression testing of compiler components continues to be a difficult problem. Furthermore, with increasing complexity of underlying hardware pipelines and memory hierarchies, failing to model these complex structures can result in generated code being significantly faster or slower than expected. 
         [0006]    What is needed is a framework for automated performance testing of instruction scheduler, where the framework is well suited to be used for daily regression testing in production compilers. 
       SUMMARY OF THE INVENTION 
       [0007]    Exemplary embodiments include a method for evaluating the robustness of a list scheduling framework, the method including identifying a set of compiler benchmarks known to be sensitive to an instruction scheduler, running the set of benchmarks against a heuristic under test, H and collect an execution time Exec(H[G]), where G is a directed a-cyclical graph, running the set of benchmarks against a plurality of random heuristics H rand [G] i , and collect a plurality of respective execution times Exec(H rand [G]) I , computing a robustness of the list scheduling framework, where the robustness is given by: 
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         [0000]    and checking robustness check it against a pre-determined threshold. 
         [0008]    Further exemplary embodiments include a system for evaluating the robustness of a list scheduling framework, the system including a computer processor, a compiler coupled to the processor, an instruction scheduler coupled to the compiler, a list scheduling framework robustness evaluation process residing on the processor and having instructions to identify a set of compiler benchmarks known to be sensitive to the instruction scheduler, run the set of benchmarks against a heuristic under test, H and collect an execution time Exec(H[G]), where G is a directed a-cyclical graph, run the set of benchmarks against a plurality of random heuristics H rand [G] i , and collect a plurality of respective execution times Exec(H rand [G]) I , compute a robustness of the list scheduling framework, where the robustness is given by: 
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         [0000]    check robustness check it against a pre-determined threshold and evaluate the random heuristics H rand [G] i , in response to Exec(h rand [G] i ) being a better execution time than Exec(H[G]) for the set of benchmarks. 
         [0009]    System and computer program products corresponding to the above-summarized methods are also described and claimed herein. 
         [0010]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
       TECHNICAL EFFECTS 
       [0011]    As a result of the summarized invention, technically we have achieved a solution which a framework is automated for performance testing of instruction scheduler, where the framework is well suited to be used for daily regression testing in production compilers. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0013]      FIG. 1  illustrates an exemplary system for evaluating the robustness of a list scheduling framework; and 
           [0014]      FIG. 2  illustrates a flowchart of a method for evaluating the robustness of a list scheduling framework in accordance with exemplary embodiments. 
       
    
    
       [0015]    The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    Exemplary embodiments include systems, methods and computer products for evaluating robustness of a list scheduling framework. In exemplary embodiments, instruction scheduling is a compiler optimization used to improve instruction-level parallelism, which improves performance on machines with instruction pipelines. In exemplary embodiments, testing and debugging methods include a micro-architectural model and list scheduler heuristics. Testing of micro-architecture can be implemented for complex underlying hardware pipelines and memory hierarchies. As such, in accordance with exemplary embodiments, a framework for automated performance testing of instruction scheduler can be implemented for daily regression testing in production compilers. 
         [0017]      FIG. 1  illustrates an exemplary system  100  for evaluating the robustness of a list scheduling framework. In exemplary embodiments, the system  100  includes a processing device  105  such as a computer, which includes a storage medium or memory  110 . The memory  110  can include any one or combination of volatile memory elements (e.g., random access memory (RAM, such as DRAM, SRAM, SDRAM, etc.)) and nonvolatile memory elements (e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM), tape, compact disc read only memory (CD-ROM), disk, diskette, cartridge, cassette or the like, etc.). Moreover, the memory  110  may incorporate electronic, magnetic, optical, and/or other types of storage media. Note that the memory  110  can have a distributed architecture, where various components are situated remote from one another, but can be accessed by the processing device  105 . 
         [0018]    A data repository  115  is coupled to and in communication with the processing device  105 . The system  100  can further include a compiler  120 . The compiler  120  can be any computer program (or set of programs) that translates text written in a computer language (the source language) into another computer language (the target language). The original sequence is usually called the source code and the output called object code. The system  200  can further include a list scheduling framework robustness evaluation process  125 , as further discussed herein. 
         [0019]    The general algorithm for a list scheduler involves topological re-ordering of a directed a-cyclical weighted graph (DAWG). The nodes in the graph represent each of the instructions in a basic block, while the directed edges between nodes identify the causal dependencies. In exemplary embodiments, basic block is a sequence of straight-line code of instructions with no branches leading inside the block and no branches going outside of the block. Generally, the edges of the graph are annotated with a weight representing a sum of delays and latencies between the nodes. Delay is incurred, for example, as a result of pipeline stalls that typically occur when an instruction requires the results of another instruction before it can execute. Latency is a characteristic lag time resulting from the execution of an instruction. Both delay and latency may be measured in the same time unit, namely execution cycles, and may be summed together to obtain the “weight” or total time in cycles. In exemplary embodiments, the weighted edges are then used by a given heuristic, H, which loosely couples the topological sort of the DAWG to a better re-ordering of the associated instruction sequence. Such heuristics are proven suboptimal as the problem of scheduling is known to be nondeterministic polynomial-time (NP) hard. 
         [0020]    In accordance with exemplary embodiment, the topological sort of a graph, G, can be represented using a heuristic, H, as H[G]. In addition, the actual execution time for a given topological sort H[G] can be represented as Exec{H[G]}. 
         [0021]    It is appreciated that several sources of error or inaccuracy can be present in a list scheduling implementation. For example, the weights in the DAWG, G, could model the hardware inaccurately, or the heuristic, H, could be too loosely coupled to the target architecture. The systems and methods described herein automatically evaluate the robustness of the framework represented by H[G]. 
         [0022]    In accordance with exemplary embodiments, the framework under investigation is compared against a set of non-informative heuristics H rand [G], where H rand [G] can be described as a set of random topological sorts for the given DAWG, G, Comparison requires definition of sufficient spanning set H rand [G] as well as a given distance measure ∥*∥. Given these functionals, a robustness measure can then be defined as: 
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         [0023]    Therefore, for unmanned daily regression testing, a methodology is identified for a compiler  120  having benchmarks that are sensitive to an instruction scheduler.  FIG. 2  illustrates a flowchart of a method  200  for evaluating the robustness of a list scheduling framework in accordance with exemplary embodiments. At step  210 , the method  200  identifies a set of benchmarks know to be sensitive to instruction scheduler. At step  215 , the benchmarks are run against the heuristic under test, H, and the method  200  collects the execution time Exec(H[G]) At step  220 , the same benchmarks are run against several random heuristics H rand [G] i , and the method  200  collects the execution times Exec(H rand [G]) i . At step  230 , the robustness is computed and checked against some chosen threshold to decide if the robustness is acceptable or not. In exemplary embodiments, if the desired robustness is not achieved, the set of h rand [G] i , where Exec(h rand [G] i ) is better than Exec(H[G]), can be analyzed to improve the heuristic under investigation, and thus the method  200  can be repeated. 
         [0024]    In an example using a Gaussian metric, the mean and variance of Exec[H rand (G)] can be represented respectively as: 
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         [0025]    The robustness of H[G] can then be described as the area under Gaussian(μ H , σ B ) that performs worst than Exec(H[G]). This metric can he computed over a set of DAWGs, G. The robustness would then be the sum of the areas under all curves normalized against the size of the set G. 
         [0026]    The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof. 
         [0027]    As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold, separately. 
         [0028]    Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided. 
         [0029]    The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0030]    While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.