Abstract:
A noise-shaping time-to-digital converter has a large range and high resolution. The time-to-digital converter includes a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal. The time-to-digital converter includes a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal. The time-to-digital converter includes an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code. The time-to-digital converter includes a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based on a reference signal and an enable signal. The time-to-digital converter includes a feedback circuit to generate the phase-adjusted feedback signal based on the reference signal and the gating signal.

Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention is related to data converters and more particularly to analog-to-digital converters. 
     2. Description of the Related Art 
     In general, a time-to-digital converter is an analog-to-digital data converter that generates a digital code indicative of an input time interval, typically based on a high frequency reference clock signal. Time-to-digital converters are used to measure events in various applications including clocking applications (e.g., digital phase-locked loops) and sensor applications (e.g., time-of-flight measurements). Conventional time-to-digital converters support a relatively narrow interval range in order to improve the time resolution of the converter or sacrifice time resolution for a wider interval range. Accordingly, improved techniques for time-to-digital conversion are desired. 
     SUMMARY OF EMBODIMENTS OF THE INVENTION 
     Noise-shaping time-to-digital conversion techniques are described. In at least one embodiment of the invention, an apparatus includes a time-to-digital converter. The time-to-digital converter includes a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal. The time-to-digital converter includes a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal. The time-to-digital converter includes an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code. The time-to-digital converter includes a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based on a reference signal and an enable signal. The time-to-digital converter includes a feedback circuit configured to generate the phase-adjusted feedback signal based on the reference signal and the gating signal. The digital-to-time converter may selectively provide as the gating signal, a version of the enable signal selected from a plurality of versions of the enable signal according to the digital phase error code. The feedback circuit may gate the reference clock signal with the gating signal to generate the phase-adjusted feedback signal. The digital-to-time converter may convert a most-significant portion of the digital phase error code to the gating signal. The feedback circuit may include a second digital-to-time converter configured to convert a least significant portion of the digital phase error code to the phase-adjusted feedback signal based on the gating signal. The gating signal may be the phase-adjusted feedback signal. 
     In at least one embodiment of the invention, a method includes converting an input signal to a digital phase error code. The converting includes generating a phase error signal based on a phase-adjusted feedback signal and the input signal. The converting includes integrating the phase error signal to generate an analog integrated phase error signal. The converting includes converting the analog integrated phase error signal to the digital phase error code. The converting includes converting at least a portion of the digital phase error code to a gating signal based on a reference signal and an enable signal. The converting includes generating the phase-adjusted feedback signal based on the reference signal and the gating signal. Converting at least a portion of the digital phase error code to the gating signal may include selecting a version of the enable signal from a plurality of versions of the enable signal according to the digital phase error code. The generating the phase-adjusted feedback signal may include gating the reference clock signal with the gating signal to generate the phase-adjusted feedback signal. The most-significant portion of the digital phase error code may be the only portion of the digital phase error code converted to the gating signal. Generating the phase-adjusted feedback signal may include converting a least significant portion of the digital phase error code to the phase-adjusted feedback signal based on the gating signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. 
         FIG. 1  illustrates a functional block diagram of a conventional time-to-digital converter. 
         FIG. 2  illustrates a functional block diagram of a conventional time-to-digital converter based on a noise-shaping frequency-to-digital converter. 
         FIG. 3  illustrates a functional block diagram of a noise-shaping time-to-digital converter based on a digital-to-time converter. 
         FIG. 4  illustrates a functional block diagram of a noise-shaping time-to-digital converter with phase selection consistent with at least one embodiment of the invention. 
         FIG. 5  illustrates a functional block diagram of an exemplary loop filter of the time-to-digital converter of  FIG. 4  consistent with at least one embodiment of the invention. 
         FIG. 6  illustrates a functional block diagram of an exemplary digital-to-time converter of  FIG. 4  consistent with at least one embodiment of the invention. 
         FIG. 7  illustrates a functional block diagram of an exemplary digital-to-time converter of  FIG. 4  consistent with at least one embodiment of the invention. 
         FIG. 8  illustrates a functional block diagram of an exemplary edge-gating circuit of  FIG. 4  consistent with at least one embodiment of the invention. 
         FIG. 9  illustrates a functional block diagram of an exemplary edge-gating circuit of  FIG. 4  consistent with at least one embodiment of the invention. 
         FIG. 10  illustrates a functional block diagram of a noise-shaping time-to-digital converter with fine digital-to-time conversion consistent with at least one embodiment of the invention. 
         FIG. 11  illustrates a functional block diagram of a noise-shaping time-to-digital converter configured as a sub-ranging time-to-digital converter consistent with at least one embodiment of the invention. 
         FIG. 12  illustrates a functional block diagram of noise-shaping time-to-digital converter configured as the front-end of a digital phase-locked loop consistent with at least one embodiment of the invention. 
         FIG. 13  illustrates a functional block diagram of a sub-ranging time-to-digital converter configured as the front-end of a digital frequency-locked loop consistent with at least one embodiment of the invention. 
     
    
    
     The use of the same reference symbols in different drawings indicates similar or identical items. 
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , time-to-digital converter  100  generates a quantized estimate of instantaneous phase of input clock signal ck in  with respect to an edge of reference clock signal ck ref , and provides that quantized estimate as digital code D φ . The quantization noise and spurious tones in digital code D φ  impacts system performance, which may be unacceptable in exemplary applications (e.g., delta-sigma modulator based fractional-N phase-locked loops). 
     Referring to  FIG. 2 , an exemplary implementation of time-to-digital converter  100  includes first-order noise-shaping frequency-to-digital converter  202 . Frequency-to-digital converter  202  generates a quantized estimate of the frequency ratio between the frequency of input clock signal ck in  and a frequency of reference clock signal ck ref  and provides that quantized estimate of frequency ratio as digital code D f,frac . Accumulator  204  converts that frequency ratio into a phase ratio. As a result of the conversion, accumulator  204  eliminates the noise-shaping of the quantization noise in the quantized estimate of phase ratio of digital code D φ . 
     Referring to  FIG. 3 , noise-shaping time-to-digital converter  300  performs phase error integration prior to quantization to provide second-order noise shaping in the frequency domain and first-order noise shaping in the phase domain. However, conventional digital-to-time converter  308  generates feedback clock signal ck fb  using a phase selection technique that reduces gain accuracy due to manufacturing variations. 
     Referring to  FIG. 4 , noise-shaping time-to-digital converter  400  performs phase error integration prior to quantization to provide second-order noise shaping in the frequency domain and first-order noise shaping in the phase domain. Noise-shaping time-to-digital converter  400  include phase detector  302  which generates a phase error signal φ ε  based on the phase difference between input clock signal ck in  and feedback clock signal ck fb . Phase detector  302  may be any circuit configured to generate digital pulses having pulse widths modulated by the phase difference between two input signals (e.g., AND gate, SR latch, classic phase-frequency detector). Loop filter  304  integrates phase error signal φ ε  to generate an analog output signal A LF . In at least one embodiment, phase detector  302  encodes up/down pulse widths that are used to control switches  1306  and  1308  to selectively enable current sources  1302  and  1304  of loop filter  1300  of  FIG. 5 . Loop filter  1300  is configured as a time-to-voltage accumulator that integrates charge on feedback capacitor C n  to generate voltage V LF . Referring back to  FIG. 4 , in other embodiments, loop filter  304  includes a transconductor circuit and is configured as a time-to-current accumulator and/or includes switched resistors coupled to the virtual ground node. In at least one embodiment, loop filter  304  includes a time-to-voltage sample-and-hold circuit having a sample node that is sampled, e.g., by a switched-capacitor integrator and that resets the node after each sample. Analog-to-digital converter  306  quantizes analog output signal A LF  to generate digital code D φ . Analog-to-digital converter  306  may include voltage comparators, current comparators, common analog-to-digital converter circuits, voltage-controlled oscillator-based quantizers or current-controlled oscillator-based quantizers (which also provide the integrator functionality) or other suitable circuits. 
     Still referring to  FIG. 4 , digital-to-time converter  408  and edge gating circuit  410  generate feedback clock signal ck fb  using a phase-selection technique that precisely converts the least-significant bit of digital code D φ  to reference clock signal period T ref . Control signal enable indicates a start and a stop of an evaluation interval. Control signal enable is a periodic signal which may have the periodicity of input clock signal ck in  and an edge synchronous to an edge of reference clock signal ck ref . Control signal enable triggers digital-to-time converter to start evaluating a time interval and is provided based on the application, as described further below. When control signal enable is active, digital-to-time converter  408  counts the number of clock edges indicated by digital code D φ  before asserting gating signal gate. After asserting gating signal gate, reference clock signal ck ref  travels through a predetermined delay path, which is the same delay path for all values of digital code D φ , thereby reducing or eliminating any dependence of the gain and linearity of digital-to-time converter  400  on manufacturing variations and the value of digital code D φ . In other embodiments, time-to-digital converter  400  may realize higher orders of phase-domain noise-shaping. 
     Referring to  FIGS. 4 and 6 , in at least one embodiment, digital-to-time converter  408  implements a coarse conversion using a single bit to generate gating signal gate as an assertion signal. The difference in delay between two versions of control signal enable, e.g., the difference in delay between enable signal g 0  and delayed enable signal g 1 , is approximately reference clock signal period T ref . To update feedback signal ck fb , digital code D φ  selects between enable signal g 0  and delayed enable signal g 1  based on whether input clock signal ck in  is early or late as compared to feedback clock signal ck fb . Referring to  FIGS. 4 and 7 , rather than generate gating signal gate as a gate assertion signal, digital-to-time converter  408  also includes state element  1006  and logic device  1008  to generate a pulse for gating signal gate to be a window signal. In other embodiments, digital-to-time converter  408  of  FIG. 6  and digital-to-time converter  408  of  FIG. 7  each include additional state elements coupled in series with state element  902  to generate delayed enable signal g 1  having a greater delay with respect to enable signal g 0  where the least-significant bit is associated with a larger time step. In addition, select circuit  904  may have a greater width of multiple bits for a greater digital-to-time conversion range while maintaining the least-significant bit as corresponding to reference clock signal period T ref . 
     Referring to  FIG. 8 , edge-gating circuit  410  uses one or more state elements to generate a gated clock signal when gating signal gate is an assertion signal (e.g., generated by digital-to-time converter  408  of  FIG. 6 ). Edge-gating circuit  410  of  FIG. 8  asserts gated clock signal ck gate  according to a level of gating signal gate following a rising edge of reference clock ck ref . Referring to  FIGS. 7 and 9 , edge gating circuit  410  uses combinatorial logic to generate gated clock signal ck gate  when gating signal gate is a window signal (e.g., generated by  408  of  FIG. 7 ) by windowing a pulse of the reference clock ck ref  to generate gated clock signal ck gate  having a width of one pulse of reference clock ck ref . By using digital code D φ  as a select signal in the generation of feedback signal ck fb , rather than as feedback signal ck fb  itself, the effect of device mismatches and data dependencies within the feedback path of time-to-digital converter  400  of  FIG. 4  and associated gain inaccuracy and non-linearity of feedback signal ck fb  are reduced or eliminated. 
     In at least one embodiment, a noise-shaping time-to-digital converter further reduces quantization noise below the resolution of reference clock signal period T ref . Referring to  FIG. 10 , time-to-digital converter  500  includes digital-to-time converter  508  configured as a sub-ranging or fine digital-to-time converter responsive to least-significant bits (e.g., fine bits D φf ) of digital code D φ . Digital-to-time converter  508  linearly delays gated clock signal ck gate  according to fine digital code D φf  and with a full-scale range of reference clock signal period T ref . Digital-to-time converter  510  and edge-gating circuit  512  are responsive to the most-significant bits (e.g., coarse bits D φc ) of digital code D φ . The gain of fine digital-to-time converter  508  is derived from reference clock signal ck ref . By providing the output of edge-gating circuit  512  to digital-to-time converter  508 , rather than as the feedback signal, digital-to-time converter  508  of  FIG. 5  further reduces quantization noise. 
     Referring to  FIG. 11 , time-to-digital converter  600  includes an exemplary coarse time-to-digital converter that determines the average frequency of the input clock and information regarding instantaneous frequency (i.e. fine resolution in time). An exemplary coarse time-to-digital converter includes a free running counter having a range greater than the interval being converted (e.g., greater by at least an order of magnitude). For example, counter  608  is configured to overflow without reset and, thus, is configured as a phase accumulator achieving first order noise-shaping of the quantization noise in the frequency domain. If reference clock signal ck ref  is asynchronous to input clock signal ck in , then sampling the coarse time-to-digital converter output D count  by register  610  results in quantization noise in the phase domain. That quantization noise is determined by the least significant bit of counter  608 , which is defined by reference clock signal period T ref . Accordingly, time-to-digital converter  600  includes noise-shaping time-to-digital converter  400  configured as a fine range, i.e., sub-ranging, time-to-digital converter. State element  604  synchronizes input clock signal ck in  with reference clock signal ck ref  and provides control signal enable to noise-shaping time-to-digital converter  400 . Control signal enable indicates start and stop evaluation of input clock signal ck in . Noise-shaping time-to-digital converter  400  resamples input clock signal ck in  using reference clock signal ck ref . 
     Noise-shaping time-to-digital converter  400  and counter  608  of time-to-digital converter  600  have common quantization noise since they sample using the same reference clock signal. Noise-shaping time-to-digital converter  400  accumulates phase residues at sample time boundaries and generates a fine digital code D φf , which has the same quantization noise as the least-significant bit of coarse digital code D φc . Since time-to-digital converter  400  and counter  608  have gains defined by T ref  subtraction of fine digital code D φf  from coarse digital code D φc  generates digital code D φ  having residual noise-shaped quantization noise. Finite state machine  614  samples digital code D φ , which effectively digitally filters D φ  to generate a lower noise version and higher resolution (e.g., larger bus width) signal D filt . Since clock-to-output delay of state element  604  and state element  606  of control signal enable and clock signal ck s , respectively, is the same, only a fixed phase offset is present in those signals. Additional accuracy may be achieved by replacing noise-shaping time-to-digital converter  400  with noise-shaping time-to-digital converter  500  of  FIG. 10  in sub-ranging noise-shaping time-to-digital converter  600  of  FIG. 11 . Thus, time-to-digital converter  600  combines features of a frequency counter-based time-to-digital converter (which has greater range and determines an integer frequency ratio) and fine time-to-digital converter (which has lower noise and determines a fractional frequency ratio). 
     In at least one embodiment, noise-shaping time-to-digital converter  400  of  FIG. 4  is configured as a replacement for the front-end of an analog phase-locked loop to form digital phase-locked loop  700  of  FIG. 12 . Time-to-digital converter  400  converts input clock signal ck in  to digital code D φ  using output clock ck DCO  as the reference clock signal. Digital code D φ  indicates the phase difference between clock signal ck in  and output clock ck DCO . Digital loop filter  704  integrates digital code D φ  to generate digital frequency control signal D filt . Digitally controlled oscillator  706  generates output clock ck DCO  according to digital frequency control signal D filt . Digital-to-frequency converter  708  converts a predetermined digital frequency code D f  to control signal enable, which is a clock signal having the predetermined frequency using output clock ck DCO  as the analog reference signal. Additional precision may be achieved by replacing time-to-digital converter  400  with time-to-digital converter  500  of  FIG. 10  in digital frequency-locked loop  700  of  FIG. 12 . 
     Referring to  FIG. 13 , in at least one embodiment, sub-ranging time-to-digital converter  600  of  FIG. 11  is included as sub-ranging time-to-digital converter  802  as a digital equivalent of a frequency-detector/charge pump that would otherwise be included as analog-front end of frequency-locked loop  800  of  FIG. 13 . Sub-ranging time-to-digital converter  802 , which may include filter  804 , generates digital code D φ  having residual noise-shaped quantization noise. Filter  804  digitally differentiates D φ  to generate a digital frequency code D f  with an additional order of noise shaping in the frequency domain. Summing node  806  generates a digital frequency error code D fε  by combining digital frequency code D f  with target frequency code D f,target . Digital loop filter  808  low pass filters digital frequency error code D fε  and drives a digitally controlled oscillator  810  with control code D ctrl  to generate output clock signal ck DCO  having a target frequency. 
     Thus, noise-shaping time-to-digital conversion techniques that have greater range and increased resolution as compared to other time-to-digital converters have been disclosed. While circuits and physical structures have been generally presumed in describing embodiments of the invention, it is well recognized that in modern semiconductor design and fabrication, physical structures and circuits may be embodied in computer-readable descriptive form suitable for use in subsequent design, simulation, test or fabrication stages. Structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component. Various embodiments of the invention are contemplated to include circuits, systems of circuits, related methods, and tangible computer-readable medium having encodings thereon (e.g., VHSIC Hardware Description Language (VHDL), Verilog, GDSII data, Electronic Design Interchange Format (EDIF), and/or Gerber file) of such circuits, systems, and methods, all as described herein, and as defined in the appended claims. 
     The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. Variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.