Abstract:
A semiconductor memory device is provided, having a circuit for latching data on a data line of a data output path. A related data latching method for the semiconductor memory device is also provided. The synchronous semiconductor memory device includes sense amplifiers for sensing the data of the memory cells, a data output register for latching the data of the memory cells, data lines for connecting the sense amplifiers and the data output register to transmit the sensed data to the data output register, and a data line control circuit for generating a data latch signal that releases the latching of the data on the data line in response to a first rising edge of the clock signal synchronized with a read command, and latches the data on the data line in response to a second rising edge of the clock signal.

Description:
This application relies for priority upon Korean Patent Application No. 99-25818, filed on Jun. 30, 1999, the contents of which are herein incorporated by reference in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having a circuit for latching data on a data line of a data output path, and a related data latching method for the semiconductor memory device. 
     In the read operation of general semiconductor memory devices, e.g., synchronous DRAMs, row addresses and column addresses are specified to access a given memory cell. Column address transition is detected by a circuit that provides timing pulses for enabling a data output register after a predetermined delay time. The delay time is necessary for precharging, address decoding, and a sensing or driving operation, and results in it taking a long time to perform a read command. The data latched by the data output register is data of a memory cell selected from a memory cell array block. 
     A data output path includes sense-amplifiers positioned at the ends of a memory cell array for amplifying the data read from a memory cell. The data amplified by the sense-amplifiers is transmitted to the data output register through a data line. The data output register is positioned near input/output pads of a chip. Since the sense-amplifiers and the data output register are spaced apart from each other, a transmission delay is caused between the valid window of the data read from the memory cell and the time at which the data is latched by the data output register. 
     Newly read data must be latched after the data previously latched from the memory cell array is stored in the data output register. However, if the data is read later than the timing pulse that enables the data output register and is loaded on the data line with a transmission delay, then the read data may be lost. In other words, since the data output register cannot latch the data during the valid window of the previously read data, the previous data is lost. 
     The loss of the previous data causes malfunctions of synchronous DRAMs. Therefore, when latching the data on a data line of a data output path leading to the data output register of a synchronous DRAM, the data output register must latch the data without losing of previous data. 
     SUMMARY OF THE INVENTION 
     To solve the above problems, it is an objective of the present invention to provide a semiconductor memory device having a circuit for latching data from a data line of a data output path. 
     It is another objective of the present invention to provide a method for latching data by a data output register of the semiconductor memory device. 
     Accordingly, to achieve the first objective, a synchronous semiconductor memory device is provided operating in synchronization with a clock signal, The synchronous semiconductor memory device comprises a memory cell block having a plurality of memory cells for outputting data from a selected memory cell to a data line, a data line control circuit for generating a data latch signal for releasing the latching of the data onto the data line in response to a first rising edge of the clock signal, synchronized with a read command, and latching the data on the data line in response to a second rising edge of the clock signal. The data latch signal is preferably activated within the valid window of the data from the selected memory cell. 
     A synchronous semiconductor memory device operating in synchronization with a clock signal is also provide that comprises a memory cell block having a plurality of memory cells for outputting data from a selected memory cell to a data line, sense amplifiers for sensing the data from the memory cells, a data output register for latching the data from the memory cells, data lines for connecting the sense amplifiers and the data output register for transmitting the sensed data to the data output register, and a data line control circuit for generating a data latch signal for releasing the latching of the data on the data line in response to a first rising edge of the clock signal, synchronized with a read command, and latching the data on the data line in response to a second rising edge of the clock signal. 
     The data line control circuit may itself comprise a first data line controller for generating a first data line control signal in response to a column select disable signal, a second data line controller for generating a second data line control signal in response to the clock signal and a column address, and a third data line controller activated by the second line control signal and deactivated by the first data line control signal, for generating the data latch signal having a predetermined time interval. The first data line control signal preferably operates to latch the data on the data line and disable the selection of a bit line of the memory cell, and the second data line control signal preferably operates to release the latching of the data on the data line and select a bit line of the memory cell. 
     The data line control circuit may also comprise a first data line controller for generating a first data line control signal in response to the clock signal and a column address, a second data line controller for generating a second data line control signal in response to the clock signal and the column address, and a third data line controller activated by the second line control signal and deactivated by the first data line control signal, for generating the data latch signal having a predetermined time interval. The first data line control signal preferably operates to latch the data on the data line, the column address is latched at the first falling edge of the clock signal and the first data line control signal is generated at the second rising edge of the clock, and the second data line control signal operates to release the latching of the data on the data line. 
     The data latch signal is preferably activated within the valid window of the memory cell data. 
     To achieve the second objective, a method is provided for latching data on a data line in a synchronous semiconductor memory device operating in synchronization with a clock signal, in which the data of a memory cell selected from a memory cell block having a plurality of memory cells is output to a data line. The method comprises generating the clock signal, activating a column select signal for selecting a bit line of the selected memory cell in accordance with a read command synchronized with the first rising edge of the clock signal, loading the bit line data of the selected memory cell on the data line in response to the column select signal, releasing latching of the data on the data line in response to the rising edge of the first clock, deactivating the column select signal in response to the second rising edge of the clock signal, and latching the data on the data line in response to the second rising edge of the clock signal. 
     According to the present invention, since a data latch signal is activated during the valid window of the data of the data line, the data of the data line of the data output path that leads to the data output register can be latched without a loss of data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objectives and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: 
     FIG. 1 is a block diagram of a semiconductor memory device according to a preferred embodiment of the present invention; 
     FIG. 2 is a detailed circuit diagram of the first data line controller shown in FIG. 1; 
     FIG. 3 is a detailed circuit diagram of the second data line controller shown in FIG. 1; 
     FIG. 4 is a detailed circuit diagram of the third data line controller shown in FIG. 1; 
     FIG. 5 is a detailed circuit diagram of the first data output register shown in FIG. 1; 
     FIG. 6 is a detailed circuit diagram of a circuit for generating a second data latch signal shown in FIG. 1; 
     FIG.7 is a detailed circuit diagram of the second data output register shown in FIG. 1; 
     FIG. 8 is a timing diagram illustrating the operation of the semiconductor memory device shown in FIG. 1; 
     FIG. 9 is a detailed circuit diagram illustrating an example of an alternative data line control circuit to that shown in FIG. 1 according to a second preferred embodiment of the present invention; 
     FIG. 10 is a detailed circuit diagram of the first data line controller shown in FIG. 9; 
     FIG. 11 is a diagram illustrating a comparative example of the data line control circuits shown in FIGS. 1 and 9; and 
     FIG. 12 is a timing diagram illustrating the operation of a semiconductor memory device having the data line control circuit shown in FIG.  11 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     To fully understand the invention, it&#39;s operational advantages, and the objectives accomplished by the invention, preferred embodiments of the present invention will be described below with reference to the accompanying drawings. The same reference numerals in the respective drawings denote the same elements. 
     In a synchronous DRAM operating in synchronization with a clock signal, the operation of CAS latency  2 , in which a data burst of 4 bits from 4 memory cells is output when 2 clock cycles elapse after the application of the read command, will now be described. 
     First Preferred Embodiment 
     FIG. 1 illustrates a semiconductor memory device according to a first preferred embodiment of the present invention, in which the valid data window of a data line is established using a data latch signal (FRP). Referring to FIG. 1, a semiconductor memory device  2  includes a clock buffer  10 , a clock delay circuit  12 , an address buffer  14 , a row decoder  16 , a column decoder  18 , a column select control circuit  20 , a bit line sense amplifier  24 , and a data line sense amplifier  28 . 
     The clock buffer  10  receives an external clock signal XCLK and generates an internal clock signal ICLK i  acting as a reference clock signal for an internal circuit in the semiconductor memory device. The clock delay circuit  12  generates a delayed clock signal ICLK j , which is delayed by a predetermined amount of time with respect to the internal clock signal ICLK i . 
     The address buffer  14  receives address signals XA i , and classifies the same into row addresses RA i  and column addresses CA i  in accordance with a row address strobe signal /RAS (not shown) and a column address strobe signal /CAS (not shown). The row decoder  16  decodes the row address RA i  to select a word line (not shown) of a memory cell in a memory cell array block  22 . The column select (CSL) control circuit  20  generates a column select enable signal CSLE, which instructs the selection of a bit line (not shown) of the memory cell in the memory cell array block  22 . The CSL control circuit  20  also generates a column select disable signal CSLD, which instructs the release of the selection of the bit line in response to the internal clock signal ICLK i , the delayed clock signal ICLK j  and the column addresses CA i . 
     The column decoder  18  decodes the column addresses CA i  and generates a column select signal CSL i  for selecting a bit line of the memory cell in the memory cell array block  22  in response to the column select enable signal CSLE and the column select disable signal CSLD. 
     The bit line sense amplifier  24  senses data of memory cells in the memory cell array block  22 . The data line sense amplifier  28  senses data of a local data line  26  on which data sensed from the bit line corresponding to the column select signal CSL i  is loaded. 
     The semiconductor memory device  2  further includes a data line control circuit  30 , a first data output register  40 , a second data output register  42 , and an output buffer  44 . The data line control circuit  30  provides a first data latch signal FRP for latching the data on a first data line FDL i . The first data output register  40  transmits the data on the first data line FDL i  to a second data line SDL i  in response to the first data latch signal FRP. The second data output register  42  transmits the data on the second data line SDL i  to the last data line LDL i . The output buffer  44  outputs the data of the last data line LDL i  to a data output pad DQ i  in response to an output clock signal OCLK. 
     The data line control circuit  30  includes a first data line controller  32 , a second data line controller  34 , and a third data line controller  36 . The first data line controller  32  generates a first data line control signal DLC 1  in response to the column select disable signal CSLD. The second data line controller  34  generates a second data line control signal DLC 2  in response to the column addresses CA i , the internal clock signal ICLK i  and a write enable signal WE. The third data line controller  36  generates the first data latch signal FRP in response to the first data line control signal DLC 1  and the second data line control signal DLC 2 . 
     FIG. 2 is a detailed circuit diagram of the first data line controller  32  shown in FIG.  1 . Referring to FIG. 2, the first data line controller  32  generates the first data line control signal DLC 1  as a logic low (“L”) level signal in response to a logic high (“H”) level column select disable signal CSLD and generates the first data line control signal DLC 1  as an “H” level signal in response to an “L” level column select disable signal CSLD. 
     FIG. 3 is a detailed circuit diagram of the second data line controller  34  shown in FIG.  1 . Referring to FIG. 3, the second data line controller  34  generates the second data line control signal DLC 2  in response to the column addresses CA, the inverted column addresses /CA i , a write enable signal WE, and the internal clock signal ICLK i . The write enable signal WE is enabled during a write operation period in accordance with a write command. A first node N 1 , which is the output of a 2-input NOR gate G 2  goes to an “L” level when one or more of the column address CA i  or inverted column address /CA i  go to an “H” level. A second node N 2 , which is the output of a 2-input NOR gate G 4 , goes to an “H” level in response to the “L” level of the first node N 1  and an “L” level of the write enable signal WE. 
     Therefore, in the second data line controller  34 , a third node N 3 , which is the output of a 2-input NAND gate G 6  goes to an “L” level at the rising edge of the internal clock signal ICLK i  in a state when the second node N 2  is at the “H” level. The “L” level of the third node N 3  activates the second data line control signal DLC 2  to the “H” level through an inverter INV 1 . On the other hand, when the second node N 2  is at an “H” level, the second data line controller  34  deactivates the second data line control signal DLC 2  to an “L” level at the falling edge of the internal clock signal ICLK i . 
     FIG. 4 is a detailed circuit diagram of the third data line controller  36  shown in FIG.  1 . Referring to FIG. 4, the third data line controller  36  generates the first data latch signal FRP in response to the first and second data line control signals DLC 1  and DLC 2 . While the first data line control signal DLC 1  is at an “H” level, an NMOS transistor TN 1  is turned on in response to an “H” level of the second data line control signal DLC 2  so that a fifth node N 5  goes to an “L” level. When the fifth node N 5  goes to the “L” level, it activates the first data latch signal FRP to an “H” level, while maintaining its voltage level with a latch LAT 1 . 
     Then, when the second data line control signal DLC 2  goes to an “L” level, the NMOS transistor TN 1  is turned off but the voltage level of the fifth node N 5  of the “L” level is maintained by the latch LAT 1 . In this case, a PMOS transistor TP 1  is turned on in response to the “L” level of the second data line control signal DLC 2  so that a fourth node N 4  goes to an “H” level. However, since a PMOS transistor TP 2  is turned off by the “H” level of the first data line control signal DLC 1 , the “H” level at the node N 4  is not transmitted to the fifth node N 5 . 
     Subsequently, in the third data line controller  36 , if the first data line control signal DLC 1  is changed into an “L” level, the PMOS transistor TP 2  is turned on so that the “H” level of the fourth node N 4  is transmitted to the fifth node N 5 . The “H” level of the fifth node N 5  then turns the first data latch signal FRP into an “L” level via the latch LAT 1 . 
     FIG. 5 is a detailed circuit diagram of the first data output register  40  shown in FIG.  1 . Referring to FIG. 5, the first data output register  40  transmits the data on the first data line FDL i  to the second data line SDL i  in response to the first data latch signal FRP. While the first data latch signal FRP is at the “H” level, a seventh node N 7 , which is the output of a 2-input NAND gate G 12 , goes to an “L” level in response to an “H” level of the data on the first data line FDL i . When the seventh node N 7  changes to the “L” level, an eighth node N 8  is activated to the “H” level. Then, an NMOS transistor TN 10  is turned on in response to the “H” level of the eighth node N 8  so that a ninth node N 9  goes to an “L” level. The “L” level of the ninth node N 9  is then transmitted to the second data line SDL i  by a latch LAT 2  so that the data on the second data line SDL i  rises to the “H” level. 
     Also, in the first data output register  40 , while the first data latch signal FRP is at the “H” level, a sixth node N 6 , which is the output of a 2-input NAND gate G 10  goes to an “L” level in response to the “L” level of the first data line. A PMOS transistor TP 10  is then turned on in response to the “L” level of the sixth node N 6  so that the ninth node N 9  goes to an “H” level. The “H” level of the ninth node N 9  is then transmitted to the second data line SDL i  by the latch LAT 2  so that the data on the second data line SDL i  falls to an “L” level. As a result, the first data output register  40  transmits the data on the first data line FDL i  to the second data line SDL i  while the first latch signal FRP is at an “H” level. 
     FIG. 6 is a diagram of a circuit for generating a second data latch signal SRP for controlling the operation of the second data output register  42  shown in FIG.  1 . Referring to FIG. 6, a transistor TN 12  responsive to a CAS latency mode signal CL of the “L” level is turned on so that a tenth node N 10  goes to an “L” level. When the tenth node N 10  goes to the “L” level, it sets the second data latch signal SRP to an “H” level through inverters INV 10 , INV 11  and INV 12  in three stages. When the second data latch signal SRP is set to an “H” level, the second data output register  42 , to be described later, transmits the data on the second data line SDL i  to the last data line LDL i . 
     In this embodiment, in order to perform a CAS latency  2  operation in which cell data is output after 2 clock cycles elapse after application of a read command, a mode set register MSR is set to operate the CAS latency  2  and the CAS latency mode signal CL is set to an “L” level. If the CAS latency is set to  3 , the CAS latency mode signal CL is set to an “H” level to thus turn on a transfer gate TG 1  so that the second data latch signal SRP is generated as pulses in accordance with the internal clock signal ICLK i . 
     FIG. 7 is a detailed diagram of the second data output register  42  shown in FIG.  1 . Referring to FIG. 7, the second data output register  42  transmits the data on the second data line SDL i  to the last data line LDL i  through a transfer gate TG 2  responsive to the second data latch signal SRP going to an “H” level. 
     Referring back to FIG. 1, the data on the last data line LDL i  is then output to a data output pad DQ i  through the output buffer  44 , which is responsive to the output clock signal OCLK. 
     The operation of the semiconductor memory device  2  having the data line control circuit  30  according to the present invention will now be described with reference to FIG.  8 . 
     First, internal clock signals ICLK i  are sequentially generated in accordance with an external clock signal (XCLK of FIG.  1 ), which is preferably externally applied. A read command READ is then received in a semiconductor memory device ( 2  of FIG. 1) in synchronization with the first rising edge of the internal clock signal ICLK i . A column select enable signal CSLE (a) having a predetermined pulse width is then generated in a CSL control circuit ( 20  of FIG. 1) in response to the first rising edge of the internal clock signal ICLK i , and the column select enable signal CSLE is continuously generated in accordance with the internal clock signal ICLK i . Also, in a second data line controller ( 34  of FIG.  3 ), the second data line control signal DLC 2  rises to the “H” level in response to the first rising edge of the internal clock signal ICLK i  (b). The column select signal CSL i  (c) is then activated to the “H” level in response to the rising edge of the column select enable signal CSLE. 
     Thereafter, a column select disable signal CSLD (d) having a predetermined pulse width is generated in the CSL control circuit ( 20  of FIG. 1) in response to the second rising edge of the internal clock signal ICLK i , and the column select disable signal is continuously generated in accordance with the internal clock signal ICLK i . The column select signal CSL i  is deactivated to an “L” level (e) and the first data line control signal DLC 1  in the first data line controller ( 32  of FIG. 2) falls to the “L” level (f) in response to the “H” level of the column select disable signal CSLD. 
     Bit line data of a memory cell corresponding to the column select signal CSL i  is loaded on the first data line FDL i  in response to the “H” level of the column select signal CSL i  (g) and (h). In the third data line controller ( 36  of FIG.  4 ), the first data latch signal FRP rises to the “H” level (i) in response to the “H” level of the second data line control signal DLC 2 , and the first data latch signal FRP falls to an “L” level (j) in response to the “L” level of the first data line control signal DLC 1 . Thus, the first data latch signal FRP has a pulse width of t 1 . The above-described operational sequence (a) through (j) are repeated four times in accordance with the internal clock signal ICLK i , thereby continuously generating four first data latch signals, i.e., 4 FRPs, which satisfies the assumed burst length 4 rule. 
     In the first data output register ( 40  of FIG.  5 ), the data on the first data line FDL i  is transmitted to the second data line SDL i  (k) in response to the “H” level of the first data latch signal FRP. The data on the first data line FDL i , corresponding to the continuously generated first data latch signals FRPs, is transmitted to the second data line SDL i  ( 1 ), (m), and (n) in response to the rising edge of the continuously generated first data latch signals FRPs of an “H” level. 
     Finally, the data on the second data line SDL i , corresponding to the output clock signal OCLK, is output to the output pad DQ i  in response to the “H” level of the respective output clock signals OCLKs. Since the first effective data on the output pad DQ i  exists after 2 clock cycles of the clock synchronized with the read command READ, the assumed CAS latency 2 rule is satisfied. Also, since three pieces of data are continuously output after the first data is output to the output pad DQ i , the assumed burst length 4 rule is also satisfied. 
     As described above, according to this first preferred embodiment, since the first data latch signal FRP is activated within the valid window of data on the first data line FDL i , the data on the first data line FDL i  of the data output path, which leads to the data output registers ( 40  and  42  of FIG.  1 ), can be latched without data loss. 
     Second Preferred Embodiment 
     FIG. 9 is a detailed circuit diagram illustrating an example of an alternative data line control circuit  1  to the data line control circuit  30  shown in FIG.  1 . Referring to FIG. 9, the operation of the alternative data line control circuit  130  is substantially the same as that of the data line control circuit  30  shown in FIG. 1, and includes a first data line controller  132 , a second data line controller  34  and a third data line controller  36 . 
     The second and third data line controllers  34  and  36  correspond to those in FIG.  1 . The first data line controller  132  generates a first data line control signal DLC i  in response to column addresses CA i  and the internal clock signal ICLK i , just like the second data line controller  34 . In contrast, the first data line controller  32  shown in FIG. 1 generates a first data line control signal DLC 1  in response to a column select disable signal CSLD. The first data line controller  132  is shown in detail in FIG.  10 . 
     Referring to FIG. 10, in the first data line controller  132 , a twentieth node N 20  which is the output of a 2-input NOR gate G 20  goes to an “L” level in response to any column address CA i  or complementary column address /CA i , and generates a column select signal CSL i  for selecting a bit line of a memory cell. The “L” level of the twentieth node N 20  is transmitted to a twenty-first node N 21  through a transfer gate TG 10  responsive to the “L” level of the internal clock signal ICLK i . The “L” level of the twenty-first node N 21  maintains its voltage level by a latch LAT 5  and activates a twenty-second node N 22  to an “H” level. In this case, a 2-input NAND gate G 22  sets its output, i.e., the first data line control signal DLC 1 , to an “H” level in response to a falling edge of the internal clock signal ICLK i . 
     Thereafter, the transfer gate TG 10  is turned off in response to a rising edge of the internal clock signal ICLK i . However, the “L” level of the twenty-first node N 21  and the “H” level of the twenty-second node N 22  maintain their voltage levels through the latch LAT 5 . Thus, the first data line control signal DLC i , which is the output of the 2-input NAND gate G 22 , is activated to an “L” level in response to the “H” level of the twenty-second node N 22  and the rising edge of the internal clock signal ICLK i . 
     Therefore, the first data line controller  132  latches a column address at a first falling edge of the internal clock signal ICLK i , and generates the first data line control signal DLC 1 , which is at an “L” level, at the second rising edge of the internal clock signal ICLK i . Thus, the first data line control signal DLC 1  has a predetermined pulse width of an “L” level during the second period of the internal clock signal ICLK i , as shown in FIG. 8, and is synchronously generated in accordance with the internal clock signal ICLK i . Therefore, the first data line control signal DLC 1  generated in the first data line controller  132  is produced with the same timing as that shown in FIG.  8 . 
     In other words, when the alternative first data line controller  132  of the second preferred embodiment replaces the first data line controller  32  shown in FIG. 1, the first data latch signal FRP is activated within the valid window of the data on the first data line FDL i , just as in the first preferred embodiment. Therefore, the data on the first data line FDL i  of the data output path led to the data output registers ( 40  and  42  of FIG. 1) can be latched without data loss. 
     COMPARATIVE EXAMPLE 
     FIG. 11 is a diagram illustrating a comparative example of the data line control circuits  30  and  130  shown in FIGS. 1 and 9. Referring to FIG. 11, the data line controller  230  according to this comparative example corresponds to the second data line controller  34  shown in FIG.  3 . 
     As described in FIG. 3, in the second data line controller  34 , the second data line control signal DLC 2  rises to an “H” level in response to the rising edge of the internal clock signal ICLK i  with respect to the write enable signal WE of an “L” level and a column address CA i  of an “H” level. Also, the second data line control signal DLC 2  falls to an “L” level in response to the falling edge of the internal clock signal ICLK i . In this comparative example, the second data line control signal DLC 2  corresponds to the data latch signal FRP. Therefore, the data latch signal FRP is produced as pulses having an “H” level period during cycles of the internal clock signal ICLK i . The operation of enabling the data output register using the data latch signal will be described with reference to FIGS. 1 and 12. 
     Referring to FIG. 12, the operations (a) through (e) are performed in the same manner as that shown in FIG.  8 . The data latch signal FRP is the same as the second data line control signal DLC 2  shown in FIG.  8 . The data of a memory cell in the memory cell array corresponding to the column select signal CSL i  is loaded on the first data line FDL i . For example, if the memory cell corresponding to the first column select signal CSL 0  is far from the first data line FDL i , the data of the memory cell corresponding to the first pulse of the column select signal CSL 0  is loaded on the first data line FDL i  after a delay time with respect to the activation of the first column select signal CSL 0  to the “H” level (o). 
     The data of the memory cells corresponding to the second through fourth pulses of the column select signal CSL 1  through CSL 3  are loaded on the first data line FDL i  with the delay time in accordance with the corresponding column select signals CSL i  through CSL 3  (p), (q), and (r). Thereafter, the first data output register ( 40  of FIG. 1) latches the data on the first data line FDL i  in response to the first data latch signal FRP. 
     Since the first data latch signal FRP is activated and then deactivated before the first memory cell data is loaded on the first data line FDL i , the data of the memory cell corresponding to the first pulse of the column select signal CSL 0  is not loaded on the first data line FDL i . The first data output register ( 40  of FIG. 1) latches invalid data (s) and the data FDL 0  of the memory cell corresponding to the first column select signal CSL 0  is lost. The invalid data is transmitted to the second data line SDL i , which is the output of the first data output register ( 40  of FIG.  1 ). The invalid data on the second data line SDL i  is then output to the output pad DQ i  in response to the output clock signal OCLK through the second output register ( 42  of FIG. 1) and the output buffer ( 44  of FIG. 1) (w). 
     Since the data latch signal FRP of the comparative example is not activated within the valid data window of the memory cell data on the first data line FDL 0 , the memory cell data on the first data line FDL 0  is lost. In contrast, the data latch signals of the first and second preferred embodiments are activated within the valid window of the memory cell data, the data of the memory cell on the first data line FDL i  can be latched in a stable manner without data loss. 
     Also, the memory cell data FDL 1  through FDL 3  corresponding to the second through fourth pulses of the column select signal CSL 1  through CSL 3  are transmitted to the second data line SDL i  (t), (u), and (v) in accordance with the activation of the data latch signal FRP, and are output to the output pad DQ i  in response to the output clock signal OCLK (x), (y), and (z). However, if the memory cell data FDL 1  through FDL 3 , corresponding to the second through fourth pulses of the column select signals CSL 1  through CSL 3 , are also loaded on the first data line FDL i  after a rather long delay time, like the memory cell data FDL 0  corresponding to the first column pulse of the select signal CSL 0 , the data latch signal FRP is not activated within the valid window of the memory cell data FDL 1  through FDL 3  so that the memory cell data FDL 1  through FDL 3  may also be lost. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.