Abstract:
In an SOI integrated circuit employing shallow trench isolation, the walls of the transistor active area have a nitridized oxide layer grown on them, thereby preventing the diffusion of dopants out of the transistor body and preventing a shift in threshold voltage.

Description:
FIELD OF THE INVENTION 
     The field of the invention is integrated circuit fabrication, in particular fabrication on SOI wafers. 
     BACKGROUND OF THE INVENTION 
     Shallow trench isolation (STI) has become standard in submicron integrated circuit processing, including silicon on insulator (SOI) processing, because of its size benefits. 
     A problem in small size devices, especially narrow devices (less than about 500 nm) is that of maintaining a stable threshold voltage. 
     SUMMARY OF THE INVENTION 
     The invention relates to an SOI integrated circuit employing shallow trench isolation, in which the walls of the transistor active area have a nitridized oxide layer grown on them, thereby preventing the diffusion of dopants out of the transistor body. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows in perspective an SOI transistor after STI etching. 
     FIG. 2 shows the same area after a nitriding step according to the invention. 
     FIG. 3 shows a cross section of a transistor along line A—A in FIG.  2 . 
     FIG. 4 shows a cross section along line B—B in FIG.  2 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     It has been found that a cause of instability of narrow submicron transistors is that V t  can be affected by various causes that cause it to be off spec. 
     One such cause has been found to be the diffusion of a dopant, such as Boron, out of the transistor body and into adjacent oxide, either into the oxide used to fill an STI trench or into the buried oxide (BOX) below the silicon device layer that contains the transistor bodies. 
     Referring to FIG. 1, there is shown in perspective a device layer  30  above BOX  20  that is, in turn, above substrate  10 , with shallow trench  50  having been etched to isolate a slab of the device layer that will contain a transistor. Top layer  60  (conventional pad oxide pad nitride) protects the silicon during this operation. Formation of this protective layer, threshold implants and the like will be referred to as “preparing the substrate” for simplicity in the claims. Lines denoted with numerals  32  and  34  show the corners where the trench sidewall meets the trench bottom. 
     FIG. 2 shows the same area after the next step of growing a nitridized oxide layer  112  in the vertical trench walls. Lines  32  and  34  have now become  32 ′ and  34 ′ as the previous corners have been covered by the nitridized oxide layer  112 . Illustratively, the layer of nitridized oxide is grown in an NO or N 2 O ambient at high temperature such as 1000° C. to 1100° C. At the silicon-oxide interface, there will be a high concentration of nitrogen atoms, so that diffusion blocking takes place even with very thin films. A nitride content in the range of about 5% to 15% of the total oxide has been found to be effective. 
     An additional benefit of the invention is that the nitride reduces interface states at the silicon-oxide interface in the transistor body significantly compared with a conventional process of growing a thin layer of thermal oxide. These interface states also can contribute to a shift in V t . 
     Yet another benefit of this process is that the nitridized oxide is resistant to hot phosphoric acid, which is conventionally used to strip nitride films in STI processing, so that the use of this invention does not interfere with other processing steps. 
     When the nitridized-oxide layer is greater in thickness than about 20 nm, nitrogen will diffuse underneath the silicon slab  110  and form a layer of nitridized oxide at the bottom silicon-oxide interface between silicon  110  and BOX  20 . For smaller geometries, the bottom interface will be affected with a film of less than 20 nm, since the distance over which the nitrogen must diffuse is smaller. This results in encapsulation of the silicon body and provides further resistance to dopant diffusion. The invention is not confined to SOI, however, and may be used in bulk silicon circuits as well. 
     Referring now to FIG. 3, there is shown in cross section the transistor after the addition of gate oxide  120  and gate  130 . This view is along the main axis of the transistor, the direction denoted by A—A in FIG. 2, with the source and drain in front of and behind the plane of the cross section. Body  110  has nitridized oxide  112  on either side and a layer of nitridized oxide  114  on the bottom. The trench is filled with oxide  60 , which is deposited and planarized before the formation of the gate. 
     Referring now to FIG. 4, there is shown another cross section along lines B—B in FIG. 2, showing source and drain  142 ,  144  and conventional gate sidewalls  132  on gate  130 . 
     While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.