Abstract:
The present invention relates to an integrated circuit package and method of manufacturing an integrated circuit package. In one aspect, the present invention relates to an integrated circuit package including a lead frame having a lead with an inner pad and an outer pad connected by a connection member, wherein a region of the inner pad and a region of the outer pad are separated by a channel extending through a width of the lead. Such an integrated circuit package further includes a semiconductor die electrically coupled with the inner pad of the lead, and an encapsulant material encapsulating at least a portion of said lead frame, wherein a portion of said outer pad is exposed. In another aspect, the present invention relates to a method including providing a matrix of lead frames, each of the lead frames having a lead, forming a channel extending through a width of the lead to create an inner pad, an outer pad and a connection member in the lead, electrically coupling a semiconductor die with the inner pad, and encapsulating at least a portion of the lead frame such that at least a portion of the outer pad is exposed.

Description:
FIELD OF THE INVENTION 
     The present invention relates to integrated circuit packaging technology, and more particularly, to lead frames, integrated circuit packages, and methods of manufacturing such lead frames and packages. 
     BACKGROUND OF THE INVENTION 
     A conventional lead frame may include a die attachment pad for accommodating a semiconductor die, as well as a number of leads connected to the semiconductor die. Such a conventional lead frame and semiconductor die may be packaged by being encapsulated within a plastic or resinous material. Various shapes and sizes of such packages exist. For example, U.S. Pat. No. 6,229,200 to Mclellan, entitled “Saw-Singulated Leadless Plastic Chip Carrier,” discloses a chip carrier having an encapsulation encapsulating a semiconductor die. In certain standard and conventional lead frames, the leads connected to the semiconductor die may be spaced somewhat far from the semiconductor die&#39;s bonding pads when the die is of a relatively small size compared to the lead frame. Therefore, in connection with certain packages, it may be advantageous to have a lead frame which includes a portion of a lead for attachment to the semiconductor die, and another portion of the lead for connection to an external device. 
     SUMMARY OF THE INVENTION 
     In one aspect, the invention features an integrated circuit package including a lead frame with a lead having an inner pad and an outer pad connected by a connection member, wherein a region of the inner pad and a region of the outer pad are separated by a channel extending through a width of the lead, a semiconductor die electrically coupled with the inner pad of the lead, and an encapsulant material encapsulating at least a portion of the lead frame, wherein a portion of the outer pad is exposed. 
     In another aspect, the invention features an integrated circuit package including a lead frame having a die attachment pad and a plurality of inwardly projecting leads, each of the leads having an inner pad and an outer pad, wherein a region of the inner pad and a region of the outer pad is separated by a channel extending through a width of the lead and connected by a connection member integral with the inner pad and the outer pad, the connection member having a thickness that is approximately half a thickness of the lead, a semiconductor die electrically coupled with the inner pad of the lead, and an encapsulant material encapsulating at least a portion of the lead frame, wherein a portion of the outer pad is exposed. 
     In yet another aspect, the invention features a method including providing a matrix of lead frames, each of the lead frames having a lead, forming a channel extending through a width of the lead to create an inner pad, an outer pad and a connection member in the lead, electrically coupling a semiconductor die with the inner pad, and encapsulating at least a portion of the lead frame such that at least a portion of the outer pad is exposed. 
     In a further aspect, the invention features a method including providing a lead frame having a lead, forming a channel extending through a width of the lead to create an inner pad, an outer pad and a connection member in the lead, electrically coupling a semiconductor die with the inner pad, and encapsulating at least a portion of the lead frame such that at least a portion of the outer pad is exposed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing features, methods and other aspects of the invention are explained in the following description taken in connection with the accompanying drawings, wherein: 
         FIG. 1  shows a bottom view of an integrated circuit package  10  according to one embodiment of the present invention; 
         FIG. 2  is a simplified cross-sectional view, along line A—A, of the integrated circuit package  10  shown in  FIG. 1 ; 
         FIG. 3  is a side view of the integrated circuit package  10  shown in  FIG. 1 ; 
         FIG. 4  is a top view of a lead frame pre-assembly of the integrated circuit package  10  shown in  FIG. 1 ; 
         FIG. 5  shows a bottom view of an integrated circuit package  20  according to another embodiment of the present invention; 
         FIG. 6  is a simplified cross-sectional view, along line B—B, of the integrated circuit package  20  shown in  FIG. 5 ; 
         FIG. 7  is a top view of a lead frame pre-assembly of the integrated circuit package  20  shown in  FIG. 5 ; 
         FIG. 8  shows a strip  800 , including six sections  801 - 1  to  801 - 6 , which may be used to make integrated circuit packages according to the present invention; 
         FIG. 9  shows a 3×3 array  900  of lead frames  100 - 1  to  100 - 9  which may be provided in one or more of the sections  801 - 1  to  801 - 6  of the strip  800 ; and 
         FIGS. 10   a - 10   j  show simplified cross-sectional views of certain steps of one type of process for making an integrated circuit package. 
     
    
    
     It is to be understood that the drawings are exemplary, and are not to be deemed limiting to the full scope of the appended claims. 
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Various embodiments of devices according to the present invention will now be described with reference to the drawings. 
       FIG. 1  is a bottom view of an integrated circuit package  10  according to one embodiment of the present invention. Inner lead pads  102 , outer lead pads  106  and a die attachment pad  108  of a lead frame  101  are shown exposed to the environment. Also shown is an encapsulant material  120  encapsulating certain internal portions of the integrated circuit package  10 . The encapsulant  120  may be configured such that certain bottom surfaces of the die attachment pad  108  and the leads  101  are exposed. 
     In one embodiment, the lead frame  100  may have inner rows  105  of inner lead pads  102  arranged in a generally annular configuration, and outer rows  107  of outer lead pads  106  arranged in a generally annular configuration. The pitch between adjacent inner lead pads  102  and adjacent out lead pads  106  of a lead frame  100  of one embodiment may be different. As shown in the embodiment depicted in  FIG. 1 , the inner lead pads  102  of an inner row  105  of pads may be more closely spaced in relation to one another than the outer lead pads  106  of an outer row  107  of pads. Moreover, an inner lead pad  102  may have a smaller footprint or planform area than a corresponding outer lead pad  106 . In such an embodiment, the outer lead pads  106  may conform to a standard leadless plastic chip carrier configuration, while the inner lead pads  102  may be configured to more closely match the placement and spacing of bonding pads  112  of the semiconductor die  110 . 
     The lead frame  100  may also include a die attachment pad  108  onto which a semiconductor die  110  may be attached. In such an embodiment, a soft solder may be used to attach the semiconductor die  110  to the die attachment pad  108 , which may provide improved thermal performance. 
     Certain example dimensions are also depicted in FIG.  1 . As shown in  FIG. 1 , each inner lead pad  102  may be smaller than its corresponding outer lead pad  106 . In one embodiment, the width of a package  10  (shown as dimension “a”) may be about 7.000 mm, the length of an outer lead pad  106  (shown as dimension “b”) may be about 0.550 mm, each outer lead pad  106  may be about 0.230 mm wide (shown as dimension “c”), the pitch (shown as dimension “d”) of adjacent outer lead pads  106  may be approximately 0.500 mm, and inner dimensions “e” and “f” may be about 4.300 mm. 
       FIG. 2  shows a cross-sectional view along line A—A of the integrated circuit package  10  shown in FIG.  1 . This cross-sectional view shows certain components of the package  10  displayed in their respective positions relative to one another. One embodiment of an integrated circuit package  10  may generally include a lead frame  100 , a semiconductor die  110  and an encapsulant  120 . 
     The lead frame  100  of the integrated circuit package  10  of one embodiment may be made of an electrically conductive material such as, e.g., copper. However, the lead frame  100  may be made of other metals, electrically conductive materials, or electrically conductive compounds in accordance with other embodiments of the present invention. The lead frame  100  may provide, at least in part, interconnections between the power, input and/or output terminals of the semiconductor die  110  and any external terminals that may be provided on the integrated circuit package  10 .  FIG. 2  shows a semiconductor die  110  connected to the inner lead pads  102  of the lead frame  100  via, for example, a gold thermo-sonic wire bonding technique. In such an embodiment, conductive gold wires  115  may interconnect bonding pads  112  formed on a top surface of the semiconductor die  110  to the leads  101  of the lead frame  100 . Each such wire  115  may be bonded to both a bonding pad  112  of the semiconductor die  110  at one end, and the corresponding inner lead pad  102  at the other end. Each inner lead pad  102  may be connected to a corresponding outer lead pad  106  by an integrally formed connection portion  104  which, in one embodiment, may have a thickness dimension which is approximately half of the total thickness dimension “t” of a lead  101 . A chemical etching process may be used to form a channel  109  in the lead  101  to create the connection portion  104  of a particular lead  101 . 
     In one embodiment, portions of the upper and lower surfaces of a lead frame  100  may be plated  113  with solder or pure tin (Sn). This solder or pure tin plating  113  may provide an interface surface for mechanical, electrical or both types of connection of the integrated circuit package  10  to an external device (not shown). Alternatively, the lead frame  100  may be pre-plated with palladium to avoid silver migration. 
     As is further shown in  FIG. 2 , the semiconductor die  110  and lead frame  100  may be encapsulated in connection with an integrated circuit package  10  according to one embodiment of the present invention. The encapsulant  120  may be, for example, an epoxy based material applied by, for example, a liquid encapsulation process or a transfer molding encapsulation process. The top surface of the encapsulation may be given a distinctive pattern, which can be conferred to the encapsulation from the molding cavity during the molding process. This pattern, (e.g., a dimple array) may be used to orient the package  10  after singulation. 
       FIG. 3  is a side view of an example embodiment of an integrated circuit package  10  according to the present invention. As shown in  FIG. 3 , the external terminals of an integrated circuit package  10  may include an array of conductive members such as, e.g., solder balls  117 . Such solder balls  117  may be attached to the outer lead pads  106  of the leads  101  using a reflow soldering process. In such an embodiment, the solder balls  117  function as electrical extensions of the leads  101 , and may be capable of providing power, signal inputs and signal outputs to and from the semiconductor die  110 . Such solder balls  117  may also provide clearance between the package  10  bottom and the printed circuit board (not shown) on which the package  10  is mounted. The solder balls  117  may be made of a variety of materials including lead (Pb) free solder. Such a configuration may be referred to as a type of ball grid array. Absent the solder balls  117 , such a configuration may be referred to as a type of land grid array. 
       FIG. 4  depicts a top view of a lead frame  100  and semiconductor die  110  prior to encapsulation. As shown, a semiconductor die  110  is attached to the die attachment pad  108  of the lead frame  100 , and the bonding pads  112  of the semiconductor die  110  are connected via wires  115  to the inner lead pads  102  of the leads  101 . The bonding pads  112  may provide locations at which the semiconductor die  110  may receive power and/or input signals, as well as transmit output signals. The wires  115  are one way to electrically couple a semiconductor die  110  of an integrated circuit package  10  to the leads  101  of the package  10  such that the semiconductor die  110  may receive power, input signals and/or output signals. The configuration of inner lead pads  102  as shown in  FIG. 4  may allow the semiconductor die  110  to be connected to the lead frame  100  using a shorter length of wire  115  than may otherwise be required. 
       FIG. 5  shows a bottom view of an integrated circuit package  20  according to another embodiment of the present invention. In such an embodiment, the die attachment pad  208  may be shaped to accommodate the contours of inner lead pads  202  projecting inwardly from the periphery of the package  20 . 
       FIG. 6  shows a cross-sectional view along line B—B of the integrated circuit package  20  shown in FIG.  5 . The integrated circuit package  20  generally includes a lead frame  200 , one or more semiconductor dies  210  and an encapsulant  220 .  FIG. 7  depicts a top view of a lead frame  200  and semiconductor dies  210 - 1 ,  210 - 2  prior to encapsulation. A number of semiconductor dies  210 - 1 ,  210 - 2  may be attached to the die attachment pad  208 . The configuration of inner lead pads  202  as shown in  FIG. 7  may allow two semiconductor dies  210 - 1 ,  210 - 2  to be connected to the lead frame  200  using a shorter length of wire  215  than may otherwise be required. Conductive wires  215  may be bonded between bonding pads  212  on each semiconductor die  210 - 1 ,  210 - 2  and the inner lead pads  202  of the respective leads  201 . In some cases, it may be desirable to position the inner lead pads  202  close to the semiconductor die  210 . As shown, the connection portions  204  of certain leads  201  may be longer than others to allow certain inner lead pads  202  to be positioned more closely to bonding pads  212  of the semiconductor dies  210 . 
     According to certain embodiments, shown in  FIGS. 8 and 9 , a lead frame  100 ,  200  may be formed in a matrix  900  of substantially identical lead frames. Furthermore, the matrix  900  of lead frames may be formed as one of multiple matrices of lead frames formed in a metal strip  800 . 
       FIG. 8  shows a strip  800  including six sections  801 - 1  to  801 - 6  which may be used to fabricate integrated circuit packages  10 ,  20  of the embodiments described above. Using such a strip  800  may allow an assembly process to be carried out in automated assembly equipment and molds. Several lead frames  100 ,  200  may be produced in the form of, or otherwise assembled into, the strip  800  shown in  FIG. 8  to accommodate semiconductor manufacturing equipment and process flows. Each of sections  801 - 1  to  801 - 6  may include a frame area  802  in which lead frames such as the lead frames  100 ,  200  described above may be formed using, for example, a chemical etching process, a stamping process, a combination of these processes and/or other processes. For example, an array of lead frames, may be formed in the frame area  802 , as shown in FIG.  9 . The periphery of the frame area  802  may contain alignment targets, tooling through-holes and other assembly features (labeled, collectively, by reference numerals  803   a - 803   c ) for use in automated assembly equipment. 
     As shown in  FIG. 9 , several lead frames may also be configured in a matrix array  900 . For example, the strip  800  shown in  FIG. 8  may contain six substantially identical sections  801 - 1  to  801 - 6 , each of which may contain a 3×3 matrix array  900  similar to that shown in  FIG. 9 , which shows nine lead frames. A matrix array  900  like the one shown in  FIG. 9  may be formed in the frame area  802  of each section  801  of the strip  800 . Thus, in one configuration, fifty-four lead frames may be formed in each strip  800 . Other configurations of either the strip  800 , the matrix array  900 , or both, may produce other volumes of lead frames.  FIG. 9  shows lines  901 ,  902 ,  903 ,  904  along which the lead frame  100  may be cut to form integrated circuit packages. 
     Methods of manufacturing embodiments of integrated circuit packages will now be described with reference to the drawings, in particular,  FIGS. 10   a - 10   j.    
     A lead frame  100  may be formed into the configuration shown in the figures by a number of different processes including a chemical process (e.g., etching), a mechanical process (e.g., metal stamping), or a combination of these and/or other processes. As represented in  FIGS. 10   a - 10   b , in one aspect of one method embodiment according to the present invention, a lead frame  100  may be stamped from a sheet  1000  of copper to create a die attachment pad  108  and leads  101 . In such an example method of manufacture, a lead frame  100  may be stamped while it is a part of a matrix array  900  of lead frames. 
     As depicted in  FIG. 10   c , after one or more lead frames  100  have been formed, an etching process may be used to etch a channel  109  into a bottom side of a lead  101  to create an inner lead pad  102 , an outer lead pad  106  and a connection portion  104 . In one method embodiment, a chemical etching process may be used to create the channel  109 . For example, a chemical etching process may include masking the bottom portion of the outer lead pad  106  and inner lead pad  102  such that material from the lead  101  is removed to form the channel  109 . In one method embodiment, the etching process may remove material from the lead  101  to create a channel  109  that is approximately half the thickness of the lead  101 . 
     In one example manufacturing process, as shown in  FIG. 10   d , a semiconductor die  110  may be attached to a die attachment pad  108  of the lead frame  100 . A semiconductor die  110  may be mounted or attached to the die attachment pad  108  by epoxy or any suitable adhesive or fastening material. The semiconductor die  110  may also be attached using a soft solder to provide thermal conductivity between the semiconductor die  110  and the die attachment pad  108 , thereby improving the thermal performance of the resulting package. 
     After the adhesive is cured, if required, the semiconductor die  110  may be wire-bonded to the inner lead pads  102  of the leads  101  using automated bonding equipment including a moving capillary device  1001  (see  FIGS. 10   e - 10   g ). As shown in  FIGS. 10   e - 10   g , gold wires may be attached first to the bonding pads  112  of the semiconductor die  110  ( FIG. 10   e ), and then to the inner lead pads  102  of the leads  101  ( FIG. 10   f ) using automated bonding equipment with a flat plate support  1002 . 
     Following attachment of the semiconductor die  110  to the lead frame  100 , the pre-assembly may be encapsulated. As shown in  FIG. 10   h , a liquid encapsulation process or a transfer molding encapsulation process may be used to create packages  10 ,  20  such as those shown in  FIGS. 1-7 . Upon completion of this assembly step of a particular assembly process, at least a portion of the outer lead pad  106  of the lead frame  100  may remain exposed to allow electrical connection to a printed circuit board (not shown), another semiconductor die and/or another integrated circuit package. 
     As shown in  FIG. 10   i , solder balls  117  may then be attached to the outer lead pads  106  of the leads  101  of each lead frame  100  using, for example, a reflow soldering process. Solder balls  117  attached to the exposed portions of the leads  101  may provide a clearance when the package  10 ,  20  is mounted on a printed circuit board. Such clearance may facilitate cleaning (e.g., cleaning of solder flux). 
     In one example method embodiment of the present invention, after the encapsulation and ball attachment assembly steps, the integrated circuit packages  10 ,  20  may be singulated into individual units using a saw singulation or punching technique (shown in  FIG. 10   j ). During saw singulation, the strip  800  may be mounted to a wafer saw ring by an adhesive tape and saw-singulated using a conventional wafer saw. Singulation may be guided by alignment targets and other features (labeled as reference  901 - 904 ) formed, for example, on a lower surface of the strip  800  (for example, etched or stamped into the lead frame). Such targets or features may be incorporated into the strip  800  during its fabrication, and may help to maintain accurate size tolerances of each integrated circuit package produced in this way. In one example method, the underside of the strip  800  may face upward during a saw singulation process. Once singulated, an individual package  10 ,  20  may be ready for mounting onto a printed circuit board or other device. Optionally, the strip  800  then may be ink-marked or laser-marked and tin- or solder-plated to facilitate a subsequent board-attachment step. 
     Although illustrative embodiments and example methods have been shown and described herein in detail, it is to be understood that there may be numerous variations, embodiments, and examples which may be equivalent to those explicitly shown and described. For example, the scope of the present invention may not necessarily be limited in all cases to execution of the aforementioned steps in the order discussed. Unless otherwise specifically stated, the terms and expressions have been used herein as terms and expressions of description, not of limitation. Accordingly, the invention is not to be limited by the specific illustrated and described embodiments and examples (or terms or expressions used to describe them), but only by the scope of the appended claims.