Abstract:
A window comparator includes a differential circuit stage and a load circuit stage. The differential circuit stage produces a pair of differential currents from an input voltage, the differential currents varying depending on the input voltage with having a maximum and a minimum when the input voltage is a reference voltage. The load circuit stage produces an output voltage from a reference current and a current corresponding to a selected on of the differential currents. The reference current and the current are produced such that a voltage range is determined around the predetermined voltage depending on whether the second current is greater than the reference current. Since a window of the window comparator is formed based on the current and the reference current, the output voltage changes in level depending on whether the input voltage falls into the voltage range.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a semiconductor integrated circuit, and in particular to a window comparator circuit suitable for the semiconductor integrated circuit. 
     2. Description of the Related Art 
     A window comparator outputs a different voltage signal depending on whether an input voltage falls into a predetermined voltage range (hereinafter referred to as a window). In general, such a window comparator includes two operational amplifiers to produce a window. More specifically, a first operational amplifier compares the input voltage with a first reference voltage and a second operational amplifier compares the output of the first operational amplifier with a second reference voltage. 
     However, the conventional window comparator is not suitable for a semiconductor integrated circuit. In other words, it is hard to form the conventional circuit arrangement of a window comparator on a semiconductor substrate using a bipolar process. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a window comparator which is suitable for a semiconductor integrated circuit formed on a semiconductor substrate by using a bipolar process. 
     Another object of the present invention is to provide a window formation method which is capable of forming a window of a window comparator. 
     A circuit of a window comparator according to the present invention includes a first circuit stage and a second circuit stage. The first circuit stage produces a first current from an input voltage, the first current varying depending on the input voltage such that the first current has one of a maximum and a minimum when the input voltage is a predetermined voltage. The second circuit stage produces an output voltage from a reference current and a second current corresponding to the first current. The reference current and the second current are produced such that a voltage range is determined around the predetermined voltage depending on whether the second current is greater than the reference current. In other words, the window of the window comparator is formed based on the second current and the reference current. Therefore, the output voltage changes in level depending on whether the input voltage falls into the voltage range. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a first embodiment according to the present invention; 
     FIG. 2 is a circuit diagram showing an input differential stage of the first embodiment as shown in FIG. 1; 
     FIG. 3 is a diagram showing how the respective currents I c1  -I c4  vary with an input voltage Vin in the input differential stage of FIG. 2; 
     FIG. 4 is a diagram showing how the respective output currents I 1  and I 2  vary with the input voltage Vin in the input differential stage of FIG. 2; 
     FIG. 5 is a circuit diagram showing a load circuit of the first embodiment as shown in FIG. 1; 
     FIG. 6 is a diagram showing how the respective currents I 3  -I 5  vary with the input voltage Vin in the load circuit of FIG. 5; 
     FIG. 7 is a diagram showing how an output voltage V A  varies with the input voltage Vin in the first embodiment of FIG. 1; 
     FIG. 8 is a diagram showing how an inverted output voltage V B  varies with the input voltage Vin in the first embodiment of FIG. 1; 
     FIG. 9 is a circuit diagram showing a second embodiment according to the present invention; 
     FIG. 10 is a diagram showing how the respective currents I 3  -I 6  vary with the input voltage Vin in a load circuit of the second embodiment as shown in FIG. 9; 
     FIG. 11 is a diagram showing how the output voltages V A  and V B  vary with the input voltage Vin in the second embodiment of FIG. 9; 
     FIG. 12 is a circuit diagram showing a third embodiment according to the present invention; 
     FIG. 13 is a diagram showing how the respective currents vary with the input voltage Vin in a load circuit of the third embodiment as shown in FIG. 12; and 
     FIG. 14 is a diagram showing how the output voltages V B  varies with the input voltage Vin in the third embodiment of FIG. 12. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIRST EMBODIMENT 
     Referring to FIG. 1, a window comparator is composed of an input differential stage including NPN transistors Q1-Q4 and a load circuit including PNP transistors Q5-Q8 and NPN transistors Q9-Q11. The input differential stage inputs an input voltage Vin and produces output currents I 1  and I 2 . The load circuit produces an output voltage V A  and an inverted output voltage V B  from the output currents I 1  and I 2  of the input differential stage. 
     The input differential stage is composed of a first differential pair circuit having the transistors Q1 and Q2 whose emitters are connected in common to a constant current source 101 (constant current I L1 ) and a second differential pair circuit having the transistors Q3 and Q4 whose emitters are connected in common to a constant current source 102 (constant current I L2 ). The bases of the transistors Q2 and Q3 are interconnected and a reference voltage Vref is applied thereto and the input voltage Vin is applied to the bases of the transistors Q1 and Q4 which are interconnected. Further, the collectors of the transistors Q1 and Q3 are interconnected and the collectors of the transistors Q2 and Q4 are interconnected. 
     In the first differential pair circuit, the emitter area S E1  of the transistor Q1 is different from the emitter area S E2  of the transistor Q2. Similarly, in the second differential pair circuit, the emitter area S E3  of the transistor Q3 is different from the emitter area S E4  of the transistor Q4. Here, S E1  :S E2  =S E3  :S E4  =a:b (a≠b). 
     The load circuit is composed of three current mirror circuits and an inverter circuit. More specifically, a first current mirror circuit is composed of the transistors Q5 and Q6. The base and collector of the transistor Q5 are interconnected and further connected to the collectors of the transistors Q1 and Q3 of the input differential stage. The bases of the transistors Q5 and Q6 are interconnected and a power supply voltage Vcc is applied to the emitters thereof. Therefore, the transistor Q5 cooperates with the transistor Q6 to form the first current mirror circuit. Similarly, a second current mirror circuit is composed of the transistors Q7 and Q8. The base and collector of the transistor Q7 are interconnected and further connected to the collectors of the transistors Q2 and Q4 of the input differential stage. The bases of the transistors Q7 and Q8 are interconnected and the power supply voltage Vcc is applied to the emitters thereof. Therefore, the transistor Q7 cooperates with the transistor Q8 to form the second current mirror circuit. 
     In the first current mirror circuit, the emitter area S E5  of the transistor Q5 is different from the emitter area S E6  of the transistor Q6. Here, S E5  :S E6  =c:d (c≠d). Similarly, in the second current mirror circuit, the emitter area S E7  of the transistor Q7 is different from the emitter area S E8  of the transistor Q8. Here, S E7  :S E8  =e:f (e≠f). 
     A third current mirror circuit is composed of the transistors Q9 and Q10. The base and collector of the transistor Q9 are interconnected and further connected to the collector of the transistor Q8 of the second current mirror circuit. The collector of the transistor Q10 is connected to the collector of the transistor Q6 of the first current mirror circuit. The bases of the transistors Q9 and Q10 are interconnected and their emitters are grounded. The emitter area of the transistor Q9 is equal to that of the transistor Q10. The output voltage V A  appears on a connection point of the collectors of the transistors Q6 and Q10. 
     The inverter circuit is composed of the transistor Q11 and a resistor R1. The base of the transistor Q11 is connected to the connection point of the collectors of the transistors Q6 and Q10. The emitter of the transistor Q11 is grounded and the collector thereof is connected to the power supply voltage Vcc through the resistor R1. The inverted output voltage V B  appears on the collector of the transistor Q11. 
     INPUT DIFFERENTIAL STAGE 
     Referring to FIG. 2, there is shown the input differential stage in the window comparator of FIG. 1. In this figure, the load circuit is denoted by R C1  and R C2 . First and second loads R C1  and R C2  are connected to first and second output points of the input differential stage, that is, the collectors of the transistors Q1 and Q3 and the collectors of the transistors Q2 and Q4, respectively. The output currents I 1  and I 2  of the input differential stage flow through the first and second loads R C1  and R C2 , respectively. Further, the collector currents of the transistors Q1-Q4 are denoted by I C1  -I C4 , respectively, and, as described before, the respective emitter area ratios of the differential pair circuits are both a/b. In such an input differential stage, the collector currents I C1  -I C4  of the transistors Q1-Q4 are, as known well, represented by the following equations (1) to (4): ##EQU1## wherein K is Boltzmann&#39;s constant, T is the absolute temperature, q is the charge of an electron, β is a current amplification factor, V1 is the input voltage Vin, and V2 is the reference voltage Vref. Further, dV is represented as follows: 
     
         dV=(KT/q)×ln(a/b)                                    (5), 
    
     wherein ln indicates the natural logarithm. Therefore, when a/b≠1, the characteristic curves of the collector currents I C1  and I C2  and those of the collector currents I C3  and  I   C4  are shifted away from the reference voltage Vref by dV in opposite directions. 
     Referring to FIGS. 3 and 4, the current characteristic curves are shown in the case of I L1  =I L2  =I L . As shown in FIG. 3, the respective collector currents I C1  -I C4  of the transistors Q1-Q4 vary according to the input voltage Vin. Since the respective emitter area ratios of the differential pair circuits are a/b≠1, the characteristic curves of the collector currents I C1  and I C2  and those of the collector currents I C3  and I C4  are symmetric with respect to a vertical line indicating the reference voltage Vref as shown in the figure. Since I 1  =I C1  +I C3  and I 2  =I C2  +I C4 , the characteristic curves of I 1  and I 2  are symmetric with respect to a horizontal line indicating the constant current I L  as shown in FIG. 4. 
     LOAD CIRCUIT 
     Referring to FIG. 5, there is shown the load circuit of the window comparator of FIG. 1, corresponding to R C1  and R C2  of FIG. 2. As described above, the transistors Q5 and Q6 having a first emitter area ratio (c:d) constitute the first current mirror circuit, the transistors Q7 and Q8 having a second emitter area ratio (e:f) constitute the second current mirror circuit, and the transistors Q9 and Q10 having the equal emitter area constitute the third current mirror circuit. When the respective collector currents of the transistors Q6 and Q8 are denoted by I 3  and I 4 , the base current of the transistor Q11 by I 5 , and the collector current of the transistor Q10 by I 6 , the collector current I 3  is represented by d/c×I 1  and the collector current I 4  is represented by f/e×I 2 . Further, the collector current I 6  is substantially equal to I 4  because the transistors Q9 and Q10 have the equal emitter area and therefore the base current is negligible. 
     Referring to FIG. 6, the current characteristic curves of the load circuit are shown in the case where c:d=1:2 and e:f=1:3. More specifically, the collector current I 3  is represented by 2I 1  and the collector current I 4  is represented by 3I 2 . By setting the emitter area ratios like these, a window range 201 where I 3  ≧I 4  and other ranges 202 where I 3  &lt;I 4  are generated from a pair of differential output currents I 1  and I 2  of FIG. 4. The window range 201 where I 3  ≧I 4  has a center voltage of Vref with a deviation determined by the emitter area ratios d/c and f/e. In other words, the emitter area ratios d/c and f/e may be set so that a desired window range 201 can be generated. 
     In the outside ranges 202 where I 3  &lt;I 4 , all the collector current I 3  of the transistor Q6 flows into the collector of the transistor Q10, resulting in I 3  =I 6 . Therefore, the base current I 5  of the transistor Q11 is equal to zero when the input voltage Vin falls into the outside ranges 202. On the other hand, in the window range 201 where I 3  ≧I 4 , the extra current of the collector current I 3  flows as the base current I 5  into the base of the transistor Q11. That is, I 5  =I 3  -I 6 . 
     In this manner, the base current I 5  of the transistor Q11 flows only when the input voltage Vin falls into the window range 201. In other words, with a cut-off point of I 3  =I 4 , the transistor Q11 is kept off or non-conductive during the outside range 202 and becomes on or conductive during the window range 201. Therefore, a sharp comparator window can be obtained as shown in FIGS. 7 and 8. 
     FIGS. 7 and 8 show an input-output response of the embodiment in circuit-simulation on condition that a:b=2:1, c:d=1:2, e:f=1:3, I L1  =I L2  =I L  =5 μA, Vref=0.87 V, Vcc=1.05 V, the resistor R1=100 KΩ. It is apparent from the figures that the output voltage V A  and the inverted output voltage V B  sharply change at the edges of the window range 201 to produce a sharp comparator window. 
     SECOND EMBODIMENT 
     Referring to FIG. 9, a window comparator according to a second embodiment of the present invention has the same input differential stage as the first embodiment of FIG. 1. Therefore, the characteristic curves of the output currents I 1  and I 2  are shown in FIG. 4, as in the case of the first embodiment. In the second embodiment, however, the load circuit is different from the first embodiment as will be described hereinafter. 
     As shown in FIG. 9, the load circuit is composed of three current mirror circuits and an inverter circuit. More specifically, a first current mirror circuit is composed of the transistors Q21 and Q22. The base and collector of the transistor Q21 are interconnected and further connected to the collectors of the transistors Q1 and Q3 of the input differential stage. The bases of the transistors Q21 and Q22 are interconnected and a power supply voltage Vcc is applied to the emitters thereof. Therefore, the transistor Q21 cooperates with the transistor Q22 to form the first current mirror circuit. Similarly, a second current mirror circuit is composed of the transistors Q23 and Q24. The base and collector of the transistor Q23 are interconnected and further connected to the collectors of the transistors Q2 and Q4 of the input differential stage. The bases of the transistors Q23 and Q24 are interconnected and the power supply voltage Vcc is applied to the emitters thereof. Therefore, the transistor Q23 cooperates with the transistor Q24 to form the second current mirror circuit. In the second embodiment, the emitter area of the transistor Q21 is equal to that of the transistor Q22, that is, c:d=1:1. Similarly, the emitter area of the transistor Q23 is equal to that of the transistor Q24, that is, e:f=1:1. 
     A third current mirror circuit is composed of the transistors Q25 and Q26. The base and collector of the transistor Q25 are interconnected and further connected to the collector of the transistor Q24 of the second current mirror circuit. The collector of the transistor Q26 is connected to the collector of the transistor Q22 of the first current mirror circuit. The bases of the transistors Q25 and Q26 are interconnected and their emitters are grounded. The emitter area SE 25  of the transistor Q25 is different from the emitter area SE 26  of the transistor Q26. Here, SE 25  :SE 26  =h:g. The output voltage V A  appears on a connection point of the collectors of the transistors Q22 and Q26. 
     The inverter circuit is composed of the transistor Q11 and the resistor R1 as in the case of the first embodiment. The inverted output voltage V B  appears on the collector of the transistor Q11. 
     The transistors Q21 and Q22 having the equal emitter area constitute the first current mirror circuit, the transistors Q23 and Q24 having the equal emitter area constitute the second current mirror circuit, and the transistors Q25 and Q26 having different emitter areas (area ratio is h:g) constitute the third current mirror circuit. When the respective collector currents of the transistors Q22 and Q24 are denoted by I 3  and I 4 , the base current of the transistor Q11 by I 5 , and the collector current of the transistor Q26 by I 6 , the collector current I 3  is substantially equal to I 1  and the collector current I 4  is substantially equal to I 2 . Further, the collector current I 6  is represented by g/h×I 4  because the base current is negligible. 
     Referring to FIG. 10, the current characteristic curves of the load circuit are shown in the case where h:g=2:3. More specifically, the collector current I 6  is represented by 3/2×I 4 . By setting the emitter area ratio like this, a window range 301 where I 3  ≧I 6  (=3/2×I 4 ) and other ranges 302 where I 3  &lt;I 6  (=3/2×I 4 ) are generated from a pair of differential output currents I 1  and I 2  of FIG. 4. The window range 301 has a center voltage of Vref with a deviation determined by the emitter area ratios g/h. In other words, the emitter area ratios g/h may be set so that a desired window range 301 can be generated. 
     In the outside ranges 302 where I 3  &lt;I 6 , all the collector current I 3  of the transistor Q22 flows into the collector of the transistor Q26, resulting in I 3  =I 6 . Therefore, the base current I 5  of the transistor Q11 is equal to zero when the input voltage Vin falls into the outside ranges 302. On the other hand, in the window range 301 where I 3  ≧I 6 , the extra current of the collector current I 3  flows as the base current I 5  into the base of the transistor Q11. That is, I 5  =I 3  -I 6 . 
     In this manner, the base current I 5  of the transistor Q11 flows only when the input voltage Vin falls into the window range 301. In other words, with a cut-off point of I 3  =I 6 , the transistor Q11 is kept off or non-conductive during the outside range 302 an d becomes on or conductive during the window range 301. Therefore, a sharp comparator window can be obtained as shown in FIG. 11. 
     FIG. 11 shows an input-output response of the embodiment in circuit simulation on condition that a:b=2:1, h:g=2:3, I L1  =I L2  =I L  =5 μA, Vref=0.87 V, Vcc=1.05 V, the resistor R1=100 KΩ. It is apparent from the figure that the output voltage V A  and the inverted output voltage V B  sharply change at the edges of the window range 301 to produce a sharp comparator window. 
     THIRD EMBODIMENT 
     Referring to FIG. 12, a window comparator according to a third embodiment of the present invention has the same input diferential stage as the first embodiment of FIG. 1. Therefore, the characteristic curves of the output currents I 1  and I 2  are shown in FIG. 4, as in the case of the first embodiment. In the third embodiment, however, the load circuit is different from the first embodiment as will be described hereinafter. 
     As shown in FIG. 12, the load circuit is composed of a current mirror circuit composed of the transistors Q21 and Q22, a load Rc, a constant current source 103 and an inverter circuit composed of the transistor Q11. More specifically, the base and collector of the transistor Q21 are interconnected and further connected to the collectors of the transistors Q1 and Q3 of the input differential stage. The bases of the transistors Q21 and Q22 are interconnected and a power supply voltage Vcc is applied to the emitters thereof. Therefore, the transistor Q21 cooperates with the transistor Q22 to form the current mirror circuit. In the third embodiment, the emitter area of the transistor Q21 is equal to that of the transistor Q22, that is, c:d=1:1. The collector of the transistor Q22 is grounded through the constant current source 103. The output voltage V A  appears on the collector of the transistor Q22. The inverter circuit is composed of the transistor Q11 and the resistor R1 as in the case of the first embodiment. The inverted output voltage V B  appears on the collector of the transistor Q11. On the other hand, the collectors of the transistors Q2 and Q4 of the input differential stage is connected to the power supply Vcc through the load Rc. 
     Hereinafter, the collector current of the transistor Q22 is denoted by I 3 , the base current of the transistor Q11 by I 5  and the constant current of the constant current source 103 by I L3 . 
     Referring to FIG. 13, the collector current I 3  is substantially equal to I 1  because the emitter area of the transistor Q21 is equal to that of the transistor Q22 and the constant current I L3  of the constant current source 103 is set so that a horizontal line indicating the constant current I L3  cuts the curve of the collector current I 3  or I 1  as shown in this figure. Therefore, a window range 401 where I 3  ≧I L3  and other ranges 402 where I 3  &lt;I L3  are generated from the output current I 1  of FIG. 4. The window range 401 has a center voltage of Vref with a deviation determined by the constant current I L3 . 
     In the outside ranges 402 where I 3  &lt;I L3 , all the collector current I 3  of the transistor Q22 flows into the constant current source 103, resulting in I 3  =I L3 . Therefore, the base current I 5  of the transistor Q11 is equal to zero when the input voltage Vin falls into the outside ranges 402. On the other hand, in the window range 401 where I 3  ≧I L3 , the extra current of the collector current I 3  flows as the base current I 5  into the base of the transistor Q11. That is, I 5  =I 3  -I L3 . 
     In this manner, the base current I 5  of the transistor Q11 flows only when the input voltage Vin falls into the window range 401. In other words, with a cut-off point of I 3  =I L3 , the transistor Q11 is kept off or non-conductive during the outside range 402 and becomes on or conductive during the window range 401. Therefore, a sharp comparator window can be obtained as shown in FIG. 14. 
     FIG. 14 shows an input-output response of the embodiment in circuit simulation on condition that a:b=2:1, I L1  =I L2  =I L  =5 μA, I L3  =5.5 μA, Vref=0.87 V, Vcc=1.05 V, the resistor R1=100 KΩ. It is apparent from the figure that the inverted output voltage V B  sharply changes at the edges of the window range 401 to produce a sharp comparator window. 
     As described above, according to the present invention, a sharp comparator window can be obtained with simplified circuit arrangement. In other words, the window comparator can be formed with the reduced number of circuit elements and reduced power consumption. Therefore, it is suitable for circuit integration.