Abstract:
A chip-packaging substrate. The substrate is capable of reducing damage during packaging, shrinking its connecting portions so that the length of any of the gap slots between the packaging portion and the frame portion of the substrate is increased. Furthermore, a dummy layer is provided to one surface of the frame portion to flush the surface on the frame portion with that of the packaging portion as much as possible.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates in general to a packaging substrate. More specifically, it relates to a chip-packaging substrate capable of reducing damage to the substrate during packaging.  
           [0003]    2. Description of the Related Art  
           [0004]    Ball Grid Array (hereinafter referred to as BGA) packaging is widely applied to package the integrated circuits of chip sets or graphic chips, etc. The BGA packaging has a plurality of tin balls provided onto the bottom surface of a substrate and arranged in a form of an array. The balls serve as the leads or pins (conductive media) between a chip (or IC) and a circuit board, replacing the conventional lead frames. The BGA packaging can provide not only more pins but also larger space between every two adjacent pins than that of conventional packaging, under the same size of substrate. Compared with the conventional QFP, with pin number up to  304  but whose pins are easily bent or twisted, BGA packaging is not subject to this issue. In addition, BGA packaging provides superior heat dissipation and electrical conductivity by providing shorter conducting paths between the chip and the circuit board.  
           [0005]    According to the raw material of the substrate, BGA substrates are divided into three categories: Plastic BGA (PBGA), Metal BGA (MBGA), and Tape BGA (TBGA). The PBGA substrate is made of organic materials such as compounds of BT resin and glass fiber. It is the most popular BGA substrate in the packaging industry.  
           [0006]    [0006]FIG. 1A shows a top view of a PBGA substrate. The PBGA substrate in FIG. 1A has four units, in the form of a 1×4 array, for packaging 4 chips. The packaging units of a PBGA substrate can also be arranged in the form of an n×m (n and m&gt;1) array for specific requirement. FIG. 1B shows an enlarged view of one unit  100  of the PBGA substrate. In FIG. 1B, the unit  100  comprises a rectangular packaging portion  102 , a rectangular frame portion  104  enclosing the packaging portion  102  so that a gap exists between the outer edge of the packaging portion  102  and the inner edge of the frame portion  104 , and four connecting portions ( 106   a ˜ 106   d ) respectively provided to connect the four corner regions at the outer edge of the packaging portion  102  with the four corner regions at the inner edge of the frame portion  104 . All the four connecting portions ( 106   a ˜ 106   d ) are substantially L-shaped and connect the packaging portion  102  and the frame portion  104  to form the main body of the unit  100 .  
           [0007]    A first circuit layer (for example, a copper layer not shown in FIG. 1B) is provided on the top surface of the unit  100 . An isolating paint covers the first circuit layer, only revealing a portion of the first circuit layer at some specific positions. A second circuit layer (for example, a copper layer not shown in FIG. 1B) is provided on the bottom surface of the unit  100 . An isolating paint also covers the second circuit layer, only revealing a portion of the second circuit layer at some specific positions. The first and second circuit layers have corresponding connections electrically.  
           [0008]    The main process for packaging a chip using the PBGA unit  100  comprises the steps of: (1) Assembly, (2) Molding, (3) Ball grid implantation, and (4) Singulation, as illustrated in FIG. 2.  
           [0009]    Assembly mounts a die (chip) cut from a wafer to the top surface of the packaging portion  102  of the PBGA unit  100 , and then provides gold bonding wires to electrically connect the die with the revealing first circuit layer.  
           [0010]    Molding encapsulates the die mounted in the packaging portion  102 , using a packaging body in conjunction with plastic (or glue) material.  
           [0011]    Ball gird implantation forms a plurality of conductive balls, arranged in the form of an array, on the second circuit layer on the bottom surface of the PBGA unit  100 .  
           [0012]    Singulation separates the frame portion  104  and the encapsulated packaging portion  102  by destroying the connecting portions  106   a˜   106   d  using press machine or cutting apparatus.  
           [0013]    The first, second, third and fourth connecting portions ( 106   a˜   106   d ) are of the same dimensions and sizes. Using the second connecting portion  106   b  as an example, each of the two branches of the L-shaped second connecting portion  106   b  extends a distance of L 1  along the adjacent inner edge of the frame portion  104 .  
           [0014]    For the PBGA substrate with packaging area of 40 mm×40 mm (the area of the packaging portion  102 ), the distance of L 1  is about 3 mm to 4 mm. The distance of L 1  is long enough that the distance (L 2 ) of the gap slot  108  becomes smaller. Consequently, damage such as cracks and chip-out will easily occur on the packaging portion  102  when carrying out the singulation process.  
           [0015]    Additionally, no copper layer is formed on the top surface of the frame portion  104  and therefore the surfaces of the first circuit layer (formed on the packaging portion  102 ) and that of the frame portion  104  are not flush. The height difference between the surfaces of the packaging portion  102  and the frame portion  104  will cause glue overflow (disfiguring the outlook of the encapsulated chip) or pressing damage to packaging portion  102  of the PBGA substrate when molding.  
         SUMMARY OF THE INVENTION  
         [0016]    Therefore, an object of the present invention is to provide a chip-packaging substrate capable of reducing damage to the substrate during packaging. The connecting portions of the substrate are shrunk so that the lengths of any of the gap slots between the packaging portion and the frame portion of the substrate are increased, thereby preventing damage such as cracking and chip-out when carrying out singulation.  
           [0017]    The other object of the present invention is to provide a chip-packaging substrate having additional dummy layers provided to the surface of the frame portion of the substrate so that the height difference between the packaging portion and the frame portion is alleviated, thereby preventing the glue overflow and pressing damage during molding process. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:  
         [0019]    [0019]FIG. 1A shows a top view of a PBGA substrate;  
         [0020]    [0020]FIG. 1B shows an enlarged view of one unit of the PBGA substrate depicted in FIG. 1A;  
         [0021]    [0021]FIG. 2 shows a main process for packaging a chip using the PBGA substrate;  
         [0022]    [0022]FIG. 3A shows a top view of a novel PBGA substrate according to one preferred embodiment of the present invention;  
         [0023]    [0023]FIG. 3B shows an enlarged view of one unit of the PBGA substrate depicted in FIG. 3A. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]    [0024]FIG. 3A shows a top view of a novel PBGA substrate according to one preferred embodiment of the present invention. The PBGA substrate depicted in FIG. 3A has four encapsulation units arranged in the form of a 1×4 array and can package four chips. The packaging units of a PBGA substrate can also be arranged in the form of an n×m (n and m&gt;1) array such as 2×4, 3×4 . . . , for specific requirement.  
         [0025]    [0025]FIG. 3B shows an enlarged view of one unit  300  of the PBGA substrate. In this embodiment, the specification of the PBGA substrate is 40 mm×40 mm (about the area of the packaging portion of the PBGA unit  300 ) but not limited to the above.  
         [0026]    Referring to FIG. 1B, the unit  300  comprises a rectangular packaging portion  302 , a rectangular frame portion  304  enclosing the packaging portion  102  so that a gap exists between the outer edge of the packaging portion  302  and the inner edge of the frame portion  304 , and four connecting portions ( 306   a˜   306   d ) respectively provided to connect the four corner regions at the outer edge of the packaging portion  302  with the four corner regions at the inner edge of the frame portion  304 . All the four connecting portions ( 306   a˜   306   d ) are substantially L-shaped and connect the packaging portion  302  and the frame portion  304  to form the main body of the unit  300 .  
         [0027]    The first aspect of the present invention is that each of the two branches of any of the L-shaped first to third connecting portions  106   a˜   106   c has an extended distance of L 3  along the adjacent inner edge of the frame portion  104  not greater than 2 mm, as depicted in FIG. 3B.  
         [0028]    The first to third connecting portions  306   a˜   306   c are shrunk, therefore increasing the length of any of the gap slots  308 . The packaging portion  302  and the frame portion  304  can easily be separated by destroying the connecting portions during the singulation process, preventing damage from crack and chip-out, etc.  
         [0029]    Furthermore, through holes  310  are formed in the first to third connecting portions  306   a˜   306   c . Each of the through holes  310  is round and has a diameter between 0.8˜1.2 mm.  
         [0030]    Similar to the conventional art,a first circuit layer (for example, a copper layer not shown in FIG. 3B) is provided on the first surface of the packaging portion  302  (that is, the top surface of the unit  300 ). An isolating paint covers the first circuit layer, only revealing a portion of the first circuit layer at some specific positions. A second circuit layer (for example, a copper layer not shown in FIG. 3B) is provided on the second surface of the packaging portion  302  (that is, the bottom surface of the unit  300 ). An isolating paint also covers the second circuit layer, only revealing a portion of the second circuit layer at some specific positions, for ball gird implantation. Also the first and second circuit layers have corresponding connections electrically.  
         [0031]    The second aspect of the present invention is that a first dummy layer  312  (for example a copper layer) is provided on the first surface of the frame portion  304 , and covered with isolating paint. Without the first dummy layer, a height difference between the first surface of the frame portion  304  and the surface of the first circuit layer will be introduced, resulting in the problems of glue overflow and pressing damage.  
         [0032]    Similarly, a second dummy layer (for example a copper layer, not shown in FIG. 3B) is provided on the second (or bottom) surface of the frame portion  304 , and covered with isolating paint.  
         [0033]    The first dummy layer  312  and second dummy layer respectively have a specific pattern uniformly distributed on the first surface of each of the frame portions  304 , referring to the FIGS. 3A and 3B. The first and second dummy layers are respectively mesh, lattice, or parallel line patterns. In this embodiment, the first dummy layer is mesh.  
         [0034]    Also, a plurality of holes can be formed in the frame portion for positioning.  
         [0035]    While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.