Abstract:
A method and corresponding apparatus first encodes digital data by grouping the data into a data segment. A particular length of the data segment is placed into check information encoded within the data segment. The encoded data segments are then transmitted from a first computer to a second computer that receives and decodes the data segments. The second computer decodes the received data segments dependent on the particular length information that was placed in the check information during encoding of the data segment. Decoding dependent upon the particular length information provides dependable synchronization and improved resistance to the introduction of errors, accordingly.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention is directed to the encoding, transmission and decoding of digital data that are, grouped into data segments of variable length. 
     2. Description of the Prior Art 
     In what is referred to as packet-oriented data transmission, the data transmitted as digital data are grouped into data segments that comprise a permanent prescribed or a variable segment length. The data segments are channel-encoded and transmitted. 
     Digital data are, for example, digital video data, digital audio data or digital text information such as in the ASCII format. 
     When variable segment lengths are allowed for the data segments, a problem arises for the receiving station of synchronizing correctly to the received sequential bit stream in view of the data segments (i.e., to respectively correctly find the start of a data segment). This job is usually carried out by a multiplexer. 
     The multiplex protocol ITU-H.223 of the picture telephony standard ITUH-H.324 is described in ITU-H.223, International Telecommunications Union, Multiplex Protocol for Low Bit Rate Multimedia Communication, 1996. Variable segment lengths are employed in the multiplex protocol ITU-H.223. The individual data segments are separated from one another by what is referred to as a synchronization word or HDLC Flags, ( H igh  L evel  D ata  L ink  C ontrol Flags). The HDLC flag is composed of the bit sequence “0111 1110”. In order to prevent an incorrect classification (emulation) of an identical bit sequence occurring in the data segment as synchronization word, each data segment is investigated for the bit sequence “11111” (five successive bits having the value “1”) in the encoding. When such a bit sequence is found, then one bit having the value “0” is automatically inserted. This procedure is referred to as bit stuffing. 
     This method exhibits poor properties given a faulty transmission channel, for example in the radio transmission according to the GSM method or the DECT method. As a result of the faulty transmission channel, the synchronization word is often not found when an error occurs in the synchronization word during the, transmission. A transmission error in the data segment can also lead to emulation of the synchronization word, this leading to an incorrect synchronization at the receiver of the transmitted data segment. 
     EP-A-0 690 630 discloses a method and an arrangement for the transmission of digital data. Given the method disclosed in EP-A-0 699 630, digital data are encoded according to a “serial digital data interface (SDDI) format, are transmitted and decoded. An apparatus correspondingly matched to the SDDI format is employed for the encoding, transmission and decoding. 
     EP-A-0 666 652 discloses a method for decoding a digital signal with variable length. Given the procedure disclosed by EP-A-0 666 652, the length of a received digital signal is respectively processed such before the actual decoding of received digital signals that the processed digital signal comprises a predetermined maximum length. 
     SUMMARY OF THE INVENTION 
     The invention is thus based on the problem of specifying methods and devices with which a dependable synchronization to the data segments is achieved. 
     According to a method of the present invention, the digital data are grouped into at least one data segment. The data segment is encoded, wherein a length of the data segment is entered into check information of the data segment during the encoding. 
     In addition the data segment, which contains check information having a particular length of the data segment, is decoded dependent on the particular length of the data segment. 
     In a further embodiment the data segments, which contain check information having a particular length of the data segment, are decoded dependent on the particular length of at least one other data segment. 
     An apparatus of the present invention for decoding digital data comprises a processor unit that is configured to decode the received data segment dependent on the particular length of the data segment encoded into the data segment and also the synchronization information. 
     The apparatus of the present invention can be comprised of a computer, having a programmable microprocessor as the processor unit. The encoding and decoding of the digitized images in the present invention ensues upon employment of a computer program that is programmed such that the corresponding method steps are implemented by the computer. 
     The apparatus can also be specific hardware modules, such as a specific computer card for encoding or, decoding example. 
     It will be appreciated by those skilled in the art that the present invention utilizing a particular length of the respective data segment contained in the check information of the data segment results in a reliable synchronization and, thus improved resistance to errors. 
     The resistance to errors is further improved in a an embodiment of the invention in that a synchronization word is also employed in addition to the particular segment length and the technique of bit stuffing may also be employed. 
     For further enhancing the resistance to error, it is also advantageous in an embodiment to secure the specification of the segment length and/or a specification about the type of data contained in the data segment with error recognition information and/or error correction information. 
     Additional advantages and novel features of the invention will be set forth in part in the description which follows and, in part, will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The Advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed-out in the attended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The figures showed a preferred exemplary embodiment of the invention, which is explained in greater detail below. 
     Shown are: 
     FIG. 1 which is a sketch of the structure of a data segment having check information and payload data information; 
     FIG. 2 which is a sketch of a computer arrangement having two computers and a transmission medium for encoding, transmission and decoding of digital data; and 
     FIG. 3 which is a flowchart wherein the method steps of the method are shown. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 shows a camera K with which a sequence of images B are registered and supplied as digital video data VD to a first computer R 1  and stored. A voice signal SS is registered via a microphone MIK and is supplied as digitized audio data AD to the first computer R 1  and is stored. Input of text information TD is performed via a keyboard TA and/or a mouse MA. The first computer R 1  also comprises a picture screen BS for displaying arbitrary information. 
     The first computer R 1  is connected to a second computer R 2  via a transmission medium UM, for example a cable or a radio tense mission link. The digital data encoded by the first computer R 1  are transmitted via the transmission medium UM to the second computer R 2  and which decodes the encoded data. The first computer R 1  and the second computer R 2  both include a memory SP and a processor unit P that are connected to one another via a bus BU. The processor unit P of the first computer R 1  is conformed to implement method steps explained below for encoding the digital data are implemented. The processor unit P of the second computer R 2  is fashioned such that the received, encoded data are decoded in conformity with the method described below. The second computer R 2  likewise comprises a picture screen BS for displaying arbitrary information as well as a keyboard TA and/or a mouse MA, a camera K and a microphone MIK. 
     The digital data, video data VD, audio data AD and/or text data TD are grouped into at least one data segment DSi (i=1 . . . n) in the first computer R 1  (Step  101 ; see FIG.  3 ). 
     The data segment DSi contains check information Ki and payload information NDi, which is the actual digital data to be transmitted. 
     The structure of the data segment DSi is shown in FIG.  1 . 
     The data segment DSi comprises a synchronization word S (HDLC Flag) composed of the bit sequence “0111 1110”. 
     The check information Ki contains information required for the transmission. Information conconcerning the type of data and the sequence are contained in the payload data information NDi in a multiplex code field MC having a length of 4 bits. 
     The length of the payload data information NDi is indicated with a segment length field MPL and, thus, the length of the data segment DSi is also implicitly indicated since the check information Ki and the synchronization word S comprise a fixed, prescribable length. The segment length field MPL comprises a length of 7 bits, wherein a maximum length of the payload data information NDi of 126 bytes can be described. The value  127  is reserved for the case wherein the payload data information NDi is longer than 126 bytes. 
     A field contains error recognition information and/or error correction information for the data contained in the check information Ki. The BCH field comprises a length of 4 bits. The field contains the BCH code ( 15 ,  11 ) formed over the check information Ki with a free distance of 3. An error can be corrected with the BCH code ( 15 ,  11 ) and further errors can be recognized. 
     The payload information NDi contain video data VD, audio data AD and text data TD. 
     The data segment DSi or, the data segments DSi are encoded, wherein the length of the payload data information in the ith data segment is entered into the segment length field MPL by the first computer R 1  (see Step  102  in FIG.  3 ). 
     The encoded data segment DSi is transmitted from the first computer R 1  to the second computer R 2  (see Step  103 ). 
     The data segments DSi received by the second computer R 2  are decoded dependent on the particular length in the segment length field MPL of the data segment DSi and/or dependent on the particular length in the segment length field MPL of another data segment DSj, j≠i (see Step  104 ). 
     Decoding proceeds in that the synchronization word S is first identified in the received bit stream in order to find the start of a data segment DS 1  within the bit stream. 
     In order to enhance protection against of error of the synchronization word S, a correlation threshold is employed that indicates a number of bits that a data word identical to the synchronization word S must have in order to be classified as synchronization word S. When the correlation threshold is selected too high, then the plurality of unrecognized synchronization words S will increase since transmission errors falsify the synchronization word S. 
     If a correlation threshold selected too low, more synchronization words S are recognized. However, the number of incorrectly classified synchronization words S also increases as more synchronization words S are recognized. 
     Given a length of the synchronization word S of 32 bits, a correlation threshold of 27 bits has proven adequate. 
     When the synchronization word S was correctly identified and when the check information Ki was also correctly decoded, then the position of the synchronization word S of the following data segment DSi+1 is determined upon employment of the segment length field MPL. 
     Thus it is intuitive to lower the correlation threshold for the identified position in order to increase the resistance error. In this case, a correlation threshold of 23 bits has proven adequate 
     In order to prevent faulty decoding, the present invention also searches for the synchronization word S in the payload data information NDi, wherein the correlation threshold, however, is selected high in order to avoid the detection of incorrect synchronization words S. In this case, a correlation threshold of 30 bits has proven adequate 
     The present invention also includes analyzing preceding data segments DSi−1 in the decoding in order to defectively determine the position of the synchronization word S of the data segment DSi and, thus, the position of the check information Ki in the data segment DSi as well. When the decoding of the check information Ki in the data segment DSi is now-error-free, then conclusions can be drawn dependent on the correlation result that the data segment DSi was correctly recognized. 
     When the check information Ki in the data segment DSi is not decoded, then the segment length field MPL cannot be employed. In this case, the synchronization word S of the following data segment DSi+1 is determined. It is thus known how many bits are between the successive synchronization words S. The length of the payload data information NDi and, thus, the value of the segment length field MPL is calculated from this information (check information Ki and synchronization word S have fixed lengths). It is thus possible to correct the segment length field MPL on the basis of the calculation. Hence the probability of a correct decoding of the check information Ki increases. 
     A few alternatives to the exemplary embodiment described above are disclosed below. 
     The plurality of bits in the aforementioned fields in the check information Ki are freely prescribable and not critical to the invention. 
     The employment of the synchronization word is not required but increases the resistance to error in the data transmission. The resistance to error that can be achieved is increased as the synchronization word selected becomes longer. 
     The error recognition information and/or error correction information contained in the BCH field can be formed in an arbitrary way upon employment of a code for error recognition and/or error correction. The employment of the BCH field is optional in the framework of the invention. 
     What is to be understood by a computer in this context is a device having a processor unit with which the above-described method steps can be implemented including, for example, a picture telephone with integrated microprocessor. 
     The invention can be clearly seen therein that a length particular of the respective data segment is contained in the check information of the data segment, as a result whereof a dependable synchronization and, thus, improved resistance to error is achieved. 
     While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment, but, on the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.