Abstract:
An operational amplifier includes a differential amplifier stage having positive and negative input terminals formed by a pair of differential amplifier circuits, a current mirror stage having a pair of current mirror circuits coupled to the differential amplifier stage and producing a common output, and a buffer circuit having a current source connected to the common output of the current mirror stage, wherein the buffer circuit includes a plurality of first input transistors and plurality of second input transistors. The buffer circuit has a diamond arrangement formed of a first output transistor, a second output transistor, at least one of the first input transistors, and at least one of the second input transistors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an operational amplifier, and more particularly, to an operational amplifier suited for use in portable communication equipment and the like. 
     2. Description of the Related Art 
     Japanese Unexamined Patent Publication No. 7-46059 shows a conventional operational amplifier (see FIG.  3 ). Referring to FIG. 3, an operational amplifier  100  comprises a differential amplifier stage  1 , a current mirror stage  2 , and a buffer circuit  3 . The differential amplifier stage  1  includes first and second differential amplifier circuits  1   a ,  1   b , respectively, arranged symmetrically with respect to a transverse center line of the circuit. The current mirror stage  2  comprises first and second current mirror circuits  2   a ,  2   b , respectively, arranged symmetrically with respect to a transverse center line of the circuit. The buffer circuit  3  is connected to the common output of the current mirror circuits  2   a ,  2   b.    
     The first differential amplifier circuit  1   a  is formed of a pair of NPN transistors Q 1 , Q 2 . The second differential amplifier circuit  1   b  is formed of a pair of PNP transistors Q 3 , Q 4 . The first current mirror circuit  2   a  comprises three PNP transistors Q 5 , Q 6 , and Q 7 . The second current mirror circuit  2   b  is made up of three NPN transistors Q 8 , Q 9 , and Q 10 . The buffer circuit  3  has a diamond arrangement, and includes two NPN transistors Q 11 , Q 13 , and two PNP transistors Q 12 , Q 14 . The buffer circuit is also provided with a PNP transistor Q 15  and an NPN transistor Q 16  which act as current sources. Transistors Q 11 , Q 12  are first and second input transistors, respectively, and transistors Q 13 , Q 14  are first and second output transistors, respectively. 
     In the above arrangement, the bases of transistors Q 1 , Q 3  (which are taken from the first and second differential amplifier circuits  1   a ,  1   b , respectively) are connected to a positive-phase input terminal IN 1 . The bases of the remaining transistors Q 2 , Q 4 , are connected to a negative-phase input terminal IN 2 . The collector of transistor Q 1  is the output of the first differential amplifier circuit  1   a , and is connected to the input of the first current mirror circuit  2   a . The collector of transistor Q 2  is connected to a positive power source +Vcc. The emitters of transistors Q 1 , Q 2  are directly tied together and are connected to a first constant current circuit  4   a . Further, the collector of transistor Q 3  is the output of the second differential amplifier circuit  1   b , and is connected to the input of the second current mirror circuit  2   b . The collector of transistor Q 4  is connected to a negative power source −Vcc. The emitters of transistors Q 3 , Q 4  are directly tied together and are connected to a second constant current circuit  4   b . The collectors of transistors Q 7 , Q 10  (which are the outputs of the first and second current mirror circuits  2   a ,  2   b , respectively) are connected to the positive and negative power sources +Vcc, −Vcc, respectively through respective phase compensating capacitors C 1 , C 2 . In addition, the collectors of transistors Q 7  and Q 10  are directly tied together and connected to the input of the buffer circuit  3 . 
     In the buffer circuit  3 , transistors Q 15 , Q 16  are used as current sources for transistors Q 11 , Q 12 , respectively. More particularly, the collector of transistor Q 15  is connected to a node between the emitter of transistor Q 12  and the base of transistor Q 13 . The emitter of transistor Q 15  is connected to the positive voltage +Vcc, and the base of transistor Q 15  is connected to the bases of transistors Q 5 , Q 6  (which are directly tied together) in the second current mirror circuit  2   a . The collector of transistor Q 16  is connected to a node between the emitter of transistor Q 11  and the base of transistor Q 14 . The emitter of transistor Q 16  is connected to the negative voltage −Vcc, and the base of transistor Q 16  is connected to the bases of transistors Q 8 , Q 9  (which are directly tied together) in the current mirror circuit  2   b . Thus, the buffer circuit  3  is controlled with the operating current flowing in the current mirror stage  2 , depending on an input signal voltage. 
     For the operational amplifier  100  described above to operate at a high speed and over a wide bandwidth, it is necessary to increase the mutual conductance of the differential amplifier stage  1  (i.e., converting a voltage in a current). To increase the mutual conductance of the differential amplifier stage  1 , one must increase a current flowing in the differential amplifier stage  1 . 
     In the above-described arrangement of the conventional operational amplifier  100 , the increase of current flowing in the differential amplifier stage  1  is accomplished by enhancing the increasing change-ratio of current flowing in the first current mirror circuit  2   a  of the current mirror stage  2 , and enhancing the decreasing change-ratio of current flowing in the second current mirror circuit  2   b . As a result, the increasing change-ratio of the current in the first current mirror circuit  2   a  cannot be processed in the buffer circuit  3 . The current which cannot be processed in the buffer circuit  3  begins to flow into the second current mirror circuit  2   b  in which the current is reduced. Accordingly, the second current mirror circuit  2   b  becomes saturated and cannot normally operate. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to solve the above-described problems and to provide an operational amplifier in which a buffer circuit has a reduced input impedance and is capable of processing an increased amount of current. 
     According to the present invention, there is provided an operational amplifier which includes a differential amplifier stage having a positive input terminal and a negative input terminal, formed of a pair of differential amplifier circuits, a current mirror stage formed of a pair of current mirror circuits and connected to the outputs of the differential amplifier stage, and a buffer circuit having current sources connected to the common output of the current mirror stage, wherein the buffer circuit includes a plurality of first input transistors connected in parallel and a plurality of second input transistors connected in parallel. 
     Preferably, the buffer circuit further includes a first output transistor and a second output transistor, and has a diamond arrangement formed of the first output transistor, the second output transistor, at least one of the plurality of first input transistors, and at least one of the plurality of second input transistors. 
     More preferably, the remainder of the plurality of first input transistors and the remainder of the plurality of second input transistors are directly tied together and connected to the output. 
     In the operational amplifier of the present invention, since the buffer circuit includes the plurality of first input transistors and the plurality of second input transistors, the respective impedances of the plurality of first input transistors and the plurality of second input transistors are in parallel with each other. Thus, the input impedance of the buffer circuit is reduced. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of an operational amplifier according to a first embodiment of the present invention; 
     FIG. 2 is a circuit diagram of an operational amplifier according to a second embodiment of the present invention; and 
     FIG. 3 is a circuit diagram of a conventional operational amplifier. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. In the drawings, the same or like parts as those of the conventional operational amplifier  100  are designated by like reference numerals, and the detailed description of the parts is omitted. 
     In FIG. 1, there is shown a circuit diagram of an operational amplifier  10  according to an embodiment of the present invention. A buffer circuit  30  as an element of the operational amplifier  10  includes two first input transistors Q 17 , Q 21  connected in parallel (i.e., having the respective emitters, collectors, and bases directly tied together) and two second input transistors Q 18 , Q 22  also connected in parallel. In the buffer circuit  30 , the first input transistors Q 17 , Q 21 , the second input transistors Q 18 , Q 22 , and the first and second output transistors Q 19 , Q 20  form a diamond arrangement. Transistors Q 23  and Q 24  are used as respective current sources for the first input transistors Q 17  and Q 21  and for the second input transistors Q 18  and Q 22 . 
     Since the buffer circuit  30  includes the plurality of first input transistors Q 17 , Q 21 , in parallel and the plurality of second input transistors Q 18 , Q 22  in parallel, a current which flows in the buffer circuit  30  from the current mirror stage  2  can be divided to flow in the parallel-connected first input transistors Q 17 , Q 21  and in the parallel-connected second input transistors Q 18 , Q 22 . As a result, the quantity of current processable in the buffer circuit  30  can be increased. Hence, the mutual conductance of the differential amplifier stage  1  which converts a voltage into a current can be enhanced. Therefore, the operational amplifier  10  can operate at a high speed and over a wide bandwidth. This high speed and wide bandwidth operation can be achieved with high stability and without a significant increase in current consumption by the buffer circuit  30 . 
     In addition, the impedances of the first input transistors Q 17 , Q 21  and the second input transistors Q 18 , Q 22  are in parallel, which reduces the input impedance (R) of the buffer circuit  30 . Thus, the first pole frequency (1/RC: a phase lag of 45°) at which the gain begins to roll off is shifted toward higher frequencies. Thus, an operational amplifier operating over a wide bandwidth is realizable in the amplifier  10  of the present invention. 
     Moreover, since the combined base resistances of the first input transistors Q 17 , Q 21  and the second input transistors Q 18 , Q 22  are reduced, the cut-off frequency (fc) of the plurality of first and second input transistors Q 17 , Q 21  and Q 18 , Q 22  (fc=k 1 /[2π·r b ·[C j +C′]], where r b  is a combined base resistance, C j  is a junction capacitance, C′ is a parasitic capacitance or phase compensating capacitance, and k 1  is a proportional constant) is shifted toward higher frequencies. Thus, the operational amplifier  10  functions over wider bandwidths. In addition, since the second pole frequency of the operational amplifier  10  (i.e., the frequency at which the phase lag is inversely proportional to the combined base resistance r b  becomes −180°) is enhanced, the phase margin increases. In addition, the through rate (k 2 /[r b ·[C j +C′]], where k 2  is a proportional constant) is enhanced. 
     Moreover, since the first input transistors Q 17 , Q 21 , the second input transistors Q 18 , Q 22 , and the first and second output transistors Q 19 , Q 20  form a diamond arrangement, all of the first and second input transistors Q 17 , Q 21  and Q 18 , Q 22 , and the first and second output transistors Q 19 , Q 20  in the buffer circuit  30  operate as an emitter follower (common-collector). Accordingly, the operational amplifier  10  exhibits improved high frequency performance, has improved skew characteristics, and can operate with stability over a wide bandwidth. 
     FIG. 2 is a circuit diagram of an operational amplifier  20  according to another embodiment of the present invention. The buffer circuit  31  of the operational amplifier  20  includes two first input transistors Q 25 , Q 34  having their bases and emitters connected in parallel. The buffer circuit  31  also includes two second input transistors Q 26 , Q 35  having their bases and emitters connected in parallel. In the buffer circuit  31 , first input transistor Q 25 , second input transistor Q 26 , and first and second output transistors Q 27 , Q 28  form a diamond arrangement. Transistors Q 29  and Q 33  are used as respective current sources for the first input transistors Q 25  and Q 34  and for the second input transistors Q 26  and Q 35 . 
     The collector of the other first input transistor Q 34  and the collector of the other second input transistor Q 35  are directly tied together and connected to the output (OUT). Hence, the collector-emitter voltages of the first input transistor Q 34  and the second input transistor Q 35  are reduced. Accordingly, the current consumption in the buffer circuit  31  is reduced. In correspondence with the reduction of the current consumption, more current can flow in the differential amplifier stage  1  to increase the mutual conductance of the differential amplifier stage  1 . Thus, the through rate of the operational amplifier  20  is further enhanced. 
     The through rates and the phase margins of the operational amplifier  10  of one embodiment (FIG.  1 ), the operational amplifier  20  (FIG. 2) of another embodiment, and the conventional operational amplifier  100  (FIG. 3) were calculated and the results are shown in Table 1. 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                                               TABLE 1 
               
               
                   
                   
               
               
                   
                                operational 
                 operational 
                 operational 
               
               
                   
                 amplifier 10 
                 amplifier 20 
                 amplifier 100 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                    through rate 
                 193 
                 211 
                 165 
               
               
                   
                 (V/#s) 
               
               
                   
                 phase margin 
                 26.4 
                 26.3 
                 16.6 
               
               
                   
                 [deg] 
               
               
                   
                   
               
             
          
         
       
     
     As may be seen in Table 1, the phase margin and the through rate of the operational amplifier  10  of one embodiment is improved over the conventional operational amplifier  100 . The operational amplifier  20  of the other embodiment exhibits even better through rate characteristics. 
     In the above-description of the operational amplifiers according to the embodiments of the present invention, two first input transistors and two second input transistors are connected in parallel, respectively. However, the numbers of the first and second input transistors may be further increased, provided that the first and second input transistors are connected in parallel, respectively. As the number of input transistors is increased, the input impedance of the buffer circuit is correspondingly and advantageously decreased. 
     According to an aspect of the present invention, the buffer circuit includes a plurality of first input transistors connected in parallel and a plurality of second input transistors connected in parallel. A current which flows in the buffer circuit from the current mirror stage can be divided to flow in the plurality of first input transistors and in the plurality of second input transistors. Accordingly, the quantity of current capable of being processed in the buffer circuit can be increased. The mutual conductance of the differential amplifier stage in which a voltage is converted into a current can thus be enhanced. Therefore, the operational amplifier can operate at high speeds and over wide bandwidths. Further, the operational amplifier exhibits high speed and wide bandwidth operation without requiring a significant increase in the current consumption by the buffer circuit. 
     Moreover, the respective impedances of the plurality of first input transistors and the plurality of second input transistors are in parallel, resulting in a reduced input impedance of the buffer circuit. Hence, the first pole frequency at which the gain begins to roll off (45° phase lag) is shifted toward higher frequencies and, thus permits wide bandwidth operation. 
     In addition, since the respective plurality of first input transistors and plurality of second input transistors are connected in parallel, the respective combined base resistances are reduced. Since the cut-off frequencies of the plurality of first input transistors and the plurality of second input transistors are shifted toward higher frequencies, the operational amplifier exhibits wide band-width operation. In addition, the phase margin and the through rate of the operational amplifier, which are inversely proportional to the combined base resistance, can be enhanced. 
     According to another aspect of the present invention, the buffer circuit has a diamond arrangement formed of at least one of the plurality of first input transistors, at least one of the plurality of second input transistors, and the first and second output transistors. Thus, the first and second input transistors and the first and second output transistors in the diamond arrangement operate as emitter followers (common-collectors). Hence, the high frequency characteristics of the operational amplifiers  10 ,  20  are enhanced, and the skew is also improved. Wide bandwidth operation can be achieved with stability. 
     According to still another aspect of the present invention, the remainder of the parallel-connected plurality of first input transistors and the remainder of the parallel-connected plurality of second input transistors are directly tied together and connected to the output. Hence, the collector—emitter voltages of the remainder of the plurality of first input transistors and the remainder of the plurality of second input transistors are reduced. As a result, the current consumption in the buffer circuit is reduced. In correspondence with the reduced current consumption, more current can flow in the differential amplifier stage, thereby increasing the mutual conductance of the differential amplifier stage. Thus, the through rate of the operational amplifier is enhanced. 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.