Abstract:
A silicon wafer having a distributed Bragg reflector buried within it. The buried reflector provides a high efficiency, readily and accurately manufactured reflector with a body of silicon. A photodetector using the buried layer to form a resonant cavity enhancement of the silicon&#39;s basic quantum efficiencies and selectivity is provided. The DBR is created by bonding of two or more substrates together at a silicon oxide interface or an oxide-oxide interface. In the former, an hydrogen implant is used to cleave silicon just above the bond line. In the latter, the bonding is at the oxide layers.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is a continuation of U.S. application Ser. No. 10/009,386 filed Nov. 5, 2001 entitled, REFLECTIVE LAYER BURIED IN SILICON AND METHOD OF FABRICATION, the whole of which is hereby incorporated by reference herein. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002] The present invention was funded in whole or in part by Government Support under Contract Number DAAD17-99-2-0070 awarded by the Army Research Laboratory. The Government has certain rights in the invention. 
     
    
     
       FIELD AND BACKGROUND OF THE INVENTION  
         [0003]    The advent of high speed communications links using chains of photodetectors and emitters has increased the pressure to find a low cost, quantum efficient detector with high speed capability. Silicon has been the material of choice for such detectors. The need for sensitivity implies greater silicon thickness but that is met with increased noise and reduced bandwidth.  
           [0004]    The present invention has the goal of providing a buried reflector in a silicon wafer. The buried layer has particular advantage in providing a more cost effective and efficient photodetector assembly using silicon as the light detecting material. Silicon is advantageous because its micromechanical processing is well established and understood, and thus efficient. In the construction of photodetectors of silicon it is normally desired to overcome the relatively low photon absorption of silicon through the use two reflecting surfaces separated by the silicon to provide a Fabry-Perot cavity and enhanced sensitivity and selectivity. The realization of such a cavity structure has been hampered by the fact that in conventional silicon processing, the cavity dimensions, which define selectivity and wavelength, have been hard to control.  
         SUMMARY OF THE INVENTION  
         [0005]    The present invention provides a reflective layer buried in silicon. The buried layer is provided as a Distributed Bragg Reflector (DBR). This reflective layer has particular advantage for use in a silicon based photodetector using resonant cavity enhancement of the silicon&#39;s basic quantum efficiencies and selectivity using the buried, distributed Bragg reflector (DBR) formed in the silicon cavity.  
           [0006]    The DBR is created by bonding of two or more substrates together at a silicon oxide interface or oxide interface. In the former, an hydrogen implant is used to cleave silicon just above the bond line. In the latter, the bonding is at the oxide layers. In the former, after the steps are repeated to achieve a desired number of alternating silicon and oxide layers, a conducting layer is implanted, an epitaxial layer is grown and then another conducting implant. Finally metalizations are applied to and through the surface and a window through the oxide provided for the admittance of light.  
           [0007]    In the latter case, two oxide topped wafers are joined, repeatedly to get the desired number of alternating layers. The first bonding has one layer given an implant of a dopant to impart conductivity. 
       
    
    
     DESCRIPTION OF THE DRAWING  
       [0008]    These and other features of the invention are more fully set forth below and in the accompanying drawing of which:  
         [0009]    [0009]FIG. 1 is a graph illustrating the performance enhancement of a photodetector using the present invention;  
         [0010]    [0010]FIG. 2 is a diagram of a photodetector structure using a buried layer according to the invention;  
         [0011]    [0011]FIG. 3-24 illustrate one method of forming the buried layer and its application to a photodetector according to the present invention;  
         [0012]    [0012]FIGS. 25-31 illustrate an alternative method of forming a buried layer  
         [0013]    [0013]FIG. 32 illustrates the invention used with on-chip electronics and optionally in an array of photodetectors. 
     
    
     DETAILED DESCRIPTION  
       [0014]    The present invention provides a distributed Bragg reflector (DBR) as a reflective layer in a silicon wafer. The reflective layer is shown in an application for use as a photodetector assembly. The reflective layer provides for an enhanced Fabry-Perot, resonant cavity response to incident light. The buried layer comprises alternating silicon and silicon dioxide layers which form the distributed Bragg reflector (DBR).  
         [0015]    The invention provides a buried DBR reflector which in its application to a photodetector acts to improve the quantum efficiency of a silicon light detector relative to a detector without the buried reflector. FIG. 1 illustrates graphically the improvement in efficiency as a function of the buried reflectance for silicon of different αd (absorption coefficient, silicon depth product) values showing a great improvement over regular or conventional detectors without the buried layer. FIG. 2 illustrates the basic structure of the invention in a photodetector in which a silicon body  12  has a buried DBR layer  14  comprising alternating silicon dioxide  16  and silicon layers  18  spaced to provide a Fabry-Perot cavity in the silicon  12 . To create a photodetector from the buried DBR  14  a top reflective surface is formed with the interface of the silicon  12  and the air environment.  
         [0016]    A preferred method for the fabrication of the buried layer  14  of FIG. 2 is illustrated with respect to FIGS. 3-13. The photodetector application is then illustrated in FIGS. 11-24. In FIG. 3 a wafer of silicon  20  has an oxide layer  22  thereon. Dimensions are given in the figures for purposes of an example for a photodetector selected to respond selectively to light distributed around 850 nm (+/− nearly 100 nm), but the invention is not limited to any particular wavelength. In this case the silicon dioxide is 437 nm in depth. Hydrogen atoms are implanted through the oxide to form a thin layer  25  at an exemplary depth of 611 nm with a dosage of, for example only, 2×10 16  cm −2  to 1×10 17  cm −2  and thus and thus are placed in the silicon below the oxide as shown in FIG. 4 a . A second silicon body  26  is provided in FIG. 4 b  and the oxide layer  22  is thermally bonded onto the top of this layer  26 . The thermal bonding, typically at 600 degrees C., cleaves the boundary between the hydrogen and no hydrogen containing silicon, leaving a 174 nm silicon layer  28  on top of the oxide  24  as shown in FIG. 5. Final bonding at 1000 degrees C. is then performed. The top silicon layer  28  is mechanically polished to achieve the result of FIG. 6.  
         [0017]    Additional layers are created by continuing the above process until the desired layer structure is achieved. FIG. 7 illustrates the provision of a further body of silicon  30  having an oxide layer  32  as shown in FIG. 3. FIG. 8A illustrates the addition of an hydrogen layer  34  as above which is then bonded to the layer of FIG. 6, reproduced as FIG. 8B to achieve the bonded and cleaved wafer of FIG. 9. For the exemplary case of an 850 nm detector, a layering of hydrogenated silicon and oxide layers of 174 and 437 nm thickness is achieved. This can be repeated as many time as desired to achieve a multilayered DBR  35  shown in FIG. 10, but a DBR of two oxide layers (1.5 pairs of silicon and silicon dioxide) has been found to be an advantageous cost/performance compromise. The top layer  34  is typically mechanically polished in producing the final wafer of FIG. 10.  
         [0018]    The top silicon layer  34  is implanted or otherwise provided with a n+ arsenic doping to provide an n-type semiconductivity to it. On top of it an epitaxial layer  36  is grown, for example, to a depth of 4,826 nm, FIG. 12, and a top layer  38  is oxidized to a depth of 500 nm, FIG. 13. Because of the silicon expansion upon oxidation, this leaves 5 μm of silicon.  
         [0019]    The invention thus shown has advantage in being able to produce uniform and accurate thickness of the burried layers insuring uniformity of performance of different units. The silicon body can also be manufactured as a single crystal layer as can the intervening silicon layers be made single crystal avoiding optical effects at crystal interfaces. The technique provided above also uses silicon fabrication techniques which are well established and understood. The invention also can create thicknesses of widelt varying relative thickness between the insulator and silicon layers. In particular it is desirable for optimal reflectivity to have them of the same optical path length as above. It is thus possible to achieve high efficiency reflectance with a minimum of layers as discussed elsewhere.  
         [0020]    The fabrication of a photodetector using the buried layer of the invention is now illustrated in FIGS. 14-24. Thereafter, and as shown in FIG. 14, the oxide layer  38  is apertured by any well known procedure to expose a surface region  40  of the detector for the admittance of light and a p+ region  42  of dopant created to complete the electrode structure.  
         [0021]    To provide electrical connection to the regions  34  and  42 , the oxide layer  38  is regrown across the entire detector, FIG. 16, and a small aperture  44  off to the side of the region  42  opened in it. A deep etch  46  is made to a level  48  just above the n+ layer  34 , FIG. 18. An n+ dopant is implanted in the region  50  between the opening  46  and the n+ layer  34 , as shown in FIG. 20. Next an entire top layer  52  of oxide is grown or otherwise formed on the surface, FIG. 21, and then etched to open accesses  56  and  54  to the regions  50  and  42  respectively as shown in FIG. 22. Metalizations  60  and  58  are then deposited to provide connection from the regions  50  and  42  to the surface of the oxide layer  52 , FIG. 23. Finally as shown in FIG. 24, a light admitting aperture  62  is etched in the oxide layer  52  in the area of region  42  creating an upper reflecting layer and completing the photodetector. A bias source  64  would be provided for operation in light detection, the current drawn thereby being an indication of incident light.  
         [0022]    Formation of the DBR layer may alternatively be as shown in FIGS. 25-31. The process begins with first and second wafers as shown in FIGS. 25 and 26. Each has a buried oxide layer, layers  70  and  72  respectively, which is a wafer form generally available in industry. On each, an oxide layer, layers  74  and  76 , are formed, all with the exemplary dimensions given for 850 nm sensitivity and selectivity. An n+ dopant is implanted through the layer  76  into a region  80  at an exemplary density of 1×10 19  cm −3  of the underlying silicon region  78 , FIG. 27. The surface oxide is then stripped, a new oxide grown as a wet H 2 O process at 950 degrees C. for typically ten minutes. The layers  74  and  76  are then brought into contact, FIG. 28, and bonded while being heated to a bonding temperature, FIG. 29. The silicon is mechanically etched as by polishing to leave a thin silicon layer, FIG. 29, which is then removed along with the oxide layer  72  leaving a silicon layer  78  on top of a DBR structure, FIG. 30. A layer  84  of oxide is then created on the silicon layer  78 , FIG. 31, and creation of a top layer electrode and metalization connection can proceed as before.  
         [0023]    In FIG. 32 there is shown a silicon chip having a buried reflector device according to the invention used in a phtotdetector  92 . On-chip electronices  94  are provided to process signals from and energize the photodetector  92  for the provision of an output signal reflecting incident light. An array of photodetectors  96  can also be provided in association with the electronics  94  to detect light in two dimensions. The individual photodetectors may have buried layers of different dimensions tailered to respond to different frequencies of light as well.  
         [0024]    The various layers described above which are fabricated above the DBR of the invention, or different layers, may be treated with additives of given properties that provide specific frequency characteristics, such as IR sensitivity, to a photodetector thus formed. These layers may include a SiGe absorption region, SiGe/Si quantum well absortpion region, or metal semiconductor internal photoemission (Schottky) type absorption using metal such as Pt, Ir, Pd pr Ni.  
         [0025]    It is to be noted that the above described examples use dimensions for wavelengths which are exemplary only and which create no limits on the invention except as claimed.