Abstract:
An in-plane switching mode liquid crystal display device includes: a gate line on a substrate along a first direction; a data line crossing the gate line along a second direction to define a pixel region; a gate electrode connected to the gate line; a semiconductor layer over the gate electrode; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a common line spaced apart from the gate line and disposed along the first direction; a common electrode connected to the common line, the common electrode having a first common electrode pattern and a second common electrode pattern extending from the first common electrode pattern in the pixel region; an auxiliary common electrode extending from the common line, the auxiliary common electrode having a first protrusion pattern overlapping with an end portion of the second common electrode pattern, the first protrusion in parallel with the second common electrode pattern; a pixel electrode connected to the drain electrode, the pixel electrode having a first pixel electrode pattern and a second pixel electrode pattern extending from the first pixel electrode pattern in the pixel region; and an auxiliary pixel electrode extending from the drain electrode, the auxiliary pixel electrode having a second protrusion pattern overlapping an end portion of the second pixel electrode pattern, the second protrusion pattern in parallel with the second pixel electrode pattern.

Description:
[0001]    This application claims the benefit of Korean Patent Application No. 10-2006-0102237, filed on Oct. 20, 2006, which is hereby incorporated by reference for all purposes as if fully set forth herein. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field Of The Invention 
         [0003]    The present invention relate to an in-plane switching (IPS) mode liquid crystal display (LCD) device, and more particularly, to an array substrate for an IPS mode LCD device that can obtain a high aperture ratio and a high brightness. 
         [0004]    2. Discussion Of The Related Art 
         [0005]    The conventional LCD devices use an optical anisotropic property and polarization properties of liquid crystal molecules to display images. The liquid crystal molecules have orientation characteristics of arrangement resulting from their thin and long shape. Thus, an arrangement direction of the liquid crystal molecules can be controlled by applying an electrical field to them. Accordingly, when the electric field is applied to them, polarization properties of light is changed according to the arrangement of the liquid crystal molecules such that the LCD devices display images. 
         [0006]    Among the known types of LCD devices, active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) arranged in a matrix form, are the subject of significant research and development because of their high resolution and superior ability in displaying moving images. 
         [0007]    The LCD device includes a first substrate, a second substrate and a liquid crystal layer interposed therebetween. A common electrode and a pixel electrode are respectively formed on the first and second substrates. The first and second substrates may be referred to as a color substrate and an array substrate, respectively. The liquid crystal layer is driven by a vertical electric field induced between the common and pixel electrodes. The LCD device has excellent transmittance and aperture ratio. 
         [0008]    However, the LCD device using a vertical electric field has a narrow viewing angle. To overcome this problem, an IPS mode LCD device having a wide viewing angle is suggested. 
         [0009]      FIG. 1  is a schematic cross-sectional view of an IPS mode LCD device according to the related art. As shown in  FIG. 1 , the IPS mode LCD device I includes an array substrate “AS,” a color filter substrate “CS” and a liquid crystal layer “LC.” The array substrate “As” and the color filter substrate “CS” face each other, and the liquid crystal layer “LC” is interposed therebetween. The array substrate “AS” includes a first substrate  10  including a pixel regions “P,” a thin film transistor “T,” a plurality of common electrodes  18  and a plurality of pixel electrodes  32 . The thin film transistor “T,” the plurality of common electrodes  18  and the plurality of pixel electrodes  32  are formed in the pixel region “P.” The thin film transistor “T” is disposed in the pixel region “P” and includes a gate electrode  12 , a semiconductor layer  22 , a source electrode  24  and a drain electrode  26 . The source and drain electrodes  24  and  26  are spaced apart from each other. 
         [0010]    Although not shown, a gate line connected to the gate electrode  12  is formed along a first direction on the first substrate  10 , and a data line connected to the source electrode  24  along a second direction on the first substrate  10 . The gate line crosses the data line to define the pixel region “P.” In addition, although not shown, a common line, which is connected to the plurality of common electrodes  18  and parallel to the gate line, is formed along the first direction on the first substrate  10 . The common electrode  18  is formed with the same material at the same layer as the gate electrode  12 , and the pixel electrode  32  includes a transparent conductive material. 
         [0011]    The color filter substrate “CS” includes a second substrate  40 , a black matrix  42  and a color filter layer  44 . The black matrix  42  shields portions except for the plurality of pixel regions “P.” The color filter layer  44  is formed on the black matrix  42  and corresponds to the plurality of pixel regions “P.” Particularly, the color filter layer  44  including a red sub-color filter  44   a , a green sub-color filter  44   b  and a blue sub-color filter (not shown). 
         [0012]    The liquid crystal layer “LC” is driven by a horizontal electric field (not shown) induced between each common electrode  18  and each pixel electrode  32 . 
         [0013]    Further, a gate insulating layer  20  and a passivation layer  31  are disposed between the common electrode  18  and the pixel electrode  32 . At this time, at a step difference due to the gate insulating layer  20  and the passivation layer  31  interposed between the common electrode  18  and the pixel electrode  32 , liquid crystal molecules of the liquid crystal layer “LC” may be abnormally arranged because of electric field distortion at the step difference. Therefore, the electric field distortion causes disclination. To solve the problem, a structure that the common electrode is formed with the same material at the same layer as the pixel electrode without any step difference therebetween is suggested. 
         [0014]      FIG. 2A  is a schematic plan view of an array substrate for an IPS mode LCD device with respect to one pixel region according to the related art, and  FIG. 2B  is a schematic cross-sectional view taken along a line “IIb-IIb” of  FIG. 2A  according to the related art. 
         [0015]    In  FIGS. 2A and 2B , a gate line  52  and a data line  68  crossing the gate line  52  are formed in a substrate  50  to define a pixel region “P.” A thin film transistor “T” is formed at crossing of the gate and data lines  52  and  68  and includes a gate electrode  54 , an active layer  60 , a source electrode  64  and a drain electrode  66 . A common electrode  74  and a pixel electrode  72  are disposed in the pixel region “P.” Specifically, the common electrode  74  includes a first common electrode pattern  74   a  and a second common electrode pattern  74   b  diverged from the first common electrode pattern  74   a , and the pixel electrode  72  includes a first pixel electrode pattern  72   a  and a second pixel electrode pattern  72   b  diverged from the first pixel electrode pattern  72   a.  In particular, the second common electrode pattern  74   b  and the second pixel electrode pattern  72   b  are alternately arranged with each other in the pixel region “P” to generate a horizontal electric field (not shown). The common electrode  74  is connected to a common line  73  parallel with the gate line  52 , and the pixel electrode  72  is connected to the drain electrode  66 . An auxiliary common electrode  56  extends from the common line  73  and includes first to fourth auxiliary common electrode patterns  56   a ,  56   b ,  56   c  and  56   d  having a tetragonal frame shape. 
         [0016]    Here, the first auxiliary common electrode pattern  56   a  as a first capacitor electrode, the first pixel electrode pattern  72   a  as a second capacitor electrode with a gate insulating layer  57  and a passivation layer  69  therebetween as insulators constitute a storage capacitor “Cst.” 
         [0017]    According to the related art, to obtain a large capacity by increasing the size of the storage capacitor “Cst,” the first auxiliary common electrode  56   a  and the first pixel electrode pattern  72   a  are manufactured with a relative large size. Therefore, the aperture region is reduced, so it is difficult to obtain a high aperture ratio, a high brightness and a high resolution. 
         [0018]    In addition, because the common electrode  74  and the pixel electrode  72  are formed with the same material at the same layer as each other, the common electrode  74  and the pixel electrode  72  should have a predetermined distance with each other to prevent shorting defect between the common electrode  74  and the pixel electrode  72 . In particular, the shorting defect may be generated at gap spaces between an end portion of the second common electrode pattern  74   b  and the first pixel electrode pattern  72   a  and between an end portion of the second pixel electrode pattern  72   b  and the first common electrode pattern  74   a.    
         [0019]    In particular, horizontal electric fields between the first common electrode pattern  74   a  and the second pixel electrode pattern  72   b  and between the second common electrode pattern  74   b  and the first pixel electrode pattern  72   a  are easily distorted, so there is a problem that the horizontal electric fields badly affects movement of the liquid crystal molecules of the liquid crystal layer “LC.” 
         [0020]      FIG. 3  is an expanded plan view regarding an area “III” of  FIG. 2A  according to the related art. 
         [0021]    In  FIG. 3 , two second common electrode patterns  74   b  are diverged from the first common electrode pattern  74   a  along the second direction. The second pixel electrode pattern  72   b  is disposed between the two second common electrode patterns  74   b  to be in parallel with each other. Further, an end portion of the second pixel electrode pattern  72   b  is spaced apart from the first common electrode pattern  74   a  to prevent a shorting defect as above. 
         [0022]    Therefore, although a first horizontal electric field “F 1 ” between the second common electrode pattern  74   a  and the second pixel electrode pattern  72   b  in a main portion of the pixel region “P” is normally generated, a second horizontal electric field “F 2 ” between an end portion of the second pixel electrode pattern  72   b  and the first common electrode pattern  74   a  is electrically distorted. 
         [0023]    As a result, because first and second arrangement features of the liquid crystal molecules in accordance with the first and second horizontal electric fields “F 1 ” and “F 2 ” are different from each other, optical properties in accordance with the first and second horizontal electric fields “F 1 ” and “F 2 ” are also different from each other. Therefore, for example, brightness property at a peripheral area “LK” is different from that of the main area of the pixel region “P,” so light leakage occur in the peripheral area “LK.” 
         [0024]    As a result, the peripheral area “LK” should be shielded to prevent reducing an image quality, so the aperture region is reduced. Consequently, the aperture ratio, the brightness, and the resolution are reduced. 
         [0025]    Further, to obtain an enough capacity, the storage capacitor is manufactured with a relative large size, so it is difficult to obtain a high aperture ratio. 
       SUMMARY OF THE INVENTION 
       [0026]    Accordingly, embodiments of the present invention are directed to an array substrate for an IPS mode LCD device and a method of fabricating the same that substantially obviates one or more problems due to limitations and disadvantages of the related art. 
         [0027]    An object of the present invention is to provide an array substrate for an IPS mode LCD and a method of fabricating the same that obtain a desired aperture region by minimizing a light leakage and reducing a size of a storage capacitor without loss of the capacity. 
         [0028]    Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
         [0029]    To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an in-plane switching mode liquid crystal display device includes: a gate line on a substrate along a first direction; a data line crossing the gate line along a second direction to define a pixel region; a gate electrode connected to the gate line; a semiconductor layer over the gate electrode; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a common line spaced apart from the gate line and disposed along the first direction; a common electrode connected to the common line, the common electrode having a first common electrode pattern and a second common electrode pattern extending from the first common electrode pattern in the pixel region; an auxiliary common electrode extending from the common line, the auxiliary common electrode having a first protrusion pattern overlapping with an end portion of the second common electrode pattern, the first protrusion in parallel with the second common electrode pattern; a pixel electrode connected to the drain electrode, the pixel electrode having a first pixel electrode pattern and a second pixel electrode pattern extending from the first pixel electrode pattern in the pixel region; and an auxiliary pixel electrode extending from the drain electrode, the auxiliary pixel electrode having a second protrusion pattern overlapping an end portion of the second pixel electrode pattern, the second protrusion pattern in parallel with the second pixel electrode pattern. 
         [0030]    In another aspect, a method of fabricating an in-plane switching mode liquid crystal display device includes: forming a gate line, a gate electrode connected to the gate line, a common line, and an auxiliary common electrode extending from the common line and having a first protrusion pattern, the gate line and the common line spaced apart from each other and disposed along a first direction; forming a gate insulating layer on the gate line, the gate electrode, the common line and the auxiliary common electrode; forming a semiconductor layer on the gate insulating layer over the gate electrode; forming a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, a data line connected to the source electrode and crossing the gate line along a second direction to define a pixel region, and an auxiliary pixel electrode extending from the drain electrode and having a second protrusion pattern; forming a passivation layer on the source electrode, the drain electrode, the data line and the auxiliary pixel electrode; and forming a common electrode and a pixel electrode on the passivation layer, the common electrode having a first common electrode pattern and a second common electrode extending from the first common electrode pattern, the pixel electrode having a first pixel electrode pattern and a second pixel electrode pattern extending from the first pixel electrode pattern, the second common electrode pattern and the second pixel electrode pattern alternately disposed in the pixel region, wherein an end portion of the second common electrode pattern overlaps with the first protrusion pattern and an end portion of the second pixel electrode pattern overlaps with the second protrusion pattern, the first protrusion pattern in parallel with the second common electrode and the second protrusion pattern in parallel with the second pixel electrode pattern. 
         [0031]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0032]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings: 
           [0033]      FIG. 1  is a schematic cross-sectional view of an IPS mode LCD device according to the related art; 
           [0034]      FIG. 2A  is a schematic plan view of an array substrate for an IPS mode LCD device with respect to one pixel region according to the related art; 
           [0035]      FIG. 2B  is a schematic cross-sectional view taken along a line “IIb-IIb” of  FIG. 2A  according to the related art; 
           [0036]      FIG. 3  is an expanded plan view regarding an area “III” of  FIG. 2A  according to the related art; 
           [0037]      FIG. 4  is a schematic plan view of an array substrate for an IPS mod LCD device with respect to one pixel region according to an embodiment of the present invention; 
           [0038]      FIGS. 5A and 5B  are expanded plan views of  FIG. 4  according to an embodiment of the present invention; 
           [0039]      FIGS. 6A and 6B  are schematic cross-sectional views taken along lines “VIa-Via” and “VIb-VIb” of  FIG. 5  according to an embodiment of the present invention, respectively; and 
           [0040]      FIGS. 7A to 7E  and  FIGS. 8A to 8E  are schematic cross sectional views showing a manufacturing process of an array substrate for an IPS mode LCD device taken along lines “VII-VII” and “VIII-VIII” according to an embodiment of the present invention, respectively. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0041]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. 
         [0042]      FIG. 4  is a schematic plan view of an array substrate for an IPS mod LCD device with respect to one pixel region according to an embodiment of the present invention. 
         [0043]    In  FIG. 4 , a gate line  102  is formed on a substrate  100  along a first direction, and a data line  126  crosses the gate line  102  along a second direction to define a pixel region “P.” A thin film transistor “T” is formed at crossing of the gate line  102  and the data line  126 . Specifically, the thin film transistor “T” includes a gate electrode  104  connected to the gate line  102 , an active layer  112  on the gate electrode  104 , a source electrode  116  connected to the data line  126  and a drain electrode  118  spaced apart from the source electrode  116 . 
         [0044]    Furthermore, a common line  105  is formed along the first direction and is spaced apart from the gate line  102 . An auxiliary common electrode  106  extends from the common line  105  and includes first to fourth auxiliary common electrode patterns  106   a ,  106   b ,  106   c  and  106   d  having a tetragonal frame shape surrounding the pixel region “P.” Here, the first and second auxiliary common electrode patterns  106   a  and  106   b  and the third and fourth auxiliary common electrode patterns  106   c  and  106   d  are disposed along a crossing direction to each other. That is, the first auxiliary common electrode pattern  106   a  is in parallel with the second auxiliary common electrode pattern  106   b , and the third auxiliary common electrode pattern  106   c  is in parallel with the fourth auxiliary common electrode pattern  106   d.    
         [0045]    A common electrode  134  is connected to the common line  105  and includes a first common electrode pattern  134   a  and a second common electrode pattern  134   b  extending from the first common electrode pattern  134   a  along the second direction. A pixel electrode  132  is connected to the drain electrode  118  and includes a first pixel electrode pattern  132   a  and a second pixel electrode pattern  132   b  extending from the first pixel electrode pattern  132   a  along the second direction. For example, the third and fourth auxiliary common electrode pattern  106   c  and  106   d , the second common electrode pattern  134   b,  and the second pixel electrode pattern  132   b  have a bar shape in the pixel region “P,” respectively. Here, the second common electrode pattern  134   b,  and the second pixel electrode pattern  132   b  are alternately disposed. 
         [0046]    Furthermore, an auxiliary pixel electrode  122  extends from the drain electrode  118  and includes a first auxiliary pixel electrode pattern  122   a , a second auxiliary pixel electrode pattern  122   b  extending from the first auxiliary pixel electrode pattern  122   a  along the second direction, and a third auxiliary pixel electrode pattern  122   c  extending from the second auxiliary pixel electrode pattern  122   b.  Here, the second auxiliary pixel electrode pattern  122   b  acts as an electrode forming a horizontal electric field with adjacent electrodes in the pixel region “P.” For example, the third and fourth auxiliary common electrode patterns  106   c  and  106   d  are disposed at sides of the pixel region “P” and the second auxiliary pixel electrode pattern  122   b  is disposed at a central position of the pixel region “P.” Accordingly, the second common electrode pattern  134   b  and the second pixel electrode pattern  132   b  are disposed between the third auxiliary common electrode pattern  106   c  and the second auxiliary pixel electrode pattern  122   b  and between the fourth auxiliary common electrode pattern  106   d  and the second auxiliary pixel electrode pattern  122   b.    
         [0047]    The auxiliary common electrode  122  further includes a fifth auxiliary common electrode pattern  106   e  overlaps an end portion of the second common electrode pattern  134   b  to be in parallel with each other. The auxiliary pixel electrode  122  further includes a fourth auxiliary pixel electrode pattern  122   d  overlaps with an end portion of the second pixel electrode pattern  132   b  to be in parallel with each other. 
         [0048]    Meanwhile, an overlapped region between the first auxiliary common electrode pattern  106   a  and the first auxiliary pixel electrode pattern  122   a  with a first insulating layer (not shown) therebetween is utilized as a first storage capacitor “Cst1.” Here, the first auxiliary common electrode pattern  106   a  acts as a first capacitor electrode, and the first auxiliary pixel electrode pattern  122   a  acts as a second capacitor electrode. 
         [0049]    In addition, another overlapped regions between the second auxiliary common electrode pattern  106   b  and the third auxiliary pixel electrode pattern  122   c  with a second insulating layer (not shown) and between the third auxiliary pixel electrode pattern  122   c  and the first common electrode pattern  134   a  with a third insulating layer (not shown) are utilized as a second storage capacitor “Cst 2 .” Here, the second auxiliary common electrode pattern  106   b  acts as a first capacitor electrode, the third auxiliary pixel electrode pattern  122   c  acts as a second capacitor electrode, and the first common electrode pattern  134   a  acts as a third capacitor electrode. Although not shown, the first and second insulating layers may be the same insulating layer. Here, the second storage capacitor “Cst 2 ” corresponds to a parallel storage capacitor. 
         [0050]    According to the present invention, the first and second storage capacitors “Cst 1 ” and “Cst 2 ” are disposed at two sides of each pixel region “P,” so the first and second storage capacitors “Cst 1 ” and “Cst 2 ” are increased. However, in the case of the first storage capacitor “Cst 1 ,” only single insulating layer is interposed between the first and second capacitor electrodes. Since the thickness of an insulator of a storage capacitor is in inverse proportion to the amount of a capacity, the size of the first and second storage capacitors “Cst 1 ” and “Cst 2 ” can be reduced without loss of the capacity. 
         [0051]    Consequently, the size of the second storage capacitor “Cst 2 ” adjacent to the thin film transistor “T” and in connection with the aperture ratio can be reduced without loss of the capacity differently from the related art as shown in  FIG. 2A . 
         [0052]      FIGS. 5A and 5B  are expanded plan views of  FIG. 4  according to an embodiment of the present invention.  FIG. 5A  is a view regarding an area “Va” of  FIG. 4 , and  FIG. 5B  is a view regarding another area “Vb” of  FIG. 4 . 
         [0053]    In  FIGS. 5A and 5B , the fifth auxiliary common electrode pattern  106   e  is connected to the common electrode  134  and overlaps with the end portion of the second common electrode pattern  134   b  to be in parallel with each other. Accordingly, a gap space between the second common electrode pattern  134   b  and the first pixel electrode pattern  132   a  can be removed by the fifth auxiliary common electrode pattern  106   e , distortion of the horizontal electric field at the gap space can be solved. Similarly, the fourth auxiliary pixel electrode pattern  122   d  is connected to the pixel electrode  132  and overlaps with the end portion of the second pixel electrode pattern  132   b  to be in parallel with each other. Accordingly, the fourth auxiliary pixel electrode pattern  122   d  can remove another gap space between the second pixel electrode pattern  132   b  and the first common electrode pattern  134   a , so distortion of the horizontal electric field at the other gap space can be also solved. 
         [0054]    In other words, since the common electrode  134  and the pixel electrode  132  are formed through the same process with the same material, the common electrode  134  and the pixel electrode  132  should be spaced apart from each other to prevent a shorting defect. Therefore, light leakage defect may occur at respective end portions of the common electrode  134  and the pixel electrode  132 . To solve the light leakage defect without loss of the aperture region, the auxiliary common electrode  106  insulated with the pixel electrode  132  at a different layer from the common electrode  134  and the auxiliary pixel electrode  122  insulated with the common electrode  134  at another different layer from the pixel electrode  132  are suggested to change abnormal horizontal electric fields into a desired horizontal electric field. 
         [0055]    Consequently, the light leakage defect due to the abnormal horizontal electric field can be reduced, so the aperture region can be increased. That is, a high aperture ratio, a high brightness and a high resolution can be obtained. 
         [0056]      FIGS. 6A and 6B  are schematic cross-sectional views taken along lines “VIa-Via” and “VIb-VIb” of  FIG. 5  according to an embodiment of the present invention, respectively. 
         [0057]    In  FIGS. 6A and 6B , a pixel region “P” including a switching region “S,” a first storage region “C 1 ,” and a second storage region “C 2 ” are defined in a substrate  100 . 
         [0058]    In the switching region “S,” a gate electrode  104 , a gate insulating layer  110  on the gate electrode  104 , an active layer  112  on the gate insulating layer  110 , an ohmic contact layer  114  on the active layer  112 , and source and drain electrode  116  and  118  on the ohmic contact layer  114  constitute a thin film transistor “T.” An auxiliary common electrode pattern  106  is disposed in the pixel region “P” and includes first to fourth auxiliary common electrode patterns  106   a ,  106   b ,  106   c  and  106   d.  An auxiliary pixel electrode  122  extends from the drain electrode  118  and includes first to third auxiliary pixel electrode patterns  122   a ,  122   b  and  122   c . A passivation layer  128  is formed on the auxiliary pixel electrode  122 , and a common electrode  134  and a pixel electrode  132  are formed on the passivation layer  128 . Here, the common electrode  134  includes a first common electrode pattern  134   a  and a second common electrode pattern  134   b  extending from the first common electrode pattern  134   a.  The pixel electrode  132  includes a first pixel electrode pattern  132   a  and a second pixel electrode pattern  132   b  extending from the first pixel electrode pattern  132   a.    
         [0059]    At this time, the auxiliary common electrode  106  further includes a fifth auxiliary common electrode pattern  106   e , and the auxiliary pixel electrode  122  further includes a fourth auxiliary pixel electrode  122   d.  The first auxiliary pixel electrode  122   a  is insulated with the first auxiliary common electrode  106   a  by the gate insulating layer  110  and is insulated with the first pixel electrode pattern  132   a  by the passivation layer  130 . 
         [0060]    The third auxiliary pixel electrode pattern  122   c  is insulated with the second auxiliary common electrode pattern  106   b  by the gate insulating layer  110  and is insulated with the first common electrode pattern  134   a  by the passivation layer  130 . 
         [0061]    Substantially, the fourth auxiliary pixel electrode  122   d  pattern is diverged from the third auxiliary pixel electrode pattern  122   c , and the fifth auxiliary common electrode pattern  106   e  is diverged from the first auxiliary common electrode pattern  106   a.    
         [0062]    In the first storage region “C 1 ,” the first auxiliary common electrode pattern  106   a  acting as a first capacitor electrode, the first auxiliary pixel electrode pattern  122   a  acting as a second capacitor electrode, and the gate insulating layer  110  acting as an insulator between the first auxiliary common pattern  106   a  and the first auxiliary pixel electrode pattern  122   a  constitute a first storage capacitor “Cst 1 .” Furthermore, in the second storage region “C 2 ,” the second auxiliary common electrode pattern  106   b , the third auxiliary pixel electrode pattern  122   c , and the first common electrode pattern  134   a  constitute a second storage capacitor “Cst 2 ” with the gate insulating layer  110  and the passivation layer  128 . 
         [0063]    Specifically, the gate insulating layer  110  as a first insulator is disposed between the second auxiliary common electrode pattern  106   b  and the third auxiliary pixel electrode pattern  122   c , and the passivation layer  130  as a second insulator is disposed between the third auxiliary pixel electrode pattern  122   c  and the first common electrode pattern  134   a.    
         [0064]      FIGS. 7A to 7E  and  FIGS. 8A to 8E  are schematic cross sectional views showing a manufacturing process of an array substrate for an IPS mode LCD device taken along lines “VII-VII” and “VIII-VIII” according to an embodiment of the present invention, respectively. 
         [0065]    In  FIGS. 7A and 8A , a pixel region “P,” a switching region “S,” a first storage region “C 1 ,” and a second storage region “C 2 .” A gate electrode  104 , and a auxiliary common electrode  106  including first to fifth auxiliary common electrode patterns  106   a ,  106   b ,  106   c ,  106   d  and  106   e  are formed by depositing and patterning one of a conductive metallic material group including aluminum (Al), aluminum alloy, chromium (Cr), molybdenum (Mo), copper (Cu), and titanium (Ti) on the substrate  100 . Although not shown, the first to fourth auxiliary common electrode patterns  106   a ,  106   b ,  106   c  and  106   d  have a tetragonal frame shape and the fifth auxiliary common electrode pattern  106   e  extends from the first auxiliary common electrode pattern  106   a.  Here, the first auxiliary common electrode pattern  106   a  is disposed in the first storage region “C 1 ,” and the second auxiliary common electrode pattern  106   b  is disposed in the second storage region “C 2 .” Although not shown, in this step, the auxiliary common electrode  106  is connected to a common line (not shown) by extending from the common line, and the gate electrode  104  is connected to a gate line that is formed along a first direction. Here, the common line is also formed along the first direction and is spaced apart from the gate line. 
         [0066]    In  FIGS. 7B and 8B , a gate insulating layer  110  is formed by depositing one of an inorganic insulating material group including silicon nitride (SiNx) and silicon oxide (SiOx) on the gate electrode  104  and the auxiliary common electrode  106 . Sequentially, an active layer  112  and an ohmic contact layer  114  are formed by depositing an intrinsic amorphous silicon material (a-Si:H) and a doped amorphous silicon material (n+a-Si:H) on the gate insulating layer  110 , respectively. 
         [0067]    In  FIGS. 7C and 8C , a source electrode  116 , a drain electrode  118  spaced apart from the source electrode  116 , and an auxiliary pixel electrode  122  extending from the drain electrode  118  and including first to fourth auxiliary pixel electrode patterns  122   a ,  122   b  and  122   c  are formed by depositing and patterning one of the mentioned conductive metallic material group on the ohmic contact layer  114 . Although not shown, the fourth auxiliary pixel electrode pattern  122   d  extends from the third auxiliary pixel electrode pattern  122   c.  Further, although not shown, a data line is connected to the source electrode  116  and cross the gate line along a second direction to define the pixel region “P.” 
         [0068]    Next, a portion of the ohmic contact layer  114  exposed between the source and drain electrodes  116  and  118  is removed to expose a portion of the active layer  112  corresponding to the portion of the ohmic contact layer  114 . 
         [0069]    In  FIGS. 7D and 8D , a passivation layer  128  is formed by depositing or coating an inorganic insulating material or an organic insulating material on the source and drain electrodes  116  and  118 , and the auxiliary pixel electrode  122 . Next, a first contact hole (not shown) exposing a portion of the first auxiliary pixel electrode pattern  122   a  is formed by etching the passivation layer  128 , and a second contact hole  130  exposing a portion of the third auxiliary common electrode pattern  106   c  is formed by etching the passivation layer  128  and the gate insulating layer  110  under the passivation layer  128 . 
         [0070]    In  FIGS. 7E and 8E , a pixel electrode  132  and a common electrode  134  are formed by depositing and patterning one of a transparent conductive material group including an indium tin oxide (ITO) and an indium zinc oxide (IZO) on the passivation layer  128 . Specifically, the pixel electrode  132  includes a first pixel electrode pattern  132   a  and a second pixel electrode pattern  132   b  extending from the first pixel electrode pattern  132   a , and the common electrode  134  includes a first common electrode pattern  134   a  and a second common electrode pattern  134   b  extending from the first common electrode pattern  134   a.  Here, the second pixel electrode pattern  132   b  and the second common electrode pattern  134   b  are disposed in the pixel region “P.” Although not shown, the second pixel electrode pattern  132   b  and the second common electrode pattern  134   b  are formed along the second direction and have a bar shape. 
         [0071]    The pixel electrode  132  is connected to the auxiliary pixel electrode  122  via the first contact hole (not shown). The common electrode  134  is connected to the auxiliary common electrode  106  via the second contact hole  130  (of  FIG. 8D ). In other words, the common electrode  134  receives a common signal from the common line by being connected to the auxiliary common electrode  106  extending from the common line. 
         [0072]    In particular, an end portion of the second common electrode pattern  134   b  overlaps with and is in parallel with the fifth auxiliary common electrode pattern  106   e , and an end portion of the second pixel electrode pattern  132   b  overlaps with and is in parallel with the fourth auxiliary pixel electrode pattern  122   d.  The first auxiliary common electrode pattern  106   a  as a first capacitor electrode and the first auxiliary pixel electrode pattern  122   a  as a second capacitor electrode in the first storage region “C 1 ” with the gate insulating layer  110  therebetween as an insulator constitute a first storage capacitor “Cst 1 .” The second auxiliary common electrode pattern  106   b  as a first capacitor electrode, the third auxiliary pixel electrode pattern  122   c  as a second capacitor electrode, and the first common electrode pattern  134   a  as a third capacitor electrode with the gate insulating layer  110  and the passivation layer  128  as insulators constitute a second storage capacitor “Cst 2 .” Specifically, the gate insulating layer  110  is disposed between the second auxiliary common electrode pattern  106   b  and the third auxiliary pixel electrode pattern  122   c , and the passivation layer  128  is disposed between the third auxiliary pixel electrode pattern  122   c  and the first common electrode pattern  134   a.    
         [0073]    According to the IPS mode LCD device of the present invention, the aperture region can be increased by reducing the size of the storage capacitor without loss of the capacity, thereby improving the aperture ratio, the brightness and the resolution. 
         [0074]    It will be apparent to those skilled in the art that various modifications and variations can be made in the LCD device of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.