Abstract:
A multiplier-divider capable of offsetting errors includes a plurality of multiplication and division units to perform processes and arrangements so that errors generated by signals passing through the multiplier-divider are offset. As a result impact of the errors is reduced. More than one processing signal can be obtained from the same power supply to reduce loss of external sampling.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a multiplier-divider capable of offsetting errors and particularly to a multiplier-divider adopted for use on a power factor correction (PFC) circuit of power supplies. 
     BACKGROUND OF THE INVENTION 
     Multiplier-divider is widely used on modern electronic devices. It aims to generate an output signal proportional to two or more input signals. The output signal may be voltage or current. One of the common applications of the multiplier-divider is on a PFC circuit to generate a control signal through an input current, a feedback signal and an input voltage. 
     These days safety regulations and power saving requirements are increasingly strict. Hence power supply usually has to equip with a PFC circuit to reduce resonance wave and regulate current phase to be close the voltage phase to improve power utilization efficiency. The conventional passive PFC circuit can improve the efficiency only about 70%, while the active PFC circuit can improve the power utilization efficiency above 80%. Hence the active PFC circuit becomes a necessary element for all almost types of power supplies in the future. The active PFC circuit can be divided into a discontinuous current mode and a continuous current mode. The continuous current mode is more suitable for the power supply with power output greater than 300 W, thus is the main R &amp; D focus in the industry. The PFC circuit adopted the continuous current mode generates a control signal through a multiplier-divider to set current ON so that the continuous current forms an average current close to the output voltage phase. Therefore the multiplier-divider is an important and necessary circuit in the continuous current mode. 
     U.S. Pat. No. 7,057,440 entitled “Multiplier-divider circuit for a PFC controller” has two multiplier-divider units coupled in series and a pulse generator to regulate operation of the multiplier-divider units. Each multiplier-divider unit includes a charge time control circuit, a linear charge circuit and a sample circuit. It receives input of a first multiplier signal, a second multiplier signal and a divisor signal. It also has a current source to provide a selected current as the basis of gain. Output can be calculated according the following equation: 
     
       
         
           
             Vo 
             ∝ 
             
               
                 I 
                 R 
               
               ⁡ 
               
                 ( 
                 
                   
                     
                       I 
                       
                         A 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         C 
                       
                     
                     × 
                     
                       V 
                       E 
                     
                   
                   
                     V 
                     
                       A 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       C 
                     
                     2 
                   
                 
                 ) 
               
             
           
         
       
     
     In the cited reference mentioned above, the multiplier-divider unit generates a charge signal V CHG  through the first multiplier signal V E  and a saw-tooth signal V SAW . The saw-tooth signal V SAW  is generated by the divisor signal V AC . Moreover, the saw-tooth signal V SAW  is transformed by a current I 1  generated by the divisor signal V AC . But the current source of the divisor signal V AC  that generates the current I 1  has resistance (marked by numeral  122  in the drawings of the cited reference). Since an error occurs between two the integrated circuits due to different manufacturing processes, a difference occurs between the resistor  122  of the current source and the external resistance that causes a manufacturing variation while the current I 1  is generated and passes through the resistor  122 . As the divisor signal V AC . is generated by the current I 1 , it also contains an error resulting from the manufacturing variation. The error is proportional to the divisor signal V AC . As a result, output generated by the cited reference has an error of 1/m 2  due to variations of temperature and manufacturing process. Such an error causes the multiplier-divider used on the active PFC circuit in the continuous current mode to regulate the current phase cannot increase the efficiency to a designed value. There is still room for improvement. 
     SUMMARY OF THE INVENTION 
     In view of the aforesaid problem occurred to the conventional technique that has error caused by variations of temperature and manufacturing process, the primary object of the present invention is to provide a multiplier-divider that can execute multiplication and division, and also can offset the aforesaid error to reduce the effect caused by the error so that the calculation result is closer to the desired value. 
     The invention provides a multiplier-divider capable of offsetting errors. It includes a buffer, a resistor, three sets of differential converters, two dividers, two multipliers and a pulse generator. Each multiplier has a peak detector and a voltage integrator with the period controlled by the divider. Each divider has two waveform generators which form independent dividers function wise, and have the structure passing through the multipliers at a next stage through the period. The pulse generator has two bar gate units and a square wave generator to isolate waveform and reset the bar gate units. By means of the elements set forth above, an embodiment circuit of the invention can be formed. Through the linear relationship of voltage and charges of a capacitor as follow: 
               V   C     =       I   ×   t     C           
The following equation can be derived:
 
     
       
         
           
             t 
             = 
             
               
                 
                   V 
                   C 
                 
                 × 
                 C 
               
               I 
             
           
         
       
     
     Based on the two basic equations set forth above, I and t are connected to two input ends of the multipliers to get Vc. With Vc and I as inputs of the dividers a t-shaped output can be obtained. Thus multiplication and division calculation can be performed by the multiplier-divider through the relationship between the voltage, current and period. 
     The foregoing, as well as additional objects, features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit block diagram of the invention. 
         FIG. 2  is a circuit diagram of an embodiment of the invention. 
         FIG. 3  is a chart showing the waveform on selected nodes of the embodiment circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Please refer to  FIG. 1  for a circuit block diagram of the invention. The circuit includes a multiplier input terminal  11 , a first divisor input terminal  12 , a second divisor input terminal  13  and a third divisor input terminal  14  to receive respectively a first multiplier signal Vac, a first divisor signal Vav, a second divisor signal Vr and a third divisor signal Ve, and an output terminal  15  to output process result. There is a first differential converter  31  which and the multiplier input terminal  11  are interposed by a buffer  2 . The buffer  2  has an output end which and the first divisor input terminal  12  are bridged by a resistor  21  in a straddle manner. The first divisor input terminal  12  further is connected to a capacitor. The first multiplier signal Vac forms the first divisor signal Vav on the capacitor. Thereby the first multiplier signal Vac charges the capacitor to get the first divisor signal Vav, sampling loss can be reduced. The multiplier-divider of the invention further includes the first differential converter  31 , a second differential converter  32 , a third differential converter  33 , a pulse generator  4 , a first multiplication unit  61  and a second multiplication unit  62 . The first differential converter  31  receives the first divisor signal Vav and divides the current to output a plurality of divisor conversion signals Iav. The second differential converter  32  receives the first multiplier signal Vac and outputs at least one multiplier conversion signal Iac. The pulse generator  4  receives one of the divisor conversion signals Iav to generate a first pulse signal CLK 1  and a second pulse signal CLK 2  that are output through a first pulse output end and a second pulse output end. The first division unit  51  receives one divisor conversion signal Iav, second divisor signal Vr and first pulse signal CLK 1  to execute division and output a first quotient signal SMP 1 . The first multiplication unit  61  receives the first quotient signal SMP 1  and multiplier conversion signal Iac output from the second differential converter  32  and the first pulse signal CLK 1  to calculate the product of the first quotient signal SMP 1  and multiplier conversion signal Iac and output a first product signal Va. The third differential converter  33  receives the first product signal Va and converts to output a product conversion signal Ia. The second division unit  52  receives another divisor conversion signal Iav, third divisor signal Ve and second pulse signal CLK 2  and processes and outputs a second quotient signal SMP 2 . The second multiplication unit  62  further receives the product conversion signal Ia output from the third differential converter  33 , the second quotient signal SMP 2  and the second pulse signal CLK 2  to form an output signal Vo resulting from multiplication of the product conversion signal Ia and the second quotient signal SMP 2 . The first differential converter  31 , second differential converter  32  and third differential converter  33  convert voltage to current according to a selected ratio. As the first differential converter  31 , second differential converter  32  and third differential converter  33  are produced through a same manufacturing process, they have a same error coefficient. In the process of generating the output signal Vo, the divisor conversion signals Iav generated by the first differential converter  31  go through two division processes through the first division unit  51  and second division unit  52  that accumulate two times of errors to form a division error. The multiplier conversion signal Iac generated by the second differential converter  32  passes through the first multiplication unit  61  to generate the first product signal Va. The first product signal Va is converted to the product conversion signal Ia through the third differential converter  33 . Hence the first multiplier signal Vac also goes through the second differential converter  32  and the third differential converter  33  to accumulate two times of errors to form one multiplication error. Hence in the second multiplication unit  62  the product conversion signal Ia and the second quotient signal SMP 2  are multiplied to offset the accumulated error coefficients resulting from two times of divisions and multiplications. As a result the output signal Vo is not affected by the error coefficients. 
     Refer to  FIGS. 2 and 3  for an embodiment circuit and a waveform chart on various nodes thereof. The first multiplier signal Vac passes through the buffer  2  and is sent to the second differential converter  32  to form the multiplier conversion signal Iac. The buffer  2  has the rear end connecting to the resistor  21  in a straddle manner and the first divisor input terminal  12 . The first divisor input terminal  12  is connected to a capacitor to form the first divisor signal Vav. The first divisor signal Vav is input to the first differential converter  31  to form the divisor conversion signal Iav. The divisor conversion signal Iav and the second divisor signal Vr are input to the first division unit  51 . The first division unit  51  includes a linear charge circuit consisting of a circuit switch S 2  and a capacitor C 3  and a square wave generator consisting of a comparator U 7 . The divisor conversion signal Iav charges the capacitor C 3  during the OFF period of the switch S 2 . The comparator U 7  has two input ends connecting to the capacitor C 3  and the second divisor signal Vr. Through the linear charge circuit a saw-tooth voltage is formed and input to the square wave generator of the first division unit  51  to be compared with the second divisor signal Vr. When the peak voltage of the capacitor C 3  is higher than the second divisor signal Vr, the comparator U 7  outputs a high level. Output of the first division unit  51  is substantially same as a time period obtained by division process of the second divisor signal Vr and the divisor conversion signal Iav. The second division unit  52  includes an OR gate U 11 , an AND gate U 4  and a comparator U 10 . The comparator U 10  receives a current component of the divisor conversion signal Iav and the third divisor signal Ve. Similarly, a time period is obtained by comparing the divisor conversion signal Iav and the third divisor signal Ve and performing a division process. Through the OR gate U 11  and AND gate  4 , it is input to the second multiplication unit  62 . The pulse generator  4  includes a first bar gate unit  41  and a second bar gate unit  42 . The first bar gate unit  41  and second bar gate unit  42  may consist of two SR-flip flop. The input and output relationship of the first bar gate unit  41  and second bar gate unit  42  is a technique known in the art, thus details are omitted hereinafter. The division unit  51  and second division unit  52  have output linking respectively to an input of the first bar gate unit  41  and second bar gate unit  42 . In cooperation with the output of the first division unit  51  and second division unit  52 , the first bar gate unit  41  and second bar gate unit  42  have one output end delivering the first pulse signal CLK 1  and second pulse signal CLK 2 . The first bar gate  41  and second bar unit  42  further are interposed by a period restriction circuit. The period restriction circuit includes a linear charge circuit consisting of a switch S 6  and a capacitor C 4 , a comparator U 8  and a voltage source. The period restriction circuit has the output linking to another input end of the first bar gate unit  41  and second bar gate unit  42 . The charging time of the period restriction circuit is controlled by the first pulse signal CLK 1 . When the voltage of the capacitor C 4  of the period restriction circuit is higher than the voltage source a pulse is output to make the first pulse signal CLK 1  and second pulse signal CLK 2  to become a lower level. The first pulse signal CLK 1  passes through a NOT gate U 5  to control the switch S 2  of the linear charge circuit of the first division unit  51 , thereby to control the operation sequence of the first division unit  51 . The first pulse signal CLK 1  passes through the NOT gate U 5  and a NOR gate U 6  to be linked to the first multiplication unit  61 . The first multiplication unit  61  includes a peak detector and a voltage integrator. The voltage integrator includes a switch S 5  and a capacitor C 5 . ON/OFF of the switch S 5  is controlled by the first pulse signal CLK 1 . The capacitor C 5  is connected to the second differential converter  32 . The capacitor C 5  performs charging through the multiplier conversion signal Iac during the first pulse signal CLK 1  is at a low level. The peak detector includes a sampling switch S 7 , a capacitor C 6  and a comparator X 3 . When the first quotient signal SMP 1  output from the first division unit  51  is at a high level, the sampling switch S 7  of the peak detector is ON. For the first multiplication unit  61  the first quotient signal SMP 1  is substantially same as a time period to be multiplied with the current. The peak detector takes voltage samples of the integration performed by the voltage integrator to make the capacitor C 6  to be charged at the same voltage level of the capacitor C 5 . Meanwhile, the first bar gate unit  41  also outputs the first pulse signal CLK 1  to set the sampling switch S 7  OFF when charging of the capacitor C 6  is finished through the delay of the NOT gate U 5  and NOR gate U 6 . Thereafter the switch S 5  is ON to allow the capacitor C 5  to perform discharging. Thereby the capacitor C 6  can maintain a voltage peak value for the multiplier conversion signal Iac to charge the capacitor C 5  during the first pulse signal CLK 1  at a low level to form a multiplication effect to output a first product signal Va. The first product signal Va is linked to the third differential converter  33  to be converted to a product conversion signal Ia to be sent to the second multiplication unit  62 . The second multiplication unit  62  also has a peak detector and a voltage integrator which consists of a switch S 1  and a capacitor C 1 . The second pulse signal CLK 2  passes through three NOT gates U 1 , U 2  and U 3  and is linked to the switch S 1  to control ON and OFF of the switch S 1 . When the switch S 1  is OFF the product conversion signal Ia charges the capacitor C 1 . The peak detector includes a sampling switch S 3 , a capacitor C 2  and a comparator X 1 . When the second quotient signal SMP 2  output by the second division unit  52  is at a high level, by cooperating with the second pulse signal CLK 2  which also is at a high level, the AND gate U 4  can output a high level to set the sampling switch S 3  ON. The peak detector takes a voltage sample integrated by the voltage integrator so that the capacitor C 2  keeps the capacitor C 1  at a voltage peak value. Then the sampling switch S 3  is set OFF, and the switch S 1  is ON to make the capacitor C 1  to perform discharging. The peak voltage of the capacitor C 2  makes the comparator X 1  to generate the output signal Vo to finish the whole multiplication and division processes. 
     The processes previously discussed adopt the following equations:
 
 Iav=Vav×M 1  (1)
 
 Iac=Vac×M 2  (2)
 
 Ia=Va×M 3  (3)
 
     where M 1 , M 2  and M 3  are conversion coefficients of the first differential converter  31 , the second differential converter  32  and the third differential converter  33 . Presume that the gain of the second differential converter  32  is same as the third differential converter  33 , the following condition may be set:
 
 M 2=1 X M 3=1 X M 1=(π/2) X  
 
     where X is an error coefficient of the differential converter, the constant of M 3  is set π/2 so that the calculation result can become the set constant. 
     based on the formulas as follow: 
     
       
         
           
             
               
                 V 
                 C 
               
               = 
               
                 
                   
                     
                       I 
                       × 
                       t 
                     
                     C 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   and 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   t 
                 
                 = 
                 
                   
                     
                       V 
                       C 
                     
                     × 
                     C 
                   
                   I 
                 
               
             
             , 
           
         
       
     
     The following can be derived: 
     
       
         
           
             
               
                 
                   
                     
                       T 
                       
                         CLR 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     = 
                     
                       
                         Vr 
                         × 
                         C 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         3 
                       
                       Iav 
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   and 
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
             
               
                 
                   Va 
                   = 
                   
                     
                       Iac 
                       × 
                       
                         T 
                         
                           CLR 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                     
                     
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     where TCLR 1  is the charge time of Iac to C 5 , by putting (4) into (5), the following can be derived: 
     
       
         
           
             
               
                 
                   Va 
                   = 
                   
                     
                       Iac 
                       × 
                       Vr 
                       × 
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
             
               
                 
                   
                     T 
                     
                       CLR 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   = 
                   
                     
                       Ve 
                       × 
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     Iav 
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   Vo 
                   = 
                   
                     
                       Ia 
                       × 
                       
                         T 
                         
                           CLR 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                     
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     where TCLR 2  is the charge time of Ia to C 1 , by putting (3), (6) and (7) into (8), the following can be derived: 
     
       
         
           
             
               
                 
                   
                     V 
                     O 
                   
                   = 
                   
                     
                       
                         M 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         3 
                         × 
                         M 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                         × 
                         C 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           3 
                           2 
                         
                       
                       
                         C 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                         × 
                         C 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         5 
                         × 
                         M 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           1 
                           2 
                         
                       
                     
                     × 
                     
                       
                         Vr 
                         × 
                         Vac 
                         × 
                         Ve 
                       
                       
                         Vav 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     In the condition of M 2 =M 3 =1X M 1 =(π/2)X, where X is the error coefficient of the differential converter, by putting in 
     Vav=(2√{square root over (2)}/π)×Vrms, where Vrms is the average square root value of the first multiplier signal Vac, the following can be derived: 
     
       
         
           
             Vo 
             = 
             
               
                 0.5 
                 × 
                 Vr 
                 × 
                 Ve 
                 × 
                 Vac 
               
               
                 Vrms 
                 2 
               
             
           
         
       
     
     In the equation of Vo, as the conversion coefficients M 2  and M 3  of the second differential converter  32  and the third differential converter  33  are numerators, and the denominator is the square of the conversion coefficient M 1  of the first differential converter  31 , the error coefficient X of M 1 , M 2  and M 3  can be offset. As a result, all the variables M 1 , M 2 , M 3 , C 1 , C 3  and C 5  that relate to the manufacturing process or temperature are offset. Thus the error resulting from temperature coefficient and manufacturing process can be offset. 
     While the preferred embodiment of the invention has been set forth for the purpose of disclosure, modifications of the disclosed embodiment of the invention as well as other embodiments thereof may occur to those skilled in the art. Accordingly, the appended claims are intended to cover all embodiments which do not depart from the spirit and scope of the invention.