Abstract:
A circuit for simulating the parallel combination of a floating inductor and capacitor in the bilinear and LDI domains has a pair of nodes receiving an input voltage and connected to input terminals of associated first and second voltage followers. A first capacitor C1 is alternately or periodically connected across the output terminals of the voltage followers for sampling the input voltage, and connected between the output of the second voltage follower and the input terminal of an integrator including a second capacitor C2 which integrates and stores the charge voltage on C1. A third capacitor is periodically connected to the nodes for sampling the input voltage, and connected between the output terminals of the first voltage follower and the integrator for subsequently also sampling and storing the integrated voltage on C2. The sum of the input voltage and the integrated voltage that is stored by C3 is discharged to the new input voltage when C3 is again connected across the nodes. The parallel combination of a grounded inductor and capacitor is simulated by replacing one of the voltage followers with a short circuit and connecting the associated node to ground. An inductor alone is simulated across the nodes by proper selection of values of the three capacitors.

Description:
BACKGROUND OF INVENTION 
     This invention relates to switched capacitor circuits or networks for simulating electrical impedance elements, and more particularly to a switched capacitor circuit replacement for an inductor and/or the parallel combination of an inductor and a capacitor. 
     A switched capacitor floating-inductor simulation circuit that is relatively insensitive to parasitic capacitance is described in the article &#34;Switched Capacitor Filters Using Floating-Inductance Simulation Circuits&#34; by Man Shek Lee, Electronics Letters, Sept. 27, 1979, Vol. 15, No. 20, pages 644-645, and in the U.S. patent application &#34;Switched-Capacitor Floating-Inductor Simulation Circuit&#34; by Man Shek Lee, Ser. No. 162,981, Filed June 25, 1980, U.S. Pat. No. 4,333,157, Issued Jun. 1, 1982, both of which are incorporated herein by reference. The inductor simulation circuit described there requires matched capacitors, however, to simulate a truly floating lossless inductor or impedance. It is desirable to have switched capacitor types of simulation circuits that do not depend on the matching of components. An object of this invention is the provision of a switched capacitor circuit that does not require matching of components to simulate a desired impedance. Another object is the provision of a switched capacitor circuit that simulates an inductor. A further object is the provision of such a circuit that simulates the parallel combination of an inductor and a capacitor. 
     SUMMARY OF INVENTION 
     In accordance with this invention, an integratable switched capacitor circuit for simulating an impedance element comprises: a pair of nodes adapted for receiving an input voltage; voltage follower means having an input terminal connected to one of the nodes and having an output terminal; capacitors C1 and C3; integrator means including a second capacitor C2; switch means associated with C1 and C3 and being periodically operative in first and second switch states; and means for coupling the switch means to the other node; operation of the switch means in the first state electrically connecting C1 between the output terminal of the voltage follower means and the coupling means for sampling and storing an input voltage, and electrically connecting C3 across the nodes for sampling the input voltage; operation of the switch means in the second state electrically connecting C1 to the integrator means for causing it to integrate the charge voltage stored on C1, and electrically coupling C3 between the output terminal of the integrator means and one of the output terminal of the voltage follower means and the coupling means for causing C3 to also sample the integrated voltage; the sum of the input voltage and the integrated voltage that is stored by C3 being discharged to a new input voltage when the switch means subsequently operates in the next first state which again connects C3 across the nodes. The circuit may simulate the parallel combination of a floating inductor and a capacitor, or a floating inductor alone, when the coupling means comprises a second voltage follower means. Conversely, the circuit may simulate a grounded inductor in parallel with a capacitor, or a grounded inductor alone, when the coupling means connects the other node to ground. 
    
    
     DESCRIPTION OF DRAWING 
     This invention will be more fully understood from the following detailed descriptions of preferred embodiments thereof, together with the drawing in which: 
     FIG. 1 is a schematic circuit diagram of a preferred embodiment of this invention for simulating the parallel combination of a floating inductor and capacitor; 
     FIG. 2 is a schematic circuit diagram of a switched capacitor circuit for simulating the parallel combination of a grounded inductor and capacitor; and 
     FIG. 3 is a schematic circuit diagram of an alternate embodiment for simulating the parallel combination of a grounded inductor and capacitor. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     This invention is described in the article &#34;Improved Circuit Elements for Switched-Capacitor Ladder Filters&#34; by Man Shek Lee, Electronics Letters, Feb. 14, 1980, Vol. 16, No. 4, pages 131-133, which is incorporated herein by reference. 
     Referring now to FIG. 1, the switched capacitor circuit 10 here for simulating the parallel combination of a floating inductor and capacitor across a pair of nodes 21 and 22 thereof is preferably implemented in fully integrated circuit form. The switched capacitor circuit comprises a pair of voltage follower circuits 31 and 32; an active integrator circuit 34; a pair of integrated capacitors C1 and C3; and a plurality of transistor switch means 41-44 for making desired connections to the capacitors C1 and C3. The dots adjacent one sides of integrated capacitors indicate the locations of the top plates thereof. 
     The integrator circuit 34 comprises an integrated capacitor C2 and an integrated differential input operational amplifier 35 which is essentially a voltage controlled voltage source having a very low output impedance, a very high input impedance, and providing whatever output current is demanded by external circuitry. The non-inverting input line 37 is directly electrically connected to the output terminal of voltage follower 32. The integrating capacitor C2 is connected across the amplifier with the top and bottom plates connected to its input line 36 and output line 38, respectively. Consideration of this integrated structure reveals that the bottom plate parasitic capacitance of C2 cannot change the ouptut impedance of amplifier 35 since this impedance is already substantially zero ohms. This means that the switched capacitor circuit 10 is generally insensitive to the bottom plate parasitic capacitance effects of C2. Since the parasitic capacitance associated with the top plate of integrated capacitors is generally very low, its effect on the operation of the circuit is negligible. 
     Each of the voltage follower circuits 31 and 32 may be an integrated differential input operational amplifier having its non-inverting input connected to an associated one of the nodes and its output directly electrically connected to the inverting input thereof. These voltage followers are essentially voltage controlled voltage sources that have very high input impedance and very low output impedances. Alternatively, the circuits 31 and 32 can be other types of voltage followers. Since the gain of a voltage follower is by definition substantially unity, the voltage between lines 53 and 54 is substantially equal to an input voltage v i  that is connected across the nodes 21 and 22. 
     In an integrated circuit embodiment of the circuit 10 that is implemented with MOS technology, each of the switch means 41-44 comprises a pair of series-connected MOS FET transistors having gate electrodes that are driven by different ones of a pair of two phase non-overlapping digital timing control signals φ1 and φ2 that are produced by a source 48. That is, assuming that the switches are turned on by a positive signal, the positive portions of the control signals φ1 and φ2 are non-overlapping, although the negative portions of these control signals may overlap. The transistors 71 and 72 are connected in series between the output terminals of the voltage followers 31 and 32 whereas the transistors 73 and 74 are connected in series between the inverting input of amplifier 34 and the output terminal of voltage follower 32. The pair of switching transistors 75 and 76 are connected in series across the voltage follower 31, whereas the transistors 77 and 78 are connected in series between the node 22 and the output terminal of the integrator. The intermediate terminal between the transistors of each switch means is connected to a side of an associated integrated capacitor. The control signals φ1 and φ2 are 180° out of phase with each other in FIG. 1, and preferably have a 50% duty cycle. The switching frequency f s  of the control signals is f s  =1/T, where T is the period of a switching cycle. It is known that the switching frequency should be greater than the Nyquist sampling rate. 
     In operation, switching transistors 71 and 74 are poled for connecting C1 between the output lines 53 and 54 of the voltage followers when the control signal φ1 is high. This causes C1 to sample an input voltage v i  that is applied to the nodes 21 and 22. The transistors 75 and 77 are also caused to conduct when φ1 is high for connecting C3 across the input nodes for causing it to charge to the input voltage. When φ2 subsequently goes high, transistors 72 and 73 conduct to connect C1 between the inverting input of the amplifier and the output of voltage follower 32. This causes the charge on C1 to be transferred to C2 so that the input voltage is integrated by the circuit 34 and stored on C2. The transistors 76 and 78 also conduct in response to this positive voltage in φ2 for connecting C3 between the output terminal of the integrator and the output terminal of the other voltage follower 31. This causes C3 to also sample the integrated input voltage which is stored on C2. When φ1 next goes high, transistors 75 and 77 again connect C3 across the nodes 21 and 22 for enabling C3 to charge (or discharge) in a positive or negative direction from the sum of the previously sampled input voltage and the integrated voltage to the new value of input voltage that is now present on the nodes 21 and 22. This creates a current in lines 51 and 52 that has an average value that is related to the integral of the input voltage v i  and the derivative thereof so that this circuit effectively simulates the parallel combination of a discrete time domain inductor and capacitor between nodes 21 and 22. 
     The aforementioned operation of switch means 41 and transistors 71 and 72 connects the bottom plate of integrated capacitor C1 between the output terminals of voltage sources 31 and 32 so that the bottom plate parasitic capacitance of C1 does not have a deliterious effect on the operation of the circuit. Consideration of the circuit 10 reveals that the bottom plate parasitic capacitance of C3 may have an effect on the circuit operation when the circuit is considered by itself. In a network employing the circuit 10, however, an external capacitance is normally connected between node 21 and ground. The value of this external capacitance may be adjusted in order to compensate for the parasitic capacitance associated with the bottom plate of C3 so that it will not have an adverse effect on the operation of the circuit 10. Thus, the switched capacitor circuit 10 will be generally insensitive to bottom plate capacitance effects in a network employing it. 
     The lossless discrete integrator (LDI) and the bilinear transformations are commonly used in deriving a discrete time domain filter from a continuous time domain filter. The LDI (Loss less Discrete Integrator) and bilinear transformations are ##EQU1## where T is the sampling period and z=e st . In circuits characterized by both the LDI and the bilinear transformations, the differential charge-voltage relationship for a capacitor is 
     
         ΔQ(z)=C(1-z.sup.-1) V(z)                             (3) 
    
     The charge-voltage relationship for an inductor that is characterized by the LDI transformation is ##EQU2## where L is inductance. The charge-voltage relationship for an inductor that is characterized by the bilinear transformation, however, is ##EQU3## Substituting the algebraic identity 
     
         z.sup.-1 =1/4(1+z.sup.-1).sup.2 -1/4(1-z.sup.-1).sup.2     (6) 
    
     in equation 4, the relationship in equation 4 for an inductor may be rewritten as ##EQU4## for the LDI transformation. Comparing the expressions in equations 3, 5 and 7, it will be noted that an inductor in the LDI domain (equation 7) is equivalent to an impedance element in the bilinear transformed domain comprising the parallel combination of an inductor of the same value L (equation 5) and a capacitor having a negative capacitance -T 2  /4L (equation 3). 
     In framing an analysis of the switched capacitor circuit in FIG. 1, it is assumed that the parasitic capacitance associated with the switch means and the top plates of the integrated MOS capacitors are small and the effects thereof negligible. The bottom plate parasitic capacitances of C1 and C2 also have no effect on the operation of the circuit since C1 is switched between the output terminals of voltage follower types of voltage sources 31 and 32, and C2 is driven by a voltage source 34. Since the bottom plate parasitic capacitance of C3 is equivalent to a fixed capacitor connected between the node 21 and ground, its effects can readily be compensated for by incorporating it into an external capacitor that is also connected between node 21 and ground. The effects of the bottom plate parasitic capacitances of C1, C2 and C3 are therefore also omitted in the following analysis. 
     Considering now the circuit in FIG. 1, the differential charge in line 51 between adjacent sample times is ##EQU5## where v o  is the voltage across C2 of the integrator 34 (which is also the difference between the voltages measured between ground and lines 38 and 54), q(nT) is the net charge in line 51 from time -∞ to time nT, and q(nT-T) is the net charge in line 51 from time -∞ to time (nT-T). The differential charge in line 52 during this time interval is also defined by equation 8. Recognizing that the voltage v o  on the integrator is the integral of the input voltage v i  (t) between the lines 51 and 52, and also between lines 53 and 54, these voltages are related in the expression 
     
         C2(v.sub.o (nT-T)-v.sub.o (nT-2T))=C1 v.sub.i (nT-T)       (9) 
    
     for the differential charge in the integrated capacitor C2. Applying the z-transform to equations 8 and 9, one obtains the expressions 
     
         ΔQ(z)=C3(1-z.sup.-1) V.sub.i (z)+C3 z.sup.-1 V.sub.o (z)(10) 
    
     and 
     
         C2(1-z.sup.-1) (z.sup.-1) V.sub.o (z)=C1 z.sup.-1 V.sub.i (z)(11) 
    
     Solving for the output voltage in equation 11, one obtains ##EQU6## Substituting equation 12 into equation 10, one obtains the desired differential charge-voltage relationship ##EQU7## for the simulation circuit in FIG. 1. Comparing equation 13 with equations 3 and 4 reveals that the circuit in FIG. 1 simulates an LDI impedance element having an inductance T 2  C2/C1C3 in parallel with a capacitance C3. By substituting equation 6 into equation 13, one obtains the relationship ##EQU8## Comparing equation 14 with equations 3 and 5 reveals that this same circuit 10 in FIG. 1 also simulates a bilinear impedance element consisting of an inductance T 2  C2/C1C3 that is connected in parallel with a capacitance C3-C1C3/4C2. This circuit has particular advantage since it does not depend on the matching of capacitors. The circuit 10 may be caused to simulate only a bilinear inductor across the nodes 21 and 22 by setting C1=4C2. Alternately, the circuit 10 may be caused to simulate only an LDI or a bilinear inductor by connecting an element having a negative capacitance of the proper value across the nodes 21 and 22. The circuit 10 may also be caused to simulate the parallel combination of a bilinear inductor and a negative capacitor by proper selection of values of the capacitors. 
     Although this invention is described in relation to preferred embodiments thereof, variations and modifications will occur to those skilled in the art. By way of example, the simulation circuit in FIG. 1 may be modified for simulating a grounded impedance element consisting of the parallel combination of an inductor and a capacitor by merely replacing the voltage follower 32 with a short circuit and connecting the node 22 to a ground reference potential, as is shown in FIG. 2 where the switch means are illustrated in schematic form. Alternatively, the voltage follower 31 may be replaced with a short circuit and the node 21 connected to ground, as is illustrated in FIG. 3. Also, the simulation circuit may employ a voltage follower type of integrator circuit 34&#39; and switch means 45 and 46 which are associated with the switched capacitor C1&#39;. The integrator means 34&#39; comprises a voltage follower circuit 33 and an integrator capacitor C2&#39; that is electrically connected between the input terminal of this voltage follower and the output terminal of voltage follower 32 in FIG. 3. Since the bottom plate of the integrating capacitor C2&#39; is driven by a voltage source 32, the bottom plate parasitic capacitance of C2&#39; has negligible effect on the operation of the circuit. In this simulation circuit 10.increment., the switch means 45 and 46 are responsive to φ1 for connecting C1&#39; between node 21 and the output terminal of voltage follower 32. Alternatively, the simulation circuit may employ other types of integrator circuits. Further, the simulation circuit may be realized with integrated circuit technologies other than MOS, in other than fully integrated circuit form, and fully or partially implemented with discrete components. Also, the switch means may comprise other types of switching elements such as discrete transistors, mechanical switches, relays, and other types of integrated switches. Additionally, the circuits 31-33 may comprise other types of voltage followers. Additionally, the duty cycle of the timing control signals may be less than 50%, although it should not exceed this value. The scope of this invention is therefore to be determined from the attached claims rather than from the aforementioned detailed descriptions of preferred embodiments thereof.