Abstract:
Disclosed is a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode. The memory device includes: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number; (N+1) sense amp blocks corresponding to the N memory cell blocks; 2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively; and N controllers for controlling the 2N switching blocks, respectively, wherein the N controllers turn off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a memory device for reducing leakage current, and more particularly to a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode.  
         [0003]     2. Description of the Prior Art  
         [0004]     With the high integration of a memory device, the space of a memory cell is reduced and the size of a pattern is also reduced according to the reduction. Therefore, the occurrence probability of a bridge may also increase between a word line and a bit line. A memory device typically includes a redundant cell and a bad memory cell generated by a bridge between a word line and a bit line, etc., is replaced with the redundant cell through a redundant operation. However, even though the bad memory cell generated by the bridge between the word line and the bit line is replaced with the redundant cell, leakage current may flow by the bridge between the word line and the bit line in a waiting mode of a memory device. Therefore, power may be consumed.  
         [0005]      FIG. 1  is a circuit diagram illustrating one example of a case where a bridge is formed between a word line and a bit line in a conventional memory device.  
         [0006]     As shown in  FIG. 1 , the memory device includes memory cell blocks  111  to  114 , sense amp blocks  121  to  125 , switching blocks  141  to  148 , and controllers  171  to  174 .  
         [0007]     Hereinafter, cases where the memory device is in an operation mode and a waiting mode will be separately described.  
         [0008]     When the memory device is in the operation mode, in order to designate matrix type memory cells, row addresses and column addresses are applied to the memory cells through word lines WL 1  to WL 4  and bit lines BL 1 , /BL 1 , BL 2 , /BL 2 , BL 3 , /BL 3 , BL 4 , and /BL 4 . Simultaneously, an enable signal ACT is applied to the controller  171  to  174 . Then, the controller  171  applies a control signal BIS 1  to the switching blocks  141  and  142 , the controller  172  applies a control signal BIS 2  to the switching blocks  143  and  144 , the controller  173  applies a control signal BIS 3  to the switching blocks  145  and  146 , and the controller  174  applies a control signal BIS 4  to the switching blocks  147  and  148 . For example, when one memory cell block  112  is selected from the four memory cell blocks  111  to  114 , only the control signal BIS 2  comes into a low level from among the four control signals BIS 1 , BIS 2 , BIS 3  and BIS 4 . Therefore, only two switching blocks  142  and  145  are turned off from among the eight switching blocks  141  to  148 . As a result, the sense amp blocks  122  and  123  are connected to the memory cell block  112  to be selected. The sense amps  128  and  129  of the connected sense amp block  122  and the sense amps  130  and  131  of the connected sense amp block  123  detect data of the memory cells in the memory cell block  112 , respectively. Specifically, the sense amp block described in  FIGS. 1 and 2  includes an equalizer for precharging corresponding pairs of bit lines with precharge voltage. As known in the art, an equalizer is a circuit for precharging pairs of bit lines with precharge voltage (e.g., Vdd/2) in a precharge mode.  
         [0009]     When the memory device is in the waiting mode, each of the word lines WL 1  to WL 4  maintains a ground level, i.e., a Vss level, and each of the bit lines BL 1 , /BL 1 , BL 2 , /BL 2 , BL 3 , /BL 3 , BL 4 , and /BL 4  maintains a Vcc/2 level. The controller  171  applies the control signal BIS 1  of a high level to the switching blocks  141  and  142  by the enable signal ACT, the controller  172  applies the control signal BIS 2  of a high level to the switching blocks  143  and  144  by the enable signal ACT, the controller  173  applies the control signal BIS 3  of a high level to the switching blocks  145  and  146  by the enable signal ACT, and the controller  174  applies the control signal BIS 4  of a high level to the switching blocks  147  and  148  by the enable signal ACT. Therefore, all of the switching blocks  141  to  148  are turned on. That is, the memory cell block  111  is connected to the sense amp blocks  121  and  122 , the memory cell block  112  is connected to the sense amp blocks  122  and  123 , the memory cell block  113  is connected to the sense amp blocks  123  and  124 , and the memory cell block  114  is connected to the sense amp blocks  124  and  125 . Herein, because the bit line is maintained with the precharge voltage, leakage current is continuously generated from the bit line to the word line having the ground voltage through a defective cell transistor. That is, when a bridge  181  is formed between the word line WL 2  and the bit line BL 3 , the leakage current flows from the bit line to the word line by voltage difference between the word line and the bit line because the switching block  144  is in the turn-on state.  
         [0010]     The leakage current flows when the memory device is in the waiting mode, thereby consuming power. Specifically, this power consumption may be largely problematic in recent memory devices pursuing low power consumption.  
       SUMMARY OF THE INVENTION  
       [0011]     Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a memory device which can reduce power consumption by blocking leakage current in a waiting mode through improvement of a connection relation between a switching block and a controller.  
         [0012]     In order to achieve the above objects, according to one aspect of the present invention, there is provided a memory device for reducing leakage current, the memory device including: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number; (N+1) sense amp blocks corresponding to the N memory cell blocks; 2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively; and N controllers for controlling the 2N switching blocks, respectively, Wherein the N controllers turn off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.  
         [0013]     In the present invention, wherein N word lines connect the memory cells with each other, the N word lines corresponding to the N memory cell blocks respectively, bit lines corresponding to the memory cells connect the N memory cell blocks, the 2N switching blocks and the (N+1) sense amp blocks with each other, and a random i th  controller of the N controllers is connected to a (2i−1) th  switching block and a 2i th  switching block of the 2N switching blocks, wherein i represents a constant having a value of 1, 2, . . . , N.  
         [0014]     In the present invention, both a (2k−1) th  switching block and a 2k th  switching block of the 2N switching blocks are turned on by an k th  controller of the N controllers when the memory device is in an operation mode for selecting an k th  memory cell block of the N memory cell blocks, wherein k represents a constant having a value of 1, 2, . . . , N.  
         [0015]     In order to achieve the above objects, according to another aspect of the present invention, there is provided a memory device having a folded bit line structure, the memory device including: N memory cell blocks; and a first switching block, a sense amp block and a second switching block disposed every between the memory cell blocks, wherein the first switching block is located between an i th  memory cell block and the sense amp block, the second switching block is located between an (i−1) th  memory cell block and the sense amp block, the first switching block and the second switching block are turned off when the memory device is in a waiting mode, and only the first switching block adjacent to the i th  memory cell block is turned on when the memory device is in an operation mode.  
         [0016]     In the present invention, bit lines of the memory cell block maintain ground voltage. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0018]      FIG. 1  is a circuit diagram of a conventional memory device; and  
         [0019]      FIG. 2  is a circuit diagram of a memory device according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]     Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings.  
         [0021]      FIG. 2  is a circuit diagram of a memory device for reducing leakage current according to the present invention.  FIG. 2  shows a part of a memory cell array having a folded bit line structure.  
         [0022]     As shown in  FIG. 2 , the memory device includes memory cell blocks  211  to  214 , sense amp blocks  221  to  225 , switching blocks  241  to  248 , and controllers  271  to  274 .  
         [0023]     Each of the memory cell blocks  211  to  214  includes a plurality of memory cells and the memory cells are connected by a corresponding word line WL 1  or WL 4 .  
         [0024]     When the memory device is in an operation mode, the sense amp block  221  detects data of the memory cells through sense amps  226  and  227  therein, the sense amp block  222  detects data of the memory cells through sense amps  228  and  229  therein, the sense amp block  223  detects data of the memory cells through sense amps  230  and  231  therein, the sense amp block  224  detects data of the memory cells through sense amps  232  and  233  therein, and the sense amp block  225  detects data of the memory cells through sense amps  234  and  235  therein.  
         [0025]     The switching block  241  connects the memory cell block  211  with the sense amp block  221 , the switching block  242  connects the memory cell block  211  with the sense amp block  222 , the switching block  243  connects the memory cell block  212  with the sense amp block  222 , the switching block  244  connects the memory cell block  212  with the sense amp block  223 , the switching block  245  connects the memory cell block  213  with the sense amp block  223 , the switching block  246  connects the memory cell block  213  with the sense amp block  224 , the switching block  247  connects the memory cell block  214  with the sense amp block  224 , and the switching block  248  connects the memory cell block  214  with the sense amp block  225 . The switching block  241  and the switching block  242  are turned on/turned off by the control signal BIS 1  of the controller  271 , the switching block  243  and the switching block  244  are turned on/turned off by the control signal BIS 2  of the controller  272 , the switching block  245  and the switching block  246  are turned on/turned off by the control signal BIS 3  of the controller  273 , and the switching block  247  and the switching block  248  are turned on/turned off by the control signal BIS 4  of the controller  274 . Further, the memory cell block  211 , the sense amp block  221  and the switching block  241  are connected by the bit lines BL 1 , /BL 1 , BL 3  and /BL 3 . The memory cell block  211 , the switching block  242 , the sense amp block  222 , the switching block  243 , and the memory cell block  212  are connected by the bit lines  
         [0026]     BL 2 , /BL 2 , BL 4  and /BL 4 . The memory cell block  212 , the switching block  244 , the sense amp block  223 , the switching block  245 , and the memory cell block  213  are connected by the bit lines BL 1 , /BL 1 , BL 3  and /BL 3 . The memory cell block  213 , the switching block  246 , the sense amp block  224 , the switching block  247 , and the memory cell block  214  are connected by the bit lines BL 2 , /BL 2 , BL 4  and /BL 4 . The memory cell block  214 , the switching block  248  and the memory cell block  225  are connected by the bit lines BL 1 , /BL 1 , BL 3  and /BL 3 .  
         [0027]     The controllers  271  to  274  receive the enable signal ACT to output the control signals BIS 1  to BIS 4 , respectively. The outputted control signal BIS 1  is inverted through an inverter IN 1  and transferred to the switching blocks  241  and  242 . The outputted control signal BIS 2  is inverted through an inverter IN 2  and transferred to the switching blocks  243  and  244 . The outputted control signal BIS 3  is inverted through an inverter IN 3  and transferred to the switching blocks  245  and  246 . The outputted control signal BIS 4  is inverted through an inverter IN 4  and transferred to the switching blocks  247  and  248 .  
         [0028]     Hereinafter, cases where the memory device is in an operation mode and a waiting mode will be separately described.  
         [0029]     When the memory device is in the operation mode, in order to designate matrix type memory cells, row addresses and column addresses are applied to the memory cells through the word lines WL 1  to WL 4  and the bit lines BL 1 , /BL 1 , BL 2 , /BL 2 , BL 3 , /BL 3 , BL 4 , and /BL 4 . Simultaneously, the enable signal ACT is applied to the controller  271  to  274 . Then, the controller  271  applies the control signal BIS 1  to the switching blocks  241  and  242 , the controller  272  applies the control signal BIS 2  to the switching blocks  243  and  244 , the controller  273  applies the control signal BIS 3  to the switching blocks  245  and  246 , and the controller  274  applies the control signal BIS 4  to the switching blocks  247  and  248 . For example, when one memory cell block  212  is selected from the four memory cell blocks  211  to  214 , only the control signal BIS 2  comes into a low level from among the four control signals BIS 1 , BIS 2 , BIS 3  and BIS 4 . The control signal BIS 2  is inverted by the inverter IN 2  and is applied to the switching blocks  243  and  244 . As a result, only the two switching blocks  243  and  244  are turned on from among the eight switching blocks  241  to  248 . Therefore, the sense amp blocks  222  and  223  are connected to the memory cell block  212  to be selected. The sense amps  228  and  229  of the connected sense amp block  222  and the sense amps  230  and  231  of the connected sense amp block  223  detect data of the memory cells in the memory cell block  212 , respectively. As described above, the sense amp block described in the present invention includes an equalizer for precharging corresponding pairs of bit lines with precharge voltage. As known in the art, the equalizer is a circuit for precharging pairs of bit lines with precharge voltage in a precharge mode.  
         [0030]     When the memory device is in the waiting mode, each of the word lines WL 1  to WL 4  maintains a ground level, i.e., a Vss level. The controller  271  outputs the control signal BIS 1  of a high level by the enable signal ACT, the controller  272  outputs the control signal BIS 2  of a high level by the enable signal ACT, the controller  173  outputs the control signal BIS 3  of a high level by the enable signal ACT, and the controller  174  outputs the control signal BIS 4  of a high level by the enable signal ACT. The control signal BIS 1  is inverted by the inverter IN 1  and is applied to the switching blocks  241  and  242 , the control signal BIS 2  is inverted by the inverter IN 2  and is applied to the switching blocks  243  and  244 , the control signal BIS 3  is inverted by the inverter IN 3  and is applied to the switching blocks  245  and  246 , and the control signal BIS 4  is inverted by the inverter IN 4  and is applied to the switching blocks  247  and  248 . As a result, all of the switching blocks  241  to  248  are turned off. That is, the memory cell blocks  211  to  214  and the sense amp blocks  221  to  225  are turned off, respectively, so that the sense amp block and the memory cell block are separated. Consequently, the equalizer in the sense amp block does not have influence on the memory cell block. That is, because the bit lines of the memory cell block are separated from the sense amp block, the bit lines comes into a state where they are not influenced by the equalizer in the sense amp block. As a result, the bit lines have ground voltage. Consequently, leakage current does not flow even when a bridge is formed between a bit line and a word line corresponding to the bit line. In other words, even when a bridge  281  is formed between the bit line WL 2  and the word line BL 3 , current does not flow because the switching block  244  is in the turn-off state.  
         [0031]     Hereinafter, the superiority of the memory device according to the present invention will be described through comparison of a conventional memory device and the memory device of the present invention.  
         [0032]     As described above, when the conventional memory device is in a waiting mode, a switching block is turned on. Therefore, when a bride is formed between a word line and a bit line, leakage current flows by voltage difference between the word line and the bit line, so that power is consumed.  
         [0033]     However, when the memory device of the present invention is in a waiting mode, a switching block is turned off. Therefore, even when a bride is formed between a word line and a bit line, leakage current does not flow by the switching block turned off. Accordingly, power consumption does not occur.  
         [0034]     As described above, when the memory device according to the present invention is used, leakage current does not flow in the waiting mode of the memory device even when a bride is formed between a word line and a bit line. AS a result, power consumption can be reduced.  
         [0035]     The preferred embodiment of the present invention has been described for illustrative purposes, and those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.