Abstract:
An ESD protection device is provided. Each of a first and a second well has a first conductive type. Each of a first and a second doping region has a second conductive type and is formed in the first well. A third doping region has the first conductive type. A fourth doping region has the second conductive type. The third and fourth doping regions are formed in the second doping region. Each of a fifth and a sixth doping region has the second conductive type and is formed in the second well. A seventh doping region has the first conductive type. An eighth doping region has the second conductive type. The seventh and eighth doping region are formed in the sixth doping region. A first and a second trigger gate are formed on the first and second wells and partially cover the second and sixth doping regions respectively.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to an electrostatic discharge protection device, and more particularly to an electrostatic discharge protection device with a silicon controlled rectifier. 
     Description of the Related Art 
     As semiconductor manufacturing processes have developed, electrostatic discharge (ESD) protection has become one of the most critical reliability issues for integrated circuits (IC). ESD protection circuits generally protect integrated circuits (IC) from machine model (MM) or human body model (HBM) electrostatic discharge events. Commercial integrated circuits require high tolerance to accidental ESD and the dangers this can cause. Otherwise, the IC can easily become damaged by an accidental ESD event. Therefore, designers always research how to design ESD protection elements to effectively protect ICs. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with an embodiment, an electrostatic discharge protection device comprises a first well, a first doping region, a second doping region, a third doping region, a fourth doping region, a first trigger gate, a second well, a fifth doping region, a sixth doping region, a seventh doping region, an eighth doping region, and a second trigger gate. The first well has a first conductive type. The first doping region has a second conductive type and is formed in the first well. The second doping region has the second conductive type and is formed in the first well. The third doping region has the first conductive type and is formed in the second doping region. The fourth doping region has the second conductive type and is formed in the second doping region. The first trigger gate is formed on the first well and partially covers the second doping region. The second well has the first conductive type. The fifth doping region has the second conductive type and is formed in the second well. The sixth doping region has the second conductive type and is formed in the second well. The seventh doping region has the first conductive type and is formed in the sixth doping region. The eighth doping region has the second conductive type and is formed in the sixth doping region. The second trigger gate is formed on the second well and partially covers the sixth doping region. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a schematic diagram of an exemplary embodiment of an ESD protection device, according to various aspects of the present disclosure; 
         FIG. 2  is a schematic diagrams of another exemplary embodiments of the ESD protection device, according to various aspects of the present disclosure; 
         FIG. 3  is an equivalent circuit of the ESD protection device according to embodiments of the present invention; and 
         FIG. 4  is another equivalent circuit of the ESD protection device according to embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1  is a schematic diagram of an exemplary embodiment of an ESD protection device, according to various aspects of the present disclosure. As shown in  FIG. 1 , the ESD protection device  100  comprises a substrate  110 , wells  121 ˜ 122 , doping regions  131 ˜ 132 ,  141 ˜ 144 , and  151 ˜ 152 , and trigger gates  161 ˜ 162 . The doping regions  121 ˜ 122  are lightly doped. In this embodiment, the well  121  is separated from the well  122  and does not contact the well  122 . In one embodiment, a deep trench isolation technology is used to separate the wells  121  and  122 . Each of the wells  121  and  122  has a first conductive type and formed in the substrate  110 . The substrate  110  has a second conductive type. In one embodiment, the first conductive type is a N-type, and the second conductive type is a P-type. In another embodiment, the first conductive type is a P-type and the second conductive type is a N-type. 
     Each of the doping regions  131  and  141  has the second conductive type and formed in the first well  121 . The impurity concentration of the doping region  131  is lower than the impurity concentration of the doping region  141 . In one embodiment, when the second conductive type the the P-type, the doping region  131  is referred to as a P-body. However, when the second conductive type is the N-type, the doping region  131  is referred to as a N-body. In this embodiment, the doping region  141  is a heavily doped region. 
     The doping region  151  has the first conductive type and formed in the doping region  131 . In one embodiment, the doping region  151  is a heavily doped region. The impurity concentration of the doping region  151  is higher than the impurity concentration of the well  121 . The doping region  142  has the second conductive type and formed in the doping region  131 . In one embodiment, the doping region  142  is a heavily doped region. The impurity concentration of the doping region  142  is similar to the impurity concentration of the doping region  141  and higher than the impurity concentration of the doping region  131 . In this embodiment, the doping region  141 , the well  121  and the doping regions  131  and  151  constitute a silicon controlled rectifier (SCR). Additionally, the doping region  141 , the well  121  and the doping region  131  constitute a bipolar junction transistor (BJT). 
     Each of the doping regions  132  and  144  has the second conductive type and formed in the second well  122 . The impurity concentration of the doping region  132  is lower than the impurity concentration of the doping region  144 . The impurity concentration of the doping region  132  is similar to the impurity concentration of the doping region  131 . In one embodiment, when the second conductive type is the P-type, the doping region  132  serves as a P-body. When the second conductive type is the N-type, the doping region  132  serves as a N-body. In this embodiment, the doping region  144  is a heavily doped region. The impurity concentration of the doping region  144  is similar to the impurity concentration of the doping region  141 . 
     The doping region  152  has the first conductive type and formed in the doping region  132 . In one embodiment, the doping region  152  is a heavily doped region. The impurity concentration of the doping region  152  is higher than the impurity concentration of the well  122 . In another embodiment, the impurity concentration of the doping region  152  is similar to the impurity concentration of the doping region  151 . The doping region  143  has the second conductive type and formed in the doping region  132 . In one embodiment, the doping region  143  is a heavily doped region. The impurity concentration of the doping region  143  is similar to the impurity concentration of the doping region  141  and higher than the impurity concentration of the doping region  132 . In this embodiment, the doping region  144 , the well  122 , the doping regions  132  and  152  constitute a SCR. Furthermore, the doping region  144 , the well  122  and the doping region  132  constitute a BJT. 
     The trigger gate  161  is formed on the well  121  and partially covers the doping region  131 . The trigger gate  162  is formed on the well  122  and partially covers the doping region  132 . In this embodiment, the trigger gate  161 , the doping regions  151 ,  142 ,  143 , and  152  and the trigger gate  162  are electrically connected to each other via the connection line LN. The doping region  141  is electrically connected to the node ND 1 . The doping region  144  is electrically connected to the node ND 2 . When an ESD event occurs in the node ND 1  and the node ND 2  is coupled to ground, beginning at the node ND 1 , an ESD current flows through the first SCR constituted by the doping region  141 , the well  121 , the doping regions  131  and  151  and enters the doping region  143  through the connection line LN. Since the trigger gate  162  is coupled to the connection line LN, a channel CH 1  is formed in the well  132 . The ESD current entering into the doping region  143  flows to the well  122  through the doping region  132  and the channel CH 1 . Therefore, the voltage difference between the well  122  and the doping region  144  quick arrives to a turn-on level (e.g. 0.7V) such that the first BJT constituted by the doping region  132 , the well  122  and the doping region  144  is triggered and turned on. Therefore, the ESD current quick flows through the doping regions  143 ,  132 , the well  122  and the doping region  144  and finally to the node ND 2 . 
     Similarly, when an ESD event occurs in the node ND 2  and the node ND 1  is coupled to ground, beginning at the node ND 2 , an ESD current flows through the second SCR constituted by the doping region  144 , the well  122 , the doping regions  132  and  152  and enters the doping region  142  through the connection line LN. Since the trigger gate  161  is coupled to the connection line LN, a channel CH 2  is formed in the well  131 . The ESD current entering into the doping region  142  flows to the well  121  through the doping region  131  and the channel CH 2 . Therefore, the voltage difference between the well  121  and the doping region  141  quick arrives to a turn-on level (e.g. 0.7V) such that the second BJT constituted by the doping region  131 , the well  121  and the doping region  141  is triggered and turned on. Therefore, the ESD current quick flows through the doping regions  142 ,  131 , the well  121  and the doping region  141  and finally to the node ND 1 . 
     In one embodiment, when the first conductive type is the N-type and the second conductive type is the P-type, the first BJT constituted by the doping region  132 , the well  122  and the doping region  144  is a pnp transistor. Similarly, the second BJT constituted by the doping region  131 , the well  121  and the doping region  141  is a pnp transistor. Additionally, each of the wells  121  and  122  is a high voltage N-well (HVNW). 
     In another embodiment, when the first conductive type is the P-type and the second conductive type is the n-type, the first BJT constituted by the doping region  132 , the well  122  and the doping region  144  is an npn transistor. Similarly, the second BJT constituted by the doping region  131 , the well  121  and the doping region  141  is an npn transistor. Additionally, each of the wells  121  and  122  is a high voltage O-well (HVPW). 
     In this embodiment, the wells  121  and  122  are formed in the same substrate (e.g.  110 ), but the disclosure is not limited thereto. In other embodiments, the well  121  is formed in a substrate (e.g.  211 ) and the well  122  is formed in another substrate (e.g.  212 ) as shown in  FIG. 2 . In this case, the substrates  211  and  212  are separated and independent from each other. The substrate  211  does not contact the substrate  212 . 
       FIG. 3  is an equivalent circuit of the ESD protection device  100  according to an embodiment of the present invention. For brevity, assume that the first conductive type is the N-type and the second conductive type is the P-type. As shown in  FIG. 3 , an equivalent diode D 1  is formed between the doping region  141  and the well  121 . Another equivalent diode D 2  is formed between the doping region  131  and the well  121 . Another equivalent diode D 3  is formed between the doping regions  131  and  151 . Another equivalent diode D 4  is formed between the doping regions  132  and  152 . Another equivalent diode D 5  is formed between the doping region  132  and the well  122 . Another equivalent diode D 6  is formed between the doping region  144  and the well  122 . 
     When an ESD event occurs in the node ND 1  and the node ND 2  is coupled to ground, the equivalent diodes D 1  and D 3  are turned on in a forward direction. Since the doping region  152  is electrically connected to the doping region  151 , the voltage level of the doping region  152  increases. Therefore, the equivalent diode D 4  is turned on in a reverse direction. Additionally, the voltage level of the trigger gate  162  is also increased. Therefore, the equivalent diode D 5  is turned on in the forward direction. When the equivalent diode D 5  is turned on, the voltage level of the well  122  is increased such that the equivalent diode D 6  is turned on in the reverse direction. Since the equivalent diodes D 1 , D 3 , D 4  and D 6  are turned, the ESD current is released from the node ND 1  to the node ND 2 . In this case, the doping region  141 , the well  121 , the doping regions  131  and  151  constitute a SCR. The SCR is serially connected to the pnp transistor constituted by the doping region  132 , the well  122  and the doping region  144 . 
     Similarly, when an ESD event occurs in the node ND 2  and the node ND is coupled to ground, the equivalent diodes D 4  and D 6  are turned on in a forward direction. Since the doping region  152  is electrically connected to the doping region  151 , the voltage level of the doping region  151  increases. Therefore, the equivalent diode D 3  is turned on in a reverse direction. Additionally, the voltage level of the trigger gate  161  is also increased. Therefore, the equivalent diode D 2  is turned on in the forward direction. When the equivalent diode D 2  is turned on, the voltage level of the well  121  is increased such that the equivalent diode D 1  is turned on in the reverse direction. Since the equivalent diodes D 6 , D 4 , D 3  and D 1  are turned, the ESD current is released from the node ND 2  to the node ND 1 . In this case, the doping region  144 , the well  122 , the doping regions  132  and  152  constitute a SCR. The SCR is serially connected to the pnp transistor constituted by the doping region  131 , the well  121  and the doping region  141 . 
       FIG. 4  is another equivalent circuit of the ESD protection device according to an embodiment of the present invention. In this embodiment, assuming that the first conductive type is the P-type and the second conductive type is the N-type. When an ESD event occurs in the node ND 1  and the node ND 2  is coupled to ground, each of the equivalent diodes D 8  and D 10  are turned on in a reverse direction. Since the doping region  152  and the trigger gate  162  are electrically connected to the doping region  151 , the equivalent diode D 11  is turned on in a forward direction and the equivalent diode D 12  is turned on in the the reverse direction. Therefore, the voltage level of the well  122  is increased such that the equivalent diode D 13  is turned on in the forward direction. Since the equivalent diodes D 8 , D 10 , D 11  and D 13  are turned on, the ESD current is released from the node ND 1  to the node ND 2 . In this case, the doping region  132 , the well  122 , and the doping region  144  constitute an npn transistor. 
     When an ESD event occurs in the node ND 2  and the node ND 1  is coupled to ground, each of the equivalent diodes D 11  and D 13  are turned on in the reverse direction. Since the doping region  152  is electrically connected to the doping region  151 , the voltage level of the doping region  151  is increased such that the equivalent diode D 10  is turned on in the forward direction. Furthermore, the voltage level of the trigger gate  161  is also increased such that the equivalent diode D 9  is turned on in the reverse direction. When the equivalent diode D 9  is turned on, the voltage level of the well  121  is increased such that the equivalent diode D 8  is turned on in the forward direction. Since the equivalent diodes D 13 , D 11 , D 10  and D 8  are turned on, the ESD current is released from the node ND 2  to the node ND 1 . In this case, the doping region  131 , the well  121 , and the doping region  141  constitute an npn transistor. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.