Abstract:
A package structure includes a first carrier board provided with a through hole, at least a filling hole in communication with the through hole, a semiconductor chip received in the through hole, and a fastening member disposed in the filling hole and abutting against the semiconductor chip so as to secure the semiconductor chip in position, thereby preventing the semiconductor chip in the through hole from displacement under an external force.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a semiconductor package structure. 
     2. Description of Related Art 
     In addition to conventional wire bonding packages, the semiconductor industry developed, thanks to ever-evolving semiconductor packaging technology, various semiconductor device packages. For example, an IC semiconductor chip is directly embedded in a package substrate and electrically integrated therewith so as to reduce the whole size of the semiconductor device and enhance the electrical function thereof. Such a package type has become a mainstream. 
       FIGS. 1A to 1D  shows a method for fabricating a conventional package structure, wherein FIG.  1 A′ is a top view of FIG  1 A. 
     Referring to FIGS.  1 A and  1 A′, a first carrier board  11  having a first surface  11   a  and an opposing second surface  11   b  is provided, and a rectangular through hole  110  penetrating the first surface  11   a  and the second surface  11   b  is formed in the first carrier board  11 . As shown in the drawings, a second carrier board  12  is provided and coupled to the second surface  11   b  of the first carrier board  11 . 
     Referring to  FIG. 1B , a semiconductor chip  13  is provided, which has an active surface  13   a  with a plurality of electrode pads  131  thereon and an inactive surface  13   b  opposing the active surface  13   a . As shown in the drawing, the inactive surface  13   b  of the semiconductor chip  13  is fixed in position to the second carrier board  12  in the through hole  110  of the first carrier board  11  through an adhesion layer  14 . 
     Referring to  FIG. 1C , a dielectric layer  15  is formed on the first carrier board  11  and the active surface  13   a  of the semiconductor chip  13  by laminating. As shown in the drawing, the dielectric layer  15  fills the gap between the through hole  110  and the semiconductor chip  13 . 
     As shown in  FIG. 1D , a wiring layer  16  is formed on the dielectric layer  15 , and a plurality of conductive vias  161  are formed in the dielectric layer  15  for electrical connection with the electrode pads  131  of the semiconductor chip  13 . 
     However, in the above-described prior art, since a gap exists between the semiconductor chip  13  and the through hole  110 , the semiconductor chip  13  received in the through hole  110  may have a positional offset e caused by pressure or air bubbles created during the laminating of the dielectric layer  15 , and in consequence the positional offset e contributes to an alignment offset between the conductive vias  161  and the electrode pads  131  and even causes failure of the electrical connection therebetween. 
     Therefore, it is imperative to overcome the above-described drawbacks of the prior art. 
     SUMMARY OF THE INVENTION 
     In view of the above drawbacks of the prior art, it is an objective of the present invention to provide a package structure capable of securing a semiconductor chip in position. 
     Another objective of the present invention is to provide a package structure capable of enhancing the product yield. 
     In order to achieve the above and other objectives, the present invention provides a package structure, which comprises: a first carrier board with a first surface and a second surface opposing the first surface, a through hole penetrating the first and second surfaces, and at least a filling hole in communication with the through hole; a semiconductor chip received in the through hole with a gap existing between them, wherein the semiconductor chip has an active surface with a plurality of electrode pads thereon and an inactive surface opposing the active surface and facing the same direction as the second surface of the first carrier board; and a fastening member fixed in position to the filling hole and abutting against the semiconductor chip so as to secure the semiconductor chip in position. 
     Therein, the first carrier board is one of a core board with circuits on both sides thereof, a multi-layer circuit board, a dielectric layer and a metal plate. The through hole has a square shape, a rectangular shape, or a polygonal shape. The first carrier board has a plurality of filling holes in communication with sides and/or corners of the through hole, respectively. 
     The fastening member is fixed in position to the gap between the semiconductor chip and the through hole, or fixed in position to the filling hole and a portion of the through hole. 
     The through hole has a round shape, an oval shape or any other shape made up of curves. The fastening member is made of resin, metal, ceramic, an organic material or a cured glue, which manages to assume a fixed shape without being heated. The fastening member is made of a resin mixed filler, which needs to be heated so as to assume a fixed shape. The fastening member is made of an underfill, an epoxy resin or a photosensitive resin. The fastening member is of a columnar shape, a spherical shape, a conical shape, or an irregular three-dimensional shape. 
     The above-described structure further comprises a second carrier board coupled to the second surface of the first carrier board and the inactive surface of the semiconductor chip, a first adhesion layer is disposed on the second surface of the first carrier board to thereby be coupled to the second carrier board, and the inactive surface of the semiconductor chip is coupled to the second carrier board by means of a second adhesion layer. Alternatively, the second carrier board is coupled to the second surface of the first carrier board through a first adhesion layer, and the inactive surface of the semiconductor chip is coupled to the first adhesion layer through a second adhesion layer. The second carrier board is an insulation board, a core board with circuits on both sides thereof, a multi-layer circuit board, a dielectric layer, or a metal plate. 
     The above-described structure further comprises a build-up structure disposed on the first surface of the first carrier board and the active surface of the semiconductor chip, wherein the build-up structure comprises at least a dielectric layer, a wiring layer disposed on the dielectric layer, a plurality of conductive vias disposed in the dielectric layer and electrically connected to the wiring layer and the electrode pads of the active surface of the semiconductor chip. A plurality of electrical contact pads are provided on the wiring layer. A solder mask layer is disposed outward on the the build-up structure and has a plurality of openings for exposing the electrical contact pads, respectively. The dielectric layer is filled between the through hole and the semiconductor chip. 
     According to the present invention, the fastening member is disposed in the gap between the through hole and the semiconductor chip and abuts against the semiconductor chip so as to prevent positional offset of the semiconductor chip in the through hole as occurring in the prior art when the dielectric layer is laminated to the first carrier board and the semiconductor chip, thereby securing the semiconductor chip in position and ensuring reliable electrical connection between the conductive vias and the electrode pads of the semiconductor chip. As a result, the product yield is enhanced. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIGS. 1A to 1D  are schematic views of a method for fabricating a conventional package structure, wherein FIG.  1 A′ is a top view of  FIG. 1A ; 
         FIGS. 2A to 2D  are schematic views of a method for fabricating a package structure according to the present invention, wherein FIG.  2 A′ and FIG.  2 C′ are top views of  FIG. 2A  and  FIG. 2C , respectively, and FIG.  2 D′ is a schematic view of another embodiment of the method illustrated with  FIG. 2D ; 
       FIGS.  3  and  3 ′ are schematic views of another embodiment of a package structure according to the present invention; 
         FIGS. 4A to 4E  are perspective views of a fastening member of the package structure according to the present invention; and 
         FIG. 4F  is a schematic view of another embodiment of the fastening member according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading this specification. 
       FIGS. 2A to 2D  are schematic views of a method for fabricating a package structure according to the present invention. 
     Referring to FIGS.  2 A and  2 A′, wherein FIG.  2 A′ is a top view of  FIG. 2A , a first carrier board  21  having a first surface  21   a  and an opposing second surface  21   b  is provided, and at least a rectangular through hole  210  is formed in the first carrier board  21  to penetrate the first and second surfaces  21   a ,  21   b . As shown in the drawings, the through hole  210  is of a square shape, a polygonal shape, or any shape as needed. 
     A plurality of filling holes  210   a  are formed at the four sides of the through hole  210  to communicate therewith, wherein the filling holes  210   a  have an arc-shaped contour. 
     Subsequently, a first adhesion layer  24  is disposed on the second surface  21   b  of the first carrier board  21  to thereby be coupled to a second carrier board  22 . In the present embodiment, the first adhesion layer  24  is not formed on the second carrier board  22  in the through hole  210 . 
     The first carrier board  21  and the second carrier board  22  are each a core board with circuits on both sides thereof, a multi-layer circuit board, a dielectric layer or a metal plate. Further, the second carrier board  22  is an insulation board. Since different types of package substrates are used for embedding of semiconductor chips and they are well known in the art, detailed description thereof is omitted herein. 
     Referring to  FIG. 2B , a semiconductor chip  23  having an active surface  23   a  with a plurality of electrode pads  231  formed thereon and an inactive surface  23   b  opposing the active surface  23   a  is provided and received in the through hole  210 . As shown in the drawing, the inactive surface  23   b  is coupled to the second carrier board  22  through a second adhesion layer  25  such that the inactive surface  23   b  of the semiconductor chip  23  and the second surface  21   b  of the first carrier board  21  face the same direction. 
     As shown in FIGS.  2 C and  2 C′, wherein FIG.  2 C′ is a top view of  FIG. 2C , a plurality of fastening members  26  are disposed in the filling holes  210   a , wherein each of the fastening members  26  is of a cylindrical shape corresponding in shape to the filling holes  210   a  and protrude from the through hole  210  so as to abut against the four sides of the semiconductor chip  23 . Despite a gap d between the through hole  210  and the semiconductor chip  23 , with the fastening members  26  abutting against the sides of the semiconductor chip  23 , the semiconductor chip  23  is securely positioned in the through hole  210  and yet does not manifest any positional offset otherwise found in the prior art. 
     As shown in  FIG. 2D , a build-up structure  27  is formed on the first surface  21   a  of the first carrier board  21  and the active surface  23   a  of the semiconductor chip  23 . 
     The build-up structure  27  comprises at least a dielectric layer  271 , a wiring layer  272  formed on the dielectric layer  271 , and a plurality of conductive vias  273  formed in the dielectric layer  271  and electrically connected to the wiring layer  272 , wherein portions of the conductive vias  273   a  are electrically connected to the electrode pads  231  of the semiconductor chip  23 . A plurality of electrical contact pads  274  are formed on the wiring layer  272   a , the outermost layer of the build-up structure  27 . A solder mask layer  28  is formed outward on the build-up structure  27  and has a plurality of openings  280  for exposing the electrical contact pads  274 , respectively. 
     Further, the dielectric layer  271   a , which is the innermost layer of the build-up structure  27 , is partially filled in the gap d (as shown in FIG.  2 C′) between the through hole  210  and the semiconductor chip  23  so as to strengthen the positioning effect of the semiconductor chip  23  in the through hole  210 . 
     In the present embodiment, plated through holes (PTH) are formed in the first carrier board  21 , the second carrier board  22  and the build-up structure  27 . There are various plated through holes according to the prior art. Since related techniques are well known in the art and are not attributable to technical features of the present invention, detailed description of the related techniques is omitted herein. 
     FIG.  2 D′ shows another embodiment of the package structure. Unlike the above-described embodiment, in the present embodiment, the first adhesion layer  24  shown in FIG.  2 D′ is formed on the second carrier board  22  and the second carrier board  22  exposed from the through hole  210  such that the inactive surface  23   b  of the semiconductor chip  23  is coupled to the first adhesion layer  24  in the through hole  210  through a second adhesion layer  25 . 
     Therefore, the fastening members  26  are disposed in the filling holes  210   a  at the four sides of the through hole  210  to thereby abut against the sides of the semiconductor chip  23  received in the through hole  210  so as to prevent the semiconductor chip  23  from a positional offset which might otherwise occur, as it does according to the prior art, when the dielectric layer  271   a  is subsequently laminated to the first carrier board  21  and the semiconductor chip  23 , thereby allowing the semiconductor chip  23  to be better fixed in position to the through hole  210  and ensuring reliable electrical connection between the conductive vias  273   a  and the electrode pads  231 . 
     FIGS.  3  and  3 ′ are schematic views of another embodiment of the package structure according to the present invention. The sole difference between FIGS.  3  and  3 ′ in terms of respective embodiments illustrated therewith lies in the position and number of the filling holes  210   a . Accordingly, a detailed description of the same processes and structures is omitted herein. Referring to  FIG. 3 , two filling holes  210   a  are formed at each side of the through hole  210 , and a filling hole  210   a  is formed at each of the four corners of the through hole  210  such that a plurality of fastening members  26  are disposed in the filling holes  210   a  to abut against the semiconductor chip  23 , thereby allowing the semiconductor chip  23  to be better fixed in position to the through hole  210 . Alternatively, as shown in FIG.  3 ′, the presence of the filling holes  210   a  is limited to the four corners of the through hole  210 . 
     Referring to  FIGS. 4A to 4E , the fastening members  26  made of resin, metal, ceramic, cured glue or an organic material assume a fixed shaped without being heated. Each of the fastening members  26  is of a columnar shape, a spherical shape, a conical shape or an irregular three-dimensional shape, as shown in  FIG. 4E , allowing the fastening members  26  disposed in the filling holes  210   a  to efficiently abut against the semiconductor chip  23 . 
     Referring to  FIG. 4F , in another embodiment, a fastening members  26 ′ made of a resin mixed filler is heated at low temperature so as to assume a fixed shape. Alternatively, the fastening members  26 ′ are made of an underfill, an epoxy resin, or a photosensitive resin. With a glue (not shown) applied to the filling holes  210   a , the fastening members  26 ′ are glued to the semiconductor chip  23 ; afterward, the fastening members  26 ′ are cured by heating or UV radiation to allow the semiconductor chip  23  to be fixed in position to the through hole  210  of the first carrier board  21 , as shown in the drawing. 
     According to the above-described method, the present invention further provides a package structure comprising a first carrier board  21 , a semiconductor chip  23 , and a fastening member  26 . 
     The first carrier board  21  has a first surface  21   a , an second surface  21   b  opposing the first surface  21   a , at least a through hole  210  formed to penetrate the first surface  21   a  and the second surface  21   b , and at least a filling hole  210   a  in communication with the through hole  210 . 
     The semiconductor chip  23  is received in the through hole  210 . The semiconductor chip  23  has an active surface  23   a  with a plurality of electrode pads  231  thereon and an inactive surface  23   b  opposing the active surface  23   a.    
     The fastening member  26  fills the filling hole  210   a  to thereby abut against the semiconductor chip  23 , thereby allowing the semiconductor chip  23  to be fixed in position to the through hole  210 . 
     The package substrate further comprises a second carrier board  22  coupled to the second surface  21   b  of the first carrier board  21  through a first adhesion layer  24 , and the inactive surface  23   b  of the semiconductor chip  23  is coupled to the second carrier board  22  through a second adhesion layer  25 . 
     Referring to  FIGS. 2D  and and  2 D′ again, the package substrate further comprises the build-up structure  27  provided on the first surface  21   a  of the first carrier board  21  and the active surface  23   a  of the semiconductor chip  23 . 
     The build-up structure  27  comprises at least a dielectric layer  271 , a wiring layer  272  formed on the dielectric layer  271 , and a plurality of conductive vias  273  formed in the dielectric layer  271  and electrically connected to the wiring layer  272 , wherein portions of the conductive vias  273   a  are electrically connected to the electrode pads  231  of the semiconductor chip  23 . A plurality of electrical contact pads  274  are formed on the wiring layer  272   a , the outermost layer of the build-up structure  27 . A solder mask layer  28  is formed outward on the build-up structure  27  and has a plurality of openings  280  for exposing the electrical contact pads  274 , respectively. 
     According to the present invention, the fastening member is disposed in the filling hole and abuts against the semiconductor chip so as to prevent positional offset of the semiconductor chip as occurring in the prior art when the dielectric layer is laminated to the first carrier board and the semiconductor chip, thereby securely positioning the semiconductor chip in the through hole and ensuring reliable electrical connection between the conductive vias and the electrode pads. As a result, the product yield is enhanced. 
     The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention, Accordingly, all modifications and variations made to the embodiments by persons skilled in the art should fall within the scope of present invention defined by the appended claims.