Abstract:
A system is provided for down-converting a narrow band signal that includes a polyphase filter having a specified number of filter branches. The polyphase filter is operable to decimate the signal by a decimation factor based on the specified number of filter branches. A channel mixer is coupled to the polyphase filter. The channel mixer is periodic with a period of twice the specified number of filter branches.

Description:
TECHNICAL FIELD OF THE INVENTION 
     This invention relates generally to digital receivers and more particularly to an improved method and system for down-converting a signal. 
     BACKGROUND OF THE INVENTION 
     Communication systems send signals to communicate information, such as voice, image or other data, from one communication device to another. In many applications, the signal is modulated into an analog transmission signal that acts as a carrier wave to communicate the information. The analog transmission signal may be communicated in several different forms. For example, the analog transmission signal may be an electrical signal as used in a copper wire telephone transmission line. Alternatively, the analog transmission signal may be a radio frequency as used in wireless communication systems. 
     A typical wireless communication system generally comprises a communication device, such as a base station, satellite or the like, that communicates with another communication device over a specific radio frequency band. Conventional communication devices receive the analog transmission signal with a receiver, such as a superheterodyne receiver. A typical superheterodyne receiver includes a digital or analog down-converter that mixes the intermediate frequency signals down to baseband, or a lower intermediate frequency, and low-pass filters the mixed signals to obtain the desired result. 
     Digital down-converters generally outperform analog down-converters and are less sensitive to variations in parameters such as time, temperature and frequency. In addition, as digital technology advances, digital down-converters are requiring less power and can be manufactured at a lower cost. However, digital down-converters require high speed digital multipliers in order to function at a high sample rate. Thus, it has been difficult to take advantage of the performance of digital down-converters over a wide frequency range because of the correspondingly high sample rate which requires high speed digital multipliers to perform the mixing function. 
     For applications in which the signal bandwidth is significantly less than the tuning bandwidth, mixing and filtering are generally followed by sample rate decimation so that the sample rate is appropriate for the signal bandwidth. For applications in which the signal bandwidth is wide in comparison to the tuning bandwidth, previous down-converters have used a parallel architecture that replaces one relatively high speed multiplier with a plurality of slower multipliers. Finally, for channelizer applications that require multiple simultaneous signal channels, previous down-converters have used a polyphase filter bank with modulated filter coefficients to channelize the signal. Thus, previous down-converters require relatively low sample rates, high speed multipliers, numerous multipliers in parallel, and/or complex filtering. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a method and system for down-converting a signal are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, the present invention decimates the sample rate of the signal before filtering and mixing to digitally tune a signal without high speed multipliers or complex filtering. 
     In one embodiment of the present invention, a system is provided for down-converting a narrow band signal that includes a polyphase filter having a specified number of filter branches. The polyphase filter is operable to decimate the signal by a decimation factor based on the specified number of filter branches. A channel mixer is coupled to the filter. The channel mixer is periodic with a period of twice the specified number of filter branches. 
     In another embodiment of the present invention, a method for down-converting a wide band signal is provided that includes mixing the signal with an analog mixer to produce a mixed signal. The mixed signal is band-pass filtered to produce a band-pass filtered signal. The band-pass filtered signal is converted to a digital signal. The digital signal is decimated with a polyphase filter. The polyphase filter has a specified number of filter branches. A decimation factor for decimating the signal is based on the specified number of filter branches. The digital signal is filtered with the polyphase filter to produce a plurality of filter outputs. The filter outputs are mixed with a channel mixer. The channel mixer is periodic with a period of twice the specified number of filter branches. 
     Technical advantages of the present invention include providing an improved method and system for down-converting a signal. In particular, decimation of the data is performed before filtering, and filtering is performed before mixing. As a result, complex filtering is avoided and slower multipliers and filters may be used. This reduces the overall cost of the down-converter. Additionally, given a maximum technology limit for mixer speed, total tuning bandwidth is significantly increased. 
     Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein like numerals represent like parts, in which: 
     FIG. 1 is a block diagram illustrating a digital down-converter constructed in accordance with the teachings of the present invention; 
     FIG. 2 is a block diagram illustrating one embodiment of a filter branch and a mixer branch for the down-converter of FIG. 1; 
     FIGS. 3A-C are block diagrams illustrating embodiments of the filter and channel mixer for the down-converter of FIG. 1; and 
     FIG. 4 is a block diagram illustrating an analog/digital down-converter constructed in accordance with the teachings of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a block diagram illustrating a digital down-converter  10  constructed in accordance with the teachings of the present invention. The down-converter  10  may be part of a digital receiver for use in telecommunications applications or other suitable applications requiring a tunable band-pass filter. The down-converter  10  may be used to digitally tune a relatively narrow band signal over a wide tuning bandwidth, such as a signal with a bandwidth approximately 5% or less of the tuning bandwidth. The down-converter  10  comprises a band-pass filter  12 , an analog-to-digital converter  14 , a polyphase decimating filter  16 , a channel mixer  18  and a fine-tune mixer  20 . The down-converter  10  also comprises a real summer  22 , an imaginary summer  24 , an input terminal  30 , an in-phase output terminal  32  and a quadrature output terminal  34 . As described in more detail below, the filter  16  comprises a plurality of filter branches  40 , and the channel mixer  18  may comprise a plurality of corresponding mixer branches  42 . 
     In operation, the down-converter  10  receives a signal at the input terminal  30 . The signal is filtered by the band-pass filter  12  and converted into digital data by the analog-to-digital converter  14  before being passed through the filter  16 . In order to prevent aliasing, the bandwidth of the filter  16  is made consistent with the decimated sample rate. 
     The filter  16  comprises a plurality of filter coefficients for performing the filtering function. The filter  16  separates these filter coefficients into any specified number, M, of filter branches  40  with the filter coefficients of the kth branch  40  corresponding to the plurality of filter coefficients decimated by M and time offset by k. According to one embodiment, the first filter branch  40  receives the first filter coefficient, the second filter branch  40  receives the second filter coefficient, and so on, with the Mth filter branch  40  receiving the Mth filter coefficient. The first filter branch  40  also receives the M+1th filter coefficient, the second filter branch  40  receives the M+2th filter coefficient, and so on, so that all of the filter coefficients are distributed among the filter branches  40 . 
     The filter  16  also separates the data, sending each sample through only one of the M filter branches  40 . According to one embodiment, the filter  16  sends the first sample through the first filter branch  40 , the second sample through the second filter branch  40 , and so on, with the Mth sample being sent through the Mth filter branch  40 . The M+1th sample is then sent through the first filter branch  40 , the M+2th sample is sent through the second filter branch  40 , and so on, as long as samples are being received by the filter  16 . Thus, in addition to filtering the data, the filter  16  decimates the data by M. 
     The filter coefficients for the filter branches  40  are determined by decomposing the z-transform of a linear time-invariant filter into M components as follows:                H        (   z   )       =                ∑       h        (   n   )            z     -   n                       =                  ∑       h        (   Mn   )            z     -   Mn           +       z     -   1            ∑       h        (     Mn   +   1     )            z     -   Mn             +              …              +     z     -     (     M   -   1     )                                    ∑       h        (     Mn   +     (     M   -   1     )       )            z     -   Mn                         =                    H   0          (     z   M     )       +       z     -   1              H   1          (     z   M     )         +              …              +       z     -     (     M   -   1     )                H     M   -   1            (     z   M     )             ,                                
     where 
     
       
           H   k ( z ) =Σh ( Mn+k ) z   −n . 
       
     
     Thus, from the above decomposition, decimation by a factor of M is combined with filtering by splitting the filter  16  into M filter branches  40 , with the kth filter branch  40  having a time delay of k, and by dividing the data from the analog-to-digital converter  14  among the M filter branches  40 . This allows a slower, less expensive filter  16  to be used in the down-converter  10  because each filter branch  40  filters data at only 1/Mth the data sample rate of the down-converter  10 , allowing the use of relatively slow multipliers in the filter  16 . 
     The down-converter  10  performs mixing after decimation and filtering of the digital data. The mixing function of the down-converter  10  is separated into a periodic component in the channel mixer  18  and an aperiodic component in the fine-tune mixer  20 . The channel mixer  18  comprises a plurality of mixer coefficients for mixing the output from the filter  16 . As described in more detail below, the mixer coefficients may be included in mixer branches  42 . Let w k   m =e −j2π(m/N)k  represent the mixer coefficients used to tune the input to the mth channel, where k ranges from 0 to N−1 before the sequence repeats and where the complex value w k   m  corresponds to the W m,k  element of an N-point discrete Fourier transform (DFT) matrix W. The full set of N mixer coefficients for the mth channel is denoted by w m . 
     The real and imaginary sign and magnitude of the complex phasor w k   m  can be separated using the following notation:                w   k   m     =                  x   k   m     +     j                   y   k   m                       =                      s   R          (     m   ,   k     )              m   R          (     m   ,   k     )         +     j                     s   1          (     m   ,   k     )              m   1          (     m   ,   k     )             ,                                
     where S R (m,k), m R (m,k), S I (m,k) and m I (m,k) represent the real and imaginary sign and magnitude of the kth element of the mth channel. Separating the real and imaginary sign and magnitude of the mixer coefficients allows the symmetries of w m  to be used in order to reduce the total number of multiplies required for implementing the mixing function after the data is filtered. 
     The mixing function can be decomposed as follows:                       -       j2π      f     0          k       =            -     j2π        (       m   /   N     +     f   d       )            k                     =              -     j2π        (     m   /   N     )            k                   -       j2π      f     d          k           ,                                
     where f 0  represents the desired tuning frequency, m represents one of N tuning channels in the channel mixer  18  and f d  represents the frequency delta to be tuned within the channel by the fine-tune mixer  20 . The channel mixer  18  for the mth channel comprises a periodic sequence with period N formed from the mth harmonic w m  of the N-point DFT sequence w 1 . The N-point DFT mixer coefficients may be included in the mixer branches  42  and are assigned to the filter branches  40  after the filtering is done. As a result, only real filtering is required, which reduces the amount of filtering by half, and the mixing is performed on decimated data, which allows the use of slower multipliers. Any remaining in-channel tuning (represented by the aperiodic mixer component) is performed by the fine-tune mixer  20 . 
     Although the mixer coefficients could be assigned uniquely to each filter branch  40  if the channel mixer  18  were periodic with a period of N=M, adjacent channels would not overlap and frequencies on channel boundaries could not be received if the total bandwidth were split into N channels with each channel decimated by M=N. Therefore, the channel mixer  18  is made periodic with a period of N=2M or other suitable multiple of M. In other words, for N=2M, the total bandwidth is split into N channels with each channel decimated by M=½N. This provides fifty percent overlap in adjacent channels. While the mixer coefficients of a channel mixer  18  with period 2M cannot generally be assigned directly to a filter  16  with M filter branches  40 , the mixer coefficients can be assigned indirectly because of the fact that a DFT of length 2M has a period of M (modulo the sign), as shown below:                 -     j2π        (     m     2      M       )              (     k   +   M     )         =                -     j2π      mk       /   2        M                 -     jπ      m                                  
     Thus, for even channels, the first half of the mixer coefficients are identical to the second half. For odd channels, the magnitudes of the first and second halves of the mixer coefficients are the same, while the signs are opposite. Therefore, for even channels, the channel mixer  18  has a period of M and the mixer coefficients can be included in M mixer branches  42  that are assigned directly to the M filter branches  40 . For odd channels, an alternating positive/negative, or +1/−1, multiplier is assigned to each filter branch  40 , along with the first M of the mixer coefficients that are included in the M mixer branches  42 . “Each” means every one of at least a subset of identified items. This results in the second M of the mixer coefficients being negated during the second half of the mixing function. 
     FIG. 2 is a block diagram illustrating one embodiment of a filter branch  40  and a mixer branch  42  for the down-converter  10  of the present invention. The filter branch  40  comprises a plurality of inverse-z delay blocks  50 , a plurality of filter coefficient multiplier blocks  52 ,  54  and  56 , and a plurality of summers  58 . Although the embodiment shown in FIG. 2 includes three delay blocks  50  and three multiplier blocks  52 ,  54  and  56 , it will be understood that these delay blocks  50  and multiplier blocks  52 ,  54  and  56  may be representative of any number of delay blocks and multiplier blocks. In addition, although the embodiment shown includes a plurality of summers  58 , it will be understood that the summers  58  may be implemented as a single summer  58  without departing from the scope of the present invention. As data from the analog-to-digital converter  14  is received at filter branch #k  40 , the data is processed by the delay blocks  50 , the multiplier blocks  52 ,  54  and  56 , and the summers  58  in order to produce the filter outputs H k (z M ), as described above. 
     The mixer branch  42  comprises a real sign multiplier block  60 , a real magnitude multiplier block  62 , an imaginary sign multiplier block  64  and an imaginary magnitude multiplier block  66 . It will be understood that the sign multiplier blocks  60  and  64  may be implemented without the use of multipliers without departing from the scope of the present invention. For example, the sign multiplier blocks  60  and  64  may be implemented with sign changers or with any other component suitable for changing the sign of a piece of data. The multiplier blocks  60 ,  62 ,  64  and  66  represent the mixer coefficients for the kth branch. Data received at the mixer branch  42  from the filter branch  40  is multiplied by the real multiplier blocks  60  and  62  to produce a real output and by the imaginary multiplier blocks  64  and  66  to produce an imaginary output. The real output is sent to the real summer  22 , and the imaginary output is sent to the imaginary summer  24 . 
     As opposed to being placed downstream of the filter  16 , the mixer coefficients could be introduced at terminal  70 . However, this requires the filter  16  to provide complex filtering. As discussed above, the mixer coefficients may instead be moved downstream of the filter  16  for even channels, as illustrated by the mixer branch  42  in FIG.  2 . For odd channels, a +1/−1 multiplier can be introduced at terminal  72 , in addition to the mixer branches  42  downstream of the filter  16 . As an alternative to the +1/−1 multiplier at terminal  72 , a +1/−1 multiplier could be introduced at terminals  74  and a −1/+1 multiplier could be introduced at terminals  76 , where the terminals alternate between terminals  74  and  76 . This arrangement of alternating +1/−1 and −1/+1 multipliers is a result of the delays from one delay block  50  to the next. In yet another alternative, the −1/+1 multipliers at terminals  76  can be replaced with +1/−1 multipliers by negating the corresponding filter coefficients. According to the embodiment shown in FIG. 2, the filter branch  40  includes an even number of multiplier blocks  52 ,  54  and  56 , as indicated by the final multiplier block  56  corresponding to a terminal  76 . Thus, for this embodiment, the filter coefficients included in multiplier blocks  54  and  56  are negated. It will be understood that, for an odd number of multiplier blocks  52 ,  54  and  56 , the final multiplier block  56  would follow a terminal  74  instead of a terminal  76  and would not be negated. Thus, since each terminal  74  and  76  at each filter branch  40  in this alternative has the same +1/−1 multiplier, the +1/−1 multipliers can be pulled out of the filter branches  40  and introduced after the summers  22  and  24  at terminals  80 . 
     FIG. 3A is a block diagram illustrating one embodiment of a filter  16  and a channel mixer  18  for a down-converter  10 . According to this embodiment, each filter branch  40  has a corresponding mixer branch  42 . Each mixer branch  42  comprises real and imaginary multiplier blocks  60 ,  62 ,  64  and  66 , as described above in connection with FIG.  2 . The real magnitude multiplier block  62  for the mixer branch  42  corresponding to k=0 is simply a 1 and the imaginary magnitude multiplier block  66  is a 0 due to the fact that the mixer phasor for this first mixer branch  42  is always at either 0° or 180°. Similarly, the mixer phasor for the mixer branch  42  corresponding to k=M/2 is always at either 0°, 90°, 180° or 270°. Thus, the real magnitude multiplier block  62  and the imaginary magnitude multiplier block  66  for this mixer branch  42  are always either 1 or 0. 
     As described above, data from the analog-to-digital converter  14  is passed to the filter  16  where each sample goes through one filter branch  40  and is then passed to a corresponding mixer branch  42 . The real outputs from the mixer branches  42  are passed to the real summer  22 , and the imaginary outputs from the mixer branches  42  are passed to the imaginary summer  24 . For odd channels, the data from the summers  22  and  24  is then passed through +1/−1 multipliers  90 , and alternating filter coefficients in the filter branches  40  are negated as previously described. 
     The data from the summers  22  and  24  for even channels, or from the +1/−1 multipliers  90  for odd channels, is passed to the fine-tune mixer  20 . The fine-tune mixer  20  comprises a cosine multiplier  92 , a sine multiplier  94 , a first summer  96  and a second summer  98 . The cosine multiplier  92  multiplies the output of the real summer  22 , or the +1/−1 multipliers  90 , by cos(ω d n), where ω d  represents the frequency delta described above. The sine multiplier  94  multiplies the output of the imaginary summer  24 , or the +1/−1 multipliers  90 , by sin(ω d n). The first summer  96  subtracts the output of the sine multiplier  94  from the output of the cosine multiplier  92  to produce an in-phase output at the in-phase output terminal  32 . The second summer  98  adds the output of the cosine multiplier  92  to the output of the sine multiplier  94  to produce a quadrature output at the quadrature output terminal  34 . 
     FIG. 3B is a block diagram illustrating a second embodiment of a channel mixer  18  for down-converter  10 . According to this embodiment, a portion of the mixer coefficients are shared, making use of the symmetries in the channel mixer  18 . Thus, in this embodiment, the mixer coefficients are not included in separate mixer branches  42 . Instead, the output from a filter branch  40  is passed to a real sign multiplier block  60  and an imaginary sign multiplier block  64 . From the sign multiplier blocks  60  and  64 , the data is passed to shared magnitude multiplier blocks  62  and  66 . For systems designed using application-specific integrated circuits for the filters  16  or for systems with filters  16  specially designed to minimize the size of the filter multiplier, this embodiment substantially reduces the cost and size of the required components by reducing the mixer multipliers. 
     FIG. 3C is a block diagram illustrating a third embodiment of a channel mixer  18  for a down-converter  10 . This embodiment is a variation of the embodiment shown in FIG.  3 B. The symmetries are again used to allow sharing of the magnitude multiplier blocks  62  and  66 . However, this embodiment moves the mixer coefficients corresponding to the real magnitude multiplier blocks  62  into the filter coefficients. Thus, the filter coefficients in the filter branches  40  are multiplied by the mixer coefficients from the corresponding real magnitude multiplier blocks  62 . This allows unity gain for data from a filter branch  40  that is passed through a real sign multiplier block  60 . Mixer coefficients in the imaginary magnitude multiplier block  66  are divided by the mixer coefficients of the removed real magnitude multiplier blocks  62  because the multiplied filter coefficients affect data that is passed through the imaginary sign blocks  64 , as well as the real sign blocks  60 . 
     FIG. 4 is a block diagram illustrating an analog/digital down-converter  99  constructed in accordance with the teachings of the present invention. The analog/digital down-converter  99  comprises the same components as the digital down-converter  10 , with the exception of the fine-tune mixer  20 . Instead of the fine-tune mixer  20 , the analog/digital down-converter  99  comprises an analog mixer  100 . This down-converter  99  may be used to digitally tune a wide band signal over a wide tuning bandwidth, such as a signal with a bandwidth approximately 50% or less of the tuning bandwidth. 
     According to the embodiment shown in FIG. 4, the filter  16  and the channel mixer  18  are identical to those in the embodiment shown in FIG.  3 A. It will be understood, however, that the channel mixer  18  shown in FIGS. 3B and 3C may be used in this embodiment without departing from the scope of the present invention. In this embodiment, data received at the input terminal  30  of the down-converter  10  is passed through the analog mixer  100  before being received by the band-pass filter  12 . Using the analog mixer  100  in this manner provides full tuning flexibility which optimizes bandwidth utilization. This embodiment provides better performance than a pure analog system because the analog mixer  100  operates over a greatly reduced frequency range and avoids the requirement of a high speed digital mixer. 
     Although the present invention has been described with several embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.