Abstract:
A bandgap reference circuit incorporates first, second, and third current sources, first and second operational amplifiers, first and second bipolar transistors, a feedback device, a voltage divider, and a first resistor. The voltage divider divides a voltage difference between the third current source and the base of the second bipolar transistor to provide a reference voltage whose value is smaller than a silicon bandgap voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to reference circuits, and more specifically to a bandgap reference circuit. 
     2. Description of the Related Art 
     A bandgap reference circuit is used to generate a precise and a stable output voltage. The generated voltage is independent of process, voltage, and temperature. The bandgap reference circuit is widely used in various analog and digital circuits that require a precise voltage for operation. 
       FIG. 1  illustrates one commonly used bandgap reference circuit  100 . Referring to  FIG. 1 , the bandgap reference circuit  100  includes PMOS transistors M 1 , M 2 , and M 3 , an operational amplifier OP, resistors R 1  and R 2 , and bipolar transistors Q 1 , Q 2 , and Q 3 . If the base current is neglected, the output voltage VOUT of the bandgap reference circuit  100  can be expressed as: 
     
       
         
           
             
               
                 
                   VOUT 
                   = 
                   
                     
                       VEB 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     + 
                     
                       VT 
                       × 
                       ln 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       N 
                       × 
                       
                         ( 
                         
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     Where VEB 3  is the emitter-base voltage of the bipolar transistor Q 3 , VT is the thermal voltage at room temperature, and N is the ratio of the emitter areas of the bipolar transistor Q 2  to the emitter areas of the bipolar transistor Q 1 . 
     As can be seen from the equation (1), by adjusting the resistance ratio of resistor R 2  to R 1 , the conventional bandgap reference circuit  100  can provide a stable reference voltage VOUT having a zero temperature coefficient. The voltage level of the voltage VOUT is at around 1.25V, which is approximately equal to the silicon energy gap measured in electron volts, i.e., the silicon bandgap voltage. 
     However, in order to meet the application requirement of different integrated circuits, a reference voltage with a substantially zero temperature coefficient at the lower voltage level is needed. 
     SUMMARY OF THE INVENTION 
     An aspect of the present invention is to provide a bandgap reference circuit to provide a reference voltage having a substantially zero temperature coefficient. 
     According to one embodiment of the present invention, the bandgap reference circuit comprises first, second, and third current sources, first and second operational amplifiers, first and second bipolar transistors, a feedback device, a voltage divider, and a first resistor. The first amplifier has a first input, a second input and a first output. The second amplifier has a third input, a fourth input and a second output. The first current source is coupled between a power supply node and the inverting input of the first amplifier. The second current source is coupled between the power supply node and the non-inverting input of the first amplifier. The third current source is coupled between the power supply node and the third input of the second amplifier. The first bipolar transistor has a base, an emitter coupled to the first current source, and a collector coupled to the ground voltage. The second bipolar transistor has a base coupled to the base of the first bipolar transistor, an emitter, and a collector coupled to a ground voltage. The first resistor is coupled between the second current source and the emitter of the second bipolar transistor. The feedback device is coupled between the third current source and the base of the second bipolar transistor. The feedback device is controlled by the second output of the second amplifier. The voltage divider divides a voltage difference between the third current source and the base of the second bipolar transistor to provide a reference voltage. The fourth input of the second amplifier is couple to one of the first input of the first amplifier and the second input of the first amplifier. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will be described according to the appended drawings in which: 
         FIG. 1  illustrates one commonly used bandgap reference circuit; 
         FIG. 2  shows a schematic diagram of a bandgap reference circuit for a first embodiment of the present invention; 
         FIG. 3  shows a schematic diagram of a bandgap reference circuit for a second embodiment of the present invention; 
         FIG. 4  shows a schematic diagram of a bandgap reference circuit for a third embodiment of the present invention; and 
         FIG. 5  shows a schematic diagram of a bandgap reference circuit for a fourth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  shows a schematic diagram of a bandgap reference circuit  200  according to one embodiment of the present invention. Referring to  FIG. 2 , the bandgap reference circuit  200  comprises a current source unit  22 , an operational amplifier OP 1 , an operational amplifier OP 2 , a resistor R 1 , a bipolar transistor Q 1 , a bipolar transistor Q 2 , a feedback transistor M 4 , a voltage divider  24 , and a resistor R 4 . 
     The current source unit  22  provides a plurality of stable bias currents I 1 , I 2 , and I 3 . In this embodiment, the current source unit  22  is a current mirror formed by a plurality of PMOS transistors M 1 , M 2 , and M 3 . Referring to  FIG. 2 , the PMOS transistor M 1  has a source coupled to a supply voltage VDD, a gate coupled to an output of the operational amplifier OP 1 , and a drain coupled to an inverting input of the operational amplifier OP 1 . The PMOS transistor M 2  has a source coupled to the supply voltage VDD, a gate coupled to the output of the operational amplifier OP 1 , and a drain coupled to a non-inverting input of the operational amplifier OP 1  and a non-inverting input of the operational amplifier OP 2 . The PMOS transistor M 3  has a source coupled to the supply voltage VDD, a gate coupled to the output of the operational amplifier OP 1 , and a drain coupled to an inverting input of the operational amplifier OP 2 . 
     The bipolar transistor Q 1  has a base configured to receive a bias voltage VB, an emitter coupled to the inverting input of the operational amplifier OP 1 , and a collector coupled to a ground voltage. The bipolar transistor Q 2  has a base configured to receive the bias voltage VB, an emitter, and a collector coupled to the ground voltage. The resistor R 1  is coupled between the non-inverting input of the operational amplifier OP 1  and the emitter of the bipolar transistor Q 2 . 
     Referring to  FIG. 2 , the feedback transistor M 4  is a PMOS transistor having a source coupled to the inverting input of the operational amplifier OP 2 , a gate coupled to an output of the operational amplifier OP 2 , and a drain coupled to the base of the bipolar transistor Q 1  and the base of the bipolar transistor Q 2 . The voltage divider  24  is connected in parallel with the feedback transistor M 4 . The resistor R 4  is coupled between the voltage divider  24  and the ground voltage. 
     Referring to  FIG. 2 , the operational amplifier OP 1  and the current source unit  22  constitute a negative feedback loop which forces the voltages VD 1  and VD 2  to be substantially equal. Thus, the voltages VD 1  and VD 2  can be expressed as:
 
 VD 1= VD 2= VB +VEB1= VB +VEB2+ I 2× R 1  (2)
 
     VEB 1  is the emitter-base voltage of the bipolar transistor Q 1 , and VEB 2  is the emitter-base voltage of the bipolar transistor Q 2 . 
     Accordingly, equation (2) can rearranged into the following equation (3): 
     
       
         
           
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   = 
                   
                     
                       
                         ( 
                         
                           
                             VEB 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           - 
                           
                             VEB 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         ) 
                       
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     = 
                     
                       
                         Δ 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         VBE 
                       
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Referring to  FIG. 2 , the operational amplifier OP 2 , the current source unit  22 , and the feedback transistor M 4  constitute a negative feedback loop which forces the voltages VD 2  and VD 3  to be substantially equal. Since the gates of the PMOS transistors M 1 , M 2 , and M 3  are connected to each other, the sources of the PMOS transistors M 1 , M 2 , and M 3  are connected to the common supply voltage VDD, and the voltages at the drains of the PMOS transistors M 1 , M 2 , and M 3  are substantially equal, the currents I 1 , I 2 , and I 3  flowing through the PMOS transistors M 1 , M 2 , and M 3  are proportional to the W/L ratio of the transistors. 
     In this embodiment, the W/L ratio of the PMOS transistors M 1 , M 2 , and M 3  in the current source unit  22  is set to 1:1:m, wherein m is a positive integer. Therefore, the currents I 1  and I 2  are substantially the same and the current I 3  has m times the magnitude of the current I 2 . 
     For the purpose of conciseness, the voltage divider  24  composed of two series-connected resistors R 2  and R 3  is exemplified. However, the present invention is not limited to such a configuration. In this embodiment, the voltage divider  24  divides the voltage difference between the voltage VD 3  and the voltage VB to provide a reference voltage VREF at the cross point of the resistors R 2  and R 3 . Therefore, equation (3) can be rearranged into the following equation (4): 
     
       
         
           
             
               
                 
                   
                     
                       
                         VREF 
                         = 
                           
                         ⁢ 
                         
                           
                             
                               ( 
                               
                                 
                                   VD 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   3 
                                 
                                 - 
                                 VB 
                               
                               ) 
                             
                             × 
                             
                               ( 
                               
                                 
                                   R 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   3 
                                 
                                 
                                   
                                     R 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                   + 
                                   
                                     R 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     3 
                                   
                                 
                               
                               ) 
                             
                           
                           + 
                           VB 
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             
                               ( 
                               
                                 
                                   VD 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                                 - 
                                 VB 
                               
                               ) 
                             
                             × 
                             
                               ( 
                               
                                 
                                   R 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   3 
                                 
                                 
                                   
                                     R 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                   + 
                                   
                                     R 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     3 
                                   
                                 
                               
                               ) 
                             
                           
                           + 
                           
                             I 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                             × 
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             4 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             VEB 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                             × 
                             
                               ( 
                               
                                 
                                   R 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   3 
                                 
                                 
                                   
                                     R 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                   + 
                                   
                                     R 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     3 
                                   
                                 
                               
                               ) 
                             
                           
                           + 
                           
                             m 
                             × 
                             
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 4 
                               
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                             × 
                             Δ 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             VBE 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Since the emitter-base voltage of the transistor Q 1  has a negative temperature coefficient and the voltage difference ΔVBE has a positive temperature coefficient, the temperature coefficient of the voltage VREF can be adjusted to be positive, negative, or substantially zero. For example, the positive temperature coefficient of the voltage VREF is obtained by increasing the value of m or increasing the resistance ratio of the resistor R 4  to R 1 . The negative temperature coefficient of the voltage VREF is obtained by increasing the resistance of the resistor R 3  of the voltage divider  24 . 
     Referring to  FIG. 2 , the operational amplifier OP 1  and the operational amplifier OP 2  maintain the voltages VD 1 , VD 2  and VD 3  at substantially equal voltages by negative feedback. However, it should be obvious that the present invention is not limited to this configuration. Referring to  FIG. 3 , the non-inverting input of the operational amplifier OP 2  receives the voltage VD 1  rather than the voltage VD 2  in  FIG. 2 . Referring to  FIG. 4 , a feedback transistor M 5  is a NMOS transistor having a drain coupled to the non-inverting input of the operational amplifier OP 2 , a gate coupled to an output of the operational amplifier OP 2 , and a source coupled to the base of the bipolar transistor Q 1 . The inverting input of the operational amplifier OP 2  can be coupled to the PMOS transistor M 2  as shown in  FIG. 4 , or coupled to the PMOS transistor M 1  in another embodiment. 
     In addition, the prior art bandgap reference circuit provides a stable reference voltage VOUT having a substantially zero temperature coefficient at around 1.25V. However, the bandgap reference circuit  200  of  FIG. 2  can provide the reference voltage having a substantially zero temperature coefficient at a lower voltage level. For example, if the resistance of the resistor R 2  is equal to that of the resistor R 3 , the bandgap reference circuit  200  can provide the reference voltage VREF having a substantially zero temperature coefficient at a 0.63V by properly selecting the value of m or the resistance ratio of the resistor R 4  to R 1  according to equation (4). 
     The bandgap reference circuit  200  of  FIG. 2  provides a stable reference voltage VREF for the internal circuits. However, the present invention is not limited to this configuration. Referring to  FIG. 5 , the bandgap reference circuit  500  provides a stable reference current IREF for the internal circuits. From Equation (3), the temperature coefficient of the current IREF can be adjusted by varying the W/L ratio of the PMOS transistor M 3  to M 2  and selecting the temperature coefficient of the resistor R 1 . 
     The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the invention as recited in the following claims.