Abstract:
A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention generally relates to limiting resistor heating in semiconductors by conducting heat to the semiconductor substrate by the insertion of multiple metal levels below the resistor, increasing the size of the inactive portion of the resistor, and capturing heat rising off the top of the resistor 
     2. Background 
     Thin-film resistors of several configurations are used in microelectronics circuits. Usually, these resistors are placed relatively close to the Si substrate, being made from diffusions, polysilicon, M 1 , and thin TaN, or other resistive film near M 1 . This placement has the advantage that heat can flow with relative ease to the Si through the relatively thin insulator layer upon which they are formed. Recently, there has been a demand for placing thin film resistors farther away from the substrate, for example, above four or five levels of metal. In this position, the insulator thickness below the resistor is much greater, and provides a substantial increase in thermal resistance, which materially affects the cooling rate of the resistor during operation. 
     In addition, the insulator layers themselves may be composed of low dielectric constant (low-k) or ultra-low dielectric constant (ULK) dielectrics, which often have a lower density and therefore a lower thermal conductivity than SiO2. The combination of increased thickness and decreased thermal conductivity cause the temperature of the resistor to be significantly greater for the same current than would be the case for the resistors fabricated near the Si substrate, and over conventional SiO2. 
     The temperature increase in the resistor has two deleterious effects: 1) damage to the resistor itself, and 2) enhanced electromigration damage in nearby metal lines that become hotter due to the resistor heating. For this reason, heating in the wiring levels is limited to 5 degrees C. (which is, nonetheless, roughly equivalent to a 25% decrease in lifetime). Hence, a larger resistor width must be used to meet the required current for a given circuit, and for these upper level resistors, that width can require costly chip area. Thus, some method for controlling the temperature of the resistor is needed to make the required devices smaller. 
       FIGS. 1A and 1B  illustrate a semiconductor  100  having an Si semiconductor substrate  102 , an M 1  dielectric layer  104 , an M 2  dielectric layer  106 , an M 3  dielectric layer  108 , an M 4  dielectric layer  110 , an M 5  dielectric layer  112 , a resistor layer  114 , and an upper layer  116 . Circuit wire elements  120 , (shown on both sides of the semiconductor  100 ) are positioned within the layers M 1 -M 5 ,  104 - 112 , respectively. Cu or Al wires  122  lead to a refractory metal based resistor  124  located in a layer  114  above the M 5  layer  112 . The refractory metal based resistor  124  may include a refractory metal nitride such as TaN. A top view of a vertical footprint  126  of the resistor  124  is illustrated in  FIG. 1B . 
     Multiple insulator layers M 1 -M 5 / 104 - 112  below the resistor  124  create a high thermal resistance. Heat flow, illustrated by dashed arrow lines in a vertical downward direction in the general area and designated by reference number  130 A, is impeded and the resistor heats up with relatively small current. Heat also flows upwards, illustrated by reference number  130 B, and heats lines routed above the resistor  124 , and heat flows into the contacting Cu (or Al) lines  122  heating them as well. 
     Compared to any resistors located above M 1 , resistors located high in the stack must operate at reduced current or else they will cause earlier metallization failure by EM and/or resistor damage from the elevated temperature. Furthermore, if the dielectric layers are composed of low-k or ULK insulator, the thermal conductivity is only a fraction that of oxide, compounding the problem. Current restrictions caused by heating constraints require larger resistor size to allow the same amount of current as is used for resistors at lower levels. 
     BRIEF SUMMARY 
     An exemplary aspect of an embodiment herein comprises a structure including a semiconductor substrate having a top surface that defines a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface of the substrate. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level are physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors is aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further includes horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors. 
     Another exemplary aspect of an embodiment herein comprises a structure including a semiconductor substrate having a top surface that defines a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface of the substrate. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level are physically connected to the top surface of the substrate, and the vertical conductors form a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors are aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors. A heat shield is formed from a metal layer immediately above the resistor, where the heat shield substantially inhibits transmission of thermal radiation in an upward vertical direction from the resistor and is connected to the plurality of interconnect levels forming the heat sink immediately below the resistor. 
     Another exemplary aspect of an embodiment herein is a method of fabricating a semiconductor structure that includes providing a semiconductor substrate having a top surface that defines a horizontal direction, and stacking a plurality of interconnect levels on the top surface of the semiconductor substrate to form a heat sink. The stacking further includes forming vertical metal conductors and horizontal metal conductors in each of the interconnect levels. A resistor is provided in a layer immediately above an uppermost level of the plurality of interconnect levels such that a downward vertical resistor footprint of the resistor is substantially aligned over the plurality of interconnect levels. 
     Another exemplary aspect of an embodiment herein is a method of fabricating a semiconductor structure includes providing a semiconductor substrate having a top surface that defines a horizontal direction, and stacking a plurality of interconnect levels on the top surface of the semiconductor substrate to form a heat sink. The stacking further includes forming vertical metal conductors and horizontal metal conductors in each of the interconnect levels. A resistor is provided in a layer immediately above an uppermost level of the plurality of interconnect levels such that a downward vertical resistor footprint of the resistor is substantially aligned over the plurality of interconnect levels. A heat shield is provided immediately above and electrically isolated from the resistor that substantially inhibits thermal radiation in an upward vertical direction from the resistor. 
     With these novel features, the embodiments herein may effectively limit resistor driven temperature increase in semiconductors by conducting heat to the Si semiconductor substrate by the insertion of multiple metal levels below the resistor, increasing the size of the inactive portion of the resistor, and capturing heat rising off the top of the resistor. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of an exemplary embodiment herein with reference to the drawings, in which: 
         FIG. 1A  illustrates cross section of a semiconductor circuit chip embodiment herein; 
         FIG. 1B  illustrates a top view of a resistor of an embodiment herein; 
         FIG. 2A  illustrates cross section of a semiconductor circuit chip embodiment herein; 
         FIG. 2B  illustrates a top view of a resistor footprint and of metal conductors in the interconnect layers of an embodiment herein; 
         FIG. 3A  illustrates cross section of a semiconductor circuit chip embodiment herein; 
         FIG. 3B  illustrates a top view of a resistor footprint and of metal conductors in the interconnect layers of an embodiment herein; 
         FIG. 4A  illustrates cross section of a semiconductor circuit chip embodiment herein; 
         FIG. 4B  illustrates a top view of a resistor footprint and of metal conductors in the interconnect layers of an embodiment herein; 
         FIG. 5  illustrates cross section of a semiconductor circuit chip embodiment herein; 
         FIG. 6  illustrates cross section of a semiconductor circuit chip embodiment herein; and 
         FIG. 7  illustrates a logic flowchart of a method of fabrication of an embodiment herein. 
     
    
    
     DETAILED DESCRIPTION 
     Keeping the temperature of a resistor within the required 5° C. ensures the rate of heat conduction away from the resistor is equal to or greater than the rate of heat production within the resistor due to Joule heating. Since Joule heating is proportional to I 2 R=J 2 ρ, reduction of the current density is the most important parameter. However, for a given required current, the only way to decrease the current density is by increasing the cross-sectional area of the resistor, or in this case, since the film thicknesses are fixed, by increasing the width. Therefore, the only other option is to increase the heat flow away from the resistor by increasing the thermal conductance of the materials surrounding the resistor. Heat flows radially out from the resistor, but for thin, wide and long resistors, most of the heat flows either up or down from the resistor. The nearest heat sink is the Si substrate, so most of the heat flows towards the substrate. However, a significant amount of heat flows upward as well, heating metal levels above the resistor, and some heat flows directly into the metal level that contacts the resistor electrically. (See  FIG. 1A .) To keep the contacting metal within 5° C. above the chip temperature, the actual temperature of the resistor must also be limited to within 5° C. 
     The most direct approach to cooling is to place a stack of metal structures beneath the resistor extending from just under the resistor down to the Si substrate, (since the Si is the nearest heat sink). The topmost metal layer immediately below the resistor must not be in electrical contact with the resistor, but the vias on the bottom can contact the Si because the structure itself will not contact any other circuit components and will be electrically “floating.” Plates on the order of the size of the resistor are connected together by a dense array of vias to create a continuous Cu structure extending through all the dielectric layers to the Si. Semiconductor  200  represented in  FIGS. 2A and 2B  is similar to  FIG. 1A , and illustrates an array of parallel metal lines  202  or wires with the maximum number of vias  204  along each line placed within the resistor footprint  126  at each metal level M 1 -M 5 / 104 - 112  below the resistor  124 . Vias  204  contact to the Si substrate at reference number  206  ensuring a physical contact of the heat sink structure to the substrate. 
     Since the Si substrate is the best nearby heat sink, cooling the resistor requires creating a stack of Cu structures that reach from just under the resistor  124  down to the Si substrate  102 . Cu has a thermal conductivity of about 400 W/(cm-K) compared to 1.0 W/(cm-K) for SiO2 and even less than that for low-k insulators. Since the metal/via stacked structure  202 / 204  is electrically isolated from surrounding circuitry, it can contact the Si substrate  102 . 
     To estimate the effectiveness of this approach, one can compare the thermal resistance of the insulator stack to that of the Cu plus via stack. The following demonstrates that the thermal conductance of a layer containing the Cu plus the vias is about 155 times more thermally conductive than the insulator alone, assuming SiO2 as the insulator: 
     
       
         
           
             
               
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     These calculations assume the area of the via level to be 20% covered, and the thickness of the insulator level alone is equal to the thickness of the metal layer (115 nm) plus the thickness of the via layer (75 nm). These calculations also demonstrate that the metal/via stack is 115 times more effective at transporting heat away from the resistor for SiO2 than SiO2 alone. The thermal conductivity of the Cu plus via stack will be several times more effective in addition if the insulator is ULK, which has about 20% of the thermal conductivity of SiO2. 
     The following list is of several relevant film layer combinations and their corresponding thermal resistance: Mx oxide=19,000/tw; M 1 -M 5  oxide=95,000/tw; Mx+Via Cu=122.5/tw; M 1 -M 5  Cu=612.5/tw; Mx alone=28.75/tw; Vx alone=93.75/tw. 
     However, this may not determine the temperature of the resistor by itself, where other film thicknesses and sizes may be factors as well. There is also thermal resistance in series due to the thin layer of dielectric located between the bottom of the resistor and the next metal layer, as well as the thermal resistance to heat flowing up through the overlying oxide and out through the metal contacts. For purposes of temperature estimation, the heat flow along the resistor should be relatively small because the very thin refractory-metal-based film (˜70 nm) provides too small of a cross section to allow much heat transport. That means that the cooling through the contacting wires will be restricted to the region around the contacts. 
       FIG. 2B  demonstrates a top view of a metal conductor plate as a heat sink  202  where a metal plate with insulator fill shapes may be used to accommodate chemical mechanical polishing (CMP) requirements instead of an array of parallel lines as shown in  FIG. 2A . In this configuration, an “outrigger” portion of the metal conductor projects outside of the resistor footprint  126  to enable more rapid lateral heat spreading in a second horizontal direction. This same “outrigger” configuration is illustrated in  FIGS. 3B and 4B . 
       FIGS. 3A and 3B  illustrate a semiconductor  300  where the resistor  302  can be horizontally extended beyond the vias connecting the resistor to metal layer  122 , which enlarges the thermal footprint of the resistor without changing its resistance. For maximum heat transport effectiveness, the dimensions of the heat sink  202 / 204  that connect the proximate lower layer  112  to provide extra cooling area should be increased to match the resistor footprint.  FIG. 3B  illustrates the extended footprint  304  of the widened resistor  302  in relation to the metal conductor plate  202 . 
       FIGS. 4A and 4B  illustrate a semiconductor  400  where metal conductor plates  402 ,  404  and  406  may be made larger than the resistor footprint, and to increase in horizontal size in lower layers commensurate with the area of the thermal path (see  130 A in  FIG. 1A ), as it approaches the substrate  102 . This has the dual effect of increasing the thermal capacity of the stack and of decreasing the thermal resistance, enabling greater heat flow. 
     One or more of the plates  402 ,  404  and  406  can be made larger than plates in layers above them, making the larger lower plates having the greatest impact on the thermal resistance, since heat spreads much faster in Cu than in SiO2. Because of the high thermal conductivity of the Cu, heat will travel at least as far laterally as it does vertically as it flows down from the resistor. When the plates are made wider, the thermal footprint at the top of the Si becomes much larger, and this reduces the thermal resistance. The cost of this added thermal conductance is in wiring channels at the various metal levels, but there may be some situations where the cooling benefits outweigh the cost in loss of wiring area. If the resistor has a short wide shape, extending the resistor area to the outside of the contacts in an inactive area, (where no current is flowing through it), it will increase the thermal footprint of the resistor on the metal below, and will increase the thermal conductance. 
       FIG. 5  illustrates a semiconductor  500  where the upper heat conduction path ( 130 B as shown in  FIG. 1A ), may be blocked with an overlying metal heat shield  502  that is attached to the metal layer  202  under the resistor  124 . Most of the heat will therefore be supplied by the central region of the resistor  124  far away from the contacts  122 . Heat flowing upward can be captured by a metal layer  502  over the resistor, and then channeled downward to the stacked metal/via structure  504 / 506  to the substrate  102 . The effectiveness of this path will depend mostly on thickness of the insulator between the top of the resistor film and the bottom of the overlying metal. Contacting vias  504  of the heat shield  502  may be formed around the resistor  124 , i.e., outside of the resistor footprint  126  in a similar manner to the conductive metal plates having an “outrigger” portion outside the resistor footprint, (see  FIGS. 2A and 2B ), and connected to the underlying metal pad/wire  202 . Additionally, when the resistor is large enough, and ground rules allow it, holes  506  can also be designed through the resistor  124  to allow heat shield vias  504  to reach down through the resistor  124  to the Cu metal conductor layer  202  in layer M 5   112 . 
       FIG. 6  illustrates a semiconductor  600  where in an event that the resistor  124  is on an SOI technology, special contacts  606 / 608 , which penetrate through both the thin Si layer  604  and the buried oxide layer  602  and are electrically isolated form Si layer  604 , can be used to enhance the thermal conductance. Multiple vias  606 / 608  extend through the buried oxide layer to provide a low-resistance thermal path to the Si substrate  102 . Contacting vias as well as the special contacts  606 / 608  may also be formed around the resistor  124 , outside the resistor footprint  126 , in a manner similar to the “outrigger” portion outside the resistor footprint (see  FIGS. 2A and 2B ), and connected to the underlying substrate Si. 
       FIG. 7  illustrates a method of fabrication for a semiconductor chip that includes providing a semiconductor substrate  700  having a top surface that defines a horizontal direction and stacking a plurality of interconnect levels on the top surface of the semiconductor substrate to form a heat sink  702 . The stacking further includes forming vertical metal conductors and horizontal metal conductors in each of the interconnect levels. A resistor is provided  704  in a layer immediately above an uppermost level of the plurality of interconnect levels such that a downward vertical resistor footprint of the resistor is substantially aligned over the plurality of interconnect levels. A heat shield is provided  706  immediately above the resistor that substantially prevents thermal radiation in an upward vertical direction from the resistor. 
     With its unique and novel features, one or more embodiments herein provide effective limiting of resistor heating in semiconductor circuit chips by conducting heat to the Si substrate by the insertion of multiple metal levels below the resistor, increasing the size of the inactive portion of the resistor, and capturing heat rising off the top of the resistor. 
     The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of any embodiments herein. As used herein, the singular forms ‘a’, ‘an’ and ‘the’ are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms ‘comprises’ and/or ‘comprising,’ when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the embodiments herein has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments herein in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments herein. The embodiment was chosen and described in order to best explain the principles of the embodiments herein and the practical application, and to enable others of ordinary skill in the art to understand the embodiments herein for various embodiments with various modifications as are suited to the particular use contemplated.