Abstract:
A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.

Description:
FIELD OF THE INVENTION 
     The invention relates to the general field of power devices with particular reference to RFLDMOS devices fabricated by standard LDMOS processes and its application in Radio-Frequency (RF) ICs. 
     BACKGROUND OF THE INVENTION 
     High frequency power devices are increasingly needed as an indispensable part in modem personal communication service systems. LDMOSFETs are the only suitable devices on silicon substrates for such applications, the desirable characteristics being high frequency performance, high transconductance, and high blocking voltage. Now the focus is on faster chips that also require less power—a key requirement for extending the battery life of small, hand-held power devices that will be pervasive in the future. Relatively higher parasitic capacitance and high leakage will limit the achievable application frequency and power dissipation of RF LDMOSFET. 
     When an FET device is required to operate at high power, means must be found for dissipating the generated heat. To accomplish this, the design illustrated in FIG. 1 a  has been widely adopted in the industry. In this design, connection to the source is made though lower area  11  which occupies the entire bottom of the device, where it can be directly connected to a heat sink Lower area  11  is connected to source  10  through sinker  12 . Both  11  and  12  are of P+ silicon because P− region  14  needs to be grounded and metallic shorting bar  15  is provided in order to connect  10  to  12 . The remainder of the device is of a standard nature. Gate  16  controls the current flow in the body of the device, across channel region  13 , into the drain which is made up of an inner, lightly doped section  18  and an outer, heavily doped section  17 . 
     Unfortunately, C ds  the source-to-drain capacitance, is large in designs of the type shown in FIG. 1 a  because of the relatively thin depletion layer that forms at the N+/P− interface. One approach that has been used to overcome this problem has been the design illustrated in FIG. 1 b . Here, dielectric layer  33  is inserted between the source, drain and channel regions  10 ,  17 / 18 , and  14 , respectively. This ensures that the magnitude of C ds  will be determined by the thickness of  33  rather than by any depletion layers. 
     The SOI (silicon on insulator) structure shown in FlG.  1   b  produces devices with smaller junction area, simple Isolation structure, and steeper subthreshold-voltage slopes the bulk devices. Performance dearly profits from the consequent reduction in parasitic capacitance and leakage current, which is appropriate for high frequency and low power dissipation applications. However, at the same time, this SOI structure also has many other drawbacks, such as floating-body effect and low thermal dissipation capability. A quasi-SOI power MOSFET fabricated by reverse silicon wafer direct bonding was recently reported (Satoshi Matsumoto, et al., IEEE Transactions on Electron Devices, vol. 45, no.9, September(1998)1940-1946) to suppress the short channel effect and parasitic bipolar action. However, the device is still with the floating-body effect. Also, the fabrication process was very complicated and difficult to make compatible with standard IC process. Thus, the fabrication of such a device implies a high manufacturing cost. 
     A routine search of the prior art was performed with the following references of interest being found: 
     “Application of partially bonded SOI structure to an intelligent power device having vertical DMOSFET”—IEEE ISPSD&#39;97 p309-312 and “Modeling of self-heating effect in thin SOI and partial SOI LDMOS power devices”—Solid-State Electronics  43  (1999)1267-1280. 
     Additionally, in U.S. Pat. No. 5,338,965, Malhi shows a “partial SOI” LDMOS with oxide under the channel, drain and source. Pein (U.S. Pat. No. 5,382,818) and Pein (U.S. Pat. No. 5,378,912) both show various LDMOS devices with different oxide layer configurations. In U.S. Pat. No. 5,777,365, Yamaguchi et al. disclose an LDMOS transistor formed overlying a buried oxide layer for good electrical isolation while Malhi, in U.S. Pat. No. 5,338,965, teaches a SOI MOS combined with RESURF LDMOS. 
     SUMMARY OF THE INVENTION 
     It has been an object of at least one embodiment of the present invention to provide a semiconductor device having low parasitic capacitance while being capable of operating at relatively high power levels. 
     Another object of at least one embodiment of the present invention has bean to provide a process for the formation of a buried layer of oxide, of any shape, any size, any thickness, and at any depth. 
     These objects have been achieved by etching deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pincer occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of oxide whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS device is also described together with performance data for the resulting structure. The buried oxide layer is inserted only under the LDD and the drain regions, on top of which fabrication processes of the RF LDMOSFET proceed as usual. This structure keeps the same benefits of low parasitic capacitance, low leakage, steeper sub-threshold slope, and good isolation properties as SOI device does. At the same time, the device is “bulk-like” and can overcome the drawbacks of full SOI devices, such as floating-body effect and poor thermal dissipation properties. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 a  shows a conventional FET power device. 
     FIG. 1 b  shows an FET device modified to include full SOI isolation. 
     FIG. 2 shows an FET device modified to include partial SOI isolation. 
     FIG. 3 is the starting point for the process of the present invention. 
     FIGS. 4-7 illustrate steps in the formation of deep trenches whose inner walls are protected near the trenches&#39; mouths. 
     FIG. 8 shows how pinch-off oxidation is used to create a thick continuous layer of buried oxide. 
     FIGS. 9-10 illustrate completion of the structure by filling trenches with polysilicon. 
     FIGS. 11-14 compare various performance characteristics of a partial SOI structure, formed according to the process of the present invention, to conventional and/or full SOI structures. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention solves the problem of having both high frequency performance and good power handling capability by taking a partial SOI approach to FIG.  2  we show an example of an LDMOS device having partial SOI. As can be seen, it is similar to the device shown in FIG. 1 a  except dielectric layer  23  has been inserted between the drain region and the body of the device  18 . Unlike the prior art device of FIG. 1 b , layer  23  underlies only the outer (N+) section  17  of the drain as well as just a small part of the inner (N−) section  16 . 
     The partial SOI idea is a universal concept and several methods have been proposed for implementing partial SOI technology and partial SOI devices. Different partial SOI devices are based on different partial SOI technology. Most of these partial SOI technologies are very complicated and/or difficult to blend with standard CMOS processes. The key points for these structures ace to put an oxide layer under different junction areas, but each uses a different partial SOI technology. 
     Our partial SOI process is based on direct thermal oxide pinch-off. The oxide thickness is not limited by normal thermal oxidation constraints and can be from a few microns to tens of microns thick. The partial SOI substrate can be selectively located in any area of a device, including active areas, to reduce parasitic capacitance for high frequency performance and also cart be used to reduce the substrate losses of passive components, for example, under an inductor or transmission line when there is a high Q value requirement. Thus, the present invention has the flexibility to place a SOI substrate anywhere it may be needed, without affecting other areas of bulk silicon, and, additionally, this technology is fully compatible with standard CMOS processes. 
     We will describe the process of the present invention in terms of the formation of a RFLDMOS FET but it will be understood that the process is of a general nature and may be employed wherever there is need for a buried layer of insulation of limited area. 
     We begin our description by referring to FIG. 3 which shows the structure of FIG. 2 in its early stages, namely after P− silicon layer  14  has been epitaxially deposited onto P+ silicon substrate  11  (not inducted in FIG.  3 ). Silicon oxide layer  30  (thickness between about 0.3 and 0.7 microns) is then formed on the surface of layer  14  followed by the deposition thereon of silicon nitride layer  31  to a thickness between about 0.1 and 0.2 microns. Then second layer of silicon oxide  32  is deposited onto layer  31 . Layer  32  is between about 0.3 and 0.7 microns thick and is formed from LPCVD (low pressure chemical vapor deposition) of tetraethylorthosilicate (TEOX). 
     After suitable photolithographic patterning, layer  32  becomes a hard mask shaped to define a set of trenches  4 , as seen in FIG.  4 . Each trench has a width between about 0.3 and 1.5 microns and could be located anywhere on the wafer surface but, for the specific case of the LDMOS device, they extend inwards from one side (away from the right edge in the current example). Trench depth at this stage was between about 0.3 and 1.5 microns. 
     Note that the width of the trenches and the distance between trenches cannot be varied independently. If, for a given width, the trenches are too far apart then pinch-off will occur inside the trenches first and not all silicon between trenches will get oxidized. Conversely, if the trenches are too dose together pinch-off will occur first within the silicon body and the trenches will not become completely filled with oxide. We have determined that pinch-off can be made to occur simultaneously in both regions if the trench separation distance is about 1.1 times the trench width. 
     Referring first to FIG. 5, two-layer laminate  41 / 42  (silicon oxide layer  42  on (silicon nitride layer  41 ) is deposited on all an surfaces, following which laminate  49 / 42  is selectively removed from all horizontal surfaces (see FIG.  6 ). Layer  42  is between about 0.01 and 0.02 microns thick while layer  41  is between about 0.01 and 0.03 microns thick, for a total laminate thickness between about 0.02 and 0.05 microns Then, using layers  30 - 32  and  41 / 42  as a hard mask, trench etching is resumed so that deeper trenches  70  result, as shown in FIG.  7 . For etching the second portion of the trenches we have used a mix of C 4 F 8  and SF 6  in an inductive coupled (ICP) RIE (Reactive Ion Etching) system. Typical operating conditions were: pressure 15 mtorr; ICP coil power 800 W; bias power 15 W; C 4 F 8  flow rate 90 SCCM; SF 6  flow rate 40 SCCM. This resulted in an etch rate of about 0.3-0.4 microns/minute. During etching the nitride spacer is also attacked, but more slowly, its etch rate being about 10-15 times slower than for the oxide and about 15-20 times slower than for the resist. 
     The additional depth that has been added is between about 0.5 and 15 microns. A key feature of the deeper trenches is that the sidewalls at the top (where the initial trenches were) retains its protective two layer laminate  41 / 42 . 
     Referring now to FIG. 8, all exposed silicon surfaces are now thermally oxidized. Oxide then grows both inwards and outwards away from the sidewalls of the second trench set oxidation being continued until the newly formed oxide layers meet and are pinched off, both inside the trenches and inside the surrounding material. The result is continuous silicon oxide layer  88  whose upper surface is parallel to the top surface of silicon  14 , whose thickness is between about 0.5 and 16 microns, and whose location has been determined by the placement of the original trenches  4 . 
     Next, as seen in FIG. 9, two layer laminate  41 / 42  is removed so that the original trenches  4  are restored. These are then overfilled with polysilicon  99 , following which a planarizing etch, with overetching, is used to remove all excess polysilicon above the surface of silicon  14 . For the planarizing etch we have used RIE etch-back. Hard mask  30 - 32  is then removed giving the structure the appearance shown in FIG. 10 where polysilicon regions  99  are no longer shown as being distinct from any other silicon regions of body  14 . 
     To complete formation of the LDMOS device, the standard manufacturing process is resumed, A sinker  12  (see FIG. 2) of P+ silicon that extends away from the left edge (in this example) is formed. Then, layer of N− silicon  18  is formed as shown in FIG. 2 following which the N+ areas  10  and  17  get formed, in the locations shown, through a mask. Layer of gate oxide  19  is formed over the gap  13  (between  10  and  18  i.e. the channel area) with gate electrode  16  being formed above it. Metallic contacts  15  to  10  and  17  are then formed and the process is complete. If the above-described process is implemented as we have described, the resulting field effect transistor will have a cutoff frequency greater than about 10 Ghz. Additionally, its thermal dissipation capability will be such that it can operate at a power level between about 0.5 and 60 watts. 
     RESULTS 
     (a) Parasitic capacitance and leakage 
     FIG. 11 compares simulated C-V plots for bulk, SOI and partial SOI devices as a function of drain bias. The thickness of the buried oxide layer was 1.0 micron for the partial SOI and full SOI devices. As seen from the plots, Cds in the conventional bulk structure at zero bias is 4.7 pf/cm (curve  114 ), compared to 1.37 pf/cm in the partial SOI structure (curve  113 ), a decease of 70%, and is almost the same as that of the full SOI structure (curve  112 ). More important, the flat Cds curve is easy to match and so facilitates RF 
     It is much easier to get a thicker oxide layer for the partial SOI device, than it is for conventional full SOI technology. FIG. 12 is a comparison of the simulated C-V plots for SOI and partial SOI devices for different buried oxide thickness. The thickness of the buried oxide was 3.0 micron for partial SOI (curve  122 ) and 1.0 micron for full SOI devices (curve  121 ). At a source-drain voltage of 3.6 V, the drain to source capacitance in the full SOI structure is 1.02 pF/cm, while it is only 0.65 pF/cm in the partial SOI structure. 
     FIG. 13 compares simulated leakage plots for bulk and partial SOI devices. As can be seen, there is a significant reduction in leakage for the partial SOI device. 
     (b) Thermal Dissipation Characteristics 
     Full SOI MOSFETs suffer from self-heating effects due to the low thermal conductance of the buried oxide. At high power levels, this leads to the onset of negative output conductance in the saturation region. This behavior is mainly attributed to a reduction in mobility with increasing channel temperature resulting from self heating. Threshold voltage shifts with the increasing temperature, thereby causing a high sub-threshold current in the off state. 
     Non-isothermal simulations were carried out to study any variations in the performance of the device due to increase in its internal temperature caused by self heating. The results confirmed that temperature increases due to self-heating in partial SOI structure is much lower than that in a conventional SOI structure. The highest temperature in a partial SOI structure was 67° C., a decease of 65% relative to a normal SOI structure. 
     (c) Breakdown 
     One of the major obstacles facing full SOI MOSFETs is the low drain breakdown voltages that the N-channel devices suffer from this premature breakdown in full SOI MOSFETs is due to punch-through or to a parasitic bipolar transistor which is triggered by the impact ionization charging of the film body. The problem does not arise in the partial SOI devices. 
     (d) Kink effect 
     The kink seen in the saturation-region I ds -V ds characteristics of floating-body SOI MOSFET&#39;s is a result of the decease in the threshold voltage V th  caused by forward-biasing of the source-body junction. Impact ionization in the high-drain-field region injects holes into the floating body, and the concomitant stored charge induces the forward bias. The kink effect is one of the main floating body effects that are triggered by impact ionization charging of the film body. This leads to an excess drain current in saturation. FIG. 14 shows the simulated I ds -V ds  characteristics of fully SOL (curves  141 ) and partial SOI devices (curves  142 ), an obvious kink effect In fully SOI device being indicates.