Abstract:
A neural network system includes a random access memory (RAM); and an index-based weightless neural network with a columnar topography; wherein patterns of binary connections and values of output nodes&#39; activities are stored in the RAM. Information is processed by pattern recognition using the neural network by storing a plurality of output patterns to be recognized in a pattern index; accepting an input pattern and dividing the input pattern into a plurality of components; and processing each component according to the pattern index to identify a recognized output pattern corresponding to the input pattern.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention  
     The invention relates to a pattern recognition device that has an index-based weightless neural network with a columnar topography, and to a method whereby an input pattern is divided into a plurality of components and each component is processed to identify a recognized output pattern corresponding to the input pattern. 
     An artificial neural network is a structure composed of a number of interconnected units typically referred to as artificial neurons. Each unit has an input/output characteristic and implements a local computation or function. The output of any unit can be determined by its input/output characteristic and its interconnection with other units. Typically the unit input/output characteristics are relatively simple. 
     There are three major problems associated with artificial neural networks, namely: (a) scaling and hardware size practical limits; (b) network topology; and (c) training. The scaling and hardware size problem arises because there is a relationship between application complexity and artificial neural network size, such that scaling to accommodate a high resolution image may require hardware resources which exceed practical limits. 
     The network topology problem arises due to the fact that, although the overall function or functionality achieved is determined by the network topology, there are no clear rules or design guidelines for arbitrary application. 
     The training problem arises because training is difficult to accomplish. 
     The n-Tuple Classifier has been proposed in an attempt to address these problems. This classifier was the first suggested RAM-based neural network concept. The first hardware implementation of the n-Tuple Concept was the WISARD system developed at Brunel University around 1979 (see “Computer Vision Systems for Industry: Comparisons,” appearing as Chapter 10 in “Computer Vision Systems for Industry,” I. Alexander, T. Stonham and B. Wilkie, 1982). The WISARD system belongs to the class of RAM-based weightless neural networks. This style of neural network addresses the problem of massive computations-based training by writing the data into a RAM-network and the problem of topology by suggesting a universal RAM-based network structure. However, the network topology of WISARD-type universal structure leads to inefficient use of memory with the consequence that the problem of scaling still remains acute within RAM-based neural networks, and the application range of the WISARD-technology is limited. 
     Another example of neural networks that overcomes the problem of training by a simple memorization task is Sparse Distributed Memory (P. Kanerva, 1998, “Sparse Distributed Memory,” Cambridge, Mass.: MIT Press). However, a problem with the Sparse Distributed Memory, as with the WISARD system, is a large memory size. Another disadvantage of the Sparse Distributed Memory is its computational complexity. This is because for this type of memory, an input word must be compared to all memory locations. 
     N-Tuple classification systems use a method of recognition whereby an input to the neural network is divided into a number of components (n-Tuples) with each component addressing a respective one of a series of component look-up tables. Each memory cell of the RAM stores a discriminator word that has as many bits in it as there are pattern classes. Whenever a pattern is present at the input, each component addresses just one of its discriminator words. The network totals the number of 1s addressed in each bit position and recognizes the pattern as the class that gives the biggest score (see “Computer Vision Systems for Industry: Comparisons,” appearing as Chapter 10 in “Computer Vision Systems for Industry,” I. Alexander, T. Stonham and B. Wilkie, 1982, page 189). 
     The presence of a number of look-up tables results in a potentially large memory size. The memory size required is proportional to the number of components which the network may identify. This can result in a substantial increase in memory where the pattern size increases. For example, an artificial neural network might be designed for an image processing application, initially using an n×n image, where n=128. This is a relatively low-resolution image by today&#39;s standards. Where the image to be processed increases from n=128 to n=2048 , the size of the network increases by a factor of 256. This increase in memory results in the requirement for network expansion potentially requiring additional hardware modular blocks. Where the resolution of the image increases a point is quickly reached where the scaling to accommodate a high resolution image is beyond a practically achievable memory limit. 
     An object of the present invention is to address, overcome or alleviate some or all of the disadvantages present in the prior art. 
     BRIEF SUMMARY OF THE INVENTION 
     According to a first aspect of the invention, there is provided a RAM-based weightless neural network device for classifying an input pattern as corresponding to one of a plurality of output patterns, comprising an input arranged to decompose an input pattern into a plurality of components, and RAM storing, for each component, a plurality of output pattern indications defining a column corresponding to the component, and having address lines so as to form a look-up table, the address lines being addressed by each of the components, characterized in that the RAM comprises a RAM for storing a plurality of address entities defining a linked data representation to represent the component, and in that a logic device is provided for causing sequential accessing of the plurality of address entries. 
     The n-Tuple Classifier of the prior art requires the height of columns (i.e., the number of output pattern class indicators they store) to be flat and predetermined. For instance, if just a few columns are tall (i.e., containing many output pattern indications) whereas most columns are short, then the allocated memory is mostly wasted. In contrast, the variable columnar height of embodiments of the invention, achieved by the use of the linked data structure, takes up less total memory. 
     Preferably, the neural network hardware component is a computer hardware component. 
     In a preferred form the neural network hardware component has potential for scaling. Scaling may be achieved in any suitable manner. It is preferred that systematic expansion is achieved by increasing the size of the RAM. 
     The neural network may be trained in any suitable manner. It is preferred that the neural network is trained by writing of data into the RAM and network topology emerges during the training. 
     It is preferred that performance of the neural network is adjustable by changing decomposition style of input data, and thereby changing dynamic range of input components. 
     It is preferred that input components to the neural network address a single common index. 
     According to a second aspect of the invention, there is provided a method of processing an input pattern by pattern recognition using a neural network storing an index to identify a recognized output pattern corresponding to the input pattern, the method including the steps of—
         (a) storing a plurality of output pattern indications, each corresponding to an output pattern to be recognized;   (b) accepting an input pattern;   (c) dividing the input pattern into a plurality of components; and   (d) processing each component according to the index, the processing comprising, for each component:
           (1) looking up, in RAM, a first link associated with a first output pattern;   (2) using the first link to look up, in RAM, a second link associated with a second output pattern; and   (3) for each link looked up, increasing a corresponding stored score corresponding to the associated output pattern.   
               

     Preferably each output pattern is divided into a plurality of recognized components with each recognized component being stored in the pattern index for recognition. The index preferably consists of columns with each column corresponding to one or more recognized components. Preferably the index is divided into a number of columns which is equal to or less than the number of recognized components. More preferably, the index is divided into a number of columns which is equal to the number of recognized components. 
     The method may further include the steps of each input component being compared to the corresponding recognized component column, and a score being allocated to one or more recognized components. Preferably the score for each recognized component of a pattern is added and the recognized pattern with the highest score is identified as the output pattern. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The invention will now be described in further detail by reference to the attached drawings which show an example form of the invention. It is to be understood that the specificity of the following description does not limit the generality of the foregoing disclosure. 
         FIG. 1  is an index table illustrating recognition processing according to one embodiment of the invention. 
         FIG. 2  is a schematic block diagram illustrating a read cycle process according to that embodiment of the invention. 
         FIG. 3  is a schematic block diagram illustrating processing of a write cycle process output according to that embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention can be implemented through the use of a neural card built with the use of standard digital chips. The invention is an index-based weightless neural network with a columnar topology that stores in RAM the indications of output patterns. The network offers:
         (a) Scaling potential: Systematic expansion of the neural network can be achieved not by adding extra modular building blocks as in previous artificial neural networks, but by increasing the RAM size to include additional columns or by increasing the height of the index. For example, 16 million connections can be implemented with a 64 MB RAM.   (b) The required memory size is reduced by a factor of N, when compared with previous n-Tuple systems such as the WISARD system, with N being the number of input components (n-Tuples).   (c) The network topology emerges automatically during the training.   (d) Training is reduced to writing of data into RAM.   (e) The performance can easily be adjusted by changing the dynamic range of input components, which can be achieved by changing the decomposition style of input data.       

     A device made according to the present embodiment is herein referred to as a Neural Cortex by the inventors. A general view of the single common index on which the present invention is based can best be described as a collection of vertical columns, wherein the signals propagate in a bottom-to-top fashion. 
     Unlike traditional RAM-based neural networks, the present embodiment operates by creating and memorizing an index (a linked data representation) of input components. This index is created on training. 
     On retrieval, the present embodiment, like the prior art n-Tuple Classifier, sums up the number of times each output class pattern was activated by input components. The summing operation provides the generalizing ability typical of neural networks. However, unlike the prior art n-Tuple Classifier, the present embodiment uses a single common storage. In the case of the prior art n-Tuple Classifier, each input component (n-tuple) addresses its own look-up table. In the case of the described embodiment, all input components address a single common index. This brings about a dramatic decrease in memory size. The absence of a single common index in both the n-Tuple Classifier and the Sparse Distributed Memory systems explains why previous RAM-based neural networks had difficulties in terms of memory requirements whose large size significantly limited the application range. 
     Further, a single common index according to a preferred and described embodiment is an efficient solution to the neural network expansion problem. As has been indicated above, both traditional artificial neural networks and traditional RAM-based artificial neural networks have scaling difficulties when the application size grows. For instance, if the image size grows from 128×128 pixels to 2048×2048, then a traditional artificial neural networks will need a 256-fold increase in memory because the number of n-tuples increases by the factor of 256=2048*2048/128*128. However, paradoxically, in the same situation, the memory size according to the present embodiment may remain unchanged because still only one common index is used. 
     The present embodiment creates a single pattern index ( 104 ) of input components. The index contains the output components and is created by storing the output pattern and training the neurons to recognize the pattern stored within the pattern index. 
     An output pattern S is decomposed into N number of components S 1 , S 2 , S N  (each having a reference number), such that each component S i  is interpreted as the address of a column ( 106   1 ,  106   2 , . . .  106   1 , . . .  106   N ) from the index ( 104 ). Each column stores entries ( 107   1 ,  107   2 ) containing the reference number of those patterns which have the value S i  in one or more of their components; each column does not contain more than one sample of each reference number. When an input I ( 100 ) is received, this is divided into a number of components I 1 , I 2 , . . . ,I X . Each input component I 1 , to I X  is processed by the network by inputting the component with the pattern index ( 104 ) via an address selector ( 102 ). Where a component of the input I i  produces a component of the output S i , then each reference number listed ( 107   1 ,  107   2 ) in the column ( 106   i ) of S i  has a score of one added to its total. This process is repeated for each of the input components. The scores are then added to determine the winner. The winner is the reference number with the greatest score. The reference number, corresponding to a recognized output pattern, is recognized by the network. 
     An example of the device containing the pattern index is illustrated in  FIG. 1 . This figure illustrates where the device has been trained or programmed to recognize three words “background,” “variable” and “mouse.” In this figure the words are assigned the reference numbers  1 ,  2  and  3  respectively. The output patterns are letters from “a” to “z” with these included as columns ( 106 ) within the index ( 104 ). When an input ( 100 ) is received by the network, each of the components of the input is processed by reference to this single pattern index. In this example the input is in the form of the word “mouse.” This input ( 100 ) is subsequently broken down into five letters (the input components). Each letter is processed in the network by using the index ( 104 ). The nature of processing undertaken in the network can ensure that processing of each component is undertaken virtually simultaneously. The following processing is undertaken—
         (a) the component of the input “m” is processed and in this case one point is added to the score attributable to reference number  3  (corresponding to output pattern “mouse”);   (b) the component input “o” is processed and one point is added to the scores attributable to reference numbers  1  and  3  (corresponding to output patterns “background” and “mouse”);   (c) the component input “u” is processed and one point is added to the scores attributable to reference numbers  1  and  3  (corresponding to output patterns “background” and “mouse”);   (d) the component input “s” is processed and one point is added to the scores attributable to reference number  3  (corresponding to output pattern “mouse”);   (e) the component input “e” is processed and one point is added to the scores attributable to reference numbers  2  and  3  (corresponding to output patterns “variable” and “mouse”).       

     The network then sums up (not shown in this figure) the points attributable to each variable. In this instance variable  1  has a score of 2, variable  2  a score of 1 and variable  3  has a score of 5. The variable with the highest score is determined to be the winner and hence identified. The variable  3  which has a score of 5, corresponding to the word “mouse,” is, therefore, considered to be identified. 
     In the case of standard RAM according to the prior art, two different address words (i.e., input pattern components) always point towards two different memory locations. This is no longer true in the case of the described embodiment which uses a single index. For example, if the input pattern has three components (a, b, c) and the component dynamic range is 1 byte then the patterns (a, c, b), (b, a, c), (b, c, a), (c, a, b), (c, b, a) will produce the same score equal to 3 because the device according to the present embodiment is invariant with respect to permutations. The invariance is caused by the fact that all input components (n-tuples) address a single common index, thus creating the permutational invariance, which is the price to be paid for dramatic reduction in memory size as compared to traditional RAM-based neural networks. This invariance becomes practically harmless when the component dynamic range is increased. For the above example, by increasing the component dynamic range from 1 byte to 2 bytes, where the pattern (a, b, c) is converted into the 2 component pattern (ab, bc), the following scores will be obtained: (a, b, c)=&gt;2, (a, c, b)=&gt;0, (b, a, c)=&gt;0, (b, c, a)=&gt;1, (c, a, b)=&gt;1, (c, b, a)=&gt;0, so that the pattern (a, b, c) will be identified correctly. 
     In general case, the conversion of the n-component input pattern (s 1 , s 2 , . . . , s N ) into a new pattern (c 1 , c 2 , . . . , c M ) whose components have a greater dynamic range and M&lt;N is preferably done by the software driver of the card of the present embodiment. 
     A read-cycle block-diagram of the embodiment is shown in  FIG. 2 . The blocks “Roots” ( 110 ), “Links” ( 120 ), “Names” ( 130 ), “Score” ( 140 ) are RAM-devices. Σ( 150 ) is a summer. T-logic ( 160 ) is a terminating logical device.
         1. Each pattern component (A-Word) is passed to the address bus of the “Roots” RAM ( 110 ).   2. The output value R of the “Roots” RAM ( 110 ) is passed to the address bus of the “Links” RAM ( 120 ).   3. The output value L of the “Links” RAM ( 120 ) is passed to the address bus of the “Names” RAM ( 130 ).   4. And, finally, the output value N of the “Names” RAM ( 130 ) is passed to the address bus of the “Score” RAM ( 140 ).       

     If L is 0 then the T-logic ( 160 ) terminates the process. Otherwise, the “Score” RAM ( 140 ) content found at address N that is determined by the output of the “Name” RAM is incremented by the value of 1. Next, the “Links” RAM ( 120 ) output is fed back to the “Links” RAM ( 120 ) address bus. The process repeats itself from point 3. 
     A corresponding write-cycle block-diagram is shown in  FIG. 3 . CU is the control unit ( 170 ).
         1. Each pattern component A is passed to the address bus of the “Roots” RAM ( 110 ).   2. The output value R of the “Roots” RAM ( 110 ) is passed to the address-bus of the “Links” RAM ( 120 ).   3. The output value L of the “Links” RAM ( 120 ) is passed to the address-bus of the “Names” RAM ( 130 ). The output value of the “Names” RAM ( 130 ) is denoted by N, and the current pattern name by P.   4. The values R, L, N and P are passed to the control unit  170 , which utilizes the following logic. If L is 0 then the control unit makes a decision (point 5) on updating “Roots,” “Links,” and “Names” RAM ( 130 ). Otherwise, L is fed back to the “Links” RAM ( 120 ) address bus. The process repeats itself from point 3.   5. Decision Logic:
           a) if N=P, terminate the process;
               if R=0, increment the counter value C by 1,
                   write C to “Roots” RAM ( 110 ) at address A,   write C to “Links” RAM ( 120 ) at address R,   write P to “Names” RAM ( 130 ) at address L,   
                   if R&gt;0 &amp; L=0, increment the counter ( 180 ) value C by 1,
                   write C to “Links” RAM ( 120 ) at address R,   write P to “Names” RAM ( 130 ) at address L,   
                   
               b) terminate the process.   
               

     Performance of the embodiment can be adjusted in terms of memory size and read/write times. Normally, storage and recall times increase when the number of classes grows as the training continues. Additional classes increase the amount of reference numbers that are stored in index columns and, therefore, the amount of index cells that have to be accessed. As a remedy, one can increase the dynamic range D of input pattern components. This increases the number of index columns because the index address space is equal to D. As a result, the same amount of reference numbers will be spread upon the greater area, which, in turn, decreases the average index height H. 
     The processing time on storage and recall is proportional to the number of accessed memory cells, which is proportional to HN. Here, N is the number of the pattern components. As D increases, the processing time approaches O(N). This follows from the fact that H is inversely proportional to D. 
     The memory size is proportional to HD. However, H grows/decreases faster than D. Hence, adjusting the dynamic range D can efficiently control the memory size. In the worst case, the memory size does not exceed CD, where C is the number of pattern classes, which is because the embodiment has only one “look-up-table.” On the other hand, the memory size of a traditional RAM-based artificial neural network is CDN because for this type of artificial neural network the number of input look-up-tables is equal to the number N of input pattern components. 
     It is to be understood that various modifications, alterations and/or additions may be made to the parts previously described without departing from the ambit of the present invention.