Abstract:
A semiconductor IC device has word lines which are sequentially arranged and each connected to the gate of a MOS transistor such that its drain and source are individually connected to the adjacent word lines. Either of these adjacent word lines is connected to a fixed potential source such that potential changes in selected one of these word lines are electrically shielded and do not affect the non-selected other word lines in the device.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a semiconductor integrated circuit (IC) device having a plurality of line selection signal lines (hereinafter referred to as word lines) and more particularly to such a semiconductor IC device which can prevent the voltage changes in a selected word line from affecting the adjacent non-selected word lines. 
     There are semiconductor IC devices in which many memory cells are arranged in a matrix formation within a chip such that one of these memory cells can be selected by means of an address signal for writing information on it or reading information from it. FIG. 2 shows a known word line selection circuit used in connection with a semiconductor IC circuit of this kind, having a large number of word lines W 1 , W 2 , . . . (only four word lines W 1  -W 4  shown for the purpose of explanation) disposed parallel with respect to one another and many memory cells connected to each of these word lines. 
     In order that a desired one of these word lines can be selected, each of the lines W 1  -W 4  has one end connected to one of MOS transistors T 11  -T 14  and also one of MOS transistors T 21  -T 24 . The other terminals of the MOS transistors T 11  -T 14  are grounded, their gates being connected respectively to the NAND output of a line decoder P 1  or P 2  and the other terminals of the other MOS transistors T 21  -T 24  are connected to a set of word line driving circuits D 1  and D 2 . The gates of the MOS transistors T 21  -T 24  are connected to the output terminals of the inverters I 1  and I 2  through MOS transistors which serve as loads. The outputs from the aforementioned NAND gates P 1  and P 2  are applied to the input terminals of these inverters I 1  and I 2 . 
     With a group of word lines thus structured, pairs of mutually adjacent lines such as W 1  and W 2 , or W 3  and W 4 , may be considered to form a set. Within each of these sets, an output signal from a same NAND gate such as P 1  or P 2  is applied to the gates of MOS transistors T 11  and T 12  or T 13  and T 14  and an inverse output signal to the gates of MOS transistors T 21  and T 22  or T 23  and T 24  through the inverter I 1  or I 2 . One of each set of word lines such as W 1  and W 3  is connected to a first word line driving circuit D 1  and the other such as W 2  and W 4  to a second word line driving circuit D 2 . 
     Operation of the circuit described above is explained next for the situation where the word line W 2  is selected. 
     In the beginning, the outputs from the NAND gates P 1  and P 2  are maintained at high levels, the outputs of the inverters I 1  and I 2  at low levels and the outputs of the word line driving circuits D 1  and D 2  also at low levels. When the word line W 2  is selected, the output from the line decoder P 1  connected to it changes to a low level and that of the inverter I 1  therefore becomes high such that the MOS transistors T 21  and T 22  are switched on. Thereafter, a high-level selection signal is outputted from the second word line driving circuit D 2  and this signal reaches the word line W 2  through the MOS transistor T 12 . During this process, the word line W 1 , to which the output from the same MAND gate P 1  is applied, is kept at a low level through the MOS transistor T 21  by the first word line driving circuit D 1  and the other word lines W 3  and W 4 , to which the output from the NAND gate P 2  is applied are kepy at low levels respectively through the MOST transistors T 13  and T 14 . In summary, the voltage levels of the adjacent word lines W 1 , W 3  and W 4  do not rise due to capacitance between the lines (inter-line capacitance) even if the level of the word line W 2  is raised when this line is selected. 
     When a circuit of the aforementioned type is actually designed, however, the separations between adjacent word lines are controlled by the size of the memory cells and other factors and it is difficult to arrange MOS transistors within a limited space and to connect wires to their gates in order to apply signals from NAND gates to them. Recently, extremely small memory cells are coming to be used, for example, in dynamic RAMs. In such devices, separations between word lines become accordingly smaller and it becomes a serious problem to arrange MOS transistors properly inside such a device. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a semiconductor IC device with a line selection circuit which can be laid out easily even if separations between word lines are small. 
     It is another object of the present invention to provide a semiconductor IC device with such a line selection circuit that the voltage levels of non-selected word lines are not influenced by the voltage changes of a selected word line through the inter-line capacitance. 
     The above and other objects of the present invention are achieved by forming a semiconductor IC device with MOS transistors such that a selected word line will be connected to the gate of one of them and the non-selected word lines adjacent to this selected word line will be connected to its source or drain and further such that at least one of these non-selected word lines is set at a fixed voltage level. 
     When a word line is selected with a circuit structured as described above, the selection signal serves to switch on the MOS transistor of which the gate is connected to the selected word line. The non-selected word lines adjacent to this selected word line remain at a low level, however, because at least one of them is maintained at a fixed voltage and this fixed voltage is applied to the other of them through the aforementioned MOS transistor which has been switched on, thereby electrically shielding the selected word line. 
     In summary, effects of inter-line capacitance do not appear on non-selected word lines even when the voltage level of a selected word line changes. The circuit pattern becomes extremely easy to lay out, furthermore, because the gate, source and drain of each MOS transistor for selecting or not selecting a word line are required to be in contact only with mutually adjacent word lines and hence the connecting lines for these MOS transistors need not be passed between the word lines. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated in and form a part of the specification, illustrate an embodiment of the present invention and, together with the description, serve to explain the principles of the invention. In the drawings: 
     FIG. 1 is a circuit diagram of a line selecting circuit for a memory device according to the present invention, and 
     FIG. 2 is a circuit diagram of a known line selecting circuit. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In what follows, the present invention is explained by way of FIG. 1 which describes a circuit for selecting one of a plurality of word lines. Such circuits may be used conveniently in connection with an integrated circuit having many unit circuits such as memory cells arranged in a matrix formation such that any one of them can be selected by specifying its row and column. 
     With reference to FIG. 1, word lines W i  (i=1,2, . . . N) are nearly parallel to one another and each of them (W i ) is connected at one end through a MOS transistor T 2i  to a first word line driving circuit D 1  if i is odd (or if i=2n-1 where n is a positive integer 1,2, . . . ) or to a second word line driving circuit D 2  if i is even (or i=2n). Each of the aforementioned MOS transistors T 2i  has its gate connected to the output terminal of a line decoder through a load MOS transistor. Since there are two word line driving circuits D 1  and D 2  as described above, the word lines are paired to form a plurality of groups such that each group contains two word lines and than the (2n-1)st and (2n)th word lines are combined to form the nth group. For example, word lines W 1  and W 2  are combined to form a (first) group and word lines W 3  and W 4  are combined to form another (second) group. Line decoder outputs Q n  (n=1,2 . . . ) are applied correspondingly to these groups, that is, the output Q n  is applied to the nth group containing the word lines W 2n-1  and W 2n . These line decoder outputs are applied to the gates of the aforementioned MOS transistors T 2i  as inverted signals obtained by inverting the outputs from respective NAND gates. 
     To each of these word lines W i  is connected the gate of a MOS transistor T 3i , the source and drain of which are connected to the adjacent word lines W i-1  and W i+1 . In other words, three mutually adjacent word lines W i-1 , W i  and W i+1  form a group and are connected respectively to the source, gate and drain of the MOS transistor T 3i . For example, the word line W i+1  is connected to the gate of the MOS transistor T 3 (i+1), the source of this MOS transistor T 3 (i+1) is connected to the word line W i  and its drain is connected to the word line W i+2 . The source and drain not connected to the word line W 2  or W N-1  of the first and last of these MOS transistors T 31  and T 3N  are connected to a source of fixed voltage, or grounded. It is preferable that the aforementioned MOS transistors T 31   through T 3N  be disposed near the opposite ends of the word lines opposite to the line decoders for driving the word lines. It is to be reminded that of the two word line driving circuits D 1  and D 2 , one is adapted to apply a voltage which is high enough for driving a selected word line but the other is for maintaining the non-selected word lines at a specified fixed voltage. 
     Operation of the circuit described above is explained next for the situation where the second word line W 2  is selected. 
     Initially, the outputs Q 1 , Q 2 , . . . of the inverters as well as those of the word line driving circuits D 1  and D 2  are set at low levels. When the word line W 2  is selected, the output Q 1  of the line decoder connected to this word line W 2  becomes high and this switches on the MOS transistors T 21  and T 22 . Thereafter, a high-level output is introduced from the second word line driving circuit D 2  and the selected word line W 2  is driven to a high level through the MOS transistor T 22  which has been switched on. With a high voltage applied to the word line W 2 , the MOS transistor T 32  is switched on and the word lines W 1  and W 3  become electrically connected through its source and drain. Since the MOS transistor T 21  is now in the ON condition, the word line W 1  is kept at a low level by the first word line driving circuit D 1  and is not influenced by the voltage changes in the selected word line W 2 . Since the other adjacent word line W 3  is connected to the word line W 1  through the MOS transistor T 32 , it is kept at the same low level and is likewise unaffected by these voltage changes in the selected word line W 2 . In other words, the selected word line W 2  is electrically shielded by the adjacent non-selected word lines W 1  and W 3 . The other word line W 4 , . . . which are farther away are nearly completely free from the effects of the selected word line W 2  as a result of the electrical shielding. When one of the outermost word lines W 1  and W N  is selected, a similar result is obtained because the source or drain of the corresponding MOS transistor T 31  or T 3N  is grounded. 
     In summary, the present invention disclosed an IC which includes a plurality of word lines and is operated by having one of these word lines selected without allowing the effects of voltage changes therein to reach the non-selected word lines. Each of the MOS transistors which are provided to keep the non-selected word lines at a fixed voltage level has its gate, source and drain connected to the adjacent word lines such that connecting wires need not be disposed across the word lines. 
     The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed and many modifications and variations are possible in light of the above teaching. For example, any number (other than 2) of word lines may be grouped together to be connected to a line decoder output. If p (greater than 2) word line driving circuits D 1 , . . . D p  are used such that p word lines are grouped together and connected to each of them and q line decoders are used to operate a total of N (=p×q) word lines W 1 , . . . W N , these N word lines may be arranged similarly as shown in FIG. 1 such that the word line connected to the ith word line driving circuit D i  and the jth line decoder (1≧i≧p and 1≧j≧q) is placed in the [(i-1)q+j]th position. According to the present invention, these N word lines, thus arranged, are connected together through N MOS transistors T 31 , . . . T 3N  as shown in FIG. 1. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of this invention.