Abstract:
A detector circuit for detecting a digital word matching a bit pattern programmed by fusible devices. The detector circuit includes decoder circuits coupled to first and second sense nodes, and a reference node, and further includes an evaluation circuit also coupled to the first and second sense nodes. The evaluation circuit senses the voltage of both sense nodes and produces a match signal according to these voltages. The voltage of the first and second sense nodes are determined by the programmed status of the decoder circuit and whether a matching bit is detected. The decoder circuit includes a fusible device, such as an antifuse, and a switch having a control terminal coupled to receive one bit of the digital word. An enable circuit may also be coupled to the detector circuit to either enable or disable operation of the detector circuit based on whether the enable circuit has been programmed.

Description:
TECHNICAL FIELD 
     The present invention relates to integrated circuit devices, and more particularly, to antifuse circuits in memory devices. 
     BACKGROUND OF THE INVENTION 
     Typical integrated memory devices include arrays of memory cells arranged in rows and columns. In many such memory devices, several redundant rows and columns are provided to replace malfunctioning memory cells found during testing. Testing is typically performed by having predetermined data values written to selected row and column addresses that correspond to memory cells. The memory cells are then read to determine if the data read matches the data written to those memory cells. If the read data does not match the written data, then those memory cells are likely to contain defects which will prevent proper operation of the memory device. 
     The defective memory cells may be replaced by enabling the redundant circuitry. A malfunctioning memory cell in a column or a row is substituted with an entire column or row of redundant memory cells. Therefore, a memory device need not be discarded even though it contains defective memory cells. Substitution of one of the redundant rows or columns is accomplished in a memory device by programming a specific combination of fuses, or if the memory device uses antifuses, by programming a specific combination of antifuses, located in one of several fuse or antifuse blocks in the memory device. Conventional fuses are resistive devices which may be opened or broken with a laser beam or an electric current. Antifuses are capacitive devices that may be closed or blown by breaking down a dielectric layer in the antifuse with a relatively high voltage. 
     A specific combination of antifuses are programmed to correspond to an address of a row or column having defective memory cells. For example, if the defective row or column has a 12-bit binary address of 100100100100, then the antifuses in a set of 12 antifuses are programmed to store this address. Antifuses are typically arranged in an antifuse bank with the number of antifuses corresponding to the number of address bits for a row or column address. The memory device contains several antifuse banks so that several redundant rows and columns can be substituted for defective memory cells. 
     When the programmed redundant address is detected by the memory device, the redundant row or column is accessed instead of the row or column having the defective memory cells. The antifuse bank compares the incoming addresses to the redundant addresses programmed by the antifuses, and determines whether there is a match. If a match is detected, then the corresponding antifuse bank outputs a match signal. The match signal indicates that a redundant row or column should be accessed, and the defective row or column should be ignored. 
     A problem with conventional antifuse banks is that they occupy a significant amount of the total layout area of a memory device. This is a result of the current design of conventional antifuse banks. Each antifuse of the antifuse bank includes circuitry dedicated to programming and comparing that one antifuse. As shown in FIG. 1, a conventional antifuse bank  10  includes several antifuse circuits  12   a-g.  There is one antifuse circuit  12  for each address bit of a row or column address A 0 -Am. Each antifuse circuit  12   a-g  includes the same elements. In particular, an antifuse  16 , a programming circuit  18  for programming the antifuse  16 , and a comparing circuit  20  that compares a respective bit of the incoming address to the programmed state of the corresponding antifuse  16 . Conventional antifuse comparing and programming circuits are well known in the art and do not need to be discussed in detail herein. The comparing circuit  20  generates a high COMP signal when the respective bit of the incoming address matches the programmed state of the antifuse  16 . Each comparing circuit provides a COMP signal to a judgment circuit  24  that generates a MATCH signal when all of the antifuse circuits  12   a-g  provide a high COMP signal. 
     As illustrated by FIG. 1, the structure of a conventional antifuse bank  10  consists of the same basic circuitry repeated for each bit of a row or column address. In the case of the programming circuit  18 , which has several transistors having physically large dimensions because of the high current necessary to program an antifuse, having one programming circuit  18  for each antifuse  16  requires a significant portion of the overall layout area of a memory device. Another consideration is that, as the number of memory cells for a memory device continues to increase, additional address bits will be required to access the memory cells. Consequently, antifuse circuits  12  corresponding to the additional address bits will also be required to facilitate replacement of any defective memory cells, thus further increasing the layout area occupied by an antifuse bank  10 . 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a method and apparatus for detecting a digital word on a plurality of signal lines matching a bit pattern programmed by a corresponding plurality of fusible devices. A detector circuit comprises decoder circuits coupled between first and second sense nodes and a reference node, and an evaluation circuit also coupled to the first and second sense nodes to generate a match signal indicative of detecting the digital word. The decoder circuits may comprise a fusible device and a switch, where closing the switch of a programmed fusible device will change the voltage of the sense node to which the decoder circuit is coupled. The evaluation circuit senses the voltage of both sense nodes and produces a match signal according to these voltages. An enable circuit may also be coupled to the detector circuit to either enable or disable operation of the detector circuit based on whether the enable circuit has been programmed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a conventional antifuse bank. 
     FIG. 2 is a block diagram of an antifuse bank according to an embodiment of the present invention. 
     FIG. 3 is a schematic diagram of a precharge circuit according to an embodiment of the present invention. 
     FIG. 4 is a schematic diagram of an antifuse array according to an embodiment of the present invention. 
     FIG. 5 is a schematic diagram of a bank enable circuit according to an embodiment of the present invention. 
     FIG. 6 is a schematic diagram of an evaluation circuit according to an embodiment of the present invention. 
     FIG. 7 is a block diagram of an embodiment of a memory device including the antifuse bank illustrated in FIG.  2 . 
     FIG. 8 is a block diagram of an embodiment of a computer system including the memory device illustrated in FIG.  7 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Shown in FIG. 2 are antifuse banks  50   a-d.  Each antifuse bank  50   a-d  is in accordance to an embodiment of the present invention that may be substituted for a conventional antifuse bank. The antifuse banks  50   a-d  will generate a high BANK_MATCH signal when a current row or column address A 0 -Am matches the redundant row or column address, respectively, programmed by the antifuses of each antifuse bank  50   a-d.  Rather than the having a structure consisting of a network of individual antifuse comparing and programming circuits, like the conventional antifuse block  10  (FIG.  1 ), each antifuse bank  50   a-d  shares many comparing and programming elements between the individual antifuses located within each antifuse bank  50   a-d.    
     In the interests of brevity, the construction and operation of the antifuse banks  50   a-d  will be explained with specific reference to antifuse bank  50   a.  The remaining antifuse banks  50   b-d  are constructed and operated in the same manner as antifuse bank  50   a.  The antifuse bank  50   a  will be described in general, with a more detailed explanation thereafter. 
     The antifuse bank  50   a  includes a precharge circuit  52  coupled to receive a precharge signal PREI that activates the antifuse bank  50   a.  While the PREI signal is inactive, or low, the precharge circuit  52  precharges a pair of precharge nodes in preparation for an address detection operation. Upon receiving an active PREI signal that initiates an address detection operation, the precharge circuit  52  couples the precharge nodes to a pair of sense lines  60 ,  62  of an antifuse array  64 . Consequently, the voltage of the sense lines  60 ,  62  are raised to approximately the precharge voltage. Non-complementary and complementary address signals of the current address A 0 -Am are simultaneously strobed into the antifuse array  64  by the active PREI signal. If the address A 0 -Am strobed into the antifuse array  64  matches the redundant address programmed by the antifuses, each of the sense lines  60 ,  62  will continue to have a voltage nearly equal to the precharge voltage. Conversely, if the address A 0 -Am does not match the redundant address, at least one of the sense lines  60 ,  62  will be discharged and have a voltage much lower than the precharge voltage. 
     A bank enable circuit  70  is coupled to the sense line  60 . The bank enable circuit  70  must be enabled for the corresponding antifuse bank circuit to be functional. As will be explained in greater detail below, if none of the redundant rows or columns associated with the antifuse bank circuit are used, the enable circuit  70  should not be programmed so the antifuse bank  50   a  will always generate an inactive low BANK_MATCH signal. 
     An evaluation circuit  74  coupled to the antifuse array  64  senses the resulting voltage of the sense lines  60 ,  62 , and generates the BANK_MATCH signal. As mentioned previously, when the current address A 0 -Am matches the redundant address, resulting in both the sense lines  60 ,  62  being nearly equal to the precharge voltage, the evaluation circuit  74  will sense the voltage and generate a high BANK_MATCH signal indicating a match. Otherwise, the evaluation circuit  74  will generate a low BANK_MATCH signal indicating that the current address A 0 -Am does not match the programmed address. The resulting BANK_MATCH signal can be used in a manner similar to the MATCH signal of the conventional antifuse bank  10  (FIG.  1 ). 
     FIG. 3 illustrates an embodiment of a precharge circuit  80  that may be used as the precharge circuit  52  of FIG. 2. A capacitor  82   a  is charged by coupling a charging node  84   a  to a supply terminal through a PMOS charging transistor  88   a  that is turned ON by the inactive PREI signal. Similarly, a capacitor  82   b  is also charged by coupling a charging node  84   b  to a supply terminal through a PMOS charging transistor  88   b.  A pair of NMOS isolating transistors  90   a,    90   b  are switched OFF by the low PREI signal to isolate the charging nodes  84   a,    84   b  from a respective sense node  92   a,    92   b.  At the same time the capacitors  82   a,    82   b  are charging, the sense nodes  92   a,    92   b  are discharged through a respective NMOS discharging transistor  94   a,    94   b  switched ON by the output of an inverter  96 . The sense nodes  92   a,    92   b  are coupled to a ground node in order to fully discharge the sense nodes  92   a,    92   b  prior to initiating all address detection operation. 
     When the PREI signal becomes active, or high, the PMOS charging transistors  88   a,    88   b  and the NMOS discharging transistors  94   a,    94   b  are switched OFF. The sense nodes  92   a,    92   b  are simultaneously coupled to the respective charging nodes  84   a,    84   b  by switching ON isolating transistors  90   a,    90   b.  Consequently, the voltage of the sense nodes  92   a,    92   b  are raised to the voltage of the charging nodes  84   a,    84   b.    
     FIG. 4 illustrates an embodiment of an antifuse array  100  that may be used as the antifuse array  64  of FIG.  2 . Two NMOS transistors  102   a,    102   b,  are each coupled between a respective sense line  104   a,    104   b  and a supply terminal. Two NMOS transistors  106   a,    106   b,  are each coupled between a respective sense line  104   a,    104   b  and a ground terminal. These transistors are used while programming the antifuse array  100  with the address of the memory location that requires a redundant row or column. The use of these transistors will be explained in greater detail below. 
     Several antifuse-switch pairs  110   a - 110   m,    112   a - 112   m  are coupled between the sense lines  104   a,    104   b,  respectively, and a cell plate node  116 . The cell plate node  116  is grounded during an address detect operation. The number of antifuse-switch pairs  110   a - 110   m,    112   a - 112   m  coupled to each sense line  104   a,    104   b  corresponds to the number of address bits that identify a redundant row or column. Each antifuse switch pair  110   a - 110   m,    112   a - 112   m  includes an NMOS transistor  120  coupled in series with an antifuse  122 . The NMOS transistor  120  of each antifuse-switch pair  110   a - 110   m  has a gate coupled to a non-complementary address line  124   a - 124   m  that is output by an inverter  126   a - 126   m.  A two input NAND gate  128   a - 128   m  is coupled to the input of each inverter  126   a - 126   m.  One input of each NAND gate  128   a - 128   m  receives the PREI signal and the other input receives a respective non-complementary address signal. This arrangement allows all of the antifuse-switch pairs  110   a - 110   m  to receive the individual address signals simultaneously when the PREI signal goes high. The antifuse-switch pairs  112   a - 112   m  are coupled to a complementary address line  130   a - 130   m  in a fashion similar to antifuse-switch pairs  110   a - 110   m.  That is, the complementary address lines are coupled to the output of an inverter  132   a - 132   m  that is connected in series to a two input NAND gate  134   a - 134   m.    
     In operation, an antifuse-switch  110   a - 110   m,    112   a - 112   m  will couple the sense line  104   a,    104   b,  respectively, to the cell plate node  116  when the antifuse  122  has been programmed, and the address signal coupled to the gate of the NMOS transistor  120  is high. As mentioned previously, each of the sense lines  104   a,    104   b  is precharged prior to an address detect operation. Therefore, if any of the antifuse-switch pairs  110   a - 110   m,    112   a - 112   m  becomes conductive when the address signals are strobed into the antifuse array  100 , the respective sense line  104   a,    104   b  will be pulled to below the precharge voltage. As will be explained below, when the voltage of either, or both, of the sense lines  104   a,    104   b  is much less than the precharge voltage, a BANK_MATCH signal indicating that the current address A 0 -Am does not match the programmed redundant address will be generated. Conversely, when both sense lines  104   a,    104   b  maintain the precharge voltage, the resulting BANK_MATCH signal will indicate that the current address A 0 -Am matches the redundant address. 
     When programming the redundant address into the antifuse array  100 , an antifuse  122  is programmed if the corresponding non-complementary or complementary address bit of the redundant address is a “0”. Therefore, an antifuse-switch pair  110   a - 110   m,    112   a - 112   m  will be conductive only when the antifuse  122  is programmed to expect a “0”, but the antifuse-switch pair receives a “1” address bit instead. However, when the address bit matches the expected address bit, the antifuse-switch pair  110   a - 110   m,    112   a - 112   m  will not provide a conductive path through which the sense line  104   a,    104   b  may be discharged. 
     For example, when the least significant bit (“LSB”) of the redundant address is “0”, the antifuse-switch pair  110   a  coupled to receive the non-complementary LSB address signal A 0  is programmed, and the antifuse-switch pair  112   a  receiving the complementary LSB address signal A 0 * is not programmed. If the A 0  bit strobed into the antifuse array  100  is a “1”, the antifuse-switch  110   a  will be conductive, and the antifuse-switch  112   a  will not be conductive. Consequently, the sense line  104   a  will be discharged and its voltage will be much less than the precharge voltage. The resulting BANK_MATCH signal will not indicate a match. However, if the A 0  bit strobed into the antifuse array  100  is a “0”, neither of the antifuse-switches  110   a,    112   a  will be conductive, and both the sense lines  104   a,    104   b  will maintain voltages approximately equal to the precharge voltage. 
     The antifuses are programmed during the manufacture of the memory device so that the use of the redundant memory will appear transparent to a user. During the programming operation, a high-voltage and a high-current is coupled across the antifuse  122  to breakdown the dielectric between the conductive plates of the antifuse. The voltage of the cell plate node  116  is raised to approximately 10 volts and the NMOS transistor  120  of the antifuse-switch pair  110   a - 110   m,    112   a - 112   m  coupled to the antifuse  122  to be programmed is switched ON. The NMOS transistors  102   a,    102   b  and  106   a,    106   b  work in tandem to either program or not program the antifuse  122  by providing a conductive path to a ground terminal or to a supply terminal, respectively. 
     For example, continuing from above, the antifuse-switch  110   a  receiving the A 0  bit must be programmed, and the antifuse-switch  112   a  receiving the A 0 * bit is not programmed. However, both the A 0  and A 0 * bits will be provided to the gates of the antifuse-switch pairs  110   a  and  112   a  simultaneously. Thus, programming the antifuse-switch  110   a,  and not  112   a,  requires that only one of the sense lines  104   a,    104   b  have a high current, high voltage conductive path for programming, while the other one does not. Programming signals FBSELPG 0  and FBSEL 0  are coordinated to accommodate the aforementioned situation. 
     When programming the antifuse-switch  110   a,  the cell plate voltage is raised to approximately 10 volts. Then the FBSEL 0  signal goes high to switch ON the NMOS transistor  106   a,  and the FBSELPG 0 * signal goes high to switch ON the NMOS transistor  102   b.  Both the NMOS transistors  102   a  and  106   b  remain OFF. Coupling the sense line  104   a  to the ground terminal provides the high current, high voltage conductive path necessary for programming an antifuse. On the other hand, coupling the sense line  104   b  to the supply terminal does not provide the voltage difference necessary to program an antifuse. Thus, only one the antifuse-switch pair  110   a  is programmed. Antifuse switches coupled to the sense line  104   b  are programmed by reversing the logic levels of the programming signals, that is, FBSEL 0  is low, FBSELPG 0  is high, FBSEL 0 * is high and FBSELPG 0 * is low during programming. 
     The NMOS transistors  106   a  and  106   b  must be relatively large in order to carry a current sufficient to program the antifuses. Unlike the conventional antifuse bank  10  (FIG.  1 ), where each individual antifuse  16  has a dedicated programming circuit  18  with its own large high current transistors, the antifuse array  100  can share the large high current transistors  102   a,    102   b  and  106   a,    106   b  with all of the antifuses  122  within the antifuse array  100 . 
     FIG. 5 illustrates an embodiment of a bank enable circuit  150  that may be used as the bank enable circuit  70  of FIG.  2 . As mentioned earlier, the bank enable circuit  150  illustrated in FIG. 5 must be programmed to enable the associated antifuse bank to which it is coupled. Otherwise, the respective antifuse bank will always generate a low BANK_MATCH signal. 
     The bank enable circuit  150  is enabled by programming an enable antifuse  152 . To program the enable antifuse  152 , a high voltage and high current path is created from a switchable ground terminal  153 , through an NMOS transistor  154 , the enable antifuse  152 , and NMOS transistors  156  and  158 . A PMOS transistor  160  is switched OFF by a high FBSTAT signal during programming. The NMOS transistors  156 ,  158  are switched ON by high BANK_ENABLE and FBSELEN signals, respectively, and the voltage of the switchable ground terminal  153  is raised to approximately 10 volts by other circuitry not illustrated in FIG.  5 . The NMOS transistors  156  and  158  are relatively large and will be able to carry a current great enough to sufficiently program the enable antifuse  152 . When the PROGI signal goes high to switch ON the NMOS transistor  154 , approximately 10 volts will be coupled across the enable antifuse  152 , and the high current carried by the NMOS transistors  156  and  158  will program the enable antifuse  152  by breaking down its dielectric layer. 
     After the programming step has been completed, the NMOS transistors  154  and  158  will be switched OFF, and the NMOS transistor  156  will be switched ON during an address detect operation. Additionally, a cell plate node  162  is grounded to provide a voltage reference for the antifuse array  64  (FIG. 2) whenever an address detect operation takes place. 
     To determine whether the antifuse bank  50  has been enabled, the PMOS transistor  160  is switched ON momentarily by strobing the FBSTAT signal low prior to an address detect operation. A PMOS transistor  164 , which has its gate grounded, serves as a current limiting device whenever the PMOS transistor  160  is switched ON and the enable antifuse  152  has been programmed. If the bank enable circuit  150  has been programmed, an NMOS transistor  170  will remain OFF because its gate terminal will be coupled to the grounded cell plate node  162  through the programmed antifuse  152 . Thus, during an address detect operation, the voltage of the sense line to which the bank enable circuit  150  is coupled will be determined by the results of strobing in the current address A 0 -Am into the antifuse array  64 , and not by the bank enable circuit  150 . 
     In the case where the bank enable circuit  150  has not been programmed, the NMOS transistor  170  will be switched ON when the FBSSTAT signal is strobed low. The sense line to which the bank enable circuit  150  is connected will then be coupled to a ground node. As will be explained below in greater detail, when either of the sense lines  60 ,  62  (FIG. 2) is pulled low, the antifuse bank generates a low BANK_MATCH signal. 
     FIG. 6 illustrates an embodiment of an evaluation circuit  180  that may be used as the evaluation circuit  74  of FIG. 2. A pair of sense lines  184   a,    184   b  is coupled to a respective pair of sense amplifiers  186   a,    186   b.  Each of the sense amplifiers  186   a,    186   b  generates an evaluation signal at a respective determination node  190   a,    190   b.  The evaluation signal is provided to a determination circuit  196 . As shown in FIG. 6, the sense amplifiers  186   a,    186   b  are formed by a pair of cross-coupled inverters. However, one ordinarily skilled in the art will appreciate that a variety of other well-known sense amplifier circuits may be substituted for the sense amplifier circuits  186   a,    186   b.    
     The sense amplifiers  186   a,    186   b  are preconditioned prior to initiating an address detection operation by coupling the determination nodes  190   a,    190   b  to a preconditioning voltage VREF. The VREF voltage is approximately one-half of the internal voltage supply, and is generated by a VREF generator (not shown). A high SETREF signal, coordinated with a low PREI signal, switches ON NMOS preconditioning transistors  192   a,    192   b  to couple the determination nodes  190   a,    190   b,  respectively, to a supply terminal that provides the VREF voltage. When an address detection operation is initiated by PREI going high, the NMOS preconditioning transistors  192   a,    192   b  are switched OFF by a low SETREF signal so that the nodes  190   a,    190   b  are free to be pulled high or low according to the voltage of the respective sense line  184   a,    184   b.    
     The voltage of the sense lines  184   a,    184   b  relative to the VREF voltage will determine whether the determination nodes  190   a,    190   b  are pulled high or low. For example, if the resulting voltage of the sense line  184   a  is greater than the VREF voltage after the address A 0 -Am has been strobed into the antifuse array  64 , the sense amplifier  186 a will pull the determination node  190   a  low. Conversely, if the resulting voltage is less than the VREF voltage, the sense amplifier  186   a  will pull the determination node  190   a  high. 
     The determination circuit  196  is coupled to the determination nodes  190   a,    190   b  to receive an evaluation signals from each of the sense amplifiers  186   a,    186   b.  The determination circuit  196  generates an output signal according to logical levels of the two evaluation signals. The determination circuit  196  is represented in FIG. 6 as a logic NOR gate circuit. Therefore, the determination circuit  196  will generate a high output signal only when both evaluation signals are low. If either of the evaluation signals is high, the determination circuit  196  will output a low signal. As previously explained, this situation occurs only when both the sense lines  184   a,    184   b  have voltages greater than the VREF voltage, that is, when the current address A 0 -Am matches the redundant address programmed in the antifuse array  64 . 
     An output latch  200  is coupled to the output of the determination circuit  196 . The output latch  200  includes two series connected inverters  204 ,  206  having an input and feedback coupled through transfer gates  210 ,  212 , respectively. The control terminals of the transfer gates  210 ,  212  are coupled to receive the RLAT signal and an inverted RLAT signal, output from an inverter  214 , such that the output latch  200  will not latch the output of the determination circuit  196  until the RLAT signal is low. The signal ultimately latched by the output latch  200  is the BANK_MATCH signal of the antifuse bank  50 . After the BANK_MATCH signal has been latched by the output latch  200 , the determination nodes  190   a,    190   b  may be preconditioned without changing the BANK_MATCH signal. 
     FIG. 7 is a block diagram of a memory circuit  220 , which incorporates the antifuse banks  50   a-d  of FIG.  2 . The memory circuit  220  includes an address register  222 , which receives an address from an ADDRESS bus. A control logic circuit  224  receives a clock (CLK) signal, and receives clock enable (CKE), chip select ({overscore (CS)}), row address strobe ({overscore (RAS)}), column address strobe ({overscore (CAS)}), and write enable ({overscore (WE)}) signals from the COMMAND bus, and communicates with the other circuits of the memory circuit  220 . 
     A row address multiplexer  226  receives the address signal from the address register  222  and provides the row address to a row address latch  228   a,    228   b.  Each of the row address latches  228   a,    228   b  stores the row address and applies it to a respective block of antifuse banks  230   a,    230   b.  The antifuse banks of the block  230   a,    230   b  compare an incoming address to the programmed redundant addresses to determine whether the incoming address matches an address of a defective memory cell in a memory bank  234   a,    234   b,  respectively. If an antifuse bank in either block  230   a,    230   b  determines such a match, a match signal will be output to a row address decoder  232   a,    232   b.  In response, the row address decoder  232   a,    232   b  causes an appropriate redundant row to be accessed, and ignores the defective row in the memory bank  234   a,    234   b.  If no match signal is received, the row address decoder will access the row in the memory bank  234   a,    234   b  having the row address provided by the row address latch  228   a,    228   b.    
     A column address latch  236  receives the column address from the address register  222  and provides the column address of the selected memory cells to a block of antifuse banks  238 . As with the block of antifuse banks  230   a,    230   b  coupled to the row address latches  228   a,    228   b,  the block of antifuse banks  238  coupled to the column address latch  236  compares the incoming column address to the redundant addresses programmed in the antifuse banks of the block  238 . If a match is detected, a match signal is output to a column decoder  240  and an appropriate redundant column is accessed. However, if no match signal is received, the column of the memory bank  234   a,    234   b  having the column address provided by the column address latch  236  will be accessed. 
     During read and write cycles, the row and column address decoders  232   a,    232   b,    240 , respectively, access the addressed memory cell, as described above, and read/write circuits  242   a,    242   b  read data from the addressed memory cells during a read cycle, or write data to the addressed memory cells during a write cycle. 
     A data input/output (I/O) circuit  244  includes a plurality of input buffers  246 . During a write cycle, the buffers  246  receive and store data from the DATA bus, and the read/write circuits  242   a  and  242   b  provide the stored data to the memory banks  234   a  and  234   b,  respectively. The data I/O circuit  244  also includes a plurality of output drivers  250 . During a read cycle, the read/write circuits  242   a  and  242   b  provide data from the memory banks  234   a  and  234   b,  respectively, to the drivers  250 , which in turn provide this data to the DATA bus. 
     A refresh counter  252  stores the address of the row of memory cells to be refreshed either during a conventional auto-refresh mode or self-refresh mode. After the row is refreshed, a refresh controller  254  updates the address in the refresh counter  252 , typically by either incrementing or decrementing the contents of the refresh counter  252  by one. Although shown separately, the refresh controller  254  may be part of the control logic  224  in other embodiments of the memory circuit  220 . 
     The memory circuit shown in FIG. 7 has not been described as a specific form of memory device because some or all of the principles previously described are applicable to a variety of memory devices including, but not limited to, asynchronous DRAM, synchronous DRAM, SLDRAM, static RAM, and the like. Accordingly, the present invention is not limited by the specific form of memory device. 
     Shown in FIG. 8 is an example of a computer system  260  using the antifuse banks  50   a-d  of FIG. 2 in each of a plurality of memory devices  266   a-c.  The computer system  260  includes a processor  262  having a processor bus  264  coupled through a memory controller  268  and system memory bus  273  to three memory devices  266   a-c.  The computer system  260  also includes one or more input devices  270 , such as a keypad or a mouse, coupled to the processor  262  through a bus bridge  272  and an expansion bus  274 , such as an industry standard architecture (“ISA”) bus or a peripheral component interconnect (“PCI”) bus. The input devices  270  allow an operator or an electronic device to input data to the computer system  260 . One or more output devices  280  are coupled to the processor  262  to display or otherwise output data generated by the processor  262 . The output devices  280  are coupled to the processor  262  through the expansion bus  274 , bus bridge  272  and processor bus  264 . Examples of output devices  274  include printers and a video display units. One or more data storage devices  288  are coupled to the processor  262  through the processor bus  264 , bus bridge  272 , and expansion bus  274  to store data in or retrieve data from storage media (not shown). Examples of storage devices  288  and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives. 
     In operation, the processor  262  sends a data transfer command via the processor bus  264  to the memory controller  268 , which, in turn, communicates with the memory devices  266   a-c  via the system memory bus  283  by sending the memory devices  266   a-c  control and address information. Data is coupled between the memory controller  268  and the memory devices  266   a-c  through a data bus portion of the system memory bus  273 . During a read operation, data is transferred from the memory devices  266   a-c  over the memory bus  273  to the memory controller  268  which, in turn, transfers the data over the processor bus  264  to the processor  262 . The processor  262  transfers write data over the processor bus  264  to the memory controller  268  which, in turn, transfers the write data over the system memory bus  273  to the memory devices  266   a-c.  Although all the memory devices  266   a-c  are coupled to the same conductors of the system memory bus  273 , only one memory device  266   a-c  at a time reads or writes data, thus avoiding bus contention on the memory bus  273 . The computer system  260  also includes a number of other components and signal lines that have been omitted from FIG. 8 in the interests of brevity. 
     It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. For example, the bank enable circuit  70  was shown in FIG. 2 as being coupled to the sense line  60 . However, the bank enable circuit could also be coupled to the sense line  62 . Furthermore, the antifuse banks  50   a-d  have been described as generating a high BANK_MATCH signal when an address match is detected. However, a low BANK_MATCH signal could be generated to indicate an address match if the output of the evaluation circuit  180  (FIG. 6) is taken from between the inverters  204  and  206 , rather than from the output of the inverter  206 . Therefore, the present invention is to be limited only by the appended claims.