Abstract:
A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.

Description:
PRIORITY 
       [0001]    This is a divisional of U.S. patent application Ser. No. 14/858,010, filed Sep. 18, 2015, herein incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC design and material have produced generations of ICs where each generation has smaller and more complex circuits than previous generations. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. 
         [0003]    This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing. For these advances to be realized, similar developments in IC processing and manufacturing are needed. One area is the wiring, or interconnects, between the transistors and other devices. Although existing methods of fabricating IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, challenges rise to develop robust process for forming metal interconnection with low via resistance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    Aspects of the present disclosure are best understood from the following detailed description when read in association with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features in drawings are not drawn to scale. In fact, the dimensions of illustrated features may be arbitrarily increased or decreased for clarity of discussion. 
           [0005]      FIG. 1  is a flowchart of an example method for fabricating a semiconductor device constructed in accordance with some embodiments. 
           [0006]      FIG. 2  is a cross-sectional view of an exemplary initial structure of a semiconductor device in accordance with some embodiments. 
           [0007]      FIGS. 3, 4, 5A, 5B, 6, 7, 8, 9, 10A, and 10B  are cross-sectional views of an exemplary semiconductor device in accordance with some embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
         [0009]    Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
         [0010]      FIG. 1  is a flowchart of a method  100  of fabricating one or more semiconductor devices in accordance with some embodiments. The method  100  is discussed in detail below, with reference to an initial structure  205  of a semiconductor device  200  showed in  FIG. 2  and the semiconductor device  200  shown in  FIGS. 3, 4, 5A, 5B, 6, 7, 8, 9, 10A , and  10 B. 
         [0011]    Referring to  FIGS. 1 and 2 , the method  100  starts at step  102  by providing the initial structure  205 . The initial structure  205  includes a substrate  210 , which may include silicon. Alternatively or additionally, the substrate  210  may include other elementary semiconductor such as germanium. The substrate  210  may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate  210  may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate  210  includes an epitaxial layer. For example, the substrate may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate  210  may include a semiconductor-on-insulator (SOI) structure. For example, the substrate  210  may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding. 
         [0012]    The substrate  210  also includes various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, light doped region (LDD), heavily doped source and drain (S/D), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a complimentary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, and/or light emitting diode (LED). The substrate  210  may further include other functional features such as a resistor or a capacitor formed in and on the substrate. The substrate  210  may further include lateral isolation features provided to separate various devices formed in the substrate  210 . In one embodiment, shallow trench isolation (STI) features are used for lateral isolation. The various IC devices may further include other features, such as silicide disposed on S/D and gate stacks overlying channels. 
         [0013]    The initial structure  205  may also include a plurality of dielectric layers and conductive features integrated to form an interconnect structure configured to couple the various p-type and n-type doped regions and the other functional features (such as gate electrodes), resulting a functional integrated circuit. In one example, the initial structure  205  may include a portion of the interconnect structure and is collectively referred to as the substrate  210 . The interconnect structure is further described later. 
         [0014]    As noted above, the substrate  210  includes an interconnect structure. The interconnect structure includes a multi-layer interconnect (MLI) structure and an inter-level dielectric (ILD) integrated with the MLI structure, providing an electrical routing to couple various devices in the substrate  210  to the input/output power and signals. The interconnect structure includes various metal lines, contacts and via features (or via plugs). The metal lines provide horizontal electrical routing. The contacts provide vertical connection between silicon substrate and metal lines while via features provide vertical connection between metal lines in different metal layers. 
         [0015]    Exemplary conductive features  214  are shown in  FIG. 2  for illustration. In one embodiment, the conductive features  214  include a portion of the interconnect structure. For example, the conductive feature  214  includes a contact, a metal via, and/or a metal line. The conductive feature  214  may include aluminum (Al), copper (Cu), and/or tungsten (W). In another embodiment, the conductive feature  214  includes an electrode of a capacitor, a resistor or a portion of a resistor. Alternatively, the conductive features  214  include a doped region (such as a source or a drain), or a gate electrode. In another example, the conductive features  214  are silicide features disposed on respective source, drain or gate electrode. 
         [0016]    In some embodiments, the conductive features  214  may be further surrounded by a barrier layer  216  to prevent diffusion and/or provide material adhesion. The barrier layer  216  may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN) and/or tantalum silicon nitride (TaSiN). The conductive features  214  and the barrier layer  216  may be formed by a procedure including lithography, etching and deposition. An example lithography process may include coating, exposure, post exposure baking, and developing processes. The etch process may include a wet etch, a dry etch, and/or a combination thereof. The deposition technique may include physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD), and/or other suitable technique. 
         [0017]    The initial structure  205  also includes a dielectric layer  220  deposited over the substrate  210 , including over the conductive features  214 . The dielectric layer  220  may include silicon oxide, silicon nitride, a dielectric material layer having a dielectric constant (k) lower than thermal silicon oxide (therefore referred to as low-k dielectric material layer), and/or other suitable dielectric material layer. The dielectric layer  220  may include a single layer or multiple layers. The dielectric layer  220  may be deposited by CVD, atomic layer deposition (ALD) or spin-on coating. 
         [0018]    Referring to  FIGS. 1 and 3 , once the initial structure  205  is received, the method of  100  proceeds to step  104  by removing a portion of the dielectric layer  220  to form trenches  310  in the dielectric layer  220 . Trenches  310  are placeholders for conductive lines to be formed therein. Trenches  310  may be formed by a first lithography and etch processes. The first lithography process may include forming a photoresist (or resist) layer over the dielectric layer  220 , exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. The masking element is then used for etching trenches into the dielectric layer  220 . The etching process may include dry etching, wet etching, and/or other suitable processes. 
         [0019]    Referring to  FIGS. 1 and 4 , the method  100  proceeds to step  106  by performing a second lithography process to define via trenches  410  over trenches  310 . As shown, illustrated therein is an exemplary lithography process using three layers of material (tri-layer lithography). The three layers are a first material layer referred to as bottom layer (BL)  311 , a second material layer referred to as a middle layer (ML)  312 , and a third material layer referred to as resist  313 . The BL layer  311  protects the dielectric layer  220  in a subsequent etch process. In some embodiments, the BL layer  112  includes an organic polymer free of silicon. The ML  312  may include a silicon-containing layer designed to provide etch selectivity from the BL layer  311 . In some embodiments, the ML  312  is also designed to function as a bottom anti-reflective coating that reduces reflection during a lithography exposure process, thereby increasing the imaging contrast and enhancing the imaging resolution. The BL  311  fills trenches  310 , the ML  312  is formed over the BL  311 , and the resist  313  is formed over the ML  312 . Resist  313  is patterned by a photolithography process to provide via trenches  410  therein. As shown, via trenches  410  are aligned with the respective conductive features  214 . 
         [0020]    Referring to  FIGS. 1 and 5A , the method  100  proceeds to step  108  by extending via trenches  410  through various underlying layers. As shown, the ML  312 , the BL  311  and the dielectric layer  220  are etched through via trenches  410  to expose a portion of the conductive feature  214 . In the present embodiment, trenches  310  have a first width w 1  which is wider than a second width w 2  of via trenches  410 . The etch process may include a wet etch, a dry etch, and/or a combination thereof. As an example, the etch process includes a plasma dry etching process using a fluorine-based chemistry, such as CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 . The respective etch process may be tuned with various etching parameters, such as etchant used, etching temperature, etching solution concentration, etching pressure, etchant flow rate, and/or other suitable parameters. 
         [0021]    After forming via trenches  410 , the remaining portions of resist  313 , ML  312  and BL  311  are removed by another etch process, such as a wet stripping and/or plasma ashing. As shown in  FIG. 5B , after removing the remaining portions of resist  313 , ML  312  and BL  311 , trenches  310  are revealed and in communication (or connected) with via trenches  410 . A portion of the conductive feature  214  is exposed in the respective via trenches  410 . 
         [0022]    The combination of trench  301  and via trench  410  may be generally referred to as stepped trench (or deep trench)  411 . Thus, the deep trench  411  has a upper portion with the first width w 1  and a lower portion with the second width w 2 . 
         [0023]    Referring to  FIGS. 1 and 6 , the method  100  proceeds to step  110  by depositing a first barrier layer  510  in trenches  411  (i.e. the combination of via trenches  410  and trenches  310 ), as well as on the top of the dielectric layer  220 . The first barrier layer  510  may include manganese (Mn), manganese nitride (MnN), titanium (Ti), tantalum (Ta), cobalt (Co), cobalt tungsten (CoW), molybdenum (Mo), and/or other suitable conductive material. The first barrier layer  510  may be deposited by ALD, PVD, CVD, MOCVD, and/or other suitable technique. In some embodiment, the first barrier  510  is deposited by ALD to achieve good step coverage with a quit thin thickness. As an example, the first barrier layer  510  includes MnN layer deposited by ALD. 
         [0024]    In the present embodiment, the first barrier layer  510  is conformably deposited along and physical contacts with first sidewalls  315  of trenches  310 , second sidewalls  415  of via trenches  410  and a bottom  416  of via trenches  410  defined by the conductive features  214 . Therefore, a first portion of the first barrier layer  510  extending along first sidewalls  315  and second sidewalls  415  physical contacts with the dielectric layer  220  while a second portion of the first barrier layer  510  extending along the bottom  416  physical contacts with the conductive feature  214 . For the sake of clarity and simplicity, the first portion is designated with the reference numeral  510 D while the second portion is designated with the reference numeral  510 M. 
         [0025]    Referring to  FIGS. 1 and 7 , the method  100  proceeds to step  112  by performing a thermal treatment to transform (or convert) the first portion  510 D and the second portion  510 M into different barrier layers. In some embodiments, during the thermal treatment, the first portion  510 D reacts with the dielectric layer  220  to thereby transform into a second barrier layer  610  while the second portion  510 M reacts with the conductive feature  214  to thereby transform into a third barrier layer  620  (or bottom-barrier layer). In such an embodiment, the second barrier layer  610  is formed of a different material than the third barrier layer  620 . 
         [0026]    Alternatively, in some embodiments, during the performance of the thermal treatment to transform (or convert) the first portion  510 D into the second barrier  610 , the second portion  510 M remains intact and the third barrier layer  620  is formed of the same material as the first barrier  510 . 
         [0027]    In the present embodiment, the second barrier layer  610  has a substantial different etch selectivity comparing with the bottom-barrier layer  620  in a subsequent etch. The first barrier layer  510  and the dielectric layer  220  are chosen such that the second barrier  610  formed with adequate ability to enhance adhesion and prevent inter-diffusion and reactions between the dielectric layer  220  and metal layers to be filled in via trenches  410  and trenches  310 . In an example, the first barrier layer  510  includes MnN while the dielectric layer  220  includes silicon oxide. After the thermal treatment, the first portion  510 D converts to MnSi x O y N z  while the second portion  510 M has almost no reaction with the conductive feature  214  and thus the bottom-barrier layer  620  remains as the MnN layer  510 M. Here, x represents Si composition in atomic percent, y represents oxygen composition in atomic percent and z represents nitrogen composition in atomic percent. 
         [0028]    With the thermal treatment, the second and third barrier layers,  610  and  620 , are formed with self-selective-formation nature, which provides process simplicity and relaxes process constrains. Especially, converting by the thermal treatment, the second barrier layer  610  may carry film characteristics of the first barrier layer  510 , such as good step coverage with a thin thickness, which provides a good sidewall protection for a metal layer to be filled in via trenches  410  and avoids formation of overhang. 
         [0029]    The thermal treatment may comprise a rapid thermal anneal (RTA), a laser anneal, a furnace anneal, and/or a flash lamp anneal. As an example, the thermal treatment is performed, with a temperature range from 100° C. to 400° C., by using noble gases such as helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and nitrogen (N 2 ). As another example, the thermal treatment is performed in a vacuum environment. 
         [0030]    Referring to  FIGS. 1 and 8 , the method  100  proceeds to step  114  by removing the third barrier layer  620 . In the present embodiment, a selective etch is performed such that the etch process etches the third barrier layer  620  without substantially etching the second barrier layer  610  and the conductive feature  214 . A selective etch process provides process simplicity and relaxes process constrains. The selective etch may include a selective wet etch, a selective dry etch, and/or a combination thereof. As discussed above, in some embodiments, the third barrier layer  620  is formed of the same material as the first barrier layer  510 , namely MnN, while the second barrier layer  610  is MnSi x O y N z  and the first conductive feature is Cu. In such an embodiment, without substantially etching the MnSi x O y N z  barrier layer  610 , the MnN third barrier layer  620  is removed by an aqueous wet clean process with a weak acid solution (pH value less than 7). The aqueous wet clean process adds simplicity to the manufacturing process and also minimizes process-induced-damage to the conductive feature  214 . 
         [0031]    In the present embodiment, after removing the third barrier layer  620 , the contact features  214  are exposed within via trenches  410 . The resistance of a bottom barrier layer (e.g. third barrier layer  620 ) deposited on the bottom of via trenches  410  is usually much higher than a resistance of a metal layer deposited in via trenches  410  over such a bottom barrier layer. Therefore, the resistance of a bottom barrier layer dominates a resistance of a conductive interconnection formed by the combination of the bottom barrier layer and the metal layer. This resistance is referred to as via resistance. In the present embodiment, the method  100  provides a bottom-barrier-free scheme. 
         [0032]    Referring to  FIGS. 1 and 9 , the method  100  proceeds to step  116  by forming a via metal  710  in via trenches  410 . The via metal  710  physical contacts with the conductive feature  214 . The via metal  710  may include copper or copper alloy, such as copper manganese (CuMn), copper aluminum (CuAl), copper titanium, (CuTi), copper vanadium (CuV), copper chromium (CuCr), copper silicon (CuSi) and/or copper niobium (CuNb). The via metal  710  may be formed by PVD, CVD, MOCVD, electroless deposition (ELD), and/or other suitable technique. In the present embodiment, the via metal  710  is formed by ELD process, which provides a low process temperature, an intrinsic process selectivity and conformal bottom-up deposition to reduce via trench gap-fill challenge. In one embodiment, the via metal  710  is Cu deposited by ELD process. As shown, the vial metal  710  has the second barrier  610  as its sidewall barrier and thereby it improves device reliability by limiting electron migration (EM) and time-dependent dielectric breakdown (TDDB) associated with via metal diffusion into the underlying dielectric layer  220 . Also, by having sidewall barrier layer, constrains in choosing candidates for via metal layer  710  is also relaxed. 
         [0033]    Referring to  FIGS. 1 and 10A , the method  100  proceeds to step  118  by filling in trenches  310  with a metal layer  720 . In the present embodiment, the metal layer  720  is deposited over and directly contacts with the via metal  710 . In the present embodiment, without a barrier layer on an interface of the via metal  710  and the metal layer  720 , a resistance contributed by the via metal  710  and the metal layer  720  together is reduced. The metal layer  720  may include Cu, Co, W, Ru, Ag, Au, CoW, CoF, CoSi, or other suitable metals. The conductive layer  720  may be deposited by PVD, CVD, MOCVD, or plating. In one embodiment, the conductive layer  720  includes a Cu layer deposited by PVD. In one embodiment, the conductive layer  720  includes a Cu layer deposited by plating. In various other examples, Cu deposition may be implemented by other techniques. A Cu reflow process may be added to enhance Cu filling profile. 
         [0034]    By forming via metal  710  and the metal layer  720  separately, it provides the benefit of using different deposition processes to better suit the different needs of the via trench  410  and the trench  310 . The scheme is sometimes referred as via pre-fill scheme. For example, an ELD process is used to form the via metal  710  for its adequate conformal deposition in gap-filling while a PVD process is used to fill in the trench  310 , which has a wider gap, for its higher deposition rate and lower process cost comparing with the ELD process. 
         [0035]    Additionally, a chemical mechanical polishing (CMP) process is performed to planarize the top surface of the device  200  to remove excessive metal layer  720  and the second barrier layer  610  over the dielectric layer  220 , as shown in  FIG. 10B . The second barrier layer  610  and metal layer  720  in trenches  310  remain, forming the conductive lines  725 . As a result of the CMP process, the top surface of the dielectric layer  220  and the top surface of the conductive lines  725  are substantially coplanar. 
         [0036]    Additional steps can be provided before, during, and after the method  100 , and some of the steps described can be replaced, eliminated, or moved around for additional embodiments of the method  100 . For example, instead of forming via metal  710  and depositing metal layer  720  separately, in step  116  and step  118  respectively, via metal  710  and metal layer  720  are formed by one deposition process. 
         [0037]    The semiconductor devices,  200 , may include additional features, which may be formed by subsequent processing. For example, various vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) are formed over the substrate  210 . For example, a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. 
         [0038]    Based on the above, it can be seen that the present disclosure provide methods of forming a bottom-barrier-free metal interconnection for achieving low via contact resistance, such that bottom-barrier-free at the bottom of via metal and at the bottom of the metal line, which is formed over and physical contacts the via metal. The method provides sidewall barrier for ELD via metal to improve TDDB and electron migration (EM). The method provides a robust metal interconnection formation process with selective formation and selective etch to relax process constrains and simplify the manufacturing process. 
         [0039]    The present disclosure provides many different embodiments of fabricating a semiconductor device that provide one or more improvements over existing approaches. In one embodiment, a method for fabricating a semiconductor device includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a trench in the dielectric layer. The trench has a first width in its lower portion and a second width in its upper portion and the second width is greater than the first width. The first conductive feature is exposed within the trench. The method also includes forming a first barrier layer in the trench. The first barrier has a first portion disposed over the dielectric layer and a second portion disposed over the first conductive feature. The method also includes applying a thermal treatment to convert the first portion of the barrier layer to a second barrier layer, exposing the first conductive feature in the trench while a portion of the second barrier layer is disposed over the dielectric layer and forming a second conductive feature in the trench. 
         [0040]    In yet another embodiment, a method includes forming a dielectric layer over a first conductive feature disposed on a substrate, forming a trench in the dielectric layer. The trench has a first width in its upper portion and a second width in its lower portion. The first width is greater than the second width. The first conductive feature is exposed within the trench. The method also includes forming a first barrier layer in the trench. A first portion of the first barrier is formed along a sidewall surface of the trench defined by the dielectric layer and a second portion of the first barrier layer is formed along a bottom surface of the trench defined by the first conductive feature. The method also includes converting the first portion of the first barrier layer into a second barrier layer. The second barrier layer is formed of a different material than the first barrier layer. The method also includes exposing the first conductive feature in the trench while a portion of the second barrier layer is disposed over the dielectric layer and forming a second conductive feature in the trench. 
         [0041]    In yet another embodiment, a semiconductor device includes a first conductive feature disposed over a substrate, a second conductive feature disposed over the first conductive feature. The second conductive feature has an upper portion having a first width and a lower portion having a second width that is different than the first width. The lower portion is in physical contact with a top portion of the first conductive feature. The device also includes a first barrier layer disposed along sidewalls of the second conductive feature and a dielectric layer disposed along the first barrier layer. The dielectric layer is in physical contact with a side of the first barrier layer that faces away from the second conductive feature. 
         [0042]    The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.