Abstract:
A tangible storage medium and data processing system build a runtime environment of a system. A profile manager receives a service request containing a profile identifier. The profile identifier specifies a required version of at least one software component. The profile manager identifies a complete installation of the software component, and at least one delta file. The profile manager dynamically constructs a classpath for the required version by preferentially utilizing files from the at least one delta file followed by files from the complete installation. The runtime environment is then built utilizing the classpath.

Description:
BACKGROUND 
       [0001]    1. Field 
         [0002]    The disclosure relates generally to a computer implemented method, a computer usable program code, and a data processing system. More specifically, the present disclosure relates to a computer implemented method, a computer usable program code, and a data processing system for controlling access to a contested resource. 
         [0003]    2. Description of the Related Art 
         [0004]    Increasingly large symmetric multi-processor data processing systems are not being used as single large data processing systems. Instead, these types of data processing systems are being partitioned and used as smaller systems. These systems are also referred to as logical partitioned (LPAR) data processing systems. A logical partitioned functionality within a data processing system allows multiple copies of a single operating system or multiple heterogeneous operating systems to be simultaneously run on a single data processing system platform. A partition, within which an operating system image runs, is assigned a non-overlapping subset of the platform&#39;s resources. These platform allocable resources include one or more architecturally distinct processors and their interrupt management area, regions of system memory, and input/output (I/O) adapter bus slots. The partition&#39;s resources are represented by the platform&#39;s firmware to the operating system image. 
         [0005]    Each distinct operating system or image of an operating system running within a platform is protected from each other, such that software errors on one logical partition cannot affect the correct operation of any of the other partitions. This protection is provided by allocating a disjointed set of platform resources to be directly managed by each operating system image and by providing mechanisms for ensuring that the various images cannot control any resources that have not been allocated to that image. Furthermore, software errors in control of an operating system&#39;s allocated resources are prevented from affecting the resources of any other image. Thus, each image of the operating system, or each different operating system, directly controls a distinct set of allocable resources within the platform. 
         [0006]    With respect to hardware resources in a logical partitioned data processing system, these resources are shared disjointly among various partitions. These resources may include, for example, input/output (I/O) adapters, memory DIMMs, non-volatile random access memory (NVRAM), and hard disk drives. Each partition within a logical partitioned data processing system may be booted and shut down over and over without having to power-cycle the entire data processing system. 
         [0007]    Each distinct operating system or image of an operating system running within a platform is implemented using a partition management firmware, such as PowerVM, which is available from International Business Machines Corporation. In systems that contain a partition management firmware and many guest operating systems, performance is a major concern. Each guest operating system has at least one virtual central processing unit (VCPU). The partition management firmware controls access to a physical central processing unit (CPU) core by the guest operating systems and allocates time slices during which each VCPU gets to execute on the physical CPU core. It is often the case that the total number of VCPUs for all the guest operating systems is greater than the number of physical CPUs in the system. 
       SUMMARY 
       [0008]    The different illustrative embodiments provide a computer implemented method, computer usable program code, and a data processing system for control access to a contested resource. When a lock acquisition request is received from a virtual machine, the partition management firmware determines whether the lock acquisition request is received within a preemption period of a time slice allocated to the virtual machine. If the lock acquisition request is received within the preemption period, the partition management firmware ends the time slice early, and performs a context switch. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0009]      FIG. 1  is a block diagram of a data processing system in which illustrative embodiments may be implemented; 
           [0010]      FIG. 2  is a block diagram of an exemplary logical partitioned platform in which illustrative embodiments may be implemented; 
           [0011]      FIG. 3  is a data processing system for controlling access to a contested resource according to an illustrative embodiment; 
           [0012]      FIG. 4  is a timeline for lock acquisition and lock release in system having multiple virtual processors according to the prior art; 
           [0013]      FIG. 5  is a timeline for deferred lock acquisition in system having multiple virtual processors according to an illustrative embodiment; 
           [0014]      FIG. 6  is a timeline for lock acquisition and lock release in system having multiple virtual processors according to an illustrative embodiment; 
           [0015]      FIG. 7  is a flowchart for controlling access to a contested resource according to an illustrative embodiment; and 
           [0016]      FIG. 8  is a flowchart for extending an allocated time slice according to an illustrative embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. 
         [0018]    Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. 
         [0019]    A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. 
         [0020]    Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. 
         [0021]    Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user&#39;s computer, partly on the user&#39;s computer, as a stand-alone software package, partly on the user&#39;s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user&#39;s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). 
         [0022]    Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. 
         [0023]    These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks. 
         [0024]    The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. 
         [0025]    With reference now to the figures and in particular with reference to  FIG. 1 , a block diagram of a data processing system in which illustrative embodiments may be implemented is depicted. Data processing system  100  may be a symmetric multiprocessor (SMP) system including processors  101 ,  102 ,  103 , and  104 , which connect to system bus  106 . These processors are hardware devices. Software or virtual processes are specifically identified as being virtual components. For example, virtual processor means a virtual or software process that runs on hardware. Processor means a hardware device. For example, data processing system  100  may be an IBM eServer, a product of International Business Machines Corporation in Armonk, N.Y., implemented as a server within a network. Alternatively, a single processor system may be employed. Also connected to system bus  106  is memory controller/cache  108 , which provides an interface to local memories  160 ,  161 ,  162 , and  163 . I/O bridge  110  connects to system bus  106  and provides an interface to I/O bus  112 . Memory controller/cache  108  and I/O bridge  110  may be integrated as depicted. 
         [0026]    Data processing system  100  is a logical partitioned (LPAR) data processing system. Thus, data processing system  100  may have multiple heterogeneous operating systems (or multiple instances of a single operating system) running simultaneously. Each of these multiple operating systems may have any number of software programs executing within it. Data processing system  100  is logically partitioned such that different PCI I/O adapters  120 ,  121 ,  128 ,  129 , and  136 , graphics adapter  148 , and hard disk adapter  149  may be assigned to different logical partitions. In this case, graphics adapter  148  connects to a display device (not shown), while hard disk adapter  149  connects to and controls hard disk  150 . 
         [0027]    Thus, for example, suppose data processing system  100  is divided into three logical partitions, P 1 , P 2 , and P 3 . Each of PCI I/O adapters  120 ,  121 ,  128 ,  129 , and  136 , graphics adapter  148 , hard disk adapter  149 , each of host processors  101 ,  102 ,  103 , and  104 , and memory from local memories  160 ,  161 ,  162 , and  163  is assigned to each of the three partitions. In these examples, memories  160 ,  161 ,  162 , and  163  may take the form of dual in-line memory modules (DIMMs). DIMMs are not normally assigned on a per DIMM basis to partitions. Instead, a partition will get a portion of the overall memory seen by the platform. For example, processor  101 , some portion of memory from local memories  160 ,  161 ,  162 , and  163 , and I/O adapters  120 ,  128 , and  129  may be assigned to logical partition P 1 ; processors  102  and  103 , some portion of memory from local memories  160 ,  161 ,  162 , and  163 , and PCI I/O adapters  121  and  136  may be assigned to partition P 2 ; and processor  104 , some portion of memory from local memories  160 ,  161 ,  162 , and  163 , graphics adapter  148  and hard disk adapter  149  may be assigned to logical partition P 3 . 
         [0028]    Each operating system executing within data processing system  100  is assigned to a different logical partition. Thus, each operating system executing within data processing system  100  may access only those I/O units that are within its logical partition. Thus, for example, one instance of the Advanced Interactive Executive (AIX) operating system may be executing within partition P 1 , a second instance (image) of the AIX operating system may be executing within partition P 2 , and a Linux or OS/400 operating system may be operating within logical partition P 3 . 
         [0029]    Peripheral component interconnect (PCI) host bridge  114  connected to I/O bus  112  provides an interface to PCI local bus  115 . PCI I/O adapters  120  and  121  connect to PCI bus  115  through PCI-to-PCI bridge  116 , PCI bus  118 , PCI bus  119 , I/O slot  170 , and I/O slot  171 . PCI-to-PCI bridge  116  provides an interface to PCI bus  118  and PCI bus  119 . PCI I/O adapters  120  and  121  are placed into I/O slots  170  and  171 , respectively. Typical PCI bus implementations support between four and eight I/O adapters (i.e. expansion slots for add-in connectors). Each PCI I/O adapter  120 - 121  provides an interface between data processing system  100  and input/output devices such as, for example, other network computers, which are clients to data processing system  100 . 
         [0030]    An additional PCI host bridge  122  provides an interface for an additional PCI bus  123 . PCI bus  123  connects to a plurality of PCI I/O adapters  128  and  129 . PCI I/O adapters  128  and  129  connect to PCI bus  123  through PCI-to-PCI bridge  124 , PCI bus  126 , PCI bus  127 , I/O slot  172 , and I/O slot  173 . PCI-to-PCI bridge  124  provides an interface to PCI bus  126  and PCI bus  127 . PCI I/O adapters  128  and  129  are placed into I/O slots  172  and  173 , respectively. In this manner, additional I/O devices, such as, for example, modems or network adapters may be supported through each of PCI I/O adapters  128 - 129 . Consequently, data processing system  100  allows connections to multiple network computers. 
         [0031]    A memory mapped graphics adapter  148  is inserted into I/O slot  174  and connects to I/O bus  112  through PCI bus  144 , PCI-to-PCI bridge  142 , PCI bus  141 , and PCI host bridge  140 . Hard disk adapter  149  may be placed into I/O slot  175 , which connects to PCI bus  145 . In turn, this bus connects to PCI-to-PCI bridge  142 , which connects to PCI host bridge  140  by PCI bus  141 . 
         [0032]    A PCI host bridge  130  provides an interface for PCI bus  131  to connect to I/O bus  112 . PCI I/O adapter  136  connects to I/O slot  176 , which connects to PCI-to-PCI bridge  132  by PCI bus  133 . PCI-to-PCI bridge  132  connects to PCI bus  131 . This PCI bus also connects PCI host bridge  130  to the service processor mailbox interface and ISA bus access passthrough  194  and PCI-to-PCI bridge  132 . Service processor mailbox interface and ISA bus access passthrough  194  forwards PCI accesses destined to the PCI/ISA bridge  193 . NVRAM storage  192  connects to the ISA bus  196 . Service processor  135  connects to service processor mailbox interface and ISA bus access passthrough logic  194  through its local PCI bus  195 . Service processor  135  also connects to processors  101 ,  102 ,  103 , and  104  via a plurality of JTAG/I 2 C busses  134 . JTAG/I 2 C busses  134  are a combination of JTAG/scan busses (see IEEE 1149.1) and Phillips I 2 C busses. However, alternatively, JTAG/I 2 C busses  134  may be replaced by only Phillips I 2 C busses or only JTAG/scan busses. All SP-ATTN signals of the host processors  101 ,  102 ,  103 , and  104  connect together to an interrupt input signal of service processor  135 . Service processor  135  has its own local memory  191  and has access to the hardware OP-panel  190 . 
         [0033]    When data processing system  100  is initially powered up, service processor  135  uses the JTAG/I 2 C busses  134  to interrogate the system (host) processors  101 ,  102 ,  103 , and  104 , memory controller/cache  108 , and I/O bridge  110 . At the completion of this step, service processor  135  has an inventory and topology understanding of data processing system  100 . Service processor  135  also executes Built-In-Self-Tests (BISTs), Basic Assurance Tests (BATs), and memory tests on all elements found by interrogating the host processors  101 ,  102 ,  103 , and  104 , memory controller/cache  108 , and I/O bridge  110 . Any error information for failures detected during the BISTs, BATs, and memory tests are gathered and reported by service processor  135 . 
         [0034]    If a meaningful and valid configuration of system resources is still possible after taking out the elements found to be faulty during the BISTs, BATs, and memory tests, then data processing system  100  is allowed to proceed to load executable code into local (host) memories  160 ,  161 ,  162 , and  163 . Service processor  135  then releases host processors  101 ,  102 ,  103 , and  104  for execution of the code loaded into local memory  160 ,  161 ,  162 , and  163 . While host processors  101 ,  102 ,  103 , and  104  are executing code from respective operating systems within data processing system  100 , service processor  135  enters a mode of monitoring and reporting errors. The type of items monitored by service processor  135  include, for example, the cooling fan speed and operation, thermal sensors, power supply regulators, and recoverable and non-recoverable errors reported by processors  101 ,  102 ,  103 , and  104 , local memories  160 ,  161 ,  162 , and  163 , and I/O bridge  110 . 
         [0035]    Service processor  135  saves and reports error information related to all the monitored items in data processing system  100 . Service processor  135  also takes action based on the type of errors and defined thresholds. For example, service processor  135  may take note of excessive recoverable errors on a processor&#39;s cache memory and decide that this is predictive of a hard failure. Based on this determination, service processor  135  may mark that resource for de-configuration during the current running session and future Initial Program Loads (IPLs). IPLs are also sometimes referred to as a “boot” or “bootstrap”. 
         [0036]    Data processing system  100  may be implemented using various commercially available computer systems. For example, data processing system  100  may be implemented using IBM eServer iSeries Model 840 system available from International Business Machines Corporation. Such a system may support logical partitioning using an OS/400 operating system, which is also available from International Business Machines Corporation. 
         [0037]    Those of ordinary skill in the art will appreciate that the hardware depicted in  FIG. 1  may vary. For example, other peripheral devices, such as optical disk drives and the like, also may be used in addition to or in place of the hardware depicted. The depicted example is not meant to imply architectural limitations with respect to illustrative embodiments. 
         [0038]    With reference now to  FIG. 2 , a block diagram of an exemplary logical partitioned platform is depicted in which illustrative embodiments may be implemented. The hardware in logical partitioned platform  200  may be implemented as, for example, data processing system  100  in  FIG. 1 . Logical partitioned platform  200  includes partitioned hardware  230 , operating systems  202 ,  204 ,  206 ,  208 , and partition management firmware  210 . Operating systems  202 ,  204 ,  206 , and  208  may be multiple copies of a single operating system or multiple heterogeneous operating systems simultaneously run on logical partitioned platform  200 . These operating systems may be implemented using OS/400, which are designed to interface with a partition management firmware, such as PowerVM, which is available from International Business Machines Corporation. OS/400 is used only as an example in these illustrative embodiments. Of course, other types of operating systems, such as AIX and Linux, may be used depending on the particular implementation. Operating systems  202 ,  204 ,  206 , and  208  are located in partitions  203 ,  205 ,  207 , and  209 . Partition management firmware software is an example of software that may be used to implement partition management firmware  210  and is available from International Business Machines Corporation. Firmware is “software” stored in a memory chip that holds its content without electrical power, such as, for example, read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and non-volatile random access memory (non-volatile RAM). 
         [0039]    Additionally, these partitions also include partition firmware  211 ,  213 ,  215 , and  217 . Partition firmware  211 ,  213 ,  215 , and  217  may be implemented using initial boot strap code, IEEE-1275 Standard Open Firmware, and runtime abstraction software (RTAS), which is available from International Business Machines Corporation. When partitions  203 ,  205 ,  207 , and  209  are instantiated, a copy of boot strap code is loaded onto partitions  203 ,  205 ,  207 , and  209  by partition management firmware  210 . Thereafter, control is transferred to the boot strap code with the boot strap code then loading the open firmware and RTAS. The processors associated or assigned to the partitions are then dispatched to the partition&#39;s memory to execute the partition firmware. 
         [0040]    Partitioned hardware  230  includes processors  232 ,  234 ,  236 , and  238 , memories  240 ,  242 ,  244 , and  246 , input/output (I/O) adapters  248 ,  250 ,  252 ,  254 ,  256 ,  258 ,  260 , and  262 , and storage unit  270 . Each of processors  232 ,  234 ,  236 , and  238 , memories  240 ,  242 ,  244 , and  246 , NVRAM storage  298 , and I/O adapters  248 ,  250 ,  252 ,  254 ,  256 ,  258 ,  260 , and  262  may be assigned to one of multiple partitions within logical partitioned platform  200 , each of which corresponds to one of operating systems  202 ,  204 ,  206 , and  208 . 
         [0041]    Partition management firmware  210  performs a number of functions and services for partitions  203 ,  205 ,  207 , and  209  to create and enforce the partitioning of logical partitioned platform  200 . Partition management firmware  210  is a firmware implemented virtual machine identical to the underlying hardware. Thus, partition management firmware  210  allows the simultaneous execution of independent OS images  202 ,  204 ,  206 , and  208  by virtualizing all the hardware resources of logical partitioned platform  200 . 
         [0042]    Service processor  290  may be used to provide various services, such as processing of platform errors in the partitions. These services also may act as a service agent to report errors back to a vendor, such as International Business Machines Corporation. Operations of the different partitions may be controlled through a hardware management console, such as hardware management console  280 . Hardware management console  280  is a separate data processing system from which a system administrator may perform various functions including reallocation of resources to different partitions. 
         [0043]    Referring now to  FIG. 3 , a data processing system for controlling access to a contested resource is shown according to an illustrative embodiment. Data processing system  300  can be a data processing system, such as logical partitioned platform  200  of  FIG. 2 . 
         [0044]    Data processing system  300  includes central processing unit  310 . Central processing unit  310  is the portion of data processing system  300  that carries out instructions. Data processing system  300  is the primary element carrying out the computer&#39;s functions. Central processing unit  310  carries out each instruction of the program in sequence to perform the basic arithmetical, logical, and input/output operations of the system. 
         [0045]    Data processing system  300  includes kernel  312 . Kernel  312  is a bridge between applications and the actual data processing done at the hardware level. Kernel  312  manages the resources of data processing system  300  including communication between hardware and software components. 
         [0046]    Data processing system  300  includes partition management firmware  314 . Partition management firmware  314  can be, for example, partition management firmware  210  of  FIG. 2 . Partition management firmware, also known as a partition management firmware or virtual machine monitor, is software that provides virtualization to a logical partitioned platform by creating and enforcing the partitioning of a logical partitioned platform. Partition management firmware  314  provides virtualization for the execution of virtual machine  316  and virtual machine  318 . Partition management firmware  314  enables the sharing of hardware resources among virtual machine  316  and virtual machine  318  executing on those hardware resources. Partition management firmware  314  enforces access restrictions between virtual machine  316  and virtual machine  318  executing on those hardware resources. 
         [0047]    Virtual machine  316  and virtual machine  318  are controlled by partition management firmware  314  and execute on central processing unit  310 . Each of virtual machine  316  and virtual machine  318  is a software implementation of a machine that executes programs like a physical machine. Virtual machine  316  and virtual machine  318  share the underlying resources of central processing unit  310 , as well as other hardware attached to or incorporated into data processing system  300 . 
         [0048]    Virtual machine  316  includes virtual central processing unit  320 . Virtual central processing unit  320  is the processor for virtual machine  316 . Virtual central processing unit  320  executes instructions for virtual machine  316 . 
         [0049]    Virtual machine  318  includes virtual central processing unit  322 . Virtual central processing unit  322  is the processor for virtual machine  318 . Virtual central processing unit  322  executes instructions for virtual machine  318 . 
         [0050]    Data processing system  300  includes contested resource  323 . Contested resource  323  is data, program instructions, or hardware that is utilized by both virtual central processing unit  320  and virtual central processing unit  322 . 
         [0051]    In order to maintain process synchronization, data processing system  300  includes lock  324 . Lock  324  is a synchronization mechanism for enforcing limits on access to contested resource  323  by virtual machine  316  and virtual machine  318 . Lock  324  ensures that virtual machine  316  and virtual machine  318  do not concurrently attempt to utilize contested resource  323 . If virtual machine  316  is utilizing contested resource  323 , virtual machine  318  must wait until virtual machine  316  finishes before virtual machine  318  is able to access contested resource  323 . Conversely, if virtual machine  318  is utilizing contested resource  323 , virtual machine  316  must wait until virtual machine  318  finishes before virtual machine  316  is able to utilize contested resource  323 . In one illustrative embodiment, lock  324  may be implemented as part of a synchronization control. 
         [0052]    In one illustrative embodiment, lock  324  is a spinlock. A spinlock is a lock where a thread wanting to access a contested resource simply waits in a loop repeatedly checking until the lock becomes available. Once the lock is available, the thread is able to access the contested resource. As the waiting thread “spins,” it remains active but does not perform any task other than waiting on another thread to release the lock. 
         [0053]    Each of virtual central processing unit  320  and virtual central processing unit  322  is allocated a time slice. Virtual central processing unit  320  is allocated time slice  326 . Virtual central processing unit  322  is allocated time slice  328 . Each of time slice  326  and time slice  328  is an allocated amount of time that the corresponding one of virtual central processing unit  320  and virtual central processing unit  322  is normally allowed to execute on central processing unit  310  without being preempted by another process. At the end of a time slice, kernel  312  chooses which process to run next on central processing unit  310  based on process priorities. Defined duration  330  is the length of time of time slice  326 . Defined duration  332  is the length of time of time slice  328 . 
         [0054]    Data processing system  300  includes clock  334 . In one illustrative embodiment, clock  334  can be implemented in kernel  312 . Clock  334  is a timer mechanism that is, among other possible functions, capable of tracking defined duration  330  of time slice  326  and defined duration  332  of time slice  328 . 
         [0055]    In data processing systems that contain a partition management firmware and many guest operating systems, performance is a major concern. The partition management firmware controls access to a physical CPU core, and each guest operating system has virtual CPUs (VCPU). It is often the case that the total number of VCPUs for all the guest operating systems is greater than the number of physical central processing units in the system. The partition management firmware controls the time slices that each VCPU gets to execute on the physical CPU core. 
         [0056]    In cases where the guest OS needs to take a spinlock, performance can be very bad if, during the time that VCPU holds a spinlock, it gets preempted and another VCPU gets a time slice and then tries to acquire that spinlock. This is commonly referred to as lockholder preemption. 
         [0057]    Currently used processes employs “pause loop exiting” in which those VCPUs trying to acquire a spinlock trap to the partition management firmware. The partition management firmware then reschedules the VPCU that holds the lock. However, this method still has significant overhead and causes performance to slow. 
         [0058]    The present invention overcomes the deficiencies of previously implemented pause loop exiting by implementing a hardware extension to the processor that allows lock instructions in operating system guests to conditionally trap to the partition management firmware. The conditional trapping to the partition management firmware only occurs when the virtual CPU is near the end of its allocated time slice. This can be measured by calculating the delta between current time and the next scheduled timer interrupt. For example, if a time slice is 10 ms long and the virtual CPU has run for 9.5 ms, the timer interrupt would be 0.5 ms in the future. If the lock instruction is set to trap in the last 1 ms of the time slice, it would trap in this instance when the virtual CPU attempts to acquire a lock. The partition management firmware would then end the time slice early and schedule a different virtual CPU who would be free to acquire the lock. 
         [0059]    Data processing system  300  also includes lock-held flag  336 . Lock-held flag  336  is an indication as to whether one of virtual central processing unit  320  or virtual central processing unit  322  currently holds lock  324 . 
         [0060]    The illustrative embodiments further overcome the deficiencies of previously implemented pause loop exiting by implementing a “lock-held flag” in the processor state. When the partition management firmware performs a context switch from a virtual CPU, the partition management firmware can look at the “lock-held flag” and decide to extend a time slice of that virtual CPU. This increases the chances of the lock being released before the virtual CPU is time sliced. 
         [0061]    Referring now to  FIG. 4 , a timeline for lock acquisition and lock release in system having multiple virtual processors is shown according to the prior art. Timeline  400  is a representation of the relative times of various processing steps occurring within a data processing system, such as logical partitioned platform  200  of  FIG. 2 . 
         [0062]    VCPU  1  is allocated processor usage during time slice  412 . At time  414 , VCPU  1  acquires a lock for a contested resource. At time  416 , time slice  412  expires, and VCPU  1  is preempted by VCPU  2 . VCPU  1  still holds the lock for the contested resource at the time that time slice  412  expires. 
         [0063]    VCPU  2  is allocated processor usage during time slice  418 . Because VCPU  1  still holds the lock for the contested resource, VCPU  2  is prevented from accessing the contested resource until the lock is released. Because VCPU  1  is not active in time slice  418 , VCPU  1  cannot release the lock during time slice  418 . VCPU  2  is therefore unable to access the contested resource and must instead wait for a subsequent time slice during which the lock has been released. At time  420 , time slice  418  expires, and VCPU  2  is preempted by VCPU  1 . 
         [0064]    VCPU  1  is allocated processor usage during time slice  422 . At time  424 , VCPU  1  releases the lock for the contested resource. At time  426 , time slice  422  expires, and VCPU  1  is preempted by VCPU  2 . 
         [0065]    VCPU  2  is allocated processor usage during time slice  428 . Because VCPU  1  has released the lock for the contested resource, VCPU  2  can now access the contested resource. At time  430 , VCPU  2  acquires the lock for the contested resource. 
         [0066]    Referring now to  FIG. 5 , a timeline for deferred lock acquisition in system having multiple virtual processors is shown according to an illustrative embodiment. Timeline  500  is a representation of the relative times of various processing steps occurring within a data processing system, such as data processing system  300  of  FIG. 3 . 
         [0067]    VCPU  1  is allocated processor usage during time slice  512 . During preemption period  514 , VCPU  1  attempts to acquire a lock for a contested resource. A preemption period is an end portion of the defined duration during which a VCPU is not permitted to acquire a lock. In one illustrative embodiment, the preemption period can be an absolute period of time, such as for example, the last 1 milliseconds of a defined duration of a time slice. In one illustrative embodiment, the preemption period can be a relative period of time, such as for example, the last 10% of a defined duration of a time slice. 
         [0068]    VCPU  1  attempts to acquire the lock at time  516 . Time  516  occurs during preemption period  514 . Therefore, VCPU  1  is not permitted to acquire the lock. In one illustrative embodiment, a partition management firmware, such as partition management firmware  314  of  FIG. 3 , prevents VCPU  1  from acquiring the lock during preemption period  514 . VCPU  1  must instead wait for a subsequent time slice during which the lock has been acquired. In one illustrative embodiment, VCPU  1  can spin for the remainder of time slice  512  until time  516 . In one illustrative embodiment, a partition management firmware such as partition management firmware  314  of  FIG. 3  can simply end time slice  512  after the partition management firmware determines that the lock was requested during preemption period  514 . 
         [0069]    VCPU  2  is allocated processor usage during time slice  518 . At time  520 , time slice  518  expires, and VCPU  2  is preempted by VCPU  1 . 
         [0070]    VCPU  1  is allocated processor usage during time slice  522 . At time  524 , VCPU  1  acquires the lock for the contested resource. Time  524  does not occur during preemption period  526  of time slice  522 . Therefore, VCPU  1  is permitted to acquire the lock. 
         [0071]    Referring now to  FIG. 6 , a timeline for lock acquisition and lock release in system having multiple virtual processors is shown according to an illustrative embodiment. Timeline  600  is a representation of the relative times of various processing steps occurring within a data processing system, such as data processing system  300  of  FIG. 3 . 
         [0072]    VCPU  1  is allocated processor usage during time slice  612 . At time  614 , VCPU  1  acquires a lock for a contested resource. Time  614  occurs prior to preemption period  616 . Therefore, VCPU  1  is permitted to acquire the lock. At time  618 , time slice  612  expires. VCPU  1  still holds the lock for the contested resource at the time that time slice  612  expires. 
         [0073]    A partition management firmware, such as partition management firmware  314  of  FIG. 3  determines that VCPU  1  still holds the lock for the contested resource at the time that time slice  612  expires. The partition management firmware can make this determination by examining a lock-held flag, such as lock-held flag  336  of  FIG. 3 . 
         [0074]    Because the lock is still held by VCPU  1 , the partition management firmware can extend the time slice allocated to VCPU  1  beyond time  618 . In one illustrative embodiment, this extended allocation period can be an absolute period of time, such as for example, an additional 1 millisecond of a defined duration of a time slice. In one illustrative embodiment, the extended allocation period can be a relative period of time, such as for example, an additional 10% of a defined duration of a time slice. 
         [0075]    The partition management firmware extends the time slice allocated to VCPU  1  by extended allocation period  620  to time  622 . VCPU  1  releases the lock at time  624  prior to the expiration of extended allocation period  620  at time  622 . At time  622 , extended allocation period  620  expires, and VCPU  1  is preempted by VCPU  2 . 
         [0076]    Referring now to  FIG. 7 , a flowchart for controlling access to a contested resource is shown according to an illustrative embodiment. Process  700  is a process executing on a computer system, such as data processing system  300  of  FIG. 3 . Process  700  can execute within partition management firmware, such as partition management firmware  314  of  FIG. 3 . 
         [0077]    Process  700  begins by receiving a request for access to a contested resource (step  710 ). The contested resource can be, for example, contested resource  323  of  FIG. 3 . 
         [0078]    Responsive to receiving the contested resource, process  700  determines whether the contested resource is available (step  715 ). In one illustrative embodiment, the process determines whether the contested resource is available by determining whether a lock is currently held for the contested resource. The lock can be, for example, lock  324 , of  FIG. 3 . 
         [0079]    Responsive to determining that the contested resource is not available (“no” at step  715 ), process  700  spins the requesting thread (step  720 ). Process  700  then iterates back to step  715  to wait for the resource to become available. 
         [0080]    Responsive to determining that the contested resource is available (“yes” at step  715 ), process  700  determines whether the request for access to the contested resource is received during a preemption period (step  725 ). The preemption period is an end portion of the defined duration during which a VCPU is not permitted to acquire a lock. The preemption period can be, for example, one of preemption period  514  and preemption period  526  of  FIG. 5 . 
         [0081]    Responsive to determining that the request for access was received during the preemption period (“yes” at step  725 ), process  700  ends a time slice for the virtual processor executing the requesting thread (step  730 ). Because the request occurred during the preemption period, the requesting VCPU  1  is not permitted to acquire the lock. VCPU  1  must instead wait for a subsequent time slice during which the lock has been acquired. Process  700  then performs a context switch (step  735 ), with the process terminating thereafter. 
         [0082]    Returning now to step  725 , responsive to determining that the request for access was not received during the preemption period (“no” at step  725 ), process  700  sets a lock-held flag (step  740 ). The lock-held flag can be, for example, lock-held flag  336  of  FIG. 3 . Process  700  then grants the lock for the contested resource (step  745 ), with the process terminating thereafter. 
         [0083]    Referring now to  FIG. 8 , a flowchart for extending an allocated time slice is shown according to an illustrative embodiment. 
         [0084]    Process  800  begins by identifying that a defined duration of an allocated time slice has expired (step  810 ). The allocated time slice can be, for example, one of time slice  326  and time slice  328  of  FIG. 3 . 
         [0085]    Responsive to identifying that a defined duration of an allocated time slice has expired, process  800  determines whether a lock is held by the virtual machine of the current time slice (step  820 ). In one illustrative embodiment, process  800  can identify whether a lock is held by examining a lock-held flag. The lock-held flag can be, for example, lock-held flag  336  of  FIG. 3 . 
         [0086]    Responsive to determining that a lock is not held by the virtual machine of the current time slice (“no” at step  820 ), the process performs a context switch, (step  830 ), with the process terminating thereafter. 
         [0087]    Responsive to determining that a lock is held by the virtual machine of the current time slice (“yes” at step  820 ), process  800  extends the current time slice by an extended allocation period (step  840 ). The extended allocation period allows a brief time extension during which the lock may be released. 
         [0088]    Responsive to extending the current time slice by the extended allocation period, process  800  executes until the end of the extended time slice (step  850 ). Responsive to reaching the end of the extended time slice, process  800  performs a context switch, (step  830 ), with the process terminating thereafter. 
         [0089]    Thus, illustrative embodiments of the present invention provide a computer implemented method, computer usable program code, and a data processing system for controlling access to a contested resource. When a lock acquisition request is received from a virtual machine, the partition management firmware determines whether the lock acquisition request is received within a preemption period of a time slice allocated to the virtual machine. If the lock acquisition request is received within the preemption period, the partition management firmware ends the time slice early and performs a context switch to prevent possible lockholder preemption situations. 
         [0090]    The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. 
         [0091]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0092]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.