Abstract:
A power supply system to provide power for a central processing unit (CPU) includes a bridge circuit, a pulse width modulation (PWM) controller and a pulse adjusting driver circuit. The bridge circuit detects a work state of the PWM controller to obtain a feedback signal output from the PWM controller, and provides the feedback signal to the CPU. The CPU outputs a control signal to the bridge circuit according to a work state of the CPU and the feedback signal, and the bridge circuit outputs a PWM signal to the pulse adjusting driver circuit according to the control signal. The pulse adjusting driver circuit receives a first driving signal provided by an external circuit, and adjusts the first driving signal according to the PWM signal to generate at least one second driving signal to drive the CPU.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure generally relates to power supply systems, and particularly to a power supply system that can selectively deliver signals in one or more than phase. 
         [0003]    2. Description of Related Art 
         [0004]    Power supply requirements for central processing units (CPUs) used in different electrical devices usually differ even among devices developed by the same company. For example, computers using voltage regulator modules (VRMs) developed by INTEL Corporation have certain power supply requirements that are different from the power supply requirements of computers using INTEL mobile voltage positioning (IMVP) technology. 
         [0005]    Therefore, too many power supply designs are needed to meet the needs of the industry. 
         [0006]    What is needed, therefore, is a power supply system which can overcome the described limitations. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views, and all the views are schematic. 
           [0008]      FIG. 1  is a schematic block diagram of a power supply system according to an embodiment, the power supply system including a pulse adjusting driver circuit. 
           [0009]      FIG. 2  is a schematic circuit diagram of the pulse adjusting driver circuit of  FIG. 1  according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    Reference will be made to the drawings to describe the embodiments in detail. 
         [0011]      FIG. 1  is a schematic block diagram of a power supply system  10  according to an embodiment, the power supply system  10  including a pulse adjusting driver circuit  150 . In this embodiment, the power supply system  10  is configured to provide power to a CPU  20 , and includes a bridge circuit  110 , a pulse width modulation (PWM) controller  130 , and the pulse adjusting driver circuit  150 . In other embodiments, the system  10  may be used to provide power to other kinds of components or devices. 
         [0012]    In one embodiment, the bridge circuit  110  can be an integrated circuit, and includes four pins  111 ,  113 ,  115 ,  117 . The two pins  111 ,  113  are connected to the CPU  20 , the pin  111  is configured to receive a control signal output from the CPU  20 , and the pin  113  is configured to provide a feedback signal to the CPU  20 . The other two pins  115 ,  117  are connected to the PWM controller  130 . 
         [0013]    The PWM controller  130  is a unidirectional PWM controller, and includes a control signal input terminal “CON”, a feedback signal output terminal “FE”, and a PWM signal output terminal “PWM”. The control signal input terminal “CON” and the feedback signal output terminal “FE” are respectively connected to the two pins  115 ,  117  of the bridge circuit  110 , and the PWM signal output terminal “PWM” is connected to the pulse adjusting driver circuit  150 . 
         [0014]    The bridge circuit  110  is configured to detect a work state of the PWM controller  130 , receive the feedback signal output from the feedback signal output terminal “FE” of the PWM controller  130  via the pin  117 , and provide the feedback signal to the CPU  20  via the pin  113 . The CPU  20  is configured to output a control signal according to a work state thereof and the feedback signal. The work state of the CPU  20  may be a power type requirement thereof. The bridge circuit  110  is further configured to receive the control signal via the pin  111 , and provide the control signal to the control signal input terminal “CON” of the PWM controller  130  via the pin  115 . The PWM controller  130  is configured to generate a PWM signal according to the control signal, and output the PWM signal to the pulse adjusting driver circuit  150  via the PWM signal output terminal “PWM”. 
         [0015]    The pulse adjusting driver circuit  150  includes a signal receiving terminal  151 , a driving signal input terminal  153 , and a voltage output terminal  155 . The signal receiving terminal  151  is connected to the PWM signal output terminal “PWM” of the PWM controller  130  to receive the PWM signal, the driving signal input terminal  153  is configured to receive a first driving signal provided by an external circuit, and the voltage output terminal  155  is connected to the CPU  20 . The pulse adjusting driver circuit  150  is configured to adjust a phase of the first driving signal according to the PWM signal, generate a second driving signal, and output the second driving signal to the CPU  20  for driving the CPU  20 . 
         [0016]      FIG. 2  is a schematic circuit diagram of the pulse adjusting driver circuit  150  of  FIG. 1  according to one embodiment. The pulse adjusting driver circuit  150  includes a plurality of pulse adjusting drivers  157  and a plurality of pulse adjusting switch circuits  159  corresponding to the adjusting drivers  157 . In this embodiment, three adjusting drivers  157  and three switch circuits  159  are taken for example. In an alternative embodiment, the numbers of the adjusting drivers  157  and the switch circuits  159  can be increased or decreased to meet an actual requirement of the CPU  20  according to different power supply standards. 
         [0017]    Each adjusting driver  157  includes a PWM signal pin “PWM” connected to the signal receiving terminal  151 , two detection pins “CS−”, “CS+”, an average current pin “Lavg”, a power pin “VCC”, a ground “GND”, a phase pin “PHASE”, a phase adjusting pin “PH#”, a bootstrap pin “BOOT”, a low pass pin “LGATE”, and a high pass pin “UGATE”. Each pulse adjusting driver  157  further includes an average current controller (not shown) and a phase controller (not shown) therein. The power pin “VCC” is connected to an external power source, and the ground “GND” is grounded. 
         [0018]    In this embodiment, a first capacitor C 1  is connected between the bootstrap pin “BOOT” and the phase pin “PHASE” to pull up a voltage of the phase pin “PHASE”. In an alternative embodiment, the second capacitor C 2  can be omitted. In this embodiment, the phase adjusting pin “PH#” is grounded via a phase adjusting resistor R, and the phase controller can automatically adjust a phase of the PWM signal received by the pulse adjusting driver circuit  150  by adjusting a resistance of the phase adjusting resistor R. The adjusted PWM signal is output to the corresponding switch circuit  159  via the phase pin “PHASE” to adjust the phase of the first driving signal. 
         [0019]    Each switch circuit  159  includes a first transistor Q 1 , a second transistor Q 2 , an inductor L, a second capacitor C 2 . Each of the first transistor Q 1  and the second transistor Q 2  includes a control terminal (not labeled), a first conducting terminal (not labeled), and a second conducting terminal (not labeled). 
         [0020]    The phase pin “PHASE” of the corresponding adjusting driver  157  is connected to the voltage output terminal  155  via the inductor L. The two detection pins 
         [0021]    “CS−”, “CS+” of the corresponding adjusting driver  157  are connected to two terminals of the inductor L to detect an inducting current flowing through the inductor L. The average current controller of the corresponding adjusting driver  157  outputs an average current signal via the average current pin “Lavg” according to the inducting current. The average current pins “Lavg” of all the adjusting drivers  157  are connected to one another to make average current signals output from the adjusting drivers  157  be equal. 
         [0022]    The control terminal of the first transistor Q 1  is connected to the low pass pin “LGATE” of the corresponding adjusting driver  157 . The first conducting terminal of the first transistor Q 1  is connected to the phase pin “PHASE” of the corresponding adjusting driver  157  and the second conducting terminal of the second transistor Q 2 . The second conducting terminal of the first transistor Q 1  is grounded. The control terminal of the second transistor Q 2  is connected to the high pass pin “UGATE” of the corresponding adjusting driver  157 . The first conducting terminal of the second transistor Q 2  is connected to the driving signal input terminal  153 . In this embodiment, the first and second transistors Q 1 , Q 2  are field effect transistors, and the control terminal, the first conducting terminal and the second conducting terminal of each of the first and second transistors Q 1 , Q 2  respectively correspond to a gate electrode, a drain electrode, and a source electrode of the field effect transistor. 
         [0023]    The second capacitor C 2  is connected between the voltage output terminal  155  and ground to filter the second driving signal. 
         [0024]    In this embodiment, the adjusting driver  157  adjusts the phase of the PWM signal by adjusting a resistance of the phase adjusting resistor R. In other embodiments, the phase controller of the adjusting drivers  157  can be designed to realize a phase adjusting function by adjusting parameters of other components, such as capacitances of capacitors or inductances of inductors, and not limited to the resistance of the phase adjusting resistor R. 
         [0025]    In operation, the signal receiving terminal  151  receives the PWM signal output from the PWM controller  130 . Each adjusting driver  157  adjusts the phase of the PWM signal by adjusting the resistance of the respective phase adjusting resistor R to make the adjusted PWM signals provided by all the adjusting drivers  157  have different phases. Each adjusting driver  157  outputs a low pass driving signal and a high pass driving signal respectively via the low pass pin “LGATE” and the high pass pin “UGATE” to turn on/off the first and second transistors Q 1 , Q 2  of the corresponding switch circuit  159  by time-sharing control. That is, each adjusting driver  157  respectively outputs the low pass driving signal and the high pass driving signal during different times, thus the first and second transistors Q 1 , Q 2  of each corresponding switch circuit  159  can be turned on/off without during the same time. Under the condition that the first transistor Q 1  is turned off and the second transistor Q 2  is turned on, the first driving signal received by the driving signal input terminal  153  and the adjusted PWM signal output from the phase pin “PHASE” are provided to the inductor L, and transformed into the second driving signal output from the voltage output terminal  155  via the inductor L. 
         [0026]    Due to the phase of the second driving signal from each adjusting driver  157  different from one another, the pulse adjusting driver circuit  150  can provide driving signals having different phases to the CPU  20  in time-sharing or during different times to achieve a multiphase output function. Therefore, the CPU  20  can work with multiphase driving signal. 
         [0027]    In an alternative embodiment, if the CPU  20  merely needs a single phase driving signal, the pulse adjusting driver circuit  150  can merely include one pulse adjusting driver  157  and one corresponding pulse adjusting switch circuit  159  to provide the driving signal to the CPU  20 . 
         [0028]    Therefore, even the power supply standards change, the power supply system  10  can change the number of the pulse adjusting driver  157  and the pulse adjusting switch circuit  159  or adjust the outputs of the pulse adjusting drivers  157  to meet the different power supply standards. Thus, the power supply system  10  can provide power to the CPUs of different network devices, such as desktop computers, notebooks, workstations, servers, and the like. 
         [0029]    It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the embodiments or sacrificing all of their material advantages.