Abstract:
A signal processing large scale integrated circuit for carrying out convolution calculations includes multiple delay stages serially connected to thereby form an input data path for a first input signal, a first calculation circuit wherein predetermined calculations are carried out using the output of each of the above mentioned delay stages and a second calculation circuit connected to a convolution path wherein predetermined calculations are carried out using the output of the above mentioned first calculation circuit and a second input signal output from another large scale integrated circuit. The problem of a prolonged delay when multiple LSI circuits are cascade-connected together is eliminated by outputting the first output signal from an intermediate delay element and supplying it as the input to the next stage large scale integrated circuit. Additionally, the direction of the input data path and the convolution path are reverse with respect to one another, so that the value calculated in the first calculation circuit in the first circuit is calculated using the output from the following stage circuit. As a result, the total delay of the cascade-connected circuits is equivalent to the delay of the first circuit in the cascade.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention pertains to integrated signal processing circuits suitable for application to circuits for carrying out convolution calculations. 
     2. Related Art 
     Convolution calculation circuits are often employed in devices such as digital audio equipment wherein various types of filtering operations are applied to an audio signal, including equalization, reverberation effect processing and the like. As an example of this kind of circuit, a block diagram illustrating the fundamental makeup of an N stage convolution calculation circuit is shown in FIG. 3, where N is an integral value. In the illustrated circuit, a digital signal is input periodically at a sampling cycle length given by τ, whereupon the supplied signal is sequentially delayed in serially connected delay circuits D 1 , D 2  , . . . D N-1 . The above mentioned delay circuits D 1 , D 2  , . . . D N-1  comprise registers, where each respective register is of a fixed bit width. To each of these registers, a clock pulse is supplied periodically at the above mentioned sampling cycle length τ. Accordingly, at the point in time when sample signal X n  is input to delay circuit D 1 , the sample signal output from delay circuit D 1  at that point in time is sample signal X n-1  which was input at a point time τ previously, the sample signal output from delay circuit D 2  when sample signal X n  is input to delay circuit D 1  is sample signal X n-2  which was input at a point in time 2τ previously, and the sample signal output from delay circuit D N-1  when sample signal X n  is input to delay circuit D 1  is sample signal X n-N-1  which was input at a point in time (N-1)τ previously. Input signal Xn, as well as the output signal X n  -1, X n-2  , . . . N n-N+  of each delay circuit D 1  D 2  , . . . D N-1 , respectively, are each provided to a respective multiplier circuit M 0 , M 1  , . . . M N-1 , wherein each supplied signal is multiplied by a corresponding multiplication coefficient C 0 , C 1  , . . . C N-1 , the output of each multiplication then being supplied to adder A wherein the result of all of the multiplication operations are added together. In this way, within the described convolution calculation circuit, a plurality of convolution calculations are carried out, after which the results of all of the calculations are summed in adder A, the result of which is output as digital data Y n . This operation is mathematically expressed in Equ. 1 below: ##EQU1## 
     When an attempt is made to implement the above described convolution calculation circuit with a great number of convolution calculations using LSI (large scale integration) techniques, the total number of components inevitably becomes unmanageably large, thus making such an implementation in a single LSI integrated circuit quite difficult from a practical point of view. 
     Methods exist for applying LSI techniques to convolution calculation circuits having a great number of calculation stages, wherein two or more signal processing LSI integrated circuits are fabricated, each integrated circuit corresponding to a continuous series of calculation stages. With such an implementation, the entire series of delay stages over which the convolution calculations occur is divided into two or more continuous blocks along the time axis with respect to time delay. The calculations of each of these blocks are allocated to a corresponding one of the above mentioned signal processing LSI integrated circuits. By cascade connecting the signal processing LSI integrated circuits, the entire convolution calculation circuit is formed. 
     In FIG. 4, an example of this kind of convolution calculation circuit is shown. The illustrated circuit is made up of three signal processing LSI integrated circuits LSI 11, LSI 12 and LSI 13, each having M convolution calculation stages, where M is an integral value, thus comprising 3M convolution calculation stages for the circuit as a whole. All elements in FIG. 4 corresponding to elements in the circuit of FIG. 3 described above will retain the original identifying numeral. 
     To describe an example of the operation of the circuit shown in FIG. 4, when a signal is input at input port DI of signal processing LSI integrated circuit LSI 11, it first passes through delay circuit D 0  where it is delayed by a single sampling interval τ, after which it then passes successively through each of the delay circuits D 1 , D 2  , . . . D N-1 , as well as through multiplier circuits M 0 , M 1 , to then be summed in adder A 11 , just as was described above for the circuit of FIG. 3. 
     In the circuit presently under discussion, delay circuit D 0  acts as an interface and provides an initial delay for the sampling signal after it passes through input port DI. In the same way, delay circuits DJ 01 , DJ 02 , DK 01 , and DK 02  act to delay incoming and outgoing data for signal processing LSI integrated circuit LSI 11. 
     In addition to the results of each of the multiplication operations carried out in multiplication circuits M 0 , M 1  , . . . M M-1 , adder A 1  1 also includes in the calculated sum any signal provided to convolution calculation result input port SI after first passing through delay circuit DK 01  where the input signal is first delayed by a single sampling interval τ before it is supplied to adder A 11 . In the case of signal processing LSI integrated circuit LSI 11, no signal is supplied to convolution calculation result input port SI since it is the first signal processing circuit in the cascade. The result of the addition operation output from adder A 11  is then supplied to delay circuit DK 02  where the input signal is first delayed by a single sampling interval τ, after which it is output at convolution calculation result output port SO as the result of the convolution calculations carried out in signal processing LSI integrated circuit LSI 11. Thus output, the signal is then supplied to convolution calculation result input port SI of signal processing LSI integrated circuit LSI 12, the next integrated circuit in the cascade. The signal thus supplied to convolution calculation result input port SI of signal processing LSI integrated circuit LSI 12 is then further delayed in delay circuit DK 11  by a single sampling interval τ. 
     On the other hand, the output signal from delay circuit D M-1  is signal processing LSI integrated circuit LSI 11 passes through delay circuits DJ 01  and DJ 02  thereby causing it to be delayed by two sampling intervals τ before being output at delayed signal output port DO. From delayed signal output port DO, the signal is supplied to the following signal processing stage, signal processing LSI integrated circuit LSI 12 via calculation result input port SI. As described above, in signal processing LSI integrated circuit LSI 11, the sum of the delay intervals in delay circuits DJ 01  and DJ 02  and the sum of the delay intervals in delay circuits DK 01  and DK 02  are equal. In this way, the phase of the delayed sampling signal supplied from signal processing LSI integrated circuit LSI 11 to signal processing LSI integrated circuit LSI 12 remains synchronized with the phase of the result of the convolution calculations. 
     Signal processing LSI integrated circuit LSI 12 which is connected with the last stage of signal processing LSI integrated circuit LSI 11 is of an analogous structure to signal processing LSI integrated circuit LSI 11. However, in the case of signal processing LSI integrated circuit LSI 12, the multiplication coefficients by which each successively delayed sampling signal is multiplied are designated as multiplication coefficients C M , C M+1  , . . . C 2M-1 . Thus, in signal processing LSI integrated circuit LSI 12, the signal input at calculation result input port SI from signal processing LSI integrated circuit LSI 11 is successively delayed in delay circuits D M , D M+1  , . . . D 2M-1 , and each successively delayed signal is multiplied in a respective multiplication circuit M M , M M+1  , . . . M 2M-1  by a corresponding multiplication coefficient C M , C M+1  , . . . C 2M-1 , just as described for signal processing LSI integrated circuit LSI 11 above. The results of these multiplication operations are then summed in adder A 12  , along with the first stage convolution calculation signal input at calculation result input port SI after it has been delayed in delay circuit DK 11 . The result of this addition operation is then output at calculation result output port SO after first being delayed by a single sampling interval τ in delay circuit DK 12 . Thus having undergone convolution calculations in signal processing LSI integrated circuit LSI 11 and LSI 12, the signal output from calculation result output port SO of signal processing LSI integrated circuit LSI 12 is supplied to the calculation result input port SI of the following signal processing stage, signal processing LSI integrated circuit LSI 13. In the present example, the structure of signal processing LSI integrated circuit LSI 13 is analogous to that of the previously described signal processing LSI integrated circuits LSI 11 and LSI 12. 
     In the following, with reference to FIG. 5, the operation of this conventional convolution calculation circuit will be described. At a given point in time t 0 , a sample signal X n  is supplied to input port DI (node N 0 ) of the first stage signal processing circuit, signal processing LSI integrated circuit LSI 11. Because the sample signal output from signal processing LSI integrated circuit LSI 11 at delayed signal port DO (node 1) at time t 0  has traversed M+2 delay circuits, this signal is sample signal X n-M-2  which was input at input port DI (node N 0 ) at a point in time (M+2)τ earlier than time t 0 . In the same way, because the sample signals output from signal processing LSI integrated circuits LSI 12 and LSI 13 at their respective delayed signal output ports DO (nodes N 2  and N 3  respectively) have traversed M+2 delay circuits in each of these integrated circuits, at time t 0 , the signal at node N 2  is sample signal X n-2M-4 , and that at node N 3  is sample signal X n-3M-6 . 
     At time t 0 , sample signals X n-1 , X n  , . . . X n-M  are output from delay circuits D 0 , D 1  , . . . D M-1 , respectively, and their aggregate sum is determined in adder A 11 . Accordingly, at time t 0 , the signal value at node N 1a  is given by Equ. 2 below: ##EQU2## Since two delay circuits are interposed in the connection between adders A 11  and A 12 , the signal supplied to adder A 12  from adder A 11  at time t 0  is the signal output from adder A 11  at a point in time 2τ earlier than time t 0 , the value of which is given by Equ. 3 below: ##EQU3## Sample signals X n-M-3 , X n-M-2  , . . . X n-2M-2  are output from delay circuits D M , D M+1  , . . . D 2M-1 , respectively, at time t 0 . Thus, the value of the signal present at node N 2a  at time t 0 , which is the result of adding the results obtained by multiplying each of sample signals X n-M-3 , X n-M-2  , . . . X n-2M-2  by a respective multiplication coefficient in a respective multiplication circuit, and additionally adding the signal supplied from adder A 11  in adder A 12 , is given by Equ. 4 below: ##EQU4## The result of the convolution calculations carried out in signal processing LSI integrated circuit LSI 12, as given by Equ. 4 above, is then employed in the convolution calculations carried out in the following stage, signal processing LSI integrated circuit LSI 13 after having been delayed by two sampling intervals τ. After undergoing further convolution calculation processing in signal processing LSI integrated circuit LSI 13, which is analogous to that described for signal processing LSI integrated circuits LSI 11 and LSI 12, the final result of the convolution calculations over the three stages is output at calculation result output port SO of signal processing LSI integrated circuit LSI 13 after having been delayed by an additional sampling interval τ. Thus, the value of the signal at node N 4  at time t 0  is given by Equ. 5 below: ##EQU5## It can therefore be seen that at time t 0 , the convolution calculation result output at node N 4  represents the result of convolution calculations involving 3M sample signals from sample signal X n-6  which was input a point in time 6τ prior to time t 0  and all sample signals input up to and including sample signal X n  input at time time t 0 . Accordingly, and as is shown in FIG. 5, when a sample signal X n  is input into the conventional convolution calculation circuit shown in FIG. 4 at time t 0 , at time t 6  six sampling intervals τ after time t 0 , the result of convolution calculations involving sample signals X n , X n-1  , . . . X n-3M+1  is output at node N4. 
     In the above description where three integrated circuits are cascade connected, to further expand the system by adding fourth and fifth stages, the number of delay circuits which a signal must traverse and which are not directly involved in the convolution calculations (for example, delay circuits DK 01  and DK 02  in signal processing LSI integrated circuit LSI 11) increases in proportion to the number of calculation stages. Thus, in conventional convolution calculation circuits in which two or more signal processing LSI integrated circuits are cascade connected, with each added signal processing LSI integrated circuit, the amount of time which is required for signals to pass through delay elements not directly involved in the convolution calculations increases. For this reason, the elapsed time between when a signal is input and when calculation results involving that signal are output becomes quite long, which is a significant problem for many of the applications of this type of circuit. For example, in the case of an electronic musical instrument, for the individual operating such a musical instrument, any noticeable delay between the actions of the operator and the time at which the effect is produced in the musical output is clearly undesirable. 
     SUMMARY OF THE INVENTION 
     In consideration of the above, it is an object of the present invention to provide a signal processing integrated circuit for which when two or more of these circuits are cascade connected together, the delay stages in each circuit which are not directly involved with signal processing calculations do not exert a great effect on the time required for an input signal to traverse the cascaded circuits as a whole. 
     To achieve the above object, the signal processing integrated circuit of the present invention includes a serial delay means which is formed of multiple delay stages connected in series, each of which having a predetermined delay interval. A first input signal is supplied to the first delay stage of the above mentioned serial delay means, and a first output signal is output from a delay stage a predetermined number of delay stages prior to the final delay stage. Additionally, the signal processing integrated circuit of the present invention includes a first calculation means wherein predetermined calculations are carried out using the output of each delay stage of the above mentioned serial delay means. Furthermore, the signal processing integrated circuit of the present invention includes a second calculation means wherein predetermined calculations are carried out using the output of the above mentioned first calculation means and a second input signal, the result of the calculations then being output as a second output signal. With the signal processing integrated circuit of the present invention, the above mention first output signal is delayed by a time interval less than the total delay interval of the above mentioned serial delay means. 
     Moreover, when two or more signal processing integrated circuits of the present invention are cascade connected, for each adjacent pair of integrated circuits, if the first output signal of the first integrated circuit in the pair is supplied as the first input signal to the following integrated circuit, and if the second output signal of the following integrated circuit is supplied as the first input signal to the first integrated circuit of the pair, when a signal is input as the second input signal to the final integrated circuit in the cascade, an output signal from the cascade can be obtained after a very short delay, the delay bearing no relationship to the total number of delay stages in the cascade connected integrated circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a calculation circuit employing a signal processing LSI integrated circuit of a first preferred embodiment of the present invention. 
     FIG. 2 is a time chart illustrating the operation of the signal processing LSI integrated circuit of the first preferred embodiment of the present invention. 
     FIG. 3 is a block diagram illustrating the structure of a conventional general purpose convolution calculation circuit. 
     FIG. 4 is a block diagram illustrating the composite structure of a calculation circuit in which three conventional convolution calculation circuits have been cascade connected together. 
     FIG. 5 is a time chart illustrating the operation of the conventional signal processing LSI integrated circuit shown in FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, a first preferred embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of a calculation circuit employing signal processing LSI integrated circuits LSI 21, LSI 22 and LSI 23 of present embodiment. Description of all elements in FIG. 1 corresponding to elements in the circuit of FIG. 3 previously described will be abbreviated and the elements will retain the original identifying numeral used in FIG. 3. 
     Just as with signal processing LSI integrated circuit LSI 11 shown in FIG. 3, in the signal processing LSI integrated circuit of the present embodiment, delayed signals for use in calculations are generated using M stages of serially connected delay circuits D 0 , D 1  , . . . D M-1 . However, in the case of signal processing LSI integrated circuits LSI 21, LSI 22 and LSI 23 of present embodiment, the output of delay circuit D M-5 , which is four delay stages prior to the final delay stage, delay circuit D M-1 , is output as the first output signal via delay circuits DJ 01  and DJ 02 . Accordingly, from input port DI up to delayed signal output port DO, the number of delay stages is given by M-2. 
     Furthermore, when two or more of the conventional signal processing LSI integrated circuits LSI 11 are cascade connected together as shown in FIG. 4, they are connected in such a way that the calculation result output port SO of one circuit is connected to the calculation result input port SI of the following circuit in the cascade, if it exists. In the case of signal processing LSI integrated circuits LSI 21, LSI 22 and LSI 23 of present embodiment as shown in FIG. 1, they are connected in such a way that the calculation result output port SO of one circuit is connected to the calculation result input port SI of the preceding circuit in the cascade, if it exists. 
     With signal processing LSI integrated circuit LSI 21 of present embodiment, a signal input at calculation result input port SI is delayed by a single sample interval τ in delay circuit DK 01 , after which it is supplied to adder A 31 . Also supplied to adder A 31  is the output of adder A 21  which is the sum of the results of multiplying the output of each delay circuit D 0 , D 1  , . . . D M-1  by a respective multiplication coefficient in multiplication circuits M 0 , M 1  , . . . M M-1 . Thus, adder A 31  calculates the sum of the outputs of each delay circuit D 0 , D 1  , . . . D M-1  after multiplication of each by a respective multiplication coefficient and the input signal from calculation result input port SI delayed by a sample interval τ. The result of the addition operation in adder A 31  is then supplied to calculation result output port SO via delay circuit DK 02 . The internal structure of signal processing LSI integrated circuits LSI 22 and 23 is identical. 
     In the following, with reference to the time chart of FIG. 2, the operation of cascade connected signal processing LSI integrated circuits LSI 21, LSI 22 and LSI 23 of present embodiment as shown in FIG. 1 will be described. When a sample signal X n  is supplied to input port DI (node N 0 ) of signal processing LSI integrated circuit LSI 21 at time t 0 , the signal at delayed signal port DO (node 1) at time t 0  is sample signal X n-M+2  which was input at input port DI (node N 0 ) at a point in time (M-2)τ earlier than time t 0 . In the same way, because the sample signals output from signal processing LSI integrated circuits LSI 22 and LSI 23 at their respective delayed signal output ports DO (nodes N 2  and N 3  respectively) have traversed M-2 delay circuits in each of these integrated circuits, at time t 0 , the signal at node N 2  is sample signal X n-2M+4 , and that at node N 3  is sample signal X n-3M+6 . 
     At time t 0 , sample signals X n-1 , x n-2  , . . . X n-M  are output from delay circuits D 0 , D 1 , . . . D M-1 , respectively, and their sum is determined in adder A 21 . Accordingly, at time t 0 , the signal value at node N 1b  is given by Equ. 6 below: ##EQU6## In signal processing LSI integrated circuit LSI 22, the signal output from input port DI (node N 1 ) is successively delayed in each delay circuit D M , D M+1  , . . . D 2M-1  by one sample interval τ each. At any give time, the output from any delay circuit D M , D M+1  , . . . D 2M-1  is equivalent to the input to the same delay circuit one sample interval τ earlier. Thus, because the input to signal processing LSI integrated circuit LSI 22 at time t 0  is sample signal X n-M+2 , the output from delay circuits D M , D M+1  , . . . D 2M-1  are sample signals X n-M+1 , X n-M  , . . . X n-2M+2 , respectively, at time t 0 . Therefore, the value of the signal present at node N 2b  at time t 0  as calculated in adder A 22  is given by Equ. 7 below: ##EQU7## By the same reasoning, in signal processing LSI integrated circuit LSI 23, the signal output from delay circuits D 2M , D 2M+1  , . . . D 3M-1  are sample signals X n-M+1 , X n-M  , . . . X n-2M+2 , respectively, at time t 0 . Therefore, the result of the convolution calculation at time t 0  as calculated in adder A 23  is given by Equ. 8 below: ##EQU8## 
     In the present embodiment, no signal is input at calculation result input port SI of signal processing LSI integrated circuit LSI 23. For that reason, the output from calculation result output port SO of signal processing LSI integrated circuit LSI 23 is equivalent to the result of the convolution calculation shown in Equ. 8 above delayed by one sampling interval τ in delay circuit DK 01 . It can therefore be seen that at time t 0 , the value of the signal at node N 5  which is supplied to calculation result input port SI of signal processing LSI integrated circuit LSI 22 is given by Equ. 9 below: ##EQU9## The convolution calculation obtained in Equ. 9 above which is supplied to calculation result input port SI of signal processing LSI integrated circuit LSI 22 is further delayed by one sampling interval τ in delay circuit DK 11 , after which it is supplied to adder A 32 . In adder A 32 , the signal is then added to the result of the convolution calculations carried out in signal processing LSI integrated circuit LSI 22 as given by Equ. 7 above. Because of the result of the calculation of Equ. 7 at time t 0  is added in adder A 32  to the signal value that was at node N 5  one sampling interval τ  earlier, the signal calculated in adder A 32  at time t 0  is given by Equ. 10 below: ##EQU10## The result of the above calculation in adder A 32  is output from calculation result output port SO of signal processing LSI integrated circuit LSI 22 after being delayed one sampling interval in delay circuit DK 11 , after which it is supplied to calculation result input port SI of signal processing LSI integrated circuit LSI 21. Thus, at time t 0 , the value of the signal at node N 6  is given by Equ. 11 below: ##EQU11## The signal given by Equ. 11 above which is supplied to calculation result input port SI of signal processing LSI integrated circuit LSI 21 is further delayed by one sampling interval τ in delay circuit DK 01 , after which it is supplied to adder A 31 . In adder A 31 , the signal is then added to the result of the convolution calculations carried out in signal processing LSI integrated circuit LSI 21 as given by Equ. 6 above. The result of this addition operation is then output from calculation result output port SO after being further delayed by one sampling interval τ in delay circuit DK 02 . Thus, the value of the signal at node N 7  at time t 0  is given by Equ. 12 below: ##EQU12## 
     As can be seen in FIG. 2, from time t 0  to time t 2  at which time two sampling intervals τ have passed, results of convolution calculations involving sample signals X n , X n+1  , . . . X n-3M+1  are output. The convolution calculation circuit of the present embodiment is in no way limited to the arrangement shown in FIG. 1 in which three signal processing LSI integrated circuits are cascade connected together. Regardless of the total number of cascaded circuits, it is possible to limit the required time from when a sample is input to when the result of the convolution calculations are output to two sampling intervals τ. The time interval of two sampling intervals τ is based on the amount of time lost in delay elements in signal processing LSI integrated circuits LSI 21, LSI 22 and LSI 23 which are not directly involved with convolution calculations. With the conventional convolution calculation circuit shown in FIG. 4, the time delay for the circuit as a whole is equal to the sum of the time lost in delay elements in each of signal processing LSI integrated circuits LSI 11, LSI 12 and LSI 13 which are not directly involved with convolution calculations. In contrast, with the convolution calculation circuit of the present invention shown in FIG. 1, the time delay for the circuit as a whole is limited only to time lost in delay elements in signal processing LSI integrated circuit LSI 21 which are not directly involved with convolution calculations. The reason for this will be described below. 
     When a sample signal is input at input port DI of signal processing LSI integrated circuit LSI 21, that signal is delayed only by an interval given by (M-2)τ before it is supplied to signal processing LSI integrated circuit LSI 22. Further, after only a time interval given by 2(M-2)τ has elapsed since the time of input, the signal is supplied to signal processing LSI integrated circuit LSI 23. In the case when four or more signal processing LSI integrated circuits are cascade connected together, the elapsed time from the time of input until when the input signal reaches the L th  signal processing LSI integrated circuit is given by (L-1)(M-2)τ. Furthermore, the results of convolution calculations in signal processing LSI integrated circuit LSI 21 are delayed only by a single sampling interval τ (corresponding to the delay in delay circuit DK 01 ) before they are output at node N 7 . The results of convolution calculations in signal processing LSI integrated circuit LSI 22 are delayed only by three sampling intervals τ (corresponding to the delay in delay circuits DK 01  and DK 02  and internal delay in signal processing LSI integrated circuit LSI 22) before they are output at node N 7 , and the results of convolution calculations in signal processing LSI integrated circuit LSI 23 are delayed only by a five sampling intervals τ before they are output at node N 7 . When L signal processing LSI integrated circuits are cascade connected together, a time interval given by (2L-1)τ is required for convolution calculations in the L th  signal processing LSI integrated circuit to be output at node N 7 . 
     For a convolution calculation circuit of the present embodiment having L signal processing LSI integrated circuits, when the transfer functions for the component signal processing LSI integrated circuits are given by F 1  (z), F 2  (z) , . . . and F L  (z), the transfer function for the path from input port DI of signal processing LSI integrated circuit LSI 21 (node N 0 ) to calculation result output port SO of signal processing LSI integrated circuit LSI 21 (node N.sub.(2L+1)) is given by Equ. 13 below: ##EQU13## In the above Equ. 13, delay elements z -M , z -2M  , . . . z - (L-1)M represent delay elements which are indispensable for convolution calculations. As is clear from Equ. 13, because the total delay from node N 0  to node N.sub.(2L-1) caused by delay elements not directly involved in the convolution calculations is reduced, the factors before and after each F 1  (z), F 2  (z) , . . . F L  (z) tend to cancel one another, leaving only z -1  which represents those delay elements in the first stage which are not directly involved in the convolution calculations. Thus, because the time losses due to delay elements not directly involved in the convolution calculations from the time a sample signal is input up to the time when the convolution calculation results are obtained are independent of the number of cascade connected signal processing LSI integrated circuits, this loss factor is constant.