Abstract:
Systems and methods for switching electronic signals are disclosed. The switching may be performed with a low loss and low peak voltages. The switching scheme is suitable for switching RF signals, for example, and may be used in devices such as wireless systems, terminals, and handsets. One exemplary embodiment is directed to a CMOS-implemented transmit/receive switching system. The system comprises one or more transmit ports, each coupled via a respective transmit path to an input/output port and one or more receive ports, each coupled via a respective receive path to the input/output port. Each receive path comprises a switching circuit comprising a transistor and an inductor in parallel with the transistor. The switching circuit is adapted to at least substantially isolate the respective receive port from the input/output port when the transistor is in an on state and operatively couple the respective receive port to the input/output port when the transistor is an off state.

Description:
RELATED APPLICATIONS 
   This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application Ser. No. 60/866,147, entitled “Electronic Switch Network,” filed on Nov. 16, 2006; U.S. Provisional Application Ser. No. 60/866,144, entitled “Distributed Multi-Stage Amplifier,” filed on Nov. 16, 2006; and U.S. Provisional Application Ser. No. 60/866,139, entitled “Pulse Amplifier,” filed on Nov. 16, 2006. Each of the foregoing applications is hereby incorporated by reference herein in its entirety. 

   FIELD OF INVENTION 
   This invention relates to the field of electronic and RF switching. Applications include, but are not limited to, wireless systems, microwave components, transceivers, CMOS amplifiers, and portable electronics. 
   BACKGROUND OF INVENTION 
   Switches in analog and radiofrequency (RF) applications often must deal with a wide dynamic range of signal strength. Transmitters, in particular, sometimes have to handle very high peak voltages. This can be a problem in the field of switch design, as the signal strength may exceed the voltage breakdown of the device. Another problem is that the control voltages available are much smaller than the signal strength. This makes it difficult to keep the switches in an on or off position. Switches for wireless handsets are a notable example of a system exhibiting these problems. In a GSM handset, for instance, the maximum signal strength may be as high as 35 dBm. Transmission through a 50 Ohm system results in a peak voltage of 17.88 V, while the control voltage and maximum available supply voltage are 2.5 V and 3.5 V, respectively. 
     FIG. 1  demonstrates one of the oldest circuits used to deal with this problem. In this case discrete PIN diodes are used as the switching element. This type of diode exhibits excellent RF characteristics with a large breakdown voltage. Direct current (DC) voltages are used to forward or reverse bias the diodes for a low or high impedance. A quarter wave matching network is required to isolate the off port from the on port. This solution works well in multi-port systems. However, high performance PIN diodes are not easily integrated. Further, a large number of passive elements are required to provide the bias and matching. Another significant problem is the current necessary to forward bias the diodes. This may be acceptable in a simple transmit-receive system, as the design may be configured so that the on diode is only used in the transmit mode. Multi-port systems, however, require current in receive mode as well. 
   Another common solution is shown in  FIG. 2 . In this case, field effect transistors (FETs) are used for the switching elements. Gallium arsenide (GaAs) pseudomorphic high electron mobility transistors (PHEMTs) are most commonly used due to their low loss and high breakdown voltage. However, the breakdown voltage is only about 16 V, which is too low to handle high signal level of a GSM system by itself. Also, a control voltage of 2.5 V will result in the off transistor turning on during the negative swing of the output signal. The solution to these problems is to use multiple FETs in series, as shown in  FIG. 3 . This effectively divides the signal voltage evenly across each transistor. This solution is capable of handling the high signal levels while introducing an acceptable amount of loss. It also has the advantage of a near zero current requirement, may be configured for multiple ports applications, and may be integrated on a single die. A disadvantage is that a large number of control signals are required. The lack of a complementary transistor technology on GaAs means that any logic functions will draw significant amounts of current. A separate CMOS control chip is often used with the GaAs switch die for this reason. Also, the use of an exotic technology means that the switch cannot be integrated with the other functions in the handset. 
   Attempts have been made to use CMOS as a switching technology with limited success. In some cases, a DC converter has been used to overcome the control signal limitations. However, the high loss of the substrate has been unacceptable. Silicon-on-Sapphire (SOS) and other exotic technologies have overcome this problem, but the high cost makes then unsuitable for integration with other functions. 
   SUMMARY OF INVENTION 
   One embodiment of the invention is directed to a switching system operable in a transmit mode and a receive mode. The switching system comprises a transmit port coupled via a transmit path to an input/output port; a receive port coupled via a receive path to the input/output port; and a switching circuit in the receive path. The switching circuit comprises a switch device comprising an input terminal, an output terminal, and a control terminal to receive a control signal that controls a state of the switch device between an on state and an off state. When the switch device is in the on state, the switching system is adapted to operate in a transmit mode in which the transmit port is operatively coupled to the input/output port and the receive port is at least substantially isolated from the input/output port. When the switch device is in the off state, the switching system is adapted to operate in a receive mode in which the receive port is operatively coupled to the input/output port. 
   Another embodiment of the invention is directed to a CMOS-implemented switching system comprising one or more transmit ports, each coupled via a respective transmit path to an input/output port and one or more receive ports, each coupled via a respective receive path to the input/output port. Each receive path comprises a switching circuit comprising a transistor and an inductor in parallel with the transistor. The switching circuit is adapted to at least substantially isolate the respective receive port from the input/output port when the transistor is in an on state and operatively couple the respective receive port to the input/output port when the transistor is an off state. 
   A further embodiment of the invention is directed to transmit/receive device comprising an antenna; a radio-frequency transmitter; a radio-frequency receiver; and a switching system. The switching system comprises a transmit port arranged between the transmitter and the antenna, wherein the transmit port is coupled to the antenna via a transmit path; a receive port arranged between the receiver and the antenna, wherein the receive port is coupled to the antenna via a receive path; and a switching circuit in the receive path. The switching circuit comprises a switch device comprising an input terminal, an output terminal, and a control terminal to receive a control signal that controls a state of the switch device between an on state and an off state. When the switch device is in the on state, the switching system is adapted to operate in a transmit mode in which the transmit port is operatively coupled to the input/output port and the receive port is at least substantially isolated from the input/output port. When the switch device is in the off state, the switching system is adapted to operate in a receive mode in which the receive port is operatively coupled to the input/output port. 
   Another embodiment of the invention is directed to a switching method, comprising an act of using CMOS switching circuitry, switching a transmit/receive device between a transmit mode, in which a transmission signal comprising a transmission carrier signal is transmitted from a transmit port to an input/output port, and a receive mode, in which a reception carrier signal is transmitted from the input/output port to a receive port. When operated in the transmit mode, the CMOS switching circuitry generates no harmonics larger than approximately −60 dB relative to the transmission carrier signal. When operated in the transmit mode, the CMOS switching circuitry imposes a signal loss on the transmission signal that is no greater than about 2.5 dB. 
   A further embodiment of the invention is directed to a switching system, comprising CMOS switching circuitry adapted to switch between a transmit mode, in which a transmission signal comprising a transmission carrier signal is transmitted from a transmit port to an input/output port, and a receive mode, in which a reception carrier signal is transmitted from the input/output port to a receive port. The CMOS switching circuitry is adapted to generate no harmonics larger than approximately −60 dB relative to the transmission carrier signal when operated in the transmit mode. The CMOS switching circuitry is also adapted to impose a signal loss on the transmission signal that is no greater than about 2.5 dB when operated in the transmit mode. 
   Another embodiment of the invention is directed to a switching system operable in a transmit mode and a receive mode. The switching system comprises a plurality of ports comprising at least one transmit port coupled to an input/output port and at least one receive port coupled the input/output port; and switching circuitry adapted to select one of the plurality of ports to be operatively coupled the input/output port, wherein a transmit port is operatively coupled to the input/output port when the switching system is operated a transmit mode, and wherein a receive port is coupled to the input/output port when the switching system is operated in a transmit mode. The switching circuitry comprises at least one transistor, and wherein each transistor of the switching circuitry is in an on state when the switching system is operated in the transmit mode. 
   A further embodiment of the invention is directed to a switching system operable in a first mode and a second mode. The switching system comprises a first port coupled via a first path to an input/output port, wherein the first port passes a first signal; a second port coupled via a second path to the input/output port, wherein the second port passes a second signal having a lower power than the first signal; and a switching circuit in the second path, the switching circuit comprising a switch device comprising an input terminal, an output terminal, and a control terminal to second a control signal that controls a state of the switch device. The switching circuit is adapted to switch the switching system between (1) a first mode in which the voltage across the switch device is substantially zero, the first port is operatively coupled to the input/output port, and the second port is at least substantially isolated from the input/output port, and (2) a second mode in which the second port is operatively coupled to the input/output port. 
   Another embodiment of the invention is directed to a switching system comprising one or more first ports, each coupled via a respective first path to an input/output port, wherein each first port passes a respective first signal; and one or more second ports, each coupled via a respective second path to the input/output port, wherein each second port passes a respective second signal having a lower power than each first signal. Each second path comprises a switching circuit comprising a transistor and a transformer in parallel with the transistor, and the switching circuit is adapted to switch the switching system between (1) a first mode in which the voltage across the transistor is substantially zero, the first port is operatively coupled to the input/output port, and the second port is at least substantially isolated from the input/output port, and (2) a second mode in which the second port is operatively coupled to the input/output port. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  shows a conventional switch implemented using PIN diodes; 
       FIG. 2  shows a first conventional switch implemented FET switches; 
       FIG. 3  shows a second conventional switch implemented FET switches; 
       FIG. 4  shows a first embodiment of a switching system that performs a Single-Pull-Double-Throw (SPDT) function; 
       FIG. 5  shows the circuit of  FIG. 4  with a first example of an output matching network (OMN); 
       FIG. 6  shows the circuit of  FIG. 4  with a second example of an OMN; 
       FIG. 7  shows another embodiment of a switching system; 
       FIG. 8  shows a variation on the circuit of  FIG. 7 ; 
       FIG. 9  shows an embodiment of a switching system usable for multi-port operation; 
       FIG. 10  shows an another embodiment of a switching system usable for multi-port operation; 
       FIG. 11  shows a further embodiment of a switching system usable for multi-port operation; and 
       FIG. 12  shows yet another embodiment of a switching system usable for multi-band, multi-port operation. 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows how PIN diodes have conventionally been used to switch RF signals. A switch  100  comprises a transmit port  104  and a receive port  105 , each coupled to an antenna  106 . The transmit path comprises a capacitor  108  and a diode  101 , an inductor  109  coupled between the capacitor  108  and the diode  101 , and a capacitor  110  coupled between the inductor  109  and ground. A control signal Vc is applied to a node  111  between the inductor  109  and the capacitor. The receive path comprises a quarter wave line  103 , a capacitor  112 , and a diode  102  coupled at one end between the quarter wave line  103  the capacitor  112 . At its other end, the diode  102  is coupled to ground. 
   In transmit mode, the control signal Vc is set high, which forward biases both diodes  101  and  102 . When diode  101  is forward biased, it presents a low impedance path from the transmit port  104  to the receive port  105 . When the diode  102  is forward biased, it presents a near short circuit to the receive port  105 , which helps to isolate it from the high transmit signal levels. The quarter wave line  103  transforms the short circuit impedance at the receive port  105  to a high, new open, impedance at the antenna  106 . When Vc is set low, both diodes  101  and  102  are reversed biased and in a high impedance state. Diode  101  provides a high impedance path and isolates the transmit and antenna ports  104 ,  106 . Diode  102  is also in a high impedance state, which allows signals to flow freely between the receive and antenna ports  105 ,  106 . 
     FIG. 2  shows a common implementation of an Single-Pull-Double-Throw (SPDT) switch  200  implemented using field effect transistors (FETs)  201  and  202 . GaAs PHEMTs are most commonly used for this application. Because these are depletion mode devices, the gate must be biased below the drain and source terminals to turn the transistor off. To accommodate this, the switch is typically DC isolated or “floating” via the use of blocking capacitors  203 ,  204 ,  205  at the respective transmit, receive and antenna ports  206 ,  207 ,  208 . A control signal Vref, which is applied to one end of a resistor  209 , is then set to the highest control voltage. A control signal equal to Vref may thus turn the switch on and a control signal of zero may turn the switch off. When complementary signals are used for control signals Vc 1  and Vc 2 , which are respectively coupled to FETs  202  and  201  via resistors  210  and  211 , FETs  101  and  102  are toggled and the switch moves between transmit mode and receive mode. 
     FIG. 3  shows a switch  300  similar to the SPDT switch of  FIG. 2 , wherein FETs  201  and  202  have each been replaced with three series FETs  201   a - c  and  202   a - c . The control signals Vc 2  and Vc 1  are used to control the respective chains of FETs  201  and  202 . The advantage of this technique is that the voltage is divided across the off chain, avoiding breakdown. 
   Single-Pole-Multi-Throw switch topologies share a common problem for transmit/receive systems. This is partly due to the reciprocal nature of the design. During transmit, one branch of the switch is on while multiple receive branches are turned off. The switch should have low loss in the transmit branch while providing adequate isolation to the receive ports to protect the low noise amplifiers (LNAs) coupled to them. However, the opposite case is not true. In receive mode, the loss is important, but the isolation from the transmit port is only important insofar as it impacts the loss. The receive signal strength will not cause any damage to the power amplifier coupled to the transmit port. Single-Pole-Multi-Throw switch topologies tend to provide similar isolation for both cases. Certain exemplary embodiments disclosed herein may make use of these uneven or non-reciprocal requirements. 
   Another aspect of switches for transmit/receive systems is that the most distortion and potential damage to the devices occurs because a switching transistor is held in the off position, with a high impedance, while the switch is handling the highest signal levels. When the transistors are in a high impedance state, all of the signal potential may be present across the terminals of the device. This increases the risk of entering the transistor breakdown region. The existence of both a positive and negative voltage swing makes it difficult to keep the transistor fully off, causing some channel modulation and signal distortion. Such high voltage potentials, with risk of breakdown and control problems, are usually not be present in the devices in the on position. These devices may be in a low impedance state. Instead they may have to pass large currents. If the devices are scaled so as to operate in the linear region, the voltage potential can remain low, avoiding breakdown and signal distortion, and the devices may remain in the on state. In certain exemplary embodiments disclosed herein, a switch may be configured so that all transistors remain in an on state during transmit mode. 
     FIG. 4  shows one embodiment of a switching system that makes use of the aforementioned uneven or non-reciprocal requirements, and which may be configured such that all transistors remain in an on state during transmit mode. Transmit/Receive switching system  400  comprises a transmit path including a transmit port  408 , which is coupled via a power amplifier  401  and an impedance matching network  403 , to an output port  409 . The output port  409  is coupled to load impedance  404 . The switching system  400  also comprises a receive path. In the receive path, a receive impedance  407 , switching transistor  406  and transformer  405  are coupled in parallel with each other and between a receive port  410  and the impedance matching network  403 . An inductor  402 , coupled between the power amplifier  401  and the impedance matching network  403  is used to bias the power amplifier  401 . Transformer  405  is coupled to a shunt element of the impedance matching network  403 . The shunt element may have a wide variety of configurations, including one or more resistors, capacitors, and inductors, alone or in combination. In this embodiment, the shunt element may be advantageously selected to be the element that would be used in a transmitter without the receiving path, and coupled from the impedance matching network to ground, so as to provide the correct matching impedance to the power amplifier. 
   In transmit mode, the power amplifier  401  may be turned on, and amplifies a signal Vin to a level Vd. Signal Vd then propagates through the matching network  403 . Switching device  406  is turned on and provides a low impedance from the receive port to ground. This may effectively short out the two primary terminals of the transformer  405 . The transformer may map the impedance seen at the primary winding to the secondary winding by the equation Zs=n*Zp. When the primary impedance approaches a short circuit, the secondary impedance may also approach a short circuit. This may effectively couple the shunt element in the impedance matching network to ground. The shunt element may then have the proper impedance to match the power amplifier  401  to the load impedance  404 . For example, the shunt element may be designed such that when coupled to ground as previously described, the shunt element has an impedance to suitable to match the power amplifier  401  to the load impedance  404 . The low impedance of the switch may provide isolation for the receive impedance. When sized correctly, the switch may provide adequate isolation and have a low potential voltage across its terminals. Circulating currents may be present in the transformer, and the switch device may be sized to pass these currents without distortion. 
   In receive mode, the power amplifier  401  may be turned off, and presents a known impedance to the matching network  403 . Depending on the design of the power amplifier  401 , this might be an open circuit, short circuit, or reactive impedance. Switch  406  may be turned off and the load impedance  404  may be coupled to the receive impedance  407  through the transformer  405  and output matching network  403 . The output impedance of the power amplifier may effect the connection of the receive port to the output load. Because the isolation between the output load and the power amplifier is usually not a concern, the impedance matching network may be designed to accommodate the off-state power amplifier impedance. An optimum design may be created that provides a good match with low loss between the output and receive ports  409 ,  410 . Other matching elements might also be used at the receive port to improve the receive match, loss, and bandwidth. 
     FIG. 5  shows a more detailed embodiment of the switching system of  FIG. 4 . In particular, an exemplary implementation of the impedance matching network  403  of  FIG. 4  is shown. Impedance matching network  503  comprises a first shunt capacitor  508 , a series inductor  509 , a second shunt capacitor  510 , and a series blocking capacitor  511 . The shunt capacitor  510  is coupled to the secondary winding of the transformer  505 . When the switch is turned on, the capacitor  510  is effectively coupled to ground and the power amplifier  401  is able to operate with the proper impedance. The receive port  410  may be isolated by the low impedance of the switch and only low signal potentials may be present at the switch terminals. In receive mode, the power amplifier  401  may be turned off and present an impedance characterized by a high real part in parallel with a shunt capacitance. The output capacitance of the device combined with the shunt capacitor  508  may resonate with the bias inductor  402 . The value of the inductor  402  may be chosen so that the reactances cancel and a high impedance is presented at the series inductor  509 . The receive port  410  may then be coupled directly through the transformer  405 , the shunt capacitance  510  and the blocking capacitor  511 . The leakage inductance of the transformer may be designed to cancel the series reactance of the capacitor  510 , leaving a low impedance path between the receive port and the output load. 
     FIG. 6  shows the switching system of  FIG. 4  with another exemplary implementation of the impedance matching network  403  of  FIG. 4 . In this embodiment, the impedance matching network  603  comprises a shunt capacitor  608 , a series capacitor  609 , and a shunt capacitor  610 . The operation in transmit mode is similar to the circuit in  FIG. 5 , with the receive network coupling the inductor  610  to ground for proper matching. In receive mode, the power amplifier may be put into a low impedance state. This may happen in some power amplifier circuits. A secondary matching network, for example, might transform the naturally high state of the amplifier devices to a low impedance at the output. In this state, capacitor  608  and inductor  602  are effectively removed from the circuit, and one side of the series capacitor  609  sees a short. Capacitor  609  then serves as a shunt capacitance in parallel with the inductor  610 , the leakage inductance of the transformer and the receive load. This capacitance may be used to tune the receive branch for optimum performance. 
     FIG. 7  shows another exemplary embodiment of a switching system. In the switching system  700 , the matching network  703  may represent either the low-pass network of  FIG. 5  or the high-pass network of  FIG. 6 . Shunt matching inductor  704  has been left out of the matching block to illustrate the operation of the switch. As shown, the transformer has been realized using coupled inductors  705   a  and  705   b . These may be characterized by a self inductance for each coil and a mutual inductance. Those familiar in the art will be able to translate this real structure with a transformer network characterized by a number of turns and a leakage inductance. The coupled coils may be realized by parallel windings around a core, spiral inductors printed on a board or substrate, or coupled transmission lines. The capacitors  706  and  707  may be used to resonate with the leakage inductance and improve the loss of the transformer. Receive impedance  407  and switch device  406  may operate in a manner similar to the corresponding devices in the circuit in  FIG. 6 . 
     FIG. 8  shows a switching system  800  that is similar to the switching system  700  of  FIG. 7 , but replaces the capacitor  707  with a more complex and arbitrary impedance matching network  807 . This provides more flexibility to resonate with the leakage inductance, and at the same time provide a proper match to the load impedance R RX ,  407 . Impedance matching network  807  may be comprised of shunt and series capacitors and inductors. 
   The circuit of  FIG. 9  shows an embodiment that provides for two receive ports. This effectively creates a Single-Throw-Triple-Pull (SP 3 T) switch. Similar to other switching systems described herein, the switching system  900  comprises a power amplifier  401  coupled between a transmit port  408  and a bias inductor  402 . The bias inductor  402  is coupled to an impedance matching network  703 , which is in turn coupled to an output load  404  at an output port  409 . The impedance matching network  703  is coupled via an inductor  904  to first and second transformers  905 ,  910  (or first and second coupled inductor pairs  905   a,b  and  910   b,c ) corresponding to first and second receive ports  913 ,  914 . Inductor  905   b  is coupled in parallel with receive load  908  and switch device  909 , while inductor  910   b  is coupled in parallel with a second receive load  911  and switch device  912 . During transmit, both switches  909 ,  912  are on and the inductors  905   b  and  910   b  are effectively short circuited. During receive mode, one of the switches may remain closed to maintain the associated inductor as an effective short circuit, while the other switch is open. This provides selectivity between two or more ports while keeping the same advantages during the transmit mode. This technique may be extended to an arbitrary number of receive ports with the penalty of additional leakage inductance and loss due to the circulating currents. Other techniques and embodiments will be apparent to those skilled in the art. 
     FIG. 10  shows an alternate embodiment of the multi-port switch of  FIG. 9 . In particular, switching system  1000  omits transformer  910  (or coupled inductors  910   a ,  910   b ), such that switch  1011  is in the ground path for transformer  905  (or coupled inductors  905   a ,  905   b ). In this case, the switch  1011  may be used to provide a real short circuit to one end of inductor  905   a , rather than the virtual short circuit provided by the transformer  910  (or coupled inductors  910   a ,  910   b ) of  FIG. 9 . Those skilled in the art will recognize that a variety of matching elements may be added to improve performance. 
     FIG. 11  shows a variation on the switching system of  FIG. 9  wherein the amplifier  901  and matching network  903  have been realized using a pair of amplifiers  901   a ,  901   b  matched using coupled inductors or transformers  1103   a ,  1103   b . Amplifiers  901   a  and  901   b  are associated with respective first and second transmit ports  908   a  and  908   b . Amplifier pair  901   a  and  901   b  may be configured differentially or in phase, and be of equal or substantially different sizes. More than two amplifiers may also be combined in this manner. Coupled inductors, or transformers,  1103   a  and  1103   b  may also be constructed in a similar manner to the coupled inductors or transformers of  1105  and  1110 . A transformer implementation of  1103   a  and  1103   b  may use a turns ratio of 1: 1, as drawn, or virtually any other turns ratio. 
     FIG. 12  shows an exemplary embodiment of the invention wherein the amplifier is made up of many small components, each combined via a coupled inductor transformer network. For example, amplifiers  1201  and  1202  may represent separate amplifiers covering different frequency ranges. Receive switch sections  1203  and  1204  function in a similar manner to the circuit of  FIG. 9 , in this case allowing for selection between four receivers Rx  1 , Rx  2 , Rx  3 , Rx  4 . In this embodiment, switch sections  1203  and  1204  may be designed to work with separate amplifiers and cover different frequency ranges. Additional transmit or receive paths can be added as desired according to any of the previously described embodiments. In addition, any number of the receive switches can be fabricated using complementary metal oxide semiconductor (CMOS) technology. More variations on this theme will be evident to one skilled in the art. 
   The circuits of the switching systems described herein may be implemented using, for example, silicon bipolar transistors, CMOS transistors, Gallium arsenide (GaAs), metal semiconductor field effect transistors (MESFETs), GaAs heterojunction bipolar transistors (HBTs), and/or GaAs pseudomorphic high electron mobility transistors (PHEMTs). The circuits may also be compatible with the various integrated circuit (IC) technologies associated with the above technologies, and can yield a monolithic solution. 
   One exemplary application of the switching systems described herein is a transmit/receive switch. In the methods and systems described herein, the switch may generate no harmonics larger than approximately −60 dB (or −70 dB, according to another example) relative to the transmission carrier signal when the switching system is operated in a transmit mode. In addition, in the methods and systems described herein, the switch may impose a signal loss on the transmission signal that is no greater than approximately 2.5 dB (or 1.5 dB, according to another example). Thus, the transmit/receive switch may advantageously operate with reduced loss and distortion. It should be appreciated that while a transmit/receive switch is one beneficial application of the switching systems described herein, the invention is not so limited. 
   Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.