Abstract:
A voltage regulator circuit for providing power management for a memory device is disclosed. The voltage regulator circuit comprises a voltage regulator and a switch circuit. The switch circuit includes a first oscillator to generate an oscillating signal, and a pulse generator to generate a pulse signal in response to the oscillating signal. The voltage regulator provides a current during standby mode of the memory device in response to the pulse signal. The current is smaller than one provided by the voltage regulator during normal mode of the memory device.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The current disclosure relates to power management for a memory device and, in particular, to a voltage regulator circuit that supports power management for a memory device. 
     2. Description of the Related Art 
     Voltage regulators are used to regulate a voltage level and supply internal power. A memory device, such as a dynamic random access memory (DRAM), may operate in normal mode or active mode, during which mode a reading or writing operation may be performed. Voltage regulators may be used to provide a relatively large current for the reading or writing operation. On the other hand, the memory device may operate in standby mode, during which mode a refresh operation may be performed. However, in the standby mode, only a small current is required to maintain data in the memory device. 
     It may therefore be desirable to have a voltage regulator circuit that provides a relatively large current during normal mode of a memory device, and provides a relatively small current during standby mode of the memory device. 
     SUMMARY OF THE INVENTION 
     Embodiments of the present invention provide a voltage regulator circuit for providing power management for a memory device. The voltage regulator circuit comprises a voltage divider, a voltage regulator and a switch circuit. The voltage regulator includes an output coupled to the voltage divider and regulates a voltage level at the output. The switch circuit includes a first oscillator to generate an oscillating signal, and a pulse generator to generate a pulse signal in response to the oscillating signal. The voltage regulator provides a current during standby mode of the memory device in response to the pulse signal. The current is smaller than one provided by the voltage regulator during normal mode of the memory device. 
     Some embodiments of the present invention also provide a voltage regulator circuit for providing power management for a memory device. The voltage regulator circuit comprises a voltage regulator and a switch circuit. The switch circuit includes a first oscillator to generate an oscillating signal, and a pulse generator to generate a pulse signal in response to the oscillating signal. The voltage regulator provides a current during standby mode of the memory device in response to the pulse signal. The current is smaller than one provided by the voltage regulator during normal mode of the memory device. 
     In order to have further understanding of the techniques, means, and effects of the current disclosure, the following detailed description and drawings are hereby presented, such that the purposes, features and aspects of the current disclosure may be thoroughly and concretely appreciated; however, the drawings are provided solely for reference and illustration, without any intention to be used for limiting the current disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The objectives and advantages of the present invention are illustrated with the following description and upon reference to the accompanying drawings in which: 
         FIG. 1  is a schematic block diagram of a voltage regulator circuit in accordance with an embodiment of the present invention; 
         FIG. 2  is a schematic block diagram of a voltage regulator circuit in accordance with another embodiment of the present invention; 
         FIG. 3  is a timing diagram illustrating an oscillating signal and a pulse signal generated in accordance with an embodiment of the present invention; and 
         FIG. 4  is a timing diagram illustrating an oscillating signal and a pulse signal generated in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention discloses a voltage regulator circuit for a memory device. 
       FIG. 1  is a schematic block diagram of a voltage regulator circuit  10  in accordance with an embodiment of the present invention. Referring to  FIG. 1 , the voltage regulator circuit  10  may include a voltage divider  11 , a capacitor  13 , an active-mode voltage regulator  15  and a switch circuit  17 . 
     The voltage divider  11  includes resistors R 1  and R 2  connected in series. 
     The active-mode voltage regulator  15 , coupled between the voltage divider  11  and the capacitor  13 , includes an operational amplifier  150  and a transistor  151 . The operational amplifier  150 , which may serve as a comparator, includes a non-inverting terminal coupled to a point between the resistors R1 and R2, and an inverting terminal coupled to a reference voltage Vref. The transistor  151 , in the present embodiment a p-type MOS (PMOS) transistor, includes a gate terminal  7  coupled to an output (not numbered) of the operational amplifier  150 , a source terminal  8  coupled to a voltage source VDD, and a drain terminal  9  coupled to the capacitor  13 . A voltage level “VPS” at the drain terminal is fed back to the voltage divider  11 , specifically, one end of the resistor R1. Moreover, the capacitor  13  may function to stabilize the voltage level VPS. 
     The switch circuit  17  may include a first oscillator  177 , a pulse generator  175 , a first transistor  173  and a second transistor  171 . The first transistor  173  includes a gate terminal  1  coupled to the pulse generator  175 , a drain terminal  2  coupled to the operational amplifier  150 , and a source terminal  3  coupled to ground. Moreover, the second transistor  171  includes a gate terminal  4  coupled to the pulse generator  175 , a drain terminal  5  coupled to the voltage divider  11 , and a source terminal  6  coupled to ground. Persons having ordinary skill in the art will understand that a source terminal and a drain terminal may be interchangeable, depending on the voltage levels applied thereto. 
     The first oscillator  177  may be configured to generate an oscillating signal. In response to the oscillating signal, the pulse generator  175  generates a pulse signal. The oscillating signal has a period greater than the pulse width of the pulse signal. In one embodiment according to the present invention, during normal mode of a memory device associated with the voltage regulator circuit  10 , the pulse signal may be bypassed or ignored and the first and second transistors  173  and  171  are turned on by, for example, an additional high-level signal. Furthermore, during standby mode of the memory device, the pulse signal is sent to the first and second transistors  173  and  171 , which turns on the transistors  173  and  171 . 
     In operation, during normal mode, the additional signal turns on the transistors  173  and  171 . Accordingly, when the voltage level VPS rises above a predetermined level, the operational amplifier  150  outputs a high-level signal, which turns off the PMOS transistor  151 , allowing VPS to fall from above the predetermined level. On the other hand, when the voltage level VPS falls below the predetermined level, the operational amplifier  150  outputs a low-level signal, which turns on the PMOS transistor  151 , allowing VPS to rise from below the predetermined level. The transistors  173  and  171  are kept at an “on” state during the normal mode so that a relatively large current may be provided to the memory device. 
     During standby mode, the pulse signal from the pulse generator  175  turns on the transistors  173  and  171 . The transistors  173  and  171  are kept at an “on” state for the pulse width of the pulse signal, and are turned off after the pulse width. In one embodiment, the pulse signal is generated at a rising edge of the oscillating signal. As a result, the transistors  173  and  171  are not turned on until a next pulse signal is generated. Accordingly, during the standby mode, only a relatively small current may be provided to the memory device. 
       FIG. 2  is a schematic block diagram of a voltage regulator circuit  20  in accordance with another embodiment of the present invention. Referring to  FIG. 2 , the voltage regulator circuit  20  is similar to the voltage regulator circuit  10  illustrated in  FIG. 1  except that, for example, an active-mode voltage regulator  25  replaces the active-mode voltage regulator  15  in  FIG. 1 . Specifically, the active-mode voltage regulator  25  may include an operational amplifier  250 , a second oscillator  251  and a charge pump  253 . The operational amplifier  250 , which may serve as a comparator, includes an inverting terminal coupled to a point between the resistors R 1  and R 2 , and a non-inverting terminal coupled to a reference voltage V ref . The second oscillator  251  is coupled between an output (not numbered) of the operational amplifier  250  and the charge pump  253 . 
     In operation, during normal mode of a memory device associated with the voltage regulator circuit  20 , the additional signal turns on the transistors  173  and  171 . Accordingly, when the voltage level VPS rises above a predetermined level, the operational amplifier  250  outputs a low-level signal, which turns off the second oscillator  251  and in turn the charge pump  253 , allowing VPS to fall from above the predetermined level. On the other hand, when the voltage level VPS falls below the predetermined level, the operational amplifier  250  outputs a high-level signal, which turns on the second oscillator  251  and in turn the charge pump  253 , allowing VPS to rise from below the predetermined level. The transistors  173  and  171  are kept at an “on” state during the normal mode so that a relatively large current may be provided to the memory device associated with the voltage regulator circuit  20 . 
     During standby mode, the pulse signal from the pulse generator  175  turns on the transistors  173  and  171 . The transistors  173  and  171  are kept at an “on” state for the pulse width of the pulse signal, and are turned off after the pulse width. Accordingly, during the standby mode, only a relatively small current may be provided to the memory device. 
       FIG. 3  is a timing diagram illustrating an oscillator signal Osc_ 1  and a pulse signal P 1  generated in accordance with an embodiment of the present invention. Referring to  FIG. 3 , the pulse signal P 1  may be generated at a rising edge of the oscillating signal Osc_ 1 . Furthermore, the pulse signal P 1  may have a pulse width of approximately 1 microsecond (μs) and the oscillating signal Osc_ 1  may have a period of approximately 10 μs. 
       FIG. 4  is a timing diagram illustrating the oscillating signal Osc_ 1  and a pulse signal P 2  generated in accordance with another embodiment of the present invention. Referring to  FIG. 4 , the pulse signal P 2  is similar to the pulse signal P 1  shown in  FIG. 3  except that, for example, the pulse signal P 2  is generated at a falling edge of the oscillating signal Osc_ 1 . 
     Although the present invention and its objectives have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented using different methodologies, replaced by other processes, or a combination thereof. 
     Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.