Abstract:
An apparatus having a plurality of insulating layers, a plurality of conductive layers and a plating is disclosed. The conductive layers may be separated by the insulating layers. A first pattern in a first of the conductive layers generally extends to an edge castellation. A second pattern in a second of the conductive layers may also extends to the edge castellation. The plating may be disposed in the edge castellation and connect the first pattern to the second pattern. The plating in the castellation may extend at most between a subset of the conductive layers.

Description:
FIELD OF THE INVENTION 
     The present invention relates to multilevel circuits generally and, more particularly, to a method and/or apparatus for implementing a blind via edge castellation. 
     BACKGROUND OF THE INVENTION 
     Conventional land grid array packages often have blind solder joints. Such solder joints cannot be visually inspected and so present a problem. Conventional edge castellations overcome the visual inspection problem by running platings in vias on an outside edge of the package. The solder joints made to the platings are visible. For high-frequency signals used in radio frequency circuits, the edge castellations act like transmission line stubs. Some edge castellations add such sufficient loss to the high-frequency signals that the edge castellations cannot be implemented. 
     It would be desirable to implement a blind via edge castellation. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus having a plurality of insulating layers, a plurality of conductive layers and a plating. The conductive layers may be separated by the insulating layers. A first pattern in a first of the conductive layers generally extends to an edge castellation. A second pattern in a second of the conductive layers may also extend to the edge castellation. The plating may be disposed in the edge castellation and connect the first pattern to the second pattern. The plating in the castellation may extend at most between a subset of the conductive layers. 
     The objects, features and advantages of the present invention include providing a blind via edge castellation that may (i) support a visually inspectible solder joint, (ii) reduce performance degradation, (iii) accommodate high frequency signals, (iv) extend only one or a few layers along an edge of a board and/or (v) be implemented in a land grid array board or substrate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a diagram of an example implementation of a device; 
         FIG. 2  is a flow diagram of a method for fabricating a board assembly; 
         FIG. 3  is a cutaway perspective diagram of a portion of a board in accordance with a preferred embodiment of the present invention; 
         FIG. 4  is a cutaway perspective diagram of an example embodiment of the board, 
         FIG. 5  is a cutaway perspective diagram of another example embodiment of the board; and 
         FIG. 6  is a perspective diagram of the board showing a bottom surface. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     various embodiments of the invention generally implement one or more blind edge castellations. The blind edge castellations may extend only one or a few conductive layers up from a bottom of a board. Limiting the height of the blind edge castellations generally reduces parasitics that degrade high-frequency signals conveyed by the blind edge castellations. The blind edge castellations may also permit visual inspection of solder joints created between platings in the blind edge castellations and traces on a mother board. 
     Referring to  FIG. 1 , a diagram of an example implementation of a device  90  is shown. The device (or circuit or component)  90  may implement a packaged radio frequency circuit mounted on a mother board. The device  90  generally comprises a board assembly (or substrate or apparatus)  91  and a mother board (or circuit board)  92 . The mother board  92  generally comprises multiple traces (or wires)  94   a - 94   c  on a top surface. The board assembly  91  generally comprises a board  100 , a heat sink  102  and one or more circuits (or chips or dice)  104 . The circuits  104  are generally mounted on a bottom of the board  100 . A bottom (or solder side or component side) surface  106  of the board  100  may adjoin (or contact) the top surface of the mother board  92 . The heat sink  102  may be mounted to a top surface  108  of the board  100 . Multiple plated edge castellations  110 - 114  may be formed in one or more side edges of the board  100 . 
     Each trace  94   a - 94   c  may be aligned to a respective edge castellation  110 - 114 . Solder between the traces  94   a - 94   c  and the bottom conductive layer of the board  100  generally flows into the edge castellations  110 - 114  during fabrication to provide visually inspectible electrical connections (e.g., solder joints) between the mother board  92  and the board  100 . 
     In some embodiments, the board  100  may be a printed circuit board with a land grid array. In other embodiments, the board  100  may be a multilayer ceramic board. The board  100  generally comprises multiple (e.g., three or more) layers of patterned conductors separated by multiple insulating layers. Some of the patterns in the various conductive layers may be interconnected by vias. An outermost (e.g., bottom) conductive layer may include bonding pads to electrically connect to the circuits  104 . The outermost conductive layer may also include solder areas used to solder the board  100  to the mother board  92 . 
     The heat sink  102  may be operational to efficiently transfer heat generated by the circuits  104  into the surrounding atmosphere. The heat sink  102  may be finned or un-finned. 
     The circuits  104  generally comprise radio frequency circuits, passive components and digital drivers. The circuits  104  are operational to transmit and/or receive one or more high-frequency signals and one or more low-frequency signals to and from the mother board  92 . The circuit  104  may also receive one or more power signals and one or more ground signals from the mother board  92 . A high-frequency signal may be carried between the mother board  92  and the board  100  via the edge castellation  112 . The low-frequency signals, power and ground may be transferred via the edge castellations  110  and  114 . 
     The high-frequency signals generally comprise signals having a frequency above approximately 1 gigahertz (e.g., GHz). The high-frequency signals may be routed through the short edge castellation  112  instead of the long edge castellations  110  and  114  to avoid attenuations due to the open-circuited transmission line stub characteristics that may be present in the long edge castellations  110  and/or  114 . 
     The low-frequency signals generally comprise signals having a frequency below approximately 500 megahertz (e.g., MHz). The low-frequency signals may be conveyed through the edge castellations  110  and/or  114  because the attenuations, if any, are not a factor in a performance of the circuit  104 . Signals having intermediate frequencies are generally routed on edge castellations  110 ,  112  or  114  depending on the nature of the signal and a susceptibility to the stub-like characteristics of the edge castellations  110  and  114 . 
     Referring to  FIG. 2 , a flow diagram of an example implementation of a method  120  for fabricating the board assembly  91  is shown. The method (or process)  120  generally comprises a step (or state)  122 , a step (or state)  124 , a step (or state)  126 , a step (or state)  128 , a step (or state)  130 , a step (or state)  132 , a step (or state)  134 , a step (or state)  136  and a step (or state)  138 . The method  120  may be performed in a normal circuit board fabrication facility using normal fabrication techniques. 
     In the step  122 , a lower portion of a package substrate (or multilayer ceramic substrate) may be created by laminating (or layering or depositing) a single or multiple insulating layers and multiple conductive layers. Each conductive layer is generally patterned before being covered by a subsequent insulating layer. The layering sequence generally begins at a bottom surface of the package substrate (e.g., what will become the bottom surface  106  of the board  100 ) with a bottom conductive layer (e.g., layer  1 ) and progresses upward. 
     After two or more of the conductive layers have been assembled, holes (or vias) for the short edge castellations (e.g.,  112 ) may be drilled in the partially-fabricated package substrate in the step  124 . The holes may be referred to as short holes. The short holes may be plated in the step  126  with a conductive material. The conductive material electrically connects to each pattern of each conductive layer intersected by the short holes. In the step  128 , the laminating of more insulating layers and more conductive layers may continue until the top surface of the package substrate (e.g., what will become the top surface  108  of the board  100 ) has been added. After each conductive layer is added, the conductive layer is patterned. 
     In the step  130 , more holes (or vias) are created in the package substrate. The holes created in the step  130  generally pass through all of the conductive layers and all of the insulating layers of the package substrate and so may be referred to as long holes. Plating of the long holes with the conductive material may be performed in the step  132 . The conductive material electrically connects to each pattern of each conductive layer intersected by the long holes. The connections may include one or more of the conductive layers. In contrast, the plating in the short holes is limited to one or more of the lower conductive layers that were present when the short holes were formed. In some embodiments, both the short holes and the long holes may be plated at the same time if the plating technique being used can deposit into the close-ended short holes. 
     In the step  134 , the package substrate may be cut into individual boards. The circuits  104  are generally mounted into the boards in the step  136  and electrically connected to bonding pads formed in one or more of the conductive layers (e.g., wire bonds, soldering, tab bonds, ball grid arrays, or the like). After the circuits  104  have been sealed, the heat sink  102  may be added in the step  138  to create the board assembly  91 . 
     Referring to  FIG. 3 , a cutaway perspective diagram of an example embodiment of a portion of the board  100  is shown in accordance with a preferred embodiment of the present invention. An orientation of the board  100  shown in  FIG. 3  is flipped 180 degrees from the orientation shown in  FIG. 1 . The portion is focused on the short edge castellation  112 . The board  100  generally comprises multiple conductive layers  150   a - 150   f . In some embodiments, all of the conductive layers  150   a - 150   f  may have a uniform thickness. In other embodiments, the different conductive layers  150   a - 150   f  may have different thicknesses. 
     One or more insulating layers  152   a - 152   e  are provided between each neighboring pair of the conductive layers  150   a - 105   f . In some embodiments, all of the insulating layers  152   a - 152   e  may have a uniform thickness. In other embodiments, the different insulating layers  152   a - 152   e  may have different thicknesses. The bottom conductive layer  150   a  on the solder (or bottom) side  106  of the board  100  is generally an outermost layer. As illustrated, the top conductive layer  150   f  top side  108  of the board  100  is generally an outermost layer. In some embodiments, the outermost layer on the top side  108  may be an insulating layer. 
     The short edge castellation  112  is generally formed where the short hole intersects the patterns on one or more of the lower conductive layers (e.g.,  150   a - 150   b ). The pattern on each conductive layer  150   a - 150   b  that makes electrical contact with the plating in the short edge castellation  112  has a respective annular pattern. When the package substrate is cut (e.g., the step  134  in  FIG. 2 ), the resulting semi-annular patterns form pads  154 - 156 . A plating deposited (e.g., the step  126  in  FIG. 2 ) provides an electrical connection between the pads  154 - 156 . 
     In many embodiments, the pad  154  in the bottom conductive layer  150   a  is connected to a trace that carries a high-frequency signal related to the circuit  104 . The pad  156  is generally isolated from the rest of the pattern(s) in the next conductive layer  150   b . In some embodiments, the pad  156  may also be connected to a trace to convey the signal passing through the short edge castellation  112  to another area in the board  100 . A shortness of the inter-layer length of the short′ edge castellation  112  generally helps reduce stub-like characteristics (e.g., incident wave reflections and/or inversions) that may contribute to the attenuation and/or distortion of the high-frequency signals. 
     Referring to  FIG. 4 , a cutaway perspective diagram of an example embodiment of the board  100  is shown. An orientation of the board  100  shown in  FIG. 4  is flipped 180 degrees from the orientation shown in  FIG. 1 . The conductive layer  150   a  is generally patterned into multiple traces  160   a - 160   c . Each trace  160   a - 160   c  connects to a respective pad of a respective edge castellation  110 - 114  (e.g.,  160   a  is shown connected to  110 ,  160   b  is shown connected to  112  and  160   c  is shown connected to  114 ). 
     A dielectric layer is generally formed on the traces  160   a - 160   c . The dielectric layer may be patterned into solder masks  161   a - 161   c  over areas that should avoid contact with the solder. The solder is deposited into solder areas  163   a - 163   c  to permit the traces  160   a - 160   c  to be soldered to the respective traces  94   c - 94   a  on the mother board  92 . Some of the solder may flow onto the castellations  110 ,  112  and  114  during the mounting step (e.g., the step  136  in  FIG. 2 ). The solder that extends onto the castellations  110 ,  112  and  114  enables visual inspection of the resulting solder joints. 
     An embodiment of the short edge castellation  112  as shown is only connected to the trace (or pattern)  160   b  in the bottom conductive layer  150   a . The pattern formed in the next conductive layer  150   b  includes a non-conductive area (or insulating area or gap)  164  that electrically isolates the short edge castellation  112  from the rest of the conductive layer  150   b . The electrical isolation helps reduce parasitics (e.g., capacitances, resistances and/or inductances) that contribute to the attenuation and/or distortion of the signal in the trace  160   b . Similar non-conductive areas may be created in one or more of the conductive layers (e.g.,  150   c - 150   f ) aligned with the short edge castellation  112 . For example, a non-conductive area (or insulating area or gap)  166  is shown created in the intermediate conductive layer  150   c  aligned about a half-cylinder  162  defined by the short edge castellation  112 . Additional insulating gaps similar to the non-conductive area  166  may be formed in one or more of the other conductive layers  150   d - 150   f  between the top of the short edge castellation  112  and the top  108  of the board  100 . The non-conductive area(s)  166  may also help reduce parasitics between the short edge castellation  112  and the other conductive layers  150   c - 150   f.    
     Referring to  FIG. 5 , a cutaway perspective diagram of another example embodiment of a board  100   a  is shown. The board  100   a  may be a variation of the board  100 . Elements with common reference numbers generally refer to the same elements in both embodiments. The board  100   a  may be implemented with all short edge castellations  112 ,  116  and  118 . The steps in the method  120  used to create the long edge castellations  110  and  114  of the board  100  may be skipped when fabricating the board  100   a.    
     Referring to  FIG. 6 , a perspective diagram of the board assembly  91  showing the bottom surface  106  is illustrated. The circuits  104  (a single circuit  104  is illustrated for simplicity) are generally mounted on the bottom surface  106  of the board  100 . The circuits  104  may be electrically connected (e.g., wire bonds, soldering, tab bonds, ball grid arrays, or the like) to bonding pads formed in the one or more of the conductive layers  150   a - 150   f  (e.g., the outer layer  150   a ). 
     Use of all short edge castellations  112 ,  116  and  118  generally permits a simple board fabrication technique, eliminating the separate step of creating the long castellations. Since all of the edge castellations of the board  100   a  have the same height, the soldering process and visual inspection criteria of each short edge castellation  112 ,  116  and  118  may be the same. 
     Similar to the long edge castellations  110  and  114  of the board  100 , some short edge castellations (e.g.,  116  and  118 ) of board  100   a  may be used to carry signals between the lower conductive layers (e.g.,  150   a - 150   b ). The pads (e.g.,  154  and  156  in  FIG. 3 ) formed in the patterns of the conductive layer  150   b  may be connected to one or more traces  168  that carry the signals to other areas of the conductive layer  150   b . As such, some short edge castellations (e.g.,  118 ) may be used for inter-conductive layer connections and/or connections to the mother board  92 . 
     The functions and structures illustrated in the diagrams of  FIGS. 1-6  may be designed, modeled and simulated using one or more of a conventional general purpose processor, digital computer, microprocessor, microcontroller and/or similar computational machines, programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software, firmware, coding, routines, instructions, opcodes, microcode, and/or program modules may readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). The software is generally executed from a medium or several media by one or more of the processors. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.