Abstract:
The present invention provides an integrated memory cell array comprising: a semiconductor substrate; a plurality of cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding a lower region of said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and a second source/drain region formed in an upper region of said semiconductor substrate adjoining said gate trench; a plurality of bitlines being connected to respective first groups of first source/drain regions of said cell transistor devices; a plurality of wordlines connecting the respective gates of second groups said cell transistor devices; and a plurality of cell capacitor devices being connected to the second source/drain regions of said cell transistor devices.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an integrated memory cell array. 
   2. Description of the Related Art 
   Junction leakage of an integrated MOSFET transistor to the substrate is one of the key problems in device development. In DRAM applications, for example, these parameters have to be optimized for one contact only, i.e. an asymmetric device. All of these devices for DRAM applications need a body contact. 
   Recently, asymmetric planar devices, asymmetric three-dimensional devices, such as FINCUT or EUD or double gate devices have been proposed for DRAM applications. However, they all have a non-gated direct path from the node junction to the substrate. 
   However, still no satisfactory solution that is easy implementable has been found. 
   BRIEF SUMMARY OF THE INVENTION 
   According to a first aspect of the invention, an integrated memory cell array comprises a semiconductor substrate; a plurality of cell transistor devices formed along a plurality of parallel active area stripes of said substrate, said active area stripes running in a first direction and being laterally insulated from each other by intervening insulation trenches; each of said cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding a lower region of said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and a second source/drain region formed in an upper region of said semiconductor substrate adjoining said gate trench; a plurality of parallel bitlines running in a second direction and being connected to respective first source/drain regions of said cell transistor devices; a plurality of wordlines running in a third direction and connecting the respective gates of said cell transistor devices; and a plurality of cell capacitor devices being connected to the second source/drain regions of said cell transistor devices. 
   According to a second aspect of the invention, an integrated memory cell array comprises a semiconductor substrate; a plurality of cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding a lower region of said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and a second source/drain region formed in an upper region of said semiconductor substrate adjoining said gate trench; a plurality of bitlines being connected to respective first groups of first source/drain regions of said cell transistor devices; a plurality of wordlines connecting the respective gates of second groups of said cell transistor devices; and a plurality of cell capacitor devices being connected to the second source/drain regions of said cell transistor devices. 
   The basic idea underlying this invention is the formation of an array of memory cells having transistor devices with a fully surrounded gate around the contact on one source/drain side and a conventional contact on the other source/drain side. The source/drain side fully surrounded by the gate has no junction area towards the body which leads to a remarkable reduction of leakage current. The GIDL (GIDL=gate induced strain leakage) can be reduced by vertical arranged potential reduction area, i.e. a lowly doped area&lt;10 18  cm −3  between the highly doped source/drain side and the gate. 
   Preferred embodiments are listed in the respective dependent claims. 
   According to an embodiment, each of said cell transistor devices comprises a third source/drain region formed in an upper region of said semiconductor substrate adjoining said gate trench opposite to said second source/drain region, said second and third source/drain regions belonging to two different memory cells which share said first source/drain region and which have adjacent wordlines. 
   According to another embodiment, said second and third directions are orthogonal to each other and said first direction lies between said second and third directions. 
   According to another embodiment, said first direction forms an angle of between 15 and 25 degrees with said second direction. 
   According to another embodiment, said adjacent wordlines are insulated from another neighboring wordline by a respective insulation region formed in said active area stripe. 
   According to another embodiment, each of said cell transistor devices comprises a channel formed in the semiconductor substrate below the gate dielectric which has a curved upper surface in a direction perpendicular to a current flow direction. 
   According to another embodiment, said pillar has curved sidewalls. 
   According to another embodiment, each of said cell transistor devices comprises a channel formed in the semiconductor substrate below the gate dielectric which includes upper corners covered by said gate dielectric and gate. 
   According to another embodiment, said cell capacitor devices are formed above an associated second or third source/drain region. 

   
     DESCRIPTION OF THE DRAWINGS 
     In the Figures: 
       FIG. 1   a )- f ) to  10   a )- f ) show schematic layouts of a manufacturing method for an integrated transistor device used in a memory cell array according to a first embodiment of the present invention; 
       FIG. 11   a )- f ) to  13   a )- f ) show schematic layouts of a manufacturing method for an integrated transistor device used in a memory cell array according to a second embodiment of the present invention; 
       FIG. 14   a )- f ) to  16   a )- f ) show schematic layouts of a manufacturing method for an integrated transistor device used in a memory cell array according to a third embodiment of the present invention; 
       FIG. 17   a )- f ) and  18   a )- f ) show schematic layouts of a manufacturing method for an integrated transistor device used in a memory cell array according to a fourth embodiment of the present invention; and 
       FIG. 19   a ),- c ) to  28   a )- d ) show schematic layouts of a manufacturing method for a memory cell array according to a fifth embodiment of the present invention. 
   

   In the Figures, identical reference signs denote equivalent or functionally equivalent components. 
   In each of  FIG. 1 to 18 , a) denotes a plain view, b) denotes a cross section along line A-A of the plain view of a), c) denotes a cross section along line B-B of the plain view of a), d) denotes a cross section along line I-I of the plain view of a), e) denotes a cross section along line II-II of the plain view of a), and f) denotes a cross section along line III-III of the plain view of a). 
   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1   a )- f ) to  10   a )- f ) show schematic layouts of a manufacturing method for an integrated transistor device used in a memory cell array according to a first embodiment of the present invention. 
     FIG. 1   a )- f ) show a silicon semiconductor substrate  1  in which insulation trenches IT 1  and IT 2  filled with a dielectric insulating material such as silicon dioxide have been formed. The formation of said insulating trenches IT 1 , IT 2  has been carried out by means of a silicon nitride mask stripe  5 , provided on an upper surface OF of said substrate  1 . After an etch step for forming the insulation trenches IT 1 , IT 2 , the insulating filling material has been deposited and treated by a chemical mechanical polishing step wherein the silicon nitride mask stripe  5  has been used as a polish stop. Therefore, the upper surface of the silicon nitride mask stripe  5  and the insulation trenches IT 1 , IT 2  are on a same level L of height. It should be mentioned that the thickness of the silicon nitride mask stripe  5  amounts to x where x is in the order of several 25-200 nm. 
   Although not shown here, it is clear that insulation trenches could also be provided at the remaining two sides of the layout of  FIG. 1   a ). 
   In a subsequent process step shown in  FIG. 2   a )- f ), a hard mask  15  is formed on the structure of  FIG. 1   a )- f ) having a thickness of 2x, i.e. double the thickness of the silicon nitride mask stripe  5  lying thereunder. The material of said hard mask  15  is preferably also silicon nitride. The hard mask  15  includes a window F which exposes a part of said silicon nitride mask stripe  5  and of said insulation trenches IT 1 , IT 2 . It should be mentioned that during the step of forming said hard mask window F, the underlying oxide of said insulation trenches IT 1 , IT 2  can be used for endpoint detection. 
   In a next process step which is depicted in  FIG. 3   a )- f ), a silicon oxide liner layer  30  is deposited on the structure of  FIG. 2   a )- f ) and subjected to an oxide liner spacer etch step for opening said oxide liner layer  30  only on the bottom of said window F such that a smaller window F′ is formed. Thereafter, another silicon nitride layer  25  is deposited and etched back in said smaller window F′ to a final thickness of x, i.e. the thickness of said silicon nitride mask stripe  5  or half of the thickness of said hard mask  15 . 
   Thereafter, as shown in  FIG. 4   a )- f ) the silicon oxide liner layer  30  is stripped in an etch step, said etch step being stopped on the upper surface of said hard mask  15 . As may be obtained from  FIG. 4   a ), the process state of  FIG. 4   a )- f ) differs from the process status of  FIG. 2   a )- f ) by the additional silicon nitride stripe  25  having the extensions of said smaller window F′. 
   In a next process step, a transfer etch is performed which means that the exposed silicon nitride layers  5 ,  15 ,  25  are reduced by thickness of x which results in the process state shown in  FIG. 5   a )- f ). This transfer etch step etches silicon nitride selective to silicon oxide and to silicon. Thus, two windows W 1 , W 2  exposing said substrate  1  are formed between said insulation trenches IT 1 , IT 2 , said windows W 1 , W 2  being separated by a part of said silicon nitride mask stripe  5 . 
   As may be obtained from  FIG. 6   a )- f ), a combined silicon oxide/silicon etch step is now performed for forming a gate trench GW having. The gate trench has one depth in the substrate  1  and in the neighboring insulation trenches IT 1 , IT 2 . Therefore, the etching must proceed much faster in silicon oxide. 
   Alternatively, a silicon oxide etch step may be performed first, and thereafter a silicon oxide/silicon etch step having no selectivity. 
   The etch process for said gate trench GW forms a pillar  1   a  in said substrate  1  which is completely surrounded by said gate trench GW, as may be particularly obtained from  FIG. 6   f ). In the substrate  1  below the bottom of the gate trench GW, there is the channel of the transistor device to be formed. 
   After said etching process of said gate trench GW, optionally channel implants into said windows W 1 , W 2  may be performed for adjusting the characteristics of the transistor channel CH. 
   Having regard to  FIG. 7   a - f ), a gate dielectric layer  40 , for example made of silicon oxide, is formed on the exposed silicon substrate  1  in said gate trench GW, f.e. by thermal oxidation or by high-k material deposition or a combination thereof. Thereafter, a polysilicon layer  50  is deposited and recessed in said gate trench GW which polysilicon layer  50  constitutes the gate of the transistor device to be formed. It should be mentioned that the material for the gate is not limited to polysilicon, but also other conductive materials can be used, such as metals, TiN, silicides etc. 
   Thereafter, another silicon oxide layer  60  is deposited over the entire structure and polished back to the upper surface of the remaining hard mask  15  by a chemical mechanical polishing step. This leads to the process state shown in  FIG. 7   a )- f ). 
   In another process step which is illustrated in  FIG. 8   a )- f ), an silicon oxide/silicon nitride etch step is performed which removes a thickness of x of said silicon oxide layer  60  and the remaining thickness x of said hard mask  15  from the structure of  FIG. 7   a )- f ). 
   Further, with reference to  FIG. 9   a )- f ), the exposed parts of said silicon nitride mask stripe  5  are stripped by a selective etch step, and thereafter an ion implantation is performed into the exposed surface of the substrate  1  in order to form a first source/drain region S in said pillar  1   a  and second and third source/drain regions D 1 , D 2  at the surface OF of said substrate  1 . Then, a poly-silicon layer  70  is deposited and polished back to the level L of the upper surface of the adjoining insulation trenches IT 1 , IT 2 . 
   Finally, as shown in  FIG. 10   a )- f ), another insulating layer  100 , for example made of silicon oxide, is deposited over the entire structure, and thereafter source/drain contacts CD 1 , CD 2 , source/drain contact CS and a gate contact CG are formed for contacting said first and second source/drain regions D 1 , D 2 , said source/drain region S, and said gate region  50 . 
   As may be seen in  FIG. 10   e ), the channel CH of the device according to this embodiment has a planar upper surface in a direction perpendicular to the current flow direction. 
   It should be mentioned here that the source/drain contact CD 2  as well as the source/drain region D 2  are optional and not necessary. In particular, this source/drain region D 2  and source/drain contact CD 2  are useful, if the transistor according to this embodiment is used symmetrically. 
     FIG. 11   a )- f ) to  13   a - f  show schematic layouts of a manufacturing method for an integrated transistor device used in a memory cell array according to a second embodiment of the present invention. 
   The second embodiment starts with the process state shown in  FIG. 5   a )- 5   f ). 
   Having regard to  FIG. 11   a )- f ), the etch process for the gate trench GW′ of the second embodiment is started with a silicon oxide/silicon etch step which etches silicon oxide much faster than silicon such that the final depth of the gate trench GW′ in the insulation trenches IT 1 , IT 2  is reached, thereafter whereas the final depth of the gate trench GW′ in the silicon substrate  1  is not yet reached thereafter. Clearly, this etch step is highly selective with respect to the silicon nitride which is used as a mask. 
   Thereafter, a silicon etch step is performed which is highly selective with respect to silicon oxide and silicon nitride. In this silicon etch step the substrate  1  is etched isotropically which leads to the process state shown in  FIG. 12   a )- f ). 
   Particularly, this silicon etch step results in a lateral thinning of said pillar  1   a ′ resulting in curved sidewalls thereof and a curved surface  1   b ′ of the channel region CH′ below the gate trench GW′, as seen perpendicular to the current flow direction in  FIG. 12   e ). By this silicon thinning step, the electrical characteristics of the transistor to be formed can be varied in a broad way. 
   The process steps following the process state of  FIG. 12   a )- f ) correspond to the process steps of  FIG. 7   a )- f ) to  10   a )- f ), and therefore a repeated description thereof will be omitted here. Only the final process state is shown in  FIG. 13   a )- f ) which corresponds to the process state shown in  FIG. 10   a )- f ). 
     FIG. 14   a )- f ) to  16   a )- f ) show schematic layouts of a manufacturing method for an integrated transistor device used in a memory cell array according to a third embodiment of the present invention. 
   The third embodiment also starts with the process state shown in  FIG. 5   a )- f ). In this third embodiment, the etch step for forming the gate trench GW″ commences with a silicon etch step which is highly selective over silicon oxide and silicon nitride and forms a tapered gate trench GW″ in the silicon substrate  1  as shown in  FIG. 14   a )- f ). 
   Thereafter, a silicon oxide silicon etch step is performed which etches the silicon oxide much faster than silicon. This results in the process state shown in  FIG. 15   a )- f ) which reveals that the channel region CH″ under the gate trench GW″ has a curved surface  1   c , the curvature of which is opposite to the curvature of the surface  1   b ′ of the second embodiment, as may be particularly obtained from  FIG. 15   e ). 
   The process steps following  FIG. 15   a )- f ) correspond to the process steps already explained above with regard to  FIG. 7   a )- f ) to  10   a )- f ), and a repeated description will be therefore omitted here. Only shown in  FIG. 16   a )- f ) is the final process state corresponding to the process state shown in  FIG. 10   a )- f ). 
     FIGS. 17   a )- f ) and  18   a )- f ) show schematic layouts of a manufacturing method for an integrated transistor device used in a memory cell array according to a fourth embodiment of the present invention. 
   The third embodiment starts with the process state shown in  FIG. 6   a )- f ), i.e. after partial formation of the gate trench GW′″. 
   As depicted in  FIG. 17   a )- f ) a silicon oxide etch step is performed subsequent to the process state shown in  FIG. 6   a )- f ) which exposes corners C of the channel CH′″ lying below the gate trench GW′″. For better understanding, in  FIGS. 17   c ),  17   e ) and  17   f ) the dashed line illustrates the process state of  FIG. 6   a )- f ), i.e. before the silicon oxide etch step. 
   The following process steps correspond to process steps described above with respect to  FIG. 7   a )- f ) to  FIG. 10   a )- f ), and a repeated description will be therefore omitted here. 
   Only shown in  FIG. 18   a )- f ) is the final process state corresponding to the process state of  FIG. 10   a )- f ). 
   As may be obtained from  FIG. 18   e ), the gate region  50 ′ which is covered by the oxide layer  60 ′ covers said exposed corners C of the channel CH′″ lying below the gate trench GW′″, i.e. this transistor exhibits a corner device effect. 
     FIG. 19   a )- c ) to  28   a )- d ) show schematic layouts of a manufacturing method for a memory cell array according to a fifth embodiment of the present invention. 
   In each of  FIG. 19 to 28 ,  a ) denotes a plain view, b) denotes a cross section along line A′-A′ of the plain view of a), c) denotes a cross section along line B′-B′ of the plain view of a), and d) denotes a cross section along line C-C′ of the plain view of a), except for  FIG. 19  where d) is omitted. 
   The process status shown in  FIG. 19   a )- c ) corresponds to the process status shown in  FIG. 1   a )- f ). Particularly, an array of parallel mask stripes  5  is formed on the surface of the semiconductor substrate  1  which mask stripes  5  run along z direction. The z direction forms an angle α of about 20 degrees with the x-axis of an orthogonal xy coordinate system shown in  FIG. 19   a ). Between that mask stripes  5  insulation trenches IT having the same dimension as said mask stripes  5  are formed. The substrate stripes under the mask stripes are active area stripes AA where the cell transistors will be formed. 
   The process state of  FIG. 20   a )- d ) corresponds to the process state shown in  FIG. 3   a )- f ). Particularly, stripes of hard mask  15  covered with said oxide liner having intervening windows F′ are formed, and in said windows F′ said nitride layer  25  is deposited and etched back to a thickness of x which is half of the thickness 2x of said hard mask stripes  15 . 
   Thereafter, as shown in  FIG. 21   a )- d ) corresponding to  FIG. 4   a )- f ) said oxide liner layer  30  is stripped in a selective etch step. 
   In a subsequent process step which is shown in  FIG. 22   a )- d ) corresponding to  FIG. 5   a )- f ), the transfer etch for reducing silicon nitride layers  5 ,  15 ,  25  by a thickness of x is performed as described above. 
   The process state shown in  FIG. 23   a )- d ) corresponds to the process state shown in  FIG. 7   a )- f ), i.e. the buried wordlines WL 1 -WL 4  made of gate material  50  are formed in the corresponding wordline trenches etched in said substrate  1  using that silicon nitride layers  5 ,  15  as masks. Finally, insulating silicon oxide layer  60  is deposited and polished back to the upper surface of the residuals silicon nitride layer  15 . As can be clearly seen, the wordlines WL 1 -WL 4  also run in parallel along the y-direction. 
   As shown in  FIG. 24   a )- d ) corresponding to  FIG. 8   a )- f ) a silicon oxide/silicon nitride etch step is performed which removes a thickness of x of said oxide layer  60  and the remaining thickness of said hard mask  15  stripes. 
   In a next process step which is shown in  FIG. 25   a )- d ), a block mask layer M made of silicon oxide is deposited and structured into block stripes running along the y-direction over the memory cell array. Particularly, the individual block stripes of said block mask M cover two adjacent wordlines WL 2 , WL 3  and intervening regions, as may be especially obtained from  FIG. 25   d ). 
   The adjacent block stripes of the block mask M are spaced by one wordline distance, i.e. the distance between wordline WL 1  and WL 2  and the distance between wordline WL 3  and WL 4 , respectively. 
   Using said block mask M, firstly the exposed silicon nitride layer  5  is selectively removed, f.e. in a hot phosphor acid etch step. This etch step is selective with respect to the adjacent isolation trench regions IT and the block mask M itself. 
   Thereafter, a silicon etch is performed for removing a silicon substrate  1  region along the active area stripes AA between wordlines WL 1  and WL 2  and between wordlines WL 3  and WL 4 , as may be obtained from  FIG. 25   d ). Then, insulation regions  61  are formed by a silicon oxide deposition and backpolish step which electrically isolate the wordlines WL 2  and WL 3  from the corresponding other neighboring wordline WL 1  and WL 4 , respectively. 
   It should be mentioned here, that instead of removing the respective silicon substrate  1  regions by an etch step, an implantation step, f.e. implanting boron ions, into the substrate  1  using the block mask M could be performed in order to form said insulation regions  61 . 
   The process state shown in  FIG. 26   a )- d ) is achieved by removing the block mask layer M and bringing the insulation regions  61  down to the level of the remaining silicon nitride mask stripes  5  in said backpolish step. 
   Then, as already explained with respect to  FIG. 9   a )- f ), the exposed silicon nitride mask stripes  6  are stripped, and an implantation step is performed in order to form source and drain regions S, D 1 , D 2 , and then the polysilicon layer  70  is deposited and polished back to the level of the adjoining insulation trenches IT. 
   Further with respect to  FIG. 27   a )- d ), an insulation layer  100  made of silicon oxide is formed over the entire memory cell array. Then, bitline contact holes BLK 1 , BLK 2 , BLK 3 , BLK 4  are formed in a photolithography/etch step using a stripe mask along lines B′-B′ to contact the source regions S of the cell transistors. Subsequently, bitlines BL 1 , BL 2 , BL 3 , BL 4  running in parallel along the x-direction are formed, which bitlines BL 1 , BL 2 , BL 3 , BL 4  comprise a lower polysilicon layer  101 , an intermediate tungsten layer  102  and an upper nitride cap layer  103  as well know in the art. The polysilicon layer  101  forms the bitline contacts in bitline contact holes BLK 1 , BLK 2 , BLK 3 , BLK 4 . As may be seen in  FIG. 27   c , a slight underetch is created in the source regions S in the step of etching said bitlines BL 1 , BL 2 , BL 3 , BL 4 . 
   Thereafter, as depicted in  FIG. 28   a )- d ), another dielectric layer  105  made of silicon dioxide is deposited and polished back to the upper side of said bitlines BL 1 , BL 2 , BL 3 , BL 4 . Then, capacitor contacts CC 11 , CC 12 , CC 21 , CC 22 , CC 31 , CC 32 , CC 41 , CC 42  are formed in said dielectric layer  105  to expose the drain regions D 1 , D 2  of the cell transistor devices. These capacitor contacts CC 11 , CC 12 , CC 21 , CC 22 , CC 31 , CC 32 , CC 41 , CC 42  can be formed by a photolithography/etch step followed by a deposition/backpolish step using f.e. tungsten as contact material. 
   In a final process step, capacitors C 11 , C 12 , C 21 , C 22 , C 31 , C 32 , C 41 , C 42  are formed on the most upper level above said dielectric layer  105 , thus completing the memory cell array. Said capacitors C 1 , C 12 , C 21 , C 22 , C 31 , C 32 , C 41 , C 42  can be formed in symmetrical rows and columns, shifted rows and columns or any other suitable arrangement. 
   As may be seen from  FIG. 28   d ), the memory cells of this array are symmetrically, i.e. share bitline BL 1  and are connected to two different wordlines WL 2  and WL 3 . The major advantage of the memory cell array according to this embodiment is that the transistor can cut-off more effectively, because of the fully surrounding gate on the node side. There is the possibility to form a sub-6F 2  memory cell, because the size of the memory cells in bitline direction amounts to 2F whereas the size of the memory cells in wordline direction is diminishable from 2F, because of the spacer concept using the oxide spacer layer  30  for the source contacts. 
   It should be noted that the transistor devices of the memory cell array according to the fifth embodiment are shown as being identical to the transistor devices explained above with respect to  FIG. 1   a )-F) to  10   a )- f ). However, of course the transistor devices according to  FIG. 11   a )- f ) to  13   a )-),  14   a )- f ) to  16   a )- f ) and  17   a )- f ) to  18   a )- f ) may also be used for the memory cell array according to the present invention. 
   Particularly, the active areas AA may also have a zig-zag substructure which can be achieved by mirroring every second drain  1 —source-drain  2 —element. 
   Although the present invention has been described with reference to a preferred embodiment, it is not limited thereto, but can be modified in various manners which are obvious for a person skilled in the art. Thus, it is intended that the present invention is only limited by the scope of the claims attached herewith.