Abstract:
A control circuit is provided to generate a mode signal at light load of the power converter. The mode signal is coupled to disable the switching signal for saving power. The impedance of an input circuit is increased in response to the mode signal. Furthermore, a soft start circuit is initiated by the mode signal when switching signal is enabled. An external capacitor associates with the impedance of the input circuit determine the off period of the switching signal.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to power converters, and more specifically relates to the control of switching power converters. 
         [0003]    2. Description of Related Art 
         [0004]    Switching power converters have been widely used to provide regulated voltage and current. However, the switching of power converter will cause power losses such as conduction loss and switching loss, in which the switching loss is the significant power loss at light load. In order to maintain high efficiency of power converter at light load, many techniques have been proposed to reduce the power consumption, such as “Full load to no-load control for a voltage fed resonant inverter” by Park, et al, U.S. Pat. No. 4,541,041; “Strobed DC-DC converter with current regulation” by Pace, et al, U.S. Pat. No. 5,028,861; “Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit” by Wilcox, et al, U.S. Pat. No. 5,481,178; “Switching regulator having low power mode responsive to load power consumption” by Jeffrey Hwang, U.S. Pat. No. 5,747,977. However, the drawback of these prior arts is the load detection circuit of the power converter. A hysteresis comparator is utilized to detect the load condition and on/off state of the power converter. The switching frequency of the power converter cannot be programmed especially when acoustic noise is generated. Besides, the output ripple caused by the burst switching is uncontrollable. These shortcomings are the main object of the present invention to overcome. 
       SUMMARY OF THE INVENTION 
       [0005]    The present invention provides a control circuit including a switching circuit coupled to a feedback loop of the power converter to generate a switching signal in response to a feedback signal for regulating output. A soft start circuit generates a soft start signal coupled to switching circuit to control the pulse width of the switching signal for the soft start. An input circuit is connected to the feedback loop. A comparison circuit is coupled to the feedback loop to generate a mode signal when the feedback signal is lower than a threshold signal. The mode signal is used to disable the switching signal for saving power. The mode signal is further coupled to reset the soft start circuit for enabling soft start of the switching signal when switching signal is enabled. The impedance of the input circuit is increased in response to the enablement of the mode signal. The resistance of the input circuit associated with the capacitance of an external capacitor determines the off period of the switching signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The accompanying drawings are included to provide further understanding of the invention, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
           [0007]      FIG. 1  shows a schematic diagram of a power converter. 
           [0008]      FIG. 2  is a preferred embodiment of a control circuit of the power converter according to the present invention. 
           [0009]      FIG. 3  shows an oscillation circuit according to a preferred embodiment of the present invention. 
           [0010]      FIG. 4  is a soft start circuit according to a preferred embodiment of the present invention 
           [0011]      FIG. 5  shows switching signal waveforms according to a preferred embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0012]      FIG. 1  shows a circuit schematic of a power converter. A control circuit  90  generates a switching signal V G  to regulate the output of the power converter in response to a feedback signal V FB  at a feedback terminal FB. The switching signal V G  drives a power transistor  20  for switching a transformer  10 . The transformer  10  is connected to an input voltage V IN  of the power converter for energy storage and power transfer. The energy of the transformer  10  is transferred to the output of the power converter through a rectifier  40  and a capacitor  45 . An output voltage V O  is coupled to an opto-coupler  50  through a resistor  65  and zener diode  60 . The output of the opto-coupler  50  is connected to the feedback terminal FB of the controller  90  to form a feedback loop. The pulse width of the switching signal V G  is modulated in response to the feedback signal V FB  to achieve the regulation of the power converter. 
         [0013]      FIG. 2  shows a preferred embodiment of the controller  90  according to the present invention. The controller  90  includes a comparison circuit  110 , an input circuit  100 , a switching circuit  200 , a soft start circuit  280  and an oscillation circuit  300 . 
         [0014]    The switching circuit  200  is used to generate the switching signal V G  in response to an oscillation signal PLS. The oscillation circuit  300  is adapted to periodically generate the oscillation signal PLS and a ramp signal RAMP. In one embodiment of the present invention, the switching circuit  200  includes a flip-flop  210  to generate the switching signal V G  through an AND gate  230 . The input of the AND gate  230  is connected to the output of the flip-flop  210 . Another input of the AND gate  230  is connected to the oscillation signal PLS through an inverter  215  to limit the maximum duty cycle of the switching signal V G . The flip-flop  210  is enabled in response to the oscillation signal PLS. An AND gate  253  is coupled to reset the flip-flop  210 . The output of comparators  250  and  251  are connected to inputs of the AND gate  253 . The positive input of the comparator  250  is connected to the input circuit  100 . The negative input of the comparator  250  is coupled to the ramp signal RAMP for the pulse width modulation (PWM). The negative input of the comparator  251  is also coupled to the ramp signal RAMP. The positive input of the comparator  251  is coupled to receive a soft start signal SS for the soft start of the switching signal V G . 
         [0015]    In one embodiment of the present invention, the input circuit  100  includes a resistive device  150  and the feedback input circuit  240 . The feedback input circuit  240  is coupled to the output of the power converter through the feedback terminal FB and the feedback loop of the power converter (shown in  FIG. 1 ). A transistor  241  and resistors  245  and  246  form the feedback input circuit  240 . The transistor  241  performs the level shift. The feedback signal V FB  is connected to the gate of the transistor  241 . A feedback signal V 245  is generated at the source of the transistor  241 . Resistor  245  and  246  further provides attenuation to the feedback signal V 245  to stabilize the feedback loop. The resistor  245  is connected to the feedback signal V 245 . An attenuated feedback signal V 246  is generated at the resistor  246 . The feedback signal V 246  is connected to the positive input of the comparator  250  for PWM control. 
         [0016]    The comparison circuit  110  is coupled to the feedback input circuit  240  to generate a mode signal LEN when the feedback signal V 245  is lower than a threshold signal V REF . The mode signal LEN indicates the light load of the power converter. Wherein the mode signal LEN resets the soft start circuit for enabling soft start of the switching signal when switching signal is enabled. The control circuit  90  further comprises an external capacitor  70  coupled to the input circuit  100 . An external capacitor  70  is coupled to the feedback terminal FB as shown in  FIG. 1 . A resistive device  150  is coupled to the feedback terminal FB as well. The resistive device  150  and the external capacitor  70  operate as a low-pass filter for the feedback signal V FB . A transistor  140  and resistors  120  and  125  constitute the resistive device  150 . The resistor  120  and the resistor  125  are connected in serial. The transistor  140  is connected to the resistor  120  in parallel. The mode signal LEN controls the on/off of the transistor  140 . Therefore, the resistance of the resistive device  150  is increased in response to the enablement of the mode signal LEN. 
         [0017]    The resistance of the input circuit  100  will be increased once the mode signal LEN is enabled, which causes the feedback signal V FB  to become low. The switching signal V G  will be turned on again when the feedback signal V FB  is charged up to a voltage V B . The voltage V B  can be expressed as, 
         [0000]                    V   B     =       V   A     ×     (     1   -     ɛ       -     T   OFF         R   ×   C           )               (   1   )                 V   B   =V   REF   +V   241   (2) 
         [0000]    in which the voltage V A  is given by, 
         [0000]        V   A   V   CC −( I   C   ×R )  (3) 
         [0000]        I   C   =CTR×I   D   (4) 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     
                       
                         V 
                         O 
                       
                       - 
                       
                         V 
                         Z 
                       
                       - 
                       
                         V 
                         D 
                       
                     
                     
                       R 
                       65 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where T OFF  is the off period of the switching signal V G ; R is the resistance of the resistive device  150 ; C is the capacitance of the external capacitor  70 ; V REF  is the voltage of the threshold signal V REF ; V 241  is the threshold voltage of transistor  241 ; I C  is a feedback current, which is the output current of the opto-coupler  50  (shown in  FIG. 1 ); I D  is the input current of the opto-coupler  50  (shown in  FIG. 1 ); CTR is the current transfer rate of the opto-coupler  50 ; V D  is the forward voltage drop of the opto-coupler  50 ; V Z  is the voltage of the zener diode  60 ; R 65  is the resistance of the resistor  65 .
 
The equation (1) can be rewritten as,
 
         [0000]    
       
         
           
             
               
                 
                   
                     T 
                     OFF 
                   
                   = 
                   
                     R 
                     × 
                     C 
                     × 
                     
                       
                          
                         n 
                       
                       ( 
                       
                         
                           V 
                           A 
                         
                         
                           
                             V 
                             A 
                           
                           - 
                           
                             V 
                             B 
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The capacitance C of the external capacitor  70  associated with the resistance R of the resistive device  150  determines the T OFF  of the switching signal V G . The feedback current I C  is further coupled to adjust the T OFF  to control the output ripple of the power converter. 
         [0018]      FIG. 3  shows the oscillation circuit  300  according to a preferred embodiment of the present invention. A charge current  310  is connected to a switch  315  in serial for charging a capacitor  350 . A discharge current  320  is connected to a switch  325  in serial for discharging the capacitor  350 . The ramp signal RAMP is therefore generated on the capacitor  350 . Comparators  370 ,  380  and NAND gates  375 ,  385  generate the oscillation signal PLS. The oscillation signal PLS is connected to control switches  315  and  325  through inverters  390  and  395  respectively. Trip-point voltages V H  and V L  are connected to comparators  370  and  380  respectively. The ramp signal RAMP thus swings in between the trip-point voltage V H  and V L . 
         [0019]      FIG. 4  shows the soft start circuit  280  according to a preferred embodiment of the present invention. A charge current  291  is connected to charge a capacitor  293 . A transistor  292  is connected to the capacitor  293  in parallel for discharging the capacitor  293 . The soft start signal SS is generated on the capacitor  293 . An OR gate  295  is connected to control the on/off of the transistor  292 . An input of the OR gate  295  is connected to the mode signal LEN. Another input of the OR gate  295  is coupled to a power-on-reset signal PWRST through an inverter  296 . A resistive device  297  and a capacitor  298  generate the power-on-reset signal PWRST during the power on of the controller  90 . Therefore, the capacitor  293  is reset in response to the power-on-reset signal PWRST and/or the mode signal LEN. The soft start signal SS is further coupled to control the pulse width of the switching signal V G  for the soft start. 
         [0020]      FIG. 5  shows the waveform of the switching signal V G  and the mode signal LEN according to a preferred embodiment of the present invention. The switching signal V G  is enabled during the T ON  period. The period of T ON  is depended on the load condition and the feedback. Once the feedback signal V 245  is lower than the threshold signal V REF , the mode signal LEN will be enabled to turn off the switching signal V G . The T OFF  period can be programmed by the external capacitor  70  to prevent the switching period of the switching signal V G  from falling into the audio band. 
         [0021]    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.