Abstract:
A current sensing circuit and the control circuit thereof and a power converter circuit. The current sensing circuit includes a sample and hold circuit ( 1 ), a rising edge detecting circuit ( 2 ), a falling edge detecting circuit ( 3 ), a timing control circuit ( 4 ), a synchronous detecting circuit ( 5 ) and a low pass filter ( 6 ). The power converter circuit uses the current sensing circuit to sense and process the current flowing through a main switch (S 1 ).

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of the circuit, and particularly relates to an current detection circuit, and a control circuit and a power conversion circuit thereof. 
       BACKGROUND OF THE INVENTION 
       [0002]    The power conversion circuits, such as AC-DC conversion circuits, can convert the alternating current into the direct current to supply power to the relevant apparatuses. However, an existing power conversion circuits usually don&#39;t have the output current detection function. 
       DISCLOSURE OF THE INVENTION 
     Technical Problem 
       [0003]    An object of the embodiments of the present invention is to provide a current detection circuit for the power conversion circuit, which can detect the output current and features with high reliability, simple structure, and low cost. 
         [0004]    Another object of the embodiments of the present invention is to provide a control circuit for the above-mentioned current detection circuit. 
         [0005]    Another object of the embodiments of the present invention is to provide a power conversion circuit with the above-mentioned control circuit. 
       Technical Solution 
       [0006]    The embodiments of the present invention are implemented as follows: a current detection circuit for the power conversion circuit, comprising a sample and hold circuit, a rising edge detection circuit, a falling edge detection circuit, a timing control circuit, a synchronous detection circuit, and a low-pass filter, wherein, the first terminal of the sample and hold circuit is connected with the third terminal of the drive control tube, the second terminal of the sample and hold circuit is connected with the first terminal of the timing control circuit, and the third terminal of the sample and hold circuit is connected with the first terminal of the synchronous detection circuit; the first terminal of the rising edge detection circuit is connected with the second terminal of the main switch S 1 , and the second terminal of the rising edge detection circuit is connected with the second terminal of the timing control circuit; the first terminal of the falling edge detection circuit is connected with the second terminal of the main switch S 1 , and the second terminal of the falling edge detection circuit is connected with the third terminal of the timing control circuit; the fourth terminal of the timing control circuit is connected with the second terminal of the synchronous detection circuit, and the third terminal of the synchronous detection circuit is connected with the first terminal of the low-pass filter, and the second terminal of the low-pass filter is the output terminal of the current detection circuit. 
         [0007]    The embodiments of the present invention provide a power conversion circuit with the above-mentioned control circuit, which comprising: 
         [0008]    A filter circuit  12 , connected with an external AC power supply and designed to filter off the noise in the AC power supply; a rectifier circuit  13 , connected with the filter circuit and designed to convert the alternating current into direct current; and 
         [0009]    A single-stage power conversion circuit  14 , comprising a capacitor C 1 , an inductor or switching transformer L, a diode D 1 , a capacitor C 2 , a main switch S 1 , a drive control tube S 2 , a resistor R 2 , a control circuit, and an auxiliary power supply circuit, wherein, the first terminal of the capacitor C 1  is connected with the rectifier circuit and the negative electrode of a DC load, and the second terminal of the capacitor C 1  is grounded; the first terminal of the inductor or switching transformer L is connected with the negative electrode of the DC load, the second terminal of the inductor or switching transformer L is connected with the positive electrode of the diode D 1 , and the negative electrode of the diode D 1  is connected with the positive electrode of the DC load; the capacitor C 2  is connected between the positive electrode and negative electrode of the DC load; the first terminal of the main switch S 1  is connected with the negative electrode of the DC load through the auxiliary power supply circuit, and the second terminal of the main switch S 1  is connected with the positive electrode of the diode D 1 ; the first terminal of the drive control tube S 2  is connected with the control circuit, the second terminal of the drive control tube S 2  is connected with the third terminal of the main switch S 1 , and the third terminal of the drive control tube S 2  is grounded through the resistor R 2  and is also connected with the control circuit; the control circuit is also connected to the second terminal of the main switch S 1 ; the single-stage power conversion circuit is designed to regulate the power factor, and obtain the output current signals through computation by detecting the circuit current through the main switch. 
       Beneficial Effects 
       [0010]    The current detection circuit for the power conversion circuit provided in the present invention obtains the output current signals through computation by detecting the circuit current through the main switch. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a circuit diagram of a power conversion circuit that applies the current detection circuit provided in the present invention; 
           [0012]      FIG. 2  is a schematic circuit diagram of a control circuit that has the current detection circuit provided in the present invention in  FIG. 1 ; 
           [0013]      FIG. 3  is a circuit diagram of a first preferred embodiment of the current detection circuit provided in the present invention; 
           [0014]      FIG. 4  is a circuit diagram of a second preferred embodiment of the current detection circuit provided in the present invention; 
           [0015]      FIG. 5  is a waveform schematic diagram at the points shown in  FIG. 1  and  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0016]    To make the objects, technical solution and advantages of the present invention understood more clearly, the present invention will be further detailed in embodiments, with reference to the accompanying drawings. It should be understand that the embodiments described here are only provided to interpret the present invention, but not to limit the present invention. 
         [0017]    A current detection circuit for the power conversion circuit is provided in the embodiments of the present invention. The current detection circuit can detect the output current and features with high reliability, simple structure. 
         [0018]    Referring to  FIG. 1 . The power conversion circuit provided in the present invention comprises a filter circuit  12 , a rectifier circuit  13  and a single-stage power conversion circuit  14 . 
         [0019]    The filter circuit  12  is connected with both the live wire L and null wire N of the external AC power supply. 
         [0020]    The rectifier circuit  13  is connected with the external AC power supply through the filter circuit  12 . 
         [0021]    The single-stage power conversion circuit  14  is connected between the positive output terminal of the rectifier circuit  13  and a DC load  15 . Here the node between the positive output terminal of the rectifier circuit  13  and the DC load  15  is denoted as “C”. 
         [0022]    Wherein, the filter circuit  12  is a filter circuit well-known in the art, and the rectifier circuit  13  is a bridge rectifier circuit. They will not be described further here. 
         [0023]    The single-stage power conversion circuit  14  comprises a capacitor C 1 , an inductor or switching transformer L, a diode D 1 , a capacitor C 2 , a main switch S 1 , a drive control tube S 2 , a resistor R 2 , a control circuit  16 , and an auxiliary power supply circuit  17 . 
         [0024]    The first terminal of the capacitor C 1  is connected with the rectifier circuit  13  and the negative electrode of the DC load  15 , and the second terminal of the capacitor C 1  is grounded; the first terminal of the inductor or switching transformer L is connected with the negative electrode of the DC load  15 , the second terminal of the inductor or switching transformer L is connected with the positive electrode of the diode D 1 , and the negative electrode of the diode D 1  is connected with the positive electrode of the DC load  15 ; the capacitor C 2  is connected between the positive electrode and negative electrode of the DC load  15 ; the first terminal of the main switch S 1  is connected with the negative electrode of the DC load  15  through the auxiliary power supply circuit  17 , and the second terminal of the main switch S 1  is connected with the positive electrode of the diode D 1 ; the first terminal of the drive control tube S 2  is connected with the first terminal H of the control circuit  16 , the second terminal of the drive control tube S 2  is connected with the third terminal of the main switch S 1 , and the third terminal of the drive control tube S 2  is grounded through the resistor R 2  and is also connected with the second terminal U of the control circuit  16 , the third terminal D of the control circuit  16  is connected with the second terminal of the main switch S 1 . 
         [0025]    The main switch S 1  and the drive control tube S 2  are N-channel field effect tubes. Here, the node between the drain electrode of the main switch S 1  and the positive electrode of the diode D 1  is denoted as “D”, the node between the gate electrode of the main switch S 1  and the auxiliary power supply circuit  17  is denoted as “E”, and the node between the drain electrode of the drive control tube S 2  and the source electrode of the main switch S 1  is denoted as “F”. 
         [0026]    Referring to  FIG. 2 . The control circuit  16  comprises a peak-valley detection circuit  161 , a current detection circuit  162 , an error amplifier Err_amp, a PWM controller U 1 , and a drive control circuit  163 ; the input terminal U of the current detection circuit  162  is connected with the third terminal of the drive control tube S 2 , the input terminal D of the current detection circuit  162  is connected with the second terminal of the main switch S 1 , and the output terminal of the current detection circuit  162  is connected with the input terminal of the error amplifier Err_amp; the output terminal of the error amplifier Err_amp is connected with the PWM controller U 1 , which is connected with the first terminal of the drive control circuit  163 ; the second terminal of the drive control circuit  163  is connected with the output terminal of the peak-valley detection circuit  161 , and the third terminal of the drive control circuit  163  is connected with the first terminal of the drive control tube S 2 ; the input terminal of the peak-valley detection circuit  161  is connected with the second terminal of the main switch S 1 . 
         [0027]    The auxiliary power supply circuit  17  comprises a diode D 2 , a resistor R 1 , a capacitor C 6 , and a voltage-stabilizing tube Z 2 , wherein, the positive electrode of the diode D 2  is connected with the negative electrode of the DC load  15 , and the negative electrode of the diode D 2  is grounded through the resistor R 1  and capacitor C 6  in turn; the node between the resistor R 1  and capacitor C 6  is connected with the first terminal of the main switch S 1 ; the positive electrode of the voltage-stabilizing tube Z 2  is grounded, and the negative electrode of voltage-stabilizing tube Z 2  is connected with the first terminal of the main switch S 1 . 
         [0028]    The working process of the power conversion circuit in the present invention will be described as follows: 
         [0029]    The filter circuit  12  is designed to filter off the noise in the AC power supply, the rectifier circuit  13  is designed to carry out AC-DC conversion, and the single-stage power conversion circuit  14  is designed to regulate the power factor of the power conversion circuit and detect the output current. Wherein, the auxiliary power supply circuit  17  in the single-stage power conversion circuit  14  is designed to provide auxiliary power supply, the control circuit  16  is designed to detect the output current which output to the DC load  15 , and regulate the average output current value which output to the DC load  15  to a predetermined value set in it, so as to achieve constant current output control. 
         [0030]    The input control terminal E of the main switch S 1  is clamped to a fixed level after power-on, and the ON/OFF of the main switch S 1  is mainly controlled by the drive control tube S 2 . Once the main switch S 1  switches on, the current in the inductor L will rise up; when the main switch S 1  switches off, the voltage at the point D above the main switch S 1  will rise up from 0 gradually (switch off at voltage “0”) due to the effect of the parasitic capacitance of the main switch S 1  and diode D 1 ; once the potential at point D exceeds the potential at point K of the DC load  15 , the diode D 1  will gate on, and the current in the inductor L will be output to the DC load  15  through the diode D 1  which will drop from the peak value; once the current in the inductor L drops to 0, the potential at the point D above the main switch S 1  will drop owing to the resonance effect between the parasitic capacitance of the diode D 1  and main switch S 1  and the inductor L; after a while, a peak-valley voltage value will occur at the point D above the main switch S 1 . 
         [0031]    The peak-valley detection circuit  161  is mainly designed to control the switch-on moment of the single-stage power conversion circuit  14  through detects the voltage at the terminal D, and, when a peak-valley voltage value occurs, sends the detected result to the drive control circuit  163 , the drive control circuit  163  and drive control tube S 2  drive the main switch S 1  to switch on at that moment and thereby achieve switch-on at “zero” voltage, reduce the switching loss. In the working process of the circuit, as the ON time of the main switch S 1  increases, the working current in the inductor L and the current output to the load  15  will increase; as the ON time of the main switch S 1  decreases, the working current in the inductor L and the current output to the load  5  will decrease. 
         [0032]    Referring to  FIG. 2 . The control circuit  16  and the single-stage power conversion circuit  14  have three connection ports: D, U and H. The ports D and U are two input terminals of the control circuit  16 , and the control circuit  16  generates a control signal at port H according to the information from the two input terminals, so as to control the drive control tube S 2 , and thereby control the operation of the entire single-stage power conversion circuit  14 . The control circuit  16  needs to obtain the information on the current output to the load  15 , so as to control the switching circuit and obtain the better power supply efficiency and power factor. 
         [0033]    The power conversion circuit in the present invention filters off the noise in the AC power supply through the filter circuit  12 , carries out AC-DC conversion through the rectifier circuit  13 , and detects the output current and regulates the power factor through the single-stage power conversion circuit  14 . 
         [0034]    Furthermore, the power conversion circuit in the present invention further comprises a fuse F 1 . The fuse F 1  is connected between the live wire L and the filter circuit  12 . In case the current flow through the fuse F 1  is too high, the fuse F 1  will be fusing to protect the power conversion circuit. 
         [0035]    Referring to  FIG. 2 . Moreover, the current detection circuit  162  further comprises a sample and hold circuit  1 , a rising edge detection circuit  2 , a falling edge detection circuit  3 , a timing control circuit  4 , a synchronous detection circuit  5 , and a low-pass filter  6 . 
         [0036]    The first terminal S 11  of the sample and hold circuit  1  is connected with the node U, the second terminal S 12  of the sample and hold circuit  1  is connected with the first terminal S 41  of the timing control circuit  4 , and the third terminal S 13  of the sample and hold circuit  1  is connected with the first terminal S 51  of the synchronous detection circuit  5 . 
         [0037]    The first terminal S 21  of the rising edge detection circuit  2  is connected with the node D, and the second terminal S 22  of the rising edge detection circuit  2  is connected with the second terminal S 42  of the timing control circuit  4 . 
         [0038]    The first terminal S 31  of the falling edge detection circuit  3  is connected with the node D, and the second terminal S 32  of the falling edge detection circuit  3  is connected with the third terminal S 43  of the timing control circuit  4 . 
         [0039]    The fourth terminal S 44  of the timing control circuit  4  is connected with the second terminal S 52  of the synchronous detection circuit  5 . 
         [0040]    The third terminal S 53  of the synchronous detection circuit  5  is connected with the first terminal S 61  of the low-pass filter  6 . The second terminal S 62  of the low-pass filter  6  is connected with the input terminal of the error amplifier Err_amp. 
         [0041]    The control circuit  16  detects the current through the sample resistor R 2  by the current detection circuit  162  and treats the current signal, so as to obtain the current average value output to the DC load  15 , input the current average value to the drive control circuit  163 , and compare with the preset value, to decide whether to increase or decrease the ON time of the main switch S 1 , and thereby regulate the output current to the preset value. No matter whether the DC load  15  or the input voltage varies, the drive control circuit  163  can dynamically regulates the ON/OFF time of the main switch S 1  to obtain the expected current output from the DC load  15 . 
         [0042]    Referring to  FIG. 3 , as a preferred embodiment of the present invention, the sample and hold circuit  1  in the current detection circuit  162  comprises an N-channel FET N 1 , an inverter INV 1 , a capacitor C 3 , an amplifier A 1 , and resistors R 3  and R 4 . The drain electrode of the N-channel FET N 1  is connected with the node U, the gate electrode of N 1  is connected with the input terminal of the inverter INV 1 , and the source electrode of N 1  is grounded through the capacitor C 3 . The input terminal of the inverter INV 1  is connected with a control terminal CTL. The non-inverting input terminal of the amplifier A 1  is connected with the source electrode of the N-channel FET N 1 , the inverting input terminal of A 1  is grounded through the resistor R 3 , and the output terminal of A 1  is connected with the inverting input terminal through the resistor R 4 . The current sample and hold circuit  1  is in sample mode when the main switch S 1  is in ON state, and outputs a signal that is proportional to the input current signal; the current sample and hold circuit  1  will enter into hold mode when the main switch S 1  switches off. 
         [0043]    The rising edge detection circuit  2  comprises an amplifier A 2  and resistors R 5  and R 6 . One terminal of the resistor R 5  is connected with the node D, and the other terminal of the resistor R 5  is grounded through the resistor R 6 . The non-inverting input terminal of the amplifier A 2  is connected to the node between the resistor R 5  and resistor R 6 , and the inverting input terminal of the amplifier A 2  is connected with a reference voltage terminal VREF 2 . Once the rising edge detection circuit  2  detects that the voltage at the point above the main switch S 1  rises to a preset value, it will trigger a latch circuit and control the synchronous detection circuit  5  to work, and output the signals from the current sample and hold circuit  1  to the low-pass filter  6 . 
         [0044]    The falling edge detection circuit  3  comprises an amplifier A 3 , an inverter INV 2 , an N-channel FET N 2 , a capacitor C 4 , clamping Zener diodes Z 1 ˜Z 4 , and resistors R 7  and R 8 . One terminal of the resistor R 7  is connected with the node D, and the other terminal of the resistor R 5  is grounded through the resistor R 8 . One terminal of the capacitor C 4  is connected with the node between the resistor R 7  and resistor R 8 , and the other terminal of the capacitor C 4  is connected with the non-inverting input terminal of the amplifier A 3 . The inverting input terminal of the amplifier A 3  is connected with a reference voltage terminal VREF 1 , and the output terminal of the amplifier A 3  is connected with the input terminal of the inverter INV 2 . The gate electrode and drain electrode of the N-channel FET N 2  are connected with the non-inverting input terminal of the amplifier A 3 , and the source electrode of N 2  is grounded. The negative electrode of the clamping Zener diode Z 1  is connected to the node between the resistor R 7  and resistor R 8 , and the positive electrode of Z 1  is grounded through clamping Zener diodes Z 2 ˜Z 4  in sequence. Once the falling edge detection circuit  3  detects a falling edge of voltage at the point above the main switch S 1 , it will unlock the latch and cut off the synchronous detection circuit  5 , to force the input signal of the low-pass filter  6  to “0”. 
         [0045]    The timing control circuit  4  comprises D flip-flops DF 1  and DF 2 . The clock signal terminal CK of the D flip-flop DF 1  is connected with the output terminal of the inverter INV 2  in the falling edge detection circuit  3 , the reset terminal R of DF 1  is connected with the output terminal of the inverter INV 1  in the sample and hold circuit  1 , the signal input terminal D of DF 1  is connected with a power supply VDD, the output terminal Q of DF 1  is connected with the reset terminal R of the D flip-flop DF 2 , and the inverted output terminal QB of DF 1  is free. The terminal CK of the D flip-flop DF 2  is connected with the output terminal of the amplifier A 2  in the rising edge detection circuit  2 , the signal input terminal D of DF 2  is connected with the power supply VDD, and the output terminal Q of DF 2  is free. 
         [0046]    The synchronous detection circuit  5  comprises an inverter INV 3  and N-channel FETs N 3  and N 4 . The input terminal of the inverter INV 3  is connected with the inverted output terminal QB of the D flip-flop DF 2  in the timing control circuit  4 , and the output terminal of INV 3  is connected with the gate electrode of the N-channel FET N 3 . The drain electrode of the N-channel FET N 3  is connected with the output terminal of the amplifier A 1  in the sample and hold circuit  1 , and the source electrode of N 3  is connected with the drain electrode of the N-channel FET N 4 . The gate electrode of the N-channel FET N 4  is connected with the input terminal of the inverter INV 3 , and the source electrode of N 4  is grounded. 
         [0047]    The low-pass filter  6  comprises a resistor R 9  and a capacitor C 5 . One terminal of the resistor R 9  is connected with the drain electrode of the N-channel FET N 4  in the synchronous detection circuit  5 , and the other terminal of the resistor R 9  is grounded through the capacitor C 5  and is also connected with the input terminal of the error amplifier; the low-pass filter  6  filters the input signal and then outputs a signal that is proportional to the current average value output from the DC load  15 . 
         [0048]    Referring to  FIG. 5  at the same time. The current waveform of the inductor L is denoted as “I_L”, the current waveform of the diode D 1  is denoted as “I_D 1 ”, the voltage waveform of the node F is denoted as “V_F”, the voltage waveform of the node D is denoted as “V_D”, the output signal waveform of the sample and hold circuit  1  is denoted as “S_H_out”, the output signal waveform of the synchronous detection circuit  5  is denoted as “Syn_out”, the output waveform of output terminal Q of the D flip-flop DF 1  is denoted at “DF 1 _Q”, and the output waveform of inverted output terminal QB of the D flip-flop DF 2  is denoted as “DF 2 _QB”. 
         [0049]    It can be seen from  FIG. 5  that the current average value I_avr output to the DC load  15  is equal to the average value of I_D 1 , i.e., equal to the peak value of I_D 1  divided by 2 and multiplied by the duty ratio. From the viewpoint of actual application, only a signal proportional to I_avr is required. Hereafter how the current detection circuit  162  acquires such a signal will be described as follows: 
         [0050]    When the main switch S 1  switches on, the signal from node U is inputted to the sample and hold circuit  1 . When the main switch S 1  is in ON state, the sample and hold circuit  1  is in sample mode, and the output signal S_H_out of the sample and hold circuit  1  follows the electric current I_L of the inductor L; the synchronous detection circuit  5  is in OFF state, and the output signal Syn_out of the synchronous detection circuit  5  is at low level. 
         [0051]    At the end of the “ON” period of the main switch S 1 , the voltage V_F at the node F rises up, the main switch S 1  switches off, and the potential V_D at the main node D rises up; when the potential at the node D is close to the potential at the node C, the electric current I_L in the inductor will be discharged to the DC load  15  through the diode D 1 . The rising edge detection circuit  2  acts, and outputs the actuating signal to the timing control circuit  4 ; the timing control circuit  4  forces the sample and hold circuit  1  into hold mode; Then, voltage held in the sample and hold circuit  1  is proportional to the peak value of current in inductor L. Since the peak value of current in the inductor L is equal to the peak value of current in the diode D 1 , the output S_H_out of the sample and hold circuit  1  is proportional to the peak value of the current I_D 1  in diode D 1 . 
         [0052]    That signal will remain unchanged before the current I_L in inductor L decreases to 0, owing to the sample and hold circuit  1  is in hold mode in the period. At this point, the synchronous detection circuit  5  is in ON state, and the output S_H_out of the sample and hold circuit  1  is outputted to the low-pass filter  6  through the synchronous detection circuit  5 . As the current I_L in the inductor L is discharged to the DC load  15  through the diode D 1 , the current I_L in the inductor L decreases gradually. 
         [0053]    When the current I_L in inductor L decreases to “0”, the potential at the node D begin to drop; when the falling edge detection circuit  3  detects a voltage drop signal at the node D, it will act and output the actuating signal to the timing control circuit  4 , and the timing control circuit  4  will cut off the synchronous detection circuit  5  and thereby force the input signal of the low-pass filter  6  to “0”. In the ON-OFF cycle, the input signal average value output to the low-pass filter  6  is proportional to the average output current value in the cycle, i.e., the low-pass filter outputs a signal that is proportional to the output current I_avr average value. 
         [0054]    The voltage signal output from the low-pass filter  6  is fed into an error amplifier Err_amp together with an internally preset reference value; if the average output current is higher than the internally preset reference value, the output of the error amplifier Err_amp will decrease the ON time of the main switch S 1  slowly through the PWM controller U 1 ; if the average output current is lower than the internally preset reference value, the output of error amplifier Err_amp will increase the ON time of the main switch S 1  slowly through the PWM controller U 1 . Finally, the average output current value is regulateed to be equal to the internally preset reference value, and thereby constant current output control is achieved. 
         [0055]    At the end of the OFF period of the main switch S 1 , the main switch S 1  will switch on again, and the circuit will enter into the next cycle. 
         [0056]    When V_F is at low level, the main switch S 1  will switch on, and the terminal D 2 _QB of the D flip-flop DF 2  will output high level. The signal from the current sample resistor R 2  is input to the FET N 1  in the sample and hold circuit  1 . The sequence of the signal applied to the gate electrode of FET N 1  is synchronous with the driving signal of the main switch S 1 . When the main switch S 1  is in ON state, the control terminal CTL is at high level (inversed to V_F), and the sample and hold circuit  1  is in sample mode; at this point, the terminal D 1 _Q of the D flip-flop DF 1  in the timing control circuit  4  outputs high level, the terminal D 2 _QB of the D flip-flop DF 2  outputs high level, the FET N 4  in the synchronous detection circuit  5  gates on to the ground, the FET N 3  in the synchronous detection circuit  5  gates off, and the output of the synchronous detection circuit  5  is “0”. 
         [0057]    At the end of the ON period of the main switch S 1 , V_F changes into high level, the main switch S 1  switches off, the control terminal CTL changes into low level, the sample and hold circuit  1  enters into hold mode, the D flip-flop DF 1  resets, the output of the terminal D 1 _Q of the D flip-flop DF 1  is at low level, and the D flip-flop DF 2  is relieved from reset state. As the main switch S 1  switches off, the potential at point D above the main switch S 1  rises up; when the potential at the point D gets close to the potential at the point C, the rising edge detection circuit  2  acts, and the output of the amplifier A 2  increases and triggers the D flip-flop DF 2  in the timing control circuit  4 , the output of the terminal D 2 _QB decreases, and therefore the FET N 3  in the synchronous detection circuit  5  gates on, the FET N 4  in the synchronous detection circuit  5  gates off, and the output signal of the sample and hold circuit  1  is output to the input terminal of the low-pass filter circuit  6 . At this point, the current I_L in the inductor L is discharged to the DC load  15  and thereby decreases gradually. 
         [0058]    Referring to  FIG. 4 . In another preferred embodiment of the present invention, the N-channel FET N 1  in the falling edge detection circuit  3  in the current detection circuit  162  may be replaced with a diode D 3 . The positive electrode of the diode D 3  is connected with the non-inverting input terminal of the amplifier A 1 , and the negative electrode of the diode D 3  is grounded. 
         [0059]    The power conversion circuit in the present invention filters off the noise in the AC power supply through the filter circuit  12 , accomplishes AC-DC conversion through the rectifier circuit  13 , and regulates the power factor and regulates the average output current to equal to an internally preset value through the single-stage power conversion circuit  14 , and thereby achieves constant current output control. 
         [0060]    The above are only some preferred embodiments of the present invention, but not limit to the present invention. Any modification, equivalent replacement, and improvement made without departing from the spirit and principle of the present invention shall be deemed as falling into the protected scope of the present invention.