Abstract:
A pull-down circuit uses an npn transistor operating at close to saturation and the collector/emitter voltage is used as the pull-down voltage. To keep this within strict limits the npn transistor is connected in circuit with other transistors and resistors as well as a current source that generates a current proportional to absolute temperature. By selecting the values of the resistors and transistor parameters the collector/emitter voltage may be kept stable within a small range over wide temperature variation.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to bipolar junction transistor (BJT) circuits in which an output transistor is driven close to saturation.  
         BACKGROUND OF THE INVENTION  
         [0002]    CMOS (complementary metal oxide semiconductor) circuits require that the voltage of a signal be at either one of two predetermined voltage levels, one high and one low, typically 3.3 volts and 0 volts. However, output signals from BJT (bipolar junction transistor) circuits are usually at either of two values which differ from the predetermined levels required by the CMOS circuitry. Thus, in order for a BJT circuit to be coupled to a CMOS circuit these BJT values have to be pulled up to 3.3 volts and pulled down to 0 volts.  
           [0003]    Typically, it has been found that pull-up to 3.3 volts can be achieved easily but pull-down is problematic. Typically, pull-down is achieved by driving an npn transistor close to saturation and using the collector/emitter voltage, VCE, as the pull-down voltage. In practice, the pull-down voltage achieved falls in a range 0.1-0.75 volts above the predetermined CMOS low reference level. However, according to the CMOS specification the pull-down voltage must be less than 0.5 volts above the low reference level. Furthermore, to avoid saturation, the pull-down voltage should preferably be greater than 0.2 volts above the low reference level. Thus, the pull-down voltage should fall in a range 0.2-0.5 volts above the low reference level.  
           [0004]    There is clearly a discrepancy between the 0.2-0.5 volt range required for proper operation and the range 0.1-0.75 achieved in practice. If the pull-down voltage actually falls outside the 0.2-0.5 volt range the circuit would be considered unacceptable or failed.  
           [0005]    It is an object of the invention to obviate or mitigate this problem.  
         SUMMARY OF THE INVENTION  
         [0006]    According to one aspect of the invention there is provided a method of controlling the collector/emitter voltage of a bipolar junction transistor operating close to saturation comprising injecting a current which is proportional to absolute temperature parallel to the base emitter junction and selecting the values of certain circuit components connected to the transistor to provide a predetermined variation with temperature of the collector/emitter voltage.  
           [0007]    According to another aspect of the invention there is provided a method of controlling the collector/emitter voltage of a bipolar junction transistor operating close to saturation comprising injecting a current which is proportional to absolute temperature parallel to the base emitter junction and selecting the values of certain circuit components connected to the transistor to minimise the variation with temperature of the collector/emitter voltage.  
           [0008]    According to yet another aspect of the invention there is provided a circuit comprising first and second bipolar junction transistors each having a base, an emitter and a collector, at least two resistors, a voltage drop device and a current source arranged to generate a current iPTAT which is proportional to absolute temperature, wherein: the bases of the first and second transistors are connected together; the first resistor is connected across the base/emitter junction of the second transistor; the second resistor is connected across the base/collector junction of the first transistor; the current source is connected across the base/emitter junction of the first transistor; the emitters of the first and second transistors are both connected to a biasing voltage terminal; the collector of the first transistor is connected directly or indirectly to an input terminal; the voltage drop device is connected between the input terminal and the collector of the second transistor; and the values of at least the first and second resistors are selected to provide a predetermined variation with temperature of the voltage VCE across the collector/emitter of the second transistor. 
       
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 is a circuit diagram of a pull-down circuit according to one embodiment of the present invention;  
         [0010]    [0010]FIG. 2 is a circuit diagram of a pull-down circuit according to another embodiment of the present invention;  
         [0011]    [0011]FIG. 3 is a circuit diagram of a pull-down circuit according to yet another embodiment of the present invention.  
         [0012]    [0012]FIG. 4 is a circuit diagram of a typical bandgap reference circuit; and  
         [0013]    [0013]FIG. 5 is a sketch illustrating the response of the circuit of FIG. 4.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0014]    Referring to FIG. 1, three npn transistors Q 1 , Q 2  and Q 3  and three resistors R 1 , R 2  and R 3 , are connected together to form a pull-down circuit.  
         [0015]    More specifically, the base B 1  of first transistor Q 1  is connected to the base B 2  of second transistor Q 2 . Both of these bases are also connected to a first terminal  10  of first resistor R 1  and to a first terminal  12  of second resistor R 2 . A second terminal  14  of resistor R 1  is connected to the emitter E 1  of transistor Q 1  and to the emitter E 2  of transistor Q 2 . Thus, resistor R 1  is connected across the base/emitter junctions of both transistors Q 1  and Q 2 . Terminal  14  is also connected to a negative power supply voltage terminal -V.  
         [0016]    A second terminal  16  of resistor R 2  is connected to the collector C 1  of transistor Q 1  such that resistor R 2  can be said to be connected across the collector/base junction of transistor Q 1 . The second terminal  16  is also connected to one terminal  18  of third resistor R 3  the other terminal  20  of which is connected to an input voltage terminal  22 .  
         [0017]    The third transistor Q 3  is diode connected. That is to say its base B 3  is directly connected to its collector C 3 . The terminal  16  of resistor R 2  is also connected to the base and collector of transistor Q 3 . The collector C 2  of transistor Q 2  is connected to the emitter E 3  of transistor Q 3  and to an output voltage terminal  24 .  
         [0018]    Finally, a current source  26  is connected between the base B 1  and emitter E 1  of transistor Q 1 . The current source  26  is of a type which produces a current iPTAT which is directly proportional to the absolute temperature of the device. Such current sources are well known and can for example take the form of a bandgap reference circuit. A typical example of which is shown in FIG. 4.  
         [0019]    Referring to FIG. 4, it is known that the bandgap voltage  
             Vbg   =     VbeQ7   +       m   RPTAT        Vt               (   1   )                               
 
         [0020]    Where m is a constant, RPTAT is the value of resistor RPTAT, VbeQ 7  is the base/emitter voltage of transistor Q 7  and Vt is the temperature voltage obtained from  
             Vt   =     kT°   q             (   2   )                               
 
         [0021]    where k is Boltzmann Constant, q is electron charge and T o  is absolute temperature in ° Kelvin.  
         [0022]    It is known also that equation (1) can be represented graphically as shown in FIG. 5.  
         [0023]    It is known also that the collector current of transistor Q 8 ,  
             iPTAT   =     mVt   RPTAT             (   3   )                               
 
         [0024]    The operation of the circuit of FIG. 1 will now be analysed in terms of the output voltage VO obtained at output terminal  24  when a voltage VI present on input terminal  22  is at a high level and Q 2  is on and operating close to saturation.  
         [0025]    Voltage VI in terminal  22  gives rise to a voltage VA at terminal  18  of resistor R 3 .  
         [0026]    It can be readily understood that:  
           VA=VbeQ 1+ VR 2   (4)  
         [0027]    and  
           VO=VA—VbeQ 3   (5)  
         [0028]    where VbeQ 1  and VbeQ 3  respectively indicate the base/emitter voltage of transistor Q 1  and the base/emitter voltage of transistor Q 3 .  
         [0029]    Substituting VA from equation (4) into equation (5) gives  
           VO=VCEQ 2= VbeQ 1+ VR 2— VbeQ 3   (6)  
         = VbeQ 1— VbeQ 3+ VR 2;   (7)  
         [0030]    It can also readily be understood that:  
             VR2   =     R2                   (     iPTAT   +     VbeQ1   R1       )               (   8   )                               
 
         [0031]    Substituting VR2 from equation (8) into equation (7) gives  
             Vo   =     VbeQ1   -   VbeQ3   +   R2iPTAT   +       R2   R1        VbeQ1               (   9   )                               
 
         [0032]    Substituting IPTAT from equation (3) into equation (9) gives  
             Vo   =     VbeQ1   -   VbeQ3   +       R2   R1        VbeQ1     +       R2                 mVt     RPTAT               (   10   )                               
 
         [0033]    It is known from basic transistor theory that the ratio of the currents i 1  and i 3  flowing through the collectors (or emitters assuming the base current is negligible) of two transistors Q 1  and Q 3  which are identical except that they have different sizes of area A 1  or A 3  of the emitter/base junction can be expressed  
               i1   i3     =       A1   A3               (       VbeQ1   -   VbeQ3     Vt     )                 (   11   )                               
 
         [0034]    Where Vt is the temperature voltage and this derives to  
               VbeQ1   -   VbeQ3     =       -   Vt                   ln             i3A1   i1A3                    (   12   )                               
 
         [0035]    Substituting for VbeQ 1 -VbeQ 3  in equation (10) gives  
             Vo   =         -   Vt                   ln             i3A1   i1A3            +       R2   R1        VbeQ1     +     m      R2                   mVt   RPTAT                 (   13   )               =         R2   R1        VbeQ1     +     Vt                   (       mR2   RPTAT     -     ln                        i3A1   i1A3              )                 (   14   )                               
 
         [0036]    Let  
       R2   R1                         
 
         [0037]    be represented by A and let  
         mR2   RPTAT     -     ln                   i3A1   i1A3                             
 
         [0038]    be represented by B.  
         [0039]    Then equation (14) may be written  
           VO=AVbeQ 1+ BVt    (15)  
         [0040]    It is noted that equation 15 is of the same form as equation (1) describing the operation of the bandgap reference circuit. Thus, considering FIG. 5, A is equivalent to a negative temperature coefficient and B a positive temperature coefficient.  
         [0041]    To find A and B for VO=0.3 volts , for example, and VO to be independent of T o  we try to obtain these values near room temperature (300° K.) because if true at all temperatures it is true at 300° K.  
         [0042]    Substituting VO=0.3 in equation (15) gives  
           AVbeQ 1+ BVt= 0.3   (16)  
         [0043]    At T o =300 it is known from FIG. 5 that  
               AVbeQ1   BVt     ≈   0.2           (   17   )                               
 
         [0044]    At T o =300°, VbeQ 1 =0.83 V and Vt=0.026 V.  
         [0045]    Inserting these values in equations (16) and (17) allows us to find values for A and B.  
         [0046]    Looking again at  
         B   =       mR2   RPTAT     -     ln                        i3A1   i1A3                ,                         
 
         [0047]    we know  
       i3   i1                         
 
         [0048]    =current gain of the current mirror created by Q 1  and Q 2  and as a result  
         i3   i1     =       iQ2   iQ1     =     A2   A1                             
 
         [0049]    Substituting  
       A2   A1                         
 
         [0050]    for  
       i3   i1                         
 
         [0051]    in the value for B we get  
             B   =       mR2   RPTAT     -     ln                        A2   A3                      (   19   )                               
 
         [0052]    and as previously defined  
             A   =     R2   R1             (   20   )                               
 
         [0053]    As we have determined the values of A and B to give VO=0.3 volts we can then determine from equations (19) and (20) the values of R 1 , R 2 , A 2  and A 3  necessary to achieve VO=0.3 volts irrespective of temperature.  
         [0054]    It should be noted that matching by locating components in close proximity, using similar physical dimensions etc. should be attempted with respect to all of the transistors Q 1 , Q 2  and Q 3  and also matching of the transistors R 1 , R 2  and RPTAT should be carried out for optimum temperature stability.  
         [0055]    Referring now to FIG. 2, this is a modification of the FIG. 1 embodiment in which the single diode connected transistor Q 3  is replaced by two or more diode connected transistors Q 3  connected such that the emitter of one is connected to the collector/base of the following one.  
         [0056]    With reference to FIG. 3, this circuit is similar to the circuit of FIG. 1 except that a fourth transistor Q 4  is provided as a current mirror with respect to transistor Q 3 . Thus, the emitter of transistor Q 4  is connected to the collector of transistor Q 1  and the diode connected collector/base is connected to input resistor R 3  as well as to the base/collector of transistor Q 3 . In this embodiment, while R 2  is still connected across the collector/base junction of transistor Q 1 , the end  16 ′ of resistor is no longer connected to the base/collector of transistor Q 3 .  
         [0057]    It is noted that each of the single transistors Q 3  and Q 4  could be replaced with a series of identical transistors in the manner of FIG. 2.  
         [0058]    Although the invention has been described with reference to a pull-down circuit it should not be limited to such use. The invention may be used in any circuit where low output voltage may be expected such as in a current mirror circuit or where high voltage swings may be expected such as the output stage of an amplifier.  
         [0059]    The circuits of FIGS.  1  to  3  are, in essence, current mirror circuits in which the output voltage is switched between high and low. Without such switching the circuit would be recognised as a current mirror rather than a pull-down circuit.  
         [0060]    Furthermore, although the invention has been described in terms of npn transistors the invention could also be used with pnp transistors with appropriate positive biasing voltage replacing voltage terminal V-.  
         [0061]    As another modification, the preferred embodiment as shown in FIG. 1 uses a diode connected transistor Q 3  to provide a necessary voltage drop Vbe. However, it is envisaged that the voltage drop could conceivably be obtained using a single diode or resistor (or some other combination of components) instead of transistor Q 3 . Generally such a device is refined to hereinafter as a voltage drop device.  
         [0062]    The invention was conceived primarily to provide a stable output voltage but the invention could be used to provide a predetermined positive or negative change in voltage with temperature.