Abstract:
The present invention generally relates to a capacitor of a semiconductor device and a method of manufacturing such capacitors that improve the processing yield and the reliability of device operation by forming the plate electrode from a p-type polysilicon, thereby improving device resistance to write operation failures resulting from concentration of holes in the plate electrode terminal during a data write operation.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention generally relates to a capacitor of a semiconductor device and a method for manufacturing such capacitors that improves the reliability of processing yield and device operation by forming a plate electrode with p-type polysilicon layer and thereby preventing a write operation failure resulting from concentration of holes in the plate electrode terminal during a data write operation.  
           [0003]    2. Description of the Prior Art  
           [0004]    Recently, it has become more difficult to form a capacitor with sufficient capacitance due to reductions in cell size resulting from increasingly high integration levels in semiconductor devices.  
           [0005]    Particularly in Dynamic Random Access Memory ‘DRAM’ devices consisting of a MOS transistor and a capacitor, it is important to fabricate a capacitor, which typically occupies the majority of the space in each memory cell, that has a large capacitance but uses as little space as possible.  
           [0006]    Currently, capacitors having a polysilicon conductor typically use an oxide film, a nitride film or stacked layers thereof, such as an oxide-nitride-oxide ‘ONO’ structure, as a dielectric layer.  
           [0007]    In order to increase capacitance, determined by the equation:  
           (ε 0 ×ε r ×A)/T  
           [0008]    (where ε 0  is the permittivity of free space, ε r  is the dielectric constant of the dielectric film, A is the surface area of the capacitor, and T is the thickness of the dielectric film), the general practice has been to use dielectric materials with a high dielectric constant, reduce the thickness of dielectric film; and/or increase the effective surface area of the capacitor.  
           [0009]    However, each of these methods has problems. First, it is difficult to implement a device using a dielectric with a high dielectric constant such as Ta 2 O 5 , TiO 2 , or SrTiO 3  to production devices since the reliability and the characteristics of the thin film, such as a junction breakdown voltage of Ta 2 O 5 , TiO 2 , or SrTiO 3  are not reliably known. The method of reducing the thickness of a dielectric film has a problem of deteriorating the reliability of a capacitor since the dielectric film is more easily destroyed during the device operation.  
           [0010]    In order to increase a surface area of the capacitor, capacitors have been formed as multilayer structures of polysilicon layers that are penetrated and connected to act as fin structures or by forming a storage electrode in the shape of an open cylinder in the upper part of contact. However, if the height of a capacitor is increased, subsequent processing becomes difficult due to the stepped topography and obtaining high capacitance becomes difficult due to the decreased surface area of the device available to form such structures in highly integrated DRAMs.  
           [0011]    A design in which the number of cells is more than twice that of the conventional cells per bit line has been used to increase the capacitance of cell capacitor in order to improve cell efficiency. However, since the available surface area for a capacitor is decreased, conventional fin or cylinder type capacitors typically attempt to increase the effective surface area by increasing the height of a capacitor, decreasing the gap between storage electrodes, or using hemispherical grain ‘HSG’ silicon.  
         SUMMARY OF THE INVENTION  
         [0012]    The present invention overcomes the above-mentioned problems of the prior art and provides a capacitor for semiconductor devices and method of manufacturing such capacitors that improves the operational characteristics of the resulting devices, by making holes the main carriers and concentrating them at the ends of the plate electrodes, thereby preventing decreased capacitance when 0V is applied to a storage electrode and +V cc /2 to a plate electrode during a “0” data write.  
           [0013]    The present invention is also characterized in forming the p-type polysilicon layer by one of a variety of doping methods including doping an initially undoped polysilicon layer by ion-implanting B or BF 2 ; by making B 2 H 6 , BF 3  or BCl 3  react with O 2  to form a B-doped oxide on the polysilicon layer and then diffusing B from the oxide into a polysilicon layer; by coating and diffusing liquid source BBr 3  or (CH 2 O) 3 B; or by making B 2 H 6 , BF 3  or BCl 3  react with SiH 4  or Si 2 H 6  in a CVD chamber to produce B-doped polysilicon. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The objects and aspects of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings in which:  
         [0015]    [0015]FIG. 1 a  is a cross-sectional view illustrating a conventional method of forming an electrode of a capacitor.  
         [0016]    FIG  1   b  is a cross-sectional view illustrating another conventional method of forming an electrode of a capacitor.  
         [0017]    [0017]FIGS. 2 a  and  2   b  are cross-sectional views illustrating depletion and accumulation states in the conventional capacitor.  
         [0018]    [0018]FIG. 3 is a cross-sectional view illustrating a “1” data write operation of a conventional capacitor.  
         [0019]    [0019]FIG. 4 is a cross-sectional view illustrating a “0” data write operation of a conventional capacitor.  
         [0020]    [0020]FIG. 5 is a graph illustrating capacitance according to a bias voltage of the conventional capacitor.  
         [0021]    [0021]FIG. 6 is a cross-sectional view illustrating a capacitor in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    Generally, a storage electrode and a plate electrode are formed of an n-typed polysilicon layer doped with phosphorus ‘P’.  
         [0023]    [0023]FIG. 1 a  is cross-sectional view illustrating a conventional capacitor electrode and FIG. 1 b  is a cross-sectional view illustrating another conventional capacitor electrode. FIG. 2 a  and FIG. 2 b  are cross-sectional views illustrating depletion and accumulation phenomena of the conventional capacitor.  
         [0024]    [0024]FIG. 1 a  is a conventional method of forming an electrode of a capacitor. A undoped polysilicon layer  10  is formed and then a P 2 O 5  film  12  is formed on the polysilicon layer  10  by exposing the polysilicon layer  10  to a gaseous doping source in a diffusion chamber. P of the P 2 O 5  film is diffused into the polysilicon layer, forming an n-typed polysilicon layers, and then the P 2 O 5    12  is removed.  
         [0025]    Here, a gas mixture of POCl 3  and O 2  is used as the doping source.  
         [0026]    [0026]FIG. 1 b  illustrates another conventional method of forming an electrode of a capacitor. By performing Chemical Vapor Deposition process using a gas mixture of either SiH 4  and PH 3  or Si 2 H 6  and PH 3  or a combination thereof, a P-doped polysilicon layer  14  is formed.  
         [0027]    As shown in FIG. 2 a , an electrode of a capacitor  20  formed by the conventional method comprises a storage electrode  22  which is an n-type polysilicon layer, the main carrier of which is an electron, a plate electrode  24  separated by a dielectric film  26 . When a positive (+) voltage is applied to the storage electrode  22 , a depletion of the main carrier occurs and a depletion region  28  is formed. Also, as shown in FIG. 2 b , when a positive voltage is applied to the plate electrode  24 , an electron accumulation occurs and an accumulation region  30  is formed.  
         [0028]    These characteristics of an operation of a capacitor are as follows: FIG. 3 is a cross-sectional view illustrating a “1” data write operation of the conventional capacitor, FIG. 4 is a cross-sectional view illustrating a “0” data write operation, and FIG. 5 is a capacitance graph in accordance with a bias voltage of the conventional capacitor.  
         [0029]    First, when storing a data “1” in a capacitor  20 , 0V is applied to a storage electrode  22  and—V ss /2 to a plate electrode  24 , and, as shown in FIG. 3, more depletion occurs closer to the interface of the storage electrode  22  and the dielectric  26 . When storing a data “0” in the capacitor  20 , 0V is applied to the storage electrode  22  and +V cc /2 to the plate electrode  24 . As a result, as shown in FIG. 4, a depletion region  28  is formed close to the interface of the plate electrode  24  with the dielectric  26 .  
         [0030]    As described above, when the impurity concentration is not fully saturated, the depletion phenomenon is intensified as the voltages applied to electrodes increase in electrodes of capacitor formed by the conventional method. As shown in FIG. 5, when the amount of the impurity dose is small, the desired capacitance of approximately 25 fF cannot be obtained and write operation failures occur. There is a limit in increasing the amount of doping in order to prevent the depletions mentioned above.  
         [0031]    Because the lower storage electrode is formed with a higher aspect ratio during manufacturing process of plate electrodes, phosphorus, with its relatively lower turnover rate compared to Si, cannot move fully into the inside of the electrode, thereby decreasing doping concentration of electrodes actually formed.  
         [0032]    The problem described above cannot be overcome since the aspect ratio increases are necessary to maintain capacitance as devices become smaller and the distance between storage electrodes decreases.  
         [0033]    Hereafter, a capacitor of a semiconductor device and manufacturing method for the same will be explained in detail referring to the attached drawings.  
         [0034]    [0034]FIG. 6 is a cross-sectional view of a capacitor formed in accordance with the present invention. A capacitor comprises a storage electrode  42  formed of an n-type polysilicon layer, a plate electrode  44  formed of a p-type polysilicon layer separated by a dielectric film  46 .  
         [0035]    Since the main carriers of plate electrode  44  are holes as a result of forming plate electrode  44  of the capacitor  40  from a p-type polysilicon layer, holes are concentrated on the ends of the plate electrode and a capacitance does not decrease when 0V is applied to a storage electrode and +V cc /2 to a plate electrode during the write operation of data “0” write to the capacitor. As a result, the reliability of “0” data write operation is improved.  
         [0036]    The p-type polysilicon layer is formed by doping B on a undoped polysilicon layer through ex-situ or in-situ methods.  
         [0037]    As an example of ex-situ method, there is provided a first method of ion-implanting B or BF 2  after forming an undoped polysilicon layer.  
         [0038]    There is provided a second method of forming an oxide film doped with B on the surface of the polysilicon layer by reacting B 2 H 6 , BF 3  or BCl 3  with O 2 , and then diffusing B from oxide film into the polysilicon layer.  
         [0039]    There is provided a third method for coating a liquid source such as BBr 3  or (CH 2 O) 3 B on the surface of a undoped polysilicon layer and then diffusing B into the polysilicon layer.  
         [0040]    Also, there is provided an in-situ method of forming a p-type polysilicon layer doped with B by reacting B 2 H 6 , BF 3  or BCl 3  with SiH 4  or Si 2 H 6  in a CVD device.  
         [0041]    As is apparent from the above description, in accordance with the present invention, a capacitor of a semiconductor device and manufacturing method for the same is provided by forming a plate electrode from a B-doped polysilicon layer, applying 0V to a storage electrode and +V cc /2 to a plate electrode when “0” data is written, thereby preventing holes, which are the main carriers in the plate electrode, from being concentrated on the ends of plate electrode. Accordingly, it is possible to prevent the degradation of capacitance, and improve processing yield, and improve the reliability of device operation.