Abstract:
A semiconductor memory device includes a substrate, a first diffusion region composed of at least one longitudinal and continuous source region which is disposed on the substrate and commonly used for a plurality of memory transistors, and a second diffusion region composed of at least one longitudinal and continuous drain region which is disposed in parallel with the first diffusion region and commonly used for the plurality of memory transistors. A refractory metal film is disposed on each of the first and second diffusion regions. An electric insulation film is disposed on the refractory metal film. A plurality of parallel gate electrodes are disposed crossing over the first and second diffusion regions. And a gate oxide film is arranged to electrically insulate the gate electrodes from the diffusion regions.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a continuation-in-part of application Ser. No. 07/800,746 filed Nov. 29, 1991, abandoned, which in turn is a continuation of application Ser. No. 07/554,665 filed on Jul. 17, 1990 abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device and a method for producing the memory device. 
     2. Description of the Related Art 
     In general, a MOS type semiconductor integrated circuit device is fabricated in such a way that a field oxide film is formed to isolate the device and that the source region and the drain region are formed by a self-aligning method using a gate electrode as a mask and implanting impurities into the substrate. The source region and the drain region have to be contacted together through one or two contacts for one transistor. This results in a disadvantage that the integration density is lowered depending on the contact margin of the regions and the wiring pitch thereof. 
     To cope with this problem, a semiconductor integrated circuit device having a planar cell structure is proposed (see Japanese Patent Application Laying Open (KOKAI) Nos .61-288464 and 63-96953). 
     In accordance with the planar cell structure, a continuous diffusion area as a common source region for a plurality of MOS transistors and a continuous diffusion area as a common drain region for a plurality of MOS transistors are formed on a substrate in parallel to each other. Also, on the substrate are formed gate electrodes which crossover both of the source and drain diffusion areas through an insulation film. 
     Due to the planar cell structure mentioned above, it becomes unnecessary to provide a field oxide film for device isolation and also it becomes possible to use one common contact for several or more transistors since each of the source diffusion area and the drain diffusion area is commonly used for a plurality of transistors, which makes it possible to achieve a high integration density of the device. 
     In accordance with a method for producing the planar cell structure memory device, the device is fabricated in such a way that, first, on a substrate are formed a field oxide film, diffusion areas for source and drain of the memory region, a gate oxide film and a gate electrode made from polycrystalline silicon (polysilicon). After that, a resist pattern having openings in a core portion (channel region) of the memory transistor is formed in accordance with the data to be written. After that, ions are implanted to raise the threshold voltage of the transistor so that the transistor is not turned on at a level of the value of the gate voltage for reading the data. 
     However, the above-mentioned planar cell structure has a disadvantage that the diffusion resistance becomes large since the bit line is elongated in the longitudinal diffusion region, which lowers the functional speed of the transistor. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a semiconductor memory device having a planar cell structure in which the functional speed thereof is heightened. 
     Another object of the present invention is to provide a method for producing the high speed semiconductor memory device having the planar cell structure. 
     The object of the invention can be achieved by a semiconductor memory device comprising: a first diffusion region for source regions of a plurality of memory transistors formed on a substrate; a second diffusion region for drain regions of a plurality of transistors, the second diffusion region being formed in parallel with the first diffusion region on the substrate; a silicide film formed on the first and second diffusion regions; an insulation film formed on the silicide film, the insulation film being thicker than a gate oxide film; and a gate electrode crossing over the first and second diffusion regions and being insulated from the diffusion regions. 
     Also, the object of the invention mentioned above can be achieved by a method for producing the semiconductor memory device comprising steps of: (A) forming a silicon nitride film on a semiconductor substrate through a buffer oxide film and patterning the silicon nitride film so that the film has openings in a first diffusion region for source regions of a plurality of memory transistors and in a second diffusion area for drain regions of a plurality of memory transistors; (B) implanting impurities into the substrate using the patterned silicon nitride film as a mask; (C) removing the buffer oxide film in the openings of the patterned silicon nitride film and after that depositing a refractory metal film; (D) forming a silicide film by a thermal treatment; (E) removing the unreacted refractory metal film by etching; (F) filling the openings of the pattern of the silicon nitride film with an insulation material other than silicon nitride; (G) removing the silicon nitride film; (H) removing the buffer oxide film; (I) forming a gate oxide film; and (J) depositing a polysilicon film and patterning the film to form gate electrodes. 
     An advantage of the above mentioned semiconductor memory device of the present invention is that, due to the structure that the silicide film is formed along the longitudinal diffusion region which functions as a bit line, the resistance of the bit line is lowered compared to the structure that only the diffusion region is formed without the silicide film. 
     Another advantage of the memory device of the present invention is that the capacity between the bit line and the word line (gate electrode) can be reduced due to the arrangement of the insulation film which is thicker than the gate oxide film and disposed between the bit line and the word line which crossovers the bit line. 
     Still another advantage of the memory device of the present invention is that it becomes possble to avoid increasing the junction capacitance of the bit line due to the arrangement of the thick insulation film disposed between the bit line and the word line so that the core ions are prevented from being implanted into the bit line at the time of ion implantation process. 
     Therefore, it becomes possible to achieve a high speed function of the memory device. 
     Further objects and advantages of the present invention will be apparent from the following description of the preferred embodimemts of the invention as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1a is a plan view of a memory device in accordance with an embodiment of the present invention; 
     FIG. 1b is a sectional view of the memory device of FIG. 1a taken along the line B-B&#39; of FIG. 1a; 
     FIG. 1c is a sectional view of the memory device of FIG. 1a taken along the line C-C&#39; of FIG. la; and 
     FIGS. 2a to 2h are explanatory views for explaining an embodiment of the method for producing the memory device of the present invention and representing the sections of the device in series in the order of different steps of the method, respectively. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIGS. 1a to 1c illustrate an embodiment of the present invention. FIG. 1a is a plan view. FIGS. 1b and 1c are sectional views of the device taken along the lines B-B&#39; and C-C&#39; of FIG. 1a, respectively. Note that the scales of the drawings are not strictly the same. 
     Numeral 2 designates a P-type silicon substrate. In the illustration of FIG. 1a, two source regions 4s and a drain region 4d are formed on the substrate 2. Each region is formed in a form of continuous strip. The regions are in parallel to each other. The regions 4s and 4d are made by N 30   diffusion regions commonly used for a plurality of memory transistors. A refractory metal silicide film 6 is formed on each of the diffusion regions 4s and 4d. On the silicide film 6 is formed a thick oxide film 8 made from PSG (Phospho-Silicate Glass), for example. The surface of the substrate 2 in the portion uncovered by the silicide film 6 is covered by a gate oxide film 10 instead. 
     Gate electrodes (word lines) 12 made of polysilicon are formed on the substrate 2 through the gate oxide film 10 or the thick oxide film 8 in the direction perpendicular to the longitudinal direction of the diffusion regions 4s and 4d. 0n each of the word lines 12 is formed a refractory metal silicide film 14. Numeral 16 designates an insulation film to cover the layered structure. 
     The diffusion regions 4s and 4d are alternately arranged in the order of the source region 4s, the drain region 4d, the source region 4s . . . . . . . The numeral 18 designates a contact. 
     In FIG. 1a, each of the regions 20a and 20b defined by dash lines represents one memory transistor. The ROM code of each transistor is determined from the threshold voltage which depends on whether the core ions are implanted into its channel region in the substrate or not. In this particular embodiment, it is assumed that the core ions are not implanted into the channel region of the transistor 20a while the ions are implanted into the channel region of the transistor 20b. Under this assumption, when the word line 12 of the transistor 20a is selected and supplied with voltage, current flows from the bit line (drain diffusion region 4d) to the source region 4s. On the other hand, when the word line 12 of the transitor 20b is selected and supplied with voltage, current does not flow from the bit line 4d to the source region 4s . Due to such a functional arrangement, it becomes possible to read the ROM code of the transistor by a sensor circuit connected to the bit line 4s. 
     FIGS. 2a to 2h illustrate sectional views of the memory device in sequence in different steps of a method for producing the memory device in accordance with one embodiment of the present invention. 
     (A) FIG. 2a illustrates a step of forming a buffer oxide film 30 to a thickness of about 250 Å on a P-type silicon substrate 2 by a thermal oxidation process. After that, a silicon nitride film 32 is deposited on the film 30 to a thickness of about 2500 to 3000 Å. 
     (B) FIG. 2b illustrates a step of coating the film 32 with a resist 34. The resist 34 is patterned by a photolithographic process to have openings in the portions for forming the source region and the drain region of the memory transistor. 
     After that, the film 32 is etched to form a pattern with the use of the resist pattern 34 as a mask. 
     After that, ions of phosphorus (P + ) or arsenic (As + ) are implanted into the substrate 2 through the buffer film 30. The implantation energy of the ions is more than 100KeV. 
     (C) FIG. 2c illustrates a step of removing the resist 34 and the buffer film 30 in the openings of the pattern of the silicon nitride film 32. After that, a refractory metal film 36 such as Ti (titanium) or W (tungsten) is deposited over the substrate 2 and the patterned film 32 by a sputtering process or a CVD process. The thickness of the film 36 is 500 to 10,000 Å. In this particular embodiment, the thickness is 600 Å. 
     (D) FIG. 2d illustrates a step of thermal treatment of the layered structure for 15 to 20 minutes at a temperature of about 950° C. By this treatment, the impurities (ions) implanted into the substrate 2 are activated and form a source region 4s and a drain region 4d, respectively. At the same time, a silicide film 6 is formed in each opening as a result of reaction between the deposited refractory metal film 36 and the silicon substrate 2 in this thermal treatment. 
     After that, the unreacted film 36 is etched away remaining the silicide film 6 in each opening. The film 36 may be etched either by a wet etching process or a dry etching process, known per se. 
     (E) FIG. 2e illustrates a step in which a silicon oxide film 8 such as PSG is deposited to a sufficient thickness to fill the openings of the film 32 by an appropriate method such as a CVD method. For example, the thickness of the film 8 is about 1 μm. 
     (F) FIG. 2f illustrates a step in which the film 8 is etched away from the surface of the film 32 by an etch back method to form a state that the openings of the film 32 are filled with the film 8. The etch back process may be conducted in such a way that the whole area is eched without applying any treatment of the surface of the film 8 after the deposition thereof. Or otherwise, it may be conducted in such a way that the whole area is etched after the surface of the film 8 is flattened by coating the surface with an insulation film such as SOG (Spin on Glass) under the condition that the etching speed of the film 8 is equal to that of the insulation film. 
     (G) FIG. 2g illustrates a step of removing the silicon nitride film 32 by etching. After the film 32 is etched away, the buffer film 30 deposited under the film 32 is removed by a silicon oxide etching process. In this process of etching the film 30, the silicon oxide film 8 deposited on the silicide film 6 is also etched by the same thickness as the film 30. 
     (H) FIG. 2h illustrates a step of forming a gate oxide film 10 to a thickness of 100 to 500 Å (200 Å in this particular embodiment) on the substrate 2 and the film 8. After that, a polysilicon film 12 is deposited on the film 10 to a thickness of 1000 to 5000 Å (2000 Å in this particular embodiment). 
     After that, a refractory metal such as Ti or W is deposited on the film 12 by a sputtering method or a CVD method. The refractory metal is heated to form a silicide film 14 on the film 12. 
     After that, the films 12 and 14 are patterned to form a word line (gate electrode) by a photolithographic process and an etching process. 
     After that, an insulation film for isolating the layers is formed, which is followed by forming processes of contact holes, metal wirings and a passivation film. 
     The core implantation process for determining the ROM code is carried out after the word lines are formed in the step (H), mentioned above. 
     The above mentioned embodiment of the invention is explained with regard to the N-channel MOS transistor. However, the invention is not limited to that type of transistor but can be applied to a P-channel MOS transistor as well. 
     Furthermore, in the memory device according to the present invention, polysilicon may be used for silicon substrate 2 in the step (A) mentioned above. In this case, the refractory metal film 36 deposited on the surfaces of the substrate 2 reacts with the polysilicon constituting the substrate 2 to thereby form polycide films 6, when subjected to the thermal treatment in the step (D). 
     As mentioned above, in accordance with the memory transistor having the planar cell structure according to the present invention, due to the arrangement of the silicide film formed on each of the source diffusion region and the drain diffusion region, the resistance of the bit lines made from the source region and the drain region can be lowered. For example, it becomes possible to reduce the resistance to about 1/10 or less of the structure in which the bit lines are made only from the diffusion regions without provision of the silicide films. 
     Also, the capacitance between the bit line and the word line is lowered since a thick insulation film is disposed therebetween. 
     Further, it becomes possible to avoid the increase of junction capacitance of the bit line since the core ions are hardly implanted into the bit lines due to the arrangement of the thick insulation film disposed between the word line and the bit line. 
     Therefore, it becomes possible to heighten the functional speed of the memory device of the planar cell structure. 
     It is to be noted that in the memory device according to the present invention, instead of the silicide film 6 disposed on each diffusion region, a refracrory material may be arranged without thermal treatment. 
     In that case, the memory device is produced in such a way that ions are implanted into the substrate and thereafter diffused therein by a thermal treatment of the substrate, after that the buffer oxide film 30 in the openings of the mask (silicon nitride film 32) is removed, and after that a refractory matal is deposited on the diffusion region exposed in each of the openings by an appropriate method. After that, a thick silicon oxide film 8 is formed on the refractory metal. After that, the gate oxide film 10 and the gate electrodes 12 are formed in the same way as described with reference to FIGS. 2g and 2h. On each of the electrodes 12 may be deposited a refractory metal instead of the silicide film 14. 
     Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.