Abstract:
A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

Description:
BACKGROUND 
       [0001]    Technical Field 
         [0002]    The present disclosure relates to a normally-off transistor with reduced ON-state resistance and to a method for manufacturing the transistor. 
         [0003]    Description of the Related Art 
         [0004]    Known to the art are high-electron-mobility transistors (HEMTs) with a heterostructure, made in particular of gallium nitride (GaN) and gallium and aluminum nitride (AlGaN). For instance, HEMT devices are appreciated for use as power switches thanks to their high breakdown threshold. Furthermore, the high current density in the conductive channel of the HEMT enables a low ON-state resistance (R ON ) of the conductive channel to be obtained. 
         [0005]    To favor use of HEMTs in high-power applications, HEMTs with normally-off channel have been introduced. HEMT devices with recessed-gate terminal have proven particularly advantageous for use as transistors with normally-off channel. A device of this type is, for example, known from Wantae Lim et al., “Normally-Off Operation of Recessed-Gate AlGaN/GaN HFETs for High Power Applications”, Electrochem. Solid-State Lett. 2011, volume 14, issue 5, H205-H207. 
         [0006]    This HEMT has a gate trench that extends in depth in the heterostructure to the GaN layer. Extending in said trench is the gate metallization, which is separated from the AlGaN/GaN layers that form the heterostructure by a gate-dielectric layer. Formation of the gate trench is obtained by known steps of chemical etching and generates morphological defectiveness of various nature, such as for example even extensive surface corrugations or in general damage generated by the etching process (such as depressions or protuberances). 
         [0007]    The document No. U.S. Pat. No. 8,330,187 discloses a MOSFET with AlGaN/GaN heterojunction which has a recessed-gate terminal that extends in depth in a semiconductor body. The semiconductor body has, underneath the heterojunction, a GaN layer with a doping of a P-type, having the function of channel layer. Since the channel layer has a doping of a P-type, it makes it possible to obtain, in use, a transistor of a normally-off type with high turn-on threshold voltage. The gate terminal extends as far as the channel layer, and terminates within the channel layer itself. When, in use, the voltage applied to the gate terminal generates a charge-carrier inversion in the channel layer, a conductive channel is set up in the channel layer, which enables flow of a current between the source and drain terminals. However, the present applicant has found that the device according to U.S. Pat. No. 8,330,187 has a high ON-state resistance due to the fact that the conductive channel is formed, for the most part, within the channel layer. 
       BRIEF SUMMARY 
       [0008]    At least some embodiments provide a transistor of a normally-off type that enables a good trade-off between high threshold voltage and reduced ON-state resistance for overcoming the drawbacks of the known art. 
         [0009]    According to at least some embodiments of the present disclosure a transistor of a normally-off type includes: 
         [0010]    a semiconductor body lying in a plane and including a buffer region and a heterostructure extending over the buffer region; 
         [0011]    a gate recessed electrode extending in the semiconductor body at least partially through the buffer region, along a direction orthogonal to the plane; 
         [0012]    a first working electrode and a second working electrode, which extend at respective sides of the gate electrode; and 
         [0013]    an active area which extends in the buffer region alongside and underneath the gate electrode and is configured to house, in a first operating condition in which a voltage between the gate electrode and the first working electrode is higher than a threshold voltage, a conductive path for a flow of an electric current between the first and second working electrodes. 
         [0014]    The active area in the buffer region houses a resistive region configured to hinder, in a second operating condition in which the voltage between the gate electrode and the first working electrode is lower than the threshold voltage, the electric current flow between the first and second working electrodes. The resistive region extends at least in part in said active area, and said gate electrode extends in the semiconductor body to a depth, in said direction, equal to, or greater than, a maximum depth reached by the resistive region. 
         [0015]    According to at least some embodiments of the present disclosure a method for manufacturing a normally-off transistor includes: 
         [0016]    forming a recessed gate electrode in a semiconductor body extending in a plane and including a buffer region and a heterostructure, the gate electrode extending at least partially through the buffer region, along a direction orthogonal to the plane; 
         [0017]    forming a first working electrode and a second working electrode at respective sides of the gate electrode, wherein the gate electrode, and the first and second working electrodes define an active area in the buffer region alongside and underneath the gate electrode, said active area being configured to house, in a first operating condition in which a voltage between the gate electrode and the first working electrode is higher than a threshold voltage, a conductive path for a flow of electric current between the first and second working electrodes; and 
         [0018]    forming a resistive region at least in part in the active area in said buffer region, said gate electrode extending in the semiconductor body as far as a depth, in the direction, equal to, or higher than, a maximum depth reached by the resistive region, the resistive region being configured to hinder, in a second operating condition in which the voltage between the gate electrode and the first working electrode is lower than the threshold voltage, the flow of electric current between the first and second working electrodes. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0019]    For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein: 
           [0020]      FIG. 1  shows, in lateral section, a HEMT according to one embodiment of the present disclosure; 
           [0021]      FIG. 2  shows, in lateral section, a HEMT according to a further embodiment of the present disclosure; 
           [0022]      FIG. 3  shows, in lateral section, a HEMT according to a further embodiment of the present disclosure; 
           [0023]      FIG. 4  shows, in lateral section, a HEMT according to a further embodiment of the present disclosure; 
           [0024]      FIG. 5  shows, in lateral section, a HEMT according to a further embodiment of the present disclosure; and 
           [0025]      FIGS. 6A-6E  show steps for manufacturing the HEMT of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0026]      FIG. 1  shows, in a triaxial system of orthogonal axes X, Y, Z, a HEMT device  1  of a normally-off type, based upon gallium nitride, including: a substrate  2 , made, for example, of silicon, or silicon carbide (SiC), or sapphire (Al 2 O 3 ); a buffer layer  11  extending over the substrate  2 ; and a heterojunction, or heterostructure,  7  extending over the buffer layer  11 . 
         [0027]    The buffer layer  11  comprises an electrical-conduction layer  4  and a resistive layer  6 , where the electrical-conduction layer  4  is of gallium nitride (GaN) of an intrinsic type or with N-type doping and extends over the substrate  2 , whereas the resistive layer  6  is of gallium nitride (GaN) with a doping of a P-type (for example, with a concentration of dopant species comprised between 10 15  and 10 20  ions/cm 3 ) and extends over the electrical-conduction layer  4 . The buffer layer  11  further comprises, optionally, one or more additional buffer layers (or interface layers)  3  of compounds formed by elements belonging to Groups III-V of the Periodic Table including gallium, which extend between the substrate and the electrical-conduction layer  4 . 
         [0028]    The buffer layer  11  has the function of configuring the device as a normally-off device. 
         [0029]    The one or more interface layers  3  have the function of withstanding the drain voltage when the device is off and of decreasing the density of threading dislocations. 
         [0030]    The heterostructure  7  includes, in particular, a barrier layer  9 , made for example of gallium nitride (GaN) of an intrinsic type, extending over the resistive layer  6 , and a channel layer  10 , in this case of aluminum gallium nitride (AlGaN), extending over the barrier layer  9 . 
         [0031]    The HEMT device  1  further comprises an insulation layer  12 , of dielectric material such as silicon nitride (Si 3 N 4 ) or silicon oxide (SiO 2 ), extending over a top side  7   a  of the heterostructure  7 ; and a gate region  14 , extending between a source region  16  and a drain region  18 . 
         [0032]    In what follows, the substrate  2 , the buffer layer  11  (and the buffer layer  3 , when present), and the heterostructure  7  are referred to, as a whole, as the semiconductor body  15 . The semiconductor body  15  houses an active region  15   a , which forms the active part of the HEMT device  1 . 
         [0033]    The gate region  14  is separated laterally (i.e., along X) from the source region  16  and the drain region  18  by respective portions of the insulation layer  12 . The gate region  14  is of a recessed type, and, according to one aspect of the present disclosure, extends in depth through the heterostructure  7 , the resistive layer  6 , and, in part, the electrical-conduction layer  4 , terminating within the electrical-conduction layer  4 . For example, considering an electrical-conduction layer  4  having a thickness, along Z, comprised between 20 nm and 10 μm, the gate region  14  extends in the electrical-conduction layer  4  for a depth greater than 0 μm and less than 10 μm, for example 0.5 μm. 
         [0034]    According to a different aspect of the present disclosure, as illustrated in  FIG. 2 , the gate region  14  extends in depth right through the heterostructure  7  and the resistive layer  6  and terminates at the interface between the resistive layer  6  and the electrical-conduction layer  4 . The gate region  14  thus reaches the electrical-conduction layer  4 , but does not penetrate therein. 
         [0035]    Irrespective of the embodiment, the gate region  14  is formed in a trench  19  etched through part of the semiconductor body  15 . The trench  19  is partially filled by a dielectric layer  11 , for example silicon oxide, which forms a gate-dielectric layer  14   a . The gate-dielectric layer  14   a  extends over the bottom and inner side walls of the trench  19 . A gate metallization  14   b  extends in the trench  19  on the gate-dielectric layer  14   a . The gate-dielectric layer  14   a  and the gate metallization  14   b  form the gate region  14  of the HEMT device  1 . 
         [0036]    According to further embodiments (not shown), the semiconductor body  15 , like the active region  15   a  housed thereby, may comprise a single layer or a number of layers of GaN, or GaN alloys, appropriately doped or of an intrinsic type. 
         [0037]    The source region  16  and drain region  18 , of conductive material, for example metal, extend over, and in contact with, the heterostructure  7 . According to a different embodiment, the source region  16  and drain region  18  may be of a recessed type, i.e., penetrate into a portion of the semiconductor body  15 . 
         [0038]    The gate region  14  extends in an area corresponding to the active region  15   a.    
         [0039]    In use, when the gate region  14  is biased with a voltage V G  higher than a threshold voltage V th , a conductive channel  22  is created (represented schematically by arrows) between the source region  16  and the drain region  18 , said channel extending in the direction Z through the resistive layer  6  and in the direction X through the electrical-conduction layer  4 , underneath the gate region  14 . In this way, the path of the current through the resistive layer  6 , of p-GaN, is minimized and the ON-state resistance, R ON , is optimized. 
         [0040]    Operation of the HEMT device  1 ′ of  FIG. 2  and the corresponding advantages are similar to those described with reference to the HEMT device  1  of  FIG. 1 . 
         [0041]      FIG. 3  shows a HEMT  30  according to a further embodiment of the present disclosure. 
         [0042]    The HEMT  30  is similar to the HEMT  1  of  FIG. 1  (elements that are in common are not described any further and are designated by the same reference numbers). However, in this case, the electrical-conduction layer  4  of GaN, represented in  FIG. 1 , is replaced by an electrical-conduction layer  34  of a compound of gallium nitride comprising aluminum, such as AlGaN. In addition, extending between the electrical-conduction layer  4 , which is made, for example, of AlGaN, and the substrate  2 , is a gallium-nitride layer  35  for forming a further heterojunction, or heterostructure,  37  underneath the gate region  14 . 
         [0043]    This solution is advantageous in so far as, in addition to the aforementioned advantages, the presence of the further heterostructure  37  underneath the gate region  14  enables formation of a layer of two-dimensional electron gas (2DEG) that reduces further the value of the ON-state resistance R ON  of the HEMT device  30 . 
         [0044]      FIG. 4  shows a HEMT device  40  according to a further embodiment of the present disclosure. 
         [0045]    The HEMT device  40  has, on the substrate  2  and on the buffer layer  3 , a heterostructure formed by a channel layer  44  and a barrier layer  46 . The channel layer  44  is, for example, of intrinsic gallium nitride (GaN), and the barrier layer  46  is, for example, of intrinsic aluminum gallium nitride (AlGaN). A gate region  48  of a recessed type extends between the source region  45  and the drain region  47 . The source region  45  and drain region  47  extend alongside the gate region  48 , on the barrier layer  46 . Optionally, also the source region  45  and drain region  47  may be of a recessed type. The channel layer  44  and the barrier layer  46  are of materials such that, when they are coupled together as illustrated in the figure, they form a heterojunction that enables formation of a 2DEG layer. 
         [0046]    The gate region  48  extends, along Z, through the barrier layer  46  and the channel layer  44 , and terminates in the channel layer  44 . 
         [0047]    A resistive region  50 , with P-type doping, extends alongside the gate region  48  and underneath the source region  45 . The resistive region  50  may extend both in the barrier layer  46  and in the channel layer  44 , or else exclusively in the channel layer  44 . 
         [0048]    It may be noted that the resistive region  50  extends at least in part in lateral contact with the gate region  48  and completely underneath the source region  45  in such a way that, in use, the conductive channel is formed necessarily through it in order to enable a flow of electric current (represented by arrows  52 ) between the source region  45  and the drain region  47 . The resistive region  50  does not extend underneath the gate region  48 . 
         [0049]    Optionally, a further resistive region (not represented in the figure) may be present on the opposite side of the gate region  48 , i.e., in lateral section, between the gate region  48  and the drain region  47  (in particular, specular to the resistive region  50 ). 
         [0050]    The resistive region  50  (and the further resistive region, when present) has a density of dopant species comprised between 10 15  cm −3  and 10 20  cm −3 , for example 10 17  cm −3 . 
         [0051]    According to a variant of the embodiment of  FIG. 4 , the resistive region  50  extends ( FIG. 5 ) exclusively in the channel layer  44  at least in part in lateral contact with the gate region  48  and completely underneath the source region  45  in such a way that, also in this case, the conductive channel is formed through the resistive region  50 . A further resistive region (not shown) may be present on the opposite side of the gate region  48 , specular to the resistive region  50 . 
         [0052]    Described in what follows, with reference to  FIGS. 6A-6E , are steps for manufacturing the HEMT device  1  of  FIG. 1 . 
         [0053]      FIG. 6A  shows, in cross-sectional view, a portion of a wafer  60  during a step of manufacture of the HEMT device  1 , according to one embodiment of the present disclosure. Elements of the wafer  60  that are in common to the ones already described with reference to  FIG. 1  and appearing in  FIG. 1  are designated by the same reference numbers. 
         [0054]    In particular ( FIG. 6A ), the wafer  60  is provided comprising: the substrate  2 , made, for example, of silicon (Si) or silicon carbide (SiC) or aluminum oxide (Al 2 O 3 ), having a front side  2   a  and a rear side  2   b  opposite to one another in a direction Z; the electrical-conduction layer  4 , of intrinsic gallium nitride (GaN), having its own underside  4   a  that extends on the front side  2   a  of the substrate  2  (with the possible intermediate presence of the buffer layer  3 ); the resistive layer  6 , of gallium nitride (GaN) with P-type doping; and the heterostructure  7 , extending over the resistive layer  6 . 
         [0055]    By way of example, the resistive layer  6  has a thickness comprised between 5 nm and 1 μm, and the GaN layer  10  has a thickness comprised between a few nanometers (e.g., 2 nm) and 1 μm. 
         [0056]    According to the present disclosure, extending on the front side  7   a  of the heterostructure  7  is the passivation layer, or insulation layer,  12 , of dielectric or insulating material such as silicon nitride (SiN), silicon oxide (SiO 2 ), or some other material still. The insulation layer  12  has a thickness comprised between 5 nm and 300 nm, for example 100 nm, and is formed by chemical-vapor deposition (CVD) or atomic-layer deposition (ALD). 
         [0057]    The wafer  60  according to  FIG. 6A  may be purchased prefabricated or else formed by processing steps in themselves known. 
         [0058]    Next ( FIG. 6B ), the insulation layer  12  is selectively removed, for example with lithographic and etching steps, for removing selective portions thereof in the region of the wafer  60  where, in subsequent steps, a gate region of the HEMT device is to be formed (i.e., in an area corresponding to a part of the active area  15   a ). 
         [0059]    The etching step may stop at the electrical-conduction layer  4  (in a way not represented in the figure), or else proceed partially into the electrical-conduction layer  4  (the latter solution is represented in  FIG. 6B ). In either case, a surface portion  4 ′ of the electrical-conduction layer  4  is exposed. The portion of the electrical-conduction layer  4  removed generates a cavity, in the electrical-conduction layer  4 , having a depth d 1  along Z comprised between 0 and 1 μm. However, other embodiments are possible, and the portion of the electrical-conduction layer  4  removed may have a depth, along Z, greater than 1 μm (in any case less than the total thickness of the electrical-conduction layer  4 ). 
         [0060]    Then ( FIG. 6C ), a step is carried out of deposition, or growth, of the gate-dielectric layer  14   a , for example of a material chosen from among aluminum nitride (AlN), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), and silicon oxide (SiO 2 ). The gate-dielectric layer  14   a  has a thickness chosen between 5 nm and 50 nm, for example, 20 nm. 
         [0061]    Next ( FIG. 6D ), a step is carried out of deposition of conductive material on the wafer  60  to form a conductive layer  58  on the gate-dielectric layer  14   a , in particular filling the trench  19  completely. For example, the conductive layer  58  is of metal material, such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), palladium (Pa), tungsten (W), tungsten silicide (WSi 2 ), titanium aluminum (Ti/Al), and nickel gold (Ni/Au). 
         [0062]    The conductive layer  58  is then selectively removed with lithographic and etching steps in themselves known for eliminating the conductive layer  58  from the wafer  60  except for the portion thereof that extends in the trench  19  to form the gate metallization  14   b . The gate metallization  14   b  and the gate dielectric  14   a  form, as a whole, the recessed-gate region  14  of the HEMT device  1  of  FIG. 1 . 
         [0063]    Then ( FIG. 6E ), one or more further steps are carried out of masked etching of the dielectric layer  14   a  and of the insulation layer  12 , to remove selective portions thereof that extend in regions of the wafer  60  where the source and drain regions  16 ,  18  of the HEMT device  1  are to be formed. 
         [0064]    In particular, openings  54   a  and  54   b  are formed on opposite sides, along X, of the gate region  14 , and at a distance from the gate region  14 . 
         [0065]    Next, a step of formation of ohmic contacts is carried out to provide the source and drain regions  16 ,  18 , depositing conductive material, in particular metal such as titanium (Ti) or aluminum (Al), or their alloys or compounds, by sputtering or evaporation, on the wafer  60  and in particular inside the openings  54   a ,  54   b . There is then carried out a subsequent step of etching of the metal layer thus deposited to remove said metal layer from the wafer  60  except for the metal portions that extend within the openings  54   a  and  54   b , to form in said openings  54   a  and  54   b  the source region  16  and the drain region  18 , respectively. 
         [0066]    Then, a step of rapid thermal annealing (RTA), for example at a temperature between approximately 500° C. and 900° C. for a time ranging from 20 s to 5 min, enables formation of ohmic contacts of the source region  16  and drain region  18  with the underlying heterostructure  7 . 
         [0067]    The HEMT device  1  represented in  FIG. 1  is thus formed. 
         [0068]    With reference to the embodiment of  FIG. 3 , the manufacturing steps are similar to the ones described with reference to  FIGS. 6A-6E , with the difference that, as an alternative to the electrical-conduction layer  4 , of GaN, the layers  35  and  34 , made, respectively, of GaN and AlGaN, are formed, stacked on top to one another. 
         [0069]    With reference to the embodiment of  FIG. 4 , in this case, after providing a wafer comprising the substrate  2 , the channel layer  44 , and the barrier layer  46 , prior to formation of the gate region  48 , source region  45 , and drain region  47 , a step of implantation of dopant species, for example Mg, Zn, F, is carried out using as parameters an implantation energy of 30 keV and an implantation dose of 10 15  cm −2 . The insulation layer  12  may be present during implantation in order to limit surface damage of the wafer. A step of thermal annealing enables activation of the implanted dopant species to form the resistive region  50  of  FIG. 4 . 
         [0070]    By modulating the implantation energy, it is possible to modulate the implantation depth. For example, by increasing the implantation energy it is possible to form the resistive region  50  exclusively in the channel layer  44 , at the desired depth. Use of an implantation step enables, in particular, definition of the resistive region only in the low-field region of the device. 
         [0071]    The implantation steps are carried out using an appropriate mask in order to define the extension, in the plane XY, of the resistive implanted region. 
         [0072]    The advantages of the disclosure according to the present disclosure emerge clearly from what has been set forth previously. 
         [0073]    In particular, a considerable improvement of the trade-off between turn-on threshold voltage (V th ) and ON-state resistance (R ON ) is obtained. 
         [0074]    Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure. 
         [0075]    For example, at the interface between the substrate  2  and the electrical-conduction layer  4  there may be present one or more further transition layers (not shown) of gallium nitride and compounds thereof, such as, for example, AlGaN, or AlN, having the function of interface for reducing the lattice misalignment between the substrate  2  and the electrical-conduction layer  4 . 
         [0076]    The metallization of the contacts (source, drain, gate) on the front of the wafer may be carried out using any variant known in the literature, such as, for example, formation of contacts of AlSiCu/Ti, Al/Ti, or W-plugs, or others still. 
         [0077]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.