Abstract:
A combinational circuit functioning as a TPC radix converter comprised from a TPC decoder connected to a TPC encoder for converting an operand from a TPC represented input in the form of n-digit by r-bit of a first number system of radix r to a TPC represented output in the form of p-digit by b-bit of a second number system of radix b has been disclosed.

Description:
This application is a continuation of application Ser. No. 07/917,397, filed Jul. 23, 1992, now abandoned, which is a division of application Ser. No. 07/789,410, filed Nov. 1, 1991, now U.S. Pat. No. 5,181,186. 
    
    
     BACKGROUND OF THE INVENTION 
     Information needs to be represented in a suitable form in order to be operated upon in a desired way. A coding system is one of such a suitable form. There is not yet a coding system that is good for all purposes and accordingly many coding systems are invented and correspondingly many manipulating in accordance machines are designed. Information represented according to a particular coding system may not be recognized and processed by a machine designed for manipulation according to a different coding system. Communications between one system and another are needed in many cases where code conversion is a must when coding system are not the same. Radix conversion is a very special case limited to number representations where radices are relevant. For example, the conversion of Roman numerals to and from Fibonacci code does not involve radix conversion. Radix conversion according to the conventional methods is equivalent basically to an evaluation of the formula ##EQU1## where N denotes a positive integer needs to be converted and a i  is a digit of a number system of radix r. An evaluation of a formula of such type is not a simple task because it may involve all basic arithmetic operations addition, subtraction, multiplication and division. 
     SUMMARY OF THE INVENTION 
     The complexity implied by the evaluation of the above-mentioned formula adopted in conventional radix conversion methods is avoided altogether in this invention. Instead of the principle that radix conversion is an evaluation of a formula of the type mentioned-above, followed conventionally, this invention is based on that radix conversion is simply a decoding-encoding procedure and accordingly the radix converter of this invention is precisely a TPC decoder connected to a TPC encoder. The only requirement is that decoding and encoding processes of this invention need to be upon operands in TPC representations. How an operand may be represented in a TPC form is fully explained in the cited above parent application. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a logic diagram of a combinational circuit of a TPC decoder(DR) for the case n=2 and r=6; 
     FIG. 2 is a logic diagram of a combinational circuit of a TPC trimmed decoder(TD) for the case n=2, r=6 and m=17; 
     FIG. 3 is a logic diagram of a combinational circuit of a c-out-of-r decoder(CDR) for the case c=2 and r=10; 
     FIG. 4 is a logic diagram of a combinational circuit of a TPC encoder (ER) for the case n=3 and r=3; and 
     FIG. 5 is a logic diagram of a combinational circuit of a TPC radix converter(RC) for the case n=2, r=6, p=3 and b=4 where n and r are positive integer of a first number system of radix r and p and b are positive integers of a second number system of radix b. 
    
    
     DESCRIPTION OF THE INVENTION 
     As explained in the Text Book [Mano, M. M., Digital Logic and Computer Design, Englewood Cliffs, N.J., Prentice-Hall, 1979], a combinational circuit is fully specified by its input-output(I/O) relations. It is stated there that I/O relations and logic diagrams are two equivalent expressions concerning combinational circuits. This is part of the fact stating that calculus of propositions and combinational (relays and switching) circuits are equivalent discovered by the American mathematician Claude E. Shannon in 1938, [Shannon, C. E., A Symbolic Analysis of Relay and Switching Circuits, Transaction of the AIEE, Vol. 57, pp. 713-723, 1938 ]. All the circuits of this invention are combinational circuits precisely specified by their associating input-output relations. 
     FIG. 1 is a combinational circuit for a TPC decoder drawn according to the following I/O relations for the case n=2 and r=6: ##EQU2## where the multiplication sign &#34;π&#34; denotes AND operator, L ij  for i j  =0, 1, . . . , r-1 denotes the inputs, r is an integer greater than 1 denotes the radix of a given number system, n is a positive integer denotes how many digits of radix r each is the width of a given input and d k  for k=0, 1, . . . , r n  -1 denotes the outputs. For the given case (i.e., for the case n=2 and r=6), relations (1 ) are as follows: ##EQU3## Relations (1) are obtained according to the following procedure: 
     ALGORITHM 1: A design procedure for a TPC decoder 
     1. Write down the integers 0 through r n  -1 consecutively, where r denotes the radix of the given system and n denotes the width of the given input measured in digits of radix r each; 
     2. For each integer of step 1 let there be a corresponding AND gate; and 
     3. Connect-the input lines(there are rn as many) to the AND gates of step 2 as indicated by integers of step 1. FIG. 1 shows direct application for algorithm 1. 
     FIG. 2 is a combinational circuit for a TPC trimmed decoder drawn according to the following I/O relations for the case n=2, r=6 and m=17: ##EQU4## where multiplication and summation signs denote AND and OR operators respectively; L ij , d k , i j , k, r and n are as defined for relations (1); and m is a positive integer. The difference between the decoder of FIG. 1 and the trimmed decoder of FIG. 2 is that all the outputs correspond to a number greater than a given positive integer m are not required in case of the trimmed decoder and accordingly ORed with the nearest output correspond to the given positive integer m. 
     FIG. 3 is a combinational circuit for a c-out-of-r decoder drawn, for the case c=2 and r=10, according to the following I/O relations: ##EQU5## where the multiplication sign denotes AND operator, c is a positive integer less than r, and r, d k , L ij  and i j  are as defined for relations (1). For the given case c=2 and r=10, there are ten inputs L i  and r!/c!(r-c)!=45 outputs d k  as shown in FIG. 3, where &#34;!&#34; denotes factorial operator, e.g., 4!=4×3×2×1=24. The circuit of FIG. 3 can be drawn according to ALG. 1 where the integers of step 1 are the combinations of (0, 1, . . . , r-1) taken c at a time. 
     FIG. 4 is a combinational circuit for a TPC encoder drawn, for the case r=3 and n=3, according to the following I/O relations: ##EQU6## where the summation sign denotes OR operator, L ij  for i=0, 1, . . . , r-1 and j=1, 2, . . . , n denotes the output, d k  for k=0, 1, . . . , r n  -1 denotes the input, r is a positive integer greater than 1 denotes the radix of a given number system, and n is a positive integer denotes the width of the output measured in digits of radix r. For the given case (i.e., for r=3 and n=3), relations (4) are as follows: 
     
         L.sub.01 =d.sub.000 +d.sub.010 +d.sub.020 +d.sub.100 +d.sub.110 +d.sub.120 +d.sub.200 +d.sub.210 +d.sub.220 
    
     
         L.sub.11 =d.sub.001 +d.sub.011 +d.sub.021 +d.sub.101 +d.sub.111 +d.sub.121 +d.sub.201 +d.sub.211 +d.sub.221 
    
     
         L.sub.21 =d.sub.002 +d.sub.012 +d.sub.022 +d.sub.102 +d.sub.112 +d.sub.122 +d.sub.202 +d.sub.212 +d.sub.222 
    
     
         L.sub.02 =d.sub.000 +d.sub.001 +d.sub.002 +d.sub.100 +d.sub.101 +d.sub.102 +d.sub.200 +d.sub.202 d.sub.202 
    
     
         L.sub.12 =d.sub.010 +d.sub.011 +d.sub.012 +d.sub.110 +d.sub.111 +d.sub.112 +d.sub.210 +d.sub.211 +d.sub.212 
    
     
         L.sub.22 =d.sub.020 +d.sub.021 +d.sub.022 +d.sub.120 +d.sub.121 +d.sub.122 +d.sub.220 +d.sub.221 +d.sub.222 
    
     
         L.sub.03 =d.sub.000 +d.sub.001 +d.sub.002 +d.sub.010 +d.sub.011 +d.sub.012 +d.sub.020 +d.sub.021 +d.sub.022 
    
     
         L.sub.13 =d.sub.100 +d.sub.101 +d.sub.102 +d.sub.110 +d.sub.111 +d.sub.112 +d.sub.120 +d.sub.121 +d.sub.122 
    
     
         L.sub.23 =d.sub.200 +d.sub.201 +d.sub.202 +d.sub.210 +d.sub.211 +d.sub.212 +d.sub.220 +d.sub.221 +d.sub.222. 
    
     Relations (4) are obtained according to the following algorithm: 
     ALGORITHM 2: A procedure for designing a TPC encoder 
     1. Write down the integers 0 through r n  -1 consecutively; 
     2. Let there be rn OR gates in front of the integers of step 1 arranged into n groups of r OR gates each so that the outputs of the OR gates correspond together to an integer represented by L ij  in which i is a digit in position j for i=0, 1, . . . , r-1 and j=1, 2, . . . , n; and 
     3. Connect the inputs representing the integers of step 1 to the OR gates of step 2 as indicated by the labelling L ij . 
     FIG. 4 shows direct application to algorithm 2. 
     FIG. 5 is a combinational circuit for a TPC radix converter from a first number system of radix r to a second number system of radix b drawn(for the case r=6, n=2, b=4 and p=3) according to the following I/O relations: ##EQU7## where multiplication and summation signs denote AND and OR operators respectively, m is an integer greater than or equal to r n , n denotes how many digits of the first number system of radix r is the width of the input, p denotes how many digits of the second number system of radix b is the width of the output, L ij   1  for i j  =0, 1, . . . , r-1 and j=1, 2, . . . , n denotes the input, L ij   2  for i j  =0, 1, . . . , b-1 and j=1, 2, . . . , p denotes the outputs, d k  denotes an internal variable, and k=0, 1, . . . , r n  -1 with respect to the first number system of radix r and k=0, 1, . . . , m with respect to the second number system of radix b. Relations (5) are obtained according to the following algorithm which is merely a combination of algorithms 1 and 2 above: 
     ALGORITHM 3: A design procedure for a TPC radix converter 
     1. Algorithm 1 given above with respect to the first number system of radix r; and 
     2. Algorithm 2 given above also with respect to the second number system of radix b and where the outputs of step 1 are the same inputs of step 2. 
     FIG. 5 shows an illustration for algorithm 3. 
     Any TPC representation for any n-digit operand of a number system of radix r must be in the form of n-digit by r-bit. For example, the integer 203 of the number system of radix r=4 is represented in the TPC by 0100 0001 1000 which is a TPC representation of 3-digit by 4-bit, i.e., in the form of n-digit×r-bit. The TPC decoder of FIG. 1 converts a number from a TPC representation of the form n-digit by r-bit to another TPC representation of the form one-digit×r n  -bit. The TPC encoder of FIG. 4, on the other hand, converts a number from a TPC representation of the form one-digit×m-bit to another TPC representation of the form p-digit×b-bit. Means that the TPC decoder is precisely a TPC radix converter from a number system of radix r to a number system of radix r n  and the TPC encoder is precisely a TPC radix converter from a number system of radix m to another number system of radix b. Choosing m greater than or equal to r n  and combining the TPC decoder and the TPC encoder together simply by connecting the outputs of the TPC decoder to the corresponding inputs of the TPC encoder means that the combination so obtained is precisely a TPC radix converter from a number system of radix r to another number system of radix b. It is that simple. Radix conversion according to this invention is merely a decoding-encoding procedure and accordingly the TPC radix converter of this invention is simply a combination of a TPC decoder and a TPC encoder. The TPC decoder and the TPC encoder are both combinational circuits and accordingly their combination the TPC radix converter is a combinational circuit. Means that radix conversion is reduced from a procedure for evaluating a formula of the type cited in the summary of the invention above where a multi-operation processor may be necessary to a decoding-encoding procedure requires no more than a combinational circuit for its implementation.