Abstract:
A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application No. 60/488,328, filed on Jul. 18, 2003 and under 35 U.S.C. § 119(a) of European patent application EP 03447238.1, filed on Sep. 25, 2003. U.S. Provisional Patent Application No. 60/488,328 and European patent application EP 03447238.1 are herein incorporated by reference in their entirety. 
     
    
     BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     This invention is related to integrated circuits and methods for manufacturing such integrated circuits. More particularly, the present invention relates to semiconductor devices with multiple gates and non-uniform doping profiles in the channel region of those devices.  
         [0004]     2. Description of Related Art  
         [0005]     Current semiconductor chips feature technology with circuit feature sizes in the range of 130 nanometers, with components manufactured with technologies having 90 nanometer feature sizes just beginning to reach the marketplace. Industry plans are to deliver 65 nanometer technologies in the year 2007, 45 nanometer technologies in the year 2010, 32 nanometer technologies in the year 2013 and 22 nanometer technologies in the year 2016. This schedule was set forward in the International Technology Roadmap for Semiconductors (ITRS) defined by the Semiconductor Industry Association (SIA) in 2001. The schedule translates to smaller chip dimensions earlier in time than had been previously thought. Among the main transistor scaling issues to be solved is the need for thinner gate oxides that result in a higher on-current and hence increased switching speed in semiconductor devices; a smaller off-current and lower threshold voltage to allow such gate oxide scaling, and the use of lower supply voltages; a higher channel mobility; and smaller series resistance of the source/drain regions. In order to meet these forecasted stringent scaling requirements, non-classical Complementary Metal-Oxide-Semiconductor (CMOS) devices and alternative materials, such as metal gate materials and high dielectric constant (high-k) gate dielectrics are currently under investigation.  
         [0006]     One non-classical CMOS device is so-called Fin Field Effect Transistors (FinFETs). In a FinFET, the gate at least partially envelops the channel region in multiple planes, as compared to a classic planar CMOS device where the gate electrode is formed in a single plane on top of the channel region, where the channel region is part of the substrate.  
         [0007]     A double gate FinFET made by using the sidewalls of a dry-etched silicon (Si) fin as conducting channels was discussed by D. Hisamoto et al. in “A folded-channel MOSFET for deep-sub-tenth Micron Era” in the IEDM Technical Digest 1998 pp. 1032-1034. In such FinFETs, a thin gate line straddles a thin silicon channel fin. Bin Yu et al, discusses an alternative process to manufacture a FinFET device in “FinFET scaling to 10 nm Gate Length”, IEDM Technical Digest 8-11 Dec., 2002 pp. 251-254. For the process described by Yu et al., polysilicon is used as a gate electrode material and the channel of the device is uniformly lightly doped.  
         [0008]     While is possible for a FinFET be manufactured in a near-planar fashion, such that the manufacturing is compatible with traditional CMOS processing technologies, the performance of FinFET devices manufactured in such a fashion is typically inferior to traditional planar CMOS transistors manufactured with the same processing technology. The respective performance of such devices (FinFET versus planar CMOS) may be indicated by various parameters such as the sub-threshold swing (S, mV/dec), which is the variation of drive current with gate voltage for gate voltages below the transistor threshold voltage (V t ), the maximum or saturation drive current (I on ), the off state-current or leakage current (I off ), the threshold voltage roll-off (ΔV t ) expressing the dependency of the threshold voltage on channel length (L g ) and drain voltage (V ds ).  
         [0009]     Two approaches are currently being employed to improve the performance (as measured by such parameters) of FinFET devices manufactured using CMOS technologies. A first approach is to increase the dopant concentration level (N fin ) of the fin. Although this approach yields a low sub-threshold slope and a controllable threshold voltage, during operation, when inversion occurs near the surface of the fin, the carrier mobility is degraded due to ionized impurity scattering. This results in a lower saturation current, which slows down the device and reduces its performance. Further, in such an approach, threshold voltage roll-off will be more pronounced, as the highly doped fin will typically not become fully depleted during operation.  
         [0010]     A second approach involves reducing the fin doping concentration level N fin  and developing a tunable work-function gate technology. Such an approach is described by Yang-Kyu Choi et al. in “FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering” in IEDM 2002 Digest International, 8-11 Dec., 2002, pp. 259-262. Apart from forming a high quality interface between the fin and the gate dielectric, the mobility of the carriers may be improved by lowly doping the fin resulting in less ionized impurity scattering and, hence, in a larger saturation current. Further, the lowly doped fin also increases the immunity of the threshold voltage to fluctuations in the dopant distribution profile.  
         [0011]     However, because of the low doping of the fin, the threshold voltage is determined by the work function of the gate electrode, which must then be carefully selected in order to obtain the desired threshold voltage for either n-type or p-type FinFETs. This approach is cumbersome, as only a limited selection of materials is available, thereby still requiring additional efforts to tune the work function of these materials to the desired value. The introduction of such materials increases the manufacturing process complexity as additional process steps may be employed.  
         [0012]     Still further, the low doping concentration of the fin results in a higher sub-threshold slope and, consequently, in increased leakage current and increased power consumption as is described in “A Comprehensive Model Analytical Sub-threshold Swing (S) Model for Double-gate MOSFETs” by Qiang Chen et al, in IEEE Transactions on Electronic Devices, Vol. 49, No. 6, Jun. 2002, p. 1086. Based on the foregoing, alternative FinFET devices and methods for manufacturing FinFET devices that improve their performance without degrading other device parameters such as sub-threshold slope, saturation current, leakage current and threshold voltage roll-off are desirable.  
       SUMMARY  
       [0013]     Embodiments of the invention address, at least some of, the performance concerns of current FinFET approaches, such as degradation of sub-threshold slope, saturation current, leakage current and threshold voltage roll-off parameters. In one embodiment, a multi-gate semiconductor device includes a source region, a drain region, a semiconductor body in between the source region and the drain region, which connects the source region and the drain region; and a gate electrode on at least two sides of the semiconductor body. The semiconductor body includes a first region having a first dopant level and a second region that is in between the gate electrode and the first region. The second region has a second dopant level that is lower than the first dopant level. Such a device may be referred to as having a retrograde doping profile or a as being a retrograde device.  
         [0014]     Such a multi-gate semiconductor retrograde device may take the form of a retrograde FinFET device, where the semiconductor body is the fin of the FinFET device. In certain embodiments, the first dopant level remains constant over the first region and the second dopant level remains constant over the second region. In alternative embodiments, the dopant concentration in the second region decreases from the first dopant level to the second dopant level over at least a portion of the second region.  
         [0015]     An embodiment of a method for manufacturing a retrograde doped multi-gate device, such as the FinFET device described above includes providing a substrate, where the substrate has a source, a drain and a fin connecting the source and the drain. In this embodiment, the fin has a first dopant level. The method further includes forming a layer, at least at the exposed surfaces of the fin, where the formed layer has a dopant level lower than the first dopant level. Such devices have improved performance without substantially degrading other device parameters, such as sub-threshold slope, saturation current, leakage current and threshold voltage roll-off.  
         [0016]     These and other aspects will become apparent to those of ordinary skill in the art by reading the following detailed description, with reference, where appropriate, to the accompanying drawings. Further, it should be understood that the embodiments noted in this summary are not intended to limit the scope of the invention as claimed.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The appended drawings are intended to illustrate some aspects and embodiments of the present invention. Devices in the drawings are depicted in a simplified way for reason of clarity. Not all alternatives and options are shown and, therefore, the invention is not limited in scope by the drawings. It is noted that like reference numerals are employed to reference analogous parts of the various drawings, in which:  
         [0018]      FIG. 1  includes  FIG. 1   a , which is a drawing of a prior art FinFET device formed in a SOI layer, and  FIG. 1   b , which is a cross-sectional drawing of the fin of the FinFET device of  FIG. 1   a  along its gate;  
         [0019]      FIG. 2  includes  FIG. 2   b , which is a cross-sectional drawing of a dual gate semiconductor device having a lowly doped region and a highly doped region (e.g., a retrograde doping profile), and  FIG. 2   a , which illustrates the dopant profile of the device of  FIG. 2   b;    
         [0020]      FIG. 3  includes  FIG. 3   b , which is a cross-sectional drawing of a triple gate semiconductor device having retrograde doping,  FIG. 3   a , which illustrates the dopant profile of the device of  FIG. 3   b  in the horizontal direction, and  FIG. 3   c , which illustrates the dopant profile of the device of  FIG. 3   b  in the vertical direction;  
         [0021]      FIG. 4  illustrates various aspects of three alternative FinFET devices, the three devices having (i) uniform doping of the fin, (ii) retrograde doping in accordance with an embodiment of the invention (e.g., according to the dopant profile shown in  FIG. 4   a ), and (iii) work function engineering of the gate electrode material, where  FIG. 4   b  illustrates saturation current for the three devices using a linear scale,  FIG. 4   c  illustrates saturation current for the three devices using a logarithmic scale, and  FIG. 4   d  illustrates sub-threshold swing for the three devices;  
         [0022]      FIG. 5  illustrates a doping profile of the fin of a retrograde FinFET; and  
         [0023]      FIG. 6  illustrates an alternative FinFET device according to another embodiment of the invention, where  FIG. 6   a  illustrates a patterned fin with a highly doped body,  FIG. 6   b  illustrates the formation of a lowly doped surface layer enveloping the highly doped body of the device,  FIG. 6   c  illustrates the doping of the source region and the drain region while using the formed gate as a mask to block the channel(s) of the FinFET from implantation, and  FIG. 6   d  is a cross-sectional drawing of the FinFET device of  FIG. 6   c.    
     
    
     DETAILED DESCRIPTION  
       [0024]     While embodiments of multiple gate semiconductor devices are generally discussed herein with respect to Fin Field Effect Transistors (FinFETs), it will be appreciated that the invention is not limited in this respect and that embodiments of the invention may be implemented in any number of types of device. For example, in his article “Beyond the Conventional Transistor”, published in IBM Journal of Research &amp; Development, Vol. 46, No. 23 2002, which in incorporated by reference herein in it entirety, H. S. Wong discloses various types of multi-gate devices. In  FIG. 14, 15  and  17  of this paper, alternative orientations of double and triple gate devices are depicted with the corresponding process sequences being detailed on pages 146-152. Such device configurations may be employed with embodiments of the invention.  
         [heading-0025]     1. Current FinFET Device  
         [0026]      FIG. 1   a  is a drawing of a prior art FinFET device  100 . The FinFET device  100  includes a semiconductor layer  102  disposed on a substrate  101 . The FinFET device  100  (and other semiconductor devices) are formed on (and in) the substrate  101 . The substrate  101  may be a semiconductor substrate, e.g. silicon. An insulating layer  103  is formed on top of the substrate  101  to insulate the semiconductor layer  102  from the substrate  101 . This approach results in, for example, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate being formed. The FinFET device  100  includes a source region  104  and a drain  105  region connected by a fin  106 , where the fin  106  is located in between the source region  104  and the drain region  105 . As may be seen in  FIG. 1 , the source region  104 , the drain region  105  and the fin  106  are formed from the semiconductor layer  102 .  
         [0027]     The fin  106  constitutes the body of the FinFET  100 . Depending on the particular semiconductor manufacturing process flow employed, the source region  104 , the drain  105  and the fin  106  may be formed from a single layer of semiconductor material (e.g., the semiconductor layer  102 , as shown in  FIG. 1   a ) or from different layers of material. A gate  107 , which includes a gate dielectric layer and a gate electrode layer (not separately designated), is also shown in  FIG. 1   a . The gate  107  overlies the fin  106  on three of its sides (e.g., the top surface and two sidewall surfaces). The channel of the FinFET  100  will be the portion of the fin  106  that is covered by and, depending on the thickness of the gate dielectric, that is under electrical control of the gate voltages applied to the gate  107  (e.g., which may extend beyond the portion of the fin  106  that is physically covered by the gate  107 ).  
         [0028]     A cross-sectional drawing (along line A-A through the gate  107 ) of the FinFET  100  is illustrated in  FIG. 1   b . This drawing shows, in more detail, the overlay of the gate  107  of the fin  106 . The gate  107  overlies the fin  106  at both sidewalls of the fin  106  as well on the top of the fin  106 . As was indicated above, and is shown in  FIG. 1   b , the gate  107  includes a gate dielectric  107   b  and a gate electrode layer  107   a . In embodiments where a relatively thick gate dielectric  107   b  (designated with the thickness t topox ) is present on top of the fin  106 , a double gate device is obtained in which inversion occurs along the upstanding sidewalls of the fin  106  (as shown in  FIG. 1   b ) at a lower threshold voltage than the top of the fin  106 . In comparison, for a thin top gate dielectric  107   a  (e.g., of approximately the same thickness as on the sidewalls), inversion of the top channel would occur in the top surface of the fin  106  at substantially the same threshold voltage as along the sidewalls of the fin  106 . Techniques for forming such FinFET devices are discussed in “High-Performance Symmetric-Gate and CMOS Compatible V t  Asymmetric-Gate FinFET devices”, IEDM Technical Digest 2001 pp 437-440, by J. Kedzierski et al. For the devices described by Kedzierski et al., the source and drain regions are formed together with the fin in an SOI layer using optical lithography, hard mask trimming techniques and uniform doping of the channel region in the fin  106 . However, adjusting the threshold voltage of such devices to improve their performance results in other device parameters, such as saturation current, leakage current, sub-threshold slope, threshold voltage roll-off, being degraded, thus adversely impacting device performance.  
         [heading-0029]     2. Improved FinFET Device  
         [0030]     To improve the performance of multiple gate semiconductor devices, such as the FinFET  100  illustrated in  FIG. 1 , it would be advantageous to be able to adjust the threshold voltage of the device without significantly degrading other device parameters, such as saturation current, leakage current, sub-threshold slope, threshold voltage roll-off.  
         [0031]      FIG. 2  illustrates a FinFET device  200  that allows for adjustment of its threshold voltage without significantly degrading other performance related parameters of the device. The FinFET  200  includes a retrograde doped channel. In this context, retrograde doping means that the doping of the fin (which includes the channel) is relatively low at the surface of the fin, but increases towards the bulk of the fin. For such a doping profile, high surface mobility of the carriers is obtained because ionized impurity scattering is reduced. Further, the higher bulk doping concentration allows for tuning the threshold voltage of the FinFET device  200  without significantly degrading the other device parameters. For such devices, polysilicon may be used for the gate electrode  107   a , as is typically used for gate electrodes of classical MOS devices. Alternatively, other gate materials, such as metals, may be used. In the latter case, the higher bulk doping offers an additional degree of freedom for obtaining the desired threshold voltage relative to tuning the work function of the gate electrode material.  
         [0032]     Referring to  FIG. 2   a , a retrograde doping profile for the FinFET device  200  shown in  FIG. 2   b  (which is a cross section view along a similar line as line A-A of  FIG. 1 ) is shown. As may be seen in  FIG. 2   a , the surface dopant level of the fin  106  has a constant value N surface  over a depth d w  (e.g., the surface regions  106   a  of the fin  106 ) into the fin  106  and a higher constant value N bulk  in the bulk  106   b  of the fin  106  over a distance W fin −2d w .  
         [0033]     For the FinFET  200 , a blocking layer  109  is formed on the top surface of the fin  106 . The layer  109  is used to prevent formation of the lowly doped region  106   a  at the top of fin  106  and also to implement the FinFET  200  as a multiple (two) gate device by effectively increasing the gate dielectric thickness (in conjunction with gate dielectric  107   b  on the top surface of the fin  106 . Alternatively, the thickness of gate dielectric  107   b  on top of the fin  106  may be relatively thick as compared to its thickness on the sidewalls of the fin  106  (in similar fashion as shown in  FIG. 2   b ). For such two gate devices, it is sufficient to employ a retrograde dopant profile in the fin in only the horizontal direction, as is shown in  FIG. 2   b.    
         [0034]     In such an approach, lowly doped regions  106   a  are formed at or near the interface between the fin  106  and the gate dielectric  107   b  along each of the sidewalls of the fin  106 . For the device illustrated in  FIG. 2 , the dopant concentration at a given point in the fin  106  remains constant in the vertical direction (e.g., perpendicular to the substrate  101 ). However, it will be appreciated that variation in the doping concentration will be present at the boundaries of the bulk region  106   b  and the other regions  106   a.    
         [0035]     Referring now to  FIG. 3 , a triple gate FinFET  300  is illustrated.  FIG. 3   b  is a drawing illustrating a cross-section of such the FinFET device  300 . As may be seen in  FIG. 3   b , the FinFET  300  is formed by having thin gate dielectric  107   b  (e.g., of substantially the same thickness as on the sidewalls of the fin  106 ) on top of the fin  106 . For the FinFET  300  a lowly doped region  106   a  is also formed along the top surface of the fin  106  in addition to the lowly doped regions  106  a formed along the sidewalls of the fin  106 ).  
         [0036]      FIG. 3   a  illustrates the dopant profile in the horizontal direction along the line B-B of  FIG. 3   b . This profile is similar to the dopant profile shown in  FIG. 2   a . In the FinFET  300 , during operation, conduction will occur not only along the sidewalls of the fin  106 , but also along the top surface of the fin  106  in a direction parallel with the substrate  101 . Along line B-B, the lowly doped region  106   a  has a low doping concentration N surface  over a distance d w  at each sidewall of the fin  106 , while the bulk region  106   b  has a higher constant doping concentration value N bulk  over a distance W fin −2d w .  
         [0037]      FIG. 3   c  illustrates the dopant profile of the fin  106  along the line C-C of  FIG. 3   b . As may be seen from the dopant profile, a lowly doped region  106   a  is present along a depth d w  from the interface between the top surface of the fin  106  and the gate dielectric  107   b  towards the bulk  106   b  of the fin  106 . Along line C-C, the lowly doped region  106   a  has a low doping concentration N surface  over a distance d w  at the top surface of the fin  106 , while the bulk region  106   b  has a higher constant doping concentration value N bulk  over a distance t fin −d w .  
         [heading-0038]     3. Performance Comparisons  
         [0039]      FIG. 4  illustrates and compares various aspects of three different FinFET devices, which demonstrates at least some of the advantages of implementing a retrograde dopant profile over prior art approaches.  
         [0040]      FIG. 4   a  illustrates a dopant profile (such as along the line B-B in  FIG. 2   b ) for the fin or a FinFET device used in this comparison. The width of the fin W fin  was approximately 22.5 nm, where the depth d w  of the low doping region on each sidewall of the fin was approximately 5 nm. The doping concentrations for this particular retrograde FinFET were about N surface =1e16/cm 3  (e.g. in the lowly doped regions  106   a , as in  FIG. 2   b ) and about N bulk =6.5e18/cm 3  (e.g. in the highly doped region  106   b , as in  FIG. 2   b ).  
         [0041]     In  FIGS. 4   b - 4   d , a FinFET device with the retrograde doping profile shown in  FIG. 4   a  is compared with (i) a FinFET having a threshold voltage of 100 mV manufactured using a uniform doping profile of 3e18 cm −3  throughout the fin and (ii) a FinFET manufactured using work function engineering. Work function engineering includes, among other things, selecting an appropriate gate material in order to achieve improved performance of the device. Work function engineering is discussed in the earlier referenced article by H. S. Wong on p. 137.  
         [0042]      FIG. 4   b  illustrates, on a logarithmic scale, a comparison of the saturation current for each the three FinFET devices described above as a function of the gate voltage. At zero gate voltage, the leakage current in the saturation region for each alternative is shown. As may be seen in  FIG. 4   b , the “work function” device has the largest leakage current, while the “retrograde profile” device performs in comparable fashion with the “uniform profile” device.  
         [0043]      FIG. 4   c  depicts a comparison of the saturation current for each of the three devices being compared as function of the gate voltage. At maximum gate voltage, the drive current for each alternative is shown. As may be seen in  FIG. 4   c , the “uniform profile” device has the lowest drive current, while the “retrograde profile” performs in comparable fashion with the “work function” device.  
         [0044]      FIG. 4   d  shows a comparison of the sub-threshold swing for each of the three devices as a function of the gate length L g . For a gate length of 45 nm, which is the gate length of the devices compared in  FIGS. 4   b  and  4   c , where the devices have threshold voltages of 100 mV, the sub-threshold swing of the “retrograde profile” device is comparable with the sub-threshold swing of the “uniform profile.” However, as the gate length is decreased, the sub-threshold swing of the “retrograde profile” device becomes the smallest of all three approaches, indicating that such devices will maintain their performance even with further reduction of processing technology dimensions (e.g., to less than 45 nm).  
         [heading-0045]     4. Alternative FinFET Doping Profiles  
         [0046]     While the doping profiles of the FinFETs illustrated in  FIGS. 2, 3  and  4   a  are box-like in shape, other doping profiles are possible. For example, referring to  FIG. 2   b , a doping profile with the bulk portion  106   b  of the fin  106  having a first constant doping level, and an outer region  106   a  of the fin  106  where the doping level decreases to a second doping level, being less than the first doping level may be implemented. Within this outer region  106   a , the doping level may decrease in various ways: (e.g., linearly, exponentially, etc). In such embodiments, the doping level would change from one value (e.g., the first doping level) to the other value (e.g., the second doping level) over a portion (or over the complete width d w ) of the outer region  106   a.    
         [0047]     Referring to  FIG. 5 , such an alternative doping profile is shown. As may be seen in  FIG. 5 , the doping concentration in the fin decreases (when moving from the bulk region  106   b  to either of the outer regions  106   a ) from the first doping level N bulk  starting at the border of the bulk region  106   b  and the outer regions  106   a  to the second doping level N surface  within the outer regions  106   a . Once the second doping level N surface  is reached in the outer regions  106   a , the doping level in the outer regions  106   a  remains constant until the edge of the fin is reached. Because, during operation of such a FinFET, charge carriers will mainly flow in the constantly doped portions of the outer regions  106   a , the carriers will be less prone to interference from impurity scattering and, thus, a larger drive current will be obtained as compared to a more heavily doped outer region  106   a.    
         [0048]     In certain embodiments, the width d i  of the constant doping concentration region within the outer regions  106   a  corresponds to the width of the inversion layer region. The first doping level may be in the range of 1e18/cm 3  to 1e20/cm 3 , such as 1e19/cm 3 . The second doping level may be in the range of 1e15/cm 3  to 1e17/cm 3 , such as 1e16/cm 3 . The values of the first and second doping level will depend, at least in part, on the desired threshold voltage. In one particular embodiment, the first doping level is on the order of 1e19/cm 3  and the second doping level is on the order of 1e16/cm 3 . The fin for this embodiment has a total thickness of about W fin =45 nm, with a central (bulk) portion  106   b  width of about 25 nm and outer regions  106   a  of about d w =10 nm width per side. Typically, for such devices, the inversion layer thickness is less than a few nanometers.  
         [heading-0049]     5. Method of Manufacturing a Retrograde FinFET  
         [0050]     Referring now to  FIG. 6 , drawings illustrating a method of manufacturing a semiconductor device with a retrograde doping profile, such as the devices described above, is illustrated. The method includes employing deposition techniques to form a layer that envelops the body of the device, thus resulting in a bi-layer structure. Each layer of the bi-layer structure (the body and the enveloping layer) has a different doping concentration. The enveloping layer (from which the gate(s) will be formed) is at least present at the surfaces of the body where conduction is to take place. Various techniques exist in semiconductor technology to deposit such layers. For example, one such technique is chemical vapor deposition (CVD), which includes a wide range of deposition processes such as epitaxial layer growth, atomic layer CVD and plasma enhanced CVD.  
         [0051]     Referring again to the FinFET  300  illustrated in  FIG. 3   b , such a method will be generally described. For the FinFET  300 , prior to depositing the gate dielectric  107   b , a layer, such as a conformal layer, is formed that overlies the fin  106  of the device. This layer can be in-situ doped, (e.g., dopants may be added to the precursors of the gas mixture from which the conformal layer is to be formed). Of course, alternative doping methods may be employed. The dopants are incorporated into the deposited (e.g., conformal) layer. Thus, the dopant concentration of this deposited layer may be different from the dopant concentration in the initial body or the dopant concentration of the patterned fin of the device. The gate dielectric  107   b  is then formed on top of this deposited layer. The deposited (e.g., conformal layer) may be formed uniformly over an entire wafer or, alternatively, may be formed in a selective manner, such as only on the exposed surfaces of the fin  106 . Such a technique may be employed in embodiments where the top surface of the fin  106  is first covered with a layer or treated so as to not react with the species of the deposition atmosphere. This selective deposition may be achieved by using epitaxial layer growth or selective atomic layer deposition (ALD).  
         [0052]     For example, Wolf and Tauber teach in “Silicon Processing for the VLSI era, Volume I—Process Technology”, 2 nd  Edition, Lattice Press, epitaxial growth (page 225-226), in-situ doping of layers (section 7.4.3 on page 236) and selective epitaxial growth (section 7.7 on pages 245-247). By way of further example, published PCT Application WO 01/15220 teaches the use of atomic layer deposition (ALD) for forming layers on selected surfaces only. The referenced sections of Wolf and Tauber and PCT Application WO 01/15220 are incorporated by reference herein in their entirety. Generally, such deposition selectivity may be achieved by using layers with different surface chemistry to form selected surfaces, or by pre-treating selected surfaces to block the depositing of a layer on these pre-treated surfaces.  
         [0053]     Referring now to  FIG. 6   a , a drawing illustrating a patterned semiconductor layer  102  at an intermediate point of a FinFET manufacturing process is shown. The layer  102  is disposed on an insulating layer  103 , which is, in turn, disposed on a substrate  101 , as has been previously described. The patterned layer  102  includes a fin  106  having a width W fin . The patterned layer  102  further includes a source region  104  and a drain region  105 . Alternatively, the source region  104 , the drain region  105  and the fin  106  may be formed from separate materials, as opposed to the single semiconductor layer  102  shown in  FIG. 6   a.    
         [0054]     After the layer  102  is patterned, the fin  106  is implanted to a first doping level N bulk  which is selected for the bulk of the body based on desired device performance. Alternatively, the N bulk  implantation may be done prior to patterning the layer  102  to form the source region  104 , the drain region  105  and the fin  106 . This implantation may be done using an implantation mask (e.g., only doping the fin  106 ) or, alternatively, without the use of an implantation mask (e.g., also doping the source region  104  and the drain region  105 , or the entire layer  102  before the source region  104 , the drain region  105  and the fin  106  are formed). In the latter case, the doping of the source region  104  and the drain region  105  when doping the fin  106  will be compensated for by a higher dose junction doping (using an opposite dopant type) of the source region  104  and the drain region  105  in a subsequent operation. For FinFET devices that employ electrons as carriers (e.g., n-channel devices), the fin  106  will be p-type doped using dopants such as B or BF2, while the source region  104  and the drain region  105  will be n-type doped using dopants such as P or As.  
         [0055]     In certain embodiments, a sacrificial oxide may be grown after the patterning of the layer  102  to form the source region  104 , the drain region  105  and the fin  106  are formed. The sacrificial oxide is then removed using a wet etch. This growth and etching of the sacrificial oxide will remove damage to the layer  102  resulting from the patterning step, which occurs at the exposed surfaces of before the source region  104 , the drain region  105  and the fin  106 .  
         [0056]     Referring to  FIG. 6   b , a layer  108  is formed (e.g., using epitaxial layer growth) that envelops the fin  106 , the source region  104  and the drain region  105 . The layer  108  is in-situ doped to a second dopant level N surface , which is lower than the bulk concentration N bulk . Such an approach is advantageous as the formation of the epitaxial layer reduces the roughness of the fin  106  with the layer  108 . This reduced roughness may further improve the performance of the final FinFET device.  
         [0057]     Referring to  FIG. 6   c , a drawing illustrating a gate  107  after formation and the implantation (doping) of the source region  104  and the drain region  105  is shown. As was discussed above, the doping of the portion of the epitaxial layer  108  enveloping the source region  104  and the drain region will be compensated for by this counter-doping, while the portion of the layer  108  enveloping the fin  106  (which corresponds to the channel) will remain as-doped due to it being masked by the gate  107 . Additional process steps are then executed to complete the processing of the FinFET device  600  (e.g., forming insulating layers covering the device, forming electrical contacts to contact the source region  104  and the drain region  105 , among any number of other operations).  
         [0058]      FIG. 6   d  is a cross-sectional of the FinFET device  600  shown in  FIG. 6   c  along the line D-D. As may be seen in  FIG. 6   c , a body  106   b  of the fin  106  (which has a first dopant level) is covered at the sidewalls and along the top with a layer  106   a , 108 . The layer  106   a , 108  has a second dopant level that is lower than the first dopant level, as has been previously described. This bi-layer structure is covered by the gate  107 , where the overlay area between the bi-layer structure and the gate  107  defines a channel length L g .  
         [0059]     In order to produce a double gate FinFET device (such as the device illustrated in  FIG. 2   b ), minor modifications to the above manufacturing method are made. Specifically, prior to forming or growing the layer  108  a blocking layer (e.g., the layer  109  in  FIG. 2   b ) would be formed on the top surface of the fin  106 . It will be appreciated that such a blocking layer may be formed over the unpatterned semiconductor layer  102  and then patterned in a region where the fin  106  is to be formed. The source region  104 , the drain region  105  and the fin  106  are then patterned in alignment with the blocking layer.  
         [0060]     Alternatively, the blocking layer may be deposited uniformly over the unpatterned semiconductor layer  102  and patterned along with the source region  104 , the drain region  105  and the fin  106 . In this scenario the patterned blocking layer  109  will substantially coincide with the pattern of the source region  104 , the drain region  105  and the fin  106 , as formed in the semiconductor layer  102 . As discussed above selective depositing process, such as epitaxial layer growth or atomic layer deposition (ALD) may be used to form the layer  108  only on the exposed surfaces of the fin  106  (e.g., the sidewalls), and not on the patterned blocking layer on top of the fin  106 .  
       6. CONCLUSION  
       [0061]     Various arrangements and embodiments in accordance with the present invention have been described herein. It will be appreciated, however, that those skilled in the art will understand that changes and modifications may be made to these arrangements and embodiments without departing from the true scope and spirit of the present invention, which is defined by the following claims.