Abstract:
According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate in the first region and the second region; forming a first metal film on the insulating film in the first region and in the second region; removing the first metal film in the second region; forming a second metal film on the first metal film in the first region and on the insulating film in the second region; and flattening top surfaces in the first region and the second region by performing a flattening process.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority from Japanese Patent Application No. 2008-010344 filed on Jan. 21, 2008, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    An aspect of the present invention relates to a method for manufacturing a semiconductor device and more particularly to a method for manufacturing a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) using a metal gate electrode. 
         [0004]    2. Description of the Related Art 
         [0005]    As the downscaling of the CMIFET progresses, a depletion caused by use of a polysilicon electrode gate becomes a problem, and a metal gate electrode has been used. 
         [0006]    In a metal gate electrode structure, a threshold of a transistor is determined by an impurity concentration in a channel region and a work function of a gate electrode material. Therefore, in a dual metal gate structure, it is desired to use a metal gate material having an optimum work function for each of an n type MISFET (which will be hereinafter referred to as an nMIS) and a p type MISFET (which will be hereinafter referred to as a pMIS) (for example, see JP-2002-329794-A). 
         [0007]    However, there has not been developed a practical method for respectively fabricating metal gate electrodes having optimum work functions for the nMIS and pMIS. It is desired to develop the practical method. 
       SUMMARY OF THE INVENTION 
       [0008]    According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate in the first region and the second region; forming a first metal film on the insulating film in the first region and in the second region; removing the first metal film in the second region; forming a second metal film on the first metal film in the first region and on the insulating film in the second region; and flattening top surfaces in the first region and the second region by performing a flattening process. 
         [0009]    According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate; forming a first cap film on the insulating film; forming a first metal film on the first cap film; removing the first metal film and the first cap film in the second region; forming a second metal film on the first metal film in the first region and on the insulating film in the second region; and flattening top surfaces in the first region and the second region by performing a flattening process. 
         [0010]    According to still another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate; forming a first metal film on the insulating film; removing the first metal film in the second region; forming a second cap film on the first metal film in the first region and on the insulating film in the second region; forming a second metal film on the second cap film; and flattening top surfaces in the first region and the second region by performing a flattening process so that the second cap film is removed in the first region. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIGS. 1A to 1D  illustrate a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 
           [0012]      FIGS. 2A to 2D  illustrate the method according to the first embodiment. 
           [0013]      FIGS. 3A to 3C  illustrate a method for manufacturing a semiconductor device according to a second embodiment of the present invention. 
           [0014]      FIGS. 4A to 4E  illustrate a method for manufacturing a semiconductor device according to a comparative example. 
           [0015]      FIGS. 5A to 5E  illustrate the method according to the comparative example. 
           [0016]      FIGS. 6A to 6D  illustrate the method according to the first embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Manufacturing Method Tried by the Inventor 
       [0017]    A comparative-example method for respectively fabricating different metal gates for an nMIS and a pMIS by using a first lithography for opening only a pMIS region and a second lithography for opening only an nMIS region which has been tested by the inventor will be described with reference to  FIGS. 4A to 5E . 
         [0018]    As shown in  FIG. 4A , a gate insulating film  105  is formed on a p well  103  to be an nMIS region and an n well  104  to be a pMIS region which are isolated by an STI (Shallow Trench Isolation)  102  over a silicon substrate  101 . Next, as shown in  FIG. 4B , a first metal gate material such as a titanium nitride film  106 , which is suitable for the nMIS, is formed on the gate insulating film  105 , and a silicon nitride film  107  to be a first hard mask material is formed on the titanium nitride film  106 . 
         [0019]    Then, as shown in  FIG. 4C , a resist  108  is formed on the silicon nitride film  107 , an opening for exposing the pMIS region is formed on the resist  108  by a lithography technique (a first lithography) so that the resist  108  is used as a mask to remove the silicon nitride film  107  on the pMIS region through an etching technique, thereby forming a first hard mask. 
         [0020]    Subsequently, as shown in  FIG. 4D , the resist  108  is removed, and the titanium nitride film  106  on the pMIS region is removed by etching using the first hard mask  107  as a mask. 
         [0021]    Next, as shown in  FIG. 4E , a second metal gate material such as a tungsten film  109 , which is suitable for the pMIS, is formed on the gate insulating film  105  provided on the pMIS region and the silicon nitride film  107  provided on the nMIS region, and a silicon nitride film  110  to be a second hard mask is laminated on the tungsten film  109 . 
         [0022]    Thereafter, as shown in  FIG. 5A , a resist  111  is formed on the silicon nitride film  110 , and an opening for exposing the nMIS region is formed on the resist  111  by a lithography technique (a second lithography) Subsequently, as shown in  FIG. 5B , the resist  111  is used as a mask to remove the silicon nitride film  110  in the nMIS region by an etching technique, thereby forming the second hard mask. 
         [0023]    Subsequently, as shown in  FIG. 5C , the resist  111  is removed, and the tungsten film  109  on the nMIS region is removed by etching using the second hard mask  110  as a mask. Thereafter, the first and second hard masks  107  and  110  are removed. 
         [0024]    As shown in  FIG. 5D , a polysilicon film  114  is formed on the nMIS region and the pMIS region. Furthermore, a resist  115  is formed on the polysilicon film  114 , and a gate wiring pattern is formed on the nMIS region and the pMIS region by a lithography technique (a third lithography). 
         [0025]    Next, as shown in  FIG. 5E , using the resist  115  as a mask, an anisotropic etching over the polysilicon film  114  and a titanium nitride film  106  in the nMIS region and the polysilicon film  114  and the tungsten film  109  in the pMIS region is performed, and the resist  115  is removed to finish a gate structure. 
         [0026]    A gate electrode of the nMIS has a laminated structure of the titanium nitride film  106  and the polysilicon film  114 . On the other hand, a gate electrode of the pMIS has a laminated structure of the tungsten film  109  and the polysilicon film  114 . Thus, a gate structure using different materials for the nMIS and the pMIS is finished. 
         [0027]    According to the comparative-example method, between the first lithography for opening only the pMIS region and the second lithography for opening only the nMIS region, an alignment shift is generated due to a precision limitation of the lithography. The alignment shift is generated in the case where the resist positions in the first lithography and the second lithography overlap each other or separated from each other. 
         [0028]    In the case where the resist positions overlap, the titanium nitride film  106  and the silicon nitride film  107  overlap each other at a circular portion  116  as shown in a broken line of  FIG. 5C . When the polysilicon film  114  is deposited as shown in  FIG. 5D , a height at the portion is increased more greatly than in the other portions. As a result, the focus precision in a third lithography might be deteriorated, and a residue  112  might be generated by an insufficiently etching through the anisotropic etching for forming a gate structure. 
         [0029]    On the other hand, in the case where the resist positions are separated, an excessively etched portion is remained at a circular portion  117  as shown in a broken line of  FIG. 5C , thereby generating a step portion. As a result, the focus precision in the third lithography might be deteriorated, and a disconnection  113  might be generated by the excessive etching. 
         [0030]    In the comparative-example method, in the first lithography and the second lithography, an alignment shift of the mask position is caused. As a result, at a wiring step in the third lithography, the residue or the disconnection might be generated. In order to solve the problem, the inventor supposed embodiments according to the invention which will be described below. The embodiments will be described below with reference to the drawings. 
       FIRST EMBODIMENT 
       [0031]      FIGS. 1A to 2D  are sectional views showing a process for forming a gate electrode of a CMISFET according to a first embodiment of the invention. 
         [0032]    First of all, as shown in  FIG. 1A , an element region insulated by an element isolating region  2  such as an STI is formed on a main surface of a silicon substrate  1 , that is, a p well  3  is formed in an nMIS region and an n well  4  is formed in a pMIS region. The p and n wells may be formed to be deeper than the element isolating region  2 . Then, a gate insulating film  5  is formed on the p and n wells  3  and  4  or the whole main surface of the silicon substrate  1 . For example, as the gate insulating film  5 , an insulating film, such as a hafnium oxide film, a hafnium oxynitride film and a hafnium silicate nitride film, which has a higher dielectric constant than a silicon oxide film or a silicon oxynitride film is used. The high-dielectric constant insulating film may be formed on the silicon oxide film to be used as a laminated-layer gate insulating film, and may be directly formed on the silicon substrate  1  to be used as a single-layer gate insulating film. 
         [0033]    In the embodiment, the gate insulating film  5  is formed in a laminated-layer structure by forming the silicon oxide film through a thermal oxidation process or a radical oxidation process, and by forming the hafnium oxide film thereon through an MOCVD (Metal Organic Chemical Vapor Deposition) process. 
         [0034]    Next, as shown in  FIG. 13 , a metal gate electrode material, such as a titanium nitride film  6 , for the nMIS is formed in a thickness of 20 nm on the gate insulating film  5 , and a first polysilicon film  7  is formed on the titanium nitride film  6  in a thickness of 100 nm. 
         [0035]    Subsequently, as shown in  FIG. 1C , the first polysilicon film  7  is coated with a resist  8 , and the resist  8  is selectively opened at the pMIS region by a lithography technique. The first polysilicon film  7  on the pMIS region is removed  8  by an etching technique such as RIE (Reactive Ion Etching) using the opened resist as a mask. 
         [0036]    Then, as shown in  FIG. 1D , the resist  8  is removed using a solvent, and the titanium nitride film  6  on the pMIS region is removed by etching using the first silicon film  7  as a mask. At this time, the gate insulating film  5  is not removed but left. 
         [0037]    As an etching treatment for the titanium nitride film  6 , it is more preferable to use a wet etching as compared with the case using a plasma etching such as the RIE to suppress an influence on the gate insulating film  5 . 
         [0038]    Next, as shown in  FIG. 2A , next, a metal gate electrode material, such as a tungsten film  9 , for the pMIS is formed in a thickness of 20 nm on the gate insulating film  5  in the pMIS region and the polysilicon film  7  in the nMIS region, and a second polysilicon film  10  is formed in a thickness of 200 nm on the tungsten film  9 . The thickness of the second polysilicon film  10  may be adjusted to obtain a desirable flatness at a CMP step to be performed immediately thereafter. 
         [0039]    In a portion in which the tungsten film  9  and the second polysilicon film  10  are provided in contact with each other, they react to each other when a heat treatment is performed at a subsequent step and tungsten silicide is thus formed. In the case where a device performance is not particularly influenced, they may be maintained without performing the heat treatment. When the device performance might be considered to be influenced, the reaction may be prevented by forming a barrier metal, such as a tungsten nitride film and a tantalum nitride film, in a thickness of approximately several nm between the tungsten film  9  and the second polysilicon film  10 . 
         [0040]    Subsequently, as shown in  FIG. 2B , a flattening by a CMP is performed. In this case, polishing is executed until at least the second polysilicon film  10  and the tungsten film  9  are removed in the nMIS region, and the flattening is performed so that upper surfaces of the first polysilicon film  7  on the nMIS region and the second polysilicon film  10  on the pMIS region are on the same level. As a polishing material, a material capable of polishing the second polysilicon film  10  and the tungsten film  9  at an equal speed is preferable. 
         [0041]    The flattening process may be performed in two-steps. That is, the second polysilicon film  10  is polished using the tungsten film  9  as a stopper, and then, the tungsten film  9  is polished using the first polysilicon film  7  as a stopper. 
         [0042]    After the CMP has been performed, a laminated structure including the gate insulating film  5 , the titanium nitride film  6  and the first polysilicon film  7  is formed on the nMIS region, and a laminated structure including the gate insulating film  5 , the tungsten film  9  and the second polysilicon film  10  is formed on the pMIS region. The thicknesses of both the laminated structures are adjusted to be almost equal to each other. 
         [0043]    Then, as shown in  FIG. 2C , a resist  11  is deposited, and the gate structures of the nMIS and pMIS are patterned by a lithography technique. 
         [0044]    Subsequently, as shown in  FIG. 2D , an anisotropic etching is performed over the second polysilicon film  10 , the tungsten film  9  and the gate insulating film  5  in the pMIS region and the first polysilicon film  7 , the titanium nitride film  6  and the gate insulating film  5  in the nMIS region, by use of the resist  11  a mask, and then, the resist  11  is removed so that a gate structure is finished. 
         [0045]    According to the embodiment, the following advantages can be obtained. Both of the nMIS and pMIS regions are flattened by the CMP after the metal gate electrode materials have been formed respectively on both regions. As a result, a defect caused by the mask position shift in the lithography is prevented from being occurred. 
         [0046]    Although the HfO film is used as the high-dielectric-constant insulating film of the gate insulating film  5  in the embodiment, the other material, such as an HfON film, a Zro film, a ZrON film, a HfSiO film, an HfSiON film, a ZrSiO film, a ZrSiON film, an HfZrO film, an HfZrON film, an HfZrSiO film, an HfZrSiON film, an HfAlSiON film and a ZnAlSiON film, may be used. 
         [0047]    Although the tungsten film and the titanium nitride film are used as the metal gate electrode materials in the embodiment, other metal materials, such as Ru, RuO, NiSi, PtTiN, TaC, TaN, Mo, W, WN and PtSi, may be used. 
         [0048]    In the embodiment, a step of forming a cap film may be added. For example, when the nMIS metal gate electrode material is formed as shown in  FIG. 1B , an nMIS cap film  201  may be formed on the gate insulating film  5 , and the titanium nitride film  6  may be formed thereon as shown in  FIG. 6A . In this case, an opening process in the pMIS region shown in  FIG. 1C  is performed to remove also the nMIS cap film  201  as shown in  FIG. 6B . 
         [0049]    For example, when the pMIS metal gate electrode material is formed in the pMIS region as shown in  FIG. 2A , a pMIS cap film  202  may be formed on the gate insulating film  5  and on the polysilicon film  7 , and the tungsten film  9  may be formed thereon as shown in  FIG. 6C . In this case, a flattening process shown in  FIG. 2B  is performed to remove the pMIS cap film  202  in the nMIS region as shown in  FIG. 6D . 
         [0050]    As a material for the nMIS cap film  201  and the pMIS cap film  202 , for example, one or plural film of La, Al, Sc, Sr, Er, Mn, Mg, Tb, Yb, Y, Dy, Pt, W, Ru, Ta and C may be used. One or both of the nMIS cap film and the pMIS cap film may be formed. 
         [0051]    In the embodiment, the polysilicon film is formed on the metal gate electrode to form a silicide film on the polysilicon film at a subsequent step to reduce a resistance. When the low-resistance material is used or when a low resistance can be realized only by the metal gate electrode itself, the polysilicon film may be omitted. 
       SECOND EMBODIMENT 
       [0052]    Next, description will be given to a method for manufacturing a CMISFET according to a second embodiment of the invention. In the embodiment, when the flattening is performed to process upper surfaces of a first polysilicon film on an nMIS region and a second polysilicon film on a pMIS region to be the same level, an etchback technique is used in place of the CMP flattening technique that is used in the first embodiment. The other manufacturing processes, the materials and structures of films are substantially same as those in  FIG. 2A  and previous drawings according to the first embodiment, description of repetitive portions will be omitted. 
         [0053]    After a second polysilicon film  10  is formed, a resist  12  is formed on the second polysilicon film  10  by a coating method, for example, as shown in  FIG. 3A . Here, the resist  12  is formed to have a flat top surface. Subsequently, as shown in  FIG. 3B , the resist  12 , the second polysilicon film  10  and a tungsten film  9  are flattened by the etchback technique. 
         [0054]    For example, in the etchback technique, the resist  12  is formed to have a flat top surface, and an etching condition is adjusted so that etching rates for the resist  12 , the second polysilicon film  10  and the tungsten film  9  are substantially equal by selecting an etching gas. 
         [0055]    Then, as shown in  FIG. 3C , patterning for gate structures of the nMIS and the pMIS is performed and the second polysilicon film  10 , the tungsten film  9  and a gate insulating film  5  in the pMIS region and a first polysilicon film  7 , a titanium nitride film  6  and the gate insulating film  5  in the nMIS region are subjected to anisotropic etching to finish a gate structure. 
         [0056]    Also in the second embodiment, the same advantages as those in the first embodiment can be obtained. Similarly to the first embodiment, the step of forming a cap film may be added. 
         [0057]    Although the p well  3  and the n well  4  are formed to be shallower than the element isolating region  2  in the second embodiment, the p well  3  and the n well  4  may be formed to be deeper than the element isolating region  2  as similar to the first embodiment. 
         [0058]    The invention is not restricted to the embodiments but various changes can be made without departing from the scope of the invention. For example, while the first metal gate electrode material for the N type MISFET is formed earlier than the second metal gate electrode material for the P type MISFET in the embodiment, the order may be reversed to form the metal gate electrode material for the P type MISFET earlier.