Abstract:
A reference voltage generation circuit, including a first current source in series with a first bipolar transistor; a second current source in series with a first resistor; a third current source in series with a second bipolar transistor, the third current source being assembled as a current mirror with the first current source; a second resistor between the base of the second bipolar transistor and the junction point between the current source and the first resistor; and a fourth current source in series with a third resistor, the junction point between the fourth current source and the third resistor defining a reference voltage terminal.

Description:
BACKGROUND 
     Technical Field 
     The present disclosure relates to a circuit for gene-rating a reference voltage under a power supply voltage smaller than 1 V. 
     Description of the Related Art 
       FIG. 1  hereof corresponds to  FIG. 3  of French patent application 2969328 of Dec. 17, 2010 (B10442). This drawing shows an example of a circuit generating a reference voltage in the order of 0.1 V. This circuit comprises, between two terminals of application of a power supply voltage V DD  and ground GND:
         a MOS transistor M 1  in series with a bipolar transistor Q 1 , of type NPN, having its emitter on the side of ground GND;   a MOS transistor M 2  in series with a bipolar transistor Q 2  (of type NPN, having its emitter on the side of ground GND) and with a resistor R 1 , the emitter of transistor Q 2  defining an output terminal of the circuit providing a reference voltage V OUT , transistors M 1  and M 2  being assembled as a current mirror; and   the power supply terminals of a follower assembly  3 .       

     The input of the follower assembly is connected to the collector of transistor Q 1  and its output is connected by an optional resistor R 2  to the base of transistor Q 2 . A resistive dividing bridge formed of resistors R 3  and R 4  in series is connected between the output terminal of follower assembly  3  and ground GND. The midpoint of this dividing bridge is connected to the base of transistor Q 1 . Resistor R 4  is connected between the base of transistor Q 1  and ground GND. 
     Due to the current mirror formed of MOS transistors M 1  and M 2 , transistors Q 1  and Q 2  receive the same collector current. 
     As indicated by the above-mentioned French patent application, reference voltage V OUT  can be written as follows, neglecting base current i b2  of transistor Q 2 :
 
 V   OUT =V BE1  *( R 4/ R 3)+( kT/q )* In ( p   2|1 ),  (1)
 
where V BE1  designates the base-emitter voltage of transistor Q 1 , k designates Boltzmann&#39;s constant, q designate the electron charge, T designates the temperature in Kelvin, and In(p 2|1 ) designates the natural logarithm of surface ratio p 2|1  between transistors Q 1  and Q 2  (p 2|1  being greater than 1).
 
     Follower assembly  3  is formed of a current source  4  and of a MOS transistor M 3 . The gate of transistor M 3  corresponds to the input of follower assembly  3  and the source of MOS transistor M 3  corresponds to the output of follower assembly  3 . The follower assembly has the voltage present on its input follow on its output and delivers the current necessary to drive the bases of transistors Q 1  and Q 2  and for resistor R 4 . This circuit has an infinite input impedance, and no current flows through the gate of MOS transistor M 3 . 
     The base currents of transistors Q 1  and Q 2  are equal (due to transistors Ml and M 2  assembled as a current mirror). Resistor R 2  is added to cancel the effect of the base currents on the reference voltage. The compensation will be optimal if the values of resistances R 2  and R 3  are equal. 
     Resistor R 1  sets the current in the two branches of the assembly. Power supply voltage V DD  can be written as:
 
 V   DD   =V   OUT   +V   BE2   +R 2 *i   b2   +V   4 ,   (2)
 
where V OUT  is the reference voltage generated by circuit, V BE2  is the base-emitter voltage of transistor Q 2 , and V 4  is the voltage drop across current source  4 .
 
     In practice, in current integrated circuit technologies, the base-emitter voltage of a bipolar transistor is in the order of 0.8 V and the drain-source voltage of a MOS transistor at saturation is in the order of 0.1 V. If a reference voltage V OUT  of 0.1 V is desired to be generated, formula (2) thus provides V DD =0.1+0.8+0.1=1 V, neglecting term R 2 *i b2 , which is much smaller than 0.1 V. 
       FIG. 2  hereof corresponds to  FIG. 2  of U.S. Pat. No. 7,408,400. This drawing shows an example of a circuit generating a reference voltage in the order of 0.1 V. This circuit comprises, between two terminals of application of a power supply voltage V DD  and ground GND:
         a current source  11  generating a current I 1  in series with a bipolar transistor Q 3 , of type NPN;   a current source  13  generating a current I 2  in series with a bipolar transistor Q 4 , of type NPN;   a current source  15  generating the same current I 1  as current source  11  in series with a bipolar transistor Q 5 , of type NPN, and with a resistor R 7 , the base of transistor Q 5  being connected to the collector of transistor Q 4 ; and   a bipolar transistor Q 6 , of type NPN, in series with a current source  17 , the base of transistor Q 6  being connected to the collector of transistor Q 5  and the emitter of transistor Q 6  being connected to the base of transistor Q 4 .       

     Resistor R 5  is connected between the base of transistor Q 3  and ground GND. A resistor R 6  is connected between the collector of transistor Q 4  and the base of transistor Q 3 . A bipolar transistor Q 7  is connected between terminal V DD  and the emitter of transistor Q 5 . The base of transistor Q 7  is connected to the collector of transistor Q 3 . The junction point of the emitters of transistors Q 5  and Q 7  forms output V OUT  of the circuit. 
     Transistors Q 3  and Q 5  receive a same collector current I i . As indicated by the above-mentioned US patent, reference voltage V OUT  can be written as follows:
 
 V   OUT   =V   BE3 *( R 6/ R 5)+( kT/q )* In ( p   5|3 ),   (3)
 
where V BE3  designates the base-emitter voltage of transistor Q 3 , k, q, and T have been previously defined, and p 5|3  designates the surface ratio between transistors Q 3  and Q 5  (p 5|3  being greater than 1).
 
     Power supply voltage V DD  can be written as:
 
 V   DD   =V   OUT   +V   BE7   +V   11 ,   (4)
 
where V OUT  is the reference voltage generated by circuit, V BE7  is the base-emitter voltage of transistor Q 7 , and V 11  is the voltage drop across current source  11 .
 
     In practice, in current integrated circuit technologies, the base-emitter voltage of a bipolar transistor is in the order of 0.8 V and the drain-source voltage of a MOS transistor at saturation is in the order of 0.1 V. If a reference voltage V OUT  of 0.1 V is desired to be generated, formula (4) thus provides V DD =0.1+0.8+0.1=1 V. 
     The power supply voltages of the circuits of  FIGS. 1 and 2  are greater than or equal to 1 V. 
     Further, in the circuits of  FIGS. 1 and 2 , if voltage V OUT  is desired to be increased by 1 V, the power supply voltage should increase by 1 V. 
     Recent circuits in CMOS technology operate under power supply voltages smaller than or equal to 1 V. The circuits of  FIGS. 1 and 2  can thus not be used since they require a power supply voltage greater than 1 V. 
     BRIEF SUMMARY 
     It would be desirable to provide a reference voltage generation circuit having a power supply voltage smaller than 1 V. 
     It would also be desirable to provide such a circuit capable of generating a reference voltage greater than 0.1 V. 
     Thus, an embodiment provides a circuit for generating a reference voltage, comprising, between first and second terminals of application of a power supply voltage: a first current source in series with a first bipolar transistor; a second current source in series with a first resistive element, the junction point between the second current source and the first resistive element being connected to the base of the first bipolar transistor; a third current source in series with a second bipolar transistor, the third current source being assembled as a current mirror with the first current source; a second resistive element between the base of the second bipolar transistor and the junction point of the current source and of the first resistive element; and a fourth current source in series with a third resistive element, the junction point of the fourth current source and of the third resistive element defining a third terminal providing the reference voltage, the fourth current source forming a current mirror with the second current source. 
     According to an embodiment, a fifth current source is connected between the first terminal and the third terminal, and a fourth resistive element is series-connected with the second bipolar transistor, the fifth current source forming a current mirror with the first current source. 
     According to an embodiment, the current sources are formed of MOS transistors. 
     According to an embodiment, the surface area of the collector of the second bipolar transistor is larger than the surface area of the collector of the first bipolar transistor. 
     The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIGS. 1 and 2 , previously described, illustrate two examples of circuits for generating a 0.1-V reference voltage; and 
         FIGS. 3 and 4  illustrate two embodiments of a circuit for generating a 0.1-V reference voltage. 
     
    
    
     DETAILED DESCRIPTION 
     The present description corresponds to the case of transistors in CMOS technology. It may however be applied to any other transistor technology or to a combination of different technologies. In the following, “PMOS transistor” will designate P-channel MOS transistors. 
       FIG. 3  illustrates an embodiment of a reference voltage generation circuit. This circuit comprises, between two supply terminals respectively providing a power supply voltage V DD  and of ground GND:
         a PMOS transistor M 4  in series with a bipolar transistor Q 8 , of type NPN, having its emitter on the side of ground GND;   a PMOS transistor M 5  in series with a resistor R 8 , the base of transistor Q 8  being connected to the drain of transistor M 5 ;   a PMOS transistor M 6  in series with a bipolar transistor Q 9 , of type NPN, the emitter being on the side of ground GND and transistors M 4  and M 6  being assembled as a current mirror; and   a PMOS transistor M 7  in series with a resistor R 10 , the gate of transistor M 7  being connected to the collector of transistor Q 9  and to the gate of transistor M 5 , transistors M 5  and M 7  thus forming a current mirror, the drain of transistor M 7  forming a reference voltage terminal V OUT .       

     A resistor R 9  is connected between the base of transistor Q 9  and the drain of transistor M 5 . 
     The current mirror formed by transistors M 4  and M 6  results in that transistors Q 8  and Q 9  receive equal collector currents I c8  and I c9 . The circuit is designed so that transistor M 5  is in saturation state. 
     Power supply voltage V DD  can be written as:
 
 V   DD   =V   BE8   +V   M5 ,   (5)
 
where V BE8  is the base-emitter voltage of transistor Q 8 , and V M5  is the drain-source voltage of transistor M 5 .
 
     In practice, in current integrated circuit technologies, the base-emitter voltage of a bipolar transistor is in the order of 0.8 V and the drain-source voltage of a 
     MOS transistor at saturation is in the order of 0.1 V. Formula (5) thus provides V DD =0.8+0.1=0.9 V. 
     There appears from formula (5) that voltage V DD  is smaller than 1 V and that it is independent from value V OUT , conversely to the cases of circuits of  FIGS. 1 and 2  and of formulas (2) and (4). 
     Further, transistor M 7  operates in linear state when reference voltage V OUT  is smaller than voltage V BE8  ( 0 .8 V). For a 0.9V power supply voltage, it is thus possible to set reference voltage V OUT  in a range from 0.1 V to 0.8 V. 
     Reference voltage V OUT  can be written as:
 
 V   OUT   =R 10 *I   M7 ,   (6)
 
where I M7  is the current in resistor R 10 . Transistors M 5  and M 7  being assembled as a current mirror, current I M7  is the copy of current I M5 .
 
     Current I M7  can be written as:
 
 I   M7   =I   M5 =( V   BE8   /R 8)+ i   b8   +i   b9 ,   (7)
 
where i b8  and i b9  are the base currents of transistors Q 8  and Q 9 . The collector currents of transistors Q 8  and Q 9  being equal, currents i b8  and i b9  are equal.
 
     Current i b9  can be written as:
 
 i   b9   =ΔV   BE   /R 9,
 
where ΔV BE =V BE8 −V BE9 =(kT/q)*ln(p 9|8 ), V BE8  and V BE9  designate the base-emitter voltages of transistor Q 8  and Q 9  and In(p 9|8 ) designates the natural logarithm of surface area ratio p 98  between transistors Q 8  and Q 9  (p 9|8  being greater than 1).
 
     Reference voltage V OUT  can be written as:
 
 V   OUT   =R 10*[( V   BE8   /R 8)+(2 *kT/q*R 9)* ln ( p   9|8 )],   (8)
 
     An advantage of such a circuit is that power supply voltage V DD  is 0.9 V only. This circuit may be used in recent circuits in CMOS technology operating under power supply voltages smaller than 1 V. 
     Another advantage is that for a power supply voltage of V DD  of 0.9 V, the circuit can generate a reference voltage V OUT  in the range from 0.1 V to 0.8 V. 
     However, as shown by formulas (6) and (7), reference voltage V OUT  depends on base current i b9  of transistor Q 9 . Current collector i c9  of transistor Q 9  is determined by relation i c9 =β*i b9 , β being the gain of transistor Q 9 . Gain β varies along with temperature and manufacturing dispersions. Currents i c8  and i c9  vary accordingly. Voltage V BE8  varies according to current Ic 8 . According to formula (8), voltage V OUT  depends on V BE8 . The variation of gain β of transistor Q 9  thus degrades the accuracy of the generated reference voltage V OUT . As an example, for a variation of gain β of transistor Q 9  by a factor 2, voltage V OUT  varies by approximately 2%. 
     A reference voltage V OUT  independent from the variation of current gain β would be desired. 
       FIG. 4  illustrates another embodiment of a reference voltage generation circuit having the advantages of the embodiment of  FIG. 3  while avoiding the possible variation of V OUT  with gain β. 
     This circuit comprises the elements of the circuit of  FIG. 3  designated with the same reference numerals. Further, a resistor R 11  is placed between the emitter of transistor Q 9  and ground GND and a PMOS transistor M 10  is connected between power supply voltage V DD  and the drain of transistor M 7 . The source of transistor M 10  is connected to voltage V DD . Transistor M 10  forms a current mirror with transistors M 4  and M 6 . 
     Power supply voltage V DD  remains equal to:
 
 V   DD   =V   BE8   +V   M5 ,   (5)
 
     Reference voltage V OUT  can be written as:
 
 V   OUT   =R 10 *I   R10   =R 10*( I   M7   +I   M10 )   (9)
 
where I R10  is the current in resistor R 10  and I M10  is the drain current of transistor M 10 . Transistors M 4 , M 6 , and M 10  being assembled as a current mirror, currents i c8 , i c9 , and I M10  are equal. Transistors M 5  and M 7  being assembled as a current mirror, currents I M5  and I M7  are equal.
 
     Current i c9  can be written as:
 
 i   c9   =V   E   /R 11− i   b9 ,   (10)
 
where V E  is the voltage across resistor R 11 .
 
     Voltage V E  can be written as:
 
 V   E   =ΔV   BE   −R 9* i   b9 ,
 
where ΔV BE =V BE8 −V BE9 =(kT/q)*ln(p 9|8 ).
 
     Current i c9  can be written as:
 
 i   c9   =ΔV   BE   /R 11 −i   b9 *(1+ R 9/ R 11).
 
     Current I R10  can thus be written as:
 
 I   R10   =V   BE8   /R 8+2* i   b9   +ΔV   BE   /R 11− i   b9 *(1+ R 9/R11).
 
     If resistors R 9  and R 11  are equal, current I R10  no longer depends on current i b9 , I R10  can be written as:
 
 I   R10   =V   BE8   /R 8+Δ V   BE   /R 11
 
     Reference voltage V OUT  can thus be written as:
 
 V   OUT   =R 10*[( V   BE8   /R 8)+( kT/q*R 9)* In ( p   9|8 )]  (11)
 
     As shown by formula ( 11 ), current i c9  no longer depends on gain β, conversely to the case of the circuit of  FIG. 3 . Voltage V BE8  is no longer affected by the variation of gain β and, since voltage V OUT  depends on V BE8 , the accuracy of voltage V OUT  is no longer affected by gain β. 
     An advantage of such a circuit is that a possible variation of gain β of transistor Q 9  does not affect the accuracy of reference voltage V OUT . 
     Although term resistor has here been used to designate elements R 1  to R 11 , it should be noted that these elements may be formed of any resistive element such as a resistor-connected MOS transistor. 
     The resistance values may be in the range from 1 to 100 kΩ, for example, 50 kΩ. 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present disclosure. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.