Abstract:
A technique for implementing impedance matching circuits  100  that use the transfer functions of each line impedance model. This technique allows implementation of an impedance match for a diverse number of line impedances reusing the same circuit  100  topology, by simply adjusting coefficients to accommodate different line impedances.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates generally to subscriber line interface circuits, and more particularly, to a generic line impedance matching circuit using decomposed configurable transfer functions.  
           [0003]    2. Description of the Prior Art  
           [0004]    Impedance matching is a very important function of any equipment that is attached to copper twisted pairs. A line-matched impedance helps control reflections and echoes in the line which then helps maintain good quality of service.  
           [0005]    Previous impedance matching functions have been performed using hybrid transformers and a discrete matching impedance, and more recently, using Subscriber Line Interface Circuits (SLICs) with op-amps and a discrete matching feedback impedance. These methods have required large discrete components and large amounts of board space. The large number of different standardized line impedances (more than 24), and the need for custom line impedance matching make the design of a generic integrated impedance matching circuit very difficult and costly. A traditional SLIC implementation is illustrated in FIG. 1( a ). The SLIC  10  provides the Tip and Ring function as well as the sense function required to perform an impedance match at the Tip Ring via the impedance matching op-amp network  20 . This traditional implementation necessitates the requirement for a new op-amp network  20  for each different line impedance. The traditional op-amp impedance matching circuit (network)  20  can be represented as a transfer function given by H(S) as depicted in FIG. 1( b ).  
           [0006]    In view of the foregoing, it would be desirable and advantageous to provide a simple and inexpensive scheme to reuse the same circuit topology for implementing an impedance match for a diverse number of line impedances.  
         SUMMARY OF THE INVENTION  
         [0007]    Impedance matching in the digital domain has been limited to slower sampling digital implementations requiring external discrete resistors, and/or multiple stages of complex digital filtering. These known implementations have a very limited range with regard to gain and filter functions that limits the range of impedance matching. Some known impedance matching (IM) implementations have a combinational analog/digital approach with the digital portion itself decomposed into two to three decimated loops following an ADC, imposing even higher delays in the IM path.  
           [0008]    The present invention is directed to a technique for implementing impedance matching circuits that uses the transfer functions of each line impedance model. This technique allows implementation of an impedance match for a diverse number of line impedances reusing the same circuit topology, by simply adjusting coefficients to accommodate different line impedances.  
           [0009]    In one aspect of the invention, a generic impedance matching circuit is implemented using decomposed configurable transfer functions.  
           [0010]    In another aspect of the invention, a generic impedance matching circuit is implemented to perform impedance matching for a variety of line impedance models and allow integration into the digital core.  
           [0011]    In yet another aspect of the invention, a generic impedance matching circuit is provided by decomposing a matching function into its base transfer functions and implementing as either simple analog gain and/or a digital transfer function.  
           [0012]    In still another aspect of the invention, a generic impedance matching circuit is provided by representing the reactive components of a line impedance as a transfer function in the digital domain, and then processing the matching signal in the digital domain to eliminate the need for a large discrete capacitor.  
           [0013]    In still another aspect of the invention, a generic impedance matching circuit is provided to support all International Telecommunication Union, ITU-T line impedance models, by allowing for custom impedance matching models using the same circuit.  
           [0014]    In still another aspect of the invention, a generic impedance matching circuit is implemented using separate analog impedance matching gain and impedance matching filter elements to alleviate the need for a faster sampling clock as compared to an all-digital solution.  
           [0015]    One embodiment of the invention is directed to a line impedance matching circuit comprising no more than one analog path having an output, and no more than one digital path having an output, wherein the no more than one analog path output and the no more than one digital path output are selectively summed to provide impedance matching associated with a plurality of subscriber line interfaces.  
           [0016]    Another embodiment of the invention is directed to a line impedance matching circuit comprising a circuit having an analog path and a digital path, wherein the analog path and the digital path are combined to selectively provide a plurality of decomposed configurable transfer functions selected from the group consisting of a simple analog gain, and a digital domain transfer function.  
           [0017]    Still another embodiment of the invention is directed to a method of impedance matching comprising the steps of providing a generic line impedance matching circuit comprising a circuit having an analog path and a digital path, wherein the analog path and the digital path are combined to selectively provide a plurality of decomposed configurable transfer functions; and selecting transfer function coefficients to provide an impedance match associated with a prescribed subscriber line.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    Other aspects, features and advantages of the present invention will be readily appreciated, as the invention becomes better understood by reference to the following detailed description, when considered in connection with the accompanying drawing figures wherein:  
         [0019]    FIGS.  1 ( a ) and  1 ( b ) illustrate an impedance matching technique commonly associated with Subscriber Line Interface Circuits; and  
         [0020]    [0020]FIG. 2 illustrates an impedance matching technique for use with Subscriber Line Interface Circuits according to one embodiment of the present invention. 
     
    
       [0021]    While the above-identified drawing figures set forth particular embodiments, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    Four distinct types of transfer functions exist for the ITU-T prescribed line impedances. These prescribed line impedances are made up of a combination of a resistor Rs in series with a resistor Rp in parallel with a capacitor Cp. The final impedance match must account for the case where protection resistors Rprot are used just before the input to the SLIC, by subtracting the resistance of the protection resistors from the series resistor Rs. The four distinct types of transfer functions are set forth below as Cases 1-4, wherein the ± is dependent upon various SLIC specifications.  
                 Case                 1     :                            Z   =            Rs   ,              resistive                 case                 only   ,              Hg                   H        (   S   )       =            ±       Rs   -     2      Rprot       Rin                       Case                 2     :                              Z   =            Rx   +     Cp   ,              resistor                 in                 series                 with                 a                 capacitor   ,              Hg     +     Hf        (   S   )                                    H        (   S   )       =            ±     [         Rs   -     2      Rprot       Rin     +     1   RinCpS       ]                       Case                 3     :                            Z   =              Rs   +   Rp     //     Cp   ,              resistor                 in                 series                 with                 parallel                 resistor                     and                 capacitor   ,              Hg     +     Hf        (   S   )                     H        (   S   )       =            ±     [         Rs   -     2      Rprot       Rin     +     Rp     Rin                   (     RpCpS   +   1     )           ]                       Case                 4     :                            Z   =            Rp   //     Cp   ,              no                 series                 resistor   ,              parallel                 resistor                 and                 capacitor   ,                Hf   (   S   )                       H        (   S   )       =            ±     [     Rp     Rin        (     RpCpS   +   1     )         ]                                   
 
         [0023]    The foregoing transfer functions can be separated into a gain part Hg, and a frequency dependent part Hf(S). The frequency dependent parts have an S-domain transfer function that belongs to a family of b/(S+a) low pass functions. These S-domain transfer functions can be implemented in the digital Z-domain by performing a bilinear transform represented by  
           Hf        (   S   )       ⇒     Hf        (   Z   )         =         A   0     +       A   1          Z     -   1               B   0     -       B   1          Z     -   1                                   
 
         [0024]    [0024]FIG. 2 is a block diagram illustrating a final implementation of an impedance matching circuit  100  for use with Subscriber Line Interface Circuits according to one embodiment of the present invention. Circuit  100  can be seen to include a transmit programmable gain amplifier, transmit programmable gain amplifier (Tx PGA)  102 , Impedance Matching Gain  104 , an Anti-Alias Filter (AAF)  106 , an analog-to-digital converter (ADC)  108 , a Z-Domain Impedance Matching Filter  110 , a Digital Summing Node  112 , a digital-to-analog converter (DAC)  114 , an Image Reject Filter (IRF)  116 , a receive programmable gain amplifier (RxPGA)  118 , and an Analog Summing Node  120 .  
         [0025]    The gain portion Hg of the transfer functions discussed herein before will be implemented by a combination of the TxPGA  102  and the Impedance Matching Gain block  104 . The frequency dependent portion Hf(S) will be implemented by a combination of the TxPGA  102 , the AAF  106 , ADC  108 , the Z-Domain Impedance Matching Filter  110 , DAC  114 , IRF  116 , and the RxPGA  118 . Although settings for the filters  106 ,  110 ,  116  and gain stages  102 ,  104 ,  118  can be set to any arbitrary value, finite values must be chosen to reflect real line impedances and implementations to correctly emulate the H(S) function. The gain component Hg and frequency dependent component Hf(S) portions of the transfer functions emulated via impedance matching circuit  100  are now discussed herein below with reference to cases 1-4 described above.  
         [0026]    Case 1:  
         [0027]    H(S) is just a gain component and does not have any frequency dependent components. In this case, only the Impedance Matching Gain block  104  is used. The Z-Domain Impedance Matching Filter  110  is not used and can be disconnected. The gain through TxPGA  102  and the Impedance Matching Gain block  104  must then be equivalent to the required Hg.  
         [0028]    Case 2 and Case 3:  
         [0029]    H(S) is comprised of a gain portion Hg and a low pass portion Hf(S). The Hg portion must be accounted for using TxPGA  102  and the Impedance Matching Gain block  104  such as done in Case 1 discussed above. The Hf(S) function must be implemented by cascading TxPGA  102 , AAF  106 , ADC  108 , the Z-Domain Impedance Matching Filter  110 , Digital Summing Node  112 , DAC  114 , IRF  116  and RxPGA  118 . The Hf(S) function frequency dependency generally will be implemented by the Z-Domain Impedance Matching Filter  110 ; but the overall gain will be accounted for in frequency responses will be accounted for in the frequency responses determined by TxPGA  102 , AAF  106 , ADC  108 , the Z-Domain Impedance Matching Filter  110 , Digital Summing Node  112 , DAC  114 , IRF  116  and RxPGA  118 . The overall response then is represented as H(S)=Hg+Hf(S) as discussed herein before.  
         [0030]    Case 4:  
         [0031]    H(S) is simply the low pass function Hf(S). Hg is not required; and therefore, the Impedance Matching Gain block  104  can now be disconnected. Hf(S) will then be implemented by the cascaded responses of TxPGA  102 , AAF  106 , ADC  108 , the Z-Domain Impedance Matching Filter  110 , Digital Summing Node  112 , DAC  114 , IRF  116  and RxPGA  118 .  
         [0032]    In summary explanation, the implementations discussed above with reference to Cases 1-4 are generally equivalent to H(S) within some prescribed mismatch in amplitude and phase, and so offer a viable solution for implementing a generic line impedance matching circuit using decomposed configurable transfer functions.  
         [0033]    Impedance matching in the digital domain has historically been implemented using slower sampling techniques requiring external discrete resistors, and/or multiple stages of complex digital filtering resulting. These known impedance matching implementations have a very limited range regarding gain and filter functions, negatively affecting the range of impedance matching. Some know impedance matching implementations have a combinational analog/digital approach with the digital portion itself decomposed into two to three decimated loops following the ADC, imposing even higher delays in the impedance matching path.  
         [0034]    Design Considerations:  
         [0035]    The deciding factor when designing for impedance matching is the Return Loss (RL). Return Loss is usually defined as the −10 log of the reflection factor ρ r . Zr is the termination impedance; and Zo is the incident impedance. The reflection factor then is  
               ρ   r     =                Zr   -   Zo       Zr   +   Z0       ,              and                 the                 Return                 Loss                 is                 RL   =              -   10                       log        (       |     Zr   -   Zo     |       |     Zr   +   Zo     |       )       2                                   
 
         [0036]    For a perfectly matched system, the reflection factor is 0; and the Return Loss in infinite, such that  
               ρ   r     =                Vr   -   Vo       Vr   +   Vo       ,              and                 RL   =              -   10                       log        (       |     Vr   -   Vo     |       |     Vr   +   Vo     |       )       2     ,                                 
 
         [0037]    i.e. there is no reflection. The reflection factor may also be expressed as a ratio of the incident voltage Vo and the reflected voltage Vr.  
         [0038]    One primary concern when designing an impedance matching circuit is to maximize the Return Loss by minimizing the amplitude and phase distortions caused by the impedance matching circuit. The voltage Return Loss equation clearly shows that a difference in the voltage Vo across the incident impedance and the termination impedance (reflected) Vr, directly affects the Return Loss. It can also be shown that the Return Loss is dependent on the phase difference between the incident Vo and the termination Vr.  
         ρ   r     =         Vr   -   Vo       Vr   +   Vo       =         1   -     1      ∠0         1   +     1      ∠0         =         1   -     (       cos                 θ     +     j                 sin                 θ       )         (     1   +     (       cos                 θ     +     j                 sin                 θ       )       )       =         Re        (     1   -     cos                 θ       )       +     Im        (     sin                 θ     )             Re        (     1   +     cos                 θ       )       +     Im        (     sin                 θ     )                                       
 
         [0039]    It is also possible to look at the magnitude of the reflection factor to determine Return Loss.  
               Magnitude   2     =              Re   2     +     Im   2                   RL   =                -   10                     log        (           (     1   -     cos                 θ       )     2     +       sin   2        θ             (     1   +     cos                 θ       )     2     +       sin   2        θ         )         =                              -   10                     log        (       1   -     cos                 θ         1   +     cos                 θ         )         -     10                   log        (         sin   2        θ         cos   2        θ       )                       RL   =              -   10                     log        (       tan   2          θ   2       )                                     
 
         [0040]    The Return Loss can be affected by a phase difference between the incident and reflected voltages, which translates to a reactive difference in the line impedance and the matching impedance. There will be a specific phase difference for a given Return Loss. Intuitively, this angle will translate to different delays for different frequencies, longer delays at lower frequencies and shorter delays at higher frequencies. For this reason, among others, the present inventors split the impedance matching circuit  100  into two parts, an analog Impedance Matching Gain, Hg function, and a digital Z-domain Impedance Matching filter. The low frequency response of Hf(S) can be implemented in the low frequency digital core; while the wideband gain stage Hg is implemented in the analog process. The present inventors realized that a completely digital impedance matching scheme would require a much faster digital core (codec with less delays) to ensure that the overall group delay was minimal and did not adversely affect Return Loss. The amplitude and phase variation must therefore be kept to a minimum on all components to ensure an effective impedance matching circuit.  
         [0041]    The impedance matching circuit  100  discussed above with reference to FIG. 2 is an entirely integrated solution that is capable of matching all ITU-T country impedances; and also allows for custom line impedance matching. The impedance matching circuit  100  employs a faster ADC to reduce the digital processing delays, and a simple 1 st  order low-pass Z-Domain IIR filter  110  in the digital domain, summed to an analog gain path. Those skilled in the art will readily appreciate this single analog path, single digital path solution is simpler to use and program than previous realizations with comparable performance.  
         [0042]    In view of the above, it can be seen the present invention presents a significant advancement in the art of line impedance matching circuits and systems. In view of the foregoing descriptions, it should be apparent that the present invention also represents a significant departure from the prior art in construction and operation. However, while particular embodiments of the present invention have been described herein in detail, it is to be understood that various alterations, modifications and substitutions can be made therein without departing in any way from the spirit and scope of the present invention, as defined in the claims which follow.