Abstract:
A method for accessing shared memory, the method includes loading a private context ID into a private context ID register, where the first private context ID enables a thread to access a private memory region only accessible by the thread. The method further includes receiving, from the thread, a first request to access a shared memory region, loading a shared context ID into a shared context register, permitting, by a memory management unit (MMU), the thread to access the shared memory region using the shared context ID, and receiving, from the thread, a second request to disable access to the shared memory region. The method further includes removing, in response to the second request, the shared context ID from the shared context ID register, where after removing the shared context ID from the shared context ID register the thread is no longer able to access the shared memory region.

Description:
BACKGROUND 
       [0001]    Access to a shared memory region on a thread-level basis may be implemented using Translation Lookaside Buffers (TLBs). The process of changing which threads can access the shared memory region is facilitated using time-consuming TLB shoot-downs. Through alternate uses of a private context ID register in some systems, TLB shoot-downs may be reduced. Similarly, in other systems, alternate uses of a current page table register may also reduce TLB shoot-downs. 
       SUMMARY 
       [0002]    In general, in one aspect, the invention relates to a method for accessing shared memory, the method including: loading a first private context ID into a private context ID register, where the first private context ID enables a first thread to access a first private memory region only accessible by the first thread; receiving, from the first thread, a first request to access a shared memory region; loading a shared context ID into a shared context register; permitting, by a memory management unit (MMU), the first thread to access the shared memory region using the shared context ID; receiving, from the first thread, a second request to disable access to the shared memory region; and removing, in response to the second request, the shared context ID from the shared context ID register, where after removing the shared context ID from the shared context ID register the first thread is no longer able to access the shared memory region. 
         [0003]    In general, in one aspect, the invention relates to a method for accessing shared memory, the method including: receiving, from a first thread, a first request to access a shared memory region; loading a first page table address into a current page table register, where the first page table address enables the first thread to access a first private memory region associated with the first thread and to access the shared memory region; permitting, by a MMU, the first thread to access the shared memory region using the first page table address; receiving, from the first thread, a second request to disable access to the shared memory region; removing, in response to the second request, the first page table address from the current page table register, where after removing the first page table address from the current page table register the first thread is no longer able to access the shared memory region; and loading, after the removing, a second page table address into the current page table register, where the second page table address enables the first thread to access only the first private memory region. 
         [0004]    In general, in one aspect, the invention relates to a system for improving access permissions, the system including: a private context ID register; a shared context ID register; a shared memory region, where access to the shared memory region is managed by an operating system and a memory management unit (MMU); a first private memory region, where the first private memory region is managed by the operating system and the MMU; the operating system configured to: load a first private context ID into a private context ID register, where the first private context ID enables a first thread to access the first private memory region only accessible by the first thread; receive, from a first thread, a first request to enable access to the shared memory region; load the shared context ID into the shared context ID register; receive, from the first thread, a second request to disable access to the shared memory region; and remove, in response to the second request, the shared context ID from the shared context ID register, where after removing the shared context ID from the shared context ID register the first thread is no longer able to access the shared memory region; the memory management unit configured to: permit the first thread to access the shared memory region using the shared context ID; and an application including: the first thread configured to: send, to the operating system, the first request to enable access to the shared memory region; and send, to the operating system, the second request to disable access to the shared memory region. 
         [0005]    In general, in one aspect, the invention relates to a system for improving access permissions, including: a current page table register; a shared memory region, where access to the shared memory region is managed by an operating system and a memory management unit (MMU); a first private memory region, where the first private memory region is managed by the operating system and the MMU; the operating system configured to: receive, from a first thread, a first request to enable access to the shared memory region; load a first page table address into the current page table register, where the first page table address enables the first thread to access a first private memory region associated with the first thread and to access the shared memory region; receive, from the first thread, a second request to disable access to the shared memory region; remove, in response to the second request, the first page table address from the current page table register, where after removing the first page table address from the current page table register the first thread is no longer able to access the shared memory region; and load, after removing, a second page table address into the current page table register, where the second page table address enables the first thread access to only the first private memory region; the memory management unit (MMU) configured to: permit the first thread to access the shared memory region using the first page table; and an application including: the first thread configured to: send, to the operating system, the first request to enable access to the shared memory region; and send, to the operating system, the second request to disable access to the shared memory region. 
         [0006]    In general, in one aspect, the invention relates to a non-transitory computer readable medium including instructions, which when executed by a processor perform a method for accessing shared memory, the method including: loading a first private context ID into a private context ID register; where the first private context ID enables a first thread to access a first private memory region only accessible by the first thread; receiving, from the first thread, a first request to access a shared memory region; loading a shared context ID into a shared context register; permitting, by a memory management unit (MMU), the first thread to access the shared memory region using the shared context ID; receiving, from the first thread, a second request to disable access to the shared memory region; and removing, in response to the second request, the shared context ID from the shared context ID register, where after removing the shared context ID from the shared context ID register the first thread is no longer able to access the shared memory region. 
         [0007]    Other aspects of the invention will be apparent from the following description and the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0008]      FIG. 1  shows a system in accordance with one or more embodiments of the invention. 
           [0009]      FIG. 2  shows data structures of various system components in accordance with one or more embodiments of the invention. 
           [0010]      FIG. 3  shows a flowchart for initializing a shared memory region in accordance with one or more embodiments of the invention. 
           [0011]      FIG. 4  shows a flowchart for making an operating system request in accordance with one or more embodiments of the invention. 
           [0012]      FIG. 5  shows a system in accordance with one or more embodiments of the invention. 
           [0013]      FIG. 6  shows a flowchart for initializing a shared memory region in accordance with one or more embodiments of the invention. 
           [0014]      FIG. 7  shows a flowchart for making an operating system request in accordance with one or more embodiments of the invention. 
           [0015]      FIGS. 8A-B  show an example in accordance with one or more embodiments of the invention. 
           [0016]      FIGS. 9A-B  show an example in accordance with one or more embodiments of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Specific embodiments of the invention will now be described in detail with reference to the accompanying figures. In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description. 
         [0018]    In the following description of  FIGS. 1-9B , any component described with regard to a figure, in various embodiments of the invention, may be equivalent to one or more like-named components described with regard to any other figure. For brevity, descriptions of these components will not be repeated with regard to each figure. Thus, each and every embodiment of the components of each figure is incorporated by reference and assumed to be optionally present within every other figure having one or more like-named components. Additionally, in accordance with various embodiments of the invention, any description of the components of a figure is to be interpreted as an optional embodiment which may be implemented in addition to, in conjunction with, or in place of the embodiments described with regard to a corresponding like-named component in any other figure. 
         [0019]    In general, embodiments of the invention relate to a method that uses a shared context register or a page table address register to control access to a shared memory region. Further, embodiments of the invention restrict access to a shared memory region to individual threads, processes, or applications. Further, embodiments of the invention enable applications executing on the system to control which threads have access to the shared memory by instructing the operating system to load values into (or remove values from) the shared context register or page table address register. 
         [0020]    Referring to  FIG. 1 , a system in accordance with one embodiment of the invention is shown. The system includes a Memory Management Unit (MMU) ( 100 ) operatively connected to a private context ID register ( 102 ) and a shared context ID register ( 104 ), which are used to determine access privileges of a thread to a private memory region (not shown) and a shared memory region (not shown). The process of granting access to memory regions is improved through the use of a Translation Lookaside Buffer (TLB) ( 106 ). 
         [0021]    In one embodiment of the invention, the MMU ( 100 ) is a computer component that handles requests to access regions of memory. Further, the MMU may access the TLB ( 106 ), a private memory page table ( 110 ), and a shared memory page table ( 114 ). More specifically, the MMU may grant or deny a thread, process, or application access to a particular memory region based on the values in the private context ID register and the shared context ID register. The MMU may also include functionality to translate virtual addresses into corresponding physical addresses in memory. When the MMU processes a memory access request from a thread, the MMU checks the TLB ( 106 ) for a corresponding cache entry as explained below. If an entry is not found, the MMU uses the private memory page table ( 110 ) or shared memory page table ( 114 ) to determine the corresponding physical address. 
         [0022]    In one embodiment of the invention, the private context ID register ( 102 ) is a small amount of memory that is used to store a private context ID. A private context ID identifies a thread, process, or application that is accessing memory. Loading a predetermined private context ID into the private context ID register may grant a thread, process, or application access to a private memory region. Further, as described below, loading the private context ID may also allow the thread to access all TLB entries corresponding to the given private context ID. Each thread is associated with a private context ID that corresponds to a private memory region. The private context ID may be unique to a process or an application. Said another way, all of the threads in a process of an application may have the same private context ID, making the private context ID unique to the process. 
         [0023]    In one embodiment of the invention, the shared context ID register ( 104 ) is a small amount of memory that is used to store a shared context ID. A shared context ID corresponds to access privileges for a thread, process, or application to a particular shared memory region. Loading a shared context ID into the shared context ID register may grant a thread, process, or application access to the corresponding shared memory region. Further, as described below, loading the shared context ID may also allow the thread to see all TLB entries corresponding to the given shared context ID. 
         [0024]    In one embodiment of the invention, the TLB ( 106 ) caches previously translated virtual addresses and the corresponding physical addresses in memory. A TLB is a cache that stores a predetermined number of the most recent translations from virtual addresses to physical addresses by a thread associated with a given context ID. Said another way, a thread may use TLB entries associated with the same context ID to obtain a recently calculated physical address corresponding to the requested virtual address. The TLB stores these values in TLB entries ( 108 A and  108 B). For example, when a thread requests to access the shared memory region, the MMU may check the TLB ( 106 ) for an entry with the given shared context ID and requested virtual address. If a TLB entry exists, the MMU may determine the physical address without using a page table. 
         [0025]    In one embodiment of the invention, a private memory page table ( 110 ) is a table of mappings ( 112 A and  112 B) from virtual addresses to physical addresses in a private memory region. 
         [0026]    In one embodiment of the invention, a private memory region (not shown) is a region in memory that is designated as accessible by a thread or group of threads. The private memory region may be defined prior to use of the private context ID register. The private memory region may be organized into pages, each of which is the smallest unit of memory that the operating system may allocate. Based on  FIG. 1 , the private memory region includes the pages ( 118 A and  118 C) mapped ( 112 A and  112 B) by the private memory page table. 
         [0027]    In one embodiment of the invention, a shared memory page table ( 114 ) is a table of mappings ( 112 A- 112 D) from virtual addresses to physical addresses in a shared memory region. 
         [0028]    In one embodiment of the invention, a shared memory region (not shown) is a region in memory that is designated as accessible by multiple threads. The shared memory region may be defined prior to use of the shared context ID register. The shared memory region may be organized into pages. Based on  FIG. 1 , the shared memory region includes pages ( 118 B and  118 D) mapped ( 112 C and  112 D) by the shared memory page table. 
         [0029]    In one embodiment of the invention, the memory ( 116 ) is the total memory in hardware for the given computing device hosting the memory. As shown in  FIG. 1 , the memory includes the memory regions mapped by the shared memory page table and the private memory page table. 
         [0030]    The invention is not limited to the system shown in  FIG. 1 . 
         [0031]      FIG. 2  shows data structures of various system components in accordance with one or more embodiments of the invention. 
         [0032]    In one embodiment of the invention, a TLB entry ( 200 ) is an entry in the TLB that is used to store previously translated virtual addresses with corresponding physical address information. Each TLB entry includes a virtual address ( 202 ), a context ID ( 204 ), and a physical address ( 206 ). For a system, such as the one shown in  FIG. 1 , the context ID ( 204 ) may be a private context ID or a shared context ID depending on which memory region the thread accesses. For a system, such as the one shown in  FIG. 5 , the context ID may be a private page table address or hybrid page table address depending on which memory region the thread accesses. For example, in a system as in  FIG. 1 , if a thread with a private context ID of x1234 accesses a virtual address of x3045, the TLB entry may include a virtual address of x3045, a context ID of x1234, and a physical address of x0005. 
         [0033]    In one embodiment of the invention, a page table ( 208 ) stores the mappings between virtual addresses ( 202 A- 202 N) and corresponding physical addresses ( 210 A- 210 N) in a particular memory region. The page tables may be used to designate a set of virtual addresses that map to a set of physical addresses in a private or shared memory region. For example, if the private memory region includes virtual addresses x0000 to x0050, then the private memory page table may include mappings from a set of virtual addresses to a corresponding set of physical addresses from x0075 to x0005. 
         [0034]      FIGS. 3 and 4  show flowcharts in accordance with one or more embodiments of the invention. While the various steps in the flowchart are presented and described sequentially, one of ordinary skill will appreciate that some or all of the steps may be executed in different orders, may be combined or omitted, and some or all of the steps may be executed in parallel. In one embodiment of the invention, the steps shown in any of the flowcharts may be performed in parallel with the steps shown in any of the other flowcharts. 
         [0035]    Referring to  FIG. 3 , a flowchart for initializing a shared memory region in accordance with one or more embodiments of the invention is shown. In Step  300 , a shared memory region is identified by the application. For example, the application may define a shared memory region with virtual addresses from x00DD to x0100. 
         [0036]    In one embodiment of the invention, the application may also define a private memory region. Following the example above, the application may define a non-overlapping private memory region as having virtual addresses from x0110 to x0150. Alternatively, the application may define the shared memory region(s) and the operating system may define the private memory region(s). 
         [0037]    In Step  302 , the operating system is notified of the shared memory region for which access will be enabled and disabled. In one embodiment of the invention, any pre-existing TLB entries including an address in the shared memory region and a private context ID are removed. Further, any data structures, such as page tables, that grant access to the shared memory region from the private context ID are invalidated. For example, the operating system may be notified of the shared memory region with virtual addresses spanning from x00DD to x0100. 
         [0038]    In one embodiment of the invention, the operating system may select a shared context ID for the shared memory region. For example, the operating system may select a shared context ID of xAAAA for the shared memory region. 
         [0039]    In Step  304 , instructions are inserted into application code sections that require access to the shared memory region. Specifically, the instructions that generate a request to the operating system to enable access to the shared memory region are added at some point before the instructions that access the shared memory region. Said another way, the code section is modified to send a request to the operating system to enable access before a thread accesses the shared memory region. Further, the location of the instructions to send a request to the operating system to enable access may vary based on implementation. Specifically, the instructions may be located within the code section at any point prior to the instructions requiring access to the shared memory region or prior to the entire code section. 
         [0040]    Likewise, the instructions that generate a request to the operating system to disable access to the shared memory region are added after the instructions that access the shared memory region. Said another way, the code section is modified to send a request to the operating system to disable access after a thread accesses the shared memory region. The code section may be a routine in the application code. For example, if an application routine includes instructions to read from the shared memory region, instructions to send a request to enable access may be placed at some point before the read instructions and instructions to send a request to disable access may be placed at some point after the read instructions. Further, the location of the instruction to send a request to the operating system to disable access may vary based on implementation. Specifically, the instructions may be located within the code section at any point after the instructions requiring access to the shared memory region or after the entire code section. 
         [0041]    Once the shared memory region is initialized as in  FIG. 3 , the application code may be executed using at least one process. Each process may include a group of threads in which a thread of the group of threads may execute a code section that requires access to the shared memory region. With the code modified as shown in  FIG. 3 , the thread may first execute the inserted instructions from Step  304  before executing instructions that access the shared memory region. Said another way, as the thread executes application code, the thread may encounter a code section requiring access to the shared memory region and subsequently send a request to the operating system to enable access to the shared memory region, as is shown in  FIG. 4 . 
         [0042]    Referring to  FIG. 4 , a flowchart for an application making an operating system request in accordance with one or more embodiments of the invention is shown. Specifically, the thread encounters a modified code section that requires access to the shared memory region and as a result sends a request to the operating system to enable access to the shared memory region prior to accessing the shared memory region. 
         [0043]    In Step  400 , the thread executes the inserted instructions from Step  304  and the application generates a request to the operating system to enable access for the thread to a shared memory region. For example, the request to the operating system may include a request for enabling access to a shared memory region spanning from x0200 to x0250. 
         [0044]    In Step  402 , the operating system loads the corresponding shared context ID into the shared context ID register. Following the above example, the operating system may load a shared context ID of xAAAA. 
         [0045]    In Step  404 , the thread accesses the shared memory region and may read from shared memory and/or write to the shared memory region. Specifically, the thread may execute instructions after the instructions that send a request to enable access but before the instructions that send a request to disable access. With the shared context ID in the shared context ID register, the thread may also use preexisting TLB entries with the shared context ID. As the thread accesses the shared memory region, TLB entries with the shared context ID are created. For example, the thread may access TLB entries including the shared context ID of xAAAA. 
         [0046]    In Step  406 , after the thread accesses the shared memory region, the thread executes the inserted instructions from Step  304  and the application generates a request to the operating system to disable access to the shared memory region. For example, the request to the operating system may include a request for disabling access to the shared memory region spanning x0200 to x0250. 
         [0047]    In Step  408 , the operating system removes the shared context ID from the shared context ID register. In one embodiment of the invention, the operating system may leave the shared context ID register with a value of null. In another embodiment of the invention, the operating system may insert a predetermined value into the shared context ID register. With the removal of the shared context ID, the thread may not access TLB entries that include the shared context ID. 
         [0048]    Some memory systems (as described below in  FIGS. 5-7 ), in lieu of using a shared context ID register, have a current page table register that points to a particular page table. Accordingly, a given thread may only access the memory region mapped by the page table to which the current page table register points. Therefore, the system maintains several page tables that map to particular memory regions. Specifically, the memory system may maintain a page table that maps to a private memory region and another page table that maps to both the private memory region and shared memory region. This configuration of page tables may allow a thread to access either only the private memory region or both the private memory region and the shared memory region. 
         [0049]    Referring to  FIG. 5 , a system using page tables in accordance with one or more embodiments of the invention is shown. The system includes a MMU ( 500 ) operatively connected to a current page table address register ( 502 ), which is used to determine access privileges to a private memory region (not shown) and a shared memory region (not shown). The process of granting access to memory regions is improved through the use of a TLB ( 504 ). 
         [0050]    In one embodiment of the invention, the MMU ( 500 ) is a computer component that handles requests to access regions of memory. Further, the MMU may access a TLB ( 504 ), a private memory page table ( 508 ), and a hybrid memory page table ( 512 ). More specifically, the MMU may grant or deny a thread, process, or application access to a particular memory region based on the value in the current page table register. The MMU also includes functionality to translate virtual addresses into corresponding physical addresses in memory. When the MMU processes an address access request from a thread, the MMU checks the TLB ( 504 ) for a corresponding cache entry. If an entry is not found, the MMU uses the private memory page table ( 508 ) or hybrid memory page table ( 512 ) to determine the corresponding physical address. 
         [0051]    In one embodiment of the invention, the current page table register ( 502 ) is a small amount of memory that is used to store a page table address corresponding to a page table that may be used to access a memory region. The page table that the current page table register points to includes mappings of virtual addresses to physical addresses within a certain region of memory. The current page table register may only point to one page table at a time, allowing the thread to access only the region mapped by one page table at any given time. 
         [0052]    In one embodiment of the invention, the TLB ( 504 ) caches virtual addresses and the corresponding physical addresses in memory associated with a given context ID. The TLB stores these values in TLB entries ( 506 A- 506 B), as defined in  FIG. 2 . For this system, the context ID used in a TLB entry is the address of the page table that is currently being pointed to, which is the value in the current page table register. For example, when a thread requests to access the shared memory region, the MMU may check the TLB ( 504 ) for an entry with the requested virtual address and a context ID of the current page table address. If a TLB entry exists, the MMU may determine the corresponding physical address without using a page table. 
         [0053]    In one embodiment of the invention, a private memory page table ( 508 ) is a table of mappings ( 510 A and  510 B) from virtual addresses to physical addresses in a private memory region. 
         [0054]    In one embodiment of the invention, a private memory region (not shown) is a region in memory that is designated as accessible by a thread or group of threads. The private memory region may be defined prior to use of the private context ID register. The private memory region may be organized into pages. Based on  FIG. 5 , the private memory region includes pages ( 516 A and  516 C) mapped ( 510 A and  510 B) by the private memory page table. 
         [0055]    In one embodiment of the invention, a hybrid memory page table ( 512 ) is a table of mappings from virtual addresses to physical addresses in a shared memory region that is designated as accessible by an application. In accordance with one embodiment of this invention, the hybrid memory page table includes mappings to both a shared memory region and a private memory region. Referring to  FIG. 5 , the hybrid memory page table ( 512 ) includes all the mappings to the private memory region ( 510 A and  510 B) as well as the mappings to the shared memory region ( 510 C and  510 D). 
         [0056]    In one embodiment of the invention, the memory ( 514 ) is the total memory in hardware for the given computing device hosting the memory. As shown on  FIG. 5 , the memory includes the memory regions mapped by the hybrid and private page tables. 
         [0057]      FIGS. 6 and 7  show flowcharts in accordance with one or more embodiments of the invention. While the various steps in the flowcharts are presented and described sequentially, one of ordinary skill will appreciate that some or all of the steps may be executed in different orders, may be combined or omitted, and some or all of the steps may be executed in parallel. In one embodiment of the invention, the steps shown in any of the flowcharts may be performed in parallel with the steps shown in any of the other flowcharts. 
         [0058]    Referring to  FIG. 6 , a flowchart for initializing a shared memory region in accordance with one or more embodiments of the invention is shown. In Step  600 , a shared memory region is identified by the application. For example, the application may define a shared memory region with virtual addresses spanning from x00FF to x0300. In one embodiment of the invention, the application may also determine a private memory region. Alternatively, the private memory region may be determined by the operating system. 
         [0059]    In Step  602 , the operating system is notified of the shared memory region for which access will be enabled and disabled. For example, the operating system may be notified of the shared memory region with virtual addresses spanning from x00FF to x0300. In one embodiment of the invention, the operating system may generate a hybrid page table with mappings to both the private memory region and the shared memory region. Further, the operating system may remove any mappings to the shared memory region that are included in the private page table. The address of the hybrid page table may then be used as the context ID for TLB entries. 
         [0060]    In Step  604 , instructions are inserted into application code sections that require access to the shared memory region. Specifically, the instructions that generate a request to the operating system to enable access to the shared memory region are added at some point before the instructions that access the shared memory region. Said another way, the code section is modified to send a request to the operating system to enable access before a thread accesses the shared memory region. Further, the location of the instructions to send a request to the operating system to enable access may vary based on implementation. Specifically, the instructions may be located within the code section at any point prior to the instructions requiring access to the shared memory region or prior to the entire code section. 
         [0061]    Likewise, the instructions that generate a request to the operating system to disable access to the shared memory region are added after the instructions that access the shared memory region. Said another way, the code section is modified to send a request to the operating system to disable access after a thread accesses the shared memory region. The code section may be a routine in the application code. For example, if an application routine includes instructions to read from the shared memory region, instructions to send a request to enable access may be placed at some point before the read instructions and instructions to send a request to disable access may be placed at some point after the read instructions. Further, the location of the instruction to send a request to the operating system to disable access may vary based on implementation. Specifically, the instructions may be located within the code section at any point after the instructions requiring access to the shared memory region or after the entire code section. 
         [0062]    Once the shared memory region is initialized as in  FIG. 6 , the application code may be executed using at least one process. Each process may include a group of threads in which a thread may execute a code section that requires access to the shared memory region. With the code modified as shown in  FIG. 6 , the thread may first execute the inserted instructions from Step  604  before executing instructions that access the shared memory region. Said another way, as the thread executes application code, the thread may encounter a code section requiring access to the shared memory region and subsequently send a request to the operating system to enable access to the shared memory region, as is shown in  FIG. 7 . 
         [0063]    Referring to  FIG. 7 , a flowchart for an application making an operating system request in accordance with one or more embodiments of the invention is shown. Specifically, the thread encounters a modified code section that requires access to the shared memory region and as a result sends a request to the operating system to enable access to the shared memory region prior to accessing the shared memory region. 
         [0064]    In Step  700 , thread executes the inserted instructions from Step  604  and the application generates a request to the operating system to enable access for the thread to a shared memory region. In Step  702 , the operating system loads the hybrid page table address into the current page table register. 
         [0065]    In Step  704 , the thread accesses the shared memory region and may read from shared memory and/or write to the shared memory region. The thread may also access the private memory region that is included in the hybrid memory page table. Specifically, the thread may execute instructions after the instructions that send a request to enable access but before the instructions that send a request to disable access. As the thread continues execution of the application code while access to the shared memory region is enabled, TLB entries with a context ID of the hybrid memory page table are created. Accordingly, the thread may access only TLB entries with a context ID of the hybrid memory page table address. 
         [0066]    In Step  706 , after the thread accesses the shared memory region, the thread executes the inserted instructions from Step  604  and the application generates a request to the operating system to disable access to the shared memory region. In Step  708 , the operating system loads the private memory page table address into the current page table register. As the context ID of the thread is the private page table address, the thread may not access any of the TLB entries created while access to the shared memory region was enabled. 
         [0067]    The following discussion describes examples in accordance with one or more embodiments of the invention. 
         [0068]    Referring to  FIGS. 8A-B , an example in accordance with one or more embodiments of the invention is shown. This example is not intended to limit the scope of the invention or the claims. 
         [0069]    Consider a scenario in which there is a thread executing a code section that requires access to a shared memory region. As shown in  FIG. 8A , the system ( 800 ) includes a private memory region and a shared memory region. The private memory region and the shared memory region do not overlap with each other. In this example, the shared memory region is a database with bank account information. The shared context ID for the shared memory region is xBEEF and the private context ID for the private memory region is xAAAA. The application code has been modified to include instructions to enable and disable access to the shared memory region in all appropriate code sections. The private context ID register begins with a value of xAAAA and the shared context ID register begins with a value of null. As shown on  FIG. 8A , the TLB includes 5 TLB entries of format [Context ID, Virtual Address, Physical Address]. 
         [0070]    Referring to  FIG. 8A , Thread 1 executes a routine that includes a write operation to the database at virtual address x0202. In the routine, the thread executes instructions to generate a request to the operating system to enable access to the database for Thread 1. In response to the request, the operating system loads the value xBEEF into the shared context ID register. The MMU checks for TLB entries with a virtual address of x0202 and a context ID of xAAAA or xBEEF. The MMU finds an entry with a context ID of xBEEF, a virtual address of x0202, and a physical address of x0010. With access to the shared memory region enabled, Thread 1 continues to execute instructions in the routine and writes new bank account information to the database at physical address x0212. Memory accesses to the shared memory region result in TLB entries with a context ID of xBEEF. 
         [0071]    Referring to  FIG. 8B , the system ( 800 ) includes the private memory region and the shared memory region shown in  FIG. 8A . While continuing to execute instructions in the routine, Thread 1 executes instructions to send a request to the operating system to disable access for Thread 1. In response to the request, the operating system removes the shared context ID from the shared context ID register. Thread 1 may no longer access the shared memory region nor use TLB entries with a context ID of xBEEF. 
         [0072]    Referring to  FIGS. 9A-B , an example in accordance with one or more embodiments of the invention is shown. This example is not intended to limit the scope of the invention or the claims. 
         [0073]    Consider a scenario in which there is a thread executing a code section that requires access to a shared memory region. As shown in  FIG. 9A , the system ( 900 ) includes a private memory region and a shared memory region. The private memory region and the shared memory region do not overlap with each other. In this example, the shared memory region is a library with mathematical functions. The hybrid memory page table has an address of x0D75 and the private memory page table has an address of x0D10. The application code has been modified to include instructions to enable and disable access to the shared memory region in all appropriate code sections. The current page table register begins with a value of x0D10 as shown in  FIG. 9A . 
         [0074]    Referring to  FIG. 9A , Thread 1 executes a routine that includes a read operation from the library at virtual address x0111. In the routine, the thread executes instructions to generate a request to the operating system to enable access to the library for Thread 1. In response to the request, the operating system loads the value x0D75 into the current page table register. The MMU uses the hybrid memory page table to determine that the corresponding physical address is x0222. With access to the shared memory region enabled, Thread 1 continues to execute instructions in the routine and reads a mathematical function from the library at physical address x0222. While access to the shared memory region is enabled, any memory accesses result in TLB entries with a context ID of x0D75. 
         [0075]    Referring to  FIG. 9B , the system ( 900 ) includes the private memory region and the shared memory region shown in  FIG. 9A . While continuing to execute instructions in the routine, Thread 1 executes instructions to send a request to the operating system to disable access for Thread 1. In response to the request, the operating system loads the private page table address into the current page table register. The MMU then loads x0D10 into the current page table register. Thread 1 may no longer access the shared memory region and is restricted to accessing the private memory region. Thread 1 may not use TLB entries with a context ID of x0D75. 
         [0076]    One or more embodiments of the invention may be implemented on a multi-threaded system in which each of the threads is associated with a private context ID and a corresponding private memory region. Further, one or more of the threads may also be granted access to one or more shared memory regions using the corresponding shared context ID. 
         [0077]    Software instructions to perform embodiments of the invention may be stored on a non-transitory computer readable medium such as a magnetic storage, optical storage, solid state storage, or any other computer readable storage device. Further, such instructions may be executed by a processor(s) as described above. 
         [0078]    While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.