Abstract:
A CAM cell array is disclosed in which a comparator function is performed by incorporating a selected transistor of each CAM cell latch into a signal path extending between a match line and a second (e.g., charge or discharge) line. A first terminal of the selected transistor is connected to the match line (or the second line), a second terminal is connected to an internal node of the latch, and a gate terminal of the selected transistor is controlled by the data value stored in the latch. The internal node of the latch is connected through a control transistor having a gate terminal connected to receive an applied data value. When the applied data value is equal to the stored data value, the match line is coupled to the second line along a signal path passing through the selected transistor and the pass transistor. During programming (i.e., when data values are written to the latch), the match line (or second line) carries a low/high voltage signal needed to set (flip) the latch into a desired state.

Description:
FIELD OF THE INVENTION 
     The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to ternary and higher order CAM cells and methods for operating these cells in a CAM array. 
     DISCUSSION OF RELATED ART 
     Unlike conventional random access memory (RAM) arrays, CAM arrays include memory cells that are addressed in response to their content, rather than by a physical address within a RAM array. That is, data words stored in a RAM array are accessed by applying address signals to the RAM array input terminals. In response to each unique set of address signals, a RAM array outputs a data value that is read from a portion of the RAM array designated by the address. In contrast, a CAM array receives a data value that is compared with all of the data values stored in rows of the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value. 
     CAM arrays are useful in many applications, such as search engines. For example, assume an employee list is searched to identify all employees with the first name “John”. The first names are written into a CAM array such that they are stored in a predetermined order (e.g., according to employee number). The compare data value (“John”) is then applied to the CAM input terminals. When one or more stored data values match the compare data value (a match condition), the match line coupled to the one or more matching rows of CAM cells generates a match value (e.g., a logic highvalue) output signal. The rows having CAM cells having stored data values that do not match the compare data value (a no-match condition) generate a no-match value (e.g., a logic low value) output signal on the associated match lines. By identifying which rows have associated high match lines, and comparing those row numbers with the employee number list, all employees named “John” are identified. Note that some CAM arrays generate a logic low value as a match value output signal. In contrast, to search a RAM array containing the same employee list, a series of addresses must be applied to the RAM array so that each stored data value is read out and compared with the “John” data value. Because each RAM read operation takes one clock cycle, a relatively large amount of time is required to read and compare a particular data value with all data values stored in a RAM array. 
     CAM cells are typically defined by the number of data values that they store. For example, binary CAM cells stores one of two logic values: a logic high value or a logic low value. Ternary CAM cells store one of three logic values: a logic high value, a logic low value, and a “don&#39;t care” logic value. A “don&#39;t care” logic value is a logic value that produces a match condition for any applied compare data value. Higher order CAM cells store additional data values. For example, a CAM cell storing four states will have one of a logic high value, a logic low value, a logic high “don&#39;t care” value, and a logic low “don&#39;t care” value. Thus, a CAM cell storing four states beneficially stores a data value (e.g., a high or low value) and simultaneously indicates whether that data value is to be involved in a match operation (e.g., a logic high or a logic high “don&#39;t care”). As a result, a read operation on a four-state CAM cell storing a “don&#39;t care” value distinguishes the “don&#39;t care” value read from the CAM cell as either a logic high “don&#39;t care” value or a logic low “don&#39;t care” value. 
     When the logic value stored in a ternary CAM cell matches an applied data value, assuming all other CAM cells coupled to the CAM array row also match, then the voltage on the match line coupled to the ternary CAM cell is maintained at the match value (e.g., a logic high value), thereby indicating that a match has occurred. In contrast, when the logic value stored in the ternary CAM cell does not match an applied data value, then the voltage on the match line coupled to the ternary CAM cell is changed to the no-match value (e.g., pulled down to a logic low value), thereby indicating that a match has not occurred. A ternary CAM cell storing a “don&#39;t care” value will provide a match condition for any data value applied to that CAM cell. This “don&#39;t care” capability allows CAM arrays to indicate when a data value matches a selected group of ternary CAM cells in a row of the CAM array. For example, assume each row of a ternary CAM array has eight ternary CAM cells. Additionally assume that the each of the first four ternary CAM cells of each row each store one of a logic high and a logic low value (for comparison to the first four bits of an input 8-bit data value) and the each of the last four ternary CAM cells of each row store “don&#39;t care” values. Under these conditions, when an 8-bit data value is applied to the ternary CAM array, a match occurs for each row of the CAM array in which the data values stored in the first four ternary CAM cells match the first four bits of the applied 8-bit data value. A read operation for all eight ternary CAM cells will provide meaningful data (e.g., a logic high or logic low value) for each of the first four ternary CAM cells, but only a “don&#39;t care” value for each of the last four ternary CAM cells. 
     A four-state CAM cell operates similarly to the ternary CAM cell described above. However, the “don&#39;t care” data capability of the four-state CAM cell additionally allows meaningful “don&#39;t care” data (e.g., a logic high “don&#39;t care” or a logic low “don&#39;t care”) to be stored in the CAM cell. For example, assume each row of a four-state CAM array has eight four-state CAM cells. Additionally assume that the each of the first four four-state CAM cells of each row each store one of a logic high and a logic low value (for comparison to the first four bits of an input 8-bit data value) and the each of the last four four-state CAM cells of each row store one of a logic high “don&#39;t care” and a logic low “don&#39;t care” value. Similar to the ternary CAM cell example above, under these conditions, when an 8-bit data value is applied to the four-state CAM array, a match occurs for each row of the CAM array in which the data values stored in the first four four-state CAM cells match the first four bits of the applied 8-bit data value. However, a read operation for all eight four-state CAM cells will provide meaningful data (e.g., a logic high “don&#39;t care” or a logic low “don&#39;t care) for each of the last four four-state CAM cells as well as meaningful data (e.g., a logic high or logic low value) for each of the first four four-state CAM cells. 
     FIG. 1 is a schematic diagram of a conventional ternary CAM cell  100 . CAM cell  100  includes two 6-transistor (6-T) static random access memory (SRAM) cells  101 A and  101 B (i.e., storage elements  101 A and  101 B) and a 4-T exclusive-NOR circuit  101 C (i.e., comparator  101 C). Thus, CAM cell  100  is a 16-T CAM cell. SRAM cell  101 A includes n-channel transistors  110 ,  111 ,  114 , and  115  and p-channel transistors  122  and  123 . Transistors  114 ,  115 ,  122 , and  123  are cross-coupled to form a storage latch having storage node N 1  and inverted storage node N 1 #. Access transistors  110  and  111  couple storage node N 1 # and N 1 , respectively, to inverted bit line B 1 # and bit line B 1 , respectively. Similarly, SRAM cell  101 B includes n-channel transistors  116  and  117  and p-channel transistors  124  and  125 , which are cross-coupled to form a storage latch having node N 2  and inverted storage node N 2 #, and access transistors  112  and  113 , which couple storage nodes N 2 # and N 2 , respectively, to inverted bit line B 2 # and bit line B 2 , respectively. Exclusive NOR circuit  101 C includes n-channel transistors  118 - 121 . Transistors  120  and  118  are coupled in series between the match line and a steady state supply source (i.e., V SS  or ground). The gate of transistor  120  is coupled to node N 1  and the gate of transistor  118  is coupled to an inverted data line D 1 #. Similarly transistors  121  and  119  are coupled in series between the match line and the steady state supply source. The gate of transistor  121  is coupled to node N 2 # and the gate of transistor  119  is coupled to an data line D 1 . 
     CAM cell  100  stores one of a logic high, a logic low, and a logic “don&#39;t care” value by selectively storing data values in nodes N 1  and N 2 , and inverted data values in nodes N 1 # and N 2 #, during a write operation. During subsequent read operations, the values stored in nodes N 1 , N 2 , N 1 # and N 2 # are provided on bit lines B 1  and B 2  and inverted bit lines B 1 # and B 2 #, respectively. During a compare operation, the value stored in node N 2 # is compared to a data value and the value stored in node N 1  is compared to an inverted data value. Depending upon the outcome of this comparison, the match line MATCH 1  is either maintained in a charged state (indicating a match condition) or discharged to ground (indicating a no-match condition) in response to the applied data and inverted data values. As used herein, the term “discharged” means a voltage state is changed. Thus, in one embodiment, “discharged” may mean a logic high value of a match line is discharged to a logic low value or ground. In another embodiment, “discharged” may mean a logic low value of a match line is discharged to a logic high value or the V CC  voltage supply source. 
     A problem with conventional CAM cell  100  is that the 16 transistors forming CAM cell  100  take up valuable chip area. It is preferred to minimize the number of transistors required to perform a function to maximize available chip area. Another problem with conventional CAM cell  100  is the space required by the six bit lines (i.e., B 1 , B 1 #, B 2 , B 2 #, D 1A , and D 1B #) coupled to CAM cell  100 . These many connections similarly occupy valuable chip area. It would therefore be desirable to have a CAM cell having a minimized area that is capable of storing at least three values. 
     FIG. 2 is a schematic diagram of another conventional ternary CAM cell  200  as described in U.S. Pat. No. 5,841,874. CAM cell  200  includes two 5-T memory cells  120  and  130  (i.e., storage elements  120  and  130 ) and a 4-T comparator circuit  150  (i.e., comparator  150 ). Thus, CAM cell  200  is a 14-T CAM cell. Memory cell  120  includes transistors  210  and  220 - 223 . Memory cell  130  includes transistors  230 - 234 . Comparator circuit  150  includes transistors  251 - 254 . Transistors  220 - 223  are cross-coupled to form a storage latch. Access transistor  210  couples the gates of transistors  220  and  222  (i.e., the storage node, RA, of cross-coupled transistors  221  and  223 ) to bit line A. Transistors  230 - 233  are cross-coupled to form a storage latch. Access transistor  234  couples the gates of transistors  231  and  233  (i.e., the storage node of cross-coupled transistors  230  and  232  that is the inverse of the value stored in storage node RB) to bit line B. 
     Similarly to CAM cell  100 , CAM cell  200  stores one of a logic high, a logic low, and a logic “don&#39;t care” value by selectively storing data values in memory cells  120  and  130  during a write operation. During subsequent read operations, the values stored in memory cells  120  and  130  are provided on bit lines A and B, respectively. During a compare operation, the value stored in memory cell  120  is compared to a first data value applied to bit line B and the value stored in memory cell  130  is compared to a data value applied to bit line A in comparator  150 . Depending upon the outcome of this comparison, the match line MATCH is either maintained in a charged state (indicating a match) or discharged to ground (indicating a no-match) in response to the applied data and inverted data values. 
     While CAM cell  200  has fewer transistors than CAM cell  100 , thereby occupying a smaller chip area, a write operation of logic high values in CAM cell  200  is much more difficult than in CAM cell  100 . This difficulty arises because the voltage between a logic low and a logic high value when one bit line is used must accommodate writing a logic low value, reading, and writing a logic high value. Latches easily change state upon the application of a logic low value to a node of the latch storing a logic high value. However, latches must distinguish between the voltage applied during a read operation (and therefore resist a change of state) and the voltage applied when storing a logic high value (and therefore potentially change state). During a write operation, CAM cell  100  either applies a logic low value to node N 1 , thereby storing a logic low value in CAM cell  100  if node N 2  also stores a logic low value, or applies a logic low value to node N 1 #, thereby storing a logic high value in CAM cell  100  if node N 2 # also stores a logic low value. As a result, the state of SRAM cell  101 A is easily changed. In contrast, memory cell  120  applies a logic low value to memory cell  120  only during some write operations (e.g., while storing a logic low value in memory cell  120 ). In other write operations, a logic high value is applied to memory cell  120 , resulting in the difficult write operation of CAM cell  200  described above. 
     Read operations in CAM cell  200  are also more difficult than in CAM cell  100 . CAM cell  200  must either read data stored in memory cell  120  and  130  from bit lines A and B at the same time, or read the data stored in memory cell  120  through comparator  150  and then read the data stored in memory cell  130  through comparator  150 . Reading from bit lines A and B is complicated because of the similarity of the read operation to a write operation. Because bit lines A and B are pre-charged to a logic high value during a read operation from bit lines A and B, at least one of the values of bit lines A and B are similar to the values of bit lines A and B during a write operation. This similarity of values of bit lines A and B may cause a read disturbance of the value stored in memory cells  120  and  130 . Additionally, reading from comparator  150  is complicated because of the length of time required to read each memory cell. Because each of memory cells  120  and  130  must be read separately through comparator  150 , the read operation of CAM cell  200  using this method requires approximately twice the time required by CAM cell  100 . It would be desirable to eliminate these write and read operation complications while minimizing the area occupied by a CAM cell. 
     SUMMARY 
     The present invention is directed to an array of CAM cells that utilize selected transistors of the storage latches to perform comparator functions, thereby reducing the size of each CAM cell by reducing the required number of transistors. The comparator function is performed by incorporating a selected (first) transistor of each latch, which is used to store data values in each CAM cell, into a signal path extending between a match line and a second (e.g., charge or discharge) line. Specifically, a first terminal of the selected transistor is connected to the match line (or the second line), a second terminal is connected to an internal node of the latch, and a gate terminal of the selected transistor is controlled by the data value stored in the latch. The internal node of the latch is connected through a control (second) transistor having a gate terminal connected to receive an applied data value. When the applied data value is equal to the stored data value (i.e., when both the selected transistor and the pass transistor are turned on by the stored data value and the applied data value, respectively), the match line is coupled to the second line along a signal path passing through the selected transistor and the pass transistor. Note that during programming (i.e., when data values are written to the latch), the match line (or second line) carries a low/high voltage signal needed to set (flip) the latch into a desired state. Accordingly, at least one transistor of the latch is utilized in the comparator function of the CAM cell, thereby reducing the number of transistor needed to form the CAM cell and minimizing the size of the CAM cell array. 
     In accordance with the disclosed embodiments, each CAM cell is an SRAM cell including a latch formed by cross-coupled inverters, and connected to one or more bit lines by one or more access transistors. Each inverter of the cross-coupled inverters includes an n-channel transistor and a p-channel transistor connected in series between a voltage source (e.g., V CC ) and the match line (or second line). The n-channel transistor of at least one of the inverters is used as a selected transistor, and has one terminal connected to the match line (or second line). In some embodiments, an access transistor is used as the second transistor to form the signal path with the n-channel transistor between the match line and the second line. In other embodiments, an additional pass transistor, which is connected in parallel with one of the access transistors, is provided to form the signal path. In yet other embodiments, a third transistor or control circuit is connected in the signal path to control charging/discharging of the match line in accordance with a control signal (e.g., stored by a mask memory cell). In further embodiments, the third transistor is controlled by a voltage level maintained on the match line such that the third transistor is turned off when the match line is sufficiently discharged, thereby saving power by allowing the discharged match line to float above ground. 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional ternary CAM cell; 
     FIG. 2 is a schematic diagram of a conventional ternary CAM cell; 
     FIG. 3A is a schematic diagram of a ternary CAM array in accordance with an embodiment of the present invention; 
     FIG. 3B is a schematic diagram of a ternary CAM array in accordance with another embodiment of the present invention; 
     FIG. 3C is a schematic diagram of a ternary CAM array in accordance with another embodiment of the present invention; 
     FIG. 4A is a schematic diagram of a CAM array in accordance with an embodiment of the present invention; 
     FIG. 4B is a schematic diagram of a ternary CAM cell in accordance with the CAM array of FIG. 4A; 
     FIG. 4C is a schematic diagram of a CAM array in accordance with another embodiment of the present invention; 
     FIG. 4D is a schematic diagram of a CAM array in accordance with another embodiment of the present invention; 
     FIG. 5A is a schematic diagram of another ternary CAM cell in accordance with an embodiment of the present invention; 
     FIG. 5B is a schematic diagram of another ternary CAM cell in accordance with another embodiment of the present invention; 
     FIG. 6A is a schematic diagram of another ternary CAM cell in accordance with an embodiment of the present invention; 
     FIG. 6B is a schematic diagram of another ternary CAM cell in accordance with another embodiment of the present invention; 
     FIG. 7 is a schematic diagram of a four-state CAM cell in accordance with an embodiment of the present invention; 
     FIG. 8 is a schematic diagram of another four-state CAM cell in accordance with an embodiment of the present invention; 
     FIG. 9A is a schematic diagram of another four-state CAM cell in accordance with an embodiment of the present invention; 
     FIG. 9B is a schematic diagram of a control circuit in accordance with an embodiment of the present invention; 
     FIG. 9C is a schematic diagram of a control circuit in accordance with another embodiment of the present invention; 
     FIG. 9D is a schematic diagram of a control circuit in accordance with another embodiment of the present invention; 
     FIG. 9E is a schematic diagram of a diode in accordance with an embodiment of the present invention; and 
     FIG. 10 is a schematic diagram of another four-state CAM cell in accordance with an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 3A is a simplified schematic diagram showing a portion of a CAM array  380 ( 1 ) in accordance with the present invention. CAM array  380 ( 1 ) includes CAM cells  381 - 384  that are coupled to bit lines B 1A #, B 1B , B 2A #, and B 2B , data lines D 1 , D 1 #, D 2 , and D 2 #, control lines C 1  and C 2 , word lines WL 1 , WL 2 , WL 3 , and WL 4 , the V CC  voltage supply source, the low match line LM 1 , V SS  voltage supply source, and match lines MATCH 1  and MATCH 2 . Storage cells  381 A- 384 A and  381 B- 384 B are each single bit storage cells (e.g., a static random access memory (SRAM) cell). Because each of CAM cells  381 - 384  store two bits (e.g., CAM cell  381  stores one bit each in storage cells  381 A and  381 B), each of CAM cells  381 - 384  are capable of storing one of up to four data values. 
     Control lines C 1  and C 2 , word lines WL 1 , WL 2 , WL 3 , and WL 4 , and match lines MATCH 1  and MATCH 2  isolate a first row of CAM cells (e.g., CAM cells  381  and  382 ) from a second row of CAM cells (e.g., CAM cells  383  and  384 ). Bit lines B 1A #, B 1B , B 2A #, and B 2B , and data lines D 1 , D 1 #, D 2 , and D 2 # isolate one column of CAM cells (e.g., CAM cells  381  and  383 ) from a second column of CAM cells (e.g., CAM cells  382  and  384 ). As a result, data may be written to, read from, or compared to a single CAM cell or a combination of CAM cells in CAM array  380 ( 1 ). 
     Low match lines LM 1  and LM 2  are controllable lines coupled to a control circuit such that the voltage of low match lines LM 1  and LM 2  may be varied. For example, in one embodiment, during a standby operation where a row of cells coupled to low match line LM 1  is not active, low match line LM 1  may be allowed to float. As a result, a power savings is achieved from the un-powered low match line LM 1 . However, in another example, in the same embodiment, during a write operation, low match line LM 1  may be held to a logic low value. As a result, proper voltages required for the write operation are provided. 
     FIG. 3B is a simplified schematic diagram showing a portion of a CAM array  380 ( 2 ) in accordance with another embodiment the present invention. Similar elements in CAM arrays  380 ( 1 ) (FIG. 3A) and  380 ( 2 ) are labeled similarly. CAM array  380 ( 2 ) differs from CAM array  380 ( 1 ) in the combination of word lines WL 1  and WL 2  (FIG. 3A) into word line WL 1  (FIG. 3B) and the combination of word lines WL 3  and WL 4  (FIG. 3A) into word line WL 2  (FIG.  3 B). As a result, the area required to implement CAM array  380 ( 2 ) is less than the area required to implement CAM array  380 ( 1 ), because one fewer word line per row is needed. 
     FIG. 3C is a simplified schematic diagram showing a portion of a CAM array  380 ( 3 ) in accordance with another embodiment the present invention. Similar elements in CAM arrays  380 ( 1 ) (FIG. 3A) and  380 ( 3 ) are labeled similarly. CAM array  380 ( 3 ) differs from CAM array  380 ( 1 ) in the combination of bit lines B 1A # and B 1B  (FIG. 3A) into bit line B 1  (FIG. 3C) and the combination of bit lines B 2A # and B 2B  (FIG. 3A) into bit line B 2  (FIG.  3 C). As a result, the area required to implement CAM array  380 ( 3 ) is less than the area required to implement CAM array  380 ( 1 ), because one fewer bit line per column is needed. 
     The operation of CAM array  380 ( 1 )is described below with respect to several embodiments. Note that low match lines LM 1  and LM 2  and the V SS  voltage supply source may not necessarily both be present in an embodiment. Additionally, note that not all lines are present in all embodiments. Different embodiments may combine similarly functioning lines, such as combining word lines WL 1  and WL 2  into one word line (e.g., CAM array  380 ( 2 )) or combining bit line B 1A # and B 1B  into one bit line (e.g., CAM array  380 ( 3 )). 
     First Embodiment: 12-T Ternary CAM Cell 
     FIG. 4A is a schematic diagram showing a portion of a ternary CAM array  400 ( 1 ) in accordance with a first embodiment of the present invention. CAM array  400 ( 1 ) includes 12-T ternary CAM cells  401 - 404  each comprising SRAM cells  301 A- 304 A, respectively and  301 B- 304 B, respectively. SRAM cells  301 A- 304 A and  301 B- 304 B are coupled to bit lines B 1B , B 1A #, B 2B , and B 2A #, data lines D 1 , D 1 #, D 2 , and D 2 #, control lines C 1  and C 2 , word lines WL 1 , WL 2 , WL 3 , and WL 4 , the V CC  voltage supply source, and match lines MATCH 1  and MATCH 2 . 
     Similar to prior art CAM cell  100  (discussed above), each of CAM cells  401 - 404  includes a first storage element (e.g., one of SRAM cells  301 A- 304 A) and a second storage element (e.g., one of SRAM cells  301 B- 304 B). SRAM cell  301 A includes a pair of inverters formed by transistors  326  and  342  (having output node N 1A ) and transistors  327  and  343  (having output node N 1A #), which are cross-coupled to form a storage latch, and access transistors  310  and  318 , which are coupled to output nodes N 1A  and N 1A #, respectively. An output node is a storage node where a data value is stored. Similarly, SRAM cell  301 B includes a pair of inverters formed by transistors  328  and  344  (having output node N 1B #) and transistors  329  and  345  (having output node N 1B ), which are cross-coupled to form a storage latch, and access transistors  311  and  319 , which are coupled to output nodes N 1B  and N 1B #, respectively. 
     Similarly to CAM cell  401 , CAM cell  402  includes SRAM cells  302 A and  302 B. SRAM cell  302 A includes cross-coupled inverters formed from transistors  330  and  346  (having output node N 2A ) and  331  and  347  (having output node N 2A #), which form a storage latch, and access transistors  312  and  320 , which are coupled to output nodes N 2A  and N 2A #, respectively. SRAM cell  302 B includes cross-coupled inverters formed from transistors  332  and  348  (having output node N 2B ) and  333  and  349  (having output node N 2B #), which form a storage latch, and access transistors  313  and  321 , which are coupled to output nodes N 2B  and N 2B #, respectively. CAM cell  403  includes SRAM cells  303 A and  303 B. SRAM cell  303 A includes cross-coupled inverters formed from transistors  334  and  350  (having output node N 3A ) and  335  and  351  (having output node N 3A #), which form a storage latch, and access transistors  314  and  322 , which are coupled to output nodes N 3A  and N 3A #, respectively. SRAM cell  303 B includes cross-coupled inverters formed from transistors  336  and  352  (having output node N 3B ) and  337  and  353  (having output node N 3B #), which form a storage latch, and access transistors  315  and  323 , which are coupled to output nodes N 3B  and N 3B #, respectively. CAM cell  404  includes SRAM cells  304 A and  304 B. SRAM cell  304 A includes cross-coupled inverters formed from transistors  338  and  354  (having output node N 4A ) and  339  and  355  (having output node N 4A #), which form a storage latch, and access transistors  316  and  324 , which are coupled to output nodes N 4A  and N 4A #, respectively. SRAM cell  304 B includes cross-coupled inverters formed from transistors  340  and  356  (having storage node N 4B ) and  341  and  357  (having storage node N 4B #), which form a storage latch, and access transistors  317  and  325 , which are coupled to output nodes N 4B  and N 4B #, respectively. 
     Bit lines B 1A #, B 1B , B 2A #, and B 2B  are coupled to a terminal of access transistors  310 - 313 , respectively and to a terminal of access transistors  314 - 317 , respectively. Data lines D 1 , D 1 #, D 2 , and D 2 # are coupled to a gate of access transistors  318 - 321 , respectively, and to a gate of access transistors  322 - 325 , respectively. Control line C 1  is coupled between terminals of transistors  318  and  319  and between terminals of transistor  320  and  321 . Control line C 2  is coupled between terminals of transistors  322  and  323  and between terminals of transistors  324  and  325 . Word lines WL 1 , WL 2 , WL 3 , and WL 4  are coupled to the gates of transistors  310 ,  311 ,  314 , and  315 , respectively, and to the gates of transistors  312 ,  313 ,  316 , and  317 , respectively. The V CC  voltage supply source provides power to a terminal of transistors  342 - 357 . Match line MATCH 1  is coupled to a terminal of transistors  326 - 333 . Match line MATCH 2  is coupled to a terminal of transistors  334 - 341 . 
     FIG. 4B is a closer view of CAM cell  401  in CAM array  400 ( 1 ) of FIG.  4 A. Thus, this CAM cell comprises SRAM cells  301 A and  301 B, which include n-channel transistors  310 ,  311 ,  318 ,  319 , and  326 - 329  and p-channel transistors  342 - 345 . SRAM cells  301 A and  301 B are coupled to bit lines B 1B  and B 1A #, data lines D 1  and D 1 #, control line C 1 , word lines WL 1  and WL 2 , the V CC  voltage supply source, and match line MATCH 1  as described with respect to FIG.  4 A. 
     The operation of an individual CAM cell (e.g., CAM cell  401 ) in CAM array  400 ( 1 ) will now be described with reference to FIGS. 4A and 4B. CAM array  400 ( 1 ) operations include standby, write, read, and compare operations. In a standby operation (standby state), for example, of CAM cell  401 , word lines WL 1  and WL 2  and data lines D 1  and D 1 # are pulled down to logic low values, thereby turning off access transistors  310 ,  311 ,  318 , and  319 , respectively. The match line MATCH 1  is held to a logic low value and the control line C 1  is preferentially left in it&#39;s last state. Under these conditions, SRAM cells  301 A and  301 B latch (i.e., store) the values at nodes N 1A  and N 1B  (and the inverted values N 1A # and N 1B #), respectively. Other CAM cells in CAM array  400 ( 1 ) may similarly be held in a standby state. Note that CAM cells within the CAM array that are not undergoing write, read, or compare operations are held in a this standby state or a modified standby state. CAM cells in a standby state that are located in the same row or the same column as a CAM cell or cells undergoing a write, read, or compare operation are not in a true standby state because of the effect of the voltages applied to the CAM cell undergoing the write, read, or compare operation. As a result, these CAM cells are held in a modified standby state. A modified standby state applies all standby conditions to a CAM cell except those set by the CAM cell undergoing the write, read, or compare operation that is the same row or column. Thus, while a first CAM cell (e.g., CAM cell  401 ) undergoes a write operation, another CAM cell (e.g., the fourth CAM cell  404 ) is held in a standby state. 
     A write operation to CAM cell  401  may accomplish one of three tasks: data is written to SRAM cell  301 A, data is written to SRAM cell  301 B, or data is written to both SRAM cells  301 A and  301 B simultaneously. Note that the ability to accomplish one of these three tasks depends on the configuration of the CAM cell. Therefore, in one embodiment, a CAM cell sharing a single bit line may not be able to write data to both SRAM cells simultaneously. Each of SRAM cells  301 A and  301 B holds a single bit. Thus, one of a logic high value and a logic low value may be written to each of SRAM cells  301 A and  301 B. CAM cell  401  holds two bits (i.e., the values (bits) stored in SRAM cells  301 A and  301 B). Thus, one of a logic high value, a logic low value, and a logic “don&#39;t care” value may be written to CAM cell  401 . 
     To write a data value (e.g., a logic high value) to both SRAM cells  301 A and  301 B simultaneously, bit line B 1A # and data line D 1  are held to a first write data value (e.g., a logic low value) and bit line B 1B  and data line D 1 # are held to a second write data value (e.g., a logic high value). Control line C 1  and match line MATCH 1  are held to logic low values. Word lines WL 1  and WL 2  are pulled up to logic high values to perform the write operation. 
     Referring to FIGS. 4A and 4B, to prevent the write operation of CAM cell  401  from affecting other CAM cells in the row (e.g., CAM cell  402 ) or other CAM cells in other rows (e.g., CAM cells  403  and  404 ), the other CAM cells are held in standby or modified standby states to prevent disturbance of their stored contents. Thus, word lines WL 2  and WL 3  and data lines D 2  and D 2 # are pulled down to logic low values, thereby turning off access transistors  314  and  316 ,  315  and  317 ,  320  and  324 , and  321  and  325 , respectively. As a result, CAM cells in a different row and column (e.g., CAM cell  404 ) from the CAM cell being written (e.g., CAM cell  401 ) are isolated from the write operation (e.g., by turned off access transistors  316 ,  317 ,  324 , and  325 ). The match line MATCH 2  is held to a logic low value to facilitate the latching of data in CAM cells  403  and  404 . Bit lines B 2A # and B 2B  are held to logic high values, thereby applying logic high values to nodes N 2A  and N 2B  of CAM cell  402  through turned on transistors  312  and  313 , respectively. Because a logic high value applied to an SRAM cell node is typically insufficient to change the value stored by the SRAM cell and access transistors  320  and  321  are turned off, the disturbance of the values stored in CAM cell  402  is prevented. This condition is similar to a read condition for CAM cell  402 . Control line C 2  is held to a logic high value, thereby applying a logic high value to one or more of nodes N 3A # and N 3B # if any of transistors  322  and  323  are turned on. Because a logic high value applied to an SRAM cell node is typically insufficient to change the value stored by the SRAM cell and access transistors  314  and  315  are turned off, the disturbance of the values stored in CAM cell  403  is prevented. 
     Returning to FIG. 4A, to write a logic high value to CAM cell  401 , bit line B 1A # and data line D 1  are held to logic low values (i.e., a first write data value) and bit line B 1B  and data line D 1 # are held to logic high values (i.e., a second write data value). Under these conditions, the logic high value of word line WL 1  turns on transistor  310 , the logic high value of data line D 1 # turns on transistor  319 , the logic high value of word line WL 2  turns on transistor  311 , and the logic low value of data line D 1  turns off transistor  318 . As a result, turned on transistor  310  couples the logic low value of bit line B 1A # to node N 1A #, thereby pulling up node N 1A  to a logic high value through turned on transistor  343 . Turned off transistor  318  isolates node N 1A  from the logic low value of control line C 1 . Additionally, turned on transistor  319  couples the logic low value of the control line C 1  to node N 1B #, thereby pulling up node N 1B  to a logic high value through turned on transistor  345 . Note that turned on transistor  311  also pulls up node N 1B  to a logic high value. As a result, both SRAM cells  301 A and  301 B store logic high values, thereby storing a logic high value in CAM cell  401 . 
     To write a logic low value to CAM cell  401 , bit line B 1A # and D 1  are held to logic high values (i.e., a first write data value) and bit line B 1B  and data line D 1 # are held to logic low values (i.e., a second write data value). Under these conditions, the logic high value of word line WL 1  turns on transistor  310 , the logic high value of data line D 1  turns on transistor  318 , the logic high value of word line WL 2  turns on transistor  311 , and the logic low value of data line D 1 # turns off transistor  319 . As a result, turned on transistor  318  couples the logic low value of the control line C 1  to node N 1A , thereby pulling up node N 1A # to a logic high value through turned on transistor  342 . Note that turned on transistor  310  also pulls up node N 1A # to a logic high value. Additionally, turned on transistor  311  couples the logic low value of bit line B 1B  to node N 1B , thereby pulling up node N 1B # to a logic high value through turned on transistor  344 . As a result, both SRAM cell  301 A and  301 B store logic low values, thereby storing a logic low value in CAM cell  401 . 
     To write a logic “don&#39;t care” value to CAM cell  401 , bit line B 1A # and data line D 1  are held to logic low values (i.e., a first write data value) and similarly bit lines B 1B  and data line D 1 # are held to logic low values (i.e., a second write data value). Under these conditions, the logic high value of word line WL 1  turns on transistor  310 , the logic high value of word line WL 2  turns on transistor  311 , the logic low value of data line D 1  turns off transistor  318 , and the logic low value of data line D 1 # turns off transistor  319 . As a result, turned on transistor  310  couples the logic low value of bit line B 1A # to node N 1A #, thereby pulling up node N 1A  to a logic high value through turned on transistor  343 . Turned off transistor  318  isolates node N 1A  from the logic low value of control line C 1 . Additionally, turned on transistor  311  couples the logic low value of the bit line B 1B  to node N 1B , thereby pulling up node N 1B # to a logic high value through turned on transistor  344 . Turned off transistor  319  isolates node N 1B # from the logic low value of control line C 1 . As a result, SRAM cell  301 A stores a logic high value and SRAM cell  301 B stores a logic low value, thereby storing a logic “don&#39;t care” value in CAM cell  401 . 
     As mentioned above, SRAM cell  301 A may be written independent of SRAM cell  301 B. To write a first data value to SRAM cell  301 A, bit line B 1A # and data line D 1  are held to the inverse of the first write data value. Data line D 1 #, control line C 1 , word line WL 2 , and match line MATCH 1  are held to logic low values. Word line WL 1  is pulled up to a logic high value to perform the write operation. 
     To write a logic high value (i.e., a first write data value) to SRAM cell  301 A, bit line B 1A # and data line D 1  are held to logic low values (i.e., the inverse of the first write data value). Under these conditions, the logic high value of word line WL 1  turns on transistor  310  and the logic low value of data line D 1  turns off transistor  318 . As a result, turned on transistor  310  couples the logic low value of bit line B 1A # to node N 1A #, thereby pulling up node N 1A  to a logic high value through turned on transistor  343 . Turned off transistor  318  isolates node N 1A  from the logic low value of control line C 1 . Note that the logic low values of word line WL 2  and data line D 1 # turn off transistors  311  and  319 , respectively. Turned off transistors  311  and  319  isolate SRAM cell  301 B, thereby preserving the data previously stored therein. In this way, a logic high value is stored in SRAM cell  301 A without disturbing the contents of SRAM cell  301 B. 
     To write a logic low value (i.e., a first write data value) to SRAM cell  301 A, bit line B 1A # and data line D 1  are held to logic high values (i.e., the inverse of the first write data value). Under these conditions, the logic high value of data line D 1  turns on transistor  318  and the logic high value of word line WL 1  turns on transistor  310 . As a result, turned on transistor  318  couples the logic low value of control line C 1  to node N 1A , thereby pulling up node N 1A # to a logic high value through turned on transistor  342 . Node N 1A # is also pulled up to a logic high value through turned on transistor  310 . Note that the logic low values of word line WL 2  and data line D 1 # turn off transistors  311  and  319 , respectively. Turned off transistors  311  and  319  isolate SRAM cell  301 B, thereby preserving the data previously stored therein. In this way, a logic low value is stored in SRAM cell  301 A without disturbing the contents of SRAM cell  301 B. 
     SRAM cell  301 B may be written independent of SRAM cell  301 A in a fashion similar to that described for SRAM cell  301 A above. To write a first data value to SRAM cell  301 B, bit line B 1B  and data line D 1 # are held to the first write data value. Data line D 1 , control line C 1 , word line WL 1 , and match line MATCH 1  are held to logic low values. word line WL 2  is pulled up to a logic high value to perform the write operation. 
     To write a logic high value (i.e., a first data value) to SRAM cell  301 B, bit line B 1B  and data line D 1 # are held to logic high values (i.e., the first write data value). Under these conditions, the logic high value of word line WL 2  turns on transistor  311  and the logic high value of data line D 1 # turns on transistor  319 . As a result, turned on transistor  319  couples the logic low value of control line C 1  to node N 1B #, thereby pulling up node N 1B  to a logic high value through turned on transistor  345 . Node N 1B  is also pulled up to a logic high value through turned on transistor  311 . Note that the logic low values of word line WL 1  and data line D 1  turn off transistors  310  and  318 , respectively. Turned off transistors  310  and  318  isolate SRAM cell  301 A, thereby preserving the data previously stored therein. In this way, a logic high value is stored within SRAM cell  301 B without disturbing the contents of SRAM cell  301 A. 
     To write a logic low value (i.e., a first data value) to SRAM cell  301 B, bit line B 1B  and data line D 1 # are held to logic low values (i.e., the first write data value). Under these conditions, the logic low value of data line D 1 # turns off transistor  319  and the logic high value of word line WL 2  turns on transistor  311 . As a result, turned on transistor  311  couples the logic low value of bit line B 1B  to node N 1B , thereby pulling up node N 1B # to a logic high value through turned on transistor  344 . Note that the logic low values of word line WL 1  and data line D 1  turn off transistors  310  and  318 , respectively. Turned off transistors  310  and  318  isolate SRAM cell  301 A, thereby preserving the data previously stored therein. In this way, a logic low value is stored in SRAM cell  301 B without disturbing the contents of SRAM cell  301 A. 
     A read operation from CAM cell  401  may accomplish one of three tasks: data is read from SRAM cell  301 A, data is read from SRAM cell  301 B, or data is read from both SRAM cells  301 A and  301 B simultaneously. As described above, because SRAM cells  301 A and  301 B each hold a single bit, one of a logic high value and a logic low value may be read from each of SRAM cells  301 A and  301 B. Similarly, because CAM cell  401  holds two bits, one of a logic high value, a logic low value, and a logic “don&#39;t care” value may be read from CAM cell  401 . To read a data value from both SRAM cells  301 A and  301 B simultaneously (i.e., to read a data value from CAM cell  401 ), both bit lines B 1A # and B 1B  are pre-charged to a logic high value. Data lines D 1  and D 1 # and match line MATCH 1  are held to logic low values. The value of control line C 1  does not matter and is therefore left in it&#39;s previous state. Word lines WL 1  and WL 2  are pulled up to logic high values to perform the read operation. 
     During a read operation from CAM cell  401 , the logic high value of word line WL 1  turns on transistor  310 , thereby coupling the pre-charged logic high value of bit line B 1A # to node N 1A #. As a result, a logic low value stored at node N 1A # pulls down bit line B 1A # to a logic low value and a logic high value stored at node N 1A # causes bit line B 1A # to remain at a logic high value. Because bit line B 1A # is coupled to the inverted storage node of SRAM cell  301 A (i.e., node N 1A #), bit line B 1A # is an inverted value bit line. Thus, the data read from bit line B 1A # (i.e., the data value stored at node N 1A #) is the opposite value of the data value stored in SRAM cell  301 A (i.e., the data value stored at node N 1A ). Similarly, in reading from SRAM cell  301 B, the logic high value of word line WL 2  turns on transistor  311 , thereby coupling the pre-charged logic high value of bit line B 1B  to node N 1B . As a result, a logic low value stored at node NIB pulls down bit line B 1B  to a logic low value and a logic high value stored at node N 1B  causes bit line B 1B  to remain at a logic high value. Because bit line B 1B  is coupled to the storage node of SRAM cell  301 B (i.e., node N 1B ), the data read from bit line B 1B  is the value of the data value stored in SRAM cell  301 B (i.e., the data value stored at node N 1B ). 
     For example, if CAM cell  401  stores a logic high value, then nodes N 1A  and N 1B  store logic high values and nodes N 1A # and N 1B # store logic low values. Under these conditions, a read operation results in bit line B 1A # having a logic low value and bit line B 1B  having a logic high value. As a result, the data read from CAM cell  401  is interpreted as a logic high value stored in SRAM cell  301 B (i.e., the value read from bit line B 1B ) and a logic high value stored in SRAM cell  301 A (i.e., the opposite of the value read from bit line B 1A #). Therefore, a logic high value is read from CAM cell  401 . 
     As mentioned above, SRAM cell  301 A may be read independent of SRAM cell  301 B. To read a first data value from SRAM cell  301 A, bit line B 1A # is pre-charged to a logic high value. Data line D 1 , data line D 1 #, word line WL 2 , and match line MATCH 1  are held to logic low values. The values of bit line B 1B  and control line C 1  do not matter, and so are preferentially left in their last states. Word line WL 1  is pulled up to a logic high value to perform the read operation. 
     The logic high value of word line WL 1  turns on transistor  310 , thereby coupling the pre-charged logic high value of bit line B 1A # to node N 1A #. As a result, a logic low value stored at node N 1A # pulls down bit line B 1A # to a logic low value and a logic high value stored at node N 1A # causes bit line B 1A # to remain at a logic high value. As described above, because bit line B 1A # is coupled to the inverted storage node of SRAM cell  301 A (i.e., node N 1A #), bit line B 1A # is an inverted value bit line. Thus, the data read from bit line B 1A # (i.e., the data value stored at node N 1A #) is the opposite value of the data value stored in SRAM cell  301 A (i.e., the data value stored at node N 1A ). The logic low values of data line D 1 # and word line WL 2  turn off transistors  319  and  311 , respectively, thereby isolating SRAM cell  301 B from the read operation. 
     Similarly, SRAM cell  301 B may be read independent of SRAM cell  301 A. To read a first data value from SRAM cell  301 B, bit line B 1 B is pre-charged to a logic high value. Data line D 1 , data line D 1 #, word line WL 1 , and match line MATCH 1  are held to logic low values. The values of bit line B 1B # and control line C 1  do not matter, and so are preferentially left in their last states. Word line WL 2  is pulled up to a logic high value to perform the read operation. 
     The logic high value of word line WL 2  turns on transistor  311 , thereby coupling the pre-charged logic high value of bit line B 1B  to node N 1B . As a result, a logic low value stored at node NIB pulls down bit line B 1B  to a logic low value and a logic high value stored at node N 1B  causes bit line B 1B  to remain at a logic high value. As described above, the data read from bit line B 1B  is the value of the data value stored in SRAM cell  301 B (i.e., the data value stored at node N 1 B). The logic low values of data line D 1  and word line WL 1  turn off transistors  318  and  310 , respectively, thereby isolating SRAM cell  301 A from the read operation. 
     A compare operation from CAM cell  401  may accomplish one of three tasks: applied data is compared to SRAM cell  301 A, applied data is compared to SRAM cell  301 B, or applied data is compared to both SRAM cells  301 A and  301 B simultaneously. As described above, because SRAM cells  301 A and  301 B each hold a single bit, only a single bit (i.e., a logic high or a logic low value) may be compared to each of SRAM cells  301 A and  301 B. Similarly, because CAM cell  401  holds two bits, one of a logic high value, a logic low value, and a logic “don&#39;t care” value may be compared to the data stored in CAM cell  401 . To compare a data value to both SRAM cells  301 A and  301 B simultaneously (i.e., to compare a data value to CAM cell  301 ), match line MATCH 1  is pre-charged to a logic low value. Control line C 1  is held to a logic high value, and word lines WL 1  and WL 2  are held to logic low values. The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous states. A compare data value is applied to data lines D 1  and D 1 # to perform the compare operation. 
     To compare a logic high compare data value to CAM cell  401 , data line D 1  is held to a logic high value and data line D 1 # is held to a logic low value. Under these conditions, the logic low value of data line D 1 # turns off transistor  319 , thereby de-coupling the logic high value of control line C 1  from node N 1B #. Thus, the logic value stored in SRAM cell  301 B does not affect the value of match line MATCH 1  during the compare operation. The logic high value of data line D 1  turns on transistor  318 , thereby coupling the logic high value of control line C 1  to node N 1A . If CAM cell  401  stores a matching logic high value (SRAM cell  301 A node N 1A  stores a logic high value and node N 1A # stores a logic low value), then node N 1A  is de-coupled from match line MATCH 1  due to turned off transistor  327 . As a result, match line MATCH 1  remains in a logic low state, thereby indicating a match condition. Similarly, if CAM cell  401  stores a logic “don&#39;t care” value (SRAM cell  301 A node N 1A  stores a logic high value and node N 1A # stores a logic low value), then match line MATCH 1  similarly remains in a logic low state, thereby indicating a match condition. If CAM cell  401  stores a non-matching logic low value (SRAM cell  301 A node N 1A  stores a logic low value and node N 1A # stores a logic high value), then node N 1A  is coupled to match line MATCH 1  through turned on transistor  327 . As a result, match line MATCH 1  is pulled up to the logic high value of control line C 1  through turned on transistors  318  and  327 , thereby indicating a no-match condition. 
     To compare a logic low compare data value to CAM cell  401 , data line D 1  is held to a logic low value and data line D 1 # is held to a logic high value. Under these conditions, the logic low value of data line D 1  turns off transistor  318 , thereby de-coupling the logic high value of control line C 1  from node N 1A . Thus, the logic value stored in SRAM cell  301 A does not affect the value of match line MATCH 1  during the compare operation. The logic high value of data line D 1 # turns on transistor  319 , thereby coupling the logic high value of control line C 1  to node N 1B #. If CAM cell  401  stores a matching logic low value (SRAM cell  301 B node N 1B  stores a logic low value and node N 1B # stores a logic high value), then node N 1B # is deoupled coupled from match line MATCH 1  due to turned off transistor  328 . As a result, match line MATCH 1  remains in a logic low state, thereby indicating a match condition. Similarly, if CAM cell  401  stores a logic “don&#39;t care” value (SRAM cell  301 B node NIB stores a logic low value and node N 1B # stores a logic high value), then match line MATCH 1  similarly remains in a logic low state, thereby indicating a match condition. If CAM cell  401  stores a non-matching logic high value (SRAM cell  301 B node N 1B  stores a logic high value and node N 1B # stores a logic low value), then node N 1B # is coupled to match line MATCH 1  through turned on transistor  328 . As a result, match line MATCH 1  is pulled up to the logic high value of control line C 1  through turned on transistors  319  and  328 , thereby indicating a no-match condition. 
     To compare a logic “don&#39;t care” compare data value to CAM cell  401 , data lines D 1  and D 1 # are held to logic low values. Under these conditions, the logic low values of data lines D 1  and D 1 # turn off transistors  318  and  319 , respectively, thereby de-coupling the logic high value of control line C 1  from nodes N 1A  and N 1B #. Thus, the logic values stored in SRAM cells  301 A and  3101 B do not affect the value of match line MATCH 1  during the compare operation. As a result, match line MATCH 1  remains at a logic high value, thereby indicating a match condition for all values stored in CAM cell  401 . 
     As mentioned above, SRAM cell  301 A may be compared to a data value independent of SRAM cell  301 B. To compare a first data value to SRAM cell  301 A, match line MATCH 1  is brought to a logic low value. Control line C 1  is held to a logic high value, and word lines WL 1  and WL 2  and data line D 1 # are held to logic low values. The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous states. A compare data value is applied to data line D 1  to perform the compare operation. The logic low values of word line WL 2  and data line D 1 # isolate SRAM cell  301 B from the compare operation. The compare operation is then carried out similarly to that described above with respect to a comparison operation on CAM cell  401 . 
     Similarly, SRAM cell  301 B may be compared to a data value independent of SRAM cell  301 A. To compare a first data value to SRAM cell  301 B, match line MATCH 1  is brought to a logic low value. Control line C 1  is held to a logic high value, and word lines WL 1  and WL 2  and data line D 1  are held to logic low values. The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous states. A data value equivalent to the inverted compare 
     data value is applied to data line D 1 # to perform the compare operation. The logic low values of word line WL 2  and data line D 1  isolate SRAM cell  301 A from the compare operation. The compare operation is then carried out similarly to that described above with respect to a comparison operation on CAM cell  401 . 
     Operations similar to those described above may be performed on a row of CAM cells by applying the techniques described with respect to CAM cell  401  to the other CAM cells in the row. A comparison operation in CAM cell  401  (and similarly in CAM array  400 ( 1 )) results in a logic low value of the match line MATCH 1  if the applied comparison data value matches the data value stored in CAM cell  401 , and results in a logic high value of the match line MATCH 1  if the applied comparison data value does not match the data value stored in CAM cell  401 . It is also beneficial to have a CAM cell which results in a logic high value of the match line for a match condition and results in a logic low value of the match line for a no-match condition. 
     FIG. 4C is a schematic diagram of ternary CAM array  400 ( 2 ) in accordance with another embodiment of the present invention. Similar elements between CAM arrays  400 ( 2 ) and  400 ( 1 ) (FIG. 4A) are labeled similarly. Thus, CAM array  400 ( 2 ) includes SRAM cells  301 A- 304 A and  301 B- 304 B which are coupled to bit lines B 1B , B 1A #, B 2B , and B 2A #, data lines D 1 , D 1 #, D 2 , and D 2 #, control lines C 1  and C 2 , word lines WL 1 , and WL 3 , the V CC  voltage supply source, and match lines MATCH 1  and MATCH 2 . Note that word lines WL 1  and WL 2  (FIG. 4A) are combined into one word line WL 1  (FIG. 4C) and word lines WL 3  and WL 4  (FIG. 4A) are combined into one word line WL 3  (FIG.  4 C). As a result, the gates of transistors  310 - 313  are held to the same voltage (i.e., the voltage level of word line WL 1 ) and the gates of transistors  314 - 317  are held to the same voltage (i.e., the voltage level of word line WL 3 ). Thus, for example, when the voltage on bit line B 1A # is being applied to node N 1A # through turned on transistor  310 , then the voltage on bit line B 1B  is simultaneously being applied to node N 1B  through turned on transistor  311 . The benefit of the single word line for a row of CAM cells is smaller cells size. CAM array  400 ( 2 ) operates similarly to CAM array  400 ( 1 ). 
     FIG. 4D is a schematic diagram of ternary CAM array  400 ( 3 ) in accordance with another embodiment of the present invention. Similar elements between CAM arrays  400 ( 3 ) and  400 ( 1 ) (FIG. 4A) are labeled similarly. Thus, CAM array  400 ( 3 ) includes SRAM cells  301 A- 302 A and  301 B- 302 B which are coupled to bit lines B 1  and B 2 , data lines D 1 , D 1 #, D 2 , and D 2 #, control line C 1 , word lines WL 1 , and WL 2 , the V CC  voltage supply source, and match line MATCH 1 . SRAM cells  301 A and  301 B form CAM cell  409  and SRAM cells  302 A and  302 B form CAM cell  410 . Note that bit lines B 1A # and B 1B  (FIG. 4A) are combined into one bit line B 1  (FIG. 4C) and bit lines B 2A # and B 2B  (FIG. 4A) are combined into one bit line B 2  (FIG.  4 C). As a result, a terminal of each of transistors  310  and  311  is held to the same voltage (i.e., the voltage level of bit line B 1 ) and a terminal of each of transistors  313  and  314  is held to the same voltage (i.e., the voltage level of bit line B 2 ). As a result, SRAM cells  301 A and  301 B may not be written with different data values simultaneously. However, the single bit line allows a smaller array size. CAM array  400 ( 3 ) operates similarly to CAM array  400 ( 1 ). 
     Second Embodiment: 13-T Ternary CAM Cell 
     FIG. 5A is a schematic diagram of ternary CAM cell  501 ( 1 ) in accordance with another embodiment of the present invention. Similar elements between CAM cells  501 ( 1 ) and  401  (FIG. 4B) are labeled similarly. Thus, CAM cell  501 ( 1 ) includes SRAM cells  301 A and  301 B and n-channel transistor  370 . CAM cell  501 ( 1 ) is coupled to bit lines B 1B  and B 1A #, data lines D 1  and D 1 #, control line C 1 , word lines WL 1  and WL 2 , the V CC  voltage supply source, match line MATCH 1 , and the V SS  voltage supply source as described below. A no-match condition in CAM cell  501 ( 1 ) occurs when match line MATCH 1  is pulled to a logic low value as described below. 
     CAM cell  501 ( 1 ) includes SRAM cells  301 A and  301 B. Transistor  310  is coupled as an access transistor between bit line B 1A # and node N 1A #. The gate of transistor  310  is coupled to word line WL 1 . Transistor  318  is coupled as an access transistor between node N 1C  and node N 1A . The gate of transistor  318  is coupled to data line D 1 . SRAM cell  301 A is coupled between the V CC  power supply source (e.g., at terminals of transistors  342  and  343 ) and the V SS  power supply source (e.g., at terminals of transistors  326  and  327 ). Transistor  311  is coupled as an access transistor between bit line B 1B  and node N 1B . The gate of transistor  311  is coupled to word line WL 2 . Transistor  319  is coupled as an access transistor between node N 1C  and node N 1B #. The gate of transistor  319  is coupled to data line D 1 #. SRAM cell  301 B is coupled between the V CC  power supply source (e.g., at terminals of transistors  344  and  345 ) and the V SS  power supply source (e.g., at terminals of transistors  328  and  329 ). Transistor  370  is coupled between match line MATCH 1  and node N 1C . Transistor  370  has a gate coupled to control line C 1 . 
     The operation of CAM cell  501 ( 1 ) is similar to that of CAM cell  401 , and will now be described. In a standby state, word lines WL 1  and WL 2  and data lines D 1  and D 1 # are pulled down to logic low values, thereby turning off access transistors  310 ,  311 ,  318 , and  319 , respectively. Match line MATCH 1  is held to a logic low value and the value of control line C 1  does not matter but is preferentially left in it&#39;s last state. Under these conditions, SRAM cells  301 A and  301 B latch the values at nodes N 1A  and N 1B  (and the inverted values N 1A # and N 1B #), respectively. 
     Similarly to that described for CAM cell  401  (FIG.  4 B), a write operation to CAM cell  501 ( 1 ) may accomplish one of three tasks: data is written to SRAM cell  301 A, data is written to SRAM cell  301 B, or data is written to both SRAM cells  301 A and  301 B simultaneously. Because each of SRAM cells  301 A and  301 B hold a single bit, one of a logic high value and a logic low value may be written to each of SRAM cells  301 A and  301 B. Because CAM cell  501 ( 1 ) holds two bits (i.e., the values stored in SRAM cells  301 A and  301 B), one of a logic high value, a logic low value, and a logic “don&#39;t care” value may be written to CAM cell  501 ( 1 ). To write a data value to CAM cell  501 ( 1 ), bit line B 1A # and data line D 1  are held to a first write data value and bit line B 1B  and data line D 1 # are held to a second write data value. Control line C 1  is held to a logic high value. Match line MATCH 1  is held to a logic low value, thereby coupling the logic low value of match line MATCH 1  to node N 1C  through turned on transistor  370 . Word lines WL 1  and WL 2  are pulled up to logic high values to perform the write operation. 
     Write operations for logic high values, logic low values, and logic “don&#39;t care” values are performed similarly to those of CAM cell  401  described above. 
     SRAM cell  301 A may be written independently of SRAM cell  301 B. To write a first data value to SRAM cell  301 A, bit line B 1A # and data line D 1  are held to the inverse of the first write data value. Data line D 1 #, word line WL 2 , and match line MATCH 1  are held to logic low values. Control line C 1  is held to a logic high value, thereby coupling the logic low value of match line MATCH 1  to node N 1C . Word line WL 1  is pulled up to a logic high value to perform the write operation. Under these conditions, a write operation to SRAM cell  301 A is performed similarly to the write operation of SRAM cell  301 A in FIG.  4 B. 
     SRAM cell  301 B may be written independently of SRAM cell  301 A in a fashion similar to that described for SRAM cell  301 A above. To write a first data value to SRAM cell  301 B, bit line B 1B  and data line D 1 # are held to the first write data value. Data line D 1 , word line WL 1 , and match line MATCH 1  are held to logic low values. Control line C 1  is held to a logic high value, thereby coupling the logic low value of the match line MATCH 1  to node N 1C . Word line WL 2  is pulled up to a logic high value to perform the write operation. Under these conditions, a write operation to SRAM cell  301 B is performed similarly to the write operation of SRAM cell  301 B (FIG.  4 B). 
     To read a data value from both SRAM cells  301 A and  301 B simultaneously (i.e., to read a data value from CAM cell  501 ( 1 )), bit lines B 1A # and B 1B  are both pre-charged to a logic high value. Data lines D 1  and D 1 # are held to logic low values. The values of control line C 1  and match line MATCH 1  do not matter and are therefore left in their previous states. Word lines WL 1  and WL 2  are pulled up to logic high values to perform the read operation. Read operations for logic high values, logic low values, and logic “don&#39;t care” values are then performed similarly to those of CAM cell  401  described above. 
     SRAM cell  301 A may be read independently of SRAM cell  301 B. To read a first data value from SRAM cell  301 A, bit line B 1A # is pre-charged to a logic high value. Data line D 1 , data line D 1 # and word line WL 2  are held to logic low values. The values of bit line B 1B , match line MATCH 1 , and control line C 1  do not matter, and so are preferentially left in their last state. Word line WL 1  is pulled up to a logic high value to perform the read operation. Read operations for logic high values and logic low values are then performed similarly to those of SRAM cell  301 A (FIG. 4B) described above. 
     Similarly, SRAM cell  301 B may be read independently of SRAM cell  301 A. To read a first data value from SRAM cell  301 B, bit line B 1B  is pre-charged to a logic high value. Data line D 1 , data line D 1 #, and word line WL 1  are held to logic low values. The values of bit line B 1B #, match line MATCH 1 , and control line C 1  do not matter, and so are preferentially left in their last state. Word line WL 2  is pulled up to a logic high value to perform the read operation. Read operations for logic high values and logic low values are then performed similarly to those of SRAM cell  301 B described above. 
     A compare operation from CAM cell  501 ( 1 ) may accomplish one of three tasks: applied data is compared to SRAM cell  301 A, applied data is compared to SRAM cell  301 B, or applied data is compared to both SRAM cells  301 A and  301 B simultaneously. Because SRAM cells  301 A and  301 B each hold a single bit, only a single bit (i.e., a logic high or a logic low value) may be compared to each of SRAM cells  301 A and  301 B. Similarly, because CAM cell  501 ( 1 ) holds two bits, one of a logic high value, a logic low value, and a logic “don&#39;t care” value may be compared to the data stored in CAM cell  501 ( 1 ). To compare a data value to CAM cell  501 ( 1 ), match line MATCH 1  is pre-charged to a logic high value. Word lines WL 1  and WL 2  are held to logic low values. Control line C 1  is held to a logic high value, thereby coupling the pre-charged logic high value of match line MATCH 1  to node N 1C . The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous states. A compare data value is applied to data lines D 1  and D 1 # to perform the compare operation. 
     To compare a logic high compare data value to CAM cell  501 ( 1 ), data line D 1  is held to a logic high value and data line D 1 # is held to a logic low value. Under these conditions, the logic low value of data line D 1 # turns off transistor  319 , thereby de-coupling the pre-charged logic high value at node N 1C  from node N 1B #. Thus, the logic value stored in SRAM cell  301 B does not affect the prearged charged logic high value of match line MATCH 1  during the compare operation. The logic high value of data line D 1  turns on transistor  318 , thereby coupling the pre-charged logic high value at node N 1C  to node N 1A . If CAM cell  501 ( 1 ) stores a matching logic high value (SRAM cell  301 A node N 1A  stores a logic high value and node N 1A # stores a logic low value), then node N 1A  is de-coupled from the V SS  voltage supply source due to turned off transistor  327 . As a result, match line MATCH 1  remains in a logic high state, thereby indicating a match condition. Similarly, if CAM cell  501 ( 1 ) stores a logic “don&#39;t care” value (SRAM cell  301 A node N 1A  stores a logic high value and node N 1A # stores a logic low value), then match line MATCH 1  similarly remains in a logic high state, thereby indicating a match condition. If CAM cell  501 ( 1 ) stores a non-matching logic low value (SRAM cell  301 A node N 1A  stores a logic low value and node N 1A # stores a logic high value), then node N 1A  is coupled to the V SS  voltage supply source through turned on transistor  327 . As a result, match line MATCH 1  is pulled down to the logic low value through turned on transistors  318 ,  327 , and  370 , thereby indicating a no-match condition. 
     To compare a logic low compare data value to CAM cell  501 ( 1 ), data line D 1  is held to a logic low value and data line D 1 # is held to a logic high value. Under these conditions, the logic low value of data line D 1  turns off transistor  318 , thereby de-coupling the pre-charged logic high value at node N 1C  from node N 1A . Thus, the logic value stored in SRAM cell  301 A does not affect the value of match line MATCH 1  during the compare operation. The logic high value of data line D 1 # turns on transistor  319 , thereby coupling the pre-charged logic high value at node N 1C  to node N 1B #. If CAM cell  501 ( 1 ) stores a matching logic low value (i.e., SRAM cell  301 B node N 1B  stores a logic low value and node N 1B # stores a logic high value), then node N 1B # is de-coupled from the V SS  voltage supply source due to turned off transistor  328 . As a result, match line MATCH 1  remains in a logic high state, thereby indicating a match condition. Similarly, if CAM cell  501 ( 1 ) stores a logic “don&#39;t care” value (SRAM cell  301 B node N 1B  stores a logic low value and node N 1B # stores a logic high value), then match line MATCH 1  similarly remains in a logic high state, thereby indicating a match condition. If CAM cell  501 ( 1 ) stores a non-matching logic high value (SRAM cell  301 B node N 1B  stores a logic high value and node N 1B # stores a logic low value), then node N 1B # is coupled to the V SS  voltage supply source through turned on transistor  328 . As a result, match line MATCH 1  is pulled down to a logic low value through turned on transistors  319 ,  328 , and  370 , thereby indicating a no-match condition. 
     To compare a logic “don&#39;t care” compare data value to CAM cell  501 ( 1 ), data lines D 1  and D 1 # are held to logic low values. Under these conditions, the logic low values of data lines D 1  and D 1 # turn off transistors  318  and  319 , respectively, thereby de-coupling the pre-charged logic high value of match line MATCH 1  from nodes N 1A  and N 1B #. Thus, the logic values stored in SRAM cells  301 A and  301 B do not affect the value of match line MATCH 1  during the compare operation. As a result, match line MATCH 1  remains at a logic high value, thereby indicating a match condition for all logic values stored in CAM cell  501 . 
     SRAM cell  301 A may be compared to a data value independent of SRAM cell  301 B. To compare a first data value to SRAM cell  301 A, match line MATCH 1  is pre-charged to a logic high value. Control line C 1  is held to a logic high value, thereby coupling the pre-charged logic high value of match line MATCH 1  to node N 1C . Word lines WL 1  and WL 2  and data line D 1 # are held to logic low values. The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous states. A compare data value is applied to data line D 1  to perform the compare operation. The logic low values of word line WL 2  and data line D 1 # isolate CAM cell  301 B from the compare operation. The compare operation is then carried out similarly to that described above with respect to a comparison operation on CAM cell  501 ( 1 ). 
     Similarly, SRAM cell  301 B may be compared to a data value independent of SRAM cell  301 A. To compare a compare data value to SRAM cell  301 B, match line MATCH 1  is pre-charged to a logic high value. Control line C 1  is held to a logic high value, thereby coupling the pre-charged value of match line MATCH 1  to node N 1C . Word lines WL 1  and WL 2  and data line D 1  are held to logic low values. The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous states. A data value equivalent to the inverted compare data value is applied to data line D 1 # to perform the compare operation. The logic low values of word line WL 2  and data line D 1  isolate CAM cell  301 A from the compare operation. The compare operation is then carried out similarly to that described above with respect to a comparison operation on CAM cell  501 ( 1 ). 
     In this manner, the beneficial result of having a CAM cell which results in a logic high value of the match line for a match condition and results in a logic low value of the match line for a no-match condition is achieved while maintaining a small CAM cell size. 
     Note that variations of CAM cell  501 ( 1 ) are possible, such as a variation combining word lines WL 1  and WL 2  and a variation combining bit lines B 1A # and B 1B . 
     FIG. 5B is a schematic diagram of ternary CAM cell  501 ( 2 ) in accordance with a variation of the present embodiment. Similar elements between CAM cells  501 ( 1 ) (FIG. 5A) and  501 ( 2 ) are labeled similarly. Thus, CAM cell  501 ( 2 ) includes n-channel transistors  310 ,  311 ,  318 ,  319 ,  326 - 329 , and  370  and p-channel transistors  342 - 345 . In contrast to CAM cell  501 ( 1 ), transistors  326 - 329  of CAM cell  501 ( 2 ) have terminals coupled to low match line LM 1 . 
     CAM cell  501 ( 2 ) functions similarly to CAM cell  501 ( 1 ). However, the use of low match line LM 1  enables a beneficial power savings in CAM cell  501 ( 2 ), for example, during a standby condition when low match line LM 1  is allowed to float above a grounding voltage. 
     Third Embodiment: 14-T Ternary CAM Cell 
     FIG. 6A is a schematic diagram of ternary CAM cell  601 ( 1 ) in accordance with another embodiment of the present invention. Similar elements between CAM cells  601 ( 1 ) and  501 ( 1 ) (FIG. 5A) are labeled similarly. Thus, CAM cell  601 ( 1 ) includes SRAM cells  301 A and  301 B and n-channel transistors  370  and  371 . CAM cell  601 ( 1 ) is coupled to bit lines B 1B  and B 1A #, data lines D 1  and D 1 #, word line WL 1 , the V CC  voltage supply source, match line MATCH 1 , and the V SS  voltage supply source as described below. A no-match condition in CAM cell  601 ( 1 ) occurs when match line MATCH 1  is pulled down to a logic low value as described below. 
     CAM cell  601 ( 1 ) includes SRAM cells  301 A and  301 B. Transistor  310  is coupled as an access transistor between bit line B 1A # and node N 1A #. The gate of transistor  310  is coupled to word line WL 1 . Transistor  318  is coupled as an access transistor between node N 1C  and node N 1A . The gate of transistor  318  is coupled to data line D 1 . SRAM cell  301 A is coupled between the V CC  power supply source (e.g., at terminals of transistors  342  and  343 ) and the V SS  power supply source (e.g., at terminals of transistors  326  and  327 ). Transistor  311  is coupled as an access transistor between bit line B 1B  and node N 1B . The gate of transistor  311  is coupled to word line WL 1 . Transistor  319  is coupled as an access transistor between node N 1C  and node N 1B #. The gate of transistor  319  is coupled to data line D 1 #. SRAM cell  301 B is coupled between the V CC  power supply source (e.g., at terminals of transistors  344  and  345 ) and the V SS  power supply source (e.g., at terminals of transistors  328  and  329 ). Transistor  370  is coupled between match line MATCH 1  and node N 1C . Transistor  370  also has a gate coupled to match line MATCH 1 . Transistor  371  is coupled between node N 1C  and the V SS  power supply source. Transistor  371  has a gate coupled to word line WL 1 . 
     The operation of CAM cell  601 ( 1 ) is similar to that of CAM cell  501 ( 1 ), and will now be described. In a standby state, word line WL 1 , data lines D 1  and D 1 #, and match line MATCH 1  are pulled down to logic low values, thereby turning off transistors  310 ,  311 , and  371 ,  318 ,  319 , and  370 , respectively. Under these conditions, SRAM cells  301 A and  301 B latch the values stored at nodes N 1A  and N 1B  (and the inverted values stored at N 1A # and N 1B #), respectively. 
     Similarly to that described for CAM cell  501 ( 1 ), a write operation to CAM cell  601 ( 1 ) may accomplish one of three tasks: data is written to SRAM cell  301 A, data is written to SRAM cell  301 B, or data is written to both SRAM cells  301 A and  301 B simultaneously. Because SRAM cells  301 A and  301 B each hold a single bit, one of a logic high value and a logic low value may be written to each of SRAM cells  301 A and  301 B. Because CAM cell  601 ( 1 ) holds two bits (i.e., the values stored in SRAM cells  301 A and  301 B), one of a logic high value, a logic low value, and a logic “don&#39;t care” value may be written to CAM cell  601 ( 1 ). To write a data value to CAM cell  601 ( 1 ), bit line B 1A # and data line D 1  are held to a first write data value and bit line B 1B  and data line D 1 # are held to a second write data value. Match line MATCH 1  is held to a logic low value, thereby de-coupling match line MATCH 1  from node N 1C  through turned off transistor  371 . Word line WL 1  is pulled up to logic high values to perform the write operation and couple node N 1C  to the V SS  voltage power supply. 
     Write operations for logic high values, logic low values, and logic “don&#39;t care” values are performed similarly to those of CAM cell  501 ( 1 ) described above. 
     SRAM cell  301 A may be written independently of SRAM cell  301 B. To write a first data value to SRAM cell  301 A, bit line B 1A # and data line D 1  are held to the inverse of the first write data value. Data line D 1 # and match line MATCH 1  are held to logic low values. The logic low value of match line MATCH 1  de-couples the logic low value of match line MATCH 1  from node N 1C . Bit line B 1B  is held to a logic high value to prevent disturbance of the data stored in SRAM cell  301 B. Word line WL 1  is pulled up to a logic high value to perform the write operation and couple node N 1C  to the V SS  voltage power supply. Under these conditions, a write operation to SRAM cell  301 A is performed similarly to a write operation to SRAM cell  501 ( 1 ) (FIG.  5 A). 
     SRAM cell  301 B may be written independently of SRAM cell  301 A in a fashion similar to that described for SRAM cell  301 A above. To write a first data value to SRAM cell  301 B, bit line B 1B  and data line D 1 # are held to the first write data value. Data line D 1  and match line MATCH 1  are held to logic low values. The logic low value of match line MATCH 1  de-couples the logic low value of match line MATCH 1  from node N 1C . Bit line B 1A # is held to a logic high value to prevent disturbance of the data stored in SRAM cell  301 A. Word line WL 1  is pulled up to a logic high value to perform the write operation and couple node N 1C  to the V SS  voltage power supply. Under these conditions, a write operation to SRAM cell  301 B is performed similarly to a write operation to SRAM cell  301 B (FIG.  5 A). 
     To read a data value from both SRAM cells  301 A and  301 B simultaneously (i.e., to read a data value from CAM cell  601 ( 1 )), bit lines B 1A # and B 1B  are both pre-charged to a logic high value. Data lines D 1  and D 1 # are held to logic low values. The value of match line MATCH 1  does not matter and is therefore left in it&#39;s previous state. Word line WL 1  is pulled up to a logic high value to perform the read operation. Read operations for logic high values, logic low values, and logic “don&#39;t care” values are then performed similarly to those of CAM cell  501 ( 1 ) (FIG. 5A) described above. 
     SRAM cell  301 A may be read independently of SRAM cell  301 B. To read a first data value from SRAM cell  301 A, bit line B 1A # is pre-charged to a logic high value. Data line D 1  and data line D 1 # are held to logic low values. Bit line B 1B  is held to a logic high value to prevent disturbance of SRAM cell  301 B. The value of match line MATCH 1  does not matter, and so is preferentially left in it&#39;s last state. Word line WL 1  is pulled up to a logic high value to perform the read operation. Read operations for logic high values and logic low values are then performed similarly to those of SRAM cell  301 A (FIG. 5A) described above. 
     Similarly, SRAM cell  301 B may be read independently of SRAM cell  301 A. To read a first data value from SRAM cell  301 B, bit line B 1B  is pre-charged to a logic high value. Data line D 1  and data line D 1 # are held to logic low values. Bit line B 1A # is held to a logic high value to prevent disturbance of SRAM cell  301 A. The value of match line MATCH 1  does not matter, and so is preferentially left in it&#39;s last state. Word line WL 1  is pulled up to a logic high value to perform the read operation. Read operations for logic high values and logic low values are then performed similarly to those of SRAM cell  301 B (FIG. 5A) described above. 
     A compare operation from CAM cell  601 ( 1 ) may accomplish one of three tasks: applied data is compared to SRAM cell  301 A, applied data is compared to SRAM cell  301 B, or applied data is compared to both SRAM cells  301 A and  301 B simultaneously. To compare a data value to CAM cell  601 ( 1 ), match line MATCH 1  is brought to a logic high value. Word line WL 1  is held to a logic low value, thereby de-coupling bit lines B 1B  and B 1A # and the V SS  power voltage supply from nodes N 1B , N 1A #, and N 1C , respectively. Match line MATCH 1  is pre-charged to a logic high value, thereby coupling a pre-charged logic high value to node N 1C . The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous states. A compare data value is applied to data lines D 1  and D 1 # to perform the compare operation. Compare operations for logic high values, logic low values, and logic “don&#39;t care” values are then performed similarly to those of SRAM cell  501 ( 1 ) FIG. 5A) described above. 
     SRAM cell  301 A may be compared to a data value independently of SRAM cell  301 B. To compare a first data value to SRAM cell  301 A, match line MATCH 1  is pre-charged to a logic high value. Word line WL 1  is held to a logic low value, thereby de-coupling node N 1C  from the V SS  power supply source via turned of transistor  371  and de-coupling bit lines B 1B  and B 1A # from nodes N 1B  and N 1A #, respectively. The pre-charged logic high value of match line MATCH 1  couples a pre-charged logic high value to node N 1C . Data line D 1 # is held to a logic low value. The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous state. A compare data value is applied to data line D 1  to perform the compare operation. The logic low values of word line WL 1  and data line D 1 # isolate CAM cell  301 B from the compare operation. The compare operation is then carried out similarly to that described above with respect to a comparison operation on CAM cell  601 ( 1 ). 
     Similarly, SRAM cell  301 B may be compared to a data value independently of SRAM cell  301 A. To compare a first data value to SRAM cell  301 B, match line MATCH 1  is pre-charged to a logic high value. Word line WL 1  is held to a logic low value, thereby de-coupling node N 1C  from the V SS  supply source via turned off transistor  371  and de-coupling bit lines B 1B  and B 1A # from nodes N 1B  and N 1A #, respectively. The pre-charged logic high value of match line MATCH 1  couples a pre-charged logic high value to node N 1C . Data line D 1  is held to a logic low value. The value of bit lines B 1B  and B 1A # do not matter and are therefore left in their previous state. A data value equivalent to the inverted compare data value is applied to data line D 1 # to perform the compare operation. The logic low values of word line WL 1  and data line D 1  isolate CAM cell  301 A from the compare operation. The compare operation is then carried out similarly to that described above with respect to a comparison operation on CAM cell  601 ( 1 ). 
     In this manner, the beneficial result of having a CAM cell which results in a logic high value of the match line for a match condition and results in a logic low value of the match line for a no-match condition is achieved while maintaining a small CAM cell size in another embodiment of the present invention. 
     FIG. 6B is a schematic diagram of ternary CAM cell  601 ( 2 ) in accordance with a variation of the present embodiment. Similar elements between CAM cells  601 ( 1 ) (FIG. 6A) and  601 ( 2 ) are labeled similarly. Thus, CAM cell  601 ( 2 ) includes SRAM cells  301 A and  301 B and n-channel transistors  370  and  371 . In contrast to CAM cell  601 ( 1 ), transistors  326 - 329  of CAM cell  601 ( 2 ) have terminals coupled to low match line LM 1 . 
     CAM cell  601 ( 2 ) functions similarly to CAM cell  601 ( 1 ). However, the use of low match line LM 1  enables a beneficial power savings in CAM cell  601 ( 2 ), for example, during a standby condition when low match line LM 1  is allowed to float above a grounding voltage. 
     Fourth Embodiment: 9-T Four-state CAM Cell Plus Mask 
     FIG. 7 is a schematic diagram of four-state CAM cell  701  in accordance with another embodiment of the present invention. CAM cell  701  includes SRAM cell  301 A, mask memory cell  701 B, and n-channel transistors  706 - 708 . CAM cell  701  is coupled to bit lines B 1  and B 1 #, data lines D 1  and D 1 #, control line C 1 , word line WL 1 , the V CC  voltage supply source, and match line MATCH 1  as described below. Mask memory cell  701 B may be any type of memory storage cell, including 1-T, 4-T, 5-T, 6-T, etc. memory cells. Mask memory cell  701 B may be coupled to word line WL 1  and one or more of bit lines B 1  and B 1 #. Thus, the total number of transistors in CAM cell  701  includes the sum of the nine transistors shown including SRAM cell  301 A plus the number of transistors in the chosen embodiment of memory mask  701 B. 
     SRAM  301 A is coupled between the V CC  voltage supply source and match line MATCH 1 . Access transistor  310  is coupled between bit line B 1 # and node N 1 #. Access transistor  318  is coupled between bit line B 1  and node N 1 . The gates of access transistors  310  and  318  are coupled to word line WL 1 . Access transistor  706  is coupled between a first terminal of mask transistor  708  and node N 1 #. Access transistor  707  is coupled between a first terminal of mask transistor  708  and node N 1 . The gates of access transistors  706  and  707  are coupled to data line D 1 # and D 1 , respectively. Mask transistor  708  has a second terminal coupled to control line C 1  and a gate coupled to mask memory cell  701 B. 
     In one variation of the present invention, mask memory cell  701 B is a conventional memory cell that is conventionally operated. In another variation of the present invention, mask memory cell  701 B is an SRAM cell according to the present invention (e.g., SRAM cell  301 A) and operated as described herein. Thus, operations to mask memory cell  701 B will not be described in detail. As a result, the descriptions below with respect to CAM cell  701  describe operations reading from and writing to SRAM cell  301 A. 
     A no-match condition in CAM cell  701  occurs when match line MATCH 1  is pulled up to a logic high value as described below. 
     The operation of CAM cell  701  will now be described. CAM cell  701  operations include standby, write, read, and compare operations. In a standby operation, word line WL 1  and data lines D 1  and D 1 # are pulled down to logic low values, thereby turning off access transistors  310  and  318 ,  707 , and  706 , respectively. The match line MATCH 1  is held to a logic low value and the control line C 1  is preferentially left in it&#39;s last state. Under these conditions, SRAM cell  301 A latches the values at node N 1  and the inverted value at node N 1 #. 
     SRAM cell  301 A holds a single bit. Thus, one of a logic high value and a logic low value may be written to SRAM cell  301 A. Note that mask memory cell  701 B also holds a single bit (i.e., one of a logic high value and a logic low value). 
     To write a data value (e.g., a logic high value) to SRAM cell  301 A, bit line B 1  is held to the first data value (e.g., a logic high value) and bit line B 1 # is held to the inverse of the first write data value (e.g., a logic low value). Data lines D 1  and D 1 # are held to logic low values, thereby turning of transistors  707  and  706 , respectively. Turned off transistors  706  and  707  de-couple SRAM cell  301 A from the first terminal of transistor  708 . Thus, the value stored in mask memory cell  701 B does not affect the write operation. Match line MATCH 1  is held to a logic low value. The value of control line C 1  does not matter, and therefore is left in it&#39;s last state. Word line WL 1  is pulled up to a logic high value to perform the write operation. 
     To write a logic high value to SRAM cell  301 A, bit line B 1  is held to a logic high value (i.e., a first write data value) and bit line B 1 # is held to a logic low value (i.e., a second write data value). Under these conditions, the logic high value of word line WL 1  turns on transistors  310  and  318 . As a result, turned on transistor  310  couples the logic low value of bit line B 1 # to node N 1 #, thereby pulling up node N 1  to a logic high value through turned on transistor  343 . Note that turned on transistor  318  also pulls up node N 1  to a logic high value. As a result, SRAM cell  301 A stores a logic high value. 
     To write a logic low value to SRAM cell  301 A, bit line B 1  is held to a logic low value (i.e., a first write data value) and bit line B 1 # is held to a logic high value (i.e., a second write data value). Under these conditions, the logic high value of word line WL 1  turns on transistors  310  and  318 . As a result, turned on transistor  318  couples the logic low value of bit line B 1  to node N 1 , thereby pulling up node N 1 # to a logic high value through turned on transistor  342 . Note that turned on transistor  310  also pulls up node N 1 # to a logic high value. As a result, SRAM cell  301 A stores a logic low value. 
     A read operation from CAM cell  701  will now be described. As described above, because SRAM cell  301 A holds a single bit, one of a logic high value and a logic low value may be read from SRAM cell  301 A. To read a data value from SRAM cell  301 A, both bit lines B 1 # and B 1  are pre-charged to a logic high value. Data lines D 1  and D 1 # and match line MATCH 1  are held to logic low values. The value of control line C 1  does not matter and is therefore left in it&#39;s previous state. Word line WL 1  is pulled up to logic a high value to perform the read operation. 
     During a read operation from CAM cell  701 , the logic high value of word line WL 1  turns on transistor  318 , thereby coupling the pre-charged logic high value of bit line B 1  to node N 1 . As a result, a logic low value stored at node N 1  pulls down bit line B 1  to a logic low value and a logic high value stored at node N 1  causes bit line B 1  to remain at a logic high value. Similarly, the logic high value of word line WL 1  turns on transistor  310 , thereby coupling the pre-charged logic high value of bit line B 1 # to node N 1 #. As a result, a logic low value stored at node N 1 # pulls down bit line B 1 # to a logic low value and a logic high value stored at node N 1 # causes bit line B 1 # to remain at a logic high value. Because bit line B 1 # is coupled to the inverted storage node of SRAM cell  301 A (i.e., node N 1 #), bit line B 1 # is an inverted value bit line. Thus, the data read from bit line B 1 # (i.e., the data value stored at node N 1 #) is the opposite value of the data value stored in SRAM cell  301 A (i.e., the data value stored at node N 1A ). 
     For example, if CAM cell  701  stores a logic high value, then node N 1  stores a logic high value and node N 1 # stores a logic low value. Under these conditions, a read operation results in bit line B 1 # having a logic low value and bit line B 1  having a logic high value. As a result, a logic high value is read from CAM cell  701 . Note that the logic value stored in mask memory cell  701 B does not affect this read value. Therefore, a read operation from CAM cell  701  returns a logic high value both when CAM cell  301 A stores a logic high value (e.g., mask memory cell  701 B stores a logic high value) and when CAM cell  301 A stores a logic high “don&#39;t care” value (e.g., mask memory cell  701 B stores a logic low value). Similarly, a read operation from CAM cell  701  returns a logic low value both when CAM cell  301 A stores a logic low value (e.g., mask memory cell  701 B stores a logic high value) and when CAM cell  301 A stores a logic low “don&#39;t care” value (e.g., mask memory cell  701 B stores a logic low value). In this way, CAM cell  701  provides meaningful data for “don&#39;t care” values. 
     A compare operation from CAM cell  701  will now be described. Match line MATCH 1  is pre-charged to a logic low value. Control line C 1  is held to a logic high value and word line WL 1  is held to a logic low value. The value of bit lines B 1  and B 1 # do not matter and are therefore left in their previous states. A compare data value is applied to data lines D 1  and D 1 # to perform the compare operation. 
     To compare a logic high compare data value to CAM cell  701 , data line D 1  is held to a logic high value and data line D 1 # is held to a logic low value. Under these conditions, the logic low value of data line D 1 # turns off transistor  706 , thereby de-coupling the first terminal of transistor  708  from node N 1 #. The logic high value of data line D 1  turns on transistor  707 , thereby coupling the first terminal of transistor  708  to node N 1 . If mask memory cell  701 B stores a logic low value, node N 1  is de-coupled from the logic high value of control line C 1  via turned off transistor  708 . Thus, turned off transistor  708  prevents a change in the value of match line MATCH 1  due to the value stored in CAM cell  701 . In this way, CAM cell  701  is masked from the compare operation. As a result, whether SRAM cell  301 A stores a logic high value or a logic low value, CAM cell  701  effectively stores a logic “don&#39;t care” value. 
     If mask memory cell  701 B stores a logic high value, node N 1  is coupled to the logic high value of control line C 1  via turned on transistor  708 . As a result, CAM cell  701  participates in the compare operation. If CAM cell  701  stores a matching logic high value (SRAM cell  301 A node N 1  stores a logic high value), then node N 1  is de-coupled from match line MATCH 1  due to turned off transistor  327 . As a result, match line MATCH 1  remains in a logic low state, thereby indicating a match condition. If CAM cell  701  stores a non-matching logic low value (SRAM cell  301 A node N 1  stores a logic low value), then node N 1  is coupled to match line MATCH 1  through turned on transistor  327 . As a result, match line MATCH 1  is pulled up to the logic high value of control line C 1  through turned on transistors  327 ,  707 , and  708 , thereby indicating a no-match condition. 
     To compare a logic low compare data value to CAM cell  701 , data line D 1  is held to a logic low value and data line D 1 # is held to a logic high value. Under these conditions, the logic low value of data line D 1  turns off transistor  707 , thereby de-coupling the first terminal of transistor  708  from node N 1 . The logic high value of data line D 1 # turns on transistor  706 , thereby coupling the first terminal of transistor  708  to node N 1 #. As described above, if mask memory cell  701 B stores a logic low value, then CAM cell  701  is masked from the compare operation. However, if mask memory cell  701 B stores a logic high value, then CAM cell  701  participates in the compare operation. If CAM cell  701  stores a matching logic low value (SRAM cell  301 A node N 1  stores a logic low value), then node N 1 # is de-coupled from match line MATCH 1  due to turned off transistor  326 . As a result, match line MATCH 1  remains in a logic low state, thereby indicating a match condition. If CAM cell  701  stores a non-matching logic high value (SRAM cell  301 A node N 1  stores a logic high value), then node N 1 # is coupled to match line MATCH 1  through turned on transistor  326 . As a result, match line MATCH 1  is pulled up to the logic high value of control line C 1  through turned on transistors  326 ,  706 , and  708 , thereby indicating a no-match condition. 
     To compare a logic “don&#39;t care” compare data value to CAM cell  701 , data lines D 1  and D 1 # are held to logic low values. Under these conditions, the logic low values of data lines D 1  and D 1 # turn off transistors  707  and  706 , respectively, thereby de-coupling the first terminal of transistor  708  (and in turn control line C 1 ) from nodes N 1  and N 1 #. Thus, the logic value stored in SRAM cell  301 A does not affect the value of match line MATCH 1  during the compare operation. As a result, match line MATCH 1  remains at a logic low value, thereby indicating a match condition for all values stored in CAM cell  701 . 
     Operations similar to those described above may be performed on a row of CAM cells similar to CAM cell  701  by applying the techniques described above to the other CAM cells in the row. A comparison operation in CAM cell  701  results in a logic low value of the match line MATCH 1  if the applied comparison data value matches the data value stored in CAM cell  701 , and results in a logic high value of the match line MATCH 1  if the applied comparison data value does not match the data value stored in CAM cell  701 . 
     Fifth Embodiment: 9-T Four-state CAM Cell Plus Mask 
     FIG. 8 is a schematic diagram of four-state CAM cell  801  in accordance with another embodiment of the present invention. Similar elements in CAM cells  801  and  701  (FIG. 7) are labeled similarly. CAM cell  801  includes SRAM cell  301 A mask, memory cell  701 B, and n-channel transistors  707 ,  708 , and  711 . CAM cell  801  is coupled to bit line B 1 , data lines D 1  and D 1 #, control line C 1 , word line WL 1 , the VCc voltage supply source, and match line MATCH 1  as described below. Mask memory cell  701 B may be any type of memory storage cell, including SRAM cells as described herein. Thus, the total number of transistors in CAM cell  801  includes the sum of the nine transistors shown including SRAM cell  301 A plus the number of transistors in the chosen embodiment of memory mask  701 B. 
     SRAM cell  301 A is coupled between the V CC  voltage supply source and match line MATCH 1 . Access transistor  310  is coupled between a first terminal of mask transistor  708  and node N 1 #. Access transistor  318  is coupled between bit line B 1  and node N 1 . Pull-down transistor  711  is coupled between a first terminal of mask transistor  708  and the V SS  voltage supply source. The gates of access transistor  318  and pull-down transistor  711  are coupled to word line WL 1 . Access transistor  707  is coupled between a first terminal of mask transistor  708  and node N 1 . The gates of access transistors  310  and  707  are coupled to data line D 1 # and D 1 , respectively. Mask transistor  708  has a second terminal coupled to control line C 1  and a gate coupled to mask memory cell  701 B. 
     As described above, mask memory cell  701 B stores one of a logic high and a logic low value. Thus, the descriptions below with respect to CAM cell  801  describe operations reading from and writing to SRAM cell  301 A. 
     A no-match condition in CAM cell  801  occurs when match line MATCH 1  is pulled up to a logic high value as described below. 
     The operation of CAM cell  801  will now be described. CAM cell  801  operations include standby, write, read, and compare operations. In a standby operation, word line WL 1  and data lines D 1 # and D 1  are pulled down to logic low values, thereby turning off transistors  318  and  711 ,  310 , and  707 , respectively. The match line MATCH 1  is held to a logic low value and the control line C 1  is preferentially left in it&#39;s last state. Under these conditions, SRAM cell  301 A latches the values at node N 1  and the inverted value at node N 1 #. 
     SRAM cell  301 A holds a single bit. Thus, one of a logic high value and a logic low value may be written to SRAM cell  301 A. To write a data value (e.g., a logic high value) to SRAM cell  301 A, bit line B 1  and data line D 1 # are held to the first data value (e.g., a logic high value). Data line D 1  is held to a logic low value, thereby turning of transistor  707 . Turned off transistor  707  de-couples node N 1  of SRAM cell  301 A from the first terminal of transistor  708 . Both match line MATCH 1  and control line C 1  are held to logic low values. Word line WL 1  is pulled up to a logic high value to perform the write operation. 
     To write a logic high value to SRAM cell  301 A, bit line B 1  and data line D 1 # are held to logic high values (i.e., a first write data value). Under these conditions, the logic high value of word line WL 1  turns on transistors  711  and  318 . Turned on transistor  711  couples a first terminal of transistor  708  to ground (e.g., the V SS  supply source). As a result, turned on transistor  310  couples the logic low value of ground to node N 1 #, thereby pulling up node N 1  to a logic high value through turned on transistor  343 . Note that turned on transistor  318  also pulls up node N 1  to a logic high value. As a result, SRAM cell  301 A stores a logic high value. 
     To write a logic low value to SRAM cell  301 A, bit line B 1  and data line D 1 # are held to logic low values (i.e., a first write data value). Under these conditions, the logic high value of word line WL 1  turns on transistors  711  and  318 . As a result, turned on transistor  318  couples the logic low value of bit line B 1  to node N 1 , thereby pulling up node N 1 # to a logic high value through turned on transistor  342 . Turned off transistor  310  de-couples node N 1 # from the logic low value of ground applied through turned on transistor  711 . As a result, SRAM cell  301 A stores a logic low value. 
     A read operation from CAM cell  801  will now be described. As described above, because SRAM cell  301 A holds a single bit, one of a logic high value and a logic low value may be read from SRAM cell  301 A. To read a data value from SRAM cell  301 A, bit line B 1 # is pre-charged to a logic high value. Data lines D 1  and D 1 #, control line C 1 , and match line MATCH 1  are held to logic low values. Word line WL 1  is pulled up to logic a high value to perform the read operation. 
     During a read operation from CAM cell  801 , the logic high value of word line WL 1  turns on transistor  318 , thereby coupling the pre-charged logic high value of bit line B 1  to node N 1 . As a result, a logic low value stored at node N 1  pulls down bit line B 1  to a logic low value and a logic high value stored at node N 1  causes bit line B 1  to remain at a logic high value. 
     A compare operation from CAM cell  801  will now be described. Match line MATCH 1  is pre-charged to a logic low value. Control line C 1  is held to a logic high value. Word line WL 1  is held to a logic low value, thereby turning off transistors  318  and  711 . The value of bit line B 1  does not matter and is therefore left in it&#39;s previous state. A compare data value is applied to data lines D 1  and D 1 # to perform the compare operation. 
     To compare a logic high compare data value to CAM cell  801 , data line D 1  is held to a logic high value and data line D 1 # is held to a logic low value. Under these conditions, the logic low value of data line D 1 # turns off transistor  310 , thereby de-coupling the first terminal of transistor  708  from node N 1 #. The logic high value of data line D 1  turns on transistor  707 , thereby coupling the first terminal of transistor  708  to node N 1 . If mask memory cell  701 B stores a logic low value, node N 1  is de-coupled from the logic high value of control line C 1  via turned off transistor  708 . Thus, turned off transistor  708  prevents a change in the value of match line MATCH 1  due to the value stored in CAM cell  801 . In this way, CAM cell  801  is masked from the compare operation. As a result, whether SRAM cell  301 A stores a logic high value or a logic low value, CAM cell  801  effectively stores a logic “don&#39;t care” value. 
     If mask memory cell  801 B stores a logic high value, node N 1  is coupled to the logic high value of control line C 1  via turned on transistor  708 . As a result, CAM cell  801  participates in the compare operation. If CAM cell  801  stores a matching logic high value (SRAM cell  301 A node N 1  stores a logic high value), then node N 1  is de-coupled from match line MATCH 1  due to turned off transistor  327 . As a result, match line MATCH 1  remains in a logic low state, thereby indicating a match condition. If CAM cell  801  stores a non-matching logic low value (SRAM cell  301 A node N 1  stores a logic low value), then node N 1  is coupled to match line MATCH 1  through turned on transistor  327 . As a result, match line MATCH 1  is pulled up to the logic high value of control line C 1  through turned on transistors  327 ,  707 , and  708 , thereby indicating a no-match condition. 
     To compare a logic low compare data value to CAM cell  801 , data line D 1  is held to a logic low value and data line D 1 # is held to a logic high value. Under these conditions, the logic low value of data line D 1  turns off transistor  707 , thereby de-coupling the first terminal of transistor  708  from node N 1 . The logic high value of data line D 1 # turns on transistor  310 , thereby coupling the first terminal of transistor  708  to node N 1 #. As described above, if mask memory cell  701 B stores a logic low value, then CAM cell  801  is masked from the compare operation. However, if mask memory cell  701 B stores a logic high value, then CAM cell  801  participates in the compare operation. If CAM cell  801  stores a matching logic low value (SRAM cell  301 A node N 1  stores a logic low value), then node N 1 # is de-coupled from match line MATCH 1  due to turned off transistor  326 . As a result, match line MATCH 1  remains in a logic low state, thereby indicating a match condition. If CAM cell  801  stores a non-matching logic high value (SRAM cell  301 A node N 1  stores a logic high value), then node N 1 # is coupled to match line MATCH 1  through turned on transistor  326 . As a result, match line MATCH 1  is pulled up to the logic high value of control line C 1  through turned on transistors  326 ,  310 , and  708 , thereby indicating a no-match condition. 
     To compare a logic “don&#39;t care” compare data value to CAM cell  801 , data lines D 1  and D 1 # are held to logic low values. Under these conditions, the logic low values of data lines D 1  and D 1 # turn off transistors  707  and  310 , respectively, thereby de-coupling the first terminal of transistor  708  (and in turn control line C 1 ) from nodes N 1  and N 1 #. Thus, the logic value stored in SRAM cell  301 A does not affect the value of match line MATCH 1  during the compare operation. As a result, match line MATCH 1  remains at a logic high value, thereby indicating a match condition for all values stored in CAM cell  801 . 
     Operations similar to those described above may be performed on a row of CAM cells similar to CAM cell  801  by applying the techniques described above to the other CAM cells in the row. A comparison operation in CAM cell  801  results in a logic low value of the match line MATCH 1  if the applied comparison data value matches the data value stored in CAM cell  801 , and results in a logic high value of the match line MATCH 1  if the applied comparison data value does not match the data value stored in CAM cell  801 . As noted above, it is also beneficial to have a CAM cell which results in a logic high value of the match line for a match condition and results in a logic low value of the match line for a no-match condition. 
     Sixth Embodiment: 10-T Four-state CAM Cell Plus Mask 
     FIG. 9A is a schematic diagram of four-state CAM cell  901  in accordance with another embodiment of the present invention. Similar elements in CAM cells  901  and  801  (FIG. 8) are labeled similarly. CAM cell  901  includes SRAM cell  301 A, mask memory cell  901 B, control circuit  912 , and n-channel transistors  906  and  907 . CAM cell  901  is coupled to bit lines B 1  and B 1 #, data lines D 1  and D 1 #, word line WL 1 , the V CC  voltage supply source, match line MATCH 1 , and low match line LM 1  as described below. Low match line LM 1  is a controllable line that allows transmission of logic low values (e.g., the V SS  voltage supply source) as well as signals (e.g., a voltage of ½ the V CC  voltage supply source). Mask memory cell  901 B may be any type of memory storage cell including SRAM cells described herein. Control circuit  912  controls the coupling of a terminal of transistors  906  and  907  to match line MATCH 1 . Several embodiments of control circuit  912  are shown in FIGS. 9B-9C. 
     FIG. 9B is a first embodiment  930  of control circuit  912  (FIG.  9 A). Control circuit  930  includes diode  921  and n-channel transistor  922 . Diode  921  operates in a conventional manner to limit the current flow through control circuit  930 . One embodiment of diode  921  is shown in greater detail in FIG.  9 E. 
     FIG. 9C is a second embodiment  931  of control circuit  912  (FIG.  9 A). Control circuit  931  includes diode  924  and n-channel transistor  923 . Diode  924  operates similarly to diode  921  (FIG.  9 B). 
     FIG. 9D is a third embodiment  932  of control circuit  912  (FIG.  9 A). Control circuit  932  includes n-channel transistors  925  and  926 . Diode  924  operates similarly to diode  921  (FIG. 9B) to limit the current flow through control circuit  932 . 
     Returning to FIG. 9A, the total number of transistors in CAM cell  901  includes the eight transistors shown including those of SRAM cell  301 A plus the number of transistors in the chosen embodiment of control circuit  912  plus the number of transistors in the chosen embodiment of memory mask  901 B. 
     SRAM cell  301 A is coupled between the V CC  voltage supply source and the low match line LM 1 . Access transistor  310  is coupled between bit line B 1 # and node N 1 #. Access transistor  318  is coupled between bit line B 1  and node N 1 . The gates of access transistors  310  and  318  are coupled to word line WL 1 . Access transistor  906  is coupled between a first terminal of control circuit  912  and node N 1 #. Access transistor  907  is coupled between a first terminal of control circuit  912  and node N 1 . The gates of access transistors  906  and  907  are coupled to data line D 1 # and D 1 , respectively. Control circuit  912  has a second terminal coupled to match line MATCH 1  and a third terminal coupled to mask memory cell  901 B. 
     As described above, mask memory cell  901 B stores one of a logic high and a logic low value. One stored logic value (e.g., a logic high value) will close control circuit  912  to form a connection between terminals of transistors  906  and  907  and match line MATCH 1 . Another stored logic value (e.g., a logic low value) will open control circuit  912 , thereby de-coupling terminals of transistors  906  and  907  from match line MATCH 1 . Note that other embodiments of control circuit  912  may cause a connection to be formed when mask memory cell  901 B stores a logic low value and open a circuit when mask memory cell  901 B stores a logic high value. The descriptions below with respect to CAM cell  901  describe operations reading from and writing to SRAM cell  301 A with this understanding. 
     A no-match condition in CAM cell  901  occurs when match line MATCH 1  is pulled down to a logic low value as described below. 
     The operation of CAM cell  901  will now be described. CAM cell  901  operations include standby, write, read, and compare operations. In a standby operation, word line WL 1  and data lines D 1 # and D 1  are pulled down to logic low values, thereby turning off transistors  310  and  318 ,  906 , and  907 , respectively. The value of match line MATCH 1  and bit lines B 1  and B 1 # do not matter and are therefore held to their previous states. Low match line LM 1  is held to a logic low value. Under these conditions, SRAM cell  301 A latches the values at node N 1  and the inverted value at node N 1 #. 
     SRAM cell  301 A holds a single bit. Thus, one of a logic high value and a logic low value may be written to SRAM cell  301 A. To write a data value (e.g., a logic high value) to SRAM cell  301 A, bit lines B 1  is held to a first data value (e.g., a logic high value) and B 1 # is held to a second data value (e.g., a logic low value). Data lines D 1  and D 1 # are held to logic low values, thereby turning of transistors  907  and  906 , respectively. Turned off transistors  906  and  907  de-couple SRAM cell  301 A from a first terminal of control circuit  912 . Thus, the value stored in mask memory cell  901 B does not affect the write operation. Word line WL 1  is pulled up to a logic high value to perform the write operation. 
     To write a logic high value to SRAM cell  301 A, bit line B 1  is held to a logic high value (i.e., a first write data value) and bit line B 1 # is held to a logic low value (i.e., a second write data value). Under these conditions, the logic high value of word line WL 1  turns on transistors  310  and  318 . Turned on transistor  310  couples the logic low value of bit line B 1 # to node N 1 #, thereby pulling up node N 1  to a logic high value through turned on transistor  343 . Note that turned on transistor  318  also pulls up node N 1  to a logic high value. As a result, SRAM cell  301 A stores a logic high value. 
     To write a logic low value to SRAM cell  301 A, bit line B 1  is held to a logic low value (i.e., a first write data value) and bit line B 1 # is held to a logic high value (i.e., a second write data value). Under these conditions, the logic high value of word line WL 1  turns on transistors  310  and  318 . As a result, turned on transistor  318  couples the logic low value of bit line B 1  to node N 1 , thereby pulling up node N 1 # to a logic high value through turned on transistor  342 . Note that turned on transistor  310  also pulls up node N 1 # to a logic high value. As a result, SRAM cell  301 A stores a logic low value. 
     A read operation from CAM cell  901  will now be described. As described above, because SRAM cell  301 A holds a single bit, one of a logic high value and a logic low value may be read from SRAM cell  301 A. To read a data value from SRAM cell  301 A, bit lines B 1  and B 1 # are pre-charged to logic high values. Data lines D 1  and D 1 # are held to logic low values. The value of match line MATCH 1  does not matter and is therefore left in it&#39;s last state. Word line WL 1  is pulled up to logic a high value to perform the read operation. 
     During a read operation from CAM cell  901 , the logic high value of word line WL 1  turns on transistors  318 , thereby coupling the pre-charged logic high value of bit line B 1  to node N 1 . As a result, a logic low value stored at node N 1  pulls down bit line B 1  to a logic low value and a logic high value stored at node N 1  causes bit line B 1  to remain at a logic high value. Similarly, the logic high value of word line WL 1  turns on transistors  310 , thereby coupling the pre-charged logic high value of bit line B 1 # to node N 1 #. As a result, a logic low value stored at node N 1 # pulls down bit line B 1 # to a logic low value and a logic high value stored at node N 1 # causes bit line B 1 # to remain at a logic high value. 
     A compare operation from CAM cell  901  will now be described. Match line MATCH 1  is pre-charged to a logic high value. Word line WL 1  is held to a logic low value, thereby turning off transistors  310  and  318 . Low match line LM 1  is held to a logic low value. The value of bit lines B 1  and B 1 # do not matter and are therefore left in their previous states. A compare data value is applied to data lines D 1  and D 1 # to perform the compare operation. 
     To compare a logic high compare data value to CAM cell  901 , data line D 1  is held to a logic high value and data line D 1 # is held to a logic low value. Under these conditions, the logic low value of data line D 1 # turns off transistor  906 , thereby de-coupling the first terminal of control circuit  912  from node N 1 #. The logic high value of data line D 1  turns on transistor  907 , thereby coupling the first terminal of control circuit  912  to node N 1 . If mask memory cell  901 B masks the compare function (e.g., by storing a logic low value), node N 1  is de-coupled from the logic high value of match line MATCH 1  via open control circuit  912 . Thus, turned open control circuit  912  prevents a change in the value of match line MATCH 1  due to the value stored in CAM cell  901 . In this way, CAM cell  901  is masked from the compare operation. As a result, whether SRAM cell  301 A stores a logic high value or a logic low value, CAM cell  901  effectively stores a logic “don&#39;t care” value. 
     If mask memory cell  901 B does not mask the compare function, node N 1  is coupled to the logic high value of match line MATCH 1  via closed control circuit  912 . As a result, CAM cell  901  participates in the compare operation. If CAM cell  901  stores a matching logic high value (SRAM cell  301 A node N 1  stores a logic high value), then node N 1  is de-coupled from the logic low value of low match line LM 1  due to turned off transistor  327 . As a result, match line MATCH 1  remains in a logic high state, thereby indicating a match condition. If CAM cell  901  stores a non-matching logic low value (SRAM cell  301 A node N 1  stores a logic low value), then node N 1  is coupled to low match line LM 1  through turned on transistor  327 . As a result, match line MATCH 1  is pulled down to the logic low value of low match line LM 1  through turned on transistors  327 ,  907 , and closed circuit  912 , thereby indicating a no-match condition. 
     To compare a logic low compare data value to CAM cell  901 , data line D 1  is held to a logic low value and data line D 1 # is held to a logic high value. Under these conditions, the logic low value of data line D 1  turns off transistor  907 , thereby de-coupling the first terminal of control circuit  912  from node N 1 . The logic high value of data line D 1 # turns on transistor  906 , thereby coupling the first terminal of control circuit  912  to node N 1 #. As described above, if mask memory cell  901 B stores a masking logic value, then CAM cell  901  is masked from the compare operation. However, if mask memory cell  901 B stores a non-masking value, then CAM cell  901  participates in the compare operation. If CAM cell  901  stores a matching logic low value (SRAM cell  301 A node N 1  stores a logic low value), then node N 1 # is de-coupled from low match line LM 1  due to turned off transistor  326 . As a result, match line MATCH 1  remains in a logic high state, thereby indicating a match condition. If CAM cell  901  stores a non-matching logic high value (SRAM cell  301 A node N 1  stores a logic high value), then node N 1 # is coupled to low match line LM 1  through turned on transistor  326 . As a result, match line MATCH 1  is pulled down to the logic low value of low match line LM 1  through turned on transistors  326 ,  906 , and closed control circuit  912 , thereby indicating a no-match condition. 
     To compare a logic “don&#39;t care” compare data value to CAM cell  901 , data lines D 1  and D 1 # are held to logic low values. Under these conditions, the logic low values of data lines D 1  and D 1 # turn off transistors  907  and  906 , respectively, thereby de-coupling the first terminal of control circuit  912  (and in turn match line MATCH 1 ) from nodes N 1  and N 1 #. Thus, the logic value stored in SRAM cell  301 A does not affect the value of match line MATCH 1  during the compare operation. As a result, match line MATCH 1  remains at a logic high value, thereby indicating a match condition for all values stored in CAM cell  901 . 
     Operations similar to those described above may be performed on a row of CAM cells similar to CAM cell  901  by applying the techniques described above to the other CAM cells in the row. A comparison operation in CAM cell  901  results in a logic high value of the match line MATCH 1  if the applied comparison data value matches the data value stored in CAM cell  901 , and results in a logic low value of the match line MATCH 1  if the applied comparison data value does not match the data value stored in CAM cell  901 . In this way, the benefits of having a CAM cell, which results in a logic high value of the match line for a match condition and results in a logic low value of the match line for a no-match condition are achieved. 
     FIG. 9B is a schematic diagram of an embodiment of control circuit  912  (FIG. 9A) in accordance with the present invention. Control circuit  930  (an embodiment of control circuit  912 ) includes diode  921  and n-channel transistor  922 . Transistor  922  has a gate coupled to mask memory cell  901 B, a first terminal coupled to match line MATCH 1 , and a second terminal coupled to an input terminal of diode  921 . Diode  921  has an output terminal coupled to a terminal of transistor  907 . Control circuit  912  operates to open a path for current to flow from match line MATCH 1  to a terminal of transistor  907  when mask memory cell  901 B stores a logic high value and close that path when mask memory cell  901 B stores a logic low value. 
     FIG. 9C is a schematic diagram of another embodiment of control circuit  912  (FIG. 9A) in accordance with the present invention. Control circuit  931  (an embodiment of control circuit  912 ) includes diode  924  and n-channel transistor  923 . Control circuit  931  operates similarly to control circuit  930 . 
     FIG. 9D is a schematic diagram of another embodiment of control circuit  912  in accordance with the present invention. Control circuit  932  (an embodiment of control circuit  912 ) includes n-channel transistors  925  and  926 . Transistor  926  has a gate coupled to mask memory cell  901 B, a first terminal coupled to match line MATCH 1 , and a second terminal coupled to a first terminal for transistor  925 . Transistor  925  has a gate coupled to match line MATCH 1  and a second terminal coupled to a terminal of transistor  907 . Control circuit  932  operates similarly to control circuit  930 . 
     FIG. 9E is a schematic diagram of a diode in accordance with an embodiment diodes  921  (FIG. 9B) and  924  (FIG. 9C) of the present invention. Diode  921  includes an n-channel transistor  927  having a gate coupled to a first terminal of transistor  927 . The first terminal for transistor  927  is thus the input terminal of the diode and the second terminal of transistor  927  is the output terminal. Diode  921  turns off when the voltage at the input terminal falls below the threshold of transistor  927 . 
     Seventh Embodiment: 10-T Four-state CAM Cell Plus Mask 
     FIG. 10 is a schematic diagram of four-state CAM cell  1001  in accordance with another embodiment of the present invention. Similar elements in CAM cells  1001  and  901  (FIG. 9) are labeled similarly. CAM cell  1001  includes SRAM cell  301 A, mask memory cell  901 B, control circuit  912 , and n-channel transistors  907  and  1013 . CAM cell  1001  is coupled to bit line B 1 , data lines D 1  and D 1 #, word line WL 1 , the V CC  voltage supply source, match line MATCH 1 , and low match line LM 1  as described below. Low match line LM 1  is a controllable line that allows transmission of logic low values (e.g., a grounding voltage) as well as signals (e.g., a voltage of ½ the V CC  voltage supply source). Mask memory cell  901 B may be any type of memory storage cell including SRAM memory cells described herein. Control circuit  912  controls the coupling of a terminal of transistors  310 ,  907  and  1013  to match line MATCH 1 . 
     The total number of transistors in CAM cell  1001  includes the sum of the eight transistors shown including those from SRAM cell  301 A plus the number of transistors in the chosen embodiment of control circuit  912  plus the number of transistors in the chosen embodiment of memory mask  901 B. 
     SRAM cell  301 A is coupled between the V CC  voltage supply source and the low match line LM 1 . Access transistor  318  is coupled between bit line B 1  and node N 1 . The gate of access transistor  318  is coupled to word line WL 1 . Access transistor  310  is coupled between a first terminal of control circuit  912  and node N 1 #. Access transistor  907  is coupled between a first terminal of control circuit  912  and node N 1 . The gates of access transistors  1013  and  907  are coupled to data line D 1 # and D 1 , respectively. Transistor  1013  is coupled between a first terminal of control circuit  912  and the V SS  voltage supply source. Transistor  1013  has a gate coupled to word line WL 1 . Control circuit  912  has a second terminal coupled to match line MATCH 1  and a third terminal coupled to mask memory cell  901 B. CAM cell  1001  operates similarly to CAM cells  901  (FIG. 9A) and  801  (FIG.  8 ), and will therefore not be described in detail. 
     Although the invention has been described in connection with the present embodiments, it is understood that this invention is not limited to the embodiment disclosed, but is capable of various modifications which would be apparent to a person skilled in the art. For example, transistors having gates coupled to the same word line may instead be coupled to separate word lines. Similarly, a low match line may be controlled to a non-grounding voltage for beneficial purposes such as reducing power consumption of the CAM cell. Thus, the invention is limited only by the following claims.