Abstract:
Phase-locked loop (PLL) integrated circuits according to embodiments of the invention provide dual feedback control. The first feedback control utilizes a conventional phase locking scheme that passes a feedback clock signal to an input of a phase-frequency detector (PFD). The second feedback control utilizes an automatic frequency calibrator that evaluates a frequency of an output of a voltage-controlled oscillator (VCO) relative to a locked frequency detected during calibration and provides separate calibration control to a charge pump.

Description:
REFERENCE TO PRIORITY APPLICATION 
     This application claims priority to Korean Patent Application No. 10-2008-0098160, filed Oct. 7, 2008, the contents of which are hereby incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present invention relates to integrated circuit devices and, more particularly, to phase-locked loop integrated circuits. 
     BACKGROUND 
     Mismatch in a charge pump corresponds to mismatch between up and down currents and occurs due to a difference between transconductances Gm of a PMOS transistor and an NMOS transistor constructing the charge pump according to PVT (Process-Voltage-Temperature), and mismatch occurring when bias voltages of the transistors are generated. 
     When mismatch occurs in a charge pump included in a PLL, changes in control voltage of a voltage controlled oscillator (VCO) can cause reference spur and jitter. 
     SUMMARY 
     Phase-locked loop (PLL) integrated circuits according to embodiments of the invention provide dual feedback control. The first feedback control utilizes a conventional phase locking scheme that passes a feedback clock signal to an input of a phase-frequency detector (PFD). The second feedback control utilizes an automatic frequency calibrator that evaluates a frequency of an output of a voltage-controlled oscillator (VCO) relative to a locked frequency detected during calibration and provides separate calibration control to a charge pump. 
     According to some of these embodiments of the invention, the PLL integrated circuit includes a charge pump, which is responsive to up and down control signals and first and second bias signals, and a charge pump calibration circuit. This charge pump calibration circuit includes a current mirror configured to generate the first bias signal and a current source circuit, which is electrically connected to the current mirror and is responsive to a multi-bit calibration signal and the second bias signal. In some embodiments of the invention, the current source circuit includes a plurality of parallel current sources responsive to respective ones of the multi-bit calibration signal. For example, the current mirror may include a PMOS transistor and each of the plurality of parallel current sources may include a respective pair of NMOS transistors. Alternatively, the current mirror may include an NMOS transistor and each of the plurality of parallel current sources may include a respective pair of PMOS transistors. 
     A voltage-controlled oscillator (VCO) and a frequency calibrator are also provided. The VCO is configured to generate an output signal in response to a control signal generated by the charge pump. The frequency calibrator, which is responsive to the output signal, is configured to change a value of the multi-bit calibration signal in response to detecting changes in a frequency of the output signal. In particular, the frequency calibrator may be automated to adjust the value of the multi-bit calibration signal in response to detecting differences in a frequency of the output signal during normal operation relative to a frequency of the output signal during calibration. 
     According to still further embodiments of the invention, the PLL may include a phase-frequency detector (PFD) configured to generate the up and down control signals in response to a reference clock signal (REF_CLK) and a feedback clock signal (FB_CLK). To facilitate calibration of the PLL, a selector (e.g., multiplexer) is provided. This selector is configured to pass the reference clock signal as the feedback clock signal in response to a calibration mode signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a conventional charge pump used for a phase locked loop (PLL); 
         FIG. 2  is a graph for explaining current mismatch of a charge pump; 
         FIG. 3  is a block diagram of a PLL including a charge pump mismatch calibrating apparatus according to an embodiment of the inventive concept; 
         FIG. 4  is a graph illustrating a variation in a voltage Vctrl according to time when a reference clock signal is input to both input terminals of a phase frequency detector in a charge pump calibration mode; 
         FIG. 5A  is a circuit diagram of a charge pump mismatch calibrating apparatus according to an embodiment of the inventive concept; 
         FIG. 5B  is a dual circuit diagram of the circuit illustrated in  FIG. 5A ; and 
         FIG. 6  is a graph illustrating a voltage V_match varying according to calibration of current I_UP in a charge pump calibration mode. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Like reference numerals in the drawings denote like elements, and thus their description will be omitted. 
       FIG. 1  is a circuit diagram of a typical charge pump employed in a phase locked loop (PLL). 
     Referring to  FIG. 1 , mismatch between a current I_UP flowing through an upper PMOS transistor MP and a current I_DN flowing through a lower NMOS transistor MN occurs according to a difference between transconductances Gm of the transistors MP and MN due to PVT (Process-Voltage-Temperature) and mismatch occurring when bias voltages Vbias_p and Vbias_n of the transistors MP and MN are generated. The currents I_UP and I_DN vary with a voltage Vctrl according to output resistances of the transistors MP and MN, as illustrated in  FIG. 2 . A voltage V_lock that locks the PLL is determined by characteristic of a voltage controlled oscillator VCO, and thus a voltage V_match at which the voltage V_lock and the currents I_UP and I_DN are matched has no relation to the voltage V_lock, as illustrated in  FIG. 2 . Accordingly, mismatch may occur if a target frequency varies or the characteristic of the VCO varies to change the voltage V_lock even though the currents I_UP and I_DN become identical according to a PVT variation. 
       FIG. 3  is a block diagram of a PLL including a charge pump mismatch calibrating apparatus according to an embodiment of the inventive concept. 
     Referring to  FIG. 3 , the PLL includes a selector  31 , a phase frequency detector (PFD)  32 , a charge pump  33 , a voltage controlled oscillator (VCO)  34 , an automatic frequency calibrator (AFC)  35  and a frequency divider (DIV)  36 . 
     The selector  31  selectively outputs a reference clock signal. REF_CLK input from an external device or a signal input from the frequency divider  36  according to a charge pump calibration mode signal CP_CAL Mode. In the charge pump calibration mode, the reference clock signal REF_CLK is output when the charge pump is calibrated, and the signal input from the frequency divider  36  is output when a PLL operation is performed after calibration. 
     The PFD  32  detects a phase difference between the reference clock signal REF_CLK and the output signal of the selector  31 , FB_CLK, and outputs an UP signal and a DN signal. Here, if the charge pump is to be calibrated, the reference clock signal REF_CLK is input to the PFD  32  and the PFD  32  operates in the same manner as when the PLL is locked. An upper PMOS transistor and the lower NMOS transistor illustrated in  FIG. 5  are respectively turned on according to the UPb signal and the DN signal input from the charge pump  33 , and thus the currents I_UP and I_DN respectively flow through the upper PMOS transistor and the lower NMOS transistor. The output voltage of the charge pump  33 , Vctrl, reaches a voltage V_match at which the currents I_UP and I_DN become identical to each other. When the voltage V_match becomes identical to the voltage V_lock, mismatch between the PFD  32  and the charge pump  33  is eliminated while the PLL is locked. 
     However, the mismatch between the PFD  32  and the charge pump  33  is not eliminated in practice due to a difference in a process and is delivered to the VCO  34 . The output signal of the VCO  34  is transmitted to the AFC  35  in order to compare the voltage V_lock to the voltage V_match. In AFC  35 , the output frequency of the VCO  34  is compared with an output frequency when the PLL is locked. The frequency comparison is performed in such a manner that the number of clock pulses output from the VCO  34  for a predetermined period of time is counted and then the counted number is compared to a predetermined value, that is, the number of clock pulses corresponding to the output frequency when the PLL is locked. 
     If the output frequency of the VCO  34  is higher than the output frequency when the PLL is locked, it means that the voltage V_match is higher than the voltage V_lock. Accordingly, the current I_UP of the charge pump  33  is reduced to decrease the voltage V_match to be matched to the charge pump  33 . If the output frequency of the VCO  34  is lower than the output frequency when the PLL is locked, it means that the voltage V_match is lower than the voltage V_lock. Accordingly the current I_UP of the charge pump  33  is increased to enhance the voltage V_match. 
       FIG. 5A  is a circuit diagram of a charge pump calibrated to match the currents I_UP and I_DN according to an embodiment of the inventive concept. 
     Referring to  FIG. 5A , a calibration circuit  51  is connected to a bias input of the charge pump circuit  50  as illustrated in  FIG. 1 . The calibration circuit  51  includes a current mirror  511  and an NMOS switch bank. The NMOS switch bank includes NMOS switches  512  turned on/off according to a calibration signal output from the AFC  35  illustrated in  FIG. 3  and an NMOS current source  513  driven by a bias voltage Vbias. The bias voltage Vbias is input as a voltage Vbias_n to the charge pump circuit  50  and the output of a PMOS diode  511  is input as a voltage Vbias_p to the charge pump circuit  50 . 
     A dual embodiment of the circuit of  FIG. 5A  may be also considered. The dual embodiment circuit is illustrated in  FIG. 5B . 
     Referring to  FIG. 5B , a calibration circuit  54  is connected to a bias input of the charge pump circuit  53 . The calibration circuit  54  includes a current mirror  541  and a PMOS switch bank. The PMOS switch bank includes PMOS switches  542  turned on/off according to a calibration signal output from the AFC  35  illustrated in  FIG. 3  and a PMOS current source  543  driven by a bias voltage Vbias. The bias voltage Vbias is input as a voltage Vbias_p to the charge pump circuit  53  and the output of an NMOS diode  541  is input as a voltage Vbias_n to the charge pump circuit  53 . 
     The AFC  35  can digitally calibrate the charge pump  33  if the charge pump illustrated in  FIG. 5  is employed as the charge pump  33 .  FIG. 6  is a graph illustrating the voltage V_match varying according to calibration of the current I_UP in the charge pump calibration mode. The AFC  35  controls the calibration signal until the voltage V_match reaches the voltage V_lock to calibrate the current I_UP. 
     Calibration of the charge pump  33  is completed as described above, the selector  31  outputs the signal FB_CLK to the PFD  32  to operate the PLL. Here, the frequency divider  36  divides the frequency of the signal output from the VCO  34  in a predetermined ratio and outputs the divided frequency as the signal FB_CLK. 
     While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.