Abstract:
Individual pixel reset circuits for an array of electromagnetic radiation sensors include a reset transistor connected to enable a reset of the pixel&#39;s sensor, and a logic gate connected to activate the reset transistor in response to a plurality of array reset signals. The logic gate can be implemented with only three transistors, and enables the selection of individual pixels for reset.

Description:
BACKGROUND OF THE INVENTION 1. Field of the Invention  
         [0001]    This invention relates to digital imaging devices, and more particularly to the resetting of individual pixels in an imaging sensor with minimal disruption to surrounding pixels.  
           [0002]    2. Description of the Related Art  
           [0003]    Imaging sensors are used in many applications such as digital cameras and camcorders, high definition television (HDTV) and telescopes. Two types of commonly used image sensors for these applications are charge coupled device (CCD) and complementary metal oxide semiconductor (CMOS). Each type of sensor includes a (typically) two-dimensional array of pixel circuits. Each pixel circuit includes an electromagnetic radiation detector which converts photons (electromagnetic radiation) into a charge which accumulates at the detector, and an output circuit. Each detector has a maximum charge that it will hold. Once this maximum charge is reached, the detector saturates and will not accumulate any additional charge.  
           [0004]    Each pixel in a CMOS sensor senses one small area within the larger image, with its circuit outputting a signal representing that portion of the image. The pixel circuits may need to be reset from time to time, such as when a new image is to be obtained or when a bright star in an image has saturated the circuit.  
           [0005]    Most imaging sensors reset one row of pixels at a time. With this method, only one transistor per pixel is needed to implement a reset. However, it is not applicable to situations in which it is desired to reset a portion of the array other than an entire row.  
           [0006]    A conventional pixel with a row reset circuit is illustrated in FIG. 1. The pixel includes a photosensor  12  that accumulates charge in response to received radiation and a row reset transistor  14  that, when activated by a sufficient voltage on row reset control line  16 , applies a reset voltage on reset voltage line  18  to sensor  12  to reset its voltage level. A voltage source  19  supplies line  18 , providing sufficient current to reduce the voltage on the sensor to the voltage level of line  18 . The reset voltage is typically a low voltage, such as 0-500 millivolts for a p-n type sensor. Sensor  12  may be a photodiode, phototransistor, or other type of photosensitive device.  
           [0007]    A read transistor  20  and source follower transistor  22  have their source-drain circuits connected in series between a read bus  24  and the source-drain circuit of reset transistor  14 . Source follower transistor  22  has its gate connected to output node  26  of sensor  12 . The voltage at node  28 , between read transistors  20  and  22 , tracks the voltage at sensor node  26  through the normal source follower action of transistor  22 . To read out a signal from the pixel, a voltage is applied to a read enable line  30  sufficient to activate read transistor  20 , which then applies the sensor output voltage at node  28  to the read bus  24  through its activated source-drain circuit.  
           [0008]    All of the pixels in the sensor include similar reset circuits. Each row of pixels has an associated row reset control line  16  which connects the gates of the row reset transistors in each pixel of the row. Each column of pixels has an associated reset voltage line  18  that, for each pixel in the column, connects to the side of the reset transistor  14  source-drain circuit opposite to detector node  26 . With this configuration, only entire rows can be reset at a time.  
           [0009]    Available imaging sensors which are configured to reset individual pixels employ a pair of reset transistors connected in series for each pixel, one for “row reset” and the other for “column reset,” as described in U.S. Pat. No. 5,881,184 to Guidash. Both transistors are activated to produce a reset. A negative aspect of the individual pixel reset capability is that it allows a parasitic capacitance to build up between the substrate and the node between the reset transistors when one of the transistors is activated but not the other. The voltage at this node is transmitted to the sensor and adds to the normal sensor output voltage, resulting in an erroneous output.  
           [0010]    Such an individual pixel reset circuit is illustrated in FIG. 2. It adds a column reset control line  42  and column reset transistor  44  to a row reset circuit of FIG. 1, with the gate of transistor  44  connected to column reset control line  42  and its source-drain circuit connected between the source-drain circuit of row reset transistor  14  and the sensor output node  26 . The remainder of the circuit is the same as in FIG. 1. With this configuration both reset transistors  14  and  44  must be turned on, by activating both the row reset line  16  and column reset control line  42 , to apply the reset voltage on line  18  to sensor  12 . This circuit can also introduce an undesirable parasitic capacitance between node  46 , between the reset transistors  14  and  44 , and the substrate. When row reset control line  16  is activated but column reset control line  42  is not, row reset transistor  14  turns on, setting the voltage at node  46  to the level of reset voltage line  18 . Some charge remains at node  46 , due to the parasitic capacitance, even after row reset control line  16  and row reset transistor  14  have been deactivated. Then, when column reset control line  42  and column reset transistor  44  are activated, the voltage at node  46  passes to sensor output node  26  and adds to the normal sensor output voltage, resulting in an erroneous output that can affect all pixels in the row and/or column of the reset pixel.  
         SUMMARY OF THE INVENTION  
         [0011]    The present invention overcomes the problems noted above. It provides an individual pixel reset circuit with a reset transistor that resets the sensor when it is activated, and a logic gate that is connected to activate the reset transistor in response to a plurality of reset signals.  
           [0012]    In one embodiment, a reset transistor is connected between a reset voltage line and the sensor, with a logic gate that has three transistors and three logic inputs activating the reset transistor when it is desired to reset the sensor, and otherwise disconnecting the reset voltage line from the sensor. The logic gate activates the reset transistor in response to a combination of three reset signals.  
           [0013]    One implementation of the logic gate includes a pair of opposite polarity CMOS transistors connected as a parallel switch between the first logic input and a control for the reset transistor, and a reset inhibit switch which has a control terminal connected in common with the gate of one of the CMOS transistors. The reset inhibit switch switches in an opposite manner to the one CMOS transistor in response to a signal at its control terminal to set the logic gate output to a reset inhibit voltage that deactivates the reset transistor when the CMOS transistors are off.  
           [0014]    Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    [0015]FIGS. 1 and 2 are schematic diagrams of prior pixel reset circuits;  
         [0016]    [0016]FIG. 3 is a schematic diagram of an individual pixel reset circuit according to one embodiment of the invention;  
         [0017]    [0017]FIG. 4 is a schematic diagram of a logic gate that can be used in the pixel reset circuit; and  
         [0018]    [0018]FIG. 5 is a schematic diagram of a digital imaging system which uses the individual reset capability of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    A pixel with an individual pixel reset circuit according to one embodiment of the invention is shown in FIG. 3. The pixel includes an electromagnetic radiation sensor  12 , reset transistor  14 , row reset control line  16 , reset voltage line  18 , reset voltage source  19 , read transistor  20 , source follower transistor  22 , read bus  24 , read enable line  30 , and column reset control line  42  as in the prior circuit of FIG. 2. A keep-alive current source  43  maintains NMOS source follower transistor  22  in an active state. The direction of current flow would be reversed if a PMOS source follower were used.  
         [0020]    The invention is most commonly applicable to photosensitive detectors which are sensitive to visible light, infrared and/or ultraviolet, but it is also applicable to other regions of the electromagnetic spectrum. In contract to FIG. 2, a feature of the FIG. 3 circuit is that instead of the gate of reset transistor  14  being directly controlled by row reset line  16 , a logic gate  44  has been added with its output connected to the gate of reset transistor  14 . Logic gate  44  receives logic inputs from the row and column reset control lines  16  and  42 . When both reset lines are activated, logic gate  44  activates reset transistor  14 . This allows the voltage on sensor output node  26  to be set to the reset voltage on reset voltage line  18 , as described above. With this configuration, no unwanted charge is introduced to the sensor and a more accurate voltage is read from sensor node  26 . The voltage from electromagnetic radiation sensor  12  is read out in the same manner as described in connection with FIG. 1.  
         [0021]    Logic gate  44  is preferably an AND gate, but other types of logic gates could be used that turn on reset transistor  14  in response to the activation of row reset control line  16  and column reset control line  42 . The row and column reset control lines are typically “activated” by applying positive voltages to them, but activation could also occur in response to zero, negative, or opposite polarity voltages on the reset control lines, depending upon the nature of logic gate  44 . For example, if a NOR gate is employed, reset transistor  14  would be activated in response to an absence of voltage on both reset lines. The type of logic gate used and the nature of the signals applied to the reset control lines also depend upon the nature of reset transistor  14 . For example, if an nFET device is used instead of a pFET, logic gate  44  would need to provide an opposite polarity signal in response to the same inputs from the reset control lines to activate reset transistor  14 .  
         [0022]    [0022]FIG. 4 is a schematic diagram of one embodiment of logic gate  44  that uses only three transistors. This logic gate retains a single row reset control line  16 , but instead of a single column reset control line  42  it employs complementary column reset control lines  42   a  and  42   b . Complementary voltages are applied to lines  42   a  and  42   b  so that one line is active when the other is not. A pair of CMOS transistors  46  and  48  are connected as a parallel switch between row reset control line  16  and a reset node  50  that is connected to the gate of reset transistor  14 . A reset inhibit transistor  52  of opposite doping type to transistor  46  has its gate connected to the gate of transistor  46 , and its source-drain circuit connected between a reset inhibit voltage source  54 , via line  55 , and reset node  50 . When column reset control line  42   a  is on and line  42   b  is off, the complementary transistors  46  and  48  are both turned on to pass any reset signal on row reset control line  16  to the reset node  50 . If row reset control line  16  is activated at this time, reset transistor  14  is activated and a reset occurs. If row reset control line  16  is not activated, the voltage at reset node  50  will be too low to turn on reset transistor  14 .  
         [0023]    Both complementary transistors  46  and  48  are used to assure that the voltage at reset node  50  is held at the full voltage on reset control line  16 . The CMOS transistors  46  and  48  typically have threshold voltages of 0.5-0.7 V, with nMOS transistor  46  turning on when its gate voltage exceeds its source voltage by the threshold amount, and pMOS transistor  48  turning on when its voltage exceeds its gate voltage by the threshold amount. Thus, as long as the difference between the complementary voltages on column reset control lines  42   a  and  42   b  is maintained at at least 1.4 volts when a reset is desired, it is assured that at least one of the transistors will conduct when row reset control line  16  is activated.  
         [0024]    Transistors  46 ,  48  and  52  are shown as n-type, p-type and n-type respectively, but this could be reversed, with a corresponding reversal of signal polarities on column reset control lines  42   a  and  42   b . Other types of switches, controlled by row and column reset control lines to transmit a reset signal to the pixel circuitry, could also be used, with the switch preferably transmitting the full voltage on row reset control line  16  to the gate of reset transistor  14 .  
         [0025]    Reset inhibit voltage source  54 , when connected to reset node  50  through reset inhibit transistor  52 , ensures that the voltage at reset node  50  is not floating when the complementary switch  46 / 48  is off, and is held below the voltage needed to activate reset transistor  14  so that the sensor is not inadvertently reset. Although reset inhibit voltage source  54  is shown as ground, it can provide any voltage level, such as 0-1 volt, that deactivates and holds reset transistor  14  off.  
         [0026]    Current CMOS logic gates have at least four transistors. The three-transistor logic gate described herein reduces the number of components included in each pixel and thus the size of each pixel, enabling a higher resolution image sensor with a higher pixel density. The saving of at least one transistor per pixel is significant, since conventional image sensors can be very large, with multimillions of pixels.  
         [0027]    The use of complementary control lines reduces circuit noise during individual pixel reset, since the noise associated with each line substantially cancels the noise associated with the other. A buildup of parasitic charge that can be added to the sensor during individual pixel reset is avoided with the addition of only two transistors compared to the prior circuit of FIG. 2.  
         [0028]    [0028]FIG. 5 illustrates a simplified imaging system with an array  56  of pixels  58  employing the reset scheme of FIG. 4. Pixels  58  are shown spaced widely apart for ease of illustrating the various signal lines, but in practice they would be much closer together. With conventional large pixel arrays, smaller pixel size and thus better resolution is enabled by the invention.  
         [0029]    The imaging system includes column reset circuitry  60  and row reset circuitry  62  that activate desired sets of column reset control lines  42   a  and  42   b  and row reset control line  16 , respectively, under the control of the user. Column reset control lines  42   b  are topped off of corresponding column reset control lines  42   a , with a respective inverter  64  inserted into each line  42   b  to set each pair of column reset control lines  42   a ,  42   b  at complementary logic levels. Individual pixels are reset by activating their respective row and column reset control lines. Individual keep-alive current sources  43  could be provided for each pixel, but preferably a common keep-alive current source is provided for a full column or group of columns.  
         [0030]    The system also includes row select circuitry  66  which activates the corresponding read enable line  30  to enable the read transistors  20  of the pixels in a selected row when the voltage from a desired pixel in the row is to be read out. Read bus circuitry  68  allows the sensor voltages from selected pixels in a selected row to be read out.  
         [0031]    While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. For example, while an imaging array has been described in terms of rows and columns of pixels with specific row and column inputs and outputs, the row inputs and outputs could be exchanged with those for the columns, or other array geometries such as concentric circular or staggered pixels could be used. Also, while an FET has been shown in the reset inhibit circuit, other switches such as bipolar transistor could be used. A bipolar transistor substituted for reset inhibit transistor  52  would have its base control terminal connected to the gate of CMOS transistor  46 , and be doped to switch opposite to CMOS transistors  46  and  48  so that the bipolar transistor was on when the CMOS transistors were off, and vice versa. Npn and pnp bipolar transistors could also be substituted for the CMOS transistors. Accordingly, it is intended that the invention be limited only in terms of the appended claims.