Abstract:
A multiphase controller for a PWM power converter employs a single current sense device to measure input current, I, and an integrator at each phase to accurately measure power delivered during a pulse. The integrator monitors current delivered through a circuit which delivers a current signal scaled to I/N where N is the number of active phases. Thus where there are three overlapping phases, one-third of I is delivered to the integrator for each phase that is on or active. The integrator provides a Charge Ramp signal to an input of a Pulse Width Modulation (PWM) comparator associated with each phase. The other input of the PWM comparator is tied to an error control signal common to all of the phases. When the Charge Ramp signal and the error control signal match, the corresponding phase is turned off for the duration of the cycle.

Description:
FIELD OF THE INVENTION 
     The present invention is directed to a high-speed charge-mode controller for use with a switched-mode power converter. 
     BACKGROUND OF THE INVENTION 
     Power converters are used in modem electronic equipment to convert relatively poorly regulated direct current (DC) power supply voltages to highly regulated DC power supply voltages. Such devices are used, for example, to power microprocessors and similar devices. Current technology microprocessors can require 1.5 volts or less of supply voltage at peak levels exceeding 80 amperes (A). Because such devices are often switched at rates exceeding 1.5 GHz, they routinely experience current slew rates of 400 A/microsecond (μSec) or more. As a result, it has become necessary in recent years to provide such devices with power from a multi-phase voltage regulator. The multi-phase voltage regulator typically obtains its power from a single relatively poorly regulated power supply and provides a number of sources (phases) of highly regulated voltage for use by the device. 
     In the past, peak input current mode (PICM) control has been used to control some multi-phase controllers, such as the Semtech SC-2422, SC-2425, SC-2424, SC-2433 and SC-2434 models available from Semtech Corporation of Newbury Park, California. In such PICM systems, current sensing is realized on the input positive rail of the power converter by using a low value (e.g., 0.002-0.005 Ohm) current sensing resistor. The PICM-type approach generally works well and has the advantages that: (1) phase currents are automatically balanced; (2) active voltage positioning is easily implemented with very good precision; (3) the wide control bandwidth settles the output to its correct position very quickly; and (4) module current sharing can be implemented. 
     Although PICM has these merits, it also has some shortcomings. These are: (1) the leading edge spike of the MOSFET (metal oxide semiconductor field effect transistor) current needs to be filtered out; (2) parasitics in the layout tend to interact with the sensing filter to cause ringing and limit operational frequencies to about 500 KHz per phase at 5 volts input and 250 KHz per phase at 12 volts input; (3) in order to avoid overlapping of the current pulses coming from different phases (a requirement of this approach) multiple sensing resistors and current amplifiers are required. This last shortcoming adds to system cost and IC (integrated circuit) pin count. The maximum duty cycle of the PWM (pulse with modulation) pulses is also limited depending on the configuration to less than 50% for a two-phase controller, less than 33% for a three-phase controller, etc. This limits the applications in which such a controller may be used. 
     Accordingly, it would be desirable to provide a high-speed controller which could operate on multiple phases with no duty cycle overlap limitation and no requirement for multiple current sensing devices. 
     BRIEF DESCRIPTION OF THE INVENTION 
     A multiphase controller for a PWM power converter employs a single current sense device to measure input current, I, and an integrator at each phase to accurately measure power delivered during a pulse. The integrator monitors current delivered through a circuit which delivers a current signal scaled to I/N where N is the number of active phases. Thus where there are three overlapping phases, one-third of I is delivered to the integrator for each phase that is on or active. The integrator provides a Charge Ramp signal to an input of a Pulse Width Modulation (PWM) comparator associated with each phase. The other input of the PWM comparator is tied to an error control signal common to all of the phases. When the Charge Ramp signal and the error control signal match, the corresponding phase is turned off for the duration of the cycle. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present invention and, together with the detailed description, serve to explain the principles and implementations of the invention. 
     In the drawings: 
     FIG. 1 is an electrical schematic diagram of a typical application circuit employing a high-speed charge-mode, multi-phase power converter in accordance with an embodiment of the present invention. 
     FIG. 2 is a simulation circuit illustrating the operation of an IICM (integrated input current mode) power converter circuit. This circuit is implemented as a 250 KHz three-phase five-volt input 1.6±80 mv output 45A buck-type voltage converter. 
     FIG. 3 is an electrical schematic diagram of the charge mode controller in accordance with one embodiment of the present invention. 
     FIG. 4 is an electrical schematic diagram of one instantiation of the charge storing generation block of the charge mode controller of FIG.  3 . 
     FIG. 5A is a plot of current vs. time for the instantaneous current in the top MOSFET of one phase of a PWM power converter in accordance with the embodiment of FIG.  2 . 
     FIG. 5B is a plot of current vs. time for the current in the sensing resistor R 12  of FIG.  2 . 
     FIG. 5C is a plot of voltage vs. time for the voltage across the current sensing input pins IS+, IS− of FIG.  2 . 
     FIG. 5D is a plot of voltage vs. time for the filtered voltage of the Charge Ramp signal used in accordance with the embodiment of FIG. 2 as filtered by C 9  and R 15 . 
     FIG. 6A is a plot of current vs. time for the current passing through MOSFETs MPL 2 ( 82 ), MPL 3 ( 84 ) and MPL 4 ( 86 ) of FIG. 4 for one phase in a no-phase-overlap case. Note that the current through MPL 3  and MPL 4  is always zero in this case. 
     FIG. 6B is a plot of voltage vs. time for the voltages  88 ,  90 ,  92 ,across the drain to source of the low side MOSFETs (or “phase nodes”)  138 ,  140 ,  142  of the three phases  88 ,  90 ,  92 . 
     FIG. 7A is a plot of current vs. time for the current passing through MOSFETs MPL 2 ( 94 ), MPL 3 ( 96 ) and MPL 4 ( 98 ) of FIG. 4 for a two-phase-overlap case. Note that the current through MPL 4  is always zero in this case. 
     FIG. 7B is a plot of voltage vs. time for the voltage across the phase nodes  138 ,  140 ,  142  of the three phases  100 ,  102   104 . 
     FIG. 8A is a plot of current vs. time for the current passing through MOSFETs MPL 2 ( 106 ), MPL 3 ( 108 ) and MPL 4 ( 110 ) of FIG. 4 in a three-phase overlap case. 
     FIG. 8B is a plot of voltage vs. time for the voltage across the phase nodes  138 ,  140 ,  142  of the three phases  112 ,  114  and  116  and also illustrating the Charge Ramp signal for phase  1  ( 118 ). 
     FIG. 9A is a plot of voltage vs. time for the three Charge Ramp signals  120 ,  122 ,  124  which are the outputs of the integrators. 
     FIG. 9B is a plot of current vs. time for the current flow through the input sensing resistor R 12 . 
     FIG. 9C is a plot of current vs. time for the output inductor currents taken at nodes  126 ,  128  and  130  of FIG.  2 . The corresponding traces are  132 ,  134  and  136 . 
     FIG. 9D is a plot of voltage vs. time for the three phase nodes  138 ,  140 ,  142  of FIG.  2 . 
     FIG. 9E is a plot of voltage vs. time for the overall voltage output of the power converter. Note that the converter transitions from no load at 80 μS-100 μS to full load at 100 μS-200 μS and back to no load at 200 μS-220 μS. 
     FIG. 10A is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9A surrounding application of a maximum load at T=100 μS. 
     FIG. 10B is a plot of current vs. time showing 20 μS of the plot on FIG. 9B surrounding application of a maximum load at T=100 μ. 
     FIG. 10C is a plot of current vs. time showing 20 μS of the plot of FIG. 9C surrounding application of a maximum load at T=100 μS. 
     FIG. 10D is a plot of voltage vs. time showing 20 v of the plot of FIG. 9D surrounding application of a maximum load at T=100 μS. 
     FIG. 10E is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9E surrounding application of a maximum load at T=100 μS. 
     FIG. 11A is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9A surrounding release of the maximum load at T=200 μS. 
     FIG. 11B is a plot of current vs. time showing 20 μS of the plot of FIG. 9B surrounding release of the maximum load at T=200 μS. 
     FIG. 11C is a lot of current vs. time showing 20 μS of the plot of FIG. 9C surrounding release of the maximum load at T=200 μS. 
     FIG. 11D is a plot of voltage vs. time showing 20 μS of the plot of FI 9 D surrounding release of the maximum load at T=200 μS. 
     FIG. 11E is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9E surrounding release of the maximum load at T=200 μS. 
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention are described herein in the context of a high-speed charge-mode controller for a multi-phase switched mode power converter. Those of ordinary skill in the art will realize that the following detailed description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts. 
     In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer&#39;s specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure. 
     Turning now to the figures, FIG. 1 is an electrical schematic diagram of a typical application circuit  10  employing a high-speed charge mode controller  12  for a multi-phase switched mode power converter. The example circuit  10  includes a number of inputs  14 , a current sense resistor R 19  ( 16 ), driver circuits H 51 , H 52 , H 53  and H 54  for the four phases shown, and pulse width modulation (PWM) MOSFET pairs  18 ,  20 ,  22  and  24  corresponding to each driver circuit. Example circuit  10  also includes conventional filter circuitry  26  and provides a highly regulated output voltage at pin  28 . 
     FIG. 2 is a simulation circuit  50  illustrating the operation of an IICM (integrated input current mode) power converter circuit in accordance with one embodiment of the present invention. This circuit is implemented as a 250 KHz three-phase five-volt input 1.6±80 mV output 45A buck-type voltage converter. Total input current is sensed at R 12  ( 52 ) and delivered to controller  54  via pins designated IS+ and IS−. In one embodiment, R 12  has a resistance in a range of about 0.002 ohms to about 0.005 ohms. Alternatively a current transformer or other known approach may be used to sense current. Controller  54  may be a single integrated circuit but is not required to be. Controller  54  may provide output pins for each desired phase or may have extra unused output pins. Voltage reference is provided by a highly precise conventional band gap source. 
     FIG. 3 is an electrical schematic diagram of the charge mode controller  54  of FIG. 2 is accordance with one embodiment of the present invention. This diagram is also shown as a simulation circuit. A conventional band gap reference plus error amplifier circuit  56  provides an error voltage signal which is used to turn off the various phases when they have achieved a desired phase during a particular cycle of operation. Charge steering circuits  58   a ,  58   b  and  58   c  each have inputs P 1 , P 2  and P 3  which correspond to the turn-on logic signal of phases  1 ,  2  and  3 , respectively. They. also receive Vdd (the input voltage signal), I_sense (a signal proportional to the sensed current) and produce a Charge Ramp signal. This charge ramp signal is applied at each phase to a comparator ( 60   a ,  60   b ,  60   c ) with the error signal and the comparator turns off the phase when the error signal and the Charge Ramp signal are equal. Flip flops U 1 , U 2  and U 2  (or equivalent circuitry well known to those of ordinary skill in the art) hold the OUT 1 , OUT 2  and OUT 3  signals high until cleared by comparators  60   a ,  60   b  and  60   c , respectively. Clock signals V_CLK 1 , V_CLK 2  and V_CLK 3  turn on flip flops U 1 , U 2  and U 3  at the beginning of each respective cycle in a conventional manner. 
     FIG. 4 is an electrical schematic diagram (also in simulation form) of one instantiation of the charge steering generation block for phase P 1  of the charge-mode controller of FIG.  3 . (Note that each of the other phases has a similar, though not identical, block, i.e., substitute P 1  for P 2 , P 2  for P 3 , P 3  for P 1  for the P 2  block, etc.) This circuit includes four main blocks. 
     The first block is a current level decoder  62  which takes logic inputs P 1 , P 2  and P 3 , any of which may be “on” or “off” and provides outputs G 11 , G 12  and G 13  where G 11  is asserted if only one of the three phases P 1 , P 2  and P 3  is “on”, G 12  is asserted if two of the three phases are “on”, G 13  is asserted if all three phases are “on”, and none of G 11 , G 12  and G 13  are asserted if all three phases are “off”. The logic circuit of decoder  62  is one example of how to perform this function. Many other ways of performing this function are available and more or fewer phases may be implemented as will now be apparent to those of ordinary skill in the art. 
     The second block is a current mirror block  64  which generates a current I at node  66  which is proportional to I_sense; The same current I is generated at node  68 . A current I/2 is generated at node  70  and a current I/3 is generated at node  72 . Those of ordinary skill in the art will now realize that there are other techniques for generating these currents and this invention is not intended to be limited to any particular such technique. 
     The third block is a current selector block  74 . Current selector block receives I from node  68 , I/2 from node  70  and I/3 from node  72 . It gates each of these current sources with the signals G 11 , G 12  and G 13 , respectively, from current level decoder block  62 . Thus, when one phase is in use, G 11  is asserted and turns on MOSFET MPL 2  allowing current I to pass to node  76 , when two phases are in use, G 12  is asserted and turns on MOSFET MPL 3  allowing I/2 to pass to node  76 . Likewise, if all three phases are in use, G 13  is asserted, MOSFET MPL 4  is turned on and I/3 passes to node  76 . In this way, the current passed to node  76  at any moment is scaled with the number of phases in use at that moment. 
     The fourth block is a Charge Ramp block  78  which provides a charge ramp signal representing an integration via capacitor C 2  of the charge received at node  76 . When P 1  is deasserted by comparator  60 a (FIG. 4) switch MNL 1  is turned on to discharge C 2  until the next cycle. The accumulated voltage on C 2  appears at output “Ramp”. 
     To complete the converter, an appropriate filter as well known to those of ordinary skill in the art should also be included as shown, for example, in FIG.  2 . 
     FIGS. 5A-11E illustrate operational characteristics of a power converter built in accordance with the principles shown herein. 
     FIG. 5A is a plot of current vs. time for the instantaneous current in the top MOSFET of one phase of a PWM power converter in accordance with the embodiment of FIG.  2 . Note that a leading edge spike  80  is typically present due to MOSFET switching transients. This needs to be filtered out in PICM-type voltage regulators to avoid erroneous operation. In the present approach there is no requirement that it be filtered out. 
     FIG. 5B is a plot of current vs. time for the current in the sensing resistor R 12  of FIG.  2 . Due to circuit parasitics, a switching frequency noise is superimposed on the high-side MOSFET current signal which provides a very distorted signal for PICM-type voltage regulation. The present invention avoids this problem. 
     FIG. 5C is a plot of voltage vs. time for the voltage across the current sensing input pins IS+, IS− of FIG.  2 . By applying only common RC filtering, the leading edge spike and the switching noise cannot be effectively removed. This poses a problem for PICM-type operation but not IICM-type operation. 
     FIG. 5D is a plot of voltage vs. time for the voltage of the Charge Ramp signal used in accordance with the embodiment of FIG. 2 as filtered by C 9  and R 15 . This Charge Ramp signal is based on charge integration and greatly reduces the noise caused by the leading edge spike and switching. The Charge Ramp signal can therefore be used as a good quality PWM carrier signal. As a result, one can operate the PWM converter at a much higher switching frequency than before, e.g., in excess of 500 KHz. 
     FIG. 6A is a plot of current vs. time for the current passing through MOSFETs MPL 2 ( 82 ), MPL 3 ( 84 ) and MPL 4 ( 86 ) of FIG. 4 for one phase in a no-phase-overlap case. Note that the current through MPL 3  and MPL 4  is always zero in this case. 
     FIG. 6B is a plot of voltage vs. time for the voltages  88 ,  90 ,  92  across the phase nodes  138 ,  140  and  142  of FIG. 2 for the case of FIG.  6 A. 
     FIG. 7A is a plot of current vs. time for the current passing through MOSFETs MPL 2 ( 94 ), MPL 3 ( 96 ) and MPL 4 ( 98 ) of FIG. 4 for a two-phase-overlap case. Note current through MPL 4  is always zero in this case. 
     FIG. 7B is a plot of voltage vs. time for the voltage across the phase nodes  138 ,  140  and  142  of FIG. 2 for the case of FIG.  7 A. 
     FIG. 8A is a plot of current vs. time for the current passing through MOSFETs MPL 29 ( 106 ), MPL 3 ( 108 ) and MPL 4 (  10 ) of FIG. 4 in a three-phase overlap case. 
     FIG. 8B is a plot of voltage vs. time for the voltage across the phase nodes  138 ,  140  and  142  of FIG. 2 for the case of FIG.  8 A. 
     FIG. 9A is a plot of voltage vs. time for the Charge Ramp signals which are outputs of the integrators. 
     FIG. 9B is a plot of current vs. time for the current through sensing resistor R 12 . 
     FIG. 9C is a plot of current vs. time for the output inductor currents taken at nodes  126 ,  128  and  130  of FIG.  2 . The corresponding traces are  132 ,  134  and  136 . 
     FIG. 9D is a plot of voltage vs. time for the phase nodes  138 ,  140  and  142  of FIG.  2 . 
     FIG. 9E is a plot of voltage vs. time for the overall voltage output of the power converter. Note that the converter transitions from no load at 80 μS-100 μS to full load at 100 μS-200 μS and-back to no load at 200 μS-220 μS. 
     FIG. 10A is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9A surrounding application of a maximum load at T=100 μS. 
     FIG. 10B is a plot of current vs. time showing 20 μS of the plot on FIG. 9B surrounding application of a maximum load at T=100 μS. 
     FIG. 10C is a plot of current vs. time showing 20 μS of the plot of FIG. 9C surrounding application of a maximum load at T=100 μS. 
     FIG. 10D is a plot of voltage vs. time showing 20 v of the plot of FIG. 9D surrounding application of a maximum load at T=100 μS. 
     FIG. 10E is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9E surrounding application of a maximum load at T=100 μS. 
     FIG. 11A is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9A surrounding release of the maximum load at T=200 μS. 
     FIG. 11B is a plot of current vs. time showing 20 μS of the plot of FIG. 9B surrounding release of the maximum load at T=200 μS. 
     FIG. 11C is a lot of current vs. time showing 20 μS of the plot of FIG. 9C surrounding release of the maximum load at T=200 μS. 
     FIG. 11D is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9D surrounding release of the maximum load at T=200 μS. 
     FIG. 11E is a plot of voltage vs. time showing 20 μS of the plot of FIG. 9E surrounding release of the maximum load at T=200 μS. 
     The present invention is not limited to use in buck converter circuits and will find use in many types of power converter circuits. While the present invention is primarily intended for use in multi-phase converters, it will operate in a single phase environment, a two-phase environment, etc., as desired by the circuit designer. 
     While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.