Abstract:
A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.

Description:
BACKGROUND 
       [0001]    1. Field 
         [0002]    This disclosure relates generally to forming semiconductor devices, and more specifically, to forming a lifetime monitor. 
         [0003]    2. Related Art 
         [0004]    Excessive voltage and/or extreme temperature conditions, which may be defined as overstress, cause semiconductor devices to fail earlier than expected. This is especially problematic in high performance devices where the semiconductor devices are exposed to excessive voltages, where “overclock” occurs when the voltage stated in the specification is purposely surpassed. This problem also arises in automotive applications where the semiconductor devices are exposed to very high temperatures due to their proximity to the engine. It is difficult to detect these undesirable conditions. 
         [0005]    Prior art solutions for detecting excessive voltage and extreme temperature conditions are provided at the transistor level. The prior art utilizes clock edge counting or voltage comparators. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. 
           [0007]      FIG. 1  illustrates a block diagram of a semiconductor device having a lifetime monitor in accordance with an embodiment of the present invention; 
           [0008]      FIG. 2  illustrates the lifetime monitor of  FIG. 1  in accordance with an embodiment of the present invention; and 
           [0009]      FIG. 3  illustrates a schematic for the detect and disconnect circuit of  FIG. 2  in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    In one embodiment, an overstress detection structure, which may include copper, is used to calculate the lifetime of the semiconductor device based on excessive voltage, extreme temperature conditions, other factors that affect dielectric property changes, or combinations of the above. If a product is returned to the semiconductor supplier, this structure can be used to easily determine if the product was subjected to overstress. In one embodiment, a plurality of conductive lines exists with varying spaces (and possibly varying lengths) between each of them and a conductive perpendicular line. The spaces between the lines consist of a dielectric material. As the property of the dielectric changes in a predictable manner due to voltage and temperature applied to the circuit, the change may result in overstress detection. The dielectric property change separating each line can determine to what voltage or temperature the semiconductor was exposed. In addition, other embodiments may be used to measure the dielectric property changes. In one embodiment, a cutoff detection circuit may be used to detect the dielectric change and disconnect either the power or ground connection in real time to avoid detecting further overstress. Thus, unlike the prior art, a measurement of stress to a circuit is possible. 
         [0011]      FIG. 1  illustrates a semiconductor device  10 , which in the embodiment illustrated in a system on a chip (SOC). The SOC  10  is formed on or within a substrate. The SOC  10  may include a central processing unit (CPU)  12  for controlling the SOC  10  coupled to a bus  20  (which transports data), a fusebox  14  (which includes factory settings), and a lifetime monitor  16  (which monitors the overstress). The bus  20  is coupled to a Universal Asynchronous Receiver/Transmitter (UART)  22 , which may translate data between parallel and serial forms; a Universal Serial Bus (USB)  24 , which is a connector between a device and a host controller; a JTAG  26 , which is a port used to debug the semiconductor device; Double Data Rate (DDR)  28 , which is hardware used to transfer data; a video processing unit (VPU)  18  for manipulating computer graphics, and/or any other blocks, hardware, or modules. 
         [0012]      FIG. 2  illustrates the lifetime monitor  16  of  FIG. 1  in accordance with one embodiment. In the embodiment illustrated, the lifetime monitor  16  includes conductors  35 - 40 . A barrier layer  42  surrounds the first conductor  35 , which is coupled to ground. In one embodiment, the first conductor  35  is copper and the barrier layer  42  is a material that will prevent the diffusion of copper, such as tantalum nitride or silicon nitride. The first conductor  35  may be another suitable material, such as aluminum, gold, or silver and the barrier layer  42  may be another material that prevents the diffusion of the elements in the dielectric material  45 . Each of the second to six conductors  36  to  40  are partially surrounded by a barrier layer  44 . The same materials for the first conductor  35  and barrier layer  42  may be used for the second to six conductors  36  to  40  and the barrier layers  44 , respectively. The barrier layers  42  and  44  may all be the same or different materials. Similarly, the conductors  35 - 40  may all be the same or different materials. A surface of the second to sixth conductors  36  to  40  that is closest to the first conductors  35  does not include the barrier layer  44 , so that an element from the second to sixth conductors  36  to  40  (a diffusing species) will diffuse from the second to sixth conductors  36  to  40 , which usefulness will be further explained below, from the exposed areas  46  of the second to sixth conductors  36 - 40 . 
         [0013]    The diffusing species will diffuse in the dielectric  45  towards the negative potential, which in the embodiment illustrated is ground. (Thus, in the embodiment illustrated in  FIG. 2  if VDD and ground are switched, then the diffusing species will travel from the first conductor  35  to the second to sixth conductors  36  to  40 . In this embodiment, all sides of the second to sixth conductors  36  to  40  will be surrounded by the barrier layer  44  and portions of the first conductor  35  that are across from the second to sixth conductors  36  to  40  will be devoid of the barrier layer  42  to enable the diffusion of the diffusing species (e.g., Cu).) The diffusing species would then be an impurity in the dielectric  45  in the region between the two conductors. The presence of the diffusing species in the dielectric  45  will alter the electrical properties of the lifetime monitor  16 . 
         [0014]    For example, the capacitance or resistance between two of the conductors may be altered. In this case, the amount of overstress as opposed to whether an overstress occurred may be determined. The capacitance measured may be compared to a predetermined capacitance to determine, for example, what voltage was applied. While this may be achieved using only two conductors, it is probably better achieved using more than two conductors. If the predetermined distances  50 - 54  are different, then a different voltage may be applied to each of the conductor(s)  36 - 40  and in one embodiment, the conductor that has the voltage applied to it that is the same as the overstress voltage will short to the first conductor  35 . This allows for determination of the voltage that is used for the overstress voltage. 
         [0015]    The first to sixth conductors  35  to  40  are surrounded by a dielectric material  45 . The dielectric material may be any suitable material, such as silicon dioxide or a high dielectric constant (hi-k) material, such as SiLK. The first to sixth conductors  35  to  40  and the dielectric  45  are surrounded by an isolation structure  32 . In one embodiment, the isolation structure  32  is a layer including copper with a barrier layer, such as tantalum nitride or silicon nitride. Other materials, such as silicon nitride, can be used for the isolation structure  32 . 
         [0016]    The conductors  36  to  40  are coupled to monitor circuitry  61 , where in the embodiment illustrated, each of the conductors  36  to  40  are coupled to a detect and disconnect circuit  60  that in turn is coupled to Vdd and register  62 . The detect and disconnect circuit  60  supplies Vdd to the conductor and determines when an electrical property of the dielectric  45  is changed or meets a predetermined value. 
         [0017]    Although six conductors are illustrated in  FIG. 2 , the lifetime monitor  16  may include any number of conductors greater than or equal to two. With two conductors an electrical property of the dielectric  45  may be monitored using, for example, monitor circuitry  61 , to determine if there has been an overstress of the semiconductor device. One of the conductors (e.g., first conductor  35 ) is coupled to ground and the other conductor(s) is/are coupled to VDD and monitor circuitry  61 . For example, if an overstress occurs by operating the semiconductor device at a voltage of 1.2V, for example, when the semiconductor device is designed to operate at 1V, when VDD is 1.2V, the conductor(s)  36 - 40  that are coupled to VDD will have a diffusing species diffuse through the dielectric  45  from the conductor(s)  36 - 40  to the first conductor  35 . If the conductors  35 - 40  include copper, the diffusing species may be copper. 
         [0018]    In one embodiment,  FIG. 2  is a top-down view of the lifetime monitor  16  so that elements  42 ,  35 - 40 , and  44  are all formed in the same level of a semiconductor device, such as at the metal  1 ,  2 , etc. layer in the semiconductor device. Transistors and interconnects may be formed directly under or on layers under or within the same layer as the lifetime monitor  16 . Passivation and/or additional interconnect layers may be formed inlayers above or even directly above the lifetime monitor  16 . 
         [0019]    In another embodiment,  FIG. 2  is a cross-sectional view and for example, element  35  is formed in one interconnect layer and elements  36 - 40  are formed in one or more interconnect layer that is different than the interconnect layer that element  35  is formed within. For example, the sixth conductor  40  may be a via formed in a first interconnect layer; the fifth conductor  39  may be a via formed in the second or first and second interconnect layer; the fourth conductor  38  may be a via formed in the third layer or a combination of the first, second, and/or third layer; the third conductor  37  may be a via formed in the fourth layer or a combination of the first, second, third and/or fourth layer; and the second conductor  36  may be a via formed in the fifth layer or a combination of the first, second, third, fourth and/or fifth layer. The first conductor  35  may be formed in an interconnect layer that is above the highest interconnect layer that includes at least a portion of the second conductor  36 . 
         [0020]      FIG. 3  illustrates a schematic for the detect and disconnect circuit of  FIG. 2  in accordance with an embodiment of the present invention. A resistor  74  is coupled to VDD and a current electrode, such as the drain electrode, of transistor  72 . The other current electrode, which may be a source electrode, of transistor  72  is coupled to the conductor  36 . The control or gate electrode of the transistor  72  is coupled to and controlled by the stress signal from the AND gate  70 , which is coupled to the detectbar signal (the complement of detect) for feedback in case of detection. The detectbar signal is taken from the drain electrode of transistor  72 . 
         [0021]    In the embodiment illustrated, when one of the predetermined distances  50 - 52  closes so that there is no longer a gap between the conductor  36 , for example, and the conductor  35 , the transistor  72  will be turned off so that the conductor  36  is no longer coupled to VDD. (The disappearance of the gap is due to the diffusion of the diffused species into this gap area.) When the circuit is turned on and no electrical signal is detected, detectbar is high and voltage is applied to the conductor  36 . When the detectbar node is pulled low due to the dielectric change, the signal is sent to the register  62  and stored and the circuit is disconnected by turning off the transistor  72  to prevent VDD from being further applied to the conductor  36 . 
         [0022]    Additional conductors can be used to better determine at least two conductors. In the embodiment illustrated, a first conductor  35  is perpendicular to the second to sixth conductors  36 - 40  and the conductors  35 - 40  are rectangular in shape. The second to sixth conductors  36 - 40  are a predetermined distance  50 - 54 , respectively, from the first conductor  35 . As illustrated, the predetermined distances  50 - 54  are different distances. However, the predetermined distances  50 - 54  may be the same distance. Whether the distances  50 - 54  are the same or are different may be chosen based on what electrical property is monitored, as will be better understood after further discussion. 
         [0023]    Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed. 
         [0024]    The terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements 
         [0025]    Some of the above embodiments, as applicable, may be implemented using a variety of different information processing systems. For example, although  FIG. 2  and the discussion thereof describe an exemplary lifetime monitor, this lifetime monitor is presented merely to provide a useful reference in discussing various aspects of the invention. Of course, the description of the architecture has been simplified for purposes of discussion, and it is just one of many different types of appropriate architectures that may be used in accordance with the invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality. Also for example, in one embodiment, the illustrated elements of the semiconductor device  10  are circuitry located on a single integrated circuit or within a same device. Alternatively, semiconductor device  10  may include any number of separate integrated circuits or separate devices interconnected with each other. Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. 
         [0026]    Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.