Abstract:
A digital input/output circuit to be connected between an internal data bus composed of 2 n  signal lines (n is zero or a positive integer) and 2 n  external terminals includes an output port for outputting data from the internal data bus to the external terminals and an input port for inputting the data from the external terminal to the internal data bus. The output port comprises a scrambler receiving data of 2 n  bits from the internal data bus and a mode signal and operating for relocating the received data in accordance with the mode signal so as to output the relocated data with each unit of 2 m  bits (m is an integer not greater than n) indicated by the mode signal. An output circuit includes 2 n  output buffers each having an input connected to receive directly or indirectly an output of the scrambler and an output connected to a corresponding one of the external terminals. This output circuit operates in response to the mode signal so as to make active 2 m  output buffers of the 2 n  output buffers in accordance with the mode signal and to make the other output buffers inactive. A data shifter is connected to the scrambler and includes data latch for latching data in accordance with the relocation pattern of the scrambler and shifting the latched data in accordance with the mode signal so that the data of 2 n  bits is outputted with each unit of 2 m  bits through the active buffers.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital data input/output circuit, and more specifically to an input/output circuit for use in an input/output port of a memory and capable of sending and receiving a digital data in different formats. 
     2. Description of Related Art 
     So-called digital data input/output circuits have been used in various fields of data processings. On the other hand, the format of data processed or transferred is different in apparatuses or systems being used. For example, a serial data is handled in one field, and 4-bit parallel data is transferred in another field. Further, 2-bit parallel-serial data transmission is performed in still another field. Therefore, the input/output circuit is desired to comply with different formats or modes of data. However, conventional input/output circuits cannot handle two or more different formats or modes of data, and in addition, the input/output circuits have been complicated although the circuits can handle two different formats or modes of data. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide an input/output circuit which has overcome the above mentioned defect of the conventional one. 
     Another object of the present invention is to provide a digital input/output circuit capable of freely processing the data in various modes or formats. 
     The above and other objects of the present invention are achieved in accordance with the present invention by a digital input/output circuit to be connected between an internal data bus composed of 2 n  lines (n is zero or a positive integer) and 2 n  external terminals and including an output port for outputting data from the internal data bus to the external terminals and an input port for inputting the data from the external terminal to the internal data bus. 
     The output port comprises: 
     a scrambler means receiving data of 2 n  bits from the internal data bus and a mode signal and operating for relocating the received data in accordance with the mode signal so as to output the relocated data with each unit of 2 m  bits (m is an integer not greater than n) indicated by the mode signal, 
     output circuit means including 2 n  output buffers each having an input connected to receive directly or indirectly an output of the scrambler means and an output connected to a corresponding one of the external terminals, the output circuit means operating in response to the mode signal so as to make active 2 m  output buffers of the 2 n  output buffers in accordance with the mode signal and to make the other output buffers inactive, and 
     data shift means connected to the scrambler and including data latch means for latching data in accordance with the relocation pattern of the scrambler means and shifting the latched data in accordance with the mode signal so that the data of 2 n  bits is outputted with each unit of 2 m  bits through the active output buffers. 
     On the other hand, the input port includes: 
     input circuit means having 2 n  input buffers connected at their inputs to the external terminals, respectively, 
     data shift means including data latch means for directly or indirectly receiving the data outputted from the input circuit so as to latch the data of least 2 m  bits in accordance with the mode signal, the data shift means operating to shift the latched data between the data latch means in accordance with the mode signal, and 
     scrambler means connected to the data shift means so as to allow a data of 2 n  bits relocated in accordance with the mode signal to be outputted to the internal data bus. 
     The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of one typical conventional digital input/output circuit of four bits; FIG. 2 is a timing chart of a serial clock SCK and four interleaving clock φ 1 , φ 2 , φ 3 , and φ 4  derived from the serial clock SCK for driving the transfer gate transistors used in the circuit shown in FIG. 1; 
     FIG. 3 is a block diagram illustrating an output port of a four-bit type digital input/output circuit embodying the present invention. 
     FIG. 4 is a block diagram illustrating an input port of a four-bit type digital input/output circuit embodying the present invention; 
     FIG. 5 is a circuit diagram of one embodiment of the output port in accordance with the present invention, which can be used as the output port shown in FIG. 3; 
     FIGS. 6A to 6C and 7A and 7D illustrate the relation between the data on the internal signal lines and the data on the external terminals of the output port shown in FIG. 5 in different operation modes; 
     FIG. 8 is a circuit diagram of one embodiment of the input port in accordance with the present invention, which can be used as the input port shown in FIG. 3; 
     FIGS. 9A to 9C and 10A and 10D illustrate the relation between the data on the internal signal lines and the data on the external terminals of the input port shown in FIG. 8 in different operation modes; 
     FIG. 11 is a circuit diagram of another embodiment of the output port in accordance with the present invention, which can be used as the output port shown in FIG. 3; 
     FIGS. 12A to 12C and 13A and 13D illustrate the relation between the data on the internal signal lines and the data on the external terminals of the output port shown in FIG. 11 in different operation modes; 
     FIG. 14 is a circuit diagram of another embodiment of the input port in accordance with the present invention, which can be used as the input port shown in FIG. 3; and 
     FIGS. 15A to 15C and 16A and 16D illustrate the relation between the data on the internal signal lines and the data on the external terminals of the input port shown in FIG. 14 in different operation modes. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, there is shown a diagram of one typical conventional digital input/output circuit of four bits. The shown circuit is connected between four signal lines 10, 12, 14 and 16 and external terminals 20, 22, 24 and 26. The signal lines 10 to 16 form an internal data bus. The input/output circuit includes a field effect transistor (called &#34;FET&#34; hereinafter) Q 1  connected at its one end to the signal line 10 and having a gate connected to receive an interleaving clock φ 1 , and an input/output buffer 30 connected at its one end to the other end of the transistor Q 1  and at its other end to the terminal 20 through an input/output signal line 40. Accordingly, when the interleaving clock φ 1  is rendered active, the signal line 10 is coupled to the one end of the input/output buffer 30. The input/output circuit also includes an input/output buffer 32 connected at its one end to the signal line 12 and at its other end to the terminal 22 through an input/output signal line 42, and a FET Q 2  connected between the signal line 12 and a connection line between the FET Q 1  and the Input/output buffer 30 and having a gate connected to receive an interleaving clock φ 2 , so that, when the interleaving clock φ 2  is rendered active, the signal line 12 is coupled not only to the one end of the input/output buffer 32 but also to the one end of the input/output buffer 30. Furthermore, an input/output buffer 34 is connected at its one end to the signal line 14 and at its other end to the terminal 24 through an input/output signal line 44, and a FET Q 3  is connected between the signal line 14 and the connection line between the FET Q 1  and the Input/output buffer 30. The FET Q 3  has a gate connected to receive an interleaving clock φ 3 , so that, when the interleaving clock φ 3  is rendered active, the signal line 14 coupled to the one end of the input/output buffer 34 is also coupled to the one end of the input/output buffer 30. Similarly, an input/output buffer 36 is connected at its one end to the signal line 16 and at its other end to the terminal 26 through an input/output signal line 46, and a FET Q 4  is connected between the signal line 16 and the connection line between the FET Q 1  and the Input/output buffer 30. The FET Q.sub. 4 is also connected to receive at its gate an interleaving clock φ 4 , so that, when the interleaving clock φ 4  is rendered active, the signal line 16 coupled to the one end of the input/output buffer 36 is also coupled to the one end of the input/output buffer 30. 
     Now, an operation of the above mentioned input/output circuit will be explained with reference to FIG. 2. The four interleaving clock φ 1 , φ 2 , φ 3  and φ 4  are derived from a basic serial clock SCK as shown in FIG. 2 so that the four interleaving clock φ 1 , φ 2 , φ 3  and φ 4  will alternatively and sequentially made active. 
     Assume that four digital data D 1 , D 2 , D 3  and D 4  appear on the signal lines 10, 12, 14 and 16, and these data should be serially outputted from only the terminal 20. This data transmission manner will be called &#34;1-bit operation&#34;. In this operation, the input/output buffer 30 is maintained in an active condition and the other input/output buffers 32, 34 and 36 are put in an inactive condition so that the external terminals 22, 24 and 26 are maintained in a high impedance condition. In a first cycle of the serial clocks SCK, the interleaving clock φ 1  is applied to the FET Q 1  to turn on the FET Q 1 , and therefore, the data D 1  is inputted into the buffer 30 and then is outputted to the external terrminal 20. At this time, the FET Q 2 , Q 3  and Q 4  are in an off condition, and the data D 2 , D 3  and D 4  are supplied to the buffers 32, 34 and 36, respectively. However, since the buffers 32, 34 and 36 are inactive as mentioned above, the data D 2 , D 3  and D 4  are not outputted to the terminals 22, 24 and 26. 
     In a second cycle of the serial clocks SCK, the interleaving clock φ 2  is applied to the FET Q 2  to turn on the FET Q 2 , and on the other hand, the FET Q 1 , Q 3  and Q 4  are in an off condition. Therefore, the data D 2  is inputted into the buffer 30 and then is outputted to the external terminal 20. 
     In a third cycle, the interleaving clock φ 3  is applied to the FET Q 3  to turn on the FET Q 3 , so that the data D 3  is inputted into the buffer 30 and then is outputted to the external terminal 20, since the FET Q 1 , Q 2  and Q 4  are in an off condition. 
     In a fourth cycle, the interleaving clock φ 4  applied to the FET Q 4  to turn on the FET Q 4 , so that the data D 4  is inputted into the buffer 30 and then is outputted to the external terminal 20. 
     Thus, the data D 1 , D 2 , D 3  and D 4  supplied to the signal lines 10, 12, 14 and 16 in parallel are serially outputted bit by bit from the terminal 20 in synchronism with the serial clock SCK. 
     In addition, in a serial data receiving case that a serial data is supplied through the terminal 20 to the input/output buffer 30, the data is distributed to the signal line 10, 12, 14 and 16 in accordance with the four interleaving clock φ 1 , φ 2 , φ 3  and φ 4 , similarly to the above mentioned data sending case that the parallel data D 1 , D 2 , D 3  and D 4  are serially outputted to the terminal 20. 
     In a parallel data transmitting case, all the input/output buffers 30, 32, 34 and 36 are maintained in an active condition. At the same time, only the interleaving clock φ 1  is ceaselessly maintained in an active condition, and on the other hand, the other interleaving clock φ 2 , φ 3  and φ 4  maintained in an inactive condition so that the signal lines 12, 14 and 16 are maintained in a condition isolated from the buffer 30. Therefore, the signal lines 10, 12, 14 and 16 are ceaselessly coupled to the buffers 30, 32, 34 and 36 in a one-to-one relation, respectively. Accordingly, respective bits of parallel data are transferred to one-to-one relation between the signal lines 10, 12, 14 and 16 and the external terminals 20, 22, 24 and 26 through the input/output buffers 30, 32, 34 and 36. 
     As seen from the above, the above mentioned input/output circuit can assume only two data input/output port arrangements or formats, one of which enables all the bits to use all the external terminals and the other of which enables only one bit to use only one external terminal. In other words, the conventional input/output circuit is low in feasibility of input/output port arrangement or format. In addition, it is necessary to interleave a control signal for an external serial clock, and therefore, a complicated signal system is required. 
     Turning to FIGS. 3 and 4, there are respectively shown block diagrams illustrating an output port and an input port of a four-bit type digital input/output circuit embodying the present invention. 
     The output port shown in FIG. 3 includes a scrambler 100 having four inputs connected to the internal signal lines 10, 12, 14 and 16 which form an internal data bus. The scrambler 100 has four outputs connected to four inputs of a shift register 110, which has four outputs connected to four outputs of an output circuit 120. This output circuit 120 has four outputs connected through the signal lines 40, 42, 44 and 46 to the external terminals 20, 22, 24 and 26, respectively. The scrambler 100, the shift register 110 and the output circuit 120 are respectively connected to receive mode signals MOD4, MOD2 and MOD1 through a mode signal bus 130. The mode signal MOD4 requires a four-bit parallel transmission, and the mode signal MOD2 requires a two-bit parallel transmission. The mode signal MOD1 requires a one-bit serial transmission. 
     With the above mentioned arrangement, the scrambler 100 responds to the mode signal so as to relocate the input bits into a positional arrangement of bits indicated by the mode signal. The shift register 110 latches the signals of four bits outputted from the scrambler 100 and shifts the latched bits by the amount indicated by the mode signal. For example, when the mode signal MOD4 is supplied, the shift register 110 outputs the received bits to the output circuit 120 without shift if the scrambler 100 does not change the position of the bits. If the scrambler 100 changes the position of the bits, the shift register 110 cyclicly shifts the received bits by a necessary amount for permitting the same position of bits as the positional arrangement of bits on the input signal lines 10 to 16 to be outputted to the output circuit 120. When the mode signal MOD2 or MOD1 is applied, the shift register 110 cyclicly shifts the received bits in accordance with a required amount determined by the mode signal. 
     The output circuit 120 outputs the bits received form the shift register 110 to all or selected one or ones of the external terminals 20 to 26 designated by the mode signal MOD4, MOD2 or MOD1. 
     The input port shown in FIG. 4 has an input circuit 140 having four inputs connected through the signal lines 40 to 46 to the external terminals 20 to 26. This input circuit 140 also has four outputs connected to a shift register 150, which in turn has four outputs connected to a scrambler 160. Four outputs of this scrambler 160 are connected to the internal signal lines 10 to 16, respectively. Further, the shift register 150 and the scrambler 160 are respectively connected to receive mode signals MOD4, MOD2 and MOD1 through a mode signal bus 170 so that these circuits are controlled as follows: 
     When the mode signal MOD4 is applied, the shift register 150 operates to simultaneously latch all the bits outputted form the input circuit 140. When the mode signal MOD2 is inputted, the shift register 150 latches only two bits of the four bits outputted from the input circuit 140, two times sequentially at different moments. Further, when the mode signal MOD1 is applied, the shift register 150 latches only one bit of the four bits outputted from the input circuit 140, four times sequentially at different moments. The scrambler 160 relocates the bits outputted from the shift register 150 into an arrangement of bits in accordance with the received mode signal MOD4, MOD2 or MOD1 and outputs the relocated bits to the internal signal lines 10 to 16 in parallel. 
     Referring to FIG. 5, there is shown a circuit diagram of one embodiment of the output port in accordance with the present invention, which can be used as the output port shown in FIG. 3. 
     The scrambler 100 comprises one set of four connection lines L 10 , L 11 , L 12  and L 13  which are connected to the internal signal lines 10, 12, 14 and 16, respectively, and which are respectively connected to one ends of four transfer gate FETs Q 10 , Q 11 , Q 12  and Q 13 . These FETs have gates commonly connected to receive the mode signal MOD4 and coupled at their other ends to another set of four connection lines L 20 , L 21 , L 22  and L 23 , as shown in the drawing. Namely, the other ends of the FETs Q 10 , Q 11 , Q 12  and Q 13  are connected to the connection lines L 20 , L 22 , L 21  and L 23 , respectively. 
     The scrambler 100 includes another set of four transfer gate FETs Q 20 , Q 21 , Q 22  and Q 23  having their one ends connected to the connection lines L 10 , L 11 , L 12  and L 13 , respectively and their other ends connected to the connection lines L 23 , L 21 , L 20  and L 22 , respectively. Gates of these FETs Q 20 , Q 21 , Q 22  and Q 23  are commonly connected to receive the mode signal MOD2. Further, a third set of transfer gate FETs Q 30 , Q 31 , Q 32  and Q 33  are connected at their one ends to the connection lines L 10 , L 11 , L 12  and L 13 , respectively and at their other ends connected to the connection lines L 21 , L 22 , L 23  and L 20 , respectively. Gates of these FETs Q 30 , Q 31 , Q 32  and Q 33  are commonly connected to receive the mode signal MOD1. 
     The four connection lines L 20 , L 21 , L 22  and L 23  of the scrambler 100 are connected to four connection lines L 30 , L 31 , L 32  and L 33 , which are respectively connected to one ends of four transfer gate FETs Q 40 , Q 41 , Q 42  and Q 43  of the shift register 110. These FETs have gates commonly connected to receive a gate control signal LOD and coupled at their other ends through four connection lines L 40 , L 41 , L 42  and L 43  to inputs D of four D-type flipflops 111, 112, 113 and 114. All the flipflops 111, 112, 113 and 114 are connected to receive the same basic clock SCK at their clock inputs, so that each time the clock SCK is inputted, the data on the lines L 40 , L 41 , L 42  and L 43  are latched in the D-type flipflops 111, 112, 113 and 114, respectively. In addition, the flipflops 111, 112, 113 and 114 have their outputs Q connected through four transfer gate FETs Q.sub. 51, Q 52 , Q 53  and Q 50  to the four connection lines L 41 , L 42 , L 43  and L 40 , respectively. These FETs Q 50 , Q 51 , Q 52  and Q 53  are connected to receive a shift signal SFT at their gates so that when the shift signal SFT is active, if the clock SCK is rendered active, the data on the outputs Q of the D-type flipflops 111, 112, 113 and 114 are shifted to the input of the D-type flipflops 112, 113, 114 and 111. 
     The output circuit 120 includes four output buffers 121, 122, 123 and 124. The output buffer 121 is connected at its input to the output Q of the flipflop 111 and at its output to the external terminal 20. The output buffer 122 is connected at its input to the output Q of the flipflop 113 and at its output to the external terminal 22 and has a control inverted input connected to receive the mode signal MOD1 so that when the mode signal MOD1 is active, the buffer 122 is put in an inactive condition. Further, the output buffer 123 is connected at its input to the output Q of the flipflop 112 and at its output to the external terminal 24 and has a control inverted input connected to an output of an OR gate 125 which receives the mode signal MOD1 and the mode signal MOD2. In addition, the output buffer 124 is connected at its input to the output Q of the flipflop 114 and at its output to the external terminal 26 and has a control inverted input connected to an output of an OR gate 126 which receives the mode signal MOD1 and the mode signal MOD2. Therefore, if either the mode signal MOD1 or the mode signal MOD2 is active, the buffers 123 and 124 are put in an inactive condition, respectively. 
     Now, operation of the output port shown in FIG. 5 will be explained with reference to FIGS. 6A to 6B and 7A and 7D which illustrate the relation between the data on the internal signal lines 10 to 16 and the data on the external terminals 20 to 26 of the output port shown in FIG. 5 in different operation modes. 
     (1) Active mode signal MOD4 (FIG. 6A) 
     When the mode signal MOD4 is made active, the other mode signals MOD2 and MOD1 are inactive. Accordingly, the FETs Q 10 , Q 11 , Q 12  and Q 13  are turned on so that the respective data d 0 , d 1 , d 2  and d 3  on the internal signal lines 10, 12, 14 and 16 are transferred through the connection lines L 20 , L 22 , L 21  and L 23  to the connection lines L 30 , L 32 , L 31  and L 33 , as seen from FIG. 5. Namely, the data d 1  and d 2  are exchanged by the scrambler 100. Thus, the data d 0 , d 2 , d 1  and d 3  relocated in the named order are inputted form the connection lines L 30 , L 31 , L 32  and L 33  to the shift register 110, and then transferred to the lines L 40 , L 41 , L 42  and L 43  when the gate control signal LOD is made active. Thereafter, when the clock SCK is rendered active, the data d 0 , d 2 , d 1  and d 3  are latched to the flipflops 111, 112, 113 and 114, respectively, as shown in FIG. 6A. The data d 0 , d 2 , d 1  and d 3  thus latched in the flipflops 111, 112, 113 and 114 are outputted to the output buffers 121, 123, 122 and 124, respectively. Namely, the order of the data d 2  and d 1  is returned to the named order of d 1  and d 2 . Accordingly, the dta d 0  d 1 , d 2  and d 3  on the internal signal lines 10 to 16 are outputted to the output buffers 121, 122, 123 and 124, respectively. At this time, since the mode signal MOD4 is active and the other mode signals MOD2 and MOD1 are inactive, all the output buffers 121, 122, 123 and 124 are active or in an enable condition. Thus, the data d 0 , d 1 , d 2  and d 3  respectively inputted to the output buffers 121, 122, 123 and 124 are outputted to the external terminals 20 to 26, respectively. 
     (2) Active mode signal MOD2 (FIGS. 6B and 6C) 
     When the mode signal MOD2 is made active, the other mode signals MOD4 and MOD1 are inactive. Accordingly, the FETs Q 20 , Q 21 , Q 22  and Q 23  are turned on so that the respective data d 0 , d 1 , d 2  and d 3  on the internal signal lines 10, 12, 14 and 16 are relocated to the order of the respective data d 2 , d 1 , d 3  and d 0  and then transferred to the connection lines L 30 , L 31 , L 32  and L 33 . The relocated data d 2 , d 1 , d 3  and d 0  are transferred to the lines L 40 , L 41 , L 42  and L 43  when the gate control signal LOD is made active. Thereafter, when the clock SCK is rendered active, the data d 2 , d 1 , d 3  and d 0  are latched to the flipflops 111, 112, 113 and 114, respectively, as shown in FIG. 6B. The data d 2 , d 1 , d 3   and d 0  thus latched in the flipflops 111, 112, 113 and 114 are outputted to the output buffers 121, 123, 122 and 124, respectively. At this time, since the mode signal MOD2 is active and the other mode signal MOD1 is inactive, the output buffers 121 and 122 are made active or in an enable condition and the output buffers 123 and 124 are made inactive or in an disable condition. Thus, only the data d 2  and d 3  respectively inputted to the output buffers 121 and 122 are outputted to the external terminals 20 and 22, respectively, as shown in FIG. 6B. 
     Thereafter, the gate control signal LOD is made inactive, so that the connection lines L 30 , L 31 , L 32  and L 33  are isolated form the lines L 40 , L 41 , L 42  and L 43 . After this isolation, the active shift signal SFT is inputted to the gates of the FETs Q 50 , Q 51 , Q 52  and Q 53 , so that the outputs Q of the flipflops 111, 112, 123 and 124 are connected to the inputs D of the flipflops 112, 123, 124 and 121, respectively. Therefore, after the shift signal SFT is made inactive and when the clock SCK is made active, the contents of the outputs Q of the flipflops 111, 112, 123 and 124 are latched in the flipflops 112, 123, 124 and 121, respectively. Namely, The data d 0 , d 2 , d 1  and d 3  are latched in the flipflops 111, 112, 113 and 114, respectively, as shown in FIG. 6C and are ouputted form the outputs Q of the flipflops 111, 112, 113 and 114 to the output buffers 121, 123, 122 and 124, respectively. Namely, the data d 0  and d 1  of the data d 0 , d 2 , d 1  and d 3  are outputted through the buffers 121 and 122 to the external terminals 20 and 22, respectively, as shown in FIG. 6C. 
     (3) Active mode signal MOD1 (FIGS. 7A, 7B, 7C and 6D) 
     When the mode signal MOD1 is made active, the other mode signals MOD4 and MOD2 are inactive. Accordingly, the FETs Q 30 , Q 31 , Q 32  and Q 33  are turned on so that the respective data d 0 , d 1 , d 2  and d 3  on the internal signal lines 10, 12, 14 and 16 are relocated to the order of d 3 , d 0 , d 1  and d 2  and then transferred to the connection lines L 30 , L 31 , L 32  and L 33 . The relocated data d 3 , d 0 , d 1  and d 2  are transferred to the lines L 40 , L 41 , L 42  and L 43  through the FETs Q 40 , Q 41 , Q 42  and Q 43  when the gate control signal LOD is made active. Thereafter, when the clock SCK is rendered active, the data d 3 , d 0 , d 1  and d 2  are latched to the flipflops 111, 112, 113 and 114, respectively, as shown in FIG. 7A. The data d 3 , d 0 , d 1  and d 2  thus latched in the flipflops 111, 112, 113 and 114 are outputted to the output buffers 121, 123, 122 and 124, respectively. At this time, since the mode signal MOD1 is active, only the output buffer 121 is in an enable condition and the output buffers 122, 123 and 124 are made inactive or in an disable condition. Thus, only the data d 3  inputted to the output buffer 121 is outputted to the external terminal 20 as shown in FIG. 7A. 
     Thereafter, similarly to the case of the mode signal MOD4 being active, the gate control signal LOD is made inactive, so that the connection lines L 30 , L 31 , L 32  and L 33  are isolated from the lines L 40 , L 41 , L 42  and L 43 . After this isolation, the active shift signal SFT is inputted to the gates of the FETs Q 50 , Q 51 , Q 52  and Q 53 , so that the outputs Q of the flipflops 111, 112, 123 and 124 are connected to the inputs D of the flipflops 112, 123, 124 and 121, respectively. Therefore, after the shift signal SFT is made inactive and when the clock SCK is made active, the contents of the outputs Q of the flipflops 111, 112, 123 and 124 are latched in the flipflops 112, 123, 124 and 121, respectively. Namely, The data d 2 , d 3 , d 0  and d 1  are latched in the flipflops 111, 112, 113 and 114, respectively, as shown in FIG. 7B and are ouputted form the outputs Q of the flipflops 111, 112, 113 and 114 to the output buffers 121, 123, 122 and 124, respectively, so that the data d 2  is outputted through the buffer 121 to the external terminal 20, as shown in FIG. 7B. Thereafter, similarly, each time the shift control signal SFT and the clock SCK are applied, the data latched in the flipflops 111, 112, 113 and 114 are shifted by one bit so that the data d 1  and d 0  are sequentially outputted to the external terminal 20. 
     Thus, when the mode signal MOD1 is active, the data is sequentially outputted from the external terminal 20 in the order of d 3 , d 2 , d 1  and d 0 . 
     Turning to FIG. 8, there is shown a circuit diagram of one embodiment of the input port in accordance with the present invention, which can be used as the input port shown in FIG. 3. 
     The input circuit 140 includes four input buffers 141, 142, 143 and 144 located in parallel and having their inputs connected to the external terminals 20 to 26, respectively. 
     An output of the input buffer 141 is connected through a connection line L 60  to an input D of a D-type flipflop 151 included in the shift register 150. An output of the input buffer 143 in coupled to an input D of a D-type flipflop 152 through a connection line L 51 , a transfer gate FET Q 60  and a connection line L 61 . The FET Q 60  has a gate connected to receive the mode signal MOD4 so that the signal MOD4 is active, the line L 51  is connected to the line L 61 . An output of the input buffer 142 is coupled through a connection line L 52 , a transfer gate FET Q 61  and a connection line L 62  to an input D of a D-type flipflop 153. The FET Q61 has a gate connected to receive through an OR gate 155 the mode signal MOD4 and the mode signal MOD2 so that the signal MOD4 or MOD2 is active, the line L 52  is connected to the line L 62 . An output of the input buffer 144 is coupled to an input D of a D-type flipflop 154 through a connection line L 53 , a transfer gate FET Q 62  and a connection line L 63 . The FET Q 62  has a gate connected to receive the mode signal MOD4 so that the signal MOD4 is active, the line L 53  is connected to the line L 63 . 
     All the flipflops 151 to 154 are connected to receive the same clock SCK at their clock inputs. Further, a Q output of the flipflop 151 is connected to the line L 61  through a transfer gate FET Q 70  whose gate is connected to receive the mode signals MOD2 and MOD1 through an OR gate 156, so that when either the mode signal MOD2 or MOD1 is made active, the output of the flipflop 151 is coupled to the input D of the flipflop 152. Similarly, a Q output of the flipflop 152 is connected to the line L 62  through a transfer gate FET Q 71  whose gate is connected to receive the mode signal MOD1. In addition, a Q output of the flipflop 153 is connected to the line L 63  through a transfer gate FET Q 72  whose gate is connected to receive the mode signals MOD2 and MOD1 through the OR gate 156. 
     The respective outputs Q of the flipflops 151 to 154 are connected to four connection lines L 23 , L 22 , L 21  and L 20 , respectively. These connection lines L 23 , L 22 , L 21  and L 20  are connected through transfer gate FETs Q 80 , Q 82 , Q 81  and Q 83  to four connectioon lines L 10 , L 12 , L 11  and L 13 , respectively. The FETs Q 80 , Q 82 , Q 81  and Q 83  have their gates commonly connected to receive through an OR gate 161 the mode signals MOD4 and MOD2 so that either the mode signal MOD4 or MOD2 is active, the lines L 23 , L 22 , L 21  and L 20  are connected to the lines L 10 , L 12 , L 11  and L 13 , respectively. Further, the lines L 23 , L 22 , L 21  and L 20  are respectively connected to four connection lines L 10 , L 11 , L 12  and L 13  through transfer gate FETs Q 90 , Q 91 , Q 92  and Q 93  whose gates are commonly connected to receive the mode signal MODE1. The four connection lines L 10 , L 11 , L 12  and L 13  are connected to the internal signal lines 10, 12, 14 and 16, respectively. 
     Now, operation of the input port shown in FIG. 8 will be explained with reference to FIGS. 9A to 9C and 10A and 10D which illustrate the relation between the data on the internal signal lines 10 to 16 and the data on the external terminals 20 to 26 of the input port shown in FIG. 8 in different operation modes. 
     (1) Active mode signal MOD4 (FIG. 9A) 
     When the mode signal MOD4 is made active, the other mode signals MOD2 and MOD1 are inactive. Accordingly, the FETs Q 70 , Q 71 , Q 72  and Q 73  are maintained off and the FETs Q 60 , Q 61  and Q 12  are turned on. Therefore, the data d 0 , d 1 , d 2  and d 3  inputted form the external terminals 20, 22, 24 and 26 are inputted through the input buffers 141 to 144 to the connection lines L 60 , L 62 , L 61  and L 63 . When the clock SCK is rendered active, the flipflops 151, 153, 152 and 154 respectively latch the data d 0 , d 2 , d 1  and d 3  on the lines 60, 61, 62 and 63, as shown in FIG. 9A. The data d 0 , d 2 , d 1  and d 3  thus latched are outputted from the Q outputs of the the flipflops 151, 153, 152 and 154 to the connection lines L 23 , L 22 , L 21  and L 20  of the scrambler 160, respectively. The data d 0 , d 2 , d 1  and d 3  on the lines L 23 , L 2i , L 21  and L 20  are supplied through the FETs Q 80 , Q 82 , Q 81  and Q 83  to the connection lines L 10 , L 11 , L 12  and L 13 , as seen from FIG. 8. Namely, the positions of data d 2  and d 1  are exchanged by the scrambler 160. Thus, the data d 0 , d 1 , d 2  and d 3  relocated in the named order are inputted form the connection lines L 10 , L 11 , L 12  and L 13  to the internal signal lines 10, 12, 14 and 16, respectively. Accordingly, the data d 0 , d 1 , d 2  and d 3  on the external terminals 20 to 26 are inputted to the internal signal lines 10 to 16, respectively. 
     (2) Active mode signal MOD2 (FIGS. 9B and 9C) 
     When the mode signal MOD2 is made active, the other mode signals MOD4 and MOD1 are inactive. Accordingly, the FETs Q 60 , Q 62  and Q 71  are maintained off and the FETs Q 61 , Q 70  and Q 72  are turned on. Therefore, the data d 2  and d 3  inputted to the external terminals 20 and 22 are supplied through the input buffers 141 and 142 to the connection lines L 60  and L 62 . When the clock SCK is rendered active, the flipflops 151 and 153 respectively latch the data d 2  and d 3 , as shown in FIG. 9B. The data d 2  and d 3  thus latched are outputted from the Q outputs of the the flipflops 151 and 153 to the internal signal lines 10 and 12, respectively. 
     After the data d 2  and d 3  are latched in the flipflops 151 and 153, the data d 0  and d 1  are inputted to the external terminals 20 and 22. The data d 0  and d 1  inputted to the external terminals 20 and 22 are supplied through the input buffers 141 and 142 to the connection lines L 60  and L 62 . When the clock SCK is rendered active, the flipflops 151 and 153 respectively latch the data d 0  and d 1 , and the flipflops 152 and 154 respectively latch the data d 2  and d 3  outputted from the Q outputs of the flipflops 151 and 153 through the FETs Q 70  and Q 72  in the conductive condition, as shown in FIG. 9C. The data d 0 , d 2 , d 1  and d 3  thus latched are outputted from the Q outputs of the the flipflops 151 to 154 through the scrambler 160 to the internal signal lines 10 to 16 in the order of data d 0 , d 1 , d 2   and d 3 , as shown in FIG. 9C. 
     Accordingly, the data d 2  and d 3  and the data d 0  and d 1  which are sequentially supplied in a two-bits-by-two-bits manner to the external terminals 20 and 22 are inputted to the internal signal lines 10 to 16 in the order of data d 0 , d 1 , d 2  and d 3  in a parallel arrangement. 
     (3) Active mode signal MOD1 (FIGS. 10A, 10B, 10C and 10 D) 
     When the mode signal MOD1 is made active, the other mode signals MOD4 and MOD2 are inactive. Accordingly, the FETs Q 60 , Q 61  and Q 62  are maintained off and the FETs Q 70 , Q 71  and Q 72  are turned on. Therefore, only the output of the input buffer 141 of the four buffers 141 to 144 is inputted to the input D of the flipflop 151. 
     When the data d 3  is inputted to the external terminal 20 and the active clock SCK is applied to the four flipflops 151 to 154, the flipflop 151 latches the data d 3 , as shown in FIG. 10A. At the next clock SCK, the data d 2  is inputted to the external terminal 20 so that the flipflop 151 latches the data d 2 , and the flipflop 152 latches the data d 3  outputted from the Q output of the flipflop 151 through the conducting FET Q 70 , as shown in FIG. 10B. Similarly, at third and fourth clocks SCK, the data d 1  and d 0  are sequentially inputted to the external terminal 20 so that the flipflop 151 sequentially latches the data d 1  and d 0 . On the other hand, the data latched in the respective flipflops are sequentially shifted. As result, after the fourth clock SCK, the data d 0 , d 1 , d 2  and d 3  are latched in the the flipflops 151 to 154 and are outputted from the Q outputs of the flipflops 151 to 154 through the FETs Q 90 , Q 91 , Q 93  and Q 94  of the scrambler 160 to the internal signal lines 10 to 16 in the order of data d 0 , d 1 , d 2  and d 3 , as shown in FIG. 10D. 
     Accordingly, the data d 3 , d 2 , d 1  and d 1  which are sequentially supplied byit by bit to the external terminal 20 are inputted to the internal signal lines 10 to 16 in the order of data d 0 , d 1 , d 2  and d 3  in a parallel arrangement. 
     Referring to FIG. 11, there is shown a circuit diagram of another embodiment of the output port in accordance with the present invention, which can be used as the output port shown in FIG. 3. But, as seen form comparison between FIGS. 3 and 11, the scrambler 100 and the shift register 110 are exchanged in positional sequence. 
     The shift register 110 includes four FETs Q 100 , Q 101 , Q 102  and Q 103  connected at their one ends to the internal signal lines 10, 12, 14 and 16, respectively. The FETs Q 100 , Q 101 , Q 102  and Q 103  have their gates commonly connected to receive a gate control signal LOD, and the other ends of the FETs Q 100 , Q 101 , Q 102  and Q 103  are connected to inputs D of four D-type flipflops 115, 116, 117 and 118, respectively, so that when the gate control signal LOD is made active, the signal on the internal signal lines 10 to 16 are inputted to the inputs D of four D-type flipflops 115, 116, 117 and 118. These flipflops are connected to receive the clock signal SCK at their clock input C, and D outputs of the flipflops 115, 116, 117 and 118 are connected to the four connection lines L 10 , L 11 , L 12  and L 13  of the scrambler 100. 
     Further, the D input of the flipflop 116 is connected to the connection line L 10  through FETs Q 111  and Q 121 , and the D input of the flipflop 117 is connected to the connection line L 11  through FETs Q 112  and Q 122  and to the connection line L 10  through FETs Q 112  and Q 132 . In addition, the D input of the flipflop 118 is connected to the connection line L 12  through FETs Q 113  and Q 123  and to the connection line L 11  through FETs Q 113  and Q 133 . FETs Q 111 , Q 112  and Q 113  have their gates commonly connected to receive the shift control signal SFT. FETs Q 121 , Q 122  and Q 123  have their gates commonly connected to receive the mode signal MOD1. FETs Q 132  and Q 133  have their gates commonly connected to receive the mode signal MOD2. 
     In the scrambler 100, the four connection lines L 10 , L 11 , L 12  and L 13  are connected to four connection lines L 20 , L 21 , L 22  and L 23 , respectively, through FETs Q 140 , Q 141 , Q 142  and Q 143  whose gates are connected to receive the mode signal MOD4. Further, the connection lines L 12 , L 13 , L 10  and L 11  are connected to the connection lines L 20 , L 21 , L 22  and L 23 , respectively, through FETs Q 150 , Q 151 , Q 152  and Q 153  whose gates are connected to receive the mode signal MOD2. The connection lines L 13 , L 10 , L 11  and L 12  are also connected to the connection lines L 20 , L 21 , L 22  and L 23 , respectively, through FETs Q 160 , Q 161 , Q 162  and Q 163  whose gates are connected to receive the mode signal MOD1. 
     The output circuit 120 shown in FIG. 11 are constructed similar to that shown in FIG. 5. But the connection lines L 20 , L 21 , L 22  and L 23  are connected to the inputs of the output buffers 121 to 124, respectively. 
     Now, the operation of the output port shown in FIG. 11 will be explained with reference to FIGS. 12A to 12C and 13A and 13D which illustrate the relation between the data on the internal signal lines 10 to 16 and the data on the external terminals 20 to 26 of the output port shown in FIG. 11 in different operation modes. 
     (1) Active mode signal MOD4 (FIG. 12A) 
     When the mode signal MOD4 is made active, the other mode signals MOD2 and MOD1 are inactive. Accordingly, FETs Q 121 , Q 122  and Q 123 , FETs Q 132  and Q 133  FETs Q 150 , Q 151 , Q 152  and Q 153  and FETs Q 160 , Q 161 , Q 162  and Q 163  are maintained off, and the FETs Q 140 , Q 141 , Q 142  and Q 143  are turned on. In addition, all the output buffers 121 to 124 are maintained in the enable condition. Therefore, the respective data d 0 , d 1 , d 2  and d 3  on the internal signal lines 10, 12, 14 and 16 are transferred to the flipflops 115 to 118 when the gate control signal LOD is made active and latched to these flipflops when the clock SCK is made active. As a result, the respective data d 0 , d 1 , d 2  and d 3  latched in the flipflops 115 to 118 to the external terminals 20 to 26, respectively, without relocation of parallel data bits, as shown in FIG. 12A. 
     (2) Active mode signal MOD2 (FIGS. 6B and 6C) 
     When the mode signal MOD2 is made active, the other mode signals MOD4 and MOD1 are inactive. Accordingly, FETs Q 121 , Q 122  and Q 123 , FETs Q 140 , Q 141 , Q 142  and Q 143  and FETs Q 140 , Q 161 , Q 162  and Q 163  are maintained off and the FETs Q 132  and Q 133 , and FETs Q 150 , Q 151 , Q 152  and Q 153  are turned on. In addition, the output buffers 121 and 122 are maintained in the enable condition but the output buffers 123 and 124 are maintained in the disable condition. 
     Thus, when the gate control signal LOD is made active, the respective data d 0 , d 1 , d 2  and d 3  on the internal signal lines 10, 12, 14 and 16 are inputted to the flipflops 115 to 118, and then latched to these flipflops when the clock SCK is made active. As a result, the respective data d 0 , d 1 , d 2  and d 3  latched in the flipflops 115 to 118. Therefore, the respective data d 2  and d 3  latched in the flipflops 117 and 118 to the external terminals 20 and 22, respectively, through the FETs Q 150  and Q 151 , as shown in FIG. 12A. 
     Thereafter, the gate control signal LOD is made inactive, so that the signal lines 10 to 16 are isolated form the flipflops 115 to 118. After this isolation, the active shift signal SFT is inputted to the gates of the FETs Q 111  to Q 113 , so that the outputs Q of the flipflops 115 and 116 are connected to the inputs D of the flipflops 117 and 118, respectively. Therefore, after the shift signal SFT made inactive and when the clock SCK is made active, the outputs Q of the flipflops 115 and 116 are latched in the flipflops 117 and 118, respectively. Namely, the data d 0  and d 2 , are latched in the flipflops 117 and 118, respectively, as shown in FIG. 12C and are outputted to the output buffers 121 and 122, respectively. On the other hand, the content of the flipflops 115 and 116 are not constant. Thus, the data d 0  and d 1  of the data d 0 , d 2 , d 1  and d 3  are outputted through the buffers 121 and 122 to the external terminals 20 and 22, respectively, as shown in FIG. 12C. 
     (3) Active mode signal MOD1 (FIGS. 13A, 13B, 13C and 13D) 
     When the mode signal MOD1 is made active, the other mode signals MOD4 and MOD2 are inactive. Accordingly, FETs Q 132  and Q 133 , FETs Q 140 , Q 141 , Q 142  and Q 143  and FETs Q 132  and Q 133 , FETs Q 140 , Q 141 , Q 142  and Q 143  and FETs Q 150  and Q 151 , Q 152  and Q 153  are maintained off, and the FETs Q 121 , Q 122  and Q 123 , and FETs Q 160 , Q 161 , Q 162  and Q 163  are turned on. In addition, only the output buffer 121 is maintained in the enable condition but the output buffers 122, 123 and 124 are maintained in the disable condition. 
     Thus, when the gate control signal LOD is made active, the respective data d 0 , d 1 , d 2  and d 3  on the internal signal lines 10, 12, 14 and 16 are inputted to the flipflops 115 to 118, and the latched to these flipflops when the clock SCK is made active. As a result, the respective data d 0 , d 1 , d 2  and d 3  latched in the flipflops 115 to 118. Therefore, the respective data d 3  latched in the flipflop 118 is outputted to the external terminal 20 through the FET Q 160 , as shown in FIG. 13A. 
     Thereafter, the gate control signal LOD is made inactive, so that the signal lines 10 to 16 are isolated form the flipflops 115 to 118. After this isolation, the active signal SFT is inputted to the gates of the FETs Q 111  to Q 113 , so that the inputs Q of the flipflops 115, 116 and 117 are connected to the inputs D of the flipflops 116, 117 and 118, respectively. Therefore, after the shift signal SFT made inactive and when the clock SCK is made active, the outputs Q of the flipflops 115, 116 and 117 are latched in the flipflops 116, 117 and 118, respectively. Namely, the data d 0 , d 1  and d 2 , are latched in the flipflops 116, 117 and 118, respectively, as shown in FIG. 13B and the data d 2  is outputted to the output buffer 121. 
     Thereafter, similarly, each time the shift control signal SFT and the clock SCK are applied, the data latched in the flipflops 115, 116, 117 and 118 are shifted by one bit so that the data d 1  and d 0  are sequentially outputted to the external terminal 20. 
     Thus, when the mode signal MOD1 is active, the data is sequentially outputted from the external terminal 20 in the order of d 3 , d 2 , d 1  and d 0 . 
     Turning to FIG. 14, there is shown a circuit diagram of another embodiment of the input port in accordance with the present invention, which can be used as the input port shown in FIG. 3. 
     The input circuit 140 includes four input buffers 141, 142, 143 and 144 located in parallel and having their inputs connected to the external terminals 20 to 26, respectively. 
     An output of the input buffer 141 is connected through three parallel-connected FET Q 190 , Q 200  and Q 210  to an input D of the D-type flipflop 151, which has a Q output connected to the internal signal line 10 and a connection line L 93 . An output of the input buffer 142 is connected through two parallel-connected FET Q 191  and Q 201  to an input D of the D-type flipflop 152, which has a Q output connected to the internal signal line 12 and a connection line L 92 . An output of the input buffer 143 is connected through a FET Q 192  to an input D of the D-type flipflop 153, which has a Q output connected to the internal signal line 14 and a connection line L 91 . Further, an output of the input buffer 144 is connected through a FET Q 193  to an input D of the D-type flipflop 154, which has a Q output connected to the internal signal line 116 and a connection line L 90 . In addition, the D input of the flipflop 152 is connected to the connection line L 93  through a FET Q 211 . The D input of the flipflop 153 is connected to the connection line L 93  through a FET Q 202  and to the connection line L 92  through a FET Q 212 . Further, the D input of the flipflop 154 is connected to the connection line L 92  through a FET Q 203  and to the connection line L 91  through a FET Q 213 . 
     The FET Q 190 , Q 191 , Q 192  and Q 193  have their gates commonly connected to receive the mode signal MOD4. The FET Q 200 , Q 201 , Q 202  and Q 203  have their gates commonly connected to receive the mode signal MOD2. The FET Q 210 , Q 211 , Q 212  and Q 213  have their gates commonly connected to receive the mode signal MOD1. 
     Now, operation of the output port shown in FIG. 14 will be explained with reference to FIGS. 15A to 15C and 16A and 16D which illustrate the relation between the data on the terminal signal lines 10 to 16 and the data on the external terminals 20 to 26 of the input port shown in FIG. 14 in different operation modes. 
     (1) Active mode signal MOD4 (FIG. 15A) 
     When the mode signal MOD4 is made active, the other mode signals MOD2 and MOD1 are inactive. Accordingly, the FET Q 200 , Q 201 , Q 202  and Q 203  and the FET Q 210 , Q 211 , Q 212  and Q 213  are maintained off and the FET Q 190 , Q 191 , Q 192  and Q 193  are turned on. Therefore, the data d 0 , d 1 , d 2  and d 3  inputted on the external terminals 20, 22, 24 and 26 are applied through the input buffers 141 to 144 and to the FET Q 190 , Q 191 , Q 192  and Q 193  to the flipflops 151, 153, 152 and 154, respectively. These flipflops latch the data d 0 , d 2 , d 1  and d 3 , as shown in FIG. 15A. The data d 0 , d 2 , d 1  and d 3  thus latched are outputted from the Q outputs of the the flipflops 151, 153, 152 and 154 to to the internal signal lines 10, 12, 14 and 16, respectively. Accordingly, the data d 0 , d 1 , d 2  and d 3  on the external terminals 20 to 26 are inputted to the internal signal lines 10 to 16, respectively. 
     (2) Active mode signal MOD2 (FIGS. 15B and 15C) 
     When the mode signal MOD2 is made active, the other mode signals MOD4 and MOD1 are inactive. Accordingly, the FET Q 190 , Q 191 , Q 192  and Q 193  and the FET Q 210 , Q 211 , Q 212  and Q 213  are maintained off and the FET Q 200 , Q 201 , Q 202  and Q 203  are turned on. Therefore, the data d 2  and d 3  inputted to the external terminals 20 and 22 are supplied through the input buffers 141 and 142 to the flipflops 151 and 152. When the clock SCK is rendered active, the flipflops 151 and 152 respectively latch the data d 2  and d 3 , as shown in FIG. 15B. The data d 2  and d 3  thus latched are outputted from the Q outputs of the the flipflops 151 and 152 to the D inputs of the flipflops 153 and 154 through a path formed of the connection line L 93  and the FET Q 202  and another path formed of the connection line L 92  and the FET Q 203 , respectively. 
     When the clock SCK is made active after the data d 2  and d 3  are latched in the the flipflops 151 and 152, the data d 0  and d 1  are inputted from the external terminals 20 and 22 to to the flipflops 151 and 152. When the clock SCK is rendered active, the flipflops 151 and 152 respectively latch the data d 0  and d 1 , and the flipflops 153 and 154 respectively latch the data d 2  and d 3  outputted from the Q outputs of the flipflops 151 and 152, as shown in FIG. 15C. Thus, the data d 0 , d 2 , d 1  and d 3  thus latched are outputted from the Q outputs of the the flipflops 151 and 153 to the internal signal lines 10 to 16 in the order of data d 0 , d 1 , d 2  and d 3 , as shown in FIG. 9C. 
     (3) Active mode signal MOD1 (FIGS. 16A, 16B, 16C and 16D) 
     When the mode signal MOD1 is made active, the other mode signals MOD4 and MOD2 are inactive. Accordingly, the FET Q 190 , Q 191 , Q 192  and Q 193  and the FET Q 200 , Q 201 , Q 202  and Q 203  are maintained off and the FET Q 210 , Q 211 , Q 212  and Q 213  are turned on. 
     When the data d 3  is inputted to the external terminal 20 and the active clock SCK is applied to the four flipflops 151 to 154, the flipflop 151 latches the data d 3 , as shown in FIG. 16A. At the next clock SCK, the data d 2  is inputted to the external terminal 20 so that the flipflop 151 latches the data d 2 , and the flipflop 152 latches the data d 3  outputted from the Q output of the flipflop 151 through the connection line L 93  and the conducting FET Q 211 , as shown in FIG. 16B. Similarly, at third and fourth clocks SCK, the data d 1  and d 0  are sequentially inputted to the external terminal 20 so that the flipflop 151 sequentially latches the data d 1  and d 0 . On the other hand, the data latched in the respective flipflops are sequentially shifted. As result, after the four clock SCK, the data d 0 , d 1 , d 2  and d 3  are latched in the the flipflops 151 to 154 and are inputted from the Q outputs of the the flipflops 151 to 154 to the internal signal lines 10 to 16 in the order of data d 0 , d 1 , d 2   and d 3 , as shown in FIG. 16D. 
     When the digital input/output circuit is used in a memory circuit, a high speed operation is demanded, and this demand is gradually increased. For example, it is required to operate with a basic clock of 30 ns. In this case, when the input/output circuit is operated in the serial mode (MOD1) on the basis of the basic clock SCK of 30 ns, the data must be transferred through the data input buffer, shift register, the scrambler and the internal data bus for a very short limited time, and then transmitted to a data register inherent to the memory circuit within a predetermined period of time. The above mentioned second embodiment omits one stage of transfer gate which is one cause for delay, as compared with the first embodiment, so that it makes a high speed operation. Accordingly, the second embodiment can execute all operations which can be performed in the first embodiment, at a speed higher than that of the first embodiment, and with a less number of perts than that required in the first embodiment. 
     As is apparent from the above explanation of the preferred embodiments of the invention, the input/output circuit in accordance with the present invention is characterized by the provision of the scrambler and the data shifter in the input/output port so that the data processing in the input/output port can be executed in any format of 2 m . Therefore, the function of the input/output circuit is greatly increased. This is very effective particularly in the case of processing the pixel data in the graphic display technology, since a external circuit including a so-called parallel-to-serial converting shifter can be omitted. 
     The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.