Abstract:
The invention discloses a display panel. A substrate comprising a chip bonding region and a cut cross-section is provided. A first conductive layer is disposed on the chip bonding region. An insulating layer is disposed on the substrate between the first conductive layer and the cut cross-section, covering a sidewall of the first conductive layer. A second conductive layer is disposed on the insulating layer extending until the cut cross-section and electrically connected to the first conductive layer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a display panel and in particular to a display panel with corrosion protection. 
         [0003]    2. Description of the Related Art 
         [0004]    Flat panel display devices commonly use LCD panels. An LCD panel may include a pixel region having an array of pixel thin film transistors and intersecting arrays of spaced data lines and gate lines connected to the array of pixel thin film transistors. The array of pixel thin film transistors, data lines and gate lines form an array of addressable pixels. The LCD panel may also include a peripheral region associated with driver integrated circuit chips (ICs), which drive the array of pixel thin film transistors. The ICs may be mounted to the LCD panel in the peripheral region thereof using a chip-on-glass (COG), tape-carrier-package (TCP) or chip-on-film (COF) technology. In COG, TCP and COF, anisotropic conductive films (ACFs) bond the driver ICs or the flexible printed circuits or other films which carry driver ICs to the LCD panel. 
         [0005]      FIG. 1  is a plane view of a traditional LCD panel  100 . The panel  100  includes a pixel region  101  and a peripheral region  103 , which comprises a chip bonding region  105  with a plurality of chip bonding pads (not shown), and fringe circuit  107  with a plurality of test pads (not shown). The pixel region  101  has a pixel thin film transistor (TFT) array with conductive gate and data lines (not shown). 
         [0006]    The fringe circuit region  107  serves as a signal receiver during array testing, or is connected to an ESD (electrostatics discharge) circuit, providing electrostatic protection. The fringe circuit is provided adjacent to a chip bonding region  105  of the LCD panel. The fringe circuit is electrically connected to a group of terminal pads disposed on the surface of the LCD panel, which are electrically connected to the integrated circuits (ICs) with anisotropic conductive film bonds. 
         [0007]      FIG. 2A  is a cross-section diagram of the peripheral region  103  of the traditional LCD panel  100  along the dash line A-A′. As shown in  FIG. 2A , the peripheral region  103  comprises a substrate  201  having a chip bonding region  105  and a fringe circuit region  107 , and a conductive layer  203  disposed thereon. The chip bonding region  105  is separated apart from the fringe circuit region  107  by an insulating layer  207 . A conductive layer  205  is formed covering the conductive layer  203  and part of the top surfaces of the insulating layer  207 , exposing a cut region  209  of the insulating layer  207 . The fringe circuit region is used to receive the driving signals during the array test or protect the electrostatics discharge damage during the manufacturing process. After a cell process, the fringe circuit region  107  is removed by cutting through the cut region  209  within the insulating layer  207 , exposing the sidewall of the conductive layer  203  to the air, as shown in  FIG. 2B , such that the exposed sidewall  210  of the conductive layer  203  is corroded. The corrosion extends to the bonding pads through the conductive layer resulting in failure of signal transmission 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    The invention provides a display panel comprising an insulating layer to protect the sidewall of the conductive layer from corrosion after cutting. 
         [0009]    In one embodiment, a display panel comprises a substrate comprising a chip bonding region and a cut cross-section; an insulating layer on the substrate between the first and the second conductive layer and the cut cross-section, covering a sidewall of the first conductive layer; and a second conductive layer disposed on the insulating layer extending until the cut cross-section and electrically connected to the first conductive layer. 
         [0010]    In another embodiment, the display panel comprises a substrate comprising a chip bonding region, a fringe circuit region and a cut cross-section; a first conductive layer on the chip bonding region; a second conductive layer on the fringe circuit region, wherein the first and the second conductive layer have opposite sidewalls; a first insulating layer on the substrate, between the first and the second conductive layer and covering the opposite sidewalls; a second insulating layer disposed on the second conductive layer, spaced from the first insulating layer; and a third conductive layer disposed on the first and the second insulating layers extending until the cut cross-section and electrically connected the first and the second conductive layers. 
         [0011]    In yet another embodiment, the display panel comprises a substrate comprising a chip bonding region and a cut cross-section; a first conductive layer on the chip bonding region; a first insulating layer on the substrate, between the first conductive layer and the cut cross-section, covering a sidewall of the first conductive layer; a second conductive layer on the first insulating layer; a second insulating layer covering the second conductive layer, with an opening exposing a top surface thereof, and a third conductive layer disposed on the second insulating layer extending until the cut cross-section and electrically connecting the first and second conductive layers. 
         [0012]    In addition, the display panel further comprises a fringe circuit region on the substrate; a fourth conductive layer on the fringe circuit region, between the first insulating layer and the cut cross-section; a third insulating layer disposed on the fourth conductive layer extending until the cut cross-section; and the third conductive layer disposed on the third insulating layer extending until the cut cross-section and electrically connecting the first, second and third conductive layers. 
         [0013]    A detailed description is given in the following with reference to the accompanying drawing. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0015]      FIG. 1  is a plane view of a traditional LCD panel with chip-on-class (COG) bonded driver integrated circuit chips (ICs); 
           [0016]      FIG. 2A  is a cross-section of the peripheral region of a traditional LCD panel along the line A-A′ of  FIG. 1 ; 
           [0017]      FIG. 2B  is a cross-section of the peripheral region of a traditional LCD panel after removal of the fringe circuit region by cutting; 
           [0018]      FIG. 3  is a plane view of a LCD panel of the invention with chip-on-class (COG) bonded driver integrated circuit chips (ICs); 
           [0019]      FIG. 4A  is a cross-section of the peripheral region of the LCD panel of  FIG. 3 ; 
           [0020]      FIG. 4B  is a cross-section of the peripheral region of the LCD panel after removal of the fringe circuit region by cutting; 
           [0021]      FIG. 5A  is a cross-section of a peripheral region according to one embodiment of the invention; 
           [0022]      FIG. 5B  is a cross-section of a peripheral region according to  FIG. 5A  after removal part of the fringe circuit region by cutting at one position; 
           [0023]      FIG. 5C  is a cross-section of a peripheral region according to  FIG. 5A  after removal part of the fringe circuit region by cutting at the other position; 
           [0024]      FIG. 6A  is a cross-section of a peripheral region according to another embodiment of the invention; 
           [0025]      FIG. 6B  is a cross-section of a peripheral region according to  FIG. 6A  after removal part of the fringe circuit region by cutting at one position; 
           [0026]      FIG. 6C  is a cross-section of a peripheral region according to  FIG. 6A  after removal part of the fringe circuit region by cutting at the other position; 
           [0027]      FIG. 7A  is a cross-section of a peripheral region according to further another embodiment of the invention; and 
           [0028]      FIG. 7B  is a cross-section of a peripheral region according to  FIG. 7A  after removal part of the fringe circuit region by cutting. 
       
    
    
     DETAILED DESCRIPTION OF INVENTION 
       [0029]    The invention provides a display panel having an insulating layer to protect the sidewall of the conductive layer from corroding after cutting. 
         [0030]    Reference will now be made in detail to preferred embodiments, examples of which are illustrated in the accompanying drawings. 
         [0031]      FIG. 3  is a plane view of a LCD panel  300  of the invention. The panel  300  comprises a pixel region  301  and a peripheral region  303 , wherein the peripheral region  303  comprises a chip bonding region  305  and fringe circuit region  307  next to the chip bonding region. The pixel region  301  has a pixel thin film transistor array (TFT) with conductive gate and data lines (not shown). 
         [0032]      FIG. 4A  is a cross-section of a peripheral region  303  of the LCD panel  300  along the dash line B-B′. As shown in  FIG. 4A , the peripheral region  303  comprises a substrate  401 , such as glass substrate, having a chip bonding region  305  and a fringe circuit region  307 . Conductive layers  403   a  and  403   b  having opposite sidewalls  403   c  are disposed on the chip bonding region and the fringe circuit region respectively. Conductive layer  403   a  and  403   b  may be metal, such as Mo, Ti, Cr, W, Al, AlNd, MoW or like. An insulating layer  407  is formed on the substrate  401  between the conductive layer  403   a  and  403   b , covering the opposite sidewalls  403   c  thereof. The insulating layer  407  may be but is not limited to oxide or nitride. As shown in  FIG. 4A , the insulating layer  407  preferably covers part of the top surface of the conductive layer  403   a  and  403   b , providing complete protection of the sidewall  403   c  of the conductive layer  403   a  and  403   b . A conductive layer  409  is formed on the conductive layer  403   a , the insulating layer  407  and the conductive layer  403   b , electrically connecting the chip bonding region  305  and fringe circuit region  307 . The conductive layer  409  may be a transparent conductive layer, such as ITO, IZO, AZO, or CTO. Overlying the chip bonding region  305  further comprises a chip bonding pad and IC chip thereon (not shown). After cell process, the fringe circuit region  307  is removed by cutting through the cut region  405  within the insulating layer  407  between the opposite sidewalls  403   c . A cross-section of the LCD panel  300  after cutting is shown in  FIG. 4B , wherein a cut cross-section  410  is produced along the boundary of the cut region  405  of  FIG. 4A . Compared to the traditional display panel shown in  FIGS. 2A and 2B , the sidewall  403   c  of the conductive layer  403   a  is protected by the insulating layer  407 , such that the sidewall  403   c  of the conductive layer  403   a  is not exposed and corroded after cutting, as shown in  FIG. 4B . In this embodiment, the electrical connection between the chip bonding region  305  and the fringe circuit region  307  accomplished by the conductive layer  409 . 
         [0033]      FIG. 5A  shows a cross-section of the peripheral region  303  according to another embodiment of the invention. As shown in  FIG. 5A , the peripheral region  303  comprises a substrate  601  having a chip bonding region  305  and a fringe circuit region  307 . Conductive layer  603   a  and  603   b  having opposite sidewalls  603   c  are disposed on the chip bonding region  305  and fringe circuit region  307  respectively. The conductive layer  603   a  and  603   b  may be metal, such as Mo, Ti, Cr, W, Al, AlNd, MoW or like. An insulating layer  607  is formed on the substrate  601  between the conductive layer  603   a  and  603   b  and covers the opposite sidewalls  603   c  thereof. The insulating layer  607  may be oxide or nitride. Referring to  FIG. 5A , the insulating layer  607  preferably covers part of the top surfaces of the conductive layers  603   a  and  603   b . An insulating layer  611  is disposed on the conductive layer  603   b , spaced from the insulating layer  607 . The insulating layer  611  and  607  may be the same or different materials. A conductive layer  609  is formed to cover the conductive layer  603   a , the insulating layer  607  and part of the insulating layer  611 , electrically connecting the chip bonding region  305  and the fringe circuit region  307 . The conductive layer  609  may be a transparent conductive material, such as ITO, IZO, AZO, or CTO. In this embodiment, the cut region  605  may be within the insulating layer  607  between the opposite sidewalls  603   c  or, alternatively, within the insulating layer  611 . After cell process, the fringe circuit region  307  is removed by cutting through the cut region  605  within the insulating layer  607  or the insulating layer  611 , and the insulating layer  607  protects the conductive layer  603   a  from corrosion. 
         [0034]      FIG. 5B  shows the resulting structure when the cutting is conducted on the cut region  605  within the insulating layer  611 . As shown in  FIG. 5B , a cut cross-section  610  produced is along the boundary of the cut region  605  of  FIG. 5A . The insulating layer  607  prevents the corrosion from extending to the conductive layer  603   a , whereby the corrosion only happens within the conductive layer  603   b .  FIG. 5C  shows the resulting structure when the cutting is conducted on the cut region  605  within the insulating layer  607 . As shown in  FIG. 5C , a cut cross-section  612  produced is along the boundary of the cut region  605  of  FIG. 5A . The insulating layer  607  prevents the corrosion from extending to the conductive layer  603   a.    
         [0035]      FIG. 6A  shows a cross-section of the peripheral region  303  according to another embodiment of the invention. As shown in  FIG. 6A , the peripheral region  303  comprises a substrate  701  having a chip bonding region  305  and a fringe circuit region  307 . Conductive layers  703   a  and  703   b  are disposed on the chip bonding region  305  and the fringe circuit region  307  respectively. An insulating layer  707  is formed on the substrate  701  between the conductive layer  703   a  and  703   b  and covers opposite sidewalls  703   c  thereof. The insulating layer  707  may be oxide or nitride. Referring to shown  FIG. 6A , the insulating layer  707  also may cover part of the top surfaces of the conductive layers  703   a  and  703   b . A conductive layer  708  is disposed on the insulating layer  707 . In this embodiment, the conductive layers  703   a ,  703   b  and  708  may be the same or different materials. An insulating layer  710  is optionally formed on the conductive layer  708 , having an opening exposing the top surface thereof. As shown in  FIG. 6A , the insulating layer  710  is formed on the corners of the conductive layer  708 . An insulating layer  711  is formed on the conductive layer  703   b , spaced from the insulating layer  707 . A conductive layer  709  is formed to cover the conductive layer  703   a , the insulating layer  710 , the conductive layer  708 , and the exposed conductive layer  703   b  between the insulating layer  711  and  707 , and part of the insulating layer  711 , electrically connecting the chip bonding region  305  and the fringe circuit region  307 . The conductive layer  709  may be a transparent conductive material, such as ITO, IZO, AZO, or CTO. In this embodiment, the cut region  705  may be within the insulating layer  707  between the opposite sidewalls  703   c  or within the insulating layer  711 . The conductive layer  709  at the cut region  705  within the insulating layer  707  can be disposed with an opening exposing a top surface of the conductive layer  708 . After cell process, the fringe circuit region  307  is removed by cutting through the cut region  705  within the insulating layer  707  or within the insulating layer  711 , and irrespective of the cut region  705  is chosen, the insulating layer  707  protects the conductive layer  703   a  from corrosion. 
         [0036]    As shown in  FIG. 6B , the cutting may be conducted on the cut region  705  within the insulating layer  711 , producing a cut cross-section  712  along the boundary of the cut region  705  of  FIG. 6A . As shown in  FIG. 6C , the cutting may be conducted on the cut region  705  within the insulating layer  707 , producing a cut cross-section  714  along the boundary of the cut region  705  of  FIG. 6A . 
         [0037]      FIG. 7A  shows a cross-section diagram of the peripheral region  303  according to yet another embodiment of the invention. As shown in  FIG. 7A , the peripheral region  303  comprises a substrate  801  having a chip bonding region  305  and a fringe circuit region  307 . Conductive layers  803   a  and  803   b  are disposed on the chip bonding region  305  and the fringe circuit region  307  respectively. An insulating layer  807  is formed on the substrate  801  between the conductive layers  803   a  and  803   b  and covers opposite sidewalls  803   c  thereof. The insulating layer  807  may be oxide or nitride. Referring to  FIG. 7A , the insulating layer  807  also may cover part of the top surface of the conductive layer  803   a  and  803   b , separating the conductive layer thereon from the conductive layer  803   a  and  803   b . A conductive layer  808  is disposed on the insulating layer  807 . An insulating layer  810  is formed on the conductive layer  808  with openings  810   a  exposing the top surfaces thereof. Two conductive layers  809   a  and  809   b  are then used to connect conductive layers  803   a ,  808 , and  803   b  through the openings  810   a . The conductive layer  809   a  is formed to cover the conductive layer  803   a , the insulating layer  810 , the exposed conductive layer  808 , electrically connecting the conductive layers  803   a  and  808 . The conductive layer  809   b  is formed to cover part of the insulating layer  811 , the exposed conductive layer  808  and the conductive layer  803   b . Note that the conductive  809   a  and  809   b  are spaced with the exposed portion of the insulating layer  811  serving later as a cut region. The conductive layer  809   a  and  809   b  may be a transparent conductive material, such as ITO, IZO, AZO, or CTO. By the formation of the conductive layers  809   a  and  809   b , the chip bonding region  305  and the fringe circuit region  307  can be electrically connected. After cell process, the fringe circuit region  307  is removed by cutting through the cut region  805  within the insulating layer  811  and the conductive layer  803   a  can be protected by the insulating layer  807  from corrosion. As shown in  FIG. 7B , the cutting through the cut region  805  within the insulating layer  811 , producing a cut cross-section  812  along the boundary of the cut region  805  of  FIG. 7A . 
         [0038]    Finally, while the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.