Abstract:
Embodiments of the present invention disclose operational amplifiers which demonstrate good settling behavior with minimum over-shoot or ringing for improving settling behavior. The amplifiers include one or more amplification stages connected to form a symmetric structure. The amplification stage includes a boosting amplifier, a MOS transistor and a compensation capacitor. The MOS transistor can be an NMOS transistor and a PMOS transistor. Using this scheme pole-zero doublets are rearranged in a manner to improve the transient settling response.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from Indian patent application No. 2024/DeI/2006, filed Sep. 12, 2006, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     Embodiments of the present invention relate to operational amplifiers and more specifically to gain-boosted operational amplifiers for reducing the settling time and overshoot during the transient response owing to the presence of pole-zero doublets in the amplifier transfer function.  
       BACKGROUND  
       [0003]     Speed and accuracy are the two major requirements of analog electronic circuits. Circuit optimization is again in great demand because in general optimization results in contradictory conditions. The speed and accuracy are determined by the settling behavior of the operational amplifier (Op-Amp); fast settling requires high unity gain frequency and accuracy requires a high DC gain. Need to raise the unity gain frequency leads to design of single stage amplifiers with short channel MOS transistors and high bias currents and in contradiction to this high gain requirement leads to multi stage amplifiers with large channel transistors and low bias currents.  
         [0004]     A gain boosted technique proposed in “A fast-settling CMOS operational amplifier for SC circuits with 90-db dc gain” by K. Bult and G. Geelen, IEEE Journal of Solid State Circuits, vol. 25, pp. 1379-1394, December 1990, has enabled circuit designers to exploit the advantages of single-stage amplifiers with adequate gain. But with this technique pole-zero doublets are added in the transfer function of the op-amp which does not noticeably affect the frequency response of the amplifier but which introduces a very slow settling component in the settling response which can adversely affect the accuracy of the whole device.  
         [0005]     Therefore, there is a need for an operational amplifier for reducing the settling times and overshooting during the transient response.  
       SUMMARY  
       [0006]     Embodiments of the present invention provide operational amplifiers exhibiting excellent settling behavior with minimum over-shoot or ringing.  
         [0007]     According to one embodiment of the present invention an operational amplifier for improving settling behavior which includes: 
        a first amplification stage connected to a first input port (INP) and a second input port (INM), a second amplification stage operatively coupled to said first amplification stage comprising:     a third amplification stage operatively coupled to said first amplification stage and said second amplification stage comprising:     a fourth amplification stage operatively coupled to said second amplification stage comprising:     a fifth amplification stage operatively coupled to said third amplification module and said fourth amplification stage comprising:     a sixth amplification stage operatively coupled to said fourth and fifth amplification stage.        
 
         [0013]     According to one embodiment of the present invention, the first amplification stage includes: 
        a first transistor connected to said first input port;     a second transistor operatively coupled to said first transistor connected to said second input port; and     a third transistor having its drain connected to source terminals of said first transistor, and said second transistor, a gate terminal connected to a third input port, its source terminal connected to a ground voltage.        
 
         [0017]     According to one embodiment of the present invention, the second amplification stage includes: 
        a first gain boosting module receiving a bias voltage at one of an input terminals;     a fourth transistor having a gate terminal connected to an output of said first gain boosting module, a source terminal connected to a second input of said first gain boosting module, and a drain terminal connected to a first output terminal;     a first compensation module operatively coupled to said fourth transistor and said first gain boosting module, said capacitor being connected to a node.        
 
         [0021]     According to one embodiment of the present invention, the third amplification stage includes: 
        a second gain boosting module receiving a bias voltage at one of an input terminals;     a fifth transistor having a gate terminal connected to an output of said second gain boosting module, a source terminal connected to a second input of said second gain boosting module, and a drain terminal connected to a second output terminal;     a second compensation module having a first terminal coupled to said fifth transistor and said second gain boosting module, and having a second terminal connected to said fourth transistor of said second amplification stage.        
 
         [0025]     According to one embodiment of the present invention, the fourth amplification stage includes: 
        a third gain boosting module receiving a bias voltage at one of an input terminal;     a sixth transistor having a gate terminal connected to an output of said third gain boosting module, a source terminal connected to a second input of said third gain boosting module, and a drain terminal connected to said first output terminal;     third compensation module having a first terminal coupled to said sixth transistor and said third gain boosting module, and having a second terminal connected to a node.        
 
         [0029]     According to one embodiment of the present invention, the fifth amplification stage includes: 
        a fourth gain boosting module receiving a bias voltage at one of an input terminal;     a seventh transistor having a gate terminal connected to an output of said fourth gain boosting module, a source terminal connected to a second input of said fourth gain boosting module, and a drain terminal connected to said second output terminal;     a fourth compensation module having a first terminal coupled to said seventh transistor and said fourth gain boosting module, and having a second terminal connected to said sixth transistor of said fourth amplification stage.        
 
         [0033]     According to one embodiment of the present invention, the sixth amplification stage includes: 
        an eighth transistor having its source terminal connected to a supply terminal, and its drain terminal connected to said fourth amplification stage; and     a ninth transistor having its gate connected to a gate terminal of said eighth transistor for receiving a bias voltage, having its source terminal connected to said supply terminal, and its drain terminal connected to said fifth amplification stage.        
 
         [0036]     In one embodiment, the transistors comprise a NMOS transistor and a PMOS transistor.  
         [0037]     In one embodiment, the compensation module comprises a capacitor.  
         [0038]     In one embodiment, the boosting module and compensation module are substantially matched.  
         [0039]     According to one embodiment of the present invention an operational amplifier for improving settling behavior includes: 
        a first amplification stage connected to a first input port and a second input port including: 
            a first transistor connected to the first input port;     a second transistor connected to the second input port; and     a third transistor having a drain connected to source terminals of said first transistor and said second transistor, a gate terminal connected to a third input port, and a source terminal connected to a ground voltage;    
            a second amplification stage operatively coupled to the first amplification stage comprising: 
            a first gain boosting stage receiving a first signal and a second signal;     a fourth transistor having a gate terminal connected to the first gain boosting stage, a source terminal connected to said first transistor, and a drain terminal connected to a first output port;     a fifth transistor having a gate terminal connected to the first gain boosting stage, a source terminal connected to said second transistor, and a drain terminal connected to a second output port; 
                a first capacitor and a second capacitor operatively coupled with the first gain boosting stage;    
               
            a third amplification stage operatively coupled to the second amplification stage comprising: 
            a second gain boosting stage receiving a third signal and a fourth signal;     a sixth transistor having a gate terminal connected to the second gain boosting stage, a drain terminal connected to said fourth transistor through the first output port, and a source terminal connected to an input terminal of the second gain boosting stage;     a seventh transistor having a gate terminal connected to the second gain boosting stage, a drain terminal connected to said fifth transistor through the second output port, and a source terminal connected to the second gain boosting stage; 
                a third capacitor and a fourth capacitor operatively coupled to the second gain boosting stage;    
               
            a fourth amplification stage operatively coupled to the third amplification stage comprising: 
            an eighth transistor having a source terminal connected to a supply terminal, and a drain terminal connected to said third amplification stage; and     a ninth transistor having a gate connected to a gate terminal of said eighth transistor for receiving a bias voltage, a source terminal connected to said supply terminal, and a drain terminal connected to said third amplification stage.    
               
 
         [0057]     In one embodiment, the transistors comprise NMOS transistors and PMOS transistors.  
         [0058]     An embodiment of the present invention further provides a method of providing an improved settling behavior through an operational amplifier including: 
        providing a first amplification stage including a first transistor having a gate coupled to receive a first input signal, a second transistor having a gate coupled to receive a second input signal, and a third transistor coupled to sources of the first and second transistors for receiving a first supply voltage;     providing a second amplification stage including a first gain boosting module receiving a bias voltage at one of an input terminals, a fourth transistor having a gate coupled to an output of said boost module, a source terminal connected to a second input of said gain boosting module, and a drain terminal connected to a first output terminal, a first compensation module operatively coupled to said fourth transistor and said gain boosting module;     providing a third amplification stage including a second gain boosting module receiving the bias voltage at one of an input terminals, a fifth transistor having a gate coupled to an output of said boosting module, a source terminal connected to a second input of said gain boosting module, and a drain terminal connected to a second output terminal, a second compensation module operatively coupled to said fourth transistor and said second gain boosting module;     providing a fourth amplification stage including a third gain boosting module receiving a bias voltage at one of an input terminals, a sixth transistor having a gate coupled to an output of said third boosting module, a source terminal connected to a second input of said third gain boosting module, and a drain terminal connected to the first output terminal, a third compensation module operatively coupled to said sixth transistor and said third gain boosting module;     providing a fifth amplification stage including a fourth gain boosting module receiving a bias voltage at one of an input terminals, a seventh transistor having a gate coupled to an output of said fourth boosting module, a source terminal connected to a second input of said fourth gain boosting module, and a drain terminal connected to the second output terminal, a fourth compensation module operatively coupled to said sixth transistor and said fourth gain boosting module; and     providing a sixth amplification stage operatively coupled to said fourth and fifth amplification stage including an eighth transistor having its source terminal connected to a supply terminal, and its drain terminal connected to said fourth amplification stage and a ninth transistor having its gate connected to a gate terminal of said eight transistor for receiving a bias voltage, having its source terminal connected to said supply terminal, and its drain terminal connected to said fifth amplification stage.       
 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0065]     The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:  
         [0066]      FIG. 1  illustrates a schematic diagram of a fully-differential gain-boosting technique according to an embodiment of the present invention.  
         [0067]      FIG. 2  illustrates a schematic diagram of a fully-differential gain-boosting technique according to an embodiment of the present invention.  
         [0068]      FIG. 3  illustrates a pole zero plot showing movement of doublets with different values of compensation capacitors.  
         [0069]      FIG. 4  illustrates an open loop gain Vs Frequency showing the improvement with embodiments of present invention.  
         [0070]      FIG. 5  illustrates Open loop Phase response Vs Frequency showing the improvement with embodiments of present invention.  
         [0071]      FIG. 6  illustrates a transient settling behavior comparison with embodiments of the present invention.  
         [0072]      FIG. 7  illustrates a comparison plot for unity gain frequency Vs compensation capacitor value. 
     
    
     DETAILED DESCRIPTION  
       [0073]     The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.  
         [0074]      FIG. 1  illustrates a schematic diagram of a fully-differential gain-boosting technique according to one embodiment of the present invention. In particular, the operational amplifier  100 , has a first input terminal INP and a second input terminal INM and a first output terminal OUTP and a second output terminal OUTM respectively connected through a first, second, third, fourth, fifth, sixth amplification branches  102 ,  104 ,  106 ,  108 ,  110 , and  112  respectively and these are connected to each other so as to form a symmetrical circuit.  
         [0075]     In detail first amplification branch  102  includes one input NMOS transistor pair M 0 , M 1  with gate terminals connected to input ports INP, INM respectively and having source terminals connected together with a drain terminal of another NMOS transistor M 8  whose gate terminal is connected to an input port VB 4  and having a source terminal connected to a second supply terminal AGND.  
         [0076]     The amplification branches  104 - 112  include transistors such as  114 A,  114 B,  114 C,  114 D. The transistors  114 A,  114 B,  114 C,  114 D having their gate terminal connected to an output terminal of gain boosting stages such as  116 A,  116 B,  116 C,  116 D, and their source terminal connected to one input of the gain boosting stage ( 116 A,  116 B,  116 C,  116 D). The other inputs of the gain boosting stages (such as  116 A,  116 B,  116 C,  116 D) are connected to a fixed bias voltage VB 1 , VB 2 . Compensation capacitors, such as C 0 , C 1 , C 2 , C 3  having one terminal connected to a source terminal of the transistors  114 A,  114 B,  114 C,  114 D and to an input of the gain boosting stage  116 A,  116 B,  116 C,  116 D and having other terminal connected to a gate terminal of a symmetrically opposite branch&#39;s transistor (such as transistor  114 B which is opposite to transistor  114 A).  
         [0077]      FIG. 2  illustrates a schematic diagram of a fully-differential gain-boosting technique according to an embodiment of the present invention. In particular, an operational amplifier  200  is used for improving settling behavior. The operational amplifier  200  includes a first amplification stage  202 , a second amplification stage  204 , a third amplification stage  206  and a fourth amplification stage  208 . The first amplification stage  202  is connected to a first input port (INM) and a second input port (INP).  
         [0078]     The first amplification stage  202  includes a first transistor  210  connected to the first input port (INM), a second transistor  212  connected to the second input port (INP), and a third transistor  214  having a drain connected to source terminals of the first transistor  210  and the second transistor  212 , a gate terminal connected to a third input port (IBN), and a source terminal connected to a ground voltage (AGND). The second amplification stage  204  is connected to the first amplification stage  202  through the first transistor  210  and the second transistor  212 .  
         [0079]     The second amplification stage  204  includes a first gain boosting stage  228  receiving a first signal (INMNB) and a second signal (INPNB), a fourth transistor  216  having a gate terminal connected to the first gain boosting stage  228 , a source terminal connected to the first transistor  210  and a drain terminal connected to a first output port (OUTP), a fifth transistor  218  having a gate terminal connected to the first gain boosting stage  228 , a source terminal connected to the second transistor  212 , and a drain terminal connected to a second output port (OUTM), a first capacitor  232  and a second capacitor  234  connected with the first gain boosting stage  228 .  
         [0080]     The third amplification stage  206  is connected to the second amplification stage  204 . The third amplification stage  206  includes a second gain boosting stage  230  receiving a third signal (INMPB) and a fourth signal (INPPB), a sixth transistor  220  having a gate terminal connected to the second gain boosting stage  230 , a drain terminal connected to the fourth transistor  216  through the first output port (OUTP), and a source terminal connected to an input terminal of the second gain boosting stage  230 , a seventh transistor  222  having a gate terminal connected to the second gain boosting stage  230 , a drain terminal connected to the fifth transistor  218  through the second output port (OUTM), and a source terminal connected to the second gain boosting stage  230 , a third capacitor  236  and a fourth capacitor  238  connected to the second gain boosting stage  230 .  
         [0081]     The fourth amplification stage  208  is connected to the third amplification stage  206 . The fourth amplification stage  208  include an eighth transistor  224  having a source terminal connected to a supply terminal (AVDD), and a drain terminal connected to the third amplification stage  206 , and a ninth transistor  226  having a gate connected to a gate terminal of the eighth transistor  224  for receiving a bias voltage (CMP), a source terminal connected to the supply terminal (AVDD), and a drain terminal connected to the third amplification stage  206 . The transistors can be NMOS transistors and PMOS transistors.  
         [0082]     In greater detail the drain terminals of the NMOS transistors M 0 , M 1  of the amplification branch  102  are connected to the source terminals of the NMOS transistors  114 A,  114 B of amplification branches  104  and  106  respectively and the drain terminals of the transistors  114 A,  114 B are connected to the output terminals OUTP, OUTM. The drain terminals of PMOS transistors  114 C,  114 D of the amplification branches  108  and  110  and the source terminals of the transistors  114 C,  114 D are connected to the PMOS transistors M 6 , M 7  of the amplification branch  112  and gate terminals of the transistors M 6 , M 7  are connected together to a bias voltage VB 3  and the source terminals are connected to a first supply terminal AVDD which supplies a higher supply voltage. The presence of compensation capacitors C 0 , C 1 , C 2 , and C 3  substantially minimizes the effects due to pole-zero doublets resulting from a gain boosting.  
         [0083]     A technique referred to as “capacitive neutralization” can be used to reduce a component of input capacitance of the op-amp due to the Miller effect, as described in Paul R. Gray, et al. “Neutralization”,  Analysis and design of analog integrated circuits,  4 th  ed., pp 849-850, which is incorporated herein by reference.  
         [0084]     Considering the amplification branch  104 , because of the symmetrical structure of the op-amp  100 , the consideration that will be proposed may also be extended to the other amplification branches  106 - 110 .  
         [0085]     Present scheme attempts to reduce the capacitance at node  118 , simultaneously do not help in fine tuning boosters with a capacitor at node  120 . “ A New Modeling and Optimization of Gain - Boosting Amplifier for High - Speed and Low - Voltage Applications ”, M. M. Ahmadi,  IEEE Transaction on circuits and systems II , Volume 53, Issue 3, March 2006, Pages 169-173, which is incorporated herein by reference, has detailed gain expressions and the effect of node  118  capacitance on the open loop gain and shows clearly that a second order component of remainder has coefficient as node  118  capacitance.  
         [0086]     The computation of the total capacitance at node  118  is done as following:  
         [0087]     C gs  is gate to source capacitance of transistor M 2 , C gd  is gate to drain capacitance of transistor M 0 , g m0  is a transconductance of the transistor M 0 , r 9  is an impedance at node  118 , A b  is booster amplifier (G 0 ) gain and C 0  is a compensation capacitance of the compensation module C 0  and C ib  is capacitance at an input of booster.  
         [0088]     Total capacitance at node  118  is composed of Miller capacitance of transistor MO≈[(C gd ·g m0 *r 9 )/(1+g m0 *r 9 )].  
         [0089]     Input capacitance of a booster amplifier G 0 ≈C ib .  
         [0090]     Miller capacitance from transistor M 2  and the booster amplifier G 0 ≈[(1+Ab)*Cgs].  
         [0091]     Miller capacitance of the capacitance C 0 ≈(1−Ab)*C 0  (Ab is the approximate gain between node  118  and  120 ). 
 
Total capacitance is given by ≈[( C   gd   *g   m0   *r   9 )/(1 +g   m0   *r   9 )]+ C   ib +(1 +Ab )* C   gs +(1 −Ab )* C 0  (1). 
 
         [0092]     Equation 1 shows that the capacitance at node  118  can be reduced by changing the values of C 0 .  
         [0093]     This capacitance reduction will result in movement (out of application range) of non dominant poles associated with the capacitance of node  118  thus improvement in unity gain bandwidth which is clearly visible from  FIG. 3 .  FIG. 3  shows the unity gain bandwidth of the op-amp as a function of compensation capacitor value.  
         [0094]     Gain and phase plots (Bode diagrams) showed in  FIG. 4  and  FIG. 5  also show improvement. In general more uniform is gain and phase plots better is the settling behavior of the op-amp.  
         [0095]     Pole zero plots shown in  FIG. 6  show movement of non dominant poles as lines  5   b  and  5   c  and curve  5   a  shows the movement of doublet associated with the gate capacitance of the transistor  114 A.  FIG. 7  clearly shows the behavior of the output voltage with time and different values of the compensation capacitance.  
         [0096]     Embodiments of the present invention therefore allow the use of gain boosting technique, avoiding the problems linked with the presence of pole-zero doublets in the bandwidth of operational amplifier  100 .  
         [0097]     Embodiments of the present invention offer various advantages. First, a first order settling behavior of an operational amplifier is achieved. Second, the novel circuit provides an improvement in the open loop bandwidth that makes settling faster. Thirdly, the novel circuit provides inherent booster compensation. Fourth the novel circuit provides immunity to small changes; because of process corners in capacitor values. Fifth, the novel circuit is an elegant compensation scheme with a wide range of application.  
         [0098]     Operational amplifiers including CMFB modules according to embodiments of the present invention may be utilized in a variety of different types of electronic circuits and systems, such as portable devices like cell phones and personal digital assistants (PDAs), as well as in computer systems, communications and control systems, and so on.  
         [0099]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.