Abstract:
A method and system for automatically producing clock signals for sampling data signals at different data rates via a phase locked loop, wherein in a synchronization process by means of the phase locked loop, a data signal is sampled successively using a clock signal at different frequencies, which are associated with different transmission protocols, and is checked for the presence of protocol identification information associated with the selected clock signal, until protocol identification information is detected such that the frequency resolution of the phase locked loop is advantageously increased, and the synchronization of the clock signal to the data signal is improved.

Description:
BACKGROUND OF THE INVENTION 
   The high level of transparency of optical networks with regard to data transmission rates and the use of different transmission methods and transmission protocols for the transmission of digital information (for example, the Synchronous Digital Hierarchy SDH, Gigabit-Ethernet, Fiber Channel) requires future devices for data regeneration and for reproduction of the amplitude, flank and clock of a transmitted digital data signal or data stream—also referred to as “3R data regeneration”. 
   Apparatuses for producing a clock signal from a digital data stream or from a data signal stream are known. Phase/frequency control loops or phase locked loops are frequently used for clock recovery and include, for example, a phase discriminator, a frequency discriminator, a loop filter, voltage controlled oscillators (also referred to as VCOs) and variable digital frequency dividers. The function of phase locked loops for clock recovery from a digital data stream and for sampling of the digital data stream to be regenerated via a sampling flipflop are sufficiently well known to those skilled in the art, such that their method of operation will not be described in further detail. 
   Various methods for determining the data transmission rate of the digital data stream are used to preset the phase locked loop. All the methods used, in particular, in wide area networks or WAN communications networks are based on more or less exactly determining the statistically distributed flank changes in the data stream within a defined observation time period. Conclusions can be drawn on the actual data transmission rate from the number of flank changes identified. These methods are also referred to as flank density analyses. Apart from the described flank density analysis, period duration measurements of individual bits are also used for low transmission rates. 
   By way of example, Laid-Open Specification DE 197 04 299 A1 describes an apparatus for producing a clock signal from a data signal, and a bit rate identification device for determining the bit rate of the incoming data signal. The apparatus includes a phase/frequency control device and a frequency divider device which is arranged in the feedback part of the phase/frequency control device and can be switched via a data word. The switchable frequency divider device is connected to the bit rate identification device, to which the digital data stream and at least one reference frequency signal can be supplied. The bit rate identification device provides a bit-rate-dependent data word as a function of the applied reference frequency signal and the digital data stream passed to it. This is then supplied to the frequency divider device arranged in the phase/frequency control device. The described apparatus for producing a clock signal from a digital data signal or data stream has the disadvantage that the resolution of the identification circuit is highly limited; that is, digital data stream transmission rates which differ by less than a factor of 4 cannot be distinguished reliably in this way. A further disadvantage is the risk of false synchronization to side lines in the frequency spectrum during the transmission of certain data contents, for example, when transmitting AIS information in SDH signals (Synchronous Digital Hierarchy). 
   The present invention is, therefore, directed toward improving the production of a clock signal from a transmitted digital data signal during a synchronization process and, in particular, the synchronization of the clock signal to the incoming digital data signal. 
   SUMMARY OF THE INVENTION 
   The method according to the present invention provides for automatic production of clock signals for sampling data signals at different data rates via a phase locked loop. A major aspect of the method according to the present invention is that, during a synchronization process, the data signal is sampled successively using a clock signal at different frequencies, which are associated with different transmission protocols, and is checked for the presence of protocol identification information associated with the selected clock signal, until protocol identification information is detected. 
   A major advantage of the method according to the present invention is that the link between the detection of the transmission rate of the transmitted digital data signal and the detection of the transmission protocol that is matched to the frequency of the digital data signal or of the clock signal that is produced avoids false synchronization of the clock signal that is produced to side lines, harmonics and subharmonics of the transmission frequency or transmission rate of the data signal. The method according to the present invention also makes it possible to distinguish reliably between transmission rates that are arranged adjacent in the frequency domain, for example, distinguishing between “Gigabit-Ethernet” at a transmission rate of 1.25 Gbit/s and “Fiber Channel” at a transmission rate of 1.064 Gbit/s. A further advantage of the method according to the present invention is that it allows the transmission rate to be set automatically to “3R data regeneration” for frame-oriented transmission methods, and automatic identification of the respective transmission protocol. In future optical communication networks, the method according to the present invention will allow not only pure wavelength conversion via flexible “3R data regeneration”, but also analysis of the respectively transmitted digital data signals or data streams, for example, for the preprocessing of statistics, in order to provide network planning, or for volume-dependent billing. 
   Additional features and advantages of the present invention are described in, and will be apparent from, the following Detailed Description of the Invention and the Figures. 

   
     BRIEF DESCRIPTION OF THE FIGURES 
       FIG. 1  shows a circuit arrangement for producing a clock signal, according to the present invention, from a transmitted digital data stream. 
       FIG. 2  shows an example of a tabular representation of the binary information which is required to carry out the method according to the present invention and is stored in a memory in the circuit arrangement. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  uses a block diagram to show an exemplary embodiment of a circuit arrangement for producing a clock signal ts from a digital data signal or data stream ds passed to it. The circuit arrangement illustrated in  FIG. 1  is subdivided into two functional circuit units PLL, RD, which are each represented by a rectangle with a dashed-dotted outline. The first functional circuit unit includes a phase/frequency control device (PLL), which is generally known to those skilled in the art and is also referred to as a phase locked loop or PLL circuit. The second circuit unit includes a frame identification RD, which is connected to the phase/frequency control device (PLL) and is also referred to in the following text as frame detector. 
   A digital data stream ds transmitted with the aid of a transmission protocol is passed to one input ET of the phase/frequency control device PLL and is passed on to an input EF 1  of a sampling flipflop AFF. In the exemplary embodiment, it is assumed that the data stream ds is transmitted in accordance with the Synchronous Digital Hierarchy SDH. The Synchronous Digital Hierarchy is based on synchronous transmission of user information using synchronous transport modules (also referred to as STM) with a standard structure. The basic transport module is the STM-1 frame, with a data transmission rate of 155 Mbit/s. Each STM-1 frame includes a matrix of 9 rows each having 270 data octets. The frame has a repetition frequency of 125 μs, and the transmission is carried out at a bit rate of 155.520 Mbit/s. The STM-1 frame is inserted into a payload and an overhead, with the first 9 octets in all 9 rows containing the overhead, and the remaining columns containing the payload. The overhead contains information which is required to operate SDH systems, and these are also referred to as section overheads (SOH) and are transported in the SOH areas of the overhead. The SOH areas contain, for example, the A1 and A2 bytes, which are known to those skilled in the art, and which each represent frame identification information. 
   The data input ET of the phase/frequency control device PLL is at the same time connected to a first input EP of a discriminator unit DE. A reference signal f Ref  at a reference frequency is passed to a second input EF 2  of the discriminator unit DE. The discriminator unit DE is functionally subdivided into two components, a phase discriminator PD and a frequency window discriminator FD, each indicated by a rectangle with a dashed outline. 
   The discriminator unit DE is connected via an output AP to an input EL of a loop filter LF, which is, in turn, connected via an output AL to an input EV of a voltage controlled oscillator VCO. A first and a second variable digital frequency divider T 1 ,T 2  is each connected via an input (ET 1 , ET 2 ) to an output AV of the voltage controlled oscillator VCO. The first digital frequency divider T 1  is connected to a clock input CLK of the phase discriminator PD, and the second digital frequency divider T 2  is connected to a divider input ETF of the frequency window discriminator FD, in each case via an output AT 2 . The described discriminator unit DE, including a phase window discriminator PD and a frequency window discriminator FD, as well as the loop filter LF, the voltage controlled oscillator VCO and the two variable digital frequency dividers T 1 , T 2  are functional components of a generally known phase locked loop, whose function for recovery of the clock from the data stream ds passed to it in addition to the sampling of the data stream ds to be regenerated in conjunction with the sampling flipflop AFF are sufficiently well known to those skilled in the art, and will not be described in any more detail in the following text. 
   The phase/frequency control device PLL has a clock output CA which is connected to the output AT 1  of the first frequency divider T 1 , and to which the clock signal ts which is produced is passed. The output AT 1  of the first frequency divider T 1  is, in turn, connected to a clock input CLK of the sampling flipflop AFF. The sampling flipflop AFF is connected via an output AF to a data output ATP of the phase/frequency control device PLL, to which the data stream cds, regenerated via the sampling flipflop AFF, is passed. Furthermore, the output AF of the sampling flipflop AFF is connected to an input ESR of a shift register SR arranged in the frame identification unit RD. The shift register SR has a clock input CLK which is connected to the output AT 1  of the first frequency divider T 1 . 
   Furthermore, a memory MEM is arranged in the frame identification unit RD and is connected via a connecting line to a control unit STRG arranged in the frame identification unit RD. A table tab, illustrated in  FIG. 2 , is stored in the memory MEM. The illustrated table tab has a number of table entries te 1  . . . n, with each table entry te 1  . . . n having a respectively associated, defined transmission protocol. Each table entry te 1  . . . n is used to store protocol identification information PID 1  . . . n which uniquely identifies the respectively defined transmission protocol (for example, the frame identification information contained in the overhead information, in this case the A1 and A2 bytes) control loop control information PLL_WORD 1  . . . n for setting the phase/frequency control device PLL to the transmission rate to be expected for the data stream ds, and further overhead control information CNT_WD 1  . . . n for optional protocol-specific evaluation and processing of the overhead information arranged in the respective data packets or data frames of the data stream ds, cds. The overhead control information CNT_WD 1  . . . n can be used to evaluate, and if necessary to recalculate, for example, the B1 byte contained in the overhead information in a data stream transmitter using the SDH transmission method. 
   The control unit STRG is connected via a data bus DB having a number of data lines to a memory register MR, which is arranged in the frame identification unit RD and to which protocol identification information PID 1  . . . n which is stored in the memory MEM can be transmitted and stored therein, indicated by a rectangle with a dashed outline. The shift register SR and the memory register MR are connected via respective outputs AS, AM and a respective number of data lines DL 1  . . . n to corresponding inputs EC of a comparator unit COMP. The comparator COMP has comparison capabilities which are used to compare the binary information or data words applied to the inputs EC, and the comparison result is transmitted in the form of a data signal int via an output AC and a signaling line SCS to an input ESG of the control unit STRG. 
   The data bus DB is also used to connect the control unit STRG to a register unit REG, which is connected via first outputs A 1  and via first control lines SL 1  to a control input S of the frequency window discriminator FD, via second outputs A 2  and via second control lines SL 2  to corresponding control inputs S of the second controllable frequency divider T 2 , via third outputs A 3  and third control lines SL 3  to corresponding inputs S of the first controllable frequency divider T 1 , and via fourth outputs A 4  and fourth control lines SL 4  to corresponding inputs S of the voltage controlled oscillator VCO. The register unit REG has one or more memory registers ( FIG. 1  shows only one memory register, in the form of a rectangle with a dashed outline) in each of which the control device control information PLL_WORD 1  . . . n stored in the memory MEM, or control words or binary information derived from such control information, can be stored, via which the circuitry components, in this case FD, PD, LF, VCO, T 1  and T 2 , arranged in the phase/frequency control device PLL can be controlled. Alternatively, analog signals can be derived from the control words stored in the register REG, and can be supplied to the circuitry components. 
   The frame identification unit RD also has a control/monitoring interface SS, which is connected to the control unit STRG via a connecting line. 
   The method, which can be implemented via the circuit arrangement illustrated in  FIG. 1 , for producing a clock signal ts from the digital data stream ds transmitted with the aid of a transmission protocol optionally allows both the manual and automatic selection of a transmission protocol, and corresponding presetting of a data transmission rate matched to the selected transmission protocol. The method for producing the clock signal ts on the basis of manual selection, also referred to as a manual operating mode, and on the basis of automatic selection, also referred to as an automatic operating mode—of the transmission protocol and of the associated data transmission rate is explained in more detail in the following text with reference to the circuit arrangement illustrated in  FIG. 1 . For the further exemplary embodiment, it is assumed that the digital data stream ds is transmitted with the aid of a frame-oriented transmission protocol, in this case STM-1, to the input ET of the phase/frequency control device (PLL) and is passed on to the data input EF of the sampling flipflop AFF. 
   Manual Operating Mode 
   During manual operation of the circuit arrangement, the transmission protocol with which the digital data stream ds is transmitted to the data input EF of the sampling flipflop AFF is known. On the basis of the knowledge of the transmission protocol, the control unit STRG arranged in the frame identification unit RD selects the first table entry te 1  that is associated with the STM-1 transmission protocol in the table tab and reads the corresponding control loop control information, in this case PLL_WORD 1 , from the memory MEM, and transmits this via the data bus DB to the corresponding register or registers in the register unit REG. Alternatively, further control information can be derived from the transmitted control loop control information PLL_WORD, and can be stored in the corresponding register in the register unit REG. According to a further embodiment (not illustrated) a number of control words or control device control information items associated with the STM-1 transmission protocol also can be stored in the respective table entries te 1  . . . n in the table tab (not illustrated in  FIG. 2 ), which are transmitted via the data bus DB to corresponding registers in the register unit REG. The transmission of the control loop control information PLL_WORD 1  . . . n stored in the memory MEM allows the circuitry components VCO, T 1 , T 2 , FD, PD, LF to be preset to the corresponding data transmission rate of the incoming digital data stream ds, in this case 155 Mbit/s. Furthermore, the control unit STRG reads the protocol identification information, in this case PID 1 , associated with the selected transmission protocol, in this case STM-1, from the corresponding table entry te 1  in the table tab, and transmits this via the data bus DB to the memory register MR, in which it is temporarily stored. In this exemplary embodiment, the frame identification word which is specific for the STM-1 transmission protocol and includes the last A1 and the first A2 byte of the overhead information is transmitted as the protocol identification information PID 1  to the memory register REG. 
   As already explained, the phase locked loop which is arranged in the phase/frequency control device PLL is matched to the data transmission rate of the incoming digital data stream ds via the control loop control information PLL_WORD 1  stored in the register unit REG. By way of example, the transmission of appropriate control information si 2 , si 3  via the control lines SL 2  and SL 3  sets the controllable frequency dividers T 1 , T 2  such that the frequency of the signal delivered from the voltage controlled oscillator VCO is divided as appropriate for matching of the optimum operating point of the phase discriminator PD and of the frequency window discriminator FD. Additional control information, in this case si 4 , transmitted via the fourth control line SL 4  is used to provide any possibly required presetting or switching of the voltage controlled oscillator VCO. According to one alternative embodiment of the circuit arrangement, a number of voltage controlled oscillators VCO can be arranged in the phase/frequency control device PLL, in which case one voltage controlled oscillator VCO, which is matched to the data transmission rate of the incoming digital data stream ds, in each can case be selected with the aid of the fourth control signal si 4 . 
   According to a further embodiment of the circuit arrangement, which is not illustrated in  FIG. 1 , the loop filter LF arranged in the phase/frequency control device PLL is likewise controlled as a function of the control loop control information PLL_WORD 1  . . . n stored in the register unit REG. 
   The digital data stream cds sampled with the aid of the recovered clock signal ts is read to the shift register SR, that is to say the shift register SR contains the data bits read with the aid of the recovered clock ts. Alternatively, the data stream ds which is applied to the input ET but is not sampled also can be read to the shift register SR, which is clocked by the clock signal ts, via a connecting line, indicated by a dashed connecting line in  FIG. 1 . 
   The bit sequence read to the shift register SR is permanently compared by the comparator unit COMP with the protocol identification information, in this case pid 1 , temporarily stored in the memory register MR. If the comparator unit COMP finds a match or a partial match between the digital bit sequence that is read and the protocol identification information pid 1 , a corresponding control signal int is generated in the comparator unit COMP, and is transmitted via the control line SCS to the control unit STRG. The transmission of the control information int to the control unit STRG indicates the identification of the selected transmission protocol, in this case STM 1 , and the setting of the associated data transmission rate for the phase/frequency control device PLL. 
   In order to improve the synchronization of the clock signal ts that is produced to the incoming digital data stream ds, according to a further embodiment that is not illustrated, the control unit STRG checks whether the protocol identification information, in this case pid 1 , is identified more than once, for example three times, in a cycle time which is specific for the selected transmission protocol. If the transmission protocol being used resulting the frame sequence being asynchronous, for example when using the Gigabit-Ethernet transmission protocol, this embodiment allows the pause pattern, or “Interframe Gap”, to be analyzed. 
   When the selected or expected protocol identification information pid 1  is identified in the sampled data stream cds, the start of data transmission can be recorded via the control unit STRG. If there are no periodically produced data frames, for example when using the STM-1 transmission protocol, it is advantageously possible in conjunction with further parameters, for example loss of the signal (LOS) or optical level, to deduce that there is a fault or that this is the end of transmission. In the situation where the phase locked loop which is arranged in the phase/frequency control device PLL becomes synchronized to an adjacent transmission rate, for example PDH at 140 Mbit/s, the analysis of the incoming data frames according to the present invention makes it possible to identify and record the fact that the preselected transmission protocol is not being used and/or has not been identified. If, for example, the preselected transmission protocol is not identified, termination of the connection can be initiated automatically. 
   Automatic Operation 
   When using the circuit arrangement illustrated in  FIG. 1  in the automatic operating mode, the clock signal ts which is produced by the phase/frequency control device PLL should be synchronized without any operator action to the digital data stream arriving at the data input ET, allowing subsequent “3D data regeneration” of the digital data stream ds. For this purpose, all the transmission protocols to be expected are stored in the table tab arranged in the memory MEM, together with the associated protocol-specific protocol identification information pid 1  . . . n and the associated control device control information PLL_WORD 1  . . . n for setting the phase/frequency control device PLL to the data transmission rate to be expected. When the automatic operating mode is activated, this causes the control unit STRG to transmit the protocol identification information PID 1  . . . n and control device control information PLL_WORD 1  . . . n arranged in the table tab of the memory MEM step-by-step in the described manner and cyclically to the register unit REG and, respectively, to the memory register MR, until the comparator unit COMP identifies a defined transmission protocol stored in the table tab, and signals this to the control unit STRG. When a transmission protocol stored in the memory MEM is identified, the cyclic processing of the table tab arranged in the memory MEM is ended. If the currently selected transmission protocol is not identified, the described, successive run through the stored protocol identification information PID 1  . . . n and control device control information PLL_WORD 1  . . . n is carried out once again, after a predefined, protocol-specific delay. 
   The automatic protocol search sequence can be enabled only by an operator action. According to a further advantageous embodiment, selective enabling can be carried out by selection of the transmission protocols stored in the table tab via an appropriate identifier in the respective table entries te 1  . . . n. 
   In order to further improve the synchronization monitoring, the current state of the phase/frequency control device PLL can be detected with the aid of a generally known lock detector (not illustrated) which is also arranged in the phase/frequency control device PLL, and can be signaled to the control unit STRG. 
   The control/monitoring interface SS which is connected to the control unit STRG allows the table entries te 1  . . . n which are stored in the memory MEM to be processed and updated and, in addition to the monitoring of the respectively transmitted transmission protocols, allows the enabling of specific transmission protocols to be controlled. The control/monitoring interface SS also makes it possible to switch between the described manual or automatic operating modes. The control/monitoring interface SS can, for example, be connected to a higher-level network administration unit or network management unit so that, for example, it is possible for a network operator to monitor and to control the data transmission rate of the digital data stream ds arriving at the phase/frequency control device PLL. 
   The linking, according to the present invention, of the presetting of the data transmission rate to be expected to the phase/frequency control device PLL (which is generally known to those skilled in the art) and the checking of the transmission protocol used for transmitting the digital data stream by partial evaluation of the overhead information contained in the individual data frames avoids false synchronization of the clock signal to side lines, harmonics and subharmonics of the data transmission rate. The method according to the present invention also makes it possible to distinguish reliably between data transmission rates which are separated only slightly, by evaluation of the various overhead information items. 
   Although the present invention has been described with reference to specific embodiments, those of skill in the art will recognize that changes may be made thereto without departing from the spirit and scope of the invention as set forth in the hereafter appended claims.