Abstract:
Techniques for interchanging positions of external terminals of an integrated circuit chip are disclosed. According to one aspect of the present invention, a chip comprises at least a pair of external terminals for communicating with other components or circuits, an internal circuit and an interchangeable unit coupled between the external terminals and the internal circuit. The interchangeable unit is configured to interchange the external terminals electronically such that the chip remains compatible in various versions involving an change of the terminals thereof, wherein the an interchangeable unit is controllable externally by a selecting pin applicable to either a high level or a low level to cause the external terminals interchanged.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to integrated circuit (IC) chip designs, and more particularly to circuits facilitating to interchange external connectors or terminals of an IC chip. 
   2. Description of Related Art 
     FIG. 1  schematically shows an IC chip configuration comprising a package and an internal circuit. Around the package, a plurality of external connectors or terminals is disposed. For explanation simplicity, only two external terminals A, B are shown in  FIG. 1 . The external terminal A is electrically connected with pin  1  of the internal circuit for transferring data between an external device and the internal circuit. Correspondingly, the external terminal B is electrically connected with pin  2  of the internal circuit for the similar purpose. 
   In the course of chip designs requiring to continuously update the design solutions, there will be different versions in a kind of chips. Different versions may result in different layouts of the external terminals in the same kind of chips. However, in some applications, the application circumstance of the chips does not change along with the versions of the chips, thereby sometimes causing an updated version of the chips to be incompatible with the original version. 
   Thus there is a need for techniques for interchanging the external terminals of chips in order to increase the compatibility of the chips. 
   SUMMARY OF THE INVENTION 
   This section is for the purpose of summarizing some aspects of the present invention and to briefly introduce some preferred embodiments. Simplifications or omissions in this section as well as in the abstract or the title of this description may be made to avoid obscuring the purpose of this section, the abstract and the title. Such simplifications or omissions are not intended to limit the scope of the present invention. 
   In general, the present invention pertains to techniques for interchanging positions of external terminals of a chip. According to one aspect of the present, an integrated circuit chip includes at least a pair of external terminals for communicating with other components or circuits, an internal circuit providing main functions of the chip, and an interchangeable unit. The interchangeable unit is provided between the terminals and the internal circuit such that the chip remains compatible in various versions involving an change of the terminals thereof, wherein the an interchangeable unit is controllable externally by a selecting pin applicable to either a high level or a low level to cause the external terminals interchanged. 
   The present invention may be implemented in many forms including a circuit, a method, or as a part of a device or system. According to one embodiment, the present invention is an integrated circuit chip. The chip comprises at least a pair of external terminals for communicating with other components or circuits, an internal circuit providing main functions of the chip, an interchangeable unit, provided between the terminals and the internal circuit, including at least first, second, third and fourth signal pins for signal transference and a selecting pin, the first and second signal pins connecting with the external terminals, the third and fourth signal pins connecting with the internal circuit, and wherein the selecting pin is controlled to cause the first signal pin to be electrically connected with the third signal pin and the second signal pin to be electrically connected with the fourth signal pin to interchange the external terminals of the chip. 
   According to another embodiment, the present invention is an integrated circuit chip that comprises at least a pair of external terminals for communicating with other components or circuits; an internal circuit providing main functions of the chip; an interchangeable unit, provided between the terminals and the internal circuit, configured to interchange the external terminals electronically such that the chip remains compatible in various versions involving an change of the terminals thereof, wherein the an interchangeable unit is controllable externally by a selecting pin applicable to either a high level or a low level to cause the external terminals interchanged. 
   One of the objects, features, and advantages of the present invention is to facilitate interchanging electronically external connectors or terminals of an IC chip. 
   Other objects, features, and advantages of the present invention will become apparent upon examining the following detailed description of an embodiment thereof, taken in conjunction with the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
       FIG. 1  is a block diagram schematically showing a conventional chip; 
       FIG. 2  is a block diagram schematically showing a chip of the present invention; 
       FIG. 3  is a diagram showing a general structure of an interchangeable unit in the chip of the present invention; 
       FIG. 4  shows one embodiment of the interchangeable unit; 
       FIGS. 5 ,  6  both are a block diagram schematically showing the chip which the one embodiment of the interchangeable unit is disposed in; and 
       FIG. 7  is a block diagram schematically showing the chip which the other embodiment of the interchangeable unit is disposed in. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The detailed description of the present invention is presented largely in terms of procedures, steps, logic blocks, processing, or other symbolic representations that directly or indirectly resemble the operations of devices or systems contemplated in the present invention. These descriptions and representations are typically used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. 
   Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams or the use of sequence numbers representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations in the invention. 
   Referring now to the drawings, in which like numerals refer to like parts throughout the several views.  FIG. 2  shows a chip  100  comprising a package  102 , an internal circuit  300  and an interchangeable unit  200  disposed between the package  102  and the internal circuit  300 . Around the package  102 , a plurality of external terminals is disposed. In  FIG. 2 , only two external terminals  100 - 1  and  100 - 2  are shown for explanation simplicity. 
   The interchangeable unit  200  is configured for interchanging positions of the external terminals  100 - 1  and  100 - 2  in some certain applications.  FIG. 3  schematically shows a general structure of the interchangeable unit  200 . The interchangeable unit  200  has one group of signal pins  200 - 1  and  200 - 2 , the other group of signal pins  200 - 3  and  2004 , and a selecting pin  200 - 5 . The value of the selecting pin  200 - 5  has two status, one is “H”(high level), the other is “L”(low level). In one embodiment, when the selecting pin  200 - 5  is set to “L”, the signal pin  200 - 1  is electrically connected with the signal pin  200 - 3  while the signal pin  200 - 2  is electrically connected with the signal pin  2004 . When the selecting pin  200 - 5  is set to “H”, the signal pin  200 - 1  is electrically connected with the signal pin  200 - 4  and the signal pin  200 - 2  is electrically connected with the signal pin  200 - 3 . 
   Depending on applications, the interchangeable unit  200  may have various different configurations.  FIG. 4  shows one embodiment of the interchangeable unit  200 . The interchangeable unit  200  comprises a pair of gates  400   a  and  400   b , each has a pair of input nodes S 1  and S 2 , an output node D and a controlling node C. The signal pin  200 - 1  is electrically connected with the input node S 2  of the gate  400   a  and the input node S 1  of the gate  400   b . The signal pin  200 - 2  is electrically connected with the input node S 1  of the gate  400   a  and the input node S 2  of the gate  400   b , respectively. The controlling nodes C of the gates  400   a  and  400   b  are electrically connected with the selecting pin  200 - 5 . The output node D of the gates  400   a  and  400   b  are electrically connected with the signal pin  200 - 4  and  200 - 3 , respectively. 
   In operation, when the selecting pin  200 - 5  is set to “L”, that means that the controlling nodes C of the gates  400   a ,  400   b  are both set to “L”. The input node S 1  of either the gate  400   a  or  400   b  is selected to be electrically connected with the output node D, as a result, the signal pin  200 - 1  is electrically connected with the signal pin  200 - 3  by the gate  400   b  and the signal pin  200 - 2  is electrically connected with the signal pin  200 - 4  by the gate  400   a . When the selecting pin  200 - 5  is set to “H”, that means that the controlling node C is “H”. The input nodes S 2  of either the gate  400   a  or  400   b  is selected to electrically connected with output node D, as a result, the signal pin  200 - 1  is electrically connected with the signal pin  200 - 4  by the gate  400   a  and the signal pin  200 - 2  is electrically connected with the signal pin  200 - 3  by the gate  400   b.    
   Referring now to  FIG. 5 , there shows a block diagram of a chip  100  employing the present invention. The chip  100  includes an internal circuit  300  that provides main functions of the chip. The external terminals  100 - 1  and  100 - 2  are electrically connected with the signal pins  200 - 1  and  200 - 2 , respectively. The signal pins  200 - 3  and  200 - 4  are electrically connected with the internal circuit  300 . It is assumed that the signal pins  200 - 1  and  200 - 2  are to receive one or more input signals. 
   When the selecting pin  200 - 5  is set to “L”, an input signal from the external terminal  100 - 1  is led to the signal pin  200 - 3  by the gate  400   b  and an input signal from the external terminal  100 - 2  is led to the signal pin  200 - 4  by the gate  400   a . When the selecting pin  200 - 5  is set to “H”, the input signal from the external terminal  100 - 1  is led to the signal pin  200 - 4  by the gate  400   a  and the input signal from the external terminal  100 - 2  is led to the signal pin  200 - 3  by the gate  400   b . Consequently, the chip  100  shown in the  FIG. 5  can be readily compatible in versions that result in changes of the terminals by employing an interchangeable unit that is controllable by a selecting pin. In one embodiment, the value of the selecting pin  200 - 5  is realized by connecting the selecting pin  200 - 5  to a power source or a grounding terminal of the chip  100 . 
   Referring now to  FIG. 6 , there shows another block diagram of a chip  100  employing the present invention. The chip  100  includes an internal circuit  300  that provides main functions of the chip. The external terminals  100 - 1  and  100 - 2  are electrically connected with the signal pins  200 - 3  and  200 - 4 , respectively. The signal pins  200 - 1  and  200 - 2  are electrically connected with the internal circuit  300 . It is assumed that the signal pins  200 - 1  and  200 - 2  are to receive one or more output signals. When the selecting pin  200 - 5  is set to “L”, an output signal from the signal pin  200 - 1  is led to the external terminal  100 - 1  by the gate  400   b  and an output signal from the signal pin  200 - 2  is led to the external terminal  100 - 2  by the gate  400   a . When the selecting pin  200 - 5  is set to “H”, the output signal from the signal pin  200 - 1  is led to the external terminal  100 - 2  by the gate  400   a  and the output signal from the signal pin  200 - 2  is led to the external terminal  100 - 1  by the gate  400   b . Consequently, the chip  100  shown in the  FIG. 6  can be readily compatible in versions that result in changes of the terminals by employing an interchangeable unit that is controllable by a selecting pin. 
   Referring now to  FIG. 7 , there shows still another block diagram of a chip  100  employing the present invention. The chip  100  includes an internal circuit  300  that provides main functions of the chip. The external terminals  100 - 1 ,  100 - 2  are electrically connected with the signal pins  200 - 1 ,  200 - 2 , respectively. The signal pins  200 - 4 ,  200 - 3  are electrically connected with the internal circuit  300 , where the signal between the external terminals  100 - 1 ,  100 - 2  and the internal circuit  300  is assumed to be one or more bidirectional signals. 
   As shown in  FIG. 7 , the interchangeable unit  200  includes two pairs of gates  400   a ,  400   b ,  400   c , and  400   d  each of which is substantially similar to that described above. The signal pin  200 - 1  is electrically connected with the input node S 2  of the gate  400   a  and the input node S 1  of the gate  400   b  by an input buffer  5  in series. The signal pin  200 - 2  is electrically connected with the input node S 1  of the gate  400   a  and the input node S 2  of the gate  400   b  by an input buffer  8  in series. The output nodes D of the gates  400   a  and  400   b  are electrically connected with the signal pins  200 - 4  and  200 - 3  by input buffers  9  and  11  in series, respectively. Accordingly, the signal pin  200 - 3  is electrically connected with the input node S 1  of the gate  400   d  and the input node S 2  of the gate  400   c  by an output buffer  12  in series. The signal pin  200 - 4  is electrically connected with the input node S 2  of the gate  400   d  and the input node S 1  of the gate  400   c  by an output buffer  10  in series. The output nodes D of the gates  400   c  and  400   d  are electrically connected with the signal pins  200 - 2  and  200 - 1  by output buffers  6 ,  7  in series, respectively. The controlling nodes C of the gates  400   a ,  400   b ,  400   c , and  400   d  are electrically connected with the selecting pin  200 - 5 . 
   When the selecting pin  200 - 5  is set to “L”, that means that the controlling nodes C of all gate are “L”, in this status, the input nodes S 1  of all gate  400  are selected to electrically connected with the output node D, thereby an input signal from the external terminal  100 - 1  is led to the signal pin  200 - 3  by the gate  400   b  and an output signal from the signal pin  200 - 3  is led to the external terminal  100 - 1  by the gate  400   d , and an input signal from the external terminal  100 - 2  is led to the signal pin  200 - 4  by the gate  400   a  and an output signal from the signal pin  200 - 4  is led to the external terminal  100 - 2  by the gate  400   c.    
   When the selecting pin  200 - 5  is set to “H”, that means that the controlling nodes C of all gate are “H”, in this status, the input nodes S 2  of all gate  400  are selected to electrically connected with the output node D, thereby the input signal from the external terminal  100 - 1  is led to the signal pin  200 - 4  by the gate  400   a  and the output signal from the signal pin  200 - 4  is led to the external terminal  100 - 1  by the gate  400   d , and the input signal from the external terminal  100 - 2  is led to the signal pin  200 - 3  by the gate  400   b  and the output signal from the signal pin  200 - 3  is led to the external terminal  100 - 2  by the gate  400   c.    
   It can be appreciated that the chip  100  shown in the  FIG. 7  can be readily compatible in versions that result in changes of the terminals by employing an interchangeable unit that is controllable by a selecting pin. 
   According to the above descriptions, it can be appreciated that one or more interchangeable units may be employed in a chip so that the positions of the external terminals can be interchanged. Hence, the compatibility of chips may be increased in view of various versions thereof. 
   The present invention has been described in sufficient details with a certain degree of particularity. It is understood to those skilled in the art that the present disclosure of embodiments has been made by way of examples only and that numerous changes in the arrangement and combination of parts may be resorted without departing from the spirit and scope of the invention as claimed. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description of embodiments.