Abstract:
A decoding apparatuses and a method utilized in an optical storage device are disclosed. The decoding apparatus includes: a level slicer for setting a plurality of adjustable boundary values to distinguish a plurality of signal regions, and outputting a set of state values in accordance with signal regions corresponding to an input value; and a Viterbi detector coupled to the level slicer for decoding a transmission data according to the state value.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present disclosure relates to decoding apparatuses and related methods, and more particularly, to decoding apparatuses and methods that correct the non-linear effect by adjusting the boundaries of signal regions of a level slicer.  
         [0003]     2. Description of the Prior Art  
         [0004]     In an optical storage system, such as a conventional optical disc drive (e.g., VCD player or DVD+/-R disc drive), data are decoded from the conventional RF signal retrieved from an optical disc. However, the RF signal may have mismatch problems due to interference caused by the system or the operating environment, such as the pick-up head drift or electronic noise, and which results in nonlinear distortion to the decoded signal so the decoded digital data stream is prone to errors. The conventional decoding operation decodes data by using a Viterbi detector. For example, the U.S. Pat. No. 6,754,160 utilizes a DC offset compensation control scheme to calculate a proper DC level compensation value to control the input value of the Viterbi detector so that the Viterbi detector decodes the data stored on the optical disc based on a best slicing level and not affected by the nonlinear distortion described previously.  
       SUMMARY OF THE INVENTION  
       [0005]     It is therefore an objective of the present disclosure to provide decoding apparatuses and associated decoding methods for use in an optical storage device. The decoding apparatuses and associated decoding methods provide a set of adjusted state values to a Viterbi detector by adjusting the signal boundaries of a level slicer. Then, the Viterbi detector decodes a transmission data according to the state values.  
         [0006]     An exemplary embodiment of a decoding apparatus in an optical storage device is disclosed comprising: a level slicer for setting at least one adjustable boundary value to distinguish a plurality of signal regions, and outputting a set of state values in accordance with a signal region corresponding to an input value; and a Viterbi detector coupled to the level slicer for decoding a transmission data according to the set of state values.  
         [0007]     An exemplary embodiment of an optical storage device is disclosed comprising: a pick-up head for emitting a laser beam and receiving reflected laser beam from an optical disc to generate an analog data signal; an analog-to-digital converter (ADC) coupled to the pick-up head for converting the analog data signal to a digital data signal; an equalizer coupled to the ADC for equalizing the digital data signal according to partial response characteristics to generate at least one input value; a level slicer for setting a plurality of adjustable boundary values to distinguish a plurality of signal regions, and outputting a set of state values in accordance with a signal region corresponding to the input value; and a Viterbi detector coupled to the level slicer for decoding a transmission data according to the set of state values.  
         [0008]     An exemplary embodiment of a decoding method for use in an optical storage device is disclosed comprising: setting a plurality of adjustable boundary values to distinguish at least one signal region, and outputting a set of state values in accordance with a signal region corresponding to an input value; and decoding a transmission data according to the set of state values.  
         [0009]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  is a block diagram of a decoding apparatus for use in an optical storage device according to a first embodiment of the present invention  
         [0011]      FIG. 2  is a distribution diagram of output levels in the case where the partial response of the equalizer of  FIG. 1  is PR[1 2 1] model and the channel has no non-linear distortion.  
         [0012]      FIG. 3  is a distribution diagram of output levels in the case where the partial response of the equalizer of  FIG. 1  is PR[1 2 1] model and the channel has non-linear distortion.  
         [0013]      FIG. 4  is a block diagram of a boundary value calibration module of the level slicer of  FIG. 1  according to an exemplary embodiment.  
         [0014]      FIG. 5  is a block diagram of a decoding apparatus for use in an optical storage device according to a second embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0015]     Please refer to  FIG. 1 , which shows a block diagram of a decoding apparatus  95  for use in an optical storage device  10  according to a first embodiment of the present invention. The optical storage device  10  comprises a pick-up head  15 , a pre-equalizer  20 , an ADC  30 , a sampling rate converter  40 , an equalizer  60 , an equalizer controller  50 , a sampling rate controller  70 , and the decoding apparatus  95 . As illustrated in  FIG. 1 , the decoding apparatus  95  comprises a level slicer  80  and a Viterbi detector  90 . The pick-up head  15  emits a laser beam to read data recorded on an optical disc and converts the reflected laser beam into an analog signal, i.e., the RF signal described previously. The analog signal is amplified by the pre-equalizer  20  and then converted into a digital signal by the ADC  30 . Since the sampling rate adopted by the ADC  30  to perform the analog-to-digital conversion differs from the channel bit rate, the digital signal generated by the ADC  30  needs to be adjusted by sampling rate converter  40  so that the sampling rate and the channel bit rate can be synchronous. Then, the equalizer  60  processes the synchronized signal to generate an input value S 1  that satisfies partial response condition. The input value S 1  is applied to the equalizer controller  50 , the sampling rate controller  70 , and the level slicer  80 . The equalizer controller  50  and the sampling rate controller  70  respectively adjust the equalizer controller  50  and the sampling rate controller  70  by using feedback control means. The level slicer  80  sets a plurality of adjustable boundary values according to the results of a number of test input values after they are passed through a same channel to distinguish a plurality of signal regions. The level slicer  80  then outputs a state value R according to the signal region corresponding to the input value S I . Finally, the Viterbi detector  90  is able to decode a transmission data D recorded on the optical disc in accordance with the state value R.  
         [0016]     Note that the sampling rate converter  40  is employed by the foregoing embodiment to synchronize the sampling rate and the channel bit rate. This is merely an example rather than a restriction of the practical implementations. For example, the sampling rate and the channel bit rate can be synchronized by utilizing a VCO to control the ADC  30 .  
         [0017]     Hereinafter, the operations of the decoding apparatus  95  will be described in more detail. Please refer to  FIG. 2 , which shows a distribution diagram of output levels in the case where the partial response of the equalizer  60  is PR[1 2 1] model and the channel has no non-linear distortion. The equalizer  60  shown in  FIG. 1  can be adjusted by using conventional art, such as the least-mean-square (LMS) algorithm. The partial response should be the PR[1 2 1] model so that the level of the input value S 1  generated by the equalizer  60  can be divided into four signal regions as shown in  FIG. 2 . In  FIG. 2 , the input value S 1  is divided into four signal regions by three boundary values SI 1 ˜S 13 . For no non-linear distortion caused by the mismatch channel effect, the four signal regions are symmetrical with respect to the origin and the boundary values SI 1 ˜S 13  are located at −0.4, 0, and 0.4, respectively. In practice, however, the non-linear distortion is unavoidable.  
         [0018]     Please refer to  FIG. 3 , which shows a distribution diagram of output levels in the case where the partial response of the equalizer  60  is PR[1 2 1] model and the channel has non-linear distortion. Due to the effect of the non-linear distortion, each of the four signal regions shifts toward right-hand side or left-hand side, and the interval between signal regions varies. Obviously, if SI 1 ˜S 13  are employed as the boundary values, the input value S 1  may be erroneously determined to locate within an incorrect signal region. The level slicer  80  outputs the state value R according to the signal region of each input value, and the Viterbi detector  90  decodes the transmission data D recorded on the optical disc based on the sate value R. Accordingly, if the input value S 1  is erroneously determined to locate within an incorrect signal region, the transmission data D may be decoded erroneously. Please note that the number of boundary values and signal regions can be adjusted based on the design requirement and not limited to that illustrated in the foregoing embodiment.  
         [0019]     In this case, the level slicer  80  comprises a plurality of boundary value calibration modules for calibrating the plurality of boundary values, respectively. Hereinafter, the calibration of the boundary value SI 1  is taken as an example to illustrate the operations of the boundary value calibration module. Please refer to  FIG. 4 , which depicts a block diagram of a boundary value calibration module  110  of the level slicer  80  according to an exemplary embodiment. The boundary value calibration module  110  comprises a comparator  120 , an adjusting circuit  130 , a memory unit  140 , and a switch  150 . The memory unit  140  stores an initial boundary value SIi 1  and predetermined adjusting values C 11  and C 12 . When the boundary value calibration module  110  starts to calibrate the boundary value SI 1 , the switch  150  couples the comparator  120  to the memory unit  140  and disconnects the comparator  120  and the adjusting circuit  130 . Thus, the comparator  120  reads the initial boundary value SIi 1  from the memory unit  140 , and compares a given test input value S IT   1  with the initial boundary value SIi 1  to obtain a comparison result. The comparison result is then applied into the adjusting circuit  130 . The adjusting circuit  130  reads the predetermined adjusting values C 11  and C 12  stored in the memory unit  140 , and selects one of the predetermined adjusting values C 11  and C 12  to adjust the initial boundary value SIi 1  so as to obtain the boundary value SI 1  .  
         [0020]     For example, if the test input value S IT   1  is greater than or equal to the initial boundary value SIi 1 , the adjusting circuit  130  adds the predetermined adjusting value C 11  to the initial boundary value SIi 1  to obtain the boundary value SI 1  . If the test input value S IT   1  is less than the initial boundary value SIi 1 , the adjusting circuit  130  subtracts the predetermined adjusting value C 12  from the initial boundary value SIi 1  to obtain the boundary value SI 1  . At that time, the switch  150  switches the comparator  120  to the adjusting circuit  130  from the memory unit  140 . The adjusted boundary value SI 1  is feedback to the comparator  120  to replace the initial boundary value SIi 1  . Then, the boundary value SI 1  is adjusted in the same way until the difference between the test input value S IT   1  and the boundary value SI 1  is less than a threshold. The foregoing descriptions illustrate the calibration of the boundary value SI 1  . In this embodiment, the other boundary values, such as SI 2  and SI 3 , are adjusted in the same way as the boundary value SI 1  . In other words, if the level slicer  80  has n boundary values, the level slicer  80  comprises n boundary value calibration modules.  
         [0021]     Note that the initial boundary value SIi 1  and the predetermined adjusting values C 11  and C 12  are adjustable. In order to make SI 1  lie between the maximum signal region and the second maximum signal region, the ratio of the predetermined adjusting value C 11  to the predetermined adjusting value C 12  can be determined based on statistics information. The adjustment of each boundary value is performed based on the statistic distribution of the boundary value independently. Therefore, when channel mismatch occurs, those boundary values would be individually adjusted to a proper value instead of compensating all the boundary values with a same DC level as the prior art. Additionally, since the predetermined adjusting values are set according to the coding of the input value, the initial boundary value SIi 1  and the predetermined adjusting values C 11  and C 12  can be pre-recorded in the memory unit  140 .  
         [0022]     Please refer to  FIG. 5 , which shows a block diagram of a decoding apparatus  295  for use in an optical storage device  210  according to a second embodiment of the present invention. The optical storage device  210  comprises a pick-up head  215 , a pre-equalizer  220 , an ADC  230 , a sampling rate converter  240 , an equalizer  260 , an equalizer controller  250 , a sampling rate controller  270 , and the decoding apparatus  295 . Obviously, a difference between the optical storage device  210  of  FIG. 5  and the optical storage device  10  of  FIG. 1  is that the components of the decoding apparatus  295  are different to that of the decoding apparatus  95 . Specifically, the decoding apparatus  95  of the first embodiment adopts a conventional hard decision Viterbi algorithm to decode data. To improve the decoding performance, the decoding apparatus  295  of the second embodiment adopts a soft decision Viterbi algorithm to decode data. For implementing the soft decision Viterbi algorithm, the transmission data D needs to be decoded based on the input value S I  and a group mean M of the input value S I  with respect to each signal region. Accordingly, the decoding apparatus  295  comprises a level slicer  280 , a mean calculator  296 , and a Viterbi detector  290 . As illustrated in  FIG. 5 , the input value S 1  is simultaneously applied to the level slicer  280 , the mean calculator  296 , and the Viterbi detector  290 . The level slicer  280  sets boundary values for each signal region according to the input value S 1 , and outputs a state value R to the mean calculator  296 . The mean calculator  296  then calculates the group mean M corresponding to the input value S 1  according to the state value R. Finally, the Viterbi detector  290  is able to decode a transmission data D in accordance with the input value S 1  and the group mean M.  
         [0023]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.