Abstract:
A comparison device includes; a comparison block suitable for comparing a pixel signal with a reference voltage including a ramp-up signal and a ramp-down signal; a correlated double sampling (CDS) block suitable for performing a correlated double sampling operation on the pixel signal; a first switch suitable for selectively inputting the ramp-up signal as the reference voltage based on a first switch control signal; a second switch suitable for selectively inputting the ramp-down signal as the reference voltage based on a second switch control signal; and a feedback control unit suitable for generating the first and second switch control signals based on a result of the comparison during an initialization operation.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2016-0054048 filed on May 2, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
       TECHNICAL FIELD 
       [0002]    Exemplary embodiments of the present disclosure relate to a high-speed and low-power comparator, an image sensor including the same, and an operating method thereof. 
       DESCRIPTION OF THE RELATED ART 
       [0003]    Image sensing devices capture images using photosensitive properties of semiconductors. Image sensing devices are generally classified into charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors. CMOS image sensors allow both analog and digital control circuits to be integrated in a single integrated circuit (IC), making CMOS image sensors the most widely used type of image sensor. 
         [0004]    Generally, CMOS image sensors have advantages of low power consumption, low cost and a small size compared to those of other competitive products. Hence, as the image quality of CMOS image sensors, which has been relatively insufficient compared to that of competitive products, is improving, the application field thereof is widening including video applications that require both high resolution and a high-speed frame rate. 
         [0005]    Heretofore, in order to realize improved CMOS image sensors which combine higher-speed frame rates with higher resolutions, efforts have focused on improving the analog-to-digital conversion (ADC) characteristics of the CMOS image sensors. 
         [0006]    However, employing a conventional analog-to-digital conversion method, it has been difficult to reduce the time required for converting the data, which means that improvements up to now have been made at the cost of increasing power consumption requirements of the CMOS image sensor. 
       SUMMARY 
       [0007]    Various embodiments are directed to a comparator with a correlated double sampling (CDS) block which combines a higher data conversion speed and reduced power consumption, an image sensor including the same, and an operating method thereof. 
         [0008]    In an embodiment, a comparator for an image sensor, the comparator may comprise: a comparison block suitable for comparing a pixel signal with a reference voltage including a ramp-up signal and a ramp-down signal; a correlated double sampling (CDS) block suitable for performing a correlated double sampling operation on the pixel signal; a first switch suitable for selectively inputting the ramp-up signal as the reference voltage based on a first switch control signal; a second switch suitable for selectively inputting the ramp-down signal as the reference voltage based on a second switch control signal; and a feedback control unit suitable for generating the first and second switch control signals based on a result of the comparison during an initialization operation. 
         [0009]    The feedback control unit may activate the first switch control signal when a voltage level of the pixel signal may be greater than the reference voltage until a predetermined time passes after the initialization operation. The feedback control unit may activate the second switch control signal when a voltage level of the pixel signal may be equal to or less than the reference voltage until a predetermined time passes after starting the initialization operation. The comparison block may include an operational amplifier and a feedback switch. The comparison block further may include a buffer. The CDS block may include a capacitor. 
         [0010]    In an embodiment, an operating method of an image sensor, the operating method may comprise: comparing a pixel signal to a ramp signal during an initialization operation; generating a control signal for selecting a ramp-up signal or a ramp-down signal based on a result of the comparison; and selecting the ramp-up signal or the ramp-down signal as the ramp signal based on the control signal to perform a comparison operation using the selected ramp signal. 
         [0011]    The ramp-up signal may be selected as the ramp signal during the comparison operation when a voltage level of the pixel signal may be greater than a voltage level the ramp signal during the initialization operation, and the ramp-down signal may be selected as the ramp signal during the comparison operation when a voltage level of the pixel signal may be equal to or less than the reference voltage during the initialization operation. 
         [0012]    In an embodiment, an image sensor may comprise: a pixel array suitable for outputting a pixel signal corresponding to incident light; a ramp signal generation circuit suitable for generating a ramp-up signal and a ramp-down signal; a comparison circuit suitable for selecting the ramp-up signal or the ramp-down signal based on a value of the pixel signal during an initialization operation, comparing a value of the pixel signal with a value of the selected ramp signal and generating an output comparison signal; a counting circuit suitable for performing a counting operation on the output comparison signal; a memory circuit suitable for storing data representative of the counting information outputted from the counting circuit; a column readout circuit suitable for outputting the data of the memory circuit; and a control circuit suitable for controlling operations of pixel array, the ramp signal generation circuit, the comparison circuit, the counting circuit, the memory circuit and the column readout circuit. 
         [0013]    In an embodiment, a comparator provided in each column of the comparison circuit, may comprise: a comparison block suitable for comparing a pixel signal with a ramp signal; a correlated double sampling (CDS) block suitable for performing a correlated double sampling operation on the pixel signal; a first switch suitable for selectively inputting a ramp-up signal as the ramp signal based on a first switch control signal; a second switch suitable for selectively inputting a ramp-down signal as the ramp signal based on a second switch control signal; and a feedback control unit suitable for generating the first and second switch control signals based on a result of the comparison during the initialization operation. 
         [0014]    The comparison block performs a comparison operation using the inputted ramp signal. The feedback control unit may activate the first switch control signal when a voltage level of the pixel signal may be greater than a voltage level of the ramp signal until a predetermined time passes after the initialization operation. The feedback control unit may activate the second switch control signal when a voltage level of the pixel signal may be equal to or less than a voltage level of the ramp signal until a predetermined time passes after starting of the initialization operation. The comparison block may include an operational amplifier and a feedback switch. The comparison block further may include a buffer. The CDS block may include a capacitor. The image sensor may be a CMOS image sensor. The image sensor may further may comprise a row circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The above and other features and advantages of the present invention will become more apparent to those skilled in the art to which the present invention belongs by describing in detail various embodiments thereof with reference to the attached drawings in which: 
           [0016]      FIG. 1A  is a diagram illustrating a CMOS image sensor. 
           [0017]      FIG. 1B  is a timing diagram describing an analog-digital conversion operation of the CMOS image sensor shown in  FIG. 1A . 
           [0018]      FIG. 2A  is a diagram illustrating a CMOS image sensor in accordance with an embodiment of the present invention. 
           [0019]      FIG. 2B  is a timing diagram describing an analog-digital conversion operation of the CMOS image sensor shown in  FIG. 2A . 
           [0020]      FIG. 3A  is a diagram illustrating a comparator in accordance with an embodiment of the present invention. 
           [0021]      FIGS. 3B and 3C  are diagrams showing control signal timings of the comparator shown in  FIG. 3A . 
           [0022]      FIG. 3D  is a flowchart showing a method of operating the comparator shown in  FIG. 3A . 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0024]    The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate. 
         [0025]    In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well-known process structures and/or processes have not been described in detail in order not to unnecessarily obscure the present invention. 
         [0026]    It is also noted, that in some instances, as would be apparent to those skilled in the relevant art, an element (also referred to as feature) described in connection with one embodiment may be used singly or in combination with other elements of another embodiment, unless specifically indicated otherwise. 
         [0027]    Hereinafter, the various embodiments of the present invention will be described in detail with reference to the attached drawings. 
         [0028]      FIG. 1A  is a diagram illustrating a CMOS image sensor.  FIG. 1A  shows a CMOS image sensor having a column parallel structure embodied using a general single slope analog-to-digital converter. Referring to  FIG. 1A , the CMOS image sensor includes a pixel array  10 , a row circuit  20 , a ramp signal generation circuit  30 , a comparison circuit  40 , a counting circuit  50 , a memory circuit  60 , a column readout circuit  70  and a control circuit  80 . 
         [0029]    The pixel array  10  outputs pixel signals (e.g. VPIXEL 1 , and VPIXEL 2  of  FIG. 1B ) corresponding to incident light. The row circuit  20  selects pixels in the pixel array  10  by respective row lines, and controls the operations of the selected pixels. For example the row circuit  20  includes a row decoder and a row driver. The ramp signal generation circuit  30  generates a ramp signal VRAMP. The comparison circuit  40  compares a value of the ramp signal applied from the ramp signal generation circuit  30  with a value of each pixel signal outputted from the pixel array  10 . The counting circuit  50  counts a clock that is provided from the control circuit  80  according to each output signal of the comparison circuit  40 . The memory circuit  60  stores counting information outputted from the counting circuit  50 . The column readout circuit  70  successively outputs data of the memory circuit  60  as pixel data PXDATA. The control circuit  80  controls the operations of the row circuit  20 , the ramp signal generation circuit  30 , the counting circuit  50 , the memory circuit  60 , and the column readout circuit  70 . For example, the control circuit  80  includes a timing generator. 
         [0030]    The CMOS image sensor compares pixel signals (i.e., pixel output voltages) generated before and after an optical signal is incident thereon, with each other in order to remove an offset value of a pixel itself, and thus measures only a pixel signal substantially resulting from the incident light. Such an operation is referred to as Correlated Double Sampling (CDS). The CDS operation is performed by the comparison circuit  40 . 
         [0031]    The comparison circuit  40  includes a plurality of comparators  41 , the counting circuit  50  includes a plurality of counters  51 , and the memory circuit  60  includes a plurality of memories  61 . The comparators, the counters, and the memories are provided in columns corresponding to the columns of the pixel array so that for each column corresponds a comparator  41 , a counter  51  and a memory  61 . Hence, a pixel signal generated by the pixel array is transmitted to a comparator, counter and memory of a respective column in the recited order. 
         [0032]    Hereinafter, the operation of one comparator, one counter, and one memory will be described by way of example. 
         [0033]    A first comparator  41  receives through one terminal thereof a pixel signal that is outputted from a first column of the pixel array  10 . The first comparator  41  also receives through the other terminal thereof a ramp signal VRAMP that is applied from the ramp signal generation circuit  30 . The first comparator  41  compares the values of the two signals with each other, and outputs a comparison signal. 
         [0034]    The ramp signal VRAMP is a signal, the voltage level of which is reduced by a predetermined amount over time after initialization has started. Hence, the ramp signal VRAMP may start form a certain high voltage value and then may gradually be reduced. As the ramp signal VRAMP is being gradually reduced, at some time point the values of the two signals inputted to the first comparator  41  coincide with each other. When this happens, immediately after the time point when the two input values coincided, the value of the comparison signal outputted from the first comparator is inverted. The same process occurs with respect to each of the plurality of the comparators in the comparison circuit  40 . 
         [0035]    Next, a first counter  51  counts a clock that is provided from the control circuit  80  from a time point at which the ramp signal VRAMP begins to fall, to the time point at which the comparison signal outputted from the comparison device  41  is inverted, and outputs the counting information. Each counter is initialized according to a reset signal that is provided from the control circuit. The same process is performed by each of the plurality of the counters in the counting circuit  50 . 
         [0036]    Then, a first memory  61  stores the counting information outputted from the first counter  51  according to a load signal that is provided from the control circuit  80 , and outputs the counting information to the column readout circuit  70 . The same function is performed by each of the plurality of memories in the memory circuit  60 . 
         [0037]    In the above-mentioned analog-to-digital conversion method, the maximum time for analog-to-digital converting data is determined by a value of the data. More specifically, the data conversion time TTOTAL may be expressed by the following Equation 1. 
         [0000]        T   Total =(Δ V   1   +ΔV   2 )/Δ V   stop    [Equation 1]
 
         [0038]    Wherein, ΔV 1 =VRAMP−VDMAX, ΔV 2 =VDMAX−VDMIN, ΔVstep denotes one step when the ramp signal falls, VDMAX denotes a maximum value within a range of a total amount of data to be converted in the analog-to-digital conversion, and VDMIN denotes a minimum value within the range of the total amount of data to be converted in the analog-to-digital conversion. 
         [0039]    However, in the above-mentioned analog-to-digital conversion method, the maximum time required for converting the data from analog-to-digital is rather substantial. Hence, the aforementioned conversion has a disadvantage in that the power consumption is increased. 
         [0040]    To overcome this, an embodiment of the present invention is directed to an image sensor having a higher data conversion speed. For example, in an embodiment the data conversion speed may be at least two times higher than that of the aforementioned analog-to-digital conversion method. The inventive method may thus reduce power consumption, and makes it possible to operate an image sensor employing such method with substantially lower power consumption. An embodiment will be described in detail with reference to  FIGS. 2A to 3B . 
         [0041]      FIG. 2A  illustrates a CMOS image sensor in accordance with an embodiment of the present invention.  FIG. 2B  is a timing diagram describing an analog-to-digital conversion operation of the CMOS image sensor shown in  FIG. 2A . 
         [0042]    Referring to  FIG. 2A , the CMOS image sensor may include a pixel array  10 , a row circuit  20 , a ramp signal generation circuit  30 , a comparison circuit  40 , a counting circuit  50 , a memory circuit  60 , a column readout circuit  70 , and a control circuit  80 . 
         [0043]    The pixel array  10  may output pixel signals corresponding to incident light. The row circuit  20  selects pixels in the pixel array  10  by respective row lines and controls the operations of the selected pixels. For example, the row circuit  20  may include a row decoder and a row driver. The ramp signal generation circuit  30  generates a ramp-up signal +VRAMP or a ramp-down signal −VRAMP. The comparison circuit  40  selects a value of the ramp-up signal +VRAMP or the ramp-down signal −VRAMP applied from the ramp signal generation circuit  30  and compares it with a value of each pixel signal outputted from the pixel array  10 . The counting circuit  50  counts a dock that is provided from the control circuit  80  according to each output signal of the comparison circuit  40 . The memory circuit  60  stores counting information outputted from the counting circuit  50 . The column readout circuit  70  successively outputs data of the memory circuit  60  as pixel data PXDATA, and the control circuit  80  controls the operations of the row circuit  20 , the ramp signal generation circuit  30 , the counting circuit  50 , the memory circuit  60 , and the column readout circuit  70 . For example, the control circuit  80  may include a timing generator. 
         [0044]    The comparison circuit  40  includes a plurality of comparators  41 , the counting circuit  50  includes a plurality of counters  51 , and the memory circuit  60  includes a plurality of memories  61 . The comparators, the counters, and the memories are provided in columns corresponding to the columns of the pixel array so that for each column corresponds a comparator  41 , a counter  51  and a memory  61 . Hence, a pixel signal generated by the pixel array is transmitted to a comparator, counter and memory of a respective column in the recited order. Hereinafter, the operation of one comparator, one counter, and one memory will be described by way of example. 
         [0045]    A first comparator  41  receives through one terminal thereof a pixel signal that is outputted from a first column of the pixel array  10 . The first comparator also selects any one of the ramp-up signal +VRAMP and the ramp-down signal −VRAMP that are applied from the ramp signal generation circuit  30 , receives the selected ramp signal through the other terminal thereof, compares values of the two signals with each other, and outputs a comparison signal. 
         [0046]    The ramp-up signal +VRAMP and the ramp-down signal −VRAMP have the same voltage level until a predetermined time passes after initialization. For example, the same voltage level may be set equal to (VDMAX+VDMIN)/2. After passing of the predetermined amount of time from the initialization time point, the voltage level of the ramp-up signal +VRAMP is gradually increased at a constant rate by a predetermined amount. At the same time when the ramp-up signal +VRAMP starts to increase, (i.e., at the passing of the predetermined time after initialization), the voltage level of the ramp-down signal −VRAMP is gradually reduced at a constant rate by a predetermined amount. Eventually, a time point at which the value of a selected one of the ramp-up signal +VRAMP and the ramp-down signal −VRAMP coincides with the value of the pixel signal occurs. With the passage of the coincidence time point the value of the comparison signal outputted from the comparator is inverted. The same process is performed by each one of the plurality of the comparators in the comparison circuit  40 . 
         [0047]    Then, a first counter  51  counts the clock from the control circuit  80  from a time point at which the voltage level of the ramp signal VRAMP begins to be increased or reduced, to the time point at which the comparison signal outputted from the comparison device  41  is inverted, and outputs the counting information. The same process is performed by each of the counters in the counting circuit  50 . Each counter is initialized according to a reset signal provided from the control circuit. 
         [0048]    Then, a first memory  61  stores the counting information outputted from the counter  51  according to a load signal provided from the control circuit  80 , and outputs the counting information to the column readout circuit  70 . 
         [0049]    In the above-described analog-to-digital conversion method, the maximum time for analog-to-digital converting data may be reduced substantially. More specifically, the data conversion time TTOTAL may be determined by the following Equation 2. 
         [0000]        T   TOTAL   ΔV   3   /ΔV   stop    [Equation 2]
 
         [0050]    Here, ΔV 3 =VRAMP−VDMAX or ΔV 3 =(VDMAX−VDMIN)/2 is satisfied, ΔVstep denotes one step when the ramp signal rises or falls, VDMAX denotes a maximum value within a range of a total amount of data to be converted in the analog-to-digital conversion, and VDMIN denotes a minimum value within the range of the total amount of data to be converted in the analog-to-digital conversion. 
         [0051]      FIG. 3A  is a diagram illustrating a comparator in accordance with an embodiment of the present invention.  FIGS. 3B and 3C  are diagrams showing control signal timings of the comparator shown in  FIG. 3A ,  FIG. 3D  is a flowchart showing a method of operating the comparator shown in  FIG. 3A .  FIG. 3B  illustrates a control signal timing when a voltage level of a pixel signal is greater than a reference voltage (i.e., a voltage level of a ramp signal applied until a predetermined time passes after initialization), and  FIG. 3 c    illustrates a control signal timing when the voltage level of the pixel signal is equal to or less than the reference voltage. 
         [0052]    Referring to  FIG. 3A , the comparator may include a comparison block  310 , a CDS block  320 , a second switch S 2 , a third switch S 3 , and a feedback control unit  330 . 
         [0053]    The comparison block  310  compares any one selected signal of the ramp-up signal +VRAMP and the ramp-down signal −VRAMP with the pixel signal VPIXEL (i.e., a pixel signal). The CDS block  320  is provided between a first input terminal to which the pixel signal VPIXEL is inputted and a negative input terminal (−) of the comparison block  310 , and is configured to perform CDS. The CDS block  320  may include a first capacitor C 1 . The CDS block  320  may further include a second capacitor and a switch. The second switch S 2  is provided between a second input terminal to which the ramp-up signal +VRAMP is inputted and a positive input terminal (+) of the comparison block  310 . The third switch S 3  is provided between a third input terminal into which the ramp-down signal −VRAMP is inputted and the positive input terminal (+) of the comparison block  310 . The feedback control unit  330  activates a second switch control signal CTRL_S 2  or a third switch control signal CTRL_S 3  for controlling the second and third switches S 2  and S 3 , respectively, according to a comparison signal outputted from the comparison block  310 . The third switch control signal CTRL_S 3  may be a complementary signal (or an inverted signal) of the second switch control signal CTRL_S 2 . 
         [0054]    In this regard, the comparator shown in  FIG. 3A  selects the ramp-up signal +VRAMP or the ramp-down signal −VRAMP according to the switch control signals after initialization, and performs a comparison operation. That is, the comparator compares the pixel signal to the reference voltage. If the voltage level of the pixel signal VPIXEL is greater than the reference voltage, the comparator activates the second switch control signal CTRL_S 2 , selects the ramp-up signal +VRAMP, and then performs a comparison operation. If the voltage level of the pixel signal VPIXEL is equal to or less than the reference voltage, the comparator activates the second switch control signal CTRL_S 3  selects the ramp-down signal −VRAMP, and then performs a comparison operation. 
         [0055]    For example, the comparison block  310  may include an operational amplifier OPAMP, a first switch (i.e., a feedback switch) S 1  and a buffer BUF, or include the comparator and the first switch S 1 . The CDS block  320  may include a first capacitor C 1  as illustrated in  FIG. 3A . 
         [0056]    Hereinafter, an operation process of the comparator will be descried with reference to  FIGS. 3A to 3D . 
         [0057]    The overall operation of the comparator is implemented in a sequence of an initialization operation (i.e., an offset canceling operation), a control signal generation operation, and a comparison operation (i.e., a pixel signal comparison operation). 
         [0058]    The comparator performs the initialization operation at step  410 . The initialization operation includes the comparator comparing the pixel signal VPIXEL to the reference voltage (i.e., a voltage level of a ramp signal applied until a predetermined time passes after initialization) and outputs a comparison signal. In more detail, the first and second switches S 1  and S 2  are turned on, and the third switch S 3  is turned off. A value of the pixel signal VPIXEL inputted from the first input terminal is stored in the first capacitor C 1 . As the second switch S 2  is turned on, the ramp-up signal +VRAMP is inputted to the positive input terminal (+) of the comparison block  310  through the second input terminal. Then the comparison block  310  compares the pixel signal VPIXEL to the reference voltage and outputs a comparison signal to the feedback control unit  330 . 
         [0059]    Thereafter, the comparator generates switch control signals for selecting the ramp-up signal +VRAMP or the ramp-down signal −VRAMP at step  420 . That is, as the result of comparison between the pixel signal VPIXEL and the reference voltage, if the voltage level of the pixel signal VPIXEL is greater than the reference voltage, the comparator activates the second switch control signal CTRL_S 2 , and if the voltage level of the pixel signal VPIXEL is equal to or less than the reference voltage, the comparator activates the third switch control signal CTRL_S 3 . In more detail, the first switch S 1  is turned off (i.e., a first switch control signal CTRL_S 1  is deactivated). As the result of comparison between the pixel signal (i.e., pixel output voltage) and the level of the reference voltage while the second switch S 2  is turned on and the third switch S 3  is turned off, if the voltage level of the pixel signal VPIXEL is greater than the reference voltage, the feedback control unit  330  activates the second switch control signal CTRL_S 2 , and if the voltage level of the pixel signal VPIXEL is equal to or less than the reference voltage, the feedback control unit  330  activates the third switch control signal CTRL_S 3 . In this case, the counter and the memory acquire and store data of a most significant bit (MSB). 
         [0060]    Thereafter, the comparator performs a comparison operation using the selected the ramp signal (i.e., the ramp-up signal +VRAMP or the ramp-down signal −VRAMP) at step  430 . That is, the comparator selects the ramp-up signal +VRAMP according to the activated second switch control signal CTRL_S 2  and performs the comparison operation, or selects the ramp-down signal −VRAMP according to the activated third switch control signal CTRL_S 3  and performs the comparison operation. In more detail, the first switch S 1  is in an off state. When the second switch control signal CTRL_S 2  is activated, the ramp-up signal +VRAMP is inputted to the positive input terminal (+) of the comparison block  310  through the second input terminal while the second switch S 2  is turned on and the third switch S 3  is turned off. Then the comparison block  310  compares the pixel signal VPIXEL with the ramp-up signal +VRAMP and outputs a comparison signal to the feedback control unit  330 . When the third switch control signal CTRL_S 3  is activated, the second switch S 2  is turned off and the third switch S 3  is turned on, whereby the ramp-down signal −VRAMP is inputted to the positive input terminal (+) of the comparison block  310  through the third input terminal. Then, the comparison block  310  compares the pixel signal VPIXEL with the ramp-up signal +VRAMP and outputs a comparison signal to the feedback control unit  330 . In this case, the counter and the memory perform the data conversion operation by up-counting in the case where the ramp-up signal +VRAMP is selected, or performs the data conversion operation by down-counting in the case where the ramp-down signal −VRAMP is selected, and then stores the data. 
         [0061]    Various embodiments provide an image sensor having a high-speed data conversion speed which may be two or more times as high as that of the conventional technology, thereby reducing power consumption, and making it possible to operate the image sensor with low power. 
         [0062]    Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.