Abstract:
Circuitry for eliminating magnetic instability of an inductive magnetic transducer during sensing of data from a magnetic recording medium to prevent distortion of the readback signal by hysterically moving domain walls. An inductive sensing coil has an impedance constituting the output impedance of the transducer. Means connected to the coil amplifies a data signal generated by the magnetic flux changes and produces a selected input impedance. The sum of these input and output impedances is selected to be small enough to substantially eliminate motion of the domain walls in the yoke of the transducer while the transducer is sensing data from the medium.

Description:
This invention relates to circuitry for eliminating or substantially reducing magnetic instability in inductive recording heads, and more particularly to circuitry including means for reducing motion of the magnetic domain walls in the yoke region of the head while the head is sensing data on a magnetic recording disk. 
     BACKGROUND OF THE INVENTION 
     Inductive magnetic recording heads (ferrite, metal-in-gap ferrite as well as thin-film heads) exhibit magnetic instability resulting from unstable and nonreproducible magnetic domain patterns in the yoke of the head after different write operations. These instabilities become more pronounced as track widths become narrower and the number of coil turns is increased to enhance recording density. One type of magnetic instability is &#34;write instability&#34;; i.e., the nonconstancy of the read response of a head following successive write operations as a result of Barkhausen noise. Another type of magnetic instability is &#34;read instability&#34; which can occur even when a head is not write-exercised for a long time and causes the data readback signal to vary or be distorted as a result of hysteretically moving domain walls. These types of instability can cause the head to respond to prerecorded magnetic transitions by affecting the readback signal in four different ways: (a) varying pulse amplitude, (b) varying pulse shape, (c) generating noise transients on predominantly the trailing edge of the pulse, and (d) generating noise transients randomly in time, predominantly directly after a write operation. 
     Phenomena (a) and (b) are caused by the domain patterns in predominantly the pole tip and apex regions of a thin-film head and in the crystallites adjacent to the gap and the airbearing surface of a ferrite head. Varying pulse amplitude (a) is due to variation in readback efficiency caused by variations in reluctance of the yoke associated with the different domain patterns following successive write operations. This results in a variation in the efficiency with which data signal flux is collected by the head. Varying pulse shape (b) is caused by the frequency dispersion in the part of the total data flux threading the coil that is contributed by predominantly reversible domain wall motion rather than by magnetization rotation. The different domain patterns occurring after write operations contribute differing fractions to the total flux sensed by the coil, resulting in differing dispersions; i.e., frequency dependencies. Phenomenon (c) results from the irreversible part of the wall motion induced by the data signal, which produces noise transients in head output voltage that are correlated to the readback signal. Finally, effect (d) results from delayed relaxation of the domain pattern in the head yoke after a write operation. 
     As a result of these phenomena (1) equalization of the channel becomes ambiguous because there is a plurality of pulse shapes to be equalized, rather than a single, isolated pulse shape; (2) the noise transients can create peak shift or extra peaks in a peak-detect channel and cause signal-correlated noise in a partial response maximum likelihood (PRML) channel; (3) specific domain patterns in the yoke of the head may produce enough remanence of the pole tips to partially erase the magnetic data transitions on the recording disk because even a weak field will reduce the magnetic data after many passes; and (4) servo sector information may become erratic (i.e., produce jittery position error signals) when writing data in a disk drive with embedded servo. Magnetic head instability, therefore, limits the use of inductive heads in high linear density applications using narrow track widths, and/or using embedded servo. 
     U.S. Pat. No. 4,280,158 discloses a magnetoresistive (MR) head comprising an MR sensor connected to an amplifier for suppressing Barkhausen noise by generating a negative feedback magnetic field that produces a magnetic flux in the MR sensor of a polarity opposite that of the field to be detected. The MR sensor is DC-biased, and a DC sense current is needed for readout of the sensor. A separate actuator is required in the form of a coil or &#34;turn&#34; to generate the field. The negative feedback is generated by a loop circuit. The purpose of the MR head is to linearize the resistance of the MR sensor in relation to the magnetic data signal input. 
     No prior art known to applicants discloses circuitry for eliminating magnetic instability of an inductive magnetic head by inhibiting motion of the domain walls in the yoke of the head during sensing of data so that inductive magnetic heads can be used in applications requiring narrow track widths, high linear densities, and embedded servo. 
     SUMMARY OF THE INVENTION 
     Circuitry is disclosed for substantially eliminating magnetic instability of an inductive magnetic transducer during sensing of data from a magnetic recording medium. This objective is achieved by making the impedance of a loop circuit consisting of an inductive sensing coil connected to the input of a modified arm electronics module (data signal preamplifier) as small as possible so essentially no voltage will be induced during reading of data by the transducer. Any voltage will be immediately opposed by a very large current, so no readback signal-induced change in magnetic flux will occur in the yoke of the transducer; the magnetic domain walls in the yoke therefore will not move, and the magnetic domain pattern will remain constant. 
     More specifically, the circuitry embodying the invention comprises means connected to the inductive sensing coil for amplifying a data signal generated by magnetic flux changes and producing a selected input impedance. The impedance of the coil constitutes the output impedance of the transducer. The sum of these input and output impedances is selected to be small enough to substantially eliminate motion of the domain walls in the yoke of the transducer while the transducer is sensing data from the recording medium. 
     The selected input impedance may be substantially zero, effectively short circuiting the coil, or substantially equal to but of opposite polarity from the output impedance, effectively making the impedance of the loop circuit zero. This may be achieved with a voltage amplifier having inputs connected to the coil and either shunting the amplifier with an impedance means or providing a transconductance amplifier in the feedback path of the amplifier to provide negative feedback for reducing the input impedance substantially to zero or positive feedback for reducing the loop circuit impedance substantially to zero. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a plot of percentage reduction in signal amplitude vs. the number of passes after writing of data at various flying heights of a remanent inductive magnetic transducer over the air bearing surface of the magnetic recording medium; 
     FIG. 2 is a schematic diagram of circuitry generically embodying the invention and showing that the generic principle of the invention involves providing a loop circuit with a low impedance εZ h  ; 
     FIGS. 3 and 4 are schematic diagrams of circuitry constituting different implementations of the invention of FIG. 2, each comprising negative feedback applied across an operational voltage amplifier to an essentially zero input impedance; 
     FIGS. 5 and 6 are schematic diagrams of circuitry constituting other, different implementations of the invention of FIG. 2, each comprising positive feedback applied across a voltage amplifier to create a selected negative input impedance; 
     FIG. 7 is a schematic diagram of a preferred embodiment of the circuitry illustrated in FIG. 6; and 
     FIG. 8 is a detailed schematic diagram of circuitry for implementing the preferred embodiment illustrated in FIG. 7. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 illustrates how nonrelaxing domain walls in the yoke region of an inductive magnetic transducer can cause a magnetic remanence large enough to progressively reduce the amplitude of a readback signal and thereby progressively partially erase the data recorded on a magnetic recording medium as the number of passes following a write operation increases. FIG. 1 also shows that the rate of deterioration in readback signal amplitude increases as the flying height of the transducer over the recording medium decreases. 
     FIG. 2 depicts an inductive magnetic recording transducer or head 10 comprising a yoke 12 having magnetic domain walls and an inductive sensing coil 14 wrapped around the yoke for sensing data on a magnetic recording medium (not shown) and generating a data signal in response to magnetic flux changes. Coil 14 has an impedance Z h  which constitutes the output impedance of head 10. 
     According to the invention, a circuit 20 constituting a modified arm-electronics module is connected to the output terminals 16, 18 of the head. Circuit 20 amplifies the induced voltage signal V ind  by providing a voltage gain G=V out  /V ind , and it also produces a low input impedance Z in . 
     According to a feature of the invention, coil 14 in combination with circuit 20 forms a loop circuit 22 having a low total loop impedance εZ h  where ε has a value between -1 and +1. This impedance εZ h  is the sum of the input impedance Z in  and output impedance Z h . This sum is selected to have a magnitude small enough to inhibit data signal flux variations in yoke 12 for substantially eliminating (i.e., freezing) motion of the domain walls of the yoke while head 10 is sensing data. 
     More specifically, this low loop impedance εZ h  is designed to inhibit flux variations in the data signal at low frequencies (i.e., below the range of about 0.5-2.5 MHz) at which motion of the domain walls of the yoke can occur. 
     FIG. 2 constitutes a schematic diagram generically depicting circuitry for achieving the above-stated objectives of the invention. Various specific embodiments for implementing the invention will now be described. 
     As illustrated in FIG. 3, circuit 20a includes an operational voltage amplifier 24 with its inputs connected to terminals 16, 18. Means 26 produces an impedance Z fb  which shunts amplifier 24 and provides a negative feedback path across the amplifier for short circuiting coil 14. This creates an input impedance Z in  =0(i.e., ε=1), and provides a data signal voltage gain G=V out  /V ind  =-Z fb  /Z h . 
     In the modified implementation shown in FIG. 4, circuit 20b includes the amplifier 24 but means 26 is replaced by a transconductance amplifier 28 that is connected in a feedback path from amplifier 24, creating negative feedback which nulls the input impedance Z in  and short circuits coil 14. This creates an input impedance Z in  =0(i.e., ε=1), and produces a data signal voltage gain G=V out  /V ind  =-1/gZ h , where g is the transconductance of amplifier 28. 
     As illustrated in FIG. 5 circuit 20c includes a voltage amplifier 30 with its inputs connected to terminals 16, 18. Means 32 shunts amplifier 30 and provides an impedance Z fb  in a positive feedback path that modifies the input impedance Z in  to render it substantially equal to, but of a polarity opposite that of, output impedance Z h . The input impedance Z in  =-Z h  (1-ε), where ε has a value between -1 and +1, and feedback impedance Z fb  =Z h  (1-ε) (A-1), A being the gain of voltage amplifier 30. This reduces the impedance εZ h  of the loop circuit below that achieved in FIGS. 3 or 4. The data signal gain V out  /V ind  =A(ε-1)/ε, and ε has a value preferably close to ε=0. 
     In the modified implementation depicted in FIG. 6, circuit 20d includes the amplifier 30, but means 32 is replaced by a transconductance amplifier 34 interposed in the feedback path from voltage amplifier 30. Amplifier 34 provides positive feedback for modifying input impedance Z in  to make it equal to, but of a polarity opposite that of, output impedance Z h . Then input impedance Z in  =-Z h  (1-ε), where ε has a value between -1 and +1, if the transconductance of amplifier 34 is selected such that gain g=1/AZ h  (1-ε), where A is the gain of the forward path of voltage amplifier 30. The data signal gain G=V out/Vind  =A(ε-1)/ε. Again, ε has a value preferably close to ε=0. 
     FIG. 7 illustrates a preferred embodiment of the implementation shown in FIG. 6. In this preferred embodiment, input impedance Z in  =-Z h  (1-ε) and ε has a value between -1 and +1, as in FIG. 6; but amplifier 34 is replaced by two transconductance amplifiers g 1 , g 2  circuited in cascade with an impedance Z inserted to give a transconductance gain g=g 1  g 2  Z with the required frequency dependency. Z is chosen so that Z=1/g 1  g 2  AZ h  (1-ε). As in FIG. 6, the data signal voltage G=V out  /V ind  =A(ε-1)/ε, with ε having a value as close as possible to ε=0, preferably 0.1 to 0.05. Note that since output impedance Z h  appears in the denominator, impedance Z can desirably be provided by a resistor in parallel with a capacitor. By contrast, if Z h  were in the numerator, impedance Z would have to be provided by a resistor in series with an inductor, and inductors have more parasitic properties, larger tolerances, provide more electro-magnetic interference, and cost more than capacitors. 
     FIG. 8 shows a preferred embodiment of the modified arm-electronics module 20e shown schematically in FIG. 7. As illustrated in FIG. 8, module 20e comprises an amplifier consisting of transistors T 1  and T 2  connected as a pair and with tail current I 2  for amplifying the head voltage V ind . Head terminal 16 is connected to the base of transistor T 1  and head terminal 18 is grounded. The base of transistor T 2  is grounded. This amplifier constitutes the transconductance amplifier g 1  of FIG. 7, where the base of transistor T 1  is the input terminal and the collector of transistor T 1  is the output terminal. Amplifier A is degenerated in this embodiment to a simple connection between node 19 and the base of transistor T 1  (A=1) whose output is available at the collector of transistor T 2  after amplification. The collector of transistor T 2  is connected via a resistor Rc to positive power supply line +V s . The voltage across resistor Rc is the data signal output voltage V out  which constitutes the induced readback signal. Between the collector of transistor T 1  and positive power supply +V s  a network is connected comprising a resistor R 1  and a diode D in series with a capacitor C in parallel. This network constitutes the impedance Z in FIG. 7. The voltage across this network is the input voltage of the second transconductance amplifier (g 2  in FIG. 7) in the feedback path. This transconductance amplifier g 2  comprises PNP transistor T 3  whose base is the input terminal of the transconductance amplifier g 2  and is connected via a resistor R 2  to power supply +V s . The collector of transistor T 3  is the output terminal of the transconductance amplifier and is connected to head terminal 16. A bleed-off current source I 1  is provided to avoid dc current through the head. The current I 1  should be substantially equal to the dc output current of the transconductance amplifier. With R 2  =R 1 , current I 1  should be equal to the collector current of transistor T 1 . With no dc current flowing through the head, the dc voltage at the base of transistor T 1  is zero. As a result, the collector currents of transistors T 1  and T 2  are equal and each is consequently equal to I 2  /2. Hence, current I 1  should be substantially equal to I 2  /2. 
     The impedance of the network in the collector of transistor T1 is ##EQU1## where s is the Laplace variable, r e  =2kT/qI 2 , with T the absolute temperature, k Boltzmann&#39;s constant, and q the electron charge. 
     The head impedance ##EQU2## where L h  is the inductance of the head and R h  is the resistance of the head. 
     The time constant C(R 1  +r e ) should be chosen to be equal to the head time constant τ h , where τ h  =L h  /R h . 
     With the above assumptions, the input impedance Z in  becomes Z in  =-2r e  (sτ h  +1); and the output voltage V out  becomes ##EQU3## where V ind  is the induced head voltage if the head terminals 16, 18 were left unconnected. With 2r e  =R h  (1-ε), the input impedance Z in  becomes -Z h  (1-ε) and the output voltage ##EQU4## 
     While the invention has been particularly shown and described with reference to various embodiments thereof, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention. Accordingly, the embodiments herein disclosed are to be considered as merely as illustrative and the invention is to be limited only as specified in the claims.