Abstract:
A power switching circuit including an MOS power switching transistor (P 1 ) is disclosed. The power switching transistor (P 1 ) has a body node that is selectably biased to either its source or its drain, depending upon a comparison of the voltage at the circuit input (IN) relative to the voltage at the circuit output (OUT). In a reverse voltage situation in which the output voltage exceeds the input voltage, a first body node switching transistor (P 11 ) connected between the body node of the power switching transistor (P 1 ) and its source is turned off by a voltage corresponding to the output voltage, as conducted from the drain of the power switching transistor (P 1 ) through a pull-down device (P 5 ) in an inverter. Also in this reverse voltage situation, the gate of the power switching transistor (P 1 ) is isolated from a control input (ON_/OFF) by series pass transistors (N 0 , N 1 ; P 12 , P 13 ), and the power switching transistor (P 1 ) is held off by a bias transistor (P 10 ), with a gate voltage also corresponding to the output voltage.

Description:
This application claims priority under 35 USC § (e)(1) of European Application Number 03291302.2 filed May 30, 2003. 
   CROSS-REFERENCE TO RELATED APPLICATIONS 
   Not applicable. 
   STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
   Not applicable. 
   BACKGROUND OF THE INVENTION 
   This invention is in the field of semiconductor integrated circuits, and is more specifically directed to metal-oxide-semiconductor (MOS) power transistor switches. 
   Many modern electronic devices and systems ultimately rely upon the controlled switching of high power levels to a load. For example, electronic devices that produce audio signal output require the controlled switching of significant levels of energy (current or voltage) to a physical speaker. Control systems also require the switching of significant energy to electronically operated machinery and the like. Solid state transistors effecting such power switching are now in widespread use, due to advances in the technology. 
   In order to reduce the cost of the overall device or system, it is of course desirable to integrate as much of the solid state circuitry of the device or system into fewer integrated circuits, ultimately into a single integrated circuit. In recent years, a preferred device technology for accomplishing such integration has been metal-oxide-semiconductor (MOS) technology, preferably complementary metal-oxide-semiconductor (CMOS) technology, which implements both p-channel and n-channel MOS transistors, as is fundamental in the art. It is therefore desirable to implement power switching by way of CMOS technology, to obtain the benefits of very large scale integration. 
     FIG. 1   a  schematically illustrates a conventional MOS power switching circuit including power switching transistor  22 . In this simplified arrangement, power switching transistor  22  is a p-channel MOS transistor, having its source connected to input IN to receive a high power signal, and its drain connected to pull-down load Z at output OUT. Power switching transistor  22  is sufficiently large, in terms of channel length and width, enabling it to conduct large currents and to handle large drain-source voltages. The body node, or channel node, of power switching transistor  22  is connected to its source in this conventional implementation; this connection is commonly referred to as the “back-gate” bias. Load Z is connected between the drain of power switching transistor  22  and ground, and presents an impedance so that energy from input IN is transferred to output OUT when power switching transistor  22  is turned on, while pulling down output OUT when power switching transistor  22  is off. 
   The gate of power switching transistor  22  is connected to control line ON_/OFF, which applies a control signal to turn the device on and off. Because power switching transistor  22  is p-channel, a low level on control line ON_/OFF relative to the voltage on input IN will turn on power switching transistor  22 , to conduct current from input IN to load Z. Conversely, a high voltage on control line ON_/OFF, within a threshold voltage of the voltage on line IN, will turn off power switching transistor  22 . The voltage at output OUT is thus pulled toward the high voltage of input IN when power switching transistor  22  is on, and is pulled toward ground through load Z when it is off. The circuit of  FIG. 1   a  is often used to generate large drive currents, of on the order of hundreds of milliamperes or greater. 
   In normal operation, the voltage at output OUT is lower than the voltage at input IN. In this typical condition, the source-drain leakage through power switching transistor  22  when off is substantially zero, at most in the sub-microampere range. It is of course desirable that the source-drain leakage be at these low levels whenever power switching transistor  22  is off, especially when implemented into a battery-powered device such as a wireless telephone handset. 
   However, it is possible for the voltage at output OUT to be higher than the voltage at input IN. One such fault situation occurs when power switching transistor  22  is turned off and the voltage at input IN then falls, so that the voltage at output OUT at the drain of power switching transistor  22  stays higher than that of the newly fallen voltage at the source of power switching transistor  22 . This can occur if an external device connected to output OUT, such as an electrolytic coupling capacitor, maintains the voltage at output OUT for some time after power switching transistor  22  is turned off. Another cause of a reverse voltage condition is the external driving of output OUT to a voltage above that of input IN. 
   In these situations, the drain voltage of power switching transistor  22  when off will be higher than the voltage at its source. This bias condition can cause significant leakage from drain to source, considering that parasitic diode D at the p-n junction between the drain and body node of power switching transistor  22  will be forward biased due to the body node being connected to the lower voltage at the source of power switching transistor  22 . The resulting reverse leakage can be significant, in some cases large enough to damage power switching transistor  22 . 
   To address this possibility for large drain-source leakage in power switching transistors, it is known to switch the body node connection of the power switching MOS transistor in response to circuit conditions.  FIG. 1   b  illustrates this conventional concept in a generic fashion, in which a pair of transistors  28   p ,  28   n  selectably connect the body node of power switching transistor  22 ′ to either its source (at input IN) or drain (at output OUT) according to the state of the circuit. 
   In this conventional switched body node arrangement, PMOS transistor  28   p  has its source connected to the source of power switching transistor  22 ′, and its drain connected to the body node of transistor  22 ′ and to the drain of NMOS transistor  28   n . NMOS transistor  28   n  has its source connected to the drain of power switching transistor  22 ′. Each of transistors  28   p ,  28   n  has its respective body node connected to its source, and the gates of transistors  28   p ,  28   n  are connected together to line SW. The state of line SW may be controlled by the state of line ON_/OFF at the gate of power switching transistor  22 ′, or alternatively may be driven from a comparator in response to the relative voltage of input IN to output OUT. 
   According to this conventional approach, transistors  28   p ,  28   n  are controlled so that the body node of power switching transistor  22 ′ is connected to either the drain or source of transistor  22 ′, whichever is at a higher voltage than that of the body node of power switching transistor  22 ′. This controlled switching is intended to ensure that a reverse-biased diode is always in place between the source and drain of transistor  22 ′. In normal operation, where the voltage at input IN is equal to or higher than the voltage at output OUT, line SW will be maintained low (e.g., by line ON_/OFF being low, or by the output of a comparator indicating that the voltage at output OUT is below that of input IN). This turns off NMOS transistor  28   n , and turns on PMOS transistor  28   p , connecting the body node of power switching transistor  22 ′ to its source. 
   Conversely, to avoid reverse leakage, line SW is driven high, to about the voltage at input IN. This turns on NMOS transistor  28   n  and turns off transistor  28   p , connecting the body node of power switching transistor  22 ′ to its drain. Line SW may be driven high by line ON_/OFF going high to turn off power switching transistor  22 ′. Alternatively, a comparator may drive line SW high in response to the voltage at output OUT going above that at input IN. 
   However, it has been observed, in connection with this invention, that this conventional body node switching arrangement has significant limitations. Referring to  FIG. 1   b , a voltage at output OUT that is significantly higher than that at input IN and on line SW can cause leakage through the series connection of transistors  28   p ,  28   n , even with PMOS transistor  28   p  turned off. Considering that transistor  28   n  effectively shorts the body node of transistor  22 ′ to its drain when on, transistor  28   p  can turn on if its drain voltage exceeds the voltage at its source (input IN) by the sum of its gate-to-source voltage plus its threshold voltage. If transistor  28   p  turns on, the reverse leakage through the series chain of transistors  28   n ,  28   p , from output OUT to input IN, can be significant, even in this conventional arrangement in which the body node bias of power switching transistor  22 ′ is controlled. 
   It has also been observed that overvoltage device specifications have become more stringent, relative to the manufacturing technology. Modern devices are required to guarantee extremely low reverse leakage levels, even under significant reverse voltage conditions. 
   BRIEF SUMMARY OF THE INVENTION 
   It is therefore an object of this invention to provide a power switching transistor circuit in which the power switching transistor exhibits extremely low levels of reverse leakage. 
   It is a further object of this invention to provide such a circuit in which the extremely low reverse leakage is attained even at relatively large externally applied output voltages. 
   It is a further object of this invention to provide such a circuit in which the body node of the power switching transistor is reliably controlled to ensure such extremely low reverse leakage performance. 
   Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings. 
   The present invention may be implemented into a control circuit for a metal-oxide-semiconductor (MOS) power switching transistor. A pair of MOS transistors are provided for selectably switching the body node of the MOS power switching transistor to its drain or source, responsive to whether the drain or source is at a higher voltage. In operation, one of the pair of MOS transistors will turn on, for example in response to a comparison of the drain and source voltages of the power switching transistor. Additional transistors are provided to also fully turn off the other one of the MOS transistor, holding it off even in the event of an excessive reverse voltage across the power switching transistor. Additional circuitry isolates the gate of the power switching transistor from its control signal in the reverse voltage situation, and holds the power switching transistor off in this state. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
       FIGS. 1   a  and  1   b  are electrical diagrams, in schematic form, of a conventional power switching transistor and of conventional circuitry for controlling its back-gate bias. 
       FIG. 2  is an electrical diagram, in schematic form, of a power switching circuit constructed according to the preferred embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention will be described in connection with its preferred embodiment, namely as implemented by way of complementary metal-oxide-semiconductor (CMOS) technology. More particularly, this description is provided for the example in which a p-channel metal-oxide-semiconductor (MOS) transistor serves as the power switching transistor. This particular description is provided because it is contemplated that this invention is especially beneficial when implemented in such an fashion and application. It will be understood by those skilled in the art having reference to this specification that this invention will have benefits when implemented in other contexts, and according to other alternative technologies. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed. 
   Referring now to  FIG. 2 , a power switching circuit according to the preferred embodiment of the invention will now be described. In this example, power switching transistor P 1  is a p-channel MOS (PMOS) transistor, having its source connected to input IN and its drain connected to load Z, at output OUT. Load Z is connected between output OUT at the drain of power switching transistor P 1  and ground, in this example. The gate of power switching transistor P 1  is coupled to control line ON_/OFF, via the source/drain paths of NMOS series transistors N 0 , N 1  in parallel with the source/drain paths of PMOS series transistors P 12 , P 13 . In normal operation, NMOS series transistors N 0 , N 1  and PMOS series transistors P 12 , P 13  are all on, so that the state of control line ON_/OFF directly controls the on-off state of power switching transistor P 1 . 
   It will be understood by those skilled in the art that power switching transistor P 1  may alternatively be realized by an n-channel MOS (NMOS) device. In such a complementary realization, it is contemplated that the channel conductivity type of each of the transistors, and the relationships of the various voltages, in the circuit of  FIG. 2  will also be complementary to that shown. It is further contemplated that those skilled in the art having reference to this specification will be readily able to effect such a complementary implementation of this exemplary circuit. 
   In its basic operation, the input power to be switched is applied to input IN from elsewhere in the system incorporating the power switching circuit of FIG.  2 . For example, input IN may supply power for driving audio speakers that are connected to output OUT, such as in a wireless telephone handset or in an audio amplifier circuit for a computer or audio system. Of course, many applications of power switching circuits are known in the art, in connection with which this preferred embodiment of the invention is suitable. The state of control line ON_/OFF is controlled by the system to determine the application of this power to output OUT. For example, a pulse width modulator may control power switching transistor P 1  by controlling the state of control line ON_/OFF in a pulse width modulated fashion. In the example of  FIG. 2 , a low level on control line ON_/OFF will turn on power switching transistor P 1 , applying the power from input IN to load Z and driving output OUT accordingly. Conversely, a high level on control line ON_/OFF will turn off power switching transistor P 1 , isolating output OUT from input IN. 
   Referring back to the construction of the preferred embodiment of this invention, the body node connection, or back-gate bias, of power switching transistor P 1  is controlled by way of PMOS transistor P 11  and PMOS transistor P 2 . PMOS transistor P 11  has its source connected to input IN, and its drain and body node connected to the body node of power switching transistor P 1 . Conversely, PMOS transistor P 2  has its source, and its body node, connected to the body node of power switching transistor P 1 , and its drain connected to output OUT. PMOS transistor P 5  and NMOS transistor N 6  have their source-drain paths connected in series with that of PMOS transistor P 2 , creating a series path from output OUT to ground. In this example, PMOS transistor P 5  has its source connected to the drain of PMOS transistor P 2 , and its drain connected to the drain of NMOS transistor N 6  in CMOS inverter fashion; the source of NMOS transistor N 6  and its body node are at ground. The gate of PMOS transistor P 11  is connected to the output of this CMOS inverter at the drains of PMOS transistor P 5  and NMOS transistor N 6 , shown as node CMP− in FIG.  2 . The body nodes of PMOS transistors P 2 , P 5 , and also that of PMOS transistor P 10 , are connected in common to the source of PMOS transistor P 2 , which is at the same potential as the switched body node of power switching transistor P 1 . 
   The gates of PMOS transistors P 2 , P 5 , and the gate of NMOS transistor N 65  are driven by the output of comparator  10 , at node CMP+. Comparator  10  may be a conventional voltage comparator circuit as known in the art. Comparator  10  has a non-inverting input connected to input IN, at the source of power switching transistor P 1 , and an inverting input connected to output OUT, at the drain of power switching transistor P 1 . Comparator  10  thus produces an output signal having a polarity corresponding to the polarity of the voltage at input IN relative to output OUT, and thus to the polarity of the source voltage of transistor P 1  to its drain voltage. The output of the inverter of PMOS transistor P 5  and NMOS transistor P 6 , at node CMP−, is complementary to the output of comparator  10 , at node CMP+. 
   The combination of PMOS transistors P 11 , P 2 , P 5  and NMOS transistor N 6  controls the voltage to which the body node of power switching transistor P 1  is biased, in response to the output of comparator  10 . This operation will be described in further detail below. 
   The power switching circuit according to the preferred embodiment of the invention also includes the function of isolating the gate of power switching transistor P 1  from control line ON_/OFF, in the event that the voltage at output OUT exceeds the voltage at input IN. To realize this function, a parallel pair of complementary series transistors couple control line ON_/OFF to the gate of power switching transistor P 1 , as mentioned above. NMOS transistor N 0  has its source connected to control line ON_/OFF, and its drain connected to the drain of NMOS transistor N 1 ; the source of NMOS transistor N 1  is connected to the gate of power switching transistor P 1 . The body nodes of each of NMOS transistors N 0 , N 1  are connected to their respective drains, and the gates of transistors N 0 , N 1  are connected in common to node CMP+, at the output of comparator  10 . The source/drain paths of PMOS transistors P 12 , P 13  are in parallel with those of NMOS transistors N 0 , N 1 , with the source of PMOS transistor P 12  connected to control line ON_/OFF, the drains of PMOS transistors P 12 , P 13  connected together, and the source of PMOS transistor P 13  connected to the gate of power switching transistor P 1 . The body nodes of PMOS transistors P 12 , P 13  are connected to their respective sources, and the gates of PMOS transistors P 12 , P 13  are connected in common to node CMP−, at the output of the inverter formed by PMOS transistor P 5  and NMOS transistor N 6 . As such, the gates of the parallel complementary NMOS transistors N 0 , N 1  and PMOS transistors P 12 , P 13  receive complementary signals relative to one another, as will be described in detail. 
   Also according to the preferred embodiment of the invention, power switching transistor P 1  is held off in the event that the voltage at output OUT exceeds the voltage at input IN. This function is realized by PMOS transistor P 10 , which has its source connected to the gate of power switching transistor P 1 , its drain connected to output OUT, and its gate driven from node CMP+ at the output of comparator  10 , in common with the gates of PMOS transistors P 2 , P 5  and NMOS transistor N 6 . As mentioned above, the body node of PMOS transistor P 10  is connected in common with the body nodes of PMOS transistors P 2 , P 5  and power switching transistor P 10 . 
   In normal operation, the voltage at input IN is higher than the voltage at output OUT. Comparator  10  in turn issues a positive polarity output at node CMP+, at a sufficient voltage to turn on NMOS transistors N 6 , N 0 , and N 1 , and turn off PMOS transistors P 2 , P 5 . This causes the voltage at node CMP−, at the drains of transistors P 5 , N 6 , to be pulled to ground by NMOS transistor N 6 . With node CMP− low, PMOS transistor P 11  is turned on, biasing the body node of power switching transistor P 1  to its source at the higher voltage at input IN (i.e., higher than the voltage at output OUT), considering that PMOS transistor P 2  is turned off by the high voltage at node CMP+. The body nodes of PMOS transistors P 2 , P 5 , P 10  are also biased to the higher voltage at input IN. The high voltage at node CMP+ and the low voltage at node CMP− also turns on all of NMOS transistors N 0 , N 1  and PMOS transistors P 12 , P 13 , connecting the gate of power switching transistor P 1  to control line ON_/OFF. PMOS transistor P 10  is turned off by the high voltage at node CMP+, so that it does not affect the gate voltage of power switching transistor P 1 . Power switching transistor P 1  is thus enabled to switch power from input IN to output OUT under the control of control line ON_/OFF. 
   In the reverse voltage fault condition in which output OUT is at a higher voltage than that of input IN, typically occurring after power transistor P 1  is turned off by control line ON_/OFF, comparator  10  senses this relative voltage polarity condition, and in response drives a low level at node CMP+. This turns off NMOS transistor N 6 , and turns on PMOS transistor P 5  so that the high voltage at output OUT is conducted through PMOS transistor P 5  to appear at node CMP−, turning off PMOS transistor P 11  and isolating the body node of power switching transistor P 1  from its source at input IN. The low voltage at node CMP+ also turns on PMOS transistor P 2 , connecting the body node of power switching transistor P 1  (and that of PMOS transistors P 11 , P 2 , P 5 , P 10 ) to its drain, which is at the higher voltage of output OUT (i.e., higher than the voltage at input IN). 
   According to this preferred embodiment of the invention, the gate of power switching transistor P 1  is also isolated from control line ON_/OFF in the reverse voltage condition. The low voltage at node CMP+ turns off NMOS transistors N 0 , N 1 , and the high voltage at node CMP− turns off PMOS transistors P 12 , P 13 , effecting this isolation. The low voltage at node CMP+ also turns on PMOS transistor P 10 , coupling the high voltage at output OUT to the gate of power switching transistor P 1 , ensuring that transistor P 1  remains fully off in this reverse voltage state. 
   According to this embodiment of the invention, reverse leakage current is greatly reduced, even at relatively high reverse voltages. This is accomplished by the common biasing of the body nodes of PMOS transistors P 10 , P 2 , P 5 , along with the body node of power switching transistor P 1 , to the higher voltage at the drain of transistor P 1  at output OUT, in the reverse voltage condition. Because the body nodes of each of these devices are biased to this highest voltage in the circuit, these devices are not vulnerable to undesirable turn-on, as in conventional circuits. In addition, because PMOS transistors P 2 , P 5  are turned on by comparator  10 , the higher voltage at output OUT is applied directly to the gate of PMOS transistor P 11 , ensuring that this device not only turns off but remains off, regardless of how high the voltage at output OUT is driven (short of overstress, of course). 
   Furthermore, because of the isolation of the gate of power switching transistor P 1  from control line ON_/OFF, and because of the operation of PMOS transistor P 10  actively driving the gate of transistor P 1  to an off state, drain-source reverse leakage through power switching transistor P 1  itself is also prevented. This is especially important in battery-backup situations, where the power switching function is intended to be disabled, and where leakage current is to be minimized to maximize battery life. 
   It is therefore contemplated that the power switching circuit according to the preferred embodiment of the invention, as described above, is capable of achieving extremely low reverse leakage currents, as low as the sub-microampere range. This excellent level of performance is attained while still using a single MOS power switching transistor, rather than requiring discrete devices to ensure low reverse leakage. This power switching circuit can therefore be efficiently realized in relatively small silicon area, especially considering that single MOS transistors are also still used to switch the body node of the power switching device. 
   Other advantages are also provided by the power switching circuit according to this embodiment of the invention. In particular, the body node biasing transistors share the same body node connection as the body node of the power switching transistor itself. This greatly reduces the required silicon area, as these transistors can all be realized in the same tank or well, thus eliminating the need not only for one or more additional tanks, but also the tank-to-tank spacing required for isolation of the body nodes. By sharing the same tank for these devices, the parasitic junction capacitance is reduced as is interconnect resistance, permitting faster switching of the circuit itself. The single tank for these devices also improves the immunity of the circuit to CMOS latchup. 
   While the present invention has been described according to its preferred embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.