Abstract:
The image sensor includes an array of pixels, each pixel having a photo-diode, for providing a pixel voltage, an analog-to-digital converter (ADC) operable to convert the pixel voltage to a digital value and a memory for storing the digital value. Read circuitry is included for reading out the digital values from the pixels of the array in a predetermined order. The image sensor may be configured such that a counter incorporates the memory, and the counter may be adapted to operate as a shift register. The counters of two or more pixels may be connected to form one or more chains such that digital values can be read out in a bit-serial manner.

Description:
FIELD OF THE INVENTION 
     The present invention relates to an image sensor, and particularly, to a serial readout CMOS image sensor. 
     BACKGROUND OF THE INVENTION 
     Typically, CMOS image sensors have a pixel array with information from each pixel in a row of the pixel array being read out in parallel. This requires each pixel in a column of the pixel array to be connected to a common column bus. Each row is selected in turn and the pixel information read out on each column bus. As image sensor resolution increases, pixel array size increases accordingly, requiring that a single pixel drive an increasingly large column bus. 
     SUMMARY OF THE INVENTION 
     According to the first aspect of the present invention there is provided an image sensor including an array of pixels, each pixel comprising a photo-diode, for providing a pixel voltage, an analog-to-digital converter (ADC) operable to convert the pixel voltage to a digital value and a memory for storing the digital value. The image sensor includes a reading circuit or means for reading out the digital values from the pixels of the array in a predetermined order. 
     Preferably, the means for reading out comprises means for connecting the pixel memories in one or more chains. Preferably, the ADC comprises a comparator, wherein the comparator is supplied with a ramp voltage and detects when the ramp voltage is substantially equivalent to the pixel voltage, and a counter, the counter also providing the pixel memory. 
     Preferably, the counter is adaptable to operate as a shift register and the counter of two or more pixels in the pixel array are connected in series to form the chain enabling a bit-serial readout of the two or more pixels. Preferably, the counter comprises one or more memory elements for storing the digital values. Preferably, the chain comprises each pixel in a row enabling bit-serial readout of each row. Alternatively, the chain comprises each pixel in a column enabling bit serial readout of each column. 
     Further alternatively, the chain comprises each pixel in the pixel array enabling bit-serial readout of the entire pixel array. Preferably, the chain has an input tied to logic “zero” enabling the bit-serial readout of the chain to set the memory element of the counter in each pixel to logic “zero”. Preferably, the memory element is a D-type memory element. 
     According to a second aspect of the present invention there is provided an optical pointing device comprising a serial readout image sensor according to the first aspect of the invention. Preferably, the optical pointing device is an optical mouse. 
     According to a third aspect of the present invention there is provided a mobile device comprising a serial readout image sensor according to the first aspect of the invention. Preferably, the mobile device is a mobile cellular telephone. Alternatively, the mobile device is a camera. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: 
         FIG. 1  is a schematic diagram illustrating a pixel according to the present invention; 
         FIG. 2  is a signal timing diagram illustrating one embodiment of various signal levels used to operate a pixel according to the present invention; 
         FIG. 3  is a schematic diagram illustrating a counter chain of three pixels according to the present invention; 
         FIG. 4  is a schematic diagram illustrating a counter chain of each pixel in a pixel array according to the present invention; and 
         FIG. 5  is a schematic diagram illustrating several counter chains of each pixel in a row according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring initially to  FIG. 1 , and  FIG. 2 , a pixel  10  comprises a photodiode  12 , reset transistor  14 , comparator  16  and counter  18 . A reset signal  20  is applied to the gate, a supply voltage VRT is applied to the source and a node  22  is connected to the drain of the reset transistor  14 . When the reset signal  20  is high, the node  22  has a pixel voltage  23  equivalent to the supply voltage VRT. 
     When the reset signal  20  is low, the pixel  10  enters an integration phase  21  and the node  22  has a pixel voltage  23  related to impinging light on the photodiode  12 . The pixel voltage  23 , when the reset signal  20  is low, varies according to the amount of impinging light and the integration time. At the end of the integration phase  21 , and while the reset signal  20  is still low, the pixel  10  enters an ADC (Analog to Digital Converter) conversion phase  25 . 
     The comparator  16  has a first input connected to the node  22  and a second input connected to a ramp generator (not shown), which provides a ramp signal  24 . The comparator  16  has a comparator output  26  connected to the counter  18 . The counter  18  also receives a clock signal  28 , a scan enable input  30  and a scan input  32 . The counter also has a scan output  34 . The counter  18  may be a true counter, that is, increments its value every clock cycle, or a pseudo random linear feedback shift register (LFSR). 
     Once the ADC conversion phase  25  has begun, the ramp generator starts reducing the ramp signal  24  from supply voltage and the counter  18  a count sequence  27  and starts to digitally count. When the ramp signal  24  is equal to the pixel voltage, the comparator output  26  goes from low to high stopping the counter  18  at a digital value equivalent to the pixel voltage. Once the ADC conversion phase  25  has completed, a readout phase  36  can begin. The scan enable input  30  is set high which adapts the counter  18  to operate as a shift register. 
     The counter  18  is part of a counter chain, which is more fully described below. The scan input  32  is connected to a scan output from a previous pixel in the counter chain. The scan output  34  is connected to a scan input of a subsequent pixel in the counter chain. Referring to  FIG. 3 , a counter chain  50  has a first pixel PX 1 , a second pixel PX 2  and a third pixel PX 3  each equivalent to the pixel  10  as described previously and therefore like references are numbered accordingly. 
     The counters  18  are now shown with memory elements  52 . In this example, four memory elements are shown which would enable a four-bit number to represent the pixel voltage. In preference, the memory elements are D-type memory elements. With scan enable  30  set at high the counters  18  are configured as shift registers. The first pixel PX 0  has its scan input  32  connected to a low input  54 . The third pixel PX 2  has its scan output  34  connected to a serial output  56 . 
     Once the clock  28  is active as well as the scan enable  30  being high, each bit in each memory element  52  is moved one memory element towards the serial output  56  on each clock pulse. For example, on the first clock pulse, the first pixel&#39;s PX 0  memory element  52 D has its value shifted to the second pixel&#39;s PX 1  memory element  52 A. Therefore the serial output  56  receives one bit at a time and, knowing the length of each digital pixel value can reconstruct the digital pixel value for each pixel. 
     As the first pixel PX 0  has its scan input  32  connected to a low input  54 , and, as the digital pixel values are shifted one place on each clock pulse, the memory elements  52  have their digital pixel values replaced with low values. Each pixel, once all digital pixel values are readout, has all its memory elements storing low values. The shift register operation thereby acting as an automatic reset of the memory elements  52  during each readout phase. Furthermore, there is no requirement for a global counter reset signal. The counters re-configured as a shift register may be either connected together on a row-by-row basis, column-by-column basis or as a global counter chain. 
       FIG. 4  shows how a pixel array  60  can be connected together as a global counter chain. Firstly, pixel ( 0 , 0 ) has its counter scan input connected to low input  62  and the remaining pixels in row  0  are connected together as described above for  FIG. 3  except for pixel ( 0 , 3 ). The last pixel in row  0 , pixel ( 0 , 3 ), has its counter scan output connected to the last pixel in row  1 , pixel ( 1 , 3 ). Row  1  pixels are then connected together moving from column  3  to column  0 . The first pixel in row  1 , pixel ( 1 , 0 ), is then connected to the first pixel in row  2 , pixel ( 2 , 0 ). This method of connection continues through the pixel array until the end of the counter chain is reached, in this case the last pixel in the counter chain is pixel ( 3 , 0 ), being the first pixel in row  3 . Pixel ( 3 , 0 ) is connected to serial output  64  which receives all the pixel value from the pixel array  60  on a bit-serial basis. 
       FIG. 5  shows how a pixel array  70  can be connected together on a row-by-row basis as a number of parallel counter chains. All pixels in row  0  are connected together in series with the first pixel in row  0 , pixel ( 0 , 0 ), having a low input  72  and the last pixel in row  0 , pixel ( 0 , 3 ), being connected to a row  0  serial output  74 . Row  1 , row  2  and row  3  each have individual counter chains having individual low inputs and serial outputs. This enables parallel readout of each row. 
     The pixel array  70  can also be read out on a column-by-column basis by modifying the connections between pixels such that the pixels are connected together in columns. It may also be possible to choose other arrangements of connections between the pixels for readout without departing from the scope of the invention. 
     The present invention only requires local pixel-to-pixel interconnections to enable readout of the pixel data rather than an interconnect which spans a whole column or row or a digital pixel which has a parallel readout. This approach has several benefits in including: no global wide (for example, 8-bit) data bus to distribute; as the readout mechanism is integrated within the pixel there is no need for additional readout circuitry (for example, x and y shift registers); smaller routing overhead in the pixel cell enabling more area available for the photo sensitive part of the pixel; and improved scalability as the output of one pixel only has to drive its neighbor rather than long wire length of which increases with the resolution of the sensor. 
     Improvements and modifications may be incorporated without departing from the scope of the present invention.