Abstract:
A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is related to, and claims the benefit of, U.S. Provisional Patent Application Ser. No. 62/190,341 entitled “CELL PITCH WITH SIDEWALL IMPLANTED TRENCH FETS,” filed on Jul. 9, 2015 and incorporated herein by reference. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
       [0002]    Understanding that the drawings depict only exemplary embodiments and are not therefore to be considered limiting in scope, the exemplary embodiments will be described with additional specificity and detail through the use of the accompanying drawings. 
         [0003]      FIGS. 1A-1W  depict a process of forming a trench MOSFET cell with a depleted gate shield, which can be utilized to implement one or more exemplary embodiments of the present invention. 
         [0004]      FIG. 2  depicts a cross-sectional view of a semiconductor device that can be formed utilizing the exemplary process depicted in  FIGS. 1A-1W . 
         [0005]      FIG. 3  is a schematic block diagram of an electronic system that can be utilized to implement one exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION 
       [0006]    In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of specific illustrative embodiments. However, it is to be understood that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made. Furthermore, the method presented in the drawing figures and the specification is not to be construed as limiting the order in which the individual acts may be performed. The following detailed description is, therefore, not to be construed in a limiting sense. Wherever possible, the same or like reference numbers are used throughout the drawings to refer to the same or like structural components or parts. 
         [0007]    Metal-oxide-semiconductor field effect transistors (MOSFETs) are commonly utilized in electronic circuits, such as, for example, communication systems, power supplies, and the like. Power MOSFETs are commonly utilized in power supply and/or power conversion applications, such as, for example, as electronic switches that can enable and disable the conduction of large currents (e.g., 5 A-100 A) in DC to DC power converters and the like. Power MOSFETs include a large number of MOSFET cells and/or individual transistor devices that are connected in parallel and distributed across the surface of a semiconductor die. In order to maximize power conversion efficiency, the power MOSFETs utilized must minimize both conduction and switching losses. Power MOSFET conduction losses are proportional to the drain-to-source resistance in the operation or “on” state (RDSON) of the transistor device involved. Switching losses are proportional to the switching frequency and internal parasitic capacitance, and most significantly, to the gate-to-drain capacitance (Cgd) of the transistor device involved. Trench power MOSFETs are thus widely utilized in switching applications due to their characteristically low RDSON. 
         [0008]    Trench power MOSFETs utilize a “shielded” gate or “split” gate architecture to improve the tradeoff between breakdown voltage (BV) and RDSON. Under the split gate architecture, a dielectrically isolated shield is formed under the polysilicon gate within a trench in a cell of the MOSFET device. The shield is electrically connected to the source terminal of the MOSFET device. Although incremental improvements have been made to improve the tradeoff between BV and RDSON (e.g., through feature size scaling techniques) of existing devices, these improvements have been made at the expense of increased manufacturing complexity. 
         [0009]    A more pressing concern for manufacturers of shielded gate trench power MOSFETs is the tradeoff between reduced on resistance (RON) versus increased gate-to-source capacitance (Cgs) and drain-to-source capacitance (Cds) across the field oxide adjacent to the shield. For example, an in-situ doped N+ polysilicon material is typically utilized to form the shield. Consequently, the parasitic output capacitance (COSS) of the MOSFET device is dominated by the surface area of the polysilicon shield and the thickness of the oxide adjacent the shield. As a result, a significantly high electric field is generated across the oxide adjacent the shield when the MOSFET device is in the “off” or non-operational state. This result requires the manufacturers to utilize a thick layer of oxide adjacent the shield to ensure the reliability of the MOSFET device against the adverse effects of such events as hot carrier injections and time-dependent dielectric breakdowns. As described below, the present invention resolves these and other, related problems with a depleted shield, split gate trench power MOSFET device formed on an integrated circuit, wafer, chip or die. 
         [0010]    In accordance with the teachings of the present application, a depleted gate shield is formed in a trench in a split gate trench power MOSFET device. The depleted gate shield, which is a dopant type opposite to that of the drift region adjacent the trench, significantly reduces the magnitude of the electrical field in the oxide material adjacent the shield and in the trench, and thereby transfers a substantial amount of the stress generated by the electric field to the polysilicon material of the shield while the power MOSFET device is in the “off” state. Consequently, the device manufacturer can utilize a significantly thinner (e.g., −10 nm) than usual layer of oxide material adjacent the shield and, as a result, significantly reduce the overall width of the trench (e.g., from approximately 0.5 μm to approximately 0.2 μm) and the cell pitch of the device to produce a significantly lower than typical RDSON. The depleted gate shield trench power MOSFET device also significantly reduces its output capacitance (COSS) as a function of its drain-to-source voltage (Vds). As the gate shield is being depleted, the COSS is reduced or scaled down as a function of the width of the depletion area. 
         [0011]      FIGS. 1A-1W  depict a process of forming a trench MOSFET cell  100  including a depleted gate shield, which can be utilized to implement one or more exemplary embodiments of the present invention. In one embodiment, a plurality of MOSFET cells  100  can be electrically connected in parallel to form, for example, a power trench MOSFET device with a high current carrying capacity. The power MOSFET device can be an n-channel device or a p-channel device, where “n” denotes a negative carrier type (e.g., electron), and “p” denotes a positive carrier type (e.g., hole). As such, although the embodiment depicted herein is described in terms of a dopant species for an N-channel MOSFET (N-MOS) device, a second embodiment can utilize the opposite dopant type species to form a P-channel MOSFET (P-MOS) device. 
         [0012]      FIG. 1A  depicts a cross-sectional view of a semiconductor substrate  102  on which a trench MOSFET device  100  including a depleted gate shield can be formed. For this exemplary embodiment, the trench MOSFET  100  is an N-MOS device, and the substrate  102  is formed with an n-type (N+) semiconductor material, such as, for example, phosphorous, antimony or arsenic. The substrate  102  includes an active surface  101  and back surface  103  opposite the active surface  101 . For this embodiment, a p-type epitaxial (p-epitaxial) region  104  is grown over the N+ substrate (drain) region  106 . The thickness of the p-epitaxial region  104  is approximately 1 μm. A first insulating layer  108  (referred to herein as a thermal oxide layer) is formed over the active surface  101  utilizing, for example, a physical vapor deposition (PVD), chemical vapor deposition (CVD), thermal oxidation, or other suitable oxide deposition process. In this embodiment, the thermal oxide layer  108  is approximately 50 nm thick, and can be formed utilizing one or more layers of silicon dioxide (SiO2), tantalum pentoxide (Ta205), aluminum oxide (Al203), or other suitable material for such an insulating layer. In addition to insulating, the thermal oxide layer  108  also functions herein as a pad oxide layer to provide structural support. 
         [0013]    Next, a second insulating or dielectric layer  110  (referred to herein as a hard mask layer) is deposited on the thermal oxide layer  108 . For this exemplary embodiment, the hard mask layer  110  is approximately 200 nm thick and is formed utilizing one or more layers of silicon nitride (Si3N4), silicon oxynitride (SiON), polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), or other suitable dielectric material. The hard mask layer  110  is deposited on the thermal oxide layer  108  utilizing, for example, a PVD, CVD, screen printing, spin coating, spray coating, or other suitable deposition process. Notably, in this embodiment, both the thermal oxide layer  108  and hard mask layer  110  are utilized in combination as an etch stop for terminating the etching process at controllable depths during subsequent processing steps described below. For example, a photo-resist (PR) layer or mask is formed over the hard mask layer  110 . A suitable portion of the PR layer is removed, and a photolithography (e.g., dry etch) process is utilized to remove a portion (e.g., approximately 0.20 μm wide) of the thermal oxide layer  108  and hard mask layer  110  down to the active surface  101  of polysilicon. 
         [0014]    As shown in  FIG. 1B , a suitable CMOS sidewall spacer formation process is then utilized to form a first sidewall spacer  112  and a second sidewall spacer  114  adjacent to the exposed sides of the thermal oxide layer  108  and hard mask layer  110 . In this embodiment, the width of the spacers  112 ,  114  is approximately  200  nm, and the distance between the spacers  112 ,  114  is approximately 0.16 μm. A PR layer is then formed over the hard mask layer  110 , a suitable portion of the PR layer is removed, and a photolithography or other suitable silicon etch process is utilized to form a trench  116  through the hard mask layer  110 , the thermal oxide layer  108 , the p-epitaxial region  104 , and extending partially into the N+ region  106 . Alternatively, the trench  116  can be formed utilizing a laser direct ablation (LDA) process. In this embodiment, the depth of the trench  116  is approximately 1 μm. Next, as shown in  FIG. 1C , a suitable oxide wet etch process is utilized to remove the sidewall spacers  112 ,  114 . A sacrificial oxide (Sac Ox) layer is then grown approximately 20 nm thick on the exposed surfaces in the trench  116 . The Sac Ox layer is then removed utilizing a suitable oxide wet etch process. 
         [0015]    As shown in  FIG. 1D , an oxide layer  118  is then grown on the exposed surfaces of the trench  116 . In this embodiment, the thickness of the oxide layer  118  is approximately 300 Å. In  FIG. 1E , a p-type gate shield  120  is formed within the trench  116 . The trench  116  is filled with a suitable oxide material to form a field oxide or insulating region  122  adjacent the shield  120 . The oxide region  122  can be formed, for example, utilizing a suitable dielectric insulating material, such as tetraethyl-orthosilicate (TEOS) deposited with a high temperature, low pressure deposition process, such as a vapor deposition process. In a second embodiment, the oxide region  122  can be formed utilizing another suitable dielectric insulating material, such as one or more layers of SiO2, Si3N4, SiON, Ta205, Al203, polyimide, BCB or PBO. 
         [0016]    As described above, the shield  120  is formed with a suitable p-type polysilicon material and electrically connected to the source terminal of the MOSFET device. Notably, the polysilicon (p-type) shield  120  is doped oppositely of the N+ (drift) region in the substrate and adjacent to the trench  116  so that the shield  120  will be effectively depleted when the MOSFET device is turned off. For example, in order to control the dopant type and doping concentration of the p-type shield  120  to enable the depletion to occur, a suitable diffusion process, implant process, or in-situ doping process can be utilized to form the shield  120 . As a result, both the Cgs and Cds of the depleted gate shield trench MOSFET device are substantially reduced compared to existing trench MOSFET devices. Returning to  FIG. 1E , a suitable chemical-mechanical polishing or planarization (CMP) process is then utilized to smooth the surface of the oxide layer  122  down to the nitride material of the hard mask layer  110 . Next, utilizing a PR mask and suitable oxide etch process, the filed oxide region 
         [0017]    As shown in  FIG. 1F , utilizing a PR mask and suitable oxide etch process, a portion of the field oxide region  122  over the shield  120  is removed. An oxide layer approximately 20 nm thick is then grown on the exposed surfaces. The “removed” region is then refilled with an N+ polysilicon material to form a gate structure or region  124 . The surface of the N+ polysilicon material is then planarized down to the hard mask layer  110  utilizing a suitable CMP process. Notably, the hard mask layer  110  functions as a mask to protect the active surface  101  during the CMP process. As shown in  FIG. 1F , for this exemplary embodiment, the polysilicon gate  124  extends approximately 0.40 μm into the p-epitaxial region  104 , the distance between the polysilicon gate  124  and the shield  120  is approximately 0.10 μm, and the distance between the upper surface of the shield  120  and the bottom of the trench  116  is approximately 0.50 μm. 
         [0018]    As shown in  FIG. 1G , utilizing a suitable etch process, a portion of the polysilicon in the gate region  124  is removed down to the surface of the thermal oxide layer  108 . A thermal oxidation process is then utilized to oxidize the polysilicon material in the gate region  124  to a depth of approximately 20 nm. As shown in  FIG. 1H , utilizing a suitable oxide deposition process, a layer  126  of a suitable oxide material (e.g., SiO2) is deposited on the oxidized surface of the gate polysilicon region  124  and the hard mask layer  110 . In this embodiment, the deposited oxide layer  126  is approximately 5000 Å thick. As shown in  FIG. 1I , a suitable CMP process is then utilized to planarize the oxide layer  126  down to the level of the hard mask layer  110 . Next, as shown in  FIG. 1J , a suitable etch process is utilized to remove the nitride material of the hard mask layer  110 . Then, as shown in FIG. IK, a suitable ion implantation process is utilized to deposit a p-type dopant (e.g., Boron, Aluminum or Gallium) with a typical concentration of approximately 5E17 cm-3 into the p-epitaxial region  104  to form the p-channel region  128 . 
         [0019]    Next, as shown in  FIG. 1L , a suitable ion implantation process is utilized to heavily dope the substrate within the p-epitaxial region  104  with n-type semiconductor material, such as, for example, phosphorous, antimony or arsenic, to form an N+ region  130  within the p-channel region  128 . As shown in  FIG. 1M , a suitable process is then utilized to deposit one or more oxide spacers on the sidewalls of the oxide layer  126  to form an oxide spacer  132 . The one or more spacers can be formed utilizing a PVD, CVD, screen printing, spin coating, spray coating, or other suitable oxide deposition process. In one embodiment, for example, the one or more spacers can include TEOS deposited utilizing a high-temperature, low-pressure deposition process, such as vapor deposition. In a second embodiment, the spacers can be formed with one or more layers of SiO2, Si3N4, SiON, Ta205, Al203, polyimide, BCB, PBO, or other suitable insulating or dielectric material. Next, as shown in  FIG. 1N , a suitable silicon etch process is utilized to remove a portion of the n-type material in the N+ region  130  and approximately 0.20 μm of the silicon in the p-channel region  128 . Then, as shown in  FIG. 1O , a p-type dopant, such as, for example, Boron, Aluminum or Gallium, is deposited by ion implantation with a suitable dosage to form P+ region  134  adjacent the p-channel region  128 . 
         [0020]      FIG. 1P  depicts a cross-sectional view of the gate contact region adjacent the active channel region shown in the cross-sectional view depicted in  FIGS. 1A-1O . In  FIG. 1P , a PR mask is formed over the insulating layer  132  (e.g., oxide spacer  132  in  FIGS. 1A-1O ). Utilizing a suitable photolithography process (e.g., oxide dry etch process) is utilized to remove a portion of the insulating layer  132  to form the opening  136  extending to the gate region  124 . In a second embodiment, the opening  136  can be formed, for example, utilizing an LDA process. A p-type dopant, such as Boron, Aluminum or Gallium, is deposited by ion implantation into the opening  136  to form a P+ region as an ohmic contact.  FIG. 1Q  depicts a cross-sectional view of the shield contact region adjacent the active channel region shown in the cross-sectional view depicted in  FIGS. 1A-1O . Referring to  FIG. 1Q , similarly to the process described directly above with respect to  FIG. 1P , an opening  138  is also formed in the insulating layer  132 . The opening  138  extends to the shield region  120 . A p-type dopant, such as Boron, Aluminum or Gallium, is deposited by ion implantation into the opening  138  to form a P+ region as an ohmic contact. Next, as shown in  FIG. 1R , an electrically conductive material is deposited into the openings  136  and  138  utilizing a PVD, CVD, electrolytic plating, electro-less plating, sputtering, or other suitable metal deposition process. In this exemplary embodiment, the electrically conductive material is Tungsten (W) including an adhesion layer of Titanium or Titanium Nitride. However, in a second embodiment, the electrically conductive material can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. 
         [0021]    In  FIG. 1R , the deposited electrically conductive material (e.g., W) is shown with respect to the cross-sectional view of the active channel region. In  FIG. 1S , the deposited electrically conductive material (e.g., W) is shown with respect to the cross-sectional view of the gate contact region. In  FIG. 1T , the deposited electrically conductive material (e.g., W) is shown with respect to the cross-sectional view of the shield contact region. 
         [0022]    In  FIG. 1U , utilizing a suitable metal deposition process, an electrically conductive or metal layer  142  is deposited over the planarized surface of the device  100  as shown. The metal layer  142  is approximately 4 μm thick and formed with an AlCu material. In a second embodiment, the metal layer  142  can formed with one or more layers of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable electrically conductive material. A PR layer or mask is formed and a suitable metal dry etch process is utilized to remove certain portions of the metal layer  142  down to the surface of the silicon. As a result of the etch process, the metal layer  142  forms a source metal interconnect layer that is electrically connected to the N+ (source) region  130  and the p-channel region  128 , as shown in the active channel region depicted in  FIG. 1U . The etched metal layer also forms a gate metal interconnect layer  144 , as shown in the gate contact region depicted in  FIG. 1V . The etched metal layer also forms a source metal interconnect layer  146 , as shown in the shield contact region depicted in  FIG. 1W . A suitable passivation process is then utilized to pattern bond pads or solderable contact pads on the die including the device  100 . A suitable wafer thinning process is also performed to reduce parasitic N++ resistances, and the backside  103  of the die is metallized to form the drain metal on the drain region  106 . 
         [0023]      FIG. 2  depicts a cross-sectional view of a semiconductor device  200  that can be formed utilizing the exemplary process depicted in  FIGS. 1A-1W , in accordance with one exemplary embodiment of the present invention. The cross-sectional view depicted in  FIG. 2  shows the active channel region of the semiconductor device  200 . Referring to  FIG. 2 , the exemplary semiconductor device  200  includes three trenches (e.g., trench  202 ). For ease of understanding, since the three trenches are structured virtually identically, only the one trench  202  will be described. The trench  202  includes a polysilicon gate region  204  disposed over a polysilicon (gate) shield region  206 . The gate region  204  is electrically and physically isolated from the shield region  206  by a dielectric or insulating region  208 . The shield region  206  is electrically connected to the source and thus the source metal layer  210  of the semiconductor device  200 . The trench  202  extends into the n-type drift region  212 . Notably, in accordance with the present invention, the (p-type) shield region  206  is doped opposite to that of the (n-type) drift region  212 , which enables the shield region  206  to deplete when the semiconductor device  200  is in the “off” state. Consequently, the magnitude of the electrical field in the oxide material  208  adjacent the shield region  206  is significantly reduced, and thereby transfers a substantial amount of the stress generated by the electric field to the polysilicon material of the shield region  206  while the power MOSFET device  200  is in the “off” state. The semiconductor device  200  also includes an N++ substrate  214  that forms a drain region of the semiconductor device  200 . The drain region is electrically connected to the drain metal  216 . A channel region  218  is formed in the semiconductor device  200  adjacent a trench. 
         [0024]      FIG. 3  is a schematic block diagram of an electronic system  300 , which can be utilized to implement one exemplary embodiment of the present invention. In the exemplary embodiment shown, electronic system  300  includes a power subsystem  302 , a digital processor unit  304 , and a peripheral subsystem  306 . For example, the digital processor unit  304  can be a microprocessor or microcontroller and the like. The peripheral subsystem  306  includes a memory unit  308  for storing the data processed by the digital processor unit  304 , and an input/output (I/O) unit  310  for transmitting and receiving the data to/from the memory unit  308  and the digital processor unit  304 . In the exemplary embodiment depicted in  FIG. 3 , the power subsystem  302  includes a DC-DC controller  312 , and a power trench MOSFET device  314  including a depleted gate shield utilized to enable and disable the conduction of large currents in the DC-DC controller  312 . The DC-DC controller  312  and power subsystem  302  provide a regulated voltage via line  316  to power the electronic components in the digital processor unit  304  and peripheral subsystem  306 . In the exemplary embodiment shown, the power trench MOSFET device  314  with a depleted gate shield can be implemented, for example, utilizing the power trench MOSFET device  100  with the depleted gate shield depicted in and described with respect to  FIGS. 1A-1W  and  FIG. 2 . In one or more embodiments, the components of the electronic system  300  can be implemented in one or more integrated circuits, wafers, chips or dies. 
         [0025]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiments shown. Therefore, it is manifestly intended that the present application be limited only by the claims and the equivalents thereof.