Abstract:
Secondary side synchronous rectifier driver circuits with adaptive turn-off of each of a pair of synchronous rectifiers in the secondary circuit of isolated and non-isolated transformer coupled power supplies having a continuous inductor current. When a respective turnoff signal is received from the controller, each synchronous rectifier driver senses the synchronous rectifier switch current, and holds the respective synchronous rectifier switch on until the current in the switch goes to zero, indicating a proper charging or discharging of the transformer leakage inductance. This may be done, for example for a FET synchronous rectifier, by sensing the drain-source voltage and turning the FET off when the drain-source voltage goes to zero. This minimizes synchronous rectifier body diode or external Schottky diode conduction and energy loss. Other current sensing techniques may also be used, including but not limited to, current sense resistors and current sensing transformers. Specific embodiments are disclosed.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to the field of switching power supplies.  
         [0003]     2. Prior Art  
         [0004]     The continual trend in operating voltage reduction for modern VLSI ICs has created a need for power supplies with output voltages much lower than 5V. State of the art processors require supply voltages that are as low as 1.25V, with further reductions anticipated in the future to voltages below 1V. Traditionally, single phase or multiple phase buck regulators have been used to generate the required low voltages. The use of simple buck regulators, however, starts being problematic as duty cycles commanded by these low voltages are less than 10% with a power distribution bus of 12V, and the output currents are several tens of amps.  
         [0005]     One way to alleviate this problem is to use voltage and current scaling through the use of a transformer. Although this solves the problems of current, voltage and duty cycle scaling, it introduces other problems that become pronounced, especially when output currents are several tens of amps, for example greater than 30 A. Such systems use synchronous rectification at the output (secondary side) for high efficiency. The synchronous rectifiers on the secondary side are commutated by signals obtained from a controller on the primary side.  
         [0006]     This serves the purpose, to a certain degree, to lower power dissipation at the output rectifiers by using the synchronous rectification. However at high output currents, significant conduction of parasitic or external diodes across the synchronous rectifiers can take place that results in comparatively high losses. Such conduction of output diodes occurs as a result of uncoupled (to the primary) transformer and trace inductances. These inductances effectively appear as an inductance in series with the transformer secondary. The resulting diode conduction might be termed as forced diode conduction, due to stored parasitic energy in these unavoidable inductances.  
         [0007]     Specifically, this loss occurs in the body diode of a synchronous rectifier, or external Schottky diode if used, when the corresponding synchronous FET is turned off from the primary side. The current that has been flowing in the FET gets diverted to the parallel diode and decays to zero amps.  
       BRIEF SUMMARY OF THE INVENTION  
       [0008]     Secondary side synchronous rectifier driver circuits with adaptive turn-off of each of a pair of synchronous rectifiers in the secondary circuit of isolated and non-isolated transformer coupled power supplies having a continuous inductor current are disclosed. When a respective turnoff signal is received from the controller, each synchronous rectifier driver senses the synchronous rectifier switch current, and holds the respective synchronous rectifier switch on until the current in the switch goes to zero, indicating a proper charging or discharging of the transformer leakage inductance. This may be done, for example for a FET synchronous rectifier, by sensing the drain-source voltage and turning the FET off when the drain-source voltage goes to zero. This minimizes synchronous rectifier body diode or external Schottky diode conduction and energy loss. Other current sensing techniques may also be used, including but not limited to, current sense resistors and current sensing transformers. Specific embodiments are disclosed.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a circuit diagram for the basic structure of a prior art current doubling, full wave output transformer coupled buck converter.  
         [0010]      FIG. 2  illustrates the drain-source voltages of FET devices Q 5  and Q 6  of the prior art circuit of  FIG. 1 .  
         [0011]      FIG. 3  shows the diode conduction current waveform in relation to the drain-source voltage waveform for the prior art circuit of  FIG. 1 .  
         [0012]      FIG. 4  shows the absence of diode conduction current in a current doubling, full wave output transformer coupled buck converter incorporating the present invention.  
         [0013]      FIG. 5  is a circuit diagram for a fully isolated current doubling full wave output converter incorporating an embodiment of the present invention.  
         [0014]      FIG. 6  is a circuit diagram for a half wave output converter incorporating an embodiment of the present invention.  
         [0015]      FIG. 7  is a circuit diagram similar to  FIG. 6  showing an embodiment using a sense resistor RS.  
         [0016]      FIG. 8  is a circuit diagram similar to  FIG. 6  showing an embodiment using a current sense transformer CST.  
         [0017]      FIG. 9  is a circuit diagram similar to  FIG. 5  showing an embodiment using a sense resistor RS.  
         [0018]      FIG. 10  is a circuit diagram similar to  FIG. 5  showing an embodiment using a current sense transformer CST.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0019]     First referring to  FIG. 1 , the basic structure for a prior art current doubling, full wave output transformer coupled buck converter may be seen. The present invention relates to the unwanted conduction of either the body diodes of FETs Q 5  and Q 6 , or the Schottky diodes that might be connected with each FET (DQ 5  and DQ 6 ), respectively. The invention is particularly applicable to transformer coupled, switching power supplies operating with a continuous (forward) inductor current.  
         [0020]     In the circuit of  FIG. 1 , transistors Q 3  and Q 2  are turned on during one half cycle while transistors Q 4  and Q 1  are off, with transistors Q 4  and Q 1  being turned on during the alternate half cycle while transistors Q 2  and Q 3  are off. Regulation is provided by a controller varying the duty cycle of transistors Q 3  and Q 2 , and Q 4  and Q 1  during their active half cycle based on a feedback of the output voltage Vout, as is well known in the art. The synchronous rectifier switches Q 5  and Q 6  are switched generally in synchronism with the turn on of the respective primary side switch pair. With transistors Q 3 , Q 2  and Q 5  turned on and the other transistors turned off, the transformer T 1  secondary voltage, which is higher than the output voltage Vout, preferably approximately twice the output voltage Vout, causes the respective output current component to increase through the leakage inductance Lleak and inductor L 1 .  
         [0021]     When transistors Q 3 , Q 2  and Q 5  are turned off and transistors Q 1 , Q 4  and Q 6  are turned on, the transformer T 1  secondary voltage reverses, and the current in inductor L 1  starts to decrease. The current in the leakage inductance Lleak, which is at its peak of approximately Iout, cannot instantaneously reverse, but instead decays with a back EMF exceeding the secondary voltage to turn on the body or Schottky diode DQ 5  associated with transistor Q 5  until the current in the leakage inductance decays to zero. Thus during this period, instead of the leakage inductance and inductor L 2  being coupled to the transformer secondary voltage to cause current to build in inductor L 2 , one end of inductor L 2  is coupled to a voltage one diode forward conduction voltage drop below ground.  
         [0022]      FIG. 2  shows the drain-source voltages of FET devices Q 5  and Q 6  with a non-adaptive gate drive waveform. This diagram assumes that the FET devices Q 5  and Q 6  are switched off, respectively, simultaneously with the associated switching of the primary side switching devices. This waveform results from the presence of the leakage inductance Lleak comprising the secondary referred uncoupled transformer and lead or PCB trace inductances. The current that conducts during this time is triangular with a starting or peak value approximately equal to the output current Iout. This conduction can result in losses that can be significant at low output voltages and high output currents.  
         [0023]      FIG. 3  shows the diode conduction current waveform in relation to the drain-source voltage waveform. In conventionally designed synchronously rectified transformer coupled circuits with just primary side switching information, the secondary side gate voltage terminates prematurely. The diode currents are a function of both the amount of leakage inductance as well as the output current. The average current through each diode can be calculated by using the following formulas:  
         IDQ5   avg     =       IDQ6   avg     =       1.2   ⁢     Iout             ⁢   2       ⁢     NL   leak     ⁢     f     sw   /   leg           2   ⁢   VIN               
 Where: 
        IDQ5 avg =the average current through the diode associated with the FET Q 5      IDQ6 avg =the average current through the diode associated with the FET Q 5      Iout=the output current     N=number of turns on the secondary winding of the transformer     L leak =the sum of the secondary referred leakage and lead line inductances     F sw/leg =the switching frequency for each leg     VIN=the input voltage          
         [0031]     As an example, for a 50 A switching supply operating at 250 KHz from a 12 volt supply:  
               IDQ5   avg     =     IDQ6   avg                 =       1.2   ⁢       (     50   ⁢   A     )     2     ⁢     (     3   ⁢   T     )     ⁢           ⁢     (     50   ⁢   nH     )     ⁢           ⁢     (     250   ⁢           ⁢   KHz     )         2   ⁢     (     12   ⁢           ⁢   V     )                     =     4.688   ⁢           ⁢     A   avg                 
 
         [0032]     Clearly this would result in power dissipation across both diodes that is approximately given by the following formula: 
 
 PDQ 5 avg   =PDQ 6 avg   =IDQ 5 avg   VDQ 5 
 
 PDQ 5 avg   =PDQ 6 avg =(4.688 A) (0.45)=2.109 Watts 
 
         [0033]     Assuming a 0.8V, 50 A power supply, this would represent up to 9% efficiency reduction. To mitigate this efficiency loss as a result of the parallel diode conduction, extra steps can be taken so that the gate drive across the respective synchronous rectifier is kept on until the current through the synchronous rectifier decays to zero, and then rapidly removed to avoid shorting the transformer. This can be accomplished by adapting the gate drive to the time when the current in the synchronous rectifier has decayed to zero, or alternately by monitoring the drain-source voltage of each FET, and removing the gate drive when the drain-source voltage goes to zero (approaches zero, goes through zero and/or starts to reverse).  
         [0034]     The additional gate control circuit needed is minimal and for DC isolated (galvanic isolation) cases, can reside entirely on the secondary side of the transformer T 1 . Referring back to  FIG. 3 , the synchronous rectifier gate drive may be adaptively controlled, as an example, by using a gate control circuit to turn on the respective FET on command of the primary side controller. However, rather than turning off the FET on receipt of a turn-off signal from the controller, holding the respective FET on until the drain-source voltage of the FET begins to reverse, indicating that the current in the FET is beginning to reverse. When this is done, the resulting waveforms are shown in  FIG. 4 . As can clearly be seen from  FIG. 4 , the diode conduction has virtually been eliminated.  
         [0035]     Now referring to  FIG. 5 , a circuit diagram for a fully isolated current doubling full wave output converter incorporating one embodiment of the present invention may be seen. For a fully isolated power supply, the gate drive signals from the controller may be coupled to the secondary side of the transformer T 1  by any convenient isolation means, opto-couplers being shown, though other coupling means, such as transformer coupling could be used if desired (DC isolation (galvanic isolation) generally provides adequate isolation between the primary side and secondary side circuitry). Similarly, the output voltage may be fed back through some coupling means such as an opto-coupler for output voltage regulation purposes, which regulation control may be in accordance with the prior art. Accordingly, details of the regulation circuitry are not shown. With this isolation, the ground or neutral connections PSG on the primary side circuitry may be different from the secondary side ground or neutral SSG.  
         [0036]     The gate drive signals VG 5  and VG 6  are used to cause the respective gate control circuits to each hold the respective FET on during the normal on-time of the respective FETs Q 5  and Q 6 . When the respective gate drive signal VG 5  or VG 6  is removed (goes low in the embodiment shown), the respective gate control circuit will hold the respective FET on as long as the drain of the respective transistor remains at a voltage lower than the voltage on its source. When the respective drain voltage begins to rise above its source voltage (begins to reverse), the respective gate control circuit will rapidly turn off the device. In a way, the gate control circuit functions somewhat like an RS flip-flop, though is much more sensitive to the source-drain voltage (or other current sensing signal) around zero for the turn-off function.  
         [0037]     Referring again to  FIG. 5 , when transistor Q 5  is on, current will be flowing through the leakage inductance in the direction of the arrow I sec , and through inductor L 1  to the output. Current will also be flowing through inductor L 2  to the output (based on the assumption of a continuous conduction converter). At the moment transistors Q 1 , Q 4  and Q 6  are turned on, the secondary voltage will reverse. However the current in the leakage inductance cannot instantaneously reverse, but instead, with transistor Q 5  being held on by the gate control circuit, and neglecting voltage drops across transistors Q 5  and Q 6 , the current in the leakage inductance Lleak will decay at a rate: 
 
 V   s   =L   leak   di   leak   /dt  
 
 Where: 
        V s =the secondary voltage     i leak =the current in the leakage inductance        
 
         [0040]     With transistor Q 5  still turned on, the source to drain current in transistor Q 5  is equal to the leakage inductance current plus the current through inductance L 2 . The leakage inductance current needs to go through zero and increase in the reverse direction to equal the current through inductance L 2  before the current in transistor Q 5  starts to reverse, and the respective gate control circuit turns transistor Q 5  off.  
         [0041]     For purposes of illustration and not for purposes of limitation, the embodiment of the present invention herein before disclosed has been disclosed with respect to a full bridge primary side switching circuit. However the primary side switching circuit may be a half bridge or any other single ended topology as are well known in the art.  
         [0042]     Now referring to  FIG. 6 , an embodiment of the present invention using a half wave secondary side output circuit may be seen. As before, the converter operates with a continuous current Iout in the inductor L 1 . In this embodiment, the primary side uses two switching transistors Q 1  and Q 2 , and two diodes D 1  and D 2 , with regulation being attained by control of the duty cycle of transistors Q 1  and Q 2 . When transistors Q 1  and Q 2  are turned on, transistor Q 3  is turned on (VG 3  is driven high by the controller, causing the respective gate control circuit to drive the gate of transistor Q 3  high, and VG 4  is driven low. However, because of the current flow through transistor Q 4  and the inductor L 1  at the time of switching, the voltage across the transistor Q 4  is negative. Thus the respective gate control circuit will leave transistor Q 4  on even though the control signal VG 4  has gone low. Also at the time of switching, the current in the leakage inductance Lleak will be zero, but will fairly rapidly increase. When the current in the leakage inductance Lleak begins to exceed the current in the inductor L 1 , the current through transistor Q 4  will start to reverse, causing the respective gate control circuit to turn off transistor Q 5 . Thus transistor Q 4  has been kept on until the current in the transistor goes to zero (or begins to reverse), preventing current flow and power loss through diode DQ 4  during this time.  
         [0043]     When transistors Q 1  and Q 2  are turned off, transistor Q 4  is turned on (VG 4  driven high) and VG 3  is driven low. At the time of switching, the current in the leakage inductance Lleak is at a maximum. Consequently the voltage drop across transistor Q 3  is negative, so the respective gate control circuit will keep transistor Q 3  on until the current flow through and thus the voltage drop across transistor Q 3  becomes positive, at which time the gate control circuit will turn off transistor Q 3 . Thus transistor Q 3  has been kept on until the current in the transistor goes to zero (or begins to reverse), preventing current flow and power loss through diode DQ 3  during this time.  
         [0044]     In the embodiment of  FIG. 6 , the control signals VG 3  and VG 4  may be isolated such as by using opto-couplers, or may be directly connected to the controller, depending on whether a fully isolated power supply is desired or needed.  
         [0045]     Now referring to  FIG. 7 , an embodiment using a sense resistor RS instead of the drain-source voltage may be seen. The circuit functions the same way, with the gate control circuit sensing the voltage drop across the resistor rather than the drain-source voltage on the transistor. Alternatively, the gate control circuit could sense the voltage across both the transistor and the resistor.  FIG. 8  shows an embodiment using a current sense transformer CST. Either the current sense resistor or the current sense transformer could be on the other side of transistors Q 3  and Q 4 , and of course could be used with other embodiments, such as the full wave embodiment of  FIG. 5 , as shown in  FIGS. 9 and 10 , respectively.  
         [0046]     Also in any of the foregoing embodiments, or in other embodiments that may be obvious to those skilled in the art, the gate control circuit may be part of or integrated into the primary side controller if DC isolation is not required.  
         [0047]     While certain preferred embodiments of the present invention have been disclosed and described herein, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.