Abstract:
In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.

Description:
FIELD 
     The present invention relates to integrated circuit packages, and more particularly to removing heat from an integrated circuit package. 
     BACKGROUND 
     In electronic system-in-package (or package-in-package) technology, a single package comprises one or more dice, where one or more of these dice are in their own individual packages. An example is provided in  FIG. 1 .  FIG. 1  is a simplified, plan view (not to scale) illustration of a flip chip stacked module package. A die  102  is flip chipped, with its active side facing a package substrate  104 . In the flip chip process, also formally called the Controlled Collapse Chip Connection (C4) evaporative bump process, conductive bumps ( 106 ) are formed and soldered to pads on the active side of the die  102 . The solder bumped die  102  is then placed face down onto matching bonding pads on the package substrate  104 , which may be a multilayer organic substrate. The assembly is reflowed so that the conductive bumps  106  are soldered to pads on the package substrate  104  so as to provide electrical connection between the active side of the die  102  and the package substrate  104 . The conductive bumps  106  also provide a load bearing link between the die  102  and the package substrate  104 . Usually, the conductive bumps comprise solder. The package substrate  104  includes electrical interconnects so that the conductive bumps  106  are electrically connected to at least some of a plurality of package contacts  108 . 
     Attached to the backside of the die  102  is a package  110 . This is a wirebond package, where a die  112  is attached to a package substrate  114 , and electrical connection is provided by way of wirebonds from the active side of the die  112  to pads on the package substrate  114 . As an example, one such wirebond, labeled  116 , is shown. Wirebonds from pads on the outer side of the substrate package  114  provide electrical connection to the package substrate  104 . For example, one such wirebond, labeled  118 , is shown. Attached to the package  110  is a die  120 , which is wirebonded to the package substrate  104 . For example, one such wirebond, labeled  122 , is shown. 
     An epoxy resin, sometimes referred to as an underfill, is usually applied to help compensate for the difference in the coefficient of thermal expansion (CTE) between the die  102  and the package substrate  104 , and to prevent moisture damage. The assembly may also be capped with a liquid epoxy for further protection, resulting in the final system-in-package  124 . 
     For some applications, the die  102  may comprise digital logic circuits, the package  110  may be a memory module, and the die  120  may comprise analog circuits. 
     As more and more integration takes place in system-in-package technology, thermal management may present a challenge. Conventional thermal management includes thermal vias in the package substrate  104 , and the use of heat spreaders. However, for heat to escape from the die  120  to the package contacts  108 , the heat flows from the die  120  through various materials in the package  110 , the flip-chipped die  102 , the underfill, and the package substrate  104 , and through the package contacts  108  before escaping the system-in-package  124 . It would be desirable to provide a system-in-package technology with efficient thermal pathways for heat to escape. 
     SUMMARY 
     In an embodiment, a die is embedded in a package substrate. The package substrate has package contacts. Thermal vias in the package substrate couple the die to at least some of the package contacts. At least one of the thermal vias has a cross-sectional shape substantially similar to a union of at least two overlapping circles. 
     In another embodiment, a hole is formed in a package substrate core, where the package substrate core has a first side with a first metal layer, and a second side with a second metal layer. Tape is placed on the second side of the package substrate core. A die is then placed into the hole, the die having a first side, and a second side proximal to the tape. A substrate is formed on the first side of the die, the first metal layer, and the first side of the package substrate core. Thermal vias are formed in the substrate to couple to the first side of the die at thermal hotspots of the die. 
     In another embodiment, a hole is formed in a package substrate core, where the package substrate core has a first side with a first metal layer, and a second side with a second metal layer. Tape is placed on the second side of the package substrate core. A die is placed into the hole, where the die has a first side and a second side proximal to the tape. A first substrate is formed on the first side of the die, the first metal layer, and the first side of the package substrate core. The tape is removed. A second substrate is formed on the second side of the die, the second metal layer, and the second side of the package substrate core. Thermal vias are formed in the second substrate to couple to the second side of the die at thermal hotspots of the die. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan view of a conventional multi-module integrated circuit package. 
         FIGS. 2A and 2B  illustrate an integrated circuit package with an embedded die and thermal vias. 
         FIG. 3  is a plan view of a portion of an integrated circuit package with an embedded die and thermal vias. 
         FIG. 4  is a plan view illustrating a procedure for embedding a die in an integrated circuit package substrate with thermal vias. 
         FIG. 5  illustrates a cross-sectional plan view of a thermal via covering a thermal hotspot. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     In the description that follows, the scope of the term “some embodiments” is not to be so limited as to mean more than one embodiment, but rather, the scope may include one embodiment, more than one embodiment, or perhaps all embodiments. 
       FIG. 2A  illustrates a simplified plan view (not drawn to scale) of a system-in-package  200 , where a die  202  is embedded within a package substrate  208 . As in  FIG. 1 , the system-in-package  200  comprises the flip chipped die  102 , and the die  112  in its own package  110 . In the particular embodiment of  FIG. 2A , the active side of the die  202  faces away from the side of the package substrate  208  that is connected to the package contacts  108 . Copper plating (or contacts) on the active side of the die  202  are shown in  FIG. 2A , where one such example of copper plating is labeled as  204 . Although not explicitly shown, the copper plating  204  is electrically connected to traces in the package substrate  208  so as to be electrically connected to at least some of the package contacts  108 . 
     In the illustration of  FIG. 2A , thermal vias in the package substrate  208  are coupled to the backside of the die  202 , and are coupled to at least some of the package contacts  108  so that an efficient thermal path may be provided between the die  202  and some of the package contacts  108 . One such thermal via is labeled as  206 . The thermal vias may comprise copper, for example, so that they may also be electrically conductive. 
     For a thermal via not positioned directly over a package contact, a trace may be formed within the package substrate to continue the thermal path to one of the package contacts. This is illustrated in  FIG. 2B , where a trace  210  provides a conductive thermal path from the thermal via  206  to the package contact  108 , where it is assumed that there is no package contact positioned directly underneath the thermal via  206 . The orientation of the view illustrated in  FIG. 2B  is orthogonal to the view illustrated in  FIG. 2A , where  FIG. 2B  illustrates a slice of an embodiment along the die  202  parallel to the face of the package substrate  208 . For ease of illustration,  FIG. 2B  is not drawn to scale, and is not scaled to the illustration in  FIG. 2A . In  FIG. 2B , the dashed line  202  represents the outline of the die  202  in  FIG. 2A , and the dashed line  208  represents the outline of the package substrate  208  in  FIG. 2A . These outlines are dashed to indicate that they lie above and below the slice through the die  202  that provides the view of  FIG. 2B . 
     For some embodiments, the die  202  may be embedded in the package substrate  208  so that its active side faces the side of the package substrate  208  that is attached to the package contacts  108 . For such embodiments, some of the thermal vias may, in addition to providing a thermal path, also provide electrical connection to some of the active components on the active side of the die  202  to one or more of the package contacts  108 . 
       FIG. 3  is a plan view (not to scale) of a portion of the package substrate  208  with the embedded die  202 , but in greater detail than the illustration of  FIG. 2A . The package substrate of  FIG. 3  is shown to be multilayered comprising a metal layer  302 , a substrate  304 , a metal layer  306 , a core  308 , a metal layer  310 , a substrate  312 , and a metal layer  314 . The metal layers may comprise copper. Various materials and laminates may be used for the substrates and the core. The core  308  may comprise the same material as used for the substrates. For some embodiments FR-4 (Flame Retardant  4 ) may be used for the core  308  or the substrates, or polyimide may be used, for example. 
     The plan view illustrated in  FIG. 3  is simplified because it does not show openings in the metal layers, except for the openings to the die  202 . That is, the illustration is simplified in the sense that the plan view of the metal layers, which is a slice of an embodiment in a direction perpendicular to the direction of view in the illustration, shows the metal layers as rectangles. In practice, etching is performed on the metal layers so that electrical connections may be made to various components. 
     Copper plating on the backside of the die  202  thermally couples various hotspots to the thermal vias  206 . One such example of the copper plating is labeled as  316  in  FIG. 3 . For some embodiments, a thermal analysis may be performed on the die  202  so that the copper plating  316  is deposited on the hotspots, or at least some of the hotspots. This allows fine tuning of the thermal management. 
     For some embodiments, the active side of the die  202  may face the metal layer  306 , in which case some of the copper plating  316  may provide electrical connection to various devices on the active side as well as thermal coupling. For such embodiments in which the active side faces the metal layer  306 , the copper plating as represented by the label  204  may not necessarily be needed. 
       FIG. 4  shows various plan views (not to scale) illustrating a procedure for embedding the die  202  into the core  308 , where the procedure sequence is indicated by the letters A through E. Starting with the core  308  in A, a hole is drilled into the core  308  in B. In B, the metal layers  306  and  310  have been deposited on both sides of the core  308 , and etching has been performed on these metal layers to provide the traces. In C, a tape  402  is attached to the bottom of the core  308 , and in D the die  202  is dropped into the hole that was drilled in the core  308 . The die  202  includes the copper plating  204  and  316 . The substrate  312 , such as FR-4, is laminated on top of the assembly. This substrate material is indicated by crosshatches. In E, the tape  402  has been removed and the substrate  304  is laminated on the bottom, again crosshatched. Thermal vias  206  are formed into the substrate  304  to make contact with the copper plating  316 . 
     For ease of illustration, the previous drawings illustrated the thermal vias  206  as being uniformly positioned along the bottom face of the die  202 , but in practice, because the thermal vias  206  are coupled to hotspots on the die  202 , the positioning of the thermal vias  206  may not be uniform. Also, because the thermal vias  206  are concentrated about various hotspots, the shape for some of the thermal vias  206  is not expected to be substantially cylindrical as for the case of power or signal vias. Some of the thermal vias  206  may be the union of two or more cylinders that overlap each other. 
       FIG. 5  illustrates a cross-sectional plan view (not necessarily drawn to scale) of a thermal via comprising a plurality of individual vias. The cross-sectional view is a slice taken parallel to the bottom face of the die  202  and substantially perpendicular to the thermal vias  206 . The cross-sectional plan view of the measured hotspot which the thermal via is to cover is illustrated by the irregular shape having the outline labeled  502 . The shape of the thermal via is formed from the union of a number of overlapping cylindrical shapes, which appear as circles in the illustration. The outer envelope of the union of these circles is illustrated as a solid line with the label  504 . The parts of the circles that are not part of the envelope are illustrated with dashed lines. 
     In the illustration of  FIG. 5 , the thermal via does not completely cover the thermal hotspot  502 , but for some embodiments a shape for a thermal via may be synthesized by forming the union of more circles so as to completely cover the thermal hotspot. In practice, perfect circles may not be realized, so that the cross-sectional shape of the thermal via may only be substantially similar to a geometric shape formed by the union of overlapping circles. 
     Various modifications may be made to the described embodiments without departing from the scope of the invention as claimed below. For example, in E of  FIG. 4 , thermal vias could be formed in the substrate  312  instead of the substrate  304 . That is, the substrate  312  that is applied before the tape  402  is removed may contain the thermal vias.