Abstract:
In a bridged, pipelined network (FIG. 1), a network-to-host bridge ( 140 ) identifies the address space of a host computer (FIG. 2) as not being contained within the host computer memory space ( 120 ). During the removal of the host computer ( 100 ) and its replacement by a new host computer, the network-to-host bridge ( 140 ) momentarily locks out traffic (FIG. 3, step  320 ) in order to disable peripheral components (FIG. 1,  160, 180 ) from initiating bus transactions. When the new host computer is installed (FIG. 3, step  320 ) and the bus lockout is removed (step  340 ), the new host memory area is protected from direct memory access transactions which were stored in the bus hierarchy during the host computer swap.

Description:
FIELD OF THE INVENTION 
     The invention relates to computer systems and, more particularly, to a method for host protection during hot swap in a pipelined network. 
     BACKGROUND OF THE INVENTION 
     In a pipelined network, such as a Peripheral Component Interconnect (PCI) network, a bridge can be used in order to provide a means of conveying information across multiple constituent bus segments. The use of multiple bus segments enables the network to include more peripheral components than would be possible if only a single bus segment were to be used. Additionally, the use of a bridge in a pipelined network provides a means of increasing the aggregate bandwidth of the network by allowing transactions to initiate and terminate within a bus segment without involving the entire network. 
     In a high-availability system which incorporates a bridged multi-segmented network, transactions which are initiated at a peripheral component which is interfaced to a secondary bus segment can remain in the network since each bridge typically incorporates a capability to store a transaction as the transaction is bridged between bus segments. This capability allows the bridge to forward the transaction through the network hierarchy and place the transaction on a target bus as the intervening buses become available and able to accept the new transaction. Among these are transactions which allow the direct memory access of areas within the host computer memory space by particular peripheral components. 
     In a bridged, pipelined network operating in a high-availability environment, a hot swap of a host computer while a direct memory access transaction exists at a bridge located within the bus hierarchy can degrade the new host computer. This event can be made possible if the new host computer includes a memory allocation scheme which is not identical to the memory allocation scheme of the previous host computer. Therefore, during the moments immediately after the hot swap of the host computer, direct memory access transactions intended for the previous host computer can degrade and, in some cases, temporarily suspend (i.e. crash) operations on the network. 
     Therefore, what is needed, is a method for host protection during hot swap in a bridged, pipelined network. This type of method can be useful in  5  preserving the integrity of the new host computer after the removal and replacement of the previous host computer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is pointed out with particularity in the appended claims. 
     However, a more complete understanding of the invention may be derived by reading the specification herein in conjunction with the figures wherein like reference numbers refer to like components, and; 
     FIG. 1 is a block diagram for an architecture in which a method for host protection during hot swap in a bridged, pipelined network may be practiced in accordance with a preferred embodiment of the invention. 
     FIG. 2 is an illustration of an address space used by a candidate bridge in a pipelined network in accordance with a preferred embodiment of the invention; and 
     FIG. 3 is a method for host protection during hot swap in a bridged, pipelined network. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A method for host computer protection during hot swap in a bridged, pipelined network preserves the integrity of the network as well as the host computer during critical hot swap operations. The method protects the host computer without requiring a reset of the various segments of the network after the hot swap of the host processor. Therefore, the method is particularly useful in high-availability applications where a reset of the network bus would be highly undesirable. Additionally, the method can be used to protect the memory of the host processor from direct memory access transactions intended for the previous host processor. The method does not require additional hardware, and can be executed without violating the constraints of the Peripheral Component Interconnect (PCI) specification. 
     FIG. 1 is a block diagram for an architecture in which a method for host protection during hot swap in a bridged, pipelined network may be practiced in accordance with a preferred embodiment of the invention. In FIG. 1, host computer  100  interacts with peripheral components  160  and  180  which are interfaced to primary and secondary bus segments  150  and  190 , respectively. Host computer  100  accesses bridge window register  130  in order to configure each bridge and assign address ranges for bus segments  150  and  190 . Host computer  100  includes central processing unit  110  and memory space  120 . Although the network of FIG. 1 illustrates a bus hierarchy which consists of only a primary and secondary bus segment, this is not intended to limit the scope of the invention in any way. The two-level bus hierarchy of FIG. 1 is intended to provide a simple and easily understandable environment in which the invention may be practiced. More complex bus hierarchies are possible without diminishing the utility of the various aspects of the present invention. 
     In FIG. 1, network-to-host bridge  140  provides host computer  100  with access to primary bus segment  150 . In a similar manner, secondary bridge  170  provides access secondary bus segment  190 . It is generally anticipated that each bridge is an intelligent repeater that incorporates a pipelined capability that allows messages and transactions to be conveyed in directions both toward and away from host computer  100 . Each bridge allows arbitration within a particular segment and allows this arbitration to occur independently of the other bus segment. 
     In the context of the present example, it is contemplated that the pipelined network of FIG. 1 incorporates a store-and-forward capability. This allows messages to be stored at bridges  140  and  170 , thereby allowing each bridge to hold a particular message or transaction until the succeeding bus segment becomes available to accept the transaction. This store-and-forward capability is especially useful in multilevel architectures where bus segments can become congested with local bus traffic. 
     In the bridged, pipelined network of FIG. 1, it is anticipated that an address space of a particular size is used by the network. Thus, when the pipelined network of FIG. 1 is designed in accordance with the PCI specification, a four-gigabyte address space is used. Additionally, it is anticipated that both network-to-host bridge  140  and secondary bridge  170  identify address ranges which cross each bridge in the upstream direction (meaning transactions which move toward host computer  100 ) and address ranges which cross each bridge in the downstream direction (meaning transactions which move away from host computer  100 ). Through the use of these address ranges, transactions can be properly directed from host computer  100  towards a particular peripheral component, and from a particular peripheral component toward host computer  100 . 
     In accordance with the PCI specification, transactions from peripheral components, such as peripheral components  160  and  180 , may include direct memory accesses of memory space  120  within host computer  100 . Thus, a direct memory access transaction can initiate from peripheral component  180 , through secondary bridge  170 , across primary bus segment  150 , and terminate at network-to-host bridge  140 . Through the appropriate use of the aforementioned upstream and downstream address ranges, each transaction can be properly routed through the network of FIG.  1 . In the event that network-to-host bridge  140  does not recognize the transaction as belonging to host computer  100 , network-to-host bridge  140  does not claim the transaction. In the event that the transaction includes an address which corresponds to one of peripheral components  160 , the appropriate one of peripheral components  160  claims the address and executes the transaction. In the event that neither network-to-host bridge  140  nor one of peripheral components  160  claims the transaction, a period of time is allowed to elapse, and the transaction is dropped. When this occurs, network-to-host bridge  140  can raise an error flag that indicates that the transaction has been dropped. 
     Although FIG. 1 has been described as including a network which conforms to conventional PCI bus standards, primary and secondary bus segments  150  and  190  can represent any hierarchical parallel bus structure that incorporates a bridged, pipelined architecture for expanding the number of peripherals which can be interfaced with each bus segment. 
     FIG. 2 is an illustration of an address space used by a candidate bridge in a pipelined network in accordance with a preferred embodiment of the invention. Thus, for example, the address space of FIG. 2 can represent the global address space for the bridged, pipelined network of FIG. 1 when network-to-host bridge  140  and secondary bridge  170  represent bridges used in Peripheral Component Interconnect equipment. Additionally, address range  200  can represent those addresses which lie upstream of network-to-host bridge  140 , meaning that these addresses exist within memory space  120 , while address range  250  represents those addresses which lie downstream of network-to-host bridge  140 , meaning that these addresses do not lie within memory space  120 . For the example of FIG. 2, boundary  255  provides the boundary between address ranges  200  and  250 . 
     In a preferred embodiment, the value of boundary  255  is accessible to host computer  100 . Host computer  100  functions to allocate portions of the address ranges  200  and  250  by way of bridge window register  130 . It is anticipated that when using current PCI-compliant networks, host computer  100  is capable of only extending boundary  255  in order to direct transactions in an upstream or downstream direction. However, in the event that additional registers can be incorporated into network-to-host bridge  140 , a more flexible manipulation of the address space of FIG. 2 can be achieved. For example, address range  200  could be segmented in order to allow multiple regions within the range to correspond to upstream address ranges, while regions in-between can correspond to downstream address ranges. 
     In a preferred embodiment of the invention, boundary  255  is advantageously manipulated in order to protect memory space  120  when host computer  100  is swapped. When host computer  100  is swapped, the address range corresponding to locations within memory space  120  is modified. Desirably, bridge window register  130  modifies boundary  255  in a manner which causes address range  250  to increase in size, while address range  200  decreases in size. In some instances, it may be advantageous for bridge window register  130  to cause boundary  255  to move so that address range  250  encompasses all of the address space of FIG. 2, thereby eliminating address range  200  altogether. 
     By modifying boundary  255  in order to reduce the size of (or eliminate altogether) address range  200 , the likelihood of a transaction affecting memory space  120  is reduced or eliminated entirely. Therefore, when the new host is inserted in place of host computer  100 , network-to-host bridge  140  will not enable any transactions, such as direct memory accesses, to affect memory space  120  of the new host computer (which is not shown in FIG.  1 ). Therefore, any transaction which exists at either primary bus segment  150  or secondary bus segment  190  will not be forwarded to memory space  120 . Desirably, transactions intended for memory space  120  are dropped when they remain unclaimed by any one of peripheral components  160  or  180 , or the new host computer. 
     In the event that additional registers can be incorporated into network-to-host bridge  140 , these registers can be used to specify special actions for a particular address range. Thus, transactions which correspond to a particular address range (or ranges) can be purged or more positively acted upon as opposed to merely allowing a transaction to drop. This technique prevents error flags from being raised in response to unclaimed transactions being dropped by bus segment  150  or  190 . In addition to purging transactions, other special actions could include ignoring a transaction, claiming a transaction and returning a fixed data pattern, or aborting the transaction. Further, the special action registers could be configured to enable a transaction which is dependent upon the originator of the transaction. Thus, transactions originating from a particular peripheral which may be behaving erratically can be prevented from affecting a host computer. 
     FIG. 3 is a flowchart of a method for host computer protection during hot swap in a bridged, pipelined network. The apparatus of FIG. 1 is suitable for performing the method of FIG. 3, although networks functionally similar or equivalent to FIG. 1 may be used. The method of FIG. 3 begins at step  300  where the host computer memory address space subject to later exclusion is determined. It is contemplated that this includes a substantial portion of the host computer&#39;s memory space. 
     At step  310 , a network-to-host bridge initiates an arbitration lockout command in order to preclude peripherals and other bridges from initiating transactions. During step  310 , it is anticipated that peripherals interfaced to primary and secondary bus segments of the network are precluded from initiating transactions, but can respond to transactions initiated by a network-to-host bridge. This arbitration lockout ensures that the bus segments remain in a predictable and definite state during step  320 . At step  320 , a host computer is removed, and a new host computer is inserted in its place. The precise actions that constitute step  320  may include either the physical or logical swapping of a host computer. It is anticipated that this host computer swap is the result of a host fault or software fault or for the purposes of upgrade or latent fault detection. 
     In step  330 , the contents of a bridge window register is modified in order to allocate the bridge window such that vulnerable host memory space is excluded from the address range indicative of the previous host computer memory space. Preferably, this entails a bridge window register conveying a designation that the host computer memory space corresponds to a location outside of the actual memory space. One technique by which this can be accomplished is by way of extending a boundary of an address range which identifies memory locations downstream of the host computer memory space, as discussed in relation to FIG.  2 . 
     At step  340 , the new host computer removes the arbitration lockout thereby enabling the peripheral components interfaced to primary and secondary bus segments to initiate transactions. During this time, transactions that can affect the memory space, such as direct memory accesses, are forbidden from occurring. When these transactions are not forwarded across the network-to-host bridge, an error flag is raised on a primary bus segment. This error flag notifies the new host computer that transactions intended for the memory space of the previous host computer are being dropped by the primary bus segment. 
     In the event that special action registers are in use, step  340  need not lead to generation of error flags when while transactions intended for the previous host memory space are being received. The special action registers can be employed purge transactions from the bridge, claim and ignore the transaction, claim a transaction and return a fixed data pattern, and claim a transaction and perform a target abort. The special action register can also perform a particular action which is dependent on the originator of the transaction. 
     At step  350 , the host computer determines that address ranges for upstream transactions can no longer degrade the host computer. Step  350  can be performed in response to the new host computer no longer receiving error flags which indicate that transactions are being discarded. Thus, after initial error flags have been received, the host computer may determine that such an error flag has not been received within a predetermined time period, thereby determining that transactions addressed to the previous host computer memory space are no longer occurring. 
     Step  350  can also include the new host computer conveying a new address range to peripheral components interfaced to a bus segment. These new address ranges correspond to the new host computer memory space wherein a transaction will not degrade the performance of the host computer. Step  350  may also include reading a status of a peripheral in order to determine that the peripheral component has received the new address range for the memory space of the new host computer. 
     At step  360 , a bridge window modifies an address range in order to designate the address range of the host computer as corresponding to a location within the actual host computer memory space. This step allows transactions properly addressed to the memory space of the new host computer to pass in the upstream direction through the network-to-host bridge and into the memory space of the new host computer. 
     In conclusion, a method for host computer protection during hot swap in a bridged, pipelined network preserves the integrity of the network as well as the host computer during critical hot swap operations. The method protects the host computer without requiring a reset of the various segments of the network after the hot swap of the host processor. Therefore, the method is particularly useful in high-availability applications where a reset of the network bus would be highly undesirable. The method does not require additional hardware, although additional hardware such as special action registers can increase the flexibility of the method. Additionally, the method can be executed without violating the constraints of the Peripheral Component Interconnect (PCI) specification. 
     Accordingly, it is intended by the appended claims to cover all modifications of the invention that fall within the true spirit and scope of the invention.