Abstract:
It is an object of the present invention to provide a method, a program, and an apparatus for processing a moving image, allowing efficient and smooth decoding in a simple configuration without heavily depending on the functions of an OS. Herein disclosed is a method for processing a moving image using a plurality of processing units, comprising: a step of dividing a frame of the moving image into a plurality of slices, where a number of the plurality of slices is not a multiple of a number of the plurality of processing units; a processing step, assigned to each of the plurality of slices, for processing each of the plurality of slices; and a switching step for executing slice switching, which switches between the slices to be processed, in the processing step. The method according to the present invention, not limited to the processing of moving images, allows efficient and smooth decoding in a simple configuration, even if the number of slices is not an integer multiple of the number of the processing units, without heavily depending on the functions of an OS.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a method, program and apparatus for processing moving images using a plurality of processing units. 
       BACKGROUND ART 
       [0002]    In general, information quantities of moving images are much larger than for still images, and when being used with communication media and storage media, compression technologies with higher efficiency than for still images are required. Preferable compression technologies for such purposes include, for example, video coding/decoding formats (MPEG1, MPEG2 and MPEG4, which are below referred to in general as MPEG) defined by the MPEG (Moving Picture Experts Group), which is an international standards committee for image compression, the JPEG format (Joint Picture Experts Group) and the JPEG2000 format. 
         [0003]    The H.264/AVC format (Advanced Video Coding: ISO/IEC14496-10, below referred to as AVC), which has been standardized in recent years, is a coding standard that improves compression performance by a factor of 1.5 to 2 in comparison with the conventional MPEG2 and MPEG4 video coding formats. Japanese Patent Application Laid-Open Publication No. 2006-229411 discloses an AVC intra coding format (below referred to as the AVC intra standard). The high compression performance of this format is achieved by improving efficiency of (1) an intra prediction scheme that utilizes correlations within (intra) a frame and (2) a variable block movement prediction scheme that utilizes relationships between (inter) frames. Using this method, even in a case in which intra coding of coding for still images is used for moving images, it has been verified that higher compression performance relative to JPEG or JPEG2000 can be achieved. 
         [0004]    Meanwhile, for faster computing, processing is being performed using a plurality of cores or a plurality of CPUs. Processing using the plurality of cores or the plurality of CPUs is mainly implemented under the control of functions of an OS (operating system). 
         [0005]    In processing of moving images, further increases in speed, with high reliability being maintained, are required. For improved reliability and speeding up of processing, moving images are processed using, for example, a plurality of cores or a plurality of CPUs under the control of an OS. 
       DISCLOSURE OF INVENTION 
     Problems to be Solved by the Invention 
       [0006]    To process a moving image using a plurality of cores or a plurality of CPUs, the moving image to be processed needs to be divided and assigned to each of the core or the CPU. According to the abovementioned coding format, a moving image is commonly processed by dividing image data constituting the moving image into a pre-determined number of slices (each a unit that can be processed independently). Such a method for decoding a moving image, by assigning to a plurality of cores or a plurality of CPUs under the control of a conventional OS, has the following problems. 
         [0007]    If processing using a plurality of cores or a plurality of CPUs is implemented under the control of a conventional OS, when the conventional OS generates a new processing, for example, in response to a mouse operation by a user, processing distributed between a plurality of cores or a plurality of CPUs needs to be re-distributed. Consequently, processing efficiency thus obtained may not be simply proportional to the number of cores or CPUs being used. 
         [0008]    In addition, if a switching interval of the switch between the CPUs is not sufficiently small with respect to the processing time of the CPUs, certain CPUs may have a heavier workload than others and thus the plurality of CPUs may not efficiently used. On the contrary, an overly small switching interval may increase the overhead of the switching, thus deteriorating the performance of the whole processing. 
         [0009]    In addition, the number of slices obtained by dividing the image data may not be an integer multiple of the number of the plurality of CPUs available. In such a case, the image data cannot be efficiently distributed on the basis of the number of the CPUs. Thus, certain slices may be decoded later than other slices. This makes decoding of a piece of image data slower and may interrupt playback if input speed of the moving image is high. 
         [0010]    Thus, the present invention is made in view of the abovementioned problems, and it is an object of the present invention to provide a method, a program, and an apparatus for processing a moving image, allowing efficient and smooth decoding in a simple configuration, even if the number of slices is not an integer multiple of the number of processing units such as CPUs, by appropriately providing a switching interval for the switch between CPUs, without heavily depending on the functions of an OS. 
         [0011]    It is another object of the present invention to provide a method, a program, and an apparatus for processing, not limited to the processing of moving images, allowing efficient and smooth decoding in a simple configuration, even in a case where the number of slices is not an integer multiple of the number of the processing units, by appropriately providing a switching interval for the switch between the processing units, without heavily depending on the functions of an OS. 
       Means for Solving the Problems 
       [0012]    In accordance with a first aspect of the present invention, there is provided a method implemented by a computer for processing a moving image using a plurality of processing units, comprising: a step of dividing a frame of the moving image into a plurality of slices, where a number of the plurality of slices is not a multiple of a number of the plurality of processing units; a processing step, assigned to each of the plurality of slices, for processing each of the plurality of slices; and a switching step for executing slice switching, which switches between the slices to be processed, in the processing step. 
         [0013]    The aforementioned method comprising: a step of dividing a frame of the moving image into a plurality of slices, where a number of the plurality of slices is not a multiple of a number of the plurality of processing units; a processing step, assigned to each of the plurality of slices, for processing each of the plurality of slices; and a switching step for executing slice switching, which switches between the slices to be processed, in the processing step, allows efficient and smooth decoding in a simple configuration, even in a case where the number of slices is not an integer multiple of the number of processing units such as CPUs, by appropriately providing a switching interval for the switch between the processing units, without heavily depending on the functions of an OS. In the aforementioned method, the processing units comprise a plurality of cores that constitute a CPU, or a plurality of CPUs. 
         [0014]    According to the present invention, the switching step may comprise: a step of executing an event generation instruction for generating an event triggering processing of another slice when a processing of the slice progresses to a predetermined position; and a step of executing an event standby instruction for waiting for an event to be generated by the event generation instruction and triggering processing of the slice in response to the event. 
         [0015]    In the aforementioned method, the switching step comprising: a step of executing an event generation instruction for generating an event triggering processing of another slice when a processing of the slice is progressed to a predetermined position; and a step of executing an event standby instruction for waiting for an event to be generated by the event generation instruction and triggering processing of the slice in response to the event, allows efficient and smooth decoding in a simple configuration, even if the number of slices is not an integer multiple of the number of processing units such as CPUs, by appropriately providing a switching interval for the switch between the processing units, without heavily depending on the functions of an OS. 
         [0016]    According to the present invention, the event generation instruction may generate the event on the basis of a first function, for example, the SetEvent Function provided by an OS, and the event standby instruction may wait the event on the basis of a second function, for example, the WaitEvent Function, provided by the OS. 
         [0017]    In the aforementioned method, the first function provided by an OS can generate an event, and the second function provided by the OS can cause a thread to wait for the event, thereby enabling implementation in a simple configuration. 
         [0018]    Further, according to the present invention, the event generation instruction and the event standby instruction may be realized by a thread storing a register and jumping to another thread, where the thread is a unit for processing the slice. 
         [0019]    In the aforementioned method, the event generation instruction and the event standby instruction can be realized by a thread, which is a unit for processing the slice, storing a register in an internal memory and jumping to another thread, thereby enabling the implementation of functions equal to the event generation instruction and the event standby instruction in a simple configuration 
         [0020]    Further, according to the present invention, the event generation instruction may be positioned at each point at which a processing quantity of each of the threads, which are the individual units for carrying out processing of the respective slices, is divided in accordance with the number of processing units. 
         [0021]    In the aforementioned method, the event generation instruction can be positioned at each point at which a processing quantity of each of the threads, which are the individual units for carrying out processing of the respective slices, is divided in accordance with the number of processing units, thereby allowing efficient and smooth decoding in a simple configuration, even in a case where the number of slices is not an integer multiple of the number of the processing units, without heavily depending on the functions of an OS. 
         [0022]    Further, according to the present invention, the event generation instruction may be positioned at each point at which a processing quantity of each of the threads, which are the individual units for carrying out processing of the respective slices, is equally divided in accordance with the number of processing units. 
         [0023]    In the aforementioned method, the event generation instruction can be positioned at each point at which a processing quantity of each of the threads, which are the individual units for carrying out processing of the respective slices, is equally divided in accordance with the number of processing units, thereby allowing efficient and smooth decoding in a simple configuration, even in a case where the number of slices is not an integer multiple of the number of processing units, without heavily depending on the functions of an OS. 
         [0024]    Further, according to the present invention, a value obtained by multiplying the number of threads by the number of portions of each thread divided in accordance with the processing quantity may be a multiple of the number of processing units, and the slice switching is executed in units of the portions. Further, according to the present invention, a value obtained by multiplying the number of threads by the number of portions of each thread divided in accordance with the processing quantity can be a multiple of the number of processing units, and the slice switching can be executed in units of the portions, thereby allowing efficient and smooth decoding in a simple configuration, even if the number of slices is not an integer multiple of the number of processing units, without heavily depending on the functions of an OS. 
         [0025]    Further, according to the present invention, processing carried out in the processing step may be decoding of the moving image including the plurality of slices. In the aforementioned method, processing carried out in the processing step can be decoding of the moving image including the plurality of slices, thereby allowing efficient and smooth decoding in a simple configuration, without heavily depending on the functions of an OS. 
         [0026]    According to the present invention, the moving image including the plurality of slices may be encoded according to the AVC intra standard. Further, the plurality of processing units may include not only general-purpose CPUs, but also, for example, DSPs (Digital Signal Processors) specific for sound or image processing. 
         [0027]    In accordance with a second aspect of the present invention, there is provided a program executable by a computer for processing a moving image using a plurality of processing units, comprising: a step of dividing a frame of the moving image into a plurality of slices, where a number of the plurality of slices is not a multiple of a number of the plurality of processing units; a processing step, assigned to each of the plurality of slices, for processing each of the plurality of slices; and a switching step for executing slice switching, which switches between the slices to be processed, in the processing step. 
         [0028]    The aforementioned program, executable by a computer to carry out: a step of dividing a frame of the moving image into a plurality of slices, where a number of the plurality of slices is not a multiple of a number of the plurality of processing units; a processing step, assigned to each of the plurality of slices, for processing each of the plurality of slices; and a switching step for executing slice switching, which switches between the slices to be processed, in the processing step, allows efficient and smooth decoding in a simple configuration, even if the number of slices is not an integer multiple of the number of processing units such as CPUs, by appropriately providing a switching interval for the switch between the processing units, without heavily depending on the functions of an OS. 
         [0029]    In accordance with a third aspect of the present invention, there is provided an apparatus for processing a moving image using a plurality of processing units, comprising: a dividing unit for dividing a frame of the moving image into a plurality of slices, wherein a number of the plurality of slices is not a multiple of a number of the plurality of processing units; a processing unit, assigned to each of the plurality of slices, for processing each of the plurality of slices; and a switching unit for executing slice switching, which switches between the slices to be processed. 
         [0030]    The aforementioned apparatus comprising: a dividing unit for dividing a frame of the moving image into a plurality of slices, wherein a number of the plurality of slices is not a multiple of a number of the plurality of processing units; a processing unit, assigned to each of the plurality of slices, for processing each of the plurality of slices; and a switching unit for executing slice switching, which switches between the slices to be processed, allows efficient and smooth decoding in a simple configuration, even if the number of slices is not an integer multiple of the number of processing units such as CPU, by appropriately providing switching interval for the switch between the processing units, without heavily depending on the functions of an OS. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIG. 1  is a functional structural view of a video processing apparatus that implements a method according to the present invention; 
           [0032]      FIG. 2  is a diagram for explaining the structure of slices constituting a frame; 
           [0033]      FIG. 3  is a flowchart schematically describing the method according to the present invention; 
           [0034]      FIG. 4  is a hardware structure diagram of an embodiment of the moving image processing apparatus according to the present invention; 
           [0035]      FIG. 5  is a diagram describing threads which are executed by the moving image processing apparatus shown in  FIG. 4 ; 
           [0036]      FIG. 6  is a timing chart for describing switching processing that is executed by the moving image processing apparatus shown in  FIG. 4 ; 
           [0037]      FIG. 7  is a table showing correspondences between CPUs and respective threads; 
           [0038]      FIG. 8  is a diagram showing a program executed by the moving image processing apparatus shown in  FIG. 4 ; 
           [0039]      FIG. 9  is a diagram showing a program, following that shown in  FIG. 8 , executed by the moving image processing apparatus shown in  FIG. 4 ; 
           [0040]      FIG. 10  is a flow chart describing the operation executed by the moving image processing apparatus shown in  FIG. 4 ; 
           [0041]      FIG. 11  is a functional structural view of the video processing apparatus shown in  FIG. 4 ; 
           [0042]      FIG. 12  is a functional structural view of a video processing apparatus, similar to that shown in  FIG. 12 , in which the processing units is constructed with cores; and 
           [0043]      FIG. 13  is a functional structural view of the video processing apparatus, similar to that shown in  FIG. 12 , in which the processing units are combined with a DPS. 
       
    
    
     EXPLANATION OF REFERENCE 
       [0044]      1  to  4  Processing Unit 
         [0045]      5  Slice Dividing section 
         [0046]      6  Switching Section 
         [0047]      200  Busline 
         [0048]      300  Control Section 
         [0049]      301  to  304  CPU 
         [0050]      320  Communication I/F (Interface) 
         [0051]      330  Main Memory 
         [0052]      340  BIOS 
         [0053]      350  Display Device 
         [0054]      360  I/O Controller 
         [0055]      370  Input/Output Apparatus 
         [0056]      420  Memory Device 
       DETAILED DESCRIPTION 
       [0057]    First, the present invention will be schematically described with reference to  FIG. 1  to  FIG. 3 .  FIG. 1  is a functional structural view of a moving image processing apparatus that implements the method according to the present invention.  FIG. 2  is a diagram for explaining structure of slices.  FIG. 3  is a flowchart schematically describing the method according to the present invention. 
         [0058]    As shown in  FIG. 1 , a moving image processing apparatus that implements a moving image processing method according to the present invention comprises a plurality of processing units  1  to  4 , which process and decode moving image data, hereinafter referred to as “video data”, constituting a moving image, a slice dividing section  5 , which sequentially divides the video data into a plurality of slices when the video data is inputted, and a switching section  6 , which switches the plurality of slices divided up by the slice dividing section  5  between the plurality of processing units  1  to  4 . The plurality of processing units  1  to  4  process and decode the slices that are switched by the switching section  6 . Each of the plurality of processing units  1  to  4  is provided with a decoder. 
         [0059]    As shown in  FIG. 2 , a frame of the moving image is divided into a plurality of slices and processed. In an MPEG standard or the like, a slice is a minimum unit in a sequence of data with a start code, and is a strip of macroblocks with arbitrary lengths, but cannot straddle between pictures. Ordinarily, a macroblock is constituted by a luminance block and a color difference block for a square pixel block of 16 pixels by 16 lines. 
         [0060]    When the switching section  6  switches the plurality of slices which have been divided by the slice dividing section  5  to each of the plurality of processing units  1  to  4 , tasks, referred to as threads, are created for the decoding processing of the respective slices. According to the present invention, the slice dividing section  5  may divide, into a plural number of slices, the number not being a multiple of the plural number of processing units. As will be described in more detail later, the switching section  6  segments the plurality of slices which have been divided up by the slice dividing section  5 , and switches the slices between the plurality of processing units  1  to  4  in accordance with the states of progress in processing of the respectively corresponding threads. 
         [0061]    As shown in  FIG. 3 , the moving image processing method according to the present invention includes the following steps: a step of dividing a frame of video data constituting a moving image into a plurality of slices (step S 101 ); a step of applying decoding processing to the divided plurality of slices at respectively corresponding processing units (step S 102 ); a step of determining whether a processing quantity that has been processed by a respective processing unit has equaled a threshold value (step S 103 ); a step of, when it is determined that a processing quantity has equaled the threshold value, executing slice-switching for switching a slice to be processed (step S 104 ); and a step of determining whether decoding of the whole of the video data has been completed (step S 105 ). In step S 105 , if it is determined that decoding of the whole image data has not been completed, the processing returns to step S 102 , and when it is determined that the decoding has been completed, the moving image processing ends. In  FIG. 3 , for simplicity of description, a single flow of the steps S 102  to S 104  is described. However, the number of steps S 102  to S 104  will be the same as the number of processing units processing the video. For example, in a case in which there are four processing units as shown in  FIG. 1 , parallel processing is executed by flows of the same number as the processing units performing processing, steps S 102   1  to S 104   1 , steps S 102   2  to S 104   2 , steps S 102   3  to S 104   3  and steps S 102   4  to S 104   4 . 
         [0062]    According to the present invention, the threshold value for comparison in step S 103  is decided on the basis of a quantity found by dividing a processing quantity of the slices that are to be processed by the number of processing units. A slice that is being processed is suitably switched in step S 104  when a processed quantity thereof has reached the threshold value. Accordingly, the number of the plurality of slices divided up in step S 101  need not be an integer multiple of the number of processing units. 
         [0063]    The best mode for carrying out the present invention will be described herebelow with reference to the drawings. 
       Embodiment 
       [0064]    A preferred embodiment of a moving image processing apparatus according to the present invention will be described with reference to  FIG. 4  to  FIG. 7 . 
       Hardware Structure of Moving Image Processing Apparatus 
       [0065]      FIG. 4  is a hardware structure diagram of the present embodiment of the moving image processing apparatus according to the present invention. 
         [0066]    As shown in  FIG. 4 , the present embodiment of a moving image processing apparatus  1  comprises a control section  300 , which is structured with a group of a plurality of CPUs (central processing units), a busline  200 , a communication I/F (interface)  320 , a main memory  330 , a BIOS (Basic Input/Output System)  340 , a display device  350 , an I/O controller  360 , an input/output apparatus  370  such as a keyboard and a mouse or the like, a hard disk  380 , an optical disk drive  390 , and a semiconductor memory  410 . The hard disk  380 , the optical disk drive  390 , and the semiconductor memory  410  are collectively referred to as a memory device  420 . 
         [0067]    The control section  300  is a section that performs overall control of the moving image processing apparatus  1  and, by reading and executing various programs stored on the hard disk  380  as appropriate, cooperates with the hardware described above to realize various functions relating to the present invention. In the present embodiment, the control section  300  is structured with four CPUs  301  to  304 . 
         [0068]    The communication I/F  320  is a network adapter for when the moving image processing apparatus  1  is exchanging video data, control information or the like with a remote user terminal or the like through a communications network N (not shown). The communication I/F  320  may include a modem, a cable modem and an Ethernet (registered trademark) adapter. 
         [0069]    The BIOS  340  records a boot program that is executed by the control section  300  at a time of startup of the moving image processing apparatus  1 , a program dependent on the hardware of the moving image processing apparatus  1 , and the like. 
         [0070]    The display device  350  includes a cathode ray tube display device (CRT), a liquid crystal display device (LCD) or the like. 
         [0071]    The I/O controller  360  may be connected to the memory device  420 , such as the hard disk  380 , the optical disk drive  390  and the semiconductor memory  410 , or the like. 
         [0072]    In response to control by an operator, the input/output apparatus  370  inputs information required for controlling the moving image processing apparatus  1  from an operator and outputs required information to the operator. 
         [0073]    The hard disk  380  stores various programs and data, including an OS (operating system) for causing the present hardware to function as the moving image processing apparatus  1  and a program which realizes the functions according to the present invention. The moving image processing apparatus  1  may employ a separately provided external hard disk (not shown) as an external memory device. 
         [0074]    For example, a DVD-ROM drive, a CD-ROM drive, a DVD-RAM drive or a CD-RAM drive may be employed as the optical disk drive  390 . In such a case, an optical disk  400  suitable for the respective drive is employed. A program or video data may be read from the optical disk  400  by the optical disk drive  390  and provided to the main memory  330  or the hard disk  380  via the I/O controller  360 . 
         [0075]    The term “computer” herein used is intended to include an information processing device provided with the memory device  420  and the control section  300  or suchlike. The moving image processing apparatus  1  is structured by an information processing device provided with the memory device  420 , the CPUs  301  to  304  and so forth, and this information processing device is to be included in the concept of a computer according to the present invention. In the present embodiment, the CPUs  301  to  304  constitute the processing units  1  to  4  described in  FIG. 1 . The slice dividing section  5  and the switching section  6  are realized by the control section  300  executing a program stored on the hard disk  380 . 
         [0076]    For the moving image processing, the CPUs  301  to  304  operate in accordance with respective standards, so detailed descriptions of the moving image processing will not be given. For example, a moving image coded in accordance with the AVC Intra standard may be used. Information which has been decoded by the control section  300  may be displayed by the display device  350 , or may be sent to another terminal or the like by the communication I/F  320 , or may be stored on the hard disk  380 . 
         [0077]    Principles of Thread-Switching Processing 
         [0078]    The processing for switching slices that was described with reference to step S 104  of  FIG. 3  is processing for switching threads.  FIG. 5  to  FIG. 7  are diagrams for explaining the principles of the thread-switching processing that is executed by the present embodiment of the moving image processing apparatus  1 . 
         [0079]    Threads in the present embodiment will be described with reference to  FIG. 5 .  FIG. 5  is a diagram describing threads which are executed by the present embodiment of the moving image processing apparatus  1 . 
         [0080]    The threads that are provided for processing five slices are referred to, respectively, as threads T 0 , T 1 , T 2 , T 3  and T 4 . The respective points at which the threads are divided are shown by t 0 , t 1 , t 2 , t 3  and t 4 , and the portions of the threads which are demarcated by these points are referred to as A, B, C and D. 
         [0081]    According to the present invention, when processing of the threads is divided up, if the number of divided portions is Nd, the number of threads is Nt, and the number of processing units is Nc, then the number of divided portions is decided so as to satisfy the following equation. 
         [0000]      Nt*Nd=Nc*i (i is a positive integer) 
         [0082]    To be specific, a value found by multiplying the number of portions Nd into which a thread is divided by the number of threads Nt is preferably a multiple of the number of processing units Nc. 
         [0083]    For example, if the number of processing units performing processing of 5 threads is 4, then the number of portions Nd into which a thread is divided will be calculated such that Nd*5 is a multiple of 4. In the present embodiment, for simplicity of understanding, a description is given with the number of portions into which a thread is divided being four, but the present invention is not limited thus. The number of divided portions Nd may be any number as long as the value found by multiplying the number into which a thread is divided Nd by the number of threads Nt is a multiple of the number of processing units Nc, and various cases are possible such as, for example, 4, 8, 12 or 16. 
         [0084]    In the present embodiment, the CPU  301 , the CPU  302 , the CPU  303  and the CPU  304  are initially assigned to the threads T 0 , T 1 , T 2  and T 3 , and no CPU is assigned to thread T 4 . Accordingly, at t 0 , the CPUs  301  to  304  commence processing of the respective threads T 0 , T 1 , T 2  and T 3 , and processing of the A portion of each of the threads T 0 , T 1 , T 2  and T 3  is executed. Meanwhile, for thread T 4 , a wait flag w 3  is set, which is a flag that issues an event standby instruction to thread T 4 , to wait for event  3  and then recommence processing. Processing of thread T 4  is not carried out from t 0 . 
         [0085]    At t 1 , processing of the threads T 0 , T 1  and T 2  continues, and processing of the B portion of each of the threads T 0 , T 1  and T 2  is executed. For thread T 3 , however, a setting flag s 3  is set, which issues an event generation instruction to generate event  3 , and a wait flag w 2  is set, which issues an event standby instruction to wait for event  2  and then recommence processing. Thus, processing of thread T 3  is suspended. 
         [0086]    At t 2 , processing of the threads T 0  and T 1  continues, and processing of the C portion of each of the threads T 0  and T 1  is executed. For thread T 2,  however, a setting flag s 2  is set, which issues an event generation instruction to generate event  2 , and a wait flag w 1  is set, which issues an event standby instruction to wait for event  1  and then recommence processing. Thus, processing of thread T 2  is suspended. 
         [0087]    At t 3 , processing of the threads T 0  continues, and processing of the D portion of the thread T 0  is executed. For thread T 1 , however, a setting flag s i  is set, which issues an event generation instruction to generate event  1 , and a wait flag w 0  is set, which issues an event standby instruction to wait for event  0  and then recommence processing. Thus, processing of thread T 1  is suspended. 
         [0088]    At t 4 , a setting flag s 0  is set, which issues an event generation instruction to thread T 0  to generate event  0 . Processing of thread T 0  is suspended. 
         [0089]    In the present embodiment, the event generation instruction may cause the thread to generate an event on the basis of a first function provided by the OS, and an event standby instruction may cause the thread to wait for an event on the basis of a second function provided by the OS. Alternatively, the event generation instruction and event standby instruction may be realized by a thread, which is an individual unit for carrying out processing of a slice, storing a register in an internal memory and jumping to another thread. 
         [0090]    The thread-switching processing of the present embodiment will be described more in detail with reference to  FIG. 6  and  FIG. 7 .  FIG. 6  is a timing chart for describing switching processing, that is, the thread-switching processing that is executed by the present embodiment of the moving image processing apparatus  1 .  FIG. 7  is a table showing correspondences between the CPUs  301  to  304  and the thread portions that are processed. As shown in  FIG. 2 , image data is divided into  5  slices, and the slices are referred to, respectively, as slices  1 ,  2 ,  3 ,  4  and  5 . 
         [0091]    In the present embodiment, for ease of explanation, a single slice is processed as, for example, a strip of 200 macroblocks. The processing quantity that is the threshold value used when the CPUs  301  to  304  switch threads is a value found by dividing the processing quantities of the slice that is to be processed by the number of CPUs that are to perform processing. Thus, the value found by dividing 200 macroblocks by the number of CPUs, which is 4, is 50 macroblocks. 
         [0092]    Firstly, at t 0 , as shown in  FIG. 6 , processing of the A portions of the threads T 0 , T 1 , T 2  and T 3  commences. Meanwhile, for thread T 3 , the wait flag w 3  is set, which is the flag that issues an event standby instruction to thread T 3  to wait for event  3  and then recommence processing. Thus, no CPU will be assigned to thread T 4  until event  3  has been generated (see  FIG. 5 ). Specifically, as shown in  FIG. 7 , the CPUs  301  to  304  commence processing of threads T 0 , T 1 , T 2  and T 3 , respectively, and process the A portion of each of the threads T 0 , T 1 , T 2  and T 3 , that is, process 50 macroblocks of the respective slices  1 ,  2 ,  3  and  4 . 
         [0093]    When t 1  has been reached, as shown in  FIG. 6 , processing of the B portions of threads T 0 , T 1  and T 2  continues and, at the same time, processing of thread T 4  commences. Specifically, as shown in  FIG. 7 , the CPUs  301  to  303  continue the processing of threads T 0 , T 1  and T 2 , respectively, and process the B portion of each of the threads T 0 , T 1  and T 2 , that is, process 50 macroblocks of the respective slices  1 ,  2  and  3 . For thread T 3 , the setting flag s 3  is set, which issues an event generation instruction to thread T 3  to generate event  3 , and the wait flag w 2  is set, which issues an event standby instruction to wait for event  2  and then recommence processing (see  FIG. 5 ). After event  3  has been generated, by the setting flag s 3  issuing the event generation instruction for generating event  3 , thread T 3  is set to a state in which no CPU will be assigned thereto until event  2  has been generated. Meanwhile, because the wait flag w 3 , which is the flag that issues an event standby instruction to thread T 4  to wait for event  3  and then recommence processing, is set (see  FIG. 5 ), processing of thread T 4  is recommenced in response to event  3  being generated by thread T 3 . At this time, as shown in  FIG. 7 , the CPU  304 , which was processing thread T 3  just before, takes up the processing and processes the A portion of thread T 4 , that is, processes 50 macroblocks of the corresponding slice  4 . 
         [0094]    When t 2  has been reached, as shown in  FIG. 6 , processing of the C portions of threads T 0  and T 1  and the B portion of thread T 4  continues, and, at the same time, processing of thread T 3  commences. Specifically, as shown in  FIG. 7 , the CPUs  301 ,  302 , and  304  continue the processing of threads T 0 , T 1  and T 4 , respectively, and process the C portion of each of the threads T 0  and T 1  and B portion of thread T 4 , that is, process 50 macroblocks of the respective slices  1 ,  2  and  5 . For thread T 2 , the setting flag s 2  is set, which issues an event generation instruction to thread T 2  to generate event  2 , and the wait flag w 1  is set, which issues an event standby instruction to wait for event  1  and then recommence processing (see  FIG. 5 ). After event  2  has been generated, by the setting flag s 2  issuing the event generation instruction for generating event  2 , thread T 2  is set to a state in which no CPU will be assigned thereto until event  1  has been generated. Meanwhile, because the wait flag w 2 , which is the flag that issues an event standby instruction to thread T 3  to wait for event  2  and then recommence processing, is set (see  FIG. 5 ), processing of thread T 3  is recommenced in response to event  2  being generated by thread T 2 . At this time, as shown in  FIG. 7 , the CPU  303 , which was processing thread T 2  just before, takes up the processing and processes the B portion of thread T 3 , that is, processes 50 macroblocks of the corresponding slice  4 . 
         [0095]    When t 3  has been reached, as shown in  FIG. 6 , processing of the D portion of thread T o and the C portions of threads T 3  and T 4  continues, and, at the same time, processing of thread T 2  commences. Specifically, as shown in  FIG. 7 , the CPUs  301 ,  302 , and  304  continue the processing of threads T 0 , T 3  and T 4 , respectively, and process the D portion of the thread T 0  and C portions of threads T 3  and T 4 , that is, process 50 macroblocks of the respective slices  1 ,  4  and  5 . For thread T 1 , the setting flag s 1  is set, which issues an event generation instruction to thread T 1  to generate event  1 , and the wait flag w 0  is set, which issues an event standby instruction to wait for event  0  and then recommence processing (see  FIG. 5 ). After event  1  has been generated, by the setting flag s 1  issuing the event generation instruction for generating event  1 , thread T 1  is set to a state in which no CPU will be assigned thereto until event  0  has been generated. Meanwhile, because the wait flag w 1 , which is the flag that issues an event standby instruction to thread T 2  to wait for event  1  and then recommence processing, is set (see  FIG. 5 ), processing of thread T 2  is recommenced in response to event  1  being generated by thread T 1 . At this time, as shown in  FIG. 7 , the CPU  302 , which was processing thread T 1  just before, takes up the processing and processes the C portion of thread T 2 , that is, processes 50 macroblocks of the corresponding slice  3 . 
         [0096]    When t 4  has been reached, as shown in  FIG. 6 , processing of thread T 1  recommences and, at the same time, processing of threads T 2 , T 3  and T 4  continues. Specifically, as shown in  FIG. 7 , the CPUs  302 ,  303  and  304  continue the processing of threads T 2 , T 3  and T 4 , respectively, and process the D portions of the threads T 2 , T 3  and T 4 , that is, process 50 macroblocks of the respective slices  3 ,  4  and  5 . The setting flag s 0  is set, which issues an event generation instruction to thread T 0  to generate event  0  (see  FIG. 5 ), and thread T 0  is set to a state in which no CPU is assigned thereto. Meanwhile, because the wait flag w 0 , which is the flag that issues an event standby instruction to thread T 1  to wait for event  0  and then recommence processing, is set (see  FIG. 5 ), processing of thread T 1  is recommenced in response to event  0  being generated by thread T 0 . At this time, as shown in  FIG. 7 , the CPU  301 , which was processing thread T 0  just before, takes up the processing and processes the D portion of thread T 1 , that is, processes 50 macroblocks of the corresponding slice  1 .  FIGS. 8 and 9  show a pseudocode program used for carrying out the above-described processing. 
         [0097]    As can be seen from the timing chart shown in  FIG. 6 , according to the present embodiment of the method, the intervals of switching can be appropriately assured, as being a period from t 0  to t 1  when the CPU  304  is switching from thread T 3  to thread T 4 , a period from t 1  to t 2  when the CPU  303  is switching from thread T 2  to thread T 3 , a period from t 2  to t 3  when the CPU  302  is switching from thread T 1  to thread T 2 , and a period from t 3  to t 4  when the CPU  301  is switching from thread T 0  to thread T 1 . 
         [0098]    The event generation instructions may be positioned at respective points of each of the frames at which a processing quantity of each of the threads, which are the individual units for carrying out processing of the respective slices, is divided in accordance with the number of processing units. Proportions into which the processing quantity of each of the threads is divided or suchlike may be decided with threshold values being set in accordance with either data that is to be processed or data quantities that have been processed. In such cases, it is preferable to give consideration to the capabilities of the processing units that are to perform the processing and to the characteristics of the data that is to be processed. The event generation instructions are preferably positioned at the respective points of each of the frames at which the processing quantity of each of the threads which are the individual units for carrying out processing of the slices are equally divided in accordance with the number of processing units. 
         [0099]    Operation of Moving Image Processing Apparatus 
         [0100]    Operations in decoding processing carried out by the present embodiment of the moving image processing apparatus  1  will be described with reference to  FIG. 10 . Control of the following processing is implemented by the control section  300  executing various programs, including the OS, which have been stored on the hard disk  380 . 
         [0101]    Firstly, when video data is inputted, the video data is sequentially cut up into five slices  1 ,  2 ,  3 ,  4  and  5 , and a thread T 0  for decoding slice  1 , a thread T 1  for decoding slice  2 , a thread T 2  for decoding slice  3 , a thread T 3  for decoding slice  4  and a thread T 4  for decoding slice  5  are created. 
         [0102]    At this time, for thread T 0 , the processing quantity of the whole thread, that is, the processing quantity of decoding 200 macroblocks, is assigned as a threshold value. When the threshold value is reached, the setting flag s 0  will be set, which will issue an event generation instruction to generate event  0 , and processing will be suspended. 
         [0103]    For thread T 1 , a processing quantity of three quarters of the whole thread, that is, a processing quantity of decoding 150 macroblocks, is assigned as a threshold value. When the threshold value is reached, the setting flag s 1  will be set, which will issue an event generation instruction to generate event  1 , the wait flag w 0  will be set, which will issue an event standby instruction to wait for event  0  and then recommence processing, and processing will be suspended. 
         [0104]    For thread T 2 , a processing quantity of one half of the whole thread, that is, a processing quantity of decoding 100 macroblocks, is assigned as a threshold value. When the threshold value is reached, the setting flag s 2  will be set, which will issue an event generation instruction to generate event  2 , the wait flag w 1  will be set, which will issue an event standby instruction to wait for event  1  and then recommence processing, and processing will be suspended. 
         [0105]    For thread T 3 , a processing quantity of one quarter of the whole thread, that is, a processing quantity of decoding 50 macroblocks, is assigned as a threshold value. When the threshold value is reached, the setting flag s 3  will be set, which will issue an event generation instruction to generate event  3 , the wait flag w 2  will be set, which will issue an event standby instruction to wait for event  2  and then recommence processing, and processing will be suspended. 
         [0106]    For thread T 4 , the wait flag w 3  is set, which will issue an event standby instruction to wait for event  3  and then recommence processing. 
         [0107]    In step S 1 , the CPU  301  is assigned to thread T 0  for decoding slice  1 , and decoding processing of slice  1  by the CPU  301  is commenced. When the decoding processing commences, control of thread T 0  proceeds to step S 21 , and it is determined whether the processing quantity has reached the threshold value, specifically, whether decoding processing of 200 macroblocks, corresponding to processing of the whole thread, has been completed. If it is determined that the processing quantity has reached the threshold value, control proceeds to step S 22 . On the other hand, if it is determined that the processing quantity has not reached the threshold value, control returns to step S 1  and the decoding processing continues. 
         [0108]    In step S 2 , the CPU  302  is assigned to thread T 1  for decoding slice  2 , and decoding processing of slice  2  by the CPU  302  is commenced. When the decoding processing commences, control of thread T 1  proceeds to step S 16 , and it is determined whether the processing quantity has reached the threshold value, specifically, whether decoding processing of 150 macroblocks, corresponding to processing of the three quarters of the whole thread, has been completed. If it is determined that the processing quantity has reached the threshold value, control proceeds to step S 17 . On the other hand, if it is determined that the processing quantity has not reached the threshold value, control returns to step S 2  and the decoding processing continues. 
         [0109]    In step S 3 , the CPU  303  is assigned to thread T 2  for decoding slice  3 , and decoding processing of slice  3  by the CPU  303  is commenced. When the decoding processing commences, control of thread T 2  proceeds to step S 11 , and it is determined whether the processing quantity has reached the threshold value, specifically, whether decoding processing of 100 macroblocks, corresponding to processing of one half of the whole thread, has been completed. If it is determined that the processing quantity has reached the threshold value, control proceeds to step S 12 . On the other hand, if it is determined that the processing quantity has not reached the threshold value, control returns to step S 3  and the decoding processing continues. 
         [0110]    In step S 4 , the CPU  304  is assigned to thread T 3  for decoding slice  4 , and decoding processing of slice  4  by the CPU  304  is commenced. When the decoding processing commences, control of thread T 3  proceeds to step S 6 , and it is determined whether the processing quantity has reached the threshold value, specifically, whether decoding processing of 50 macroblocks, corresponding to processing of one quarter of the whole thread, has been completed. If it is determined that the processing quantity has reached the threshold value, control proceeds to step S 7 . On the other hand, if it is determined that the processing quantity has not reached the threshold value, control returns to step S 4  and the decoding processing continues. 
         [0111]    In step S 5 , event standby instruction is carried out by thread T 4  for decoding slice  5 . Specifically, the wait flag w 3  is set, which is a flag that issues an event standby instruction to thread T 4 , to wait for event  3  and then recommence processing. 
         [0112]    In step S 6 , when it is determined that the processing quantity of thread T 3  has reached the threshold value, specifically, that processing of one quarter of the whole thread has been completed, meaning that decoding processing of 50 macroblocks has been completed, then control proceeds to step S 7 . 
         [0113]    In step S 7 , event  3  is generated. Specifically, event setting flag s 3 , which issues an event generation instruction for generating event  3 , is executed, event  3  is generated, and control proceeds to step S 8 . In step S 8 , the CPU  304  suspends the decoding processing. Control proceeds to step S 9 , and event standby processing is performed. Specifically, the wait flag w 2 , which issues an event standby instruction to wait for event  2  and then recommence processing, is set. 
         [0114]    For thread T 4 , processing commences in response to the wait flag w 3  at event  3  which is generated in step S 7 . Specifically, control proceeds to step S 10  and the CPU  304 , which has suspended decoding processing of thread T 3 , commences decoding processing of thread T 4 . Thereafter, processing of thread T 4  ends when the decoding processing of thread T 4  has all been completed. 
         [0115]    For thread T 2 , when it is determined in step S 11  that the processing quantity of thread T 2  has reached the threshold value, specifically, that processing of one half of the whole thread has been completed, meaning that decoding processing of 100 macroblocks has been completed, then control proceeds to step S 12 . 
         [0116]    In step S 12 , event  2  is generated. Specifically, event setting flag s 2  is executed and event  2  is generated, and control proceeds to step S 13 . In step S 13 , the CPU  303  suspends decoding processing. In step S 14 , event standby processing is performed. Specifically, the wait flag w 1 , for waiting for event  1  and then recommencing processing, is set. 
         [0117]    For thread T 3 , processing is recommenced in response to the wait flag w 2  at event  2  which is generated in step S 12 . Specifically, control proceeds to step S 15  and the CPU  303 , which has suspended decoding processing of thread T 2 , recommences decoding processing. Thereafter, processing of thread T 3  ends when the decoding processing of thread T 3  has all been completed. 
         [0118]    For thread T 1 , when it is determined in step S 16  that the processing quantity of thread T 1  has reached the threshold value, specifically, that processing of the three quarters of the whole thread has been completed, meaning that decoding processing of 150 macroblocks has been completed, then control proceeds to step S 17 . 
         [0119]    In step S 17 , event  1  is generated. Specifically, event setting flag s 1  is executed and event  1  is generated, and control proceeds to step S 18 . In step S 18 , the CPU  302  suspends decoding processing. In step S 19 , event standby processing is performed. Specifically, the wait flag w 0 , for waiting for event  0  and then recommencing processing, is set. 
         [0120]    For thread T 2 , processing is recommenced in response to the wait flag w 1  at event  1  which is generated in step S 17 . Specifically, control proceeds to step S 20  and the CPU  302 , which has suspended decoding processing of thread T 1 , recommences decoding processing. Thereafter, processing of thread T 2  ends when the decoding processing of thread T 2  has all been completed. 
         [0121]    For thread T 0 , when it is determined in step S 21  that the processing quantity of thread T 0  has reached the threshold value, specifically, that processing of the whole thread has been completed, meaning that decoding processing of 200 macroblocks has been completed, then control proceeds to step S 22 . 
         [0122]    In step S 22 , event  0  is generated. Specifically, the event setting flag s 0  is executed and event  0  is generated, and the decoding processing of thread T 0  ends. 
         [0123]    For thread T 1 , processing is recommenced in response to the wait flag w 0  at event  0  which is generated in step S 22 . Specifically, control proceeds to step S 23  and the CPU  301 , which has suspended decoding processing of thread T 0 , recommences decoding processing. Thereafter, processing of thread T 1  ends when the decoding processing of thread T 1  has all been completed. 
         [0124]    Thus, according to the present embodiment, the following steps can be implemented: 
         [0125]    a step of dividing into a plural number of slices, the number not being a multiple of the plural number of processing units; a processing step of performing assignments for each of the plurality of slices and processing each of the plurality of slices; and a switching step of, in the processing step, executing slice-switching for switching the slices that are being processed. 
         [0126]    Here, the switching step includes an event generation instruction which, when processing of a slice has progressed as far as a predetermined point, generates an event for causing processing of another slice to be performed. Thus, the slices can be suitably switched without great dependence on the functions of the OS. Accordingly, even if the number of slices is a number that is not an integer multiple of the number of processing units such as CPUs or the like, switching intervals of switching of the processing units can be suitably assured and decoding processing can be carried out efficiently and smoothly. 
         [0127]    A structure is also possible in which an event generation instruction may generate an event on the basis of a first function provided by the OS, and an event standby instruction may cause a thread to wait for an event on the basis of a second function provided by the OS. Furthermore, a simple structure may be realized in which an event generation instruction and an event standby instruction can be realized by a thread, which is an individual unit for carrying out processing of a slice, storing a register in an internal memory and jumping to another thread. 
         [0128]    As described earlier, the event generation instructions may be positioned at respective points of each of the frames at which a processing quantity of each of the threads, which are individual units for carrying out processing of slices, is divided in accordance with the number of processing units. As will be seen from the foregoing description it has been described in the above that each of the threads carries out processing of one slice for simplicity of understanding. In reality, each of threads, however, carries out processing of a plurality of slices. In order to enable each of threads to carry out processing of a plurality slices, the above operations may be repeated for, for example, the number of times equal to that of slices. 
         [0129]    The proportions into which the processing quantity of each of the threads is divided or suchlike may be decided with threshold values being set in accordance with data that is to be processed or data quantities that have been processed. In such cases, consideration may be given to the capabilities of the processing units that are to perform the processing and to the characteristics of the data that is to be processed, and the processing quantity of each of the threads which are the individual units for carrying out processing of the slices may be equally divided up in accordance with the number of processing units and suchlike. Specifically, when a processing quantity of each of the threads is divided up, a value found by multiplying the number of divisions by the number of threads is set so as to be a multiple of the number of processing units. Thus, even if the number of slices is a number that is not an integer multiple of the number of processing units such as CPUs or the like, processing can be carried out efficiently and smoothly with a simple structure and without great dependence on the functions of the OS. 
         [0130]    In the present embodiment, a processing quantity, which is a threshold value used for when one of the CPUs  301  to  304  is to switch threads, has been set to 50 macroblocks, which is the value found by dividing the 200 macroblocks that constitute a single slice by the number of processing CPUs, which is 4. However, the present invention is not limited thus. For example, a value may be set for which a data quantity of data to be processed, i.e., data that has not yet been decoded by processing by the CPUs  301  to  304  is divided by the number of processing CPUs. 
         [0131]    Generally, a moving image is compressed such that large weighting factors are applied to low frequency components included in the image data and high frequency components go to zero. Consequently, the amounts of image data constituting individual macroblocks are not uniform. Therefore, rather than a value found by dividing a data quantity of compressed data that is yet to be decoded by the number of processing units performing processing, setting a threshold value to a value found by dividing a number of macroblocks that have been obtained by decoding by the number of processing units performing processing enables decoding of a video at higher quality. Furthermore, it is acceptable for a threshold value to be a value found by dividing a quantity to be processed by the number of processing units performing processing, and the divisions need not necessarily be equally divided. For example, one portion of a particular thread may be larger than another portion of the thread, depending on capabilities of the processing units performing processing and on the data to be decoded. 
         [0132]    A threshold value need not be specified as a data quantity or a number of decoded macroblocks, and may be specified as a processing duration required for decoding a target number of macroblocks. 
         [0133]    In the present embodiment, as shown in  FIG. 4  and  FIG. 11 , the plurality of processing units are structured as a plurality of CPUs  1 A to  4 A, but the present invention is not limited thus. As shown in  FIG. 12 , a plurality of processing units may be structured as, for example, a plurality of cores  1 B to  4 B that constitute a CPU, or as shown in  FIG. 13 , may be, for example, a combination of a plurality of CPUs  1 C to  3 C and a DSP  4 C. 
         [0134]    An embodiment according to the present invention has been described hereabove, but the present invention is not to be limited to the above-described embodiment. Moreover, the effects described for the embodiment according to the present invention are merely a recitation of the most excellent effects produced by the present invention, and effects resulting from the present invention are not be limited to those described for the embodiment according to the present invention. 
         [0135]    For example, application of the present invention is not limited to processing for decoding moving images. The present invention is employable for various applications that require stable processing at high speeds, such as arithmetic calculations, DV (digital video) coding, various simulations, and so forth.