Abstract:
A signal generator having a switching function includes a first oscillation circuit, a second oscillation circuit, a frequency-division circuit and a combination circuit. The first oscillation circuit outputs a first frequency signal having a first frequency and a reset signal synchronized with the first frequency signal. The second oscillation circuit outputs a second frequency signal having a second frequency which is N times higher than the first frequency. The frequency-division circuit frequency-divides the second frequency signal by N, resets a value for frequency-division based on the reset signal and generates a divided second frequency signal. The combination circuit combines the first frequency signal and the divided second frequency signal and outputs a combined signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a signal generator having a switching function for disconnecting an oscillator of a working system, when a failure occurs therein, and connecting an oscillator of a backup system. 
     2. Description of the Related Art 
     With recent advances in sophisticated information transmission, for example transmission of banking data, apparatus to be used for communication lines are required to have very high reliability. 
     Therefore, a method of improving reliability by providing a fully redundant structure and then switching into operation, as required, the redundant circuits has been provided for oscillators such as a local oscillator of a frequency converter in a radio communication device. However, if the switching time of the oscillator becomes longer, the oscillation signal disappears during the switching period and the frequency of a phase-locked loop circuit provided in the successive stage changes. Therefore, switching must be done within a very short period of time. 
     In a prior signal generator having a switching function, a watch-dog timer is provided as a failure detecting means of an oscillator and a switching instruction is issued to a switch upon judgement of a failure because no oscillation signal is input within a predetermined constant period. 
     An example of such a structure is shown in FIG. 1 and a timing chart indicating operations of each point A to F in FIG. 1 is shown in FIGS. 2A to 2F. In FIG. 1, the numerals 11 and 12 respectively denote crystal oscillators of the working system and backup system. A switch 14 selects any one output signal of these oscillators and inputs such output signal to a phase-locked loop (PLL) circuit 15. The PLL circuit 15 is provided for absorbing signal discontinuity during a switching operation by the switch 14. The numeral 13 denotes a control circuit such as a watch-dog timer for instructing switch 14 to perform the switching operation by detecting an OFF state of the oscillation signal A. The control circuit 13 is usually formed by a retriggerable one-shot multivibrator. Moreover, as the watching time for the detection of the OFF state, an R-C time constant is generally used. 
     However, in the prior art, a problem exists in that the switching operation is delayed for a period corresponding to the watching time. The watching time is required to have a duration based on the stability of the oscillation frequency and an error of the time constant (usually, 5 to 20% in the R-C circuit). Moreover the watching time is usually set to a period of 10 cycles or more in order to prevent switching from occurring frequently during the transitional period from the normal operating condition until perfect stoppage of oscillation. If switching from the oscillator 12 to the oscillator 11 is generated before the PLL circuit 15 is completely locked to a phase of the oscillator 12 after switching from the oscillator 11 to the oscillator 12, a phase error in the PLL circuit 15 is increased and the PLL circuit 15 may become out-of-synchronization. 
     Therefore, as shown in FIG. 2C, at least the time which is equal to several cycles of the oscillation signal may be necessary for the control circuit 13 to judge an OFF state of the oscillation signal A as a failure from the timing where the oscillation signal in the working system actually enters the OFF state (point X in FIG. 2A). Thereafter, the switch 14 switches the oscillator of the working system to that of the backup system as shown in FIG. 2D. 
     During the period T, which is from the timing of entering the OFF state to the timing of switching, an output frequency of PLL 15 changes by a large amount (Δf) as indicated in FIG. 2F because the switch 14 does not select the backup system even when the oscillation signal A is in the OFF state and the oscillation signal is not input to PLL 15 as shown in FIG. 2E. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a signal generator having a switching function which realizes immediate switching of the working system to the backup system in response to the OFF state of the oscillation signal. 
     Another object of the present invention is to decrease fluctuation of the output frequency when switching occurs. 
     Additional objects and advantages of the invention will be set forth in part in the description which follows, and, in part, will be clear from the description, or may be learned by practice of the invention. 
     To achieve the foregoing objects and in accordance with the purpose of the invention, as embodied and broadly described herein, a signal generator having a switching function comprises first oscillation means, second oscillation means, frequency-division means and combination means. The first oscillation means outputs a first frequency signal having a first frequency and a reset signal synchronized with the first frequency signal. The second oscillation means outputs a second frequency signal having a second frequency which is N times the first frequency. The frequency-division means frequency-divides the second frequency signal by N, resets a value for frequency-division based on the reset signal and generates a divided second frequency signal. The combination means combines the first frequency signal and the divided second frequency signal and outputs a combined signal. 
     In the present invention, the frequency-division means is reset by the reset signal synchronized with the first frequency signal. Therefore, stoppage of the first frequency signal causes immediate outputting of the divided second frequency signal. And the divided second frequency signal has almost the same phase as the first frequency signal because the frequency-division means has been reset in synchronization with the first frequency signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a prior art signal generator; 
     FIGS. 2A-2F are time charts for the operation of the signal generator of FIG. 1; 
     FIG. 3 is a block diagram of an embodiment of a signal generator in accordance with the present invention; 
     FIGS. 4A-4G, 5A-5G and 6A-6G are time charts for the operation of the signal generator of FIG. 3; 
     FIG. 7 is a block diagram of an alternate embodiment of the delay circuit 23 of FIG. 3; 
     FIGS. 8A-8D are time charts for the operation of the delay circuit of FIG. 7; 
     FIG. 9 is a block diagram of another alternate embodiment of the delay circuit 23 of FIG. 3; 
     FIGS. 10A-10H are time charts for the operation of the delay circuit of FIG. 9; 
     FIG. 11 is a block diagram of the frequency-divider 22 of FIG. 3; 
     FIGS. 12A-12C are time charts for the operation of the frequency divider of FIG. 11; 
     FIG. 13 is a block diagram of an alternate embodiment of a part corresponding to the frequency-divider 22 and the delay circuit 23 in FIG. 3; 
     FIGS. 14A-14D are time charts for the operation of the circuit of FIG. 13; 
     FIG. 15 is a block diagram of a second embodiment of a signal generator in accordance with the present invention; 
     FIGS. 16A-16l are time charts for the operation of the signal generator of FIG. 15; 
     FIG. 17 is a circuit diagram of the edge detector 51 of FIG. 15; 
     FIGS. 18A and 18B are time charts for the operation of the edge detector of FIG. 17; 
     FIG. 19 is a block diagram of an alternate embodiment of an edge detector; 
     FIGS. 20A and 20B are time charts for the operation of the edge detector of FIG. 19; 
     FIG. 21 is a block diagram of still another embodiment of an edge detector; 
     FIGS. 22A-22C are time charts for the operation of the edge detector of FIG. 21; 
     FIG. 23 is a block diagram of a third embodiment of a signal generator in accordance with the present invention; 
     FIGS. 24A-24H are time charts for the operation of the signal generator of FIG. 23; 
     FIG. 25 is a block diagram of a fourth embodiment of a signal generator in accordance with the present invention; and 
     FIGS. 26A-26I are time charts for the operation of the signal generator of FIG. 25. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 is a block diagram of an embodiment of the present invention. FIG. 4A to FIG. 4G are timing charts for explaining the operation of the circuit of FIG. 3. The waveforms of the signals at the points A to G in FIG. 3 are respectively shown as FIG. 4A to FIG. 4G. 
     The signal generator of FIG. 3 includes working and backup oscillators 21 and 24, which are formed, for example, using a crystal-controlled oscillator, and frequency-dividers 22 and 26. A delay circuit 23 is formed by cascade-connected inverters 231 and 232, and has a delay time which may be adjusted depending on the number of inverters. An OR gate 25 is connected to the input and output of the delay circuit 23, while an exclusive-OR gate 27 operates as a switch. 
     As shown in FIGS. 4A-4G, a frequency divider 26 does not output a frequency-divided signal while the crystal oscillator 21 of the working system operates normally. If the frequency of the crystal oscillator 21 of the working system is defined as f1 and the frequency of the crystal oscillator 24 of the backup system is defined as f2, when f1&gt;f2 the frequency-divider 26 (which is reset as the point X of FIG. 4F) tries to output the frequency-divided signal at the point U. However, since it is reset by an output signal of the OR gate 25, namely by an output signal of the delay circuit 23 (FIG. 4C) at the point Z preceding the point U, the frequency-divider 26 does not output the frequency-divided signal. 
     When f1&gt;f2, the frequency-divider 26 which is reset at the point X of FIG. 4F tries to output the frequency-divided signal at the point Y preceding the point Z. However, the frequency-divider 26 is reset with an output of the OR gate 25 at the point W. Namely, an input signal (FIG. 4B) of the delay circuit 23 is generated a time Td before the point Z and therefore the frequency-divider 26 cannot output the frequency-divided signal. 
     Accordingly, in FIG. 3, since an output of the frequency divider 26 is kept at the low level while the crystal oscillator 21 of the working system operates normally, an output of the crystal oscillator 21 is provided as the output of exclusive-OR gate 27 and is then supplied to PLL 28. 
     PLL 28 includes an edge-detection type phase comparator 281, a low pass filter 282, and a voltage-controlled oscillator (VCO) 283. The phase comparator 281 compares a front edge (rising point), namely a phase, of the output signal from the exclusive-OR gate 27 and a front edge of an output signal of the VCO 283. An output of the phase comparator 281 is input to the VCO 283 through filter 282. The VCO 283 outputs a local oscillation signal, the frequency of which is controlled by the output signal from the filter 282. 
     FIGS. 5A-5G and FIGS. 6A-6G are timing charts for explaining the operation of the signal generator when an output of the crystal oscillator 21 stops. FIGS. 5A-5G show waveforms for explaining the operation for the OFF state of the oscillation signal in the working system when an output (FIG. 5B) of the frequency divider 22 is at the low level. Since the frequency divider 26 has been reset continuously with an output (FIG. 5C) of the delay circuit 23 through OR gate 25 (FIG. 5D), its internal condition maintains the same relationship of phase as an output of the delay circuit 23. When the reset signal (FIG. 5D) disappears, the frequency divider 26 immediately outputs a frequency-divided signal (FIG. 5F) in substantially the same phase relationship and continuously provides a continuous reference signal to PLL 28 without allowing large fluctuation of an output (FIG. 5G) of the exclusive-OR gate 27. 
     FIGS. 6A-6G show waveforms for explaining the operation for the OFF state of the reference signal in the working system when an output (FIG. 6B) of the frequency-divider 22 is at the high level. In this case, an output signal of the frequency-divider 22 is inverted. Therefore, a small phase deviation is generated, but since a continuous reference signal is supplied to PLL 28 as in the case of FIG. 5G, the frequency of an output signal of PLL 28 has little change. 
     In the first embodiment of FIG. 3, the delay time Td of delay circuit 23 is determined by following formula: 
     
         Td&gt;N/f1 min-(N-1)/f2 max 
    
     wherein f1min is the minimum frequency of the frequency fluctuation range of the oscillation signal from the crystal oscillator 21, f2max is the maximum frequency of the frequency fluctuation range of the oscillation signal from the crystal oscillator 24 and N is the dividing rate of the frequency-divider 22 and 26. 
     When the dividing rate N is 8, the oscillation frequency of the crystal oscillators 21 and 24 is 8 MHz and the frequency fluctuation is 50 ppm, 
     
         Td&gt;8/(8,000,000 Hz -400 Hz)-7/(8,000,000 Hz+400 Hz)≈125.1 nsec. 
    
     The delay time of each inverter is 115 nsec when C-MOS 4000 series logic gates are used as inverters 231 and 232. Then Td is 230 nsec. 
     FIG. 7 shows another type of the delay circuit 23 and FIGS. 8A-8D show time charts of points A-D of FIG. 7. In FIG. 7, the delay circuit 23 includes flip-flops 233 and 234 which are connected in series. The oscillation signal from crystal oscillator 21 is used as a clock signal for the flip-flops 233 and 234. In this case, the delay time Td of the delay circuit 23 is equal to two periods of the oscillation signal from the oscillator 21. 
     FIG. 9 shows further another type of delay circuit 23 and FIGS. 10A-10H show time charts of points A-H of FIG. 9. In FIG. 9, the delay circuit 23 includes serial resistors 301, 304 and 307, parallel capacitors 302, 305 and 308, Schmitt trigger gates 303, 306 and 309, and an inverter 310. One serial resistor, one parallel capacitor and one Schmitt trigger gate construct a unit delay circuit. When each resistor R is 1 kΩ, each capacitor C is 54.3 pF, the power supply voltage E is 5 V, the threshold voltage V+ from low level to high level of each Schmitt trigger gate is 3.15 V and the threshold voltage V- from high level to low level of each Schmitt trigger gate is 0.9 V, the rising delay time T+and falling delay time T-of each unit delay circuit are given by the following formulas: 
     
         T+=-RC In(1-V+/E)=63.6 nsec, 
    
     
         T-=-RC ln(V-/E)=109.0 nsec. 
    
     Then, the total delay time Td of the delay circuit 23 in FIG. 7 is given by the following formula: 
     
         Td=T++T-+T+=236.2 nsec. 
    
     The frequency-divider 22 is constructed by a binary counter 221 and a decoder 222 as shown as FIG. 11. FIGS. 12A-12C show time charts of points A-C in FIG. 11. The binary counter 221 counts pulses in the oscillation signal (FIG. 12A) from the oscillator 21 and outputs cyclic numbers 0-7 as shown in FIG. 12B. The decoder 222 decodes number 7 of the output signal from the binary counter 221. Then, the oscillation signal is divided by 8. The frequency-divider 26 has the same structure as the frequency-divider 22. 
     The frequency-divider 22 is not necessary if an oscillator having an oscillation frequency equal to the freuqency of the output signal of frequency-divider 26 is used instead of the oscillator 21. 
     The frequency-divider 22 and the delay circuit 23 may be replaced by a circuit shown in FIG. 13, and FIGS. 14A-14D show time charts of points A-D in FIG. 13. The binary counter 223 counts pulses in the oscillation signal (FIG. 14A) from the oscillator 21 and outputs cyclic numbers 0-7 as shown in FIG. 14B. The decoders 224 and 225 respectively decode numbers 5 and 7 of the output signal from the binary counter 223. Then, the decoder 224 outputs an advanced divided signal and the decoder 225 outputs a delayed divided signal. 
     In the first embodiment, frequency-divider 26 is reset at the rising point of the reset signal. However, many frequency-dividers on the market are reset while the reset signal is at a high (or low) level. If such a frequency-divider is used as frequency-divider 26, the frequency-divider outputs a continuing low level signal as in the case of FIGS. 6A-6G. FIG. 15 shows a second embodiment, in which a frequency-divider which is reset while the reset signal is at a high level, can be used. FIGS. 16A-16I show time charts of points A-I in FIG. 15. The difference between FIG. 3 and FIG. 15 is that edge detectors 51 and 52 are inserted in front of each input of OR gate 25. Therefore, the reset signal (FIG. 16F) from OR gate 25 returns to a low level even if the output signal (FIG. 16B) of frequency-divider 22 continues at a high level. 
     FIG. 17 shows one type of edge detector, and time charts of points A and B are shown in FIGS. 18A and 18B. The edge detector has a serial capacitor 510, a parallel resistor 511 and a diode 512. The serial capacitor 510 and the parallel resistor 511 make differential pulses of an input signal. The diode 512 deletes negative pulses. 
     Another type of edge detector is shown in FIG. 19, and FIGS. 20A and 20B show time charts of points A and B in FIG. 19. The edge detector is a one-shot multivibrator 513 having an external resistor 514 and an external capacitor 515. A pulse width Tw of an output signal is determined by R-C constants of the resistor 514 and the capacitor 515. 
     FIG. 21 shows another type of edge detector and time charts of points A-C are shown in FIGS. 22A-22C. The edge detector of FIG. 21 has three serial inverters 516, 517 and 518 and an AND gate 519. The three serial inverters 516, 517 and 518 output delayed and inverted signals. The total delay time is triple the delay time of each inverter. The AND gate 519 outputs a pulse having a pulse width Tw equal to the total delay time. 
     In this case, the delay time Td of the delay circuit 23 is given by the following formula: 
     
         Td&gt;N/f1 min-(N-1)/f2 max-Tw. 
    
     If the pulse width Tw of the output signal of the edge detectors 51 and 52 is shorter than the delay time Td of the delay circuit 23, the reset signal from the OR gate 25 has two pulses per one pulse of the divided signal output from the frequency-divider 22. In this case, a frequency-divider which is reset at a rising point of the reset signal can be used as the frequency-divider 26. 
     FIG. 23 shows a third embodiment of the invention and time charts of points A-H are shown in FIGS. 24A-24H. The difference between FIG. 15 and FIG. 23 is that edge detector 53 is inserted at the output of the OR gate 25 instead of the inputs. Also in this embodiment, the reset signal returns to a low level even if the output signal (FIG. 24B) of frequency-divider 22 continues at a high level. 
     A fourth embodiment of the invention is shown in FIG. 25 and time charts of points A-I are shown in FIGS. 26A-26I. In this embodiment, edge detectors 54 and 55 are inserted at outputs of the frequency dividers 22 and 26. Therefore, the divided signals (FIGS. 26C, 26D and 26H) return to a low level and the reset signal (FIG. 26E) also returns to a low level even if the output signal (FIG. 26B) of frequency-divider 22 continues at a high level. Because the divided signals (FIGS. 26C, 26D and 26H) return to a low level, OR gate 29 can be used instead of the exclusive-OR gate 28. 
     When the pulse width Tw meets the following condition: 
     
         Tw&gt;N/f1 min-(N-1)/f2 max, 
    
     the delay circuit 23 and the OR gate 25 are not necessary in the embodiments of FIGS. 15, 23 and 25. Then, in the embodiments of FIGS. 15 and 23, the output signal of the frequency-divider 22 is input to the frequency-divider 26 through the edge detector (51 or 53) and is directly input to the exclusive-OR gate 27. In the embodiment of FIG. 25, the output signal of the edge detector 54 is directly input to the frequency-divider 26 and the OR gate 29. 
     In the embodiments above, the duty ratio of the output signal from the frequency-divider 26 is 1/N. However, if the duty ratio R is another value, for example 1/2, &#34;(N-1)&#34; in the above three formulas should be changed to &#34;N(1-R)&#34;. 
     The foregoing is considered as illustrative only of the preferred embodiments and principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be resorted to, as falling within the scope of the invention in the appended claims and their equivalents.