Abstract:
A data converter ( 20 ). The converter comprises an input (I 0 -I 3 ) for receiving a digital word. The converter further comprises a string ( 22 ) of series connected resistive elements. The string comprises an integer number T of voltage taps (T 0 ′-T 8 ′). The converter further comprises an output (V OUT2 ) for providing an integer number P of different analog voltage levels in response to the digital word. The integer number P is greater than the integer number T.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     Not Applicable. 
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     Not Applicable. 
     BACKGROUND OF THE INVENTION 
     The present embodiments relate to data converters, and are more particularly directed to converters using resistor strings. 
     Data converters may be used in various types of electronic circuits, or may be formed as a single integrated circuit device. Such converters typically take one of two forms, either as a digital-to-analog converter (“DAC”) or an analog-to-digital converter (“ADC”). For the DAC, its operation converts an input digital signal to an output analog signal, typically where the amplitude of the output analog signal corresponds directly to the magnitude of the input digital signal Conversely, the ADC converts an input analog signal to an output digital signal, typically where the value of the output digital signal corresponds directly to the amplitude of the input analog signal. In many configurations, both DACs and ADCs implement a resistor string that includes a number of series-connected resistors, where each resistor provides a voltage tap at each of its ends. Indeed, often an ADC includes a DAC within the overall ADC configuration. In any event, the overall resistor string typically is biased at opposing ends by two different reference voltages, for example where one such voltage may be a positive voltage and the other is ground. Accordingly, the resistor string forms a voltage dividing network and each of the voltage taps is accessible as part of the operation for the data conversion (i.e., either from digital to analog, or analog to digital). Given this functionality, the relevant art teaches that a common concern is to endeavor to ensure that the overall device is as small and as fast as possible. The present embodiments are directed to this concern and, in providing a solution to same, improve both DAC and ADC technology. 
     For further background to converters and by way of example, FIG. 1 illustrates a typical configuration of a prior art DAC  10 , and is detailed briefly below. In addition, since the primary focus of the preferred embodiments described later is directed to resistor strings as used in either a DAC or an ADC, the following discussion provides one example of such a string as used in a DAC, but is not unduly lengthened by also providing a detailed analysis of an ADC. Instead, such an understanding is left to one skilled in the art. 
     Turning to DAC  10  of FIG. 1, it includes a series-connected resistor string designated generally at  12 . By way of example and as appreciated later, DAC  10  is a 3 input 8 output DAC, while numerous other dimensions may exists for different DAC configurations. For the current example of a 3-to-8 DAC, resistor string  12  includes seven resistive elements shown as R 0  through R 6 . Resistive elements R 0  through R 6  may be formed using various techniques, where the particular technique is not critical to the present inventive teachings. The relevant art teaches, however, that regardless of the technique used to form the resistive elements, a common concern is to endeavor to ensure that each resistive element has as close to the same resistance value as all other resistors in the string. Moreover, a voltage source V S1  is applied across resistor string  12 , and may be of any suitable biasing voltage, which for current applications is typically on the order of two volts. Thus, given the equal resistance of each element in the string, the voltage division across the resistors is uniform. 
     Looking to the detailed connections with respect to the resistive elements in string  12 , each resistive element provides two taps from which a voltage may be measured as detailed below. For example, looking to the bottom of FIG. 1, resistive element R 1  provides a tap T 0  and a tap T 1 , while resistive element R 2  shares the same tap T 1  and provides another tap T 2 , and so forth. Each tap has a switching device connected between it and an output node, V OUT1 . In the current example, each of these switching devices is an n-channel field effect transistor, although in an alternative embodiment all of the switching devices may be p-channel transistors. In any event, each switching device is labeled for convenience by combining the abbreviation ST (i.e., switching transistor) with the same numeric identifier corresponding to the tap to which a first source/drain of the transistor is connected. For example, a first source/drain of transistor ST 0  is connected to tap T 0 , a first source/drain of transistor ST 1  is connected to tap T 1 , and so forth. The gate of each of transistors ST 0  through ST 7  is connected to receive a control signal from a decoder  14 . Decoder  14  is connected to receive a 3-bit digital input at corresponding inputs I 0  through I 2 , and to enable one of eight output conductors, C 0  through C 7 , in an output bus  16 , as further detailed below. 
     The operation of DAC  10  is as follows. A 3-bit digital word is connected to inputs I 0  through I 2  of decoder  14 , and it includes sufficient logic circuitry or the like to respond by enabling only one of the eight output conductors, C 0  through C 7 , in output bus  16 . In a simple case, therefore, the numeric identifiers of the conductors in bus  16  may be thought of as corresponding to the value of the digital word, that is, the corresponding numbered conductor is asserted in response to the magnitude of the 3-bit digital word. For example, if the 3-bit digital word equals 001, then conductor C 1  of bus  16  is enabled. Once a conductor in bus  16  is asserted, which in the current example occurs by asserting the conductor logically high, it enables the single switching transistor to which it is connected. By way of illustration of this operation, and continuing with the example of conductor C 1  of bus  16  being asserted, it therefore places a logic high signal at the gate of switching transistor ST 1 , which in response provides a conductive path between tap T 1  and output node V OUT1 . In addition, recall that the voltage source V S1 , is evenly divided across resistor string  12 ; consequently, by enabling transistor ST 1 , then the divided voltage at tap T 1  is coupled to output node V OUT1 . Accordingly, the digital input of 001 has been converted to an analog voltage which equals this divided voltage. Using common voltage division as provided by a series of resistors such as in string  12 , for the current example this voltage is that across resistive element R 0  and, therefore, equals 1/7* V S1 . 
     Given the above, one skilled in the art will further appreciate that with different digital inputs, any of the transistors of DAC  10  may be enabled, and for each such transistor it will correspondingly cause an output which represents a divided voltage between 0 volts or any value incrementing up from 0 volts by 1/7V S1 , and up to an output equal to V S1 . From this observation and for purposes of later contrast to the preferred embodiments, note that the number of possible different analog output voltages of DAC  10  (i.e., 8 different voltages) necessarily includes the same number of taps as are provided by that DAC, that is, the same number of connections provided by the series resistance string. 
     The configuration of DAC  10  has been accepted in various contexts, however it provides certain drawbacks. Particularly, due to the requirement of equal resistance for elements R 0  through R 7 , one approach has been to form them along a single continuous line as depicted schematically in FIG.  1 . However, for larger decoders, this may provide for too large a device and, thus, an alternative is to provide a back-and-forth resistance string, sometimes referred to as a meander, in an effort to reduce the span of the resistance string. With the meander, however, there arises complications in the efforts to maintain the resistance of each element at the same value, particularly given that those configurations may include corner elements which are different in shape than the non-cornering elements. In addition, it is often the goal of an integrated circuit to be made smaller, and this goal may well apply to a converter, either alone or in combination with other circuitry on the same single integrated circuit Still further, the integral non-linearity (“INL”) of a larger circuit may be greater due to variances of device characteristics on one side of the circuit versus those on another side of the circuit. Still further, it is desirable to reduce the overall size of the converter to reduce internal impedances, and because reduced size often equates to a faster device. In view of these drawbacks and goals, there arises a need to provide an improved converter configuration, as is achieved by the preferred embodiments discussed below. 
     BRIEF SUMMARY OF THE INVENTION 
     In the preferred embodiment, there is a data converter. The converter comprises an input for receiving a digital word. The converter further comprises a string of series connected resistive elements. The string comprises an integer number T of voltage taps. The converter further comprises an output for providing an integer number P of different analog voltage levels in response to the digital word. The integer number P is greater than the integer number T. Other circuits, systems, and methods are also disclosed and claimed. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     FIG. 1 illustrates a schematic of a prior art digital-to-analog converter (“DAC”); 
     FIG. 2 illustrates a schematic of a first inventive DAC operable to produce double the output capacity of the prior art DAC of FIG. 1 by interpolating voltages between tap voltages; 
     FIG. 3 illustrates a truth table for the preferred operation of the decoder of DAC  20  in FIG. 2; 
     FIG. 4 illustrates a schematic of a second inventive DAC operable to produce four times the output capacity of the prior art DAC of FIG. 1 by interpolating voltages between tap voltages; 
     FIG. 5 a  illustrates a truth table for the preferred operation of the decoder of DAC  30  in FIG. 4; 
     FIG. 5 b  illustrates a consolidated table of the truth table of FIG. 5 a,  where for FIG. 5 b  only the asserted output columns are shown and are classified according to one of four different situations which may arise from the switching elements connected between each tap and the output; 
     FIG. 6 a  illustrates an equivalent resistance network corresponding to situation  2  identified in the table of FIG. 5 b;    
     FIG. 6 b  illustrates an equivalent resistance network corresponding to situation  3  identified in the table of FIG. 5 b;    
     FIG. 6 c  illustrates an equivalent resistance network corresponding to situation  4  identified in the table of FIG. 5 b;  and 
     FIG. 7 illustrates a preferred layout of a set of three switching elements connected to a tap as shown schematically in FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 was described in the preceding Background of the Invention section of this document and in connection with the prior art. 
     FIG. 2 illustrates a schematic of a DAC  20  according to a first inventive embodiment DAC  20  includes many components which are comparable in formation and connection to components in DAC  10  of FIG.  1 . To illustrate these like components, they are shown with the same reference identifiers as in FIG. 1, with the exception that an apostrophe is added to the identifier. In addition, and for reasons evident later, DAC  20  includes an additional resistor, tap, and switching transistor as compared to DAC  10 . Briefly reviewing the elements of DAC  20 , and assuming the reader is familiar with DAC  10 , DAC  20  includes a series-connected resistor string  22  having eight resistive elements R 0 ′ through R 7 ′, across which is connected a voltage source V S2 , and where the resistive elements may be formed using various techniques known in the art. In addition, each resistive element R 0 ′ through R 7 ′ connects to a pair of taps, thereby forming a total of nine taps T 0 ′ through T 8 ′. Each of taps T 0 ′ through T 8 ′ has a corresponding switching transistor, ST 0 ′ through ST 8 ′, connected between the tap and an output node V OUT2 . The switching transistors are preferably n-channel field effect transistors, although other devices may be substituted for these transistors. Lastly, a bus  24  includes nine conductors, each of which is connected to a gate of a corresponding one of switching transistors ST 0 ′ through ST 8 ′. 
     A key distinction between DAC  20  in FIG.  2  and DAC  10  of the prior art arises from decoder circuit  26 . Specifically, decoder circuit  26  includes four inputs, designated I 0  through I 3 , with only one additional output conductor, C 8 , in its bus  24 . Thus, here an additional input is provided in contrast to DAC  10 , and from this input and the details of decoder  26  there is a corresponding doubling in the number of outputs available at output node V OUT2 . This increase in capacity is further explored below, first by examining decoder  26  into greater detail, and then following with an operational description of DAC  20  in its entirety. 
     FIG. 3 illustrates a truth table for the preferred signal operation of decoder circuit  26 . From this table as well as the following discussion, one skilled in the art may develop various circuit implementations, such as using Karnaugh maps or the like, to implement a logic or other circuit design for achieving the illustrated input/output relationships. Turning then to those relationships, FIG. 3 illustrates that the four inputs to decoder circuit  26  are permitted to provide any of sixteen different input combinations (i.e., 0000 through 1111), and in response decoder  26  produces a corresponding one of sixteen different output combinations. More particularly, FIG. 3 illustrates that for any one set of inputs, the output of decoder circuit  26  may be characterized as one of two types of situations: (1) an assertion of a single one of conductors C 0  through C 8 ; or (2) an assertion of a two consecutive ones of conductors C 0  through C 8 . As an example of situation (1), if the input is 0000, then the output asserts only conductor C 0 . As an example of situation (2), if the input is 0001, then the output asserts consecutive conductors C 0  and C 1 . The result of these two situations is further appreciated by returning to FIG. 2, as is done immediately below. 
     Returning to DAC  20  of FIG. 2, note that the signal output variations in the FIG. 3 truth table correspond to the output possibilities of DAC  20 . More specifically, DAC  20  may operate to output sixteen different output voltages in response to the corresponding sixteen different input combinations of I 0  through I 3 . As an illustration, the following discussion again considers the examples of situations (1) and (2) of the preceding paragraph, and now relates those to the operation of DAC  20 . 
     In situation (1), recall an earlier example is provided where the input is 0000 and the output asserts only conductor C 0 . In this case, transistor ST 0 ′ is enabled. Consequently, the voltage at tap T 0 ′ is connected to the output node V OUT2 . This situation, therefore, is the same as the operation of DAC  10  of the prior art when its conductor C 0  is asserted. 
     In situation (2), recall that an earlier example is provided where the input is 0001 and output asserts consecutive conductors C 0  and C 1 . Consequently, both transistors ST 0 ′ and ST 1 ′ conduct. As a result, a voltage loop is formed, which includes resistive element R 0 ′ as well as both conducting transistors ST 0 ′ and ST 1 ′. In this regard, it is now noted that in the present embodiment the resistance of each of the switching transistors is preferably equal to one another, as may be accomplished using replication. Further in the preferred embodiment, the resistance of each of the switching transistors when conducting is considerably higher than the resistance of the resistive elements R 0 ′ through R 7 ′. For example, preferably the resistance of each of the switching transistors is on the order of ten to one hundred times larger than the resistance of the resistive elements R 0 ′ through R 7 ′. Given the relative resistance values set forth above, and returning to the operation of DAC  20  in situation (2), the output voltage may be approximated by noting that resistance of element R 0 ′ may be considered negligible; thus, the concurrent conduction of transistors ST 0 ′ and ST 1 ′ effectively halves the total voltage at tap T 1 ′, that is, the output voltage at output node V OUT2  equals approximately ½* V (tap T1′) (assuming the potential at tap T 0 ′ is ground). In other words, with sufficient gate voltage, the two switching transistors are guaranteed to be in a linear region and, therefore, exhibit similar resistance. Moreover, because the resistance of these conducting transistors is much larger than that of the resistive element between the taps to which the transistors are connected, then the disturbance on the current in the resistive element is negligible. Thus, the operation for situation (2) in effect creates a level of interpolation between the voltage at tap T 0 ′ and the voltage at tap T 1 ′. In other words, the output voltage for situation (2) is approximately half way between the voltage at tap T 0 ′ at the voltage tap adjacent to it, namely, tap T 1 ′. Moreover, by examining the remaining situations provided by the truth table of FIG. 3, it will be apparent that the remaining values therein permit a total of sixteen different output voltages, where each voltage equals either the voltage at a given one of taps T 0 ′ through T 7 ′, or equals a voltage approximately equal to the half way voltage between two adjacent (ie., consecutively numbered) taps. As a result, the interpolation in effect gives rise to an additional bit of output possibilities. 
     From the above, it is now instructive to note various additional observations and advantages of the embodiment of FIG.  2 . For example, note that the number of possible output voltages provided by the described embodiment far exceeds the number of its taps. Further, DAC  20  includes only one more resistive element than DAC  10 , yet DAC  20  provides double the input and output capacity in terms of the number of binary inputs and corresponding levels of voltages which are outputted in response to those inputs. Consequently, the size and attention required of the resistor string, which tends to be the most difficult component of the device in terms of manufacturing, is approximately the same as that of the prior art, while the input/output capacity is doubled. Additionally, while the preceding is described in connection with DAC  20 , it may be applied to resistor strings in other DAC or ADC converters as will be appreciated by one skilled in the art, and further in view of the additional embodiments described below. 
     FIG. 4 illustrates a schematic of a DAC  30  according to another inventive embodiment DAC  30  includes many components which are comparable in formation and connection to components in DAC  20  of FIG. 2 and, to illustrate these like components, they are shown with the same reference identifiers as used in FIG. 2, with the exception that double apostrophes are shown with the identifier in FIG.  3 . In addition, and for reasons evident later, DAC  20  includes numerous additional switching transistors and, to distinguish the transistors in general, they are numbered in ascending order starting with a switching transistor ST 10 , as detailed later. Briefly first reviewing the elements of DAC  30  that are similar to those of DAC  20 , and assuming the reader is familiar with DAC  20 , DAC  30  includes a series-connected resistor string  32  having eight resistive elements R 0 ″ through R 7 ″, across which is connected a voltage source V S3 . In addition, each resistive element R 0 ″ through R 7 ″ connects to a pair of taps, thereby forming a total of nine taps T 0 ″ through T 8 ″. 
     A key distinction between DAC  30  in FIG.  4  and DAC  20  of FIG. 2 arises from a decoder circuit  34 , its 18-conductor bus  36 , and the switching transistors connected to the conductors of bus  36 . Specifically, decoder circuit  34  includes five inputs, designated I 0  through I 4  and, as shown below, is operable to selectively assert the conductors of bus  36  to cause corresponding ones of the switching transistors to conduct, thereby providing up to 32 different output voltages at output node V OUT3 . Before detailing the operation in this regard, it is first instructive to examine the connections with respect to the switching transistors and bus  36 . Each of taps T 0 ″ through T 8 ″ is connected to the output node V OUT3  via three switching transistors. As in the case for DAC  20  and for reasons understood later, in DAC  30  the resistance of each of the switching transistors when enabled is preferably equal to one another, and also the resistance of each of the switching transistors when enables is on the order of ten to one hundred greater than the resistance of the resistive elements R 0 ″ through R 7 ″. Looking now in greater detail to the connections concerning each tap and its three associated switching transistors, of these three transistors, two are connected in parallel such that their first source/drains are connected to a tap while their second source/drains are connected to output node V OUT3 , and the gates of these two transistors are connected to one another. For purposes of reference in the remainder of this document, these transistors are referred to as paired and parallel-connected transistors. Looking to tap T 0 ″ by way of example, it is connected to the first source/drains of paired and parallel-connected transistors ST 11  and ST 12 , with the second source/drains of transistors ST 11  and ST 12  connected to output node V OUT3  and the gates of transistors ST 11  and ST 12  connected to conductor C 1 . Turning now to the third transistor of the three transistors pertaining to each tap, it has a first source/drain connected to the tap, a second source/drain connected to output node V OUT3 , and its gate connected to a corresponding one of the conductors in bus  36 . Looking again to tap T 0 ″ by way of example, this third transistor is shown as transistor ST 10 , which has a first source/drain connected to tap T 0 ″, a second source/drain connected to output node V OUT3 , and its gate connected to conductor C 0 . 
     Given the above, note two additional observations. First, the examples of the preceding paragraph as well as the previous description should demonstrate to one skilled in the art that a comparable three transistor connection exists for each of the taps in DAC  30 . Briefly as another example, therefore, tap T 1 ″ is connected via three transistors to output node V OUT3 , where two of those transistors are paired and parallel-connected transistors ST 13  and ST 14  connected in parallel with their gates connected to a same conductor C 2 , and where a third of those transistors is transistor ST 15  which has its gate connected to a different conductor C 3 . Second, for each three transistor combination of this sort, all three transistors are connected in parallel with respect to one another. This point is particularly relevant for purposes of later appreciating the effect of this parallel connection on the output voltage provided at output node V OUT3 . 
     FIG. 5 a  illustrates a truth table for the preferred signal operation of decoder circuit  34  in FIG. 4, and FIG. 5 b  discussed later summarizes the asserted outputs shown in the truth table of FIG. 5 a.  Looking then to the truth table of FIG. 5 a  as well as the following discussion, again one skilled in the art may develop various circuit implementations to implement a circuit design for achieving the illustrated input/output relationships. Turning then to those relationships, FIG. 5 a  illustrates that the five inputs to decoder circuit  26  are permitted to provide any of thirty-two different combinations (i.e., 00000 through 11111), and in response decoder  34  produces a corresponding one of thirty-two different output combinations. More particularly and as detailed later, FIG. 5 a  illustrates that for any one set of inputs, the output of decoder circuit  34  will be such that corresponding ones of the switching transistors are enabled in one of four types of situations: (1) an assertion of a single one of the conductors in bus  36  to enable only a single transistor connected between a tap and output node V OUT3 ; (2) an assertion of three of the conductors in bus  36  to enable all three transistors connected between a tap and output node V OUT3  and also to enable a single transistor connected between the next higher order tap and output node V OUT3 ; (3) an assertion of two of the conductors in bus  36  to enable the paired and parallel-connected transistors connected between a tap and output node V OUT3  and also to enable the paired and parallel-connected transistors connected between the next higher order tap and output node V OUT3 ; and (4) an assertion of three of the conductors in bus  36  to enable a single transistor connected between a tap and output node V OUT3  and also to enable all three transistors connected between the next higher order tap and output node V OUT3 . Each of these four situations is further appreciated by way of examples, as are set forth immediately below. 
     Turning to the first situation provided by an output of decoder circuit  34 , recall that it involves an assertion of a single one of the conductors in bus  36  to enable only a single transistor connected between a tap and output node V OUT3 . An example is shown in the first line of the tables of FIGS. 5 a  and  5   b  and, indeed, in FIG. 5 b,  is identified in a “situation” column as situation  1 . In the first line of these tables, it is therefore shown that conductor C 0  is enabled. Returning now to FIG. 4 to appreciate situation  1 , when conductor C 0  is asserted, only transistor ST 10  conducts. In other words, only a single transistor ST 10  connected between tap T 0 ″ and output node V OUT3  conducts. Having established this, to further appreciate the present embodiment, attention is now directed to the output voltage with results in situation  1 . More particularly, since only a single transistor is conducting, then the voltage at output node V OUT3  equals approximately the same voltage than at the tap to which a source/drain of the conducting transistor is connected. In the example of transistor ST 10 , therefore, V OUT3  equals the voltage at tap T 0 ″. For purposes of later reference, this relationship is shown by the following Equation 1: 
     
       
         V OUT3 =V TAP    Equation 1  
       
     
     Turning to the second situation provided by an output of decoder circuit  34 , recall that it involves an assertion of three of the conductors in bus  36  to enable all three transistors connected between a tap and output node V OUT3  and also to enable a single transistor connected between the next higher order tap and output node V OUT3 . An example is shown in the second line of the tables of FIGS. 5 a  and  5   b  and is identified as situation  2  in FIG. 5 b.  In the second line of these tables, it is therefore shown that conductors C 0 , C 1 , and C 3  are enabled. Returning now to FIG. 4 to appreciate situation  2 , when conductors C 0  and C 1  are asserted, all three transistors ST 10 , ST 11 , and ST 12  connected to tap T 0 ″ conduct. In addition, since C 3  is asserted, a single transistor ST 15  connected between the next higher order tap, T 1 ″, and output node V OUT3 , also conducts. 
     By way of further illustration, FIG. 6 a  illustrates the resulting resistance network created by the four conducting transistors for situation  2  and, more particularly, for the example of the preceding paragraph relative to tap T 0 ″. Specifically, between tap T 0 ″ and output node V OUT3  are connected three parallel resistances corresponding to transistors ST 10 , ST 11 , and ST 12 , and between tap T 1 ″ and output node V OUT3  is connected a single resistance corresponding to transistor ST 15 . Recall from above that the resistance of each switching transistor is substantially the same. For purposes of discussion, let this value be identified as R. Consequently, the three parallel resistances between tap T 0 ″ and output node V OUT3  provide a resistance equal to R/3, and the single resistance between tap T 1 ″ and output node V OUT3  provides a resistance equal to R. If the differential voltage between taps T 1 ″ and T 0 ″ is identified as D, as shown in FIG. 6 a,  then by voltage division the voltage at output node V OUT3  may be defined as the voltage across the three parallel resistances relative to tap T 0 ″, as shown in the following Equation 2:                V   OUT3     =       D                   (       R   /   3         R   /   3     +   R       )       =       D        (     R     R   +     3      R         )       =       D        (     R     4      R       )       =     D   4                   Equation 2                                
     Accordingly, from Equation 2, one skilled in the art will appreciate that for situation  2 , the voltage at output node V OUT3  equals the voltage at tap T 0 ″ increased by a voltage of D/4. 
     Turning to the third situation provided by an output of decoder circuit  34 , recall that it involves an assertion of two of the conductors in bus  36  to enable the paired and parallel-connected transistors connected between a tap and output node V OUT3  and also to enable the paired and parallel-connected transistors connected between the next higher order tap and output node V OUT3 . An example is shown in the third line of the tables of FIGS. 5 a  and  5   b  and is identified as situation  3  in FIG. 5 b.  In the third line of these tables, it is therefore shown that conductors C 1  and C 2  are enabled. Returning now to FIG. 4 to appreciate situation  3 , when conductor C 1  is asserted, the paired and parallel-connected transistors ST 11  and ST 12  connected to tap T 0 ″ conduct, and at the same time when conductor C 2  is asserted, the paired and parallel-connected transistors ST 13  and ST 14  connected to tap T 1 ″ conduct. 
     By way of further illustration, FIG. 6 b  illustrates the resulting resistance network created by the two sets of conducting paired and parallel-connected transistors for situation  3  and, more particularly, for the example of the preceding paragraph relative to tap T 0 ″. Specifically, between tap T 0 ″ and output node V OUT3  are connected two parallel resistances corresponding to transistors ST 11  and ST 12 , and between tap T 1 ″ and output node V OUT3  is connected two parallel resistances corresponding to transistors ST 13  and ST 14 . Again, since the resistance of each switching transistor is substantially the same, then each set of paired and parallel-connected transistors provides a resistance between a tap and V OUT3  equal to R/2. Therefore, by voltage division the voltage at output node V OUT3  may be defined as the voltage across the paired and parallel-connected transistors relative to tap T 0 ″, as shown in the following Equation 3:                V   OUT3     =       D                   (       R   /   2         R   /   2     +     R   /   2         )       =       D        (     R     R   +   R       )       =       D        (     R     2      R       )       =     D   2                   Equation 3                                
     Accordingly, from Equation 3, one skilled in the art will appreciate that for situation  3 , the voltage at output node V OUT3  equals the voltage at tap T 0 ″ increased by a voltage of D/2. 
     Turning to the fourth situation provided by an output of decoder circuit  34 , recall that it involves an assertion of three of the conductors in bus  36  to enable a single transistor connected between a tap and output node V OUT3  and also to enable all three transistors connected between the next higher order tap and output node V OUT3 . An example is shown in the fourth lines of the tables of FIGS. 5 a  and  5   b  and is identified as situation  4  in FIG. 5 b.  In the fourth line of these tables, it is therefore shown that conductors C 0 , C 2 , and C 3  are enabled. Retuning now to FIG. 4 to appreciate situation  4 , when conductor C 0  is asserted, a single transistor ST 10  connected between tap T 1 ′ and output node V OUT3  conducts. In addition, when C 2  and C 3  are asserted, all three transistors ST 13 , ST 14 , and ST 15  connected to the next higher ordered tap T 1 ″ conduct. 
     By way of further illustration, FIG. 6 c  illustrates the resulting resistance network created by the conducting transistors for situation  4  and, more particularly, for the example of the preceding paragraph relative to tap T 0 ″. Specifically, between tap T 0 ″ and output node V OUT3  is connected a single resistance corresponding to transistor ST 10 , and between tap T 1 ″ and output node V OUT3  is connected three parallel resistances corresponding to transistors ST 13 , ST 14 , and ST 15 . Once more, since the resistance of each switching transistor is substantially the same, the single resistance between T 0 ″ and output node V OUT3  provide a resistance equal to R, and the three parallel resistances between tap T 1 ″ and output node V OUT3  provides a resistance equal to R/3. Consequently, by voltage division the voltage at V OUT3  may be defined as the voltage across the single resistance relative to tap T 0 ″, as shown in the following Equation 4:                V   OUT3     =       D                   (       R   /   3       R   +     R   /   3         )       =       D        (       3      R         3      R     +   R       )       =       D        (       3      R       4      R       )       =       3      D     4                   Equation 4                                
     Accordingly, from Equation 4, one skilled in the art will appreciate that for situation  4 , the voltage at output node V OUT3  equals the voltage at tap T 0 ″ increased by a voltage of 3D/4. 
     Having reviewed each of the four situations that may occur for a given tap in DAC  30 , it is now instructive to note various additional observations and advantages of the embodiment of FIG.  4 . For example, for each tap having a resistive element connecting it to a higher ordered tap, a total of four different voltage levels may be output relative to that tap, as shown by Equations 1 through 4. More particularly, these voltage consist of the voltage at the tap, or that voltage increased by {fraction ( 1 / 4 )}D, {fraction ( 1 / 2 )}D, or {fraction ( 3 / 4 )}D. In other words, the additional switching transistors and control thereof permit a multiple level interpolation between tap voltages, where in the example of DAC  30  the interpolation levels are at increments of one-fourth the tap voltage. Moreover, since DAC  30  includes eight taps which have a resistive element connecting the tap to a higher ordered tap (tap T 8 ″ is not connected to such a higher ordered tap), then a total of  32  different outputs are provided. In other words, the interpolation in effect gives rise to an additional two bits of output possibilities. Thus, once again the number of possible output voltages provided by the described embodiment far exceeds its number of taps. Further, DAC  30  includes only one more resistive element than DAC  10 , yet DAC  30  provides four times the output capacity in terms of the number of binary inputs and corresponding levels of voltages which are outputted in response to those inputs. As a result, and in even greater fashion than DAC  20 , the size and attention required of the resistor string is approximately the same as that of the prior art, while the input/output capacity is greatly enhanced. 
     In closing, FIG. 7 illustrates a plan view of a preferred semiconductor layout for forming a cell of DAC  30 , where the cell depicts each of three switching transistors, and by way of example transistors ST 13 , ST 14 , and ST 15  as relating to tap T 1 ″ in FIG. 4 are shown. More particularly, transistors ST 13  and ST 14  are formed in parallel, and form a square geometry. In addition, transistors ST 13  and ST 14  share the same gate conductor which corresponds to conductor C 2 . Further, note that the gate conductor extends over these transistors and may continue to overlie other transistors as well. Specifically in this regard, while DACs  20  and  30  have been illustrated with respect to a resistance string in a single dimension, it is contemplated that the present inventive teachings also apply to a DAC which includes a meandering resistor string which therefore extends in two dimensions. In this case, therefore, a typical configuration includes an array type configuration including the meander and switching elements such that a single row and column of the array are selected at a time, thereby providing an output voltage. In view of the possibility of this alternative configuration, conductor C 2  (and C 3 ) as shown in FIG. 7 extends to suggest that it also may traverse other paired and parallel-connected transistors in other columns of the array. Looking further to transistor ST 13 , it is shown to include a contact CT 1 , which is formed to connect its source/drain S/D 1 (ST 13 ) downward to the underlying resistor string, RS, which in FIG. 7 is shown in phantom. Looking further to transistor ST 14 , it extends perpendicularly from the square geometry created by the paired and parallel-connected transistors. In addition, transistor ST 14  is shown to include a contact CT 2 , which may be formed to connect its source/drain S/D 2 (ST 14 ) to a conductor corresponding to the output node V OUT3 , which is preferably formed overlying the transistor and is also shown in phantom. Lastly looking to transistor ST 15 , its source/drain S/D 1 (ST 15 ) is essentially formed as the same region, and thereby is electrically connected, to the source/drain S/D 1 (ST 14 ) of transistor ST 14 . Further, the source/drain S/D 2 (ST 15 ) of transistor ST 15  also includes an electrical contact CT 3  for connecting that region to the overlying conductor corresponding to the output node V OUT3 . Lastly, given an appreciation of the geometry presented in FIG. 7, note further in the preferred embodiment that generally the source/drain regions have silicide reacted into them so that even though the conductance path may bend in various areas, a large majority of the resistance in the path is that in the channel under the gate, since the silicide provides very low resistance cladding on top of the diffusion. 
     From the above, it may be appreciated that the above embodiments provide numerous advantages over the prior art, many of which have been set forth above and additional ones of which will be appreciated by one skilled in the art In addition, while the present embodiments have been described in detail, various substitutions, modifications or alterations could be made to the descriptions set forth above without departing from the inventive scope. Indeed, some of these type of variations have been set forth above such as the use of the preceding teachings in either DACs or ADCs, and still others may be ascertained. As yet another example, therefore, while the illustrations have shown only a single channel DAC, the present inventive teachings may apply to a double channel DAC, whereby a single resistance string is used but provides tap voltages to dual independent switching networks and outputs. As still another example, while the preceding embodiments have shown either one or three levels of interpolations between a pair of resistor string taps, still other configurations of switching devices may be implemented to achieve still additional levels of interpolation. Moreover, while DAC  30  has been shown to include only four switching situations per tap, still other variations may be included in the control of the decoder to achieve still further varying outputs based on different inputs. As yet another example, while n-channel transistors have been shown in the various embodiments, an alternative structure may be formed using p-channel transistors. As a final example, while the illustrations have been directed to DACs with three or four inputs, the present teachings apply equally to DAC having greater or lesser input/output capacities. Thus, all of the preceding as well as other ascertainable examples should further illustrate the inventive scope, where that scope is defined by the following claims.