Abstract:
A redundancy system for data communications upon two duplicate communication channels, each having transmission and reception circuits, characterized by a switching circuit for selecting one of said two communication channels, a single error detection circuit for detecting an error in the signal transmitted, and a control circuit for the switching circuit arranged to cause said two communication channels to alternately transmit signals when both the channels are in normal operation, and to cause one of said two channels to be selected when the other fails. The two channels share the error detection circuit and the control circuit and can therefore be built at a reduced cost and operated efficiently. Since the two channels are regularly checked for errors, they are operated with increased reliability.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to redundancy systems for data communications wherein two duplicate communication channels each having transmission and reception circuits are provided for reliability. Such redundancy systems frequently are used in process control arrangements to permit the controlled process to continue despite equipment breakdown. 
     2. Description of the Prior Art 
     Prior art techniques use various different redundancy systems to attain high-reliability data communications. Such redundancy systems typically are arranged either as parallel redundancy systems or as standby redundancy systems. The former is characterized in that the two duplicate systems are operated in parallel and when any discrepancy arises between data transmitted by the two systems, the failed side is isolated for services. In standby redundancy systems, one of the two systems serves as a standby for the other. Both such redundancy systems, however, are not fully satisfactory. The parallel redundancy system must have two complete pairs of control and error detection circuits, entailing a significant cost. In the standby redundancy system, a failure in the standby side remains undetected until the master side fails because the standby becomes active only in an emergency. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide an improved redundancy system for data communications. It is a specific object of the invention to provide a redundancy system which uses a minimum of equipment and therefore can be constructed at less expense, and which maintains regular supervision of both duplicate components to promptly detect failures. 
     In a preferred embodiment of the invention to be described hereinbelow in detail, the redundancy system transmits data over two duplicate communication channels each having transmission and reception circuits. Switching means select either one of the two channels to transmit data, and the transmissions are monitored by an error detecting means which detects errors in the signal transmitted over either channel. The switching means is controlled by a means which causes the switching means to alternate signal transmissions over the two communication channels when the channels are in normal operation, and, when an error in one channel is detected, causes the switching means to select the other channel. Such an arrangement is advantageous because both channels are regularly tested for errors, and a single error detection and control means can serve both channels. 
     Other objects, aspects and advantages of the invention will be pointed out in, or apparent from, the following detailed description considered together with the following drawings. 
    
    
     DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram showing a master data communications station embodying the redundancy system of the present invention; and 
     FIG. 2 is a block diagram showing a slave data communications station embodying the redundancy system of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows in block form a master data communications station constructed according to the invention and comprising duplicate transmission channels 1 and 1&#39; having couplers 2 and 2&#39;, transmitters 3 and 3&#39;, and receivers 4 and 4&#39;. The transmitters and receivers of the two channels are connected to a channel switching circuit 80 including AND gates 5 and 5&#39;, and 6 and 6&#39;, an OR gate 7, and a JK flip-flop 8. The channel switching circuit is in turn connected to an error detection circuit 9, a control circuit 10, and a check bit generator circuit 11. 
     A data signal to be transmitted from the master station is supplied to the check bit generator circuit 11 through the input or sending terminal Sin and branched to the AND gates 5 and 5&#39; and thence to the transmitters 3 and 3&#39;. Data signals received by the master station with receivers 4 and 4&#39; go to the OR gate 7 through the AND gates 6 and 6&#39;. The output of OR gate 7 is led to the output terminal Rout by way of the error detection circuit 9. 
     An error output E from the error detection circuit 9 is led to the terminal E of the control circuit 10, which is arranged to generate, in a manner described below, pulses J, K and T (trigger) for the JK flip-flop circuit 8. The AND gates 5 and 6 for communications channel 1 are enabled by the output Q of the JK flip-flop circuit 8, and the AND gates 5&#39; and 6&#39; for communications channel 1&#39; are enables by the output Q of the JK flip-flop circuit 8. 
     FIG. 2 shows in block form a slave data communications station constructed according to the invention and arranged to communicate with a master station as shown in FIG. 1. The slave station joins transmission channels 1 and 1&#39; through couplers 12 and 12&#39;, transmitters 13 and 13&#39;, and receivers 14 and 14&#39;. The slave station further comprises an OR gate 15, a check bit generator circuit 16, and an error detection circuit 17. A signal to be transmitted from the slave station to the master station is supplied to the check bit generator circuit 16 through the terminal Sin and branched to the transmitters 13 and 13&#39;. The outputs of the receivers 14 and 14&#39; are combined by way of the OR gate 15 and led to the output terminal Rout through the error detection circuit 17. The error detection output E&#39; of the circuit 17 is led to the terminal E-inhibit and utilized with, e.g., an inhibiting gate, to inhibit the use of a received signal in which an error has been detected. 
     The redundancy system formed as illustrated in FIGS. 1 and 2 operates in the following manner. The master station initiates a communication by sending a transmission statement to the slave station, which is arranged to in turn send a return statement to be received by the master station, thus concluding one communication. While the two communication channels 1 and 1&#39; and their transmission and reception circuits are in normal operation, the control circuit 10 of the master station is arranged to generate signals J = 1 and K = 1, and in addition is arranged to generate a clock pulse from the terminal T which precedes the start of each communication. This clock pulse triggers the flip-flop circuit 8 to generate 1 and 0 outputs alternately at its terminals Q and Q, thereby enabling the AND gates 5 and 6, alternately with the AND gates 5&#39; and 6&#39;. Thus the two communications channels 1 and 1&#39; are alternately used for communications, and have transmissions regularly checked for errors, eliminating possibilities of overlooking a failure developed in a standby system. 
     The circuit 9 detects an error in either communications channel 1 or 1&#39; when it fails. Upon detection of an error, the normal channel is chosen by control circuit 10 to remain in operation by selecting the outputs (J, K) = (1, 0) or (J, K) = (0, 1) to be sent to the flip-flop 8, and the failed channel concurrently is isolated for repair. The control circuit 10 can easily determine the channel to select for continued operation, as it is always the other one from the channel in which the error is detected. Hence the redundancy system of the present invention does not need two error detection circuits and two control circuits as required in prior art parallel redundancy systems. 
     As described, one of the two alternative channels is selected by the master station, and the slave station operates on whichever channel is selected. Thus, if transmitter 3 generates a signal upon channel 1 and transmitter 3&#39; generates no signal upon channel 1&#39;, then, in the slave station, an output will appear only at the receiver 14 and not at the receiver 14&#39;. Before reaching output terminal R, however, the output of the receiver 14 goes to the error detection circuit 17 through the OR gate 15. When a transmission statement from the master station is received correctly by the slave station, a return statement is supplied to the transmission input terminal Sin of the slave station and thence to the transmitters 13 and 13&#39; through the check bit generator circuit 16. If a failure takes place in the transmission channel between the master station and the slave station, the failure cannot be detected in the master station itself. However, if this happens, the error output E&#39; of the error detection circuit 17 inhibits the slave station from performing a receiving operation, and thus no return transmission statement is supplied to the master station. Receiving no return statement, the master station becomes aware of the failure and selects the other channel for continued operation. Thus, for this type of error also, a single error detection circuit 17 suffices for the two channels. 
     For the sake of simplicity, FIG. 2 shows a circuit arrangement in which a return signal from the slave station is sent over both transmission channels 1 and 1&#39; concurrently, with the appropriate channel being selected in the master station by the transmission channel switching circuit 80. If desired, the slave station can be arranged toa transmit over only one channel. 
     In the redundancy system of the present invention, errors in data transmission may be determined in any convenient fashion. For example, the concept of cyclic redundancy, or parity checks or other suitable means may be used to detect an error bit in transmitted data. In addition, in the disclosed embodiment, switching circuit 80 operates by inhibiting both input and output with gates 5 and 6 or 5&#39; and 6&#39; at the transmitter and receiver when either channel is selected. Channel selection also may be made by other suitable means such as with a channel selector switch or by disconnecting power to the transmitter and receiver. 
     If desired, error detection operations may be repeated several times in succession after a failure is initially detected on one channel. This will obviate switching from one channel to the other each time in response to a transient error bit such as may be ascribed to a channel noise, thus permitting the redundancy system to operate with stability and efficiency. 
     When a discrepancy is found existing between the two channels with respect to transmission delay or transmission quality when one system is switched to the other, a delay adjusting or level adjusting means may additionally be used to equilibrate the two systems. 
     While the master and slave stations have been described as separate entities, their elements may be incorporated into one station for the purpose of the invention. 
     As described above, two communications channels with transmission and reception circuits are operated alternately in the redundancy system of the present invention, to make it possible to quickly detect a failure on either side and to use one error detection circuit and one control circuit in common for the two systems, with the result that an efficient, economical redundancy system is realized. 
     Although one preferred embodiment of the invention and specific modifications thereof have been described herein in detail, it is to be understood that this is for the purpose of illustrating the invention, and should not be construed as limiting the scope of the invention, since numerous variations may occur to those skilled in the art without departing from the spirit of the invention.