Abstract:
A central processing unit, a read only memory, a random access memory, an oscillator for supplying a clock signal to the central processing unit, a peripheral circuit and a control circuit are provided. The control circuit supplies a first voltage to the central processing unit, the read only memory, the random access memory and the peripheral circuit in synchronization with rising/falling of the clock signal, and supplies a second voltage to the central processing unit with passage of predetermined time after the rising/falling of the clock signal. The first voltage enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to change their operations. The second voltage is lower than the first voltage, and enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to maintain their operations.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a single chip microcomputer suitably used for an electronic device such as a video camera or the like operated at a plurality of speeds. More particularly, the invention relates to a single chip microcomputer capable of reducing power consumption. 
     2. Description of the Related Art 
     A conventional single chip microcomputer comprises two kinds of oscillators provided to generate high-speed and low-speed clock signals, respectively. During a high-speed operation, a central processing unit (referred to as a CPU, hereinafter) is operated by a high-speed clock signal. During a low-speed operation, the CPU is operated by a low-speed clock signal. FIG. 1 is a block diagram showing the constitution of such a conventional single chip microcomputer. 
     The conventional single chip microcomputer shown comprises first and second oscillators  103  and  104 , to which power supply voltage Vdd is supplied from a power supply terminal. An oscillation frequency of the first oscillator  103  is set equal to, e.g., 20 MHz, while an oscillation frequency of the second oscillator  104  is set equal to, e.g., 32 kHz. In other words, the first oscillator  103  is designed for a high-speed clock signal, whereas the second oscillator  104  is designed for a low-speed clock signal. 
     The single chip microcomputer also comprises a selector  105  which is provided to select each of the clock signals G 5  and G 6  of the first and second oscillators  103  and  104 , and output it as a clock signal G 4  to a CPU  110 . The microcomputer further comprises a random access memory (referred to as a RAM, hereinafter)  106 , a read only memory (referred to as a ROM, hereinafter)  107 , and a peripheral circuit  108 . An I/O port  111  is also provided to transfer a signal with an external unit, and with the CPU  110  for transferring a signal with the CPU  110 . 
     In addition, a control circuit  112  is provided to control an oscillation frequency of a clock signal inputted to the CPU  110  based on a switching signal A 1  outputted therefrom The control circuit  112  outputs an oscillator control signal G 1  to the first oscillator  103 , where the control signal G 1  is used to switch the operation of the first oscillator  103  between ON and OFF. The control circuit  112  outputs an oscillator control signal G 2  to the Second oscillator  104 , where the control signal G 2  is used to switch the operation of the second oscillator  104  between ON and OFF. On the other hand, the clock signals G 5  and G 6  are inputted not only to the selector  105  but also to the control circuit  112 . To the selector  105 , the control circuit  112  outputs a clock selection signal G 3  used to control the selection of the clock signals G 5  and G 6 . 
     The power supply terminal directly supplies power supply voltage Vdd to the RAM  106 , the ROM  107 , the peripheral circuit  108 , the CPU  110 , the I/O port  111  and the control circuit  112 . 
     In addition, a reset signal RST is inputted to each of the CPU  110  and the control circuit  112  to realize its initial state. 
     FIG. 2 is a timing chart showing an operation before/after the conventional single chip microcomputer is changed from a high-speed operation to a low-speed operation. In the conventional single chip microcomputer constructed in the foregoing manner, when an operating speed is changed from high-speed operation to low-speed operation, the CPU  110  transmits a high-level switching signal A 1  to the control circuit  112  based on a program stored in the ROM  107 . Then, upon having received the high-level switching signal A 1 , the control circuit  112  sets the level of an oscillator control signal G 1  to be low by a specified timing. Accordingly, the operation of the first oscillator  103  is stopped. On the other hand, the level of an oscillator control signal C 2  is always high, and the second oscillator  104  is in a constantly operated state. Thus, it is only the second oscillator  104  that is operated during a low-speed operation. 
     Therefore, in the conventional single chip microcomputer, since power consumed by the first oscillator  103  during the low-speed operation is 0, a charging/discharging current is reduced, bringing about a reduction in power consumption like that shown in FIG.  2 . 
     However, there is a drawback inherent in such a conventional single chip microcomputer. Specifically, even if the charging/discharging current is reduced, no reduction occurs in an OFF leakage current caused to flow when a transistor in the chip is microstructured in dimension. Consequently, in a microstructuring process applied to the microcomputer requiring a high-speed operation, a leakage current component is increased, which makes it impossible to achieve low power consumption. If a requested operating speed is not so high, the OFF leakage current can be suppressed by setting high a threshold voltage Vt of the transistor, even when the transistor is microstructured. If a high-speed operation is requested, however, since a low threshold voltage Vt is necessary, power consumption during the low-speed operation is increased by the OFF leakage current when the transistor is microstructured. 
     Under these circumstances, regarding the microcomputer requiring the high-speed operation, one capable of reducing power consumption has been proposed (Japanese Patent Laid-open Application No. Sho. 60-10318). In the microcomputer described therein, two kinds of power supply voltages and clock signals are switched according to an operating speed, and power consumption is thereby reduced during the low-speed operation. The power supply voltages and the clock signals are simultaneously switched by a control circuit. 
     However, even in the conventional microcomputer described in Japanese Patent Laid-Open Application No. Sho. 60-10318, power consumption during the low-speed operation is still large, and there is a demand for a further reduction in power consumption. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a single chip microcomputer capable of reducing power consumption. 
     According to one aspect of the present invention, a single chip microcomputer comprises a central processing unit which stores a program executed by the central processing unit, a read only memory, a random access memory which holds data processed by the central processing unit, an oscillator which supplies a clock signal to the central processing unit, a peripheral circuit which transfers a signal to the central processing unit and receives a signal from the central processing unit, and a control circuit. The control circuit supplies a first voltage to the central processing unit, the read only memory, the random access memory and the peripheral circuit in synchronization with rising/falling of the clock signal. The control circuit supplies a second voltage to the central processing unit with passage of predetermined time after the rising/falling of the clock signal. The first voltage enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to change their operations. The second voltage is lower than the first voltage, and enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to maintain their operations. 
     According to the aspect of the present invention, a voltage supplied to each of the central processing unit, the read only memory, the random access memory and the peripheral circuit is set equal to one for enabling the respective units and circuits to be operated in synchronization with rising/falling of the clock signal. In other words, a voltage is set for enabling the respective units and circuits to change their operations. In addition, with passage of predetermined time after the rising/falling of the Clock signal, a voltage is reduced to one for enabling the respective units and circuits to maintain their operations. Accordingly, leakage current is reduced while the stable operation of each circuit is maintained. As a result, power consumption is reduced. Especially, when two kinds of high-speed and low-speed clock signals are used, a reduction in power consumption is considerable if the foregoing control is applied during a low-speed clock operation. Further, by limiting a circuit to receive the supply of a voltage for a fixed period to the RAM or its partial area, power consumption can be further reduced. 
     According to another aspect of the present invention, a single chip microcomputer comprises a central processing unit, a read only memory which stores a program executed by the central processing unit, a random access memory which holds data processed by the central processing unit, a first oscillator which supplies a first clock signal to the central processing unit, a second oscillator which supplies a second clock signal having a frequency lower than that of the first clock signal to the central processing units a clock selector which selects and supplies any one of the first and second clock signals to the central processing unit, and a peripheral circuit which transfers a signal to the central processing unit and receives a signal from the central processing unit. The single chip microcomputer further comprises a first step-down circuit which steps down a power supply voltage supplied to a power supply terminal to a first voltage, a second step-down circuit which steps down the power supply voltage to a second voltage, and a control circuit. The first voltage enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to be operated with the second clock signal. The second voltage is lower than the first voltage and enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to maintain their operations. The control circuit controls voltage supplied to the central processing unit, the read only memory, the random access memory and the peripheral circuit, and controls a clock signal supplied to the central processing unit in relation to the first and second clock signals. 
     The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings: 
     FIG. 1 is a block diagram showing a constitution of a conventional single chip microcomputer; 
     FIG. 2 is a ting chart showing an operation before/after the conventional single chip microcomputer is changed from a high-speed operation to a low-speed operation; 
     FIG. 3 is a block diagram showing a structure of a single chip microcomputer according to a first embodiment of the present invention; 
     FIG. 4 is a block diagram showing a structure of a control circuit  12  in the first embodiment; 
     FIG. 5 is a block diagram showing a structure of a selector in the first embodiment; 
     FIG. 6 is a timing chart showing an operation before/after a nigh-speed operation is changed to a low-speed operation according to the first embodiment; 
     FIG. 7 is a timing chart showing an operation before/after a low-speed operation is changed to a high-speed operation according to the first embodiment; 
     FIG. 8 is a flowchart showing an operation of the single chip microcomputer of the first embodiment; 
     FIG. 9 is a block diagram showing a structure of a single chip microcomputer according to a second embodiment of the present invention; 
     FIG. 10 is a block diagram showing a structure of a control circuit  22  in tne second embodiment; 
     FIG. 11 is a block diagram showing a structure of a clock timer  21  in the second embodiment; 
     FIG. 12 is a timing chart showing an operation before/after a high-speed operation is changed to a low-speed operation according to the second embodiment; 
     FIG. 13 is a timing chart showing an operation during a low-speed operation period according to the second embodiment; 
     FIG. 14 is a timing chart showing an operation before/after a low-speed operation is changed to a high-speed operation according to the second embodiment; and 
     FIG. 15 is a flowchart showing an operation of the single chip microcomputer of the second embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
     FIG. 3 is a block diagram showing the structure of a single chip microcomputer according to a first embodiment of the present invention. 
     In the first embodiment, first and second step-down circuits  1  and  2  are provided to supply voltages to a CPU  10 . From a power supply terminal a power supply voltage Vdd is supplied to each of the first and second step-down circuits  1  and  2 . The first step-down circuit  1  steps down the power supply voltage Vdd to a voltage Vdd 1  and then outputs it. The second step-down circuit  2  steps down the power supply voltage Vdd to a voltage Vdd 2  and then outputs it. The voltage Vdd 1  is larger than the voltage Vdd 2 . For example, the power supply voltage Vdd is set at 3.3V; the voltage Vdd 1  at 2V; and the voltage Vdd 2  at 1V. According to the present invention, however, voltages should not be limited to these, and any levels may be set as long as the voltage Vdd 1  is equal to or higher than a voltage for enabling a circuit operated by a low-speed clock signal to start its operation, and the voltage Vdd 2  is equal to or higher than a voltage for enabling the circuit operated by the low-speed clock signal to hold its operating state 
     The single chip microcomputer of the first embodiment comprises a first oscillator  3 , to which the power supply voltage Vdd is supplied from the power supply terminal, and a second oscillator  4 , to which the voltage Vdd 1  is supplied from the first step-down circuit  1 . An oscillation frequency of the first oscillator  3  is set larger than that of the second oscillator  4 . In other words, the first oscillator  3  is designed for a high-speed clock signal, while the second oscillator  4  is designed for a low-speed clock signal. For example, the oscillation frequency of the first oscillator  3  is set at 20 MHz; and that of the second oscillator  4  at 32 kHz. According to the present invention, however, oscillation frequencies should not be limited to these. 
     In addition, the single chip microcomputer comprises a selector  5  which is provided to select each of the clock signals G 5  and G 6  of the first and second oscillators  3  and  4 , and output it as a clock signal G 4  to the CPU  10 . The single chip microcomputer also comprises a RAM  6 , a peripheral circuit  8 , a level-shift circuit  9 , which are provided to transfer/receive a signal to/from the CPU  10 , and a ROM  7  provided to store a program executed by the CPU  10 . An I/O port  11  is also provided to transfer/receive a signal to/from an external unit, and to/from the level-shift circuit  9 . 
     Further, the single chip microcomputer according to the first embodiment comprises a control circuit  12  for controlling a voltage supplied to the CPU  10  and an oscillation frequency based on a switching signal A 1  outputted from the CPU  10 . A field effect transistor Tr 1  is connected between the control circuit  12  and the power supply terminal; a transistor Tr 2  between the CPU  10  and the first step-down circuit  1 ; and a transistor Tr 3  between the CPU  10  and the second step-down circuit  2 . To the gates of these transistors Tr 1 , Tr 2 , and Tr 3 , voltage selection signals T 1 , T 2  and T 3  are respectively outputted from the control circuit  12 . The transistors Tr 1  to Tr 3  may be all P-channel transistors 
     The control circuit  12  outputs an oscillator control signal G 1  to the first oscillator  3 , the control signal G 1  being used to switch its operation between ON and OFF, and an oscillator control signal G 2  to the second oscillator  4 , the control signal G 2  being used to switch its operation between ON and OFF. On the other hand, the clock signals G 5  and G 6  are inputted not only to the selector  5  but also to the control circuit  12 . Further, to the selector  5 , the control circuit  12  outputs a clock selection signal G 3  to control the selection of the clock signals G 5  and G 6 . 
     Power supply voltages Vdd are directly supplied to the level-shift circuit  9  and the I/O port  11  from the power supply terminal. Any of the power supply voltage Vdd, the voltage Vdd 2  and the voltage Vdd 1  are supplied through the transistors Tr 1  to Tr 3  to the RAM  6 , the ROM  7 , the peripheral circuit  8  and the selector  5 . A voltage is also supplied through each of the transistors Tr 1  to Tr 3  to the level-shift circuit  9   
     In addition, a reset signal RST is inputted to each of the CPU  10  and the control circuit  12  to realize its initial state 
     FIG. 4 is a block diagram showing a structure of the control circuit  12  of the first embodiment. 
     The control circuit  12  includes flip-flops FF 1  and FF 3 , the clock signal G 5  being inputted to the C terminals thereof, and an inverter IV 1 , the clock signal C 5  being inputted to the input terminal thereof. Flip-flops FF 2  and FF 4 , whose C terminals are connected to the output terminal of the inverter IV 1  are provided. The Q terminal of the flip-flop FF 1  is connected to the D terminal of the flop-flop FF 2 ; the Q terminal of the flip-flop FF 2  is connected to the D terminal of the flip-flop FF 3 ; and the Q terminal of the flip-flop FF 3  is connected to the D terminal of the flip-flop FF 4 . 
     The control circuit  12  also includes flip-flops FF 5  and FF 7 , the clock signal G 6  being inputted to the C terminals thereof, and an inverter IV 3 , to which a switching signal A 1  is inputted. The D terminal of the flip-flop FF 5  is connected to the output terminal of the inverter IV 3 . The control circuit  12  also includes an inverter IV 3 , the clock signal G 6  being inputted to the input terminal thereof, and a flip-flop FF 6 , whose C terminal is connected to the output terminal of the inverter IV 2  and whose D terminal is connected to the Q terminal of the flip-flop FF 5 . The Q terminal of the flip-flop FF 6  is connected to the D terminals of the flip-flops FF 1  and FF 7 . 
     In addition, a flip-flop FF 13  is provided, the switching signal A 1  being inputted to the S terminal thereof, and the R terminal thereof being connected to the Q terminal of the flip-flop FF 4 . A signal outputted from the Q terminal of the flip-flop FF 13  is an oscillator control signal G 1 . A two-input AND gate AND 2  is also provided, to which the switching signal A 1  and the output signal of the flip-flop FF 6  are entered. A flip-flop FF 14  is provided, the output signal of the AND gate AND 2  being inputted to the S terminal thereof. An inverter IV 9  is provided, whose input terminal is connected to the Q terminal of the flip-flop FF 14 . A two-input OR gate OR 1  is provided, one input terminal thereof being connected to the output terminal of the inverter IV 9 , and the reset signal RST being inputted to the other input terminal thereof. An oscillation stabilizing counter  13  is provided, the clock signal G 5  being inputted to the input terminal I thereof, and the output terminal of the OR gale OR 1  being connected to the reset terminal R thereof. This oscillation stabilizing counter  13  contains the preset number of pulses from the rising of the clock signal G 5  to its stabilization. After input of the output signal of the OR gate OR 1  to the reset terminal R, the number of pulses therefor is counted. 
     The control circuit  12  further includes a two-input OR gate OR 2 , whose input terminals are connected to the output terminal of the OR gate OR 1  and the output terminal O of the oscillation stabilizing counter  13 . A flip-flop FF 11  is provided, whose R terminal is connected to the output terminal of the OR gate OR 2 , and whose S terminal is connected to the Q terminal of the flip-flop FF 6 . A signal outputted from the flip-flop FF 11  is a clock selection signal G 3 . Further, an inverter IV 10  is provided to invert the output signal of the flip-flop FF 11 , and a two-input OR gate OR 3  is provided to input the output signal of the inverter IV 10  and the reset signal RST. The output terminal of the OR gate OR 3  is connected to the R terminal of the flip-flop FF 14 . 
     In addition, a flip-flop FF 12  is provided, to whose S terminal the reset signal RST is inputted, and whose R terminal is connected to the Q terminal of the flip-flip FF 7 . A signal outputted from the Q terminal of the flip-flop FF 12  is a voltage selection signal T 1 . 
     The control circuit  12  also includes inverters IV 4  and IV 5 , to which the switching signal A 1  is inputted, and an inverter IV 6  connected to the Q terminal of the flip-flop FF 12 . A delay circuit D 1  having delay time t 1  and an inverter IV 7  are connected in series to the output terminal of the inverter IV 5 . A two-input exclusive NOR gate EXNOR 1  is provided, whose input terminal is connected to the output terminal of each of the inverters IV 4  and IV 7 . A two-input AND gate AND 1  is provided, whose input terminal is connected to the output terminal of each of the exclusive NOR gate EXNOR 1  and the inverter IV 7 . The output signal of the exclusive NOR gate EXNOR 1  is inputted to an inverter IV 8 . The output signal of the inverter IV 8  is a voltage selection signal T 2 . An OR gate OR 4  is also provided, whose input terminal is connected to the AND gate AND 1  and the Q terminal of the flip-flop FF 12 . The output signal of this OR gate OR 4  is a voltage selection signal T 3 . 
     Furthermore, the control circuit  12  includes a circuit provided to output an oscillator control signal G 2 . According to the described embodiment, while the single chip microcomputer itself is in an operating state, the oscillator control signal G 2  is always at a high level, requiring no special control Thus, explanation thereof will be omitted. 
     FIG. 5 is a block diagram showing the constitution of the selector  5  of the first embodiment. 
     The selector  5  includes an inverter IV 11  for inverting the clock selection signal G 3 , a two-input AND gate AND 11 , to which the output signal of the inverter IV 11  and the clock signal G 5  are inputted, and a two-input AND gate AND 12 , to which the clock signals G 3  and G 6  are inputted. In addition, an OR gate OR 11  is provided, to which the output signals of the AND gates AND 11  and AND 12  are inputted. The output signal of the OR gate OR 11  is a clock signal G 4 . 
     Next, description will be made of the operation of the single chip microcomputer according to the first embodiment constructed in the foregoing manner. FIG. 6 is a timing chart showing an operation before/after a high-speed operation is changed to a low-speed operation in the first embodiment; FIG. 7 a timing chart showing an operation before/after a low-speed operation is changed to a high-speed operation in the first embodiment; and FIG. 8 a flowchart showing the operation of the single chip microcomputer according to the first embodiment 
     When the reset signal RST to the CPU  10  and the control circuit  12  is released, as shown in FIG. 6, the single chip microcomputer itself starts its normal operation (step S 1 ). In this normal operation, the level of the oscillator control signal G 1  is high, and the first and second oscillators  3  and  4  are in operating states. The level of the clock selection signal G 3  is low, and the selector  5  selects the high-speed clock signal G 5  and supplies it as the clock signal G 4  to the CPU  10 . On the other hand, although the level of the voltage selection signal T 1  is low, the levels of the voltage selection signals T 2  and T 3  ore high, and power supply voltages Vdd are supplied to the CPU  10 , the control circuit  12 , the RAM  6 , the ROM  7  and the peripheral circuit  8 . Accordingly, the normal operation is carried out by a high-speed clock. 
     when an operation is changed from the normal operation to a low-speed operation, the CPU  10  lowers the switching signal A 1  based on the program stored in the ROM  7 . Upon receiving this signal, the control circuit  12  raises the clock selection signal G 3  in synchronization with the next falling of the low-speed clock signal G 6 . Then, the selector  5  selects the low-speed selection signal G 6 , and supplies it as the clock signal G 4  to the CPU  10  (step S 2 ). 
     Subsequently, the control circuit  12  counts the high-speed clock signal G 5  equivalent to two clocks, and then lowers the oscillator control signal G 1 . In this way, the operation of the first oscillator  3  is stopped (step S 3 ). The control circuit  12  raises the voltage selection signal T 1  and lowers the voltage selection signal T 2  in synchronization with the next rising of the control signal G 6  after the rising of the clock selection signal G 3  as described above. Accordingly, a voltage supplied to the CPU  10 , the control circuit  12  or the like is lowered from the power supply voltage Vdd to the voltage Vdd 1 , which is lower. 
     With the passage of time t 1  after the rising of the voltage selection signal T 1  and the falling of the voltage selection signal T 2 , the control circuit  12  raises the voltage selection signal T 2 , and lowers the voltage selection signal T 3 . In this way, a voltage supplied to the CPU  10 , the control circuit  12  or the like is lowered from the voltage Vdd 1  to the lower voltage Vdd 2 . 
     Subsequently, the control circuit  12  raises the voltage selection signal T 3  and lowers the voltage selection signal T 2  in synchronization with the falling of the control signal G 6 . Accordingly, a voltage supplied to the CPU  10 , the control circuit  12  or the like is increased from the voltage Vdd 2  to the voltage Vdd 1 . 
     With the passage of time t 1  after the rising of the voltage selection signal T 3  and the falling of the voltage selection signal T 2 , the control circuit  12  raises the voltage selection signal T 2 , and lowers the voltage selection signal T 3 . Thus, a voltage supplied to the CPU  10 , the control Circuit  12  or the like is lowered from the voltage Vdd 1  to the voltage Vdd 2 . 
     Then, during the low-speed operation, the control circuit  12  carries out control for the voltage selection signals T 2  and T 3  in synchronization with the rising/falling of the low-speed clock signal G 6  like that described above (step S 4 ). 
     Specified processing in the low-speed operation is finished (step S 5 ), and when an operation is changed from the low-speed operation to the normal operation, as shown in FIG. 7, the CPU  10  raises the switching signal A 1  in synchronization with any rising of the clock signal G 4  based on the program stored in the ROM  7 . In synchronization therewith, the control circuit  12  sets high the level of the oscillator control signal G 1 . Accordingly, the first oscillator  3  starts its operation (step S 6 ), and the high-clock signal C 5  is supplied to the selector  5 . 
     Then, the control circuit  12  lowers the control signal G 3  in synchronization with the rising of the control signal G 6 . Accordingly, the selector  5  selects the high-speed clock signal C 5 , and supplies it as the clock signal G 4  to the CPU  10  (step S 7 ). 
     Subsequently, the normal operation is carried out at a high speed (step S 8 ). 
     As described above, according to the first embodiment, the voltage supplied to the CPU  10 , the control circuit  12  and the like during the low-speed operation becomes a low voltage Vdd 1  when the low-speed clock signal G 6  rises/falls and, then, with the passage of time t 1 , the voltage becomes a lower voltage Vdd 2 . Therefore, a leakage current can be reduced while the circuit operated by the low-speed clock signal G 6  is kept in a stable operating state. 
     It can therefore be understood that even if a fine process is applied to the single chip microprocessor for a high-speed operation, since a channel leakage current can be considerably reduced during the low-speed operation, power consumption during the low-speed operation can be greatly reduced. 
     The first embodiment is for the microcomputer, which needs a high-speed clock signal of, e.g., 20 MHz, and a low-speed clock signal of, e.g., 32 kHz. However, the embodiment can be applied to one, such as a gas meter, a water meter or the like, which needs no high-speed clock signals In this case, an arrangement may be made such that excluding the first oscillator  3  for generating a high-speed clock signal and a device or the like related to its operation, a voltage is supplied for enabling a device provided to, for example, CPU to start its operation in synchronization with rising/falling of the low-speed clock signal, and in the other period, a supplied voltage is reduced to a level for enabling the device to hold its operating state. 
     Next, a second embodiment of the present invention will be described. According to the second embodiment, a clock timer is provided. The second embodiment is designed to stop the supply of power to a circuit other than one necessary for maintaining the operation of the clock timer during the low-speed operation. FIG. 9 is a block diagram showing the structure of a single chip microcomputer according to the second embodiment of the present invention. In the second embodiment shown in FIG. 9, components like those of the first embodiment shown in FIG. 3 are denoted by like reference numerals, and specific explanation thereof will be omitted. 
     In the second embodiment, there is provided a clock timer  21 , which is operated in synchronization with a clock signal G 6  outputted from the second oscillator  4 . To the clock timer  21 , a voltage VDD 2  at a common connection point of the transistors Tr 1  to Tr 3  is supplied. The voltage VDD 2  is also supplied to the RAM  6 , the level-shirt circuit  9  and the selector  5 . 
     In the second embodiment, a transistor Tr 4  is provided, having one end connected to the power supply terminal; and a transistor Tr 5 , having one end connected to the other end of the transistor Tr 4 . The other end of the transistor Tr 5  is grounded. A voltage VDD 1  at a common connection point of the transistors Tr 4  and Tr 5  is supplied to the ROM  7 , the peripheral circuit  8  and the CPU  10 . The transistors Tr 1  to Tr 4  may be all P-channel transistors, whereas the transistor Tr 5  may be an N-channel transistor. 
     In addition to a switching signal A 1 , an operation instruction signal A 2  and a rewriting completion signal A 3  are outputted from the CPU  10  to a control circuit  22 . An operation start signal G 8  is outputted from the control circuit  22  to the clock timer  21 . 
     FIG. 10 is a block diagram showing a structure of the control circuit  22  in the second embodiment. In the control circuit  22  shown in FIG. 10, components like those of the control circuit  12  shown in FIG. 4 are denoted by like reference numerals, and specific explanation thereof will be omitted. 
     A flip-flop FF 21 , FF 22 , FF 23  and FF 24  are provided to the control circuit  22 . The operation instruction signal A 2  is inputted to the D terminal of the flip-flop FF 21 , and the output signal of the inverter IV 2  is inputted to the C terminal of the flip-flop FF 21 . The rewriting completion signal A 3  is inputted to the D terminal of the flip-flop FF 22 , and the output signal of the inverter IV 2  is inputted to the C terminal of the flip-flop FF 22 . The output signal of the flip-flop FF 21  is inputted to the D terminal of the flip-flop FF 23 , and a clock signal G 6  is inputted to the C terminal of the flip-flop FF 23 . The output signal of the flip-flop FF 22  is inputted to the D terminal of the flip-flop FF 24 , and the clock signal G 6  is inputted to the C terminal of the flip-flop FF 24  The output signal of the flip-flop FF 23  is an operation start signal G 8 . 
     The control circuit  22  also includes an inverter IV 22  for inverting the output signal of the flip-flop FF 24 , and a two-input AND gate AND 21  for operating logical AND of the rewriting completion signal A 3  and the output signal of the inverter IV 22 . The control circuit  22  further includes a two-input OR gate OR 21  provided for operating logical OR of a clock timer overflow signal (referred to as an OVF signal, hereinafter) G 7  from the clock timer  21  and a reset signal RST, and outputting its result to the S terminal of the flip-flop FF 12 . The control circuit  22  further includes a two-input OR gate OR 22  provided for operating logical OR of the output signal of the flip-flop FF 7  and the output signal of the AND gate AND 21 , and outputting its result to the R terminal of the flip-flop FF 12 . 
     Furthermore, four flip-flops FF 15  to FF 18  are connected in series between the output terminal of the oscillation stabilizing counter  13  and the OR gate OR 2 . The output signal of the inverter IV 2  is inputted to the C terminal of the flip-flop FF 15 . The clock signal G 6  is inputted to the C terminal of the flip-flop FF 16 . The output signal of the inverter IV 1  is inputted to the C terminal of the flip-flop FF 17 . The clock signal G 5  is inputted to the C terminal of the flip-flop FF 18 . 
     FIG. 11 is a block diagram snowing a structure of the clock timer  21  of the second embodiment. 
     The clock timer  21  includes an n-bit binary counter  23  actuated by the operation start signal G 5  to count the number of changes in the rising of the clock signal G 6 , and an inverter IV 23  for inverting the clock signal G 6 . The clock timer  21  also includes a flip-flop FF 25 , a flip-flop FF 26  and a two-input AND gate AND 22 . The output signal of the n-bit binary counter  23  is inputted to the D terminal of the flip-flop FF 25 , and the output signal of the inverter IV 23  is inputted to the C terminal of the flip-flop FF 25 . The output signal of the flip-flop FF 25  is inputted to the D terminal of the flip-flop FF 26 , and the clock signal G 6  is inputted to the C terminal of the flip-flop FF 26 . Logical AND of the output signal of the flip-flop FF 26  and the output signal of the n-bit binary counter  23  is operated by the two-input AND gate AND 22 . The output signal of the AND gate AND 22  is an OVF signal G 7 . 
     Next, description will be made of the operation of the single chip microcomputer of the second embodiment constructed in the foregoing manner. FIG. 12 is a timing chart showing an operation before/after a high-speed operation is changed to a low-speed operation in the second embodiment; FIG. 13 a timing chart showing an operation during the low-speed operation in the second embodiment; FIG. 14 a timing chart showing an operation before/after the low-speed operation is changed to the high-speed operation in the second embodiment; and FIG. 15 a flow chart showing the operation of the single chip microcomputer according to the second embodiment of the present invention. 
     When the reset signal RST to the CPU  10  and the control circuit  22  is released, as shown in FIG. 12, the single chip microcomputer itself starts its normal operation (step S 11 ). In the normal operation, the level of the oscillator control signal G 1  is high, and the first and second oscillators  3  and  4  are in operating states. The level of the clock selection signal G 3  is low, and the selector  5  selects the high-speed clock signal G 5  and supplies it as the clock signal G 4  to the CPU  10 . On the other hand, although the level of the voltage selection signal T 1  is low, the levels of the voltage selection signals T 2  and T 3  are high, and power supply voltage Vdd is supplied as the voltage VDD 2  to the RAM  6 , the level-shift circuit  9 , the selector  5  and the clock timer  21 . In addition, power supply voltage Vdd is supplied as the voltage VDD 1  to the ROM  7 , the peripheral circuit  8  and the CPU  10 . Accordingly, the normal operation is carried out with a high-speed clock. 
     Subsequently, the CPU  10  sets a clock calendar in the RAM  6  based on the program stored in the ROM  7 , and lowers the operation instruction signal A 2 . Then, the control circuit  22  raises the operation start signal G 8  in synchronization with the next rising of the clock signal G 6 . Accordingly, the clock timer  21  is placed in an ON state (step S 12 ). 
     Then, the CPU  10  lowers the switching signal A 1  based on the program stored in the ROM  7 . Upon receiving this signal, the control circuit  22  raises the clock selection signal G 3  in synchronization with the next falling of the low-speed clock signal G 6 . Accordingly, the selector  5  selects the low-speed clock signal G 6 , and supplies it as the clock signal G 4  to the CPU  10  (step S 13 ). 
     Subsequently, the control circuit  22  counts the high-Speed clock signal G 5  equivalent to two clock, and then lowers the oscillator control signal G 1 . Thus, the operation of the first oscillator  3  is stopped (step S 14 ). The control circuit  22  raises the voltage selection signal T 1  and lowers the voltage selection signal T 2  in synchronization with the next rising of the control signal G 6  after the rising of the clock selection signal G 3  as described above. In this way, the voltage VDD 2  is reduced from the power supply voltage Vdd to the lower voltage Vdd 1 . In addition, the rising of the voltage selection signal T 1  places the N-channel transistor Tr 5  in an ON state, and the voltage VDD is reduced from the power supply voltage Vdd to 0V. Therefore, the operations of the ROM  7 , the peripheral circuit  8  and the CPU  10  are stopped (step S 15 ). 
     The operation of the clock timer  21  has already been started, and thus the n-bit binary counter  23  counts the number of rising times of the clock signal G 6 . 
     Then, with the passage of time t 1  after the rising of the voltage selection signal T 1  and the failing of the voltage selection signal T 2 , the control circuit  22  raises the voltage selection signal T 2 , and lowers the voltage selection signal T 3 . Accordingly, the voltage VDD 2  is reduced from the voltage Vdd 1  to a much lower voltage Vdd 2 . On the other hand, since the voltage selection signal T 1  is kept at a high level, the voltage VDD 1  is kept at 0V. 
     Then, in synchronization with the falling of the control signal G 6 , the control circuit  22  raises the voltage selection signal T 3 , and lowers the voltage selection signal T 2  Thus, the voltage VDD 2  is increased from the voltage Vdd 2  to the voltage Vdd 1 . Then, with the passage of time t 1  after the rising of the voltage selection signal T 3  and the falling of the voltage selection signal T 2 , the control circuit  22  raises the voltage selection signal T 2 , and lowers the voltage selection signal T 3 . In this way, the voltage VDD 2  is reduced from the voltage Vdd 1  to the voltage Vdd 2 . 
     Subsequently, during the low-speed operation, the control circuit  22  carries out control for the voltage selection signals T 2  and T 3  in synchronization with the rising/falling of the low-speed clock signal G 6  like that described above. 
     When overflowing occurs in the n-bit binary counter  23  during the low-speed operation like that described above, as shown in FIG. 13, the OVF signal G 7  is raised. Upon receiving this signal, the control circuit  22  lowers the voltage selection signal T 1 , and holds the voltage selections signals T 2  and T 3  at high levels. As a result, the voltages VDD 1  and VDD 2  are increased to power supply voltages Vdd (steps S 16 , and S 17 ). Then, the CPU  10  resumes its operation, and starts the rewriting of the clock calendar stored in the RAM  6  (step S 18 ). At this time, the counter value of the counter  23  in the clock timer  21  is reset to 0. 
     After the completion of the rewriting of the clock calendar, as shown in FIG. 14, the CPU  10  outputs the rewriting completion signal A 3  to the control circuit  22 . Upon receiving the rewriting completion signal A 3 , the control circuit  22  raises the voltage selection signal T 1  in synchronization with the next falling or the clock signal G 4 , thereby setting the voltage VDD 1  to 0V (step S 20 ). Then, the control circuit  22  resumes control for the voltage selection signal T 2  and T 3 , which is carried out in synchronization with the rising/falling of the low-speed clock signal G 6  like that described above During the low-speed operation, the CPU  10 , the control circuit  22  and the like carries out this operation each time overflowing occurs in the clock timer  21 . 
     Then, specified processing is finished in the low-speed operation, and when an operation is changed from the low-speed operation to the normal operation, after the rewriting of the clock calendar, the CPU  10  raises the switching signal A 1  in synchronization with any rising of the clock signal G 4  based on the program stored in the ROM  7 , while the voltage VDD 1  is kept at the power supply voltage Vdd (step S 19 ). In synchronization therewith, the control circuit  22  raises the oscillator control signal G 1 . Thus, the first oscillator  3  starts its operation (step  521 ), and the high-speed clock signal G 5  is supplied to the selector  5 . 
     Subsequently, the control circuit  22  lowers the control signal G 3  in synchronization with the rising of the control signal G 6 . Accordingly, the selector  5  selects the high-speed clock signal G 5 , and supplies it as the clock signal G 4  to the CPU  10  (step S 22 ). 
     Then, the normal operation is carried out at a high speed (step  523 ). 
     As described above, according to the second embodiment, during the low-speed operation, the supply of voltages to the ROM  7  and the peripheral circuit  8  is completely cut off, and the supply of a voltage to the CPU  10  is carried out only at the tie of rewriting the clock calendar. Thus, compared with the first embodiment, power consumption can be reduced more. 
     In the second embodiment, during the low-speed operation, the voltage VDD 2  is always supplied to the RAM  6 , the clock timer  21 , the second oscillator  4  and the control circuit  22 . However, if an external clock timer is provided to enable an external circuit to carry out non maskable interrupt (NMI) or resetting, then a voltage can be supplied only to the RAM, and the supply of voltages and all the clock signals to the other internal circuits can be stopped. As a result, power consumption can be further reduced. In addition, a portion to receive the supply of a voltage may be limited to one which requires RAM data to be held. Recently, there have been great increases in RAM capacities. However, data to be held even while the other internal circuits are stopped is seldom stored in the entire RAM, and there will be no problems even if the supply of voltages to the other RAM areas is stopped. Therefore, power consumption can be considerably reduced. 
     While there has been described what are at present considered to be preferred embodiments or the invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claims cover all such modifications as fall within the true spirit and scope of the invention.