Abstract:
Phase locked loop calibration system. Apparatus is provided for calibration of a phase-locked loop. The apparatus includes logic to calibrate an integration filter of the phase-locked loop, and logic to calibrate a charge pump current of the phase-locked loop, wherein the integration filter and charge pump current are calibrated to achieve a desired phase-locked loop performance level.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present Application claims the benefit of priority from a co-pending U.S. Provisional Patent Application entitled “Phase Locked Loop Calibration System” having Ser. No. 60/533,524 and filed on Dec. 29, 2003, the disclosure of which is incorporated by reference herein for all purposes. 
    
    
     FIELD 
     The present invention relates generally to the calibration of a phase locked loop, and more particularly, to a system for precisely setting the loop gain, phase margin, and stability associated with a phase-locked loop. 
     BACKGROUND 
     Phase-locked loops (PLL) find widespread use in frequency synthesizers, clock recovery circuits, phase modulators, and frequency demodulators. Generally, a PLL consists of a voltage-controlled oscillator (VCO), counter, phase/frequency detector (P/FD), charge pump (CP), and low pass filter as shown in  FIG. 1 . The PLL uses feedback to track the phase of the input signal and generate a replica signal, usually offset in frequency. 
     The behavior of a phase-locked loop system depends on the parameters associated with each of the comprising circuits. These parameters vary with process and affect the system&#39;s performance—even its stability. It would therefore be advantageous to have a system to precisely set the phase-locked loop&#39;s operating parameters. 
     SUMMARY 
     In one or more embodiments, a PLL calibration system is provided to automatically calibrate the parameters of a phase-locked loop and thereby optimize its performance for a variety of applications. In one or more embodiments, the system operates to precisely calibrate the integration filter and charge pump current of a PLL to achieve a desired PLL transfer function and performance level. For example, the calibration system calibrates the PLL&#39;s integration filter to set the correct Zero/pole locations, and calibrates the charge pump current to compensate for gain characteristics of the PLL&#39;s VCO and/or integration filter. 
     In one embodiment, apparatus is provided for calibration of a phase-locked loop. The apparatus comprises logic to calibrate an integration filter of the phase-locked loop, and logic to calibrate a charge pump current of the phase-locked loop, wherein the integration filter and charge pump current are calibrated to achieve a desired phase-locked loop performance level. 
     In one embodiment, apparatus is provided for calibration of a phase-locked loop. The apparatus comprises means for calibrating an integration filter of the phase-locked loop, and means for calibrating a charge pump current of the phase-locked loop, wherein the integration filter and charge pump current are calibrated to achieve a desired phase-locked loop performance level. 
     In one embodiment, a communication device is provide that comprises apparatus for calibration of a phase-locked loop. The apparatus comprises logic to calibrate an integration filter of the phase-locked loop, and logic to calibrate a charge pump current of the phase-locked loop, wherein the integration filter and charge pump current are calibrated to achieve a desired phase-locked loop performance level. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein 
         FIG. 1  shows a diagram of a typical PLL; 
         FIG. 2  shows a mathematical model of the PLL of  FIG. 2 ; 
         FIG. 3  shows one embodiment of a passive low pass filter or integration filter; 
         FIG. 4  shows plots of the open-loop magnitude and phase response of the offset-PLL of  FIG. 2 ; 
         FIG. 5  shows one embodiment of a calibration circuit used to adjust the zero/pole locations for a PLL&#39;s integration loop filter; 
         FIG. 6  shows one embodiment of an integration loop filter with adjustable resistor that replicates the operation of the calibration circuit of  FIG. 5 ; 
         FIG. 7  shows one embodiment of a calibration circuit used to adjust the loop gain and associated parameters of a PLL; 
         FIG. 8  shows one embodiment of an LC-resonantor voltage-controlled oscillator; 
         FIG. 9  shows one embodiment of an active loop filter for use with a PLL; 
         FIG. 10  shows one embodiment of a calibration circuit used to adjust the zero/pole locations for a PLL&#39;s active loop filter; 
         FIG. 11  shows one embodiment of a calibration circuit used to adjust the loop gain and associated parameters of the PLL with active loop filter; and 
         FIG. 12  shows a communication network that includes various communication devices that include one or more embodiments of a PLL calibration system. 
     
    
    
     DETAILED DESCRIPTION 
     In one or more embodiments, a PLL calibration system is provided to automatically calibrate the parameters of a phase-locked loop. 
       FIG. 2  shows a mathematical model of the PLL of  FIG. 1 . The voltage-controlled oscillator  202  produces an output signal at a frequency set by the control voltage ν ctrl  according to;
 ν out ( t )= A   c  cos(ω free   t+K   vco ∫ν ctrl ( t ) dt ) 
where ω free  is the free-running frequency of the oscillator and K vco  is its associated gain.
 
     The gain K vco  describes the relationship between the excess phase of the carrier Φ out (s) and the control voltage ν ctrl , which can be expressed as 
                   Φ   out     ⁢           ⁢     (   s   )           v   ctrl     ⁢           ⁢     (   s   )         =       K             ⁢   vco       s           
where K vco  is in rads/V. When the phase-locked loop is locked, the phase detector  204  and charge pump circuit  206  generate an output signal i CP (s) that is proportional to the phase difference (Δθ) between the two signals input to the phase detector  204 . The output signal of the charge pump  206  (i CP (s)) can therefore be expressed as;
 
                 i   CP     ⁢           ⁢     (   s   )       =       K   pd     ⁢           ⁢       Δ   ⁢           ⁢   θ   ⁢           ⁢     (   s   )         2   ⁢           ⁢   π               
where K pd  is in A/rads and Δθ is in rads. The output signal i CP (s) is input to an integration filter  208 , which filters it to produce the control voltage ν ctrl .
 
       FIG. 3  shows one embodiment of the integration filter  208 , which comprises resistor R 1  with capacitors C 1  and C 2  that transforms the signal i CP (s) to the control voltage ν ctrl  as follows; 
                 v   ctrl     ⁢           ⁢     (   s   )       =       i   out     ⁢           ⁢     (   s   )     ⁢           ⁢     (           sR   1     ⁢           ⁢     C   1       +   1           s   2     ⁢           ⁢     R   1     ⁢           ⁢     C   1     ⁢           ⁢     C   2       +     s   ⁢           ⁢     (       C   1     +     C   2       )           )             
where a zero (at 1/R 1 C 1 ) has been added to stabilize the second order system and the capacitor C 2  has been included to reduce any ripple on the output voltage.
 
     Combining the above relationships yields the composite open-loop transfer function; 
               GH   ⁢           ⁢     (   s   )       =       K   PD     ⁢           ⁢       K             ⁢   VCO       s     ⁢           ⁢     1   N     ⁢           ⁢     1   s     ⁢           ⁢     (           sR   1     ⁢           ⁢     C   1       +   1           sR   1     ⁢           ⁢     C   1     ⁢           ⁢     C   2       +     C   1     +     C   2         )             
which has two poles at the origin (due to the voltage-controlled oscillator  202  and the integration filter  208 ). This system is referred to as a type II phase-locked loop.
 
       FIG. 4  shows graphs of the open-loop magnitude  402  and phase response  404  of the PLL of  FIG. 2 . The open-loop transfer function GH(s) is used to analyze the stability of the feedback loop. The graphs of its magnitude  402  and phase response  404  indicate the phase margin of the system. Ideally, the phase margin approaches 45°, providing a closed loop response with adequate stability while minimizing acquisition time. 
     The loop gain of the phase-locked loop (that is, the gain of the phase-locked loop near dc) depends on four parameters (I CP , K vco , R 1 , and N) 
               G   loop     =              GH   ⁢           ⁢     (   s   )              s   →     d   ⁢           ⁢   c         =         I   PD     ⁢           ⁢     R   1     ⁢           ⁢     K   VCO       N             
and approximately equals the unity-gain bandwidth of the system. To improve stability, the integration filter&#39;s zero shifts the phase slightly before the system&#39;s unity gain frequency. The closed-loop response of the system is simply;
 
               T   ⁢           ⁢     (   s   )       =         K   PD     ⁢           ⁢     K   VCO     ⁢           ⁢   N   ⁢           ⁢     (         sR   1     ⁢           ⁢     C   1       +   1     )             s   2     ⁢           ⁢     NR   1     ⁢           ⁢     C   1     ⁢           ⁢     C   2       +     s   ⁢           ⁢     (         K   PD     ⁢           ⁢     K   VCO     ⁢           ⁢     R   1     ⁢           ⁢     C   1       +     C   1     +     C   2       )       +       K   PD     ⁢           ⁢     K   VCO                 
which shows the zero and two complex poles. Both the open-loop and closed-loop responses of the phase-locked loop depend on the integration filter components (R 1 , C 1 -C 2 ), the charge pump current I CP , and the gain of the voltage-controlled oscillator, K vco , and the value of the counter in the feedback loop.
 
       FIG. 5  shows one embodiment of a circuit  500  that operates to calibrate the R 1 C 1  product that forms the basis of the integration filter  208  shown in  FIG. 3 . The circuit  500  comprises switches (S 1 -S n ) and a variable resistor R that comprises incremental resistors (ΔR 1 -ΔR n−1 ). The circuit  500  uses the following relationship to govern the calibration; 
               V   c     =       I   C     ⁢           ⁢   Δ   ⁢           ⁢   t           
where I is the charging current, Δt is the charging time, and C is the value of the capacitor C 1 . It assumes the initial voltage on the capacitor is zero, which is forced by switches S c1  and S c2 . The operational amplifier  502 , transistor N 1 , and the variable resistor R establish the charging current;
 
             I   =       V   BG     R           
which is mirrored to the capacitor C by transistors P 1 -P 2 . Note that capacitor C matches capacitor C 1  in the integration filter  208  shown in  FIG. 3 . As a result, the voltage V C  developed across the capacitor is;
 
               V   c     =         V   BG     RC     ⁢   Δ   ⁢           ⁢   t           
and is solely dependent on the RC product if Δt is accurately set.
 
     In one embodiment, a calibration algorithm is provided that starts with resistor R at its minimum value (switch S 1  closed), switch S c1  opened, and switch S c2  closed. A precise clock (such as the reference clock found in most radio systems) closes switch S c1  and toggles open switch S c2  to allow the current I to charge capacitor C. After a set time, the clock toggles switch S c1  open—stopping the charging of capacitor C—and strobes the comparator. If the voltage stored by the capacitor exceeds the bandgap voltage V BG , the output of the comparator  504  transitions positive. This causes the algorithm to open switch S 1  and close switch S 2 , increasing the value of resistor R. 
     The procedure repeats, incrementing the value of R using the switches S n , until the overall value of resistor R (R plus the incremental resistors ΔR n ) causes the comparator output to transition negative. This completes the calibration and sets the RC product. 
     In one or more embodiments, the calibration algorithm is implemented in hardware, software, firmware, or a combination thereof. For example, any suitable processor may execute software to control the inputs and switches, and monitor the outputs of the circuit  500  to perform the calibration algorithm described herein. 
       FIG. 6  shows one embodiment of an integration filter  600  that replicates the operation of the calibration circuit shown in  FIG. 5 . By design, the value of capacitor C 2  matches C 1  (which is possible using integrated circuit technology, making C 2 =αC 1 ) and therefore setting the zero (z) and pole (p) locations to; 
             z   =       1       R   1     ⁢           ⁢     C   1         =     1       V   BG     ⁢           ⁢   Δ   ⁢           ⁢   t                     p   =           C   1     +     C   2           R   1     ⁢           ⁢     C   1     ⁢     C   2         =         (     1   +     1   α       )     ⁢           ⁢     1       R   1     ⁢           ⁢     C   1           =       (     1   +     1   α       )     ⁢           ⁢   z               
Thus, the value of Δt sets the zero and pole frequencies.
 
     The second half of the calibration system provides an algorithm that targets the product I CP R 1 K vco .  FIG. 7  shows one embodiment of a circuit  700  used to determine the voltage-controlled oscillator&#39;s gain (K vco ). The circuit  700  illustrates a portion of a PLL that comprises a charge pump (CP), integration filter  208 , voltage-controlled oscillator (VCO), and gain calibration logic, shown generally at  702 . The algorithm first shifts the frequency of the output signal f vco  up by decreasing N or the reference frequency f ref  since;
 
 f   vco =( N−Δn ) f   ref   =f   vco   −Δf  
 
where Δn is the adjustment in N and Δf is the change in f vco  respectively. This is accomplished by adjusting other portions of the PLL not shown. After some time, the phase-locked loop acquires the new frequency f vco −Δf and the control voltage ν cntrl  settles. For example, in the LC-resonantor oscillator shown in  FIG. 8 , the control voltage ν ctrl  actually needs to increase to shift the oscillation frequency lower. (This is because the oscillation frequency f vco  changes with the varactor&#39;s capacitance C 2a/b , which decreases with lower control voltage ν ctrl —increasing the oscillation frequency.)
 
     Referring again to  FIG. 7 , the current I 1  is then increased until the comparator output  704  transitions negative. This occurs when
 
 V   +   −I   1   R   2 =ν ctrl  
 
and corresponds to the initial value of the control voltage ν ctrl . Next, the frequency of the output signal f vco  is shifted up so that;
 
 f   vco =( N+Δn ) f   ref   =f   vco   +Δf  
 
where the change in frequency 2Δf is sufficient to induce a reasonable change in the control voltage ν ctrl . The phase-locked loop tracks the frequency shift and eventually settles at a lower control voltage ν ctrl . The gain of the voltage-controlled oscillator is accordingly;
 
               K   vco     =       2   ⁢           ⁢   Δ   ⁢           ⁢   f       Δ   ⁢           ⁢     v   ctrl               
where Δν ctrl  is the change in control voltage. And, as a result Δν ctrl  indicates the oscillator&#39;s gain K vco .
 
     The final step in the algorithm increases current I ref  until the comparator output  704  again toggles negative. This corresponds to when;
 
 V   + −( I   1   +I   2 ) R   2 =ν ctrl  and I 2 R 2 =Δν ctrl  
 
and sets
 
     
       
         
           
             
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                 2 
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                 ⁢ 
                 Δ 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 f 
               
               
                 
                   I 
                   2 
                 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   R 
                   2 
                 
               
             
           
         
       
     
     By design, resistor R 2  matches resistor R 1  of the integration filter  208  and the current mirror formed by transistors N 1 -N 3  forces charge pump current I CP  to track current I 2 . This means the loop gain equals; 
               G   loop     =         I   CP     ⁢           ⁢     R   1     ⁢           ⁢       2   ⁢           ⁢   Δ   ⁢           ⁢   f         I   2     ⁢           ⁢     R   2           =     2   ⁢           ⁢   β   ⁢           ⁢   Δ   ⁢           ⁢   f             
where β is the fixed relationship between resistors R 1 -R 2  and currents I CP -I 2 .
 
       FIG. 9  shows one embodiment of an active circuit  900  used to realize the loop filter or integration filter. For example, the circuit  900  is suitable for use as the integration filter  208 . The operational amplifier (op amp) improves the performance of the charge pump circuit by maintaining the voltage seen at its output at or near the voltage V R . 
       FIG. 10  shows a calibration circuit  1000  used to calibrate the RC product of the active integration filter  900  shown in  FIG. 9 . The calibration circuit  1000  is similar to the calibration circuit  500  of  FIG. 5 . It differs slightly to keep the switches at the same potential as resistor R 1  (and its switches) in the active loop filter. This is important since the on resistance of the switches varies with bias voltage. Furthermore, complimentary switches are usually needed to minimize the on resistance of the switches, especially if V R  lies midway between V +  and ground. Otherwise, the calibration algorithm operates as before. 
       FIG. 11  shows one embodiment of a calibration circuit  1100  used to calibrate the loop gain of a phase-locked loop. The circuit  1100  operates in situ (i.e., as in  FIG. 7 ) and comprises the active integration filter  900  shown in  FIG. 9 . The calibration algorithm for constant loop gain also remains unchanged from that described with reference to  FIG. 7 . 
     The accuracy of the calibration algorithm depends on the value of the feedback counter N (not shown in  FIG. 11 ) and varies with different phase-locked loop architectures. To improve precision, the programmable charge pump current I CP  can be adjusted to compensate for changes in the value of N according to; 
               Δ   ⁢           ⁢     I   CP       =       (         f   vco     -     f   cal         f   cal       )     ⁢           ⁢     I   CP             
where f cal  is the frequency where the calibration is performed. This allows the loop gain to remain constant even if the value of the feedback counter changes significantly.
 
       FIG. 12  shows a communication network  1200  that includes various communication devices that include one or more embodiments of a PLL calibration system. The network  1200  includes multiple network servers, a tablet computer, a personal digital assistant (PDA), a cellular telephone, and an email/pager device all communicating over a wireless data network. Each of the devices includes one or more embodiments of a PLL calibration system as described herein. The network  1200  illustrates only some of the devices that may comprise one or more embodiments of a PLL calibration system. However, it should be noted that one or more embodiments of a PLL calibration system are suitable for use in virtually any type of communication device. 
     In one or more embodiments, a PLL calibration system is provided that automatically calibrates the parameters of a phase-locked loop and thereby optimize its performance. Accordingly, while one or more embodiments of a PLL calibration system have been illustrated and described herein, it will be appreciated that various changes can be made to the embodiments without departing from their spirit or essential characteristics. Therefore, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.