Abstract:
This invention relates to a power supply circuit wherein first transistors, resistors, ann sscood rajsitoos itt a polarity opposite to that of said first transistors are series-connected between the power supply side and the output side. In one embodiment, the circuit is provided as a semiconductor integrated circuit wherein first transistor elements, diffusion resistor elements, and second transistor elements with a polarity opposite to that of said first transistor elements are respectively formed on a common semiconductor substrate together with interconnects.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to a power supply circuit and a semiconductor integrated circuit device using it, and particularly to a constant-current supply circuit and a semiconductor integrated circuit device using it. 
     BACKGROUND OF THE INVENTION 
     In the past, for a high voltage withstanding display driver (a circuit in which many current outputs are required), a constant-current supply with a circuit structure as shown in FIG. 5 may be considered. As shown in the figure, on the side of a power supply 3 (V EE ), the respective emitters of (high potential withstanding) PNP switching transistors Q 1 , Q 2 , Q 3  . . . and Q 34  are connected in common, and the bases of the switching transistors Q 1 , Q 2 , Q 3  . . . and Q 34  are respectively connected to switches 51, 52, 53 . . . and 84. (This circuit diagram shows a state in which the switches are ON, i.e., the state that the base voltage is OV, for example). Collectors of the switching transistors Q 1 , Q 2 , Q 3  . . . and Q 34  are respectively connected through resistors R 1 , R 2 , R 3  . . . and R 34  to respective output terminals T 1 , T 2 , T 3  . . . and T.sub. 34. Each of Z 1 , Z 2 , Z 3  . . . and Z 34  in the figure represents a load impedance (e.g., picture element of plasma display), and 5 (V CC ) indicates a negative power supply. 
     Referring to a circuit unit 101 (also to 102, 103 . . . and 134) which are the parts shown by a broken line in this circuit diagram, the resistance value of the resistor R 1  is increased to increase the voltage drop due to the resistor R 1  (assuming that the current flowing R 1  is I 0 , R 1 .I 0 ), thereby controlling a change in the power supply 3 and an output current change due to a change in the load impedance Z 1 . That is, with a change in the power supply 3 as ΔV EE , a change in the output voltage V CC  due to a change in the load impedance Z 1  as ΔV CC , and a change in the load impedance Z 1  as ΔZ 1 , we obtain ##EQU1## (where R 1  &gt;&gt;Z 1  +ΔZ 1  ; I O  R 1  &gt;&gt;ΔV EE  ; and I O  R 1  &gt;&gt;ΔV CC ). Therefore, with R 1  as being large (I O  R 1  &gt;&gt;ΔV EE , I O  R 1  &gt;&gt;ΔV CC ), I O  can be almost constant. 
     However, in a circuit which requires many current outputs (a power supply circuit having 34 current outputs consisting of circuits 101, 102, 103 . . . and 134 shown by broken lines in FIG. 5), since there are many resistors like R 1  (e.g., 34 resistors R 1 , R 2 , R 3  . . . and R 34 ) with large resistance values described above, the voltage drop due to the resistance becomes large, wasting power. There is a problem that this amounts for a large portion of power consumption in the above entire display driver. There is also a problem that it is difficult to form many resistors with large resistance values in a semiconductor IC (integrated circuit) with high precision (without dispersion in the resistance value), (that is, it is difficult to output a constant-current). 
     An object of the invention is to provide a power supply circuit and a semiconductor integrated circuit device using it wherein power consumption is reduced and dispersion of output current is small. 
     SUMMARY OF THE INVENTION 
     This invention relates to a power supply circuit wherein first transistors (e.g., NPN transistors Q 35 , Q 36 , Q 37  . . . and Q 68 , described later), resistors, and second transistors with a polarity opposite to that of said first transistors (e.g., PNP transistors Q 1 , Q 2 , Q 3  . . . and Q 34  described later) are series-connected in this order between the power supply side and the output side. 
     This invention provides a semiconductor integrated device for a power supply circuit wherein first transistor elements, diffusion resistor elements, and second transistor elements with a polarity opposite to that of said first transistor elements are respectively formed on a common semiconductor substrate, and wherein interconnecting lines for connecting said first transistor element, said diffusion resistor elements, and said second transistor elements in series are formed on said semiconductor substrate. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an equivalent circuit diagram of a constant-current supply circuit in accordance with a first embodiment of the invention; 
     FIG. 2 is a cross-sectional view showing a device structure of FIG. 1, (a cross-sectional view being taken on the plane of lines II--II of FIG. 3 which will be described later); 
     FIG. 3 is a plan view of FIG. 2; 
     FIG. 4 is an equivalent circuit diagram showing another embodiment of the invention; and 
     FIG. 5 is an equivalent circuit diagram of a constant-current supply circuit regarded as prior art. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The embodiments of the invention will be now described. 
     FIGS. 1-3 show a first embodiment of the invention. 
     As shown in FIG. 1, a power supply circuit in accordance with this embodiment comprises circuit units 201, 202, 203 . . . and 234 which are shown by broken lines, and has 34 current outputs. A power supply 1 (V 1  : 5V, for example) is connected with respective collectors of NPN bipolar transistors Q 35 , Q 36 , Q 37  . . . and Q 68 , with emitters of the transistors Q 35 , Q 36 , Q 37  . . . and Q 68  respectively connected through resistors R 35 , R 36 , R 37  . . . and R 68  (e.g., each being of approximately 4.3 Kohm) to emitters of PNP bipolar transistors Q 1 , Q 2 , Q 3  . . . and Q 34  (which are similar transistors to those in the prior art example in FIG. 5). 
     Collectors of the transistors Q 1 , Q 2 , Q 3  . . . and Q 34  are respectively connected to output terminals T 41  -T 74 . Each of these output terminals is connected to a picture element of a plasma display (not shown: corresponding to Z 1  -Z 34  in FIG. 5). Bases of the PNP transistors Q 35 , Q 36 , Q 37  . . . and Q 68  and of the PNP transistors Q 1 , Q 2 , Q 3  . . . Q 34  are respectively connected in common to a power supply 2 (V 2  : +2.7 V, for example) and a power supply 4 (V 4 ) or OV (earth). I 1 , I 2 , I 3  . . . and I 34  (e.g., each being of 250 uA) represent output currents. 
     In the structure as described above, the circuit 201 indicated by a broken line will be now described (other circuits 202, 203 . . . and 234 can be also described in like manner). 
     Considering the case that the collector current I C35  (not shown) of the NPN transistor Q 35  will be increased by the change of the power supply 1 (V 1 ): 
     (1) When the collector current I C35  is increased. I E35  is increased according to the relative equation of I E35  =I C35  +I B35 , (where I E35  represents the emitter current and is not shown); 
     (2) When I E35  is increased, the voltage on both ends of (the voltage across) the resistor R 35  is increased; 
     (3) When the voltage on both ends of resistor R 35  is increased, the base-emitter voltage V BE35  and further the base-emitter voltage V BE1  of the PNP transistor Q 1  become smaller; and 
     (4) When the voltage V BE35  and further the base-emitter voltage V BE1  of the PNP transistor Q 1  become smaller, the collector current I C35  also becomes smaller. 
     Therefore, when a change in the power supply 1 (V 1 ) causes the collector current I C35  of the transistor Q 35  to increase, the increase will be restrained. Conversely, when a change in the power supply 1 (V 1 ) causes the collector current I C35  of the transistor Q 35  to decrease, it can be described by the reversed operation of the above (1)-(4), and the decreased of the collector current I C35  is restrained. Since beta, grounded-emitter current amplification factor, of the NPN transistor Q 35  is high, more than 100, the small current output from the power supply 2 (V 2 ) can be sufficient, and many NPN transistors can be connected. 
     Next, considering the case that a change in the load impedance on the output side (not shown in FIG. 1) increases the collector current I Cl  of the PNP transistor Q 1  (i.e., the output current I 1 ): 
     (1) When the collector current I Cl  is increased, the emitter current I E1  is increased; 
     (2) When the emitter current I E1  is increased, the voltage of both ends of the resistor R 35  becomes larger; 
     (3) When the voltage of both ends of the resistor R 35  becomes larger, the base-emitter voltage V BE1  and further the base-emitter voltage V BE35  of the NPN transistor Q 35  become smaller; 
     (4) When the base-emitter voltage V BE1  and further the base-emitter voltage V BE35  of the NPN transistor Q 35  become smaller, the collector current I Cl  also becomes smaller. (The collector current I C1 , the emitter current I E1 , and the base current I B1  are not shown.) 
     Therefore, when a change in the load impedance on the output side causes the collector current I Cl  (the output current I 1 ) of the transistor Q 1  to increase, the increase will be restrained. Conversely, when a change in the load impedance on the output side causes the collector current I Cl  of the transistor Q 1  to decrease, it can be described by the reversed operation of the above (1)-(4), and the decrease of the collector current I Cl  (the output current I 1 ) is restrained. 
     In addition to the above, since the NPN transistor Q 35  and the PNP transistor Q 1  are reversely biased between their respective collectors and bases, changes in the respective collector currents of the transistor Q 35  and the transistor Q 1  due to changes in the power supply 1 (V 1 ) and in the load impedance can be restrained, (i.e., this means that the input impedance of respective collectors of the NPN transistor Q 35  and the PNP transistor Q 1  is very large). 
     Assuming that the transistor Q 1  and the transistor Q 35  are under the condition that they operate in their saturation region, the current I 35  flowing through the transistor R 35  is determined by: ##EQU2## (where, with the transistor Q 1  as grounded-base, the effect of dispersion of h FE  can be small; and with grounded-base current amplification factor of Q 1  as alpha, the output current I 1  is I 1  =alpha I 35 ). Therefore, the resistor R 35  produces the current I 35  by the voltage between the power supply 2 (V 2 ) and the power supply 4 (V 4 ) (i.e., it corresponds to the numerator of the above equation). 
     Since the resistor R 35  has a temperature coefficient of resistance value opposite to that of V BE35  and V BE1 , the current change according to the temperature is small (that is, the temperature coefficient of the base-emitter voltages V BE35  and V BE1  of the above transistor Q 35  and transistor Q 1  are respectively negative, and therefore, in the equation determining the above I 35 , since the signs of the temperature coefficients of the denominator and the numerator are the same, the current change becomes small). 
     As described above, with the circuit of the embodiment, the NPN transistor Q 35  and the resistor R 35  can restrain the change in the collector current of transistor Q 35  due to the change in the power supply 1 (V 1 ), and further the resistor R 35  can restrain the change in the current (which flows across the resistor R 35 ) due to the change in the power supply 2 (V 2 ) and the power supply 4 (V 4 ). The PNP transistor Q 1  and the resistor R 35  can restrain the change in the collector current (i.e., the output current I 1 ) of the transistor Q 1  due to the change in the load impedance on the output side, so that a certain constant current (i.e., I 1  =I 2  =I 3  =. . . and I 34 ) can be always supplied on the output side. Since the resistor with high resistance value is not required, the increase in the power consumption due to the voltage drop of the resistor can be limited to a small amount. 
     In FIGS. 2 and 3, the structure of the device in accordance with the embodiment will be described. 
     An N -   type epitaxial layer 8 is formed above one main face of a P type silicon substrate 5 with an N +   type buried layer 6 in between; and an N +   type diffusion region 15 and a P type diffusion region 11 are formed in the N -   type epitaxial layer 8; and an N +   type diffusion region 16 is formed in the P type diffusion region, respectively constituting a collector region, a base region, and an emitter region, to provide an NPN bipolar transistor Q 35 . 
     Similarly, a P type diffusion region 12 is formed to provide a diffusion resistor R 35  in the epitaxial layer 8 which is formed above the one main face of the P type silicon substrate 5 with the N +   type buried layer 6 in between. 
     An N +   type diffusion region 18, a P type diffusion region 13 and a P type diffusion region 14 are provided in the N -   type epitaxial layer 8, which is provided above the one main surface of the P type silicon substrate 5 with the N +   type buried layer 6 in between. The regions 18, 13, and 14 are respectively form the base region, the collector regions, and the emitter region, to form a PNP bipolar transistor Q 1 . 
     For the reference numerals shown in the figure, 7 represents a P type isolation region, 17 represents an N +   type diffusion region, 19 represents a contact hold, 21-28 respectively represent interconnecting lines of aluminum and so on formed on the semiconductor substrate, 31-34 represent electrodes, 35 represents insulating layer, 8 represents a base electrode, C represents a collector electrode, and E represents an emitter electrode. 
     Since by reversely biasing the PN junction of the NPN transistor, the diffusion resistor (the P type diffusion region 12) is isolated, the N -   type epitaxial layer 8 is connected to the highest potential (the power supply V 1 ) with the interconnecting line 23. The P type silicon substrate 5 is connected to the lowest potential (i.e., the P type region 7) with the interconnecting line 28. 
     As described above, with the device of the embodiment, the NPN type bipolar transistor, the diffusion resistor and the PNP type bipolar transistor are respectively formed on the common semiconductor substrate, series-connected so that many similar NPN type bipolar transistors, many similar diffusion resistors, and many similar PNP type bipolar transistors can be closely arranged. Therefore, voltage between the base and emitter and amplification factors of current of each transistor and the dispersion of the resistance value of each diffusion resistor can be small, and the dispersion of current of each output can be small (i.e., I 1  ≈I 2  ≈I 3  =. . . and=I 34 ). Especially, h FE  of the PNP transistor is about 10-50, as compared to that of the NPN transistor, so that the effect of I B  can not be ignored because it easily cause the dispersion, but when each PNP transistor is closely arranged in the same chip as in the device of the embodiment, the dispersion of I C  is small. 
     FIG. 4 shows another embodiment, wherein a MOS transistor for turning the output current ON and OFF is connected to the above embodiment of FIG. 1. 
     Drains (or sources) of the P-channel type MOS transistors S 35  -S 68  and the substrate (a back gate) are respectively connected to the power supply 2 (V 2 ), and their gates are respectively connected to control terminals T 81  -T 114 . The remaining sources (or drains) of transistors S 35 , S 36 , S 37  . . . S 68  are respectively connected to the bases of the NPN bipolar transistors Q 35 , Q 36 , Q 37  . . . and Q 68 . 
     Drain (or sources) of the N-channel transistors S 1  -S 34  and the substrate (a back gate) are respectively connected to the power supply 4 (and further to the PNP bipolar transistors Q 1 , Q 2 , Q 3  . . . and Q 4 ), and their gates are respectively connected to the control terminals T 81 , T 82 , T 83  . . . and T 114 . The remaining sources (or drains) of transistors S 1 , S 2 , S 3  . . . and S 4  are respectively connected to the emitters of the PNP bipolar transistors Q 1  -Q 34 . The rest of the structure is the same as in the embodiment in FIG. 1. 
     In the structure described above, the operation of a circuit 301 shown by a broken line will be described (and as for the other circuits 302, 303 . . . and 304, they may be described in like manner). 
     When the voltage V 4  which equals that of the power supply 4 is applied to the control terminals T 81 , the P-channel type MOS transistor S 35  is on to apply the voltage V 2  to the base of the NPN bipolar transistor Q 35  and to turn the transistor Q 35  on. The N-channel type MOS transistor S 1  is off to apply a voltage to the emitter of the PNP bipolar transistor Q 1  through the base and emitter of the transistor Q 35  and the resistor R 35  so as to forwardly bias between the base and emitter of the transistor Q 1 , and to turn the transistor Q 1  on. Therefore, the predetermined current will flow from the output terminal T 41 . 
     When the voltage V 1  which equals to that of the power supply 1 is applied to the control terminal T 81 , the P-channel type MOS transistor S 35  is off, so that the voltage V 2  is not applied to the base of the NPN bipolar transistor Q 35 , to be turned off. The N-channel type MOS transistor S 1  is on, so that the potential between the emitter and base of the bipolar transistor Q 1  is almost the same, the transistor Q 1  being off. Therefore, no current will flow from the output terminal T 41 . 
     While the embodiment of the invention has been described, the above embodiments can be further modified according to the technical thought of the invention. 
     For example, while in the embodiments described above, the NPN type transistor, the resistor and the PNP type transistor are series-connected between the power supply side and the output side in this order, the connection order between the NPN type transistor and the PNP type transistor may be reversed depending on the polarity of the power supply and so on. 
     MOS transistors can be used as transistors, and appropriate structures, such as MOS transistors can also be used as resistors. The conductivity type of each semiconductor region may be changed. The power supply circuit of the invention can be applied for the use other than described above. 
     EFFECTS OF THE INVENTION 
     In the invention, as described above, the first transistor, the resistor, and the second transistor having the polarity opposite to that of the above first transistor, are series-connected in this order between the power supply side and the output side, so that constant current with small power consumption can be supplied without providing the resistor with the high resistance value in the output side. The first transistor element, the diffusion resistor element, and the second transistor element having the polarity opposite to that of the above first transistor element are respectively formed on the common semiconductor substrate, so that the dispersion of the transistor elements and diffusion resistor elements can be small. Therefore, a semiconductor integrated circuit device for a power supply circuit with the small dispersion of the output current can be provided.