Abstract:
Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.

Description:
BACKGROUND 
       [0001]    Technical Field 
         [0002]    The present invention relates to semiconductor device fabrication and, more particularly, to merged fins in the source and drain regions of fin-based field effect transistors. 
         [0003]    Description of the Related Art 
         [0004]    When forming replacement metal gate fin field effect transistors (FinFETs), the portions of the fins in the source and drain regions are often merged to form a single conductive terminal. A gate spacer is formed, protecting the fins in the area under the gate, and the fins outside the gate spacer are epitaxially grown until neighboring fins come into contact with one another. 
         [0005]    However, because the fins display both &lt;110&gt; and &lt;100&gt; crystalline surfaces, simple epitaxial growth of the existing fins may cause defects, particularly in growth from &lt;110&gt; surfaces. Furthermore, uncontrolled epitaxial growth is effective at partially merging fins, but it can be difficult to control and suppress that merge in desired locations. 
       SUMMARY 
       [0006]    A semiconductor device includes multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure. 
         [0007]    A semiconductor device includes multiple fins formed in trenches in an insulator layer. Each of the fins has a uniform crystal orientation and includes an etched seed layer and an in situ doped, epitaxially grown fin extension in a source and drain region that extends vertically and laterally beyond the trench. The fin extensions of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure. 
         [0008]    A semiconductor device includes an insulator layer formed on a substrate. Multiple fins are formed in trenches in the insulator layer. Each of the fins has a uniform crystal orientation and includes an etched seed layer and an in situ doped, epitaxially grown fin extension in a source and drain region that extends vertically and laterally beyond the trench. The fin extensions of the respective fins are separate from one another. A gate structure is formed over the plurality of fins between the source and drain regions. The insulator layer rises to a height on the sidewall of the gate structure that is about a same height as portions of the plurality of fins underneath the gate structure. 
         [0009]    These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0010]    The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein: 
           [0011]      FIG. 1  is a cross-sectional view of a step in forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0012]      FIG. 2  is a cross-sectional view of a step in forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0013]      FIG. 3  is a top-down view of a step in forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0014]      FIG. 4  is a cross-sectional view of a step in forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0015]      FIG. 5  is a cross-sectional view of a step in forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0016]      FIG. 6  is a cross-sectional view of a step in forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0017]      FIG. 7  is a cross-sectional view of a step in an alternative embodiment of forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0018]      FIG. 8  is a cross-sectional view of a step in an alternative embodiment of forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0019]      FIG. 9  is a cross-sectional view of a step in an alternative embodiment of forming field effect transistors having non-merged fin extensions in accordance with the present principles; 
           [0020]      FIG. 10  is a block/flow diagram of a method for forming non-merged fin extensions in accordance with the present principles; and 
           [0021]      FIG. 11  is a block/flow diagram of an alternative embodiment of a method for forming non-merged fin extensions in accordance with the present principles. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0022]    Embodiments of the present principles provide the merging of fins in metal oxide semiconductors field effect transistors (MOSFETs) by surrounding the fins with a dielectric fill and recessing the fins below the level of the surrounding dielectric. This leaves only the top surface of the fins exposed such that subsequent epitaxial grown occurs on only the &lt;100&gt; crystal surface. When the growth extends beyond the surface of the dielectric fill, growth continues laterally as well as vertically, allowing the fins to expand without introducing the defects that commonly occur in &lt;110&gt; growth. 
         [0023]    Merged fins are often used to decrease the spreading resistance experienced by charged carriers when traveling from the end of a channel to the contact. Providing a larger volume of highly doped semiconductor lowers the resistance in comparison to simple fins. Merging the fins by epitaxial growth, however, induces higher parasitic capacitance coupling from the gate to the material between the fins. This parasitic capacitance can reduce the performance of the device. Embodiments of the present invention provide fin extensions that increase the volume of the contacts without actually merging the fins, thereby providing the benefits of merged fins without triggering the increase in parasitic capacitance coupling. 
         [0024]    It is to be understood that the present invention will be described in terms of a given illustrative architecture having a wafer; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention. 
         [0025]    It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
         [0026]    A design for an integrated circuit chip may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed. 
         [0027]    Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
         [0028]    Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment. 
         [0029]    It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed. 
         [0030]    Referring now to the drawings in which like numerals represent the same or similar elements and initially to  FIG. 1 , a cutaway view of a step in forming non-merged source/drain regions is shown. In this step, semiconductor fins  106  are formed on an insulator layer  104  above a bulk substrate layer  102 . Although the present embodiments will be disclosed in the context of a semiconductor-on-insulator substrate, it should be understood that a bulk substrate embodiment is also contemplated. The substrate layer  102  may include, for example, a semiconductor such as silicon or any other appropriate substrate material. The insulator layer  104  may be formed from a buried oxide such as, e.g., silicon dioxide. The semiconductor fins  106  may be formed from silicon or from any other appropriate semiconductor such as silicon germanium. The fins  106  may furthermore be doped with, e.g., phosphorus or any other appropriate dopant. 
         [0031]    Referring now to  FIG. 2 , a cutaway view of a step in forming non-merged source/drain regions is shown. A dummy gate  204  is formed over the fins  106  and may be formed from, for example, polysilicon. A spacer  206  is formed around the dummy  204  gate on all sides. The spacer  206  may be formed in parts be, for example forming a hardmask cap over the dummy gate  204  and then forming hardmask sidewalls around the dummy gate  204 . The spacer  206  may be formed from, e.g., silicon nitride or any other appropriate hardmask material and may have any suitable thickness. The spacer  206  serves to protect the dummy gate  204  and portions of the underling fins  106  from subsequent etches and growth processes. 
         [0032]    Referring now to  FIG. 3 , a top-down view of the step of  FIG. 2  is shown. The fins  106  extend beyond the edges of the gate  204  and spacer  206  into source and drain regions  302 . The regions of fins  106  beneath the gate  204  and spacer  206  are protected, while the source and drain regions  302  remain exposed. 
         [0033]    Referring now to  FIG. 4 , a cutaway view of a step in forming non-merged source/drain regions is shown. This view is a cutaway of a source/drain region  302 , outside of the gate  204  and spacer  206 . An insulator layer  402  is deposited between and around the fins  106 , leaving the top surface of the fins  106  exposed. The insulator layer  402  may be formed with a flowable chemical vapor deposition process that deposits, for example, silicon dioxide. The deposition may result in the insulator layer  402  being above the tops of fins  106 . In this case, the insulator layer  402  may be polished in a chemical mechanical planarization step and then etched down to the level of the fins  106 . 
         [0034]    As an alternative to chemical mechanical planarization, which might accidentally polish away the gate  204 , an etch of the insulator  402  may be performed instead. By controlling etch chemistry, the insulator  402  may be preferentially etched compared to the fins  106 . 
         [0035]    Referring now to  FIG. 5 , a cutaway view of a step in forming non-merged source/drain regions is shown. The fins  106  in the source/drain regions  302  are etched down below the level of the insulator layer  402 . This etch may be performed using any appropriate etch, including an isotropic etch, such as a wet chemical etch, or an anisotropic etch, such as a reactive ion etch. The etched fins  502  are brought down to a small thickness. For example, the etched fins may be reduced to a thickness of about 5 nm. 
         [0036]    Referring now to  FIG. 6 , a cutaway view of a step in forming non-merged source/drain regions is shown. Fin extensions  602  are epitaxially grown from the etched fins  502 . When the growth rises above the level of the insulator layer  402 , it naturally begins to expand laterally as well as vertically, maintaining the &lt;100&gt; crystal configuration of the etched fins&#39; top surfaces. In this figure, the fins are not merged. In contrast to conventional epitaxial growth, where growth from the &lt;110&gt; and &lt;100&gt; surfaces might interfere and cause uncertainty as to when and where the fins will merge, embodiments of the present principles provide the ability to predictably control the merging of the fins if desired. It should be recognized that, although the present embodiments provide for growth from the &lt;100&gt; surfaces of the fins  106 , any suitable crystal orientation may be used instead. 
         [0037]    As shown in the figure, the fin extensions  602  will take on a “mushroom” shape that expands outward. The uniform crystal growth provides expansion of the fin extensions  602  at a predictable rate. This allows for accurate determinations to be made regarding the amount of time to perform the growth, such that the fin extensions  602  may be grown as large as possible without contacting one another. The same principles may be employed to produce fin extensions  602  having any desired size, including merging the fins if that is appropriate to a given application. 
         [0038]    When a crystal is epitaxially grown, the crystal orientation of a seed crystal determines the crystal orientation of the grown material. This step can be performed using any appropriate form of crystal epitaxy including the use of gaseous and/or liquid precursors. It should be noted that the fin extensions  602  may be formed from the same semiconductor material as fins  106  or may be formed from another semiconductor having a compatible crystalline structure. Furthermore, the fin extensions  602  may be in situ doped with, e.g., boron or phosphorus. For example, if a gaseous epitaxy process is used, dopants may be added to the source gas in a concentration appropriate to the desired dopant concentration in the fin extensions  602 . 
         [0039]    Referring now to  FIG. 7 , a cutaway view of a step in forming an alternative embodiment of non-merged source/drain regions is shown. Rather than forming fins  706  on top of insulator layer  704 , trenches are formed in the insulator layer  704  and the fins are formed directly on the substrate  702 . The trenches in insulator layer  704  may be formed by any appropriate etch process. 
         [0040]    A gate  204  and spacer  206  may be formed over the fins  706  in the manner described above with respect to  FIGS. 2 and 3 . The spacer  206  leaves part of the fins  706  on either side uncovered, creating source and drain regions  302  as shown above. 
         [0041]    Referring now to  FIG. 8 , a cutaway view of a step in forming an alternative embodiment of non-merged source/drain regions is shown. The fins  802  are etched down below the level of the insulator layer  704 . This etch may be performed using any appropriate etch, including an isotropic etch, such as a wet chemical etch, or an anisotropic etch, such as a reactive ion etch. The etched fins  802  are brought down to a small thickness. For example, the etched fins may be reduced to a thickness of about 5 nm. 
         [0042]    Referring now to  FIG. 9 , a cutaway view of a step in forming an alternative embodiment of non-merged source/drain regions is shown. Fin extensions  902  are epitaxially grown from the etched fins  802 . When the growth rises above the level of the insulator layer  704 , it naturally begins to expand laterally as well as vertically, maintaining the &lt;100&gt; crystal configuration of the etched fins&#39; top surfaces. In this figure, the fins are not merged. In contrast to conventional epitaxial growth, where growth from the &lt;110&gt; and &lt;100&gt; surfaces might interfere and cause uncertainty as to when and where the fins will merge, embodiments of the present principles provide the ability to predictably control the merging of the fins. It should be noted that the fin extensions  902  may be formed from the same semiconductor material as fins  706  or may be formed from another semiconductor having a compatible crystalline structure. Furthermore, the fin extensions  902  may be in situ doped with, e.g., boron or phosphorus. 
         [0043]    Referring now to  FIG. 10 , a method for forming non-merged source/drain regions is shown. Block  1002  forms fins  106  on a substrate. In the present embodiments the substrate is shown as having an insulator layer  104  on a bulk semiconductor layer  102 , but the present principles may also be embodied on a bulk semiconductor substrate. Block  1004  forms a dummy gate  204  over the fins  106  including a spacer  206 . The dummy gate  204  and spacer  206  cover only a middle portion of the fins  106 , leaving the source and drain regions  302  exposed. 
         [0044]    Block  1006  deposits an insulator layer  402  around the fins  106  using, for example, a flowable chemical vapor deposition process. Block  1006  may also include a chemical mechanical planarization process to expose the top of the fins  106 . Block  1108  performs an etch of the fin  106  down below the surface level of the insulator layer  402 . This etch may be performed using any appropriate etch, including an isotropic etch, such as a wet chemical etch, or an anisotropic etch, such as a reactive ion etch. The etched fins  502  are brought down to a small thickness. For example, the etched fins  502  may be reduced to a thickness of about 5 nm. Block  1010  then forms fin extensions  602  by epitaxially growing from the top surfaces of the etched fins  502 . 
         [0045]    Referring now to  FIG. 11 , a method for forming non-merged source/drain regions is shown. Block  1102  forms trenches in an insulator layer  104  using any appropriate etching process. Block  1104  forms fins  706  in the trenches. In the present embodiments the substrate is shown as having an insulator layer  704  on a bulk semiconductor layer  702 . Block  1106  forms a dummy gate  204  over the fins  706  including a spacer  206 . The dummy gate  204  and spacer  206  cover only a middle portion of the fins  706 , leaving the source and drain regions  302  exposed. 
         [0046]    Block  1108  performs an etch of the fin  106  down below the surface level of the insulator layer  704 . This etch may be performed using any appropriate etch, including an isotropic etch, such as a wet chemical etch, or an anisotropic etch, such as a reactive ion etch. The etched fins  802  are brought down to a small thickness. For example, the etched fins  802  may be reduced to a thickness of about 5 nm. Block  1110  then forms fin extensions  902  by epitaxially growing from the top surfaces of the etched fins  802 . 
         [0047]    Having described preferred embodiments of non-merged epitaxially grown MOSFET devices and methods of forming the same (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.