Abstract:
A digital signal processing apparatus is provided for identifying the octave, note and cent of a musical sound. The apparatus includes a transducer for converting the musical sound into an electrical signal, a digital detection unit, receiving the electrical signal from the transducer, for determining the octave, note and cent of the material sound by detecting a fundamental frequency of the electrical signal; and a display unit, responsive to the detection unit, for displaying the note as an alphanumeric character and the cent as a positive or negative decimal integral number from -49 to +50 with zero cents representing perfect concert pitch.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an apparatus for determining the pitch of notes and indicating a standard pitch reference in the manufacture and tuning of musical instruments and a display for indicating the accuracy relative to perfect pitch of notes generated by musical instruments. 
     2. Background Art 
     Microprocessor-based pitch analyzers and tuning aids have attempted to make the art of instrument tuning a simple endeavor, but unfortunately for various reasons have not demonstrated their usefulness to musicians as measured by the overwhelming market share currently held by analog and strobe tuners. 
     Generally, analog tuners contain a phase locked loop set to concert pitch of the desired note to be tuned. Upon the application of a tone or signal, an error voltage is produced by the voltage-controlled-oscillator in the phase locked loop which drives a meter movement indicating the pitch error. Strobe tuners contain a stepper motor that spins an attached marked disc at a predetermined speed, so that when a tone or signal is applied, neon lights are cycled on and off at the frequency of the applied signal. The lights visually appear to cause the markings on the spinning disc to rotate left if the applied signal is flat and to rotate right if the applied signal is sharp, or to be stationary if concert pitch is applied. 
     These devices have shortcomings in that the user/operator is required to have prior knowledge of the note to be tuned, with the user/operator presetting a selector switch to the desired note to be tuned. Another shortcoming of these devices is the visual presentation of the pitch error. A strobe tuner will only indicate that an applied tone or signal is either flat, sharp, or exactly concert pitch. This makes relative measurements between instruments difficult if not impossible. The analog tuner meter movement is only limited to accuracy around the midpoint of the meter movement and determining pitch error accuracy to less than four one hundredths of a semitone is impossible, thus making relative measurements between instruments very difficult. Additionally, the lack of input tone or signal filtering can render both of these devices useless when the applied tone or signal contains high amplitude odd harmonics such as those issued by a trombone which contains high third and fifth order harmonics that are higher in amplitude than that of the fundamental. The fundamental and the associated harmonics have an additive effect when developed into an electronic signal. When the odd harmonics of the applied tone or signal possess amplitudes higher than the fundamental, any tuning device without proper filtering will be deceived into perceiving that the applied tone or signal is either a third or a fifth of the applied pitch above the fundamental. 
     Microprocessor-based tuners have addressed some of the aforementioned issues quite successfully. U.S. Pat. No. 4,429,609 to Warrender, U.S. Pat. No. 4,523,506 to Holliman, and U.S. Pat. No. 4,434,697 to Roses describe methods for determining the octave and the note of an unknown applied tone or signal without user/operator intervention. Additionally, all three devices support some sort of input filtering, but all three of these types of microprocessor-based tuning aids suffer from a combination of flaws that can individually or collectively cause a very serious problem relating to the readability of the pitch error indication that has kept these tuners from becoming &#34;the state-of-the-art&#34; for instrument tuning. 
     A. INPUT SIGNAL DIGITALIZATION 
     Most digitalization techniques of the applied tone or signal use the zero-crossing method which compares an amplified substantially sine wave input signal that varies above and below a zero reference point. A voltage comparator circuit has one of its inputs connected to the varying input signal while its other input is connected directly to the zero reference point. Whenever the applied tone or signal is above the zero reference point, the voltage comparator output will be &#34;high&#34; or a logical &#34;1.&#34; Whenever the applied tone or signal is below the zero reference point, the voltage comparator will be &#34;low&#34; or a logical &#34;0.&#34; When a continuous substantially sine wave input is applied to the voltage comparator, a square wave output will result which is basically a digital stream of a logical &#34;1&#34; followed by a logical &#34;0&#34; continuously through time. Microprocessor tuners use these bit streams as the basis for determining the octave, the note, and the pitch error by using these pulses to control very fast digital circuits connected to a crystal time base. Extreme care in the design of this circuitry is of the utmost importance since any inaccuracies will have adverse implications in the reliability and the readability of the displayed output. 
     U.S. Pat. No. 4,429,609 to Warrender describes a digitalization method using the zero-crossing technique which relies on the voltage comparator to be presented a signal from an operational amplifier with extremely high gain referenced to 1.2 volts as the zero reference point at the voltage comparator. The voltage comparator circuitry contains a hysteresis feedback path from the output to the input to modify the switching points of the output of the voltage comparator with respect to the zero reference point. There are many problems associated with the method of input signal digitalization which need to be realized for proper design of circuitry interfacing to high speed digital logic capable of indicating pitch error on a digital numeric display. 
     Input signals applied to a tuning apparatus are relatively slow moving and of very low amplitude. Signal amplification is required before the signal can be properly presented to a voltage comparator. The amplified signal also requires a certain relationship to the zero reference point connected to the voltage comparator. U.S. Pat. No. 4,429,609 uses 1.2 volts as a zero reference point so that the input signal is centered around this voltage. The first problem occurs when the input signal to the operational amplifier is amplified with a very high gain. Operational amplifiers possess a characteristic called &#34;input offset voltage&#34; which appears at the output of the amplifier as a D.C. offset which is multiplied by the amplifier gain. Normal offsets are usually on the order of two to ten millivolts and vary from amplifier to amplifier. By taking the worst case scenario into account, the offset produced by the operational amplifier with a gain of 100 would yield a D.C. offset of about 1 volt at the amplifier output. To further complicate matters the input signal is centered around 1.2 volts D.C. and the offset from the amplifier equals 1 volt D.C.. Adding these D.C. voltages together yields a value of 2.2 volts D.C. at the operational amplifier output around which the varying input signal will now be centered. Although voltage comparator switching might still occur due to the large gain of the signal and the hysteresis circuitry, the voltage comparator switching point will not be optimized. 
     Even when the input signal is amplified, the signal still travels at a fairly slow rate. Voltage comparator circuits are very fast and require the input signal to travel quickly through the threshold region of the zero reference point where switching of the logic states takes place or the voltage comparator output will be indeterminate causing glitching of the voltage comparator output to occur. This is why a hysteresis circuit is used which modifies the zero reference point by creating a switching window for the voltage comparator output. 
     The correct method of implementing input signal digitalization in this device would be to implement an offset nulling circuit on the high gain operational amplifier to obtain a zero D.C. offset with resect to the 1.2 volt zero reference point and eliminate the hysteresis circuitry so that the voltage comparator can switch at the zero degree and 180 degree points where the varying amplified input signal is traveling at the fastest rate. Even with this modification, the amplified input presented to the voltage comparator would be too slow for the voltage comparator to exhibit fast enough rise and fall times of the pulses produced to control reliably digital logic circuits. This is due to the input signal step over drive above the zero reference point required by the voltage comparator for fast switching between states to occur. The longer the input signal is within the voltage comparator threshold region, the slower the rise and fall times will be at the voltage comparator output. 
     U.S. Pat. No. 4,523,506 also describes a method of producing a digitalized signal output from a voltage comparator to interface to high speed digital logic, but without a hysteresis circuit. The described method is without regard to the operational amplifier output D.C. offset voltage that presents the varying input signal to the voltage comparator. This method will also cause the voltage comparator to switch states at the non-ideal points away from the preferred zero degree and 180 degree points of the substantially sine wave signal as previously discussed. 
     One item of importance relating to voltage comparator performance is the inclusion of an input amplifier under control of an automatic gain control circuit that will stabilize the output signal amplitude. This will tend to increase the voltage comparator performance relating to the input step over drive required for more stable and faster switching to occur at the voltage comparator output minimizing errors when the digitalized pulse is presented to high speed digital circuitry. In a tuning system which requires the tuning of string instruments, the tone or signal tends to decay fairly rapidly so that if some type of automatic gain control is not employed, the input signal step over drive required by voltage comparators when referenced to the threshold region will further decrease the voltage comparator output rise and fall times resulting in poor performance. 
     B. INPUT SIGNAL FILTERING 
     A system that is intended to display pitch and pitch error with accuracy requires a method of suppressing any harmonics associated with the fundamental. The tone associated with each instrument contains harmonics of the fundamental which produce the characteristic sound of each different instrument. These harmonics, especially odd order harmonics, can produce serious errors in the displayed pitch indication unless they are eliminated. 
     U.S. Pat. No. 4,429,609 describes a method of filtering by which the fundamental frequency of a harmonically rich tone can be deduced from a method of correlation between fourteen successive half cycles of the digitalized input tone or signal. This method suffers from the fact that the tone or signals emitted by an instrument are continually changing in their harmonic structure. The irregular harmonics of a tone occur in string instruments very actively after the initial plucking or hammering of a string. This action is due to inaccuracies in the manufacture of the string allowing the oscillation of the string to vary in intensity at different points along the string, dynamically changing the harmonic content of the sounded tone. The period of each complete cycle of the digitalized input signal will remain somewhat constant, but the two half cycles that make up the period of the tone will vary in relation to each other, proportional to the changing harmonic structure of the tone on a cycle-to-cycle basis. 
     The digital correlations depend upon all of the fourteen consecutive half cycles having a time relationship between each of the half cycles. The described circuit presents a remedy via the microprocessor which chooses the filter that achieves the best results. Since this filtering arrangement is fixed, it would be impossible to eliminate totally all of the harmonics of every note within each octave. Errors would be introduced into the device and correlations between fourteen half cycles would be rare. 
     U.S. Pat. No. 4,434,697 and U.S. Pat. No. 4,523,506 use straightforward methods of input signal filtering that attempt to eliminate any harmonics before the input signal is applied to the voltage comparator for digitalization. 
     U.S. Pat. No. 4,434,697 describes a method of filtering input signals employing fixed low pass filters placed one octave apart from each other. Although this device is intended for use in determining chord triads, it is not without shortcomings. Even though the low pass filters are an octave apart, lower amplitude odd order harmonics still affect the input signal by slowing down the zero-crossing time. Fixed cascaded low pass filters can also create another error source which is related to power line interference induced into high impedance transducers such as a guitar pickup having an additive effect on a low level input signal possibly causing irregularities in the calculated period. 
     U S. Pat. No. 4,523,506 describes a method of filtering a gain-controlled constant amplitude input signal by presenting the signal to the input of sixteen fixed-frequency low pass filters located one half an octave apart consecutively adjacent to each other. Each filter output is connected to a threshold detector to allow selection logic to determine the relative output amplitude of each filter and close a normally open analog switch for connecting one of the filter outputs to a master bus. The master bus presents the filtered signal to a voltage comparator for digitalization. 
     This filtering process can be quite effective in the determination of the fundamental frequency from a harmonically rich input tone or signal, but unfortunately there are problems associated with this method of deducing the fundamental frequency. First, by the use of fixed frequency low pass filters, power line interference emitted by light dimmers or fluorescent lights can be induced into high impedance transducers producing an unwanted additive effect on low level applied tones or signals causing errors in the calculation of the period and consequently false indications on the display. Power line noise induced into a high impedance transducer can also cause false triggering of the apparatus and garbage to be displayed. Second, to support deduction of the fundamental for eight full octaves, it would be necessary to use numerous components to construct sixteen low pass filters, sixteen threshold detectors, sixteen sections of the selection logic, and sixteen analog switches rendering the device both prohibitively large and expensive. 
     C. SYNCHRONIZATION OF THE APPLIED INPUT SIGNAL TO DIGITAL LOGIC 
     The device of U.S. Pat. No. 4,523,506 also suffers from the method by which the applied tone or signal is synchronized to the crystal time base to develop a digitized value used to calculate pitch and pitch error. The digitalized voltage comparator output requires very fast rise and fall times as previously discussed for interface to high speed logic circuits. Even the fastest voltage comparator output signal will not have a timing relationship to the crystal time base unless a method of synchronization is used. This apparatus requires a flipflop so that each rising edge of the voltage comparator output causes the flipflop to output a &#34;high&#34; or logical &#34;1&#34; state to a dual input AND gate to control the output of the crystal time base presented to the digital counter. 
     Two problems arise from this method of input signal synchronization to the crystal time base. First, as previously mentioned, voltage comparator outputs normally have rise and fall times that can vary between eighty nanoseconds to well over one microsecond. Upon presenting the voltage comparator output to the flipflop clock input, timing errors occur at the flipflop output due to the clock input threshold specification for the flipflop to change states. The threshold limits for the flipflop to perceive a rising edge of the digitalized input lie between 0.9 volts and 1.9 volts for transistor, transistor logic (TTL) families. During the period that the flipflop clock signal is within the threshold region, the flipflop output state is indeterminate. If the rise time for the voltage comparator to switch between 0.4 (logical &#34;0&#34;) volts to 5.0 (logical &#34;1&#34;) volts takes 500 nanoseconds at the clock input to the flipflop, a possible error of 220 nanoseconds could result from the two flipflop clock edges required for each full cycle of the applied input signal to control or gate the crystal time-base presented to the digital counting circuitry. Second, the high or &#34;1&#34; state of the flipflop output denoting one complete input cycle enables the crystal time-base to be presented to the digital counter. A problem arises between the time relationship of the flipflop output and the crystal time-base. The crystal time-base output to the digital counter will always be behind in time with the relationship to the flipflop output used to enable or disable the clock from the crystal time-base to the digital counter. The possible error could be just less than two cycles of the crystal time base. Since the crystal time-base frequency is 7.4201987 megahertz, two crystal time-base clock cycles amount to 270 nanoseconds which is the possible error condition. 
     Both of the aforementioned errors would be accumulative over time and can vary on an input-cycle-to-input-cycle basis causing the displayed pitch error indication to vary by the accumulated error. Additionally, a crystal time-base with accuracy of exactly 7.4201987 megahertz would be prohibitively expensive or would require a great amount of time for adjustment, with costly equipment being required for this adjustment. 
     D. DISPLAYED NOTE AND PITCH ERROR INDICATION 
     Microprocessor-based tuning aids have long suffered from the method used to display pitch indication to the user/operator. The device of U.S. Pat. No. 4,434,697 can display a single note or a combination of notes in a chord triad by the use of an alphanumeric indication easily interpreted by the user/operator. The apparatus, however, is not intended for use as a pitch analyzer. Only two indications of pitch error are displayed; one being the minus sign (-) to indicate a note is flat with respect to concert pitch and the other being the plus sign (+) to indicate a note is sharp with respect to concert pitch. Relative measurements between different instruments not tuned to concert pitch would be impossible. 
     U.S. Pat. No. 4,429,609 and U.S. Pat. No. 4,523,506 both describe light emitting diodes (LEDs) placed relative to the note position on the musical grand staff for indication of the sounded note with the octave of the note displayed either above or below the musical grand staff. This method of notation takes into account that the user/operator of the apparatus is very experienced with the standard of written music as it is denoted on the musical grand staff. Many musicians and musical instrument repair technicians are only somewhat familiar with the method by which notes are indicated on the musical grand staff, so that they would need a great amount of time to determine the sounded note and would find this method of display difficult to use. 
     U.S. Pat. No. 4,429,609 describes eight LEDs used to indicate pitch error. Each LED has adjacent labeling of the value of the pitch error deviation from theoretically perfect concert pitch, but is only capable of displaying pitch error with a ten cent resolution between adjacent LEDs allowing the user/operator to tune or analyze the pitch with very limited accuracy. 
     U.S. Pat. No. 4,523,506 describes the use of one hundred LEDs adjacent to each other in a straight line to indicate the pitch error. Only the centered LED in the middle is labeled and indicates exact concert pitch when active. The user/operator of this device cannot easily determine the degree of the pitch error for relative measurements between instruments. This method of pitch error indication would require a front panel twenty inches high to mount all the LEDs in a straight line if standard two tenths of an inch spacing is used between adjacent LEDs making the apparatus prohibitively large. 
     E. THE AVERAGING TECHNIQUE 
     Notes sounded from musical instruments change dynamically in harmonic content as well as in pitch. When these tones or signals are developed into an electrical signal, the dynamic quality of the signal can cause the displayed indication of pitch error to fluctuate unless certain precautions are addressed. This phenomenon tends to be averaged by the human ear and becomes perceived as the intended pitch. The electronic signal developed from an input tone or signal originating from an instrument used to calculate the pitch error must attempt to emulate the human ear for the stable indication of pitch error. 
     The device of U.S. Pat. No. 4,429,609 accumulates all the input signal data during the entire time that the input tone or signal is active. Then the apparatus calculates and averages the correct correlations between a number of fourteen successive half cycles of the applied tone or signal and outputs the pitch and pitch error to the display. Only one output is made to the display for each input tone or signal applied to the apparatus, making the indication of the direction of the tone or signal difficult to track while the tuning mechanism of an instrument is being adjusted. In order to indicate the direction of the pitch error and to emulate the human ear, a random sampling of input cycles must be collected to maintain the past and present history of the applied tone or signal and update the display in a manner so that the user/operator is presented an indication of the applied pitch in real time. 
     The device of U.S. Pat. No. 4,523,506, upon detection of the applied input tone or signal, will present the digital counter with the exact number of crystal time-base clocks to accumulate the desired resolution needed to calculate accurately the period of the fundamental. At low frequencies the resolution is based on just one cycle of the applied tone or signal, while at higher frequencies more than one cycle of the applied input tone or signal is needed to acquire the resolution to calculate accurately the period of the fundamental. Once it has been determined that the resolution requirement has been met, counters that tally the pitch error are decoded and the octave and note are applied directly to the display. 
     The outcome of data displayed in this manner will effect the pitch error indication so that a group of some of the adjacent LEDs will be illuminated simultaneously. The reason for this is due to the varying pitch on cycle-to-cycle because any instrument is basically an unstable oscillator. Tones or signals emitted by an instrument when developed into an electronic signal are irregular with respect to the crystal time-base, thus many input cycles should be averaged to define accurately the applied pitch. 
     It would be desirable to be able to collect a number of cycles of the applied pitch, average the cycles over a period of time, reject the largest and smallest values, record the present and past history of the averaged cycles, and indicate pitch error as a positive or negative decimal numeric value in real time to display the direction of the pitch while the tuning mechanism of an instrument is being adjusted. An alternative method to the averaging of cycles and rejecting the largest and smallest values is to provide a way of determining the mean of a number of input cycles by the use of buffers which store the calculated periods that have a certain numeric relationship. A count of the number of cycles in each buffer could then be tallied, and the buffer with the most closely related periods would contain the mean of the applied input cycles which then could be averaged and displayed in real time. Each of the U.S. patents referred to above are incorporated herein by reference. 
     SUMMARY OF THE INVENTION 
     The present invention intends to eliminate all the problems associated with prior tuning aids or pitch analyzers in general and microprocessor tuning aids or pitch analyzers in particular as discussed above. The object of the present invention is, inter alia, to provide the user/operator with an apparatus to be used as a reference standard based on theoretically perfect concert pitch, to indicate the deviation from theoretically perfect concert pitch as a positive or negative decimal number, to indicate the direction of the applied tone or signal during the tuning of an instrument relative to theoretically perfect concert pitch, and to indicate the relative difference in pitch between instruments relative to theoretically perfect concert pitch. 
     Accordingly, the present invention provides an apparatus for identifying the octave, note and degree of sharpness or flatness of a musical sound. The apparatus includes a transducer means for converting the sound into an electrical signal and a filter means, responsive to the electrical signal provided by the transducer means, for sweeping a plurality of frequencies to pass a filter output signal having a frequency corresponding to a frequency of the electrical signal. The apparatus also includes a microprocessor means and a fundamental detection means, cooperating with the microprocessor means, for analzying the filter output signal to identify when the frequency of the filter output signal corresponds to the fundamental frequency of the electrical signal and for providing a fundamental detection signal indicating such correspondence. The filter means, responsive to the fundamental detection signal, is maintained at a particular scanning frequency at which the frequency of the filter output signal corresponds to the fundamental frequency. A square wave generator means, responsive to the frequency of the filter output signal corresponding to the fundamental frequency, provides a square wave output signal having a same period as the filter output signal. A logic circuit means, responsive to the square wave output signal, provides an output indicating a period of the square wave output signal. The microprocessor means comprises means for comparing the output from the logic means with a look-up table including a plurality of previously calculated periods to provide an output indicating the octave, note and degree of sharpness or flatness of the musical sound. A display means, responsive to the output of the microprocessor means, displays the octave, note and degree of sharpness or flatness of the musical sound, with the note being displayed as an alphanumeric character and the degree of sharpness or flatness being displayed as a positive or negative number on a scale including a zero value representing perfect concert pitch and a plurality of positive and negative values on each side of zero. 
     Also according to the invention, there is provided a digital signal processing aparatus for identifying the octave, note and cent of a musical sound, comprising a transducer means for converting the musical sound into an electrical signal, a digital detection means, receiving the electrical signal from the transducer means, for determining the octave, note and cent of the musical sound by detecting a fundamental frequency of the electrical signal, and a display means, responsive to the detection means, for displaying the note as an alphanumeric character and the cent as a positive or a negative decimal integral number from minus 49 to plus 50 with zero cents representing perfect concert pitch. 
     According to another aspect of the invention there is provides an apparatus for indicating the instantaneous pitch of an unknown applied acoustical tone or electronic signal relative to theoretically correct perfect concert pitch. An input means inputs acoustical sound waves via a microphone and an associated preamplifier or an electrical signal through a phone jack and an associated preamplifier. A system zero reference point is established through a constant current source connected to a precision Zener diode to provide a zero reference voltage under the conditions of a varying power source. A potentiometer is provided for the user/operator to manually adjust the preamplifier output amplitude of the applied tone or signal to the apparatus. An amplifier amplifies both outputs of either of the input preamplifiers and the amplification is controlled by a microprocessor. Either of the output signals of the amplifiers is directed under microprocessor control to a switched capacitor bandpass filter by means of a single pole, double throw switch. A means is provided for enabling the microprocessor to read the binary logic level of a single pole switch to determine which of the two amplifiers under microprocessor control is to expect the applied tone or signal so that only one of the amplifiers will be under control of the microprocessor. The output amplitude of the amplifier under microprocessor control is converted to a binary digital value proportional to the amplitude by rectifying the output of the amplifier under microprocessor control and filtering the rectified voltage for presentation to an analog to digital conversion device. A gain adjustment means is provided for adjusting the gain of the amplifier under microprocessor control by the microprocessor writing control signals through a latch to a digitally adjustable resistor in the gain determining circuitry of the amplifier. The presence of an applied tone or signal is detected by the microprocessor reading through a buffer a predetermined digital binary value from the analog-to-digital conversion device. The amplifier under microprocessor control is adjusted to a predetermined optimal amplitude by the microprocessor reading through a buffer the present digital binary value of the analog-to-digital conversion device and adjusting the gain of the amplifier until the predetermined digital binary value as read through a buffer by the microprocessor of the output of the analog-to-digital device corresponds to the predetermined optimal value. The microprocessor reads a predetermined digital binary value through a buffer of the analog to digital conversion device to exit the operation of the apparatus when the applied tone or signal is below the required amplitude for the proper operation of the apparatus to continue. A switched capacitor bandpass filter is presented with an optimal signal amplitude to attenuate all the frequencies outside the bandpass of the filter and to provide gain to only one percent of the frequency domain located inside the bandpass of the filter on either side of the center frequency of the filter. A variable frequency oscillator output, under control of the microprocessor, is presented to the switched capacitor bandpass filter for adjustment of the filter bandpass center frequency proportional to the oscillator frequency. A table of predetermined values is provided for presentation to the variable frequency oscillator by the microprocessor through latches. The values are calculated so that each adjacent value will cause the oscillator to change frequency corresponding directly to a two-percent difference in the frequency domain in terms of the center frequency of the filter bandpass starting with the lowest center frequency of the bandpass and sweeping upward to consecutive adjacent center frequencies of the bandpass. A buffer area in RAM memory is incremented for every table value loaded into the variable frequency oscillator so that the microprocessor can cause restart of the apparatus if a fundamental has not been detected when the count in the buffer denotes that the top of the table has been reached. A means is provided for buffering the output of the switched bandpass filter. A means is provided for isolating the buffered output of the switched capacitor bandpass filter by a capacitor or other means to provide direct current isolation and alternating current coupling to the circuitry for interfacing to digital logic. An amplifier is provided for amplifying the isolated buffered output of the switched capacitor bandpass filter to make up for the atenuation in the coupling circuitry. The output amplitude of the amplifier is rectified and filtered to buffer the coupled output of the switched capacitor bandpass filter to create a direct current voltage proportional to the amplitude for presentation to an analog to digital conversion device to be read by the microprocessor through a buffer to detect the predetermined value of fundamental acquisition. An integrator integrates the isolated and coupled output signal of the switched capacitor bandpass filter to remove distortion in the form of a staircase, sinusoidal output to provide a normal sine wave output. An amplifier is provided to yield greater amplitude through signal gain to the buffered, isolated, coupled and integrated signal. The signal gain amplifier includes an output offset nulling circuit so that the output signal of the amplifier has zero output offset with respect to the system zero reference voltage to present two amplifiers, one inverting and one noninverting, a signal with zero output offset with respect to the system zero reference voltage. A circuit is provided to accomplish output offset nulling of the inverting and noninverting amplifiers to create two reference signals exactly opposite with respect to the system zero reference voltage and exactly 180 degrees out of phase for presentation to a voltage comparator. A digital square wave output generating means provides a digital square wave output from the voltage comparator, which changes state exactly at the zero and the 180 degree points of the reference signals when the signals logically intersect each other producing a digitalized representation of the period of the output of the switched capacitor bandpass filter. The square wave is presented to a Schmitt trigger logic device for the interfacing of the square wave to the 74 HC logic family. A 20 megahertz crystal oscillator with an accuracy of 100 parts per one million is provided to give timing cycles for synchronization of the square wave by clocking an eight bit serial shift register with the time base to provide control for the counting and latching digital logic. Metastability is avoided in the shift register during the synchronization process to the square wave by requiring that the first two stages of the shift register be unused. Separate counting and logic devices are divided and synchronized between each state of the digitalized pulse cycle so that counts of 100 nanosecond cycles are accumulated and latched for each half cycle. An interrupt to the microprocessor is created on the rising edge of each pulse cycle output by the Schmitt trigger logic device so that the microprocessor will read the accumulated counts stored in the latches and store the accumulated counts of the whole period in a RAM buffer area. A means is provided for enabling or disabling two modes of requesting interrupt processing by the microprocessor, one mode for reading the latches which contain the accumulated counts from the digital counting circuitry and another mode for updating the data indicated on the display. A means is provided for giving priority to the interrupt request for reading the latches containing the accumulated counts over an interrupt request to update the data on the display. A means is provided for determining that 16 valid pulse cycle periods have been collected by the microprocessor and stored in RAM memory by comparing a count that is incremented inside the interrupt subroutine to the predetermined count of 18 periods at which time the pulse cycle interrupt routine is disabled and the last 16 pulse cycle periods are added together with the synchronization average delay for 16 pulse cycles and stored in a RAM memory buffer area for presentation to the pitch table and interrupts are enabled so that more pulse cycle periods can be collected while the octave, note and cent values are determined or a display update is underway. A table is provided containing 1200 calculated periods exactly relating to the midpoint of every cent in an octave. A means is provided for calculating all the periods in a table by finding the inverse of 440.000 hertz which is 0.0022727 seconds and adjusting the period to the exact number of 100 nanosecond hexacdecimal counts that are accumulated by sixteen periods which is equal to &#34;A8&#34; or 22727 decimal. The number of 100 nanosecond hexadecimal counts that equals 22727 decimal counts is multiplied by the ratio of 1:1.0005778 or the ratio of one to the twelve hundredth root of two to find the periods one cent adjacent to each other until the bottom of the table is reached which is the period equal to the pitch &#34;C8-50.&#34; Then the sixteen periods of 100 nanosecond hexadecimal counts which is equal to 22727 decimal counts is divided by the same ratio to find the periods one cent adjacent to each other until the top of the table is reached which is the period equal to &#34;B8+50.&#34; A means is provided for calculating the final values for the lookup table by averaging each two adjacent cents in the table of the cent period boundaries to yield a table consisting of each midpoint period between each cent. An adder is provided for always adding groups of sixteen pulse cycle periods together so that when the added sum of the periods is presented to the table, sufficient resolution is obtained so that the table values will be directly equal to the highest octave supported by the apparatus which is the octave ranging between &#34;C8-50&#34; to &#34;B8+50&#34; and all pitches in lower octaves will have more than sufficient resolution. The added sum of sixteen pulse cycles periods and the associated synchronization delays is presented to determine if the added value falls inside the table limits. The added sum is divided by two and a buffer area in RAM memory relating to the octave count is decremented until the added value falls inside the table limits. A buffer area in RAM memory is incremented for each remainder from the divide-by-two process and the remainders are added to the value found to fall inside the table limits. The note value is determined from the table of 1200 consecutive values by comparing the table values starting 100 table entries apart from the bottom of the table to the input value and incrementing a buffer in RAM memory each time the table value is found to be greater than the input value until a table value is found to be less than or equal to the input value at which time the buffer area in RAM memory will contain the note value of the input value equalling a count between one and twelve. The cent value is determined by comparing table values to the input values 100 table entries below the point in the table where the note table value was found to be less than or equal to the input value and incrementing a buffer area in Ram memory each time an upper consecutive table value entry is found to be greater than the input value until a table value is found to be less than or equal to the input value at which time the buffer area in RAM memory will contain the cent value of the input value where a count of 51 will equal perfect concert pitch and all counts below 51 will be flat while all counts above 51 will be sharp with respect to perfect concert pitch. The octave, note and cent values are stored in a RAM buffer area for each acquisition until a predetermined number of acquisitions have been collected at which time the acquisitions will be correlated for accuracy so that if acquisitions without a predetermined correlation exists, an exit path is provided to abort normal processing causing a total system restart, and a flag is set in the display update routine to denote that a restart operation was caused by correlations which were outside the predefined tolerance, but if the correlations are within the predetermined tolerance, the cent values will be averaged and stored along with the octave and note values in the display buffer in RAM memory. A display buffer in RAM memory is provided so that up to six averaged cent values can be stored between display updates. A 250 millisecond timer is provided to interrupt the microprocessor for a display of update requests. Flag buffers are provided in RAM memory which denote the present condition of the apparatus. One flag is used to denote that there is presently no data in the display buffer, and another flag is used to indicate that there is not an applied tone or signal to be processed. An additional flag denotes that the correlation of at least separate acquisitions were out of tolerance and that normal processing was aborted and the apparatus restarted. A buffer area in RAM memory is provided to hold the present cent values for correlation with the latest value upon receipt of a display update request. A display update routine is initiated by the timer interrupt which first checks the operation flag conditions of the present status of the operation of the apparatus for display of any abnormal status which will override any data in the display buffer. If normal status is indicated in the flag buffers in RAM memory, the cent values are averaged and correlated with the correlation buffer holding the present cent value being displayed to determine if the latest value exceeds the present displayed value by more than plus or minus two cents, and if the latest value is over the correlation tolerance, the latest cent value is loaded into the correlation buffer and averaged with the current display update data for display. If the correlation between the latest cent value and the present cent value are within the tolerance, the cent value is stored, converted into a positive or negative decimal number, presented to a table that corresponds to the segments of the two numerical seven segment indicators, the two segments that relate to the plus or minus indication on the display and the note value is presented to a table which corresponds to the segments which relate to the alphanumeric and sharp or flat indications on the display. The display segment data is then loaded serially into the RAM in the display driver which will then activate the corresponding segments on the display and the display update routine is terminated and normal processing resumes. The buffer RAM memory stores the note value last indicated on the display. The alphanumeric portion of the display can indicate the notes &#34;C&#34;, &#34;Db&#34;, &#34;D&#34;, &#34;Eb&#34;, &#34;E&#34;, &#34;F&#34;, &#34;F#&#34;, &#34;G&#34;, &#34;Ab&#34;, &#34;A&#34;, &#34;Bb&#34;, and &#34;B&#34; and &#34;-&#34; to indicate that the correlations between at least two acquisitions were out of tolerance and &#34;::&#34; is indicated when the microprocessor has determined that the tone or signal applied to the apparatus possesses an amplitude greater than can be properly processed and the apparatus has been restarted. The two seven segment numerical displays and a plus or minus display can indicate a positive or negative decimal number ranging from minus 49 to plus 50 with zero (without either the plus or minus indication) denoting perfect concert pitch. The display will indicate the word &#34;READY&#34; when the microprocessor sets the corresponding flag which is read in the display update routine when there is not a tone or signal applied to the apparatus. The octave of the applied pitch is indicated via eight light emitting diodes located in a straight line adjacent the display and labelled consecutively 1-8 from top to bottom. An active or lit LED indicates the octave of the presently displayed note and cent value unless none of the LEDs are lit indicating octave zero. 
     The apparatus can also include a switch which is thrown to change the mode of the fundamental acquisition from the automatic mode as described above to the manual mode for the fundamental processing of a known pitch. A momentary switch, when depressed, will cause the alphanumeric indication of the display to scroll through all twelve of the note indications and an indication for setting the octave of the selected note until the momentary switch is released causing the display to indicate the note indication present when the momentary switch was released and a buffer in RAM memory stores the note value presently displayed. In the event that the octave indication was selected, the momentary switch when depressed will cause the octave LED&#39;s to indicate in a scrolling manner the desired octave. Upon releasing the momentary switch the octave value is stored in a RAM buffer and the display will indicate both the selected note and octave. The last stored note and octave value in automatic mode processing is indicated on the display in the manual mode. A table of calculated values is provided for presentation to the variable frequency oscillator to change the center frequency of the switched capacitor bandpass filter so that this filter will only scan six percent of the frequency domain centered around the octave of the note indicated on the display starting at the lowest frequency of the octave scanning consecutively upward to higher frequencies until the fundamental is determined by the microprocessor in the above-described manner of reading through a buffer the predetermined digital binary value of the digital-to-analog conversion device which indicates the detection of the fundamental. Once the fundamental is detected, the apparatus causes normal processing to begin in the same manner as described above. 
     The apparatus can also include a means for determining the mean of the digital pulse cycles produced from the fundamental by creating three buffer areas in RAM memory so that after the collection of eighteen consecutive pulse cycle periods, the last sixteen pulse cycle periods are examined and placed into one of the three buffers depending on their relation to the boundaries separating the buffers which is equal to, e.g., two microseconds. The first boundary is calculated by averaging the last sixteen pulse cycle periods and the other two boundaries are placed on both sides of the first boundary. If a pulse cycle period is found not to correlate to any of the three buffers, it will be discarded. Three separate buffer areas in RAM memory corresponding to the three pulse cycle period buffers are incremented when a pulse cycle period is placed in one of each of the three buffers as well as a buffer area which is incremented for each input pulse cycle period used a threshold excess buffer. The first buffer to contain sixteen pulse cycle periods contains the mean of the input pulse cycle period which are added together with the synchronization delay and presented to the table for octave, note and cent calculation. The threshold limit is predetermined and checked each time a group of sixteen pulse periods have been collected. If the predetermined threshold limit is exceeded, the microprocessor will abort normal processing and restart the apparatus. Once the octave, note and cent values have been determined in the manner previously described, they are placed directly into the display buffer avoiding the correlation time of processing a predetermined number of separate acquisitions. 
     The apparatus can also include means for quickly determining the fundamental of an unknown pitch by means by the use of the above circuitry and the further inclusion of a two-to-one analog multiplexer to present to the circuitry that produce the digitalized pulse cycle to the digital logic either the output of the switched capacitor bandpass filter or the output of the input amplifier so that unfiltered pulse cycle periods can be collected and analyzed. A harmonically rich input tone or signal, when developed into a digital square wave, will produce a pulse cycle period in relation to musical pitch that is a third of the fundamental an octave and one-half above the fundamental or a fifth of the fundamental two and one quarter octaves above the fundamental. At the beginning of the fundamental acquisition process, the microprocessor will direct the output of the input amplifier through the analog multiplexer to the circuitry that produces the pulse cycle for the digital logic and sixteen pulse cycle periods will be collected and stored in the RAM memory. The sixteen pulse cycles are then averaged and the average value of the pulse cycles is used to calculate the position in the table of center frequencies that fundamental acquisition will start. The microprocessor will then direct the output of the switched capacitor bandpass filter through the analog multiplexer to the circuitry that produces the pulse cycles for the digital logic and the filter output rectifier. Since the averaged value of the unfiltered input tone or signal is known, a point in the center frequency cable can be selected as a starting point for the fundamental acquisition which will be two and one-half octaves in relation to musical pitch below the point in the center frequency table to which the averaged unfiltered input value corresponds. The switched capacitor bandpass filter will now only have to sweep upward through the consecutive center frequencies from the point two and one-half octaves below where the unfiltered tone or signal input value is calculated in the center frequency cable, thus greatly increasing the fundamental acquisition processing speed. 
     The invention also provides an apparatus for indicating the instantaneous pitch of an unknown applied sonance relative to theoretically perfect concert pitch. This apparatus determines the frequency of a mechanical resonance via the above-described apparatus and by a memory storing all pitches within the limits of the apparatus and the direct frequency that corresponds to each pitch. The frequency relationship to the pitch indications of the apparatus are computed by the mathmetical ratio of 1:1.0005778 starting at &#34;A4&#34; which is equal to 440.000 hertz. Each frequency relationship to pitch can be computed by dividing 440.000 by the ratio 1:1.0005778 until the bottom limit of the apparatus is reached at 25 hertz or multiplying 440.000 hertz by the ratio 1:1.0005778 until the top frequency of the apparatus is reached at 8000 hertz. The apparatus, when presented a sonance from the motion of a material object, will deduce the fundamental and display the pitch of the sonance. If the fundamental frequency of the sonance is required, then the list of frequencies in relation to musical pitch provides a quick method of determining the frequency from the indicated pitch value displayed on the apparatus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, advantages and features of the present invention will be more fully understood when considered in conjunction with the attached figures, of which: 
     FIGS. 1A-1C represent a simplified block diagram of the preferred embodiment of the hardware required in accordance with the present invention; 
     FIGS. 2A-2G represent a simplified flowchart of the preferred embodiment of the software operation of the present invention; 
     FIGS. 3A-3D are a detailed representation of the preferred embodiment of the display used to indicate the pitch or note as an alphanumeric character and pitch error or cents from theoretical perfect concert pitch as a positive or negative decimal number; 
     FIG. 4 is a timing diagram of the synchronization errors involved in synchronizing the input pulse cycle to the digital logic; and 
     FIG. 5 is a block diagram illustrating the operation of the system according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A. Overview 
     Regarding tuning systems and notations, the modern musical scale includes notes or pitches that maintain a mathematical relationship in frequency to the note &#34;A,&#34; located in the octave of what is called middle &#34;C,&#34; equal to exactly 440.000 hertz. By doubling this frequency to 880.000 hertz an octave would be formed relative to each other. By halving the frequency &#34;A&#34; 440.000 hertz to 220.000 hertz another octave would be formed. When converting these frequencies to sound simultaneously the notes would be heard to be the same but the tone of the notes would be higher or lower in pitch relative to &#34;A&#34; 440.000 hertz. These same sounding notes are called octaves, and exactly twelve notes or semitones are inside each octave. There are ten complete octaves in the audio spectrum of which the middle eight octaves contain most of the more frequently sounded notes. Notation of the notes inside certain octaves will be used to numerically define the octave within which the notes reside. Octaves will be given a corresponding numerical value ranging from zero to nine so that &#34;middle C&#34; for example will be noted as &#34;C4&#34; which has an exact relationship in frequency to 261.625 hertz. 
     As previously stated, between octaves are twelve notes called semitones. Each note in the entire musical spectrum can be mathematically calculated to provide a frequency relative to theoretically perfect pitch. Adjacent notes or semitones are separated from each other in frequency by the twelfth root of two which is equal numerically to 1.0594631. Multiplying or dividing the frequency of any note by 1.0594631 will yield the higher or lower adjacent note in frequency. 
     Between adjacent notes or semitones are one hundred units of pitch called cents. A mathematical relationship in frequency also exists for determining the pitch between the notes or semitones equal to the twelve hundredth root of two which is equal numerically to 1.0005778. Starting at the frequency that is directly related to any note or semitone, adjacent cents can be determined higher or lower in frequency by multiplying or dividing the frequency by 1.0005778. For example, to find the frequency of the pitch which is one cent sharp of &#34;A4&#34; multiplying 440.000 by 1.005778 yields the frequency of pitch which is notated &#34;A4+1&#34;. Likewise, dividing &#34;A4&#34; 440.000 by 1.0005778 yields the pitch in frequency of &#34;A4-1&#34;. Multiplying or dividing each adjacent cent in frequency equals the next adjacent cent in frequency. If these calculations are performed 1200 times a value with a direct relationship to frequency can be found for every cent inside an entire octave. 
     FIGS. 1A-1C represent a simplified block diagram of the preferred embodiment of the present pitch analyzer/tuning aid apparatus. Upon depressing the power on/off switch, microprocessor 50 will set the gain of the &#34;microphone input&#34; operational amplifier 2 and &#34;phone jack input&#34; operational amplifier 7 through control by the &#34;microprocessor controlled&#34; digital resistors 3,5 (EEPOTS by Xicor, Inc.) from &#34;microprocessor write&#34; latch output 8 to the minimum gain. The outputs from the &#34;microphone input&#34; operational amplifiers 2 and the &#34;phone jack&#34; operational amplifier 7 are directed to the switched capacitor bandpass filter 13 and the &#34;input rectifier&#34; buffer 14 by a switch mechanism 4 internal to the phone jack 6. Also included internal to the phone jack 6 is another switch mechanism 37 that applies a logic level to &#34;microprocessor controlled&#34; digital resistors 3,5. Logic selection control 37 is initiated by inserting or by the absence of a 1/4&#34; phone plug in phone jack 6. If the 1/4&#34; phone plug is installed in phone jack 6, the &#34;phone jack&#34; operational amplifier 7 output is directed to the switched capacitor bandpass filter 13 and &#34;input rectifier&#34; operational amplifier 14. If the 1/4&#34; phone plug is not installed into phone jack 6, the &#34;microphone input&#34; operational amplifier 2 output is directed to the switched capacitor bandpass filter 13 and the &#34;input rectifier&#34; operational amplifier 14. 
     Upon the application of a tone or signal to the apparatus, the signal is directed through the &#34;input rectifier&#34; operational amplifier 14 to the &#34;input&#34; rectifier 15 where the signal is converted to a D.C. voltage level proportional to the amplitude of the input signal and detected by voltage comparator 27. Any input level higher in amplitude than loud room noise will cause voltage comparator 27 to change to the active state. Microprocessor 50 will read this condition through &#34;microprocessor read&#34; buffer 26 and processing of the input will begin. 
     The present apparatus supports two different modes of input processing, the automatic mode and the manual mode. The mode of input processing is initiated by the microprocessor reading the logic state of switch 35 through &#34;microprocessor read&#34; buffer 34. Both modes of input processing are intended to be used either together or separately to hasten the process of tuning complex instruments, while the ability to use each mode separately to optimize different pitch analyzing/tuning applications is maintained. 
     Automatic processing begins upon detection of an applied tone or signal to the apparatus by the microprocessor reading the active state of voltage comparator 27 through &#34;microprocessor read&#34; buffer 26 and the correct logic level of switch 35 through &#34;microprocessor read&#34; buffer 34. The detection of an applied tone or signal causes microprocessor 50 to start issuing control signals through &#34;microprocessor write&#34; latch 8 to digital resistor 3 or 5 of the previously chosen &#34;input&#34; operational amplifier 2 or 7 output to control the input signal gain to switched capacitor bandpass filter 13 until the optimum signal amplitude is obtained. The optimum signal amplitude has been predetermined. &#34;Input signal&#34; rectifier 15 outputs a D.C. voltage that is sensed by voltage comparators 28,29 which is read by microprocessor 50 through &#34;microprocessor read&#34; buffer 26. If the outputs of voltage comparators 28,29 were both active, microprocessor 50 would reduce the gain of &#34;input&#34; operational amplifier 2 or 7 through &#34;microprocessor write&#34; latch 8 to control digital resistor 3 or 5 to reduce the resistance in the feedback loop of &#34;input&#34; operational amplifier 2 or 7 decreasing the signal amplitude presented to switched capacitor filter 13. Ideally, microprocessor 50 should read voltage comparator 28 in the active state and voltage comparator 29 in the inactive state indicating the proper amplitude is currently being presented to switched capacitor filter 13. The output of &#34;input&#34; operational amplifier 2 or 7 needs to be continually monitored by microprocessor 50 to keep the amplitude of the signal presented to switched capacitor bandpass filter 13 stable for proper detection of the fundamental. Switched capacitor bandpass filter 13 will then scan all the frequencies in consecutive order from the lowest frequency (&#34;A0&#34;) upward until switched capacitor bandpass filter 13 reaches a frequency equal to that of the applied signal so that filter 13 outputs a signal amplitude that when presented to &#34;filter output&#34; rectifier 25, converted to a D.C. voltage and presented to voltage comparators 30,31,32,33 is read by microprocessor 50 as the detection of the fundamental. 
     There are two main differences between the automatic and the manual modes. In the automatic mode, switched capacitor bandpass filter 13 upon detection of an input tone or signal will sweep through all the consecutive frequencies within the limits of the apparatus. The theory of the detection of the fundamental is when frequency sweeping starts at the lowest possible frequency (&#34;A0&#34;) and sweeps upward, the first noticeable signal level detected by voltage comparators 30,31,32,33 will be the fundamental. The present invention ensures fundamental detection because the predetermined gain and width of the switched capacitor filter bandpass is designed for optimal relationships with the reference voltages presented to voltage comparators 30,31,32,33. 
     The manual mode is initiated by placing auto/manual switch 35 in the manual position. In this mode, switched capacitor bandpass filter 13 can be preset by depressing a momentary switch 36 which will cause the note indication on display 65 to scroll through all twelve notes. When the intended note to be analyzed or tuned is presented on display 65, the operator/user then releases momentary switch 36 and the selected note remains indicated on display 65. When processing begins upon the application of a tone or signal to the apparatus, switched capacitor bandpass filter 13 will only be sensitive to the fundamental of the note selected on display 65. 
     The manual mode of operation is particularly useful for analyzing pitch or tuning instruments with a limited tuning range such as the brass and woodwind families. When analyzing or tuning complex string instruments and the latest electronic keyboard instruments, the automatic and manual modes can be used in conjunction with each other. First, the automatic mode is used to find the fundamental of an unknown applied input tone or signal and then by placing auto/manual switch 35 in the manual position, the last detected fundamental from the automatic mode will be indicated on display 65. The manual mode provides a method for processing of the fundamental in a more expeditious manner because switched capacitor bandpass filter 13 will only scan the frequencies around the octave of the known applied input tone or signal. The frequencies scanned in the manual mode always start with the lowest frequency of the selected note in the octave and scan upward from the lowest to higher frequencies in a similar manner to that used in the automatic mode. The manual mode is also particularly useful for analyzing or tuning notes that possess very fast attack and decay rates such as the uppermost octaves of most string instruments. 
     Once the fundamental has been determined the apparatus functions basically the same in both modes of operation. The fundamental is formed into a square wave by presenting the output of the switched capacitor bandpass filter 13 to circuitry designed to provide an interface between the period of the fundamental and the digital logic. 
     When the amplitude of the applied tone or signal decreases, the D.C. offset of switched capacitor bandpass filter 13 varies in relation to the D.C. offset when switched capacitor bandpass filter 13 input was within the optimum signal amplitude range. To eliminate the varying D.C. offset the switched capacitor bandpass filter must be A.C. coupled to provide D.C. isolation. Switched capacitor bandpass filter 13 output is buffered by operational amplifier 16 to drive a capacitor 17 which provides A.C. coupling and D.C. isolation from the interface circuitry to the digital logic. The A.C. coupled output from capacitor 17 is presented to both the &#34;filter output rectifier&#34; buffer operational amplifier 24 and &#34;integrator buffer&#34; operational amplifier 18. Integrator 19 circuitry removes clock noise from the signal outputted by switched capacitor bandpass filter 13. The clock noise is generated by &#34;microprocessor controlled&#34; oscillator 9, 10, 11, 12. The output frequency of this oscillator is used to control the bandpass center frequency by using the fifty percent duty cycle square wave as the clock input of switched capacitor bandpass filter 13 where the noise is produced internal to switched capacitor bandpass filter 13 and causes the bandpass output to be a staircase sinusoidal waveform. &#34;Filter output&#34; rectifier 25 provides a D.C. output voltage proportional to the amplitude of the output of switched capacitor bandpass filter 13 which is presented to voltage comparators 30, 31, 32, 33. This proportional D.C. voltage is measured against the reference voltages connected to each of voltage comparators 30, 31, 32,33 which provides a means of detecting the fundamental frequency when read by the microprocessor through &#34;microprocessor read&#34; buffer 26. 
     The output of integrator 19 is applied to operational amplifier 20 which provides gain to the input tone or signal fundamental after integration. This operational amplifier 20 requires an offset nulling circuit to maintain zero D.C. offset with respect to the apparatus zero reference point. The output of operational amplifier 20 is presented to the inputs of two operational amplifiers 21, 22. One of the operational amplifiers is configured as a noninverting amplifier known as the &#34;positive reference&#34; operational amplifier 21, while the other operational amplifier is configured as an inverting amplifier known as the &#34;negative reference&#34; operational amplifier 22. Both amplifiers 21,22 also require an offset nulling circuit to maintain zero D.C. offset with respect to the zero reference point of the apparatus for presentation to the &#34;pulse output&#34; voltage comparator 23. The &#34;negative reference&#34; operational amplifier 22 is connected to the negative input of the &#34;pulse output&#34; voltage comparator 23 and the &#34;positive reference&#34; operational amplifier 21 is connected to the positive input of the &#34;pulse output&#34; voltage comparator 23. Since the output of both &#34;reference&#34; operational amplifiers 21, 22 are exactly opposite and 180 degrees out of phase with each other, &#34;pulse output&#34; voltage comparator 23 will change states whenever the two out of phase signals logically intersect each other. This will happen at the zero degree and 180 degree points when the signals are changing at their fastest rate due to the zero D.C. offset nulled in all of operational amplifiers 20,21,22. This minimizes the time that the signals presented to &#34;pulse output&#34; voltage comparator 23 are inside the threshold region of the comparator. Another advantage of this method is the increase in the response time of &#34;pulse output&#34; voltage comparator 23 when converting an input tone or signal into a very accurate digital pulse cycle representation of periods of the fundamental. The operation of this circuitry is almost transparent to the low signal-to-noise ratio of a decaying, weak input applied to the apparatus allowing enough resolution of the digital pulse to measure the fundamental to an accuracy of one half of one cent. 
     Synchronization of the pulse to digital counting logic 39,40,44,45,46,47,48,49,56,57,58,59 is accomplished by applying the output of &#34;pulse output&#34; voltage comparator 23 to a Schmitt trigger logic device to obtain compatibility in the pulse rise and fall times between &#34;pulse output&#34; voltage comparator 23 output and the digital synchronization and counting logic. This will basically take &#34;pulse output&#34; voltage comparator 23 output rise and fall times of 200 nanoseconds and convert the signal to a pulse with rise and fall times less than 20 nanoseconds. The crystal time base 39 operates at 20 megahertz with an accuracy of 100 parts per one million. The cycle time of the crystal time base is 50 nanoseconds allowing for enough resolution to guarantee the synchronous timing requirements of the digital counting 57,59 and latching 56,58 logic. 
     Microprocessor 50 reads the calculated period from &#34;microprocessor read&#34; latches 56,588 when an interrupt service request is issued from flipflop 42 on the rising edge of the next asynchronous input pulse. The results are stored in RAM memory 54 until eighteen consecutive complete cycles have been collected. The last sixteen cycles are then added together and compared against a table of 1200 calculated values. Each value in the table corresponds to the midpoint of all the cents in the octave starting at &#34;C8-50&#34; and ending at &#34;B8+50.&#34; The table is constructed so that all the pitches that fall below &#34;B8+50&#34; cause a divide by two to occur until the input value falls inside the table limits. All the remainders of the divide by two process are tabulated and the octave value stored in ram memory 54 before determining the note and cent values from the table. After a predetermined number of acquisitions the note and cent values are compared for accuracy providing the ability to detect pitch values without correlation between them. If pitch values do not have a certain correlation between them, the operation of the apparatus is restarted from the beginning providing an exit path from the main process and avoiding the display of meaningless data. If a relatively close correlation exists between the predetermined number of acquisitions, the cent values are averaged and placed along with the octave value and the note value into a display buffer in ram memory 54. Upon the receipt of a display update request from a 250 millisecond timer 43 to the microprocessor 50 the cent values, if more than one exists, are averaged and converted into a positive or negative decimal value. The note value and the cent value are then presented to the display driver 64 and the octave value latched in the &#34;octave display driver&#34; 60. The pitch is then indicated on both displays 62,65. 
     An alternative method of determining the pitch of an applied input tone or signal to the apparatus is to find the mean of the period of the fundamental. This is done by placing periods with close correlations into a set of different buffers in RAM memory 54. 
     The pulse cycle periods are collected consecutively until eighteen pulse cycle periods have been stored in a buffer in RAM memory at which time the last sixteen pulse cycle periods are averaged to establish the first boundary which is two microseconds wide. Two 2-microsecond buffers are then established on either side of the first boundary. The pulse cycle periods are then examined and stored inside the buffer in RAM memory that corresponds to the period of the pulse cycle. If a pulse cycle period does not fall inside any of the established buffer boundaries, then that pulse cycle period is discarded. A count of the number of pulse cycle periods is maintained for each buffer until one of the buffers contains sixteen pulse cycle periods. A total count of all the pulse cycles collected is tallied until a certain number of input periods have been detected. At the end of this predetermined number of input cycles and none of the buffers contains sixteen pulse cycle periods, the threshold count has been exceeded and the apparatus will be restarted to provide an exit path from gathering useless input. 
     The buffer with sixteen correlations will contain the mean of the input periods. The data in this buffer is added and compared against the table of 1200 calculated values. Once the octave, note and cent values are found, they are place directly in the display buffer and displayed in the manner previously defined. 
     B. Description of Preferred Embodiments 
     INITIALIZATION 
     Referring to FIGS. 1A-1C and FIGS. 2A-2G, the initialization process begins when power is applied to the apparatus by depressing the ON/OFF switch which causes a 100 millisecond active low pulse to be presented to the microprocessor 50 reset input from the power on reset circuitry. Once the reset pulse issued to the microprocessor 50 becomes inactive or returns to the &#34;high&#34; state, microprocessor 50 will begin to execute operation codes by accessing ROM 52 at physical address 0000H as selected by address decoder 53. The instructions are read by the microprocessor 50 in the form of hexadecimal bytes programmed into ROM 52 that reside in the physical addresses between 0000H and 17FFH which cause microprocessor 50 to perform the desired actions for the successful operation of the apparatus. 
     The initialization of the apparatus begins by disabling the &#34;input interrupts&#34; 67 by microprocessor 50 writing a &#34;1&#34; to the &#34;high priority enable/disable&#34; flipflop 41 which holds the output of the &#34;high priority interrupt&#34; flipflop 42 in the inactive state so that no input interrupts can be serviced. The &#34;low priority interrupt&#34; or the display update interrupt is automatically disabled when the power on reset pulse is applied to the microprocessor 50 reset input and can be enabled or disabled at any time by either of two instructions read by microprocessor 50 from ROM 52. Both interrupt exception subroutines are initialized so that the &#34;low priority interrupt&#34; or the display update interrupt service starts at physical address 0038H and the &#34;high priority interrupt&#34; or the input interrupt service starts at 0066H. RAM 54 which lies in the physical address space between 2000H and 27FFH is selected by decoder 53 The stack pointer is used for storing the microprocessor 50 internal registers when the external interrupts request service. The locations in the RAM 54 that reside between 27F0H and 27FFH are reserved for flag registers for indicating the status of the apparatus at different points in the operation of the program stored in ROM 52. 
     Once the stack pointer has been initialized all the apparatus status registers located in RAM 54 are written with default values by microprocessor 50 that indicate the apparatus initialization is in progress and is preparing to accept input 68. Some of these registers function as status indicators of the fundamental acquisition process while other status registers indicate intermediate values and status information for both the automatic and manual modes of operation for processing data when determining pitch values and display output. After all the register default values have been initialized by microprocessor 50, microprocessor 50 will enable the display interrupts so that the display will indicate the apparatus is ready to accept input 69. The microprocessor 50 also has control over output devices that control the operation of the apparatus which must be written default values. Microprocessor driven components comprise the &#34;microprocessor write&#34; latch 8 that controls the digital resistors 3,5, the &#34;microprocessor write&#34; latch 10 which holds the count for the digitally controlled variable oscillator 9,10,11,12, the &#34;microprocessor controlled&#34; flipflop 41 which controls whether the &#34;high priority&#34; input interrupts are enabled or disabled, the &#34;microprocessor write&#34; latch 60 which controls which of the octave display LEDs will be active, and the display driver 64, which must all have default values written into them by microprocessor 50 before the initialization is completed. 
     The last part of the initialization phase involves setting up the apparatus to accept input and determining the mode of operation. The digital resistors 3,5 may be set in any random manner at power up. The digital resistors 3,5 must be decremented 100 steps each so that both of the digital resistors 3,5 are at step zero. Each of the digital resistors 3,5 have 99 steps or increments inside the total resistance of the device which makes each step worth 1/99 of the total resistance value of the device. The digital resistors 3,5 can be incremented 99 times or decremented 99 times but will never exceed the top or bottom limits of the device even though it may be instructed to do so. At the initialization of the digital resistors 3,5, decrementing each device 100 times will ensure that both of the devices are at the same step value which is equal to zero steps. Once the digital resistors 3,5 are known to be at step zero, each of the digital resistors 3,5 are incremented a certain number of steps required by each of the &#34;microphone input&#34; operational amplifier 2 and the &#34;instrument input&#34; operational amplifier 7 for the predetermined gain required to detect an input tone or signal 70. The number of steps that each of the digital resistors 3,5 are incremented is kept track of in two buffers; POTCNT1 for the digital resistor 3 that determines the gain of the &#34;microphone input&#34; operational amplifier 2 and POTCNT2 for the digital resistor 5 that determines the gain of the &#34;instrument input&#34; operational amplifier 7. Now that the apparatus is set for input detection of the applied tone or signal, the microprocessor 50 will read the logic level of the AUTO/MANUAL switch 35 that determines the mode of operation 71 for fundamental acquisition and will send microprocessor 50 to one of two loops in either the automatic mode or the manual mode section of the program that reads through &#34;microprocessor read buffer&#34; 25 to determine whether there is an input applied so that fundamental processing can begin. 
     The following is an explanation of the register functions: 
     DFLAG--The display update flag register. In the initialization process the default value placed in this register is 00H. If a display update interrupt request is issued by the display update timer 43 while the default value is present, microprocessor 50 is informed that there is not a note or cent value in the display buffer (ABUF-ABUF+15). The display driver 64 is sent data to blink the &#34;READY&#34; indication on the display 65 (step 147) until microprocessor 50 detects display data in the display buffer. Upon processing octave, note, and cent value that are within the predetermined correlation boundaries of valid pitch detection, data is placed in the display buffer. As soon as data is placed in the display buffer, the DFLAG register is written with the value of 01H which indicates that, upon the receipt of a display update interrupt request, the octave, note, and cent values are ready to be processed for indication on the display 65. If a correlation is detected that is out cf tolerance, the value 02H is written into the DFLAG register which, upon a display update interrupt request, will cause the display 65 to indicate &#34; -&#34; (steps 149,150,151). An additional consecutive out of tolerance correlation will cause the DFLAG register to be incremented to 03H which will cause the apparatus to be restarted. 
     ABUF-ABUF+15--The display buffers--in the initialization process these buffers are written with 00H. The Buffer ABUF+1 will hold the note value while ABUF, ABUF+3, ABUF+6, ABUF+9, ABUF+12, and ABUF+15 hold the cent values between display update interrupts. Up to six cent values can be stored and averaged for each display interrupt exception. After the display update interrupt averages the cents values in the buffers, the buffers are cleared by writing with the default value 00H into each register. ABUF+1 which holds the note value is also used as a status register for the display update exception along with the DFLAG register. A note value in ABUF+1 will cause the DFLAG register to be written with 01H so that the data in the display buffer can be averaged and processed to be indicated on the display 65 (step 152). 
     CENTCNT--This register is initialized to 00H and is used to keep track of the number of valid correlations in the display buffer between display update interrupts. This register is cleared to 00H after display update exception. 
     BBUF--In the initialization process this register is written with 00H indicating that the apparatus is waiting for an applied tone or signal. When the apparatus is actively processing an input tone or signal, this register is written with 01H after the fundamental acquisition. When a display update interrupt exception is being processed if this register contains the value 00H and the DFLAG register contains 00H indicating that the display buffer has no data, then the display update exception is aborted and the display 65 will remain unchanged (steps 144,145,146). 
     CBUF--In the initialization of the apparatus this register is written with the value 00H. CBUF is used to cause a blinking effect of the &#34;READY&#34; indication on the display 65 while the apparatus is waiting for input. When a display update interrupt exception is received and BBUF is equal to 00H and CBUF is equal to 00H the entire display 65 is blanked. At the end of the blanking routine CBUF is written with 01H so when the next display update interrupt exception is received and BBUF is equal to 00H and CBUF is equal to 01H the &#34;READY&#34; indication on the display 65 147 is turned on and CBUF is returned to 00H to produce a &#34;READY&#34; blinking effect as long a BBUF is equal to 00H (steps 144,147,148). 
     LBUF--In the initialization process this register is written with 00H. This register is used to keep track of the past history of the cent value for the purpose of smoothing the cent value while the tuning mechanism of an instrument is being adjusted. The last cent value displayed is stored in this register and compared with the current cent value in the display update routine. If the current cent value is more than plus or minus two cents of the last displayed value, the current value is averaged with the previous cent value and the resulting cent value is stored in LBUF and indicated on the display 65. If the current cent value is less than plus or minus two cents, LBUF is updated with the current value and that cent value is displayed. 
     BLKDIS--This register is for use in the manual mode. It is initialized to 01H. In the manual mode this register is written with the value 00H which will cause only the alphanumeric portion of the display to indicate on the display the note indication that is held in the NOTEINC register while the note is chosen by depressing momentary switch 36 and to indicate the chosen note to be processed while the apparatus is waiting for input (steps, 171, 172, 173, 175). When the apparatus is actively processing a note, the value of this register is written with 01H so that the cents portion of the display will not be bypassed. In the automatic mode this register is left unchanged with the value of 01H. 
     NOTEINC--This register holds the note value of the last pitch that was processed. In the initialization this register is written with 01H indicating the &#34;C&#34; note. This register is used mainly in the manual mode for indicating the current note to be processed. In the manual mode the content of this register can be changed by depressing the note switch 36 while the apparatus is waiting for input (steps 171,172,173,175). The automatic mode can modify this register with the last note processed. After processing a pitch in the automatic mode, the last note processed in the automatic mode can be processed in the manual mode by setting switch 35 in the manual mode position. 
     POTCNT1-POTCNT2--These registers are used to keep track of the number of steps that the digital resistors 3,5 are incremented or decremented that directly relates to the resistance value currently presented by the devices. POTCNT1 holds the count of steps that digital resistor 3 is currently at, which relates directly to the gain of &#34;microphone input&#34; operational amplifier 2. POTCNT2 holds the count of steps that digital resistor 5 is currently at, which relates directly to the gain of &#34;instrument input&#34; operational amplifier 7. 
     POTDATA--This register is initialized to 33H. POTDATA is the storage register used to write to the digital resistor control latch 8. The 33H value indicates that the digital resistors are ready to be incremented upwardly to increase the resistance of the device. 
     BIGEST--This register is used in the fundamental acquisition loop as a register that holds intermediate data while each center frequency of the switched capacitor bandpass filter 13 is under test to determine the greatest amplitude output at that particular portion of the frequency domain. This register is always updated to indicate the highest amplitude that was detected at each center frequency of the bandpass output. This register is also used during the fundamental detection because the value contained in this register is compared against the predetermined amplitude values for fundamental detection. This register is initialized to 00H and is written again to 00H upon completion of each center frequency test. 
     BIGBUF--This register is used during the fundamental acquisition. Once the amplitude of the center frequency of the switched capacitor bandpass filter 13 is within the predetermined limits for fundamental detection, the register BIGEST will modify the contents of BIGBUF when the current center frequency test of the value of BIGEST is greater than the current content of BIGBUF. This is so there is a record of the highest amplitude when the bandpass center frequency is directly over the fundamental. 
     CLKCNT--This register is initialized with the value 00H and is used to keep track of the number of center frequency tests that the switched capacitor bandpass filter 13 has currently completed which is directly related to the location of the center frequency of the bandpass filter 13 in terms of the frequency domain. 
     LITE1-LITE6--These are buffer registers used to store the value of the &#34;automatic mode center frequency&#34; table count (CLKCNT) when the amplitude of the switched capacitor bandpass filter 13 center frequency is within the predetermined limits of fundamental detection and is approaching the fundamental. In the initialization of the apparatus, each of the LITE buffers is written with a default value of FFH. Each LITE buffer is directly related to the center frequency amplitude found within the limits of fundamental detection. In other words, there is a LITE buffer for each of the six possible amplitude values that can be detected by the analog-to-digital conversion circuitry 30,31,32,33. When the switched capacitor bandpass filter 13 bandpass output amplitude approaches the fundamental, the bandpass output amplitude will become greater and the current table count (CLKCNT) will be written into the LITE buffer that corresponds to the current bandpass output amplitude until a LITE buffer that corresponds to a lesser amplitude is written with a table count (CLKCNT) that has a higher count than a LITE buffer that corresponds to a greater amplitude. At this point the fundamental has been passed over and the fundamental acquisition is completed. 
     NOTESW--This register is used to indicate that eighteen pulse cycle periods have been collected and the last sixteen pulse cycle periods have been added together when FFH is written into this register so that the octave, note and cent values can be determined. This register is initialized to 00H and is written again to 00H once pitch processing is underway and input interrupts are enabled to gather eighteen more pulse cycle periods. 
     MATCHB1-MATCHB3--These registers are initialized to 00H and are used to hold the note and cent values from the predetermined number of acquisitions of sixteen pulse cycle periods for correlation processing. The registers are cleared to 00H after correlation processing is finished to be ready for the next predetermined number of acquisitions of sixteen pulse cycle periods. 
     After setting up all the default values in the registers, buffers, and latches, microprocessor 50 enables the display interrupts 69 and sets the gain of both the input amplifiers 2,7 to the optimum gain 70 used to determine if a tone or signal is applied to the apparatus. The gain is adjusted through the digital resistors 3,5 by decrementing the digital resistors 3,5 100 times to ensure that each of the digital resistors 3,5 is at the minimum resistance value and then incrementing each of the digital resistors 3,5 by a predetermined number of steps to increase the gain of each of the input operational amplifiers 2,7 to the optimum gain for detecting an applied input tone or signal. The number of steps that each of the digital resistors 3,5 is incremented is stored in two registers, one for each of the digital resistors 3,5. These registers (POTBUF1 and POTBUF2) are used to hold the exact step number of each digital resistor which is directly proportional to the resistance value of each digital resistor and the gain of each of the input amplifiers 2,7. This enables microprocessor 50 to have complete control over the input gain of each input amplifier 2,7, by writing control signals to the digital resistors 3,5 through &#34;microprocessor write&#34; latch 8 and reading the logic states of of voltage comparators 28,29 through &#34;micrprocessor read&#34; buffer 26. 
     Microprocessor 50 then loads the latch 10 with the first &#34;automatic mode&#34; center frequency table value causing the digital variable oscillator 9,11,12 to output a 50 percent duty cycle square wave to the switched capacitor bandpass filter 13 clock input. The frequency output of the digital variable oscillator 9,11,12 sets the center frequency of the bandpass of the filter at its lowest value in the frequency domain within the limits of the apparatus to give the &#34;filter output rectifier&#34; 25 time to settle in case the automatic mode fundamental acquisition is chosen. 
     At this point of the initialization, the logic level of switch 35 is read through &#34;microprocessor read&#34; buffer 34 by microprocessor 50 to determine the mode of fundamental processing to take place (steps 71,72). If the automatic mode of fundamental processing is selected, microprocessor 50 will jump to a loop which reads the digitized value proportional to the input signal amplitude through &#34;microprocessor read&#34; buffer 26 until a value is read that indicates an applied input tone to the apparatus (steps 73,74). 
     If switch 35 is read through &#34;microprocessor read&#34; buffer 34 and the logic level that indicates the apparatus is to be used for manual mode fundamental acquisition processing (steps 71,72), microprocessor 50 will jump to the loop for input acquisition in the manual mode section of the program (steps 159,160,161,162,171,172, 173,175,176,177,174). First, microprocessor 50 will read the default value in the NOTEINC register and set the BLKDIS register to 00H to bypass the plus, minus, and the two seven segment portions of the display 65 (step 160). Microprocessor 50 will then send the display driver the segments to be displayed on the alphanumeric portion of the display 65 to indicate the note &#34;C&#34; (step 161). Microprocessor 50 will then read &#34;microprocessor read&#34; buffer 26 for a digitized value proportional to the input amplitude 162 and be put into a delay loop for the purpose of causing a blinking effect of the displayed note if the predetermined amplitude for input acquisition is not detected (step 171). The blinking effect for denoting the apparatus is waiting for input is started when the note indication on the display is cleared (step 172) by microprocessor 50 sending the data to the display driver 64 to blank the display 65. If momentary switch 36 is depressed (step 173), microprocessor 50 will increment the NOTEINC register that holds the note value for the display 65 (step 175) and again verify the logic level of switch 35 (step 177) to enable the user to switch back to automatic fundamental acquisition while in the manual mode fundamental acquisition input process. Microprocessor 50 is then put in another delay loop (step 174) to make the blinking effect on the display to appear uniform. Momentary switch 36 can be depressed for any length of time causing the display 65 to indicate all twelve notes at a rate of about one second per note because switch 36 is depressed. When the desired note to be processed in indicated on the display 65, releasing momentary switch 36 will cause the note indicated on the display 65 to remain displayed in a blinking manner indicating that there is currently no applied input to the apparatus. 
     FUNDAMENTAL ACQUISITION 
     Referring to FIGS. 1A-1C and 2A-2G, the automatic mode of fundamental acquisition begins when microprocessor 50 reads the digitized value proportional to the input amplitude through &#34;microprocessor read&#34; buffer 26 that indicates the predetermined input amplitude value for detection of an applied note or signal to the apparatus 74. Once the input is detected, the switch 37 (step 75) is read by microprocessor 50 through &#34;microprocessor read&#34; buffer 34 to determine which of the input amplifiers 2,7 requires gain adjustment through control of the digital resistors 3,5 to the optimum input gain for fundamental detection (step 76). The gain of the active input amplifier 2,7 is then adjusted by microprocessor 50 controlling the gain of the amplifier 2,7 by writing control signals to &#34;microprocessor write&#34; latch 8 and then reading the rectified D.C. voltage output by rectifier 15 proportional to the input amplitude presented to the analog-to-digital conversion circuitry 28,29 read through &#34;microprocessor read&#34; buffer 26 until the optimum amplitude is obtained for presentation to the switch capacitor bandpass filter 13 (step 76). 
     The automatic mode fundamental acquisition table pointer has been previously initialized in the initialization of the apparatus. The rest of the automatic mode acquisition consists of a loop (steps 76,77,78,79,80,81,82) in which consecutive table entries are loaded into the digital variable oscillator 9,10,11,12 to sweep the center frequency of the switched capacitor bandpass filter 13 in two percent increments of the frequency domain from the lowest center frequency in the table (A0-50) to consecutively upper center frequencies until it is determined that the fundamental has been passed over as described in the register definition section on the registers LITE1-LITE6. Once it has been determined that the center frequency has been passed over, the digital variable oscillator is loaded with center frequency table values in descending order until the amplitude of current center frequency under test is equal to the value stored in register BIGBUF which holds the value of the greatest amplitude of the center frequency tests (steps 83,84,85). At this point the switched capacitor bandpass filter 13 center frequency is placed directly over the fundamental of the input tone or signal. 
     The manual mode fundamental acquisition process begins with the detection of an applied input signal or tone by microprocessor 50 reading the digitized value proportional to the input amplitude indicating an applied input through &#34;microprocessor read&#34; buffer 26 (step 162). Microprocessor is then instructed to read the switch 37 which indicates the active input and adjusts the gain of the chosen input amplifier 2,7 through control of the digital resistor 3,5 to the optimum gain required by the switched capacitor bandpass filter 13 (step 163). Microprocessor 50 then reads the value of the NOTEINC register which holds the note value to be processed and determines the start of the manual mode fundamental acquisition table by incrementing a table pointer until the table pointer is at the start of the octave table which corresponds to the note value in NOTEINC 164. There are three table values for each of the nine octaves that are tested for each note value which provides for the testing of six percent of the frequency domain around the octave for the chosen note value. This relates to about two percent on either side of the chosen note value and the two percent of the frequency domain located directly over the octave. 
     Before each table value is loaded into the digital variable oscillator 9,10,11,12 the input amplitude gain is adjusted by microprocessor 50 so that the optimum amplitude for fundamental detection is always presented to the switched capacitor bandpass filter 13 so that each measurement is relative to the optimum input amplitude (step 165). The manual mode fundamental acquisition table is constructed so that the lowest center frequency values in the lowest octave are tested first and consecutive table entries are tested in a manner from lower to higher adjacent center frequencies in terms of the frequency domain. Fundamental detection is set up as a loop that tests the amplitude of a center frequency (step 167) and compares the detected value against the predetermined value for fundamental detection (step 169) and if the tested value is not within the limits of fundamental detection, the table pointer is incremented to the next higher center frequency table value (step 170) which, after the adjustment of the input gain 165, loads the next value into the digital variable oscillator 9,10,11,12. Once a center frequency of the switched capacitor bandpass filter 13 is determined to have sufficient amplitude for fundamental detection, the manual mode acquisition table value remains in the digital variable oscillator and octave, note and cent processing begins. When the table pointer indicates that it has reached the end of the table and none of the bandpass center frequencies possessed the amplitude required for fundamental detection, then the apparatus is restarted (step 168). 
     SYNCHRONIZATION OF THE INPUT PULSE CYCLES TO THE DIGITAL LOGIC 
     Referring to FIGS. 1A-1C and 4, the digitalized square wave output from voltage comparator 23 has no timing relationship to the twenty megahertz time base 39 that clocks the shift register 40 which is the synchronization mechanism between the two asynchronous sections of the apparatus. Besides being the synchronization mechanism between the time base oscillator 39 and the input pulse cycle, shift register 40 is used to guarantee the timing of the counting 57,59 and latching 56,58 circuitry. Since the twenty megahertz time base oscillator 39 has no timing relationship to the input pulse cycle, a method of synchronization is needed to reduce any possible timing errors between the two asynchronous timing periods and guarantee the digital counting and latching logic 56,57,58,59 in terms of the collected periods that the apparatus uses to determine pitch relative to perfect concert pitch as the standard for the basis of the accuracy presented to the user/operator of the apparatus. 
     The first problem to circumvent is the problem of metastability in the flipflop stages of the shift register 40. When the rising or falling edge of the input pulse cycle presented to the shift register 40 serial input is sufficiently close to the rising edge of the twenty megahertz time base oscillator 39 presented to the clock input of shift register 40, a condition arises in the first flipflop stage of the shift register where the flipflop output stage can be indeterminate or oscillating. This condition is known as metastability and requires that two serial flipflop stages be used to guarantee synchronization between two asynchronous pulse cycles because, upon the second rising edge of the time base oscillator 39, the setup time of the shift register 40 serial input is guaranteed and both flipflop stages will be stable. This requires that to develop guaranteed timing for the control signals presented to the digital clocking 45,46, counting 57,59, and latching 56,58 circuitry, the first two stages of the serial shift register 40 be unused. 
     To properly control the counting and latching circuitry 56,57,58,59 and to meet the guaranteed setup timing for the counters 57,59 and latching via latches 56,58 requires that all timing related to enabling the counters and latching the outputs of the counters be done relative to the falling edge of the gated ten megahertz clock produced from flipflops 45,46 and that a predetermined chain of events takes place upon the rising and falling edge of the input pulse cycle. To accomplish this there are delays associated with starting each section of the counting logic 57,59 and latching (via latches 56,58) of the count of each half cycle period. In addition to the delays there are synchronization errors associated with the setup time of the serial input of the shift register 40 to the rising edge of the time base clock 39 and the phase of the ten megahertz gated clock 45,46 when one input pulse half cycle periods is ending. Referring to FIG. 5 the different delays and error sources are depicted. Since these delays and errors are random in nature, the best and worst case scenarios need to be calculated so that an average value of the delays and errors can be used to reconstruct the correct total of the accumulated periods. Because of the random nature of the errors and delays and because of the relatively large sample of 32 input pulse half cycle periods used to calculate the pitch values, the average of the delays and errors can be added to the added sum of the sixteen pulse cycle periods that are used to calculate the pitch value. 
     PITCH VALUE PROCESSING 
     Referring to FIGS. 1A-1C and 2A-2G, in either mode of fundamental acquisition the process of the determination of the pitch value is the same. When the fundamental of the input tone or signal has been found and the bandpass of the switched capacitor bandpass filter 13 center frequency is placed over the fundamental frequency, determination of the octave, note and cent value can begin. 
     Microprocessor 50 is instructed to initialize the input pulse buffer pointer to the beginning of the pulse input buffer located in RAM 54, and the &#34;high priority&#34; input interrupts are enabled by microprocessor 50 writing 00H to the &#34;input interrupt enable/disable&#34; flipflop 42. Microprocessor 50 is then put in a one and one-half second timing loop which constantly checks the value of buffer register NOTESW which indicates that sixteen pulse cycle periods have been collected and added together along with the average synchronization delay and errors and put into a buffer from which the pitch of the note can be determined (steps 86,87,88,89,90). If the timing loop times out after one and one half seconds, then the apparatus will be restarted (step 91). 
     Once the input pulse buffer pointer has been initialized and the input interrupts enabled, the rising edge of the input pulse cycle will cause the interrupt flipflop 42 to be clocked &#34;low&#34; causing an interrupt exception to occur. Processing the &#34;high priority&#34; input pulse cycle exception will begin at location 0066H in ROM 52. Once inside the pulse cycle input exception the program counter, the accumulator, flag and index registers are pushed on to the stack in RAM 54 (steps 123,124). The &#34;high priority&#34; interrupt flipflop 42 is returned to the &#34;high&#34; state by microprocessor 50 writing a byte of 01H to disable the &#34;high priority enable/disable&#34; flipflop 41 (step 125). Then the latches 56,68 are read by microprocessor 50 and stored in RAM 54 at the locations pointed to by the pulse buffer pointer which is incremented each time a latch is read and stored in memory (steps 126-131). After reading the latches and storing the data in RAM 54, the pulse buffer pointer is compared against the predetermined value that indicates that eighteen pulse cycle periods have been collected (step 132). If eighteen pulse cycle periods have not been collected, then the index, flag, accumulator registers and the program counter are popped back from the stack and &#34;high priority interrupt enable/disable&#34; flipflop 41 is enabled so that the next pulse cycle can be stored in RAM 54 and normal processing will resume (steps 140, 141). If the count contained in the pulse buffer pointer indicates that eighteen pulse cycle periods have been collected, then the last sixteen pulse cycles will be added together along with the synchronization delays and errors and loaded into the register used to determine the pitch value of the sixteen pulse cycle periods (steps 133,134,135). Then the pulse buffer pointer is initialized to the beginning of the the pulse buffer and the register NOTESW is written with FFH to indicate that a pitch value is ready for processing and the input amplitude is adjusted though the digital resistor 3,5 to the optimum value used in note processing. All the registers stored on the stack are popped back into microprocessor 50 but the &#34;high priority&#34; input pulse cycle interrupts are left disabled until pitch processing begins at which time the &#34;high priority&#34; input pulse cycle interrupts are enabled so that while during the calculation of the octave, note and cent values and while during display update exceptions, pulse cycle periods can be collected (steps 136,137,138,139). 
     At the beginning of pitch processing the input pulse buffer might not be full so included at the start of pitch processing is a one and one-half second timing loop (steps 88,89,90,91) which reads the pitch value ready register NOTESW every ten milliseconds (step 89). If the value in the pitch value ready register NOTESW is equal to FFH, the timing loop is aborted and pitch processing begins. First, the &#34;high priority&#34; pulse cycle input interrupt is enabled (step 93) so that input pulse cycles can be collected while pitch value processing and display update exceptions are in progress and the pitch value ready register NOTESW is reset to 00H (step 92). This is the reason for the pulse input interrupts having the higher priority in the active processing of the apparatus, and time is saved in processing pitch if the pitch values can be collected while the apparatus is processing non-time-critical routines. 
     After enabling the input pulse cycle interrupts, the octave count register is initialized to a count of seven and the input value is compared to the last value in the pitch table consisting of 1200 entries (steps 94,95). If the input pitch value is less than the last entry in the pitch table, the pitch is higher than &#34;B8+50&#34; which is the highest tone or signal that the apparatus can process and the apparatus is restarted 96. Then the input pitch value is compared to the first entry in the pitch table 100. If the input pitch value is greater than the first entry in the pitch table, the input pitch value is divided by two and the octave value register decremented by one, the divided pitch value is presented to the first value in the pitch table again (steps 101,102,103,104). The pitch value is divided by two (step 103) and the octave value register is decremented by one (step 102) until the pitch value is less than or equal to the first table entry at which time the octave value has been determined and is stored (step 101). 
     The note value is found by initializing the pitch table pointer with the beginning address of the pitch table and adding 100 cents or pitch table entry locations to the pitch table pointer (step 105) and comparing the pitch table value 100 cents or entry locations to the input pitch value and incrementing the note value register from one by one and adding 100 cents or table entries to the pitch table pointer each time the input pitch value is greater than the pitch table value until a pitch value is found to be less than or equal to the input pitch value at which time the value in the note value register contains the note value of the input pitch value (steps 106,107,108,109,110). 
     The cent value is found by subtracting 100 cents or pitch table entries from the pitch table pointer 111 and incrementing the cent value register each time that the input pitch value is greater than the pitch table entry and then incrementing the pitch table pointer by one and comparing the input pitch value to each consecutive pitch table entry until a pitch table entry is found to be less than or equal to the input pitch value at which time the cent value register will hold the cent value of the input pitch value (steps 112,113,114,115,116). 
     Once the octave, note and cent values have been determined, they are stored in the correlation buffers MATCHB1-MATCHB3 until three input pitch values have been collected (step 117). Upon storing the third acquisition of input pitch values, the buffers are compared against each other to determine if the three input pitch values are within the predetermined tolerance (step 118). If the input pitch values are within the predetermined tolerance, then the cent values are averaged (steps 119,120) and placed along with the note value in the display buffers ABUF-ABUF+15 (steps 121,122). The DFLAG register is then written with 01H denoting that valid data is ready for display. If correlations between the three input pitch values are found to be out of tolerance, the input pitch values are discarded (step 118) and the DFLAG register is written with 02H. If the next acquisition of three input pitch values is determined again to be outside the predetermined tolerance, the DFLAG register is written with 03H and the apparatus will be restarted. 
     DISPLAY UPDATE PROCESSING 
     Referring to FIGS. 1A-1C and 2A-2G and the DFLAG, ABUF, BBUF, CBUF register descriptions, a 250 millisecond timer 43 is provided to present a &#34;low&#34; pulse to microprocessor 50 low priority interrupt input to initiate display update processing so that the displayed data can be easily visualized by the user/operator. In the manual mode the display update interrupts are disabled in the initialization process (step 59) so that the note values can be selected by momentary switch 36 and the timing loop can display that the apparatus is awaiting input as previously described. Once active input pitch value processing has begun the display update interrupts are enabled (step 86) so that the pitch values can be displayed as normal. In the automatic mode, display interrupts are enabled during the initialization process and only disabled during the averaging subroutine and again enabled immediately upon completion of the averaging subroutine. 
     When active pitch processing is underway and the DFLAG is equal to 01H, the register CENTCNT holds the number of valid pitch correlations stored in the display buffer ABUF-ABUF+15. When a display update interrupt request is presented to the microprocessor 50 (step 142) low priority interrupt input, microprocessor 50 pushes all the internal registers onto the stack 143 and reads the value of the CENTCNT register. Microprocessor 50 then averages all the display buffers with display data contained in them (step 152). Then, the averaged value is compared to the value of the LBUF register to determine if the current display data is within tolerance of the last displayed value as described in the description of the past history processing in the register definition of the register LBUF. 
     In order to display the octave, note and cent values, some additional processing is required to determine the segments on the display 65 that are sent to the display driver 64 to indicate the data correctly. First, the octave data can be sent without further processing from the octave value register to &#34;microprocessor write&#34; latch 60 and decoded by decoder 61 which will illuminate the correct LED indicating the octave value (step 158). The note value register is compared against the twelve possible note values, and the segments of the alphanumeric portion of the display 65 are sent to the display driver 64. Processing the cent value to be displayed requires additional processing to convert the cents value in hexadecimal to a positive or negative decimal value 156. 
     The first step in determining whether the hexadecimal cents value is positive or sharp, or negative or flat in relation to perfect concert pitch is to subtract 33H or 51 decimal from the hexadecimal cent value. The flag register in microprocessor 50 is tested and if the carry bit is set, the cent value will be negative or flat with respect to perfect concert pitch and the segments that drive the minus sign are written into the display driver 64. If the zero bit is set in the flag register of microprocessor 50, the apparatus detects that perfect concert pitch is applied and the segment data is sent to the display driver 64 to inhibit both the plus and minus indications. If the carry bit in the flag register of microprocessor 50 is not set, the cent value is positive or sharp with respect to perfect concert pitch and the segment data is sent to the display driver to drive the plus indication. 
     At this point the polarity of the pitch has been determined. The hexadecimal cent value must be converted to a decimal number indicating a positive value for sharp pitches that indicate the degree of sharpness of the pitch value in a positive ascending order from +1 to +50 and a decimal number indicating a negative value for flat pitches that indicate the degree of flatness of the input pitch value in a negative descending order from -1 to -49. The hexadecimal conversion of the cents value to a two digit decimal value is accomplished by first subtracting 33H or 51 decimal from the cent value and testing the carry bit in the flag register. If a carry bit is set in the flag register of microprocessor 50, a hexadecimal conversion to decimal numbering is required to indicate pitch in the negative direction. The result of the subtraction that caused the carry bit to be set also causes the accumulator to contain a value less than zero which causes the accumulator to roll over. If the carry bit is reset and the 2&#39;s complement is performed on the contents of the accumulator, a value results that provides a hexadecimal value in the negative direction of a positive value from 1 to 50 in the accumulator of microprocessor 50. Since the minus sign has already been sent to the display driver 64, the positive value is easily converted to a two digit decimal number. If the subtraction of 33H or 51 decimal from the hexadecimal cent value had not caused the carry bit or the zero bit to be set in the flag register of microprocessor 50, the number would be positive or sharp in relation to the zero cent value of 33H or 51 decimal. A positive or zero number resulting from the subtraction of the zero point or 33H or 51 decimal from the hexadecimal cent value can be directly converted to two decimal digits. 
     The hexadecimal conversion routine first finds the decimal equivalent of the most significant hexadecimal digit. This is accomplished by first storing the hexadecimal cent value in a register for later use and then storing the most significant hexadecimal digit in the least significant bits of a register and shifting the hexadecimal bits in the accumulator four times to the right which will now hold the most significant hexadecimal digit in the least significant bit locations of the accumulator. The accumulator and the register holding the most significant hexadecimal digit in the four least significant bit positions are then added together. A decimal adjust accumulator instruction is performed after each addition. This process is done fifteen times consecutively resulting in the decimal equivalent of the hexadecimal most significant digit. The original hexadecimal cent value that was stored for later use is then recalled from storage and the most significant digit is masked. The resulting decimal value from conversion of the most significant digit of the hexadecimal cent value is then added to the hexadecimal cent value of the least significant digit. The results of this addition are then decimal adjusted in the accumulator and a two digit decimal value results in the accumulator of microprocessor 50 which can be used to drive the display 65. 
     The two seven segment displays indicating the positive or negative decimal cent value are driven by first comparing the most significant decimal value in the accumulator of microprocessor 50 to the values one through five which, upon finding the correct comparison, will send the segment data to the display driver 64. A zero in the most significant digit position is suppressed so that the segment data sent to the display driver 64 for the most significant digit position will blank that portion of the display 65. After sending the most significant decimal digit segments to the display driver 64, the least significant decimal cent value in the accumulator of microprocessor 50 is compared against the values zero through nine which upon finding the correct comparison will send the segment data to the display driver 64 for the least significant decimal value to be displayed (step 157). After the indication of the cent value on the display 65, the update exception routine is terminated and normal active pitch processing resumes (step 158). 
     The following is a table of the values used to calculate the octave, note, and cent values from the sixteen added pulse cycle periods from the digital logic. ##SPC1## 
     The above description and the accompanying drawings are merely illustrative of the application of the principles of the present invention and are not limiting. Numerous other arrangements which embody the principles of the invention and which fall within its spirit and scope may be readily devised by those skilled in the art. Accordingly, the invention is not limited by the foregoing description, but is only limited by the scope of the appended claims.