Abstract:
A DSP (Digital Signal Processor) having a pipe line structure which is capable of decreasing the time required for storing a result of a computation. Data stored in a cache memory is output when an instruction input into a judging unit is a judged to be a computation instruction and when an address of the stored data is the same as a previously stored address in the judging unit. The cache memory temporarily stores data inputted through a decoder and is controlled by the judging unit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a memory control apparatus for a digital signal processor (DSP) having a pipeline structure, and in particular to an improved memory control apparatus for a digital signal processor having a pipeline structure which is capable of implementing a fast storing and computing operation by providing a cache memory for temporarily storing a data inputted through a decoder. 
     2. Description of the Background Art 
     FIG. 1 illustrates the construction of a conventional memory control apparatus for a digital signal processor (DSP) having a pipeline structure. As shown therein, the conventional memory control apparatus for a DSP having a pipeline structure includes a ROM (Read Only Memory)  40  for storing an execution program therein, a data storing block  30  provided with a plurality of RAMs (Random Access Memories) for storing a computation data therein, a decoder  10  for decoding an instruction INST and a data DATA and outputting a control code CTL, an address ADDR and a data DATA based on the decoding operation, and a memory management unit  20  for receiving the control code CTL, address ADDR and data from the decoder  10  and controlling an input/output operation of a data of the ROM  40 . 
     Differently from the common processor, since the digital signal processor performs a computation based on an accumulator and a product register, a result of the computation is frequently stored in the memory. Therefore, the DSP processor has a three-step pipeline structure as shown in FIG. 2 or a four-step pipeline structure as shown in FIG. 3 for enabling a high speed data processing operation. 
     The processor having a three-step pipeline structure is performed by the following steps: an instruction fetch (IF) step in which an instruction to be executed is read, a decoding (D) step in which the read instruction is decoded, and an execution (E) step. Since the data which is used during the computation operation should be generated between the decoding step and the execution step, it is impossible to enable a high speed operation which is required in an application algorithm, and in addition, since more than one clock signal is internally used, it is impossible to maintain a uniformity of a design. 
     Therefore, in order to overcome the above-described problems, a four-step pipeline structure including a step for reading data is mainly used. 
     The DSP processor adapting the four-step pipeline structure performs the following steps: an instruction fetch (IF) step, a decoding (D) step, an operand fetch (OF) step in which a data used for a computation is read, and an execution step (E). 
     The operation of the conventional apparatus in which the fourth step is executed will be explained. 
     The decoder  10  decodes an instruction inputted and transfers a control code CTL, an address ADDR and a data DATA to a memory management unit  20 , respectively, based on the decoding operation. The memory management unit  20  judges the control code CTL and activates a corresponding memory among an N-number of RAMs or ROM 40  of the data storing block  30 , or ROM  40  which corresponding memory is designated by the address ADDR. Therefore, a new data is stored into a corresponding memory, or the stored data is externally outputted through a data bus, so that an operation can be externally performed. 
     When an addition instruction is read in the instruction fetch (IF) step of the first pipeline line I of FIG. 3, and an addition operation is performed in the execution step (E), the operational result value is stabilized in the execution step (E). If a storing instruction is read in an instruction fetch (IF) step of a second pipe (II), the memory management unit  20  activates a memory designated by an address (ADDR) in a number N of RAMs or ROMs of the data storing block  30  during the operand fetch (OF) step, when a computation result value is stabilized. The computation result value is stored in the activated memory. The time when the operational result is stored into an accumulator or an accumulating register corresponds to the operand fetch (OF) step which is indicated by * as shown in FIG.  3 . In addition, the accumulator and accumulating register (not shown) are connected with the data bus BUS. 
     Since the time when the value from the accumulator or accumulating register is stabilized is later than the operand fetch (OF) step of the next instruction, namely, since the time when the data is stored is earlier than the time when the data to be stored is stabilized, one cycle is further needed so that the instruction is executed for storing the data. Therefore, in the operand fetch (OF) step (*), the data are not stored. Namely, the data are stored in the operand fetch (OF) step (**) of the third pipeline III. In addition, the addition operation after the storing step is performed in the operand fetch (OF) step (***) of the fourth pipeline IV. 
     Therefore, one cycle is further needed for a data computation. In addition, for the data storing operation, one cycle is further needed, so that two cycles are totally needed for the data storing operation, and thus the system operation is delayed due to the extended data storing time. 
     In the DSP in which a computation is performed based on the accumulator, since all computations are performed based on the accumulator or accumulating register, and there are many steps for storing the data, the delay time which occurs in the data storing step becomes an important factor by which the processing performance of the DSP is decreased. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a memory control apparatus for a digital signal processor (DSP) having a pipeline structure which overcomes the aforementioned problems encountered in the background art. 
     It is another object of the present invention to provide memory control apparatus for a digital signal processor having a pipeline structure which is capable of implementing a fast storing and computing operation by providing a cache memory for temporarily storing a data inputted through a decoder. 
     To achieve the above objects, there is provided a memory control apparatus for a digital signal processor (DSP) having a pipeline structure, including: a ROM (Read Only Memory) for storing an execution program therein; a data storing block composed of a plurality of RAMs (Random Access Memories) for storing data therein; a decoder for decoding an instruction and associated data and outputting a control code, address and the associated data; a memory management unit; a judging unit for comparing the control code and the address outputted from the decoder with a previously stored control code and address, respectively, outputting an enable signal if the compared addresses are the same based on the comparison, and outputting the previously stored control code and address to the memory management unit if the compared addresses are not the same; and a cache memory for storing the associated data from the decoder, outputting the stored data to the outside through a data bus in accordance with a logic state of the enable signal and outputting the stored data to the memory management unit; wherein the memory management unit receives the previously stored control code and address from the judging unit and the stored data from the cache memory and controls data transfer to and from the data storing block and ROM. 
     Additional advantages, objects and features of the invention will become more apparent from the description which follows. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: 
     FIG. 1 is a block diagram illustrating the construction of a conventional memory control apparatus for a digital signal processor (DSP) having a pipeline structure; 
     FIG. 2 is a view illustrating a conventional three-step pipeline structure; 
     FIG. 3 is a view illustrating a conventional four-step pipeline structure; 
     FIG. 4 is a block diagram illustrating the construction of a memory control apparatus for a digital signal processor (DSP) having a pipeline structure according to the present invention; 
     FIG. 5 is a view illustrating a four-step pipeline structure of FIG. 4; and 
     FIG. 6 is a flow chart illustrating an operation of a cache memory of FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 is a block diagram illustrating the construction of a memory control apparatus for a digital signal processor (DSP) having a pipeline structure according to the present invention. As shown therein, the constructions of the ROM  40 , the data storing block  30 , the decoder  10 , and the memory management unit  20  are identical to the conventional apparatus except the following elements. 
     First, a judging unit  50  compares a control code CTL and an address ADDR from the decoder  10  and previously inputted control code CTL′ and address ADDR′ and outputs an enable signal ES based on a result of the comparison, and outputs the previously inputted control code CTL′ and address ADDR′ to the memory management unit  20 . 
     A cache memory  60  stores a data DATA which is outputted from the decoder  10  and composed of one word length corresponding to a size for storing a data DATA outputted from the decoder  10 , and outputs the stored data DATA to the outside through the data bus or to the memory management unit  20 . 
     The judging unit  50  is composed of a flag region indicating a state that a data is stored in the cache memory  60 , a control code region in which a control code is stored, and an address region in which an address is stored. When the data is stored in the cache memory  60 , the flag of the flag region is set “1”. 
     The operation and effects of the memory control apparatus for a digital signal processor (DSP) having a pipeline structure according to the present invention will now be explained with reference to the accompanying drawings. 
     The decoder  10  decodes an instruction INST inputted, and outputs a control code and address ADDR obtained based on the decoding operation to the judging unit  50  and outputs the data DATA to the cache memory  60 . 
     The data DATA are stored in the cache memory  60 , and the judging unit  50  stores the control code CTL and address ADDR and judges whether the instruction from the decoder  10  is a storing instruction or a computation instruction, thus performing according to the flow chart shown in FIG.  6 . 
     If the inputted instruction is a computation instruction in Step S 1 , the judging unit  50  compares the address ADDR with the previously stored address ADDR′ in Step S 2 . As a result of the comparison, if both addresses ADDR and ADDR′ are identical, an enable signal ES is outputted so that the cache memory  60  outputs the stored data DATA′ to the outside through the data bus thereby in Step S 3 . As a result of the comparison, if the addresses ADDR and ADDR′ are different, the previously inputted control code CTL′ and address ADDR′ are outputted to the memory management unit  20  in Step S 4 . Thereafter, the memory management unit  20  activates a corresponding RAM among the N-number of RAMs of the data storing block  30 . 
     If the inputted instruction is a storing instruction in Step S 5 , the judging unit  50  judges whether the internal flag is “1”. If the flag is set to “1”, it means that a predetermined data is stored in the cache memory  60  in the storing step of the previous pipeline in Step S 6 . If the flag is 0, it means that no data is stored in the cache memory  60 . Therefore, the data DATA is stored into the cache memory  60 . 
     If the flag is set to “1”, it is compared whether the address ADDR and the previously stored ADDR′ are identical in Step S 7 . If both the addresses ADDR and ADDR′ are identical, the value stored in the cache memory  60  in the previous step is continuously maintained. If both the addresses ADDR and ADDR′ are different, the enable signal ES is outputted, and the data DATA′ stored in the cache memory  60  is outputted to the memory management unit  20  in Step S 8 . The data DATA inputted into the memory management unit  20  is stored in Step S 9 . 
     The operations of the judging unit  50  and cache memory  60  will be explained with reference to the accompanying drawings. 
     FIG. 5 is a view illustrating a four-step pipeline structure of FIG.  4 . 
     As shown therein, when a storing instruction is read in the instruction fetch (IF) step of the second pipeline II, the judging unit  50  recognizes the storing instruction from the control code CTL and stores the inputted address ADDR, and then the current flag is confirmed in Steps S 1 , S 5  and S 6 . The current flag is set to “1”, and the data DATA is stored in the cache memory  60 . The above-described operation is performed in the execution step (E) in Step S 9 . 
     Next, when the addition instruction is read in the instruction fetch (IF) step of the third pipeline III, the judging unit  50  judges whether the currently inputted address ADDR is identical with the address ADDR′ stored in the second pipeline II. As a result of the judgement, if both the addresses ADDR and ADDR′ are different, the control code CTL′ and address ADDR′ are outputted to the memory management unit  20  in Steps S 1 , S 2  and S 4 . In addition, if both the addresses ADDR and ADDR′ are identical, the enable signal ES is outputted, so that the data DATA′ stored in the cache memory  60  is outputted to the outside through the data bus BUS. The above-described step is performed in the operand fetch (OF) step (*) in Step S 3 . Here, the case that both the addresses ADDR and ADDR′ are identical denotes that the data stored in the second pipeline  11  are computed in the third pipeline III. 
     In the conventional art, since the data is not stored in the operand fetch (OF) step (*) of the second pipeline II shown in FIG. 3 but in the operand (OF) step (**) of the third pipeline III, the data stored in the operand fetch (OF) step (***) of the fourth pipeline IV is read. However, in the present invention, the data stored in the operand fetch (OF) step (*) of the third pipeline III in FIG. 5 is read. 
     Next, if the storing instruction is read in the instruction fetch (IF) step of the fourth pipeline IV, the judging unit  50  judges the flag. If the flag is set to “1”, the address ADDR and the previously stored address ADDR′ are compared in Step S 7 . As a result of the comparison, if both the addresses ADDR and ADDR′ are different, the enable signal ES is outputted, and a newly inputted data DATA is stored into the cache memory  60  in Step S 9 . The data DATA′ stored in the cache memory  60  is outputted to the memory management unit  20 . The above-described operation is executed in the execution step (E) in Step S 8 . The fourth pipeline IV denotes that a new data is stored. Therefore, a new data is stored in the cache memory  60 . The previously stored data is transferred to the memory management unit  20 . 
     As described above, in the conventional art, the stored data is stored into the RAM of the memory block, and after the accumulator or product register are stabilized, the stored data are used for a computation. However, in the present invention, the data are temporarily stored in the cache memory having a size of one word, and in the next step, the computation is performed, so that the data stored in the cache memory are outputted, and thus the delay time which is required for the storing operation is not necessary in the present invention. 
     Therefore, in the present invention, the processing capacity of the DSP is increased by decreasing the time which is required for storing a result of the computation. Furthermore, the shortening of the time which is required for the storing operation is very important for increasing the performance of the DSP. 
     In the present invention, the cache memory is separately configured. More preferably, the cache memory may be configured in the decoder  10  or the memory management unit  20 . 
     Although the preferred embodiment of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.