Abstract:
The present invention performs decoding of trellis coded modulated data using a conventional decoder by splitting up the tasks of estimating the uncoded portion and estimating the coded portion into separate tasks. The task of estimating the coded portion is performed based on a transformation on the input symbols and by taking advantage of the symmetry of the constellation associated with the modulated data when referencing a lookup table. The lookup table may also be designed to be smaller than a straight forward implementation by taking advantage of the same symmetry of the constellation. 
     The alteration of the data is then corrected for, resulting in a smaller constellation (Bi Phase Shift Key for 1 coded bit per symbol systems, Quadrature Phase Shift Key for 2 coded bits per symbol systems) mapping only the coded portion of the data. This allows a conventional Viterbi decoder to estimate the coded portion. The task of estimating the uncoded portion of the data is then performed by using information about the sector of the constellation of the original data along with a re-encoded version of the estimated coded portion.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a continuation-in-part of patent application Ser. No. 09/018,678, filed Feb. 4, 1998, now U.S. Pat. No. 6,101,626, and entitled, &#34;Method for choosing coding schemes, mappings, and puncturing rates for modulation/encoding systems&#34;, by inventors Robert Morelos-Zaragoza and Advait Mogre, assignors to LSI Logic Corporation, a Delaware corporation. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the decoding of modulated signals. More specifically, the present invention relates to decoding trellis coded modulated data using a conventional Viterbi decoder. 
     2. The Background Art 
     FIG. 1 is a block diagram illustrating a communications system having digital signal transmission and reception. A transmission portion of the system includes an encoder 10, a puncture module 12, and a modulator 14 providing a coded modulated signal at a communication channel 16. Similarly, a reception portion of the digital signal transmission and reception system includes a demodulator 18, a depuncturing module 20, and a decoder 22. 
     The encoder 10 may be a convolutional encoder. Convolutional codes typically include redundant symbols to increase the effective signal to noise ratio. In this manner, the probability of errors introduced during transmission is reduced. Standard convolutional coding techniques increase required bandwidth. However, some of the coded bits may be systematically removed in favorable channel conditions through a process called puncturing. 
     The encoder 10 is defined by the number of coded bits per symbol (CBPS) it produces as well as by its rate, which is defined as the ratio between the number of input bits to the number of output bits. For an encoder, the rate is equal to the number of input bits to the decoder divided by the number of output bits per symbol it produces. Thus, an encoder that takes a single bit and produces two coded bits has a rate of 1/2. The ratio is read inversely for the decoder, thus a decoder with a rate of 1/2 takes two coded bits and produces a single decoded bit. 
     The modulated signal includes an in-phase (I) component and a quadrature (Q) component. When the modulated signal is received, after conversion from an analog to a digital signal, each bit is demodulated into the in-phase and quadrature signal components by the demodulator 18 using sine and cosine functions. 
     The decoder 22 is typically a Viterbi decoder. Viterbi decoders allow the system to achieve most of the coding gain promised by a particular convolutional encoder. The rate and the number of coded bits per symbol of a decoder will match that of the corresponding encoder. In order to optimally perform the decoding, most Viterbi decoders are trellis Viterbi decoders (and the matching Viterbi encoders are trellis Viterbi encoders). A trellis Viterbi decoder operates on the received in-phase (I) and quadrature (Q) signals and processes them using a trellis diagram similar to that of the convolutional encoder. FIG. 2 depicts an example trellis diagram. The trellis diagram has two states 40 and two symbol epochs. The paths from state to state are determined by the bits of the data. Thus, in FIG. 2 there are two bits in the data, evidenced by the fact that there are two parallel paths at each state transition. In general, there are 2 k  paths out of and into a state, where k is the number of information bits. 
     A trellis diagram is read from left to right. Therefore, in order to determine the a values of the data bits, the trellis Viterbi decoder attempts to determine which states have been visited. FIG. 3 depicts the trellis diagram of data after it has been passed through the Viterbi decoder, which indicates the values of the data. The complexity of using the trellis Viterbi decoder system lies in the fact that there are parallel branches at each state transition. For example, in an 8-PSK system using 2 CPBS, there will be two branches at each state transisition (like the paths in FIGS. 2-3). Both of these paths represent the coded bit and each is determined by the uncoded bit. For each additional uncoded bit which is used, the number of parallel branches doubles. This increases the complexity in the implementation of these decoders. 
     The existence of parallel branches means that the number of data lines within the Viterbi decoder must be at least double what it would be without parallel branches (as in a conventional Viterbi decoder). This additionally leads to an increase in the size and cost of the trellis Viterbi decoder. Furthermore, more computational ability is required to process the code. Another drawback is that the memory associated with the Viterbi decoder used in the present invention (which stores a lookup table for computational purposes) must be bigger than in a conventional Viterbi decoder. 
     It is therefore an object of the present invention to provide a method of transforming the incoming symbols using a lookup table to allow decoding with a conventional Viterbi decoder. 
     It is a further object of the present invention to provide an architecture that allows for decoding of a trellis encoded sequence without using parallel branches. 
     It is a further object of the present invention to provide an architecture that allows for decoding of a trellis encoded sequence without using parallel branches using a conventional Viterbi decoder. 
     It is a further object of the present invention to provide a method for decoding trellis encoded data which requires less memory than previously required. 
     BRIEF DESCRIPTION OF THE INVENTION 
     The present invention performs decoding of trellis coded modulated data using a conventional decoder by splitting up the tasks of estimating the uncoded portion and estimating the coded portion into separate tasks. The task of estimating the coded portion is performed based on a transformation on the input symbols and by taking advantage of the symmetry of the constellation associated with the modulated data when referencing a lookup table. The lookup table may also be designed to be smaller than a straight forward implementation by taking advantage of the same symmetry of the constellation. 
     The alteration of the data is then corrected for, resulting in a smaller constellation (Bi Phase Shift Key for 1 coded bit per symbol systems, Quadrature Phase Shift Key for 2 coded bits per symbol systems) mapping only the coded portion of the data. This allows a conventional Viterbi decoder to estimate the coded portion. The task of estimating the uncoded portion of the data is then performed by using information about the sector of the constellation of the original data along with a re-encoded version of the estimated coded portion. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES 
     FIG. 1 is a block diagram illustrating a communications system having digital signal transmission and receiving. 
     FIG. 2 is a trellis diagram having two states and two paths at each state transition. 
     FIG. 3 is a trellis diagram showing a sample output of a trellis Viterbi decoder. 
     FIG. 4 is a diagram illustrating an 8-PSK contellation for 2 coded bits per symbol. 
     FIG. 5 is a diagtam illustrating an 8-PSK constellation for 1 coded bit per symbol. 
     FIG. 6 is a diagram illustrating a 16-PSK constellation for 1 coded bit per symbol. 
     FIG. 7 is a diagram illustrating a 16-PSK constellation for 2 coded bits per symbol. 
     FIG. 8 is a block diagram illustrating a decoder for use with an 8-PSK constellation and 2 coded bits per symbol in accordance with a presently preferred embodiment of the present invention. 
     FIG. 9 is a block diagram illustrating the coset constellation mapping block of FIG. 6 in greater detail 
     FIG. 10 is an example of a lookup table as known in the prior art. 
     FIG. 11 is an example of a lookup table designed for use with the present invention. 
     FIG. 12 is a diagram depicting a received point in an 8-PSK constellation with 2 coded bits per symbol. 
     FIG. 13 is a diagram depicting a modified received point in an 8-PSK constellation with 2 coded bits per symbol, before reading from a lookup table. 
     FIG. 14 is an example of a table suitable for use with both the memory address generating task and the correction tasks of the present invention. 
     FIG. 15 is an example of a transformed received point in the QPSK constellation generated by the lookup table in accordance with a presently preferred embodiment of the present invention. 
     FIG. 16 is an example of a coset select table, which is used to determine the value if an uncoded bit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons. 
     In a trellis coded modulation system with 2 coded bits per symbol, a certain type of symmetry occurs where, for a 2 m  -PSK constellation, the signal points can be grouped into subsets, each of which is a symmetric 2.sup.(m-2) constellation having a fixed rotation between each point in the subset. For example, the 8-PSK constellation of FIG. 4 may be grouped into four distinct subsets. The first subset contains points (000, 100). The second subset contains points (001, 101). The third subset contains points (011, 111) and the fourth subset contains points (010, 110). For 1 coded bit per symbol, if a mapping is chosen such that the least significant bit alternates between neighboring signal points, then a similar symmetry occurs. An example of this is depicted in FIG. 5, where it can be seen that the least significant bit alternates between neighboring points so this mapping would exhibit this symmetry. 
     The same symmetry can be seen in the 16-PSK constellation with 2 coded bits per symbol shown in FIG. 6. The constellation depicted in FIG. 6 may be grouped in four distinct subsets. The first subset contains points (0000, 0100, 1100, 1000), the second subset contains points (0001, 0101, 1101, 1001), the third subset contains points (0011, 0111, 1111, 1011) and the fourth subset contains points (0010, 0110, 1110, 1010). The primary features of these four subsets are that the phase rotation between each point in each subset is identical (90 degrees) and that the coded bits (the two least significant bits) are identical for each point in each subset. If there is one coded bit per symbol, as depicted in FIG. 7, then the symmetry occurs because the least significant bit (the coded bit, shown by the underline underneath the number) is the opposite of each of its neighbors. 
     By utilizing this symmetry, it is possible to design a system which folds the original constellation into a much smaller constellation consisting of only the coded bits, allowing a conventional Viterbi decoder to decode the signal bits. For 1 CBPS systems, the constellation is converted to Bi Phase Shift Keyed (BPSK). For 2 CPBS systems, the constellation is converted to Quadrature Phase Shift Keyed (QPSK). The uncoded bits may then be determined later by using the estimated coded bits along with information regarding the sector of the original signal to estimate the uncoded bits. This two-stage decoding process allows for a much cheaper and smaller decoder to be used. 
     By separating the two portions, it is possible to use a standard Viterbi decoder within a trellis encoded system. Additionally, since only a portion of the constellation needs to be used in referencing the lookup table, the present invention also allows for the use of a much smaller lookup table than would otherwise be required. 
     FIG. 8 is a block diagram illustrating a decoder for use with an 8-PSK constellation and 2 coded bits per symbol in accordance with a presently preferred embodiment of the present invention. The invention may be used in systems with other constellations and coded bits per symbol rates as well, requiring only minor modifications as will be readily apparent to those of ordinary skill in the art. Coset constellation and sector mapping block 50 has two inputs, I --  IN 52 and Q --  IN 54, and three outputs, I --  OUT 56, Q --  OUT 58, and sector 60. I --  IN 52 and Q --  IN 54 are the I and Q components of the demodulated signal and may be mapped in a constellation. Coset constellation and sector mapping block performs a transformation on I --  IN 52 and Q --  IN 54 to produce I --  OUT 56 and Q --  OUT 58, which are components of a signal point in a simpler coset constellation. Coset constellation and sector mapping block also uses I --  IN 52 and Q --  IN 54 to determine the sector 60 of the constellation in which the original signal lies. 
     Viterbi decoder 62 receives I --  OUT 56 and Q --  OUT 58 and performs a standard Viterbi decoding of the components, resulting in an estimation of the coded portion of the data 64. This estimated coded portion 64 is also used to estimate the uncoded portion. Encoder 66 receives the information and re-encodes it, sending the coset output 68 to an intra-coset selector 70. Intra-coset selector 70 uses the re-encoded information along with the sector information 60 to estimate the uncoded bit or bits. A sector delay 72 may have to be placed between the coset constellation and sector mapping block 50 and the intra-coset selector 70 so that the re-encoded coset information 68 reaches the intra-coset selector 70 at the same time as the sector information 60. The output of the circuit is an estimation of both the coded and uncoded portions. 
     FIG. 9 depicts the coset constellation mapping block 50 of FIG. 6 in greater detail. A splitter block 100 splits the bits of I --  IN 52 and Q --  IN 54 into constituent sign bits, I --  SIGN 102 and Q --  SIGN 104, and value bits, I --  ABS 106 and Q --  ABS 108. For example, in some systems, I --  IN 52 and Q --  IN 54 are each 6 bits long. The first bit in each represents the sign (positive or negative) of the value and the other 5 bits represent the absolute value. Thus, in this example, L --  SIGN 102 and Q --  SIGN 104 are each 1 bit long, while I --  ABS 106 and Q --  ABS 108 are each 5 bits long. 
     I --  SIGN 102, Q --  SIGN 104, I --  ABS 106, and Q --  ABS 108 are all used as inputs to a memory address generator and sector calculation block 110, which functions to generate an address to look up in memory 112. Memory 112 contains a lookup table of memory address and corresponding output values, I --  OUT&#39; 114 and Q --  OUT&#39; 116. FIG. 10 depicts a portion of a typical lookup table as used by the prior art to determine the coded bits. As can be seen, it is normally addressed using the sign and value bits of the I component concatenated with the sign and value bits of the Q component. Thus the table has 2 n  entries where n is the total number of bits for both the I and Q components. For typical systems having 6 bits for each component, the table then has 2 12  entries, or 4096 entries. For 1 coded bit per symbol systems, the output of the table is (I --  OUT, sector). 
     For the present invention, the lookup table need only be indexed using the value bits of the I and Q components, without using the sign bits. FIG. 11 depicts a portion of such a lookup table. By eliminating the sign bits, the table is reduced in size by a factor of 4 (the table now has only 2 10 , or 1024 entries). These figures are assuming an 8-PSK system with 2 coded bits per symbol. The factor of reduction may be different in different systems as would be apparent to those of ordinary skill in the art. 
     Because the sign bits are no longer used to index the lookup table, however, a memory address generator (located in the memory address generator and sector calculation block 110) must be used to determine the proper output. In essence, this block maps the original point to a comparable point in the first quadrant of the constellation. This may involve swapping the I --  IN 52 and Q --  IN 54 values. Since the sign bits are not used in indexing the lookup table, there is no need to negate the values as might otherwise be required. The determination of whether or not to swap the values is made by examining the I --  SIGN 102 and Q --  SIGN 104 bits along with the I --  ABS 106 and Q --  ABS 108, which together indicate the sector in which the original signal lies. For example, in an 8-PSK system, if I --  SIGN is positive, Q --  SIGN is negative and I --  ABS&gt;Q --  ABS, then the original signal lies in sector 7. A fixed table may then be referenced which indicates whether or not swapping is necessary based on the sector. These new values are then used as the address to reference the lookup table. 
     The lookup table then gives corresponding I --  OUT&#39; 114 and Q --  OUT&#39; 116 values for the point. The lookup table essentially performs a transformation of the incoming components. Generically, the transformation can be defined as follows. In any 2 m  -PSK trellis coded modulation system, for v=1, 2 where v is the number of coded bits per symbol: ##EQU1## and Φ is a constant phase rotation of the constellation. This converts any 2 CBPS constellation to a QPSK constellation and any 1 CBPS constellation to a BPSK constellation. 
     The I --  OUT&#39; 114 and Q --  OUT&#39; 116 values may need to be corrected in a symmetry block 118, which produces corrected values I --  OUT 52 and Q --  OUT 54. The symmetry block 118 receives the I --  SIGN 102, Q --  SIGN 104, I --  OUT&#39; 114, and Q --  OUT&#39; 116 values determines whether the I --  OUT&#39; and Q --  OUT&#39; values need to be negated (i.e. I --  OUT=-I --  OUT&#39;, Q --  OUT=-Q --  OUT&#39;). Again, a fixed table may be used in determining the need for negation, but here all that is required to determine the need for negation is the quadrant of the original signal using the sine and cosine symmetry. If the original signal was in the fourth quadrant (I --  SIGN&gt;0 and Q --  SIGN&lt;0), then when it was mapped to the first quadrant the Q component was negated. Thus it will be necessary to negate the Q component in the symmetry block to correct for the earlier negation. In essence, this is performing a phase rotation depending on the specific locations of the points of the constellation. 
     Referring back to FIG. 8, intra-coset selector 70 receives the re-encoded coset values 68 from the encoder 66 as well as the sector 60 from the coset constellation and sector mapping block 50. It then references a table which tells it the value of the uncoded bit based on the coset values and sector. This block is essentially examining the possible points in the constellation based on the coset values, and then picking the point closest to the sector received from the coset constellation and sector mapping block 70 
     An example of the action of the present invention for an 8-PSK constellation with 2 coded bits per symbol is provided as follows. This example is for a system with a rate=1/2 encoding scheme. FIG. 12 depicts an 8-PSK constellation. The sectors have been numbered from 0 to 7. The received signal 120 is shown in sector 7 of the constellation in FIG. 12. I --  IN and Q --  IN components are received by the decoder. These are input to the coset constellation and sector mapping block. Since the received signal is located in sector 7, then I --  IN will be positive and Q --  IN will be negative. Then, the splitter block in the coset constellation and sector mapping block separates the signal bits from the absolute value bits, and passes them all to memory address generator and sector calculation block. The absolute value bits are used to look up the appropriate entry in the lookup table, which is only indexed by value bits. The memory address generator and sector calculation block, however, first maps the point (and every input point) to a point in the first quadrant of the 8-PSK constellation (here, sector 7 maps to sector 1). Thus, FIG. 13 depicts the 8-PSK constellation with the point used for the lookup table. This point may be generated using a table similar to that depicted in FIG. 14. The table in FIG. 14 is read as follows. First, the sector of the original input point is referenced (here, sector 7). The lookup addresses are then computed by concatenating the I --  ABS and Q --  ABS values in the order they appear in the table entry for that sector (here, sector 7 has Q --  ABS, I --  ABS thus the lookup address is Q --  ABS | I --  ABS). 
     The lookup table then is used to produce a transformation on both the received symbols and the constellation, resulting in the QPSK constellation of FIG. 15, with the point still in sector 1, but sector 1 now appearing in the second quadrant rather than the first. The problem now is that the point needs to be rotated to properly indicate the value of the coded bit (I --  OUT&#39; and Q --  OUT&#39; may not be correct). This can be performed using the table from FIG. 14. Again, the table is read in the same way, but now the I --  OUT&#39; and Q --  OUT&#39; may need to be negated to arrive at corrected values I --  OUT and Q --  OUT. In the present example, it will be necessary to negate both I --  OUT and Q --  OUT to correct for the mapping of the point from sector 7 to sector 1. 
     Then the I --  OUT and Q --  OUT values may be passed to the Viterbi decoder, which estimates the coded bit. This uncoded coded bit is then re-encoded and passed to the intra-coset selector. The sector (in the present case, sector 7) was computed in the memory address generator and sector calculation block of the coset constellation and sector mapping block. The coset values are then used along with the sector information to estimate the uncoded bit. This step may be performed using a table similar to that in FIG. 16. 
     Referring back to FIG. 12, the original point 120 was located near label &#34;110&#34;, so one might assume that the uncoded bit for that point should be estimated to be 1. However, it is possible that the Viterbi decoder found an error in the transmission and actually predicted the coded bits to be, for example, 01 rather than 10. In such a case, the table in FIG. 16 is used to determine which label the original signal was supposed to be closest to, label &#34;001&#34;, or label &#34;101&#34;. According to the table in FIG. 17, sector 7 with a coset of 01 results in an uncoded bit of 0. Referring back to FIG. 12, one can see how this is the case, since sector 7 is closer to label &#34;001&#34; than to &#34;101&#34;. 
     While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.