Abstract:
An electronic system includes a feedback voltage regulator circuit including input terminals receiving an alternating input voltage signal and a feedback input terminal receiving a feedback voltage that is generated based on a load current through an electric load. A sensing element senses the load current through the electric load and generates and sensed voltage based upon the sensed load current. A current transducer receives the sensed voltage provides the feedback voltage based upon the sensed voltage. A current generator receives the alternating input voltage signal and provides a biasing current signal that is a function of the alternating input voltage signal to modulate the feedback voltage on the feedback input terminal based upon the alternating input voltage signal.

Description:
BACKGROUND 
     Technical Field 
       [0001]    The present disclosure relates to a biasing and driving circuit, based on a feedback voltage regulator, in particular a switching-mode power supply (SMPS), for an electric load. 
       Description of the Related Art 
       [0002]      FIG. 1A  shows a driving circuit for light-emitting diodes (LEDs), which is designated by the reference  1  and in particular includes a voltage regulator  5  of an SMPS type configured to operate as constant-current source and adapted to supply a string of LEDs  2  (illustrated in  FIG. 1A  is just one LED  2 , coupled between output supply pins, V LED   + and V LED   − ). The SMPS device  5  is of a per se known type, for example described in the datasheet of the product “LED5000” manufactured by STMicroelectronics, entitled “LED5000—A monolithic step-down current source with dimming capability”, September, 2014. 
         [0003]    The SMPS device 5 is operatively coupled to input supply terminals V IN   +  and V IN   − , present between which is a voltage V IN , for example generated by an electronic transformer (not illustrated). 
         [0004]    The SMPS device  5  has, in a known way, a plurality of operating terminals, and in particular: a supply terminal  1   a , adapted to receive an input voltage V IN , having a value, for example between 5.5 and 48 V; a reference terminal  1   b , which forms a reference-voltage terminal; a feedback input terminal  1   c , which is coupled to the sensing resistor  4  and constitutes the inverting input of an error amplifier internal to the SMPS device  5  (regulation terminal); a terminal  1   d , which provides a power-supply connection for the internal analog circuitry; a terminal  1   e , which forms, together with the reference terminal  1   b  and with the error amplifier, the output of a regulation loop internal to the SMPS device  5 ; and a terminal  1   f  that implements an output terminal for switching the SMPS device  5  and is coupled to the terminal  1   d  via a capacitor  8 . 
         [0005]    As illustrated in greater detail in  FIG. 1B , the regulation loop internal to the SMPS device  5  includes the voltage-error amplifier  3 , which implements a first stage of the regulation loop. In particular, the voltage-error amplifier  3  is a transconductance operational amplifier, the non-inverting input of which is connected to a voltage reference V REF  internal to the SMPS device  5  (variation of which is typically between 194 and 206 mV; in particular, a typical value of 200 mV in closed loop is considered in what follows), whereas the inverting input terminal is connected to a sensing resistor  4 . The inverting input terminal of the voltage-error amplifier  3  forms a feedback input terminal  1   c  of the SMPS device  5 . The voltage-error amplifier  3  generates, on the terminal  1   e , a control signal V CONTROL , which is supplied to the non-inverting input of a PWM comparator  7 , which, in turn, drives, on the terminal  1   f , the high-side (HS) switch of a DC-DC converter  9 ′. A current detector  9 ″ detects the current circulating in the high-side (HS) switch and supplies the value detected (transduced) to the inverting input of the PWM comparator. 
         [0006]    The DC-DC converter  9 ′ generates at output a regulation signal V SW  having a duty cycle such as to regulate the supply current OLEO appropriately. 
         [0007]    In other words, present between the terminal  1   a  and the terminal  1   f  is an SMPS converter, wherein the non-inverting input of the error amplifier acts on the terminal  1   c , and the output of the amplifier acts on the terminal  1   e.    
         [0008]    Thus, with reference to  FIG. 1A , the SMPS regulator  5 , the inductor  6  and the diode  11  form, for example, a DC-DC converter topology of a boost type. 
         [0009]    The regulated current level supplied at output from the SMPS device  5  is thus set, or regulated, on the basis of the current that flows through the sensing resistor  4 , across which, according to what has been said, there may be noted a voltage drop equal to the reference V REF  of 200 mV. The resistance value R S  of the sensing resistor  4  is consequently given by R S =(200mV)/I LED , where I LED  is the current that flows through the string of LEDs  2 . In a case provided by way of example, where I LED =1A, we have R S =0.2 Ω. 
         [0010]    Coupled to the terminal  1   c  of the SMPS device  5  a resistor  26  is further present, having a resistance R 1  of approximately 10 kΩ. Optionally, it is possible to insert a Zener diode (not illustrated) in parallel to the resistor  26  so that the resistor  26  and the Zener diode implement a protection from overvoltages. The effect of the resistor  26  is negligible in so far as the current at input to the terminal  1   c  is substantially zero, or negligible (at the most a few tens of nanoamps). 
         [0011]    Furthermore, coupled to the terminal le are a resistor &#39;and a capacitor  15 , connected together in series, which have the function of implementing a compensation network for the regulation loop. By way of example, the resistor  13  has a resistance of 22 kΩ and the capacitor  15  has a capacitance of 10 nF. 
         [0012]    It is evident that the SMPS device  5  may include further input/output terminals, for implementing further functions, as required. 
         [0013]    The input capacitor  10 , coupled to respective supply inputs of the SMPS device  5 , is configured to withstand the maximum operating input voltage and the maximum mean square value of the current. Capacitors adapted for this purpose, available for use for a wide range of currents, are, for example, electrolytic capacitors, ceramic capacitors, tantalum capacitors. 
         [0014]    An output capacitor  12 , coupled between the input V IN   +  and the reference terminal  1   b , has the function of filtering the current ripple of the diode  11 , which, given a specific application and an output current, depends upon the value of inductance of the inductor  6 . In general, if ΔI L  is the current ripple of the inductor  6  and I L  the average current that flows through the inductor, the value of inductance L is chosen in such a way that (ΔI L /I L )&lt;0.5. 
         [0015]    The driving circuit  1  may be coupled, as has been said, to an electronic transformer, which generates the input voltage V IN . Electronic transformers of a known type are typically based on a self-oscillating circuit and, to operate properly, require a load of a resistive type. In other words, the driving circuit  1  must be seen, by an electronic transformer coupled to the inputs V IN  and V IN   − , as a resistive load. However, it is known that an SMPS device, for example of the type illustrated in  FIG. 1A  and described with reference to that figure, in the absence of further arrangements, is seen as a load with negative impedance and thus is not optimized to be coupled to the output of an electronic transformer that requires a resistive load for its proper operation. 
         [0016]    To overcome this drawback, it is known in the art to use a current control of the input signal. See, for example, Application Note 5372, “MR16 LED Driver Makes MR16 LED Lamps Compatible with Most Electronic Transformers” by Suresh Hariharan, Mar. 27, 2013, Maxim Integrated Products. A similar solution is discussed in the datasheet of the product MAX16840, manufactured by Maxim Integrated Products, Inc., “LED Driver with Integrated MOSFET for MR16 and Other 12V AC Input Lamps”. 
         [0017]    In this technical solution, represented schematically in  FIG. 2 , the voltage on the sensing resistor  4  is regulated at each switching cycle, exploiting a reference circuit  18  external to the SMPS device  5 , adapted to supply a voltage signal V REFI  to a further input terminal  1   g  of the SMPS device  5 , for the purpose of setting the input current level by appropriately controlling the voltage on the terminal  1   c . In other words, when the voltage V REFI  present on the terminal  1   g  drops below a certain threshold value, the input current (voltage on the resistor  4 ) is regulated proportionally to the value assumed by the voltage V REFI  on the terminal  1   g . Instead, when the voltage V REFI  present on the terminal  1   g  exceeds the threshold value, then the input current (voltage on the resistor  4 ) is set at a predefined fixed value. The voltage on the sensing resistor  4  is thus regulated as a function of the voltage V REFI  received at input on the terminal  1   g , which is in turn a function of the input voltage V IN . This type of modulation of the voltage on the terminal  1   c  enables simulation of a resistive load, seen by an electronic transformer coupled to the input of the driving circuit  1  of  FIG. 2 . However, this implementation requires a terminal of the device  5  (terminal  1   g ) explicitly dedicated to this purpose, a circuitry internal to the device  5  adapted for regulating the voltage on the terminal  1   c  as a function of the reference on the terminal  1   g , as well as, at the same time, an external circuit for generating the reference signal to be supplied to the terminal  1   g . In other words, this solution is not applicable to any generic SMPS device; the latter, instead, must be purposely built. 
         [0018]    Other known solutions require provision of dedicated dual-stage converters, with consequent implementation of double inductive components, which increase the costs and size. 
         [0019]    There is thus a need to provide a driving circuit for a voltage regulator, for example of an SMPS type, that is adapted to emulate a resistive load when seen from the input terminals V IN   +  and V IN   − , is such as to increase the power factor, with lower production costs and reduced occupation of space, and is able to operate with any generic voltage regulator. 
       BRIEF SUMMARY 
       [0020]    In one embodiment, a circuit includes input terminals configured to receive an alternating input voltage signal and configured to supply an output voltage signal to an electric load. The circuit is configured to generate a biasing current signal that is a function of the alternating input voltage signal and is configured to supply the biasing current signal to a feedback input of a feedback voltage regulator to modulate a feedback voltage signal generated on the feedback input. 
         [0021]    In another embodiment, an electronic system includes a feedback voltage regulator circuit including input terminals receiving an alternating input voltage signal and a feedback input terminal receiving a feedback voltage that is generated based on a load current through an electric load. A sensing element senses the load current through the electric load and generates and sensed voltage based upon the sensed load current. A current transducer receives the sensed voltage provides the feedback voltage based upon the sensed voltage. A current generator receives the alternating input voltage signal and provides a biasing current signal that is a function of the alternating input voltage signal to modulate the feedback voltage on the feedback input terminal based upon the alternating input voltage signal. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0022]    For a better understanding of the present disclosure, some embodiments thereof will now be described, purely by way of non-limiting example and with reference to the annexed drawings, wherein:  FIG. 1A  illustrates a biasing and driving circuit for a string of LEDs, according to an embodiment of a known type; 
           [0023]      FIG. 1B  illustrates a regulation loop internal to an SMPS device that forms part of the biasing and driving circuit of  FIG. 1A ; 
           [0024]      FIG. 2  illustrates a biasing and driving circuit for a string of LEDs, according to a further embodiment of a known type; 
           [0025]      FIG. 3  illustrates a biasing and driving circuit for a string of LEDs, according to one embodiment of the present disclosure; 
           [0026]      FIG. 3 a    illustrates the circuit of  FIG. 3  with an additional biasing circuit that improves the behaviour of the circuit of  FIG. 3  according to another embodiment of the present disclosure; 
           [0027]      FIG. 4  illustrates a circuit implementation of the biasing and driving circuit of  FIG. 3 , according to an embodiment of the present disclosure; 
           [0028]      FIG. 4 a    illustrates a circuit implementation of the biasing and driving circuit of  FIG. 3 a   , according to an embodiment of the present disclosure; 
           [0029]      FIGS. 5A-5H  show electrical signals during operating steps of the biasing and driving circuits of  FIGS. 4 and 4   a;    
           [0030]      FIG. 6  illustrates a further circuit implementation of the biasing and driving circuit of  FIG. 3 , according to a further embodiment of the present disclosure; 
           [0031]      FIG. 6 a    illustrates a further circuit implementation of the biasing and driving circuit of  FIG. 3 a   , according to a further embodiment of the present disclosure; 
           [0032]      FIG. 6 b    illustrates a still further circuit implementation of the biasing and driving circuit of  FIG. 3 a   , according to yet another embodiment of the present disclosure; and 
           [0033]      FIG. 7  illustrates, in greater detail, the biasing and driving circuit of  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION 
       [0034]      FIG. 3  shows, according to an embodiment of the present disclosure, a biasing and driving circuit  20  for a string of LEDs, comprising a switching-mode power-supply (SMPS) device  5 , configured to operate as constant-current source and adapted to supply the string of LEDs  2  (illustrated by way of example in  FIG. 3  is just one LED  2 ). Elements of the driving circuit  20  that are common to those of the driving circuit  1  of  FIG. 1A  are designated by the same reference numbers and are not described any further. 
         [0035]    The driving circuit  20  further includes a current generator  22 , operatively coupled to the terminal  1   c  of the SMPS device  5 , configured to supply on the terminal  1   c  of the SMPS device 5 a current signal I 1  of an alternating current (a.c.) type, in particular a sinusoidal signal. According to one aspect of the present disclosure, the bandwidth of the regulation loop internal to the SMPS device  5 , illustrated in  FIG. 1B , is greater than the maximum frequency of the current signal I 1 , for example greater by one or more orders of magnitude. For instance, the bandwidth of the regulation loop of  FIG. 1B  is 10 kHz, and the frequency of the current signal I 1  (e.g., a sinusoidal signal) is 100 Hz. 
         [0036]    The resistor  26 , having a resistance R 1  with a value of approximately 10 kΩ, is adapted to receive the current signal I 1 , modulating the voltage drop on the sensing resistor  4 . The output terminal of the current generator I 1  is coupled between the terminal  1   c  and the resistor  26 , and the reference terminal of the current generator, instead, is coupled to the input terminal V IN   + . The terminal  1   c  is a high-impedance terminal, and consequently (to a first approximation) the current signal I 1  flows entirely through the resistor 26 and not towards the terminal  1   c.    
         [0037]    The current L ED  that flows through the sensing resistor  4  is, thus, given by: 
         [0000]    
       
         
           
             
               I 
               LED 
             
             = 
             
               
                 
                   V 
                   FB 
                 
                 - 
                 
                   ( 
                   
                     
                       I 
                       1 
                     
                     · 
                     
                       R 
                       1 
                     
                   
                   ) 
                 
               
               
                 R 
                 S 
               
             
           
         
       
     
         [0000]    where V FB  is the feedback voltage present on the terminal  1   c  in closed loop (in the example considered previously, equal to 200 mV) and I 1 ·R 1  is the voltage contribution generated by the resistor  26  in the presence of the current signal I 1  supplied by the generator  22  (R 1  is here chosen by way of example equal to 10 kΩ). In other words, V FB −(I 1 ·R 1 ) is the voltage across the sensing resistor  4 . 
         [0038]    From the foregoing equation, it is evident that, in the absence of the current signal I 1  (i.e., I 1 =0 A), the current I LED =V FB /R S  circulating in the string of LEDs  2  and in the sensing resistor  4  is determined only by the internal reference V REF  (reference of the error amplifier on the feedback terminal  1   c  of the SMPS regulator  5 ). Instead, in the presence of the current signal I 1 , the current circulating in the LEDs  2  depends upon the voltage drop across the resistor  26 . In particular, for example with I 1 =20 μA, i.e., I 1 ·R 1 =200 mV, the current I LED =(V FB −(I 1 ·R 1 ))/R S  circulating in the string of LEDs 2 and in the sensing resistor  4  is zero. 
         [0039]    The voltage drop on the resistor  4  as a result of the current signal I 1  is considered negligible. 
         [0040]    By what has been said herein, it may be noted that, in the absence of the current signal I 1 , the current I LED  has a substantially constant value, and the load seen by an electronic transformer, in these conditions, has a negative impedance. 
         [0041]    Instead, in the presence of the current signal I 1 , the current circulating in the LEDs  2  that traverses the sensing resistance  4  is modulated in such a way that the load seen by the electronic transformer resembles a resistive load. 
         [0042]    The present applicant has found that, to emulate a resistive load, it is expedient for the current signal I 1  to assume values inversely proportional to the respective values assumed by the input signal V IN . In other words, the current signal I 1  has a time plot 180° phase-shifted with respect to the time plot of the input voltage signal V IN . 
         [0043]    The current signal I 1  that implements what has been described above is generated by a signal-generating circuit illustrated in  FIG. 4 . 
         [0044]    In  FIG. 3 a   , an additional biasing circuit named a current holder circuit (CH) is shown. This circuit CH connects a resistor R CURR   _   HOLD  between the terminal VIN+ and VIN− when the current I 1  from current generator  22  is higher than a certain value, so that the electronic transformer providing the voltage V IN  is loaded also when the current requested by the voltage regulator  5  is very low (i.e. when a rectified input voltage VIN_R (see  FIG. 4 ) is at its minimum and current I 1  is at its highest value). The present applicant has found that the current holder circuit CH further improves the emulation of a resistive load, since it loads the electronic transformer providing the voltage V IN  with an adequate resistor when the current signal I 1  is at its maximum, i.e. when the voltage regulator  5  of the SMPS type is absorbing zero current from the electronic transformer. Moreover, the current holder circuit CH sustains the electronic transformer switching activity during the light load phase, so that the current generator  22  is properly biased on the beginning of every power line cycle. 
         [0045]    With reference to  FIG. 4 , the generator  22  includes a rectifier input stage  30 , for example obtained by a diode bridge  31 - 34 , configured to receive the input voltage V IN  (a.c. signal) on its own input terminals  30   a  and  30   b , and generate a rectified input voltage V IN   _   R  (i.e., a direct current (d.c.) signal) on its own output terminals  30   c  and  30   d.    
         [0046]    Furthermore, the generator  22  includes a division stage  42 , which is coupled between the output terminals  30   c ,  30   d  of the rectifier  30  and is configured to acquire the rectified input voltage V IN   _   R  and generate a first intermediate operating voltage V P1  that is a function of the rectified input voltage V IN   _   R  but has a reduced maximum amplitude, in particular having a value such as to drive a first transistor  56  (operation of which is described more fully hereinafter) into the on state. For this purpose, the division stage  42  includes a resistive voltage divider formed by resistors  36 ,  38  connected together in series between the output terminals  30   c ,  30   d  of the rectifier  30 , and a capacitor  40 , which is electrically coupled in parallel to the resistor  38  and has the function of providing a filter for removal of the high frequencies (e.g., frequencies higher than 60-100 kHz). The first intermediate operating voltage V P1 , which biases the control terminal (gate) of the first transistor  56 , is picked up on a node  37 , between the resistor  36  and the resistor  38 . 
         [0047]    By way of example, the resistor  36  has a resistance of 10 kΩ, the resistor  38  has a resistance of 2.4 kΩ, and the capacitor  40  has a capacitance of 68 nF. 
         [0048]    The generator  22  further includes an integration stage  50 , configured to receive the first intermediate operating voltage V P1  and generate a second intermediate operating voltage V P2  that is the integral of the first intermediate operating voltage V P1 . The second intermediate operating voltage V P2  is used for biasing the control terminal (base) of a second transistor  58  (operation of which is described more fully hereinafter). For this purpose, the integration stage  50  includes: a resistor  44 , electrically coupled between the node  37  and the control terminal of the second transistor  58  (i.e., electrically coupled to the output terminal  30   d  of the rectifier  30  via the resistor  36 ); and a capacitor  48  electrically coupled between the control terminal of the second transistor  58  and the output terminal  30   c  of the rectifier  30 . 
         [0049]    By way of example, the resistor  44  has a resistance of 100 kΩ, and the capacitor  48  has a capacitance of 1 μF. 
         [0050]    The transistors  56  and  58  are, in particular, BJTs of a PNP type that are the same as one another, and implement a differential pair, of a per se known type. Both the emitter terminal of the transistor  56  and the emitter terminal of the transistor  58  are electrically coupled to the output terminal  30   c  of the rectifier  30  by a tail resistor  59 , having for example a resistance of 43 kΩ. Furthermore, each transistor  56 ,  58  has a respective degeneration resistor  60 ,  62  coupled between its own emitter terminal and the tail resistor  59 . The degeneration resistors  60 ,  62  have the same value of resistance, for example of 30 kΩ. 
         [0051]    The collector terminal of the transistor  56  is, for example, electrically coupled to the output terminal  30   d  of the rectifier  30 , whereas the collector terminal of the transistor  58  is electrically coupled between the feedback input terminal  1   c  of the SMPS device  5  and the resistor  26  (on the node designated by the reference number  70 ). A Zener diode (not illustrated) may likewise be coupled in parallel to the resistor  26  for providing protection from overvoltages. 
         [0052]      FIGS. 5A-5E  show, using the same time scale, voltage/current signals at input to, and generated by, the generator  22  of  FIG. 4 . 
         [0053]      FIG. 5A  illustrates by way of example the envelope of the input signal V IN , generated by the electronic transformer, whereas  FIG. 5B  illustrates, by way of example, the envelope of the rectified input signal V IN   _   R  referred to the node  30   c , present on the output of the rectifier  30 . 
         [0054]      FIG. 5C  illustrates the control signals of the transistors  56  and  58  referred to the node  30   c . In particular, it may be noted that the plot of the first intermediate operating voltage V P1  follows the plot of the envelope of the rectified input signal V IN R  with a peak value, in modulus, lower than that of the rectified input signal V IN R  (in this example, it ranges between 0V and −3V approximately). The second intermediate operating voltage V P2  is, as has been said, the integral of the first intermediate operating voltage V P1  and, in this example, assumes values close to −2V. 
         [0055]    With reference to  FIG. 5C , there may be noted two operating conditions of the differential pair. In a first operating condition, in which the rectified input voltage V IN   _   R  has, in modulus, a maximum value, the differential stage does not inject current into the node  70 ; instead, when the rectified input voltage V IN   _   R  has, in modulus, a minimum value, the differential stage injects into the node  70  the current that flows through the transistor  58 . According to one embodiment, this current is the current I 1  identified previously, having a value, in modulus, of approximately 20 μA. 
         [0056]      FIG. 5D  illustrates the plot of the currents through the transistor  56  (intermediate current signal I INT1 ) and through the transistor  58  (intermediate current signal I INT2  corresponding to the current signal I 1  of  FIG. 3 ). The sum of I INT1  and I INT2  is equal to the current circulating in the resistor  59  (signal I INT3 ). As may be noted, when the rectified input voltage V IN   _   R  has a maximum value (in modulus), the current signal I INT1 =I INT2  is minimum and approximately to 0 A. Instead, when the rectified input voltage V IN   _   R  has a minimum value (in modulus), the transistor  56  is off (V P1 =0 V), and the transistor  58  behaves like a current generator that generates a current I 1  equal to approximately −20 μA, injecting into the node  70  a current I 1  equal, in modulus, to approximately 20 μA, and thus there is a voltage drop of 200 mV on the resistor  26 . 
         [0057]    It is evident that, in the transitions of the rectified input voltage V IN   _   R  between the maximum value and the minimum value, the current I 1  injected into the node  70  assumes intermediate values, but always inversely proportional to the value assumed by the rectified input voltage V IN   _   R . 
         [0058]      FIG. 5E  illustrates the voltage drop on the resistor  26 , proportional to the values assumed by the current I 1 . Assuming the voltage on the node  1   c  set by the regulation loop of the SMPS converter as being fixed, it is evident that the current that flows in the sensing resistor  4  follows, in a directly proportional way, the variations of the input voltage V IN . 
         [0059]      FIG. 4 a    shows a further embodiment of the present disclosure including the same generator  22  of  FIG. 4  with the addition of a possible implementation of the Current holder circuit CH of  FIG. 3 a   , which is designated CH 4 A in the embodiment of  FIG. 4 a   . This circuit CH 4 A includes a resistor Rc 1 , a resistor Rc 2 , a resistor Rc 3 , a resistor Rc 4 , a BJT of NPN polarity Q 1 , a diode D 1  and a MOSFET of N polarity M 1 , and a resistor R CURR   _   HOLD . 
         [0060]    By way of example, the resistor Rc 1  has a resistance of 100 kΩ, the resistor Rc 2  has a resistance of 10 Ω, the resistor Rc 3  has a resistance of 10 kΩ, the resistor Rc 4  has a resistance of 33 kΩ and the resistor RCURR_HOLD has a resistance of 5.1 Ω. 
         [0061]    In particular, in the operating condition of the differential pair  56 ,  58 , when  56  is off (i.e. V IN   _   R  is at its minimum), the BJT Q 1  has no current injected in its base and therefore there is no current flowing in the collector of Q 1  and in the resistor Rc 3 . As a consequence, the MOSFET M 1  works with the gate equal to V IN   _   R  and connects with a low impedance the drain of M 1  to V IN   _   R . The current flowing in the resistor RCURR_HOLD can be calculated according to the equation 
         [0000]    
       
         
           
             
               I 
               RCURR_HOLD 
             
             = 
             
               
                 V 
                 IN_R 
               
               
                 
                   R 
                   CURR_HOLD 
                 
                 + 
                 
                   R 
                   
                     DSON 
                     , 
                     
                       M 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
               
             
           
         
       
     
         [0062]    Otherwise, in the operating condition of the differential pair  56 ,  58  when  56  is on (i.e. V IN   _   R  is at its maximum), the base of Q 1  is biased by the current flowing in  56 . The current flowing in the resistor Rc 3  through (the collector of Q 1 ) turns off M 1 . As a result the current flowing in the resistor RCURR_HOLD is equal to zero. 
         [0063]    The behavior of the current generator  22  and current holder circuit CH 4 A described with reference to  FIG. 4 a    can be seen in  FIGS. 5F-5H . 
         [0064]    When VP 2  is higher than VP 1  the base of transistor Q 1  is positively biased so that there is current flowing in RC 3  so that VGS of M 1  goes below the transistor threshold voltage, thus disconnecting RCURR_HOLD from the electronic transformer. In this condition no resistive load is necessary since the SMPS  5  is absorbing significant current from the electronic transformer. Otherwise, when VP 2  is lower than VP 1 , the current IINT 1  is reducing down to the condition when the base of Q 1  is no more positively biased. At this point, the gate to source voltage of transistor M 1  goes above the transistor threshold voltage, thus connecting the resistor RCURR_HOLD between the two output terminals of the electronic transformer. As a consequence, during this phase, a sinusoidal current is absorbed from the electronic transformer. 
         [0065]    The current holder circuit CH 4 A described above adds a resistive load to the electronic transformer when the current I INT2  is at its maximum (i.e. when VIN_R is at its minimum). In this biasing condition, the SMPS is absorbing no current from the electronic transformer, and therefore, the connection of this resistor improves the resistive emulation of the circuit  22 . Moreover, the current holder sustains the switching activity of the electronic transformer at the beginning of every power line cycle, so that the current generator  22  works properly in every power line cycle. 
         [0066]      FIG. 6  shows a further embodiment of the present disclosure. Elements of  FIG. 6  common to elements appearing in  FIG. 4 , and described with reference to this figure, are designated by the same reference numbers and are not described any further. 
         [0067]    According to the embodiment of  FIG. 6 , the generator  22  further includes a stage for biasing the tail resistor  59  of the differential stage. For instance, said biasing is obtained by a charge pump  75  operatively coupled to the electronic transformer for receiving the input signal V IN . The charge pump  75  thus receives the input signal V IN  and supplies a biasing signal V IN  p at input to the tail resistor  59 , and is likewise electrically coupled to the node  30   c  via a capacitor  83  (e.g., with a capacitance of 220 nF). According to one embodiment, the tail resistor 59 of the differential stage is biased with a voltage V IN   _   P  having a value, in modulus, of approximately 5 V (in this example, V IN   _   P =−5 V). 
         [0068]    The embodiment of  FIG. 6  has the advantage of maintaining constant the current circulating in the resistor  59  as the input signal varies and thus the linearity of the response of the current generator  22  increases. As a consequence, the resistive emulation of the current absorbed by the SMPS  5  is improved, and the compatibility between the electronic transformer and the SMPS is increased. 
         [0069]      FIG. 6 a    illustrates a further circuit implementation of the biasing and driving circuitry of  FIG. 3 a    including the current generator  22  of  FIG. 6  and another embodiment of the current holder circuit CH of  FIG. 3 a   , which is designated CH 6 A in  FIG. 6 a    according to yet another embodiment of the present disclosure. The structure of the current holder circuit CH 6 A is similar to the structure of the current holder circuit CH 4 A of  FIG. 4A  except the resistor RC 3  is coupled to the charge pump  75  to receive the biasing signal V IN   _   P . The operation of the current holder circuit CH 6 A is also similar to that of the current holder circuit CH 4 A of  FIG. 4A , and will be understood by those skilled in the art in view of the description of the circuit CH 4 A above. Briefly, when the transistor  56  of the differential pair  56 ,  58  is turned OFF, which occurs when the rectified input voltage V IN   _   R  is at its minimum, then transistor Q 1  has no current injected into its base and therefore the current through the collector of this transistor and thus through the resistor RC 3  is negligible. As a result, the transistor M 1  receives approximately the voltage V IN   _   R  at it gate, turning ON the transistor and thereby connecting the resistor RCURR_HOLD across the rectified input voltage V IN   _   R  (i.e., connecting resistor RCURR_HOLD across terminals  30   c  and  30   d ). The current I RCURR   _   HOLD  through the resistor RCURR_HOLD is again given by the above equation. Conversely, when the rectified input voltage V IN   _   R  has its maximum value, current from transistor  56  turns ON the transistor Q 1  which, in turn, drives the voltage applied to the gate of the transistor M 1  to a voltage level that turns the transistor M 1  OFF. In this situation no meaningful current flows through the resistor RCURR_HOLD as this resistor is effectively isolated from the rectified input voltage V IN   _   R  by the deactivated transistor M 1 . 
         [0070]      FIG. 6 b    illustrates a still further circuit implementation of the biasing and driving circuit  20  of  FIG. 3 a    according to yet another embodiment of the present disclosure. In this embodiment, the pumped voltage VIN_P generated by the charge pump  75  is supplied to bias the only current holder circuit CH 6 A. This is in contrast to the embodiment of  FIG. 6  where the pumped voltage VIN_P is applied to bias only the current generator  22  and the embodiment of  FIG. 6 a    where the pumped voltage VIN_P is applied to bias both the current generator  22  and the current holder circuit CH 6 A. The use of the pumped voltage VIN_P has the benefit of increasing the voltage biasing of M 1  gate, so it helps connecting the resistive load at the output of the electronic transformer when the voltage VIN_R is at its very minimum, i.e. at the beginning of every power line cycle. 
         [0071]      FIG. 7  shows a circuit embodiment of the charge pump  75  of  FIG. 6 . Elements of the circuit of  FIG. 7  that are in common with those of the circuit of  FIG. 6  are designated by the same reference numbers and are not described any further. The charge pump  75  includes a diode  76  and a resistor  78  (e.g., with a resistance of 1 kΩ), connected together in series between the input terminal at the voltage V IN   −  (ground reference GND) and an intermediate node  79 ; in particular, the diode  76  has its anode coupled to V IN   −  and its cathode coupled to the resistor  78 . Furthermore, the charge pump  75  includes a capacitor  80  (e.g., with a capacitance of 220 nF) and a Zener diode  81  coupled in parallel to one another, between the intermediate node  79  and the input terminal at the voltage V IN   + ; in particular, the Zener diode  81  has its anode coupled to V IN   +  and its cathode coupled to the intermediate node  79 . A diode  82 , having its anode coupled to the intermediate node  79 , is set on the output of the charge pump  75 , for supplying at output the signal V IN   _   P . 
         [0072]    The advantages obtained emerge clearly from the foregoing description. In particular, the biasing and driving circuit described may be used for any generic SMPS, enabling operative coupling of said generic SMPS with a generic electronic transformer that requires a resistive load at the output of the transformer. Consequently, the power factor is increased. 
         [0073]    The biasing and driving circuit described further supports SMPSs with both current-mode and voltage-mode internal architecture. 
         [0074]    Modifications and variations may be made to the device and to the method described herein, without thereby departing from the scope of the present disclosure, as defined in the annexed claims. 
         [0075]    In particular, the present disclosure applies to any generic feedback voltage regulator (whether of the SMPS switching type or of the linear type). Furthermore, the driven electric load may be a generic electric load, not limited to the string of LEDs. 
         [0076]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
         [0077]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.