Abstract:
The disclosure relates to a time-overcurrent relay utilizing successive linear time-current segments which approximate a non-linear, inverse time-current curve the linear segments are determined by subtracting a series of ramp like voltages of increasing magnitudes from a series of bias voltages, each of which is of substantially constant magnitude and which bias voltage magnitudes decrease in sequence by the peak magnitude of the preceding ramp voltage.

Description:
BACKGROUND OF THE INVENTION 
     It is a commonly accepted practice in the electrical arts to provide a current relay which will have an inverse time-current characteristic. This has in the past usually been accomplished by electromechanical switch means and has resulted in the development of generally accepted families of time-current characteristic curves which may vary from a slightly inverse to an extremely inverse time-current characteristic. 
     SUMMARY OF THE INVENTION 
     Solid state electronics have many desirable characteristics, such as requiring less power for their operation and a consequent lessening of the burden imposed on the circuits being protected. In accordance with the teachings herein, the non-linear curve is broken up into a series of linear segments which are readily and economically attained with solid state electronics. This is accomplished by dividing the time axis of the non-linear curve into a desired number of time intervals and approximating the non-linear curve with linear segments extending between the intersections of the time points with the non-linear time-current curve. 
     The time-current curve is usually plotted as time against the number of pick-up values of the current to be monitored. The current magnitude is usually sensed by a network which will produce an input voltage quantity C which has a magnitude which represents the current magnitude and a voltage scale may be substituted for the pick-up value scale. When the current magnitude reaches a predetermined number of multiples of pick-up, the trip output of the relay should be &#34;instantaneous&#34; with no programmed time interval. This pick-up magnitude will provide an established input voltage for any given current to-voltage ratio. An extrapolation of the usual electromechanical relay curve to this pick-up value, as well as to the 1 unit of pick-up current value, will normally be required. This establishes the magnitude of the input voltage C which must be equalled for the relay to trip with no programmed delay and to trip with the maximum delay at just over 1 unit of pick-up value. 
     In accordance with our invention, this input voltage is compared with two voltages A and B generated within the relay itself. One of these generated voltages A comprises a number of constant value or bias segments, one for each time interval starting with a segment of a magnitude equal to the magnitude of the voltage C for an instantaneous trip. The second B of the generated voltages comprises a series of voltages, one for each time interval, having magnitudes which will change in magnitude from an initial to a final magnitude during each time interval by an amount equal to the change in magnitude of the curve during each of the time intervals of the linear segments. It will be appreciated that with inverse, time-overcurrent curves, this will mean the greatest change in magnitude of the voltage B occurs during the first time interval and progressively decreasing changes in magnitude occur as the number of the time intervals increases. 
     At the end of each time interval, the magnitude of the voltage B returns to its initial value and the magnitude of the voltage A is reduced by the peak value of the voltage B during the just-elapsed time interval. When the magnitude of the combined voltages A and B equals the magnitude of the voltage C, the relay will trip. 
     Since the change in voltage B will reduce the voltage A, the combined value may be considered as A-B. The combined value reaches trip magnitude when the magnitude of the voltages A-B equals the magnitude of the voltage C and may be stated by the mathematical quantity A - B = C. It will be apparent that this relationship may be restated as A = B + C or as B = A - C. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1, 2 and 3 are curves illustrating the time-voltage (magnitude of pick-up current) magnitudes when combined as A - B = C, B + C = A, and A - C = B respectively; 
     FIG. 4 is a schematic diagram illustrating a first preferred form of a solid state relay embodying the invention in the form B + C = A; 
     FIG. 5 is a schematic diagram illustrating a second preferred form of a solid state relay embodying the invention also in the form B + C = A; and 
     FIGS. 6 and 7 are block diagrams illustrating a solid state relay embodying the invention in the forms A - B = C and A - C = B, respectively. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the drawings by characters of reference, the character NL designates a desired non-linear, time-current curve which is to substantially be duplicated by the relay of the present invention. This curve is normally plotted with the abscissa representing current and the ordinate representing time. The abscissa may be rescaled in terms of the magnitude of the voltage developed at each of the current multiple, in this case, 0 to 13 volts for 0 to 26 multiples of pick-up current. The ordinate is rescaled in equal intervals or steps, commencing with the time at the pick-up current value for instantaneous trip, which are shown as being light intervals to agree with the eight steps performed by the relays 30 and 30&#39; of FIGS. 4 and 5. A greater number of steps will increase the accuracy since the linear approximations LA will more nearly lie on the curve NL. While the preferred forms of the relays utilize equal time increments and require less complicated apparatus than would be required if the intervals or increments were unequal, such inequality can be implemented. When this is done, modifications will be required which will cause the preferred embodiments to become more complicated, but which may be made by those skilled in the art in accordance with the teachings of the illustrated embodiments. 
     The stepped curve A represents the magnitudes of a bias voltage and consists of constant value steps. Initially, its magnitude is the magnitude of the voltage established by the magnitude of the line current when &#34;instantaneous&#34; tripping is desired. This is designated as time 0. At time 1, the magnitude reduces to the magnitude corresponding to that of the curve NL. Similarly, the magnitude of the bias voltage drops in steps at the time 2, 3, 4, etc., until the breaker in the controlled power line opens and reduces the voltage C developed in consequence of the power line current. The sequencing stops when the magnitude of C is reduced below the 1 pick-up current multiple as will be explained below. 
     The curve B represents the slope segment voltage and is shown as having an initial value of zero and a peak value equal to the change in volts along the curve NL during the respective time interval. During the time interval 0-1, it will increase in magnitude from zero to 9.5 volts. During subsequent time intervals, the increase will be less as illustrated. The slope voltage B when subtracted from the bias voltage A will provide the time voltage relationship LA. 
     The embodiments of FIGS. 4 and 5 utilize the curve relationship B + C = A for controlling the energization of their respective tripping circuits, while the embodiments of FIGS. 6 and 7 utilize the curve relationship A - B = C and A - C = B respectively for controlling their respective tripping circuits. 
     As illustrated in FIG. 4, the current in the power circuit 32 is sensed by a current transformer CT, the secondary of which energizes a loading resistor R. The primary of the transformer is preferrably tapped so that the voltage quantity established across the resistor R provides the proper relationship of the control quantity supplied to the rectifier and filter network 34 of the relay 30. The network 34 comprises a rectifying circuit including the amplifier A1 and a filtering circuit including the amplifiers A2 and A3. These amplifiers, as well as the amplifiers A4-A10, may be operational amplifiers of the type sold under the designation SN-72747. Each amplifier will, of course, have its power input terminals energized from the + 15 or + 15 volt busses as required. The rectified direct potential output voltage of the network 34 is the voltage C as set forth above. 
     The voltage C is supplied to the instantaneous trip comparator or network 36, the summing network 38 and the pick-up comparator or network 40. At magnitudes of the voltage C below pick-up magnitude, the output voltage of the amplifier A7 of the network 40 provides positive voltage or logical 1 signal to the diode D 1  of the ramp generator network 42 which maintains the transistor Q 1  conducting and thereby shunts the current from the constant current source 44 around the connected one of the capacitors C X . This keeps the + input terminal of the amplifier A6 of the segment slope generator network 44 at zero or ground potential and the output voltage D of the amplifier A6, as well as the output voltage of the amplifier A8, are also maintained substantially at ground potential. The ground voltage D is supplied to the + input terminal of the amplifier A9 of the slope generating network 44 whereby its output voltage B is also maintained substantially at ground potential. 
     The magnitude of the segment bias voltage A of the segment bias generator 45 is determined by a voltage dividing network 47 connected between the + 15 volt supply and the ground or neutral potential. The voltage dividing network 47 includes a first or common resistor 48 connecting the + 15 volt supply to a bus 49 and 8 individual resistors which connect the bus 49 to the ground or neutral potential through individual transistor switches. Conveniently, seven of these switches may be the seven NPN transistors of a CA 3081 transistor array 50 and the eighth switch a discrete NPN transistor 51. The bases of the NPN transistor switches are connected to the 4 bit counter 46 through a decoder 52 which for example may be of the SN7442 type. 
     As the counter is actuated, the decoder sequentially provides a logical 0 signal at its output pins 1-7 and 9. This logical 0 signal is inverted by the inverters associated with these pins and applied as logical 1 signals to sequentially render conducting the NPN transistors of the array 50 and the discrete transistor 51. At the ninth pulse of the counter, the decoder resets to its initial or count zero condition. The magnitude of the individual resistors of the network 47 are so proportioned that the voltage on bus 49 will provide the voltage segments A of FIGS. 1-3. 
     The magnitude of the slope voltage B is a portion of the output voltage D of the amplifier A6 as determined by a voltage dividing network 54 connected between the output terminal of the amplifier A6 and the ground or neutral potential. This dividing network is similar to the network 47 and comprises a first or common resistor 55 connecting a bus 56 to the output terminal of amplifier A6 and 8 individual resistors which connect the bus 56 to ground through 8 individual transistor switches. Conveniently, seven of these switches may be the seven NPN transistors of a CA3081 transistor array 57 and the eighth switch a discrete NPN transistor 58. The logical 0 output signals of the decoder 52 are inverted and sequentially render conducting the NPN transistors of the array 57 and the discrete transistor 58 as described above in connection with the segment bias generator 45. 
     The slope generator 44 is energized from the output of the ramp generator 42. The output potential of the ramp generator 42 is determined by the potential across the capacitor network 60, as limited by the effect of amplifier A8. When the shorting transistor Q 1  is non-conductive, the constant current source will the capacitor network 60 at a constant rate as determined by the setting of the switches associated therewith, in this instance, the connected capacitor C X . 
     When the current in the power circuit 32 increases to some value in excess of the pick-up setting (the maximum desired current of the power circuit), the pick-up network 40 will terminate the logical 1 signal to the diode D1 of the ramp generator 42. The transistor Q 1  will thereupon become non-conducting and the voltage across the capacitor network 60 will increase at a predetermined rate. Initially, the NPN transistor of the array 57 associated withthe output terminal 1 of the decoder 52 will be conducting and the voltage dividing network 54 will provide the maximum ratio between the voltage output of the ramp generator 42 and the bus 56. This results in an output voltage B as indicated in FIGS. 1 and 3 during the time interval 0 - 1. During this same interval, the output terminal 1 of the decoder 52 will be maintaining the NPN transistor of the array 50 associated therewith in its conducting condition to provide the maximum voltage on the bus 49 of the voltage dividing network 47 to provide the bias voltage A (FIGS. 1 and 2). In the form shown in FIG. 2, the voltages B and C are added to provide the wave shape B + C during the time interval 0 - 1. 
     When the voltage across the capacitor network 60 reaches a critical value (in this case 5 volts), the amplifier A8 changes its output voltage condition from its low to its high state. The output voltage condition of inverter 62 will thereupon change from its high to its low state causing a capacitor 63 to momentarily lower the potential of the base of a normally conducting transistor 64 to become non-conducting whereby the collector thereof momentarily assumes a + 5 volt potential. This coupled with the effect of the inverter 65, causes a flow of base current of the transistor Q 1  through the diode D2. Transistor Q 1  conducts and rapidly discharges the capacitor network 60 to initiate a subsequent recharging of the network 60. 
     The momentary positive pulse resulting at the collector of the transistor 64 provides a counting pulse to the input terminal 2 of the segment counter 46. The change in state of the counter 46 is decoded by the segment decoder 52 and results in the termination of the logical 0 signal at its output terminal 1 and the provision of a logical 0 signal at its output terminal 2. 
     During the next time interval 1-2, the next of the NPN transistors of the arrays 50 and 57 will be rendered conducting. The voltage dividing network 47 will now apply a lesser voltage to the bus 49 and the segment bias voltage A is reduced to the value shown in FIGS. 1 and 2 during the time interval 1-2. The voltage dividing network 54 will now apply a lesser percentage of the output voltage of the ramp generator to the bus 56 and the slope voltage will increase at a lesser rate to limit the slope voltage B to the value shown in FIGS. 1 and 3 during the time interval 1-2. 
     At the time 2, the ramp generator 42 is again reset and the segment counter 46 reactuated to provide the time interval 2-3 and the bias voltage A (see time 2-3 of FIGS. 1 and 2) and the slope voltage B (see time 2-3 of FIGS. 1 and 3). 
     Assuming a line current of three times the pick-up value as illustrated in FIGS. 1, 2 and 3 and from B + C = A of FIGS. 2 and 4, the cycling as above described will continue into the time interval 3-4 and a trip signal will be established when the curve B + C crosses the curve A. In the forms A - B = C and A - C = B (FIGS. 1 and 6 and 3 and 7), the summing and comparing are somewhat different because of the different transpositions of the mathematical formula, but in each instant the trip signal occurs at the time instant when the curve A-B intersects the curve C and the curve A-C intersects the curve B, which from inspection is the same instant in time after initiation of the relay 30. 
     When the curves intersect, the trip comparator 68 forwards a the flip-flop 70. This provides an energizing signal to the trip circuit (not shown) and a resetting signal to the counter 46. 
     In many instances, a separate instantaneous trip actuation is desired. For this purpose, the network 36 is provided and is energized directly by the output voltage C of the rectifier and filter network 34. At line currents below the instantaneous trip value, the output of the amplifier A4 supplies a logical 1 signal through the isolation diode 72 to the trip comparator 68. 
     The relay 30&#39; of FIG. 5 operates in substantially the same manner as the relay 30 of FIG. 4. The main difference between the two is in the ramp generator 42&#39;. The generator 42&#39; develops the ramp voltage digitally under control of a timer 80 having a digital output. As illustrated, this timer 80 comprises an operational amplifier A8 and a capacitor network 81 which is alternately charged and discharged to provide a series of digital output signals to drive the first 5 output terminals of two series connected 4-bit counter 82 and 83 which may for example be of the SN7493 type. The first 5 output terminals are connected through inverters to the input terminals 9, 8, 7, 6 and 5 respectively of a 6-bit multiplying digital-to-analog converter 84 which may be of the MC1406L type. The output terminal 4 of the converter 84 is connected to the input terminal of amplifier A6 of the slope generator 44&#39;. The difference between the generators 44 and 44&#39; is that amplifier A6 of generator 44&#39; produces staircase-like ramp voltages versus linear ramp voltages in 44. The RC network in the feedback path of the amplifier A6 of the generator 44&#39; is to smooth the staircase. This shunting capacitor is not necessary if a stepped wave is desired. 
     The last three output terminals of the counter 83 are connected to the input terminals 15, 14 and 13 of the SN7442 decoder of the segment decoder network 52&#39;. The network 52 will control the segment generator 45 and the slope generator 44&#39; as described above in connection with the same structure found in FIG. 4.