Abstract:
A radiation hardened active OR circuit for providing a controlled electrical response in radiation-intensive applications. The circuit can include a first voltage source; a second voltage source; a comparator for sampling the first voltage source and the second voltage source; a first switch; and a second switch. The comparator can select a higher magnitude of the first voltage source and the second voltage source and connects the higher magnitude of the first voltage source and the second voltage source to a common output by steering a drive signal to one of the first switch or the second switch.

Description:
BACKGROUND 
       [0001]    The present invention relates to a radiation hardened active “OR” circuit. 
         [0002]    Certain electronic applications use two or more independent voltage sources to improve reliability. In the event of one of the power sources dropping out or becoming too low to operate the load circuitry, the load is powered by a second source. Many such applications are designed for use in satellites and spacecraft. In these applications, function must operate in the presence of high radiation levels. 
         [0003]    As shown in  FIG. 1 , a simple diode OR circuit  1  is shown. A simple diode OR circuit  1  can be implemented by connecting two power sources  2 ,  3  to the load  6  through two rectifiers  4 ,  5 . The higher magnitude of the two voltage sources  2 ,  3  supplies the load  6  while current is not allowed to be fed to the lower magnitude voltage source. This type of connection is termed a “redundant” arrangement. The connection of two voltage sources  2 ,  3  to two rectifiers  4 ,  5  with a common output  6  is termed an “OR” or “diode OR” circuit. 
         [0004]    There are two significant drawbacks to the diode OR circuit  1 . One drawback is the power loss associated with the voltage drop across the rectifier that is conducting current. A second drawback is that a voltage sources doesn&#39;t always fail by reducing or dropping out, but may instead fail by increasing in magnitude. In the latter instance, instead of the application being more reliable due to the use of the diode OR, the diode OR may allow a potentially damaging over-voltage to be applied to the load. Furthermore, when a simple diode OR circuit is used for low voltage, high current applications, the resultant power and voltage drop may be intolerable. 
       SUMMARY 
       [0005]    Active “OR” devices are circuits designed to efficiently combine two redundant voltage sources that feed a single load. The object of the disclosed technology is to implement radiation hardened active “OR” devices, using non-radiation hardened transistors. This invention is a method of implementing an economical active OR circuit that can operate in a high ionizing radiation dose environment such as found in spacecraft and particle accelerator applications. 
         [0006]    In one implementation, a radiation hardened active OR circuit for providing a controlled electrical response in radiation-intensive applications comprises: a first voltage source; a second voltage source; a comparator for sampling the first voltage source and the second voltage source; a first switch; and a second switch, wherein the comparator selects a higher magnitude of the first voltage source and the second voltage source and connects the higher magnitude of the first voltage source and the second voltage source to a common output by steering a drive signal to one of the first switch or the second switch. 
         [0007]    In some implementations, the first switch can be a P-channel MOSFET and the second switch can be a P-channel MOSFET, wherein the first switch and the second switch require higher bias voltages, when properly driven, in radiation environments. 
         [0008]    In some implementations, the circuit can further comprise: a bias voltage DC-DC converter; and a diode circuit for feeding voltage to the bias voltage DC-DC converter, wherein the bias voltage DC-DC converter converts a low voltage source from the diode circuit into a higher bias voltage thereby properly driving the one of the first switch or the second switch. In some implementations, when a bias voltage is present and when the comparator steers the higher bias voltage to the one of the first switch or the second switch, a drain to source channel of the one of the first switch or the second switch conducts and a voltage drop is reduced to a value determined by a resistance of the one of the first switch or the second switch. 
         [0009]    In another implementation, a radiation hardened active OR circuit for providing controlled electrical response in radiation-intensive applications comprises: a first voltage source; a second voltage source; a voltage sense/shutdown block; a first set of FETs, the first set of FETs being connected in series; and a second set of FETs, the second set of FETs being connected in series, wherein the voltage sense/shutdown block disconnects the first voltage source or the second voltage source in the event that one of the first voltage source or the second voltage source exceeds a pre-set, programmable limit. 
         [0010]    In some implementations, the use of the first set of FETs being connected in series and the second set of FETs being connected in series in each voltage source leg can allow one or both of the voltage sources to be completely disconnected from a common output in the event of the one of the first voltage source or the second voltage source exceeding the pre-set, programmable limit. 
         [0011]    In some implementations, the circuit can further comprise: a comparator for sampling the first voltage source and the second voltage. In some implementations, when a voltage level of the first voltage source exceeds pre-set, programmable limit, a first signal from the voltage sense/shutdown block is fed to the comparator which causes a gate drive voltage to be removed from the first set of FETs, and, when a voltage level of the second voltage source exceeds pre-set, programmable limit, a second signal from the voltage sense/shutdown block is fed to the comparator which causes a gate drive voltage to be removed from the second set of FETs. 
         [0012]    In some implementations, the comparator may select a higher magnitude of the first voltage source or the second voltage source and connects the higher magnitude of the first voltage source or the second voltage source to a common output by steering a drive signal to the first set of FETs or the second set of FETs. 
         [0013]    In some implementations, the first set of FETs can be P-channel MOSFETs and the second set of FETs can be P-channel MOSFETs, the first set of FETs and the second set of FETs requiring a higher bias voltage, when properly driven, in radiation environments. 
         [0014]    In some implementations, the circuit can further comprise: a bias voltage DC-DC converter; and a diode circuit for feeding voltage to the bias voltage DC-DC converter, wherein the bias voltage DC-DC converter converts a low voltage source from the diode circuit into a higher bias voltage thereby properly driving the first set of FETs or the second set of FETs. 
         [0015]    An “active OR” circuit can substitute a controllable active element, such as, a transistor, e.g., a MOSFET in place of the diode. Although this transistor must be driven by a control signal, the use of a transistor can result in a lower voltage drop than is obtained with a simple diode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0016]      FIG. 1  is a block diagram of a simple diode OR circuit; 
           [0017]      FIG. 2  is a block diagram of a radiation tolerant active OR circuit of the disclosed technology; 
           [0018]      FIG. 3  is a block diagram of a radiation hardened active OR circuit combined with an over voltage shutoff of the disclosed technology; 
           [0019]      FIG. 4  is a block diagram of bias voltage DC-DC converter of the disclosed technology; 
           [0020]      FIG. 5  is a circuit diagram of bias voltage DC-DC converter of the disclosed technology; 
           [0021]      FIG. 6  is a circuit diagram of a voltage comparator of the disclosed technology; and 
           [0022]      FIG. 7  is a circuit diagram of a voltage comparator of the disclosed technology. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    A simplified block diagram of a radiation tolerant active OR circuit is shown in  FIG. 2 . Referring to  FIG. 2 , there are two independent voltage sources—voltage source A  21  and voltage source B  22 . These voltage sources  21 ,  22  are connected to form output  25 . The desired function of the active OR circuit  20  is to select the higher magnitude of either voltage source  21 ,  22  and to efficiently connect the higher magnitude source to output  25 . 
         [0024]    In some implementations, a semiconductor device for power control in an active OR circuit can be an insulated gate FET (Field Effect Transistor), due to its high power gain. FETs used for power switching use are usually enhancement mode types. This means that they are normally non-conducting. When a gate voltage above a threshold is applied, the FET becomes conducting. FETs are available in two gate polarities; N channel and P channel. Power switching circuits designed for general purpose use are usually constructed with N channel FETs because, for any given die size transistor, the N channel FET has a lower on resistance than a correspondingly sized P channel FET would have. 
         [0025]    The radiation hardened active OR circuit  20  of the disclosed technology uses P channel MOSFETs  23 ,  24  since these devices are inherently functional, when properly driven, in radiation environments. 
         [0026]    For background, an ordinary diode OR, as shown in  FIG. 1 , creates a proportionally greater voltage drop when combining low voltage sources. Such low voltage sources may be in the range of 0.9 VDC to 5 VDC. Therefore, an active OR is most beneficial when it is used combines low voltage sources. However, P channel MOSFETs require higher bias voltage for proper drive and radiation tolerance. Therefore the function of the Bias Voltage DC-DC converter block  27  is to convert a low voltage source (typically as low as 2.5 VDC) to at least 15 VDC to properly drive the FETs  23 ,  24 . In order to supply the Bias Voltage DC-DC converter block  27 , a conventional diode or circuit  26  is used. In some implementations, the diode circuit  27  can consist of two diodes with a common cathode connection (not shown) that feeds voltage to the bias voltage DC-DC converter  27 . This provides bias power if either of the two voltage source inputs  21 ,  22  have a sufficiently high voltage. 
         [0027]    The radiation hardened active OR circuit of the disclosed technology also includes a voltage comparator  28 . The voltage comparator  28  is capable of sampling each of the two input voltage sources  21 ,  22  and then steer a drive signal to energize the higher of the two sources  21 ,  22 . The input to the voltage comparator  28  must sense the higher of the two input sources  21 ,  22  without allowing current to flow from one source to another. The output of the voltage comparator  28  can be a negative drive voltage, referred to the most positive input, of at least 15 VDC. 
         [0028]    The radiation hardened active OR circuit  20  of the disclosed technology can also include power switches  23 ,  24 . That is, the active OR of  FIG. 2  has two independent power switches, switch A  23  and switch B  24 . The source terminal of each of the P FET switches  23 ,  24  is connected to the respective input power bus  29 , and the drain of both P FETs  23 ,  24  is tied in common to the output  25 . In this way, without application of bias voltage, the intrinsic body-drain diode of each FET acts as a simple diode OR. When bias voltage is present, and when the comparator steers the bias voltage to the appropriate FET, the FET drain to source channel conducts and the voltage drop is reduced to a value determined by the on resistance of the FET. 
         [0029]    In short, the active OR shown in  FIG. 2  is a relatively simple circuit that selects the higher of two input voltages and efficiently connects the higher of the two voltages to a common output. This increases system reliability since the output is maintained even if one of the two voltage sources decreases below usability, or drops out altogether. 
         [0030]    However, in a small fraction of instances, one of the voltage sources may fail and produce a damaging over voltage. In this case, the Active OR still operates, and the A higher, damaging voltage, will be applied to the load. 
         [0031]    In one implementation, to overcome the limitations of the circuit of  FIG. 2 , a radiation hardened active OR combined with over-voltage shutoff of  FIG. 3  can be used. One advantage of FIG.  3 &#39;s circuit  30  as compared to FIG.  2 &#39;s circuit  20  is the means to disconnect either voltage source A or voltage source B in the event that one (or both) of the voltage sources exceeds a pre-set, programmable limit, possibly due to a failure. This protects a load connected to output C  37 . An additional feature is the ability to disconnect either voltage source A, voltage source B or both voltage sources, by operating an inhibit pin  43 ,  44 . 
         [0032]    The circuit of  FIG. 3  is a derivative of the circuit of  FIG. 2 . However, the single FET in each input power leg is replaced with a series connection of two back-to-back FETS  33 / 34 ,  35 / 36  connected to a common output  37 . The use of two back-to-back FETs  33 / 34 ,  35 / 36  in each voltage source leg, in lieu of single FETs, allows one or both of the voltage sources  31 ,  32  to be completely disconnected from the common connection in the event of an unacceptably high over voltage. It should be noted that the use of a single PET in each voltage source leg (instead of two back-to-back FETs), with the voltage source connected to the drain and a common source connection, would be unsatisfactory. This would allow conduction of the body drain diode to conduct from the output in the event that one of the voltage sources was shorted. 
         [0033]    Referring to  FIG. 3 . Voltage source A  31  is compared to a fixed reference voltage by a comparator  40 . The voltage reference and comparator comprise over voltage sense/shutdown block  41 . When the voltage level of source A  31  exceeds a preset value, a signal from the over voltage sense/shutdown block  41  is fed to voltage comparator  40  and causes the gate drive voltage to be removed from FET switches  33 / 34 . 
         [0034]    Similarly, voltage source B  32  is sensed by over voltage/sense block  42  and causes a removal of gate drive to FETs  35 / 36  in the event that voltage source B  32  exceeds a preset value. Additionally, the over voltage/sense blocks  41 ,  42  have the ability to disconnect one or both voltage sources  31 ,  32  using inhibit pins  43 ,  44 . Inhibit commands using the inhibit pins  43 ,  44  can be very useful in high radiation environments. This function is readily implemented by using the shutdown means in block  41 ,  42 . 
         [0035]    The radiation hardened active OR circuit  30  of  FIG. 3  also includes a bias voltage DC-DC converter  39 . Although the design of the bias DC-DC converter  39  may use any number of suitable topologies, in some implementations, the converter  50  of  FIG. 4  can be used. The diode OR input voltage  51  from voltage source A and voltage source B can be fed to a Colpitts LC oscillator  52  operating at 800 kHz. The oscillator  52  can use a PNP bipolar transistor suitable for low voltage operation. A PNP transistor is desirable because the current gain of a PNP transistor usually degrades less than the current gain of an NPN transistor after accumulation of ionizing radiation. 
         [0036]    The PNP Colpitts oscillator stage  52  is followed by an NPN switch stage  53 . When working with a low supply voltage, it is often advantageous to use complementary polarity devices. The NPN switch stage  53 , in turn, drives a flyback step up transformer  54 . The output of the flyback transformer  54  then drives a diode/capacitor voltage doubler  55 , ultimately resulting in a 15 to 20 VDC bias voltage  56  from a 2.5 VDC source. 
         [0037]    Although the design of the bias DC˜DC converter  50  may use any number of suitable topologies, in some implementations, the converter  60  of  FIG. 5  can be used. In  FIG. 5 , a low voltage source (Vcc)  61  is fed through inductor L 3  for filtering. Capacitor C 1  is a filter bypass capacitor. A Colpitts oscillator tank is formed by L 1 , C 2  and C 3 . The output of the tank circuit is fed through DC blocking capacitor C 4 , then to the base of PNP transistor Q 1 . Resistors R 1  and R 2  bias the base of Q 1  in the active region. Resistor R 3  limits the collector current of Q 1 . Resistor R 4  is the collector load of Q 1 , and this drives the base of Q 2 . Q 1  and Q 2  each provide 180 degree phase shifts, and the combination of Q 1  and Q 2  form a non inverting amplifier. The collector of Q 2  drives the C 2 ˜C 3  tap of the Colpitts oscillator tank, as well as the tap of L 2 , a step up auto transformer. Resistor RS limits the current in Q 2  and CR 1  prevents the collector of Q 2  from going negative with respect to the emitter. Pin  1  of tapped inductor L 2  is connected to the filtered Vcc supply voltage  61 . Pin  3  produces a stepped up sinusoid voltage at the Colpitts oscillator frequency. The oscillation frequency of the Colpitts oscillator is preferably determined by the L 1 , C 2 , C 3  components to be in the 500 kHz to 1 mHz range to allow small size inductive components. The stepped up sinusoid produce by L 2  pin  3  as DC restored by CS and CR 3 , then peak detected by CR 2  and C 6 . This circuit is also described as a diode voltage doubler. 
         [0038]    Although the design of the comparator may use any number of suitable topologies, in some implementations, the comparator  28  of  FIG. 2  can have a circuit  70  of  FIG. 6 . In  FIG. 6 , independent voltage inputs A and B  71 ,  72  are connected to the comparator  28  of  FIG. 2 . Using a conventional diode OR consisting of diodes CR 11  and CR 12 , a voltage Vcc  73  is generated which supplies the bias voltage DC-DC converter  50  shown in  FIG. 4 . Operating from input A  71 , resistor R 11  provides a common emitter resistance for the Schmitt trigger consisting of PNP transistors Q 15  and Q 17 . R 13  provides base current for Q 17  and R 15  is the collector load for Q 17 . Complementary transistors Q 19  and Q 20  buffer the collector voltage of Q 17  and provide a low impedance drive for the switching FETs. A mirror image for voltage source B  72  consists of Q 16 , Q 18 , Q 21 , Q 22 , R 12 , R 14  and R 16 . R 17  provides a base current source for either Q 15  or Q 16 , depending on whether Input A  71  or Input B  72  is higher. 
         [0039]    Although the design of the comparator may use any number of suitable topologies, in some implementations, the comparator  40  of  FIG. 3  can have a circuit  90  of  FIG. 7 . In  FIG. 7 , independent voltage inputs A and B  91 ,  92  are connected to the comparator  40 . Using a conventional diode OR consisting of diodes CR 110  and CR 111 , a voltage Vcc  97  is generated which supplies the bias voltage DC-DC converter  50  shown in  FIG. 4 . 
         [0040]    Operating from input A  91  and through transistor Q 111 , resistor R 115  provides a common emitter resistance for the Schmitt trigger consisting of PNP transistors Q 104  and Q 110 . R 111  provides base current for Q 110  and R 112  is the collector load for Q 110 . Diode CR 106  limits reverse current flow from Q 112  to Q 110 . 
         [0041]    Complementary transistors Q 105  and Q 108  buffer the collector voltage of Q 110  and provide a low impedance drive for the switching FETs. A mirror image for voltage source B  92  consists of CR 107 , Q 113 , Q 103 , Q 109 , Q 106 , Q 107 , Q 114 , R 116 , R 117  and R 113 . 
         [0042]    R 111  provides a base current source for either Q 103  or Q 104 , depending on whether Input A  91  or Input B  92  is higher. 
         [0043]    The over-voltage protection circuitry compares the input voltage of voltage source A  91  or voltage source B  92  to a fixed reference voltage. The fixed reference voltage is derived from precision reference diode CR 112 , which is supplied current from the Vcc  97  through R 127 . The input from voltage source A  91  is connected to a voltage divider consisting of R 120  and R 121 . The divided voltage is fed to comparators U 1 -A and U 1 -B. The output of each comparator is open collector. When the input voltage is within normal limits, comparator A&#39;s output is low and comparator B&#39;s output is open. When Comparator A output is low, transistor Q 111  conducts, connecting voltage source A to the sense resistor R 115 . 
         [0044]    When the input voltage source level exceeds the over voltage set point, comparator B&#39;s output goes low, making transistor Q 112  conduct and FET drive A is removed. Concurrently, transistor Q 111  is turned off removing the over voltage input from sense resistor R 115 . 
         [0045]    A similar circuit applies to voltage source B. In order to disconnect voltage source A from the common output by using the inhibit function, a positive voltage of sufficiently high magnitude is applied to the R 120 , R 121  voltage divider through diode CR 108 . This simulates an over voltage, and voltage source A is disconnected from the common output. A similar circuit applies to voltage source B. 
         [0046]    While this specification contains many specific implementation details, these should not be construed as limitations on the scope of the disclosed technology or of what can be claimed, but rather as descriptions of features specific to particular implementations of the disclosed technology. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination can be directed to a subcombination or variation of a subcombination. 
         [0047]    The foregoing Detailed Description is to be understood as being in every respect illustrative, but not restrictive, and the scope of the disclosed technology disclosed herein is not to be determined from the Detailed Description, but rather from the claims as interpreted according to the full breadth permitted by the patent laws. It is to be understood that the implementations shown and described herein are only illustrative of the principles of the disclosed technology and that various modifications can be implemented without departing from the scope and spirit of the disclosed technology.