Abstract:
An improved MOS current mirror wherein the mirror transistors are biased to operate in the saturated region near the boundary between the linear and the saturated regions to maximize the voltage gain and the power supply rejection ratio while maintaining a high output impedance.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to semiconductor circuits, and more particularly to an improved current mirror circuit using metal-oxide-semiconductor (MOS) field-effect transistors. 
     A current mirror is a current-controlled current source wherein the current output is constant for a given current input. Typical applications of this circuit include bandgap voltage references, operational amplifiers and comparators. In complementary MOS (CMOS) applications using this circuit high impedance stages are desirable for high gain, low offset, and high power supply rejection ratio. One method of meeting these requirements is to use stages with cascoded outputs. A typical circuit having cascoded outputs requires a voltage equal to twice the gate to source voltage, or 2 V GS , on the input and a voltage equal to the difference between this voltage and the threshold voltage, or (2 V GS  -V T ), on the output for proper operation. However, this prevents the output from directly driving a subsequent stage requiring only one V GS  on its input unless a level translating circuit is included. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention provides an improved MOS current mirror wherein the mirror transistors are biased in the saturated region on or near the boundary between the linear region and the saturated region in order to maximize the voltage gain and the power supply rejection ratio while maintaining a high output impedance at voltages down to 2 (V GS  -V T ). 
     In one embodiment of the present invention the mirror transistors are biased by means of a second cascoded stage in combination with a series-parallel stage of three transistors having a common gate connection. 
     In another embodiment the bias voltage is obtained by using a MOS transistor having a threshold voltage different from the threshold voltage of the mirror transistors. 
     In yet another embodiment a second cascoded stage is biased by a single transistor connected to a bias current source wherein the bias current is related to the mirror input current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and many of the attendant advantages of the present invention will be readily apparent as the invention becomes better understood by reference to the following detailed description with the appended claims, when considered in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a schematic diagram of a current mirror circuit according to one embodiment of the present invention; 
     FIG. 2 is a graphical representation of the output characteristics for a typical p-channel MOS transistor; 
     FIG. 3 is a schematic diagram of a second embodiment of the current mirror circuit of the present invention; and 
     FIG. 4 is a schematic diagram of a third embodiment of the current mirror. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings, there is shown in FIG. 1 a current mirror circuit according to one embodiment of the present invention. Although the circuit is illustrated with p-channel MOS transistors, it will be readily apparent to those skilled in the art that n-channel devices may also be employed. 
     The basic current mirror is formed of two MOS transistors M3 and M4 having their gates connected together and their sources connected to a supply voltage V DD . To optimize the operation of the current mirror M3 and M4 are biased to operate in the saturated region on or near the boundary between the linear and saturated regions, that is, the output characteristic is: 
     
         V.sub.DS =V.sub.GS -V.sub.T 
    
     where 
     V DS  =drain to source voltage 
     V GS  =gate to source voltage 
     V T  =threshold voltage 
     The output characteristic is shown in FIG. 2, which is a graph of drain current as a function of drain to source voltage (I D  vs. V DS ) for a p-channel MOS device at various gate to source voltages, V GS . 
     Transistors M6 and M2 form a second stage of the current mirror wherein their gates are connected together and their sources are connected to the drains of M3 and M4, respectively. The drain of M2 is the output, node 5, of the mirror. The drain of M6 is connected to the sources of M5 and M7, the drain of M5 is connected to the source of M1, and the drain of M1 is connected to the drain of M7 as well as the gates of M1, M5 and M7, which forms the input node 2. The source of M5 is connected to the M3-M4 gates, and the drain of M5 is connected to the M2-M6 gates. 
     The relative dimensions and current densities of M7 and M5 are selected so that substantially all of the current in the series-parallel combination of M1-M5 and M7 passes through M7. Because the gate of M7 is connected to its drain, M7 operates on the V DS  =V GS  line, shown in FIG. 2, and node 3 in FIG. 1 is thus V GS  volts above node 2. Further, since the gate of M3 is connected to node 3, node 2 is (V GSM7  +V GSM3 ), or approximately 2 V GS  volts below V DD . Almost no current passes through M5 to M1, thus the voltage across M1, i.e., node 1 minus node 2, is the threshold voltage, V T , since M1 is diode-connected. The voltage difference between node 3 and node 1, i.e., the source to drain voltage of M5, is therefore (V GS  -V T ). Further, since the voltage at node 1 is applied to the gates of M6 and M2, nodes 7 and 4 are (V GS  +V T ) above node 2. 
     From the foregoing, the following equalities are apparent: 
     
         V.sub.SDM3 =V.sub.SDM4 =V.sub.DD -V.sub.N7 =V.sub.DD -V.sub.N4 
    
     
         V.sub.DD =V.sub.N2 +2V.sub.GS 
    
     
         V.sub.N7 =V.sub.N4 =V.sub.N2 +V.sub.GS +V.sub.T 
    
     
         V.sub.SD(M3,M4) =(V.sub.N2 +2V.sub.GS)-(V.sub.N2 +V.sub.GS +V.sub.T) 
    
     thus, for transistors M3 and M4 
     
         V.sub.SD =V.sub.GS -V.sub.T 
    
     where 
     V DD  =supply voltage 
     V SD  =source to drain voltage 
     V NX  =voltage at node X 
     V GS  =gate to source voltage 
     V T  =threshold voltage 
     Transistors M3 and M4 therefore operate on the characteristic line (V GS  -V T ), and the output voltage can approach to within 2(V GS  -V T ) of the supply voltage because of the two stages of the current mirror. 
     Referring now to FIG. 3 there is shown a second embodiment of the present invention wherein a current mirror is formed of two n-channel MOS transistors M1 and M2. M3 is a &#34;natural&#34; threshold device in which the unadjusted threshold voltage is typically about 0.6 volts less than the threshold voltage of M2. This difference in V T , together with the proper selection of current densities for the devices, forces M1 and M2 to operate at or near the boundary between the linear and saturated regions as in the above-described embodiment. Of course, p-channel devices may also be used if the threshold voltage of M3 is adjusted to be sufficiently lower than that of M2. 
     FIG. 4 shows a third embodiment of the invention wherein n-type MOS transistors M1 and M2 form the first stage of a current mirror with the input current passing through M1 and the output current passing through M2. M3 forms the second stage of the current mirror, as in the previous embodiments, with the source of M3 being connected to the drain of M2. In some applications it may be desirable to include a transistor series connected to M1, however, the illustrated embodiment shows the minimum number of transistors required to use this particular bias circuit. The gate and drain of a fourth transistor M4 are connected together and to the gate of M3 to provide the M3 bias voltage, which is also the gate to source voltage of M4. The source of M4 is connected to the sources of M1 and M2. The bias voltage is generated by a bias current I B  passing through M4. I B  is related to I IN  so that as I IN  changes the gate voltage on M3 will vary accordingly. The relative dimensions of M4 and the magnitude of I B  are selected to that M2 is in the saturated region, at or near the boundary between the linear and saturated regions, over the desired operating range of the current mirror, that is, V GS  of M4 must be greater than V GS  of M1 and M2. I B  may conveniently be generated by a current mirror (not shown) which also generates I IN . This circuit thus achieves the desired high impedance output with a minimum number of transistors. 
     Other embodiments and modifications of the present invention will readily come to those of ordinary skill in the art having the benefit of the teachings presented in the foregoing description and drawings. It is therefore to be understood that this invention is not to be limited thereto and that said modifications and embodiments are intended to be included within the scope of the appended claims.