Abstract:
Integrated circuit analysis is enhanced via a method and system for detecting defects associated with particular logic states of an integrated circuit. According to an example embodiment of the present invention, a constant current supply is applied to an integrated circuit. The voltage across the constant current supply is detected for each of a plurality of clock cycles of the integrated circuit, each clock cycle being representative of a logic state of the integrated circuit. The voltage detected at each clock cycle is compared, and the comparison is used to analyze the integrated circuit for a defect.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for analyzing and debugging circuitry within an integrated circuit. 
     BACKGROUND OF THE INVENTION 
     The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been an increase in difficulty of the processes used for manufacturing the devices. 
     As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual circuits are functional, it is also important to ensure that batches of circuits perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured. 
     Several testing techniques have been developed for integrated circuits for detecting failure modes such as gate-oxide shorts, bridging defects, parasitic transistor leakage, defective p-n junctions, and transistors with incorrect threshold voltages. Such faults may pass functional and logical testing, but can malfunction over time, causing reliability problems. Many of those faults cause elevated quiescent power supply current (I ddq ), which is typically several orders of magnitude greater than the I ddq  of a fault-free device. For example, in static random-access memories (SRAMs), most of the I ddq  testable faults are activated during the write/read cycles. By monitoring an output current level, I ddq  testing has been shown as an effective way for testing integrated circuits such as CMOS combinational circuits, and can also be effective for detecting SRAM defects that escape traditional voltage monitoring techniques. In typical I ddq  testing, the device under test (DUT) has a constant voltage power supply and the current is monitored for changes. These changes are used to analyze the DUT. One problem associated with I ddq  testing is the difficulty of measuring the I ddq  current. In particular, obtaining an accurate current measurement from a DUT exhibiting high current can be difficult, inefficient, and produce inaccurate results. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to integrated circuit analysis, and is exemplified in a number of implementations and applications, some of which are summarized below. 
     According to an example embodiment of the present invention, an integrated circuit device (DUT) is analyzed using a constant current source and a voltage detection device. The current source is electrically coupled to the DUT and the voltage is monitored while the current supply is held constant. Detected variations in voltage between test vectors at different clock cycles are used for evaluating the potential for a defect at the particular logic state associated with the clock cycle exhibiting a variation. By using a constant current source and monitoring the voltage, the difficulties associated with current measurement addressed hereinabove can be avoided. In this manner, the logic states having a defect can be isolated for additional testing, improving failure analysis of the DUT. 
    
    
     The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which: 
     FIG. 1 is a system for analyzing an integrated circuit, according to an example embodiment of the present invention; and 
     FIG. 2 is a graph of voltage versus clock cycle, according to another example embodiment of the present invention. 
    
    
     While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
     DETAILED DESCRIPTION 
     The present invention is believed to be applicable for a variety of different types of semiconductor devices, and the invention has been found to be particularly suited for integrated circuits that draw high current and require or benefit from analysis involving defect detection at various logic states. While the present invention is not necessarily limited to such devices, various aspects of the invention may be appreciated through a discussion of various examples using this context. 
     According to an example embodiment of the present invention, an integrated circuit device under test (DUT) is analyzed for defects under various DUT logic states. It has been discovered that, by coupling a constant current source to the DUT while monitoring the V ddq  voltage across the current source for various DUT clock cycles, variations in the monitored V ddq  between clock cycles can be used as an indication of a potential defect affecting the circuit. These variations can be used to discover and isolate defects in the circuit. Once the defects have been discovered, other failure analysis methods can also be used to perform further tests. This provides an efficient manner in which to detect, isolate, and analyze integrated circuit defects. 
     According to a more particular example embodiment of the present invention, FIG. 1 shows a system  100  adapted to analyze an integrated circuit. The system may be a dedicated system for analyzing the die using the analysis methods described herein, or may be part of another conventional failure analysis system, such as a light-induced voltage alteration (LIVA) or thermal-induced voltage alteration (TIVA) system. A die  110  is placed in a die holder  120 , and a power supply  130  is coupled to the die through the die holder. The voltage across leads  132  and  134  can be monitored (e.g., using conventional voltage measurement equipment  135 ) and used for analyzing the die. In one implementation, the power supply  130  is adapted to first supply a constant voltage, and the current is measured for a known logic state. Once the current is measured, the power supply is switched to a constant current mode, and is used to supply the measured current to the die. In another implementation, the power supply is specially adapted to input selected signals to the die, such as to simulate normal operation, to simulate an operational loop that induces a failure, and to cycle the die through clock cycles. 
     The system  100  optionally includes a controller  140  adapted to control the power supply  130 . In one implementation, the controller includes a computer having a memory adapted to store information, such as the signals supplied to the die or test data obtained in response to the signals. Test data, such as voltage data across the leads  132  and  134 , can be stored in memory along with data representing the signals provided to the die. The stored data can then be used to analyze the die. One example representation of stored voltage data is shown in FIG.  2 . 
     FIG. 2 is a graph of voltage versus clock cycle for a DUT, according to another example embodiment of the present invention. Ten clock cycles are shown, and voltage is plotted for each clock cycle. The graph is generated by first powering the device under test (DUT) and clocking it out of reset and into a known logic state. The clock and any signals being applied to the die are stopped, and a reference current being supplied to the die is measured. A power source having a constant current supply is then connected to the die with the current being set at the level of the reference current, and a reference voltage (V CC0 ) is obtained across the leads of the power supply. The die is then clocked (advanced one clock cycle) several times, and voltage measurements across the power supply are obtained for each clock cycle. 
     As circuitry in the die is operated (e.g., transistors switched), the voltage drops when power is drawn during a particular clock cycle. After the circuit operation takes place, the voltage returns to a level near V CC0 . In instances where there is a defect, such as in a circuit exhibiting leakage, the voltage doesn&#39;t necessarily return to a level that is as high as it would have been, absent the defect. Clock cycles having a voltage delta (difference from a reference voltage) that is significant represent clock cycles for which further analysis may be useful. For example, the graph shows voltage peaks (i.e., as spikes or mesas) at clock cycles  4  and  8 , wherein the voltage is below a threshold amount (V T ) less than V CC0 . The threshold amount is selected as a function of the particular die being tested and/or other operating conditions of the die. In one implementation, the threshold amount is in a range of between about 10 millivolts and 100 millivolts less than the reference voltage. Once clock cycles having a potential defect are identified, such as cycles  4  and  8  in FIG. 2, further analysis is performed on the die. 
     One cause of a voltage not reaching the threshold amount is the existence of excess current in the die. Excess current often results while the die is in a logic state in which an internal defect is affecting the circuit. By identifying the logic states that are affected, the defect source can be tracked down and tested further. For instance, the die can be clocked into the particular logic state exhibiting a below-threshold voltage peak and analyzed using other failure analysis techniques, such as LIVA or emission microscopy. This enables fault isolation that helps to speed the analysis process of integrated circuit dies. 
     The detected voltage can also be used in other manners for isolating a defect. For example, as an alternative to comparing the voltage at each clock cycle to V CC0 , comparisons may be made from cycle to cycle. Any significant change in the voltage is noted and used for further analysis. In addition, a voltage threshold (shown as V T  in FIG. 2) may be defined as a particular voltage level below the reference voltage that is sufficiently low to indicate the presence of a defect. When the voltage detected at a particular clock cycle does not reach V T , it is noted and used for further analysis. This is particularly useful in a testing arrangement, such as shown in FIG. 1, wherein the controller further includes a comparator. The comparator is adapted to generate a signal when the detected voltage does not reach V T  and, in response, the controller notes the clock cycle at which the voltage was detected. In another implementation, the threshold voltage is defined as a particular voltage level below a voltage level detected at a previous clock cycle. 
     In still another example embodiment of the present invention, a non-defective die having the same design as the defective die being analyzed is first used to determine the reference voltage V CC0  in a manner not inconsistent with the die analysis described herein. The non-defective die may also be used to determine voltages at each clock cycle and to generate a non-defective voltage plot. A reference voltage curve is obtained from the non-defective die. The defective die is then clocked as described herein and a test voltage curve is obtained and overlaid on the reference voltage curve. Voltage levels in the reference curve that are below those in the test curve represent logic states being affected by a defect in the circuit. 
     In another example embodiment of the present invention, a plurality of test vectors (e.g., patterns) are run on a die, and the supply voltage is monitored for all threshold voltages and potentially several vectors having lower thresholds are detected. Voltages not reaching a threshold voltage for a particular clock cycle represent a potential defect for a particular test vector. Vectors resulting in a detected defect are noted and used to identify potential defective circuit paths or elements. This is particularly useful for narrowing the number of potential defect sites and isolating selected circuitry for additional analysis. For example, when a large number (e.g., 10,000) test vectors are run on a die, defects may be observed on a selected number (e.g., 250) of test vectors. By identifying these selected test vectors, the source of the defect is narrowed to include a circuit path or element being operated during the selected vectors for which a defect is observed. In this manner, other circuit elements or paths that do not exhibit a defect when operated can be eliminated as a potential defect source, improving the ability to isolate defects. 
     While the present invention has been described with reference to several particular example embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention, which is set forth in the following claims.