Abstract:
A motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, and a voltage regulating circuit electronically connected to the first slot and the second slot. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulating circuit detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
   Relevant subject matter is disclosed in a co-pending U.S. patent application Ser. No.11/952,140, filed on the same date and entitled “MOTHERBOARD”, and a co-pending U.S. patent application with application Ser. NO. 11/766,105, filed on the Jun. 21, 2007, and entitled “MOTHERBOARD”, which are assigned to the same assignee as this patent application. 
   BACKGROUND 
   1. Field of the Invention 
   The present invention relates to motherboards, and particularly to a motherboard for supporting different types of memories. 
   2. Description of Related Art 
   Currently, a typical personal computer comprises a motherboard, interface cards, and peripheral accessories. The motherboard is the heart of the personal computer. On the motherboard, in addition to the central processing unit (CPU), the chip set, and the slots for installing the interface cards, it further includes memory module slots for installing memory modules. 
   Due to constant change in the computer industry, memories used in the computer have changed from DDR2 (Double Data Ram II) used in the past to higher speed memories such as DDR3 (Double Data Ram III). 
   Because DDR2 is cheaper than DDR3, the main board with DDR2 still is in demand in the market. The difference in operating DDR2 and DDR3 includes: DDR2 utilizes 1.8V VDD and 0.9V VTT, while DDR3 utilizes 1.5V VDD and 0.75V VTT. Currently, no motherboard is compatible with both DDR3 and DDR2. As a result, more motherboards have to be fabricated adding to production cost. 
   What is needed is to provide a motherboard capable of flexibly supporting different types of memories. 
   SUMMARY 
   An exemplary motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, and a voltage regulating circuit electronically connected to the first slot and the second slot. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulating circuit detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of memory mounted on the motherboard accordingly. 
   Other advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiment when taken in conjunction with the accompanying drawing, in which: 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawing is a circuit diagram of a motherboard for supporting different types of memories in accordance with the present invention. 
   

   DETAILED DESCRIPTION 
   Referring to the drawing, a motherboard for supporting different types of memories in accordance with an embodiment of the present invention includes a voltage regulating circuit  10 , a first slot  20 , and a second slot  30 . The first slot  20  is used for installing a first memory, such as a DDR2 memory. The second slot  30  is used for installing a second memory, such as a DDR3 memory. The first slot  20  includes a ground terminal to generate a ground signal when the first memory is mounted in the first slot  20 . The second slot  30  includes a ground terminal to generate a ground signal when the second memory is mounted in the second slot  30 . The first memory and the second memory are alternatively mounted on the motherboard. 
   The voltage regulating circuit  10  comprises a controller  12  having a feedback terminal and an output terminal, a filter  14  having an input terminal and an output terminal, a linear voltage regulator  16 , and a feedback circuit  18 . The output of the controller  12  is connected to the input terminal of the filter  14 , and the filter  14  outputs a VDD voltage at the output terminal thereof. The VDD voltage is transmitted to the linear voltage regulator  16 , and is converted into a VTT voltage transmitted to the first slot  20  and the second slot  30 . The output terminal of the filter  14  is connected to the first slot  20  and the second slot  30  to provide the VDD voltage. 
   The feedback circuit  18  comprises two transistors Q 1  and Q 2 , four resistors R 1 ˜R 4 , and a feedback resistor R 5 . The transistors Q 1  and Q 2  are PMOS transistors. The gate of the transistor Q 1  is connected to the ground terminal of the first slot  20  and to a 5V power source via the resister R 1 . The source of the transistor Q 1  is grounded. The drain of the transistor Q 1  is connected to the  5 V power source via the resistor Q 2  and to the gate of the transistor Q 2 . The gate of the transistor Q 2  is connected to the ground terminal of the second slot  30 . The source of the transistor Q 2  is grounded. The drain of the transistor Q 2  is grounded via the resistors R 3  and R 4  in turn and also connected to the feedback terminal of the controller  12  via the resistor R 3 . The feed back resistor R 5  is connected between the output terminal of the filter  14  and the feedback terminal of the controller  12 . The resistances of the resistors R 1  to R 4  are approximately 4.7 Kohms, 4.7 Kohms, 2.4 Kohms, and 1.2 Kohms respectively, and the resistance of the feedback resistor R 5  is approximately 1.1 Kohms. The operation of the feedback circuit  18  is premised upon the fact that the level of the feedback voltage Vfb is stable, in this preferred embodiment, the level of the feedback voltage Vfb is 0.78V. 
   When the DDR2 memory is mounted in the first slot  20 , the second slot  30  is idle. The ground terminal of the first slot  20  generates a ground signal. The transistor Q 1  is turned on, and the transistor Q 2  is turned off. According to the following formula: VDD=Vfb*(R 5 +R 4 )/R 4 , the voltage output from the controller  12  is 1.8V. The voltage is provided to the filter  14 , which filters and rectifies the voltage to provide a smooth voltage output. The VDD is provided to the feedback circuit  18  and the DDR2 memory mounted in the first slot  20 . The linear voltage regulator  16  is configured to receive the VDD voltage and provide a regulated output voltage of VTT (0.9V), which is provided to the DDR2 memory. 
   When the DDR3 memory is mounted on the second slot  30 , the first slot  20  is idle. The ground terminal of the second slot  30  generates the ground signal. The transistor Q 1  is turned off, the transistor Q 2  is turned on, and the resistor R 3  is connected in the circuit. According to the following formula: VDD=Vfb*(R 5 +Rx)/Rx, wherein Rx=(R 3 +R 4 )/R 3 *R 4 , the voltage output from the controller  12  is 1.5V. The voltage is provided to the filter  14 , which filters and rectifies the voltage to provide a smooth voltage output. The VDD is provided to the feedback circuit  18  and the DDR3 memory mounted in the second slot  30 . The linear voltage regulator  16  is configured to receive the VDD voltage and provide a regulated output voltage of VTT (0.75V), which is provided to the DDR3 memory. 
   Thus, the motherboard is capable of utilizing either the DDR2 or the DDR3, thus enhancing production capability and reducing production cost. 
   It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appterminaled claims are expressed.