Abstract:
A method for reading out an image sensor, the method includes the steps of integrating charge in a photodetector with the photodetector at a first capacitance; reading the resulting signal level at a first time with the photodetector at the first capacitance; changing the photodetector capacitance to a second capacitance; and reading the signal level associated with the photodetector at the second capacitance.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates generally to the field of image sensors and, more particularly, to increasing the dynamic range of image sensors using variable charge-to-voltage conversion capability. 
       BACKGROUND OF THE INVENTION 
       [0002]    Currently, image sensors have a predetermined dynamic range for capturing images. Some scenes require a large capture dynamic range that may exceed the capability of the image sensor. In this case, the captured scene may not be faithfully represented. Therefore, increasing the dynamic range of image sensors in addition to the normal mode of operation is desirable. 
         [0003]    The present invention overcomes the shortcomings of the prior art by providing an image sensor with variable sensitivity to convert captured photoelectron charge into a voltage. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides in a method for reading out an image sensor, the method comprising the steps of integrating charge in a photodetector with the photodetector at a first capacitance; reading the resulting signal level at a first time with the photodetector at the first capacitance; changing the photodetector capacitance to a second capacitance; and reading the signal level associated with the photodetector at the second capacitance. 
         [0005]    These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings. 
       ADVANTAGEOUS EFFECT OF THE INVENTION 
       [0006]    The present invention has the advantage of extended dynamic range by doing multiple transfer and sample operations and increasing the floating diffusion capacitance by connecting additional floating diffusions after each transfer and sample operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a schematic diagram of one embodiment of the present invention; 
           [0008]      FIG. 2  is a schematic diagram of a second embodiment of the present invention; 
           [0009]      FIG. 3  is a schematic diagram of a third embodiment of the present invention; 
           [0010]      FIG. 4  is a schematic diagram of a fourth embodiment of the present invention; 
           [0011]      FIG. 5  is a graph depicting linear capacitance and non-linear capacitance; and 
           [0012]      FIG. 6  is a digital camera of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]    Referring to  FIG. 1 , there is shown a schematic diagram (five transistor pixel or  5 T pixel) of three pixels  10  of the image sensor  20  of the present invention. Each pixel  10  includes a photosensitive region  30 , preferably a pinned photodiode, that collects charge in response to incident light. A transfer gate  40  transfers the charge to a charge-to-voltage conversion mechanism  50 , preferably a floating diffusion. It is noted that the floating diffusions  50  of each pixel  10  are electrically connected together as will be discussed in detail hereinbelow. A reset transistor  60  resets the floating diffusion  50  to a predetermined voltage. An amplifier  70 , preferably a source follower, senses and buffers the signal from the floating diffusion  50  for readout on an output bus  80 . 
         [0014]    A row select transistor  90  selects the particular row for readout. 
         [0015]    A bin select transistor  100  having a gate  105  is pulsed to combine charge on the floating diffusions  50 . Although three floating diffusions  50  are shown as combinable in  FIG. 1 , the number of floating diffusions  50  that are combined are design choices and any desired number of floating diffusions  50  are combinable. The sharing of floating diffusions  50  provides the ability to change the capacitance of the floating diffusions  50  depending on the number of floating diffusions  50  that are combined. 
         [0016]    In the above embodiments, the signal from the photodiodes  30  is read out in the following manner. To read out the photodiode  30  of the middle pixel in  FIG. 1 , for example, the middle readout structures (RG  60 , SF  70 , and RSEL transistor  90 ) are employed, but the floating diffusions  50  from all three rows are shared by turning on the two BSEL transistors  100 . The three floating diffusions  50  are reset using the RG transistor  60 , and the reset level is sampled in a sampling circuit (not shown and well known in the art). Next, the upper and lower floating diffusions  50  are disconnected by turning off the two BSEL transistors  100 , and the resulting reset level of the middle floating diffusion  50  is sampled. Charge is transferred from the middle photodiode  30  into the middle floating diffusion  50  by operating the middle TG gate  40 . The resulting signal is sampled. Note that the capacitance of the middle floating diffusion  50  may be insufficient by itself to hold all the accumulated charge in the photodiode  30 ; in this case, the charge will be shared between the photodiode  30  and the floating diffusion  50 , and the sampled signal will reflect a non-linearity as a consequence of this charge sharing. After this third sample is taken (two reset samples and a first signal sample), all three floating diffusions  50  are reconnected by means of the two BSEL transistors  100 ; when this happens, any signal charge on the middle floating diffusion  50  will spread out over the network of three floating diffusions  50 . The middle TG gate  40  is operated again to move any remaining charge from the middle photodiode  30  into the three floating diffusions  50 , and the resulting signal is sampled. The four samples captured, reset for the three connected floating diffusions  50 , reset for one floating diffusion  50 , signal on one floating diffusion  50 , and signal on three connected floating diffusions  50 , provide two fully correlated results as follows: three floating diffusions correlated signal=three floating diffusion signal−three floating diffusion reset; one floating diffusion correlated signal=one floating diffusion signal−one floating diffusion reset. 
         [0017]    Referring to  FIG. 2 , a four transistor ( 4 T) embodiment is shown. 
         [0018]    All of the transistors function the same except the BSEL is deleted. In order to change the capacitance of floating diffusion  50 , a gate (CSEL)  110  is added. This gate  110  is pulsed in order to change the capacitance. 
         [0019]    In the  4 T embodiment, the signal from the photodiodes is read out in the following manner. The CSEL gate  110  is operated to provide a smaller floating diffusion capacitance, the floating diffusion  50  is reset using the RG transistor  60 , and the reset level is sampled in a sampling circuit (not shown and well known in the art). Next, the CSEL gate  110  is operated to provide a larger floating diffusion capacitance, and the resulting reset level of the floating diffusion  50  is sampled. Charge is transferred from the photodiode  30  into the floating diffusion  50  by operating the TG gate  40 . The signal resulting from the transfer of charge to the larger floating diffusions capacitance is sampled. After this third sample is taken (two reset samples and a first signal sample), the CSEL gate  110  is operated to provide a smaller floating diffusion capacitance, and the signal resulting from the application of the same charge to the smaller floating diffusion capacitance is sampled. The four samples captured, reset for the smaller and larger floating diffusion capacitances, and signal resulting from application of accumulated photodiode charge to the larger and smaller floating diffusion capacitances, provide two fully correlated results as follows: larger floating diffusion capacitance correlated signal=larger floating diffusion capacitance signal−larger floating diffusion capacitance reset; smaller floating diffusion capacitance correlated signal=smaller floating diffusion capacitance signal−smaller floating diffusion capacitance reset. 
         [0020]    Referring to  FIG. 3 , in an alternative embodiment, a three-transistor ( 3 T) embodiment is shown. In a three transistor active pixel, it is well known that the capacitance of the photodiode  30  provides the charge-to-voltage conversion, with the integrated photodiode charge providing a voltage by means of the photodiode capacitance. Hence, compared to the  4 T embodiment, the floating diffusion (FD) and transfer gate (TG) are eliminated. The voltage resulting from the integrated photodiode charge and the photodiode capacitance is applied to the gate of a transistor  70 , preferably a source follower, to allow the voltage to be read out. This embodiment includes a gate (CSEL)  110  that is selectively energized to change the capacitance of the photodiode  30 . As in the preferred embodiment, there is a row select transistor  90  and a reset transistor  60  which function in the same manner described hereinabove. 
         [0021]    In the  3 T embodiment, the signal from the photodiodes  30  is read out in the following manner. After integrating charge in the photodiode  30  for some period of time with the CSEL gate  110  operated to provide a larger photodiode capacitance, the voltage resulting from the integrated charge and the larger photodiode capacitance is sampled. Next, the CSEL gate  110  is operated to provide a lower photodiode capacitance, and the voltage resulting from the integrated charge and the smaller photodiode capacitance is sampled. Next, the reset transistor  60  is operated to reset the photodiode  30  by removing the integrated charge with the CSEL gate  110  operated to continue providing the smaller photodiode capacitance, the resulting reset voltage is sampled. Finally, the CSEL gate  110  is operated to provide a larger photodiode capacitance, and the resulting reset voltage is sampled. The four samples captured, signal for the smaller and larger photodiode capacitances, and reset for the larger and smaller photodiode capacitances, provide two differential results as follows: larger photodiode capacitance differential signal=larger photodiode capacitance signal−larger photodiode capacitance reset; smaller photodiode capacitance differential signal=smaller photodiode capacitance signal−smaller photodiode capacitance reset. As is well understood for the operation of a  3 T pixel, the resulting differential signals cannot be regarded as fully correlated because the sampled reset level is the result of a reset operation that is different from the reset that preceded the integration and measurement of the signal. Nevertheless, the differential signal is beneficial for eliminating source follower offset which varies from pixel to pixel due to variations in threshold for the source follower transistor. 
         [0022]    Referring to  FIG. 4 , an alternative embodiment of the present invention, there is shown a  4 T pixel structure as has previously been described having a non-linear capacitance  120  connected to the node controlling the gate of the source follower  70 .  FIG. 5  shows the charge-to-voltage behavior of both a linear capacitance and a non-linear capacitance. Such a non-linear capacitance may be provided by a common MOS transistor with the source, drain, and channel regions providing one plate of the capacitor and the gate providing the other. If the source, drain, and channel material are connected together and held at one potential, and the gate held at another potential that is below the threshold voltage of the transistor, a non-linear capacitance is provided. This non-linear capacitance may be employed to provide a pixel level compression operation on the signal provided by the pixel. In the non-linear capacitance shown in  FIG. 5 , changes in lower charge signals have relatively higher changes in voltage than higher charge signals. This pixel arrangement is operated in the commonly understood way by resetting the non-linear capacitance  120  of the source follower gate node, sampling the resulting voltage, transferring charge from the photodiode  30  to the floating diffusion  50  (and thereby to the non-linear capacitance, since the floating diffusion node is in common with the non-linear capacitance node), and sampling the new voltage. 
         [0023]      FIG. 4  also illustrates an additional mode of operation by providing selectable additional capacitance via the CSEL control  110 . The CSEL control  110  is used to change the non-linear capacitance of the source follower node. In  FIG. 4 , the change in capacitance is made possible by a gate adjacent to the floating diffusion  50 : changing the potential of the gate changes the capacitance of the floating diffusion  50 , and thereby the overall non-linear capacitance of the source follower node. 
         [0024]      FIG. 6  is a side view of a digital camera  130  of the present invention having the image sensor  20  of the present invention. 
         [0025]    The invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention. 
       PARTS LIST 
       [0000]    
       
           10  pixels 
           20  image sensor 
           30  photosensitive region 
           40  transfer gate 
           50  floating diffusion 
           60  reset transistor 
           70  amplifier 
           80  output bus 
           90  row select transistor 
           100  bin select transistor 
           105  gate 
           110  gate 
           120  non-linear capacitance 
           130  digital camera