Abstract:
The invention relates to an embedded system, and in particular, to an embedded system capable of compensating setup time violation. An embedded system comprises a serial flash and an access circuit. The serial flash further comprises an input pin and an output pin. The access circuit further comprises a processor, a shift register, a serial flash controller, and a time compensator. The input pin receives an adjusted input signal and the output pin sends an output signal. The processor controls the operation of the access circuit. The serial flash controller enables an operational clock of the access circuit. The time compensator compensates a timing of the output signal by referring to the operational clock. The shift register converts data in parallel form to serial form.

Description:
BACKGROUND 
     The invention relates to an embedded system, and in particular, to an embedded system for compensating setup time violation. 
     Embedded systems typically comprise flash memory such as serial flash or parallel flash for storing data and code. An embedded system requires a plurality of pins (address pins, data pins, and control pins) to access a parallel flash. Fewer pins are required to access a serial flash. Data rate of the serial flash is, however, getting faster and faster to make the setup time of various signals becomes critical and sensitive. 
     SUMMARY 
     An object of the invention is to provide an embedded system capable of compensating setup time violation. The embedded system comprises a serial flash and an access circuit. The serial flash further comprises an input pin and an output pin. The access circuit further comprises a processor, a shift register, a serial flash controller, and a time compensator. The input pin receives an adjusted input signal and the output pin sends an output signal. The processor controls the operation of the access circuit. The serial flash controller enables an operational clock of the access circuit. The time compensator compensates a timing of the output signal by referring to the operational clock. The shift register converts data in parallel form to serial form. 
     Another object of the invention is to provide an embedded system capable of adjusting time. The embedded system comprises a serial flash and an access circuit. The serial flash further comprises: a first input pin, a second input pin, and an output pin. The access circuit further comprises a processor, a shift register, a serial flash controller, a first time adjuster, and a second time adjuster. The first input pin receives an adjusted operational clock. The second input pin for receives an adjusted input signal. The output pin sends an output signal. The processor controls the operation of the access circuit. The serial flash controller enables an operational clock of the access circuit. The first time adjuster adjusts a timing of the operational clock to generate the adjusted operational clock. The second time adjuster adjusts a timing of an input signal to generate the adjusted input signal. The shift register converts data in parallel form to serial form. 
     Another object of the invention is to provide a method of controlling an embedded system. The method comprises: receiving an adjusted input signal; sending an output signal; enabling an operational clock; compensating a timing of the output signal by referring to the operational clock; converting data in parallel form to serial form. 
     Another object of the invention is to provide a method of controlling an embedded system. The method comprises: receiving an adjusted operational clock; receiving an adjusted input signal; sending an output signal; enabling an operational clock of the access circuit; adjusting a timing of the operational clock to generate the adjusted operational clock; adjusting a timing of an input signal to generate the adjusted input signal; converting data in parallel form to serial form. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
       The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which: 
         FIG. 1  shows a block diagram of an embedded system according to a first embodiment of the invention; 
         FIG. 2  shows a timing diagram of a plurality of signals in  FIG. 1 ; 
         FIG. 3  shows a circuit diagram of the phase sampler in  FIG. 1 ; 
         FIG. 4A  shows a circuit diagram of the phase sampler in  FIG. 1 ; 
         FIG. 4B  shows a timing diagram of a plurality of signals in  FIG. 4A ; 
         FIG. 5  shows a circuit diagram of the phase sampler in  FIG. 1 ; 
         FIG. 6  shows a block diagram of an embedded system according to a second embodiment of the invention; 
         FIG. 7  shows a circuit diagram of one delay chain in  FIG. 6 ; 
         FIG. 8  shows a block diagram of an embedded system according to a third embodiment of the invention; 
         FIG. 9  shows a circuit diagram of the clock selector  819 ; 
         FIG. 10A-FIG .  10 D show timing diagrams of a plurality of signals in  FIG. 8 ; 
         FIGS. 11A˜11C  show timing diagrams of a plurality of signals in  FIG. 8  in different situations; 
         FIG. 12  shows a block diagram of an embedded system according to a fourth embodiment of the invention; 
         FIG. 13  is a flow chart of a control method applied to an embedded system; 
         FIG. 14  is a flow chart of a control method applied to a serial flash controller. 
     
    
    
     DESCRIPTION 
     A detailed description of the invention is provided in the following. Please refer to  FIG. 1 .  FIG. 1  shows a block diagram of an embedded system  100  according to a first embodiment of the invention. The embedded system  100  comprises a chip (e.g. ASIC)  110  and a serial flash  120 . The chip  110  can read data from or write data to the serial flash  120  through three I/O pins C, Q, D. The chip comprises a processor (e.g. CPU)  112 , a plurality of parallel-to-serial shift registers  114 , a serial flash controller  116 , and a phase sampler  118 . The processor  112  controls the entire operation of the chip  110 . The plurality of parallel-to-serial shift registers  114  convert parallel signals to serial signals. The serial flash controller  116  enables a free-run clock CLK source  to generate an operational clock CLK inchip  for a period of Count bit  cycles. Count bit  is a parameter provided by the processor  112 . The clock CLK inchip  is taken as the operational clocks of the chip  110  and the serial flash  120 . If there is no data traffic between the chip  110  and the serial flash  120 , the operational clock CLK inchip  is gated; Otherwise, the operational clock CLK inchip  is activated. An input signal DATA-IN inchip  is shifted from the chip  110  to the serial flash  120  through the input pin D. An output signal DATA-OUT outchip  is shifted from the serial flash  120  to the chip  110  through the output pin Q. The output signal DATA-OUT outchip  is sent into the chip  110  to become an adjusted output signal DATA-OUT inchip  after being adjusted for a propagation time. Unfortunately, a setup time of the adjusted output signal DATA-OUT inchip  is shortened and inadequate due to the above-mentioned propagation time. Hence, the phase sampler  118  samples the adjusted output signal DATA-OUT inchip  to generate a compensated output signal DATA-OUT sampled  to solve the shortened setup time problem. A detailed description of solving the setup time problem is provided in the following. 
     Please refer to  FIG. 1  and  FIG. 2  at the same time.  FIG. 2  shows a timing diagram of a plurality of signals in  FIG. 1 . Please note that the data signals are fetched at positive edges of the clock in this figure. However, data signals can also be fetched at the negative edges of the clock. The data signals and clocks are described in greater depth in the following. The operational clock CLK inchip  is sent into the serial flash  120  to become an adjusted operational signal CLK outchip  after being adjusted for a propagation time. The input signal DATA-IN inchip  is sent into the serial flash  120  to become an adjusted input signal DATA-IN outchip  after being adjusted for a propagation time. The output signal DATA-OUT outchip  is sent into the chip  110  to become the adjusted output signal DATA-OUT inchip  after being adjusted for a propagation time. It can be observed that the latency between the operational clock CLK inchip  and the adjusted output signal DATA-OUT inchip  is enlarged (about twice the propagation time) and the setup time of the adjusted output signal DATA-OUT inchip  is thus shortened. In this embodiment, in order to compensate for the shortened setup time, the phase sampler  118  samples the adjusted output signal DATA-OUT inchip  according to a sampling signal SAMPLE sampled  to generate a compensated output signal DATA-OUT sampled  to solve the shortened setup time problem. 
     Additionally, a first sample of the sampling signal SAMPLE sampled  must be discarded. In some embodiments, the higher the clock speed, the more samples are discarded. The discarded sample number Count discard  is a parameter provided by the processor  112 . A detailed-description of the phase sampler  118  is provided in the following. 
     Please refer to  FIG. 1  and  FIG. 3  at the same time.  FIG. 3  shows a circuit diagram of the phase sampler  118  in  FIG. 1 . The phase sampler  118  comprises a delay chain  310 , a multiplexer (MUX)  320 , and a register  330 . The delay chain  310  further comprises a plurality of delay buffers. Each delay buffer can provide different delay phases of the adjusted output signal DATA-OUT inchip . The MUX  320  selects one signal from the plurality of delay buffers as the sampling signal SAMPLE sampled  according to a phase selection parameter PHASE select . There are various ways to determine the phase selection parameter PHASE select ; one is to utilize a trial-and-error method to attempt every phase and compare the read back data signal with a pattern (e.g. golden pattern) stored in memory (not shown) to find a best phase selection parameter PHASE select . The adjusted output signal DATA-OUT inchip  can then be sampled to generate the compensated output signal DATA-OUT sampled  according to the sampling signal SAMPLE sampled  through the register  330 . Note that there are various kinds of phase samplers. Other kinds of phase samplers are detailed in the following. 
     Please refer to  FIG. 4A  and  FIG. 4B  at the same time.  FIG. 4A  shows another circuit diagram of the phase sampler  118  in  FIG. 1 .  FIG. 4B  shows a timing diagram of a plurality of signals in  FIG. 4A . The phase sampler  118  comprises a delay chain  410 , multiplexers (MUX)  420  and  450 , and registers  430  and  440 . A detailed description of elements in  FIG. 4A  sharing the same labels as in  FIG. 3  is omitted for the sake of brevity. In  FIG. 4A , a key difference with  FIG. 3  is that an extra negative-edge-clock-triggered register  440  is added in order to reduce the number of delay buffers in the delay chain  410 . The registers  430  and  440  utilize positive and negative edge triggered clocks CLK pos , and CLK neg  to sample the adjusted output signal DATA-OUT inchip  and generate a positive edge triggered data signal DATA-OUT pos  and a negative edge triggered data signal DATA-OUT neg , respectively. Finally the MUX  450  selects the positive edge triggered data signal DATA-OUT pos  and the negative edge triggered data signal DATA-OUT neg  periodically to output the compensated output signal DATA-OUT sampled . Please refer to  FIG. 4B . The required number of delay buffers is reduced by half (compared with  FIG. 3 ) since the positive (rising) and negative (falling) edges of the operational clock CLK inchip  are utilized at the same time. 
     Please refer to  FIG. 5 .  FIG. 5  shows another circuit diagram of the phase sampler  118  shown in  FIG. 1 . The phase sampler  118  comprises delay chains  510  and  540 , multiplexers (MUX)  520  and  550 , and a register  530 . A detailed description of elements in  FIG. 5  sharing the same labels as in  FIG. 3  is omitted for the sake of brevity. In  FIG. 5 , a key difference with  FIG. 3  is that an extra delay chain  540  is added in order to tune phases in deeper depth. It is clear that if the sampling phase can be tuned continuously, the optimal sampling phase will be easily obtained. There exists, however, a minimum time unit of the delay chain, which limits the sampling phase to being tuned continuously. If the minimum time unit is too long, the hold time may not be enough. To compensate for the hold time, the delay chain  540  is added to further tune the phase of the adjusted output signal DATA-OUT inchip  to generate the hold time compensated data signal DATA-OUT hold-compensated . 
     Please refer to  FIG. 6 .  FIG. 6  shows a block diagram of an embedded system  600  according to a second embodiment of the invention. A detailed description of elements in  FIG. 6  sharing the same labels as in  FIG. 1  is omitted for the sake of brevity. In the second embodiment, a key difference with the first embodiment is that a phase sampler  118  is replaced with a plurality of delay chain modules. The delay chain modules  618  and  619  are utilized to tune phases of the operational clock CLK inchip  and the input signal DATA-IN inchip , respectively. It can also solve the shortened setup time problem of the output signal DATA-OUT outchip . In other words, the phase of the output signal DATA-OUT outchip (embodiment 1) can be tuned or the phases of the operational clock CLK inchip  and the input signal DATA-IN inchip  (embodiment 2) can be tuned. 
     Please refer to  FIG. 6  and  FIG. 7  at the same time.  FIG. 7  shows a circuit diagram of one delay chain module in  FIG. 6 . The delay chain module  618  comprises a delay chain  710  and a MUX  720 . The delay chain  710  further comprises a plurality of delay buffers. Each delay buffer can provide different delay phases of the operational clock CLK inchip . The MUX  720  selects one signal from the plurality of delay buffers to accomplish the task of phase tuning. 
     Please refer to  FIG. 8˜FIGS .  10 A- 10 D at the same time.  FIG. 8  shows a block diagram of an embedded system  800  according to a third embodiment of the invention. A detailed description of elements in  FIG. 8  sharing the same labels as in  FIG. 1  is omitted for the sake of brevity. In the third embodiment, a key difference with the first embodiment is that a clock selector  819  is added in the embedded system  800  to provide the operational clock CLKsource with tunable frequency. The process of solving a critical path problem will be further provided later. Please refer to  FIG. 9 .  FIG. 9  shows a circuit diagram of the clock selector  819 . The clock selector  819  is a clock divider, which comprises a plurality of registers  910  and a MUX  920 , to select a proper free-run clock CLKsource from a plurality of clocks with different frequencies. Please note that there are various kinds of clock selectors. The clock divider is only taken as an example, not a limitation. Please refer to  FIGS. 10A-10D .  FIGS. 10A-10D  show a timing diagram of a plurality of signals in  FIG. 8 . Please note that the data signals are fetched at positive edges of the clock in this figure. Assume that the parameter Countbit is equal to M+N wherein M and N are positive integers respectively representing the number of bits transmitted to and received from the chip  810 . M bit data is transmitted in the data-in phase, X bit data is discarded in the data-out phase according to the parameter Countdiscard, (N−X) bit data is received in the data-out phase, and X bit data is further received in the data-out phase to compensate for the discarded X bit data according to the parameter Countcompensate. In other words, although X bit data is discarded, the total received bit data is still equal to N ((N−X)+X=N). In this embodiment, the variable X here is equal to 1. A detailed description of dealing the critical path issue is provided in the following. 
     Please refer to  FIGS. 11A˜11C .  FIGS. 11A˜11C  show timing diagrams of a plurality of signals in  FIG. 8  in different situations. In  FIG. 11A , the frequency of the operational clock CLK inchip  is too low to induce the critical path problem. However, in  FIG. 11B  and  FIG. 11C , the frequency of the operational clock CLK inchip  is high enough to induce the critical path problem. The frequency of the operational clock CLK inchip  is said to be high if it satisfies the following equation:
 
 T−Δt&lt;T   setup   +T   trans  
 
     Wherein T is a period of the operational clock CLK inchip , Δt is a time difference between an edge of the operational clock CLK inchip  and a sampling time of the sampling signal SAMPLE sampled , T setup  is a setup time depending on a manufacturing process, and T trans  is affected by the distance between the phase sampler  818 , and the parallel-to-serial shift registers  814  is a time that the compensated output signal DATA-OUT sampled  becomes valid after the sampling time.  FIG. 11A  shows that there is no setup time violation in the compensated output signal DATA-OUT sampled  since no critical path problem occurs and therefore no compensation is required.  FIG. 11B  shows the setup time violation in the compensated output signal DATA-OUT sampled  and hence the compensated output signal DATA-OUT sampled  is incorrect.  FIG. 11C  shows the setup time violation compensation in the compensated output signal DATA-OUT sampled . A detailed description of the setup time violation compensation due to the critical path issue is provided in the following. 
     Please refer to  FIG. 11C . The sampling phase of the phase sampler  814  is adjusted to make the valid region of the compensated output signal DATA-OUT sampled  overlap with the positive edge of the operational clock CLK inchip . Then the discard count parameter is increased to delay one clock cycle of the compensated output signal DATA-OUT sampled  to finish the setup time violation compensation procedure. Finally, the setup time violation of the compensated output signal DATA-OUT sampled  is compensated. 
     Please refer to  FIG. 12 .  FIG. 12  shows a block diagram of an embedded system  1200  according to a fourth embodiment of the invention. A detailed description of elements in  FIG. 12  sharing the same labels as in  FIG. 8  is omitted for the sake of brevity. In the fourth embodiment, a key difference with the third embodiment is that a plurality of delay chain modules  1231 ˜ 1233  are added to compensate for the skew due to physical layout of the chip  1210 . 
     Please refer to  FIG. 13 .  FIG. 13  is a flow chart of a controlling method applied to an embedded system. The steps of the method are given in the following.
         Step  1302 : Select a lower frequency at which the read-back data from the serial flash is correct.   Step  1304 : Store the read-back data into its memory as a golden pattern.   Step  1306 : Select a higher frequency and try every set zero phase. Discard the first sample in the data-out phase.   Step  1308 : Read back data from the serial flash and compare the read-back data with the golden pattern.   Step  1310 : Determine if the comparison result is matched and if the data is correct. If yes, proceed to step  1314 ; Otherwise proceed to step  1312 .   Step  1312 : Increase sampling phase.   Step  1314 : Use the current selected frequency as the operational frequency.       

     Please refer to  FIG. 14 .  FIG. 14  is a flow chart of a control method applied to a serial flash controller. The steps of the method are given in the following.
         Step  1402 : Start (initial value of Count bit  is equal to M+N−1).   Step  1404 : In each cycle, shift out one bit of the parallel-to-serial shift register to a serial flash through its input pin and count down the value Count bit .   Step  1406 : Determine if the value Count bit  is equal to N−1? If yes, proceed to step  1408 ; Otherwise proceed to step  1404 .   Step  1408 : In each cycle, count down the value of Count discard  and the value of Count bit .   Step  1410 : Determine if the value Count discard  is equal to zero. If yes, proceed to step  1412 ; Otherwise proceed to step  1408 .   Step  1412 : In each cycle, shift in one bit from the serial flash through its output pin and count down the value Count bit .   Step  1414 : Determine if the value Count bit  is equal to zero. If yes, proceed to step  1416 ; Otherwise proceed to step  1412 .   Step  1416 : Stop feeding clock and count down a compensated value X to zero.   Step  1418 : Determine if the value X is equal to zero? If yes, proceed to step  1420 ; Otherwise proceed to step  1416 .   Step  1420 : Stop feeding clock to stop shift in data signal from the phase sampler.   Step  1422 : End.       

     While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.