Abstract:
Within an electrophotographic copying machine having a predetermined number of sensing elements each deriving an output indicative of respective one of operating states of the machine, there is provided a single chip, MOS-LSI microprocessor responsive to the outputs of the sensing elements to control the machine in a sequential or serial mode. The microprocessor contains storage means storing a string of instructions, processing means to fetch sequentially the instructions from the storage means and to deal with the fetched instructions, first input means to receive synchronizing signals generated within the body of the machine, first output means to determine with aid of the processing means whether any synchronizing signal is inputted via the first input means and to produce confirmation signals after confirming the sensed operating states of the machine, second input means to introduce through the sensing elements the confirmation signals supplied via the first output means, and a second output means to process with aid of the processing means the signals received by the first input means and the second input means and to consequently produce control signals effective to control operation of the machine.

Description:
This application is a continuation of application Ser. No. 794,140 filed on May 21, 1977, which is now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention pertains to a control for an electrophotographic copying machine and, more particularly, to a method for controlling an electrophotographic copying machine by means of a single control element. 
     It is conventional in the art of an electrophotographic copying machine that a plurality of microswitches are provided for sensing events in the sequence of operation of the machine, the respective outputs of the microswitches being useful to determine the next succeeding events. 
     Briefly speaking, in the electrophotographic copying machine, there is provided a photo-sensitive member or a master paper carrying a photoconductive layer deposited on the upper surface of an electrically conductive layer. First, uniform charge is carried out on the photoconductive layer on the master paper. If the photoconductive layer is exposed to a light pattern, the corresponding electrostatic latent image is formed thereon. Thereafter, the latent image is developed in a visual form by means of toners through a development station. A copy sheet after being fed is forced into a close contact position with the photosensitive member to transfer the toner image onto the copy sheet which in turn is sent to a fixing station for the purpose of fixing the toner image. The copy sheet is finally sent to an outlet. 
     As briefly stated, the sequence of copying operation consists of the charging, light exposing, developing, transferring, fixing steps, etc., and these steps are under control of the microswitches which sense the feeding states of the copy sheet and the rotation position of the photosensitive drum. 
     In this case, a control circuit is essentially complicated and needs a number of wirings communicating with the microswitches. The control circuit is typically composed of cascade connected stages of TTL-IC&#39;s. Taking an example of the charging station, the control circuit provides charging control signals and operates the charging station via a driver circuit. However, the microswitches cannot be focused on a single position because of operational and physical problems. 
     Meanwhile, solenoids are employed as a means of transducing respective sensing outputs inclusive ones indicative of copy sheet jam into mechanical outputs. There is created a possibility that the whole of the machine inclusive of these solenoids serves as a source of noises for the electronic control circuits. It is obvious that the control circuits undergo the influences of the noise source because of complexity and extended length of wirings. In addition, while the essential steps of the machine such as the charging, the light exposure and movement of an original table are carried out in synchronization of the master paper, the control circuits operate in response to signals inputted in an asynchronous mode. Therefore, they are susceptible to noise. 
     The control for the electrophotographic copying machine needs a sufficiently long period of time to return of the original table upon operation of a print start switch. Nevertheless, it is not necessarily required to perform the sensing operations of the microswitches in a parallel fashion. If time permits, the operating states of the family of the switches can be confirmed in a serial fashion. Such conversion into the serial control permits extra wirings to be avoided and maximum allowance for noise to be enhanced. 
     SUMMARY OF THE INVENTION 
     To achieve the above, in accordance with the present invention, a microprocessor implemented with a one-chip, one-package, MOS-FET ROM-RAM scheme is employed to provide a control for copying operation. 
     The micro-processor is one that operates sub-divided digital control and arithmetic circuits under control of a string of instructions stored in a read-only memory (ROM) together with transmission with a read-write memory (RAM). 
     Fortunately, the inherent disadvantages of the microprocessor that the processing speed thereof is much longer is negligible as compared with the normal operating speed of the electrophotographic copying machine. Therefore, the combined copying machine and micro-processor is very preferable. 
     In particular, employment of MOS-FET&#39;s provides less or no power consumption and enhances degree of integration as compared with TTL&#39;s. 
     In addition, a considerable reduction in the size of the electronic control circuit is realized by employing the micro-processor for controlling the copying machine. In other words, the control circuit needs merely a single element that is the micro-processor. This enhances degrees of reliability and service and eliminates the influences of incoming noises. Interconnections are simplified because confirmation as to the respective states of the copying machine, for example, sensed by the micro-switches is performed in a series fashion. Moreover, when it is desired to modify the specification of the machine itself or to accommodate the machine to modification in its peripheral tools in future, all that is necessary is to modify the micro-processor. These advantages are not expected at all in accordance with the conventional parallel controlled copying machine. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects and novel features of the present invention are set forth in the appended claims and the present invention as to its organization and its mode of operation will be understood from a consideration of the following detailed description of the preferred embodiments when used in connection with the accompanying drawings; 
     FIG. 1 is a sectional-view showing construction of an electrophotographic copying machine embodying the present invention; 
     FIG. 2 is a circuit diagram showing a power supply used in the machine of FIG. 1; 
     FIG. 3 is a block diagram showing a control for the machine; 
     FIG. 4 is a front view showing a disc adapted to rotate in union with a rotary member and to generate a series of synchronizing signals; 
     FIG. 5 is a block diagram showing implementation of a control element of the present invention; 
     FIG. 6 is a diagram showing a string of instructions contained in a storage of the control element; 
     FIGS. 7 through 10 are logic diagrams showing counters and registers employed to address the storage shown in FIG. 5, wherein FIG. 7 shows a stack register associated with page addressing, FIG. 8 shows a counter associated with step addressing, FIG. 9 shows a counter associated with page addressing and FIG. 10 shows a stag register associated with step addressing; 
     FIG. 11 is a time chart showing clock signals derived from a clock generator in FIG. 5; 
     FIG. 12 is a diagram for illustrating operation of a RAM in FIG. 5; 
     FIG. 13 is a logical gate diagram for illustrating operation of an adder of FIG. 5; 
     FIG. 14 is a logical gate diagram for illustrating operation of an accumulator of FIG. 5; 
     FIGS. 15 through 28 are diagrams showing instructions written into a ROM on page P 0  to P 13  for controlling the copying machine; 
     FIGS. 29 through 34 are flow charts associated with the instructions shown in FIGS. 15 through 28; 
     FIG. 35 shows storage positions in the RAM of portions to be controlled; 
     FIG. 36 shows storage positions of flip-flops stored in the RAM; 
     FIG. 37 is a block diagram showing input and output terminals of the control element; 
     FIGS. 38(a) and 38(b) are time charts showing the operating states of the portions to be controlled; and 
     FIG. 39 is a time chart showing exchange of a photosensitive drum. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     First of all, construction of an electrophotographic copying machine embodying the present invention will be discussed briefly with reference to FIG. 1. 
     There is provided a rotary drum 1 which rotates about an axis 2 at a fixed rate in the direction denoted by the arrow. The drum 1 is removably covered with a master paper 3, namely, a light-sensitive member having a photoconductive layer at its upper surface and an electrically conductive base at its rear surface. Although the master paper 3 is not illustrated herein, its end position is arrested by means of a finger means secured about the rotary drum 1. Therefore, the master paper 3 is secured about the drum 1. When the old paper 3 is to be replaced by a new one, the finger means is opened so that the old paper 3 is sent to an outlet 5 and at the same time a new paper 3 is introduced into an inlet 4, being arrested by the finger means. This operation is carried out in union with rotation of the drum 1. 
     A microswitch MS 7  disposed adjacent the inlet 4 determines whether the master paper member 3 is entered. As discussed below, an exchange cycle is executed for the master paper 3 as far as the switch MS 7  is in the ON state. Description of details of the exchange scheme is omitted herein because it is of no particular importance in understanding the present invention. 
     A variety of means available for forming an image corresponding to an original on the surface of the master paper 3 are placed in close proximity with the rotary drum 1. A charger 6 is provided for affording uniform charge to the surface of the master paper 3. The charger 6 produces a high voltage effective to provide the surface of the master paper 3 with uniform charge when a high voltage generation region CHVU is activated as shown in FIG. 2. This activation is executed through a charging relay and its contact CHVR-a. 
     A light exposure station 7 is provided where a light image is applied onto the charge master paper 3, thereby to form its corresponding electrostatic light image. The light exposure is carried out in a manner that an original table 8 carrying an original to be copied thereon is illuminated through a lighting means 9 and light reflected from the original is utilized through an optical system 10. 
     The original table 8 moves in synchronization with the rotary drum 1. In other words, the original table 8 begins to rotate as soon as the light-sensitive member on the rotary drum 1 has arrived at the light exposure station 7. The rate of movement of the original table is, of course, equal to the rotation ratio of the drum 1. 
     A development station 11 charges the electrostatic latent image into a visual image through the use of toners. 
     A charger 12 is provided for transportation of the toner image onto a copy receiving paper 13. The paper 13 is automatically fed via a feeding roller 20 and led via a first roller 21 into the interior of the machine. The feeding of the paper is prohibited by a paper stopper 14 for a while. Introduction of the paper is sensed by a microswitch MS 1 . When the rotary drum 1 rotates by a certain degree under the circumstances that the microswitch MS 1  senses the introduced paper, the stopper 14 is opened so that the transportation paper 13 is fed in good time and forced into close contact position with the master paper 3 bearing the toner image. Through the charger 12 the toner image is transported onto the copy receiving paper 13. A pick-off means 15 serves to remove the copy paper 13 from the master paper 3. 
     Upon removal of the copy paper 13 from the master paper 3, the paper 13 is attached to a conveying belt 15a with aid of absorption power created within the pick-off means 15. A second microswitch MS 2  secured adjacent the pick-off means 15 senses separation of the copy paper. 
     At this stage the toner image has not yet been transferred on the paper 13. The fixture of the toners is needed. This is accomplished by advancing the paper 13 toward a fixing station 16 through the conveying belt 15a. 
     The toner fixing station 16 includes a heating lamp HL as a heating source to effect the fixing procedure. The fixing station 16 bears a range of the optimum temperatures. The machine will fail to achieve the copying operation unless the optimum temperatures are exceeded. The optimum temperatures are about 300° C.. It is noted that a paper tray 17 in the fixing station 16 is placed as denoted by the solid line when power is thrown, and shifted to the position denoted by the dotted line when power is opened. This state is sensed by a microswitch MS 8 . The reason why the tray 17 is shifted upon removal of power supply is that the paper is isolated from the heating lamp HL to prevent combustion and to facilitate removal of the paper 13 in the event of paper jamming. 
     The paper 13 travels to an outlet 5 by rotation of a feeding roller 22. A microswitch MS 3  is positioned adjacent the outlet 5 to sense the leaving paper. A driving roller 23a and a follower roller 23b in combination are useful to sense a slip roller jam. As far as the paper 13 travels in a normal fashion, rotation of the driving roller 23a is transmitted. However, in the case of jamming, no transmission of rotation results. 
     Meanwhile, a discharger 18 removes charge on the paper 13 by means of corona discharge. Although not shown, light beams from the heating lamp HL remove charge carried on the light-sensitive member 13 and a brush 19 clears up the surface of the light-sensitive member 13 to get it ready for the formation of a next latent image. 
     It will be understood that the discharger 18 and the charger 12 produce corona discharge effective to discharging and charging for image transformation when the high voltage generation portion THVU is connected. Operation of the portion THVU is realized when a relay is turned ON and its contact THVR-a is closed in response to control signals from control circuits. 
     The original table 8 starts advancing as soon as the rotary drum 1 reaches a specific rotation position, and returns to its home position when its degree of advancement is in excess. A microswitch MS 4  is positioned against an actuator 8a moving in union with advancement of the original table 8, to thereby detect the home position of the original table 8. The microswitch MS 5  facing against the above-discussed microswitch MS 4  serves to detect excess advancement of the original table 8. 
     Pursuant to the concept of the present invention, a one-chip micro-processor governs revolution of the rotary drum 1, advancement and return of the original table 8, transportation of the paper, actuation of the chargers 6, 12 and the discharger 18, etc. Normal events in the sequence of a copying operation are carried out as discussed below. 
     First, a main motor MM starts rotating when a power switch MSW is thrown. Contacts PR-a and PR-b (see FIG. 2) of a power relay are closed such that the heating lamp HL 2  and HL 3  are turned on to increase the temperature of the fixing station 16. When the fixing station 16 is heated over a predetermined temperature, the ready state for a copying operation is visually displayed. Upon depression of a print switch PSW the rotary drum 1 rotates such that the respective components operate depending upon the states of the microswitches or sensing switches. That is, when the rotary drum 1 reaches a specific position, the lamp CL in the illumination station 9 is turned on so that the surface of the master paper 3 is charged by the respective chargers and simultaneously the original table 8 starts to move. If the microswitch MS 1  senses the introduction of the paper, then the paper stopper 14 will be opened in synchronization with rotation of the drum 1. The paper 13 is conveyed via the roller 21. At the light exposure station 7 an electrostatic latent image is formed on the master paper 3. The latent image is changed into a toner image via the development station 11. The paper 13 is conveyed so as to come into contact with the master paper 3. Then, the toner image is transferred onto the paper 13 after passing over the charger 12. The paper is detached from the light-sensitive member 3 on the drum 1. Within the pick-off means 15 the paper is attracted onto the conveying belt 15a through air absorption force, the residual charge thereon being cleaned up through the discharger 18. After traveling within the fixing station 16, the copy paper 13 is led to the outlet 5 via the feeding roller 22. 
     Discharge is carried out on the surface of the light-sensitive member 3 by light beams emitted from the heating lamp HL in the fixing station 16. The brush 19 cleans up the copy paper. Thus, the machine is ready for the formation of a next latent image. If the original table 8 has overrun the predetermined distance, the microswitch MS 5  becomes operative such that the table 8 restores to its home position. This return is sensed by a microswitch MS 4 . Therefore, the copy paper is stopped and the rotary drum 1 also is stopped at its initial position. 
     In the making of multiple copies, the procedure is repeated. For example, a multicopy dial is provided such that copy operation is inhibited when one dial shows zero. This may be detected by a microswitch MS 6 . 
     FIG. 3 shows a block diagram of the copying machine employing the micro-processor of the present invention. In FIG. 3, 30 designates a one-chip, one-package micro-processor (hereinafter referred to as a &#34;control element&#34;). Control signals derived from the control element 30 supply current to solenoids, relays via a driver circuit 32. For example, when a drum feed clutch DFC is on, the rotary drum 1 begins to rotate. In order to control the solenoids, the relays, etc., synchronizing signals 33 associated with rotation of the drum 1 are inputted to the control element 30. These signals 33 permit strobe signals 35 to be derived from the control element 30, the strobe signals being useful to confirm the operating states of the microswitches 34. 
     The control element 30 outputs the control signals 31 to control the copying machine in accordance with the confirmed states of the microswitches and the synchronizing signals. 
     The synchronizing signals 33 to be applied to the control element 30 are provided by a signal generation portion 37 responsive to rotation of the rotary drum 1. That is, the generation portion 37 comprises a series of slits Pa and a series of slits Pb formed on a disc 24 as shown in FIG. 4 coaxial with the shaft 2 of the rotary drum 1 and a photo-coupler secured with intervention of these slits. Accordingly, a signal 33 synchronous with rotation of the drum 1 is outputted via the signal generation portion 37. The position as shown by the arrow in FIG. 4 is the initial one of the rotary drum 1. Under these circumstances the synchronizing signals are obtained via the slits Pa-0, Pb-1. 
     A WTL level control circuit 39 is adapted to adjust the temperature of the fixing station 16 at a desired one by controlling the two heating lamps HL 2  and HL 3 . The outputs of the WTL level control circuit 39 are applied to the control element 30. When the outputs from the circuit 39 assume the logic value &#34;1&#34;, this indicates that the temperature of the fixing station 16 reaches the desired temperature. The logic value &#34;0&#34; shows that the same is below the desired one. 
     A circuit 40 senses slip roller jamming. In the event that there are abnormal events in operation of the roller 23, the control element 30 is informed of such abnormality. In summary, the logic value &#34;1&#34; shows the jam state while the logic value &#34;0&#34; shows the normal state. 
     When the power switch MSW of FIG. 2 is closed, the main motor MM rotates and the control element 30 is placed in its original state upon receipt of the signals from the signal source 38. The drum 1 and the original table 8 rotate, shift and stop once. Now, when the signals from the WTL circuit is &#34;1&#34;, depression of the print switch PSW permits the control element 30 to provide its control signal 31. The resulting signal renders the drum feed clutch DFC operative via the driver circuit 32 to rotate the rotary drum 1. In response to such rotation of the drum 1 the synchronizing signals 33 are impressed on the control element 30. The outcome is that the control element 30 delivers the strobe signals 35 for confirmation of the operating states of the microswitches and the control signals 31 are provided for the driver circuit 32. The control signals 31 operate the solenoids, the relays, etc. to sequentially perform the charging and movement of the original table. 
     The control element 30 featured by the present invention will be explained in detail. The control element 30 includes a read-only memory (ROM), a read-write memory (RAM), an accumulator, an input/output means, a clock pulse generator and a power supply. FIG. 5 shows a block diagram of contruction of the control element 30. The ROM 41 contains instructions each implemented with 8-bit parallel signals I 1  -I 8 . All the instructions are partitioned into page P 0  through page P 13  each page having 64 words (or steps). The stored instructions are fetched in sequence. 
     More particularly, the ROM 41 has a 6-bit counter PL available for addressing a specific step in respective ones of the pages, the counter PL being adapted to increment step-by-step except when a jump instruction is fetched from the ROM. There is provided also a 4-bit counter Pu to address a specific page within pages P 0  through P 13 . This counter Pu is different from the counter PL in that its counts are varied only when a jump instruction is fetched. Address signals from the counter PL provide access to a specific step of the ROM 41 via the decoder 42. As a consequence of this, the ROM 41 delivers all instructions belonging to the same step on page P 0  through P 13  and leads them to a gate circuit 43. In response to signals received from the counter Pu via the decoder 45, the gate circuit 43 outputs the code signals I 1  -I 8  of the instructions on the specific page which in turn are transferred to an instruction matrix 44. The instruction 44 produced micro-orders, that is, inputs to respective logic circuits. 
     After execution of the instructions, the counter PL is one incremented but the counter Pu is not varied except for jump. In this manner, the respective instructions are sequentially fetched from the ROM 41. 
     The ROM 41 also includes stack registers SL and Su similar to the bit arrangement of the counters PL and Pu. If the jump instruction is read out from the ROM 41, the current count of the counter PL plus one are loaded into the stack register SL while the count of the counter PU is loaded into the stack register SU. The designation to be jumped is stored in the counters PL and PU. Afterward, when the instruction to be returned is fetched from the ROM 41, the counts of the stack registers SL and SU are transferred to the counters PL and PU. Consequently, the ROM 41 reverts to the next step immediately after the step calling for the jumping. 
     Format of the instructions contained within the ROM 41 is illustrated in FIG. 6. There are illustrated several types TR 1 , TR 0 , SSR, RTN and RTN 1  of instructions effective to address the ROM 41. Although sub-routine pages P 0 , P 1 , P 2  and P 3  are previously determined, it is of course possible to employ all of pages as main routine ones. The instruction SSR indicates that the code signals I 1  -I 4  of the instructions are to be transferred into one stack register SU. The SSR codes I 8  -I 1  are denoted as &#34;0111XXXX&#34; in FIG. 6. The micro-order  4  is resulted so that the micro-order  4  applied to AND gates 106a-109a render the same effective. I 1  -I 4  are inputted into the stack registers SU 1  -SU 4  via OR gates 106-109. 
     TR0 is an instruction indicating that the instruction codes I 1  -I 6  are to be jumped into the steps 0 through 63 on the same page. This is denoted as 10XXXXXX and provides a micro-order 2. Since the instruction code I 8  is &#34;1&#34; as shown in FIG. 8, AND gates 71a-76a operate so that the contents of the code signals I 1  -I 6  are loaded via OR gages 71-76 into counters PL 1  -PL 6  of which the contents are modified into the contents represented by the codes I 1  -I 6 . The step represented by the codes I 1  -I 6  are thus addressed. 
     If there is data stored within the stack register SU, its contents are transferred to the counter PU to enable jump to a specific page. SSR and TR o  are a combined instruction. When SSR is first fetched, the stack register SU is loaded with I 1  -I 4 . When TR o  is next fetched, the contents of the stack register SU are transferred to the counter PU. The counter PL indicates jump to a specific page upon receipt of the contents I 1  -I 6 . 
     During a main routine TR 1  instructs jump to a sub-routine if it is fetched. The jumped designation is page P 0 . In this case the codes I 8  -I 1  are denoted as &#34;11XXXXXX&#34; and no micro-order is resulted. Referring to FIG. 10, the contents of the counters PL 1  -PL 6  are one-step incremented via an adder 46 and then transferred into the stack registers SL 1  -SL 6 . Because of I 8  =I 7  =&#34;1&#34; on counters PL 1  -PL 6  are one-step incremented at the timing of a clock signal C 1 . The incremented contents being transferred into the stack registers SL 1  -SL 6 . In FIG. 7, since no micro-order is developed AND gates 106b-109b are effective so that the contents of the counters PU 1  -PU 4  are transferred to the stack registers SU 1  -SU 4 . Contrarily, the counter PU 1  -PU 4  receives no signals and assumes all &#34;zeros&#34;. This designates page P o  that is the subroutine page. In addition, since the code I 8  is &#34;1&#34; in FIG. 8, the contents of I 1  -I 6  are transferred to the counter PL 1  -PL 6 , thereby designating the step indicated by the contents I 1  -I 6  on page P o . 
     RTN is an instruction useful for executing return from the sub-routine to the main routine. In response to the above discussed instruction TR 1 , the next step following the jumped subroutine is approached. In other words, when RTN is fetched during the sub-routine, the counters PU and PL are actuated to designate the next step following the jumped step. In case where the instruction TR 1  calling for jump is fetched, the contents of the counter PU are shifted into the stack register SU and the contents of the counter PL are shifted into the stack register SL with one-step increment. It will be easily understood for this reason that the contents of the stack register SU and the stack register SL are respectively shifted into the counter PU and the counter PL. The codes for the RTN instruction are &#34;01011110&#34;. At this time, micro-orders 2 and 10 are derived. In FIG. 9, AND gates 89a, 90b, 91a and 92a are effective, thereby transferring the contents of the stack register SU 1  -SU 4  into the counter PU 1  -PU 4 . In this drawing, ACL represents the signals derived from the signal generation source 37 discussed with respect to FIG. 3. When these signals ACL are inputted, the counter PU 1  -PU 4  assumes &#34;1011&#34;, page 13 of the ROM 41 is assigned. 
     Alike the instruction RTN, RTN 1  is used for return to main routine from sub-routine, thereby skipping the instruction contained in the step following the step which has called for jump to subroutine in response to the instruction TR 1 . The second step following the step of the instruction TR 1  is executed. Since the outputs from a flip-flop J are supplied via an inverter to the gate circuit 43, the instruction on the next step is skipped. Therefore, when RTN 1  is fetched, the flip-flop J is set thereby skipping the next instruction following the step calling for jump into sub-routine by instruction TR 1 . 
     The following sets forth the RAM 50 within the control element 30. Similarly, the RAM 50 has a 4-bit counter BL for addressing words or steps. The counter BL is variable in accordance with instructions. However, if instructions have no properties of varying the contents of the counter BL, the counter BL remains unchanged. The RAM 50 is further provided with a 2-bit counter BU available for four blocks 0-3 of the RAM 50. The 2-bit counter BU also remains unchanged except for the instructions read out from the ROM 41 bearing the properties of changing the contents of the counter BU. 
     The outputs of the counter BL are inputted to a decoder 51 of which the output permits the addressing of a specific word in the blocks 0-3 belonging to the same step of the RAM 50. Therefore, the addressed word is provided with access via the gate 53. The output of the counter BU is supplied to a decoder 54 of which the output renders a portion of the gate circuit 53 in the selected block operative. Thus, the outputs of the counters BL and BU provide access to a specific step in the signle block of the RAM 50. 
     The 4-bit input/output signals are in parallel supplied from and to the gate circuit 53. The input signals M 1  I-M 4  I are stored in a specific step addressed by the counter BL within a specific block designated by the counter BU. The output signals M 10  -M 40  are ones stored on a specific step within a specific block . 
     As shown in a time chart of FIG. 11, the clock generator 60 produces clock signals C 1 , C 2  and C 3 . The clock signal C 1  makes it possible to enter the above described input signals M 1  I-M 4  I into the RAM 50. They are stored in the RAM 50. The clock signals C 3  permit the contents of the RAM 50 to be outputted as the output signals M 10  -M 40  via the gate circuit 53. The fetching of the instructions from the ROM 41 is carried out in synchronous with the clock signals C 1 . It takes approximately 10 μsec to fetch the next succeeding instructions. 
     The decoder 51 serves to address the RAM 50 and provide the decoder outputs outside the control element. These outputs are derived from terminals S 1 , S 2 , S 3 , . . . S 7 , when the counter BL is &#34;15&#34;, &#34;14&#34;, &#34;13&#34;, . . . &#34;19&#34;, respectively. The signals from the terminals S 1  -S 7  are used as key strobing signals as well known in the art of calculators. 
     By way of example, the instructions fetched from the ROM 41 will be executed in the following manner. 
     When fetching the instruction LB from the ROM 41, its instruction codes I 1  -I 5  are shifted into the address counters BU and BL to designate a specific position of the RAM 50. The counter BL may be set into any one of &#34;0000&#34;, &#34;1100&#34;, &#34;1101&#34;, &#34;1110&#34; or &#34;1111&#34;. The counter BU may designate any blocks 0-3. These circumstances are viewed from FIG. 12. When LB is fetched as shown in FIG. 6, the micro-order  14  is developed so that the micro-order 14 and the instruction code I 3  are applied to the counter BL, via an AND gate. The counter BL 2  receives the AND gated output of  14  ad I 4 . The counter BL 3  receives the OR gated output of I 3 , I 4  and I 5  and the AND gated output thereof including 14 as another input. Therefore, when it is desired to modify the contents of the counter BL into &#34;0000&#34; as viewed from FIG. 12, all that is necessary for I.sub. 5, I 4  and I 3  is to assume &#34;000&#34;. Similarly, I 5 , I 4  and I 3  should be &#34;100&#34;, &#34;001&#34;, &#34;010&#34; and &#34;011&#34; when the contents of the counter BL are to be &#34;1100&#34;, &#34;1101&#34;, &#34;1110&#34; and &#34;1111&#34;, respectively. 
     The instruction codes I 2  and I designate a specific block of the RAM. The AND gated output of the instruction code I 1  and the micro-order 14  is applied to the counter BU1 and the AND gated signals I 2  and 14 are applied to the counter BU2. When it is desired to designate the block &#34;0&#34; the contents of the counter BU should be &#34;00&#34; and thus the codes I 2  and I 1  should be &#34;00&#34;. Similarly, when I 2  and I 1  are &#34;01&#34; and the counter BU are &#34;01&#34;, the first block of the RAM is assigned. When the codes I 2  and I 1   and thus the counter BU are &#34;10&#34;, the second block is assigned. When the counter BU is &#34;11&#34;, the third block is designated. 
     If the instruction LB is fetched from the ROM 41, the codes assume &#34;01000100&#34; so that I 5 , I 4  and I 3  are &#34;001&#34; and I 2  and I 1  are &#34;00&#34;. Therefore, the counter BL is &#34;1101&#34; while the counter BL is &#34;00&#34;. It will be obvious from FIG. 12 that the instruction LB designates (4) of the 13th stop of the block 0 of the RAM. The respective one of the steps consists of 4 bits each corresponding to the respective input and output signals M 1  I--M 4  I, M 10  -M 40 . One bit consists of a flip-flop. 
     When the instruction SM (&#34;000011XX&#34;) is outputted, is forced into set position one bit designated by the instruction codes I 2  and I 1  within four bits of the RAM 50 addressed by LB. In other words, when the codes I 2  and I 1  are &#34;00&#34;, &#34;01&#34;, &#34;10&#34; and &#34;11&#34;, the 0th, 1st, 2nd and 3rd bits are set, respectively. For example, when the 3rd bit is to be set, I 2  and I 1  should be &#34;11&#34;. In this case, the input signal M 4  I should be &#34;1&#34;. The remaining bits remain unchanged. In addition, when RSM is outputted, is forced into reset position one bit designated by the instruction codes I 2  and I 1  within the four bits which have been addressed. At this time, the instruction codes I 8  -I 1  are &#34;000001XX&#34; the instruction I 4  of SM is &#34;1&#34;  and I 4  of RSM is &#34;0&#34;. The code I 4  is applied to one input terminal of an AND gate of which the remaining input terminals receive I 2  and I 1 . The input signals M 1  I-M 4  I designated by I 2  and I 1  are inputted as &#34;0&#34; into the gate circuit 53 to reset the designated bit. The micro-order derived in response to RSM and SM is  36  that is used as control signals for gates. 
     The accumulator is illustrated in FIG. 5. This serves as a repeating station for data transmission and includes 4-bit accumulators A 1  -A 4 . Only when instructions are fetched to execute transmission, the clock signals C 1  are inputted to the accumulator scheme. These instructions force the accumulators A 1  -A 4  into set or reset position. The accumulator stages A 1  -A 4  are connected to 4-bit binary adder FA 1  -FA 4 . A carry flip-flop C is effective when addition or transmission. All arithmetic controls are performed via the accumulator stages A 1  -A 4 . 
     When the instruction KTA is shown in FIG. 6 is fetched, the contents of the counter K 1  -K 4  are transferred to the accumulator stages. Under the circumstances, two micro-orders  25  and  27  are derived from the instruction matrix 44. As shown in FIG. 14, OR gates 61-64 serving as set inputs to the accumulators A 1  -A 4  permit the count of the counters K 1  -K 4  to be outputted since the development of the micro-order 25 renders AND gates 61a-64a operative. The respective stages of the accumulator A 1  -A 4  receive the count of the counter K 1  -K 4  and, in response to the micro-order  27 , the count of the counter K 1  -K 4  is transferred into the accumulator A 1  -A 4  through the use of the clock signal C 1 . When the instruction TAM is fetched, the second instruction rather than the first instruction is executed as far as there is determined equivalency between the accumulator A 1  -A 4  and the output signals M 10  -M 40  from the addressed RAM 50. In other words, equivalency sensed enables skipping. At this moment, micro-orders  32 ,  24  and  33  are developed. The development of the micro-orders  24  and  33  renders AND gates 81, 82b, 83, 84b, 85, 86b, 87 and 88b effective such that the input terminals a 4  -a 1  of the adder FA 4  -FA 1  receive the contents of the accumulator A 4  -A 1  via the enabled AND gates 81, 83, 85 and 87. On the contrary, the input terminals b 4  -b 1  receive the outputs M 40  -M 10  of the RAM 50 via the enabled OR gates 82, 84, 86 and 88. A coincidence circuit compares whether the contents of the accumulator A 4  -A 1  applied to the adder FA 4  -FA 1  are equal to the outputs M 40  -M 10  of the RAM 50. The respective outputs from the coincidence circuit are AND gated and sent to the skipping flip-flop J. 
     If the contents of the accumulator A 4  -A 1  are in agreement with the outputs M 40  -M 10  of the RAM, the coincidence circuit provides the logic output &#34;1&#34; which in turn is supplied to the flip-flop J via an AND gate. For this reason, the flip-flop J is set to thereby skip the next instruction. 
     Conversely, if affirmative answer is not given, the flip-flop J is not forced into the set state, thereby fetching and executing the next instruction. 
     The input/output means is under control of the instructions fetched from the ROM 41. The input means includes input ports TAB, AK, KN 2  receiving the strobe signals from the control element 30 as viewed from FIG. 3 and synchronizing signal receiving ports α and β for the purpose of synchronization. The input ports α and β accept the signals from the slits Pa and Pb of the disc 24. The former receives the signals from the slits Pa, while the latter receives the same from the slits Pb. In the following description the synchronizing signals are denoted as P A  and P B . There are also included in input port KN 1  responsive to signals from the WTL circuit 39 and an input port KF responsive to signals from the slip roller jam detection. As noted earlier, the power supply input ACL reset a family of flip-flops to set up page 13 of the ROM 41. 
     Meanwhile, the output means has a 4-bit register F 1  -F 4  and a 15-bit register W 1  -W 15  of which the outputs are derived in parallel. The registers W 1  -W 15  are outputted when a flip-flop N P  is set. 
     In accordance with the present invention, the signals derived in parallel from the registers F 1  -F 4  and W 1  -W 15  provide a control for the copying machine. The clock signals C 1  -C 3  operable within the control element 30 are derived from a clock generator 60 which operates in response to application of signals from a clock generating means 59 to a clock signal input port 4. The outcome is that the clock signals C 1 , C 2  and C 3  are generated in a time relationship as shown in FIG. 11. 
     As discussed above, the instruction are contained within the ROM 41 of the control element 30. FIGS. 15 through 28 illustrate the contents of the instructions written on each page P 0  to P 13  of the ROM 41. If additional functions are needed, all that is necessary is to modify the contents of the instructions contained within the ROM 41. 
     Flow charts associated with the instructions shown in FIGS. 15 through 28 are depicted in FIGS. 29 through 34. 
     Now, the power switch is turned ON. The main switch MSW of FIG. 2 is closed so that the main motor MM rotates and the input port ACL receives signals to place the control element 30 into the initial state. As a result, the addressing counter PU assumes &#34;1&#34;, &#34;0&#34;, &#34;1&#34; and &#34;1&#34; at the respective stages thereof, PU1, PU2, PU3 and PU4, thereby designating page 13. The counter PL is all zero&#39;s. 
     The register F 1  -F 4  in the control element 30 is cleaned to thereby place the contents of the RAM 50 into all zero&#39;s state. Since the counter PU shows &#34;1101&#34; and the counter PL shows &#34;all zero&#39;s&#34; upon power throw, the instruction LAX on page P 13  (See FIG. 15) of the ROM 41 is fetched. LAX permits the instruction codes I 4  -I 1  to be inputted into the accumulator. At this moment, I 4  -I 1  are &#34;0000&#34;. After the execution of this instruction, the counter PL is one-step incremented and thus ready for the fetching of the next succeeding instruction ATF from the ROM 41. ATF is an instruction that transmits data in the accumulator A 1  -A 4  into the register F 1  -F 4 . The register F 1  -F 4  is cleaned up. This means no development of any control signals. Thereafter, the instruction IDFS is fetched. IDFS sets a flip-flop IDF within the control element 30. A set input is applied to the input terminal of the flip-flop IDF because of a micro-order  a , thereby setting that flip-flop. As discussed below, the output IDF of the flip-flop IDF is used as a control signal for a sam lamp JL. Subsequently, NPR is fetched to reset a flop-flop NP. The fetching of the next succeeding instruction RSC resets a flip-flop C of which the output is applied to the gate 52 as the strobe signals. Under the conditions that the flip-flop C is in the set position, the strobe signals are all derived from the terminals S 1  -S 7 . But when the same is in the reset position, the strobe signal is derived from any one of the terminals S 1  -S 7  depending upon the count of the counter BL. 
     After the completion of the last named instruction LB is fetched. At this time the codes I 5  -I 1  are &#34;00000&#34; and thus the counters BU and BL designate the 0th block and the 0th step. As viewed from FIG. 12, the designation address (0) of the RAM 50 is assigned. 
     The fetching of TR 1  enables sub-routine jump. This instruction permits the contents of the counter PU to be shifted into the stack register SU and the count of the counter PL to be one-step incremented and shifted into the stack register SL. When this occurs, the contents of the counter BU are &#34;00&#34; and the contents of the counter BL are &#34;0000&#34;. After fetching the instruction TR 1  the jump into page P 0  of the sub-routine (See FIG. 28) is attained to fetch the 6th step instruction TR 1 . TR 1  jumps into subroutine page P 1  so that the AND gate 89b of FIG. 9 is enabled to introduce &#34;1&#34; into the counter stage PU 1  via the OR gate 89 while the remaining counter stages PU 2  -PU 4  are &#34;0&#34;. Consequently, the counter PU designates page P 1 . The contents of the counter PL are &#34;110110&#34;. To this end is fetched the instruction LAX located at the 54th step of page P 1 . 
     As discussed previously, since the codes I 4  -I 1  for the instruction LAX are &#34;0000&#34;, the contents of the accumulator A are also &#34;0000&#34;. After the execution of this instruction, EXCI is fetched to exchange the contents of the accumulator A for the contents of the addressed RAM 50. Simultaneously, the instruction codes I 1  and I 2  and the contents of the address counter stages BU 1  and BU 2  in the RAM are impressed on the address counter BU after passing past a non-coincidence circuit. The address counter BL is incremented and, if BL is &#34;1111&#34;, the next step instruction is skipped. 
     When fetching EXCI the RAM 50 assumes &#34;0000&#34; at its 0th block and 0th step. At this time the counter BU is &#34;00&#34; because of the codes I 1  and I 2  being &#34;0&#34;, while the counter BL is &#34;0001&#34; thereby designating the 1st step, 0th block. Because the counter BL is &#34;0001&#34;, TR0 is fetched. This instruction is to achieve the jump within the same page. The codes I 1  -I 6  are inputted into the counter PL which assumes &#34;110110&#34;. The procedure jumps into the 54th step on page P 1  to enable the fetching of the instruction LAX. 
     In summary, the above sequence is repeated such that the contents of the respective steps in the 0th block of the RAM 50 are placed into all &#34;zero&#39;s&#34; state and, when BL assume &#34;1111&#34;, the instruction RTN is outputted. RTN is executed to shift the contents of the stack registers SU, SL into the counters PU and PL. As a result, the main routine is reverted from the sub-routine. To this end, the counter PU is &#34;1011&#34; and the counter PL is &#34;000111&#34; so as to fetch LB. This leads to the facts that the address counter BU of the RAM 50 is &#34;01&#34; and the counter BL is &#34;0000&#34;, thereby designating the 0th step, the 1st block of the RAM 50 (See FIG. 12). The instruction TR 1  is fetched so that the respective steps of the first step are all &#34;0&#39;s&#34;. The same circumstances are applicable to the second and third blocks. The above discussed procedure places the control element 30 into its initial state. 
     Reverting the flow chart of FIG. 29, a test judge is achieved after operation of 0→RAM. The test judge is achieved to find out whether the events in the sequence of machine operation are succeeded satisfactorily. In the following description it is assumed that no affirmative answers are given for all the events. 
     After completing the test judge, determination is performed as to a contact JR-a of a jam relay JR. If there is caused a copy paper jam, the contact JR-a is closed thereby informing the operator of such jam. 
     In the following description assumption is placed for the purpose of explanation that in this case the judge answers NO to thereby judge the microswitch MS 1 . One terminal of the microswitch MS 1 , the remaining microswitches MS 2  -MS 8 , the jam relay contact JR-a, the master paper exchanger contact CSSR-a and the print switch PSW as illustrated in FIG. 37, are connected with the strobe output terminals S 1  -S 7  of the control element 30, while their other terminals are connected in common with the input terminals TAB, AK and KN 2  of the control element 30. This is one of the important features of the present invention. It will be obvious from FIG. 37 that the number of necessary wires communicating between the microswitches and the control element 30 is considerably reduced. In other words, determination is carried out in a serial fashion as to the instantaneous conditions of the respective microswitches. 
     When it is desired to sense the conditions of the microswitch MS 1 , TR 1  on the 37th step is fetched from the ROM 41. Consequently, the jumped 12nd step on the sub-routine page P 0  becomes operative. LB is fetched to designate the 14th step of the first block of the RAM 50 for the purpose of achieving jump into the sub-routine page P 1  responsive to the next instruction TR 1 . Thus, SSR is fetched. 
     The counter BL which addresses steps in response to the instruction LB, assumes &#34;1110&#34; so that the strobe signal is derived from the terminal S 2  via decoder 51. As shown in FIG. 37, the strobe signal S 2  is impressed on the microswitch MS 1  having the contact NC connected with the input port TAB of the control element 30 and the contact NO connected with KN 2 . When the microswitch MS 1  is turned toward NC, TAB receives the strobe signal S 2 . The microswitch MS 1  provided for the purpose of sensing arrival of the copy paper is now in the contact site NC because of absence of the copy paper. 
     When the instruction SSR is fetched, it sets up a complex instruction together with the next succeeding instruction TR0 to enable again jump to the sub-routine page P 2 . The designation is changed into the 0th step of page P 2  in accordance with the codes I 8  -I 1 . The instruction LAX is fetched. This leads that the accumulator A assumes &#34;0000&#34; and extracts the next instruction EXC. EXC is executed to exchange the contents of the accumulator A 1  -A 4  for the contents of the RAM 50 (the 14th step of the 1st block). The codes I 1 , I 2  and the address counters BU 1  and BU 2  are inputted into the counter BU after passing past a non-coincidence circuit. Modification is performed as to the designation associated with the addressed RAM block. Since I 2  =I 1  =&#34;1&#34; for the RAM block, the counter BU is &#34;10&#34; to designate the 2nd block. At this time, the address (10) of the RAM 50 shown in FIG. 12 is selected. After executing the above discussed instruction, LAX is fetched so that the accumulator A is &#34;0000&#34;. The next succeeding instruction EXC modifies the contents of the 14th step of the 2nd block of the RAM 50 into &#34;0000&#34; and the address counter BU ito &#34;01&#34; designating the 1st block. 
     When the instruction LAX of the 4th step of the page P 2  (See FIG. 26), the accumulator A receives &#34;0011&#34; or &#34;3 (decimal)&#34;, the instruction TTAB is outputted. TTAB skips the next instruction if the input port TAB is &#34;1&#34;. Therefore, the input port TAB receives the strobe signal S 2  to confirm the operating state of the microswitch MS 1  since the microswitch MS 1  is inclined to NC. Because of the input terminal TAB being &#34;1&#34;, the next instruction TR0 is skipped. ADD 11 of the 7th step of the page P 2  is executed. ADD performs binary addition of data of the accumulator and data of the addressed RAM, the results of the addition being loaded into the accumulator A. In addition, ADD 1  skips the next step instruction if a carry in the results from the adder FA is &#34;0&#34;. 
     The input terminal a of the adder FA receives the contents of the accumulator A 1  -A 4  with the other terminal b thereof receiving the output data M 10  -M 40  of the RAM 50, thereby executing addition. The flip-flop C is reset. Since the output data M 10  -M 40  is &#34;0000&#34;, the outputs from the adder FA are &#34;0011&#34; and the carry output is &#34;0&#34;. The outputs &#34;0011&#34; are transferred into the accumulator A. 
     EXC of the 9th step is executed. The contents of the accumulator A are stored in the address (9) of the 14th step, the 1st block of the RAM 50. Since the codes I 2  and I 1  are &#34;00&#34;, the contents of the counter BU remain &#34;10&#34;. Then, the instruction TR0 of the 10th step is executed. LAX is executed after reverting to the 4th step of the same page. The accumulator A is &#34;0011&#34; so that the next instruction TTAB is executed to confirm again the microswitch MS 1 . ADD 11 on the 7th step is derived. Addition is carried out between &#34;0011&#34; stored on the address (9) of the RAM 50 and &#34;0011&#34; of the accumulator A, the results thereof (&#34;0110&#34;) being loaded into the accumulator A. The instruction EXC of the 9th step permits the contents of the accumulator A to be loaded into the address (9) of the RAM 50. 
     At the moment where the instruction ADD11 on the 7th step is fetched, a carry &#34;1&#34; is developed under the condition the contents of the adder FA 1  --FA 4  are over 15. The next instruction TR0 is fetched. When jumping into the 32nd step, RSC is fetched to reset the flip-flop C. If RTN is fetched to return to the main routine, the instruction on the 38th step of the page P 13  is fetched. 
     In this manner, addition is carried out many times until the adder FA outputs a carry &#34;1&#34;, for the purpose of confirming the strobe signal &#34;1&#34; applied to the input terminal TAB. In other words, this makes sure confirmation as to the operating state of the microswitch MS 1 . In the given embodiment, the operating state of the microswitch MS 1  is sensed six times. The same confirmation procedure is performed as to the remaining microswitches MS 2  -MS 8 . 
     In the foregoing description, the microswitch MS 1  is judged as &#34;NO&#34; and judgement is shifted into the second microswitch MS 2 . In the event that the microswitches MS 1  and MS 2  are judged as &#34;YES&#34;, the jam state JAM is determined. The microswitch MS 2  is to detect removal of the copy paper 13. But, it does not see such removal at this moment and thus inclines to NC. The strobe signal S 3  is outputted and transmitted into the input port TAB. To this end confirmation is repeated as to the operating state of the microswitch MS 2 . Accordingly, the microswitch MS 2  is judged as &#34;NO&#34;. Subsequently, the microswitch MS 8  is subjected to such judgement. The microswitch MS 8  is adapted to sense the tray 17 in the fixing station and more particularly the same raised when power switch is thrown. The judgment procedure continues working as far as an answer &#34;NO&#34; is given. If &#34;YES&#34; is given, CSSR is judged, CSSR being a contact placed into NO site as shown in FIG. 37 when the associated relay CSSR is ON in exchanging the master paper 3. In this case the relay CSSR is not inclined to NO site and thus judged as &#34;NO&#34;. When CSSR is ON, the control element 30 outputs control signals effective to turn ON a power relay PR. However, these signals are not developed at this time. For, as shown in FIG. 15, TRI is fetched from the 52nd step of the page P13 to attain subroutine jump. When LB is derived from the 53rd step of the page P 0 , the 13rd step, the 0th block of the RAM 50 is designated, namely, (4) in FIG. 12. When fetching SM, the 2nd bit of 4 bits in the designation (4) is set. The operating states of respective loads are stored on the steps 12 to 15 of the 0th block of the RAM 50 as shown in FIG. 35. Therefore, the power relay PR in its ON state permits &#34;1&#34; to be stored on the 2nd bit of the designation (4) of the RAM 50. 
     When RTN is fetched at the sub-routine page P 0  the main-routine is coming back. The test judge is again performed and, when NO is given, judgement is shifted into WTL. When the fixing station 16 is heated up to a sufficiently high temperature, WTL permits the signal &#34;1&#34; from the WTL level control circuit 39 to be supplied to the input port KN 1  of the control element 30. If WTL judgement gives answer &#34;YES&#34;, the ready lamp is turned OFF and the drum feed clutch DFC is turned ON, conversely. If &#34;NO&#34; is answered, the heating lamp relay HLR is turned ON. In case where WTL is judged as &#34;NO&#34;, the 0th bit of the address (8), the 0th and 1st bits of the address (12) contain &#34;1&#34;, &#34;1&#34;, and &#34;0&#34;, respectively. Referring to FIG. 15, when WTL is judged as &#34;NO&#34;, the main-routine is returned so that LB of the 59th step of the page P 13  is fetched from the ROM 41 to designate the address (12) of the RAM 50 as shown in FIG. 12. SM permits the 0th bit of the address (12) to contain &#34;1&#34;. Subsequent to this, in response to the complex instruction SSR/TR0 P12 is jumped to fetch the 0th step instruction TR 1  to enable sub-routine jump. The thus jumped instruction LB indicates the address (12) of the RAM 50 and RSM resets the 1st bit of the address (12) which in turn stores &#34;0&#34;. The next instruction LB designates the address (8). The 0th bit of the address (8) is &#34;1&#34; in response to SM and the drum feed clutch DFC is placed into the ON state. After that, TR 1  is fetched so that the contents (see FIG. 35) of the addresses (16), (4), (8) and (12) of the 0th block of the RAM 50 are loaded into the register W 1  -W 5 . This implies that TR 1  permits jump into P 1  and SSR/TR0 permit jump into P 2 . At this time NPR is fetched to reset the flip flop NP. The contents of the register W are not developed to prohibit the development as the control signals. After the control signals from the register W shift the contents of the RAM 50 into the register W, the flip flop NP is set so that the above discussed signals are derived in parallel. If the flip flop NP is reset, the control signals are not outputted for an extremely short period of time. 
     To shift the contents of the RAM 50 into the register W, NPR and then LB are sequentially fetched to designate the address (16) of the 0th block of the RAM 50. In reply to TM the 1st bit of the designation (16) stores whether CSSR is set. Since CSSR is now in &#34;0&#34; state, TR0 is fetched to allow jump within the same page and to fetch WIR. WIR inputs &#34;0&#34; into W of the register W to effect one-position right shift. On the contrary, W 1  S inputs &#34;1&#34; into the register W 1  to effect one-position right shift. When WIR is fetched in this manner, &#34;0&#34; is supplied to the register stage W 1  to effect right shift. Afterward, TM is outputted to extract the 2nd bit of the designation (16) of the RAM 50 and, if this is &#34;1&#34;, the next instruction is skipped. The 2nd bit of the designation (16) stores CSSR in the reset state. Of course, the output is &#34;0&#34; which is supplied to the register W 1  to effect right shift. 
     In the above mentioned manner, the contents of the RAM 50 are shifted into the register W 1  -W 15 . For example, when 2NCB is fetched, the counter BL is incremented to bear &#34;1101&#34;. That is, the designation (4) of the RAM 50 is assigned. This follows that the contents of the designation (4) are transferred into the register W 1  -W 15 . The 2nd bit of the designation (4) stores the power relay PR and hence provides &#34;1&#34; for the register W. When the contents of the RAM are completely transmitted into the register W 1  -W 15 , NPS is fetched to place the flip flop NP into the set state and derive the contents of the register W 1  -W 15  as control signals. In this instance the drum feed clutch DFC, the power relay PR and the heating lamp relay HLR are all in the ON state so that the drum 1 rotates and the lamps HL 2 , HL 3  and HL 1  are turned on to increase the temperature at the fixing station. RTN enables main-routine jump. Revolution of the drum sets up the initial state of the copying machine. Therefore, if the machine is in the initial state and WTL is &#34;YES&#34;, the print ready condition is informed. Upon depression of the print switch PSW the copy cycle starts working as shown by a flow chart of FIG. 29. A flip flop D is reset, which is located within the RAM 50 as shown in FIG. 36. Briefly speaking, all the flip flops as shown in FIG. 36 are in the reset state. After resetting the D flip flop, the wait time level WTL is judged. If the desired temperature is exceeded, &#34;YES&#34; is given to turn off the heating lamp relay HLR to determine the microswitch MS 4 . If not, the three heating lamps HL 1  -HL 3  continue operating to increase the temperature. 
     The function of the microswitch MS 4  is to sense the initial stop position of the original table 8 of FIG. 1 and thus gives &#34;YES&#34; when the original table is in its initial position. An original table return solenoid TRS is turned OFF to judge the microswitch MS 7 . The function of TRS is to restore the original table 8 to its home position, but the function of TFC is to advance the same in the forward direction. 
     The microswitch MS 7  detects arrival of a new master paper 3 for exchange of the master paper. In FIG. 37, this inclines to NC and, if &#34;NO&#34; is judged, a master paper stopper solenoid MSS is turned OFF. After that, the slip roller jam SRJ is judged. As discussed with respect to FIG. 1, SRJ detects the roller 23 and provides its results for the input port KF of the control element 30 via the slip roller jam detector 40. Therefore, in this case &#34;NO&#34; is judged and judgement is effected on the synchronizing signals PB. To attain the judgment as to the synchronizing signals PB, TR 1  on P 12  is fetched to effect P 0  sub-routine jump and P 1  jump. LAX is fetched from the 0th step, P 1  to change the accumulator A into &#34;0000&#34;. Then, TB is developed. When the synchronizing signal input port β is &#34;1&#34;, the next instruction is skipped by TB. Similarly, TA skips the next instruction when the synchronizing signal input port α is &#34;1&#34; . The synchronizing signal PA applied to the input port α sets a flip flop αF and Ta resets the same. As far as TB is fetched and the synchronizing signals PB are applied to the input β of the control element 30, ADX is fetched. If not, RTN is fetched for return to the main-routine. The fetching of RTN shows that the drum 1 is not in its initial position. WTL is again judged. When the synchronizing signals PB are then applied, PB judge answers &#34;YES&#34;. During the PB judge ADX is fetched so that the adder FA effects addition of &#34;0000&#34; of the accumulator A and &#34;0101&#34; of the codes I 4  -I 1 . The results being placed into the accumulator A. The adder FA does not develop a carry and the next RTN 1  is skipped and TB is again fetched. ADX is again executed to effect addition of &#34;0101&#34; of the accumulator A and &#34;0101&#34; of I 4  -I 1 . The resulting &#34;1010&#34; is placed into the accumulator A. The above operation is repeated. If the adder FA outputs a carry &#34;1&#34;, RTN 1  is fetched for return to the main-routine such that LB is fetched from the 12th step of P 12 . If TA is developed and the flip flop αF is &#34;1&#34;, that is, if the synchronizing signals PA is inputted, TR 1  is executed to effect jump into the sub-routine P 0  and to judge WTL. 
     In a flow chart of FIG. 29, PA is judged when &#34;YES&#34; is answered. When PB is &#34;YES&#34; and the synchronizing signals PB-1 are applied to the control element 30. Twice detection of PA (Pa-11 and Pa-0 as shown in FIG. 4) represents that the drum 1 is exactly in the original state. The revolution of the drum is stopped. In other words, PB is &#34;YES&#34; and the synchronizing signal PA-11 is supplied to the control element. PA is judged as &#34;YES&#34; and judgement is shifted into the flip flop D. In the event that PA is &#34;NO&#34;, the wait time level WTL is again judged. In case where PA is &#34;YES&#34;, the D flip flop is judged. Since the D flip flop is not in the set state (&#34;1&#34;), &#34;NO&#34; is answered. In this instance the 3rd bit of the designation (0) of the RAM 50 as shown in FIG. 36 sotres &#34;1&#34; to force the D flip flop into the set state. After executing confirmation as to WTL, the input state of PA-0 is confirmed. When the synchronizing signal PA-0 is inputted to the α terminal of the control element 30, PS is judged as &#34;YES&#34;. Thereafter, the 3rd bit of the designation of the RAM receives and stores &#34;0&#34;. The A flip flop is judged so that &#34;NO&#34; is given because the A flip flop is in the reset state. The circumstance may be applicable to a β flip flop. For CSSR &#34;NO&#34; is judged. 
     The above operations turn off the high voltage relay THVR and the drum feed clutch DFC. As shown in FIG. 1, the relay THVR in the ON condition operates the chargers 12 and 18. The relay THVR is in the OFF state after throw of the power switch MSW, whereas the feed clutch DFC is in the ON state to prohibit rotation of the drum 1. Namely, the drum 1 is stopped because of the relationship between the synchronizing signals PA and PB applied to the terminals α and β of the control element 30. 
     As stated above, the copying machine is placed into its initial state. Thereafter, the instructions are sequentially fetched from the ROM 41 to provide a control for the machine. 
     Referring to a flow chart of FIG. 30, the microswitch MS 4  is judged whereby the strobe signal S 1  is outputted and then applied to the input port KN 2 . Thus, the microswitch MS 4  is judged &#34;YES&#34;. For this reason the original table return solenoid TRS is rendered OFF (previously OFF) to judge the slip roller jam SRJ and the microswitch MS 2 . Anyway these judges are concluded as &#34;NO&#34;. However, a jam is evaluated because the microswitch MS 2  is in such state. 
     While PB is judged, the synchronizing signal PB is of course impressed on the input port β of the control element 30 because the rotary drum 1 is in its initial state. The conclusion is that &#34;YES&#34; is answered. If &#34;NO&#34; is answered during PB judge, the drum feed clutch DFC 13 placed into the ON state to seek again the initial state of the rotary drum 1. 
     After that, WTL is judged wherein &#34;YES&#34; is given when the temperature of the fixing station 16 is above a predetermined one. If &#34;YES&#34; is not given, the lamp relay HLR is turned ON and the ready lamp RL is turned OFF to repeat the above procedure. In case where the temperature of the fixing station 16 is above the predetermined one, the signal &#34;1&#34; from the wait time level detector circuit 39 is applied to the input port KN so that WTL is judged as &#34;YES&#34; to turn OFF the heating lamp relay HLR. Then, the microswitch MS 4  is judged as &#34;yes&#34; to turn OFF TRS, CHVR and CLR. The last named CLR is a relay for an illuminating lamp wherein a lamp CL (see FIG. 2) is turned on to illuminate the original table 8 when the relay is in the ON state. 
     Subsequently, the preheating PH is judged. The preheating means that the fixing station 16 is settled into a relatively low temperature state when power throw. In judging PH, the instruction LB at the 12th step of the page P 11  is fetched so that the address counter BL of the RAM 50 is &#34;1100&#34; and BU is &#34;01&#34; to thereby designate (17). In reply to the instruction DECB the address counter BU is decremented into &#34;1011&#34;. This follows that the strobe signal is derived from the terminal S 5  and supplied via a diode to the input terminal AK of the control element 30. TR 1  effects jump into the sub-routine P 0  and TR 1  is again fetched at the jumped designation to effect jump into the sub-routine P 1 . Again, the SSR/TR0 complex instruction effects jump into P 3  to fetch LAX at the 45th step as shown in FIG. 25. LAX results in the accumulator A bearing &#34;0000&#34; which is added to &#34;0011&#34; of the codes I 4  -I 1  in response to the next ADX, the results being returned back to the accumulator A. Since the adder FA provides no carry, ADX permits the next instruction to be skipped with executing TAK. Since the strobe signal from the terminal S 5  is applied via a diode to the input terminal AK, the next instruction is skipped. This means that PH is judged as &#34;YES&#34;. 
     When in reply to ADX the adder FA provides a carry &#34;1&#34;. RTN 1  is fetched for return to the main-routine so that PH is judged as &#34;YES&#34; and TR 1  is fetched for the test judge. 
     As illustrated in FIG. 37, a diode DPH is connected to effect the preheating in a few minutes, for example, 2 minutes after judging PH. Power supply to the heating lamp HL is controlled to save power energy. A lamp PH is turned ON indicative of the preheating state. 
     If the diode DPH as shown in FIG. 37 is removed, the preheating state is placed after 2 minutes has run. In other words, PH jump is completed as &#34;NO&#34;. 
     As far as PH is judged as &#34;YES&#34;, test judge is concluded as &#34;NO&#34; to set up a two-minute timer circuit which is normally disposed within the control element 30. The instructions are executed immediately after fetching. A duration of time needed for fetching the next succeeding instructions extends for about 10μ seconds. 
     The two-minute timer is judged and &#34;YES&#34; is answered after expiration of two minutes. If print is carried out immediately after power throw, the preheating will work automatically in two minutes. At this time the 2 minute timer is reset so that the heating lamp relay HLR and the preheating PH are ON and the ready lamp is OFF. Because of the heating lamp relay HLR in the ON state the heating lamp HL 1  serving as a standby lamp is turned ON. Meanwhile, in response to the preheating HL 1  in the ON state the heating lamps HL 2  and HL 3  are broken with the WTL circuit 39. The contents of the designations (16), (4), (8) and (12) of the RAM 50 shown in FIG. 35 are transferred into the register W 1  -W 15 . The register stage W 2  provides control signals to rurn ON a display lamp indicating the preheating state, etc., by the driver circuit 32. The control signals from the register W 2  inputs the WTL circuit 39 via the driver circuit 32, etc., to control the heating lamps HL 2  and HL 3 . 
     Next, the microswitch MS 4  is judged as &#34;YES&#34;. Since the drum 1 is in the initial state, PB is judged as &#34;YES&#34; and the slip roller jam SRJ is subjected to judgement. The microswitch MS 2  and the print switch PSW are judged as &#34;NO&#34;. In summary, the machine is settled in the pre-heating state. The print switch PSW serves also to clean the pre-heating state and inform the operator of the pre-heating state when being depressed. When PSW is depressed in the ready state, the print cycle is entered. 
     In other words, when the print switch PSW is operated in the pre-heating state, PSW is judged as &#34;YES&#34; to turn OFF the pre-heating and extinguish the lamp indicative of the pre-heating and actuate the heating lamps HL 2  and HL 3 . The G flip-flop is judged to set the F flip-flop so that the copying machine restores to its initial state. 
     The 2-minute timer begins working if the 2-minute timer is judged as &#34;NO&#34; before starting the pre-heating. The F flip-flop is judged as &#34;YES&#34; after the pre-heating state is cancelled. If &#34;NO&#34; is answered, the microswitch MS 7  is examined to turn ON the ready lamp RL to effect examination of the print switch PSW. When examining the print switch PSW, the strobe signal is derived from the terminal S 3  for confirmation of the ON and OFF states. When the print switch PSW is judged as &#34;NO&#34;, the F flip-flop is reset to repeat again the same operation. This implies the ready state which is visually displayed on the ready lamp RL. The reason why the print switch PSW is examined twice under the circumstances is that the print switch PSW serves both as a pre-heating cancelling switch and copy cycle executing switch, and thus distinction between both is needed. That is, after cancelling the pre-heating, the F flip-flop is set not to judge PSW as &#34;YES&#34;. PSW is, therefore, not judged through examination of the F flip-flop. The copy cycle is not entered as soon as the print switch PSW is depressed during the pre-heating state to cancel the pre-heating. If the copy cycle is entered and the temperature of the fixing station 16 is above the predetermined value, the ready lamp RL is turned ON and no problem is arisen. If the same circumstances are not viewed, WTL is judged as &#34;NO&#34; to turn OFF the ready lamp R. The confirmation signal as to PSW is not outputted and the copy cycle is not entered even when the print switch PSW. 
     The copy cycle begins working the the following manner. 
     The ready lamp RL is turned ON and, when the print switch PSW is depressed, PSW is judged as &#34;YES&#34; as shown in a flow chart of FIG. 30, thereby entering into the copy cycle. This follows that the control element 30 provides control signals to turn OFF the high voltage generation relay THUR. The 2-minute timer is reset. 
     For example, in FIG. 18, the instruction TR 1  at the 28th step enables jump into the sub-routine P 0  to examine PSW in the similar way as discussed above. At this time, &#34;YES&#34; is answered because of the print switch PSW depressed. Thus, TRO at the 29th step of the page P 10  is skipped to execute the next instruction LAX. LAX causes the accumulator A to accept the instruction codes I 4  -I 1 , the accumulator A bearing &#34;0010&#34;. ATF functions to shift the contents of the accumulator A into the register F which is arranged to provide the control signals. To this end, the register F bears &#34;0010&#34;. The contents of the register F are provided as the control signals for the control element 30 thereby turning ON the relay THUR via the driver. Therefore, the contact THUR-a is closed to excite the charger 12 and the discharger or charge remover 18. The contents of the respective register stages F 1 , F 2 , F 3  and F 4  control the high voltage generating relay CHUR, the just mentioned relay THUR, the relay CLR for a lighting lamp CL and the original table return solenoid TRS, respectively. &#34;1&#34; means ON and &#34;0&#34; means OFF. 
     The charging procudure begins in this manner and TR 1  is fetched to reset the 2-minute timer. RTN is called to return the subroutine to the main-routine to fetch SSR at the 33rd step of the P 10 . SSR and TRO together enable jump into the 0th step, the page P 9  (See FIG. 19) to examine the microswitch MS 1  at the 0th step. At the present stage, the microswitch MS 1  concludes as &#34;NO&#34; because of an absence of the copy receiving paper 13. Afterword, LB is fetched so that the address (4) of the RAM 50 as illustrated in FIG. 12 is assigned by the counters BL and BU. The 3rd bit of that position (4) is set as &#34;1&#34; in reply to the instruction SM. This implies that the paper feeding solenoid PFS is in the ON state. The sub-routine P 0  (See FIG. 28) is jumped by TR 1  to fetch at the 32nd step. LB designates (12) of the RAM 50. The 1st bit of the designation (12) stores &#34;0&#34; in accordance with RSM. The ready lamp RL is turned OFF. 
     In addition, the position (8) of the RAM 50 is designated by LB and the 0th bit of that position is set as &#34;1&#34; by SM. Subsequent to this, TR 1  enables jump into the sub-routine P 1  and jump into P 2  in accordance with SSR/TRO complexed instruction. For this reason, NPR is fetched at the 42nd step of P 2  (See FIG. 26) so that the flip-flop NP is reset and the register W 1  -W 15  ceases temporarily providing the control signals. As noted earlier, the contents of the RAM 50 shown in FIG. 35 are shifted into the register W 1  -W 15 . As soon as the contents of the RAM 50 have been completely transferred into the register W 1  -W 15  pursuant to the next succeeding instruction, NPS is fetched to set the flip-flop NP. The contents of the register W 1  -W 15  are outputted as the control signals. Since a duration of period from prohibition against delivering the control signals to cancellation of such prohibition is very short, such duration can be disregarded. The control signals operate the paper feeding solenoid PFS, the drum feeding clutch DFC and the high voltage generating relay THUR. The feeding roller 20 introduces the copy sheet 13 into the interior of the machine. Meanwhile, the rotary drum 1 begins rotating. These events in the copy cycle are illustrated in FIGS. 38(a) and 38(b). Subsequently, referring to FIG. 31(a), the microswitch MS 4  is examined and determined as &#34;YES&#34; to turn OFF the table return solenoid TRS. Then, the input condition of the synchronizing signal PA is examined. The operating state of the microswitch MS 4  is again confirmed to turn OFF TRS. Examination is applied to SRJ, CSSR and MS 2 . Anyway &#34;NO&#34; is answered, the input condition of the synchronizing signal PA is confirmed. When examining the synchronizing signal PA, PA is concluded as &#34;YES&#34; because of &#34;1&#34; applied to the input terminal α. If the synchronizing signal PA-1 is not inputted, the same cycle is repeated to examine again the microswitch MS 4  until the synchronizing PA-1 is received. After confirming receipt of the synchronizing signal PA-1, the solenoid PFS is OFF to supply a memory M with &#34;1&#34;. M+1 remembers that &#34;1&#34; is applied to the RAM 50 and &#34;1&#34; is applied out of the synchronizing signal PA. Upon application of the synchronizing signal PA-2, operation M+1 is executed so that the memory stores &#34;2&#34;. After completing M+1, it is examined whether M=6. When the contents of the memory are 6, &#34;YES&#34; is given. In this case M=1 and &#34;NO&#34; is answered since the synchronizing signal PA-1, in case of M=7 and M=8, &#34;NO&#34; is determined to thereby examine the microswitch MS 4 . The above discussed procedure is performed each time the synchronizing signal is applied. If &#34;YES&#34; is given during examination as to whether M=8, the next stage of the procedure is in effect. 
     With reference to the instructions, the above procedure will be explained in detail. 
     At P 9  (See FIG. 19), TR 1  is fetched at the 17th step to judge PA. In this case, TR 1  enables jump into P 0  (See FIG. 28) to confirm the input condition of the synchronizing signal to allow the TR 1  to be fetched at that jumped position. To this end P 1  (See FIG. 27) is jumped to fetch the instruction TA at the 48th step. TA confirms whether the synchronizing signal PA is applied to the input terminal α. For example, in the absence of the signal at the input terminal α, RTN is fetched. PA is judged as &#34;NO&#34; to effect return to the main routine and to examine the microswitch MS 4 . If the synchronizing signal PA is applied to the input terminal α in TA, LAX is executed rather than the next succeeding instruction. Therefore, the contents of the accumulator A are &#34;0000&#34;  in response to LAX and the adder FA effects addition of &#34;0000&#34; of the accumulator A and &#34;0001&#34; of the codes I 4  -I 1 , the results of addition being loaded into the accumulator. At this time, the accumulator A bears &#34;0001&#34;. Since the adder FA does not output carry &#34;1&#34; by execution of ADX, the next instruction is skipped and TR 0  is executed to perform again ADX. By repetition of the above operation, the adder FA provides carry &#34;1&#34; to fetch the instruction RTN 1 . As a result, PA is judged as &#34;YES&#34;. 
     If RTN 1  is fetched to effect return to the main routine, LB is fetched at the 19th step as shown in FIG. 19. LB designates the position (4) as shown by FIG. 12 by the address counters BL and BU of the RAM 50. TR 1  effects jump into P 0  and TR 1  (the 30th step) and the thus jumped position is fetched to effect again jump into P 1 . TM (the 44th step) is fetched and executed. In FIG. 35, the 3rd bit of the designation (4) stores information concerning the paper feeding solenoid PFS, and thus stores &#34;1&#34;. Since the 3rd bit is &#34;1&#34;, the next instruction RTN (the 45th step ) is skipped to execute the next instruction RSM. Consequently, the 3rd bit of the designation (4) is reset and thus &#34;0&#34;. The contents of the RAM 50 are shifted into the register W 1  -W 15  of which the contents are provided as the control signals. In this case, the solenoid PFS is OFF via the driver 32, M+1 is executed. At this time, the instruction TR 1  (the 21st step of P 9 ) is fetched. As a result, LB (the 2nd step of P 0 ) is fetched to designate (3) of the RAM 50, SSR/TR 0  instruction allows jump into the 51st step of P 3 , LAX forces the contents of the accumulator A into &#34;0001&#34; to fetch the next instruction LAX. In case where LAX is consequently developed, the next one is skipped. ADD11 carries out addition of the contents of the accumulator A and the designation (3) of the addressed RAM 50. The results are transferred into the accumulator A, namely, the accumulator A assumes &#34;0001&#34;. In case where the adder FA has no carry &#34;0&#34;, the next instruction is skipped to execute the next instruction. EXC is executed so that &#34;0001&#34; of the accumulator A is transferred into the designation (3) at the RAM 50 addressed. The contents of the designation (3) are &#34;0001&#34;. Thereafter, RTN is fetched for return to the main-routine, thereby fetching the 22nd step of P 9 , that is, LAX. The RAM 50 stores the first synchronizing signal PA-1. 
     Examination as to whether M=6 is effected. LAX carries out comparison between the contents of the accumulator A and the contents of the designation (3) of the RAM 50 presently addressed. In this instance, answer is &#34;NO&#34;. The same answer is resulted for M=7 and M=8. As shown in FIG. 31(a), the microswitch MS 4  is examined. 
     After repeating the above operation, if the drum 1 rotates and the 6th of the synchronizing signals obtained from such rotation is applied to the input terminal α of the control element 30, the contents of the designation (6) of the RAM 50 assume &#34;6&#34; or &#34;0110&#34;. For judgement as to whether M=6, &#34;YES&#34; is judged, followed by examining the B flip-flop. The B flip-flop concerns exchange of the light-sensitive master paper 3. Such judgement is of course concluded as &#34;NO&#34;. For this reason, the operation is repeated. The 7th pulse of the synchronizing pulses PA is inputted and stored in the designation (3) of the RAM 50. The contents of the designation are &#34;0111&#34;. For M=6, judgement &#34;NO&#34; is answered, but for M=7, judgement &#34;YES&#34; is answered. Judgement as to CSSR provides answer &#34;NO&#34;. 
     It will be easily understood that when the 8th pulse PA-8 of the synchronizing signals PA is applied, judgement for M=8 is concluded as &#34;YES&#34;. The contents of the designation (3) of the RAM 50 are &#34;0000&#34;. When confirming the microswitch MS 4 , it is inclined to NO site to thereby sense the original table 8 in its initial state. Since examination for MS 4  is concluded as &#34;YES&#34;, the original table return solenoid TRS is turned OFF. The slip roller jam SRJ 1  is judged as &#34;NO&#34; because of the absence of the copy paper 13. Therefore, PA is examined. PA examination is carried out on the 9th pulse PA-9 of the synchronizing signals PA and, when that signal PA-9 is applied to the input terminal α, &#34;YES&#34; is answered. WTL is judged when the temperature of the fixing station has reached the predetermined one, SRJ and MS 4  are judged. Then, the microswitch MS 1  is judged. Under the circumstances the microswitch MS 1  does detect the copy sheet 13 and inclines to NO site. In conclusion, due to the solenoid PFS in the ON state, one copy sheet 13 is conveyed into the machine by the feeding roller 20. 
     The copy paper 13 is temporarily clutched by the paper stopper PS and at this time the microswitch MS 1  detects arrival of the paper. When confirming the operating state of the microswitch MS 1 , the strobe signal is outputted from the terminal S 2  and transferred via the NO site of MS 1  and the diode into the terminal KN 2 . This confirms the microswitch MS 1  at the NO site and provides answer &#34;YES&#34;. As a result, the high voltage relay CHUR and the lamp relay CLR are turned ON. TRS remains in the OFF state and DFC remains in the ON state. The output signals from the register F 1  -F 4  are control signals to turn ON CHUR and CLR. In other words, &#34;1&#34; is inputted to the register stages F 1  and F 3 . The contents of the accumulator A are changed into &#34;0101&#34; in response to the instruction LAX and then transferred into the register F in response to ATF. Since THUR has been previously in the ON state, the contents of the accumulator A may be &#34;0111&#34;. 
     As noted earlier, the lamp CL is turned ON and the charger 6 is excited to provide uniform charge for the master paper 3 when the rotary drum 1 rotates and the 9th pulse PA-9 of the synchronizing signal PA is developed as shown in the time charts of FIGS. 38(a ) and 38(b). 
     Subsequently, PA is judged and then PB is judged. In response to receipt of the synchronizing signal PB, the copy sheet 13 is conveyed in synchronization with rotation of the rotary drum 1. At a point in time when the synchronizing signal PB-2 is inputted, the stopper solenoid PSS is turned ON to release the stopping of the copy sheet 13. The 10th pulse signal of the synchronizing pulses PA drives the development station and the original table S. Relative alignment of the slits Pa-10 and Pb-2 determines whether both synchronizing signals PB-2 and PA-10 are simultaneously developed or which one of both is developed earlier. 
     In the case where the synchronizing signals PB-w are developed earlier during PB judgement, the stopper solenoid PSS is turned ON and PA continues to be examined until the synchronizing signals PA-10 are developed. When the synchronizing signals PA-10 are inputted, the development motor relay DMR and the original table feed clutch TRC are placed into the ON state. Conversely, if the synchronizing signals PA-10 are inputted, the development motor relay DMR and the original table feed clutch TRC are in the ON state. When applying PB-2, the solenoid PSS is turned ON. Therefore, as shown by the flow chart, the motor relays DMR and TFC are ON and PSS is ON to render the development 11 and the original table 8 operative. The copy sheet 13 is conveyed. In this case, the microswitch MS 4  is inclined to NC. 
     After execution of M+1, the designation (3) of the RAM 50 stores application of the synchronizing signals PA-10 and flip-flops E, H and O are judged. These flip-flops not in the set state are judged as &#34;NO&#34;. The microswitch MS 5  is judged as &#34;NO&#34;. The microswitch MS 5  is examined, which senses excess advance of the original table 8. At this time, microswitch MS 5  is concluded as &#34;NO&#34;. Judgement is shifted into the microswitch MS 1 . The microswitch MS 1  will be inclined to NC site when passing the trailing edge of the copy sheet 13. In this case, the microswitch MS 1  is not inclined to the NC site and judged as &#34;YES&#34;. PA is examined to confirm the input conditions of the synchronizing signal PA-11. As far as the drum 1 rotates and synchronizing signal PA-11 is applied, PA is concluded as &#34;YES&#34; to effect M+1. According to M+1, the designation (3) of the RAM 50 stores addition of &#34;1&#34;. Since when applying the synchronizing signal PA-10 M+1 is executed and the designation (3) of the RAM 50 stores &#34;1&#34;, that designation (3) of the RAM 50 stores M+2 upon receipt of the synchronizing signal PA-11. Therefore, M=1 judgement is concluded as &#34;NO&#34; because the designation (3) of the RAM 50 stores M=2. M=4, 5, 6, 7, 8 and 9 are next examined. In these examination procedures, &#34;NO&#34; is given and the E flip-flop is judged. In this manner, M+1 is executed each time the synchronizing signals PA, which of the synchronizing signals is stored. In other words, the position of the rotary drum 1 is confirmed. As soon as the microswitch MS 1  detects the trailing edge of the copy sheet 13 and declines to the NC site, the stopper solenoid PSS is turned OFF and the next succeeding copy sheet 13 ceases going ahead at that position. In this case, the microswitch MS 1  is judged as &#34;NO&#34; to turn OFF PSS. In the time chart B5, A4 and B4 represent the size of the copy paper 13. 
     When the contents of the designation (3) of the RAM 50 are &#34;0100&#34; and the synchronizing signal PA-1 is inputed, the flip-flops P and C and the stopper solenoid PSS are judged. Referring to the time chart of FIG. 38(2), in case of B 5  size, the microswitch MS 1  is in the NC site prior to application of the 2nd synchronizing signal PA-1 and MS 1  is judged to turn OFF the stopper solenoid PSS. In case of size A 4  or B 4 , the microswitch MS 1  detects the arrival of the copy paper 13. The stopper solenoid PSS remains in the ON state. Under the conditions that the synchronizing signal PA-1 is applied and M=4, PSS is concluded as &#34;NO&#34; for the copy sheets of B 5  size and &#34;YES&#34; for the copy sheets of A 4   and B 4 . In the following the copy sheets of B 5  size will be discussed. 
     Therefore, the C flip-flop is set after examining PSS. In FIG. 36, the 2nd bit of the designation (2) of the RAM 50 stores &#34;1&#34;. After judging M=6, M=9 and M=8, the E flip-flop is again judged. 
     The synchronizing signal PA-2 is applied and M+1 is executed durng PA examination. The designation (3) of the RAM 50 stores &#34;0101&#34;. Because the C flip-flop is in the set state, the P flip-flop is set after judgement as to the C flip-flop. The E flip-flop is judged. When the synchronizing signal PA-3 is applied to the input terminal α of the control element 30 during PA examination, the designation (3) of the RAM 50 stores &#34;0110&#34;. 
     After judging the P flip-flop, the development motor relay DMR is turned OFF. The development motor contained within the development station 11 is stopped dependent upon the size of the copy paper 13. For example, the development ceases working when M=8 or the synchronizing signal PA-5 is applied in case of A 4  size, and when the synchronizing signal PA-6 is applied in case of B 4  size. 
     During M=6 judgement the designation (3) of the RAM 50 stores &#34;0110&#34; and then the E flip-flop is set. The operating state of the microswitch MS 2  is confirmed after judging the E flip-flop. In this case, the microswitch MS 2  is inclined to the NO site because the copy paper 13 in contact with the master paper is removed therefrom. But if the microswitch MS 2  is inclined to the NC site, the copy paper 13 remains in close contact with the drum 1 to inform JAM. The following description concerns operation where &#34;YES&#34; is answered. PA is again judged. PA judgement is effected on the synchronizing signals PA-4 to execute M+1. 
     Since answer &#34;NO&#34; is given for judgements M=6, M=9 and M=8,  the E flip-flop is again judged to sense the next synchronizing signal PA-5. MS 5  is turned ON if the original table 8 has overadvanced when confirming the operating state of the microswitch MS 5  prior to PA judgement. For this reason, the strobe signal is derived from the terminal S 1  and then supplied to the input terminal AK, thereby confirming the ON state of the microswitch MS 5 . In judging PSS the high voltage relay CHUR and the original feed clutch TFC are turned OFF. After judging the O flip-flop the H flip-flop is set. The H and O flip-flops relate to a 220 ms timer to be described later. The charging operation of the charger 6 is stopped since the original table 8 is stopped and the charging relay CHUR is turned OFF due to the above discussed operation. 
     At the present stage, the microswitch MS 1  does not detect the introduction of the copy paper 13 and thus the copy paper stopper solenoid PSS is in the OFF state. Meanwhile, the microswitch MS 2  detects removal of the copy paper 13 and inclines to the NO site. But, the microswitch MS 3  does not detect the leaving copy sheet 13 and is positioned at the NC site. The microswitch MS 4  is positioned at the NC site because the original table 8 moves from its initial position due to the original feed clutch in the ON state. The microswitch MS 5  detects overadvanced original table 8 so that the original table feed clutch TFC is turned OFF to force the original table 8 and the charger 6 into the stop condition. 
     If application of the synchronizing signal PA-5 has not yet been confirmed, the E and H flip-flops are examined. The H flip-flop is in the set state to set the 220 msec timer. This 220 msec timer prohibits movement of the original table 8 for 220 msec, that is, a duration of period beginning with turning OFF of the original feed clutch TFC and ending at turning ON of the original table return solenoid. Otherwise, TRS will be turned ON immediately after the original table 8 stops moving, thereby damaging clutches, gears, etc. The above mentioned timer is not necessarily needed and is normally contained within the control element 30. 
     If the timer is set and the synchronizing signal PA-5 is not confirmed. The above operational cycle is repeated such that the original table return solenoid TRS is turned ON for return of the table after expiration of 220 msec. Then, the 220 msec timer is reset so that the H flip-flop is set and the O flip-flop is set. The O flip-flop is judged as &#34;YES&#34; to effect confirmation of one microswitch MS 4 . The microswitch MS 4  is positioned in the NC site because the original table 8 is not in the initial state. The control element provides control signals effective to turn ON the original return solenoid TRS. In reply to the receipt of the synchronizing signal PA-5 the designation (3) of the RAM 50 assume &#34;1000&#34;. 
     After &#34;YES&#34; is answered during M=8 judgement, the E flip-flop is placed into the reset state and the microswitch MS 6  is subjected to examination. The function of the microswitch MS 6  is to confirm the multi-copy dial which is in the OFF state (see FIG. 37) and are judged as &#34;NO&#34; in case of one copy. The E flip-flop is again judged. In case of multi-copy the above operation is repeated after the microswitch MS 1  is confirmed and the paper feed solenoid PFS is turned ON. 
     Upon receipt of the synchronizing signal PA-6, M+1 is executed so that the contents of the designation (3) assume &#34;1001&#34; (M=9). For this reason, the microswitch MS 4  is confirmed and the original return solenoid TRS is turned ON or OFF after M=9 is determined and PFS, DMR and TFC are turned OFF. In other words, if the original table 8 is returned to the home position, the microswitch MS 4  will sense this. This confirmation is accomplished by outputting the strobe signals from the terminal S 1 , thereby turning OFF the original return solenoid TRS. Is confirmed whether the synchronizing signal PA-7 is applied. Thereafter, the mocroswitch MS 3  is judged. The microswitch MS 3  detects the leaving of the copy paper 13 carrying the toner image and is now in the NO site. Otherwise, conveyance of the copy paper 13 is evaluated as abnormal to warn jam. After confirming the operational state of the microswitch MS 3  a total counter TC is turned ON and one incremented. After sensing the microswitch MS 4  the synchronizing signal PA-8 is confirmed to turn OFF PSS, CHUR, CLR and TC. Simultaneously, the designation (3) of the RAM 50 assumes &#34;0000&#34; and the timer is OFF and the respective flip-flops O, C and P are reset. 
     The microswitch MS 4  is judged after completing the above operational sequence (see FIG. 31(a),*11). The operational state of the synchronizing signal PA-9 is confirmed to see the inputs from the WTL circuit. The microswitch MS 4  is again confirmed until it is switched to the NO site. At this moment the drum feed clutch DFC is turned OFF to prevent to rotary drum 1 from revolving. When the microswitch MS 4  is turned to the NO site, judgement is shifted into the microswitch MS 1 . If it is desired to make multi-copies, the feeding paper solenoid PFS is turned ON to enter into the subsequent copy mode. When the microswitch MS 1  does not sense the arrival of the paper, the operation is executed to seek the original position of the rotary drum 1. As illustrated in FIG. 29, the ready lamp RL is turned OFF and the drum feed clutch DFC is turned ON. The rotary drum 1 rotates again. When entering into the multi-copy mode the microswitch MS 4  is inclined to the NO site and the original return solenoid is turned OFF to restore the original table 8 into the original position. PA is judged under the circumstances that the synchronizing signal PB (the slit Pb-2) is applied during PB judgement. Next, PB judge confirms the synchronizing signal PB-1 and the D flip-flop is placed into the set state when the synchronizing signal PA-11 is inputted. The D flip-flop is reset when the next synchronizing signal PA-0 is applied. The drum feed clutch DFC is OFF. In other words, the drum 1 is in the initial state (namely, stopped) as far as the synchronizing signals PA-11 and PA-0 are inputted. Subsequently, the ready state is reached to turn ON the ready lamp RL. 
     As discussed above, the copying machine of the present invention is controlled by the one-chip control element 30. Since according to the present invention the control element 30 provides the strobe signals to confirm the operational states of the respective microswitches together with the synchronizing signals PA and PB obtainable from the revolution of the drum 1, as viewed from FIG. 37, the number of the wires leading from the microswitches is considerably reduced. 
     In operation, when conveyance of the copy paper 13 is abnormal, the so called jam state is sensed by the slip roller jam SRJ or the respective microswitches to enter into jam cycle. The cycle is illustrated in FIG. 32. 
     In FIG. 32, all the loads are placed into the OFF state when finding out jam. LB is fetched from the 50th step of p 5 as illustrated in FIG. 23, thereby designating (0) of the RAM 50. The succeeding instruction TR 1  enables jump into the sub-routine P 0  (FIG. 28). TR 1  (P 0 , 6th step) is fetched and P 1  is again jumped to execute the instruction LAX (P 1 , 54 step). Due to LAX the accumulator A is modified into &#34;0000&#34; and (0) of the RAM 50 assigned by EXCI also assumes &#34;0000&#34;. After the contents of the RAM 50 are all modified into &#34;0&#34; as shown in FIG. 35, RTN is fetched returning to the main routine from the sub-routine. LAX at the 58th step of P 5  is executed so that the register F assumes &#34;0000&#34; in response to ATF without development of the control signals. 
     LB designates (12) of the RAM 50 (see FIG. 35). P 10  is jumped in response to SSR/TR0 instruction. SM (35th step) permits the 3rd bit of (12) of the RAM 50 designated by LB to store &#34;1&#34;, indicating that the jam relay JR is turned ON in FIG. 35. TR1 enables jump into the sub-routine where the contents of the RAM shown in FIG. 35 are transferred into the register W 1  -W 15  within the control element 30. The flip-flop NP is set and the register W 1  -W 15  provides control signals to turn ON the jam relay JR. After that, the jam relay contact JR-a is judged as illustrated in the flow chart of FIG. 32. If the jam relay contact JR-a operates, the jam relay JR is turned OFF. Once the jam relay JR operates its associated contact JR-a is held in the closed state, the contact JR-a may be manually released. 
     The jam relay contact JR-a is confirmed until it delcines to the NO site and the jam relay JR is turned OFF after completing such confirmation. The jam lamp timer JLT is reset to repeat confirmation of the contact JR-a. In this case &#34;YES&#34; is answered. If the contact JR-a is open due to any cause, the above discussed operation is repeatedly carried out. In case of &#34;YES&#34; the jam lamp timer JLT starts to operate to judge the jam lamp timer JLT. JLT is judged as &#34;YES&#34; after a predetermined period of time has expired. The jam lamp JL is turned ON thereby indicating jam or error state and setting the K flip-flop. After the jam lamp timer JLT is reset, operation of the timer is repeated. If &#34;YES&#34; is answered in judging the jam lamp timer JLT, the K flip-flop is judged. Since the K flip-flop is in the set state, the jam lamp JL is OFF and the K flip-flop is reset. The jam lamp JL blinks each time the period determined by the jam lamp timer JLT has elapsed, indicating the jam state. The determined period is, for example, 500 msec. 
     LB is fetched at the 40th step as shown in FIG. 18. The designation (19) of the RAM 50 is assigned and TR1 permits the designation (19) to store &#34;0&#34;. Subsequently, TR 1  at the 42th step enables sub-routine jumb and executes judgement as to the jam relay contact JR-a. In this case &#34;YES&#34; is answered and TR 1  is fetched at the 44th step thereby initiating operation of the timer. Therefore, LB at the 57th step of the sub-routine page P 0  (see FIG. 28) is fetched to designate (19) of the RAM 50. Jump is effected because of TR 0  and the 51st step of P 3  (see FIG. 25) is jumped due to SSR/TR 1  instruction. LAX is fetched, which permits the accumulator A to assume &#34;0001&#34;. LAX is skipped and thus ADD11 is executed. ADD11 performs addition of the contents of the accumulator A and the contents of the RAM 50 addressed (that is, &#34;0000&#34; is the designation (19)), the results being transferred back to the accumulator A. In conclusion, the accumulator A assumes &#34;0001&#34;. Because the adder FA carries &#34;0&#34; during ADD11 execution, the next instruction is skipped with executing EXC. For this reason the contents &#34;0001&#34; of the accumulator A are supplied to the designation (19) of the RAM 50. RTN is called back for return to the main-routine. 
     Thereafter, as viewed from FIG. 18, TR 1  at the 45th step is fetched to execute test judge. Since &#34;NO&#34; is answered, TR 0  is fetched which enables jump within the same page to fetch LB. 
     LB designates the position (11) of the RAM 50. In the event that the 1st bit of the designation (11) stores &#34;1&#34; due to the instruction TM, the next instruction is skipped. However, since the 1st bit bears &#34;0&#34; in this case, TR 0  enables jump within the same page to judge the jam relay contact JR-a. This implies that the jam lamp timer JLT is judged. When the 1st bit of the designation (11) of the RAM 50 bears &#34;1&#34;, LB at the 52nd step is fetched to examine the K flip-flop. 
     Although the designation (19) of the RAM 50 assumes &#34;0001&#34;, &#34;YES&#34; is answered when the designation (11) of the RAM 50 is &#34;0010&#34; during judgement is to the jam lamp timer JLT. Because the designation (11) of the RAM 50 assumes &#34;0000&#34; in this case, &#34;NO&#34; is resulted. By repeating the above operation, the contents of the designation (19) of the RAM 50 are modified. In other words, the designation (19) of the RAM 50 counts the number of repeated operations. When the operations are repeated 15 times, the designation (19) reaches &#34;1111&#34;. Upon the 16th operation LAX at the 51th step modifies the accumulator A into &#34;0001&#34;. ADD11 executes addition of &#34;0001&#34; of the accumulator A and &#34;1111&#34; of the designation (19) of the RAM 50 now addressed. As a result, the adder FA outputs carry &#34;1&#34;. Execution of the next instruction TR 0  permits EXCI to be fetched EXCI shifts the contents of the accumulator A into the designation (19) of the RAM 50 assuming &#34;0000&#34;. The counter BL addressing the step of the RAM 50 is one incremented with assuming &#34;1101&#34;. The designation (7) of the RAM 50 is assigned (see FIG. 12). LAX is fetched to modify the contents of the accumulator A into &#34;0000&#34;. ADD 11 executes addition of the contents of the accumulator A and the contents of the designation (7) of the RAM 50 plus the carry &#34;1&#34;, the results thereof being supplied to the designation (7). Thus, the designation (7) stores &#34;0001&#34;. When the designation (11) bears &#34;0010&#34;, 500 msec has elapsed. Therefore, as shown in FIG. 18, LB designates (11) of the RAM 50 during judgement as to the jam lamp timer JLT. The 1st bit designated by I 1  and I 2  bears &#34;1&#34; and the next instruction is skipped with executing LB. When the designation (11) bears &#34;0010&#34;, the above operation is repeated 512 times. This indicates expiration of 500 msec. 
     As viewed from FIG. 36, the 3rd bit of the RAM designated position (14) stores the K flip-flop. Since in the case the 3rd bit is &#34;0&#34;, TM at the 53rd step serves to confirm the state of the K flip-flop. TR 0  enables jump into the same page to execute the instruction IDFR at the 58th step. IDFR resets the flip-flop IDI which provides its output IDF as control signals for the driver J2 to light the jam lamp JL. That is, when the flip-flop IDF is reset, the jam lamp JL is excited. If it is set, JL is extinguished. The jam lamp JL blink at the period of 500 msec. 
     Exchange of the master paper 3 is carried out in the following manner with reference to FIG. 39. 
     After the rotary drum 1 rotates three times, exchange of the master paper 3 is finished. The microswitch MS 7  detects the introduction of the master paper 3. The arrived master paper 3 is arrested by the stopper MS. The microswitch MS 7  is confirmed as &#34;YES&#34; (see FIG. 30). 
     CSSR is turned ON as shown by FIG. 34. When the solenoid CSSR is released, the master paper 3 is free. When that relay is ON, its contact CSSR-a is closed. Conversely, when it is ON, the contact CSSR-a will restore to its home position. After judging CSSR-a, the power relay PR and the relay CSSR is turned OFF and the solenoid CSS is turned ON. 
     The drum 1 rotates and the synchronizing signals PA and PB control are exchange cycle. When the master paper 3 reaches the pick off means 15 due to rotation of the drum 1, it will be separated from the drum 1. In FIG. 31(a), application of the synchronizing signal PA-7 confirms the contact CSSR-a after M-7 judgement. In this case the contact CSSR-a is in the NO site to shift judgement into the microswitch MS 2 . &#34;YES&#34; is obtained to confirm the microswitch MS 3 . If MS 3  does not see leaving of the master paper 3, jam state is informed. Otherwise, the contents of the RAM bear &#34;0&#34;. 
     The drum 1 continues to rotate to seek the initial conditions. As illustrated in the flow chart of FIG. 29, the B flip-flop is set after examining the relay contact CSSR. When the synchronizing signal PA-6 is supplied during the 2nd rotation of the drum 1, the 13 flip-flop is judged as &#34;YES&#34; is illustrated in FIG. 31(a). As a result, the master stopper solenoid MSS is turned ON after examination of MS 7  together with stopping of the rotation of the drum 1. To this end the stopper MS is open to introduce the master paper 3 into the interior of the machine. 
     The drum 1 restarts to rotate after expiration of 1.5 msec. Thereafter, the rotary drum is set into its initial state and the B flip-flop is judged as &#34;YES&#34; as shown in FIG. 29. PA is judged as shown in FIG. 33, which confirms the input state of the synchronizing signal PA-1. Upon receipt of the synchronizing signal PA-1 the relay CSSR is turned ON and the solenoid CSS is turned OFF. At this time the leading edge of the master paper 3 is arrested by finger means. After the synchronizing signal PA-2 is applied. The relay CSSR is turned OFF and the B flip-flop is reset. 
     Afterword, the rotary drum 1 rotates until its initial state is reached. In case where CSSR is ON and CSS is OFF, the power relay PR is turned ON to light the heating lamps HL 2  and HL 3 . Thus, the exchange cycle is completed. 
     The invention being thus described, it will be obvious that the same way be varied in many ways. Such variations are not to be regarded as a departure form the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.