Abstract:
Switch card apparatus are disclosed. In one embodiment, a circuit includes a first portion having a first switch adapted to be coupled to a first voltage, a second portion including a second switch, and a third portion including a third switch. The first portion activates the first switch to couple the first voltage to the second portion. Similarly, the second portion activates the second switch in response to a second input signal and the first voltage to couple a second voltage to the third portion. Finally, the third portion activates the third switch in response to a third input signal and in response to the second voltage from the second portion to couple a control voltage to a load. Embodiments of the invention provide the desired reliability suitable for a variety of electrical systems, including arming and firing applications over a wide voltage and wide current range.

Description:
STATEMENT OF GOVERNMENT INTEREST  
       [0001]     This invention was made with government support under U.S. Government Contract HQ0006-01-C-0001 awarded by the United States Army. The U.S. Government has certain rights in this invention. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present disclosure relates to switch cards for electrical systems, and more specifically, to switch card apparatus and methods having wide voltage range, high current capability for use with, for example, safe and arm devices for missiles.  
       BACKGROUND OF THE INVENTION  
       [0003]     The handling of live missile boosters presents obvious dangers to personnel. Conventional safe and arm devices are mechanical relays that fully isolate the battery from the squib for purposes of firing train interruption. Applicable specifications (e.g. Mil-STD-1901A) typically require safe and arm devices to include the ability to eliminate a single fault scenario. Particular program requirements may impose more stringent safety specifications.  
         [0004]     Although desirable results have been achieved using prior art safe and arm devices, there may be room for improvement. For example, each missile may have a variety of critical signals that must be isolated, each of which may have widely different voltage and current levels. A particular missile&#39;s load current variability may be very high with an extremely wide voltage range that requires a specific design solution. Thus, conventional safe and arm devices are typically designed for a particular missile, and lack the capacity to handle the range of voltages and current variabilities presented by multiple missile types.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention is switch card switch card apparatus and methods for electrical systems. Embodiments of the present invention may provide a safe and reliable solution as an acceptable safe and arm device on multiple missile configurations, meeting or exceeding isolation requirements for safely isolating the battery and squibs and ensures personnel safety during the handling of live missile boosters. Furthermore, embodiments of the present invention may be capable of handling a wide voltage and current range, suitable for use in association with multiple missile and safety applications.  
         [0006]     In one embodiment, an arming and firing circuit for applying a control voltage to a load includes a first portion having a first switch adapted to be coupled to a first voltage, a second portion operatively coupled to the first portion and including a second switch, and a third portion operatively coupled to the second portion and adapted to be coupled to the load, the third portion also including a third switch. The first portion is adapted to receive a first input signal and to activate the first switch in response to a first value of the first input signal to couple the first voltage to the second portion. Similarly, the second portion is adapted to receive a second input signal and to activate the second switch in response to a second value of the second input signal and in response to the first voltage from the first portion to couple a second voltage to the third portion. Finally, the third portion is adapted to receive a third input signal and to activate the third switch in response to a third value of the third input signal and in response to the second voltage from the second portion to couple the control voltage to the load.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]     Preferred and alternate embodiments of the present invention are described in detail below with reference to the following drawings.  
         [0008]      FIG. 1  is a schematic view of a missile assembly coupled to a test system in accordance with an embodiment of the present invention;  
         [0009]      FIG. 2  is an isometric view of the assembly test equipment module of the test system of  FIG. 1 ;  
         [0010]      FIG. 3  is a block diagram of a missile assembly coupled to a test system in accordance with an embodiment of the invention; and  
         [0011]      FIG. 4  is a circuit diagram of the switch card of  FIG. 3 . 
     
    
     DETAILED DESCRIPTION  
       [0012]     The present invention relates to switch card apparatus and methods for electrical systems. Many specific details of certain embodiments of the invention are set forth in the following description and in  FIGS. 1-4  to provide a thorough understanding of such embodiments. One skilled in the art, however, will understand that the present invention may have additional embodiments, or that the present invention may be practiced without several of the details described in the following description.  
         [0013]     In general, embodiments and apparatus and methods in accordance with the present invention provide a safe and reliable solution as an acceptable safe and arm device on multiple missile configurations, meeting the requirements for safely isolating the battery and the squibs, and ensuring personal safety during the handling of live missile boosters. Because embodiments of the present invention are adapted to handle a wide voltage and current range, multiple missile and safety applications may be safely accommodated.  
         [0014]      FIG. 1  is a schematic view of a missile assembly  100  coupled to a test system  110  in accordance with an embodiment of the present invention. In this embodiment, the missile assembly  100  includes a payload module  102  coupled to a Booster Avionics Module (BAM)  104 . The missile assembly  100  further includes a third stage motor  106 , a second stage motor  107 , and a first stage motor  108 . The Booster Avionics Module  104  includes control circuitry coupled to the payload module  102  and to the motors  106 ,  107 ,  108 , and the BAM  104 . The BAM  104  is adapted to receive control signals and to transmit appropriate commands to the various components of the missile assembly  100 .  
         [0015]     The test system  110  includes an assembly test equipment module  112  coupled to a booster emulator module  114  which is, in turn, coupled to the Booster Avionics Module  104  of the missile assembly  100 . The telemetry system  116  receives signals from the control module  104  and transmits the signals to the assembly test equipment module  112 .  
         [0016]      FIG. 2  is an isometric view of the assembly test equipment module  112  of the test system  100  of  FIG. 1 . As shown and  FIGS. 1 and 2 , a subassembly  118  of the assembly test equipment module  112  includes a host computer  120  coupled to a first data processing system  122 , a second power conditioning system  124 , and a monitor and keyboard  126 . In one embodiment, the first electronics system  122  may be a PCI eXtensions for Instrumentation (PXI) chassis, and the second electronics chassis  124  may be an SCXI electronics chassis, such as, for example, the models of PXI chassis and SCXI chassis commercially-available from National Instruments Corporation of Austin Texas. In one particular embodiment, the PXI chassis  122  is a single 3U chassis with a PCI back plane. The PXI chassis  122  houses the primary processor and data capture components to support the test/launch functionality in  FIG. 1 . The embedded processor has state of the art memory and hard drive capability. It may have several high speed Analog to Digital (A to D) cards in the system which provide high speed multiple channels of data capture and sampling, and may also have several programmable events driven opto-isolated digital input/output (DIO) cards and a single TTL DIO card. These cards provide the input stimulus required to drive the input circuits of the Wide Voltage Range Wide Current Range switch cards used primarily to switch ground power to  FIG. 100 . Each component of the PXI chassis is part of the analog measurement chain required to accurately and safely test/launch the components of  FIG. 1 .  
         [0017]     In one embodiment, the SCXI  124  is a 4U chassis that houses signal conditioning boards which will manipulate the analog voltages into the appropriate ranges required to feed the A to D cards. The SCXI contains a programmable switch matrix card used in conjunction with the analog measurement system to measure assembly test equipment simulated load box parameters. Each component of the PXI chassis is part of the analog measurement chain required to accurately and safely test/launch the components of  FIG. 1 . The subassembly  118  also includes a pair of switch boxes  128 , which contain multiple versions of the invention, and load boxes  130 . Power supplies  132  are coupled to the subassembly  118 , and fans  134  provide cooling flow to the components of the assembly test equipment module  112 , specifically to  128  and  130 . Switch card boxes  136  are coupled between the subassembly  118  and the booster emulator module  114 .  
         [0018]      FIG. 3  is a block diagram of a missile assembly  300  coupled to a test system  310  in accordance with an embodiment of the invention. The missile assembly can include both squibs to activate various systems within the First Stage Motor  108 , Second Stage Motor,  107 , and Third Stage Motor  106 , or sequenced power inputs within the Payload  102 , BAM  104 , First Stage Motor  108 , Second Stage Motor,  107 , and Third Stage Motor  106 . In this embodiment, the test system  310  includes a computer  312  that provides inputs to a switch card  314 . In turn, the outputs of the switch card  314  are coupled to the missile assembly  300 . In operation, the switch card  314  advantageously has the capability of driving resistive or inductive-resistive loads over a wide voltage range and wide current range. For example, in one particular embodiment, the switch card  314  has the capability of driving resistive or inductive loads over a voltage range of 12 to 100 V, and a current range of 0 to 12 Amps. Minor adaptations to this circuit can substantially increase both the voltage and current range.  
         [0019]      FIG. 4  is a circuit diagram  400  of the switch card  314  of  FIG. 3 . As shown in  FIGS. 3 and 4 , the switch card  314  may be divided into six sections for simplicity. A first section  316  (Section  1 ) performs input signal conversion. Three independent input signals (CONTROL_IN 1 , CONTROL_IN 2 , and CONTROL_IN 3 ) must be initiated for circuit activation (two fault tolerant system). Each input signal passes through an optocoupler (or optoisolator) (U 2 ) which provides ground and noise isolation between the computer input signals and the firing circuitry (Sections  2 - 6 ) described below. As used in this application, the terms optocoupler and optoisolator are used interchangeably.  
         [0020]     A second section  318  (Section  2 ) provides the filtering for an input battery voltage  320  and dc voltages (C 1 -C 3 , C 9 -C 11 , C 15 -C 20 , and C 28 -C 29 ) and a voltage regulation (VR 1 ). A third section  322  (Section  3 ) includes signal conditioning  324  and high side switch circuitry  326  for the first input signal CONTROL_IN 1 . The third section  322  works as a safe and arm for the firing circuitry of a fourth and fifth sections  328 ,  330  (Sections  4  and  5 ). As shown in  FIG. 4 , when activated, a signal out of the optocoupler U 2  enters the third section  322  and deactivates a first transistor Q 4 , which turns on a second transistor Q 3 , and then a third transistor Q 1 , and a fourth transistor Q 2 . In one embodiment, the third transistor Q 3  is an n-channel MOSFET which turns on the p-channel MOSFETs Q 1  and Q 2 . Transistors Q 1  and Q 2  are connected in parallel to allow increased current capability. Transistors Q 1  and Q 2  also separate the battery power  320  from next stage circuitry. When the third section  322  (Section  3 ) is deactivated, the first transistor Q 4  turns on, which shuts off transistors Q 3 , Q 1 , and Q 2 .  
         [0021]     Specifically, in the embodiment show in  FIG. 4 , the activation works as follows: the first input signal CONTROL_IN 1  (e.g. a +5V signal) comes from the computer inputs  312  into a resistor R 24  and the optocoupler U 2 . The first input signal CONTROL_IN 1  turns on a light emitting diode inside of the optocoupler U 2  forcing the output of the optocoupler U 2  to go low. This shuts off the first transistor Q 4 , which produces a voltage divider output at resistors R 7 , R 10 , and R 12  (e.g. of 12 V) at the gate-to-source of transistor Q 3 . This turns on the second transistor Q 3  setting up another voltage divider at resistors R 6  and R 8  (e.g. of 12 V) from transistors Q 1  and Q 2  gate to source. Transistors Q 1  and Q 2  then turn on, thereby closing the switch  326  ( FIG. 3 ) and allowing the battery voltage  320  to go to the fourth section  328  (Section  4 ). This activation pattern is similar in the fourth and fifth sections  328 ,  330  (Sections  4  and  5 ). A pair of diodes VR 5  and VR 8  (e.g. Zener diodes) limit the maximum divider voltage across the gate to source of the transistors Q 3 , Q 1 , and Q 2  (e.g. to 15 V) over a relatively wide voltage range input (e.g. 12 to 100 Vdc).  
         [0022]     The deactivation works as follows: a deactivation signal (e.g. 0V) comes from the computer  312  into the resistor R 24  and the optocoupler U 2 . The deactivation signal turns off the light emitting diode inside of the optocoupler U 2  forcing the output of the optocoupler U 2  to go high. This turns on transistor Q 4 , grounding off transistor Q 3 . With transistor Q 3  off, the gate to source voltage across transistors Q 1  and Q 2  is zero, keeping both transistors Q 1  and Q 2  off, and opening the switch  326 . This deactivation pattern is also similar in the fourth and fifth sections  328 ,  330  (Sections  4  and  5 ).  
         [0023]     As mentioned above, the fourth section  328  (Section  4 ) works in a similar manner to the third section  322  (Section  3 ) and includes a signal conditioning  332  and a high side switch circuitry  334  for a second input signal CONTROL_IN 2 . When activated, the signal out of the Optocoupler U 2  deactivates Q 8 , which turns on transistor Q 7 , and then transistors Q 5 , and Q 6 . In a presently preferred embodiment, transistor Q 7  is an n-channel MOSFET which turns on the p-channel MOSFETs Q 5  and Q 6 . Transistors Q 5  and Q 6  are connected in parallel to allow increased current capability. Transistors Q 5  and Q 6  also separate the third section power from the load (missile squib)  300 . When the fourth section  328  (Section  4 ) is deactivated, transistor Q 8  turns on, which shuts off transistors Q 7 , Q 5 , and Q 6 . The fourth section  328  also contains diodes (CR 4 ) for reverse voltage protection and for the option of additional current summing of modules.  
         [0024]     With continued reference to  FIGS. 3 and 4 , the fifth section  330  (Section  5 ) includes signal conditioning  336  and low side switch circuitry  338  for the third input signal CONTROL_IN 3 . When activated, the signal out of the optocoupler U 2  deactivates transistors Q 11  and Q 12 , which turns on transistors Q 10  and Q 9 . Again, in one embodiment, transistors Q 10  and Q 9  are n-channel MOSFETs and are connected in parallel to allow increased current capability. Transistors Q 10  and Q 9  separate the load from ground  340 . When the fifth section  330  (Section  5 ) is deactivated, transistors Q 11  and Q 12  turn on, which shuts off transistors Q 10  and Q 9 .  
         [0025]     A sixth section  342  (Section  6 ) includes load current and load voltage telemetry monitoring circuitry  344 . The telemetry current out of a current sensor U 1 , in one embodiment equal to a load current divided by 10, is sent as a voltage to telemetry. The resulting telemetry load voltage is a buffered output of the load voltage. Light emitting diodes (LEDs) DS 1 -DS 8  are also utilized to indicate when the battery input and Sections  3 ,  4 , and  5  are activated.  
         [0026]     Embodiments of the present invention may provide significant advantages over prior art safe and arm devices. For example, embodiments of the present invention provide a safe and reliable solution as an acceptable safe and arm device on multiple missile configurations, meeting or exceeding isolation requirements for safely isolating the battery and squibs and ensures personnel safety during the handling of live missile boosters. Embodiments of the present invention also provide multiple fault tolerances. Furthermore, because embodiments of the present invention are capable of handling a wide voltage and current range, such embodiments are suitable for use in association with multiple missile and safety applications.  
         [0027]     While preferred and alternate embodiments of the invention have been illustrated and described, as noted above, many changes such as adding equivalent blocks ( FIG. 3 , sections  3 ,  4 , or  5 ), can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is not limited by the disclosure of these preferred and alternate embodiments. Instead, the invention should be determined entirely by reference to the claims that follow.