Abstract:
A moving picture decoding apparatus includes an input part which provides a picture tag to a bit stream which has been subjected to intraframe or interface encoding, the picture tag having a value monotonously changing on a picture base. A buffer memory stores the bit stream. A controller controls a number of pictures stored in the buffer memory by referring to the picture tag.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention generally relates to moving picture decoding, and more particularly to a moving picture decoding apparatus and method for decoding bit stream data of a moving picture encoded by intraframe encoding and interframe encoding.  
           [0003]    2. Description of the Prior Art  
           [0004]    The MPEG (Moving Picture Experts Group) standard is known as an international standard related to the image compression scheme, the disclosure of which is hereby incorporated by reference. The moving picture encoding/decoding technique consistent with the MPEG standard is one of the essential schemes in the recent multimedia environment. Now, a variety of moving picture encoding/decoding is developed.  
           [0005]    The encoding system based on the MPEG standard employs a variable-length code in which the number of bits forming data after encoding is not fixed but varied. That is, the amount of information per picture obtained after encoding is increased or decreased on the basis of the property of picture. With the above in mind, a decoder temporarily stores picture data in a built-in buffer memory after encoding (such picture data is referred to as bit stream) in order to start the decoding process when a given number of pictures (picture planes or sheets) is stored. If the buffer memory overflows or underflows, the decoder will not operate normally. In order to avoid the above problem, it is required to monitor the amount of data which is currently stored in the buffer memory and thus control the amount of the bit stream to be written to the buffer memory and the amount of bit stream to be read therefrom.  
           [0006]    The MPEG standard is silent in the method of controlling the buffer memory. Hence, various buffer memory control methods have been proposed.  
           [0007]    [0007]FIG. 1 is a block diagram of a conventional moving picture decoding apparatus, which is directed to monitoring, per picture, the amount of the bit stream occupying the buffer memory by using a temporary reference. A bit stream input part  12  is located at the front stage of a buffer memory  11 , and a video decoder  13  is provided at the rear stage thereof. The bit stream input part  12  includes a PSC (Picture Start Code) detector  16  and a TR (Temporary Reference) detector  17 . A controller  14  controls the bit stream input part  12  and the video decoder  13 . The controller  14  includes a picture counter  18 , which counts the number of pictures (picture planes).  
           [0008]    An operation of the apparatus shown in FIG. 1 will be given by referring to FIG. 2.  
           [0009]    First, at time t 0 , the controller  14  issues a bit stream request against the bit stream input part  12  in order to store, in the buffer memory  11 , data to be decoded, namely, a bit stream supplied from an external storage medium  15 . In response to receipt of the bit stream request, the bit stream input part  12  starts to read the bit stream from the external storage medium  15 . The bit stream input part  12  extracts a picture start code PSC and a temporary reference TR while reading the bit stream from the external storage medium  15 . The picture start code PSC indicates the beginning of the picture layer. According to the MPEG standard, the moving picture data has a hierarchal structure consisting of six layers. Besides the picture layer, the moving picture data has the block layer, macro block layer, slice layer a GOP (Group Of Picture) layer, and sequence layer. The temporary reference TR is a display sequence number assigned to each picture, and is reset at the beginning of the GOP.  
           [0010]    [0010]FIG. 3 is a diagram showing the concept of the GOP and the temporary reference TR. Each of the GOPs includes a plurality of pictures. For the sake of simplicity, FIG. 3 shows each GOP includes four pictures. The temporary reference TR is a serial number which is assigned to each GOP and starts from “0”. The MPEG standard defines an I picture (Intra picture), a P picture (Predictive picture) and a B picture (Bidirectionally predictive picture). Each picture is one of the I, P and B pictures. A GOP header is inserted at the beginning portion of each GOP, and includes a group start code.  
           [0011]    It will be noted that the structure shown in FIG. 3 is a frame structure (non-interlace). A field structure (interlace) is known in which one frame consists of an odd field and an even field to which fields an identical temporary reference is assigned.  
           [0012]    If the value of the temporary reference TR differs from that of the temporary reference assigned to the immediately prior picture, the bit stream input part  12  informs the controller  14  of detection of picture (time t 1 , shown in FIG. 2). Then, the bit stream input part  12  writes pictures into the buffer memory  11 .  
           [0013]    When the controller  14  is informed of the detection of picture, it counts up an internal picture counter  18  (time t 1 ). In the example shown in FIG. 2, the count value is changed from “0” to “1”. Subsequently, the controller  14  issues the bit stream request until the picture counter becomes equal to “2”.  
           [0014]    When the picture counter becomes equal to “2”, the controller  14  determines that data to be decoded is available in the buffer memory  11 , and stops issuing the bit stream request. Then, the controller  14  issues a decode start instruction (time t 2 ). The video decoder  13 , which is in the standby state, receives the decode start instruction, and starts decoding in synchronism with a vertical synchronizing signal VSYNC. At that time, the video decoder  13  sends a picture consumption notification to the controller  14 .  
           [0015]    In response to receipt of the picture consumption notification, the controller  14  counts down the picture counter  18 . In the example shown in FIG. 2, the count value is changed from “2” to “1”. When the picture counter  18  becomes equal to “1”, the controller  14  issues the bit stream request again (time t 3 ).  
           [0016]    The above sequence is repeatedly carried out during the decode process, the controller  14  issues the bit stream request against the bit stream input part  12  and issues the decode start instruction against the video decoder  13  so that the count value of the picture counter  18  is always “2”.  
           [0017]    The above sequence does not cause any problem in the normal decoding. However, a problem occurs in a decoding other than the normal decoding, such as a quick decoding.  
           [0018]    Let us consider a case where only I pictures are decoded in the quick decoding. The bit stream input part  12  discards the P and B pictures and picks up only the I pictures. The above selecting operation refers to the value of a PCT (Picture Code Type), which will be described later with reference to FIG. 5. The PCT indicates whether the encoded data is obtained by using the intraframe encoding or the interface encoding. The I picture (intraframe encoding) is indicated when PCT=1. The P and B pictures are respectively indicated when the PCT is equal to 2 and 3, respectively.  
           [0019]    If there is a bit stream in which a group includes only one I picture, the bit stream input part  12  cannot issue the picture detection notification. This is because the value of the temporary reference TR is reset by the I picture located at the beginning of the group and is always equal to “0”. Hence, the bit stream input part  12  does not detect a change of the value of the temporary reference TR. Hence, the bit stream input part  12  does not decode a picture to be decoded, and writes the corresponding bit stream into the buffer memory  11 . Hence, the quick decoding does not function.  
         SUMMARY OF THE INVENTION  
         [0020]    It is a general object of the present invention to provide a moving picture decoding apparatus and method in which the above disadvantages are eliminated.  
           [0021]    A more specific object of the present invention is to provide a moving picture decoding apparatus and method capable of quick-decoding any bit stream.  
           [0022]    The above objects of the present invention are achieved by a moving picture decoding apparatus comprising: an input part which provides a picture tag to a bit stream which has been subjected to intraframe or interface encoding, the picture tag having a value monotonously changing on a picture base; a buffer memory storing the bit stream; and a controller controlling a number of pictures stored in the buffer memory by referring to the picture tag.  
           [0023]    The above moving picture decoding apparatus may be configured so that the controller refers to the picture tag of a picture written into the buffer memory and the picture tag of a picture read therefrom.  
           [0024]    The moving picture decoding apparatus may be configured so that the controller controls the number of pictures on the basis of a difference between the picture tag of a picture written into the buffer memory and the picture tag of a picture read therefrom.  
           [0025]    The moving picture decoding apparatus may be configured so that the controller controls the number of pictures so that a difference between the picture tag of a picture written into the buffer memory and the picture tag of a picture read therefrom is equal to or less than a threshold value.  
           [0026]    The moving picture decoding apparatus may be configured so that the controller requests the input part to output the bit stream when the difference is less than the threshold value.  
           [0027]    The moving picture decoding apparatus may be configured so that the controller allows a read operation of the buffer memory when the difference is equal to the threshold value.  
           [0028]    The moving picture decoding apparatus may be configured so that the picture tag has a value which monotonously increases on the picture base.  
           [0029]    The moving picture decoding apparatus may be configured so that the input part inserts the picture tag into the bit stream.  
           [0030]    The moving picture decoding apparatus may be configured so that the input part overwrites the picture tag onto a given field of the bit stream.  
           [0031]    The moving picture decoding apparatus may be configured so that the given field of the bit stream corresponds to a temporary reference in the MPEG standard.  
           [0032]    The moving picture decoding apparatus may further comprise a video decoder which decodes the bit stream read from the buffer memory.  
           [0033]    The moving picture decoding apparatus may be configured so that the bit stream is consistent with the MPEG standard.  
           [0034]    The moving picture decoding apparatus may be configured so that: the bit stream is consistent with the MPEG standard which defines a temporary reference; and the picture tag has a value only when a value of the temporary reference changes.  
           [0035]    The above objects of the present invention are also achieved by a moving picture decoding method comprising the steps of: (a) providing a picture tag to a bit stream which has been subjected to intraframe or interface encoding, the picture tag having a value monotonously changing on a picture base; (b) storing the bit stream in a buffer memory; and (c) a number of pictures stored in the buffer memory by referring to the picture tag.  
           [0036]    The moving picture decoding method may be configured so that the step (c) comprises the step of referring to the picture tag of a picture written into the buffer memory and the picture tag of a picture read therefrom. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0037]    Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:  
         [0038]    [0038]FIG. 1 is a block diagram of a conventional moving picture decoding apparatus;  
         [0039]    [0039]FIG. 2 is a timing chart of the operation of the apparatus shown in FIG. 1;  
         [0040]    [0040]FIG. 3 is a diagram explaining the GOP (Group of Picture) and TR (Temporary Reference);  
         [0041]    [0041]FIG. 4 is a diagram showing the principle of the present invention;  
         [0042]    [0042]FIGS. 5A, 5B and  5 C are diagrams for explaining a picture tag TAG newly introduced in the present invention;  
         [0043]    [0043]FIG. 6 is a block diagram of a moving picture decoding apparatus according to an embodiment of the present invention;  
         [0044]    [0044]FIG. 7 is a timing chart of an operation of the moving picture decoding apparatus shown in FIG. 6;  
         [0045]    [0045]FIG. 8 is a block diagram of a structure of a bit stream input part shown in FIG. 6;  
         [0046]    [0046]FIG. 9 is a block diagram of a structure off a word aligning part shown in FIG. 8;  
         [0047]    [0047]FIG. 10 is a timing chart of a normal operation of the word aligning part shown in FIG. 9;  
         [0048]    [0048]FIG. 11 is a timing chart of another operation of the word aligning part in which the picture tag TAG is added;  
         [0049]    [0049]FIG. 12 is a flowchart of an operation of a controller shown in FIG. 8; and  
         [0050]    [0050]FIG. 13 is a block diagram of a video decoder shown in FIG. 8. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0051]    First, a description will be given of the principle of the present invention.  
         [0052]    As has been described previously, the prior art refers to a change of the value of the temporary reference. Hence, no change of the value of the temporary reference is detected when only I picture is extracted from each group which consists of only the I picture. According to the present invention, a number other than the temporary reference TR is used. For example, a picture serial number other than the temporary reference TR is assigned to the bit stream.  
         [0053]    The picture serial number introduced in the present invention is not reset by the beginning picture of each GOP but increases monotonously. In a frame structure shown in FIG. 4, the above picture serial number is depicted as a picture tag TAG. The picture tag TAG is not reset periodically but is designed to serially count the number of pictures over the GOPs. In FIG. 4, the value of the picture tag TAG monotonously increases one by one starting from “1”.  
         [0054]    As has been described, in the field structure, the identical value of the temporary reference TR is assigned to the two fields (first (odd) and second (even) fields). In this case, the identical value of the picture tag TAG is assigned to the two fields. The value of the picture tag TAG is changed only when the value of the temporary reference TR is changed.  
         [0055]    More particularly, the picture tag TAG consisting of a given number of bytes is inserted immediately after the picture start code PSC by the bit stream input part  12  shown in FIG. 1. Then, the bit stream is written into the buffer memory  11 . The above procedure will be described with reference to FIGS. 5A, 5B and  5 C.  
         [0056]    [0056]FIG. 5A shows a format of the bit stream consistent with the MPEG standard. FIG. 5C shows a bit stream in which the picture tag TAG consisting of the given number of bytes is inserted immediately after the picture start code PSC. The bit stream input part  12  and the other parts following the part  12  manages the number of pictures by using the picture tag TAG. Hence, it is no longer necessary to consider the periodical resetting of the temporary reference TR in order to manage the number of pictures. A symbol SLICE shown in FIGS. 5A, 5B and  5 C denotes slice-layer data.  
         [0057]    The picture tag TAG may have the value which decreases monotonously. It is also possible to replace the temporary reference TR by the picture tag TAG by overwriting the picture tag TAG onto the temporary reference TR.  
         [0058]    [0058]FIG. 6 is a block diagram of a moving picture decoding apparatus according to an embodiment of the present invention, in which parts that are the same as those shown in FIG. 1 are given the same reference numbers. The apparatus shown in FIG. 6 differs from that shown in FIG. 1 in the following.  
         [0059]    First, a bit stream part  22  shown in FIG. 6 is substituted for the bit stream part  12  shown in FIG. 1, and includes a picture tag adding part  32 , which is replaced by the TR detecting part  17 . Second, a controller  24  shown in FIG. 6 is substituted for the controller  14  shown in FIG. 1, and includes a picture tag monitor  32 , which is replaced by the picture counter  18 . Third, the bit stream part  22  outputs a stored picture tag TAG1 to the controller  24 . Fourth, the video decoder  13  outputs a consumed picture tag TAG2 to the controller  24 .  
         [0060]    The stored picture tag TAG1 and the consumed picture tag TAG2 are based on the picture tag TAG, which has an initial value of “0”, and monotonously increases “1”, “2”, “3”, . . . In the present embodiment of the invention, the picture tag TAG is inserted immediately after the picture start code PSC as shown in FIG. 5C and is composed of four bytes. The picture tag TAG is used to count the number of pictures.  
         [0061]    A description will now be given, with reference to FIGS. 7 and 12, of an operation of the moving picture decoding apparatus shown in FIG. 6. FIG. 12 is a timing chart of the operation of the moving picture decoding apparatus, and FIG. 12 is a flowchart of a control sequence executed when the controller  24  is formed of a microcomputer, microprocessor or the like.  
         [0062]    At step ST 1  shown in FIG. 12, the controller  24  issues the bit stream request against the bit stream input part  22  in order to store moving picture data to be stored in the buffer memory  11  (time t 0 , TAG1=0, TAG2=0). The bit stream input part  22  receives the bit stream request, and starts to read the bit stream from the external storage medium  15 .  
         [0063]    The PSC detector  16  of the bit stream input part  22  extracts the picture start code PSC from the read bit stream. In the above extracting procedure, the bit stream input part  22  adds the picture tag TAG of four bits to the bit stream so that it follows the picture start code PSC. Simultaneously, the bit stream input part  22  informs the controller  24  of the value of the picture tag TAG as the stored picture tag TAG1 (step ST 2 ). In this case, the picture first received after the picture tag TAG is initialized is assigned the stored picture tag TAG1 of “1” (time t 1 , TAG1=1, TAG2=0).  
         [0064]    The picture tag monitor  32  of the controller  24  monitors the difference delta-TAG between TAG1 and TAG2 at step ST 3 . The controller  24  repeatedly issues the bit stream request until the difference delta-TAG becomes equal to “2” (the process returns to step ST 1  when the answer of step ST 4  is YES), which is a threshold value for defining the number of pictures stored in the buffer memory  11 . When it is determined that the difference delta-TAG becomes equal to “2”, the controller  24  determines that moving picture data to be decoded is now available in the buffer memory  11 , and stops issuing the bit stream request. Instead, the controller  24  issues the decode start instruction against the video decoder  13  at step ST 5 . Hence, it is allowed to read the bit stream from the buffer memory  11 .  
         [0065]    The video decoder  13  receives the decode start instruction and starts, in synchronism with the vertical synchronizing signal VSYNC, to decode the bit stream read from the buffer memory  11 . At that time, the video decoder  13  outputs the consumed picture tag TAG2 to the controller  24 . In this case, the consumed picture tag TAG2 is equal to “1” (time t 2 , TAG1=2, TAG2=1). Since the delta-TAG reduced to “1”, the controller  24  issues the bit stream request again. The consumed picture tag TAG2 corresponds to the picture tag TAG of the picture from the buffer memory  11 .  
         [0066]    The above sequence is repeatedly carried out so that the delta-TAG is always equal to “2” during the decoding operation. That is, the controller  24  repeatedly issues the bit stream request and the decode start instruction against the bit stream input part  22  and the video decoder  13 , respectively.  
         [0067]    [0067]FIG. 8 is a block diagram of the bit stream input part  22 , which converts the bit stream data of eight bits into data of 32 bits. The 8bits-to-32bits conversion is called a word alignment, and the word-aligned bit stream is called word aligned data. That is, four pieces of data each having one byte (eight bits) are converted into one word (32 bits). The bit stream input part  22  has a word aligning part  35  following the PSC detector  16 . The word aligning part  35  adds the picture tag TAG due to the function of a built-in tag adding part  31  while performing the above word aligning conversion.  
         [0068]    [0068]FIG. 9 is a block diagram of the word aligning part  35 , which includes a shift register  47 , a word data register  48 , a counter  49  and a selector  50 . The shift register  35  is located at the input stage of the word aligning part  35 , and has four D-type flip-flops, each having an eight-bit structure. In other words, the shift register  47  is made up of  32  one-bit D-type flip-flop. The word data register  48  is located at the output stage of the word aligning part  35  and stores word aligned data. The counter  49  and the selector  50  are located between the shift register  47  and the word data register  48 . The counter  49  functions to generate the picture tag TAG. The selector  50  receives the output signals Q 0 -Q 3  of the respective stages FF0-FF3 of the shift register  47  and the output signal of the counter  49 , and selects one signal from among the received signals. Further, the word aligning part  35  includes a timing generator  54 , which generates a latch pulse  52  and a select pulse  53  on the basis of a shift pulse  51  from the PSC detector  16  and a PSC detection notification  34 .  
         [0069]    The shift pulse  51  is applied to enable terminals of the respective stages FF0-FF3 of the shift register  47 , and shifts eight-bit data applied to data terminals D thereof. The latch pulse  52  defines the timing at which word data is latched in the word data register  48 . The select pulse  53  is used to switch the data selection of the selector  50 . When the select pulse  53  is at a low level, the selector  50  selects the output signals of the shift register  47 . When the select pulse  53  is at a high level, the selector  50  selects the output signal of the TAG counter  49 .  
         [0070]    [0070]FIG. 10 is a timing chart of a normal operation of the word aligning part  35  in which the picture tag TAG is not added. The PSC detector  16  detects the picture start code PSC, and generates the PSC detection notification  34 . Byte data (part of the PSC) located next to the picture start code PSC is applied to the first stage FF0 of the shift register  47 . When the shift pulse  51  is applied four times (four shift pulses), all the stages FF0-FF3 of the shift register  47  have latched data. When the timing generator  54  counts the shift pulse  51  four times (four shift pulses), it generates the latch pulse  52 , which is applied to the enable terminal EN of the word data register  48  via an OR gate  55 . The word data register  48  stores four pieces of eight-bit data d 0 , d 1 , d 2  and d 3  at time t 0 . The first four pieces of eight-bit data d 0 , d 1 , d 2  and d 3  corresponds to the picture start code PSC. At time t 0 , the select pulse  53  is maintained at the low level, so that the output signals of the shift register  47  are always selected. At time t 1 , when the shift pulse  51  is applied to the shift register  47  four times, the timing generator  54  generates the latch pulse  52 , and 32-bit data consisting of pieces of data d 4 -d 7  is stored in the word data register  48 .  
         [0071]    The above operation is repeatedly carried out, and thus 32-bit word data can be produced from four pieces of byte data.  
         [0072]    [0072]FIG. 11 is a timing chart of an operation of the word aligning part  35  in which the picture tag TAG is added. The state observed at time t 0  shown in FIG. 11 is the same as that shown in FIG. 10. At time t 0.5  when the shift pulse  51  is applied twice after the picture start code PSC is detected, the timing generator  54  sets the select pulse  53  to the high level, so that the selector  50  selects the output signal of the TAG counter  49 . The TAG counter  49  increments the value of the picture tag TAG by 1 each time the select pulse  53  is received.  
         [0073]    The select pulse  53  and the latch pulse  52  are connected to the OR gate  55 . Hence, even when the select pulse  53  is switched to the high level while the latch pulse  52  is low, the high-level signal is applied to the enable terminal EN of the register  48 , the word data register  48  is activated. Hence, at time 0.5 , the word data register  48  stores the picture tag TAG selected by the selector  50 . Then, when the timing generator  54  further receives the shift pulse  51  twice, it generates the latch pulse  52 . Hence, as shown in FIG. 5C, the picture tag TAG is added between the picture start code PSC and the temporary reference TR.  
         [0074]    By newly defining the picture tag TAG which monotonously changes (increases or decreases) assigned to each picture of the bit stream, the adjacent pictures to be written into the buffer memory  11  are assigned different values of the picture tag TAG. Hence, even if only I pictures are used to reproduce the original picture, the I pictures can certainly be written into the buffer memory  11 . The I pictures can be selected by the bit stream input part  22 , which refers to the picture code type PCT. In the prior art, even if the I picture is selected, it is not written into the buffer memory  11  until the value of the temporary reference TR changes. In contract, the present invention refers to the newly defined picture tag TAG, and does not have the problem of the prior art.  
         [0075]    [0075]FIG. 13 is a block diagram of a structure of the aforementioned video decoder  13 . As shown in FIG. 13, the video decoder  13  is made up of a series decoder  61 , an adder  62 , an information source decoder  63 , a frame memory  64 , a postprocessing part  65  and a controller  66 . When the controller  66  receives the decoder start instruction from the controller  24 , it supplies the series decoder  61  with a signal which starts the series decoder  61  to operate, and sends the consumed picture tag TAG2 to the controller  24 . The series decoder  61  decodes the moving picture data encoded by the variable-length encoding (entropy encoding) to thereby reproduce an equal length code, which is applied to the adder  62 . The adder  62  adds the equal-length code indicative of the difference between the frames to the frame data read from the frame memory  64 , and outputs the added result to the information source decoder  63 . Then, the information source decoder  63  performs an inverse DCT (Discrete Cosine Transform) process and a dequantization process, so that data compressed in the time axis can be expanded. The data thus obtained is output to the postprocessing part  65  and the frame memory  64 . The postprocessing part  65  performs a conventional postprocessing so that data arranged in the block formation is converted into serial data which produces the original picture.  
         [0076]    The above-mentioned embodiment of the present invention employs the arrangement shown in FIG. 5C. Alternatively, it is possible to employ the arrangement shown in FIG. 5B in which the picture tag TAG is overwritten onto the temporary reference TR, which is thus lost. The structure of the bit stream input part  22  to be used when the arrangement shown in FIG. 5B is employed is the same as shown in FIGS. 8 and 9. However, it is required that the timing generator  54  operates in a different manner. When the arrangement shown in FIG. 5B is employed, the timing generator  54  generates the select pulse  53  when receiving the shift pulse  51  eight times (eight shift pulses). Hence, the picture tag TAG is written into the word data register  48  rather than the pieces of data d 4 -d 7  (which correspond to the temporary reference TR).  
         [0077]    The threshold value defining the number of pictures stored in the buffer memory  11  is not limited to 2 but may be set equal to an arbitrary number.  
         [0078]    The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention.