Abstract:
Timing difference division circuit with a high operating speed and a small area, assuring broadband operation. The circuit includes a logic circuit L 1  generating a first gate signal and a second gate signal based on a first input signal and a second input signal, a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal, a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source. The first and second series circuits are connected in parallel across the inner node and the second power source. The first and second gate signals are connected to control terminals of the second and third switches, respectively. The circuit also includes a plurality of MOS capacitors, connection of which to the inner node is separately controlled by a control signal, and a buffer circuit an input end of which is connected to the inner node and the value of an output signal of which is determined based on the relative magnitude of the potential of the inner node and a threshold voltage. An overlap period during which the first and second gate signals output from the logic circuit are both activated to turn on the second and third switch elements is set to an optional value.

Description:
FIELD OF THE INVENTION 
     This invention relates to a signal controlling method and apparatus. 
     BACKGROUND OF THE INVENTION 
     A conventional signal dividing method for dividing (internally dividing or interpolating) a timing difference is used for multiplying the frequency of clock signals, as disclosed in Publication 1 (Japanese patent application 09-157028 (JP Patent Kokai JP-A-11-4145)). 
     In e.g., Publication 2 (ISSCC Digest of Technical Papers pp.216 to 217, February 1996, U.S. Pat. Nos. 5,442,835 and 5,530,837), there is disclosed a clock signal frequency multiplying circuit, as shown herein in FIG.  24 . 
     Referring to FIG. 24, the clock signal frequency multiplying circuit is made up of four sets of delay circuits  301  to  304 , a phase comparator  309  and a counter  310 , in case of 4× frequency multiplying. 
     Each of the first to fourth delay circuits  301  to  304  has its output terminals selected by first to fourth switchers  305  to  308 , with the first to fourth delay circuits  301  to  304  being connected in series with one another. 
     A first clock  311 , input from outside to the first delay circuit  301 , is compared in the phase comparator  309  with a fifth clock  315  passed through the first to fourth delay circuits  301  to  304 . An UP signal  316  or a DOWN signal  317  is transferred to the counter  310 , based on the results of comparison, and a control signal  318  is output from the counter  310  to the first to fourth switchers  305  to  308  to make adjustment so that the first clock  311  will be of the same phase (in-phase) to the fifth clock  315 . 
     Since the four delay circuits  301  to  304  are adjusted equally in delay time, the delay time is equal, with the timing difference of the first to fourth clocks  311  to  314  being equal to one another at one-fourth of the clock period tCK. 
     Thus, by synthesising the first to fourth clocks  311  to  314 , 4× clocks are produced. 
     As a circuit for multiplying the frequency of clock signals, a phase locked loop (PLL) is used. In the PLL, shown in FIG. 25, an output of a voltage-controlled oscillator VCO  322  is frequency-divided by a frequency divider  323 , and the resulting signal is compared by a phase comparator  319  to an external clock  324 . The result of comparison is input as an UP signal  325  or a DOWN signal  326  via a charging pump  320  and a loop filter  321  to the VCO 322  to control the VCO  322  so that clocks obtained on frequency-dividing the output of the VCO  322  will be of a frequency equal to a frequency of the external clock  324 . This causes the VCO  322  to output frequency-multiplied clocks  327  with the number of times of multiplying equal to a reciprocal of the number of times of frequency division. 
     However, the circuit shown in FIG. 24 is such a circuit comparing a signal which has traversed the series-connected delay circuits to external clocks approximately several tens of times to correct the delay difference and the phase difference progressively as comparison proceeds. 
     On the other hand, the PLL circuit, shown in FIG. 25, has a drawback that it is insufficient in operating speed, since clocks obtained on frequency division of the output of the VCO  322  will be of a frequency equal to the frequency of the external clock  324 , such that a time interval not less than several tens of clock periods must elapse until the clocks multiplied in frequency are obtained. 
     The circuits shown in FIGS. 24 and 25 basically can be used only for clock control, while it cannot be used as a delay circuit for varying the degree of signal delay. 
     With a view to solving these drawbacks and to realizing a method and apparatus for controlling the clock signals also usable as a variable delay circuit, the present inventors have proposed the following circuit configuration in the JP-A-11-4145. The clock control circuit, described in JP-A-11-4145, is now explained by referring to the drawings, the entire disclosure of which is herein incorporated by reference thereto. 
     FIG. 4 shows the configuration of the JP-A-11-4145. The circuit shown in FIG. 4 multiplies the frequency of external clocks. Specifically, the circuit shown in FIG. 4 frequency divides external clocks  1  into multi-phase clocks  3  and divides the input timing difference of different phase pulse edges of the multi-phase clocks  3  or multiplexes the clocks  9   c  of different phases resulting from the division to multiply the phases of the external clock  1 . The circuit shown in FIG. 4 includes a frequency divider  2 , a multi-phase clock frequency multiplying circuit  5  and a clock synthesis circuit  8 . The frequency divider  2  divides the frequency of the external clock  1  to the multi-phase clocks  3 . A multi-phase clock multiplying circuit  5  includes a timing difference dividing circuit  4   a  for dividing pulses of different phases of different phase clocks of the multi-phase clocks  3 , timing difference dividing circuits  4   a  for dividing the pulses of the same phase by n and a multiplying circuit  4   b  for multiplying different phase pulses resulting from division by n, and outputs multi-phase clocks  9   a.    
     The clock synthesis circuit  8  synthesises the multi-phase clocks  9   a , output from the multiplying circuit  4   b , to generate single-phase clocks  9 . The timing difference dividing circuits  4   a  are connected in parallel with one another. 
     The external clocks  1  are frequency divided by the frequency divider  2  into the multi-phase clocks  3 , and the input timing difference of different phase pulse edges of the frequency divided multi-phase clocks  3  is divided by a timing difference dividing circuit  4   a . The resulting clocks  9   c  of different phases, obtained on frequency division, are multiplexed to multiply the external clock  1 , to multiply the phases of the multi-phase clocks. 
     FIG. 5 shows an illustrative structure of a two-phase clock multiplying circuit as the multi-phase clock frequency multiplying circuit  5 . The two-phase clock multiplying circuit divides the frequency of the external clocks  105  by two to output two-phase clocks having the double (2×) frequency. 
     In FIG. 5, a frequency divider  101  divides the frequency of the external clocks  105  by two to generate two-phase clocks D 1 , D 2 . Plural two-phase clock multiplying circuits  102   1  to  102   n  divide the input timing difference of different phase pulse edges of the frequency divided multi-phase clocks D 1 , D 2  ( 3  of FIG.  4 ), the first stage two-phase clock multiplying circuit  102   1  generates two-phase clock signals D 11 , D 12  obtained on frequency doubling the two-phase clocks D 1 , D 2  from the frequency divider  101 . In similar manner, the two-phase clock multiplying circuits  102   1 ,  102   3  to  102   n−1  each doubles the frequency of the clocks D 21 , D 22  of the previous stage so that two-phase clocks Dn 1 , Dn 2  obtained on 2nX-multiplying the external clocks  105  are obtained by the two phase clock multiplying circuit  102   n  of the last stage. 
     A clock synthesis circuit  103  synthesises 2nX-multiplied two-phase clocks Dn 1 , Dn 2  output from the last stage two phase clock multiplying circuit  102   n  to output multiplied clocks  107 . 
     A period detection circuit  104  ( 6  of FIG. 4) is fed as an input with the external clocks  105  to output a control signal  106  ( 7  of FIG. 4) to each two-phase clock multiplying circuits  102   1  to  102   n . The control signal  106  corrects the clock period dependency of the timing difference dividing circuit contained in each two-phase clock multiplying circuits  102   1  to  102   n  for load adjustment. 
     The period detection circuit  104  is made up of a ring oscillator of a fixed number of stages and counters and counts the number of oscillations of the ring oscillators during the period of the external clocks  105  to output a control signal  105  depending on the number of counts. 
     The two-phase clock multiplying circuits  102   1  to  102   n  are freed of fluctuations in characteristics by the control signal  106  from the period detection circuit  104 . 
     The circuit shown in FIG. 5 divides the frequency of the external clocks  105  by a ½ frequency divider  101  and doubles the frequency of the clocks D 1 , D 2  by the initial state two-phase clock multiplying circuit  102   1  to generate two-phase clocks D 11 , D 12 . The similar process is repeatedly carried out in the two-phase clock multiplying circuits  102   2  to  102   n  until 2nX two-phase clocks Dn 1 , Dn 2  are ultimately obtained from the last stage two-phase clock multiplying circuits  102   n . 
     These clocks Dn 1 , Dn 2  are synthesised by the clock synthesis circuit  103  to produce multiplied clocks  107 . 
     In the embodiment shown in FIG. 6, in which n=4, the multiplied clocks  107  are of the same clock period as that of the external clocks  105  and are obtained as signals 2nX (8X) from the external clocks  105 . Meanwhile, n=4 is merely illustrative such that n may be set to any suitable integer. 
     FIG. 7 shows a structure of the two-phase clock multiplying circuit  5 . Since the two-phase clock multiplying circuits  102   1  to  102   n  are of the same structure, the following explanation is directed to the last stage two-phase clock multiplying circuits  102   n . The structure of the two-phase clock multiplying circuits  102   n  is designed for the setting of n=4. 
     The two-phase clock multiplying circuit  102   n  includes parallel-connected first to fourth timing difference dividing circuits  108  to  111  and first and second multiplexing circuits  112 ,  113 . Two phase clocks D (n−1)  1 , D (n−1)  2  are input to two input ends of the first to fourth timing difference dividing circuits  108  to  111 . The control signal  106  and four phase clocks P 1  to P 4  from the timing difference dividing circuits  108  to  111  in the complementary configuration are fed back to the input side. 
     The first and second multiplexing circuits  112 ,  113  are fed with and multiplex two-phase clocks P 1 , P 3  and P 2 , P 4  from the first to fourth timing difference dividing circuits  108  to  111  to generate two-phase clocks Dn 1 , Dn 2 . 
     The operation of the two-phase clock multiplying circuit, shown in FIG. 7, is explained with reference to FIG.  8 . 
     The two-phase clock multiplying circuit  102   n  is fed with two-phase clocks D (n−1)  1  and D (n−1)  2  from the previous stage and with the control signal  106  from the period detection circuit  104  to output frequency doubled two-phase clocks Dn 1 , Dn 2 . 
     In the two-phase clock multiplying circuit  102   n , the two-phase clocks D (n−1)  1  and D (n−1)  2  and the control signal  106  are input to the totality of the four timing difference dividing circuits  108  to  111 . The clocks P 1  to P 4  are output from the four timing difference dividing circuits  108  to  111  so as to be fed back as inputs to the associated timing difference dividing circuits  108  to  111 . 
     Referring to FIG. 8, the rising of the clock P 1  is determined by the delay corresponding to the inner time delay of the timing difference dividing circuit  108  as from the rising of the clock D (n−1)  1 . 
     The rising of the clock P 2  is determined by the division of the timing difference between the rising of the clock D (n−1)  1  and that of the two-phase clock D (n−1)  2  and the delay corresponding to the internal delay. 
     The rising of the clock P 3  is determined by the delay corresponding to the internal delay as from the clock D (n−1)  2 . The rising of the clock P 4  is determined by the division of the timing difference between the rising of the clock D (n−1)  2  and that of the clock D (n−1)  1  and the delay corresponding to the internal delay as from the clock D (n−1)  2 . 
     The clock P 2  controls the decay (falling) of the clock P 1  input to the timing difference dividing circuit  108 . The clock P 3  controls the decay of the clock P 2  input to the timing difference dividing circuit  109 . The clock P 4  controls the decay of the clock P 3  input to the timing difference dividing circuit  110 . The clock P 1  controls the decay of the clock P 4  input to the timing difference dividing circuit  111 . 
     So, the periods of the clocks P 1  to P 4  are equal to those of the clocks D (n−1)  1  and D (n−1)  2  such that the clocks P 1  to P 4  become substantially four-phase signals with a 25% duty. 
     Moreover, the clocks P 1 , P 3  are input to and multiplexed by the multiplexing circuit  112  so as to be output as a clock signal Dn 1 . 
     The clocks P 2 , P 4  are input to and multiplexed by the multiplexing circuit  113  so as to be output as a clock signal Dn 2 . 
     The clocks Dn 1 , Dn 2  are two-phase clocks with subsequently 50% duty, with the periods thereof being one-half those of the clocks D (n−1)  1  and D (n−1)  2 . 
     Referring to FIGS. 9 to  12 , typical structures of the timing difference dividing circuits  108  to  111 , shown in FIG. 7, are explained. In FIGS. 9 to  12 , MP 11 , MP 21 , MP 31  and MP 41  are P-channel MOS transistors, MN 11  to MN 19 , MN 21  to MN 29 , MN 31  to MN 39  and MN 41  to MN 49  are N-channel MOS transistors, while CAP 11  to CAP  13 , CAP 21  to CAP 23 , CAP 31  to CAP 33  and CAP 41  to CAP 43  are capacitance devices. 
     The timing difference dividing circuits  108  to  111  are of the identical device structure. That is, each of the difference dividing circuits  108  to  111  is made up of a two-input NAND  10 , an inverter  11 , a sole P-channel MOS transistor MP 11  etc., three sets each of two-series connected N-channel MOS transistors, three sets each of a series-connected N-channel MOS transistor and a capacitance device. The three NAND transistors are all of an identical gate width, with the gate width of the three sets of NMOS transistors and the capacitance of the capacitance device being of a size ratio of 1:2:4. 
     The difference dividing circuits  108  to  111 , shown in FIGS. 9 and 11, are similar in structure, with the difference being the connection of inputs D (n−1)  1  and D (n−2)  2  and the connection of the input P 2  (P 4 ). 
     Referring to FIG. 9, the timing difference division circuit  108  includes a NAND circuit NAND 11 , having a signal D (n−1)  2  and a signal P 2  as inputs, a P-channel MOS transistor MP 11  having a source, a gate and a drain connected to a power source VCC, to an output end (node  11 ) of the NAND 11  and to an internal node N 12 , respectively, N-channel MOS transistors MN 12 , MN 13  each having a drain and a gate connected to the inner node N 12  and to a signal D (n−1)  1 , respectively, a N-channel MOS transistor MN 11  having a gate connected to ground potential, and N-channel MOS transistors MN 14 , MN 15  and MN 16 , having sources commonly connected to the ground potential GND and gates commonly connected to an output end of NAD  11 . The inner node N 12  is connected to an input end of an inverter INV 11  to output a signal P 1  at an output terminal of the inverter INV 11 . The inner node N 12  is provided with N-channel MOS transistors MN 17 , MN 18  and MN 19 , having drains commonly connected and having gates connected to a control signal  106 , and with capacitances CAP 11 , CAP 12  and CAP 13 , having one end connected to a source of N-channel MOS transistors MN 17 , MN 18  and MN 19  and having the other ends commonly connected to the ground potential. 
     Referring to FIG. 10, a timing differential circuit  109  include a NAND circuit NAND  21 , fed with a signal D (n−1)  2  and with a signal P 3  as inputs, a P-channel MOS transistor MP 21 , having a source, a gate and a drain connected to the power source VCC, to an output end (node N 21 ) of the NAND 21  and to the inner node N 22 , respectively, an N-channel MOS transistor MN 21  having a drain and a gate connected to the inner node N 22  and to the signal D (n−1)  1 , respectively, N-channel MOS transistors MN 22  and MN 23 , having drains and gates connected commonly to the inner node N 22  and to the signal D(n−1) 2 , respectively, and N-channel MOS transistors MN 24 , MN 25  and MN 26  having sources commonly connected to the ground potential GND and gates commonly connected to an output end (node N 21 ) of the NAND 21 . The inner node N 22  is connected to the input end of the inverter INV 21  to output a signal P 3  at an output end of the inverter INV 21 . The inner node N 22  includes N-channel MOS transistors MN 27 , MN 28  and MN 29  having drains commonly connected and having gates connected to a control signal  106 , and capacitances CAP 21 , CAP 22  and CAP 23  having one ends connected to sources of N-channel MOS transistors MN 27 , Mn 28  and MN 29  and having the other ends commonly connected to the ground potential. 
     Referring to FIG. 11, a timing difference division circuit  110  includes a NAND circuit NAND 31 , fed with the signal D (n−1)  1  and with a signal P 4 , as input, a P-channel MOS transistor MP 31  having a source, a gate and a drain connected to the power source VCC, to an output end of the NAND 31  and to an inner node N 32 , respectively, N-channel transistors MN 32 , MN 33 , having drains commonly connected to the inner node N 32  and having gates commonly connected to the signal D (n−1)  2 , a N-channel MOS transistor MN 31  having a gate connected to the ground potential, and N-channel MOS transistors Mn 34 , MN 35  and MN 36  having sources commonly connected to the ground potential GND and having gates commonly connected to the output end of the NAND 31 . The inner node N 32  is connected to the input end of the inverter INV 31  and outputs a signal P 3  at an output end of the inverter INV 31 . The inner node N 32  includes N-channel MOS transistors MN 37 , MN 38  and MN 39  having drains commonly connected and having gates connected to control signals, and capacitances CAP 31 , CAP 32  and CAP 33  having one ends to sources of N-channel MOS transistors MN 37 , MN 38  and Mn 39  and having the other ends commonly connected to the ground potential. 
     Referring to FIG. 12, a timing difference division circuit  111  includes a NAND circuit NAND 41 , fed with the signal D (n−1)  1  and with the signal P 1 , a P-channel MOS transistor MP 41  having a source, a drain and a gate connected to the power source VCC, to an output end (node N 41 ) of the NAND 41  and to an inner node N 42 , respectively, an N-channel MOS transistor MN 41  having a drain and a gate connected to the internal node N 42  and to the signal D (n−1)  2 , N-channel MOS transistors MN 42 , MN 43  having drains and gates commonly connected to the inner node N 42  and connected to the signal D(n−1) 1 , respectively, and N-channel MOS transistors MN 44 , MN 45  and MN 46  having sources and gates commonly connected to the ground potential GND and commonly connected to an output end of the NAND 41 , respectively. The inner node N 41  is connected to an input end of the inverter INV 41  and outputs a signal P 4  at an output end of the inverter INV 41 . The inner node N 42  includes N-channel MOS transistors MN 47 , MN 48  and MN 49 , having drains commonly connected and also having gates connected to a control signal, and capacitances CAP 41 , CAP 42  and CAP 43 , having one ends connected to the sources of the N-channel MOS transistors MN 47 , MN 48  and MN 49  and having the other ends commonly connected to the ground potential. 
     The operation of the timing difference division circuits  108  to  111  is explained by referring to the timing waveform diagram of FIG.  13 . The timing difference division circuits  108 ,  110 , shown in FIGS. 9 and 11, are of the same circuit configuration except input/output signal, while the timing difference division circuits  109 ,  111  shown in FIGS. 10 and 12 are of the same circuit configuration except the input/output signals. So, the operation of the timing difference division circuits  108 ,  109 , shown in FIGS. 9 and 10 are hereinafter explained. 
     As for the inner operation of the timing difference division circuit  108 , shown in FIG. 9, one period is from t 1  until t 3  in FIG.  13 . So, the inner node waveform for this one period duration is shown. 
     First, the rise timing of the clocks P 1  is explained. 
     By a rising edge of a clock D (n−1)  1 , electrical charges at the node N 12  are extracted to the N-channel MOS transistors MN 12 , MN 13 . When the potential of the node N 12  has reached a threshold value of the inverter INV 11 , there rises an edge of the clock P 1 , output from the inverter INV 11 . 
     If the electrical charges of the internal node N 12  that need to be extracted until reaching the threshold value of the inverter INV 11  are denoted CV and charge-extracting current values of the N-channel MOS transistors MN 12  and MN 13  are denoted I, the result of extraction of the electrical charges of CV from the clock D (n−1)  1  with the current of 2I, that is CV/2I, represents the timing as from the rising edge of the clock D (n−1)  1  until rising of the clock P 1 . 
     The decay of clocks P 1  is by the output of the two-input NAND  11  going low to turn ON the P-channel MOS transistor MP 11  to charge the inner node N 12  to a high level. The two-input NAND  11  is fed with a clock D (n−1)  2  and a clock P 2 , with the output going low when both the clock D (n−1)  2  and the clock P 2  are high. The period during which the clock P 2  is high is comprised within a period during which the clock D (n−1)  2  is high, so that the output clock is of a pattern corresponding to a pattern of the inverted clock P 2 . However, during the time an initial value of the clock P 2  is not fixed with the power being turned on, a logical value is taken of the clock P 2  and the clock D (n−1)  2 . 
     As for the operation of the timing difference division circuit  109 , shown in FIG. 10, there is shown the internal node waveform during the time period as from t 1  until t 3  in FIG. 13, because this time period corresponds to one period. 
     The rise timing of the clock P 2  is explained. During the time period tCKn as from the rising edge of the clock D (n−1)  1 , the electrical charges of the node N 22  are extracted by the N-channel MOS transistor MN 21 . After time tCKn, the residual electrical charges at the node N 22  are extracted from the rising edge of the clock D (n−1)  2  by the N-channel MOS transistors MN 22 , MN 23 . When the potential of the node N 22  reaches the threshold value of the inverter INV 21 , the edge of the clock P 2  rises. If the electrical charges of the node N 22  are denoted CV, and the charge extracting current values of the N-channel MOS transistors MN 22 , MN 23  are denoted I, the result of extracting the current CV from the clock D (n−1)  1  during the time period tCKn with the current I, and during the remaining period with 2I, that is 
     
       
           tCKn+ ( CV−tCK·I )/2 I=CV+tCKn/ 2 
       
     
     represents the timing as from the rising edge of the clock D(n−1)  1  until the rising of the clock P 2 . 
     Therefore, the timing difference with respect to the rising of the clock P 1  is just equal to tCKn/2. 
     The decay timing of the clock P 2  is caused by an output of the two-input NAND  21  going low to turn the P-channel MOS transistor MP 21  on to charge the node N 22  to high. The output of the two-input NAND  21  goes low only when a clock D (n−1)  2  and a clock P 3  are fed as inputs and both the clock D (n−1)  2  and the clock P 3  are high. 
     The clocks P 3  and P 4  are now explained. Since the timing difference between the rising edge of the clock D (n−1)  1  and that of the clock D (n−1)  2  is tCKn, the rise timing difference between the clocks P 1  and P 3  is tCKn. So, the rising timing difference between the clocks P 2  and P 3  is also ½tCKn. Similarly, the rising timing difference between clocks P 3  and P 4  and that between clocks P 4  and P 1  are also ½tCKn. 
     Therefore, the clocks P 1  to P 4  are four-phase signals of 25% duty, as mentioned previously. 
     The clocks P 1  and P 3  and the clocks P 2  and P 4  are respectively multiplexed by multiplexing circuits  112 ,  113 , each being comprised of a NOR circuit NOR 12  and an inverter INV 13 , shown in FIG. 14, and become two-phase clock signals of 50% duty. 
     In order for the rising of the clock P 2  to be ½tCKn for the rising of the clock P 1 , the condition that the threshold value of the inverter INV 21  be not reached even when electrical charges of the node N 22  are extracted by the N-channel MOS transistor MN 21  during the period of tCKn, that is the condition of 
     
       
           CV−tCKn·I&gt; 0 
       
     
     need to be met. 
     However, tCKn is not previously determined by the period of the external clock  1  at the time of designing, so that the current I is fluctuated with device characteristics. 
     Therefore, in order to cope with this, the CV value is varied depending on the period of the external clock  105  and with device characteristics. 
     The gates of the N-channel MOS transistors, connected to the capacitance device (MN 17  to MN 19  in FIG.  9 ), are fed with a control signal  106 , as explained previously, such that the load of the common node N 12  can be varied with the control signal  106 . 
     Since the N-channel MOS transistors and the capacitance devices are set to the size ratio of 1:2:4, eight-stage adjustment is possible. 
     The control signal  106  is a value corresponding to the count value of the number of times of oscillations of the ring oscillator, obtained by a counter, during a period of the external clock  105 , in a period detection circuit  104 . In this circuit configuration, since the relation between the period of the external clocks and the period of the ring oscillator representative of device characteristics is coded, not only is the operating range not increased relative to the period of the external clocks  1 , but also variations in the device characteristics are resolved. 
     In the present conventional structure, two-phase clock multiplying circuits  102   1  to  102   n  are connected in series, with the frequency of the respective input clocks D 1 , D to D (n−1)  1  and D (n−1)  2  increasing at a factor of two, so that the capacitance value is adjusted between the two-phase clock multiplying circuits  102   1  to  102   n  in order to optimise the CV value. 
     In the conventional circuit, described above, multiplied clocks can be generated by dividing the frequency of the external clocks  1  by two to generate two-phase clocks without using feedback circuits, such as PLL or DLL. 
     FIG. 15 shows a circuit configuration explained as the second embodiment in the JP-A-11-4145 and including a ¼ frequency divider  201 , series-connected four-phase clock multiplying circuits  202   1  to  202   n , a clock synthesis circuit  203  and a period detection circuit  204 . 
     The operation of the circuit shown in FIG. 15 is explained with reference to the timing diagram of FIG.  16 . This circuit divides the external clock signals  205  by the ¼ frequency divider  201  to generate four-phase clocks Q 1  to Q 4  which are frequency-doubled by a four-phase clock multiplying circuit  202 , to generate four-phase clocks Q 11  to Q 14 . The similar process is repeated up to four-phase clock multiplying circuits  202   1  to  202   n  to generate four-phase clocks Q 1  to Q 4  frequency multiplied by a factor of 2n. These clocks are synthesised by a clock synthesis circuit  203  to generate multiplied clocks  207 . 
     The period detection circuit  204  is made up of a fixed number of steps of ring oscillators and counters. Specifically, the number of times of oscillations of the ring oscillator during the period of the external clocks  205  is counted by a counter, and a control signal  206  is generated depending on the count value to adjust the load in the four-phase clock multiplying circuits  202   1  to  202   n . By the period detection circuit  204 , the operating range of the external clocks of the circuit and variations in the device characteristics may be resolved. 
     Referring to FIG. 17, the structure of the four-phase clock multiplying circuit  202  is explained. The four-phase clock multiplying circuits  202   1  to  202   n  are of the same configuration. Referring to FIG. 17, the four-phase clock multiplying circuit  202   n  is made up of eight timing difference division circuits  208  to  215 , eight pulse width correction circuits  216  to  223  and four multiplexing circuits  224  to  227 . 
     The inner structures of the eight timing difference division circuits  208  to  215 , eight pulse width correction circuits  216  to  223  and four multiplexing circuits  224  to  227  will be explained subsequently. 
     Referring to FIGS. 17 and 18, the internal connection and operation of the four-phase clock multiplying circuit  202   n  are hereinafter explained. The four-phase clock multiplying circuit  202 , is fed with four-phase clocks Q (n−1)  1  to Q (n−1)  4  and a control signal  206  from the period detection circuit  204  to output frequency doubled four-phase clocks Qn 1  to Qn 4 . 
     In the four-phase clock multiplying circuit  202 ,, the control signal  206  is input to the eight timing difference division circuits  208  to  215 . The clocks Q (n−1) to D (n−1)  4  are input to the timing difference division circuits  208 ,  210 ,  212 ,  214 , one signal at a time, while being input to the timing difference division circuits  209 ,  211 ,  213 ,  215 , two signals at a time. Eight clocks T 21  to T 28  are output from the eight timing difference division circuits  208  to  215 . 
     The rising of the clocks T 21  is determined by the delay corresponding to the internal delay as from the rising of the clock Q (n−1)  1 . 
     The rising of the clock T 22  is determined by the timing division of the rising of the clock Q (n−1)  1  and the rising of the clock Q (n−1)  2  and by the inner delay. 
     The rising of the clock T 23  is determined by the delay corresponding to the inner delay as from the rising of the clock Q (n−1)  2 . 
     The rising of the clock T 24  is determined by the timing division of the rising of the clock Q (n−1)  2  and the rising of the clock Q (n−1)  3  and by the inner delay. 
     The rising of the clock T 25  is determined by the delay corresponding to the inner delay as from the rising of the clock Q (n−1)  3 . 
     The rising of the clock T 26  is determined by the timing division of the rising of the clock Q (n−1)  3  and the rising of the clock Q (n−1)  4  and by the inner delay. 
     The rising of the clock T 27  is determined by the delay corresponding to the inner delay as from the rising of the clock Q (n−1)  4 . 
     The rising of the clock T 28  is determined by the timing division of the rising of the clock Q (n−1)  4  and the rising of the clock Q (n−1)  1  and by the inner delay. 
     The clocks T 21  and T 23  are input to a pulse width correction circuit  216  which then outputs an L pulse P 21  having a decaying edge determined by the clock T 21  and a rising edge determined by the clock T 23 . By a similar sequence of operations, pulses p 22  to P 28  are generated. So, the clocks P 21  to P 28  are eight pulses with 25% duty respectively dephased by 45°. 
     The clocks P 25 , dephased by 180° from the clock P 21 , are multiplexed and inverted by the multiplexing circuit  224  and output as 25%-duty clock Qn 1 . In a similar sequence of operations, clocks Qn 2  to Qn 4  are generated. So, the clocks Qn 1  to Qn 4  are 50%-duty four-phase H pulses each with a dephasing of 90°. 
     The period of the clocks Qn 1  to Qn 4  is just one-half that of the clock Q (n−1)  1  to Q (n−1)  4 . That is, the clock frequency is doubled in the course of generating the clocks Qn 1  to Qn 4  from the clocks Q (n−1)  1  to Q (n−1)  4 . 
     Referring to FIGS. 19 and 20, the circuit configuration of the timing difference division circuits  208  to  215  is explained. The timing difference division circuits  208  to  215  are of the same circuit configuration. 
     In the following, only the timing difference division circuits  208  and  209  are explained. FIGS. 19 and 20 show the circuit configuration of the timing difference division circuits  208  and  209 , respectively. The circuits shown in FIGS. 19 and 20 are similar in structure except that the two inputs vary. That is, the input signals to the two-input NOR circuit differ in FIGS. 19 and 20. 
     The timing difference division circuit  208  has an inner node N 51 , as an output node of the two-input NOR  51 , having the same input Q (n−1)  1  as an input. The inner node N 51  is connected to an input end of the inverter INV 51 , which outputs T 21  at its output end. The timing difference division circuit  208  also includes N-channel MOS transistors MN 51 , MN 52  and MN 53 , having drains commonly connected to the inner node N 51 , and which are controlled on and off by a control signal  206  from the period detection circuit  204  being coupled to the gates, and capacitances CAP 51 , CAP 52  and CAP 53  connected across the sources of the N-channel MOS transistors MN 51 , MN 52  and MN 53  and the ground potential. The gate widths of the N-channel MOS transistors MN 51 , MN 52  and MN 53  and the capacitances CAP 51 , CAP 52  and CAP 53  are set to the size ratio of e.g., 1:2:4. The clock period is set by eight-stage adjustment of the load connected to the common node based on the control signal  206  output from the period detection circuit  204 . 
     The timing difference division circuit  209  has an inner node N 61 , as an output node of the two-input NOR  61 , having the same input Q (n−1)  2  as an input. The inner node N 61  is connected to an input end of the inverter INV 61 , which outputs T 22  at its output end. The timing difference division circuit  208  also includes N-channel MOS transistors MN 61 , MN 62  and MN 63 , having drains commonly connected to the inner node N 61 , and which are controlled on and off by a control signal  206  from the period detection circuit  204  being coupled to the gates, and capacitances CAP 61 , CAP 62  and CAP 63  connected across the sources of the N-channel MOS transistors MN 61 , MN 62  and MN 63  and the ground potential. The gate widths of the N-channel MOS transistors MN 61 , MN 62  and MN 63  and the capacitances CAP 61 , CAP 62  and CAP 63  are set to the size ratio of e.g., 1:2:4. The clock period is set by eight-stage adjustment of the load connected to the common node based on the control signal  206  output from the period detection circuit  204 . 
     The operation of the timing difference division circuits  208 ,  209  is now explained by referring to the timing waveform shown in FIG.  21 . 
     The operation of the timing difference division circuit  208  is finished during the time period from tc 21  until tc 24  of FIG.  21 . So, the waveform of the inner node N 51  during this time period is shown. 
     First, the rising timing of the output clock T 21  is explained. The two-input NOR  51  includes two P-channel MOS transistors for connecting input signals IN 1 , IN 2  to the gates, and two N-channel MOS transistors, connected in parallel across the output end and the ground and having gates fed with the input signals IN 1 , IN 2 . 
     When the electrical charges of the node N 51  are extracted by the NOR 51  with the rising edge of the clock Q (n−1)  1 , so that the potential of the node N 22  reaches the threshold value of the inverter INV 51 , the edge of the clock T 21 , output by the inverter INV 51 , rises. If the electrical charges of the node N 51  that need to be extracted until the threshold value of the inverter INV 51  is reached, are denoted CV, and the charge extracting current values of the N-channel MOS transistors are denoted I, the result of extracting the electrical charges CV from the rising of the clock Q (n−1)  1 , that is CV/2I, represents the timing from the rising of the clock Q (n−1) until rising of the clock T 21 . 
     The rising of the clock T 21  is by the clock Q (n−1)  1  going low to charge the output node N 51  of the two-input NOR 51  to high. 
     As for the operation of the timing difference division circuit  209 , shown in FIG. 20, the operation of the timing difference division circuit  209  is well-nigh finished during the time period from ta 21  until ta 24  of FIG.  21 . So, the waveform of the inner node N 61  during this time period is shown. 
     First, the rising timing of the output clock T 22  is explained. During the time period tCKn as from the rising edge of the clock D (n−1)  1 , the electrical charges of the inner node N 22  are extracted by the N-channel MOS transistor. After time tCKn, the residual electrical charges at the inner node N 61  are extracted from the rising edge of the clock Q (n−1)  2  by the N-channel MOS transistors, so that, when the potential of the node N 61  reaches the threshold value of the inverter INV 61 , the edge of the clock T 22  rises. If the electrical charges of the node N 61  are denoted CV, and the charge extracting current values of the N-channel MOS transistors of the two-input NOR 61  are denoted I, the result of extracting the current CV from the clock Q (n−1)  1  during the time period I of tCKn with the current I, and during the remaining period with 2I, that is 
     
       
           tCKn+ ( CV−tCKn· )/2 I=CV+tCKn/ 2 
       
     
     represents the timing as from the rising edge of the clock Q(n−1) until the rising of the clock T 22 . 
     Therefore, the timing difference with respect to the rising of the clock T 21  is just equal to tCKn/2. 
     The rising of the clock T 22  is by both the clocks Q (n−1)  1  and clocks Q (n−1)  12  going low to charge the output node N 61  of the two-input NOR 61  high. 
     The same explanations apply for clocks T 23  to T 28 , that is, the rise timing differences of the clocks T 21  to T 28  are respectively equal to ½tCKn. 
     The pulse width correction circuits  216  to  223  are each made up of an inverter INV 71  and a two-input NAND  71 , as shown in FIG. 22, and generate eight-phase pulses (split signals) P 21  to P 28 , with the duty of 25%, with a dephasing being 45°. 
     The multiplexing circuit  224  is comprised of a two-input NAND  81 , and generates 50% duty four-phase clocks Qn 1  to Qn 4 , having a dephasing of 90°, as mentioned previously. The period of the clocks Qn 1  to Qn 4  is just one-half the clock Q (n−1)  1  to Q (n−1)  4 . 
     In the present conventional clock multiplying circuits, the condition required to make the load of the common node N 61  variable is the same as that in FIG.  9 . So, the capacitances and NMOS transistors having the same operating object are used in combination. It is possible not only to increase the operating range for the period of the external clock signals  205  but also to eliminate variations in device characteristics. 
     In the above-described conventional multiplying circuit, proposed in the JP-A-11-4145, multiplied clocks may be produced by frequency-dividing the external clocks by a factor of four to prepare four-phase clocks at the outset, without using feedback circuits, such as PLL or DLL. 
     There may also be derived an advantage that, by frequency division by a factor of four, multiplying circuits may be constructed by fully static simple circuits using basic CMOS devices, such as NAND, NOR or inverters. 
     In the JP-A-11-4145, two-phase multiplied clocks are generated from two-phase clocks, while four-phase multiplied clocks are generated from four-phase clocks. It is however possible to connect plural timing difference division circuits in parallel in a tree-like fashion to increase the number of clock phases exponentially to 2, 4 or 8 to generate higher frequency components. 
     In the JP-A-11-4145, multiplied clocks may be generated extremely readily by frequency dividing external clocks into multi-phase clocks and taking an intermediate timing of each phase without the necessity of using a loop configuration. 
     So, the time period in which to produce multiplied clocks may be shorter, while the number of required clocks can be predicted at the outset, and hence the queuing time until using the multiplied clocks may be reduced appreciably. 
     The method of realising multiples other than powers of two by a similar technique is described in JP Patent Application 09-157042 (JP-A-11-4146), the entire disclosure thereof being herein incorporated by reference thereto. 
     SUMMARY OF THE DISCLOSURE 
     However, in the timing difference division circuit (interpolator) in the multiplying circuits, as proposed in JP-A-11-4146 and in JP-A-11-4145, since multi-phase clocks are directly input as input signals, the operating range is not enlarged to the maximum extent. 
     For example, if the capacitance value of the capacitance device is fixed and four-phase clock signals are input, there is a constraint that the capacitance value which is just one half of the input phase difference is in a range from 1:3 for the smallest and largest values, as now explained. 
     FIG. 26 shows an illustrative structure of a conventional timing difference division circuit. Referring to FIG. 26, the conventional timing difference division circuit includes a logical sum circuit OR 1 , fed with first and second input signals IN 1 , IN 2 , a P-channel MOS transistor MP 1 , connected across the power source VCC and the inner node N 26  and to the gate of which an output signal of the logical sum circuit OR 1  is fed, an inverter INV 3 , for outputting an inverted version of the potential of the inner node N 26 , and N-channel MOS transistors MN 1 , MN 2 , each having a drain connected to the inner node N 26 , a gate fed with first and second input signals IN 1 , IN 2 , respectively, and a source connected to a constant current source  10 . Across the inner node N 26  and the ground are connected switching devices MN 11  to MN 15 , comprised of N-channel MOS transistors, and capacitances CAP 11  to CAP 15 . As in the timing difference division circuit, explained with reference to FIGS. 9 to  12 , a control signal  106  output from the period detection circuit is connected to control terminals (gate terminals) of the switching devices MN 11  to MN 15 , comprised of N-channel MOS transistors, to set a capacitance value to be appended to the inner node N 26 . 
     When the first and second input signals IN 1 , IN 2  are of low levels, an output of the logical sum circuit OR 1  goes low to turn on the P-channel MOS transistor MP 1  to charge the inner node N 26  to the power source potential so that the output of the inverter INV 3  goes low. 
     When one or both of the first and second input signals IN 1 , IN 2  are high, an output of the logical circuit OR 1  goes high to turn the P-channel MOS transistor MP 1  and the power source path of the inner node N 26  and the power source VCC off, while one or both of the N-channel MOS transistors MN 1  and MN 2  are on, to discharge the inner node N 26 . When the potential of the inner node N 26  starts to be decreased from the power source potential, until a potential that is not higher than the threshold value of the inverter INV 3 , an output of the inverter INV 3  starts from the low level to the high level. 
     FIG. 27 illustrates the operation of the timing difference division circuit (TMD). Referring to FIG. 27 a , two outputs of the first timing difference division circuit (TMD) of the three timing difference division circuits are fed with the same input signal IN 1  to output an output signal OUT 1 . The second timing difference division circuit (TMD) is fed with the input signals IN 1 , IN 2  to output an output signal OUT 2 , while the third timing difference division circuit (TMD) is fed at two inputs thereof with the same input signal IN 2  to output an output signal OUT 3 . Of these, the second timing difference division circuit (TMD) fed with the input signals IN 1 , IN 2  to output the output signal OUT 2  is matched to the structure of the timing difference division circuit  209  of FIG.  17 . On the other hand, the timing difference division circuit (TMD) commonly fed with IN 1  and the timing difference division circuit (TMD) commonly fed with IN 2  are configured for being fed with the same signal in FIG.  26  and hence is matched to the configuration of the timing difference division circuit  208  of FIG.  17 . 
     FIG. 27 b  shows outputs OUT 1  to OUT 3  of the first to third timing difference division circuits fed with input signals IN 1 , IN 2  of the timing difference T and changes A 1  to A 3  of the inner nodes of the first to third timing difference division circuits. For facilitating the description, it is assumed that the inner node is charged from the zero potential and, when the threshold value Vt is exceeded, the output signal is changed from the low level to the high level. 
     Referring to FIG. 27 b , there is a timing difference between the input signals IN 1  and IN 2 , the first timing difference division circuit (TMD) issues an output signal OUT 1  with a delay time t 1 , the third timing difference division circuit (TMD) issues an output signal OUT 3  with a delay time t 3  and the second timing difference division circuit (TMD) issues an output signal OUT 2  with a delay time t 2 , with the delay time t 2  being of a value corresponding to the interior division of the delay time t 1  and the delay time t 3 , such that 
     
       
           T   1 = CV/ 2 I   
       
     
     
       
           t   2 = T+ ( CV−IT )/(2 I )= T/ 2+ CV/ 2 I.   
       
     
     On the other hand, t 3 =T+CV/2I. It is noted that electrical charges discharged until the threshold value of the buffer circuit (inverter), to the input end of which is connected the inner node, is exceeded, is denoted CV. 
     FIG. 28 is a signal waveform diagram showing, for two-phase clocks IN 1 , IN 2  obtained on frequency division of the clocks with the period equal to tCK, the manner of voltage changes in the inner node  26  and input signals in case the in-phase signals and phase signals are input to the timing difference division circuit shown in FIG.  26 . 
     Referring to FIGS. 26 and 28, if electrical charges discharged until the threshold value of the inverter INV 3  is exceeded are CV, where C is a capacitance value appended to the inner node N 26 , and V is the threshold voltage t of the inverter INV 3 , the N-channel MOS transistors MN 1 , MN 2  are turned on, in case of the in-phase input, by the rising of the input signal IN 1  from the low level to the high level, to turn the N-channel MOS transistors MN 1 , MN 2  on to discharge the electrical charges with the current 2I. The time period during which the N-channel MOS transistors MN 1 , MN 2  are turned on is not longer than 2tCK, so that, if the electrical charges are not extracted during 2tCK, there is produced no output at an output end of the timing difference division circuit. 
     So, the capacitance value C satisfying 
     
       
           CV/ 2 I&gt; 2 tCK   
       
     
     represents the maximum value C max meeting the I/2 component of the phase difference T: 
     
       
           C  max=4 tCK·I/Vt.   
       
     
     In the case of the different phase input, the N-channel MOS transistor MN 1  is turned on by the rising of the input signal IN 1  from the low level to the high level to discharge the electrical charges at the current I. After T=tCK, the N-channel transistor MN 2  is turned on by the rising of the input signal IN 2  from the low level to the high level. 
     If the electrical charges of the node N 26 , that need to be extracted until the threshold value of the inverter INV 3  is reached, are CV, and the current with which the electrical charges of the N-channel MOS transistors MN 1  and MN 2  is I, respectively, the electrical charges CV are extracted with the current I during the phase difference T as from the rising of the first input signal IN 1  until the rising of the second input signal IN 2  and thereafter with the current 2I. 
     If the electrical charges CV are extracted during the phase difference T until the rising of the second input signal IN 2 , the I/2 component of the phase difference T is removed. So, 
     
       
         
           CV/I&lt;T 
         
       
     
     and 
     
       
           C  min= tCK·I/Vt.   
       
     
     The period of extraction with the current 2I is the overlap period Tovp of the first input signal IN 1  and the second input signal IN 2 . If the CV is not completely extracted during this overlap period Tovp, the output of the timing difference division circuit is devoid of the I/2 component of the phase difference T. 
     So, the maximum capacitance value C which satisfies 
      ( CV−T·I )/2 I&lt;T   
     represents the maximum value C max: 
     
       
           C  max=(2 T·+T ) I/V= 3 tCK·I/Vt   
       
     
     which satisfies the I/2 component (T/2) of the phase difference T. 
     If two four-phase clock signals, with a period tCK, are input, to output a signal with a delay just equal to ½ (2tCK), the ratio of the minimum value C min to the maximum value C max of the value of the capacitance appended to the inner node N 26  subjected to charging/discharging is approximately 1:3, as shown in FIG. 28, in which the ordinate is the ratio of the interior division of the timing difference division circuit (dividing ratio), which, from the delay time of A 1  to A 3  in FIG. 27 b , is equivalent to A 2 /(A 3 −A 2 ), and the abscissa is the value of the capacitance appended to the interior node N 26 . 
     In the structure of the conventional timing difference division circuit, shown in, for example, FIG. 26 etc., the MOS transistors and the MOS capacitance are used to adjust the value of the capacitance of the capacitance device CAP appended to the inner node, there is required an area corresponding to the area of the MOS transistors and the MOS capacitances, thus increasing the chip area. 
     It is therefore an object of the present invention to provide a timing difference division circuit and a method for timing difference division whereby the operating speed may be increased and the chip area may be prevented from being increased while enabling a broadband operation. 
     According to a first aspect of the present invention, there is provided a timing difference division circuit (e.g., interpolator) at least comprising: 
     two switches connected in parallel to control a path between an inner node and a power source on or off, one of switches being turned on based on one of two input signals undergoing faster transition to charge or discharge a capacitance appended to the inner node with a first current, the other switch being turned on based on the other input signal undergoing transition with a delay with respect to the one input signal, capacitance appended to the inner node being charged or discharged through the one switch in the on-state and the other switch in the on-state with a current value corresponding to a sum of the first current and a second current; 
     there being provided a buffer circuit an output logic value of which is changed when the voltage of the inner node exceeds or is smaller than a threshold value. The timing difference division circuit further comprises a circuit unit for setting, based on the one signal and on the other signal, an overlap period (Tovp) during which an on time period of the one switch is overlapped with an on time period of the other switch, to a desired value. 
     According to a second aspect of the present invention, the aforementioned circuit unit elongates the overlap period (Tovp) forwardly of a leading edge of the other signal undergoing transition with a delay from the one signal. The overlap period (Tovp) may also begin at the leading edge of the other signal and may be further extended from the trailing edge of the one signal so that the overlap period will have an optionally selected value. 
     According to a third aspect of the present invention, the circuit unit sets the overlap period Tovp so that it begins at the forward edge of the other signal undergoing transition with a delay from the one signal and ends at the trailing edge of the other signal. 
     According to a fourth aspect of the present invention, the capacitance of the inner node is made up of plural capacitances (typically of MOS capacitors), the connection of which to the inner node is controlled by a control signal. 
     According to a fifth aspect, there is provided a timing difference division circuit comprising: 
     a logic circuit generating and outputting a first gate signal and a second gate signal based on a first input signal; and 
     a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal; 
     a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source, the first and second series circuits being connected in parallel across the inner node and the second power source; 
     the first and second gate signals being connected to control terminals of the second and third switches, respectively; 
     the timing difference division circuit further comprising: 
     a plurality of MOS capacitors, connection of which to the inner node being separately controlled by a control signal; and 
     a buffer circuit an input end of which is connected to the inner node and the value of an output signal of which is determined based on the relative magnitude of a potential of the inner node and a threshold voltage; 
     wherein an overlap period during which the first and second gate signals output from the logic circuit are both activated to turn on the second and third switch elements is set to an optional value. 
     According to a sixth aspect, there is provided a timing difference division circuit comprising: 
     a logic circuit generating and outputting a first gate signal and a second gate signal based on a first input signal and a second input signal; 
     a first MOS transistor of a first conductivity type, having a source, a drain and a gate connected to a first power source, an inner node and to the first gate signal, respectively; 
     second and third MOS transistors of a second conductivity type having drains commonly connected to the inner node and to the gates of which the first and second gate signals are connected; 
     a first constant current source and a second constant current source connected across a source of the second MOS transistor and the second power source and across a source of the third MOS transistor and the second power source, respectively; 
     a plurality of MOS transistors of the first conductivity type, having sources and drains connected to the inner node and to the gates of which control signals are connected; and 
     a buffer circuit an input end of which is connected to the inner node and the value of an output signal of which is determined based on the relative magnitude of the potential of the inner node and a threshold voltage; 
     wherein an overlap period during which the first and second gate signals output from the logic circuit are both activated to turn on the second and third MOS transistors simultaneously is set to an optional value. 
     In the timing difference division circuit of the fifth or sixth aspect, the following may be employed. 
     The logic circuit outputs, as the first gate signal, a signal the timing of a beginning edge of which is determined by a beginning edge of one of the first and second input signals having a leading phase and the timing of an end edge of which is determined by an end edge of the input signal having a lagging phase; 
     the logic circuit outputting, as the second gate signal, a signal the timing of a beginning edge of which is determined by a beginning edge of one of the first and second input signals having a lagging phase and the timing of an end edge of which is determined by an end edge of the input signal having the lagging phase. 
     Also, the following structure may be employed: 
     The logic circuit includes a first gate circuit outputting a first value as the first gate signal when the first and second signals assume first and second values, respectively, or both assume the second value such that both of the first and second signals assume values other than the first value; and 
     a second gate circuit outputting a first value as the second gate signal when the signal of the lagging phase assumes a second value. 
     Further, the following structure may be employed: 
     The logic circuit outputs, as the first and second gate signals, an in-phase signal the timing of a beginning edge of which is determined by a beginning edge of one of the first and second input signals having a leading phase and the timing of an end edge of which is determined by an end edge of the input signal having a lagging phase. 
     The capacitance values of plural MOS capacitors are connected to the inner node differ from one another. 
     For the fourth or fifth aspect, the plural MOS transistors of the first conductivity type, the sources and drains of which are connected to the inner node, may be of respectively different gate lengths or gate widths. 
     For the sixth aspect, the first and second input signals may be made up of clocks of respectively different phases generated on frequency division of input clock signals; and 
     the control signal fed to the gates of the plural MOS transistors of the first conductivity type, the sources and drains of which are both connected to the inner node, is supplied from a circuit detecting the period of the clocks. 
     According to a seventh aspect, there is provided a clock controlling circuit for generating and outputting multi-phase clocks on frequency division of input clocks; 
     the clock controlling circuit comprising: 
     a frequency divider generating and outputting multi-phase clocks by frequency-dividing an input clock; 
     a period detection circuit for detecting the period of the input clock; and 
     a multi-phase multiplying circuit being fed as input with multi-phase clocks output from the frequency divider to generate multi-phase clocks multiplied from the clocks; 
     wherein the multi-phase multiplying circuit includes: 
     a plurality of timing difference division circuits outputting a signal corresponding to division of the timing difference of two inputs as defined in any one of first to sixth aspects, and 
     a plurality of multiplexing circuits multiplexing and outputting outputs of two of the timing difference division circuits. 
     The clock controlling circuit may further comprise a two-phase clock multiplying circuit, wherein the two-phase clock multiplying circuit includes: 
     four timing difference division circuits being fed with two-phase clocks and outputting a signal corresponding to division of the timing difference of two inputs, and 
     two multiplexing circuits one being fed with outputs of the first and third timing difference division circuits and the other being fed with outputs of the second and fourth timing difference division circuits. 
     For the clock controlling circuit, 
     the multi-phase clock multiplying circuit may include 
     (a) 2n timing difference division circuits each being fed with n-phase clocks (first to nth clocks) and outputting a signal corresponding to the division of the timing difference of two inputs; 
     the 2I−1st timing difference division circuit, where 1≦I≦n, being fed with the same Ith clock as the two inputs; 
     the 2Ith timing difference division circuit, where 1≦I≦n, being fed with the Ith clock and (I+1 mod n)th clock, as inputs, where “mod” denotes remainder processing and I+1 mod n means a remainder resulting from division of I+1 by n; 
     (b) 2n pulse width correction circuits fed with an output of the Jth timing difference division circuit, where 1≦J≦2n, and with an output of the (J+2mod n) th timing difference division circuit, where n is a remainder obtained on dividing J+2 with n, as inputs; and 
     (c) n multiplexing circuits fed each with an output of the Kth pulse width correction circuit, where 1≦K≦n, and with an output of the (K+n)th pulse width correction circuit, as inputs. 
     According to an eighth aspect, there is provided a signal controlling method in which one of two switches connected in parallel across an inner node and a power source is turned on based on one of two input signals undergoing faster transition to charge or discharge a capacitance of the inner node with a first current, 
     the other switch being turned on based on the other input signal undergoing transition with a delay with respect to the one input signal, the capacitance of the inner node being charged or discharged through the one switch in the on-state and the other switch in the on-state with a current value corresponding to a sum of the first current and a second current, an output logic value of the buffer circuit being changed when the voltage of the inner node exceeds or is smaller than a threshold value of the buffer circuit to output from the buffer circuit a signal of a delay time corresponding to a divided value of the timing difference of two input signals; 
     wherein based on the one signal and the other signal, an overlap period (Tovp) during which an on time period of the one switch is overlapped with an on time period of the other switch is made adjustable to a desired value to enlarge the range of the capacitance appended to the inner node with respect to the divided value of the timing difference of the two input timing signals. 
     In the signal controlling method, 
     the overlap period (Tovp) may be elongated forwardly of a leading edge of the other signal undergoing transition with a delay with respect to the one signal or the overlap period (Tovp) is caused to begin at the leading edge of the other signal and to be elongated rearwardly of the trailing edge of the one signal so that the overlap period will have an optional value. 
     In the signal controlling method, the overlap period (Tovp) may be caused to begin at the forward edge of the other signal undergoing transition with a delay from the one signal and to end at the trailing edge of the other signal. 
     According to a ninth aspect, there is provided a signal controlling method in which first and second input signals with respective different phases are input and an output signal of a delay time determined by a time resulting from division of a timing difference between the two input signals, 
     wherein from the first and second input signals, a first gate signal and a second gate signal are generated, 
     the timing of a beginning edge of the first gate signal being determined based on a beginning edge of one of the first and second input signals having a leading phase, and the timing of an end edge of the first gate signal being determined by an end edge of the input signal having a lagging phase, and 
     the timing of a beginning edge of the second gate signal being determined by a beginning edge of one of the first and second input signals having a lagging phase, and the timing of an end edge of the second gate signal being determined by an end edge of the input signal having the lagging phase, 
     the capacitance of the inner node is first charged or discharged by one of first and second switch elements connected across the inner node and a power source, the one being turned on based on the first gate signal; 
     subsequently the capacitance of the inner node is also charged or discharged by the switch element turned on based on the second gate signal in conjunction with the switch element turned on based on the second gate signal; and 
     wherein from a buffer circuit to an input end of which the inner node is connected and an output logic value of which is changed in case where the inner node voltage exceeds or is smaller than a threshold value, an output signal including a time resulting from division of the timing difference of the first and second input signals is output. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 a  shows a structure of an embodiment of the present invention and FIG. 1 b  is a timing diagram showing the operation. 
     FIG. 2 a  shows a structure of another embodiment of the present invention and FIG. 2 b  is a timing diagram showing the operation. 
     FIG. 3 a  shows a structure of still another embodiment of the present invention and FIG. 3 b  is a timing diagram showing the operation. 
     FIG. 4 shows a structure of a clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 5 similarly shows a structure of a clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 6 is a timing chart for illustrating the operation of the clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 7 is a circuit diagram showing a two-phase clock multiplexing circuit used in the clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 8 is a timing chart for illustrating the operation used in the clock signal controlling device shown in JP-A-11-4145. 
     FIG. 9 is a circuit diagram showing timing difference division circuit used in the clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 10 is a circuit diagram showing timing difference division circuit used in the clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 11 is a circuit diagram showing a specified typical timing difference division circuit used in the clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 12 is a circuit diagram showing another specified typical timing difference division circuit used in the clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 13 is a timing chart for illustrating the operation of four timing difference division circuits used in the clock signal controlling device shown in JP-A-11-4145. 
     FIG. 14 is a circuit diagram showing a specified typical multiplexing circuit used in the clock signal-controlling device shown in JP-A-11-4145. 
     FIG. 15 shows the structure of a clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 16 is a timing chart for illustrating the operation of the clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 17 is a circuit diagram showing a specified typical four-phase clock multiplying circuit used in the clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 18 is a timing chart for illustrating the operation of a four-phase clock multiplying circuit used in the clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 19 is a circuit diagram showing a specified typical timing difference division circuit used in the clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 20 is a circuit diagram showing a specified typical timing difference division circuit used in the clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 21 is a timing chart for illustrating the operation of the timing difference division circuit used in the clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 22 is a circuit diagram showing a specified typical pulse width correction circuit used in the clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 23 is a circuit diagram showing a specified typical multiplexing circuit used in the clock signal controlling device shown in JP-A-11-4145 (embodiment  2 ). 
     FIG. 24 is a circuit diagram showing a conventional clock signal multiplying circuit employing a delay circuit queue. 
     FIG. 25 is a circuit diagram showing a conventional clock signal multiplying circuit employing a PLL. 
     FIG. 26 shows a typical circuit configuration of a conventional timing difference division circuit (interpolator). 
     FIG.  27 ( a ) to FIG.  27 ( c ) illustrate the operating principle of a timing difference division circuit (interpolator). 
     FIG.  28 ( a ) and FIG.  28 ( b ) show timing charts for illustrating the operation of the conventional timing difference division circuit shown in FIG.  26 . 
     FIG. 29 shows a typical relation between the capacitance value and the ratio of interior division in the conventional timing difference division circuit. 
    
    
     PREFERRED EMBODIMENTS OF THE INVENTION 
     An embodiment of the present invention is explained. The present invention is directed to a timing difference division circuit at least including two switches MN 1 , MN 2  connected in parallel to control a path between an inner node N 1  and a power source on or off, one of the switches MN 1  being turned on based on one of two input signals IN 1 , IN 2  undergoing faster transition to charge or discharge a capacitance C appended (connected) to the inner node N 1  with a first current (I), the other switch MN 2  being turned on based on the other input signal undergoing transition with a delay with respect to the one input signal, the capacitance appended to the inner node being charged or discharged through the one switch in the on-state and the other switch in the on-state with a current value corresponding to a sum (2I) of the first current and a second current; there being provided a buffer circuit INV 1  an output logic value of which is changed when the voltage of the inner node exceeds or is smaller than a threshold value. The timing difference division circuit includes a circuit unit L 1  for setting, based on the one signal and on the other signal, an overlap period Tovp during which an on time period of the one switch is overlapped with an on time period of the other switch, to a desired value. 
     More specifically, a preferred embodiment is directed to a timing difference division circuit L 1  including a logic circuit L 1  fed with a first input signal and a second input signal IN 1 , IN 2  and outputting first and second gate signals G 1 , G 2 , a first MOS transistor MP 1  of a first conductivity type, having a source, a drain and a gate connected to a first power source Vcc, an inner node N 1  and to the first gate signal G 1 , respectively, second and third MOS transistors MN 1 , MN 2  of a second conductivity type having drains commonly connected to the inner node and to the gates of which the first and second gate signals G 1 , G 2  are connected, a first constant current source and a second constant current source  10   1 ,  10   2  connected across a source of the second MOS transistor MN 1  and the second power source and across a source of the third MOS transistor MN 2  and the second power source GND, respectively, a plurality of MOS capacitors MP 11  to MP 14  of the first conductivity type connected to the inner node and a buffer circuit INV 1  an input end of which is connected to the inner node N 1  and the value of an output signal of which is determined based on the relative magnitude of the potential of the inner node and a threshold voltage Vt. 
     In a preferred embodiment of the present invention, the logic circuit L 1  outputs, as the first gate signal G 1 , a signal the timing of a beginning edge of which is determined by a beginning edge (leading edge) of one of the first and second input signals IN 1 , IN 2  having a leading phase and the timing of an end edge of which is determined by an end edge (trailing edge) of the input signal having a lagging phase. The logic circuit L 1  outputs, as the second gate signal, a signal the timing of a beginning edge of which is determined by a beginning edge of one of the first and second input signals having a lagging phase and the timing of an end edge of which is determined by an end edge of the input signal having the lagging phase. 
     In a preferred embodiment of the present invention, the timing of the first and second gate signals, output from the logic circuit L 1 , is adjusted by adjusting the timing at which the second and third MOS transistors MN 1 , MN 2  of the second conductivity type are overlapped and turned on. The maximum value C max of the capacitance to be appended to the inner node N 1  can be varied when two four-phase clocks with the period tCK are input and signals with the delay just equal to ½ (2tCK) can be varied. 
     In the conventional timing difference division circuit, it is retained to be necessary to extract electrical charges CV of the inner node down to the threshold voltage or less, within the phase difference T and the overlapping time Tovp (=tCK) of the first and second input signals IN 1 , IN 2  of a signal with a dephasing of 90°, obtained on frequency-dividing clocks by a factor of four (period: 4tCK), with a ratio of the minimum value C min to the maximum value C max being 1:3. 
     By frequency dividing the external clocks into multi-phase clocks and taking the intermediate timing of the respective phases, it is possible to enlarge the operating range that permits the desired timing difference dividing operation in a timing difference division circuit used in a circuit that can generate multiplied clocks extremely readily without employing a looped structure. 
     The present embodiment of the present invention also features using MOS capacitors MP 11  to MP 14  as capacitances appended (annexedly connected) to the inner node N 1 . 
     The MOS capacitors MP 11  to MP 14  are MOS transistors the sources and the drains of which are connected to the inner node N 1 , and the gates of which are fed with a control signal  7 . If, in the case of a p-type semiconductor, the voltage VG applied to the gate, that is the voltage of the control signal  7 , is positive, a depletion layer is produced in the semiconductor interface, so that, as an equivalent circuit, there is produced a capacitor comprised of a series connection of the capacitance CD of the depletion layer and the capacitance C 0  of the gate oxide film. Plural MOS transistors (MP 11  to MP 14 ) of the first conductivity type are of respective different gate lengths or gate widths. 
     With such structure of the present invention, the chip area arranged in an integrated circuit can be smaller than that of a conventional circuit explained with reference to e.g., FIG.  26 . 
     The timing difference division circuit according to the present embodiment includes a frequency divider  2  (FIG. 4) for generating and outputting multi-phase clocks on frequency division of input clocks, a period detection circuit  6  (FIG. 4) for detecting the period of the input clock, and a multi-phase multiplying circuit  5  for being fed as input with multi-phase clocks output from the frequency divider to generate multi-phase clocks multiplied from the clocks. The multi-phase multiplying circuit includes a plurality of timing difference division circuits for outputting a signal corresponding to division of the timing difference of two inputs and a plurality of multiplexing circuits for multiplexing and outputting outputs of two of the timing difference division circuits. 
     The control signal from the period defection circuit is fed as a control signal to the MOS capacitance device connected to an inner node of the timing difference division circuit. 
     The clock controlling circuit also includes a two-phase clock multiplying circuit, these two-phase clock multiplying circuit including four timing difference division circuits  108  to  111  of FIG. 7 for being fed with two-phase clocks (first and second clocks) and for outputting a signal corresponding to division of the timing difference of two inputs, and two multiplexing circuits for being each fed with outputs of the first and third timing difference division circuits and outputs of the second and fourth timing difference division circuits. The timing difference division circuit of the present invention is used as these timing difference division circuits. 
     The multi-phase clock multiplying circuit includes 2n timing difference division circuits  208  to  215  (FIG. 17) each for being fed with n-phase clocks (first to nth clocks) and for outputting a signal corresponding to the division of the timing difference of two inputs. The (2I−1)st timing difference division circuit, where 1≦I≦n, is fed with the same Ith clocks as the two inputs, whilst the 2Ith timing difference division circuit, where 1≦I≦n, is fed with the Ith clock and with (I+1 mod n)th clock, as inputs, where mod denotes remainder processing and I+1 mod n means a remainder resulting from division of I+1 by m. The multi-phase clock multiplying circuit also includes 2n pulse width correction circuits  216  to  223  fed with an output of the Jth timing difference division circuit, where 1≦J≦2n, and with an output of the (J+2mod n)th timing difference division circuit where n is a remainder obtained on dividing J+2 with n, as inputs, and n multiplexing circuits  224  to  227  each fed with an output of the Kth pulse width correction circuit, where 1≦K≦n, and with an output of the (K+n)th pulse width correction circuit, as inputs. The timing difference division circuit of the present invention is used as these timing difference division circuits. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the drawings, a preferred embodiment of the present invention will be explained in detail. 
     FIG. 1 a  shows a structure of a timing difference division circuit embodying the present invention. The timing difference division circuit, also termed an interpolator, includes a logical circuit L 1 , having an input clock  1  (IN 1 ) and an input clock  2  (IN 2 ) as inputs, a P-channel MOS transistor MP 1 , having a source, a gate and a drain connected to a power source, to an output G 1  (first gate signal) of the logical circuit L 1  and to a node N 1 , respectively, and N-channel MOS transistors MN 1 , MN 2 , having drains, gates and sources connected to a common node N 1 , outputs G 1  (first gate signal) and G 2  (second gate signal) of the logical circuit L 1  and to constant current sources  10   1 ,  10   2 , respectively, with the node N 1  being connected to an input end of the inverter INV 1 . The current values of the constant current sources  10   1 ,  10   2  are equal to each other and set to 1. 
     The timing difference division circuit also includes plural P-channel MOS transistors MP 11  to MP 15 , having sources connected commonly, and having drain connected commonly and connected to the node N 1 . A control signal  7  from the period detection circuit  6  of FIG. 4 is connected to the gates of the P-channel MOS transistors MP 11  to MP 15 . Control is made so that, if the clock period is large or small, the value of the capacitance appended (connected) to the inner node N 1  is increased or decreased, respectively. 
     The first gate signal G 1  has the timing of a beginning edge (leading edge) determined by a beginning edge of a leading phase input of two-phase inputs of the input clocks  1  and  2 , while having the timing of an end edge (trailing edge) determined by the end edge of the lagging phase input. 
     The second gate signal G 2  has a timing of a beginning edge (leading edge) determined by a beginning edge of a lagging phase input of two-phase inputs of the input clocks  1  and  2 , while having the timing of an end edge (trailing edge) determined by the end edge of the lagging phase input. 
     An area specified by the gate length (L) or the gate width (W) of the P-channel MOS transistors MP 11  to MP 15  making up MOS capacitors has a ratio of 1:2:4:8:16, so that the capacitance ratio is 1:2:4:8:16. The capacitance values of the P-channel MOS transistors MP 11  to MP 15  are variably set by the voltage of the control signal  7 . 
     FIG. 1 b  shows a timing waveform for illustrating the operation of the timing difference division circuit of the embodiment of the present invention shown in FIG. 1 a . Specifically, FIG. 1 b  shows the waveform of the input clocks  1 ,  2 , at the input terminals IN 1 , IN 2 , generated by the logic circuit L 1 , first and second gate signals G 1 , G 2  generated by the logic circuit L 1  and the inner node N 1 . The input clocks  1 ,  2  are two-phase clocks, with the phase difference (timing difference) equal to T, frequency divided by a ¼ frequency diving circuit, not shown, from the four-frequency-divided signals of the clocks with the period of 4T exhibiting a phase difference of T from one another. 
     The first gate signal G 1  has its rising edge determined by the timing of the rising edge of the input clock  1  having a leading phase, while having its falling edge determined by the timing of the falling edge of the input clock  2  with the lagging phase. 
     The second gate signal G 2  has its rising edge determined by the timing of the rising edge of the input clock  1  having a lagging phase, while having its falling edge determined by the timing of the falling edge of the input clock  2  with the lagging phase. 
     FIG. 1 b  shows two sorts of waveforms N 1   e  and N 1   f , as voltage waveforms of the inner node N 1 . In order for the timing of the output signal OUT to indicate a value equal to division to ½ of the phase difference of the input clocks  1  and  2 , there is imposed a limitation to the value of the capacitance connected to the inner node N 1 . 
     It is noted that N 1   e  and N 1   f  indicate the case where the value of the capacitance connected to the inner node N 1  is the minimum capacitance C min and the case where the value of the capacitance connected to the inner node N 1  is the maximum capacitance C max. 
     First, the voltage waveform N 1  of the node N 1   e  with the minimum value of the capacitance connected to the inner node N 1  is explained. 
     During the time of the phase difference T until the second gate signal G 2  rises from the rising edge of the first gate signal G 1 , only the N-channel MOS transistor MN 1 , to the gate of which the first gate signal G 1  is input, is turned on. 
     When the electrical charges of the inner node N 1  are extracted (drawn) by the N-channel MOS transistor MN 1  so that the potential of the inner node N 1  reaches the threshold value Vt of the inverter INV 1 , an output of the inverter INV 1  rises. 
     Assume that the electrical charge of the inner node N 1 , that needs to be extracted until the threshold value of the inverter INV 1  is exceeded, is CV, and the current with which the electrical charges of the N-channel MOS transistor MN 1  are extracted is I, the electrical charge CV is extracted with the current I as from the rising of the first gate signal G 1  (voltage of the node n 1  is decreased). 
     If the electrical charge CV is extracted during the phase difference T until the rising of the second gate signal G 2  from the rising edge of the first gate signal G 1 , the I/2 component of the phase difference T is removed. That is, before rising of the input clock  2 , an output signal is output from the timing difference division circuit (inverter INV 1 ), that is the output rises. 
     So, the minimum capacitance value C which satisfies 
     
       
         
           CV/I&gt;T 
         
       
     
     represents the minimum value C min satisfying the I/2 component of the phase difference T, resulting in: 
     
       
           C  min= T·I/V.   
       
     
     Next, the voltage waveform N 1   f  of the node N 1  in case the value of the capacitance connected to the inner node N 1  is the maximum C max is explained. 
     During the phase difference T until the second gate signal G 2  rises from the rising edge of the first gate signal G 1 , only the N-channel MOS transistor MN 1 , to the gate of which the first gate signal G 1  is input, is turned on. The charges of the node N 1  are extracted by the N-channel MOS transistor MN 1 . Then, by the rising of the second gate signal G 2 , the charge of the node N 1  is extracted by the N-channel MOS transistors MN 1 , MN 2 . That is, the voltage of the node N 1  is lowered. When the potential of the node N 1  reaches the threshold value Vt, an output rises from the inverter INV 1 . 
     Assume that the electrical charge of the node N 1 , that needs to be extracted until the threshold value Vt of the inverter INV 1  is exceeded, is CV, and the current with which the electrical charge of the N-channel MOS transistors MN 1  and MN 2  is I, the electrical charge CV is extracted with the current I of the N-channel MOS transistor MN 1  during the phase difference T as from the rising of the first gate signal G 1  to the rising of the second input signal IN 2 , and thereafter with the current 2I. 
     The time during which the charge is extracted with the current 2I is an overlap period Tovp of the first and second gate signals G 1  and G 2 . If the charge CV is not completely extracted during this overlap period Tovp, the I/2 component of the phase difference T is depleted in the output of the timing difference division circuit. So, the maximum capacitance value C which satisfies: 
     
       
         ( CV−T·I )/2 I&lt;Tovp   
       
     
     is the maximum value C max satisfying the I/2 component of the phase difference T. That is: 
       C  max=(2 Tovp·+T ) I/V.   
     In an embodiment of the present invention, the size of C max can be adjusted by adjusting the length of the overlap period Tovp of the first and second gate signals G 1 , G 2  by the logic circuit L 1 . 
     Moreover, by connecting the sources and drains of the commonly to the P-channel MOS transistors MP 11  to MP 15  to the node N 1 , the variable capacitance can be constructed without the necessity of providing the MOS transistor switches (MN 11  to MN 14 ) and capacitors (CAP 11  to CAP 15 ) shown in FIG. 26 etc., thus reducing the chip area. 
     FIGS. 2 and 3 show a structure of an embodiment of the present invention. In the present embodiment, shown in FIGS. 2 and 3, the circuit for controlling the overlap of the input clocks is constructed using circuits of the same phase input and circuits of the different phase input using NAND devices. The inputs are four-phase clock inputs. Meanwhile, in FIGS. 2 and 3, the input signals are signals IN 1  and IN 2  having timing differential. The constant current sources  10   1 ,  10   2  are of an equal current value I. 
     In FIG. 2 a , by way of the logic circuit L 1 , the circuit for generating a first gate signal IN 1 A from the inputs IN 1 , IN 2  is a NAND circuit NAND 1 , whilst the circuit for generating a second gate signal IN 2 A from the inputs IN 1 , IN 2  is a NAND circuit NAND 2 . To the gate signal IN 2 A is connected a MOS capacitor device MP 2  to counterbalance the first gate signal IN 1 A and the load. 
     Referring to FIG. 2 b , the first and second gate signals IN 1 , IN 2  are high as from the falling edge of the signal IN 1  until the rising edge of the signal IN 2 , with the overlap period Tovp being 3tCK. The N-channel MOS transistors MN 1 , MN 2  are turned on to extract electrical charge at the current 2I. If, during this time period, the rising edge of the output signal of the inverter INV 1  is to exist, 
     
       
           CV/ 2 I&lt; 3 tCK   
       
     
     
       
           C  max= tCK· 6 I/V   
       
     
     where CV denotes electrical charge to be extracted until reaching the threshold value voltage of the inverter INV 1 . 
     Referring to FIG. 3 a,  the logic circuit L 1  includes a NAND circuit NAND 11 , as a circuit for generating the first gates signal IN 1 B from the first and second inputs IN 1 , IN 2  as inputs of different phases. The logic circuit L 1  also includes a NAND circuit NAND 12 , fed with the second input IN 2  and with a fixed high value as inputs, as a circuit for generating the second gate signal IN 2 B. To the second gate signal IN 2 B is connected a MOS capacitor device MP 2  for counterbalancing the first gate signal IN 1 B and the load. The NAND circuit NAND 13  is fed as input with the input IN 1  and with the ground potential to counterbalance the loads of the inputs  1  and  2 . 
     If the N-channel MOS transistor MN 1  is fired by the first gate signal IN 1 B and the electrical charge CV of the inner node N 1 , where C is the load capacitance of the inner node and V is the threshold value voltage Vt of the inverter, is extracted within tCK=T, the divided component of the I/2 component with the timing difference T ceases to exist in an output of the timing difference division circuit. So, the following holds: 
     
       
         
           CV/I&lt;tCK 
         
       
     
     
       
           C  min= tCK·I/V.   
       
     
     If, in the case of the different phase input, the N-channel MOS transistors MN 1 , MN 2  are turned ON during the overlap period Tovp of the first gate signal IN 1 B and the second gate signal IN 2 B to extract the electrical charge CV from the inner node N 1  with the current 2I, the divided component as the I/2 component, with the timing difference T, exists in the output of the timing difference division circuit. So, the following holds: 
     
       
         ( CV−tCK·I )/2 I&lt; 2 tCK   
       
     
     
       
           C  max&gt;( tCK· 5 I )/ Vt.   
       
     
     The capacitance value with which the timing difference division circuit is able to provide timing with the interior division ratio of ½ of the timing difference is 1:5 from the minimum value to the maximum value. This indicates marked improvement over the conventional value of 1:3 thereby enhancing the range of the operating frequency. 
     In the above-described embodiment, an interpolator in which the N-channel MOS transistors MN 1 , MN 2  are arranged in parallel with each other, is used in a discharge path of the inner node. Alternatively, the polarity may also be reversed using P-channel MOS transistors. In this case, the inner node N 1  is charged instead of being discharged by the first and second gate signals output from the logic circuit L 1  fed with the input signals IN 1  and IN 2 . 
     The above-described timing difference division circuit may be used with advantage in a timing difference division circuit in the clock control circuit shown in FIGS. 4 to  7  and  15  to  17 . Although four-phase clocks are used in the above-described embodiment, eight phase or sixteen phase signals, for example, may, of course, be used. 
     A wide variety of circuits may be formed by the combination of e.g., NAND circuits as the logic circuit L 1  used for generating gate signals. Alternatively, a circuit for producing one-shot signals may lengthen the overlap period. 
     Although the present invention has been described with reference to the above-described embodiments, it is to be noted that the present invention may comprise a variety of modifications that may be within the reach of those skilled in the art from the teaching of the invention as disclosed in the claims. 
     The meritorious effects of the present invention are summarized as follows. 
     According to the present invention, in which, in a timing difference division circuit (interpolator) for outputting a signal having delay time corresponding to the division by a preset interior dividing ratio of the timing difference of an input signal, there is provided a circuit for controlling the on/off time of a switch for controlling the signal rising and decay at the internal node, it is possible to enlarge the range of the value of the capacitance appended to the inner node thus increasing the operating range by a simplified logic circuit. 
     Moreover, according to the present invention, in which the capacitances and switches for controlling the connection of the capacitance to the inner node is removed by replacing the capacitances by MOS capacitors, it is possible to suppress or decrease the chip area. 
     It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith. 
     Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items might fall under the modifications aforementioned.