Abstract:
Provided is an apparatus and method for receiving signals in a communication system. A first processor inputs dc input messages through dc input nodes, respectively, generates one output message from the dc input messages using a predetermined operation scheme, and outputs the output message to dc output nodes. A corrector inputs output messages output from the dc output nodes through dv input nodes, corrects the input dv output messages using a predetermined correction value, and outputs the dv output messages corrected using the correction value to dv input nodes of a second processor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) AND CLAIM OF PRIORITY 
       [0001]    This application claims the benefit under 35 U.S.C. §119(a) of a Korean Patent Application filed in the Korean Intellectual Property Office on Jan. 30, 2007 and assigned Serial No. 2007-9491, the entire disclosure of which is hereby incorporated by reference. 
       TECHNICAL FIELD OF THE INVENTION 
       [0002]    The present invention relates to a communication system, and in particular, to an apparatus and method for receiving signals in a communication system. 
       BACKGROUND OF THE INVENTION 
       [0003]    Next-generation communication systems have evolved into a packet service communication system for transmitting burst packet data to a plurality of mobile stations. The packet service communication system has been designed to be suitable for high-capacity data transmission. Further, next-generation communication systems are positively considering the use of a Low Density Parity Check (LDPC) code, together with a turbo code, as a channel code. The LDPC code is known to have excellent performance gain for high-speed data transmission, and advantageously enhances data transmission reliability by effectively correcting errors caused by noises generated in a transmission channel. Examples of the next-generation communication systems positively considering the use of the LDPC code include the IEEE (Institute of Electrical and Electronics Engineers) 802.16e communication system, and the IEEE 802.11n communication system, etc. 
         [0004]    With reference to  FIG. 1 , a description will now be made regarding a structure of a signal transmission apparatus in a general communication system using a LDPC code. 
         [0005]      FIG. 1  is a block diagram illustrating a structure of a signal transmission apparatus in a general communication system using a LDPC code. 
         [0006]    Referring to  FIG. 1 , the signal transmission apparatus (e.g., one or more base stations) includes an encoder  111 , a modulator  113 , and a transmitter  115 . If information data to be transmitted by the signal transmission apparatus (i.e., an information vector s) is generated, the information vector s is delivered to the encoder  111 . The encoder  111  generates a codeword vector c (i.e., an LDPC codeword) by encoding the information vector s using a predetermined encoding scheme, and outputs the codeword vector c to the modulator  113 . The predetermined encoding scheme is herein an LDPC encoding scheme. The modulator  113  generates a modulation vector m by modulating the codeword vector c using a predetermined modulation scheme, and then outputs the modulation vector m to the transmitter  115 . The transmitter  115  inputs therein the modulation vector m output from the modulator  113 , performs transmission signal processing on the modulation vector m, and then transmits the resulting signal to a signal reception apparatus via an antenna ANT. 
         [0007]    Next, a description will be made regarding a structure of a signal reception apparatus in a general communication system using a LDPC code, with reference to  FIG. 2 . 
         [0008]      FIG. 2  is a block diagram illustrating a structure of a signal reception apparatus in a general communication system using a LDPC code. 
         [0009]    Referring to  FIG. 2 , the signal reception apparatus (e.g., a mobile station) includes a receiver  211 , a de-modulator  213 , and a decoder  215 . A signal transmitted by a signal transmission apparatus is received via an antenna ANT of the signal reception apparatus, and the received signal is delivered to the receiver  211 . The receiver  211  performs reception signal processing for the received signal in order to generate a reception vector r, and then outputs the reception vector r to the demodulator  213 . The demodulator  213  inputs therein the reception vector r output from the receiver  211 , generates a demodulation vector x by demodulating the reception vector r using a demodulation scheme corresponding to a modulation scheme used in the modulator  113  of the signal transmission apparatus, and then outputs the modulation vector x to the decoder  215 . The decoder  215  inputs therein the demodulation vector x output from the demodulator  213 , decodes the input demodulation vector x using a decoding scheme corresponding to an encoding scheme used in the encoder ill of the signal transmission apparatus, and then outputs the decoded demodulation vector x as a finally restored information vector S. For the decoding scheme (i.e., an LDPC decoding scheme), an iterative decoding algorithm based on a sum-product algorithm or based on a min-sum algorithm is widely used and the sum-product algorithm and the min-sum algorithm will be described below in detail. 
         [0010]    The LDPC code is a code defined by a parity check matrix in which most elements have a value of ‘0’, but a small minority of the other elements have a non-zero value, for example, a value of ‘1’. The LDPC code can be expressed using a bipartite graph that is expressed with variable nodes, check nodes, and edges connecting the variable nodes to the check nodes. 
         [0011]    The LDPC code can be decoded on the bipartite graph by using an iterative decoding algorithm based on a sum-product algorithm. The sum-product algorithm is a kind of a message passing algorithm in which messages are exchanged over the edges in the bipartite graph, and output messages are calculated and updated from messages input into the variable nodes or the check nodes. Since a decoder for decoding the LDPC code uses the iterative decoding algorithm based on the message passing algorithm, it is less complex than a decoder for decoding a turbo code, and can be easily implemented as a parallel processing decoder. 
         [0012]    Next, with reference to  FIG. 3 , a description will be made regarding a message passing operation in an arbitrary check node of a general decoder using an LDPC decoding scheme, hereinafter referred to as an ‘LDPC decoder’. 
         [0013]      FIG. 3  illustrates a message passing operation in an arbitrary check node of a general LDPC decoder. 
         [0014]    In  FIG. 3 , there are included a check node m  300  and a plurality of variable nodes  310 ,  320 ,  330 , and  340  connected to the check node m  300 . Further, T n′,m  indicates a message passed (or transferred) from the variable node n′  310  to the check node m  300 , and E n,m  indicates a message passed (or transferred) from the check node m  300  to the variable node n  330 . A set of all variable nodes connected to the check node m  300  will be defined as N(m). A set given by excluding the variable node n  330  from N(m) will be defined as N(m)\n. In this case, a message update rule based on the sum-product algorithm can be expressed as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           Sign 
                            
                           
                             ( 
                             
                               E 
                               
                                 n 
                                 , 
                                 m 
                               
                             
                             ) 
                           
                         
                         = 
                         
                           
                             ∏ 
                             
                               
                                 n 
                                 ′ 
                               
                               ∈ 
                               
                                 
                                   N 
                                    
                                   
                                     ( 
                                     m 
                                     ) 
                                   
                                 
                                  
                                 \n 
                               
                             
                           
                            
                           
                             Sign 
                              
                             
                               ( 
                               
                                 T 
                                 
                                   
                                     m 
                                     ′ 
                                   
                                   , 
                                   m 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         
                            
                           
                             E 
                             
                               n 
                               , 
                               m 
                             
                           
                            
                         
                         = 
                         
                           
                             Φ 
                             [ 
                             
                               
                                 ∑ 
                                 
                                   
                                     n 
                                     ′ 
                                   
                                   ∈ 
                                   
                                     
                                       N 
                                        
                                       
                                         ( 
                                         m 
                                         ) 
                                       
                                     
                                      
                                     \n 
                                   
                                 
                               
                                
                               
                                 Φ 
                                  
                                 
                                   ( 
                                   
                                      
                                     
                                       T 
                                       
                                         
                                           n 
                                           ′ 
                                         
                                         , 
                                         m 
                                       
                                     
                                      
                                   
                                   ) 
                                 
                               
                             
                             ] 
                           
                           . 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Eqn 
                     . 
                     
                         
                     
                      
                     1 
                   
                   ] 
                 
               
             
           
         
       
     
         [0015]    In Equation 1, Sign(E n,m ) indicates a sign of a message E n,m  and indicates a magnitude of the message |E n,m |. A function Φ(x) can be expressed as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     Φ 
                      
                     
                       ( 
                       x 
                       ) 
                     
                   
                   = 
                   
                     - 
                     
                       
                         log 
                          
                         
                           [ 
                           
                             tanh 
                              
                             
                               ( 
                               
                                 x 
                                 2 
                               
                               ) 
                             
                           
                           ] 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Eqn 
                     . 
                     
                         
                     
                      
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
         [0016]    A message update rule based on the min-sum algorithm can be expressed as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           Sign 
                            
                           
                             ( 
                             
                               E 
                               
                                 n 
                                 , 
                                 m 
                               
                             
                             ) 
                           
                         
                         = 
                         
                           
                             ∏ 
                             
                               
                                 n 
                                 ′ 
                               
                               ∈ 
                               
                                 
                                   N 
                                    
                                   
                                     ( 
                                     m 
                                     ) 
                                   
                                 
                                  
                                 \n 
                               
                             
                           
                            
                           
                             Sign 
                              
                             
                               ( 
                               
                                 T 
                                 
                                   
                                     n 
                                     ′ 
                                   
                                   , 
                                   m 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         
                            
                           
                             E 
                             
                               n 
                               , 
                               m 
                             
                           
                            
                         
                         = 
                         
                           
                             
                               min 
                               
                                 
                                   n 
                                   ′ 
                                 
                                 ∈ 
                                 
                                   
                                     N 
                                      
                                     
                                       ( 
                                       m 
                                       ) 
                                     
                                   
                                    
                                   
                                     \ 
                                      
                                     n 
                                   
                                 
                               
                             
                              
                             
                               { 
                               
                                  
                                 
                                   T 
                                   
                                     
                                       n 
                                       ′ 
                                     
                                     , 
                                     m 
                                   
                                 
                                  
                               
                               } 
                             
                           
                           = 
                           
                             
                                
                               
                                 T 
                                 
                                   
                                     n 
                                     0 
                                   
                                   , 
                                   m 
                                 
                               
                                
                             
                             . 
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Eqn 
                     . 
                     
                         
                     
                      
                     3 
                   
                   ] 
                 
               
             
           
         
       
     
         [0017]    In Equation 3, no can be rewritten as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     n 
                     0 
                   
                   = 
                   
                     
                       argmin 
                       
                         
                           n 
                           ′ 
                         
                         ∈ 
                         
                           
                             N 
                              
                             
                               ( 
                               m 
                               ) 
                             
                           
                            
                           
                             \ 
                              
                             n 
                           
                         
                       
                     
                      
                     
                       
                         { 
                         
                            
                           
                             T 
                             
                               
                                 n 
                                 ′ 
                               
                               , 
                               m 
                             
                           
                            
                         
                         } 
                       
                       . 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Eqn 
                     . 
                     
                         
                     
                      
                     4 
                   
                   ] 
                 
               
             
           
         
       
     
         [0018]    Although an input or output message of each node is used without an absolute sign of Equation 1, 3, or 4, a magnitude of the message can be expressed. 
         [0019]    Next, input/output message passing operations in an arbitrary check node and a variable node of an LDPC code generated in a general LDPC decoder will be described with reference to  FIGS. 4A and 4B . For convenience of explanation, a check node operation unit and a variable node operation unit will be separately described with reference to  FIGS. 4A and 4B . 
         [0020]      FIG. 4A  illustrates a check node operation unit of the general LDPC decoder. 
         [0021]    Referring to  FIG. 4A , the check node operation unit includes a first memory  400 , a check node processor  410 , and a second memory  420 . The first memory  400  stores messages to be input to the check node processor  410 , and the second memory  420  stores messages output from the check node processor  410 . The first memory  400  includes a plurality dc of sub-memories, e.g., sub-memory # 1  T n,m  ( 400 - 1 ) through sub-memory #d c            ( 400 - d   c ). The second memory  420  includes a plurality dc of sub-memories, e.g., sub-memory # 1  E n     1     ,m  ( 420 - 1 ) through sub-memory #d c            ( 420 - d   c ). 
         [0022]    A variable node operation unit of a general LDPC decoder will now be described with reference to  FIG. 4B . 
         [0023]      FIG. 4B  illustrates a variable node operation node of the general LDPC decoder. 
         [0024]    Referring to  FIG. 4B , the variable node operation unit includes a third memory  430 , a variable node processor  440 , and a fourth memory  450 . The third memory  430  stores messages to be input to the variable node processor  440 . The fourth memory  450  stores messages output from the variable node processor  440 . The third memory  430  includes a plurality d v  of sub-memories, e.g., sub-memory # 1  E n,m     1    ( 430 - 1 ) through sub-memory #d v            ( 430 - d   v ). The fourth memory  450  includes a plurality dv of sub-memories, e.g., sub-memory # 1  T n,m     1    ( 450 - 1 ) through sub-memory #d v            ( 450 - d   v ). 
         [0025]    On the assumption that an input degree of the check node processor  410  is dc in  FIGS. 4A and 4B , d c  input messages are stored in the sub-memory # 1  T n     1     ,m  ( 400 - 1 ) through sub-memory #d c            ( 400 - d   c ), respectively, and output messages corresponding to the dc input messages are stored in the sub-memory # 1  E n,m     1    ( 430 - 1 ) through sub-memory #d v            ( 430 - d   v ), respectively. 
         [0026]    As discussed above, when the sum-product algorithm is used for a check node operation, check node output messages E n     1     ,m  ( 420 - 1 ), E n     2     m  ( 420 - 2 ), E n     3     ,m  ( 420 - 3 ) and          ( 420 - d   c ) illustrated in  FIG. 4A  are calculated using Equation (1). The output message E n     1     ,m  ( 420 - 1 ) is calculated using the remaining d c - 1  messages except for the input message T n     1     ,m  ( 400 - 1 ) among the d c  input messages T n     1     ,m  ( 400 - 1 ), T n     2     ,m  ( 400 - 2 ), T n     3     ,m  ( 400 - 3 ) and          ( 400 - d   c ). The output message E n     2     ,m  ( 420 - 2 ) is calculated using the remaining d c - 1  messages except for the input message T n     2     ,m  ( 400 - 2 ) among the dc input messages T n     1,m    ( 400 - 1 ), T n     2     ,m  ( 400 - 2 ), T n     3     ,m  ( 400 - 3 ) and          ( 400 - d   c ). The output message E n     3     ,m  ( 420 - 3 ) is calculated using the remaining d c - 1  input messages except for the input message T n     3     ,m  ( 400 - 3 ) among the dc input messages T n     1     ,m  ( 400 - 1 ), T n     2     ,m  ( 400 - 2 ), T n     3     ,m  ( 400 - 3 ) and          ( 400 - d   c ) 
         [0027]    As such, the output messages E n     1     ,m  ( 420 - 1 ) , E n     2     ,m  ( 420 - 2 ), E n     3     ,m  ( 420 - 3 ) and          ( 420 - d   c ) calculated using Equation (1) generally have different values and are input to dc variable nodes n 1 , n 2 , n 3  and n d     c   , respectively. 
         [0028]    When the check node operation unit is implemented with hardware, the dc output messages are input to the dc variable nodes along a data path and thus have different values, increasing routing complexity and thus reducing a data rate. Therefore, there is a need for a node operation method capable of coping with the increase in routing complexity. 
       SUMMARY OF THE INVENTION 
       [0029]    An aspect of the present invention is to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the present invention is to provide an apparatus and a method for receiving a signal in a communication system using an LDPC code. 
         [0030]    Another aspect of the present invention is to provide an apparatus and a method for receiving a signal in a communication system using an LDPC code whereby routing complexity can be reduced. 
         [0031]    Further another aspect of the present invention is to provide an apparatus and method for receiving a signal in a communication system using an LDPC code whereby routing complexity can be reduced using a minimum value detector and a corrector. 
         [0032]    According to an aspect of the present invention, there is provided a method for receiving a signal in a signal reception apparatus of a communication system. The method includes inputting dc input messages through dc input nodes, respectively, at a first processor, generating one output message from the dc input messages using a predetermined operation scheme and outputting the output message to dc output nodes, at the first processor, inputting output messages output from the dc output nodes through dv input nodes and correcting the input dv output messages using a predetermined correction value, at a corrector, and outputting the dv output messages corrected using the correction value to dv input nodes of a second processor, at the corrector. 
         [0033]    According to another aspect of the present invention, there is provided a signal reception apparatus of a communication system. The signal reception apparatus includes a first processor for inputting therein dc input messages through dc input nodes, respectively, and generating one output message from the dc input messages using a predetermined operation scheme and outputting the output message to dc output nodes, and a corrector for inputting therein output messages output from the dc output nodes through dv input nodes, correcting the input dv output messages using a predetermined correction value, and outputting the dv output messages corrected using the correction value to dv input nodes of a second processor. 
         [0034]    Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0035]    For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
           [0036]      FIG. 1  is a block diagram illustrating a structure of a signal transmission apparatus in a general communication system using a Low Density Parity Check (LDPC) code; 
           [0037]      FIG. 2  is a block diagram illustrating a structure of a signal reception apparatus in a general communication system using a LDPC code; 
           [0038]      FIG. 3  illustrates a message passing operation in an arbitrary check node of a general LDPC decoder; 
           [0039]      FIG. 4A  illustrates a check node operation unit of the general LDPC decoder; 
           [0040]      FIG. 4B  illustrates a variable node operation node of the general LDPC decoder; 
           [0041]      FIG. 5A  illustrates a check node operation unit of an LDPC decoder according to a first exemplary embodiment of the present invention; 
           [0042]      FIG. 5B  illustrates a variable node operation unit of the LDPC decoder according to the first exemplary embodiment of the present invention; 
           [0043]      FIG. 6A  illustrates a check node operation unit of an LDPC decoder according to a second exemplary embodiment of the present invention; and 
           [0044]      FIG. 6B  illustrates a variable node operation unit of the LDPC decoder according to the second exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0045]      FIGS. 5   a  through  6   b,  discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged communication systems. 
         [0046]    The present invention suggests a method and apparatus for outputting a message from a check node to all variable nods connected to the check node in a communication system using a Low Density Parity Check (LDPC) code. The present invention also suggests a signal reception apparatus and method in which in order to reduce routing complexity during a check node operation required for message output, messages are input to a check node, a message having a minimum value among the messages is output using a predetermined operation method, e.g., a minimum value detection method, and the output message is corrected at each variable node, thereby decoding an LDPC code. 
         [0047]    First, input or output message passing operations at a check node and a variable node of an LDPC code generated by an LDPC decoder according to a first exemplary embodiment of the present invention will be described with reference to  FIGS. 5A and 5B . The LDPC decoder according to the first exemplary embodiment of the present invention includes a check node operation unit and a variable node operation unit. For convenience of explanation, the check node operation unit and the variable node operation unit will be separately described with reference to  FIGS. 5A and 5B . 
         [0048]      FIG. 5A  illustrates the check node operation unit of the LDPC decoder according to the first exemplary embodiment of the present invention. 
         [0049]    Referring to  FIG. 5A , the check node operation unit includes a first memory  500 , a check node processor  510 , and a second memory  520 . The first memory  500  stores messages to be input to the check node processor  510 . The second memory  520  stores messages output from the check node processor  510 . The first memory  500  includes a plurality dc of sub-memories, e.g., sub-memory # 1  T n     1     ,m  ( 500 - 1 ) through sub-memory #dc          ( 500 - d   c ). The second memory  520  includes a plurality dc of sub-memories, e.g., sub-memory # 1  E n     1     ,m  ( 520 - 1 ) through sub-memory #d c            ( 520 - d   c ). 
         [0050]    The check node processor  510  inputs therein d c  messages T n     1     ,m  ( 500 - 1 ), T n     2     ,m  ( 500 - 2 ) T n     3     ,m  ( 500 - 3 ) and          ( 500 - d   c ). The check node processor  510  outputs d c  messages E n     1     ,m  ( 520 - 1 ), E n     2     ,m  ( 520 - 2 ), E n     3     ,m  ( 520 - 3 ) and           ( 520 - d   c ). The dc messages output from the check node processor  510  have the same value. In other words, a relationship of E n     1     ,m =E n     2     ,m =E n     3     m = . . . =          can be established. 
         [0051]    The check node processor  510  outputs the same message for the dc input messages, thereby reducing its complexity. 
         [0052]    Next, input or output message passing operations in an arbitrary variable node of an LDPC decoder according to the first exemplary embodiment of the present invention will be described with reference to  FIG. 5B . 
         [0053]      FIG. 5B  illustrates the variable node operation unit of the LDPC decoder according to the first exemplary embodiment of the present invention. 
         [0054]    The variable node operation unit includes a third memory  530 , a corrector  540 , a fourth memory  550 , a variable node processor  560 , and a fifth memory  570 . The third memory  530  stores messages to be input to the corrector  540 , and the messages stored in the third memory  530  are the same as the messages stored in the second memory  520  illustrated in  FIG. 5A . The fourth memory  550  contains messages output from the corrector  540 , i.e., messages to be input to the variable node processor  560 . The fifth memory  570  stores messages output from the variable node processor  560 . 
         [0055]    The third memory  530  includes a plurality d v  of sub-memories, e.g., sub-memory # 1  E n,m   1  ( 530 - 1 ) through sub-memory #d v             ( 530 - d   v ). The fifth memory  570  includes a plurality d v  of sub-memories, e.g., sub-memory # 1  T n,m     1    ( 570 - 1 ) through sub-memory #d v             ( 570 - d   v ). 
         [0056]    The d v  messages E n,m     1    ( 530 - 1 ), E n,m     2    ( 530 - 2 ), E n,m     3    ( 530 - 3 ) and           ( 530 - d   v ) stored in the third memory  530  are input to the corrector  540 . The corrector  540  inputs a predetermined correction value to the output messages having the same value from the check node processor  510 , thereby outputting messages {tilde over (E)} n,m     1    ( 550 - 1 ), {tilde over (E)} n,m     2    ( 550 - 2 ), {tilde over (E)} n,m     3    ( 550 - 3 ) and           ( 550 - d   v ). The predetermined correction value is determined by a system. There may be a plurality of parameters of the correction value determined by the system, and parameter determination for the correction value will not be described due to its irrelevance to the present invention. The output messages {tilde over (E)} n,m     1    ( 550 - 1 ), {tilde over (E)} n,m     2    ( 550 - 2 ), {tilde over (E)} n,m     3    ( 550 - 3 ) and           ( 550 - d   v ) are input to the variable node processor  560 . The variable node processor  560  performs a variable node operation using the output messages, thereby outputting T n,m     1    ( 570 - 1 ) T n,m     2    ( 570 - 2 ), T n,m     3    ( 570 - 3 ) and          ( 570 - d   v ). 
         [0057]    While input or output message passing operations in an arbitrary check node and an arbitrary variable node of an LDPC code generated by the LDPC decoder according to the first exemplary embodiment of the present invention have been described with reference to  FIGS. 5A and 5B , input or output message passing operations at a check node and a variable node of an LDPC code generated by an LDPC decoder according to a second exemplary embodiment of the present invention will now be described with reference to  FIGS. 6A and 6B . The LDPC decoder according to the second exemplary embodiment of the present invention includes a check node operation unit and a variable node operation unit. For convenience of explanation, the check node operation unit and the variable node operation unit will be separately described with reference to  FIGS. 6A and 6B . Although a min-sum algorithm will be used by way of example in  FIGS. 6A and 6B , the present invention can also be realized using other algorithms than the min-sum algorithm. 
         [0058]      FIG. 6A  illustrates the check node operation unit of the LDPC decoder according to the second exemplary embodiment of the present invention. 
         [0059]    Referring to  FIG. 6A , the check node operation unit includes a first memory  600 , a minimum value detector  610 , and a second memory  620 . The first memory  600  stores messages to be input to the minimum value detector  610 . The second memory  620  stores messages output from the minimum value detector  610 . The first memory  600  includes a plurality dc of sub-memories, e.g., sub-memory # 1  T n     1     , m  ( 600 - 1 ) through sub-memory #d c            ( 600 - d   c ). The second memory  620  includes a plurality dc of sub-memories, e.g., sub-memory # 1  E n     1     ,m  ( 620 - 1 ) through sub-memory #d c            ( 620 - d   c ). 
         [0060]    The minimum value detector  610  inputs therein dc messages T n     1     ,m  ( 600 - 1 ), T n     2     ,m  ( 600 - 2 ) T n     3     ,m  ( 600 - 3 ) and          ( 600 - d   c ), and detects a minimum value from among the input messages. A value output from the minimum value detector  610  is copied into dc values that are equal to one another, thereby outputting messages E n     1     ,m  ( 620 - 1 ), E n     2     ,m  ( 620 - 2 ), E n     3     ,m  ( 620 - 3 ) and          ( 620 - d   c ). 
         [0061]    Next, input or output message passing operations in an arbitrary variable node of the LDPC decoder according to the second exemplary embodiment of the present invention will be described with reference to  FIG. 6B . 
         [0062]      FIG. 6B  illustrates the variable node operation unit of the LDPC decoder according to the second exemplary embodiment of the present invention. 
         [0063]    Referring to  FIG. 6B , the variable node operation unit includes a third memory  630 , a corrector  640 , a fourth memory  650 , a variable node processor  660 , and a fifth memory  670 . The third memory  630  stores messages to be input to the corrector  640 , and the fourth memory  650  contains messages output from the corrector  640 , i.e., messages to be input to the variable node processor  660 . The fifth memory  670  stores messages output from the variable node processor  660 . 
         [0064]    The third memory  630  includes a plurality d v  of sub-memories, e.g., sub-memories # 1  E n,m     1    ( 630 - 1 ) through #d v            ( 630 - d   v ). The fourth memory  650  includes a plurality d v  of sub-memories, e.g., sub-memories # 1  {tilde over (E)} n,m     1    ( 650 - 1 ) through #d v            ( 650 - d   v ). The fifth memory  670  includes a plurality d v  of sub-memories, e.g., sub-memories # 1  T n,m     1    ( 670 - 1 ) through #d v            ( 670 - d   v ). 
         [0065]    The corrector  640  performs correction by subtracting a predetermined correction value from the dv messages E n,m     1    ( 630 - 1 ), E n,m     2    ( 630 - 2 ), E n,m     3    ( 630 - 3 ) and          ( 630 - d   v ). The correction value is predetermined by a system, and it is assumed that correction is performed by subtraction of a constant δ in the present invention. The corrector  640  outputs corrected values {tilde over (E)} n,m     1    ( 650 - 1 ), {tilde over (E)} n,m     2    ( 650 - 2 ), {tilde over (E)} n,m     3    ( 650 - 3 ) and          ( 650 - d   v ). The variable node processor  660  inputs therein the corrected values {tilde over (E)} n,m     1    ( 650 - 1 ), {tilde over (E)} n,m     2    ( 650 - 2 ), {tilde over (E)} n,m     3    ( 650 - 3 ) and          ( 650 - d   v ) and performs a operation, thereby outputting T n,m     1    ( 670 - 1 ), T n,m     2    ( 670 - 2 ), T n,m     3    ( 670 - 3 ) and          ( 670 - d   v ). 
         [0066]    For example, it is assumed that d c  is 4 and input message magnitudes are T n     1     ,m =5, T n     2     ,m =9, T n     3     ,m =3, and T n     4     ,m =7 for description with reference to  FIGS. 6A and 6B . When a min-product algorithm is used according to prior art, the output message E n     1     ,m  is a minimum value of 3 among T n     2     ,m =9, T n     3     ,m =3, and T n     4     ,m =7 except for T n     1     ,m =5. However, when a min-product algorithm is used according to the present invention, a minimum value of 3 among T n     1     ,m =5, T n     2     ,m =9, T n     3     ,m =3, and T n     4     ,m =7 is detected and is then copied into 4 (=dc) values, thereby outputting E n     1     ,m =E n     2     ,m =E n     3     ,m =E n     4     ,m =3. 
         [0067]    It is assumed that the degree of a variable node n is d v =3 and messages input to the corrector  640  are E n,m     1   =8, E n,m     2   =5, and E n,m     3   =6. If a correction value δ used in the corrector  640  is set to 2, the corrector  640  outputs {tilde over (E)} n,m     1   =6, {tilde over (E)} n,m     2   =3, and {tilde over (E)} n,m     3   =4 and these output values are input to the variable node processor  660 . 
         [0068]    As is apparent from the foregoing description, the present invention can reduce the routing complexity of a decoder by outputting the same message to each variable node during a check node operation and performing correction with a predetermined correction value at a variable node during decoding of an LDPC code in a communication system. 
         [0069]    Although the present disclosure has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.