Abstract:
A method and apparatus for reducing offset errors in a variable gain circuit is offered. A first programmable gain amplifier is located in a feedforward signal path and a second programmable amplifier is connected in feedback with the first programmable gain amplifier. Each programmable gain amplifier has a separate gain control circuit so that the gain of each programmable gain amplifier can be independently controlled.

Description:
RELATED APPLICATION 
     This application claims the benefit of the fling date, under 35 U.S.C. §119(e), of provisional application Ser. No. 60/137,567 filed Jun. 4, 1999. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to variable gain circuits and, more particularly, to an improved circuit and method for reducing offset errors in a variable gain circuit. 
     BACKGROUND 
     A charge-couple device (CCD) is the sensor of choice in modern imaging to convert photons into electrons, hence enabling the use of electronics for image processing. FIG. 1 shows typical analog front-end building blocks for a CCD signal processing channel. The CCD input signal  100  is received by a correlated double sampling circuit (CDS)  102  whose function is to extract the image content from the CCD signal  100  and remove an unwanted correlated noise component. The output of the CDS  102  is amplified by a programmable gain amplifier (PGA)  104  before it gets converted to digital data by an analog-to-digital converter (ADC)  106 . The gain of the PGA can be programmed by providing a gain input to the gain control circuit which controls the gain in the PGA. 
     In reality, the circuit building blocks have offset, and such offset can reduce the dynamic range of the processing channel. In particular, an offset input to the PGA can get amplified by the PGA by an amount of the gain of the PGA, and hence seriously reduce the useful dynamic range of the PGA output and ADC. Such an offset can come from the CCD signal, the CDS, or can be the input referred offset of the PGA. For example, an offset of 10 mV input into a PGA with a gain of 50×, yields an output referred offset at the output of the PGA of 0.5V. This reduces the dynamic range of the PGA output and ADC by 0.5V, which is not acceptable in most integrated circuit design applications. 
     In order to address this problem, an offset correction is typically used. One way to provide an offset correction is to integrate the output of the PGA and subtract the accumulated error from the input of the PGA in a feedback fashion. The feedback will adjust the input of the PGA such that the output of the PGA is equal to the system&#39;s “zero” reference. This scheme is shown in FIG.  2 . In this figure, INT  200  refers to an integrator. 
     One problem with the scheme of FIG. 2 is that the time constant of the loop depends on the gain of the PGA  104 . To keep the feedback loop stable and the noise of the “zero” reference low, it is preferable to keep the bandwidth of the loop low and constant, thereby keeping the loop gain constant with varying PGA gain. This can be accomplished by inserting another PGA in the feedback path with a reciprocal gain characteristic of the PGA in the forward path. This is called a reverse PGA (RPGA)  300 , which is shown in FIG.  3 . The gain characteristics of PGA and RPGA and the loop gain are shown in FIG.  4 . In FIG. 4, shown are the gain of the RPGA, the gain of the PGA, and the loop gain, each with respect to the gain input provided to the gain control circuit. In terms of the dynamics of the loop, the order of RPGA  300  and INT  200  in the feedback path does not matter, but it does have circuit level consequences that usually limit the circuit to having INT  200  on the output side of the PGA  104 . 
     One problem with the modified scheme of FIG. 3 is that any offset at the input side of the PGA  104  gets gained back to the input of the RPGA  300  or the output of the INT  200 . This offset can consist of the CCD&#39;s offset, the CDS&#39; offset, or the input referred offset of the PGA, and can be substantial. Although this offset does not directly affect the dynamic range of the processing channel itself (CDS, PGA, and ADC), it severely limits the operation of the RPGA and INT when the gain of the PGA is high. Again, an offset of 10 mV with a 50× gain in the PGA gets referred back to the input of RPGA as 0.5V. Under a large offset condition, the offset correction scheme of FIG. 3 fails to operate due to the limited headroom range of the RPGA  300  and INT  200 . 
     SUMMARY 
     One embodiment of the invention is directed to a variable gain circuit that includes a first PGA in a feedforward signal path and a second PGA connected in feedback with the first PGA. The variable gain circuit need not be used in an image sensor application (e.g., CCD) as disclosed herein, but may be any variable gain circuit in which it is desired to reduce offset errors of the circuit. An embodiment of the invention includes circuitry for controlling the gain of the first PGA and controlling the gain of the second PGA, independently of one another. 
     Another embodiment of the invention is directed to a method for correcting offset errors in a variable gain circuit including a first PGA and a second PGA connected in feedback with the first PGA. The method includes the steps of: controlling a gain of the first PGA, controlling a gain of the second PGA independently from the gain control of the first PGA. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a CCD signal processing channel according to the prior art; 
     FIG. 2 shows a block diagram of a CCD signal processing channel with offset correction according to the prior art; 
     FIG. 3 shows a block diagram of a CCD signal processing channel with offset correction and constant loop gain according to the prior art; 
     FIG. 4 shows the PGA, RPGA, and loop gain characteristic of the circuit shown in FIG. 3 according to the prior art; 
     FIG. 5 shows a block diagram of a CCD signal processing channel with modified gain control; 
     FIG. 6 shows the PGA, RPGA, and loop gain characteristic of one embodiment of the circuit in FIG. 5; and 
     FIG. 7 shows the PGA, RPGA, and loop gain characteristic of one embodiment of the circuit of FIG.  5 . 
    
    
     DETAILED DESCRIPTION 
     One embodiment of the invention is shown in FIG.  5 . Shown is a variable gain circuit with which the method and circuit of the invention may be used. The variable gain circuit may include a first PGA  104  in a feedforward signal path and a second PGA  300  connected in feedback with the first PGA  104 , as shown in FIG.  5 . The feedback path also may include an integrator (INT)  200 . 
     The embodiment contemplates controlling the gain of the first PGA  104  and controlling the gain of the second PGA  300 , independently of one another. This is illustrated in FIG. 5 where a first gain control circuit  500  controls the gain of the first PGA  104  and a second gain control circuit  502  controls the gain of the second PGA  300 . The two gains may be completely unrelated or may be related, but importantly, each can be controlled independently of the other. 
     By separating the gain control of the PGA and RPGA the embodiment partially decouples the reciprocal relationship of the PGA and RPGA gains. By separating the gain relationship the embodiment also separates the relationship between noise and offset between which circuit designers were often forced to choose. More flexibility is provided to alter the RPGA and/or loop gains so that more precise control can be exerted over the circuit behavior. 
     A specific embodiment of the invention shown as a CCD image sensor in FIG. 5 shows the variable gain circuit with which the invention is used. It should be appreciated that the invention is not so limited and that the invention can be used with any variable gain circuit for which it is desired to reduce offset errors. This invention can be applied to processing of other types of signals, and is not limited to the processing of a CCD signal. 
     The circuit employs one gain control circuit  500  to control the gain of the PGA  104  and a separate gain control circuit  502  to independently control the gain of the RPGA  300 . This allows the gain characteristic of the RPGA  300  to be set independently of that of the PGA  104 . 
     One example is shown in FIG. 6 in which the gain of the RPGA, the gain of the PGA, and the loop gain are each shown with respect to the gain input provided to the gain control circuits. In this example, the reciprocal slope of the RPGA is set to be lower than the slope of the PGA so that the loop gain has a positive slope as the gain input is increased. The benefit of doing this is so that one can select the loop gain to be low at low gain input to keep the noise of the loop low, and then set the loop gain at high gain high to be higher to increase the offset correction range in the loop. A low loop gain is important for noise since it lowers the bandwidth of the loop; hence more noise gets rejected. On the other hand, a high loop gain is important for the offset correction range since it allows more input referred offset to be corrected for the same headroom in the RPGA and INT. 
     FIG. 7 shows another example using the modified gain control scheme of FIG.  5 . In this example, the gain of the RPGA has the same slope as FIG. 4, but it clips to a higher gain limit. Again, the result is that the loop gain ends up at a higher gain than in the FIG. 4 example, and the offset correction range can be increased. For both the examples of FIGS. 6 and 7, the loop gain at low gain is at the same level as that of FIG. 4 (low noise), but the loop gain at high gain is higher than that of FIG. 4, and therefore, it can handle more input referred offset. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.