Abstract:
A fabrication method for an inter-metal dielectric layer is applicable to multi-level interconnects. A substrate is provided with metal lines formed thereon. A first (fluorinated silicon glass) FSG layer with low fluorine content is then formed on the substrate, followed by forming a biased-clamped FSG layer on the first FSG layer. A second FSG layer with low fluorine content is formed on the biased-clamped layer, prior to forming an oxide cap layer on the second FSG layer. The oxide cap layer is planarized until the oxide cap layer is level with the second FSG layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 89106031, filed Mar. 13, 2000. 
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to fabrication method for a semiconductor device. Particularly, the invention relates to a method of fabricating an inter-metal dielectric (IMD) layer that is applicable to multilevel interconnects. 
     2. Description of Related Art 
     In an integrated circuit with two or more levels of interconnects, an inter-metal dielectric (IMD) layer must be placed between the levels for an isolation purpose. Generally, this dielectric layer needs to satisfy the following: its good film&#39;s reliability and mechanical stability, low water absorption, and ease for integration, etc. A typical material for the IMD layer includes silicon oxide that has a dielectric constant of about 4. Alternatively, fluorinated silicate glass (FSG) is used to make the IMD layer, for the reason that FSG has a lower dielectric constant of about 3.5 as compared to undoped silicate glass (USG). With a lower dielectric constant, it is desirable for the IMD layer to reduce the RC time delay of the interconnect metallization. Thus, in terms of process simplicity and integrity, FSG is a better choice among other lower dielectric constant materials for making a low dielectric layer. 
     FIG.  1 A and FIG. 1B are schematic, cross-sectional diagrams illustrating a conventional fabrication method for an IMD layer. Referring to FIG. 1A, a plurality of metal lines  102  are formed on a substrate  100 . A gap-filled FSG layer  106  with turning on bias power and clamped the wafer by electrostatic chuck (ESC) is formed on the substrate  100  by high-density plasma chemical vapor deposition (HDPCVD), and it fills the gap between the metal lines  102 . Prior to the gap-fill FSG layer, an USG  104  normally is introduced, preventing the metal line from being attacked by fluorine. Then, a cap layer  108  is formed on the gap-fill FSG layer  106 , wherein the cap layer  108  is made of oxide by plasma enhanced chemical vapor deposition (PECVD). A chemical mechanical polishing (CMP) process is subsequently performed to planarize the cap layer  108 , as shown in FIG.  1 B. 
     On the substrate  100 , the metal lines  102  are usually distributed in a conductive line region both with dense and loose areas, respectively. As a result, a large step height difference exists between the gap-fill FSG layer  106  on the dense conductive line region  102   a  and that on the loose conductive line region  102   b , after the biased-clamped FSG layer  106  and the cap layer  108  being formed. Thus, it is difficult to control a polishing stop for chemical mechanical polishing (CMP), and over-polishing easily arises. As a result, the gap-fill FSG layer  106  may be exposed, probably resulting in the instability of fluorine. Intrinsically, the gap-fill FSG layer exhibits a chemically or physically hydrophilic behavior. Therefore, the gap-fill FSG layer  106  easily absorbs moisture when the gap-fill FSG layer  106  is in contact with CMP slurry. The absorbed moisture and/or solvent certainly increases the dielectric constant of the IMD layer and can cause further problems when the IMD layer is exposed to a thermal process, such as an anneal process. After high temperature anneal processes, the moisture would be absorbed to result in a severe blister if the out gas is sealed in subsequent deposition processes. 
     Furthermore, fluorine is known as a reactive chemical species, as it can produce a rigorous chemical reaction to produce HF that is a more reactive intermediate. HF can result in metal corrosion, oxide degradation, peeling at the metal/IMD layer interface in subsequent processes when a metal plug is formed. Therefore, the FSG layers with high fluorine content can lead to an instability of processes, which degrades device reliability. 
     SUMMARY OF THE INVENTION 
     The invention provides a fabrication method for an inter-metal dielectric layer applicable to multi-level interconnects. A first liner layer is formed, followed by depositing a dielectric layer on the first liner layer. A second liner layer is then formed on the dielectric layer, while a cap layer is formed on the second liner layer. A planarization process is performed on the cap layer until the second liner layer is exposed. 
     As embodied and broadly described herein, the invention provides a fabrication method for an IMD layer applicable to a semiconductor process. A substrate is provided with a metal layer formed thereon. A gap-fill fluorinated silicon glass (FSG) layer is formed on the substrate and covers the metal layer. A FSG layer with low fluorine content is then formed on the gap-fill FSG layer, follows by forming a planarized oxide layer on the oxide cap layer. The method prevents a direct contact between the CMP slurry and the gap-fill FSG layer, to result in metal corrosion, peeling, as well as an increase of dielectric constant. 
     According to the present invention, an additional FSG layer with low fluorine content can be formed on the substrate prior to forming the gap-fill FSG layer. The FSG layer with low fluorine content can serve as a liner to provide a better adhesion between the gap-fill FSG layer and the metal layer, to prevent a metal corrosion, and to provide a lower dielectric constant than that of a conventional undoped silicon glass (USG) layer. Since the gap-fill FSG layer with higher fluorine content is protected by two FSG layers with low fluorine content, the surface of the gap-filled FSG layer is not exposed. As a result, this prevents the metal corrosion, degradation of the oxide, peeling issue at a metal/IMD interface. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIG.  1 A and FIG. 1B are schematic, cross-sectional diagrams illustrating a conventional fabrication method for an IMD layer; 
     FIG.  2 A through FIG. 2C are schematic, cross-sectional diagrams illustrating a fabrication method for an IMD layer according to one preferred embodiment of this invention; and 
     FIG. 3 is a graph showing a relationship between the fluorine content and the dielectric constant. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Description is made with reference to FIGS. 2A through 2C, while FIG. 3 is incorporated as an experimental result showing the relationship between the fluorine content and the dielectric constant. 
     Referring to FIG. 2A, a plurality of metal lines  202  are formed on a substrate  200 . The metal lines  202  are distributed in a dense conductive line region  202   a  having a high-density distribution and a loose conductive line region  202   b  having a low-density distribution. A first liner layer  204  is formed on the substrate  200  to cover the metal lines  202  so as to prevent the metal lines  202  from corrosion, with improving an adhesion between the metal lines  202  and a dielectric layer  206  which is formed subsequently. 
     The first liner layer  204  is preferably made of fluorinated silicon glass (FSG) layer with a low fluorine content. The method for forming the first liner layer  204  includes high-density plasma chemical vapor deposition (HDPCVD), while the method uses a dopant source comprising SiH 4  and SiF 4 , with a preferred fluorine content of about 4-7% of fluorine atoms in the dopant source. The first liner layer  204  is formed to have a thickness of about 500-1500 angstroms. 
     A dielectric layer  206  is formed on the first liner layer  204  and fills gaps between the metal lines  202 . The dielectric layer  206  is preferably formed by HDPCVD and is made of a biased-clamped FSG layer with high gap-filled capability via simultaneously sputtering and deposition process. 
     Referring to FIG. 2B, a second liner layer  208  is formed on the dielectric layer  206 . The second liner layer  208  is made of a FSG layer with low fluorine content. The second liner layer  208  in this case is made of the same material as that of the first liner layer  204 , therefore they possess the same fluorine content of about 4-7% of fluorine atoms in a dopant mixture comprising SiH 4  and SiF 4 . Also, the second liner layer  208  has a thickness of about 500-1500 angstroms. Since the liner layers  204  and  208  both possess a lower fluorine content than the dielectric  206 , the liner layers  204  and  208  provide a relative chemical inertness in terms of fewer reactive fluorine atoms. 
     Furthermore, a cap layer  210  is formed on the second liner layer  208  to complete the fabrication of the IMD layer. The cap layer  210  can be made of any dielectric material having a low dielectric constant (k), but it is preferably made of oxide by plasma enhanced chemical vapor deposition (PECVD). 
     Referring to FIG. 2C, a chemical mechanical polishing (CMP) process is performed to planarize the cap layer  210  until a top surface of the cap layer  210  is level with the second liner layer  208 . Since the second liner layer  208  exhibit a relatively weak hydrophilic behavior due to a low fluorine content, the second liner layer  208  isolates the CMP slurry from the dielectric layer  206 . This eventually prevents a metal corrosion, peeling, as well as an increase of dielectric constant. 
     Since the first liner layer  204  and the second liner layer  208  are more inert due to a low content of fluorine atoms known to be reactive with metals and other elements, it imply that the liner layers  204  and  208  formed as such are chemically and thermally more stable. In addition, the first liner layer  204  also has a lower dielectric constant (about 3.7) as compared to the conventional USG layer (about 4.1). 
     Referring to FIG. 3, the illustrated experimental result shows that a dielectric constant of a FSG layer is related to a HF ratio (shown as SiH 4 /(SiH 4 +SiF 4 )%) in its dopant source. From the diagram, it is seen that the FSG layers in this case all have a low dielectric constant as compared to other conventional dielectric materials, while the fluorine content of the FSG layer is directly related to the HF ratio in its dopant source. 
     According to the present invention, the overall dielectric constant of the IMD layer remains low even though it includes the FSG layer with low fluorine content, since such FSG layer has a slightly higher dielectric constant (about 3.7) than that of the conventional FSG layer (about 3.5). Therefore, the dielectric constant of the IMD layer is not significantly affected, whereas the IMD layer formed as such is free from corrosion problems caused by fluorine atoms. 
     Summarizing the above, it is understood that a first liner layer with low fluorine content is formed on the substrate prior to forming the dielectric layer. The first liner layer with low fluorine content provides a better adhesion between the dielectric layer and the metal lines, while it prevents the metal lines from being corroded. Also, the first liner has a lower dielectric constant than that of a conventional USG layer. A second liner layer with low fluorine content is formed on the dielectric layer. This prevent a direct contact between the CMP slurry and the dielectric layer, which results formation of HF acid and metal corrosion, after CMP is performed to planarize the cap layer. 
     Since the biased-clamped FSG layer is protected between two FSG layers both with low fluorine content, the IMD layer as a whole exhibits a relative chemical inertness, said to be a very weak hydrophilic behavior. As a result, the present method prevents the metal corrosion, degradation of the oxide, peeling issue at a metal/IMD interface. 
     Although the method described above is embodied with reference to the multilevel interconnect process, the method are equally applicable to other processes such as formation of metal contact, dual damascene process, or deposition of a dielectric layer between the conductive lines or devices. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.