Abstract:
An interleaved auto-zero analog-to-digital converter includes chopper comparators for comparing an analog input signal to predetermined voltage values. An additional chopper comparator is included for performing the comparison function of a chopper comparator undergoing an auto zero operation.

Description:
FIELD OF THE INVENTION 
     The present invention relates to an analog-to-digital converter which converts an analog signal to a digital signal, and more particularly, an IAZ (Interleaved Auto-Zero) analog-to-digital converter. 
     BACKGROUND OF THE INVENTION 
     A parallel analog-to-digital converter comprises a plurality of comparators for comparing an analog signal with an analog reference voltage, and an encoder for converting the signals output from the comparators to a digital signal. 
     The parallel analog-to-digital converter is superior to other types of analog-to-digital converters in terms of the analog-to-digital conversion speed. FIG. 1 shows a first conventional parallel analog-to-digital converter which produces two output bits. Four resistors R are connected in series between a high-potential reference voltage VRH and a low-potential reference voltage VRL. The resistance value of the resistor at each end is set to one-half that of the other resistor. 
     Each of the nodes among the resistors is connected to one of two input terminals of each of three comparators CM 1  to CM 3 . Reference voltages VR 1  to VR 3  (which are obtained by division of the voltage difference between the reference voltages VRH and VRL by the resistances of the resistors R) are input, respectively, to the comparators CM 1  to CM 3 . An analog input signal Vin is input to the other input terminal of each of the comparators CM 1  to CM 3 . The comparators CM 1  to CM 3  compare, respectively, the reference voltages VR 1  to VR 3  with the analog input signal Vin. When the analog input signal Vin has a potential higher than the corresponding reference voltage VRl to VR 3 , the comparators CM 1  to CM 3  output, respectively, high-level output signals SG 1  to SG 3 . In contrast, when the analog input signal Vin has a potential lower than the corresponding reference voltage VR 1  to VR 3 , the comparators CM 1  to CM 3  output, respectively, low-level output signals SG 1  to SG 3 . 
     If the analog input signal Vin has a potential higher than the reference voltage VR 2  and a potential lower than the reference voltage VR 3 , the comparators CM 1  and CM 2  output the output signals SG 1  and SG 2  high, and the comparator CM 3  outputs the output signal SG 3  low. The output signals SG 1  to SG 3  form a thermometer code. 
     An encoder  3  receives the signals SG 1  to SG 3  and outputs two bits of digital output signals D 0 , D 1 . A control circuit  4  controls the timing of the comparators CM 1  to CM 3  and the encoder  3 . 
     To ensure the accuracy of conversion regardless of a variation in the characteristics of the underlying transistors of the circuit, the comparators CM 1  to CM 3  preferably comprise, respectively, chopper type comparators. In the case of a CMOS comparator, an input offset voltage varies from comparator to comparator because of a variation in the characteristics of the MOS transistors. Such comparators produces an insufficiently accurate comparison result because of the variance in the input offset voltage. 
     FIG. 2 is a circuit diagram of the chopper type comparator. The input terminals, which receive the analog input signal Vin and the reference voltage VR, are connected to a node N 1  (first terminal of a capacitor  1 ) via switching circuits SW 1  and SW 2 . The switching circuits SW 1  and SW 2  are turned on in response to the control signals C 1  and /CZ high. The second terminal of the capacitor  1  (a node N 2 ) is connected to an input terminal of an inverter circuit  2   a . Input and output terminals of the inverter circuit  2   a  are connected to each other via a switching circuit SW 3 . The switching circuit SW 3  is turned on in response to the control signal CZ high. 
     In an auto-zero operation, the input and output terminals of the inverter circuit  2   a  are reset to a threshold value of the inverter circuit  2   a . The output terminal of the inverter circuit  2   a  is connected to an input terminal of an inverter circuit  2   c  via an inverter circuit  2   b  and a switching circuit SW 4 . The switching circuit SW 4  is turned on in response to the control signal /CF high. The signal output from the inverter circuit  2   c  is inverted by an inverter circuit  2   e  and output as a signal OUT. Further, the signal output from the inverter circuit  2   c  is fed back to the inverter circuit  2   c  via an inverter circuit  2   d  and a switching circuit SW 5 . The switching circuit SW 5  is turned on in response to the control signal CF high. 
     The operation of the chopper type comparator will be described with reference to FIG.  3 . First, when the control signal C 1  goes high, and the control signal /CZ goes low, through the auto-zero operation, the node N 2  is reset to the threshold value of the inverter circuit  2   a , so that a charging current flows into the capacitor  1 , thereby increasing the potential of the node N 1  to the reference voltage VR. Subsequently, when the control signal C 1  goes low, and the control signals /CZ and /CF go high, the analog input signal Vin is compared with the reference voltage VR. If the analog input signal Vin has a potential higher than the reference voltage VR, the potential of the node N 2  becomes higher than the threshold value of the inverter circuit  2   a  as a result of capacitive coupling of the capacitor  1 . In contrast, if the potential of the analog input signal Vin is lower than the reference voltage VR, the potential of the node N 2  becomes lower than the threshold value of the inverter circuit  2   a . Since the switching circuit SW 4  is turned on at this time, the signal output from the inverter circuit  2   a  is provided to the inverter circuit  2   c  via the inverter circuit  2   b  and the switching circuit SW 4 . The signal output from the inverter circuit  2   c  is output as the signal OUT via the inverter circuit  2   e.    
     Next, when the control signal C 1  goes high again, and the control signals /CZ and /CF go low, the potential of the node N 1  is reset to the reference voltage VR. Through the auto-zero operation performed by the inverter circuit  2   a , the potential of the node N 2  is reset to the threshold value of the inverter circuit  2   a . At this time, the switching circuit SW 5  is turned on, so that the inverter circuits  2   c  and  2   d  form a latch circuit which latches the signal OUT. 
     The chopper type comparator alternately performs the auto-zero operation and the comparing operation. Accordingly, one-half of the time required for the converting operation is spent on the auto-zero operation, thereby decreasing the conversion speed. Increasing the frequencies of the control signals C 1 , CZ, /CZ, CF, and /CF makes it difficult to perform the auto-zero operation and the comparing operation. Accordingly, it is not easy to increase the conversion speed of analog-to-digital conversion by increasing the frequencies of the control signals C 1 , CZ, /CZ, CF, and /CF. 
     If the number of comparators is increased in order to increase the number of bits of the digital output signal, noise is apt to arise in the reference voltage VR, the analog input signal Vin, and the power source which causes erroneous operation of the comparator. At the time of the auto-zero operation a charge/discharge current simultaneously flows between the reference voltage VR and the capacitor C 1 , and the input and output terminals of the inverter circuit  2   a  are concurrently reset to the threshold value. Consequently, a through current simultaneously flows through the inverter circuits  2   a . Furthermore, at the time of the comparing operation, a charge/discharge current simultaneously flows between the analog input signal Vin and of each of the capacitors  1 . 
     To increase the conversion speed of the chopper type comparator, a technique of controlling the control signals C 1 , CZ, /CZ, CF, and /CF at the timing shown in FIG. 4 has been proposed. More specifically, after the auto-zero operation, the control signals C 1 , CZ, and /CZ are maintained in the state of a comparing operation, and the control signals CF and /CF are inverted several times to thereby sample, e.g., analog input signals VA and VB. As a result, the comparing operation is performed several times on the basis of one auto-zero operation. This is because the comparing operation can be performed several times until the electric charge stored in the capacitor  1  during the auto-zero operation discharges completely. The ratio of the time required for the comparing operation to the time required for the auto-zero operation is increased, the conversion speed is increased. 
     However, there still remains the need for separate time required by all the comparators to simultaneously perform the auto-zero operation, and the noise caused at the time of the auto-zero operation is not prevented. Furthermore, the number of times of the comparing operation is limited. 
     Japanese Patent Application Laid-Open No. 8-293795 describes an IAZ (Interleaved Auto-Zero) analog-to-digital converter having four chopper type comparators which output e.g., digital output signals D 1  and D 0 . The four comparators are selected in turn one at a time and caused to perform the auto-zero operation, while the comparison operation is performed by each of the other three comparators. Each comparator performs the comparing operation several times on the basis of one auto-zero operation. Since the analog-to-digital converter performs the auto-zero operation in parallel with the comparing operation, the operating speed is increased. Since the comparators do not all perform the auto-zero operations simultaneously, the noise resulting from the auto-zero operation is suppressed. 
     However, in the IAZ analog-to-digital converter, switching noise, which occurs when each of the comparators proceeds from the comparing operation to the auto-zero operation, causes an error in the comparing operation performed immediately before auto-zero operation. Furthermore, switching noise, which occurs when each of the comparators proceeds from the auto-zero operation to the comparing operation, causes an error in the comparing operation performed immediately after the auto-zero operation. Furthermore, when the comparators each proceed to the auto-zero operation from the comparing operation, the comparators may fail to latch and output the result of the comparison performed immediately before the auto-zero operation. Further, the limitation on the response speed of the comparator itself with respect to the switching from the reference voltage to the analog input signal does not provides an accurate comparison result obtained by the comparing operation immediately after the auto-zero operation. These problems degrade the error rate of the analog-to-digital converter when the respective comparator is operated at high speed. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide an IAZ analog-to-digital converter which provides improved error rate and operating speed. 
     Briefly stated, the present invention provides an analog-to-digital converter including a plurality of chopper type comparators, a controller circuit and an encoder. Each of the plurality of chopper type comparators receives a reference voltage and an analog voltage and performs an auto-zero operation for setting the reference voltage and a comparing operation for comparing the reference voltage set by the auto-zero operation with the analog voltage to output a comparison result signal. The comparing operation is performed a plurality of times subsequent to the auto-zero operation. The controller circuit is coupled to the plurality of chopper type comparators and controls one comparator to perform the auto-zero operation and the remaining comparators to perform the comparing operations, substantially simultaneously. The controller circuit selectively outputs the comparison result signals output from the remaining comparators. The encoder is coupled to the controller circuit and receives the comparison result signals and generating a digital signal therefrom. The controller circuit includes a signal selector circuit for switching a first comparison result signal output from a first comparator performing the comparing operation before or after the auto-zero operation to a second comparison result signal output from a second comparator performing the comparing operation using the same reference voltage as the first comparator. 
     The present invention provides an analog-to-digital (A/D) converter for converting an analog input signal into a digital signal. The converter includes a plurality of chopper type comparators, a controller circuit and an encoder. Each of the plurality of chopper type comparators receives and compares a reference voltage and the analog input signal to generate a comparator output signal and performs an auto-zero operation to set the reference voltage. The controller circuit is connected to the plurality of comparators and causes a selected one of the comparators to perform the auto-zero operation and the remaining, nonselected comparators to perform the comparing operation. The encoder is connected to the control circuit and the comparators and receives the output signals from the nonselected comparators and generating the digital signal therefrom. The selected comparator does not provide its comparison output signal to the encoder for at least one cycle after completing the auto-zero operation. 
     The present invention provides an analog-to-digital (A/D) converter for converting an analog input signal into a digital signal. The converter includes a plurality of chopper type comparators, a controller circuit and an encoder. Each of the plurality of chopper type comparators receives and compares a reference voltage and the analog input signal to generate a comparator output signal and performs an auto-zero operation to set the reference voltage. The controller circuit is connected to the plurality of comparators and causes a selected one of the comparators to perform the auto-zero operation and the remaining, nonselected comparators to perform the comparing operation. One of the nonselected comparators performs its comparing operation using the same reference voltage set for the selected comparator by the auto-zero operation. The encoder is connected to the control circuit and the comparators and receives the output signals from the nonselected comparators and generates the digital signal therefrom. The selected comparator does not provide its comparison output signal to the encoder for at least two cycles after completing the auto-zero operation. 
     Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
     FIG. 1 is a circuit diagram of a conventional parallel analog-to-digital converter; 
     FIG. 2 is a circuit diagram of a conventional chopper comparator; 
     FIG. 3 is a timing chart of the operation of the conventional chopper comparator of FIG. 2; 
     FIG. 4 is a timing chart of the operation of a modified conventional chopper comparator; 
     FIG. 5 is a circuit diagram of an analog-to-digital converter according to the present invention; 
     FIG. 6 is a circuit diagram of an analog-to-digital converter according to a first embodiment of the present invention; 
     FIG. 7 is a circuit diagram of a chopper comparator of the converter of FIG. 6; 
     FIG. 8 is a timing chart of the operation of the analog-to-digital converter according to the first embodiment; 
     FIG. 9 is a timing chart of the operation of an analog-to-digital converter according to a second embodiment of the present invention; 
     FIG. 10 is a circuit diagram of an analog-to-digital converter according to a fourth embodiment of the present invention; 
     FIG. 11 is a timing chart of the operation of the analog-to-digital converter according to the fourth embodiment; 
     FIG. 12 is a timing chart of the operation of an analog-to-digital converter according to a fifth embodiment; 
     FIG. 13 is a timing chart of the operation of an analog-to-digital converter according to a sixth embodiment; 
     FIG. 14 is a circuit diagram of an analog-to-digital converter according to a seventh embodiment of the present invention; 
     FIG. 15 is a timing chart of the operation of the analog-to-digital converter according to the seventh embodiment; 
     FIG. 16 is a block diagram of a control section of the analog-to-digital converter of FIG. 6 according to the first embodiment; 
     FIG. 17 is a circuit diagram of a third logic block in the control section of FIG. 16; 
     FIG. 18 is a circuit diagram of a first logic block in the control section of FIG. 16; 
     FIG. 19 is a circuit diagram of a second logic block in the control section of FIG. 16; 
     FIG. 20 is a circuit diagram of a first signal selection block in the control section of FIG. 16; 
     FIG. 21 is a circuit diagram showing a second signal selection block in the control section of FIG. 16; 
     FIG. 22 is a block diagram showing a first signal generation circuit connected to the control section of FIG. 16; 
     FIG. 23 is a circuit diagram showing a second signal generation circuit connected to the control section of FIG. 16; 
     FIG. 24 is a circuit diagram showing a fourth logic block of the signal generation circuit of FIG. 22; 
     FIG. 25 is a circuit diagram showing a third signal generation circuit connected to the control section of FIG. 16; 
     FIG. 26 is a timing chart of the operation of the control section of FIG. 16; 
     FIG. 27 is a block diagram of the control section according to the fourth embodiment of the present invention; 
     FIG. 28 is a timing chart of the operation of the control section of in FIG. 27; 
     FIG. 29 is a circuit diagram of an analog-to-digital converter according to an eighth embodiment of the present invention; and 
     FIG. 30 is a timing chart of the operation of the analog-to-digital converter according to the eighth embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 5 is a block diagram schematically showing an analog-to-digital converter  10  according to the present invention. Each of a plurality of chopper comparators CP performs an auto-zero operation by receiving an input reference voltage VRn and a comparing operation for comparing the reference voltage VRn input at the time of the auto-zero operation with an analog input signal Vin. Subsequent to an auto-zero operation, the comparing operation is performed a plurality of times. A control section  11  performs a control operation to sequentially carry out the auto-zero operation of the plurality of comparators CP and control the timing of the comparing operation and the auto-zero operation, and the setting of the reference voltage VR at the time of the comparing operation. Further, the control section  11  receives the signals output from the comparators and outputs selected signals. The encoder  12  receives the selected signals output from the control section  11  and generates a digital signal Dn. The control section  11  comprises a signal selection circuit S which switches at least one of the comparing output signals output before and after the auto-zero operations of the respective comparators CP to the comparing signal output from a comparator CP which performs the comparing operation at the same reference voltage VR. 
     (First Embodiment) 
     FIG. 6 shows an improved IAZ type analog-to-digital converter  100  according to a first embodiment of the present invention. The analog-to-digital converter  100  comprises four chopper comparators CP 1  to CP 4  for converting an analog input signal Vin to two bits of digital output signals D 1  and D 2 . Four resistors R are connected in series between a high-potential reference voltage VRH and a low-potential reference voltage VRL. The resistance value of the resistor R at each end is set to one-half that of the other resistor, thereby producing reference voltages VR 1  to VR 3  which are equal to the result of division of the voltage difference between the reference voltages VRH and VRL by the resistances of the resistors R. 
     The analog input signal Vin is input to an input terminal B of each of the comparators CP 1  to CP 4 . Each of the comparators CP 1  to CP 4  has another two input terminals A 1  and A 2  for receiving the reference voltages. In the comparator CP 1 , the input terminal A 2  receives the reference voltage VRL, and the input terminal A 1  receives the reference voltage VR 1 . In the comparator CP 2 , the input terminal A 2  receives the reference voltage VR 1 , and the input terminal A 1  receives the reference voltage VR 2 . In the comparator CP 3 , the input terminal A 2  receives the reference voltage VR 2 , and the input terminal A 1  receives the reference voltage VR 3 . In the comparator CP 4 , the input terminal A 2  receives the reference voltage VR 3 , and the input terminal A 1  receives the reference voltage VRH. 
     FIG. 7 is a circuit diagram of each of the comparators CP 1  to CP 4 . Each of the comparators CP 1  to CP 4  has switching circuits for selecting one of the reference voltages input to the input terminals A 1  and A 2  in response to control signals C 1  and C 2 . Signals Q 1  to Q 4  are provided from the comparator CP 1  to CP 4  to a control section  11   a . The control section  11   a  selects three of the output signals Q 1  to Q 4  and causes the associated three comparators to perform a comparing operation. The control section  11   a  also causes the remaining, nonselected comparator to perform an auto-zero operation. Signals Q output from the selected comparators are provided to the encoder  12  as signals E 1  to E 3 . In FIG. 6, the signal selection circuit  11   a  is schematically shown as a plurality of switches which are turned on when a corresponding one of a plurality of selection signals S 1  to S 6  goes high. The encoder  12  receives a thermometer code E 1  to E 3  output from the control section  11   a  and produces two bits of digital output signals D 1  and D 0 . 
     With reference to FIG. 16, the specifics of the control section  11   a  will be described. The control section  11   a  comprises first logic blocks  13   a  to  13   h , second logic blocks  14   a  to  14   h , third logic blocks  16   a  to  16   d , first signal selection blocks  15   a  to  15   g , second signal selection blocks  17   a  to  17   c . As shown in FIG. 18, each of first logic blocks  13   a  to  13   h  comprises an input terminal I for receiving an input signal, a reset signal input terminal RES, a clock signal input terminal CK, an output terminal O, a NAND gate, a pair of inverter circuits, and switching circuits S and XS. The clock signal input terminal CK receives a clock signal HCK whose frequency is one-twelfth of that of the clock signal CLK used for driving the comparator CPO to CP 4 . 
     When the clock signal HCK goes high, the switching circuit S is turned on. In contrast, the switching circuit XS is turned on when the clock signal HCK goes low. The reset signal input terminal RES receives a reset signal XRES (see FIG. 26) from an external device (not shown). 
     As shown in FIG. 19, each of the second logic blocks  14   a  to  14   h  comprises an input terminal I for receiving an input signal, a reset signal input terminal RES, a clock signal input terminal CK, an output terminal XO, a NAND gate, an inverter circuit, and switching circuits S and XS which are switched by the clock signal HCK input to the clock signal input terminal CK. When the clock signal HCK goes high, the switching circuit S is turned on. In contrast, the switching circuit XS is turned on when the clock signal HCK goes low. 
     As shown in FIG. 20, each of the first signal selection blocks  15   a  to  15   h  comprises two input terminals I 1  and I 2 , a selection signal input terminal SEL, an output terminal XO, two switching circuits S and XS, and an inverter circuit. The switching circuit S is turned on when a selection signal XUD input to the selection signal input terminal SEL from the external device goes high. The switching circuit XS is turned on when the selection signal XUD goes low. Each of the first signal selection blocks  15   a  to  15   g  inverts either of the signals input to the input terminals I 1  and I 2  in response to the selection signal XUD and outputs the inverted signal from the output terminal XO. 
     As shown in FIG. 17, each of the third logic blocks  16   a  to  16   d  comprises input terminals I and XI, an output terminal O, a reset signal input terminal PRS, an auto-zero clock signal input terminal AZCK, an inverter circuit, and two NOR gates. The reset signal input terminal PRS receives an inverted signal of the reset signal XRES. The auto-zero clock signal input terminal AZCK receives a clock signal HK which differs from the clock signal HCK in at least the timing of a leading edge or a trailing edge, as shown in FIG.  26 . 
     As shown in FIG. 21, each of the second signal selection blocks  17   a  to  17   c  comprises two input terminals I 1  and I 2 , a selection signal input terminal SEL, an output terminal XO, a clock signal input terminal XC, two switching circuits S and XS, an inverter circuit, and a flip-flop circuit FF. The switching circuit S is turned on when a selection signal SL goes high, and the switching circuit XS is turned on when the selection signal XSL goes low. The flip-flop circuit FF latches a selection signal SEL according to the trailing edge of the clock signal XC and outputs the latched signal as the signal SL. Further, the flip-flop circuit FF outputs an inverted signal of the selection signal SEL as the signal XSL. Each of the second signal selection blocks  17   a  to  17   c  inverts either of the signals input to the input terminals I 1  and I 2  in response to the selection signal SEL and outputs the inverted signal from the output terminal XO. 
     As shown in FIG. 16, the input terminals I 1  and I 2  of the second signal selection block  17   a  receive signals Q 3  and Q 4  output from the comparators CP 3  and CP 4 , respectively. The input terminals I 1  and I 2  of the second signal selection block  17   b  receive signals Q 2  and Q 3  output from the comparators CP 2  and CP 3 . Further, the input terminals I 1  and I 2  of the second signal selection block  17   c  receive signals Q 1  and Q 2  from the comparators CP 1  and CP 2 . 
     FIG. 22 shows a signal generation circuit  110  which is connected to the control section  11   a . The signal generation circuit  110  produces the control signal XUD in response to control signals A and XA and the reset signal XRES. The signal generation circuit  110  comprises two fourth logic blocks  18   a  and  18   b  connected to an inverter circuit in a ring shaped configuration. The control signal XUD is output from the inverter circuit and input to the fourth logic block  18   b.    
     As shown in FIG. 24, each of the fourth logic blocks  18   a  and  18   b  comprises an input terminal I for receiving an input signal, a reset signal input terminal RES receiving the reset signal XRES from the external device, a clock signal input terminal CK, an output terminal XO, a NOR gate, an inverter circuit, and switching circuits S and XS switched by the control signal A, which is input to the clock signal input terminal CK. 
     In the fourth logic block  18   a , the switching circuit S is turned on when the control signal A goes high, and the switching circuit XS is turned on when the control signal A goes low. In the fourth logic block  18   b , the switching circuit S is turned on when the control signal XA goes high, and the switching circuit XS is turned on when the control signal XA goes low. 
     FIG. 23 shows a second signal generation circuit  112  which is connected to the control section  11   a . The second signal generation circuit  112  receives the clock signal HCK, a signal NHa output from the second logic block  14   a , and a signal NLa output from the second logic block  14   g . The second signal generation circuit  112  comprises four inverter circuits, an AND gate, and a NOR gate and produces the control signals A and XA, which is the reverse of the control signal A. 
     The control section  11  outputs thermometer codes signals E 1  to E 3 . Specifically, a signal NH is output from the first signal selection block  15   a , and a signal NL is output from the first signal selection block  15   g . A signal NO is provided to the first and third logic blocks  13   f  and  16   d  from the first signal selection block  15   f , and a signal N 1  is output from the first logic block  15   e  to the first and third logic blocks  13   e ,  16   c ,  16   d  and the second signal selection block  17   c . A signal N 2  is output from the first logic block  15   d  to the first and third logic blocks  13   d ,  16   b ,  16   c  and the second signal selection block  17   b . A signal N 3  is output from first the logic block  15   c  to the first and third logic blocks  13   e ,  16   a ,  16   b  and the signal selection block  17   a . A signal N 4  is output from the first logic block  15   b  to the first and third logic blocks  13   b  and  16   a . The third logic blocks  16   a  to  16   d  output control signals XAZ 1  to XAZ 4  to the comparators CP 1  to CP 4 , and the logic blocks  17   a  to  17   c  output signals E 1  to E 3 . 
     The control signals XAZ 1  to XAZ 4  output by the third logic block  16   a - 16   d  function as the control signals CZ and /CZ used for controlling the auto-zero operations of the comparators CP 1  to CP 4 . The second signal selection blocks  17   a  to  17   c  functions as the signal selection circuit of FIG. 6 which is switched by the control signals S 1  to S 6 . The output signal N 1  is used to generate the control signals S 1 , S 2 , which are complementary to each other. The output signal N 2  is used to generate the control signals S 3 , S 4 , which are complementary to each other. The output signal N 3  is used to generate the control signals S 5 , S 6 , which are complementary to each other. 
     FIG. 25 shows a third signal generation circuit  114  connected to the control section  11   a . The third signal generation circuit  114  produces the control signals C 1  and C 2  in response to the control signals XUD, XAZ. The control signals C 1  and C 2  are then output to the comparators CP 1  to CP 4 . A reverse signal of the control signal XAZ is input to a NOR gate and a NAND gate, and the control signal XUD is input to the NOR gate and the NAND gate. The NOR gate outputs the control signal C 1 , and the NAND gate outputs the control signal C 2 . 
     With reference to FIG. 26, the operation of the control section  11   a  will be described. The reset signal XRES goes low at the time of an initial resetting operation, so that the control signals XAZ 1  to XAZ 4  provided, respectively, to the comparators CP 1  to CP 4  go low. Further, the control signal XUD goes high, and the signals NL to N 4  go low. Subsequently, when the control signal XUD goes low, the control signals NL to NH rise in order in every cycle of the clock signal HCK. Further, when the control signal XUD goes high, the signals NH to NL fall in order (i.e., NL, N 0 , N 1 , N 2 , N 3 , N 4 , NH) in every one cycle of the clock signal HCK. As a result, the control signals XAZ 1  to XAZ 4  sequentially go low, in order, for a period of time which is half the cycle of the clock signal HCK in every one cycle of the clock signal HCK. When each of the control signals XAZ 1  to XAZ 4  goes low, the each of the comparators CP 1  to CP 4  performs the auto-zero (AZ) operation. 
     The rise and fall timing of the signals NL to NH is determined by the clock signal HCK. The fall timing of the control signals XAZ 1  to XAZ 4  is determined by the clock signal HK. By controlling the rise and fall timing of the clock signal HK with respect to the clock signal HCK, the rise and fall timing of the signals N 1  to N 3  and the fall timing of the control signals XAZ 1  to XAZ 4  is controlled. 
     Subsequently, with particular reference to FIGS. 6-8, the operations of the comparators CP 1  to CP 4  under the control of the control section  11   a  will be described. The control signals S 1  to S 6 , C 1 , C 2 , and CZ, shown in FIG. 8, are produced by the control section  11   a . The control signal CF is a clock signal CLK supplied to each of the comparators CP 1  to CP 4  from the control section  11   a . The control signals S 1  to S 6  are produced by causing the clock signal HK to fall prior to the trailing edge of the clock signal HCK. When the control section  11   a  is started, the comparators CP 1  to CP 4  are respectively initialized. That is, when the control signals C 2  and CZ go high, the comparator CP 1  performs an auto-zero operation while inputting the reference voltage VRL. The comparator CP 2  performs an auto-zero operation while inputting the reference voltage VR 1 . The comparator CP 3  performs an auto-zero operation while inputting the reference voltage VR 2 . The comparator CP 4  performs an auto-zero operation while inputting the reference voltage VR 3 . 
     Next, when the control signal CZ goes low, each of the comparators CP 1  to CP 4  commences a comparing operation. At this time, the control signals S 1  to S 6  are maintained in a low state, thereby preventing the comparators CP 1  to CP 4  from outputting signals Q 1  to Q 4  to the encoder  12 . Subsequently, after one cycle of the control signal CF, the control signals C 1  and CZ of the comparator CP 1  go high. The comparator CP 1  performs the auto-zero operation while inputting the reference voltage VR 1 . 
     After the completion of the auto-zero operation of the comparator CP 1 , the control signals S 2 , S 4 , and S 6  go high. As a result, the signals Q 2 , Q 3 , and Q 4  are provided to the encoder  12  from the comparators CP 2 , CP 3 , and CP 4 . At this time, the comparator CP 2  outputs the comparison result of the reference voltage VR 1  and the analog input signal Vin. The comparator CP 3  outputs the comparison result of the reference voltage VR 2  and the analog input signal Vin. The comparator CP 4  outputs the comparison result of the reference voltage VR 3  and the analog input signal Vin. After the auto-zero operation of the comparator CP 1 , the state is maintained during two cycles of the control signal CF. Accordingly, invalid data D 1  and indefinite data D 2  output from the comparator CP 1  after the auto-zero operation is not provided to the encoder  12 . After the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 1 , the control signals C 1  and CZ of the comparator CP 2  go high. The comparator CP 2  then performs the auto-zero operation while inputting the reference voltage VR 2 . 
     After the completion of the auto-zero operation of the comparator CP 2 , the control signal S 2  goes low, and the control signal S 1  goes high. As a result, in place of the signal Q 2 , the signal Q 1  output from the comparator CP 1  is provided as a signal E 1  to the encoder  12 . That is, the comparators CP 1 , CP 3  and CP 4  output the comparison results. Accordingly, the invalid data D 1  and the indefinite data D 2  output from the comparator CP 2  after the auto-zero operation is not provided to the encoder  12 . 
     After the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 2 , the control signals C 1  and CZ of the comparator CP 3  go high. The comparator CP 3  then performs the auto-zero operation while inputting the reference voltage VR 3 . After the completion of the auto-zero operation of the comparator CP 3 , the control signal S 4  goes low, and the control signal S 3  goes high. As a result, in place of the signal Q 3 , the signal Q 2  output from the comparator CP 2  is provided as a signal E 2  to the encoder  12 . That is, the comparators CP 1 , CP 2  and CP 4  output the comparison results. Accordingly, the invalid data D 1  and the indefinite data D 2  output from the comparator CP 3  after the auto-zero operation is not provided to the encoder  12 . 
     After the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 3 , the control signals C 1  and CZ of the comparator CP 4  go high. The comparator CP 4  then performs the auto-zero operation while inputting the reference voltage VRH. After the completion of the auto-zero operation of the comparator CP 4 , the control signal S 6  goes low, and the control signal S 5  goes high. As a result, in place of the signal Q 4  output from the comparator CP 4 , the signal Q 3  output from the comparator CP 3  is provided as a signal E 3  to the encoder  12 . That is, the comparators CP 1 , CP 2  and CP 3  output the comparison results. Subsequently, after the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 4 , the control signals C 2  and CZ of the comparator CP 4  go high again. The comparator CP 4  then performs the auto-zero operation while inputting the reference voltage VR 3 . Accordingly, the invalid data D 1  and the indefinite data D 2  output from the comparator CP 4  after the auto-zero operation is not provided to the encoder  12 . From then on, the comparators CP 1  to CP 3  sequentially perform the auto-zero operations in the same manner as mentioned previously, and the operations are repeated. 
     As discussed above, during two cycles of the control signal CF after the auto-zero operation, a signal output from the comparator is not provided to the encoder  12 . A signal output from another comparator which is performing the comparing operation at the same reference voltage is output to the encoder  12 . Therefore, invalid data and indefinite data output from the comparator immediately after the auto-zero operation are not provided to the encoder  12 , so that the error rate of the analog-to-digital converter is improved, and a high speed analog-to-digital conversion is accurately performed. 
     (Second Embodiment) 
     FIG. 9 shows the operation of the analog-to-digital converter  100  operating according to a second embodiment of the present invention. In the second embodiment, the comparators CP 1  to CP 4  are selected by the control signals S 1  to S 6  produced in accordance with the clock signal HK high after the leading edge of the clock signal HCK. 
     Referring to FIG. 9, the control signals S 1  to S 6  are switched faster than in the first embodiment by one cycle of the control signal CF. 
     The control signals C 1  and CZ of the comparator CP 1  go high after one cycle of the control signal CF. The comparator CP 1  performs the auto-zero operation while inputting the reference voltage VR 1 . In synchronization with the initiation of the auto-zero operation, the control signals S 2 , S 4 , and S 6  go high. As a result, the comparators CP 2 , CP 3 , and CP 4  output the comparison result signals Q 2 , Q 3 , and Q 4  to the encoder  12 . This state is maintained for two cycles of the control signal CF after initiation of the auto-zero operation of the comparator CP 1 . Accordingly, the invalid data D 1  output from the comparator CP 1  after the auto-zero operation and the indefinite data D 2  output from the comparator CP 1  prior to the invalid data D 1  are not provided to the encoder  12 . The indefinite data D 2  is caused by switching noise which occurs during transition of the respective comparator from the comparing operation to the auto-zero operation, or by the deficiency of hold time of the output latch circuit of each comparator. 
     After one cycle of the control signal CF from the auto-zero operation of the comparator CP 1 , the control signals Cl and CZ of the comparator CP 2  go high. The comparator CP 2  performs the auto-zero operation while inputting the reference voltage VR 2 . In synchronization with the initiation of the auto-zero operation, the control signal S 2  goes low, and the control signal S 1  goes high. As a result, in place of the signal Q 2 , the signal Q 1  output from the comparator CP 1  is provided as a signal E 1  to the encoder  12 . That is, the comparators CP 1 , CP 3  and CP 4  output the comparison results. Accordingly, the invalid data D 1  output at the time of auto-zero operation and the indefinite data D 2  output from the comparator CP 2  prior to the invalid data D 1  are not provided to the encoder  12 . 
     After the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 2 , the control signals C 1  and CZ of the comparator CP 3  go high. The comparator CP 3  performs the auto-zero operation while inputting the reference voltage VR 3 . In synchronization with the initiation of the auto-zero operation, the control signal S 4  goes low, and the control signal S 3  goes high. As a result, in place of the signal Q 3 , the signal Q 2  output from the comparator CP 2  is provided as the signal E 2  to the encoder  12 . That is, the comparators CP 1 , CP 2  and CP 4  output the comparison results. Accordingly, the invalid data D 1  output at the time of auto-zero operation and the indefinite data D 2  output from the comparator CP 3  prior to the invalid data D 1  are not provided to the encoder  12 . 
     After the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 3 , the control signals C 1  and CZ of the comparator CP 4  go high. The comparator CP 4  performs the auto-zero operation while inputting the reference voltage VRH. In synchronization with the initiation of the auto-zero operation, the control signal S 6  goes low, and the control signal S 5  goes high. As a result, in place of the signal Q 4 , the signal Q 3  output from the comparator CP 3  is provided as the signal E 3  to the encoder  12 . That is, the comparators CP 1 , CP 2  and CP 3  output the comparison results. 
     Subsequently, after the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 4 , the control signals C 2  and CZ of the comparator CP 4  go high again. The comparator CP 4  performs the auto-zero operation while inputting the reference voltage VR 3 . Accordingly, the invalid data D 1  output from the comparator CP 4  at the time of auto-zero operation and the indefinite data D 2  output from the comparator CP 4  prior to the invalid data D 1  are not provided to the encoder  12 . 
     In the second embodiment, during two cycles of the control signal CF after the auto-zero operation, a signal output from the comparator is not provided to the encoder  12 . Therefore, invalid data D 1  immediately after the auto-zero operation and indefinite data D 2  output prior to the invalid data D 1  during the auto-zero operation are not provided to the encoder  12 . 
     (Third Embodiment) 
     The analog-to-digital converter  100  may also be operated according to a third embodiment of the present invention. In the third embodiment, the comparators CP 1  to CP 4  are selected by the control signals S 1  to S 6  produced in accordance with the clock signal HK high after the leading edge of the clock signal HCK and the clock signal low prior to the trailing edge of the clock signal HCK. 
     In the third embodiment, the comparators CP 1  to CP 4  perform the auto-zero operations in every two cycles of the control signal CF. The control signals S 1  to S 6  are controlled to prevent the invalid data D 1  during the auto-zero operation of a first comparator and indefinite data D 2  output subsequent to the invalid data D 1  from being provided to the encoder  12  and to prevent invalid data D 1  during the auto-zero operation of a second comparator subsequent to the first comparator and indefinite data D 2  output prior to the invalid data D 1  from being provided to the encoder. In the third embodiment, the invalid data D 1  immediately after an auto-zero operation and indefinite data D 2  before and after the invalid data are not provided to the encoder  12 . 
     (Fourth Embodiment) 
     FIG. 10 is a schematic diagram of an analog-to-digital converter  200  according to a fourth embodiment of the present invention. The analog-to-digital converter  200  comprises five chopper comparators CP 1  to CP 5  used to produce two digital output signals D 0  and D 1 , a control section  11   b  and the encoder  12 . The analog input signal Vin is input to an input terminal B of each of the comparators CP 1  to CP 5 . In the comparator CP 1 , the input terminal A 1  receives the reference voltage VR 1 , and the input terminal A 2  receives the reference voltage VRL. In the comparator CP 2 , the input terminal A 1  receives the reference voltage VR 2 , and the input terminal A 2  receives the reference voltage VRL. In the comparator CP 3 , the input terminal A 1  receives the reference voltage VR 3 , and the input terminal A 2  receives the reference voltage VR 1 . In the comparator CP 4 , the input terminal A 1  receives the reference voltage VRH, and the input terminal A 2  receives the reference voltage VR 3 . 
     In response to a control signal S 1  output from the control section  11   b , the signal Q 1  output from the comparator CP 1  is selected to be input as the signal E 1  into the encoder  12 . In response to the control signal S 3 , the signal Q 2  output from the comparator CP 2  is selected to be input as the signal E 2  into the encoder  12 . In response to the control signals S 2  and S 5 , the signal Q 3  output from the comparator CP 3  is selected to be input as the signal E 1  or E 3  into the encoder  12 . In response to the control signal S 4 , the signal Q 4  output from the comparator CP 4  is selected to be input as the signal E 2  into the encoder  12 . In response to the control signal S 6 , the signal Q 5  output from the comparator CP 5  is selected to be input as the signal E 3  into the encoder  12 . 
     FIG. 27 is a block diagram of the control section  11   b  of the fourth embodiment. The control section  11   b  comprises nine first logic blocks  13   a  to  13   i , nine second logic blocks  14   a  to  14   i , eight first signal selection blocks  15   a  to  15   h , and five third logic blocks  16   a  to  16   e . The signals N 2  to N 4  output from the first signal selection blocks  15   c  to  15   e  are provided to the second signal selection blocks  17   a  to  17   c , which perform the selecting operations by the control signals S 1  to S 6 . 
     With reference to FIG. 11, the operations of the comparators CP 1  to CP 5  of the fourth embodiment will be described. The control signal CF is a clock signal CLK supplied to each of the comparators CP 1  to CP 5  from the control section  11   b . The control signals S 1  to S 6  are produced by causing the clock signal HK to rise prior to the leading edge of the clock signal HCK. 
     When the control section  11   b  is started, the comparators CP 1  to CP 5  are respectively initialized. That is, when the control signals C 2  and CZ go high, the comparator CP 1  performs an auto-zero operation while inputting the reference voltage VRL. The comparator CP 2  performs an auto-zero operation while inputting the reference voltage VRL. The comparator CP 3  performs an auto-zero operation while inputting the reference voltage VR 1 . The comparator CP 4  performs an auto-zero operation while inputting the reference voltage VR 2 . The comparator CP 5  performs an auto-zero operation while inputting the reference voltage VR 3 . 
     Subsequently, when the control signal CZ goes low, each of the comparators CP 1  to CP 5  commences a comparing operation. At this time, the control signals S 1  to S 6  are maintained in a low state, thereby preventing the comparators CP 1  to CP 5  from outputting signals Q 1  to Q 5  to the encoder  12 . 
     After one cycle of the control signal CF, the control signals C 1  and CZ of the comparator CP 1  go high. The comparator CP 1  performs the auto-zero operation while inputting the reference voltage VR 1 . Next, after the completion of the auto-zero operation of the comparator CP 1 , the control signals S 2 , S 4 , and S 6  go high. As a result, the signals Q 3 , Q 4 , and Q 5  are provided to the encoder  12  from the comparators CP 3 , CP 4 , and CP 5 . At this time, the comparator CP 3  outputs the comparison result of the reference voltage VR 1  and the analog input signal Vin. The comparator CP 4  outputs the comparison result of the reference voltage VR 2  and the analog input signal Vin. The comparator CP 5  outputs the comparison result of the reference voltage VR 3  and the analog input signal Vin. After the auto-zero operation of the comparator CP 1 , the state is maintained during two cycles of the control signal CF. Accordingly, the invalid data D 1  and indefinite data D 2  output from the comparator CP 1  after the auto-zero operation is not provided to the encoder  12 . 
     After the comparator CP 1  has completed the auto-zero operation, the control signals C 1  and CZ of the comparator CP 2  go high substantially simultaneously with the leading edge of the next control signal CF. The comparator CP 2  then performs the auto-zero operation while inputting the reference voltage VR 2 . In this state, there are no substantial changes in the control signals S 1  to S 6 , and the comparator CP 1  is performing a comparing operation. However, the signal Q 1  output from the comparator CP 1  is not provided to the encoder  12 . 
     After a lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 2 , the control signal S 2  goes low, and the control signal S 1  goes high. As a result, in place of the signal Q 3 , the signal Q 1  output from the comparator CP 1  is provided as the signal E 1  to the encoder  12 . That is, the comparators CP 1 , CP 4  and CP 5  output the comparison results. Accordingly, the invalid data D 1  and the indefinite data D 2  output from the comparator CP 2  after the auto-zero operation is not provided to the encoder  12 . 
     After the comparator CP 2  has completed the auto-zero operation, the control signals C 1  and CZ of the comparator CP 3  go high substantially simultaneously with the leading edge of the next control signal CF. The comparator CP 3  then performs the auto-zero operation while inputting the reference voltage VR 3 . After the lapse of one cycle of the control signal CF after the auto-zero operation of the comparator CP 3 , the control signal S 4  goes low, and the control signal S 3  goes high. As a result, the signal Q 2  output from the comparator CP 2  is provided as the signal E 2  to the encoder  12 . That is, the comparators CP 1 , CP 2  and CP 5  output the comparison results Accordingly, the invalid data D 1  and the indefinite data D 2  output from the comparator CP 3  after the auto-zero operation is not provided to the encoder  12 . 
     After the comparator CP 3  has completed the auto-zero operation, the control signals C 1  and CZ of the comparator CP 4  go high substantially simultaneously with the leading edge of the next control signal CF. The comparator CP 4  then performs the auto-zero operation while inputting the reference voltage VRH. Next, after the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 4 , the control signal S 6  goes low, and the control signal S 5  goes high. As a result, in place of the signal Q 5 , the signal Q 3  output from the comparator CP 3  is provided as the signal E 3  to the encoder  12 . That is, the comparators CP 1 , CP 2  and CP 3  output the comparison results. Accordingly, the invalid data D 1  and the indefinite data D 2  output from the comparator CP 4  after the auto-zero operation is not provided to the encoder  12 . 
     After the comparator CP 4  has completed the auto-zero operation, the control signals C 1  and CZ of the comparator CP 5  go high simultaneously with the leading edge of the next control signal CF. The comparator CP 5  then performs the auto-zero operation while inputting the reference voltage VRH. Next, after the lapse of one cycle of the control signal CF from the auto-zero operation of the comparator CP 5 , the control signals C 2  and CZ of the comparator CP 5  go high. The comparator CP 5  then performs the auto-zero operation while inputting the reference voltage VR 3 . At this time, since there are no substantial changes in the control signals S 1  to S 6 , the signals Q 1  to Q 3  are provided to the encoder  12  without interruption. 
     Next, after the comparator CP 5  has completed the auto-zero operation, the control signals C 2  and CZ of the comparator CP 4  go high substantially simultaneously with the leading edge of the next control signal CF. The comparator CP 4  then performs the auto-zero operation while inputting the reference voltage VR 2 . At this time, since there are no substantial changes in the control signals S 1  to S 6 , the signals Q 1  to Q 3  are provided to the encoder  12  without interruption. Accordingly, the invalid data D 1  and the indefinite data D 2  output from the comparator CP 5  after the auto-zero operation is not provided to the encoder  12 . 
     After the comparator CP 4  has completed the auto-zero operation based on the reference voltage VR 2 , the control signals C 2  and CZ of the comparator CP 3  go high substantially simultaneously with the leading edge of the next control signal CF. The comparator CP 3  then performs the auto-zero operation while inputting the reference voltage VR 1 . Substantially simultaneously with the completion of the auto-zero operation, the control signal S 6  goes high, and the control signal S 5  goes low. As a result, in place of the signal Q 3 , the signal Q 5  is provided as the signal E 3  to the encoder  12 . Further, the signals Q 1  and Q 2  are provided as the signals E 1  and E 2  to the encoder  12  without interruption. Accordingly, the invalid data D 1  and the indefinite data D 2  output from the comparator CP 4  after the auto-zero operation is not provided to the encoder  12 . 
     In the fourth embodiment, during two cycles of the control signal CF after the auto-zero operation, the signal output from the comparator that has performed the auto-zero operation is switched to a signal output from another comparator which is performing the comparing operation at the same reference voltage. Therefore, invalid data D 1  and indefinite data D 2  immediately after the auto-zero operation are not provided to the encoder  12 . Furthermore, When the comparators CP 1  to CP 5  perform the auto-zero operation in turn at each rising edge of the control signal CF, the three comparators, which performs comparison operation in a stable state, are selected, the remaining one of two unselected comparators performs an auto-zero operation, and the remaining another one of two unselected comparators outputs invalid data and indefinite data. Accordingly, the speed of analog-to-digital conversion is increased. 
     (Fifth Embodiment) 
     FIG. 12 is a timing diagram showing the operation of the analog-to-digital converter  200  operating according to a fifth embodiment of the present invention. The operation of the analog-to-digital converter  200  according to the fifth embodiment is modified from the fourth embodiment in the timing at which the auto-zero operations are performed, as well as in the timing at which the signals Q 1  to Q 5  are selected by the control signals S 1  to S 6 . The control signals Si to S 6  are produced in accordance with the control section  11   b . The clock signals HK and HCK are produced in accordance with the clock signal HK low after the trailing edge of the clock signal HCK. 
     In FIG. 12, the timing at which each of the comparators CP 1  to CP 5  performs the auto-zero operation is the same as the fourth embodiment. However, the control signals S 1  to S 6  of the fifth embodiment are switched earlier than the fourth embodiment by one cycle of the control signal CF. During two cycles of the control signal CF from the commence of the auto-zero operation, the signal output from the comparator that has performed the auto-zero operation is switched to a signal output from another comparator which is performing the comparing operation at the same reference voltage. Therefore, invalid data D 1  and indefinite data D 2  output prior to the invalid data D 1  during the auto-zero operation are not provided to the encoder  12 . 
     (Sixth Embodiment) 
     FIG. 13 shows the operation of the analog-to-digital converter  200  operating according to a sixth embodiment of the present invention. The operation of the analog-to-digital converter  200  according to the sixth embodiment is modified from the operation of the fourth embodiment in the timing at which the auto-zero operations are performed, as well as in the timing at which the signals Q 1  to Q 5  are selected by the control signals S 1  to S 6 . The control signals S 1  to S 6  are produced in accordance with the clock signal HK low after the trailing edge of the clock signal HCK and the clock signal HK high prior to the leading edge of the clock signal HCK. The timing at which each of the comparators CP 1  to CP 5  performs the auto-zero operation is the same as that the fourth embodiment. The control signals S 1  to S 6  of the sixth embodiment are switched by delaying the timing of the leading edges of the control signals S 1 , S 3  and S 5  and the trailing edges of the control signals S 2 , S 4  and S 6  according to the fifth embodiment by one cycle of the control signal CF. 
     In the six embodiment, the invalid data D 1  output from the comparator immediately after the auto-zero operation and indefinite data D 2  output before and after the invalid data D 1  are not provided to the encoder  12 . 
     (Seventh Embodiment) 
     FIG. 14 is a circuit diagram of an analog-to-digital converter  300  according to a seventh embodiment of the present invention. The analog-to-digital converter  300  comprises six chopper comparators CP 1  to CP 6  used to produce two digital output signals D 0  and D. 
     The analog input signal Vin is input to an input terminal B of each of the comparators CP 1  to CP 6 . In the comparator CP 1 , the input terminal A 1  receives the reference voltage VR 1 , and the input terminal A 2  receives the reference voltage VRL. In the comparator CP 2 , the input terminal A 1  receives the reference voltage VR 2 , and the input terminal A 2  receives the reference voltage VRL. In the comparator CP 3 , the input terminal A 1  receives the reference voltage VR 3 , and the input terminal A 2  receives the reference voltage VR 1 . In the comparator CP 4 , the input terminal A 1  receives the reference voltage VRH, and the input terminal A 2  receives the reference voltage VR 3 . In the comparator CP 5 , the input terminal A 1  receives the reference voltage VRH, and the input terminal A 2  receives the reference voltage VR 2 . In the comparator CP 6 , the input terminal A 1  receives the reference voltage VRH, and the input terminal A 2  receives the reference voltage VR 3 . 
     In response to the control signal S 1 , the signal Q 1  output from the comparator CP 1  is selected to be input as the signal E 1  into the encoder  12 . In response to the control signal S 3 , the signal Q 2  output from the comparator CP 2  is selected to be input as the signal E 2  into the encoder  12 . In response to the control signal S 5 , the signal Q 3  output from the comparator CP 3  is selected to be input as the signal E 3  into the encoder  12 . In response to the control signal S 2 , the signal Q 4  output from the comparator CP 4  is selected to be input as the signal E 1  into the encoder  12 . In response to the control signal S 4 , the signal Q 5  output from the comparator CP 5  is selected to be input as the signal E 2  into the encoder  12 . In response to the control signal S 6 , the signal Q 6  output from the comparator CP 6  is selected to be input as the signal E 3  into the encoder  12 . 
     FIG. 15 shows the operation of the analog-to-digital converter  300  of the seventh embodiment. Of the control signals S 1  to S 6 , with the exception of an initial operation, the control signals S 1  and S 4  are complementary to each other; the control signals S 2  and S 5  are complementary to each other; and the control signals S 3  and S 6  are complementary to each other. The comparators CP 1  to CP 6  perform the auto-zero operation in turn on in response to the control signals C 1 , C 2 , and CZ at each leading edge of the control signal CF. 
     In the seventh embodiment, invalid data D 1  immediately after the auto-zero operation and indefinite data D 2  output before and after the invalid data D 1  are not provided to the encoder  12 . 
     Furthermore, when the comparators CP 1  to CP 6  perform the auto-zero operation in turn at each rising edge of the control signal CF, the three comparators which perform comparison operation in a stable state are selected, the remaining one of three unselected comparators performs an auto-zero operation, and the remaining two of three unselected comparators output invalid data and indefinite data. Accordingly, the speed of analog-to-digital conversion is increased. 
     (Eighth Embodiment) 
     FIG. 29 is a circuit diagram of an analog-to-digital converter  400  according to an eighth embodiment of the present invention. The eighth embodiment is a modified version of the fourth embodiment of FIG.  10 . In the eighth embodiment, the control section  11   b ′ provides a first control signal XAZ 1  to the first and second comparators CP 1  and CP 2 , a second control signal XAZ 2  to the third and fourth comparators CP 3  and CP 4 , and a third control signal XAZ 3  to the fifth comparator CP 5 . Accordingly, the control section  11   b ′ has only three logic circuits for generating the first to third control signals XAZ 1 -XAZ 3 , so that reduction of a circuit area and power consumption of the converter  400  is achieved. In contrast, the control section  11   b  of the fourth embodiment has five logic circuits for generating the first to fifth control signals XAZ 1 -XAZ 5  for five comparators CP 1 -CP 5 . 
     FIG. 29 is a timing chart of the operation of the analog-to-digital converter  400  according to the eighth embodiment. The converter  400  operates such that when a pair of comparators performs an auto-zero operation, the remaining three comparators perform a comparison operation. For example, when a pair of comparators CP 1  and CP 2  perform an auto-zero operation, the remaining three comparators CP 3 -CP 5  perform a comparison operation. 
     Since the number of the control signals of the eighth embodiment are less than the number of the control signals of the fourth embodiment, the maximum period of auto-zero operations of all of the comparators is shortened, so that the charging period of the capacitor of the comparator is narrowed. This allows the converter to be fully operated at a relatively low frequency. 
     The eighth embodiment may be applied to the seventh embodiment of FIG.  14 . That is, the control section  11   b ′ provides a first control signal XAZ 1  to the first to third comparators CP 1 -CP 3  and a second control signal XAZ 2  to the fourth to sixth comparators CP 4 -CP 6 . Accordingly, the control section has only two logic circuits for generating the first and second control signals XAZ 1  and XAZ 2 . The converter of the eighth embodiment operates so that when three comparators perform an auto-zero operation, the remaining three comparators perform a comparison operation. For example, when three comparators CP 1 -CP 3  perform an auto-zero operation, the remaining three comparators CP 4 -CP 6  perform a comparison operation. Alternatively, when three comparators CP 4 -CP 6  perform an auto-zero operation, the remaining three comparators CP 1 -CP 3  perform a comparison operation. 
     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. For example, the operation of the output latch circuit may be stopped at the time of the auto-zero operation by suspending the input of the control signal CF to the output latch circuit in accordance with the control signal CZ. In this case, an unnecessary operation of the output latch circuit during the auto-zero operation is stopped, the power consumption by the output latch circuit is reduced. Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.