Abstract:
The present invention is directed to a CMOS sensor. A substrate has a metal-oxide semiconductor. The metal-oxide semiconductor has a gate and a source/drain region in the substrate. A dummy shield layer is over a part of the substrate. A sensor region is in the substrate with one end extended from a part of the source/drain region and the other end adjacent to the part of the substrate under the dummy shield layer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a structure of a semiconductor device. More particularly, the present invention relates to a structure of complementary metal-oxide semiconductor (CMOS) sensor. 
     2. Description of the Related Art 
     Charge-coupled devices (CCDs) have been the mainstay of conventional imaging circuits for converting light into an electrical signal that represents the intensity of the energy. The applications of the CCDs include monitors, transcription machines and cameras. Although CCDs have many strengths, CCDs also suffer from high costs and the limitation of the CCDs&#39; volume. To overcome the weaknesses of CCDs and reduce costs and dimension, a CMOS photodiode device was developed. Because a CMOS photodiode device can be produced using conventional techniques, costs and the volume of the sensor can be reduced. The applications of CMOS photodiodes include PC cameras, digital cameras etc. 
     The photodiode is based on the theory that a P-N junction can convert light into an electrical signal. Before energy in the form of photons strikes the photodiode, there is an electric field in the P-N junction. The electrons in the N region do not diffuse forward to P region and the holes in the P region do not diffuse forward to N region. When enough light strikes the photodiode, the light creates a number of electron-hole pairs. The electrons and the holes diffuse forward to the P-N junction. While the electrons and the holes reach the P-N junction as a result of the effect of the inner electric field across the junction, the electrons flow to the N region and the holes flow to the P region. Thus a current is induced between the P-N junction electrodes. Ideally, a photodiode in the dark is open-circuit. In other words there is no current induced by light while the photodiode is in the dark. 
     FIG. 1A is a circuit diagram of a CMOS sensor. FIG. 1B is a layout of the sensor cell  110  in the FIG.  1 A. FIG. 1C is a schematic, cross-sectional view of conventional CMOS sensor as taken along the I—I line in FIG.  1 B. 
     As shown in FIG. 1A, the sensor array used in the latest CMOS sensor is improved from a passive pixel sensor array to an active pixel sensor array. The CMOS having the active pixel sensor array cell includes at least three active transistors  104 ,  106 ,  108  and a photodiode  102 . The three active transistors are reset transistor  104 , sense transistor  106  and select transistor  108 . One of the source/drain regions of the transistor  104  is electrically coupled to the source voltage V DD . One of the source/drain regions of the transistor  106  is electrically coupled to the source voltage V DD . One of the source/drain regions of the transistor  108  is electrically coupled to the output. The sensor cell  110  comprises the transistor  104  and the photodiode  102 . The photodiode  102  can convert light into an electrical signal by using the P-N junction and the electrical signal is transferred to the transistor  104 . 
     As shown in FIG. 1B, the sensor cell  110  comprises the transistor  104  and the photodiode  102 . The transistor  104  comprises a gate structure  104   a,  a source/drain region  104   b  adjacent to the gate structure  104   a  in the substrate. The sensor region  102   a  of the photodiode  102  is adjacent to the source/drain region  118  in the substrate. 
     As shown in FIG. 1C, the method of manufacturing the sensor cell  110  comprises providing a substrate  100  having an isolation region  112 , an insulating layer  114  and a gate  104   a.  The insulating layer  114  can be a field oxide layer, for example. An ion implantation step is used to formed lightly doped drain (LDD) regions in portions of the substrate  100  exposed by the gate  104   a  and the isolation region  112 . A spacer  116  is formed on the sidewall of the gate  104   a.  An ion implantation step is used to form heavily doped regions in portions of the substrate  100  exposed by the gate  104   a,  the spacer  116  and the isolation region  112 . A source/drain region  104   b  is formed by a composition of the heavily doped region and the lightly doped drain region. A patterned photoresist (not shown) is formed over the substrate  100  to expose the region for the subsequently formed sensor region  102   a.  An implantation step with low energy and a high implanting dosage is performed to form a sensor region  102   a  across a portion of the source/drain region  118  and extending from the surface of the substrate  100  into the substrate  100 . 
     Since the bird&#39;s beak region  112   a  is present at the boundary between the sensor region  112  and the sensor region  102   a,  the stress of the interface between the isolation region  112  and sensor region  102   a  is large. Because of the large stress, many crystal defects are present at the boundary between the sensor region  112  and the sensor region  102   a.  Therefore, the crystal defects induce large junction leakage current and dark current of the sensor. Furthermore, spots of light easily occur in the display image. 
     In order to overcome the problems induced by the bird&#39;s beak  112   a,  another conventional method of manufacturing a CMOS sensor was developed. 
     FIG. 2A is a layout of a sensor cell produced by another conventional method. FIG. 2B is a schematic, cross-sectional view of the conventional CMOS sensor referred to the II—II line in FIG.  2 A. 
     Referring to FIG. 2A together with FIG. 2B, a gate  204   a  of a reset transistor  204  is formed on a substrate  200 . A dummy shield layer  218  is formed on a isolation region  212  and covers the bird&#39;s beak region  212   a.  The gate  204   a  and the dummy shield layer  218  are formed in the same step. The region which is covered by the dummy shield layer  218  extends from the bird&#39;s beak region  212   a  extending 0.5 μm to the reset transistor  204  and to the isolation region  212 . 
     Because of the dummy shield layer  218 , the subsequently formed sensor region  202   a  and the bird&#39;s beak region  212   a  are staggered. Therefore, the junction leakage current is small. Since the dummy shield layer  218  extends about 0.5 μm form the bird&#39;s beak region  212   a  to the reset transistor  204 , the size of subsequently formed sensor region  202   a  is limited. Furthermore, the efficiency and the effect of the sensor are poor. 
     SUMMARY OF THE INVENTION 
     It is therefore an objective of the invention to provide a structure of a CMOS sensor. The invention can overcome the problem of junction leakage current caused by the crystal defect in the bird&#39;s beak region. 
     It is another an objective of the invention to provide a structure of a CMOS sensor. The invention can overcome the problems that the size of the sensor region is limited by the dummy shield layer covering the bird&#39;s beak region and the efficiency and the effect of the sensor are poor. 
     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a structure of a CMOS sensor. The structure comprises of a substrate having a metal oxide semiconductor, wherein the metal oxide semiconductor has a source/drain region in the substrate and a gate on the substrate. A sensor is region adjacent to the source/drain region in the substrate, and a dummy shield layer is around the sensor region on the substrate. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIG. 1A is a circuit diagram of a CMOS sensor; 
     FIG. 1B is a layout of the sensor cell in the FIG. 1A; 
     FIG. 1C is a schematic, cross-sectional view of the conventional CMOS sensor as taken substantially along line I—I in FIG. 1B; 
     FIG. 2A is a layout of a sensor cell produced by another conventional method; 
     FIG. 2B is a schematic, cross-sectional view of the conventional CMOS sensor as taken substantially along line II—II in FIG. 2A; 
     FIGS. 3A through 3C are schematic, cross-sectional views of the process for manufacturing a CMOS sensor in a preferred embodiment according to the invention; and 
     FIG. 3D is a layout of a sensor cell produced by the invention referred to the FIG.  3 C. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     FIGS. 3A through 3C are schematic, cross-sectional views of the process for manufacturing a CMOS sensor in a preferred embodiment according to the invention. 
     First, as shown in FIG. 3A, a substrate  300  having an insulating layer  314  such as a silicon oxide formed by thermal oxidation is provided. The substrate  300  can be a doped well, for example. A gate  304   a  and a dummy shield layer  320  are formed on the insulating layer  314  in the same step. The gate  304   a  can be formed by a composition of a polysilicon layer formed by low-pressure chemistry vapor deposition and a polycide layer on the polysilicon layer. It is the characteristic of the invention, since there is no isolation region on the substrate  300 , the surface of the substrate is plane. Furthermore, the dummy shield layer  320  is formed instead of the isolation region and defines the range for the subsequently formed sensor region, so that the problem of the junction leakage current induced by the crystal defect of the bird&#39;s beak region  112   a  (as shown in FIG. 1C) can be solved and the dark current of the sensor caused by junction leakage current is improved. Moreover, since there is no isolation region, the dummy shield layer  320  is not needed to stagger the bird&#39;s beak region  212   a  and sensor region  202   a  (as shown in FIG.  2 B). Therefore, the size of the subsequently formed sensor region would not be limited and the efficiency and the effect of the sensor can be improved. Additionally, since there is no isolation region, the process for manufacturing a sensor and the layout of the sensor are simplified and the integration of the device is increased. 
     Next, a source/drain region  304   b  is formed adjacent to the gate  304   a  in the substrate  300 . In this example, the steps of forming the source/drain region  304   b  comprise performing a LDD process to form a LDD region in the substrate  300  exposed by the gate  304   a  and the dummy shield layer  320 . Then, a spacer  316  is formed on the sidewall of the gate  304   a.  A heavily doped process  324  is performed to form a heavily doped region in the substrate  300  exposed by the gate  304   a,  the spacer  316  and the dummy shield layer  320 . The source/drain region  304   b  is formed by a composition of the LDD region and the heavily doped region. The dosage of the LDD process is low and the preferred dosage is about 10 13  atoms/cm 2 . The utility of the LDD region is to prevent the source/drain region  304   b  from the short channel effects. The dosage of the heavily doped process  324  is high and the preferred dosage is about 10 15  atoms/cm 2  and the preferred implantation energy is about below 100 KeV. 
     As shown in FIG. 3B, an ion implantation step  326  is used to form a sensor region  302   a  in the substrate  300  exposed by a photoresist  328  and the dummy shield layer  328 , wherein the sensor region  302   a  is adjacent to the dummy shield layer  328  and across a portion of the source/drain region  304   b  and extending from the surface of the substrate  300  into the substrate  300 . The dopant types of the sensor region  302   a  and the substrate  300  are different. The dosage of the ion implantation step  326  is low and the preferred dosage is about 10 13  atoms/cm 2 −5.0×10 14  atoms/cm 2  and the preferred implantation energy is about 30 KeV. 
     As shown in FIG. 3C, the photoresist  328  is stripped away to expose the transistor  304 . 
     FIG. 3D is a layout of a sensor cell produced by the invention referred to the FIG.  3 C. In FIG. 3D, the dummy shield layer  320  surround the sensor region  302   a,  and one of the source/drain region  304   b  of the transistor  304  is adjacent to the sensor region  302   a.    
     Altogether, the characteristics of the present invention include the following: 
     1. In the invention, since there is no isolation region on the substrate, the surface of the substrate is plane. The problem of the junction leakage current induced by the crystal defect of the bird&#39;s beak region can be overcome. 
     2. In the invention, since there is no isolation on the substrate, the dummy shield layer is unnecessary to stagger the bird&#39;s beak region and sensor region. Therefore, the size of the sensor region would not be limited and the efficiency and the effect of the sensor is improved. 
     3. In the invention, since there is no isolation on the substrate, the process for manufacturing a sensor and the layout of the sensor are simplified and the integration of the device is increased. 
     4. The invention is suitable for manufacturing high integration device, and the invention and the conventional process techniques are compatible; thus the present invention is suitable for the manufacturers to utilize. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.