Abstract:
A self-biased cascode current mirror/scaler circuit can include a bias FET biased with an input current to generate a gate-source voltage, which can be divided by a bias circuit into a first voltage component (e.g., at a threshold voltage) and a second voltage component (at a FET drain-source saturation voltage or edge of saturation voltage). An input FET of the current mirror/scaler circuit can receive approximately the input current or a function thereof. A gate of the input FET can be biased at the first voltage component in sum with a FET drain-source saturation voltage or edge of saturation voltage of the input FET. A gate of the output FET can be connected to the gate of the input FET. A gate of a cascode FET in series with the output FET can be biased at the first voltage component in sum with the second voltage component in sum with the FET drain-source saturation voltage or edge of saturation voltage of the input FET. Multiple cascode FETs, multiple output stages, high frequency bypass capacitors, and lowpass filters are also described.

Description:
BACKGROUND 
     Current mirrors can be used in analog circuits for providing current bias or signals to a variety of circuits. The output impedance of the current mirror can affect the accuracy of the current provided by the current mirror. High output impedance in current mirrors is desired for accurate replication of currents. Cascode transistors can be used to obtain high output impedance. A current mirror may also be characterized as having an output voltage swing. High voltage swing in current mirrors can be desired for accurate operation, such as with low power supply voltages, and for increased voltage signal amplitudes, which can improve the accuracy of analog circuitry utilizing the current mirrors. 
     Current mirrors are building blocks used in integrated circuits. In CMOS technologies, current mirrors operate on the principle that if the gate-source voltages of two identical transistors are equal, then their drain currents are equal. A current mirror&#39;s output impedance can be represented by the slope of the output current when graphed against the output voltage—the smaller the slope, the higher the output impedance. A high output impedance can be desirable for a current mirror because parameters of the circuits with which the current mirror is used can be detrimentally affected by a low output impedance (e.g., the common-mode rejection ratio of a differential transistor pair can be worse with low output impedance of a current mirror sourcing or sinking current to the differential pair). A current mirror&#39;s compliance voltage range parameter provides a measure of the output voltage range over which the current mirror can maintain a constant output current. 
     One approach to achieving high output impedance for a current mirror is to use one or more cascode transistors in series with an output transistor of the current mirror. While the cascode transistors themselves do not consume current, additional circuits that consume current can be needed provide bias voltages for their gates. Moreover, if cascode gate bias voltages are not well-controlled for ensuring transistor operation at the lower end or edge of the saturation region, a substantial reduction in the compliance voltage range can occur. 
     SUMMARY/OVERVIEW 
     The present inventor has recognized, among other things, that one approach to limit current consumption for the cascode bias circuits in current mirrors is to use a self-biased cascode device, such as in which the input current itself can be used to bias one or more cascode devices. A challenge in providing one or more self-biased cascodes is to achieve a large compliance output voltage range and enough voltage margin, such as to accommodate process, temperature, and input-current variations. 
     This document describes, among other things, a device that can include a self-biased cascode current mirror/scaler circuit (“mirroring” can include providing an output current that is a scaled version of the input current, rather than an output current that is identical in magnitude to the input current). The self-biased cascode current mirror/scaler circuit can include a bias field-effect transistor (FET). The bias FET can have a drain electrically coupled to a gate, and having a source. The bias FET can be biased using a first input current to generate a gate-source bias voltage, Vgs, between the gate and the source of the bias FET. 
     A first bias circuit can be electrically coupled to the bias FET, such as to receive the Vgs provided by the bias FET. The first bias circuit can be arranged to divide Vgs into a first voltage component (which can be specified at a FET threshold voltage) and a second voltage component (which can be specified at a FET drain-source saturation voltage ΔVds). An input FET of the current mirror/scaler can have a drain electrically coupled to receive a drain current (which can optionally be approximately equal to a drain current of the bias FET, or a function thereof). A first output stage can include a first output FET, having a gate electrically coupled to apply the voltage at the gate of the input FET. A drain of the output FET can provide a first output current that is mirrored or scaled as a specified function of the first input current. A first cascode FET can be in series with the first output FET to pass the first output current between a drain and a source of the first cascode FET. A gate of the first cascode FET can be biased by the first bias circuit at a voltage that is equal to the second voltage component in sum with the first voltage component in sum with a FET drain-source saturation voltage ΔVds (e.g., of the input FET of the current mirror/scaler). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an example of a self-biased cascode current mirror. 
         FIG. 2  shows an example of a self-biased multiple-cascode current mirror circuit. 
         FIG. 3  shows an example of a self-biased cascode current mirror circuit. 
         FIG. 4  shows an example of a self-biased multiple-cascode current mirror circuit. 
         FIG. 5  shows an example of a self-biased cascode current mirror circuit with a bias circuit including a transistor configured to operate at a threshold voltage. 
         FIG. 6  shows an example of a self-biased multiple-cascode current mirror circuit with a bias circuit including a transistor configured to operate at a threshold voltage. 
         FIG. 7  shows an example of a self-biased multiple-cascode current mirror circuit with a bias circuit including a transistor configured to operate at a threshold voltage and including isolated-well type transistors. 
         FIG. 8  shows an example of a self-biased multiple-cascode current mirror circuit that can include multiple output stages to provide multiple output currents. 
         FIG. 9  shows an example of a self-biased multiple-cascode current mirror circuit that can include multiple output stages to provide multiple output currents, and including isolated-well type transistors. 
         FIG. 10  shows an example of a self-biased current mirror circuit in which the cascode transistor gates can be biased from a different input current than used to bias the output transistor gate. 
         FIG. 11  shows an example of a self-biased current mirror circuit that can include one or more high frequency bypass capacitors. 
         FIG. 12  shows an example of a self-biased multiple-cascode current mirror circuit that can include one or more high frequency bypass capacitors. 
         FIG. 13  shows an example of a self-biased current mirror circuit that can include a lowpass filter such as at a gate of a cascode device. 
         FIG. 14  shows a generalized example of a self-biased multiple cascode current mirror circuit that can include one or more lowpass filters such as at one or more gates of the cascode devices, or one or more high frequency bypass capacitors, or both. 
         FIG. 15  shows a differential generalized example, which can be regarded similar to the circuit in  FIG. 14 . 
         FIG. 16  shows an example of a single-ended-output operational transconductance amplifier (OTA), which can incorporate the self-biased current mirror/scaler, such as shown in the various examples herein. 
         FIG. 17  shows an example of a self-biased multiple-cascode current mirror/scaler, e.g., similar to the one shown in  FIG. 12 , which can be employed to provide the current mirror CM 0  in  FIG. 16 . 
         FIG. 18  shows an example of a differential-output operational transconductance amplifier. 
         FIG. 19  shows an example in which a self-biased multiple-cascode current mirror/scaler, e.g., similar to that shown in  FIG. 8 , can be employed as to provide the current source I 1  in  FIG. 18 . 
         FIG. 20  shows an approach for providing a generalized cascode circuit for generating cascode voltages V CAS2 , . . . , V CASN  in  FIG. 18 . 
         FIG. 21  shows an example of an improved approach (relative to that shown in  FIG. 20 ) for generating cascode voltages V CAS2 , . . . , V CASN  in  FIG. 18 , such as by using a self-biasing branch similar to the one used in the circuit of  FIG. 6 . 
         FIG. 22  shows an approach to a CMOS current mirror used for comparison in the computer-simulated plots of  FIGS. 23-30 . 
         FIGS. 23-25  show examples of the computer-simulated output current-voltage characteristics of the self-biased multiple-cascode current mirror circuit of  FIG. 7 . 
         FIG. 26  shows computer-simulated example of the output impedance z OUT  of four circuit variants. 
         FIGS. 27-29  show the computer-simulated examples of output current-voltage characteristics of the self-biased multiple-cascode current mirror circuit of  FIG. 7 , such as for different values of N 
         FIG. 30  shows an example of the computer-simulated output impedance z OUT  of four circuit variants. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows an example of a self-biased CMOS cascode current mirror. An input branch can include DC sources V 1  and V 2 , and transistor M 1 . An output branch can include replica transistors M R1 , M R2 . Voltages V 1  and V 2  can be chosen such that all transistors operate in the saturation region. If all the transistors are assumed identical, saturation is met if the following conditions apply:
 
 V   1   ≧V   T ,   (1)
 
 V   2   ≧V   DSAT ,   (2)
 
where V T  is the threshold voltage of the transistors and V DSAT  is their drain-source saturation voltage. For increased or maximum compliance output voltage range of the current mirror (e.g., lowest possible voltage equal to 2V DSAT,EOS  (at edge of saturation EOS) on output node E) and good current matching between input and output, voltages V 1  and V 2  should ideally assume their limit values, e.g., V 1 =V T  and V 2 =V DSAT,EOS , which can be difficult to achieve. It can also be very difficult to ensure conditions (1) and (2) for a wide range of input currents. Process and temperature variations should also be accommodated, which can introduce additional restrictions.
 
       FIG. 2  shows an illustrative example of a self-biased multiple-cascode current mirror circuit. In the generalized example of  FIG. 2 , an N≧1 number of identical output cascode devices M Rk , k=1, . . . , N, can be used in the output branch, such as for an improved output impedance z OUT . The gates of the output transistors M Rk  can be connected to the intermediate nodes of a chain of ideally-equal voltage sources V 2 =V 3 = . . . =V N ≧V DSAT ; voltage V 1  can be chosen such that is satisfies condition (1). In this way, all transistors in  FIG. 2  can operate in saturation, and a substantially higher output impedance z OUT  can obtained for larger N. Again, using certain circuits, it can be very difficult to ensure proper values for the voltages V 1 , V 2 , . . . , V N , such that all transistors operate at the lower limit of the saturation region V DSAT,EOS  for maximum compliance output voltage range. The minimum achievable output voltage for the circuit in  FIG. 2  is N·V DSAT . 
       FIG. 3  shows an example of a self-biased cascode current mirror circuit. In an example, the circuit can include an input branch that can include transistors M 1 , M 2  and resistors R 1 , R 2 , and an output branch that can include transistors M R1 , M R2 . The transistors can be assumed to be identical (e.g., have same transconductance parameter K′, width W, length L, and threshold voltage V T ), and the body effect (generally responsible for an undesirable increase in threshold voltage when the source node is at higher potential than the substrate node) can be assumed negligible. Resistors R 1  and R 2  can be assumed large enough such that input current I IN  flows mainly through transistor M 2  and only a small fraction of it through the resistors, such that 
                   V     GS   ⁢           ⁢   2           R   1     +     R   2         ⁢     &lt;&lt;     I   IN         ,         
where V GS2 =V C −V B  (difference between voltages on nodes C and B). In an example, R 1  and R 2  can be used to generate the voltages V 1  and V 2  in the diagram of  FIG. 1  as fractions of the gate-source voltage V GS2 , such that all transistors operate in saturation. In an example in which current I IN  serves as drain current for both M 1  and M 2 , assuming that proportionality factor
 
             α   =         R   2         R   1     +     R   2         &lt;   1           
is chosen large enough such that M 1  operates in saturation (M 2  operates in saturation because of the diode connection), the following equation applies:
 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       
                         GS 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     = 
                     
                       
                         V 
                         
                           GS 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       = 
                       
                         
                           V 
                           T 
                         
                         + 
                         
                           
                             
                               2 
                               ⁢ 
                               
                                 I 
                                 IN 
                               
                             
                             β 
                           
                         
                       
                     
                   
                   , 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       where 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       β 
                     
                     = 
                     
                       
                         K 
                         ′ 
                       
                       ⁢ 
                       
                         
                           W 
                           L 
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     The condition for transistor M 1  to operate in saturation is V DS1 ≧V GS1 −V T , which, using the node notations in  FIG. 3 , is equivalent to V B ≧V GS1 −V T . Using Eqn. (3), this can be re-written as: 
     
       
         
           
             
               
                 
                   
                     V 
                     B 
                   
                   ≥ 
                   
                     
                       
                         
                           2 
                           ⁢ 
                           
                             I 
                             IN 
                           
                         
                         β 
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     At the same time, however, V B =V A −(1−α)V GS2 , and V A =V GS1 =V GS2 , which yields:
 
 V   B   =V   GS2 −(1−α) V   GS2   =αV   GS2 .  (5)
 
     Using (3) and (5), the condition (4) for M 1  to operate in saturation is re-written as: 
     
       
         
           
             
               
                 
                   
                     
                       α 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         V 
                         
                           GS 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                     ≥ 
                     
                       
                         
                           2 
                           ⁢ 
                           
                             I 
                             IN 
                           
                         
                         β 
                       
                     
                   
                   ; 
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       α 
                       ⁡ 
                       
                         ( 
                         
                           
                             V 
                             T 
                           
                           + 
                           
                             
                               
                                 2 
                                 ⁢ 
                                 
                                   I 
                                   IN 
                                 
                               
                               β 
                             
                           
                         
                         ) 
                       
                     
                     ≥ 
                     
                       
                         
                           2 
                           ⁢ 
                           
                             I 
                             IN 
                           
                         
                         β 
                       
                     
                   
                   ; 
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     α 
                     = 
                     
                       
                         
                           
                             R 
                             2 
                           
                           
                             
                               R 
                               1 
                             
                             + 
                             
                               R 
                               2 
                             
                           
                         
                         ≥ 
                         
                           α 
                           min 
                         
                       
                       = 
                       
                         
                           
                             
                               2 
                               ⁢ 
                               
                                 I 
                                 IN 
                               
                             
                             β 
                           
                         
                         
                           
                             V 
                             T 
                           
                           + 
                           
                             
                               
                                 2 
                                 ⁢ 
                                 
                                   I 
                                   IN 
                                 
                               
                               β 
                             
                           
                         
                       
                     
                   
                   ; 
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       R 
                       2 
                     
                     
                       R 
                       1 
                     
                   
                   ≥ 
                   
                     
                       1 
                       
                         V 
                         T 
                       
                     
                     ⁢ 
                     
                       
                         
                           
                             2 
                             ⁢ 
                             
                               I 
                               IN 
                             
                           
                           β 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     With all transistors in  FIG. 3  assumed identical and conducting the same current, we have V GSR1 =V GSR2 =V GS1 =V GS2 =V A , and the drain-source voltage of M R1  (assuming V E  is large enough so that M R2  is in saturation) can be calculated as:
 
 V   DSR1   =V   D   =V   A   +αV   GS2   −V   GSR2   =αV   GS2   =V   B   =V   DS1   (10)
 
     Because V DSR1 =V DS1  (from (10)), it follows that meeting condition (9) ensures operation in the saturation region for both M 1  and M R1 . 
     If α=α min  (e.g., as defined in (8)), all transistors can operate at the lower limit of the saturation region (“edge of saturation” or “EOS”). The voltage developed across R 2  is a fraction (a) of a gate-source voltage (V GS2 ), which is not a strong function of I IN , allowing the circuit to tolerate a much wider input current range than certain other approaches. Although condition (9) can be met for a relatively wide input current range, process and temperature variations (which affect V T  and β) will introduce limitations, and 
               R   2       R   1           
can be chosen sufficiently large in order for (9) to be met under all conditions.
 
       FIG. 4  shows another example, which is a generalization of the self-biased cascode concept of  FIG. 3 , using an N≧2 number of identical output cascode devices. In  FIG. 4 , as in  FIG. 3 , the input current I IN  can be mainly accommodated by transistor M 2  due to the fact that R 1  and R 2  can be assumed large enough such that 
                 V     GS   ⁢           ⁢   2           R   1     +     R   2         ⁢       &lt;&lt;     I   IN       .           
In addition to the circuit of  FIG. 3 , the input branch can include additional equal resistors R 3 , . . . , R N  (and equal to R 2 ) such as for biasing the gates of additional identical transistors M R3 , . . . , M RN , respectively. Because the drain of M 2  can be connected in such a way that only the current flowing through R 2  flows through R 3 , . . . , R N , the voltages developed across R 2 , R 3 , . . . , R N  are each equal to αV GS2 . In this way, the circuit can be regarded as conceptually similar to the circuit of  FIG. 2 , and condition (9) (with the same observations as for  FIG. 3 ) can be met for all transistors to operate in saturation.
 
       FIG. 5  shows another example that can provide a robust self-biased cascode current mirror. With all transistors assumed identical, resistor R 2  can be chosen very large such that practically the entire input current flows only through transistor 
                 M   2     ⁡     (           V     GS   ⁢           ⁢   2       -     V   T         R   2       ⁢     &lt;&lt;     I   IN         )       .         
At the same time, ignoring subthreshold conduction, body effect, velocity saturation, and other second-order behavior, because of the very small drain current of M 3 , it follows that V GS3 ≃V T . As a consequence, because M 1  and M 2  conduct practically the same drain current, the voltage across R 2  is V GS2 −V GS3 ˜V GS1 ˜V T =V DSAT . In this way, the circuit in  FIG. 5  can be regarded as conceptually similar to the circuit in  FIG. 1 , with V 1 ˜V T , and V 2 ≃V DSAT , which are the ideal conditions for all the transistors to operate at the limit (edge) of the saturation region. In this example, the requirements for operation on saturation can be met regardless of process parameters (V T  or β). In this way, the circuit can operate with all the transistors at the edge of the saturation region regardless of current I IN . Practically, limitations occur at the low end of the current range where maintaining
 
                   V     GS   ⁢           ⁢   2       -     V   T         R   2       ⁢     &lt;&lt;     I   IN             
can be problematic, and at the higher end of the range where velocity saturation and possible headroom issues can tend to come into play.
 
       FIG. 6  shows another example, which can be regarded as a generalization of the self-biased cascode circuit concept of  FIG. 5 , for an N≧2 number of output cascode devices. With the exception of transistor M 3  in lieu of resistor R 1 , the circuit of  FIG. 6  can be topologically identical to the circuit of  FIG. 4  and can operate under the same general principles as the circuit in  FIG. 2 . In certain examples with large N, circuit adjustments can be made to the circuit of  FIG. 6  for further robustness. For example, resistor R 2  can be adjusted such that M 3  operates slightly in subthreshold, and M 2  can be slightly undersized relative to 
               M   1     ⁡     (         W   2       L   2       ≤       W   1       L   1         )           
such that the voltage drops across R 2 , R 3 , . . . , R N  are slightly larger than V DSAT,EOS .
 
       FIG. 7  shows an example that is similar to the circuit of  FIG. 6 , but in which the transistors can be isolated-well type such as for insensitivity to body effect and better precision. 
       FIGS. 8 and 9  show other examples (using bulk and isolated-well transistors, respectively), which detail the connection of more than one output branch to the same input branch. 
       FIG. 10  shows an example of a current-amplifying multiple-cascode current mirror/scaler. The input branch can include input transistor M 1  and input cascode transistor M 2 . A bias branch of a bias circuit can include bias transistors M BIAS1 , M BIAS2 , M BIAS3 , and resistors R BIAS2 , R BIAS3 , . . . , R BIASN , such as in an arrangement similar to the input branch in  FIG. 6 . The output cascode devices M R2 , M R3 , . . . , M RN  can receive their gate voltages from the bias branch. The current through transistor M 1  can be mirrored by the (optionally scaled) transistor M R1  and applied to the output such as via the cascode devices, which can be biased close to the edge of the saturation region by the bias branch. The bias branch can be sized such that the cascode devices can operate at the maximum current without exiting the saturation region. 
       FIG. 11  shows an example of a self-biased cascode current amplifier. All capacitors (each can be as large as several picoFarads) are optional, and can provide additional low-impedance paths at high frequencies. With capacitor C 1  providing a short-circuit at the frequencies of interest, transistor M 1  can be diode-connected and can accommodate the signal component of i IN  via the indicated path. At high frequencies, without C 2  in the circuit, the small input impedance of the amplifier can be provided by the equivalent diode-connected transistors M 1  and M 2 ; with C 2  in the circuit and shorting M 2  at high frequencies, the input impedance reduces to the equivalent resistance of diode-connected M 1  only. As in a regular current mirror, current amplification can be achieved by scaling M R1  (and implicitly M R2 ) relative to M 1  and M 2 . 
       FIG. 12  shows an example of a self-biased multiple-cascode current amplifier, which can be regarded as a generalization of the circuit in  FIG. 11  for an N≧2 number of output cascode devices. Capacitors C 1 , C 2 , . . . , C N  (each can be as large as several pF) are optional and behave like short-circuits at high-frequencies. At high frequencies, without C 2  in the circuit, the small input impedance of the amplifier can be ensured by the equivalent diode-connected transistors M 1  and M 2 ; with C 2  in the circuit and shorting M 2  at high frequencies, the input impedance reduces to the equivalent resistance of diode-connected M 1  only. Current amplification can be achieved by scaling M R1  (and implicitly M R2 , . . . , M RN ) relative to M 1  and M 2 . 
       FIG. 13  shows another example, which can be regarded as a variant of the circuit shown in  FIG. 11 . In an example, an additional gate resistor R MR2  (e.g., on the order of 10 KΩ or larger) and gate capacitor C MR2  (e.g., as large as several pF) can be connected to the gate of M R2 , such as to provide a virtual short-circuit on the gate of M R2  at high frequencies. 
       FIG. 14  shows an example of a generalization for an N≧2 number of output cascode devices. In an example, additional resistors R MR3 , . . . , R MRN  and additional capacitors C MR3 , . . . , C MRN  can be connected to the gates of additional cascodes M R3 , . . . , M RN , such as for providing short circuits to ground at high frequencies. 
       FIG. 15  shows a differential example, which can be regarded similar to the circuit in  FIG. 14 . In the example of  FIG. 15 , the input current signals can be of the form i IN+ (t)=I DC +I IN  cos(ω 0 t+Φ 0 ) and i IN− (t)=I DC −I IN  cos(ω 0 t+Φ 0 ), which, owing to circuit symmetry, can help ensure that the midpoints of the circuits are signal virtual grounds. In this way, no additional capacitors need be required on the gates of cascode transistors M RA2 , . . . , M RAN  and M RB2 , . . . , M RBN . 
       FIG. 16  shows an example of a single-ended-output operational transconductance amplifier (OTA), which can incorporate the self-biased current mirror/scaler, such as shown in the various examples herein. 
       FIG. 17  shows an example of a self-biased multiple-cascode current mirror/scaler, e.g., similar to the one shown in  FIG. 12 , can be employed to provide the current mirror CM 0  in  FIG. 16 . 
       FIG. 18  shows an example of a differential-output operational transconductance amplifier in which the common-mode circuit for adjusting either I 0  or I 1  is omitted for clarity. 
       FIG. 19  shows an example in which a self-biased multiple-cascode current mirror/scaler, e.g., similar to that shown in  FIG. 8 , can be employed as to provide the current source I 1  in  FIG. 18 . 
       FIG. 20  shows an approach for providing a generalized cascode circuit for generating cascode voltages V CAS2 , . . . , V CASN  in  FIG. 18 . The approach shown in  FIG. 20  can use multiple cascode bias currents I C2 , . . . , I CN , as well as a multiplicity of devices with unwieldy geometries M C2 , . . . , M CN . The current through the main amplifying devices M A1  and M B1  is obtained as the difference between I 0 (=2I 1 ) and (I C2 + . . . +I CN ), which can be difficult to control. 
       FIG. 21  shows an example of an improved approach for generating cascode voltages V CAS2 , . . . , V CASN  in  FIG. 18 , such as by using a self-biasing branch similar to the one used in the circuit of  FIG. 6 . In an example, only one bias current is used for the cascode bias branch, all transistors have similar geometries, and the current through the main amplifying devices M A1  and M B1  is better controlled, being the difference between I 0 (=2I 1 ) and just one current, I 2 . 
       FIG. 22  shows an approach to a CMOS current mirror used for comparison in the plots of  FIGS. 23-30 . 
       FIGS. 23-25  show examples of the computer-simulated output current-voltage characteristics of the self-biased multiple-cascode current mirror circuit of  FIG. 7 , such as for different values of N (N=1 corresponds to the current mirror circuit of  FIG. 22 ) and input currents (25 μA, 100 μA, and 400 μA, respectively). In these examples, all transistors are high-voltage devices in a 65 nm CMOS process, with W=20 μm, L=0.5 μm; M 2  is slightly undersized for additional cascode headroom, having W=15 μm, L=0.5 μm. Resistors R 2 , . . . , R N  are 15 KΩ each. All cascoded current mirrors operate very well with minimal voltage headroom for the cascode devices, over a wide range of input currents. 
       FIG. 26  shows computer-simulated example of the output impedance z OUT  of the four circuit variants under consideration; a substantial improvement in z OUT  can be achieved as N is increased. All computer-simulated circuits exhibit robustness over temperature and process. 
       FIGS. 27-29  show the computer-simulated output current-voltage characteristics of the self-biased multiple-cascode current mirror circuit of  FIG. 7 , such as for different values of N (N=1 corresponds to the current mirror circuit of  FIG. 22 ) and input currents (25 μA, 100 μA, and 400 μA, respectively). All transistors are low-voltage devices in a 65 nm CMOS process, with W=4 μm, L=0.1 μm; M 2  is slightly undersized for additional cascode headroom, having W=3.2 μm, L=0.1 μm. Resistors R 2 , . . . , R N  are 50 KΩ each. All computer-simulated cascoded mirrors operate very well with minimal headroom required for the cascode devices, over a wide range of input currents. 
       FIG. 30  shows an example of the computer-simulated output impedance z OUT  of the four circuit variants under consideration; a substantial improvement in z OUT  can be achieved as N is increased. All computer-simulated circuits exhibit robustness over temperature and process. 
     The present description has described biasing and operation in terms of a FET drain-source saturation voltage, V DSAT  or ΔVds in saturation. To provide a wider range of output voltages that can be tolerated by the current mirror/scaler, it may be desirable to provide such biasing with the FET drain-source saturation voltage, V DSAT  or ΔVds at the edge of saturation (EOS), however, this is not required, even though it is desirable. 
     Moreover, although certain devices have been described as “replicas,” it is understood that scaled replica devices can be provided, and that such scaling can be accomplished in a number of ways, such as by scaling the W/L ratios of the FETs, or by using a desired number of like parallel input FETs and a desired number of like parallel output FETs of the current mirror/scaler to obtain a desired current scaling. 
     Further, although the cascode FETs have been described together with the output FETs as “replicas” it is understood that this is not required. For example, a longer channel length output FET can be used together with one or more shorter channel cascode FETs in series therewith, which will increase the output impedance of the circuit, but can allow increased voltage swing by establishing a different ΔVds in saturation for the one or more cascode FETs than for the output FET, if desired. 
     The foregoing description and drawings of embodiments are merely illustrative of the principles of the invention. Various modifications can be made to the embodiments by those skilled in the art without departing from the scope of the invention, which is defined in the appended claims.