Abstract:
A digital sample and hold circuit for memorizing the initial voltage across an electrical resistance probe which is partly immersed in the liquid in a tank.

Description:
BACKGROUND AND SUMMARY OF THE INVENTION 
     This invention relates generally to devices which check the level of a liquid in a tank by utilizing a partially submerged electrical resistance probe. More particularly this invention relates to a digital sample and hold circuit which memorizes the initial voltage across the electrical resistance probe. 
     Electrical resistance or hot-wire fluid level detection systems depend on the detection of probe resistance increase resulting from the application of a test current. The hot wire is mounted in a probe which in turn is positioned in the fluid to be monitored. The positive temperature coefficient characteristic of the hot wire produces a probe resistance increase when the test current is applied. The magnitude of this increase is proportional to the percentage of the hot wire element which is not immersed in fluid. 
     The sequence of electrical events which describe the complete fluid level sensing system are the application of current to the probe during the very short test interval, memorization of the initial voltage developed across the probe, measurement of the amplitude of the resistance change, comparison of the resistance change to a preselected threshold and the triggering of a warming signal when the fluid level is below the level corresponding to the preselected threshold. 
     In order to prevent the system from responding to resistance changes attrributable solely to the temperature of the probe environment, it is necessary to measure and memorize the initial resistance of the probe at the moment current is initially applied and to compare that initial resistance to the final resistance at the end of the test interval. 
     The warning threshold is selected to be between the energized probe&#39;s outputs representing the free air condition and the completely submersed condition. 
     Previous known designs have depended upon analog sample and hold circuits to memorize the initial probe resistance. Analog sample and hold circuits employ capacitors to retain a voltage proportional to the initial condition to be memorized. If the charge on the capacitor leaks off during the hold period, a memory error will occur. Conventional means to minimize the effects of this leakage effect are not cost effective. 
     Accordingly, it is an object of this invention to employ a digital sample and hold circuit to permit retention of any desired initial condition without the introduction of memory errors due to capacitor leakage. 
     Other objects and advantages of this invention will be made apparent as the description progresses. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawing in which one of various possible embodiments is illustrated: 
     The FIGURE is an electrical block diagram of the complete fluid sensor system. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The test interval is initiated at time t=0 by the application of a test current from a current source through switch means 24 energizing the probe 18 and the resistor path in parallel with the probe 18 formed by the series connection of 20 and 22. 
     The test current is applied for a total of approximately three seconds; it is during this time period that the sample and hold function occurs. 
     At time t=0, the output of the R-2R ladder network 15 is approximately equal to zero, the maximum output being approximately 5.0 volts. This zero level output of 15 is presented to the inverting input of operational amplifier 17 through an input resistor 26. The non-inverting input to operational amplifier 17 is presented with a fixed offset voltage 30 which is equal to approximately one-half of the peak output voltage of R-2R ladder network 15. 
     The result of these inputs to operational amplifier 17 at time t=0 is a high level output from 17 of approximately 4.5 volts. This high level voltage is presented to the inverting input of operational amplifier 12A. 
     The output of the probe 18 varies between 2.0 volts and 3.0 volts. Therefore, the non-inverting input to operational amplifier 12A is intially lower than the inverting input to 12A. The output of 12A is thus initially low and is presented to one input of NOR gate 13 while the output of clock generator 11 is presented to the other input of NOR gate 13. 
     The signal from clock 11 is therefore initially present on the output of NOR gate 13 and is presented to the input of counter 14 which is initially in the reset condition. The outputs of counter 14 are connected in the proper order to the inputs of R-2R ladder network 15. The output of R-2R ladder network 15 therefore increases with each count causing the output of operational amplifier 17 to decrease at a rate of approximately 20 millivolts per count. This is a typical system which utilizes an eight bit counter and a 5.0 volt counter supply voltage. The resolution is a function of the number of bits designed into the system. 
     When the output of operational amplifier 17, which is connected to the inverting input of operational amplifier 12A, drops below the non-inverting input of 12A, the output of 12A changes to a logical high voltage level. Since the output of 12A is connected to NOR gate 13, the output of NOR gate 13 is forced to a low level and pulses from clock 11 to counter 14 are interrupted 
     The output of operational amplifier 17 therefore holds at a level very close to the initial value of probe voltage and will remain held at this level for any increasing probe voltage, thus eliminating memory errors due to capacitor leakage associated with analog sample and hold circuits. 
     The threshold alarm point voltage is determined by a resistive divider network 20 and 22 across probe 18. The division point 32 of this divider is connected to the non-inverting input of operational amplifier 12B while the inverting input of operational amplifier 12B is connected to the memorized voltage at the output of the operational amplifier 17. It should be appreciated that alternative means can be used to achieve the threshold point. Voltage outputs across probe 18 which exceed this threshold alarm point voltage will cause the output of operational amplifier 12B to change to a high voltage level and provide a trigger for a suitable warning device. 
     An alternative embodiment of the sample and hold circuit described herein provides for a fluid level detector which tracks decreasing voltages by omitting operational amplifier 17, connecting the output of R-2R ladder network 15 to the non-inverting inputs of 12A and 12B and feeding the probe voltage into the inverting input to 12A and the voltage at division point 32 into the inverting input to 12B. 
     In view of the foregoing it will be seen that the several objects and other advantages are attained. 
     Although several embodiments of the invention have been disclosed and described, it is apparent that other embodiments and modifications of the invention are possible.