Abstract:
A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-128164, filed on May 15, 2008, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a data modulation circuit. 
       BACKGROUND 
       [0003]    In the past, ΔΣ modulation circuits (data modulation circuits) have been utilized for audios, A/D converters, etc. and, for example, have been used for converting analog signals or PCM digital signals to 1-bit signals (trains). 
         [0004]      FIG. 1A  and  FIG. 1B  are views illustrating an example of a conventional data modulation circuit and indicate a data modulation circuit applying primary ΔΣ modulation to modulate data. Note that  FIG. 1A  is a block diagram of a conventional data modulation circuit, while  FIG. 1B  is a view for explaining the operation of a selector in a conventional data modulation circuit. 
         [0005]    In  FIG. 1A , reference numerals  100  and  101  indicates adders,  102  a quantizer (comparator), and  103  and  104  D-type flip-flops (DFF). Here, the input signal Vin is, for example, made a 7-bit digital signal (signal of 28 to 100 minus predetermined bands at the minimum and maximum sides). 
         [0006]    As illustrated in  FIG. 1A , the input signal is input to the adder  100  where it added with the output signal AZ −1 [ 7 : 0 ] of the DFF  103 . The output signal of the adder  100  is input to the adder (subtractor)  101  where the output signal YZ −1 [ 8 : 0 ] of the DFF  104  input to the negative input of the adder  101  is subtracted (negative addition). 
         [0007]    Here, the DFF&#39;s  103  and  104  output the signal (Z −1 ) delayed by exactly one cycle of the clock signal from the input signal. Further, the signal Y[ 1 : 0 ] is the output signal Vout[ 1 : 0 ] of the output circuit part  102 , while the signal A[ 7 : 0 ] is the output signal of the adder  101 . Note that [ 8 : 0 ] indicates an 8-bit signal, [ 7 : 0 ] indicates a 7-bit signal, and [ 1 : 0 ] indicates a 1-bit signal. 
         [0008]    The adder  100 , for example, adds an input signal Vin[ 7 : 0 ] from 28 to 100 and the output of the DFF  103 , that is, the signal AZ −1 [ 7 : 0 ] has the processing signal A delayed by 1 clock. Further, the adder  101  subtracts from the output signal of the adder  100  the signal BZ −1 [ 8 : 0 ] having the processing signal AB output by the DFF  104  delayed by 1 clock. 
         [0009]    Further, the output circuit part  102  discriminates and quantizes the output signal A[ 7 : 0 ] of the adder  101  by a predetermined threshold value. That is, as illustrated in  FIG. 1B , the output circuit part  102 , for example, outputs Y[ 1 : 0 ]=00 in the case where the input signal (output signal of the adder  101 ) A[ 7 : 0 ] is “less than 0” (A 2 [ 7 : 0 ]&lt;0), outputs Y[ 1 : 0 ]=01 in the case where “0 to 63” (0≦B 2 [ 7 : 0 ]≦63), and outputs Y[ 1 : 0 ]=10 in the case where “64 to 128” (64≦B 2 [ 7 : 0 ]≦128). 
         [0010]    The selector  105  receives as input the output signal Y[ 1 : 0 ] of the output circuit part  102  and outputs the signal B[ 8 : 0 ]. Further, the output signal B[ 8 : 0 ] of the selector  105  is made, for example, B[ 8 : 0 ]=0 in the case where Y[ 1 : 0 ]=00, is made B[ 8 : 0 ]=64 in the case where Y[ 1 : 0 ]=01, and is made B[ 8 : 0 ]=128 in the case where Y[ 1 : 0 ]=10 by the output signal Y[ 1 : 0 ] of the output circuit part  102 . Further, the DFF  104  delays the signal B[ 8 : 0 ] by 1 clock and outputs the signal BZ −1 [ 8 : 0 ]. 
         [0011]      FIG. 2A  and  FIG. 2B  are views for explaining the operation of the data modulation circuit illustrated in  FIG. 1A , where  FIG. 2A  illustrates the change in the time-series signals (AZ −1 , A, Y[ 1 : 0 ], BZ −1 , B) for the first to 10 th  clocks  1  to  10  when inputting “100” to the input Vin, while  FIG. 2B  illustrates the change in the time-series signals for the first to 10 th  clocks  1  to  10  when inputting “28” to the input Vin. 
         [0012]    Here, if the input signal Vin is X and the quantized error of the output circuit part  102  is Q, the result becomes: 
         [0000]        A=AZ   −1   −YZ   −1   +X    (1) 
         [0000]        Y=A+Q    (2) 
         [0013]    If entering formula (2) into formula (1): 
         [0000]        Y−Q =( Y−Q ) Z   −1   −YZ   −1   +X    
         [0014]    Therefore, the following is obtained 
         [0000]        Y=X +(1− Z   −1 ) Q    (3) 
         [0015]    Note that Y[ 1 : 0 ]=00 indicates that the signal A is “0”, Y[ 1 : 0 ]=01 indicates that the signal A is “64”, and Y[ 1 : 0 ]=10 indicates that the signal A is “128”. 
         [0016]    In the case of the ΔΣ demodulator, if dividing the sum of the number of the Y[ 1 : 0 ]=01 of a certain time×64 and the number of Y[ 1 : 0 ]=10×128 by the number of clocks, it is possible to demodulate the input signal. 
         [0017]    Specifically, for example, in the case of  FIG. 2A , it is learned that there are six Y[ 1 : 0 ]=10 and four Y[ 1 : 0 ]=01 in 10 clocks, so (128×6+64×4)/10=102.4 and the input signal  100  can be expressed by a 1-bit signal. 
         [0018]    Further, for example, in the case of  FIG. 2B , it is learned that there are five Y[ 1 : 0 ]=01 and five Y[ 1 : 0 ]=00 in 10 clocks, so (64×5+0×5)/10=32 and the input signal  28  can be expressed by a 1-bit signal. 
         [0019]    Note that these values can express values approximating “100” and “28” as the number of clocks becomes greater. 
         [0020]    In this regard, in the past, as a ΔΣ demodulator able to maintain a high conversion precision (linearity) by a low over sampling ratio and reduce the number of analog devices, there is proposed one providing a digital ΔΣ demodulator at the back end of an analog ΔΣ demodulator and feeding back a signal obtained by delaying 1-bit output of the digital ΔΣ demodulator to the front-end analog ΔΣ demodulator (see, for example, Japanese Laid-open Patent Publication No. 2001-094429). 
         [0021]    Furthermore, in the past, there is also proposed a high speed over sample modulation circuit simplifying the quantizer so as to slash the number of bits of the processing circuit and realize multibit signal processing and high speed processing without increasing the circuit size (see, for example, Japanese Laid-open Patent Publication No. 2004-147074). 
         [0022]    This high speed over sample modulation circuit includes an adder for adding an input signal of a plurality of bits and a first feedback signal, and a subtractor subtracting a second feedback signal from a first signal of a predetermined number of bits at the higher side in the output signal from the adder. 
         [0023]    Further, the high speed over sample modulation circuit includes a first delay device, a quantizer and a second delay device. The first delay device delays a first signal having a second signal comprised of the remaining bits at the lower side of the output signal of the adder as its lower bits and having the output signal of the subtractor as its higher bits to output a first feedback signal. 
         [0024]    The quantizer receives a third signal as input for quantization processing and outputting a quantization signal of a predetermined number of bits, and the second delay device delays the quantization signal to output a second feedback signal. 
         [0025]    The quantizer is designed to select specific bits in the third signal to output the quantization signal. 
         [0026]    The conventional data modulation circuit explained with reference to  FIG. 1A ,  FIG. 1B ,  FIG. 2A , and  FIG. 2B  has to perform processing through the adders  100  and  101  and the output circuit part  102  from when the input signal Vin[ 7 : 0 ](X) is input to when the output signal Vout[ 1 : 0 ](Y[ 1 : 0 ]) is output. As systems become higher in speed and greater in number of bits, it becomes difficult for these processings to be completed within 1 clock. 
       SUMMARY 
       [0027]    According to an aspect of the embodiments, a data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. 
         [0028]    The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device. 
         [0029]    Additional objects and advantages of the embodiments will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiment. The object and advantages of the embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
         [0030]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the embodiments, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0031]      FIG. 1A  and  FIG. 1B  are views for explaining an example of a conventional data modulation circuit; 
           [0032]      FIG. 2A  and  FIG. 2B  are views for explaining the operation of the data modulation circuit illustrated in  FIG. 1A ; 
           [0033]      FIG. 3A  and  FIG. 3B  are views for explaining a first embodiment of the data modulation circuit; 
           [0034]      FIG. 4  is a circuit diagram illustrating an example of an output circuit part in the data modulation circuit illustrated in  FIG. 3A ; 
           [0035]      FIG. 5A  and  FIG. 5B  are first parts of a view for explaining the operation of the data modulation circuit illustrated in  FIG. 3A ; 
           [0036]      FIG. 6A  and  FIG. 6B  are second parts of a view for explaining the operation of the data modulation circuit illustrated in  FIG. 3A ; 
           [0037]      FIG. 7A  and  FIG. 7B  are views for explaining a data modulation circuit of a second embodiment; 
           [0038]      FIG. 8  is a circuit diagram illustrating an example of an output circuit part in the data modulation circuit illustrated in  FIG. 7A ; 
           [0039]      FIG. 9A  and  FIG. 9B  are views for explaining the operation of the data modulation circuit illustrated in  FIG. 7A ; 
           [0040]      FIG. 10A  and  FIG. 10B  are views for explaining a third embodiment of the data modulation circuit; 
           [0041]      FIG. 11A  and  FIG. 11B  is a view for explaining the operation of the data modulation circuit illustrated in  FIG. 10A ; 
           [0042]      FIG. 12A  and  FIG. 12B  are views for explaining a fourth embodiment of the data modulation circuit, 
           [0043]      FIG. 13A  and  FIG. 13B  are first parts of a view for explaining the operation of the data modulation circuit illustrated in  FIG. 12A , 
           [0044]      FIG. 14A  and  FIG. 14B  are second parts of a view for explaining the operation of the data modulation circuit illustrated in  FIG. 12A , 
           [0045]      FIG. 15A  and  FIG. 15B  is a view for explaining a fifth embodiment of the data modulation circuit, 
           [0046]      FIG. 16  is a circuit diagram illustrating an example of an output circuit part in the data modulation circuit illustrated in  FIG. 15A , 
           [0047]      FIG. 17  is a view for explaining a sixth embodiment of the data modulation circuit, and 
           [0048]      FIG. 18  is a view for explaining a seventh embodiment of the data modulation circuit. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0049]    Preferred embodiments of the data modulation circuit will be described in detail below while referring to the attached figures. 
         [0050]      FIG. 3A  and  FIG. 3B  are views for explaining a first embodiment of the data modulation circuit and indicate how a data modulation circuit applying primary ΔΣ modulation to modulate data. 
         [0051]    Note that in the embodiments explained below, the explanation will be given with reference to an example of a data modulation circuit applying primary ΔΣ modulation, but the embodiments can of course also be applied to secondary or higher ΔΣ modulation as well of course. 
         [0052]    Here,  FIG. 3A  is a block diagram of a data modulation circuit of a first embodiment, while  FIG. 3B  is a view for explaining the operation of a selector in the data modulation circuit of the first embodiment. In  FIG. 3A , reference numeral  200  indicates an adder,  201  an output circuit part,  202  a logic circuit part, and  203  a D-type flip-flop (DFF). Note that the input signal Vin[ 7 : 0 ] is for example a digital signal of a range of −128 to 127, while Vin[ 7 ] is a sign bit. 
         [0053]    Note that in the data modulation circuit of the first embodiment, the input signal Vin[ 7 : 0 ] is an integer in the range of −128 to 127. The quantization level is four levels. 
         [0054]    As illustrated in  FIG. 3A , the input signal Vin[ 7 : 0 ] is added by the adder  200  with the output signal B 4 [ 7 : 0 ] of the DFF  203  and outputs the signal B 2 [ 7 : 0 ] from the adder  200 . Further, the output circuit part  201  discriminates and quantizes the output signal B 2 [ 7 : 6 ] of the adder  200  by a predetermined threshold value. 
         [0055]    That is, as illustrated in  FIG. 3B , the output circuit part  201 , for example, for the input signal (output signal of the adder  200 ) B 2 [ 7 : 0 ], outputs Y[ 1 : 0 ]=00 in the case where −128≦B 2 [ 7 : 0 ]≦−65, outputs Y[ 1 : 0 ]=01 in the case where −64≦B 2 [ 7 : 0 ]≦−1, output Y[ 1 : 0 ]=11 in the case where 0≦B 2 [ 7 : 0 ]≦63, and outputs Y[ 1 : 0 ]=10 in the case where 64≦B 2 [ 7 : 0 ]≦127. 
         [0056]    In the 2-bit signal Y[ 1 : 0 ] output from the output circuit part  201 , the higher bit Y[ 1 ] is input to the DFF  203 , while the lower bit Y[ 0 ] is input to the logic circuit part  202 . 
         [0057]    The DFF  203  receives as input the 5-bit signal B 3 [ 5 : 0 ] from the adder  200 , the output signal from the logic circuit part  202  becoming the 6-bit signal B 3 [ 6 ], and the output signal Y[ 1 ] of the output circuit part  201  becoming the 7th bit signal B 3 [ 7 ] and outputs the above-mentioned 7-bit signal B 4 [ 7 : 0 ] to the adder  200 . Note that the signal B 2 [ 5 : 0 ] from the adder  200  becomes the B 3 [ 5 : 0 ] input to the DFF  203  as it is. 
         [0058]    Further, the logic circuit part  202  receives as input the 6 th  bit signal B 2 [ 6 ] from the adder  200  and the signal Y[ 0 ] from the output circuit part  201  and outputs the above-mentioned signal B 3 [ 6 ] to the DFF  203 . 
         [0059]    Note that logic circuit part  202  is for example comprised of two AND gates  221 ,  222  with one input made an inverted input and an OR gate  223 . The output signal B 3 [ 6 ] is obtained by the next formula (4): 
         [0000]        B 3[6]=/ B 2[6]· Y[ 0]+ B 2[6]·/ Y[ 0]  (4) 
         [0060]      FIG. 4  is a circuit diagram illustrating an example of the output circuit part in the data modulation circuit illustrated in  FIG. 3A . 
         [0061]    As illustrated in  FIG. 4 , the output circuit part  201  in the data modulation circuit of the first embodiment is provided with an inverter  211 , an AND gate  212  with both inputs made inverted inputs, an AND gate  213 , and a NOR gate  214 , receives the higher two bits B 2 [ 7 ] and B 2 [ 6 ] in the output B 2 [ 7 : 0 ] of the adder  200 , and outputs the signal Y[ 1 ] inverted from B 2 [ 7 ] and the signal Y[ 0 ] obtained by the next formula (5): 
         [0000]        Y[ 0]= B 2[6]· B 2[7]+/ B 2[6]·/ B 2[7]  (5) 
         [0062]    Further, in the first embodiment, the DFF  203  delays the input signal B 3 [ 7 : 0 ] by 1 clock&#39;s worth of time and supplies the signal B 4 [ 7 : 0 ] to the adder  200  and thereby can realize high speed operation without causing a large increase in the circuit compared with the conventional data modulation circuit illustrated in  FIG. 1A . 
         [0063]      FIG. 5A ,  FIG. 5B ,  FIG. 6A , and  FIG. 6B  are views for explaining the operation of the data modulation circuit illustrated in  FIG. 3A . 
         [0064]      FIG. 5A  illustrates the changes in the time-series signals (B 4 , B 2 , B 3 , Y[ 1 : 0 ]) for the first to 10 th  clocks  1  to  10  when inputting “100” to the input signal Vin, while  FIG. 5B  illustrates the changes in the time-series signals for the first to 10 th  clocks  1  to  10  when inputting “28” to the input signal Vin. 
         [0065]    Furthermore,  FIG. 6A  illustrates the change of the time-series signals for the first to 10 th  clocks  1  to  10  when “−28” is input to the input Vin, while  FIG. 6B  illustrates the change of the time-series signals for the first to 10 th  clocks  1  to  10  when “−100” is input to the input Vin. Note that in the figures, Vin, B 4 , B 2 , and B 3  are expressed by decimal numbers, while Y[ 1 : 0 ] is expressed by a binary number. 
         [0066]    As illustrated in the above-mentioned  FIG. 3A , when Y[ 1 : 0 ]=00, B 2  indicates −128, when Y[ 1 : 0 ]=01, B 2  indicates −64, when Y[ 1 : 0 ]=11, B 2  indicates 64, and when Y[ 1 : 0 ]=10, B 2  indicates 128. 
         [0067]    In the case of  FIG. 5A , there are zero Y[ 1 : 0 ]=00, zero Y[ 1 : 0 ]=01, four Y[ 1 : 0 ]=11, and six Y[ 1 : 0 ]=10 in 10 clocks, the following calculation formula stands: 
         [0000]        V out=((−128)×0+(−64)×0+64×4+128×6)/10 
         [0000]    and the figure of Vout=102.4 can be calculated. 
         [0068]    That is, inherently, the output is 2 bits, so only a signal from 0 to 3 can be expressed, but by using a ΔΣ demodulator, a value approximating “100” is obtained. 
         [0069]    Further, in the case of  FIG. 5A , there are zero Y[ 1 : 0 ]=00, four Y[ 1 : 0 ]=01, three Y[ 1 : 0 ]=11, and three Y[ 1 : 0 ]=10 in 10 clocks, the following calculation formula stands: 
         [0000]        V out=((−128)×0+(−64)×4+64×3+128×3)/10 
         [0000]    Vout=32, and a value approximating “28” is obtained. 
         [0070]    Further, in the case of  FIG. 6A , there are three Y[ 1 : 0 ]=00, three Y[ 1 : 0 ]=01, four Y[ 1 : 0 ]=11, and zero Y[ 1 : 0 ]=10 in 10 clocks, the following calculation formula stands: 
         [0000]        V out=((−128)×3+(−64)×3+64×4+128×0)/10 
         [0000]    Vout=−32, and a value approximating “−28” is obtained. 
         [0071]    Further, in the case of  FIG. 6B , there are six Y[ 1 : 0 ]=00, four Y[ 1 : 0 ]=01, zero Y[ 1 : 0 ]=11, and zero Y[ 1 : 0 ]=10 in 10 clocks, the following calculation formula stands: 
         [0000]        V out=((−128)×6+(−64)×4+64×0+128×0)/10 
         [0000]    Vout=−102.4, and a value approximating “−100” is obtained. 
         [0072]    In this way, inherently the output is two bits, so only a signal from 0 to 3 can be expressed, but by using the ΔΣ demodulator, it is learned that it is possible to obtain values approximating “100”, “128”, “−28”, and “100”. Note that these values were calculated by 10 clocks, but the greater the number of clocks, the smaller the error. 
         [0073]      FIG. 7A  and  FIG. 7B  are views for explaining a second embodiment of the data modulation circuit. Here,  FIG. 7A  is block diagram of a data modulation circuit of a second embodiment, further  FIG. 7B  is a view for explaining the operation of the selector in the data modulation circuit of the second embodiment. 
         [0074]    In  FIG. 7A , reference numeral  300  indicates an adder,  301  an output circuit part,  302  a first logic circuit part,  303  a D-type flip-flop (DFF), and  304  a second logic circuit part. Note that the input signal Vin[ 7 : 0 ] is a digital signal of for example the range of positive integers (0 to 127). 
         [0075]    As illustrated in  FIG. 7A , the input signal Vin[ 7 : 0 ] is added by the adder  300  with the output signal B 4 [ 7 : 0 ] of the DFF  303 , whereupon the adder  300  outputs the signal B 2 [ 7 : 0 ]. Further, the output circuit part  301  discriminates and quantizes the output signal B 2 [ 7 : 6 ] of the adder  300  by a predetermined threshold value. 
         [0076]    That is, as illustrated in  FIG. 7B , the output circuit part  301 , for example, for the input signal (output signal of the adder  300 ) B 2 [ 7 : 0 ], outputs Y[ 1 : 0 ]=00 in the case where B 2 [ 7 : 0 ]≦0, outputs Y[ 1 : 0 ]=11 in the case where  0 &lt;B 2 [ 7 : 0 ]≦63, and outputs Y[ 1 : 0 ]=10 in the case where 64≦B 2 [ 7 : 0 ]≦127. 
         [0077]    In the 2-bit signal Y[ 1 : 0 ] output from the output circuit part  301 , the higher bit Y[ 1 ] is input to the second logic circuit part  304 , while the lower bit Y[ 0 ] is input to the first logic circuit part  302 . 
         [0078]    The DFF  303  receives as input the 5-bit signal B 3 [ 5 : 0 ] from the adder  300 , the output signal of the first logic circuit part  302  becoming the 6th bit signal B 3 [ 6 ], and the output signal of the second logic circuit part  304  becoming the 7th bit signal B 3 [ 7 ] and outputs the above-mentioned 7-bit signal B 4 [ 7 : 0 ] to the adder  300 . Note that the signal B 2 [ 5 : 0 ] from the adder  300  becomes the B 3 [ 5 : 0 ] input to the DFF  303  as it is. 
         [0079]    Further, the first logic circuit part  302  receives as input the 6 th  bit signal B 2 [ 6 ] from the adder  300  and the signal Y[ 0 ] from the output circuit part  301  and outputs the above-mentioned signal B 3 [ 6 ] to the DFF  303 . Note that the first logic circuit part  302 , like the logic circuit part  202  of the above-mentioned first embodiment, for example is comprised of two AND gates  321  and  322  with one input made an inverted input and an OR gate  323 . The output signal B 3 [ 6 ] is obtained by the above-mentioned formula (4). 
         [0080]    Further, the second logic circuit part  304  receives as input the 7 th  bit signal B 2 [ 7 ] from the adder  300  and the signal Y[ 1 ] from the output circuit part  301  and outputs the above-mentioned signal B 3 [ 7 ] to the DFF  303 . Note that the second logic circuit part  304  is, for example, comprised of two AND gates  341  and  342  with one input made an inverted input and an OR gate  343 . The output signal B 3 [ 7 ] is obtained by the next formula (6): 
         [0000]        B 3[7]=/ B 2[7]· Y[ 1]+ B 2[7]·/ Y[ 1]  (6) 
         [0081]      FIG. 8  is a circuit diagram illustrating an example of the output circuit part in the data modulation circuit illustrated in  FIG. 7A . 
         [0082]    As illustrated in  FIG. 8 , the output circuit part  301  in the second embodiment is comprised of two inverters  311  and  312 , while the output signals Y[ 0 ] and Y[ 1 ] become signals inverted in logic from the input signals B 2 [ 6 ] and B 2 [ 7 ]. 
         [0083]    That is, since the input signal Vin[ 7 : 0 ] is a digital signal of the range of positive integers (0 to 127), when the quantization level is 64, the output circuit part  301  becomes a simple circuit making the signals of the higher bits B 2 [ 7 ] and B 2 [ 6 ] inverted (outputting “1”, when the input becomes “0” and outputting “0” when the input becomes “1”) Y[ 1 ] and Y[ 0 ] thereby enabling much faster speed. 
         [0084]      FIG. 9A  and  FIG. 9B  are views for explaining the operation of the data modulation circuit illustrated in  FIG. 7A , where  FIG. 9A  illustrates the changes in the time-series signals (B 4 , B 2 , B 3 , Y[ 1 : 0 ]) for the first to 10 th  clocks  1  to  10  when inputting “100” to the input signal Vin, while  FIG. 9B  illustrates the changes in the time-series signals for the first to 10 th  clocks  1  to  10  when inputting “28” to the input signal Vin. Note that in the figures, Vin, B 4 , B 2 , and B 3  are expressed by decimal numbers, while Y[ 1 : 0 ] is expressed by a binary number. 
         [0085]    In the case of  FIG. 9A , there are zero Y[ 1 : 0 ]=00, zero Y[ 1 : 0 ]=01, four Y[ 1 : 0 ]=11, and six Y[ 1 : 0 ]=10 in 10 clocks, the following calculation formula stands: 
         [0000]        V out=(64×4+128×6)/10 
         [0000]    and the figure of Vout=102.4 can be calculated. 
         [0086]    Further, in the case of  FIG. 9B , there are five Y[ 1 : 0 ]=00, zero Y[ 1 : 0 ]=01, five Y[ 1 : 0 ]=11, and zero Y[ 1 : 0 ]=10 in 10 clocks, the following calculation formula stands: 
         [0000]        V out=(0×5+64×5)/10 
         [0000]    Vout=32, and a value approximating “28” is obtained. Note that these values were calculated by 10 clocks, but the larger the number of clocks, the smaller the error of course. 
         [0087]      FIG. 10A  and  FIG. 10B  are views for explaining a third embodiment of the data modulation circuit. Here,  FIG. 10A  is a block diagram of the data modulation circuit of the third embodiment, while  FIG. 10B  is a view for explaining the operation of the selector in the data modulation circuit of the third embodiment. 
         [0088]    In  FIG. 10A , reference numeral  400  indicates an adder,  401  indicates an output circuit part, and  403  indicates a DFF. Note that the data modulation circuit of the third embodiment indicates a circuit enabling even higher speed operation when the input signal Vin[ 7 : 0 ] is a digital signal of the range of positive integers (0 to 127) and the quantization level is 3. 
         [0089]    As illustrated in  FIG. 10A , in the data modulation circuit of the third embodiment, the signal Y[ 1 : 0 ] of the output circuit part  401  is not made the input of the DFF  403 , while the input signal B 3 [ 7 : 0 ] of the DFF  403  is comprised of the signal B 2 [ 5 : 0 ] from the adder  400  and the signals B 3 [ 6 ] and B 3 [ 7 ] fixed to the high level “1”. Note that the B 3 [ 7 ]=1′b1 in  FIG. 10A  indicates to set 1 bit of the most significant bit B 3 [ 7 ] input to the DFF  403  to the high level “1”. 
         [0090]    As illustrated in  FIG. 10A , the input signal Vin[ 7 : 0 ] is added by the adder  400  with the DFF  403  output signal B 4 [ 7 : 0 ], whereby the adder  400  outputs the signal B 2 [ 7 : 0 ]. Further, the output circuit part  401  discriminates and quantizes the output signal B 2 [ 7 : 6 ] of the adder  400  by a predetermined threshold value. 
         [0091]    That is, as illustrated in  FIG. 10B , the output circuit part  401 , for example, for the input signal (output signal of the adder  400 ) B 2 [ 7 : 0 ], outputs Y[ 1 : 0 ]=00 in the case where B 2 [ 7 : 0 ]&lt;0, outputs Y[ 1 : 0 ]=11 in the case where 0≦B 2 [ 7 : 0 ]≦63, and outputs Y[ 1 : 0 ]=10 in the case where 64≦B 2 [ 7 : 0 ]≦127. 
         [0092]    Note that the critical path of timing in the data modulation circuit of the third embodiment can be said to be suited to higher speeds since the delay of the adder  400  need only be completed within 1 clock. 
         [0093]      FIG. 11A  and  FIG. 11B  are views for explaining the operation of the data modulation circuit illustrated in  FIG. 10A , where  FIG. 11A  illustrates the changes in the time-series signals (B 4 , B 2 , B 3 , Y[ 1 : 0 ]) for the first to 10 th  clocks  1  to  10  when inputting “100” to the input signal Vin, while  FIG. 11B  illustrates the changes in the time-series signals for the first to 10 th  clocks  1  to  10  when inputting “2” to the input signal Vin. 
         [0094]    As illustrated in  FIG. 11A , it is learned that when the input signal Vin is “100”, there are four Y[ 1 : 0 ]=11 and six Y[ 1 : 0 ]=10 and when Vout=102.4, a value approximating “100” is obtained. 
         [0095]    Further, as illustrated in  FIG. 11B , it is learned that when the input signal Vin is “28”, there are five Y[ 1 . 0 ]=00 and five Y[ 1 : 0 ]=11 and when Vout=32, a value approximating “28” is obtained. 
         [0096]      FIG. 12A  and  FIG. 12B  are views for explaining a fourth embodiment of the data modulation circuit. In the above third embodiment, an example of the case where the input signal Vin[ 7 : 0 ] was made a digital signal of the range of the integers (128 to 127) including also negative values. Here,  FIG. 12A  is a block diagram of the data modulation circuit of the fourth embodiment, while  FIG. 12B  is a view for explaining the operation of a selector in the data modulation circuit of the fourth embodiment. 
         [0097]    In  FIG. 12A , reference numeral  500  indicates an adder,  501  an output circuit part,  502  an inverter, and  503  a DFF. 
         [0098]    As illustrated in  FIG. 12A , even in the data modulation circuit of the fourth embodiment, the signal Y[ 1 : 0 ] from the output circuit part  501  is not made the input of the DFF  503 , while the input signal B 3 [ 7 : 0 ] of the DFF  503  is comprised of the signal B 2 [ 5 : 0 ] from the adder  500  and the signals B 3 [ 6 ] and B 3 [ 7 ] obtained by inverting the signal B 2 [ 7 ] from the adder  500  by the inverter  502 . 
         [0099]    As illustrated in  FIG. 12A , the input signal Vin[ 7 : 0 ] is added by the adder  500  with the output signal B 4 [ 7 : 0 ] of the DFF  503 , whereupon the adder  500  outputs the signal B 2 [ 7 : 0 ]. Further, the output circuit part  501  discriminates and quantizes the output signal B 2 [ 7 : 6 ] of the adder  500  by a predetermined threshold value. 
         [0100]    That is, as illustrated in  FIG. 12B , the output circuit part  501 , for example, for the input signal (output signal of the adder  500 ) B 2 [ 7 : 0 ], outputs Y[ 1 : 0 ]=00 in the case where −128≦B 2 [ 7 : 0 ]≦−65, outputs Y[ 1 : 0 ]=01 in the case where −64≦B 2 [ 7 : 0 ]≦−1, outputs Y[ 1 : 0 ]=11 in the case where 0≦B 2 [ 7 : 0 ]≦63, and outputs Y[ 1 : 0 ]=10 in the case where 64≦B 2 [ 7 : 0 ]≦127. 
         [0101]    Note that the critical path of the timing in the data modulation circuit of the fourth embodiment becomes the sum of the delay of the adder  500  and the delay of the inverter  502 , so compared with the prior art, faster speed operation becomes possible. 
         [0102]      FIG. 13A ,  FIG. 13B ,  FIG. 14A , and  FIG. 14B  are views for explaining the operation of the data modulation circuit illustrated in  FIG. 12A . Here,  FIG. 13A ,  FIG. 13B ,  FIG. 14A , and  FIG. 14B  correspond to  FIG. 5A ,  FIG. 5B ,  FIG. 6A , and  FIG. 6B  explaining the operation of the above-mentioned first embodiment. 
         [0103]    That is, as illustrated in  FIG. 13A , when inputting “100” to the input signal Vin, the output Vout becomes 102.4. Further, as illustrated in  FIG. 13B , when inputting “28” to the input signal Vin, the output Vout becomes 32. Furthermore, as illustrated in  FIG. 14A , when inputting “−28” to the input signal Vin, the output Vout becomes −32. Further, as illustrated in  FIG. 14B , when inputting “−100” to the input signal Vin, the output Vout becomes −102.4. 
         [0104]    In this way, according to the data modulation circuit of the fourth embodiment, it is learned that the output signal Vout approximating the input signal Vin can be output. 
         [0105]      FIG. 15A  and  FIG. 15B  are views for explaining a fifth embodiment of the data modulation circuit. Here,  FIG. 15A  is a block diagram of a data modulation circuit of the fifth embodiment, while  FIG. 15B  is a view for explaining the operation of a selector in the data modulation circuit of the fifth embodiment. Note that the data modulation circuit of the fifth embodiment illustrated in  FIG. 15A  corresponds to a generalized type of the data modulation circuit of the first embodiment illustrated in  FIG. 3A . 
         [0106]    In  FIG. 15A , reference numeral  600  indicates an adder,  601  an output circuit part,  602  a logic circuit part, and  603  a DFF. Note that the fifth embodiment indicates the case where N is made a natural number, the input signal Vin[N: 0 ] is a digital signal of the range of (−2 N  to 2 N −1), and the quantization level is 2 M  (M is a natural number smaller than N). Note that  FIG. 15B  indicates when N=7 and M=3. 
         [0107]    As illustrated in  FIG. 15A , the input signal Vin[N: 0 ] is added by the adder  600  with the output signal B 4 [N: 0 ] of tile DFF  603 , whereupon the adder  600  outputs the signal B 2 [N: 0 ]. 
         [0108]    The output circuit part  601  receives the signal B 2 [N:N−M] from the adder  600  and outputs the signal Y[M− 1 : 0 ]. Here, in the signal Y[M− 1 : 0 ] output from the output circuit part  601 , the highest bit Y[M− 1 ] is input to the DFF  603 , while the bits Y[M− 2 ] and Y[M− 3 ] are input to the logic circuit part  602 . 
         [0109]    The DFF  603  receives as input the N−M bit signal B 3 [N−M: 0 ] from the adder  600 , the output signal from the logic circuit part  602  becoming the N−Mth bit signal B 3 [N−M] and N−M+1st bit signal B 3 [N−M+ 1 ], and the output signal Y[M− 1 ] of the output circuit part  601  becoming the M−1st bit signal B 3 [M− 1 ] and outputs the above-mentioned N-bit signal B 4 [N: 0 ] to the adder  600 . Note that the signal B 2 [N:N−M] from the adder  600  becomes the B 3 [N:N−M] input to the DFF  603  as it is. 
         [0110]    As illustrated in  FIG. 15A , the logic circuit part  602  is provided with a first partial circuit  602   a  receiving as input the output signal B 2 [N− 1 ] from the adder  600  and the signal Y[M− 2 ] from the output circuit part  601  and outputting the above-mentioned signal B 3 [N−M] to the DFF  603  and a second partial circuit  602   b  receiving as input the output signal B 2 [N− 2 ] from the adder  600  and the signal Y[M− 3 ] from the output circuit part  601  and outputting the above-mentioned signal B 3 [N−M+ 1 ] to the DFF  603 . 
         [0111]    The first partial circuit  602   a  and second partial circuit  602   b  are for example comprised of two AND gates  621   a,    622   a;    621   b,    622   b  with one input made inverted inputs and OR gates  623   a;    623   b.    
         [0112]      FIG. 15B  indicates the case where N=7 and M=3. At this time, the output circuit part  601 , for the signal B 2 [ 7 : 0 ], outputs Y[ 1 : 0 ]=000 in the case where −128≦B 2 [ 7 : 0 ]≦−97, outputs Y[ 1 : 0 ]=001 in the case where −96≦B 2 [ 7 : 0 ]≦−65, outputs Y[ 1 : 0 ]=010 in the case where −64≦B 2 [ 7 : 0 ]≦−33, and outputs Y[ 1 : 0 ]=011 in the case where −32≦B 2 [ 7 : 0 ]≦−1. 
         [0113]    Further, the output circuit part  601 , for the signal B 2 [ 7 : 0 ], outputs Y[ 1 : 0 ]=111 in the case where 0≦B 2 [ 7 : 0 ]≦31, outputs Y[ 1 : 0 ]=110 in the case where 32≦B 2 [ 7 : 0 ]≦63, outputs Y[ 1 : 0 ]=101 in the case where 64≦B 2 [ 7 : 0 ]≦95, and outputs Y[ 1 : 0 ]=100 in the case where 96≦B 2 [ 7 : 0 ]≦127. 
         [0114]      FIG. 16  is a circuit diagram illustrating an example of an output circuit part in the data modulation circuit illustrated in  FIG. 15A  and indicates an example of the configuration of the output circuit  601  when the input signal Vin illustrated in  FIG. 15A  is in the range of [N: 0 ] (−2 N  to 2 N −1) and the quantization level is  2   M . 
         [0115]    As illustrated in  FIG. 16 , the output circuit  601  is provided with a partial circuit comprised of an inverter  611  for generating a signal Y[M− 1 ], a plurality of sets of AND gates  621   a,    621   b  with both inputs made inverted inputs . . . , AND gates  622   a,    622   b,  . . . and NOR gates  623   a,    623   b  . . . for generating the signals Y[M− 2 ], Y[M− 3 ], . . . and generates an output signal [M− 1 : 0 ]. 
         [0116]    Note that if making K=1, 2, 3, . . . , M−1, the signal Y[M−K− 1 ] produced by the different sets of partial circuits (that is, Y[M− 2 ], Y[M− 3 ], . . . ) is obtained from the next formula (7): 
         [0000]        Y[M−K− 1]= B 2[ N−K]·B 2[ N]+/B 2[ N−K]·/B 2[ N]   (7) 
         [0117]    Therefore, when the input signal Vin is the range of [N: 0 ] (−2 N  to 2 N −1) and the quantization level is 2 M , when B 2 [N] is positive (+), the output circuit  601  outputs the inversion of Y[M− 1 ]=B 2 [N], the inversion of Y[M− 2 ]=B 2 [N− 1 ], and the inversion of Y[M− 3 ]=B 2 [N− 2 ]. 
         [0118]    Further, when B 2 [N] is negative (−), it outputs the inversion of Y[M− 1 ]=B 2 [N], Y[M− 2 ]=B 2 [N− 1 ], and Y[M− 3 ]=B 2 [N− 2 ]. 
         [0119]      FIG. 17  is a view for explaining a sixth embodiment of the data modulation circuit and indicates a block diagram of a data modulation circuit. Note that the data modulation circuit of this sixth embodiment illustrated in  FIG. 17  corresponds to a generalized type of the data modulation circuit of the third embodiment illustrated in  FIG. 10A . 
         [0120]    In  FIG. 17 , reference numeral  700  indicates an adder,  701  an output circuit part, and  703  a DFF. Note that this sixth embodiment indicates the case where N is a natural number, the input signal Vin[N: 0 ] is a digital signal of the range of (−2 N  to 2 N −1), and the quantization level is 2 M  (M is a natural number smaller than N). 
         [0121]    As illustrated in  FIG. 17 , the input signal Vin[N: 0 ] is added by the adder  700  with an output signal. B 4 [N: 0 ] of the DFF  703 , whereupon the adder  700  outputs the signal B 2 [N: 0 ]. The output circuit part  701  receives the signal B 2 [N:N−M] from the adder  700  and outputs the signal Y[M− 1 : 0 ]. 
         [0122]    The DFF  703  receives the N−M bit signal B 3 [N−M: 0 ] from the adder  700  and the M-bit signal fixed at the high level “1” (1′b1) (that is, B 3 [N], B 3 [N− 1 ], . . . , B 3 [N−M+ 1 ]) and outputs the above-mentioned signal B[N: 0 ] to the adder  700 . 
         [0123]    That is, the data modulation circuit of this sixth embodiment, like the above-mentioned third embodiment, is suitable for increasing the speed since the signal Y[M: 0 ] from the output circuit part  701  is not made the input of the DFF  703  and the delay of the adder  700  need only be completed within one clock. 
         [0124]      FIG. 18  is a view for explaining a seventh embodiment of the data modulation circuit and indicates a block diagram of the data modulation circuit. Note that the data modulation circuit of the seventh embodiment illustrated in  FIG. 18  corresponds to a generalized type of the data modulation circuit of the fourth embodiment illustrated in  FIG. 12A . 
         [0125]    In  FIG. 18 , reference numeral  800  indicates an adder,  801  an output circuit part,  802  an inverter, and  803  a DFF. Note that this sixth embodiment indicates the case where N is a natural number, the input signal Vin[N: 0 ] is a digital signal of the range of (−2 N  to 2 N −1), and the quantization level is 2 M  (M is a natural number smaller than N). 
         [0126]    As illustrated in  FIG. 18 , the input signal Vin[N: 0 ] is added by the adder  800  with the output signal B 4 [N: 0 ] of the DFF  803 , whereupon the adder  800  outputs the signal B 2 [N: 0 ]. 
         [0127]    The output circuit part  801  receives the signal B 2 [N:N−M] from the adder  800  and outputs the signal Y[M− 1 : 0 ]. The inverter  802  receives the signal B 2 [N] from the adder  800  and outputs an M-bit signal (that is, B 3 [N], B 3 [N− 1 ], . . . , B 3 [N−M+ 1 ]) inverted from that signal B 2 [N] to the DFF  803 . 
         [0128]    That is, the DFF  803  receives the N−M bit signal B 3 [N−M: 0 ] from the adder  800  and the M-bit signal. B 3 [N:N−M+ 1 ] inverted from the signal B 2 [N] from the inverter  802  and outputs the above-mentioned signal B[N: 0 ] to the adder  800 . 
         [0129]    In the data modulation circuit of the seventh embodiment, like the above-mentioned fourth embodiment, the critical path of the timing in the data modulation circuit becomes the sum of the delay of the adder  800  and the delay of the inverter  802 , so compared with the prior art, a much faster speed operation becomes possible 
         [0130]    In this way, according to the embodiments, it is possible to provide a data modulation circuit able to operate at a high speed. 
         [0131]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a illustrating of the superiority and inferiority of the invention. 
         [0132]    Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.