Abstract:
An asynchronous switching system and method for processing SDI data streams, the system and method utilizing one or more buffers for cleaning up an output of a dirty IP switch.

Description:
PRIORITY AND INCORPORATION BY REFERENCE 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 62/214,962 filed Sep. 5, 2015 which is incorporated herein by reference in its entirety and for all purposes. This application incorporates by reference in their entireties and for all purposes U.S. Pat. Nos. 6,493,357 B1 filed Mar. 22, 2000 and 8,291,116 B2 filed Jan. 5, 2009. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    Signals transported from a source to a destination can be switched. Current day practice in professional video environments typically involves use of cross point switches interconnecting devices with a serial digital interface (SDI). 
         [0003]    SDI signals can be encapsulated in or mapped to packetized traffic such as Ethernet packets for transport on an internet protocol (IP) line segment where each video frame translates to a multitude of, e.g. a few thousand, packets. 1  In this IP environment, signals can be switched using widely deployed IP switching technologies available from a multitude of vendors including Cisco, Juniper Networks, and Alcatel-Lucent.  1  See e.g., SMPTE 2022-6:2012, Transport of High Bit Rate Media Signals over IP Networks (HBRMT). 
         [0004]    However, Ethernet switches do not provide for clean switching of video signals for reasons including their ignorance of video frame boundary locations in the packetized traffic. And, even if Ethernet switches included this capability, yet other problems arise in the context of switching non-aligned video streams. 
       FIELD OF INVENTION 
       [0005]    This invention relates to the electrical and process arts. In particular, a system and method for switching video signals in provided. 
       DISCUSSION OF THE RELATED ART 
       [0006]    Switching of packetized video signals is not unknown. However, the professional video industry has yet to find an effective IP solution for handling live production/real time operations with minimum latency where video streams can be switched without picture disruption. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention provides for asynchronous switching with cleanup of the output of a dirty switch. 
         [0008]    In an embodiment, an asynchronous video signal switching method comprises the steps of: providing first and second SDI signal sources and respective interconnected SDI to IP converters; providing an Ethernet/IP switch receiving IP outputs of the SDI to IP converters; providing a cleanup switch that receives the Ethernet/IP (EIP) switch output; via the EIP, initially forwarding signals from the first source to the cleanup switch and subsequently forwarding signals from the second source to the cleanup switch; initially buffering the first source signals in a first buffer of the cleanup switch; and, subsequently buffering the second source signals in a second buffer of the cleanup switch; wherein play from buffer 1 includes buffer 1 replay while buffer 2 is being loaded and play from buffer 2 begins after a start-of-frame is detected in buffer 2. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The present invention is described with reference to the accompanying figures. The figures, incorporated herein and forming part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art to make and use the invention. 
           [0010]      FIG. 1  shows an asynchronous switch system of the present invention. 
           [0011]      FIGS. 2-3  show asynchronous switch systems for handling serial digital interface signal sources. 
           [0012]      FIG. 4  shows an embodiment of a cleanup switch of the asynchronous switch system of  FIG. 1 . 
           [0013]      FIGS. 5-6  show a method of asynchronous switching of the asynchronous switch system of  FIG. 1 . 
           [0014]      FIG. 7  shows an exemplary low latency frame switching diagram of the asynchronous switch system of  FIG. 1   
           [0015]      FIG. 8  shows an exemplary intermediate latency frame switching diagram of the asynchronous switch system of  FIG. 1 . 
           [0016]      FIG. 9  shows an exemplary switching methodology of the asynchronous switch system of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0017]    The disclosure provided in the following pages describes examples of some embodiments of the invention. The designs, figures, and descriptions are non-limiting examples of certain embodiments of the invention. For example, other embodiments of the disclosed device may or may not include the features described herein. Moreover, disclosed advantages and benefits may apply to only certain embodiments of the invention and should not be used to limit the disclosed inventions. 
         [0018]    Where parts are connected, descriptions herein using the words “coupled,” “connected,” or “interconnected” refer to either direct or indirect connections. Direct connections provide for a first part connected directly to a second part, for example A connected directly to B. Indirect connections provide for a first part connected indirectly to a second part, for example A connected indirectly to C via B. 
         [0019]      FIG. 1  shows an asynchronous switch system of the present invention  100 . A digital switch that does not provide for clean switching, that is a dirty switch,  106  selectively interconnects signal sources with a cleanup switch. Dirty switch operation may be controlled at least in part by a source select line or function  110 . 
         [0020]    For example, where there are first and second signal sources  102 ,  103  with respective source outputs  103 ,  105 , the dirty switch  106  selectively interconnects either the first source or the second source with a cleanup switch  108  via a dirty switch output  107 . The cleanup switch  108  mitigates signal disruptions introduced when the dirty switch switches from source 1 to source 2 or vice versa and provides a cleaned up output  109 . 
         [0021]    In various embodiments, the dirty switch  106  output  107  transports only one of the source signals  103 ,  105  at a time. And, in various embodiments operation of the dirty switch causes deselection of one source followed by selection of another source such that the dirty switch operates in a “break before make” mode. 
         [0022]      FIGS. 2-3  show asynchronous switch systems for handling serial digital interface signal sources  200 - 300 . 
         [0023]    In  FIG. 2 , a dirty switch for handling packetized traffic is provided. Exemplary switches include Ethernet/IP switches and SDN (software defined network) switches  206 . Dirty switch operation may be controlled at least in part by a source select line or function  210 . 
         [0024]    IP outputs  203 ,  205  available from sources A, B ( 202 ,  204 ) interconnect with the dirty switch  206  and a dirty switch IP output  207  interconnects with a cleanup switch  208 . In various embodiments, one or both of the sources A, B include an SDI to IP converter such as an SMPTE 2022-6 type converter. 
         [0025]    The cleanup switch  208  mitigates signal disruptions introduced when the dirty switch  206  switches from source A to source B or vice versa and provides a cleaned up output such as a cleaned up SDI output  209 . 
         [0026]    In various embodiments, the dirty switch  206  output  207  transports only one of the source signals  203 ,  205  at a time. And, in various embodiments operation of the dirty switch causes deselection of one source followed by selection of another source such that the dirty switch operates in a “break before make” mode. 
         [0027]    In  FIG. 3 , a dirty switch for handling packetized traffic is provided. Exemplary switches include Ethernet/IP switches and SDN (software defined network) switches  306 . Dirty switch operation may be controlled at least in part by a source select line or function  310 . 
         [0028]    IP outputs  303 ,  305  available from sources  302 ,  304  interconnect with the dirty switch  206  and a dirty switch IP output  207  interconnects with a cleanup switch  208 . Source  302  includes an SDI camera A ( 322 ) and an SDI to IP converter  323 . Source  304  includes an SDI camera B ( 332 ) and an SDI to IP converter  333 . In some embodiments, the SDI to IP converters  323 ,  333  are compliant with SMPTE 2022-6. 
         [0029]    The cleanup switch  308  mitigates signal disruptions introduced when the dirty switch  306  switches from camera A to camera B or vice versa and provides a cleaned up output such as a cleaned up SDI output  309 . 
         [0030]    In various embodiments, the dirty switch  306  output  307  transports only one of the source signals  303 ,  305  at a time. And, in various embodiments operation of the dirty switch causes deselection of one source followed by selection of another source such that the dirty switch operates in a “break before make” mode. 
         [0031]      FIG. 4  shows an embodiment of a cleanup switch  400 . The cleanup switch includes a buffer loader section  440 , a cleanup section  450 , and an IP to SDI converter section. The buffer loader section includes a buffer loader  442 , the cleaner section includes buffers A, B ( 452 ,  456 ) and a cleaner  454 , and the converter section includes an IP to SDI converter  460 . 
         [0032]    The buffer loader  442  receives, via an Ethernet/IP input  441 , a stream of video data, initially from a source A and subsequently from a source B with a time gap therebetween. When data from source A arrives at the buffer loader, the data is directed to buffer A via a first data line  447 . When data from source B arrives at the buffer loader, the data is directed to buffer B via a second data line  449 . 
         [0033]    Data is received at the cleaner  454  initially from buffer A and subsequently from buffer B with a time gap therebetween. As described above and below, when the received data  441  switches from source A to source B, the cleaner loops/replays a portion of buffer A while buffer B is receiving data. When buffer B includes a start of video frame boundary, the cleaner jumps from buffer A to the start of the video frame detected in buffer B. 
         [0034]    As a consequence of switching from source A to source B, a cleaner output  457  is initially source A data and subsequently source B data played, out by the cleaner in a manner that mitigates picture or video disruptions. 
         [0035]    In the converter section  460 , the IP to SDI converter receives the cleaner IP output  457  and converts it to a converter serial digital interface output. 
         [0036]      FIGS. 5-6  show a method of asynchronous switching of the present invention. In particular,  FIG. 5  shows a switching timeline  500  and  FIG. 6  shows a switching flowchart  600 . 
         [0037]    In the timeline, forwarding A indicates video data A is being forwarded to a cleaner similar to the cleaner  454  of  FIG. 4  (“cleaner”). In the flowchart, the corresponding step  602  is buffer loader forwarding A frames and playing from buffer A to a destination such as destination 1. 
         [0038]    In the timeline, select B indicates that the video source is switched from source A to source B. In the flowchart, the corresponding step  604  is user selects source B for destination 1. 
         [0039]    In the timeline, await B indicates buffer B is awaiting video data from source B. In the flowchart, the corresponding step  606  is buffer B awaits B frames from buffer loader. 
         [0040]    In the timeline and the flowchart, buffer A playout  608  indicates that buffer A plays out before the await B step completes. 
         [0041]    In the timeline, a portion of buffer A is replayed during the await B step. In the flowchart, the corresponding step  610  is loop back and replay portion of buffer A. 
         [0042]    During the buffer A replay step  610 , data from source B begins to arrive as shown in the timeline. This source B data is forwarded to buffer B. A signal for a cleaner read pointer to jump from playing buffer A to playing buffer B occurs when a video frame start boundary is detected in buffer B. As seen in the flowchart, this detection occurs in step  612  and the cleaner read pointer jump occurs in step  614 . 
         [0043]      FIG. 7  shows an exemplary low latency frame switching diagram of the present invention  700 . As seen, buffer A ( 710 ) is loaded by source A ( 711 ) and includes partial frame A1 ( 712 ), frame A2 ( 714 ), and frame A3 ( 716 ), the same indicating a buffer embodiment with a capacity of less than three frames. Buffer B ( 720 ) is loaded by source B ( 721 ) and includes frame B1 ( 722 ) and partial frame B2 ( 724 ), the same indicating a buffer embodiment with a capacity of less than two frames. 
         [0044]    When the video source is switched from source A to source B, a portion of buffer A, in some embodiments the last frames worth of data (as shown), is replayed before playback from buffer B is available. The start of the replay data portion of buffer A is indicated by the arrow on loop back  705 . As seen, the replay data indicated by the loop back is typically not a full/integral frame, rather the loop back encompasses data from each of adjacent frames A1, A2. 
         [0045]    When a start-of-frame  726  is detected in buffer B, a read pointer can jump from buffer A to the detected start-of-frame in buffer A. For example, upon detection of a start-of-frame  726  in buffer B, a read pointer  730  continues play from buffer A until a buffer A end of frame  718  is reached. At this point, the read pointer  730  jumps to the detected start-of-frame  726  in buffer B and commences play from buffer B. 
         [0046]    In various embodiments, the video frames of buffers A and B need not be aligned. And, in various embodiments no overlap of the buffers is required and a gap in time  728  may exist between the initial playout of buffer A and the time when buffer B loading begins. 
         [0047]      FIG. 8  shows an exemplary intermediate latency frame switching diagram of the present invention  800 . As seen, buffer A ( 810 ) is loaded by source A ( 811 ) and includes partial frame A1 ( 812 ), frame A2 ( 814 ), and frame A3 ( 816 ), the same indicating a buffer embodiment with a capacity of less than three frames. Buffer B ( 820 ) is loaded by source B ( 821 ) and includes frame B1 ( 822 ) and partial frame B2 ( 824 ), the same indicating a buffer embodiment with a capacity of less than two frames. 
         [0048]    When the video source is switched from source A to source B, a portion of buffer A, in some embodiments the last full/integral frame of data (as shown), is replayed before playback from buffer B is available. The start of the replay data portion of buffer A is indicated by the arrow on loop back  805 . Loop back to the beginning of a frame, here frame A2, provides for an integer frame wrap but typically higher latency as compared to the example of  FIG. 7 . 
         [0049]    When a start-of-frame  826  is detected in buffer B, a read pointer can jump from buffer A to the detected start-of-frame in buffer A. For example, upon detection of a start-of-frame  826  in buffer B, a read pointer  830  continues play from buffer A until a buffer A end of frame  818  is reached. At this point, the read pointer  830  jumps to the detected start-of-frame  826  in buffer B and commences play from buffer B. 
         [0050]    In various embodiments, the video frames of buffers A and B need not be aligned. And, in various embodiments no overlap of the buffers is required and a gap in time  828  may exist between the initial playout of buffer A and the time when buffer B loading begins. 
         [0051]      FIG. 9  shows and exemplary switching methodology  900 . In a first step  902  an IP switch such as an Ethernet/IP switch forwards source A to a cleanup switch serving destination 1. In a second step  904 , the cleanup switch receives source A and passes it through a buffer 1. In a third step  906 , a user selects source B for destination 1. In a fourth step  908  an SDN or equivalent stops forwarding source A and begins forwarding source B to destination 1; the ceasing and initiation of flows is done asynchronously to the video content. In a fifth step  910  the clean switch sees the cessation of flow from source A and to maintain the video output loops back to replay the last frame of video from the buffer 1. In a sixth step  912 , the cleanup switch sees the new feed from source B start to arrive and writes this into to buffer 2. In a seventh step  914 , when the new feed is established, upon detection of the start-of-frame in the readout of the existing video repeat from buffer 1, the readout moves to taking its feed from buffer 2 (at the start-of-frame position). In an eight step  916 , when the next switch of incoming feed occurs, the process is repeated with transposed buffers. 
         [0052]    The appendix to this application provides descriptions of similar and/or other embodiments of the present invention. 
         [0053]    While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the art that various changes in the form and details can be made without departing from the spirit and scope of the invention. As such, the breadth and scope of the present invention should not be limited by the above-described exemplary embodiments, but should be defined only in accordance with the following claims and equivalents thereof.