Abstract:
Disclosed is a method of dynamical adjustment for a power supply. The method takes aim at lowering the minimum bulk capacitor voltage to the maximum extent through increasing the switching frequency or the OCP (Over-Current Protection) trip point during the holdup time so that the holdup time can get prolonged or the bulk capacitor can get downsized provided that all other parameters remain unchanged. In general, the proposed method is applicable to a wide variety of power converters.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to two cost-effective methods either for prolonging the holdup time without the necessity for upsizing the bulk capacitor or for downsizing the bulk capacitor without the penalty of shortening the holdup time so that the performance-to-cost ratio can be brought up to a higher level. 
     2. The Prior Arts 
     The majority of today&#39;s computer and computer peripherals require that their power supplies be capable of lasting a holdup time of at least 10 ms to orderly terminate the operation of data-processing equipment or switch over to the UPS (Uninterrupted Power Supply) operation after a short-/long-term outage of electric power. The holdup time is generally defined as the time interval during which a power supply needs to hold up its output voltage(s) within a specified range after a power outage. 
     The energy required for holding up the output voltage(s) during the holdup time is solely provided by a properly sized bulk capacitor C B , as is shown in  FIG. 1 a   . The front-end rectifier is in charge of rectifying a sinusoidal AC input into an unregulated DC input via a bridge rectifier or a regulated DC input via a conventional/bridgeless power factor corrector (PFC). To achieve a desired holdup time after the outage of AC power, the DC/DC converter output stage must be able to operate in a certain voltage range with a minimum bulk capacitor voltage V BMIN  which is lower than a nominal bulk capacitor voltage V BNOM  that corresponds to the line voltage at which the holdup time is specified. 
     Without being recharged up by the AC mains during the holdup time T H , the bulk capacitor C B  keeps providing power to the outputs until discharging down to the minimum bulk capacitor voltage V BMIN  below which the DC/DC converter output stage would shut off, as is illustrated in  FIG. 1   b.    
     The holdup time T H  can be mathematically expressed as 
                       Δ   ⁢           ⁢     E   CB       =         1   2     ⁢       C   B     ⁡     (       V   BNOM   2     -     V   BMIN   2       )         =             P   OH     ⁢     T   H         η     DC   /   DC         ⇒     T   H       =         η     DC   /   DC       ⁢   Δ   ⁢           ⁢     E   CB         P   OH             ,           (   1   )               
where η DC/DC  is the DC/DC converter efficiency and P OH  is the output power delivered to the outputs during the holdup time T H .
 
     The energy delivery ratio r can be calculated from 
                     r   =         Δ   ⁢           ⁢     E   CB         E   CBNOM       =           1   2     ⁢       C   B     ⁡     (       V   BNOM   2     -     V   BMIN   2       )             1   2     ⁢     C   B     ⁢     V   BNOM   2         =     1   -       (       V   BMIN       V   BNOM       )     2             ,           (   2   )               
where ΔE CB  is the partial energy delivered to the outputs during the holdup time T H  and E CBNOM  is the total energy stored in the bulk capacitor C B  at the nominal bulk capacitor voltage V BNOM . Eq. (2) can be graphically represented in  FIG. 2 .
 
     As can be seen from Eq. (1) and Eq. (2), the holdup time T H  can be prolonged and the energy delivery ratio r can be enlarged or the bulk capacitor C B  can be downsized by lowering the minimum bulk capacitor voltage V BMIN  above which the DC/DC converter output stage still can work, provided that all other parameters remain unchanged. 
     In prior arts, the minimum bulk capacitor voltage V BMIN  is usually restricted to 80% to 90% of the nominal bulk capacitor voltage V BNOM  and disallowed to get lowered due to the lack of feasible and economical approaches, leaving most stored bulk capacitor energy unused and wasted after the DC/DC converter output stage shuts off below the minimum bulk capacitor voltage V BMIN . 
     In view of the deficiency of prior arts, the present invention comes up with two cost-effective methods for substantially prolonging the holdup time T B  and enlarging the energy delivery ratio r or downsizing the bulk capacitor C B  by lowering the minimum bulk capacitor voltage V BMIN  to the maximum extent, making the most of the stored bulk capacitor energy and maximizing the performance-to-cost ratio of power supplies. 
     SUMMARY OF THE INVENTION 
     In the present invention, two cost-effective methods that substantially improve the utilization of the stored bulk capacitor energy in a power supply during the holdup time are detailed. 
     The substantial improvement is achieved by lowering the minimum bulk capacitor voltage to the maximum extent through increasing the switching frequency or the OCP (Over-Current Protection) trip point during the holdup time so that the holdup time can get prolonged or the bulk capacitor can get downsized provided that all other parameters remain unchanged. 
     In general, the proposed methods are applicable to a wide variety of power converters. For ease of making clear the central idea behind the present invention, a flyback converter is singled out as an illustrative example in the present invention without loss of generality. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be apparent to those skilled in the art by reading the following detailed description of a preferred embodiment thereof, with reference to the attached drawings, in which: 
         FIG. 1 a    shows a typical AC/DC power supply architecture, where a bulk capacitor C B , placed between a front-end rectifier and a DC/DC converter output stage as an energy-storage capacitor, would be the one and only power source to hold up the outputs V o1 , V o2 , . . . , V on  after the outage of the AC power V N ; 
         FIG. 1 b    defines the holdup time T H =T 1 −T 0 , where T 0  is the time instant when the bulk capacitor C B  starts holding up the outputs, i.e., when the bulk capacitor voltage V B  drops from its nominal voltage level V BNOM , and T 1  is the time instant when the bulk capacitor C B  stops holding up the outputs, i.e., when the bulk capacitor voltage V B  gets to its minimal voltage level V BMIN ; 
         FIG. 2  gives a plot of the energy delivery ratio r=ΔE CB /E CBNOM  as a function of the normalized minimum bulk capacitor voltage V BMIN /V BNOM ; 
         FIG. 3  shows a typical flyback converter architecture taken as an illustrative example for exemplifying/instantiating the present invention; 
         FIG. 4  contrasts the original holdup time T H(ori)  with the prolonged holdup time T H(pro)  by lowering the original minimum bulk capacitor voltage V BMIN(ori)  to a lowered minimum bulk capacitor voltage V BMIN(low) ; 
         FIG. 5  shows the primary current waveform when the flyback converter operates in CCM (Continuous-Conduction Mode) during the holdup time after the outage of AC power; 
         FIG. 6  shows the effect of increasing the switching frequency on the primary current waveform during the holdup time; 
         FIG. 7  shows the effect of increasing the OCP trip point on the primary current waveform during the holdup time; 
         FIG. 8  gives a plot of the lowered minimum bulk capacitor voltage V BMIN(low)  as a function of the increased switching frequency, parameterized with an increase in the OCP trip point; and 
         FIG. 9  gives a plot of the prolonged holdup time T H(pro)  as a function of the increased switching frequency, parameterized with an increase in the OCP trip point. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
       FIG. 3  shows a simplified flyback converter architecture, where a PWM (Pulse-Width Modulation) controller  10  takes control of a primary power switch Q 1  to regulate a secondary output voltage V OUT  through a unshown feedback control scheme, which can be but won&#39;t be limited to Primary-Side Regulation (PSR) or Secondary-Side Regulation (SSR). 
     In the presence of AC power before a power outage, an input capacitor C N  (commonly called a bulk capacitor C B  as a jargon) would be discharged down to its valley voltage when the sinusoidal AC voltage V AC  of the AC power source is lower than the bulk capacitor voltage V B , i.e., when a unshown bridge rectifier stops conducting current, and recharged up to its peak voltage when the sinusoidal AC voltage V AC  is higher than the bulk capacitor voltage V B , i.e., when a unshown bridge rectifier starts conducting current. The unshown bridge rectifier can be but won&#39;t be limited to a diode bridge rectifier or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) bridge rectifier. 
     The ripple voltage, defined as the difference between the peak voltage and the valley voltage, is normally negligibly small compared to the average value of the bulk capacitor voltage V B . So, the bulk capacitor voltage V B  can be deemed almost constant when the AC mains voltage stays unchanged. 
     In the absence of AC power after a power outage, all the energy required for holding up the output voltage V OUT  during the holdup time relies on the bulk capacitor C B . 
     From Eq. (1) and  FIG. 4  it can be seen that the holdup time T H  will get prolonged as the minimum bulk capacitor voltage V BMIN  gets lowered, milking as much stored energy out of the bulk capacitor C B  as possible. The output voltage V OUT  will drop out of regulation and then down to zero soon after the expiry of the holdup time T H  due to OCP or DRL (Duty-Ratio Limit), whichever comes first, because the primary peak current I PPK  will eventually go up to the OCP trip point or the duty ratio D will finally reach the DRL trip point when the bulk capacitor voltage V B  drops down to the minimum bulk capacitor voltage V BMIN . It is OCP or DRL that terminates the holdup time T H . 
       FIG. 5  shows the primary current waveform when the flyback converter runs deep into CCM during the holdup time after the outage of AC power. When the bulk capacitor voltage V B  drops down to the minimum bulk capacitor voltage V BMIN , the maximum duty ratio D MAX  can be derived from the volt-second product balance equation: 
                   {                 n   ⁢     =   Δ     ⁢       N   P       N   S                       V   BMIN     ⁢     D   MAX       =       nV   OUT     ⁡     (     1   -     D   MAX       )               ⇒     D   MAX       =       nV   OUT         V   BMIN     +     nV   OUT           ,             (   3   )               
where n is the fixed primary-to-secondary turns ratio and V OUT  is the regulated output voltage. The maximum duty ratio D MAX  can thus be considered constant when the minimum bulk capacitor V BMIN  stays constant and should be kept below an upper limit, imposing a lower limit on the minimum bulk capacitor voltage V BMIN :
 
                         D   MAX     ≤     D   LIM       ⇒       V   BMIN     ≥       nV   OUT     ⁡     (       1     D   LIM       -   1     )           ,           (   4   )               
where D LIM  is the duty ratio limit the PWM controller is disallowed to exceed.
 
     The primary flattop current I PFT  in  FIG. 5  is so defined that the rectangle encloses the same area as does the trapezoid, facilitating the calculation of the primary average current I PAV . 
                       I   PFT     ⁢     =   Δ     ⁢           1       D   MAX     ⁢     T   SW         ⁢       ∫   0       D   MAX     ⁢     T   SW         ⁢         i   P     ⁡     (   t   )       ⁢           ⁢   d   ⁢           ⁢   t         ⇒     I   PAV       =         1     T   SW       ⁢       ∫   0     T   SW       ⁢         i   P     ⁡     (   t   )       ⁢           ⁢   d   ⁢           ⁢   t         =       I   PFT     ⁢     D   MAX             ,           (   5   )               
where the primary current i P (t) is nonzero in the time interval of 0 to D MAX T SW  and zero in the time interval of D MAX T SW  to T SW .
 
     From Eq. (4) it follows that the average input power P IN  at the minimum bulk capacitor voltage V BMIN  is:
 
 P   IN   V   BMIN   I   PAV   =V   BMIN   I   PFT   D   MAX   (6),
 
which can be further related to the average output power P OH :
 
 P   OH =η DC/DC   P   IN =η DC/DC   V   BMIN   I   PFT   D   MAX   (7),
 
where the DC-to-DC conversion efficiency η DC/DC  during the holdup time T H  for supporting the average output power P OH  can be assumed to be almost constant for simplicity.
 
     From Eq. (7) it can be deduced that the minimum bulk capacitor voltage V BMIN  can be lowered by heightening the primary flattop current I PFT , provided that all other parameters remain constant. From another point of view, the primary flattop current I PFT  in  FIG. 5  can be expressed as: 
                   {                   I   PPK     =       V   OCP       R   CS                     I   PFT     =       I   PPK     -       Δ   ⁢           ⁢   I     2                       L   P     ⁢       Δ   ⁢           ⁢   I         D   MAX     ⁢     T   SW           =     V   BMIN             ⇒     I   PFT       =         V   OCP       R   CS       -         V   BMIN     ⁢     D   MAX         2   ⁢     L   P     ⁢     f   SW             ,             (   8   )               
where V OCP  is the OCP trip point, R CS  is the current-sense resistance, L P  is the primary inductance, and f SW  is the switching frequency. In accordance with Eq. (8), there are two feasible approaches to heightening the primary flattop current I PFT : one is to heighten the switching frequency f SW  and the other is to heighten the OCP trip point V OCP .
 
     Putting train of thought in order would help one see the whole picture more clearly. Prolonging the holdup time T H  boils down to heightening the switching frequency f SW  or the OCP trip point V OCP  in line with the central idea behind the present invention. 
     
       
         
           
             
               
                 T 
                 H 
               
               ↑ 
             
             ⇐ 
             
               
                 V 
                 BMIN 
               
               ↓ 
             
             ⇐ 
             
               
                 I 
                 PFT 
               
               ↑ 
             
             ⇐ 
             
               { 
               
                 
                   
                     
                       
                         f 
                         SW 
                       
                       ↑ 
                     
                   
                 
                 
                   
                     
                       
                         V 
                         OCP 
                       
                       ↑ 
                     
                   
                 
               
             
           
         
       
     
     With knowledge of relevant coefficients, the minimum bulk capacitor voltage V BMIN  can be easily solved from the following quadratic equation in one unknown: 
                   {                 V   r     ⁢     =   Δ     ⁢     nV   OUT                   D   MAX     =       V   r         V   BMIN     +     V   r                       P   OH     =       η     DC   /   DC       ⁢       V   BMIN     ⁡     (         V   OCP       R   CS       -         V   BMIN     ⁢     D   MAX         2   ⁢     L   P     ⁢     f   SW           )       ⁢     D   MAX               ⇒         (           V   OCP     ⁢     V   r         R   CS       -       V   r   2       2   ⁢     L   P     ⁢     f   SW         -       P   OH       η     DC   /   DC           )     ⁢     V   BMIN   2       +       (           V   OCP     ⁢     V   r   2         R   CS       -       2   ⁢     P   OH     ⁢     V   r         η     DC   /   DC           )     ⁢     V   BMIN       -         P   OH     ⁢     V   r   2         η     DC   /   DC             =     0   ⁢     
     ⁢     {                 a   ⁢     =   Δ     ⁢           V   OCP     ⁢     V   r         R   CS       -       V   r   2       2   ⁢     L   P     ⁢     f   SW         -       P   OH       η     DC   /   DC                       b   ⁢     =   Δ     ⁢           V   OCP     ⁢     V   r   2         R   CS       -       2   ⁢     P   OH     ⁢     V   r         η     DC   /   DC                       c   ⁢     =   Δ     ⁢     -         P   OH     ⁢     V   r   2         η     DC   /   DC                   ⇒       aV   BMIN   2     +     bV   BMIN     +   c       =       0   ⇒     V   BMIN       =         -   b     ±         b   2     -     4   ⁢   ac             2   ⁢   a           ,                   (   9   )               
where the unknown minimum bulk capacitor voltage V BMIN  mathematically has two distinct real roots as long as the quadratic coefficient a is positive and hence the discriminant b 2 −4ac is positive, imposing a lower limit on the OCP trip point V OCP :
 
                   a   =               V   OCP     ⁢     V   r         R   CS       -       V   r   2       2   ⁢     L   P     ⁢     f   SW         -       P   OH       η     DC   /   DC           &gt;   0     ⇒     {               b   2     -     4   ⁢   ac       &gt;   0                   V   OCP     &gt;         R   CS       V   r       ⁢     (         V   r   2       2   ⁢     L   P     ⁢     f   SW         +       P   OH       η     DC   /   DC           )         ,                       (   10   )               
where a positive quadratic coefficient a&gt;0 implies a positive discriminant b 2 −4ac&gt;0 because the constant coefficient c is negative. In further consideration of the acceptability/applicability of the two distinct real roots, the positive root is physically meaningful while the negative root is physically meaningless simply because the minimum bulk capacitor voltage V BMIN  is physically nonnegative. The physically meaningful result from Eq. (9) can then be put into Eq. (1) for the calculation of the holdup time T H .
 
     As is illustrated with  FIG. 6  and  FIG. 7 , the primary flattop current I PFT  can be heightened by heightening the switching frequency f SW  or the OCP trip point V OCP . 
       FIG. 8  gives a plot of the lowered minimum bulk capacitor voltage V BMIN(low)  as a function of the increased switching frequency f SW(inc) , parameterized with an increase in the OCP trip point V OCP , where the curve C 1  corresponds to an original OCP trip point while the curve C 2  corresponds to a heightened OCP trip point, i.e., increasing the original OCP trip point by 0.1V. 
       FIG. 9  gives a plot of the prolonged holdup time T H(pro)  as a function of the increased switching frequency f SW(inc) , parameterized with an increase in the OCP trip point V OCP , where the curve C 3  corresponds to an original OCP trip point while the curve C 4  corresponds to a heightened OCP trip point, i.e., increasing the original OCP trip point by 0.1V. 
     From  FIG. 8  and  FIG. 9  it can be concluded that the minimum bulk capacitor voltage V BMIN  can be lowered and hence the holdup time T H  can be prolonged by heightening the switching frequency f SW  or the OCP trip point V OCP . It goes without saying that a prolonged holdup time T H  can be traded off for a downsized bulk capacitor C B , i.e., trading better performance off for lower cost. 
     Although the present invention has been described with reference to the preferred embodiments thereof, it is apparent to those skilled in the art that a variety of modifications and changes may be made without departing from the scope of the present invention which is intended to be defined by the appended claims.