Abstract:
A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a non-volatile semiconductor memory device (EEPROM) capable of electrically rewriting data, which device is constituted by memory cells each having a MOS transistor structure having a charge storage layer and a control gate, and more particularly, to an EEPROM for writing/erasing data in/from each memory cell using a tunnel current. 
     2. Description or the Related Art 
     In the field of EEPROMs, a memory cell of a MOS transistor structure having a charge storage layer (floating gate) and a control gate is widely used, and there is a growing trend toward higher integration densities. This memory cell is capable of electrically writing data by exchanging charges between the floating gate and the semiconductor substrate. 
     In a device of this type, when a data erase operation is to be performed, a high electric field is applied to the tunnel oxide film of each memory cell between the floating gate and the semiconductor, posing problems in terms of dielectric breakdown and leakage current. In a data write operation, a high electric field is applied to the tunnel oxide film, and hence a great stress is applied thereto. For this reason, the tunnel oxide film of each memory cell deteriorates after the device is used for a predetermined period of time. This deterioration in the tunnel oxide film will reduce the resistance of cell data to a stress acting on each cell in a cell data read operation, and shorten the service life of cell data. 
     As one of the above EEPROMs, a NAND-type EEPROM which allows a high integration density is known. In a NAND-type EEPROM, a plurality of memory cells are connected in series such that the respective adjacent memory cells share sources and drains. These memory cells are connected, as a unit, to a bit line. Each memory cell generally has an FET structure in which a charge storage layer and a control gate are stacked on each other. A memory cell array is integrally formed in a p-type well formed in a p- or n-type substrate. 
     The drain and source sides of a NAND cell are respectively connected to a bit line and a source line (reference potential line) via selection gates. The control gates of the respective memory cells are continuously connected to each other in the row direction to constitute a word line. In general, a set of cells connected to the same word line is called a page, and a set of pages between a pair of selection gates on the drain and source sides is called a NAND block or simply a block. In general, one block is the minimum unit which can be independently erased. 
     The NAND-type EEPROM is operated as follows. 
     A data erase operation is performed with respect to the memory cells in one NAND block at once. All the control gates of a selected NAND block are set at V SS , and a high voltage V pp  (e.g., 20 V) is applied to the p-type well and the n-type substrate. With this operation, electrons are discharged from the floating gates of all the memory cells, and the threshold value of each memory cell shifts in the negative-value direction (normally, this state is defined as a “1” state). A chip erase operation is performed by setting all the NAND blocks in a selected state. 
     A data write operation is sequentially performed from the memory cell located farthest from the bit line. A high voltage V pp  (e.g., 20 V) is applied to a selected control gate in a NAND block, and an intermediate potential V M  (e.g., 10 V) is applied to the remaining non-selected control gates. A potential V SS  or V bitH  (8 V) is applied to the bit line in accordance with data. When the potential V SS  is applied to the bit line (“0” write operation), the potential is transferred to the selected memory cell, and electrons are injected into the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive-value direction (normally this state is defined as a “0” state). When the potential V bitH  is applied to the bit line (“1” write operation), since no electrons are injected into the memory cell, the threshold value of the memory cell does not change and remains negative. The potential V M  is applied to the drain-side selection gate to transfer the bit line potential. 
     A data read operation is performed as follows. The control gate of a selected memory cell in a NAND block is set at V SS , and the remaining control gates and the selection gates are set at V CC . In this state, it is checked whether a current flows in the selected memory cell. The readout data is latched in a sense amplifier/data latch circuit. 
     A write verify cycle will be described below. 
     After write data is input, a set voltage (e.g., 20 V) is applied to selected control gates for a set time (e.g., 40 μsec), Thereafter, a read operation is performed to confirm the completion of the write operation. If there are any memory cells which have undergone an insufficient write operation, a write operation is performed again with respect to these memory cells by applying a voltage of 20 V thereto for 40 μsec. At this time, with respect to memory cells which have undergone a sufficient write operation, the potential V bitH  is applied to the bit line to prevent further electron injection. That is, the write operation with a voltage of 20 V and a writing time of 40 μsec is repeated until the data is completely written in all the memory cells. 
     Table 1 shows potentials at the respective portions in this case. 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Number of 
                   
                   
                   
                   
                   
               
               
                   
                 Times of 
               
               
                   
                 Write 
                 First 
                 Second 
                 Third 
                 Fourth 
                 Fifth 
               
               
                   
                 Operations 
                 Time 
                 Time 
                 Time 
                 Time 
                 Time 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 (V bitH ) 
                 bit line 
                 8V 
                 8V 
                 8V 
                 8V 
                 8V 
               
               
                   
                 “1” 
               
               
                   
                 bit line 
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 8V 
               
               
                   
                 “0” 
               
               
                 (V M ) 
                 SG D   
                 10V 
                 10V 
                 10V 
                 10V 
                 10V 
               
               
                 (V M ) 
                 CG 1  to CG 7   
                 10V 
                 10V 
                 10V 
                 10V 
                 10V 
               
               
                 (V PP ) 
                 CG 8   
                 20V 
                 20V 
                 20V 
                 20V 
                 20V 
               
               
                   
                 (selected) 
               
               
                   
                 CG S   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
               
               
                   
               
             
          
         
       
     
     In the above write method of verifying data in units of blocks (or chips), a method of writing data while increasing the voltage (high voltage V pp ) applied to each control gate so as to shorten the programming time is known (to be referred to as a chip-by-chip verify voltage increasing method hereinafter). 
     This write method will be described below with reference to FIG.  1 . In the method, a program is written by the following procedure. 
     There are variations in process and threshold value among the respective memory cells. For example, in this case, the threshold value of a memory cell having the minimum threshold value (i.e., a hardest cell M 2  to write thereto) is set to be V th =−4 V (A 0  in FIG.  1 ); a memory cell having the maximum threshold value (i.e., an easiest memory cell M 1  to write thereto) is set to be V th =−1 V (B 0  in FIG.  1 ); and the threshold value of a memory cell in which “0” is written is set to fall within the range of 0.5 V to 2 V. 
     A page (or a chip) is selected first. 
     The potential V SS  (e.g., 0 V) for “0” write operation or the potential V bitH  (e.g., 10 V) for “0” write operation is applied to the bit line connected to each memory cell of the selected page in accordance with data to be written. 
     Thereafter, the first write operation is performed by applying the high voltage V pp  (e.g., 18.5 V) to each selected word line (i.e., the control gate of each selected memory cell). 
     Upon completion of the first write operation, it is checked whether the threshold value V th  of each memory cell has reached a completion determination level (verify operation). At this time, the threshold value V th  of the memory cell M 1  is 0 V (B 1 ), and the threshold value V th  of the memory cell M 2  is −3 V (A 1 ). 
     Since both the threshold values V th  of the memory cells M 1  and M 2  are lower than a predetermined value, it is determined that the write processing is not completed. As a result, a constant voltage V pp  (e.g., 19.5 V) higher than the voltage applied in the first write operation is applied to each selected word line, thus performing the second write operation. With the second write operation, the threshold value V th  of the memory cell M 1  becomes 3 V (B 3 ), and hence falls within the predetermined range. However, the threshold value V th  of the memory cell M 2  is −0.5 V (A 3 ), and hence falls outside the predetermined range. Therefore, it is determined that the write processing is not completed. 
     In order to perform a write operation with respect to the memory cell M 2 , a constant voltage V pp  (e.g., 20.5 V) higher than the voltage applied in the second write operation is applied to each selected word line, thus performing the third write operation. Subsequently, verify and write operations are performed, while the voltage of the selected word line is gradually increased, until the write processing with respect to the hardest memory cell M 2  to write thereto is completed (the threshold value falls within the predetermined range). 
     This method is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 61-239497. 
     In the above method, the voltage V pp  applied to selected word line is sequentially increased until all the memory cells on a selected page are programmed. The finally applied voltage V pp  (=21.5 V) is equally applied to both the hardest memory cell to write thereto and the easiest memory cell to write thereto. That is, data is written in all memory cells by using the same voltage V pp . 
     The programming time, therefore, can be shortened. However, the easiest memory cell to write thereto is subjected to over-programming. 
     In order to solve the above problem, a method of verifying memory cells in units of bits (to be referred to as a bit-by-bit verify fixed voltage method hereinafter) may be used. 
     This method will be described below with reference to FIG.  2 . 
     There are process variations among the respective memory cells and variations in threshold value depending on the application states of the memory cells. For example, in this case, a memory cell having the minimum threshold value (i.e., an easiest memory cell M 2  to write thereto) is set to be V th =−3 V (CO in FIG.  2 ); a memory cell having the maximum threshold value (i.e., a hardest memory cell M 1  to write thereto) is set to be V th =0 V (D 0  in FIG.  2 ); and the threshold value V th  of a memory cell in which “0” is to be written is set to fall within the range of 0.5 V to 2 V. 
     A given page (or a chip) is selected first. 
     A voltage V SS  (eg., 0 V) for “0” write operation or a voltage V bitH  (e.g., 10 V) for “1” write operation is applied to a bit line connected to each memory cell of the selected page in accordance with data to be written. 
     The first write operation is performed by applying a high voltage V pp  (=18.5 V) to each selected word line (i.e., the control gate of each selected memory cell). 
     Upon completion of the first write operation, it is checked whether the threshold value V th  of each memory cell has reached a completion determination level (verify operation). In this case, the threshold value V th  of the memory cell M 1  is 1 V (C 1 ), and hence falls within the predetermined range. However, the threshold value V th  of the memory cell M 2  is −2 V (D 1 ), and hence falls outside the predetermined range. 
     Therefore, it is determined that the write processing is not completed. 
     A voltage of 10 V is applied to bit lines connected to memory cells (not shown) for which no write operation is to be performed and memory cells for which data processing is completed, and a voltage of 0 V is applied to a bit line connected to memory cells for which write processing is not completed. In addition, the same voltage V pp  (18.5 V) as that applied in the first write operation is applied to each selected word line for a slightly longer period of time than in the first write operation. 
     The above operation is repeated until write processing with respect to the hardest memory cell M 2  to write thereto is completed (the threshold value falls within the predetermined range). 
     This method is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 1-159895. 
     In the above method, since data is verified in units of memory cells, over-programming with respect to memory cells can be prevented. That is, the width of the threshold value distribution of memory cells can be set within a predetermined (desired) range. All the memory cells on a selected page are programmed by the same voltage V pp  (18.5 V). Since a memory cell exhibiting a low programming speed (a hard memory cell to write thereto) and a memory cell exhibiting a high programming speed (an easy memory cell to write thereto) are programmed by the same voltage, it takes much time to completely program all the memory cells. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a non-volatile semiconductor memory device which can prevent a dielectric breakdown of a tunnel oxide film and an increase in leakage current in data erase and write operations, and can improve the reliability of each memory cell. 
     It is another object of the present invention to provide a non-volatile semiconductor memory device having a write verify scheme which can suppress an increase in writing time even if cell characteristics vary. 
     It is still another object of the present invention to provide an EEPROM which can ensure a sufficient writing voltage V pp  margin, can reduce the width of the threshold value distribution of memory cells, and can perform electron injection at high speed. 
     The gist of the present invention is to program with the optimal program condition by bit during a page programming. This technology is named as bit by bit program voltage selected page programming method. A specific embodiment is to gradually increase a writing voltage V pp  (or gradually decrease a voltage V CC  of a selected gate) while a write operation/bit-by-bit verify operation cycle is repeated. The writing voltage V pp  is increased by Δ V pp  for every cycle, and a writing time Δ t for one write operation is made constant. In addition, the values Δ V pp  and Δ t are set such that the width of a threshold value distribution after a “0” write operation becomes the value Δ V pp . 
     The characteristic features of the present invention will be described in more detail below. 
     A non-volatile semiconductor memory device according to the first aspect of the invention is characterized by comprising: a semiconductor substrate; a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges; and means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer. 
     A non-volatile semiconductor memory device according to another first aspect of the invention is characterized by comprising: a semiconductor substrate; a plurality of memory cells, each including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cells being capable of electrically rewriting data by exchanging charges between the charge storage layers and the semiconductor substrates and being arranged in the form of a matrix; and means for applying a high potential to the semiconductor substrate and the control gate of each non-selected memory cell and applying an intermediate potential to the control gate of a selected memory cell in a first data erase operation, and applying a high potential to the semiconductor substrate and the control gate of each non-selected memory cell and applying a potential lower than the intermediate potential to the control gate of the selected memory cell in second and subsequent data erase operations, thereby removing electrons from the charge storage layer. 
     According to the first aspect of the present invention, before a data write operation is performed, the data in each memory cell is data “1” or “0”. In this case, the threshold value of a memory cell having data “0” is higher than a reference potential. That is, many electrons are injected into the charge storage layer. Thereafter, a high potential is applied to the substrate to discharge the electrons from the charge storage layer to the substrate, thereby erasing the data. When data “0” is stored, since electrons are present in the charge storage layer, a higher electric field is applied to the tunnel oxide film. 
     In the first aspect, the high potential is a boosted potential, the intermediate potential is a power supply potential, and the low potential is a ground potential. 
     According to the present invention, in the first erase operation, a high potential (to be referred to as, for example, an “H”-level potential) is applied to the substrate, and an intermediate potential (to be referred to as, for example, an “M” level) is applied to the control gate. In practice, a voltage applied between the gate and the substrate corresponds to the difference between the “H”- and “M”-level potentials, and the peak electric field applied to the tunnel oxide film is reduced. At this time, the threshold value shifts in the negative-value direction, and the number of electrons in the charge storage layer decreases. In the second erase operation, for example, an “H”-level potential is applied to the substrate, and a low potential (to be referred as an “L”-level potential) or a potential lower than the “M”-level potential is applied to the control gate. With this operation, although a higher voltage is applied, the peak electric field applied to the tunnel oxide film can be suppressed because electrons are removed from the charge storage layer, and its potential is decreased. In this case, a potential of the control gate and the substrate thereof may be inversely set and may use during the program. 
     In the above-described manner, the peak electric field applied to the tunnel oxide film is suppressed, and the problems of a dielectric breakdown and an increase in leakage current can be solved. 
     A non-volatile semiconductor memory device according to the second aspect of the invention is characterized by comprising: a memory cell array including a plurality of memory cells, which are arranged in matrix, capable of electrically rewriting and erasing data and connected in series such that the memory cells share drains and sources; a plurality of bit lines coupled to the drain of the memory cells; a plurality of word lines which are control gates of the memory cells; write means for, when a page write operation is to be performed, applying a first writing potential to a selected word line, applying a first bit line potential to a bit line which is connected to the selected word line and to which a memory cell a memory cell in which data is to be written is connected, and applying a second bit line potential to a bit line which is connected to the selected word line and to which a memory cell in which no data is to be written is connected; and rewrite means for reading out data written by the write means, causing the write means to perform a write operation again if there is a memory cell which has undergone an insufficient write operation, and sequentially increasing the first writing potential in accordance with the number of times of write operations. 
     The rewrite means is characterized by including means for variably setting the first and second bit line potentials. 
     According to the second aspect of the present invention, a writing voltage V pp  applied to each selected control gate of a selected block, a bit line potential transfer potential V M  applied to each non-selected control gate of the selected gate, a bit line potential V bitH  applied to each cell in which “1” is to be written, and the like are controlled in accordance with the number of times of verify write operations. More specifically, a predetermined number of times of write operations is detected, and these voltages are increased within predetermined ranges. For example, in a conventional scheme, the same V pp  pulse voltage is repeatedly applied (20 V-20 V-20V). In the present invention, the V pp  pulse voltage is sequentially increased from 19 V to 21 V at a rate of 1 V (19 V-20 V-21 V-21V). In addition, the set voltage is increased in accordance with a predetermined relationship between the potentials V M  and V bitH . As described above, terminating potential of V pp  (e.g., 21 V) is determined by a rated potential of the device. 
     With the above arrangement, the following effects can be obtained. 
     First, an effect obtained by decreasing the first writing potential will be described. The first writing voltage is lower than that in the conventional scheme. If a limiter exhibits a variation in the direction of higher voltages (+0.5 V), a voltage of 20.5 V is output with respect to a set voltage of 20 V in the conventional scheme. As a result, the easiest memory cell to write thereto with a 40-μsec pulse reaches 2 V which is the upper limit of a threshold value distribution. This pulse width determines the minimum pulse width. 
     In the present invention, even if a limiter exhibits a variation in the direction of higher voltages, since the first writing voltage is set to be lower than that in the conventional scheme by 1 V, the threshold value of even the easiest memory cell to write thereto exceeds 2 V with a 200-μsec pulse. That is, with a 40-μsec pulse, even if the output voltage of the limiter shifts in the direction of higher voltages, the threshold value does not exceed the upper limit of a threshold value distribution. As a result, process control of the limiter is facilitated to improve the yield. 
     Second, an effect obtained by increasing the writing voltage in the second and third operations will be described. Consider a case wherein the limiter exhibits a variation in the direction of lower voltages. In the conventional scheme, a voltage of 19.5 V is output with respect to a set voltage of 20 V. In this case, a writing time of 400 μsec is required to write data in the easiest memory cell to write thereto up to a lower limit of 0.5 V. In the above case with the minimum pulse width being 40 μsec, write and verify operations must be repeated 10 times at maximum. 
     According to the present invention, since the writing voltage is gradually increased, the voltage of the first write pulse is lower than that in the conventional scheme. However, the writing voltage is increased in the second and third operations. Even if, therefore, the voltage in the third and subsequent operations is fixed, data is written in the memory cell up to the threshold value lower limit (0.5 V) with five writing operations using a 40-μsec write pulse. The writing time is shortened to ½ the writing time in the conventional scheme. The writing time is shortened more as the threshold value distribution (calculated as q 1  V in the above case) without a verify operation expands. 
     Third, the reliability of a memory cell will be described. It is known that a deterioration in a memory is greatly associated with the maximum electric field applied to the tunnel oxide film in a write operation. Consider the easiest memory cell to write thereto in a case wherein a limiter exhibits a variation in the direction of higher voltages in a conventional method. Before the first write operation, each memory cell is in an erased state and has a negative threshold value. In general, an easy memory cell to write thereto is a memory cell which can be easily erased, and hence has a large negative value. When a writing voltage exhibiting a variation in the direction of higher voltages is applied to this memory cell, a very high electric field is applied to the tunnel oxide film, resulting in a deterioration in the memory cell. 
     According to the present invention, since the writing voltage for the first write operation is set to be low, only a low electric field is applied to the tunnel oxide film as compared with the conventional method. Therefore, a deterioration in the memory cell can be suppressed. 
     Fourth, consider a case wherein the bit line potential transfer voltage V M  applied to each non-selected control gate of a selected block and the bit line potential V bitH  applied to each cell in which “1” is written are increased with an increase in V pp . 
     V pp  and V bitH  are respectively applied to the control gate and source/drain of each memory cell in which “1” is written and each memory cell in which “0” is completely written so as not to inject electrons therein any more. Therefore, a write error can be prevented by increasing V bitH  with an increase in V pp . For this reason, the voltage V M  of each non-selected gate is increased to transfer V bitH . Since each memory cell connected to a non-selected control gate is subjected to a weak write mode in which V M  and V SS  are respectively applied to the gate and the source/drain, V pp  and V bitH  need to be increased proportionately to prevent a write error. 
     As described above, according to the present invention, an improvement in the reliability of each memory cell and a high-speed write operation can be achieved at the same time. 
     A non-volatile semiconductor memory device according to the third aspect of the invention is characterized by further comprising means for setting a rise time of a first write pulse to be longer than a rise time of second and subsequent pulses in a data write operation using a plurality of pulses in addition to the device of the first aspect. 
     The effects of the third aspect of the present invention will be described below. Consider an EEPROM in which a data write or erase operation is performed by supplying an F-N tunnel current to the entire gate insulating film of a memory cell to store negative or positive charges in the charge storage layer. It is known that in general, as the F-N tunnel current flows in the gate insulating film, a leakage current on the low-electric-field side increases, and the data holding characteristics deteriorate. It is also known that the degree of this deterioration in the gate insulating film depends on an electric field applied to the gate insulating film, and can be suppressed by reducing the electric field. 
     In a memory cell, letting C 1  be the capacitance of a capacitor constituted by the substrate and the charge storage layer, C 2  be the capacitance of a capacitor constituted by the charge storage layer and the control gate, V pp  is the potential applied to the control gate in a write operation, V 1  is the potential difference applied to the capacitance C 1 , Q be the charges stored in the charge storage layer, and T ox  be the thickness of the gate insulating film, an electric field E ox  applied to the gate insulating film can be given by 
     In an EEPROM using n-channel cell transistors, a write operation is performed by injecting electrons into a charge storage layer to store negative electrons therein. It is, therefore, apparent that the electric field E ox  decreases as write processing progresses. In this case, injection of electrons is performed by using the F-N tunnel current, and the intensity of the F-N tunnel current is highly proportional to the electric field E ox  applied to the gate (tunnel) insulating film. Therefore, a decrease in the electric field E ox  with the progress of write processing is equivalent to a degradation in electron injecting efficiency with the progress of write processing. 
     Similar to the first aspect of the present invention, a high voltage as the voltage V pp  is required when write processing progresses to a certain extent, but a sufficient injecting efficiency can be obtained by using a relatively low voltage as the voltage V pp  in the initial period of the write processing. At the same time, the maximum value of the electric field E ox  applied to the gate insulating film can be suppressed to a low value by decreasing the voltage V pp  in the initial period of the write processing, thereby reducing a deterioration in the gate insulating film. More specifically, this effect can be obtained by prolonging the rise time of the first pulse of a plurality of pulses in a write operation. As the rise time is prolonged, a greater effect is expected. However, in consideration of a writing speed, it is not practical to prolong the rise time too much. 
     In a write operation using the second and subsequent pulses, since a certain amount of charges are stored in the charge storage layer, even if the pulse rise time is prolonged, the effect for the deterioration in the gate insulating film cannot be expected as much as in the first write operation. Therefore, the pulse rise time need not be prolonged any more. The extent to which the rise time of the first pulse is prolonged is determined in consideration of a writing speed. However, if at least the rise time of the first pulse is set to be longer than a normal rise time (the rise time of the second and subsequent pulses), a deterioration in the gate insulating film can be suppressed as compared with that in a normal write operation. 
     According to the first to third aspects of the present invention, since the peak electric field applied to a tunnel oxide film in a data erase or write operation can be suppressed, a dielectric breakdown of the tunnel oxide film and an increase in leakage current can be prevented, thus improving the reliability of each memory cell. A write verify scheme can be realized, in which even if cell characteristics vary, the prolongation of the writing time can be suppressed by controlling the writing potential in accordance with the number of times of write operations. 
     A non-volatile semiconductor memory device according to the fourth aspect of the invention is characterized by comprising: a semiconductor substrate; a memory cell array constituted by memory cells capable of electrically rewriting data and arranged in the form of a matrix, each of the memory cells being formed by stacking a charge storage layer and a control gate on the semiconductor substrate; threshold value changing means for applying a threshold value changing voltage pulse between the control gate and the semiconductor layer to change a threshold value of each of an arbitrary number of memory cells in the memory cell array; threshold value verify means for detecting states of the arbitrary number of memory cells after application of the threshold value changing voltage pulse; threshold value re-changing means for applying a threshold value changing voltage pulse to a memory cell, of the arbitrary number of memory cells, whose threshold value has not reached a desired threshold value yet, for a time Δ t, thereby changing the threshold value again; and repeating means for, after a threshold value changing operation and a threshold value verify operation are respectively performed by the threshold value changing means and the threshold value verify means, repeating a threshold value re-changing operation by the threshold value re-changing means and the threshold value verity operation until the threshold value of the memory cell reaches the desired value, wherein the threshold value re-changing means includes means for increasing a potential of the threshold value changing voltage pulse by a pulse peak value increase Δ V pp  every time a threshold value re-changing operation is performed, and the repeating means includes means for electrically erasing or writing data such that a width of a threshold value distribution of the memory cell whose threshold value has reached the desired threshold value becomes |Δ V pp |. 
     A non-volatile semiconductor memory device according to another fourth aspect of the invention is characterized by comprising: a memory cell array constituted by memory cells capable of electrically rewriting data and arranged in the form of a matrix, each of the memory cells being formed by stacking a charge storage layer and a control gate on a semiconductor layer; erase means for performing an erase operation to set data in each memory cell of the memory cell array to “0”; pulse applying means for applying threshold value changing voltage pulses (V pp1 , V pp2 , . . . , V ppn ) corresponding to write data (“1”, “2”, . . . , “n”) between the control gate and the semiconductor layer to change a threshold value of each of an arbitrary number of memory cells in the memory cell array; threshold value verify means for detecting states of the arbitrary number of memory cells upon application of the threshold value changing voltage pulses; rewrite pulse applying means for applying threshold value changing voltage pulses corresponding to the write data to memory cells, of the arbitrary number of memory cells, whose threshold value values have not reached desired threshold values (V th1 , V th2 , . . . V thn ) corresponding to the write data (“1”, “2”, . . . , “n”), thereby changing the threshold values again in accordance with the write data; and repeating means for, after a threshold value changing operation and a threshold value verify operation are respectively performed by the write pulse applying means and the threshold value verify means, repeating a threshold value re-changing operation by the rewrite pulse applying means and the threshold value verify operation until the threshold values of the memory cells reach the desired values corresponding to the write data, wherein the write pulse applying means includes means for setting the threshold value changing voltage pulses according to V pp1 =V pp2 −Δ V ppd2 =V pp3 −Δ V ppd3 = . . . =V ppn−Δ V   ppdn , and the rewrite pulse applying means includes means for setting the desired threshold values according to V thi −V thi−1 =Δ V ppdi  (i=2, 3, . . . , n). 
     The preferred embodiments of the fourth aspect of the present invention are as follows. 
     (1) The write pulse applying means includes means for applying a threshold value changing voltage pulse for a time Δ t 0 , the rewrite pulse applying means includes means for applying a threshold value changing voltage pulse for a time Δ t, and means for increasing the threshold value changing voltage pulse by a pulse peak value increase Δ V pp  every time a threshold value re-changing operation is performed, and the repeating means includes means for electrically writing data such that a width of a threshold value distribution of the memory cell whose threshold value has reached the desired threshold value becomes |ΔV pp |. 
     (2) The rewrite pulse applying means includes means for keeping a peak value of a threshold value changing voltage pulse constant. 
     (3) The rewrite pulse applying means includes means for increasing a peak value of a threshold value changing voltage pulse by a pulse peak value increase Δ V pp  for a time corresponding to a pulse width Δ t, and means for increasing a peak value of a threshold value changing voltage pulse by Δ V pp ×Δ t 0 /Δ t for a time corresponding to a pulse width Δ t 0 . 
     (4) The rewrite pulse applying means includes means for increasing a peak value of a threshold value changing voltage pulse by a pulse peak value increase Δ V pp  at a predetermined increase rate for a time corresponding to a pulse width Δ t, and means for increasing a peak value of a threshold value changing voltage pulse by Δ V pp ×Δ t 0 /Δ t at a predetermined increase rate for a time corresponding to a pulse width Δ t 0 . 
     (5) Δ threshold value changing pulse width Δ t 0  used in a threshold value changing operation is equal to a threshold value changing pulse width Δ t used in a threshold value re-changing operation. 
     (6) A threshold value changing pulse width Δ t 0  used in a threshold value changing operation is larger than a threshold value changing pulse width Δ t used in a threshold value re-changing operation. 
     In the present invention, the writing voltage V pp  is gradually increased with the lapse of a writing time. With this operation, write processing with respect to an easy memory cell to write thereto is completed by using a relatively low writing voltage V pp , and write processing with respect to a hard memory cell to write thereto is performed by using a relatively high writing voltage V pp , thereby obtaining a wide writing voltage V pp  margin. 
     To set the values Δ V pp  and Δ t such that the width of a threshold value distribution after a “0” write operation becomes Δ V pp  means that the threshold value shift amount in one cycle is almost the constant value Δ V pp . Therefore, the voltage applied to an insulating film in which a tunnel current flows is controlled to be uniform in every cycle, and the maximum value of the voltage can be reduced, resulting in an improvement in reliability. 
     The preferred embodiments of the first to fourth aspects of the present invention are as follows. 
     (1) The memory cells construct NAND cell structure by connecting the plurality of memory cells in series. 
     (2) A first selecting gate connected to one end of the NAND cell and the bit line; a second selecting gate connected to another end of the NAND cell; and a source line connected to another end of the NAND cell via the second selecting gate is further provided. 
     (3) The plurality of memory cells construct memory cell unit by connecting to the bit lines in parallel. 
     (4) The memory cells, whose common drain is connected to the bit line via a first selecting gate and common source is connected to a common source line via a second selecting gate, construct NOR structure by connecting to the bit line in parallel. 
     (5) Means for setting a potential of a first write pulse to a potential to prevent overprogram for the easiest memory cell to write thereto during data write by a plurality of pulses is further provided. 
     (6) Means for setting a upper-limit potential of a write pulse to a rated potential of the memory cells and peripheral circuits during data write by a plurality of pulses is further provided. 
     According to the present invention, there is provided an EEPROM which can ensure a sufficient V pp  margin, can reduce the width of the threshold value distribution of memory cells, and allows a high-speed electron injecting operation by gradually increasing the writing voltage V pp  while repeating a write operation/bit-by-bit verify operation cycle. An electron discharging operation can be easily performed by inverting the polarity of the voltage of the control gate of each memory cell. In addition, the present invention can be equally applied to a device using a p-channel MOS transistor as a memory cell. 
     Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the present invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the present invention in which: 
     FIG. 1 is a graph for explaining a chip-by-chip verify voltage increasing method; 
     FIG. 2 is a graph for explaining a bit-by-bit verify fixed voltage method; 
     FIG. 3 is a graph for explaining the present invention; 
     FIG. 4 is a graph showing the relationship between the programming time and the width of the threshold value distribution of memory cells; 
     FIG. 5 is a graph showing the relationship between the maximum electric field (peak electric field) and the coupling factor; 
     FIG. 6 is a block diagram showing a NAND-type EEPROM system arrangement according to the first embodiment of the present invention; 
     FIGS. 7A and 7B are perspective and plan views, respectively, showing an LSI memory card as an example of the system arrangement shown in FIG. 6; 
     FIG. 8 is a block diagram showing the arrangement of a NAND-type EEPROM according to the first embodiment; 
     FIGS. 9A and 9B are a plan view and an equivalent circuit diagram, respectively, of one NAND cell portion of a memory cell array; 
     FIGS. 10A and 10B are sectional views taken along lines  10 A- 10 A′ and  10 B- 10 B′ in FIG. 9A, respectively; 
     FIG. 11 is an equivalent circuit diagram of a cell array constituted by NAND cells arranged in the form of a matrix; 
     FIG. 12 is a circuit diagram showing the detailed arrangement of a row decoder of a NAND-type EEPROM; 
     FIG. 13 is a timing chart showing the waveforms of voltages applied to a substrate, a control gate, and a selection gate in a data erase operation; 
     FIG. 14 is a flow chart showing write processing; 
     FIG. 15 is a circuit diagram showing a sense amplifier/data latch circuit; 
     FIG. 16 is a circuit diagram showing a limiter circuit for realizing a write operation in the embodiment; 
     FIG. 17 is a block diagram showing a concept of a circuit for applying a writing potential; 
     FIG. 18 is a circuit diagram showing a circuit for variably changing the period of a ring oscillator; 
     FIGS. 19A and 19B are a sectional view and an equivalent circuit diagram, respectively, of the structure of a memory cell used in the embodiment of the present invention; 
     FIGS. 20A to  20 D are charts showing electron injection characteristics obtained by an electron injection scheme using a verify operation in the second embodiment of the present invention when the selected cells are programmed by “0” data; 
     FIGS. 21A to  21 D are charts showing electron injection characteristics obtained by an electron injection scheme using a verify operation in the third embodiment of the present invention; 
     FIGS. 22A and 22B are charts showing changes in the threshold values of memory cells in an electron injection scheme using a bit-by-bit verify operation in the third embodiment; 
     FIGS. 23A to  23 D are charts showing electron injection characteristics obtained by an electron injection scheme using a verify operation to improve the controllability of the threshold value of each memory cell in the third embodiment; 
     FIGS. 24A to  24 D are charts showing electron injection characteristics obtained by an electron injection scheme using a verify operation in the fourth embodiment of the present invention; 
     FIGS. 25A to  25 D are charts showing electron injection characteristics obtained by an electron injection scheme using a verify operation in the fifth embodiment of the present invention; 
     FIGS. 26A and 26B are charts showing the first modification of the electron injection scheme using the verify operation in the fifth-embodiment; 
     FIGS. 27A and 27B are charts showing the second modification of the electron injection scheme using the verify operation in the fifth embodiment; 
     FIG. 28 is a circuit diagram showing a memory cell array of NAND-type EEPROMs in the sixth embodiment of the present invention; 
     FIG. 29 is a block diagram showing the arrangement of a circuit for driving control gates in the sixth embodiment; 
     FIG. 30 is a diagram showing the circuit arrangement of a control gate driver in the sixth embodiment; 
     FIG. 31 is a circuit diagram showing the detailed circuit arrangement of a control gate driver in the sixth embodiment; 
     FIGS. 32A and 32B are circuit diagrams showing the detailed arrangement of a current control circuit in a control gate driver in the sixth embodiment; 
     FIG. 33 is a timing chart for explaining a write/verify operation in the sixth embodiment; 
     FIG. 34 is a chart showing the write characteristics of memory cells in the sixth embodiment; 
     FIG. 35 is a block diagram showing the arrangement of a control gate driver in the seventh embodiment of the present invention; 
     FIG. 36 is a circuit diagram showing the detailed circuit arrangement of a control gate driver in the seventh embodiment; 
     FIG. 37 is a timing chart for explaining a write/verify operation in the seventh embodiment; and 
     FIGS. 38A and 38B are charts showing an electron injection scheme using a verify operation and its electron injection characteristics in the eighth embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention will be described below with reference to the accompanying drawings. 
     The gist of the present invention is to gradually increase a writing voltage V pp  (or gradually decrease a voltage V CC  of a selected gate) while a write operation/bit-by-bit verify operation cycle is repeated. First, the features of the invention will be explained. 
     The features of the present invention will be described below with reference to FIGS. 3 to  5 . 
     The present invention will be described with reference to FIG.  3 . 
     In this case, a memory cell having the minimum threshold value (i.e., a hardest memory cell M 2  to write thereto) is set to be V th =−4 V (E 0  in FIG.  3 ); a memory cell having the maximum threshold value (i.e., an easiest memory cell M 1  to write thereto) is set to be V th =−1 V (F 0  in FIG.  3 ); and the threshold value V th  of a memory cell in which “0” is to be written is set to fall within the range of 0.5 V to 2 V. 
     A given page (or a chip) is selected. 
     A potential V SS  (e.g., 0 V) for a “0” write operation or a potential V bitH  (e.g., 10 V) for a “1” write operation is applied to a bit line connected to each memory cell of the selected page in accordance with data to be written. In this case, there are process variations among the respective memory cells and variations in threshold value depending on the used states of the memory cells (i.e., V pp  is applied to a selected page). 
     The first write operation is performed by applying a high voltage V pp  (=18.5 V) to each selected word line (i.e., the control gate of each selected memory cell). 
     Upon completion of the first write operation, it is checked whether the threshold value V th  of each memory cell has reached a completion determination level (verify operation). In this case, the threshold value V th  of the memory cell M 1  is 1 V (E 1 ), and hence falls within the predetermined range. However, the threshold value V th  of the memory cell M 2  is −2 V (F 1 ), and hence falls outside the predetermined range. Therefore, it is determined that the write processing is not completed. 
     A voltage of 10 V is applied to bit lines connected to memory cells (not shown) for which no write operation is to be performed and memory cells for which data processing is completed, and a voltage of 0 V is applied to a bit line connected to memory cells for which write processing is not completed. In addition, a constant voltage V pp  (19.5 V) higher than that applied in the first write operation is applied to each selected word line, thus performing the second write operation. With the second write operation, the threshold value V th  of the memory cell M 1  becomes 3 V (F 3 ), and hence falls within the predetermined range. However, the threshold value V th  is −0.5 V (E 3 ), and hence falls outside the predetermined range. Therefore, it is determined that the write processing is not completed. 
     In order to write data in the memory cell M 2 , a constant voltage V pp  (e.g., 20.5 V) higher than the voltage applied in the second write operation is applied to the selected word line, thus performing the third write operation. Subsequently, verify and write operations are performed while the voltage applied to the selected word line is gradually increased until the write processing with respect to the hardest memory cell M 2  to write thereto is completed (the threshold value falls within the predetermined range). Therefore, since memory cells having slow program characteristics is programmed by 20.5 V, and memory cells having fast program characteristics is programmed by 19.5 V, memory cells are programmed by optimal V pp . The inventors calls this method as a bit-by-bit V pp  (program voltage) selected page program method (technology). 
     With the above processing, no memory cell is subjected to over-programming as in the bit-by-bit verify fixed voltage method, and the prolongation of the programming time as in the chip-by-chip verify voltage increasing method can be prevented. 
     FIG. 4 is a graph showing the relationship between the programming time and the width of the threshold value distribution of the respective memory cells after write processing. In this graph, the ordinate indicates the programming time, and the abscissa indicates the range of threshold voltage variations. Referring to FIG. 4, a curve A indicates the case of the chip-by-chip verify voltage increasing method; a curve B, the case of the bit-by-bit verify fixed voltage method; and a curve C, the case of the present invention. 
     In the case of the chip-by-chip verify voltage increasing method, the width of the threshold value distribution of the respective memory cells cannot be corrected by a program, and does not depend on the programming time. 
     In the case of the bit-by-bit verify fixed voltage method, as variations in the threshold values of the respective memory cells after write processing are to be made small, a longer writing time is required. For example, if the width of the threshold value distribution is 2 V, the writing time is about 500 μsec. If, however, the width of the threshold value distribution is 1 V, the writing time is prolonged about three times. 
     As compared with the above two methods, in the present invention, if the threshold value variation is set to be 0.5 V, the writing time is about 300 μsec. That is, write processing can be performed with a small threshold value variation without requiring a long writing time. 
     FIG. 5 is a graph showing the relationship between the maximum electric field (peak electric field) and the coupling factor. In this graph, the ordinate indicates the maximum electric field; and the ordinate, the coupling factor. Since the types of curves in FIG. 5 are the same as those in FIG. 4, a description thereof will be omitted. 
     Referring to FIG. 5, curves A and C have almost the same characteristics. A curve B indicates that as the coupling factor increases, the maximum electric field increases (if, for example, the coupling factor is 0.5, the maximum electric field is about 1.2 times that indicated by the curves A and C). Therefore, the peak electric field applied to a tunnel oxide film increase, and problems are posed in terms of dielectric breakdown and leakage current. 
     FIG. 6 is a block diagram showing the system arrangement of NAND-type EEPROMs according to the present invention. This EEPROM system includes a plurality of NAND-type EEPROMs  1  and a control circuit  2  for controlling a data rewrite operation with respect to each NAND-type EEPROM  1 . 
     FIGS. 7A and 7B are perspective and plan views, respectively, showing an LSI memory card as an example of the system arrangement shown in FIG. 1. A card body  3  of the LSI memory card incorporates four NAND-type EEPROMs  1  and one control circuit  2 . The card body  3  is connected to an external unit via a terminal  4 . 
     FIG. 8 is a block diagram showing the circuit arrangement of a NAND-type EEPROM according to the first embodiment of the present invention. 
     The NAND-type EEPROM of the first embodiment includes a memory cell array  21 , a row decoder  22 , a control gate control circuit  23 , a substrate potential control circuit  24 , a data input/output buffer  25 , a bit line control circuit  26 , a column decoder  27 , and an address buffer  28 . 
     The control gate control circuit  23  outputs predetermined control signals corresponding to data write, erase, read, and verify operations to control gate lines, of the memory cell array  21 , which are selected by the row decoder  22 . 
     The substrate potential control circuit  24  controls a p-type well constituting a cell at a potential of 0 V in a normal operation, and at a potential V pp  (about 20V) in an erase operation. 
     The bit line control circuit  26  performs data write and read operations with respect to the memory cell array  21 . The bit line control circuit  26  is connected to the data input/output buffer  25 . 
     The address buffer  28  transfers an input address to the row decoder  22  and the column decoder  27 . 
     Although not shown, the NAND-type EEPROM of the first embodiment further includes write, erase, and intermediate potential generating circuits for respectively applying a writing potential V W , an erase potential V E , and an intermediate potential V M , required for data write, erase, and read operations, to control gate lines, bit lines, the substrate, and the like. 
     FIGS. 9A and 9B are a plan view and an equivalent circuit diagram, respectively, of one NAND cell portion of the memory cell array. FIGS. 10A and 10B are sectional views taken along lines  10 A- 10 A′ and  10 B- 10 B′ in FIG. 9A, respectively. 
     A memory cell array constituted by a plurality of NAND cells is formed in a p-type silicon substrate (or p-type well)  11  surrounded by an element isolation oxide film  12 . 
     The arrangement of memory cells will be described below, considering one NAND cell. 
     One NAND cell is constituted by eight series-connected memory cells M 1  to M 8 . Each memory cell has the following arrangement. Δ floating gate  14  ( 14   1 ,  14   2 , . . . ,  14   8 ) is formed on the substrate  11  via a gate oxide film  13 . A control gate  16  ( 16   1 ,  16   2 , . . . ,  16   8 ) is formed on the floating gate  14  via an insulating interlayer  15 . These memory cells are connected in series in such a manner that the respective adjacent memory cells share n-type diffusion layers  19  serving as the sources and drains of the memory cells. With this arrangement, a NAND cell is formed. 
     Two pairs of selection gates  14   9  and  16   9 , and  14   10  and  16   10 , which are formed simultaneously with the floating and control gate of each memory cell, are respectively formed on the drain and source sides of the NAND cell. The substrate having elements formed thereon is covered with a CVD oxide film  17 . A bit line  18  is arranged on the CVD oxide film  17 . The bit line  18  is in contact with a drain diffusion layer  19  at one end of the NAND cell. 
     The control gates  16  of the NAND cell are arranged in the row direction as control gate lines CG 1 , CG 2 , . . . , CG 8  serving as word lines. The selection gates  14   9 ,  16   9 ,  14   10 , and  16   10  are also continuously arranged in the row direction as selection gate lines SG S  and SG D . 
     FIG. 11 is an equivalent circuit diagram of the memory cell arrays having the above NAND cells arranged in the form of a matrix. 
     FIG. 12 shows the detailed arrangement of the row decoder of a NAND-type EEPROM. 
     The row decoder includes an enable circuit constituted by E type n-channel MOS transistors Q n4l   and Q n42  and E type p-channel MOS transistors Q p11  and Q pl2 , and a transfer circuit constituted by E type n-channel MOS transistors Q n43  and Q n44  and E type p-channel MOS transistors Q p13  and Q p14 . 
     The row decoder is activated by an address signal a i  and a decoder enable signal RDENB to select a block, of the memory cell array, which corresponds to an input address. In the erase mode, the row decoder is operated when a signal φ ER  is set at “H” level. A voltage V ppRW  becomes V CC  in a read operation, and V pp  (about 20V) in an erase/write operation. 
     E type n-channel MOS transistors Q n50  to Q n69  and E type p-channel MOS transistors Q p20  to Q p29  constitute a transfer gate for transferring selection gate potentials SG 1D  and SG 2D  and control gate potentials CG 1D  to CG 8D  and V USS  upon reception of an output from the row decoder. Reference symbols V USS , SG 1D , SG 2D , and CG 1D  to CG 8D  denote signals common to the respective row decoders. 
     A data erase operation in the first embodiment will be described below. FIG. 13 shows the waveforms of voltages applied to the substrate (well), a control gate CG, and a selection gate SG in the erase mode. 
     As shown in FIG. 13, the selection gate SG and non-selection gates CG′ 1  to CG′ 8  are set at “H” level in the first and second operations, whereas the selection word lines CG 1  to CG 8  are set at “M” level in the first operation, and at “L” level in the second operation. 
     As described above, in the data erase mode, in the first erase pulse applying operation, a voltage of “M” level is applied to the word lines to change the threshold value while an electric field applied to the tunnel oxide film is kept low. In the second and subsequent operations, a high electric field is applied to the tunnel oxide film to suppress a peak electric field applied to the tunnel oxide film. With this operation, the reliability of the EEPROM is improved. In FIG. 13, the voltage is raised and fallen at first and second times erasure. Voltages except for the selecting gate may be maintained. 
     A data write operation in the first embodiment will be described. A write operation is performed in accordance with the flow chart shown in FIG.  14 . 
     After the write mode is set (steps A 1  and A 2 ), data setting is performed (step A 3 ), and a write operation with respect to a memory cell is performed (step A 4 ). Thereafter, a verify read operation is performed to check whether the written data is correct (step A 5 ). If the data is correct, the write processing is completed (step A 6 ). If it is determined in step A 5  that the data is abnormal, a write operation is performed again (steps A 8 , A 7 , and A 4 ). At this time, the writing potential is variably set, as will be described later. If the data is not properly written after, e.g., 10 write operations, the flow goes to an abnormal end (steps A 8  to A 10 ). 
     Tables 2 to 5 show the relationships between SG D , SG S , and CG 1  to CG 8  and the bit line potentials in the write mode. Assume that the word line CG 8  is selected in this case. A “1” write operation includes a case wherein the data is “1” and a case wherein a “0” write operation is completed, and a voltage equal to the writing voltage at “1” write operation is applied to prevent further injection of electrons. 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Number 
                   
                   
                   
                   
                   
               
               
                   
                 Time of 
               
               
                   
                 Write 
                 First 
                 Second 
                 Third 
                 Fourth 
                 Fifth 
               
               
                   
                 Operations 
                 Time 
                 Time 
                 Time 
                 Time 
                 Time 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 (V bitH ) 
                 bit line 
                 8V 
                 8V 
                 9V 
                 9V 
                 9V 
               
               
                   
                 “1” 
               
               
                   
                 bit line 
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
               
               
                   
                 ”0” 
               
               
                 (V M ) 
                 SG D   
                 10V 
                 10V 
                 11V 
                 11V 
                 11V 
               
               
                 (V M ) 
                 CG 1  to CG 7   
                 10V 
                 10V 
                 11V 
                 11V 
                 11V 
               
               
                 (V PP ) 
                 CG 8   
                 19V 
                 20V 
                 21V 
                 21V 
                 21V 
               
               
                   
                 (selected) 
               
               
                   
                 CG S   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                 Number of 
                   
                   
                   
                   
                   
               
               
                   
                 Times of 
               
               
                   
                 Write 
                 First 
                 Second 
                 Third 
                 Fourth 
                 Fifth 
               
               
                   
                 Operations 
                 Time 
                 Time 
                 Time 
                 Time 
                 Time 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 (V bitH ) 
                 bit line 
                 8V 
                 8.5V 
                 9V 
                 9V 
                 9V 
               
               
                   
                 “1” 
               
               
                   
                 bit line 
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
               
               
                   
                 “0” 
               
               
                 (V M ) 
                 SG D   
                 10V 
                 10.5V 
                 11V 
                 11V 
                 11V 
               
               
                 (V M ) 
                 CG 1  to CG 7   
                 10V 
                 10.5V 
                 11V 
                 11V 
                 11V 
               
               
                 (V PP ) 
                 CG 8   
                 19V 
                 20V 
                 21V 
                 21V 
                 21V 
               
               
                   
                 (selected) 
               
               
                   
                 CG S   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 4 
               
               
                   
                   
               
               
                   
                 Number of 
                   
                   
                   
                   
                   
               
               
                   
                 Times of 
               
               
                   
                 Write 
                 First 
                 Second 
                 Third 
                 Fourth 
                 Fifth 
               
               
                   
                 Operations 
                 Time 
                 Time 
                 Time 
                 Time 
                 Time 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 (V bitH ) 
                 bit line 
                 9V 
                 9V 
                 9V 
                 9V 
                 9V 
               
               
                   
                 “1” 
               
               
                   
                 bit line 
                 2V 
                 1V 
                 V SS   
                 V SS   
                 V SS   
               
               
                   
                 “0” 
               
               
                 (V M ) 
                 SG D   
                 11V 
                 11V 
                 11V 
                 11V 
                 11V 
               
               
                 (V M ) 
                 CG 1  to CG 7   
                 11V 
                 11V 
                 11V 
                 11V 
                 11V 
               
               
                 (V PP ) 
                 CG 8   
                 21V 
                 21V 
                 21V 
                 21V 
                 21V 
               
               
                   
                 (selected) 
               
               
                   
                 CG S   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 5 
               
               
                   
                   
               
               
                   
                 Number of 
                   
                   
                   
                   
                   
               
               
                   
                 Times of 
               
               
                   
                 Write 
                 First 
                 Second 
                 Third 
                 Fourth 
                 Fifth 
               
               
                   
                 Operations 
                 Time 
                 Time 
                 Time 
                 Time 
                 Time 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 (V bitH ) 
                 bit line 
                 8V 
                 8V 
                 9V 
                 9V 
                 9V 
               
               
                   
                 “1” 
               
               
                   
                 bit line 
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
               
               
                   
                 “0” 
               
               
                 (V M ) 
                 SG D   
                 11V 
                 11V 
                 11V 
                 11V 
                 11V 
               
               
                 (V M ) 
                 CG 1  to CG 7   
                 11V 
                 11V 
                 11V 
                 11V 
                 11V 
               
               
                 (V PP ) 
                 CG 8   
                 19V 
                 20V 
                 21V 
                 21V 
                 21V 
               
               
                   
                 (selected) 
               
               
                   
                 CG S   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
                 V SS   
               
               
                   
               
             
          
         
       
     
     Table 2 shows a case wherein the writing voltage is increased to two levels from 19 V to 20 V and 21 V. In this case, when the writing voltage is increased by 2 V, the bit line potential and the selection gate SG D  potential are increased by 1 V. 
     Table 3 shows a case wherein as the writing voltage is increased, the bit line potential and the selection gate potential V M  are increased. 
     Each of the above voltages is not limited to the value in the embodiment but may be properly changed. For example, in each of the above cases, the voltage is increased 1 V at a time. However, this voltage may be increased 0.5 V or 2 V at a time. In addition, the voltage need not be increased regularly. For example, the increase may be gradually decreased in the following manner: 19 V-20 V-20.5 V-20.7 V. In contrast to this, the increase may be gradually increased. 
     In the first embodiment, the voltage is changed for each operation. However, for example, the voltage may be changed for every other operation in the following manner: 19 V-19 V-20 V-20 V-21 V-21 V. Alternatively, the voltage may be increased for each of set operations in the following manner: 19 V-20V-20 V-21 V-21 V-21 V. Similarly, a high degree of freedom is allowed in methods of increasing bit line potentials V bitH  and V M . As is apparent, the two potentials may be fixed if there is a sufficient voltage margin for write errors. 
     The timings of increasing the potentials need not is coincide with the timing of increasing the writing voltage, as in the above embodiment, but may be independently controlled. In the above embodiment, V PP  is gradually increased. However, in order to increase the potential difference between the control gate and the source-drain path, the bit line potential may be decreased while the writing voltage is fixed. As shown in Table 4, the bit line potential may be decreased stepwise. 
     Both the potentials V bitH  and V M  need not be increased. For example, only the potential V bitH  may be increased while the potential V M  is fixed (Table 5). In this case, however, the increased potential V bitH  must be transferred to a selected memory cell. The potentials V bitH  and V M  may be equal to each other. In this case, since a voltage drop by the threshold value occurs at the drain-side selection gate, a voltage corresponding to the drop by the threshold value is transferred to the bit line. In contrast to this, the potential V M  applied to the selection gate line SGD may differ from the potential V M  applied to a non-selected memory cell. 
     A write verify scheme will be described with reference to the sense amplifier/data latch circuit (FF) shown in FIG.  15 . 
     As shown in FIG. 15, the sense amplifier/data latch circuit (FF) is constituted by a CMOS flip-flop. The first output of this circuit is connected to a bit line BLi via an E type n-channel MOS transistor Q n7  which is controlled by a signal φ F . E type n-channel MOS transistors Q n8  and Q n9 , which are respectively controlled by the first output of the flip-flop FF and a signal φ V , are connected in series between the bit line BLi and V CC . An E type p-channel MOS transistor Q p5  for precharging the bit line and an E type n-channel MOS transistor Q n10  for discharging the bit line are connected to the bit line. A sense line V DTC  is connected to V SS  via a detection transistor Q n11  for receiving the second output from the flip-flop FF. 
     In the write mode, when a “1” write operation is to be performed, the bit-line-side node of the flip-flop FF is latched at “H” level, and an intermediate potential is transferred to the bit line. When a “0” write operation is to be performed, the bit-line-side node of the flip-flop FF is latched at “L” level, and the potential V SS  is transferred to the bit line. 
     In a write verify operation, while the transistor Q n7  is kept on, a precharge signal φ PB  is set at “L” level to precharge the bit line to V CC . In this state, write data is held in the flip-flop FF. Thereafter, the selection and control gates are driven. In this case, if the cell data is of a D type, the bit line discharged to V SS . If the cell data is of an E type, the bit line is held at “V CC ” level. After the selection and control gates are reset, and a verify signal φ V  is set at “H” level. As a result, the bit line in which data “1” is held is charged to V CC -V th . Subsequently, a CMOS inverter constituting the flip-flop FF is inactivated, and the transistor Q n7  is turned on. With this operation, the potential of the bit line is sensed, latched, and used as data to be written again. 
     Each bit line in which “1” is written is latched at “H” level, and each bit line in which “0” is written and for which a write operation is sufficiently performed is latched at “H” level. In addition, each bit line in which “0” is written and for which a write operation is not sufficiently performed is latched at “L” level. The write operation is continued until the bit-line-side nodes of all the flip-flops FF are latched at “H” 0  level. 
     Written states are detected in the following manner. 
     The detection transistors of all the flip-flops FF are connected to a sense line SL. The sense line V DTC  is connected to a p-channel transistor Q PK . After a latch operation, the transistor Q PK  is activated for a predetermined period of time. If write processing with respect to all the bits has been completed at this time, all the detection transistors are in an OFF state. Therefore, the sense line V DTC  is charged to V CC . If cells which have undergone an insufficient write operation are left, since the detection transistors corresponding to the bit lines of these cells are in an ON state, the potential of the sense line V DTC  decreases to V SS . Therefore, by detecting the potential of the sense line V DTC  the completion of the write operation can be detected at once (unlike the case wherein all the bits are read out by changing the address). If the write processing is not completed, a write operation is performed again. 
     FIG. 16 shows a limiter circuit for realizing the above write operation. In this case, a reverse-biased diode D is connected to the output of a step-up circuit  29  via a p-type transistor M p . The breakdown voltage of the diode D is set to be 9.5 V per step. 
     Assume that signals φ 1  and φ 2  are set at V SS  in the first write operation. In this case, since nodes N 1  and N 3  are short-circuited via p-type transistors M p3  and M p4 , 19 V is output as V pp . In the second write operation, the signals φ 1  and φ 2  are respectively set at V pp  and V SS . In this case, although a node N 2  and the node N 3  are short-circuited, the voltage between the nodes N 1  and N 2  drops by a threshold value V th  of a p-type transistor M p1 . Therefore, if the threshold value of this p-type transistor is 1 V, the output V pp  is 20 V. Similarly, in the third write operation, both the signals φ 1  and φ 2  are set at V pp . Consequently, 21 V is output as the output V pp  in accordance with a two-step voltage drop corresponding to the threshold values V th . 
     A desired voltage can be obtained by controlling the limiter circuit upon detection of the number of times of write operations in the above-described manner. 
     The circuit shown in FIG. 16 uses the two p-type transistors. However, this arrangement may be variously modified. For example, transistors having different threshold values may be arranged to change the increased voltage, or three or more transistors having the same threshold value may be arranged to be divided into two transistors and one transistor. In addition, p- and n-type transistors may be coupled. A step-up circuit for V M  and V bitH  may be formed by a similar arrangement. 
     A write/verity cycle may be automatically controlled within a chip or may be externally controlled. 
     When the cycle is to be automatically controlled within the chip, a counter circuit for storing the number of times of a write operation is arranged, and the set voltage of a set-up circuit limiter is switched in accordance with an output signal from the counter circuit or the like. A ready/busy pin is set in a busy state during a write/verify cycle, and completion of the write operation is confirmed by a verify read operation. Alternatively, if the write processing is not completed after the write/verify operation is repeated a predetermined number of times, the ready/busy pin is restored to a ready state, and, for example, information indicating whether the verify operation is completed is output to a specific I/O pin. As is apparent, when or after the ready/busy pin is restored to the ready state, the counter circuit is reset at a predetermined timing by, for example, inputting a reset signal. 
     When the write/verify cycle is to be controlled outside the chip, a data input command, a write command, a verify command, and the like are prepared. When a write operation is completed, a verify command is input. If the write operation is not completed, a write command is input again. At this time, a CPU or the like outside the chip stores the number of times of write operations. In such a control operation, for example, three types of write commands are prepared, to which output voltages from the step-up circuit are caused to correspond. With this arrangement, the writing voltage can be controlled in accordance with the number of times of write operations. 
     With this write verify operation, the following effects can be obtained. 
     Since the writing voltage at the first operation is set to be lower than that in the conventional system, even if the threshold value of the limiter varies in the high-voltage direction, the threshold value does not exceed the upper limit of the threshold value distribution, thus facilitating the process control of the limiter. The number of times of verify operations can be reduced by gradually increasing the writing potential. This shortens the writing time. In addition, since the writing potential at the first operation in which the highest electric field is applied to the tunnel oxide film is set to be low, a deterioration in the tunnel oxide film can be prevented, and an improvement in the reliability of each memory cell can be realized. 
     Another write verify operation will be described below. 
     A memory cell array block in which data is to be written is selected. The data in the memory cells of all the NAND cells in the selected block are erased before a data write operation with respect to the block is performed. In a data erase operation, 0 V is applied to all the control gate lines (word lines) CG. At this time, the erase potential V E  is applied to the selection gate lines SG S  and SG D , the bit and source lines, and the p-type substrate (or the p-type well) on which the memory cell array is formed. Similarly, the erase potential is applied to the control gate lines of the non-selected blocks. By keeping this biased state for, e.g., 10 ms, electrons are discharged from the floating gates of all the memory cells in the selected blocks, and the threshold value of each memory cell is changed in the negative-value direction. 
     An erase verify operation is then performed to check whether the threshold value of each erased memory cell has become a sufficiently negative value. The control gates of the memory cells in all the selected NAND cells are set at 0 V. The selection gates SG S  and SG D  are set at, e.g., 5 V, and a read potential of, e.g., 1.5 V is applied to the bit lines. The source lines and the p-type substrate (or the p-type well) are set at 0 V. At this time, the time during which the selection gates SG S  and SG D  are kept at 5 V is set such that data “0” can be read out if the threshold value of each erased memory cell becomes a negative value to a certain degree. If data “0” cannot be read out within this set time, a data erase operation is performed again, and a verify operation is repeated until the condition is satisfied. 
     Subsequently, a data write operation is performed. In this data write operation, data corresponding to the number of bits constituting a NAND cell, e.g., data corresponding to eight words (if one NAND cell is constituted by eight bits), is latched in a data latch circuit. The bit line potential is controlled in accordance with this data to write “0” or “1”. At this time, the writing potential V W  is applied to the selected control gate line, and the intermediate potential V M  is applied to the non-selected control gate lines. A voltage of 0 V is applied to the bit line BL when a “1” write operation is performed. The intermediate potential V M  is applied to the bit line BL when a “0” write operation is performed. In this write operation, the intermediate potential V M  is applied to the selection gate SG D , and 0 V is applied to the selection gate SG S  and the p-type substrate (or the p-type well). 
     By keeping the biased state of a data write operation for, e.g., 1 ms, the threshold value of each memory cell in which “1” is written shifts in the positive-value direction, and the threshold value of each memory cell in which “0” is written is fixed to a negative value. 
     Subsequently, a write verify operation is performed. In the first embodiment, a write verify potential V VER  is used to check whether the threshold value of each memory cell in which data “1” is written is a desired value or more. This threshold value is determined in consideration of the data holding characteristics of each memory cell and is set to be, e.g., 1.5 V. 
     More specifically, the write verify potential V VER  is applied to the selected control gate line. V CC  is applied to the remaining control gate lines. Both the selection gates SG S  and SG D  simultaneously selected at this time are set at V CC . A read potential, e.g., 1.5 V, is applied to the bit line, and the source line is set at 0 V. With this operation, if the threshold value of a selected memory cell in which “1” is written exceeds the write verify potential, the selected memory cell is rendered nonconductive, and data “1” is read out. If a “1” write operation is not sufficiently performed, and the threshold value of the selected memory cell has not reached the write verify potential, the selected memory cell is rendered conductive, and data “0” is read out. Therefore, a “1” write operation and stress relaxation operation  2  are repeated. A verify operation is repeated until the threshold value of each selected memory cell becomes the write verify potential or more. 
     A write operation is performed by a plurality of pulses repeatedly applied until a desired cell Tr threshold value is obtained. 
     FIG. 17 shows the concept of a circuit for applying a writing potential. 
     A signal is supplied from a write number counter  30  in a program controller to a ring oscillator  31  for supplying a signal to a step-up circuit  32 . In response to this signal, the period of the ring oscillator  31  is delayed with respect to only the initial writing potential pulse to delay the rise time of the pulse relative to the second and subsequent pulses. 
     FIG. 18 shows a circuit for variably changing the period of the ring oscillator  31 . An “L”-level potential (e.g., 0 V) is normally applied to a terminal V select . However, an “H”-level potential (e.g., 5 V) is applied to the terminal V select  to prolong the period. If the above circuit for controlling the pulse rise speed is added to a conventional circuit, the rise of the initial pulse can be set to be longer than that of the second and subsequent pulses. With this arrangement, a deterioration in the gate insulating film can be suppressed more than in the conventional arrangement. 
     FIG. 19A shows the structure of a non-volatile memory cell. The same reference numerals in FIG. 19A denote the same parts as in FIGS. 10A and 10B. 
     A floating gate (charge storage layer)  14  and a control gate  16  are stacked on a p-type well  11 B on an n-type silicon substrate  11 A. The p-type well  11 B and the floating gate  14  are insulated from each other by a tunnel oxide film  13 . The floating gate  14  and the control gate  16  are insulated from each other by a gate insulating film  15 . An n-type diffusion layer  19  forms the source and drain of a memory cell transistor. 
     The capacitances between the floating gate  14  and the control gate  16 , and between the floating gate  14  and the p-type well  11 B are respectively denoted by reference symbols C cg  and C ox  in FIG.  19 B. The capacitor C ox  includes the capacitance between the floating gate  14  and the n-type diffusion layers  19 . The memory cell stores data in accordance with the threshold value of the capacitance. The threshold value is determined by the amount of charges stored in the floating gate  14 . The amount of charges stored in the floating gate  14  is changed by a tunnel current passing through the gate oxide film  13 . 
     When the control gate  16  is set at a sufficiently higher potential than those of the p-type well  11 B and the n-type diffusion layers  19 , electrons are injected into the floating gate  14  via the gate oxide film  13 . As a result, the threshold value increases. In contrast to this, when the p-type well  11 B and the n-type diffusion layers  19  are set at a higher potential than that of the control gate  16 , electrons are discharged from the floating gate  14  via the gate oxide film  13 . As a result, the threshold value decreases. 
     FIGS. 20A to  20 D show an electron injection method according to the second embodiment of the present invention when “0” data is programmed to the selected cell. FIG. 20A to  20 D respectively show a control gate voltage V cg , a floating gate potential V fg , a tunnel current I tunnel , and a threshold value V th  of a memory cell. 
     A high potential V pp  is applied to a control gate, and a verify operation is performed upon application of a V pp  pulse. The initial V pp  pulse voltage is set to be a voltage V cgo  and is gradually increased at a rate of Δ V pp . The pulse width is a predetermined time Δ t. The values Δ t and Δ V pp  are set such that a maximum change amount Δ V th  of the threshold value of the memory cell in one electron injecting operation becomes equal to the value Δ V pp . In practice, if the change amount Δ V th  of the threshold value of the memory cell in one electron injecting operation is set to be equal to the value Δ V pp  when the value Δ V pp  is sufficiently high, and a sufficient tunnel current flows, electrons injected in one electron injecting operation cancel an increase in voltage applied to the tunnel oxide film owing to the increase Δ V pp  of the high potential V pp   in the next electron injection operation. Subsequently, the threshold value change amount Δ V th  becomes the predetermined value Δ V pp  in each operation. 
     If the initial pulse voltage V cgo  is set to be sufficiently low, the threshold value of the easiest memory cell to inject electrons thereinto can be reliably controlled to be lower than an upper limit V th-max  of the threshold value. As a result, a wide V pp  margin can be obtained. At the same time, V th-max  −V th-min =Δ V pp  can be set. In the hardest memory cell to inject electrons thereinto, when the high potential V pp  is increased, the threshold value quickly reaches the lower limit V th-min . When the threshold value of each memory cell is checked by a verify operation to detect that the threshold value has reached the lower limit V th-lim , the electron injecting operation for each memory cell is completed. 
     In the second embodiment, since the high potential V pp  is increased in accordance with an increase in the amount of electrons injected, a maximum value V fg-max  of the floating gate potential V fg  is suppressed, and a deterioration in the tunnel oxide film is also suppressed. In practice, the threshold value change amount Δ V th  becomes the predetermined value Δ V pp  in each electron injection operation, and the floating gate potential V fg  is applied in the same manner in each operation. As a result, the maximum value V fg-max  is suppressed. 
     FIGS. 21A to  21 D show an electron injection scheme according to the third embodiment of the present invention when “0” data is programmed to the selected cell. The third embodiment is basically the same as the second embodiment except that a high speed operation is realized by grouping several pulses in the initial electron injection period and omitting a verify operation. The third embodiment is effective in performing electron injection at high speed in a case wherein the threshold value of each memory cell does not reach the lower limit V th-min  upon application of several pulses in the initial electron injection period in the second embodiment. 
     FIGS. 22A and 22B show changes in the threshold values of the easiest memory cell to inject electrons thereinto, a typical memory cell, and the hardest memory cell to inject electrons thereinto over time in the third embodiment when “0” data is programmed to the selected cell. In order to prevent a deterioration in the tunnel oxide film, the lower the maximum value V fg-max  becomes, the better the effect is. For this reason, as shown in FIGS. 23A to  23 D, the V pp  pulse width Δ t and the V pp  increase rate Δ V pp  may be set to be small. In this case, however, the number of times of verify operations increases, and a long period of time is required for electron injection. In addition, the width of the threshold value distribution becomes unnecessarily small, resulting in a wasteful operation. 
     FIGS. 24A to  24 D are views showing an electron injection scheme according to the fourth embodiment of the present invention when “0” data is programmed to the selected cell. 
     In the fourth embodiment, the V pp  pulses used in the third embodiment are grouped into several sets of pulses. In the initial period, as described with reference to FIGS. 21A to  21 D and  22 A and  22 B, a larger number of pulses are grouped. According to the fourth embodiment, a floating gate potential V fg  becomes almost constant, and a deterioration in the tunnel oxide film can be suppressed more than in the schemes described with reference to FIGS. 21A to  21 D and  22 A and  22 B. Similarly, V th-max −V th-min =Δ V pp  is set, and electron injection can be performed at high speed. 
     FIGS. 25A to  25 D are views showing an electron injection method according to the fifth embodiment of the present invention. 
     The fifth embodiment of the present invention is equivalent to the fourth embodiment except that Δ t 0 →0 and Δ V pp0 →0 when “0” data is programmed to the selected cell. Each V pp  pulse has a predetermined value dV pp /dt and continuously increases at a rate of Δ V pp . In the fifth embodiment, the floating gate potential during an electron injecting operation can be set to be almost constant, and a deterioration in the tunnel oxide film can be minimized. 
     During an electron injecting operation with respect to the above NMOS memory cell, if V pp  is sufficiently high, the channel portion is inverted, and the drain, source, and channel portions are set at the same potential. Therefore, the method shown in FIGS. 25A to  25 D is equivalent to the methods respectively shown in FIGS. 26A and 26B and FIGS. 27A and 27B. 
     FIGS. 26A and 26B show the first modification of the fifth embodiment, in which a control gate voltage V cg  is set to be constant, and a drain voltage V d  is gradually decreased. With this operation, the same effects as those of the fifth embodiment can be obtained. If an initial value V d0  of a voltage applied to the drain is higher than the breakdown voltage in the first modification, the second modification shown in FIGS. 27A and 27B may be used. More specifically, an initial value V d0  of the drain voltage is decreased, and an initial value V cgo  of the control gate voltage is also decreased. When a drain voltage V d  is decreased to 0 V, a control gate voltage V cg  is increased by V d0 , and V d  is increased from V d0 . With this scheme, the same effects as those of the fifth embodiment FIGS. 25A to  25 D can be obtained. 
     In the scheme shown in FIGS. 25A to  27 B, dV pp /dt is constant value. Even if this is difficult to realize in practice, V pp  is changed at a rate of Δ V pp  for a time Δ t while dV pp /dt&gt;=0 is kept. In addition, the width of the threshold value distribution after electron injection is set to be Δ V pp . With this operation, an effect similar to that obtained with dV pp /dt constant value can be obtained. 
     As is apparent, the voltage V pp  has its upper limit, which is determined by a breakdown voltage V break  of the device. When the voltage V pp  reaches the breakdown voltage V break , the voltage V pp  cannot be increased any more. Even in this case, the effects of the present invention can be obtained until the voltage V pp  reaches the breakdown voltage V break  Injection of electrons has been described above with reference to FIGS. 20A to  27 B. However, an electron discharging operation can be performed in the same manner by inverting the polarity of the control gate with respect to the p-type well. 
     FIG. 28 shows a memory array of NAND-type EEPROMs according to the sixth embodiment of the present invention. 
     Eight memory cells M 1  to M 8  are connected in series such that the respective adjacent cells share sources and drains, thus constituting one NAND cell. One end of the NAND cell is connected to a bit line BL via a first selection transistor S 1 . The other terminal of the NAND cell is connected to a common source line VS via a second selection transistor S 2 . Selection gates SG 1  and SG 2  are the gate electrodes of the selection transistors S 1  and S 2 . Control gates CG 1  to CG 8  are the gate electrodes of the memory cells. A page constituted by a memory cell group sharing a control gate CG, and a block is constituted by a NAND cell group sharing a selection gate SG. Each memory cell has a structure similar to that shown in FIG. 19, and the memory cell array is formed in a common p-type well. 
     Erase, write, read, and read verify operations with respect to each NAND-type EEPROM are performed as follows. 
     An erase operation is performed in units of blocks. The p-type well is set at a high voltage (about 20 V), and the control gates GC 1  to CG 8  in a selected block are set at 0 V. The control gates in the non-selected blocks and all the selection gates are set at V pp . Electrons in the floating gates are discharged to the p-type well, and the threshold value of each memory cell becomes a negative value. 
     After the erase operation, a data write operation is performed in units of pages, starting from the page located farthest from the bit line. In an write operation, V pp  (about 10 to 20 V) is applied to the control gate (e.g., CG 4 ) of a selected page, and an intermediate potential V M  (about 10 V) is applied to the control gates CG 1  to CG 3  and CG 5  to CG 8  of the non-selected pages and to the first selection gate SG 1 . A voltage of 0 V is applied to the bit line BL when a “0” write operation is performed. The voltage V M  is applied to the bit line BL when a “1” write operation is performed. The second selection gate SG 2  is set at 0 V. 
     In the “0” write operation, owing to the potential difference between the selected selection gate GC 4  and the channel, electrons are injected from the channel into the floating gate by a tunnel current. As a result, the threshold value changes in the positive-value direction. In the “1” write operation, since the potential of the channel is set at V M , the electric field applied to the tunnel oxide film is weak, and no effective injection of electrons into the floating gate occurs. Therefore, the threshold voltage undergoes no change. 
     After the write operation, a verify operation is performed to check the threshold value of each memory cell. A verify potential (about 0.5 V) is applied to a selected control gate (e.g., CG 4 ), and the non-selected control gates CG 1  to CG 3  and CG 5  to CG 8  and the first and second selection gates SG 1  and SG 2  are set at power supply voltage V CC . If the bit line BL and the source line are electrically connected to each other after a “0” write operation, it indicates that the threshold value of the selected memory cell is lower than the verify potential, and the “0” write operation is insufficient. Therefore, a “1” write operation is executed again when a write operation is performed again. Otherwise, it is determined that the threshold value is higher than the verify potential; the “0” write operation is sufficient; and injection of electrons into the floating gate need not be performed any more. Therefore, a “1” write operation is executed when a write operation is performed again. After the “1” write operation, a “1” write operation is executed again regardless of the threshold value of the memory cell when a write operation is performed again. 
     Since data are written by repeating write and verify operations, the writing time is adjusted for each memory cell. When it is detected that the data are sufficiently written in all the memory cells of one page, the data write processing corresponding to one page is completed. 
     In a read operation, a selected control gate (e.g., CG 4 ) is set at 0 V, and the non-selected control gates CG 1  to CG 3  and CG 5  to CG 8  and the first and second selection gates SG 1  and SG 2  are set at the power supply voltage V CC . If the potential of the precharged bit line BL decreases, the threshold value of the memory cell is lower than 0 V, and the data is “1”. If the potential of the bit line BL is held, the threshold value of the memory cell is higher than 0 V, and the data is “0”. In a read operation, the threshold value of each memory cell must be lower than the power supply voltage V CC . 
     A method of applying a writing voltage V pp  to a selected control gate CG of a NAND-type EEPROM in a write operation will be described below. 
     FIG. 29 shows the arrangement of a circuit for driving control gates. 
     This circuit includes transfer circuits  22 A selectively transferring outputs from control gate drivers  23 B, a first selecting gate driver  23 A, and a second selecting gate driver  23 C to the respective control and selection gates. A group of ten transfer circuits  22 A corresponding to a block of a memory cell array  21  is selected by block selection signals φ wi  and φ wBi . A step-up circuit  29  generates voltages V pp  and V M  required for write and erase operations from a power supply voltage V CC , and applies them to the control gate drivers  23 B, the first selecting gate driver  23 A, and the second selecting gate driver  23 C. 
     FIG. 30 shows the arrangements of the transfer circuits  22 A of the control gates CG 4 , the control gate driver  23 B, and the step-up circuit  29  in FIG. 29 in more detail. Each transfer circuit  22 A comprises a CMOS transfer circuit constituted by n- and p-channel MOS transistors Q n1  and Q p1 , and a reset circuit constituted by an n-channel MOS transistor Q n2 . When the signals φ wi  and φ wBi  are set at “H” level and “L” level, respectively, a voltage at a node N 1  is transferred to the control gate. When the signals φ wi  and φ wBi  are set at “L” level and “H” level, respectively, the control gate is grounded. The step-up circuit  29  is constituted by a V M  step-up circuit  41  and a V pp  step-up circuit  42 . The control gate driver  23 B is constituted by a first switching circuit  43 , a second switching circuit  44 , and a third switching circuit  45 . 
     The first switching circuit  43  performs control as to whether the output V M  from the V M  step-up circuit  41  is connected to the node N 1 . The second switching circuit  44  performs control as to whether the output V pp  from the V pp  step-up circuit  42  is connected to the node N 1 . The voltage transferred to the node N 1  is V pp −Δ V pp . The third switching circuit  45  performs control as to whether the output V pp  from the V pp  step-up circuit  42  is connected to the node N 1 . In this case, the amount of current to be supplied when the output V pp  is transferred to the node N 1  is adjusted to control an increase rate dV pp /dt of the potential of the node N 1 . 
     FIG. 31 shows the detailed arrangement of the control gate driver  23 B. 
     The first switching circuit  43  includes p-channel MOS transistors Q p1  to Q p4 , n-channel MOS transistors Q n3  and Q n4 , an n-channel MOS transistor Q D1 , and an inverter I 1 . A circuit constituted by the MOS transistors Q p2 , Q p3 , Q n3 , and Q n4  and the inverter I 1  serves to convert a signal φ 1  which has an amplitude among 0 V and V CC  into a signal which has an amplitude among 0 V and V pp . When the signal φ 1  is set at “L” level, the gates of the transistors Q p4  and Q D1  are set at V pp  ad 0 V, respectively. As a result, V M  is disconnected from the node N 1 . When the signal φ 1  is set at “H” level, the gates of the transistors Q p4  and Q D1  are set at 0 V and V pp , respectively. As a result, V M  is connected to the node N 1 . The transistor Q D1  prevents transfer of V pp  to the transistor Q p4  when the node N 1  is set at V pp . 
     The second switching circuit  44  includes p-channel MOS transistors Q p5  to Q p8  n-channel MOS transistors Q n5  and Q n6 , and an inverter I 2 . When a signal φ 2  is set at “L” level, the gate of the transistor Q p7  is set at V pp . As a result, V pp  is disconnected from the node N 1 . When the signal φ 2  is set at “H” level, the gate of the transistor Q p7  is set at 0 V. As a result, V pp  is connected to the node N 1 , and a voltage lower than V pp  by the threshold value of the transistor Q p8  is transferred to the node N 1 . 
     The third switching circuit  45  includes p-channel MOS transistors Q p9  to Q p11 , n-channel MOS transistors Q n7  and Q n8 , and inverter I 3 , and a current control circuit  46 . When a signal φ 3  is set at “L” level, the gate of the transistor Q p11  is set at V pp . As a result, V pp  is disconnected from the node N 1 . When the signal φ 3  is set at “H” level, the gate of the transistor Q p11  is set at 0 V. As a result, V pp  is connected to the node N 1 , and V pp  is transferred to the node N 1  while dV pp /dt is controlled by the current control circuit  46 . 
     A p-channel MOS transistor Q p12 , an n-channel MOS transistor Q n9 , and an n-channel D type MOS transistor Q D2  constitute a circuit for setting the node N 1  at V GH  or V CC . When a signal φ 4  is set at “H” level, the node N 1  is set at V GH . When the signal φ 4  is set at “L” level, the node N 1  is set at V CC . The voltage V GH  is normally 0 V and is set to be a verify voltage V VRFY  (˜0.5 V) in a verify operation. The transistor Q D2  prevents transfer of V M  or V pp  to the transistor Q p12  when a signal φ 5  is set at “L” level, and V M  or V pp  is applied to the node N 1 . 
     Each of FIGS. 32A and 32B shows the detailed arrangement of the current control circuit  46  in FIG.  31 . 
     The current control circuit  46  in FIG. 32A includes p-channel MOS transistors Q p13  to Q p15  and n-channel D type MOS transistors Q D3  and Q D4 . A signal φ 3B  is an inverted signal of the signal φ 3  in FIG.  31 . When the signals φ 3  and φ 3B  are respectively set at “H” level and “L” level, and a node N 2  is set at V pp , the gate of the transistor Q p15  is set at V pp  −2V tP  (V tP  is the threshold value of the p-channel MOS transistor). As a result, a current flowing from a node N 3  to the node N 1  is controlled by the transistor Q p15 . 
     The current control circuit  46  in FIG. 32B includes p-channel MOS transistors Q p16  and Q p17 , an n-channel MOS transistor Q n10 , a capacitor C 1 , and a resistor R 1 . When the signal φ 3  is set at “H” level, and a node N 2  is at V pp , the gate of the transistor Q p16  is controlled by the capacitor C 1  and the resistor R 1 , and the gate voltage changes from V pp  to 0 V. As a result, a current from a node N 3  to a node N 1  is controlled by the transistor Q p16 . 
     FIG. 33 is a timing chart showing a write operation with respect to the EEPROM having the above arrangement. Referring to FIG. 33, when the control gate CG 4  is selected, the voltages V M  and V pp  are boosted from the power supply voltage V CC  by the V M  step-up circuits  41  and  42 . The voltage V pp  is increased from V pp1  by V tP  every time a write/verify operation is repeated. The signals φ wi  and φ wBi  shown in FIG. 30 are respectively set at V pp  and 0 V in a selected block. 
     In a write operation, when the signal φ 4  is set at “L” level, the node N 1  is set at V CC . As a result, all the control gates CG 1  to CG 8  of the selected block are set at V CC . At the same time, the selection gate SG 1  of the selected block is also set at V CC . The bit line BL is set at V CC  when a “1” write operation is to be performed. During the write operation, the selection gate SG 2  is kept at 0 V. When the signal φ 1  is set at “H” level, the control gates CG 1  to CG 8 , the selection gate SG 1 , and the bit line BL in which “1” is written are set at V M . When the signal φ 3  is set at “H” level, the voltage of the selected control gate CG 4  is increased from V M  to V pp1  in a time Δ t 0 . The non-selected control gates CG 1  to CG 3  and CG 5  to CG 8 , the selection gate SG 1 , and the bit line BL in which “1” is written are kept at V M . The signals φ 1 , φ 2 , φ 3 , and φ 4  associated with the non-selected control gates are indicated by the dotted lines in FIG.  20 . 
     When the signal φ 4  is set at “H” level, all the control gates CG 1  to CG 8  are set at 0 V. At this time, the selection gate SG 1  is also reset to 0 V, and the bit line BL is reset to 0 V afterward. 
     A verify operation is continuously performed after the above operation. The selected control gate CG 4  is set at the verify potential V VRFY . The non-selected control gates CG 1  to CG 3  and CG 5  to CG 8  are set at V CC  when the signal φ 4  is set at “L” level. The selection gates SG 1  and SG 2  are also set at V CC . 
     If it is detected that the threshold value of each memory cell in which “0” is to be written exceeds the verify potential V VRFY , a “1” write operation is performed when a write operation is performed again, thus preventing an excessive “0” write operation. If it is detected that the threshold value of each memory cell in which “0” is to be written does not exceed the verify potential V VRFY , a “0” write operation is performed again when a write operation is performed again. When a write operation is performed again, a “1” write operation is performed again with respect to each memory cell in which “1” is to be written. 
     In the second and subsequent write operations, after the selected control gate CG 4  is charged to V M , the signal φ 2  is output to quickly charge the selected control gate CG 4  to the maximum selected control gate voltage in the previous write operation. In addition, the signal φ 3  is set at “H” level, so that the selected control gate voltage is controlled/increased by V tP  in the time Δ t. For example, in the second write operation, the voltage is controlled/increased from V pp1  to V pp2  (V pp2 =V pp1 +V tP ). 
     The value (V pp1 −V M )/Δ t 0  in the first write operation is set to be almost equal to the value V tP /Δ t in the second and subsequent write operations. These values are set such that the threshold value of the fastest memory cell to write “0” therein is set to be lower than the maximum value of a threshold value distribution, on which the threshold value after the “0” operation should converge, in the first write operation, and the threshold value of each memory cell in which “0” is to be written shifts at a rate of Δ V pp  (ΔV pp  is the increase rate of V pp , which is V tP  in this case) in the second and subsequent write operations (FIG.  34 ). Therefore, the width of the threshold value distribution after “0” write operation becomes Δ V pp  (V tP  in this case). 
     The data write operation is ended when the above write and verify operations are repeated, and the threshold values of the memory cells in which “0” is to be written are detected to exceed V VRFY . 
     FIGS. 35 and 36 show another embodiment of the control gate driver  23 B. This driver includes first and second first V pp  step-up circuits  47  and  48  for generating outputs respectively denoted by reference symbols V ppA  and V ppB . A fourth switching circuit  49  performs control as to whether the output V ppA  from the first V pp  step-up circuit  47  is connected to a node N 1 . 
     FIG. 37 is a timing chart showing a write operation. 
     The outputs V ppA  and V ppB  are set to be the same voltage V pp1  in the first write operation; and V ppB =V ppA +Δ V pp  in the second and subsequent write operations. Voltages other than V ppA  and V ppB  are the same as those shown in FIG.  20 . In this embodiment, setting of Δ V pp  is easier than that in the embodiment shown in FIGS. 30 and 31. 
     FIGS. 38A and 38B show an electron injection scheme according to the eighth embodiment of the present invention. Three states (data “0”, “1”, and “2”) are stored in one memory cell. Although the V pp  pulse waveforms are the same as those shown in FIGS. 25A to  25 D, the voltage applied to a memory cell in which “2” is written is different from the voltage applied a memory cell in which “1” is written by Δ V ppB . In a verify operation, of all the memory cells in which “2” is to be written, memory cells whose threshold values have not reached a desired threshold value (V VRFY2 ) yet are detected. In addition, of all the memory cells in which “1” is to be written, memory cells whose threshold values have not reached a desired threshold value (V VRFY1 ) yet are detected. With respect to only these memories, “2” and “1” write operations are respectively performed again. At this time, dV pp2 /dt=dt=dV pp1 /dt=Δ V ppA  is set, and Δ V ppA  is made equal to a threshold value change amount dV th /dt. 
     With this operation, a threshold value distribution Δ V th  after the “2” and “1” write operations becomes Δ V ppA . The value Δ V ppB  is made equal to the value obtained by adding the width Δ V th  of the threshold value distribution to a threshold value margin Δ V margin  between the threshold value distributions obtained after “2” and “1” write operations (Δ V ppB =Δ V th +Δ V margin  or Δ V ppB =V VRFY2 −V VRFY1 ). As a result, “2” and “1” write operations are independently and parallelly performed to realize a high-speed read operation. As is apparent, the maximum voltage applied to the tunnel oxide film of each memory cell is minimized. 
     For independent, parallel processing of “2” and “1” write operations and a high-speed write operation, it is effective to set a difference between the voltage applied to a memory cell in which “2” is written and the voltage applied to a memory cell in which “1” is written by Δ V ppB  regardless of V pp  pulse waveforms. 
     According to the gist of the above description, the present invention can be equally applied to multivalue (quaternary or more) storage. The electron injection scheme has been described with reference to FIGS. 38A and 38B. However, the present invention can be equally applied to an electron discharge scheme by inverting the polarity of a control gate relative to a p-type well. 
     The present invention is basically characterized in that an increase in the intensity of an electric field applied to each oxide film portion in which electrons (holes) move under the floating gate owing to the potential V pp  which is gradually increased is canceled by a change in the potential of the floating gate owing to electron (hole) injection or discharge. Therefore, according to the gist of the above description, in addition to the scheme of injecting or discharging electrons (holes) by using a tunnel current flowing via the entire channel surface as in the above embodiments, the present invention can be applied to other schemes to obtain the same effects, e.g., a scheme of performing electron injection or discharge by using a tunnel current flowing between a drain or a source and a floating gate and a scheme of using hot electrons or hot holes.