Abstract:
Charge pump circuit. A charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit that outputs a control voltage. The charge pump circuit also comprises a replica circuit that is coupled to the charge pump core circuit, wherein the replica circuit receives the control voltage and produces one or more bias signals that are coupled to the charge pump core circuit to minimize the difference between charge up and charge down currents generated by the charge pump core circuit.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of priority from a pending U.S. Provisional Patent Application entitled “IMPROVED CHARGE PUMP CIRCUIT” Ser. No. 60/405,669 filed on Aug. 24, 2002, the disclosure of which is incorporated by reference herein in its entirety for all purposes. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to phase-locked loop systems, and more particularly, to phase-locked loop systems that utilize charge pump circuits. 
     BACKGROUND OF THE INVENTION 
     Phase-locked loops (PLL) find widespread use in frequency synthesizers, clock recovery circuits, phase modulators, and frequency demodulators. Generally, a PLL consists of a voltage-controlled oscillator (VCO), counter, phase/frequency detector (P/FD), charge pump (CP), and RC integration filter. 
     The phase-locked loop relies on feedback to drive the frequency difference and phase offset between a reference signal and the output of the counter towards zero. Its operation depends on the circuits that comprise the system; and as such, variations in circuit parameters alter the response of the system, lower the stability of the feedback loop, and introduce distortion. The charge pump and integration filter are circuits that are especially sensitive. 
     It is therefore desirable to improve the performance of the charge pump so that the PLL can better adapt to parameter changes. 
     SUMMARY OF THE INVENTION 
     In one or more embodiments, a PLL system is provided that includes an improved charge pump (CP) circuit that operates linearly and compensates for parameter variations. The improved CP circuit produces fast and symmetric current pulses with reduced ringing and overshoot. 
     In one embodiment, a charge pump circuit is provided that comprises a replica circuit that provides a current difference between charge (UP) and discharge (DN) currents, and a buffer coupled to the replica circuit to buffer a received control voltage. 
     In one embodiment, a charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit that outputs a control voltage. The charge pump circuit also comprises a replica circuit that is coupled to the charge pump core circuit, wherein the replica circuit receives the control voltage and produces one or more bias signals that are coupled to the charge pump core circuit to minimize the difference between charge up and charge down currents generated by the charge pump core circuit. 
     In one embodiment, a method is provided for operating a charge pump circuit in a phase-lock loop circuit. The method comprises generating an output control voltage at a charge pump core circuit, generating one or more bias signals based on the control voltage, and adjusting the operation of the core circuit based on the one or more bias signals so as to minimize a difference between charge up and charge down currents. 
     In one embodiment, a charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit means for outputting a control voltage. The charge pump circuit also comprises a replica circuit means for receiving the control voltage and producing one or more bias signals that are coupled to the charge pump core circuit means to minimize the difference between charge up and charge down currents generated by the charge pump core circuit means. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein: 
         FIG. 1  shows one embodiment of a PLL; 
         FIG. 2  shows a mathematical model of the PLL of  FIG. 1 ; 
         FIG. 3  shows a circuit diagram that illustrates the operation of a phase/frequency detector and a CP circuit included in the PLL of  FIG. 1 ; 
         FIG. 4  shows a timing diagram that illustrates the signal timing of the circuits of  FIG. 3 ; 
         FIG. 5  shows one embodiment of a CP core circuit; 
         FIG. 6  shows a signal diagram that illustrates ringing and overshoot in the current pulses connected to an integration filter of the CP of  FIG. 5 ; 
         FIG. 7  shows one embodiment of a CP core circuit where differential pair switches replace single switch transistors used in the CP core circuit of  FIG. 5 ; 
         FIG. 8  shows one embodiment of the CP core circuit where a diode-connected transistor is added to the CP core circuit of  FIG. 7 ; 
         FIG. 9  shows a detail diagram of one embodiment of a CP circuit that operates to minimize the difference in the charge (I UP ) and discharge (I DN ) currents; 
         FIG. 10  shows a detailed view of one embodiment of a buffer circuit that operates to minimize the difference in the charge (I UP ) and discharge (I DN ) currents in a CP circuit; 
         FIG. 11  shows a detailed view of error amplifier circuits for use in a CP circuit; 
         FIG. 12  shows a detailed diagram of one embodiment of a replica circuit for use inaCP; 
         FIG. 13  shows one embodiment of a switch driver for use in a CP circuit. 
         FIG. 14  shows another embodiment of a switch driver where a switch amplifier is realized as a bipolar differential pair; and 
         FIG. 15  shows one embodiment of a servo circuit for use with a CP circuit. 
     
    
    
     DETAILED DESCRIPTION 
     In one or more embodiments, a PLL system is provided that includes an improved charge pump (CP) circuit that operates linearly and compensates for parameter variations. 
       FIG. 1  shows one embodiment of a PLL that comprises a charge pump (CP), RC integration filter, voltage-controlled oscillator (VCO), N-counter, and a phase/frequency detector (P/FD). The PLL relies on feedback to drive the frequency difference and phase offset between a reference (Ref) signal and the output of the N-counter towards zero. The operation of the PLL may also depend on the circuits that comprise the system; and as such, variations in circuit parameters alter the response of the system, lower the stability of the feedback loop, and introduce distortion. The CP and RC integration filter are circuits that may be especially sensitive. 
       FIG. 2  shows a mathematical model of the PLL of  FIG. 1 . The VCO produces an output signal (V out ) at a frequency set by control voltage (v ctrl ) that is expressed as;
   V   out ( t )= A   c  cos (ω free   t+K   VCO   ∫v   ctrl ( t ) dt ) 
where ω free  is the free-running frequency of the oscillator and K vco  is its gain function. The gain function K vco  describes the relationship between the excess phase of the carrier Φ out (s) and the control voltage v ctrl , i.e.
 
                   Φ   out     ⁡     (   s   )           v   ctrl     ⁡     (   s   )         =       K   vco     s           
The Div-by-N counter simply divides the output phase Φ out (s) by N. When the PLL is locked, the phase/frequency detector and CP combination generate an output signal (i CP (t)) that is proportional to the phase difference (error Δθ) between the two periodic signals input to the phase detector. The CP output signal can be expressed as;
 
                 i   CP     ⁡     (   s   )       =       K   PD     ⁢       Δθ   ⁡     (   s   )         2   ⁢   π               
A simple RC integration filter, consisting of resistor R and capacitor C, transforms the CP output signal to the control voltage V ctrl , which can be expressed as;
 
                 v   ctrl     ⁡     (   s   )       =         i   out     ⁡     (   s   )       ⁢     (     R   +     1   sC       )             
Combining the above transfer functions yields the composite transfer function;
 
               T   ⁡     (   s   )       =         K   PD     ⁢       K   VCO     ⁡     (     Rs   +     1   C       )             s   2     +       K   PD     ⁢     K   VCO     ⁢     1   N     ⁢     (     Rs   +     1   C       )                 
where a zero (at 1/RC) has been added to the second order system to stabilize it.
 
     The phase/frequency detector and CP define the parameter K PD . These circuits compare the output of the feedback N-counter to the reference signal Φ in  and generate the output signal I cp (t) representing their phase difference. 
       FIG. 3  shows a circuit diagram that illustrates the operation of the phase/frequency detector and CP circuits included in the PLL of  FIG. 1 .  FIG. 4  shows a timing diagram that illustrates the signal timing of the circuits of  FIG. 3 . 
     Referring again to  FIG. 3 , the phase/frequency detector (P/FD) tracks the N-counter&#39;s output signal (expressed as DIV) and the reference signal (expressed as REF), thereby triggering flip-flops (FF 1  and FF 2 ) on the active falling edges of these signals. An AND gate  302  resets the flip-flops, forcing both UP and DN pulses low, shortly after the triggering of the second flip-flop (FF 2 ) occurs. As such, the UP and DN pulses overlap slightly and stop at the same time, as illustrated in  FIG. 4 . 
     The P/FD drives the CP, which comprises a pair of switches S 1  and S 2  that connect current sources I UP  and I DN  to the integration filter (R 1 , C 1 ). An UP pulse closes switch S 1  and directs charge to the integration filter, raising the control voltage v ctrl . Similarly, a DN pulse closes switch S 2  and removes charge from the integration filter, lowering the control voltage v ctrl . The control voltage v ctrl , in turn, sets the frequency of the voltage-controlled oscillator (VCO in  FIG. 2 ). 
     Ideally, the CP circuit is both symmetrical and insensitive to the level of the control voltage v ctrl . The net charge (ΔQ) transferred or removed from the integration filter is proportional to the time difference (Δt) between the active edges of the N-counter&#39;s output signal (DIV) and the reference signal (REF), and can be expressed as;
 
ΔQ=K PD IΔt
 
where K PD  is the associated scaling factor and I is the current level—either I UP  or I DN . It may also be important that these currents be equal and therefore cancel during the overlap of the UP and DN pulses, otherwise, an error occurs.
 
     In one embodiment, the current sources I UP  and I DN  and the switches S 1  and S 2  are implemented using CMOS transistors. In one embodiment, the current source transistors operate in the saturation region with V DS ≧V GS −V T . In this region, the applied gate-source voltage V GS  sets the drain current I D  as expressed by; 
               I   D     =         μ   ⁢           ⁢     C   OX       2     ⁢     W   L     ⁢         (       V   GS     -     V   T       )     2     ⁡     [     1   +     λ   ⁡     (       V   DS     -     V   GS     -     V   T       )         ]               
where the μ is the carrier mobility, C OX  is the oxide capacitance, W and L are the device dimensions, V T  is the threshold voltage, and λ is the channel-length modulation coefficient. The voltage difference V GS -V T  is oftentimes noted as the overdrive or effective voltage V eff . In other applications, V DS &lt;V GS −V T  and the transistor operates in the linear region with I D  given by;
 
               I   D     =       μ   ⁢           ⁢     C   OX     ⁢       W   L     ⁡     [         (       V   GS     -     V   T       )     ⁢     V   DS       -       V   DS   2     2       ]       ⁢           ⁢   for   ⁢           ⁢     V   DS       &lt;       V   GS     -     V   T               
Therefore, to operate the transistor in saturation mode, the minimum drain-source V DS(sat)  is approximated by;
 
               V     DS   ⁡     (   sat   )         ≈         I   D     κ             
where κ is the intrinsic gain of the device
 
                 μ   ⁢           ⁢     C   OX       2     ⁢     W   L           
and λ is assumed to be small.
 
     Phase-locked loops may target a specific frequency or range of frequencies. The feedback system adapts to different device parameters and circuit responses through changes in the control voltage v ctrl . Supporting a wide control voltage range provides for lower VCO sensitivity (K VCO ) and improved noise immunity. Unfortunately, this may also mean dramatic changes in the operating bias for the transistors in the CP circuit. As a result, the symmetry, matching, and overall performance of the CP circuit may suffer. 
       FIG. 5  shows one embodiment of a CP core circuit. Transistors P 3 , N 3  act as switches and connect current-source transistors P 1 , N 1  to the integration filter. These switches also set the drain-source voltage V DS  applied to the current sources. To transfer an accurate charge to the integration filter (R 1 , C 1 ) and to operate devices P 1 , P 3  in the saturation mode, the following two conditions should be met;
   V   UP+   &lt;V   +   −+V   DS(sat)     P1     −V   GSP     P2      V   ctrl   &lt;V   +   −V   DS(sat)     P1     −V   DS(sat)     P2      
Increasing voltage V UP+ , collapses the drain-source voltage available to the current-source transistor P 1  and thereby prevents any charge transfer.
 
     Similarly, to remove an accurate charge from the integration filter and to operate devices N 1 , N 3  in the saturation mode, the following two conditions should be met;
 
 V   DN+   &gt;V   GS     P2     +V   DS(sat)     N1      V   ctrl   &gt;V   DS(sat)     N2     +V   DS(sat)     N1    
 
Lowering voltage V DN+  prevents any charge transfer. This means that the drain-source voltage applied to current-source transistors P 1  and N 1  actually switches, charging and discharging any associated device capacitances.
 
       FIG. 6  shows a signal diagram that illustrates how the charging and discharging action, described with reference to the CP core circuit of  FIG. 5 , may create ringing and overshoot in the current pulses connected to the integration filter. This adversely affects the switching times of the CP circuit, altering the net charge transferred and degrading the performance of the phase-locked loop. 
       FIG. 7  shows one embodiment of a CP core circuit  700  where differential pair switches replace the single switch transistors that were used in the CP core circuit  500 . Transistors P 2  and P 3  form one of the differential pair switches and operate to steer current I UP  either to the integration filter or directly to ground. The following voltage difference (ΔV UP ) is required to ensure complete switching, with all the current I UP  flowing through one of the devices—either transistor P 2  or P 3 —so that; 
               Δ   ⁢           ⁢     V   UP       &gt;         2   ⁢   I     κ             
Ideally, the differential pair switch maintains a fixed voltage at the drain of transistor P 1 . In practice, this voltage may change due to voltage and impedance differences seen at the drain of transistors P 2  and P 3 .
 
       FIG. 8  shows one embodiment of a CP core circuit  800 . The CP core circuit  800  comprises the CP core circuit  700  where a diode-connected transistor N 4  is added to raise the voltage and impedance seen by the drain of transistor P 2 . As a result, the two transistors (P 2  and P 3 ) closely match, thereby reducing the voltage changes at the drain of transistor P 1 , which improves the performance of the CP core circuit  800 . Diode-connected transistor P 4  serves a similar purpose. 
     The current source transistors P 1 , N 1  generally have long-channel geometries and high effective gate-source bias voltages (V eff ) to reduce channel-length modulation effects, minimize parasitic capacitance, and improve matching. The effective voltage also corresponds to the minimum drain-source voltage for operation in saturation mode V DS(sat)  since; 
               V     DS   ⁡     (   sat   )         ≈         I   D     κ             
and as a result;
   V   DS(Sat)     N1     ≦V   ctrl   ≦V   +   −V   DS(sat)     P1      
The effective voltage is typically several hundred millivolts.
 
     An ideal charge pump circuit generates matching charge (I UP ) and discharge (I DN ) currents so that these currents cancel each other when the UP and DN pulses overlap. In practice, this is challenging because the current sources are implemented using complimentary devices—PMOS and NMOS transistors—and therefore may be dependent upon different parameters. 
       FIG. 9  shows a detail diagram of one embodiment of a CP circuit that operates to minimize the difference in the charge (I UP ) and discharge (I DN ) currents. The CP circuit comprises the CP core circuit  800  and a replica circuit that duplicates the core circuit  800 . The replica circuit shares the same bias conditions including the output voltage (v ctrl ), which is forced through a buffer amplifier (BUFFER) and connects to the replica circuit through resistor R 2 . The forcing action may require the buffer amplifier to supply an output current Δi, indicating that I UP  is different from I DN . For example, if Δi is positive (current flows towards the replica circuit), then I DN  is greater than I UP . Similarly, if Δi is negative (current flows towards buffer amplifier), then I UP  is greater than I DN . The difference current Δi may be due to device mismatches or the level of the control voltage, V ctrl . 
     Any output current Δi is sensed by resistor R 2  and amplified by error amplifiers G M1  and G M2 . In one embodiment, the amplifiers G M1  and G M2  are transconductance amplifiers that convert an input differential voltage to an output current. The output currents from error amplifiers G M1  and G M2  adjust bias currents IB 2  and IB 4 , which are mirrored to the replica circuit and the CP core current sources (transistors P 1  and N 1 ). The two error amplifiers (G M1  and G M2 ) are part of feedback loops that reduce the current Δi, and thus the difference in the replica circuit&#39;s as well as the charge pump&#39;s currents (I UP  and I DN ). 
       FIG. 10  shows a detailed view of one embodiment of a buffer circuit that operates to minimize the difference in the charge (I UP ) and discharge (I DN ) currents in a CP circuit. The buffer circuit uses a buffer amplifier  1002  and resistor R 2  to force a replica circuit (constructed using transistors that match P 5 , P 6  and N 5 , N 6 ) to the same control voltage v ctrl  that is input to the charge pump circuit at node  1004 . In this way, the buffer circuit supplies or sinks the necessary current Δi to establish the control voltage v ctrl  at the replica circuit, where;
   Δi=I   N6   −I   P6   ≈I   DN   −I   UP    
and develops a proportional voltage across resistor R 2  equal to ΔiR 2 .
 
       FIG. 11  shows a detailed view of error amplifier circuits (G M1 , G M2 ) for use in a CP circuit. In one case, with regards to the circuit G M1 , the voltage developed across resistor R 2  is zero, and as such, bias current I B1  splits equally between transistors N 8  and N 9 , with I N8 =I N9 , (I N8  and I N9  are the currents through transistors N 8  and N 9 , respectively. Since transistors P 8  and P 9  mirror current I N8 , current I P9  essentially equals current I N9  and the difference current ΔI UP  approaches zero. When the operational amplifier  1102  supplies current to the replica circuit, it indicates that I UP  is less than I DN . The voltage developed across resistor R 2  drives transistor N 9  to pull more current than transistor N 8 . The difference current ΔI UP  is then pulled through transistor P 7 , with;
   I   P7   =I   B2   +ΔI   UP   ≈I   UP    
where current source I B1  (and thus ΔI UP ) depends on the output of the operational amplifier  1102 . That is to say that the current I B1  exists only when the voltage v ctrl  rises significantly above its lower limit, V DS(sat)N1 . As a result, the difference current ΔI UP  is generally positive.
 
     With regards to G M2 , transistors P 10 , P 11 , N 7 , and N 10 , N 11 , along with current sources I B3  and I B4  form a network similar to the one described above that adjusts current-source transistors N 1  and N 6 . When the operational amplifier  1102  sinks current from the replica circuit, it indicates that I UP  is larger than I DN . This creates a voltage across resistor R 2  that steers more current through transistor P 11  than transistor P 10 . As a result, a difference current ΔI DN  is directed towards transistor N 7 , making;
 
 I   N7   =I   B4   +ΔI   DN   ≈I   DN  
 
where the bias current I B3  (and thus ΔI DN ) depends on the output of the operational amplifier  1102 . Although it operates similarly to bias current I B1 , in this case, current I B3  exists only when the voltage v ctrl  falls significantly below its upper limit, V + −V DS(sat)P1 . This generally makes ΔI DN  positive.
 
       FIG. 12  shows a detailed diagram of one embodiment of a replica circuit for use in a CP. The replica circuit sets the bias voltages V B1  and V B2  to properly bias current sources P 6  and N 6  in the replica circuit. Transistor P 12  duplicates transistor P 5  along with transistor P 3  (see  FIG. 11 ) of the CP circuit. Transistor P 12  is connected as a diode to force its drain voltage to equal its gate voltage (and thus V DS  to equal V GS ). With transistor P 13  biased at V DS(sat) , the gate voltage of transistor P 12  corresponds to the maximum value allowed for V B1 ;
   V   B1   =V   +   −V   DS(sat)     P13     −V   GS     P12      
where mirror circuitry N 7  and N 12  establishes the proper current in transistors P 12  and P 13 . Similarly, transistor P 14  establishes the proper current density needed to set the gate-source voltage of transistor N 13  and the drain-source voltage of transistor N 14  with;
   V   B2   =V   GS     N13     +V   DS(sat)     N14      
where the voltage V B2  serves as a reference to a feedback network shown in  FIG. 12 .
 
       FIG. 13  shows a detailed embodiment of a driver switch for use with a CP circuit. The output levels associated with the driver switch are set by current sources I N16  and I N18  and resistors R 3 , R 4 , and R 5  such that;
   V   DN+   =V   + −( I   N16   +I   N18 ) R   5  and  V   DN−   =V   + −( I   N16   +I   N18 )R 5   +I   N18   R   5    
where R 3 =R 4  and
 
                 I   N18     ⁢     R   4       ≈     Δ   ⁢           ⁢     V   UP       &gt;         2   ⁢   I     κ             
which assures full switching of the differential pair N 2 , N 3 . In addition, the voltage V DN+  actually sets the drain voltage of the current source transistor N 1  with
   V   DS(sat)     N1     =V   DN+   −V   GS     N13      
Note that V DS(sat)  changes with both the drain current and the effective voltage V eff  of the device. A similar switch driver can be used to control transistors P 2  and P 3 .
 
       FIG. 14  shows another embodiment of a switch driver where a switch amplifier is realized as a bipolar differential pair (Q 1 , Q 2 ). 
       FIG. 15  shows one embodiment of a servo loop circuit for use with a CP circuit. The required drain voltage for transistor N 1  is set by the replica circuit and servo loop circuit. For example, the replica circuit shown in  FIG. 15  may be the same replica circuit shown in  FIG. 12 . The replica circuit establishes a copy of the charging current I UP  and develops a voltage V B2  equal to;
   V   B2   =V   GS     N13     +V   DS(sat)     N14      
which corresponds to the voltage needed for V DN+  to properly bias transistor N 1 . This assumes matching between transistors N 2 , N 3  and N 13  (to duplicate V GS(on) ) and transistors N 3  and N 14  (to duplicate V DS(sat) ). In turn, the servo loop circuit forces the maximum output level from the switch driver (equivalent to V DN+ ) to be equal to V B2 , assuming transistors N 15  and N 16 , N 17  and N 18 , resistors R 3  and R 7 , plus resistors R 5  and R 6  are matched. As a result,
 ( I   N15   +I   N17 ) R   6   +I   N17   R   7 =( I   N16   +I   N18 ) R   5   +I   N18   R   4    
which establishes the proper output levels from the driver switch.
 
     The above circuit descriptions remain valid even when the currents in the replica and mirror structures are lowered as long as the current density in these structures is uniform. This minimizes the overall current consumption of the CP. 
     These innovative circuits generate the proper switch levels, minimize the difference between the charge and discharge currents of the CP circuit, and remove many of the design restrictions associated with current source transistors. The result is a circuit with improved performance, stable K PD , and extended control voltage range. The described circuits also allow the CP circuit to operate at lower supply voltages. 
     In one or more embodiments, an improved charge pump circuit is provided. Accordingly, while one or more embodiments of the charge pump circuit have been illustrated and described herein, it will be appreciated that various changes can be made to the embodiments without departing from their spirit or essential characteristics. Therefore, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.