Abstract:
A clock and carrier recovery circuit, and a related method, for use in a minimum shift keying (MSK) receiver demodulator. The clock and carrier recovery circuit uses ringing filters to lock onto two frequency-doubled tone components of a received MSK signal. A signal having the same frequency as the clock is recovered by taking the difference of the outputs of the two filters. The output of each filter is then combined separately with a signal having a frequency to produce to signals, each having a frequency equal to twice the carrier frequency and having complementary amplitude modulation. These two signals are summed to cancel the amplitude modulation and the resulting sum signal, having constant amplitude and a frequency twice that of the carrier, is divided by two to recover the carrier signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to digital communications, and more particularly to demodulators for minimum shift keying (MSK) digital communication systems. The following brief explanation of MSK communication systems is by way of background to a discussion of the prior art and the invention. 
     MSK In General 
     Digital information is transmitted as a serial stream of discrete bits of information each bit being either a logic &#34;1&#34; or a logic &#34;0&#34;. The bits are presented for transmission at a rate called the clock rate or clock frequency F k . F k  is sometimes expressed in terms of the clock period T, where F k  =1/T. 
     Frequency shift keying (FSK) is a method of encoding and transmitting digital data by radio. In an FSK system, the &#34;0&#34; and &#34;1&#34; bits to be transmitted are converted into two tones, one of the tones having frequency F 1  and the other having frequency F 2 . These two tones are used to frequency modulate a radio frequency (&#34;rf&#34;) carrier having frequency F c , and the resulting frequency modulated (FM) signal is then transmitted. 
     At a receiver, the received FSK signal is demodulated to recover the tones, and then the tones are converted back into digital data. 
     Minimum shift keying (MSK) is a particularly efficient type of FSK system and hence is preferred for satellite communication systems. In MSK, tone frequencies F 1  and F 2  are required to relate to F c  and F k  in accordance with the equations: 
     
         F.sub.1 =F.sub.c -F.sub.k /4                               (1) 
    
     
         F.sub.2 =F.sub.c +F.sub.k /4                               (2) 
    
     MSK Modulation 
     Data bits are presented to an MSK modulator serially. Each bit has a duration equal to the clock period T. Thus at time 0, the first bit arrives; at time T, the next bit; at time 2T, the next bit; and so on. 
     The MSK modulator diverts this serial stream of data bits into two parallel channels called the &#34;I&#34; channel and the &#34;Q&#34; channel. The data bits alternate between channels; thus, if the nth bit goes to the I channel, the (n+1)th bit goes to the Q channel. 
     Because each bit has duration T, but only every other bit is present in the I channel, there is a space of duration T between successive bits in the I channel. The existence of these spaces permits each bit in the I channel to be shaped into a single half-sinusoid of duration 2T, thereby filling in the spaces. The output of the I channel is thus a continuous stream of half-sinusoids, each of duration 2T. Each half-sinusoid is positive if it represents a logic &#34;1&#34; and negative if it represents a &#34;0&#34;. 
     A half-sinusoid of duration 2T corresponds to one-half of a sinusoid having period 4T and frequency 1/(4T)=F k  /4. 
     The I channel output therefore corresponds to a continuous sinusoid I(t) having a frequency F k  /4. Because successive bits in the I channel are presented at times that are even multiples of T, I(t) is a cosine function defined by the expression: ##EQU1## where i=+1 when I(t) is representing a logic &#34;1&#34; and i=-1 when I(t) is representing a logic &#34;0&#34;. 
     A similar shaping process is performed on bits in the Q channel. Because successive bits in the Q channel are presented at times that are odd multiples of T, Q(t) is a sine function defined by the expression: ##EQU2## where q=+1 when Q(t) is representing a logic &#34;1&#34; and q=-1 when Q(t) is representing a logic &#34;0&#34;. 
     The rf carrier signal is split into two signals, each being a sinusoid having frequency F c . One of these F c  signals is modulated by I(t), resulting in a signal given by the expression: ##EQU3## The other F c  signal is shifted 90 degrees in phase and then is modulated by Q(t), resulting in the following signal: ##EQU4## The final step in the modulation process is to add I*F c  and Q*F c  together to produce an MSK output signal S: ##EQU5## The trigonometric identities 
     
         cos A cos B-sin A sin B=cos (A+B), 
    
     and 
     
         cos A cos B+sin A sin B=cos (A-B) 
    
     may be applied to S with the following results: ##EQU6## Hence, if i and q have the same sign, then S will have a frequency F 1  =F c  -F k  /4, but if i and q have opposite signs then S will have a frequency F 2  =F c  +F k  /4. These two values of the frequency of S are equal to the required frequencies for tones F 1  and F 2  as given by equations (1) and (2). 
     To summarize the above process, in an MSK modulator an input stream of digital data having a clock period T and clock frequency F k  is divided into two channels designated the I and Q channels. The even-numbered bits go to one-channel, the odd-numbered bits to the other. The bits in each channel are converted into a sinusoidal signal having a frequency of one-fourth the clock frequency. The I and Q channel sinusoidal output signals are 90 degrees out of phase with respect to each other. These I and Q output signals modulate an rf carrier having frequency F c  to produce a final MSK output signal S. The phase of S changes back and forth between 0 and 180 degrees from time to time, and the frequency of S changes back and forth between F 1  =F c  -F k  /4 and F 2  =F c  +F k  /4 from time to time, according to the values of the data being transmitted. S may therefore be considered as assuming the frequencies F 1  and F 2  at various times, and each of these frequencies may have a phase of 0 or 180 degrees. The signal S takes only one of these four possible forms at any given moment. 
     Transmission 
     A double-sideband suppressed-carrier transmission technique is used for the actual transmission of S. In this technique, the carrier at frequency F c  is suppressed before transmission, and only frequencies F 1  and F 2  are actually sent. A substitute &#34;carrier&#34; having frequency F c  in phase with the transmitter&#39;s carrier must be regenerated in the receiver in order to demodulate S and recover I(t) and Q(t). Also, a clock signal at frequency F k  =1/T must be regenerated in the receiver in order to convert I(t) and Q(t) back into digital data. 
     Demodulation 
     In an MSK receiver, a received MSK signal S is demodulated to extract the I(t) and Q(t) sinusoidal signals. This demodulation process is effected by splitting the signal S into two channels; electronically mixing a regenerated carrier having frequency F c  with S in one of the channels to produce I(t); phase-shifting the regenerated carrier 90 degrees; and then mixing the phase-shifted carrier with S in the other channel to produce Q(t). 
     I(t) is then combined with a regenerated clock signal to reproduce the I channel data bits, and Q(t) is combined with the same clock signal to reproduce the Q channel data bits. Finally the I and Q channel data bits are recombined to yield a reproduction of the original digital data in serial form. 
     Circuits to regenerate carrier and clock signals in MSK receivers are known to the art. However, these circuits are not practical for time division multiple access (TDMA) applications, such as modern satellite communication systems, as will become apparent from the following discussion of the prior art. The present invention overcomes this problem and provides a practical MSK demodulator for use in TDMA applications. 
     The Prior Art 
     It will be apparent that a regenerated carrier signal having the same frequency F c  as the transmitter carrier, and precisely in phase with it, is needed to successfully demodulate a received MSK signal S. Also, a regenerated clock signal having frequency F k  =1/T is required in order to recover digital data from the demodulated S signal. 
     The only frequencies actually received by an MSK receiver are F 1  =F c  -F k  /4 and F 2  =F c  +F k  /4 as given in equations (1) and (2). These two equations can be solved for F c  and F k  as follows: 
     
         F.sub.c =(2F.sub.1 +2F.sub.2)/4                            (5) 
    
     
         F.sub.k =2F.sub.2 -2F.sub.1                                ( 6) 
    
     The operations described by equations (5) and (6) can be carried out by an electronic circuit to regenerate F c  and F k  from F 1  and F 2 . The circuit of FIG. 1, developed by de Buda (&#34;Coherent Demodulation of Frequency-Shift Keying With Low Deviation Ratio&#34;, IEEE Trans. Commun., Vol. COM-20, No. 6, June 1972, pages 429-435), can be used for this purpose. 
     In FIG. 1, a received MSK signal S is applied to a squarer 11. Since S is sinusoidal, the effect of squarer 11 is to apply the trigonometric identity 
     
         cos.sup.2 A=1/2+1/2 cos 2A                                 (6a) 
    
     to S, thereby doubling the frequency of S. The resulting signal, at any given moment, is either 
     
         X.sub.1 =cos [2πt (2F.sub.1)]                           (6b) 
    
     is S is then being transmitted at frequency F 1 , or 
     
         X.sub.2 =cos [2πt (2F.sub.2)]                           (6c) 
    
     if S is then being transmitted at frequency F 2 . 
     X 1  and X 2  are applied to phase-locked loop (&#34;PLL&#34;) 12 and to PLL 13. PLL 12 locks onto X 1  during those times when F 1  is being transmitted and gives a stable, continuous output signal having frequency 2F 1 . PLL 13 locks onto X 2  during those times when F 2  is being transmitted and gives a stable, continuous output signal having frequency 2F 2 . 
     The outputs of PLL 12 and PLL 13 are multiplied in mixer 14, yielding an output X 3  composed of the sum and the difference of 2F 1  and 2F 2 . A low pass filter 15 removes the sum, leaving the difference 2F 2  -2F 1  as its output. In accordance with equation (6), this output from filter 15 is the desired clock frequency F k , and recovery of the clock signal is complete at this point in the circuit. 
     The output of PLL 12 which is a signal having frequency 2F 1 , is reduced to a signal having frequency F 1  in divider 16, and the output of PLL 13 is similarly reduced to a signal having frequency F 2  in divider 17. F 1  and F 2  are added in summing block 18, producing an output signal X 4  that contains 
     
         cos (2πt F.sub.c)                                       (6d) 
    
     in a form usable to demodulate S so as to recover I(t). 
     Similarly, output signal X 5  from summing block 19 contains 
     
         sin (2πt F.sub.c)                                       (6e) 
    
     in a form usable to demodulate S so as to recover Q(t). 
     The positive or negative sign in front of S is removed by the squaring operation performed by squarer 11, resulting in a 180 degree phase ambiguity in the recovered carrier signal F c . The undesirable effect of this ambiguity on the output digital data can be compensated for by differentially encoding the digital data prior to transmission and differentially decoding the data after reception, a process known to the art. 
     The phase-locked loops used in the circuit of FIG. 1 require a long interval of time, as much as several seconds, to lock onto their respective signals. This long lock-on time does not matter provided the duration of the transmission is much longer than the acquisition time. However, in satellite TDMA applications, a ground station transmits a burst of data to a satellite receiver during a time interval measured in microseconds. Then the transmission stops until the next burst of data is ready for transmission. In the meantime, the satellite receiver is reassigned to receive a burst of data from a different ground station; when that burst of data has been transmitted, the receiver is reassigned to yet a third ground station, and so on. A significant problem in TDMA systems arises from the randomness of the clock and carrier phase on a burst-to-burst basis. It will be apparent that a receiver using phase-locked loops does not have enough time to lock onto signals coming from various transmitters when each such signal has a duration measured in microseconds. 
     Attempts have been made to avoid the long lock-on times characteristic of phase-locked loops by replacing them with narrow bandpass filters. However, unlike a phase-locked loop, a narrow bandpass filter does not produce a constant-amplitude output. Rather, the amplitude of the output of such a filter varies, reaching a maximum level only after the desired input frequency has been continuously present for some interval of time. When the input signal vanishes, the amplitude of the filter output starts to decay. 
     It will be recalled that the frequency of the MSK signal S changes back and forth between F 1  and F 2 , and that only one of these two frequencies is present at any given time. Therefore, if narrow bandpass filters are used to isolate these two frequencies, the amplitude of the output of each filter will continuously vary as S changes back and forth between F 1  and F 2 . This variation in amplitude of the filter outputs constitutes amplitude modulation (AM) of the filter output signals, and the AM thus introduced must be removed by a limiter circuit before further use can be made of these signals. A limiter prevents the amplitude of a signal from exceeding a specified level, while preserving the shape of the waveform at amplitudes less than the specified level. 
     Current and future satellite communication systems employ high data rates, which require relatively high intermediate processing frequencies. A significant problem for rapid acquisition systems is the need to provide a recovered carrier with constant power. A significant problem resulting from this need is that limiters at these frequencies, while eliminating amplitude modulation, lead to unacceptable levels of phase modulation. This phase modulation causes significant degradation in the accuracy of the processed data. Hence, there has not been any practical way to take advantage of the highly efficient MSK method of transmission in TDMA applications at such high data rates. The present invention satisfies the need for such a circuit. 
     SUMMARY OF THE INVENTION 
     The present invention is characterized by a carrier and clock recovery circuit, and a related method, using filters to produce two signals at frequency 2F c . Although each of these signals is amplitude modulated by its respective filter, the modulation patterns are complementary, and thus when the two signals are added together, the result is a constant-amplitude signal at frequency 2F c . 
     Briefly and in general terms, the present invention uses ringing filters rather than phase-locked loops to lock onto the 2F 1  and 2F 2  components of the doubled input signal S. These filters acquire their respective input signals without the long time delay characteristic of phase-locked loops. The amplitude modulation (AM) introduced by either filter is at all times equal in magnitude but opposite in polarity to the AM introduced by the other. 
     The output signal of the 2F 1  filter may, by using equation (1) be represented as: 
     
         2F.sub.1 =2(F.sub.c -F.sub.k /4)=2F.sub.c -F.sub.k /2 
    
     In the present invention, this 2F 1  signal is mixed with a recovered F k  /2 signal to yield a sum signal having frequency 
     
         2F.sub.1 +F.sub.k /2=2F.sub.c -F.sub.k /2+F.sub.k /2=2F.sub.c. 
    
     This signal will hereafter be referred to as 2F c  &#39;. 
     The output signal of the 2F 2  filter may, by using equasion (2), be represented as: 
     
         2F.sub.2 =2(F.sub.c +F.sub.k /4)=2F.sub.c +F.sub.k /2 
    
     In the present invention, this 2F 2  signal is mixed with a recovered F k  /2 signal to yield a difference signal having frequency 
     
         2F.sub.2 =F.sub.k /2=2F.sub.c +F.sub.k /2-F.sub.k /2-2F.sub.c. 
    
     This signal will hereafter be referred to as 2F c  &#34;. 
     The 2F 1  ringing filter impresses on the 2F 1  signal an AM that varies according to the presence of the F 1  tone in S, and the 2F 2  ringing filter impresses on the 2F 2  signal an AM that varies according to the presence of the F 2  tone in S. But, since either F 1  or F 2 , but not both, is always present in S, the AM of the 2F 2  signal is complementary to the AM of the 2F 2  signal. Two signals with complementary AM have the property that the sum of their amplitudes always equals a constant. The AM on the 2F 1  signal is passed through its mixer onto 2F c  &#39;, and the AM on the 2F 2  signal is passed through its mixer onto 2F c  &#34;. Since the AM on 2F c  &#39; is equal and opposite to the AM on 2F c  &#34;, if the two signals are summed, their respective AM parts cancel each other and the result is a constant-amplitude signal of frequency 2F c . A simple frequency divider yields the desired end result, a constant-amplitude signal having frequency F c . 
     In accordance with the invention, a received MSK signal S is applied to a frequency-doubling circuit such as a squarer. As discussed previously, the result is a signal having components of frequency twice F 1  and twice F 2 . This signal is applied to two ringing filters, one tuned to 2F 1  and the other tuned to 2F 2 . These ringing filters produce output signals of frequency 2F 1  and 2F 2 , respectively. 
     It is necessary to recover the clock frequency F k  as well as the carrier, and this clock recovery is performed by the same means as in the prior art clock recovery circuit. Specifically, the 2F 1  and 2F 2  signals are mixed to produce a difference signal of frequency F k . Filtering is used to eliminate spurious mixer output frequencies, and, although AM is present in the recovered clock signal, the frequency F k  is sufficiently low that the AM may be eliminated by using a conventional limiter without introducing unacceptable PM. 
     The F k  signal is divided by two to produce a signal having frequency F k  /2. This signal is mixed with 2F 1  to produce sum and difference frequencies, but only the sum, having frequency 2F c  and referred to as 2F c  &#39;, is used. 
     The signal having frequency F k  /2 is also mixed with 2F 2  to produce sum and difference frequencies, but only the difference, having frequency 2F c  and referred to as 2F c  &#34;, is used. 
     The 2F c  &#39; signal carries the AM caused by the 2F 1  filter, and the 2F c  &#34; signal carries the AM caused by the 2F 2  filter. These two signals are algebraically added in a summing circuit, and the equal and opposite AM component cancel each other, yielding a signal of frequency 2F c  and constant amplitude. This signal is filtered and divided by two to produce the final output signal F c . Additional filtering of the final F c  signal may be performed as needed. 
     Although the carrier and clock recovery technique of the present invention will work at many frequencies, it has particular value at frequencies where other circuits with limiters present unacceptable phase modulation. At these high frequencies, power dividers must be used at each point in the circuit where the signal is divided into two paths. Also, depending on the frequency and signal strength of the received signal and on whether the signal is preamplified prior to the clock and carrier recovery operation, amplifiers may be needed at various points in the recovery circuit, including before and after the squaring operation and after each filtering operation. 
     It may also be desirable to filter the clock signal as recovered from the first mixer by the combination of a bandpass filter and a low pass filter, with amplification taking place in conjunction with each filtering operation, prior to the limiter stage. 
     The carrier and clock recovery circuit may be combined with an I-Q demodulator circuit to produce output signals I(t) and Q(t). In such a demodulator, the F c  signal is split by a power divider or other suitable dividing means into two signals. The input signal S is also split into two signals, but one of these signals is phase-shifted 90 degrees. The phase-shifted input signal is mixed with one of the F c  signals to produce Q(t), and the other input signal is mixed with the other F c  signal to produce I(t). After suitable filtering to remove spurious mixer outputs, I(t) and Q(t) are available for decoding. 
     In terms of a novel method for recovering clock and carrier signals from a received signal containing two frequency tones F 1  and F 2 , the invention comprises the steps of doubling the frequency of the received signal, filtering the frequency-doubled signal in two ringing filters tuned to frequencies 2F 1  and 2F 2 , respectively, to yield first and second continuous signals at these frequencies, deriving a half-clock-frequency signal from the first and second continuous signals, and mixing the first and second continuous signals with the half-clock-frequency signal, to yield two composite signals containing a component at twice the carrier frequency. The concluding steps needed to recover the carrier are summing the two composite signals to eliminate opposite amplitude modulations, filtering the signal resulting from the summing step, to obtain a signal of constant amplitude and at twice the carrier frequency, and frequency-dividing the latter signal to recover the carrier signal. 
     In the preferred embodiment of the invention, the step of deriving the half-clock-frequency signal includes mixing the two first and second continuous signals with each other, filtering the signals resulting from the last-mentioned mixing step to obtain a difference component at the clock frequency, limiting the difference component signal to eliminate amplitude variations, and frequency-dividing the clock-frequency signal to obtain the half-clock-frequency signal. 
     It will be appreciated from the foregoing that the present invention represents a significant advance in the field of digital communications. In particular, the present invention makes possible the transmission of digital data by means of the highly efficient and relatively error-free MSK method at high data rates in a TDMA environment. Other aspects and advantages of the present invention will become apparent from the following more detailed description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a prior art MSK clock and carrier recovery circuit; 
     FIG. 2 is a block diagram of an MSK clock and carrier recovery circuit according to the present invention; and 
     FIG. 3 is a detailed block diagram of an MSK demodulator employing a clock and carrier recovery circuit according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     It has not been possible to use the highly efficient minimum shift keying (&#34;MSK&#34;) system for transmitting digital data in time-division multiple-access (TDMA) applications because phase-locked loops in the carrier and clock recovery section of the demodulators of MSK receivers are subject to prolonged phase transients and cannot lock onto tone components of the received signal fast enough. Other available methods of signal acquisition introduce unacceptable phase modulation distortion into the recovered carrier signal. 
     The present invention solves this problem by using ringing filters for signal acquisition in the carrier and clock recovery section of an MSK demodulator; producing two carrier signals having complementary amplitude modulation; and using a summing circuit to eliminate this amplitude modulation without introducing phase modulation distortion. 
     FIG. 1 illustrates a typical prior art carrier and clock recovery circuit. An MSK input signal S is applied to squarer 11. Since S is sinusoidal, the effect of squarer 11 is to double the frequency of S. The output of squarer 11 at any given moment has frequency either X 1  =twice F 1  or X 2  =twice F 2 , where F 1  and F 2  are the two modulating tones, see equations (1) and (2), which produce S. 
     X 1  and X 2  are applied to phase-locked loop (PLL) 12 and to PLL 13. PLL 12 locks onto X 1  during those times when F 1  is being transmitted and gives a stable, continuous output at frequency 2F 1 . PLL 13 locks onto X 2  during those times when F 2  is being transmitted and gives a stable, continuous output at frequency 2F 2 . 
     The outputs of PLL 12 and PLL 13 are multiplied in mixer 14, yielding an output X 3  composed of the sum and the difference of 2F 1  and 2F 2 . A low pass filter 15 removes the sum, leaving as its output a signal having a frequency equal to the difference 2F 2  -2F 1  =clock frequency F k . 
     The output of PLL 12, 2F 1 , is reduced to F 1  in divider 16, and 2F 2  is similarly reduced to F 2  in divider 17. F 1  and F 2  are added in summing block 18 to produce X 4 , a cosine function of carrier frequency F c , and F 1  and -F 2  are added in summing block 19 to produce X 5 , a sine function of F c . 
     In accordance with the present invention, ringing filters are substituted for the phase-locked loops as shown in the block diagram of FIG. 2. and the more detailed diagram of FIG. 3. Basically, a ringing filter is a resonant cavity that is responsive to a very narrow band of frequencies. Such a filter is said to &#34;ring at&#34; a particular frequency, meaning that the output the filter will be at the ringing frequency, but at an amplitude dependent on the amplitude and duration of the ringing-frequency component at the input of the filter. The numbers of the elements in FIG. 2 correspond with the comparable elements in FIG. 3. 
     In FIG. 2, an input MSK signal S is applied to squarer 23, doubling the input signal to produce a signal having, at any given moment, a frequency of either 2F 1  or 2F 2 , just as in the circuit of FIG. 1. Ringing filter 29 rings at 2F 1 , which provides a continuous output signal having frequency 2F 1  but an amplitude that varies according to when F 1  is actually present in S. Likewise, ringing filter 35 rings at 2F 2  and gives a continuous output signal having frequency 2F 2  but an amplitude that varies according to when F 2  is actually present in S. Unlike the relatively slow phase-locked loops 12 and 13 of FIG. 1, ringing filters 29 and 35 are single-cavity filters which provide minimum step-function response time for a given bandwidth. This is a key requirement for rapid carrier recovery. 
     A clock signal with frequency F k  is recovered by mixer 39 and a filter 41, just as the clock signal is recovered in the circuit of FIG. 1 by mixer 14 and filter 15. In FIG. 2, a limiter 49 is used to eliminate amplitude modulation introduced by the action of filters 29 and 35. The limiter 49 prevents the amplitude of the clock signal from exceeding a specified value. Frequency F k  is sufficiently low that the limiter 49 does not introduce unacceptable phase modulation distortion into the clock signal. 
     The clock signal F k  is divided in divider 51 to produce a new signal having frequency F k  /2. This new signal is mixed with 2F 1  in mixer 55 to produce sum and difference signals. The sum signal, 2F c  &#39;, has frequency 2F c  and an amplitude modulation that varies according to when F 1  is actually present in S. 
     The F k  /2 signal is mixed with 2F 2  in mixer 57 to produce sum and difference signals. The difference signal, 2F c  &#34;, has frequency 2F c  and an amplitude modulation that varies according to when F 2  is actually present in S. 
     The amplitude modulation present in 2F c  &#39; is complementary to the amplitude modulation present in 2F c  &#34;. Hence, when these two signals are applied to summer 59, their amplitude modulations cancel, yielding a signal having frequency 2F c  and constant amplitude. Bandpass filter 61 removes any other signals introduced by the summer 59, and divider 63 reduces the signal having frequency 2F c  to a final recovered carrier at frequency F c . 
     A preferred embodiment of the present invention is shown in FIG. 3. FIG. 3 is a more detailed diagram than FIG. 2, but each element in FIG. 2 has a corresponding element in FIG. 3, and corresponding elements in the two figures are numbered alike. For example, limiter 49 in FIG. 2 corresponds to limiter 49 in FIG. 3. 
     In FIG. 3, a directional coupler 20 provides part of input signal S to squarer 23. Squarer 23 doubles the frequencies present in S and, after amplification by amplifier 25, the signal with these doubled frequencies is applied to ringing filters 29 and 35 through power divider 27. The output of filter 29 has a frequency 2F 1  and is applied to the mixer 39 through an amplifier 31 and a power divider 33. The output of filter 35 has a frequency 2F 2  and is applied to the mixer 39 through an amplifier 37 and another power divider 38. The mixer 39 produces a signal having a frequency equal to the difference between 2F 2  and 2F 1 . This difference signal, having frequency F k , is the desired clock signal. The filter 41 removes extraneous frequencies from the output of the mixer 39, and after amplification by amplifier 43, the limiter 49 removes any remaining variations in amplitude of the recovered clock signal F k . 
     The clock signal F k  is divided by frequency divider 51 to produce a signal having frequency F k  /2, and this signal is applied to the mixers 55 and 57 through another power divider 53. The mixer 55 produces the sum and difference of 2F 1  and F k  /2, of which only the sum, having frequency 2F c , is desired. The 2F 2  signal is applied to the mixer 57 through amplifier 56, and the result is the sum and difference of 2F 2  and F k  /2, of which only the difference, having frequency 2F c , is desired. The amplitude modulation added to 2F 1  by the filtering action of filter 29 is complementary to the amplitude modulation added to 2F 2  by filter 35, and these two amplitude modulation components cancel each other in the summer 59, yielding an output having frequency 2F c  and constant amplitude. 
     The bandpass filter 61 removes the unwanted signals from the output of the summer 59, and after amplification by amplifiers 63 and 65, the frequency 2F c  is divided by divider 67 to give a recovered carrier signal having the desired frequency F c . 
     The recovered carrier F c  is then applied to mixers 79 and 81 through a filter 69, a variable delay 71, an amplifier 73 and another power divider 75. The received signal S is applied to mixer 79 through power divider 77, and the output of the mixer 79 includes the difference between S and F c , which is a signal I(t) carrying half of the original digital data being transmitted. A low pass filter 85 removes the undesired sum output of the mixer 79. 
     The phase of signal S is also shifted 90 degrees by power divider 77 and is then applied to another mixer 81. The output of the mixer 81 contains the sum and difference of F c  and the phaseshifted S, and the difference signal is a signal Q(t) carrying the other half of the original data being transmitted. A low-pass filter 83 removes the undesired sum output of the mixer 81. 
     In the preferred embodiment illustrated in FIG. 3, the circuit components have been selected for an input signal S having frequencies F 1  =537.5 MHz and F 2  =662.5 MHz. These two signals correspond to an original transmitter carrier of frequency F c  =600 MHz and a clock of frequency F k  O=250 MHz. The following specific components can be used for operation at these frequencies: 
     
         ______________________________________No.  Designator     Manufacturer Part No.______________________________________20   Directional Coupler               Anaren       10014-1021   Amplifier      Avantek      UTC12-104M23   Doubler        Vari-L       WD-10225   Amplifier      Aertech      A467627   Power Divider  Anzac        DS-31329   Cavity Filter:1,075 MHz31   Amplifier      Avantek      UT80-0658M33   Sigma/Delta Hybrid               Anzac        HH-12835   Cavity Filter:1,325 MHz37   Amplifier      Avantek      UT80-0658M38   Sigma/Delta Hybrid               Anzac        HH-12839   Mixer          Watkins-Johnson                            M1J41   Cavity Filter:250 MHz43   Amplifier      Avantek      UT80-0673M49   Comparator     Plessey      968551   Flip-Flop      Fairchild    11C06and Line Driver               Tau-Tron     PM501M53   Sigma/Delta Hybrid               Anzac        HH-12855   Mixer          Watkins-Johnson                            M1J57   Mixer          Watkins-Johnson                            M1J59   Sigma/Delta Hybrid               Anzac        HH-12861   Cavity Filter: Delta Microwave1,200 MHz63   Amplifier      Avantek      UT80-0658M65   Amplifier      Watkins-Johnson                            6202-767   1000 MHz-2     Plessey      860569   Cavity Filter:600 MHz71   Delay Line73   Amplifier      Avantek      UTC-103375   Power Divider  Anaren       4J026477   90 degree Hybrid               Anaren       10014-379   Mixer          Watkins-Johnson                            M1J81   Mixer          Watkins-Johnson                            M1J83   Lumped LC Filter:250 MHz85   Lumped LC Filter:250 MHz______________________________________ 
    
     The present invention is key to efficient use of TDMA/MSK communications. Prior to the present invention, it has not been possible to fully utilize MSK transmission at high data rates in TDMA communication systems. 
     Although one specific embodiment of this invention has been described and illustrated, it will be understood that the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated, and that various changes can be made within the scope of the invention. For example, by proper selection of parts, operation at many different carrier and clock frequencies can be achieved. Operation at other frequencies might obviate the need for some of the components illustrated in FIG. 3 such as power dividers and directional couplers. It is therefore to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.