Abstract:
A closed loop control system for variable reluctance stepper motors which senses a voltage indicative of motion on the driven windings, uses this voltage to confirm that motion has occurred, compares this voltage with one modeled after a waveform indicative of no motion and effects successive changes in the winding drive states at optimum times.

Description:
BACKGROUND OF THE INVENTION 
     It is well known that stepping motors of all kinds exhibit instabilities at certain combinations of drive, load inertia and operating frequency. These instabilities result from the fact that the force/displacement characteristic at each cardinal position of the stepper is like a spring constant which, acting on the inertia mass of the moving part, results in a highly undamped mechanical resonance. Operation of the stepper at the resonant frequency or at harmonics of this frequency will often result in erratic performance. While there are timing methods which will uniformly accelerate and decelerate a stepping motor through its resonance frequencies, these methods are all subject to the requirement that the load must be nearly constant. A well-compensated stepping motor drive system which smoothly accelerates, slews and decelerates a given load will usually perform very badly if the load is doubled or halved. 
     Manufacturers and users of stepping motors have developed various techniques for controlling stepper motors in a closed-loop manner. Feedback stepper controls may be classified into two groups: (1) velocity feedback systems, in which a signal indicative of mechanical stepping rate is developed and used to modify the drive frequency; and (2) pulse position or timing feedback systems, in which an output is derived from either the motor itself or a separate transducer and used directly to control stepper drive switching. Velocity feedback is implicit in the latter systems and the response of the stepper to time varying loads is much more rapid. The most successfully known method of feedback control involves the addition of an external position measuring device such as an electro-optical transducer. Signals from the transducer are used to confirm and count steps and in some systems the transducer output is used directly to time driving pulses to the motor. 
     Investigators have tried to derive feedback signals directly from the windings of a stepper motor. The principal advantage of this approach would be lower costs. A secondary advantage in high performance systems would be the elimination of the inertia of a separate transducer, which can be a significant part of the total load. The problems most frequently encountered are that the windings of most stepper motors have a high degree of cross-coupling and the feedback signals are small compared with drive voltages. In conventional steppers, as the motor speed changes the relative magnitudes of these voltages vary significantly. The most successful known system is one which measures average motor current which is indicative of average motor speed because the motor back EMF reduces motor current. At least one such closed loop motor control system is commercially available. The response of such a system to load transients is extremely poor, however, because the averaging process involves a long time constant. 
     BRIEF DESCRIPTION OF THE INVENTION 
     It has been discovered that stepping motors of the type disclosed in application Ser. No. 926,311 filed July 20, 1978 and entitled &#34;Variable Reluctance Stepper Motor&#34; are characterized by the production of a motion dependent electrical signal that can be employed in the incremental motion motor controller of the present invention to time the drive pulses in an optimum fashion so as to achieve reliable stepper operation during acceleration, slewing and deceleration under widely varying load conditions. 
     Variable reluctance stepper motors characterized by such a motion dependent signal generally comprise cooperating fixed and moving structures having tooth-like patterns of equal pitch but with the fixed and moving teeth having different lengths, measured in the direction of movement. The smaller teeth are divided into groups which are offset from one another by fractions of a tooth pitch to provide a bi-directional motor capable of being stepped from one position to the next with the teeth tending to produce force in the desired direction carrying essentially all of the flux and the teeth tending to produce force in the opposite direction carrying essentially no flux. 
     One embodiment of a linear variable reluctance stepper motor characterized by such a motion dependent signal comprises a cylindrical slider and a rod-shaped stator. The slider comprises two poles separated by a permanent magnet. Each pole comprises two sets of one or more spiral teeth separated by a winding. Each winding is continuously energized by a direct current, the direction of which is controlled. The stator comprises a toothed member having uniformly spaced spiral teeth having a pitch P and a width equal to P/2. The spiral slider teeth have a pitch P and a width equal to P/4. The slider tooth sets on each pole are offset from each other by an amount equal to (n±1/2)P, n being an integer. The poles of the slider are offset from each other by an amount equal to (m±1/4)P, m being an integer. 
     One embodiment of a disk, rotary variable reluctance stepper motor characterized by such a motion dependent signal comprises a rotor and a stator having two poles. Between the stator poles is a disk-shaped rotor having uniformly spaced radial teeth having an angular pitch P and an angular width equal to P/2. Each stator pole comprises two sets of radial teeth, the locus of each set describing a circle with a different radius. The stator teeth have an angular pitch P and an angular width equal to P/4. Associated with each stator pole is a permanent ring magnet and a winding. The sets of teeth in each stator pole are offset from each other by an angular amount equal to (n±1/2)P, n being an integer. The stator poles are offset from each other by an angular amount equal to (m+1/4)P, m being an integer. Each winding is continuously energized by a direct current, the direction of which is controlled. 
     One embodiment of a cylindrical, rotary variable reluctance stepper motor characterized by such a motion dependent signal comprises a rotor and a stator having two poles. The rotor is cylindrical and has longitudinally extending teeth with grooves therebetween, the rotor teeth having an angular pitch P and an angular width equal to P/2. The stator is cylindrical and surrounds the rotor. The stator has two annular poles separated by an annular magnet. Each stator pole has two sets of equally spaced, longitudinally extending teeth having an angular pitch P and an angular width equal to P/4. The sets of teeth in each stator pole are offset from each other by an angular amount equal to (n±1/2)P, n being an an integer. The two stator poles are offset from each other by an angular amount equal to (m±1/4)P, m being an integer. The sets of teeth in each stator pole are separated by an annular winding which is continuously energized by a direct current, the direction of which is controlled. 
     Thus, the variable reluctance stepper motors suitable for use with the incremental motion motor controller of the present invention comprise a pair of windings continuously energized by direct currents the direction of which is controlled. The motion dependent signal employed in the incremental motion controller of the present invention is derived from that end of the winding which has most recently switched to the lower (e.g., ground) voltage. In the absence of any motion, the voltage will exhibit an unperturbed waveform which, in the case of a linear variable reluctance stepper motor, may be of the type V=a(1-e -bt ), where a and b are constants. When the stepper motor is allowed to move, however, the change in reluctance induces a transient voltage in the winding which is superimposed on the unperturbed waveform and results in a perturbed waveform. In the case of a linear variable reluctance stepper motor the perturbation may be such as might be caused if &#34;b&#34; in the expression V=a(1-e -bt ) were not constant but, for some time t&gt;0, b=b(t), first decreasing and then increasing in value. See, e.g., the lower curves in FIGS. 8A and 8B. As described in greater detail hereinafter, the incremental motion motor controller of the present invention compares the motion induced (perturbed) signal with a synthesized signal which is modeled after the no-motion (non-perturbed) waveform and which is offset from the no motion waveform in the direction of perturbation so as to control the timing of the drive pulses and achieve reliable stepper operation during acceleration, slewing and deceleration under widely varying load conditions. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified view in section of a linear, variable reluctance stepper motor for use with the motor controller of the present invention. 
     FIG. 2 is a simplified plan view, partially sectioned, of a cylindrical, rotary, variable reluctance stepper motor for use with the motor controller of the present invention; 
     FIG. 3A is a simplified view in section of a disk, rotary, variable reluctance stepper motor for use with the motor controller of the present invention; 
     FIG. 3B is a simplified view of the tooth arrangement of the motor of FIG. 3A; 
     FIG. 4A is a simplified view in section of a slider element for the motor of FIG. 1; 
     FIG. 4B is a simplified partial plan view of a stator for use with the spiral slider element of FIG. 4A; 
     FIG. 5 is a functional block diagram of one embodiment of the incremental motion motor controller of the present invention; 
     FIG. 6 is a schematic diagram of one embodiment of the motor drive circuit of FIG. 5; 
     FIG. 7 is a schematic diagram of one embodiment of the function generator and comparator circuits of FIG. 5; 
     FIGS. 8A, 8B and 8C are graphical representations of typical waveforms associated with one embodiment of the incremental motion controller of FIG. 5; and 
     FIGS. 9A, 9B and 9C are flow diagrams of one embodiment of the programs for the processor of FIG. 5. 
    
    
     DETAILED DESCRIPTION 
     One embodiment of a linear variable reluctance motor useful with the incremental motion motor controller of the present invention is illustrated in FIG. 1. Linear variable reluctance motor 10 comprises a cylindrical stator 11 and an annular slider 14. Stator 11 has teeth 12 and interspersed grooves 13. The teeth have pitch P and a width P/2. Stator 11 is preferably formed from 2.5% silicon iron. Annular slider 14 slides along stator 11 on support bearings 15. Slider 14 comprises poles 16 and 17 separated by ring permanent magnet 18, preferably a samarium cobalt magnet. Pole 16 comprises two annular slider elements 19 and 20 while pole 17 comprises two annular slider elements 21 and 22. Slider elements 19 and 20 are separated by winding 23 while slider elements 21 and 22 are separated by winding 24. Between ring permanent magnet 18 and poles 16 and 17 are flux &#34;regulators&#34; 25 and 26. The slider elements and flux &#34;regulators&#34; are also formed of 2.5% silicon iron. Annular rings 27 and 28, also of 2.5% silicon iron, provide flux paths between slider elements 19-20 and 21-22, respectively. 
     Whereas stator teeth 12 have a pitch P and a width equal to P/2, slider teeth 29 have a pitch P and a width equal to P/4. In addition, the teeth in slider elements 19 and 20 (as well as the teeth in slider elements 21 and 22) are offset from each other by an amount equal to (n±1/2)P, n being an integer. The teeth of poles 16 and 17 are offset from each other by an amount equal to (m±1/4)P, m being an integer. Motor 10 is &#34;stepped&#34; from one linear position to the next by reversing the direction of current in one of the two control windings 23 and 24, both of which are continuously energized. 
     One embodiment of a cylindrical rotary variable reluctance motor useful with the incremental motion motor controller of the present invention is illustrated in FIG. 2. Motor 40 comprises a cylindrical rotor 41 having longitudinally extending teeth 42 with grooves 43 therebetween. Teeth 42 have an angular pitch P and an angular width equal to P/2. Grooves 43 may be filled with a non-magnetic material so that rotor 41 presents a smooth outer periphery. Stator 44 is provided with two poles, 44a and 44b. Associated with each of stator poles 44a and 44b are two sets of longitudinally extending stator teeth 45-46 and 47-48. Positioned between stator teeth 45-46 and 47-48 are control windings 49a and 49b, respectively. Stator teeth 45, 46, 47 and 48 have an angular pitch P and an angular width equal to P/4. Stator poles 44a and 44b are separated from each other by ring permanent magnet 49. Stator teeth 45 and 46 (as well as stator teeth 47 and 48) are displaced from each other by an angular amount equal to (n±1/2)P, n being an integer. Stator poles 44a and 44b are offset from each other by an angular amount equal to (m±1/4)P, m being an integer. 
     Control windings 49a and 49b are continuously energized by direct currents of a magnitude sufficient to create an MMF equal to that developed by permanent magnet 49, the direction of current being selected to cause the magnetic flux developed by the control winding either to aid or oppose the magnetic flux of permanent magnet 49. The four possible combinations of current direction establish flux paths through the rotor and stator teeth which are analogous to those created in the linear stepper motor of FIG. 1. The rotary stepper motor is stepped by changing the direction of current of one of control windings 49a or 49b. 
     One embodiment of a disk, rotary variable reluctance motor useful with the incremental motion motor controller of the present invention is illustrated in FIGS. 3A and 3B. Motor 50 comprises a rotor 51 mounted on a non-magnetic, preferably stainless steel, shaft 51a by means of a central collar 51b, which may be made from an epoxy resin, upon which is mounted an integral soft iron ring 51c. Two stator poles 52 and 53 are disposed on opposite sides of rotor 51. Stator pole 52 comprises two sets of radial, wedge-shaped teeth 54, 55, the locus of each set describing a circle with a different radius. Stator pole 53 comprises two sets of similar stator teeth 56, 57. Associated with stator poles 52 and 53 respectively are permanent ring magnets 57 and 58 preferably of samarium cobalt. Surrounding ring magnets 57 and 58 respectively are coils 59 and 60 having leads 59a-59b and 60a-60b adapted for connection to sources of current whose direction is controllable. 
     Rotor 51 comprises equally spaced, wedge-shaped radial teeth 61. Rotor teeth 61 and stator teeth 54-56 are preferably made from vanadium premendur. Rotor teeth 61 have an angular pitch P and an angular width P/4. Stator teeth 54, 55 (as well as stator teeth 56, 57) are offset from each other by an angular amount equal to (n±1/2)P, n being an integer. Stator poles 52 and 53 are offset by an angular amount equal to (m±1/4)P, m being an integer. FIG. 3B shows the spatial relation between rotor teeth 61 and stator teeth 54, 55. Both the rotor and stator teeth are preferably embedded in epoxy rings. 
     The direct current continuously applied to control windings 59, 60 is of a magnitude substantially equal to the MMF of a ring-shaped permanent magnets 57 and 58, either aiding or opposing. Incremental stepping of the disk-type stepping motor is controlled by switching current direction as described earlier. Although not shown for purposes of simplicity, it should be understood that stator halves 52, 53 are typically enclosed within a non-magnetic housing. 
     FIGS. 4A and 4B show a spiral slider element and stator for use with the linear variable reluctnce stepper motor of FIG. 1. Spiral slider element 19 is comprised of a hollow cylindrical shell 19a having an outwardly extending circular flange 19b provided for mounting purposes. The hollow interior is provided with a tooth pattern comprised of teeth 29 arranged in a regular helix, each tooth having a pitch P and a width equal to P/4. Grooves 30 are three times as wide as teeth 29. Four spiral slider elements are employed in each motor 10 (elements 19, 20, 21 and 22 of FIG. 1). FIG. 4B shows the stator 11 having interspersed teeth 12 and grooves 13. Teeth 12 and grooves 13 have a pitch P and a width equal to P/2. Teeth 12 of the stator form a continuous helix and have square threads. 
     In a preferred method for fabricating stator 11 an iron bar, preferably 2.5% silicon iron, is machined on a latch and helical threads of the desired depth are cut therein. The threaded bar is then tin flashed with a very thin electro-deposit of elemental tin so as to make soldering material to the threaded bar possible. Next a tinned trip of electrically conducting, non-magnetic material is fitted into the groove 13 extending the length of the bar. This material may, for example, be copper or aluminum. The strip may be secured to the bar by a screw 11a. After the strip has been placed in groove 13 the bar is soldered, for example by dipping, so as to fill up the space around the tinned strip with solder. Next the bar is ground to a diameter slightly smaller than the desired finished diameter. It may, for example, be ground to a diameter 0.002 inches less than the desired finished diameter. The ground rod is now preferably copper flashed with a very thin copper coating a fraction of a thousandth of an inch thick. The ros is now plated with, for example, a thin layer of a non-magnetic material such as chromium to produce a very hard finish. When chromium is used for plating it is necessary to go through the step of copper flashing. When other plating materials such as nickel are used, the copper flashing step may be omitted. 
     In the finished structure support bearings 15 ride on stator 11 (See FIG. 1). Where the plating on stator 11 is hard, support bearings 15 are of a softer material. Conversely, where the surface of stator 11 is soft, the support bearing material is harder. For example, where the surface of stator 11 is very hard, e.g., chromium, support bearings 15 are preferably of an oilite sintered bronze material. Alternatively, support bearings 15 may be eliminated and the grooves between teeth 23 of the slider elements may be filled with a Teflon loaded material called &#34;Delrin&#34; or with a nylon loaded material called &#34;Rulon&#34; and employed directly in lieu of bearings 15. Where stator 11 is plated with a material which is not quite as hard as chromium, such as nickel, then support bearing 15 may be made from aluminum treated with the &#34;Tufram&#34; process of General Magnaplate which has the effect of oxidizing the aluminum to make polycrystalline alumina after which the voids are impregnated with Teflon. This is a very hard bearing material which has a low coefficient of friction. 
     It should be understood that the tooth arrangements heretofore described may be reversed in that the wide teeth or the narrow teeth may be provided on the fixed or on the moving part, the opposite tooth configuration being placed on the moving and fixed parts respectively. In addition, the permanent magnets, although preferably formed of samarium cobalt, can be formed of any suitable material. Alternatively, they may be electromagnets. Magnetic paths may be either solid or laminated and the coils may be located as shown or wound directly around the teeth to provide different coupling for their MMF&#39;s. In the linear embodiment, the cross section of the inner member need not be round but may be square, hexagonal or any other desired shape. An inner member having a round cross section is preferred because it is easier to manufacture. 
     The number of teeth employed and, therefore, the size of motion increments, is not limited by any ratio or formula involving pole and slot counts as is the case with vernier steppers. If the desired number of rotary steps is divisible by four two but not by four, a motor car be designed to provide directly this capability. If the desired number of steps is divisible by then the motor must have two electrical steps per design step. To provide an odd number of steps per revolution of the motor, the motor must be designed with four electrical steps per design step. In most cases, however, one to three steps can be added to the design value to simplify the design. On the other hand, linear motors can be designed to have any pitch within the practical limits of physical size and gap tolerances. Although gap tolerances should be close, they fall well within practical ranges. 
     FIG. 5 is a functional block diagram of one embodiment of the incremental motion controller of the present invention. It comprises a processor 70, motor drive circuits 71, 72, waveform generators 73, 74, 75, 76 and comparators 77, 78, 79, 80. The motor drive circuits continuously supply direct current to the motor windings which may, for example, be windings 23 and 24 of the linear variable reluctance motor of FIG. 1. Processor 70 may, for example, be a Rockwell 6502 microprocessor. Motor drive circuit 71 may, for example, be of the type shown in FIG. 6. Waveform generator 74 and comparator 80 may, for example, be of the type shown in FIG. 7. 
     Each motor drive circuit comprises an H-bridge which drives its winding with essentially constant current in one of two directions. The feedback signal used to control stepper timing is derived from the end of the winding which has been most recently switched to the lower in this case (ground) voltage. At the moment of switching the winding produces an EMF that causes the diode in parallel with the lower switching transistor to conduct, and the voltage reaches approximately -1.0 volts. As the energy in the winding inductance is dissipated, this voltage rises above ground and approaches a positive voltage equal to the IR drop of the winding current through the forward resistance of the driving transistor and the resistance of the 1.5 ohm current limiting resistor. In the absence of any motion produced EMF, the voltage will exhibit an unperturbed waveform which, in the case of a linear variable reluctance stepper motor of the type shown in FIG. 1, may be of the form V=a(1-e -bt ), where a and b are constants.Such waveforms are shown, for example, in the upper curves in FIGS. 8A and 8B. 
     If, however, the stepper is allowed to move in response to the condition described above, then the reluctance change at the end of the motor controlled by this winding will produce a momentary EMF, superimposed on the unperturbed waveform. In the case of a linear variable reluctance stepper motor of the type shown in FIG. 1, the perturbation may be such as might be caused if &#34;b&#34; in the expression V=1(1-e -bt ) were not constant but, for some time t&gt;0,b=b(t), first decreasing and then increasing in value. Such perturbed waveforms are shown, for example, in the lower curves in FIGS. 8A and 8B. The lower curve in FIG. 8A, which is typical of the motion voltage produced with light load. If the stepper is more heavily loaded, however, the motion voltage will resemble that shown in the lower curve in FIG. 8B. The motion voltage occurs later, indicating a slower mechanical response to the reversal of winding current. 
     In the incremental motion motor controller of the present invention a signal is synthesized in waveform generators 73-76 which is modeled after the no motion (non-perturbed) waveform and is offset from the no motion waveform in the direction of the perturbation. The motion induced (perturbed) signal is compared with the synthesized signal using comparators 77-80. In the case of linear variable reluctance stepper motor of the type shown in FIG. 1, the synthesized and perturbed waveforms, together with the comparator output are shown graphically in FIG. 8C. The first crossing, indicated by the comparator output going to its low output voltage, occurs at the time which is nearly optimum for acceleration switching. The second crossing, indicated by comparator output going to its higher output voltage, occurs at a nearly optimum time for deceleration switching. Depending on the desired program of motion, one of these transitions can be used to cause reversal of the winding current at the other motor pole so that the next mechanical state is selected. That winding, in turn, will produce a motion control voltage which can be used to time the next reversal of the first winding current, and so on. 
     As will be readily appreciated by those skilled in the art, the waveform of the no motion signal and the motion induced signal is heavily dependent on the physical construction of the motor. In the case of other linear embodiments or in the case of rotary embodiments of the variable reluctance stepper motors disclosed herein, those waveforms may or may not be exponential in character. They might, for example, be parabolic or hyperbolic. They may even take a form which does not readily lend itself to mathematical expression. Nevertheless, such waveforms can still be synthesized in waveform generators using, for example, piecewise linear approximations, read only memories (ROM&#39;s), microprocessors or a combination thereof. 
     It will also be understood that those skilled in the art that if the stepper motor encounters a hard stop or an excessive load, then the motion voltage and resulting comparator outputs will not be produced and the next state of the windings will not be selected. This condition can be used to signal an overload or to stop counting and indicate the actual position reached by the stepper. A correct response to a hard stop or an excessive load is possible only with a step-by-step feedback technique. It is not possible with a velocity averaging feedback technique. 
     With a large but not excessive load the timing of the first crossover at the comparator input will be delayed, as shown in FIGS. 8A and 8B, and switching to the next state will be automatically delayed. The stepper will therefore automatically slow down in response to increasing load and speed up when the load is decreased or removed, and this response will occur on a step-by-step basis. 
     While an incremental motion motor controller could be used to control stepper motion directly, without the counting of steps, by a system which connects the comparator outputs directly to winding controls, most actual systems will require a means of step counting and a method for commanding the stepping motor to move to various positions according to a fixed or adjustable sequence. A flexible control device which can produce this type of response is a microprocessor, incorporating control programs which select the winding states and feedback signals, providing full positioning performance. The flow charts for one suitable program are shown in FIGS. 9A, 9B and 9C, with FIGS. 9B and 9C showing the &#34;STEPS&#34; and &#34;DELCSN&#34; subroutines. 
     The value POSNOW is the present position of the stepper motor, counted up and down as the stepper actually moves. POSCOM is the commanded new position, set at a new value before entering the program from the Monitor. The program starts by computing the difference between POSNOW and POSCOM. The flag indicating the sign of this difference is DIRFLG. The absolute difference is OFFSET, a quantity which will be counted down to zero as positioning proceeds. If OFFSET is initially zero the routine returns to Monitor. If not, the first step is taken by subroutine STEPS. After this, the program checks whether 2 steps remain and, if so, switches to a deceleration routine. If more than 2 steps remain, the DELSCN subroutine examines the selected feedback comparator for a motion signal. When it occurs, the next step is taken. 
     The deceleration routine uses a subroutine DELSCN also. But when the comparator has made a transition to zero, the routine continues by examining the same comparator for a transition to one. When that occurs, the next step is taken and this routine repeats until OFFSET=φ. 
     The STEPS subroutine corrects the value of POSNOW by adding DIRFLG, which is either +1 or -1. The lowest order 2 bits of POSNOW are now masked and used to select the state of output windings to cause motion to the position POSNOW. This is done by using the low order bits of POSNOW as part of an index. After a delay the same bits are used to construct another index which selects the generator for the comparison transient. Finally, the OFFSET is decremented, and the subroutine exits. 
     The DELSCN subroutine initially delays action to allow the winding current transient to die down. Then an index is computed to select the proper input for feedback. The input is repeatedly scanned by a loop whose iterations are counted. If no feedback has occurred by the time initial value LOOPCT φ has been decremented to zero, the program exits to Monitor because the stepper has taken too long to move. In so doing, it must correct the stack pointer (SP) because it is jumping out of a subroutine. When the input from the comparator is found to be zero, the subroutine exits normally. 
     The program described is, and will usually be, part of an overall control program which communicates with a source of commanded positions and may feed back condition reports to this source. The routines described are sufficient to provide positioning response to a digital command, however, and comprise only 180 bytes. 
     Tests with a linear variable reluctance stepper motor of the type shown in FIG. 1 have demonstrated that under closed loop control reliable stepping rates of about 400 steps/second are readily achieved even though in an open loop mode the motor will not reliably step at over about 150 steps/second. Under closed loop control the motor has been shown to be quite insensitive to load, running from 400 steps/second down to less than 50 steps/second with increasing load, and always indicating actual steps completed after a hard stop 
     While the incremental motion motor controller of the present invention has been described in detail in connection with linear variable reluctance stepper motor it will be appreciated by those skilled in the art that it is equally applicable to rotary disk and cylindrical rotary embodiments as well. In addition, while the program disclosed in FIGS. 9A-9C and in the Appendix adjusts the timing of current switching on the basis of position, it will be appreciated by those skilled in the art that the timing of current switching may also be adjusted on the basis of a velocity signal, derived from the time between steps. Even higher speeds may be attained by a control system which commands a position more than one step away from the dynamic position. This technique may be particularly effective where the delay in energizing windings becomes a significant limiting factor in stepper performance. Under these circumstances, the feedback signal will have to be measured on the other winding and a delay adjustment may be necessary to avoid producing reverse forces or torques. 
     Although two waveform generators are shown in FIG. 5 for each winding, it will be appreciated by those skilled in the art that where the no-motion waveform produced when one end of a winding is switched to the lower potential is substantially the same as when the other end of the winding is switched to the lower potential, then only a single waveform generator is needed for each winding. Similarly, only one comparator would be required for each winding if it were time shared. When employing integrated circuits, however, it is often simpler to avoid time sharing and to use multiple components, the additional size and cost being nominal. 
     Although unnecessary to enable persons skilled in the art to make and use the present invention, a complete program for both open loop and closed loop positioning is annexed hereto as an Appendix since that constitutes the best mode contemplated by the applicant of carrying out the invention. 
     Although this invention has been described with respect to its preferred embodiments, it should be understood that many variations and modifications will now be obvious to those skilled in the art. Accordingly, the scope of the invention is limited, not by the specific disclosure herein, but only by the appended claims. 
     
                       APPENDIX______________________________________  Instruc-  tionMemory Mne-Location  monic    Mode    Opcode Comments______________________________________0400                    00     OPSELL0401                    04     OPSELH0402                    CF     STDEL0403                    00     POSCOM0404                    00     POSNOW0405                    00     DIRFLG0406                    00     OFFSET0407                    00     DELIND0408                    7F     INDLD0409                    1F     SENDEL040A                    FF     SENCNT040B                    08     SCMASK040C                    20     GOADRL040D                    05     GOADRH040E                    00     TWOFLG040F                    00     TWOPS 10410                    32     TWOPS 20411                    03     SEVIND0412                    FB     SEVPS 10413                    9A     SEVPS 20414                    90     SEVPS 30415                    50     SEVPS 40416                    13     SEVPS 50417                    09     SEVPS 60418                    00     SEVPS 70419                    7F     EXPDEL041A041B041C041D041E041F0420                    CC     Final Drive State 10421                    99     Final Drive State 20422                    33     Final Drive State 30423                    66     Final Drive State 40424                    04     Feedback Sensing                          Mask 10425                    08     Feedback Sensing                          Mask 20426                    01     Feedback Sensing                          Mask 30427                    02     Feedback Sensing                          Mask 40428                    04     Feedback Sensing                          Mask 10429                    03     2 Step Delay042A                    04     3 Step Delay 1042B                    03     3 Step Delay 2042C                    04     4 Step Delay 1042D                    05     4 Step Delay 2042E                    03     4 Step Delay 3042F                    04     5 Step Delay 10430                    05     5 Step Delay 20431                    06     5 Step Delay 30432                    03     5 Step Delay 40433                    04     6 Step Delay 10434                    05     6 Step Delay 20435                    06     6 Step Delay 30436                    07     6 Step Delay 40437                    03     6 Step Delay 50438                    04     7 Step Delay 10439                    05     7 Step Delay 2043A                    06     7 Step Delay 3043B                    07     7 Step Delay 4043C                    05     7 Step Delay 5043D                    03     7 Step Delay 6043E                    04     8 Step Delay 1043F                    05     8 Step Delay 20440                    06     8 Step Delay 30441                    07     8 Step Delay 40442                    07     8 Step Delay 50443                    04     8 Step Delay 60444                    03     8 Step Delay 70445                    29     Delay Address                          Offset 10446                    29     Delay Address                          Offset 20447                    2A     Delay Address                          Offset 30448                    2C     Delay Address                          Offset 40449                    2F     Delay Address                          Offset 5044A                    33     Delay Address                          Offset 6044B                    38     Delay Address                          Offset 7044C                    3E     Delay Address                          Offset 8044D                    B7     0 - OP Reset Counters044E                    C2     1 - OP Step Slow +044F                    CD     2 - OP Step Slow -0450                    D8     3 - OP Step Fast +0451                    E0     4 - OP Step Fast -0452                    E8     5 - OP Two Positions0453                    EB     6 - OP Seven Posi-                          tions0454                    EE     7 - OP Feedback On0455                    F6     8 - OP Feedback Off0456                    83     9 - OP Unused0457                    6C     Intermediate Drive                          State 1-F0458                    C9     Intermediate Drive                          State 2-F0459                    93     Intermediate Drive                          State 3-F045A                    36     Intermediate Drive                          State 4-F045B                    9C     Intermediate Drive                          State 1-R045C                    39     Intermediate Drive                          State 2-R045D                    63     Intermediate Drive                          State 3-R045E                    C6     Intermediate Drive                          State 4-R045F0460   LDA      IMM     A9     Initialization -                          Entry0461                    FF0462   STA      ABS     8D     Designate Port B -                          Outputs0463                    010464                    170465   LDA      IMM     A90466                    CC0467   STA      ABS     8D     Set Output - Final                          State 10468                    000469                    17046A   CLD      IMP     D8     Clear Decimal Mode046B   LDA      IMM     A9046C                    00046D   STA      ABS     8D     Designate Port A -                          Inputs046E                    03046F                    170470   STA      ABS     8D     Set IRQ L.S.B. = 000471                    FE0472                    170473   LDA      IMM     A90474                    1C0475   STA      ABS     8D     Set IRQ M.S.B. = 1C0476                    FF0477                    170478   LDY      IMM     A0     Initialize RAM                          1780 - 179F0479                    20047A   LDA      ABY     B9     Loop to load                          RAM from PROM047B                    00     Loop to load                          RAM from PROM047C                    04     Loop to load                          RAM from PROM047D   STA      ABY     99     Loop to load                          RAM from PROM047E                    80     Loop to load                          RAM from PROM047F                    17     Loop to load                          RAM from PROM0480   DEY      IMP     88     Loop to load                          RAM from PROM0481   BNE      REL     D0     Loop to load                          RAM from PROM0482                    F7     (-9) Loop to load                          RAM from PROM0483   LDA      IMM     A9     Monitor Entry -                          Display POSNOW0484                    7F0485   STA      ABS     8D     Initialize Display0486                    410487                    170488   LDX      IMM     A20489                    11048A   LDA      ABS     AD     Fetch POSNOW048B                    84048C                    17048D   LSR      IMP     4A     Shift 4X to display048E   LSR      IMP     4A     Upper byte048F   LSR      IMP     4A0490   LSR      IMP     4A0491   JSR      ABS     20     Jump to KIM display                          subroutine0492                    480493                    1F0494   LDA      ABS     AD     Fetch POSNOW0495                    840496                    170497   AND      IMM     29     Mask lower byte                          for display0498                    0F0499   JSR      ABS     20     Jump to KIM Display                          Routine049A                    48049B                    1F049C   STX      ABS     8E049D                    42049E                    17049F   LDA      IMM     A904A0                    0004A1   STA      ABS     8D     Turn off Display04A2                    4104A3                    1704A4   JSR      ABS     20     Jump to KIM                          Subroutine GETKEY04A5                    6A04A6                    1F04A7   CMP      IMM     C904A8                    0A04A9   BCS      REL     B0     Loop if key not 0-904AA                    D8     (-40) (Abs = 0483)04AB   NOP              EA04AC   NOP              EA04AD   TAX      IMP     AA     Transfer Key No. to                          index04AE   LDA      ABX     BD     Fetch lower byte                          of address04AF                    4D     for selected opera-                          tion04B0                    0404B1   STA      ABS     8D     Store in OPSELL04B2                    8004B3                    1704B4   JMP      IND     6C     Jump to selected                          operation04B5                    8004B6                    1704B7   LDA      IMM     A9     0 - OP Reset                          Counters04B8                    0004B9   STA      ABS     8D     Set POSCOM = 0-04BA   8304BB                    1704BC   STA      ABS     8D     Set POSNOW = 004BD                    8404BE                    1704BF   JMP      ABS     4C     Return to MONITOR04C0                    8304C1                    0404C2   LDA      IMM     A9     1 - OP Step Slow it04C3                    CF04C4   STA      ABS     8D     Set STDEL Maximum04C5                    8204C6                    1704C7   INC      ABS     EE     Add 1 to POSCOM04C8                    8304C9                    1704CA   JMP      ABS     4C     Go to STEPCT Routine04CB                    FB04CC                    0404CD   LDA      IMM     A9     2 - OP Step Slow -04CE                    CF04CF   STA      ABS     8D     Set STDEL Maximum04D0                    8204D1                    1704D2   DEC      ABS     CE     Subtract 1                          from POSCOM04D3                    8304D4                    1704D5   JMP      ABS     4C     Go to STEPCT Routine04D6                    FB04D7                    0404D8   LDA      IMM     A9     3 - OP Step Fast +04D9                    1804DA   STA      ABS     8D     Set STDEL Minimum04DB                    8204DC                    1704DD   JMP      ABS     4C     Finish with 1 - OP04DE                    C704DF                    0404E0   LDA      IMM     A9     4 - OP Step Fast -04E1                    1804E2   STA      ABS     8D     Set STDEL Minimum04E3                    8204E4                    1704E5   JMP      ABS     4C     Finish with 2 - OP04E6                    D204E7                    0404E8   JMP      ABS     4C     5 - OP Two Position04E9                    0504EA                    0604EB   JMP      ABS     4C     6 - OP Seven Position04EC                    1E04ED                    0604EE   LDA      IMM     A9     7 - OP Turn on                          Feedback04EF                    5B04F0   STA      ABS     8D     Load GOADRL04F1                    8C04F2                    1704F3   JMP      ABS     4C     Return to MONITOR04F4                    8304F5                    0404F6   LDA      IMM     A9     8 - OP Turn OFF                          Feedback04F7                    2004F8   JMP      ABS     4C     Finish with 7 - OP04F9                    FO04FA                    0404FB   LDA      ABS     AD     STEPCT Entry - Load                          POSCOM04FC                    8304FD                    1704FE   SEC      IMP     3804FF   SBC      ABS     ED     Subtract POSNOW0500                    840501                    170502   BEQ      REL     FO     OFFSET = 0? Exit0503                    19     (+25)0504   BCS      REL     BO     OFFSET + ?0505                    OC     (+12)0506   EOR      IMM     49     Complement0507                    FF0508   ADC      IMM     69     Correct0509                    01050A   LDX      IMM     A2050B                    FF050C   STX      ABS     8E     Set DIRFLG = -1050D                    85050E                    17050F   JMP      ABS     4C0510                    170511                    050512   LDX      IMM     A20513                    010514   STX      ABS     8E     Set DIRFLG = +10515                    850516                    170517   STA      ABS     8D     Store OFFSET0518                    860519                    17051A   JMP      IND     6C     Jump to Feedback or                          Non-feedback051B                    8C     Control Routine051C                    17051D   JMP      ABS     4C     Exit to Next                          Position Delay051E                    F7051F                    050520   CMP      IMM     C9     NON-FEEDBACK                          Entry - OFFSET &gt; 8?0521                    090522   BCS      REL     B0     Go to Long Move                          Routine0523                    15     (+21)0524   TAX      IMP     AA     Prepare index for                          DELIND fetch0525   LDA      ABX     BD     Fetch address of                          first delay0526                    440527                    040528   STA      ABS     8D     Store DELIND0529                    87052A                    17052B   JSR      ABS     20     Go to STEPS Sub-                          routine052C                    7F052D                    05052E   BEQ      REL     FO     Exit if OFFSET = 0052F                    ED     (-19)0530   JSR      ABS     20     Go to DELAY                          Subroutine0531   JSR      ABS     B20532                    050533   INC      ABS     EE     INCREMENT                          DELIND0534                    870535                    170536   JMP      ABS     4C     Loop until OFFSET                          = 00537                    2B0538                    050539   LDA      IMM     A9     Long Move Entry053A                    3E053B   STA      ABS     8D     Store DELIND = ini-                          tial                          value for 8                          step move053C                    87053D                    17053E   JSR      ABS     20     Go to STEPS Sub-                          routine053F                    7F0540                    050541   JSR      ABS     20     Go to DELAY Sub-                          routine0542                    B20543                    050544   INC      ABS     EE     Increment DELIND0545                    870546                    170547   LDA      ABS     AD     Load new DELIND0548                    870549                    17054A   CMP      IMM     C9     Midpoint Delay?054B                    41054C   BNE      REL     DO     Loop until midpoint                          delay reached054D                    FO     (-16)054E   JSR      ABS     20     Go to STEPS                          Subroutine054F                    7F0550                    050551   CMP      IMM     C9     4 Steps remaining?0552                    050553   BCC      REL     90     Do last 4 steps                          decrementing DELIND0554                    DB     (-37) offer each step                          Abs = 05300555   JSR      ABS     20     Go to DELAY                          Subroutine0556                    B20557                    050558   JMP      ABS     4C     Loop until 4 steps                          remain0559                    4E055A                    05055B   CMP      IMM     C9     Feedback Entry -                          OFFSET &gt; 2?055C                    03055D   BCC      REL     90     If OFFSET ≦ 2, switch                          to non-feedback055E                    C5     (-59) control routine055F   JSR      ABS     20     Go to STEPS                          Subroutine0560                    7F0561                    050562   CMP      IMM     C9     OFFSET = 2?0563                    020564   BEQ      REL     FO     Go to DECEL Routine0565                    06     (+6)0566   JSR      ABS     20     Go to DELSCN                          Subroutine0567                    C40568                    050569   JMP      ABS     4C     Loop until                          OFFSET = 2056A                    5F056B                    05056C   JSR      ABS     20     DECELERATION -                          Go to                          DELSCN. If input = 0                          return056D                    C4056E                    05056F   LDA      ABS     AD     Load SCMASK0570                    8B0571                    170572   AND      ABS     2D     AND SCMASK                          with Input0573                    020574                    170575   BEQ      REL     F0     Continue scanning                          until input = 10576                    F8     (-8)0577   JSR      ABS     20     Go to STEPS Subroutine0578                    7F0579                    05057A   BEQ      REL     F0     If OFFSET = 0, branch                          to Next Position Delay057B                    7B     (+123)057C   JMP      ABS     4C057D                    6C057E                    05057F   LDA      ABS     AD     STEPS Subroutine -                          load POSNOW0580                    840581                    170582   CLC      IMP     180583   ADC      ABS     6D     Use DIRFLG to modify                          POSNOW0584                    850585                    170586   STA      ABS     8D     Store new POSNOW0587                    840588                    170589   AND      IMM     29     Mask two lower hits058A                    03058B   LDY      ABS     AC     Test DIRFLG058C                    85058D                    17058E   BPL      REL     10     Branch if N = 0 or                          DIRFLG +058F                    03     (+3) If -, increase                          index by 40590   CLC      IMP     180591   ADC      IMM     69     Add 4 to index0592                    040593   TAX      IMP     AA     Final index0594   LDA      ABX     BD0595                    570596                    040597   STA      ABS     8D     Set Intermediate                          Output State0598                    000599                    17059A   LDA      ABS     AD     Load Exp. Delay Value059B                    99059C                    17059D   TAY      IMP     A8059E   DEY      IMP     88     Loop to Delay Start of059F   BNE      REL     D0     Synthesized Exponential05A0                    FD     (-3)05A1   TXA      IMP     8A05A2   AND      IMM     2905A3                    0305A4   TAX      IMP     AA     Prepare index for                          Final drive state05A5   LDA      ABX     BD05A6                    2005A7                    0405A8   STA      ABS     8D     Set Final Output State05A9                    0005AA                    1705AB   DEC      ABS     CE     Decrement OFFSET05AC                    8605AD                    1705AE   LDA      ABS     AD     Load new OFFSET05AF                    8605B0                    1705B1   RTS      IMP     6005B2   LDA      IMM     A9     DELAY Subroutine -                          load DELVAL05B3                    4005B4   SEC      IMP     3805B5   LDX      ABS     AE     Load DELIND05B6                    8705B7                    1705B8   LDY      ABS     AC     Load INDLD - Outer                          Delay Loop05B9                    8805BA                    1705BB   DEY      IMP     88     Inner Delay Loop05BC   BNE      REL     D0     Inner Delay Loop05BD                    FD     (-3) Inner Delay Loop05BE   SBC      ABX     FD05BF                    0005C0                    0405C1   BPL      REL     1005C2                    F5     (-11) Outer Delay Loop05C3   RTS      IMP     6005C4   LDX      ABS     AE     DELSCN Subroutine -                          Load SENDEL05C5                    8905C6                    1705C7   DEX      IMP     CA     Loop to Delay                          Scanning of Inputs05C8   NOP              EA     Loop to Delay                          Scanning of Inputs05C9   NOP              EA     Loop to Delay                          Scanning of Inputs05CA   BNE      REL     D0     Loop to Delay                          Scanning of Inputs05CB                    FB     (-5) Loop to Delay                          Scanning of Inputs05CC   LDA      ABS     AD     Fetch POSNOW05CD                    8405CE                    1705CF   AND      IMM     29     Mask 2 L.S.B.05D0                    0305D1   TAX      IMP     AA     Prepare tentative                          index05D2   LDY      ABS     AC05D3                    85     Test DIRFLG05D4                    17     If +, increase index                          by 105D5   BMI      REL     3005D6                    01     (+1)05D7   INX      IMP     E805D8   LDA      ABX     BD     Fetch SCMASK Value05D9                    2405DA                    0405DB   STA      ABS     8D     Store SCMASK05DC                    8B05DD                    1705DE   LDX      ABS     AE     Fetch SENCNT05DF                    8A05E0                    1705E1   LDY      IMM     A005E2                    FF05E3   LDA      ABS     AD     Load SCMASK05E4                    8B05E5                    1705E6   AND      ABS     2D     Read Input05E7                    0205E8                    1705E9   BEQ      REL     F0     Branch if Input = 0                          Take next step05EA                    OB     (+11)05EB   DEY      IMP     8805EC   BNE      REL     DO05ED                    F5     (-11)05EE   DEX      IMP     CA05EF   BNE      REL     DO05F0                    FO     (-16)05F1   PLA      IMP     68     Adjust Stock pointer                          in prep. to abort.                          subroutine05F2   PLA      IMP     68     Jump to Monitor05F3   JMP      ABS     4C     Jump to Monitor05F4                    8305F5                    0405F6   RTS      IMP     6005F7   LDY      IMM     AO     Next Position Delay -                          Entry 000005F8                    FF05F9   LDX      ABS     AE     Load STDEL05FA                    8205FB                    1705FC   DEX      IMP     CA05FD   BNE      REL     D005FE            FD      (-3)05FF   DEY      IMP     880600   BNE      REL     D00601                    F7     (-9)0602   JMP      ABS     4C     Jump to Monitor0603                    830604                    040605   LDX      IMM     A2     Two Position Routine -                          Entry 000E0606                    000607   CPX      ABS     EC     Is TWOFLG = 00608                    8E0609                    17060A   BEQ      IMP     F0060B                    05     (+5)060C   STX      ABS     8E     Set TWOFLG = 0060D                    8E060E                    17060F   BNE      IMP     D0     Unconditional0610                    D4     (+4)0611   INX      IMP     E8     Set X = 10612   STX      ABS     8E     Set TWOFLG = 10613                    8E0614                    170615   LDA      ABX     BD     Fetch next TWOPS, X0616                    8F0617                    170618   STA      ABS     8D     Store in POSCOM0619                    83061A                    17061B   JMP      ABS     4C     Go to STEPCT061C                    FB061D                    04061E   LDX      ABS     AE     Seven Position RoutineEntry 0027061F                    910620                    170621   LDA      ABX     BD     Fetch next value0622                    920623                    170624   STA      ABS     8D     Store in POSCOM0625                    830626                    170627   DEX      IMP     CA0628   BNE      REL     D0     Is SEVIND = 0?0629                    02062A   LDX      IMM     A2062B                    06062C   STX      ABS     8E     Set SEVIND = 6062D                    91062E                    17062F   JMP      ABS     4C     Go to STEPCT0630                    FB0631                    04______________________________________