Abstract:
A method for manufacturing a plurality or metal core substrates for a surface-mounted light emitting diode includes steps of adhering a pair of metal base plates and a plurality of insulation layers, adhering a pair of metal base plates interposing one of the insulation layers as a first insulation layer to form a set plate, stacking a plurality of set plates between a pair of guide plates, interposing a separation gap between adjacent set plates to form a set plate block, cutting the set plate block in a stacking direction to form a set plate aggregation, securing a second insulation layer to a cut surface of the set plate aggregation, securing a circuit pattern aggregation layer to the second insulation layer to form a metal core substrate aggregation, forming a separation groove on the circuit pattern aggregation layer between adjacent set plates, corresponding to the separation gap, forming a groove along a center line of the set plate to separate the set plate into first and second circuit pattern aggregations, forming electrodes on both sides of the substrate aggregation, separating the guide plates, and cutting off the substrate aggregation into independent substrates.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority from U.S. Provisional Patent Application Ser. No. 60/476,593, filed Jun. 6, 2003, which is incorporated by reference as if fully set forth herein.  
       FIELD OF THE INVENTION  
       [0002]     The present invention generally relates to receiver design in wireless communication systems. More particularly, the present invention relates to digital signal processing (DSP) techniques used to adjust gain and to compensate for direct current (DC) offset introduced into real and imaginary signal components processed by an analog radio receiver.  
       BACKGROUND  
       [0003]     In conventional receivers, an analog gain control (AGC) loop is used to measure the instantaneous power as well as the average power received by an analog-to-digital converter (ADC). Based on the average power, the gain of the analog circuitry is adjusted such that the input to the ADC will stay within its predetermined dynamic range. In such conventional receivers, gain is controlled by a feedback loop which causes an undesired delay when adjusting the gain.  
         [0004]     As shown in  FIG. 1 , a conventional radio frequency (RF) receiver  100  includes an analog radio receiver  102 , at least one analog-to-digital converter (ADC)  104 , and an analog gain control loop that measures the instantaneous power as well as the average power. The analog gain control loop includes a power estimator  106 , a loop filter  108  (e.g., an LPF), a summer  110 , a lookup table (LUT)  112 , a digital-to-analog converter (DAC)  114  and a gain control circuit  116 . The summer  110  adds a reference signal having a predetermined value −P ref  to the output of the loop filter. The error voltage at the output of the summer  110  becomes zero when the average input power reaches the value of P ref .  
         [0005]     The analog radio receiver  102  is a direct conversion receiver which includes an antenna  125  for receiving a wireless communication signal, a bandpass filter  130 , a low noise amplifier (LNA)  135 , an optional second filter  140  (e.g., bandpass filter), a demodulator  145  having two outputs  150 ,  155 , a phase-locked loop (PLL)  160 , an analog real signal path low pass filter (LPF)  165 A, an analog imaginary signal path LPF  165 B, at least one real signal path amplifier  170 A, at least one imaginary signal path amplifier  170 B, at least one analog real signal path high pass filter (HPF) circuit  175 A, and at least one analog imaginary signal path HPF circuit  175 B. Each of the amplifiers  170 A,  170 B, includes a high gain stage residing in the analog domain of the RF receiver  100 .  
         [0006]     The PLL  160  generates a local oscillator (LO) signal to control the two outputs  150 ,  155  of the demodulator  145 . The output  150  is an in-phase (I) output of the demodulator  145  for outputting a real signal component of the wireless communication signal. The output  155  is a quadrature (Q) output of the demodulator  145  for outputting an imaginary signal component of the wireless communication signal. The analog LPFs  165 A,  165 B, control the bandwidth selectivity of the I and Q outputs  150  and  155 , respectively. The outputs of the analog LPFs  165 A,  165 B, are then amplified by the amplifiers  170 A,  170 B, respectively.  
         [0007]     Due to high gain requirements, the analog HPF circuits  175 A,  175 B, are included in the analog radio receiver  102  to provide capacitance after each of the amplifiers  170 A,  170 B, respectively, whereby the amplifiers  170 A,  170 B, are AC-coupled and any residual direct current (DC) is removed to prevent DC offset. Each of the analog HPF circuits  175 A,  175 B, has a signal input, a signal output, at least one capacitor C 1 , C 2 , which connects the signal input to the signal output, and at least one resistor R 1 , R 2 , which connects the output of the capacitor to ground, thus forming an R-C filter. The analog HPF circuits  175 A,  175 B, alter the spectral shape (i.e., reducing the energy) of the lower portion (e.g., below 50 kHz) of the frequency domain response associated with the real and imaginary signal components.  
         [0008]     In the conventional RF receiver  100  of  FIG. 1 , the ADC  104  is connected to the output of the analog HPF circuits  175 A,  175 B. The analog HPF circuits  175 A,  175 B, are utilized to guarantee the spectral shape of the wireless communication signal received via the antenna  125  before being sampled at the ADC  104 . The ADC  104  outputs digital I and Q outputs  180 ,  185 , to the power estimator  106  which, for example, performs a function in which I 2 +Q 2  is calculated.  
         [0009]     In the RF receiver  100 , the reaction time necessary to adjust the gain of the amplifiers  170 A,  170 B, to respond to large changes in the gain of signals received at the antenna  125  is considerable. The gain adjustment of the amplifiers  170 A,  170 B, is based on a feedback loop which includes a power estimator  106 , a loop filter  108 , a summer  110 , look up table (LUT)  112 , a digital-to-analog converter (DAC)  114  and a gain control circuit  116 . A reference power (PREF) value is subtracted from the output of the loop filter via the summer  110  to generate an error signal  118 . Based on the error signal  118 , the LUT  112  sets the DAC  114  to a predetermined setting such that the gain control circuit  116  adjusts the gain of the amplifiers  170 A,  170 B accordingly. Furthermore, because the potential range of the input signal variation received at the antenna  125  of the analog radio receiver  102  may be very large (e.g., a 75 dB dynamic range), a very large capacity and expensive ADC  104  (e.g., having 13 bits whereby 6 dB dynamic range is provided per bit) is required. The ADC  104  will also consume considerable power.  
         [0010]     It is desirable to provide a method of addressing DC offset cancellation and gain control without the disadvantages addressed above.  
       SUMMARY  
       [0011]     The present invention is a digital baseband (DBB) receiver for receiving and processing a wireless communication signal. The DBB receiver includes at least one low noise amplifier (LNA), at least one demodulator, a direct current (DC) discharge circuit and an LNA control circuit. The LNA selectively amplifies the communication signal. The demodulator outputs analog real and imaginary signal components on real and imaginary signal paths, respectively, in response to receiving the communication signal from the LNA. The DC discharge circuit selectively discharges DC accumulating on at least one of the real and imaginary signal paths. The LNA control circuit turns the LNA on or off.  
         [0012]     The DBB receiver may further include a first high pass filter (HPF) circuit in communication with the real signal path and a second HPF circuit in communication with the imaginary signal path. Each of the first and second HPF circuits may include at least one capacitor, at least one resistor and at least one transistor in parallel with the resistor. Each transistor may be controlled by the DC discharge circuit to selectively flush accumulated DC from the respective capacitor to ground.  
         [0013]     Alternatively, each of the first and second HPF circuits may include at least one capacitor, at least one resistor and at least one switch in parallel with the resistor. Each switch may be controlled by the DC discharge circuit to selectively flush accumulated DC from the respective capacitor to ground.  
         [0014]     The DBB receiver may further include a first digital gain control circuit having an input in communication with the first HPF circuit, and a second digital gain control circuit having an input in communication with the second HPF circuit. The DBB receiver may further include a DC offset and normalization compensation module in communication with respective outputs of the first and second digital gain circuits, an input to the DC discharge circuit and an input to the LNA control circuit. The DC offset and normalization compensation module may be configured to maintain the output of the DBB receiver at a constant output power level. 
     
    
     BRIEF DESCRIPTION OF THE DRAWING(S)  
       [0015]     A more detailed understanding of the invention may be had from the following description of a preferred example, given by way of example and to be understood in conjunction with the accompanying drawing wherein:  
         [0016]      FIG. 1  is a block diagram of a conventional RF receiver including an analog radio receiver; and  
         [0017]      FIGS. 2A, 2B ,  2 C and  2 D, taken together, are a block diagram of a DBB RF receiver with a digital DC offset and normalization compensation module configured in accordance with a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]     Preferably, the method and system disclosed herein is incorporated into a wireless transmit/receive unit (WTRU). Hereafter, a WTRU includes but is not limited to a user equipment, mobile station, fixed or mobile subscriber unit, pager, or any other type of device capable of operating in a wireless environment. The features of the present invention may be incorporated into an integrated circuit (IC) or be configured in a circuit comprising a multitude of interconnecting components.  
         [0019]     The present invention is applicable to communication systems using time division duplex (TDD), time division multiple access (TDMA), frequency division duplex (FDD), code division multiple access (CDMA), CDMA  2000 , time division synchronous CDMA (TDSCDMA), and orthogonal frequency division multiplexing (OFDM). However, the present invention is envisaged to be applicable to other types of communication systems as well.  
         [0020]      FIGS. 2A, 2B ,  2 C and  2 D, taken together, illustrate the overall architecture of a digital baseband (DBB) receiver  200  operating in accordance with the preferred embodiment of the present invention. A mapping is used to normalize the input. The receiver  200  includes an analog radio receiver  202  (see  FIG. 2A ), a real signal path digital gain control circuit  205 A, an imaginary signal path digital gain control circuit  205 B, respective LPFs  245 A,  245 B, a digital direct current (DC) offset and normalization compensation module  300 , a DC-discharge flag circuit  250  and an LNA control circuit  275  (see  FIG. 2B ). The DC-discharge flag circuit  250  is used to flush out DC accumulated in the real and imaginary signal component paths when a predetermined threshold is exceeded. Furthermore, if the input power to the analog radio receiver  202  is very low, the LNA control circuit  275  turns on the LNA  135  and, if the input power to the analog radio receiver  202  is very high, the LNA control circuit  275  turns off the LNA  135 .  
         [0021]     In receiver  200 , full dynamic range is provided using a normalization process without the use of a DAC, such as the one used in the prior art system  100  illustrated in  FIG. 1 .  
         [0022]     As shown in  FIG. 2A , the analog radio receiver  202  is a direct conversion receiver which includes an antenna  125  for receiving a wireless communication signal, a bandpass filter  130 , an LNA  135 , an optional second filter  140  (e.g., bandpass filter), a demodulator  145  having two outputs  150 ,  155 , a PLL  160 , an analog real signal path LPF  165 A, an analog imaginary signal path LPF  165 B, at least one real signal path amplifier  170 A, at least one imaginary signal path amplifier  170 B, at least one analog real signal path high pass filter (HPF) circuit  175 A, and at least one analog imaginary signal path HPF circuit  175 B. Each of the amplifiers  170 A,  170 B, include a high gain stage residing in the analog domain of the analog radio receiver  202 . Each of the HPF circuits  175 A,  175 B, include at least one capacitor C 1 , C 2 , at least one resistor R 1 , R 2  and at least one transistor T 1 , T 2 , for selectively grounding the output of the respective capacitor C 1 , C 2 , to eliminate DC offsets accumulating thereof. Alternatively, one or more switches may be used to short the outputs of the capacitors C 1 , C 2 , of the HPF circuits  175 A,  175 B, to ground.  
         [0023]     As shown in  FIG. 2B , the digital DC offset and normalization compensation module  300  has a real signal input  305  connected to the real signal path digital gain control circuit  205 A via the LPF  245 A, and an imaginary signal input  310  connected to the imaginary signal path digital gain control circuit  205 B via the LPF  245 B. The digital DC offset and normalization compensation module  300  further includes real and imaginary compensated signal outputs  380 ,  390 . The digital DC offset and normalization compensation module  300  also outputs a DC estimation signal  392  for the real signal path  305 , a DC estimation signal  394  for the imaginary signal path  310 , and a magnitude estimation signal  396 . The DC estimation signals  392 ,  394  are received by the DC-discharge flag circuit  250  which, in turn, outputs a control signal when it is determined that DC on C 1  and C 2  in the analog radio receiver  202  shown in  FIG. 2A  should be dissipated. The magnitude estimation signal  396  is received by the LNA control circuit  275  which, in turn, outputs a control signal to turn on or off the LNA  135  in the analog radio receiver  202  shown in  FIG. 2A .  
         [0024]     Referring to  FIG. 2B , each of digital gain control circuits  205 A,  205 B, include a logarithmic amplifier  210 A,  210 B, or other amplifier with known compression characteristics for compressing the input analog signals received from analog radio receiver  202  from a wider dynamic range to a lower dynamic range. In other words, the logarithmic amplifiers  210 A,  210 B, apply a particular level of amplification to the analog real (I) and imaginary (Q) signal components in accordance with their amplitude. Each of the digital gain control circuits  205 A,  205 B, further includes an ADC  215 A,  215 B, a look up table (LUT)  220 A,  220 B, and a combiner  225 A,  225 B. The LUTs  220 A,  220 B, provide an anti-log function used to decompress the converted digital signals based on previously captured compression curve data. The ADCs  215 A,  215 B, digitize the outputs of the logarithmic amplifiers  210 A,  210 B, and provide the digitized outputs to the LUTs or anti-log functions  225 A,  225 B, in order to decipher the digital domain of the analog real and imaginary signal components. The outputs of the ADCs  215 A,  215 B, are converted to a linear scale by generating (2*n−1) bit signals. It may be necessary to add one or more additional gain stages before each logarithmic amplifier  215 A,  215 B, if the existing gain is not sufficient to promote saturation. The combiners  225 A,  225 B, combine the digitized outputs of the LUTs  220 A,  220 B, with sign bits  230 A,  230 B, provided by saturated outputs of the logarithmic amplifiers  210 A,  210 B, to generate a digital real signal component  235  and a digital imaginary signal component  240 . The sign bits  230 A,  230 B, are created from saturated outputs of logarithmic amplifiers  210 A,  210 B, respectively.  
         [0025]     The digital gain control circuits  205 A,  205 B, are used to compensate for channel loss variation and to support a large dynamic range of incoming signals (e.g., from −100 dBm to −25 dBm). The digital gain control circuits  205 A,  205 B, are also used to minimize the number of bits required for operating the ADCs  215 A,  215 B, and are designed to efficiently compensate for channel loss variation in an expeditious manner, without distorting the signal envelope. The digital gain control circuits  205 A,  205 B, have a linear response, in dB-per-volt. In a closed loop system, the digital gain control circuits  205 A,  205 B, are used to maintain functions such as stability, settling time, overshoot, etc.  
         [0026]      FIG. 2C  shows the architecture for the digital DC offset and normalization compensation module  300 . The digital DC offset and normalization compensation module  300  includes real and imaginary signal component inputs  305 ,  310 , adders  315 ,  320 ,  325 ,  330 , multipliers  335 ,  340 , delay units  345 ,  350 , DC estimators  355 ,  360 , absolute power estimator  365 , magnitude estimator  370  and inverse function unit  375 . The real (I) signal component input  305  is connected to an input of the delay unit  345 , the DC estimator  355  and the summer  315 . The imaginary (Q) signal component input  310  is connected to an input of the delay unit  350 , the DC estimator  360  and the summer  320 .  
         [0027]     The DC estimator  355  outputs a signal  392  to an input of the summers  315 ,  325 , and to the DC-discharge flag circuit  250 . The summer  325  subtracts the signal  392  from a delayed real signal component  348  outputted by the delay unit  345  and outputs a resulting real signal  328  free of a DC offset. The DC estimator  360  outputs a signal  394  to an input of the summers  320 ,  330 , and to the DC-discharge flag circuit  250 . The summer  330  subtracts the signal  394  from a delayed real signal component  352  outputted by the delay unit  350  and outputs a resulting imaginary signal  332  free of a DC offset. Each of the DC estimators  355 ,  360  take a substantial amount of time to converge. Thus the delay units  355 ,  360 , are used to compensate for the delay in generating an estimation of the DC level on the real and imaginary signal component inputs  305 ,  310 , respectively.  
         [0028]     When the signal  392  indicates that the DC level on the real (I) or imaginary (Q) signal component inputs  305 ,  310 , exceeds a predetermined value, the DC-discharge flag circuit causes the transistors T 1 , T 2 , in the analog radio receiver  202  to discharge any DC stored in the capacitors C 1 , C 2 .  
         [0029]     In one embodiment, switches may be substituted for the transistors T 1 , T 2 , used in the analog radio receiver  202  whereby any DC stored in the capacitors C 1 , C 2  is selectively discharged to ground. In another embodiment, when the present invention is implemented by a time-slotted system (e.g., TDD, TDMA), the discharge of the capacitors C 1  and C 2  only takes place during a guard period which occurs between time slots, such that the transmission of data is not interfered with.  
         [0030]     Still referring to  FIG. 2C , the output of the DC estimator  355  is subtracted from the real (I) signal component input  305  via the summer  315  which outputs a result  318  to the absolute power estimator  365 . The output  368  of the DC estimator  360  is subtracted from the imaginary (Q) signal component input  310  via the summer  320  which outputs a result  322  to the absolute power estimator  365  which performs a function based on the results  318  and  322  (e.g., {square root}{square root over (I 2 +Q 2 )}). The output of the absolute power estimator is fed to the magnitude estimator which outputs an averaged magnitude estimation signal  396  (e.g., E(|{square root}{square root over (I 2 +Q 2 )}|)) to the LNA control circuit  275  and to the inverse function unit  375  which determines the inverse of the estimated power (e.g., 1/E(|{square root}{square root over (I 2 +Q 2 )}|)) such that the output power is maintained at a constant level.  
         [0031]     The inverse function unit  375  outputs inverse power estimation signals  376 ,  378 , to respective inputs of the multipliers  335 ,  340 . The multiplier  335  multiplies the resulting signal  328  by the signal  376  to provide a compensated real signal component output  380 . The multiplier  340  multiplies the resulting signal  332  by the signal  376  to provide a compensated imaginary signal component output  380 .  
         [0032]      FIG. 2D  shows the architecture for the DC-discharge flag circuit  250 . The DC-discharge flag circuit  250  includes real and imaginary magnitude detectors  255 ,  260 , a DC power estimator  265  and a comparator  270  which compares the output of the DC power estimator with a predetermined threshold K 1 . The comparator  270  selectively outputs a control signal causing switches S 1  and S 2  in the analog radio receiver  202  to close when the output of the DC power estimator exceeds the predetermined threshold K 1 .  
         [0033]     While this invention has been particularly shown and described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention described hereinabove.