Abstract:
The data transmission device including: a data bus sense amp controlled according to a control signal which is a pulse signal, for detecting and amplifying a data applied to a data bus; a plurality of driving units for buffering and outputting an output from the data bus sense amp; a read data line for receiving a pulse data transmitted by the plurality of driving units; a plurality of pull-down units controlled according to an output signal from the plurality of driving units, for performing a pull-down operation on the read data line; a plurality of multi-delay units controlled according to a detection signal detecting a period of an externally-inputted clock signal, for delaying the pulse data applied to the read data line for a different delay time; and a pull-up unit controlled according to an output signal from the plurality of multi-delay units, for resetting the data line. According to the data transmission device, a pulse width of the data line is controlled according to a clock period by using as a control signal an output signal from a pulse generating device in order to prevent a mis-operation in a high frequency operation, and reduce noise generation in a low frequency operation by differently controlling a pulse width of signals generated in the high and low frequency operations.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a data transmission device using a pulse generating device, and in particular to an improved data transmission device which can prevent a mis-operation in a high speed operation, and reduce noise generation in a low speed operation, by detecting a period of an externally-inputted clock signal, and controlling a pulse width of a pulse signal generated in a device according to the period. 
     2. Description of the Background Art 
     In general, a synchronous dynamic random access memory (DRAM) controls an input/output of a data, synchronized with an externally-inputted clock signal CLK, and thus internal signals are regularly generated according to the clock signal. 
     FIG. 1 is a circuit diagram illustrating a conventional data transmission device. As shown therein, the data transmission device includes: a data bus line sense amp  2  operated according to a data sense amp enable signal EN which is a pulse signal having a predetermined pulse width; first and second inverters IN 1 , IN 2  respectively inverting outputs from the data bus line sense amp  2 ; first and second pull-down drivers  4 ,  6  respectively performing a pull-down operation on read data lines RD, /RD according to outputs from the first and second inverters IN 1 , IN 2 ; first and second delay units DE 1 , DE 2  respectively delaying pulse data from the read data lines RD, /RD for a predetermined time; first and second pull-up drivers  8 ,  10  controlled according to outputs from the first and second delay units DE 1 , DE 2 , for respectively resetting the read data lines RD, /RD at a high level after a predetermined time from the time when the pulse data are applied to the read data lines RD, /RD; and a data output unit  12  buffering and externally outputting the data applied to the read data lines RD, /RD. 
     The data output unit  12  consists of a third inverter INV 3  and a fourth inverter INV 4  which are connected to the read data lines RD, /RD, respectively. 
     Here, the data bus sense amp enable signal EN which is an internal pulse signal having a predetermined pulse width is generated by a conventional pulse generating device as shown in FIG. 2 a  or  2   b.    
     That is, the pulse generating device includes: a delay unit DE delaying the externally-inputted clock signal CLK for a predetermined time; and a NAND gate ND or a NOR gate NOR generating a pulse signal by NANDing or NORing an output signal from the delay unit DE and the clock signal CLK, thereby outputting an internal pulse signal EN having a predetermined pulse width. 
     However, a pulse width of a signal generated by the pulse generating device is determined according to the delay time of the delay unit DE, and thus the pulse generating device generates a pulse signal having a pulse width as long as the delay time. 
     The operation of the conventional data transmission device will now be explained. 
     The data applied to local data bus lines LDB, /LDB are inputted to the data bus line sense amp  2 . When the data bus line sense amp  2  is operated according to the data bus line sense amp enable signal EN, and outputs an output signal, the pull-down drivers  4 ,  6  are driven by the output signal, thereby transmitting the pulse data to the read data lines RD, /RD. 
     The data applied to the read data lines RD, /RD drive the succeeding pull-up drivers  8 ,  10  after a predetermined delay time, thereby resetting the read data lines RD, /RD. 
     The conventional data transmission device has a disadvantage in that the delay time of the delay units DE 1 , DE 2  controlling the pull-up drivers  8 ,  10  is fixed, and thus the pulse width of the pulse signal outputted through the read data lines RD, /RD is also fixed. 
     Accordingly, when the delay time is set longer in a high frequency operation, if data having an identical phase are consecutively inputted, a margin between two pulse data signals is not obtained, thus causing a mis-operation that the data line is not resetted. 
     In addition, in case the delay time is too short in a low frequency operation, although an operational speed is low, a large amount of current is consumed for a short time in the data transmission, and thus a noise is generated. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a data transmission device which can selectively transmit a data signal according to a high/low frequency by detecting a period of a clock signal, and receiving as a control signal an output signal from a pulse generating device controlling a pulse width according to the period. 
     In order to achieve the above-described object of the present invention, there is provided a data transmission device including: a data bus sense amp controlled according to a control signal which is a pulse signal, for detecting and amplifying a data applied to a data bus; a plurality of driving units for buffering and outputting an output from the data bus sense amp; a read data line receiving a pulse data transmitted by the plurality of driving units; a plurality of pull-down units controlled according to an output signal from the plurality of driving units, for performing a pull-down operation on the read data line; a plurality of multi-delay units controlled according to a detection signal detecting a period of an externally-inputted clock signal, for delaying the pulse data applied to the read data line for a different delay time; and a pull-up unit controlled according to an output signal from the plurality of multi-delay units, for resetting the data line. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: 
     FIG. 1 is a circuit diagram illustrating a conventional data transmission device; 
     FIGS. 2 a  and  2   b  are circuit diagrams illustrating a conventional pulse generating device, respectively; 
     FIG. 3 is a circuit diagram illustrating a data transmission device in accordance with the present invention; 
     FIGS. 4 a  and  4   b  are detailed circuit diagrams respectively illustrating a multi-delay unit and a pull-up unit in accordance with the present invention; 
     FIGS. 5 a  and  5   b  are operational timing diagrams of the data transmission device in accordance with the present invention, in a state where a data length is 4; 
     FIG. 6 is a detailed block diagram illustrating a clock period detector in the configuration of FIG. 3; 
     FIG. 7 is a circuit diagram illustrating a pulse width detector in the configuration of FIG. 6, in a state where a high frequency clock signal is inputted; 
     FIGS. 8 a  and  8   b  are operational timing diagrams of a clock period detector in the configuration of FIG. 7; 
     FIG. 9 is a circuit diagram illustrating the pulse width detector in the configuration of FIG. 6, in a state where a low frequency clock signal is inputted; 
     FIGS. 10 a  and  10   b  are operational timing diagrams of a clock period detector in the configuration of FIG. 9; and 
     FIGS. 11 a  and  11   c  are detailed circuit diagrams illustrating examples of a pulse width controller in the configuration of FIG.  3 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 is a detailed circuit diagram illustrating a data transmission device in accordance with the present invention. As shown therein, the data transmission device includes: a data bus line sense amp  22  controlled and operated according to a data sense amp enable signal CON which is a pulse signal; first and second inverters IN 11 , IN 12  inverting potentials of each output terminal of the data bus line sense amp  22 ; pull-down drivers  24 ,  26  respectively performing a pull-down operation on read data lines RD, /RD according to outputs from the first and second inverters IN 11 , IN 12 ; first and second delay units DE 11 , DE 12  respectively delaying the data applied to the read data lines RD, /RD by controlling a delay time according to a control signal DET; pull-up drivers  28 ,  29  respectively controlled according to outputs from the first and second delay units DE 11 , DE 12 , for resetting the read data lines RD, /RD at a high level after a predetermined time from the time when a pulse data is applied to the read data lines RD, /RD; and a data output unit  32  buffering and externally outputting the data applied to the read data lines RD, /RD. 
     Here, the data bus line sense amp  22  is a general cross-coupled latch type sense amp, and thus an explanation thereof will be omitted. 
     The first and second delay units DE 11 , DE 12  respectively include: first and second delay units DEL 1 , DEL 2  respectively delaying the pulse data applied to the read data lines RD, /RD for a different delay time; and first and second transmission gates TG 1 , TG 2  controlled according to the control signal DET and an inverted signal /DET of the control signal DET by the inverter INV 1 , for respectively selectively outputting the outputs from the first and second delay units DEL 1 , DEL 2 . 
     The first and second pull-up drivers  28 ,  29  respectively include first and second PMOS transistors PM 1 , PM 2  controlled according to the outputs from the first and second transmission gates TG 1 , TG 2  of the first and second delay units DEL 1 , DEL 2 , for resetting the read data lines RD, /RD at a high level by performing the pull-up operation thereon. In addition, the first and second pull-up drivers  28 ,  29  may include a PMOS transistor controlled according to a potential of a node which commonly connects the outputs from the first and second transmission gates TG 1 , TG 2  of the first and second delay units DE 11 , DE 12 , for resetting the read data lines RD, /RD at a high level by carrying out the pull-up operation thereon. 
     FIG. 4 a  is a circuit diagram illustrating a second example of the first and second delay units DE 11 , DE 12 . As shown therein, the first and second delay units DE 11 , DE 12  include: a first NOR gate NOR 1  NORing the control signal DET and the pulse data applied to the read data lines RD, /RD; a second NOR gate NOR 2  NORing the inverted signal /DET of the control signal DET by the first inverter INV 11  and the pulse data applied to the read data lines RD, /RD; first and second delay units DEL 11 , DEL 12  respectively delaying the outputs from the first and second NOR gates NOR 1 , NOR 2  for a different time; and second and third inverters INV 12 , INV 13  respectively inverting the outputs from the first and second delay units DEL 11 , DEL 12 . 
     Here, in case the example as shown in FIG. 4 a  is employed, the first and second pull-up drivers  28 ,  29  include first and second PMOS transistors MP 11 , MP 12  respectively controlled according to the outputs from the first and second inverters INV 12 , INV 13  of the delay unit DEL 11 , for resetting the read data lines RD, /RD at a power supply voltage VCC by the pull-up operation. 
     FIG. 4 b  is a circuit diagram illustrating a third example of the first and second delay units DE 11 , DE 12 . As shown therein, the first and second delay units DE 11 , DE 12  include: a first NOR gate NOR 11  NORing the control signal DET and the pulse data applied to the read data line RD; a second NOR gate NOR 12  NORing the inverted signal /DET of the control signal DET by the first inverter INV 11  and the pulse data applied to the read data line RD; first and second delay units DEL 111 , DEL 112  respectively delaying the outputs from the first and second NOR gates NOR 11 , NOR 12  for a different time; and a third NOR gate NOR 13  NORing the outputs from the first and second delay units DEL 111 , DEL 112 . 
     The operation of the data transmission device in accordance with the present invention will now be explained. 
     Firstly, in a high frequency operation, a period of an externally-inputted clock signal is shorter than that of a reference clock signal. Thus, it is presumed that the control signal DET is at a low level. When the data bus line sense amp enable signal CON is applied, the pull-down driver  24  is driven, and thus the pulse data is applied to the data line. The pulse data signal passes through the first delay unit DEL 1  having a relatively short delay time, and drives the pull-up drivers  28 ,  29  after a predetermined delay time DT 1 , thereby resetting the data lines RD, /RD. 
     Conversely, in a low frequency operation, a period of the externally-inputted clock signal is longer than that of the reference clock signal. Thus, it is presumed that the control signal DET is at a high level. When the data bus line sense amp enable signal CON is applied, in the same manner, the pull-up drivers  28 ,  29  are driven after a predetermined delay time DT 2  according to a signal transmitted through the second delay unit DEL 12  having a relatively long delay time DT 2 . At this time, the data lines are resetted. 
     As described above, a speed of resetting the data line is controlled according to the frequency, thereby narrowing the pulse width of the transmitted data signal in the high frequency operation, and widening it in the low frequency operation. 
     FIGS. 5 a  and  5   b  are operational timing diagrams of the data transmission device in accordance with the present invention, in a state where a data length is 4. The delay used by the data lines RD, /RD in the high speed operation is constantly fixed, and thus the data lines RD, /RD are operated to be resetted at the same time (FIG. 5 a ). In the low speed operation, the delay unit has a different delay time in regard to each data line, and thus the data lines are resetted at a different timing (FIG. 5 b ). As a result, a noise is reduced. 
     FIG. 6 is a detailed block diagram illustrating the clock period detector  40  generating the control signal DET. As shown therein, the clock period detector  40  includes: a clock buffer  42  buffering the externally-inputted clock signal having a transistor-transistor logic (TTL) level, and converting it into a signal BUF having a CMOS level suitable for an internal operation of the memory device; a ½ divider  44  generating a signal DIS having a double period of a period of the output signal BUF from the clock buffer  42 ; and a pulse width detector  46  controlled according to a power-up signal PWRUP, for comparing an output signal DIV from the ½ divider  44  with a reference pulse width, and outputting the detection signal DET detecting a pulse width of the output signal DIV from the ½ divider  44 . 
     Here, the clock buffer  42  and the ½ divider  44  in the clock period detector  40  have been publicly known, and thus an explanation thereof will be omitted. 
     FIG. 7 is a circuit diagram illustrating the pulse width detector  46  used when the high frequency clock signal CLK is inputted. As shown therein, the pulse width detector.  46  includes: a first delay unit DEL 21  delaying the output signal DIV from the ½ divider  44  for a predetermined time TD 1 ; a second delay unit DEL 22  delaying an output from the first delay unit DEL 21  for a predetermined time TD 2 ; a first NAND gate ND 21  NANDing an output signal NET 1  from the first delay unit DEL 21  and an output signal NET 2  from the second delay unit DEL 22 , and outputting a low enable pulse signal NOD 1 ; a first NOR gate NOR 21  NORing the output signal NOD 1  from the first NAND gate ND 21  and the output signal DIV from the ½ divider  44 ; a first inverter INV 21  inverting an output from the first: NOR gate NOR 21 , and outputting a pulse signal NOD 2 ; a second inverter INV 22  inverting the power-up signal PWRUP; a first PMOS transistor PM 21  and a first NMOS transistor NM 21  respectively controlled according to the output signal NOD 2  from the first inverter INV 21  and an output signal from the second inverter INV 22 , and connected in series between the power supply voltage VCC and the ground voltage VSS; and third and fourth. inverters INV 23 , INV 24  having their input/output terminals connected to output the detection signal DET by latching a potential at a commonly-connected drain of the first PMOS transistor PM 21  and the first NMOS transistor NM 21 . 
     At this time, as illustrated in FIG. 8 a,  in the case that a high potential width of the output signal NOD 1  from the first NAND gate ND 21  of the pulse width detector  46  is smaller than a sum of the delay time TD 1  of the first delay unit DEL 21  and the delay time TD 2  of the second delay unit DEL 22 , the output signal NOD 2  from the first inverter INV 1  is a low enable pulse signal identical to the output signal NOD 1  from the first NAND gate ND 1 . Thereafter, the output signal DET from the pulse width detector  46  is transited from high to low because the output signal NOD 2  from the first inverter INV 21  which is the low enable pulse signal turns on the first PMOS transistor PM 21 , and supplies the power supply voltage to the third and fourth inverters INV 23 , INV 24 . 
     On the other hand, as shown in FIG. 8 b,  when a high potential width of the output signal NOD 1  from the first NAND gate ND 21  of the pulse width detector  46  is greater than the sum of the delay time TD 1  of the first delay unit DEL 21  and the delay time TD 2  of the second delay unit DEL 22 , although the output signal NOD 1  from the first NAND gate ND 21  generates a low pulse, the output signal NOD 2  from the first inverter INV 21  maintains a high level because the output signal DIV from the ½ divider  44  constantly maintains a high level. Accordingly, the output signal DET from the pulse width detector  46  maintains a high level latched at an initial state. 
     FIG. 9 is a circuit diagram illustrating another example of the pulse width detector  46  used when the low frequency clock signal CLK is inputted. As shown therein, the pulse width detector  46  includes: a first delay unit DEL 211  delaying the output signal DIV from the ½ divider  44  for a predetermined time TD 1 ; a second delay unit DEL 212  delaying an output from the first delay unit DEL 211  for a predetermined time TD 2 ; a first NAND gate ND 211  NANDing the output signal NET 1  from the first delay unit DEL 211  and the output signal NET 2  from the second delay unit DEL 212 ; a first inverter INV 211  inverting an output from the NAND gate ND 211 , and outputting a high enable pulse signal NOD 11 ; a second NAND gate ND 212  NANDing the output signal NOD 11  from the first inverter INV 211  and the output signal DIV from the ½ divider  44 , and outputting a pulse signal NOD 12 ; a second inverter INV 212  inverting the power-up signal PWRUP; a first PMOS transistor PM 211  and a first NMOS transistor NM 211  respectively controlled according to the output signal NOD 12  from the second NAND gate NAND 212  and an output signal from the second inverter INV 212 , and connected in series between the power supply voltage VCC and the ground voltage VSS; and third and fourth inverters INV 213 , INV 214  having their input/output terminals connected to output the detection signal DET by latching a potential at a commonly-connected drain of the first PMOS transistor PM 211  and the first NMOS transistor NM 211 . 
     At this time, as depicted in FIG. 10 a,  in the case that a high potential width of the output signal NOD 11  from the first inverter INV 211  of another example of the pulse width detector  46  as shown in FIG. 9 is smaller than a sum of the delay time TD 1  of the first delay unit DEL 211  and the delay time TD 2  of the second delay unit DEL 212 , although the output signal NOD 11  from the first inverter INV 211  generates a high pulse, the output signal NOD 12  from the second NAND gate ND 212  maintains a high level because the output signal DIV from the ½ divider  44  constantly maintains a high level. Accordingly, the output signal DET from the pulse width detector  46  maintains a high level latched at an initial state. 
     On the other hand, as shown in FIG. 10 b,  in case a high potential width of the output signal NOD 11  from the first inverter INV 211  of another example of the pulse width detector  46  as shown in FIG. 9 is greater than the sum of the delay time TD 1  of the first delay unit DEL 211  and the delay time TD 2  of the second delay unit DEL 212 , the output signal NOD 12  from the second NAND gate ND 212  is a low enable pulse signal transited at an identical point to the output signal NOD 11  from the first inverter INV 211 . Thereafter, the output signal NOD 12  from the second NAND gate ND 212  which is the low enable pulse signal turns on the first PNOS transistor PN 21 , thereby supplying the power supply voltage VCC to the third and fourth inverters INV 213 , INV 214 . As a result, the output signal DET from the pulse width detector  46  is transited from high to low. 
     FIG. 11 a  is a detailed circuit diagram illustrating a first example of the pulse width controller  50 . As shown therein, the pulse width controller  50  includes: a first delay unit DE 21  delaying the externally-inputted clock signal CLK for a predetermined time; a second delay unit DE 22  delaying the clock signal CLK for a predetermined time; a first inverter IN 21  inverting the output signal DET from the clock period detector  40 ; first and second transmission gates TG 21 , TG 22  controlled according to the output signal DET from the clock period detector  40  and the inverted signal /DET thereof, for respectively selectively transmitting outputs from the first and second delay units DE 21 , DE 22 ; and a NAND gate ND 211  NANDing the input signal CLK and an output from the first delay unit DE 21  or the second delay unit DE 22  selectively transmitted by the first transmission gate TG 21  or the second transmission gate TG 22 , and outputting the output signal CON. 
     Here, as depicted in FIG. 11 b,  the NAND gate ND 211  may be replaced by a NOR gate NOR 221 . 
     The pulse width controller  50  selectively transmits the two outputs from the delay unit having a different delay time by employing the transmission gate controlled according to the output signal DET from the clock period detector  40 . Accordingly, the pulse width can be selectively used by distinguishing whether the period of the externally-inputted clock signal CLK is longer or shorter than that of the reference clock signal. 
     In addition, FIG. 11 c  illustrates another example of the pulse width controller  50 . A pulse signal PUL that has been already generated in the semiconductor memory device is employed, and therefore the pulse width can be selectively used by distinguishing whether the period of the externally-inputted clock signal CLK is longer or shorter than that of the reference clock signal. As shown therein, the pulse width controller  50  includes: a delay unit DE 31  delaying the pulse signal PUL that has already been generated inside for a predetermined time; a NAND gate ND 31  NANDing an output from the delay unit DE 31  and the pulse signal PUL; and first and second transmission gates TG 31 , TG 32  controlled according to the output signal DET from the clock period detector  40  and the inverted signal /DET thereof, for respectively selectively transmitting the pulse signal PUL and an output from the NAND gate ND 31 , and outputting the output signal CON. 
     As discussed earlier, in accordance with the present invention, the data transmission device using the pulse generating device controls the pulse width of the signal according to the period of the externally-inputted clock signal, thereby reducing possibility of a mis-operation in the high frequency operation, preventing excessive current consumption in the low frequency operation, and minimizing noise generation. 
     As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.