Abstract:
The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a dynamic random access memory and in particular to an electrostatic discharge structure of a dynamic random access memory. 
         [0003]    2. Description of the Related Art 
         [0004]    For a dynamic random access memory (hereinafter referred to as DRAM), the data storage status is determined by charging or discharging of the array of capacitors on the semiconductor substrate. In general, charging status of a capacitor is represented as “1”, and discharging status of a capacitor is represented as “0”. If operating voltage and upper/lower electrode plate dielectric constant is fixed, the amount of storage charges is determined by the surface area of the capacitors in DRAM. 
         [0005]    Ordinarily, a DRAM has an electrostatic discharge (hereinafter referred to as ESD) region between a periphery region and a device region. The ESD region prevents electrostatic charges from interrupting operations or damaging the DRAM. In general, higher ESD resistance results in less current produced by electrostatic discharge, such that the circuit is protected from large instantaneous electrostatic charges. Reducing the contact area between the plug and the substrate to increase electrostatic resistance without enhancing the plug aspect ratio, and simultaneously improving the mechanism strength of the ESD region are major objectives in the field. 
       SUMMARY OF THE INVENTION 
       [0006]    The invention provides a method for manufacturing a method for manufacturing an electrostatic discharge structure, comprising the steps of providing a substrate having an electrostatic discharge region, wherein the electrostatic discharge region has a plurality of conductive structures; forming an interlayer dielectric layer on top of the substrate; forming a contact hole in the interlayer dielectric layer to exposes part of the substrate, wherein the contact hole is formed between each two of the conductive structures; and forming a conductor in the contact hole and on the top surface of the interlayer dielectric layer, wherein the conductor electrically connects to the substrate. 
         [0007]    The invention also provides an electrostatic discharge structure, comprising a substrate having a plurality of conductive structures thereon; an interlayer dielectric layer formed on the substrate, wherein the interlayer dielectric layer has a contact hole between the conductive structures to expose part of the substrate; a sacrificial layer formed in a lower portion of the contact hole; and a conductor in an upper portion of the contact hole and overlying the top surface of the interlayer dielectric layer. 
         [0008]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The invention can be more fully understood by reading the subsequent detailed description and embodiments with references made to the accompanying drawings, wherein: 
           [0010]      FIGS. 1A-1H  show serial cross sections of manufacturing a DRAM with an electrostatic discharge structure in a comparative embodiment of the invention; and 
           [0011]      FIGS. 2A-2H  show serial cross sections of manufacturing a DRAM with an electrostatic discharge structure in an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0012]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0013]      FIGS. 1A-1H  show serial cross sections of manufacturing a DRAM with an electrostatic discharge structure in a comparative embodiment of the invention. 
         [0014]    As shown in  FIG. 1A , a semiconductor substrate  10  is provided. The semiconductor substrate is separated into a device region  1 A and an ESD region  1 B. A gate oxide layer  11 , a polysilicon layer  13 , a metal silicide layer  15 , and a hard mask layer  17  are subsequently formed on the substrate  10 . These stacked layers are then patterned by a lithography process to form conductive structures  101  in the device region  1 A and conductive structures  103  in the ESD region  1 B. The conductive structures  101  are so-called word lines. 
         [0015]    As shown in  FIG. 1B , a silicon oxide layer  19  is then comfortably formed on the device region  1 A and ESD region  1 B. 
         [0016]    As shown in  FIG. 1C , a sacrificial polysilicon layer  21  is blanketly deposited over the silicon oxide layer  19 . After planarizing the top surface of the sacrificial polysilicon layer  21 , a mask layer  23  is formed overlying the planarized top surface. Subsequently, a patterned photoresist layer  25  is formed to selectively cover the predetermined position for the later formed plugs. 
         [0017]    As shown in  FIG. 1D , the mask layer  23  and the sacrificial polysilicon layer  21  not protected by the patterned photoresist layer  25  are then removed. 
         [0018]    As shown in  FIG. 1E , the mask layer  23  and the silicon oxide layer  19  in lateral direction are removed with part of the mask layer  23  remaining, wherein the silicon oxide layer  19  serve as side spacers of the conductive structures  101  and  103 . Subsequently, a silicon oxide layer  27  is comfortably formed on the described structure. 
         [0019]    As shown in  FIG. 1F , an interlayer dielectric layer  29  is blanketly formed on the silicon oxide layer  27 . A chemical mechanical polish (hereinafter CMP) is performed until exposing the sacrificial polysilicon layer  21 . 
         [0020]    As shown in  FIG. 1G , the sacrificial polysilicon layer  21  is removed, and the silicon oxide layer  19  in lateral direction is removed by anisotropic etching such as dry etch. After the processes as shown in  FIGS. 1A-1G , the device region  1 A has a bit line contact hole  31 , and the ESD region  1 B has a contact hole  33 . 
         [0021]    As shown in  FIG. 1H , a metal layer  35  is filled into the bit line contact hole  31  and contact hole  33  to form plugs  37  and  39  and covered on the interlayer dielectric layer  29 . The metal layer  35  is then planarized and patterned to form bit lines. 
         [0022]    The plug  39  in the ESD region  1 B has several defects as described below. First, the contact area between the plug  39  and the substrate  10  is similar to the opening area of the plug  39 . If a smaller contact area is desired, the opening should be correspondingly be reduced and therefore increasing the aspect ratio of the plug  39 . High aspect ratio of the plug  39  makes filling in of the metal layer  39  more difficult, resulting in possible effects such as void, thus, degrading device performance. 
         [0023]      FIGS. 2A-2H  show serial cross sections of manufacturing a DRAM with an electrostatic discharge structure in an embodiment of the invention. As shown in  FIG. 2A , a semiconductor substrate  50  is provided. The semiconductor substrate can be silicon, silicon on insulator (SOI), germanium silicide, germanium, or the like. In some embodiments of the invention, the substrate  50  is preferably silicon. Similar to the structure in  FIG. 1A , the substrate  50  in  FIG. 2A  is separated into a device region  5 A and an ESD region  5 B. 
         [0024]    A gate oxide layer  51  is then formed on the semiconductor substrate  50 . The formation of the gate oxide layer  51  can be divided into two processes, the thermal oxide growth with silicon consumption and the oxide deposition without silicon consumption. The former process places the substrate in oxygen-containing gas to form an oxide layer on the substrate surface. Because the oxide formation consumes silicon, this process is categorized as consumption type oxide growth. The latter process mixes silicon-containing gas and oxygen-containing gas to form silicon oxide on the silicon substrate surface. Subsequently, a polysilicon layer  53  is deposited on the gate oxide layer  51  surface. The general deposition is low temperature chemical vapor deposition (LPCVD). A metal layer (not shown) is deposited on the polysilicon layer  53  and then reacted with the underlying polysilicon layer  53  in high temperature to form a metal silicide layer  55 . The un-reacted metal layer is removed. Suitable metal layer includes nickel, cobalt, tungsten, titanium, chromium, or the like. In one embodiment of the invention, the metal layer is tungsten. Subsequently, a hard mask layer  57  is deposited on the metal silicide layer  55 . The hard mask  55  can be silicon nitride formed by chemical vapor deposition (CVD). 
         [0025]    The described multi layered structure can be patterned by a lithography process to form a plurality of conductive structures  501  and  503  in the device region  5 A and the ESD region  5 B, respectively. The conductive structures  501  are so-called word lines. Note that the distance between the conductive structures  501  is narrower than the distance between the conductive structures  503 . In addition, the size of the conductive structures  503  is larger than the conductive structures  501 . 
         [0026]    As shown in  FIG. 2B , a silicon oxide layer  59  is comfortably deposited on the device region  5 A and the ESD region  5 B. The deposition source includes tetraethyl ortho silicate (TEOS), and the deposition can be processed by LPCVD. Different from the process in  FIG. 1B , the example of the invention patterns the silicon oxide layer  59  in the ESD region  5 B by the lithography process to expose part of the semiconductor substrate. The exposed part of the substrate  50  determines the contact area of a following formed plug and the substrate. 
         [0027]    As shown in  FIG. 2C , a sacrificial polysilicon layer  61  is blanketly formed on the described structure by CVD such as LPCVD. The sacrificial polysilicon layer  61  has a higher top surface than the conductive structures  501  and  503 . After planarizing the sacrificial polysilicon layer  61  by CMP, a mask layer  63  is deposited thereon. The mask layer  63  can be silicon nitride formed by plasma enhanced CVD (PECVD). Subsequently, a patterned photoresist layer  65  is formed to selectively protect part of the sacrificial polysilicon layer  61  for the predetermined position of the later formed contact hole. 
         [0028]    As shown in  FIG. 2D , the mask layer  63  and the sacrificial polysilicon layer  61  not protected by the patterned photoresist layer  65  are then removed. The patterned photoresist layer  65  is then ashed. Removal of the mask layer  63  and the sacrificial polysilicon layer  61  is by anisotropic etching, including reactive ion etch (RIE) such as inductive coupled plasma RCE (ICP-RCE), high density plasma RIE (HDP-RIE), and the like. Ashing the photoresist layer  65  can be by general oxygen-containing plasma. 
         [0029]    As shown in  FIG. 2E , the mask layer  63  and silicon oxide layer  59  in lateral direction are removed by anisotropic etching as described above with a part of the mask layer  63  remaining and the silicon oxide layer  59  serve as side spacers of the conductive structures  501  and  503 . Subsequently, a silicon oxide layer  67  is comfortably formed on the described structure. The formation and the material of the silicon oxide layers  59  and  67  can be similar. 
         [0030]    As shown in  FIG. 2F , an interlayer dielectric layer  69  is blanketly formed on the silicon oxide layer  67 . The interlayer dielectric layer  69  is planarized until exposing the top surface of the sacrificial polysilicon layer  61 . In general, the interlayer dielectric layer  69  includes borophosphosilicate glass (BPSG) or borosilicate glass (BSG) formed by CVD and then an anneal process. By removing the sacrificial polysilicon layer  61 , the contact hole is formed, and by filling in the metal layer in the contact hole, the plug is formed. The sacrificial polysilicon layer  61  of the example is not directly removed; however, the sacrificial polysilicon layer  61  in the ESD region  5 B is covered by a patterned photoresist layer  70 . The patterned photoresist layer  70  should meet at least two requirements. First, the patterned photoresist layer  70  must totally cover the sacrificial polysilicon layer  61  in the ESD region  5 B. Second, the patterned photoresist layer  70  should not cover any part of the sacrificial polysilicon layer  61  in the device region  5 A. The patterned photoresist layer  70  should extend to the device region if these requirements are met. Because the critical dimension (hereinafter CD) of the patterned photoresist layer  70  is not high, low resolution lithography process and inexpensive negative type photoresist material can be applied to the invention to reduce costs. 
         [0031]    As shown in  FIG. 2G , a first removal process is performed to partially remove the sacrificial polysilicon layer  61  in the device region  5 A. The removed part occupies ⅓ to ⅔ depth of the bit line contact hole  71 . After ashing the patterned photoresist layer  70 , the second removal process is performed to totally remove the remaining sacrificial polysilicon layer  61  in the device region  5 A and partially remove the sacrificial polysilicon layer  61  in the ESD region  5 B to form a trench. If the thickness of the remaining sacrificial polysilicon layer  61  in the device region  5 A after the first removal process is thicker, than the thickness of the remaining sacrificial polysilicon layer  61  after the second removal process will be thinner. Alternatively, if the thickness of the remaining sacrificial polysilicon layer  61  in the device region  5 A after first removal process is thinner, than the thickness of the remaining sacrificial polysilicon layer  61  after the second removal process will be thicker. In the embodiments of the invention, the height of the remaining sacrificial polysilicon layer  61  in the ESD region  5 B occupies ⅓ to ⅔ depth of the contact hole  73 . In one embodiment of the invention, the height of the remaining sacrificial polysilicon layer  61  in the ESD region  5 B occupies a half depth of the contact hole  73 . 
         [0032]    As shown in  FIG. 2H , a metal layer  75  is filled into the bit line contact hole  71  and upper portion of the contact hole  73  to form plugs  77  and  79  and covered on the interlayer dielectric layer  69 . The metal layer  75 , for example, includes tungsten. After planarized, the metal layer  75  is patterned to form bit lines. Because the layout of bit lines and word lines is not a feature of the invention and process and methods are well known in the art, it is omitted for brevity. Thus, the DRAM with an electrostatic discharge structure of the invention is completed. 
         [0033]    Comparing the structures in  FIGS. 1H and 2H , the embodiment of the invention has several benefits as follows. First, the plug  79  in the ESD region  5 B has an upper portion of metal and a lower portion of polysilicon, thereby efficiently improving the mechanism strength of the ESD region. Next, the contact area between the bottom of the plug  79  and the substrate  50  can be controlled by the silicon oxide layer  59 , such that the contact area is reduced without increasing aspect ratio of the plug. If the sacrificial polysilicon layer in the lower portion of the plug  79  is totally removed as shown in  FIG. 1H , the silicon oxide layer  59  will be simultaneously removed. In brief, even if patterning is performed on the silicon dioxide layer  19  during a front end process in the comparative embodiment, the effect of controlling the contact area by the silicon dioxide layer  59  in the embodiment is still not achieved. Alternatively, the sacrificial polysilicon layer  61  serving as the lower portion of the plug  79  may rapidly release heat from electrostatic discharge, thereby preventing operating error caused by high temperatures. The described structure also shrinks the distance between the plug  79  and the conductive structure  503  and the distance between the plug  79  and the device region  5 A, thereby reducing the ESD region  5 B area. The bi-layer structure plug  79  can be completed by a low CD controlled patterned photoresist layer  70 , such that the processes and equipments are substantially maintained without much adjustment. 
         [0034]    While the invention has been described by way of embodiment and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.