Abstract:
In a semiconductor device, first and second substrates are supported with respective first major surfaces in opposing, parallel and spaced relationship. A conductor layer of low resistivity material is provided on a selected one of the opposing and spaced major surfaces, in intimate contact and spaced from the opposed major surface of the other substrate. An active device is formed in the first substrate with a region electrically connected to the conductor layer. A contact region is exposed at the second major surface of the first substrate and extends through the first substrate and into electrical contact with the conductor layer.

Description:
This application is a continuation, of application Ser. No. 08/150,253, filed Nov. 10, 1993, now abandoned which is a continuation of Ser. No. 07/787,911 filed Nov. 5, 1991, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention generally relates to semiconductor devices and more particularly to a fabrication process of an SOI (semiconductor-on-insulator) device, wherein a buried layer of reduced resistivity is provided. 
     The bipolar transistors generally have a buried collector layer of increased impurity concentration level under the collector layer to reduce the collector resistance. When constructing such a bipolar transistor on a semiconductor layer formed on an insulating substrate, one encounters a difficulty in forming such a buried collector contact layer. 
     FIGS. 1(A)-1(C) show a conventional process for forming such a buried low-resistivity layer in the SOI device. 
     Referring to FIG. 1(A), a silicon oxide layer 12 is formed to cover a support substrate 11 of silicon, for example, and a tungsten layer 13 is deposited on the upper major surface of the silicon oxide layer 12. Further, a silicon single crystal layer 14 is placed on the upper major surface of the tungsten layer 13 as shown in FIG. 1(B), and the structure of FIG. 1(B) is held at a temperature that causes a reaction between the silicon layer 14 and the tungsten layer 13. Typically, the structure of FIG. 1(B) is held at about 1100° C. As a result of the reaction, a silicide layer 15 is formed under the silicon layer 14. This silicide layer 15 has a low resistivity and is used for the buried low-resistivity layer of the active devices formed on the semiconductor layer 14. 
     In this conventional process, there exists a problem in that a stress tends to develop at an interface between the silicide layer 15 and the silicon oxide layer 12 particularly when the control of the temperature for reacting the tungsten layer 13 and the silicon layer 14 is poor or when the duration of the reaction is longer than an optimum duration. Thereby, there is a substantial risk that the silicide layer 15 and the silicon oxide layer 12 will separate from each other. When this occurs, the yield of the device is inevitably decreased. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof, wherein the foregoing problems are eliminated. 
     Another and more specific object of the present invention is to provide a process for fabricating a semiconductor device on a substrate covered by an insulation layer, wherein a buried low-resistivity layer is formed under a semiconductor layer on which active devices are formed. 
     Another object of the present invention is to provide a semiconductor device and a fabrication process thereof, wherein the semiconductor device comprises: an insulation layer having upper and lower major surfaces provided on a support substrate; a semiconductor layer having upper and lower major surfaces and provided on the upper major surface of the insulation layer with a separation therefrom; a spacer region provided between the lower major surface of the semiconductor layer and the upper major surface of the insulation layer to form said space; a low-resistivity layer provided on either the upper major surface of the insulation layer or the lower major surface of the semiconductor layer in correspondence to the space as a buried low-resistivity layer; and an active device provided on the semiconductor layer. According to the present invention, the buried low-resistivity layer is provided in correspondence to the space formed between the insulation layer and the semiconductor layer, and the problem associated with the heat treatment to form the silicide layer is eliminated. More specifically, the buried low-resistivity layer is formed by depositing a silicide layer at the bottom of the depression by sputtering and patterning the same subsequently. In this process, the heat treatment to form the silicide layer is eliminated. In a preferred embodiment, the depression is filled by a polysilicon layer that forms a contact region extending from the buried-low resistivity layer to the surface of the semiconductor layer. Alternatively, the depression may be made vacant. 
     Other objects and further features of the present invention will become apparent from the following detailed description read in conjunction with the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1(A)-1(C) are diagrams showing a conventional process for fabricating an SOI device having a buried low-resistivity region; 
     FIGS. 2(A)-2(J) are diagrams showing the process for fabricating a bipolar transistor on an SOI substrate together with a buried collector layer of reduced resistivity according to a first embodiment of the present invention; 
     FIGS. 3(A) and 3(B) are diagrams showing the structure of a semiconductor device according to a second embodiment of the present invention, respectively in a plan view and a cross sectional view; 
     FIGS. 4(A) and 4(B) are diagrams showing a bipolar transistor as an example of the device of the second embodiment; 
     FIGS. 5(A)-5(E) are diagrams showing the process for fabricating the semiconductor device of the second embodiment; 
     FIGS. 6(A)-6(E) are diagrams showing another process for fabricating the semiconductor device of the second embodiment; and 
     FIG. 7(A)-7(H) are diagrams showing still another process for fabricating the semiconductor device of the second embodiment. 
    
    
     DETAILED DESCRIPTION 
     FIGS. 2(A)-2(E) show the process for fabricating a semiconductor device according to a first embodiment of the present invention. 
     Referring to FIG. 2(A), a first silicon oxide layer 22 is formed on the upper surface of a support substrate 21 of silicon with a thickness of about 1.2 μm by a thermal oxidation process. 
     In the next step of FIG. 2(B), a photoresist layer 24 is provided on the upper major surface of the first silicon oxide layer 22 and subsequently is patterned to expose a part of the upper major surface the silicon oxide layer 22, and a reactive ion etching (RIE) process is applied to the thus-exposed part. Thereby, a depression 25 is formed in the silicon oxide layer 22 defined by sidewalls 22a of the layer 22 as illustrated in FIG. 2 (B) with a depth d of about 800 nm. Typically, a fluoride etching gas is used for the RIE process. 
     After the photoresist 24 is removed, a tungsten silicide (WSi) layer 26 is deposited on the silicon oxide layer 22 including the depression 25 by a CVD process or a sputtering process. Typically, the silicide layer 26 is deposited with a thickness of 300 nm. Further, ion implantation of arsenic (As + ) into the tungsten silicide layer 26 is conducted under the energy of 30 keV and the dose of 1×10 16  /cm 2 . See FIG. 2(C). 
     Next, a photoresist layer is deposited and subsequently patterned to form a resist mask 27 that covers the silicide layer 26 in correspondence to the part that is located in the depression 25. Further, an RIE process is applied to remove the silicide layer, 26, selectively with respect to the underlying silicon oxide layer except for the part that is protected by the patterned resist mask 27 in the depression 25. Typically, the RIE process is achieved by using a chloride etching gas. Thereby, a structure shown in FIG. 2(D) is obtained, in which the patterned portion of the silicide layer 26, remaining on the exposed upper surface of the depression 25 in the insulating layer 22, has sidewalls 26a substantially perpendicular to the exposed upper surface thereof and defining a lateral boundary of the patterned resistivity layer 26; the sidewalls 26a are spaced from the sidewalls 22a of the insulating layer 22, defining a space therebetween. 
     Next, a semiconductor layer 28 of single crystal silicon doped to the n-type is provided on the structure obtained in the step of FIG. 2(D) and heated at a temperature of about 1000° C. Thereby, the silicon layer 28 is firmly bonded to the silicon oxide layer 22. Further, the upper major surface of the silicon layer 28 is subjected to a polishing process to reduce the thickness to about 500 nm. See FIG. 2(E). 
     After the layer 28 is thus formed and polished, a second silicon oxide layer 29 is deposited on the layer 28 by a CVD process with a thickness of about 200 nm as shown in FIG. 2(F). Further, a photoresist 30 is applied on the upper major surface of the silicon oxide layer 29 as shown in FIG. 2(G), and a pair of elongated windows 31 and 32 are formed in the photoresist 30 in correspondence to the spaces between the sidewalls 22a of the depression 25 and the lateral boundaries 26a of the silicide pattern 26. Through these windows 31 and 32, an RIE process is applied against the silicon oxide layer 29 and further against the silicon layer 28 to form openings 33 and 34 in correspondence to the windows 31 and 32, until the openings reach the space 25. Thereby, the structure shown in FIG. 2(G) is obtained. In the structure of FIG. 2(G), it should be noted that the part 28a, of the silicon layer 28, that is located above the silicide region 26 forms a bridge structure that extends across the space 25. 
     Next, a deposition of polysilicon is achieved through the openings 33 and 34 by a reduced-pressure CVD process, and a polysilicon layer 35 is formed to fill the space 25 left between the silicide region 26 and the part 28 a of the silicon layer 28 located immediately above the silicide region 26 as well as the openings 33 and 34. See the structure of FIG. 2(H). 
     Next, the polysilicon layer 35 is polished until the silicon oxide layer 29 is exposed, and the structure thus obtained is subjected to a heat treatment at about 900° C. Thereby, the arsenic ions that are implanted in the silicide region 26 in the step of FIG. 2(C) are diffused into the polysilicon layer 35 and further into a bottom portion of the silicon layer part 28a that is used for the active layer or device layer of the semiconductor device. See the structure of FIG. 2(I). 
     In this heat treatment, it should be noted that the diffusion of arsenic ions occurs more easily in the polysilicon layer 35 than in the single crystal silicon layer part 28a, and the polysilicon layer 35 is doped to the n +  -type up to the part that fills the openings 33 and 34. Of course, the bottom portion of the silicon layer part 28a is doped also to the n +  -type as shown in FIG. 2(I). Thereby, it should be noted that the silicide region 26 in FIG. 2(I) forms a buried low-resistivity layer that is located under the device layer 28a and connected to the surface of the layer part 28a by the channel provided by the doped polysilicon layer 35 that acts as a collector contact region. It should be noted that the polysilicon layer 35 thus doped by the diffusion of the arsenic ions from the doped silicide region 26 has the sheet resistance of 4-5 Ω/ that is substantially lower than the value normally achieved by the ion implantation. 
     In the step of FIG. 2(J), a bipolar transistor is formed on the structure of FIG. 2(I). More specifically, the portion of the device layer part 28a that is doped to the n-type is used for the collector region C of the bipolar transistor, and the base region B is formed in the device layer part 28a by incorporating a p-type dopant. When doping the base region B and the emitter region E, the silicon oxide layer 29 is removed from the device region 28a. Further, the emitter region E of the n-type is formed in the base region B. After the base region B and the emitter region E are formed as such in the device region 73, a silicon oxide layer 37 is deposited and patterned to expose the base region B and the emitter region E. Further, the silicon oxide layer 37 is patterned to expose the polysilicon collector contact region 35, and a base electrode 38, an emitter electrode 39 and a collector electrode 40 are provided respectively in contact with the base region B, the emitter region E and the collector contact region 35. 
     The bipolar transistor thus formed has a reduced collector resistance because of the silicide region 26 formed immediately under the collector region C. Further, the resistance between the collector region C and the silicide region 26 is reduced by the increased carrier density that is achieved by the diffusion of the dopants from the silicide region 26. In the fabrication process described, the formation of the silicide region 26 does not include the heating process and hence the problems, such as the silicide region 26 coming off upon heat treatment, do not occur. Of course, the silicide region 26 is not limited to tungsten silicide as described but other silicide of refractory metals such as titanium silicide and molybdenum silicide may also be used. 
     Next, a second embodiment of the present invention will be described with reference to FIGS. 3(A) and 3(B), wherein FIG. 3(A) shows a plan view and FIG. 3(B) shows a cross sectional view taken along a line 3--3&#39;. 
     Referring to the plan view of FIG. 3(A), the semiconductor device of the present invention includes a number of device regions D formed in a silicon single crystal device layer 42 in rows and columns, wherein there is formed a low-resistivity layer 44 under the device layer 42 in correspondence to each device region D. 
     Referring to the cross sectional view of FIG. 3(B), there is provided a silicon wafer 41b on which a silicon oxide layer 41a is formed. The thickness of the silicon oxide layer 41a is arbitrary and may be selected to about 1 μm. 
     On the silicon oxide layer 41a, a silicon oxide spacer region 43 is provided in a grid pattern of spaces 45 surrounded by sidewalls 43a of the grid 43, in correspondence to the device regions D, and the device layer 42 is provided on the spacer region 43. Thereby, there are formed a number of spaces 45 between the silicon oxide layer 41a that covers the silicon wafer 41b and the low-resistivity layer 44 in correspondence to the device regions D. Further, in each device region D, there is provided a low-resistivity layer 44 on the lower major surface of the device layer 42. The active devices are formed on the device layer 42 in correspondence to each of the device regions D. As the semiconductor device is formed on the device layer 42 that is isolated from the silicon substrate 41b by the silicon oxide layer 41a and the insulating spacer region 43, the device of the present invention provides an effect substantially identical with the SOI devices. 
     FIGS. 4(A) and 4(B) are diagrams showing an example of the bipolar transistor formed on the structure of FIGS. 3(A) and 3(B), respectively in the plan view and the cross sectional view. 
     Referring to the cross sectional view of FIG. 4(B), there is formed an insulating device isolation region 61 in the device layer 42 so as to surround each device region D in correspondence to the grid-shaped spacer region 43, wherein the isolation region 61 extends from the upper major surface to the lower major surface of the device layer 42 and establishes a contact with the grid-shaped spacer region 43 at the lower major surface of the device layer 42. The isolation region 61 may be formed by the ion implantation of oxygen ions. 
     On the upper major surface of the device layer 42, a base layer 64 is deposited and an emitter layer 63 is formed on the upper major surface of the base layer 64 in contact thereto. Further, there is formed a region 49 of low-resistivity having a vertical sidewall 49a defining a lateral boundary thereof and disposed at the lower major surface of the device layer 42 in correspondence to each space 45, and a diffusion region 48 is formed in the device layer 42 in correspondence to the part adjacent to the low-resistivity region 49. Thereby, the part of the device layer 42 that is located between the base region 64 and the diffusion region 48 forms the collector of the bipolar transistor. The low-resistivity region 49 and the diffusion region 48 form together the low-resistivity region 44 of FIG. 3(B). Typically, the region 49 may be formed of a silicide of refractory metals such as tungsten silicide, molybdenum silicide, and the like. Alternatively, one may use these refractory metals as the low-resistivity region 49. 
     Furthermore, there is formed a collector contact region 62 to which extends from the lower major surface to the upper major surface of the device layer 42 in correspondence to the part where the region 49 is formed and provides a current path extending from the low-resistivity region 49 to the surface of the device layer 42. 
     FIG. 4(A) shows the plan view of the structure of FIG. 4(B), wherein it will be seen that the base region 64 is formed with a rectangular shape, and the emitter region 63 also of a rectangular shape but having a reduced size is provided on the base region 64. Further, there is formed a rectangular opening of the collector contact region 62. 
     In the present device, too, one can reduce the collector resistance significantly by providing the low-resistivity region 49 under the collector region and providing a channel of the current by the collector contact region 62. The only structural difference from the device of the first embodiment is that the low-resistivity region 49 is provided at the lower major surface of the device layer 42 and the space 45 formed under the device layer 42 remains vacant. 
     In the device of the present embodiment, it will be noted that the low-resistivity region 49 is not used for connecting the device layer 42 and the silicon wafer 41b mechanically. Thereby, the silicide region 49 is free from mechanical stresses and the risk of the silicide region 49 coming off from the lower major surface of the device layer 42 is substantially eliminated. Further, the region 49 can be formed with uniform thickness. As will be explained below, any suitable material having a sufficiently low resistivity can be used for the low-resistivity region 49. Thereby, one can reduce the thickness of the region 49 and hence the thickness of the region 43, and the fabrication of the SOI structure becomes easier. 
     Hereinafter, a fabrication process of the device of the second embodiment will be described with reference to FIGS. 5(A)-5(E). 
     Referring to FIG. 5(A), a silicon oxide layer is formed on the lower major surface of a silicon wafer 46 that has a thickness of about 500 μm. Further, a photoresist is applied on the lower major surface of the silicon oxide layer and patterned to form a resist pattern 47 that corresponds to the grid-shaped spacer region 43. Further, an etching process is applied to the lower major surface of the silicon oxide layer while using the patterned resist 47 as a mask to form the spacer region 43 and a depression region 43a that is surrounded by the spacer region 43. Further, an ion implantation is applied to the depression region 43a while using the patterned resist 47 as a mask. Thereby, a doped region 148 is formed in correspondence to the depression region 43a. 
     In the step of FIG. 5(B), a layer 49&#39; of silicide or metal is deposited on the lower major surface of the wafer 46, including the patterned resist 47 and the depression region 43a with a thickness of about 500 nm. Further, the layer 49&#39; that is deposited on the patterned resist 47 is lifted off by removing the resist 47. Thereby, a structure shown in FIG. 5(C) is obtained. It should be noted that one can use a refractory metal such as tungsten, tantalum or molybdenum for the layer 49 in place of silicide. 
     In the step of FIG. 5(D), a silicon support substrate 41 is attached to the bottom surface of the wafer 46. There, the upper major surface of the silicon substrate 41 establishes a contact with the lower major surface of the spacer region 43, and the space 45 is formed between the lower major surface of the layer 49 and the upper major surface of the substrate 41. The structure of FIG. 5(D) is subsequently heat treated such that the support substrate 41 is firmly bonded to the silicon oxide spacer region 43. Simultaneously, the impurities in the doped region 148 diffuse into the silicon wafer 46 and form the diffusion region 48. Further, it is possible to convert the metal forming the low-resistivity region 49 to a silicide upon the heat treatment by suitably choosing the condition of heat treatment. 
     In the step of FIG. 5(E), the thickness of the silicon wafer 46 is reduced to about 500 nm by polishing to form the device layer 42. Further, various devices are formed on the device layer 42 according to the well known processes such as the one described with reference to the first embodiment. 
     FIGS. 6(A)-6(E) show another process for fabricating the device of the second embodiment. 
     Referring to FIG. 6(A), a photoresist is applied to the bottom surface of the silicon wafer 46 and patterned subsequently to form a patterned resist 47 in correspondence to the grid-shaped spacer region 43. Further, while using the resist 47 as the mask, an etching process is applied to the bottom surface of the silicon wafer 46 to form a depression region 43a&#39; defined by a surrounding sidewall 43a of the spacer region 43 that is now formed as a part of the silicon wafer 46. Compare the structure of FIG. 6(A) with the structure of FIG. 5(A), wherein the spacer region 43 of the latter structure is formed of silicon oxide. After the depression region 43a&#39; is thus formed, an ion implantation of impurities is achieved into the depression region 43a&#39; while using the patterned resist 47 as a mask. 
     In the step of FIG. 6(B), the layer 49&#39; of metal or silicide is deposited on the bottom surface of the structure of FIG. 6(A), including the depression region 43a&#39; and the patterned resist 47. Further, in the step of FIG. 6(C), the layer 49&#39; that covers the patterned resist 47 is lifted off by removing the resist 47. Thereby, the low-resistivity region 49 is formed in correspondence to the depression region 43a&#39; and again has a vertical sidewall 49a defining a lateral boundary thereof. 
     In the step of FIG. 6(D), a support substrate identical in construction with the support substrate 41 and comprising the silicon substrate 41b and the silicon oxide layer 41a is attached to the bottom surface of the silicon wafer 46 such that the upper major surface of the silicon oxide layer 41a establishes an intimate contact with the lower major surface of the spacer region 43. Further, the structure of FIG. 6(D) is subjected a heat treatment, and the support substrate 41 is bonded firmly against the silicon wafer 46. Upon the heat treatment, the impurities doped into the impurity region 48 diffuse into the silicon wafer 46 similarly to the previously explained process and the diffusion region 48 is formed. 
     After the structure of FIG. 6(D) is thus formed, the silicon wafer 46 is subjected to the polishing process to reduce the thickness to about 1 μm, and the device layer 42 is obtained as shown in FIG. 6(E). 
     According to the fabrication process described above, one can eliminate the process for forming the silicon oxide layer for the spacer region 43, and the problem of deterioration in the quality of the crystal of the device layer 42 at the interface between the spacer region 43 and the device layer 42 as in the case of the device formed by the process of FIGS. 5(A)-5(E), is eliminated. 
     Next, a still other process for fabricating the semiconductor device of the second embodiment will be described with reference to FIGS. 7(A)-7(H). 
     In the present process, the steps of FIGS. 7(A)-7(C) are achieved similar to the steps of FIGS. 5(A)-5(C). After the structure of FIG. 7(C) is formed, a polysilicon layer 54 is deposited on the bottom surface of the structure of FIG. 7(C) as shown in FIG. 7(D) such that the polysilicon layer 54 covers the low-resistivity region 49 and buries the spacer region 43. 
     Next, the polysilicon layer 54 is polished starting from the lower major surface thereof until the silicon oxide spacer region 43 is exposed. Preferably, a urethane pad is used for polishing in combination with colloidal silica abrasives. After the spacer region 43 is exposed, the polishing is continued for another 10 minutes and the structure shown in FIG. 7(E) is obtained, wherein a polysilicon layer 54a having a concave lower major surface is left (i.e., remains) in correspondence to the marginal part of the depression 43a&#34; defined by sidewalls 43a. 
     Further, in the step of FIG. 7(F), a silicon substrate corresponding to the substrate 41 is attached to the bottom surface of the structure of FIG. 7(E), and there is formed a space 45a between the upper major surface of the substrate 41 and the concaved lower major surface of the polysilicon layer 54a. See the enlarged view of FIG. 7(G). In this state, the silicon substrate 41 is bonded to the spacer region 43 by heating, similar to the previous embodiments. Preferably, the bonding of the substrate 41 is achieved under a reduced pressure condition to avoid damaging of the wafer 46 due to the dilation of the air in the space 45a. As best seen in the enlarged view of FIG. 7(G), the low-resistivity region 49 has a vertical sidewall 49a defining a lateral boundary thereof, contiguous the corresponding vertical sidewall 43a of the spacer region 43. 
     Next, in the step of FIG. 7(H), the silicon wafer 46 is polished such that the thickness is reduced to form a device layer 42 having a thickness of about 500 nm. Further, various active devices are formed on the device layer 42 according to the well known process. 
     According to the present invention, the low-resistivity layer 49 is reinforced by the polysilicon layer 54a and the mechanical stability of the structure is increased, in addition to the reduction in the collector resistance. 
     Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention.