Abstract:
For use with a power supply having a controllable switch that switches in response to a drive signal received from a drive signal generator, a circuit for, and method of, modifying the drive signal to cause the switch to turn on at a reduced voltage. The circuit includes: (1) a synchronization signal generating circuit that senses an electrical characteristic of the supply representing a voltage across the switch, the synchronization signal generating circuit developing a synchronization signal as a function of the characteristic and (2) a drive signal modifier circuit that receives the synchronization signal and causes the drive signal generator to modify the drive signal in response thereto, the synchronization signal generating circuit and drive signal generator cooperating to synchronize the drive signal to the characteristic thereby to reduce power dissipation in the switch.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention is directed, in general, to power supplies and, more specifically, to a high efficiency switching power converter and a method of operation thereof. 
     BACKGROUND OF THE INVENTION 
     The development of high-efficiency power supplies in combination with a requirement of higher power density is a continuing goal in the field of power electronics. A switched-mode power converter is frequently employed in power supplies to convert an input voltage waveform into a specified output voltage waveform. Switched-mode power converters are also employed in power supplies to provide a stable, well-regulated output voltage. 
     A switched-mode power converter may be employed in a number of different power supply applications. For instance, a power supply coupled to a battery reserve system in wireless telecommunications equipment is one application for switched-mode power converters. The battery reserve system provides input power to the power supply in the event that primary power from a commercially available source is interrupted. Switched-mode power converters are also employed in off-line applications, wherein the input power is provided by a commercial utility, and it is desired that the power supply provide power factor correction in addition to maintaining a regulated voltage at the output of the power supply. 
     In battery-operated systems, the efficiency of the power converter is extremely important. Not only should the converter be highly efficient at maximum load, but it is also desirable to maintain efficiency under light- or no-load conditions. In off-line applications, where the input power is received from a commercial utility line, it is also necessary, in order to achieve &#34;green&#34; status, that the converter consume minimum power during light- and no-load conditions. 
     Furthermore, it is also desired to maintain efficiency over a large input voltage range, typically 4:1. It is very difficult to achieve high efficiency over a wide range of input voltages and variations in load requirements. Typically, converters are designed to have a maximum operating efficiency at 75% of rated output power. As a consequence, however, such converters are usually very inefficient under light-load conditions. 
     A switched-mode power converter generally includes an inductor, or transformer, coupled to an input power source and a switching transistor. When the switching transistor is on, energy is supplied to the inductor or transformer from the input power source. When the switching transistor is off, the output stage, comprised of a rectifying diode and output capacitor, receives energy from the inductor and the input voltage source. The operation of the switching transistor is controlled such that the converter output voltage is well-regulated. One of the principal contributors to converter losses, and thus inefficiency of operation, however, is turn-on losses in the switching transistor. This is particularly true when a converter is operated under light- or no-load conditions  e.g., operating in a discontinuous conduction mode (&#34;DCM&#34;)!. 
     Accordingly what is needed in the art is a switching power converter, and method of operation thereof, with improved light- and no-load efficiency when operating in the DCM at nearly constant switching frequency. 
     SUMMARY OF THE INVENTION 
     To address the aforementioned deficiencies, the present invention provides, for use with a power supply having a controllable switch that switches in response to a drive signal received from a drive signal generator, a circuit for, and method of, modifying the drive signal to cause the switch to turn on at a reduced voltage. The circuit includes: (1) a synchronization signal generating circuit that senses an electrical characteristic of the supply representing a voltage across the switch, the synchronization signal generating circuit developing a synchronization signal as a function of the characteristic and (2) a drive signal modifier circuit that receives the synchronization signal and causes the drive signal generator to modify the drive signal in response thereto, the synchronization signal generating circuit and drive signal generator cooperating to synchronize the drive signal to the characteristic and thereby reduce power dissipation in the switch. 
     In an alternative embodiment of the present invention, the switch is a field effect transistor (&#34;FET&#34;). FETs are commonly employed in switch-mode power supplies because of their fast switching characteristics. Other types of controllable switches are, however, within the scope of the present invention. 
     In an alternative embodiment of the present invention, the drive signal is a pulse-width modulated (&#34;PWM&#34;) signal. Switch-mode power converters commonly employ PWM circuits that, in response to signals indicative of characteristics of the power supply operation, alter the drive signal to the controllable switch to thereby regulate the operation of the power converter. Other control schemes, however, are within the broad scope of the present invention. 
     In an alternative embodiment of the present invention, the electrical characteristic sensed by the synchronization signal generating circuit is a voltage across the controllable switch. The synchronization signal generating circuit generates pulses upon sensing a maximum value of the electrical characteristic. Those skilled in the art should recognize that the principles of the present invention may be employed by sensing other electrical characteristics, such as current, and that such embodiments are within the broad scope of the present invention. 
     In an alternative embodiment of the present invention, the synchronization signal comprises a plurality of pulses, the drive signal modifier circuit causing the drive signal generator to superpose the pulses on an intermediate waveform developed within the drive signal generator, and employed by the drive signal generator to develop the drive signal, the pulses thereby temporally advancing the drive signal. PWM controllers, used in switch-mode power converters, typically employ a constant frequency circuit that produces an intermediate waveform used by the drive signal generation circuitry within the PWM. The present invention discloses a circuit and method operative to modify the intermediate waveform utilized by such PWMs, thereby effecting a change in the drive signal generated. 
     In an alternative embodiment of the present invention, the switch-mode power converter includes a transformer having a bias winding coupled to the synchronization signal generating circuit, the synchronization signal generating circuit sensing the electrical characteristic from the bias winding. The bias winding produces a voltage that is proportional to the voltage across a controllable switch. 
     In an alternative embodiment of the present invention, the synchronization signal generating circuit includes a zener diode for limiting the voltage of the synchronization signal pulses. By limiting the peak voltage of the synchronization pulses, the maximum variation in the normal switching frequency of the converter is minimized. 
     Those skilled in the art should recognize, from the detailed description provided hereafter, that the principles of the present invention may be employed to advantage in virtually all power converter topologies, including AC to DC, DC to AC and power factor-correcting topologies. 
     The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a schematic diagram of a prior art flyback converter; 
     FIG. 2 illustrates timing diagrams for the flyback converter of FIG. 1 operating in a continuous conduction mode (&#34;CCM&#34;); 
     FIG. 3 illustrates timing diagrams for the flyback converter of FIG. 1 operating in a discontinuous conduction mode (&#34;DCM&#34;); 
     FIG. 4 illustrates timing diagrams for the flyback converter of FIG. 1 operating in the DCM, taking into account the effects of the leakage inductance and parasitic capacitance; 
     FIG. 5 illustrates another schematic diagram of the flyback converter of FIG. 1; 
     FIG. 6 illustrates a schematic diagram of a constant frequency circuit employed within the PWM controller of the flyback converter of FIG. 5; 
     FIG. 7 illustrates timing diagrams for the constant frequency circuit of FIG. 6 employed within the PWM controller of FIG. 5; 
     FIG. 8 illustrates a schematic diagram of a flyback converter employing a control circuit constructed in accordance with the principles of the present invention; 
     FIG. 9 illustrates timing diagrams for the flyback converter of FIG. 8 operating in a DCM; 
     FIG. 10 illustrates another embodiment of the control circuit of the present invention employed in the flyback converter of FIG. 8; and 
     FIG. 11 illustrates timing diagrams for the flyback converter of FIG. 8 employing the control circuit of FIG. 10 and operating in a DCM. 
    
    
     DETAILED DESCRIPTION 
     Referring initially to FIG. 1, illustrated is a schematic diagram of a prior art flyback converter 100. The flyback converter 100 includes leakage inductance L 1k  and parasitic capacitance C p  associated with a switching transistor Q 1 , transformer T 1  and other circuit components. Those skilled in the art should understand the fundamental operation of the flyback converter 100 and should further recognize and address the potential detrimental effects that losses, such as the leakage inductance L ik , for a specified drive signal DRQ 1 , can have on the flyback converter 100. 
     Turning now to FIGS. 2 and 3, FIG. 2 illustrates timing diagrams for the flyback converter 100 of FIG. 1 operating in a continuous conduction mode (&#34;CCM&#34;); FIG. 3 illustrates timing diagrams for the flyback converter 100 of FIG. 1 operating in a discontinuous conduction mode (&#34;DCM&#34;). With continuing reference to FIG. 1, the waveform of the turn-on and turn-off for the switching transistor Q 1  and associated current i Q1  therethrough (demonstrated by turn-on/turn-off waveform and current i Q1  waveform, respectively, of FIG. 2) illustrate that there is a high turn-on peak current in the switching transistor Q 1  when operating in the CCM. The high turn-on current is generally attributable to a reverse recovery current of a diode D 1  associated with the flyback converter 100, and the current associated with discharging the parasitic capacitance C p . 
     Additionally, the waveform of the turn-on and turn-off for the switching transistor Q 1  and associated current i Q1  therethrough (demonstrated by turn-on/turn-off waveform and current i Q1  waveform, respectively, of FIG. 3) illustrate that there is also a high turn-on peak current in the switching transistor Q 1  when operating in the DCM. Again, the high turn-on current is generally attributable to the current associated with discharging the parasitic capacitance C p . Those skilled in the art should recognize that if the peak turn-on current conducted by the switching transistor Q 1  is reduced, the efficiency of the flyback converter 100 can be improved. 
     Turning now to FIG. 4, illustrated are timing diagrams for the flyback converter 100 of FIG. 1 operating in the DCM, taking into account the effects of the leakage inductance L 1k  and parasitic capacitance C p . Again, with continuing reference to FIG. 1, the waveform of the voltage V Q1  (see voltage V Q1  waveform) across the switching transistor Q 1  oscillates during a period D 3  T 3 . During this period of time, both the switching transistor Q 1  and diode D 1  are off (the flyback converter 100 is operating in the DCM) and a &#34;ringing&#34; (generally designated within range R of the voltage V Q1  waveform) is attributable to stray impedances, including the leakage inductance L 1k  and parasitic capacitance C p . Depending on when the switching transistor Q 1  is turned on again, the voltage V Q1  across the switching transistor Q 1  can range from a maximum peak voltage equal to the sum of the input voltage V in  and the reflected output voltage V o , as shown at points P 1 , P 3 , P 5  of voltage V Q1  waveform, to a minimum peak voltage equal to the difference between the input voltage V in  and the reflected output voltage V o , as shown at points P 2  and P 4  of voltage V Q1  waveform. The number of oscillations in the voltage V Q1  depends on both the circuit design and the operating conditions, and thus there may be many more maximum (e.g. point P 1 , P 3 , P 5 ) and minimum (e.g. points P 2 , P 4 ) peak voltages. Since the power loss due to discharging parasitic capacitance C p  through the switching transistor Q 1  is given by C p  V 2  F s  /2, it is preferable to turn-on the switching transistor Q 1  at a minimum peak voltage (e.g., point P 2 , P 4 ). 
     In addition to the power loss due to discharging parasitic capacitance C p  through the switching transistor Q 1 , there are additional power losses in the switching transistor Q1 due to non-zero turn-on current. As the input voltage V in  increases, the non-zero turn-on current can become the dominant source of losses within the switching transistor Q 1 . To improve the overall efficiency of flyback converter 100, therefore, the losses attributable to turn-on currents should be minimized. The power losses associated with the non-zero turn-on current, however, can also be minimized by turning on the switching transistor Q 1  when the voltage V Q1  thereacross is at a minimum peak voltage (e.g., point P 2 , P 4 ). Stated another way, the objective is to achieve zero-voltage switching across the switching transistor Q 1 . 
     Conventionally, the prior art includes power converters (e.g., the flyback converter 100) designed to operate at a boundary between the CCM and DCM. The flyback converter 100, operating at the boundary between CCM and DCM, generally employs variable-frequency pulse-width modulators (&#34;PWMs&#34;) to turn-on the switching transistor Q 1  at the point P 1 , corresponding to the point in time when the current i D1  (illustrated in current i D1  waveform) through the diode D 1  reaches a value of zero. The principle disadvantage of this solution is that it requires a wide switching-frequency range, typically in the range of 10:1 or greater. To minimize the maximum operating frequency, the flyback converter 100 is designed to operate at very low switching frequencies under nominal load. Whereas the required physical size of circuit components increase for low frequencies, the prior art solutions yield an increase in overall size of the flyback converter 100. Furthermore, to design the flyback converter 100 to withstand very high switching frequency operation requires more expensive magnetic components semiconductor devices and control circuitry. Those skilled in the art should recognize that when the flyback converter 100 operates at very high frequency under light loading, turn-on losses in the switching transistor Q1 could be equal to the total power losses in the switching transistor Q1 when operated at low switching frequency under nominal load. Therefore, to reduce the variation in switching frequency caused by turning on the switching transistor Q 1  before the normal switching point (e.g., point P 5  in voltage V Q1  waveform), it is preferable to induce the switching transistor Q 1  to turn-on at a minimum peak voltage preceding the normal switching point (e.g., point P 4  of voltage V Q1  waveform). 
     Turning now to FIG. 5, illustrated is another schematic diagram of the flyback converter 100 of FIG. 1. The flyback converter 100 also includes an input capacitor C 1 , inductor (&#34;transformer&#34;) T 1 , switching transistor Q 1 , diode D 1  and output capacitor C o . A capacitance C p , shown across the switching transistor Q 1 , is the equivalent to the parasitic capacitance C p  in the flyback converter 100. The current through the switching transistor Q 1  is sensed with a resistor R s  and the sensed voltage is directed to an input of a PWM controller 125. The transformer T 1  includes a primary winding N p , secondary winding N s  and a bias or auxiliary winding N B . When the flyback converter 100 is initially started, the supply voltage V cc  for the PWM controller 125 is provided from the capacitor C 2 , which is charged from the input voltage V in  through resistor R 1 . When the output voltage V o  is within regulation, the supply voltage V cc  for the PWM controller 125 is provided from the bias winding N B . The output voltage V o  is compared by an error amplifier 150 with a reference voltage V ref . The output of the error amplifier 150 is directed to the PWM controller 125 through a feedback isolation block 175. Constant frequency operation is provided by charging and discharging the capacitor C osc , as described with reference to FIGS. 6 and 7. The PWM controller 125, in response to the voltage on the capacitor C osc  and the output of the error amplifier 150, generates a drive signal DRQ 1  that controls the operation of the switching transistor Q 1  to regulate the output of the flyback converter 100. 
     Turning now to FIGS. 6 and 7, FIG. 6 illustrates a schematic diagram of a constant frequency circuit 600 employed within the PWM controller 125 of the flyback converter 100 of FIG. 5; FIG. 7 illustrates timing diagrams for the constant frequency circuit 600 of FIG. 6 employed within the PWM controller 125 of FIG. 5. With continuing reference to FIG. 5, the constant frequency circuit 600 may be integrated into the PWM controller 125 (as shown) or may be constructed from discrete components. A capacitor C osc  is charged by a current source 620 (e.g., a resistor) providing a nearly linear rise of the capacitor voltage V R (t) (as demonstrated by voltage V R (t) waveform of FIG. 7). When the voltage V R (t) is equal to a predetermined threshold voltage V m , a comparator 640 generates a voltage pulse V CL  causing a switch 660 to close and thereby discharge the voltage V R (t) on the capacitor C osc . Once the capacitor C osc  is discharged, the output of comparator 640 goes low causing the switch 660 to open, thus allowing the capacitor C osc  to begin charging again. At this point, the PWM controller 125 generates the drive signal DRQ 1  turning-on the switching transistor Q 1 . The resulting waveform of the voltage V Q1  across the switching transistor Q 1  (as shown by voltage waveform of FIG. 7), demonstrates that switching can occur at a point in time when the voltage V Q1  is at a peak maximum voltage (reference A, voltage V Q1  waveform of FIG. 7), thereby providing undesired turn-on losses in the switching transistor Q 1 . 
     Turning now to FIG. 8, illustrated is a schematic diagram of a flyback converter 800 employing a control circuit constructed in accordance with the principles of the present invention. The control circuit of the present invention is embodied in a synchronization signal generating circuit 810 and a drive signal modifier circuit 820. The synchronization signal generating circuit 810 includes a rectifying element 812 and pulse shaping circuit 814. The drive signal modifier circuit 820 is embodied in a resistor 822 in the illustrated embodiment. The remainder of the components illustrated in the flyback converter 800 are analogous to the components of the flyback converter 100 described with respect to FIGS. 1 and 5. 
     Turning now to FIG. 9, illustrated are timing diagrams for the flyback converter of FIG. 8 operating in a DCM. With continuing reference to FIG. 8, the transformer bias winding N B  produces a voltage signal V B  proportional to the voltage V&#39; Q1  across the switching transistor Q 1 . The voltage signal V B  is rectified by the rectifying element 812 and then shaped by the pulse shaping circuit 814. In the illustrated embodiment, the pulse shaping circuit 814 is a monostable multivibrator (one shots) circuit thereby providing a short duration pulse (as demonstrated by pulse P on voltage V&#39; R (t) waveform). The resulting synchronization signal waveform V syn  comprises a plurality of pulses temporally corresponding to the peak maximum voltages V&#39; Q1  across the switching transistor Q 1  (see voltage V syn  waveform). The synchronization signal waveform V syn  is coupled to the drive signal modifier circuit 820 (coupled in series between the capacitor C osc  and the circuit ground) such that the synchronization signal waveform V syn  is superposed on the normal capacitor voltage V R (t) waveform, resulting in a new voltage V&#39; R (t) (see voltage V&#39; R (t) waveform). The amplitude, as well as the duration, of the pulses including the synchronization signal waveform V syn  are preferably selected such that the last pulse in a given switching period induces the capacitor voltage V&#39; R (t) to exceed the predetermined threshold voltage V m . 
     When the capacitor voltage V&#39; R (t) exceeds the threshold voltage V m , a comparator (not shown), associated with a PWM controller 850, generates a voltage pulse V CL  at a time T s  &#39;, rather than the normal time T s , causing a switch, associated with the PWM controller 850, to close, thereby discharging the voltage V&#39; R (t) on the capacitor C osc . Once the capacitor C osc  is discharged, the output of comparator goes low causing the switch to open, thereby allowing the capacitor C osc  to begin charging again. 
     The discharge time of the capacitor C osc  is preferably designed to be approximately equal to one-half of the period of the oscillation T r  (see reference in FIG. 4) for the voltage V&#39; Q1  across the switching transistor Q1. Therefore, the maximum variation in a switching period is given by: ##EQU1## where T r  is the period of oscillation of the voltage V&#39; Q1  across the switching transistor Q1 and T s  is the original switching period of the flyback converter 800. 
     Those skilled in the art should recognize that although the charging time of the capacitor C osc  is slightly reduced, the discharge time is substantially unaffected, thus resulting in only a slight increase in the flyback converter 800 switching frequency. Furthermore, an examination of the resulting voltage V&#39; Q1  across the switching transistor Q 1  reveals that the switching occurs at a point (reference A in FIG. 9) when the voltage V&#39; Q1  is at a peak minimum, thus resulting in reduced turn-on losses in the switching transistor Q 1  and, therefore, improved overall efficiency for the flyback converter 800 at nearly constant operating frequency. 
     Turning now to FIG. 10, illustrated is another embodiment of a control circuit of the present invention employed in the flyback converter 800 of FIG. 8. As previously mentioned, the control circuit constructed in accordance with the principles of the present invention is embodied within the synchronization signal generating circuit 810 and the drive signal modifier circuit 820. The synchronization signal generating circuit 810 includes the rectifying element 812 and pulse shaping circuit 814. The pulse shaping circuit 814, however, includes a resistor 1015 and zener diode 1020. Additionally, the drive signal modifier circuit 820 is embodied in a resistor 822 and an additional capacitor C syn  in the illustrated embodiment. 
     Turning now to FIG. 11, illustrated are timing diagrams for the flyback converter 800 of FIG. 8 employing the control circuit of FIG. 10 and operating in the DCM. With continuing reference to FIGS. 8 and 10, the transformer bias winding N B  produces a voltage signal V B  proportional to the voltage V&#39; Q1  across switching transistor Q 1 . The voltage signal V B  (see voltage V B  waveform) is rectified by the diode 812, scaled by a resistor 1015, and the peak is limited by a zener diode 1020, to thereby produce a synchronization signal waveform V syn  (see voltage V syn  waveform) that includes a plurality of pulses temporally corresponding to the peak maximum voltages V&#39; Q1  across the switching transistor Q 1 . The synchronization signal waveform V syn  is coupled to the resistor 822, (coupled in series between the capacitor C osc  and the circuit ground) such that the synchronization signal waveform V syn  is superposed on the normal capacitor voltage V R (t) waveform, resulting in a new voltage V&#39; R (t). As opposed to the control circuit discussed with respect to FIGS. 8 and 9, the synchronization signal waveform V syn  that is superposed on the normal capacitor voltage V R (t) waveform to form the voltage V&#39; R (t) includes a pulse (designated by reference P on voltage V&#39; R (t) waveform) longer in duration than the equivalent pulse illustrated in FIG. 9 (see pulse P on voltage V&#39; R (t) waveform of FIG. 9). The pulse is longer in duration because the synchronization signal waveform V syn  is a function of the voltage V B  rectified by the voltage V z  across the zener diode 1020 (as demonstrated by voltage V syn  waveform). 
     The amplitude and duration of the pulses including the synchronization signal waveform V syn  are preferably selected such that the last pulse in a given switching period induces the capacitor voltage V&#39; R (t) to exceed the predetermined threshold voltage V m . This is accomplished by proper selection of the component values for the resistors 822, 1015 and the zener diode 1020. The synchronization signal generating circuit 810 includes the zener diode 1020 for limiting the voltage of the synchronization signal pulses. By limiting the peak voltage of the synchronization pulses, the maximum variation in the normal switching frequency of the flyback converter 800 is minimized. Furthermore, the capacitor C syn  delays the pulses including the synchronization signal waveform V syn , thus allowing additional control over the switching frequency. Those skilled in the art should understand that the control circuit (including the zener diode 1020) is a representative alternative embodiment of the present invention and variations that accomplish the same or similar objective are well within the broad scope of the present invention. 
     Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.