Abstract:
A digital camera for capturing and processing images of different resolutions and a corresponding method for down-scaling a digital image are provided. The method includes forming an image of a real scene on an image sensor that is made up of a plurality of pixels arranged in a matrix. The method further includes addressing and reading pixels in the matrix to obtain analog quantities related to the pixels luminance values, converting the analog quantities from the pixels matrix into digital values, and processing the digital values to obtain a data file representing the image of the real scene. To reduce computation time and power consumption, the addressing and reading of the pixels includes selecting a group of pixels from the matrix, and storing the analog quantities related to the pixels of the selected group of pixels into an analog storing circuit. The stored analog quantities are averaged to obtain an analog quantity corresponding to an average pixel luminance value.

Description:
FIELD OF THE INVENTION 
   The present invention relates to the acquisition and processing of images in a digital format, and in particular, to a method for down-scaling a digital image and to a digital camera for capturing and processing images having different resolutions. 
   BACKGROUND OF THE INVENTION 
   Digital still cameras are currently among the most common devices used for acquiring digital images. The ever-increasing resolution of the sensors on the market and the availability of low-consumption digital-signal processors have led to the development of digital cameras which can achieve quality and resolution very similar to those offered by conventional film cameras. 
   As well as being able to capture individual images (still pictures), the most recent digital cameras can also acquire video sequences (motion pictures). To produce a video sequence, it is necessary to acquire a large number of photograms taken at very short intervals (for example, 15 photograms per second). The processed and compressed photograms are then encoded into the most common digital video formats (for example, MPEG-4). 
   In devices which can acquire both individual images and video sequences, there are two conflicting requirements. For photographic applications, high resolution and a large processing capacity are required, even at the expense of acquisition speed and memory occupation. In contrast, for video applications, a fast acquisition speed and optimization of memory resources are required, at the expense of resolution. 
   The same remarks are applicable to digital cameras which are not designed for acquiring video sequences in addition to still images, but are provided with a low-resolution digital display for previewing the image before shooting and/or editing an image after acquisition. 
   With reference to  FIG. 1 , a digital camera  1  for photographic and video applications includes an acquisition block  2  formed by a lens and diaphragm  3  and by a sensor  4  onto which the lens focuses an image representative of a real scene. 
   The sensor  4  is part of an integrated circuit comprising a matrix of photosensitive cells and a driving circuit. Each cell can be addressed and read to obtain an analog electrical quantity related to the light exposure of the cell. The analog electrical quantity obtained from each photosensitive cell is converted into a digital value by an A/D converter  5 . This value may be represented by 8, 10 or 12 bits, according to the dynamics of the camera. 
   In a typical sensor, a single photosensitive cell is associated with each pixel. The sensor is covered by an optical filter formed by a pattern of filter elements each of which is associated with a photosensitive cell. Each filter element transmits to the photosensitive cell associated therewith the luminous radiation corresponding to the wavelength solely of red light, solely of green light, or solely of blue light (absorbing a minimal portion thereof), so that only one component, that is, the red component, the green component, or the blue component is detected for each pixel. 
   The type of filter used varies according to the manufacturer. The most commonly used is known as a Bayer filter. In this filter, the arrangement of the filter elements, which is known as the Bayer pattern, is shown in  FIG. 4   a  in connection with a 6×6 pixel matrix. With a filter of this type, the green component (G) is detected by half of the pixels of the sensor with a chessboard-like arrangement. The red (R) and blue (B) components are detected by the remaining pixels in alternating rows. 
   The image output by the analog/digital converter  5  is an incomplete digital image because it is formed by a single component (R, G or B) per pixel. The data that represent this image are conventionally referred to as raw CFA (color filter array) data. 
   The raw CFA data are sent to the input of a preprocessing unit (PrePro)  6 . This unit is active prior to and during the entire acquisition stage, and interacts with the acquisition block  2 . The unit estimates, from the incomplete image, various parameters which are useful for performing automatic control functions, i.e., auto-focus, auto-exposure, correction of sensor defects, and white balancing functions. 
   The incomplete CFA digital image is then sent to a unit  7  known as the IGP (Image Generation Pipeline) which is composed of several blocks. Starting with the CFA image, a block  8  known as a ColourInterp generates by an interpolation process a complete RGB digital image in which a set of three components corresponding to the three R, G and B components is associated with each pixel. This conversion may be considered as a transition from a representation of the image in a single plane (Bayer) to a representation in three planes (R, G, B). This image is then processed by a block  9 , known as ImgProc, which is provided for improving quality. Several functions are performed in this block  9 , i.e., exposure correction, filtering of the noise introduced by the sensor  4 , application of special effects, and other functions. The number and type varies in general from one manufacturer to another. 
   The complete and improved RGB image is passed to a block  10 , which is known as the scaling block. This block reduces the resolution of the image, if required. An application which requires the maximum available resolution equal to that of the sensor (for example, a high-resolution photograph) does not require any reduction in resolution. If, however, for example, the resolution is to be halved for acquiring a video sequence, the scaling block  10  eliminates three quarters of the pixels. 
   After scaling, the RGB image is converted by a block  11  into the corresponding YCbCr image, in which each pixel is represented by a luminance component Y and by two chrominance components Cb and Cr. This is the last step performed in the IGP unit  7 . The next block is a compression/encoding block  12 . Generally, the JPEG format is used for individual images and the MPEG-4 format for video sequences. 
   The resolution necessary for video applications or for preview display is lower than that required for photographic applications. Nevertheless, in the prior art apparatus, the sensor and the IGP are at maximum resolution in both cases. This leads to wasted computation, which translates into a large consumption of time and energy and an unnecessary occupation of memory. 
   SUMMARY OF THE INVENTION 
   In view of the foregoing background, an object of the present invention is to provide a method for down-scaling a digital image. 
   Another object of the present invention is to provide a digital camera for capturing and processing images having different resolutions. 
   This and other objects, advantages and features in accordance with the present invention are provided by a method for down-scaling a digital image comprising forming an image of a real scene on an image sensor comprising a plurality of pixels arranged in a matrix, and addressing and reading the pixels in the matrix to obtain analog quantities on luminance values of the pixels. 
   The addressing and reading preferably comprises selecting a group of pixels in the matrix, storing the analog quantities of the selected group of pixels, and producing a weighted average of the stored analog quantities to obtain an analog quantity corresponding to an average pixel luminance value. The method preferably further comprises converting the analog quantities on the average pixel luminance values of the selected groups of pixels to digital values, and processing the digital values to obtain a data file representing the image of the real scene. 
   The digital camera preferably comprises an image sensor comprising a plurality of pixels arranged in a matrix, and a driver for addressing and reading the pixels in the matrix to obtain analog quantities on luminance values of the pixels. An analog/digital circuit preferably converts the analog quantities on the luminance values to digital values. 
   The digital camera preferably comprises a processing circuit for processing the digital values to obtain a data file representing an image. The processing circuit may comprise an analog down-scaling unit and a by-pass circuit connected thereto for by-passing or enabling the analog down-scaling unit for respectively obtaining a high resolution image or a low resolution image. 
   The analog down-scaling unit and the by-pass circuit are preferably connected between the image sensor and the analog/digital circuit. The analog down-scaling unit preferably comprises at least one bank of capacitors, and first and second sets of switches. The first set of switches is for selecting groups of pixels from the matrix, and for charging the at least one bank of capacitors to respective levels corresponding to the analog quantities of the selected group of pixels. The second set of switches produces a weighted average of the respective charge levels of the at least one bank of capacitors to obtain for each selected group of pixels an analog quantity corresponding to an average pixel luminance value. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be better understood from the following detailed description of various embodiments thereof given with reference to the appended drawings, in which: 
       FIG. 1  is a block diagram of a digital camera according to the prior art; 
       FIG. 2  is a block diagram of a digital camera according to the invention; 
       FIG. 3  is a detailed block diagram of a portion of the digital camera illustrated in  FIG. 1 ; 
       FIGS. 4   a - 4   f  show how the resolution of a digital image is modified by the down-scaling method according to the invention; 
       FIG. 5  is a basic circuit diagram for implementing the down-scaling method according to the invention; 
       FIG. 6  is a circuit diagram illustrating the down-scaling method according to the invention; 
       FIG. 7  shows a circuit diagram for down-scaling a 6×6 pixel matrix in a digital camera and a table illustrating operation of the circuit according to the invention; 
       FIG. 8  is a circuit diagram similar to the circuit diagram illustrated in  FIG. 7 , but with a simplified wiring according to the invention; 
       FIG. 9  shows a simplified version of the circuit diagram illustrated in  FIG. 7  and a corresponding operation table according to the invention; and 
       FIG. 10  is a block diagram representing a generalized down-scaling system of a digital camera according to the invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The block diagram of  FIG. 2  is similar to that of  FIG. 1 , and reference numerals identical to the reference numerals in  FIG. 1  are used to identify the same or equivalent blocks. A substantial difference in  FIG. 2  is that the sensor output is not connected to the A/D block  5  directly, but is connected to the A/D block  5  through an analog down-scaling unit  14 . In addition, a block  15  is provided to by-pass the down-scaling unit  14  if a by-pass signal is applied to a control input  16 . A digital scaling block  10 , as shown in  FIG. 1 , is also included in  FIG. 2 . However, it can be omitted if a further down-scaling is not required. 
   In  FIG. 3  the sensor  4  is shown in greater detail, together with the analog down-scaling unit  14  and the by-pass block  15 . A driver  22  generates clocking signals for addressing each pixel of a sensor matrix  17  at the intersections of row and column lines, and transferring pixel signals to a register  23  through the analog down-scaling unit  14 . The analog signal output by the register  23  is sampled in a sampling block  24  and converted into digital form in the A/D block  5  for further digital processing, as explained in  FIG. 1 . A timing generator  25  provides timing signals to a plurality of system units, and in particular, to a driver  22 . A microprocessor controller  26  controls the A/D converter  5  and additional system units (not shown), and exchanges control signals with the timing generator  25 . 
   A broad explanation of the operation of the down-scaling method of the invention is given below with reference to  FIGS. 4   a - 4   f.    FIG. 4   a  shows a 6×6 pixel matrix of a Bayer patterned pixel array.  FIG. 4   b  shows four 3×3 pixel sub-matrices which divide the 6×6 pixel matrix into four quarters Q 1 -Q 4 .  FIGS. 4   c - 4   e  show the arrangements of the red (R), green (G) and blue (B) pixels in the matrix of  FIG. 4   a.    
   According to the down-scaling method of the invention, the four red pixels R in quarter Q 4  are detected. An analog average of the luminance levels of these four pixels is obtained and a new red pixel having this average as its luminance value, as shown at R 4  in  FIG. 4   f,  is defined. In the same way, the four blue pixels in quarter Q 1  are detected and averaged to a new blue pixel B 1 . The four green pixels at the corners of quarter Q 2  and the four green pixels at the corners of quarter Q 3  are also detected. An average of each group of four pixels is obtained and two new average green pixels, as shown with G 2  and G 3  in  FIG. 4   f,  are defined. As an alternative or in addition, the four green pixels in quarter Q 1  and the four green pixels in quarter Q 4  can be used to obtain two new average green pixels, as shown with G 1  and G 4  in  FIG. 4   f.    
     FIG. 5  shows a preferred implementation of the analog averaging of four pixels. A 3×3 pixel sub-matrix  17 ′ has three column lines, indicated as bitlineA, bitlineB and bitlineC, connected to a horizontal register  23 ′ through an averaging unit  14 ′. A driver unit  22 ′ includes a vertical driver  33  that selects and activates the matrix lines of the matrix  17 ′ by control signals se 11 , se 12  and se 13 , a horizontal driver  34  that generates control signals se 1 A, se 1 B and se 1 C, and a sample and hold driver  35  that generates control signals smp 11 , smp 12 , smp 13  and smp 14 . The averaging unit  14 ′ comprises four capacitors C 1 , C 2 , C 3  and C 4  having an equal capacitance. The four capacitors have a common terminal and are connectable in parallel to one another by three sample and hold switches SH 2 , SH 3  and SH 4  respectively controlled by signals smp 12 , smp 13  and smp 14 . A fourth sample and hold switch SH 1  is controlled by signal smp 11  and is connected to a common terminal N of three switches b 1 A, b 1 B and b 1 C which are respectively connected to bitline A, bitline B and bitline C. 
   In operation, the drivers  33 ,  34 ,  35  generate control signals to activate the matrix rows in sequence and to close and/or open the switches according to a predetermined timing. More particularly, starting from an initial condition with switches b 1 A, b 1 B and b 1 C open and switches SH 1 , SH 2 , SH 3  and SH 4  closed, the timing of the control signals for averaging four pixels of the matrix  17 ′, for example, the corner pixels a 1 , c 1 , a 3 , c 3 , is as follows: 
   1) se 11  is high to activate the row line  1 , se 12  and se 13  are low; se 1 A is high to close switch b 1 A; and se 1 B and se 1 C are low; the value of pixel a 1  is charged into capacitors C 1 -C 4 , then smp 14  goes low to open switch SH 4 ; 
   2) with switch SH 4  hold open—sell is high to activate the row line  1  and se 12  and se 13  are low; se 1 C is high to close switch b 1 C and se 1 A and se 1 B are low; the value of pixel c 1  is charged into capacitors C 1 -C 3 , then smp 13  goes low to open switch SH 3 ; 
   3) with switches SH 4  and SH 3  hold open—se 13  is high to activate the row line  3 , se 11  and se 12  are low; se 1 A is high to close switch b 1 A and se 1 B and self are low; the value of pixel a 3  is charged into capacitors C 1  and C 2 , then smp 12  goes low to open switch SH 2 ; 
   4) with switches SH 4 , SH 3  and SH 2  hold open—se 13  is high to activate the row line  3  and se 11  and se 12  are low; se 1 C is high to close switch bIC and se 1 A and se 1 B are low; the value of pixel C 3  is charged into capacitor C 1 , then smpli goes low to open switch SH 1 ; 
   5) now the pixel values of a 1 , c 1 , a 3 , c 3  are respectively on capacitors C 4 , C 3 , C 2 , C 1 —to perform the averaging, smp 12 , smp 13  and smp 14  are set high to turn on the associated switches SH 2 , SH 3  and SH 4 , thus redistributing the charge between the four capacitors in parallel; the output voltage representing the average luminance level of the four pixels is provided to the horizontal register  23 ′. 
   As readily understood by one skilled in the art of electronic circuit design, the averaging unit can be implemented in many different ways. In particular, alternative ways of connecting the capacitors to the output of the bitline switching arrangement can be devised to avoid the series connection of the access switches (the sample and hold switches in  FIG. 5 ). Furthermore, the capacitors do not need to be equal. Unequal capacitors can be used advantageously when weighted averaging is required. Moreover, a different number of capacitors can be used according to the number of pixel values to be averaged. 
   To perform the down-scaling operation on a 6×6 pixel matrix, a more complex circuit is required. Consider first  FIG. 6  wherein b 1 A, b 1 B and b 1 C are three column lines of a pixel matrix and NA, NB, NC are three output nodes to be connected each to a bank of four capacitors, as C 1 -C 4  in  FIG. 5 . Each column line b 1 A, b 1 B, b 1 C can be connected to an output node NA, NB, NC either through switches driven by respective signals indicated oA, iA, oB, iB, oC, iC, or through bypass switches driven in common by a signal indicated bypass. The switches can be driven by a suitable control unit to pass a pixel value from any of the three matrix columns to any of the three capacitor banks connected to the output nodes. For example, to pass a pixel value from column b 1 C to the capacitor bank connected to output node NA, the switches oA and iC are closed, while the remaining switches remain open. The control unit drives the switches so that only one pixel bitline value may be routed to an output node at a time, except when a bypass signal closes the bypass switches. In this case, all other switches are open and the pixels are read as in a normal reading of the pixel matrix at full resolution. 
   Consider now a sensor comprising a 6×6 pixel matrix like the Bayer patterned matrix shown in  FIG. 4   a,  with columns indicated as A, B, C, D, E, F and rows indicated  1 ,  2 ,  3 ,  4 ,  5 ,  6 . In the sensor all the pixels in a row share a read access line and all the pixels in a column are connected to a common line (bitline). A circuit for down-scaling the 6×6 Bayer patterned matrix to a 2×2 Bayer patterned matrix with two extra averaged pixels values (like the averaged green pixels in quarters Q 1  and Q 4  as shown in  FIG. 4   f ) is shown in  FIG. 7 . The switches shown in the previous Figures have been replaced by NMOS transistors. The column lines, or bitlines, are indicated as b 1 A-b 1 F, the output lines, i.e., the output terminals of the six capacitor banks, are indicated as outputA-outputF. The signals for driving the transistors of the capacitor banks are identified by c 1 -c 4  followed by a letter A-F, as in the corresponding output line. A switching arrangement similar to the switching arrangement of  FIG. 6  but using NMOS transistors in place of switches is connected between the column lines b 1 A-b 1 F and the capacitor banks. The gates of the bypass transistors of the arrangement are connected to a common line for receiving a bypass signal. The control signals applied to the gates of the switching transistors are identified by the letters “o” and “i” followed by a letter A-F, as in the corresponding column line b 1 A-b 1 F. 
   The sequence of switching operations used to perform the down-scaling as explained above in  FIG. 4  is given in a table that is included in  FIG. 7 . Some sharing between the control signals is possible so that the wiring required can be reduced, as shown in  FIG. 8 . The pairs of control signals oA and oD, oC and oF, iA and iD, iC and iF are respectively replaced by single control signals oAD, oCF, iAD, iCF. 
   If the extra two green values (G 1  and G 4 ) are not necessary, the circuit can be simplified as shown in  FIG. 9 . The switching sequence is given in the table included in  FIG. 9 . 
   The examples described above use a down-scaling by a factor  3 , however, the invention can be implemented also for down-scaling by factors other than 3. In general, a down-scaling unit operating according to the method of the invention can be represented by a block diagram as shown in  FIG. 10 . The output lines of a pixel matrix  40  are connected to a plurality of multiplexors  41 , which have the same function as the switching arrangements connected to the matrix output lines in  FIG. 6 , for example, and the multiplexor outputs are connected to respective analog averaging blocks  42  which have the same function as the capacitor banks. The scaled output data from the analog averaging blocks  42  are then converted in digital form, and further processed as explained in  FIG. 2 . 
   As readily understood from the above description, the object of the invention is fully achieved. In particular, the computation time and the power consumption are greatly reduced because the A/D converter rate is reduced (by ⅙ in the example shown and described), and the amount of pixel data to be processed by the IGP to produce the final image is also reduced (by 1/9 in the example). As a further advantage, the output of the down-scaling unit applied to a Bayer patterned image sensor is itself a Bayer pattern. Therefore, both the high and the low resolution outputs can be processed by the same IGP unit. Moreover, the overall system complexity is reduced because the digital scaling circuit can be omitted. 
   Although only a few embodiments of the invention have been described, a number of modifications are possible within the scope of the same inventive concept. For example, the inventive method can be applied advantageously to a system comprising a sensor with a filter of a type different from the Bayer filter, or also to a monochromatic sensor.