Abstract:
An automatic arpeggio musical instrument includes a pulse generator having a plurality of keys for generating periodic pulses by depression of one of the keys, each of the keys generating a voltage, a timing pulse generator connected to the pulse generator, a memory connected to the timing pulse generator for generating digital signals of a musical scale, digital-to-analog converter means connected to the memory for converting the digital signals into analog signals, a processor connected to the converter for selectively adding and subtracting the key-generated voltage to the analog signals, and for generating an output voltage therefrom, and a voltage-controlled oscillator connected to the processor for controlling the output voltage.

Description:
OBJECTS OF THE INVENTION 
     This invention has for its principal object the provision of an automatic arpeggio apparatus in an electronic musical instrument having a main oscillator of a voltage-controlled type. 
     Another object of the present invention is to provide an apparatus of the aforesaid type wherein an automatic arpeggio performance according to a rhythm can be given, and an automatic arpeggio performance corresponding to a key depressed can be obtained. An additional object of the invention is to provide such an apparatus of the aforesaid kind wherein words can be written into a memory circuit by depression of a key, and then the words can be reproduced on performance, and furthermore, without carrying out any change in the setting of the circuit memory, the memories in a major scale thereof can be converted into those in a minor scale so that a performance in a minor scale can be given. 
     SUMMARY OF THE INVENTION 
     An automatic arpeggio musical instrument includes pulse generator means having a plurality of keys for generating periodic pulses by depression of one of the keys, each of the keys generating a voltage, a timing pulse generator connected to the pulse generator means, memory means connected to the timing pulse generator for generating digital signals of a musical scale, digital-to-analog converter means connected to the memory means for converting the digital signals into analog signals, processor means connected to converter means for selectively adding and subtracting the key-generated voltage to the analog signals and for generating an output voltage therefrom, and a voltage-controlled oscillator connected to the processor means for controlling the output voltage. 
     The pulse generator means preferably include a rhythm pulse generator, and pulse-width change circuit interconnected between the pulse generator means and the timing pulse generator; the memory means preferably include a read-only memory. 
     In an alternative embodiment, the memory means includes a read-write memory for storing a plurality of addresses, and a plurality of words, each of the addresses corresponding to one of the words, and the write-read memory has an input and an output. The instrument includes further analog-to-digital converter means having an input and an output, and the analog-to-digital converter means output is connected to the read-write memory input. Voltage generator means for generating the voltage and having an output are connected to the analog-to-digital converter means input, and keying generator means are connected to the timing pulse generator for generating a plurality of pulses following the depression of one of the keys; each of the pulses selects the addresses respectively in sequence, so that a word corresponding to a depressed key is selected and memorized in that memory means. 
     The musical instrument preferably includes word converting circuit means for converting a word of a major scale into a word of a minor scale and which is interconnected between the memory means and the digital-to-analog converter means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The present invention will be better understood by means of the accompanying drawing, in which: 
     FIG. 1 is a block diagram showing one embodiment of the present invention; 
     FIGS. 2A through 2F are waveform diagrams explaining the operation thereof; 
     FIG. 3 is a circuit diagram showing one example of a rhythm pulse generator; 
     FIGS. 4A through 4E are waveform diagrams explaining operation of FIG. 1 when the rhythm pulse generator of FIG. 3 is used, and words in a memory circuit are converted; 
     FIG. 5 is a block diagram showing another embodiment of the present invention; 
     FIGS. 6-1 through 6--6 are diagrams showing various output pulses of a timing pulse generator, according to the present invention; and 
     FIGS. 7 and 8 are block diagrams showing other embodiments of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, numeral 1 denotes a pulse generator which generates pulses repeatedly by depression of a key, numeral 2 denotes a timing pulse generator, numeral 3 denotes a memory circuit, numeral 4 denotes a D-A converter, numeral 5 denotes a gain control circuit, numeral 6 denotes a calculation or processor circuit, numeral 7 denotes a voltage controlled type main oscillator (called hereinafter &#34;VCO 7&#34;), numeral 8 denotes a voltage controlled type filter (called hereinafter &#34;VCF 8&#34;), numeral 9 denotes a voltage controlled type amplifier (called hereinafter &#34;VCA 9&#34;), numeral 10 denotes an amplifier, and numeral 11 denotes a speaker, and these components are sequentially connected. 
     The timing pulse generator 2 includes a counter 2a and a decoder 2b, so that if the pulse generator 1 generates pulses as shown in FIG. 2A, there may be obtained in sequence at the plural output terminals 2-1, 2-2, . . . . 2-18 of the decoder 2B timing pulses as shown in FIG. 2B, and sequentially shown as 1,2. . . .18. Numerals 2a-1, 2a-2 . . . . 2a-5 denote flip-flop circuits constituting the counter 2a. 
     The memory circuit 3 includes a matrix circuit, and a read-only memory, for instance, is used for the matrix circuit. 
     Numeral 12 denotes a voltage generating circuit which generates a voltage corresponding to a key depressed, and an output 12a thereof is connected to an input terminal of the processor or calculation circuit 6. The voltage generating circuit 12 includes plural series resistances 15-1, 15-2 . . . . connected through a constant electric current circuit 14a to a positive electric source terminal 13a, and there are provided key-switches 16-1, 16-2 . . . . at respective contacts of the resistances 15-1, 15-2 . . . . , and these key-switches 16-1, 16-2 . . . . are connected in common to the output terminal 12a, and through a constant electric current circuit 14b to a negative electric source terminal 13b. 
     If, thus, any desired key is depressed, a key-switch corresponding thereto is closed, and a voltage corresponding to the depressed key is generated at the output terminal 12a and is applied to the processor or calculation circuit 6. 
     Numeral 17 denotes a monostable multivibrator driven by output pulses of the pulse generator 1, and an output terminal thereof is connected to the VCF 8 and the VCA 9 through an AND circuit 17a, and an envelope signal forming circuit or envelope generator 18. The output terminal 12a of the voltage generating circuit 12 is connected through a keying signal generating circuit 19 to a &#34;set&#34; terminal of the pulse generator 1, and &#34;reset&#34; terminals of the counter 2a. 
     The keying signal generating circuit 19 includes an operational amplifier, and is so arranged that a voltage &#34;V&#34; at the output terminal 12a, and a standard voltage &#34;-V&#34; are compared with one another, and when &#34;V&#34; is larger than &#34;ΔV&#34;, a &#34;1&#34; is generated, and when &#34;V&#34; is smaller than &#34;ΔV&#34; a &#34;O&#34;, is generated; and the pulse generator 1 is driven by the logic &#34;1&#34; signal and the counter 2a is reset thereby. An output terminal of the keying signal generating circuit 19 is connected to another input terminal of the AND circuit 7a. 
     Prior to explaining how words are memorized in the memory circuit 3, it should be understood that respective musical scale tones can be represented by digital signals of the binary scale, as shown in Table 1; in what follows the tones of a major scale will be denoted by first, second, third . . . . seventh tones of a first octave, second octave, and so on. 
     
                       Table 1______________________________________Tone designation Digital signal______________________________________C.sub.1          0 0 0 0 0 0C.sub.1.sup.♯            0 0 0 0 0 1D.sub.1          0 0 0 0 1 0D.sub.1.sup.♯            0 0 0 0 1 1E.sub.1          0 0 0 1 0 0F.sub.1          0 0 0 1 0 1F.sub.1.sup.♯            0 0 0 1 1 0G.sub.1          0 0 0 1 1 1G.sub.1.sup.♯            0 0 1 0 0 0A.sub.1          0 0 1 0 0 1A.sub.1.sup.♯            0 0 1 0 1 0B.sub.1          0 0 1 0 1 1C.sub.2          0 0 1 1 0 0C.sub.2.sup.♯            0 0 1 1 0 1D.sub.2          0 0 1 1 1 0D.sub.2.sup.♯            0 0 1 1 1 1E.sub.2          0 1 0 0 0 0F.sub.2          0 1 0 0 0 1F.sub.2.sup.♯            0 1 0 0 1 0G.sub.2          0 1 0 0 1 1______________________________________ 
    
     If it is now intended to achieve an arpeggio performance for obtaining a fifth tone, a third tone and a first tone of an octave higher by three octaves in relation to a depressed key, and therefore denoted as third octave, and subsequently thereto to obtain a fifth tone, a third tone and a first tone of a second octave, which is lower than the third octave, and still further subsequently thereto to obtain a fifth tone, a third tone and a first tone of a first octave in that order, followed by the first tone, the third tone and the fifth tone of the first octave, the first tone, the third tone and the fifth tone of the second octave, and the first tone, the third tone and the fifth tone of the third octave, it will be understood in view of Table 1 that there must be memorized respective words in respective addresses of the memory circuit 3 as shown in Table 2. 
     
                       Table 2______________________________________Address No.     Word          Tone     Octave______________________________________1         0 1 1 1 1 1   5th2         0 1 1 1 0 0   3rd      3rd octave3         0 1 1 0 0 0   1st4         0 1 0 0 1 1   5th5         0 1 0 0 0 0   3rd      2nd octave6         0 0 1 1 0 0   1st7         0 0 0 1 1 1   5th8         0 0 0 1 0 0   3rd      1st octave9         0 0 0 0 0 0   1st10        0 0 0 0 0 0   1st11        0 0 0 1 0 0   3rd      1st octave12        0 0 0 1 1 1   5th13        0 0 1 1 0 0   1st14        0 1 0 0 0 0   3rd      2nd octave15        0 1 0 0 1 1   5th16        0 1 1 0 0 0   1st17        0 1 1 1 0 0   3rd      3rd octave18        0 1 1 1 1 1   5th______________________________________ 
    
     If therefore a key of the tone C 1  is depressed and the key-switch 16-1 is thereby closed, a voltage corresponding to the tone C 1  is generated, and it is applied to the processor or calculation input terminal of the processor or calculation circuit 6, and also to the &#34;set&#34; terminal of the pulse generator 1, and the &#34;reset&#34; terminals of the counter 2a, so that the pulse generator 1 is activated or driven, and the counter 2a then counts output pulses thereof (FIG. 2A); and there are generated at the respective output terminals 2-1, 2-2, . . . . 2-18 of the decoder 2b timing pulses shown in FIG. 2 as 1, 2 . . . . 18. These timing pulses are applied in sequence to the respective addresses of the memory circuit 3 and thereby the words shown in Table 2 are outputted therefrom in sequence. Each of these words is converted by the D-A converter 4 into a corresponding analog signal, is gain-controlled by the gain control circuit 5, applied to the processor or calculation circuit 6, and is added onto, or subtracted from a voltage corresponding to the depressed tone key, that is, in the example shown, this is performed for the tone key C 1  at the calculation circuit 6, so that there is obtained an analog signal in step form, as shown in FIG. 2C. This analog signal is then applied to the VCO 7, so that the VCO 7 oscillates at a frequency corresponding to that analog signal. 
     In the meantime, the monostable multivibrator 17 is operated by the output pulses of the pulse generator 1 and generates negative pulses as shown in FIG. 2D, respective rising portions thereof driving the envelope signal generating circuit 18 so that there is obtained on its output side an envelope waveform as shown in FIG. 2E. Thus, the output signal of the VCO 7 is modulated by the VCF 8, the envelope modulated signal being applied to the VCA 9, so that there is obtained an output signal therefrom as shown in FIG. 2F. Thus, since the depressed key is the tone key C 1 , there can be obtained an arpeggio performance beginning with the fifth tone G 3  of an octave higher by 3 octaves than the octave including the tone C 1 , resulting in the series G 3  E 3  C 3 , G 2  E 2  C 2 , G 1  E 1  C 1 , C 1  E 1  G 1 , C 2  E 2  G 2 , C 3  E 3  G 3 , the suffixes denoting respective octaves. If, then, the depressed key is released, the output pulses of the pulse generator 1 disappear, and the arpeggio performance ceases. 
     If the tone key D 1  is depressed, in almost the same manner as above, an arpeggio including the notes A 3  F 3 .sup.♯ D 3 , A 2  F 2 .sup.♯ D 2 , A 1  F 1 .sup.♯ D 1  F 1 .sup.♯ A  1 , D 2  F 2 .sup.♯ A 2 , D 3  F 3 .sup.♯ A 3  can be obtained. 
     For obtaining an arpeggio performance of the type which moves from a lower octave to a higher octave in relation to a depressed key, respective words as shown in Table 3 are memorized in respective addresses of the memory circuit 3. 
     
                       Table 3______________________________________Address No.     Words         Tone     Octave______________________________________1         0 0 0 0 0 0   1st2         0 0 0 1 0 0   3rd      1st octave3         0 0 0 1 1 1   5th4         0 0 1 1 0 0   1st5         0 1 0 0 0 0   3rd      2nd octave6         0 1 0 0 1 1   5th7         0 1 1 0 0 0   1st8         0 1 1 1 0 0   3rd      3rd octave9         0 1 1 1 1 1   5th10        1 0 0 0 1 0   1st11        1 0 1 0 0 0   3rd      4th octave12        1 0 1 0 1 1   5th13        1 1 0 0 0 0   1st14        1 1 0 1 0 0   3rd      5th octave15        1 1 0 1 1 1   5th______________________________________ 
    
     If, therefore, a key of the tone C 1  is depressed, for the memory sequence shown in FIG. 3, there is obtained an arpeggio performance including in sequence C 1  E 1  G  1 , C 2  E 2  G 2 , C 3  E 3  G 3 , C 4  E 4  G 4 , C 5  E 5  G 5  by almost the same operation as above-described. 
     The operation of the pulse generator 1 shown in FIG. 2 has been described for the case where it generates sequentially, pulses identical in waveform, but an arpeggio performance according to any desired rhythm can be obtained, if the pulse generator 1 includes a rhythm pulse generator which generates pulses according to a specific rhythm. A rhythm pulse generator employed, for example, in generating a rhythm for an electronic musical organ may be used. 
     A rhythm pulse generator 1afor obtaining a rhythm as shown in music notation in FIG. 4A, and in time sequence in FIG. 4B, is constructed as shown in FIG. 3. Thus the rhythm pulse generator 1a includes a combination of a main oscillator 1a-1, two flip-flop circuits 1a-2 and 1a-3, two AND circuits 1a-4 and 1a-5, and a single OR circuit 1a-6. 
     Thus, timing pulses according to a rhythm as shown in FIG. 4, denoted respectively by waveforms 1,2 . . . . 15 of FIG. 4 can be obtained from the timing pulse generator 2, and if the words as shown in the Table 3 are memorized in the respective addresses of the memory circuit 3, and a key of the tone C 1  is depressed, an analog signal as shown in FIG. 4D is obtained at the output terminal of the processor or calculation circuit 6, and an output signal having an envelope as shown in FIG. 4E is obtained at the output terminal of the VCA 9, so that an arpeggio performance with the notes C 1  E 1  G 1 , C 2  E 2  G 2 , C 3  E 3  G 3 , C 4  E 4  G 4 , C 5  E 5  G 5 , in the order shown is obtained. 
     FIG. 5 shows another embodiment of the present invention. In this embodiment, the pulse generator 1 of FIG. 1 is used, and a pulse width changing circuit 20 is interposed between the pulse generator 1 and the timing pulse generator 2, so that a rhythm pulse can be applied to the timing pulse generator 2 in almost the same manner as in the case of the aforedescribed rhythm pulse generator. 
     Thus, the pulse width changing circuit 20 includes two flip-flop circuits 21 and 22, two coincidence circuits 23 and 24, a NAND circuit 25 and a rhythm-pattern setting-circuit 26, the rhythm pattern setting circuit 26 including a read-only memory. The respective input terminals of the circuit 26 are connected to respective output terminals 2-1, 2-2 . . . . 2-18 of the timing pulse generator 2, and two output terminals 26a, 26b of the circuit 26 are connected to the coincidence circuits 23 and 24. In this embodiment, words as shown in Table 4 are memorized in respective addresses of the rhythm pattern setting circuit 26. 
     
                                           Table 4__________________________________________________________________________Address No.   1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18__________________________________________________________________________Output ter-minal a 1 1 0 1 1 0 1 1 0 1  1  0  1  1  0  1  1  0Output ter-minal b 1 0 1 1 0 1 1 0 1 1  0  1  1  0  1  1  0  1Tone length__________________________________________________________________________ 
    
     If, now, a key is depressed, in almost the same manner as in the foregoing example, the pulse generator 1 is driven, the counter 2a and the flip-flop circuits 21, 22 are reset, and the envelope signal forming circuit 18 is driven through the keying signal generating circuit 19a, so that a logic &#34;1&#34; is obtained at the first output terminal of the decoder 2b, and the first addresses of the memory circuit 3 and of the rhythm pattern setting circuit 26 are selected. Thus, the output terminals 26a and 26b of the rhythm pattern setting circuit 26 become &#34;1, 1&#34; as will be seen from the foregoing Table 4. In the meantime, the output pulses of the pulse generator 1 are frequency-divided by the flip-flop circuits 21 and 22, and when the output terminals 21a and 22a thereof become &#34;1, 1&#34; the outputs of the coincidence circuits 23, 23 become &#34;1, 1&#34;, respectively, the output of the NAND circuit 25 becoming &#34;0&#34;, and by the latter&#39;s falling output the counter 2a is driven, so that there is obtained a logic &#34;1&#34; at the second output terminal 2-2 of the decoder 2b, and at the same time the flip-flop circuits 21 and 22 are reset; also, when the output of the flip-flop circuits becomes &#34;1, 0&#34;  the latter coincides with the output &#34;1, 0&#34; (the words in the 2nd address of the Table 4) of the rhythm pattern setting circuit 26, the output of the NAND circuit 25 falls from &#34;1&#34; to &#34;0&#34;, and by that falling output the counter 2a is driven, and a logic &#34;1&#34; is obtained at the third output terminal of the decoder 2b. Thus, each time an output signal of the flip-flop circuits 21,22 and an output signal of the rhythm pattern setting circuit coincide with one another, the counter 2a is driven by the falling output of the NAND circuit 25, and thereby there are obtained at the output terminals 2-1, 2-2 . . . . of the decoder 2b timing pulses corresponding to the set values of the rhythm pattern setting circuit 26 as shown in FIGS. 6-1, 6-2, 6-3 to 6-6. Thus, any desired rhythm pattern can be obtained by the words in the addresses of the rhythm pattern setting circuit 26 being properly set. 
     FIG. 7 shows a further embodiment example of the present invention, the memory circuit 3 being composed of a read-write memory 3a, and any desired words can be written thereinto by depressing a key. The read-write memory 3a shown in this Figure includes plural flip-flop circuits, the latter including a decoder identical to the decoder 2a, and having selective input terminals 3a-1 . . . . 3a-10, data input terminals 3b-1 . . . . 3b-6, output terminals 3c-2 . . . . 3c-6, a memory control terminal ME and a write-in terminal WE. The selective input terminals 3a-1 . . . . 3a-6 are connected to the counter 2a, and the data input terminals 3b-1 . . . . 3b-6 are connected to plural input terminals of an A-D converter 27, the latter being connected to the output terminals 12a of the voltage generating circuit 12. The key-switches 16-1, 16-2 to 16n have a second keying signal generating circuit 28 which includes key-switches 28-1, 28-2 to 28n, and stationary contacts of these key-switches 28-1, 28-2 to 28n are connected in common to the ground, and movable contacts thereof are connected in common to an electric source terminal 30 through a resistance 29, and to an output terminal 31. The output terminal 31 is connected to a gate circuit 32 interposed between the pulse generator 1 and the counter 2a. The gate circuit 32 includes a combination of NAND circuits 33, 34, 35 an inverter circuit 36, and a switch 37 for control of these circuits 33, 34, 35, 36. The switch 37 is further connected to a write-command circuit 38 for the read-write memory 3a. The write-command circuit 38 includes a lead 39 connecting the switch 37 to the write-in terminal WE, a pulse forming circuit 41, a flip-flop circuit 42, and a NOR circuit 43 interposed between a lead 40 and the memory control terminal ME for connecting the switch 37 to the latter, so that when the switch 37 is ON, the terminals WE, ME become low and write-in is performed, and on completion of the writing-in of each address the flip-flop circuit 42 is reversed, so that the terminal ME becomes high and thus the write-in is inhibited. 
     Numeral 44 denotes a reset circuit for resetting the counter 2a when the switch 37 is closed, and this circuit 44 includes a NAND circuit 45, and an inverter 46 connected to the switch 37, and the output terminal 31 of the key-switches 28-1, 28-2 to 28n. 
     In almost the same manner as in the case shown in FIG. 1, plural output terminals 3c-1 . . . . 3c-n of the read-write memory 3a are connected to the D-A converter 4. Numeral 47 denotes a change-over switch which serves to directly control the VCO 7 by an output signal of the voltage generating circuit 12, so as to confirm a tone corresponding to the word written in. 
     If, now, the switch 37 is ON, and the change-over switch 47 is changed over to the side of the output terminal 12a of the voltage generating circuit 12, as shown by dotted lines, the terminals WE and ME become low, and thereby the gate circuit 32 is interrupted by the NAND circuit 33 due to an output of the rhythm pulse generator 1, and is ready for passing of pulses generated by closing of the second key-switches 28-1, 28-2 to 28n, and the counter 2a is reset. 
     If, then, the key of the tone C 1  is depressed, the key-switches 16-1, 28-1 are simultaneously closed. By closing of the key-switch 16-1, a voltage of a level corresponding to the tone C 1  can be obtained at the output terminals 12a, and the same is converted by the A-D converter circuit 27 into a digital signal &#34;000000&#34;, and is applied to the read-write memory 3a through the data input terminals 3b-1, . . . . 3b-6. By closing of the key-switch 28-1, a falling pulse a as shown in the same Figure is applied to the counter 2a through the NAND circuits 34 and 35 of the gate circuit 32, and an output of the counter 2a is applied to the selective terminals 3a-1 . . . . 3a-10 of the read-write memory 3a; the first address is selected by the internal decoder. Thus, &#34;000000&#34; is memorized in the first address. At that time, the voltage obtained at the output terminals 12a of the voltage generating circuit 12 is applied to the VCO 7, so that the tone C 1  can be obtained from the speaker 11, and it can thus be confirmed that the tone C 1  has been memorized. 
     If, next, the key of the tone E 1  is depressed, in almost the same manner as above, a voltage corresponding to the tone E 1  is generated, and &#34;00100&#34; is outputted from the A-D converter 27, and at the same time the second address is selected and thus &#34;000100&#34; is memorized therein. 
     Thus, by depressing keys in succession, tones corresponding to respective depressed keys are memorized in digital signal form in respective addresses of the memory circuit 3a. 
     Thus, if memorizing in the respective addresses is completed, a logic &#34;1&#34; of the last output terminal 2a-n of the counter 2a is applied through the pulse forming circuit 41 to the flip-flop circuit 42, whereby the circuit 42 is reversed so that the terminal ME may become high. Accordingly, any write-in is no longer possible, even if a key is depressed. 
     If the switch 37 is subsequently opened and the reversed switch 47 is changed over to a position shown by the solid lines, one input terminal of each of the NAND circuits 34 and 35 becomes high, so that a condition is obtained, where, if any of the keys are depressed, pulses from the rhythm pulse generator 1 are applied to the counter 2a through the NAND circuits 33, 35, and the terminals WE, ME become both high. 
     If a key is then depressed, it operates in such a manner as mentioned in connection with FIG. 1, and the words memorized in the read-write memory 3a are outputted in sequence for an arpeggio performance. 
     FIG. 8 shows an additional embodiment of the present invention. In this embodiment, a word converting circuit 50 for converting a word of major scale into a word of minor scale is interposed between the memory circuit 3 and the D-A converter 4, so that a performance of a minor scale is made possible by the words in the memory circuit 3 being left as those of major scale and being converted into words of minor scale. 
     The word converting circuit 50 includes exclusive OR circuits 51-1, 51-2 and 51-3 interposed between the second to fourth memory output wires 3-2 . . . . 3-4 and the memory circuit 3, an OR circuit 52 connected to the first to fourth output wires 3-1 . . . . 3-4, a NOR circuit 53 connected at one of its input terminals to the output terminal of the circuit 52, a switch 54 interposed between the other input terminal of the circuit 53 and ground, and an inverter 55 interposed between the second output wire 3-2 and the OR circuit 52, and output terminal of the NOR circuit 53 being connected to other input terminals of the exclusive OR circuits 51-1, 51-2 and 51-3. Numeral 45 denotes an electric source terminal. 
     Under the condition (major scale) that the switch 54 is opened as illustrated, an output of the NOR circuit 53 is &#34;0&#34;, and the other input terminals of the respective exclusive OR circuits 51-1. 51-2, 51-3 are &#34;0&#34;, so that respective words &#34;0000&#34; &#34;0100&#34; &#34;0111&#34;, for instance, outputted form the memory circuit 3, are applied to the D-A converter 4, and a major scale performance is obtained. 
     For a minor scale performance to be obtained the switch 54 is closed, and &#34;0000&#34; is outputted from the memory circuit 3; an output of the OR circuit 52 is then a logic &#34;1&#34;, and an output of the NOR circuit 53 is then a logic &#34;0&#34;, and therefore in almost the same manner as above &#34;0000&#34; is applied to the D-A converter 4. If, &#34;0100&#34; is then outputted, an output of the OR circuit 52 becomes &#34;0&#34;, and an output of the NOR circuit 53 becomes &#34;1&#34;, and therefore an output of the exclusive OR circuits 51-1, 51-2 and 51-3 becomes &#34;0011&#34; and consequently &#34;0011&#34; is fed to the D-A converter 4, being a word of the minor scale. If &#34;0111&#34; is outputted from the memory circuit, an output of the OR circuit 52 becomes &#34;1&#34;, and an output of the NOR circuit 53 becomes &#34;0&#34;, and therefore the word &#34;0111&#34; is applied to the D-A converter 4. Thus, only the word of the major scale &#34;0100&#34; (tone E 1 ) converted into a word of the minor scale &#34;0011&#34; (tone D 1 .sup.♯) is applied to the D-A converter 4, and thereby a minor performance is obtained. 
     In the case of this embodiment, it is only required that &#34;. . . . 100&#34; is converted into &#34;. . . . 011&#34;, so that, as will be clear from the Table 1, converting into the minor scale becomes possible only in the first octave, the third octave and the fifth octave. Accordingly, an arpeggio performance becomes possible, where, for instance, C E G, C E G, . . . . in the first, third and fifth octaves are repeated. 
     Thus, according to the present invention, by only a single key being kept depressed, an arpeggio performance is obtainable automatically during that key depression period, and since the arpeggio performance is obtained from a tone corresponding to the key being depressed, an arpeggio performance corresponding to the playing of an electronic organ or the like can be carried out, and if a memory circuit includes a read-write memory, a word corresponding to a key can be memorized by depression of that key in that memory and also be reproduced, and consequently any desired arpeggio performance can be obtained at any time, and it becomes additionally possible that when a word of a major scale has been memorized in the memory circuit, a performance of converting it into a corresponding minor scale can be obtained.