Abstract:
An embodiment of a self-supply circuit, for a voltage converter that converts an input voltage into an output voltage and has a main switch and a controller, designed to control switching of the main switch for controlling the output voltage; the self-supply circuit is provided with: a charge accumulator, which is connected to the controller and supplies a self-supply voltage to the same controller; a generator, which supplies a charge current to the charge accumulator; and an auxiliary switch, which has a first conduction terminal in common with a respective conduction terminal of the main switch and is operable so as to control transfer of the charge current to the charge accumulator. In particular, the self-supply circuit is provided with a precharge stage, connected to the auxiliary switch, which carries out a precharging of an intrinsic capacitance of the auxiliary switch before a turning-off transient of the main switch ends.

Description:
PRIORITY CLAIM 
     The present application claims the benefit of Italian Patent Application Serial No.: TO2007A000860, filed Nov. 29, 2007, which application is incorporated herein by reference in its entirety. 
     RELATED APPLICATION DATA 
     This application is related to the U.S. patent application Ser. No. 12/324,194 entitled ISOLATED VOLTAGE CONVERTER WITH FEEDBACK ON THE PRIMARY WINDING, AND CORRESPONDING METHOD FOR CONTROLLING THE OUTPUT VOLTAGE, filed Nov. 26, 2008, application Ser. No. 12/324,062 entitled ISOLATED VOLTAGE CONVERTER WITH FEEDBACK ON THE PRIMARY WINDING, AND CORRESPONDING METHOD FOR CONTROLLING THE OUTPUT VOLTAGE, filed Nov. 26, 2008 and application Ser. No. 12/324,412 entitled ISOLATED VOLTAGE CONVERTER WITH FEEDBACK ON THE PRIMARY WINDING AND PASSIVE SNUBBER NETWORK, AND CORRESPONDING CONTROL METHOD, filed Nov. 26, 2008 and which are incorporated herein by reference in their entireties. 
     TECHNICAL FIELD 
     An embodiment of the present disclosure relates to a self-supply circuit and method for a voltage converter, and more precisely for a switched-mode voltage converter, controlled in pulse-width modulation (PWM). 
     BACKGROUND 
     As is known, switched-mode voltage converters, which are preferred for their high efficiency and their reduced size as compared to classic linear converters, usually implement a self-supply technique that enables, starting from non-regulated input voltages, regulated output voltages to be obtained having an amplitude greater or smaller than the input voltage. 
     One of the most common types of switched-mode voltage converters is the isolated accumulation (“flyback”) type. A flyback voltage converter enables conversion of a first voltage value (present on an input of the converter) into a second voltage value (supplied on the output of the converter), maintaining the input and output of the converter galvanically isolated by the use of a transformer. 
       FIG. 1  shows a circuit diagram of a known voltage converter  1 , of a flyback type. 
     The voltage converter  1  has an input  2  to which an input voltage V in  (for example, supplied by a rectifier circuit, not illustrated, starting from the mains voltage) is applied, and an output  3  supplying an output voltage V out , and comprises a transformer  4 , having a primary side and a secondary side, which is electrically isolated from the primary side. In particular, the transformer  4  has a primary winding  4   a  coupled to the input  2 , a secondary winding  4   b  coupled to the output  3  by interposition of a first diode  6 , and an auxiliary winding  4   c  (the latter set on the primary side of the transformer  4 ). An output capacitor  7  is coupled to the output  3 . A main transistor  10 , in particular an N-channel MOS transistor, is coupled between an internal node  8 , which is in turn coupled to the primary winding  4   a , and a reference terminal  9  (for example, a ground terminal). A bulk capacitor  11  is coupled between the input  2  and the reference terminal  9 . 
     The voltage converter  1  further comprises: a PWM controller  12 , used for regulation of the output voltage V out , having a supply terminal  13 , which receives a supply voltage V cc  and is coupled to the auxiliary winding  4   c  via the interposition of a second diode  14 , and an output terminal, which is coupled to the gate terminal of the main transistor  10  and supplies a PWM signal for controlling opening and closing of the main transistor  10 ; and a self-supply circuit  15 , having an input terminal coupled to the input  2  of the voltage converter  1 , and an output terminal, which coincides with the supply terminal  13  of the PWM controller  12  and supplies the supply voltage V cc . 
     In detail, the self-supply circuit  15  comprises: an accumulation capacitor  16 , coupled between the supply terminal  13  and the reference terminal  9 ; and a start-up resistor  18  coupled between the input terminal  2  of the voltage converter and the supply terminal  13 . 
     In a known way, the function of the self-supply circuit  15  is that of supplying the PWM controller  12  to enable it to regulate the output voltage V out . In use, the accumulation capacitor  16  is initially charged by the input voltage V in , through the start-up resistor  18 . The PWM controller  12  switches on when the value of the voltage on the accumulation capacitor  16  reaches a first threshold value V ccon , for example, equal to 13.5 V. Next, the PWM controller  12  receives the supply voltage V cc  directly from the auxiliary winding  4   c  of the transformer  4 . 
     The start-up resistor  18  is used in the initial turn-on phase (start-up) of the voltage converter  1  for supplying the turn-on supply to the PWM controller  12 . However, a current flows through the start-up resistor  18  also at the end of the initial start-up phase, causing a considerable dissipation of power and reducing the efficiency of the voltage converter  1 . 
     In addition, if the converter is used for regulating also an output current I out , for example as a battery-charger, the auxiliary winding  4   c  is also used (in a known way that is not described in detail herein) for supplying a feedback signal to the PWM controller  12 , for regulating both the output voltage V out  and the output current I out . In this case, the voltage on the auxiliary winding  4   c  might not have a value sufficient for supplying the PWM controller  12 . Consequently, also during the switching phase in which the PWM controller  12  is active, the PWM controller  12  is self-supplied through the start-up resistor  18 , thus increasing the total power dissipation. 
       FIG. 2  shows a different circuit embodiment of the self-supply circuit  15  of the voltage converter  1  (the remaining elements of the voltage converter, which are present also in this embodiment, are not illustrated again here for clarity reasons). 
     In detail, the self-supply circuit  15  comprises: the accumulation capacitor  16  (previously described); an auxiliary transistor  21 , in particular an N-channel MOS transistor having a drain terminal coupled to the input  2  of the voltage converter  1  and receiving the input voltage V in ; a first biasing resistor  22 , having, for example, a value of resistance of 15 MΩ and coupled between the input  2  of the voltage converter  1  and the gate terminal of the auxiliary transistor  21 ; a second biasing resistor  23 , coupled between the gate terminal of the auxiliary transistor  21  and the reference terminal  9 ; a current generator  24 , which is coupled between the source terminal of the auxiliary transistor  21  and the supply terminal  13  of the PWM controller  12 , via the interposition of a third diode  25 , and has a control terminal; and a switch  26 , coupled between the gate terminal of the auxiliary transistor  21  and the reference terminal  9 . 
     The self-supply circuit  15  further comprises a control logic  28 , having a first input coupled to the gate terminal of the auxiliary transistor  21 , a second input coupled to the supply terminal  13 , a first output supplying a control signal V cc     —     OK  to a control terminal of the switch  26 , and a second output supplying to the control terminal of the current generator  24  an activation signal HV_EN. 
     In use, during a start-up phase, when the input voltage V in  (following upon progressive charging of the bulk capacitor  11 , shown in  FIG. 1 ) reaches a given threshold value, for example, equal to 80 V, the control logic  28  turns on the current generator  24  via the activation signal HV_EN, enabling a current I charge  to flow through the auxiliary transistor  21 . This current I charge , for example, having a value of 1 mA, charges the accumulation capacitor  16 , raising the supply voltage V cc  across its terminals in a substantially linear way. When the supply voltage V cc  reaches the first threshold value V ccon , the signal V cc     —     OK  generated by the control logic  28  closes the switch  26 , causing turning-off of the auxiliary transistor  21  and interruption of the flow of current I charge  through the same auxiliary transistor  21  and the current generator  24 . The PWM controller  12  ( FIG. 1 ) is then supplied by the energy stored in the accumulation capacitor  16 , as long as the auxiliary winding  4   c  generates a voltage sufficiently high to sustain the operations of regulation of the controller. 
     The residual consumption of the self-supply circuit  15  is hence due only to the presence of the first biasing resistor  22 , and is typically from 50 to 70 times lower than that of the circuit of  FIG. 1 . 
     The self-supply circuit  15  also intervenes for charging the accumulation capacitor  16  during the switching phase of the main transistor  10  ( FIG. 1 ), in the case where the voltage on the auxiliary winding is not sufficient to supply the supply voltage V cc , for example, in the case of operation as a battery-charger, when the battery is run down or in the presence of overload at the output. In detail, as soon as the supply voltage V cc  drops below a second threshold value V ccrestart , for example, equal to 10.5 V, the control logic  28  controls opening of the switch  26  by means of the signal V cc     —     OK , and enables the current generator  24  by means of the signal HV_EN so as to charge the accumulation capacitor  16  via the current I charge . 
     In order to contain costs, it is possible to integrate in one and the same chip (not illustrated) the auxiliary transistor  21  and the main transistor  10 . In this case, as shown in  FIG. 3 , the auxiliary transistor  21  and the main transistor  10  share the drain terminal. The drain terminal is coupled to the internal node  8  ( FIG. 1 ), which is in turn coupled to the primary winding  4   a  of the transformer  4 , and is at a voltage which is not constant (i.e., which switches between a value of approximately 0 V and the value of the input voltage V in ). 
     The self-supply circuit  15  of  FIG. 3  thus enables charging of the accumulation capacitor  16  only when the main transistor  10  is turned off, i.e., when the voltage of the aforesaid drain terminal (or, in a similar way of the internal node  8 ) is high and equal to the value of the input voltage V in . Consequently, in the case where the self-supply circuit  15  is also used for self-supply of the PWM controller  12  through the accumulation capacitor  16  during the switching phase of the PWM controller  12 , the current I charge  can charge the accumulation capacitor  16  only during the OFF phase of the switching period, when the voltage of the drain terminal is high. This condition can jeopardize proper operation of the self-supply circuit  15 , especially for high values of duty cycle (higher than 50%) of the switching signal that regulates operation of the voltage converter  1 , and consequently considerably limits the maximum value of duty cycle that can be obtained. 
     In fact, the auxiliary transistor  21  should be able to turn on rapidly during turning-off of the main transistor  10  in order to maximize the useful time (substantially corresponding to the OFF phase of the switching signal) for charging the accumulation capacitor  16 . However, the switching rate of the auxiliary transistor  21  is limited by the gate capacitance of the latter and by the presence of the first biasing resistor  22 , the value of which is commonly chosen high (for example, equal to 15 MΩ) in order to minimize the losses. 
     In use, when the main transistor  10  is turned on, the voltage on the internal node  8  is approximately 0 V and the auxiliary transistor  21  is off. When the main transistor  10  is turned off, the signal V cc     —     OK  generated by the control logic  28  controls opening of the switch  26 , the voltage on the drain terminal of the auxiliary transistor  21  starts to increase, and the gate capacitor of the same auxiliary transistor  21  is charged, first by the injection of charge coming from the capacitance between the drain and gate terminals and then, when the voltage on the drain terminal reaches a sufficiently high value, through the biasing resistor  22 . Both of these contributions of charge may not be, however, sufficient to turn on the auxiliary transistor  21  completely, and to supply the current I charge  required by the current generator  24 , in a reasonable time. Consequently, a substantial part of the time available for charging the accumulation capacitor  16  may not be exploited. Therefore, in order to guarantee in any case the self-supply operation, it is hence common to limit the duty cycle to a value lower than 50%, for example equal to 45%. 
     SUMMARY 
     Embodiments of the present disclosure include a self-supply circuit and method that will be free from the drawbacks described above, and in particular that will enable self-supply to be guaranteed in a voltage converter without setting any limitations on the duty cycle. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments of the disclosure are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein: 
         FIG. 1  shows a circuit diagram of a flyback voltage converter of a known type; 
         FIG. 2  shows a circuit diagram of a self-supply circuit of the voltage converter of  FIG. 1 ; 
         FIG. 3  shows a different circuit diagram, of a known type, of the self-supply circuit; 
         FIG. 4  shows part of a circuit diagram of a voltage converter with highlighted therein a self-supply circuit, made according to an embodiment of the present disclosure; 
         FIG. 5  shows a possible circuit embodiment of a precharge stage within the self-supply circuit of  FIG. 4 ; 
         FIGS. 6 and 7  show the plots in time of the waveforms of electrical signals involved during a precharge step in the voltage converter of  FIG. 4 ; 
         FIG. 8  shows a possible embodiment of a precharge control block inside the precharge stage of  FIG. 5 ; 
         FIG. 9  shows the plots of electrical signals involved during the precharge step; 
         FIG. 10  shows a first embodiment of a portion of the precharge-control block; 
         FIG. 11  shows the plots of the signals involved during the precharge step, using the precharge control block of  FIG. 10 ; 
         FIG. 12  shows a second embodiment of the precharge control block; 
         FIG. 13  shows the plots of the signals involved during the precharge step, using the precharge control block of  FIG. 12 ; 
         FIG. 14  shows a third embodiment of the precharge control block; and 
         FIG. 15  shows the plots of the signals involved during the precharge step, using the precharge control block of  FIG. 14 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 4  shows a self-supply circuit  30 , made according to an embodiment of the present disclosure. Elements that have already been described with reference to the known art are designated by the same reference numbers and are not described again. In particular, the self-supply circuit  30  may find use in a voltage converter  1  of the type described with reference to  FIG. 1  (not illustrated in  FIG. 4 ). 
     In detail, the self-supply circuit  30  differs from the one described in  FIG. 3 , in so far as it comprises a precharge stage  31  coupled (in this embodiment coupled) directly to the gate terminal of the auxiliary transistor  21 . In particular, it should be noted that, even though they are not described again in detail, the second biasing resistor  23  and the control logic  28  are present (for greater clarity, these elements are not shown again in the subsequent figures). 
     The precharge stage  31  enables a rapid switching of the auxiliary transistor  21  to be obtained during each switching cycle, in so far as it has the function of precharging the capacitance between the gate and source terminals of the auxiliary transistor  21 , whilst the voltage on the drain terminal is still at a low value, during or at the end of the turning-on phase (ON phase of the switching period) of the main transistor  10 . In this way, following upon turning-off of the main transistor  10 , when the voltage present on the internal node  8  starts to increase, the auxiliary transistor  21  is already turned on, and the current generator  24  can generate the current I charge  for charging the accumulation capacitor  16  without appreciable time delays. It should be noted that the precharge stage  31  has also the function of controlling turning-off of the auxiliary transistor  21  in order to interrupt the flow of the current I charge . 
     In particular, the value of the current I charge  generated by the current generator  24  is determined as a function of the maximum duty cycle D max  of the switching signal, and of the current consumption I cons  of the voltage converter  1 , and must satisfy the following condition: 
     
       
         
           
             
               I 
               charge 
             
             &gt; 
             
               
                 I 
                 cons 
               
               
                 1 
                 - 
                 
                   D 
                   max 
                 
               
             
           
         
       
     
     When this relation is satisfied, the self-supply operation is carried out without limiting the duty cycle of the switching signal. 
     In fact, the average charge current of the accumulation capacitor  16  is
 
 I   average   =I   charge   ·D   aux  
 
where D aux  is the duty-cycle of the current I charge , i.e., the ratio between the time used for charging the accumulation capacitor  16  and the switching period. Since, as discussed previously, charging of the accumulation capacitor  16  is enabled when the main transistor is turned off we have:
 
 D   aux =1 −D   max  
 
     The average current I average  is such as to charge the accumulation capacitor  16  and simultaneously sustain the consumption of the PWM controller  12 . Consequently, in order for this to occur, the following expression (wherefrom the aforesaid condition derives) holds:
 
 I   average =(1 −D   max )· I   charge   &gt;I   cons  
 
     As shown in  FIG. 5 , in a possible embodiment, the precharge stage  31  comprises: a first precharge switch  33 , coupled between the gate terminal of the auxiliary transistor  21  and the reference terminal  9 ; a second precharge switch  34 , coupled between the source terminal of the auxiliary transistor  21  and the reference terminal  9 ; a third precharge switch  35 , coupled between the gate terminal of the auxiliary transistor  21  and the supply terminal  13  of the PWM controller  12  (and hence to the accumulation capacitor  16 ); and a precharge control block  36 , designed to generate respective control signals for the first, second, and third precharge switches  33 ,  34 ,  35  such as to implement self-supply management. In detail, the first precharge switch  33  is controlled in opening and closing by a logic signal HV_EN_G, the second precharge switch  34  is controlled in opening and closing by a logic signal HV_EN_S, and the third precharge switch  35  is controlled in opening and closing by a logic signal EN_PRE. 
     In particular, when the current generator  24  is disabled (during the ON phase of the switching period of the main transistor  10 ), the first and second precharge switches  33 ,  34  are closed (signals HV_EN_G and HV_EN_S high), and the third precharge switch  35  is open (signal EN_PRE low), thus connecting the source and gate terminals of the auxiliary transistor  21  to the reference terminal  9 . At the end of the ON phase of switching of the main transistor  10  (as will be clarified hereinafter), the first precharge switch  33  is controlled in opening (signal HV_EN_G low), whilst the second and third precharge switches  34 ,  35  are controlled in closing (signals HV_EN_S and EN_PRE high). In this way, the source terminal of the auxiliary transistor  21  is coupled to the reference terminal  9 , and the gate terminal directly to the supply voltage V cc , thus starting precharging of the gate-source capacitance of the auxiliary transistor  21  to the supply voltage V cc . 
     Before the voltage on the drain terminal of the auxiliary transistor  21  starts to increase, or at the moment in which the same voltage starts to increase, the second and third precharge switches  34 ,  35  are controlled in opening (signals HV_EN_S and EN_PRE low), given that the precharging phase can be considered completed. It should be noted that the auxiliary transistor  21 , in this situation, is already turned on, and the charge current I charge  can immediately flow (as soon as the voltage at the internal node  8  becomes high) through the current generator  24 , thus charging the accumulation capacitor  16  so that the entire OFF phase of the switching signal is exploited. 
       FIG. 6  shows the waveforms of the voltage on the drain terminal, designated by V (drain) , on the gate terminal, designated by V (gate) , and on the source terminal, designated by V (source) , of the auxiliary transistor  21 , and of the charge current I charge . Following the switching of the main transistor  10  (instant of times t 1  and t 2 ), the waveform of the current I charge  follows the waveform of the voltage on the drain terminal V (drain) , responding substantially immediately to its variations, thanks to the precharging phase managed by the precharge stage  31 . 
       FIG. 7  shows an enlarged portion of the aforesaid waveforms, approximately upon switching at the instant of time t 2 , together with the plot of the logic signals HV_EN_G, HV_EN_S, and EN_PRE, with highlighted the precharging phase. It should be noted that the voltage on the gate terminal V (gate)  starts to rise after switching of the signal EN_PRE to the high value, as a result of the precharging operation. 
       FIG. 8  shows a possible embodiment of the precharge-control block  36  of the precharge stage  31 , which comprises a precharge logic  38 , and an end-of-precharge controller  39 . 
     The end-of-precharge controller  39  controls, as will be described in detail hereinafter, the appropriate instant of time at which the precharging phase of the auxiliary transistor  21  stops, generating an end-of-precharge signal END_PRE. 
     The precharge logic  38  receives at input, from the end-of-precharge controller  39 , the end-of-precharge signal END_PRE, and, from the PWM controller  12 , a control signal Q G , which is a function of a signal that controls, in a per-se known manner (for example, through a driver), the main transistor  10 . The precharge logic  38 , according to the end-of-precharge signal END_PRE and to the control signal Q G , generates the logic signals HV_EN_G, HV_EN_S, EN_PRE for management of the precharging phase. 
       FIG. 9  shows in detail the plots of the control signal Q G , of the logic signal EN_PRE, of the voltage on the gate terminal V (gate)  and of the voltage on the drain terminal V (drain)  of the main transistor  10 . In detail, when the control signal Q G  is active high, the main transistor  10  is in conduction (the voltage signal on the gate terminal V (gate)  is high), whilst the voltage signal on the drain terminal V (drain)  and the logic signal EN_PRE have a low value, indicating that the precharging phase has not started yet. As soon as the signal Q G  assumes a low value (instant of time t 1 ), the turning-off transient of the main transistor  10  starts, the voltage signal on the gate terminal V (gate)  starts to decrease, and the logic signal EN_PRE assumes a high value, indicating the start of the precharging interval. The precharging phase is disabled by the end-of-precharge controller  39  at the instant of time t 2 , before or at the end of a delay interval T delay  that represents a delay of turning-off of the main transistor  10 , after which the voltage signal on the gate terminal V (gate)  drops below the threshold voltage V TH  of the main transistor  10 , and the voltage on the drain terminal V (drain)  starts to increase. It is in fact expedient for the precharging phase to terminate before the voltage signal on the drain terminal V (drain)  starts to increase so as to prevent the phenomenon of cross-conduction between the drain terminal of the auxiliary transistor  21  and the reference terminal  9 . 
     As is shown in  FIG. 10 , in a first embodiment, the end-of-precharge controller, here designated by  39 ′, includes a comparator device  42 , which receives on a first input a reference voltage V REF , and on a second input the voltage on the gate terminal V (gate)  taken on the gate terminal of the main transistor  10 , and supplies at output the end-of-precharge signal END_PRE. When the value of the voltage on the gate terminal V (gate)  drops below the value of the reference voltage V REF , the end-of-precharge signal END_PRE assumes a logic value (for example, high) indicating the end of the precharging interval. 
     As is shown in  FIG. 11 , the value of the reference voltage V REF  may be chosen so as to be higher than the threshold-voltage value V TH  of the main transistor  10 , given that the voltage on the drain terminal V (drain)  starts to increase when the voltage on the gate terminal V (gate)  drops below the threshold-voltage value V TH . 
     A second embodiment of the end-of-precharge controller, designated by  39 ″, is shown in  FIG. 12 . The end-of-precharge controller  39 ″ comprises in this case a pulse generator  44 , which receives on an input thereof the control signal Q G , and generates at output the end-of-precharge signal END_PRE, here of an impulsive type, for example, having a pulse duration T pulse  equal to or shorter than the delay interval T delay . 
     As is shown in  FIG. 13 , the end-of-precharge controller  39 ″ is configured to generate the end-of-precharge signal END_PRE when the control signal Q G  assumes a low value. In addition, the precharge is stopped (the logic signal EN_PRE is brought to the low value) at the falling edge of the end-of-precharge signal END_PRE. 
       FIG. 14  shows a third embodiment of the end-of-precharge controller, designated by  39 ′″, in the case where the PWM controller  12  drives the main transistor  10  in such a way as to guarantee the so-called “soft-switching”. In this embodiment, the end-of-precharge controller  39 ′″ comprises: a negative-derivative detector (NDD)  45 , of a known type and not described in detail, which receives on an input thereof the voltage on the gate terminal V (gate)  and supplies on an output thereof a negative-derivative signal NEG_DER, as a function of the sign of the derivative of the voltage on the gate terminal; and a counter block  48 , which receives at input the negative-derivative signal NEG_DER and supplies on an output thereof the end-of-precharge signal END_PRE. 
     In detail, and as is shown in  FIG. 15 , at an instant t 1 , the control signal Q G  switches from the high level to the low level, controlling turning-off of the main transistor  10 . At the same instant, the logic signal EN_PRE assumes a high value, indicating start of the precharging interval. Next, at an instant t 2 , the voltage on the gate terminal V (gate)  starts to decrease and the negative-derivative signal NEG_DER assumes a high value, indicating that the derivative of the signal has assumed a negative value. At an instant t 3 , on account of the Miller effect, the voltage on the gate terminal V (gate)  assumes a stationary value. Approximately at the same instant of time t 3 , the negative-derivative signal NEG_DER returns to the low value, and the voltage on the drain terminal V (drain)  starts to increase slowly. When the Miller effect terminates (instant of time t 4 ), the voltage on the gate terminal V (gate)  starts to decrease again, the voltage on the drain terminal V (drain)  increases rapidly, and a new rising edge of the negative-derivative signal NEG_DER determines the end of the precharging interval (the logic signal EN_PRE assumes a low value). In particular, the counter block  48  detects the occurrence of the second pulse generated by the negative-derivative detector  45 , and consequently generates the end-of-precharge signal END_PRE. 
     The above-described embodiments, as well as other embodiments, of a self-supply circuit and method for a voltage converter may allow a number of advantages to be achieved. 
     In particular, precharging of the gate terminal of the auxiliary transistor  21  that manages the precharging phase enables maximization of the time interval useful for charging the accumulation capacitor  16 , so as to guarantee proper self-supply of the controller  12  of the voltage converter  1  without imposing limitations on the duty cycle of the switching signal. In fact, thanks to the preceding precharging phase, following turning-off of the main transistor  10 , the auxiliary transistor  21  is already turned on and the current generator  24  can supply the current I charge  to the accumulation capacitor  16  without appreciable time delays (after the main transistor is turned off). 
     Finally, it is clear that modifications and variations can be made to what is described and illustrated herein, without thereby departing from the scope of the present disclosure. 
     In particular, it is clear that, even though the embodiments have been described with particular reference to a configuration of a flyback type, these other embodiments may be applied in all converters (or regulators, or power supplies) operating in switched-mode (the so-called SMPS—Switch-Mode Power Supply). 
     In addition, the embodiments described above, as well as other embodiments, may be used irrespective of: the modality of energy transfer between the source and load, at a fixed or variable frequency; the particular circuit solution used for implementing operation of the individual blocks of the control circuit; the type of control switch; and the feedback mode envisaged on the primary side of the transformer. 
     Furthermore, one or both of T delay  and T pulse  may extend to or beyond a time when V (gate)  of the main transistor  10  equals V TH  of the main transistor. 
     Moreover, some or all of the components in the circuits of  FIGS. 1-5 ,  8 ,  10 ,  12 , and  14  may be discrete components, disposed on the same integrated circuit (IC) as others of the components, or disposed on ICs that are different from ICs on which others of the components are disposed. 
     Naturally, in order to satisfy local and specific requirements, a person skilled in the art may apply to the solution described above many modifications and alterations. Particularly, although the present disclosure has been described with a certain degree of particularity with reference to described embodiment(s) thereof, it should be understood that various omissions, substitutions and changes in the form and details as well as other embodiments are possible. Moreover, it is expressly intended that specific elements and/or method steps described in connection with any disclosed embodiment of the disclosure may be incorporated in any other embodiment as a general matter of design choice.