Abstract:
The disclosed invention relates to a re-synchronization system that operates in a switching arrangement receiving a plurality of incoming data packets. The switching arrangement is made of an active switch card that transmits the incoming data packets and a backup switch card that may be re-activated by an operator after replacement. The re-synchronization system is implemented in each switch card. When the backup switch card is re-activated, both switch cards receive the incoming data packets and the system of the invention allows to re-synchronized both switch cards by controlling the transmission of the incoming data packets out of each switch card until the same data packets are transmitted. The re-synchronization system further comprise storage for storing the incoming data packets and detector for detecting a re-synchronization information among the incoming data packets.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates to the transmission of data packets such as ATM packets between Local Area Networks (LAN) interconnected by a switch engine and relates in particular to a packet loss less system and method for packet switch cards re-synchronization.  
         BACKGROUND ART  
         [0002]    Local Area Networks (LAN) such as Ethernet or token-ring networks, are generally interconnected through hubs. The hub is a system made of LAN adapters that communicate together through a switch card. The switch card is mainly composed of input ports, output ports and a shared memory.  
           [0003]    The data packets received by the input ports are stored into the shared memory at address locations determined by queues containing the packet destination addresses. Then the packets are de-queued to be transmitted to the destination output ports.  
           [0004]    Any hardware failure on the switch card is damageable on the data packet transfer, and one common solution to prevent any hardware failure is to duplicate the switch card.  
           [0005]    This solution consists in having two switch cards, where one switch is active while the other is backup. During normal operation, both switches operate in parallel meaning that:  
           [0006]    they both receive the same commands coming from a Control Point of the switching system;  
           [0007]    they both receive the same data packets coming from the LAN adapters;  
           [0008]    they both transmit the same data packets. However, the LAN adapters receive the data packets from only the active switch card.  
           [0009]    In case of the active switch card replacement, the backup switch card is substituted to the active one and operates in place of this latter. The LAN adapters then receive the data packets from the newly connected backup switch. When the active switch card is re-activated, a major difficulty is to have the two switches re-synchronized on the same data packets. This problem is not solved in the existing switch systems which admit lost data packets.  
           [0010]    Therefore there is a need for a packet loss less system for data packet switch re-synchronization. The present invention offers such system.  
         SUMMARY OF THE INVENTION  
         [0011]    Accordingly, the main object of the invention is to provide a packet loss less re-synchronization system and associated method to process data transfer through active and backup switch cards without losing any data packet.  
           [0012]    In a preferred embodiment, the re-synchronization system operates in a switching arrangement that receives a plurality of incoming data packets. The switching arrangement is made of an active switch card that transmits the incoming data packets and a backup switch card that may be re-activated by an operator after replacement. The re-synchronization system is implemented in each switch card. When the backup switch card is re-activated, both switch cards receive the incoming data packets and the system of the invention allows to re-synchronized both switch cards by controlling the transmission of the incoming data packets out of each switch card until the same data packets are transmitted. The re-synchronization system further comprise means for storing the incoming data packets and means for detecting a re-synchronization information among the incoming data packets. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The above and other objects, features and advantages of the invention will be better understood by reading the following more particular description of the invention in conjunction with the accompanying drawings wherein:  
         [0014]    [0014]FIG. 1 is a schematic block diagram of a data transmission system including four LANs interconnected by a hub according to the principles of the invention;  
         [0015]    [0015]FIG. 2 represents schematically a redundant switching system where each adapter transfers/receives data packets to/from the two switches;  
         [0016]    [0016]FIG. 3 is a schematic block diagram of the incoming data packet flow structure located on each switch card of FIG. 2;  
         [0017]    [0017]FIG. 4 details the Lease Address Selector block of FIG. 3;  
         [0018]    [0018]FIG. 5 details the Release Address Selector block of FIG. 3;  
         [0019]    [0019]FIG. 6 details the Remote Switch Logic block of FIG. 3;  
         [0020]    [0020]FIG. 7 illustrates a data packet synchronisation within Fifo&#39;s content of the two switch cards;  
         [0021]    [0021]FIG. 8A and 8B are flow charts of the de-queue operations of the state machine of FIG. 5;  
         [0022]    [0022]FIG. 9 to FIG. 13 illustrate Fifo&#39;s content of the two switch cards during the steps of switch cards re-synchronization. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]    The invention is preferably implemented in a data transmission environment as illustrated on FIG. 1. For sake of simplicity, the environment is made of four Local Area Networks (LAN)  10 _ 1 ,  10 _ 2 ,  10 _ 3 , and  10 _ 4  but it could be extended to a plurality of LANs and as such a LAN is also denoted  10 _i in the description. LANs  10 _i are interconnected together by a hub  12  that may be of the type ATM, Ethernet, or token-ring. Each LAN is connected to a switching system  14  within the hub  12  by means of a respective adapter card  16 _ 1  for LAN  10 _ 1 , adapter card  16 _ 2  for LAN  10 _ 2 , adapter card  16 _ 3  for LAN  10 _ 3  and adapter card  16 _ 4  for LAN  10 _ 4 . Each adapter card (also denoted  16 _i) sends data packets by means of a data bus-in (bus-in  13 _ 1  to bus-in  13 _ 4 ) connected to input ports of the switching system  14 . Each adapter card receives data packets by means of a data bus-out (bus-out  15 _ 1  to bus-out  15 _ 4 ) connected to output ports of the switching system  14 . Then, a data bus-in  13 _i carries data packets from the respective adapter card  16 _i to switching system  14  and data bus-out ( 15 _i) carries data packets from switching system  14  to the adapter card  16 _i.  
         [0024]    Referring now to FIG. 2, the switching system  14  is zoomed. Switching system is made of two distinct switch cards, an active switch card  14 _ 1  and a backup switch card  14 _ 2 . These two switch cards communicate through a switch bus  24  and are controlled by Control Point card block  21  through bus  20 . The system of the invention is preferably implemented within the transmit data path of each switch card. Each switch card contains a control system operating with a shared memory in read operations. The two control systems communicate together through the switch bus  24  to perform the data packet re-synchronization.  
         [0025]    As it will be further detailed, after a switch card replacement, the operator enters a command through the Control Point device to allow each adapter to send a specific data packet herein called ‘re-synchronisation data packet’ for each priority level.  
         [0026]    Generally, a data packet is made of a header and a payload. The header contains information such as a destination address, a priority level, and the payload contains the data. To operate the re-synchronisation method of the present invention, a specific bit called the ‘re-synch bit’ is set within the header of the re-synchronisation data packet. The re-synch bit is active only for each re-synchronisation data packet while is inactive for the normal flow of data packets.  
         [0027]    Referring now to FIG. 3, the system of the invention is illustrated as part of one switch card. For the ease of description, the transmission of data packets is exemplified for data packets issued from adapter card  16 _ 1  on data bus-in  13 _ 1 , switched through active switch  14 - 1  and send to adapter card  16 _ 2  on data bus-out  15 _ 2 .  
         [0028]    It is to be easily understood that adapter cards  16 _ 1  and  16 _ 2  along with the number of priorities (up to four levels in this description) are only taken as example. In the preferred embodiment, each switch card is mainly composed of:  
         [0029]    a Shared Memory  250 ;  
         [0030]    a Header Detection and Packet Validation block  100 _ 1 ;  
         [0031]    a Memory Write entity made of:  
         [0032]    an En-queue Register block  380 _ 1 ,  
         [0033]    a Lease Address Selector block  350 ,  
         [0034]    a Memory Write Controller block  150 ;  
         [0035]    a Memory Read entity made of:  
         [0036]    four De-queue Priority FIFO&#39;s blocks  512 _ 1 ,  512 _ 2 ,  512 _ 3  and  512 _ 4 ,  
         [0037]    a Release Address Selector block  300 ,  
         [0038]    a Memory Read Controller block  200 ,  
         [0039]    a Destination Output Buffer block  280 _ 2 ;  
         [0040]    a Free Buffer Queue block  400 ; and  
         [0041]    a Remote Switch Logic block  450 .  
         [0042]    The structure and operating of the different blocks are now described.  
         [0043]    Shared Memory ( 250 ):  
         [0044]    The Shared Memory receives data packets from adapter card  16 _ 1  on data bus-in  13 _ 1  and transmits them to adapter card  16 _ 2  on data bus-out  15 _ 2  through the Destination Output Buffer block  280 _ 2 . Write and Read operations within the Shared Memory are respectively controlled by bus  160  and by bus  210 .  
         [0045]    Header Detection and Packet Validation ( 100 _ 1 ):  
         [0046]    The Header Detection and Packet Validation block  100 _ 1  receives data packets from adapter card  16 _ 1  through data bus-in  13 _ 1 . When a valid data packet is detected, the destination address, the priority level and the re-synch bit are extracted and generated on bus  140 _ 1 . Therefore this bus is made of the destination address bus, four priority level signals and one re-synch signal. Simultaneously, a write enable signal  130 _ 1  is activated.  
         [0047]    Memory Write Entity:  
         [0048]    The Memory Write Entity is made of the En-queue Register block  380 _ 1 , the Lease Address Selector block  350  and the Memory Write Controller block  150 .  
         [0049]    To detail each task:  
         [0050]    a. The En-queue Priority Register block  380 _ 1  contains the memory address where to store an incoming data packet. The address comes from the Free Buffer Queue block  400  through bus  410 . The output bus  370 _ 1  is connected to the Lease Address Selector block  350 .  
         [0051]    b. The Lease Address Selector block  350  is detailed in FIG. 4. Its function is to transfer to the De-queue Priority FIFOs the memory address stored into the En-queue Register block  380 _ 1  through a Buffer block  351  along with a re-synch signal  140 _ 11  derived from bus  140 _ 1 . These two information are carried onto bus  360 . This buffer block  351  is controlled by a decode logic made of a Decoder block  353  and a Gate block  352 . The Decoder block  353  receives the destination address and the priority level of the incoming data packet on bus  140 _ 1 . In our example, for the destination address of port # 2 , only one chip select signal is activated among the four priority signals  360 _ 1 ,  360 _ 2 ,  360 _ 3 ,  360 _ 4 . These chip select signals are carried out to the Remote Switch Logic block  450  and to four De-queue Priority FIFO&#39;s of port # 2  blocks  512 _ 1 ,  512 _ 2 ,  512 _ 3  and  512 _ 4 .  
         [0052]    c. The Memory Write Controller block  150  controls the Shared Memory block  250  through bus  160 . The write address is available on bus  360  and the write command is available on signal  130 _ 1 .  
         [0053]    Memory Read Entity:  
         [0054]    The Memory Read Entity is made of the four De-queue Priority FIFO&#39;s blocks  512 _i, the Release Address Selector block  300  and the Memory Read Controller block  200 .  
         [0055]    To detail each task:  
         [0056]    a. When an incoming data packet is stored into the shared memory block  250 , the content of bus  360 _i (re-synch signal and memory address of the incoming packet) are stored into the corresponding De-queue Priority FIFO block  512 _i. The four input FIFO data busses are dotted and connected to bus  360 . Each input FIFO write signal is connected to a chip select signal  360 _i. The four output FIFO data busses  332 _i and the four input FIFO read signal  322 _i are connected to the Release Address Selector block  300 .  
         [0057]    b. The Release Address Selector block  300  for destination adapter  16 _ 2  is detailed in FIG. 5. Its function is to de-queue memory read addresses and corresponding re-synch signals. A State Machine  380  controls the de-queueing in a round-robin fashion from the highest priority level “ 1 ” to the lowest priority level “ 4 ”. The read address of incoming bus  332 _i is connected to a Buffer block  342 _i and to a Comparator block  352 _i while the re-synch signal of incoming bus  332 _i is connected to the State Machine block  380  and to the Remote Switch Logic block  450  by signal  312 _i. The output busses of the buffer blocks  342 _i are dotted and connected to the Memory Read Controller block  200  through bus  220 . The Comparator block  352 _i compares the output address to zero which is default value when there is no address stored into the FIFO. The result is received by State Machine block  380  on signal  362 _i. The State Machine  380  also generates the De-queue Priority FIFO read signals  322 _i and the buffer output enable signals  382 _i. These latter four signals provide through Gate block  390  the read signal  221  to the Memory Read Controller block  200  and to the Destination Output Buffer block  280 _ 2 . The State Machine block  380  is clocked by the outgoing data packet clock received on signal  381 .  
         [0058]    c. The Memory Read Controller block  200  controls the Shared Memory block  250  through bus  210 . The read address is available on bus  220  and the read command is available on signal  221 . The data packet is transmitted from the memory to adapter  16 _ 2  through the Destination Output Buffer block  280 _ 2  on bus  15 _ 2 .  
         [0059]    Free Buffer Oueue block ( 400 ):  
         [0060]    The Free Buffer Queue block  400  contains memory addresses ready to be used. Its output bus  410  provides addresses to the En-queue Register for memory write operations. Its input bus  220  receives addresses from the Release Address Selector block  300  when a memory read operation has been completed.  
         [0061]    Remote Switch Logic ( 450 ):  
         [0062]    The Remote Switch Logic block  450  exchanges the re-synchronization information with the backup switch card block  14 _ 2  through bus  24 . This bus connects the output signals of remote switch logic block  450  of switch card  14 _ 1  to the input signals of remote switch logic block  450  of switch card  14 _ 2  and vice-versa. Referring to FIG. 6, the Remote Switch Logic block  450  is composed of a Connector block  455  and four 2-input AND gates (one per priority level) blocks  462 _i. The connector block  455  is made of an output bus  312 _i and an input bus  472 _i. Each output Re-synch signal  312 _i is connected to one input of AND gate block  462 _i and the other input of AND gate block  462 _i is connected to the input bus  472 _i. When the backup switch card block  14 _ 2  detects its synchronization data packet, it activates its own output Re-synch signal  312 _i which then activates the input signal  472 _i of active switch card through bus  24 . The input signal  472 _i is transmitted to the Release Address Selector block  300  onto bus  452 _i through AND gate  462 _i as the Release signal.  
         [0063]    The principle of operation of the system is now described as previously explained with adapter  16 _ 1  transmitting data packets with different priority levels to adapter  16 _ 2 .  
         [0064]    Case #1:  
         [0065]    Data packets are built by adapter  16 _ 1  with the re-synch bit de-asserted which is the normal operation. The following process applies for each data packet within each switch card blocks  14 _ 1  and  14 _ 2 .  
         [0066]    Each data packet is received by the Header Detection and Packet Validation block  100 _ 1  on bus  13 _ 1  which performs the following tasks:  
         [0067]    extracting the destination address, the priority level and the re-synch bit to create bus  140 _ 1  made of the destination address bus, four priority level signals and one re-synch signal;  
         [0068]    sending these information to the Lease Address Selector block  350  through bus  140 _ 1 ;  
         [0069]    informing the Write Memory Controller block  150  through signal  130 _ 1  to perform a write operation.  
         [0070]    Next the Lease Address Selector block  350  performs the following tasks:  
         [0071]    decoding the destination address and the priority level to activate one chip select among the four priority signals  360 _i which enables Buffer block  351  through gate block  352 ;  
         [0072]    transmitting the address stored into the En-queue Register block  380 _ 1  to the Write Memory Controller block  150 . This address was previously taken from the Free Buffer Queue block  400 ;  
         [0073]    storing this address along with the re-synch bit into the corresponding De-queue Priority FIFO block  310 _i.  
         [0074]    Finally the Write Memory Controller block  150  allows to store the data packet into the Shared Memory block  250 . At this stage the addresses stored into each De-queue Priority FIFO are waiting for a transmission to port # 2  as illustrated in FIG. 7. Both switches are synchronised and have exactly the same queues.  
         [0075]    The de-queue of each FIFO is a background task performed by the Release Address Selector block  300  and more precisely by State Machine block  380 . As illustrated in FIG. 8 a , the state machine operates per priority from the highest priority FIFO (block  802 ) to the lowest priority FIFO (block  808 ). The objective is to have a higher priority FIFO emptied before processing a next one. As shown on FIG. 8 a , the higher priority FIFO is first checked on step  802 . If it is empty, then the next priority level FIFO is checked on step  804 , otherwise the FIFO is emptied through a de-queueing process on step  803 . When the FIFO is empty the next priority level FIFO is checked on step  804 . These checking and de-queueing operations are run for all FIFOs.  
         [0076]    The de-queue process is illustrated on FIG. 8 b  for first FIFO, and is made of the following operations:  
         [0077]    in step  8002 : checking if the re-synch variable is active. For the normal flow of data packets the re-synchronization bit is not set (i.e. the re-synch variable is not active) and the state machine goes to step  8004  through branch No, otherwise the process goes to step  8014  (branch Yes);  
         [0078]    in step  8004 : the FIFO is read and the data contained into the De-queue Destination FIFO block  512 _ 1  is pushed out onto bus  332 _ 1  by activating signal  322 _ 1 ;  
         [0079]    in next step  8006 : the address bus of bus  332 _ 1  is compared by comparator block  352 _ 1  to zero which is the default value when the FIFO is empty:  
         [0080]    if the control signal  362 _ 1  is not activated (branch No), an address is available and the state machine goes to step  8008 ; otherwise  
         [0081]    if the control signal  362 _ 1  is activated (branch Yes), the FIFO is empty and the state machine exits the de-queue process for this priority and next FIFO is checked on step  804 .  
         [0082]    in step  8008 : checking if the re-synch signal of bus  332 _ 1  is active. In normal operation this signal is not set and the state machine goes to step  8010  (branch No) to complete the data packet transfer. The state machine then activates signal  382 _ 1  to perform the following tasks:  
         [0083]    1/enabling buffer block  342 _ 1  which outputs the address to Memory Controller block  200  through bus  221 ;  
         [0084]    2/activating the read signal  221  through gate  390 ;  
         [0085]    3/releasing the address into the Free Buffer Queue block  400  for further use;  
         [0086]    4/the data packet is read from the shared memory block  250  but only the active switch card enables the Destination Output Buffer block  280 _ 2  to transfer the data packet to adapter  16 _ 2  onto output bus  15 _ 2 ;  
         [0087]    5/at the end of the transfer the state machine goes back to step  8002 .  
         [0088]    otherwise, if the re-synch signal is active on step  8008 , the state machine goes to step  8012  (branch Yes) to perform a re-synchronization operation as described hereafter with case #2.  
         [0089]    Case #2:  
         [0090]    Let&#39;s assume that the backup switch card block  14 _ 2  has been replaced by the operator. As illustrated in FIG. 9, the queues of the backup switch card block  14 _ 2  are empty while the queues of the active switch card block  14 _ 1  are transmitting the normal data traffic.  
         [0091]    Then the operator initialises the backup switch card block  14 - 2  and the data packets are then received by both switch cards, stored into the shared memory of each card and de-queued as previously described.  
         [0092]    Next, the operator enters the appropriate commands to allow each adapter to send a re-synchronization data packet for each priority level. The re-synchronization data packet is illustrated on FIG. 10 and following FIGS.  11  to  13 as a checkerboard rectangle stored in each FIFO. To recall, the re-synchronization data packet does not contain any valid data payload but has a re-synch bit activated in its header.  
         [0093]    As illustrated in FIG. 11 when the re-synchronization data packet has reached the bottom of a FIFO by the backup switch card block  14 _ 2 , the following operations illustrated on FIG. 8 b  are performed by its State Machine block  380 :  
         [0094]    in step  8002 : checking if the re-synch variable ‘i’ is active. The previous received packets being data packets the re-synch variable ‘i’ is not active and the state machine goes to step  8004  through branch No;  
         [0095]    in step  8004 : the re-synchronization data packet contained into the De-queue Destination FIFO block  512 _ 1  is pushed out onto bus  332 _ 1  by activating signal  322 _ 1 . The activated re-synch signal  312 _ 1  enables the AND gate block  462 _ 1  and is transmitted to the active switch card block  14 _ 1  through cable  24 ;  
         [0096]    in step  8006 : the control signal  362 _ 1  is not activated, the address of the re-synchronization data packet is available and the state machine goes to step  8008  through branch No;  
         [0097]    in step  8008 : the re-synch signal being active, the state machine goes to step  8012  through branch Yes;  
         [0098]    in step  8012 : setting a re-synch variable ‘i’. This variable is set to skip the reading of the De-queue Destination FIFO of the backup switch card until the re-synchronization data packet is detected by the active switch card;  
         [0099]    in step  8014 : checking the status of the Release signal coming from the active switch card block  14 _ 1 :  
         [0100]    until the Release signal  452 _ 1  is activated the state machine exits the de-queue process from branch No. At a next re-entry of the de-queue process, the state machine  380  of the backup switch card block  14 _ 2  performs step  8002  where the re-synch variable ‘i’ is checked active, the process goes to step  8014  where the release signal is not active and thus exits the de-queue process from branch No. The backup switch card block  14 _ 2  does not empty its De-queue Destination FIFO until the active switch card block  14 _ 1  detects its re-synchronisation data packet;  
         [0101]    as illustrated in FIG. 12, finally the re-synchronization data packet is detected by the active switch card block  14 _ 1  which activates its re-synch signal  312 _ 1 . This signal is transmitted to the backup switch card through cable  24  to the other input of AND gate block  462 _ 1 . Its output activates the Release signal  452 _ 1 . This mechanism occurs simultaneously on both switch cards. At their next re-entry both state machines are now able to jump from step  8014  to step  8016  through branch Yes. The re-synch variable is reset and the state machine exits the de-queue process for this priority. FIG. 13 illustrates the status of each FIFO at this stage. It should be noted that the re-synchronization data packet is not transmitted to the adapter. Both FIFOs for priority #1 are now synchronized. This mechanism repeats for each priority.