Abstract:
An equalizer circuit includes: a plurality of amplifiers that convert a voltage signal into a current; a plurality of capacitive loads that are charged and discharged in accordance with respective outputs of the plurality of amplifiers; a charge discharge circuit provided for each of the plurality of capacitive loads to charge or discharge one of the plurality of capacitive loads; and a reset circuit provided for each of the capacitive loads to initialize the charge stored in the one of the plurality of capacitive loads, wherein a current according to the voltage signal is integrated in different periods for each of the plurality of capacitive loads and the capacitive load is discharged through the current in a first period and the capacitive load is charged through the current in a second period following the first period.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of priority from Japanese Patent Application No. 2009-217409 filed on Sep. 18, 2009, the entire contents of which are incorporated herein by reference. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    The embodiments discussed herein relate to an equalizer circuit and a reception apparatus having the equalizer circuit. 
         [0004]    2. Description of Related Art 
         [0005]    An equalizer circuit that compensates for the frequency characteristics of channels may be used in signal transmission at data rates from several Gbps to several tens of Gbps. For example, a transmission path (channel) may have the characteristics of a low-pass filter, and therefore a signal at a high frequency may be attenuated by the transmission path. 
         [0006]    A related art is disclosed, for example, in Willy M. C. Sansen, “Analog Design Essentials”, Springer. 
       SUMMARY 
       [0007]    According to one aspect of the embodiments, an equalizer circuit is provided which includes a plurality of amplifiers that convert a voltage signal into a current; a plurality of capacitive loads that are charged and discharged in accordance with respective outputs of the plurality of amplifiers; a charge and discharge circuit provided for each of the plurality of capacitive loads to charge and discharge one of the plurality of capacitive loads; and a reset circuit provided for each of the capacitive loads to initialize the charge stored in the one of the plurality of capacitive loads, wherein a current according to the voltage signal is integrated in different periods for each of the plurality of capacitive loads and the capacitive load is discharged through the current in a first period and the capacitive load is charged through the current in a second period following the first period. 
         [0008]    Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning by practice of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  illustrates an exemplary analog high-pass filter; 
           [0010]      FIG. 2  illustrates an exemplary equalizer circuit; 
           [0011]      FIG. 3  illustrates an exemplary operation of an equalizer circuit; 
           [0012]      FIG. 4  illustrates an exemplary operation of an equalizer circuit; 
           [0013]      FIG. 5A  illustrates an exemplary multi-phase timing signal generation circuit; 
           [0014]      FIG. 5B  illustrates an exemplary output of a voltage control oscillator (VCO); 
           [0015]      FIG. 5C  illustrates an exemplary output of logical product computation circuits; 
           [0016]      FIG. 6  illustrates an exemplary equalizer circuit; 
           [0017]      FIGS. 7A and 7B  illustrate an exemplary equalizer circuit; 
           [0018]      FIG. 8  illustrates an exemplary equalizer circuit; 
           [0019]      FIG. 9  illustrates an exemplary equalizer circuit; 
           [0020]      FIGS. 10A and 10B  illustrate an exemplary equalizer circuit; 
           [0021]      FIG. 11  illustrates an exemplary equalizer circuit; and 
           [0022]      FIG. 12  illustrates an exemplary receiver. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0023]      FIG. 1  illustrates an exemplary analog high-pass filter. The high-pass filter receives differential input signals in and inx, and outputs differential output signals out and outx. In an N-channel MOS (metal oxide semiconductor) transistor TR 121 , the gate receives the input signal in, the source is coupled to a current source  121 , and the drain is coupled to a power source voltage via a resistance R 121 . In an N-channel MOS transistor TR 122 , the gate receives the input signal inx, the source is coupled to a current source  122 , and the drain is coupled to a power source voltage via a resistance R 122 . The respective sources of the N-channel MOS transistors TR 121  and TR 122  are coupled to a capacitance C 121 . The output signal out is output from a connection point between the drain of the N-channel MOS transistor TR 121  and the resistance R 121  to a output signal line. The output signal outx is output from a connection point between the drain of the N-channel MOS transistor TR 122  and the resistance R 122 . 
         [0024]      FIG. 2  illustrates an exemplary equalizer circuit. Reference numerals  11  and  12  each denote a transconductor (amplifier) that converts a voltage signal into a current. Cj denotes a capacitive load that is charged and discharged in accordance with respective outputs of the transconductors  11  and  12 . SWAj, SWBj, and SWCj each denote a switch. The letter “j” is a suffix, and the value of “j” may be any of 0, 1, 2, and 3, for example. 
         [0025]    The transconductors  11  and  12  receive a voltage signal via an input terminal Vi, and outputs a current according to the voltage signal. The transconductance Gm 1  of the transconductor  11  may be negative. The transconductance Gm 2  of the transconductor  12  may be positive. When a signal input from the input terminal Vi has a voltage V, the transconductor  11  outputs a current that flows in the direction of the illustrated arrow (Gm 1 ×V), and the transconductor  12  outputs a current that flows in the direction of the illustrated arrow (Gm 2 ×V). 
         [0026]    One end of the capacitive load C 0  is coupled to the transconductor  11  via the switch SWA 0 , to the transconductor  12  via the switch SWB 0 , and to a reference potential, for example a ground, via the switch SWC 0 . The other end of the capacitive load C 0  is coupled to the reference potential. The one end of the capacitive load C 0  is coupled to an output terminal Vo 0 . 
         [0027]    One end of the capacitive load C 1  is coupled to the transconductor  11  via the switch SWA 1 , to the transconductor  12  via the switch SWB 1 , and to the reference potential via the switch SWC 1 . The other end of the capacitive load C 1  is coupled to the reference potential. The one end of the capacitive load C 1  is coupled to an output terminal Vo 1 . 
         [0028]    One end of the capacitive load C 2  is coupled to the transconductor  11  via the switch SWA 2 , to the transconductor  12  via the switch SWB 2 , and to the reference potential via the switch SWC 2 . The other end of the capacitive load C 2  is coupled to the reference potential. The one end of the capacitive load C 2  is coupled to an output terminal Vo 2 . 
         [0029]    One end of the capacitive load C 3  is coupled to the transconductor  11  via the switch SWA 3 , to the transconductor  12  via the switch SWB 3 , and to the reference potential via the switch SWC 3 . The other end of the capacitive load C 3  is coupled to the reference potential. The one end of the capacitive load C 3  is coupled to an output terminal Vo 3 . 
         [0030]    The output terminals Vo 0 , Vo 1 , Vo 2 , and Vo 3  may be electrically coupled to respective input terminals of a plurality of A/D converters (not illustrated) that operate in a time-interleaving manner. 
         [0031]    The equalizer circuit illustrated in  FIG. 2  includes a unit circuit, for example an integrate-and-dump sampler, that includes the transconductors  11  and  12  and the capacitive load Cj and the switches SWAj, SWBj, and SWCj with the suffix j having the same value. The switches SWAj, SWBj, and SWCj are controlled such that a current according to the voltage signal input from the input terminal Vi is integrated in different periods for each unit circuit. The equalizer circuit performs a high-pass filtering process. 
         [0032]      FIG. 3  illustrates an exemplary operation of the equalizer circuit. The switch SWA 0  is controlled by a control signal SC 0 . The switch SWB 0  is controlled by a control signal SC 1 . The switch SWC 0  is controlled by a control signal SC 3 . Each of the switches SWA 0 , SWB 0 , and SWC 0  is turned on, for example become a conductive state, when the control signal is at a high level, and is turned off, for example become a non-conductive state, when the control signal is at a low level.  FIG. 3  illustrates exemplary control signals SC 0 , SC 1 , SC 2 , and SC 3  and a voltage of the capacitive load C 0 . 
         [0033]    When the control signal SC 0  is at a high level, the switch SWA 0  is turned on to couple the transconductor  11  and the capacitive load C 0 . Therefore, the capacitive load C 0  is discharged through a current (charge) according to the voltage signal input from the input terminal Vi. When the control signal SC 1  is at a high level, the switch SWB 0  is turned on to couple the transconductor  12  and the capacitive load C 0 . Therefore, the capacitive load C 0  is charged based on a current (charge) according to the voltage signal input from the input terminal Vi. When the control signal SC 2  is at a high level, all of the switches SWA 0 , SWB 0 , and SWC 0  are turned off. Thus, the charge stored in the capacitive load C 0  is held. When the control signal SC 3  is at a high level, the switch SWC 0  is turned on to couple the ends of the capacitive load C 0  to the reference potential. Therefore, the charge stored in the capacitive load C 0  is discharged to be reset, for example initialized. 
         [0034]    In time periods from t 1  to t 2  and from t 5  to t 6  when the control signal SC 0  is at a high level, the capacitive load C 0  is discharged through a current (charge) according to the input signal. In time periods from t 2  to t 3  and from t 6  to t 7  when the control signal SC 1  is at a high level, the capacitive load C 0  is charged through a current (charge) according to the input signal. In time periods from t 3  to t 4  and from t 7  to t 8  when the control signal SC 2  is at a high level, the current (charge) stored in the capacitive load C 0  is held. In time periods from t 4  to t 5  and from t 8  to t 9  when the control signal SC 3  is at a high level, the load stored in the capacitive load C 0  is reset. 
         [0035]    Each unit circuit of the equalizer circuit repeatedly discharges the capacitive load Cj through a current (charge) according to the input signal or charges the capacitive load Cj through a current (charge) according to the input signal into the capacitive load Cj, holds the charge stored in the capacitive load Cj, and resets the capacitive load Cj. Discharging the capacitive load Cj through a current (charge) according to the input signal in a certain period, for example a sampling period, and charging the capacitive load Cj through a current (charge) according to the input signal in the next sampling period may correspond to an operation of a digital high-pass filter. In a period in which the stored charge is held during the operation corresponding to the high-pass filter, the voltage of the capacitive load Cj is supplied to the A/D converter via the output terminal Voj. When a high-pass filtering process is performed digitally, the intensity of high-frequency components of the signal is recovered, and the gain is supplied. The equalizer circuit generates an equalized signal subjected to an equalization process by compensating for high-frequency components attenuated through signal transmission without being affected by variations in element characteristics. 
         [0036]      FIG. 4  illustrates an exemplary operation of an equalizer circuit. In  FIG. 4 , the switches SWA 0 , SWC 1 , and SWB 3  are controlled by the control signal SC 0 . The switches SWB 0 , SWA 1 , and SWC 2  are controlled by the control signal SC 1 . The switches SWB 1 , SWA 2 , and SWC 3  are controlled by the control signal SC 2 . The switches SWC 0 , SWB 2 , and SWA 3  are controlled by the control signal SC 3 . Each of the switches SWAj, SWBj, and SWCj is turned on, for example become a conductive state, when the control signal is at a high level, and is turned off, for example become a non-conductive state, when the control signal is at a low level. 
         [0037]    Each of the switches SWAj, SWBj, and SWCj is controlled by the control signal SC 0 , SC 1 , SC 2 , or SC 3 . Therefore, in the capacitive load Cj in each unit circuit, the capacitive load Cj is discharged through a current (charge) according to the input signal, the capacitive load Cj is charged through a current (charge) according to the input signal, the stored charge is held, and the stored charge is reset repeatedly. A current (charge) according to the input signal is released, a current (charge) according to the input signal is injected, the stored charge is held, and the stored charge is reset in periods shifted for each unit circuit. By integrating a current according to the input signal from the input terminal Vi in different periods for each unit circuit, the equalizer circuit performs a digital high-pass filtering process. 
         [0038]      FIG. 5A  illustrates an exemplary multi-phase timing signal generation circuit. The multi-phase timing signal generation circuit generates the control signals SC 0 , SC 1 , SC 2 , and SC 3 . Reference numeral  41  denotes a voltage control oscillator (VCO) that outputs 4-phase clock signals (oscillation signals) ST 0 , ST 1 , ST 2 , and ST 3 .  FIG. 5B  illustrates an exemplary output of a voltage control oscillator (VCO). The voltage control oscillator (VCO)  41  illustrated in  FIG. 5A  outputs the 4-phase clock signals ST 0 , ST 1 , ST 2 , and ST 3 , the respective phases of which are shifted by 90 degrees, for example 0°, 90°, 180°, and 270°. 
         [0039]    Reference numeral  42  denotes a signal generation circuit that generates the control signals SC 0 , SC 1 , SC 2 , and SC 3  based on the 4-phase clock signals ST 0 , ST 1 , ST 2 , and ST 3 . The signal generation circuit  42  includes logical product computation circuits (AND circuits)  43 ,  44 ,  45 , and  46 . The AND circuit  43  receives the clock signal (0°) ST 0  as an input and the clock signal (90°) ST 1  as an inverted input, and outputs the computation results as the control signal SC 0 . The AND circuit  44  receives the clock signal (90°) ST 1  as an input and the clock signal (180°) ST 2  as an inverted input, and outputs the computation results as the control signal SC 1 . The AND circuit  45  receives the clock signal (180°) ST 2  as an input and the clock signal (270°) ST 3  as an inverted input, and outputs the computation results as the control signal SC 2 . The AND circuit  46  receives the clock signal (270°) ST 3  as an input and the clock signal (0°) ST 0  as an inverted input, and outputs the computation results as the control signal SC 3 . 
         [0040]      FIG. 5C  illustrates an exemplary output of a logical product computation circuits. The generated control signals SC 0 , SC 1 , SC 2 , and SC 3  may be activated in periods different from each other. The generated control signals may be activated exclusively. When the clock signal ST 0  is at a high level and the clock signal ST 1  is at a low level, the high-level control signal SC 0  is output. In the other periods, the low-level control signal SC 0  is output. When the clock signal ST 1  is at a high level and the clock signal ST 2  is at a low level, the high-level control signal SC 1  is output. In the other periods, the low-level control signal SC 1  is output. When the clock signal ST 2  is at a high level and the clock signal ST 3  is at a low level, the high-level control signal SC 2  is output. In the other periods, the low-level control signal SC 2  is output. When the clock signal ST 3  is at a high level and the clock signal ST 0  is at a low level, the high-level control signal SC 3  is output. In the other periods, the low-level control signal SC 3  is output. 
         [0041]    An N-channel MOS transistor may be referred to as an “NMOS transistor”. A P-channel MOS transistor may be referred to as a “PMOS transistor”. The control signals SC 0 , SC 1 , SC 2 , and SC 3  may correspond to the signals illustrated in  FIG. 5C . 
         [0042]      FIG. 6  illustrates an exemplary equalizer circuit. The equalizer circuit illustrated in  FIG. 6  may correspond to a unit circuit. 
         [0043]    Reference numeral  51  denotes a first circuit (PAC) that releases a current (charge) according to an input voltage signal. Reference numeral  52  denotes a second circuit (PBC) that injects a current (charge) according to an input voltage signal. Reference numeral  53  denotes a reset circuit (NRC) that resets a capacitive load. 
         [0044]    The first circuit (PAC)  51  includes PMOS transistors PT 51 , PT 52 , PT 53 , and PT 54 . The gate of the PMOS transistor PT 51  is coupled to an input terminal CTLA. The source of the PMOS transistor PT 51  is coupled to a current source  54 . The drain of the PMOS transistor PT 51  is coupled to the source of the PMOS transistor PT 52 . The gate of the PMOS transistor PT 52  is coupled to an input terminal Vi. The drain of the PMOS transistor PT 52  is coupled to a node ND 51 . The gate of the PMOS transistor PT 53  is coupled to the input terminal CTLA. The source of the PMOS transistor PT 53  is coupled to a current source  55 . The drain of the PMOS transistor PT 53  is coupled to the source of the PMOS transistor PT 54 . The gate of the PMOS transistor PT 54  is coupled to an input terminal Vix. The drain of the PMOS transistor PT 54  is coupled to a node ND 52 . A resistance R 51  is coupled between the respective sources of the PMOS transistors PT 51  and PT 53 . 
         [0045]    The second circuit (PBC)  52  includes PMOS transistors PT 55 , PT 56 , PT 57 , and PT 58 . The gate of the PMOS transistor PT 55  is coupled to an input terminal CTLB. The source of the PMOS transistor PT 55  is coupled to a current source  56 . The drain of the PMOS transistor PT 55  is coupled to the source of the PMOS transistor PT 56 . The gate of the PMOS transistor PT 56  is coupled to an input terminal Vix. The drain of the PMOS transistor PT 56  is coupled to the node ND 51 . The gate of the PMOS transistor PT 57  is coupled to the input terminal CTLB. The source of the PMOS transistor PT 57  is coupled to a current source  57 . The drain of the PMOS transistor PT 57  is coupled to the source of the PMOS transistor PT 58 . The gate of the PMOS transistor PT 58  is coupled to an input terminal Vi. The drain of the PMOS transistor PT 58  is coupled to the node ND 52 . A resistance R 52  is coupled between the respective sources of the PMOS transistors PT 55  and PT 57 . 
         [0046]    The reset circuit (NRC)  53  includes capacitive loads C 51  and C 52  and NMOS transistors NT 51 , NT 52 , and NT 53 . One end of the capacitive load C 51  is coupled to the node ND 51 . The other end of the capacitive load C 51  is coupled to a reference potential, for example a ground. One end of the capacitive load C 52  is coupled to the node ND 52 . The other end of the capacitive load C 52  is coupled to the reference potential. The gate of the NMOS transistor NT 51  is coupled to an input terminal CTLC. The source of the NMOS transistor NT 51  is coupled to the reference potential. The drain of the NMOS transistor NT 51  is coupled to the one end of the capacitive load C 51 . The gate of the NMOS transistor NT 52  is coupled to the input terminal CTLC. The source of the NMOS transistor NT 52  is coupled to the reference potential. The drain of the NMOS transistor NT 52  is coupled to the one end of the capacitive load C 52 . The gate of the NMOS transistor NT 53  is coupled to the input terminal CTLC. The source of the NMOS transistor NT 53  is coupled to the one end of the capacitive load C 51 . The drain of the NMOS transistor NT 53  is coupled to the one end of the capacitive load C 52 . 
         [0047]    An output terminal Vo is coupled to the node ND 52 . An output terminal Vox is coupled to the node ND 51 . 
         [0048]    Any of the control signals SC 0 , SC 1 , SC 2 , and SC 3  is input to the input terminal CTLA of the first circuit (PAC), the input terminal CTLB of the second circuit (PBC), and the input terminal CTLC of the reset circuit (NRC). The control signals input to the input terminals CTLA, CTLB, and CTLC may be different from each other. For example, when the control signal SC 0  is input to the input terminal CTLA, the control signal SC 1  may be input to the input terminal CTLB, and the control signal SC 3  may be input to the input terminal CTLC. A differential input signal input to the equalizer circuit, for example an in-phase signal Vi, may be input to the input terminal Vi of the first circuit (PAC) and the input terminal Vi of the second circuit (PBC). A differential input signal input to the equalizer circuit, for example an opposite-phase signal Vix, may be input to the input terminal Vix of the first circuit (PAC) and the input terminal Vix of the second circuit (PBC). 
         [0049]    A circuit including the PMOS transistors PT 52  and PT 54 , the current sources  54  and  55 , and the resistance R 51  may correspond to the transconductor  11  illustrated in  FIG. 2 . A circuit including the PMOS transistors PT 51  and PT 53  may correspond to the switch SWAj illustrated in  FIG. 2 . A circuit including the PMOS transistors PT 56  and PT 58 , the current sources  56  and  57 , and the resistance R 52  may correspond to the transconductor  12  illustrated in  FIG. 2 . A circuit including the PMOS transistors PT 55  and PT 57  may correspond to the switch SWBj illustrated in  FIG. 2 . A circuit including the NMOS transistors NT 51 , NT 52 , and NT 53  may correspond to the switch SWCj illustrated in  FIG. 2 . The capacitive loads C 51  and C 52  may correspond to the capacitive load Cj illustrated in  FIG. 2 . The first circuit (PAC)  51  charges the capacitive loads C 51  and C 52  through a current (charge) according to input signals Vix and Vi, which are in opposite phase to input signals Vi and Vix which the second circuit (OBC)  52  uses for charging loads C 51  and C 52 . Since the capacitive loads C 51  and C 52  is charged through a current (charge) according to the input signals Vix and Vi in the opposite phase, the first circuit (PAC)  51  discharges the capacitive loads C 51  and C 52  through a current (charge) according to the input signals Vix and Vi from the capacitive loads C 51  and C 52 . 
         [0050]      FIGS. 7A and 7B  illustrate an exemplary equalizer circuit. Reference numerals  61 - 0 ,  61 - 1 ,  61 - 2 , and  61 - 3  each denote a first circuit (PAC) that discharges a capacitive load through a current (charge) according to an input signal. The first circuits (PAC) illustrated in  FIGS. 7A and 7B  may be substantially the same as or similar to the first circuit (PAC)  51  illustrated in  FIG. 6 . Reference numerals  62 - 0 ,  62 - 1 ,  62 - 2 , and  62 - 3  each denote a second circuit (PBC) that charges a capacitive load through a current (charge) according to an input signal. The second circuits (PBC) illustrated in  FIGS. 7A and 7B  may be substantially the same as or similar to the second circuit (PBC)  52  illustrated in  FIG. 6 . Reference numerals  63 - 0 ,  63 - 1 ,  63 - 2 , and  63 - 3  each denote a reset circuit (NRC) that resets a charge in a capacitive load. The reset circuits (NRC) illustrated in  FIGS. 7A and 7B  may be substantially the same as or similar to the reset circuit (NRC)  53  illustrated in  FIG. 6 . 
         [0051]    The differential input signal Vi input to the equalizer circuit is input to the input terminal Vi of each of the first circuits (PAC)  61 - 0 ,  61 - 1 ,  61 - 2 , and  61 - 3  and the second circuits (PBC)  62 - 0 ,  62 - 1 ,  62 - 2 , and  62 - 3 . The differential input signal Vix input to the equalizer circuit is input to the input terminal Vix of each of the first circuits (PAC)  61 - 0 ,  61 - 1 ,  61 - 2 , and  61 - 3  and the second circuits (PBC)  62 - 0 ,  62 - 1 ,  62 - 2 , and  62 - 3 . 
         [0052]    A unit circuit includes the first circuit (PAC)  61 - 0 , the second circuit (PBC)  62 - 0 , the reset circuit (NRC)  63 - 0 , current sources  64 ,  65 ,  66 , and  67 , and resistances R 61  and R 62 , and outputs output signals Vo 0  and Vox 0 . The control signal SC 0  is input to the input terminal CTLA of the first circuit (PAC)  61 - 0 . The control signal SC 1  is input to the input terminal CTLB of the second circuit (PBC)  62 - 0 . The control signal SC 3  is input to the input terminal CTLC of the reset circuit (NRC)  63 - 0 . 
         [0053]    A unit circuit includes the first circuit (PAC)  61 - 1 , the second circuit (PBC)  62 - 1 , the reset circuit (NRC)  63 - 1 , the current sources  64 ,  65 ,  66 , and  67 , and the resistances R 61  and R 62 , and outputs output signals Vo 1  and Vox 1 . The control signal SC 1  is input to the input terminal CTLA of the first circuit (PAC)  61 - 1 . The control signal SC 2  is input to the input terminal CTLB of the second circuit (PBC)  62 - 1 . The control signal SC 0  is input to the input terminal CTLC of the reset circuit (NRC)  63 - 1 . 
         [0054]    A unit circuit includes the first circuit (PAC)  61 - 2 , the second circuit (PBC)  62 - 2 , the reset circuit (NRC)  63 - 2 , the current sources  64 ,  65 ,  66 , and  67 , and the resistances R 61  and R 62 , and outputs output signals Vo 2  and Vox 2 . The control signal SC 2  is input to the input terminal CTLA of the first circuit (PAC)  61 - 2 . The control signal SC 3  is input to the input terminal CTLB of the second circuit (PBC)  62 - 2 . The control signal SC 1  is input to the input terminal CTLC of the reset circuit (NRC)  63 - 2 . 
         [0055]    A unit circuit includes the first circuit (PAC)  61 - 3 , the second circuit (PBC)  62 - 3 , the reset circuit (NRC)  63 - 3 , the current sources  64 ,  65 ,  66 , and  67 , and the resistances R 61  and R 62 , and outputs output signals Vo 3  and Vox 3 . The control signal SC 3  is input to the input terminal CTLA of the first circuit (PAC)  61 - 3 . The control signal SC 0  is input to the input terminal CTLB of the second circuit (PBC)  62 - 3 . The control signal SC 2  is input to the input terminal CTLC of the reset circuit (NRC)  63 - 3 . 
         [0056]    The equalizer circuit performs an equalization operation illustrated for example in  FIG. 4  based on the control signals SC 0 , SC 1 , SC 2 , and SC 3  generated by a multi-phase timing signal generation circuit. 
         [0057]      FIG. 8  illustrates an exemplary equalizer circuit. In  FIG. 8 , a circuit that discharges a capacitive load through a current (charge) according to an input voltage signal from a capacitive load. 
         [0058]    Reference numerals  71 - 0 ,  71 - 1 ,  71 - 2 , and  71 - 3  each denote a reset circuit (NRC) that resets a charge in a capacitive load, which may be substantially the same as or similar to the reset circuit (NRC)  53  illustrated in  FIG. 6 . The control signal SC 3  is input to the input terminal CTLC of the reset circuit (NRC)  71 - 0 . The control signal SC 0  is input to the input terminal CTLC of the reset circuit (NRC)  71 - 1 . The control signal SC 1  is input to the input terminal CTLC of the reset circuit (NRC)  71 - 2 . The control signal SC 2  is input to the input terminal CTLC of the reset circuit (NRC)  71 - 3 . 
         [0059]    The differential input signal Vix is input to the gate of the PMOS transistor PT 71 . The source of the PMOS transistor PT 71  is coupled to a current source  72 . The differential input signal Vi is input to the gate of the PMOS transistor PT 72 . The source of the PMOS transistor PT 72  is coupled to a current source  73 . A resistance R 71  is coupled between the respective sources of the PMOS transistors PT 71  and PT 72 . 
         [0060]    The control signal SC 1  is input to the gate of the PMOS transistor PT 73 - 0 . The source of the PMOS transistor PT 73 - 0  is coupled to the drain of the PMOS transistor PT 71 . The drain of the PMOS transistor PT 73 - 0  is coupled to a signal line for the output signal Vox 0 . The control signal SC 1  is input to the gate of the PMOS transistor PT 74 - 0 . The source of the PMOS transistor PT 74 - 0  is coupled to the drain of the PMOS transistor PT 72 . The drain of the PMOS transistor PT 74 - 0  is coupled to a signal line for the output signal Vo 0 . 
         [0061]    The control signal SC 2  is input to the gate of the PMOS transistor PT 73 - 1  (PT 74 - 4 ). The source of the PMOS transistor PT 73 - 1  (PT 74 - 1 ) is coupled to the drain of the PMOS transistor PT 71  (PT 72 ). The drain of the PMOS transistor PT 73 - 1  (PT 74 - 1 ) is coupled to a signal line for the output signal Vox 1  (Vo 1 ). The control signal SC 3  is input to the gate of the PMOS transistor PT 73 - 2  (PT 74 - 2 ). The source of the PMOS transistor PT 73 - 2  (PT 74 - 2 ) is coupled to the drain of the PMOS transistor PT 71  (PT 72 ). The drain of the PMOS transistor PT 73 - 2  (PT 74 - 2 ) is coupled to a signal line for the output signal Vox 2  (Vo 2 ). The control signal SC 0  is input to the gate of the PMOS transistor PT 73 - 3  (PT 74 - 3 ). The source of the PMOS transistor PT 73 - 3  ( 9 T 74 - 3 ) is coupled to the drain of the PMOS transistor PT 71  (PT 72 ). The drain of the PMOS transistor PT 73 - 3  (PT 74 - 3 ) is coupled to a signal line for the output signal Vox 3  (Vo 3 ). 
         [0062]    An input transistor to which the input signals Vi and Vix are input is commonly used by a plurality of unit circuits, thereby reducing the circuit size and the drive load. 
         [0063]      FIG. 9  illustrates an exemplary equalizer circuit.  FIG. 9  may illustrate a part equivalent to a unit circuit. 
         [0064]    Reference numeral  81  denotes a first circuit (NAC) that discharges a capacitive load through a current (charge) according to an input voltage signal. Reference numeral  82  denotes a second circuit (NBC) that charges a capacitive load through a current (charge) according to an input voltage signal. Reference numeral  83  denotes a reset circuit (PRC) that resets a capacitive load. 
         [0065]    The first circuit (NAC)  81  includes NMOS transistors NT 81 , NT 82 , NT 83 , and NT 84 . The gate of the NMOS transistor NT 81  is coupled to an input terminal CTLA. The source of the NMOS transistor NT 81  is coupled to a current source  84 . The drain of the NMOS transistor NT 81  is coupled to the source of the NMOS transistor NT 82 . The gate of the NMOS transistor NT 82  is coupled to an input terminal Vi. The drain of the NMOS transistor NT 82  is coupled to a node ND 81 . The gate of the NMOS transistor NT 83  is coupled to the input terminal CTLA. The source of the NMOS transistor NT 83  is coupled to a current source  85 . The drain of the NMOS transistor NT 83  is coupled to the source of the NMOS transistor NT 84 . The gate of the NMOS transistor NT 84  is coupled to an input terminal Vix. The drain of the NMOS transistor NT 84  is coupled to a node ND 82 . A resistance R 81  is coupled between the respective sources of the NMOS transistors NT 81  and NT 83 . 
         [0066]    The second circuit (NBC)  82  includes NMOS transistors NT 85 , NT 86 , NT 87 , and NT 88 . The gate of the NMOS transistor NT 85  is coupled to an input terminal CTLB. The source of the NMOS transistor NT 85  is coupled to a current source  86 . The drain of the NMOS transistor NT 85  is coupled to the source of the NMOS transistor NT 86 . The gate of the NMOS transistor NT 86  is coupled to an input terminal Vix. The drain of the NMOS transistor NT 86  is coupled to the node ND 81 . The gate of the NMOS transistor NT 87  is coupled to the input terminal CTLB. The source of the NMOS transistor NT 87  is coupled to a current source  87 . The drain of the NMOS transistor NT 87  is coupled to the source of the NMOS transistor NT 88 . The gate of the NMOS transistor NT 88  is coupled to an input terminal Vi. The drain of the NMOS transistor NT 88  is coupled to the node ND 82 . A resistance R 82  is coupled between the source of the NMOS transistor NT 85  and the source of the NMOS transistor NT 87 . 
         [0067]    The reset circuit (PRO)  83  includes capacitive loads C 81  and C 82  and PMOS transistors PT 81 , PT 82 , and PT 83 . One end of the capacitive load C 81  is coupled to the node ND 81 . The other end of the capacitive load C 81  is coupled to a power source potential. One end of the capacitive load C 82  is coupled to the node ND 82 . The other end of the capacitive load C 82  is coupled to the power source potential. The gate of the PMOS transistor PT 81  is coupled to an input terminal CTLC. The source of the PMOS transistor PT 81  is coupled to the power source potential. The drain of the PMOS transistor PT 81  is coupled to the one end of the capacitive load C 81 . The gate of the PMOS transistor PT 82  is coupled to the input terminal CTLC. The source of the PMOS transistor PT 82  is coupled to the power source potential. The drain of the PMOS transistor PT 82  is coupled to the one end of the capacitive load C 82 . The gate of the PMOS transistor PT 83  is coupled to the input terminal CTLC. The source of the PMOS transistor PT 83  is coupled to the one end of the capacitive load C 81 . The drain of the PMOS transistor PT 83  is coupled to the one end of the capacitive load C 82 . 
         [0068]    An output terminal Vo is coupled to the node ND 82 . An output terminal Vox is coupled to the node ND 81 . 
         [0069]    One of the control signals SC 0 , SC 1 , SC 2 , and SC 3  is input to the input terminal CTLA of the first circuit (NAC), the input terminal CTLB of the second circuit (NBC), and the input terminal CTLC of the reset circuit (PRC). The control signals input to the input terminals CTLA, CTLB, and CTLC may be different from each other. For example, when the control signal SC 0  is input to the input terminal CTLA, the control signal SC 1  may be input to the input terminal CTLB, and the control signal SC 3  may be input to the input terminal CTLC. A differential input signal input to the equalizer circuit, for example an in-phase signal Vi, is input to the input terminal Vi of the first circuit (NAC) and the input terminal Vi of the second circuit (NBC). A differential input signal input to the equalizer circuit, for example an opposite-phase signal Vix, is input to the input terminal Vix of the first circuit (NAC) and the input terminal Vix of the second circuit (NBC). 
         [0070]    A circuit including the NMOS transistors NT 82  and NT 84 , the current sources  84  and  85 , and the resistance R 81  may correspond to the transconductor  11  illustrated in  FIG. 2 . A circuit including the NMOS transistors NT 81  and NT 83  may correspond to the switch SWAj illustrated in  FIG. 2 . A circuit including the NMOS transistors NT 86  and NT 88 , the current sources  86  and  87 , and the resistance R 82  may correspond to the transconductor  12  illustrated in  FIG. 2 . A circuit including the NMOS transistors NT 85  and NT 87  may correspond to the switch SWBj illustrated in  FIG. 2 . A circuit including the PMOS transistors PT 81 , PT 82 , and PT 83  may correspond to the switch SWCj illustrated in  FIG. 2 . The capacitive loads C 81  and C 82  may correspond to the capacitive load Cj illustrated in  FIG. 2 . The first circuit (NAC)  81  charges the capacitive loads C 81  and C 82  a current (charge) according to input signals Vix and Vi, which are in opposite phase to input signals Vi and Vix which the second circuit (NBC)  82  uses for charging the capacitive loads C 81  and C 82 . Since the capacitive loads C 81  and C 82  are charged based on a current (charge) according to the input signals Vix and Vi in the opposite phase, the first circuit (NAC)  81  discharges the capacitive loads C 81  and C 82  through a current (charge) according to the input signals Vix and Vi from the capacitive loads C 81  and C 82 . 
         [0071]      FIGS. 10A and 10B  illustrate an exemplary equalizer circuit. Reference numerals  91 - 0 ,  91 - 1 ,  91 - 2 , and  91 - 3  each denote a first circuit (NAC) that discharges a capacitive load through a current (charge) according to an input signal from a capacitive load, which may be substantially the same as or similar to the first circuit (NAC)  81  illustrated in  FIG. 9 . Reference numerals  92 - 0 ,  92 - 1 ,  92 - 2 , and  92 - 3  each denote a second circuit (NBC) that charges a capacitive load based on a current (charge) according to an input signal, which may be substantially the same as or similar to the second circuit (NBC)  82  illustrated in  FIG. 9 . Reference numerals  93 - 0 ,  93 - 1 ,  93 - 2 , and  93 - 3  each denote a reset circuit (PRC) that resets a charge in a capacitive load, which may be substantially the same as or similar to the reset circuit (PRC)  83  illustrated in  FIG. 9 . 
         [0072]    The differential input signal Vi input to the equalizer circuit is input to the respective input terminals Vi of the first circuits (NAC)  91 - 0 ,  91 - 1 ,  91 - 2 , and  91 - 3  and the second circuits (NBC)  92 - 0 ,  92 - 1 ,  92 - 2 , and  92 - 3 . The differential input signal Vix input to the equalizer circuit is input to the respective input terminals Vix of the first circuits (NAC)  91 - 0 ,  91 - 1 ,  91 - 2 , and  91 - 3  and the second circuits (NBC)  92 - 0 ,  92 - 1 ,  92 - 2 , and  92 - 3 . 
         [0073]    A unit circuit includes the first circuit (NAC)  91 - 0 , the second circuit (NBC)  92 - 0 , the reset circuit (PRC)  93 - 0 , current sources  94 ,  95 ,  96 , and  97 , and resistances R 91  and R 92 , and outputs output signals Vo 0  and Vox 0 . The control signal SC 0  is input to the input terminal CTLA of the first circuit (NAC)  91 - 0 . The control signal SC 1  is input to the input terminal CTLB of the second circuit (NBC)  92 - 0 . The control signal SC 3  is input to the input terminal CTLC of the reset circuit (PRC)  93 - 0 . 
         [0074]    A unit circuit includes the first circuit (NAC)  91 - 1 , the second circuit (NBC)  92 - 1 , the reset circuit (PRC)  93 - 1 , the current sources  94 ,  95 ,  96 , and  97 , and the resistances R 91  and R 92 , and outputs output signals Vo 1  and Vox 1 . The control signal SC 1  is input to the input terminal CTLA of the first circuit (NAC)  91 - 1 . The control signal SC 2  is input to the input terminal CTLB of the second circuit (NBC)  92 - 1 . The control signal SC 0  is input to the input terminal CTLC of the reset circuit (PRC)  93 - 1 . 
         [0075]    A unit circuit includes the first circuit (NAC)  91 - 2 , the second circuit (NBC)  92 - 2 , the reset circuit (PRC)  93 - 2 , the current sources  94 ,  95 ,  96 , and  97 , and the resistances R 91  and R 92 , and outputs output signals Vo 2  and Vox 2 . The control signal SC 2  is input to the input terminal CTLA of the first circuit (NAC)  91 - 2 . The control signal SC 3  is input to the input terminal CTLB of the second circuit (NBC)  92 - 2 . The control signal SC 1  is input to the input terminal CTLC of the reset circuit (PRC)  93 - 2 . 
         [0076]    A unit circuit includes the first circuit (NAC)  91 - 3 , the second circuit (NBC)  92 - 3 , the reset circuit (PRC)  93 - 3 , the current sources  94 ,  95 ,  96 , and  97 , and the resistances R 91  and R 92 , and outputs output signals Vo 3  and Vox 3 . The control signal SC 3  is input to the input terminal CTLA of the first circuit (NAC)  91 - 3 . The control signal SC 0  is input to the input terminal CTLB of the second circuit (NBC)  92 - 3 . The control signal SC 2  is input to the input terminal CTLC of the reset circuit (PRC)  93 - 3 . 
         [0077]    The equalizer circuit illustrated in  FIGS. 10A and 10B  performs an equalization operation illustrated for example in  FIG. 4  based on the control signals SC 0 , SC 1 , SC 2 , and SC 3  from a multi-phase timing signal generation circuit. 
         [0078]      FIG. 11  illustrates an exemplary equalizer circuit. In  FIG. 11 , a circuit that discharges a capacitive load through a current (charge) according to an input voltage signal from a capacitive load is not illustrated. 
         [0079]    Reference numerals  101 - 0 ,  101 - 1 ,  101 - 2 , and  101 - 3  each denote a reset circuit (PRC) that resets a charge in a capacitive load. The reset circuits (PRC) illustrated in  FIG. 11  may each be substantially the same as or similar to the reset circuit (PRC)  83  illustrated in  FIG. 9 . The control signal SC 3  is input to the input terminal CTLC of the reset circuit (PRC)  101 - 0 . The control signal SC 0  is input to the input terminal CTLC of the reset circuit (PRC)  101 - 1 . The control signal SC 1  is input to the input terminal CTLC of the reset circuit (PRC)  101 - 2 . The control signal SC 2  is input to the input terminal CTLC of the reset circuit (PRC)  101 - 3 . 
         [0080]    The signal Vix, of the differential input signals Vi and Vix, is input to the gate of an NMOS transistor NT 101 . The source of the NMOS transistor NT 101  is coupled to a current source  102 . The signal Vi, of the differential input signals Vi and Vix, is input to the gate of an NMOS transistor NT 102 . The source of the NMOS transistor NT 102  is coupled to a current source  103 . A resistance R 101  is coupled between the respective sources of the NMOS transistors NT 101  and NT 102 . 
         [0081]    The control signal SC 1  is input to the gate of an NMOS transistor NT 103 - 0 . The source of the NMOS transistor NT 103 - 0  is coupled to the drain of the NMOS transistor NT 101 . The drain of the NMOS transistor NT 103 - 0  is coupled to a signal line for the output signal Vox 0 . The control signal SC 1  is input to the gate of an NMOS transistor NT 104 - 0 . The source of the NMOS transistor NT 104 - 0  is coupled to the drain of the NMOS transistor NT 102 . The drain of the NMOS transistor NT 104 - 0  is coupled to a signal line for the output signal Vo 0 . 
         [0082]    The control signal SC 2  is input to the gate of an NMOS transistor NT 103 - 1  (NT 104 - 1 ). The source of the NMOS transistor NT 103 - 1  (NT 104 - 1 ) is coupled to the drain of the NMOS transistor NT 101  (NT 102 ). The drain of the NMOS transistor NT 103 - 1  (NT 104 - 1 ) is coupled to a signal line for the output signal Vox 1  (Vo 1 ). The control signal SC 3  is input to the gate of an NMOS transistor NT 103 - 2  (NT 104 - 2 ). The source of the NMOS transistor NT 103 - 2  (NT 104 - 2 ) is coupled to the drain of the NMOS transistor NT 101  (NT 102 ). The drain of the NMOS transistor NT 103 - 2  (NT 104 - 2 ) is coupled to a signal line for the output signal Vox 2  (Vo 2 ). The control signal SC 0  is input to the gate of an NMOS transistor NT 103 - 3  (NT 104 - 3 ). The source of the NMOS transistor NT 103 - 3  (NT 104 - 3 ) is coupled to the drain of the NMOS transistor NT 101  (NT 102 ). The drain of the NMOS transistor NT 103 - 3  (NT 104 - 3 ) is coupled to a signal line for the output signal Vox 3  (Vo 3 ). 
         [0083]    As illustrated in  FIG. 11 , an input transistor for the input signals Vi and Vix are commonly used by a plurality of unit circuits, thereby reducing the circuit size and the drive load. 
         [0084]    The equalizer circuit integrates a current according to the input voltage signal in different periods for each unit circuit to operate as a digital high-pass filter. The equalizer circuit generates an equalized signal subjected to an equalization process by compensating for high-frequency components attenuated through signal transmission without being affected by variations in element characteristics. The mounting area may be reduced. 
         [0085]      FIG. 12  illustrates an exemplary receiver. A receiver  1103  may include the equalizer circuit discussed above. Reference numeral  1101  denotes a transmitter. Reference numeral  1102  denotes a transmission line. 
         [0086]    The receiver  1103  includes a control circuit  1104 , a reception circuit  1105 , a clock data reproduction processing circuit  1106 , and an equalization processing circuit  1107 . The control circuit  1104  controls the reception circuit  1105 , the clock data reproduction processing circuit  1106 , the equalization processing circuit  1107 , and so forth. The reception circuit  1105  receives a signal transmitted by the transmitter  1101  via the transmission line  1102 . The clock data reproduction processing circuit  1106  reproduces clock data based on the signal received by the reception circuit  1105 . The equalization processing circuit  1107  includes the equalizer circuit, and compensates for attenuated high-frequency components in the received signal using a high-pass filter that provides characteristics opposite to the characteristics of the transmission line  1102 . 
         [0087]    For example, operations of discharge, charge, discharge, charge hold, and charge reset for a capacitive load may be repeated. For example, operations of discharge, charge, discharge, charge, charge hold, and charge reset for a capacitive load may be repeated. Complicated filter characteristics may be achieved by increasing the number of discharges and charges performed in accordance with a control signal for one of N phases. 
         [0088]    Example embodiments of the present invention have now been described in accordance with the above advantages. It will be appreciated that these examples are merely illustrative of the invention. Many variations and modifications will be apparent to those skilled in the art.