Abstract:
A spatial and complementary polarity device redundancy-based analog circuit architecture mitigates against single event transients. At least one and preferably multiple redundant spatially separate copies of the complementary device-configured analog circuit (such as a voltage reference or an operational amplifier) are coupled in parallel to the circuit&#39;s output node, via a complementary polarity device path. The parallel inputs to the multiple spaced apart devices make the likelihood of a single particle passing through multiple circuits at the same time extremely remote, so that the intended value of the electrical parameter will be sustained by either the given circuit itself or any circuit copy at which the upset event does not occur.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims the benefit of co-pending U.S. Provisional Patent Application, Ser. No. 60/265,706 filed Feb. 1, 2001, by James Swonger, entitled: “Analog Error Suppression Method,” assigned to the assignee of the present application and the disclosure of which is incorporated herein. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates in general to electronic circuits, and is particularly directed to a spatial and complementary semiconductor device-containing, redundancy-based circuit architecture, that is configured to prevent one or more upset events, such as those produced by the incidence of cosmic rays and the like, present in airborne and spaceborne environments, from perturbing or modifying the intended value of an electrical parameter at an output port of the circuit. To provide resistance to such upset events, the present invention couples multiple copies of a complementary semiconductor device based circuit between input ports and the output port, such that the intended value of the electrical parameter will be sustained by one of the multiple copies of the multiple copies at which the upset event does not occur. 
     BACKGROUND OF THE INVENTION 
     Semiconductor circuits employed in environments prone to incidence of cosmic rays or high energy particles can be disturbed or interrupted by charge deposit anomalies associated with such incidence, resulting in what are commonly termed single event effects (SEEs), including single event upsets (SEUs) for digital circuits, and single event transients (SETS) for analog circuits. Typical, but non-limiting examples of applications that are subject to such events or upsets include spaceborne systems, as well as airborne and terrestrial systems that operate in the vicinity of the earth&#39;s magnetic poles. Moreover, as improvements in semiconductor manufacturing techniques continue to reduce feature size (and thus increase integration density), there is an escalating probability of single event effects in such systems. 
     Up to the present, the major industry focus has been upon the digital arena, particularly on digital signal processing applications, where a single bit error caused by an SEU may cause substantial corruption of the operation of an entire digital system. Efforts to combat the SEU problem in digital applications have included installation of redundant or parallel systems (including separately clocked or sampling schemes), coupled with majority voting techniques to ‘mask’ out effects of such event upsets. 
     In contrast, industry efforts to address the potential impact of SEEs on the operation of analog systems have not produced an effective and reliable working solution. However, as increasing numbers of electronic systems, such as high data rate communication systems, are implemented as an integration of high density analog and digital components in a common support and signal feed and distribution architecture, SEE anomalies in analog components may propagate and thereby corrupt downstream digital components, especially in spaceborne and airborne systems. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, this SEE problem in analog circuits is effectively obviated by means of a new and improved spatial and complementary semiconductor device, redundancy-based analog circuit architecture, that is configured to prevent one or more single event effects (single event transients) from modifying the intended value of an electrical parameter at an output port of an analog circuit. 
     For this purpose, the invention couples at least one and preferably multiple redundant spatially separate copies of the analog circuit (such as a voltage reference or an operational amplifier) between input ports and the circuit&#39;s output port, via a complementary semiconductor device-encountering path. The architecture is configured such that the likelihood of a single particle passing through multiple circuits at the same time is rendered extremely remote, and such that the intended value of the electrical parameter will be sustained at the output port by either the given circuit itself or any of the redundant copies of the circuit at which the SEE does not occur. 
     A non-limiting example of such an analog circuit is a buffer (operational) amplifier configuration preferably configured as a triple amplifier scheme, having a pair of parallel-coupled complementary semiconductor circuits, and providing immunity against the unlikely occurrence of two simultaneous SEEs, without excessively increasing circuit occupancy of available chip real estate. A respective amplifier of a triple amplifier set has two inputs coupled to a different pair of three input lines, each of which is associated with a desired input, but may be perturbed by an SEE. 
     As will be described, the invention employs complementary semiconductor polarity input and output devices (e.g., NPN and PNP bipolar transistors) for each amplifier set, as well as complementary semiconductor device-based architectures of each pair of amplifier triplets. These circuits are connected in parallel to realize immunity against either a high-to-low or a low-to-high perturbation on any two of the three input lines. The architecture is such that one of a three amplifier set to which an unperturbed (e.g., by an SEE) voltage is applied will also effectively decouple the output node from an SEE-based perturbation (voltage spike) applied to that amplifier set, whereas the unperturbed voltage itself will be properly coupled to the output node, thereby ensuring SEE-immunity. 
     In a further embodiment of the invention, three input lines of the triple amplifier architecture are coupled to outputs of three respective differential amplifiers of a front end differential amplifier block. These front end differential amplifiers have their respective differential inputs coupled in parallel to differential polarity input nodes. The multiple redundancy provided by the front end differential amplifiers coupled with that of a cascaded triple amplifier scheme described above allows for the simultaneous occurrence of a single event transient (e.g. pulse/spike) of either polarity for any two of the front end differential amplifiers, without changing the intended state of the output node from that provided by the unperturbed amplifier within the cascaded triplet. This provides a very robust immunity to events that are capable of producing transients of either polarity. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a reduced complexity circuit diagram illustrating the principles of the spatial redundancy-based architecture of the invention as applied to an analog voltage reference circuit; 
     FIG. 2 shows an example of a reduced complexity redundant output buffer circuit coupled to the output node of the voltage reference circuit of FIG. 1; 
     FIG. 3 shows a practical implementation of a triple amplifier scheme, that prevents two simultaneous single event transients from causing a modification of the output node voltage level; 
     FIG. 4 illustrates an example of an NPN bipolar circuit implementation of the triple amplifier embodiment of FIG. 3 referenced to a ‘low’ side supply rail; 
     FIG. 5 is a block representation of the circuit of FIG. 4; 
     FIG. 6 illustrates an example of a PNP bipolar circuit implementation of the triple amplifier embodiment of FIG. 3 referenced to a ‘high’ side supply rail; 
     FIG. 7 is a block representation of the circuit of FIG. 6; 
     FIG. 8 shows a composite (dual polarity) amplifier block diagram, in which the respective complementary semiconductor device-based amplifier circuits of FIGS. 5 and 7 have been combined; and 
     FIG. 9 shows a further embodiment of the invention, in which the input lines of the amplifier architecture of the embodiments of FIGS. 4-8 are coupled to outputs of three respective differential amplifiers of a front end differential amplifier block. 
    
    
     DETAILED DESCRIPTION 
     A reduced complexity circuit diagram illustrating the principles of the spatial and complementary device redundancy-based architecture of the invention as applied to an analog voltage reference circuit is diagrammatically illustrated in FIG. 1 as comprising a pair of substantially identically configured voltage reference circuits  10  and  20  whose topographies in a given circuit die are laid out to be adjacent to one another (as diagrammatically shown in broken lines), and which are arranged to be coupled in circuit with an output (voltage reference) node  30 . In the illustrated example, each voltage reference circuit is configured as an NPN bipolar transistor-based implementation. It is to be understood, however, that the semiconductor device polarity of the present example (NPN transistor) is not limited to that shown, nor are the active elements constrained to bipolar devices; other equivalent components, such as, but not limited to, PNP transistors, (MOS)FET devices and the like may alternatively be employed. 
     Voltage reference circuit  10  contains an NPN transistor  11  having its collector  11 C coupled to a supply voltage rail  12  and its emitter  11 E coupled to output node  30 , from which a voltage reference output V REF  is derived. Output node  30  is coupled via an adjustable resistor  31  to a voltage reference (e.g., ground (GND)) terminal  32 . The base  11 B of transistor  11  is coupled to a current source  13 , sourced to the supply voltage rail  12 , and to the anode of a diode  14 , the cathode of which is coupled to a Zener diode  15  referenced to voltage terminal  32 . Similarly, the voltage reference circuit  20  contains an NPN transistor  21  having its collector  21 C coupled to the supply voltage rail  12  and its emitter  21 E coupled to output node  30 . Transistor  21  has its base  21 B coupled to a current source  23 , that is sourced to the supply voltage rail  12 , and to the anode of a diode  24 , the cathode of which is coupled to a Zener diode  25  referenced to the voltage reference terminal  32 . 
     As can be seen from the circuit architecture of FIG. 1, should one of the two voltage reference circuit suffer a single event transient (SET), the fact that voltage reference circuit contains multiple redundant copies (two— 10  and  20 , in the illustrated example) coupled to the output node  30  means that the other copy (or additional copies) of the reference circuit will prevent the value of the voltage at the output terminal  30  from departing from its intended value V REF . 
     For drive regulation, the redundant reference voltage circuit requires that the output node  30  be buffered through output amplifier circuitry. FIG. 2 shows an example of a reduced complexity redundant output buffer circuit coupled to the output node  30  of the voltage reference circuit of FIG.  1 . In the output buffer circuit of FIG. 2, a pair of output (buffer) operational amplifiers  40  and  50  are coupled between the voltage reference output node  30  and a load-driving node  60 . Output amplifier  40  has a first (e.g., inverting (−)) input  41  coupled to node  30  and a second (e.g., non-inverting (+)) input  42  coupled to node  60 . To provide isolation between its output  43  and that of amplifier  50 , the amplifier&#39;s output  43  is coupled to node  60  via a reverse voltage blocking diode  44 . 
     Similarly, the other (redundant) output amplifier  50  has a first (e.g., inverting (−)) input  51  coupled to node  30  and a second (e.g., non-inverting (+)) input  52  coupled to the output node  60 . Amplifier  53  has its output  53  coupled to node  60  though a reverse blocking diode  54 , to provide isolation between its output  53  and that of amplifier  40 . As in the redundancy of the circuit architecture of FIG. 1, should either of the two output amplifiers  40  and  50  suffer a single event transient, the other output amplifier will still maintain the output node  60  at its driven level, as established by the voltage V REF  a the voltage reference node  30 . 
     Now, although a single redundancy voltage reference architecture provides a measure of SET protection, enhanced protection may be afforded by augmenting the voltage reference redundancy architecture of FIG. 2 with one or more additional output buffer amplifiers coupled in parallel between the voltage reference node  30  and output node  60 . A practical implementation shown in FIG. 3 is that of a triple amplifier scheme, that is configured to prevent the unlikely occurrence of two simultaneous SETs from causing a modification of the output node voltage level, without creating an excessive increase in occupancy of available chip real estate. 
     In the triple amplifier architecture of FIG. 3, the output buffer amplifiers  40  and  50  are augmented by an additional output buffer amplifier  70  coupled in circuit between voltage reference node  30  and the output node  60 . The output buffer amplifier  70  has a first (e.g., inverting (−)) input  71  coupled to node  30  and a second (e.g., non-inverting (+)) input  72  coupled to node  60 . To provide reverse voltage isolation between its output  73  and output node  60 , the amplifier&#39;s output  73  is coupled to node  60  through via a reverse blocking diode  74 . To provide mutual reverse voltage isolation for each amplifier with respect to the remaining two amplifiers of the triplicate set, additional diodes  45 ,  55  and  75  are provided. Diode  45  has its cathode connected to the output  43  of amplifier  40  and its anode connected to the output  53  of amplifier  50 ; diode  55  has its cathode connected to output  53  of amplifier  50  and its anode connected to the output  73  of amplifier  70 ; and diode  75  has its cathode connected to output  73  of amplifier  70  and its anode connected to output  43  of amplifier  40 . 
     FIG. 4 illustrates an example of a practical complementary semiconductor device-based, bipolar circuit implementation of the triple amplifier embodiment of FIG. 3, referenced to a ‘low’ side supply rail, and a block representation of which is shown in FIG. 5. A first complementary bipolar transistor-based amplifier circuit  100  (of a triplicate set  100 ,  200  and  300 ) has a first input NPN transistor  110  with its collector  110 C coupled to a ‘high’ side voltage (Vcc) rail  107 , its emitter  110 E coupled to the base  130 B of a PNP output transistor  130 , and its base  110 B coupled to a first input line  101 . A second input NPN transistor  120  has its collector  120 C coupled to the Vcc voltage rail, its emitter  120 E coupled to the base  130 B of the PNP output transistor  130 , and its base  120 B coupled to a second input line  102 . The output PNP transistor  130  has its base  130 B coupled to a relatively ‘low’ side voltage reference rail (e.g., Vee or GND)  104  through a resistor  105  or a current source  106 . The collector  130 C of output transistor  130  is coupled to low side rail  104 , while its emitter  130 E is coupled to output node  60 . 
     Similarly, the second amplifier circuit  200  has a first input NPN transistor  210 , the collector  210 C of which is coupled to the Vcc voltage rail, its emitter  210 E coupled to the base  230 B of a PNP output transistor  230 , and its base  210 B coupled to the second input line  102 . A second input NPN transistor  220  has its collector  220 C coupled to the Vcc voltage rail, its emitter  220 E coupled to the base  230 B of the PNP output transistor  230 , and its base  220 B coupled to a third input line  103 . The output PNP transistor  230  has its base  230 B coupled to the voltage reference rail  104  through a resistor  205  or a current source  206 . The collector  230 C of output transistor  230  is coupled to the voltage reference rail  104 , while its emitter  230 E is coupled to the output node  60 . 
     In the third amplifier circuit  300 , a first input NPN transistor  310  has its collector  310 C coupled to the Vcc voltage rail, its emitter  310 E coupled to the base  330 B of a PNP output transistor  330 , and its base  310 B coupled to the third input line  103 . A second input NPN transistor  320  has its collector  320 C coupled to the Vcc voltage rail, its emitter  320 E coupled to the base  330 B of the PNP output transistor  330 , and its base  320 B coupled to the first input line  101 . The output transistor  330  has its base  330 B coupled to the voltage reference rail  104  through a resistor  305  or a current source  306 . The collector  330 C of output transistor  330  is coupled to the voltage reference rail  104 , while its emitter  330 E is coupled to the output node  60 . 
     To illustrate the operation of the circuit architecture of FIGS. 4 and 5 in the presence of either a positive-going or negative-going single event transient, a first, positive-going (low-high) voltage spike or pulse A is shown as being applied to the first input line  101 , a second, negative-going (high-low) voltage spike/pulse B is shown as being applied to the second input line  102 , while an intended voltage level C is shown as being applied to the third input line  103 . 
     Since an NPN transistor will inherently pass a low-high spike (A), but will “hold up” a high-low spike (B), the low-high spike A applied to the base  110 B of the NPN transistor  110  in the first amplifier circuit  100  will be coupled via its emitter path to the base  130 B of the output PNP transistor  130 ; however, the high-low spike B coupled to the base  120 B of NPN transistor  120  will be decoupled from its emitter  120 E. 
     When a low-high pulse propagates to the base  130 B of PNP transistor  130 , it reduces the PNP base current; hence, the emitter current of transistor  130  decreases, and the output voltage of the first amplifier circuit  100  drops. However, the second amplifier circuit  200  does not pass the single event transient, and its output ‘holds up’ the output node  60 . 
     In the second amplifier circuit  200 , the high-low spike B applied to the base  210 B of NPN transistor  210  will be decoupled from its emitter and therefore not applied to the base  230 B of output PNP transistor  230 . However, the unperturbed voltage level C applied to the base  220 B of NPN transistor will be coupled via its emitter  220 E as the desired drive voltage to the base  230 B of output PNP transistor  230  for application via its emitter  230 E to the output node  60 , as intended. Thus, high-low spike B applied to amplifier  200  will not change the state of the output node  60  from its intended voltage level based upon drive voltage C. 
     In the third amplifier circuit  300 , the unperturbed voltage C applied to the base  310 B of NPN transistor  310  will be coupled via its emitter path to drive the base  330 B of output PNP transistor  330 ; superimposed on this voltage is the low-high spike A coupled to the base  320 B of NPN transistor  320 , which is coupled from its emitter  320 E to the base  330 B of the PNP output transistor  330 . However, since the PNP output transistor  330  will inherently “hold up” a low-high spike (A), as described above, the low-high spike A coupled through transistor  320  to the base  330 B of PNP output transistor  330  will be decoupled from the output PNP transistor&#39;s emitter  330 E (node  60 ), so that the positive-going spike A applied to the third amplifier  300  will not change the state of the output node  60 . 
     FIG. 6 illustrates an example of a practical PNP-input, NPN-output bipolar circuit implementation of the triple amplifier embodiment of FIG. 3, referenced to a ‘high’ side supply rail, and having a semiconductor device configuration complementary with respect to that shown in FIG. 4. A block representation of FIG. 6 is shown in FIG.  7 . 
     In the ‘high’ supply-referenced circuit diagram of FIG. 6, a first amplifier circuit  400  (of a triplicate amplifier set  400 ,  500  and  600 ) has a first input PNP transistor  410 , whose collector  410 C is coupled to the Vcc voltage rail, its emitter  410 E coupled to the base  430 B of an NPN output transistor  430 , and its base  410 B coupled to the first input line  101 . A second input PNP transistor  420  has its collector  420 C coupled to the Vcc voltage rail, its emitter  420 E coupled to the base  430 B of the NPN output transistor  430 , and its base  420 B coupled to the second input line  102 . The NPN output transistor  430  has its base  430 B coupled to the voltage reference rail  104  through a resistor  405  or a current source  406 . The collector  430 C of the NPN output transistor  430  is coupled to the rail  104 , while its emitter  430 E is coupled to the output node  60 . 
     The second amplifier circuit  500  has a first input PNP transistor  510 , the collector  510 C of which is coupled to the Vcc voltage rail, its emitter  510 E coupled to the base  530 B of an NPN output transistor  530 , and its base  510 B coupled to the second input line  102 . A second input PNP transistor  520  has its collector  520 C coupled to the Vcc voltage rail, its emitter  520 E coupled to the base  530 B of the NPN output transistor  530 , and its base  520 B coupled to the third input line  103 . The NPN output transistor  530  has its base  530 B coupled to the voltage reference rail  104  through a resistor  505  or a current source  506 . The collector  530 C of the NPN output transistor  530  is coupled to the voltage reference rail  104 , while its emitter  530 E is coupled to the output node  60 . 
     In the third amplifier circuit  600 , a first input PNP transistor  610  has its collector  610 C coupled to the Vcc voltage rail, its emitter  610 E coupled to the base  630 B of an NPN output transistor  630 , and its base  610 B coupled to the third input line  103 . A second input PNP transistor  620  has its collector  620 C coupled to the Vcc voltage rail, its emitter  620 E coupled to the base  630 B of the NPN output transistor  630 , and its base  620 B coupled to the first input line  101 . The NPN output transistor  630  has its base  630 B coupled to the voltage reference rail  104  through a resistor  605  or a current source  606 . The collector  630 C of the NPN output transistor  630  is coupled to the voltage reference rail  104 , while its emitter  630 E is coupled to the output node  60 . 
     In operation, a low-high spike A applied to the base  410 B of transistor  410  in the first amplifier circuit  400  will be decoupled from its emitter path and thereby not applied to the base  430 B of output NPN transistor  430 ; however, the high-low spike B coupled to the base  420 B of PNP transistor  420  will be coupled to its emitter  420 E, and thereby to base  430 B of NPN output transistor  430 . 
     When a high-low pulse propagates to the base  430 B of NPN transistor  430 , it reduces the NPN base current; hence, the emitter current of transistor  430  decreases, and the output voltage of the first amplifier circuit  400  drops. However, the second amplifier circuit  500  does not pass the single event transient, and its output ‘holds up’ the output node  60 . 
     In the second amplifier circuit  500 , the high-low spike B applied to the base  510 B of PNP transistor  510  will be coupled to its emitter and applied to the base  530 B of output NPN transistor  530 , and superimposed on the unperturbed voltage level C applied to the base  520 B of PNP transistor  520  and coupled via its emitter  520 E to the base  530 B of output NPN transistor  530 . Again, since an NPN transistor will inherently block up “a high-low spike (B), the high-low spike B coupled through PNP transistor  510  to the base  530 B of NPN output transistor  530  will be decoupled from the output NPN transistor&#39;s emitter  530 E (node  60 ), so that the negative-going spike B will not cause amplifier  500  to change the state of the output node  60 . 
     In the third amplifier circuit  600 , the unperturbed voltage C applied to the base  610 B of PNP transistor  610  will be coupled via its emitter path as a drive input to the base  630 B of output NPN transistor  630 . The low-high spike A applied to the base  620  of PNP transistor will be decoupled from its emitter  620 E and therefore not applied to the base  630 B of output NPN transistor  630 . Thus, low-high spike A applied to amplifier  600  will not change the state of the output node  60  from its intended voltage level based upon the drive voltage C. 
     FIG. 8 shows a composite (dual semiconductor device polarity) amplifier block diagram, in which the respective complementary polarity amplifier circuits of FIGS. 5 and 7 have been combined, to provide for SEE compensation for either or both of positive-going or negative-going voltage perturbations simultaneously on two out of the three amplifier buffers of the respective devices. 
     FIG. 9 shows a further embodiment of the invention, in which the three input lines  101 ,  102  and  103  of the triple amplifier architecture of the embodiments of FIGS. 4-8, as represented by an amplifier block  900 , are coupled by way of lines  901 ,  902 , and  903 , respectively, to the outputs of three respective parallel connected differential amplifiers  910 ,  920  and  930  of a front end differential amplifier unit or block  940 . The differential amplifiers  910 ,  920  and  930  have their respective differential inputs coupled in parallel to differential +/− input nodes  941  and  942  of the front end amplifier block  940 . 
     As can be seen from this triple redundant configuration, the multiple redundancy provided by the front end amplifier triplet block  940 , coupled with that of amplifier block  900  (described in detail above with reference to FIGS. 4-8) allows for the simultaneous occurrence of a single event transient of either polarity for any two of the amplifiers  910 ,  920  and  930 , without changing the intended state of the output node  60  from that provided by the unperturbed amplifier within block  940 . Thus, the amplifier architecture of FIG. 9 provides a very robust immunity to single event transients of either polarity. 
     As will be appreciated from the above description, propagation of single event transient-sourced anomalies in analog circuits is effectively obviated by the spatial and complementary semiconductor device, redundancy-based analog circuit architecture of the invention, which couples at least one and preferably multiple redundant copies of the complementary device-configured analog circuit of interest, such as a voltage reference or an operational amplifier, to the circuit&#39;s output node, in such a manner that the intended value of the electrical parameter will be sustained by either the given circuit itself or any copy of the circuit at which the upset event does not occur. 
     While I have shown and described several embodiments in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art, and I therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.