Abstract:
Provided is an ESD protection circuit for CDM capable of preventing a high current from flowing and preventing breakage when a battery is connected with reverse polarity. The ESD protection circuit employs a circuit configuration in which transistor elements are interposed in series to OFF transistors ( 11  and  13 ) included in the ESD protection circuit for CDM so that parasitic diodes of the transistor elements are connected to parasitic diodes of the OFF transistors in a reverse direction.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2011-072736 filed on Mar. 29, 2011, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an electro-static discharge (ESD) protection element for preventing a high current from flowing and preventing breakage even when a battery is connected with reverse polarity by mistake. 
         [0004]    2. Description of the Related Art 
         [0005]    As a conventional input circuit for a semiconductor integrated circuit (hereinafter, referred to as IC), a circuit as illustrated in  FIG. 4  has been known (see, for example, Japanese Patent Application Laid-open No. Hei 7-153846 (FIG. 1)). 
         [0006]    The IC includes a positive (plus) power supply terminal  121 , a negative (minus) power supply terminal  122 , and at least one input terminal  120 . The positive power supply terminal  121  is connected to a plus terminal of a battery  101  and the negative power supply terminal  122  is connected to a minus terminal of the battery  101 . Between the input terminal  120  and the negative power supply terminal  122 , a main ESD protection circuit  100  is normally disposed in the vicinity of a pad of the IC. 
         [0007]    An internal circuit (inverter)  130  that receives a signal of the input terminal  120  is provided. As charged device model (CDM) measures for protecting a gate thereof from electro-static discharge (ESD), an ESD protection circuit  110  is disposed near the internal circuit  130 . The ESD protection circuit  110  includes an N-channel transistor  11 , a P-channel transistor  13 , and a resistor  15 . Drains of the N-channel transistor  11  and the P-channel transistor  13  are connected to the gate of the internal circuit  130 . A gate, a source, and a substrate of the N-channel transistor  11  are connected to VSS. A gate, a source, and a substrate of the P-channel transistor  13  are connected to VDD. The N-channel transistor  11  and the P-channel transistor  13  are in an OFF state (high impedance state). In a normal operating state, the presence or absence of the N-channel transistor  11  and the P-channel transistor  13  does not affect the operation of the internal circuit. The resistor  15  for ESD protection may be a resistor having a given value (for example, about 1 kΩ) interposed by design, or may be a parasitic resistance of wiring of the IC. 
         [0008]    In a CDM, in the state in which the IC is charged to a high voltage, when the voltage is discharged from the input terminal  120 , electric charges of the internal circuit  130  on the substrate side are generally discharged rapidly via the substrate and the main ESD protection circuit  100 . On the other hand, electric charges of the gate of the internal circuit  130  are discharged slowly because of the resistor  15 . As a result, a high voltage is applied instantaneously between the gate and the substrate of the internal circuit  130 , and the breakage of the gate of the internal circuit may occur. In order to prevent the breakage, the OFF transistors  11  and  13  are interposed between the gate of the internal circuit and the positive power supply terminal  121  and the negative power supply terminal  122 , respectively, so that the OFF transistors  11  and  13  are broken down before a high voltage is applied between the gate of the internal circuit and the respective power supply terminals. In this way, the gate of the internal circuit can be prevented from being applied with a high voltage, and the breakage in the CDM can be prevented. 
         [0009]    Note that, reference symbols  11 D and  13 D represent parasitic diodes of the N-channel transistor  11  and the P-channel transistor  13 , respectively. 
         [0010]      FIG. 5  illustrates an example of an image diagram of IC layout. There are three pads of a VDD PAD connected to the VDD terminal, an IN PAD connected to the IN terminal, and a VSS PAD connected to the VSS terminal. In the vicinity of the IN PAD, the main ESD protection circuit  100  is laid out. The internal circuit  130  is laid out inside the IC, and, in the vicinity thereof, the ESD protection circuit  110  for CDM measures is laid out. 
         [0011]      FIG. 5  illustrates only three pads, but a normal IC includes a larger number of pads and circuits. 
         [0012]    The conventional protection circuit, however, has the following problem. When the battery is connected with reverse polarity, the parasitic diodes of the respective ESD protection elements are biased in the forward direction, and a current flows to generate heat. 
       SUMMARY OF THE INVENTION 
       [0013]    Therefore, it is an object of the present invention to solve the conventional problem and provide an ESD protection circuit capable of preventing a current from flowing and preventing breakage even when a battery is connected with reverse polarity. 
         [0014]    The present invention solves the above-mentioned problem by employing a circuit configuration in which transistor elements are interposed in series to OFF transistors included in an ESD protection circuit for CDM so that parasitic diodes of the transistor elements are connected to parasitic diodes of the OFF transistors in a reverse direction. 
         [0015]    According to the ESD protection circuit of the present invention described above, a high current can be prevented from flowing to an IC and the breakage can be prevented even when a battery is connected with reverse polarity. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    In the accompanying drawings: 
           [0017]      FIG. 1  illustrates an ESD protection circuit according to a first embodiment of the present invention; 
           [0018]      FIG. 2  is a cross-sectional diagram of the ESD protection circuit according to the first embodiment of the present invention; 
           [0019]      FIG. 3  illustrates an ESD protection circuit according to a second embodiment of the present invention; 
           [0020]      FIG. 4  illustrates a conventional ESD protection circuit; and 
           [0021]      FIG. 5  is an image diagram of IC layout. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0022]    Referring to the drawings, embodiments of the present invention are described. 
       First Embodiment 
       [0023]      FIG. 1  is a circuit diagram of an electro-static discharge (ESD) protection circuit according to a first embodiment of the present invention. An ESD protection circuit  110  according to the first embodiment of the present invention includes an N-channel transistor  11 , P-channel transistors  12 ,  13 , and  14 , and a resistor  15 . The resistor  15  is similar to the conventional one, and may be provided by design or may be a parasitic resistance of wiring. 
         [0024]    A gate, a source, and a substrate of the N-channel transistor  11  are connected to VSS, and a drain thereof is connected to a source and a substrate (well) of the P-channel transistor  12 . A gate of the P-channel transistor  12  is connected to VSS, and a drain thereof is connected to a gate of an internal circuit  130 , the resistor  15 , a drain of the P-channel transistor  13 , and a gate of the P-channel transistor  14 . A drain of the P-channel transistor  14  is connected to VDD, and a source and a substrate (well) thereof are connected to a source and a substrate (well) of the P-channel transistor  13 . A gate of the P-channel transistor  13  is connected to VDD, and a drain thereof is connected to the gate of the internal circuit  130 , the resistor  15 , the drain of the P-channel transistor  12 , and the gate of the P-channel transistor  14 . Reference symbols  11 D,  12 D,  13 D, and  14 D represent parasitic diodes of the N-channel transistor  11  and the P-channel transistors  12 ,  13 , and  14 , respectively. 
         [0025]    Comparing with the conventional ESD protection circuit of  FIG. 4 , the N-channel transistor  11  and the P-channel transistor  13  function as OFF transistors similarly to the conventional ones and the P-channel transistors  12  and  14  are added. 
         [0026]    Next, the operations performed when a battery is normally connected and when the battery is connected with reverse polarity are described.  FIG. 1  illustrates the state in which the battery is normally connected. In this state, each of the N-channel transistor  11  and the P-channel transistor  13  functions as an OFF transistor similarly to the conventional ones and the impedance thereof is high. Therefore, even if the P-channel transistors  12  and  14  are added, the operation is not affected. 
         [0027]    Next, in a CDM, in the state in which an IC is charged to a high voltage, when the voltage is discharged from the input terminal  120 , even if the gate of the internal circuit  130  tries to have a higher potential than that of the VSS terminal, the P-channel transistor  12  is turned ON so that a gate voltage of the internal circuit  130  is applied to the drain of the N-channel transistor  11 . Accordingly, the N-channel transistor  11  is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit  130  and VSS. On the other hand, even if the gate of the internal circuit  130  tries to have a lower potential than that of the VSS terminal, the parasitic diode  11 D of the N-channel transistor  11  is turned ON so that substantially the same voltage as that of the VSS terminal is applied to the source of the P-channel transistor  12 . Accordingly, the P-channel transistor  12  is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit  130  and VSS. 
         [0028]    Similarly, even if the gate potential of the internal circuit  130  tries to be higher than that of the VDD terminal, the P-channel transistor  13  is turned ON so that the voltage of the VDD terminal is applied to the source and the substrate (well) of the P-channel transistor  14 . Accordingly, the P-channel transistor  14  is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit  130  and VDD. On the other hand, even if the gate of the internal circuit  130  tries to have a lower potential than that of the VDD terminal, the P-channel transistor  14  is turned ON so that the voltage of the VDD terminal is applied to the drain of the P-channel transistor  13 . Accordingly, the P-channel transistor  13  is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit  130  and VDD. 
         [0029]    In other words, the ESD protection circuit for CDM functions similarly to the conventional one. 
         [0030]    On the other hand, when the battery is connected with reverse polarity, no path in which diodes are connected in the forward direction is formed between VDD and VSS (because diodes in the reverse direction are always connected in series), and hence no current flows as opposed to the conventional case. Further, even when the input terminal  120  is connected to VDD or VSS, no path in which diodes are connected in the forward direction is formed between the input terminal  120  and VDD or VSS (because diodes in the reverse direction are always connected in series), and hence no current flows. 
         [0031]      FIG. 2  illustrates a cross-sectional diagram of the N-channel transistor  11  and the P-channel transistors  12 ,  13 , and  14 . The transistors are connected to the input terminal  120  (IN) via the resistor  15 , but, in  FIG. 2 , the resistor  15  is omitted. On a P-substrate, a first N-well and a second N-well are provided. The P-channel transistors  13  and  14  are manufactured in the first N-well, and the P-channel transistor  12  is manufactured in the second N-well. 
         [0032]    As described above, the N-channel transistor  11  and the P-channel transistor  12  have an effect to the CDM between VSS and the gate input of the internal circuit  130 , and the P-channel transistors  13  and  14  have an effect to the CDM between VDD and the gate input of the internal circuit  130 . Therefore, it is apparent that the effect to the CDM can be obtained even only with the transistors between the internal circuit and one of VDD and VSS. 
       Second Embodiment 
       [0033]      FIG. 3  illustrates an ESD protection circuit according to a second embodiment of the present invention. The difference from  FIG. 2  resides in that the P-channel transistors  13  and  14  switch their positions between VDD and the input gate of the internal circuit. In other words, the gate, the source, and the substrate (well) of the P-channel transistor  13  are connected to VDD, and the drain thereof is connected to the drain of the P-channel transistor  14 , and the source, the substrate (well), and the gate of the P-channel transistor  14  are connected to the drain of the P-channel transistor  12 , the resistor  15 , and the gate of the internal circuit  130 . 
         [0034]    Similarly to the first embodiment, in the state in which the battery is normally connected (state of  FIG. 3 ), the transistors  13  and  14  are turned OFF (in high impedance state) and therefore do not affect the operation. 
         [0035]    Next, in a CDM, in the state in which an IC is charged to a high voltage, when the voltage is discharged from the input terminal  120 , even if the gate of the internal circuit  130  tries to have a higher potential than that of the VDD terminal, substantially the same voltage as that of the VDD terminal is applied to the drain of the P-channel transistor  14  because the parasitic diode  13 D of the P-channel transistor  13  is in the forward direction. Accordingly, the P-channel transistor  14  is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit  130  and VDD. On the other hand, even if the gate of the internal circuit  130  tries to have a lower potential than that of the VDD terminal, substantially the same voltage as that of the gate of the internal circuit  130  is applied to the drain of the P-channel transistor  13  because the parasitic diode  14 D of the P-channel transistor  14  is in the forward direction. Accordingly, the P-channel transistor  13  is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit  130  and VDD. 
         [0036]    When the battery is connected with reverse polarity, similarly to the first embodiment, no path in which diodes are connected in the forward direction is formed between VDD and VSS (because diodes in the reverse direction are always connected in series), and hence no current flows. Further, even when the input terminal  120  is connected to VDD or VSS, no path in which diodes are connected in the forward direction is formed between the input terminal  120  and VDD or VSS (because diodes in the reverse direction are always connected in series), and hence no current flows. 
         [0037]    Further, the N-channel transistor  11  and the P-channel transistors  12 ,  13 , and  14  serving as ESD protection elements for CDM have the purpose of dissipating electric charges of the gate of the internal circuit  130 , and hence, even when the W lengths (transistor widths) of the N-channel transistor  11  and the P-channel transistors  12 ,  13 , and  14  are smaller than the W length of the main ESD protection element  100 , a sufficient effect can be obtained. The W lengths may be 50 μm or less.