Abstract:
A microphone bias amplifier circuit ( 30 ) and method for biasing a microphone with an amplifier circuit. The amplifier circuit ( 30 ) has an input stage ( 34 ) coupled to an output stage ( 40 ). The output stage ( 40 ) includes a first transistor (M 1 ) coupled to a feedback loop ( 32 ) provides a variable source current ( 13 ) to the first transistor (M 1 ) and the output stage output V out . The feedback loop ( 32 ) includes an amplifier ( 36 ) coupled to the first transistor (M 1 ) and a first current source (I 2 ) conducted through a second transistor (M 2 ) and coupled to the amplifier ( 36 ). The amplifier ( 36 ) controllably drives a third transistor (M 3 ) coupled to a voltage source (AVDD) to generate the variable current source (I 2 ). The gates of the first (M 1 ) and second (M 2 ) transistors are coupled together and driven by the input stage ( 34 ). The third transistor (M 3 ) of the feedback loop ( 32 ) provides the variable source current (I 3 ) to the first transistor (M 1 ), whereby the current conducted by the first and second transistors (I 1 , I 2 ) is equal, and the remainder (I 3 -I 1 ) of the variable source current (I 3 ) is provided to the load of the output stage ( 40 ).

Description:
TECHNICAL FIELD 
     This invention relates generally to the field of electronic amplifier circuits, and more particularly to a microphone bias amplifier. 
     BACKGROUND OF THE INVENTION 
     The recent trend towards the miniaturization of electronic circuits is driven by consumer demand for smaller and light-weight electronic devices such as cellular phones and portable computers. Often, the heaviest component in an electronic device is the battery. Smaller batteries are able to provide less power. As batteries become smaller, integrated circuits (ICs) need lower working voltages and power consumption to prevent the battery from discharging too rapidly. 
     An amplifier is a linear electronic circuit that may be used to amplify an input signal and provide an output signal that is a magnified replica of the input signal. Amplifiers are used in a variety of electronic circuit design applications. As appliances and circuit designs continue to decrease in size and increase in speed, the need for low power, low noise, current efficient amplifier circuitry increases. 
     Amplifiers have various performance requirements depending on the function they are used for in a circuit. A microphone bias amplifier should have the following attributes: 1) low noise, 2) high power supply rejection ratio (PSRR); 3) low quiescent current, or rather, low overall current usage; 4) the ability to drive high current levels with an output voltage as close to the power supply rail as possible to obtain a good acoustical gain; 5) low output impedance for rejection of any coupled noise; and 6) the use of as little silicon area as possible. 
     SUMMARY OF THE INVENTION 
     The present invention achieves technical advantages as a microphone bias amplifier having low noise, high PSRR, high output current relative to the quiescent current, and high output voltage relative to the power supply rail. The output stage includes a source-follower transistor coupled to a feedback loop that keeps the source-follower transistor current constant. The action of the output stage is very linear and works well in applications having a high voltage swing, relative to the power supply. 
     In one embodiment, disclosed is an output stage for an amplifier circuit, including a first transistor coupled to a feedback loop. The feedback loop includes an amplifier coupled to the first transistor, and a current source powering a second transistor and coupled to the amplifier. The amplifier drives a third transistor powered by a voltage source. The first and second transistors are coupled together. The third transistor of the feedback loop provides the entire source current for the first transistor. 
     In another embodiment, disclosed is a microphone bias amplifier circuit, including an input stage coupled to an output stage. The output stage includes a first transistor coupled to a first feedback loop. The first feedback loop includes a first amplifier coupled to the first transistor, and a first current source powering a second transistor and coupled to the first amplifier. The first amplifier drives a third transistor powered by a voltage source. The first and second transistors are coupled together, and the third transistor provides the entire source current for the first transistor. 
     Further disclosed is a method of biasing a microphone with an amplifier circuit having an input stage coupled to an output stage. The output stage has a feedback loop coupled to a first transistor. The method includes the step of controlling the current through the first transistor with the output stage feedback loop. 
     Advantages of the present invention are an amplifier circuit having a low quiescent current or overall current usage, having the ability to drive high current levels relative to the quiescent current. The output voltage may approach, or be approximately equal to, the voltage of the power supply. The circuit has a low output impedance for rejection of coupled noise and uses very little silicon area. Furthermore, the output stage has a high transconductance compared to circuits of the prior art, so large capacitive loads may be driven at low current levels while maintaining stability. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings, which form an integral part of the specification and are to be read in conjunction therewith: 
     FIG. 1 illustrates a source-follower amplifier circuit of the prior art having an NMOS transistor at the output, where the output voltage V out  cannot reach a high voltage due to the V gs  of M 0 ; 
     FIG. 2 illustrates a source-follower bias amplifier circuit of the prior art having a PMOS transistor at the output; 
     FIG. 3 shows a schematic diagram of a bias amplifier circuit according to the present invention; and 
     FIGS. 4 and 5 illustrate models for analysis of output impedance of the amplifier circuit. 
    
    
     Like numerals and symbols are employed in different figures to designate similar components in various views unless otherwise indicated. 
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     In a microphone circuit, ideally, a microphone would be coupled directly to the power supply, so the microphone may benefit from the highest current and voltage possible. However, this is not possible because noise from the power supply would go through the microphone and create noise on the voice channel of the cellular phone or other electronic device at the output. To prevent noise from the power supply being present at the microphone and increase PSRR, a microphone bias amplifier circuit is typically used. 
     In the past, conventional amplifiers have been used for microphone bias amplifier circuits to varying degrees of success, but an efficient amplifier design specific for a microphone bias application having a high output voltage relative to the power supply rail, high output current relative to the quiescent current, and good PSRR is not available in the prior art. A typical amplifier circuit of the prior art is shown generally at  10  in FIG.  1 . An amplifier Amp 0  is coupled to and drives a transistor M 0 , where transistor M 0  is an NMOS field effect transistor (FET). The output voltage V out  of the circuit  10  is generated at the source of the transistor M 0 . The output V out  cannot reach the fall supply voltage V DD  and is limited primarily by the gate-source voltage V gs  of transistor M 0 . The approximate maximum voltage the output voltage V out  can reach is (V DD -V gs -V DS ). 
     For a microphone bias amplifier circuit, low output impedance is desired, which typically involves using a source-follower output stage, e.g. class AB amplifier, such as the circuit shown generally at  20  in FIG.  2 . Rather than using an NMOS transistor as in the circuit  10  of FIG. 1, a PMOS transistor is used for the transistor M 0  so the output voltage V out  is higher, closer to the positive voltage rail V dd . However, the efficiency of the half source-follower circuit  20  is poor because current I 1 , must be the maximum amount regardless of current draw from the load I load , which in telecom applications typically varies from zero to 1.3 mA to support up to two external electret microphones, for example. The circuit  20  requires a certain amount of current I 1  from the power supply V dd  and also requires a wide voltage range to work properly. 
     In a source-follower amplifier circuit such as the one shown in FIG. 2, the output V out  tracks the input at V in . If the input V in  goes high, the output V out  also goes high. FIG. 2 is a class A type design which requires I 1  to be set to the maximum load current I load  plus the current necessary to bias transistor M 0  correctly. Even if I load  is removed, current I 1 , is still set to its maximum level, thus using 1-2 mA of current unnecessarily. Also, when using a conventional 2-stage common-source amplifier Amp o  with a PMOS transistor M 0  as the output device to obtain high output voltage and good efficiency, this creates a relatively high output impedance and poor PSRR. A large amount of semiconductor real estate is required for the compensation capacitor (not shown) coupled to the output. Another disadvantage of the prior art circuit  20  is that the output impedance is approximately equal to the output transconductance g m  of the transistor M 0 . A higher current I 1  is needed to accommodate the higher transconductance g m . 
     What is needed in the art is a more efficient microphone bias amplifier having good PSRR, high output current relative to the quiescent current, and high output voltage relative to the power supply rail. The more current that flows through a microphone bias amplifier, the greater the sensitivity. In a telecom application such as a wireless phone, higher current results in a better acoustic to electrical gain of the voice signal. 
     A block diagram of the microphone bias amplifier of the present invention is shown generally at  30  in FIG.  3 . The amplifier circuit  30  comprises a low noise input stage  34  coupled to an output stage  40  including transistor M 1  and having a feedback loop  32  to provide excellent PSRR. The circuit  30  has a high voltage swing, low impedance, high current-driving output stage  40 . The input stage  34  comprises an amplifier having two input terminals, V inm  and V imp . The amplifier  34  is coupled to a global feedback loop  38  coupled to V out  via resistor R 1 , with resistor R 2  coupled to R 1  and ground. 
     The output stage  40  comprises a signal amplifying transistor M 1  conducting current I 1 , coupled to the internal feedback loop  32 . The feedback loop  32  includes a transistor M 2  conducting current I 2  having a gate coupled to node V B  and to the gate of transistor M 1 . The transistor M 2  is driven by the output terminal of amplifier  34  of the input stage. The drain of transistor M 2  is coupled to a return voltage AVSS. The source of transistor M 2  is coupled to and receives fixed current source  12  and an inverting input of feedback amplifier  36  at node V x . The feedback amplifier  36  is coupled at the other input, preferably the positive non-inverting input terminal, to the output terminal V out , the source of transistor M 1 , and the drain of transistor M 3 . The source of transistor M 3  is coupled to the voltage source AVDD. The feedback amplifier  36  controllably drives the gate of transistor M 3  to provide a variable current  13  from source AVDD to the common node of transistor M 1  and the output V out , with the current provided to the load at V out  being the difference of I 3 −I 1 . 
     At first glance the amplifier  34  may appear to be a preamplifier stage driving a source-follower PMOS output stage. However, transistor M 3  advantageously acts as a variable current source, providing all the sourcing current needed for output transistor M 1 . The feedback loop  32  controls the sourcing current I 1  through transistor M 1  to be the same as the current  12  conducting through transistor M 2 . Therefore, output transistor M 1  always conducts a current I 1  from AVDD equal to source current I 2 , regardless of the loading at terminal V out . 
     The feedback loop  32  of the present invention creates a unity gain source-follower amplifier circuit  30 . In this biasing scheme, the main amplifier  34  drives the gate of transistor M 1 , and also the gate of transistor M 2 . If the output V out  goes high, node V x  goes high, which causes node V c  to go low, responsively increasing the current I 3  conducting through transistor M 1  and the current (I 3 −I 1 ) to the load. The output stage  40  of the present invention comprises a source-follower transistor M 1  coupled to a feedback loop  32  that keeps the source-follower transistor M 1  current I 1  constant to a fixed given value. The operation of the output stage  40  is very linear and works well in applications having a high voltage swing relative to the power supply. 
     Assuming that the current  13  through transistor M 3  is less than its absolute limit, the feedback loop  32  forces the voltage gain at V B  to V out {tilde over (=)}1, or as good as the feedback loop  32  can make it. Advantageously, little current is consumed by the circuit  30  when there is no load at V out . Also, the present invention can drive large capacitors such as C 0  placed at V out  in some systems. Preferably, amplifiers  34  and  36  are single stage, low power amplifier designs. 
     If the amplifier  36  voltage gain is reasonably large, which is preferable, the feedback loop  32  through M 2 , amplifier  36 , and M 3  to V out  has a gain approximately equal to 1. To illustrate this, an initial power-up sequence will be described. Initially, V c =A VDD , i R2 =0 R1 =0, i L =0 V out =0 V, V B =A VDD , V x =0 V and V INM =0 V. A VDD  is the analog power supply voltage and may be 2.7 V, for example. Upon power up, since V INM  and V INP &gt;0 (V INM  at time t=0+) the input stage amplifier  34  keeps the voltage at node V B  railed high. Since current I 2  is forced through transistor M 2 , node V x  rises from 0 V. Now the voltage at node V x  is greater than the output voltage V out  (which is still a very low potential) so amplifier  36  forces node V c  to drop. This allows transistor M 3  to provide current through the global feedback loop of R 2  and R 1 , which causes node V INM and V out  to begin to rise. This continues until V INM  and V INP  get close enough in voltage for the input stage amplifier  34  to bring the voltage at node V B  down, which brings the voltage at node V x  down due to the source-follower action of transistor M 2 . Now the voltages at nodes V x  and V out  converge, and the voltage at nodes V INM  and V INP  converge. Therefore, a steady-state is reached when the global feedback loop  38  forces V out  to be what it needs to be to keep the input terminals of the input stage  34  together, and the internal feedback loop  32  forces node V x =V out , which in turn always keeps the currents through transistors M 1  and M 2  equal, or I 1 =I 2 . No current is wasted in the output stage  40  because M 3  only supplies the current (I 3 −I 1 ) needed by the load at V out . Very high output voltage levels relative to power supply A VDD  and/or high current levels (I 3 −I 1 ) may be generated with the present invention, and the quiescent current is very well controlled. The input stage is essentially decoupled from the output stage  40  so that the circuit  30  may be specialized for high PSRR and noise performance. 
     FIGS. 4 and 5 illustrate circuit models used in the following analysis of the amplifier circuit  30  in calculating the output impedance G 0 . Using Kirchoff&#39;s Current Law (KCL) at V out : 
     
       
         g m (0−A 34  V out )−V out g dsM3 =−i t   Equation 1 
       
     
     
       
         I/V=g o , =g mM3 A 34 +g dsM3   Equation 2 
       
     
     The “g dsM3 ” portion of Equation 2 is negligible compared to the other term; therefore, the total output impedance G 0  of circuit  30  is: 
     
       
         G 0 =g mM3 A 34 +g mM2   Equation 3 
       
     
     The above analysis explains how a high conductance G 0  at node V out  is achievable on the output stage, in accordance with the present invention. The g m  of the output stage is essentially the product of the gm of transistor M 3  and amplifier  36 . Amplifier  36  may have a very high gain, on the order of 1000, for example, because it drives a high impedance load. Therefore, the circuit  30  may be very high gain and while requiring very low current. Furthermore, the circuit  30  remains stable when driving very large capacitive loads, represented by capacitor C 0 . This is advantageous because with large load capacitors, if the g m  of the output stage is too small, then the design is typically unstable in a 2-stage architecture. 
     Circuit modeling results conclude the amplifier circuit  30  may be built in a very small area of silicon, for example, 50,000 square microns. The amplifier circuit consumes less than 100 μA when driving a 100 pF load capacitor, assuming no current draw I load  from the load. This is accomplished because the output impedance is approximately equal to g mM3 A 34  as shown above. Testing of the circuit  30  revealed good noise density and transient responses under heavy loading. The circuit  30  proved stable in lab tests, with the PSRR at 50 kHz being 65 dB under maximum 1.24 mA current draw load under worse case conditions. 
     The present invention achieves technical advantages as a microphone bias amplifier having low noise, high PSRR, high output current relative to the quiescent current, and high output voltage relative to the power supply rail. The circuit  30  has a low quiescent current or overall current usage, and the ability to drive high current levels, e.g., 1 mA or greater. The output voltage V out  may be kept close to the power supply rail A VDD , e.g., 2.6 V on a 2.7 V supply. The amplifier circuit  30  has a low output impedance for rejection of any type of coupled noise and uses very little silicon area. Furthermore, the output stage has a high transconductance g m  compared to the g m  of the prior art, so a large capacitor C 0  may be driven at low current levels while maintaining stability. A plurality of amplifiers  30  may be used in a circuit with a minimal amount of current and voltage range being required. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, other transistors driven by a power-down signal, not shown, may be coupled to transistors M 1  and M 3  to ensure that no current flows when the amplifier circuit  30  is powered down. Transistors M 1 , M 2  and M 3  of the present invention preferably comprise PMOS MOSFETS, but may also comprise other transistors such as bipolar, for example. The amplifier circuit of the present invention may be implemented in a wide variety of applications, such telecommunications applications, mobile devices and systems, laptops and personal computers, mixed signal and analog devices, and any low power electrical applications, in general.