Abstract:
A semiconductor integrated circuit, comprises a semiconductor integrated circuit chip; a standard voltage generating means for generating standard voltage other than a supply voltage and a ground voltage, at least one, standard voltage wire for supplying the standard voltage to at least one circuit of said semiconductor integrated circuit chip; at least one first capacitor extending along the standard voltage wire, the first capacitor having the standard voltage wire as one electrode thereof, and the other electrode connected to the supply voltage; and at least one second capacitor extending along the standard voltage wire, the second capacitor having the standard voltage wire as one electrode thereof, and the other electrode connected to the ground voltage.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to semiconductor integrated circuits having a standard voltage wire established at a standard voltage other than supply voltage and ground voltage. 
     Semiconductor integrated circuits, especially MOS dynamic RAMs, have progressed further and further to a high degree of integration and capacity. Consequently, the amount of electric charge for charging and discharging bit lines connected to memory cells has become quite large. Thus, the fluctuation of supply voltages V cc  and V ss , namely, power supply noise, has also increased, so that operation of various circuits suffer undesirable effects. 
     In reference to an address buffer circuit that is one of the sense circuits in an MOS dynamic RAM, the problems encountered may be illustrated in the following discussion taken together with FIG. 1. 
     FIG. 1 is an example of the conventional address buffer circuit. This address buffer circuit has, as its main elements, a first sense MOS transistor Q 1  and a second sense MOS transistor Q 2 . The first MOS transistor Q 1  has a gate input from address signal A in  which feeds thereto one of &#34;H&#34; or &#34;L&#34; voltage levels, and the second MOS transistor Q 2  has a gate input from a standard voltage V R  intermediate &#34;H&#34; and &#34;L&#34; voltage levels. 
     The voltage levels at nodes N 1 , N 2  of a flip-flop 1 consisting of MOS transistors Q 3  through Q 6  are determined in accordance with the difference of conductance between Q 1  and Q 2 , which is brought about by the input noise difference described above. These levels are amplified with a first stage amplifier 2 consisting of MOS transistors Q 7  through Q 11 , and then, amplified again with a second stage amplifier 3 comprising MOS transistors Q 12  through Q 15  and boosting capacitors C3 and C4. As a result, address output A N  and inverted output A N  are provided. MOS transistors Q 18  through Q 21 , are transfer gates. The capacitor C 1  is an element for preventing undershooting, and capacitor C 2  is provided for balancing. 
     The standard voltage V R  is generated by the resistance division network of resistors R 1  and R 2  connected in series between V cc  and V ss  as shown in FIG. 1. The number 4 denotes a standard voltage wire. 
     In the foregoing construction, the standard voltage V R  is not usually generated nearby the sense MOS transistor Q 2  to which V R  is input, but the standard voltage wire 4 is usually formed on the chip in a position remote from Q 2 . Especially, in cases in which the same standard voltage V R  is supplied to a plurality of circuits, the standard voltage wire 4 is extended to a relatively long length in relation to the chip component sizes. Moreover, the standard voltage wire 4 is connected at one end thereof to the electric potential provided by the resistance division network, and thus, the wire 4 is almost in a floating state. 
     As is common, when other signal wires are arranged adjoining the standard voltage wire 4, the potential of the standard voltage V R  will fluctuate in accordance with the coupling capacitance generated by the close wires. Therefore, malfunction of the address buffer circuits is likely to occur. On the other hand, the potential fluctuation of V ss  and V cc  causes fluctuations of the substrate potential. These fluctuations produce further variations of the standard voltage V R , and this variation of the power level also is likely to cause malfunction of the address buffer circuits. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the invention is to provide an improved semiconductor integrated circuit having a standard voltage generation circuit. 
     Another object of the invention is to provide an improved semiconductor integrated circuit for accomplishing stable standard voltage. 
     Another object of the invention is to provide an improved semiconductor integrated circuit for preventing malfunction of same. 
     Another object of the invention is to provide an improved semiconductor integrated circuit for stabilizing a standard voltage against variations caused by signal wires adjoining a standard voltage wire. 
     Another object of the invention is to provide an improved semiconductor integrated circuit for stabilizing a standard voltage against potential fluctuations of the semiconductor substrate. 
     Still another object of the invention is to provide an improved semiconductor integrated circuit for stabilizing a standard voltage against voltage fluctuations of the supply voltage and ground voltage. 
     In accomplishing the foregoing objects, there has been provided according to one aspect of the invention a semiconductor integrated circuit, comprising: a semiconductor integrated circuit chip; a standard voltage generating means for generating a standard voltage other than the supply voltage and ground voltage, and being formed in the semiconductor integrated circuit chip at least one standard voltage wire for supplying said standard voltage to at least one circuit of said semiconductor integrated circuit chip; at least one first capacitor extending along the standard voltage wire, the first capacitor utilizing the standard voltage wire as one electrode, the other electrode thereof being connected to the supply voltage; and at least one second capacitor extending along the standard voltage wire as one electrode, with the other electrode thereof connected to the ground voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with its various features and advantages, will be readily understood from the following more detailed description presented in conjunction with the following drawings, in which: 
     FIG. 1 is a diagram showing a circuit diagram of a conventional address buffer circuit; 
     FIG. 2 is a diagram showing a plan view of a dynamic RAM chip to which the invention is applied; 
     FIG. 3 is a diagram showing a circuit diagram from a standard voltage generating circuit to an address buffer circuit, corresponding to FIG. 2; 
     FIG. 4 is a diagram showing a timing chart of the address buffer circuit shown in FIG. 3; 
     FIG. 5 is a diagram showing an enlarged plan view of a standard voltage wire and capacitors in FIG. 2; 
     FIG. 6a is a diagram showing a cross sectional view along line A--A&#39; of FIG. 5; 
     FIG. 6b is a diagram showing a cross sectional view along line B--B&#39; of FIG. 5; 
     FIG. 7 is a diagram showing an equivalent circuit of a dynamic RAM chip for describing voltage fluctuations; 
     FIG. 8 is a diagram showing another embodiment of a standard voltage wire and its capacitors; and 
     FIG. 9 is a diagram showing still another embodiment of a standard voltage wire and its capacitors. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 is a diagram showing a plan view of a dynamic RAM chip to which the present invention is applied. 
     In a dynamic RAM chip 11, four blocks of memory cell array regions 12 1  through 12 4  are formed. Conventional 1 Tr/1 capacitor cells are used. Between the memory cell array regions, a column address decoder 13 and row address decoders 14 1 , 14 2  are inserted. A pair of address buffer regions 15 1 , 15 2  are also provided. 
     Each of the address buffer regions 15 1  and 15 2  has a plurality of address buffer circuits for each of the columns and rows. Some of the address signals A 0 , A 1 , through A 9  are input to the address buffer region 15 1  from upper bonding pads bp of the chip 11, and other address signals are input to the address buffer region 15 2  from bonding pads of the bottom of the chip 11. The address buffer regions 15 1 , 15 2  convert each of these address signals to a pair of complementary internal signals of A N , A N . These internal signals are then supplied to the corresponding column or row decoders. 
     The input timing of the address signals of the column of the chip is different from that of the row. And, by means of the address signals received with the corresponding decoder 13 or decoders 14 1 , 14 2 , the desired column or row is selected. 
     The chip 11 has a standard voltage generating circuit (standard voltage generating means) 16, which generates 1.6 volts, and supplies it to the address buffer regions of 15 1 , 15 2  and other circuits via standard voltage wires 17. The standard voltage wires 17 diverge near the output terminals of the standard voltage generating circuit 16 and run along both sides of the chip 11. The supply voltage V cc  of 5 volts and ground voltage of 0 volt are supplied, respectively, from a supply voltage pad 18 and a ground voltage pad 19 formed on the chip. A supply voltage wire 20 and a ground voltage wire 21 run parallel and adjacent the standard voltage wires 17. Furthermore, along the standard voltage wires 17, V cc  capacitors Cc and V ss  capacitors Cs are arranged alternately along the entire length thereof. In FIG. 2, only one pair of capacitors Cc and Cs are shown for the sake of clarity of illustration. The substrate of the chip 11 is biased to -3.5 volts with a substrate bias generating circuit (not shown) composed on the chip. 
     FIG. 3 is a circuit diagram showing the standard voltage generating circuit, the standard wire and one of the address buffer circuits in the address buffer region 15 2  described in FIG. 2. 
     The structure of the address buffer circuit itself is not changed as compared with the circuit shown in FIG. 1. That is, this address buffer circuit has a first sense MOS transistor Q 1  and a second sense MOS transistor Q 2 . The first MOS transistor Q 1  has a gate input from address signal A IN  and the second MOS transistor Q 2  has gate input from standard voltage V R  of 1.6 volts. The margin (permitted variation) of A IN  is from -1 to 0.8 volt for a &#34;L&#34; level, and from 2.4 to 6.5 volt for a &#34;H&#34; level. According to the difference of conductance between Q 1  and Q 2 , which is brought about by input differences, the potential levels at N 1  and N 2  of flip-flop 1 consisting of MOS transistors Q 3  through Q 6 , are decided. These potential differences are amplified with the first stage amplifier 2 consisting of MOS transistors Q 7  through Q 11 , and then further amplified with the second stage amplifier 3 consisting of MOS transistors Q 12  through Q 15  and boosting capacitors C 3  and C 4 . As a result, address outputs A N  and A N  are obtained. MOS transistors Q 18 , Q 19 , Q 20  and Q 21  which are formed at the gates of sense MOS transistors Q 1  and Q 2 , are transfer gates. The capacitor C 1  is formed for preventing under-shooting, and capacitor C 2  is attached for balancing. 
     FIG. 4 is a timing chart of clock phases φ1, φ2 and φ3 used in FIG. 3. 
     At first, the connecting terminal p of the MOS transistors Q 9  through Q 11  is supplied with a high voltage to preset the nodes N 3 , N 4  to &#34;H&#34;. Then, by dropping the clock φ1, A IN  and V R  are stored in the gates of the first and second MOS transistors Q 1  and Q 2 , respectively. In the case A IN  is &#34;H&#34;, the sense MOS transistor Q 1  has the conductance higher than that of Q 2 . This makes the voltage of N 1  lower than that of N 2  when the clock φ2 turns on. This voltage difference is also fed back to the gate voltages of MOS transistors Q 5  and Q 6  through the MOS transistors Q 7  and Q 8  of the first stage amplifier 2; thereby the voltage difference is amplified further. The voltage difference also exists in the nodes N 3  and N 4 , and this difference is further amplified by the second stage amplifier 3. When the pulse φ3 is turned on (i.e., goes H) and the boosting capacitors Q 3  and Q 4  are operative, the high level node N 4  is pushed up, and the low level node N 3  is discharged through the MOS transistor Q 7 . Thus, the amplified signals A N  and A N  are obtained. 
     In FIG. 3, the standard voltage V R  is obtained with the resistance division network of resistors R 1  and R 2  and voltages V cc  and V ss  of the standard voltage generating circuit 16. Along the standard voltage wire 17, V cc  capacitors Cc and V ss  capacitors Cs are connected. The capacitance of each V cc  capacitor Cc is made equal to the capacitance of each V ss  capacitor Cs. In FIG. 2 and FIG. 3, the number of the V cc  capacitors Cc is made equal to that of the V ss  capacitors Cs. 
     FIG. 5 is a diagram showing an enlarged plan view of the region A shown in FIG. 2. FIG. 6a and FIG. 6b are diagrams showing the cross sectional views along the line A--A&#39; and B--B&#39; in FIG. 5, respectively. 
     On a P-type Si substrate 51, a SiO 2  layer 52 is formed, and V cc  capacitor electrodes 53 1 , 53 2  and V ss  capacitor electrodes 54 1 , 54 2  are stacked thereon. These capacitor electrodes 53 1 , 53 2 , 54 1  and 54 2  are made from the same level of a poly-Si layer, and have an L-shape. Furthermore, on these electrodes, 1 m thickness of an CVD SiO 2  layer 55 is formed. Contact holes C 1  through C 4  are opened in this SiO 2  layer 55. Onto the substrate, a standard voltage wire 56, V ss  wire 57 and V cc  wire 58 are arranged in parallel. Adjoining to the standard voltage wire 56, signal wires 59 and 60 are arranged. These are, for instance, clock signal wires. The wires 56 through 60 are made from the same level of an A1 layer. 
     As shown in FIG. 5 and FIG. 6b, the V cc  capacitor electrode 53 1  and 53 2  are connected with V cc  wire 58 at the contact holes of C 2  and C 4  ; on the other hand, the V ss  capacitor electrode 54 1  and 54 2  are connected V ss  wire 57 at the contact holes C 1  and C 3 . Hence, each of the capacitors Cc and Cs are formed along with the standard voltage wire 56, and alternately arranged. The width W of the standard voltage wire 56 is designed to be on the order of 1.2 μm, and the length L of each capacitor electrode is designed to be on the order of 50 μm. In FIG. 5, the lengthwise scale of the capacitor electrode is shown shorter than actual size for convenience of illustration. 
     According to this embodiment, the fluctuation of standard voltage V R , which is caused by the capacitor coupling with adjoining wires such as wires 59, 60 can be greatly reduced. As the capacitance accompanying the standard voltage wire becomes large, the capacitor coupling ratio with other adjacent wires reduces, thereby reducing undesired fluctuations of V R . 
     Further, the fluctuations of the standard voltage V R  caused by fluctuations of the substrate potential, which depends on the noise of V cc  and V ss , is also greatly reduced. The fluctuations of the substrate potential changes the standard voltage V R  because of the proximity of the voltage wire 56 to the surface of the substrate. The aforementioned reduction is attained because the capacitors Cc and Cs in this embodiment behave as shields. Moreover, the fact that the capacitance accompanying the standard voltage wire is large consequently reduces the capacitor coupling ratio with the substrate which also contributes to stabilization of the standard voltage V R . 
     As for the noise levels of V cc  and V ss , the fluctuations arise with opposite phase. In this embodiment, however, capacitors of Cc and Cs are both fabricated so as to offset the influence of the capacitor adjacent thereto. Therefore, malfunction of the address buffer circuits can be prevented. 
     Noise levels of V cc  and V ss  occurs mainly when a relatively large current flows, and especially occurs at the precharging and discharging of the bit lines of the memory cell array. The connecting state of dynamic RAM chip and an outer power supply are described below in reference to FIG. 7. 
     FIG. 7 is a diagram showing a simplified equivalent circuit of a dynamic RAM chip for describing the voltage fluctuations of V cc  and V ss . As shown in FIG. 7, inductances L 1  and L 2  are inherently present in the wires connecting a power supply Vc to a dynamic Ram chip DR. Further inductances L 3  and L 4  are present, respectively, in the V cc  and V ss  wires. The numeral N 1  &#39; denotes the Si-substrate. Capacitance C 1  &#39; and C 3  &#39; are present between the node N 1  &#39; and V cc , V ss  wires. Between the nodes N 1  &#39; and N 2  &#39;, in which N 2  &#39; designates bit lines, the capac-itance C 2  &#39; is present. It will be understood that in the precharging period for bit lines, the capacitance C 2  &#39; is charged. On the other hand, capacitance C 2  &#39; is discharged in the bit line discharging period. The MOS transistor Tr 1  denotes the transistor for precharging, having an input pulse φbp. The MOS transistor Tr 2  having an input pulse φbd denotes the transistor for discharging. 
     When the MOS transistor Tr 1  turns on, charging for the bit lines begins and the current I begins to flow. A number of bit lines are charged or discharged, thereby the amount of the current has a large value. 
     At this time, for example in charging, the fluctuation of supply voltage V cc  is expressed as follows: ##EQU1## The fluctuation of the ground voltage V ss  is expressed as follows: ##EQU2## The polarity in these equations is provided according to the direction of the current. 
     As described above, the dropping of the V cc  level and the rising of the V ss  level occur simultaneously. 
     In the embodiment described above, the V cc  capacitors and V ss  capacitors are arranged alternately along the standard voltage wire. Therefore, at any position, the influence of the noise of V cc  and V ss  can be reduced uniformly. 
     FIG. 8 is a diagram showing another embodiment of the standard voltage wire and its capacitors. The same numerals are used in this figure as for corresponding parts in FIG. 5. 
     In this embodiment, the V cc  capacitor electrodes 53 1  &#39;, 53 2  &#39; and V ss  capacitor electrodes 54 1  &#39;, 54 2  &#39; are formed in one body respectively adjacent and contacting the V cc  wire 58 and the V ss  wire 57 and are all made from a first A1 layer. The standard voltage wire 56&#39; and signal wires 59&#39;, 60&#39; are made from a second A1 layer. Between the first and second A1 layers, a CVD SiO 2  layer of 1.4 μm thickness is formed. 
     FIG. 9 is a diagram showing another embodiment of the standard voltage wire and its capacitors. In this embodiment, the standard voltage wire 56, the signal wire 60 and the V cc  wire 58 are made from a first A1 layer. The V cc  capacitor electrodes 53 1  and 53 2  are both made from the same level layer of poly-Si as in FIG. 5. The V ss  wire 57&#39; of a second A1 layer overlaps the standard voltage wire 56, and forms a V ss  capacitor on the entire upper surface of the standard voltage wire 56. The thickness of the CVD SiO 2  layer formed between the first and second A1 layers is 1.4 μm, which is thicker than that of the layer between the poly-Si layer and the first A1 layer of 1 μm, thereby gaps remain between each V cc  capacitor electrode of 53 1  and 53 2  for equalizing the value of both capacitors. It will be obvious that the relation between V cc  and V ss  may be reversed to that shown in FIG. 9. 
     The invention is not restricted to the embodiments described above. For instance, in the embodiments shown, the standard voltage generating circuit is positioned between the address buffer regions, however, it is possible to extend a standard voltage wire from the standard voltage generating circuit and supply the standard voltage to the address buffer regions by one standard voltage wire, such as by means of moving the standard voltage generating circuit to the left bottom corner in FIG. 2. 
     Furthermore, in the embodiments, the address buffer circuit region of the dynamic RAM is applied. However, the present invention can be applied to other sense circuit regions that perform the sense action by a similar principle using a standard voltage having a medium level between &#34;H&#34; and &#34;L&#34; levels of the input signal. For instance, data input buffer circuits may be applied. Furthermore, the invention is not restricted to a specific sense circuit region, for example, in the case for setting the cell plate electrode (common memory capacitor electrode) of a MOS dynamic RAM to a medium voltage, it is effective to arrange the V cc  and V ss  capacitor along the standard voltage wire connecting the cell plate to the standard voltage generating circuit which generates the voltage between the supply voltage V cc  and the ground voltage V ss , similar to the embodiment described above. This formation can be effective to prevent potential fluctuations of the cell plate. 
     In the embodiments described above, it is preferable to set the length of each V cc  and V ss  capacitor along the standard voltage wire to at least five times longer than the width of the standard voltage wire, and particularly to at least twenty times longer than the width of the standard voltage wire. 
     Other modifications and improvements of the invention will also become apparent to those skilled in the art, and the invention is intended to cover such modifications and improvements as defined by the appended claims.