Abstract:
Method and apparatus for use with simultaneous bi-directional (SBD) input/output circuits are included among the embodiments. In exemplary systems, the receiver in an SBD circuit compares a bit line voltage to two different voltages representing the two voltages that are expected on the bit line, based on the data that the driver in the SBD circuit is currently driving. Other embodiments are described and claimed.

Description:
RELATED APPLICATIONS  
         [0001]    This application claims the benefit of Korean Patent Applications No. 2002-87887, filed Dec. 31, 2002 and 2003-25085, filed Apr. 21, 2003, the disclosures of which are hereby incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to semiconductor devices employing simultaneous bi-directional (SBD) transmission, and more particularly to methods and apparatus for SBD input/output circuits for such devices.  
           [0004]    2. Description of the Related Art  
           [0005]    Semiconductor devices such as processors, controllers, memory devices, etc., are commonly equipped with data transceivers that allow them to receive and transmit digital signals. Conventionally, such transceivers are reconfigurable to either receive or transmit data across an attached transmission line. Recently, devices with simultaneous bi-directional (SBD) transmit/receive capability have received increased interest. As the name alludes to, SBD transceivers have the capability to receive and transmit digital data during the same clock cycle, on the same transmission line.  
           [0006]    [0006]FIG. 1 shows a conventional SBD connection between two semiconductor devices  20  and  40 . Devices  20  and  40  contain, respectively, SBD transceivers  22  and  42 . SBD transceiver  22  contains a data driver  24  and a data receiver  26 . An internal data signal to be driven, Dout 1 , is supplied as an input to driver  24  and as a control signal to receiver  26 . The output of driver  24  is coupled to the input of receiver  26 . Receiver  26  also receives two reference voltages, VrefH and VrefL, which it uses for comparisons, as will be explained shortly. The output of receiver  26  is a data input, Din 1 , to device  20 .  
           [0007]    Transceiver  42  of device  40  is preferably matched to transceiver  22  of device  20 . Transceiver  42  contains a driver  44  and a receiver  46  connected in an identical configuration as the driver and receiver of transceiver  22 . Driver  44  takes its input from an internal data signal Dout  2 , and receiver  46  generates a data input Din 2 .  
           [0008]    Semiconductor devices  20  and  40  can be connected to each other in the configuration shown in FIG. 1, by connecting the outputs of drivers  24  and  44  to a transmission line  30 . Note that in this configuration, the drive state of both driver  24  and driver  44  determine the voltage V BL  on transmission line  30 . A common reference voltage generator  32  supplies VrefH and VrefL to both circuits.  
           [0009]    [0009]FIG. 2 contains waveforms illustrating the simultaneous exchange of data between devices  20  and  40  over transmission line  30 . Dout 1  is high during time periods T1, T2, and T5. Dout  2  is high during time periods T1, T3, and T5. Consequently, during T1, drivers  24  and  44  both pull the voltage V BL  on the transmission line high, e.g., to an upper rail voltage V h . During T2, driver  24  attempts to pull the voltage V BL  high and driver  44  attempts to pull V BL  low, e.g., to a lower rail voltage V 1 . With matched drivers, V BL  will assume an approximate voltage V mid , halfway between upper rail voltage V h  and the lower rail voltage V 1 . During T3, both drivers reverse, and V BL  stays at V mid . During T4, both drivers pull V BL  low, to V 1 .  
           [0010]    Receivers  26  and  46  determine the drive state of the other device&#39;s driver during each time period by selecting an appropriate comparison voltage, based on the known drive state of their own driver. For instance, during T1 and T2, receiver  26  knows that driver  24  is driving line  30  high-thus the only two possible values of V BL  are V h  (when driver  44  is also driving line  30  high) and V mid  (when driver  44  is driving line  30  low). Thus during T1, receiver  26  selects the reference voltage VrefH in response to a logic high level on Dout 1  and then compares V BL , with its high level (Vh), to VrefH, at a level of ¾ V DD , and outputs Din 1  as a high level. Also, during T2, the receiver  26  also selects the reference voltage VrefH in response to a logic high level on Dout 1  and then compares V BL , now with a V mid  level, to VrefH, at a level of ¾V DD , and outputs Din 1  as a low level. During T3, the receiver  26  selects the reference voltage VrefL in response to a logic low level on Dout 1  and then compares V BL , with its V mid  level, to VrefL, at a level of ¼ V DD , and outputs Din 1  as a high level. Also, during T4, the receiver  26  also selects the reference voltage VrefL of ¼ V DD  in response to a logic low level on Dout 1  and then compares V BL , now with a low level, to VrefL, at a level of ¼ V DD , and outputs Din 1  as a low level. Receiver  46  operates similarly, but based on the known state of driver  44 , to determine the drive state of driver  24 .  
           [0011]    In some prior art implementations, the reference signals VrefH and VrefL are generated separately on each device. Some receivers use multiplexers, with Dout as a select signal, to decide which of the two reference signals will be compared to V BL . Other receivers use a buffer to selectively generate one of VrefH and VrefL for comparison with V BL .  
           [0012]    In the prior art devices, the SBD receivers compare the voltage V BL  to a single reference voltage VrefL or VrefH, representing 0.25 V DD  and 0.75 V DD , depending on the value of Dout for that SBD device. Referring to FIG. 3A, receiver  26  of FIG. 1 compares V BL  to 0.75 V DD  during time periods T1, T2, and T5, and compares V BL  to 0.25 V DD  during time periods T3 and T4. Likewise and as shown in FIG. 3B, receiver  46  compares V BL  to 0.75 V DD  during time periods T1, T3, and T5, and compares V BL  to 0.25 V DD  during time periods T2 and T4. Consequently, at each time period the maximum differential voltage applied to each differential receiver is approximately 0.25 V DD . This small margin can be readily eroded by noise and driver mismatches, and can also be substantially affected by small errors in the reference voltages VrefL or VrefH, which are not voltages naturally produced by SBD circuits during signaling. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1 illustrates two prior-art SBD transceivers, on separate semiconductor devices, connected by a transmission line;  
         [0014]    [0014]FIG. 2 illustrates data input value/output value relationships for the transceivers of FIG. 1;  
         [0015]    [0015]FIGS. 3A and 3B show, respectively, the comparisons made by the two SBD transceivers of FIG. 1 for various driven data states;  
         [0016]    [0016]FIG. 4 illustrates two SBD transceivers according to some embodiments of the present invention, connected by a transmission line;  
         [0017]    [0017]FIGS. 5A and 5B depict, respectively, the comparisons made by the two SBD transceivers of FIG. 4 for various driven data states;  
         [0018]    [0018]FIG. 6 illustrates two SBD transceivers according to other embodiments of the present invention, connected by a transmission line;  
         [0019]    [0019]FIGS. 7A and 7B depict, respectively, the comparisons made by the two SBD transceivers of FIG. 6 for various driven data states;  
         [0020]    [0020]FIGS. 8 and 9 illustrate, respectively, a receiver circuit and reference selector useful in some embodiments of the present invention;  
         [0021]    [0021]FIG. 10 shows an alternate embodiment of a reference selector;  
         [0022]    [0022]FIG. 11 shows an alternate embodiment of a receiver circuit; and  
         [0023]    [0023]FIG. 12 illustrates a driver circuit useful in at least some embodiments of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0024]    The embodiments described herein seek to replace the single comparison between a voltage on the transmission line and a synthesized 0.25 V DD  or 0.75 V DD  reference voltage, as practiced in prior art SBD receivers. Succinctly stated, various receiver embodiments described herein use two comparison voltages that each approximate one of the two voltages that could appear on an SBD transmission line.  
         [0025]    [0025]FIG. 4 illustrates a configuration  50  comprising two semiconductor devices  60  and  70  connected by two transmission lines  80  and  90 . Device  60  comprises an SBD input/output (I/O) circuit  100 , and device  70  comprises an SBD input/output circuit  200 . Transmission line  80  connects to an I/O pad  120  of SBD I/O circuit  100  at one end, and to an I/O pad  220  of SBD I/O circuit  200  at the other end. Transmission line  90  connects to a VREFM generator  190  on device  60  in order to supply VREFM to device  70  (alternately, each device can generate its own VREFM reference or the VREFM generator can only be located in the device  70 ). VREFM generator  190  can also supply VREFM to other SBD I/O circuits (not shown) on either device.  
         [0026]    SBD I/O circuit  100  comprises a driver  110 , a reference selector  130 , and a receiver  150 . Driver  110  can operate in a conventional manner to drive an output signal Dout 1  through pad  120  onto transmission line  80 . Reference selector  130  uses output signal Dout 1  to select a first reference voltage VREFD1 for input to receiver  150 ; VREFM generator  190  supplies a second reference voltage VREFM to receiver  150 . A third input to receiver  150  connects to I/O pad  120 , and therefore supplies a voltage V BL  to receiver  150 . As will be explained shortly, receiver  150  uses VREFD1, VREFM, and V BL  from transmission line  80  to output a signal Din 1  representative of the signal Dout  2  signaled by SBD I/O circuit  200 .  
         [0027]    SBD I/O circuit  200  comprises a driver  210 , a reference selector  230 , and a receiver  250 , configured substantially similarly to the corresponding elements of SBD I/O circuit  100 .  
         [0028]    The operation of receiver  150  will now be explained with reference to FIG. 5A, with an underlying assumption that drivers  110  and  210  are capable of driving transmission line  80  to three possible voltages V DD , V SS , and 0.5(V DD -V SS ). To simplify the discussion, V SS =0 V will be assumed, although those skilled in the art recognize that other values of V SS  can be selected in a particular implementation, and voltages V DD  and V SS  may not represent full rail voltages in other implementations due to driver limitations.  
         [0029]    During time periods T1 and T2, Dout 1  is a logic high value, and therefore the two possible expected values of V BL  are V DD  and V DD /2. VREFM generator  190  sets VREFM to V DD /2, and reference selector  130  sets VREFD1 to V DD , because the level of Dout 1  is a high level. In other words, if the level of Dout 1  is a low level, the reference selector  130  sets VREFD1 to V SS . The reference selector  230  operates the same as reference selector  130 . Receiver  150  thus compares V BL  to V DD  and V DD /2, setting Din 1  to a logic high value when V BL  is closer to V DD  (time period T1) and setting Din 1  to a logic low value when V BL  is closer to V DD /2 (time period T2).  
         [0030]    During time periods T3 and T4, Dout 1  is a logic low value, and therefore the two possible expected values of V BL  are V DD /2 and V SS . Accordingly, reference selector  130  sets VREFD1 to V SS . Receiver  150  thus compares V BL  to V DD /2 and V SS , setting Din 1  to a logic high value when V BL  is closer to V DD /2 (time period T3) and setting Din 1  to a logic low value when V BL  is closer to V SS .  
         [0031]    [0031]FIG. 5B illustrates the similar operation of SBD I/O circuit  200  for the same Dout 1 /Dout 2  drive sequence.  
         [0032]    [0032]FIG. 6 illustrates a configuration  55  comprising two semiconductor devices  65  and  75  connected by three transmission lines  85 ,  95  and  97 . Device  65  comprises an SBD input/output (I/O) circuit  300 , a VREFM1-1 generator  380 , and a VREFM2-1 generator  390 . Device  75  comprises an SBD input/output circuit  400 , a VREFM1-2 generator  480 , and a VREFM2-2 generator  490 . Transmission line  85  connects to an I/O pad  320  of SBD I/O circuit  300  at one end, and to an I/O pad  420  of SBD I/O circuit  400  at the other end. Transmission line  95  connects VREFM1-1 generator  380  on device  65  to VREFM2-2 generator  490  on device  75 . Transmission line  97  connects VREFM2-1 generator  390  on device  65  to VREFM1-2 generator  480  on device  75 .  
         [0033]    SBD I/O circuit  300  comprises a driver  310  and a receiver  350  that functionally incorporates an internal reference selector. Driver  310  can operate in a conventional manner to drive an output signal Dout 1  through pad  320  onto transmission line  85 . Receiver  350  receives output signal Dout 1 , which it uses to operate a corresponding portion of the receiver. Five comparison voltages are supplied to receiver  350 : rail voltages V DD  and V SS , voltage V BL , and voltages VREFM1-1 and VREFM2-1 generated respectively by reference generators  380  and  390 . As will be explained shortly, receiver  350  uses these voltages to output a signal Din 1  representative of the signal Dout 2  signaled by SBD I/O circuit  400 .  
         [0034]    SBD I/O circuit  400  comprises a driver  410  and a receiver  450  configured substantially similarly to the corresponding elements of SBD I/O circuit  300 .  
         [0035]    The use of two mid-point reference voltages VREFM1 and VREFM2 on each device accounts for the possibility that drivers  310  and  410  may not be perfectly matched. In such a circumstance, slightly different voltages V BL  are observed when driver  310  attempts to pull the line high and driver  410  attempts to pull the line low, compared to when driver  310  attempts to pull the line low and driver  410  attempts to pull the line high (see FIG. 7A, voltages V MID1  and V MID2  for V BL  during time periods T2 and T3, respectively). To increase the accuracy of the receiver operation, two different midpoint voltages are calculated and used in these two situations.  
         [0036]    Generator  380  is matched to driver  310 —or at least to the pull-up portion of driver  310 —and has an input tied permanently to V DD  (or possibly a logic high signal) in one embodiment. In operation, then, generator  380  is always attempting to pull line  95  high with the same strength that driver  310  attempts to pull line  85  high when Dout 1  is a logic high value.  
         [0037]    Generator  490  is matched to driver  410 —or at least to the pull-down portion of driver  410 —and has an input tied permanently to V SS  (or possibly to a logic low signal) in one embodiment. In operation, then, generator  490  is always attempting to pull line  95  low with the same strength that driver  410  attempts to pull line  85  low when Dout 2  is a logic low value.  
         [0038]    When generators  380  and  490  are connected by transmission line  95 , a VREFM1-1 value is supplied to receiver  350  that should accurately match V BL  when Dout 1  is a logic high value and Dout 2  is a logic low value, even if drivers  310  and  410  are not perfectly matched. The same value is supplied to receiver  450  as VREFM2-2.  
         [0039]    Generators  390  and  480  are constructed similar to their respective counterparts  490  and  380  and are connected in operation by transmission line  97 . Accordingly, a VREFM2-1 value is supplied to receiver  350  that should accurately match V BL  when Dout 1  is a logic low value and Dout 2  is a logic high value, even if drivers  310  and  410  are not perfectly matched. The same value is supplied to receiver  450  as VREFM1- 2 .  
         [0040]    The operation of receivers  350  and  450  can be better understood with reference to FIGS. 7A and 7B. Referring first to FIG. 7A, during time periods T1 and T2, Dout 1  is a logic high value, and therefore the two possible expected values of V BL  are V DD  and V MID1 . Accordingly, receiver  350  activates a portion of its circuitry that compares V BL  to V DD  and VREFM1-1, setting Din 1  to a logic high value when V BL  is closer to V DD  (time period T1) and setting Din 1  to a logic low value when V BL  is closer to V MID1  (time period T2).  
         [0041]    During time periods T3 and T4, Dout 1  is a logic low value, and therefore the two possible expected values of V BL  are V MID2  and V SS . Accordingly, receiver  350  activates a portion of its circuitry that compares V BL  to V MID2  and V SS , setting Din 1  to a logic high value when V BL  is closer to V MID2  (time period T3) and setting Din 1  to a logic low value when V BL  is closer to V SS .  
         [0042]    [0042]FIG. 7B shows a similar selection of comparison voltages for receiver  450 . Because driver  410  drives opposite of driver  310  when V BL  is equal to V MID1  or V MID2 , however, the voltage values supplied to receiver  450  as VREFM1-2 and VREFM2-2 are switched from the corresponding values in FIG. 7A.  
         [0043]    [0043]FIG. 8A contains a circuit diagram for some embodiments of a receiver  150  (or  250 ) as shown in FIG. 4. The receiver comprises two differential amplifiers  151  and  153  and a load circuit  155 .  
         [0044]    Load circuit  155  comprises first and second matched load resistors R L . One end of each resistor is connected to V DD . The other end of the first resistor connects to a differential output node OUT; the other end of the second resistor connects to a second differential output node OUTB. An output stage (not shown) converts the voltage difference appearing across OUT and OUTB to a logic signal Din.  
         [0045]    Differential amplifier  151  contains two matched depletion-mode N-channel MOSFET transistors N 1  and N 2 , and a third N-channel MOSFET transistor N 3 . Transistor N 3  has a drain connected to a tail current node, a source connected to V SS , and a gate connected to an input node BIAS. BIAS is set by a biasing circuit (not shown) that sets the tail current I A  flowing from the tail current node through transistor N 3 , such that N 3  acts as a current source for differential amplifier  151 .  
         [0046]    The sources of matched transistors N 1  and N 2  connect to the tail current node and therefore split tail current I A  according to the differential voltage applied to their gates. The gate of transistor N 1  receives the signal VREFM from VREFM generator  190  (FIG. 4), and the gate of transistor N 2  receives the voltage signal V BL . The drain of N 1  connects to output node OUT, and the drain of N 2  connects to output node OUTB.  
         [0047]    Differential amplifier  153  is identical to differential amplifier  151 . Differential amplifier  153  contains two matched depletion-mode N-channel MOSFET transistors N 4  and N 5 , and a third N-channel MOSFET transistor N 6 . Transistor N 6  has a drain connected to a tail current node, a source connected to V SS , and a gate connected to the input node BIAS. BIAS sets the tail current I B  flowing from the tail current node through transistor N 6 , such that N 6  acts as a current source for differential amplifier  153  and I A =I B .  
         [0048]    The sources of matched transistors N 4  and N 5  connect to the tail current node and therefore split tail current I B  according to the differential voltage applied to their gates. The gate of transistor N 4  receives the voltage signal V BL , and the gate of transistor N 5  receives the signal VREFD1 from reference selector  130  (FIG. 4). The drain of N 5  connects to output node OUT, and the drain of N 4  connects to output node OUTB.  
         [0049]    Because differential amplifiers  151  and  153  both connect to load circuit  155 , both tail current I A  and tail current I B  must flow from positive voltage rail V DD  through load circuit  155 . The combined current I A +I B  is split between the two load resistors depending on the values of VREFM, VREFD1, and V BL . For example, consider the conditions shown during time period T1 in FIG. 5A, wherein V BL =VREFD1=V DD  and VREFM=V DD /2. Under these conditions N 2  will be driven harder than N 1  and carry more than half of I A , thus dropping the voltage at OUTB as compared to OUT. N 4  and N 5  will be driven approximately the same and will split I B  equally, and thus no differential voltage will appear across OUT/OUTB as a result of amplifier  153 . The net effect is a positive differential voltage between OUT and OUTB, indicating that Din should be set to a logic high condition.  
         [0050]    For time period T2 of FIG. 5A, VREFD1 remains at V DD  and VREFM remains at V DD /2, but V BL  drops to V DD /2. Accordingly, N 1  and N 2  will be driven approximately the same and will split I A  equally, and thus no differential voltage will appear across OUT/OUTB as a result of amplifier  151 . N 5  will be driven harder than N 4 , however, and carry more than half of I B , thus dropping the voltage at OUT as compared to OUTB. The net effect is a negative differential voltage between OUT and OUTB, indicating that Din should be set to a logic low condition.  
         [0051]    Continuing with time period T3 of FIG. 5A, V BL =VREFM=V DD /2, but reference selector  130  now sets VREFD1 to V SS . Accordingly, N 1  and N 2  will be driven approximately the same and will split I A  equally, and thus no differential voltage will appear across OUT/OUTB as a result of amplifier  151 . N 4  will be driven harder than N 5 , however, and carry more than half of I B , thus dropping the voltage at OUTB as compared to OUT. The net effect is a positive differential voltage between OUT and OUTB, indicating that Din should be set to a logic high condition.  
         [0052]    Finally, consider time period T4 of FIG. 5A, when VREFD1 remains at V SS  and VREFM remains at V DD /2, but V BL  drops to V SS . Under these conditions N 1  will be driven harder than N 2  and carry more than half of I A , thus dropping the voltage at OUT as compared to OUTB. N 4  and N 5  will be driven approximately the same and will split I B  equally, and thus no differential voltage will appear across OUT/OUTB as a result of amplifier  153 . The net effect is a negative differential voltage between OUT and OUTB, indicating that Din should be set to a logic low condition.  
         [0053]    Several features of this embodiment are evident. First, the two differential amplifiers nominally complement each other—when one receives a differential input voltage, the other does not, and therefore both can drive the same load circuit to create a common output. Second, the reference values all correspond to values generated on transmission line  80 , which can therefore be generated fairly accurately. Third, the differential input voltage that is nominally amplified is 0.5 V DD , whereas the prior art single-amplifier configurations amplify a 0.25 V DD  differential signal for the same voltage.  
         [0054]    For low-voltage signaling, the embodiment of FIG. 8 is particularly useful because it uses larger differential input voltages and therefore has a superior noise margin. For instance, consider a case where V DD =1 V and V SS =0 V and two drivers are both trying to drive V BL  to V DD , but because of noise or other effects V BL =0.8 V. A prior art receiver would compare V BL =0.8 V to VREFH=0.75 V and attempt to sense a logic high signal from a 0.05 V differential voltage. Receiver  150 , on the other hand, would amplify a 0.3 V differential signal in differential amplifier  151 , and an opposing −0.2 V differential signal in differential amplifier  153 , which is equivalent to amplifying a 0.1 V differential voltage in a prior art receiver. Thus receiver  150  has twice the noise margin of a prior art receiver.  
         [0055]    [0055]FIG. 9 illustrates one embodiment for reference selector  130  of FIG. 4. A low voltage VL is applied to the source of a P-channel MOSFET transistor P 7 , and a high voltage VH is applied to the source of an N-channel MOSFET transistor N 7 . The drains of transistors P 7  and N 7  are both connected to supply VREFD1, the output of reference selector  130 . The gates of transistors P 7  and N 7  are both connected to DOUT 1 . When DOUT 1  is a logic high signal, VH is passed as VREFD1, and when DOUT 1  is a logic low signal, VL is passed as VREFD1. VL and VH may be adjusted if necessary to account for the threshold voltages of P 7  and N 7  such that VREFD1 approximate high and low voltages.  
         [0056]    [0056]FIG. 10 illustrates a second embodiment for reference selector  130  of FIG. 4. Two transmission gates T 1  and T 2  are both connected to VREFD1, the output of reference selector  130 . A low voltage VL is connected to the input of T1, and a high voltage VH is connected to the input of T 2 . DOUT 1  is connected to the input of an inverter I 1 , which generates the logical inverse of DOUT 1 , DOUT 1 #. DOUT 1  and DOUT 1 # are applied to the control gates of transmission gate T 1  such that T 1  is on when DOUT 1  is logic low. DOUT 1  and DOUT 1 # are applied to the opposite control gate terminals of transmission gate T 2  such that T 2  is on when DOUT 1  is logic high.  
         [0057]    [0057]FIG. 11 illustrates a circuit diagram for one embodiment of receiver  350  of FIG. 6, which accepts four reference voltages V DD , V SS , VREFM1, and VREFM2. Instead of the FIG. 4/FIG. 7 approach of multiplexing two reference voltages to the same transistor gate (transistor N 5 ), each reference voltage in FIG. 11 is supplied to the gate of its own transistor in its own differential amplifier. Different differential amplifiers are activated and deactivated depending on the state of Dout 1 .  
         [0058]    Receiver  350  contains a load circuit  355  and differential amplifiers  351  like the corresponding circuits in receiver  150 . In receiver  350 , however, VREFM1 is applied to the gate of N 1  and V DD  is applied to the gate of N 5 , since these are the two comparison voltages to be used when Dout 1  is a logic high value.  
         [0059]    A control voltage BIAS 1  is applied to tail current transistors N 3  and N 6 , causing them to generate matching tail currents I A1  and I B1 , respectively. BIAS 1  can be shorted to ground through a transistor N 14 , however, causing transistors N 3  and N 6  to turn off. The logic signal Dout 1  is applied to the input of an inverter  12  to produce the logical inverse of Dout 1 , Dout 1 #. Dout 1 # is applied to the gate of transistor N 14 , such that N 14  remains off when Dout 1  is in a logic high state (time periods T1 and T2 of FIG. 7A), causing differential amplifiers  351  and  353  to perform comparisons as previously described for amplifiers  151  and  153  of FIG. 8. When Dout 1  is in a logic low state, however, (time periods T3 and T4 of FIG. 7A), Dout 1 # activates N 14  to turn off current flow through differential amplifiers  351  and  353 .  
         [0060]    Receiver  350  includes a duplicate set of differential amplifiers  357  and  359 , which are activated when differential amplifiers  351  and  353  are deactivated, and vice versa. Differential amplifier  357  contains a matched differential transistor pair N 8  and N 9  and a current source transistor N 1 . Transistor N 8  receives a gate voltage VREFM2. Transistor N 9  receives a gate voltage V BL . Preferably, transistors N 8  and N 9  are matched to transistors N 1  and N 2  as well, although this is not strictly necessary.  
         [0061]    Differential amplifier  359  contains a matched differential transistor pair N 11  and N 12  and a current source transistor N 13 . Transistor N 11  receives a gate voltage V BL . Transistor N 12  receives a gate voltage V SS . Preferably, transistors N 11  and N 12  are matched to transistors N 4  and N 5  as well, although this is not strictly necessary.  
         [0062]    A control voltage BIAS 2  is applied to tail current transistors N 10  and N 13 , causing them to generate matching tail currents I A2  and I B2 , respectively. Preferably, BIAS 1 =BIAS 2  and N 10 , N 13  are matched to N 3 , N 6 , such that I A2  and I B2  have the same magnitude as I A1  and I B1  when activated. BIAS 2  can be shorted to ground through a transistor N 15 , causing transistors N 10  and N 13  to turn off. Dout 1  is applied to the gate of transistor N 15 , such that N 15  remains off when Dout 1  is in a logic low state (time periods T3 and T4 of FIG. 7A), causing differential amplifiers  357  and  359  to perform comparisons as previously described for amplifiers  151  and  153  of FIG. 8. When Dout 1  is in a logic high state, however, (time periods T1 and T2 of FIG. 7A), Dout 1  activates N 15  to turn off current flow through differential amplifiers  357  and  359 .  
         [0063]    BIAS 1  and BIAS 2  can be supplied from individual bias circuits. In the alternative, BIAS 1  and BIAS 2  can be supplied from a common BIAS circuit that connects to BIAS 1  and BIAS 2  through pass transistors (not shown) that disconnect BIAS 1  or BIAS 2  from BIAS when BIAS 1  or BIAS 2  will be shorted to ground.  
         [0064]    Inverter-type drivers can be used in each of the described embodiments. FIG. 12 shows a circuit diagram for an alternate embodiment of driver  110 . Driver  110  connects a resistor  112  between V DD  and output node  120 . Output node  120  is also connected to V SS  through a serial combination of two n-channel transistors N 20  and N 21 . N 20  receives a gate voltage VGATE, e.g., fixed at V DD /2. N 21  receives as its gate voltage the output of an inverter  13 , which has its input connected to Dout 1 . When Dout 1  is at a logic high value, transistor N 21  is turned off and node  120  is pulled up through resistor  112 . When Dout 1  is at a logic low value, transistor N 21  is turned on and node  120  is also pulled down through transistors N 20  and N 21 . Driver  110  has a small input capacitance as compared to an inverter-type driver.  
         [0065]    Those skilled in the art will recognize that many other device configuration permutations can be envisioned and many design parameters have not been discussed. For example, the circuit of FIG. 11 could be adapted to a three-reference voltage system with only one midpoint voltage by using three differential amplifiers and having the one receiving the midpoint voltage unswitched. Or, reference selector  130  of FIG. 4 could be adapted to multiplex two midpoint voltages, allowing the receiver of FIG. 8 to be used in the system of FIG. 6. Specific voltages, resistance values, transistor sizes, etc., have not been specified as these will change from application to application. Likewise, functionality shown embodied in a single functional block may be implemented using multiple cooperating circuits or blocks, or vice versa. The integrated circuits described can be any type of circuit that inputs digital data from and sends digital data to another circuit, e.g., a microprocessor or other programmable processor, a memory controller, a memory device, a serializer/deserializer, etc. Such minor modifications and implementation details are encompassed within the embodiments of the invention, and are intended to fall within the scope of the claims.  
         [0066]    The preceding embodiments are exemplary. Although the specification may refer to “an”, “one”, “another”, or “some” embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.