Abstract:
Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first word line for reading a third data from the memory cell, and comparing the second and the third data for determining if an electrical coupling path exists between the first word line and a second word line.

Description:
BACKGROUND OF THE INVENTION  
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a word line defect detecting device, and more particularly, to a detecting device for determining if a word line is short-circuited with other word lines. 
         [0003]    2. Description of the Prior Art 
         [0004]    In the memory, the data can be stored through a word line and a bit line into a corresponding memory cell. However, when a first word line is short-circuited with a second word line, if a data is to be written into a first memory cell corresponding to the first word line, the data is simultaneously written into a second memory cell corresponding to the second word line. In this way, the data pre-stored in the second memory cell is damaged. Therefore, an incorrect data is obtained when the second memory cell is read, causing a great inconvenience. 
       SUMMARY OF THE INVENTION  
       [0005]    The present invention provides a word line detecting device. The detecting device comprises a first word line, a second word line, and a controller. The first word line is coupled to at least a memory cell. The second word line is disposed adjacent to the first word line. The controller is coupled to the first word line and the second word line. The controller activates the first word line for reading a first data pre-stored in the memory cell. Then the controller suspends the first word line for a predetermined period. Then the controller writes a second data complementary to the first data into the memory cell. Then the controller activates the first word line again for reading a third data from the memory cell and compares the third data with the second data for determining if an electrical coupling path exists between the first word line and the second word line. 
         [0006]    The present invention further provides a method for detecting word line defect, wherein a memory cell is coupled to a first word line and the first word line is adjacent to a second word line. The method comprises (a) activating the first word line for reading a first data pre-stored in the memory cell, (b) suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, (c) activating again the first word line for reading a third data from the memory cell, and (d) comparing the second and the third data for determining if an electrical coupling path exists between the first word line and the second word line. 
         [0007]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0008]      FIG. 1  is a diagram illustrating a word line defect detecting device of the present invention. 
           [0009]      FIG. 2  is a flowchart illustrating a method for detecting word line defects of the present invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0010]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a word line defect detecting device  100  of the present invention. The detecting device  100  comprises a controller  110 , a decoder  120 , two drivers P 1  and P 2 , two word lines W 1  and W 2 , and two bit lines B 1  and B 2 , wherein the word line W 1  is adjacent to the word line W 2 . 
         [0011]    The memory cells M 11  and M 12  are both coupled to the word line W 1 , and respectively coupled to the bit lines B 1  and B 2 ; the memory cells M 21  and M 22  are both coupled to the word line W 2 , and respectively coupled to the bit lines B 1  and B 2 . 
         [0012]    Please refer to  FIG. 2 .  FIG. 2  is a flowchart illustrating a method  200  for detecting word line defects of the present invention. Assuming that the detecting device  100  is to determine if the word line W 1  has a defect, which means that the detecting device  100  is to determine if an electrical coupling path exists between the word lines W 1  and W 2 , the detecting device  100  executes the procedures of  FIG. 2 , which are illustrated in detail as follow:
   step  201 : the controller  110  controls the decoder  120  and the driver P 1  to activate the word line W 1 , and simultaneously to keep the word line W 2  deactivated;   step  202 : the controller  110  read data D 1  stored in the memory cell M 11  through the corresponding bit line B 1 ;   step  203 : the controller  110  turns off the decoder  120  and the driver P 1  for a predetermined period T P  for suspending the word line W 1 ;   step  204 : after the predetermined period T P , the controller  110  turns on the driver P 1  (the decoder  120  still remains turned-off) for writing a data D 2 , which is complementary to the data D 1 , into the memory cell M 11  through the bit line B 1 ;   step  205 : the controller  110  controls the decoder  120  and the driver P 1  to activate the word line W 1  again;   step  206 : the controller  110  reads a data D 3  stored in the memory cell M 11  through the bit line B 1 ;   step  207 : the controller  110  determines if an electrical coupling path exists between the word lines W 1  and W 2  according to the data D 1  and D 3 .   
 
         [0020]    A word line is activated or deactivated by means of the decoder  120  and the driver corresponding to the word line. For instance, if the word line W 1  is to be activated, the decoder  120  has to send a signal representing “activating” to the driver P 1  for activating the word line W 1 ; otherwise, if the word line is to be deactivated, the decoder  120  has to send a signal representing “deactivating” to the driver P 2  for deactivating the word line W 2 . In addition, the activated word line W 1  and the deactivated word line W 2  are driven respectively to a activating voltage level V ACT  and a deactivating voltage level V DEACT . For example, assume the activating voltage level V ACT  is a high voltage level (for example, 5 volts), and the deactivating voltage level V DEACT  is a low voltage level (for example, 0 volt). In this way, when the word line W 1  is activated, the voltage level of the word line W 1  is 5 volts; when the word line W 2  is deactivated, the voltage level of the word line W 2  is 0 volt. Or, assume the activating voltage level V ACT  is a low voltage level (for example, 0 volt), and the deactivating voltage level V DEACT  is a high voltage level (for example, 5 volts). In this way, when the word line W 1  is activated, the voltage level of the word line W 1  is 0 volt; when the word line W 2  is deactivated, the voltage level of the word line W 2  is 5 volts. A threshold voltage level V TH  is predetermined between the activating voltage level V ACT  and the deactivating voltage level V DEACT . When the voltage level of a word line is between the activating voltage level V ACT  and the threshold voltage level V TH , the memory cells corresponding to the word line can be written or read through the corresponding bit lines; otherwise, When the voltage level of a word line is between the deactivating voltage level V DEACT  and the threshold voltage level V TH , the memory cells corresponding to the word line can not be written or read through the corresponding bit lines. Hereinafter, assume the activating voltage level V ACT  is 5 volts, the deactivating voltage level V DEACT  is 0 volt, and the threshold voltage level V TH  is 3 volts. 
         [0021]    In the step  201 , activating the word lines means the voltage level of the word line W 1  is driven to 5 volts (V ACT ), and deactivating the word line W 2  means the voltage level of the word line W 2  is driven to 0 volt (V DEACT ). 
         [0022]    In the step  202 , since the word line W 1  is already activated, the memory cell M 1    1  can transmit the stored data D 1  to the controller  110  through the bit line B 1 . 
         [0023]    In the step  203 , the controller  110  turns off the decoder  120  and the driver P 1  so as to suspend the word line W 1 . Since the word line W 1  is activated previously and the word line W 2  is deactivated previously, the voltage levels of the word lines W 1  and W 2  are 5 volts and 0 volt, respectively. As the above-mentioned, the condition of the memory cell M 11  capable of being written or read is that the voltage level of the word line W 1  is higher than 3 volts (threshold voltage level V TH ). If an electrical coupling path exists between the word lines W 1  and W 2 , the voltage level of the word line W 1  are lowered down because of the leakage to the word line through the electrical coupling path. As a result, in the step  203 , the objective of suspending the word line W 1  for the predetermine period T P  is to detect if an electrical coupling path exists between the word lines W 1  and W 2 . In other words, if there is no electrical coupling path between the word lines W 1  and W 2 , then after the step  203 , the voltage level of the word line W 1  can still remain 5 volts so that the memory cell M 11  can be written or read; if there is an electrical coupling path between the word lines W 1  and W 2 , then after the step  203 , the voltage level of the word line W 1  is lowered down so that the memory cell M 11  can not be written or read. 
         [0024]    In the step  204 , after the predetermined period T P , the controller  110  turns on the driver P 1  and writes the data D 2  complementary to the data D 1  into the memory cell M 11 . That is, if the data D 1  is logic “ 1 ”, the data D 2  is logic “ 0 ”; if the data D 1  is logic “ 0 ”, the data D 2  is logic “ 1 ”. Since the decoder  120  still remains turned-off at the time, the word line W 1  is not be activated again (that is, the voltage level of the word line W 1  is not driven to 5 volts). In this way, if an electrical coupling path exists between the word lines W 1  and W 2 , the data D 2  can not be written into the memory cell M 11 ; if no electrical coupling path exists between the word lines W 1  and W 2 , the data D 2  can be written into the memory cell M 11  through the bit line B 1 . More particularly, if an electrical coupling path exists between the word lines W 1  and W 2 , after the step  204 , the stored data of the memory cell M 11  still remains the previously stored data D 1 ; if no electrical coupling path exists between the word lines W 1  and W 2 , the stored data of the memory cell M 11  becomes the data D 2 . 
         [0025]    In the step  205 , the controller  110  turns on the decoder  120  and the driver P 1 , and activates the word line W 1  again. That is, in the step  205 , the voltage level of the word line W 1  is driven to 5 volts again. In this way, in the step  206 , the controller  110  can read the data D 3  stored in the memory cell M 11  through the bit line B 1 . 
         [0026]    In step  207 , the controller  110  compares the data D 3  read in the step  206  and the data D 1  read in the step  202  for determining if an electrical coupling path exists between the word lines W 1  and W 2 . More particularly, in the step  204 , the controller  110  writes the data D 2  complementary to the data D 1 . Thus, if the data D 2  is written successfully in the step  204 , the data D 3  read in the step  207  is data D 2 ; if the data D 2  is written unsuccessfully in the step  204 , the data D 3  read in the step  207  is data D 1 . Hence, the controller  110  can determine if an electrical coupling path exists between the word lines W 1  and W 2  by means of comparing the data D 3  and D 1 . More precisely, if the data D 3  is complementary to the data D 1 , it represents the data D 2  is written successfully in the step  204 . Therefore, the controller  110  can determine no electrical coupling path between the word lines W 1  and W 2 ; if the data D 3  is equal to the data D 1 , it represents the data D 2  is written unsuccessfully in the step  204 . Therefore, the controller  110  can determine an electrical coupling path between the word lines W 1  and W 2 , and accordingly determine the word line W 1  has a defect. 
         [0027]    In conclusion, the detecting device provided by the present invention can detect if an electrical coupling path exists between two adjacent word lines by means of suspending one of the word lines for a predetermined period and then writing a complementary data into the word line. In this way, the word lines having defects can be efficiently determined, providing a great convenience. 
         [0028]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.