Abstract:
A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of semiconductor devices; more specifically, it relates to strained semiconductor devices and the methods of fabricating strained semiconductor devices. 
       BACKGROUND 
       [0002]    Strained devices utilize the principle that the mobility of carriers in semiconductor devices can be manipulated by stressing the semiconductor material. However, present techniques can result in non-uniform strain. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove. 
       SUMMARY 
       [0003]    A first aspect of the present invention is a structure, comprising: a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap. 
         [0004]    A second aspect of the present invention is a method, comprising: forming a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation in the substrate; forming a first stressed layer over the first region; forming a second stressed layer over second region, the first and second stressed layers overlapping over the trench isolation; removing the overlapped first and second stressed layers to form a gap separating the first stressed layer from second stressed layer; and forming a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap. 
         [0005]    These and other aspects of the invention are described below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0007]      FIGS. 1 through 7  are cross-sectional views illustrating fabrication of strained semiconductor devices according to an embodiment of the present invention; and 
           [0008]      FIG. 8  is a cross-sectional view of strained devices similar to those illustrated in  FIG. 7  fabricated in a bulk semiconductor substrate. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    In n-channel field effect transistors (NFETs), the mobility of the majority carriers, electrons, is greater (hole mobility is less) when the channel is in tensile stress in the direction of current flow. In p-channel field effect transistors (PFETs) the mobility of the majority carriers, holes, is greater (electron mobility is less) when the channel region is in compressive stress in the direction of current flow. Increasing the mobility of majority carriers increases the performance of the device. Formation of an internally stressed layer over an FET induces the same type of stress as the overlying stressed layer into the channel of the FET. Such an FET is termed “a strained device” or “strained FET.” 
         [0010]    The embodiments presented herein describe a structure and a method whereby oppositely stressed layers are formed on different regions of a semiconductor substrate. The stressed layers induce strain into the underlying semiconductor substrate. In selected regions, the oppositely stressed layers are spaced apart and do not overlap and do not abut so in the selected regions there is no region where the stresses in the stressed layers are directly opposing each other. However, there may or may not be other regions of the semiconductor substrate where the stressed layers do overlap. 
         [0011]      FIGS. 1 through 7  are cross-sectional views illustrating fabrication of strained semiconductor devices according to an embodiment of the present invention. In  FIG. 1 , a silicon-on-insulator (SOI) substrate  100  includes an upper semiconductor layer  105  separated from a lower supporting substrate  110  by a buried oxide layer  115 . In one example, upper semiconductor layer  105  is single-crystal silicon. Formed in upper substrate  105  is trench isolation  120 . A top surface  122  of trench isolation  120  is coplanar with a top surface  123  of semiconductor layer  105 . Trench isolation  120  extends to abut buried oxide layer  115 . In one example, trench isolation  120  is formed, by etching (e.g., by reactive ion etch (RIE)) a trench into semiconductor layer using a patterned photoresist layer as an etch mask, removing the photoresist, depositing an insulating layer to overfill the trench and then performing a chemical-mechanical-polish (CMP) to coplanarize the top surface  122  of the trench isolation  120  and the top surface  123  of semiconductor layer  105 . In one example, trench isolation  120  comprises silicon oxide (SiO 2 ). 
         [0012]    Next an n-channel field effect transistor (NFET)  125 A is formed in a region  127  of substrate  100  and a p-channel field effect transistor (PFET)  125 B is formed in a region  128  of substrate  100 . Regions  127  and  128  are separated by a region trench isolation  120 . NFET  125 A includes N-type source/drains  130 A separated by a P-type channel region  135 A under a gate electrode  140 A. Gate electrode  140 A is electrically isolated from source/drains  130 A and channel region  135 A by a gate dielectric layer  145 A. Insulating sidewall spacers  150 A are formed opposite side walls of gate electrode  140 A. PFET  125 B includes P-type source/drains  130 B separated by an N-type channel region  135 B under a gate electrode  140 B. Gate electrode  140 B is electrically isolated from source/drains  130 B and channel region  135 B by a gate dielectric layer  145 B. Insulating sidewall spacers  150 B are formed opposite side walls of gate electrode  140 B. 
         [0013]    In one example, sidewall spacers  150 A and  150 B comprise silicon nitride (Si 3 N4), SiO 2  or combinations of layers thereof. In one example, gate electrodes  140 A and  140 B comprise doped or undoped polysilicon. 
         [0014]    In  FIG. 2 , a dielectric tensile stressed layer  155  is formed over NFET  125 A, PFET  125 B and trench isolation  120 . In one example, tensile stressed layer  155  is Si 3 N 4 . In one example, a tensile stressed Si 3 N 4  layer is formed by low-pressure chemical vapor deposition (LPCVD) using silane (SiH 4 ) and ammonia (NH 3 ) precursor gases. In one example, a tensile stressed layer  155  is between about 50 nm and about 100 nm thick. In one example, the amount of tensile stress applied to NFET  125 A by tensile stressed layer  155  is between about 0.5 GPa and about 4 GPa. 
         [0015]    In  FIG. 3 , tensile stressed layer  155  is removed from over PFET  125 B using a photolithographic/etch process. For example, a patterned photoresist layer is formed over tensile stressed layer  155  and the tensile stressed layer etched, for example, using RIE, where the tensile stressed layer is not covered by the patterned photoresist layer, followed by removal of the patterned photoresist layer. In  FIG. 3 , tensile stressed layer overlaps a region of trench isolation  120  between NFET  125 A and PFET  125 B. Tensile stressed layer  155  does not overlap any region of PFET  125 B. 
         [0016]    In  FIG. 4 , a dielectric compressive stressed layer  160  is formed over PFET  125 B, trench isolation  120  and remaining portions of tensile stressed layer  155 . In one example, compressive stressed layer  160  is Si 3 N 4 . In one example, a compressive stressed Si 3 N 4  layer is formed by high density plasma (HDP) deposition or plasma enhanced chemical vapor deposition (PECVD) using SiH 4 , NH 3  and nitrogen (N 2 ) precursor gases. In one example, a compressive stressed layer  160  is between about 60 nm and about 120 nm thick. In one example, the amount of compressive stressed applied to PFET  125 B by compressive stressed layer  160  is between about 0.5 GPa and about 4 GPa. 
         [0017]    In  FIG. 5 , compressive stressed layer  160  is removed from over NFET  125 A using a photolithographic/etch process. For example, a patterned photoresist layer is formed over compressive stressed layer  160  and the compressive stressed layer etched, for example, using RIE, where the compressive stressed layer is not covered by the patterned photoresist layer, followed by removal of the patterned photoresist layer. In  FIG. 5 , compressive stressed layer  160  overlaps a region of trench isolation  120  between NFET  125 A and PFET  125 B. Compressive stressed layer  160  overlaps tensile stressed layer  155  in an overlap region  165 . Compressive stressed layer  160  does not overlap any region of NFET  125 A. Overlap region  165  does not extend over NFET  125 A or PFET  125 B. 
         [0018]    It should be understood though tensile stressed layer  155  has been illustrated as being formed and etched before forming compressed stressed layer  160 , alternatively compressed stressed layer  160  be formed and etched before forming tensile stressed layer  155 . This would result in tensile stressed layer  155  being on top of compressive stressed layer  160  in overlap region  165 . 
         [0019]    In  FIG. 6 , tensile stressed layer  155  and compressive stressed layer  160  have been removed in overlap region  165  (see  FIG. 5 ) using a photolithographic/etch process to form a gap  170  between tensile stressed layer  125 A and compressive stressed layer  160 . For example, a patterned photoresist layer is formed over tensile stressed layer  155  and compressive stressed layer  160  and the tensile and compressive stressed layers etched, for example, using RIE, where the compressive stressed layer is not covered by the patterned photoresist layer (i.e., in overlap region  165  of  FIG. 5 ), followed by removal of the patterned photoresist layer. Trench isolation  120  is exposed in gap  170  and gap  170  is fully landed (i.e., does not extend over any regions of silicon layer  105 ) on trench isolation  120 . 
         [0020]    Because tensile stressed layer  155  and compressive stressed layer  160  are not overlapped and because tensile stressed layer  155  does not abut compressive stressed layer  160  due to gap  170 , the stressed induced into NFET  125 A is only due to tensile stressed layer  155  and is not influenced by compressive stressed layer  160 . Because tensile stressed layer  155  and compressive stressed layer  160  are not overlapped and because tensile stressed layer  155  does not abut compressive stressed layer  160  due to gap  170 , the stressed induced into PFET  125 B is only due to compressive stressed layer  160  and is not influenced by tensile stressed layer  155 . Further the stress induced in the semiconductor regions of NFET  125 A and PFET  125 B is more uniform as the effect of overlapped stress layers on the underlying substrate is highest proximate to the overlapped region and diminishes with distance. 
         [0021]    In  FIG. 7 , a passivation layer  170  is formed over tensile stressed layer  155 , compressive stressed layer  160  and trench isolation  120  in gap  170 . Passivation layer  175  seals the gap and prevents contaminants entering NFET  125 A or PFET  125 B by diffusion through trench isolation  120  into silicon layer  105 . In one example, passivation layer  175  is unstressed. In one example, passivation layer  175  is in a compressive stress less than that of compressive stressed layer  160 . In one example, passivation layer  175  is in a tensile stress less than that of tensile stressed layer  155 . In one example, passivation layer  175  is unstressed Si 3 N 4 . In one example, passivation layer  175  is Si 3 N 4  in a compressive stress less than that of compressive stressed layer  160 . In one example, passivation layer  175  is Si 3 N 4  in a tensile stress less than that of tensile stressed layer  155 . It is preferred that the amount of stress in passivation layer  175  (whether compressive or tensile) be as low as possible. In one example, passivation layer  175  is a Si 3 N 4  layer which is formed by high density plasma (HDP) deposition or plasma enhanced chemical vapor deposition (PECVD) using SiH 4 , NH 3  and nitrogen (N 2 ) precursor gases. In one example, a passivation layer is between about 20 nm and about 40 nm thick. 
         [0022]      FIG. 8  is a cross-sectional view of strained devices similar to those illustrated in  FIG. 7  fabricated in a bulk semiconductor substrate. In  FIG. 8 , an NFET  125 C and a PFET  125 D have been fabricated in a bulk semiconductor substrate  180 . In one example, substrate  180  is single-crystal silicon. NFET  125 C is similar to NFET  125 A except source/drains  130 A and channel region  135 A are formed in a P-well  185 . PFET  125 D is similar to PFET  125 B except source/drains  130 B and channel region  135 B are formed in an N-well  190 . 
         [0023]    Thus the embodiments of the present invention provide more uniformly strained semiconductor devices by eliminating the overlap of differently stressed films in selected regions of the integrated circuit chip. 
         [0024]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.