Abstract:
Structures and methods are described that inhibit atomic migration which otherwise creates an undesired capacitive-resistive effect arising from a relationship between a metallization layer and an insulator layer of a semiconductor structure. A layer of an inhibiting compound may be used to inhibit a net flow of atoms so as to maintain conductivity of the metallization layer and maintain the low dielectric constant of a suitable chosen insulator material. Such a layer of inhibiting compound continues to act even with the reduction of ground rules in succeeding generations of semiconductor processing technology. 
     One embodiment includes an insulator having a first substance, wherein the first substance is selected from a group consisting of a polymer and an insulating oxide compound. The embodiment includes an inhibiting layer on the insulator, wherein the inhibiting layer includes a compound formed from a reaction that includes the first substance and a second substance. The second substance is selected from a group consisting of a transition metal, a representative metal, and a metalloid. The embodiment includes a highly conductive metallization layer on the inhibiting layer.

Description:
RELATED APPLICATIONS 
     This application is related to the following co-pending and commonly assigned application: U.S. Ser. No. 09/483,881 filed, Jan. 18, 2000, entitled A Selective Electroless-Plated Copper Metallization which is hereby incorporated by reference; U.S. Ser. No. 09/483,002 filed, Jan. 18, 2000, entitled “Process for Providing Seed Layers for Using Aluminum, Copper, Gold, and Silver Metallurgy,” which is hereby incorporated by reference; U.S. Ser. No. 09/483,098, filed Jan. 18, 2000, entitled “Method and Apparatus for Making Integrated-Circuit Wiring From Copper, Silver, Gold, and Other Metals,” which is hereby incorporated by reference; U.S. Ser. No. 09/483,303 filed Jan. 18, 2000, entitled “Methods for Making Integrated-Circuit Wiring From Copper, Silver, Gold, and Other Metals,” which is hereby incorporated by reference. 
    
    
     TECHNICAL FIELD 
     The technical field relates generally to semiconductor structures. More particularly, it pertains to metallization layers in semiconductor structures. 
     BACKGROUND 
     One of the main issues confronting the semiconductor processing industry is that of the capacitive-resistance problem in metallization layers. An industry-wide effort has undertaken to address the problem. Since the beginning, the semiconductor processing industry has relied on aluminum and aluminum alloys to serve as metallization layers. Silicon dioxide was selected as the insulator of choice although polyimide, a polymer, was used in a number of products by IBM for a number of years. With each succeeding generation of technology, the capacitive-resistance problem grows. Because each generation requires that the dimensions of the semiconductor structure be reduced, the minimum line-space combination must also decrease. As the line-space combination decreases, the capacitance and resistance of the semiconductor structure increases. Thus, these increases contribute to the problem. 
     Copper metallurgy has been proposed as a substitute for aluminum metallurgy as a material for the metallization layers since copper exhibits greater conductivity than aluminum. Yet several problems have been encountered in the development of copper metallurgy. The main issue is the fast diffusion of copper through an insulator, such as silicon dioxide, to form an undesired copper oxide compound. Another issue is the known junction-poisoning effect of copper. These issues have led to the development of a liner to separate the copper metallization layer from the insulator. The use of titanium nitride as a liner was proposed by C. Marcadal et al., “OMCVD Copper Process for Dual Damascene Metallization,” VMIC Conference Proceedings, p. 93-7 (1997). The use of tantalum nitride as a liner was proposed by Peijun Ding et al., “Copper Barrier, Seed Layer and Planarization Technologies,” VMIC Conference Proceedings, p. 87-92 (1997). The use of titanium as a liner was proposed by F. Braud et al.; “Ultra Thin Diffusion Barriers for Cu Interconnections at the Gigabit Generation and Beyond,” VMIC Conference Proceedings, p. 174-9 (1996). The use of tungsten silicon nitride as a liner was proposed by T. Iijima et al., “Microstructure and Electrical Properties of Amorphous W—Si—N Barrier Layer for Cu Interconnections,” VMIC Conference Proceedings, p. 168-73 (1996). The use of zirconium, hafnium, or titanium as a liner was proposed by Anonymous, “Improved Metallurgy for Wiring Very Large Scale Integrated Circuits,” International Technology Disclosures, v. 4 no. 9, (Sep. 25, 1996). The use of titanium as a liner was proposed by T. Laursen, “Encapsulation of Copper by Nitridation of Cu—Ti Alloy/Bilayer Structures,” International Conference on Metallurgical Coatings and Thin Films in San Diego, Calif., paper H1.03 p. 309 (1997). The use of tantalum, tungsten, tantalum nitride, or trisilicon tetranitride as a liner is currently favored by the industry. See Changsup Ryu et al., “Barriers for Copper Interconnections,” Solid State Technology, p. 53-5 (1999). 
     Yet another solution to the problem of fast diffusion of copper through an insulator was proposed by researchers at Rensselaer Polytechnic Institute (hereinafter, RPI). See S. P. Muraka et al., “Copper Interconnection Schemes: Elimination of the Need of Diffusion Barrier/Adhesion Promoter by the Use of Corrosion Resistant, Low Resistivity Doped Copper,” SPIE, v. 2335, p. 80-90 (1994) (hereinafter, Muraka); see also Tarek Suwwan de Felipe et al., “Electrical Stability and Microstructural Evolution in Thin Films of High Conductivity Copper Alloys,” Proceedings of the 1999 International Interconnect Technology Conference, p. 293-5 (1999). These researchers proposed to alloy copper with a secondary element, which is either aluminum or magnesium. In their experiments, they used copper alloys with at least 0.5 atomic percent aluminum or 2 atomic percent magnesium. When the copper alloy is brought near the insulator, silicon dioxide, the secondary element and silicon dioxide form dialuminum trioxide or magnesium oxide. The formed dialuminum trioxide or magnesium oxide acts as a barrier to the fast diffusion of copper into the silicon dioxide. 
     Along the same technique as proposed by RPI, Harper et al. discuss in U.S. Pat. No. 5,130,274 (hereinafter, IBM) the use of a copper alloy containing either aluminum or chromium as the secondary element. As above, the secondary element with the insulator, such as silicon dioxide or polyimide, forms a barrier to the fast diffusion of copper. 
     Semiconductor products with some of the discussed solutions to the fast diffusion of copper have begun to ship, on a limited basis, and yet the problem of reducing the resistivity in ever smaller line dimensions is still present. It has been shown by Panos C. Andricacos, “Copper On-Chip Interconnections,” The Electrochemical Society Interface, pg. 32-7 (Spring 1999) (hereinafter Andricacos), that the effective resistivity obtainable by the use of barrier layers was approximately 2 microhm-centimeters with a line width greater than 0.3 micrometer. The effective resistivity undesirably increases for lines narrower than that. The alloy approach investigated by RPI had similar resistivity values as found by Andricacos. RPI also found that the use of 0.5 atomic percent aluminum, in the copper, was apparently insufficient to give complete protection from copper diffusion into the silicon dioxide although a significant reduction in the rate of copper penetration through the silicon dioxide was achieved. It should be noted that the maximum solubility of aluminum in copper is 9.2 weight percent or approximately 18 atomic percent whereas the maximum solubility of magnesium in copper is 0.61 weight percent or approximately 0.3 atomic percent. Thus, the alloys used by RPI were saturated with magnesium but far below the saturation limit when aluminum was used as the secondary element in the alloy. 
     Other researchers have focused on the capacitive effect. The capacitive effect has been studied with respect to polymers, such as polyimide, which are used to substitute for silicon dioxide as insulation in semiconductor structures. Some of these polymers have dielectric constants that are considerably lower than silicon dioxide, and a presumption can be made that the use of these polymers should lessen the undesired capacitive effect. Yet, when one of these polymers is cured to form an insulator near the vicinity of the copper metallization layer, the polymer reacts with the copper metallization layer to form copper dioxide, a conductive material. See D. J. Godbey et al., “Copper Diffusion in Organic Polymer Resists and Inter-Level Dielectrics,” Thin Solid Films, v. 308-9, p. 470-4 (1970) (hereinafter, Godbey). This conductive material is dispersed within the polymer thereby effectively raising the dielectric constant of the polymer and in many cases even increasing its conductivity. Hence, the undesired capacitive effect continues even with the use of lower dielectric polymer materials. 
     Andricacos points out that the use of copper along with cladding offers a significant improvement in conductivity over the titanium/aluminum-copper alloy/titanium sandwich structure now in widespread use throughout the industry. Andricacos also noted that as the line width decreases even a thin liner would undesirably effect the line resistance. The proposals by RPI and IBM attempt to address this problem by forming the liner using a copper alloy. The liner formed using a copper alloy displaces a portion of an area that was occupied by the insulator. 
     However, in solving one problem, RPI and IBM introduce another problem. The copper alloys used by RPI and IBM essentially lack the desirable properties of copper that initially drove the industry to use it. As was pointed out by RPI, the use of an alloy containing aluminum, even at a concentration so low as to not be completely effective in preventing the diffusion of copper, shows a measurable increase in resistance. IBM used only one layer of the alloy. Yet, that one layer has a high concentration of aluminum and will undoubtedly have an undesired effect on the resistivity. 
     As the minimum dimensions shrink, the use of even a twenty-Angstrom layer of an alloy with higher resistivity will have a significant effect on the total resistivity of the conductor composite. For example, a 200-Angstrom film on both sides of a 0.1 micron trench is 40 percent of the total trench width. Therefore, at the same time that the dimensions of the metallization layer decrease, the specific resistivity undesirably increases. 
     It has also been shown that there is a significant difference between the amount of the undesired copper oxide compound that is formed when a polyimide insulator is used if the acidity of the polymer solution is low. This is the case if the precursor used in the formation of the polyimide is an ester instead of acid. In the case of PI-2701, which is a photosensitive polyimide that starts from an ester precursor, the amount of oxide formed is reduced by a factor of approximately four as compared to films with a similar final chemistry. See Godbey. It is thought that the slight acidity of PI-2701 may come from the photo-pac or the process used to form it. The films in the study by Godbey were all prepared by curing the liquid precursor in air or in an approximately inert environment. It is also well known that copper oxide will not form in and can be reduced by a high purity hydrogen atmosphere. 
     Muraka opines that the use of titanium as a barrier layer was found to increase the resistivity of the copper film significantly when heat-treated at temperatures of 350 degrees Celsius or above. If the heat-treatment was carried out in hydrogen, no increase in resistivity was reported. As this temperature is above the eutectoid temperature of the titanium-hydrogen system, the formation of titanium hydride is assumed to have occurred. Muraka also asserts that a similar increase in resistivity is seen with zirconium and hafnium containing copper alloys, yet Muraka provides no data to support the assertion. 
     Other research results weaken the conclusion of Muraka. See Saarivirta 1; see also U.S. Pat. No. 2,842,438 to Matti J. Saarivirta and Alfred E. Beck (Jul. 8, 1958). If one looks at the equilibrium phase diagrams of the copper-titanium and copper-zirconium systems, it can be seen that the solubility of zirconium in copper is more than ten times less than that of titanium. See Metals Handbook, v. 8, p. 300-2 (8 th  Ed.). It should also be noted that a series of copper-zirconium alloys have been disclosed that have quite good electrical conductivity. 
     It has been shown that alloys containing more than about 0.01 weight percent zirconium have a significant loss of conductivity in the as-cast state. See Matti J. Saarivirta, “High Conductivity Copper-Rich Cu—Zr Alloys,” Trans. of The Metallurgical Soc. of AIME, v. 218, p. 431-7 (1960) (hereinafter, Saarivirta 1). It has also been shown that the conductivity of even a 0.23 weight percent zirconium alloy is restored to above 90 percent of IACS when the alloy, in the cold drawn state, is heat-treated above 500 degrees Celsius for one hour. This shows that a significant amount of the zirconium, which was in solid solution in the as-cast state, has precipitated as pentacopper zirconium. From this data, it can be seen that if the zirconium content in the copper is kept low the conductivity of the resulting metallurgy can be above 95 percent of IACS. If it is desired to deposit a zirconium layer on top of a copper layer the temperature of deposition of the zirconium should be kept below 450 degrees Celsius, such as between 250 degrees Celsius and 350 degrees Celsius. Such deposition may occur in a single damascene process or at the bottom of vias in a dual-damascene process. The term “vias” means the inclusion of contact holes and contact plugs. When the deposition temperature is kept in this range, a thin layer of pentacopper zirconium tends to form initially thus inhibiting the diffusion of zirconium into the copper. While even at 450 degrees Celsius the solubility is low enough to give very good conductivity, and although zirconium and titanium have many properties that are very similar, their solubility in copper differs by more than a factor of ten. Therefore, the use of zirconium is much preferred over titanium for this application. 
     What has been shown is the need of the semiconductor processing industry to address the issue of interconnecting devices in integrated circuits as these circuits; get smaller with each generation. Although aluminum was initially used as the metal for interconnecting, copper has emerged as a metal of choice. However, because of the fast diffusion of copper into the semiconductor insulator, the capacitive-resistive problem becomes an important issue that must be addressed. One solution is to use a liner, but with the reduction in the geometry of the circuits, the dimensions of the liner become inadequate to prevent the fast diffusion of copper. Another solution is to form a barrier material from the insulator and a copper alloy; this solution seems promising at first, but because the copper is alloyed, the desirable conductivity property of copper is diminished. 
     Thus, what is needed are structures and methods to inhibit the fast diffusion of copper so as to enhance the copper metallization layer in a semiconductor structure. 
     SUMMARY 
     The above-mentioned problems with copper metallization layer as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems, devices, structures, and methods are described which accord these benefits. 
     An illustrative embodiment includes a method for preparing a copper wiring system for ultra-large-scale integrated circuits. This copper wiring system has a high conductivity and low capacitive loading. 
     Another illustrative embodiment includes a method for constructing an insulator, such as an oxide compound or a polymer structure. The insulator is made impervious to the copper, which is not alloyed. Because the copper is not alloyed, the copper can have as low a resistivity as possible depending on the method of deposition and the resulting microstructure. 
     Another illustrative embodiment includes a method for forming an enhanced metallization layer. The method comprises forming an insulator layer having a first substance. The first substance comprises a material selected from a group consisting of a polymer, a foamed polymer, a fluorinated polymer, a fluorinated-foamed polymer, and an oxide compound. The method further comprises forming an inhibiting layer on the insulator layer. The forming of the inhibiting layer includes depositing a second substance on the insulator layer using a technique selected from a group consisting of low-energy implantation and chemical vapor deposition. The second substance is selected from a group consisting of a transition metal, a representative metal, and a metalloid. The process of forming the inhibiting layer includes reacting the first substance and the second substance to form a compound so as to inhibit undesired atomic migration. The method further comprises forming a copper metallization layer on the inhibiting layer. 
     Another illustrative embodiment includes a semiconductor structure. The structure comprises an insulator layer having a first substance. The first substance is selected from a group consisting of a polymer, a foamed polymer, a fluorinated polymer, a fluorinated-foamed polymer, an aerogel, and an insulator oxide compound. The polymer includes polyimide. The insulator oxide compound includes silicon dioxide. The semiconductor structure includes an inhibiting layer on the insulator layer. The inhibiting layer comprises a compound formed from a reaction that includes the first substance and a second substance. The second substance is selected from a group consisting of a transition metal, a representative metal, and a metalloid. The transition is selected from a group consisting of chromium, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, niobium, and tantalum. The representative metal is selected from a group consisting of aluminum and magnesium. The metalloid includes boron. The semiconductor structure also includes a copper metallization layer on the inhibiting layer. 
     These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 a cross-sectional view of a semiconductor structure according to one embodiment the p sent invention. 
     FIGS. 2A-2F are cross-sectional views of a semiconductor structure during processing according to one embodiment of the present invention. 
     FIGS. 3A-3C are closed-up cross-sectional views of a semiconductor structure during pressing according to one embodiment of the present invention. 
     FIG. 4 a block diagram of a device according to one embodiment of the present invention 
     FIG. 5 is an elevation view of a semiconductor wafer according to one embodiment the present invention. 
     FIG. 6 is a block diagram of a circuit module according to one embodiment oft present invention. 
     FIG. 7 is a block diagram of a memory module according to one embodiment of the present invention. 
     FIG. 8 is a block diagram of a system according to one embodiment of the present invention 
     FIG. 9 is a block diagram of a system according to one embodiment of the present invent 
     FIG. 10 is a block diagram of a system according to one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     n the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. 
     The terms wafer and substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure and layer formed above, and the terms wafer or substrate include the underlying layers containing such regions/junctions and layers that may have been formed above. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims. 
     The embodiments described herein focus on the formation of an inhibiting layer interposed between an insulator and a copper metallization layer, which is not alloyed, so as to inhibit the undesired diffusion of copper into the insulator. 
     FIG. 1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention. Semiconductor structure  100  includes a substrate  199 , and a number of semiconductor device structures, such as devices  101 A and  101 B. Devices  101 A and  101 B include active devices, such as transistors, and passive devices, such as capacitors, or a combination of active and passive devices. The semiconductor structure  100  optionally includes a protective layer  102 . In one embodiment, the protective layer  102  includes silicon nitride, such as trisilicon tetranitride. The purpose of the protective layer  102  includes acting as a protective layer to prevent the metallization layer from contacting the devices  101 A and  110 B. The semiconductor structure  100  includes a number of contacts  107 . The contacts  107  provide electrical connection to the devices  101 A and  101 B. In one embodiment, the contacts  107  include a diffusion barrier, such as titanium silicide layers  106 A and  106 B, and a plug, such as tungsten layers  107 A and  107 B. 
     The semiconductor structure  100  includes an insulator layer  108 . In one embodiment, the insulator layer  108  includes a substance that comprises a material selected from a group consisting of a polymer, a foamed polymer, a fluorinated polymer, a fluorinated-foamed polymer, an aerogel, and an insulator oxide compound. The polymer includes polyimide. The insulator oxide compound includes silicon dioxide. The semiconductor structure includes a copper seed layer  116  and a copper conductor layer  120 . The copper seed layer  116  and the copper conductor layer  120  constitute a portion of a copper metallization layer  197 . 
     The semiconductor structure  100  includes an inhibiting layer  114 . Without this inhibiting layer  114 , the copper atoms of the copper metallization layer  197  may diffuse into the insulator  108 . This diffusion changes the microstructure of a portion of the semiconductor structure  100  and causes undesired capacitive-resistive effects. The presence of the inhibiting layer  114  inhibits the capacitive-resistive effects. One of the advantages of the inhibiting layer  114  over a liner is that the inhibiting layer  114  scales with the geometry of the semiconductor structure for each succeeding generation of technology. Another advantage of the inhibiting layer  114  over a formation of a barrier from a copper alloy is that the inhibiting layer  114  need not be comprised from a material that is from the copper conductor layer  120 . This leaves the copper conductor layer  120  to be completely occupied by copper so as to enhance the electrical properties of the metallization layer  197  of the semiconductor structure  100 . 
     In one embodiment, the inhibiting layer  114  comprises a compound formed from a reaction that includes the substance in the insulator  108  and a second substance. The second substance is selected from a group consisting of a transition metal, a representative metal, and a metalloid. The transition metal is selected from a group consisting of chromium, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, niobium, and tantalum. The representative metal includes elements from the alkaline earth metal. The representative metal includes aluminum and magnesium. The metalloid includes boron. 
     FIGS. 2A-2F are cross-sectional views of a semiconductor structure during processing according to one embodiment of the present invention. FIG. 2A illustrates a portion of a semiconductor structure  200 , such as an integrated circuit having a number of semiconductor devices, such as devices  201 A and  201 B. The formation of semiconductor devices, such as devices  201 A and  201 B, does not limit the embodiments of the present invention, and as such, will not be presented here in full. The devices  201 A and  201 B include active devices, such as transistors, and passive devices, such as capacitors, or a combination of active and passive devices. 
     The semiconductor structure  200  optionally includes a protective layer  202 . The protective layer  202  is deposited over the substrate  299  and devices  201 A and  201 B. The deposition of the protective layer  202  includes depositing a layer of a substance that protects the devices  201 A and  201 B from subsequent conductive semiconductor layers. In one embodiment, this substance includes a nitride compound, such as silicon nitride. Silicon nitride includes a substance such as trisilicon tetranitride (Si 3 N 4 ). In another embodiment, this layer of silicon nitride is deposited to a thickness in the range of about 100 to about 500 Angstroms. 
     The semiconductor structure  200  includes a first insulator layer  208 . The first insulator layer  208  is deposited over the protective layer  202  although in one embodiment, the first insulator layer  208  may be formed before the formation of the protective layer  202 . In one embodiment, the first insulator layer  208  abuts the protective layer  202  after deposition. In one embodiment, the first insulator layer  208  includes a first substance that is selected from a group consisting of an organic substance and an inorganic substance. 
     In one embodiment, the first substance of the first insulator layer  208  includes an organic substance that includes a material having a plurality of single-hydrocarbon molecules bonded together. In another embodiment, the material comprises at least two mers bonded together that have been treated so as to have a low dielectric constant. In another embodiment, the material is selected from a group consisting of a polymer, a foamed polymer, a fluorinated polymer, and a fluorinated-foamed polymer. Since a polymer includes polyimide, the material can be selected from a group consisting of a polyimide, a foamed polyimide, a fluorinated polyimide, and a fluorinated-foamed polyimide. In another embodiment, the material can be selected from a group consisting of DuPont PI-2801 material, a foamed DuPont PI-2801 material, a fluorinated DuPont PI-2801 material, and a fluorinated-foamed DuPont PI-2801 material. The material may be foamed, for example, as described in U.S. Ser. No. 08/892,114, filed Jul. 14, 1997, (attorney docket number 150.00530101), entitled “Method of Forming Insulating Material for an Integrated Circuit and Integrated Circuits Resulting From Same” which is hereby incorporated by reference. In the embodiment that the material is a polyimide, the first insulator layer  208  is cured after deposition, forming a layer with a thickness of about 5000 Angstroms after curing. The method of curing the first insulator layer  208  does not limit the embodiments of the present invention, and as such, will not be presented here in full. 
     In another embodiment, the first substance of the first insulator layer  208  includes an inorganic substance that includes a material selected from a group consisting of an aerogel and an insulator oxide compound. The insulator oxide compound includes silicon dioxide. 
     The hereinbefore and hereinafter discussions are illustrative of one example of a portion of a fabrication process to be used in conjunction with the various embodiments of the invention. Other methods of fabrication are also included within the scope of the embodiments of the present invention. For clarity purposes, many of the reference numbers are eliminated from subsequent drawings so as to focus on the portion of interest of the semiconductor structure  200 . 
     FIG. 2B shows the semiconductor structure following the next sequence of processing. Vias  205 A and  205 B are opened to devices  201 A and  201 B using a photolithography technique. The term “vias” means the inclusion of contact holes and contact plugs. A suitable photolithography technique:and an etching process can be chosen without limiting the embodiments of the present invention, and as such, it will not be presented here in full. In one embodiment, a first contact material, such as titanium silicide layers  206 A and  206 B, is placed in the vias  205 A and  205 B, through a process such as chemical vapor deposition (CVD). Next, a second contact material, such as tungsten plugs  206 A and  206 B, can be deposited in the vias  205 A and  205 B. The tungsten plugs  206 A and  206 B can be deposited in the vias  205 A and  205 B using any suitable technique such as a CVD process. The excess titanium silicide or tungsten can be removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface. 
     The first insulator layer  208  is patterned to define a number of trenches, such as trench  210 . The term “trench” means the inclusion of lines for electrically interconnecting devices in a semiconductor structure. In one embodiment, the first insulator layer  208  has a first predetermined thickness and the trench  210  has a second predetermined thickness such that the second predetermined thickness of the trench  21   0  is proportional to the first predetermined thickness of the first insulator layer  208 . The trench  210  is located in the first insulator layer  208  so as to open up the semiconductor structure  200  to a number of first level vias, such as vias  205 A and  205 B. In other words, a first level copper metallization layer pattern  210  is defined in a mask layer of photoresist  212 . Then, the first insulator layer  208  is etched, using any suitable process, such as reactive ion etching (RIE), such that the first level copper metallization layer pattern  210  is defined in the first insulator layer  208 . In one embodiment, a residual photoresist layer  212  is left in place on the first insulator layer  108  in a number of regions  213  outside of the number trenches  210 . 
     In one embodiment, the formation of vias  205 A and  205 B and the trench  210  is made using a damascene technique, such as the dual or triple damascene process. The structure is now as it appears in FIG.  2 B. 
     FIG. 2C shows the semiconductor structure following the next sequence of processing. An inhibiting layer  214  is formed in the trench  210 . In one embodiment, the forming of the inhibiting layer  214  includes depositing a second substance using a technique selected from a group consisting of low-energy implantation and chemical-vapor deposition. The second substance is selected from a group consisting of a transition metal, a representative metal, and a metalloid. In addition to depositing the second substance, the forming of the inhibiting layer  214  includes reacting the first substance of the insulator layer  208  and the second substance to form a compound so as to inhibit undesired atomic migration. In one embodiment, the reacting process includes reacting to form an in situ barrier. In another embodiment, the reacting process includes an annealing process. In yet another embodiment, the reacting process is accomplished prior to the completion of the semiconductor structure  200 . 
     In the embodiment that the second substance is a transition metal, the second substance is selected from a group consisting of chromium, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, niobium, and tantalum. In the embodiment that the second substance is a representative metal, the second substance includes an alkaline earth metal. In another embodiment, in which the second substance is a representative metal, the second substance includes aluminum and magnesium. In the embodiment in which the second substance is a metalloid, the second substance includes boron. In the embodiment in which the second substance is either zirconium, aluminum, or an alkaline earth metal, the second substance is deposited with a thickness of about 5 Angstroms to about 40 Angstroms. In the embodiment in which the second substance is an alkaline earth metal, the second substance includes magnesium. 
     In various embodiments, the depositing process of forming the inhibiting layer  214  includes implanting the second substance using a low-energy implantation technique with an implantation energy of about 100 electron-volts to about 2000 electron-volts. In various embodiments, the depositing process of forming the inhibiting layer  214  includes depositing in a temperature of about 250 degrees Celsius to about 375 degrees Celsius. In another embodiment, the temperature includes 325 degrees Celsius. 
     In various embodiments, the second substance is deposited into the surfaces of the trench  210  using a depositing technique where the angle of deposition  211  is varied about 3 degrees to about 15 degrees from normal with respect to the surface of the wafer. In other words, the angle is varied from normal with respect to the planarized surface. In various embodiments, the angle of implantation  211  is dependent on the height-to-width ratio of the semiconductor structure. 
     In one embodiment, the first insulator layer  208  includes the first substance selected from a polyimide or a foamed polyimide, the second substance is selected from zirconium, and the depositing of the second substance is a low-energy  16  implantation technique. Zirconium is implanted using a dose of about 5×10 16  ions per square centimeter. The implantation energy used is about 400 electron-volts to about 600 electron-volts. The angle of implantation  211  varies from about 5 degrees to about 10 degrees from normal with respect to the first insulator layer  208 . In one embodiment, zirconium is deposited with a thickness of about 5 Angstroms to about 40 Angstroms. In another embodiment, zirconium is deposited with a thickness of about 10 Angstroms to about 30 Angstroms. In another embodiment, zirconium is deposited with a thickness of about 20 Angstroms. In this embodiment, the reacting process of forming the compound of the inhibiting layer includes reacting at a temperature of about 325 degrees Celsius to about 375 degrees Celsius. In one embodiment, the time for the reacting process is from about 27 minutes to about 33 minutes. In one embodiment, the duration of the reacting process is 30 minutes. 
     In one embodiment, the first insulator layer  208  includes the first substance being selected from an insulator oxide compound, the second substance being selected from aluminum, and the depositing of the second substance being executed by a low-energy implantation technique. Aluminum is implanted using a dose of about 5×10 16  ions per square centimeter. The implantation energy used is about 400 electron-volts. The angle of implantation  211  varies from about 5 degrees to about 10 degrees from normal with respect to the first insulator layer  208 . In one embodiment, aluminum is deposited with a thickness of about 5 Angstroms to about 40 Angstroms. In another embodiment, aluminum is deposited with a thickness of about 10 Angstroms to about 30 Angstroms. In another embodiment, aluminum is deposited with a thickness of about 20 Angstroms. In this embodiment, the reacting process of forming the compound of the inhibiting layer  214  includes reacting at a temperature of about 325 degrees Celsius to about 375 degrees Celsius. In one embodiment, the duration for the reacting process is from about 27 minutes to about 33 minutes. In one embodiment, the duration of the reacting process is 30 minutes. 
     FIG. 2D shows the semiconductor structure following the next sequence of processing. A first seed layer  216  is deposited on the inhibiting layer  214  using a low-energy ion implantation. In one embodiment, depositing the seed layer  216  on the inhibiting layer  214  includes depositing a copper seed layer  216 . In one embodiment, depositing the seed layer  216  includes depositing copper seed layer  216  having a thickness of about 100 Angstroms. This can be achieved using an 8×10 16  ion implantation of copper. In one embodiment, the energy of implantation includes about 100 electron-volts. Additionally, the copper seed layer  216  is implanted at an angle  215  normal to the planarized surface. Implanting the copper seed layer  216  at an angle normal to the planarized surface would result in the copper seed layer  216  being parallel to a bottom surface  218  in the trench  210 . The copper seed layer  216  is deposited to a much lesser extent on the side surfaces  217  of the trench  210 . 
     FIG. 2E shows the semiconductor structure following the next sequence of processing. Returning briefly to FIG. 2D, the residual photoresist layer  212  has served as a blocking layer to define the implant areas for the inhibiting layer  214 , and the copper seed layer  216 . In one embodiment, the residual photoresist layer  212  is removed using a wet-strip process. In another embodiment, the residual photoresist layer  212  is removed using a tape lift-off technique. In yet another embodiment, the residual photoresist layer  212  is removed using a tape lift-off technique in combination with a wet-strip process. The tape lift-off technique In one embodiment, removing the residual photoresist layer  212  includes removing the unwanted copper seed layer  216 , and the unwanted inhibiting layer  214  from a portion of the surface of the wafer. Such a portion of the surface of the wafer may include a number of regions outside of the trench  210  near the vicinity of the top surface  219 . The semiconductor structure will now appear as shown in FIG.  2 E. 
     FIG. 2F shows the semiconductor structure following the next sequence of processing. The semiconductor structure  200  includes a copper metallization layer  220 . The copper metallization layer  220  is selectively formed on the copper seed layer  216  in the trench  210 . The copper metallization layer  220  includes copper as an element in its composition. In one embodiment, the copper metallization layer  220  is deposited using a selective CVD process. In another embodiment, depositing the metallization layer  220  includes depositing a copper metallization layer  220  using electroplating or electroless plating. 
     In the embodiment in which the second substance is zirconium, the semiconductor structure  200  is heat-treated at about 250 degrees Celsius to about 350 degrees Celsius from about one to about two hours after the electroplating of the copper. 
     The embodiments as described above in FIG. 2A to FIG. 2F may be iterated to form any number of subsequent copper metallization layers in a multi-layer wiring structure. The term “wiring structure” means the inclusion of a contacting and interconnecting structure in an integrated circuit so as to electrically connect various devices together. The term “wiring structure” means the inclusion of at least one copper metallization layer. 
     FIGS. 3A-3C are closed-up cross-sectional views of a semiconductor structure during processing according to one embodiment of the present invention. FIG. 3A shows a closed-up cross-sectional view of a semiconductor structure  300  during processing. Semiconductor structure  300  includes elements that are similar to elements discussed in FIGS. 2A-2F. The discussion of those elements that are similar and have an identical last-two digit nomenclature is incorporated here in full. 
     FIG. 3A includes a trench  310  that is defined by the current shape of protective layer  302 , an insulator  308 , and vias  305 A and  305 B. The insulator  308  includes a first substance. The trench  310  has been defined to begin the formation of a copper metallization layer. In subsequent processing steps, the trench  310  may be filled with copper to complete the formation of a copper metallization layer. As discussed hereinbefore, the formation of a copper metallization layer into the trench  310 , without the various embodiments of the present invention, may cause the undesired diffusion of copper atoms into the insulator  308 . 
     FIG. 3B shows the next sequence of processing. A layer of a second substance is deposited abutting the insulator layer  308  and the vias  305 A and  305 B. The second substance occupies a portion of the trench  310 . 
     FIG. 3C shows the next sequence of processing. An inhibiting layer  314  is formed from the first substance of the insulator  308  and the second substance  398 . This inhibiting layer  314  helps to enhance the copper metallization layer. In one embodiment, because the inhibiting layer  314  forms an integral part of the insulator  308 , the inhibiting layer  314  is effective in inhibiting the diffusion of the copper metallization layer. In another embodiment, because the inhibiting layer  314  forms an integral part of the semiconductor structure  300 , it scales with each succeeding generation of semiconductor processing technology so as to maintain an effective inhibiting layer against the capacitive-resistive effects. In another embodiment, because the inhibiting layer  314  occupies a portion of the space of the insulator  308  but not the space of the trench  310 , more of the space of the trench  31 ; 0  can be used for the deposition of copper. Thus, the metallization layer of the described embodiments is enhanced. 
     FIG. 4 is a block diagram of a device according to one embodiment of the present invention. The memory device  400  includes an array of memory cells  402 , address decoder  404 , row access circuitry  406 , column access circuitry  408 , control circuitry  410 , and input/output circuit  412 . The memory device  400  can be coupled to an external microprocessor  414 , or memory controller for: memory accessing. The memory device  400  receives control signals from the processor  414 , such as WE*, RAS* and CAS* signals. The memory device  400  is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device  400  has been simplified to help focus on the invention. At least one of the memory cells has an inhibiting layer in accordance with the aforementioned embodiments. In one embodiment, at least one of the memory cells has a capacitor and at least one transistor that are interconnected through a semiconductor structure in accordance with the aforementioned embodiments. 
     It will be understood that the above description of a DRAM (Dynamic Random Access Memory) is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a DRAM. Further, the invention is equally applicable to any size and type of memory circuit and is not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM-M (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging memory technologies. 
     As recognized by those skilled in the art, memory devices of the type described herein are generally fabricated as an integrated circuit containing a variety of semiconductor devices. The integrated circuit is supported by a substrate. Integrated circuits are typically repeated multiple times on each substrate. The substrate is further processed to separate the integrated circuits into dies as is well known in the art. 
     FIG. 5 is an elevation view of a semiconductor wafer according to one embodiment of the present invention. In one embodiment, a semiconductor die  510  is produced from a wafer  500 . A die is an individual pattern, typically rectangular, on a substrate that contains circuitry, or integrated circuit devices, to perform a specific  10  function. At least one of the integrated circuit devices includes a memory cell as discussed in the various embodiments heretofore in accordance with the invention. A semiconductor wafer will typically contain a repeated pattern of such dies containing the same functionality. Die  510  may contain circuitry for the inventive memory device, as discussed above. Die  510  may further contain additional circuitry to extend to such complex devices as a monolithic processor with multiple functionality. Die  510  is typically packaged in a protective casing (not shown) with leads extending therefrom (not shown) providing access to the circuitry of the die for unilateral or bilateral communication and control. In one embodiment, at least two of the integrated circuit devices are interconnected through a semiconductor structure as discussed in the aforementioned embodiments. 
     FIG. 6 is a block diagram of a circuit module according to one embodiment of the present invention. Two or more dies  610  may be combined, with or without protective casing, into a circuit module  600  to enhance or extend the functionality of an individual die  610 . Circuit module  600  may be a combination of dies  610  representing a variety of functions, or a combination of dies  610  containing the same functionality. One or more dies  610  of circuit module  600  contain at least one of the semiconductor structure to enhance a copper metallization layer in accordance with the aforementioned embodiments of the present invention. 
     Some examples of a circuit module include memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Circuit module  600  may be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others. Circuit module  600  will have a variety of leads  612  extending therefrom and coupled to the dies  610  providing unilateral or bilateral communication and control. 
     FIG. 7 is a block diagram of a memory module according to one embodiment of the present invention. Memory module  700  contains multiple memory devices  710  contained on support  715 , the number depending upon the desired bus width and the desire for parity. Memory module  700  accepts a command signal from an external controller (not shown) on a command link  720  and provides for data input and data output on data links  730 . The command link  720  and data links  730  are connected to leads  740  extending from the support  715 . Leads  740  are shown for conceptual purposes and are not; limited to the positions as shown. At least one of the memory devices  710  includes a memory cell as discussed in various embodiments in accordance with the invention. 
     FIG. 8 is a block diagram of a system according to one embodiment of the present invention. Electronic system  800  contains one or more circuit modules  802 . Electronic system  800  generally contains a user interface, 804 . User interface  804  provides a user of the electronic system  800  with some form of control or observation of the results of the electronic system  800 . Some examples of user interface  804  include the keyboard, pointing device, monitor, or printer of a personal computer; the tuning dial, display, or speakers of a radio; the ignition switch, gauges, or gas pedal of an automobile; and the card reader, keypad, display, or currency dispenser of an automated teller machine. User interface  804  may further describe access ports provided to electronic system  800 . Access ports are used to connect an electronic system to the more tangible user interface components previously exemplified. One or more of the circuit modules  802  may be a processor providing some form of manipulation, control, or direction of inputs from or outputs to user interface  804 , or of other information either preprogrammed into, or otherwise provided to, electronic system  800 . As will be apparent from the lists of examples previously given, electronic system  800  will often contain certain mechanical components (not shown) in addition to circuit modules  802  and user interface  804 . It will be appreciated that the one or more circuit modules  802  in electronic system  800  can be replaced by a single integrated circuit. Furthermore, electronic system  800  may be a subcomponent of a larger electronic system. At least one of the circuit modules  802  includes at least an integrated circuit that comprises at least two semiconductor devices that are interconnected through a semiconductor structure as discussed in various embodiments in accordance with the invention. 
     FIG. 9 is a block diagram of a system according to one embodiment of the present invention. Memory system  900  contains one or more memory modules  902  and a memory controller  912 . Each memory module  902  includes at least one memory device  910 . Memory controller  912  provides and controls a bidirectional interface between memory system  900  and an external system bus  920 . Memory system  900  accepts a command signal from the external bus  920  and relays it to the one or more memory modules  902  on a command link  930 . Memory system  900  provides for data input and data output between the one or more memory modules  902  and external system bus  920  on data links  940 . At least one of the memory devices  910  includes a memory cell that includes an inhibiting layer as discussed in various embodiments in accordance with the invention. 
     FIG. 10 is a block diagram of a system according to one embodiment of the present invention. Computer system  1000  contains a processor  1010  and a memory system  1002  housed in a computer unit  1005 . The processor  1010  may contain at least two semiconductor devices that are interconnected through a semiconductor structure as described hereintofore. Computer system  1000  is but one example of an electronic system containing another electronic system, e.g., memory system  1002 , as a subcomponent. The memory system  1002  may include a memory cell as discussed in various embodiments of the present invention. Computer system  1000  optionally contains user interface components. These user interface components include a keyboard  1020 , a pointing device  1030 , a monitor  1040 , a printer  1050 , and a bulk storage device  1060 . It will be appreciated that other components are often associated with computer system  1000  such as modems, device driver cards, additional storage devices, etc. It will further be appreciated that the processor  1010  and memory system  1002  of computer system  1000  can be incorporated on a single integrated circuit. Such single-package processing units reduce the communication time between the processor and the memory circuit. 
     CONCLUSION 
     Structures and methods have been described to address situations where a metallization layer acts with an insulator layer such that a capacitive-resistive effect arises. Such an effect is inhibited by the embodiments of the present invention, and at the same time, the metallization layer is enhanced. As described heretofore, the inhibiting layer inhibits diffusion between copper and an insulator layer. Such an inhibition layer is formed without the need to use a copper alloy. 
     Although the specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. Accordingly, the scope of the invention should only be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.