Abstract:
A method and system for simulating in software a digital computer system by performing virtual to physical translations of simulated instructions is disclosed. The number of virtual to physical translations using hash lookups is reduced by analyzing sequences of the instructions for determining with high probability whether the memory accesses made by the instructions perform the same virtual to physical translation in order to reduce the number of necessary hash lookups to enable faster simulation performance.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of a U.S. Provisional Application No. 60/320,283 filed on Jun. 18, 2003. 
     
    
     BACKGROUND OF INVENTION  
       [0002]     Field of the Invention  
         [0003]     The present invention relates generally to software based computer system simulators and, more particularly, to enabling faster simulation performance by analyzing the past behavior of simulated instructions to determine when it is necessary to execute code that is more costly in terms of performance.  
         [0004]     The use of simulation systems for developing computer systems and software has shown to provide tremendous advantages in terms of timesavings and cost. More recently, the technique of full system simulation has gained more attention as advances in processor speeds of contemporary host computer platforms enable good simulation of detailed hardware models in computer system architectures. System simulation provides a virtual computer with the capability to create functional models of CPUs with supporting chips in sufficient detail to execute native object code without modification. Furthermore, simulation provides the significant advantage of enabling developers to develop and test their software applications and hardware products on high-end systems without having to use actual hardware with its associated expense or unavailable hardware still under development.  
         [0005]     Simulation offers benefits for software development where it can arbitrarily parameterize, control, and inspect the computer system it is modeling and provide measurements that are non-intrusive and deterministic. It also provides a basis for automation where multiple simulator sessions can run in parallel and sessions can be fully scripted using performance monitors. For example, the software can be combined with the virtual systems in a way that facilitates modeling of the processor, disk access, memory access, cache configuration, and memory system bus and other parameters. With full system simulation, the operating system, device drivers, and application software cannot tell whether they are running on real hardware or in the simulated environment. Maximum flexibility is obtained using the simulated environment with the ability to change the parameters to suit a particular testing environment while performing comprehensive data collection and execution and performance tracking.  
         [0006]     A critical issue relating to simulation systems is that of performance i.e. a tradeoff must typically be made between the accuracy of simulating the system as closely as possible versus a performance level that is acceptable. Creating a more realistic simulation workload environment generally comes at the expense of time and cost to deal with specification inaccuracies and implementation errors. One area that has a significant affect on performance relates to memory accesses. Memory accesses are operations that are typically performed very frequently thus any improvement in access times can significantly improve simulation performance. By way of example, when simulating an instruction set of a modern processor, simulation of memory accesses is a key component of the simulator efficiency, since memory accesses are generally very frequent operations that e.g. can consist of somewhere between one fifth to one third of all operations. The simulated processor has a memory management unit (MMU) which checks that the addresses may be accessed and translates the virtual memory addresses to physical memory addresses. For every memory access, this check and translation is performed, which when normally done in hardware has an insignificant affect on performance but greatly affects the simulation performance.  
         [0007]     Modern processors often employ virtual memory page based translation. In some cases, other mechanisms such as segmentation are used in addition to paging. A page is a fixed size, aligned address range with a specific translation from virtual to physical address. The page is also used to specify the access rights i.e. if the addresses can be read, written or executed. Thus a page is the smallest address range which can have a specified virtual to physical address translation and can have a specified access protection. Some architectures allow so-called large pages, i.e. pages of different sizes where the larger page size is an even multiple of the smaller page sizes.  
         [0008]     Conventional simulators have either used the hardware support from the host or a pure software algorithm to perform the virtual to physical address translation. When doing it in software, a hash lookup is typically performed first. The hash lookup typically requires many simulated instructions thereby affecting performance if done too frequently. If the lookup hits, which is the common fast case, the access is guaranteed not to violate any access restrictions and the lookup table returns the address where simulated memory is stored. If the lookup misses, a slow path is used that can handle all the uncommon cases that can happen to a memory access, such as a TLB miss, access violation, and miss alignment. A description of such a lookup algorithm can be found in REF1 i.e. the article “Efficient Memory Simulation in SimICS” by P. S. Magnusson and B. Werner, in Proceedings of the 28th Annual Simulation Symposium, 1995, However, even if the lookup hits it is costly in terms of performance cost to perform it for every memory access.  
         [0009]     A simulator running as a user process on a conventional OS cannot use hardware support to perform translations. To this the process must be given OS privileges or the OS must be modified to allow the simulator more control of the host hardware. Typically, the simulator wants to control the host translation look-aside buffer (TLB) and/or the segmentation hardware to support the simulated translations.  
         [0010]     In view of the foregoing, it is desirable to provide a commercial quality level simulation platform that offers improved simulator performance in order to more accurately model workloads by running unmodified code in realistic configurations.  
       SUMMARY OF INVENTION  
       [0011]     Briefly described and in accordance with embodiments and related features of the invention, there is provided a method and system for simulating in software a digital computer system by performing virtual to physical translations of simulated instructions is disclosed. The number of virtual to physical translations using hash lookups is reduced by analyzing sequences of the instructions for determining with high probability whether the memory accesses made by the instructions perform the same virtual to physical translation in order to reduce the number of necessary hash lookups to enable faster simulation performance.  
         [0012]     In accordance with an embodiment of the invention, several memory accesses within a super block are known to access the same address thus a translation is performed for the first memory access and the following memory accesses use the same translation.  
         [0013]     In accordance with another embodiment, several memory accesses within a super block access the same page with high probability therefore a translation is performed for the first memory access and the following accesses do not need to perform the hash lookup but instead is checked to verify that the lookup matched with the translation of the first memory access, if there is a match the access can proceed using the translated address saved from the first lookup, otherwise a complete hash lookup is performed.  
         [0014]     In accordance with still another embodiment, one or more memory accesses within a loop are known to access only within the same page for some number of iterations of the loop. The instructions within the loop are analyzed such that, for each memory access, the number of iterations performed in the loop without accessing another page is calculated such that the virtual to physical translation is performed, the calculated number of iterations is run using the translated address in the loop.  
         [0015]     In accordance with still another embodiment, for a memory access that is executed multiple times, the translation is performed the first time the memory access is performed and saved in a table or cached in memory such that subsequent memory accesses can attempt to match the lookup.  
         [0016]     In accordance with another aspect of the invention, a computer program product capable of being run on a host system for simulating in software a physical digital computer system, comprising a computer readable storage medium having a computer readable program code means embedded in said medium. The computer readable program code means comprises computer instruction means for performing virtual to physical translations of simulated instructions whereby faster simulation performance is obtained by reducing the number of necessary virtual to physical translations using hash lookups for the simulated instructions. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0017]     The invention, together with further objectives and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:  
         [0018]      FIG. 1  illustrates steps relating to case i) in accordance with an embodiment of the invention;  
         [0019]      FIG. 2  illustrates steps relating to case ii) in accordance with an embodiment of the invention;  
         [0020]      FIG. 3  illustrates steps relating to case iii) in accordance with an embodiment of the invention; and  
         [0021]      FIG. 4  illustrates steps relating to case iv) in accordance with an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0022]     In accordance with an embodiment of the invention, simulation performance is improved by reducing the number of virtual to physical translations and to reduce the cost of the remaining translations without the need for OS privileged hardware support. In other words, the number of simulated hardware checks with memory accesses is reduced by skipping the check if a previous access to the same page in memory was performed earlier. Furthermore, the hash lookup will be used fewer times and some of the remaining hash lookups can be simplified, thereby resulting in a faster simulator. In accordance with the embodiment, the invention operates by analyzing sequences of instructions and utilizing two common properties of the memory accesses made by the instructions. The first property is that given a sequence of executed instructions, accesses made from different memory access instructions often perform the same virtual to physical translation. The second property is that if the same instruction is executed multiple times it often performs a memory access to the same page. These properties are related to spatial and temporal locality but in this case it is desirable to have locality between accesses made from a particular sequence of instructions.  
         [0023]     An analysis to check for valid memory accesses is made when the instructions are being simulated. A mechanism must be applied to make sure a performance costly analysis is not performed on all lines of executed code, but only the frequently executed parts. Statistics, on the other hand, have a low overhead and can be collected on all executed code. This is generally done by incrementing a counter each time a code jump is performed. In accordance with the embodiment, an analysis is only applied when a counter reaches a particular threshold value thereby regulating the number of analyses performed. The analysis check is typically performed for memory accesses that use the same translation or for accesses that have a high probability of using the same translation.  
         [0024]     The following definitions are used herein in describing the invention.  
         [0025]     A BASIC BLOCK is sequence of instructions that are always executed in sequence, i.e. there are only jumps to the first instruction and from the last instruction in the basic block.  
         [0026]     A SUPER BLOCK is a sequence of instructions with only one entry point, but multiple exit points, i.e there are only jumps to the first instruction in the block, but the may be conditional jumps out of the block from any instruction in the block.  
         [0027]     The fact that sequences of memory accesses often do the same virtual to physical translation is used in several ways: 
    i) Several memory accesses within a super block are known to access the same address.     ii) Several memory accesses within a super block access the same page with a high probability.     iii) One or more memory accesses within a loop are known to access only within the same page for some number of iterations of the loop.     iv) A memory access which is executed multiple times has a high probability of accessing the same page.    
 
         [0032]      FIG. 1  illustrates steps relating to case i) in accordance with an embodiment of the invention. In case i) the translation need only be done once, for the first memory access. The following memory accesses can use the same translation.  
         [0033]      FIG. 2  illustrates steps relating to case ii) in accordance with an embodiment of the invention. In case ii) the translation is done for the first memory access. The following accesses need not do the hash lookup to find the entry to compare to. They just have to do the match to check that the lookup matched. If there is a match the access can proceed using the translation saved from the first lookup. In the unlikely event of a mismatch the complete hash lookup is done.  
         [0034]      FIG. 3  illustrates steps relating to case iii) in accordance with an embodiment of the invention. In case iii) the instructions within the loop need to be analyzed. For each memory access you calculate the minimum number of iterations you can do in the loop without accessing another page. Then you do the virtual to physical translation, run that number of iterations using the translated address in the loop.  
         [0035]      FIG. 4  illustrates steps relating to case iv) in accordance with an embodiment of the invention. In case iv) the translation is done the first time the memory access is executed. The translation is cached so that subsequent memory accesses can try to match the lookup.  
         [0036]     In another embodiment of the invention, a correlation can be determined for several instructions and used advantageously to predict whether a later instruction will accesses the same page. By way of example, a later executed instruction can be assumed to reside on the same page as a previous correlated instruction, which allows for further elimination of simulated accesses and optimization of the simulation software. The correlations can be derived from OLE_LINK1heuristic algorithms OLE_LINK1based past executions of instructions.  
         [0037]     The techniques can be generalized and be applied also to sequences of super blocks, nested loops and other control flow structures to decrease the number of virtual translations further.  
         [0038]     The following examples are shown using the SPARC V9 instructions set architecture described in SPARC V9 architecture manual.  
         [0039]     By way of example, there is shown a simulation of the following instructions which increment a value in memory:  
                                   Instruction   Comments                   1. ldx [%g1], %g2   ;load register g2 with a value from address           pointed to by register g1       2. add %g2, 1, %g2   ;add 1 to register g2       3. stx %g2, [%g1]   ;store back the incremented value to the same           address in memory                  
 
         [0040]     The pseudo code that is needed to simulate the three instructions above would look something like: 
    1a. Code to simulate the read of the value in register g1 (which is the address we will load from).     1b. Code to do the hash lookup (see below).     1c. Code which uses the pointer supplied by the hash lookup to load the value 1d. Code to simulate the write to register g2.     2a. Code to simulate the read of the value in register g2.     2b. Code to add 1 to the value.     2c. Code to simulate the write of the new value to register g2.     3a. Code to simulate the read of the value in register g1 (which is the address we will store to).     3b. Code to do the hash lookup (see below).     3c. Code to simulate the read of the value in register g2.     3d. Code which uses the pointer supplied by the hash lookup to store the value.    
 
         [0051]     The code that makes the hash lookup for the load and the store instructions follows. Names starting with a lower case r are all registers that should be mapped to real registers. Here we use the more descriptive names for clarity. Words with only upper case letters are constants that are actually numbers. Again we use more descriptive names. rData is a register that points to a data section in the simulator program from where we can get the address of the hash table. The register rAddr holds the virtual address that we want to lookup.  
         [0052]     The hash lookup code comprises, in the example below, of a relatively lengthy of nine lines of code. Note that this code differs slightly from the hash table lookup code described in REF1 because that code was aimed at simulating a SPARC V8 architecture whereas this sample code is indented to simulate a SPARC V9 architecture. For instance the Idd instruction cannot be used to load two 64 bits values from memory to two consecutive registers.  
                                   Instruction   Comments                   ldx rHashBase, [rData + HASH_TABLE]   ;Get the address of the hash table.       srlx rAddr, HASH_PAGE_SHIFT, rlndex   ;Calculate an index (or offset) to the tag in the       and rlndex, HASH_INDEX_MASK, rlndex   ;hash table for the address.       ldx [rHashBase + rlndex], rTag   ;Load the tag.       add rlndex, TAG_SIZE, rlndex   ;The magic offset is stored TAG_SIZE bytes af-           ter       ldx [rHashBase + rlndex], rOffset   ;the tag in the hash table. Load the magic offset.       andn rAddr, HASH_CHECK_MASK, rPageAddr   ;Check that the tag corresponds       cmp rPageAddr, rTag   ;to the address.       add rAddr, rOffset, rRealAddress;   ;Calculate the real address (simulated physical           address) to do the actual load/store from/to       bne hash_miss   ;If not a match we jump to code for a real MMU           lookup.                  
 
         [0053]     It should be noted that the from/to addition could be performed as part of the address generation in a SPARC load/store instruction that does the actual load to/store from simulated memory. The addition has been added in the description for exemplary purposes and improved clarity.  
         [0054]     The invention in case (i) is to analyze the instructions and detect that the register g1 in this case will never change between the load and the store. In this case we know that the code will access the same page and we can thus reuse the rRealAddress pointer for the second memory access. In more general terms, the invention is to use code that analyzes a block of instructions and figures out which instructions uses (accesses) the same page. Simulation code can than be created that only makes a full lookup for the first time a page is accesses within the block. A block may be arbitrary big.  
         [0055]     The invention in case (ii) is to analyze a block of instructions and detect memory accesses that with a high degree of probability will access the same page, as shown in the following example:  
                                   Instruction   Comments                   1. ldx [%g1 + 16], %g2   ;load register g2 with a value from address g1 +           16.       2. add %g2, 1, %g2   ;add 1 to register g2       3. stx %g2, [%g1 + 24]   ;store back the incremented value to address           g1 + 24.                  
 
         [0056]     It is very likely that the address g1+16 and g1+24 will access the same page but this cannot be known with certainty since a page boundary could be located on address g1+24, for example. In this case we use code for the second memory access that looks like this:  
                                   Instruction   Comments                   and rAddr,   ;Check that the tag corresponds       HASH_CHECK_MASK, rPageAddr       cmp rPageAddr, rTag   ;to the address.       add rAddr, rOffset, rRealAddress   ;Calculate the real address           (simulated physical           address); to do the           actual load/store from/to       bne hash_miss   ;If not a match we jump to           code for a full hash           lookup (the addresses was           on different pages).                  
 
         [0057]     In this example, both the rTag and the rOffset are saved from the first hash lookup in the block. rAddr is the address that cannot be trusted completely to access the same page.  
         [0058]      FIG. 2  shows an exemplary flow diagram of an algorithm of case (ii) for checking whether the virtual address is accessible i.e. whether it is necessary to get a translation to the physical address for the virtual address. In the first step, a hash lookup is performed in a table for the first memory access to determine whether the virtual address is present. If there is a match i.e. address is in the table, then access to the address is permitted to the page in memory and can be performed. The translation is then saved for the second access that can be reused with a high level of probability. This is confirmed with a check that has a lower performance cost of three lines thus saving the execution of six lines of code. Thus the relatively long hash lookup of nine instructions is forgone at this point.  
         [0059]     The analyzer code for case (ii) can also use a statistical measure such as heuristics to find memory accesses that goes to the same page. For instance if e.g. the last 100 (or a more tuned number) accesses of two memory instructions uses the same page it is very likely that they will do so in the future as well.  
         [0060]     The invention in case (iii) is to use code that analyzes a loop and figures out which accesses in the loop that goes to the same page or are likely to go to the same page. Then either the lookup code in case (i) or in case (ii) can be used. If the loop instead is unrolled then case (i) or (ii) can be used directly on the resulting code.  
         [0061]     The invention in case (iv) is to use temporal locality instead of spatial locality as in case i, ii, and iii. The observation here is that some instructions will often access the same page every time they are executed. For instance when global variables are accessed. Here the analyzer code can use statistical measurements as in case (ii) to identify suitable instructions. The first time such instruction is executed it performs a full hash lookup but saves the values of the tag and offset for future invocations which uses the minimal lookup as in case (ii). This case has the advantage of not depending on an earlier instruction in the block that saves the tag/offset pair. It has its own copy. This case can also be used in combination with case (iii).  
         [0062]     The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed, since many modifications or variations thereof are possible in light of the above teaching. Accordingly, it is to be understood that such modifications and variations are believed to fall within the scope of the invention. It is therefore the intention that the following claims not be given a restrictive interpretation but should be viewed to encompass variations and modifications that are derived from the inventive subject matter disclosed.