Abstract:
A power supply which inputs a first direct-current voltage from the outside and outputs a high direct-current voltage to a plasma display panel. The power supply connects the input direct-current voltage to a positive polarity side of a first capacitor of a plurality of N capacitors connected in series to each other and connects a negative polarity side of the first capacitor to a ground (step 1); connects the input direct-current voltage to a positive polarity side of an Mth capacitor of the N capacitors and connects a negative polarity side of the Mth capacitor to the ground (step 2); repeats step 2 for M=2 to N (step 3); and outputs a voltage of the positive polarity side of the first capacitor to the plasma display panel (step 4).

Description:
This application is a continuation of prior application Ser. No. 08/624,775 filed on Mar. 27, 1996, now abandoned which is a continuation of parent application Ser. No. 08/181,536 filed on Jan. 14, 1194 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a power supplying apparatus used for a plasma display unit, and more particularly to a power supplying apparatus used for a color-type plasma display panel. 
     A plasma display unit displays an image on a plasma display panel by utilizing a phenomenon that an electrical discharge in a inert gas causes a luminescence. The plasma display unit is widely used as a display board for notification and advertisement and as a display panel for a portable computer, for example, because it can realize quite a large screen size considering that it is a plane type and it can display images on the screen at high density. A color-type plasma display unit usually uses a surface discharge-type panel. However, a power unit for supplying power to the surface-discharge type panel tends to be large-sized and expensive, and so does the color-type plasma display unit, because the panel requires a plurality of power-supply voltages. 
     As use of a plasma display unit has become widespread in recent years, demand for a plasma display unit which is small-sized and economical has increased. To meet this demand, a power unit for a color-type plasma display panel of the plasma display unit, which is also small-sized, energy-efficient and low-priced is also increasing. 
     2. Description of the Related Art 
     FIG. 1 shows a configuration of a plasma display panel. FIG. 2 illustrates a configuration of electrodes of a plasma display panel. 
     A color-type plasma display unit usually uses a surface discharge-type panel (hereinafter simply called a display panel). As shown in FIG. 1, between a front glass substrate and a rear glass substrate, the surface discharge-type display panel places fluorescent materials which emit light when excited by ultraviolet rays, various types of electrodes, partitions, a dielectric layer and a protection layer. Display electrodes and data electrodes are provided on the front glass substrate and the rear glass substrate, respectively. The display electrodes are comprised of discharge sustaining electrodes (e.g., X1, X2-X7 in FIG. 2, hereinafter simply called sustaining electrodes) and discharge scanning electrodes (e.g., Y1, Y2-Y7, hereinafter simply called scanning electrodes). 
     As the scanning electrodes are scanned (i.e., a voltage is applied sequentially to each of the scanning electrodes) with a voltage applied to the sustaining electrodes, lines on the display screen are selected one by one. Three data electrodes (e.g., A1, A2 and A3 in FIG. 2) correspond to three primary colors of light, i.e., red (R), green (G) and blue (B). Thus, three points (R, G, B) where the 3 data electrodes intersect the line which is selected by the sustaining electrodes and the scanning electrodes, compose a picture element (hereinafter called pixel) on the display screen. 
     Based on data to be displayed on the panel, a voltage Va (approx. 50 volts) required for starting a discharge is applied to the data electrodes and a voltage Vs (approx. 180 volts) required for maintaining the discharge is applied to the sustaining electrodes and scanning electrodes. A high voltage Vd (approx. 330 volts) is applied to the sustaining electrodes to start a discharge over the entire surface of the display panel (hereinafter this discharge operation is called entire-surface discharge). Accordingly, the display panel requires a data-selection voltage Va (approx. 50 volts) and an entire-surface-discharge-starting voltage Vd (approx. 330 volts) in addition to a discharge-sustaining voltage Vs (approx. 180 volts). 
     FIG. 3 is a circuit diagram of a power unit of the related art. Parts (a) and (b) of FIG. 3 show portions of the power unit for generating the voltage Vd and the voltage Va, respectively. 
     FIG. 3 part (b) shows a known switching regulator circuit using a pulse-width modulation (PWM) control integrated circuit (abbreviated to PWM-control IC). The switching regulator circuit turns on and off a transistor T9 with the PWM-control IC to pulse-width modulate a power supply voltage Vs (approx. 180 volts) input thereto. The circuit then rectifies and smooths the pulse voltage output from the transistor T9 with a choke coil L and a capacitor C to output a voltage Va (approx. 50 volts). 
     In FIG. 3 part (a), when a transistor T8 is turned on by a PWM-control IC, electric energy is accumulated in the a choke coil L. When the transistor T8 is turned off, the electric energy accumulated in the choke coil L is released and added to the power supply voltage Vs, generating the high voltage Vd (approx. 330 volts). 
     As described above, the power unit of the related art uses two separate and similar switching regulator circuits including the PWM-control ICs and choke coils L, to generate the voltages Vd and Va required for controlling the display panel. 
     Therefore, it is a problem of the power unit of the related art that the power unit, i.e., the plasma display unit is large-sized, expensive and power-consuming since it uses electronic parts such as PWM-control ICs and choke coils. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a small-sized and economical power unit used for a color-type plasma display panel. 
     To achieve the above and other objects, the present invention provides a voltage-booster circuit in a power supplying apparatus for a plasma display panel. 
     In a power supplying apparatus which inputs a first direct-current voltage from an external power supply and outputs a second direct-current voltage to a plasma display panel, the voltage-booster circuit converts a direct-current voltage input thereto directly into a higher direct-current voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a configuration of a plasma display panel; 
     FIG. 2 illustrates a configuration of electrodes of a plasma display panel; 
     FIG. 3 is a circuit diagram of a power unit of the related art; 
     FIG. 4 is a block diagram illustrating a plasma display unit for practicing the present invention; 
     FIG. 5 is a timing chart illustrating control of a display panel; 
     FIG. 6 is a circuit diagram of a power unit of the present invention; 
     FIG. 7 is a timing chart illustrating an operation of a voltage-booster circuit of the present invention; 
     FIG. 8 is a circuit diagram of a gate control circuit 21 of the present invention; 
     FIG. 9 is a timing chart illustrating an operation of the gate control circuit 21; and 
     FIG. 10 is a circuit diagram of a voltage-adder circuit of the present invention. 
     Throughout the above-mentioned drawings, identical reference numerals are used to designate the same or similar component parts. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 is a block diagram illustrating a plasma display unit for practicing the present invention. 
     Unlike the power unit of the related art which uses a switching regulator to generate the entire-surface discharge-starting voltage Vd (approx. 330 volts), the present invention generates a voltage Vw (approx. 150 volts) first with a voltage-booster circuit and then adds the voltage Vw to the voltage Vs (approx. 180 volts) with a voltage-adder circuit 4b (see FIG. 10), thus generating the voltage Vd. 
     A display panel 1a, which is constructed as shown in FIGS. 1 and 2, has 480 pixels wide×640 pixels long, for example, each pixel having three display cells which correspond to three primary colors (R, G, B) of light. 
     A display controller 2a controls the display panel 1a based upon control signals input from an external device (not shown). The display controller 2a inputs display data including R, G and B signals for each pixel and stores the display data sequentially into a frame memory 3a via a pair of input-output (abbreviated to I/O) buffers 5a. The R, G and B signals each consist of a plurality of bits to express a pixel of an image in a plurality of scales. The display controller 2a also generates timing signals for controlling the plasma display panel 1a based upon a clock signal (CLOCK), blanking signal (BLANK), horizontal synchronizing signal (HSYNC) and vertical synchronizing signal (VSYNC), which are input from the external device, and sends the timing signals to circuit blocks of the display unit. 
     A power supply 4a, to which the present invention relates, is supplied with the power supply voltage Vs from the external device, generates the voltages Vw and Va required for controlling the display panel 1a, and supplies the voltages to a drive circuit 10. 
     The frame memory 3a, which is a bit-map memory composed of dynamic random access memory (DRAM), stores the display data input from the external device via the display controller 2a. The frame memory 3a stores display data consisting of R, G and B signals for each pixel, each of which signals include a plurality of bits to express a pixel of an image in a plurality of scales. 
     The input-output (abbreviated to I/O) buffers 5a temporarily store the display data read from the frame memory 3a and output the data to corresponding address drivers 9a to display the display data on the display panel 1a. 
     A sustaining-pulse generator circuit 6a is supplied with the power-supply voltages Vw and Vs, generates pulses having a waveform as shown in &#34;Sustaining-electrode voltage&#34; in FIG. 5 and supplies the pulses to the sustaining electrodes. At the entire-surface discharge cycle, the sustaining-pulse generator circuit 6a adds the voltage Vw to the voltage Vs (see FIG. 10) and supplies the added voltage (approx. 330 volts) to the sustaining electrodes. 
     A scanning-pulse generator circuit 7a is supplied with the power-supply voltage Vs, generates a pulse having a waveform of amplitude Vs as shown in &#34;Scanning-electrode voltage&#34; in FIG. 5 and supplies the pulse to a scanning driver circuit 8a. 
     The scanning driver circuit 8a, which is supplied with the above-mentioned pulse from the scanning-pulse generator circuit 7a and the power-supply voltage Va from the power unit 4a, generates pulses having a waveform as shown in &#34;Scanning-electrode voltage&#34; in FIG. 5 and supplies the pulses to the scanning electrodes. 
     The address driver circuits 9a, based upon the display data input from the corresponding I/O buffers, generate pulses having a waveform of amplitude Vs as shown in &#34;Data-electrode voltage&#34; in FIG. 5 and supplies the pulses to the data electrodes. 
     FIG. 5 is a timing chart illustrating control of a display panel. 
     An image is displayed on the display panel 1a by sequentially executing an entire-surface discharge, erasing discharge and data display cycles for each frame of an image (hereinafter simply called frame). 
     Prior to displaying a frame, the entire-surface discharge cycle is executed. In the cycle, the voltage Vw (approx. 150 volts) is added to the discharge-maintaining voltage Vs (approx. 180 volts) to generate a high voltage Vd (approx. 330 volts). The high voltage Vd is applied to the sustaining electrodes, which are provided in common to all the lines of the display screen, to cause a discharge over the entire surface of the display panel. When the entire-surface discharge is caused, wall charge is formed on the sustaining electrode side. 
     In the erasing discharge cycle, the entire-surface discharge is halted and the wall charge is left on the sustaining electrode side to facilitate a discharge just by applying a low voltage to the data electrodes in the data display cycle that follows. That is, after the high voltage Vd is applied to the sustaining electrodes in the entire-surface discharge cycle, a ground (GND) is applied to the sustaining electrodes for a short period and the voltage Vs is applied to the scanning electrodes in the erasing discharge cycle. Thus, in the erasing discharge cycle, a reverse electric field is provided between the sustaining and scanning electrodes, halting the discharge and leaving wall charge on the sustaining electrode side. 
     In the data display cycle, when a GND is applied sequentially to the scanning electrodes, lines are scanned and selected one after another and when the data electrodes are driven according to display data to be displayed on the line, the display cells on the selected line are caused to discharge and display the display data. Driving the data electrodes is conducted by reading the display data for each display cell from the I/O buffers 5a and, depending on the display data bit being logical 1 or 0, by applying the voltage Va or GND to the data electrodes which correspond to the display cell, thus causing the display cell to discharge or not to discharge. 
     FIG. 6 is a circuit diagram of a power unit of the present invention. The above-mentioned power unit 4a (see FIG. 4) includes a voltage regulator 3b and a voltage-booster circuit 2b. 
     The voltage regulator 3b inputs a power supply voltage Vs and outputs a stabilized voltage Va. The voltage regulator 3b turns on and off a transistor T0 with a pulse-width modulation (PWM)-control integrated circuit (abbreviated to PWM-control IC) and rectifies and smooths the pulse voltage output from the transistor T0 with a stabilizer circuit 32 to output the voltage Va. 
     The PWM-control IC 30 is a known circuit (e.g., Fujitsu-made MB3775), which compares the voltage Va output from the stabilizer circuit 32 with a reference voltage generated within the PWM-control IC 30 and, based on an error, controls a period in which the transistor T0 is turned on. When the output voltage Va is higher than the reference voltage, the PWM-control IC 30 shortens the period to lower the output voltage Va; otherwise, lengthens the period to raise the output voltage Va, thus regulating the power supply voltage Va despite variations in load. 
     A voltage converter circuit 31 converts the output voltage of PWM-control IC 30 into a voltage for driving the gate (G) of the transistor T0. 
     When the transistor T0 of the stabilizer circuit 32 is turned on, a current flows through the transistor T0, a choke coil L and a load (not shown), and electric energy is accumulated in the choke coil L. When the transistor T0 is turned off, the energy accumulated in the coil L is released as a current through the load and a diode D3. The above operation is repeated in the period in which the transistor T0 is turned on and off, and steady and smooth direct-current voltage Va (approx. 50 volts) is via a capacitor C4. 
     The voltage-booster circuit 2b is comprised of capacitors C1, C2 and C3, p-channel field-effect transistors (FET) T1 and T2, n-channel field-effect transistors T3 and T4, reverse-current preventing diodes D1 and D2 and a gate control circuit 21. The voltage-booster circuit 2b is supplied with the voltage Va from the voltage regulator 3b and increases the voltage Va three times, i.e., steps up to a voltage Vw (approx. 150 volts). 
     The gate control circuit 21 turns on and off transistors T1-T4 by providing their gates (G) with signals G1-G4 as shown in FIG. 9 to control the voltage-booster circuit 2b. Thus, the voltage-booster circuit 2b sequentially increases or steps up the input voltage Va as shown in FIG. 7, which is a timing chart illustrating an operation of a voltage-booster circuit of the present invention. 
     (1) First, in an initial state with the transistors T1-T4 turned off, the gate control circuit 21 turns on the transistor T4 only. Then, a current flows from the power supply Va (i.e., the output of the voltage regulator 3b) to the GND through the capacitor C1 and transistor T4, while charging the capacitors C1 and C3 and providing a voltage Va to their positive polarity sides. 
     (2) Next, the gate control circuit 21 turns off the transistor T4 and turns on the transistors T1 and T3 with the transistor T2 left turned off. Then, a current flows from the power supply Va to the GND through the transistor T1, capacitor C2 and transistor T3, while charging the capacitor C2 and providing a voltage Va to its positive polarity side. Thus, the positive polarity sides of the capacitors C1 and C3 are raised by another voltage Va, eventually to a potential of voltage 2Va. 
     (3) Finally, the gate control circuit 21 turns off the transistor T3 and turns on the transistor T2, i.e., turns on the transistors T1 and T2. Then, the potential of the negative polarity side of the capacitor C2 is raised to the voltage Va and therefore, the potential of both capacitors C1 and C2 is further raised by the voltage Va, eventually raising the potential Vw of the positive polarity sides of capacitors C1 and C3 to 3 Va (50 volts×3=150 volts). 
     FIG. 8 is a circuit diagram of a gate control circuit 21 of the present invention. FIG. 9 is a timing chart illustrating an operation of the gate control circuit 21. 
     Flip-flops FF1 and FF2 constitute a counter and count up an incoming clock (CLK) signal when a clear (CLR) signal is high. The CLR signal goes high when voltage-boosting is required for entire-surface discharge, and stays low unless required including when power-on reset is performed. The flip-flop outputs, their negations through inverters (represented by I in FIG. 8) and a blocking (BL) signal are input to NAND gates (represented by A) to decode the count and thereby to generate the G1-G4 signals. The BL signal prevents undesired combinations of the transistors T1-T4 turning on which may occur at a transition of switching. The inverters connected to the NAND-gate outputs provide the G1-G4 signals with a low or high level according to the corresponding transistors T1-T4 being p- or n-channel FET, in order to turn them on. 
     FIG. 10 is a circuit diagram of a voltage-adder circuit of the present invention. 
     A voltage-adder circuit 4b, which is provided in the sustaining-pulse generator circuit 6a (see FIG. 4), is comprised of a transistor T5 (p-channel FET), a transistor T6 (n-channel FET), a capacitor C5, a reverse-current-preventing diode D4, and a gate control circuit 22. The voltage-adder circuit 4b is supplied with the voltages Vs (approx. 180 volts) and Vw (approx. 150 volts) from the voltage regulator 3b and voltage-booster circuit 2b (see FIG. 6), respectively, adds the voltage Vw to the voltage Vs to generate a high voltage Vd of approx. 330 volts and supplies the high voltage Vd to the sustaining electrodes at the entire-surface discharge cycle. 
     The gate control circuit 22 turns on and off the transistors T5 and T6 by controlling their gates (G) to add the voltage Vw to the voltage Vs at the entire-surface discharge cycle. In the data display cycle, the gate control circuit 22 turns off the transistor T5 and turns on the transistor T6 by applying a high level to both of their gates (G), thus providing a ground level (GND) to the negative polarity side of the capacitor C5. Therefore, the capacitor C5 is charged to the voltage Vs and the voltage Vs is output from a terminal TM. 
     In the entire-surface discharge cycle, the gate control circuit 22 turns on the transistor T5 and turns off the transistor T6 by applying a low level to both of their gates (G), thus providing the voltage Vw to the negative polarity side of the capacitor C5. Therefore, the positive polarity side of capacitor C5 is raised by a voltage Vw and thus, a voltage Vs+Vw, i.e., the voltage Vd is output from the terminal TM. 
     As described above, prior to displaying a frame, a high voltage Vd of approx. 330 volts is supplied to the sustaining-electrodes to start an entire-surface discharge. The high voltage Vd is generated first by boosting the voltage Va to the voltage Vw and then by adding the voltage Vs to the voltage Vw. Assuming that 60 frames are displayed per second, the high voltage Vd, i.e. the voltage Vw need be generated only once per 16.7 milliseconds and only for a period of 10-20 micro-seconds. Accordingly, the voltage-booster circuit 2b and voltage-adder circuit 4b can be composed of a smaller amount of electronic parts including transistors, logical elements and capacitors of small capacitance which are smaller-sized and more economical, compared with such electronic parts as a PWM-control IC and choke coil used in the related art. Thus, the present invention can realize a power unit for a plasma display panel, and therefore a plasma display unit which is small-sized and economical.