Abstract:
A method of making a semiconductor package substrate includes laser-ablating channels in the substrate. After the channels are ablated in the substrate, conductive material is added to fill the channels and cover the surface of the substrate. Then a photomask etching process simultaneously forms a circuit pattern above the surface of the substrate and removes excess metal above the channels, by removing metal above the surface only in patterned regions. The result is a two-level circuit pattern having conductors within and above the substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 11/045,402, filed on Jan. 28, 2005, which is a continuation in part of U.S. patent application Ser. No. 10/138,225 filed May 1, 2002, now U.S. Pat. No. 6,930,256, issued Aug. 16, 2005, having at least one common inventor and assigned to the same assignee. The specification of the above-referenced patent is herein incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor packaging, and more specifically, to a substrate having a printed circuit layer above laser-embedded conductive patterns for providing electrical inter-connection within an integrated circuit package. 
     BACKGROUND OF THE INVENTION 
     Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including “flip-chip”, ball grid array and leaded grid array among other mounting configurations. These configurations typically use a planar printed circuit etched on the substrate with bonding pads and the connections to the die are made by either wire bonding or direct solder connection to the die. 
     The resolution of the printed circuit is often the limiting factor controlling interconnect density. Photo-etch and other processes for developing a printed circuit on a substrate have resolution limitations and associated cost limitations that set the level of interconnect density at a level that is less than desirable for interfacing to present integrated circuit dies that may have hundreds of external connections. 
     As the density of circuit traces interfacing an integrated circuit die are increased, the inter-conductor spacing must typically be decreased. However, reducing inter-conductor spacing has a disadvantage that migration and shorting may occur more frequently, thus setting another practical limit on the interconnect density. 
     The above-incorporated parent patent application discloses techniques for embedding circuit patterns within a substrate for providing such high-density interconnection. One penalty that is paid for fully-embedded circuits such as those disclosed therein, is that large circuit areas require more laser-ablate time at the same line width and more careful control of the laser when producing large areas via multiple scans. Embedded terminals also sometimes must be plated up to provide a particular thickness above the substrate especially when the terminal is to project into a solder mask layer applied above the embedded circuits. It would be desirable to provide a method and substrate having further improved interconnect density with a low associated manufacturing cost, and further having easily generated large features above the surface of the substrate without requiring ablation of large areas or a second plate-up process. 
     SUMMARY OF THE INVENTION 
     A substrate including a printed circuit layer having levels atop and within a dielectric and a method for manufacturing a substrate provide increased circuit density and design flexibility for semiconductor packaging. A surface of a dielectric layer is laser-ablated to produce channels outlining a desired channel circuit pattern and conductive material is then plated over the surface of the dielectric layer and into the channels. A pattern is imaged on the plated conductive material for simultaneously removing material above the channels and forming a circuit pattern above the substrate surface, yielding a two-layer homogeneous metal structure forming a conductive pattern having features beneath the surface and features atop the surface. The opposing surface of the substrate may be simultaneously prepared in the same manner, yielding a four-level substrate. The pattern above the substrate surface may include terminal lands only, or it may include an interconnect pattern, vias and other features as well. The process may also be extended to include further layers generated on laminated dielectric layers to create a sandwich structure for multi-layer circuit applications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1K  are a pictorial diagrams depicting cross sectional side views illustrating steps of making a substrate in accordance with an embodiment of the invention; 
         FIG. 2A  is a pictorial diagram depicting an integrated circuit in accordance with an embodiment of the invention; 
         FIG. 2B  is a pictorial diagram depicting an integrated circuit in accordance with another embodiment of the invention; 
         FIG. 3A  is a pictorial diagram depicting a substrate in accordance with another embodiment of the invention; and 
         FIG. 3B  is a pictorial diagram depicting a substrate in accordance with yet another embodiment of the invention. 
     
    
    
     The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout. 
     DETAILED DESCRIPTION 
     The above-incorporated parent patent application discloses a process and structure for manufacturing a low-cost substrate having high conductor density and electrical integrity by embedding the conductive patterns beneath the surface of a substrate. The substrate is a laser-ablated substrate that does not require custom tooling for producing channels for conductors within a substrate and provides a manufacturing process having low cost and high conductor density. 
     The present invention provides an even higher-density routing capability by generating another etched level atop the dielectric surface(s) where the embedded conductors are located. The resulting metal circuit is a homogeneous metal structure having features atop the dielectric surface and features within the dielectric. The printed layer can contain large features that are generally time consuming to generate within channels and also in general are desirably located above or conformal with the substrate surface. Examples of such large features are: grid array lands, wire-bond pads and power distribution patterns. In contrast, the channel level conductors can include very fine-pitched interconnects due to the isolation provided between the channels and the increased depth of the conductors. One resulting effect is that die sizes can be substantially reduced by providing a finer wire-bond pad pitch and denser routing capability. 
     Referring now to the figures and in particular to  FIG. 1A , a side view of a clad dielectric  10 A, composed of a dielectric layer  12  covered by cladding  11  on both sides for use in preparing a substrate in accordance with an embodiment of the present invention, is depicted. Clad dielectric  10 A is the first stage of preparation of the illustrated substrate, and is processed with etchant to provide the second stage of substrate  10 B, which is dielectric layer  12  without the cladding. However, alternatives include providing a dielectric film without cladding or other solid dielectric layer that can be processed in the steps illustrated subsequent to that of  FIG. 1B . 
     A controlled laser is used to produce features within and through substrate  10 B to produce substrate  10 C of  FIG. 1C  that includes via holes  14 B and channels  14 A in an ablated dielectric layer  12 A. Next, as illustrated in  FIG. 1D , an electro-less seed plating layer  16  is generated on all surfaces of dielectric layer  12 A forming substrate  10 D. Next, as shown in  FIG. 1E , electroplating is performed to generate metal circuit  18 , which is a homogeneous metal plated structure that fills channels  14 A, vias  14 B and covers the surface(s) of substrate  10 E. 
     After substrate  10 E is completely covered in metal of sufficient height to generate all above-surface features, a photoresist film  17  is applied to the plated metal forming substrate step  10 F as illustrated in  FIG. 1F . Then, the photoresist is exposed and removed except in the above-surface feature areas  17 A and  17 B generating substrate  10 G as illustrated in  FIG. 1G . Next, the substrate  10 G is etched to form substrate  10 H, which now includes the metal circuit above and within the dielectric  12 A, with film remaining in feature areas  17 A and  17 B. Finally, the remaining film is removed, yielding substrate  10 I in accordance with an embodiment of the invention. Substrate  10 I is illustrated as including a via  19 A, and laser-embedded conductive pathways  19 A and  19 B. However,  FIG. 11  is intended to be illustrative of a potential final step in the process and not an actual substrate, which will have hundreds of features and conductive pathways and will include regions where the metal circuit extends within the substrate and also atop the substrate, providing a two-level circuit that homogeneously bridges the two levels to provide an interconnection. Such features are distinguishable from metal applied in separate steps, as is well known in the art of metallurgy, as microscopic crystalline differences will exist for a metal circuit plated up in a continuous manner rather than being deposited in subsequent plating processes. A single layer of metal generally will also provide a more reliable, lower resistance pathway than one produced in multiple steps. 
     Referring now to  FIG. 1J , solder mask  20 A and  20 B may be applied to the surfaces of substrate  10 I to protect channel conductors  19 B and facilitate attachment of solder balls and other features by providing surfaces that will not permit wicking and adhesion to covered areas. The regions where terminals will be formed on via  19 A (and other terminals not shown) are either laser-ablated or imaged open via a photo-sensitive solder mask process to form substrate  10 J. Finally, a plating such as OSP or nickel-gold may be applied to form terminals  21 A and  21 B to facilitate solder or wirebond attach, as well as protect the terminal areas from corrosion forming finished substrate  10 K as shown in  FIG. 1K . 
     Referring now to  FIG. 2A , a semiconductor package formed using substrate  10 K is shown. A die  30 A is mounted to substrate  10 K, generally with an adhesive film or epoxy and wires  32  are bonded between electrical terminals  31  of the die  30 A and bond pads  33  on substrate  10 K. Solder balls  34  are attached to lands on the bottom side of substrate  10 K to form a ball grid array package, which can then be encapsulated on the top side. An alternative semiconductor package is shown in  FIG. 2B , where a die  30 B is mounted in a flip-chip configuration using solder balls  34 A or alternatively solder posts. 
       FIGS. 2A and 2B  are intended to be illustrative of semiconductor packages (packaged integrated circuits) that may be manufactured in accordance with embodiments of the present invention and are thus not intended to be limiting. The techniques of the present invention have applications to other semiconductor package types and die types, as the two-level homogeneous metal circuit produced by the techniques of the present invention provides higher interconnect density in a low-cost manufacturing process. 
     Referring now to  FIG. 3A , a more general representation of the semiconductor package substrate of the present invention is shown. A dielectric layer  42  includes metal circuit channel areas  44  formed within dielectric layer  42  (via laser-ablation, plating and etching) and metal circuit surface areas  46  formed atop dielectric layer  42  (via plating and etching). Area A 1  illustrates an area where the metal circuit is channel level only, area A 2  illustrates an area where the metal circuit is above-surface level only (in the illustration, actually below the opposite surface) and area A 3  illustrates an area where the metal circuit bridges the two levels to provide a conductive path from a channel to a surface feature. All of the illustrations described above are for a double-sided substrate, but a single sided substrate may also be produced by selectively plating a dielectric layer that has been laser ablated on one side. 
       FIG. 3B  depicts an extension of the present invention to a multi-layer multi-level structure. Additional dielectric layers  52 A and  52 B may be laminated on a dielectric layer  52  prepared with two-level circuits in accordance with an embodiment of the present invention. Then, additional dielectric layers  52 A and  52 B may be subjected to the above-described process to generate two more outer two-level layers  56 A and  56 B having channels and surface-located features. Connections between circuit layers are provide by vias  54 A such as those vias  54 B used to connect the two-level structures on opposite sides of original dielectric layer  52 . 
     While the figures illustrate conductive circuit channels and above surface features, the figures are depicting only a portion of the total substrate. Hundreds of circuit channels and terminals will generally be used in an integrated circuit design and may be oriented in any direction within the surface of the substrate. Similarly, the pattern above the substrate surface may include terminal lands only, or may include circuit patterns as well. However, the pattern atop the substrate should be designed so that channel conductors are appropriately isolated when the metal is removed, and so unless two channels are to be electrically bridged, the pattern level above the substrate does not cross both of those channels, as electrical contact is made between a channel and the level above the substrate when any metal is present at both levels (i.e., when the circuit-positive photomask for the top layer intersects the channel ablating pattern at any point in the two-dimensional plane of the substrate surface). 
     The above description of embodiments of the invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure and fall within the scope of the present invention.