Abstract:
The present invention relates to a power socket for a microelectronic device that, in one embodiment, uses a low-resistance power and ground terminal configuration. In another embodiment, a low-resistance power and ground terminal configuration is combined on the power socket with a vertically oriented interdigital capacitor that is used to lower inductance. By this combination a significantly lowered impedance is achieved during operation of the microelectronic device.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a microelectronic device power socket. More particularly, the present invention relates to a high-power socket for a microelectronic device such as a processor. In particular, the present invention relates to a low resistance path and optionally a low inductance path for power delivery through the socket.  
           [0003]    2. Description of Related Art  
           [0004]    Chip packaging requires high-power sockets for devices such as processors and application-specific integrated circuits (ASICs). A processor requires a high current to enable the multiple-gigahertz clock cycles that are being achieved and to enable the variety of logic and memory operations that are simultaneously being executed. High currents through sockets require low resistances in order to minimize power dissipation that is otherwise caused by resistance heating. Larger power dissipations in the socket result in higher socket temperatures, that in turn slow and ultimately defeat the device. Additionally a high inductance is often generated in the power socket. Overall, the impedance, the ratio of voltage to current also affects the performance of the microelectronic device. An unacceptably high impedance will degrade both the signal and increase the resistance heating. When such a heating problem occurs, processor speed is slowed, or worse, the device fails with the result of lost data and lost productivity.  
           [0005]    One way to deal with the challenges created by high current draw is to use more input/output (I/O) pins for the current draw. This allows a larger cumulative cross-sectional area to carry the power current, but the result is added cost, and even more scarce I/O real estate on the footprint of the power socket. Further, where the number of pins added to the power dissipation load do not provide a significantly lowered resistance than the resistance of the pins in the more active regions of the processor, the effectiveness of the additional pins may not be sufficient to reduce the current flowing through a given region of the socket. Additionally, the added pins must provide an effective direct current (DC) shunt capability. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    In order that the manner in which embodiments of the present invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention that are not necessarily drawn to scale and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:  
         [0007]    [0007]FIG. 1 is a top plan view of a high power socket according to an embodiment;  
         [0008]    [0008]FIG. 2A is a top plan view of a high power socket according to an embodiment;  
         [0009]    [0009]FIG. 2B is an elevational view of the socket depicted in FIG. 2A;  
         [0010]    [0010]FIG. 2C is an elevational view of the socket depicted in FIG. 2A;  
         [0011]    [0011]FIG. 3 is a perspective view of an inter-digital capacitor according to an embodiment;  
         [0012]    [0012]FIG. 4 is a perspective view of an inter-digital capacitor according to an embodiment;  
         [0013]    [0013]FIG. 5 is a top plan view of a high power socket according to an embodiment; and  
         [0014]    [0014]FIG. 6 is a method flow diagram according to an embodiment. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]    The present invention relates to a power socket for a microelectronic device such as a processor. In one embodiment, a low resistance and low inductance path is provided for power delivery through the power socket to the processor or microelectronic device that is being serviced by the power socket.  
         [0016]    The following description includes terms, such as upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of a device or article of the present invention described herein can be manufactured, used, or shipped in a number of positions and orientations. The terms “die” and “processor” generally refer to the physical object that is the basic workpiece that is transformed by various process operations into the desired integrated circuit. A die is typically made of semiconductive material that has been singulated from a wafer after integrated processing. Wafers may be made of semiconducting, non-semiconducting, or combinations of semiconducting and non-semiconducting materials.  
         [0017]    Reference will now be made to the drawings wherein like structures will be provided with like reference designations. In order to show the structures of the present invention most clearly, the drawings included herein are diagrammatic representations of inventive articles. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the essential structures of the present invention. Moreover, the drawings show only the structures necessary to understand the present invention. Additional structures known in the art have not been included to maintain the clarity of the drawings.  
         [0018]    [0018]FIG. 1 illustrates a high-current power socket  10 . The power socket  10  includes a socket platform  12  including a major planar surface that is depicted in the X-Y plane. A first power terminal  14  is disposed on the socket platform  12  and is spaced apart from a first ground terminal  16  along an upper edge  18 . The first power terminal  14  includes a first cross-sectional area that is defined by a power terminal height  20  and a power terminal width  22 . The power socket  10  also includes an input/output (I/O) pin socket  24  that includes a second cross-sectional area defined by an I/O pin socket height  26  and an I/O pin socket width  28 . It is noted that the first cross-sectional area is larger than the second cross-sectional area. In one embodiment the ratio of the first cross-sectional area to the second cross-sectional area is from about 4:1 to about 50:1. In another embodiment, the ratio is from about 8:1 to about 40:1. In another embodiment, it is from about 16:1 to about 30:1. This cross-sectional area comparison may be a comparison of height  20  multiplied by the width  22 , compared to the cross-sectional area of a pin (not pictured) that inserts into I/O pin socket  24  from a device such as an interposer (not pictured). The cross-sectional area may also be the surface area of contact within the locking mechanism (not pictured) within the I/O pin socket  24  as is known in the art.  
         [0019]    In one embodiment, besides the first power terminal  14  and the first ground terminal  16 , the power socket  10  includes a second power terminal  30  and a second ground terminal  32 . Additionally in this embodiment as can be seen, a plurality of I/O pin sockets are provided that are substantially similar to the I/O pin socket  24 . In addition to the structure of power socket  10 , a center space  34  is provided in one embodiment for a power capacitor for delivering short-range power to the electronic device. In this embodiment, center space  34  is provided for a land-side capacitor (LSC).  
         [0020]    [0020]FIG. 2 illustrates another embodiment of a power socket  110 . In some applications, a lower inductance is desired during power delivery to an electronic device such as a general processor or an ASIC. The power socket  110  includes structures that are similar to the power socket  10  depicted in FIG. 1. A first power terminal  14  is disposed on a socket platform  112  and is spaced apart from a first ground terminal  16  along an upper edge  118 . Additionally, a first plurality of I/O pin sockets  24  is provided.  
         [0021]    Where the bulk of the power current supplied to the electronic device passes first through the power terminals  14  and  30 , and passes to ground through the ground terminals  16  and  32 , significant inductance may result for some applications. According to this embodiment, current is also allowed to pass through a capacitor structure as illustrated generically by item  136 . The capacitor structure  136  is oriented such that its capacitative surfaces (e.g. capacitor plates) are arranged orthogonal to the X-Y plane. In other words, the capacitor plates are vertically oriented to the major planar surface. In one embodiment, the capacitor structure  136  includes an inter-digital capacitor (illustrated in various embodiments in FIGS. 3 and 4). The inter-digital capacitor includes capacitor plates that are vertically (orthogonally) oriented to the major planar surface that is defined by the X-Y plane. Optionally and additionally, a second capacitor  138  that may be an inter-digital capacitor is disposed between second power terminal  30  and second ground terminal  32  at a lower edge  140  of power socket  110 .  
         [0022]    [0022]FIG. 2B is an elevational view of power socket  110 , taken along the line  2 B- 2 B from FIG. 2A. Power socket  110  in this view includes a major planar upper surface  142  and a major planar lower surface  144 . FIG. 2B illustrates that both power  30  and ground  32  terminals extend below major planar lower surface  144 , as well as second capacitor  138 . The degree to which the power and ground terminals as well as the capacitor(s) extend below major planar lower surface  144  is often determined by a specific application of the embodiment.  
         [0023]    [0023]FIG. 2C is an elevational view of power socket  110 , taken along the line  2 C- 2 C from FIG. 2A. Power socket  110  in this view includes the major planar upper surface  142  and the major planar lower surface  144 . FIG. 2C illustrates that both ground terminals  32  and  16  as they extend below major planar lower surface  144 . FIG. 2C also illustrates a second plurality of electrical bumps  150  disposed at the major planar lower surface  144 . In one embodiment, the bumps  150  are mounted on a bond pad  152 . In one embodiment, the bond pad  152  is set flush (not pictured) with the major planar lower surface  144 . In one embodiment, the second plurality of electrical bumps  150  is equal to the first plurality of I/O pin sockets  24 , depicted in FIG. 2A.  
         [0024]    [0024]FIG. 3 is a perspective view of an inventive inter-digital capacitor IDC  310  that is used in an embodiment of the invention. In this embodiment, a first capacitor plate  312  is assigned a power plate designation. First power capacitor plate  312  is connected to a first power connector  314 , and a second power connector  316  at the top side thereof, and electrical connection is made by a first power tab  318  and a second power tab  320 . At the bottom side thereof, first power capacitor plate  312  is connected to a third power connector  322 , and a fourth power connector  324  at the bottom side thereof, and electrical connection is made by a third power tab  326  and a fourth power tab  328 . By this configuration, first power tab  318  is most closely connected from the top to the bottom of IDC  310 , diagonally across first power capacitor plate  312  to fourth power tab  328 . This diagonal proximity may be referred to as a first polarity type.  
         [0025]    A second capacitor plate  330  is assigned a ground plate designation. Second ground capacitor plate  330  is connected to a first ground connector  332 , a second ground connector  334  at the top side thereof, and electrical connection is made by a first ground tab  336  and a second ground tab  338 . At the bottom side thereof, second ground capacitor plate  330  is connected to a third ground connector  340 , and a fourth ground connector  342  at the bottom side thereof, and electrical connection is made by a third ground tab  344  and a fourth ground tab  346 . Accordingly the inventive IDC includes a series of alternating power and ground connectors on the top side and on the bottom side. The power and ground connectors are configured to make a connection with other structures such as an interposer on one side and a board on the other side.  
         [0026]    It is noted that a plurality of alternating power and ground plates are depicted. According to an embodiment, the number of power and ground plates is in a range from about 4 to about 10,000 or more, depending upon the thickness of the plates and the totality of space in the X-dimension. In one embodiment, the number of power and ground plates is in a range from about 100 to about 2,000. In one embodiment, the number of power and ground plates is in a range from about 400 to about 800. In one embodiment, spacing between a given power capacitor plate and a given ground capacitor plate is in a range from about 0.1 mil to about 0.5 mils. In another embodiment, the spacing is about 0.3 mils.  
         [0027]    A dielectric material (not pictured) is placed between first power capacitor plate  312  and second ground capacitor plate  330 . In one embodiment, the dielectric material is silica. In one embodiment, the dielectric material is a low-K (meaning having a dielectric constant lower than that of silica) such as SiLK® made by Dow Chemical of Midland, Mich., or FLARE® made by AlliedSignal Inc. of Morristown, N.J.  
         [0028]    [0028]FIG. 4 is a perspective view of another IDC  410  according to an embodiment. In this embodiment, a first capacitor plate  412  is assigned a power plate designation. First power capacitor plate  412  is connected to a first power connector  414 , and a second power connector  416  at the top side thereof, and electrical connection is made by a first power tab  418  and a second power tab  420 . At the bottom side thereof, first power capacitor plate  412  is connected to a third power connector  422 , and a fourth power connector  424  at the bottom side thereof, and electrical connection is made by a third power tab  426  and a fourth power tab  428 . By this configuration, first power tab  418  is most closely connected from the top to the bottom of IDC  410 , substantially vertically across first power capacitor plate  412  to fourth power tab  428 . This substantially vertical proximity may be referred to as a second polarity type.  
         [0029]    A second capacitor plate  430  is assigned a ground plate designation. Second ground capacitor plate  430  is connected to a first ground connector  432 , a second ground connector  434  at the top side thereof, and electrical connection is made by a first ground tab  436  and a second ground tab  438 . At the bottom side thereof, second ground capacitor plate  430  is connected to a third ground connector  440 , and a fourth ground connector  442  at the bottom side thereof, and electrical connection is made by a third ground tab  444  and a fourth ground tab  446 .  
         [0030]    It is noted that a plurality of alternating power and ground plates are depicted. According to an embodiment, the number of power and ground plates is in a range from about 2 to about 10,000 or more, depending upon the thickness of the plates and the totality of space in the X-dimension. Other ground and power capacitor plate number ranges are set forth herein. In one embodiment, spacing between a given power capacitor plate and a given ground capacitor plate is in a range from about 0.1 mil to about 0.5 mils. In another embodiment, the spacing is about 0.3 mils.  
         [0031]    As set forth herein, a dielectric material (not pictured) is placed between first power capacitor plate  412  and second ground capacitor plate  430 .  
         [0032]    [0032]FIG. 5 depicts another embodiment in which the arrangement of power and ground terminals is rotated in relation to the vertical capacitors. A power socket  510  includes a first power terminal  514  embedded in a socket platform  512  and is spaced apart from a second power terminal  530  along an upper edge  518 . Additionally, a first plurality of I/O sockets  524  is provided. The major planar surface of power socket  510  is depicted in the X-Y plane. A first ground terminal  516  and a second ground terminal  532  are spaced apart along a lower edge  540 . In addition to the structure of power socket  510 , a center space  534  is provided in one embodiment for a power capacitor for delivering short-range power to the electronic device. In this embodiment, center space  534  is provided for an LSC.  
         [0033]    By this embodiment, current is also allowed to pass through a capacitor structure as illustrated generically by item  536 . The capacitor structure  536  is disposed between the first power terminal  514  and the second power terminal  530 . The capacitor structure  536  is oriented such that its capacitative surfaces (e.g. capacitor plates) are arranged orthogonal to the X-Y plane. In other words, the capacitor plates are vertically oriented to the major planar surface. In one embodiment, the capacitor structure  536  includes an inter-digital capacitor (illustrated in various embodiments in FIGS. 3 and 4). The inter-digital capacitor includes capacitor plates that are vertically (orthogonally) oriented to the major planar surface that is defined by the X-Y plane. Optionally and additionally, a second inter-digital capacitor  538  is disposed between the first ground terminal  516  and the second ground terminal  532  at the lower edge  540  of power socket  110 . It is noted in FIG. 5 that the IDCs  310  or  410  may be used as an embodiment in the location of capacitors  536  and  538 .  
         [0034]    By recitation of these embodiments, it should be noted that the placement of both the power and ground terminals as well as the capacitor with vertically oriented capacitor plates, may be substantially anywhere on the socket platform  512  as well as for the embodiment of the socket platform  12  (FIG. 1, for terminals only) and platform  112  (FIG. 2A). However, where the I/O pin sockets  524  may be optimally located directly below the processor or other microelectronic device, the location of the power and ground terminals as well as the capacitor, in one embodiment, is along the periphery of the socket platform  512 .  
         [0035]    According to a method embodiment, a method of operating a device is depicted in FIG. 6. The method commences by passing  610  a current through a power socket. The current may include an alternating first current and a direct second current. The alternating first current passes  620  in a first direction through a first capacitor plate that is configured in a plane collinear with the first direction. The direct second current passes  630  in the first direction through a power terminal. At certain frequencies, the alternating first current discharges  640  into a second capacitor plate and conducts in a second direction that is substantially opposite to the first direction. For example, the frequency is in a range from about 1 GHz to about 10 GHz. As set forth herein, the second capacitor plate is spaced apart and immediately adjacent the first capacitor plate. Because of the proximity of the first and second capacitor plates and the vertical loop inductance, surrounded by the plurality of power and ground plates, results in an inductance in a range below about 0.1 pico Henry/square. In another embodiment, the inductance is from about 0.01 pico Henry/square to about 0.06 pico Henry/square. In another embodiment, the inductance is about 0.03 pico Henry/square. Further operations in the method include the direct second current passing to ground  650  through a ground terminal in the second direction. One advantage of this embodiment is that the overall impedance is reduced by the concerted presence of the power and ground terminal(s) and the vertically oriented capacitor(s).  
         [0036]    The following is a method example. Reference may be made to the structure depicted in FIGS.  2 A- 2 C. A DC current in the range from about 30 Ampere to about 200 Ampere passes through power terminals  14  and  30 . An AC current in the range from about 10 milli Ampere to about 10 Ampere passes through the vertical capacitors  136  and  138  at a frequency of in a range from about 100 MHz to about 20 GHz. Total inductance in power socket  110  is in a range from about 0.1 picoHenry to about 10 picoHenry. Total resistance is in a range from about 2 milli Ohms to about 8 milli Ohms.  
         [0037]    It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.