Abstract:
A method of forming a gate metallization in a semiconductor integrated circuit by forming a polycrystalline silicon layer over a gate dielectric layer and then converting the polycrystalline silicon layer into tungsten or tungsten silicide by exposing the polycrystalline silicon to tungsten hexafluoride gas. The method enables the formation of polycrystalline silicon and tungsten or tungsten silicide in the same process cycle in the same reactor or in two similarly configured reactors or in two similarly configured clustered reactors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to microelectronic device fabrication, and more particularly, to a method of forming tungsten or tungsten silicide layers for use in gate metallizations and local interconnects in a semiconductor integrated circuit. 
     2. Description of the Related Technology 
     In microelectronic devices common in the art, a field effect transistor  10  is formed in a semiconductor  11  by interposing a gate  12  of the transistor between heavily doped regions comprising the source  14  and drain  16  of the transistor as shown in FIG.  1 . In older semiconductor devices, the gate  12  comprised doped polycrystalline silicon (poly) over the gate dielectric  20 . However, as the dimensions of transistors and their interconnections have decreased into the submicron region, the high resistivity of doped poly adversely impacts the switching speed of field effect transistors  10 . Thus, to increase the switching speed of a transistor  10 , semiconductor manufacturers use a multilayer structure  18  including a metallic layer, such as tungsten (W) or tungsten silicide (WSi 2 ), to reduce the resistivity of gates  12  and local interconnect lines so as to increase the operating speed of circuits formed from interconnected transistors. Thus, the gate  12  of a current transistor  10  typically comprises a multilayer structure  18  on top of a thin silicon oxide layer  20  in contact with the silicon semiconductor  11 . The multilayer structure  18  comprises a doped poly layer  22  in contact with the silicon oxide layer  20  and a metallic layer  24  comprising W or WSi 2  in contact with the poly layer  22 . 
     During the formation of the microelectronic device, a metallic W or WSi 2  layer may be deposited either selectively or nonselectively. In U.S. Pat. No. 4,913,929, Moslehi, et al., disclose several selective and nonselective methods for depositing a W layer using a cold wall single wafer thermal/microwave remote plasma multiprocessing reactor. Moreover, as described by Leusink, et al., in  J. Appl. Phys.  72, 490 (1992), selective deposition of W or WSi 2  proceeds by the following well known chemical reactions: 
     
       
         2WF 6 (g)+3Si(s)→2W(s)+3SiF 4 (g)  (1) 
       
     
     
       
         WF 6 (g)+3Si(s)→W(s)+3SiF 2 (g)  (2) 
       
     
     
       
         W(s)+2Si(s)→WSi 2   (3) 
       
     
     
       
         2WF 6 (g)+7Si(s)→2WSi 2 (s)+3SiF 4 (g)  (4) 
       
     
     Reactions 1 and 2 describe the formation of tungsten. After the tungsten has been formed by either reaction 1 or 2, it can react further with the underlying Si to form WSi 2  (reaction 3). Reaction 4 describes the direct formation of WSi 2 . Thus, the basic reaction is the silicon (Si) reduction of tungsten hexafluoride (WF 6 ) gas, a displacement reaction where exposed Si is converted to a solid layer of W thereby releasing the displaced Si in the volatile gases SiF 2  and SiF 4 . In contrast to nonselective or blanket depositions, these reactions cause selective deposition of W because only those Si regions exposed to WF 6  on the semiconductor  11  react to form a deposited W layer. There is no conversion to W of regions of the semiconductor  11  having exposed regions comprising materials other than Si, such as silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ). 
     According to reactions (1) and (2), every nanometer of W formed consumes approximately two nanometers of the exposed Si. Thus, as noted by Leusink, et al., the Si reduction of WF 6  should be suppressed as the etching of exposed Si, such as source or drain regions, is an undesired result. To prevent or reduce undesired etching of exposed Si regions, combinations of WF 6  gas and reducing agents, such as the gases H 2 , SiH 4  or GeH 4 , have been used for the chemical vapor deposition (CVD) of W. Currently, tungsten CVD by WF 6 /H 2  or WF 6 /SiH 4  are the preferred methods used in the microelectronics industry. However, in  IEEE Trans. Electron Devices , 37, 577 (1990), Kobayashi, et al., describe applying the selective deposition of W to form a W contact (plug) by substitution of undoped poly by W. FIG. 2 a  illustrates a cross sectional view of a semiconductor wafer prepared for the substitution of undoped poly by W. An oxide layer  32  resides on the silicon substrate  30 . A barrier layer  34  comprising titanium nitride (TiN) resides on the silicon oxide layer  32  and within the contact aperture  38 , where the TiN barrier layer  34  contacts the silicon substrate  30 . Lastly, a conformal poly layer  36  is deposited over the TiN barrier layer  34 . 
     Referring now to FIG. 2 b , an etch back of the poly layer  36  is performed to remove poly from the TiN barrier layer  34 . Note that the etch back step slightly over etches the poly layer  34  so that the remaining poly  36  is slightly recessed within the aperture  38 . Referring now to FIG. 2 c , a thin chemical oxide layer  40  is formed over the poly  36  within the aperture  38 . This chemical oxide layer  40  enhances the subsequent selective deposition of W. Lastly, substitution of poly  36  by W using WF 6  gas occurs to form a W plug  42  as shown in FIG. 2 d . Note that the entire volume of poly  36  (FIG. 2 c ) within the contact aperture  38  is replaced by W so as to form a W plug  42 . The TiN barrier layer  34  serves to stop the substitution of Si by W during the selective deposition of a contact. Moreover, this technique is also well adapted to via fills in multilevel metal layer interconnections. However, the TiN barrier layer  34  is not needed in a via fill process as the lower level metal serves to stop the Si substitution by W. Thus, selective deposition of W techniques have found only limited application in contact formation and via fill because of the desire to avoid consumption of exposed Si regions in other device fabrication applications. 
     Although Moslehi, et al., disclose in U.S. Pat. No. 4,913,929 that several wafer processing steps can be done sequentially in a single reactor, semiconductor manufacturers currently use multiple reactors of significantly different configuration to form and interconnect the many layers needed in a microelectronic device. For example, a manufacturer may use a cluster tool, such as an Applied Materials Centura, having a reactor chamber dedicated to the deposition of poly and also having a reactor chamber of significantly different configuration dedicated to the deposition of WSi 2 . The present art for tungsten silicide formation uses a gas mixture consisting of tungsten hexafluoride and silane or dichlorosilane. The tungsten silicide deposits according to the following reactions: 
     
       
         2WF 6 +7SiH 4 →2WSi 2 +2SiF 4 +14H 2   (5) 
       
     
     
       
         2WF 6 +10SiH 2 Cl 2 →2WSi 2 +3SiF 4 +3SiCl 4 +8HCl+6H 2   (6) 
       
     
     The nonselective WSi 2  deposition results in deposition of WSi 2  on the reactor walls and other areas exposed to the WF 6  and SiH 4  gas. Thus, this WSi 2  reactor chamber requires downtime for frequent etching (cleaning) to remove the WSi 2  buildup on exposed areas. 
     The use of multiple different reactors often results from a strategy to prevent incompatible chemical reactions and materials produced during the formation of a prior layer from impacting the formation of a current or subsequent layer in the same reactor. This strategy is of critical importance to a semiconductor manufacturer as minuscule amounts of impurities in any single layer of a microelectronic device often result in device failures and scrap. At the same time, however, the need for multiple reactors of different configuration creates substantial operational issues in addition to the significant capital funds required to procure multiple different reactors. For example, the manufacturer has to maintain spares for each of the multiple reactor configurations used in its factory at a considerable cost for spares inventory, warehousing and personnel to manage spares. 
     To improve their operations, microelectronic device manufacturers require fabrication methods and systems that enable them to perform multiple processing steps in reactor chambers of substantially similar configuration. Similarly, manufacturers require fabrication methods and systems that enable them to reduce the amount of cleanroom floorspace needed by fabrication equipment. Manufacturers likewise require fabrication methods and systems that reduce the amount of equipment downtime for cleaning and maintenance. In addition, manufacturers require fabrication methods and systems that reduce the need to manage a substantial number of different spares and consumables inventories for multiple different reactors. Moreover, manufacturers require fabrication methods and systems that facilitate continuous improvement of their fabrication equipment by their equipment vendors. Lastly, manufacturers require fabrication methods and systems that reduce the number of multiple different reactors so as to also reduce the amount of capital finds needed to procure fabrication equipment. 
     SUMMARY OF THE INVENTION 
     The present invention enables manufacturers to improve their operations by applying an integrated process to deposit poly or amorphous silicon and tungsten or tungsten silicide for use in the formation of multilayer gate metallizations in semiconductor integrated circuits. In contrast to present methods that produce tungsten or tungsten silicide deposits on reactor walls and other exposed areas, the present invention eliminates the need to use different reactors to form poly, tungsten and tungsten silicide layers in a gate structure and reduces the risk of contamination from reactor deposits and incompatible materials. The present invention likewise reduces equipment downtime for cleaning and maintenance operations associated with deposits on reactor walls and other exposed areas thereby improving equipment throughput. Moreover, the present invention permits a manufacturer to form the poly, tungsten and tungsten silicide layers of a gate structure in the same reactor, in another reactor of substantially similar configuration to the reactor used to form the poly layer or in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer. Thus, using the present invention, manufacturers can reduce the costs of procuring a variety of different reactors to form these layers. Similarly, manufacturers can reduce the cleanroom floorspace occupied by a variety of different reactors to deposit poly, tungsten and tungsten silicide. In addition, the present invention reduces the associated costs to manage spares inventories related to a variety of different reactors. Lastly, in contrast to structures fabricated using conventional techniques, the present invention produces gate metallization structures with improved adhesion between the tungsten or tungsten silicide layers and the poly layer thereby enabling the reduction of gate dimensions to increase circuit densities. 
     One aspect of the present invention includes a method of forming a gate in a semiconductor integrated circuit comprising the steps of forming a silicon layer over a gate dielectric layer on a substrate and forming a tungsten layer by converting a portion of said silicon layer to tungsten. 
     Another aspect of the present invention includes a method of forming a gate in a semiconductor integrated circuit device comprising the steps of forming a silicon layer over a gate dielectric layer on a substrate, forming a tungsten layer by converting a portion of said silicon layer to tungsten and annealing said substrate so as to convert a portion of said tungsten layer to a tungsten silicide layer. 
     Yet another aspect of the present invention includes a method of forming a gate in a semiconductor integrated circuit device comprising the steps of forming a silicon layer over a gate dielectric layer on a substrate and forming a tungsten silicide layer by converting a portion of said silicon layer to tungsten silicide. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross sectional illustration of a prior art field effect transistor having a multilayer gate structure. 
     FIG. 2 a  is a cross sectional illustration of a substrate prepared for the formation of a tungsten contact. 
     FIG. 2 b  is a cross sectional illustration of the substrate of FIG. 2 a  after etchback of the polysilicon layer. 
     FIG. 2 c  is a cross sectional illustration of the substrate of FIG. 2 b  after formation of a chemical oxide layer. 
     FIG. 2 d  is a cross sectional illustration of the substrate of FIG. 2 c  after conversion of tungsten to form a tungsten contact (plug). 
     FIG. 3 is a cross sectional illustration of a substrate prepared for the formation of a gate. 
     FIG. 4 is a cross sectional illustration of the substrate of FIG. 3 after deposition of a polysilicon layer. 
     FIG. 5 is a cross sectional illustration of the substrate of FIG. 4 after forming a tungsten layer by conversion of a portion of the polysilicon layer to tungsten. 
     FIG. 6 is a cross sectional illustration of the substrate of FIG. 5 after removing selected portions of the tungsten and polysilicon layers so as to define a gate. 
     FIG. 7 is a cross sectional illustration of the substrate of FIG. 5 after sufficient annealing to convert a portion of the tungsten layer to a tungsten silicide layer. 
     FIG. 8 is a cross sectional illustration of the substrate of FIG. 7 after removing selected portions of the tungsten, tungsten silicide and polysilicon layers so as to define a gate. 
     FIG. 9 is a cross sectional illustration of the substrate of FIG. 4 after forming a tungsten layer by conversion of the polysilicon layer to tungsten. 
     FIG. 10 is a cross sectional illustration of the substrate of FIG. 9 after removing selected portions of the tungsten layer so as to define a gate. 
     FIG. 11 is a cross sectional illustration of the substrate of FIG. 4 after forming a tungsten silicide layer by conversion of a portion of the polysilicon layer to tungsten silicide. FIG. 11 also illustrates the substrate of FIG. 5 after sufficient annealing to convert the tungsten layer to a tungsten silicide layer. 
     FIG. 12 is a cross sectional illustration of the substrate of FIG. 11 after removing selected portions of the tungsten silicide and polysilicon layers so as to define a gate. 
     FIG. 13 is a cross sectional illustration of the substrate of FIG. 4 after forming a tungsten silicide layer by conversion of the polysilicon layer to tungsten silicide. 
     FIG. 14 is a cross sectional illustration of the substrate of FIG. 13 after removing selected portions of the tungsten silicide layer so as to define a gate. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 3, a substrate  100  is prepared for the formation of a gate. The term substrate refers to one or more semiconductor layers or structures which include active or operable portions of semiconductor devices. A gate dielectric  104  has been grown over the entire substrate  100  in preparation for formation of transistor gate structures. In a preferred embodiment, the substrate  100  comprises a silicon semiconductor wafer having a lightly doped single crystal silicon top layer  102  wherein the microelectronic circuits are fabricated. The gate dielectric  104  comprises a thin layer of silicon oxide having a thickness of about 10 nanometers. 
     Referring now to FIG. 4, a silicon layer  112  has been deposited over the gate dielectric  104 . In a preferred embodiment, a polycrystalline silicon (poly) layer  112  is formed over the gate dielectric  104  by exposing the substrate  110  to silane (SiH 4 ) gas at a temperature in the range of 575° C. to 800° C. and at a pressure in the range of 0.1 torr to 760 torr for a time sufficient to form a thickness in the range of 100 nanometers to 800 nanometers. In another preferred embodiment, a poly layer  112  is formed over the gate dielectric  104  by exposing the substrate  110  to disilane (Si 2 H 6 ) gas at a temperature in the range of 575° C. to 800° C. and at a pressure in the range of 0.1 torr to 760 torr for a time sufficient to form a thickness in the range of 100 nanometers to 800 nanometers. Generally, the SiH 4  and Si 2 H 6  flows will be diluted in a H 2  or N 2  carrier gas. In yet another preferred embodiment, an amorphous silicon (a-Si) layer  112  is formed over the gate dielectric  104  by exposing the substrate  110  to SiH 4  or Si 2 H 6  gas at a temperature in the range of 500° C. to 575° C. and at a pressure in the range of 0.1 torr to 760 torr for a time sufficient to form a thickness in the range of 100 nanometers to 800 nanometers. In the higher temperature range, the a-Si layer formed may include some polycrystalline silicon regions. Note that deposited a-Si layers often have smoother surfaces and better uniformity as compared to deposited poly layers. 
     Moreover, the silicon layer  112  may be doped in situ during its formation. In a preferred embodiment, dopant gases, such as AsH 3 , PH 3  and B 2 H 6 , are added to the SiH 4  or Si 2 H 6  flow during formation of the poly or a-Si layer. The dopant profiles within the silicon layer  112  may be defined by adjustment of the dopant gas flowrate during formation of the silicon layer  112 . For example, if the dopant gas flow is shut off prior to that for the SiH 4 , the top portion of the silicon layer  112  will be undoped while the bottom portion is doped. Similarly, if the dopant gas flow is increased towards the end of the deposition process, the top portion of the silicon layer  112  will be more heavily doped than the bottom portion. The ability to fabricate a silicon layer  112  having a tailored dopant concentration profile facilitates subsequent device processing. 
     After depositing the poly layer  112 , a tungsten layer is formed from a portion of the poly layer  112  using the displacement reaction. Referring now to FIG. 5, in a preferred embodiment, formation of a tungsten layer  124  proceeds by exposing the poly layer  112  (FIG. 4) of the substrate  110  (FIG. 4) to tungsten hexafluoride (WF 6 ) gas at a temperature in the range of 300° C. to 400° C. and at a pressure in the range of 0.1 to 760 torr. Generally, the WF 6  will be diluted in a carrier gas, such as argon (Ar) or nitrogen (N 2 ). Note that any gas may be selected as a carrier gas so long as the carrier gas does not react with WF 6  to deposit W on top of the poly layer  112  instead of converting a portion of the poly layer  112  to form a tungsten layer  124 . Under these conditions, a tungsten layer  124  of a selected self-limiting thickness is formed over the poly layer  122 . Self-limiting refers to a condition where the growth of the tungsten layer  124  stops after a certain time, even though sufficient quantities of WF 6  are still available for reaction with Si. For example, at a temperature of 370° C., a total pressure of 0.5 torr, a WF 6  flow of 50 sccm and an Ar flow of 2000 sccm, a self-limiting tungsten film of about 20 nm is formed in approximately 10 seconds. Note that the growth of the tungsten layer  124  is maintained by Si diffusion from the poly layer  122  until the reaction abruptly stops due to the self-limiting effect. At temperatures above about 300° C., the reaction rate is determined by the WF 6  gas diffusion through a boundary layer that forms above the top surface of the tungsten layer  124  in the gas phase. Thus, the growth rate of the tungsten layer  124  is proportional to the WF 6  pressure and inversely proportional to the total pressure. The self-limiting effect occurs when the reaction rate becomes limited by the supply of Si atoms from the poly layer  122  to the top surface of the tungsten layer  124 . At this moment, the fast diffusion paths for Si are blocked rapidly and the growth stops. As the diffusion of Si to the top surface of the tungsten layer  124  is thermally activated, the thickness of the tungsten layer  124  can be engineered by selecting the proper temperature, WF 6  and total pressure. In another preferred embodiment, the formation of a tungsten layer  124  occurs in the same reactor used to form the poly layer  112  (FIG.  4 ). In yet another preferred embodiment, the formation of a tungsten layer  124  occurs in another reactor of substantially similar configuration to the reactor used to form the poly layer  112  (FIG.  4 ). In yet another preferred embodiment, formation of a tungsten layer  124  occurs in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer  112  (FIG.  4 ). A multilayer gate structure  136  is subsequently defined by removing selected portions of the poly layer  122  and the tungsten layer  124  as shown in FIG.  6 . Note that the gate  136  includes a tungsten layer  134  over a poly layer  132 . 
     Once a tungsten layer  124  (FIG. 5) has been formed from a portion of the poly layer  112  (FIG.  4 ), a tungsten silicide layer may be formed by conversion of a portion of the remaining poly layer  112 . Referring now to FIG. 7, in a preferred embodiment, a portion of the tungsten layer  124  (FIG. 5) has been converted to a tungsten silicide layer  146  by annealing the substrate  120  (FIG. 5) under an inert atmosphere, such as Argon, at a temperature in the range of 600° C. to 1000° C. to form a tungsten silicide layer  146 . In another preferred embodiment, the substrate  120  (FIG. 5) is annealed in the same reactor used to form the poly layer  112  (FIG. 4) and to form the tungsten layer  124  (FIG.  5 ). In yet another preferred embodiment, the substrate  120  (FIG. 5) is annealed in another reactor of substantially similar configuration to the reactor used to form the poly layer  112  (FIG. 4) and to form the tungsten layer  124  (FIG.  5 ). In yet another preferred embodiment, the substrate  120  (FIG. 5) is annealed in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer  112  (FIG. 4) and to form the tungsten layer  124  (FIG.  5 ). A multilayer gate structure  158  is subsequently defined by removing selected portions of the poly layer  142 , the tungsten silicide layer  146  and the tungsten layer  144  as shown in FIG.  8 . Note that the gate  158  includes a tungsten layer  154  over a tungsten silicide layer  156  over a poly layer  152 . 
     Referring now to FIG. 9, the entire poly layer  112  (FIG. 4) is converted into a tungsten layer  162  by using either a higher total pressure, a lower WF 6  partial pressure or a higher temperature. Under these conditions, all of the poly layer  112  is consumed before the self-limiting thickness is reached. In a preferred embodiment, formation of a tungsten layer  162  proceeds by exposing the poly layer  112  (FIG. 4) of the substrate  110  (FIG. 4) to tungsten hexafluoride (WF 6 ) gas at a temperature in the range of 300° C. to 400° C. and at a total pressure in the range of 0.1 to 760 torr for a time sufficient to convert the entire poly layer  112  (FIG. 4) to tungsten. For example, at a temperature of 370° C., a total pressure of 4.0 torr, a WF 6  flow of 50 sccm and an Ar flow of 2000 sccm, a 300 nm poly layer is entirely consumed to form a tungsten film of about 150 nm thickness in approximately 160 seconds. As noted above, there is no self-limiting effect here because the entire poly layer  112  (FIG.  4 ) is already consumed before the self-limiting thickness is reached. For example, at a temperature of 400° C., a total pressure of 0.5 torr, a WF 6  flow of 25 sccm and an Ar flow of 2000 sccm, a 300 nm poly layer is entirely consumed to form a tungsten film of about 150 nm thickness in approximately 180 seconds. In yet another preferred embodiment, formation of a tungsten layer  162  proceeds by exposing the poly layer  112  (FIG. 4) of the substrate  110  (FIG. 4) to tungsten hexafluoride (WF 6  ) gas at a temperature in the range of 300° C. to 400° C. and at a WF 6  partial pressure in the range of 0.0025 torr to 76 torr for a time sufficient convert the entire poly layer  112  (FIG. 4) to tungsten. For example, at a temperature of 370° C., a total pressure of 0.5 torr, a WF 6  flow of 12.5 sccm and an Ar flow of 2000 sccm, a 300 nm poly layer is entirely consumed to form a tungsten film of about 150 nm thickness in approximately 160 seconds. In yet another preferred embodiment, formation of a tungsten layer  162  occurs in the same reactor used to form the poly layer  112  (FIG.  4 ). In yet another preferred embodiment, formation of a tungsten layer  162  occurs in another reactor of substantially similar configuration to the reactor used to form the poly layer  112  (FIG.  4 ). In yet another preferred embodiment, formation of a tungsten layer  162  occurs in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer  112  (FIG.  4 ). A tungsten gate structure  174  is subsequently defined by removing selected portions of the tungsten layer  162  as shown in the substrate  170  in FIG.  10 . 
     Moreover, a tungsten silicide layer may also be formed from a portion of the poly layer  112  (FIG.  4 ). Referring now to FIG. 11, in a preferred embodiment, formation of a tungsten silicide layer  184  proceeds by exposing the poly layer  112  (FIG. 4) of the substrate  110  (FIG. 4) to tungsten hexafluoride (WF 6  ) gas at temperatures generally above 450° C. and at a pressure in the range of 0.1 to 760 torr. Under these conditions, the self limiting effect does not occur. Thus, to form a tungsten silicide layer  184  of a predetermined thickness over the poly layer  182 , the WF 6  flow must be terminated. For example, at a temperature of 500° C., a total pressure of 0.5 torr, a WF 6  flow of 10 sccm and an Ar flow of 2000 sccm, a WSi 2  layer of 145 nm thickness is formed when the WF 6  flow is terminated in approximately 50 seconds. Note that the tungsten silicide layer  184  formed may be in the metastable hexagonal high resistivity phase. To reduce the resistivity, the substrate  180  is annealed under an inert atmosphere, such as Argon, at a temperature in the range of 600° C. to 1000° C. for a time sufficient to convert the entire hexagonal tungsten silicide phase to the lower resistivity tetragonal tungsten silicide phase. In another preferred embodiment, formation of a tungsten silicide layer  184  occurs in the same reactor used to form the poly layer  112  (FIG.  4 ). In yet another preferred embodiment, formation of a tungsten silicide layer  184  occurs in another reactor of substantially similar configuration to the reactor used to form the poly layer  112  (FIG.  4 ). In yet another preferred embodiment, formation of a tungsten silicide layer  184  occurs in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer  112  (FIG.  4 ). 
     FIG. 11 also illustrates the substrate  120  (FIG. 5) after sufficient annealing to convert the tungsten layer  124  (FIG. 5) and a portion of the poly layer  122  (FIG. 5) to a tungsten silicide layer  184 . In a preferred embodiment, the substrate  120  (FIG. 5) having a tungsten layer  124  over a poly layer  122  (FIG. 5) is annealed under an inert atmosphere, such as Argon, at a temperature in the range of 600° C. to 1000° C. for a time sufficient to convert the entire tungsten layer  124  (FIG. 5) to tungsten silicide  184 . In another preferred embodiment, the substrate  120  (FIG. 5) is annealed in the same reactor used to form the poly layer  112  (FIG. 4) and to form the tungsten layer  124  (FIG.  5 ). In yet another preferred embodiment, the substrate  120  (FIG. 5) is annealed in another reactor of substantially similar configuration to the reactor used to form the poly layer  112  (FIG. 4) and to form the tungsten layer  124  (FIG.  5 ). In yet another preferred embodiment, the substrate  120  (FIG. 5) is annealed in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer  112  (FIG. 4) and to form the tungsten layer  124  (FIG.  5 ). A multilayer gate structure  196  is subsequently defined by removing selected portions of the poly layer  182  and the tungsten silicide layer  184  as shown in the substrate  190  in FIG.  12 . Note that the gate  196  includes a tungsten silicide layer  194  over a poly layer  192 . 
     Referring now to FIG. 13, the entire poly layer  112  (FIG. 4) is converted into a tungsten silicide layer  202 . In a preferred embodiment, formation of a tungsten silicide layer  202  proceeds by exposing the poly layer  112  (FIG. 4) of the substrate  110  (FIG. 4) to tungsten hexafluoride (WF 6  ) gas at temperatures generally above 450° C. and at a pressure in the range of 0.1 to 760 torr until the entire poly layer  112  (FIG. 4) has been consumed. For example, at a temperature of 500° C., a total pressure of 0.5 torr, a WF 6  flow of 10 sccm and an Ar flow of 2000 sccm, a 450 nm poly layer is entirely consumed to form a tungsten silicide film of about 250 nm thickness in approximately 250 seconds. Note that the tungsten silicide layer  202  formed may be in the metastable hexagonal high resistivity phase. To reduce the resistivity, the substrate  180  is annealed under an inert atmosphere, such as Argon, at a temperature in the range of 600° C. to 1000° C. for a time sufficient to convert the entire hexagonal tungsten silicide phase to the lower resistivity tetragonal tungsten silicide phase. In another preferred embodiment, formation of a tungsten silicide layer  202  occurs in the same reactor used to form the poly layer  112  (FIG.  4 ). In yet another preferred embodiment, formation of a tungsten silicide layer  202  occurs in another reactor of substantially similar configuration to the reactor used to form the poly layer  112  (FIG.  4 ). In yet another preferred embodiment, formation of a tungsten silicide layer  202  occurs in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer  112  (FIG.  4 ). A tungsten silicide gate structure  214  is subsequently defined by removing selected portions of the tungsten silicide layer  202  to leave a patterned tungsten silicide layer  212  as shown in FIG.  14 . 
     The present invention advantageously overcomes several limitations of existing technologies and alternatives. In contrast to conventional deposition processes where a reducing agent, such as H 2  or SiH 4  is added to the WF 6  flow, the WF 6  Si conversion reaction produces no deposits or coatings on the reactor walls. Thus, a semiconductor device manufacturer using the present invention to form gate metallizations avoids contamination from reactor coatings and deposits. At the same time, the manufacturer can improve the throughput of its reactors by avoiding frequent reactor cleans required for present deposition methods. In addition, use of the present invention to form a multilayer gate structure produces improved adhesion between the tungsten or tungsten silicide layers and the poly layer as compared to the adhesion of a traditionally deposited tungsten silicide layer on the poly layer, which exhibit cracking followed by delamination with narrower gate dimensions. 
     Moreover, the present invention eliminates the need to use different reactors to form the poly layer and the tungsten or tungsten silicide layer. Thus, a manufacturer can form a poly layer followed by a tungsten or tungsten silicide layer in the same reactor, in another reactor of substantially similar configuration to the reactor used to form the poly layer or in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer. This flexibility allows the manufacturer to save costs related to the procurement, installation, use and maintenance of multiple different reactors. In using the present invention, a manufacturer thus realizes certain economies of scale as reactors share the same parts, require the same maintenance and the same training to operate. Lastly, because of the high selectivity of WF 6  reduction by Si, a manufacturer may practice the present invention in multiple wafer reactors. Thus, the present invention enables the metallization of a full batch of poly deposited wafers at once with tungsten or tungsten silicide. 
     Those skilled in the art may practice the principles of the present invention in other specific forms without departing from its spirit or essential characteristics. Accordingly, the disclosed embodiments of the invention are merely illustrative and do not serve to limit the scope of the invention set forth in the following claims.