Abstract:
A system and method is provided for processing four samples per clock period of an orthogonal frequency division multiplex symbol  10  having a length not a multiple of four. The method includes providing a sequence of data samples  12  and a sequence of non-data samples  14  and  16.  The method includes selecting four input samples from one of the data samples  12  and the non-data samples  14  and  16  based on a clock signal. The method includes storing at least a portion of contents of a first group of memory cells  112  in a second group of memory cells  116 . The first group of memory cells  112  comprised of four memory cells  112   a - d . The method also provides for storing the selected four input samples in the first group of memory cells  112.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority to U.S. Provisional Application No. 60/545,631 filed Feb. 17, 2004, and entitled “Implementation for a 5 Sample Guard Interval for Multi-band OFDM,” by Navin S. Chander et al, which is incorporated herein by reference for all purposes. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     Not applicable.  
       REFERENCE TO A MICROFICHE APPENDIX  
       [0003]     Not applicable.  
       FIELD OF THE INVENTION  
       [0004]     The present disclosure is directed to wireless communications, and more particularly, but not by way of limitation, to a system and method for generating a 165 sample length orthogonal frequency division multiplex symbol for an ultra wideband system based on the Multi-band Orthogonal Frequency Division Multiplex system specification.  
       BACKGROUND OF THE INVENTION  
       [0005]     A wireless network provides for wireless communication among members of the wireless network. Wireless local area networks (WLANs) with ranges of about 100 meters or so have become increasingly popular. Wireless local area networks may employ sophisticated protocols to promote communications. Wireless personal area networks with ranges of about 10 meters are poised for growth, and continued engineering development effort is committed to developing protocols supporting wireless personal area networks.  
         [0006]     With limited range, wireless personal area networks may have fewer members and require less power than wireless local area networks. The IEEE (Institute of Electrical and Electronics Engineers) is developing the IEEE 802.15.3a wireless personal area network standard. The multi-band orthogonal frequency division multiplex (MB-OFDM) system is one possible implementation of the 802.15.3a high data rate physical layer specification. The term piconet refers to a wireless personal area network having an ad hoc topology comprising communicating devices coordinated by a piconet coordinator (PNC). Piconets may form, reform, and abate spontaneously as various wireless devices enter and leave each other&#39;s proximity. Piconets may be characterized by their limited temporal and spatial extent. Physically adjacent wireless devices may group themselves into multiple piconets running simultaneously.  
         [0007]     The MB-OFDM wireless personal area network standard divides an approximately 7.5 GHz bandwidth from about 3.1 GHz to 10.6 GHz into fourteen approximately 528 MHz wide bands. These fourteen bands are organized into four band groups of three 528 MHz bands each and one band group of two 528 MHz bands. The IEEE 802.15.3a version of this standard is directed to high data rate communications, including transmission rates of 55 mbps to 480 mbps. A piconet may transmit a first orthogonal frequency division multiplex (OFDM) symbol in a first 312.5 nS duration time interval in a first frequency band of a band group, a second OFDM symbol in a second 312.5 nS duration time interval in a second frequency band of the band group, and a third OFDM symbol in a third 312.5 nS duration time interval in a third frequency band of the band group. Other piconets may also transmit concurrently using the same band group, discriminating themselves by using a distinguishing preamble sequence. This method of piconets sharing a band group by transmitting on each of the three 528 MHz wide frequencies of the band group may be referred to as time frequency coding or time frequency interleaving (TFI). Alternately, piconets may transmit exclusively on one frequency band of the band group which may be referred to as fixed frequency interleaving (FFI).  
       SUMMARY OF THE INVENTION  
       [0008]     According to one embodiment, a circuit for assembling an orthogonal frequency division multiplex symbol is provided. The circuit includes a first multiplexer operable to select four of eight inputs to route samples present on the eight inputs to four outputs based on clock input from a first clock. The circuit includes a first group of four memory cells coupled to receive the samples from the four outputs of the first multiplexer and output the samples on an edge of clock input of the first clock. The circuit a second group of memory cells coupled to receive at least a portion of the samples from the four outputs of the first group of memory cells on an edge of clock input of the first clock. The circuit also includes a second multiplexer operable to select four of sixteen inputs to route samples present on the sixteen inputs to four outputs based on a clock input from the first clock to form orthogonal frequency division multiplex symbols.  
         [0009]     In one embodiment, the present disclosure provides a method for processing four samples per clock period of an orthogonal frequency division multiplex symbol having a length not a multiple of four. The Method includes providing a sequence of data samples and a sequence of non-data samples. The method includes selecting four input samples from one of the data samples and the non-data samples based on a clock signal. The method includes storing at least a portion of contents of a first group of memory cells in a second group of memory cells. The first group of memory cells comprised of four memory cells. The method also provides for storing the selected four input samples in the first group of memory cells.  
         [0010]     In another embodiment, the present disclosure provides a system for constructing an orthogonal frequency division multiplex symbol. The system includes a first clock, a first two-to-one multiplexer, a first and second group of memory cells, and a four-to-one multiplexer. The first two-to-one multiplexer has four outputs, a first group of four inputs, a second group of four inputs, and an input based on the first clock. The first two-to-one multiplexer is operable to select one of the first and second group of four inputs to connect to the four outputs of the first two-to-one multiplexer. The selection is based on the input based on the first clock. The first group of four memory cells having four inputs coupled to the four outputs of the first two-to-one multiplexer. The first group of four memory cells also having an input from the first clock and four outputs. The first group of memory cells stores a first set of four sample values received on the four inputs of the first group of memory cells. The second group of memory cells has inputs coupled to at least some of the four outputs of the first group of memory cells. The second group of memory cells has an input from the first clock and is operable to store a second set of sample values received on the inputs of the second group of four memory cells. The four-to-one multiplexer has four outputs and four groups of four inputs, a first, second, third, and fourth group of four inputs. The first group of four inputs is coupled to four of the first and second group of memory cells. The second group of four inputs is coupled to another four of the first and second group of memory cells. The third group of four inputs is coupled to another four of the first and second group of memory cells. The fourth group of four inputs is coupled to another four of the first and second group of memory cells. The four-to-one multiplexer has an input based on the first clock and is operable to select one of the first, second, third, and fourth group of four inputs to connect to the four outputs of the four-to-one multiplexer, the selection being based on the input of the clock.  
         [0011]     These and other features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.  
         [0013]      FIG. 1  illustrates a  165  sample orthogonal frequency division multiplex symbol.  
         [0014]      FIG. 2  illustrates a portion of a transmitter circuit according to one embodiment of the present disclosure.  
         [0015]      FIG. 3A  is a block diagram of a first portion of a symbol assembler for an embodiment of the present disclosure.  
         [0016]      FIG. 3B  is a block diagram of a cyclic prefix/guard interval two-to-one multiplexer for an embodiment of the present disclosure.  
         [0017]      FIG. 4  is a block diagram of a second portion of a symbol assembler for an embodiment of the present disclosure.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]     It should be understood at the outset that although an exemplary implementation of one embodiment of the present disclosure is illustrated below, the present system may be implemented using any number of techniques, whether currently known or in existence. The present disclosure should in no way be limited to the exemplary implementations, drawings, and techniques illustrated below, including the exemplary design and implementation illustrated and described herein.  
         [0019]     Turning to  FIG. 1 , an OFDM symbol  10  is depicted. The OFDM symbol  10  may comprise  165  samples including 128 data samples  12 , 32 cyclic prefix samples  14 , and 5 guard samples  16 . The cyclic prefix samples  14  may also be referred to as zero prefix samples. The data samples  12  contain the principle information content of the OFDM symbol  10 . The cyclic prefix samples  14  and the guard samples  16  are provided to promote reliable communications. The cyclic prefix samples  14  may support an OFDM symbol structure, and the guard samples  16  may support time frequency interleaving (TFI) of fixed frequency interleaving (FFI) of the MB-OFDM system. The samples are digital numbers comprising from 4 bits to 8 bits. In other embodiments, a different number of bits may be employed to compose the samples.  
         [0020]     Turning to  FIG. 2 , a portion of a wireless personal area network transmitter  50  is depicted. Data tones are input to an inverse fast Fourier transform component  52  which transforms the data tones from the frequency domain to the time domain as a sequence of the data samples  12 . The sequence of data samples  12  are input to a symbol assembler  54 . The cyclic prefix samples  14  and the guard interval samples  16  are also input to the symbol assembler  54 . The symbol assembler  54  assembles the data samples  12 , the cyclic prefix samples  14 , and the guard interval samples  16  into a sequence of four samples which are output to a digital-to-analog converter  56 . The symbol assembler  54  receives a first clock input  55  which the symbol assembler  54  uses to output the four samples to the digital-to-analog converter  56 . In an embodiment, the first clock input  55  is a 132 MHz clock input.  
         [0021]     The digital-to-analog converter  56  receives a second clock input  57  which may be four times the frequency of the first clock input  55 , which the digital-to-analog converter  56  uses to output one sample of the four samples received from the symbol assembler  54 , to serialize the OFDM symbol  10 . By outputting each sample, the digital-to-analog converter  56  generates a stream of samples that may be referred to as a baseband signal. In an embodiment, the second clock input  57  is a 528 MHz clock input.  
         [0022]     The digital-to-analog converter  56  outputs the baseband signal to an up converter  58  which frequency shifts the baseband signal to a higher frequency suitable for transmission. The up converter  58  outputs the up converted signal to an amplifier  60  which boosts the amplitude of the up converted signal to promote radio transmission and sends the amplified up converted signal to an antenna  62 . The antenna  62  transmits the amplified up converted signal as electromagnetic energy.  
         [0023]     Turning now to  FIG. 3A , a block diagram depicts one embodiment of a first portion of the processing provided by the symbol assembler  54 . The four data sample inputs from the inverse fast Fourier transformer  52  are shown as data sample inputs I 1    102 —a first data sample input I 1 (1)  102   a , a second data sample input I 1 (2)  102   b , a third data sample input I 1 (3)  102   c , and a fourth data sample input I 1 (4)  102   d . In the present embodiment, the cyclic prefix samples  14  and the guard interval samples  16  are always zero values. The guard interval samples are zero valued to promote frequency discrimination between adjacent frequency bands. When not otherwise employed for receiving the OFDM symbol, assigning zero values to the cyclic prefix samples further promotes frequency discrimination between adjacent frequency bands. Four zero valued sample inputs are shown as zero sample inputs I 2    104 —a first zero sample input I 2 (1)  104   a , a second zero sample input I 2 (2)  104   b , a third zero sample input I 2 (3)  104   c , and a fourth zero sample input I 2 (4)  104   d.    
         [0024]     The first clock input  55  is provided to a first state machine component  106 . The first state machine  106  controls a first multiplexer  108 , a two-to-one multiplexer, based on the first clock input  55 . In a first position, the first multiplexer  108  provides the data sample inputs I 1    102  to a respective first memory cell bank  112  via inputs  110 . In a second position, the first multiplexer  108  provides the zero sample inputs I 2    104  to the respective first memory cell bank  112  via inputs  110 . In the one embodiment, the first clock input  55  is processed by the first state machine  106  to produce a first mux count which counts the first clock input  55  modulo  165 . Thus, the first mux count increments on each clock period of the first clock input  55  from 0 to 164, and then back to 0 on the first clock period of the first clock input  55  after counting 164. The first state machine  106  may control the first multiplexer  108  to select between the data sample inputs I 1    102  and the zero sample inputs I 2    104  according to the following table.  
                                                   Select I 1      0   41 mux count    82 mux count   123 mux count       position   mux count       Select I 2     32   73 mux count   114 mux count   155 mux count       position   mux count                 For first mux count values not identified in the table, the first multiplexer 108 remains in the previously selected position.             
 
         [0025]     In other embodiments, some of the cyclic prefix samples  14  may be non-zero valued. Turning now to  FIG. 3B , a second multiplexer  134 , also a two-to-one multiplexer, is shown. The second multiplexer  134  is upstream of the first multiplexer  108  and provides the inputs  104  to the first multiplexer  108 . The second multiplexer  134  is coupled to the four inputs I 2    104  depicted in  FIG. 3A  above. Cyclic prefix inputs  130  provide cyclic prefix samples and guard interval inputs  131  provide guard interval samples to the second multiplexer  134 . A second state machine  136  controls the second multiplexer  134  based on the first clock input  55 . In a first position, the second multiplexer  134  selects cyclic prefix values to provide to the four inputs I 2    104 . In a second position, the second multiplexer  134  selects the guard interval input  131  samples to provide to the four inputs  12   104 . The guard interval samples are all zero valued. The first clock input  55  may be processed by the second state machine  136  to produce a second mux count which counts the first clock input  55  modulo  165 . The second mux count increments on each clock period of the first clock input  55  from 0 to 164, and then back to 0 on the first clock period of the first clock input  55  after counting 164. The second mux count is always in agreement with the first mux count described above. In an embodiment, the second state machine  136  is omitted and the first mux count is distributed to both the first multiplexer  108  and the second multiplexer  134 . The second state machine  136  may control the second multiplexer  134  to select between the cyclic prefix inputs  130  and the guard interval inputs  131  according to the following table.  
                                                   Select   32   73 mux count   114 mux count   155 mux count       Cyclic   mux count       Prefix       Select   40   81 mux count   122 mux count   163 mux count       Guard   mux count       Interval                 For second mux count values not identified in the table, the second multiplexer 134 remains in the previously selected position. In an embodiment in which the cyclic prefix samples on the cyclic prefix inputs 130          # are all zero valued, the second multiplexer 134 is not implemented.           
 
         [0026]     Turning back to  FIG. 3A , the first memory cell bank  112  comprises four individual memory cells—a first memory cell  112   a  having an input  110   a , a second memory cell  112   b  having an input  110   b , a third memory cell  112   c  having an input  110   c , and a fourth memory cell  112   d  having an input  110   d . The first memory cell bank  112  receives the first clock input and stores the value of the inputs  110  on the clock period. After the value of the inputs  110  have been stored by the first memory cell bank  112 , the first memory cell bank  112  outputs these values to the inputs  114  of a second memory cell bank  116 . The second memory cell bank  116  comprises four individual memory cells—a fifth memory cell  116   a  having an input  114   a , a sixth memory cell  116   b  having an input  114   b , a seventh memory cell  116   c  having an input  114   c , and an eighth memory cell  116   d  having an input  114   d . In an embodiment, the fifth memory cell  116   a  is never read from, the input  114   a  may be omitted, and the fifth memory cell  116   a  may be omitted from the second memory cell bank  116 . The second memory cell bank  116  receives the first clock input and stores the value of the inputs  114  on the clock period. The first memory cell bank  112  and the second memory cell bank  116  form a sequence such that the contents of the second memory cell bank  116  during a particular clock period is the contents that the first memory cell bank  112  held during the previous clock period.  
         [0027]     Turning now to  FIG. 4 , a block diagram depicts a second portion of the processing provided by the symbol assembler  54 . The first clock input  55  is presented to a third state machine  150 . The third state machine  150  controls a third multiplexer  152 , a four-to-one multiplexer, based on the first clock input  55 . In a first position of the third multiplexer  152 , the content of the first memory cell  112   a  is routed to an input  154   a  of the digital-to-analog converter  56  and the content of the second memory cell  112   b  is routed to an input  154   b  of the digital-to-analog converter  56 . Also in the first position, the content of the third memory cell  112   c  is routed to an input  154   c  of the digital-to-analog converter  56  and the content of the fourth memory cell  112   d  is routed to an input  154   d  of the digital-to-analog converter  56 . In a second position of the third multiplexer  152 , the contents of the sixth memory cell  116   b , the seventh memory cell  116   c , the eighth memory cell  116   d , and the first memory cell  112   a  are routed to the inputs  154   a ,  154   b ,  154   c , and  154   d  respectively of the digital-to-analog converter  56 . In a third position of the third multiplexer  152 , the contents of the seventh memory cell  116   c , the eighth memory cell  116   d , the first memory cell  112   a , and the second memory cell  112   b  are routed to the inputs  154   a ,  154   b ,  154   c , and  154   d  respectively of the digital-to-analog converter  56 . In a fourth position of the third multiplexer  152 , the contents of the eighth memory cell  116   d , the first memory cell  112   a , the second memory cell  112   b , and the third memory cell  112   c  are routed to the inputs  154   a ,  154   b ,  154   c , and  154   d  respectively of the digital-to-analog converter  56 .  
         [0028]     In the preferred embodiment, the first clock input  55  is processed by the third state machine  150  to produce a third mux count which counts the first clock input  55  modulo  165 . This third mux count is the same as the first mux count developed by the first multiplexer  108 . The counts of the third mux count and the first mux count are always in agreement. In an embodiment, a mux count may be developed from the first clock input  55  by a mux clock component (not shown) and distributed to both the first multiplexer  108  and the third multiplexer  152  in lieu of the first multiplexer  108  developing the first mux count and the third multiplexer  152  developing the third mux count. The third state machine  150  may control the third multiplexer to select the positions of the four-to-one multiplexer according to the following table.  
                                                       Select position 1    0 mux count           Select position 4    41 mux count           Select position 3    82 mux count           Select position 2   123 mux count                         For third mux count values not identified in the table, the third multiplexer 152 remains in the previously selected position.             
 
         [0029]     The above described processing provided by the symbol assembler  54  produces the desired  165  sample symbol. The approach for building the  165  sample symbols using the symbol assembler  54  can be readily extended to the case where some of the cyclic prefix samples  14  are non-zero. The symbol assembler  54  may be implemented in an application specific integrated circuit (ASIC) with circuit components such as gates and traces. Additionally, the IFFT  52 , the symbol assembler  54 , the digital-to-analog converter  56 , the up converter  58 , and the amplifier  60  may be implemented in a single ASIC. Note that while the first multiplexer  108 , the second multiplexer  134 , and the third multiplexer  152  are represented as electrical switches in  FIG. 3  and  FIG. 4  above, these multiplexers may be implemented as semiconductor circuit elements. Also note that components may be separated or combined in a single application specific integrated circuit, for example the inverse fast Fourier transform component  52  and other transmitter components may be combined with the symbol assembler component  54  in a single application specific integrated circuit.  
         [0030]     The embodiments described above are directed to 4M+1 sample length symbol systems, where M is an integer and the number of data samples  12  and the number of cyclic prefix samples  14  being multiples of 4. With very minor modification to the control rules of the state machines, the above embodiment may be revised to accommodate alternate 4M+1 sample symbols systems with the number of data samples  12  and the number of cyclic prefix samples  14  being multiples of 4, for example  161  or  169  sample symbols systems. Additionally, the embodiments described above could also be extended, by similar revisions to the control rules of the multiplexer state machines, to accommodate 4M+2 and 4M+3 sample symbol systems with the number of data samples  12  and the number of cyclic prefix samples  14  being multiples of 4. The modifications of the control rules of the multiplexer state machines needed to accommodate these alternate 4M+1, 4M+2, and 4M+3 systems can be readily determined by one of ordinary skill in the art.  
         [0031]     While several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein, but may be modified within the scope of the appended claims along with their full scope of equivalents. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.  
         [0032]     Also, techniques, systems, subsystems and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as directly coupled or communicating with each other may be coupled through some interface or device, such that the items may no longer be considered directly coupled to each other but may still be indirectly coupled and in communication, whether electrically, mechanically, or otherwise with one another. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.