Abstract:
An improved synchronous semiconductor memory device is described in which it is possible to reduce the noise level without compromising the reading speed. The synchronous semiconductor memory device is composed of a memory cell array including a plurality of memory cells for storing data items; a row selection circuit for receiving a row address signal decoded by a row decoder and selecting one row of the memory cell array; a column selection circuit for receiving a column address signal decoded by a column decoder and selecting a plurality of columns of the memory cell array at the same time; a plurality of sense amplifiers for amplifying a plurality of data items which are selected by the row selection circuit and the column selection circuit and are outputted to a plurality of data lines; and a selector element for sequentially outputting the data items which are amplified by the plurality of amplifiers in a time-interleaved manner. Particularly, the plurality of the amplifiers are activated one after another.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
         [0001]    The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei 11-348055 filed in Dec. 7, 1999, in Japan, to which the subject application claims priority under the Paris Convention and the entire contents of which is incorporated by reference herein.  
           [0002]    Also, the entire contents of U.S. patent application Ser. No. 09/268,688 filed on Dec. 7, 1999, in United States of America as assigned to the assignee of the subject application and the entire contents of U.S. patent application Ser. No. 09/299,857 filed on Apr. 26, 1999, in United States of America as assigned to the assignee of the subject application are incorporated by reference herein.  
         BACKGROUND OF THE INVENTION  
         [0003]    1. Field of the Invention  
           [0004]    The present invention relates to a synchronous semiconductor memory device, more particular to a Double Data Rate (DDR) synchronous semiconductor memory device, and more generally to a multiple data rate transmission semiconductor memory device.  
           [0005]    2. Prior Art  
           [0006]    In recent years, it is an important issue in the quest for faster semiconductor systems to increase the data transmission rate between a CPU and a semiconductor memory device. One high speed data transmission design is a design that supports the double data rate mode.  
           [0007]    [0007]FIG. 1 is a block diagram showing a semiconductor memory device in accordance with a conventional technique supporting the double data rate mode. FIG. 3 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device. When an address signal, as illustrated in FIG. 3(B), is input to an address decoder  12  through an address register  11 , the address decoder  12  serves to decode the address signal and output a decoded address signal for selecting a row to a row selection circuit  13 , and a decoded address signal for selecting a column to a column selection circuit  14 . The row selection circuit  13  and the column selection circuit  14  serve to select two memory cells for one I/O terminal in accordance with the address signals as decoded. Two data items are read out from the two memory cells substantially at the same time and input to data input/output circuits  16  and  17  through the data bus ( 1 ) and the data bus ( 2 ).  
           [0008]    A multiplexer  18  serves to select and output one of the data items as outputted from the data input/output circuits  16  and  17  in synchronism with the high and low levels of the clock signal as illustrated in FIG. 3(A).  
           [0009]    Namely, in accordance with the double data rate mode, the data bus structure is designed, unlike a conventional semiconductor memory device, in a dual structure consisting of two equivalent buses inside of a semiconductor memory device in order to read out and write at the doubled speed. Furthermore, the data transmission rate is doubled by alternately reading out of or writing in to the semiconductor memory device through a data input/output unit in synchronism with the high and low levels of the clock signal.  
           [0010]    [0010]FIG. 2 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode. The signals on the data buses ( 1 ) and ( 2 ) of the dual structure are amplified substantially at the same time by means of a sense amplifier  161 , for the signal on data bus ( 1 ), and a sense amplifier  163 , for the signal on data bus ( 2 ), in synchronism with a sense amplifier enabling signal /SAE, as illustrated in FIG. 3(C), in order to transfer the amplified signals to the output register  162 , for the signal on data bus ( 1 ), and the output register  164 , for the signal on data bus ( 2 ). The data items latched by the output register  162  and the output register  164  are input to the multiplexer  18  which is controlled by the clock signal, as illustrated in FIG. 3(A), and alternately output to the I/O terminal in synchronism with the high and low levels of the clock signal.  
           [0011]    In accordance with the conventional semiconductor memory device supporting the double data rate mode as described above, the number of the sense amplifiers activated by the sense amplifier enabling signal /SAE is doubled as compared with that of a semiconductor memory device operating in the normal mode. For example, in the case of  36  I/O terminals,  72  sense amplifiers are activated at the same time. Since a sense amplifier consumes considerable current for the purpose of amplifying a very small differential voltage, a number of the sense amplifiers tend to function as a problematic noise source when they are activated at the same time as described above. This kind of power source noise may cause of malfunction and tends to degrade the sensitivity of the sense amplifier itself, resulting in deterioration in the characteristics thereof. Namely, in accordance with the conventional semiconductor memory device supporting the double data rate mode, there is a problem that substantial noise is generated by simultaneously activating double the number of the sense amplifier as compared with that with the number of sense amplifiers activated during a conventional memory operation.  
         SUMMARY OF THE INVENTION  
         [0012]    The present invention has been developed in order to solve the shortcomings as described heretofore. It is an object of the present invention to provide an improved semiconductor memory device having an output control unit, which makes possible a reduction in the noise level without compromising the reading speed.  
           [0013]    In brief, the above and other objects and advantages of the present invention are provided by a new and improved synchronous semiconductor memory device comprising: a memory cell array consisting of a plurality of memory cells for storing data items; a row selection circuit for receiving a row address signal decoded by a row decoder and selecting one row of the memory cell array; a column selection circuit for receiving a column address signal decoded by a column decoder and selecting first and second columns of the memory cell array at the same time; first and second sense amplifiers for amplifying first and second data items which are selected by the row selection circuit and the column selection circuit and outputted to first and second data lines; and a selector element for sequentially outputting the first and second data items which are amplified by the first and second sense amplifiers in accordance with a time-interleaved manner, wherein the second sense amplifier is activated after the first sense amplifier is activated.  
           [0014]    In a preferred embodiment, further improvement is provided by the semiconductor memory device further comprising a first data storage element for latching a first data item amplified by the first sense amplifier and a second data storage element for latching a second data item amplified by the second sense amplifier.  
           [0015]    Also, in a preferred embodiment, the second sense amplifier is activated by an activation signal which is generated through a first delay circuit by imposing a delay time on the activation signal for activating the first sense amplifier.  
           [0016]    In accordance with this configuration, it is possible to disperse the electric current peak time points and reduce the noise level without compromising the reading speed by deferring activation of the sense amplifier, which is one of the two sense amplifiers for sensing and amplifying data to be outputted, when the clock signal is pulled down while the other sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up. Also, in the sense amplifier serving to sense and amplify data to be outputted when the clock signal is pulled up, the interval between the time point at which the address becomes ready and the time point at which the sense amplifier enabling signal is given is elongated, as compared with the case where the sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up, resulting in a relatively large margin for sensing and therefore resulting in a noise proof structure.  
           [0017]    Furthermore, in a preferred embodiment, the delay time Δt 1  imposed by the first delay circuit is selected to satisfy 0≦Δt 1 ≦Tcy/2 where Tcy is a cycle time of said semiconductor memory device.  
           [0018]    Furthermore, in a preferred embodiment, the size of the transistors of the second sense amplifier is designed to be smaller than that of the transistors of the first sense amplifier. By this configuration, it is possible to reduce the power consumption and the area of the semiconductor chip as occupied.  
           [0019]    In accordance with the configuration, it is possible to make the semiconductor memory device faster and to reduces the power dissipation by deferring activation of the sense amplifier provided for sensing and amplifying data to be outputted when the clock signal is pulled down with a delay time of about a half of the cycle time.  
           [0020]    Furthermore, in a preferred embodiment, the semiconductor memory device further comprises a second delay circuit for deferring the operation of the second data storage element in order to latch the second data item after the first data storage element latches the first data item.  
           [0021]    Furthermore, in a preferred embodiment, the delay time Δt 2  imposed by the second delay circuit is selected to satisfy 0≦Δt 1 ≦Δt 2 ≦Tcy/2 where Δt 1  is the delay time imposed by the first delay circuit and Tcy is a cycle time of the semiconductor memory device.  
           [0022]    In accordance with the configuration, it is possible to make the semiconductor memory device faster and to reduce the power dissipation by deferring activation of the sense amplifier provided for sensing and amplifying data with a delay time of about a half of the cycle time.  
           [0023]    Furthermore, in a preferred embodiment, the first data storage element is composed of a latch circuit which serves to latch for a preceding half period of the cycle time a data item which is obtained after a first control clock signal is pulled up. The second data storage element is composed of a latch circuit, which serves to latch through the cycle time a data item, which is obtained after a second control clock signal is pulled up.  
           [0024]    Furthermore, in a preferred embodiment, the first data storage element is composed of a latch circuit which serves to latch for a preceding half period of cycle time a data item which is obtained after a control clock signal is pulled up. The second data storage element is composed of a latch circuit which serves to latch for a subsequent half period of the cycle time a data item which is obtained after the control clock signal is pulled down.  
           [0025]    Furthermore, in a preferred embodiment, the delay time of the first delay circuit is about a half of the cycle time.  
           [0026]    In accordance with the configuration, the sense amplifiers are designed to be capable of maintaining data for a time period of no shorter than one half of the machine cycle while deferring activation of the sense amplifier provided for sensing and amplifying data to be outputted when the clock signal is pulled down by one half of the machine cycle., As a result, it is possible to reduce the area of the semiconductor chip and to make the semiconductor memory device faster and to reduce the power dissipation.  
           [0027]    Furthermore, in a preferred embodiment, the selector element serves to selectively output the first and second data items in synchronism with the rising edge and the falling edge of the system clock.  
           [0028]    In accordance with another aspect of the present invention, a synchronous semiconductor memory device comprising: a memory cell array including a plurality of memory cells for storing data items; first and second sense amplifiers connected in parallel to one output terminal for amplifying the data items stored in the plurality of memory cells; a selector element for selectively outputting the data items as outputted from the first and second sense amplifiers; and a first delay circuit for displacing the time points at which the first and second sense amplifiers are activated from one another, the first and second sense amplifiers are controlled to be capable of maintaining output data for a time period no shorter than a half of the cycle time.  
           [0029]    In accordance with a further aspect of the present invention, a synchronous semiconductor memory device comprising: a memory cell array including a plurality of memory cells for storing data items; a row selection circuit for receiving a row address signal decoded by a row decoder and selecting one row of the memory cell array; a column selection circuit for receiving a column address signal decoded by a column decoder and selecting a plurality of columns of the memory cell array at the same time; a plurality of sense amplifiers for amplifying a plurality of data items which are selected by the row selection circuit and the column selection circuit and outputted to a plurality of data lines; and a selector element for sequentially outputting the data items one after another which are amplified by means of the plurality of the amplifiers in a time-interleaved manner, wherein the plurality of the amplifiers are activated one after another.  
           [0030]    In accordance with this configuration, it is also possible to disperse the electric current peak time points and reduce the noise level without compromising the reading speed by deferring activation of the sense amplifier which is one of the two sense amplifiers for sensing and amplifying data to be outputted when the clock signal is pulled down while the other sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up. Also, in the sense amplifier serving to sense and amplify data to be outputted when the clock signal is pulled up, the interval between the time point at which the address becomes ready and the time point at which the sense amplifier enabling signal is given is elongated, as compared with the case where the sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up, resulting in a relatively large margin for sensing and therefore resulting in a noise proof structure.  
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0031]    The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of preferred embodiments taken in conjunction with the accompanying drawings, wherein:  
         [0032]    [0032]FIG. 1 is a block diagram showing a semiconductor memory device in accordance with a conventional technique supporting the double data rate mode.  
         [0033]    [0033]FIG. 2 is a block diagram showing the output control unit of the prior art semiconductor memory device supporting the double data rate mode.  
         [0034]    [0034]FIG. 3 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the conventional semiconductor memory device.  
         [0035]    [0035]FIG. 4 is a block diagram showing a semiconductor memory device supporting the double data rate mode in accordance with a first embodiment of the present invention.  
         [0036]    [0036]FIG. 5 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with the first embodiment of the present invention.  
         [0037]    [0037]FIG. 6 is a circuit diagram showing the configuration inclusive of exemplary circuits of the sense amplifiers and the delay circuit as illustrated in FIG. 5.  
         [0038]    [0038]FIG. 7 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device provided with the output control unit as illustrated in FIG. 6.  
         [0039]    [0039]FIG. 8 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with a second embodiment of the present invention.  
         [0040]    [0040]FIG. 9 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with the second embodiment of the present invention.  
         [0041]    [0041]FIG. 10 is a circuit diagram showing the configuration inclusive of an exemplary circuit of the output registers in accordance with the second embodiment of the present invention.  
         [0042]    [0042]FIG. 11 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with the second embodiment of the present invention.  
         [0043]    [0043]FIG. 12 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device provided with the output control unit as illustrated in FIG. 11.  
         [0044]    [0044]FIG. 13 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with a third embodiment of the present invention.  
         [0045]    [0045]FIG. 14 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device provided with the output control unit as illustrated in FIG. 13.  
         [0046]    [0046]FIG. 15 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with a fourth embodiment of the present invention.  
         [0047]    [0047]FIG. 16 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device provided with the output control unit as illustrated in FIG. 15.  
     
    
     DETAILED DESCRIPTION OF EMBODIMENTS  
       [0048]    Several preferred embodiments of the invention will now be described in conjunction with the accompanied drawings. FIG. 4 is a block diagram showing a semiconductor memory device supporting the double data rate mode in accordance with a first embodiment of the present invention.  
         [0049]    The semiconductor memory device is composed of a memory cell array  5  having a number of memory cells, an address register  1 , an address decoder  2  for receiving and decoding an address as latched by the address register  1 , a row selection circuit  3  receiving from the address decoder  2  a row address signal for selecting a row of the memory cell array  5 , a column selection circuit  4  receiving from the address decoder  2  a column address signal for selecting a column of the memory cell array  5 , a data bus  21 , a data bus  22 , an output control unit  6  and a multiplexer  8 . The row selection circuit  3  and the column selection circuit  4  serve to select two memory cells for one I/O terminal in accordance with the address signals as decoded.  
         [0050]    The row selection circuit  3  serves to select one row of the memory cell array  5  in accordance with the row address signal decoded by means of the address decoder  2 . On the other hand, the column selection circuit  4  serves to select two columns of the memory cell array  5  at the same time in accordance with the column address signal decoded by means of the address decoder  2 . Two data items are read out from the two memory cells substantially at the same time and input to data input/output circuit  6  through the data bus  21  and the data bus  22 . A multiplexer  18  serves to select and output one of the data items as outputted from the data input/output circuits  16  and  17  in synchronism with the high and low levels of the clock signal as illustrated in FIG. 7(A).  
         [0051]    In accordance with the double data rate mode, the data bus structure is designed, unlike a conventional semiconductor memory device, in a dual structure consisting of two equivalent buses inside of a semiconductor memory device in order to read out and write at the doubled speed. Furthermore, the data transmission rate is doubled by alternately reading out or writing in the semiconductor memory device through the output control unit  6  and the multiplexer  8  in synchronism with the high and low levels of the clock signal.  
         [0052]    [0052]FIG. 5 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with the first embodiment of the present invention. The output control unit in accordance with this embodiment of the present invention is composed of two data transmission paths respectively through a sense amplifier  61  and an output register  62  and through a sense amplifier  63  and an output register  64 , the multiplexer  8  for sequentially selecting and outputting one of the data items as latched by the output register  62  and the output register  64 , and a delay circuit  19  for delaying a sense amplifier enabling signal which functions to activate the sense amplifier  63 . The data items read out from the memory cells (not shown in the figure) are transferred to the sense amplifier  61  and the sense amplifier  63  through the data bus  21  and the data bus  22 , respectively.  
         [0053]    The sense amplifier  61  is activated by directly receiving the sense amplifier enabling signal /SAE and serves to sense and amplify a data item outputted when the clock signal is pulled up while the sense amplifier  63  is activated by receiving the sense amplifier enabling signal /SAE as delayed through the delay circuit  19  and serves to sense and amplify a data item outputted when the clock signal is pulled down.  
         [0054]    [0054]FIG. 6 is a circuit diagram showing the configuration inclusive of exemplary circuits of the sense amplifiers and the delay circuit as illustrated in FIG. 5. In the figure, each sense amplifier is composed of a latch type sense amplifier while the delay circuit is composed of an inverter chain.  
         [0055]    Namely, each sense amplifier is composed of PMOS transistors T 1 , T 2  and T 3  and NMOS transistors T 4  and T 5 . The gate terminals of the PMOS transistor T 2  and the NMOS transistor T 4  are connected to the data bus  21  while the gate terminals of the PMOS transistor T 3  and the NMOS transistor T 5  are connected to the data bus  22 . The delay circuit is composed of the inverter chain having inverters  191  and  192 , which are connected in series.  
         [0056]    [0056]FIG. 7 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device provided with the output control unit as illustrated in FIG. 6. FIG. 7(A) shows the waveform of the clock signal (CK) for use in the output circuit; FIG. 7(B) shows the waveform of the sense amplifier enabling signal /SAE 1 ; FIG. 7(C) shows the waveform of the sense amplifier enabling signal /SAE 2 ; FIG. 7(D) shows the waveform of the output signal of the sense amplifier  61 ; FIG. 7(E) shows the waveform of the output signal of the sense amplifier  63 ; FIG. 7(F) shows the waveform of the current flowing through the sense amplifier  61 ; and FIG. 7(G) shows the waveform of the current flowing through the sense amplifier  62 .  
         [0057]    The latch type sense amplifier generates a through current when activated by means of the sense amplifier enabling signal /SAE. The output control unit as described above serves to activate the sense amplifier  61  by means of the sense amplifier enabling signal /SAE 1  and then, after the delay (Δt 1 ) implemented by means of the inverter chain of the delay circuit  19 , serves to activate the sense amplifier  63  by means of the sense amplifier enabling signal /SAE 2 . Accordingly, the time of the current peak of the sense amplifier  61  does not coincide with the time of the current peak of the sense amplifier  63  so that it is possible to disperse the current peak time points during operation.  
         [0058]    The output signal of the sense amplifier  63  is therefore delayed as compared with that of the sense amplifier  61 . However, this never imposes a bottleneck limiting the operation speed of the memory because there is no problem as long as the data item of the sense amplifier  63  becomes ready only during the later half of the subsequent cycle of the clock signal, i.e., when the clock signal is pulled down. It is required that the delay time Δt 1  satisfies 0≦Δt 1 ≦Tcy/2 to delay the data item of the sense amplifier  63  until the later half of the subsequent cycle.  
         [0059]    Also, the interval between the time point at which the address becomes ready and the time point at which the sense amplifier enabling signal is given is elongated in the case of the sense amplifier  63 , as compared with the case of the sense amplifier  61 , so that the differential input level to the sense amplifier  63  is relatively increased when activated, resulting in a relatively large margin for sensing and therefore resulting in a noise proof structure.  
         [0060]    [0060]FIG. 10 is a circuit diagram showing the configuration, inclusive of an exemplary circuit, of the output registers  62  and  64  in accordance with the second embodiment of the present invention. The output register is composed of a master latch and a slave latch. Each latch is composed of clocked inverters  41  and  42  and an inverter  43 .  
         [0061]    In accordance with the present embodiment, when two data items are read out from the memory cells in the double data rate mode, the current peak time points of the sense amplifier  61  and the sense amplifier  63  can be displaced from each other as illustrated in FIG. 7(F) and FIG. 7(G) by displacing the timing of activation of the sense amplifier  63  from that of the sense amplifier  61 . In this case, since the displacement is adjusted to satisfy the relationship of 0≦Δt 1 ≦Tcy/2, the noise level can be reduced without compromising the reading speed.  
         [0062]    Meanwhile, as illustrated in FIG. 7(D) and FIG. 7(E), the input level to the sense amplifier  63  when the sensing/amplifying operation thereof is initiated is higher than that to the sense amplifier  61  so that it is possible to reduce the area of the semiconductor chip as occupied by selecting the size of the transistors of the sense amplifier  63  to be smaller than that of the transistors of the sense amplifier  61 .  
         [0063]    [0063]FIG. 8 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with a second embodiment of the present invention. Also in FIG. 8, like reference numbers indicate identical or functionally similar elements in the drawing as the output control unit as illustrated in FIG. 6 and, therefore redundant explanation is not repeated.  
         [0064]    For the output control unit as illustrated in FIG. 6, the delay circuit  19  is always connected to the data bus  22  and is not connected to the data bus  21 . In this case, however, some inconvenience may occur when data stored in an odd address is accessed while the data bus  21  is connected to the memory cells assigned to even addresses and the data bus  22  is connected to the memory cells assigned to odd addresses as given. Namely, when an odd address is given, some technical handling may be required, for example, insertion of a pause and neglect the leading data item of the even address which is input after decrementing the odd address.  
         [0065]    In the case of the semiconductor memory device in accordance with the second embodiment of the present invention, a switch circuit is inserted to the output control unit thereof for switching even/odd addresses as illustrated in FIG. 8. As illustrated in the figure, the sense amplifier  61  is connected to the data bus  21  through an NMOS transistor T 6  and an NMOS transistor T 7  which constitute a transfer gate. Also, the sense amplifier  61  is connected to the data bus  22  through an NMOS transistor T 8  and an NMOS transistor T 9  which constitute a transfer gate.  
         [0066]    On the other hand, the sense amplifier  63  is connected to the data bus through the NMOS transistor T 6  and the NMOS transistor T 7  which constitute a transfer gate. Also, the sense amplifier  63  is connected to the data bus  22  through the NMOS transistor T 8  and the NMOS transistor T 9  which constitute a transfer gate.  
         [0067]    The data item with an odd address can be read out by fixing the data lines b and c to the low level and the data lines a and d to the high level and connecting the upper sense amplifier  61  to the data bus  21  and the lower sense amplifier  63  to the data bus  22 , respectively. Accordingly, in this case, the effective configuration of the circuit is equivalent to the circuit as illustrated in FIG. 5.  
         [0068]    Also, the data item with an even address can be read out by fixing the data lines a and d to the low level and the data lines b and c to the high level and connecting the upper sense amplifier  61  to the data bus  22  and the lower sense amplifier  63  to the data bus  21  respectively. Accordingly, in this case, the effective configuration of the circuit is equivalent to the circuit as illustrated in FIG. 9. In the figure, the connection relationship of the sense amplifier  61 , the sense amplifier  63 , the data bus  21  and the data bus  22  is opposite to that as illustrated in FIG. 5.  
         [0069]    [0069]FIG. 7 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device with the signal D_rise as the output signal of the sense amplifier  61  and the signal D_fall as the output signal of the sense amplifier  63 .  
         [0070]    The configuration as illustrated in FIG. 8 is particularly effective when the semiconductor memory device in accordance with the present invention is actually implemented. Namely, it is realized by providing the switch circuit so that one of the sense amplifiers, i.e., the sense amplifier  61  always serves to sense and amplify the data item to be output when the clock signal is pulled up while the other sense amplifier, i.e., the sense amplifier  63  always serves to sense and amplify the data item to be output when the clock signal is pulled down. Accordingly, the delay circuit can be fixedly connected to the other sense amplifier, i.e., the sense amplifier  63  senses and amplifies the data item to be output when the clock signal is pulled down.  
         [0071]    [0071]FIG. 11 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with the second embodiment of the present invention. Also in FIG. 11, like reference numbers indicate identical or functionally similar elements in the drawing as the output control unit as illustrated in FIG. 5 and, therefore redundant explanation is not repeated.  
         [0072]    The output register  65  connected to the sense amplifier  61  is composed only of a master latch  1 . This is because data need not be maintained when the clock signal is pulled down. However, there is no problem even if a slave latch is provided for some reason in manufacturing processes.  
         [0073]    On the other hand, the output register  66  connected to the sense amplifier  63  is composed of a master latch and a slave latch. In this case, the clock signal (CKM 2 ) for driving the master latch of the output register  66  is given a delay Δt 2  by means of the delay circuit  20  as compared with the clock signal (CKM 1 ) for driving the master latch of the output register  65 .  
         [0074]    By this control configuration, the output signal from the output register  66  is delayed as compared with the output signal from the output register  65 . However, this never impose a bottleneck limiting the operation speed of the memory because there is no problem as long as the data item as output from the output register  66  becomes ready when the later half of the subsequent cycle of the clock signal, i.e., when the clock signal is pulled down. It is required that the delay time Δt 1  satisfy 0≦Δt 1 ≦Tcy/2 to delay the data item as output from the output register  66  until the later half of the subsequent cycle.  
         [0075]    [0075]FIG. 12 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device provided with the output control unit as illustrated in FIG. 11. FIG. 12(A) shows the waveform of the clock signal (CK) for use in the output control unit; FIG. 12(B) shows the waveform of the sense amplifier enabling signal /SAE 1 ; FIG. 12(C) shows the waveform of the sense amplifier enabling signal /SAE 2 ; FIG. 12(D) shows the waveform of the output signal of the sense amplifier  61 ; FIG.  12 (E) shows the waveform of the output signal of the sense amplifier  63 ; FIG. 12(F) shows the waveform of the clock signal for driving the master latch of the output register  65 ; FIG. 12(G) shows the waveform of the current the clock signal for driving the master latch of the output register  66 ; FIG. 12(H) shows the waveform of the current the clock signal for driving the slave latch of the output register  66 ; FIG. 12(I) shows the output data of the output register  65 ; FIG. 12(J) shows the output data of the output register  66 ; and FIG. 12(K) shows the output data of the multiplexer  8 .  
         [0076]    By providing the delay circuit  20 , and thereby providing a delay between the clock signal CKM 1  and CKM 2  for driving the master latches, to secure a sufficient margin for latching data after output data becomes ready at the output terminals of the sense amplifier  61  and the sense amplifier  63 , which are connected to the input terminals of the output register  65  and the output register  66 , i.e., to provide a sufficient time period between the sense amplifier enabling signal /SAE 1  and the clock signal CKM 1  and also a sufficient time period between the sense amplifier enabling signal /SAE 2  and the clock signal CKM 2 . The data transmission from the sense amplifier  63  to the output register  65  can be performed with a sufficient marginal time even with delay times of Δt 1  and Δt 2 , as compared with the data transmission from the sense amplifier  61  to the output register  66 , by adjusting the delay times of the delay circuit  19  and the delay circuit  20  to satisfy 
         0≦Δt 1 ≦Δt 2 ≦Tcy/2 
         [0077]    [0077]FIG. 13 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with a third embodiment of the present invention. Also in FIG. 11, like reference numbers indicate identical or functionally similar elements in the drawing as the output control unit as illustrated in FIG. 5 and, therefore redundant explanation is not repeated.  
         [0078]    In accordance with this embodiment of the present invention, the differential activation time between the sense amplifier enabling signals /SAE 1  and /SAE 2  is extended to about a half of the cycle time, i.e., Tcy/2. In this case, the output register  68  is no longer responsible for maintaining data while the clock signal is pulled up so that the master latch of the output register  68  can be dispensed with in the same manner as the slave latch of the output register  67  is dispensed with, since the output register  67  is not responsible for maintaining data while the clock signal is pulled down. It is therefore possible to make the semiconductor memory device faster and to reduce the power dissipation.  
         [0079]    [0079]FIG. 14 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device provided with the output control unit as illustrated in FIG. 13. FIG. 14(A) shows the waveform of the clock signal (CK) for use in the output control unit; FIG. 14(B) shows the waveform of the sense amplifier enabling signal /SAE 1 ; FIG. 14(C) shows the waveform of the sense amplifier enabling signal /SAE 2 ; FIG. 14(D) shows the waveform of the output signal of the sense amplifier  61 ; FIG. 14(E) shows the waveform of the output signal of the sense amplifier  63 ; FIG. 14(F) shows the waveform of the clock signal for driving the master latch of the output register  65 ; FIG. 14(G) shows the waveform of the current the clock signal for driving the slave latch of the output register  66 ; FIG. 14(H) shows the output data of the output register  65 ; FIG. 14(I) shows the output data of the output register  66 ; and FIG. 14(J) shows the output data of the multiplexer  8 .  
         [0080]    In this case, the period between the amplification by the sense amplifier  63  and the reception by the output register  68 , i.e., the period between the sense amplifier enabling signal /SAE 2  and the clock signal CKS corresponds to the period between amplification by the sense amplifier  61  and the reception by the output register  67 , i.e., the period between the sense amplifier enabling signal /SAE 1  and the clock signal CKM.  
         [0081]    [0081]FIG. 15 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode in accordance with a fourth embodiment of the present invention. Also in FIG. 15, like reference numbers indicate identical or functionally similar elements in the drawing as the output control unit as illustrated in FIG. 5 and, therefore redundant explanation is not repeated. In the case where the sense amplifier  61  and the sense amplifier  62  are designed to maintain data for a time period no shorter than a half of the machine cycle, the register circuit can be dispensed with as illustrated in FIG. 15.  
         [0082]    [0082]FIG. 16 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device provided with the output control unit as illustrated in FIG. 15. FIG. 16(A) shows the waveform of the clock: signal (CK) for use in the output circuit; FIG. 16(B) shows the waveform of the sense amplifier enabling signal /SAE 1 ; FIG. 16(C) shows the waveform of the sense amplifier enabling signal /SAE 2 ; FIG. 16(D) shows the waveform of the output signal of the sense amplifier  61 ; FIG. 16(E) shows the waveform of the output signal of the sense amplifier  63 ; and FIG. 16(F) shows the output data of the multiplexer  8 .  
         [0083]    The sense amplifier enabling signals /SAE 1  and /SAE 2  are displaced from each other a distance of about Tcy/2 so that the sense amplifiers  61  and  63  are can maintain data for a half of the cycle time Tcy, from the sense amplifier enabling signal, respectively, to make the semiconductor memory device faster and to reduce the power dissipation.  
         [0084]    As explained above in detail, in accordance with the present invention, it is possible to disperse the electric current peak time points and reduce the noise level without compromising the reading speed by deferring activation of the sense amplifier, which is one of the two sense amplifiers for sensing and amplifying data to be outputted when the clock signal is pulled down, while the other sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up. Also, in the sense amplifier which senses and amplify data to be outputted when the clock signal is pulled up, the interval between when the address becomes ready and the time point when the sense amplifier enabling signal is given is elongated, as compared with the case with the sense amplifier  61 , resulting in a relatively large margin for sensing and therefore resulting in a noise proof structure.  
         [0085]    Furthermore, it is possible to reduce the power consumption and the area of the semiconductor chip by designing the size of the transistors of the sense amplifier for sensing and amplifying data to be outputted when the clock signal is pulled down to be smaller than that of the transistors of the sense amplifier for sensing and amplifying data to be outputted when the clock signal is pulled up.  
         [0086]    The design of one of the output registers can be simplified by deferring activation of the sense amplifier provided for sensing and amplifying data to be outputted when the clock signal is pulled down with a delay time Δt 1  of about the cycle time Tcy, satisfying the equation of 0≦Δt 1 ≦Tcy/2, so that it is possible to make the semiconductor memory device faster and to reduces the power dissipation.  
         [0087]    Also, it is possible to make the semiconductor memory device faster and to reduces the power dissipation by deferring activation of the sense amplifier provided for sensing and amplifying data to be outputted when the clock signal is pulled down with a delay time of about a half of the cycle time.  
         [0088]    Furthermore, the sense amplifier  61  and the sense amplifier  62  are designed to maintain data for a time period of no shorter than a half of the machine cycle while deferring activation of the sense amplifier provided for sensing and amplifying data to be outputted when the clock signal is pulled down by a half of the machine cycle, so that it is possible to reduce the area of the semiconductor chip and to make the semiconductor memory device faster and to reduce the power dissipation.  
         [0089]    The foregoing description of the preferred embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen in order to explain most clearly the principles of the invention and its practical application thereby to enable others in the art to utilize most effectively the invention in various embodiments and with various modifications as are suited to the particular use contemplated.