Abstract:
A correlator comprises a plurality of phase rotators, a plurality of combining modules, a plurality of computation modules, and a selection module. The plurality of phase rotators selectively modifies phase for each chip of a first subset of chips by one of M phase offsets, where an incoming symbol comprises the first subset and a second subset of chips, and where M is an integer greater than one. The plurality of combining modules each combine a chip of the first subset with a respective chip of the second subset to generate an output. The plurality of computation modules includes inputs that communicate with the outputs of the plurality of combining modules and produces a plurality of correlator output signals. The selection module chooses one of the plurality of correlator output signals based upon a metric.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is a continuation of U.S. Ser. No. 10/252,138, filed on Sep. 19, 2002, which application claims priority benefit of U.S. Provisional Patent Application Ser. No. 60/368,865, filed on Mar. 29, 2002, and is a continuation-in-part of U.S. patent application Ser. No. 10/092,971, filed on Mar. 5, 2002, which in turn claims priority benefit of U.S. Provisional Patent Application Ser. No. 60/277,258, filed on Mar. 21, 2001, the contents of each are collectively incorporated herein by reference. 

   BACKGROUND 
   1. Technical Field 
   This invention relates generally to wireless local area networks, and more particularly, to wireless local area networks employing physical layer modulation and demodulation in accordance with the IEEE Standard 802.11b-1999 Supplement (“IEEE802.11b”) to the ANSI/IEEE Standard 802.11, 1999 edition. 
   2. Related Art 
   There are several known techniques for transmitting digital waveforms across wireless networks. One known technique is direct sequence spread spectrum (DSSS), which allows for high-rate modulation using complementary codes known as “spreading codes.” The use of spreading codes enables the bandwidth occupied by a DSSS waveform to be increased or “spread.” As a consequence of this bandwidth spreading (and despreading), DSSS systems are able to realize processing gains compared to systems using other transmission techniques. 
   Complementary Code Keying (CCK) is the modulation technique chosen for IEEE 802.11b high rate modes (5.5 Mbps mode and 11 Mbps mode). For example, a CCK modulated symbol c may be expressed as:
 
 c={e   j(φ     1     +φ     2     +φ     3     +φ     4     )   ,e   j(φ     2     +φ     3     +φ     4     )   ,e   j(φ     1     +φ     2     +φ     4     )   ,−e   j(φ     1     +φis 4   )   ,e   j(φ     1     +φ     2     +φ     3     )   ,e   j(φ     1     +φ     3     )   ,−e   j(φ     1     +φ     2     )   ,e   jφ     1   }
 
where (φ 1 , φ 2 , φ 3 , and φ 4  are suitable phase values as described in more detail below.
 
   For clarity of description, the chips in equation (1) are hereinafter referenced from left to right as c 0 -c 7 , respectively. In CCK modulation, the 4th and 7th chips, namely c 3  and c 6 , are rotated 180° to optimize the correlation properties and reduce DC offset. 
   When operating in the 5.5 Mbps CCK mode (4 bits/symbol), the various phase values φ 1 , φ 2 , φ 3  and φ 4  employed in equation (1) are defined as shown below in equation (2). 
                 {             φ   1     =     DQPSK   ⁢           ⁢   encode   ⁢           ⁢   with   ⁢           ⁢     (       d   ⁢           ⁢   0     ,     d   ⁢           ⁢   1       )     ⁢           ⁢   and   ⁢           ⁢     even   /   odd                     φ   2     =       (       d   ⁢           ⁢   2   *   2     +   1     )     *     π   /   2                     φ   3     =   0                 φ   4     =     d   ⁢           ⁢   3   *   2   *     π   /   2                       (   2   )               
where d 0 , d 1 , d 2  and d 3  are the 4 bits to be modulated.
 
   When operating in the 11 Mbps CCK mode (8 bits/symbol), the various phase values are defined as shown below in equation (3). 
                 {             φ   1     =     DQPSK   ⁢           ⁢   encode   ⁢           ⁢   with   ⁢           ⁢     (       d   ⁢           ⁢   0     ,     d   ⁢           ⁢   1       )     ⁢           ⁢   and   ⁢           ⁢     even   /   odd                     φ   2     =       (       d   ⁢           ⁢   2   *   2     +     d   ⁢           ⁢   3       )     *     π   /   2                     φ   3     =       (       d   ⁢           ⁢   4   *   2     +     d   ⁢           ⁢   5       )     *     π   /   2                     φ   4     =       (       d   ⁢           ⁢   6   *   2     +     d   ⁢           ⁢   7       )     *     π   /   2                       (   3   )               
where d 0 , d 1 , . . . , d 6  and d 7  are the 8 bits to be modulated.
 
   When demodulating, the d 2 -d 3  bits (5.5 Mbps mode) or the d 2 -d 7  bits (11 Mbps mode) will be decoded by the CCK correlator, and d 0 -d 1  by DQPSK demodulation. 
   The published CCK 64-vector correlation can be written as: 
           R   =           C   T     ⁡     [           ⅇ     j   ⁢           ⁢     (       φ   2     +     φ   3     +     φ   4       )                   ⅇ     j   ⁢           ⁢     (       φ   3     +     φ   4       )                   ⅇ     j   ⁢           ⁢     (       φ   2     +     φ   4       )                   ⅇ     j   ⁢           ⁢     φ   4                   ⅇ     j   ⁢           ⁢     (       φ   2     +     φ   3       )                   ⅇ     j   ⁢           ⁢     φ   3                   ⅇ     j   ⁢           ⁢     φ   2                 1         ]       *     =                 C   T     ⁡     [           ⅇ     j   ⁢           ⁢     φ   2                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   2                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   2                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   2                                                     1         ]       *     ⁡     [           ⅇ     j   ⁢           ⁢     φ   3                             1                                     ⅇ     j   ⁢           ⁢     φ   3                             1         ]       *     ⁡     [           ⅇ     j   ⁢           ⁢     φ   4                 1         ]       *             
where C T =(c 0 , c 1 , c 2 , −c 3 , c 4 , c 5 , −c 6 , c 7 ) (In-phase and Quadrature signal).
 
     FIG. 1  depicts a CCK correlator architecture of the prior art. Only one phase or vector is shown for each of the φ values. It should be appreciated that the CCK correlator architecture depicted in  FIG. 1  is capable of operating at either of 5.5 Mbps mode or 11 Mbps mode. As such, the actual hardware implementation and the time cost for both 5.5 Mbps and 11 Mbps modulation are the same, and therefore the power consumption is the same. In 5.5 Mbps modulation mode, φ 3  is always equal to zero (see equation (2) above). Because the amount of real vector used for 5.5 Mbps modulation is less than the amount used for 11 Mbps modulation, the prior correlator wastes substantial power when operating at 5.5 Mbps and consumes as much power as is required for 11 Mbps operation. 
   Further, it has been proposed to further enhance CCK symbol modulation processing gain through decision feedback analysis based on e.g. previous symbol information and/or predicted subsymbol regeneration. Therefore, it would be desirable to implement power saving correlation techniques which could conveniently include decision-directed equalization using selective subsymbol prediction and regeneration for improving overall symbol correlation and demodulation. 
   SUMMARY 
   The present invention relates to a method and apparatus for a CCK correlator employing a reduced power consumption and achieves faster performance in the 5.5 Mbps mode of operation as compared with the 11 Mbps mode of operation, and can selectively predict and regenerate subsymbol information believed useful in e.g. decision feedback and noise error correction operations. 
   Consistent with an aspect of the present invention, a symbol prediction apparatus is disclosed which includes a correlator having an input to accept a first set of modulated symbol chips in a first order to generate a first set of correlator output signals based on the first plurality of modulated symbol chips, a data cross bar to selectively feed a second set of modulated symbol chips in a second order to the correlator based on one of a plurality of predicted subsymbol types, a windowing unit to selectively generate a subset of the set of correlator output signals based on the predicted subsymbol type, and a maximum picker unit to identify a maximum-valued correlator output signal from one of the set of correlator output signals and the subset of correlator output signals, wherein the maximum-valued correlator output signal corresponds to a predicted subsymbol of the predicted subsymbol type. 
   Other disclosed aspects of the present invention include a corresponding symbol prediction method, as well as wireless communications receiver and transceiver configurations which incorporate such selective sub symbol prediction and apparatus. 
   Additional aspects and advantages of this invention will be apparent from the following detailed description of certain embodiments thereof, which proceeds with reference to the accompanying drawings, in which like reference numerals indicate like parts. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a single vector CCK correlator of the prior art; 
       FIG. 2  shows one exemplary operating environment of the present invention; 
       FIG. 3  shows one exemplary embodiment of a data transmitter used in accordance with the present invention; 
       FIG. 4  shows one exemplary data structure used in accordance with the principles of the present invention; 
       FIG. 5  shows an exemplary data encoding structure for use in accordance with the principles of the present invention; 
       FIG. 6  shows one exemplary embodiment of a data receiver for use in accordance with the principles of the present invention; 
       FIG. 7  shows data decoding structure for use in accordance with the principles of the present invention; 
       FIG. 8  shows a single-vector CCK correlator for use in accordance with one exemplary embodiment of the present invention; 
       FIG. 9  shows a 64-vector CCK correlator for use in accordance with one exemplary embodiment of the present invention; 
       FIG. 10  shows structure for use in demodulating to recover at least some original data bits according to one exemplary embodiment of the present invention; 
       FIG. 11  shows a flow diagram depicting an exemplary transmission portion of one exemplary embodiment of the present invention; 
       FIG. 12  shows a flow diagram depicting an exemplary encoding of data bits according to one exemplary embodiment of the present invention; 
       FIG. 13  shows a flow diagram depicting an exemplary receiving portion of one exemplary embodiment of the present invention; 
       FIG. 14  shows a flow diagram depicting one exemplary approach to decoding data bits according to the principles of the present invention; 
       FIG. 15  shows a 64-vector correlation unit for use in accordance with another embodiment of the invention; 
       FIG. 16  depicts a symbol demodulation system including the including the correlation unit shown in  FIG. 15 ; and 
       FIG. 17  illustrates a flowchart depicting subsymbol prediction and regeneration consistent with the embodiments shown in  FIGS. 15 and 16 . 
   

   DETAILED DESCRIPTION 
   An exemplary operating environment for the illustrated system of the present invention is depicted in  FIG. 2 . Specifically,  FIG. 2  depicts a wireless local area network  100  according to the present invention. A transmitter  102 , an antenna  104 , a receiver  106  and an antenna  108  are depicted. The transmitter  102  provides the data that is to be transmitted across antenna  104  to the receiver  106 . The receiver  106  receives the transmitted data via antenna  108 . 
     FIG. 3  depicts the transmitter  102  ( FIG. 2 ) according to one embodiment of the present invention. Referring to  FIG. 3 , a computer interface  200 , a symbol grouping module  202 , a data modulator  204 , a radio frequency modulator  206 , a radio frequency signal  208 , a radio frequency amplifier  210 , and an antenna  212  are shown. The computer interface  200  provides a stream of binary data which represents information to be modulated and transmitted across the wireless local area network  100  ( FIG. 2 ). The symbol grouping module  202  receives the stream of binary data from the computer interface  200  and divides the stream into a series of data words, with each data word representing a symbol value. The symbol values or data words from the grouping module  202  are then passed to the data modulator  204 . The data modulator  204  modulates the data words into CCK modulated data that is compliant with the IEEE802.11b specifications. The CCK modulated data is then directed to the radio frequency (RF) modulator  206  which converts the CCK modulated data into a radio frequency signal. The radio frequency signal  208  is amplified by the radio frequency amplifier  210  such that it may be transmitted by antenna  212  as packets of data  214  (represented by an arrow in  FIG. 3 ). 
   Referring to  FIG. 4 , the packets of data  214  that are transmitted by the antenna  212  contain a preamble  402 , a header  404 , an operating mode indicator  405 , and encoded data  406 . The operating mode indicator  405 , contained within the header  404 , is an indication of whether the operating mode is DSSS 1 Mbps, DSSS 2 Mbps, CCK 5.5 Mbps or CCK 11 Mbps mode. 
   Encoding Data 
   Referring to  FIG. 5 , a CCK encoder  500  according to one exemplary embodiment of the present invention is depicted. The CCK encoder  500  includes a differential quadrature phase shift key (DQPSK) modulator  502  and a CCK correlator  504 . The computer interface  200  ( FIG. 3 ) outputs data bits d 0 -d 3  (in 5.5 Mbps mode) or d 0 -d 7  (in 11 Mbps mode). Regardless of whether the encoder  500  is operating in 5.5 Mbps mode or 11 Mbps mode, d 0  and d 1  are applied to the DQPSK modulator  502  to encode the phase parameter φ 1 . DQPSK is well-known in the art. The phase parameter φ 1  is determined based on the data bits d 0  and d 1  according to the table below: 
   
     
       
             
             
             
           
         
             
                 
             
             
                 
               Phase 
               Phase 
             
             
               (d1, d0) 
               (even symbols) 
               (odd symbols) 
             
             
                 
             
           
           
             
               00 
               0 
               π 
             
             
               01 
               π/2 
               −π/2 
             
             
               10 
               −π/2 
               π/2 
             
             
               11 
               π 
               0 
             
             
                 
             
           
        
       
     
   
   Data bits d 2 -d 3  (5.5 Mbps) or d 2 -d 7  (11 Mbps) are applied to the CCK correlator  504 . The CCK correlator  504  receives the appropriate data bits (d 2 -d 3  or d 2 -d 7 ) and encodes the phase parameters φ 2 , φ 3  and φ 4  according to equation (2) or equation (3), respectively. 
   An even/odd rotator (not shown) may be utilized in the encoder  500  to output a signal that toggles between two different states. For even symbols, no rotation is applied to the phase value. For odd symbols, an additional rotation of π is applied to the phase value. By additionally encoding data with such a signal, effects of DC offset are reduced because any encoded symbol will have been encoded with a different odd/even status from the immediately preceding and following encoded symbols. 
   After the data bits have been applied to the CCK encoder  500 , all of the phase parameters φ 1 , φ 2 , φ 3  and φ 4  will have been encoded. With all of the phase parameters thus being known, the phase parameter values may then be substituted into equation (1) to yield the eight-chip symbol. It should be noted that the symbol will contain eight complex chips, regardless of whether four data bits (5.5 Mbps) or eight data bits (11 Mbps) are used. The eight-chip symbol is then RF modulated by RF modulator  206 , amplified by RF amplifier  210 , and transmitted from antenna  212  ( FIG. 3 ). 
   Encoding Example 
   As an example, if the CCK modulator  500  is operating in 5.5 Mbps mode and receives four data bits d 3 -d 0  (MSB to LSB) {1, 0, 0, 1}, the output of the DQPSK modulator  502  will be π/2, and therefore φ 1 =π/2. φ 2  is equal to (d 2 *2+1)*π/2 or (0*2+1)*π/2 which equals π/2. φ 3  is defined as 0 in 5.5 Mbps mode. Finally, φ 4  is equal to d 3 *2*π/2 or π. Thus {φ 1 , φ 2 , φ 3 , φ 4 } equals {π/2, π/2, 0, π}. Substituting those values into equation (1) yields the symbol c={e j2π , e jπ/2 , e j2π , −e j3π/2 , e jπ , e j3π/2 , −e jπ , e jπ/2 }. Euler&#39;s formula is provided below in equation (4):
 
 e   jθ =cos θ+ j  sin θ  (4)
 
   Substituting the complex chip values for c (shown above) into equation (4) yields the complex symbol c={1, −j, 1, j, −1, −j, 1, j}. Thus it is apparent that any symbol to be transmitted may be derived through the use of the above equations. 
   Decoding Data 
     FIG. 6  illustrates one exemplary embodiment of a receiver  600  (receiver  106  in  FIG. 2 ) in accordance with the principles of the present invention. The receiver  600  includes an antenna  602 , an RF amplifier  604 , an RF demodulator  606 , a data demodulator  608 , and a computer interface  610 . The encoded data packets transmitted by the antenna  212  ( FIG. 3 ) are received by the antenna  602 . The encoded data packets are applied to the RF amplifier  604  and the RF demodulator  606  to restore the data packets to a baseband signal. The data packets are then demodulated by the data demodulator  608  so that the original data from the computer interface  200  may be recovered. 
   Referring to  FIG. 7 , one exemplary embodiment of the data demodulator  608  ( FIG. 6 ) is shown in further detail. The data demodulator  608  includes a CCK 64-vector correlator  702  and a DQPSK demodulator  704 . The CCK 64-vector correlation implemented by the illustrated CCK correlator  702  can be written as: 
   
     
       
         
           
             
               
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   The correlator output R may be expanded as shown below: 
   
     
       
         
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   A single-vector implementation of the CCK correlator described above is depicted in  FIG. 8 . It should be appreciated that because the correlator  800  depicted in  FIG. 8  is a single-vector correlator, application of a particular combination of phase parameters φ 2 , φ 3  and φ 4  to the correlator  800  will yield a single output value R of the set of 64 possible correlator outputs values  802 . 
   One exemplary embodiment of the 64-vector CCK correlator  702  according to the present invention is depicted in  FIG. 9 . The received symbol c, made up of chips c 0 -c 7 , is applied to the input of the correlator  702 . It should be appreciated that, through the use of four different vector values for each of the phase parameters φ 2 , φ 3  and φ 4 , 64 different correlator output values are possible (4*4*4=64). φ 3  Rotators  710  are provided to rotate or cycle through the four possible values that φ 3  may assume. Of course, it should be appreciated that φ 3  may only assume four possible values when operating in 11 Mbps mode; in 5.5 Mbps mode, φ 3  is fixed at a value of 0. Two terms are summed at summers  712 . For example, a φ 3 -rotated value of c 0  (i.e., c 0 *e^jφ 3 ) is summed with c 2 , a φ 3 -rotated value of c 1  is summed with −c 3 , etc. At  714 , the four possible vectors of φ 2  (1, −j, −1, j) are applied to the output of the summers  712 . Two terms corresponding to φ 2  and φ 3  that have been decomposed according to equation (5) are summed at summers  716 . At  718 , the four possible vector values of φ 4  are applied to modify the outputs  718  of the summers  716 . Finally, two terms corresponding to φ 2 , φ 3  and φ 4  that have been decomposed according to equation (5) are summed at summers  720 . The output of the various summers  720  correspond to correlator outputs r 0 -r 15  (i.e. outputs  722 ). Thus, for any given value of φ 3 , there will be sixteen possible correlator outputs  722  with an index [φ 2 , φ 4 ]. 
   When the correlator  702  is operating in 11 Mbps mode, four clock cycles will be required in order to generate the 64 possible outputs  722 , i.e. 16 outputs  722  per clock cycle, with the φ 3  Rotators  710  rotating once per clock cycle. When the correlator  702  is operating in the 5.5 Mbps mode, however, only one clock cycle will be required to generate all available outputs  722 . This is because, in the 5.5 Mbps mode, φ 3  may only assume the value 0, such that there is no need to rotate through other possible vector values. As a consequence of the correlator design of the present invention, the amount of power required for demodulating while operating at 5.5 Mbps is greatly reduced compared to the prior art correlators as described above. Further, the correlator of the present invention is appreciably faster, because there is no need to rotate through the other possible φ 3  values. 
   The correlator outputs  722  are analyzed to determine which of the outputs r 0 -r 15  is of the greatest magnitude. Referring to  FIG. 10 , each of the correlator outputs  722  is applied to an absolute value module  750 . The absolute value module  750  will output a value representative of the magnitude of the inputted correlator output r 0 -r 15 , respectively. The maximum value is held in a current maximum value module  754 . The value in the current maximum value module  754  is preferably initialized to 0 such that the actual maximum correlator output  722  for the first iteration of phase rotations will be stored. The output of each absolute value module  750  and the current maximum value held in the current maximum value module  754  are compared. Thus, in one exemplary embodiment, 16 comparisons are performed (fifteen for the sixteen correlator outputs and one for the previous maximum value) for each of the four phase rotations of the φ 3  rotator. If the correlator  702  is operating in 5.5 Mbps mode, then all of the possible correlator values will have been generated, and the maximum value of those output values will be known and stored in the current maximum value module  754 . If the correlator  702  is operating in 11 Mbps mode, then φ 3  will be rotated three times, spanning all four phase values, and the correlator  702  will generate 16 correlator output values with each rotation. Comparisons are performed for each of the rotations and the maximum value of those 64 correlator values will be stored in the current maximum value module  754 . It should be appreciated by those skilled in the art that there are numerous other methods of determining the maximum value of a set of output values. 
   After determining the value of the maximum correlator output  722 , the index of the CCK correlator  702  with a maximum value is mapped to the corresponding data values. Specifically, the original data values d 2 -d 7  (11 Mbps) or d 2 -d 3  (5.5 Mbps) are determined through the use of an encoder, e.g. look-up table  758 . Look-up table  758  outputs data bits that correspond to the correlator index that has the maximum correlator output value. 
   The maximum correlator output value is also used to determine data values d 0 -d 1 . This is done through DQPSK demodulation performed by DQPSK demodulation module  704  ( FIG. 7 ). 
   The original data values d 0 -d 3  (5.5 Mbps) or d 0 -d 7  (11 Mbps) are then provided by the data demodulator  608  to the computer interface  610  ( FIG. 6 ). 
     FIG. 11  is a flow diagram depicting the transmission portion according to one embodiment of the present invention. In block  1000 , data is received from a computer via the computer interface  200  ( FIG. 3 ). The data is then grouped into symbols in block  1002  by the symbol grouping module  202  ( FIG. 3 ). In block  1004 , the data is modulated by the data modulator  204  ( FIG. 3 ). The baseband modulated data is then RF modulated in block  1006  by the RF modulator  206  ( FIG. 3 ). In block  1008 , the RF signal is amplified by RF amplifier  210  ( FIG. 3 ). Finally, the amplified RF signal is transmitted in block  1010  by antenna  212  ( FIG. 3 ). 
     FIG. 12  is a flow diagram depicting the encoding or data modulation portion according to one exemplary embodiment of the present invention. In block  1100 , data bits d 0  and d 1  are DQPSK encoded by the DQPSK encoder  500  ( FIG. 5 ). A determination is then made as to whether the CCK encoder  500  is operating in 5.5 Mbps or 11 Mbps mode (block  1102 ). An indication of the operating mode is stored in the header  404  ( FIG. 4 ). If the CCK encoder  500  is operating in 5.5 Mbps mode, then, in block  1104 , data bits d 2 -d 3  are applied to the CCK correlator  504  ( FIG. 5 ). It should be recognized that four bits are used in 5.5 Mbps encoding. If the CCK encoder  500  is operating in 11 Mbps mode, then, in block  1106 , data bits d 2 -d 7  are applied to the CCK correlator  504  ( FIG. 5 ). 
     FIG. 13  is a flow diagram depicting the receiving portion according to one embodiment of the present invention. At block  1200 , the RF signal transmitted by antenna  212  ( FIG. 3 ) is received by antenna  602  ( FIG. 6 ). The RF signal is then amplified at block  1202  by RF amplifier  604  ( FIG. 6 ). In block  1204 , the amplified RF signal is demodulated by the RF demodulator  606  ( FIG. 6 ). The demodulated RF signal is then in block  1206  demodulated by the data demodulator  608  ( FIG. 6 ). In block  1208 , the demodulated data is then supplied to a receiver computer (not shown) via computer interface  610  ( FIG. 6 ). 
     FIG. 14  is a flow diagram depicting data demodulation according to one exemplary embodiment of the present invention. In block  1302 , it is determined if the data demodulator  608  ( FIGS. 6-7 ) is operating in 5.5 Mbps or 11 Mbps mode. This is done by examining the header  404  ( FIG. 4 ) which contains an indication of the operating mode in the operating mode indicator  405 . If the data demodulator  608  is operating in 5.5 Mbps mode, then at block  1304  the received symbol is applied to the correlator  702  ( FIG. 7 ). The φ 3  rotator is set to output a value of 0, as φ 3  is not rotated in 5.5 Mbps mode according to one exemplary embodiment of the present invention. The correlator  702  then generates 16 outputs (block  1308 ). The correlator  702  keeps only four of the outputs which correspond to the four vectors used for the 5.5 Mbps mode. The other twelve output values are forced to a value of 0 (block  1309 ). If, on the other hand, the data demodulator  608  is operating in 11 Mbps mode, then at block  1306  the received symbol is applied to the correlator  702  ( FIG. 7 ). The (P 3  rotator, however, is now set to rotate through its four values (0, π/2, π and 3π/2), so that the correlator  702  will generate 64 outputs (block  1310 ). Regardless of whether 16 or 64 outputs are generated (i.e., in either operating mode), at block  1312  the maximum correlator output is determined. The maximum correlator output is then demodulated to output the original data (block  1314 ). As shown, the demodulation of the block  1314  is performed by DQPSK demodulating the data to determine data bits d 0  and d 1  (block  1316 ) and using a look-up table to recover data bits d 2 -d 3  (5.5 Mbps) or d 2 -d 7  (11 Mbps) (block  1318 ). 
     FIG. 15  illustrates a 64-vector correlation unit  1500  consistent with another embodiment of the invention, which can be configured to selectively predict CCK subsymbols responsive to a received subset of chips c 0 ′ . . . c 7 ′ defining a received CCK encoded symbol C′. These predicted CCK subsymbols can be regenerated for e.g. equalization purposes via a CCK code regenerator  1550  coupled to the output of the correlation unit  1500 . The prime notation here is used to signify potential differences between the received symbol/chips (c′={c 0 ′ . . . c 7 ′}) and the originally transmitted symbol/chips (c={c 0  . . . c 7 }) resulting from intervening ISI, inter chip interference (“ICI”), and environmental noise. As noted above, subsymbol prediction and regeneration can be used in adaptive channel equalization of the received baseband signal to address such noise and interference in order for C′ to approach the transmitted C. In accordance with the decoding techniques disclosed in U.S. patent application Ser. No. 10/080,826, filed Feb. 21, 2002, the contents of which are incorporated herein fully by reference, predicted subsymbols regenerated during certain chips in the current C′ symbol decode sequence can be used to equalize the received chips of C′ when subsequent chips of C′ are received, thereby leveraging the processing gain of the CCK decoder to provide more accurate and sensitive feedback and baseband symbol demodulation over conventional systems which e.g. employ no feedback or solely hard-decision slicing for equalization purposes. For example, regeneration of a predicted 2 nd  chip subsymbol C 2 ″, defining {c 0 ″,c 1 ″} after c 1 ′ is received (i.e. after the 2 nd  chip into the current symbol C′ decode sequence) may be used to equalize received chips c 0 ′, c 1 ′. Likewise, other subsymbols may be predicted and regenerated to equalize the received chips at other times into the current symbol decode sequence. 
   Comparing the correlation unit  1500  of  FIG. 15  to the correlator  702  shown in  FIG. 9 , the following differences are noted. First, a serial to parallel shift register  1510  is expressly shown and provides the serialized sequence of chips defining the symbol or subsymbol to be demodulated in parallel to the input of the correlator  1505 . However, though not shown in  FIG. 9 , such functionality may be provided as part of the correlator  702  based on receiver implementation requirements. Second, a data cross bar  1520  is connected to the output of the serial to parallel shift register  1510  to selectively map the received chips into the inputs of the correlator  1505  dependent upon the type of predicted subsymbol to be regenerated or if the entire symbol is to be decided. These and other functions of the data cross bar  1520  will be discussed in more detail further below. 
   Also, the correlator  1500  includes a windowing unit  1530  which selectively filters certain invalid vectors from correlation result vectors R 0  . . . R 15  (once for 5.5 Mbps mode and 4 times for 11 Mbps mode corresponding to the need for rotating through φ 3  as described above), also responsive to which type of predicted subsymbol is to be regenerated or if the entire symbol is to be decided. Alternatively phrased, the windowing unit  1530  selects a valid subset of candidate correlation result vectors R 0  . . . R 15  based on which type of subsymbol or symbol is to be realized. In this embodiment, invalid correlation results are zeroed out to the origin on the complex plane (0,0) such that their magnitude or absolute value is zero. 
   The reason why not all 16 or 64 correlation result vectors are needed here is because, consistent with most-likely subsymbol prediction according to the present embodiment, not all chips required to completely define a given symbol are needed to predict a subsymbol. In fact, as will be discussed in greater detail below, to predict and regenerate a 2 nd  chip subsymbol C 2 ″ of a given CCK-encoded symbol C, only chips c 0 ′ and c 1 ′ need be received. Likewise, only chips c 0 ′ . . . c 3 ′ are required to predict and regenerate a 4 th  chip CCK subsymbol C 4 ″, while chips c 0 ′ . . . c 5 ′ are required to for a 6 th  chip CCK subsymbol C 6 ″. 
   However, as before, all eight chips c 0 ′ . . . c 7 ′ will be needed to fully decide the CCK symbol and regenerate it during the 8 th  chip (C 8 ″). 
   The maximum magnitude picker unit  1540  combines the functionality previously associated with the absolute value units  750  and the comparator  752  described above with reference to the embodiment of  FIG. 10 , and in conjunction with a current maximum vector/index register  1545 , identifies the correlation result vector Rm from the input set of valid correlation result vectors r 0  . . . r 15  as well as its corresponding correlator index, m_index, which has the maximum correlator output value once per clock cycle in 5.5 Mbps mode, or after φ 3  rotation (four cycles) is complete when in 11 Mbps mode. The register  1545  differs from the current maximum value module  754  in that current maximum correlator index information is also stored. 
   2nd Chip Subsymbol Prediction 
   In this case, only 2 chips (c 0 ′, c 1 ′) of the current symbol are available, the shift register  1510  holds c 0 ′, and c 1 ′ 60  is received from the output of the RF demodulator  606  ( FIG. 6 ) and asserted on tap  17 . At this time, the most likely 2nd chip subsymbol may be defined as:
 
 C   2   ″={c 0″, c 1″}={ e   j(α     1     +α     2     +α     3     +α     4     )   ,e   j(α     1     +α     3     +α     4     )   }={e   jα     2   ,1}* e   j(α     1     +α     3     +α     4     )   (7)
 
And the optimized correlation should be:
 
   
     
       
         
           
             
               
                 
                   R 
                   2 
                 
                 = 
                 
                   
                     
                       
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                 ( 
                 8 
                 ) 
               
             
           
         
       
     
   
   To obtain R 2  with different possible α 2  using the correlator  1505  shown in  FIG. 15 , for either the 5.5 or 11 Mbps mode, the data cross bar  1520  is configured to reposition the received chips to the inputs of the correlator  1505  as follows {c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 }={ 0 , 0 ,I 6 ,I 7 , 0 , 0 , 0 , 0 } or, alternatively { 0 , 0 ,c 1 ′,c 0 ′, 0 , 0 , 0 , 0 }. Thus, with this configuration of the data cross bar  1520 , the correlator  1505  output may be written as: 
   
     
       
         
           
             
               
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                 ( 
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   If φ 2 =α 2 , φ 4 =0, then R 2 =R. Considering that φ 2 ε{0,π/2,π,3π/2} in 11 Mbps mode, four (4) valid correlation result vectors R may be calculated by the correlator  1505  dependent on the differing φ 2 , indicating the 2 nd  chip subsymbol can be predicted from one of 4 different combinations of c 0 ′,c 1 ′. For the 11 Mbps mode, the windowing unit  1530  window is selected as (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1) for R 0  to R 15  from left to right, thereby passing all correlation result vectors R to the maximum magnitude picker unit  1540  for maximum correlation magnitude result determination of corresponding r 0  . . . r 15 . For 5.5 Mbps, because α 2  has only two possible values (+j, −j), according to the power saving architecture of the correlator  1505 , the windowing unit  1530  window is selected as (0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0). It should be noted that the remaining correlation result R 0 -R 3 , R 5 -R 11  and R 13 -R 15  are not valid for this transmission mode and chip into the current symbol decode sequence, and are properly ignored for magnitude comparison by the maximum magnitude picker unit  1540  using this windowing unit  1530  configuration. 
   The maximum magnitude picker unit  1540  realizes the magnitude for each valid vector r and determines which exhibits the maximum magnitude (Rm) as well as correlator index m_index having the maximum correlator output value, in a manner consistent with that described above with reference to the embodiment of  FIG. 10 . The phase value for φ 2  (recoverable from the m_index into a CCK symbol lookup table) corresponding to the maximum magnitude (say, Γ 2 ) is assigned to α 2  (α 2 =Γ 2 )=+j or −j for 5.5 Mbps mode. From Equations (7) (8) (9), α 1 +α 3 +α 4 =arg R 2  which corresponds to the phase of the residue of the correlator  1505  when the 2 nd  chip subsymbol is predicted. Therefore, from Equations (7) (8) and this residue relationship, the CCK code regenerator  1550  may regenerate the most-likely 2 nd  chip subsymbol C 2 ″ as:
 
 C   2   ″={c 0″, c 1″}={ e   j(Γ     2     +arg R     2     )   ,e   j arg R     2   }  (10)
 
4 th  Chip Subsymbol Prediction
 
   In this case, the first four complex chips (c 0 ′, c 1 ′,c 2 ′,c 3 ′) of the current symbol are available, with the shift register  1510  holding (c 0 ′, c 1 ′, c 2 ′) accessible through taps I 4 , I 5  and I 6  respectively and c 3 ′ is received from the output of the RF demodulator  606  and asserted on tap  17 . At this time, the most likely 4 th  chip subsymbol may be defined as:
 
 C   4 ″={e j(α     1     +α     2     +α     3     +α     4     )   ,e   j(α     1     +α     3     +α     4     )   ,e   j(α     1     +α     2     +α     4     )   ,−e   j(α     1     +α     4     )   }={e   j(α     2     +α     3     )   ,e   jα     3     ,e   jα     2   ,−1}* e   j(α     1     +α     4     )   (11)
 
And the optimized correlation should be:
 
   
     
       
         
           
             
               
                 
                   R 
                   4 
                 
                 = 
                 
                   
                     
                       
                         [ 
                         
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 4 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 5 
                               
                             
                           
                           
                             
                               
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                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 6 
                               
                             
                           
                           
                             
                               
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                                 ⁢ 
                                 7 
                               
                             
                           
                         
                         ] 
                       
                       T 
                     
                     ⁡ 
                     
                       [ 
                       
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       2 
                                     
                                     + 
                                     
                                       α 
                                       3 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   α 
                                   3 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   α 
                                   2 
                                 
                               
                             
                           
                         
                         
                           
                             
                               - 
                               1 
                             
                           
                         
                       
                       ] 
                     
                   
                   * 
                 
               
             
             
               
                 ( 
                 12 
                 ) 
               
             
           
         
       
     
   
   To obtain R 4  with different possible combinations of α 2  and α 3  using the correlator  1505 , the data cross bar  1520  is configured to reposition the received chips as follows: (c 0 ,c 1 ,c 2 ,c 3 ,c 4 ,c 5 ,c 6 ,c 7 )=( 0 , 0 ,I 4 ,I 5 , 0 , 0 ,I 6 ,−I 7 ) or, alternatively put, =( 0 , 0 ,c 0 ′,c 1 ′, 0 , 0 ,c 2 ′,−c 3 ′). Thus, the correlator  1505  output may be written as: 
                 R   =                   [         0             I   ⁢           ⁢   4             0             I   ⁢           ⁢   5             0             I   ⁢           ⁢   6             0               -   I     ⁢           ⁢   7           ]     T     ⁡     [           ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1         ]       *     ⁡     [           ⅇ     j   ⁢           ⁢     φ   2                             1                                     ⅇ     j   ⁢           ⁢     φ   2                             1         ]       *     ⁡     [           ⅇ     j   ⁢           ⁢     φ   4                 1         ]       *             (   13   )               
If φ 2 =α 2 , φ 3 =α 3 , then R 4 =R. Considering that φ 2 ε{0,π/2,π,3π/2} and φ 3 ε{0,π/2,ρ,3π/2} in 11 Mbps mode, sixteen (16) valid correlation result vectors R are calculated by the correlator  1505 , indicating that the 4 th  chip subsymbol can be predicted from one of 16 different combinations of c 0 ′, c 1 ′, c 2 ′ and c 3 ′. For the 11 Mbps mode, the windowing unit  1530  window is selected as (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1), thereby passing all correlation result vectors R to the maximum magnitude picker unit  1540  for maximum correlation magnitude result determination of corresponding r 0  . . . r 15 . For 5.5 Mbps mode, because α 2  has only two possible values and α 3 =0, according to the power saving architecture of the correlator  1505 , the windowing unit  1530  window is selected as (0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0), such that only vectors R 4  and R 12  are passed along as r 4  and r 12  respectively, with the remaining vectors equated to the origin of the complex plane to provide a magnitude of zero.
 
   As before, the maximum magnitude picker unit  1540  realizes the magnitude for each valid vector r generated by the windowing unit and determines which exhibits the maximum magnitude (Rm) as well as m_index, as previously described. The phase values for φ 2  and φ 3  (recoverable using the m_index) corresponding to the maximum magnitude (say, Γ 2 , Γ 3 ) is assigned to α 2  and α 3 , or: 
           {               α   2     =     Γ   2                   α   3     =     Γ   3             .           
In this case, the phase of the residue of the correlator can be derived from Equations (11), (12) and (13), and can be expressed as α 1 +α 4 =arg R 4 . Therefore, from Equations (11), (12) and this residue phase relationship, the CCK code regenerator  1550  may regenerate the most-likely 4 th  chip subsymbol C 4  as:
 C 4   ″={c 0″, c 1″, c 2″, c 3″}={ e   j(arg R     4     +Γ     2     +Γ     3     )   ,e   j(arg R     4     +Γ     3     )   ,e   j(arg R     4     +Γ     2     )   ,−e   j arg R     4   }.  (14) 
6 th  Chip Subsymbol Prediction
 
   In this case, the first six complex chips (c 0 ′, c 1 ′,c 2 ′,c 3 ′, c 4 ′, c 5 ′) of the current symbol are available, with the shift register  1510  holding (c 0 ′, c 1 ′, c 2 ′, c 3 ′, c 4 ′) accessible through taps I 2 , I 3 , I 4 , I 5 , and I 6  respectively and c 5 ′ is received from the output of the RF demodulator  606  and asserted on tap  17 . At this time, the most likely 6 th  chip subsymbol C 6  may be defined as: 
                         C   6   ”     =       ⁢     {       ⅇ     j   ⁢           ⁢     (       α   1     +     α   2     +     α   3     +     α   4       )         ,     ⅇ     j   ⁢           ⁢     (       α   1     +     α   3     +     α   4       )         ,     ⅇ     j   ⁢           ⁢     (       α   1     +     α   2     +     α   4       )         ,     -     ⅇ     j   ⁢           ⁢     (       α   1     +     α   4       )           ,                       ⁢       ⅇ     j   ⁢           ⁢     (       α   1     +     α   2     +     α   3       )         ,     ⅇ     j   ⁢           ⁢     (       α   1     +     α   3       )           }               =       ⁢     {       ⅇ     j   ⁢           ⁢     (       α   2     +     α   3     +     α   4       )         ,     ⅇ     j   ⁢           ⁢     (       α   3     +     α   4       )         ,     ⅇ     j   ⁢           ⁢     (       α   2     +     α   4       )         ,     -     ⅇ     j   ⁢           ⁢     α   4           ,     ⅇ     j   ⁢           ⁢     (       α   2     +     α   3       )         ,                         ⁢     ⅇ     j   ⁢           ⁢     α   3         }     *     ⅇ     j   ⁢           ⁢     α   1                       (   15   )               
And the optimized correlation should be:
 
   
     
       
         
           
             
               
                 
                   R 
                   6 
                 
                 = 
                 
                   
                     
                       
                         [ 
                         
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 3 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 4 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 5 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 6 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 7 
                               
                             
                           
                         
                         ] 
                       
                       T 
                     
                     ⁡ 
                     
                       [ 
                       
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       2 
                                     
                                     + 
                                     
                                       α 
                                       3 
                                     
                                     + 
                                     
                                       α 
                                       4 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       3 
                                     
                                     + 
                                     
                                       α 
                                       4 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       2 
                                     
                                     + 
                                     
                                       α 
                                       4 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               - 
                               
                                 ⅇ 
                                 
                                   j 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     α 
                                     4 
                                   
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       2 
                                     
                                     + 
                                     
                                       α 
                                       3 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   α 
                                   3 
                                 
                               
                             
                           
                         
                       
                       ] 
                     
                   
                   * 
                 
               
             
             
               
                 ( 
                 16 
                 ) 
               
             
           
         
       
     
   
   To obtain R 6  with different possible combinations of α2, α3 and α4 using the correlator  1505 , the data cross bar  1520  is configured to reposition the received chips as follows: (c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 )=(I 2 ,I 3 ,I 4 ,I 5 ,I 6 ,I 7 , 0 , 0 ) or, alternatively put, =(c 0 ′, c 1 ′, c 2 ′, c 3 ′, c 4 ′, c 5 ′, 0 , 0 ). Thus, the correlator  1505  output may be written as: 
                 R   =                   [           I   ⁢           ⁢   2               I   ⁢           ⁢   3               I   ⁢           ⁢   4                 -   I     ⁢           ⁢   5               I   ⁢           ⁢   6               I   ⁢           ⁢   7             0           0         ]     T     ⁡     [           ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1         ]       *     ⁡     [           ⅇ     j   ⁢           ⁢     φ   2                             1                                     ⅇ     j   ⁢           ⁢     φ   2                             1         ]       *     ⁡     [           ⅇ     j   ⁢           ⁢     φ   4                 1         ]       *             (   17   )               
If φ 2 =α 2 , φ 3 =α 3 , φ 4 =α 4 , then R 6 =R. Considering that φ 2 ε{0,π/2,π,3π/2},100  3 ε{0,π/2,π,3π/2} in 11 Mbps mode, all 64 possible correlating operations (4 cycles of 16 vector correlating through rotation of φ 3  are carried out by the correlator  1505 , now indicating that the 6 th  chip subsymbol can be predicted from one of 64 different combinations of c 0 ′ . . . c 5 ′. For the 11 Mbps mode, the windowing unit  1530  window is selected as (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1) as in the case of predicted subsymbols C 2 ″ and C 4 ″ previously discussed, thereby passing all correlation result vectors R to the maximum magnitude picker unit  1540  for maximum correlation magnitude result determination of corresponding r 0  . . . r 15 . For 5.5 Mbps mode, because the combination of α 2  and α 4  has only four possible values and α 3 =0, according to the power saving architecture of the correlator  1505 , the windowing unit  1530  window is selected as (0,0,0,0,1,0,1,0,0,0,0,0,1,0,1,0), such that only vectors R 4 , R 6 , R 12 , and R 14  as passed along as vectors r 4 , r 6 , r 12 , and r 14  respectively, with the remaining vectors zeroed out.
 
   As in the case for C 2 ″ and C 4 ″ subsymbol prediction, the maximum magnitude picker unit  1540  here realizes the magnitude for each valid vector r generated by the windowing unit and determines which exhibits the maximum magnitude (Rm) as well as m_index. The phase values for φ 2 , φ 3  and φ 4  (recoverable using the m_index) corresponding to the maximum magnitude (say, Γ 2 , Γ 3 , Γ 4 ) is assigned to α 2 , α 3  and α 4  or: 
                 {               α   2     =     Γ   2                   α   3     =     Γ   3                   α   4     =     Γ   4             .             (   18   )               
From Equations (15), (16), and (17), the phase of the residue of the correlator  1505  may be expressed as α 1 =arg R 6 . Therefore, from Equations (15), (16) and this residue phase relationship, the CCK code regenerator  1550  may regenerate the most-likely 6 th  chip subsymbol C 6 ″ as:
   C   6   ″={c 0″, c 1″, c 2″, c 3″, c 4″, c 5″}={ e   j(arg R     6     +Γ     2     +Γ     3     +Γ     4     )   ,e   j(arg R     6     +Γ     3     +Γ     4     )   ,e   j(arg R     6     +Γ     2     +Γ     4     )   ,−e   j(arg R     6     +Γ     4     )   ,e   j(arg R     6     +Γ     2     +Γ     3     )   ,e   j(arg R     6     +Γ     3     ) }  (19) 
8 th  Chip Symbol Decision
 
   In this case, all eight received complex chips (c 0 ′ . . . c 7 ′) of the current symbol are available, with the shift register  1510  holding (c 0 ′ . . . c 6 ′) accessible through taps I 0  . . . I 6  respectively and c 7 ′ is received from the output of the RF demodulator  606  and asserted on tap I 7 . At this time, the most likely 8 th  chip symbol C 8  may be defined as: 
                         C   8   ”     =       ⁢     {       ⅇ     j   ⁢           ⁢     (       α   1     +     α   2     +     α   3     +     α   4       )         ,     ⅇ     j   ⁢           ⁢     (       α   1     +     α   3     +     α   4       )         ,     ⅇ     j   ⁢           ⁢     (       α   1     +     α   2     +     α   4       )         ,     -     ⅇ     j   ⁢           ⁢     (       α   1     +     α   4       )           ,                       ⁢       ⅇ     j   ⁢           ⁢     (       α   1     +     α   2     +     α   3       )         ,     ⅇ     j   ⁢           ⁢     (       α   1     +     α   3       )         ,     -     ⅇ     j   ⁢           ⁢     (       φ   1     +     φ   2       )           ,     ⅇ     j   ⁢           ⁢     φ   1           }               =       ⁢     {       ⅇ     j   ⁢           ⁢     (       α   2     +     α   3     +     α   4       )         ,     ⅇ     j   ⁢           ⁢     (       α   3     +     α   4       )         ,     ⅇ     j   ⁢           ⁢     (       α   2     +     α   4       )         ,     -     ⅇ     j   ⁢           ⁢     α   4           ,     ⅇ     j   ⁢           ⁢     (       α   2     +     α   3       )         ,                         ⁢       ⅇ     j   ⁢           ⁢     α   3         ,     -     ⅇ     j   ⁢           ⁢     φ   2           ,   1     }     *     ⅇ     j   ⁢           ⁢     α   1                       (   20   )               
And the optimized correlation should be:
 
   
     
       
         
           
             
               
                 
                   R 
                   8 
                 
                 = 
                 
                   
                     
                       
                         [ 
                         
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 0 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 3 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 4 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 5 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 6 
                               
                             
                           
                           
                             
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 7 
                               
                             
                           
                         
                         ] 
                       
                       T 
                     
                     ⁡ 
                     
                       [ 
                       
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       2 
                                     
                                     + 
                                     
                                       α 
                                       3 
                                     
                                     + 
                                     
                                       α 
                                       4 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       3 
                                     
                                     + 
                                     
                                       α 
                                       4 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       2 
                                     
                                     + 
                                     
                                       α 
                                       4 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               - 
                               
                                 ⅇ 
                                 
                                   j 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     α 
                                     4 
                                   
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       α 
                                       2 
                                     
                                     + 
                                     
                                       α 
                                       3 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ⅇ 
                               
                                 j 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   α 
                                   3 
                                 
                               
                             
                           
                         
                         
                           
                             
                               - 
                               
                                 ⅇ 
                                 
                                   j 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     α 
                                     2 
                                   
                                 
                               
                             
                           
                         
                         
                           
                             1 
                           
                         
                       
                       ] 
                     
                   
                   * 
                 
               
             
             
               
                 ( 
                 21 
                 ) 
               
             
           
         
       
     
   
   Using the correlator  1505  to obtain R 8 , the data cross bar  1520  simply passes along the c′. To get R 6  with different α 2 , α 3 , α 4 , we may configure the data cross bar unit  1520  just as a pass through buffer, e.g. (c 0 , c 1 , c 2 , −c 3 , c 4 , c 5 , c 6 , −c 7 )=(I 0 ,I 1 ,I 2 ,I 3 ,I 4 ,I 5 ,I 6 ,I 7 ), or, alternatively put, =(c 0 ′, c 1 ′,c 2 ′, −c 3 ′, c 4 ′, c 5 ′, c 6 ′, −c 7 ′). Then, the general correlator  1505  output is: 
                 R   =                   [           I   ⁢           ⁢   0               I   ⁢           ⁢   1               I   ⁢           ⁢   2                 -   I     ⁢           ⁢   3               I   ⁢           ⁢   4               I   ⁢           ⁢   5                 -   I     ⁢           ⁢   6               I   ⁢           ⁢   7           ]     T     ⁡     [           ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1                                                             ⅇ     j   ⁢           ⁢     φ   3                                                     1         ]       *     ⁡     [           ⅇ     j   ⁢           ⁢     φ   2                             1                                     ⅇ     j   ⁢           ⁢     φ   2                             1         ]       *     ⁡     [           ⅇ     j   ⁢           ⁢     φ   4                 1         ]       *             (   22   )               
If φ 2 =φ 3 , φ 3 =α 3 , φ 4 =α 4 , then R 8 =R. Similar to 6 th  chip subsymbol prediction discussed above, and considering that φ 2 ε{0,π/2,π,3π/2},φ 3 ε{0,π/2,π,3π/2}, and φ 4 ε{0,π/2,π,3π/2} in 11 Mbps mode, all 64 possible correlating operations (4 cycles of 16 vector correlating through rotation of φ 3 ) are carried out by the correlator  1505 , now indicating that the 8 th  chip symbol can be decided from one of 64 different combinations of c 0 ′ . . . c 7 ′. For the 11 Mbps mode, the windowing unit  1530  window is again selected as (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1), thereby passing all correlation result vectors R to the maximum magnitude picker unit  1540  for maximum correlation magnitude result determination of corresponding r 0  . . . r 15 . For 5.5 Mbps mode, because the combination of α 2  and α 4  has only four possible values and α 3 =0, according to the power saving architecture of the correlator  1505 , the windowing unit  1530  window is selected as (0,0,0,0,1,0,1,0,0,0,0,0,1,0,1,0), such that only vectors R 4 , R 6 , R 12 , and R 14  as passed along as vectors r 4 , r 6 , r 12 , and r 14  respectively, with the remaining vectors zeroed out.
 
   As in the case for subsymbol prediction discussed, the maximum magnitude picker unit  1540  here realizes the magnitude for each valid vector r generated by the windowing unit  1530  and determines which exhibits the maximum magnitude (Rm) as well as m_index. The phase values for φ 2 , φ 3 , and φ 4  (recoverable using the m_index) corresponding to the maximum magnitude (say, Γ 2 , Γ 3 , and Γ 4 ) is assigned to α 2 , α 3 , and αa 4  or: 
                 {               α   2     =     Γ   2                   α   3     =     Γ   3                   α   4     =     Γ   4             .             (   23   )               
From Equations (20), (21), and (22), the phase of the residue of the correlator  1505  may be expressed as α 1 =arg R 8 . Therefore, from Equations (20), (21) and this residue phase relationship, the CCK code regenerator  1550  may regenerate the 8 th  chip decided symbol C 8 ″ as:
 
   
     
       
         
           
             
               
                 
                   
                     
                       
                         C 
                         8 
                         ” 
                       
                       = 
                         
                       ⁢ 
                       
                         ( 
                         
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               0 
                               ″ 
                             
                           
                           , 
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               1 
                               ″ 
                             
                           
                           , 
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               2 
                               ″ 
                             
                           
                           , 
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               3 
                               ″ 
                             
                           
                           , 
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               4 
                               ″ 
                             
                           
                           , 
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               5 
                               ″ 
                             
                           
                           , 
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               6 
                               ″ 
                             
                           
                           , 
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               7 
                               ″ 
                             
                           
                         
                         ) 
                       
                     
                   
                 
                 
                   
                     
                       = 
                         
                       ⁢ 
                       
                         { 
                         
                           
                             ⅇ 
                             
                               j 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 ( 
                                 
                                   
                                     arg 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     
                                       R 
                                       8 
                                     
                                   
                                   + 
                                   
                                     Γ 
                                     2 
                                   
                                   + 
                                   
                                     Γ 
                                     3 
                                   
                                   + 
                                   
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                                     4 
                                   
                                 
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                               ⁢ 
                               
                                   
                               
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                                     ⁢ 
                                     
                                         
                                     
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                                       8 
                                     
                                   
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                                       ⁢ 
                                       
                                           
                                       
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                                       4 
                                     
                                   
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                           , 
                         
                       
                     
                   
                 
                 
                   
                     
                       
                         
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                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 ( 
                                 
                                   
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                                     ⁢ 
                                     
                                         
                                     
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                                       8 
                                     
                                   
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                                     2 
                                   
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                                     3 
                                   
                                 
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                             j 
                             ⁢ 
                             
                                 
                             
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                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     R 
                                     8 
                                   
                                 
                                 + 
                                 
                                   Γ 
                                   3 
                                 
                               
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     FIG. 16  depicts a CCK symbol demodulation unit  1600  which may be used in the data demodulation unit  608  in an alternative embodiment of the invention. This demodulation unit  1600  provides for decision feedback equalization of the received CCK symbols (C′) through a digital feedback equalizer (DFE)  1610  coupled to the CCK code regenerator  1550  and correlation unit  1500  shown in  FIG. 15 . In particular, predicted subsymbols C 2 ″, C 4 ″, C 6 ″and/or C 8 ″ are computed by the correlation unit  1500  and regenerated by the regenerator  1550  as noted above and are used by the DFE  1610  during the second, fourth, six and/or eighth chip into the current symbol decode sequence respectively to leverage the processing gain afforded by the correlation unit  1500  and equalize the corresponding chips of the current symbol C′ fed to the correlation unit  1500 , as discussed above with reference to U.S. patent application Ser. No. 10/080,826. Note here that a control unit  1620  issues data cross bar  1520  configuration parameters such as a CB_CNTRL parameter to configure the data cross bar to selectively reposition the received chips of C′ based on which subsymbol is to be predicted. The control unit  1620  likewise passes appropriate configuration parameters to the CCK code regenerator  1550  (e.g. REGEN_CNTL) and the windowing unit  1530  (e.g. WINDOW_CNTL) again based on which subsymbol type(s) are desired for prediction and what transmission rate mode the demodulation unit  1600  is operating in. As will be appreciated by those ordinarily skilled in the art, the WINDOW_CNTL, CB_CNTL and REGEN_CNTL may define individual or common parameters depending upon implementation requirements. 
     FIG. 17  is a flowchart depicting subsymbol prediction and correlation processing undertaken by the aforementioned correlation unit  1500 . 
   It should also be appreciated by those ordinarily skilled in the art that the present invention may be practiced at least in part through the use of an information processing system including a general purpose or specific-purpose processor, embodied by software or firmware. For example, the correlation unit  1500  may conveniently comprise a microprocessor programmed in accordance with the processing steps outlined in  FIG. 17  to provide the specified functionality. Likewise, discrete logic, in isolation or in combination with one or more application-specific circuits configured in accordance with the teachings of the present invention may be also used interchangeably depending upon implementation. 
   While the present invention has been described with respect to several embodiments, it is to be understood that the invention is not limited to the embodiments disclosed. To the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. For example, it is to be understood that the invention is generally applicable to other correlator architectures in which phase rotators may selectively be used, and in fact in any correlator architecture where it would be advantageous to predict subsymbols. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.