Abstract:
A sample rate converter is formed by a cascade configuration of a partial filter (20,22,32,26,28) and an equalizer (26,28,30,34) for equalizing the frequency characteristic of the partial filter. For obtaining a minimum-complexity equalizer when the complexity of the partial filter is minimized, the equalizer is arranged as a feedback system including in the feedback path an equalization filter that is substantially equal to the partial filter.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a sample rate converter for filtering a discrete-time input signal having a sample rate q·f s  by means of a system filter having an impulse response h(t) and, besides, for converting the discrete-time input signal having a sample rate q·f s  to a discrete-time output signal having a sample rate p·f s , p and q being unequal positive integers greater than or equal to one, the sample rate converter including a cascade combination of a partial filter and an equalizer for equalizing the frequency characteristic of the sample rate converter. 
     2. Description of the Related Art 
     A sample rate converter of this type is known from the journal article entitled &#34;Area-Efficient Multichannel Oversampled PCM Voiceband Coder&#34; in IEEE Journal of Solid State Circuits, Vol. 23, No. 6, December 1988. 
     Sample rate converters of this type are used, for example, in analog-to-digital converters and digital-to-analog converters operating according to the sigma-delta principle. In a sigma-delta analog-to-digital converter the analog input signal is converted to a digital 1-bit signal that denotes the sign of the difference between a sample of the analog input signal and a sample of suitably filtered preceding 1-bit signals. 
     The sample rate of the sigma-delta analog-to-digital converter is many times higher than the minimum required sample rate according to Shannon&#39;s sampling theorem. The advantage of this is that the anti-aliasing filter which is to reduce the bandwidth of the analog input signal to half the sample rate may now be arranged in a much simpler manner in that the passband and the stopband of this anti-aliasing filter are much wider apart than in the case where the sample rate were about equal to the minimum sample rate required according to the sampling theorem. 
     However, in many cases a digital output signal is ultimately desired to have a sample rate which is about equal to the minimum sample rate required according to the sampling theorem. This lower sample rate is often desired for further processing the, for example, digital output signal with the aid of a bit-parallel arranged signal processor which, in addition, has a limited processing rate. Also for the transmission of such a signal by, for example, a telephone line, the sample rate of the digital signal is desired not to be higher than is strictly necessary. 
     For obtaining a reduction of the sample rate, the 1-bit signal is applied to a sample rate converter which derives a reduced sample rate PCM signal from the 1-bit signal. 
     A known property (known, for example, from aforementioned article) of sigma-delta modulators is that the 1-bit signal comprises quantizing noise with a frequency-dependent spectral power density, which spectral power density strongly increases with frequency. If the conversion of the 1-bit signal to a PCM signal having a reduced sample rate is effected, for example, by adding bits over a specific time interval, the high-frequency quantizing noise in the 1-bit signal will be aliased to the baseband in which the desired signal is situated. Consequently, the signal-to-noise ratio of the PCM signal is degraded considerably. 
     In order to avoid this degradation of the signal-to-noise ratio, the noise of the 1-bit signal, which noise has frequencies exceeding the maximum frequency of the desired PCM signal, is to be eliminated with the aid of a filter to be termed rest filter hereinafter, before the sample rate is reduced. 
     A similar problem occurs when the sample rate is increased from a first sample rate f 1  to a second sample rate f 2 . Once the sample rate has been increased, the frequency spectrum of the discrete-time signal having the second sample rate continues to be periodic with a period f 1  that corresponds to the first sample rate, whereas a signal is desired which has a frequency spectrum that is only periodic with a period f 2  that corresponds to the second (higher) sample rate. In order to realise this, a system filter is required which also eliminates the undesired frequency components between 1/2 f 1  and 1/2 f 2 . 
     For a reduction of the complexity of the system filter, a system filter having an impulse response h(t) which is simple to realize is chosen for the known sample rate converter. As a result, the frequency characteristic of the system filter in the passband is not flat, so that the frequency spectrum of the baseband signal will change. In order to realize a flat frequency characteristic in the passband of the whole sample rate converter, the sample rate converter is arranged as a cascade configuration of a partial filter and an equalizer, while the whole system filter or part thereof is incorporated in the partial filter. 
     Although the use of a partial filter and an equalizer leads to some reduction of the complexity of the sample rate converter, the need for reducing this complexity still continues to exist. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a sample rate converter mentioned in the opening paragraph, whose complexity is further reduced. 
     For this purpose, the sample rate converter is characterized, in that the input of the equalizer is coupled to a first input of combining means, in that an output of the combining means is coupled to the input of a feedforward path and in that the output of the feedforward path is coupled to the output of the equalizer and, by way of the equalization filter, to a second input of the combining means. 
     By arranging the equalizer as a feedback system which comprises an equalization filter in the feedback path, there is achieved that the partial filter and the equalization filter show a strong resemblance. Hereinbelow it will be shown that the partial filter and the equalization filter show such a strong resemblance that a minimization of the complexity of the partial filter likewise leads to a minimization of the complexity of the equalizer. 
     Let it be assumed that the partial filter has a transfer H sys , the transfer of the equalizer H eg  is to be equal to: ##EQU1## Assuming further that the combining means comprise an adder, and that the transfer of the feedforward path is equal to 1, for H eg  may then be written: ##EQU2## In (2) H egf  is the transfer function of the equalization filter. Let (1) and (2) be equal, then: 
     From (3) it now follows that H egf  and H sys  indeed show a strong 
     
         H.sub.egf =1-H.sub.sys                                     ( 3) 
    
     resemblance. 
     An embodiment of the invention is characterized, in that the function h(t 1  +t 2 )(t 1 ,t 2  ≧0) equals g(t 1 )·h(t 2 ), in that a delay element having a delay 1/f s  is present between the output of the partial filter and the input of the equalizer, in that the input sample rate of the partial filter is equal to q·f s , in that the output sample rate of the partial filter is equal to f s , in that the input sample rate of the equalization filter is equal to p·f s , in that the output sample rate of the equalization filter is equal to f s , in that the feedforward path comprises a rest filter having an input sample rate f s  and an output sample rate f s  and summing transforming means having an input sample rate f s  and an output sample rate p·f s , the input of the feedforward path being coupled by way of the rest filter to a first input of the summing transforming means, in that the output of the partial filter is coupled to a second input of the summing transforming means and in that an output of the summing transforming means is coupled to the output of the feedforward path. 
     In this embodiment part of the partial filter and a corresponding part of the equalization filter are included in the feedforward path of the equalizer by way of the rest filter, so that part of the partial filter and the equalizer are combined resulting in a still further reduction of the complexity of the sample rate converter. Hereinbelow there will be explained that part of the partial filter and part of the equalizer may be combined to form the rest filter. 
     Let 1/f s  be equal to T and the input signal consist of samples a n  having a sample rate q·f s , there may then be derived for the response y 1  at instants jT of a system having impulse response h(t) to these samples: ##EQU3## 
     For the response y 2  at instants jT of the system having impulse response h(t) to samples b k  having the sample rate p·f s , there may be derived: ##EQU4## 
     From (4) and (5) there may be derived for y 1  and y 2  : ##EQU5## 
     If the samples a n  and b k  are representative of the same signal, y 1  (jT) and y 2  (jT) are to be equal. By utilizing this equality as well as the property of h(t 1  +t 2 )=g(t 1 )·h(t 2 )(=g(t 2 )·h(t 1 ), where f is independent of t 2  and g is independent of t 1 , it follows from (6) and (7): ##EQU6## (8) may also be written as: ##EQU7## In (9) it holds for S j-1  : ##EQU8## For S j-1  the following recurrent relationship may be derived: ##EQU9## 
     The sum of the samples a n , which sum is weighted by the function g, is determined by means of the partial filter. The sum of the samples b k , which sum is weighted by the function g, is determined by the equalization filter, whereas the rest filter recursively determines S j-1 . 
     The summing transforming means determine the sum of the output signals of the rest filter and the partial filter. Furthermore, the summing transforming means transform this sum into a suitable sequence of samples b k  for which it holds in the best way possible that the sum weighted by a function g is equal to the sum of the two input signals of the summing transforming means. 
     If the impulse response h(0) is equal to 0, a singularity arises in formula (9) because various factors are multiplied by 0. If h(0) is equal to 0, there may be derived for the samples b p (j-1)+k : ##EQU10## 
     A further embodiment of the invention is characterized, in that the sample rate converter further comprises at least one combination which includes a further partial filter, a further delay element, further combining means, a further equalization filter and a further rest filter, in that the input of the further partial filter is coupled to the input of the sample rate converter, in that the output of the further partial filter is coupled to a first of an additional pair of inputs of the summing transforming means and coupled, by way of the further delay element, to a first input of the further combining means, in that the output of the summing transforming means is coupled to the second input of the further combining means by way of the further equalization filter, and in that the output of the further combining means is coupled to the second of the additional pair of inputs of the summing transforming means by way of the further rest filter. 
     In this embodiment a plurality of equivalent sections is added to the sample rate converter. This is advantageous in that a system filter may be obtained having a steeper filter curve. This is often necessary for sufficiently suppressing noise in the input signal, for example, noise coming from aforementioned sigma-delta modulator. 
     A further embodiment of the invention is characterized, in that the partial filter comprises in addition to first Table means a serial-to-parallel converter for converting q serial input samples to q parallel output samples, in that the input of the partial filter is coupled to the input of the serial-to-parallel converter, in that the q outputs of the serial-to-parallel converter are coupled to q inputs of the first Table means and in that an output of the Table means is coupled to the output of the partial filter. 
     These measures provide a simple embodiment for the partial filter while only the serial-to-parallel converter operates at a high frequency. 
     A further embodiment of the invention is characterized, in that the impulse response of the combination formed by the partial filter and the rest filter and also the impulse response of the combination formed by the equalization filter and the rest filter comprises at least an exponential function. 
     An exponential function is a function that can be implemented in a simple manner and has the property of h(t 1  +t 2 )=g(t 1 )·h(t 2 ) for t 1 , t 2  ≧0. 
     A further embodiment of the invention is characterized, in that the ratio of two successive samples of the impulse response is a power of two. 
     As a result of this choice, multiplications necessary for determining the weighted sums may be replaced by much simpler shift operations which leads to a further reduction of the complexity of the sample rate converter. 
     A preferred embodiment of the invention is characterized, in that the combination of the partial filter and the rest filter comprises at least two imaginary zeros. 
     Since zeros are situated on the imaginary axis, zeros are developed in the frequency characteristic of the filter, so that the suppression of out-of-baseband signals is enhanced without a more complex circuit being necessary for this purpose. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will now be further explained with reference to the drawing Figures, in which like elements will be denoted by like reference characters, in which: 
     FIG. 1 shows a block diagram of a sample rate converter according to the invention; 
     FIGS. 2a through 2e show frequency spectrums of various signals as they may occur in a sample rate converter as shown in FIG. 1 at points a through e, respectively; 
     FIG. 3 shows an embodiment of the sample rate converter according to the invention; 
     FIG. 4ashows a delay unit in which, besides, the input signal is multiplied by a factor of 0.25; and 
     FIG. 4b shows a delay unit in which, besides, the input signal is multiplied by a factor of 0.5. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the sample rate converter as shown in FIG. 1 a partial filter 2 is supplied with an input signal a having a sample rate q·f s , where q equals 3. The output of the partial filter 2 is connected to the input of an equalizer 3. 
     The input of the equalizer 3 is formed by a first input of combining means constituted in this case by an adder 4. The output of the adder 4 is connected to the input of the feedforward path in this case formed by a sample rate increasing filter 6. The output of the sample rate increasing filter 6 forms the output of the sample rate converter. The output of the sample rate increasing filter 6 is connected to a second input of the adder 4 by way of an equalization filter 7. The input of the equalization filter 7 is connected to the input of a sample rate reducer 8 and to the input of a sample rate reducing filter 10. The output of the sample rate reducer 8 is connected to a first input of a subtractor 12, the output of the sample rate reducing filter being connected to a second input of the subtractor 12. The output of the subtractor 12 likewise forms the output of the equalization filter 7. 
     The input signal a, having sample rate 3f s , is filtered in the sample rate reducing filter 2 having a low-pass characteristic and its sample rate is reduced by a factor of 3. The output signal of the sample rate reducing filter 2 is filtered in the equalizer 3 so that the effect of the filter 2 on the frequency spectrum of the desired part of the input signal is compensated. In addition, the equalizer 3, increases the sample rate by a factor of 2. The compensation of the low-pass character of filter 2 is effected by the equalization filter 7 in the equalizer. According to the inventive idea, this filter has a transfer function equal to: 
     
         H.sub.egf =1-H.sub.sys                                     (3) 
    
     This transfer function is realized according to the inventive idea by subtracting the output signal of the sample rate reducing filter 10, having transfer H sys , from the output signal of the sample rate reducer 8 having a transfer function equal to 1. 
     The sample rate increasing filter 6 increases the sample rate of its input signal by a factor of 2 and likewise provides that spectral components in the input signal situated between 1/2 f s  and f s  are eliminated. The latter will be further explained with reference to the FIGS. 2a to 2d. 
     FIG. 2a shows the spectrum of an input signal a of the sample rate converter. This spectrum may be divided into two frequency ranges, i.e. the frequency range accommodating the desired signals and the frequency range accommodating the undesired signals. The latter range is shown in grey. At the output of the sample rate reducing filter 2 the spectrum shown in FIG. 2b is present. From this drawing Figure it may be noticed that the cut-off frequency (for example, the 3 dB point) of the filter 2 is much lower than the maximum frequency occurring in the signal a. In addition, it may be noticed that the frequency spectrum is periodic with a rate f s  due to the reduction of the sample rate. Furthermore, it may be noticed that the undesired signal components exhibit a much stronger attenuation than the desired signal components. 
     The influence of a change of the sample rate on the frequency spectrum of a sampled signal is described, for example, in the title of &#34;Multirate Digital Signal Processing&#34; by R. E. Crochiere and L. R. Rabiner, published by Prentice-Hall (1983), ISBN 0-13-605162-6. 
     If it is assumed that the frequency spectrum of the output signal d in the interval between -f s  and f s  is to be equal to the desired part of the input signal a between -f s  and f s , the frequency spectrum of the signal e may be determined in a simple fashion. This frequency spectrum displays a high-pass characteristic and is furthermore periodic with a rate f s . The frequency spectrum of signal c is now found by adding the frequency spectrums of the signals b and e together. The frequency spectrum of signal c is now flat, but is still periodic with a rate f s . The sample rate increasing filter 6 eliminates the frequency components situated between 1/2 f s  and f s , so that the desired output signal d is obtained. From the frequency spectrum of the signal d it is clearly noticeable that the undesired components in the signal d are strongly reduced. 
     If the bandwidth of the desired part of the signal a exceeds f s  /2, the sample rate conversion may not be effected in the manner described hereinbefore, because the desired part of the output signal b of the partial filter then no longer satisfies the sampling theorem. 
     In that case the equalizer and the partial filter have to change places, so that the sample rate is first increased by the equalizer and then reduced by the partial filter. Because the signal processing is now to take place at a higher frequency, the sample rate converter will generally be more complex. 
     In the sample rate converter as shown in FIG. 3 the input signal is applied to a serial-to-parallel converter 20. The output of the serial-to-parallel converter 20 is connected to an input of first Table means formed in this case by a ROM 22 (32). The combination of serial-to-parallel converter 20 and ROM 22 (32) forms the partial filter (further partial filter). The output of the ROM 22 (32) is connected to an input of a delay element 24 (36) and to a first and a second input respectively, of an adder 29. 
     The output of the delay element 24 (36) is connected to a first input of an adder 26 (38). The output of the adder 26 (38) is connected to the input of a multiplying delay element 28 (40). The output of the multiplying delay element 28 (40) is connected to a second input of the adder 26 (38) and to a third and fourth input respectively, of the adder 29. A combination of adder 26 (38) and the multiplying delay element 28 (40) forms the rest filter (further rest filter). 
     The output of the adder 29 is connected to a ROM 31 which produces parallel output samples for each input sample q. The adder 29 and the ROM 31 form the summing transforming means. The outputs of the ROM 31 are connected to inputs of a parallel-to-serial converter 33 and to inputs of second Table means, a ROM 30 (34) in this case. The output of the ROM 30 (34) is connected to a negative input of the adder 26 (38). The ROM 30 and the ROM 34 form the equalization filter and the further equalization filter respectively. 
     In the sample rate converter as shown in FIG. 3 the serial-to-parallel converter 20 converts q input samples to a word of p parallel output samples. These parallel output samples are converted to a single output sample by way of the ROM 22 (32). The number of values the input samples may assume is limited to 2 p , due to which also the number of different input words of the ROM 22 or 31 respectively, will be limited. If the input symbols of the serial-to-parallel converter are equal to a n , the ROM 22 generates the sum of q successive input samples weighted by the function g(t). In the serial-to-parallel converter as shown in FIG. 3 the impulse response h(t) is equal to a sum of exponential functions of time in which each exponential function is realized by its own partial filter and rest filter. In the example shown in FIG. 3 the impulse response is equal to: ##EQU11## For the output signal S 1  of ROM 22 then holds: ##EQU12## For the output signal S 3  of ROM 32 then holds: ##EQU13## The rest filter constituted by the adder 26 and the delay element 28 has an impulse response h(t)=(1/2) t/T  and the further rest filter constituted by adder 38 and delay element 40 has an impulse response h(t)=(1/4) t/T . 
     The adder 29 now determines the total response of the various sub-responses. The ROM 31 determines p output samples on the basis of the single samples at its input, the response of the system filter to the p output samples matching the input sample in the best way possible. For the relation between input samples and output samples of the ROM 31 the following is to hold: ##EQU14## On the basis of formula (18) the contents of ROM 31 may be determined in a simple manner. 
     The number of possible values that can be assumed by the output samples is always limited. This means that a number of values of the input samples of the ROM 31 are represented by the same output sample. In that case the input samples of ROM 31 are quantized to the number of possible values for which (18) holds exactly. Hereinbelow, an example of this quantization and the associated relation between the input signals and output signals of the ROM 31 will be given for p equal to 3 and the number of possible values of the input samples of ROM 31 equal to 2(+1 and -1). 
     
         ______________________________________b.sub.1b.sub.2   b.sub.3                 S.sub.5 v[16]                          S.sub.5______________________________________-1   -1        -1     -4.45    S.sub.5 ≦ -3.42 1   -1        -1     -2.40    -3.42 &lt; S.sub.5 ≦ -2.00-1    1        -1     -1.60    -2.00 &lt; S.sub.5 ≦ -1.03-1   -1         1     -0.45    -1.03 &lt; S.sub.5 ≦ 0 1    1        -1      0.45    0 &lt; S.sub.5 ≦ 1.03 1   -1         1      1.60    1.03 &lt; S.sub.5 ≦ 2.00-1    1         1      2.40    2.00 &lt; S.sub.5 ≦ 3.42 1    1         1      4.45    3.42 &lt; S.sub.5______________________________________ 
    
     In this Table the fourth column shows for which values of S 5  formula (18) holds exactly. For different values of S 5  these values are quantized to the nearest value according to column 4. Column 5 denotes at which values of S 5  the various output samples b 1 ,b 2  and b 3  are generated. The parallel-to-serial converter 33 converts the parallel output signal of the ROM 31 to a serial output signal. 
     The equalization filter is arranged as parallel operating sections, as is the partial filter. The equalization filter constituted by the ROMs 30 and 34 determines on the basis of the q parallel output signals of ROM 31 the desired feedback signals which are applied to the rest filters. 
     The following holds for the output signal of the ROM 30: ##EQU15## The output signal of ROM 34 is equal to: ##EQU16## 
     In the adder 29, the ROM 31 or in the ROMs 30 and 34 respectively, a multiplication by a factor of 1/2 is still to be performed to determine the sum of the samples b which sum has been weighted by the function g, due to the multiplication by h(0) (=2) in formula (9). 
     A first particular situation occurs if q=1 with p≠1. 
     In this situation the ROM 31 and the serial-to-parallel converter 33 may be omitted, so that the output signal of the adder 29 likewise forms the output signal of the sample rate converter. The ROM 30 and the ROM 31 then produce an output signal which depends on no more than a single input sample, which results in a simple embodiment. Furthermore, it can be noticed that except for the serial-to-parallel conversion at the input, all operations may be performed at the low output sample rate. 
     This situation occurs, for example, when there is a conversion from a 1-bit signal coming, for example, from a sigma-delta modulator, to a p-bit PCM signal. The system filter is then to suppress the quantization noise which enhances with increasing frequency, so that the system filter no longer has any influence on the sample rate converter output signal outside the baseband. In order to maintain the noise power caused by out-of-baseband noise of the sample rate converter output signal below a specific value N, the frequency characteristic of the system filter is to meet the following requirement: ##EQU17## In (21) S b  (ω) is the quantization noise spectrum of the input signal of the sample rate converter and |H(ω)| 2  is the squared absolute value of the transfer function of the system filter. (21) proves that a steep decline of the system filter past f s  /2 yields good noise suppression. 
     According to a preferred embodiment of the invention this may be realised without enhancing the complexity of the system filter by giving the transfer function two imaginary zeros while real poles are retained. In order to make this possible, the embodiment shown in FIG. 3 is to comprise at least 3 parallel filter sections, while one or two sections produce a negative output signal in the case of a positive input signal. 
     An example of an impulse response corresponding to such a transfer function is: ##EQU18## 
     In FIG. 4a the multiplying delay circuit comprises a delay circuit in which all the bits except for the two least significant bits are transported to a memory circuit 42. The output bits of the memory circuit 42 are extended by two most significant bits having a logic value &#34;-1&#34;. The effect of this is that the most significant bits are shifted two places to a less significant position, which narrows down to a multiplication by a factor of 1/4. In the circuit as shown in FIG. 4b a shift by one bit position is realized in similar fashion, which narrows down to a multiplication by a factor of 1/2.