Abstract:
A high speed data transmission channel, preferably embodied in a circuit for writing to a read channel for a hard disk drive, is provided. The channel includes a preamplifier writer, a non-uniform transmission line, and a head. The writer is configured to transmit pulses to the head via the transmission line at a transmission speed. Each pulse has a pulse width. Each pulse may experience interference. The writer is also configured to eliminate interference to each pulse by causing the interference to occur in a differential mode, which causes the interference to cancel out. A transmission time for each pulse is inversely proportional to the transmission speed. The non-uniformity of the transmission line may entail an exponential broadening of a trace width of the transmission line such that when the pulse width is greater than or approximately equal to the transmission time, the pulse propagates from the writer to the head substantially undistorted.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. 119(e) to U.S. provisional Application Ser. No. 60/265,578, entitled “Preamplifier Writer”, filed 2, Feb. 2001, the contents of which are incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an apparatus and a method for transmitting digital data at high speed over a transmission channel, and preferably for writing to a hard disk drive at high operating speeds. 
     2. Description of the Related Art 
     A hard disk drive uses a recording head to receive data from a device that writes, or transmits, the data. Typically, the data propagates from the writer to the head via a transmission line. The data is transmitted in the form of electrical pulses, where each electrical pulses can be characterized by a pulse width which is measured in seconds. The transmission rate of the data is an important circuit characteristic, because a higher transmission rate allows for a larger volume of information to be communicated. Therefore, a common objective of circuit designers is to increase the maximum data transmission rate. Typically, the transmitted pulse is also amplified before it is received. Thus, if there is any signal interference prior to amplification, the received signal may be distorted. Therefore, another common objective of circuit designers is to reduce or eliminate signal interference. Circuitry and transmission lines for providing high-speed communications between writing devices and receiving devices are well known in the art and are the subject of many patents. 
     In most cases, even when a circuit is designed to operate at a high data transmission rate, the transmission time (i.e., the length of time required for the pulse to propagate from the writer to the head) is greater than the pulse width. In these cases, there are no circuit design considerations relating to intra-pulse characteristics; the pulse is transmitted and received in an intact form. However, when a circuit is being operated at such a high speed that the transmission time is less than (or even nearly equal to) the pulse width, the circuit designer must take several intra-pulse characteristics into account, such as the rise time and fall time of the pulse and the wave propagation characteristics of the transmission line. In particular, if the voltage polarity at the writer (transmitter) changes before the previously transmitted pulse has been received at the head (receiver), then the previously transmitted pulse may be severely distorted before it is received, and the data quality may be degraded. Thus, a dilemma for writing to a hard disk drive via a high speed channel is presented. 
     SUMMARY OF THE INVENTION 
     The present invention is intended to overcome the problems noted above when the propagation time for a pulse is less than the pulse width, and provides a preamplifier writer system for a high-speed channel that preserves the integrity of transmitted pulses. In one aspect, the invention provides a circuit for writing to a read channel for a hard disk drive. The circuit may include a preamplifier writer, a non-uniform transmission line, and a head. The writer may be configured to transmit pulses having a pulse width to the head via the transmission line at a transmission speed. Each pulse may experience interference. The writer may also be configured to eliminate interference to each pulse by transmitting the pulses in a differential mode, causing the interference to be reduced. A transmission time for each pulse is inversely proportional to the transmission speed. In one aspect, the non-uniformity of the transmission line is attained by exponential broadening of a trace width of the transmission line. In another aspect, the transmission line non-uniformity is selected so that when the pulse width is greater than or approximately equal to the transmission time, the pulse propagates from the preamplifier writer to the head substantially undistorted. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a basic circuit architecture for a preamplifier writer to a hard disk drive. 
     FIG. 2 shows a more detailed circuit diagram for the preamplifier writer of FIG.  1 . 
     FIG. 3 shows a series of on-off profiles for switches used in the preamplifier writer circuitry of FIG.  2 . 
     FIG. 4 shows a simplified circuit diagram illustrating steady state operation of the preamplifier writer. 
     FIG. 5 shows a basic RL circuit and the voltage and current effects upon an RL circuit when a step voltage is applied. 
     FIG. 6 illustrates a transition caused by applying a step voltage in order to change the direction of a current through an inductor in the preamplifier writer. 
     FIG. 7 shows a simplified circuit diagram illustrating the resulting steady state operation of the preamplifier writer after the transition of FIG. 6 occurs. 
     FIG. 8 shows a model circuit diagram for a non-uniform transmission line. 
     FIG. 9 illustrates an effect of reflecting voltages due to mismatched impedances along a non-uniform transmission line. 
     FIG. 10 shows a circuit diagram for a preamplifier writer including a load resistor across the load inductor. 
     FIG. 11 shows a circuit diagram for a preamplifier writer according to the present invention including two matching pairs of non-uniform transmission lines. 
     FIG. 12 illustrates a relationship between impedance profile, decay rate, and circuit efficiency for a preamplifier writer according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention addresses the need for innovative circuit design characteristics to be implemented in high-speed channels, such as a read channel of a hard disk drive, when the transmission time of a pulse exceeds or approximately equals the pulse width. In the development of the present invention, the inventors have recognized that the physical characteristics of the transmission line can be chosen to effect various wave propagation effects. 
     Referring to FIG. 1, the basic architecture  100  of a preamplifier writer  105  to a recording head  110  of a hard disk drive is shown. The head  110  is modeled by an inductor. A channel is modeled by two pairs of non-uniform transmission lines  115  that are connected between the writer  105  and the head  110  in parallel. The transmission lines  115  are non-uniform in the sense that they each have a variable impedance. A 5-V power supply to the writer is modeled by a +2.5 V terminal  120  and a −2.5 V terminal  125 ; a third terminal  130  is connected to electrical ground. 
     Referring to FIG. 2, the circuitry of the writer  105  includes the terminals  120 ,  125 ,  130 , and switches S 1    205 , S 1 ′  210 , S 2    215 , S 2 ′  220 , and S 3    225 . Referring also to FIG. 3, it is assumed that when the circuit  100  operates in a steady state, switches S 3    225  and S 1 ′  210  are on, and nodes a  230 , b  235 , a out    240 , and b out    245  are all at ground. Current I is flowing through inductor L  110 . Although the non-uniform transmission lines  115  are still employed, they behave like standard (uniform) transmission lines because at steady state, there are no transient pulse effects, and therefore the non-uniformities of the transmission lines do not affect the circuit operation. A simplified circuit diagram of the steady-state operation is shown in FIG.  4 . 
     Next, it is assumed that it is desired to change the direction of the current I through the inductor L  110  (and therefore, the circuit will temporarily not operate in the steady state). Referring to FIG. 3, the switches S 3  and S 1 ′ open (i.e., they change from on to off), and switch S 2  closes briefly (i.e., it changes from off to on). Then, switch S 2  opens and switches S 3  and S 2 ′ close. Thus, in effect, the end result is a new steady state operation in which S 3  and S 2 ′ are on instead of S 3  and S 1 ′ being on; in other words, the current direction has been reversed. 
     By using a paired transmission line  115  and placing each switch S 1 , S 1 ′, S 2 , and S 2 ′ opposite its respective paired switch with respect to the voltage polarities and current sources, a differential mode is introduced to the circuit. Thus, any interference that is added to the input signal as a result of the switching operation described above is also added negatively on the other side of the circuit. For example, referring to FIG. 2, any interference that is added to the signal that is observable at node a  230  must also be added negatively to the signal that is observable at node b  235 . Thus, when the paired input signal finally arrives at the head  110 , the interference additively cancels itself out. 
     Referring to FIG. 6, the operation of the circuit during the transition from I=−50 mA to I=+50 mA is illustrated. The voltage of node a  230  shifts from ground (0 V) to −2.5 V, and the voltage of node b  235  shifts from ground to +2.5 V. The inductor L  110  acts like an open circuit. Once the voltage transient is completed, nodes a  230  and b  235  will decay back to ground with time constant=L/R. By choosing a small value of R, the decay is small, and the nodes a and b rapidly return to ground. It is noted that at all times, the voltage at node a  230  is exactly equal to the negative (i.e., the additive inverse) of the voltage at node b  235 . The resulting steady state circuit is shown in FIG.  7 . 
     The basic equation that relates voltage and current across an inductor is 
     
       
           V=L *( di/dt )  (Equation 1). 
       
     
     Therefore, if the current direction changes very rapidly, a high value of voltage will result. This may result in damage to a semiconductor chip on which the circuit is built. Therefore, care must be taken to ensure that the voltage does not exceed the maximum that the chip can withstand. 
     Equation 1 can be rewritten mathematically as follows: 
     
       
         Δ I =(1 /L )*∫ t   Vdt   (Equation 2). 
       
     
     Referring to FIG. 5, the voltage function V(t)  505  can be assumed to be a constant voltage V s  for a duration T P . Using this assumption, Equation 2 simplifies to 
     
       
         Δ I =(1 /L )* V   s   T   P   (Equation 3). 
       
     
     If a conventional approach is attempted for a high-speed implementation of a writer for a hard disk drive, the following exemplary values may be used: Channel speed (data rate)=2 GHz; L=60 nH;)I=100 mA (from −50 mA to +50 mA); and T P =250 ps. Therefore, V s =24 V, which exceeds the maximum voltage for the chip. Thus, an alternative approach to increasing the data rate is required. 
     The ability to increase the data rate is determined by the ability to more quickly change the direction of the current across the inductor L  110 . This results in a higher voltage V s , but the voltage is limited by the semiconductor chip characteristics. Therefore, an alternative method of changing the current direction more quickly is sought. The approach taken by the present inventors is to use a non-uniform transmission line  115 . Referring to FIG. 8, a simple model of a non-uniform transmission line  800  includes a voltage source  805 , a source resistor  810  having resistance=R s , a series of three impedances Z 1    815 , Z 2    820 , and Z 3    825 , and a load resistor  830  having resistance=R L . The series of three impedances  815 ,  820 ,  825  represents a cascade of three separate uniform transmission lines. The voltage at a point between R s    810  and Z 1    815  is designated V 1 ; the voltage at a point between Z 1    815  and Z 2    820  is designated V 2 ; the voltage at a point between Z 2    820  and Z 3    825  is designated V 3 ; and the output voltage across R L    830  is designated V o . 
     The voltages V 1 , V 2 , V 3 , and V o  can be calculated as functions of R s , Z 1 , Z 2 , Z 3 , and R L . Assuming that the voltage source  805  provides a step voltage having magnitude equal to V in =1 V, then by using Ohm&#39;s law, it is seen that V 1 =Z 1 /(Z 1 +R s ), and the voltage V 1  drops across Z 1 . Referring also to FIG. 9, once this voltage reaches the boundary  905  between Z 1  and Z 2 , part of it reflects back due to the mismatched impedances. By setting Z 2 &gt;Z 1 , the governing equations for the reflection phenomenon are 
     
       
           V   1r   =V   1 *( Z   2   −Z   1 )/( Z   2   +Z   1 )  (Equation 4) 
       
     
     and 
     
       
           V   2   =V   1 *2 Z   2 /( Z   2   +Z   1 )  (Equation 5). 
       
     
     Therefore, by setting R L &gt;Z 3 &gt;Z 2 &gt;Z 1 &gt;R s , a similar set of transfer functions can be derived for V 2 , V 3 , and V o . 
     By maximizing the voltage V o , the rate at which the current direction can be changed will also be maximized, and therefore the data rate will also be maximized. Maximizing the voltage V o  is accomplished by maximizing the transfer function shown in Equation 5. Furthermore, rather than using a cascade of only three impedances, the number of impedances being cascaded can be increased infinitely. The result of maximizing this transfer function using an infinite cascade of impedances is that a maximum value of V o  is realized by exponentially increasing the impedance Z as a function of transmission line length 1. Impedance profiles other than exponential, for example, a binomial sequence or a Chebyshev sequence, also provide comparable gain and may be preferable due to other practical considerations such as the decay rate of the input pulse (see discussion below). All such alternatives are included within the scope of the present invention. 
     One embodiment of the non-uniform transmission line may be implemented as a trace on a circuit board having a constant depth. Because impedance Z is directly proportional to each of the three spatial dimensions (i.e., length, depth, and width of the trace), an exponential increase in the impedance Z as a function of length can be implemented simply by exponentially increasing the width of the trace. This results in a horn-shaped transmission line. The governing equation for the maximized V o  is 
     
       
           V   o =0.5 *V   in *( R   L   /R   s ) 1/2   (Equation 6). 
       
     
     Alternative implementations of the non-uniform transmission line include increasing the width of the trace in the circuit board according to sequences other than an exponential sequence, such as a piecewise linear sequence, a binomial sequence or a Chebyshev sequence. Other alternatives include varying the depth of the trace according to some sequential function, or varying both trace depth and trace width. 
     Referring to FIG. 10, the above described process results in a circuit that maximizes the load voltage V o  across the inductor L  110 . However, there will also be a resistance R L    1005  that is the equivalent parallel resistance to the inductor L  110 , and it may be difficult to precisely ascertain the magnitude of the resistance R L . This may cause ringing in the circuit. 
     Referring to FIG. 11, another embodiment of the invention includes a preamplifier writer that operates similarly as the writer described above with reference to FIG. 2, and a recording head that is modeled by the inductor  110 . The embodiment also includes two identical pairs of non-uniform transmission lines  115  for communications between the writer and the recording head. The non-uniformities are implemented by an exponentially widening trace in a circuit board. The use of two separate pairs of transmission lines ensures that a signal that propagates along either transmission line pair will see a matched impedance at the recording head, thereby eliminating any problem of ringing that would be caused by a mismatched load impedance. 
     In the absence of a second pair of transmission lines, the magnitude of the ringing problem is a function of the degree to which the output impedance of the transmission line is mismatched with the equivalent parallel resistance  1005  of the inductor  110 . However, the equivalent parallel resistance  1005  is not directly measurable. Therefore, if the degree of mismatch is large, for example, if the output impedance of the transmission line Z L =100 Σ and the resistance  1005  R L =1000 Σ, the embodiment shown in FIG. 11 would be preferable. However, if the degree of mismatch is not large, for example, if Z L =100 Σ and R L =120 Σ, the embodiment shown in FIG. 10 without the second pair of transmission lines would be preferable, because otherwise the gain realized by the circuit would be reduced by an unnecessary parallel load. 
     As an example of an impedance profile, suppose that the impedance at the beginning of the non-uniform transmission line is set to Z s =5 Σ and the impedance at the end of the line is set to Z L =100 Σ, and the impedance Z increases exponentially as a function of length. Setting V in =5 V as shown in FIG.  1  and applying Equation 6, a result of V o =11.18 V is obtained; this represents a gain factor of about 2.2, which translates directly to an increase in maximum operating speed of the circuit. 
     Another circuit design consideration is the pulse width T P . Referring to FIG. 12, using a step function as an input voltage, Equation 6 provides an expression for the output voltage: V o =0.5*V in *(R L /R s ) 1/2 . However, the output voltage will immediately begin to decay to V decay =V in *R L /(R L +R s ) (Equation 7). The difference between V o  and V decay  equates to an “overshoot” that occurs at the pulse transitions, and the magnitude of the overshoot directly affects the circuit efficiency. The rate of decay is dependent upon the impedance profile of the non-uniform transmission line. It has been found that for optimum performance, the pulse width T P  should be chosen such that it is less than 90% of the time required for the output voltage from V o  to V decay . However, the pulse width T P  is also directly proportional to the change in current) I. Hence, a wider pulse width T P  results in a more efficient circuit (i.e., less overshoot). Therefore, the pulse width T P  should be maximized within the decay rate criterion described above, and the decay rate is a design consideration affecting the choice of impedance profile for the non-uniform transmission lines. 
     While the present invention has been described with respect to what is presently considered to be the preferred embodiments, i.e., an implementation in a hard disk drive, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. For example, it is to be understood that the invention is applicable to other data transmission circuitry such as optical and magnetic read circuits, cellular telephony, and digital electronic transmitters and receivers. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.