Abstract:
A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/418,551 filed on Oct. 15, 2002, which is hereby incorporated by reference in its entirety.  
       RELATED APPLICATIONS  
       [0002]    This application is related to U.S. patent application Ser. No. 09/858,528, filed on May 7, 2001 (Docket No. MEG00-003) and to U.S. patent application Ser. No. ______, filed on ______, (Docket No. MEG02-008), both of which are assigned to one of the joint Assignees of the present invention and which are hereby incorporated by reference in their entirety. 
     
    
     
       FIELD OF THE INVENTION  
         [0003]    The present invention relates to the fabrication of integrated circuit (IC) devices, and more particularly to the fabrication of wire bond pads over underlying active devices, passive devices and/or weak dielectric layers in IC devices.  
         BACKGROUND OF THE INVENTION  
         [0004]    Integrated circuits (ICs) are semiconductor devices that contain active devices such as transistors and diodes and/or passive devices such as capacitors, resistors and inductors. Performance characteristics of the ICs are typically improved by reducing the dimensions of the active and/or passive devices in the IC. The reduced dimensions of the IC devices allow an increased number of devices to be fabricated in the same chip area to provide additional functionality and/or the same number of devices can be fabricated in a reduced chip area. The reduced dimensions also typically reduce I 2 R losses and increase switching speeds. One restraint on further size reductions relates to layout requirements of data input/output or power/ground connections that are made to the IC.  
           [0005]    Typically, the IC is mounted on a package. Solder bumps and bond wires on the package are connected to bond pads on the IC. Pins provide external connections to the package. The bond pads are typically made of aluminum (Al) and/or aluminum alloy (Al-alloy). The bond pads are deposited onto the IC using conventional sputtering and photolithography techniques. The conventional process for forming bond pads is both expensive and complex.  
           [0006]    The bond pads formed on the IC are typically located in a first region of the IC. The bond pads provide connections to metal interconnects and vias, which in turn provide connections to active and/or passive devices of the IC. The bond pads are usually not formed over a second region that contains the active and/or passive devices. For example, the first region may include an outer perimeter of the IC that surrounds the second or inner region of the IC.  
           [0007]    One reason for the mutually exclusive first and second regions is related to thermal and/or mechanical stress that occurs during wire bonding. An outermost metal interconnection layer is typically covered by a passivation layer. Openings in the passivation layer expose contact pads, which are patterned in the outermost metal interconnect layer. Wires are bonded to the contact pads. If active regions are located below the contact pads, the processing will damage the underlying dielectric, the active devices and/or the passive devices. The dielectric is particularly susceptible if it is formed using a weak or low-k dielectric metal.  
           [0008]    Referring now to FIG. 1 a , conventional bond pads  10 - 1 ,  10 - 2 , . . . ,  10 - n  (collectively identified by  10 ) are typically arranged in a first region  12  of an integrated circuit (IC) die  14 . The first region  12  may correspond to an outer region or perimeter of the IC  14 , although other arrangements may be used. The bond pads  10  are laterally displaced from a second region  18 , which is separate from the first region  12 . The second region  18  contains underlying dielectric layers, active devices, and/or passive devices of the IC die  14 . The second region  18  may be a central region that is surrounded by the outer region. Positioning the dielectric layer(s), the active device(s) and/or the passive device(s) in laterally separate regions avoids damage that may be caused by thermal and/or mechanical stress that occurs during wire bonding.  
           [0009]    Referring now to FIG. 1 b , an exemplary active device  30  is located in the second region  18  and includes a transistor  32  with a gate  34 , a source  36 , a drain  38 , and field isolation regions  40 . While the transistor  32  is shown for illustration purposes, other types of active and/or passive devices may be located in the second region  18 . One or more dielectric layers  44 - 1  and  44 - 2  and one or more metal interconnect layers  48 - 1 ,  48 - 2 , . . . , and  48 - p  (collectively identified as  48 ) and vias (not shown) are used to provide connections between the active and/or passive devices and contact pads  49 , which are formed in the outermost metal interconnect layer  48 . Vias are typically used to provide connections between the metal interconnect layers.  
           [0010]    A passivation layer  58  is typically formed on top of the outermost metal interconnect layer. Openings  54  in the passivation layer expose the contact pads  49 . Wire  50  is bonded to the contact pad through passivation opening  54 . While only one active device and one bond pad is shown, additional active devices, passive devices and/or bond pads can be provided. The passivation layer is typically deposited using chemical vapor deposition (CVD), although other processes may be used. The metal interconnect layers and vias are typically made of Al or Al-alloy, although other materials may be used.  
           [0011]    The conventional layout depicted in FIGS. 1 a  and  1   b  requires lateral separation between the first region  12  containing the bond pad(s) and the second region  18  containing the underlying dielectric layer(s), active device(s) and/or passive device(s). This requirement significantly increases the size of the IC die  14  because the second region  18  is not available for bond pads.  
         SUMMARY OF THE INVENTION  
         [0012]    A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with at least one active device and/or passive device. One or more dielectric layers are arranged adjacent to, or over the active and/or passive devices. One or more metal interconnect layers are arranged adjacent to, or over the active and/or passive devices. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.  
           [0013]    In other features, a wire is bonded to the bond pad in a wire bonding region. The wire bonding region is formed over the passivation opening or is laterally displaced from the passivation opening. The dielectric layers include a low-k dielectric material. The passivation layer includes one or more layers of inorganic material.  
           [0014]    In still other features, the bond pad includes an adhesion layer arranged adjacent to, or over, the passivation layer and the exposed contact pad. A first layer is arranged adjacent to, or over the adhesion layer. A second layer is arranged adjacent to the first layer.  
           [0015]    In still other features, the adhesion layer includes at least one of titanium (Ti), chromium (Cr), titanium tungsten (TiW) and titanium nitride (TiN). The first layer includes gold that is deposited by sputtering. The second layer includes gold that is deposited by electroplating. The second layer has a hardness range of less than about 150 Hv. The gold of the second layer has a purity that is greater than or equal to about 97% and a thickness that is greater than or equal to 1 μm.  
           [0016]    Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:  
         [0018]    [0018]FIGS. 1 a  and  1   b  illustrate plan and cross-sectional views of conventional bond pads in an IC die;  
         [0019]    [0019]FIG. 2 illustrates steps of method for fabricating bond pads on an IC die according to the present invention;  
         [0020]    FIGS.  3 - 5  illustrate processing of the IC die according to the steps shown in FIG. 2;  
         [0021]    [0021]FIG. 6 is a cross-sectional view of another embodiment of the bond pad according to the present invention;  
         [0022]    [0022]FIG. 7 illustrates a bond pad with a wire bonding region that is laterally displaced from a passivation opening;  
         [0023]    [0023]FIG. 8 illustrates a bond pad and an enlarged contact pad formed in a top metal interconnect layer;. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]    The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify the same elements.  
         [0025]    Conventional methods for wire bonding that were described above damage underlying dielectric layers, active devices and/or passive devices. To avoid damage to these structures during wire bonding, these structures are usually located in areas that are not under the bond pads. This layout requirement significantly increases the IC die size, which increases the cost of the IC. As will be described below, the present invention allows wire bonding, and the pads to which bond wires are attached, over the dielectric layers and/or the active and/or passive devices without damaging the dielectric layers or the devices. As a result, the IC die size can be reduced, which lowers the cost of the IC.  
         [0026]    Referring now to FIGS. 2 and 3, steps for fabricating an improved IC die according to the present invention are shown. Initially, a wafer cleaning process is performed on an IC die  100  in step  104 . In step  106 , an adhesion layer  108  is deposited onto the passivation layer  58 . The adhesion layer  108  is also deposited in the passivation opening  54  and/or into the array of passivation openings and onto the contact pad(s)  49 . The passivation opening  54  preferably has a width of approximately 0.5 μm or greater, although widths that are greater than 0.1 μm are also acceptable. The passivation layer  58  is preferably formed using one or more layers of inorganic materials. For example, the passivation layer  58  may include a first layer of a first material and a second layer of a second material. In a preferred embodiment, the first material is silicon oxide having an approximate thickness of 0.5 μm and the second layer is silicon nitride having an approximate thickness of 0.7 μm.  
         [0027]    In preferred embodiments, the adhesion layer  108  includes at least one of titanium tungsten (TiW), titanium nitride (TiN), titanium (Ti), and chromium (Cr), although other suitable materials can be used. In a preferred embodiment, the adhesion layer  108  has a thickness of approximately 3000 Angstroms and is deposited by sputtering, although other processes and thicknesses can be used.  
         [0028]    In step  112 , a first or seed layer  116  is deposited onto the adhesion layer  108 . The first layer  116  is also deposited onto the adhesion layer  108  in the passivation opening  54  and/or the array of passivation openings. The first layer  116  is formed of a seed layer for the subsequent thick metal electroplating. In a preferred embodiment, the first layer  116  includes gold (Au). In a preferred embodiment, the first layer  116  is deposited by sputtering to a thickness of approximately 1000 Angstroms, although other suitable processes and thicknesses can be used.  
         [0029]    Referring now to FIGS. 2 and 4, a bond pad region  120  is defined in step  124 . In a preferred embodiment, the bond pad region  120  is defined using conventional photolithography. The bond pad region  120  is defined by photoresist  130 . In a preferred embodiment, the photoresist  130  is a liquid coating having a thickness of 20-22 μm, although other processes and thicknesses can be used. For example, a dry film photoresist can also be used.  
         [0030]    In step  134 , a second or bulk layer  136  is formed in the bond pad region  120  that is defined by the photoresist  130 . The second layer  136  is preferably formed of a compliant material. The second layer  136  is also formed in the passivation opening  54  and/or array of passivation openings. In a preferred embodiment, the second layer  136  is electroplated to a thickness that is greater than about 1 μm to provide adequate stress absorption, although other processes and thicknesses can be used. The second layer  136  preferably includes gold (Au) having a purity that is greater than or equal to about 97%. The second layer  136  preferably has a hardness range that is less than or equal to approximately 150 Hv (Vickers Hardness). The second layer  136  includes a relatively soft material to increase stress absorption properties of the second layer.  
         [0031]    Referring now to FIGS. 2 and 5, in step  138 , the photoresist  130  is stripped. In step  142 , the first layer  116  that is located outside of the bond pad region  120  is etched. In step  144 , the adhesion layer  108  that is located outside of the bond pad region  120  is also etched. Steps  142  and  144  may be completed in a single step if desired. In step  150 , additional processing is performed such as die sawing or other suitable processing. In step  154 , a wire  156  is bonded to the second layer  136 . In a preferred embodiment, the wire  156  includes Au.  
         [0032]    Referring now to FIG. 6, an alternate exemplary embodiment of an IC die  200  is shown to include a substrate  204 . Active and/or passive devices that are generally identified at  208  are formed on the substrate  204 . The IC die  200  includes one or more dielectric layers  212  and  214  and metal interconnect layers  216  and/or vias. The interconnect layers  216  and vias connect the devices  208  to other devices  208  and/or to one or more contact pads  220 . A passivation layer  224  is formed over an outermost metal interconnect layer  216 , which includes the contact pads  220 . The passivation layer  224  may include one or more passivation openings  225 , which expose the contact pads  220 . A wire bonding structure  226  includes an adhesion layer  228 , a first layer  232 , and a second layer  234  as described above. A wire  240  is bonded to the bulk layer  234  as described above. As can be appreciated, the dielectric layers  212  and  214  may be susceptible to damage when conventional bond pad structures are used, particularly when the dielectric layers  212  and  214  include low-k dielectric materials. Likewise, the active and/or passive devices also may be susceptible to damage when conventional bond pad structures are used. The bond pad structure according to the present invention eliminates damage to these structures.  
         [0033]    Referring now to FIG. 7, the width of the second layer  234 , the first layer  232 , and the adhesion layer  228  in FIG. 6 have been increased relative to the contact pads  220 . A wire bonding region  250  is laterally displaced with respect to the passivation opening  225  in the passivation layer  224  to provide additional layout flexibility. In FIG. 7, the second layer  234  is located over at least one of the active and/or passive devices  208 . The wire bonding region  250  is laterally spaced from the passivation opening  225 .  
         [0034]    Referring now to FIG. 8, the outermost interconnect layer includes a wider contact pad  260  instead of one or more narrower contact pads  220  that are shown in FIGS. 6 and 7. A wider opening  262  is formed in the passivation layer  224  to provide an increased contact area. The increased contact area reduces the resistance of the bond pad/contact pad connection. In a preferred embodiment, the wider passivation opening  262  has a width of 40 μm to 100 μm.  
         [0035]    There are numerous variations of the present invention that will be apparent to skilled artisans. For example, the number of dielectric layers  212  and  214  and interconnect layers  216  can be varied. In addition, while only one opening is shown in the passivation layer  224 , additional openings can be provided as needed. The invention is also not limited as to the location of the openings in the passivation layer  224  relative to the wire bond region.  
         [0036]    The wire bonding regions can be aligned with or offset from the contact pads. These structures can likewise be formed over the active and/or passive devices without causing damage.  
         [0037]    An experiment was performed in which the structure of FIG. 6 was fabricated using a 4 μm thick electroplated Au as the second layer  234  and Fluorinated Silicate Glass (FSG) as the dielectric layers  212  and  214 . After fabricating the bond pads  234 , the dielectric layers  212  and  214  and the devices  208  were not damaged.  
         [0038]    The present invention reduces the IC die size by allowing the bond pads to be located over the dielectric layers, the active devices and/or the passive devices. Due to the use of compliant material in the bulk layers according to the present invention, there are no restrictions on underlying interconnect metal routing. The present invention absorbs the thermal and/or mechanical stress that occurs during wire bonding and prevents damage to underlying dielectric layers, the active devices and/or the passive devices. The present invention also provides improved stress absorption capabilities that are particularly useful for submicron technologies that employ low-k dielectrics (which include CVD or spun-on materials).  
         [0039]    Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.