Abstract:
A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2 N  capacitors and 2 N +1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2 N  discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Description:
FIELD OF THE INVENTION 
     This invention relates in general to digital-to-analog signal conversion and, in particular, to a high-accuracy capacitor digital-to-analog converter. 
     BACKGROUND OF THE INVENTION 
     Digital-to-analog (DA) conversion is a technique for converting information expressed in digital format into analog signals. Digital-to-analog converters (DAC) is indispensable for digital electronic equipment that need to process information obtained in the form of analog signals. As is known, voice, audio and video signals, information closely related to our daily life, are inherently analog in form. Contemporary technologies have, however, employed digital form for the processing and storage of these most-used information. For example, a music Compact Disc (CD) player retrieves sound information stored on a CD in digital format for playback. Before this high-fidelity music can be played back, however, its retrieved digital representation must be converted into analog electrical signal that can be used to drive a loudspeaker system. Good digital-to-analog conversion is crucial to high-fidelity music playback. 
     In another example, an LCD (liquid crystal display) panel of a computer system also requires similar digital-to-analog conversion. Much like a pair of loudspeakers is to the ears of a music lover, the LCD panel is the instrument for presenting visual information to the operator/user of the computer. Information in the form of either text, graphics or video to be displayed on the LCD panel is stored and processed in the computer system in digital. To drive the transistors in a matrix that correspond to the screen pixels of a TFT LCD, the digital display information must be converted into analog. 
     Two categories of DAC, the resistor and capacitor DAC&#39;s, are frequently used for such DA conversion. Resistor DAC (hereafter referred to as RDAC) are relatively simpler to make but consume static power. Electric power is consumed across the resistor of the RDAC even as the converter is in static status. By contrast, capacitor DAC (CDAC) are inherently more complex to fabricate, and their operation require more precise timing control, but they consume virtually no static power, which is an important characteristics of advantage in portable electronic devices. 
     There are in general three causes of wrong voltage levels in a CDAC that lead to conversion inaccuracy. The first is the voltage difference between CDAC capacitor and gate input of the output buffer. The second is caused by charge injection for CDAC control signal. The third cause is charge injection from output buffer node voltage transition. In general, the conversion accuracy of a CDAC is greatly affected by the charge sharing and the charge injection phenomena inherent to CDAC. 
     To overcome these problems and increase CDAC conversion accuracy, a straight-forward solution is the use of large capacitors in CDAC in order to secure large capacitance. Unfortunately, large capacitors increase die sizes for these CDAC. As the conversion voltage increases, this problem becomes even more significant. This prevents the successful application of CDAC in applications such as TFT LCD because conversion voltage required in TFT driver circuitry is typically high. 
     For the purpose of the description of the invention, it suffices to examine the circuit configuration of the conventional CDAC devices and the principle problems they encounter.  FIG. 1  is a schematic diagram of a conventional N-bit CDAC with an output buffer. The illustration of  FIG. 1  also outlines the charge sharing problem these conventional CDAC have. 
     As is seen in the drawing, an N-bit CDAC converter  100  is essentially consisted of a converter capacitor network  110  and an output buffer  120 . Output of the capacitor network  110 , as extracted at node  112 , is connected to input of the buffer  120 . The capacitor network  110  requires a total of 2 N  capacitors C 1 , C 2 , . . . , C 2     N    and 2 N +1 MOS switches, including the low and high input switches S L  and S H , as well as the 2 N −1 network switches S 1 , S 2 , . . . , S 2     N     −1 . All the 2 N +1 MOS switches are connected in a series chain at their respective source/drain, with the two, S L  and S H  respectively for the low and high input voltages V L  and V H , at each of the far ends of the chain controlling the input to the converter capacitor network  110 . 
     Each of the 2 N  capacitors has its one electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain. For example, capacitor C 2  has an electrode connected to the node where switches S 1  and S 2  are connected together at their respective source/drain terminals. The other electrode of all the capacitors are tied together to a common node—the common ground node in the example of the system. All the 2 N  capacitors need to be constructed within a specified tolerance to the same capacitance. 
     For the N-bit CDAC  100  of  FIG. 1  to achieve high-precision digital-to-analog conversion, at least two problems, charge injection and charge sharing, must be handled properly.  FIG. 1  itself schematically outlines the charge sharing problem in the N-bit CDAC. The output buffer  120  coupled to the N-bit capacitor network  110  introduces an inevitable input capacitance, as is schematically represented by the equivalent capacitor  125 , to the system such that the analog voltage as converted by the converter capacitor network  110  becomes essentially drifted away at the output node  128  of the buffer  120 . In order to reduce this drift, larger capacitors must be used. However, larger capacitors lead directly to increased device surface area. 
     On the other hand,  FIG. 2  is a schematic diagram of the capacitor network of a conventional N-bit CDAC outlining the problem of charge injection. Charge injection into the capacitors C 1 , C 2 , . . . , C 2     N    of the converter capacitor network  210  is caused by junction coupling across the gate-source and/or gate-drain terminals while any of the MOS devices S L , S 1 , S 2 , . . . , S 2     N     −1 , S H  are switching. This charge injection phenomenon is schematically illustrated in the drawing by the capacitance C GS  and C GD  of the equivalent gate-source and gate-drain capacitors C GL , C G21 , C G22  and C GH  connected across the gate and either source or drain of a MOS switch device. This charge injection is sometimes considered a clock feedthrough, a phenomenon in which the gate control signal applied to a MOS switch of a converter capacitor network is coupled across its equivalent gate-source or gate-drain capacitance into the network capacitor. 
     Traditionally, two approaches have been employed to tackle this charge injection problem. The first utilizes a companion switch for each of the converter MOS switches that has half the size of its master device. The companion switch is controlled to operate against its master so as to cancel the charge injection introduced by the activation of the master utilizing its own inherent injection. However, the only function of the additional companion switch is the provision of a cancellation injection of charge for its master and nothing else. Overall circuitry complexity and device size are substantially increased as a result of this additional device. 
     A second approach employs the concept of a transmission gate for each of the MOS switch devices of the converter. A device of the reverse polarity as that of the switch whose charge injection was to be cancelled is connected in parallel. When both devices functions, the reversed injections cancels each other. However, this approach not only requires an additional MOS devices for each switch in the converter, there were also introduced additional problems of mismatched C GS /C GD  capacitance for the pair. 
     Thus, as the charge injection and sharing problems are not effectively resolved in the prior-art CDAC, it is therefore an object of the invention to provide a CDAC that resolves these problems simultaneously. 
     It is another object of the invention to provide a CDAC that is free from the charge injection and sharing problems while is simple to construct. 
     It is still another object of the invention to provide a CDAC that is free from the charge injection and sharing problems while is low in cost to construct. 
     SUMMARY OF THE INVENTION 
     The invention achieves the above-identified objects by providing a capacitor digital-to-analog converter for N-bit digital-to-analog conversion that comprises a converter capacitor network comprising 2 N  capacitors and 2 N +1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2 N  discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a conventional N-bit CDAC with an output buffer outlining the problem of charge sharing; 
         FIG. 2  is a schematic diagram of a conventional N-bit CDAC outlining the problem of charge injection; 
         FIG. 3  is a schematic diagram illustrating an N-bit CDAC of the invention employing a discrete-input buffer for the converter capacitor network; 
         FIG. 4  is a schematic diagram illustrating the basic circuit configuration for a multiple discrete-input buffer for the CDAC of  FIG. 3 ; 
         FIG. 5  is a schematic diagram illustrating the detailed circuitry of a high-accuracy CDAC in accordance with a preferred embodiment of the invention; and 
         FIG. 6  is a schematic diagram illustrating the detailed circuitry of a high-accuracy CDAC in accordance with another preferred embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The high-accuracy CDAC of the invention as described in the following paragraphs in preferred embodiments is capable of providing high-accuracy DA conversion by simultaneously resolving the charge injection and charge sharing problems in the conventional CDAC. First, to avoid the charge sharing problem, a CDAC of the invention employs a buffer circuit for its converter capacitor network with a discrete input for each and every capacitors in the network.  FIG. 3  is a schematic diagram illustrating an N-bit CDAC  300  of the invention employing such a discrete-input buffer  320  for its converter capacitor network  310 . 
     In the CDAC  300  of  FIG. 3 , each of all the switched electrodes of the 2 N  capacitors C 1 , C 2 , . . . , C 2     N    in the network  310  is connected discretely to an independent input of the buffer  320 .  FIG. 4  is a schematic diagram illustrating the basic circuit configuration for such a multiple-input buffer. Although only one input at the MOS device N 2  is shown in this depicted basic configuration, however, as will be described in detail in the following paragraphs, the device N 2 , whose gate terminal labeled as V IN , can be expanded into multiple MOS devices for receiving the input signal from the converter capacitor network for input. 
     As is seen in the drawing, the buffer  420  is comprised of two stages of amplifiers  421  and  422 . The first stage  421  is a differential amplifier consisting of a current mirror  423  and a differential pair  424  of MOS switch devices. The MOS switch devices of the current mirror  423  and that of the differential pair  424  are of the reversed polarities. For example, in the basic buffer of  FIG. 4 , the current mirror  423  are made up of PMOS devices and the differential pair  424  of NMOS devices. 
     On the other hand, the second stage  422  is an amplifier consisting of a MOS switch device P 3  and a current source CS. The output of the first-stage differential amplifier  421  is used to control the second-stage amplifier  422 . 
     In the first-stage differential amplifier  421 , the current mirror  423  has a first, P 1 , and a second, P 2 , two PMOS devices and the differential pair  424  has a first, N 1 , and a second, N 2 , two NMOS devices. Source terminals of the two PMOS devices P 1  and P 2  of the current mirror  423  are connected together and to the power source of the system. The gate terminals of PMOS devices P 1  and P 2  are tied together and also to the drain of the first PMOS P 1 . On the other hand, source terminals of the two NMOS devices N 1  and N 2  of the differential pair  424  are connected together and then to ground via another NMOS device N b . Gate terminal of the second NMOS device N 2  serves as the input to the buffer  420 , and that of the first NMOS N 1  receives feedback from the output of the buffer  420  itself from the second stage. 
     The current mirror  423  and the differential pair  424  are connected to each other at the drain terminals. The drain of the first PMOS device P 1  of the current mirror  423  is connected to the drain of the first NMOS device N 1  of the differential pair  424  and, likewise, the drain of the second PMOS P 2  of the current mirror  423  is connected to the drain of the second NMOS N 2  of the differential pair  424 . 
     Although the buffer basic circuit configuration as outlined in  FIG. 4  can be expanded to suit the need of multiple input for the capacitor network in the CDAC in a configuration as outlined in  FIG. 3  aiming at resolving the charge sharing problem as described in  FIG. 1 , however, it has an inherent nature of introducing a charge injection problem of its own. This charge injection phenomenon is in addition to what was described in  FIG. 2  above. While the charge injection problem described in  FIG. 2  is caused by the operation of the MOS switch devices of the converter capacitor network itself, the additional charge injection is caused by the MOS device of the buffer. 
     Specifically, the gate terminal of the second NMOS N 2  in the first-stage differential amplifier  421  of the buffer  420  of  FIG. 4  which serves as the input for the capacitor network of the CDAC injects charges into the capacitor to which it is connected as it is switched. Two injections are possible. One is from the source terminal of N 2  as a result of the gate-source capacitance C GS , and the other is from the drain of N 2  due to gate-drain capacitance C GD . Typical voltage deviation induced in the connected capacitor of the converter is in the range of about 1-5 mV, an amount significant enough that must be dealt with if the construction of a high-accuracy CDAC is intended. 
     Though, in accordance with the present invention, with a modification to the basic configuration of  FIG. 4 , however, it is possible to cancel this additional charge injection problem, as will be described in detail below. Refer to  FIG. 5 , a schematic diagram illustrating the detailed circuitry of a high-accuracy CDAC in accordance with a preferred embodiment of the invention. The CDAC  500  of  FIG. 5  incorporates an output buffer  520  based on the configuration  420  of  FIG. 4  for a capacitor network  510  capable of N-bit DA conversion. Note that the buffer  520  has 2 N  input MOS devices for N-bit DA conversion as compared to the single one of the basic buffer  420  of FIG.  4 . Also, three additional MOS devices PD 1 , PD 2  and PD 3  are added to the basic buffer that are used to cancel the buffer-induced injection charges into the converter network capacitors as mentioned above. 
     As is illustrated in  FIG. 5 , in the first-stage differential amplifier  521 , the current mirror  523  has a first, P 1 , and a second, P 2 , two PMOS devices. On the other hand, the differential pair  524  has a first, N 1 , at one differential branch, and a total of 2 N  NMOS devices N 2 , . . . , N 2     N   , N 2     N     +1  at the other branch. Note that the second NMOS device N 2  of the basic buffer configuration  420  of  FIG. 4  is now substantially expanded into 2 N  NMOS device N 2 , . . . , N 2     N   , N 2     N     +1  for accommodating the 2 N  capacitors in the converter capacitor network  510  as discrete inputs to the buffer  520 . Hereafter, these expanded NMOS devices will be referred to as input NMOS devices of the buffer  520 . This effectively allows each of the capacitors C 1 , . . . , C 2     N    in the network  510  of the converter  500  to “see” the same gate capacitance at its corresponding input MOS device among N 2 , . . . , N 2     N   , N 2     N     +1  . As a result, the capacitance variation for each of them can thus be avoided. Also note that in order to maintain a balanced differential pair, the effective total physical device dimension of the 2 N  NMOS device N 2 , . . . , N 2     N   , N 2     N     +1  countering the first NMOS device N 1  should be fabricated to be substantially the same as that of N 1 . 
     Source terminals of the two PMOS devices P 1  and P 2  of the current mirror  523  are connected together and to the power source V DD . Gate terminal of the second PMOS P 2  is connected to its own drain across a PMOS device P D1 . Gate terminals of PMOS devices P 1  and P 2  are tied together via a PMOS device PD 2 . Gate terminal of the first PMOS device P 1  is connected to its own drain. Then, similar as was in the basic buffer of  FIG. 4 , source terminals of all the NMOS devices N 1 , N 2 , . . . , N 2     N   , N 2     N     +1  of the differential pair  524  are connected together and then to ground via another NMOS device N b . 
     Gate terminal of each of these 2 N  input NMOS devices N 2 , . . . , N 2     N   , N 2     N     +1  serves as a discrete input to the buffer  520 , and that of the first NMOS N 1  receives feedback from the output of the buffer  520  itself from the second stage. The current mirror  523  and the differential pair  524  are connected at the drain terminals. The drain of the first PMOS device P 1  of the current mirror  523  is connected to the drain of the first NMOS device N 1  of the differential pair  524  and, likewise, the drain of the as second PMOS P 2  of the current mirror  523  is connected to the drain of all the 2 N  input NMOS devices N 2 , . . . , N 2     N   , N 2     N     +1  of the differential pair  524 . 
     In comparison to the basic buffer circuit configuration of  FIG. 4 , another additional PMOS device PD 3  connects the gate terminal of the first NMOS device N 1  of the buffer  520  to the system ground, as is illustrated in FIG.  5 . 
     In operation, in order to reduce the influence of the problematic charge injection phenomenon internal to the MOS switch devices S 1 , S 2 , . . . , S 2     N     −1  in the capacitor network  510 , only one among the 2 N −1—excluding the end—switches will be turned on at any given time when the converter  500  is operating. 
     During the charging phase of the CDAC  500 , MOS switch device PD 1  is turned on and PD 2  off. This effectively shorts the gate-drain terminals of the device P 2  while simultaneously cutting the gate of P 2  off from that of the first PMOS device P 1  such that output of the buffer  520  at node MIDB may be maintained and locked to the voltage of V DD −V GS , where V DD  is the power voltage supplied to the buffer  520 , and V GS  is the voltage drop across the PMOS device P 2  of the current mirror  523 . After the conclusion of the charging phase of the CDAC  500 , device P 1  is turned off while P 2  turned on, and the current mirror  523  of buffer  520  returns to the status of a single-output differential pair, in order to be coupled to and drive the second-stage amplifier  522 . This allows the voltage at the node MIDB under this coupled condition to be converged and settled substantially to the value of V DD −V GS . 
     Also during the charging phase of the CDAC  500 , gate voltage of the first NMOS device N 1  of the differential pair  524  is essentially pulled down to the ground voltage by the PMOS device PD 3  as it is turned off. This effectively allows the input NMOS devices N 2 , . . . , N 2     N   , N 2     N     +1  at the input branch of the differential pair (countering N 1  at the opposing branch) to dominate the voltage V S  of node S, the node where the MOS devices of the differential pair  524  are joined together at their respective drains. In other words, voltage V S  is effectively determined by the minimum voltage, V IN     N   , of all the input voltages at their respective gate terminal of the MOS switch devices N 2 , . . . , N 2     N   , N 2     N     +1  . When the system is settled after feedback, the voltage V IN     N    essentially determines the voltage V S  at node S. 
       FIG. 6  is a schematic diagram illustrating the detailed circuitry of a high-accuracy CDAC in accordance with another preferred embodiment of the invention. The embodiment of  FIG. 6  is similar to that of  FIG. 5  except that the polarity of all the MOS switch devices employed for the construction of the converter is reversed. 
     Thus, as mentioned above, there are in general three causes of wrong voltage levels in a CDAC. The first is the voltage difference between CDAC capacitor and gate input of the output buffer. In accordance with the present invention, the solution to this problem is the use of a multiple-input output buffer. The second is caused by charge injection for CDAC control signal. The solution of the present invention to this problem is cancellation. The third cause is charge injection from output buffer node voltage transition. As is taught by the present invention, additional switch devices P D1 , PD 2  and PD 3  introduced to a basic output buffer circuitry minimize the transition and thus alleviate the injection problem. These measures in combination allow the present invention to provide a CDAC that is small in device size and accurate in conversion accuracy by simultaneous elimination of the charge injection and sharing problems that would otherwise arise. 
     While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.