Abstract:
An oscillator circuit may include a latch circuit, a feed-back circuit, and an input circuit. The latch circuit may be configured to generate an oscillating output signal responsive to first and second input signals, and the feed-back circuit may be configured to generate first and second complementary feed-back signals responsive to the oscillating output signal from the latch circuit. The input circuit may be configured to generate the first and second input signals responsive to the first and second complementary feed-back signals. Related methods are also discussed.

Description:
This application claims the benefit of and priority under 35 U.S.C. Sec. 119 to Korean Patent Application No. 2004-76031, filed on Sep. 22, 2004, the disclosure of which is incorporated herein by reference in its entirety. 
   FIELD OF THE INVENTION 
   The present invention relates to electronic circuits and, more particularly, to oscillation circuits and related methods. 
   BACKGROUND OF THE INVENTION 
   In general, some semiconductor devices such flash memories may use relatively high voltages to perform erase and/or program operations. Accordingly, high voltage generators may be included in the semiconductor devices to generate high voltages. A high voltage generator may include a plurality of charge pumps which are connected in series. Each of the charge pumps may generate a high voltage using a pumping operation in response to a predetermined oscillation signal. At this time, the oscillation signal may be generated by an internal oscillation circuit included in the semiconductor device.  FIG. 1  shows an oscillation circuit used in a conventional semiconductor device. With reference to  FIG. 1 , the conventional oscillation circuit  100  includes a detection unit  110 , a comparator  120 , and a latch unit  130 . 
   The detection unit  110  includes a first detector  112  and a second detector  114 , which have a same circuit construction. In addition, the detection unit  110  receives first and second feedback signals VF 1 A and VF 2 A and the detection unit  110  generates first and second detection signals VD 1 A and VD 2 A. The first and second feedback signals VF 1 A and VF 2 A are fed-back from a latch unit  130 . The first and second detection signals VD 1 A and VD 2 A are charged responsive to a voltage level of the first and second feedback signals VF 1 A and VF 2 A. Each of detectors  112  and  114  includes a P-MOS transistor (P 1 A or P 2 A), two N-MOS transistors (N 1 A and N 2 A, or N 3 A and N 4 A), and a capacitor (C 1 A or C 2 A). The P-MOS transistor (P 1 A or P 2 A) is connected in a series between a power voltage VDD and a ground voltage VSS. The P-MOS transistor (P 1 A or P 2 A) and one N-MOS transistor (N 1 A or N 3 A) are turned on and off responsive to a feedback signal (VF 1 A or VF 2 A). Another N-MOS transistor (N 2 A or N 4 A) is turned on and off responsive to a reference voltage V refa  having a constant voltage level. 
   The comparator unit  120  includes two comparators  122  and  124 , which are embodied using respective differential amplifiers. Each of comparators  122  and  124  compares the reference voltage V refa  with a respective detection signal VD 1 A and VD 2 A provided by the detection unit  110  to generate comparison signals VC 1 A and VC 2 A. 
   As shown in  FIG. 1 , the latch unit  130  may be an SR (set-reset) latch including two NAND gates  132  and  134 . Outputs of the SR latch may be first and second feedback signals VF 1 A and VF 2 A which are fed-back to the detection unit  110 . In addition, the second feedback signal VF 2 A may be used as the output of oscillation circuit  100  (an oscillation signal OSCA). As is well known to those skilled in the art, outputs of the NAND gates of the SR latch may be complementary with respect to each other. If two inputs of each NAND gate are “0”, two outputs of the SR latch may be fixed to “1”. 
     FIG. 2  is a waveform illustrating an oscillation signal according to variations of external power in a conventional oscillation circuit. In the conventional oscillation circuit, a power source voltage may dip to a range in which the differential amplifier may be inoperative (A), and a voltage level (an output of each differential amplifier) of first and second comparison signals VC 1 A and VC 2 A may have a level of a ground voltage VSS. Accordingly, two outputs of the latch unit  130  embodied by the SR latch may become “0” so that a power voltage VDD of first and second feedback signals VF 1 A and VF 2 A (outputs of the latch unit  130 ) may be fixed to a level of the power voltage VDD. Thus, even if a power of a normal range is provided after power-dipping of the external power source, an output of the oscillation circuit  100  may still be fixed to a level of the power voltage VDD. As a result, oscillation operation may not restart. 
   Oscillation circuits are disclosed, for example, in Korean Laid-Open Patent Publication No. 2000-0027506 entitled “AN OSCILATOR FOR GENERATING HIGH VOLTAGE OF FALSH MEMORY DEVICE”, the disclosure of which is hereby incorporated herein in its entirety by reference. 
   SUMMARY OF THE INVENTION 
   An oscillator circuit may include a latch circuit, a feed-back circuit, and an input circuit. The latch circuit may be configured to generate an oscillating output signal responsive to first and second input signals, and the feed-back circuit may be configured to generate first and second complementary feed-back signals responsive to the oscillating output signal from the latch circuit. The input circuit may be configured to generate the first and second input signals responsive to the first and second complementary feed-back signals. 
   More particularly, the input circuit may include a detection circuit and a comparator circuit. The detection circuit may be configured to generate first and second detection signals responsive to the first and second feed-back signals. The comparator circuit may be configured to compare the first and second detection signals with a reference voltage and to generate the first and second input signals responsive to comparing the first and second detection signals with the reference voltage. The detection circuit may include a first detector configured to generate the first detection signal responsive to the first feed-back signal and a second detector configured to generate the second detection signal responsive to the second feed-back signal. 
   Moreover, the first detector may include a PMOS transistor coupled between a power supply voltage and a node with the first feed-back signal being provided at a gate of the PMOS transistor. In addition, an NMOS transistor may be coupled in series between the node and a ground voltage, with the first feed-back signal being provided at a gate of the NMOS transistor, and with the first detection signal being generated at the node between the PMOS and NMOS transistors. The first detector may further include a second NMOS transistor and a capacitor. The second NMOS transistor may be coupled in series with the first NMOS transistor between the node and the ground voltage with the reference voltage being provided at a gate of the second NMOS transistor. The capacitor may be coupled between the node and the ground voltage in parallel with the first and second NMOS transistors. 
   Similarly, the second detector may include a PMOS transistor coupled between a power supply voltage and a node, with the second feed-back signal being provided at a gate of the PMOS transistor. In addition, an NMOS transistor may be coupled in series between the node and a ground voltage, with the second feed-back signal being provided at a gate of the NMOS transistor, and with the second detection signal being generated at the node between the PMOS and NMOS transistors. The second detector may further include a second NMOS transistor and a capacitor. The second NMOS transistor may be coupled in series with the first NMOS transistor between the node and the ground voltage with the reference voltage being provided at a gate of the second NMOS transistor. The capacitor may be coupled between the node and the ground voltage in parallel with the first and second NMOS transistors. 
   The comparator circuit may include first and second comparators. The first comparator may be configured to generate the first input signal responsive to comparing the first detection signal with the reference voltage, and the second comparator may be configured to generate the second input signal responsive to comparing the second detection signal with the reference voltage. More particularly, the first comparator may be a first differential amplifier, and the second comparator may be a second differential amplifier. 
   The latch circuit may be a set-reset latch circuit including first and second cross-coupled logic gates, with the oscillating output signal being generated at an output of the first of the cross-coupled logic gates. The feed-back circuit may include a delay circuit configured to delay the oscillating output signal, a first inverter configured to invert the delayed oscillating output signal thereby generating the first feed-back signal, and a second inverter configured to invert the first feed-back signal thereby generating an oscillator output. Moreover, the delay circuit may include a plurality of inverters coupled in series. 
   According to additional embodiments of the present invention, methods may be provided for generating oscillating signals. An oscillating output signal may be generated responsive to first and second input signals, and first and second complementary feed-back signals may be generated responsive to the oscillating output signal. First and second input signals may be generated responsive to the first and second complementary feed-back signals. 
   More particularly, generating the first and second input signals may include generating first and second detection signals responsive to the first and second feed-back signals. The first and second detection signals may be compared with a reference voltage, and the first and second input signals may be generated responsive to comparing the first and second detection signals with the reference voltage. Moreover, generating the first and second detection signals may include generating the first detection signal responsive to the first feed-back signal and generating the second detection signal responsive to the second feed-back signal. In addition, generating the first and second complementary feed-back signals may include delaying the oscillating output signal, inverting the delayed oscillating output signal to thereby generate the first feed-back signal, and inverting the first feed-back signal to thereby generate an oscillator output. 
   Oscillation circuits according to embodiments of the present invention may be capable of restarting a normal oscillation operation when an external power supply is returned to a normal level after stopping an oscillation operation of an oscillation circuit due to a power dipping of the external power supply in a semiconductor memory device. 
   According to some embodiments of the present invention, an oscillation circuit may include a detection unit for receiving first and second feedback signals having an inverse phase with respect to each other and a reference voltage having a constant voltage to generate first and second detection signals whose voltage levels change respectively according to the first and second feedback signals. A comparator unit may compare the reference voltage with the voltage level of the first detection signal to generate a first comparison signal, and the comparator unit may compare the reference signal with the voltage level of the second detection signal to generate a second comparison signal. A latch unit may receive the first and second comparison signals to generate an oscillation signal and a restart unit may generate the first and second feedback signals using the oscillation signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram illustrating an oscillation circuit used in a conventional memory device. 
       FIG. 2  is a waveform illustrating an oscillation signal as a function of variations of external power in the conventional oscillation circuit of  FIG. 1 . 
       FIG. 3  is a schematic diagram illustrating oscillation circuits according to some embodiments of the present invention. 
       FIG. 4  is a waveform illustrating an oscillation signal as a function of variations of external power in the oscillation circuit of  FIG. 3 . 
   

   DETAILED DESCRIPTION 
   The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. 
   It will be understood that, although the terms first, second, etc. may be used herein to describe various embodiments, elements, components, regions, layers and/or sections, these embodiments, elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one embodiment, element, component, region, layer or section from another embodiment, element, component region, layer or section. Thus, a first embodiment, component, element, region, layer or section discussed below could be termed a second embodiment, component, element, region, layer or section, and, similarly, a second embodiment, component, element, region, layer or section could be termed a first embodiment, component, element, region, layer or section without departing from the teachings of the present invention. The term “directly” means that there are no intervening elements. Finally, as used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
   The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
   Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     FIG. 3  illustrates an oscillation circuit according to some embodiments of the present invention. With reference to  FIG. 3 , the oscillation circuit includes a detection unit  310 , a comparator unit  320 , a latch unit  330 , and a restart unit  340 . 
   As shown in  FIG. 3 , the detection unit  310  includes first and second detectors  312  and  314 , which may have a same circuit construction. In addition, the detection unit  310  receives a reference voltage V ref  and first and second feedback signals VF 1  and VF 2  used to generate first and second detection signals VD 1  and VD 2 . The first and second feedback signals VF 1  and VF 2  are fed-back from the latch unit  330 , and the first and second detection signals VD 1  and VD 2  change responsive to changes in voltage levels of the first and second feedback signals VF 1  and VF 2 . The first detector  312  includes a first P-MOS transistor P 1 , first and second N-MOS transistors N 1  and N 2 , and a capacitor C 1 . The first P-MOS transistor P 1  is connected between a power voltage VDD and a first node ND 1 . The first and second N-MOS transistors N 1  and N 2  are connected in series between the first node ND 1  and a ground voltage VSS. A capacitor C 1  is connected between the first node ND 1  and the ground voltage VSS. The P-MOS transistor P 1  and the N-MOS transistor N 1  of the first detector  312  are turned on and off responsive to the first feedback signal VF 1  from the restart unit  340 , which is applied to gate terminals of the P-MOS transistor P 1  and the N-MOS transistor N 1 . The second N-MOS transistor N 2  is turned on and off responsive to on a reference voltage V ref . 
   In the first detector  312  having such a circuit construction, if the first feedback signal VF 1  is high, the first P-MOS transistor P 1  is turned off, and the first N-MOS transistor is turned on. As a result, charge from the capacitor C 1  is discharged. Therefore, if the first feedback signal VF 1  is high, the first detector  312  generates the first detection signal VD 1  having a ground voltage VSS level. If the first feedback signal VF 1  is low, the first P-MOS transistor P 1  is turned on, and the first N-MOS transistor N 1  is turned off. As a result, the capacitor C 1  is charged from the power voltage VDD through the P-MOS transistor P 1 . Accordingly, if the first feedback signal VF 1  is low, the first detector  312  generates the first detection signal VD 1  having a power voltage VDD level. 
   As shown in  FIG. 3 , the second detector  314  is controlled by a voltage level of the second feedback signal VF 2  instead of the first feedback signal VF 1 . Excepting this difference, the second detector  314  has the same circuit construction as the first detector  312 . If a voltage level of the second feedback signal VF 2  is high, the second detector  314  may generate a second detection signal VD 2  having a ground voltage VSS level. If the voltage level of the second feedback signal VF 2  is low, the second detector  314  may generate a second detection signal VD 2  having a power voltage VDD level. 
   The comparator unit  320  may include first and second comparators  322  and  324 , which are embodied as differential amplifiers. The first comparator  322  compares the reference voltage V ref  with a first detection signal VD 1  from the first detector  312  and generates a first comparison signal VC 1  responsive to the comparison. The second comparator  324  compares the reference voltage V ref  with the second detection signal VD 2  and generates a second comparison signal VC 2  responsive to the comparison. That is, if the first detection signal VD 1  is at the power voltage VDD level, the first comparator  322  receives the reference voltage V ref  and the first detection signal VD 1  and generates a first comparison signal VC 1  having a power voltage VDD level. If the first detection signal VD 1  is at the ground voltage VSS level, the first comparator  322  generates the first comparison signal VC 1  having the ground voltage VCC level. In the same way, the second comparator  324  receives the reference voltage V ref  and the second detection signal VD 2  and generates the second comparison signal VC 2  responsive to a voltage level of the second detection signal VD 2 . The reference voltage V ref  may have a relatively constant voltage level between the VDD and VSS voltage levels. 
   The latch unit  330  may be embodied as an SR (set-reset) latch with two NAND gates  332  and  334 . The latch unit  330  receives the first and second comparison signals VC 1  and VC 2  from the comparator  320  at the respective NAND gates  332  and  334 . An output of each NAND gate is applied to an input of the other NAND gate. In addition, the latch unit  330  generates a first oscillation signal OSC 1  from one of the two NAND gates  332  and  334 . 
   The restart unit  340  generates first and second feedback signals VF 1  and VF 2  having inverse phase with respect to each other using the first oscillation signal OSC 1  from the latch unit  330 , and the feed-back signals VF 1  and VF 2  are fed-back to the detection unit  310 . After that, the restart unit  340  generates an oscillation signal OSC which may be the inverse of the first feedback signal VF 1 . More particularly, the restart unit  340  may include first and second inverters  342  and  344 , a third inverter  346 , and a fourth inverter  348 . The first and second inverters  342  and  344  may be connected in series and may generate the second feedback signal VF 2  by delaying the first oscillation signal OSC from the latch unit  330 . The third inverter  346  may generate the first feedback signal VF 1  by inverting the second feedback signal VF 2 . The fourth inverter  348  may generate the oscillation signal OSC by inverting the output of the third inverter  346  (the first feedback signal VF 1 ). Through these processes, the restart unit  340  generates the first and second feedback signals VF 1  and VF 2 , which will have an inverse phase as a result of inverter  346 , and the feed-back signals VF 1  and VF 2  are fed-back to the detection unit  310 . 
     FIG. 4  is a waveform illustrating an oscillation signal as a function of variations of an external power supply in oscillation circuits according to embodiments some of the present invention. As shown in  FIG. 4 , the restart unit  340  may reduce mis-operations of the oscillation circuit  300 . In this case, a mis-operation may occur in a low power condition by stopping oscillation when an external power POWER dips such that the differential amplifiers do not operate properly. If the external power POWER returns to a normal level, the oscillation circuit  300  may restart oscillation operations automatically as a result of the restart unit  340 . In particular, the first and second feedback signals VF 1  and VF 2  that are fed-back by the restart unit  340  will have an inverse phase as a result of inverter  346 . That is, detection signals VD 1  and VD 2  having different voltage levels may be generated using the complementary feedback signals VF 1  and VF 2 , thereby providing different (i.e. complementary) comparison signals VC 1  and VC 2 , which are provided to the latch unit  30 . As a result, the oscillation circuit  300  may restart oscillation operations automatically. 
   As previously mentioned, oscillation circuits according to some embodiments of the present invention may stop oscillation in a low power condition due to a power dip in such a manner that mis-operations of the oscillation circuit may be reduced. In addition, the oscillation circuit may be capable of restarting an oscillation operation automatically if an external power is returned to a normal operation voltage. 
   Oscillation circuits according to some embodiments of the present invention can thus be used to drive one or more charge pumps for high voltage generation. More particularly, oscillation circuits according to further embodiments of the present invention can be used to drive one or more charge pumps for high voltage generation in memory devices such as flash memory devices. 
   While the present invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.