Abstract:
A method of using a memory chip includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal contains information regarding an operational frequency of a system clock signal of the memory system. The method provides the advantage of enabling high operation frequencies and thus increasing the SDRAM internal timing margin.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of memory chips. 
     2. Discussion of Related Art 
     A known integrated memory IC  100  that is a writeable memory of the DRAM type is shown in FIG.  1 . Such a dynamic random access memory (DRAM) chip  100  includes a plurality of memory storage cells  102  in which each cell  102  has a transistor  104  and an intrinsic capacitor  106  (as shown in FIG.  4 ). As shown in FIGS. 2 and 3, the memory storage cells  102  are arranged in arrays  108 , wherein memory storage cells  102  in each array  108  are interconnected to one another via columns of conductors  110  and rows of conductors  112 . The transistors  104  are used to charge and discharge the capacitors  106  to certain voltage levels. The capacitors  106  then store the voltages as binary bits,  1  or  0 , representative of the voltage levels. The binary  1  is referred to as a “high” and the binary  0  is referred to as a “low.” The voltage value of the information stored in the capacitor  106  of a memory storage cell  102  is called the logic state of the memory storage cell  102 . 
     As shown in FIGS. 1 and 2, the memory chip  100  includes six address input contact pins A 0 , A 1 , A 2 , A 3 , A 4 , A 5  along its edges that are used for both the row and column addresses of the memory storage cells  102 . The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A 0  to A 5  into the row address latches  114 . Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A 0  to A 5  into the column address latches  116 . The memory chip  100  has data pin Din that receives data and data pin Dout that sends data out of the memory chip  100 . The modes of operation of the memory chip  100 , such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention. 
     A variation of a DRAM chip is shown in FIGS. 5 and 6. In particular, by adding a synchronous interface between the basic core DRAM operation/circuitry of a second generation DRAM and the control coming from off-chip a synchronous dynamic random access memory (SDRAM) chip  200  is formed. The SDRAM chip  200  includes a bank of memory arrays  208  wherein each array  208  includes memory storage cells  210  interconnected to one another via columns and rows of conductors. 
     As shown in FIGS. 5 and 6, the memory chip  200  includes twelve address input contact pins A 0 -A 11  that are used for both the row and column addresses of the memory storage cells of the bank of memory arrays  208 . The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A 0  to A 11  into the bank of row address latches  214 . Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A 0  to A 11  into the bank of column address latches  216 . The memory chip  200  has data input/output pins DQ 0 - 15  that receive and send input signals and output signals. The input signals are relayed from the pins DQ 0 - 15  to a data input register  218  and then to a DQM processing component  220  that includes DQM mask logic and write drivers for storing the input data in the bank of memory arrays  208 . The output signals are received from a data output register  222  that received the signals from the DQM processing component  220  that includes read data latches for reading the output data out of the bank of memory arrays  208 . The modes of operation of the memory chip  200 , such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention. 
     A variation of the SDRAM chip  200  is a double-data-rate SDRAM (DDR SDRAM) chip. The DDR SDRAM chip imparts register commands and operations on the rising edge of the clock signal while allowing data to be transferred on both the rising and falling edges of the clock signal. Differential input clock signals CLK and CLK(bar) are used in the DDR SDRAM. A major benefit of using a DDR SDRAM is that the data transfer rate can be twice the clock frequency because data can be transferred on both the rising and falling edges of the CLK clock input signal. 
     It is noted that new generations of memory systems that employ SDRAM and DDR SDRAM chips are increasing their frequency range. Currently, SDRAM and DDR SDRAM chips are unable to determine the frequency at which they are operating in a particular memory system. As the frequency range of the memory system widens, it can pose some problems for the SDRAM and DDR SDRAM chips. For example, a DDR SDRAM chip has to time operations between different clocking domains. It is known that the clocking domains change their relative timing to one another as a function of the operating frequency of the memory system. This change in relative timing is illustrated in FIGS. 7 and 8. 
     In the case of a slow operating frequency, such as 66 MHz, the system clock signal VCLK is directed to the clock pin of the DDR SDRAM. The system clock signal VCLK generates within the DDR SDRAM an internal clock signal ICLK that clocks the central command unit of the DDR SDRAM. This means that all internal commands generated by the central command unit are synchronized with the internal clock signal ICLK. As shown in FIG. 7, while the internal clock signal ICLK has the same frequency as the system clock signal VCLK, it lags the system clock signal VCLK by a constant amount tMAR 2 . The lag is caused by several gate and propagation delays. This lag results in a phase shift between the ICLK signal and the VCLK signal that becomes bigger as the frequency of the clock signals is raised. This phase shift increase is a result of the relation of the constant tMAR 2  to the cycle time that decreases with increasing frequency. 
     As shown in FIG. 7, a second internal clock signal DCLK is generated by a DLL of the DDR SDRAM. The internal clock signal DCLK and the system clock signal VCLK each have the same frequency. However, the internal clock signal DCLK is advanced with respect to the system clock signal VCLK by a constant amount tMAR 1  that is dependent on the chip temperature, process variation and the operating frequency. The purpose of advancing the internal clock signal DCLK relative to the system clock signal VCLK is to time internal events within the DDR SDRAM so that they are edge aligned with the system clock signal VCLK when observed at the external DDR SDRAM pin. 
     As shown in FIG. 7, the signal SIG clk1  is generated synchronously with the clock signal ICLK. Next, the signal SIG clk1  is synchronized with and handled to the internal clock signal DCLK. As shown in FIG. 7, the signal SIG clk2  shows the timing of the signal after latching (synchronizing) the signal SIG clk1  to the internal clock signal DCLK domain. Signal SIG&#39; clk2  shows the signal SIG clk2  after being shifted by one clock cycle DCLK. 
     As shown in FIG. 8, a different situation occurs when the system operates at a fast operating frequency, such as 200 MHz. In particular, while the internal clock signal ICLK still has the same frequency as the system clock signal VCLK, it lags the system clock signal VCLK by a constant amount tMAR 2  that results in a greater phase delay than that shown in the slow frequency case described previously with respect to FIG.  7 . In addition, while the internal clock signal DCLK and the system clock signal VCLK each have the same frequency, the internal clock signal DCLK is advanced with respect to the system clock signal VCLK by a constant amount tMAR 1  that is also greater than the phase delay described previously with respect to the slow frequency case of FIG.  7 . As shown in FIG. 8, the signal SIG clk1  is generated synchronously with respect to the clock signal. Similarly, the signal SIG clk1  now has to be synchronized and handled to the internal clock signal DCLK. As shown in FIG. 8, the signal SIG clk2  shows the timing of the signal SIG clk1  after being latched (synchronized) to the internal clock signal DCLK domain. The signal SIG clk2  of FIG. 8 shows the signal SIG clk2  after being shifted by one clock cycle of the internal clock signal DCLK. The end result is that the relative timing of the clock signals ICLK and DCLK in the fast frequency case is drastically different when compared with the slow frequency case. 
     With the above-described disparity in the relative timing it makes it very difficult to run commands within the DDR SDRAM in a consistent manner independent of the operating frequency of the system. For example, suppose that an output signal of the DDR SDRAM needs to be observed three VCLK cycles after the generation of the signal SIG CLK1 . If the system was in the slow frequency mode, then the output signal would occur upon the DDR SDRAM chip counting the four DCLK pulses T 0 , T 1 , T 2  and T 3 . In contrast, the output signal would occur after the chip counted only the three DCLK pulses T 1 , T 2  and T 3  in the fast frequency mode. Thus, the DDR SDRAM chip is unable to consistently run the output command based solely on the number of DCLK pulses counted. This inconsistency limits the maximum frequency at which the DDR SDRAM can be operated with a DDR system. 
     SUMMARY OF THE INVENTION 
     One aspect of the present invention regards a method of using a memory chip that includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal contains information regarding an operational frequency of a system clock signal of the memory system. 
     The above aspect of the present invention provides the advantage of simplifying control SDRAM control logic and therefore reducing die size. 
     The above aspect of the present invention provides the advantage of enabling high operation frequencies and thus increasing the SDRAM internal timing margin. 
    
    
     The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 schematically shows a top view of an embodiment of a known memory chip; 
     FIG. 2 shows a block diagram of the memory chip of FIG. 1; 
     FIG. 3 schematically shows an embodiment of a memory array to be used with the memory chip of FIG. 1; 
     FIG. 4 schematically shows an embodiment of a memory cell to be used with the memory array of FIG. 3; 
     FIG. 5 schematically shows a top view of a second embodiment of a known memory chip; 
     FIG. 6 shows a block diagram of the memory chip of FIG. 5; 
     FIG. 7 shows a first timing diagram for a third embodiment of a known memory chip; 
     FIG. 8 shows a second timing diagram for the third embodiment of a known memory chip; 
     FIG. 9 shows a timing diagram showing a first embodiment of a power up command series for the memory systems of FIGS. 1-6 according to the present invention; and 
     FIG. 10 shows a timing diagram showing a second embodiment of a power up command series for the memory systems of FIGS. 1-6 according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As shown in FIG. 9, a synchronous power up command series for the memory chips  100  and  200  of FIGS. 1-6 and the previously described DDR SDRAM chip is shown. It should be noted that the present invention can be used with other types of memory chips that need to synchronize signals between independent scaling clocking phases, such as DDR SGRAM, DDR 2  SDRAM and SRAM memory chips. In particular, a command COM is latched onto a specific timing protocol at or near the end of the power up sequence of the memory chip when the external or system clock is stable. Note that the power up sequence is chosen because it occurs prior to the issuance of any commands within the memory chip. The command COM specifies a specific value or range of values for the system operation/system clock frequency. Consequently, the system operations/system clock frequency can be used for all internal commands that occur after power up. 
     As shown in FIG. 9, a possible timing protocol is to generate the command COM during the chip select CS signal and just before the mandatory refresh command REF in a DRAM memory chip&#39;s power up sequence. The command COM can also be generated just after the refresh command REF. In either event, the memory chip has obtained, via the command COM, the operation/system clock frequency which is stable no matter whether the system frequency is high or low. Accordingly, output signals can be consistently identified by the memory irrespective of the operating frequency. 
     Another method of specifying a system operation frequency to the memory chip is shown in FIG.  10 . In this method, a command COM is issued any time after the system power has been established. In this scenario, the system clock is not necessarily stable and so the command COM is not latched onto the system clock or any specified timing protocol. Accordingly, the command COM has to be issued asynchronously with respect to the system clock. In this mode of operation, at chip select CS high, the command COM results in the controller of the memory chip comparing the voltage levels of the pins of the memory chip and determining which of the pins are at a high state and which pins are at a low state. The controller then decodes the high and low state pins so as to determine a target frequency or target frequency range Thus, the memory chip has again obtained the operation/system clock frequency which is stable no matter whether the system frequency is high or low. Accordingly, output signals can be consistently identified by the memory irrespective of the operating frequency. 
     Once the operation/system clocking frequency is determined in the manner described above, the determined clocking frequency can be used to improve the operation of the memory system. For example, the delay line length of a delay-locked-loop of a DDR SDRAM can be pre-adjusted based on the determined clocking frequency so as to be decreased to the delay-locked-loop&#39;s locking time and possibly its power consumption. In addition, memory chip internal signals can be safely synchronized to different phased clocking domains at a higher frequency range based on the determined clocking frequency. The determined clocking frequency can also be used to indicate timing protocols for devices that are specified to run in different types of systems. This provides the advantage that one memory chip would be able to meet different output specifications (e.g. different specifications for different grades of speed (high-/low-end systems)). Meeting different output specifications saves development and production costs. In addition, the determined clocking frequency can be stored on the memory chip and be used for choosing different computing modes, such as delaying the timing of an internal clock of the memory chip so as to correct the situation discussed previously with respect to FIGS. 7 and 8. 
     The foregoing description is provided to illustrate the invention, and is not to be construed as a limitation. Numerous additions, substitutions and other changes can be made to the invention without departing from its scope as set forth in the appended claims.