Abstract:
A board duplexing apparatus for an asynchronous transfer mode (ATM) switch and a method of controlling the same. The method comprises the step of monitoring in real time whether duplexed boards in each pair of duplexed boards of the ATM switch process ATM cells independently of each other or are subject to occurrence of a fault, the step of, upon the fault occurrence in a specific one of the duplexed board pairs, releasing a connection to a faulty one of the duplexed boards in the specific duplexed board pair and setting up a connection to the other duplexed board in the specific duplexed board pair, and the step of setting up a new version of connection information of the faulty duplexed board in the other duplexed board, providing an ATM cell service to all subscribers and returning to a normal state if the fault is removed. According to the invention, if a fault occurs in any board, a duplexing operation is performed, resulting in an increase in system reliability. If no fault occurs in any board, cells are processed by two independent ATM switch systems, resulting in an increase in system efficiency.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates in general to a board duplexing apparatus for an asynchronous transfer mode (ATM) switch and a method of controlling the same, and more particularly to a technique for individually duplexing all boards in an ATM switch, associated with a subscriber module, to increase a system efficiency.  
           [0003]    2. Description of the Related Art  
           [0004]    As well known to those skilled in the art, an ATM switch is a communication system that switches signals on a number of subscriber lines at high speed. The ATM switch, however, has a disadvantage in that it cannot process signals from a number of subscribers at the same time if a fault occurs in a circuit board or line for signal processing.  
           [0005]    In order to solve the above problem with the ATM switch, there is a need for a duplexing technique to dually install circuit boards and lines in the ATM switch with duplicate boards and lines. Unfortunately, this duplexing may result in an increase in cost and a reduction in efficiency. In this regard, there is another need for a duplexing scheme capable of attaining the maximum efficiency at the minimum cost.  
           [0006]    [0006]FIG. 1 is a functional block diagram of a conventional board duplexing apparatus for an ATM switch. As shown in this drawing, the conventional board duplexing apparatus comprises a subscriber module  10  for accommodating a plurality of subscribers to the ATM switch, and a synchronous digital hierarchy (SDH) interface card (SIC)  11  matching-connected to the subscriber module  10  through an optical line (interval A) for receiving an SDH frame from the subscriber module  10  at its ingress, extracting a plurality of cells from the received SDH frame and outputting the extracted cells at its egress. The SIC  11  is also adapted to receive a plurality of cells at its egress, convert the received cells into an SDH frame and transfer the converted SDH frame to the subscriber module  10  at its ingress.  
           [0007]    The conventional board duplexing apparatus further comprises first and second ATM port management cards (APMCs)  12  and  13 , each of which is matching connected to the SIC  11  through a Utopian data bus (interval B) to send and receive cells to/from the SIC  11 . Each of the first and second APMCs  12  and  13  receives a plurality of cells from the SIC  11  at its ingress, detects or looks up headers of the received cells, appends routing tags respectively to the detected or looked-up headers, stacks the resulting cells in its internal buffer and then outputs the stacked cells at its egress according to scheduling. Each of the first and second APMCs  12  and  13  further receives a plurality of cells at its egress, performs a traffic shaping operation with respect to headers of the received cells such that the cells are appropriate to a data transfer rate of the Utopian data bus, and then transfers the resulting cells to the SIC  11  at its ingress.  
           [0008]    The conventional board duplexing apparatus further comprises first and second switches  14  and  15 , each of which is connected to the first and second APMCs  12  and  13  through serial links (interval C). Each of the first and second switches  14  and  15  receives a plurality of cells with routing tags from the first or second APMC  12  or  13  at its ingress and routes the received cells at its egress. Each of the first and second switches  14  and  15  also receives a plurality of cells at its egress and outputs the received cells to the first or second APMC  12  or  13  at its ingress.  
           [0009]    A description will hereinafter be given of the operation of the conventional board duplexing apparatus with the above-mentioned construction with reference to FIG. 1.  
           [0010]    In the normal initial state of the ATM switch as shown in FIG. 1, the first APMC  12  and first switch  14  are set to an active mode, whereas the second APMC  13  and second switch  15  are set to a standby mode.  
           [0011]    The second APMC  13  of the standby mode is inhibited from making a connection to a Utopian data bus  2  under a bus switch control, while only the first APMC  12  of the active mode is connected to a Utopian data bus  1  under a bus switch control and in turn to the SIC  11  so as to send and receive cells to/from the SIC  11 .  
           [0012]    Further, the first APMC  12  sends cells to both the first switch  14  and second switch  15 , but receives and switches cells from only the first switch  14  of the active mode.  
           [0013]    In other words, cells from a connection, to be sent to a destination, are applied to and stored in both the first APMC  12  of the active mode and the second APMC  13  of the standby mode.  
           [0014]    If a fault occurs in the first APMC  12 , the first APMC  12  is disconnected from the Utopian data bus  1  by a bus switch operation under a buffer control so as to enter the standby mode, and the second APMC  13  is connected to the Utopian data bus or bus master  2  by a bus switch operation so as to enter the active mode. As a result, the second APMC  13  is connected to the SIC  11  to send and receive cells to/from the SIC  11 .  
           [0015]    Further, the second APMC  13  sends cells to both the first switch  14  and second switch  15 , but receives and switches cells from only the first switch  14  of the active mode.  
           [0016]    At this time, if a fault occurs in the first switch  14 , the second switch  15  receives and switches cells from the second APMC  13 .  
           [0017]    The above-mentioned conventional board duplexing apparatus for the ATM switch is desirable to increase reliability of the system, but disadvantageous in that the same function blocks for duplexing are kept unused in the standby mode, resulting in a reduction in efficiency and an increase in opportunity cost.  
         SUMMARY OF THE INVENTION  
         [0018]    Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a board duplexing apparatus for an ATM switch and a method of controlling the same, wherein each function block of an ATM switch is duplexed in such a manner that the duplexed function blocks are operated independently of each other to process cells, and a duplexing operation is performed if a fault occurs in any one of the duplexed function blocks, thereby increasing a system efficiency of the ATM switch.  
           [0019]    In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a board duplexing apparatus for an asynchronous transfer mode (ATM) switch, comprising a plurality of subscriber modules, each of the subscriber modules accommodating a plurality of subscribers to the ATM switch; a plurality of synchronous digital hierarchy (SDH) interface cards (SICs) matching-connected respectively to the subscriber modules, each of the SICs receiving an SDH frame from a corresponding one of the subscriber modules at its ingress, extracting a plurality of ATM cells from the received SDH frame, outputting the extracted cells at its egress, receiving a plurality of cells at its egress, converting the received cells into an SDH frame and transferring the converted SDH frame to the corresponding subscriber module at its ingress; a plurality of ATM port management cards (APMCs), each of the APMCs receiving the ATM cells from each of the SlCs at its ingress, looking up headers of the received cells, appending routing tags respectively to the looked-up headers, outputting the resulting cells at its egress, receiving a plurality of cells at its egress, performing a traffic shaping operation with respect to headers of the received cells and transferring the resulting cells to an associated one of the SICs at its ingress; and a plurality of switches, each of the switches receiving the ATM cells with the routing tags from each of the APMCs at its ingress, routing the received cells at its egress, receiving a plurality of cells at its egress and outputting the received cells to an associated one of the APMCs at its ingress.  
           [0020]    In accordance with another aspect of the present invention, there is provided a method of controlling a board duplexing operation of an asynchronous transfer mode (ATM) switch, comprising the steps of a) monitoring in real time whether duplexed boards in each pair of duplexed boards of the ATM switch process ATM cells independently of each other or are subject to occurrence of a fault; b) upon the fault occurrence in a specific one of the duplexed board pairs, releasing a connection to a faulty one of the duplexed boards in the specific duplexed board pair and setting up a connection to the other duplexed board in the specific duplexed board pair; and c) setting up a new version of connection information of the faulty duplexed board in the other duplexed board, providing an ATM cell service to all subscribers and returning to a normal state if the fault is removed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0022]    [0022]FIG. 1 is a functional block diagram of a conventional board duplexing apparatus for an ATM switch;  
         [0023]    [0023]FIG. 2 is a functional block diagram of a board duplexing apparatus for an ATM switch in accordance with the present invention;  
         [0024]    [0024]FIG. 3 is a flowchart illustrating a method of controlling a board duplexing operation of an ATM switch in accordance with the present invention; and  
         [0025]    [0025]FIG. 4 is a detailed functional block diagram of an APMC in accordance with the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]    [0026]FIG. 2 is a functional block diagram of a board duplexing apparatus for an ATM switch in accordance with the present invention.  
         [0027]    With reference to FIG. 2, the present board duplexing apparatus comprises first and second subscriber modules  20  and  21 , each of which receives ATM cells from a plurality of subscribers. The first and second subscriber modules  20  and  21  are connected to first and second SICs  22  and  23  via optical lines A, respectively, to send and receive corresponding ATM cells from/to the first and second SICs  22  and  23 .  
         [0028]    Alternatively, a synchronous transfer mode level N or digital signal level  3  (DS-3: communication access level equivalent to 28T1 channel and running at 44.736 Mbps) may be used between each of the first and second SICs  22  and  23  and each of the first and second subscriber modules  20  and  21  instead of the SDH interface.  
         [0029]    STM-N is a transfer mode of SDH-based optical fiber digital communication. The basic STM-N is called STM- 1  with a transfer rate of 155.5 Mbps.  
         [0030]    The transfer rate of STM is defined as basic rate by N, namely, STM- 3 =466.56 Mbps, STM- 4 =622.08 Mbps, STM- 6 =933.12 Mbps, STM- 8 =1224.16 Mbps, STM- 12 =1866.24 Mbps, STM- 16 =2.48 Gbps, and STM- 64 =9.95 Gbps.  
         [0031]    The first SCI  22  extracts a plurality of ATM cells from an SDH frame from the first subscriber module  20  and sends the extracted ATM cells to first and second APMCs  24  and  25  respectively via Utopian data buses  1  and  6 .  
         [0032]    The second SCI  23  extracts a plurality of ATM cells from an SDH frame from the second subscriber module  21  and sends the extracted ATM cells to the first and second APMCs  24  and  25  respectively via the Utopian data bus  6  and a Utopian data bus  7 .  
         [0033]    In other words, the first SIC  22  receives an SDH frame from the first subscriber module  20  at its ingress over the associated optical line A, extracts a plurality of ATM cells from the received SDH frame and outputs the extracted ATM cells to both the first and second APMCs  24  and  25  at its egress over the associated Utopian data buses  1  and  6 .  
         [0034]    At this time, the first SIC  22  is connected respectively to the first APMC  24  in an active mode and the second APMC  25  in a standby mode.  
         [0035]    Accordingly, cells sent and received between the first SIC  22  and the first APMC  24  over the Utopian data bus  1  are validly processed, while cells sent and received between the first SIC  22  and the second APMC  25  over the Utopian data bus  6  are stored in an internal memory of the second APMC  25 , and not processed.  
         [0036]    Similarly, the second SIC  23  is connected simultaneously to the first and second APMCs  24  and  25  via the associated Utopian data buses  6  and  7  to send and receive cells to/from the first and second APMCs  24  and  25 . At this time, the second SIC  23  is connected to the second APMC  25  in the active mode, thereby making it valid to process cells sent and received over the Utopian data bus  7 . Alternatively, the second SIC  23  is connected to the first APMC  24  in the standby mode, thereby causing the first APMC  24  to store cells from the second SIC  23  in its internal memory, and not process the cells.  
         [0037]    The first APMC  24  looks up headers of ATM cells received in the active mode, appends routing tags respectively to the looked-up headers, stores the resulting cells in its internal buffer and then outputs the stored cells to both first and second switches  26  and  27  according to scheduling.  
         [0038]    The first APMC  24  is connected to the first and second switches  26  and  27  via serial links  3  and  5 , respectively. At this time, the first APMC  24  is connected to the first switch  26  in the active mode.  
         [0039]    As a result, the first switch  26  switches ATM cells from the first APMC  24  connected thereto in the active mode, whereas the second switch  27  stores the ATM cells from the first APMC  24 , and not switches them.  
         [0040]    Similarly, the second APMC  25  provides its ATM cells to both the first and second switches  26  and  27  respectively via the serial link  5  and a serial link  4 . At this time, the second APMC  25  is connected to the second switch  27  in the active mode, thereby allowing the second switch  27  to switch the ATM cells from the second APMC  25 .  
         [0041]    A more detailed description will hereinafter be given of the construction of each of the first and second APMCs  24  and  25  as stated above, with reference to FIG. 4.  
         [0042]    The first APMC  24  includes a buffer A  31  connected to the first SIC  22  for temporarily storing ATM cells from the first SIC  22 , and a buffer B  32  connected to the second SIC  23  for temporarily storing ATM cells from the second SIC  23 .  
         [0043]    A controller  36  is provided in the first APMC  24  to monitor and control respective function blocks of the first APMC  24 . The buffer A  31  and buffer B  32  are set to either of the active mode and standby mode under the control of the controller  36 . In the present embodiment, the buffer A  31  is initially set to the active mode and the buffer B  32  is initially set to the standby mode.  
         [0044]    A cell processor  34  is provided in the first APMC  24  to process ATM cells from the first SIC  22 , stored in the buffer A  31  of the active mode, under the control of the controller  36 . The cell processor  34  looks up headers of the ATM cells from the first SIC  22 , appends routing tags respectively to the looked-up headers and temporarily stores the resulting cells in its internal buffer, as well as storing them in a memory  38 .  
         [0045]    The controller  36  outputs the ATM cells stored in the buffer of the cell processor  34  to both the first and second switches  26  and  27  according to scheduling, respectively, via serial links. At this time, the first APMC  24  is connected to the first switch  26  in the active mode and the second switch  27  in the standby mode, respectively.  
         [0046]    The first APMC  24  and the second APMC  25  are substantially the same in construction, and process reverse cells to the above cells in the same manner as the above.  
         [0047]    Next, a detailed description will be given of the operation of the board duplexing apparatus for the ATM switch with the above-stated construction in accordance with the preferred embodiment of the present invention with reference to FIG. 3.  
         [0048]    [0048]FIG. 3 is a flowchart illustrating a method of controlling a board duplexing operation of the ATM switch in accordance with the present invention.  
         [0049]    Under the condition that the ATM switch with the above-described duplex board is normally operated, in the connection interval B, the Utopian data bus  1  between the first SIC  22  and the first APMC  24  is in the active mode and the Utopian data bus  6  between the first SIC  22  and the second APMC  25  is in the standby mode. As a result, ATM cells from the first SIC  22  are not subjected to a process by the cell processor  34 ′ due to the operation of the buffer  31 ′, which functions as a bus switch.  
         [0050]    At this time, in a similar manner to the first SIC  22 , in the second SIC  23 , the Utopian data bus  7  is in the active mode and the Utopian data bus  6  is in the standby mode.  
         [0051]    The first APMC  24  selects the serial link  3  in the interval C as an active path to the first switch  26 .  
         [0052]    Similarly, the second APMC  25  selects the serial link  4  as an active path to the second switch  27 . Therefore, two individual systems are operated independently of each other.  
         [0053]    That is, the first subscriber module  20 , first SIC  22 , first APMC  24  and first switch  26  are operated as one individual ATM switch system, and the second subscriber module  21 , second SIC  23 , second APMC  25  and second switch  27  are operated as the other individual ATM switch system.  
         [0054]    On the other hand, in the first and second APMCs  24  and  25 , each of the controllers  36  and  36 ′ integratedly manages even traffic information or connection information from the other controller via a duplex data channel and has a minimum cell rate (MCR) that does not exceed a maximum port capacity of the other controller. Because the controllers  36  and  36 ′ exchange their connection information with each other, they store each other&#39;s connection information in the corresponding memories  38  and  38 ′.  
         [0055]    Under the above operating condition, the states of respective function boards are checked (S 10 ) to determine whether there is a faulty one among the function boards (S 11 ). If it is determined at step S 11  that there is no faulty one among the function boards, two individual ATM switch systems are allowed to be operated independently of each other (S 12 ).  
         [0056]    In the case where it is determined at the above step S 11  that there is a faulty one among the function boards, a determination is made as to whether a fault has occurred in the first APMC  24  (S 13 ). Where a fault has occurred in the first APMC  24 , the controller  36  in the first APMC  24  reports the controller  36 ′ in the second APMC  25  via the duplex data channel that the fault has occurred in the first APMC  24 , and controls the buffer A  31  to release its connection to the Utopian data bus  1 . As a result, the first APMC  24  is disconnected from the Utopian data bus  1  so as to enter the standby mode (S 16 ).  
         [0057]    The controller  36 ′ in the second APMC  25  changes the buffer A  31 ′ from the disconnection mode or standby mode to the active mode, thereby causing the first SIC  22  and the second APMC  25  to be interconnected. As a result, the output cells from the first SIC  22  are applied to the second APMC  25  over the Utopian data bus  6  of the active mode (S 17 ).  
         [0058]    The second APMC  25  sets up a new version of the connection information of the first APMC  24  stored therein (S 18 ), and then notifies the first and second subscriber modules  20  and  21  of the fault occurrence and that the ATM cell service will be provided at the minimum cell rate (MCR) until the fault is removed (S 19 ).  
         [0059]    In response to such a notification, the first and second subscriber modules  20  and  21  sense the fault occurrence and thus adjust their cell rates to lower values.  
         [0060]    The first and second switches  26  and  27  are also connected to the second APMC  25  in the active mode to send and receive cells to/from the second APMC  25 . If a fault also occurs in the second switch  27  under the condition that the first APMC  24  has failed, the second APMC  25  changes the serial link to the first switch  26  from the standby mode to the active mode so as to send and receive cells to/from the first switch  26 .  
         [0061]    While cells from the first and second subscriber modules  20  and  21  are processed by means of the second APMC  25  as described above, a determination is made as to whether the current fault has been removed (S 21 ). If it is determined at step S 21  that the current fault has been removed, the control method returns to the original normal state (S 22 ), so the individual ATM switch services are performed independently of each other.  
         [0062]    As apparent from the above description, the present invention provides a board duplexing apparatus for an ATM switch and a method of controlling the same, wherein, if a fault occurs in any board, a duplexing operation is performed, resulting in an increase in system reliability, and, if no fault occurs in any board, cells are processed by two independent ATM switch systems, resulting in an increase in system efficiency.  
         [0063]    Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.