Abstract:
A switching circuit disclosed herein comprises: a transmission port; a first internal connection switching circuit which is connected between the transmission port and an antenna port and includes a depletion mode first transistor and a depletion mode second transistor, the first internal connection switching circuit constituting a parallel resonant circuit and a series resonant circuit; a reception port; a second internal connection switching circuit which is connected between the reception port and the antenna port and includes a depletion mode third transistor and a depletion mode fourth transistor, the second internal connection switching circuit constituting a parallel resonant circuit and a series resonant circuit; a standby port; a third internal connection switching circuit which is connected between the standby port and the antenna port and includes a depletion mode fifth transistor, the third internal connection switching circuit connecting the standby port to the antenna port and separating the standby port from the antenna port; and a control terminal.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims benefit of priority under 35 U.S.C.§119 to Japanese Patent Application No. 2004-121904, filed on April 16, 2004, the entire contents of which are incorporated by reference herein.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a switching circuit, and particularly relates to a switching circuit including a standby port.  
         [0004]     2. Background Art  
         [0005]     In recent years, an active radio tag system is being studied. A tag device used in such a system always needs to respond to a signal from an identification device, and hence the device not only needs to be always powered on but also needs to be operated for a long time by only a built-in battery. Therefore, a mechanism, in which a high-frequency signal is monitored by a monitoring circuit which operates with low power consumption in a standby mode, that is, a waiting state where no communication is performed and the entire system starts to operate when the signal is detected, is used. For this purpose, a transmission/reception switching circuit which has a standby port and whose power consumption in a standby mode is a few hundred nA or less is required. However, the control current in a today&#39;s general high-frequency switching circuit in which a GaAsFET is used is approximately a few μA. If the size of the FET is reduced, the control current can be reduced, but this causes a problem that the property required as the high-frequency switching circuit becomes unobtainable.  
         [0006]      FIG. 1  shows an example of the related high-frequency switching circuit. The general high-frequency switching circuit uses a depletion mode MESFET (Metal Semiconductor Field Effect Transistor), the general high-frequency switching circuit includes a transmission port, a reception port and a standby port. Transistors Q 1 , Q 2 , and Q 3  are respectively inserted between these ports and an antenna port.  
         [0007]     Reactance elements L 1 , L 2 , and L 3  are connected in parallel with the transistors Q 1 , Q 2 , and Q 3 , respectively. Gates of the transistors Q 1 , Q 2 , and Q 3  are connected to control terminals T 1 , T 2 , and T 3  via resistances R 1 , R 2 , and R 3 , respectively.  
         [0008]      FIG. 2  is a diagram showing a truth table for operating the high-frequency switching circuit in  FIG. 1 . As shown in  FIG. 2 , in order to turn off the transistors Q 1 , Q 2 , and Q 3 , the gate bias voltage needs to be a reverse bias. For this purpose, it is necessary to send a reverse current which is determined by a backward current at a Schottky junction to the gates of the transistors Q 1 , Q 2 , and Q 3 . For example, when the transistor Q 3  is turned on to thereby connect the standby port to the antenna port, it is necessary to apply a reverse bias to send a reverse current in order to turn off the transistors Q 1  and Q 2 . This reverse current is approximately a few μA in the case of the general high-frequency switching circuit. To reduce the backward current, the size of the FET has only to be reduced, but in this case, the property required as the high-frequency switching circuit becomes unobtainable.  
         [0009]     On the other hand, in T. Tokumitsu, I. Toyoda and M. Aikawa “A Low-Voltage, High-Power T/R-Switch MMIC Using LC Resonators”IEEE Trans. on Microwave Theory and Tech., vol. 43, No, 5, May 1995, pp. 997-1003, an antenna transmission/reception switching circuit shown in  FIG. 3  is disclosed. This switching circuit in  FIG. 3  includes transistors Q 11  to Q 16 , reactance elements L 11  and L 12 , and capacitors C 11  to C 14 .  
         [0010]      FIG. 4  is a diagram showing a truth table for operating the switching circuit in  FIG. 3 . As shown in  FIG. 3 , in such a switching circuit, when 0 V is applied to a control terminal T 11 , an antenna port is connected to a transmission port. However, since a standby port is not provided, if nothing is done, this switching circuit cannot be used in a system which needs the standby port. Moreover, a negative control circuit is needed, which causes a problem that the system is complicated.  
       SUMMARY OF THE INVENTION  
       [0011]     In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a switching circuit, comprises: 
        a transmission port which is connectable to a transmission circuit;     a first internal connection switching circuit which is connected between the transmission port and an antenna port and which includes a depletion mode first transistor and a depletion mode second transistor, the first internal connection switching circuit constituting a parallel resonant circuit by turning on the first transistor and the second transistor, and constituting a series resonant circuit by turning off the first transistor and the second transistor;     a reception port which is connectable to a reception circuit;     a second internal connection switching circuit which is connected between the reception port and the antenna port and which includes a depletion mode third transistor and a depletion mode fourth transistor, the second internal connection switching circuit constituting a parallel resonant circuit by turning on the third transistor and the fourth transistor, and constituting a series resonant circuit by turning off the third transistor and the fourth transistor;     a standby port which is connectable to a standby circuit;     a third internal connection switching circuit which is connected between the standby port and the antenna port and which includes a depletion mode fifth transistor, the third internal connection switching circuit connecting the standby port to the antenna port by turning on the fifth transistor, and separating the standby port from the antenna port by turning off the fifth transistor; and     a control terminal which is connected to the antenna port and to which a first voltage is inputted when the standby port is connected to the antenna port such that gate bias voltages of the first to fifth transistors become 0 V and the first to fifth transistors are turned on.       
 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]      FIG. 1  is a diagram showing an example of the configuration of a related switching circuit;  
         [0020]      FIG. 2  is a diagram showing a truth table explaining the operation of the switching circuit in  FIG. 1 ;  
         [0021]      FIG. 3  is a diagram showing an example of the configuration of another related switching circuit;  
         [0022]      FIG. 4  is a diagram showing a truth table explaining the operation of the switching circuit in  FIG. 3 ;  
         [0023]      FIG. 5  is a diagram showing an example of the configuration of a transmission/reception system according to a first embodiment;  
         [0024]      FIG. 6  is a diagram showing a truth table explaining the operation of a switching circuit in the transmission/reception system in  FIG. 5 ;  
         [0025]      FIG. 7  is a diagram showing an example of the configuration of a transmission/reception system according to a second embodiment; and  
         [0026]      FIG. 8  is a diagram showing an example of the configuration of a transmission/reception system according to a third embodiment. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
     First Embodiment  
       [0027]      FIG. 5  is a diagram showing the internal configuration of a transmission/reception system according to this embodiment, and  FIG. 6  is a diagram showing a truth table explaining the operation of the transmission/reception system in  FIG. 5 .  
         [0028]     As shown in  FIG. 5 , the transmission/reception system according to this embodiment includes an antenna  100 , a switching circuit SW 100 , a transmission circuit  101 , a reception circuit  102 , a standby circuit  103 , and a control circuit  110 .  
         [0029]     The switching circuit SW 100  includes a first internal connection switching circuit SW 101 , a second internal connection switching circuit SW 102 , and a third internal connection switching circuit SW 103 . The first internal connection switching circuit SW 101  is provided between an antenna port and a transmission port, the second internal connection switching circuit SW 102  is provided between the antenna port and a reception port, and the third internal connection switching circuit SW 103  is provided between the antenna port and a standby port.  
         [0030]     The antenna  100  is connected to the antenna port. The transmission circuit  101  is connected to the transmission port. A high-frequency signal generated in the transmission circuit  101  is transmitted to the antenna  100  via the first internal connection switching circuit SW 101  and sent out from the antenna  100 .  
         [0031]     The reception circuit  102  is connected to the reception port. A high-frequency signal received by the antenna  100  is transmitted to the reception circuit  102  via the second internal connection switching circuit SW 102  and subjected to necessary processing such as amplification, demodulation, or the like in the reception circuit  102 .  
         [0032]     The standby circuit  103  is connected to the standby port. When this transmission/reception system is in a waiting state, the transmission circuit  101  and the reception circuit  102  are in a standby state where electric power is hardly consumed. When a high-frequency signal is inputted from the antenna  100  in this standby state, this high-frequency signal is received by the standby circuit  103  via the third internal connection switching circuit SW 103  to start the operations of the other circuits, that is, the transmission circuit  101  and the reception circuit  102 .  
         [0033]     The first internal connection switching circuit SW 101  includes a reactance element L 101 , capacitors C 101  and C 102 , transistors Q 101  and Q 102 , and resistances R 101  and R 102 . In this embodiment, the transistors Q 101  and Q 102  are each constituted by a depletion mode MESFET.  
         [0034]     More specifically, the capacitor C 101  and the transistors Q 101  and Q 102  are connected in series between the antenna port and the transmission port. The reactance element L 101  is connected in parallel with the capacitor C 101  and the transistor Q 101 , and the capacitor C 102  is connected in parallel with the transistor Q 102 . A gate of the transistor Q 101  is connected to a control terminal T 102  via the resistance R 101 , and a gate of the transistor Q 102  is connected to the control terminal T 102  via the resistance R 102 . These resistances R 101  and R 102  each have a relatively high resistance value (10 kΩ, for example). In this embodiment, a positive voltage or 0 V is inputted to the control terminal T 102  from the control circuit  110 . Incidentally, positive voltages in  FIG. 6  are all the same voltage (5 V, for example). Here, 0 V applied from the control circuit  110  corresponds to a first voltage, and the positive voltage corresponds to a second voltage in this embodiment.  
         [0035]     The second internal connection switching circuit SW 102  includes a reactance element L 102 , capacitors C 103  and C 104 , transistors Q 103  and Q 104 , and resistances R 103  and R 104 . In this embodiment, the transistors Q 103  and Q 104  are each constituted by a depletion mode MESFET.  
         [0036]     The concrete connection relationship among these elements in the second internal connection switching circuit SW 102  is the same as that in the aforementioned first internal connection switching circuit SW 101 . Also in this embodiment, the positive voltage or 0 V is inputted to a control terminal T 103  from the control circuit  110 .  
         [0037]     The third internal connection switching circuit SW 103  includes a transistor Q 105  and a resistance R 105 . In this embodiment, the transistor Q 105  is constituted by a depletion mode MESFET.  
         [0038]     More specifically, the transistor Q 105  is provided between the antenna port and the standby port. A gate of the transistor Q 105  is connected to a ground via the resistance R 105 . Namely, a ground voltage is fixedly inputted to the gate of the transistor Q 105 . The resistance R 105  has a relatively high resistance value (10 kΩ, for example).  
         [0039]     The antenna port is connected to a control terminal T 101  via a resistance R 106 . This resistance R 106  has a sufficiently high resistance value (10 kΩ, for example) with respect to an impedance (50 Ω, for examle) of a high-frequency signal line. In this embodiment, the positive voltage or 0 V is also inputted to the control terminal T 101  from the control circuit  110 .  
         [0040]     When the gate bias voltage of the control terminal T 102  is 0 V, the transistors Q 101  and Q 102  are turned on, the first internal connection switching circuit SW 101  becomes a parallel resonant circuit composed of the reactance element L 101  and the capacitor C 101 , and thereby the high-frequency signal is cut off. Therefore, the transmission circuit  101  and the antenna port are separated from each other.  
         [0041]     On the other hand, when the gate bias voltage of the control terminal T 102  is a reverse bias, the transistors Q 101  and Q 102  are turned off, the first internal connection switching circuit SW 101  becomes a series resonant circuit composed of the reactance element L 101  and the capacitor C 102 , and thereby the high-frequency signal can pass therethrough. Therefore, the transmission circuit  101  and the antenna port are connected to each other.  
         [0042]     Accordingly, values of the reactance elements L 101  and L 102  and the capacitors C 101  to C 104  are set to values such as resonate at a frequency to be used with consideration given to a stray capacitance such as the off capacitance of the FETs. The aforementioned cutoff/passage of the high-frequency signal applies to the second internal connection switching circuit SW 102 . Incidentally, in this embodiment, the reactance elements L 101  and L 102  are each formed by a coil.  
         [0043]     Next, the concrete operation of the switching circuit SW 100  will be explained. As shown in  FIG. 6 , when the transmission circuit  101  is connected to the antenna port, the control circuit  110  inputs the positive voltage to the control terminal T 101  and the control terminal T 103  and inputs 0 V to the control terminal T 102 . As a result, the gate bias voltages of the transistors Q 101  and Q 102  each become a reverse bias, and thereby the transistors Q 101  and Q 102  are turned off. Hence, as described above, the first internal connection switching circuit SW 101  becomes the series resonant circuit composed of the reactance element L 101  and the capacitor C 102 , whereby the high-frequency signal from the transmission circuit  101  is transmitted to the antenna port.  
         [0044]     At this time, the gate bias voltages of the transistors Q 103  and Q 104  are 0 V, whereby the transistors Q 103  and Q 104  are turned on. Therefore, as described above, the second internal connection switching circuit SW 102  becomes a parallel resonant circuit composed of the reactance element L 102  and the capacitor C 103 , whereby the high-frequency signal from the antenna port is cut off. The gate bias voltage of the transistor Q 105  also becomes a reverse bias, whereby the transistor Q 105  is turned off. Hence, the standby circuit  103  is separated from the antenna port.  
         [0045]     When the reception circuit  102  is connected to the antenna port, the control circuit  110  inputs the positive voltage to the control terminal T 101  and the control terminal T 102  and inputs 0 V to the control terminal T 103 . Consequently, in accordance with the same operation as described above, only the reception circuit  102  is connected to the antenna port.  
         [0046]     When the standby circuit  103  is connected to the antenna port, the control circuit  110  inputs 0 V to the control terminals T 101  to T 103 . As a result, the gate bias voltages of all the transistors Q 101  to Q 105  become 0 V, whereby all the transistors Q 101  to Q 105  are turned on. Accordingly, the first internal connection switching circuit SW 101  becomes the parallel resonant circuit composed of the reactance element L 101  and the capacitor C 101 , whereby the high-frequency signal is cut off. The second internal connection switching circuit SW 102  becomes the parallel resonant circuit compose of the reactance element L 102  and the capacitance C 103 , whereby the high-frequency signal is cut off. The third internal connection switching circuit SW 103  is brought into a low-impedance state since the transistor Q 105  is turned on, whereby the antenna port and the standby port are connected to each other.  
         [0047]     As described above, in the switching circuit according to this embodiment, when all the control terminals T 101  to T 103  are set to 0 V, the antenna port is connected to the standby port, whereby, in a standby mode, power consumption can be reduced to a minimum. As a result, the available time of the system driven by the battery can be prolonged. Moreover, since the voltage applied to the control terminals T 101  to T 103  can be set to the positive voltage or 0 V, a negative control voltage is unnecessary, which makes it possible to simplify the entire configuration of this transmission/reception system.  
       Second Embodiment  
       [0048]      FIG. 7  is a diagram explaining the internal configuration of a transmission/reception system according to the second embodiment. This embodiment is different from the aforementioned first embodiment in the configuration of a switching circuit SW 200 .  
         [0049]     As shown in  FIG. 7 , in the switching circuit SW 200  according to this embodiment, a reactance element L 203  is additionally connected in parallel with the transistor Q 105  of the third internal connection switching circuit SW 103 . This reactance circuit L 203  has an inductance which resonates with the off capacitance of the transistor Q 105  at a frequency at which this switching circuit is used. Incidentally, in this embodiment, the reactance element L 203  is formed by a coil.  
         [0050]     Consequently, isolation between the antenna port and the standby port when the transistor Q 105  is turned off can be improved as compared with the case where the reactance element L 203  is not provided. Namely, a parallel resonant circuit is composed of the off capacitance of the transistor Q 105  and the reactance element L 203 , whereby the high-frequency signal can be cut off more certainly.  
         [0051]     Incidentally, the operation of the switching circuit in this embodiment is the same as that in the aforementioned first embodiment. Namely, a truth table to operate the switching circuit in  FIG. 7  is the same as that in  FIG. 6 .  
       Third Embodiment  
       [0052]      FIG. 8  is a diagram showing the configuration of a transmission/reception system according to this embodiment. As shown in  FIG. 8 , in a switching circuit SW 300  of the transmission/reception system according to this embodiment, shunt circuits SH 301 , SH 302 , and SH 303  are additionally connected to the transmission port, the reception port, and the standby port in the second embodiment, respectively. Namely, the shunt circuit SH 301  is connected between the transmission port and the ground, the shunt circuit  302  is connected between the reception port and the ground, and the shunt circuit SH 303  is connected between the standby port and the ground. Moreover, a resistance R 302  is connected in parallel with the capacitor C 102 , and a resistance R 304  is connected in parallel with the capacitor C 104 .  
         [0053]     The shunt circuit SH 301  includes a transistor Q 301 , a capacitor C 301 , and a resistance R 301 . In this embodiment, the transistor Q 301  is constituted by a depletion mode MESFET. The transistor Q 301  and the capacitor C 301  are connected in series between the transmission port and the ground. A gate of the transistor Q 301  is connected to the control terminal T 102  via the resistance R 301 .  
         [0054]     The shunt circuit SH 302  includes a transistor Q 302 , a capacitor C 302 , and a resistance R 303 . In this embodiment, the transistor Q 302  is constituted by a depletion mode MESFET. The transistor Q 302  and the capacitor C 302  are connected in series between the reception port and the ground. A gate of the transistor Q 302  is connected to the control terminal T 103  via the resistance R 303 .  
         [0055]     The shunt circuit SH 303  includes a reactance element L 303 , capacitors C 303  to C 305 , transistors Q 303  and Q 304 , and resistances R 305  and R 306 . The capacitor C 303 , the transistor Q 303 , the transistor Q 304 , and the capacitor C 305  are connected in series in this order between the standby port and the ground. The reactance element L 303  is connected in parallel with the capacitor C 303  and the transistor Q 303 . The capacitor C 304  is connected in parallel with the transistor Q 304 . A gate of the transistor Q 303  is connected to the ground via the resistance R 305 , and a gate of the transistor Q 304  is connected to the ground via the resistance R 306 . In other words, in this embodiment, the ground voltage is fixedly inputted to the gates of the transistors Q 303  and Q 304 . Incidentally, in this embodiment, the reactance element L 303  is formed by a coil.  
         [0056]     The operation of the switching circuit in this embodiment is the same as that in the aforementioned first embodiment. Namely, a truth table to operate the switching circuit SW 300  in  FIG. 8  is the same as that in  FIG. 6 .  
         [0057]     When the transmission port is connected to the antenna port, the positive voltage is inputted to the control terminals T 101  and T 103 , and 0 V is inputted to the control terminal T 102 . In this case, as explained in the first embodiment, the high-frequency signal from the transmission circuit  101  is transmitted to the antenna port, and the high-frequency signal from the antenna port to the reception circuit  102  and the standby circuit  103  is cut off.  
         [0058]     Moreover, in this embodiment, the gate bias voltage of the transistor Q 301  becomes a reverse bias, whereby the transistor Q 301  is turned off. Namely, the positive voltage inputted to the control terminal T 101  is applied to a drain of the transistor Q 301  via the reactance element L 101  and the resistance R 302 . Since the control terminal T 102  is at 0 V, the gate bias voltage of the transistor Q 301  becomes the reverse bias, whereby the transistor Q 301  is turned off. When the transistor Q 301  is turned off, the transmission port is separated from the ground, whereby the high-frequency signal outputted from the transmission circuit  101  is transmitted to the antenna port.  
         [0059]     At this time, in the shunt circuit SH 302 , the positive voltage is inputted to the control terminals T 101  and T 103 , whereby the gate bias voltage of the transistor Q 302  becomes 0 V, and the transistor Q 302  is turned on. Hence, the reception port is connected to the ground, whereby the high-frequency signal leaking from the antenna port is grounded.  
         [0060]     In the shunt circuit SH 303 , the positive voltage of the control terminal T 101  is applied to a source of the transistor Q 303  and a drain of the transistor Q 304  via the reactance elements L 203  and L 303 . Consequently, the transistors  303  and Q 304  are reverse-biased and turned off. Therefore, the shunt circuit SH 303  becomes a series resonant circuit composed of the reactance element L 303  and the capacitor C 304 , and the high-frequency signal can pass therethrough. Accordingly, the high-frequency signal leaking from the antenna port is grounded.  
         [0061]     When the reception port is connected to the antenna port, the positive voltage is inputted to the control terminals T 101  and T 102 , and 0 V is inputted to the control terminal T 103 . In this case, as explained in the first embodiment, the reception circuit  102  is connected to the antenna port, and the transmission circuit  101  and the standby circuit  103  are separated from the antenna port. Further, in this embodiment, in accordance with the same operation as described above, the shunt circuit SH 301  is turned on, whereby the high-frequency signal leaking from the antenna port is grounded, and the shunt circuit SH 303  is also turned on, whereby the high-frequency signal leaking from the antenna port is grounded. The shunt circuit SH 302  is turned off, whereby the high-frequency signal from the antenna port is transmitted to the reception circuit  102 .  
         [0062]     When the standby port is connected to the antenna port, 0 V is inputted to all of the control terminals T 101 , T 102 , and T 103 . In this case, as explained in the first embodiment, the standby circuit  103  is connected to the antenna port, and the transmission circuit  101  and the reception circuit  102  are separated from the antenna port. Moreover, in this embodiment, in accordance with the same operation as described above, the shunt circuit SH 301  is turned on, whereby the high-frequency signal leaking from the antenna port is grounded, and the shunt circuit SH 302  is also turned on, whereby the high-frequency signal leaking from the antenna port is grounded.  
         [0063]     In the shunt circuit SH 303 , the gate bias voltages of the transistors Q 303  and Q 304  become 0 V, whereby the transistors Q 303  and Q 304  are turned on, and hence the shunt circuit SH 303  becomes a parallel resonant circuit composed of the capacitor C 303  and the reactance element L 303 . Consequently, in the shunt circuit SH 303 , the high-frequency signal from the antenna port is cut off and transmitted to the standby circuit  103 .  
         [0064]     As described above, according to the switching circuit of this embodiment, the transmission port, the reception port, and the standby port are provided with the shunt circuits SH 301  to SH 303 , respectively, and all but the ports connected to the antenna port are connected to the ground, whereby the leaking high-frequency signal can be grounded.  
         [0065]     It should be mentioned that the present invention is not limited to the aforementioned embodiments, and various changes may be made therein. For example, in the aforementioned embodiments, each of the transistors is formed by the MESFET which is constituted by using a compound semiconductor, but it may be formed by a HEMT (High Electron Mobility Transistor) which is constituted by using the compound semiconductor or a J-FET (Junction FET).  
         [0066]     Furthermore, in the aforementioned embodiments, the switching circuits SW 100 , SW 200 , and SW 300  are each implemented on one semiconductor chip, but the switching circuit, including the transmission circuit  101 , the reception circuit  102 , the standby circuit  103 , and the control circuit  110 , may be implemented on one semiconductor chip.