Abstract:
A non-volatile memory cell fabricated using a conventional logic process. As used herein, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses only one layer of polysilicon. The non-volatile memory cell uses a thin gate oxide (i.e., 1.5 nm to 6 nm) commonly available in a conventional logic process. This non-volatile memory cell can be programmed and erased using relatively low voltages. As a result, the voltages required to program and erase can be provided by transistors readily available in a conventional logic process. The program and erase voltages are precisely controlled to avoid the need for a triple-well process. In one embodiment, the non-volatile memory cells are configured to form a non-volatile memory block that is used in a system-on-a-chip. In this embodiment, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory. The data contents of the non-volatile memory cells are then refreshed (through charge injection and removal) with optimum signal condition. The non-volatile memory cells then remain in an idle or standby mode substantially without a significant external electric field. If a reprogramming operation or a refresh operation is required, then the non-volatile memory cells are reprogrammed or refreshed as required and then returned to the idle or standby mode. As a result, the storage characteristics of the thin oxide non-volatile memory cells are improved.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to non-volatile memory (NVM). More particularly, this invention relates to non-volatile memory cells fabricated using an ASIC or conventional logic process. In the present application, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses a single layer of polysilicon. This invention further relates to a method of operating a non-volatile memory to ensure maximum data retention time.  
         BACKGROUND OF INVENTION  
         [0002]    For system-on-chip (SOC) applications, it is desirable to integrate many functional blocks into a single integrated circuit. The most commonly used blocks include a microprocessor or micro-controller, SRAM blocks, non-volatile memory blocks, and various special function logic blocks. However, traditional non-volatile memory processes, which typically use stacked gate or split-gate memory cells, are not compatible with a conventional logic process. The combination of a non-volatile memory process and a conventional logic process results in much more complicated and expensive “merged non-volatile memory and logic” process to implement system-on-chip integrated circuits. This is undesirable because the typical usage of the non-volatile memory block in an SOC application is comparatively small compared with the overall chip size.  
           [0003]    There are several prior art approaches to minimize the complexity of such a merged non-volatile memory and logic process. For example, U.S. Pat. No. 5,879,990 to Dormans et al. describes a process that requires at least two layers of polysilicon and two sets of transistors to implement both the normal logic transistors and the non-volatile memory transistors. This process is therefore more complex than a conventional logic process, which requires only a single layer of polysilicon.  
           [0004]    U.S. Pat. No. 5,301,150 to Sullivan et al. describes a single poly process to implement a non-volatile memory cell. In this patent, the control gate to floating gate coupling is implemented using an n-well inversion capacitor. The control gate is therefore implemented using the n-well. An injector region must be coupled to the inversion layer in the n-well. The use of an n-well as the control gate and the need for an injector region result in a relatively large cell size.  
           [0005]    U.S. Pat. No. 5,504,706 to D&#39;Arrigo et al. describes a single poly process to implement a non-volatile memory cell that does not use an n-well as a control gate. FIG. 1A is a schematic diagram illustrating an array of non-volatile memory cells C 00 -C 12  as described by D&#39;Arrigo et al. FIG. 1B is a cross sectional view of one of these non-volatile memory cells. As shown in FIG. 1A, each of the memory cells contains a transistor  24  having a source connected to a virtual-ground (VG) line and a drain connected to a bit line (BL). The transistor  24  further has a floating gate  40  which is coupled to a word line (WL)  86  through a coupling capacitor. The coupling capacitor includes n+region  80 , which is located under the floating gate  40  and which is continuous with the diffusion word line  86 . The capacitance of the coupling capacitor is significantly larger than the gate capacitance of the transistor to allow effective gate control of the transistor from the WL voltage levels. The n+ region  80  is formed by an additional implant to ensure good coupling during operations. This additional implant is not available in a standard logic process. The memory cells  24  are located inside a triple-well structure. More specifically, the memory cells are formed in a p-tank  78 , which in turn, is formed in an n-tank  76 , which in turn, is formed in p-well  74 . A p+contact region  88  is located in p-tank  78 , and an n+contact region  90  is located in n-tank  76 . The triple-well structure allows flexibility of biasing in operating the memory cell. More specifically, the triple-well structure allows a large negative voltage (typically −9 Volts) to be applied to the word line  86  (i.e., the control gate). Both the extra n+ implant and the triple-well are not available in a conventional logic process. Similarly, U.S. Pat. No. 5,736,764 to Chang describes a PMOS cell having both a select gate and a control gate, wherein additional implants are required underneath the control gate.  
           [0006]    In addition, the above-described non-volatile memory cells use a relatively thick tunneling oxide (typically 9 nanometers or more). Such a thick tunneling oxide is not compatible with conventional logic processes, because conventional logic processes provide for logic transistors having a gate oxide thickness of about 5 nm for a 0.25 micron process and 3.5 nm for a 0.18 micron process.  
           [0007]    Conventional non-volatile memory cells typically require special high voltage transistors to generate the necessary high voltages (typically 8 Volts to 15 Volts) required to perform program and erase operations of the non-volatile memory cells. These high voltage transistors are not available in a conventional logic process. These high voltage transistors are described, for example, in U.S. Pat. No. 5,723,355 to Chang et al.  
           [0008]    U.S. Pat. No. 5,761,126 to Chi et al. describes a single poly EPROM cell that utilizes band-to-band tunneling in silicon to generate channel hot-electrons to be injected into a floating gate from a control gate. A relatively thin tunnel oxide can be used in this memory cell because of the enhanced electron injection. However, this memory cell only supports programming (i.e., electron injection into the floating gate). No support is provided to remove electrons from the floating gate (i.e., an erase operation is not supported).  
           [0009]    The use of a thin gate oxide as tunneling oxide presents a challenge for achieving acceptable data retention time for non-volatile memory cells. A thin gate oxide is defined herein as a gate oxide layer having a thickness in the range of 1.5 nm to 6.0 nm. Although programming voltages may be reduced by the use of a thin gate oxide, the thin gate oxide will exacerbate cell disturbances. That is, the thin gate oxide will significantly increase the probability of spurious charge injection or removal from the floating gate during normal program, erase and read operations. This is due to the high electric field present in or near the thin gate oxide. As conventional logic processes scale down in geometry, the gate oxide thickness scales down proportionally. For example, a 0.25 micron process uses a 5 nm gate oxide thickness, a 0.18 micron process uses a 3.5 nm gate oxide thickness, and a 0.15 micron process uses a 3 nm gate oxide thickness. As a result, data-retention becomes a serious problem when using the standard gate oxide as the tunnel oxide in a non-volatile memory cell. U.S. Pat. No. 5,511,020 to Hu et al. describes data refreshing techniques to improve data retention time using very thin tunnel oxides.  
           [0010]    It would therefore be desirable to implement a single-poly non-volatile memory cell using a conventional logic process, without requiring process modification and/or additional process steps.  
           [0011]    It would also be desirable to have a method of operating non-volatile memory cells in conjunction with volatile memory arrays in a manner that minimizes disturbances from write, erasing and read operations, thereby improving the data retention time for the non-volatile memory cells.  
         SUMMARY  
         [0012]    Accordingly, the present invention provides a non-volatile memory cell fabricated using a conventional logic process. The non-volatile memory cell uses a thin gate oxide (i.e., 1.5 nm to 6 nm) available in a conventional logic process. The non-volatile memory cell can be programmed and erased using relatively low voltages. The voltages required to program and erase can be provided by transistors readily available in a conventional logic process (i.e., transistors having a breakdown voltages in the range of 3 Volts to 7 Volts).  
           [0013]    In one embodiment, the non-volatile memory cell includes a p-type semiconductor substrate and an n-well located in the substrate. A PMOS transistor is fabricated in the n-well. The PMOS transistor includes the thin gate oxide and an overlying polycrystalline silicon gate. An NMOS capacitor structure is fabricated in the p-type substrate. The NMOS capacitor structure includes an n-type coupling region located in the p-type substrate. The n-type coupling region is formed by the n-type source/drain implants, thereby eliminating the need for any additional implants not normally provided by the conventional logic process. The thin gate oxide and the polycrystalline silicon gate extend over the p-type substrate and the n-type coupling region, thereby forming the NMOS capacitor structure. The NMOS capacitor structure and the PMOS transistor are sized such that the NMOS capacitor structure has a capacitance larger than a capacitance of the PMOS transistor. Advantageously, a triple-well structure is not required by the present invention.  
           [0014]    The present invention incorporates a negative voltage generator that provides a negative boosted voltage having a voltage level that is less than the Vss supply voltage by a voltage that is less than a diode turn-on voltage (0.7 Volts). In one embodiment, the negative boosted voltage has a value of −0.5 Volts. The negative boosted voltage is applied to the control gate of the non-volatile memory cell to enhance the electron removal operation and normal read operation without requiring a triple-well underneath the control gate.  
           [0015]    The present invention also incorporates a positive voltage generator that provides a positive boosted voltage having a voltage level that is greater than the V dd  supply voltage by a voltage that is less than a diode turn-on voltage (0.7 Volts). In one embodiment, the positive boosted voltage has a value equal to V dd +0.5 Volts. The positive boosted voltage is applied to the N-well of the non-volatile memory cell and the control gates of non-selected memory cells during normal read operations to suppress leakage currents through those non-selected memory cells and to improve operating margins.  
           [0016]    In accordance with one embodiment of the present invention, non-volatile memory cells are used in a system-ona-chip system. After power-up of a system-on-a-chip integrated circuit incorporating the embedded non-volatile memory cells, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory. The data contents of the non-volatile memory cells are then refreshed (through charge injection and removal) with optimum signal condition. The non-volatile memory cells then remain in an idle or standby mode substantially without a significant external electric field. If a reprogramming operation or a refresh operation is required, then the non-volatile memory cells are reprogrammed or refreshed as required and then returned to the idle or standby mode. As a result, the storage characteristics of the thin oxide non-volatile memory cells are improved.  
           [0017]    The present invention will be more fully understood in view of the following description and drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    [0018]FIG. 1A is a schematic of a conventional non-volatile memory cell fabricated by a single-poly process;  
         [0019]    [0019]FIG. 1B is a cross-sectional view of the non-volatile memory cell of FIG. 1A;  
         [0020]    [0020]FIG. 2 is a top view of a non-volatile memory cell having a PMOS access transistor and an NMOS coupling gate in accordance with one embodiment of the present invention;  
         [0021]    [0021]FIGS. 3A and 3B are cross-sectional views of the non-volatile memory cell of FIG. 2;  
         [0022]    [0022]FIG. 4 is a schematic diagram of an array of the non-volatile memory cells of FIG. 2;  
         [0023]    [0023]FIG. 5 is a table illustrating the operating modes of the array of FIG. 4 in accordance with one embodiment of the present invention;  
         [0024]    [0024]FIG. 6 is a block diagram illustrating a system-on-a-chip in accordance with one embodiment of the present invention; and  
         [0025]    [0025]FIG. 7 is a flow diagram illustrating the operation of the system-on-a-chip of FIG. 6 in accordance with one embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0026]    [0026]FIG. 2 is a top layout view of a non-volatile memory cell  200  in accordance with one embodiment of the present invention. FIG. 3A is a cross sectional view of the non-volatile memory cell of FIG. 2 along section line A-A. FIG. 3B is a cross sectional view of the non-volatile memory cell of FIG. 2 along section line B-B. In the described example, non-volatile memory cell  200  is fabricated using a 0.25 micron conventional logic process having a typical gate oxide thickness of about 5 nm. Non-volatile memory cell  200  is operated in response to a positive V dd  supply voltage that has a nominal voltage of 2.5 Volts during normal operations, and a V SS  supply voltage of 0 Volts.  
         [0027]    Non-volatile memory cell  200  is fabricated in a p-type monocrystalline semiconductor substrate  201 . In the described embodiment, substrate  201  is silicon. Non-volatile memory cell  200  includes a PMOS access transistor  210 . Access transistor  210  includes p-type source region  211  and p-type drain region  212 , which are formed in n-well  202 . Source region  211  includes lightly doped source  211 A and p+ source contact region  211 B. Drain region  212  includes lightly doped drain  212 A and p+ drain contact region  212 B. An n-type channel region  213  is located between source region  211  and drain region  212 . Channel region  213  has a width of about 0.24 microns. Source region  211  is connected to a virtual-ground (VG) line and drain region  212  is connected to a bit line (BL). Field oxide  214  is located around the source, drain and channel regions as illustrated. Field oxide  214  is planarized, such that the upper surface of field oxide  214  and the upper surface of substrate  201  are located in the same plane. A thin gate oxide layer  215 , having a thickness of about 5 nm, is located over the channel region  213 . Gate oxide layer  215  has the same thickness as the gate oxide layers used in the logic transistors (not shown) fabricated in substrate  201 . A conductively doped polycrystalline silicon floating gate  216  is located over thin gate oxide  215 . Sidewall spacers  205 - 206  and  217 - 218 , which are typically formed from silicon nitride or silicon oxide, are located at the edges of floating gate  216 .  
         [0028]    Floating gate  216  and thin gate oxide  215  extend laterally beyond access transistor  210  over p-type substrate  201  and n-type coupling region  221 . N-type coupling region  221  is coupled to n+ word line  222 . N-type regions  221 - 222 , gate oxide  215  and floating gate  216  form an NMOS capacitor structure  220 . NMOS capacitor structure  220  couples word line  222  to floating gate  216 . N-type coupling region  221  is self-aligned with the edge of floating gate  216 . This self-alignment is accomplished by implanting an n-type impurity using the edge of floating gate  216  as a mask, and then diffusing the impurity under the floating gate using an anneal step. N-type coupling region  221  is formed at the same time as the source and drain regions of NMOS logic transistors (not shown). Thus, no additional step is required to form n-type coupling region  221 .  
         [0029]    Similarly, n+ word line  222  is self-aligned with the edge of sidewall spacer  218 . This self-alignment is accomplished by implanting an n-type impurity using the edge of sidewall spacer  218  as a mask, and then diffusing the impurity under the sidewall spacer using an anneal step. N+ word line  222  is formed at the same time as the n+ contact regions of NMOS logic transistors (not shown). Thus, no additional step is required to form n+word line  222 .  
         [0030]    The total coupling capacitance of NMOS capacitor structure  220  is preferably significantly larger than the gate capacitance of the PMOS access transistor  210 . In one embodiment, the coupling capacitance of NMOS capacitor structure  220  is about four times larger than the gate capacitance of PMOS access transistor  210 . Non-volatile memory cell  200  can be fabricated using a conventional logic process, without any process modifications or special implants.  
         [0031]    [0031]FIG. 4 is a schematic diagram of a 2×2 array of non-volatile memory cells  200 ,  300 ,  400  and  500 . Non-volatile memory cells  300 ,  400  and  500  are identical to above-described non-volatile memory cell  200 . Thus, non-volatile memory cells  300 ,  400  and  500  include PMOS access transistors  310 ,  410  and  510 , respectively, and NMOS capacitor structures  320 ,  420  and  520 , respectively. The sources of PMOS access transistors  210  and  410  are commonly connected to a first virtual ground line VG 0 . Similarly, the sources of access transistors  310  and  510  are commonly connected to a second virtual ground line VG 1 . The drains of PMOS access transistors  210  and  410  are commonly connected to a first bit line BL 0 . Similarly, the drains of PMOS access transistors  210  and  410  are commonly connected to a second bit line BL 1 . NMOS capacitor structures  220  and  320  are commonly connected to a first word line WL 0 . Similarly, NMOS capacitor structures  420  and  520  are commonly connected to a second word line WL 1 . Although the described array has two rows and two columns, it is understood that arrays having other sizes can be implemented by one of ordinary skill in the art.  
         [0032]    [0032]FIG. 5 is a table that defines the operation of the array of FIG. 4 in accordance with one embodiment of the present invention.  
         [0033]    The programming mode is described in connection with the programming of non-volatile memory cell  200 . In the programming mode, electrons are selectively removed from the floating gate of the cell to be programmed. As a result, the PMOS threshold voltage (V tp ) of the programmed cell is more negative and therefore turned off during normal read operations. The programming mode is implemented by a direct tunneling (i.e., Fowler-Nordheim tunneling) mechanism through the gate oxide of the PMOS access transistor.  
         [0034]    Non-volatile memory cell  200  is programmed as follows. Word line WL 0  is held at a voltage of 0 Volts, while bit line BL 0  and virtual ground line VG 0  are each held at a voltage of 6.5 Volts. In another embodiment, either bit line BL 0  or virtual ground line VG 0  is held at a voltage of 6.5 Volts, while the other line is left floating. N-well  202  is held at a voltage of 6.5 Volts, and p-type substrate  201  is held at a voltage of 0 Volts, thereby preventing the n-well/p-substrate junction from being forward biased. Under these bias conditions, an inversion layer is formed in the channel region of NMOS capacitor structure  220 , and the floating gate  216  is coupled to a voltage slightly greater than 0 Volts. As a result, a high voltage drop exists across the gate oxide  215  of PMOS access transistor  210 . An inversion layer is therefore formed in channel region  213  of PMOS access transistor  210 , with the electric field exceeding 10 MV/cm. Under these conditions, electrons in floating gate  216  tunnel out to the high voltage PMOS inversion layer.  
         [0035]    In the present example, non-volatile memory-cell  300  is selected by the 0 Volt signal applied to word line WL 0 . However, it is not desired to program non-volatile memory cell  300 . To prevent electron removal from the floating gate of non-volatile memory cell  300 , bit line BL 1  and virtual ground line VG 1  are each held at a voltage of 3.0 Volts. In another embodiment, either bit line BL 1  or virtual ground line VG 1  is held at a voltage of 3.0 Volts, and the other line is left floating. Under these conditions, the voltage drop across the gate oxide of PMOS access transistor  310  is substantially less than the voltage required for direct tunneling.  
         [0036]    In the present programming example, a voltage of 3.0 Volts is applied to word line WL 1 . As a result, non-volatile memory cells  400  and  500  are not selected for programming. Given the above-describe voltages on bit lines BL 0 -BL 1  and virtual ground lines VG 0 -VG 1 , the 3.0 Volt signal applied to word line WL 1  ensures that the voltages across the gate oxide layers of PMOS access transistors  410  and  510  are substantially below the voltage required for direct tunneling. More specifically, because bit lines BL 0 -BL 1  and virtual ground lines VG 0 -VG 1  will be at either 6.5 Volts, 3.0 Volts or floating, the maximum disturb voltage will be 6.5 Volts minus 3.0 Volts, or 3.5 Volts. This maximum disturb voltage is therefore much less than the program voltage of 6.5 Volts.  
         [0037]    In the described embodiment, the 3.0 Volt signal is generated by a positive voltage generator. This positive voltage generator provides the 3.0 Volt signal, which is greater than the 2.5 Volt positive supply voltage by 0.5 Volts. The 3.0 Volt signal is therefore greater than the 2.5 Volt signal by a magnitude less than a diode voltage drop of 0.7 Volts. A positive voltage generator capable of generating a positive boosted voltage which is greater than the positive supply voltage by a magnitude less than a diode voltage drop is described in U.S. patent application Ser. No. 09/332,757 [Docket No. MST-007-1P], which is hereby incorporated by reference. This positive voltage generator is fabricated using elements that are compatible with a conventional logic process. Use of the 3.0 Volt signal advantageously improves the operating margin of memory cells  200 ,  300 ,  400  and  500 .  
         [0038]    In the erase mode, electrons are injected into the floating gates of memory cells  200 ,  300 ,  400  and  500 , thereby making the threshold voltage (Vtp) of PMOS access transistors  210 ,  310 ,  410  and  510  more positive. As a result of the more positive threshold voltages, the erased PMOS access transistors are turned on during normal read operations. The erase operation implements band-to-band tunneling channel hot-electron (CHE) injection into the floating gates through Fowler-Nordheim tunneling mechanism of the PMOS access transistors. The erase operation is preferably performed in a sector mode, in which all memory cells sharing word lines and bit lines are erased together.  
         [0039]    In the erase mode, word lines WL 0  and WL 1  are held at 0 Volts, and bit lines BL 0 -BL 1  and virtual ground lines VG 0 -VG 1  are held at −6.5 Volts. In another embodiment, either bit lines BL 0 -BL 1  or virtual ground lines VG 0 -VG 1  are held at −6.5 Volts, and the other lines are left floating. P-type substrate  201  and N-well  202  are both held at 0 Volts. Under these bias conditions, the floating gates of memory cells  200 ,  300 ,  400  and  500  are coupled to a voltage slightly less than 0 Volts. As a result, NMOS structures  220 ,  320 ,  420  and  520  and PMOS access transistors  210 ,  310 ,  410  and  510  are placed in an accumulation mode. A relatively high voltage drop exists across the p-type source/drain regions of the PMOS access transistors and the n-well  202 . A relatively high voltage drop also exists between the floating gates and the p-type source/drain regions of the PMOS access transistors. The high electrical field conditions cause band-to-band tunneling to occur near the edges of the p-type source/drain regions, and the resulting channel hot-electrons (CHE) are accelerated and injected into the floating gates.  
         [0040]    To read non-volatile memory cells  200  and  300 , word line WL 0  is held at 0 Volts, virtual ground lines VG 0 -VG 1  are held at 2.5 Volts (or some lower voltage level to suppress leakage current), n-well  202  is held at 3.0 Volts, and p-type substrate  201  is held at 0 Volts. Bit lines BL 0 -BL 1  are pre-charged to 0 Volts (or some other voltage lower than virtual ground lines VG 0 -VG 1 ). Under these conditions, read current will flow through the access transistors of non-programmed (erased) cells, while read current will be less through the access transistors of programmed cells.  
         [0041]    The word line WL 1  associated with the non-selected cells is held at 3.0 Volts in the normal read mode, thereby turning off access transistors  410  and  510 . Turning off access transistors  410  and  510  prevents current from flowing through these transistors into bit lines BL 0  and BL 1 . As a result, cells  400  and  500  do not interfere with the bit line signals from the selected cells  200  and  300 .  
         [0042]    During the read operation, n-well  201  is biased at a voltage that is 0.5 Volts greater than the virtual ground lines VG 0 -VG 1 . This n-well biasing is referred to as “n-well back bias”. In a conventional logic process having a minimum feature size of 0.24 microns, the typical threshold voltage of a p-channel transistor (Vtp) is equal to −0.5 Volts. The n-well back bias raises the magnitude of the p-channel threshold voltage (to a voltage that is more negative). As a result, the sub-threshold leakage current is reduced in nonselected cells (e.g., cells  400  and  500 ) and selected cells that are programmed to be “off” (i.e., non-conductive during a read operation).  
         [0043]    Similarly, the non-selected word line WL 1  is biased at 3.0 Volts, which is 0.5 Volts greater than the virtual ground lines VG 0 -VG 1 . This “gate reverse-bias” is also important to further reduce the sub-threshold leakage currents in the non-selected cells.  
         [0044]    In an alternate embodiment of the present invention, the bias condition of a cell being programmed (e.g., cell  200  in the above-described example) can be modified to have a word line voltage of −0.5 Volts (instead of 0 Volts). This reduced word line voltage prevents turn on of the junction between word line  222  and p-type substrate  201 . The −0.5 Volt word line bias, which is smaller in magnitude than a diode turn-on voltage, increases the maximum voltage across the gate oxide layer  215  without requiring higher voltage transistors to be used in negative voltage generator. The negative voltage generator used to generate a word line bias voltage of −0.5 Volts is described in U.S. patent application Ser. No. 09/332,757 [MST-007-1P].  
         [0045]    In this embodiment, the bias condition of a cell that is not being programmed, but is in the same row as a cell being programmed (e.g., cell  300  in the above-described example) will also have a word line voltage of −0.5 Volts. To compensate for this lower word line voltage, the bit line and virtual ground line of the non-selected cell are reduced by 0.5 Volts, from 3.0 Volts to 2.5 Volts.  
         [0046]    In this embodiment, the word lines of rows that do not have any cells being programmed are coupled to receive a word line bias voltage of 2.5 Volts. The associated bit lines and virtual ground lines are biased at either 2.5 Volts or 6.5 Volts, depending on whether the cells are in the same column as a cell being programmed. Note that the biasing of n-well  202  and p-type substrate  201  remain at 6.5 Volts and 0 Volts, respectively, in this embodiment.  
         [0047]    For a conventional logic process having a minimum line size at or below 0.24 microns, the use of very thin gate oxides as tunneling oxide present major challenges for achieving acceptable data retention time for non-volatile memory cells. Although programming voltages may be reduced, the disturbance problem (i.e., spurious injection or removal of charges from the floating gate) during normal program, erase and read operations increases significantly due to the high electric field present in or near the thin tunnel oxide and the resultant tunneling leakage current and channel hot-electron injection leakage currents. As conventional logic processes scale down in geometry, the standard gate oxides also get scaled down proportionally (e.g., 5 nm and 7 nm for a 0.25 micron process, 3.5 nm, 5 nm and 7 nm for a 0.18 micron process, and 3 nm, 5 nm and 7 nm for a 0.15 micron process). As a result, data-retention becomes a serious problem when using the standard gate oxide as the tunnel oxide for the non-volatile memory cell. U.S. Pat. No. 5,511,020, which is hereby incorporated by reference in its entirety, describes data refreshing techniques to improve data retention time of non-volatile memory cells using very thin tunnel oxides. The data refreshing techniques of U.S. Pat. No. 5,511,020 can be applied, as necessary, to the non-volatile memory cells of the present invention. Note that such data refreshing techniques are optional, and are not required in order to practice the present invention.  
         [0048]    Since both the tunneling current and the channel hot-electron injection current are highly dependent on the level of electric field present in or near the non-volatile memory cells, a method for operating non-volatile memory cells to minimize the frequency and duration of high electric field operations is described in a preferred embodiment of the present invention, thereby maximizing data retention time for non-volatile memory cells using very thin tunneling oxides.  
         [0049]    [0049]FIG. 6 is a block diagram of a system-on-a-chip integrated circuit  600  in accordance with one embodiment of the present invention. Integrated circuit chip  600  includes processor or controller unit  601 , various functional blocks  602 , non-volatile memory block  603  and on-chip volatile memory block  604 . In another embodiment, on-chip volatile memory block  604  can be replaced with off-chip volatile memory chips  605 . In one embodiment, functional blocks  602  include at least one programmable logic block that uses volatile memory elements as control and configuration bits. At least a portion of these control and configuration bits are stored in non-volatile memory block  603 . During initialization, these control and configuration bits are loaded into volatile memory block  604 , thereby enabling normal operations within functional blocks  602 . To reduce the disturbances originated from the program, erase and read modes, the non-volatile memory cells in on-chip non-volatile memory block  605  are operated in accordance with the flow chart  700  provided in FIG. 7.  
         [0050]    As illustrated in FIG. 7, the system-on-a-chip integrated circuit  600  is powered-up and/or initialized during Step  701 . The contents of non-volatile memory array  603  are then read during Step  702 . In one embodiment, the read operation performed during Step  702  includes adaptive algorithms that sample the data content of a selected cell or cells in non-volatile memory array  603  to determine the actual threshold voltage levels for the programmed and non-programmed non-volatile memory cells. The optimum voltages for reading out the contents of the non-volatile memory cells are then selected in view of the actual threshold voltage levels. For example, if the actual threshold voltage levels are relatively low, then a lower read voltage is used. The data content stored in non-volatile memory array  603  may be compressed to reduce the capacity requirement of the non-volatile memory array  603  on chip  600 . Data integrity may be further enhanced by utilizing error detection and correction (ECC) techniques during the read operation.  
         [0051]    During Step  703 , the contents read from non-volatile memory block  603  are stored in volatile memory block  604  (or optionally in off-chip volatile memory chips  605 ). The non-volatile memory block  603  is then controlled to enter the program and erase modes (Step  704 ). Program and erase operations are then performed to non-volatile memory block  603 , such that the original contents of non-volatile memory block  603  are restored/reconditioned from volatile memory block  604  (or volatile memory chips  605 ) (Step  705 ). Non-volatile memory block  603  then enters the standby mode (Step  706 ). During the standby mode, minimal or no external biases applied are applied to the non-volatile memory cells in non-volatile memory block  603 . Preferably, the entire non-volatile memory block  603  is powered down to 0 Volts to prevent power supply glitches or abrupt power outages from causing disturbances to the non-volatile memory cells.  
         [0052]    As long as no interrupt is received, non-volatile memory block  603  remains in the standby mode (Step  707 ). However, if an interrupt is received, then this interrupt is processed (Step  707 ). If the interrupt indicates a power down sequence, then the chip  600  is powered down (Steps  707  and  708 ). If the interrupt indicates a new program request (Step  708 ), then processing returns to Step  704 .  
         [0053]    As described above, refresh operations may be required in view of the thin gate oxide used in the non-volatile memory cells. Refresh of the non-volatile memory cells may be required a few times a day, once every few days or once every few weeks, depending on the particular characteristics of the cells in non-volatile memory block  603 . A refresh management system, such as the one described in U.S. Pat. No. 5,511,020, is used to control the refresh operations.  
         [0054]    The Restore/Recondition operation of Steps  704 - 705  can be conditional based on whether a preset criterion for charge loss is met. In this case, optional Steps  710  and  711  are added as illustrated. Step  711  is added between Steps  703  and  704 . In Step  711 , it is determined whether a refresh operation is required in non-volatile memory block  603 . If no refresh is required, then Steps  704  and  705  are bypassed (i.e., non-volatile memory block  603  is not refreshed), and processing proceeds to the standby mode in Step  706 . If a refresh operation is required, the processing proceeds to Steps  704 - 705 , where a refresh operation is performed.  
         [0055]    Step  710  is an additional interrupt that indicates that non-volatile memory  603  must be refreshed. This interrupt is processed by returning processing to Step  704 , thereby refreshing non-volatile memory  603 . Because Steps  710  and  711  are optional steps, these steps are shown in dashed lines in FIG. 7.  
         [0056]    Using the above-described steps, the disturbances from program, erase and read modes can be precisely managed and predicted to achieve maximum data-retention time and data integrity in non-volatile memory block  603 . It is noted that the system operating method of the preferred embodiment described above is applicable to conventional non-volatile memory cells including stacked-gate cells, split-gate cells, nitride-oxide (MNOS or SNOS) cells, oxidized-nitride-oxide (MONOS or SONOS) cells and their variations.  
         [0057]    Even in the standby mode or during storage conditions (i.e., when zero or no (floating) electrical biases are applied to the non-volatile memory cells) there are internal electric fields present in the non-volatile memory cells that can cause charge loss and data retention problems. To optimize data retention time during these conditions, the internal electric fields must be minimized as well. This is accomplished in the present invention by setting the threshold voltages (Vtp) for both the programmed and erased charge states to be balanced against the internal potential levels of the silicon substrate  201  and polysilicon gate electrodes, taking into consideration the flat-band voltage levels for both the NMOS capacitor structure and the PMOS access transistor in the non-volatile memory cell. In one embodiment of the present invention, the threshold voltages of the PMOS access transistors are set equal to −0.5 Volts when the non-volatile memory cell is erased, and −1.0 Volt when the non-volatile memory cell is programmed. The difference between these threshold voltages is 0.5 Volts. Similarly, the threshold voltages of the NMOS capacitor structures are set to be equal to 0.5 Volts when the non-volatile memory cell is erased, and 0 Volts when the non-volatile memory cell is programmed. Again, the difference between these threshold voltages is 0.5 Volts.  
         [0058]    Although the present invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. Thus, the invention is limited only by the following claims.