Abstract:
An improved operational amplifier generates an output signal which varies according to plural input signals. An input stage accepts the input signals and outputs an intermediate signal according to the input signals, and generates an internal control signal in place of an external control signal. A current source provides a current according to the internally provided control signal. A conversion stage generates an output signal as a function of the intermediate signal and the current. An output driver stage drives the output signal to a load and buffers the operational amplifier from the load. A precision voltage reference generator based upon the operational amplifier provides a stable voltage reference signal. The output driver provides an internal feedback signal to the input stage, in place of the external input signals, and a bandgap reference cell in the first state establishes a voltage for the output driver in place of an external bias signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an improved apparatus for converting plural input signals into an output signal. More particularly, it relates to an operational amplifier having an internally generated bias for stabilizing a current source, and a precision voltage reference generator using said op-amp. 
     2. Description of the Related Art 
     Operational amplifiers, or op-amps, are used to amplify a difference between two input signals, in order to generate an output signal. Typically, an op-amp consists of an input stage which converts the input signals into an intermediate signal whose current varies as the voltage difference between the two inputs changes. The varying-current intermediate signal is then converted into a varying-voltage signal via a conversion stage. An output driver generates the output signal as a function of the converted signal. 
     The industry standard &#34;741&#34; op-amp is typical of the prior art. See, Gray and Meyer, Analysis and Design of Analog Integrated Circuits. 2d ed., John Wiley &amp; Sons, 1984, at p. 364. 
     The input stage typically includes a differential pair of input transistors having bases connected to receive the two input signals. The input transistors, collectors are connected to respective legs of a current mirror. One of the input transistors also supplies an &#34;intermediate&#34; signal, as a current, reflecting the voltage difference between the input signals. 
     The current mirror includes a matched pair of transistors, whose base leads are tied together and to the emitter of a mirror buffer transistor. The collector current which is drawn by the mirror buffer transistor is wasted, as it just runs to the supply terminal. 
     A conversion stage converts the intermediate signal from a current to a voltage. In one typical embodiment, the conversion stage consists of a transistor having its base connected to receive the &#34;intermediate&#34; signal and its collector coupled to a constant current source, and to the base of a buffer transistor. The emitter of the buffer transistor is coupled to generate the converted signal in response to the intermediate signal and a current signal received from the current source. The current source is stabilized by an external bias signal or other special biasing circuit associated with the current source. 
     Op-amps are used in &#34;band-gap&#34; voltage reference generators such as that shown in A. Brokaw, &#34;A Simple Three-Terminal IC Bandgap Reference&#34;, IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 6, December 1974, at p. 388. 
     It is desirable to have a more efficient op-amp which minimizes current consumption and heat generation, and requires a minimum number of external bias signals. It is also desirable to have a voltage reference generator, which requires no external bias signals. 
     SUMMARY OF THE INVENTION 
     The present invention provides an improved op-amp, with an input stage for accepting plural input signals and outputting an intermediate signal, a current source for providing a current, a conversion stage for generating an output signal as a function of the intermediate signal and the current, and an output driver stage for driving the output signal to a load and buffering the op-amp from the load. The present op-amp internally provides a control signal to the current source, reducing the op-amp&#39;s requirements for externally provided bias signals. 
     According to one aspect of the invention, a current mirror in the input stage establishes a stable junction at which the emitter of a mirror buffer transistor is connected. Current through the collector of the mirror buffer transistor is therefore stable. This current through the mirror buffer is used as the internally generated control signal, and therefore is not wasted by simply being shunted to a supply terminal. 
     In another aspect of the invention, the op-amp is used as the basis for a precision voltage reference generator with no external bias signals. A bandgap reference cell in the input stage establishes a temperature compensated reference which drives the output stage. 
     Other aspects and advantages of the present invention can be seen upon review of the drawings, detailed description, and the claims which follow. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts a simplified diagram of an op-amp embodiment of the present invention, showing signal passage between elements. 
     FIG. 2 is a circuit diagram of an op-amp according to the present invention. 
     FIG. 3 depicts a simplified diagram of a precision voltage reference generator embodiment of the present invention, showing signal passage between elements. 
     FIG. 4 is a circuit diagram of a voltage reference generator according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a simplified diagram of the op-amp 100 of the present invention. The op-amp 100 is powered by first and second power signals 11 and 12. The op-amp 100 accepts first and second input signals 13 and 14 from external signal sources INVERTING INPUT and NONINVERTING INPUT, and gives output signal 58 indicating the difference between the input signals 13 and 14. First and second input signals 13 and 14 arrive at input stage 16 of the op-amp 100, along with bias signal 17. Input stage 16 translates the differential input signals 13 and 14 into a single intermediate signal 18, and supplies the intermediate signal 18 to conversion stage 19. Also, input stage 16 supplies a stable bias control signal 20 to current source 21. 
     Current source 21 supplies a constant current 22 to conversion stage 19 in response to the control signal 20. Conversion stage 19 converts the intermediate signal 18 into converted signal 15, which is sent to output driver 51. Output driver 51 drives final output signal 58 in response to converted signal 15. By internally providing control signal 20 from a stable node in the input stage 16, the op-amp 100 eliminates the need for one additional external bias signal driving the current source 21. 
     FIG. 2 is a circuit schematic of an op-amp 100 according to the present invention. First power signal 11 arrives from external power source VPOS, and second power signal 12 arrives from external power source VNEG. 
     The input stage 16 includes a first current mirror 23 and a differential pair of input transistors 32 and 33. First current mirror 23 has first and second resistors 24 and 25 coupled to power source VPOS. Current mirror 23 has a first p-n-p transistor 26, whose emitter is coupled to first resistor 24, and a second p-n-p transistor 27 whose emitter is coupled to second resistor 25. The bases of first and second transistors 26 and 27 are coupled together. First current mirror 23 also has resistor 28 coupled to power source VPOS, and to the emitter of diode connected transistor 29. The collector and base of transistor 29 are coupled to the junction of the bases of transistors 26 and 27. Also coupled to that junction is the emitter of mirror buffer transistor 30. The base of mirror buffer transistor 30 is coupled to the collector of first transistor 26, and the collector of mirror buffer transistor 30 is coupled to control signal line 31. A capacitor 37 is coupled between the collectors of transistors 26 and 30. 
     The base of first input transistor 32 (n-p-n) is coupled to the external signal source INVERTING INPUT to receive first input signal 13. The base of second input transistor 33 (n-p-n) is coupled to external signal source NONINVERTING INPUT, to receive second input signal 14. 
     The collector of first input transistor 32 is coupled to the collector of first transistor 26 of the current mirror 23 and to the base of mirror buffer transistor 30. The collector of second input transistor 33 (n-p-n) is coupled to the collector of second transistor 27 of the current mirror 23. Coupled to the collectors of input transistor 33 and mirror transistor 27 is intermediate signal line 34. 
     The emitters of first and second input transistors 32 and 33 are coupled together, and to the collector of current source transistor 35. The base of transistor 35 is coupled to external signal source VBIAS, to receive external bias signal 17. The emitter of transistor 35 is coupled through resistor 36 to external power source VNEG. 
     The current source 21 comprises a current mirror circuit including (n-p-n) mirror transistors 39 and 40 and (n-p-n) buffer transistor 38. Control signal line 31 is coupled to the base of buffer transistor 38 of current source 21. The collector of buffer transistor 38 is coupled to external power source VPOS. The bases of mirror transistors 39 and 40 are coupled together and to the emitter of buffer transistor 38. 
     Diode connected transistor 43 is coupled between the junction of the bases of transistors 39 and 40, and resistor 44. The collector of transistor 39 is coupled to the control line 31, and the emitter of transistor 39 is coupled to resistor 41. The emitter of transistor 40 is coupled to resistor 42. Resistors 41, 42 and 44 are all coupled to external power source VNEG. The collector of transistor 40 is coupled through capacitor 45 back to the collectors of transistors 32 and 26 of the input stage 16. 
     The collector of transistor 40 mirrors the current 20 that flows in the control signal line 31 and through transistor 39, and supplies the constant current 79 to current signal line 46, which is connected to conversion stage 19. 
     Conversion stage 9 has (p-n-p) converter transistor 47 whose base is coupled to intermediate signal line 34, and whose collector is coupled to current signal line 46. The emitter of converter transistor 47 is coupled to both the collector and the base of transistor 48, and the emitter of transistor 48 is coupled to resistor 49. Resistor 49 is then coupled to external power source VPOS. 
     A signal line 50 is coupled to the collector of transistor 47, and to output driver 51. Output driver 51 consists of emitter follower transistor 52, whose base is coupled to signal line 50, and whose collector is coupled to external power source VPOS. The emitter of transistor 52 is coupled through capacitor 53 to the base of transistor 47 of the conversion stage 19. The emitter of transistor 52 is also coupled to the collector of current source transistor 54. The base of transistor 54 is coupled to the external bias source VBIAS. The emitter of transistor 54 is coupled to resistor 55 which is then coupled to external power source VNEG. Coupled to the emitter of emitter follower transistor 52 is output signal line 56, which is then coupled to the external terminal OUTPUT. 
     In operation, first and second input signals 13 and 14 arrive from the external signal sources INVERTING INPUT and NONINVERTING INPUT, to the bases of first and second input transistors 32 and 33, respectively. If first and second input signals 13 and 14 are equal, the current 74 flowing through input stage 16 will be equally divided along the first and second current paths. Each input transistor 32 and 33 will then be conducting half of the current 74 which flows through transistor 35. However, as input signals 13 and 14 vary with respect to each other, the first and second input transistors 32 and 33 will draw unequal amounts of current 77 and 78 along their respective current paths. 
     If first input signal 13 is stronger than second input signal 14, first input transistor 32 will draw a first draw current 77 greater than the second draw current 78 which will be drawn by second input transistor 33. However, the current mirror 23 forces equal currents 75 and 76 along the respective current paths. Because the collector of mirror transistor 26 is directly coupled to the collector of input transistor 32 with no direct alternate current path, first draw current 77 through input transistor 32 will be equivalent to current 75 through mirror transistor 26, less the base current of mirror buffer transistor 30. Therefore, any discrepancy between the currents in the input transistors 32 and 33 will show up on intermediate signal line 34 as intermediate signal 18. 
     Current mirror 23 establishes a stable voltage at the junction between the bases of transistors 26 and 27. Mirror buffer transistor 30, having its emitter coupled to that junction and therefore subject to that constant voltage, will supply a constant current 20 at its collector. In the present invention, that current 20 is also used as control signal 20, which is sent to current source 21. 
     Current source 21 consists essentially of another current mirror. That current mirror 21 has transistor 38, which is kept in a very steady state by the constant control signal 20 arriving at its base. The flows down the current path of transistor 39 and resistor 41 to external power source VNEG. Because transistors 39 and 40 are coupled at their bases and have equivalent emitter circuits, transistor 40 will always draw a current 79 at its collector, equivalent to the current 20 which is flowing into the collector of transistor 39 from control line 31. This current 79 constitutes current signal 22. The voltage of converted signal 15 on signal line 50 varies in response to the intermediate signal 18 about a center level set by the current signal 22. 
     FIG. 3 shows a precision voltage reference generator 101 based upon the op-amp of the present invention. The voltage reference 101 has input stage 16, conversion stage 19, current source 21, output driver 51, and startup circuit 57, which are all powered by first and second power signals 11 and 12. The input stage 16 generates a temperature-independent intermediate signal 18 and supplies it to conversion stage 19. Also, the input stage 16 generates a stable bias control signal 20 and supplies it to current source 21. The conversion stage 19 converts the intermediate signal 18 into a converted signal 15. 
     Current source 21 generates current signal 22 and supplies it to conversion stage 19. Conversion stage 19 sends converted signal 15 to output driver 51. Output driver 51 then generates voltage reference signal 82 on reference line 56 and provides feedback signal 59 to the input stage 16. Reference signal 82 is then available at reference node VREF. The voltage reference 101 does not rely on any input bias signals. 
     FIG. 4 is a circuit schematic of a precision voltage reference generator 101 based upon the present invention. The current source 21 and conversion stage 19 are the same as in FIG. 2. The input stage 16 is modified to be coupled to only two external power sources TAPSHLD and VEE2. 
     The first and second input transistors 32 and 33, the current source transistor 35, and resistor 36 of FIG. 2 are replaced with bandgap reference cell 83. Bandgap reference cell 83 has first and second bandgap transistors 84 and 85, with second bandgap transistor 85 having an emitter area eight times that of first bandgap transistor 84. The emitter of second bandgap transistor 85 is coupled to resistor 86. The emitter of first bandgap transistor 84 is coupled to the other side of resistor 86, and to resistor 87. Resistor 87 is then coupled to external VEE2. The bases of first and second bandgap transistors 84 and 85 are coupled together and to feedback signal line 63. Feedback signal line 63 is then coupled to output driver 51. 
     In output driver 51, current source transistor 54 and resistor 55 of FIG. 2 have been replaced with resistors 64 and 73. Resistor 64 is coupled between the emitter of transistor 52 and the feedback signal line 63. Resistor 73 is coupled to feedback signal line 63, and to external power source VEE2. 
     Voltage reference 101 further includes startup circuit 57, which is powered by external power sources TAPSHLD and VEE2. A transistor 65 has its base and collector coupled to external power source TAPSHLD, and its emitter coupled to the base and collector of transistor 66. The emitter of transistor 66 is coupled to resistor 67, which is then coupled to the base of transistor 68 and to the collector and base of transistor 69. The emitter of transistor 68 is connected to signal line 50 and to the base of the emitter follower transistor 52. The emitter of transistor 69 is connected to resistor 70, which is then connected to the collector and base of transistor 71. The emitter of transistor 71 is then coupled to external power source VEE2. 
     The voltage reference generator 101 has two stable states, first where no current flows through the circuit, and second where current flows and the reference signal 82 is generated. Upon startup, the startup circuit 57 sends startup signal 60 to the output driver 51, by pulling the base of emitter follower transistor 52 up. The rise at the base of emitter follower transistor 52 powers the output driver 51 to supply an initial signal across feedback line 63 to the input stage 16. This shifts the voltage reference generator 101 to the second, powered state. When in operation, the converted signal 15 will cause the base of emitter follower transistor 52 to rise above the base of transistor 68 to turn off transistor 68 and eliminate any further effect of the startup circuit 57 upon voltage reference 101. 
     In the precision voltage reference generator embodiment 101 of the present invention, the operation of the current source 21 and conversion stage 19 is identical to that described above. The operation of the current mirror 23 of the input stage 16 is likewise identical. The bandgap reference cell 83 establishes a feedback voltage at feedback signal line 63. 
     The present invention has been shown and described as being based on bipolar transistor technology. It will be understood by those skilled in the art that equivalent circuits may be built using CMOS transistor technology, or by substituting n-p-n transistors for p-n-p transistors and vice versa. While the present invention has been shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that these and various other changes in form and detail may be made therein without departing from the scope and spirit of the invention itself.