Abstract:
An input-output (I/O) receiver includes a receiving terminal, a first N-type metal-oxide-semiconductor (NMOS) transistor, a reformation circuit, and a compensation unit. The receiving terminal is coupled with an external voltage signal. The first NMOS transistor has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage. The reformation circuit is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. Moreover, the compensation unit is configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application claims the priority of Chinese Patent Application No. CN201610134366.7, filed on Mar. 9, 2016, the entire content of which is incorporated herein by reference. 
       FIELD OF THE DISCLOSURE 
       [0002]    The present disclosure generally relates to the field of semiconductor integrated circuits (ICs) and, more particularly, relates to input-output receivers and operation mechanism thereof. 
       BACKGROUND 
       [0003]    An input-output (1/O) receiver is an interface circuit for internal and external signal exchange of an IC chip. The main function of an I/O receiver is to receive digital/analog signals. In some applications, the external voltage may be higher than the internal power supply voltage of the chip. Therefore, a voltage resistant circuit is commonly designed in an I/O receiver in order to protect the I/O receiver. 
         [0004]      FIG. 1  shows a schematic view of an existing I/O receiver. Referring to  FIG. 1 , the receiving terminal receives signals from Port PAD. The voltage level Vin at Port PAD is higher than the power supply voltage VDD 1  of the receiver. When the signal at Port PAD is directly transmitted to Node B, a high voltage level may cause reliability issues of NMOS transistors M 29  and M 30 . Therefore, the I/O receiver further includes an NMOS transistor M 31  to reduce the maximum level of the voltage signal at Node B. 
         [0005]    As shown in  FIG. 1 , the source electrode of the NMOS transistor M 31  is coupled with Port PAD, while the gate electrode of the NMOS transistor M 31  is coupled with the power supply voltage VDD 1 . Thus, the voltage level at Node B is controlled in a range between 0 and a value of (VDD 1 −Vthn), where Vthn is the threshold voltage of NMOS transistor M 31 . Therefore, introducing the NMOS transistor M 31  into the I/O receiver may provide protection for the NMOS transistor M 29  and the NMOS transistor M 30 . Further, the gate electrode of the PMOS transistor M 27  is connected to Port PAD so that leakage current from the power supply voltage VDD 1  to ground (i.e. Port VSS) may be avoided. Moreover, the voltage-level converting unit reduces the received voltage signal and converts the received voltage signal into an internal voltage signal. The internal voltage signal is transmitted into the internal chip through Port C. 
         [0006]    However, in existing I/O receivers, the maximum value of the voltage signal at Node B is (VDD 1 −Vthn), which cannot reach the operational power supply voltage VDD 1  of the I/O receiver. Therefore, the operation speed of the I/O receiver may be reduced and the performance of the I/O receiver may be degraded. 
         [0007]    The disclosed I/O receivers are directed to solve one or more problems set forth above and other problems in the art. 
       BRIEF SUMMARY OF THE DISCLOSURE 
       [0008]    One aspect of the present disclosure includes an input-output (I/O) receiver. The I/O receiver includes a receiving terminal, a first N-type metal-oxide-semiconductor (NMOS) transistor, a reformation circuit, and a compensation unit. The receiving terminal is coupled with an external voltage signal. The first NMOS transistor has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage. The reformation circuit is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. Moreover, the compensation unit is configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage. 
         [0009]    Other aspects of the present disclosure can be understood by those skilled in the an in light of the description, the claims, and the drawings of the present disclosure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure. 
           [0011]      FIG. 1  illustrates a schematic view of the circuit structure of an existing I/O receiver; 
           [0012]      FIG. 2  illustrates a schematic view of a circuit structure of an exemplary I/O receiver consistent with disclosed embodiments; 
           [0013]      FIG. 3  illustrates a schematic view of a circuit structure of another exemplary I/O receiver consistent with disclosed embodiments: 
           [0014]      FIG. 4  illustrates a schematic view of a circuit structure of another exemplary I/O receiver consistent with disclosed embodiments; and 
           [0015]      FIG. 5  illustrates simulated voltage profiles at certain positions in an exemplary I/O receiver consistent with disclosed embodiments and also in an existing I/O receiver. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
         [0017]      FIG. 2  shows a schematic view of a circuit structure of an exemplary I/O receiver consistent with disclosed embodiments. Referring to  FIG. 2 , the I/O receiver may include a receiving terminal (not labeled), a first NMOS transistor N 1 , a compensation unit  201 , a reformation circuit  202 , and a voltage-level converting unit  203 . 
         [0018]    The receiving terminal may be coupled with the external voltage signal transmitted into the I/O receiver through Port PAD. The source electrode of the first NMOS transistor N 1  may be coupled with the receiving terminal, while the gate electrode of the first NMOS transistor N 1  may be coupled with a first power supply voltage VDD 1 . The first power supply voltage VDD 1  may be the operation voltage level of the I/O receiver. The level of the first power supply voltage VDD 1  may be less than the maximum voltage level of the external voltage signal. As shown in  FIG. 2 , the input terminals of the reformation circuit  202  may be coupled with the first power supply voltage VDD 1 , the ground VSS, and the drain electrode of the first NMOS transistor N 1 , respectively. The reformation circuit  202  may be used to reform the voltage signal transmitted from the drain electrode of the first NMOS transistor N 1 . The input terminals of the compensation unit  201  may be coupled with the first power supply voltage VDD 1 , the ground VSS, and the receiving terminal, respectively. The output terminal of the compensation unit  201  may be coupled with the drain electrode of the first NMOS transistor N 1 . The compensation unit  201  may be used to provide a compensation voltage to the voltage signal at the drain electrode of the first NMOS transistor N 1  such that the maximum level of the voltage signal at the drain electrode of the first NMOS transistor N 1  may reach the first power supply voltage VDD 1 . 
         [0019]    In one embodiment, the compensation unit  201  may include a first PMOS transistor P 1 , a second PMOS transistor P 2 , and a second NMOS transistor N 2 . Specifically, the source electrode of the first PMOS transistor P 1  may be coupled with the first power supply voltage VDD 1 , the drain electrode of the first PMOS transistor P 1  may be coupled with the drain electrode of the second NMOS transistor N 2 , and the gate electrode of the first PMOS transistor P 1  may be coupled with the receiving terminal. The gate electrode of the second NMOS transistor N 2  may be coupled with the drain electrode of the first NMOS transistor N 1  and the source electrode of the second NMOS transistor N 2  may be grounded. The source electrode of the second PMOS transistor P 2  may be coupled with the first power supply voltage VDD 1 , the gate electrode of the second PMOS transistor P 2  may be coupled with the drain electrode of the first PMOS transistor P 1 , and the drain electrode of the second PMOS transistor P 2  may be coupled with the drain electrode of the first NMOS transistor N 1 . 
         [0020]    In one embodiment, the external voltage signal may be a rectangular wave signal. When the external voltage signal is at a logic-low voltage level while the initial voltage level at Node B is also low, the first PMOS transistor P 1  may be turned on and the second NMOS transistor N 2  may be turned off. Therefore, the voltage level at Net C may be high and the second PMOS transistor P 2  may be turned off. 
         [0021]    Further, at a rising edge where the external voltage signal rises from a logic-low voltage level to a logic-high voltage level, the first PMOS transistor P 1  may be turned off, while the second NMOS transistor N 2  may be turned on. The drain electrode of the first PMOS transistor P 1  may then be grounded through the second NMOS transistor N 2 . Thus, the voltage level of the drain electrode of the first PMOS transistor P 1  may be pulled down. When the voltage level at Net C drops to be less than or equal to the threshold voltage of the second PMOS transistor P 2 , the second PMOS transistor P 2  may be turned on so that the voltage level at Node B may reach the first power supply voltage VDD 1 . 
         [0022]    Moreover, at a falling edge where the external voltage signal falls down from a logic-high voltage level to a logic-low voltage level, the first PMOS transistor P 1  may be turned on, while the second NMOS transistor N 2  may be turned off. The voltage level at the drain electrode of the first PMOS transistor P 1  may increase. When the voltage level at Net C rises to be greater than the threshold voltage of the second PMOS transistor P 2 , the second PMOS transistor P 2  may be turned off so that the voltage level at Node B may drop to a logic-low voltage level. 
         [0023]    Specifically, a short current may flow from the first power supply voltage VDD 1  to the ground VSS on the falling edge of the receiving signal through the second NMOS transistor N 2 . When the voltage level at Node B reaches the first power supply voltage VDD 1 , the driving speed may be fast and the energy consumption may be low. 
         [0024]    Further, after the external voltage signal passes through the compensation unit  201 , the rising edge and the falling edge of the voltage signal at Node B may become moderate. The shape of the voltage signal may then be reformed through the reformation circuit  202 . After the reformation, the rising edge and the falling edge of the voltage signal may become sharp. 
         [0025]    The reformation circuit  202  may be an inverter unit. In one embodiment, the inverter unit  202  may include a third PMOS transistor P 3  and a fourth NMOS transistor N 4 . Specifically, the source electrode of the third PMOS transistor P 3  may be coupled with the first power supply voltage VDD 1 , and the gate electrode of the third PMOS transistor P 3  may be coupled with the drain electrode of the first NMOS transistor N 1 . The drain electrode of the fourth NMOS transistor N 4  may be coupled with the drain electrode of the third PMOS transistor P 3 , the source electrode of the fourth NMOS transistor N 4  may be grounded, and the gate electrode of the fourth NMOS transistor N 4  may be coupled with the drain electrode of the first NMOS transistor N 1 . In other embodiments, the inverter unit may have any other appropriate circuit structure. 
         [0026]    In one embodiment, the gate electrode of the third PMOS transistor P 3  and the gate electrode of the fourth NMOS transistor N 4  together may serve as an input terminal of the inverter unit  202  and may be coupled with Node B, while the drain electrode of the third PMOS transistor P 3  and the drain electrode of the fourth NMOS transistor N 4  together may serve as an output terminal of the inverter unit  202  and may be coupled with an input terminal of the voltage-level converting unit  203 . 
         [0027]    When the voltage signal at Node B rises from a logic-low voltage level to a logic-high voltage level, the third PMOS transistor P 3  may be turned off while the fourth NMOS transistor N 4  may be turned on. As the voltage signal at Node B stays at a logic-high voltage level, the ground VSS may pull down the voltage level at the output terminal of the inverter unit  202  to a logic-low voltage level. Further, when the voltage signal at Node B falls from the logic-high voltage level to the logic-low voltage level, the third PMOS transistor P 3  may turned on while the fourth NMOS transistor N 4  may turned off. As a result, the first power supply voltage may drive the output terminal of the inverter unit  202  to a logic-high voltage level. 
         [0028]    Further, the I/O receiver may include a voltage-level converting unit  203 . Specifically, a second power supply voltage VDD of the voltage-level converting unit  203  may be the operation voltage level of the chip. In one embodiment, the second power supply voltage VDD may be less than the first power supply voltage VDD 1 . Therefore, the output voltage signal of the I/O receiver may need to be converted to a signal in compliance with the power voltage of the chip through the voltage-level converting unit  203 . The converted voltage signal may then be transmitted to the chip through Port C. The voltage-level converting unit may have any appropriate circuit structure to realize the desired voltage conversion. 
         [0029]      FIG. 3  shows a schematic view of the circuit structure of another exemplary I/O receiver consistent with disclosed embodiments. Referring to  FIG. 3 , the I/O receiver may include a receiving terminal (not labeled), a first NMOS transistor N 1 , a compensation unit  201 , a reformation circuit  202 , and a voltage-level converting unit  203 . 
         [0030]    In one embodiment, the reformation unit  202  may be an inverter unit. Specifically, the circuit structure of the inverter unit may include a third PMOS transistor P 3 , a fourth PMOS transistor P 4 , and a fifth PMOS transistor P 5 . The source electrode of the third PMOS transistor P 3  may be coupled with a first power supply voltage VDD 1 , and the gate electrode of the third PMOS transistor may be coupled with the drain electrode of the first NMOS transistor N 1 . The source electrode of the fourth PMOS transistor P 4  may be coupled with the drain electrode of the third PMOS transistor P 3 , and the gate electrode of the fourth PMOS transistor P 4  may be coupled with the drain electrode of the first NMOS transistor N 1 . The drain electrode of the fourth NMOS transistor N 4  may be coupled with the drain electrode of the fourth PMOS transistor P 4 , and the gate electrode of the fourth NMOS transistor N 4  may be coupled with the drain electrode of the first NMOS transistor N 1 . Moreover, the drain electrode of the fifth NMOS transistor N 5  may be coupled with the source electrode of the fourth NMOS transistor N 4 , the source electrode of the fifth NMOS transistor N 5  may be grounded, and the gate electrode of the fifth NMOS transistor N 5  may be coupled with the drain electrode of the first NMOS transistor N 1 . 
         [0031]    Specifically, the gate electrodes of the third PMOS transistor P 3 , the fourth PMOS transistor P 4 , the fourth NMOS transistor N 4 , and the fifth NMOS transistor N 5  may together serve as an input terminal of the inverter unit and may be coupled with Node B, while the drain electrodes of the fourth PMOS transistor P 4  and the fourth NMOS transistor N 4  may together serve as an output terminal of the inverter unit and may be coupled with the voltage-level converting unit  203 . 
         [0032]    When the voltage signal at Node B rises from a logic-low voltage level to a logic-high voltage level, the third PMOS transistor P 3  and the fourth PMOS transistor P 4  may be turned off, while the fourth NMOS transistor N 4  and the fifth NMOS transistor N 5  may be turned on. As such, the ground VSS may pull down the voltage signal at the output terminal of the inverter unit to a logic-low voltage level. Moreover, when the voltage signal at Node B falls down from a logic-high voltage level to a logic-low voltage signal, the third PMOS transistor P 3  and the PMOS transistor P 4  may be turned on while the fourth NMOS transistor N 4  and the fifth NMOS transistor N 5  may be turned off. Therefore, a first power supply voltage VDD 1  may drive the voltage signal at the output terminal of the inverter unit to a logic-high voltage level. 
         [0033]    In other embodiments, the reformation circuit  202  may also be a Schmitt trigger. The Schmitt trigger may have any appropriate circuit structure. The reformation circuit  202  may be used to filter out noise and reform the shape for the output signal at Node B. 
         [0034]    Further, the inverter unit and the Schmitt trigger are both threshold switching circuits. Such a gate circuit with abrupt I/O characteristics may prevent changes in the output voltage due to a subtle variation in the input voltage (e.g., a change in the input voltage below a threshold value). Further, through a positive feedback during the voltage conversion process, a periodic signal with slowly-changed edges may be reformed to a pulsed rectangular wave signal with sharp rising and falling edges. Specifically, as long as the amplitude of the input signal reaches the turn-on threshold voltage of the MOS transistor, the output terminal may send out a pulsed rectangular wave signal with the same frequency as the input periodic signal. Further, any electric circuit realizing the desired signal reformation may be regarded as a reformation circuit consistent with the disclosed embodiments. 
         [0035]    Other aspects of the I/O receiver shown in  FIG. 3 , including the compensation unit  201  and the voltage-level converting unit  203 , are similar to the corresponding components of the I/O receiver shown in  FIG. 2 . One may refer to the description above for details. 
         [0036]      FIG. 4  shows a schematic view of the circuit structure of another exemplary I/O receiver consistent with the disclosed embodiments. Referring to  FIG. 4 , the I/O receiver may include a receiving terminal (not labeled), a first NMOS transistor N 1 , a compensation unit  201 , a reformation circuit  202 , and a voltage-level converting unit  203 . 
         [0037]    In one embodiment, the compensation unit  201  may include a first PMOS transistor P 1 , a second PMOS transistor P 2 , a second NMOS transistor N 2 , and a third NMOS transistor N 3 . The source electrode of the first PMOS transistor P 1  may be coupled with the first power supply voltage VDD 1 , the drain electrode of the first PMOS transistor P 1  may be coupled with the drain electrode of the second NMOS transistor N 2 , and the gate electrode of the first PMOS transistor P 1  may be coupled with the receiving terminal. The source electrode of the second PMOS transistor P 2  may be coupled with the first power supply voltage VDD 1 , while the gate electrode of the second PMOS transistor P 2  may be coupled with the drain electrode of the first PMOS transistor P 1 . The drain electrode of the third NMOS transistor N 3  may be coupled with the drain electrode of the second PMOS transistor P 2  and also to the drain electrode of the first NMOS transistor N 1 , the gate electrode of the third NMOS transistor N 3  may be coupled with the drain electrode of the first PMOS transistor P 1 , and the source electrode of the third NMOS transistor may be grounded. 
         [0038]    In one embodiment, the external voltage signal may be a rectangular wave signal. When the external voltage signal rises from the logic-low voltage level to the logic-high voltage level, the first PMOS transistor P 1  may be turned off, while the second NMOS transistor N 2  may be turned on. The drain electrode of the first PMOS transistor P 1  may then be grounded through the second NMOS transistor N 2 . Thus, the voltage level of the drain electrode of the first PMOS transistor P 1  may be pulled down. When the voltage level at the drain electrode of the first PMOS transistor P 1  drops to be less than or equal to the threshold voltage of the second PMOS transistor P 2 , the second PMOS transistor P 2  may be turned on, while the third NMOS transistor N 3  may be turned off. As such, the first power supply voltage VDD 1  may drive the output voltage at the drain electrode of the first NMOS transistor N 1  to reach the first power supply voltage VDD 1  through the second PMOS transistor P 2 . 
         [0039]    Moreover, when the external voltage signal falls down from the logic-high voltage level to the logic-low voltage level, the first PMOS transistor P 1  may be turned on, while the second NMOS transistor N 2  may be turned off. The voltage level at the drain electrode of the first PMOS transistor P 1  may then increase. When the voltage level at the drain electrode of the first PMOS transistor P 1  becomes greater than the threshold voltage of the second PMOS transistor P 2 , the second PMOS transistor P 2  may be turned off, while the third NMOS transistor may be turned on. The ground voltage VSS may drive the output voltage at the drain electrode of the first NMOS transistor N 1  to the logic-low voltage level through the third NMOS transistor N 3 . 
         [0040]    Other aspects of the I/O receiver shown in  FIG. 4 , including the reformation circuit  202  and the voltage-level converting unit  203 , are similar to the corresponding components of the I/O receiver shown in  FIG. 3 . One may refer to the description above for details. 
         [0041]      FIG. 5  shows simulated voltage profiles at certain positions in the I/O receiver shown in  FIG. 2  and also in the existing I/O receiver shown in  FIG. 1 . 
         [0042]    Referring to  FIG. 5  and  FIGS. 1-2 , the simulations are performed by using 1.6 V for the first power supply voltage VDD 1  and 3 V for the high voltage level of the external voltage signal. In addition, a threshold voltage (i.e. Vthn) of 0.9 V is assumed for both the NMOS transistor M 3  in the existing I/O receiver and the NMOS transistor N 1  in the disclosed I/O receiver. 
         [0043]    Referring to  FIG. 5 , for the existing I/O receiver shown in  FIG. 1 , the output voltage of the NMOS transistor M 31 . i.e. the voltage signal at Node B, may be in a range between 0 V and 0.7 V. That is, the maximum voltage level at Node B may only reach VDD 1 −Vthn. In such a case, the I/O receiver may still work, but the performance of the I/O receiver may be degraded. For the I/O receiver shown in  FIG. 2 , the voltage signal at Node B may be in a range between 0 V and 1.6 V. That is, the maximum voltage level at Node B may reach the first power supply voltage VDD 1 . Therefore, the performance of the I/O receiver may be desired and the working condition of the reformation unit may also be optimized. Therefore, according to the present disclosure, by raising the high voltage level output of the first NMOS transistor N 1  to the first power supply voltage VDD 1  through a compensation unit, the performance of the I/O receiver may be improved while the complexity of the circuit structure may not be increased. 
         [0044]    Compared to existing I/O receivers, the disclosed I/O receivers may demonstrate the following advantages. 
         [0045]    According to the present disclosure, each I/O receiver consistent with the disclosed embodiments may include a receiving terminal, a first NMOS transistor, a reformation circuit, and a compensation unit. The receiving terminal may be coupled with an external voltage signal. The source electrode of the first NMOS transistor may be coupled with the receiving terminal while the gate electrode of the first NMOS transistor may be coupled with a first power supply voltage. The input terminals of the reformation circuit may be coupled with the first power supply voltage, the ground, and the drain electrode of the first NMOS transistor, respectively. The reformation circuit may be used to reform the voltage signal transmitted from the drain electrode of the first NMOS transistor. 
         [0046]    Moreover, according to an I/O receiver consistent with the disclosed embodiments, the compensation unit may further include a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. Specifically, the source electrode of the first PMOS transistor may be coupled with the first power supply voltage, the drain electrode of the first PMOS transistor may be coupled with the drain electrode of the second NMOS transistor, and the gate electrode of the first PMOS transistor may be coupled with the receiving terminal. The gate electrode of the second NMOS transistor may be coupled with the drain electrode of the first NMOS transistor and the source electrode of the second NMOS transistor may be grounded. Moreover, the source electrode of the second PMOS transistor may be coupled with the first power supply voltage, the gate electrode of the second PMOS transistor may be coupled with the drain electrode of the first PMOS transistor, and the drain electrode of the second PMOS transistor may be coupled with the drain electrode of the first NMOS transistor. 
         [0047]    Further, when the receiving terminal receives a high voltage level signal, the first PMOS transistor may be turned off while the second NMOS transistor may be turned on. Therefore, the voltage level at the drain electrode of the first PMOS transistor may be pulled down through the second NMOS transistor. Moreover, because the drain electrode of the first PMOS transistor may be coupled with the gate electrode of the second PMOS transistor, the second PMOS transistor may then be turned on. Since the drain electrode of the second PMOS transistor may be coupled with the drain electrode of the first NMOS transistor, the voltage at the drain electrode of the first NMOS transistor may reach the operation power supply voltage of the I/O receiver. That is, the compensation unit may provide a compensation voltage to the voltage signal at the drain electrode of the first NMOS transistor such that the maximum level of the voltage signal at the drain electrode of the first NMOS transistor may reach the first power supply voltage. Therefore, with a simple circuit structure, the disclosed I/O receiver accepts external high voltage inputs and also improves the speed and performance of the I/O circuit. 
         [0048]    The above detailed descriptions only illustrate certain exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention. Those skilled in the art can understand the specification as whole and technical features in the various embodiments can be combined into other embodiments understandable to those persons of ordinary skill in the art. Any equivalent or modification thereof, without departing from the spirit and principle of the present invention, falls within the true scope of the present invention.