Abstract:
A circuit for detecting asynchronous events includes a first event detection latch; and a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection latch is being reset and wherein the second event detection latch is ready to detect a next event when the first event detection latch is being reset.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This Patent Application claims the benefit of the filing date of U.S. Provisional Patent Application Ser. No. 60/618,521, filed on Oct. 13, 2004 and entitled “METHOD AND APPARATUS FOR RELIABLE PULSE EVENT DETECTION,” the entire content of which is hereby expressly incorporated by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to electronic circuits; and more particularly to pulse event detection method and circuit.  
       BACKGROUND OF THE INVENTION  
       [0003]     Pulse event detection is common among electronic systems. It can be performed by synchronous or asynchronous methods depending on the requirement of the system. The asynchronous method detects pulses, without the use of a clock and is suited for low power operations of a mouse button or keyboard events, for example. However, in the operation of a typical asynchronous event detection, shown in  FIG. 1 , the event pulse might be missed depending on the frequency of the events.  
         [0004]     For example, when a rising edge event is latched in latch  10 , it triggers an interrupt  13  to a processor. After, being interrupted, the processor typically clears the event latched in latch  10  by writing to a memory location. The write operation to the memory by the processor generates a low going pulse at  12  and asynchronously clears the latch  10 . The problem arises when there is an incoming rising edge next event during this interrupt-driven clear cycle.  
         [0005]     For example, after the pulse event is acknowledged and processed by a control unit of the system (e.g., a processor), the detection circuit has to be cleared and re-armed for detection of next event. It is likely that the clearing of the detection circuit masks a new incoming edge event. This causes the new incoming event to be missed and lost.  
         [0006]     Therefore, there is a need for an circuit and method for a more reliable pulse event detection.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention is related to a solution to the above problem by employing a redundancy edge and/or level detection circuit including an edge and a level pulse detection logic, or another edge detection circuit. The present invention solves the above problem by a new design including a(n) edge/level detection latch, which begins detection after the rising edge of the “clear” pulse. In this case, the processor can check the interrupt right after the “clear” signal to make sure no edge occurs.  
         [0008]     In one embodiment, the invention is a circuit for detecting asynchronous events. The circuit includes a first event detection latch; and a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection latch is being reset and wherein the second event detection latch is ready to detect a next event when the first event detection latch is being reset.  
         [0009]     In one embodiment, the invention is a method for detecting asynchronous events. The method includes detecting a first event by a first event detection circuit; resetting the first event detection circuit after the first event is detected; detecting a second event by a second event detection circuit; and resetting the second event detection circuit after the second event is detected, wherein the first event detection circuit is ready to detect an event when the second event detection circuit is being reset and wherein the second event detection circuit is ready to detect a next event when the first event detection circuit is being reset.  
         [0010]     In one embodiment, the invention is a programmable circuit for detecting event signal. The circuit includes a first programmable event detection circuit for detecting one of the group consisting a rising edge event, a falling edge event, a high level event, and a low level event; and a second programmable event detection circuit coupled to the first programmable event detection latch for detecting one of the group consisting a rising edge event, a falling edge event, a high level event, and a low level event, wherein the first and second programmable event detection circuits operate in a ping-pong manner for detecting events. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  shows a typical asynchronous event detection circuit;  
         [0012]      FIG. 2  is an exemplary circuit diagram for a reliable pulse event detection method and apparatus, according to one embodiment of the invention;  
         [0013]      FIG. 3  is an exemplary timing diagram for circuit of  FIG. 2 ;  
         [0014]      FIG. 4  depicts an exemplary block diagram for a pulse event detection capable of detecting a rising edge event and/or a falling edge event, according to one embodiment of the present invention; and  
         [0015]      FIG. 5  is an exemplary circuit diagram for a pulse event detection capable of detecting a rising edge event and/or a falling edge event, according to one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0016]     In one embodiment, the present invention is directed to a method and apparatus for a reliable pulse event detection.  FIG. 2  is an exemplary circuit diagram for a reliable pulse event detection method and apparatus, according to one embodiment of the invention. As shown, latch  101  detects the rising edge of the event  100  by latching a “high”  110  at its output  102 . Multiplexer  104 , controlled by the sel_level signal  107  (from the processor), selects the latched high output  102  to generate an interrupt signal  109 . Once interrupted, the processor attempts to clear (re-arm) latch  101  for detection of the next event. This is performed by sending a clr 103  signal  103  used to clear latch  101 . At the same time, the processor toggles the sel_level signal  107 , used to control the multiplexor  104 .  
         [0017]     However, while latch  101  is being cleared by the clr 103 , the next event  100   a  may occur, as shown by the exemplary timing diagram of  FIG. 3 . This next event will be missed by latch  101 , because clr 103  pulse  103  is still high, as shown in  FIG. 3 . Nevertheless, next event  10   a  is captured by the level detection latch  105  by clocking a high (i.e.,  111 ) to its output  108 , as shown in the timing diagram of  FIG. 3 . Since the processor is still performing the interrupt routine, the write operation, and/or generating the clr 103  signal, it toggles the sel_level signal  107  from an “edge detect” mode to a “level detect” mode, as shown in the timing diagram of  FIG. 3 . As a result, the multiplexor  104  selects the high output  108  of the latch  105 , as a second interrupt  109  to the processor, as the detection of the second event  10   a.  This way, the level detection latch  105  begins detection right after the rising edge of the clr 103  pulse  103  and processor can check the interrupt  109  right after clr 103  to make sure no event edge occurs.  
         [0018]     Although, in the exemplary circuit of  FIG. 2 , latch  105  is depicted as a level detector, those skilled in the art will understand that latch  105  can be an edge detector similar to latch  101 . Likewise, latch  101  may be a level detector similar to latch  105 , depending on the application. In one embodiment, the two edge/level detector latches  101  and  105  operate in a “ping-pong” manner, in which while latch  101  is being reset (by the processor), latch  105  is ready for operation, and when latch  105  is being reset, latch  101  is ready for operation. In other words, in this manner, the two latched alternate to detect the next coming events.  
         [0019]      FIG. 4  is an exemplary block diagram for a programmable pulse event detection capable of detecting a rising edge event and/or a falling edge event, according to one embodiment of the present invention. It is understood that the programmable pulse event detection of  FIG. 4  may be designed to detect a high level event and/or a low level event, as discussed above with respect to  FIG. 2 .  
         [0020]     As shown in  FIG. 4 , latches  402  and  406  detect a positive edge event and latched  404  and  408  detect a negative edge event. A first control signal Pos/Neg_A controls whether the top detection circuit detects a positive edge or a negative edge by enabling and disabling (via the inverter  403 ) the respective latches  402  and  404 . For example, if the control signal Pos/Neg_A is low, the positive edge detector latch  402  is enabled and the negative edge detector latch  404  is disabled. In one embodiment, the output of the disabled latch  404  is connected to the output of the positive edge detector latch  402 . In this embodiment, the output of the disabled latched is tri-stated, so that the respective inputs to the MUX  409  are controlled by the enabled latches, respectively.  
         [0021]     Similarly, a second control signal Pos/Neg_B controls whether the bottom detection circuit detects a positive edge or a negative edge by enabling and disabling (via the inverter  405 ) the respective latches  406  and  408 . The two output of the top detection circuit and the bottom detection circuit are (alternatively) selected by the MUX  409 . The Select signal controlling the MUX  409  may be controlled by the processor. Alternatively, the Select signal may be a simple toggle switch that selects the top and the bottom detection circuits in a ping-pong fashion.  
         [0022]     As described above, one or both of the top and bottom detection circuits may be a (high and/or a low) level detection circuit. In one embodiment, the first control signal Pos/Neg_A and the second control signal Pos/Neg_B are the same signal.  
         [0023]      FIG. 5  depicts an exemplary circuit diagram for a reliable pulse event detection capable of detecting a rising edge event (by latch  201 ) and/or a falling edge event (by latch  200 ), according to one embodiment of the present invention. A rising edge and/or a falling edge event detection is programmable by control signals  210  and/or  218 . The two Nand gates  212  and  213  and the Or gate  214 , select the output of latch  201  as the rising edge detected event, or the output of latch  200  as the falling edge detected event, based on the control signal  210 . The output of the Or gate  214  is then fed to a multiplexor  215 .  
         [0024]     If the circuit is in the edge detection mode, this output of the Or gate  214  is fed through the multiplexor  215  and is synchronized by the latches  216  and  217 , before it is input to the processor as an interrupt signal  209 . The interrupt signal  209  may be disabled by the signal  208  (that may come from the processor) via the Nand gate  226 .  
         [0025]     Similarly, when the edge detection latches  200  and  201  are being reset by signal  202 , latch  203  is ready to detect the next event, as described above with respect to  FIG. 2 . Multiplexor  215  is controlled by select signal  207 , depending on the interrupt type. That is, the output of Or gate  214  is selected by the multiplexor, if edge detection is enabled. Alternatively, the output of the level detection latch  203  is selected, if level detection is enabled. Signal  218  programs the detection circuit to perform both rising edge and falling detections.  
         [0026]     The reset signals  202  and  204  clear the edge detection latches  200  and  201 , and the level detection latch  203 , respectively. In one embodiment, the reset signals are generated from the write signal of the processor in box  211 . Signal  206  is used as a “wake up” signal for power management purposes. That is, when an event is detected, the system is “woken up” from a power stand by mode. The “wake up” signal  206  can be disabled via the And gate  224 .  
         [0027]     Again, as discussed above, one or more of the latches  200  and  201  can be a (high and/or low) level detector latches.  
         [0028]     It will be recognized by those skilled in the art that various modifications may be made to the illustrated and other embodiments of the invention described above, without departing from the broad inventive scope thereof. It will be understood therefore that the invention is not limited to the particular embodiments or arrangements disclosed, but is rather intended to cover any changes, adaptations or modifications which are within the scope and spirit of the invention as defined by the appended claims.