Abstract:
Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority from S. McGrath et al. U.S. Provisional Application No. 61/280,584, filed Nov. 4, 2009, titled “Stacked die assembly having reduced stress electrical interconnects”, which is hereby incorporated by reference. 
    
    
     BACKGROUND 
     This invention relates to electrical connection of semiconductor die to circuitry in a support and, particularly, to electrical connection of a stack of electrically interconnected die to circuitry in a support. 
     A typical semiconductor die has a front (“active”) side, in which the integrated circuitry is formed, a back side, and sidewalls. The sidewalls meet the front side at front edges and the back side at back edges. Semiconductor die typically are provided with interconnect pads (die pads) located at the front side for electrical interconnection of the circuitry on the die with other circuitry in the device in which the die is deployed. Some die as provided have die pads on the front side along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows at the front side near the center of the die, and these may be referred to as central pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the margins of the die. 
     Semiconductor die may be electrically connected with other circuitry, for example in a printed circuit board, a package substrate or leadframe, or another die, by any of several means. Such z-interconnection may be made, for example, by wire bonds, or by flip chip interconnects, or by tab interconnects. The package substrate or leadframe provides for electrical connection of the package to underlying circuitry (second-level interconnection), such as circuitry on a printed circuit board, in a device in which the package is installed for use. 
     A number of approaches have been proposed for increasing the density of active semiconductor circuitry in integrated circuit chip packages, while minimizing package size (package footprint, package thickness). In one approach to making a high density package having a smaller footprint, two or more semiconductor die, of the same or different functionality, are stacked one over another and mounted on a package substrate. 
     Electrical interconnection of stacked semiconductor die presents a number of challenges. For instance, two or more die in a stack may be mounted on a substrate with their front sides facing away from the substrate, and connected by wire bonds die-to-substrate or die-to-die. Die-to-die wire bond interconnect may be made where an upper die is dimensioned or located so that the upper die does not overlie the margin of the lower die to which it is connected, and so that sufficient horizontal clearance is provided for the wire span. This condition may pertain, for example, where the footprint of the upper die is sufficiently narrower than the lower die; or, for example, where the upper die is arranged so that the footprint of the upper die is offset in relation to the margin of the lower die. Alternatively, the die in the stack may be indirectly interconnected by connecting them to a common substrate on which the stack is mounted. Where a lower die in a stack is wire bonded die-to-substrate, and where the footprint of an upper die overlies the margin of the lower die, a spacer may be interposed to provide sufficient vertical clearance between the lower and the upper die to accommodate the wire loops over the lower die. The spacer adds to the thickness of the stack and, consequently, of the package. Moreover, in such a configuration the wire bond die-to-substrate connection of the lower die must be completed before the spacer and the upper die are stacked over it; that is, the die must be stacked in situ on the substrate and the die must be stacked and connected serially. 
     S. J. S. McElrea et al. U.S. application Ser. No. 12/124,077, filed May 20, 2008, titled “Electrically interconnected stacked die assemblies”, incorporated herein by reference, describes stacked die configurations in which interconnect pads on the die are electrically connected by traces of an electrically conductive interconnect material. In some configurations adjacent die in the stack are provided with interconnect pads arranged at the front side along a die margin, and the edge at the margin of an overlying die is offset in relation to the margin of the die beneath it. The offset reveals at least a fraction of the area of the interconnect pads on the lower die, so that the pads on the lower die are available for electrical connection with pads on a die situated above. The electrically conductive interconnect material is an electrically conductive polymer, such as a curable conductive epoxy, for example. 
     T. Caskey et al. U.S. application Ser. No. 12/124,097, filed May 20, 2008, titled “Electrical interconnect formed by pulse dispense”, incorporated herein by reference, describes methods for electrical interconnection of die in a stack, and of stacked die with a substrate, by depositing an electrical interconnect material in situ in a series of pulses to form an electrically continuous interconnection. The interconnect material may be a curable material, and may be deposited in an uncured or partially cured state; and the material may be partially or additionally cured at an intermediate stage following dispense, and may be fully cured when dispense has been completed. Suitable interconnect materials include polymers filled with conductive material in particle form such as, for example, metal-filled polymers, including, for example metal filled epoxy, metal filled thermosetting polymers, metal filled thermoplastic polymers, or electrically conductive inks. 
     The quality of the die-to-die electrical connection depends in part upon the electrical continuity between the interconnect and the die pads, and in part upon the mechanical integrity of the interconnect traces. There is a general trend toward finer interconnect pad pitch and, accordingly, toward smaller interconnect pad area. Where the interconnect material is a polymer filled with electrically conductive particles, such as a silver-filled epoxy, for example, the electrical continuity between the die pad and the interconnect material depends upon the adhesion of the interconnect material with the pad surface. 
     Stacked die assemblies and stacked die packages must be capable of withstanding temperature changes during operation. The thermal expansion characteristics differ among the various materials in the package, and thermal cycling of the construct can result in fatigue-driven degradation of the interconnect trace itself, or of the contact between the die pad or the bond pad and the interconnect trace. 
     SUMMARY 
     This application discloses stacked die assemblies in which interconnect failure is reduced by any of a variety of approaches. The stacked die assemblies include die stacked over a support such as a substrate, in which pads on the die are electrically interconnected and are electrically connected to circuitry in the support by traces formed of an electrically conductive material. Suitable electrically conductive materials include materials that can be applied in a flowable form and then cured or allowed to cure to form the electrically conductive traces. Such materials include, for example, electrically conductive polymers, including electrically conductive particulates (e.g., conductive metal particles) contained in a curable organic polymer matrix (for example, conductive (e.g., filled) epoxies, or electrically conductive inks); and include, for example, electrically conductive particulates delivered in a liquid carrier. In particular embodiments the interconnect material is a conductive polymer such as a curable conductive polymer, or a conductive ink. 
     The support to which the die are electrically connected can be a circuit board, or a package substrate, or a leadframe. Suitable package substrates include, for example, a ball grid array (“BGA”) or land grid array (“LGA”) substrate, or a flex tape substrate. 
     Thermal expansion characteristics (particularly, coefficient of thermal expansion, or “CTE”) differ among the various materials in the assembly, and thermal cycling of the construct can result in fatigue-driven degradation of the contact between the die pad and the interconnect. The different CTEs of the materials making up the various components can cause the components to tend to expand or contract to different extents over a range of temperatures. Where the various components of the assembly are securely affixed to one another, this differential expansion/contraction can result in a warping of the assembly or of some of the parts of the assembly. This effect can be particularly problematic where the die in the stack are very thin. The warp may produce a convex upper die surface, or a concave upper die surface, depending upon the particular materials and the particular temperature cycle. This can result in interconnect failures by, for example, cracking or breaking of interconnect traces; or by complete or partial separation (delamination) of the traces from the die pad or the bond pad. 
     Computer modeling and stress analysis and testing have suggested or shown some patterns in the location of interconnect failures. For example, in at least some stacked die assemblies, the interconnect failure may be located in pads near the corners of the die. And, for example, in at least some stacked die assemblies, the interconnect failure is located at some point between the die pad on the bottom die in the stack and the bond pad on the substrate. The interconnect trace may, for example, be partly or entirely delaminated from the die pad, or from the bond pad; or, for example, the interconnect trace itself may be cracked or broken, near the inside corner where the back side die edge on the interconnect sidewall meets the substrate. 
     Computer modeling and stress analysis and testing have further suggested that the robustness of the electrical connection of the interconnect material with a die pad or bond pad can be better at some sites on the pad than at others. Particularly, depending upon the particular configuration of the die stack, a more robust connection may result if made at a site in the pad nearer the die edge; or nearer the inside corner where the back side die edge on the interconnect sidewall of the bottom die meets the die attach side of the underlying substrate, or where the back side die edge on the interconnect sidewall of an upper die meets the active side of an underlying die. 
     The various approaches, described below, address interconnect failure challenges. 
     In one approach, the bottom die in the stack has a greater thickness than the other die in the stack. This may be accomplished during the manufacture of the bottom die at the wafer level, by, for example, leaving the bottom die wafer thicker following backgrinding than the other die. The bottom die may have the same (or similar) functionality as the other die in the stack; or, the bottom die may have a functionality different from that of the other die in the stack. The greater thickness provides increased stiffness to the stack, and can help to reduce warping or bending. 
     In another approach, a nonfunctional die is situated between the lowest functional die in the stack and the support. The nonfunctional die may in some configurations be configured substantially the same as the lowest functional die in the stack; in some such configurations the interconnects may not contact the pads on the additional die; or, in some such configurations the pads may be disabled (for example they may be covered by a dielectric material, so that the additional die is not electrically connected to overlying interconnect traces). In some configurations the nonfunctional die may be an additional die; in other configurations the nonfunctional die is a “sacrificial” bottom die of a stack, rendered nonfunctional by being disabled. 
     In another approach, zones near the corners of the die are left free of electrical connection. In some configurations the “keepout” zones may constitute portions of the interconnect margin of the die at which no pads are situated. This arrangement may be designed into the placement of pads in a rerouting pattern; or, this arrangement may result during the die singulation process, by cutting the die wider than would be minimally required for the circuitry and the pad arrangement. In some configurations the “keepout” zone may constitute disabling interconnection to pads at one or a few die pad positions (“sacrificial pad positions”) near the affected corner. For example the die pads in the sacrificial pad positions may be disabled (for example they may be covered by a dielectric material), so that the die is not electrically connected to overlying interconnect traces in the keepout zones. In some configurations connection of die pads in the sacrificial pad positions to corresponding bond pads may be prevented by disabling bond pads at the corresponding positions on the substrate, or by designing the substrate so that no bond pads are located there. 
     In another approach, where the assembly is to be molded or encapsulated, cure of the interconnect material is completed following the molding or encapsulation procedure. Following deposition of the interconnect material in flowable form, a partial cure may be carried out. Thereafter molding or encapsulation is carried out, so that final cure of the interconnect material is delayed until after the assembly has been to some extent stabilized by the molding or encapsulation. Typically, where cure of both the molding compound or encapsulant and the interconnect material is completed by heating, and the cure processes for each may have different temperature schedules, the schedule can be manipulated according to the cure requirements for the particular materials employed. 
     In a further approach in which cure of the interconnect material is completed following the molding or encapsulation procedure, the molded or encapsulated assembly can be prestressed during final cure to provide a counteracting warp or bend in the structure. That is, where testing or modeling of a particular assembly suggests that thermal stress is likely to produce a concave upper die surface, the mold cavity is configured so that when the assembly is pressed into the cavity the assembly is flexed to form a convex upper die surface and held in that state during final cure; or, where testing or modeling of a particular assembly suggests that thermal stress is likely to produce a convex upper die surface, the mold cavity is configured so that when the assembly is pressed into the cavity the assembly is flexed to form a concave upper die surface and held in that state during final cure. 
     Some types of interconnect failure can result from transverse cracks in the trace, which typically propagate from a surface of the trace material, and which may occur during molding or encapsulation. Accordingly, in another approach, particularly for example where the assembly is to be molded or encapsulated, the interconnect traces can be coated with a film of a material such as a polymer (for example, a parylene or a silicone rubber) prior to the encapsulating or molding procedure. Apparently (without limitation) the film provides a sort of relief or lubrication at the interface of the interconnect material and the molding material or encapsulant, and thereby reduces stresses, for example during stress testing, that may result in crack formation. 
     In another approach, where modeling suggests that more robust electrical connection may be obtained on particular sites on a die pad or bond pad (“preferred sites”), electrical connection is directed to the preferred sites. Particularly, for example stress analysis of a particular assembly configuration may suggest that at some sites on a die pad or bond pad the electrical connection (that is, the joint between the conductive trace and the pad) will be under compression, while at other sites on the pad the electrical connection will be under tension. Electrical connections that are under compression are likely to be more robust. Accordingly the interconnect material is applied to particularly contact the preferred sites. In some configurations, where a dielectric coating is provided, with openings over areas that are to be contacted by the interconnect trace, this is accomplished by forming the openings particularly over the preferred sites. 
     In another approach, an underfill is formed between the bottom die in the stack and the substrate. The underfill is deposited near one or more edges of the bottom die. The underfill reinforces the adhesion of the die stack to the substrate, and helps prevent or reduce delamination along the edge. The underfill may be applied in particular spots, at intervals along the edge, or continuously along the edge. Where an electrically non-conductive underfill is used, it can be deposited at or along any of the die edges, in some configurations a non-conductive underfill is deposited at spots along the die interconnect sidewall, usually generally between the bond pads; and in some configurations the non-conductive underfill is deposited in a continuous line along one or more of the non-interconnect sidewalls. Where an electrically conductive underfill is used, it can be deposited at any location where the underfill will not cause electrical shorting. In some configurations an underfill is deposited at or near the corners of the bottom die, away from any electrically conductive features in the die or at the substrate surface. 
     In another approach, an underfill is deposited at the inside angle formed by a die sidewall and an underlying surface. The die sidewall can be, for example, the interconnect sidewall of the bottom die; and the underlying surface can be, for example, an area of the die attach side of the substrate, inboard of the bond pads and adjacent the die sidewall. Or, for example, the interconnect sidewall can be the interconnect sidewall of an upper die; and the underlying surface can be, for example, an electrically insulated area of the front side of an underlying die, inboard of the die pads on the underlying die and adjacent the upper die sidewall. Or, for example, the die sidewall can be a sidewall of a flip chip die oriented die-down on the substrate and electrically connected to the substrate in the die footprint, and the underlying surface can be, for example, an electrically insulated area of the die attach side of the substrate, inboard of the bond pads and adjacent the die sidewall. Or, for example, the interconnect sidewall can be the interconnect sidewall of a die stacked over a flip chip die; and the underlying surface can be, for example, an electrically insulated area of the back side of the underlying flip chip die. Or, for example, the underfill can be deposited at the inside angle formed by a sidewall of a molded package, such as a chip scale package. The underfill may be formed so that it forms a fillet approximating a right triangular shape in transverse section; viewed in this way the hypotenuse of the triangle shape is a sloping surface over which an interconnect trace can be formed; and a vertical side of the triangle forms an angle with the hypotenuse at or near the upper die interconnect edge. The sloping surface of the fillet may be slightly concave or convex, or may be a more complex slightly curved surface. The underfill can be CTE matched, to help stabilize the assembly, reducing delamination effects. Moreover, the underfill, shaped as described above, can provide a gradual transition from die-to-die or from die-to-substrate, eliminating abrupt angular (approximately right-angle) transitions at the interconnect edges of the die and at the inside corners where the back edge of the die sidewall meets the underlying surface. In some configurations, a first underfill fillet formed at the sidewall of a bottom die and a substrate can support a first set of electrical interconnect traces connecting pads on the bottom die with bond pads in a first row on the substrate; and an additional underfill fillet formed over the first interconnect traces on the first fillet at the sidewall of an upper die and the bottom die can support a second set of interconnect traces from die pads on the upper die to bond pads in a second row, outboard from the first row, on the substrate. 
     Further approaches can be employed where the underfill is formed at the inside angle of a sidewall of a flip chip die oriented die-down on the substrate and electrically connected to the substrate in the die footprint, and the underlying surface is an electrically insulated area of the die attach side of the substrate, inboard of the bond pads and adjacent the die sidewall, to assist in constraining the flow (“run-out” or “bleed”) of the underfill material over the substrate. 
     In one such approach, a dam is formed prior to depositing the underfill material, to prevent or limit flow of the underfill laterally—that is, to limit or prevent flow of the underfill material in a direction generally parallel to the row of bond pads on the substrate. The dam material may be a curable material applicable in a flowable form and thereafter cured or allowed to cure. The dam material may have properties that make it generally less likely than the underfill material to flow (run-out or bleed) when in an uncured state. The dam material may have a higher viscosity, for example, than the underfill material. The dam material and the underfill material may be cured in the same cure procedure, or the dam material may be cured in an earlier cure procedure. 
     In another such approach, where the die attach side of the substrate is covered by a solder mask, a trench may be formed in the solder mask, having a trench wall situated generally parallel to the row of bond pads on the substrate, to limit the flow of underfill material toward the bond pads, and thereby to prevent run-out or bleed of the underfill material over the bond pads. The advancing front of the flowing underflow material can be substantially halted at the trench wall edge. 
     The die, packages, and assemblies according to the invention can be used in computers, telecommunications equipment, and consumer and industrial electronics devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagrammatic sketch in a perspective view showing a die mounted onto a support. 
         FIG. 2A  is a diagrammatic sketch in a plan view showing a die mounted onto a support as in  FIG. 1 . 
         FIGS. 2B and 2C  are diagrammatic sketches in sectional views showing a die mounted onto a support as in  FIG. 1 , as indicated at B-B and C-C, respectively. 
         FIGS. 3A and 3B  are diagrammatic sketches showing an offset die stack mounted on and electrically connected to a support, in plan view ( FIG. 3A ) and in a sectional view ( FIG. 3B ). 
         FIG. 3C  is a diagrammatic sketch showing a portion of the sectional view of  FIG. 3B , enlarged. 
         FIG. 4A  is a diagrammatic sketch in a partial plan view showing the offset edges of an example of an 8-die offset stack, interconnected. 
         FIG. 4B  is a diagrammatic sketch in a partial sectional view of an 8-die offset stack, as indicated at B-B in  FIG. 4A , interconnected. 
         FIG. 5  is a diagrammatic sketch in a sectional view showing an example of a stacked die assembly constructed according to one of the approaches outlined above, having a thicker bottom die. 
         FIGS. 6A ,  6 B and  6 C are diagrammatic sketches in sectional views showing examples of stacked die assemblies constructed according to another of the approaches outlined above, having a nonfunctional die situated at the substrate. 
         FIGS. 7A ,  7 B and  7 C are diagrammatic sketches in sectional views showing examples of stacked die assemblies constructed according to another of the approaches outlined above, having zones near the corners of the die left free of electrical connection. 
         FIGS. 8A ,  8 B and  8 C are diagrammatic sketches in sectional views showing examples of stacked die assemblies constructed according to another of the approaches outlined above, having underfill formed at various locations between the bottom die in the stack and the substrate. 
         FIGS. 9A ,  9 B and  9 C are diagrammatic sketches in sectional views showing examples of stacked die assemblies constructed according to another of the approaches outlined above, having an underfill fillet formed at the inside corner defined by a die sidewall and an underlying surface. 
         FIGS. 10A and 10B  are diagrammatic sketches showing an example of a stacked die assembly constructed according to another of the approaches outlined above, having structures limiting the flow of underfill material over the substrate surface.  FIG. 10B  is a partial plan view; and  FIG. 10A  is a sectional view taken at A-A in  FIG. 10B . 
     
    
    
     DETAILED DESCRIPTION 
     The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGs. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGs. Also for clarity of presentation certain features are not shown in the FIGs., where not necessary for an understanding of the invention. At some points in the description, terms of relative positions such as “above”, “below”, “upper”, “lower”, “top”, “bottom” and the like may be used, with reference to the orientation of the drawings; such terms are not intended to limit the orientation of the device in use. 
     Turning now to  FIG. 1 , there is shown in a perspective view a semiconductor die  10  mounted over a substrate  110 . The die  10  has two larger generally parallel, generally rectangular sides, and four sidewalls. One larger side may be referred to as the front side, and the other may be referred to as the back side. The circuitry of the die is situated at or near the die surface at the front side, and so the front side may be referred to as the active side of the die. In the view presented in  FIG. 1  the die  10  is shown with the active side facing away from the substrate  110 , so that the front side  12  of die  10  is visible. Also visible in the view shown in  FIG. 1  are sidewalls  14  and  16  of die  10 . Margins of the die are adjacent the sidewalls; for example, margin  17  is adjacent the sidewall  14  on the front side  12  of die  10 . The intersection of a die sidewall and the front side define a front edge; for example front edge  13  is defined at the intersection of die sidewall  14  and the front side  12 . Interconnect pads are arranged in a margin along a front edge; in the example shown here pads  18  are arranged in a row  19  in or near the margin  17  along a front edge  13  of die  10 . A die edge along which pads are arranged may be referred to as an “interconnect edge”, and the adjacent margin and die sidewall may be referred to as an “interconnect margin” and an “interconnect sidewall”, respectively. 
     In the example shown in  FIG. 1  the die  10  is mounted onto a die attach side  112  of the substrate  110  by means of a die attach film  15 . Typically a number of substrates are formed in one or more rows in a strip and subsequently separated by sawing or punching. In the example shown bond pads  118  are arranged in a row  119  at the die attach side  112  of the substrate  110 , and the die is situated so that the die pads  18  are generally aligned with corresponding bond pads  118  on the substrate. Electrical connection (not shown in  FIG. 1 ) of the die pads  18  with corresponding bond pads  118  is made by applying traces of an electrically conductive material in a flowable form over the respective die pads and bond pads, and then curing the material (or allowing the material to cure) to complete the interconnect. 
     For reference, the directional axes X and Y parallel to, and Z perpendicular to, the plane of the larger sides of the die (and the plane of the die attach side of the substrate) are indicated at  11  in  FIG. 1  and at  21  in  FIGS. 2A ,  2 B and  2 C. 
     The various materials in an assembly such as is illustrated for example in  FIG. 1  may have different thermal expansion characteristics (different coefficients of thermal expansion, “CTE”). Particularly, there may be a CTE mismatch between the die (silicon) and the die attach film. Thermal cycling of the construct can cause stresses and strains in the construct, which may result in fatigue-driven degradation of the contact between the interconnect and the die pads or the bond pads, or of the interconnect itself. 
       FIGS. 2A ,  2 B and  2 C show a die  20  mounted on a substrate  210  in plan view ( FIG. 2A ) and in sectional views ( FIGS. 2B ,  2 C). In the example shown here, the die  20  is mounted onto a die attach side  212  of the substrate  210  by means of a die attach film  25 . In this example, die pads  28 ,  28 ′ are arranged in rows  29 ,  29 ′ along interconnect margins  27 ,  27 ′ at opposite front die edges  23 ,  23 ′. Corresponding bond pads  218 ,  218 ′ are arranged in rows  219 ,  219 ′ at the die attach side  212  of the substrate, and the die is situated so that the die pads  118 ,  118 ′ are generally aligned with corresponding bond pads  218 ,  218 ′ on the substrate. Electrical connection (not shown in these FIGs.) of the die pads  118 ,  118 ′ with corresponding bond pads  218 ,  218 ′ is made by applying traces of an electrically conductive material in a flowable form over the respective die pads and bond pads, and then curing the material (or allowing the material to cure) to complete the interconnect. The tendencies of the various components to contract or expand in relation to one another is illustrated by the arrows  21 . 
     The tendencies of the various components to expand or contract differently can result in relative movement of the parts; for example, the die edges may move in relation to the underlying substrate. More usually, where the various components are securely affixed to one another, the tendencies of the various components to expand or contract differently can result in a curling or warping of the structure or of parts of the structure. This distortion of the shape can cause failure of some interconnections, by causing a crack or break in the interconnect itself, or by partial or complete delamination of the interconnect from one or more pads. 
     S. J. S. McElrea et al. U.S. patent application Ser. No. 12/124,077, filed May 20, 2008, titled “Electrically interconnected stacked die assemblies”, which is incorporated herein by reference, describes among other things stacked die assemblies in which successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. The electrically conductive traces are formed of a material that is applied in a flowable form and subsequently cured or allowed to cure. Examples of such materials include electrically conductive polymers such as filled polymers, for example filled epoxies or electrically conductive inks. 
       FIG. 3A  shows in a plan view an arrangement of offset stacked die  34   a - 34   h , each die having interconnect pads arranged in one margin adjacent a front die edge; and  FIG. 3B  shows the stack in a sectional view as indicated at  1 B- 1 B in  FIG. 3A . Referring to the uppermost die  44   h  in the stack, for example, interconnect pads  32  are in this example situated in a row  312  alongside a front die edge  311 . The die  34   h  in this example is covered on all surfaces (back surface  33 , front surface  35 , sidewalls  31 ) by an electrically insulative conformal coating  37 , provided with openings exposing interconnect pads  32 . Successive coated die in the stack may, as in these examples, rest directly one upon another, such that the coating on the back side of an upper die can contact the coating on the front side of the underlying die. Optionally, or additionally, a die attach film may be laminated onto the back side of one or more of the die. 
     In the example shown in  FIGS. 3A and 3B  each die has interconnect pads situated in a margin along one front die edge (an “interconnect” edge), and succeeding die in the stack are arranged so that their respective interconnect edges face toward the same face of the stack. Successive die in the stack are displaced (offset) in a direction orthogonal to the die edge along which the pads are situated, and in the example shown here the offset leaves the pads in each underlying die fully exposed. This configuration presents as a stairstep die stack, and electrical interconnections are made over the steps. 
     The stack is mounted on a support (for example, a package substrate) having a row  316  of bond sites  36  exposed at a die mount surface  39 . The bond sites are connected to (or constitute a part of) electrical circuitry (not shown in the FIGs.) in the support. The die stack is affixed to the die mount surface  39  of the substrate, and arranged so that the front sidewall  31   a  of a first die  34   a  is aligned along the row  316  of bond sites  36 . The coated back side of the first die may, as in these examples, directly contact the support surface  39  and may serve to affix the stack to the support. Optionally, a die attach film may be laminated onto the back side of the first die to serve to affix the stack to the support. 
     The die are electrically interconnected (die-to-die) in the stack, and the stack is electrically connected to the support, by traces  318  of an interconnect material disposed in contact with die pads and bond pads. The interconnect material may be an electrically conductive polymer, such as a polymer matrix containing particles of an electrically conductive material. The material may a curable polymer, for example, such as electrically conductive epoxy (for example, a silver filled epoxy); and the interconnection may be made by forming traces of the uncured material in a prescribed pattern and thereafter curing the polymer to secure the electrical contacts with the die pads and the bond sites, and to ensure the mechanical integrity of the traces between them. 
       FIG. 3C  shows a portion (indicated by the broken outline  3 C in  FIG. 3B ) of a stack as in  FIGS. 3A and 3B  enlarged. The die are covered on all surfaces by an electrically insulative conformal coating; that is, for example, the back surface  33   a , the front surface  35   a , and the sidewall  31   a  of die  34   a  are covered by conformal coating  37 . The coating is provided with openings exposing the interconnect pads  32   a . The die are offset; that is, for example, the edge  311   b  of die  34   b  is set back (to the right in the FIG.) in relation to edge  311   a  of die  34   a  so that pad  32   a  on die  34   a  is exposed. The die stack is situated on the surface  39  of the support such that the edge  31   a  of the first (lowest) die  34   a  is aligned with the bond pad  36 , and the bond pad is at least partly exposed. The electrically conductive interconnect  318  contacts the bond pad  36 , the die pad  32   a , and the die pad  32   b  (and successive die pads in the overlying die), and it is disposed upon the coating  37 , which electrically insulates the interconnect from the underlying die surfaces. 
     Contacts of the electrically conductive interconnect with die pads and a bond pad formed as described above with reference to  FIGS. 3A ,  3 B,  3 C, may result in a satisfactory electrical die-to-die electrical interconnection, or die-to-support electrical connection. Where the pad pitch is very fine and the die pads and bonds pads are small, however, such constructs may be vulnerable to fatigue failure, in which electrical connections become unsatisfactory following repeated thermal cycling. Modeling the system (in some instances together with observation of failed interconnects) shows that the interconnects are under tension during or following thermal cycling, causing the conductive material to pull away (delaminate) from the pad, for example as suggested by the arrows A in  FIG. 3C , and to degrade or destroy the electrical continuity between the conductor and the pad. 
     Further, particularly where the interconnects are very thin, modeling the system (in some instances together with observation of failed interconnects) reveals cracks or breaks in the interconnects at the “inside corner” where the backside edge (e.g., edge  331   a  in  FIG. 3C ) of the lowermost die in the stack meets the underlying substrate. 
     As noted above, where the front side of the die is covered by an electrically insulative coating, pads on the die are made available for electrical connection by selectively removing the electrically insulative coating over the pads. When the interconnect material is deposited over the die in the stack, the material contacts only the exposed pads, and no electrical contact is made with pads (or with other die surfaces overlain by the interconnect material) that remain covered by the electrically insulative coating. In  FIGS. 3A ,  3 B,  3 C all the pads on all the die are shown as being exposed for electrical connection by the conductive traces and, accordingly, each of the pads in each die is in these examples electrically connected to pads on the other die in the stack and to a bond pad on the substrate. Depending upon the pad layout design on the die, it may not be desired to make electrical connection of all the pads on a given die with pads on other die or with circuitry in an underlying support. In such circumstances, the electrically insulative coating over selected ones of the pads on each die may be removed to expose the selected pads, and the coating may be left in place on pads to which electrical connection is not desired. This may be referred to as a “subtractive procedure” for making pads selectively available for electrical contact. Or, alternatively, in an “additive procedure”, an electrically insulative coating may be applied selectively to areas over which the electrical traces may be formed, at which no electrical contact is intended. 
     Some types of interconnect failure can result from transverse cracks in the trace itself, which typically propagate from a surface of the trace material, and which may occur during or following molding or encapsulation, such as during thermal testing or during thermal cycling in use. Accordingly, in another approach, particularly for example where the assembly is to be molded or encapsulated, the interconnect traces can be coated with a film of a material such as a polymer (for example, a parylene or a silicone rubber) prior to the encapsulating or molding procedure. A silicone rubber such as a room-temperature-vulcanizing silicone elastomer, can be suitable, these are available for example from Dow Corning. A film of such a material having a thickness about ½ mil (about 10 um), for example, may suffice to mitigate crack formation. Apparently (without limiting the invention) the film provides a sort of relief or lubrication at the interface of the interconnect material and the molding material or encapsulant, and thereby reduces stresses that may result in crack formation. Other materials can be selected to provide such stress relief or lubrication. 
     An assembly made using a subtractive procedure for making pads selectively available for connection is illustrated in  FIGS. 4A ,  4 B.  FIG. 4A  shows by way of example a portion near the interconnect edge of an 8-die offset stack in a plan view. Each die has a row  49  of pads (e.g., pads  48 ;  32  pads in this example). The pads may be referenced by numbers  1  through n ( 1 - 32  in this example) according to the pad locations, as suggested by the numerals in parentheses ( 1 ), ( 2 ), ( 3 ) . . . ( 30 ), ( 31 ), ( 32 ) aligned with the pad positions on die  40 . The die are stacked one over another and offset so that the interconnect edge of each die (except the lowermost die) is set back with respect to the interconnect edge of the die underlying it. The die are arranged in the stack so that corresponding pad locations are aligned in columns. The stack is mounted on a support (here a substrate)  400  having interconnect sites (bond pads or leads)  46 . The lowermost die in the stack is oriented with the substrate so that the stack edge (that is, the lower die interconnect edge) overlaps the leads on the substrate, and so that the pad columns are aligned with the leads, so in this example there is no interconnect span dimension next to the stack. 
     The die stack in this example is covered with a conformal insulative coating  47  (of a material such as for example a parylene). Openings through the conformal coating were made (for example by laser ablation) to expose selected interconnect die pads (pads  48 , for example), while leaving selected other interconnect die pads protected (electrically insulated). 
       FIGS. 4A ,  4 B show the interconnect portion of an 8-die offset stack, electrically interconnected with interconnect traces formed over the pad columns (e.g., traces  418  over columns ( 1 ), ( 2 ), ( 3 )).  FIG. 4B  is a sectional view thru the construct of  FIG. 4A  at the pad location ( 2 ) column, as indicated at B-B in  FIG. 4A . In this column, the pads in the upper four die (e.g., pad  48  in the fourth die from the top), and the bond pad  46  on the substrate, are exposed by openings in the conformal insulative coating; and the pads in the lower four die (as well as an area of the front side inboard from the pads on the top die, and the outboard area of the substrate) are left covered. The exposed pads are available for electrical connection by the interconnect trace formed over them, while the covered pads (and other covered surfaces) are insulated from contact with any overlying electrical traces. The traces  418  electrically connect exposed die pads in the column (e.g., pad  48 ) to other exposed die pads in the column and to a corresponding interconnect site  46  on the substrate  400 . Pads that remain covered by the insulative coating and other die surfaces overlain by the interconnect material are not electrically connected. 
     The interconnect material is a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. To form the traces, the stack of die may be supported, for example, at the back side of the lowest of the die in the stack, and the interconnect material may be applied along a trajectory over the pads to be connected and the die surfaces between them. The interconnect material may be applied using an application tool such as, for example, a syringe or a nozzle. The material exits the tool in a deposition direction generally toward the interconnect terminals, and the tool is moved over the die stack face in a work direction. The material is deposited while the tool is moved. The material may be extruded from the tool in a continuous flow, or, the material may exit the tool dropwise. The material may exit the tool as a jet of droplets, and is deposited as dots which coalesce upon or following contact with a stack face surface. The droplets may be very small, and may exit the tool as an aerosol spray. 
     The interconnect material may be an electrically conductive polymer, such as a polymer filled with particles of an electrically conductive material. The material may be a curable polymer, for example, such as electrically conductive epoxy (for example, as silver filled epoxy); and, the interconnect process may include forming traces of the uncured material in a prescribed pattern and thereafter curing the polymer to secure the electrical contacts with the terminals and to secure the mechanical integrity of the traces between them. Or, the interconnect material may be an electrically conductive ink. 
       FIG. 5  illustrates an example of an assembly in which the bottom die  51  in the stack has a greater thickness than the other die  52 ,  53 ,  54 ,  55 ,  56 ,  57 ,  58  in the stack. Many details are omitted from the drawing for clarity of presentation. For example, die attach films may be employed, and a conformal dielectric coating (or other electrical insulation) may be provided over surfaces not intended to be electrically connected to overlying electrically conductive traces. Also, the interconnect traces are not shown in this drawing. The die  52 ,  53 ,  54 ,  55 ,  56 ,  57 ,  58  may have been singulated form a wafer that was thinned (for example in a backgrinding operation) to a desired thinness; and the die  51  may have been singulated from a wafer that was thinned to a greater thickness than the others. The bottom die may have the same (or similar) functionality as the other die in the stack; for example all the die in this stack may be memory die. Or, the bottom die may have a functionality different from that of the other die in the stack; for example the thicker bottom die may be a processor die, and the other die may be memory die. Other die functionalities are contemplated, according to the desired function of the completed assembly. The greater thickness of the bottom die provides increased stiffness to the stack, and can help to reduce warping or bending. What thickness may be required for the bottom die may depend upon, among other factors, the overall dimensions of the package, the thinness of the other die, and the extent of the CTE mismatch in the various components of the assembly. 
       FIGS. 6A ,  6 B and  6 C illustrate examples of stacked die assemblies in which a nonfunctional die is situated between the lowest functional die in the stack and the substrate. In  FIG. 6A , for example, the nonfunctional die  60  is a “dummy” die; that is, it has no electronic functionality. In this example an 8-die stack of die  51 ,  52 ,  53 ,  54 ,  55 ,  56 ,  57 ,  58  is mounted over the dummy die. An effect of the dummy die is to raise the horizon of the die pads (that is, the interconnect edge) on the lowest functional die  51  in relation to the bond pads on the substrate  500 . 
     In  FIG. 6B , for example, the nonfunctional die  62  has electronic circuitry and peripheral die pads and it may be configured substantially the same as the lowest functional die  51  in the stack. In this example the die pads on the nonfunctional die  62  are disabled, as symbolized in the drawing by the “X” over the pad. The pad may be, for example covered by a dielectric material, so that the additional die is not electrically connected to overlying interconnect traces. Or, for example the electrical connection of the pad to the circuitry on the die may be severed. 
     In the examples of  FIGS. 6A and 6B , the nonfunctional die is an additional die; that is, the nonfunctional is interposed between the die stack and the substrate. The example in  FIG. 6C  is similar to that in  FIG. 6B , except that here the nonfunctional die  61  is the lowermost die of the die stack itself, disabled in a manner for example as described above with reference to  FIG. 6B . Because the lowermost die in the stack may have been fully functional before it was disabled, the die  61  may be referred to as a “sacrificial” die. 
       FIGS. 7A ,  7 B and  7 C illustrate examples of stacked die assemblies in which zones near the corners of the die are left free of electrical connection. In some configurations, illustrated for example in  FIG. 7A , the “keepout” zones  72  may constitute portions of the interconnect margin of the die at which no pads are situated. As noted above, this arrangement may designed into the placement of pads in a rerouting pattern; or, this arrangement may result during the die singulation process, by cutting the die wider than would be minimally required for the circuitry and the pad arrangement. 
     In some configurations, illustrated for example in  FIG. 7B , the “keepout” zones  74  constitute disabling interconnection to pads at one or a few die pad positions (“sacrificial pad positions”) near the affected corner; in the illustrated example the die pads in the sacrificial pad positions ( 1 ), ( 2 ), ( 3 ), and ( 30 ), ( 31 ), ( 32 ) are covered by a dielectric material (and no openings are formed over these columns of pads), so that the die is not electrically connected to overlying interconnect traces in the keepout zones. 
     In some configurations, illustrated for example in  FIG. 7C , the “keepout” zones  76  are established not by disabling pads on the die, but in disabling bond pads at the corresponding positions on the substrate, or by designing the substrate so that no bond pads are located there. In the example illustrated, the bond pads in the keepout zones  76  remain covered by the substrate surface solder mask, or other substrate surface insulation. 
       FIGS. 8A ,  8 B,  8 C illustrate examples of stacked die assemblies in which an underfill is formed near one or more edges of the bottom die between the bottom die in the stack and the substrate. The underfill reinforces the adhesion of the die stack to the substrate, and helps prevent or reduce delamination along the edge. 
     An underfill is illustrated for example in  FIG. 8A . Each of the die  51 ,  52 ,  53 ,  54 ,  55 ,  56 ,  57 ,  58  in the stack here is affixed to the underlying die (or to the substrate) by a die attach film; for example, film  518  affixes die  58  to the underlying die  57 , and film  511  affixes die  51  to the substrate  500 . Die attach film  511  is dimensioned so that some space between the die and the substrate is left unfilled by the film, adjacent the interconnect die edge. In the approach illustrated here, a quantity of underfill material is deposited at the die edge, and flows into this space, as shown at  82  in  FIG. 8A , and may form a “fillet”  83  at the die sidewall. 
     The underfill may be applied in particular spots, at intervals along an edge, as illustrated for example in  FIG. 8B , or continuously along an edge. In  FIG. 8B , an electrically non-conductive underfill material is deposited at spots along the die interconnect sidewall, e.g. spots  83 , generally between the bond pads, e.g., bond pads  85 . As is characteristic of underfill materials, the underfill once deposited may flow into any space between the bottom die and the substrate. 
     In  FIG. 8C , an underfill material is deposited at spots, e.g. spots  86 , along the bottom die edge, near the corners of the bottom die. As is characteristic of underfill materials, the underfill once deposited may flow into any space between the bottom die and the substrate. 
     In other configurations an underfill is deposited in a continuous line along one or more of the non-interconnect sidewalls. Where an electrically conductive underfill is used, it can be deposited at any location where the underfill will not cause electrical shorting. The underfill approach can be employed for die stacks in which the die are offset, as illustrated here; or for die stacks where each die in the stack is smaller in at least one dimension that the die beneath (pyramid stack), or in stacks where successive die in the stack are staggered and may be rotated. Such configurations are described, for example, in U.S. application Ser. No. 12/124,077, referenced above. 
     Electrically conductive or electrically nonconductive underfill materials may be used. Where an electrically conductive underfill is used, it can be deposited at any location where the underfill will not cause electrical shorting. The underfill material may be applied using standard equipment, and may be applied either prior to or subsequent to formation of the electrical interconnect traces. 
       FIGS. 9A ,  9 B and  9 C illustrate examples of stacked die assemblies in which an underfill material is deposited to form a fillet at the inside angle formed by a die sidewall and an underlying surface.  FIG. 9A  illustrates a configuration in which the die sidewall is the interconnect sidewall  94  of an upper die  93 , and the underlying surface is an electrically insulated area  96  of the front side of an underlying die  52 , inboard of the die pads on the underlying die and adjacent the upper die sidewall. The deposited underfill material forms a fillet  90  which provides a gradually sloping surface extending from the upper die interconnect edge to the underlying die surface inboard from the die pads, on which an electrical interconnect trace  91  can be formed, electrically connecting the pads on the upper die  53  and the underlying die  52  (and connecting additional die, e.g., die  51  as appropriate) to circuitry in the substrate  500 . 
     A standard underfill material can be used, and it can be deposited using standard equipment for applying underfill. Preferred underfill material may be high modulus materials, having good CTE matching with other materials in the assembly. By way of example, one suitable standard underfill material is marketed under the name Namics U8439-1. 
       FIG. 9B  shows a configuration in which die  51  and  52  are mounted die-up over a flip-chip die  91  mounted die-down on the substrate  500 , and in which an underfill fillet  900  is formed at the inside angle formed by sidewalls  914 ,  924  of the die  51  and the flip chip die  91 , and the surface  916  of the underlying substrate  500  inboard from the bond pads. In this example an additional fillet  902  is formed at the inside angles formed by the interconnect sidewall of the die  52  and the surface of the underlying die  51  inboard from the bond pads. The fillets  900 ,  902  provide a gradually sloping surface extending from the upper die  52  interconnect edge to the underlying die surface inboard from the die pads, and then from the die  51  interconnect edge to the underlying substrate surface inboard from the bond pads, on which an electrical interconnect trace  911  can be formed, electrically connecting the pads on the upper die  52  and the underlying die  51  to circuitry in the substrate  500 . 
       FIG. 9C  shows a further example, in which an underfill fillet  932  is formed at the inside angle formed between an interconnect sidewall of a die  53  and a surface of an underlying die  52 ; and an underfill fillet  934  is formed at the inside angle formed between an interconnect sidewall of a bottom die  51  and a surface of the underlying substrate  500 ; and an interconnect trace  931  is deposited on the fillet  934  to connect the bottom die  51  to a first row of bond pads on the substrate  550 ; and thereafter an underfill fillet  936  is formed over the fillet  934  and the trace  931 ,; and thereafter an interconnect trace  941  is formed over the fillet  932  and the fillet  936  to connect the upper die  53  to the die  52  and to a second, outboard, row of bond pads on the substrate  500 . 
     The underfill may be formed so that it forms a fillet approximating a right triangular shape in transverse section; viewed in this way the hypotenuse of the triangle shape is a sloping surface over which an interconnect trace can be formed; and a vertical side of the triangle forms an angle with the hypotenuse at or near the upper die interconnect edge. The sloping surface of the fillet may be slightly concave or convex, or may be a more complex slightly curved surface. The underfill can be CTE matched, to help stabilize the assembly, reducing delamination effects. Moreover, the underfill, shaped as described above, can provide a gradual transition from die-to-die or from die-to-substrate, eliminating abrupt angular (approximately right-angle) transitions at the interconnect edges of the die and at the inside corners where the back edge of the die sidewall meets the underlying surface. In some configurations, a first underfill fillet formed at the sidewall of a bottom die and a substrate can support a first set of electrical interconnect traces connecting pads on the bottom die with bond pads in a first row on the substrate; and an additional underfill fillet formed over the first interconnect traces on the first fillet at the sidewall of an upper die and the bottom die can support a second set of interconnect traces from die pads on the upper die to bond pads in a second row, outboard from the first row, on the substrate. 
       FIGS. 10A and 10B  illustrate examples of approaches to assist in constraining the flow (“run-out” or “bleed”) of the underfill material over the substrate.  FIG. 10A  is presented in a partial sectional view similar to that of  FIG. 9B , in part; and  FIG. 10B  is presented in a partial plan view, in which the sectional view of  FIG. 10A  is indicated by the arrow A-A. These FIGs. show a configuration in which a die  51  is mounted die-up over a flip-chip die  91  mounted die-down on a die attach side of the substrate  1000 , and in which an underfill fillet  1900  is formed at the inside angle formed by sidewalls  914 ,  924  of the die  51  and the flip chip die  91 , and the surface  1916  of the underlying substrate  1000  inboard from the bond pads  1020 . The fillets  1900  provides a gradually sloping surface extending from an upper die (out of the frame of the drawing) to the underlying surface of die  51  inboard from the die pads  5120 , and then from the die  51  interconnect edge to the underlying substrate surface inboard from the bond pads  1020 , on which an electrical interconnect trace  1021  can be formed, electrically connecting the pads on the upper die and the die  51  to circuitry in the substrate  1020 . 
     The die attach side of the substrate  1000  is covered by a solder mask  1010 , and a trench having trench walls  1013  through the solder mask  1010  exposes bond pads  1020  on the substrate  1000  for connection. 
     These FIGs. illustrate an example of an approach for limiting the bleed or run-out of the underfill material over the substrate surface, in which the die attach side of the substrate  1000  is covered by a solder mask  1010 . In this example the trench in the solder mask has trench walls  1013 ,  1013 ′, and at least trench wall  1013 , nearer the die, is situated generally parallel to the row of bond pads on the substrate (and generally parallel to the interconnect sidewall of the die). During deposition of the underflow material, the advancing front of the flowing material halts substantially at the edge of the trench wall  1013 , as indicated at  1023 . That is, the trench wall  1013  prevent run-out or bleed of the underfill material over the bond pads  1020  that are exposed within the trench. 
       FIG. 10B  additionally illustrates an example of an additional approach to limiting the bleed or run-out of the underfill material over the substrate surface. (This approach may be used whether or not the substrate has a solder mask, and may be used either without the trench approach or in addition to it.) In this example a dam  1030 ,  1030 ′ is provided at the location of each side of the underfill fillet prior to depositing the underfill material, to limit or prevent flow of the underfill material laterally, that is, in directions generally parallel to the row of die pads. 
     The dam material may be a curable material applicable in a flowable form and thereafter cured or allowed to cure, and the dam material may have properties that make it generally less likely than the underfill material to flow (run-out or bleed) when in an uncured state. The dam material may have a higher viscosity, for example, than the underfill material. The dam material and the underfill material may be cured in the same cure procedure, or the dam material may be cured in an earlier cure procedure. 
     Any of various materials may be employed for the dam, having properties suitable for the particular underfill material. In a particular example, the underfill can be one marketed by Namics Corporation under the name “Chipcoat”, such as the “Chipcoat U8439-1”. And for such an underfill a suitable dam material can be one marketed by Lord Thermoset under the name “CircuitSAF™”, such as the “CircuitSAF™ ME-456”. This dam material, applied prior to depositing the underflow material, prevents or limits lateral flow of this underfill material; and both materials can be cured in one cure procedure, which may be for example heating the assembly at 165° C. for about 1 hour. Other suitable materials may be selected without undue experimentation. 
     Other embodiments are within the claims.