Abstract:
Apparatus for monitoring the fault current in the ground conductor of a polyphase AC electrical power system. When the fault current exceeds a predetermined level, the magnetic field produced causes a magnetic reed switch to close and open at twice the AC frequency. Pulse producing circuitry connected to the reed switch responds to the switch action to produce pulses at the same frequency. The pulses are counted by logic circuitry, and when a predetermined number of pulses have been counted, an output signal triggers circuitry which trips circuit breaker apparatus in the power system. The delay period between first detecting the fault current and tripping of the circuit breaker apparatus can be adjusted by changing the number of pulses to be counted by the logic circuitry before it produces an output signal.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to apparatus for monitoring current flow in a power supply line. More particularly, it is concerned with apparatus for monitoring the flow of current in the ground conductor of a polyphase AC electrical power system. 
     It is a common practice to monitor current flow in the ground conductor of a three-phase electrical system and to trip circuit breakers protecting the load connected to the system when the current flow exceeds certain predetermined limits. It is often desirable to introduce a delay in order to avoid nuisance tripping due to transient conditions. The delay period may be variable to permit adjustments for particular situations. 
     One form of apparatus for monitoring the current in a ground conductor employs a fault current sensor which includes a normally open magnetic reed switch. The magnetic flux produced by a fault current in the conductor causes the switch to close and open at twice the frequency of the current. While the switch is closed, the capacitance in a resistance-capacitance circuit is charged by a constant current source. The capacitance is connected to a switching transistor, and when the voltage across the capacitance is sufficient, the transistor turns on causing circuit breaker apparatus coupled thereto to trip. The time required to charge the capacitance may be varied by changing the value of the resistance, thereby varying the delay period. 
     With the foregoing apparatus it is difficult to obtain an accurately controlled delay period. There is a problem in matching the values of the resistance, the capacitance, and the source of constant current. In addition, individual component values may vary over the operating temperature range encountered. Since the portions of a cycle during which the contacts of the reed switch are closed (the duty factor) depends upon the magnitude of the fault current and because of contact bouncing, the length of time the contacts close varies. Calibration of the delay period is thus a serious problem. Testing and calibration in the field are particularly difficult. 
     SUMMARY OF THE INVENTION 
     Improved current monitoring apparatus in accordance with the present invention for monitoring current flow in a power supply line includes current sensing means coupled to the power supply line. The current sensing means has a pair of terminals and a switch which is connected between the terminals. The current sensing means alternately closes and opens the switch between the terminals at a predetermined frequency while the electrical current flowing in the power supply line exceeds a predetermined level. A pulse producing means is coupled to the terminals of the current sensing means for producing switching pulses at the same predetermined frequency in response to the closing and opening of the switch at that frequency. A counting means is coupled to the pulse producing means for counting switching pulses therefrom and produces an output signal at an output terminal in response to counting a selected predetermined number of switching pulses from the pulse producing means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The single FIGURE of the drawing is a schematic circuit diagram of current monitoring apparatus in accordance with the present invention employed with circuit breaker apparatus to provide protection for a load in a three-phase power system. 
     For a better understanding of the present invention, together with other and further objects, advantages, and capabilities thereof, reference is made to the following discussion and appended claims in connection with the above-described drawing. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The FIGURE is a schematic circuit diagram illustrating apparatus in accordance with the present invention employed in conjunction with a three phase AC electrical power system 10 connected to a load 11. The system also includes a ground or neutral conductor 12 which is connected to ground. The load 11 is protected by a suitable circuit breaker apparatus as indicated at 13 which, as shown, includes a shunt trip coil 14. 
     A current sensor 20 is coupled to the ground conductor 12. The current sensor 20 includes a magnetic reed switch having normally open contacts which close when the switch is subjected to sufficiently high magnetic flux. The amount of magnetic flux produced depends on the current in the conductor 12. By varying the orientation of the reed switch with respect to the ground conductor 12 the portion of the magnetic flux to which it is subjected is varied. Thus, the current level required to close the switch can be varied by varying the orientation of the switch. Since the switch closes each time the instantaneous magnetic flux exceeds a predetermined level, the switch closes and opens at a frequency which is twice the frequency of the line current. Thus, for a 60 Hz current the switch closes and opens at a frequency of 120 Hz. 
     The apparatus as shown includes a power supply section 19 for providing operating voltages to the various components. The primary winding of a transformer 21 is connected to an AC power line, specifically to a 120 volts 60 Hz line. The secondary winding of the transformer is connected to a full-wave rectifier bridge 22 of four diodes. The output of the full-wave rectifier bridge 22 is connected through a current limiting resistance R18 to provide voltage source V++. An indicator lamp 24 and a current limiting resistance R19 are connected between the voltage source V++ and ground. An L-section filter of a capacitance C4 and a resistance R20 is shunted with a zener diode 25 to provide a regulated voltage source V+. A reference voltage V REF  is taken from the voltage divider of resistances R12 and R11. 
     The switch of the current sensor 20 is connected between two terminals 20a and 20b. One terminal 20a is connected directly to ground and the other terminal 20b is connected to voltage source V+ through resistances R1 and R2. The juncture of resistances R1 and R2 is connected to ground through a capacitance C1 which serves to minimize and absorb spurious transient spikes. 
     The juncture of resistances R1 and R2 is connected through a resistance R9 to the + input of a comparator 31. The - input of the comparator 31 is connected to the V REF  source through a resistance R10. The output of the comparator 31 is connected to an integrator 37 which includes the voltage source V+ connected through a resistance R15 to the output and a capacitance C3 connected between the output and ground. The integrator 37 has a time constant of about 1 to 2 milliseconds and serves to eliminate the effects of contact bounce upon closing of the switch in the sensor 20. The output of the comparator 31 is relatively high when the switch in the sensor 20 is open, and is relatively low when the switch is closed. The integrator 37 insures that when the switch in the sensor 20 alternately closes and opens because of excessive fault current, a series of negative-going pulses at a frequency of 120 Hz is produced at the output. 
     The output of the comparator 31 is applied as the clock input to a divider 32. The divider 32 may be formed by appropriately interconnecting counting circuits to provide, for example, a divide-by-12 arrangement which produces one output pulse for every 12 input pulses received. Thus, an output pulse is produced every 0.1 second in response to input pulses at a frequency of 120 Hz. The output of the divider 32 is applied to the clock input of a decoder 33. The decoder 33 has several output connections and an output signal is produced at each output connection in turn as determined by the number of pulses received from the divider 32. That is, the input signal from the decoder 33 steps from one output connection to the next one in turn in response to each input pulse. Thus, with ten output connections the output signal steps at 0.1 second intervals covering a range from 0.1 to 1.0 seconds. The divider 32 and decoder 33 each have reset connections, and each is reset to an initial state by a relatively high voltage applied thereto. 
     As illustrated schematically in the FIGURE, any one of the output connections of the decoder 33 may be selected by the setting of a selector switch 34. The output terminal of the switch 34 is coupled to the base of an NPN output transistor 23 by way of a resistance R24. The collector of the transistor is connected to the voltage source V++ through a resistance R21 and the emitter is connected through a resistance R22 to ground. The emitter of the transistor 23 is connected to the gate of a triac 35. The triac 35 is connected in a series circuit with the shunt trip coil 14 of the circuit breaker apparatus 13. When an output signal occurs at the selected output connection of the decoder 33, the output transistor 23 conducts firing the triac 35. The resulting current flow through the shunt trip coil 14 trips the circuit breaker apparatus 13 disconnecting the load from the electrical power system 10. 
     The apparatus also includes inhibiting circuitry of a comparator 41 having its + input connected through a resistance R7 to the juncture of resistances R1 and R2 and its - input connected to the V REF  source through a resistance R8. The output of the comparator 41 is connected to an integrator 43 of a resistance R13 connected to the voltage source V+ and a capacitance C2 connected to ground. The integrator 43 has a time constant of approximately 23 milliseconds during which the output of the comparator 41 remains low after a relatively low input voltage is terminated by the opening of the switch of the sensor 20. Thus, so long as the sensor switch closes and opens continuously at the 120 Hz frequency, the voltage level at the output of the comparator 41 remains low. The output of the comparator 41 is applied through a resistance R14 to the + input of another comparator 42. The - input of the comparator 42 is connected through a resistance R16 to the reference voltage V REF . The output of the comparator 42 is connected to the V+ voltage source through a resistance R17 and to the reset connections of the divider 32 and the decoder 33. The output of the comparator 42 is low when the output of the comparator 41 is low, that is when the switch of the sensor 20 is closed. When the switch of the sensor 20 is open for a period longer than the time constant of the integrator 43, the output of the comparator 42 is relatively high producing a reset signal at the reset connections of the divider 32 and the decoder 33. The reset signal resets the divider 32 and the decoder 33 to their initial states. They remain in their initial states prevented from responding to pulses at their clock inputs until the reset signal terminates. 
     Thus, when current flow in the ground conductor 12 is such that the instantaneous current produces a magnetic field sufficient to cause the switch in the sensor 20 to close, the switch closes and opens at a frequency of 120 Hz. Pulse producing circuitry coupled to the switch including the integrator 37 produces pulses at the clock input of the divide-by-12 divider 32. The inhibiting circuitry including the integrator 43 also responds to the closing and opening of the switch in the sensor 20 at the 120 HZ frequency to prevent a reset signal from being applied at the reset connections of the divider 32 and the decoder 33. The divider 32 applies output pulses to the decoder 33 at a frequency of 12 Hz. The decoder 33 responds to the received pulses to produce an output signal at each of its output terminals in turn. Thus, depending upon which of the ten output connections of the decoder 33 is selected by the setting of the selector switch 34, the delay period for an output signal to be produced at the output terminal of the switch 34 may be from 0.1 to 1.0 second subsequent to the first closing of the switch of the sensor 20. The output signal turns on the transistor 23 which in turn fires the triac 35 drawings current through the shunt trip coil 14 to trip the circuit breaker apparatus 13. If the switch does not continue to close and open near the 120 Hz frequency for the delay period, the inhibiting circuitry produces a reset signal resetting the divider 32 and the decoder 33 to their initial states. 
     The apparatus as shown also includes very simple testing circuitry for determining whether or not the apparatus is producing output signals with the correct delay periods. The test circuitry includes a full-wave rectifier bridge 51 of two diodes across the secondary winding of the transformer 21. The rectifier bridge is connected to ground through a voltage divider of resistances R3 and R4. The voltage divider is connected through a resistance R5 to the + input of a comparator 52. The - input of the comparator 52 is connected through a resistance R6 to the V REF  voltage source. The output of the comparator 52 is connected through a normally open pushbutton switch 53 to the terminal 20b of the switch of the sensor 20. The diode bridge 51 provides a 120 Hz pulse source to the comparator 52 which, therefore, produces output pulses at a frequency of 120 Hz. By closing the pushbutton switch 53 these pulses are applied to the comparators 31 and 41 simulating the closing and opening of the switch of the sensor 20. Thus, an operational check of the apparatus may be performed and the time delays at the output connections of the decoder 33 may be checked. 
     In one specific embodiment of the apparatus as described the V++ voltage was 17 volts, the V+ voltage was 12 volts, and the V REF  voltage was 6 volts. The comparators 31, 41, 42, and 52 were LM3302 comparators. The divider 32 employed interconnected CD4404 and CD4018 counters to form a divide-by-12 divider. The decoder was a CD4017 decoder. The NPN transistor 23 was a type MM3005, and the triac 35 was a type RCA40669. 
     Current monitoring apparatus as shown and described employs digital techniques rather than analog, with the timing information provided by the frequency of the current being monitored. Therefore problems of component matching, temperature compensation, tolerance errors, and switch duty factor are avoided. An accurate delay period is obtained and the delay period is easily changed. Circuit adjustments and lengthy calibration procedures are not required and testing in the field is extremely simple. 
     While there has been shown and described what is considered a preferred embodiment of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein with departing from the invention as defined by the appended claims.