Abstract:
A transmitter with compensating mechanism of pulling effect includes a correction unit and an output unit. The correction unit includes a memory circuit and a first address generation circuit. The memory circuit is configured to store a look up table, wherein the look up table stores correction data corresponding to an in-phase data signal, a quadrature data signal, and at least one system parameter. The first address generation circuit is configured to generate a first address according to the in-phase data signal, the quadrature data signal, and the at least one system parameter, in order to output a correction signal via the correction data. The output unit is configured to modulate the correction signal according to an oscillating signal to generate a modulated signal, and amplify the modulated signal to generate an output signal.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority to Taiwan Application Serial Number, 104144713, filed Dec. 31, 2015, which is herein incorporated by reference. 
       BACKGROUND 
       [0002]    Technical Field 
         [0003]    The present disclosure relates to a transmitter. More particularly, the present disclosure relates to a transmitter with an elimination mechanism of a pulling effect and an eliminating method thereof. 
         [0004]    Description of Related Art 
         [0005]    In various wireless communication systems, a transmitter can modulate the frequency, by using an oscillating signal generated from an oscillator, to generate a radio frequency signal that is suit for the wireless communication. However, as the sizes of transmitters become smaller and smaller, such radio frequency signals may be incidentally coupled back to the oscillator. As a result, a phase error may be introduced into the oscillating signal, and thus the overall performance of the transmitter is reduced. The aforementioned phenomenon is commonly known as the “pulling effect.” 
         [0006]    In some approaches, the calibration mechanism for eliminating the pulling effect is arranged subsequent to a mixer. As a result, the required bandwidth for such calibration mechanism may be too high. The cost and complexity of the transmitter are thus increased. In some other approaches, a calibration circuit for eliminating the pulling effect is arranged in a phase locked loop. As a result, unwanted phase noise may be introduced to reduce the performance of the transmitter. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
           [0008]      FIG. 1A  is a schematic diagram of some embodiments of a transmitter in the present disclosure. 
           [0009]      FIG. 1B  is a schematic diagram illustrating a mathematical model, for the transmitter in  FIG. 1A  occurring a pulling effect, in the time domain. 
           [0010]      FIG. 1C  is a schematic diagram illustrating a mathematical model of a correction matrix for eliminating the pulling effect. 
           [0011]      FIG. 2  is a schematic diagram of a transmitter in accordance with some embodiments of the present disclosure. 
           [0012]      FIG. 3A  is a schematic diagram of some embodiments of a correction unit. 
           [0013]      FIG. 3B  is a schematic diagram of some other embodiments of the correction unit. 
           [0014]      FIG. 4  is a schematic diagram of some other embodiments of the correction unit. 
           [0015]      FIG. 5A  is a schematic diagram of some yet another embodiments of the correction unit. 
           [0016]      FIG. 5B  is a schematic diagram of some embodiments of a correction calculation circuit. 
           [0017]      FIG. 6A  is a schematic diagram of some embodiments of an address generation circuit. 
           [0018]      FIG. 6B  is a schematic diagram of some embodiments of an address generation circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
         [0020]    As used herein, “signal A(t)” indicates a continuous signal in a form of the analog signal, “signal A[n]” indicates a discrete signal in a form of the digital signal, and corresponds to the signal A(t). For example, the signal A[n] can be converted, by a digital-to-analog converter, to the corresponding signal A(t). Similarly, in some other embodiments, the signal A(t) can be converted, by an analog-to-digital converter, to the corresponding signal A[n]. 
         [0021]      FIG. 1A  is a schematic diagram of some embodiments of a transmitter in the present disclosure. 
         [0022]    A digital-to-analog converter (DAC)  110  receives a baseband signal S DBB , and generates a corresponding analog signal S ABB  according to the baseband signal S DBB . A low pass filter  120  removes the images, which are introduced from the digital-to-analog transformation, on the analog signal S ABB . A voltage-controlled oscillator (VCO)  130  generates an oscillating signal S VCO  having a frequency f vco  to a local oscillating signal generator  140 . The local oscillating signal generator  140  thus divides the oscillating signal S VCO  to generate a local oscillating signal S LO  having a local frequency f LO  to a mixer  150 . The mixer  150  upconverts the filtered analog signal S ABB  according to the oscillating signal S LO , to output a modulation signal S VM . A power amplifier  160  amplifies the power of the modulation signal S VM  to generate an output signal S VO . An antenna  170  emits the output signal S VO . The output signal S VO  can be expressed as the following equation (1) in the time domain: 
         [0000]        S   VO   =GA   BB ( t )cos(ω LO   t+θ   BB ( t )+σ)  (1).
 
         [0023]    In the equation (1), G is an overall gain of the transmitter  100 , A BB (t) is the amplitude of the analog signal S ABB , ω LO  is a radian frequency corresponding to the local frequency f LO , θ BB (t) is the phase of the analog signal S ABB , and σ is an additional phase introduced during the baseband signal S DBB  passes the transmitter  100 . 
         [0024]    When the pulling effect is present in the VCO  130 , the output signal S VO  is able to be amended as the following equation (2): 
         [0000]        S   VO   =GA   BB ( t )cos(ω LO   t+θ   BB ( t )+σ+θ( t ))  (2),
 
         [0025]    where θ(t) is the phase error introduced from the pulling effect. If it is assumed that the additional phase σ is 0, and the gain G of the transmitter  100  is 1, the output signal S VO  can be further simplified as the following equation (3): 
         [0000]        S   VO   =A   BB ( t )cos(ω LO   t+θ   BB ( t )+( t ))  (3).
 
         [0026]    The equation (3) is expanded to obtain the following equation (4): 
         [0000]        S   VO   =[A   BB ( t )cos(θ BB ( t ))cos(θ( t ))cos(ω LO   t )]+[ A   BB ( t )sin(θ BB ( t ))cos(θ( t ))(−sin(ω LO   t )]+[ A   BB ( t )cos(θ BB ( t ))sin(θ( t ))(−sin(ω LO   t )]−[ A   BB ( t )sin(θ BB ( t ))sin(θ( t ))(cos(ω LO   t )]=[ I ( t )cos(θ( t ))cos(ω LO   t )+ Q ( t )cos(θ( t ))(−sin(ω LO   t ))]+[ I ( t )sin(θ( t ))(−sin(ω LO   t )− Q ( t )sin(θ( t ))(cos(ω LO   t ))]  (4)
 
         [0027]    where I(t)=S ABB (t)cos(θ BB (t)), and I(t) is an in-phase data signal corresponding to the baseband signal S DBB . Q(t)=S ABB (t)sin(θ BB (t)) and Q(t) is a quadrature data signal corresponding to the baseband signal S DBB . 
         [0028]      FIG. 1B  is a schematic diagram illustrating a mathematical model, for the transmitter  100  occurring the pulling effect, in the time domain. 
         [0029]      FIG. 1C  is a schematic diagram illustrating a mathematical model of a correction matrix for eliminating the pulling effect. With the mathematical model illustrated in  FIG. 1B , the present disclosure provides a correction method for eliminating the pulling effect as described as follows. 
         [0030]    In some embodiments, before being mixed, the analog signal S ABB  can be calibrated with the correction matrix  100 A in  FIG. 1C , to eliminate the phase error θ(t) introduced from the pulling effect. According to the respective mathematical models illustrated in  FIG. 1B  and  FIG. 1C , it can be obtained that the in-phase data signal I(t) and the quadrature data signal Q(t) are satisfied with the following equation (5): 
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         [0031]    Thus, according to the equation (5), the analog signal S ABB  is pre-processed by the correction matrix  100 A to eliminate the phase error θ( t ) introduced from the pulling effect. Explained in a different way, if the equation (5) is expressed as in a form of the complex function, as the following equation (6): 
         [0000]        I ′( t )+ jQ ′( t )=[ I ( t )+ Q ( t )] e   [−jθ(t)]   =[I ( t )+ Q ( t )][α( t )+ j β( t )]  (6)
 
         [0032]    where I′(t)+jQ′(t) is a correction signal, which is generated from processing of the correction matrix  100 A, a phase correction signal α(t) is cos(θ(t)), and a phase correction signal β(t) is −sin(θ(t)). Effectively, by using the correction matrix  100 A to pre-process the analog signal S ABB , a pre-phase correction signal φ(t) is able to be generated, in which φ(t)=−θ(t). As a result, when the correction signal I′(t)+jQ′(t) is mixed through the mixer  150 , the pre-phase correction signal φ(t) and the phase error θ(t) are canceled out each other. Accordingly, the impact of the pulling effect is thus eliminated. 
         [0033]      FIG. 2  is a schematic diagram of a transmitter in accordance with some embodiments of the present disclosure. As shown in  FIG. 2 , the transmitter  200  includes a correction unit  220  and an output unit  240 . The output unit  240  includes the DAC  110 , the low pass filter  120 , the VCO  130 , the local oscillating signal generator  140 , the mixer  150 , the power amplifier  160 , and the antenna  170 , as mentioned in  FIG. 1A  above. The repetitious descriptions regarding related functions and operations of the output unit  240  are thus not given here. 
         [0034]    The correction unit  220  includes a memory circuit  222  and an address generation circuit  224 . The memory circuit  222  may be a register or a random access memory. The memory circuit  222  stores at least one look up table, which stores correction data corresponding to the in-phase data signal I[n], the quadrature data signal Q[n], and a least one parameter g. 
         [0035]    With reference to the related descriptions and  FIG. 3  of a reference document (Pulling Mitigation in Wireless Transmitters IEEE JSSC vol. 49, NO. 9, September 2014.), the phase error θ(t) is related to the baseband signal S DBB . The analog signal S ABB , which the baseband signal S DBB  corresponds to, is able to be linearly superposed of the in-phase data signal I(t) and the quadrature data signal Q(t). In other words, S ABB =I(t)+jQ(t). According to  FIG. 3  of the reference document and the equation (6), the pre-phase correction signal φ(t) can be expressed as the following equation (7) after the coordinate transformation: 
         [0000]      φ[ n]=C 1( I   2   [N]−Q   2   [N ])+ C 2(2 I[n]Q[n ])  (7).
 
         [0036]    In the equation (7), the coefficients C 1  and C 2  are related to the system parameter g (e.g., the output power of the power amplifier  160  and the operating temperature of the transmitter  200 ). Thus, according to the equations (6) and (7) above, different system parameters g, the in-phase data signal I[n], and the quadrature data signal Q[n] can be calculated or a desired correction signal I′[n]+jQ′[n] may be measured in advance, in order to be stored as the aforementioned correction data. The detailed descriptions regarding the correction data will be provided in paragraphs below. 
         [0037]    The address generation circuit  224  generates a corresponding address AD according to the in-phase data signal I[n], the quadrature data signal Q[n], and the system parameters g, so as to search the correction data from the look up table, and then output the correction signal I′[n]+jQ′[n] to the output unit  240 . 
         [0038]    The following paragraphs provide various embodiments to illustrate functions and applications of the equation (7). It is noted that, for clearer illustration, drawings of following embodiments are presented in a form of the complex function to described relationships between the baseband signal S DBB , i.e., I[n]+jQ[n], and each circuit. A person skilled in the art might adjust the implementations of the correction unit  220  according to each drawing, and thus the present disclosure is not limited to the following embodiments. 
         [0039]      FIG. 3A  is a schematic diagram of some embodiments of the correction unit. As shown in  FIG. 3A , in this example, the memory circuit  222  stores a look up table  222 A and a look up table  222 B. The correction data of the look table  222 A store predetermined in-phase data values I 0 [n] and the correction data of the look table  222 B store predetermined quadrature data values Q 0 [n]. The address generation circuit  224  generates the corresponding address according the currently-received in-phase data signal I[n] and quadrature data signal Q[n], and the system parameter g, so as to select a corresponding in-phase data value I 0 [n] and a corresponding quadrature data value Q 0 [n] from the look up tables  222 A and  222 B, respectively. Accordingly, a corresponding compensation signal I 0 [n]+jQ 0 [n] is generated to be output as the correction signal I′[n]+jQ′[n] to the output unit  240 . 
         [0040]    Effectively, in this example, with a calculation of the equation (6) in advance, the correction data of the memory circuit  222  stores multiple groups of the predetermined compensation signals I 0 [n]+jQ 0 [n]. The address generation circuit  224  may select a corresponding one group of compensation signal I 0 [n]+jQ 0 [n], and output the same as the correction signal I′[n]+jQ′[n]. 
         [0041]      FIG. 3B  is a schematic diagram of some other embodiments of the correction unit  300 A. The correction unit  300 A further includes delay circuits  320 , address generation circuits  224 , look up tables  222 A and  222 B, and an adder  340 . 
         [0042]    As shown in  FIG. 3B , the delay circuits  320  are coupled in series to sequentially output previous in-phase data signals I[n−1]−I[n−L] and previous quadrature data signals Q[n−1]−Q[n−L] according to the in-phase data signal I[n] and the quadrature data signal Q[n]. The address generation circuits  224  receive previous baseband signals I[n−1]+jQ[n−1]−I[n−L]+jQ[n−L], respectively. Accordingly, each of the address generation circuits  224  is able to generate a corresponding address AD according to the received baseband signal I[n]+jQ[n] or the previous baseband signals I[n−1]+jQ[n−1]−I[n−L]+jQ[n−L], so as to select the compensation signals I 0 [n]+jQ 0 [n]−I L [n]+jQ L [n] from the corresponding look up tables  222 A and  222 B. The adder  340  sums up the compensation signals I 0 [n]+jQ 0 [n]−I L [n]+jQ L [n] to generate the correction signal I′[n]+Q′[n]. 
         [0043]    Compared to  FIG. 3A , an impact of memory effect in a wideband system is further taken into account via the correction unit  300 A. By utilizing multiple groups of the look up tables  222 A and  222 B, which correspond to the baseband signal received at pervious L times, the correction unit  300 A can eliminate the total phase error introduced in the previous L times of the VCO  130 . As a result, the performance of the transmitter  200  can be further improved. 
         [0044]      FIG. 4  is a schematic diagram of some other embodiments of a correction unit  400 . Compared with  FIG. 3B , the correction unit  400  further includes multipliers  410 . In this example, the correction data of the look up table  222 A store predetermined phase correction signals α[n]−α[n−L], respectively. The correction data of the look up tables  222 B store predetermined phase correction data signals β[n]−β[n−L], respectively. Accordingly, the address generation circuits  224  generate corresponding addresses AD according to the received baseband signal I[n]+jQ[n], the previous baseband signals I[n−1]+jQ[n−1]−I[n−L]+jQ[n−L], and the system parameter g, to select the corresponding phase correction signals α[n]−α[n−L] and β[n]−β[n−L] from the corresponding look up tables  222 A and  222 B. The pre-compensation signals α[n]+jβ[n]−α[n−L]+jβ[n−L] are then outputted from the corresponding look up tables  222 A and  222 B. The multipliers  410  multiply the baseband signal I[n]+jQ[n] with the pre-compensation signal α[n]+jβ[n], and multiply the previous baseband signal I[n−1]+jQ[n−1]−I[n−L]+jQ[n−L] with the pre-compensation signals α[n−1]+jp[n−1]−α[n−L]+jp[n−L] respectively to generate the compensation signals I 0 [n]+jQ 0 [n]−I L [n]+jQ L [n]. The adder  340  sums up the compensation signals I 0 [n]+jQ 0 [n]−I L [n]+jQ L [n] to generate the correction signal I′[n]+jQ′[n]. 
         [0045]    In some embodiments, the correction unit  400  may also utilize the arrangement illustrated in  FIG. 3A . In other words, with a single multiplier  410 , a signal address generation circuit  224 , a single look up table  222 A and  222 B, the compensation signal I 0 [n]+jQ 0 [n] is generated according to the baseband signal I[n]+jQ[n], and is output as the correction signal I′[n]+jQ′[n] to the output unit  240 . The descriptions of the related operations are similar with the paragraphs above, and thus the repetitious descriptions are not given here. 
         [0046]      FIG. 5A  is a schematic diagram of some yet another embodiments of a correction unit  500 . Compared with  FIG. 4 , the correction unit  500  further includes correction calculation circuits  510 . The look up tables  222 A of the correction unit  500  store predetermined coefficients C 1  [n]−C 1 [n−L], and the look up tables  222 B store predetermined coefficients C 2 [n]−C 2 [n−L]. The address generation circuits  224  generate corresponding addresses AD according to the received baseband signal I[n]+jQ[n], the previous baseband signals I[n−1]+jQ[n−1]−I[n−L]+jQ[n−L], and the system parameter g, to select the corresponding coefficients C 1 [n]−C 1 [n−L] and C 2 [n]−C 2 [n−L] from the corresponding look up tables  222 A and  222 B. Thus, the correction calculation circuits  510  are able to generate pre-compensation signals α[n]+jβ[n]−α[n−L]+jβ[n−L]. The multipliers  410  multiply the baseband signal I[n]+jQ[n] with the pre-compensation signal α[n]+jβ[n], and multiply the previous baseband signal I[n−1]+jQ[n−1]−I[n−L]+jQ[n−L] with the pre-compensation signals α[n−1]+jβ[n−1]−α[n−L]+jp[n−L] respectively to generate the compensation signals I 0 [n]+jQ 0 [n]−I L [n]+jQ L [n]. The adder  340  sums up the compensation signals I 0 [n]+jQ 0 [n]−I L [n]+jQ L [n] to generate the correction signal I′[n]+jQ′[n]. 
         [0047]    In some other embodiments, the correction unit  500  may also utilize the arrangement illustrated in  FIG. 3A . In other words, with a single multiplier  410 , a correction calculation circuit  510 , a single address generation circuit  224 , a single look up table  222 A and  222 B, the compensation signal I 0 [n]+jQ 0 [n] is generated according to the baseband signal I[n]+jQ[n], and is output as the correction signal I′[n]+jQ′[n] to the output unit  240 . The descriptions of the related operations are similar with the paragraphs above, and thus the repetitious descriptions are not given here. 
         [0048]      FIG. 5B  is a schematic diagram of some embodiments of the correction calculation circuit  510 . As shown in  FIG. 5B , the correction calculation circuit  510  includes multipliers  512 A- 512 E, a subtractor  513 , an adder  514 , and a coordinate converter  515 . 
         [0049]    The multiplier  512 A multiplies the in-phase data signal I[n] by the square, to generate an operation value I 2 [n]. The multiplier  512 B multiplies the quadrature data signal Q[n] by the square, to generate an operation value Q 2 [n]. The multiplier  512 C multiplies the in-phase data signal I[n] with the quadrature data signal Q[n], to generate an operation value I[n]Q[n]. The subtractor  513  subtracts the operation value Q 2 [n] from the operation value I 2 [n] to generate an operation value I 2 [n]−Q 2 [n]. The multiplier  512 D multiplies the operation value I 2 [n]−Q 2 [n] with the coefficient C 1 [n] to generate an operation value C 1  [n]*(I 2 [n]−Q 2 [n]). The multiplier  512 E multiplies the operation value I[n]Q[n] with the coefficient C 2 [n] to generate an operation value C 2 [n]*(I[n]Q[n]). The adder  514  sums up the operation value C 1 [n]*(I 2 [n]−Q 2 [n]) and the operation value C 2 [n]*(I[n]Q[n]) to generate a phase error value θ[n]. The coordinate converter  515  performs a coordinate conversion according to the phase error value θ[n] to generate phase correction signals α[n] and β[n], in which α[n]=cos(θ[n]), and β[n]=−sin(θ[n]). 
         [0050]    Effectively, in this embodiment, the correction calculation circuit  510  may sequentially calculate required parameters for composing the final output correction signal I′(t)+jQ′(t) according to the equations (6) and (7) above. 
         [0051]      FIG. 6A  is a schematic diagram of some embodiments of an address generation circuit  600 . As shown in  FIG. 6A , the address generation circuit  600  includes a data merger  610  and a multiplier  620 . The data merger  610  merges the in-phase data signal I[n] with the quadrature data signal Q[n] to generate a pre-address code PAD. The multiplier  620  multiplies the pre-address code PAD with the system parameter g to output the address AD. 
         [0052]    For example, both of the in-phase data signal I[n] and the quadrature data signal Q[n] are 5-bit digital data, and the system parameter is 2 (e.g., the gain of the transmitter is set to 2). The bit values of the in-phase data signal I[n] are “01001,” and the bit values of the quadrature data signal Q[n] are “10101.” The data merger  610  then combines the in-phase data signal I[n] with the quadrature data signal Q[n] to generate a 10-bit pre-address code PAD, of which the bit values are “0100110101.” The multipliers thus outputs 10-bit address AD, of which the bit values are “1001101010.” 
         [0053]      FIG. 6B  is a schematic diagram of some embodiments of an address generation circuit  600 A. As shown in  FIG. 6B , the address generation circuit  600 A includes multipliers  630 - 632  and an adder  640 . The multiplier  630  multiplies the in-phase data signal I[n] by the square to generate a pre-address code PAD 1 . The multiplier  631  multiplies the quadrature data signal Q[n] to generate by the square to generate a pre-address code PAD 2 . The adder  640  sums up the pre-address code PAD 1  and pre-address code PAD 2  to generate a pre-address code PAD 3 . The multiplier  640  multiplies the pre-address code PAD 3  with the system parameter g to output the address AD. 
         [0054]    For example, both of the in-phase data signal I[n] and the quadrature data signal Q[n] are 5-bit digital data, and the system parameter is 2 (e.g., the gain of the transmitter is set to 2). The bit values of the in-phase data signal I[n] are “01001,” and the bit values of the quadrature data signal Q[n] are “10101.” Accordingly, the multiplier  630  generates a 10-bit pre-address code PAD 1 , of which the bit values are “0001010001.” The multiplier  631  generates a 10-bit pre-address code PAD 2 , of which the bit values are “0010101001.” The adder  640  sums up the pre-address codes PAD 1 -PAD 2  to generate the pre-address code PAD 3 , of which the bit values are “0011111010.” The multiplier  632  then outputs a 10-bit address AD, of which the bit values are “0111110100.”  FIG. 6A  and  FIG. 6B  are given for illustrative purposes only, various types of encoder circuit, which are able to implement the address generation circuit  224 , are within the contemplated scope of the present disclosure. 
         [0055]    As discussed above, the transmitter provided in the present disclosure utilizes different arrangements to preset multiple groups of loop up tables, in order to eliminate introduced from a pulling effect according to the system operating status of the transmitter and the received baseband signal. As a result, the system performance of the transmitter and the data accuracy may be improved. 
         [0056]    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this invention provided they fall within the scope of the following claims.