Abstract:
A transistor circuit that ensures signal transmission between adjoining direct-coupled stages at a low supply voltage even when an input signal is in a high level. This transistor circuit is comprised of a first stage having a first transistor and a first load connected to a collector or drain of the first transistor, and a second stage having a second transistor. An input voltage is applied to a base or gate of the first transistor in the first stage. The first transistor produces a first output current flowing through the first load according to the input voltage, thereby outputting a first output voltage at the collector or drain of the first transistor The first output voltage from the first stage is applied to a base or gate of the second transistor in the second stage without using any coupling capacitor. The first load has a variable resistance responsive to a magnitude of a dc component of the first output current. When the magnitude of the dc component of the first output current is increased from a predetermined value due to a magnitude increase of the input voltage, thereby decreasing a magnitude of a dc component of the first output voltage, the variable resistance of the first load is decreased so as to compensate the decreased magnitude of the dc component of the first output voltage. The effect caused by the operating point shift is compensated.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a transistor circuit and more particularly, to a transistor circuit equipped with direct-coupled stages that compensates the effect caused by the shift of the operating point of a transistor or transistors due to high-level input, which is preferably applied to radio communication systems such as portable or mobile telephones operable at a low supply voltage of approximately 1 V. 
     2. Description of the Prior Art 
     In recent years, to downsize radio communication systems such as mobile telephones, more and more Integrated Circuits (ICs) have been incorporated into the systems. Under the circumstances, the ICs need to be formed as small as possible, because the chip size of the ICs affects directly the size of the systems. 
     As known well, generally, the chip area of a capacitor is comparatively large with respect to other electronic elements such as a resistor and a transistor and at the same time, it increases proportionally with the increasing capacitance value. This means that capacitors form a bottleneck in decreasing the chip size of ICs. 
     Discrete capacitor components may be prepared outside ICs and connected to the ICs, reducing the number of capacitors in ICs. In this case, however, there arises a disadvantage that discrete capacitor components increase the overall mounting area of parts or subsystems of radio communication systems, which is contrary to the downsizing of radio communication systems. Accordingly, it is necessary that the number itself of capacitors in the systems is reduced. 
     As a result, to reduce the number itself of capacitors in the ICs designed for the radio communication systems of this sort, the direct-coupling configuration has been usually used to interconnect adjoining stages of transistor circuits such as amplifiers, frequency mixers, and so on in the ICs. 
     FIG. 1 shows the circuit configuration of a prior-art transistor amplifier circuit incorporated into an IC for a mobile telephone. In FIG. 1, the input of the prior-art transistor amplifier circuit  100  is connected to an antenna  101  through a tuning circuit  102  and the output thereof is connected to the input of a demodulator  105 . The output of the demodulator  10 ; is connected to the input of a data processor  106 . The output of the data processor  106  is connected to the input of a reception indicator  107 . 
     The antenna  101  receives radio wave including transmitted Radio frequency (RF) signals. The tuning circuit  102  selects a desired one of the RF signals thus received by the antenna  101  and outputs the desired, selected RF signal to the amplifier circuit  100 . The RP signal thus inputted into the amplifier circuit  100  is referred as an input voltage V IN . 
     The amplifier circuit  100  amplifies the input voltage V IN  and outputs an amplified RF signal to the demodulator  105 . The amplified RF signal thus outputted from the amplifier circuit  100  is referred as an output voltage V OUT . 
     The demodulator  105  demodulates the RE signal (i.e., the output voltage V OUT ) outputted from the amplifier circuit  100  and outputs a demodulated signal to the data processor  106 . The data processor  106  performs predetermined data processing operations with respect to the demodulated signal. If the identification number (ID No.) included in the demodulated signal accords with the ID No. of the user or holder, the data processor  106  sends a specific signal to the reception indicator  107 , notifying the user of the reception of communications or messages. Thereafter, the user accesses the received communications or messages as necessary. 
     As seen from FIG. 1, the prior-art amplifier circuit  100  has two amplifier stages  103  and  104  directly-coupled together without using any coupling capacitors. 
     The first amplifier stage  103  has an npn-type bipolar transistor TR 101  whose emitter is connected to the ground and a load resistor R 101  (resistance: R L ) connected to the collector of the transistor TR 101 . The input voltage V IN  from the tuning circuit  102  is applied to the base of the transistor TR 101 . The collector of the transistor TR 101  is connected through the load resistor R 101  to a power supply and is applied with a constant supply voltage V CC . Here, V CC =1 V. An amplified voltage of V IN , i.e, an output voltage V 1  of the first amplifier stage  103 , is derived from the collector of the transistor TR 101 . 
     The second amplifier stage  104  has an npn-type bipolar transistor TR 102  whose emitter is connected to the ground and a load resistor R 104  connected to the collector of the transistor TR 102 . The output voltage V 1  of the first amplifier stage  103  is applied to the base of the transistor TR 102  through a coupling resistor R 103 . The collector of the transistor TR 102  is connected through the load resistor R 104  to the power supply of V CC  and is applied with the constant supply voltage V CC . An amplified voltage of V 1 , i.e., the output voltage V OUT  of the second amplifier stage  104 , is derived from the collector of the transistor TR 102  and is applied to the demodulator  105 . 
     The strength of the transmitted radio wave fluctuates in the air due to the change of the propagation and/or reflection conditions. If the antenna  101  is located in a place where the strength of the radio wave is in a high level, the input level for the first amplifier stage  103  of the amplifier circuit  100  (i.e., the input voltage V IN , to the first amplifier stage  103 ) has a large magnitude. Obviously, due to the amplification operation in the first amplifier stage  103 , the output voltage V OUT  of the amplifier circuit  100  has a larger magnitude than that of the input voltage V IN . This means that the output voltage V OUT  of the amplifier circuit  100  has an enough magnitude for receiving the transmitted communications or messages. In spite of this fact, there is a possibility that the telephone shown in FIG. 1 is unable to perform its reception operation, the reason of which is as follows. 
     Here, as shown in FIG. 1, the base-to-emitter voltage, the collector-to-emitter voltage, the base current, and the collector current of the transistor TR 101  are defined as V BE101 , V CE101 , I B101 , and I C101 , respectively. Similarly, the base-to-emitter voltage, the collector-to-emitter voltage, the base current, and the collector current of the transistor TR 102  are defined as V BE102 , V CE102 , I B102 , and I C102 , respectively. 
     The input voltage V IN  is expressed as the sum of the bias (dc) component V BB  and the signal (ac) component V IN . Then, the base-to-emitter voltage V BE101  is equal to the input voltage V IN  and therefore, the following equation (1) is established. 
     
       
           V   IN   =V   BE101   =V   BB   +V   IN   (1) 
       
     
     The base current I B101 , of the transistor TR 101  is expressed as the sum of the bias (dc) component I B101  and the signal (ac) component i B101 . Thus, the following equation (2) is established. 
     
       
           I   B101   =I   BB101   +I   B101   (2) 
       
     
     FIG. 2 shows the I BE101 −V BE101  characteristic of the transistor TR 101  in the first amplifier stage  103 , in which the reference character P 1  denotes the operating point of the transistor TR 101  located on the curve  52  of the I BE101 −V BE101  characteristic. As seen from the equations (1) and (2), the operating point P 1  has an abscissa value of V BB  and an ordinate value of I BB101 . 
     The input voltage V IN  (i.e., the base-to-emitter voltage V BE101  of the transistor TR 101 ) varies with time as schematically shown by periodic waveforms  51   a  and  51   b  in FIG.  2 . The waveform  51   a  having a small magnitude indicates the change of V IN  and V BE101  at the received strength of the radio wave being in a low level. The waveform  51   b  having a large magnitude indicates the change of V IN  and V BE101  at the received strength of the radio wave being in a very high level. 
     Due to the change of V IN  or V BE101 , the base current I B101 , of the transistor TR 101  varies with time as schematically shown by periodic waveforms  53   a  and  53   b  in FIG.  2 . The waveform  53   a  having a small magnitude indicates the change of I B101  caused by the waveform  51   a  of V IN  and V BE101  having a small magnitude. The waveform  53   b  having a large magnitude indicates the change of I B101 , caused by the waveform  51   b  of V IN  and V BE101  having a large magnitude. 
     As seen from the waveform  53   a , when the received strength of the radio wave is low, no problems occur. However, when the received strength of the radio wave is very high, there arises a problem that the waveform  53   b  has a large distortion. This is because the portion of the waveform  53   b  above the level I BB101  is fully amplified while the portion of the waveform  53   b  below the level I BB101  is not fully amplified, which is due to the shape of the I BE101 −V BE101  characteristic curve  52 . 
     The state shown by the waveform  53   b  is equivalent to the state that the dc component or average of the base current I B101  is raised from its original value I B101  to an unwanted value I B101 , where I B   101 &lt;I B101 ′. Thus, the dc component or average of the collector current I C101 , of the transistor TR 101  is increased, resulting in the operating point P 2  shown in FIG. 3 being shifted to the point P 2 ′. 
     FIG. 3 shows the I C101 −V C101  characteristic of the transistor TR 101  in the first amplifier stage  103 , in which the reference number  60  denotes the load line of the transistor TR 101 . The curve  63  denotes the I C101 −V CE101 , characteristic at I B101 =I BB101  (i.e., at the operating point P 1  in FIG.  2 ). The curve  64  denotes the I C101 −V CE101  characteristic at I B101 =I BB101 ′. 
     Because of the above-described unwanted increase of the dc component value of the collector current I C101  of the transistor TR 101 , the operating point P 2  of the transistor TR 101  located on the curve  63  is shifted to the unwanted point P 2 ′ located on the curve  64  The unwanted point P 2 ′ is located within the saturation reaction  62  of the operation of the transistor TR 101 . 
     The dc component value of the collector current I C101  is very large at the unwanted point P 2 ′ and therefore, the voltage drop caused by the load resistor R 101  is very large. The large voltage drop thus caused decreases the dc component value of collector-to-emitter voltage V CE101  of the transistor TR 101  (i.e., the dc component value of the output voltage V 1  of the first amplifier stage  103 ). Since the output voltage V 1  is equal to the base-to-emitter voltage V BE102  of the transistor TR 102  in the second amplifier stage  104 , the dc component value of the base-to-emitter voltage V BE102  is largely lowered from its wanted value. 
     As a result, as shown in FIG. 4 indicating the relationship between the base-to-emitter voltage V BE102  and the base current I B102  of the transistor TR 102 , the dc component value of the base-to-emitter voltage V BE102  is much smaller than its wanted value, in other words, the operating point of the transistor TR 102  is displaced from the I BE102  −V BE102  curve  55 . This means that the transistor TR 102  is unable to perform its amplification operation and that the telephone in FIG. 1 is unable to perform its reception operation in spite of the strength of the received radio wave being sufficiently high. In FIG. 4, the reference numeral  54  denotes the waveform of the base-to-emitter voltage V BE102 , i.e., the output voltage V 1  of the first amplifier stage  103 . 
     For example, due to the operating-point shift from P 2  to P 2 ′ in FIG. 3, the dc or bias component of the collector-to-emitter voltage V CE101  of the transistor TR 101  (i.e., the output voltage V 1  of the first amplifier stage  103 ) is lowered abruptly from 0.8 V to 0.2 V, while the supply voltage V CC  is equal to 1 V. As known well, generally, the transistor TR 102  starts its amplification operation when the base-to-emitter voltage V BE102  is approximately 0.6 V. Thus, in this case, the transistor TR 102  is unable to amplify the applied voltage V 1 , in other words, no signal is transmitted from the first stage  103  to the second stage  104 . 
     As explained above, the prior-art transistor amplifier circuit  100  shown in FIG. 1 has a problem that there is a possibility that the telephone is unable to perform its reception operation in spite of the magnitude of the received radio wave being high. This problem can be solved or suppressed by raising the supply voltage V CC . However, the supply voltage increase is not preferred in the communication systems such as portable telephones from the viewpoint that the power consumption should be as low as possible. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention to provide a transistor circuit that ensures signal transmission between adjoining direct-coupled stages at a low supply voltage even when an input signal is in a high level. 
     Another object of the present invention to provide a transistor circuit that compensates the effect caused by the shift of the operating point of a transistor or transistors due to high-level input. 
     The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description. 
     A transistor circuit according to the present invention is comprised of a first stage having a first transistor and a first load connected to a collector or drain of the first transistor, and a second stage having a second transistor. 
     An input voltage is applied to a base or gate of the first transistor in the first stage. The first transistor produces a first output current flowing through the first load according to the input voltage, thereby outputting a first output voltage at the collector or drain of the first transistor. The first output voltage from the first stage is applied to a base or gate of the second transistor in the second stage without using any coupling capacitor. 
     The first load has a variable resistance responsive to a magnitude of a do component of the first output current. 
     When the magnitude of the dc component of the first output current is increased from a predetermined value due to a magnitude increase of the input voltage, thereby decreasing a magnitude of a dc component of the first output voltage, the variable resistance of the first load is decreased so as to compensate the decreased magnitude of the dc component of the first output voltage. 
     With the transistor circuit according to the present invention, the first load has a variable resistance responsive to the magnitude of the dc component of the first output current. When the magnitude of the dc component of the first output current is increased from the predetermined value due to a magnitude increase of the input voltage, thereby decreasing the magnitude of the dc component of the first output voltage, the variable resistance of the first load is decreased so as to compensate the decreased magnitude of the dc component of the first output voltage. 
     Therefore, even if the magnitude of the dc component of the first output voltage in the first stage is decreased (i.e., the operating point of the first transistor is shifted) due to a large magnitude of the input voltage at a low supply voltage, the dc component of the first output voltage can be made to have an enough value for the operation of the second transistor in the second stage. Thus, the second transistor in the second stage is capable of its operation with the applied first output voltage from the first stage even when a large amplitude signal is inputted into the first stage. 
     As a result, signal transmission between the direct-coupled first and second stages is ensured at a low supply voltage even when an input signal is in a high level. In other words, the effect caused by the shift of the operating point of the first transistor due to high-level input is compensated. 
     In a preferred embodiment of the transistor circuit according to the present invention, the first load includes a first load resistor, a second load resistor, and a first diode. The first load resistor is connected to the collector or drain of the first transistor. The second load resistor and the first diode are connected in series. The load resistor and the first diode are connected in parallel to the first load resistor. A forward direction of the first diode and a direction of the first output current are same. 
     In this embodiment, there arises an additional advantage that the first load having the variable resistance responsive to the magnitude of the dc component of the first output current can be realized by a simple and low-cost configuration. 
     In this embodiment, it is preferred that the first diode is turned on when the magnitude of the dc component of the first output current is greater than a specific value, allowing a part of the first output current to flow through the second load resistor. In this case, there is an additional advantage that the current path for the second load resistor can be automatically turned on or off by simply setting in advance the specific value of the first diode. 
     As the first diode, a typical junction diode or Zener diode may be preferably used. 
     In another preferred embodiment of the transistor circuit according to the present invention, the second transistor has a second load connected to a collector or drain of the second transistor. The second transistor produces a second output current flowing through the second load according to the first output voltage from the first stage, thereby outputting a second output voltage at the collector or drain of the second transistor. The second load has a variable resistance responsive to a magnitude of a dc component of the second output current. 
     In this embodiment, there arises an additional advantage that signal transmission between the second stage and a third stage directly-coupled with the second stage is ensured at a low supply voltage even when a large amplitude signal is inputted into the second stage. 
     In still another preferred embodiment of the transistor circuit according to the present invention, each of the first and second transistors is a bipolar transistor having a common-emitter configuration. In this embodiment, there arises an additional advantage that the advantage of the present invention is effectively exhibited. 
     In the transistor circuit according to the present invention, each of the first and second transistors may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) having a common-source configuration. 
     Preferably, the first stage has a single-transistor configuration or a differential transistor pair configuration. However, any other configuration may be applied to the first stage if the first and second transistors are used as active elements. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order that the present invention may be readily carried into effect, it will now be described with reference to the accompanying drawings. 
     FIG. 1 is a schematic diagram showing the circuit configuration of a prior-art transistor amplifier circuit incorporated into an IC for a mobile telephone. 
     FIG. 2 is a graph showing the relationship between the base-to-emitter voltage V B101  and the base current I B101  of the bipolar transistor in the first amplifier stage of the prior-art transistor amplifier circuit of FIG.  1 . 
     FIG. 3 is a graph showing the relationship between the collector-to-emitter voltage V CE101 , and the collector current I C101 , of the bipolar transistor in the first amplifier stage of the prior-art transistor amplifier circuit of FIG.  1 . 
     FIG. 4 is a graph showing the relationship between the base-to-emitter voltage V BE102  and the base current I B102  of the bipolar transistor in the second amplifier stage of the prior-art transistor amplifier circuit of FIG.  1 . 
     FIG. 5 is a schematic diagram showing the circuit configuration of a transistor amplifier circuit according to a first embodiment of the present invention, which uses bipolar transistors and which is incorporated into an IC for a mobile telephone. 
     FIG. 6 is a graph showing the relationship between the collector-to-emitter voltage V CE1  and the collector current I C1 , of the bipolar transistor in the first amplifier stage of the transistor amplifier circuit according to the first embodiment of FIG.  5 . 
     FIG. 7 is a graph showing the relationship between the collector-to-emitter voltage V CE1  or V CE101  and the input voltage V IN  of the first transistor in the first amplifier stage of the transistor amplifier circuit according to the first embodiment of FIG.  5  and that of the prior-art transistor amplifier circuit of FIG.  1 . 
     FIG. 8 is a circuit diagram showing the circuit configuration of a transistor circuit according to a second embodiment of the present invention, which is incorporated into an IC for a mobile telephone. 
     FIG. 9 is a schematic diagram showing the circuit configuration of a transistor amplifier circuit according to a third embodiment of the present invention, which uses MOSFETs and which is incorporated into an IC for a mobile telephone. 
     FIG. 10 is a schematic diagram showing the circuit configuration of a transistor amplifier circuit according to a fourth embodiment of the present invention, which uses bipolar transistors and which is incorporated into an IC for a mobile telephone. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will be described in detail below while referring to the drawings attached. 
     FIRST EMBODIMENT 
     A transistor amplifier circuit according to a first embodiment of the present invention is shown in FIG.  5 . This circuit is incorporated into an IC for a mobile telephone. Although this IC has a transmitter circuit, it is omitted in FIG. 5 for simplification of description. 
     As shown in FIG. 5, the input of the transistor amplifier circuit  10  according to the first embodiment is connected to an antenna  1  through a tuning circuit  2  and the output thereof is connected to a demodulator  5 . The output of the demodulator  5  is further connected to the input of a data processor  6 . The output of the data processor  6  is connected to the input of a reception indicator  7 . 
     The antenna  1  receives radio wave including transmitted RF signals. The tuning circuit  2  selects a desired one of the RF signals thus received by the antenna  1  and outputs the desired, selected RF signal to the amplifier circuit  10 . The RF signal thus inputted into the amplifier circuit  10  is referred as an input voltage V IN . 
     The amplifier circuit  10  amplifies the input voltage V IN  and outputs an amplified RF signal to the demodulator  5 . The amplified RF signal thus outputted from the amplifier circuit  10  is referred as an output voltage V OUT . 
     The demodulator  5  demodulates the RF signal (i.e., the output voltage V OUT ) outputted from the amplifier circuit  10  and outputs a demodulated signal to the data processor  6 . The data processor  6  performs predetermined data processing operations with respect to the demodulated signal. If the ID No. included in the demodulated signal accords with that of the user or holder, the data processor  6  sends a specific signal to the reception indicator  7 , notifying the user of the reception of communications or messages. Thereafter, the user accesses the received communications or messages as necessary. 
     As seen from FIG. 5, the amplifier circuit  10  has a two amplifier stages  3  and  4  directly-coupled together without using any coupling capacitors. 
     The first amplifier stage  3  has an npn-type bipolar transistor TR 1  whose emitter is connected to the ground and a load  8  (resistance: R L ) connected to the collector of the transistor TR 1 . The input voltage V IN  from the tuning circuit  2  is applied to the base of the transistor TR 1 . The collector of the transistor TR 1  is connected through the load  8  to a power supply (not shown) and is applied with a constant supply voltage V CC . Here, V CC =1 V. An amplified voltage of V IN , i e. , an output voltage V 1  of the first amplifier stage  3 , is derived from the collector of the transistor TR 1 . 
     Thus, the first amplifier stage  3  has the common-emitter configuration with respect to the transistor TR 1 . 
     The load  8  has a load resistor a, a typical junction diode D 1 , and an additional load resistor R 2 . The diode D 1  and the resistor R 2  are connected in series to each other. The serially-connected diode D 1  and the resistor R 2  are connected in parallel to the load resistor R 1  at nodes N 1  and N 2 . The forward orientation of the diode D 1  is the same as that of the collector current I C1 , of the transistor TR 1 . 
     The diode D 1  serves as a switch for automatically turned on or off the current path for the resistor R 2  If the voltage drop caused by the load resistor R 1  (i.e. the voltage generated between the nodes N 1  and N 2 ) is equal to or less than a specific value, the diode D 1  is turned off or open. Therefore, the collector current I C1 , is unable to flow through the resistor R 2 . If the voltage drop caused by the load resistor R 1  (i.e., the voltage generated between the nodes N 1  and N 2 ) is greater than the specific value, the diode D 1  is turned on or conducts, allowing a part of the collector current It, to flow through the resistor R 2 . 
     For example, the resistance value of the load resistor R 1  and the dc component (i.e., the bias current) of the collector current I C1 , are determined in such a way that the voltage between the nodes N 1  and N 2  is approximately 0.2 V when the magnitude of the signal (ac) component of the input voltage V IN  is zero or small. The junction diode D 1  typically has a characteristic allowing a current to flow when an applied voltage is approximately 0.6 V or greater. In other words, the diode D 1  has a turn-on voltage of approximately 0.6 V. Therefore, when the magnitude of the signal component of the input voltage V IN  is zero or small, no current flows through the resistor R 2 . This state is the same as that of the first amplifier stage  103  of the prior-art amplifier circuit  100  shown in FIG.  1 . 
     On the other hand, when the magnitude of the signal component of the input voltage V IN  is very high, the dc or bias component of the collector current I C1 , becomes higher than its desired value and accordingly, the voltage between the nodes N 1  and N 2  becomes higher than the turn-on voltage (approximately 0.6 V) of the diode D 1 . Thus, the diode D 1  is turned on and a part of the collector current I C1 , flows through the resistor R 2 . This means that the collector current I C1 , flowing through the load resistor R 1  is decreased, in other words, the resistance of the load  8  is decreased. 
     As a result, the unwanted increase of the dc component of the collector current I C1 , is automatically compensated and at the same time, the output voltage V 1  (i.e., the base-to-emitter voltage V BE2  of the transistor TR 2 ) of the first amplifier stage  3  enters the operable range of the transistor TR 2 . 
     The second amplifier stage  4  has the same configuration as that of the first amplifier stage  3 . Specifically, the second amplifier stage  4  has an npn-type bipolar transistor TR 2  whose emitter is connected to the ground and a load  9  connected to the collector of the transistor TR 2 . The output voltage V 1  from the first amplifier stage  3  is applied to the base of the transistor TR 2  through the coupling resistor R 3 . The collector of the transistor TR 2  is connected through the load  9  to the power supply of V CC  (=1 V). An amplified voltage of the voltage V 1 , i.e., the output voltage V OUT  of the amplifier circuit  10 , is derived from the collector of the transistor TR 2 . 
     Thus, the second amplifier stage  4  also has the common-emitter configuration with respect to the transistor TR 2 . 
     The load  9  has a load resistor R 4 , a typical junction diode D 2 , and an additional load resistor R 5 . The diode D 2  and the resistor R 5  are connected in series to each other. The serially-connected diode D 2  and the resistor R 5  are connected in parallel to the load resistor R 4  at nodes N 1  and N 2 . The forward orientation of the diode D 2  is the same as that of the collector current I C2  of the transistor TR 2 . 
     The diode D 2  serves as a switch for automatically turned on or off the current path for the resistor R 5 . Since the operation of the diode D 2  is the same as that of the diode D 1 , the explanation about the diode D 2  is omitted here. Also, the operation of the transistor TR 2  is the same as that of the transistor TR 1  and therefore, no explanation about the transistor TR 2  is presented here. 
     FIG. 6 shows the relationship between the collector-to-emitter voltage V CE1  and the collector current I C1 , of the transistor TR 1  in the first amplifier stage  3  of the transistor amplifier circuit  10  according to the first embodiment of FIG.  5 . 
     As shown in FIG. 6, when the magnitude of the signal component of the input voltage V IN  is zero or small, the operating point of the transistor TR 1  is located on the point P 2  (V CE1 =0.8 V), which is located at the intersection of the curve of I B1 =I BB1  and the straight load line  60 . At this time, the operating point of the transistor TR 1  is located on he same point as indicted by P 1  in FIG.  2 . 
     When the magnitude of the signal component of the input voltage V IN  is very high, the dc or bias component of the collector current I C1  of the transistor TR 1  becomes higher than its desired value and accordingly, the voltage between the nodes N 1  and N 2  becomes higher than the turn-on voltage (approximately 0.6 V) of the diode D 1 . Then, the diode D 1  is turned on and a part of the collector current I C1 , flows through the resistor R 2 . This means that the collector current I C1  flowing through the load resistor R 1  is decreased, in other words, the resistance of the load  8  is decreased. Thus, the slope of the load line  60  is increased at the point P 2 , forming the load line  61  bent at the point P 2 . As a result, the operating point is shifted to the point P 2 ″ which is located at the intersection of the curve of I B1 =I BB1 ′ and the load line  61 . 
     In the prior-art amplifier  100 , as explained previously, when the magnitude of the signal component of the input voltage V IN  is very high, the operating point is shifted to P 2 ′ which is located at the intersection of the curve of I B1 =I BB1 ′ and the load line  60 . 
     FIG. 7 shows the relationship (the curve  74 ) between the input voltage V IN  and the collector-to-emitter voltage V CE1  in the circuit  10  according to the first embodiment of FIG.  5  and the relationship (the curve  73 ) between the input voltage V IN  and the collector-to-emitter voltage V CE101  in the prior-art circuit  100  in FIG.  1 . 
     As seen from the curves  73  and  74  in FIG. 7, when the magnitude of the signal component of the input voltage V IN  is in a high level, the lowering of the voltage V CE1  of the transistor TR 1  in the first embodiment is suppressed or compensated compared with that of the voltage V CE101  of the transistor TR 101  in the prior-art amplifier  100 . 
     As describe above, with the two-stage amplifier circuit  10  according to the first embodiment of FIG. 5, even if he magnitude of the dc component of the output voltage V1 of the first amplifier stage  3  is decreased due to a large magnitude of the input voltage V IN  at a low supply voltage of 1 V, the dc component of the output voltage V1 can be compensated to have an enough value for the amplifier operation of the transistor TR 2  in the second amplifier stage  4 . In other words, the transistor TR 2  in the second amplifier stage  4  is capable of its operation with the applied output voltage V1 even when a large amplitude signal is inputted into the first amplifier stage  3 . 
     Thus, signal transmission between the direct-coupled first and second amplifier stages  3  and  4  is ensured at a low supply voltage of 1 V even when a large amplitude signal is inputted. 
     Additionally, the shift of the operating point from P 2  to P 2 ″ in FIG. 6 generates a disadvantage that the gain of the first amplifier stage  3  becomes low. However, this disadvantage causes no problem because the operating point shift takes place in the case where the received RF signal has a sufficiently large strength for reception. 
     The diode D 2  and the resistor R 5  in the load  9  may be removed, because they have no relationship with the operation of the transistor TR 1 . However, it is preferred that the diode D 2  and the resistor R 5  are provided in the load  9 . The reason is that the diode D 2  and the resistor R 5  will produce the same advantages as explained above with respect to the transistor TR 1  for the transistor TR 2 . 
     SECOND EMBODIMENT 
     FIG. 8 shows the circuit configuration of a transistor circuit according to a second embodiment of the present invention, which is incorporated into an IC for a mobile telephone. 
     In FIG. 8, the first and second inputs of the transistor circuit  17  according to the second embodiment are connected to terminals T 1  and T 2  of the IC  20 , respectively. A local oscillator  19 , which is provided outside the IC  20 , is connected to the terminal T 1 . Therefore, a local signal voltage V LOC  outputted from the local oscillator  19  is applied to the terminal T 1 . An antenna  11  is connected to the terminal T 2  through a RF amplifier  18  and a coupling capacitor C 1 . The antenna  11 , the RF amplifier  18 , and the coupling capacitor C 1  are provided outside the IC  20 . An RF signal received by the antenna  11  is amplified by the amplifier  18 . Due to the coupling capacitor C 1 , only the signal (ac) component of the amplified RF signal is applied to the terminal T 2 . 
     The transistor circuit  17  has a single-balance frequency mixer (frequency converter) located in a frequency mixer stage  15  and a differential amplifier located in an amplifier stage  16 . 
     The frequency mixer in the stage  15  is comprised of a pair of npn-type bipolar transistors TR 11  and TR 12  whose emitters are coupled together and an npn-type bipolar transistor TR 13  whose collector is connected to the coupled emitters of the transistors TR 11  and TR 12 . The emitter of the transistor TR 13  is connected to the ground. 
     The base of the transistor TR 11  is connected to the terminal T 1  and applied with the local signal voltage V LOC . The base of the transistor TR 11  is further connected through a resistor R 12  to a power supply (not shown) and applied with a constant supply voltage V CC . The base of the transistor TR 12  is connected to the power supply of V CC  through a resistor R 1 . The base of the transistor TR 13  is connected to the terminal T 2  and applied with the RF signal voltage V IN  received by the antenna  11  The base of the transistor TR 13  is further connected to the power supply of V CC  through a resistor R 11 . 
     The collector of the transistor TR 11  is connected to the power supply of V CC  through a load  21 . The load  21  has a load resistor R 13 , a typical junction diode D 11 , and an additional load resistor R 14 . The diode D 13  and the resistor R 14  are connected in series to each other. The serially-connected diode D 11  and the resistor R 14  are connected in parallel to the load resistor R 13 . The forward orientation of the diode D 11  is the same as that of the collector current of the transistor TR 11 . 
     Like the first embodiment, the diode D 11  serves as a switch. If the voltage drop caused by the load resistor R 13  is equal to or less than a specific value, the diode D 11  is turned off or open. Therefore, the collector current is unable to flow through the additional load resistor R 14 . If the voltage drop caused by the load resistor R 13  is greater than the specific value, the diode D 11  is turned on or conducts, allowing a part of the collector current to flow through the resistor R 14 . Thus, the two parallel-connected resistors R 13  and R 14  serves as the load of the transistor TR 11 , which means that the resistance of the load  21  is lowered. 
     The collector of the transistor TR 12  is connected to the power supply of V CC  through a load  22 . The load  22  has a load resistor R 16 , a typical junction diode D 12 , aid an additional load resistor R 17 . The diode D 12  and the resistor R 17  are connected in series to each other. The serially-connected diode D 12  and the resistor R 17  are connected in parallel to the load resistor R 16 . The forward orientation of the diode D 12  is the same as that of the collector current of the transistor TR 12 . 
     The operation of the load resistors R 16  and  17  and the junction diode D 12  in the load  22  is the same as that of the load  21 . 
     The amplifier stage  16  is comprised of a pair of npn-type bipolar transistors TR 14  and TR 15  whose emitters are coupled together and an npn-type bipolar transistor TR 16  whose collector is connected to the coupled emitters of the transistors TR 14  and TR 15 . The emitter of the transistor TR 16  is connected to the ground. 
     The base of the transistor TR 14  is connected through a coupling resistor R 22  to the collector of the transistor TR 11  from which an output voltage V 11 of the frequency mixer in the stage  15  is derived. Therefore, the output voltage V 11  is applied to the base of the transistor TR 14 . The base of the transistor TR 15  is connected through a coupling resistor R 23  to the collector of the transistor TR 12  from which another output voltage V 12  of the frequency mixer in the stage  15  is derived. Therefore, the output voltage V 12  is applied to the base of the transistor TR 15 . The base of the transistor TR 16  is connected through a resistor R 24  to the power supply of V CC . 
     The collector of the transistor TR 14  is connected to the power supply of V CC  through a load  23 . The load  23  has a load resistor R 18 , a typical junction diode D 13 , and an additional load resistor R 19  The diode D 13  and the resistor R 19  are connected in series to each other. The serially-connected diode D 13  and the resistor R 19  are connected in parallel to the load resistor R 18  The forward orientation of the diode D 13  is the same as that of the collector current of the transistor TR 14 . 
     The collector of the transistor TR 15  is connected to the power supply of V CC  through a load  24 . The load  24  has a load resistor R 21 , a typical junction diode D 14 , and an additional load resistor R 20 . The diode D 14  and the resistor R 20  are connected in series to each other. The serially-connected diode D 14  and the resistor R 20  are connected in parallel to the load resistor R 21 . The forward orientation of the diode D 14  is the same as that of the collector current of the transistor TR 15 . 
     An output voltage V OUT1  of the differential amplifier stage  16  is derived from the collector of the transistor TR 14 . Another output voltage V OUT2  of the differential amplifier stage  16  is derived from the collector of the transistor TR 15 . These two output voltages V OUT1  and V OUT2  thus derived are applied to a next stage (not shown). 
     Since the operation of the frequency mixer in the stage  15  and the differential amplifier in the stage  16  is popular and known well, no explanation about the operation is presented here. 
     With the two-stage transistor circuit  17  according to the second embodiment shown in FIG. 8, because of the same reason as explained in the amplifier circuit  10  according to the first embodiment, signal transmission between the direct-coupled frequency mixer stage  15  and the differential amplifier stage  16  is ensured at a low supply voltage of 1 V even when a large amplitude signal (V IN ) is inputted. 
     THIRD EMBODIMENT 
     FIG. 9 shows the circuit configuration of a two-stage amplifier circuit  10 A according to a third embodiment of the present invention. This circuit  10 A has a configuration obtained by replacing the npn-type bipolar transistors TR 1  and TR 2  in FIG. 5 with n-channel MOSFETs TR 1 ′ and TR 2 ′, respectively. The other configuration of the circuit  10 A is the same as that of the circuit  10  according to the first embodiment Therefore, the explanation about the circuit  10 A is omitted here. 
     It is obvious that the circuit  10 A has the same advantages as those in the first embodiment. 
     FOURTH EMBODIMENT 
     FIG. 10 shows the circuit configuration of a two-stage amplifier circuit  10 B according to a fourth embodiment of the present invention. This circuit  10 B has a configuration obtained by replacing the typical junction diodes D 1  and D 2  in FIG. 5 with Zener diodes ZD 1  and ZD 2 , respectively. The other configuration of the circuit  10 B is the same as that of the circuit  10  according to the first embodiment. Therefore, the explanation about the circuit  10 B is omitted here. 
     As seen from FIG. 10, the forward orientation of the diode ZD 1  and ZD 2  is opposite to that of the collector currents of the transistors TR 1  and TR 2 . 
     It is obvious that the circuit  10 A has the same advantages as those in the first embodiment. 
     VARIATIONS 
     Although the present invention is applied to an amplifier circuit and a frequency mixer circuit in the first to fourth embodiments, it is needless to say that the present invention may be applied to any other circuit. 
     Moreover, it is needless to say that one or more combination(s) of at least one diode and at least one additional resistor may be added to the load resistor R 1 , R 4 , R 13 , R 16 , R 18 , or R 21 . 
     While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention. The scope of the invention, therefore, is to be determined solely by the following claims.