Abstract:
In a plasma display panel, sustain discharge pulses having a first voltage and a second voltage, which is a negative voltage of the first voltage, may be applied to a scan electrode when a sustain electrode is biased with the ground voltage during a sustain period. The second voltage is generated without providing an additional power source but rather by a sustain discharge supply circuit, supplied with the first voltage, that repeatedly performs switching operations to generate the second voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority to and the benefit of Korean Patent Application No. 10-2004-0037274, filed on May 25, 2004, which is hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a device and method for driving a plasma display panel (PDP).  
         [0004]     2. Discussion of the Related Art  
         [0005]     A plasma display device, which includes a PDP, is a flat display that uses plasma generated via a gas discharge process to display characters or images. Depending on its size, the PDP may have up to millions of pixels arranged in a matrix format. PDPs are categorized into direct current (DC) PDPs and alternating current (AC) PDPs, depending on the supplied driving voltage waveforms and discharge cell structures.  
         [0006]     Since DC PDPs have electrodes exposed in the discharge space, they allow a current to flow in the discharge space while the voltage is supplied, and thus require resistors for current restriction. In contrast, because AC PDPs have electrodes covered by a dielectric layer, capacitances are naturally formed that restrict the current and the electrodes are protected from ion shocks during discharging. Accordingly, AC PDPs have a longer lifespan than DC PDPs.  
         [0007]     As shown in  FIG. 1 , the PDP includes opposing glass substrates  1  and  6  facing each other with a discharge space  11  disposed therebetween. A plurality of scan electrodes  4  and sustain electrodes  5  are arranged in parallel pairs on front glass substrate  1  and extend along a first direction. Scan electrodes  4  and sustain electrodes  5  are covered by a dielectric layer  2  and a protective film  3 . A plurality of address electrodes  8  are formed on back glass substrate  6  and extend along a second direction that is substantially perpendicular to the first direction. Address electrodes  8  are covered by an insulator layer  7  having barrier ribs  9  formed thereon, which are between address electrodes  8 . Phosphors  10  are disposed on a surface of insulator layer  7  facing front substrate  1  and on both sides of barrier ribs  9 . A discharge cell  12  is formed within discharge space  11  at an intersection of an address electrode  8  and a pair of a scan and sustain electrodes  4  and  5 .  
         [0008]     As shown in  FIG. 2 , a conventional plasma display includes a PDP  10 , a chassis base  20 , a front case  30 , and a rear case  40 . Chassis base  20  is fastened to the PDP  10  on its back side opposite the front image display side. Front case  30  and rear case  40  are arranged on the front side of PDP  10  and the rear side of chassis base  20 , respectively, and are combined to provide a plasma display.  
         [0009]     Referring to  FIG. 3 , PDP  10  includes a plurality of address electrodes A 1  to A m  arranged in columns along the second direction, and a plurality of scan electrodes Y 1  to Y n  and sustain electrodes X 1  to X n  grouped in pairs and arranged in rows along the first direction. Sustain electrodes X 1  to X n  have corresponding scan electrodes Y 1  to Y n . Terminals of the sustain electrodes X 1  to X n  are connected in common. PDP  10  includes an insulation substrate on which sustain electrodes and scan electrodes X 1  to X n  and Y 1  to Y n  are provided, and another insulation substrate on which the address electrodes A 1  to A m  are provided. The two insulation substrates face each other with a discharge space therebetween so that the pairs of scan and sustain electrodes may cross the address electrodes to form a discharge cell  12 .  
         [0010]     A frame of an AC PDP includes a plurality of subfields, and a subfield may include a reset period, an address period, and a sustain period.  
         [0011]     In the reset period, the respective discharge cells are reset in order to perform fluent address operations. In the address period, discharge cells are selected to be turned on and wall charges accumulate on the turned on cells (i.e., addressed cells). In the sustain period, alternately applying sustain pulses to sustain and scan electrodes generates a sustain discharge in the addressed cells, thereby displaying an image.  
         [0012]     During the sustain period, a sustain discharge voltage of V s  is alternately applied to the scan electrode and the sustain electrode so that the voltage difference between the scan electrode and the sustain electrode may be the sustain discharge voltage of V s  in the case of applying sustain pulses in the sustain period. A reference voltage of 0V is applied to the sustain electrode when the sustain discharge voltage of V s  is applied to the scan electrode.  
         [0013]     Now referring to  FIG. 4A , the reference voltage may be applied to the sustain electrode, and ±V s  may be alternately applied to the scan electrode during the sustain period in a conventional PDP driving method. By driving the PDP in this manner, the voltage difference between the scan electrode and the sustain electrode is at V s . In an alternative conventional method for driving a PDP, as shown in  FIG. 4B , sustain discharge pulses of ± 1/2V s  are alternately applied to the scan electrode and the sustain electrode, respectively, and the voltage difference between the scan electrode and the sustain electrode is maintained at the sustain discharge voltage of V s .  
         [0014]     In general, because the sustain discharge is generated by the voltage difference between the scan and sustain electrodes, so long as this voltage difference is maintained at V s , the sustain discharge operation will be sufficient for displaying images, even when varying sustain pulses are applied to the scan electrode and the sustain electrode.  
         [0015]     However, an additional power source may be needed for supplying the sustain discharge voltages of −V s  and − 1/2V s , thereby increasing production costs. Therefore, the cost of providing a PDP may be higher when attempting to supply the sustain discharge voltages of ±V s  and ± 1/2V s  to the scan electrode and the sustain electrode.  
       SUMMARY OF THE INVENTION  
       [0016]     The present invention provides a PDP driver for supplying sustain discharge voltages to scan electrodes and sustain electrodes without adding a power source for supplying varying sustain discharge voltages.  
         [0017]     The present invention discloses a PDP driver for alternately applying sustain discharge pulses including a first voltage and a second voltage to a first electrode of a PDP having a plurality of first electrodes and a plurality of second electrodes. The PDP driver includes a first switch and a second switch coupled in series between a first power for supplying the first voltage and the ground; a first capacitor having a first terminal coupled to a node of the first switch and the second switch; a first diode coupled between a second terminal of the first capacitor and the ground to permit a current path in the direction from the second terminal of the first capacitor to the ground; a second capacitor having a grounded first terminal; and a second diode coupled between a second terminal of the second capacitor and the second terminal of the first capacitor to permit a current path in the direction from the second capacitor to the first capacitor, the second terminal of the second capacitor supplying the second voltage.  
         [0018]     The present invention also discloses a method for driving a PDP including charging a first voltage in a first capacitor coupled to a power source for supplying the first voltage; providing a current path between the first capacitor and a second capacitor, generating a second voltage through the second capacitor by repeating the steps of charging the first voltage and providing a current path for a predetermined number of times; and alternately applying the first voltage and the second voltage to a first electrode of a PDP having a plurality of first electrodes and a plurality of second electrodes. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]      FIG. 1  shows a perspective view of an AC PDP.  
         [0020]      FIG. 2  shows a perspective view of a conventional plasma display.  
         [0021]      FIG. 3  shows a schematic diagram of a conventional PDP.  
         [0022]      FIG. 4A  and  FIG. 4B  show conventional PDP driving waveform diagrams.  
         [0023]      FIG. 5  shows a sustain discharge voltage supply circuit according to an embodiment of the present invention.  
         [0024]      FIG. 6  shows a switch operation timing diagram for a sustain discharge voltage supply circuit. 
     
    
     DETAILED DESCRIPTION  
       [0025]     In the following detailed description, embodiments of the present invention are shown and described by way of illustration. As those skilled in the art would recognize, the described embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, rather than restrictive.  
         [0026]      FIG. 5  shows a sustain discharge voltage supply circuit according to an embodiment of the present invention. As shown, the sustain discharge voltage supply circuit includes a power source supplying the sustain discharge voltage V s , switches SW 1  and SW 2 , capacitors C 1  and C 2 , and diodes D 1  and D 2 .  
         [0027]     Switches SW 1  and SW 2  are coupled in series between the power source and the ground. Capacitor C 1  has a first terminal coupled to a node of switches SW 1  and SW 2 , and diode D 1  is coupled between a second terminal of capacitor C 1  and the ground to thus form a current path in the direction towards the ground. Capacitor C 2  has a grounded first terminal, and diode D 2  is coupled between the second terminal of the capacitor C 2  and the second terminal of capacitor C 1  to thus form a current path in the direction towards capacitor C 1 . A voltage of V out  is coupled to a node of the anode of diode D 2  and the second terminal of capacitor C 2 .  
         [0028]     Referring to  FIG. 6 , a process for repeating on/off operations of the switches SW 1  and SW 2  to generate the voltage of −V s  will now be described. In period I, switch SW 1  is turned on and switch SW 2  is turned off. Capacitor C 1  is charged with the sustain discharge voltage of +Vs when switch SW 1  is turned on, and the current path in this instance is illustrated by {circle over (1)}(C 1 -D 1 ).  
         [0029]     In period II, switch SW 1  is turned off and switch SW 2  is turned on. The current path when switch SW 2  is turned on is illustrated by {circle over (2)}(C 1 -SW 2 -C 2 -D 2 -C 1 ). When the capacitance of capacitor C 1  is controlled to correspond with the capacitance of capacitor C 2 , the sustain discharge voltage +V s  of capacitor C 1  during period I is discharged to reach an equilibrium state, capacitors C 1  and C 2  are then charged with a sustain discharge voltage of 1/2V s , and the output voltage of V out  becomes − 1/2V s .  
         [0030]     In period III, switch SW 1  is turned on and switch SW 2  is turned off. Capacitor C 1  is charged with the sustain discharge voltage of +V s , just as in period I, when switch SW 1  is turned on, and capacitor C 2  maintains the previous state and the output voltage of V out  is maintained at the voltage of − 1/2V s  because switch SW 2  is turned off.  
         [0031]     In period IV, switch SW 1  is turned off and switch SW 2  is turned on, and current flows in the path of {circle over (2)}, as in period II. The difference between the voltage of V s  charged in capacitor C 1  and the voltage of 1/2V s  charged in capacitor C 2  is discharged, and capacitor C 2  is charged with the voltage of 1/4V s . Thus, capacitor C 2  is charged with the voltage of 3/4V s ( 1/2V s + 1/4V s ), and the output voltage of V out  becomes − 3/4V s .  
         [0032]     In period V, switch SW 1  is turned on and switch SW 2  is turned off. Capacitor C 1  is charged with +V s , in the manner as period I, and capacitor C 2  maintains its previous state and the output voltage of V out  is maintained at the voltage of − 3/4V s .  
         [0033]     In period VI, switch SW 1  is turned off and switch SW 2  is turned on, and the current flows in the same manner as period II. The difference voltage of 1/4V s  between the voltage of Vs charged in the capacitor C 1  and the voltage of 3/4V s  charged in the capacitor C 2  is discharged, and the capacitor C 2  is charged with the voltage of 1/8Vs. Therefore, the capacitor C 2  is charged with the voltage of 7/8Vs( 3/4V s + 1/8V s ), and the output voltage of V out  becomes − 7/8V s .  
         [0034]     The output voltage of V out  may eventually reach approximately −V s  when the switches SW 1  and SW 2  are repeatedly turned on and off for a predetermined number of times.  
         [0035]     The process for generating a sustain discharge voltage of − 1/2V s  is performed in a similar manner as the above-described process. That is, a voltage of − 1/2V s  is generated by supplying a voltage of 1/2V s  to the sustain discharge supply circuit and repeatedly turning on/off the switches for a predetermined number of times to attain a desired V out .  
         [0036]     When the power is turned on, the switches of the sustain discharge supply circuit are repeatedly turned on and off in the reset period, the address period, and the sustain period of the respective subfields.  
         [0037]     Therefore, a less expensive PDP is realized by the present invention because an additional power source for supplying a negative sustain discharge voltage may not be needed.  
         [0038]     It will be apparent to those skilled in the art that various modifications and variation can be made to the disclosed embodiments without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of the disclosed embodiments that come within the scope of the appended claims and their equivalents.