Abstract:
A display panel comprising a plurality of data lines, a plurality of scan lines, a display array, a data driver, and a scan driver. The data driver defines N data sections as one group and inserts a predetermined image section into the group. When the scan driver sequentially drives the N scan lines related to the group of the N data sections according to a first start pulse, the data driver provides the group of the N data sections to the pixels. When the scan driver sequentially drives the N scan lines related to the group of the C data sections according to a second start pulse, the data driver provides the predetermined image section to the pixels.

Description:
BACKGROUND  
       [0001]     The invention relates to a display panel, and in particular to a driving method for a display panel.  
         [0002]      FIG. 1  is a schematic diagram of a conventional liquid crystal display (LCD). The LCD  1  comprises a low voltage differential signaling (LVDS) module  10 , a memory device  11 , a timing controller  12 , and a panel  13 . The panel  13  comprises a data driver  14 , a scan driver  15 , and a display array  16 . The data driver  14  controls a plurality of data lines D 0  to D X , and the scan driver  15  controls a plurality of scan lines G 0  to G Y . The display array  16  is formed by interlacing data lines D 0  to D X  and scan lines G 0  to G Y . Each interlacing data line and scan line corresponds to a pixel, for example, interlacing data line D 0  and scan line G 0  correspond to pixel  16   a.    
         [0003]     The LVDS module  10  receives picture data and provides data enable signals, vertical synchronizing signals, horizontal synchronizing signals, and synchronizing clock to the timing controller  12 . In addition, the LVDS module  10  provides picture data to the memory device  11 . Data signals are provided to the data driver  14  and a scan control signal is provided to the scan driver  15  by the timing controller  12  in response to the data enable signals, vertical synchronizing signals, horizontal synchronizing signals, and the synchronizing clock. When the scan driver  15  drives thin film transistors (TFTs) in pixels  16   a , the data driver  14  provides data signals thereto. The memory device  11  receives data signals from the timing controller  12  and picture data from the LVDS module  10 . Using the picture data and the data signals, the memory device  11  provides even and odd numbered signals required to drive the data signals in the data driver  14 .  
         [0004]      FIG. 2  is a timing diagram of the conventional LCD of  FIG. 1 . The scan driver  15  sequentially outputs gate signals SG 0  to SG Y  to the scan lines G 0  to G Y  according to the scan control signal. For example, when receiving a gate signal, the scan line G 0  turns on the TFTs within all pixels in a row corresponding to the scan line G 0 , while the TFTs within all pixels in all other rows are turned off by other scan lines. When the TFTs within all pixels in a row are all turned on, the data driver  14  outputs the corresponding data signal SD 0  to the pixels in row through the data lines D 0  to D X . Each time the scan driver  15  finishes scanning all scan lines G 0  to G Y , the operation displaying a single frame is completed. Thus, image display is achieved by repeatedly scanning scan lines G 0  to G Y  and outputting data signals SD 0  to SD Y .  
         [0005]     The conventional LCD in.  FIG. 1  has a problem in that the image of a previous frame may overlap into a next frame due to the response time of a pixel.  FIG. 3  shows the response of a pixel changing from one data state DL 1  to another data state DL 2 . A pixel, such as pixel  16   a , has the data level DL 1  during a first frame F 1 . Subsequently, the pixel  16   a  has the data state level DL 2  during a second frame F 2 . However, there is a delay when the pixel transfers from the first level DL 1  to the second level DL 2  that creates blur on the screen. The appearance of blur impedes the application of dynamic display.  
       SUMMARY  
       [0006]     A display panel is provided. The display panel comprising a plurality of data lines, a plurality of scan lines, a display array, a data driver, and a scan driver. The display array comprises a plurality of pixels, each corresponding to a set of the interlacing data line and scan line. The data driver controls the data lines. The scan driver controls the scan line. The data driver defines N data sections as one group and inserts a predetermined image section into the group. When the scan driver sequentially drives the N scan lines related to the group of the N data sections according to a first start pulse, the data driver provides the group of the N data sections to the pixels through the data lines. When the scan driver drives the scan lines related to the group of the N data sections according to a second start pulse, the data driver provides the predetermined image section to the pixels through the data lines. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0007]     The invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the invention.  
         [0008]      FIG. 1  is a schematic diagram of a conventional liquid crystal display;  
         [0009]      FIG. 2  is a timing diagram for the conventional LVD of  FIG. 1 ;  
         [0010]      FIG. 3  shows the response of a pixel changing from one data state to another data state;  
         [0011]      FIG. 4  shows an embodiment of an LCD panel;  
         [0012]      FIG. 5  is a timing diagram for the embodiment of the LCD in  FIG. 4 ;  
         [0013]      FIG. 6  shows states of the control signals corresponding to the residuary data sections; and  
         [0014]      FIG. 7  is a flow diagram of an embodiment of a driving method for a display panel. 
     
    
     DETAILED DESCRIPTION  
       [0015]     LCD panels are provided. In some embodiments, after displaying an image of a frame for a predetermined time, a pixel displays a black image, a white image, or any image of a predetermined gray scale value until the pixel displays an image of a next frame. The image of a previous frame will not overlap in to a next frame, preventing blur phenomenon.  
         [0016]      FIG. 4  shows an embodiment of an LCD panel. The panel  4  comprises a data driver  40 , a scan driver  41 , and a display array  42 . The data driver  40  controls data lines D 4   0  to D 4   X . The scan driver  41  comprises a plurality of driving units, such as driving units  400  to  403 , each controlling a plurality of scan lines. In this embodiment, each driving unit controls four scan lines to conveniently illustrate the operation of the LCD panel in  FIG. 4 . For example, the driving unit  400  controls the scan lines G 40   0  to G 40   3 . The display array  42  comprises a plurality of pixels. Each set of interlacing data line and scan line corresponds to a pixel, for example, the interlacing data line D 4   0  and scan line G 40   0  correspond to the pixel  42   a.    
         [0017]     The scan driver  41  receives a gate clock signal CPV, a start vertical signal STV, and gate-on enable signals OE 0  to OE 3 . The gate-on enable signals OE 0  to OE 3  are respectively provided to the driving units  400  to  403 . Each gate-on enable signal has a waveform OE_D or a waveform OE_B (referring to  FIG. 5 ).  
         [0018]     Data driver  40  receives a data signal D 4  and a load signal Load. The data signal D 4  is partitioned into M data sections, each corresponding to the pixels on one scan line, so that M is equal to a number of scan lines. Every N data sections among the M data sections are defined as a group, and a black image section, a white image section, or an image section of a predetermined gray scale value is inserted into each group. In the embodiment in  FIG. 4 , one black image section is inserted into every four data sections, that is, four (N=4) sections are defined as a group corresponding to four scan lines, and a black image section is inserted into the group.  
         [0019]     Referring to  FIGS. 4 , and  5 , for example, the data sections S 40   0  to S 40   3  are defined as a group P 1  and correspond to the pixels along the scan lines G 40   0  to G 40   3  respectively. A black image section B 42  is inserted between the data sections S 40   2  and S 40   3  in the group P 1 . The load signal Load indicates that each data section of the data signal D 4  is loaded into the pixels on the corresponding scan line. The start vertical signal STV comprises two pulses DS and BS. The pulse DS indicates that a period (hereinafter referred to as “first process”) in which the data sections are loaded into the pixels on the scan lines begins, and the gate-on enable signal OE 0  is in the waveform OE_D during the first process. The pulse BS indicates that a period (hereinafter referred to as “second process”) in which the black image sections are loaded into the pixels on the scan lines begins, and the gate-on enable signals OE 0  is in the waveform OE_B during the second process.  
         [0020]     Referring to  FIG. 5 , when the pulse DS occurs on the start vertical signal STV, the first process starts and the driving units  400  to  403  operate sequentially. During the first process, the driving units  400  sequentially drive the scan lines G 40   0  to G 40   3  according to the rising edge of the gate clock signal CPV and the waveform OE_D of the gate-on enable signals OE 0 , and then the data driver  40  sequentially loads the data sections S 40   0  to S 40   3  into the pixels on the scan lines G 40   0  to G 40   3  according to the load signal Load. It is noted that the waveform OE_D corresponding to the black image section B 42  remains at a high level to block the black image section B 42  from being loaded into the pixels along the scan lines G 40   0  to G 40   3 .  
         [0021]     The driving units  401  to  403  also perform the operation described above in the first process. After the first process is performed for a predetermined interval t BK , the pulse BS occurs on the start vertical signal STV, so that the second process starts and the driving units  400  to  403  operate sequentially. In the embodiment in  FIGS. 4 and 5 , the pulse BS occurs on the start vertical signal STV at the time when the pixels on the scan lines G 42   0  to G 42   3  controlled by the driving unit  402  begin receiving the data sections S 42   0  to S 42   3 . During the second process, the driving unit  400  sequentially drives the scan lines G 40   0  to G 40   3  according to the rising edge of the gate clock signal CPV. The data driver  40  then loads the black image section B 40  into the pixels along the scan lines G 40   0  to G 40   3  of the group simultaneously according to a low level of the waveform OE_B. Similarly, the driving units  401  to  403  perform the operation described above in the second process.  
         [0022]     According to the embodiment in  FIGS. 4 and 5 , during the first process, the scan lines in one group are sequentially driven, and the data sections are sequentially loaded into the driven scan lines. After the first process is performed for a predetermined time, the second process begins, and a black image section is loaded into pixels on the scan lines in the group simultaneously. Moreover, the first process and the second process are simultaneously performed and respectively correspond to different groups of scan lines.  
         [0023]     The predetermined interval t BK  between the pulses DS and BS is determined according to requirements of the LCD panel. However, to display images correctly and maintain regular timing, the predetermined interval t BK  must exceed the total time for all pixels corresponding to one driving unit to receive the data sections.  
         [0024]     In the embodiment in  FIG. 4 , four (N=4) data sections are defined as one group, with M preferably a multiple of 4. If M is not a multiple of 4, the gate clock signal CPV, the load signal Load, and the gate-on enable signals OE 0  to OE 3  are paused during a period corresponding to the residual data sections. As shown by the marked cycle in  FIG. 6 , during a period R corresponding to the residual data sections, the gate clock signal CPV, the load signal Load, and the gate-on enable signals OE 0  to OE 3  remain in the previous respective state.  
         [0025]     Referring to  FIG. 5 , during the pulse DS of the start vertical signal STV in the first process, polarities of the data sections are determined according to a state of a polarity signal corresponding to the pulse DS. For example, in the Kth frame, a polarity signal POL (K) corresponding to the pulse DS is positive, and the polarities of the data sections are determined as “+−+− . . . ”. In the (K+1)th frame, a polarity signal POL (K+1) corresponding to the pulse DS is negative, and the polarities of the data sections are determined as “−+−+ . . . ”. In the second process, polarities of the black image sections are determined according to the polarity signal POL corresponding to the waveform OE_B and switch states during the pulse BS. As shown by the marked cycle in  FIG. 5 , in the Kth frame, a low level of the waveform OE_B corresponds to a pulse POL_N of the polarity signal POL (K), and the polarity of the black image section B 40  is negative. In the (K+1)th frame, the low level of the waveform OE_B corresponds to a pulse POL_P of the polarity signal POL (K+1), and the polarity of the black image section B 40  is positive. Thus, the polarities of the data sections are switched every scan line, and the polarities of the black image sections are switched each frame.  
         [0026]      FIG. 7  is a flow diagram of an embodiment of a driving method for a display panel. Referring to  FIGS. 4, 5 , and  7 , every four (N=4) data sections, such as the data sections S 40   0  to S 40   3 , are grouped into the group P 1  (step S 700 ), and the data sections S 40   0  to S 40   3  correspond to the scan lines G 40   0  to G 40   3  respectively. The black image section B 42  is inserted into the group P 1  of data sections S 40   0  to S 40   3  (step S 710 ). The scan lines G 40   0  to G 40   3  are driven by the driving unit  400  according to the pulse DS sequentially (Step S 720 ). The group P 1  of data sections S 40   0  to S 40   3  are provided to the pixels on the scan lines G 40   0  to G 40   3  according to the waveform OE_D of the gate-on enable signal OE 1  respectively (Step S 730 ). The scan lines G 40   0  to G 40   3  are driven by the driving unit  400  according to the pulse BS sequentially (Step S 740 ), and the black image data B 40  is simultaneously provided to the pixel corresponding to the scan lines G 40   0  to G 40   3  according to the waveform OE_B of the gate-on enable signal OE 1  (Step S 750 ).  
         [0027]     Thus, every N data sections among M data sections are defined as a group, and a black image section or a white image section is inserted into the group. The relative relationship between data sections and control signals, such as load signal, gate clock signal, polarity signal, start vertical signal, or gate-on enable signal, is fixed. A black image section or a white image section can be inserted in any position, and the control signals have to shift relatively.  
         [0028]     Finally, while the invention has been described by way of preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.