Abstract:
A networking device and method for transparently modifying a cyclic redundancy check (CRC) of a message so that higher layers (e.g., data link layer and above) can detect error duplication caused by scrambling and descrambling. No increase in the size of the messaging is needed so that the invention may be used for current and future technologies. In one embodiment, the networking device comprises logic employed within a physical layer of the device. This logic, referred to as a scrambler, modifies an original cyclic redundancy check (CRC) value associated with a message. This enables detection of a duplication of bit errors at a targeted destination of the message.

Description:
BACKGROUND 
     1. Field 
     The present invention relates to the field of data communications. In particular, this invention relates to a networking device and method for maintaining error detection functionality in the presence of error duplication. 
     2. General Background 
     Over the last few years, self-synchronous scramblers have been used in various types of networks in efforts to improve the security of data being transferred between a source and a destination. Currently, self-synchronous scramblers may be used in a synchronous optical network (e.g., Point-to-Point “PPP” over Synchronous Digital Hierarchy “SDH”/Synchronous Optical Network “SONET”), in an Asynchronous Transfer Mode (ATM) based network, or even in an Ethernet network. A scrambler is considered to be “self-synchronous” when the scrambled data transferred to the destination includes the state of the scrambler. 
     At the destination, a descrambler receives the scrambled data and attempts to recover the original, descrambled data. Unfortunately, in the recovery process, a descrambler duplicates the received bit errors. In certain situations, this may adversely effect error detection capabilities such as the reliability of Ethernet cyclic redundancy check (CRC) operations for example. An Ethernet CRC can detect 1-, 2-, or 3-bit errors for any burst error with a length up to thirty-two (32) bits. However, due to error duplication by the descrambler, the burst error may greatly exceed 32 bits. 
     Although it has been shown that the reduction in the error detection capability of the Ethernet CRC is negligible for random errors, the error duplication of the descrambler causes certain normally detectable errors to become undetectable and vice versa. For example, as shown in FIG. 1, “E(x)”  100  is a polynomial representation of the error on the received bit stream before descrambling, “T(x)”  110  is a polynomial representation of a transmitted message, “E′(x)”  120  is a polynomial representation of the duplication of the error E(x), and “D(x)”  130  is a polynomial representation of the error, E(x)+E′(x), realized at the destination after descrambling. As shown, for a first boundary error condition, bit errors  140  occurring outside T(x)  110  are now duplicated inside T(x)  110 . Likewise, for a second boundary error condition, bit errors occurring inside T(x)  150  are duplicated and now are partially outside T(x)  110 . Thus, error detection in the presence of the scrambler may become less reliable. Of course, when D(x)  130  is entirely contained in T(x)  110 , the error detection capabilities of CRC are not comprised when the CRC and the scrambler polynomials have no factors in common. 
     SUMMARY 
     The present invention relates to a networking device and method for transparently modifying a cyclic redundancy check (CRC) of a message so that higher layers (e.g., data link layer and above) can detect error duplication caused by scrambling and descrambling. No increase in the size of the messaging is needed so that the invention may be used for current and future technologies. In one embodiment, the networking device comprises logic employed within a physical layer of the device. This logic, referred to as a scrambler, modifies an original cyclic redundancy check (CRC) value associated with a message. This enables detection of a duplication of bit errors at a targeted destination of the message. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will become apparent from the following detailed description of the present invention in which: 
     FIG. 1 is an illustrative embodiment of a first boundary error condition and a second boundary error condition experienced during the transmission of a message. 
     FIG. 2 is an illustrative embodiment of a network utilizing the present invention. 
     FIG. 3 is an illustrative embodiment of a networking device implemented in the network of FIG.  2 . 
     FIG. 4 is an illustrative embodiment of a data structure of a transmitted message such as an Ethernet frame. 
     FIG. 5 is an illustrative embodiment of a flowchart featuring the operations performed to generate a CRC value. 
     FIG. 6 is an illustrative embodiment of the operations of a self-synchronous scrambler implemented in a physical layer of a networking device. 
     FIG. 7 is an illustrative embodiment of the operations of a self-synchronous descrambler, implemented in a physical layer of a networking device. 
     FIG. 8 is an illustrative embodiment of the duplication of bit errors for a self-synchronous x N +1 descrambler. 
     FIG. 9 is an illustrative embodiment of the operations of a self-synchronous scrambler of FIG. 6 to correct for bit error duplication caused by a first boundary error condition. 
     FIG. 10 is an illustrative embodiment of the operations of a self-synchronous descrambler of FIG. 7 to correct for bit error duplication caused by the first boundary error condition. 
     FIG. 11 is an illustrative embodiment of the operations of a self-synchronous scrambler of FIG. 6 to correct for bit error duplication caused by a second boundary error condition. 
     FIG. 12 is an illustrative embodiment of the operations of a self-synchronous descrambler of FIG. 7 to correct for bit error duplication caused by the second boundary error condition. 
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention relate to a networking device and method for maintaining error detection functionality in the presence of error duplication without message modifications. Herein, in one embodiment, error detection functionality is maintained by including bit errors occurring up to N bits before the beginning of a transmitted message and/or after the ending of the transmitted message in cyclic redundancy check (CRC) calculations. 
     Herein, certain terminology is used to describe various features of the present invention. In general, a “network” comprises one or more networking devices in communication with each other over a link. A “networking device” comprises hardware and/or software used to transfer information to a selected destination. Examples of a networking device include a router, a switch, a repeater, a computer (e.g., server, desktop, laptop, hand held, etc.), set-top box, or any device operating as a gateway for outgoing or incoming data. The networking device includes logic such as hardware and/or software (e.g., a program being code performing certain functionality when processed) employed within the physical layer. This hardware and/or software may include a scrambler that rearranges information before transmission and/or a descrambler that rearranges incoming information back to its original, unscrambled format. A “link” is a connection between two networking devices that supports the transmission or reception of information over a selected medium such as, for example, Plain Old Telephone System (POTS) lines, twisted pair, optical fiber, or wireless (e.g., satellite, radio frequency, infrared, etc.). Of course, other link types may be considered without departing from the spirit and scope of the invention. 
     “Information” generally comprises one or more signals having one or more bits of data, address, control or any combination thereof transmitted in accordance with any chosen messaging scheme. A “message” is a selected grouping of information. For example, the message may be packet based and include a routing field (e.g., destination address, and/or source address, type or length, etc.), a data field (e.g., data, padding, etc.) and a frame check sequence (FCS) field. The FCS field includes the cyclic redundancy check (CRC) value, which is computed from at least a portion of the contents of the routing and data fields. An Ethernet frame would constitute a particular packet-based message. The term “CRC[]” indicates a CRC operation performed on the contents of a bit stream such as any transmitted message including an Ethernet frame. 
     I. General Overall Architecture 
     Referring to FIG. 2, an illustrative embodiment of a network  200  utilizing the invention is shown. Herein, the network  200  comprises a first networking device (transmitter)  210  in communication with a second networking device (receiver)  220 . The communication is established by one or more links  230 . The network  200  may be an Ethernet where links  230  support transmission rates of either 10 Megabit per second (Mbps), 100 Mbps, 1 Gigabit per second (Gbps), 10 Gbps and even faster transmission rates. Of course, the network  200  may be non-Ethernet based. 
     II. Network Embodiment 
     A. Networking Device with X N +1 Scrambler 
     Referring now to FIG. 3, an illustrative embodiment of the first networking device  210  is shown. The first networking device  210  is configured in accordance with Open System Interconnection (OSI) and includes a physical layer  300  and a data link layer  310 . More specifically, the physical layer  300  handles data transmissions over links  230  while the data link layer  310  groups the data, performs error correction and detection, and controls the flow of data over link  230 . For this invention, a scrambler  320  is employed within the physical layer  300  and is configured in accordance with any selected derivation of polynomial representation “S(x)” as set forth in equation (1), provided that it has no factors in common with a CRC generation polynomial “G(x)” described below. 
     
       
           S ( x )= x   N +1  (1) 
       
     
     B. Error Detection 
     Error detection is a technique used to determine whether the transmission of data occurred without any errors. One error detection technique uses a standard cyclic redundancy check (CRC) function. Prior to transmission, the CRC function modifies a transmitted message so that it is always divisible (modulo 2) by a predetermined CRC polynomial at the second networking (receiver) device. As shown in FIG. 4, the CRC function is used to generate an i-bit CRC value  400  (e.g., “i” is a positive whole number) for insertion into a field (e.g., FCS field)  410  of a transmitted message  420  (e.g., an Ethernet frame). The CRC value  400  is computed based on the contents of at least a routing field  430  (e.g., a destination address) and a data field  440 , namely for the routing field  430  through the end of the data field  440 , inclusive. The encoding by the CRC value is defined by G(x) where “b i ” is either a “0” (representing that no term is present) or a “1” (representing that a term is present). 
     
       
           G ( x )= x   i +( b   i−1 ) x   i−1 +( b   i−2 ) x   i−2   +. . . +b   1   x +1  (2) 
       
     
     More specifically, as shown in a flowchart of FIG. 5, the CRC value corresponding to a transmitted message is computed by selecting a predetermined number of bits (K) from the transmitted message as coefficients for a polynomial M(x) of degree K−1 (block  500 ). Of course, for the Ethernet frame however, most significant i-bits of the Ethernet frame may be complemented prior to selecting the K bits. M(x) is multiplied by x i  (e.g., to perform a 32-bit shift to the left when i=32) as set forth in block  510 . Then, the result M(x)x i  is divided by G(x), which produces a remainder R(x) having a degree less than or equal to i−1 (block  520 ). This bit sequence (R(x)) may be complemented for Ethernet and the result producing the CRC value. Alternatively, the coefficients of R(x) are collectively considered to be an i-bit sequence and constitute the CRC value. The CRC value is placed in the FCS field so that the x i−1  term is the most significant bit of the first octet, and the x 0  term is the least significant bit of the last octet (block  530 ). The transmitted message T(x) is equivalent to modulo 2 addition of M(x)x i  and FCS. It is appreciated that “modulo 2 addition” is the same as modulo 2 subtraction, which is the same as an Exclusive-OR (XOR) of the corresponding bit patterns. 
     C. Self-Synchronous Scrambler/Descrambler 
     Referring now to FIGS. 6 and 7, an illustrative embodiment of the operations of a self-synchronous scrambler and descrambler implemented in a physical layer of a networking device is shown. For clarity sake, the representative polynomial for the self-synchronous scrambler and descrambler is x N +1. Thus, at any given time, the state of the scrambler/descrambler is the contents of the respective N-bit shift register. 
     Referring to FIG. 6, a scrambler  600  includes an N-bit shift register  610  clocked by a clocking signal (CLK 1 ). At each CLK 1  cycle, a most significant bit of the shift register  610  is loaded into a first input of a logic gate  620  (e.g., Exclusive-OR “XOR”). Concurrently, a bit of a descrambled bit stream  630  is loaded into a second input of the logic gate  620 , which produces a bit of a scrambled bit stream  640 . This bit is also fed back as a least significant bit of the shift register  610  for subsequent scrambling operations. 
     It is noted that the scrambler  600  can be initially set to any arbitrary value. For security purposes, the initial state of the scrambler  600  is usually set to a random value. The initial descrambler state is irrelevant because it will acquire the correct state from the scrambled data stream. The first N descrambled bits (e.g., for an x N +1 descrambler) will be wrong because the descrambler is still collecting the correct state. 
     Referring now to FIG. 7, a descrambler  700  corresponding to x N +1 scrambler  600  includes an N-bit shift register  710  clocked by a clocking signal (CLK 2 ), which may differ from the clock frequency of CLK 1 . At each CLK 2  cycle, a most significant bit of the shift register  710  is loaded into a first input of logic gate  720  (e.g., exclusive-OR “XOR”). Concurrently, a bit of a scrambled bit stream  730  is loaded into a second input of the logic gate  720  and as a least significant bit of the shift register  710  for subsequent descrambling operations to produce a descrambled bit stream  740 . Thus, bit errors are duplicated N-bits later. For example, as shown in FIG. 8, a single bit error  800  descrambled by the x N +1 descrambler  700  of FIG. 7 produces a double bit error  810  where the bit errors are separated by N−1 zeros. 
     D. Techniques to Maintain Error Detection Functionality 
     As described below, two techniques have been developed to avoid inaccurate error detection caused by boundary error conditions without increasing the message framing size by even a single bit. These techniques may be performed either separately to correct a specific boundary error condition or collectively to eliminate the effects of error duplication without increasing the size of the message or changing its format. The first technique overcomes the first boundary error condition by extending the reach of the CRC calculation to cover all the bit errors occurring up to N bits before the beginning of a transmitted message T(x) when employing a scrambler configured in accordance with a polynomial S(x) of degree N (e.g., a x N +1 scrambler). This makes the error {tilde over (D)} (x), detectable when D(x) is detectable when using standard CRC calculations. The second technique overcomes the second boundary error condition by extending the reach of the CRC calculation to include any error duplication that spans beyond T(x) in order to eliminate problems caused by error duplication outside T(x). 
     (1) Overcoming the First Boundary Error Condition 
     Referring now to FIGS. 9 and 10, a first technique for extending the reach of the CRC calculation to cover all bit errors occurring up to N bits before the beginning of the transmitted message T(x)  420  of FIG. 4 is shown, provided the x N +1 scrambler is used. For clarity sake, the scrambler is illustrated as a x 43 +1 scrambler (where N=43). 
     At the physical layer of the first networking device, a state  900  of the scrambler at the moment the first bit of T(x)  420  is about to be scrambled is loaded into a CRC engine  910 . The CRC engine  910  is initialized prior to receiving the first input bit. After scrambler state  900  has been loaded, a number of zero bits  920  equal to the number of bits contained in T(x)  420  is loaded into the CRC engine  910 . The bit sequence formed by the scrambler state (bits x N  to x 1  in this order) followed by the zero bits  920  which are equal to the length of T(x) is taken as the coefficients of a polynomial M(x). This polynomial M(x) is then used by the CRC engine  910  to calculate a resulting CRC value  930  (labeled “CRCV1”) as described in FIG.  5 . Thereafter, resulting CRC value  930  undergoes arithmetic operations (e.g., modulo 2 addition) with contents of the FCS field  410  to produce a modified CRC value. This “modified CRC value” is placed subsequently in the FCS field  410  of T(x)  420 . This entire operation prefers a delay of at least four octets before transmission to allow the addition of the resulting CRC value  930  to the contents of the FCS field  410 . 
     As shown in FIG. 10, at the second networking (receiver) device, the same operations as described above are performed, except for using as input to a CRC engine  950  a state  940  of the descrambler (e.g., the contents of the N-bit shift register from bits x N -x 1 ) immediately before the first bit of T(x)  420  is descrambled. This bit sequence acts as the coefficients of a polynomial M(x) as described in FIG.  5 . The resultant CRC value  960  (labeled “CRCV2”) undergoes arithmetic operations (e.g., modulo 2 addition) with the contents of the FCS field  410  of T(x)  420  recovered after descrambling. 
     If there are no transmission errors, the content of the FCS field  410  is restored from its modified CRC value to its original CRC value because the scrambler and descrambler states  900  and  940  are identical at the first and second networking devices immediately before the first bit of the message is scrambled/descrambled. However, if there are transmission errors, the CRC value of the received message (referred to as “N(x)”) is equivalent to the CRC value of the error realized at the second networking device (referred to as “D(x)”) as shown in the derivation of equation (3). If the error message E(x) is detectable by the CRC, then the error message after the error duplication of the descrambler is also detectable. 
     
       
           N ( x )= T ( x )+ I   L ( x )+ {tilde over (D)} ( x )+ I   T ( x ), 
       
     
     where 
     “+” denotes modulo two addition where I L (X)+I L (X)=0, 
     T(x) is the original message received at the physical layer of the first networking (transmitter) device, 
     I L ( X ) is the resulting CRC value ( 930 ), 
     {tilde over (D)}(x)=E i +E′(x) is the error message after descrambling (where E i (x) is part of E(x) inside T(x), 
     I T (x) is the resultant CRC value ( 960 ), and 
     I T (x)=I L (x)+CRC[E o (x)] where E o (x) is the error message in the descrambler state at the second networking (receiver) device. 
     Thus, the CRC value of the received message (CRC[N(x)]) is equivalent to the CRC value of the error realized at the second networking device (CRC[D(x)]) as shown below: 
       N ( x )= T ( x )+ {tilde over (D)} ( x )+ CRC[E   o ( x )] 
     
       
           CRC[N ( x )]= CRC[T ( x )]+ CRC[{tilde over (D)} ( x )]+ CRC[E   o ( x )], since  CRC[CRC[E   o ( x )]]= CRC[E   o ( x )] 
       
     
     
       
           CRC[N ( x )]= CRC[{tilde over (D)} ( x )+E o ( x )], since  CRC[T ( x )]=0 
       
     
     
       
         = CRC[E   i ( x )+ E′ ( x )+ E   o ( x )] 
       
     
     
       
         = CRC[E ( x )+ E′ ( x )] 
       
     
     
       
         = CRC[D ( x )] 
       
     
     (2) Overcoming the Second Boundary Error Condition 
     Referring now to FIGS. 11 and 12, a second technique for overcoming the second boundary error condition by extending the reach of the CRC calculation to cover any bit error duplication that exceeds T(x) by a selected number (M) of bits is shown, provided the scrambler is configured in accordance with a selected polynomial representation S(x) of degree N. For clarity, the operations for the second technique are based on the use of a x 43 +1 scrambler. 
     At the physical layer of the first networking device, a scrambler state  1000  (immediately after the last bit of T(x)  420  is scrambled) is loaded into an initialized CRC engine  1010 . After the last bit is processed by the CRC engine  1010 , the resulting CRC value (labeled “CRCV3”)  1020  is used to calculate an i-bit sequence (labeled “CRCV4”)  1030  that is added modulo 2 to bits x 43+i−1  to x 43  of T(x)  420  after scrambling. CRCV4  1030  is selected so that modifications to bits x 43+i−1  to x 43  (e.g., x 74 -x 43  for a 32-bit CRC value i=32) are reproduced in the FCS field  410  of the transmitted message T(x) after descrambling at the second networking device. 
     The i-bit sequence CRCV 4   1030  is calculated such that the CRC value of the bit pattern obtained by extending CRCV 4  and its duplication (labeled “CRCV 4  (X 43 +1)”) to the right with 43 zero bits is equal to the CRCV 3   1020 , that is: 
       CRC[CRCV 4( x   43 +1) x   43   ]=CRCV 3  (4) 
     Thus, the R—CRC engine  1040  produces CRCV 4   1030  and operates as an inverse function to the operations set forth in equation (4). A table listing the CRCV 3  and corresponding CRCV 4  values for a x 43 +1 scrambler is shown below. 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 CRCV3 
                   
                 CRCV4 
                   
               
               
                   
                 (hex) 
                   
                 (hex) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 0000 
                 0001 
                 F3A7 
                 749C 
               
               
                   
                 0000 
                 0002 
                 E38F 
                 F48F 
               
               
                   
                 0000 
                 0004 
                 C3DE 
                 F4A9 
               
               
                   
                 0000 
                 0008 
                 837C 
                 F4E5 
               
               
                   
                 0000 
                 0010 
                 0238 
                 F47D 
               
               
                   
                 0000 
                 0020 
                 0471 
                 E8FA 
               
               
                   
                 0000 
                 0040 
                 08E3 
                 D1F4 
               
               
                   
                 0000 
                 0080 
                 11C7 
                 A3E8 
               
               
                   
                 0000 
                 0100 
                 238F 
                 47D0 
               
               
                   
                 0000 
                 0200 
                 471E 
                 8FA0 
               
               
                   
                 0000 
                 0400 
                 8E3D 
                 1F40 
               
               
                   
                 0000 
                 0800 
                 18BB 
                 2337 
               
               
                   
                 0000 
                 1000 
                 3176 
                 466E 
               
               
                   
                 0000 
                 2000 
                 62EC 
                 8CDC 
               
               
                   
                 0000 
                 4000 
                 C5D9 
                 19B8 
               
               
                   
                 0000 
                 8000 
                 8F73 
                 2EC7 
               
               
                   
                 0001 
                 0000 
                 1A27 
                 4039 
               
               
                   
                 0002 
                 0000 
                 344E 
                 8072 
               
               
                   
                 0004 
                 0000 
                 689D 
                 00E4 
               
               
                   
                 0008 
                 0000 
                 D13A 
                 01C8 
               
               
                   
                 0010 
                 0000 
                 A6B5 
                 1E27 
               
               
                   
                 0020 
                 0000 
                 49AB 
                 21F9 
               
               
                   
                 0040 
                 0000 
                 9356 
                 43F2 
               
               
                   
                 0080 
                 0000 
                 226D 
                 9A53 
               
               
                   
                 0100 
                 0000 
                 44DB 
                 34A6 
               
               
                   
                 0200 
                 0000 
                 89B6 
                 694C 
               
               
                   
                 0400 
                 0000 
                 17AD 
                 CF2F 
               
               
                   
                 0800 
                 0000 
                 2F5B 
                 9E5E 
               
               
                   
                 1000 
                 0000 
                 5EB7 
                 3CBC 
               
               
                   
                 2000 
                 0000 
                 BD6E 
                 7978 
               
               
                   
                 4000 
                 0000 
                 7E1D 
                 EF47 
               
               
                   
                 8000 
                 0000 
                 FC3B 
                 DE8E 
               
               
                   
                   
               
             
          
         
       
     
     At the second networking (receiver) device, the same operation is performed to calculate CRCV 4 , but using the CRCV 3  calculated from the descrambler state immediately after the last bit of T(x) is descrambled as the input. The i-bit sequence CRCV 4  is then added modulo 2 to the FCS field  410  and to the bits x 43+i−1  to x 43  T(x) after descrambling. 
     If there are no transmission errors, the above operation at the second networking device restores the transmitted message T(x) to its original bit sequence, since the scrambler and descrambler states will be identical after the last bit of the transmitted message is scrambled/descrambled. Note that i-bit sequence CRCV 4  is also added to the FCS field  410  at the second networking device because of the duplication effect the descrambler has on the CRCV 4  that was added after scrambling at the first networking device. 
     If there are transmission errors, the received message after descrambling (and after CRCV 4  is added to the indicated fields) can be written as the following: 
     
       
           N ( x )= T ( x )+ J   1 ( x )(x 43 +1)+ {tilde over (D)} ( x )+ J   r ( x )(x 43 +1), where  (5) 
       
     
     “T(x)” is the original message received for transmission at the physical layer of the first networking device (transmitter), 
     “J t (x)” is the polynomial representation of the i-bit sequence CRCV 4  that is added to the bits x 43+i−1  to x 43  of T(x) at the transmitter after scrambling (the term “x 43 +1” accounts for duplication of J t (x) by the descrambler at the second networking device), 
     {tilde over (D)}(x)=E(x)+E i (x) is the error message after descrambling (E′ i (x) is the part of the duplication of E(x) that is inside T(x)), and 
     “J r (x)” is the polynomial representation of the i-bit sequence CRCV 4  that is added to the bits x 43+i−1  to x 43  and to the FCS field at the second networking device (receiver) after descrambling (the term “x 43 +1” accounts for the two additions of CRCV 4  that occur 43 bits from each other). 
     Until now, we have assumed that all of these message polynomials are expressed having their x o  terms coinciding with the rightmost bit of T(x). However, in order to express the part of the error E(x) that is duplicated outside T(x), we will have to express all of these message polynomials with their x o  terms coinciding with the rightmost bit of T(x)x 43 . To indicate a polynomial that is expressed using this new reference, we use dots ( . . . ) on top of the polynomial identifier. Thus, equation (5) can be rewritten as 
     
       
         ( x )=( x )+ t ( x )( x   43 +1)+( x )+ r ( x )( x   43 +1), where  (6) 
       
     
     
       
         ( x )= N ( x ) x   43 ; ( x )= T ( x ) x   43 ; ( x )= J   t ( x ) x   43 ; ( x )= {tilde over (D)} ( x ) x   43 , and  r ( x )= J   r ( x ) x   43 . 
       
     
     Also that (x)=E(x)x 43 ;  i ′(x)=E i ′(x)x 43 . 
     Since  r (x)= t (x)+R_CRC[CRC[′ o  (x)]]x 43 , 
     
       
         ( x )=( x )+( x )+ R   —   CRC[CRC[ ′ o ( x )]] x   43 ( x   43 +1)  (7) 
       
     
     But since CRC[T(x)]=0, and 
     
       
           CRC[R   —   CRC[CRC[′   o ( x )]] x   43 ( x   43 +1)]= CRC [′ o ( x )], then, 
       
     
     
       
           CRC [( x )]= CRC [( x )]+ CRC [′ o ( x )] 
       
     
     
       
           =CRC [( x )+′ o ( x )] 
       
     
     
       
           =CRC [( x )+′ i ( x )+′ o ( x )] 
       
     
     
       
           =CRC [( x )+′( x )] 
       
     
     
       
           =CRC [( x )], 
       
     
     where (x)=(x)+′(x) is the complete error message with error duplication and ′(x) is the polynomial representation of the duplication of (x). Since ′(x)=N(x)x 43 , CRC[(x)]=0 if and only if CRC[N(x)]=0. Thus, the proposed technique makes all detectable errors on the medium detectable by a high layer that checks the CRC of the received message. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.