Abstract:
Multiple microelectromechanical (MEM) device substrates, such as MEM mirror substrates, are tiled on a base substrate. Each MEM device substrate can include one or more MEM devices such as mirrors. By including one or a relatively small number of devices on a MEM device substrate, the MEM device substrate can be manufactured with relatively high yield and can be tested prior to tiling onto the base substrate. The separate MEM device substrates and base substrate can also reduce crosstalk and/or other signal interference which could degrade MEM device operation. Solder bumps and/or other mounting techniques may be used to mount the MEM device substrates onto the base substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application claims the benefit of provisional application Serial No. 60/268,784, filed Feb. 14, 2001, entitled Tiled Microelectromechanical Mirror Arrays and Fabrication Methods, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    This invention relates to microelectronic devices and fabrication methods, and more particularly to microelectromechanical devices and fabrication methods.  
         BACKGROUND OF THE INVENTION  
         [0003]    Microelectromechanical (MEM) devices recently have been developed as alternatives for conventional electromechanical devices, such as relays, actuators, valves and sensors. MEM devices are potentially low-cost devices, due to the use of simplified microelectronic fabrication techniques. New functionality also may be provided because MEM devices can be much smaller than conventional electromechanical devices.  
           [0004]    Arrays of MEM devices are widely used for switching, sensing and/or other applications. For example, arrays of microrelays, microsensors, microactuators and/or micromirrors may be used for many applications. More specifically, MEM mirror arrays are widely used, for example, in optical cross-connect (OXC) switches. In a MEM mirror array, an array of moveable mirrors is fabricated in a microelectronic substrate. The mirrors may be moved individually to perform optical switching.  
           [0005]    Unfortunately, it may be difficult to fabricate large arrays of MEM devices with acceptable manufacturing yields. For example, in a 16×16 optical cross-connect switch, an array of 256 movable mirrors may be needed. It may be difficult to manufacture such an array with acceptable manufacturing yields.  
         SUMMARY OF THE INVENTION  
         [0006]    Embodiments of the invention can tile multiple MEM device substrates, such as MEM mirror substrates, on a base substrate. Each MEM device substrate can include one or more MEM devices such as mirrors. By including one or a relatively small number of devices on a MEM device substrate, the MEM device substrate can be manufactured with relatively high yield and can be tested prior to tiling onto the base substrate. The separate MEM device substrates and base substrate can also reduce crosstalk and/or other signal interference which could degrade MEM device operation. Solder bumps and/or other mounting techniques may be used to mount the MEM device substrates onto the base substrate. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1 is a cross-sectional view of MEM modules according to some embodiments of the present invention.  
         [0008]    FIGS.  2 A- 2 D are cross-sectional views of MEM modules according to some embodiments of the present invention during intermediate fabrication steps for forming a deep oxide pad according to some embodiments of the present invention.  
         [0009]    FIGS.  3 A- 3 D are cross-sectional views of MEM modules according to other embodiments of the present invention during intermediate steps of fabricating a mirror according to other embodiments of the present invention.  
         [0010]    FIGS.  4 A- 4 I are cross-sectional views of MEM modules according to yet other embodiments of the invention during intermediate fabrication steps according to yet other embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]    The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.  
         [0012]    Referring to FIG. 1, a plurality of MEM device substrates, such as MEM mirror substrates  120 , are mounted on a base substrate  110 , to form a tiled MEM device module, such as a tiled MEM mirror module  100 . The MEM mirror substrates  120  may be mounted on the base substrate  110  using solder bumps  130  and/or other mounting structures. Each MEM mirror substrate  120  can include one or more MEM mirrors, and may be fabricated as will be described below. The base substrate  110  may include mirror electrodes  140  that can be used to control movement of the mirrors in the MEM mirror substrates  120  and can also include driver electronics and/or other microelectronic devices that can be used, for example, in an optical cross-connect switch.  
         [0013]    In some embodiments, each MEM mirror substrate  120  can include an array of four mirrors, in two rows and two columns. A 4×4 array of MEM mirror substrates  120  may be mounted on a base substrate  110  in four rows and four columns, to provide an array of 256 mirrors for a 16×16 optical cross-connect switch. This arrangement can allow higher manufacturing yields than may be obtained with a single array of 256 mirrors in a single MEM mirror substrate. It also will be understood that other numbers of mirrors and MEM mirror substrates may be used. Moreover, a single MEM mirror substrate  120  containing one or more mirrors also may be mounted on a base substrate  110 .  
         [0014]    Methods of fabricating tiled MEM mirror modules  100  according to some embodiments of the invention now will be described. In fabricating MEM mirror substrates  120 , a deep oxide pad process may be used. A deep oxide pad process first will be described in connection with FIGS.  2 A- 2 D. Then, fabrication of a MEM mirror substrate  120  and mounting on a base substrate  110  will be described in connection with FIGS.  3 A- 3 D and  4 A- 41 .  
         [0015]    Referring now to FIG. 2A, a Semiconductor-On-Insulator (SOI) substrate or wafer  200  is provided, that includes a bulk semiconductor region  210 , a thin semiconductor-on-insulator layer  220  and a buried insulator layer  230  therebetween. Region  210  and layer  220  may comprise monocrystalline silicon, and layer  230  may comprise a buried silicon oxide layer. The design and fabrication of SOI wafers are well known to those having skill in the art and need not be described further herein.  
         [0016]    As shown in FIG. 2B, a layer of silicon nitride  240  or other masking layer is formed and patterned. As shown in FIG. 2C, a Deep Reactive Ion Etch (DRIE) is performed through the exposed SOI layer  220  down to the buried insulator layer  230 , to form an array or grating of silicon fingers  250 . The array or grating of silicon fingers  250  may be formed, so as to allow thermal oxidation thereof, to form a solid silicon dioxide pad having a relatively large area and a relatively large depth. It will be understood that if silicon fingers  250  are not used, it may be difficult to fully oxidize the large area to the depth of the SOI layer  220 , for example to a depth of 20 μm. It also may be difficult to form a deep, thick silicon dioxide layer using conventional chemical vapor deposition. In sharp contrast, as shown in FIG. 2C, if the silicon fingers  250  are sufficiently narrow, for example 1.81 μm wide, and have a sufficiently close pitch, such as a pitch of 3.4 μm, the silicon fingers  250  may be fully oxidized and coalesce to form an unbroken outer surface that is coplanar with SOI layer  220 .  
         [0017]    Referring now to FIG. 2D, thermal oxidation is performed to consume the silicon fingers  250  and to produce a pad oxide  260  that can fill the gaps between the fingers  250  due to the increase in volume of silicon dioxide compared to silicon, and that may be planarized to about 2000 Å. Stated differently, the dimensions of the silicon fingers  250  of FIG. 2C may be selected so as to provide a pad  260  that is fully oxidized and that is of approximately the same thickness (20 μm) as the SOI layer  220 . It also will be understood that the silicon fingers  250  need not be fully consumed, as long as the pad  260  is sufficiently oxidized to planarize layer  220  and to be released during later processing steps, as will be described below. Finally, a slight rippling of the surface of the oxide pad  260  may be present, as shown in FIG. 2D, due to the oxidation of the tips of the fingers  250 . This rippling can be reduced, if desired, using conventional planarization techniques.  
         [0018]    A deep oxide pad process of FIGS.  2 A- 2 D may be used to form a MEM mirror substrate  120  using processes illustrated in FIGS.  3 A- 3 D and  4 A- 4 I. It will be understood that the mirrors that are fabricated in FIGS.  3 A- 3 D have one degree of freedom (i.e., can be rotated about one axis). However, mirrors with two degrees of freedom also may be fabricated using conventional gimbal structures and used in embodiments of the invention. The mirror surface may have a thickness of between about 5 μm and about 25 μm of single crystal silicon, and may be formed in the SOI layer  220 , as will be described below. A mirror hinge may be formed of 1.5 μm thick polysilicon, which can be deposited to a total thickness variation of 0.05 μm as will be described below.  
         [0019]    Referring now to FIG. 3A, a top view of the SOI layer  220  is shown, in which the nitride mask  240  has been removed, and a pair of deep oxide pads  260  have been fabricated, for example using the fabrication process of FIGS.  2 A- 2 D. As shown in FIG. 3B, anchors  310  and hinges  320  may be formed, for example by depositing, patterning and etching a polysilicon layer. As also shown in FIG. 3B, the hinges  320  are formed at least partially on the deep oxide pad  260 , so that the deep oxide pad can become the sacrificial release layer for the hinges  320 .  
         [0020]    Then, as shown in FIG. 3C, a silicon trench or moat is etched to define the mirror  330  and a surrounding frame in the SOI layer  220 . For example, deep reactive ion etching can be performed that can stop at the buried insulator layer  230 , as shown in FIG. 3C. Then, as shown in FIG. 3D, the buried oxide layer  230  and the oxide pads  260  are etched, to thereby free the hinges  320  and the mirror  330 . As will be shown below, the buried oxide layer  230  and deep oxide pads  260  may be etched using a backside etch and/or a frontside etch. Accordingly, a hinged mirror is formed. The thickness of the deep oxide pads  260 ,which are removed, can allow sufficient space for movement of the hinges  320  during actuation of the mirror  330 . For example, a trench of about 20 μm in depth may be formed, which may be on the order of ten times thicker than the buried oxide layer  230 .  
         [0021]    FIGS.  4 A- 4 I describe additional steps for fabricating MEM mirror substrates  120 , and for mounting the MEM mirror substrates  120  on a base substrate  110  to form tiled MEM mirror arrays  100  such as those illustrated in FIG. 1. As with FIGS.  3 A- 3 D, a one degree of freedom mirror is shown, but a two degree of freedom mirror can be formed using gimbal structures. Additionally, different thicknesses may be provided for the mirror and the hinge.  
         [0022]    More particularly, as shown in FIG. 4A, an SOI wafer  200  may be provided as was described in connection with FIG. 2A. The SOI layer  220  may be between about 5 μm and about 25 μm thick in some embodiments of the invention. Then, as shown in FIG. 4B, the deep oxide pads  260  are formed, for example using a process shown in FIGS.  2 A- 2 D. Then, in FIG. 4C, the polysilicon hinges  320  and anchors  310  may be defined as was described in FIG. 3B. The polysilicon hinges  320  and anchors  310  may be of the same thickness or different thicknesses. In some embodiments, a thickness of about 1.5 μm may be used.  
         [0023]    Then, as shown in FIG. 4D, a layer is formed and patterned that can provide an underbump metallurgy (UBM)  410  and a mirror metal  420 . As is well known, a UBM may be used as a plating base for plating solder bumps. The mirror metal  420  may provide a reflective surface and/or a stress-relieving surface opposite a second mirror surface (described below). The UBM  410  and mirror metal  420  may be patterned from a single layer, for example comprising gold.  
         [0024]    Then, referring to FIG. 4E, the bulk semiconductor region  210  of the SOI substrate  200  may be etched, for example using deep reactive ion etching (DRIE), to expose the buried oxide layer  230 . As shown in FIG. 4F, a wet etch and/or other conventional etch may be performed to remove the buried oxide layer  230  and the oxide pads  260 . A single etch step also may be used. A second layer of mirror metal  430 , such as gold, then may be formed on the backside of the mirror  330 , as shown in FIG. 4G. It will be understood that dual mirror metal layers  420  and  430  may be used to maintain planarization of the mirror by equalizing stress, and/or to provide reflective surfaces on both faces of the mirror. The structure of FIG. 4G therefore can provide a complete MEM mirror substrate  120 . It will be understood that, as was described above, multiple mirrors may be formed on the MEM mirror substrate  120 .  
         [0025]    Referring now to FIG. 4H, the MEM mirror substrate  120  is mounted onto a base substrate  110 , also referred to as an IC/electrode die, for example using solder bumps  130  and/or other conventional techniques. It will be understood that solder bumps may be used, because they can provide a controlled separation between the MEM mirror substrate  120  and the base substrate  110 , and also can provide lateral alignment of the MEM mirror substrates  120  relative to the base substrate  110 . Electrostatic actuator electrodes  140  and/or other microelectronic devices also may be formed in the base substrate  110 . As shown in FIG. 41, adequate space x, such as a 35 μm space, may be maintained between the edge of the mirror  430  and the bulk silicon region  210  that remains, so as to prevent the bulk silicon region  210  from shadowing optical reflection from the mirror  330 , for a mirror tilt of up to four degrees. For larger tilts, larger gaps may need to be present and/or the bulk silicon layer  210  may be fully or partially removed.  
         [0026]    It also will be understood that, although FIGS. 4H and 4I show only a single MEM mirror substrate  120  flip-chip mounted on a base substrate  110 , multiple MEM mirror substrates  120  may be flip-chip mounted on the base substrate  110 , as was described in FIG. 1. Accordingly, MEM mirror substrates may be fabricated with improved yield and then may be packaged to form a larger MEM mirror array that may be used, for example, for optical cross-connect switching.  
         [0027]    In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.