Abstract:
A charge amplifier with DC offset canceling for use in a pixel element of an MOS image sensor is disclosed. The charge amplifier can be manufactured using a standard CMOS single polycrystalline process, making it much more cost effective than prior art designs. The charge amplifier includes an operational amplifier, a source capacitor, a series capacitor, and a feedback capacitor. The source capacitor holds the input signal. The output of the operational amplifier provides the output signal. Switches control the routing of the signal flow from the source capacitor, the series capacitor, and the feedback capacitor.

Description:
RELATED APPLICATIONS 
     This is a continuation-in-part of U.S. patent application Ser. No. 08/538,441 filed Oct. 3, 1995, now U.S. Pat. No. 5,724,095. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to metal oxide semiconductor imaging arrays, and more particularly, an improved charge amplifier for use in the array. 
     BACKGROUND OF THE INVENTION 
     Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. In the field of imaging, the charge coupled device (CCD) sensor has made possible the manufacture of relatively low cost and small hand-held video cameras. Nevertheless, the solid-state CCD integrated circuits needed for imaging are relatively difficult to manufacture, and therefore are expensive. In addition, because of the differing processes involved in the manufacture of CCD integrated circuits relative to MOS integrated circuits, the signal processing portion of the imaging sensor has typically been located on a separate integrated chip. Thus, a CCD imaging device includes at least two integrated circuits: one for the CCD sensor and one for the signal processing logic. 
     An alternative low cost technology to CCD integrated circuits is the metal oxide semiconductor (MOS) integrated circuit. Not only are imaging devices using MOS technology less expensive to manufacture relative the CCD imaging devices, for certain applications MOS devices are superior in performance. For example, the pixel elements in a MOS device can be made smaller and therefore provide a higher resolution than CCD image sensors. In addition, the signal processing logic necessary can be integrated alongside the imaging circuitry, thus allowing for a single integrated chip to form a complete stand alone imaging device. 
     Examples of MOS imaging devices are detailed in &#34;A 1/4 Inch Format 250K Pixel Amplified MOS Image Sensor Using CMOS Process&#34; by Kawashima et al., IEDM 93-575 (1993), and &#34;A Low Noise Line-Amplified MOS Imaging Devices&#34; by Ozaki et al., IEEE Transactions on Electron Devices, Vol. 38, No. 5, May 1991. In addition, U.S. Pat. No. 5,345,266 to Denyer titled &#34;Matrix Array Image Sensor Chip&#34; describes a MOS image sensor. The devices disclosed in these publications provide a general design approach to MOS imaging devices. 
     The primary building block of an image formed by an MOS imaging device is a pixel. The number, size and spacing of the pixels determine the resolution of the image generated by the imaging device. The pixels of a MOS imaging device are semiconductor devices that transform incident light photons into current signals. The signal produced by each pixel is generally extremely small, in the nanoampere range. This small signal is unsuitable for further processing. Thus, a critical component of a MOS image sensor is a series of charge amplifiers that amplify the signals generated by the pixel elements. It is the charge amplifier design and the method of making the same that is the subject of the present invention. 
     SUMMARY OF THE INVENTION 
     The present invention is a charge amplifier with DC offset canceling for use in a MOS image sensor. The charge amplifier can be manufactured using a standard CMOS single polycrystalline process, making it much more cost effective than prior art designs. The charge amplifier includes an operational amplifier, a feedback capacitor, a source capacitor, a series capacitor, and several switches (preferably formed from MOS transistors). In addition, a voltage reference is provided to cancel the offset voltage of the operational amplifier. The series capacitor is connected to the negative terminal of the operational amplifier. The positive terminal of the operational amplifier is connected to the voltage reference. The switches operate to alternately route the feedback signal through the series capacitor before being fed to the negative terminal or provide the feedback signal directly to the negative terminal. In the first instance, where the switches operate to route the feedback signal through the series capacitor, the DC offset voltage inherent to the operational amplifier is captured by the series capacitor. In the second instance, where the switches operate to route the feedback signal directly to the negative input, the voltage captured by the series capacitor cancels the DC offset voltage inherent to the operational amplifier. 
     In accordance with other aspects of the present invention, a capacitor for use in the charge amplifier comprises two series MOS transistors and a control MOS transistor. The gates of the two series MOS transistors are connected to the drain of the control MOS transistor. The drain and source of both of the series MOS transistors are tied together to form the two terminals of the capacitor, respectively. A control signal activates the control transistor to activate the capacitor for operation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a schematic diagram of a CMOS imaging sensor; 
     FIG. 1A is a schematic diagram of a prior art CMOS charge amplifier; 
     FIG. 2 is a schematic diagram of a CMOS charge amplifier in accordance with the present invention; 
     FIG. 2A is a timing diagram illustrating the operation of the CMOS charge amplifier of FIG. 2; 
     FIG. 2B is a circuit diagram illustrating the charge amplifier of FIG. 2 during a preparation period; 
     FIG. 2C is a circuit diagram illustrating the charge amplifier of FIG. 2 during a amplification period; 
     FIG. 2D is a schematic diagram of an alternative embodiment of a CMOS charge amplifier in accordance with the present invention; 
     FIG. 2E is a timing diagram illustrating the operation of the CMOS charge amplifier of FIG. 2D; 
     FIG. 2F is a circuit diagram illustrating the charge amplifier of FIG. 2D during a first time period; 
     FIG. 2G is a circuit diagram illustrating the charge amplifier of FIG. 2D during a second time period; 
     FIG. 2H is a circuit diagram illustrating the charge amplifier of FIG. 2D during a third time period; 
     FIG. 2I is a circuit diagram illustrating the charge amplifier of FIG. 2D during a fourth time period; 
     FIG. 3 is a circuit diagram of a capacitor formed using an NMOS process for use in the charge amplifier of FIG. 2; 
     FIG. 3A is a timing diagram illustrating the operation of the capacitor of FIG. 3; 
     FIG. 4 is a schematic diagram of an alternative embodiment of a capacitor using an NMOS process for use in the charge amplifier of FIG. 2; 
     FIG. 4A is a timing diagram illustrating the operation of the capacitor of FIG. 4; 
     FIG. 5 is a schematic diagram of another alternative embodiment of a capacitor using an NMOS process for use in the charge amplifier of FIG. 2; and 
     FIG. 5A is a timing diagram illustrating the operation of the capacitor of FIG. 5. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     With reference to FIG. 1, a CMOS imaging array 101 in accordance with the present invention includes a rectangular matrix of pixels 103. The number of pixels in the horizontal or x-direction, and the number of pixels in the vertical or y-direction, constitutes the resolution of the imaging array 101. Each of the pixels 103 in a vertical column routes its signal to a single charge amplifier 105 (shown in greater detail in FIG. 2). However, at any instant only one of the pixels 105 in a column sends a charge signal to the associated charge amplifier 105. Control circuitry of conventional design is operative to sequentially read the pixels 103 in a scanning manner. 
     As seen in FIG. 2, each charge amplifier 105 (also referred to in the art as a sense amplifier) includes an operational amplifier 107, and a reference voltage source 109 connected between ground and the positive input of the operational amplifier. A source capacitor C C  and a series capacitor C S  are connected in series between ground and the negative input of the operational amplifier. Also represented are two parasitic capacitances C P1  and C P2 . As can be appreciated, the parasitic capacitances are not intentionally formed capacitors, but rather a result of the source capacitor C C  and the series capacitor C S . A feedback capacitor C F  is connected between the negative input and the output of the operational amplifier. In the preferred embodiment and as detailed below, the capacitors are formed by MOS devices. As described below, switches S 0  -S 4  control the routing of the input signal (V IN ), reference voltage signal (V REF ) and feedback signal through the amplifier. 
     In a traditional design for a charge amplifier that includes an operational amplifier, one challenge is to reduce the uncertainty in the DC offset voltage between the negative input (also referred to as the inverting input) and positive input (also referred to as the non-inverting input) of the operational amplifier. As is known in the art, the DC offset voltage between the two inputs of an operational amplifier is an unavoidable but, usually, undesirable artifact of the design and manufacture of an operational amplifier. In some circumstances, the presence of a DC offset voltage in the charge amplifiers 105 would be acceptable i.e., if all of the DC offset voltages in the operational amplifiers were equal in magnitude and polarity. However, because of variations in manufacture of the operational amplifiers, the DC offset voltage will vary from operational amplifier to operational amplifier. The uncertainty of the DC offset voltage between operational amplifiers, and thus the charge amplifiers 105, interferes with the performance and integrity of the image formed by the MOS imaging array. In the case of a charge amplifier used in video applications, variations in the DC offset voltage manifests itself as bright and dark vertical lines in the picture. The present invention provides a charge amplifier 105 that eliminates or greatly lessens the effect of variable DC offset voltages. 
     As seen in FIG. 1A, a prior art design for a charge amplifier that reduces DC offset voltage is shown. The charge amplifier includes a first amplification stage 301, dual storage 303, and a second amplification stage 305. The first amplification stage 301 performs a standard amplification of the input signal. Dual storage 303 stores the output of the first amplification stage 301 and, in conjunction with the second amplification stage 305, serves to cancel the DC offset voltage of the first amplification stage 301. However, as can be seen in FIG. 1A, the number of capacitors necessary is double that of a charge amplifier without DC offset compensation, adding to size and manufacturing complexity of the circuit. In addition, supplementary electronic routing is required. The extra routing tends to introduce noise into the signal. Furthermore, as can be appreciated by those skilled in the art, in the case of color sensors, there are many additional outputs that require an even greater number of capacitors and routing. Thus, this prior art charge amplifier has significant disadvantages. 
     Returning to FIG. 2, the transfer function of the charge amplifier 105 of the present invention can be calculated using known relationships. If the open loop gain (denoted as A V ) of the operational amplifier 107 is sufficiently high such that A V  C F  is much larger than C P1  and if C S  is much larger than C P2 , then the final gain is approximated as: 
     
         V.sub.OUT =V.sub.IN *(C.sub.C /C.sub.F)-V.sub.REF          Eq.(1) 
    
     The inclusion of a reference voltage V REF  shifts the entire input signal V IN  to a higher magnitude for easier processing. Specifically, because the input signal V IN  is typically very small, near a voltage level of ground, it is difficult for the operational amplifier 107 to process the signal. By shifting the input signal V IN  to a higher magnitude (where the input signal piggybacks onto the V REF  signal), the operational amplifier 107 can operate at a more optimum range. In addition, this allows the operational amplifier used in the imaging array 101 to operate on a single power supply. Thus, although a reference voltage V REF  is included in the preferred embodiment, it can be appreciated by those skilled in the art that V REF  may be a ground signal (i.e. grounded). 
     The inclusion of series capacitor C S  in conjunction with controlled operation of the switches is operative to cancel any DC offset voltage in the operational amplifier. Switch S 1  is in parallel with feedback capacitor C F  ; switch S 2  is between the negative input of the operational amplifier and the input side of feedback capacitor C F  ; switch S 3  is between the input side of C F  and a node between C S  and C P1  ; switch S 4  is between the reference voltage source and the node between C S  and C P1  ; and switch S 0  is between the source capacitor C C  and the node between C S  and C P1  (i.e., in the path between the source capacitor C C  and the series capacitor C S ). FIG. 2A is a timing diagram of the charge amplifier 105 when in operation. In particular, during time T 1 , switches S 1 , S 2 , and S 4  are closed and switches S 0  and S 3  are open. The closing of switches S 1  and S 2  bypasses the feedback capacitor and connects the output of operational amplifier 107 directly to the negative input of operational amplifier 107. Closing of switch S 4  holds the input side of series capacitor at V REF . 
     Because the positive input of operational amplifier 107 is held to voltage V REF  and the input side of series capacitor C S  is also held to voltage V REF , the circuit performs as shown in FIG. 2B (ignoring the inconsequential effects of C P1  and CP 2 ). The voltage across series capacitor C S  is equal in magnitude to the DC offset voltage between the inputs of the operational amplifier 107. It should be noted that the input side of C S  is held at V REF  while the output side of C S  is connected to the negative input of the operational amplifier. Thus, it can be said that the series capacitor C S  stores a voltage that is equal to the DC offset voltage, and of opposite polarity. The time period T 1  during which switches S 1 , and S 2  and S 4  are closed is referred to as the preparation period, because during time period T 1 , the charge amplifier 105 is preparing to acquire and amplify the input signal V IN . 
     Next, at time T 2 , switches S 1 , S 2 , and S 4  are opened and switches S 0  and S 3  are closed. The circuit performs as shown in FIG. 2C (again ignoring the inconsequential effects of C P1  and C P2 ). The input signal V IN  is fed through the series capacitor C S  to the operational amplifier 107. The feedback signal flows through the feedback capacitor C F . As can be appreciated, this configuration is a normal amplification arrangement for the input signal V IN . Any DC offset voltage in operational amplifier 107 is momentarily cancelled by the equal and opposite voltage stored across series capacitor C S , obtained during the preparation period. The time period T 2  when switches S 1  and S 3  are closed is referred to as the amplification period because during time period T 2 , the charge amplifier 105 is amplifying the input signal V IN . Thus, as can be seen, the charge amplifier 105, by inclusion of series capacitor C S  and the switching mechanisms, is operative to cancel any DC offset voltage inherent in the operational amplifier 107 for the very brief period of actuation of a pixel. 
     An alternative preferred embodiment of the charge amplifier 105 is shown in FIG. 2D. The charge amplifier 105 includes an operational amplifier 107, a feedback capacitor C F , a reference capacitor C REF , a source capacitor C C , a parasitic capacitor C P , a calibration capacitor C CAL , and a calibration voltage source V CAL . The feedback capacitor C F  is connected between the inverting input and the output of the operational amplifier 107. Switch S 1  is also between the inverting input and the output of the operational amplifier 107. Thus, switch S 1  allows C F  to be bypassed. The reference capacitor C REF  is between ground and switch S 2 . The parasitic capacitor C P , between the inverting input of operational amplifier 107 and ground, is not an intentionally formed capacitor, but rather a result of the formation of the other circuit structures. 
     Switch S 2  is between C REF  and the inverting input of the operational amplifier 107. The source capacitor C C  is between ground and switch S 3 . Switch S 3  is between C C  and the inverting input of the operational amplifier 107. The calibration capacitor C CAL  is between the output of the operational amplifier 107 and the output node V OUT . Finally, switch S 4  and voltage source V CAL  are in series between the output node V OUT  and ground. In addition, noted on FIG. 2D are various voltage nodes V a , V b , and V c , which will be used to identify the voltage at the respective nodes. 
     In the preferred embodiment and as detailed below, the capacitors are formed by MOS devices. As described below, switches S 1  -S 4  control the routing of the input signal (V IN ), reference voltage signal (V REF ) and feedback signal through the operational amplifier 107. The voltage stored across C REF  is referred to as reference voltage V REF . The voltage stored across C C  is referred to as input voltage V IN . 
     The operation of the charge amplifier 105 is next described in connection with FIGS. 2E-2I. First, at time period T 1 , the charge amplifier 105 appears as in FIG. 2F. Switches S 1  is closed to allow the voltage at nodes V a  and V c  to equalize. In addition, closing of switch S 4  allows the voltage at node V b  to be clamped at V CAL . It should be noted that V CAL  is relatively arbitrary and may be set at a level that facilitates further processing. Indeed, V CAL  may be ground. The time period T 1  is referred to as the equalizing period. 
     Next, at time period T 2 , the charge amplifier 105 appears as in FIG. 2G. Note, however, that at the very beginning of time period T 2 , switch S 1  is opened and switch S 4  is still closed and switch S 2  is still open. The closing of switch S 2  is delayed briefly (on the order of 25 nanoseconds) to prevent signal equalization between V a  and V REF . 
     After the brief delay to prevent equalization of V a  and V REF , the signal V REF  signal is amplified by operational amplifier 107. The transfer function of the circuit during the middle of time period T 2  is given by: ##EQU1## Eq. (1) gives the charge across the calibration capacitor C CAL , where A V  is the open loop gain of the operational amplifier 107 and -V is the DC offset voltage. Note that Eq. (1) depends upon -V, the DC offset voltage. During the bulk of period T 2 , the output of the operational amplifier 107 is allowed to settle to its final value. It can be appreciated by those skilled in the art that the longer the time period T 2  is, the closer the output of the operational amplifier 107 approaches the nominal final value. 
     Near the completion of time period T 2 , switch S 4  opens and the voltage at V b  is allowed to float. This allows the voltage at V b  to float with any noise transients caused by the later opening of switch S 2 . Next, switch S 2  is opened, and briefly thereafter, switch S 1 , is closed. Again, switch S 2  is opened before the closing of switch S 1  to prevent equalization between V REF  and V a . 
     At time period T 3 , switch S 1  is closed and all other switches are open, resulting in the circuit shown in FIG. 2H. This results in an equalization between the voltages at V a  and V c . In addition, switch S 4  remains open to avoid clamping of V b  to V CAL  which would cause a loss in the amplified reference signal. 
     Next, at time period T 4 , switch S 1  is opened so that the input signal V IN  can be amplified by the operational amplifier 107. In addition, switch S 3  is closed. In the preferred embodiment, time periods T 1  and T 3  are 175 nanoseconds and time periods T 2  and T 4  are 700 nanoseconds. Further, it can be appreciated that the activation of the switches is accomplished with timing circuitry of conventional design. 
     The circuit during time period T 4  appears as in FIG. 2I. Note again that the closing of switch S 3  is delayed briefly (on the order of 25 nanoseconds) to prevent signal equalization between V a  and V IN . The resulting transfer function is given by: ##EQU2## With Eq. (1) and Eq. (2), V OUT  can be solved to give (assuming that A V  is large): ##EQU3## Note that Eq. (3) assumes that C C  and C REF  are approximately equal. However, C REF  may be different from C C  ; Eq. (3) would simply be a bit more complicated. More importantly, Eq. (3) does not depend upon the DC offset voltage ΔV. Thus, the circuit eliminates the DC offset voltage in the charge amplifier. 
     One advantage of this embodiment is that the DC offset compensation is done at the output side of the operational amplifier. This prevents noise from entering into the charge amplifier system from the switching of the storage capacitor C S  in the embodiment of FIG. 2. However, a more difficult timing cycle is necessary in order to implement this embodiment. 
     Another issue that arises is the manufacture in MOS processes the capacitors C S  and C F . In particular, in order to manufacture the charge amplifier 105 that behaves in accordance with Eq. (1), large and stable capacitors C S  and C F  must be available. In the prior art, there are three methods of manufacturing capacitors using VLSI process. First, a capacitor (known as a junction capacitor) could be formed by the junction of a pn diode. However, as can be appreciated by those skilled in the art, this capacitor is difficult to use and its capacitance value varies as the voltage across the junction capacitor changes. 
     The second type of capacitor is referred to as the MOS channel capacitor. The source and drain of a MOS transistor are tied together. The gate serves as one &#34;plate&#34; of the capacitor and the source/drain-combination as the other &#34;plate&#34; of the capacitor. The oxide material serves as the dielectric. This MOS channel capacitor suffers from the same disadvantages as the junction capacitor, namely, the capacitance of the MOS channel capacitor varies as a function of the voltage across the capacitor. 
     Finally, the third type of capacitor is referred to as the poly2 to poly1 capacitor. This capacitor involves the inclusion of two polycrystalline materials in proximity to each other. This type of capacitor requires extra manufacturing steps due to the requirement of a second polycrystalline material. In addition, the capacitance is relatively low compared to the amount of integrated circuit space necessary to fabricate such a capacitor. Moreover, the capacitance does not relate to any other MOS parameters. 
     FIG. 3 illustrates a new design for a large stable capacitor that does not suffer from any of the disadvantages of the other prior art MOS capacitors. The capacitor is formed from three MOS transistors M 1 , M 2 , and M 3 . The gates of transistors M 2  and M 3  are tied together, along with the drain of transistor M 1 . The source of transistor M 1  is connected to a voltage source V dd . In the preferred embodiment, V dd  is set to 5.0 volts. 
     The operation of the capacitor can be explained in connection with the timing diagram of FIG. 3A. At time T 1 , transistor M 1  is turned on by a signal φ. This causes node N f  to reach a voltage equal to V dd  -V t , where V t  is the threshold voltage of transistor M 1 . At time T 2 , transistor M 1  is turned off. This causes the voltage at node N f  to float at V dd  -V t . A capacitor is then formed by the transistors M 2  and M 3  in series. In such a manner, an easy to fabricate capacitor is provided. However, this design has the disadvantage of a limited operating range. For example, the voltages at nodes N a  and N b  must be lower than V dd  -2*V t . If the voltages at these nodes rise above this level, the capacitance of the MOS channel capacitor depletes. 
     To remedy the limited operating range of the embodiment of FIG. 3, the design of FIG. 4 is provided. FIG. 4 provides a similar arrangement to the capacitor of FIG. 3 with the addition of transistors M 4 , M 5 , and M 6 . As seen, the drains of transistors M 5  and M 6  are tied to the gate of transistor M 1 . Further, the gates of transistors M 4  and M 6  are tied to the gate of transistor M 1 . The gate of transistor M 5  is tied to V dd . Finally, transistor M 4  is configured into a MOS channel capacitor configuration, i.e., the source and drain of transistor M 4  are tied together. In the preferred embodiment, transistors M 4  -M 6  are sharable amongst a plurality of capacitors. Thus, a plurality of combinations of transistors M 1  -M 3  can share the transistors M 4  -M 6 . To put it another way, the combination of M 4  -M 6  provide an output that can be routed to several of the combinations of M 1  -M 3 , thus forming several capacitors. 
     The operation of the capacitor can be understood with further reference to FIG. 4A. During time T 0 , the signal φ is high which causes the voltage at node N c  to become V dd  -V t . As a consequence, the voltage at node N f  is charged to V dd . During time T 1 , signal φ returns to low resulting in the voltage at node N c  to be clamped at V dd  -V t . The voltage at node N f  is floating at V dd  and the capacitor is ready for use. The operating range of this capacitor becomes V dd  -V t  for the upper limit and V dd  -3*V t  for the lower limit, which is sufficient in many applications. 
     A further improved capacitor is seen in FIG. 5 which further includes a transistor M 7 , a delay element 113 and an inverter 115. These additional elements are also shareable amongst a plurality of basic capacitors formed from transistors M 1  -M 3 . In operation, referring to FIG. 5A, during time T 0 , signal φ goes high and the voltage at node N c  is charged to V dd  -V t . After a delay caused by delay 113, during time T 1 , the voltage at node N c  is boosted to V dd  +V t . This charges the voltage at node N f  to V dd . During time T 2 , signal phi returns to low and transistor M 7  is turned on. This in turn causes the voltage at node N c  to discharge to ground, which completely shuts off transistor M 1 . Further, the voltage at node N f  is floating at V dd . This capacitor can operate throughout the entire supply range from zero to V dd . 
     While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.