Abstract:
A time measuring device uses a clock pulse signal whose period is successively increased after a predetermined number of pulses is produced. The clock pulse signal is counted from the time when the earliest of a number of phenomena occurs.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to time measurement devices and particularly to devices for making parallel measurements of the times when different phenomena occur. 
     In an automatic focus camera (AFIC), the image of an object is formed on two light receiving element or photosensor arrays and the distance between the camera and the object is determined from the difference between the positions of the images on those arrays. To make that determination, some photosensor arrays use a system to measure photosensor response times and generate electrical signals representing the images. Many systems of this type are well known in the art. 
     FIG. 1 is a block diagram of a conventional time measuring system 10 which includes AND gates 12 (12a through 12n) and counters 13 (13a through 13n) to measure the times required for the outputs of photosensors 11 (11a through 11n) to reach a predetermined level. For example, if the outputs of photosensors 11 change from a high (H) level to a low (L) level when a desired response is sensed, counters 13 count the number of clock signals φ 0  generated while the outputs of photosensor 11 remain at a high level. The response times of photosensors 11 thus correspond to the count values of counters 13. 
     With some modifications, system 10 can also be adapted to measure the time elapsed between the onsets of selected phenomena. Conventional time measurement systems, however, have inherent limitations. 
     In conventional systems for measuring the onset times of different phenomena, the amount of hardware increases not only with the number of phenomena to be measured but also with the length of the time durations to be measured. For instance, the measurement of a one second time duration with a 1 MHz clock signal requires a twenty stage binary counter (10 6  is approximately equal to 2 20 ). In addition to the complexity of such systems, time measurement which involves an excessively large number of digits delays succeeding data processing operations and hinders the production of sufficiently effective results. This is even more of a disadvantage when the precision afforded by all the digits is not needed. 
     A solution to these problems of complexity and loss of effectiveness of conventional time measurement systems is premised on the realization that photosensor response times do not always need to be measured very precisely. Especially when the outputs of the sensors are quantized, often only the most significant data from the sensor arrays are needed for the the time measurement system to operate effectively. 
     Accordingly, an object of the invention is to provide a time measuring device which can perform effective time measurement with a relatively small amount of hardware. 
     SUMMARY OF THE INVENTION 
     To obtain the objects and provide the advantages of this invention, a device for measuring the time period between the onset of two phenomena comprises: input means for receiving occurrence signals indicating the onset of the phenomena; clock means, coupled to the input means, for generating a timing signal composed of repeating pulses with non-decreasing periods; and count means, coupled to the clock means and responsive to the occurrence signals, for counting the number of pulses of the timing signal generated by the clock means between the occurrence signals thereby to measure the time period between the onset of the phenomena. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a conventional time measuring system; 
     FIG. 2 is a diagram of one embodiment of the time measuring device of this invention; 
     FIG. 3 is a circuit diagram embodiment of the select circuits shown in the device in FIG. 2; and 
     FIG. 4 is a time chart of signals generated during the operation of the device in FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2 is a diagram of one embodiment of this invention. In FIG. 2, signals E 1  through E m  each represent a different one of m phenomena to be time-measured. When a phenomenon occurs, the level of the corresponding signal E changes from &#34;0&#34; to &#34;1.&#34; 
     In system 10, reference numeral 21 designates an OR gate and reference signals 22 (22a through 22m) designate latch circuits which latch the output of a counter 23 when the signals at their strobe input terminals ST are raised to &#34;1&#34; from &#34;0.&#34; Reference characters 24a, 24b, 25, and 26 designate two AND gates, an inverter, and a shift register, respectively. In shift register 26, the parallel outputs Q 1  through Q n  are all set to &#34;0&#34; when a reset signal RESET is applied to reset terminal R. Thereafter, whenever a clock signal is applied to the clock terminal of shift register 26, a &#34;1&#34; signal at an input terminal D is shifted from right to left until the outputs Q 1  through Q n  are all equal to &#34;1.&#34; 
     As FIG. 2 shows, system 10 also includes a 1/K frequency divider 27 (K being a positive integer) and select circuits 81, 82, . . . , 8N. In each of those select circuits, the signal at output O becomes the signal at input I 2  when the signal at input terminal S is at a &#34;1&#34; level, and the signal at output O becomes the signal at input I 1  when the signal at input terminal S is at a &#34;0&#34; level. Elements 91, 92, 93 . . . and 9N are each 1/2 frequency dividers. 
     A preferred embodiment of the select circuits 81 through 81N is shown in FIG. 3. In that preferred embodiment, the select circuit includes AND gates 38a and 38b, OR gate 38c, and inverter 38b. When the input signal S is at a &#34;1&#34; level, the output of the AND gate 38a is held at a &#34;0&#34; level and the signal at input I 2  is provided to output terminal O. When the input signal S is at a &#34;0&#34; level, the output of AND gate 38b is held at a &#34;0&#34; level and the signal at input I 1  is provided at the output terminal O. The operation of the time measuring device in FIG. 2 can best be described with reference to the timing charts of FIG. 4. The operation of the circuit in FIG. 2 begins when a reset signal (FIG. 4(a)) resets the contents of counter 23 and shift register 26. At this time instant, output signal Q 1  of shift register 26 is equal to &#34;0&#34; so select circuit 81 outputs clock signal φ 0  as shown in FIG. 4(b). When none of the phenomena has occurred, all the signals E are at a &#34;0&#34; level. This condition sets the output of OR gate 21 to a &#34;0&#34; level and the output of inverter 25 to a &#34;1&#34; level. When the output of inverter 25 is at a &#34;1&#34; level, the output of the 1/K frequency divider 27, φ T , passes through AND gate 24b into the clock input of shift register 26. 
     As the circuit continues to operate prior to the occurrence of a phenomenon, clock signals φ T  continue to be sent to the clock signal input of shift register 26 and eventually the following condition is established: 
     
         Q.sub.1 = . . . =Q.sub.j =&#34;1&#34; and 
    
     
         Q.sub.j+1 = . . . =Q.sub.n =&#34;0&#34; 
    
     In this condition, j (1/2) frequency dividers (91 through 9J) are used by selectors 81-8J and a clock signal φ S  (FIG. 4(c)) is obtained by subjecting the clock signal φ 0  to j (1/2) frequency divisions. In the embodiment of the invention shown in FIG. 2, a shift clock pulse φ T  from 1/K frequency divider 27 is applied to shift register 26 through AND gate 24b every K periods of clock signal φ S . 
     As long as the output of inverter 25 is at a &#34;1&#34; level, another 1/2 frequency divider is added every K periods of the clock signal φ S . This operation causes the period of φ s  first to double, then quadruple, etc. In other words, the frequency of clock signal φ S  equals the frequency of the original clock signal φ for the first K clock pulses, then decreases to 1/2 of that frequency for the next K clock pulses, and then decreases by 1/2 again during the succeeding K clock pulses, and so on until Q n  =1 or until a reset occurs. Thus, as long as the system is not interrupted, the period of clock signal φ S  is substantially proportional to the time elapsed from the start of the measurement, so the relative accuracy of the measurement corresponds substantially to the elapsed time. 
     The earliest of the phenomena associated with signals E 1  through E m  which occurs will be phenomenon i corresponding to signal E i  (FIG. 4(d)). When that earliest phenomenon occurs, the output of OR gate 21 is raised to &#34;1&#34; as shown in FIG. 4(e) and the clock signal φ S  /s passed through AND gate 24a and counted by the counter 23. When another phenomenon later occurs, e.g. one associated of with signal E j  (FIG. 4(f)), signal E j  acts as a strobe signal for the respective latch circuit 22j causing it to latch the output of the counter 23. In the example shown by FIG. 4, a &#34;3&#34; is recorded. When the earliest occurring phenomenon occurs, the content of the counter 23 is &#34;0&#34; and &#34;0&#34; is recorded in the respective latch circuit 22i. 
     When the earliest phenomenon occurs and generates signal E i , the output of OR gate 21 is the raised to &#34;1.&#34; In that case, the output of the inverter 25 drops to &#34;0&#34; and closes AND gate 24b which prevents shift clock pulses from changing shift register 26. Consequently, the period of the clock signal φ S  remains unchanged. 
     Later, when the phenomena corresponding to the other circuits E 1  through E m  occurs, data representing the time of their occurrence are recorded in the appropriate latch circuits 22 1  through 22 m , with the time that the earliest phenomenon occurred being the reference point (t=0). In this recording operation, the frequencies of the clock pulses used correspond to the elapsed times from the start of the measurement. Therefore, the data thus obtained are effective and significant. 
     The circuit of FIG. 2 may be modified to eliminate AND gate 24b and inverter 25, and to apply the output of 1/K frequency divider 27 directly to the clock terminal of shift register 26. In this case, the time measurement is carried out in such a manner that the period of the clock signal φ S  is increased even after the output of the OR gate 21 is raised to &#34;1.&#34; 
     It will be apparent to persons or ordinary skill that various modifications and variations can be made in the time measurement device of this invention without departing from the spirit and scope of the inventive concept. The present invention is intended to cover all such variations and modifications which come within the scope and spirit of the appended claims and their equivalents.