Abstract:
A data signal peak error detector for monitoring and detecting undesired shifts in the peak levels of a multilevel data signal, such as an MLT 3  Ethernet signal. A signal slicing circuit generates two signals: a data peak detection signal identifies occurrences of data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding intermediate and peak (e.g., positive or negative) signal levels; and a data peak error signal identifies occurrences of data signal peak errors and is asserted when the input data signal level has transitioned beyond a value which corresponds to a preceding peak signal level. Assertion of the data peak detection signal initiates a count sequence by a counter. The count sequence is decoded to produce one or more signal pulses, each of which is provided at a respective time after assertion of the first data peak signal and identifies a valid state of the data peak error signal.

Description:
RELATED APPLICATIONS 
     This application claims the benefit of and incorporates herein by reference the following U.S. provisional patent applications: 
     60/069,027, filed Dec. 10, 1997, entitled “Peak Error Detector” 
     60/069,044, filed Dec. 10, 1997, entitled “Signal Gating Controller For Enhancing Convergency of MLT 3  Data Receivers” 
     60/069,031, filed Dec. 10, 1997, entitled “Digital Interface Circuit” 
     60/069,091, filed Dec. 10, 1997, entitled “Digital Signal Processing Control Circuit For Controlling Corrections of Input Data Signal Errors” 
     60/069,030, filed Dec. 10, 1997, entitled “Control Loop For Data Signal Baseline Correction” 
     60/069,028, filed Dec. 10, 1997, entitled “Control Loop For Adaptive Equalization of a Data Signal” 
     60/069,029, filed Dec. 10, 1997, entitled “Control Loop For Multilevel Sampling of a Data Signal” 
     60/067,764, filed Dec. 10, 1997, entitled “Data Signal Baseline Error Detector” 
    
    
     A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office, patent file or records, but otherwise reserves all copyright rights whatsoever. 
     This application is submitted with a microfiche appendix containing copyrighted material, copyright 1996, National Semiconductor Corporation. Such appendix consists of 3 microfiche transparencies with a total of 293 frames. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to circuits for detecting errors in peak signal amplitudes of digital data signals, and in particular, to peak error detection circuits for detecting and identifying valid detected peak signal errors during selected time windows within digital data signals. 
     2. Description of the Related Art 
     Recovering data from data signals which have been transmitted over long lengths of cable at high data rates requires that such data signals be equalized in order to compensate for the signal loss and phase dispersion characteristics of the cable. Further, in those applications where the cable length may vary, such equalization must be capable of adapting according to the length of the cable. Conventional adaptive equalization is typically accomplished through the use of a feedback control signal having an amplitude which is proportional to the pulse height of the equalized data signal. However, such a technique for controlling the adaptive equalization process is very sensitive to amplitude errors in the incoming data signal. Accordingly, it would be desirable to have a peak error detector which, by detecting and identifying valid detected errors in the signal peaks of the incoming data signal, can be used to help generate more consistent and more accurate control over the adaptive equalization process. 
     SUMMARY OF THE INVENTION 
     A peak error detector in accordance with the present invention provides for the generation of multiple peak error signals indicating the occurrence of errors in the signal peaks within selected frequency bands of the incoming data signal. Such peak error signals identify errors between the peak of the present incoming data signal and estimated peak values of prior data signals within different time windows. Such a peak error detector can be used advantageously in a signal peak tracker or a baseline wander compensation circuit, as well as a control circuit for an adaptive equalizer (e.g., for use in a fast Ethernet transceiver). 
     A data signal peak error detector in accordance with one embodiment of the present invention includes first and second data signal detection circuits. The first data signal detection circuit is configured to receive and detect an input data signal which includes a plurality of signal levels representing an N-level data signal and in accordance therewith provide a data level signal which is asserted when the input data signal level extends beyond a predetermined value. The input data signal includes, associated therewith, a plurality of sequential intermediate signal values and a plurality of sequential extended signal values each of which extends beyond a preceding one of the plurality of sequential intermediate signal values. The predetermined value corresponds to a value which is between a preceding one of the plurality of sequential intermediate signal values and a preceding one of the plurality of sequential extended signal values. The second data signal detection circuit is configured to receive the first data level signal and in accordance therewith provide one or more signal pulses during the assertion of the first data level signal. Each one of the one or more signal pulses is provided at a respective time after the assertion of the first data level signal. 
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of a high speed data receiver in which a peak error detector in accordance with the present invention can be advantageously used. 
     FIG. 2 is a schematic diagram of a peak error detector in accordance with one embodiment of the present invention. 
     FIGS. 3A,  3 B and  3 C are signal timing diagrams illustrating the operation of the peak error detector of FIG. 2 for input data signal pulses of varying durations. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, a circuit in accordance with the present invention is advantageous for use in a high speed data receiver  100  which receives binary or MLT 3  encoded data which has been transmitted via a cable (e.g., fast Ethernet). As discussed in more detail below, such a data receiver  100  provides adaptive equalization and dynamic slicing and baseline restoration of the data signal. (Each of the circuit functions or stages as represented in FIG.  1  and discussed below are described in detail in the code listings provided in the microfiche appendix hereto, the contents of which are incorporated herein by reference. A description of a similar data receiver can be found in co-pending, commonly assigned U.S. patent application Ser. No. 08/791,381, filed Jan. 30, 1997, and entitled “High Speed Data Receiver,” the disclosure of which is incorporated herein by reference.) 
     This data receiver  100  includes a correction stage  102 , a slicer stage  104 , a digital control stage  106  and a digita-to-analog (D/A) interface  108 . As discussed in more detail below, the correction stage  102  provides for equalization and baseline wander correction of the input data signal  101 . The slicer stage  104  slices the resulting equalized, corrected data signal  117 . The digital control stage  106  processes some of the sliced data signals to produce an output digital data signal  147 , as well as generate a number of digital control signals  155   a,    157   a,    157   b,    159  for controlling the equalization, baseline wander correction and slicing of the input data signal  101 . The D/A interface  108  converts such digital control signals  155   a,    157   a,    157   b,    159  into corresponding analog signals  163 ,  167 ,  169 ,  165  for actually providing such control of the equalization, baseline wander correction and slicing of the input data signal  101 . 
     The incoming data signal  101 , which has been received via a long cable of variable length (not shown), is selectively combined with a baseline correction signal  163  (discussed further below) in a signal summer  110 . The corrected signal  111  is selectively amplified by a series of adaptive equalizers,  112 ,  114 , which each have a signal gain which increases with frequency in accordance with their respective equalizer control signals  167 ,  169 . The resulting equalized signal  115  is selectively combined with an alternative baseline correction signal  163  in another signal summer  116 . (For testing purposes, the final equalized, corrected data signal  117  is buffered by an analog buffer amplifier  118  to be provided as an analog, equalized, corrected output data signal  119 , and is also provided to the signal slicer  104 .) 
     A description of a signal equalization technique using a series of signal equalizers in this manner can be found in co-pending, commonly assigned U.S. patent application Ser. No. 08/791,382, filed Jan. 30, 1997, and entitled “Multiple Stage Adaptive Equalizer,” the disclosure of which is incorporated herein by reference. 
     The slicer  104  receives and slices the equalized, corrected data signal  117  in accordance with positive  131  and negative  133  data peak reference signals using a set of voltage comparators  120 ,  122 ,  124 ,  126 ,  128 . The positive  131  and the negative  133  data peak reference signals are the buffered, non-inverted and inverted versions of a data peak signal  165  (discussed further below) as generated by non-inverting  130  and inverting  132  buffer amplifiers, respectively. These data peak reference signals  131 ,  133  are applied differentially across a resistive voltage divider with four resisters  134 , thereby generating five respective reference signals  131 ,  135   a,    135   b,    135   c,    133 , each of which is filtered by a capacitor  136  for use as a reference signal for its respective voltage comparator  120 ,  122 ,  124 ,  126 ,  128 . Based upon these reference signals,  131 ,  135   a,    135   b,    135   c,    133 , each comparator  120 ,  122 ,  124 ,  126 ,  128  produces a respective binary output signal  121 ,  123 ,  125 ,  127 ,  129 , each of which is asserted at a logic one level when the data signal  117  transcends the value of the corresponding reference input signal  131 ,  135   a,    135   b,    135   c,    133 . 
     For example, for the positive  120  and negative  128  peak voltage comparators, the positive  131  and negative  133  data peak reference signals serve as their reference signals, respectively. The middle reference signal  135   b  represents the mean (e.g., zero or baseline) and serves as the reference signal for the middle comparator  124 . The remaining positive reference signal  135   a  represents a voltage between the mean voltage  135   b  and the positive peak voltage  131  and serves as the reference for the positive level comparator  122 . Similarly, the remaining negative reference  135   c  represents a voltage between the mean voltage  135   b  and the negative peak voltage  133  and serves as the reference for the negative level comparator  126 . 
     The binary data signals  121 ,  123 ,  125 ,  127 ,  129  are received and processed by the digital control stage  106  as follows. The mean  125 , positive  123  and negative  127  data signals are processed by a decoder  140  to produce a data signal  145  which is buffered by a buffer amplifier  146  to produce the output digital data signal  147 . The positive  123  and negative  127  data signals are logically summed in an OR Gate  142 . Then, either the resulting logical sum signal  143  or mean data signal  125  is selected with a multiplexor  144  in accordance with a control signal  141 , depending upon whether the original input data signal  101  is an MLT 3  or binary signal. This data signal  145  and the binary data signals  121 ,  123 ,  125 ,  127 ,  129  are received and processed by a high frequency logic stage  150  in accordance with a high frequency clock signal  149   a.    
     The high frequency logic stage  150  processes its input signals  145 ,  121 ,  123 ,  125 ,  127 ,  129  in a number of ways to produce a set  151  of digital signals which are then converted to a corresponding set  153  of digital signals at a lower frequency by the high-to-low frequency stage  152  in accordance with the high frequency clock signal  149   a  and a low frequency clock signal  149   b.  (By way of example, for fast Ethernet, the high frequency clock signal  149   a  has a frequency in the hundreds of megahertz and the low frequency clock signal  149   b  has a frequency in the tens of megahertz.) As discussed in more detail below, one operation performed by the high frequency logic stage  150  is that of peak error detection, whereby multiple peak error signals representing variations in the signal peaks within selected frequency bands of the incoming data signal are generated and validated so as to identify the occurrence of errors between the peak of the present incoming data signal and estimated peak values of prior incoming data signals within different time windows. 
     Another operation performed is that of baseline error detection, whereby a baseline error signal which is generated during an intermediate level state of the multiple level data signal  117  (such as the zero-state of an MLT 3  signal) is validated, thereby identifying the occurrence of an error between the baseline of the incoming data signal and an estimated baseline level. A description of this baseline error detection circuit can be found in co-pending, commonly assigned U.S. patent application Ser. No. 09/076,261, filed May 12, 1998, and entitled “Data Signal Baseline Error Detector” (attorney docket no. NSC1-C1010), the disclosure of which is incorporated herein by reference. Yet another operation performed is that of generating gating control signals for gating out false signal pulses caused by improper equalization of the original incoming data signal  101 . A description of this gating control circuit can be found in co-pending, commonly assigned U.S. patent application Ser. No. 09/076,425, filed May 12, 1998, and entitled “Signal Gating Controller for Enhancing Convergency of MLT 3  Data Receivers” (attorney docket no. NSC1-C0310), the disclosure of which is incorporated herein by reference. 
     The low frequency logic stage  154 , in accordance with the low frequency clock signal  149   b,  processes these lower frequency signals  153  to produce a number of digital control signals  155   a,    155   b,    155   c.  More specifically, the low frequency logic stage  154  processes the lower frequency error signals  153  to produce control signals for compensating for variations in peak signal values and correcting errors in the baseline of the incoming data signal  101 / 115 , as well as controlling the equalization of the incoming data signal  101 . A more detailed description of the low frequency logic stage  154  can be found in co-pending, commonly assigned U.S. patent application Ser. No. 09/076,187, filed May 12, 1998, and entitled “Distributive Encoder For Encoding Error Signals Which Represent Signal Peak Errors In Data Signals For Identifying Erroneous Signal Baseline, Peak And Equalization Conditions” (attorney docket no. NSC1-C0610), the disclosure of which is incorporated herein by reference. 
     The high-to-low frequency interface  152 , in accordance with the high  149   a  and low  149   b  frequency clock signals, converts the incoming error signals  151  to a corresponding set  153  of lower frequency error signals. A more detailed description of this interface  152  can be found in co-pending, commonly assigned U.S. patent application Ser. No. 09/076,263, filed May 12, 1998, and entitled “Digital Interface Circuit” (attorney docket no. NSCI-C0510), the disclosure of which is incorporated herein by reference. 
     One set  155   a  of control signals produced by the low frequency logic stage  154  is used for correcting baseline wander of the original input data signal  101 . This set  155   a  of digital signals is converted to an analog baseline wander control signal  163  by way of a digital-to-analog converter  162 . This analog control signal  163  is then summed with either the original input data signal  101  or the equalized input data signal  115 , as discussed above. 
     Another set  155   b  of control signals is used to generate the equalization control signals  167 ,  169  for the adaptive equalizers  112 ,  114  (discussed above). This set  155   b  of signals is processed using a circuit  156  which includes a pulse density modulator and some associated logic circuitry to produce, in turn, two pulse density modulated control signals  157   a,    157   b  for controlling the two adaptive input signal equalizers  112 ,  114 . Each of these signals  157   a,    157   b  is converted to its respective analog control signal  167 ,  169  with a resistive-capacitive digital-to-analog conversion circuit  166 ,  168 . A more detailed description of this signal converter can be found in co-pending, commonly assigned U.S. patent application Ser. No. 08/791,367 filed Jan. 30, 1997, and entitled “Distributive Digital-to-Analog Converter,” the disclosure of which is incorporated herein by reference. 
     Yet another set of control signals  155   c  is used to generate an analog peak signal  165  which is used to generate the differential peak reference signals  131 ,  133  for the slicer  104 , as discussed above. These digital signals  155   c  are converted with a pulse density modulator  158  to produce a set  159  of pulse density modulated signals which, in turn, are then converted to the analog peak signal  165  by a digital-to-analog converter  164 . 
     Referring to FIG. 2, a peak error detector  308 / 316  in accordance with one embodiment of the present invention includes digital logic which forms the following functional logic blocks: an RS (reset/set) flip-flop  402 , two D-type flip-flops  404 ,  406 , a NAND gate  408 , a counter  410  and a decoder  412 , all interconnected substantially as shown. (Throughout this discussion, for those signals which are identified by two numeric designators the first numeric designator corresponds to the signal for a positive (“P”) peak error detector  308 , while the second numeric designator corresponds to the signal for a negative (“N”) peak error detector  316 .) 
     The RS flip-flop  402  is set and reset in accordance with the P/N peak signal  121 / 129  and a feedback reset control signal  413  from the decoder  412 , respectively. Its output signal  403  is latched in a flip-flop  404  in accordance with a clock signal  149   a.  Accordingly, this output signal  151 p 1 ud/ 151 p 2 ud/ 151 n 1 ud/ 151 n 2 ud is asserted at a logic 1 when the P/N peak signal  121 / 129  indicates that the amplitude of the input data signal  117  exceeds the P/N data peak reference signal  131 / 133  (FIG.  1 ). 
     The P/N data signal  123 / 127  is latched by a flip-flop  406 , the output  407  of which is gated in a NAND gate  408  by the gating control signal  303   a / 303   b.  This gated signal  409 , when asserted, resets the counter  410  to zero. Accordingly, when the P/N data signal  123 / 127  becomes a logic 1, i.e., at the beginning of a pulse within the input data signal  117 , the reset control signal  409  is de-asserted and the counter begins counting from zero in a counting sequence of 01376453764537645 . . . The count sequence signal  411  is decoded by the decoder  412  to generate two peak error validation signals  151 p 1 v/ 151 n 1 v,  151 p 2 v/ 151 n 2 v and the reset signal  413  for the RS flip-flop  402 . Based upon these signals  151 p 1 v/ 151 n 1 v,  151 p 2 v/ 151 n 2 v,  413 , the decoder  412  defines multiple time windows DT 1 , DT 2 (1), DT 2 (2), . . . , DT 2 (N) within the pulse width of the input data signal  117 . The pulse width of this data signal  117  affects the number of time windows which are created. At the end of each time window, a one clock cycle reset pulse  413  is generated for resetting the RS flip-flop  402 . 
     Referring to FIGS. 3A,  3 B and  3 C, the generation of the peak error validation signals  151 p 1 v/ 151 n 1 v,  151 p 2 v/ 151 n 2 v and peak error signal  151 p 1 ud/ 151 p 2 ud/ 151 n 1 ud/ 151 n 2 ud can be better understood. For example, within the first time window DT 1 , if the input data signal  117  is greater than the P/N data peak reference signal  131 / 133 , then the peak error signal  151 p 1 ud/ 151 p 2 ud/ 151 n 1 ud/ 151 n 2 ud is asserted at a logic 1. However, if the input data signal  117  remains less than the P/N data peak reference signal  131 / 133  throughout such time interval DT 1 , then the peak error signal  151 p 1 ud/ 151 p 2 ud/ 151 n 1 ud/ 151 n 2 ud remains de-asserted at a logic zero. When this signal  151 p 1 ud/ 151 p 2 ud/ 151 n 1 ud/ 151 n 2 ud is asserted, it represents the error between the peak of the input data signal  117  and the P/N data peak reference signal  131 / 133  during the corresponding time interval. At the end of such time interval DT 1 , the corresponding peak error validation signal  151 p 1 v/ 151 n 1 v/ 151 p 2 v/ 151 n 2 v is asserted to indicate that the state of the peak error signal  151 p 1 ud/ 151 p 2 ud/ 151 n 1 ud/ 151 n 2 ud is valid for purposes of identifying any signal errors occurring during such time interval DT 1 . Also at the end of such time interval DT 1 , coincident with the peak error validation signals  151 p 1 v/ 151 n 1 v,  151 p 2 v/ 151 n 2 v, and after the input data signal  117  has transitioned back through the level of the positive/negative reference signal  135   a / 135   c,  the reset signal  413  resets the RS flip-flop  402 . 
     Additional time windows DT 2 (1), DT 2 (2), . . . are created as necessary, depending upon the duration of the input data signal  117  pulse. The first error validation signal  151 p 1 v/ 151 n 1 v is used for validating the peak error information (i.e., the peak error signal  151 p 1 ud/ 151 p 2 ud/ 151 n 1 ud/ 151 n 2 ud) corresponding to errors identified as having occurred during time interval DT 1 . Similarly, the second error validation signal  151 p 2 v/ 151 n 2 v is used for validating the peak error information corresponding to errors identified as having occurred during subsequent DT 2 (n) time intervals. The position of the time window within the pulse width determines the relative frequency band within which the peak error is to be evaluated. For example, the peak error information evaluated in a time window close to the rising edge of the pulse, i.e., time interval DT 1 , represents the peak error at higher frequencies, while peak error information evaluated in a time window closer to the end of the pulse, i.e., time interval DT 2 (N), represents the peak error at lower frequencies. 
     Based upon the foregoing, a number of advantages of a peak error detector in accordance with the present invention can be seen. The peak error information generated at multiple frequency bands can be advantageously used for tracking peaks of the input signal, compensating for signal baseline wander and controlling adaptive equalization. An asynchronous RS flip-flop is used to detect signal peaks, thereby significantly reducing the required sampling frequency, i.e., the operating frequency of the circuit. No analog-to-digital converters are required, thereby providing a low cost, reliable and more easily manufactured design for high frequency applications. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.