Abstract:
A voltage or current regulator has a power DAC and ADC in a negative feedback loop, locked to a reference voltage or current. The ADC may have one or more parallel comparators followed by one or more parallel filters. The regulator may include a multiplexer to select between filter output signals and to forward the selected signal to the power DAC. The regulator may receive power management mode control codes to modify filter behavior and/or to select between multiple parallel filters. By modifying the loop behavior, the regulator is able to swiftly change between power management modes supporting different power level and noise profiles. Regulators with a single comparator can lock the output to a single reference voltage or current. Regulators with two comparators can regulate the output to vary within a range limited by an upper and a lower reference voltage or current.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application claims priority from U.S. Provisional Patent Application Ser. No. 62/292,841 (Agent Docket No. PERC15_02_P-US), entitled “Regulator Circuits and Methods”, filed on Feb. 8, 2016, which is hereby incorporated by reference as if set forth in full in this application for all purposes. 
     
    
     BACKGROUND 
       [0002]    The present invention relates generally to regulating energy that is supplied to electronic circuits and particularly to regulating energy within integrated circuits (ICs). 
         [0003]    Many electronic systems use supply voltage and/or supply current regulators to provide a stable supply of energy to a sensitive circuit; to provide energy at a different level than is available from the original energy source; and/or to shield an energy source from noise generated by one of the circuits that is using its energy. For instance, a 3.3V battery may be used as an energy source for a sensitive analog circuit operating at 1.5V and a noisy digital circuit operating at 1.0V. By providing the supply voltage for the analog circuit through a first regulator that bridges a 1.8V level shift and providing the supply voltage for the digital circuit through a second regulator that bridges a 2.3V level shift, the analog circuit may be protected twice from noise generated by the digital circuit that may otherwise leak via their battery connections. And both circuits can receive stable supply voltages mostly independent of the battery voltage which may gradually reduce as the battery&#39;s charge is used up. Regulators typically include an input for receiving raw energy from a power supply, a regulated output to which a power load may be connected, a reference input, and a ground terminal. A high-efficiency regulator forwards most of the energy received at the input to the power load, and loses only little energy flowing away through the ground terminal. 
         [0004]    Regulators often use a filter that may act as an energy buffer to smooth the energy level at its regulated output. They also often use a filter for the regulation mechanism itself, which may be achieved in a negative feedback loop, wherein the regulated energy level is compared with (subtracted from) a reference level. In those cases, a well-designed filter provides stability for the feedback loop. 
         [0005]    Power management in complex integrated circuits (ICs) may require multiple regulators, often integrated, to support multiple power domains and multiple modes of activity, such as OFF, various levels of standby and sleep mode, and a fully active mode. In some cases, circuits may abruptly switch from a power-saving mode to fully active mode, and the noise spectrum of energy used may change instantly. Conventional regulators are not adapted for such a change, and as a result, circuits may not be used in the most power saving mode available. Therefore, ICs with conventional regulators may use more energy than necessary. The present invention overcomes this problem and helps circuits operate at the lowest average power possible. 
         [0006]    Reference to any prior art in the specification is not, and should not be taken as, an acknowledgment or any form of suggestion that this prior art forms part of the common general knowledge in Australia, USA, or any other jurisdiction or that this prior art could reasonably be expected to be ascertained, understood and regarded as relevant by a person skilled in the art. 
       SUMMARY 
       [0007]    Integrated circuits (ICs) may include circuits that are sensitive to noise along with other circuits that generate a lot of noise. Regulators can provide noise isolation; they can provide energy at the right (voltage or current) level to each of the circuits. Power management in complex ICs may require multiple regulators, often integrated, supporting multiple power domains and multiple modes of activity, such as OFF, various levels of standby and sleep mode, and a fully active mode. In some cases, circuits may abruptly switch from a power-saving mode to fully active mode, and the noise spectrum of energy used may change instantly. Conventional regulators are not adapted for such a change, and as a result, circuits may not be put in the most power saving mode available. Therefore, ICs with conventional regulators may use more energy than necessary. The present invention overcomes this problem and helps circuits operate at the lowest average power possible. Embodiments of the present invention make it possible to provide strong noise isolation while switching very swiftly between various modes of power management. 
         [0008]    In a first aspect, embodiments of the invention provide a method of regulating supply energy. The method comprises receiving raw energy from a power supply and receiving a first digital control code. Embodiments forward a portion of the raw energy to a power load, wherein the portion is determined by the first digital control code. The embodiments sense a physical quantity, which may include a voltage or a current, in the power load, and forward it to an analog-to-digital converter (ADC). The ADC receives a first reference physical quantity, and based on the sensed physical quantity and the first reference physical quantity, it generates the first digital control code. The steps are repeated continuously to obtain a proportional relation between the sensed physical quantity and the first reference physical quantity. 
         [0009]    The embodiments may filter the ADC output code to obtain the digital control code. In some embodiments, filtering may include using a pole at frequency zero. In further embodiments, filtering may include using two poles at frequency zero and a single zero at a non-zero frequency. 
         [0010]    In embodiments, the ADC may comprise a first clocked comparator. They may receive a clock signal and, at a time of receiving a clock signal, compare the sensed physical quantity to the first reference physical quantity to obtain a first clocked comparator output code. Upon filtering the first clocked comparator output code to obtain the digital control code, these embodiments lock the sensed physical quantity to the first reference physical quantity. 
         [0011]    In further embodiments, the ADC may comprise a second clocked comparator. These further embodiments may receive a second reference physical quantity. At a time of receiving a clock signal, they compare the sensed physical quantity to both the first and second reference physical quantities. These embodiments combine the first and second clocked comparator output signals to obtain a combined filter input signal, which they filter in the first digital filter to obtain the updated first digital control code and to allow the sensed physical quantity to vary between the first and second reference physical quantities. 
         [0012]    Embodiments may receive a mode control code and use the mode control code to modify filter behavior and/or to select between multiple parallel filters. 
         [0013]    In a second aspect, embodiments of the invention provide a method of regulating supply energy that comprises receiving an analog control signal, receiving raw energy from a power supply, and forwarding a portion of the raw energy to a power load, wherein the portion is determined by the analog control signal. The embodiments sense a physical quantity related to the portion of the raw energy in the power load, and forward the sensed physical quantity (voltage or current) to a clocked comparator. In the clocked comparator they compare the sensed physical quantity with a reference physical quantity to obtain a clocked comparator output signal. They filter the clocked comparator output signal in two or more parallel analog filters. Based on a received mode control code, they select one of the analog filters&#39; output signal to be the analog control signal. 
         [0014]    In a third aspect, embodiments of the invention provide a level regulator circuit, comprising a power digital-to-analog converter (DAC) with a raw energy input, a digital control code input, and a regulated power output, wherein the raw energy input is configured to receive raw energy from a power supply, and the regulated power output is configured to deliver regulated energy to a power load; a clocked comparator, with a first input coupled with the regulated power output, and with a second input configured to receive a reference physical quantity; and a digital filter, with an input coupled to a clocked comparator output, and with a mode control code input, wherein the digital filter is capable of modifying filter parameters based on a code received on the mode control code input, and with an output coupled with the power DAC digital control code input. 
         [0015]    In a fourth aspect, embodiments of the invention provide a level regulator circuit, comprising a power digital-to-analog converter (DAC) with a raw energy input, a digital control code input, and a regulated power output, wherein the raw energy input is configured to receive raw energy from a power supply, and the regulated power output is configured to deliver regulated energy to a power load; a clocked comparator, with a first input coupled with the regulated power output, and with a second input configured to receive a reference physical quantity; two or more digital filters, each with an input coupled with a clocked comparator output; and a digital multiplexer with inputs each coupled with a separate output of the two or more digital filters, wherein the digital multiplexer is configured to receive a mode control code, and based on the mode control code select one of the two or more digital filters, and with an output coupled with the power DAC. 
         [0016]    In a fifth aspect, embodiments of the invention provide a range regulator circuit, comprising a power digital-to-analog converter (DAC) with a raw energy input, a digital control code input, and a regulated power output, wherein the raw energy input is configured to receive raw energy from a power supply, and the regulated power output is configured to deliver regulated energy to a power load; a first and a second clocked comparator, each with a first input coupled with the regulated power output, and with a second input configured to receive a separate reference physical quantity; and a first digital filter, with inputs coupled with outputs of the first and second clocked comparator, and with an output coupled with the power DAC digital control code input. 
         [0017]    In a sixth aspect, embodiments of the invention provide a two-step regulator system, comprising a range regulator with a raw energy input configured to receive raw energy from a power supply, two reference inputs, and a regulated power output coupled to an energy storage device; a level regulator with a raw energy input coupled to the range regulator regulated power output, one reference input, and a regulated power output coupled to a power load; wherein: the range regulator is configured to regulate a first physical quantity on the energy storage device between limits determined by signal levels on the two range regulator reference inputs; and the level regulator is configured to regulate a second physical quantity on the power load to a level determined by a signal level on the level regulator reference input. 
         [0018]    As used herein, except where the context requires otherwise, the term “comprise” and variations of the term, such as “comprising”, “comprises” and “comprised”, are not intended to exclude further additives, components, integers or steps. 
         [0019]    Further aspects of the present invention and further embodiments of the aspects described in the preceding paragraphs will become apparent from the following description, given by way of example and with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The invention will be described with reference to the drawings, in which: 
           [0021]      FIG. 1  illustrates an example digital regulator according to embodiments of the invention; 
           [0022]      FIG. 2  illustrates an example digital regulator with loop filtering according to embodiments of the invention; 
           [0023]      FIG. 3  illustrates an example mixed-signal regulator according to embodiments of the invention; 
           [0024]      FIG. 4  illustrates an example range regulator according to an embodiment of the invention; 
           [0025]      FIG. 5  illustrates an example multimode regulator according to an embodiment of the invention; 
           [0026]      FIG. 6  illustrates details of an example power DAC according to embodiments of the invention; 
           [0027]      FIG. 7  illustrates an example analog multimode regulator according to an embodiment of the invention; 
           [0028]      FIG. 8  illustrates an example two-step regulator system according to embodiments of the invention; and 
           [0029]      FIG. 9  illustrates an example method of dual mode regulation in a two-step regulator system according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    Integrated circuits (ICs) may include circuits that are sensitive to noise along with other circuits that generate a lot of noise. Regulators can provide noise isolation; they can provide energy at the right (voltage and/or current) level to each of the circuits. Power management in complex ICs may require multiple regulators, often integrated, supporting multiple power domains and multiple modes of activity, such as OFF, various levels of standby and sleep mode, and a fully active mode. In some cases, circuits may abruptly switch from a power-saving mode to fully active mode, and the noise spectrum of energy used may change instantly. Conventional regulators are not adapted for such a change, and as a result, circuits may not be put in the most power saving mode available. Therefore, ICs with conventional regulators may use more energy than necessary. The present invention overcomes these problems and helps circuits operate at the lowest average power possible. Embodiments of the present invention make it possible to provide strong noise isolation while switching very swiftly between various modes of power management. 
         [0031]      FIG. 1  illustrates an example digital regulator  101  according to embodiments of the invention. System  100  includes digital regulator  101  that supplies regulated energy to power load  102 . Digital regulator  101  receives raw energy from a power supply via VDD rail  103  and at least a portion of the raw energy flows through power load  102  to ground (GND) rail  104 . Digital regulator  101  includes a reference input  105  for receiving a first reference physical quantity, a raw energy input  110 , and a regulated energy output  111 . 
         [0032]    In an embodiment, VDD rail  103  may carry raw energy at a first voltage level, whereas the power load  102  may require energy regulated at a second voltage level. In another embodiment, VDD rail  103  may carry raw energy at a first current level, whereas the power load  102  may require energy regulated at a second current level. Whether the physical quantity to be regulated includes a voltage or a current, or both, or another quantity (e.g., temperature or emitted light) related to the energy in the power load, embodiments of the invention use the same basic method of regulation. 
         [0033]    The embodiment  101  of the digital regulator comprises an analog-to-digital converter (ADC)  112  and a power digital-to-analog (DAC)  113 . ADC  112  and power DAC  113  are configured in a negative feedback control loop whose operation may be described from any point in the loop. Power DAC  113 , at its digital input, receives a first digital control code. An initial value for the first digital control code may be pre-programmed or otherwise pre-supplied, or it may be supplied by the digital output of ADC  112 . 
         [0034]    Power DAC  113  receives raw energy from a power supply via VDD rail  103  at raw energy input  110 , and forwards a portion of the raw energy to power load  102  via regulated energy output  111 . The portion is determined by the first digital control code. A difference between the raw energy received and the regulated energy forwarded to power load  102  may flow away to ground via a regulator  101  ground terminal (not drawn). 
         [0035]    ADC  112 , at its analog input, senses a physical quantity related to the portion of the raw energy in the power load. If the sensed physical quantity is a voltage, an embodiment may directly (as drawn) couple the ADC  112  analog input with regulated energy output  111 , or indirectly via, for example, a resistive voltage divider network. If the physical quantity is a current, an embodiment may sense it in a variety of ways, as known in the art, for example employing a current mirror to obtain a copy of the sensed current, or employing a series resistor between power DAC  113  and regulated energy output  111  to convert the sensed current to a sensed voltage. ADC  112  receives a first reference physical quantity at its reference input  105 , and generates an updated first digital control code based on the sensed physical quantity and the first reference physical quantity. In embodiments, the first digital control code may be based on a negative difference between the sensed physical quantity and the first reference physical quantity, divided by the first reference physical quantity. In other embodiments, there may be different relations between the first digital control code, the sensed physical quantity, and the first reference physical quantity. 
         [0036]    ADC  112  forwards the updated first digital control code to power DAC  113 , which in response to receiving a higher first digital control code value may increase the portion of raw energy forwarded to power load  102  and in response to receiving a lower first digital control code value may decrease the portion of raw energy forwarded to power load  102 . Since the loop features negative feedback, as known in the art the sensed physical quantity will stabilize to a value proportional to a value of the first reference physical quantity. Therefore, even though power load  102  may consume energy that varies over time, digital regulator  101  regulates the available energy as expressed by the sensed physical quantity at a stable level determined by the first reference physical quantity. Therefore, for the purposes of this document, digital regulator  101  is classified as a level regulator. 
         [0037]    ADCs and DACs often operate on the basis of a sample clock, where a converter may provide an updated value at its output each one or more clock periods. ADC  112  and power DAC  113  may be clocked converters or they may be instantaneous converters, in which case their output value would change as soon as their input value changes. 
         [0038]      FIG. 2  illustrates an example digital regulator  201  with loop filtering according to embodiments of the invention. System  200  includes digital regulator  201 , power load  202 , VDD rail  203 , GND rail  204 , reference input  205 , raw energy input  210 , regulated energy output  211 , ADC  212 , first digital filter  214 , power DAC  213 , and mode control (CTL) input  215 . Power DAC  213 , ADC  212 , and first digital filter  214  are configured in a negative feedback control loop. Like digital regulator  101 , digital regulator  201  is a level regulator. 
         [0039]    First digital filter  214  generates a first digital control code and its updates by performing operations, comprising filtering, on the ADC  212  digital output values. First digital filter  214  is included in a forward part of the negative feedback control loop, where it impacts the loop&#39;s behavior, including the speed at which the regulator can respond to changes, as well as the regulator&#39;s stability and accuracy. In some embodiments, first digital filter  214  may include a pole at frequency zero. In further embodiments, first digital filter  214  may include two poles at frequency zero and a single zero at a non-zero frequency. In yet further embodiments, first digital filter  214  may include any number of poles and/or zeros at any frequencies. 
         [0040]    In a system  200  where power load  202  may have characteristics that are very dependent on, for example, a power management mode setting, such as power-saving or fully active mode, the requirements for first digital filter  214  to provide speed, accuracy, and stability may quickly change. Therefore, a mode control code reflecting a power management status that controls power load  202  also includes useful information for digital regulator  201  and first digital filter  214 . Embodiments of the invention include mode control input  215  configured to receive a mode control code, where different mode control codes may identify, for example, an OFF mode, a fully active mode, a deep sleep mode, a standby mode, and so on. Mode control codes may be one or more bits wide. Although in this example power management was given as a reason to control modes, other system management may also control modes for individual blocks. For example, in a communication system, blocks may be put in different modes dependent on a direction of communication, etc. In embodiments, first digital filter  214  is configured to change between sets of filter coefficients or other filter parameters based on the mode control code received. For instance, if digital filter  214  includes a finite impulse response (FIR) filter, or an infinite impulse response (IIR) filter, the mode control code may dictate the use of a first, second, and so on, set of filter coefficients. Embodiments may include sets of pre-programmed filter coefficients to enable instant change of regulator characteristics along with the controlled status. Further embodiments may include storage of alternate state information for different modes. While system  200  depicted in  FIG. 2  shows power load  202  and first digital filter  214  receiving the same mode control code, in some embodiments first digital filter  214  may receive a different, but related, mode control code than power load  202 . 
         [0041]      FIG. 3  illustrates an example mixed-signal regulator  301  according to embodiments of the invention. System  300  includes mixed-signal regulator  301 , power load  302 , VDD rail  303 , GND rail  304 , reference input  305 , raw energy input  310 , regulated energy output  311 , first clocked comparator  312 , first digital filter  314 , power DAC  313 , mode control input  315  and clock (CLK) input  316 . Power DAC  313 , first clocked comparator  312 , and first digital filter  314  are configured in a negative feedback control loop. Like digital regulators  101  and  201 , mixed-signal regulator  301  is a level regulator. 
         [0042]    First clocked comparator  312  acts as a 1-bit ADC and fulfills the function of ADC  212  in  FIG. 2 . In the embodiments depicted in  FIG. 3 , first clocked comparator  312  receives a CLK signal from CLK input  316  which triggers a comparison between a first reference physical quantity received at reference input  305  and a sensed physical quantity from regulated energy output  311 . For instance, if the first reference physical quantity is greater than the sensed physical quantity, first clocked comparator  312  will show a digital code “1” at its output, and if the sensed physical quantity is greater than the first reference physical quantity, first clocked comparator  312  will show a digital code “0” at its output. First digital filter  314  receives the successive 1-bit digital words from the clocked comparator  312  output and executes a filtering action on them to provide speed, accuracy and stability in the negative feedback loop. In some embodiments, first digital filter  314  may include a pole at frequency zero. In further embodiments, first digital filter  314  may include two poles at frequency zero and a single zero at a non-zero frequency. In yet further embodiments, first digital filter  314  may include any number of poles and/or zeros at any frequencies. At its output, first digital filter  314  produces a first digital control code and its updates as input signals for power DAC  313 . 
         [0043]    System  300  receives a CLK signal on clock input  316 , and provides it to first clocked comparator  312  and first digital filter  314 . Some embodiments of the invention may also provide the clock to power DAC  313  and further embodiments may provide the clock to power load  302 . In yet further embodiments, power load  302  may use additional and/or entirely different clock signals. 
         [0044]    Embodiments provide mode control codes received on mode control input  315  to first digital filter  314  to enable it to change between sets of filter coefficients, or to change between sets of other filter parameters. While system  300  depicted in  FIG. 3  shows power load  302  and first digital filter  314  receiving the same mode control code, in some embodiments first digital filter  314  may receive a different, but related, mode control code than power load  302 . 
         [0045]      FIG. 4  illustrates an example range regulator  401  according to an embodiment of the invention. System  400  includes digital regulator  401 , power load  402 , VDD rail  403 , GND rail  404 , first reference input  405 H, second reference input  405 L, raw energy input  410 , regulated energy output  411 , first clocked comparator  412 H, second clocked comparator  412 L, combiner  417 , first digital filter  414 , power DAC  413 , mode control input  415 , clock input  416 , and energy storage device  423 . Power DAC  413 , energy storage device  423 , first clocked comparator  412 H, second clocked comparator  412 L, combiner  417 , and first digital filter  414  are configured in a negative feedback control loop. 
         [0046]    In embodiments, energy storage device  423 , depicted in  FIG. 4  as a capacitor, may include at least one of a capacitor, an inductor, and a rechargeable battery. Power load  402  may comprise an energy dissipating load, depicted in  FIG. 4  as a resistor. 
         [0047]    For the purposes of this document, a range regulator constitutes a regulator that is capable of regulating available energy as expressed by a sensed physical quantity within a range determined by a first reference physical quantity and a second reference physical quantity, wherein the sensed physical quantity is related to a portion of raw energy that is available in the power load. The sensed physical quantity may be a voltage, a current, or any other physical quantity that relates to the portion of the raw energy. First clocked comparator  412 H receives the first reference physical quantity at its REFH input at  405 H, and second clocked comparator  412 L receives the second reference physical quantity at its REFL input at  405 L. 
         [0048]    When first clocked comparator  412 H and second clocked comparator  412 L receive a CLK signal from CLK input  416 , they compare the sensed physical quantity with the first and the second reference physical quantities, respectively. At their outputs, first and second clocked comparators  412 H-L will show digital codes representing the results of both comparisons, wherein the digital codes may include 1-bit digital words. Combiner  417  receives and combines the respective digital codes. The combining it performs may include, for example: producing a combined digital code “1” when both received digital codes are “1”; producing a combined digital code “4” when both received digital codes are “0”; and producing a combined digital code “0” when the two received digital codes do not match each other. 
         [0049]    First digital filter  414  receives the combined digital code at its input, and executes a filtering action on it. The filtering action may include any filtering methods known in the art to provide speed, accuracy and stability in a negative feedback loop. In some embodiments, first digital filter  414  may include a pole at frequency zero. In further embodiments, first digital filter  414  may include two poles at frequency zero and a single zero at a non-zero frequency. In yet further embodiments, first digital filter  414  may include any number of poles and/or zeros at any frequencies. At its output, first digital filter  414  produces a first digital control code and its updates as input signals for power DAC  413 . In an example embodiment in which first digital filter  414  includes a simple integrator, an integrated number value inside digital filter  414  may increase when the combined digital code equals “1”, or it may decrease when the combined digital code equals “4”, or it may remain unaltered when the combined digital code equals “0”. 
         [0050]    Some embodiments of the invention may include a mode control input  415  configured to receive a mode control code, as discussed previously. Mode control codes may be one or more bits wide. In these embodiments, first digital filter  414  is configured to change between sets of filter coefficients or other filter parameters based on the mode control code received. Further embodiments may include sets of pre-programmed filter coefficients to enable instant change of regulator characteristics along with the power management status. 
         [0051]      FIG. 5  illustrates an example multimode regulator  501  according to an embodiment of the invention. System  500  includes multimode regulator  501 , power load  502 , VDD rail  503 , GND rail  504 , first reference input  505 , raw energy input  510 , regulated energy output  511 , first clocked comparator  512 , first digital filter  514   a , second digital filter  514   b , multiplexer (MUX)  517 , power DAC  513 , mode control input  515  and clock input  516 . Power DAC  513 , first clocked comparator  512 , first digital filter  514   a , second digital filter  514   b , and multiplexer  517  are configured in a negative feedback control loop. 
         [0052]    Multimode regulator  501  functions in a manner similar to mixed-signal regulator  301  in  FIG. 3 . However, first clocked comparator  512  forwards its output digital codes in parallel to first digital filter  514   a  and second digital filter  514   b , or in general, to two or more digital filters. Each of the two or more digital filters has an output coupled to a multiplexer  517  input. Each of the two or more digital filters, and multiplexer  517 , receive a mode control code from mode control input  515 . Based on the received mode control code, multiplexer  517  selects an output signal of one of the two or more digital filters, and forwards it to power DAC  513 . Each of the two or more digital filters may execute a filtering action on output digital codes received from clocked comparator  512 , wherein the filtering action is determined by the mode control code. For instance, the mode control code can determine a set of filter coefficients or other filter parameters applied to a filter. In some embodiments, the mode control code can further control if a filter is active or not. For some modes, it may interrupt clock signals received from clock input  516 , so that a filter becomes inactive and saves power. 
         [0053]    By applying multiple digital filters  514  instead of a single digital filter, it becomes possible to have smoother transitions when system  500  switches between modes. Having separate digital filters allows a state to be stored for each mode defined by the mode control input  515 . This allows regulator  501  to change the delivered output power much more rapidly than either of the digital filters  514  can respond. For example, if the load is switched from a sleep mode, consuming very little power, to an active mode, consuming significant power, switching between filters can support the new power needs much more quickly than either filter  514  could respond. 
         [0054]      FIG. 6  illustrates details of an example power DAC according to embodiments of the invention. System  600  includes power DAC  613 , power load  602 , VDD rail  603 , GND rail  604 , raw energy input  610 , regulated energy output  611 , optional clock input  616 , transistors  620 - 622 , digital input  625 , and optional latches  630 . 
         [0055]    Power DAC  613  delivers a portion of raw energy available at its raw energy input  610  to power load  602  via regulated energy output  611 . The portion is determined by a digital control code, which may have a width of N bits. Power DAC  613  receives the digital control code a 0  . . . a N-1  awl at its digital input  625 . Some embodiments may be clocked, as shown, where digital control code a 0  . . . a N-1  is forwarded to latches  630 . Upon receiving a clock pulse from clock input  616 , latches  630  may forward digital control code a 0  . . . a N-1  to transistors  620 - 622  as clocked digital control code b 0  . . . b N-1 . Other embodiments may not use optional clock input  616  and may not have latches  630 . Those embodiments directly forward digital control code a 0  . . . a N-1  to transistors  620 - 622 . 
         [0056]    A bit a i  or b i  from the digital control code or clocked digital control code activates or deactivates corresponding transistor M i , which forwards a portion of the raw energy available at raw energy input  610  to power load  602  via regulated energy output  611 . Transistors M 0  . . . M N-1  ( 620 - 622 ) may be substantially equal sized, or they may have increasing sizes to give the bits of the digital control code increasing values. For instance, M 0  could have a unit size, M 1  could have 2 units size, M 2  could have 4 units size, etc., to stepwise linearly support control codes with binary numbers. Other embodiments could implement stepwise non-linear relations with the control code. An active transistor M i  will forward a portion of the raw energy that is proportional to its size. Therefore, dependent on the digital control code, power DAC  613  will forward a smaller or larger portion of the raw energy available at raw energy input  610  to power load  602 . 
         [0057]    Some embodiments may include a resistor in series with the source or drain of each of the transistors M 0  . . . M N-1  ( 620 - 622 ). Yet other embodiments may include a current source in series with the source of each of the transistors M 0  . . . M N-1  ( 620 - 622 ) or a cascode transistor in series with the drain of each of the transistors M 0  . . . M N-1  ( 620 - 622 ). 
         [0058]    The embodiment of power DAC  613  depicted in  FIG. 6  is a very basic implementation of a DAC. The art knows many refinements that may lead to greater accuracy, speed, and efficiency. Embodiments may include any such refinements, without departure from the scope of the invention. 
         [0059]      FIG. 7  illustrates an example analog multimode regulator  701  according to an embodiment of the invention. System  700  includes analog multimode regulator  701 , power load  702 , VDD rail  703 , GND rail  704 , first reference input  705 , raw energy input  710 , regulated energy output  711 , first comparator  712 , first analog filter  714   a , second analog filter  714   b , multiplexer (MUX)  717 , power stage  713 , and mode control input  715 . Power stage  713 , first comparator  712 , first analog filter  714   a , second analog filter  714   b , and multiplexer  717  are configured in a negative feedback control loop. 
         [0060]    Analog multimode regulator  701  functions in a manner similar to multimode regulator  601  depicted in  FIG. 6 . However, this embodiment functions using analog techniques. Comparator  712  forwards its output results in parallel to first analog filter  714   a  and second analog filter  714   b , or in general, to two or more analog filters. Each of the two or more analog filters has an output coupled to a multiplexer  717  input. Multiplexer  717  receives a mode control code from mode control input  715 . Based on the received mode control code, multiplexer  717  selects an output signal of one of the two or more analog filters, and forwards it to power stage  713 . Each of the two or more analog filters performs a filtering action on the closed loop signal. The analog filter whose output signal is forwarded by multiplexer  717  to output stage  713  determines the characteristics of the closed loop, including which portion of energy available on raw energy input  710  is forwarded to power load  702  via regulated energy output  711 . A reference physical quantity received on first reference input  705  and the mode control code determine the amount of energy the embodiment forwards to power load  702 , as well as the general behavior of analog multimode regulator  701 . 
         [0061]    Some embodiments may leave out comparator  712 , and simply provide a subtractor to subtract a physical quantity sensed at regulated energy output  711  from a first reference physical quantity, and provide the result to the two or more analog filters. 
         [0062]    Some embodiments may include a single transistor as analog multimode regulator  701 &#39;s power stage  713 . Other embodiments may include more sophisticated power stages, as known in the art. 
         [0063]      FIG. 8  illustrates an example  800  two-step regulator system according to embodiments of the invention. It combines use of a range regulator  801   a  and a level regulator  801   b . Example  800  further includes VDD rail  803 , GND rail  804 , range high reference input  805 H, range low reference input  805 L, level reference input  805 F, raw energy input  810   a , and range regulated energy output  811   a , range regulated energy input  810   b , and level regulated energy output  811   b , energy storage device  802   a , and power load  802   b . With reference to energy storage device  423  in  FIG. 4 , energy storage device  802   a  in  FIG. 8  may be viewed as an integral part of range regulator  801   a.    
         [0064]    Combined use of a range regulator and a level regulator serves the dual purposes of providing a well regulated level of energy to a power load that may require big bursts of energy and reducing the noise impact that such bursts may have on the original source of raw energy. 
         [0065]    In embodiments, energy storage device  802   a  may comprise at least one of a capacitor, an inductor, and a rechargeable battery. 
         [0066]    Range regulator  801   a  takes a first portion of raw energy available at VDD rail  803  via its raw energy input  810   a  and forwards it via range regulated energy output  811   a  to energy storage device  802   a  and level regulator  801   b . The first portion splits in a second portion going into energy storage device  802   a  and a third portion going into level regulator  801   b . Energy storage device  802   a  stores energy. Some of the time, the second portion may be zero, and during this time energy storage device  802   a  may deliver part of its stored energy to level regulator  801   b , so that the total energy available to level regulator  801   b  exceeds the third portion. 
         [0067]    Range regulator  801   a  regulates energy at its range regulated energy output  811   a  such that a first sensed physical quantity (at  811   a ) will remain between range low reference physical quantity REFL and range high reference physical quantity REFH as received on range low reference input  805 L and range high reference input  805 H. In some embodiments, the first sensed physical quantity, the range low reference and range high reference physical quantities REFL and REFH may comprise voltages. In other embodiments, they may comprise currents. In yet other embodiments they may comprise physical quantities other than voltages or currents. 
         [0068]    Level regulator  801   b  takes the energy available at its range regulated energy input  810   b  from range regulator  801   a  and energy storage device  802   a  and forwards a fourth portion of it to power load  802   b.    
         [0069]    Level regulator  801   b  regulates energy at its level regulated energy output  811   b  such that a second sensed physical quantity (at  811   b ) will lock to the level reference physical quantity REF as received on level reference input  805 F. In some embodiments, the second sensed physical quantity and the level reference physical quantity REF may comprise voltages. In other embodiments, they may comprise currents. In yet other embodiments they may comprise physical quantities other than voltages or currents. 
         [0070]    Filters in level regulator  801   b  may be optimized for known characteristics of the signal on range regulated energy input  810   b . For example, if power load  802   b  periodically transitions through a known sequence of states and level regulator  801   b  delivers the correct power for each one (CTL signals are not shown in  FIG. 8 ). This periodic sequence of power use will result in a predictable change in the signal on range regulated energy input  810   b . The filters can be optimized to remove components of the periodic signal from the level regulated energy output  811   b.    
         [0071]      FIG. 9  illustrates an example method of dual mode regulation in a two-step regulator system according to an embodiment of the invention. Referring to  FIG. 8 , I 1  (not depicted here) represents a current flowing into raw energy input  810   a ; I 2  represents current flowing into range regulated energy input  810   b ; I 3  represents current flowing into energy storage device  802   a ; and V CAP  represents a voltage across energy storage device  802   a , which is also the input voltage of level regulator  801   b.    
         [0072]    The method in  FIG. 9  shields the raw energy source from noise bursts caused by periodic bursts in energy use by power load  802   b , while providing power load  802   b  with a steady level of energy. It assumes that bursts occur sufficiently close to each other and that each burst consumes not too little and not too much energy. The method attempts to keep I 1  at a constant level. It can be seen that I 1  splits into I 2  and I 3 , therefore I 1 =I 2 +I 3 =constant. 
         [0073]    Graph  901  shows current I 2  over time. Prior to time t 1 , its level is low (STDBY). From time t 1  to t 2  it is high (PEAK), after which it goes low again. It goes high again from t 3  to t 4 , and from t 5  to t 6 . 
         [0074]    The method in this embodiment keeps I 1  at a constant level higher than STDBY, but lower than PEAK. Therefore, current I 3  is positive when I 2 =STDBY, and energy storage device  802   a  increases its stored energy. However, when I 2 =PEAK, current I 3  is negative and energy storage device  802   a  delivers energy. This is shown in graph  903 . If energy storage device  802   a  is a capacitor, as shown in  FIG. 8 , then the voltage V CAP  will increase during STDBY and decrease during PEAK, as shown in graph  902 . Range regulator  801   a  regulates V CAP  to stay between the REFH and REFL levels. The system provides high isolation to the raw energy source from noise generated by power load  802   b  as long as V CAP  stays between the REFH and REFL levels, without reaching them. Should VCAP reach REFH during STDBY, then I 1  will diminish until the next burst appears. Should VCAP reach REFL during a burst, then I 1  will increase until the end of the burst to prevent the capacitor from further discharging. 
         [0075]    Although the description has been described with respect to particular embodiments thereof, these particular embodiments are merely illustrative, and not restrictive. All such variations and modifications are to be considered within the ambit of the present invention the nature of which is to be determined from the foregoing description. 
         [0076]    It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text or drawings. All of these different combinations constitute various alternative aspects of the invention. 
         [0077]    Any suitable technology for manufacturing electronic devices can be used to implement the circuits of particular embodiments, including bipolar, JFET, MOS, NMOS, PMOS, CMOS, BiCMOS, HBT, MESFET, FinFET, etc. Different semiconductor materials can be employed, such as silicon, germanium, SiGe, GaAs, InP, graphene, etc. Circuits may have single-ended or differential inputs, and single-ended or differential outputs. Terminals to circuits may function as inputs, outputs, both, or be in a high-impedance state, or they may function to receive supply power, a ground reference, a reference voltage, a reference current, or other. Although the physical processing of signals may be presented in a specific order, this order may be changed in different particular embodiments. In some particular embodiments, multiple elements, devices, or circuits shown as sequential in this specification can be operating in parallel. 
         [0078]    Particular embodiments may be implemented in a computer-readable storage medium for use by or in connection with an instruction execution system, apparatus, system, or device. Particular embodiments can be implemented in the form of control logic in software, firmware, hardware or a combination of those. The control logic, when executed by one or more processors, may be operable to perform that which is described in particular embodiments. For example, a tangible medium such as a hardware storage device can be used to store the control logic, which can include executable instructions. 
         [0079]    It will also be appreciated that one or more of the elements depicted in the drawings/figures can also be implemented in a more separated or integrated manner, or even removed or rendered as inoperable in certain cases, as is useful in accordance with a particular application. It is also within the spirit and scope to implement a program or code that can be stored in a machine-readable medium to permit a computer to perform any of the methods described above. 
         [0080]    As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. 
         [0081]    Thus, while particular embodiments have been described herein, latitudes of modification, various changes, and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of particular embodiments will be employed without a corresponding use of other features without departing from the scope and spirit as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the essential scope and spirit.