Abstract:
A charge pump circuit includes a charging capacitor, a plurality of pumping capacitors, a charging circuit, and a pumping circuit. The charging circuit is configured for charging the charging capacitor when the charge pump circuit is under a charging phase; and the pumping circuit is configured for coupling the charging capacitor charged in the charging phase to a pumping capacitor to generate an output voltage level at the pumping capacitor according to a potential difference stored in the charging capacitor, when the charge pump circuit is under a pumping phase.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a charge pump circuit, and more particularly, to a charge pump that generates a plurality output voltage according to an input voltage, and a method thereof. 
     2. Description of the Prior Art 
     A charge pump circuit is one of the most important elements in a displaying apparatus. Normally, the charge pump circuit is utilized for generating an output voltage that is higher than an input voltage of the charge pump circuit. Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional charge pump circuit  100 . The charge pump circuit  100  includes a first input switch SW 1 , a second input switch SW 2 , a first output switch SW 3 , a second output switch SW 4 , a charging capacitor C 1 , and a pumping capacitor C 2 . A node N 1  of the first input switch SW 1  receives the input voltage V i , and a node N 2  of the second input switch SW 2  is coupled to a first ground reference voltage V g1 . The charging capacitor C 1  is coupled between nodes N 3  and N 4 , the pumping capacitor C 2  is coupled between nodes N 5  and N 6 , in which the node N 5  is utilized for outputting the output voltage V o  and the node N 6  is coupled to a second ground reference voltage V g2 . Furthermore, the first output switch SW 3  is coupled between the nodes N 3  and N 5 , and the second output switch SW 4  is coupled between the nodes N 4  and N 6 . 
     According to the conventional charge pump circuit  100 , when the first input switch SW 1  and the second input switch SW 2  are switched on, the electric charge corresponding to the voltage difference between the input voltage V i  and the first ground reference voltage V g1  is charged to the charging capacitor C 1 . Meanwhile, the first output switch SW 3  and the second output switch SW 4  are switched off. Then, the first output switch SW 3  and the second output switch SW 4  are switched on to pump the electric charge to the pumping capacitor C 2 . By appropriately setting the second ground reference voltage V g2  and the capacitance of the pumping capacitor C 2 , the output voltage V o  having a voltage level higher than the input voltage V i  can be generated. In view of the above-mentioned conventional charge pump circuit  100 , only one output voltage is generated by the group of a charging capacitor and a pumping capacitor. When a large number of output voltage need to be generated in the displaying apparatus, a large number of the group of a charging capacitor and a pumping capacitor are also required. Therefore, this will significantly increase the cost of the displaying apparatus. Therefore, utilizing a predetermined number of capacitor to generate a plurality of output voltages for lowering the cost of each charge pump circuit is an urgent problem in the field of displaying apparatus. 
     SUMMARY OF THE INVENTION 
     One of the objectives of the present invention is to provide a charge pump that generates a plurality of output voltages according to an input voltage, and a method thereof. 
     According to an embodiment of the present invention, a charge pump circuit is disclosed. The charge pump circuit comprises a charging capacitor, a plurality of pumping capacitors, a charging circuit, and a pumping circuit. The charging circuit is configured for charging the charging capacitor when the charge pump circuit is under a charging phase; and the pumping circuit is configured for coupling the charging capacitor charged in the charging phase to a pumping capacitor to generate an output voltage level at the pumping capacitor according to a potential difference stored in the charging capacitor, when the charge pump circuit is under a pumping phase. 
     According to another embodiment of the present invention, a method of controlling a charge pump circuit is disclosed. The method of controlling the charge pump circuit comprises the steps of: when the charge pump circuit is under a charging phase, charging a charging capacitor; and when the charge pump circuit is under a pumping phase, coupling the charging capacitor charged in the charging phase to a pumping capacitor selected from a plurality of pumping capacitors to generate an output voltage level at the pumping capacitor according to a potential difference stored in the charging capacitor. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a conventional charge pump circuit. 
         FIG. 2  is a diagram illustrating a charge pump circuit according to an embodiment of the present invention. 
         FIG. 3  is a timing diagram illustrating a first pulse signal, a second pulse signal, a clock signal, a first divided signal, a second divided signal, a combined signal, an inversed combined signal, a first pumping signal, and a second pumping signal of the charge pump circuit shown in  FIG. 2 . 
         FIG. 4  is a flowchart illustrating a method of controlling the charge pump circuit according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating a charge pump circuit  200  according to an embodiment of the present invention. The charge pump circuit  200  comprises a charging capacitor C 1 , a first pumping capacitor C 2 , a second pumping capacitor C 3 , a charging circuit  206 , and a pumping circuit  208 . The pumping circuit  208  comprises a first switch S 1  coupled between a first node N 1  of the charging capacitor C 1  and the first node N 3  of the first pumping capacitor C 2 ; a second switch S 2  coupled between a second node N 2  of the charging capacitor C 1  and the second node N 4  of the first pumping capacitor C 2 ; a third switch S 3  coupled between the first node N 1  of the charging capacitor C 1  and the first node N 5  of the second pumping capacitor C 3 ; and a fourth switch S 4  coupled between the second node N 2  of the charging capacitor C 1  and the second node N 6  of the second pumping capacitor C 3 . The charging circuit  206  comprises a first charging switch S 5  coupled between a first voltage level V 1  and the first node N 1  of the charging capacitor C 1 ; and a second charging switch S 6  coupled between a second voltage level VSS 1  and the second node N 2  of the charging capacitor C 1 . The charge pump circuit  200  further comprises a switch control circuit  210 . 
     The switch control circuit  210  comprises a control circuit  2102 , a frequency divider  2104 , and a clock generator  2106 . The control circuit  2102  generates a first pulse signal CH 1  and a second pulse signal CH 2  according to a clock signal CK as shown in  FIG. 3 , in which the first pulse signal CH 1  is utilized to control the first charging switch S 5  and the second charging switch S 6 .  FIG. 3  is a timing diagram illustrating the first pulse signal CH 1 , the second pulse signal CH 2 , the clock signal CK, a first divided signal P 2 , a second divided signal P 4 , a combined signal DIV 0 , an inversed combined signal DIV 1 , a first pumping signal VP 1 , and a second pumping signal VP 2 , in which the first pumping signal VP 1  is utilized to control the first switch S 1  and the second switch S 2 , and the second pumping signal VP 2  is utilized to control the third switch S 3  and the fourth switch S 4 . The frequency divider  2104  comprises a first flip-flop FF 1  having a clock input node CLK coupled to the second pulse signal CH 2 , a data input node D, an inverted data output node QB coupled to the data input node D, and a non-inverted output node Q for outputting the first dividing clock P 2 ; and a second flip-flop FF 2  having a clock input node CLK coupled to the first dividing clock P 2 , a data input node D, an inverted data output node QB coupled to the data input node D of the second flip-flop FF 2 , and a non-inverted output node Q for outputting the second dividing clock P 4 . The clock generator  2106  comprises a NOR gate  2106   a  coupled to the frequency divider  2106  for performing a NOR operation upon the first dividing clock P 2  and the second dividing clock P 4  to generate the combined signal DIV 0 ; an inverter  2106   b  coupled to the NOR gate  2106   a  for inverting the combined signal DIV 0  to generate an inverted combined signal DIV 1 ; a delay circuit  2106   c  for delaying the second pulse signal CH 2  to generate a delayed second pulse signal CH 2   —   d;  a first NAND gate  2106   d  coupled to the inverter  2106   b  and the delay circuit  2106   c  for performing a NAND operation upon the delayed second pulse signal CH 2   —   d  and the inverted combined signal DIV 1  to generate the first pumping signal VP 1 ; and a second NAND gate  2106   e  coupled to the NOR gate  2106   a  and the delay circuit  2106   c  for performing a NAND operation upon the delayed second pulse signal CH 2   —   d  and the combined signal DIV 0  to generate the second pumping signal VP 2 . Furthermore, an inverter  2106   f  is utilized to generate a first complementary version signal VP 1 _bar of the first pumping signal VP 1 , and an inverter  2106   g  is utilized to generate a second complementary version signal VP 2 _bar of the second pumping signal VP 2 . Then, the first complementary version signal VP 1 _bar of the first pumping signal VP 1  is utilized to control the first switch S 1  and the second switch S 2 , and the second complementary version signal VP 2 _bar of the second pumping signal VP 2  is utilized to control the third switch S 3  and the fourth switch S 4 . Please note that, since the first switch S 1 , the second switch S 2 , the third switch S 3 , the fourth switch S 4 , the first charging switch S 5 , and the second charging switch S 6  are implemented by one transistor switch in this embodiment, thus the first pulse signal CH 1  can be utilized to control the first charging switch S 5  and the second charging switch S 6 , the first complementary version signal VP 1 _bar of the first pumping signal VP 1  can be utilized to control the first switch S 1  and the second switch S 2 , and the second complementary version signal VP 2 _bar of the second pumping signal VP 2  can be utilized to control the third switch S 3  and the fourth switch S 4 . This is not a limitation of the present invention, however. In other words, the above-mentioned switches can also be implemented by a CMOS transistor switch. In this case, some modification may need to be performed upon the switch control circuit  210  of the above-mentioned embodiment to generate a complementary control signal for the CMOS transistor switch. For example, an inverter (not shown) can be utilized to generate the complementary version of the first pulse signal CH 1 , the first pumping signal VP 1  and the first complementary version signal VP 1 _bar can be utilized to control the CMOS transistor switch, and the second pumping signal VP 2  and the second complementary version signal VP 2 _bar can be utilized to control the other CMOS transistor switch. 
     Please refer to  FIG. 2  in conjunction with  FIG. 3 . The control circuit  2102  generates the first pulse signal CH 1  in each cycle of the inputted clock signal CK as shown in  FIG. 3 . Then, during a charging phase of the charge pump circuit  200 , the first pulse signal CH 1  switches on the first charging switch S 5  and the second charging switch S 6  to charge the charging capacitor C 1  according to the first voltage level V 1  and the second voltage level VSS 1 . Then, the switch control circuit  210  switches on the first switch S 1  and the second switch S 2  to pump the first pumping capacitor C 2  according to the first complementary version signal VP 1 _bar, and switches on the third switch S 3  and the fourth switch S 4  to pump the second pumping capacitor C 3  according to the second complementary version signal VP 2 _bar during a pumping phase. Furthermore, according to the embodiment of the present invention, the frequency of the first complementary version signal VP 1 _bar is determined by the loading of a first loading circuit (not shown) that is coupled to the first pumping capacitor C 2 , while the frequency of the second complementary version signal VP 2 _bar is determined by the loading of a second loading circuit (not shown) that is coupled to the second pumping capacitor C 3 . In other words, the switch control circuit  210  allocates the pulses of the second pulse signal CH 2  to generate the first complementary version signal VP 1 _bar and the second complementary version signal VP 2 _bar, wherein if the first loading circuit requires more current than the second loading circuit, the first complementary version signal VP 1 _bar has more pulses than the second complementary version signal VP 2 _bar as shown in  FIG. 3 , and vice versa. In  FIG. 2 , the first flip-flop FF 1  divides the frequency of the second pulse signal CH 2  by two to generate the first divided signal P 2  having 50% duty cycle, and the second flip-flop FF 2  further divides the frequency of the first divided signal P 2  by two to generate the second divided signal P 4  having 50% duty cycle. Then, the NOR gate  2106   a  and the inverter  2106   b  are respectively utilized for generating the combined signal DIV 0  and the inversed combined signal DIV 1 . Then, the NAND gate  2106  performs a NAND operation upon the inversed combined signal DIV 1  and the delayed second pulse signal CH 2   —   d  for generating the first pumping signal VP 1 , in which the delayed second pulse signal CH 2   —   d  is the delay version of the second pulse signal CH 2 . The NAND gate  2106   e  also performs the NAND operation upon the combined signal DIV 0  and the delayed second pulse signal CH 2   —   d  for generating the second pumping signal VP 2 . Then, the inverter  2106   f  generates the first complementary version signal VP 1 _bar of the first pumping signal VP 1 , and the inverter  2106   g  generates the second complementary version signal VP 2 _bar of the second pumping signal VP 2 . Accordingly, in every four pulses of the second pulse signal CH 2 , three pulses (i.e., the pulses at time T 1 , T 2 , and T 3 ) are allocated for the first complementary version signal VP 1 _bar and one pulse (i.e., the pulse at time T 4 ) is allocated for the second complementary version signal VP 2 _bar. Please note that the above-mentioned switch control circuit  210  and the corresponding pulse allocating ratio are not limitations of the present invention, and those skilled in this art can obtain any pulse allocating ratio through appropriate modifications upon the switch control circuit  210 . This also falls within the scope of the present invention. 
     Accordingly, the pulses of the first pulse signal CH 1  do not overlap with the pulses of the first complementary version signal VP 1 _bar and the second complementary version signal VP 2 _bar. Furthermore, the pulses of the first complementary version signal VP 1 _bar do not overlap with the pulses of the second complementary version signal VP 2 _bar. Therefore, when the pulses of the first complementary version signal VP 1 _bar switch on the first and the second switches S 1 , S 2  concurrently to pump the first pumping capacitor C 2 , a first output voltage V 2  is generated at the first node N 3  of the first pumping capacitor C 2 , wherein the first output voltage V 2  depends on a potential difference stored in the charging capacitor C 1  and a third voltage level VSS 2  at the second node N 4  of the first pumping capacitor C 2 . Similarly, when the pulses of the second complementary version signal VP 2 _bar switch on the third and the fourth switches S 3 , S 4  concurrently to pump the second pumping capacitor C 3 , a second output voltage V 3  is generated at the first node N 5  of the second pumping capacitor C 3 , wherein the second output voltage V 3  depends on the potential difference stored in the charging capacitor C 1  and a fourth voltage level VSS 3  at the second node N 6  of the second pumping capacitor C 3 . 
     Therefore, according to the above-mentioned embodiment of the present invention, two output voltages (i.e., V 2 , V 3 ) can be generated by utilizing only one charging capacitor (i.e., C 1 ). Please note that this is not a limitation of the present invention. Those skilled in this art will readily understand that more than two output voltages can also be generated through appropriate modifications upon the charge pump circuit  200  by only utilizing one charging capacitor. 
     Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating a method  400  of controlling a charge pump circuit according to another embodiment of the present invention. Provided that substantially the same result is achieved, the steps of the flowchart shown in  FIG. 4  need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate. In addition, in order to describe the spirit of the present invention more clearly, the method  400  of controlling the charge pump circuit is described in associated with the charge pump circuit  200  in  FIG. 2 . 
     The method  400  comprises the following steps: 
     Step  402 : Generate the first pulse signal CH 1 ; 
     Step  404 : Charge the charging capacitor C 1  of the charge pump circuit  200  according to the first pulse signal CH 1 ; 
     Step  406 : Generate the first complementary version signal VP 1 _bar and the second complementary version signal VP 2 _bar; 
     Step  408 : Pump the first pumping capacitor C 2  to generate the first output voltage V 2  according to the first complementary version signal VP 1 _bar; 
     Step  410 : Pump the second pumping capacitor C 3  to generate the second output voltage V 2  according to the second complementary version signal VP 2 _bar. 
     According to the method  400 , the pulses of the first pulse signal CH 1  do not overlap the pulses of the first complementary version signal VP 1 _bar and the second complementary version signal VP 2 _bar, and the pulses of the first complementary version signal VP 1 _bar do not overlap the pulses of the second complementary version signal VP 2 _bar. Furthermore, in the steps  408  and  410 , the first output voltage V 2  depends on a potential difference stored in the charging capacitor C 1  and the third voltage level VSS 2  at the second node N 4  of the first pumping capacitor C 2  (as shown in  FIG. 2 ), and the second output voltage V 3  also depends on the potential difference stored in the charging capacitor C 1  and the fourth voltage level VSS 3  at the second node N 6  of the second pumping capacitor C 3  (as shown in  FIG. 2 ). Furthermore, those skilled in this art will readily understand that more than two output voltages can also be generated through appropriate modifications upon the method  400  by only utilizing one charging capacitor. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.