Abstract:
A one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. The SRAM circuit includes first and second flip-flop circuits which are connected in parallel to a common write word line; a first write control circuit which is connected to said first flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a first write signal to said first flip-flop circuit; and a second write control circuit which is connected to said second flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a second write signal to said second flip-flop circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application of U.S. application Ser. No. 12/213,974 filed Jun. 26, 2008, now allowed, which is a continuation of International Application No. PCT/JP2005/23917, filed on Dec. 27, 2005, now pending, herein incorporated by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to a memory device using an SRAM circuit composed of Metal Oxide Semiconductor (hereafter MOS) transistors, of which data transfer speed or input data width and output data width are different, and a buffer circuit using this SRAM circuit, and more particularly to a downsizing and increasing speed of the memory device. 
       BACKGROUND OF THE INVENTION 
       [0003]    A conventional SRAM (Static Random Access Memory) circuit has a one read/write circuit, in which a read port and a write port are in common. In this case, a port refers to an input/output interface for reading or writing data, a register for storing an address, a decoder for decoding an address, and a bit line and a word line to specify a position of an address. In the case of the one read/write circuit, reading and writing cannot be executed simultaneously. Also when data is read or written, an address position of reading or writing is determined using a common address decoder. Therefore the number of bits of an address used for reading and writing are the same. 
         [0004]    On the other hand, an SRAM circuit having a plurality of ports has been proposed (e.g. see Non-patent Document 1). 
         [0005]    A one read/two write SRAM circuit, which is an example of an SRAM circuit having a plurality of discrete ports, has one read port and two write ports. In this circuit, one address decoder for reading and two address decoders for writing are provided. 
         [0006]      FIG. 7  is a diagram depicting a configuration of a conventional one read/two write SRAM circuit. 
         [0007]    When reading data, a read address to indicate a read address position is first stored in a read address register RAR. The stored read address is supplied to a read column decoder RCDC and a read row decoder RRDC. The read column decoder RCDC and the read row decoder RRDC specify a row and a column of a read address position in a memory array  300  respectively. The data of the memory cell at the specified address position is output via an OR circuit  400 . 
         [0008]    When writing data to the one read/two write SRAM circuit, the two write addresses to indicate the two write positions respectively are stored in write address registers WAR 1  and WAR 2 . The write address stored in the write address register WAR 1  is stored in a write column decoder WCDC 1  and write row decoder WRDC 1 . The write address stored in the write address register WAR 2  is supplied to a write column decoder WCDC 2  and write row decoder WRDC 2 . The two write column decoders and the two write row decoders specify the column and row at a write position on the memory array  300  respectively. To the two memory cells at the specified positions, the write data stored in the write data registers WDR 1  and WDR 2  are written via the write column decoders WCDC 1  and WCDC 2 . 
         [0009]      FIG. 8  is a diagram depicting a configuration of an SRAM cell used for a conventional one read/two write SRAM circuit. The conventional one read/two write SRAM cell comprises P-channel MOS transistors, N-channel MOS transistors, bit lines and word lines. 
         [0010]    A P-channel MOS transistor  101  and an N-channel MOS transistor  102  are connected between the same two nodes, and constitute an inverter circuit. In the same way, a P-channel MOS transistor  103  and an N-channel MOS transistor  104  are connected between the same two nodes, and constitute an inverter circuit. A flip-flop circuit comprises of these four transistors using a loop of two inverter circuits, where one bit information is held. 
         [0011]    An N-channel MOS transistor  105 , the gate of which is connected to a read word lines +RWL, connects a read bit line +RBL and the node at the gate side of the transistors  101  and  102  constituting the inverter circuit. An N-channel MOS transistor  106 , the gate of which is connected to a write word line +WWL 0 , connects a write bit line +WBL 0  to the node at the gate side of the transistors  101  and  102  constituting the inverter circuit. An N-channel MOS transistor  107 , the gate of which is connected to a write word line +WWL 1 , connects a write bit line +WBL 1  to the node at the gate side of the transistors  101  and  102  constituting the inverter circuit. 
         [0012]    An N-channel MOS transistor  108 , of which gate is connected to the read word line +RWL, connects a read bit line −RBL to the node at the gate side of the transistors  103  and  104  constituting the inverter circuit. An N-channel MOS transistor  109 , the gate of which is connected to a write word line −WWL 0 , connects a write bit line −WBL 0  to the node at the gate side of the transistors  103  and  104  constituting the inverter circuit. An N-channel MOS transistor  110 , the gate of which is connected to the write word line +WWL 1 , connects a write bit line −WBL 1  to the node at the gate side of the transistors  103  and  104  constituting the inverter circuit. 
         [0013]    When data is written to this SRAM cell, the write word line +WWL 0 , specified by the write row decoder WRDC 1 , is set to High state (hereafter H). By this, the N-channel MOS transistors  106  and  109  turn ON. Then the target data stored in the write data register WDR 1  is input by the write column decoder WCDC 1  via the specified write bit line +WBL 0 . At the same time, the opposite state of the write bit line +WBL 0  is input via the write bit line −WBL 0 . 
         [0014]    If the data to be stored is H, the N-channel MOS transistor  102  and the P-channel MOS transistor  103  turn ON, the node at the gate side of the transistors  101  and  102  constituting the inverter circuit is fixed to H, and the node at the gate side of the transistors  103  and  104  constituting the inverter circuit are fixed to Low state (hereafter L). 
         [0015]    Data can be simultaneously written to this SRAM cell using a port of another system. In this case, the word line +WWL 1  specified by the write row decoder WRDC 2  is set to H. By this, the N-channel MOS transistors  107  and  110  turn ON. Then the target data to be stored in the write data register WDR 2  is input by the write column decoder WCDC 2  via the specified bit line +WBL 1 . At the same time, the opposite state of the bit line +WBL 1  is input via the bit line −WBL 1 . 
         [0016]    If the data to be stored is L, the N-channel MOS transistor  104  and the P-channel MOS transistor  101  turn ON, the node at the gate side of the transistors  101  and  102  constituting the inverter circuit is fixed to L, and the node at the gate side of the transistors  103  and  104  constituting the inverter circuit are fixed to H. By simultaneously writing data to different cells using the two systems, the write speed can be increased. In this case, hardware to prohibit the two systems from simultaneously writing a same position is necessary. 
         [0017]    When data is read from this SRAM cell, the read word line +RWL selected as a result of decoding by the read row decoder RRDC is set to H. By this, the N-channel MOS transistors  105  and  108  turn ON. Then the data stored at the gate side of the transistors  101  and  102  constituting the inverter circuit, which is a part of the loop of the flip-flop circuit, is output from the read bit line +RBL specified by the read column decoder RCDC. At the same time, the opposite state of the read bit line +RBL is output from the read bit line −RBL by the inverter circuit inverting the state of the read bit line +RBL. 
         [0018]    In the case of this one read/two write SRAM circuit, the number of write ports is double the number of read ports, so the data width is different between the data to be input and the data to be output. By simultaneously writing different cells using two systems, the data write speed can be virtually increased to double, and [the SRAM circuit] is used as a buffer circuit of which data write speed and data read speed are different. 
         [0019]      FIG. 9  is a diagram depicting an example of using the one read/two write SRAM circuit. A central processing unit (hereafter CPU)  100  outputs the data D 1  acquired by computation to a one read/two write SRAM circuit  101   a.  For fast computation, the CPU  100  is demanded to immediately output the acquired data and start another computation. 
         [0020]    Hence the one read/two write SRAM circuit  101   a  receives the data using the two write ports, and outputs the data D 2  via one read port. Since the number of read ports is ½ the number of write ports, the virtual transfer speed required for reading the data D 2  becomes ½ the transfer speed required for writing the data D 1 . 
         [0021]    A one read/two write SRAM circuit  101   b  receives the data D 2 , which is an output of the one read/two write SRAM circuit  101   a,  and write the data using two write ports. The written data D 2  is read by one read port, and is output as data D 3 . Since the number of read ports is ½ the number of write ports, the virtual transfer speed required for reading the data D 3  becomes ½ the transfer speed required for writing the data D 2 . As a result, the transfer speed required for reading the data D 3  becomes one fourth the transfer speed required for writing the data D 1 . 
         [0022]    In this way, the data, which is output from the CPU, gradually decreases the transfer speed. Since the data D 1 , which is output from the CPU, is not output very frequently, the speed may drop after the processing to receive the data D 1  is executed as fast as possible. This way the CPU can perform a kind of release processing, that is, outputting data without waiting for an end of slow processing of the memory circuit in subsequent stages of the data D 3 . 
         [0023]    Non-patent Document 1: “Niel H. El Weste, Kamran Eshraghi, “Principle of CMOS VLSI design from a system point of view”, issued by Maruzen Co., Ltd, pp. 310, 1988 
         [0024]    However in the case of a conventional one read/two write SRAM circuit, which writes data at double speed by providing two write ports, one read address register and two write address registers are required. In the same way, one read address decoder and two write address decoders are required. Since these circuits are installed to be redundant, decreasing the size of a conventional one read/two write SRAM circuit is difficult. 
         [0025]    Also in the one read/two write SRAM circuit, many word lines and transistors are used, which increases the memory cell size. Therefore the bit lines and the word lines become long, and resistance and wiring capacity increase. If resistance and wiring capacity increase, the drive current for driving the transistors decreases (since an increase in wiring capacity increases the load to be driven by the transistors), and it is difficult to increase the speed of the one read/two write SRAM circuit. 
       SUMMARY OF THE INVENTION 
       [0026]    With the foregoing in view, it is an object of the present invention to provide a one read/two write SRAM circuit of which memory cell size is small. 
         [0027]    It is another object of the present invention to provide a one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. 
         [0028]    It is still another object of the present invention to provide a buffer circuit using an SRAM circuit of which memory cell size is small. 
         [0029]    It is still another object of the present invention to provide a buffer circuit using an SRAM circuit of which memory cell size is small, and high-speed operation is possible. 
         [0030]    To solve the above problems, an SRAM circuit according to a first aspect of the present invention has: a plurality of memory cells composed of a pair of storage units respectively; a plurality of write word lines for specifying rows of the plurality of memory cells; a plurality of read word line pairs for specifying rows of the plurality of memory cells; a write row decoder for driving the write word line, which is common to the pair of storage units, when data is written to the pair of storage units; a read row decoder for driving the read word line, which is connected to the storage unit, when data is read from the storage unit; a plurality of write bit line pairs for specifying the pair of storage units when data is written to the pair of storage units, and writing data to be input to both of the pair of storage units, which are commonly specified by the write word lines, respectively; and (one or more, the same in the following description) read bit lines for specifying the storage unit when data is read from the storage unit and reading data from the storage unit, which is commonly specified by the read word lines. 
         [0031]    It is preferable that the first aspect of the present invention further has a write column decoder, characterized in that the write column decoder selects a write bit line to which [data] is written out of the write bit line pairs based on the least high-order bit of a write address to be input. 
         [0032]    In the first aspect of the present invention, it is preferable that the read row decoder selects a read word line from which [data] is read out of the read word line pairs based on the least high-order bit of a read address to be input. 
         [0033]    In the first aspect of the present invention, it is preferable that the write column decoder simultaneously drives the pair of write bit lines, and simultaneously writes data to the pair of storage units. 
         [0034]    It is preferable that the first aspect of the present invention further has a first and a second write transistors, and in the first write transistor, the write word line is connected to the gate side, and one of the write bit line pairs and one of the pair of storage units are connected based on the supply of a signal to the gate, and in the second write transistor, the write word line is connected to the gate side and the other of the write bit line pair and the other of the pair of storage units are connected based on the supply of a signal to the gate. 
         [0035]    It is preferable that the first aspect of the present invention further has a first and second read transistors, and in the first read transistor, one of the read word line pair is connected to the gate side, and the read bit line and one of the pair of storage units are connected based on the supply of a signal to the gate, and in the second read transistor, the other of the read word line pair is connected to the gate side, and the read bit line and the other of the pair of storage units are connected based on the supply of a signal to the gate. 
         [0036]    In the first aspect of the present invention, it is preferable that when [data] is written to the pair of storage units, all of the memory cells specified by the write word lines are specified by the write bit line pairs, and [the data] is simultaneously written to all of the pairs of storage units which are specified. 
         [0037]    In the first aspect of the present invention, it is preferable that when [data] is read from the storage unit, all of the memory cells specified by the read word lines are specified by the read bit lines, and [the data] is simultaneously read from all the storage units which are specified. 
         [0038]    A buffer circuit according to a second aspect of the present invention has a plurality of SRAM circuits, each of which has: a plurality of memory cells further having a pair of storage units respectively; a plurality of write word lines for specifying rows of the plurality of memory cells; a plurality of read word line pairs for specifying rows of the plurality of memory cells; a write row decoder for driving the write word line common to the pair of storage units when [data] is written to the pair of storage units; a read row decoder for driving the read word line which is connected to the storage unit when [data] is read from the storage unit; a plurality of write bit line pairs for specifying the pair of storage units when [data] is written to the pair of storage units, and writing data to be input to both of the pair of storage units which are commonly specified by the write word lines respectively; and a plurality of read bit lines for specifying the storage unit when [data] is read from the storage unit and reading data from the storage unit which is commonly specified by the read word lines, characterized in that the read bit line of the SRAM circuit and one of the write bit line pairs of another SRAM circuit are inter-connected. 
         [0039]    The SRAM circuit of the present invention can implement a higher processing speed and a smaller memory size by accessing 2-bit information using common write word lines. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0040]      FIG. 1  is a diagram depicting a configuration of an SRAM cell to which the present embodiment is applied; 
           [0041]      FIG. 2  is a diagram depicting a configuration of an SRAM circuit according to a first embodiment of the present embodiment; 
           [0042]      FIG. 3  is a diagram depicting an example when the SRAM of the present embodiment is applied to a buffer circuit; 
           [0043]      FIG. 4  is a diagram depicting a configuration of a register  102  for holding the computation result of CPU  100 ; 
           [0044]      FIG. 5  is a diagram depicting the SRAM circuit of the present embodiment which is applied to the buffer circuit; 
           [0045]      FIG. 6  is a diagram depicting the SRAM circuit  101   b  of the present embodiment which is applied to the buffer circuit; 
           [0046]      FIG. 7  is a diagram depicting a configuration of a conventional one read/two write SRAM circuit; 
           [0047]      FIG. 8  is a diagram depicting a configuration of an SRAM cell which is used for a conventional one read/two write SRAM circuit; and 
           [0048]      FIG. 9  is a diagram depicting an example of using the one read/two write SRAM circuit. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0049]    Embodiments of the SRAM circuit will now be described with reference to the drawings. The technical scope of the SRAM circuit, however, is not limited to these embodiments, but extend to the contents of the Claims and equivalents thereof. 
         [0050]      FIG. 1  is a diagram depicting a configuration of an SRAM to which an embodiment of the SRAM circuit is applied. The SRAM of the present embodiment has a pair of storage units  219  and  220  for storing 1 bit, and 4 P-channel MOS transistors and 12 N-channel MOS transistors. The pair of storage units included in the SRAM cell are accessed via 6-bit lines and 3 word lines. While one port is used for reading, two ports are used for writing. 
         [0051]    The P-channel MOS transistor  201  and the N-channel MOS transistor  202  are connected between the same two nodes. In the same way, the transistors  203  and  204 ,  211  and  212  and  213  and  214  are connected between the same two nodes. Since the pair of storage units  219  and  220  are constructed by these 8 transistors, 2-bit information can be stored in the SRAM cell in  FIG. 1 . 
         [0052]    An N-channel MOS transistor  205 , the gate of which is connected to a read word line +RWL 1 , connects a read bit line +RBL to a node at the gate side of the transistors  201  and  202  which constitute an inverter circuit. In the same way, an N-channel MOS transistor  207 , the gate of which is connected to the read word line +RWL 1 , connects a read bit line −RBL and a node at the gate side of the transistors  203  and  204  which constitute an inverter circuit. An N-channel MOS transistor  216 , the gate of which is connected to a read word line +RWL 0 , connects the read bit line +RBL to a node at the gate side of the transistors  211  and  212  which constitute an inverter circuit. In the same way, an N-channel MOS transistor  218 , the gate of which is connected to the read word line +RWL 0 , connects the read bit line −RBL to a node at the gate side of the transistors  213  and  214  which constitute an inverter circuit. N-channel MOS transistors  206 ,  208 ,  216  and  218 , the gate of which are connected to a write word line +WWL, are connected to the write bit lines +WBL 1 , −WBL 1 , +WBL 0  and −WBL 0  respectively. 
         [0053]    To write data to this SRAM cell, the write word line +WWL is set to H first. By this, the N-channel MOS transistors  206 ,  208 ,  215  and  217  turn ON. Then the data to be stored is input from write bit lines +WBL 0  and +WBL 1 . At the same time, a reversed state of the write bit line +WBL 0  is input from the write bit line −WBL 0 , and a reversed state of the write bit line +WBL 1  is input from the write bit line −WBL 1 . 
         [0054]    The data which is input from the write bit line +WBL 1  via the N-channel MOS transistor  206  is held at the gate side of the transistors  201  and  202  constituting the inverter circuit. The data which is input from the write bit line +WBL 0  via the N-channel MOS transistor  215  is held at the gate side of the transistors  211  and  212  constituting the inverter circuit. 
         [0055]    If the data to be stored in the node at the gate side of the transistors  201  and  202  constituting the inverter circuit is H, the N-channel MOS transistor  202  and the P-channel MOS transistor  203  turn ON, the node at the gate side of the transistors  201  and  202  constituting the inverter circuit is fixed to H, and the node at the gate side of the transistors  203  and  204  constituting the inverter circuit is fixed to L. 
         [0056]    Simultaneously with storing data in the node at the gate side of the transistors  201  and  202  constituting the inverter circuit, [data] can be written to the node at the gate side of the transistors  211  and  212  constituting the inverter circuit, using a port of another system. In this case, at a timing when the write word line +WWL becomes H, the data to be stored is input from the write bit line +WBL 0 . If the data to be stored in the node at the gate side of the transistors  211  and  212  constituting the inverter circuit is L, the N-channel MOS transistor  214  and the P-channel MOS transistors  211  turn ON, the node at the gate side of the transistors  211  and  212  constituting the inverter circuit is fixed to L, and the node at the gate side of the transistors  213  and  214  constituting the inverter circuit is fixed to H. 
         [0057]    To read data from this SRAM cell, the read word line +RWL 1  is set to H first. By this, the N-channel MOS transistors  205  and  207  turn ON. Then the data stored in the node at the gate side of the transistors  201  and  202  constituting the inverter circuit is output from the read bit line +RBL. At the same time, an opposite state of the read bit line +RBL is output from the read bit line −RBL. 
         [0058]    Then the read word line +RWL 0  is set to H. By this, the N-channel MOS transistors  216  and  218  turn ON. Then the data stored in the node at the gate side of the transistors  211  and  212  constituting the inverter circuit is output from the read bit line +RBL. At the same time, an opposite state of the read bit line +RBL is output from the read bit line −RBL. 
         [0059]    The SRAM cell of the present embodiment shown in  FIG. 1  holds information double that of the conventional SRAM cell shown in  FIG. 8 . This is because the conventional SRAM cell shown in  FIG. 8  comprises 10 transistors, 3 word lines and 6 bit lines, whereas the SRAM cell of the present embodiment comprises 16 transistors, 3 word lines and 6 bit lines. Since the SRAM cell of the present embodiment holds information double the conventional circuit, [the SRAM circuit] can save 4 transistors, 3 word lines and 6 bit lines compared with the conventional SRAM cell comprising 20 transistors, 6 word lines and 12 bit lines, if comparison is performed in the capacity in 2-bit units. Therefore compared with the prior art, the SRAM circuit can decrease the physical volume, such as transistors and word lines, per unit storage capacity. 
         [0060]    By this decrease of transistors, word lines and bit lines, the SRAM circuit size can be decreased. By decreasing the size of the SRAM circuit due to the decrease of physical volume per unit storage capacity, the line lengths of the word lines and bit lines are decreased, and the resistance values of the word lines and bit lines are also decreased, hence the drive current for driving the transistors can be decreased. By the increase of the drive current, operation of the transistors becomes faster, and the SRAM circuit itself can be faster. 
         [0061]      FIG. 2  is a diagram depicting a configuration of an SRAM circuit according to a first embodiment of the SRAM circuit. 
         [0062]    To read data from a memory cell array  200  comprising the SRAM cell of the SRAM circuit, a bit string to indicate a read address is stored in a read address register RAR. Based on low-order bits of the stored bit string, excluding the least high-order bit (column address), a read column decoder RCDC drives a corresponding read bit line. At the same time, based on the high-order bits (row address) and the least high-order bit (selection bit)  221  of the stored bit string, a read row decoder RRDC drives a corresponding read word line. The least high-order bit  221  is a selection bit which is used for determining which one of the read word lines +RWL 1  and +RWL 0  in  FIG. 1  is driven. If the least high-order bit is 0 (in the case of an even address), the read word lines +RWL 0  is driven, and if the least high-order bit  1  (in the case of an odd address), the read word line +RWL 1  is driven. 
         [0063]    By driving an appropriate word line and appropriate bit lines, the transistor  205  and  207  or  216  and  218  in  FIG. 1  are turned ON, and the desired memory cell can be accessed to read the stored data. The data in the memory array  200  accessed based on the bit string stored in the read address register RAR is output by determining OR of all the bit lines connected to the memory array  200  (OR logic operation). 
         [0064]    To write data to the memory cell array  200  comprising the SRAM cell of the SRAM circuit, a bit string to indicate a write address is stored in a write address register WAR. If the number of bits of the address used for reading is N at this time, then the number of bits of the address used for writing is N−1. Because data for the case when the selection bit, which is the least high-order bit, of the address used for reading is 1 (in the case of an odd address) and the case when this bit is 0 (in the case of an even address) can be stored in a same cell, data for the odd address and data for the even address are simultaneously written to the same cell. 
         [0065]    When N−1 bits of a bit string to indicate a write address, excluding the selection bit which corresponds to the least high-order bit, is stored in the write address register WAR, the write column decoder WCDC decodes this column address based on the low-order bits (column address) of the stored bit string, and drives the write bit line. Based on the high-order bits (row address) of the stored bit string, the write row decoder WRDC decodes the row address, and drives the write word line +WWL. When the bit line is driven, AND of the data WD 0  of which least high-order bit of the write position address is 0 (even address) and data WD 1  of which least high-order bit of the write position address is 1 (odd address) with the signals to drive the write bit lines +WBL 0  and +WBL 1  in  FIG. 1  are determined (AND logic operation), and the results are written in the cell. For example, a case of simultaneously writing data WD 0  and data WD 1  to an even address and an odd address in the SRAM cell in  FIG. 1  according to the present embodiment will be described. To write data to this SRAM cell, the write word line +WWL is set to H first. By this, the N-channel transistors  206 ,  208 ,  215  and  217  turn ON. Then data WD 0  is input from the write bit line +WBL 0  which corresponds to the even address, and data WD 1  is input from the write bit line +WBL 1  which corresponds to the odd address. If data WD 0  is 0 here, then 0, which is a result of AND of this value with the value 1 of the signal for driving the write bit line +WBL 0  (AND logic operation), is input from +WBL 0 , and if data WD 0  is 1, then 1, which is a result of AND of this value with the value 1 of the signal for driving the write bit line +WBL 0  (AND logic operation), is input from +WBL 0 . In the same way, if data WD 1  is 0, then 0, which is the result of AND of this value with the value 1 of the signal for driving the write bit line +WBL 1  (AND logic operation), is input from +WBL 1 , and if data WD 1  is 1, then 1, which is the result of AND of this value with the value 1 of the signal for driving the write bit line +WBL 1  (AND logic operation), is input from the +WBL 1 . At the same time, a reversed state of the write bit line +WBL 0  is input from the write bit line −WBL 0 , and an opposite state of the write bit line +WBL 1  is input from the write bit line −WBL 1 . 
         [0066]    The data which is input from the write bit line +WBL 1  via the N-channel MOS transistor  206  is held at the gate side of the transistors  201  and  202  constituting the inverter circuit. The data which is input from the write bit line +WBL 0  via the N-channel MOS transistor  215  is held at the gate side of the transistors  211  and  212  constituting the inverter circuit. 
         [0067]    In the conventional one read/two write SRAM circuit, the two write address registers WAR, the two write column decoders WCDC, the two write row decoders WRDC and the two write data registers WDR are required, but in the SRAM circuit of the present embodiment which has the above configuration, the number of these elements can be one each. The write column decoder WCDC can be smaller and faster, since the least high-order bit, which corresponds to the selection bit to select either the even address or the odd address, is unnecessary. In this way, the SRAM circuit can be downsized by simplifying the peripheral circuits of the memory array. 
         [0068]    Also in the conventional one read/two write SRAM circuit, which has two write systems, hardware for exclusive control to prohibit the two systems from writing a same position is required. But in the SRAM circuit of the SRAM circuit, where simultaneously writing data at a same position does not occur, this hardware for exclusive control can be omitted, and downsizing is possible. 
         [0069]    Now a second embodiment of the SRAM circuit will be described. 
         [0070]      FIG. 3  shows an example when the SRAM circuit is applied to a buffer circuit. The operation result of a CPU  100  is stored in a register  102 . Here the register  102  has a 64-bit data length, and virtually includes a high-order bit section  102   x  for storing high-order 32-bit data and a low-order bit section  102   y  for storing low-order 32-bit data. 
         [0071]    The data temporarily held in the register  102  must be stored in a buffer circuit  101   a  immediately for the CPU  100  to start the next operation. 
         [0072]    The data width of the SRAM circuit  101   a  of the present embodiment, which is used as a buffer circuit, has a 32-bit length, but since 2-bit information can be stored in one cell in the circuit configuration of the present embodiment, writing can be performed simultaneously from two systems, that is, high-order bit section  102   x  and low-order bit section  102   y,  of the register  102 . 
         [0073]    In order to simultaneously specify an address  1  section  101   a _ 1   x  which corresponds to an odd address of the SRAM circuit  101   a  and an address  0  section  101   a _ 1   y  which corresponds to an even address, a write row decoder WRDCa drives a write word line WLa_ 1  which exists between [the address  1  section and address  0  section]. The 32-bit long data of the high-order bit section  102   x  of the register  102  is written to the address  1  section  101   a _ 1   x  of the SRAM circuit  101   a.  The 32-bit long data of the low-order bit section  102   y  of the register  102  is written to the address  0  section  101   a _ 1   y  of the SRAM circuit  101   a.    
         [0074]    Now how the register  102  and the SRAM circuit  101   a  are connected so as to perform the above mentioned simultaneous write operation to the address  1  section corresponding to the odd address and the address  0  section corresponding to the even address of the SRAM circuit will be described. 
         [0075]      FIG. 4  is a diagram depicting an internal configuration of the register  102  for holding the operation result of the CPU  100 .  FIG. 5  shows the SRAM circuit  101   a  of the present embodiment, which is applied to a buffer circuit. As  FIG. 1  shows, the register  102  comprises 64 flip-flops F 00  to F 63 , which are constructed by loops of inverter circuits where P-channel MOS transistors ( 202 ,  204 ,  212  and  214  in  FIG. 1 ) and N-channel MOS transistors ( 201 ,  203 ,  211  and  213  in  FIG. 1 ) are connected between the same two nodes. Out of the 64 flip-flops F 00  to F 63 , the flip-flops F 0  to F 31  are assigned to the high-order bit section  102   x  of the register  102 , and the flip-flops F 32  to F 63  are assigned to the low-order bit sections  102   y  of the register  102 . To each of the 64 flip-flops, a clear signal for resetting the content held by the flip-flop, and a clock signal CLK for driving the flip-flop, are input. To the 64 flip-flops from F 00  to F 63 , the bits D 0  to D 63  which are the operation result of the CPU  100  are connected as data input. 
         [0076]    The flip-flops F 00  to F 63  output the data which is input from the bits D 0  to D 63  as output signals OUT 0  to OUT 63 , until the clear signal CR is input. In other words, the operation result of the CPU  100  is held in the register  102  until the clear signal CR is input. 
         [0077]    The output signals OUT 0  to OUT 63  from the register  102  are input to the write bit lines +WBL 0  and +WBL 1  of the SRAM circuit  101   a  of the present embodiment, constituting the flip-flops CL 00  to CL 31  respectively in  FIG. 5 . The reverse signals of the output signals OUT 0  to OUT 63  from the register  102  are input to the write bit lines −WBL 0  and −WBL 1  of the SRAM circuit  101   a  of the present embodiment, constituting the flip-flops CL 00  to CL 31  respectively in  FIG. 5 . 
         [0078]    More specifically, output signals OUT 0  to OUT 31  of the flip-flop F 00  to F 31 , which is a high-order bit section  102   x  of the register  102 , are input to the write bit lines +WBL 1 _ 00  to +WBL 1 _ 31  in  FIG. 5  respectively. The reverse signals of the output signals OUT 0  to OUT 31  from the flip-flop F 00  are input to the write bit lines −WBL 1 _ 00  to −WBL 1 _ 31  in  FIG. 5  in the same manner. 
         [0079]    The output signals OUT 32  to OUT 63  from the flip-flop F 32  to F 63 , which is a low-order bit section  102   y  of the register  102 , are input to the write bit lines +WBL 0 _ 00  to +WBL 0 _ 31  in  FIG. 5 . The reverse signals of the output signals OUT 32  to OUT 63  from the flip-flops F 32  to F 63  are input to the write bit lines −WBL 0 _ 00  to −WBL 0 _ 31  in  FIG. 5  in the same manner. 
         [0080]    Simultaneously with the above mentioned input of data to the write bit line, the write row decoder WRDCa in  FIG. 3  drives the word line +WWL in  FIG. 5  based on the row address decoding result. The signals which were input to the memory cells CL 00  to CL 31  specified by the word line +WWL via the write bit lines +WBL 1 _ 00  to +WBL 1 _ 31  are stored in the corresponding address  1  section  101   a _ 1   x  if the write address is an odd address, and the signals which were input from the write bit lines +WBL 0 _ 00  to +WBL 0 _ 31  are stored in the corresponding address  0  section  101   a _ 1   y  if the write address is an even address. 
         [0081]    Now the case of reading data from the SRAM circuit  101   a  in  FIG. 3  and writing the data to the SRAM circuit  101   b  will be described. 
         [0082]    First the read row decoder RRDCa in  FIG. 3  specifies a row from which data is read in the SRAM circuit  101   a,  based on the row address decoding result. In the case of  FIG. 3 , a row is selected from the four rows:  101   a _ 1   x,    101   a _ 1   y,    101   a _ 2   x  and  101   a _ 2   y.  Here it is assumed that the read word line +RWL corresponding to the address  1  section  101   a _ 1   x,  which is an odd address, is driven in  FIG. 5 . And the write row decoder WRDCb selects a row in the SRAM circuit  101   b  to which data is written. Here it is assumed that the address  1  section  101   b _ 1   x  and address  0  section  101   b _ 1   y  of the SRAM circuit  101   b  are simultaneously specified, and for this, the write word line +WWL which exists there between in  FIG. 5  is driven. 
         [0083]    The 16-bit long high-order data of the address  1  section  101   a _ 1   x,  which is an odd address in the SRAM circuit  101   a,  is written to the address  1  section  101   b _ 1   x,  which is an odd address in the SRAM circuit  101   b.  The 16-bit long low-order data of the address  1  section  101   a _ 1   x,  which is an odd address in the SRAM circuit  101   a,  is written to the address  0  section  101   b _ 1   y,  which is an even address in the SRAM circuit  101   b.    
         [0084]    Now how the SRAM circuits  101   a  and  101   b  are connected to perform the above mentioned operation will be described. 
         [0085]      FIG. 6  is the SRAM circuit  101   b  which is applied to the buffer circuit. Data output from the read bit lines +RBL_ 00  to +RBL_ 31  in the SRAM circuit  101   a  in  FIG. 5  is input to the write bit lines +WBL 1 _ 00  to WBL 1 _ 15  and +WBL 0 _ 00  to +WBL 0 _ 15  in  FIG. 6  respectively. 
         [0086]    More specifically, the read bit lines +RBL_ 00  to +RBL_ 15  for outputting 16-bit long high-order data of the address data, which is an output from the SRAM circuit  101   a  in  FIG. 3 , are input to the write bit lines +WBL 1 _ 00  to WBL 1 _ 15  in  FIG. 6 . And the read bit lines +RBL_ 16  to +RBL_ 31 , for outputting 16-bit long low-order data, which is an output from the SRAM circuit  101   a  in  FIG. 3 , are input to the write bit lines +WBL 0 _ 00  to +WBL 0 _ 15  in  FIG. 6 . 
         [0087]    The read bit lines −RBL_ 00  to −RBL_ 15 , for outputting reverse signals of the 16-bit long high-order data of the address data, which is an output from the SRAM circuit  101   a  in  FIG. 3 , are input to the write bit lines WBL 1 _ 00  to −WBL 1 _ 15  in  FIG. 6 . And the read bit lines −RBL_ 16  to −RBL_ 31 , for outputting the reverse signals of the 16-bit long low-order data, which is an output from the SRAM circuit  101   a  in  FIG. 3 , are input to the write bit lines −WBL 0 _ 00  to −WBL 0 _ 15  in  FIG. 6 . 
         [0088]    At the same time, with the input of the data to the write bit lines, the write row decoder WRDCb in  FIG. 3  drives the word line +WWL in  FIG. 6  based on the row address decoding result. The signals which were input from the write bit lines +WBL 1 _ 00  to WBL 1 _ 15  to the memory cells CL 00  to CL 15  specified by the word line +WWL are stored in the corresponding address  1  section  101   b _ 1   x  if the write address is an odd address, and the signals which were input from the write bit lines +WBL 0 _ 00  to +WBL 0 _ 15  are stored in the corresponding address  0  section  101   b _ 1   y  if the write address is an even address. 
         [0089]    As described above, the buffer circuit described above comprises memory cells using the SRAM circuit of the present embodiment, so the circuit size can be decreased by decreasing such elements as the transistors and word lines. 
         [0090]    By this downsizing, the word lines and bit lines become shorter, and resistance values of the word lines and bit lines also decrease, therefore the drive current for driving the transistors can be increased. If the drive current increases, the transistor operation can be faster, and speed of the SRAM circuit itself can be increased. 
         [0091]    Also omitting one write row decoder, out of the two write row decoders which have conventionally been required, can decrease the size of the SRAM circuit.