Abstract:
A charge-coupled device image sensor comprises a matrix array of photodiodes and a horizontal charge-coupled device (CCD). First vertical CCDs are provided, each on one side of each column of the photodiodes for receiving charge packets from the photodiodes of odd-numbered rows and moving the charge packets to the horizontal CCD and second vertical CCDs are provided, each on the other side of each column of the photodiodes for receiving charge packets from the photodiodes of even-numbered rows and moving the charge packets to the horizontal CCD. The horizontal CCD receives the charge packets from the first and second vertical CCDs and transfers the received charge packets to external circuitry. According to a modified embodiment, a second horizontal CCD is provided for receiving the charge packets from the second vertical CCDs.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to image sensing devices, and more specifically to a two-dimensional charge-coupled device (CCD) image sensor of the progressive scan format. 
     2. Description of the Related Art 
     The use of input devices such as digital still cameras for personal computers requires scan conversion from the interlace format to the noninterlace (progressive) format since most of these input devices are implemented with components used in the standard television systems, whereas the display system of computers is implemented with the progressive format. In order to eliminate the need for the scan conversion, the progressive scan format is increasingly adopted by current CCD (charge-coupled device) image sensors. 
     To implement the progressive scanning in an interline CCD image sensor, three-phase clock pulses must be used to transfer charge packets of two-dimensional image along vertical charge transfer means or CCDs to a horizontal CCD. However, one disadvantage of the three-phase transfer mode is that polysilicon electrodes must be arranged in a three-layered structure since it involves an added manufacturing step as compared with the two-layered structure of the transfer mode employed in the interlace scanning. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a charge-coupled device image sensor which can be implemented with a two-layered electrode structure. 
     According to a first aspect of the present invention, there is provided a charge-coupled device image sensor which comprises a plurality of photodiodes arranged in a matrix array of columns and rows and a horizontal charge transfer means, or horizontal CCD. A plurality of first vertical charge transfer means, or first vertical CCDs are provided. Each of the first vertical CCDs is arranged on one side of each column of the photodiodes for receiving charge packets from the photodiodes of odd-numbered rows and moving the charge packets to the horizontal CCD. A plurality of second vertical charge transfer means, or second vertical CCDs are provided, each being arranged on the other side of each column of the photodiodes for receiving charge packets from the photodiodes of even-numbered rows and moving the charge packets to the horizontal CCD. The horizontal CCD receives the charge packets from the first and second vertical CCDs and transfers the received charge packets to external circuitry. 
     According to a second aspect, the present invention provides a charge-coupled device image sensor comprising a plurality of photodiodes arranged in a matrix array of columns and rows. First and second horizontal CCDs are provided. Each of a plurality of first vertical CCDs is arranged on one side of each column of the photodiodes for receiving charge packets from the photodiodes of odd-numbered rows and moving the charge packets to the first horizontal CCD. Each of a plurality of second vertical CCDs is arranged on the other side of each column of the photodiodes for receiving charge packets from the photodiodes of even-numbered rows and moving the charge packets to the second horizontal CCD. The first horizontal CCD receives the charge packets from the first vertical CCDs and transfers the received charge packets to external circuitry, and the second horizontal CCD receives the charge packets from the second vertical CCDs and moves the received charge packets to the external circuitry. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described in further detail with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a CCD image sensor according to a first embodiment of the present invention; 
     FIG. 2 is an enlarged plan view of a portion of the image sensor of FIG. 1; 
     FIG. 3 is a cross-sectional view taken along the lines 3--3 of FIG. 2; 
     FIG. 4 is a timing diagram associated with the first embodiment of the invention; 
     FIG. 5 is a potential diagram showing charge packets successively transferred as a result of the application of the clock pulses of FIG. 4; 
     FIG. 6 is a block diagram of a CCD image sensor according to a second embodiment of the present invention; 
     FIG. 7 is an enlarged plan view of a portion of the image sensor of FIG. 6; 
     FIGS. 8A and 8B are cross-sectional views taken along the lines 8A--8A and 8B--8B of FIG. 7, respectively; 
     FIG. 9 is a timing diagram associated with the second embodiment of the invention; and 
     FIGS. 10A and 10B are potential diagrams showing charge packets successively transferred as a result of the application of the clock pulses of FIGS. 9. 
    
    
     DETAILED DESCRIPTION 
     Referring now to FIG. 1, a progressive-scan two-dimensional CCD image sensor according to a first embodiment of the present invention has a matrix array of photodiodes 1 and a plurality of vertical CCDs 2 which are divided into left-side vertical CCDs 2L and right-side vertical CCDs 2R. Each vertical CCD has a plurality of stages each having a set of four partially overlapping electrodes G 1 , G 2 , G 3  and G 4 . The electrodes G 1 , G 2 , G 3  and G 4  of all vertical CCDs are respectively connected together to receive four-phases voltage clock pulses via terminals φ 1 , φ 2 , φ 3  and φ 4 , respectively. Each stage of the vertical CCDs 2L is associated with a corresponding photodiode of odd-numbered row, and each stage of the vertical CCD 2R is associated with a corresponding photodiode of even-numbered row. A transfer gate 3L connects each odd-numbered photodiode to the associated vertical channel 2L and a transfer gate 3R connects each even-numbered photodiode to the associated vertical channel 2R. All vertical channels 2L and 2R are connected to successive stages of a horizontal CCD 4 whose output is coupled to external circuitry via an amplifier stage 5. 
     As shown in FIG. 2, vertical CCDs 2L and 2R are formed by n-type semiconductor channels 10A and 10B running parallel between columns of the photodiodes 1. Transfer gates 3L are provided between photodiodes of odd-numbered rows and channels 10A and transfer gates 3R are provided between photodiodes of even-numbered rows and channels 10B. Electrodes G 1  are formed in overlying relationship with transfer gates 3R and electrodes G 3  are formed in overlying relationship with transfer gates 3L, so that when these electrodes are driven to a high trigger voltage, the corresponding underlying transfer gates 3 are turned on to cause electrons to be transferred from the corresponding photodiodes to the associated channels 10. As clearly shown in FIG. 3, the n-type semiconductor channels 10 are formed on a p-type substrate 11 and electrodes G 1  and G 3  are successively formed on the n-type channels 10 in a partially overlying relationship with adjacent electrodes G 2  and G 4 . The electrodes G 1  to G 4  are embedded in a silicon dioxide layer 12. 
     The operation of the image sensor of the first embodiment will be described below with reference to FIGS. 4 and 5. 
     During period t 1 , the clock pulse terminals φ 1  and φ 3  are supplied with an excitation pulse of triggering level (T) and the terminals φ 2  and φ 4  are maintained at high (H) and low (L) voltage levels, respectively, as shown in FIG. 4. Electrodes G 11  and G 31  are driven to a level sufficient to turn on all the transfer gates 3L, 3R. This results in the charge packets in the odd-numbered-row photodiodes being dumped into the vertical channels 10A and trapped under the electrode G 11  as indicated by Q 11  and packets in the even-numbered-row photodiodes being dumped into the vertical channels 10B and trapped under the electrode G 3  as indicated by Q 21  (see FIG. 5). During period t 2 , terminals φ 1 , φ 2 , φ 3  are driven to the high level, so that the charge packets Q 11  and Q 21  spread under electrodes G 11 , G 21 , G 31  (G 12  and G 22 ). 
     During period t 3 , terminals φ 2  and φ 3  are switched to the high level, and portions of the charge packets Q 11  and Q 21  under electrodes G 11  move to electrodes G 21  and G 31 . 
     During period t 4 , terminals φ 3  and φ 4  are switched to the high level, and the charge packets Q 11  and Q 21  move one electrode position and trapped under electrodes G 31  and G 41 . In like manner, terminals φ 1  and φ 4  are switched to the high level during period t 5  to shift the charge packets to electrodes G 41  and G 12 , and terminals φ 1  and φ 2  are switched to the high level during period t 6  to shift the charge packets to electrodes G 12  and G 21 , thus completing a transfer cycle of charge packets using clock pulses of a 90-degree phase difference. Similar events continue during periods t 7  to t 10  corresponding respectively to the events of periods t 3  to t 6 . 
     Therefore, charge packets of odd- and even-numbered rows are transferred down at the same speed and arrive at the horizontal CCD 4 at the same time where they are shifted along to the amplifier stage 5 for delivery to external circuitry. 
     A second embodiment of the present invention is shown in FIGS. 6, 7, 8A and 8B. According to this embodiment, a first horizontal CCD 4A is connected to vertical CCDs 2A and a second horizontal CCD 4B is connected to vertical CCDs 2B. Electrodes G&#39; 1  to G&#39; 4  extend horizontally cross the vertical CCDs 2A and 2B such that, at vertical CCDs 2A, the electrodes G&#39; 1  and G&#39; 2  are reversed in position, and the electrodes G&#39; 3  and G&#39; 4  are likewise reversed in position. As a result, charge packets in the vertical CCDs 2A are transferred upwards to horizontal CCD 5A by electrodes arranged in the order of G&#39; 2 , G&#39; 1 , G&#39; 4  and G&#39; 3 , while charge packets in the vertical CCDs 2B are transferred downwards to horizontal CCD 5B by electrodes arranged in the order of G&#39; 1 , G&#39; 2 , G&#39; 3  and G&#39; 4 . Electrodes G&#39; 1  to G&#39; 4  are respectively connected to terminals φ&#39; 1  to φ&#39; 4  to which four-phase clock pulses are applied. 
     As shown in detail in FIG. 7, electrode G&#39; 1  is formed with oppositely extending rectangular portions 13 and 14, with the portions 13 extending downwards along vertical channels 10A covering transfer gates 3A and the portions 14 extending upwards along vertical channels 10B covering transfer gates 3B. Electrode G&#39; 2  has oppositely extending rectangular portions 15 and 16, with the portions extending downwards along vertical channels 10B and the portions 16 extending upwards along vertical channels 10A. In a similar manner, electrode G&#39; 3  has oppositely extending portions 17 and 18, with the portions extending along vertical channels 10A and the portions 18 extending along vertical channels 10B. Electrode G&#39; 4  is formed with oppositely extending portions 19 and 20, with the portions 19 extending downwards along vertical channels 10B and the portions 20 extending upwards along vertical channels 10A. Overlapping portions are provided between adjacent portions 16 and 17, between adjacent portions 15 and 18, between adjacent portions 14 and 19, and between adjacent portions 13 and 20. 
     With this layout, electrodes G&#39; 1 , G&#39; 2 , G&#39; 3 , G&#39; 4  are arranged along the n-type channels 10A in a recurrent series of G&#39; 2 , G&#39; 1 , G&#39; 4 , G&#39; 3  as illustrated in FIG. 8A for transferring charge packets of odd-numbered rows to the horizontal CCD 5A and in a recurrent series of G&#39; 1 , G&#39; 2 , G&#39; 3 , G&#39; 4  along the n-type channels 10B as illustrated in FIG. 8B for transferring charge packets of even-numbered rows to the horizontal CCD 5B. 
     The four-phase voltage clock pulses supplied to these electrodes are shown in FIG. 9. It is seen that only one excitation pulse is used in the clock pulse sequences. In comparison with the use of two excitation pulses of the previous embodiment, the use of only one excitation pulse is advantageous in that it eliminates the need for precision timing alignment of two excitation pulses. 
     The operation of the CCD image sensor of the second embodiment will be described below with reference to FIGS. 9, 10A and 10B. 
     During period t 1 , the clock pulse terminal φ&#39; 1  is supplied with an excitation pulse of triggering level (T) while terminal φ&#39; 2  is maintained at high voltage level (H) and terminals φ&#39; 3  and φ&#39; 4  are both maintained at low voltage level (L). Electrodes G&#39; 11  and G&#39; 12  are driven to a level sufficient to turn on all the transfer gates 3L, 3R. This causes charge packets Q&#39; 11  and Q&#39; 12  in the odd-numbered-row photodiodes to be dumped into the vertical channels 10A and trapped under the portions 13 of electrodes G&#39; 11  and G&#39; 12  respectively (FIG. 10B), and causes charge packets Q&#39; 21  and Q&#39; 22  in the even-numbered-row photodiodes to be dumped into the vertical channels 10B and trapped under the portions 14 of electrodes G&#39; 11  and G&#39; 12  respectively (FIG. 10B). 
     During period t 2 , terminals φ&#39; 1  and φ&#39; 2  are maintained at the high level while the other terminals are switched to the low level, so that the charge packet Q&#39; 11  spreads under the portions 13 and 16 of electrodes G&#39; 11  and G&#39; 21  and charge packet Q&#39; 12  spreads under the portions 13 and 16 of electrodes G&#39; 12  and G&#39; 22 . Similarly, the charge packet Q&#39; 21  spreads under the portions 14 and 15 of electrodes G&#39; 11  and G&#39; 21  and the charge packet Q&#39; 22  spreads under the portions 14 and 15 of electrodes G&#39; 12  and G&#39; 22 . 
     During period t 3 , terminals φ&#39; 2  and φ&#39; 3  are switched to the high level, and the charge packet Q&#39; 12 , for example, moves to the left one electrode position to electrodes G&#39; 22  and G&#39; 31 , (FIG. 10A), and the charge packet Q&#39; 21 , for example, moves to the right one electrode position to electrodes G&#39; 21  and G&#39; 31  (FIG. 10B). 
     During period t 4 , terminals φ&#39; 3  and φ&#39; 4  are switched to the high level, and the charge packets Q&#39; 11  move one electrode position to the left and trapped under the portions 17 and 20 of electrodes G&#39; 31  and G&#39; 41  (FIG. 10A) and the charge packets Q&#39; 21  move one electrode position to the right and trapped under the portions 18 and 19 of electrodes G&#39; 31  and G&#39; 41  (FIG. 10B). In like manner, terminals φ&#39; 1  and φ&#39; 4  are switched to the high level during period t 5  to shift the charge packets to electrodes G&#39; 41  and G&#39; 12 , and terminals φ&#39; 1  and φ&#39; 2  are switched to the high level during period t 6  to shift the charge packets to electrodes G&#39; 12  and G&#39; 21 , thus completing a transfer cycle of charge packets. Similar events continue during periods t 7  to t 9  corresponding respectively to the events of periods t 3  to t 5 . 
     Therefore, the charge packets of odd-numbered rows are transferred to the horizontal CCD 4A where they are shifted along to the amplifier 5A. On the other hand, the charge packets of even-numbered rows are transferred to the horizontal CCD 4B where they are shifted along to the amplifier 5B. 
     As shown in FIG. 6, the outputs of the CCD image sensor are delivered from amplifiers 5A and 5B and respectively stored into field memories 30A and 30B to accommodate their relative timing differences. The stored signals are then read out by readout circuitry 31. One advantage of this embodiment is that the field signals stored in memories 30A and 30B can be read either in a progressive format or an interlace format depending on applications.