Abstract:
An apparatus for generating a reference voltage in ferroelectric memory device including a sense amplifier which senses and amplifies a voltage difference between a bit line and a bit line bar, and a plurality of memory cells, each having a ferroelectric capacitor, includes a linear capacitor, in response to a predetermined voltage signal inputted from a cell plate line, for storing a predetermined amount of charges; a first switching device for selectively coupling the linear capacitor to the cell plate line; a second switching device for selectively coupling the linear capacitor to the bit line to thereby provide the predetermined amount of charges as the reference voltage to the bit line.

Description:
FIELD OF THE INVENTION 
     This invention relates to a nonvolatile ferroelectric semiconductor memory device using ferroelectric capacitor memory cell and more particularly, to a reference voltage generator to generate a reference voltage in a read operation of the nonvolatile ferroelectric semiconductor memory device. 
     DESCRIPTION OF THE PRIOR ART 
     Generally, a ferroelectric semiconductor memory device, e.g., a nonvolatile ferroelectric random access memory (NVFRAM) includes a plurality of memory cells. Each memory cell includes transistor and at least one ferroelectric capacitor so that the NVFRAM has characteristics of fast access time and small chip size. 
     FIG. 1 shows a hysteresis loop of a ferroelectric capacitor. That is, a relationship between the polarization charge Q and voltage V applied to the capacitor is shown in the FIG.  1 . In the ferroelectric capacitor, even if the voltage difference between two terminals of the ferroelectric capacitor is zero voltage, the charge Q may be one of two values of P 1  and P 2 , to thereby store binary data. Accordingly, based on this characteristics, the ferroelectric capacitor has been used in the nonvolatile memory device. 
     According to the variation of voltage applied to the both terminals of the ferroelectric capacitor, the stored charges therein vary with the degree of polarization of the ferroelectric material as shown in the hysteresis loop of FIG.  1 . 
     For example, it is assumed that the voltage level of −V 1  is applied to the two terminals of the ferroelectric capacitor, supposing that a state P 1  and a state P 2  stand for logic data “1” and “0” respectively. In this case, when the initial charge state of the ferroelectric capacitor is a state P 1 , the charge state thereof is moved to a state P 3  so that the variation of ΔQ 1  is induced. When the initial charge state of the ferroelectric capacitor is a state P 2 , the charge state thereof is moved to a state P 3  so that the variation of the charge of ΔQ 0  is induced. This varied charge ΔQ 1  or ΔQ 0  is charge-shared with a charge previously induced on a bit line of a selected memory cell, and the shared charge on the bit line is coupled to a sense amplifier which amplifies and outputs it as a sensed data corresponding thereto. A reference voltage is required to operate the sense amplifier, and has a mean value of combined varied charge, (ΔQ 1 +ΔQ 0 )/2. The reference voltage is generally generated by using a ferroelectric dummy cell circuit. 
     FIG. 2 shows a circuit diagram of a reference voltage generation circuit which is disclosed in an article by Hiroki Koike et al., “60 ns 1 M bit Nonvolatile Ferroelectric Memory with Non-driven Cell Plate Line Read/Write Scheme”, IEEE.  Journal of Solid State Circuits,  Vol.31, No.11, November 1996. As shown, two dummy cell circuits include two ferroelectric capacitors C 0  and C 1 , respectively. The ferroelectric capacitors C 0  and C 1  store the logic data “0” and “1” respectively. When turning on switching transistors T 0  and T 1  coupled to a dummy word line (DWL), the varied charges ΔQ 0  and ΔQ 1  are applied to a reference lines REF 1  and REF 2  respectively from the ferroelectric capacitors C 0  and C 1 . At this time, When a “high” state signal is applied to an equalizing dummy line EDL, a transistor T 2  turns on to thereby add ΔQ 0  and ΔQ 1  mentioned above, and when each transistor coupled to DTGN or DTGT is turned on, the charge of (ΔQ 1 +ΔQ 0 )/2 is applied to bit lines BL 1 N, BL 2 N or BL 1 T, BL 2 T. 
     However, since in the conventional reference voltage circuits, the two dummy cells should store “1” and “0” and at least one switching operation is required in order to provide the reference voltage for each access to a memory cell, the switching transistors constituting of the dummy cells may be easily fatigued to thereby cause some variation of the reference voltage. Furthermore, since the dummy cells are coupled to the bit line having a multiplicity of memory cells, the dummy cell is read out much more often than the memory cell. Thus, the problem is that lifetime of the device seriously depends upon an operation state of the dummy cell. 
     Also, another problem is that since the reference voltage generation circuit includes a complex extra circuit for driving the dummy cell which has the ferroelectric capacitor, the further integration of the semiconductor device may be limited. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an apparatus for generating a reference voltage in a ferroelectric memory device, which is capable of implementing a high integration in the ferroelectric memory device and effectively providing a reference voltage by using a linear capacitor. 
     It is another object of the present invention to provide an apparatus for generating a reference voltage in a ferroelectric memory device capable of increasing reliability of the ferroelectric memory device. 
     In accordance with an aspect of the present invention, there is provided an apparatus for generating a reference voltage in ferroelectric memory device including a sense amplifier which senses and amplifies voltage difference between a bit line and the bit line bar, and a plurality of memory cells, each having a ferroelectric capacitor, said apparatus comprising: a linear capacitor, in response to a predetermined voltage signal inputted from a cell plate line, for storing a predetermined amount of charges; a first switching device for selectively coupling the linear capacitor to the cell plate line; and a second switching device for selectively coupling the linear capacitor to the bit line to thereby provide the predetermined amount of charges as the reference voltage to the bit line. 
     In accordance with another aspect of the present invention, there is provided a ferroelectric memory device having a reference voltage generation circuit for generating a reference voltage, a sense amplifier which senses and amplifies voltage difference between a bit line and a bit line bar, and a plurality of memory cells, each having a ferroelectric capacitor, comprising: a linear capacitor, in response to a predetermined voltage signal inputted from a cell plate line, for storing a predetermined amount of charges; a first switching device for selectively coupling the linear capacitor to the cell plate line; and a second switching device for selectively coupling the linear capacitor to the bit line to provide thereby the predetermined amount of charges as the reference voltage to the bit line. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which: 
     FIG. 1 shows a hysteresis loop of a ferroelectric capacitor; 
     FIG. 2 is a circuit a circuit diagram illustrating a conventional reference voltage generating circuit employed in a conventional ferroelectric memory device; 
     FIG. 3 is a circuit diagram depicting a reference voltage generating circuit in accordance with the present invention; 
     FIG. 4 is a circuit diagram demonstrating a ferroelectric memory device employing the reference voltage generating circuit in accordance with the present invention; and 
     FIG. 5 is a timing chart disclosing the operation of the ferroelectric memory device shown in FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, preferred embodiments in accordance with the present invention will be described hereinafter in detail referring to the accompanying drawings. 
     Referring to FIG. 3, a reference voltage circuit in accordance with the present invention includes two NMOS transistors NT 0 , NT 1  and a linear capacitor. The linear capacitor can be fabricated, as known in the art in order to store a charge corresponding to (ΔQ 1 +ΔQ 0 )/2. 
     A gate terminal of the NMOS transistor NT 1  is connected to a reference word line rwl, and its drain terminal is coupled to a reference bit line rbl. A source terminal of the NT 1 , a drain terminal of the NT 0  and a upper electrode of the linear capacitor Ca are commonly coupled. A gate terminal of the NT 0  is connected to a reference word line bar rwlb, and a drain terminal of the NT 0  is coupled to a lower electrode of the linear capacitor Ca which is coupled to a cell plate line VCP. In accordance with the present invention, a voltage level of VCC/2 is applied to the cell plate line VCP. 
     The operation of the apparatus for generating reference voltage in accordance with the present invention will be described hereinafter. 
     In a standby state, the reference word line rwl is in a low level and the reference word line bar rwlb is in a high level, so that the NT 1  is turned off and the NT 0  is turned on. A cell plate line voltage of VCC/2 is applied via the cell plate line VCP to the upper and lower electrodes of the linear capacitor Ca which stores a charge corresponding to a reference voltage of (ΔQ 1 +ΔQ 0 )/2. 
     In an active state, a signal of a high level is inputted to the reference word line rwl and thereby, when the NT 1  is turned off, the charge of the linear capacitor Ca is coupled to the reference bit line rbl to thereby generate the reference voltage. 
     FIG. 4 is a circuit diagram illustrating a ferroelectric memory device employing the reference voltage generating circuit in accordance with the present invention. 
     The ferroelectric memory device includes the reference voltage generation circuit  100 , a memory cell array  120 , a sense amplifier  140  which senses and amplifies a voltage difference between a bit line bl 0  and a bit line bar bl 0   b,  and a control circuit  150  which controls a state of the operation of NMOS transistors NT 2 , NT 3 , NT 4 , NT 5  and a cell plate line VCC/2. The reference voltage generation circuit block  100  includes a first reference voltage generation circuit  110  which is coupled to a bit line bl 0  and transfers a reference voltage to a bit line bl 0 , and a second reference voltage generation circuit  111  which is connected to a bit line bar bl 0   b  and transfers a reference voltage to a bit line bar bl 0   b.  The first reference voltage generation circuit  110  is connected between the cell plate line VCC/2 and the bit line bl 0  and in an active state, applies a reference voltage (ΔQ 1 +ΔQ 0 )/2 to the bit line bl 0 . The first reference voltage generation circuit includes an NMOS transistor NT 2 , a gate terminal of which is coupled to a first reference word line bar rwl 0   b,  an NMOS transistor NT 3 , a gate terminal of which is coupled to a first reference word line rwl 0 , and a linear capacitor Ca 1 , an upper electrode and a lower electrode of which are connected to a common source-drain node of the NMOS transistors NT 2  and NT 3 , and a cell plate line VCC/2, respectively. The second reference voltage generation circuit  111  is connected between the cell plate line VCC/2 and the bit line bar bl 0   b,  and, in an active state, applies the reference voltage (ΔQ 1 +ΔQ 0 )/2 to the bit line bar bl 0   b.  The second reference voltage generation circuit includes an NMOS transistor NT 4 , a gate terminal of which is coupled to a second reference word line bar rwl 1   b,  an NMOS transistor NT 5 , a gate terminal of which is coupled to a second reference word line rwl 1 , and a linear capacitor Ca 2  an upper electrode and a lower electrode of which are connected to a common source-drain node of the NMOS transistors NT 4  and NT 5 , and a cell plate line VCC/2, respectively. 
     The memory cell array  120  includes a plurality of memory cells, each memory cell having a ferroelectric capacitor. The configuration and operation of the memory cell array is well known in the art and for the shake of convenience, detailed description is omitted. 
     FIG. 5 is a timing chart depicting the operation of the ferroelectric memory device shown in the FIG.  4 . 
     In a duration “A”, when a first word line signal wl 0  is enabled to a “high” level VPP, according to data stored in the ferroelectric capacitor C 3 , a charge of “Q 0 ” or “Q 1 ” is loaded into the bit line bl 0 . And when also the second reference word line rwl 1  is enabled to a “high” level VPP, a charge of (ΔQ 1 +ΔQ 0 ) stored in the linear capacitor Ca 2  in the second reference voltage generation circuit  111 , is loaded into the bit line bar bl 0   b.    
     In a duration “B”, when the sense amplifier  140  is enabled, the sense amplifier reads out data “1” or “0” stored in the ferroelectric capacitor C 3  by sensing and amplifying the potential difference between the bit line bl 0  into which a charge of “Q 1 ” or “Q 0 ” is loaded, and the bit line bar bl 0   b,  into which a charge of “(ΔQ 1 +ΔQ 0 )/2” is loaded from the second reference voltage generation circuit  111 . 
     Also, in a duration “C”, when the second word line signal wl 1  is enabled to a “high” level VPP, according to data stored in a ferroelectric capacitor C 4 , a charge of “Q 0 ” or “Q 1 ” is loaded into the bit line bar bl 0   b.  And, when also the first reference word line rwl 0  is enabled to a “high” level, a charge of “(ΔQ 1 +ΔQ 0 )/2” stored in the linear capacitor Ca 1  in the first reference voltage generation circuit  110 , is loaded into the bit line bl 0 . 
     In a duration “D”, when the sense amplifier  140  is enabled, the sense amplifier reads out data “1” or “0” stored in the ferroelectric capacitor C 4  by sensing and amplifying the potential difference between the bit line bar bl 0   b  into which a charge of “Q 1 ” or “Q 0 ” is loaded, and the bit line bl 0 , into which a charge of “(ΔQ 1 +ΔQ 0 )/2” is loaded from the first reference voltage generation circuit  110 . 
     As can be seen from above, the reference voltage generation circuit of the present invention supplies a stable reference voltage because degradation due to a ferroelectric capacitor is removed by employing a linear capacitor which stores a charge corresponding to a reference voltage. Accordingly, reliability of the ferroelectric memory device can be increased. 
     Also, the reference voltage generation circuit does not employ a complex extra circuit to drive ferroelectric capacitors used in the art, the integration of the ferroelectric memory device can be effectively increased. 
     Although the preferred embodiments of the invention have been disclosed for illustrative purpose, those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope and sprit of the invention as disclosed in the accompanying claims.