Abstract:
A low-dropout regulator with a single-transistor-control providing improved transient response and stability is disclosed. The single-transistor-control provides a dynamic resistance at the output of the regulator for minimizing undershoot and overshoot, and hence improves transient response. Since the single-control transistor reduces the output resistance of the regulator, the output pole is pushed to a sufficiently high frequency without affecting stability. Therefore, the limited choice of combinations of the output capacitance and its equivalent-series-resistance is substantially relaxed.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefits of U.S. Provisional Application No. 60/658,752 filed on Mar. 7, 2005, which is hereby incorporated herein by reference in its entirety. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates to a low-dropout regulator, and in particular, to a low-dropout regulator that has improved transient response and stability.  
       BACKGROUND OF THE INVENTION  
       [0003]     A low-dropout (LDO) regulator accepts an unregulated input voltage (V IN ) and provides a regulated output voltage (V OUT ) that is nearly independent of output current (e.g. a load current). A PMOS pass transistor is used to minimize the voltage difference between the input and output of a LDO regulator, and hence increases power conversion efficiency.  
         [0004]      FIG. 1  shows the schematic of a typical LDO regulator according to the art, which consists of a pass transistor, an error amplifier, a reference voltage, a feedback resistor network and an optional output capacitor. Frequency compensation to achieve stability in a typical LDO is necessary as there are two high-impedance nodes, which are at the error amplifier output and at the drain of pass transistor. To provide such frequency compensation dominant-pole compensation and pole-zero cancellation are commonly used in the art, but these limit the choices of combinations of the output capacitance (C OUT ) and its equivalent-series-resistance (R ESR ) for LDO regulator stability. Furthermore, since the loop bandwidth of a conventional LDO is degraded by dominant-pole compensation, optimization between stability and transient response is difficult to achieve.  
       SUMMARY OF THE INVENTION  
       [0005]     According to the present invention there is provided a low-dropout regulator comprising: 
    (a) a pass transistor connected to an output terminal of said regulator,     (b) a control transistor having a first electrode connected to the output terminal of said regulator, a second control electrode biased with a control voltage generated by a reference mirror circuit, and a third electrode connected to a DC-biasing circuit and a biasing-current source,     (c) a DC-biasing circuit connected between a control electrode of the pass transistor and the third electrode of the control transistor,     (d) a reference mirror circuit accepting a supply- and temperature-independent reference voltage and generating a control voltage applied to the control electrode of the control transistor, and     (e) a first biasing-current source providing biasing to the control transistor and the DC-biasing circuit.    
 
         [0011]     In preferred embodiments of the invention the pass transistor is a P-channel Metal-Oxide-Silicon Field-Effect-Transistor (PMOSFET) or a PNP bipolar junction transistor, and the pass transistor is connected in series between an input terminal and the output terminal of the regulator, wherein the first electrode of the control transistor is the low-impedance electrode and the third electrode of the control transistor is the output electrode, and wherein one end of the DC-biasing circuit is coupled to the input of the regulator. The control transistor provides ultra-low resistance at the output terminal of the regulator, and this resistance can be dynamically changed according to the output voltage of the regulator.  
         [0012]     The control transistor may also be preferably either a PMOSFET or a PNP bipolar junction transistor. In such embodiments of the invention the gate/base electrode of the control transistor is biased with a control voltage generated by the reference mirror circuit, the source/emitter electrode of the control transistor is coupled to the output of the regulator, and the drain/collector electrode of the control transistor is connected to the DC-biasing circuit and the first biasing-current source.  
         [0013]     In preferred embodiments of the invention the DC-biasing circuit provides a DC voltage difference between the control electrode of the pass transistor and the output electrode of the control transistor whereby the control transistor operates in the saturation region.  
         [0014]     The DC-biasing circuit preferably comprises a second biasing-current source and a resistive element. In such an embodiment preferably the second biasing-current source is connected between the input terminal of the regulator and the control electrode of the pass transistor, the resistive element is interposed between the control electrode of the pass transistor and the output electrode of the control transistor, and the second biasing-current source provides biasing current to the resistive element in order to produce a DC voltage difference between the control electrode of the pass transistor and the output electrode of the control transistor.  
         [0015]     The resistive element may be a resistor connected between the control electrode of the pass transistor and the output electrode of the control transistor, or alternatively may be an N-channel Metal-Oxide-Silicon Field-Effect-Transistor (NMOSFET) or a NPN bipolar junction transistor. If the resistive element is a NMOSFET or a NPN bipolar junction transistor then the source/emitter electrode of the NMOSFET/NPN bipolar junction transistor is coupled to the output electrode of the control transistor, the drain/collector electrode of the NMOSFET/NPN bipolar junction transistor is connected to the control electrode of the pass transistor, and the voltage applied on the gate/base electrode of the NMOSFET/NPN bipolar junction transistor is used to control the source-to-drain/emitter-to-collector resistance whereby a suitable DC voltage difference is provided between the control electrode of the pass transistor and the output electrode of the control transistor.  
         [0016]     Preferably the reference mirror circuit comprises a diode-connected transistor, a current mirror, a transconductance G m -cell and a third biasing-current source. It is particularly preferred that (within tolerances) the diode-connected transistor has the same dimensions and consumes the same current as the control transistor whereby the voltage across the low-impedance electrode and the control electrode of both the diode-connected transistor and the control transistor are the same whereby the output voltage of the regulator equals the voltage applied to the low-impedance electrode of the diode-connected transistor.  
         [0017]     The diode-connected transistor may be a PMOSFET or a PNP bipolar junction transistor. In such embodiments preferably both the drain/collector electrode and the gate/base electrode of the diode-connected transistor and the third biasing-current source are connected to form the output terminal of the reference mirror circuit and thereby generating a control voltage biased to the control electrode of the control transistor.  
         [0018]     The current mirror may comprise two PMOSFETs or PNP bipolar junction transistors. In such embodiments the source/emitter electrodes of both the PMOSFETs/PNP bipolar junction transistors are coupled to the input terminal of regulator, and one of the PMOSFETs/PNP bipolar junction transistors is diode-connected to sense the output current of G m -cell, whereby by connecting the gate/base electrodes of both PMOSFETs/PNP bipolar junction transistors the sensed output current of G m -cell is mirrored to the low-impedance electrode of the diode-connected transistor.  
         [0019]     Preferably both the current mirror and the G m -cell mirror the supply- and temperature-independence reference voltage to the low-impedance electrode of the diode-connected transistor with current-driving capability.  
         [0020]     It will also be understood by those skilled in the art that instead of using PMOSFET/PNP transistors for the pass and control transistors, an alternative circuit may be configured using NMOSFET/NPN transistors.  
         [0021]     Therefore in an alternative embodiment of the invention the pass transistor is a N-channel Metal-Oxide-Silicon Field-Effect-Transistor (NMOSFET) or a NPN bipolar junction transistor, wherein the pass transistor is connected in series between the output terminal of the regulator and ground, wherein the first electrode of the control transistor is the low-impedance electrode and the third electrode of the control transistor is the output electrode, and wherein one end of the DC-biasing circuit is coupled to ground. The control transistor provides ultra-low resistance at the output terminal of the regulator, which resistance can be dynamically changed according to the output voltage of the regulator.  
         [0022]     In this embodiment the control transistor may also be a NMOSFET or a NPN bipolar junction transistor. The gate/base electrode of the control transistor may be biased with a control voltage generated by the reference mirror circuit, the source/emitter electrode of the control transistor is coupled to the output of the regulator, and the drain/collector electrode of the control transistor is connected to the DC-biasing circuit and the first biasing-current source.  
         [0023]     The DC-biasing circuit may provide a DC voltage difference between the control electrode of the pass transistor and the output electrode of the control transistor whereby the control transistor operates in the saturation region.  
         [0024]     The DC-biasing circuit preferably comprises a second biasing-current source and a resistive element. The second biasing-current source may be connected between ground and the control electrode of the pass transistor, the resistive element is interposed between the control electrode of the pass transistor and the output electrode of the control transistor, and the second biasing-current source provides biasing current to the resistive element, which produces a DC voltage difference between the control electrode of said pass transistor and the output electrode of the control transistor. The resistive element may be a resistor connected between the control electrode of the pass transistor and the output electrode of the control transistor, or alternatively may be a P-channel Metal-Oxide-Silicon Field-Effect-Transistor (PMOSFET) or a PNP bipolar junction transistor.  
         [0025]     Preferably the source/emitter electrode of the PMOSFET/PNP bipolar junction transistor is coupled to the output electrode of the control transistor, the drain/collector electrode of the PMOSFET/PNP bipolar junction transistor is connected to the control electrode of the pass transistor, and the voltage applied on the gate/base electrode of the PMOSFET/PNP bipolar junction transistor is used to control the source-to-drain/emitter-to-collector resistance whereby a suitable DC voltage difference is provided between the control electrode of the pass transistor and the output electrode of the control transistor.  
         [0026]     The reference mirror circuit may comprise a diode-connected transistor, a current mirror, a transconductance G m -cell and a third biasing-current source. Preferably, within tolerances the diode-connected transistor has the same dimensions and consumes the same current as the control transistor. Preferably within tolerances the voltage across the low-impedance electrode and the control electrode of both the diode-connected transistor and the control transistor are the same whereby the output voltage of said regulator equals the voltage applied to the low-impedance electrode of the diode-connected transistor. The diode-connected transistor may be a NMOSFET or a NPN bipolar junction transistor. Both the drain/collector electrode and the gate/base electrode of the diode-connected transistor and the third biasing-current source may be connected to form the output terminal of the reference mirror circuit and thereby generating a control voltage biased to the control electrode of the control transistor.  
         [0027]     In one embodiment of the invention the current mirror comprises two NMOSFETs or NPN bipolar junction transistors. In this embodiment the source/emitter electrodes of both NMOSFETs/NPN bipolar junction transistors are coupled to ground, and one of the NMOSFETs/NPN bipolar junction transistors is diode-connected to sense the output current of G m -cell, whereby by connecting the gate/base electrodes of both said NMOSFETs/NPN bipolar junction transistors the sensed output current of G m -cell is mirrored to the low-impedance electrode of the diode-connected transistor.  
         [0028]     Preferably both the current mirror and the G m -cell mirror the supply- and temperature-independence reference voltage to the low-impedance electrode of the diode-connected transistor with current-driving capability. Preferably the reference mirror circuit accepts a supply- and temperature-independent reference voltage and mirrors this reference voltage to the output terminal of the regulator by generating a control voltage biased to the control electrode of the control transistor.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     Some embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:  
         [0030]      FIG. 1  is a schematic illustration of an art LDO regulator,  
         [0031]      FIG. 2  is a schematic illustrating the structure of a LDO regulator according to an embodiment of the invention,  
         [0032]      FIG. 3  is a schematic illustration of the embodiment of  FIG. 2 ,  
         [0033]      FIG. 4  is a schematic illustrating the structure of an LDO regulator according to an alternative embodiment of the invention, and  
         [0034]      FIG. 5  is a schematic illustration of the embodiment of  FIG. 4 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0035]     This invention provides a LDO regulator with improved transient response and stability based on the concept of providing ultra-low resistance, which can be dynamically changed according to V OUT , at the output of the LDO regulator, even though the pass transistor itself has high output resistance.  
         [0036]      FIG. 2  shows the basic structure of an embodiment of the LDO regulator in accordance with this invention, including a pass transistor M PASS , a control transistor M CON , a DC-biasing circuit, a reference mirror circuit, a first biasing-current source I B1  and an optional output capacitor. M PASS  is interposed between V IN  and V OUT . The gate electrode of M PASS  is coupled to one end of the DC-biasing circuit. The source electrode of M CON  is connected to V OUT . The gate electrode of M CON  is biased by a control voltage V CON , which is generated by the reference mirror circuit. The drain electrode of M CON  is coupled to one end of the current source and one end of the DC-biasing circuit. Another end of current source is coupled to ground. M CON  produces a control current I C  that is proportional to the difference between V OUT  and V CON . Both I C  and I B1  provide information to the DC-biasing circuit, which determines the gate voltage of M PASS  for regulating V OUT .  
         [0037]     Although M PASS  operates in saturation region, the output resistance is reduced by the source electrode of M CON . In addition, feedback action further reduces the output resistance by at least two orders of magnitude due to the high voltage gain of M CON . Since the pole formed by C OUT  and output resistance is located at a sufficiently high frequency without affecting stability of the LDO regulator, the limited choices of combinations of C OUT  and R ESR  are substantially relaxed.  
         [0038]     The output resistance R OUT  of a LDO regulator is given by the equation  
         R   OUT     =     1       g     m   ⁢           ⁢   c       ⁡     (     1   +       g     m   ⁢           ⁢   p       ⁢     r   b         )             
 
 where 
    a) g mp  and g mc  are the transconductance of M PASS  and M CON , respectively, and     b) r b  is the total resistance contributed by devices connecting to the gate electrode of M PASS .    
 
         [0041]     The transient response of a LDO regulator also benefits from M CON  according to this invention. When load current is increased, the decreased V OUT  increases the resistance of M CON , which minimizes the discharge of the output capacitor, and hence reduces the undershooting voltage. Moreover, I C  produced by M CON  is reduced due to the decreased V OUT . The gate of M PASS  is discharged by I B1  through the DC-biasing circuit to match heavy load condition. While load current is reduced, the resistance of M CON  is reduced due to increased V OUT . As M PASS  cannot respond immediately, the excess current of M PASS  is sunk by the low-resistance M CON  to minimize the charge of the output capacitor and the overshoot voltage. In addition, the increased V OUT  triggers M CON  to produce more I C , which increases the gate voltage of M PASS  through the DC-biasing circuit to match light load condition.  
         [0042]      FIG. 3  shows in detail a circuit for realizing the general structure of  FIG. 2  to form a LDO regulator according to an embodiment of this invention. In this embodiment the reference mirror circuit consists of a third biasing-current source I B3 , which has the same current level as the biasing current I B1  of M CON , a diode-connected transistor M OFF , a current mirror consisting of two transistors M 1  and M 2  and a transconductance G m -cell. The source electrode of M OFF  is connected to the drain electrode of M 2  and the non-inverting input of G m -cell. Both the drain electrode and the gate electrode of M OFF  are coupled together to form a diode-connection, producing a V CON  for biasing the gate electrode of M CON . The biasing-current source inside the reference mirror circuit is interposed between the output of the reference circuit and the ground. The source electrodes of both M 1  and M 2  are coupled to V IN . The gate and drain electrodes of M 1  and gate electrode of M 2  are connected and driven by the output of G m -cell. V REF  is coupled to the inverting input of G m -cell.  
         [0043]     Preferably, at least within tolerances, the diode-connected transistor M OFF  has the same dimensions and consumes approximately the same current as the control transistor M CON . The advantage of this is that the voltage across the low-impedance electrode and the control electrode of both M OFF  and M CON  are the same whereby the output voltage of the regulator equals the voltage applied to the low-impedance electrode of M OFF . Since M OFF  and M CON  have the same size and the same biasing current, the dependence of the gate-to-source voltage of M CON  on V OUT  is eliminated by M OFF , and thus, V OUT  equals the voltage applied to the source electrode of M OFF . The current mirror and G m -cell are used to provide V REF  with driving capability to the source electrode of M OFF . Therefore, the reference circuit accepts a supply- and temperature-independent V REF , and generates V CON  to the source electrode of M CON . Hence, the LDO regulator regulates V OUT  closely to V REF  applied to the reference circuit.  
         [0044]     The DC-biasing circuit consists of a second biasing-current source I B2  and a resistive element or a voltage level shifting element. The resistive element may be either a resistor or may be either a NMOSFET or NPN bipolar junction transistor. In the latter case the source/emitter electrode of the NMOSFET/NPN bipolar junction transistor is coupled to the output electrode of the control transistor, the drain/collector electrode of the NMOSFET/NPN bipolar junction transistor is connected to the control electrode of the pass transistor, and the voltage applied on the gate/base electrode of the NMOSFET/NPN bipolar junction transistor is used to control the source-to-drain/emitter-to-collector resistance whereby a suitable DC voltage difference is provided between the control electrode of the pass transistor and the output electrode of the control transistor.  
         [0045]     The biasing-current source inside the DC-biasing circuit is connected between V IN  and the gate electrode of M PASS . The resistive element is interposed between the gate electrode of M PASS  and the drain electrode of M CON . Both I B2  and the resistive element create a DC-offset voltage between the drain electrode of M CON  and the gate electrode of M PASS . M CON  is guaranteed to operate in saturation region under a wide range of V IN , and therefore extends the input voltage range of a LDO regulator.  
         [0046]     It will be understood that while in the embodiment shown in  FIGS. 2 and 3  the transistors M PASS , M CON  and M OFF  are all shown as PMOSFET transistors it will be understood that they could be placed by PNP bipolar junction transistors (BJT). If PNP BJTs are used then it will be understood that in the above description the MOSFET electrode terminology gate/source/drain is replaced by the BJT electrode terminology base/emitter/collector respectively. Moreover, it will also be understood by those skilled in the art that a complementary circuit could be designed using NMOSFET or NPN transistors in which the PMOSFET or PNP transistors are replaced by NMOSFET or NPN transistors with appropriate reconfiguration of the circuit. An example of how this might be done is shown in  FIGS. 4 and 5 .  
         [0047]     It will be seen from the above that the present invention, at least in its preferred forms, provides a LDO regulator that unlike a conventional LDO does not require a tradeoff between stability and transient response, but rather provides a LDO regulator with simultaneously both improved transient response and stability.  
         [0048]     The LDO regulator, at least in its preferred forms, consists of a pass transistor, a control transistor, a DC-biasing circuit, a reference mirror circuit, a biasing-current source and an optional output capacitor. The pass transistor connects in series between the input terminal and the output terminal of the LDO regulator. The control electrode of the control transistor is biased with a control voltage generated by the reference mirror circuit. The output terminal of the regulator is connected to the low-impedance electrode of the control transistor, which produces a control current proportional to the difference between the V OUT  and the control voltage. The control current controls the pass transistor through the DC-biasing circuit for regulating V OUT  to a pre-defined value.  
         [0049]     In steady-state operation, the output resistance of the LDO regulator is significantly reduced by both the low-impedance electrode of the control transistor connected to the output terminal of the regulator and the feedback used for regulation. Hence, the pole location at the output of the LDO regulator is pushed to a sufficiently high frequency without affecting stability, and this approach relaxes the limited choices of combinations of C OUT  and R ESR .  
         [0050]     During load transient, the capacitor at the output of the regulator (e.g. an optional output capacitor or regulator output parasitic capacitor) is either charged by the excess current of the pass transistor or discharged by the increased load current, and the V OUT  is changed accordingly. The control transistor senses the change of V OUT , and produces a corresponding control current for regulation. More importantly, the resistance of the control transistor connected to the output of the regulator is reduced to sink the excess pass transistor current or increased to minimize the discharge of the output capacitor, and therefore improves transient response