Abstract:
A data processing system contains a processor supporting instructions and operands utilizing a Narrow word size. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. The translation between Narrow and Wide word sizes can be either at a byte/Unicode level, or at a word level.

Description:
FIELD OF THE INVENTION 
     The present invention generally relates to data processing systems, and more specifically to computer processors capable of supporting 32 or 36 bit instructions installable and communicating using 64 bit industry standard busses and peripherals. 
     BACKGROUND OF THE INVENTION 
     There are millions of lines of code in existence that execute on proprietary hardware. For example, the assignee herewith sells GCOS® 8 hardware and software. GCOS® 8 is a proprietary system with a thirty-six (36) bit word size. Another proprietary thirty-six (36) bit system is the 1100/2200 systems sold by Unisys Corporation. A number of companies sell proprietary thirty-two (32) bit systems. As computer system design has evolved, the industry has settled on a byte size of 8-bits which most typically are contained in either thirty-two (32) bit or sixty-four (64) bit words. 
     The cost of continuously developing ever more powerful proprietary systems continues to increase. Part of the cost of developing follow-on proprietary systems is the cost of developing custom I/O interfaces and the like. Continuous development in this area is extremely expensive. 
     It would thus be advantageous to have a system where legacy code can be easily executed, while still being able to utilize industry standard components that utilize a different width byte or word. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying FIGURES where like numerals refer to like and corresponding parts and in which: 
     FIG. 1 is a block diagram illustrating a General Purpose Computer; 
     FIG. 2 is a block diagram of a first processor  50 , in accordance with the present invention; 
     FIG. 3 is a block diagram illustrating a preferred translation between the sixty-four (64) bit “WIDE” data bus and the thirty-six (36) bit “NARROW” data cache and instruction cache shown in FIG. 2; and 
     FIG. 4 is a block diagram illustrating a second translation between the sixty-four (64) bit “WIDE” data bus and the thirty-six (36) bit “NARROW” data cache and instruction cache shown in FIG.  2 . 
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth such as specific word or byte lengths, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art. 
     The term “bus” will be used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status. The terms “assert” and “negate” will be used when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state will be a logic level zero. And if the logically true state is a logic level zero, the logically false state will be a logic level one. 
     FIG. 1 is a block diagram illustrating a General-Purpose Computer  20  or data processing system. The General Purpose Computer  20  has a Computer Processor  22 , and Memory  24 , connected by a Bus  26 . It should be noted that a single bus  26  is shown in this and subsequent FIGs. This is done for clarity. It should be understood that presently such a bus  26  is typically implemented as a plurality of busses. Memory  24  is a relatively high speed machine readable medium and includes Volatile Memories such as DRAM, and SRAM, and Non-Volatile Memories such as, ROM, FLASH, EPROM, EEPROM, and bubble memory. 
     Also connected to the Bus are Secondary Storage  30 , External Storage  32 , output devices such as a monitor  34  and a printer  38 , and input devices such as a keyboard  36  and mouse  37 . Secondary Storage  30  includes machine-readable media such as hard disk drives, magnetic drum, and bubble memory. External Storage  32  includes machine-readable media such as floppy disks, removable hard drives, magnetic tape, CD-ROM, and even other computers, possibly connected via a communications line  28 . The distinction drawn here between Secondary Storage  30  and External Storage  32  is primarily for convenience in describing the invention. As such, it should be appreciated that there is substantial functional overlap between these elements. Computer software including user programs can be stored in a Computer Software Storage Medium, such as memory  24 , Secondary Storage  30 , and External Storage  32 . Executable versions of computer software  33 , can be read from a Non-Volatile Storage Medium such as External Storage  32 , Secondary Storage  30 , and Non-Volatile Memory and loaded for execution directly into Volatile Memory, executed directly out of Non-Volatile Memory, or stored on the Secondary Storage  30  prior to loading into Volatile Memory for execution. 
     FIG. 2 is a block diagram of a first processor  50 , in accordance with the present invention. The processor  50  is coupled to a bus  26 . The bus  26  comprises a sixty-four (64) bit data bus  72 , a thirty-six (36) bit address bus  74 , and a control bus  76 . As noted above, the bus  26  is typically implemented as a hierarchy of busses. In this instance, the data bus  72 , address bus  74 , and control bus  76  together comprise a processor bus. The data bus  72 , the address bus  74  and the control bus  76  are coupled to a bus interface  56 . Thirty-six (36) address bus  74  lines are utilized to conform to the Intel® Pentium® II interface. Other configurations are within the scope of this invention. The bus interface  56  is coupled to a thirty-six (36) bit data cache  54  and a thirty-six (36) bit instruction cache  56 . The thirty-six (36) bit data cache  54  and the thirty-six (36) bit instruction cache  56  are typically constructed of high speed SRAM. The coupling between the data cache  54  and the bus interface  58  is typically bi-directional, whereas the coupling between the bus interface  58  and the instruction cache  56  is typically single directional, since there is typically no need to write instructions back to slower memory  24 . In the preferred embodiment, there are thirty-six (36) data signal lines coupling the bus interface  58  with the data cache  54  and instruction cache  56 . 
     The instruction cache  56  is coupled to and provides instructions to an instruction execution unit  52 . In the preferred embodiment, the instructions are thirty-six (36) bits in length. Typically, such an instruction execution unit  52  provides for pipelined execution of multiple instructions, synchronization of out-of-order execution, and branch prediction. However, these optimizations are not necessary to practice this invention. The instruction execution unit  52  provides control signals to control execution of a thirty-six (36) bit Integer Processing Unit  60 , thirty-six (36) bit general purpose registers  62 , a thirty-six (36) bit load/store unit  64 , a thirty-six (36) bit floating point unit  68 , thirty-six (36) bit floating point registers  66 , the thirty-six (36) bit data cache  54 , and the thirty-six (36) bit instruction cache  56 . The load/store unit  64  is bidirectionally coupled to the thirty-six (36) bit general purpose registers  62 , the thirty-six (36) bit floating point registers  66  and the thirty-six (36) bit data cache  54 . The load/store unit  64  loads thirty-six (36) bit values into the thirty-six (36) bit general purpose registers  62  and floating point registers  66  from the thirty-six (36) bit data cache  54 , and writes them back to the thirty-six (36) bit data cache  54 , as required. The thirty-six (36) bit general-purpose registers  62  are bidirectionally coupled to and utilized by the thirty-six (36) bit integer processing unit  60  to perform integer arithmetic, as well as other logical functions. Such an integer processing unit  60  typically comprises logical/shift modules, integer addition/subtraction modules, and integer multiplication/division modules. The thirty-six (36) bit integer processing unit  60  will typically set condition code flags in one or more condition code registers in the thirty-six (36) bit general purpose registers  62  based on the results of the arithmetic and logical functions performed. These condition code flags are provided to the instruction execution unit  52  for use in conditional branching. In this preferred embodiment, the thirty-six (36) bit integer processing unit  60  provides for thirty-six (36) bit arithmetic and logical functions. Similarly, the thirty-six (36) bit floating point registers  66  are bidirectionally coupled to and utilized by the thirty-six (36) bit floating point unit  68  to perform thirty-six (36) bit floating point arithmetic functions. 
     A single integer processing unit  60  and floating point unit  68  are shown in this and subsequent FIGs. This is done for clarity in this and the subsequent FIGs. The present invention may include more such units. In particular note that a pipelined processor  50  will typically contain multiple integer processing units  60  providing multiple concurrent integer computations, and multiple floating point units  68  providing multiple concurrent floating point computations. 
     The processor  50  shown in FIG. 2 is preferably a thirty-six (36) bit processor, with thirty-six (36) bit data paths between functional units. This thirty-six (36) bit processor can plug into an industry standard sixty-four (64) bit processor slot. This has the advantage that thirty-six (36) bit code can be executed on a computer system  20  that utilizes industry standard memory  24 , bus  26 , secondary storage  30 , external storage  32 , and other peripherals. This ability to utilize industry standard parts significantly reduces the cost of implementing a thirty-six (36) processor architecture, without the loss of any functionality. 
     The architectures shown herein are shown utilizing two different width architectures: a thirty-six (36) bit “NARROW” architecture, and a sixty-four (64) bit “WIDE” architecture. In the preferred embodiment, the thirty-six (36) bit “NARROW” architecture is the proprietary GCOS® 8 architecture provided by the assignee herein. The sixty-four (64) bit “WIDE” architecture is preferably an open architecture. Thus, a thirty-six (36) bit GCOS® 8 processor  50  is slot and bus compatible with the sixty-four (64) bit Merced architecture. It should be noted that this invention covers other combinations of “NARROW” and “WIDE” architectures. For example, most micro-processors presently utilize thirty-two (32) bit architectures. Such thirty-two (32) bit architectures typically support four eight-bit bytes. Each eight-bit byte can be utilized to store a single value ranging from zero to 255. Presently, this is sufficient for most applications that need to store English language text. It is not sufficient to store Japanese and Chinese characters. For this reason, the computer industry is undergoing a transition from using eight-bit bytes to using sixteen-bit unicode bytes. Four of these sixteen-bit unicode bytes can be combined into a sixty-four (64) bit word. This invention provides the capability of easy migration from the use of eight-bit bytes to the use of sixteen (16) bit Unicode bytes while retaining the meaning of formerly defined opcodes. 
     FIG. 3 is a block diagram illustrating a preferred translation between the sixty-four (64) bit “WIDE” data bus  72  and the thirty-six (36) bit “NARROW” data cache  54  and instruction cache  56  shown in FIG.  2 . In FIG. 2, this conversion or translation is performed by the bus interface  58 . On the left side of the FIG. are shown sixty-four (64) “WIDE” signals  42  entering or leaving a register  40 . On the right side of the FIG. are shown thirty-six (36) “NARROW” signals  44  entering or leaving the register  40 . The sixty-four (64) “WIDE” signals  42  can be seen as being divided into four groups of sixteen signals per group. Numbering signals [ 63 : 0 ], the four groups are [ 63 : 48 ], [ 47 : 32 ], [ 31 : 16 ], and [ 15 : 0 ]. Each of these sixteen (16) bit groups is further broken into a seven-bit more-significant group of signals, and a nine-bit less-significant group of signals. Thus, the sixteen-bit group of signals [ 15 : 0 ] is broken into a seven-bit group [ 15 : 09 ], and a nine-bit group [ 08 : 00 ]. Likewise, the [ 63 : 48 ] signals are broken into a [ 63 : 57 ] seven-bit and a [ 56 : 48 ] nine-bit group; the [ 47 : 32 ] signals into a [ 47 : 41 ] seven-bit and a [ 40 : 32 ] nine-bit group; and the [ 31 : 16 ] signals into a [ 31 : 25 ] seven-bit and a [ 24 : 16 ] nine-bit group. 
     The “NARROW” signals  44  can be seen as being divided into four groups of nine (9) signals per group. Numbering the thirty-six (36) signals [ 35 : 0 ], the four groups of signals are [ 35 : 27 ], [ 26 : 18 ], [ 17 : 9 ], and [ 8 : 0 ]. NARROW signals [ 8 : 0 ] are coupled to WIDE signals [ 8 : 0 ]. NARROW signals [ 17 : 9 ] are coupled to WIDE signals [ 24 : 16 ]. NARROW signals [ 26 : 18 ] are coupled to WIDE signals [ 40 : 32 ]. NARROW signals [ 35 : 27 ] are coupled to WIDE signals [ 56 : 48 ]. The remaining WIDE signals ([ 15 : 9 ], [ 31 : 25 ], [ 47 : 41 ], and [ 63 : 57 ]) are preferably discarded on the WIDE  42  to NARROW  44  transition, and set to zero on the NARROW  44  to WIDE  42  transition. In one alternative embodiment, the remaining WIDE signals ([ 15 : 9 ], [ 31 : 25 ], [ 47 : 41 ], and [ 63 : 57 ]) are utilized for error detection and correction for architectures that do not directly support complex error correction. For example, part or all of a given set of WIDE signals (e.g. [ 15 : 09 ]) not coupled to NARROW signals may contain an Error Correction Code (ECC) for the corresponding coupled WIDE signals (e.g. [ 8 : 0 ]). 
     FIG. 4 is a block diagram illustrating a second translation between the sixty-four (64) bit “WIDE” data bus  72  and the thirty-six (36) bit “NARROW” data cache  54  and instruction cache  56  shown in FIG.  2 . In FIG. 4, this conversion or translation is performed by the bus interface  58 . WIDE  42 ′ signals [ 35 : 00 ] are coupled to corresponding NARROW  44 ′ signals [ 35 : 00 ] through a register  40 ′, and the remaining WIDE  42 ′ signals [ 63 : 36 ] are discarded on the WIDE  42 ′ to NARROW  44 ′ transition, and set to zero on the NARROW  44 ′ to WIDE  42 ′transition. 
     Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims. 
     Claim elements and steps herein have been numbered and/or lettered solely as an aid in readability and understanding. As such, the numbering and/or lettering in itself is not intended to and should not be taken to indicate the ordering of elements and/or steps in the claims.