Abstract:
A high-speed output transconductance amplifier (OTA) capable of operating at different voltage levels. The high-speed output transconductance amplifier configures a cross-coupled circuit with programmable switches to offer a high-speed receiver capable of operating at lower voltage and normal voltage, for example, a receiver can be operated in both for SSTL-3 (3.3V system) and SSTL-2 (2.5V system).

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates to a high-speed output transconductance amplifier (OTA), which configures a cross-coupled circuit with programmable switches to offer a high-speed receiver capable of operating at different voltage levels.  
           [0003]    2. Description of Related Art  
           [0004]    An application example of a typical output transconductance amplifier (OTA) in an existing high speed receiver is given as follows.  
           [0005]    [0005]FIG. 1 is a circuit diagram of a typical OTA  10 . In FIG. 1, the OTA  10  is formed by an NMOS current mirror circuit M 1 -M 2 , two PMOS current mirror circuits M 3 -M 4 , M 5 -M 6  and a differential operational amplifier M 7 -M 9 . As shown in FIG. 1, the NMOS current mirror circuit includes NMOS transistors M 1 -M 2  with common gates and common grounding sources, wherein a drain of M 1  is connected to the common gate providing a current mirror function. The NMOS transistor M 9  acts as a current source providing a reference current IABC controlled by a differential voltage pair REF, IN respectively connected to gates of M 8 , M 7 . Thus, DC power dissipation from output-to-input thermal feedback (because in the layout, M 7  and M 8  are placed next to M 2  and M 3 ) is decreased by adjusting the reference current through input voltages of REF, IN. Additionally, the symmetric diode configuration of M 4  and M 5  in parallel respectively with M 3  and M 6  is a voltage to current converter and sends the current through M 3  and M 6 . In this diode configuration, it can keep M 7  and M 8  saturated and provide a high resistance region in the middle for M 3  and M 6  so the output switches faster to minimize delay. The OTA is a current steering circuit with an output current Io. The output current Io can be represented by the differential input voltages IN, REF: 
             Io=gm ( IN−REF ) 
           [0006]    where, gm is the transconductance gain equal to I ABC /2V T , and V T  is the threshold voltage of an MOS device.  
           [0007]    However, although this OTA  10  can provide suitable current to ensure function correctly (e.g. using 3.3V device in SSTL-3, 3.3V system), but for lower voltage system (e.g. using 3.3V device in SSTL-2, 2.5V system), it will not be operated function correctly. This is because the differential pair M 7  and M 8  may limit the output signal range and increase the susceptibility to device mismatching due to square-law behavior of a device in saturation. Further, a current mirror ratio B has to decrease in order to reach the requested gain gm (see MARC G. R. DEGRAUWE and WILLY M. C. SANSEN, “The Current Efficiency of MOS Transconductance Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 3, June 1984.)  
         SUMMARY OF THE INVENTION  
         [0008]    Accordingly, an object of the invention is providing a high-speed output transconductance amplifier capable of operating at different voltage levels by means of switching on or off the extra cross-coupled circuit.  
           [0009]    The invention provides a high-speed output transconductance amplifier capable of operating at different voltage levels, including an NMOS current mirror circuit consisting of a first NMOS transistor with a drain, a gate and a diode-configured NMOS with a drain and a gate connected to the gate of the first NMOS and the drain of the diode-configured NMOS transistor; two PMOS current mirror circuits consisting of a first PMOS transistor with a gate and a drain connected to the drain of the first NMOS transistor to form a connection point as an output terminal, a second PMOS transistor with a gate and a drain connected to the drain of the diode-configured NMOS transistor, a first diode-configured PMOS transistor with a drain and a gate connecting the drain of the first diode-configured PMOS transistor and the gate of the first PMOS transistor, and a second diode-configured PMOS transistor with a drain and a gate connected to the drain of the second diode-configured PMOS transistor and the gate of the second PMOS transistor; a cross-coupled circuit consisting of a first cross-coupled unit having a first programmable switch and a third PMOS transistor connected in parallel to the first diode-configured PMOS transistor, with a gate connected to the first switch, and a second cross-coupled unit having a second programmable switch and a fourth PMOS transistor connected in parallel to the second diode-configured PMOS transistor, with a gate connected to the second switch; and a differential operational amplifier consisting of a second NMOS transistor with a drain connected to the first switch and the drain of the second diode-configured PMOS transistor, a gate connected to a first voltage, and a source, a third NMOS transistor with a drain connected the second switch and the drain of the first diode-configured PMOS transistor, a gate connected to a second voltage, and a source, and a fourth NMOS transistor with a drain connected to the sources of the second and third NMOS transistors and a gate connected to a third voltage, wherein the first NMOS transistor, the third NMOS transistor, and the first diode-configured NMOS transistor respectively are grounded, and all PMOS transistors respectively have a source connected to an external voltage. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a circuit diagram of a typical OTA;  
         [0011]    [0011]FIG. 2 is a circuit diagram of an OTA according to the invention; and  
         [0012]    [0012]FIG. 3 is a diagram of an output voltage waveform of FIG. 2 when the switches are on and off. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]    The following numbers denote the same elements throughout the description and drawings.  
         [0014]    [0014]FIG. 2 is a circuit diagram of an OTA  20  according to the invention. In FIG. 2, the circuit includes an NMOS current mirror circuit consisting of a first NMOS M 2  with a drain D 2 , a gate G 2  and a diode-configured NMOS M 1  with a drain D 1  and a gate G 1  connected to the gate G 2  of the first NMOS M 2  and the drain D 1  of the diode-configured NMOS M 1 ; two PMOS current mirror circuits consisting of a first PMOS M 3  with a gate G 3  and a drain D 3  connected to the drain D 2  of the first NMOS M 2  to form a connection point A as an output terminal, a second PMOS M 6  with a gate G 6  and a drain D 6  connected to the drain D 1  of the diode-configured NMOS M 1 , a first diode-configured PMOS M 4  with a drain D 4  and a gate G 4  connected the drain D 4  of the first diode-configured PMOS M 4  and the gate G 3  of the first PMOS M 3 , and a second diode-configured PMOS M 5  with a drain D 5  and a gate G 5  connected to the drain D 5  of the second diode-configured PMOS M 5  and the gate G 6  of the second PMOS M 6 ; a cross-coupled circuit consisting of a first cross-coupled unit having a first programmable switch SW 1  and a third PMOS PD 3  connected in parallel to the first diode-configured PMOS M 4 , with a gate GD 1  connected to the first switch SW 1 , and a second cross-coupled unit having a second programmable switch SW 2  and a fourth PMOS PD 4  connected in parallel to the second diode-configured PMOS M 5 , with a gate GD 4  connected to the second switch SW 2 ; and a differential operational amplifier consisting of a second NMOS M 7  with a drain D 7  connected to the first switch SW 1  and the drain D 5  of the second diode-configured PMOS M 5 , a gate G 7  connected to a first voltage IN, and a source S 7 , a third NMOS M 8  with a drain D 8  connected the second switch SW 2  and the drain D 4  of the first diode-configured PMOS M 4 , a gate G 8  connected to a second voltage REF, and a source s 8 , and a fourth NMOS M 9  with a drain D 9  connected to the sources S 7 , S 8  of the second and third NMOSs and a gate G 9  connected to a third voltage BIAS, wherein the first NMOS, the third NMOS, and the first diode-configured NMOS are, respectively, grounded, and all PMOSs respectively have a source connected to an external voltage VCC. The external voltage VCC, the first voltage IN, the second voltage REF and the third voltage BIAS are respectively an external operating voltage providing an operating voltage, an input voltage providing a positive input voltage, a reference voltage providing a negative input voltage and a bias voltage, to control the device M 9  that is a fixed current source, to switch between the devices M 8  and M 9 . The programmable switches SW 1  and SW 2  can be a fuse, a transistor, or a MOSFET.  
         [0015]    As shown in FIG. 2, this circuit, compared to the prior art, adds a cross-coupled unit pair, each including a PMOS transistor and a programmable switch.  
         [0016]    When switches SW 1  and SW 2  are opened (switch off), the circuit acts identically the prior circuit. As such, the circuit can work well in a higher input/output voltage like 3.3V device operated for SSTL-3 system. When switches SW 1  and SW 2  are closed (switch on), because the differential voltage between terminals D 4  and D 5  is increased by the cross-coupled circuit, the external power VCC needs not reach 3.3V when operating the entire circuit in saturation. As such, the external voltage only needs a lower operating voltage as low as 2.5V for 3.3V device operated for SSTL-2 system.  
         [0017]    [0017]FIG. 3 is a diagram of an output voltage of FIG. 2 between the switches are turned on SWon and turned off SWoff. As shown in FIG. 3, for the case of VCC=3.3V (normal voltage) and 2.5V (lower voltage) (the top figure), when a voltage Vin inputs with reference to a constant reference Vref about 1.5V (next one), the circuit is not capable of operation at low voltages as low as 2.5V if the switches are turned off SWoff (next one), otherwise the circuit can operate at low voltages as low as 2.5V and at high voltages as high as 3.3V under the control of the cross-coupled circuit (the bottom one).  
         [0018]    Although the present invention has been described in its preferred embodiment, it is not intended to limit the invention to the precise embodiment disclosed herein. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.