Abstract:
A device to issue an alarm when an operating voltage is below or above a set range includes a detecting circuit, a processing circuit, and a warning circuit. The detecting circuit has first and second predetermined voltages preset and an operating voltage is read from an electronic component. The operating voltage is compared with the set range and the result of comparison is transmitted to the processing circuit. The processing circuit outputs a control signal to the warning circuit according to the comparison signal and the warning circuit outputs warning information. An electronic device including the alarm device is also provided.

Description:
FIELD 
       [0001]    The subject matter herein generally relates to indicator circuits and alarms. 
       BACKGROUND 
       [0002]    There are many electronic components in a computer. If an operating voltage of any one of the electronic components is not in a normal range, the computer may not operate properly. Therefore, whether an operating voltage of each electronic component is in a normal range should be known. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
           [0004]      FIG. 1  is a block diagram of an embodiment of an electronic device of the present disclosure, the electronic device comprising an alarm device. 
           [0005]      FIG. 2  is a block diagram of an embodiment of the alarm device of  FIG. 1 , the alarm device comprising a control unit. 
           [0006]      FIG. 3  is a block diagram of an embodiment of the control unit of  FIG. 2 . 
           [0007]      FIG. 4  is a circuit diagram of a first embodiment of the control unit of  FIG. 3 . 
           [0008]      FIG. 5  is a circuit diagram of a second embodiment of the control unit of FIG.  3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features. The description is not to be considered as limiting the scope of the embodiments described herein. 
         [0010]    Several definitions that apply throughout this disclosure will now be presented. 
         [0011]    The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. 
         [0012]    The connection can be such that the objects are permanently connected or releasably connected. The term “comprising” means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in a so-described combination, group, series and the like. 
         [0013]      FIG. 1  illustrates an embodiment of an electronic device  400  of the present disclosure. The electronic device  400  can comprise an alarm device  100 . The alarm device  100  is electrically coupled to an electronic component  500  of the electronic device  400 , to obtain an operating voltage of the electronic component  500 . In at least one embodiment, the electronic component  500  can be a central processing unit. 
         [0014]      FIG. 2  illustrates an embodiment of the alarm device  100 . The alarm device  100  can comprise a plurality of control units  10 . 
         [0015]      FIG. 3  illustrates an embodiment of the control unit  10 . The control unit  10  can comprise a detecting circuit  20 , a processing circuit  30 , and a warning circuit  40 . Both the detecting circuit  20  and the warning circuit  40  are electrically coupled to the processing circuit  30 . 
         [0016]    In at least one embodiment, the detecting circuit  20  is configured to have a first predetermined voltage and a second predetermined voltage set therein to obtain the operating voltage of the electronic component  500 . The operating voltage so obtained is compared with the first predetermined voltage and the second predetermined voltage, and a comparison signal is output to the processing circuit  30  according to the result of comparison. 
         [0017]    In at least one embodiment, the processing circuit  30  outputs a control signal to the warning circuit  40  according to the comparison signal transmitted by the detecting circuit  20 . 
         [0018]    In at least one embodiment, the warning circuit  40  outputs a warning information according to the control signal transmitted by the processing circuit  30 . 
         [0019]      FIG. 4  illustrates a first embodiment of the control unit  10 . The detecting circuit  20  can comprise a control chipset U 1 , four resistors R 1 -R 4 , and two capacitors C 1  and C 2 . A first voltage pin MTH of the control chipset U 1  is electrically coupled to a power supply VCC through the resistor R 1 , and is electrically coupled to ground through two resistors R 2  and R 3 . A second voltage pin LTH of the control chipset U 1  is electrically coupled to a node between the resistor R 2  and the resistor R 3 . A detecting pin IN of the control chipset U 1  is electrically coupled to ground through the capacitor C 1 , and is electrically coupled to a voltage terminal VCC_ 1  of the electronic component  500  through the resistor R 4 , to obtain the operating voltage from the electronic component  500 . A power supply pin VDD of the control chipset U 1  is electrically coupled to the power supply VCC, and is electrically coupled to ground through the capacitor C 2 . A ground pin GND of the control chipset U 1  is electrically coupled to ground. A signal output pin OUT of the control chipset U 1  is electrically coupled to the processing circuit  30 , to output the comparison signal to the processing circuit  30 . 
         [0020]    The relationship between the first predetermined voltage V 1  of the first voltage pin MTH of the control chipset U 1 , a voltage V of the power supply VCC, and resistance of the three resistors R 1 -R 3  is shown below: 
         [0000]        V 1= V× ( R 2+ R 3)/( R 1+ R 2+ R 3). 
         [0021]    The relationship between the second predetermined voltage V 2  of the second voltage pin LTH of the control chipset U 1 , the voltage V of the power supply VCC, and resistance of the three resistors R 1 -R 3  is shown below: 
         [0000]        V 2= V× ( R 3)/( R 1+ R 2+ R 3). 
         [0022]    If the resistances of the resistors R 1 -R 3  change, the first voltage V 1  of the first voltage pin MTH of the control chipset U 1  and the second voltage V 2  of the second voltage pin LTH of the control chipset U 1  change accordingly. 
         [0023]    The processing circuit  30  can comprise a Schmidt trigger U 2 , a NAND gate U 3 , an inverting trigger U 4 , two capacitors C 3  and C 4 , and three resistors R 5 -R 7 . An input terminal of the Schmidt trigger U 2  is electrically coupled to the signal output pin OUT of the control chipset U 1 , to receive the comparison signal from the control chipset U 1 . A power supply terminal of the Schmidt trigger U 2  is electrically coupled to the power supply VCC, and is electrically coupled to ground through the capacitor C 3 . A ground terminal of the Schmidt trigger U 2  is electrically coupled to ground. An output terminal of the Schmidt trigger U 2  is electrically coupled to a first input terminal of the NAND gate U 3 . A second input terminal of the NAND gate U 3  is floating. A power supply terminal of the NAND gate U 3  is electrically coupled to the power supply VCC, and is electrically coupled to ground through the capacitor C 4 . A ground terminal of the NAND gate U 3  is electrically coupled to ground. An output terminal of the NAND gate U 3  is electrically coupled to a data input pin D of the inverting trigger U 4 . A latch enable input pin LE of the inverting trigger U 4  is electrically coupled to the power supply VCC through the resistor R 5 . A ground pin GND of the inverting trigger U 4  is electrically coupled to ground. A power supply pin PWR of the inverting trigger U 4  is electrically coupled to the power supply VCC through the resistor R 6 . An enable input pin OE of the inverting trigger U 4  is electrically coupled to ground. A latch output pin Q of the inverting trigger U 4  is electrically coupled to the power supply VCC through the resistor R 7 , and is electrically coupled to the warning circuit  40 , to output the control signal to the warning circuit  40 . 
         [0024]    The warning circuit  40  can comprise a light emitting diode (LED) D 1  and a resistor R 8 . A cathode of the LED D 1  is electrically coupled to the latch output pin Q of the inverting trigger U 4 , to obtain the control signal from the inverting trigger U 4 . An anode of the LED D 1  is electrically coupled to the power supply VCC through the resistor R 8 . 
         [0025]    When the second input terminal of the NAND gate U 3  is floating, based on the basic logic circuit principle, the logic level state of the second input terminal of the NAND gate U 3  is at a high level, such as logic 1. 
         [0026]    When the operating voltage of the electronic component  500  detected by the detecting pin IN of the control chipset U 1  is between the first predetermined voltage V 1  and the second predetermined voltage V 2 , the signal output pin OUT of the control chipset U 1  outputs a comparison signal at a low level, to the input terminal of the Schmidt trigger U 2 . The Schmidt trigger U 2  outputs a trigger signal at a high level to the first input terminal of the NAND gate U 3 . Thus, the output terminal of the NAND gate U 3  outputs a signal at a low level to the data input pin D of the inverting trigger U 4 . 
         [0027]    The latch output pin Q of the inverting trigger U 4  outputs the control signal at a high level to turn off the LED D 1 . The LED D 1  is not lit, indicating that the operating voltage of the electronic component  500  is within a normal range. 
         [0028]    When the operating voltage of the electronic component  500  detected by the detecting pin IN of the control chipset U 1  is not between the first predetermined voltage V 1  and the second predetermined voltage V 2 , the signal output pin OUT of the control chipset U 1  outputs the comparison signal at the high level to the input terminal of the Schmidt trigger U 2 . The Schmidt trigger U 2  outputs a trigger signal at low level to the first input terminal of the NAND gate U 3 . Thus, the output terminal of the NAND gate U 3  outputs a signal at the high-voltage level to the data input pin D of the inverting trigger U 4 . The latch output pin Q of the inverting trigger U 4  outputs the control signal at the low level to turn on the LED D 1 . The LED D 1  is lit, indicating that the operating voltage of the electronic component  500  is outside the normal range. 
         [0029]      FIG. 5  illustrates a second embodiment of the control unit  10 . The processing circuit  30  further comprises a switch SW 1 . A first terminal of the switch SW 1  is electrically coupled to the second input terminal of the NAND gate U 3 . A second terminal of the switch SW 1  is electrically coupled to ground. 
         [0030]    When the switch SW 1  is turned on, the second input terminal of the NAND gate U 3  is electrically coupled to ground through the switch SW 1  and the logic level of the second input terminal of the NAND gate U 3  is at a low level, such as logic 0. At this time, the Schmidt trigger U 2  outputs the trigger signal at either a high level or at a low level to the first input terminal of the NAND gate U 3  and the output terminal of the NAND gate U 3  outputs the signal at the low level to the data input pin D of the inverting trigger U 4 . The latch output pin Q of the inverting trigger U 4  outputs the control signal at the high level to turn off the LED D 1 . As detailed above, if switch SW 1  is turned on, the warning circuit  40  is turned off. Thus, regardless of whether the operating voltage of the electronic component  500  is within the normal range or not, the LED D 1  is not lit, and the alarm function of the control unit  10  is turned off. 
         [0031]    When the switch SW 1  is turned off, the second input terminal of the NAND gate U 3  is floating, and the operation principle of the control unit  10  in the second embodiment is then the same as in the first embodiment, and is not repeated here. 
         [0032]    The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of an electronic device. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.