Abstract:
Static read/write memory structures are provided that include predetermined latent-state patterns which can be retrieved with a latent-state retrieve process that differs somewhat from a conventional write process. The patterns are realized with threshold-voltage differences and they significantly enhance flexibility of memory allocation without increasing memory area nor significantly altering conventional read/write processes.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to integrated-circuit memories. 
     2. Description of the Related Art 
     Access to static random access memories (SRAMs) and to read-only memories (ROMs) is required by various integrated circuits (e.g., digital signal processors, microcontrollers and field-programmable gate arrays). These memories are typically supplied as separate and distinct structures and fixed, pre-programmed data is generally stored in the read-only memory with variable data written into and read from the read/write memory. 
     In many applications, read-only memory is accessed infrequently yet it occupies significant integrated-circuit area. In addition, some applications of a specific integrated circuit require increased amounts of read-only memory while other applications require increased amounts of read/write memory and these conflicting needs are often unpredictable and unknown at time of integrated-circuit fabrication. Increasing both the read-only and the read/write memories has been a conventional response to these contrasting needs but this response is expensive and demands valuable integrated-circuit space. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is directed to read/write memory arrays that significantly enhance flexibility of memory allocation without increasing memory area nor significantly altering conventional read/write processes. 
     These goals are realized with a read/write memory that provides predetermined latent-state patterns which are retrieved with a latent-state retrieve process that differs somewhat from a conventional write process. 
    
    
     The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a portion of an array of read/write memory cell embodiments of the present invention; 
     FIG. 2 is an enlarged and detailed diagram of the read/write memory cell within the curved line  2  of FIG. 1; 
     FIG. 3 is an enlarged cross-sectional view through a pull-up transistor of FIG. 2; 
     FIG. 4 is a graph that illustrates a process embodiment of the present invention for recalling a latent state in the read/write memory cell of FIG. 2; 
     FIG. 5 is a block diagram of a memory that includes the array of FIG. 1; and 
     FIG. 6 is a block diagram of a digital signal processor that includes the memory of FIG.  5 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Read/write memory embodiments are described below which provide latent-state patterns that can be retrieved with a latent-state retrieve process. Thus, read-only memory functionality is also provided yet the memory area is not increased nor the read/write functions significantly altered. Accordingly, these embodiments provide significant flexibility to the design, fabrication and use of any integrated circuits that have memory requirements. 
     In particular, FIG. 1 illustrates a portion  20  of a larger array  22  of memory cells  24 . Word lines (e.g., WL 1 ) are arranged so that each accesses a respective row of the array and pairs of bit lines (e.g., bit line BL 1 and its inverse bit line bar BLB 1 ) are arranged so that each pair accesses a respective column of the array. 
     The memory cell  24  that is within the curved line  2  of FIG. 1 is shown in FIG. 2 to have first and second inverters  30  and  31  that each include pull-up and pull-down transistors. In particular, the first inverter  30  has a pull-up transistor  34  and a pull-down transistor  36  and the second inverter  31  has a pull-up transistor  35  and a pull-down transistor  37 . Within each inverter, the pull-up and pull-down transistors are drain-coupled and gate-coupled so that the coupled drains always present a signal that is inverted from a signal on the coupled gates. 
     The first and second inverters  30  and  31  are cross-coupled, i.e., the coupled gates of each of the inverters  30  and  31  is connected to the coupled drains of the other inverter. Accordingly, if the coupled drains of the inverter  30  successively present bit values 0 and 1, the coupled drains of the inverter  31  will successively present bit values 1 and 0. Thus, the memory cell  24  can be urged into either of first and second stable states. 
     The memory cell  24  also includes first and second pass transistors  38  and  39  that are respectively connected to the coupled drains of the first and second inverters  30  and  31 . A word line  40  is coupled to the gates of the first and second pass transistors  38  and  39 , a bit line  42  is coupled to the source of the first pass transistor  38  and a bit line bar  43  (the other of a pair of bit lines of FIG. 1) is coupled to the source of the second pass transistor  39 . In the embodiment of FIG. 2, the pull-up transistors  34  and  35  are p-type metal oxide semiconductor (MOS) transistors and the pull-down transistors  35  and  37  and the pass transistors  38  and  39  are n-type MOS transistors. 
     A first word signal (e.g., a high signal) on the word line will substantially short the first and second pass transistors  38  and  39  to thereby couple signals on the bit lines  42  and  43  to the coupled drains of the first and second inverters  30  and  31  and a different second word signal (e.g., a low signal) on the word line will substantially open the first and second pass transistors  38  and  39  to thereby isolate the first and second inverters. Accordingly, a selected state of the first and second stable states can be written into the memory cell  24  during the presence of the first word signal and the selected state will be maintained during the presence of the second word signal. 
     A conventional write process of the memory cell  24 , for example, begins by applying a bit signal on the bit line  42  and the inverse of that bit signal on the bit line bar  43 . A signal that turns on the first and second pass transistors  38  and  39  is then placed on the word line  40 . In response, the first and second inverters are urged into a selected one of their first and second stable states. 
     When the signal on the word line  40  subsequently turns off the first and second pass transistors, the first and second inverters remain in the selected state. In a subsequent conventional read process, the bit line  42  and bit line bar  43  can be interrogated after the pass transistors  38  and  39  are turned on by an appropriate signal on the word line  40 . 
     The cross-sectional view  50  of FIG. 3 shows that the source  51  and drain  52  of the pull-up transistor  34  are realized with heavily-doped p+ regions that are diffused into an n-type substrate  53  (composed, for example, of silicon). A narrow channel region  54  of the substrate connects the source and drain and is covered by an insulating layer  55  (e.g., silicon dioxide) and a gate electrode  56  (e.g., polysilicon). 
     As is well known, a thin layer of electrons is induced in the channel region  54  when the gate-to-source voltage V gs  reaches a threshold voltage V t . The channel region then forms a conducting channel between the drain  52  and the source  51  and drain current I d  begins to flow through the drain. The magnitude of the drain current increases as the term V gs −V t  increases. 
     During fabrication, therefore, extra p-type impurities are implanted in the channels of the pull-up transistors  34  and  35  of FIG. 2 to realize a nominal threshold voltage V t     nom   . In accordance with the invention, however, additional impurities are subsequently implanted in the channel of a selected one of the pull-up transistors to realize a greater impurity density and, thereby, a greater threshold voltage V t     gtr    that exceeds the nominal threshold voltage V t     nom    and creates a threshold-voltage difference. 
     As indicated in FIG. 2, the coupled drains of the inverters  30  and  31  are respectively referred to as MEM and MEMB. It is noted that the pull-up transistors  34  and  35  will be turned on and the pull-down transistors  36  and  37  will be turned off if a bit value 0 is simultaneously presented through the first and second pass transistors  38  and  39  to both MEM and MEMB. At this time, the pull-up transistors will be coupled to substantially-equal gate-to-source voltages V gs . The selected one of the pull-up transistors  34  and  36  will, however, be conducting a drain current that is related to the term V gs −V t     gtr    and the other will be conducting a greater drain current that is related to the term V gs −V t     nom   . 
     Because of symmetry of the memory cell  24 , substantially-equal parasitic capacitances are associated with the drains of the pull-up transistors  34  and  35  (i.e., MEM and MEMB). When the pass transistors are subsequently turned off, the selected pull-up transistor will, accordingly, charge its respective parasitic capacitance slower than will the other pull-up transistor that is conducting a greater drain current. Because the feedback coupling between the first and second inverters  30  and  31  enhances any initial voltage difference across the stray capacitances, the memory cell  24  will snap into a selected and predictable one of its first and second stable states. 
     In particular, the memory cell  24  will snap into the stable state in which the drain of the selected pull-up transistor is low and the drain of the other pull-up transistor is high. This latent state is realized because of the greater threshold voltage V t     gtr    of the selected pull-up transistor and it will always be retrieved by the latent-state retrieve process described above. 
     The latent-state retrieve process is graphically shown in the graph  60  of FIG. 4 in which it is assumed that the pull-up transistor  34  of FIG. 2 is the selected transistor. That is, the drain current I d  of the pull-up transistor  34  is related to the term V gs −V t     gtr    and the drain current of the pull-up transistor  35  is related to the term V gs −V t     nom   . FIG. 4 indicates that MEM and MEMB (see FIG. 2) are initially in the stable state wherein MEM is high and MEMB is low. The word line WL then transitions from low to high to permit access to the memory cell ( 24  in FIG.  2 ). Bit line BL and bit line bar BLB are subsequently forced to transition from high to low which forces MEM and MEMB to be low also. 
     When the word line WL subsequently transitions from high to low, the memory cell is isolated by virtue of the fact that the pass transistors are off. Because the drain current of the pull-up transistor  35  exceeds the drain current of the pull-up transistor  34 , the memory cell quickly snaps to the implanted latent stable state in which MEM is low and MEMB is high. Once the memory cell has been isolated, the bit line BL and bit line bar BLB may safely transition back to high without affecting the latent state. The previously latent state can then be read by conventional read processes. 
     It is noted that the latent-state retrieve process illustrated in FIG. 4 is similar to a conventional write process. The only difference is that the BL and BLB values are opposite (i.e., one has bit value 0 and the other has bit value 1) during the conventional write process. In an important feature of the invention, the time required by the retrieve process of FIG. 4 is substantially the same as the time required by conventional SRAM read and write processes and that this latter time is substantially unchanged by the threshold-voltage difference of the memory cell  24  of FIG.  2 . 
     As shown by the above description, a read/write memory cell of the invention is fabricated to have a predetermined latent state which is realized with a predetermined threshold-voltage difference in the memory cell&#39;s pull-up transistors. The threshold-voltage difference is oriented to ensure that the memory cell&#39;s inverters attain the predetermined latent state when its pass transistors decouple the inverters from a signal that turns off the pull-down transistors (and turns on the pull-up transistors). This latter process is exemplified in FIG. 4 where the word line WL transitions from high to low to thereby isolate the memory cell ( 24  in FIG. 2) from the bit line BL and bit line bar BLB which are low at this time. 
     FIG. 1 illustrates an exemplary array  22  of the invention in which the memory cells  24  support read/write processes and, in addition, support a read-only process. For illustrative purposes, FIG. 1 shows a predetermined read-only pattern  70  of bit values 0 and 1 in the lower right corner of each memory cell  24 . Because each of the memory cells  24  has a respective cell-position in the array  22  that corresponds with a known bit value, each cell can be provided with a threshold-voltage difference between the threshold voltages V t  of its pull-up transistors which is oriented to ensure that its inverters attain a latent state consistent with the predetermined read-only pattern  70  and the cell&#39;s respective cell-position when the cell&#39;s pass transistors decouple its inverters from a signal that turns off it&#39;s pull-down transistors. 
     Thus, the array  22  has a latent-state pattern that matches the predetermined read-only pattern  70 . When desired, all or a portion of the latent states of the array  22  can be retrieved with the latent-state retrieve process described above with reference to FIG.  4 . Alternatively, data can be written to all or a portion of the array  22  with the conventional write process described above and subsequently, written data can be read with the conventional read process described above. 
     The array that provides the predetermined latent-state pattern can be fabricated with conventional photolithographic processes. These include a process of implanting impurities in the channel regions of the pull-up transistors ( 34  and  35  in FIG. 2) to realize a nominal threshold voltage V t     nom   . Subsequently, a mask is used that defines the channel region of an appropriate pull-up transistor in each memory cell (appropriate to the definition of bit values 0 and 1). 
     With this mask, additional impurities are implanted in the defined channel regions to realize the greater threshold voltages V t     gtr    that provide the predetermined latent-state pattern. It is important to note that this single additional fabrication process does not increase the area of the memory cell so that a read/write memory of the invention contains the same amount of memory (for a given area) as a conventional read/write memory. It is also important to note that this additional fabrication process does not significantly affect the conventional read/write functions of the memory, i.e., it is transparent during conventional read/write functions. 
     Because of the properties of photolithographic fabrication processes, the nominal threshold voltages V t     nom    and parasitic capacitances of a conventional memory cell&#39;s pull-up transistors will be substantially identical and any threshold-voltage difference will be unknown. Accordingly, a conventional memory would only produce a random pattern if subjected to the latent-state retrieve process described above. Because this pattern is random and indeterminable, it has no value. 
     In contrast, a read/write memory of the current invention will provide a predetermined read-only pattern (e.g., the pattern  70  of FIG. 1) in response to the latent-state retrieve process. The read-only pattern can be fabricated to match any desired predetermined pattern. Although a reliable threshold-voltage difference (established by the nominal threshold voltage V t     nom    and the greater threshold voltage V t     gtr   ) can be as small as a few millivolts, it may be desirable to enhance relability by requiring that it have a minimum value, e.g., at least 100 millivolts or, more preferably, at least 200 millivolts. 
     The memory  22  of FIG. 1 may be supplemented with the structures of FIG. 5 which illustrates a memory  80  that adds a row decoder  82 , a column decoder and sense amplifier  84  and a bit-line conditioner  86 . As shown in FIG. 1, the memory  22  is generally organized in rows and columns and the row decoder  82  selectively activates a selected word line (e.g., WL 1 ) to thereby turn on the first and second pass transistors ( 38  and  39  in FIG. 2) of all memory cells in the corresponding row. 
     Similarly, a column decoder in the column decoder and sense amplifier  84  selectively couples output signals (via appropriate bit-line pairs) from the first and second pass transistors of any memory cell in the selected row to a sense amplifier whose output then corresponds to the memory cell&#39;s current state. Alternatively, data can be written into a selected memory cell by placing data on appropriate bit-line pairs with the bit-line conditioner  86 . The bit-line conditioner  86  may also be used to pre-charge selected bit-line pairs to thereby aid in reading cell states with a sense amplifier  84  through the column decoder. 
     Although the memory embodiments of the invention can be used wherever there is a need for read/write and read-only memory, a significant use can be found in digital signal processors such as the processor  90  of FIG.  6 . The processor includes data address generators  92 , a program sequencer  94 , arithmetic units  96 , a memory  98  and input/output (I/O) registers  100 . These structures communicate through a program memory address bus (PMA), a data memory address bus (DMA), a program memory data bus (PMD) and a data memory data bus (DMD). 
     In particular, the data address generators  92  provide memory addresses via the PMA and DMA busses as memory data is interchanged with the. I/O registers  100 . The program sequencer  94  supplies instruction addresses via the PMA bus to the memory  98  in response to program instructions received via the PMD bus. 
     The arithmetic units  96  includes independent computational units. For example, an arithmetic logic unit (ALU) provides arithmetic and logic functions, a multiplier-accumulator (MAC) performs multiply, multiply/add and multiply/subtract functions and a shifter performs logical and arithmetical shifts, normalization and derive-exponent operations. Incoming .data and computational products of the arithmetic units  96  are interchanged with the PMD and DMD busses. 
     The PMA and DMA busses are used internally for addresses associated with program and data memory in the memory  98 . The PMD and DMD busses are use for data associated with the memory  98  and the PMD bus also transfers data to and from the arithmetic units  96 . 
     Significant processing flexibility is added to the processor  90  by structuring all or a portion of the memory  98  with read/write memory embodiments of the present invention. Requirements for the amount of read/write and read-only memory will change as the processor is programmed to execute different objectives. With a memory embodiment of the present invention, corresponding changes can be made in allocation of memory assets. 
     Although memory embodiments have generally been described with reference to the memory cell of FIG. 2, the teachings of the invention can realize a predetermined latent state with any memory cell that includes at least first and second transistors and a threshold-voltage difference between the threshold voltages V t  of the first and second transistors which is oriented to ensure that the memory cell attains the predetermined latent state when the first and second transistors are activated. 
     Although embodiments of the invention have been illustrated with reference to p-type and n-type metal oxide semiconductor transistors, the invention&#39;s teachings can be practiced with any transistors that have current terminals (e.g., collectors) that respond to signals at control terminals (e.g., bases). 
     The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.