Abstract:
A DC to DC power converter (58) and method of controlling the DC to DC power converter (58). The converter (58) has a first switch (S 1 ) coupled to a second switch (S 2 ). The converter (58) is adapted to receive an input voltage V in , generate an output voltage V out , and operate at a switching frequency. A hysteretic mode control circuit (52) includes a first circuit generating a ramp signal at input (56) for controlling the converter (58). The first circuit includes a first capacitor (C 1 ) with the ramp signal generated at an end of the first capacitor (C 1 ). The hysteretic mode control circuit (52) is coupled to the first (S 1 ) and second (S 2 ) switches, where the switching frequency of the first and second switches is dependent upon the ramp signal (56) determined by the value of the components of the first circuit rather than on the voltage from the output filter of the DC to DC power converter. The invention is particularly useful for applications such as DSPs and mixed signal or analog circuits.

Description:
TECHNICAL FIELD OF THE INVENTION 
     This invention relates generally to integrated circuits, and more specifically to a hysteretic mode control regulator for a switching DC to DC converter. 
     BACKGROUND OF THE INVENTION 
     As logic integrated circuits (ICs) have migrated to lower working voltages in the search for lower power consumption and higher operating frequencies, and as overall system sizes have continued to decrease, IC power supply designs with smaller size and higher efficiency are in demand. Switch mode power supplies, or DC to DC converters, as they are sometimes called, are frequently used to supply IC circuits such as digital signal processors (DSPs) and mixed signal analog circuits, etc., to efficiently convert an input supply voltage to voltage levels appropriate for internal circuitry as well as external circuitry that the IC is coupled to. For instance, a 5.0 volt supply voltage provided to a BiCMOS IC may need to be decreased internally to 2.8 volts to operate internal CMOS circuitry. As appliances and circuit designs continue to decrease in size, the need for smaller and more efficient IC switch mode power converters increases. 
     DC to DC converters, as part of the regulated power supplies, are commonly used to provide low ripple and tolerance supplying voltages to electronic systems. Most electronic systems for computer, communication and industrial applications typically include integrated circuits like microprocessors, digital signal processors, memory, for example, which tend to cause high slew rate transients in the entire electronic system. A trend exists in the industry towards lower supply voltages for electronic systems, while the required current from power supply systems is increasing. Optimal control approaches on DC to DC converters are very important to meet tight static and dynamic tolerance requirements while supplying voltages at minimum costs. 
     SUMMARY OF THE INVENTION 
     The present invention achieves technical advantages as a fast transient response hysteretic DC to DC converter having a switching frequency independent from the output filter. In one embodiment, disclosed is a DC to DC power converter having a hysteretic mode control circuit, the converter having a first switch coupled to a second switch and adapted to receive an input voltage, generate an output voltage, and operate at a switching frequency. The control circuit includes a first circuit generating a ramp signal for controlling the converter, with the first circuit having a first capacitor generating the ramp signal at one end. The control circuit includes a hysteretic mode control circuit coupled to the first and second switches. The first circuit is coupled to an input of the hysteretic mode control circuit. The switching frequency of the power converter is dependent on the ramp signal of the first circuit rather than on the output filter of the power converter such as the output voltage. 
     In another embodiment, disclosed is a DC to DC power converter having a first switch coupled to a second switch operating at a switching frequency, and adapted to receive an input voltage, generate an output voltage. An output filter coupled to the output voltage, wherein the output voltage has a ripple. The power converter includes a first circuit generating a ramp signal being greater than the output voltage ripple. The first circuit comprises a first capacitor, with the ramp signal generated at an end of the first capacitor. The power converter includes a hysteretic mode control circuit coupled to the first and second switches and controlling the switching frequency of the first and second switches as a function of the ramp signal determined by the components of the first circuit rather than the output voltage of the output filter, wherein the ripple of the output voltage is reduced. 
     Also disclosed is a method of controlling the output voltage of a DC to DC power converter having a first switch coupled to a second switch operating at a switching frequency. The converter is adapted to receive an input voltage and generate an output voltage. The method includes the steps of generating a ramp signal using a first capacitor coupled to an input of a hysteretic mode control circuit. The method includes the step of using the ramp signal to control the switching frequency, which is dependent on the value of the first capacitor. 
     The present invention is advantageous in providing an efficient hysteretic mode control circuit for a DC to DC converter having excellent load current transient response characteristics. Unlike prior art circuits, the switching frequency of the DC to DC converter is independent from the output filter characteristics. Furthermore, a lower tolerance range is achieved with the present invention, and the voltage output ripple is lower than in prior art circuits. A further advantage is decreased size and lowered cost of the output and input filters due to the use of high frequency, low value capacitors for components of the present circuit. The additional circuit components disclosed herein may be implemented in monolithic integrated circuitry, thus decreasing the number of components, overall circuit size, and total costs. Also, external synchronization of multiple DC to DC converters can be easily implemented in accordance with an embodiment of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings, which form an integral part of the specification and are to be read in conjunction therewith: 
     FIG. 1 illustrates a prior art DC-to-DC convert having a pulse width modulated (PWM) voltage mode control circuit; 
     FIG. 2 illustrates a prior art DC-to-DC convert having a V 2  mode control circuit; 
     FIG. 3 shows another prior art DC-to-DC convert having a hysteretic mode control circuit; 
     FIG. 4 illustrates a schematic diagram of a first embodiment of the present invention with a first feedback resistor R 1  and a first capacitor C 1  that generate an additional ramp signal through the input of the hysteretic comparator 52; 
     FIG. 5 illustrates a schematic diagram of a second embodiment of the present invention having hysteretic comparator 52 with a decoupling capacitor C 2  in series with feedback resistor R 1  to prevent dependence of the output voltage from the R 1  value; 
     FIG. 6 is a schematic diagram of a third embodiment of the present invention with R 1  coupled to buffer 66; 
     FIG. 7 shows a schematic diagram of a fourth embodiment of the present invention with hysteretic comparator 52 and circuit controls I charge  and I discharge  coupled to the first capacitor C 1 , adapted to charge and discharge the first capacitor C 1  ; and 
     FIG. 8 illustrates a fifth embodiment having an external synchronization signal 82 coupled to the input of the hysteretic comparator 52 so that a plurality of DC to DC converters can be operated in parallel or interleaved. 
     Like numerals and symbols are employed in different figures to designate similar components in various views unless otherwise indicated. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Three prior art DC-to-DC converters having voltage mode control circuits will first be discussed, followed by a description of several preferred embodiments of the present invention. 
     A conventional PWM voltage mode control DC to DC converter 10 of the prior art is shown in FIG. 1. In this mode of control, the error amplifier 12 output signal comprises the gained difference between the converter output voltage V out  and reference voltage V ref . The output signal of the error amplifier 12 is compared by comparator 14 with a constant frequency ramp waveform generated by oscillator 20. As a result, the fixed frequency PWM output signal from the comparator 14 controls the on and off time of the power switches S 1  and S 2 , keeping the output voltage V out  constant and independent from the load current and input voltage V in  variations. This prior art voltage mode control configuration has several disadvantages. A careful feedback loop design is required, and the error amplifier usually has three poles, including a zero frequency pole and two zeroes Z 1  and Z 2  to stabilize the converter at all conditions. Moreover, the feedback loop has a narrow frequency bandwidth, and this approach results in poor load current transient characteristics. 
     A DC to DC converter 30 having a V 2  mode control circuit is shown in FIG. 2 and is described in U.S. Pat. No. 5,770,940 issued in June of 1998 to Goder. The control circuitry provides improved load current transient characteristics compared to the prior art circuit of FIG. 1. The voltage ripple signal V out  from the converter output is compared with the output of the error amplifier 32 by comparator 14. The feedback loop includes a slow path, the error amplifier 32 with associated compensation circuitry, and a fast path, the comparator 14 input connected directly to the output voltage V out  of converter. During load current transients, the comparator 14 reacts immediately to the output voltage V out  changes. This control approach improves dynamic characteristics but has several drawbacks. First, the switching frequency and stability of the system greatly depends upon the output filter characteristics, including Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) of the output capacitor C out  and stray inductance and resistance of the supply paths. As a result, the same schematic might have different behavior in designs with a different layout. Second, it is assumed that ESR is dominant in the output ripple waveform, so the output ripple has almost linear ramp waveform. Large, expensive and unreliable electrolytic capacitors are required, to meet this assumption. When small high frequency ceramic or film capacitors are used in this circuit, the output voltage ripple has a waveform approximately equal to a square function of time and has a π/2 phase shift relative the output current ripple, which may cause unstable and unpredictable operation. Third, this approach requires auxiliary logic circuitry 34 to avoid overstressing power switches S 1  and S 2  by restricting maximum on and off times during start up and other transients conditions of the circuit. 
     Another prior art control approach for a DC to DC converter is a hysteretic mode control circuit as shown in FIG. 3. This configuration is also referred to in the art as a ripple regulator or bang-bang regulator. Such a hysteretic mode control has faster transient response characteristics than other control circuits because the control circuitry reacts on the load transient in the same switching cycle. The response time depends only on hysteretic comparator 42 and driver 44 circuitry delays. However, a problem with this control approach is that the switching frequency of the converter is dependent upon the output filter characteristics of C out . Another drawback is that delays during high frequency operation cause the output voltage ripple to exceed the hysteresis window. This results in the output voltage ripple becoming too high. 
     The present invention solves the above problems in the prior art. FIG. 4 shows a schematic diagram of a first embodiment generally shown at 50, including a DC to DC converter 58 with a capacitor C 1  coupled between an input 56 of a hysteretic comparator 52 and ground. A feedback resistor R 1  is connected between the input of hysteresis comparator 52 and a node between power switches S 1  and S 2  of the DC to DC converter 58. The R 1  /C 1  feedback circuitry generates a time constant and generates an additional ramp signal at the input 56 of the hysteretic comparator 52. Two signals are summed by the comparator 52 through the input 56: one being the ramp signal generated by the R 1  /C 1  circuitry, and the other being the signal V out  generated by the output of converter 58. The additional ramp signal applied in the first embodiment 50 to the hysteretic comparator 52 input 56 is achieved by adding resistor R 1 , which is connected between the input 56 of the comparator 52 and a node between the power switches S 1  and S 2 , in combination with additional capacitor C 1  connected between the input 56 of the comparator 52 and ground. Resistor R 2  is coupled between the input 56 of the comparator 52 and the node at V out , and resistor R 3  is coupled between the input 56 and ground. 
     By proper selection of the values of R 1  and C 1 , an amplitude of the additional ramp signal may be obtained that is greater than the output ripple at V out  of the converter 58. As the result, the switching frequency of the switches S 1  and S 2  of the converter 58 is increased, while the output ripple is lowered. The switching frequency of the converter 58 now depends on the values of resistor R 1  and capacitor C 1  of the control circuitry, rather than depending on the output filter characteristics including the ESR, ESL and capacitance C of the output capacitor C out , as in the prior art. Furthermore, the DC feedback signal established by R 1  from the output of the converter controls the DC level of the output voltage V out . Because the switching frequency does not depend on the output capacitor C out  characteristics, high frequency, low cost ceramic or film capacitors may be used in the DC to DC converter while having excellent load current transient response characteristics. The switching frequency for the first embodiment may be evaluated by the following equation: ##EQU1## where &#34;Hyst&#34; is the hysteresis window of the hysteretic comparator 52. The output voltage may be evaluated by the following equation: ##EQU2## 
     A second embodiment generally shown at 60 of the present invention including the DC to DC converter 58 is shown in FIG. 5. As in the first embodiment, a capacitor C 1  is coupled between the input to hysteretic comparator 52 and ground, and a feedback resistor R 1  is connected between the input of hysteresis comparator 52 and the node between power switches S 1  and S 2  of the DC to DC converter 58. The R 1  /C 1  circuitry forms and generates an additional ramp signal at the input 56 of the hysteretic comparator 52. In addition, a decoupling capacitor C 2  is coupled in series with R 1 . The value of C 2  is preferably much higher than C 1 , for example, 10 times the value of C 1 . The decoupling capacitor C 2  prevents the output voltage V out  from significantly depending on the value of resistor R 1 , a feature which may be desirable in some circuit designs. The switching frequency for the second embodiment may be evaluated by the following equation: ##EQU3## The output voltage may be evaluated by the following equation: 
     
         Equation 4: V.sub.out =V.sub.ref *(1+R.sub.2 /R.sub.3) 
    
     Both the first and second embodiments 50 and 60 improve the input voltage transient response and line regulation of the output voltage V out , because the slope of the ramp signal generated by R 1  /C 1  at 56 depends on the input voltage V in  and gives a feed-forward effect to the control circuitry. Although the line transient response and line regulation of V out  are improved, the switching frequency of the converter 58 remains dependent from the input voltage V in  due to the additional ramp signal generated by R 1  /C 1 . 
     In a third embodiment shown generally at 64, resistor R 1  is connected to the output of a buffer circuit 66, as shown in FIG. 6. The input of the buffer circuit 66 is connected to the node common to transistors S 1  and S 2 . The amplitude of the output pulses from the buffer 66 is constant and independent of V in . Thus, the operating frequency of the converter is independent from V in . The equation describing the operating frequency for this embodiment is: ##EQU4## where V cc  is the peak amplitude of the buffer 66 output. In this embodiment, the line regulation of the converter is somewhat degraded because of the absence of feedforward signal from the input supply. 
     A fourth embodiment 70 of the present invention is shown to include the DC to DC converter circuit 58 of FIG. 7 having a capacitor C 1  coupled between the input to hysteretic comparator 52 and ground. The control circuitry further includes current sources I charge  and I discharge  coupled to capacitor C 1  and an amplifier 74. Current source I charge  is adapted to charge capacitor C 1  when the first power switch FET S1 of the DC to DC converter is on. At this time, current source I discharge  is disconnected from C 1 . Similarly, when the second power switch FET S 2  is on, the current source I discharge  discharges the capacitor C 1 , while the current source I charge  is disconnected from C 1 . The values of the current sources I charge  and I discharge  define the slope and rise/fall times of the ramp voltage at input 56 through capacitor C 1 . By setting the I charge  and I discharge  currents to constant values, the operating frequency of the switches S 1  and S 2  of the DC to DC converter 58 remains independent of the input and output operating characteristics of the converter 58 including the output filter, but the output voltage V out  line regulation is not reduced. Alternatively, current source I charge  may be set proportional to (V in  -V out ) and current source I discharge  may be set proportional to V out , for example, resulting in the line regulation of the output voltage V out  being improved. However, in this configuration, the operating frequency of the DC to DC converter 58 varies with the input voltage V in . 
     A fifth embodiment of the present invention is generally shown at 80 in FIG. 8 and includes DC to DC converter circuit 58 similar to the second embodiment, with resistor R 1  and capacitors C 1  and C 2 . In addition, an external synchronization signal 82 is also coupled to the input 56 of the hysteretic comparator 52. The switching frequency of converter 58 is independent from the output voltage V out . This synchronization signal 82 is advantageous in some electronic systems where it may be important to synchronize the operating frequency of DC to DC converters to an external clock source for parallel operation, for interleaving several converters, or to avoid certain frequency ranges due to system issues, for example. Because the switching frequency of the improved hysteretic controller does not depend on the output filter characteristics, a plurality of different DC to DC converters can be synchronized with this configuration using synchronization signal 82. 
     The present invention is advantageous in providing an efficient hysteretic mode control circuit for a DC to DC converter having excellent load current transient response characteristics. Unlike prior art circuits, the switching frequency of the DC to DC converter is independent from the output filter characteristics. Furthermore, a lower tolerance range is achieved with the present invention, and the voltage output ripple is lower than in prior art circuits. A further advantage is decreased size and lowered cost of the output and input filters due to the use of high frequency, low value capacitors for components of the present circuit. The additional circuit components C 1 , R 1 , and C 2  disclosed herein may be implemented in monolithic integrated circuitry, thus decreasing the number of components, overall circuit size, and total costs. Also, the external synchronization of multiple DC to DC converters may be easily implemented in accordance with the fourth embodiment of the present invention. The frequency of the DC to DC converter may also be kept constant in accordance with the present invention. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, the hysteretic mode control circuit for a DC to DC power converter of the present invention may be utilized with a power converter in a wide variety of applications, such as digital signal processors, microprocessors, telecommunications applications, mobile devices and systems, laptops and personal computers, mixed signal and analog devices, and any lower power electrical application, in general.