Abstract:
Provided is a delay locked loop comprising: a delay unit for delaying a clock supplied from an external chipset by a predetermined delay amount; a replica for delaying the clock delayed in the delay unit by a delay amount of a clock path and a data path; and a phase detector for generating a signal for controlling the delay amount of the delay unit comparing the clock supplied from the external chipset with a phase of an output of the replica, and generating a reset signal through detection of a change of a clock frequency supplied from the external chipset.

Description:
[0001]     This application relies for priority upon Korean Patent Application No. 2003-82457 filed on Nov. 20, 2003, the contents of which are herein incorporated by reference in their entirety.  
       BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a delay locked loop (DLL) of a semiconductor memory device and, more specifically, to a delay locked loop capable of detecting a change of a clock frequency supplied from a chipset and resetting a phase detector.  
         [0004]     2. Discussion of Related Art  
         [0005]     Generally, in a semiconductor memory device operating synchronized with an external clock signal, in case where an internal clock signal is delayed for a constant time comparing with the external clock signal, the high frequency operation performance of the semiconductor memory device is deteriorated. Especially, a time when data is outputted after application of the external clock signal, i.e., an output data access time (tAC) is increased. Therefore, in order to prevent the high frequency operation performance of the semiconductor memory device form being deteriorated, a circuit is required to precisely synchronize a phase of the internal clock signal to a phase of the external clock signal, and a delay locked loop is generally used for it. In addition, the delay locked loop is widely used for a clock recovery system, a precise time-to-digital conversion, and high-speed serial links, etc.  
         [0006]     Meanwhile, according to an application, one of an analog DLL, a digital DLL and a hybrid DLL may be used. Especially the analog DLL has good jitter characteristics, while it has an essential problem that it is locked in a False State that an internal clock signal is delayed by more than one period with respect to a reference clock signal, for example, an external clock signal. The False State locking is not preferable due to Jitter Accumulation and increased Noise Susceptibility.  
         [0007]     Also, the delay locked loop is used to generate clocks having negative delay characteristics of CMOS VLSI circuit and DRAM, etc. The delay locked loop functions to cause an output of data to be coincident with the external clock as the delay locked loop receives the external clock, compensates a delay component of a clock path and a data path, and outputs a signal leading the external clock.  
         [0008]     The external clock inputted to a circuit such as DRAM, etc. is applied from a chipset such as a memory controller, and so on. When the frequency of the external clock is varied, the delay locked loop has a high possibility of a malfunction. Thus, there is a problem in that the data output is not synchronized to the clock.  FIG. 1  is a block diagram of a conventional delay locked loop.  
         [0009]     A delay unit A delays an external clock by a predetermined amount and outputs it.  
         [0010]     A replica B is a copy of the clock path and data path, and the negative delay amount of the delay locked loop is determined according to the amount. A phase detector C functions to compare the external clock with the phase of the external clock passing through the delay unit A and the replica B. A clock driver D functions as a driver that supplies the delayed clock delayed in the delay unit A with other circuits.  
         [0011]     An operation principle of the delay locked loop of  FIG. 1  will be explained in detail below with reference to  FIG. 2 .  
         [0012]     In case where a clock CLOCK is inputted to the delay unit A from an external chip, the delay unit A delays the clock CLOCK and generates a delayed clock CLOCK_D. The delayed clock CLOCK_D is inputted to the replica B. The replica B delays the delayed clock CLOCK_D by a delay amount of the clock path and data path, and generates a clock feedback signal CLOCK_FEEDBACK. The phase detector C sends the delay unit A a signal to increase a delay amount of the delay unit A until a phase of the clock CLOCK is identical to a phase of the clock feedback signal CLOCK_FEEDBACK. Through these processes, when the clock CLOCK and the clock feedback signal CLOCK_FEEDBACK are coincident with each other, the delay unit A is locked and a delay synchronous clock signal DLL_CLK is generated. As a result, it is possible to compensate the delay component of the clock path and data path, and output data DATA synchronized with the external clock CLOCK.  
         [0013]      FIG. 3  shows a detailed circuit of the prior art phase detector, and  FIG. 4  shows a timing chart for describing the operation thereof.  
         [0014]     Initially, a delay amount of the delay unit A is set to “0”, the clock feedback signal CLOCK_FEEDBACK generates a signal lagging by a delay amount of the replica B, comparing with the clock CLOCK. At this time, the phase detector C compares the phase at a rising edge of the clock CLOCK. For example, at a time T 1 , an output of a NAND gate is low. An output CMP_EN of a NOR gate maintains a high state until a signal passing a delay unit  10  and an inverter G 2  becomes high. During the time T 1 , one output node N 1  of a latch  20  maintains the low state and another output node N 2  maintains the high state. An output N 3  of a NAND gate G 3  becomes high and output N 4  of NAND gate G 4  becomes low. Therefore, an output SHIFT_RIGHT of a latch  30  becomes high. If the output SHIFT_RIGHT is the high state, the delay amount of the delay unit A is increased. If an output SHIFT_LEFT thereof is the high state, the delay amount of the delay unit A is decreased. With repeating these processes, if the phase of clock CLOCK and the phase of the clock feedback signal CLOCK_FEEDBACK are coincident with each other, a phase of a signal DLL_LOCK showing that the delay locked loop is locked becomes high. This situation is the same as the timing chart of  FIG. 2 , and the clock feedback signal CLOCK_FEEDBACK has a phase lagging by a delay amount D of the delay unit A and a delay amount of the replica B, comparing with the clock CLOCK. Namely, if the delay locked loop is locked, D+T=1T (T: clock period). Therefore, the output of the delay unit A has a phase leading by a delay amount R of the replica B, comparing with the phase of the clock, as shown in  FIG. 2 .  
         [0015]     Typically, if the delay locked loop is locked, in order to be insensitive to a voltage variation of an external power supply, a circuit is installed to perform a limiting function so that the variation of the delay amount does not occur. At this time, if a frequency of the clock CLOCK inputted from the external chipset is abruptly increased, the phase of the clock CLOCK and the phase of the clock feedback signal CLOCK_FEEDBACK, which are initially identical to each other as shown in  FIG. 5 , are not coincident with each other. Thus, the output data DATA is not coincident with the phase of the clock CLOCK. This problem is continuously maintained before the delay locked loop is reset.  
         [0016]     In general, a semiconductor circuit is reset by a power up signal generated when all semiconductor circuits are powered up when the semiconductor circuit is powered up. Namely, since the conventional delay locked loop is a structure reset by both a power up signal PWRUP generated when powering up and a self refresh operation signal, so that, even though, the phase of the clock CLOCK and the phase of the clock feedback signal CLOCK_FEEDBACK, which has initially been coincident with each other do not become coincident by a change of the clock, the delay locked loop can not be reset as long as a power up signal is not newly supplied.  
       SUMMARY OF THE INVENTION  
       [0017]     The present invention is directed to a delay locked loop to be reset to the initial state when a frequency of the clock applied from an external chipset is varied.  
         [0018]     According to a preferred embodiment of the present invention, a delay locked loop comprises: a delay unit for delaying a clock supplied from an external chipset by a predetermined delay amount; a replica for delaying the clock delayed in the delay unit by a delay amount of a clock path and a data path; and a phase detector for generating a signal for controlling the delay amount of the delay unit in comparison of the clock supplied from the external chipset with a phase of an output of the replica, and generating a reset signal through detection of a change of a clock frequency supplied from the external chipset.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]      FIG. 1  is a schematic block diagram showing a prior art delay locked loop;  
         [0020]      FIG. 2  is a time chart for explaining the operation of the prior art delay locked loop of  FIG. 1 ;  
         [0021]      FIG. 3  is a detailed circuit diagram of a phase detector of  FIG. 1 ;  
         [0022]      FIG. 4  is a timing chart for explaining the operation of the phase detector of  FIG. 3 ;  
         [0023]      FIG. 5  is a timing chart for explaining problems of the prior art delay locked loop;  
         [0024]      FIG. 6  is a detailed circuit of a phase detector employed in a delay locked loop according to the present invention; and  
         [0025]      FIGS. 7 and 8  are timing charts for explaining the operation of  FIG. 6 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0026]     Referring to the drawings, a delay locked loop in accordance with the present invention will be explained in detail below.  
         [0027]     The construction of the delay locked loop of the present invention is the same as that of the prior art of  FIG. 1  except for the phase detector. Therefore, the phase detector will be explained as follows.  
         [0028]      FIG. 6  is a detailed circuit of a phase detector employed in a delay locked loop according to the present invention, which will be explained in detail referring to  FIGS. 7 and 8 .  
         [0029]     Referring to  FIG. 6 , the phase detector of the present invention comprises a phase detecting unit  6 A and a DLL resetting unit  6 B. The phase detecting unit  6 A is implemented as the same of  FIG. 3 .  
         [0030]     The DLL resetting unit  6 B according to the present invention generates a DLL reset signal DLL_RESET using a clock CLOCK and a clock feedback signal CLOCK_FEEDBACK.  
         [0031]     1. In the Case where a Clock Frequency is not Changed  
         [0032]     Initially, a delay amount of the delay unit A is set to “0”, the clock feedback signal CLOCK_FEEDBACK generates a signal lagging by a delay amount of the replica B, comparing with the clock CLOCK. At this time, the phase detector C compares phases at a rising edge of the clock CLOCK.  
         [0033]     Since the clock CLOCK is not identical to the clock feedback signal CLOCK_FEEDBACK at the initial time, an output of a NAND gate G 6  is a low state. Until a signal passing a delay unit  40  and an inverter G 7  is the high state, an output CMP_EN of a NOR gate G 8  maintains a high state. During this time, an output node N 1  of a latch  70  maintains the low state and an output node N 2  maintains the high state. An output N 7  of a NAND gate G 9  becomes high, and an output N 8  of a NAND gate G 10  becomes low. Therefore, an output SHIFT_RIGHT of a latch  80  becomes high. If the output SHIFT_RIGHT is the high state, the delay amount of the delay A is increased. If an output SHIFT_LEFT is the high state, the delay amount of the delay unit A is decreased. Through these processes, the phase of the clock CLOCK and the clock feedback phase CLOCK_FEEDBACK are identical to each other, and a signal DLL_LOCK showing that the delay locked loop is locked becomes high.  
         [0034]     2. In the Case where a Clock Frequency is Increased  
         [0035]     In case that the frequency of the clock CLOCK supplied from the external chipset is abruptly increased as shown in  FIG. 7 , even though the phase of the clock CLOCK and the phase of the clock feedback signal CLOCK_FEEDBACK are identical to each other, the phase of the clock feedback signal CLOCK_FEEDBACK abruptly leads the phase of the clock CLOCK after the clock period is increased. The clock feedback CLOCK_FEEDBACK is constantly delayed in a delay unit  50  and then converted to a delayed clock feedback signal CLOCK_FEEDBACK_D 2 . Namely, the phase of the delayed clock feedback CLOCK_FEDBACK_D 2  leads comparing with the phase of the clock CLOCK. Therefore, an output node N 3  of a latch  90  becomes low and an output node N 4  becomes high. An output N 9  of a NAND gate G 11  becomes high and an output N 10  of a NAND gate G 12  becomes low. Since an output SR_LOWFREQ of a latch  100  becomes high, an output of an OR gate G 15  becomes high. Since the lock signal DLL_LOCK was the high state, an output DLL_RESET of a NAND gate N 16  becomes high. Therefore, the delay locked loop is reset to the initial state. At this time, the delay amount of the delay unit  50  is determined according to the operated system and the circuit.  
         [0036]     3. In the Case where a Clock Frequency is Decreased  
         [0037]     A frequency of the clock CLOCK supplied from the external chipset is abruptly decreased as shown in  FIG. 8 , even though the phase of the clock CLOCK and the phase of the clock feedback signal CLOCK_FEEDBACK are identical to each other, the phase of the clock feedback signal CLOCK_FEEDBACK abruptly lags the phase of the clock after the clock period is increased. The clock CLOCK is constantly delayed in a delay unit  60  and then converted to a delayed clock CLOCK_D 2 . Namely, the phase of the delayed clock CLOCK_D 2  is led, comparing with the phase of the clock feedback signal CLOCK_FEEDBACK. Therefore, an output node N 5  of a latch  110  becomes high, and an output node N 6  becomes low. An output N 11  of a NAND gate G 13  becomes low and an output N 12  of a NAND gate G 14  becomes high. Since an output SL_HIGHWFREQ of a latch  120  becomes high, the output of the OR gate G 15  becomes high. Since the lock signal DLL_LOCK was the high state, an output DLL_RESET of a NAND gate G 16  becomes high. Therefore, the delay locked loop is reset to the initial state. The output DLL_RESET is connected to a terminal of the delay locked loop, which is not shown in the drawings. Preferably each of the lathes  70 ,  80 ,  90 ,  100 ,  110  and  120  is implemented by an SR flip-flop.  
         [0038]     Here, the delay amount of the delay unit  60  is determined according to the operated system and the circuit.  
         [0039]     From the principle above, the malfunction of the delay locked loop can be prevented by resetting the delay locked loop in response to the abrupt change of the frequency of the clock supplied from the external chipset.  
         [0040]     Meanwhile, even though the preferred embodiment of the present invention is implemented by considering both of the increase and the decrease of the clock frequency, we can readily appreciate that it can be modified to reset by either the increase or the decrease of the clock frequency.  
         [0041]     Also, in consideration of circuit design, even though the reset means for the DLL is implemented to be included in the phase detector, we can easily appreciate that the reset means for the DLL can be separately installed there from, which is also modified from the present invention.  
         [0042]     According to the forgoing description of the present invention, if the period of the clock supplied form the external chipset is abruptly increased or decreased from a normal state as the delay locked loop is reset and locked again, the malfunctions of the internal circuit and the output data can be prevented.  
         [0043]     While the present invention has been described with reference to the illustrative embodiments, various modifications of the illustrative embodiments will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.