Abstract:
A light-emitting diode chip package and a manufacturing process thereof sequentially includes a transparent layer, a fluorescent layer, a wafer layer, a light-emitting diode chip, a dielectric layer, a metal circuit layer, and a protective film and conductive blocks used to draw out the electrodes of the light-emitting diode chip. The outer surfaces of the fluorescent layer and the wafer layer retreat from the fluorescent layer down to the wafer layer to form a slant, and the dielectric layer, the metal circuit layer, and the protective film spread out to coat the slant. Simple techniques at low cost are involved.

Description:
FIELD 
       [0001]    The subject matter herein generally relates to the field of chip packages, and particularly to light-emitting diode chip packages and methods for manufacturing light-emitting diode chip packages. 
       BACKGROUND 
       [0002]    As shown in  FIG. 1 , a conventional white light-emitting diode (LED) chip package formed by a blue LED and a phosphor layer includes an LED chip  3  and a substrate  5 . The LED chip  3  is soldered on the substrate  5  via a convex element  6 . A light-emitting surface of the LED chip  3  is coated with a phosphor layer  2  and then sealed with a silicone lens  1 , gaps between the LED chip  3  and the substrate  5  being filled with filler  4 . A number of processes are involved in manufacturing the white LED chip package, including preparing a substrate  5 , manufacturing a convex element  6 , soldering an LED chip  3  to the substrate  5  with the convex element  6 , coating a phosphor layer  2  to the LED chip  3 , and formation of silicone lens  1  and others. On account of the complex manufacturing process, the investment cost for the manufacturing equipment is high, meanwhile the white LED chip package takes up much more real estate on a printed circuit board than the LED chip  3 . 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout several views. 
           [0004]      FIG. 1  is a view illustrating a conventional white LED chip package. 
           [0005]      FIG. 2  is a schematic view of a light-emitting diode chip package of the disclosure. 
           [0006]      FIG. 3  is a partially enlarged view of portion A of the light-emitting diode chip package in  FIG. 2 . 
           [0007]      FIG. 4  is a partial schematic view of a light-emitting diode chip package of the disclosure during manufacturing. 
           [0008]      FIG. 5  schematically illustrates a process step in an embodiment for manufacturing light-emitting diode chip package of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure. 
         [0010]    The term “comprising”when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
         [0011]    As shown in  FIG. 2  and  FIG. 3 , a light-emitting diode chip package provided in an embodiment of the disclosure sequentially includes a transparent layer  10 , a fluorescent layer  20 , a wafer layer  40 , a light-emitting diode chip C, a dielectric layer  90 , a metal circuit layer  100 , a protective film  120 , and a plurality of conductive blocks  110  along a predetermined direction. The conductive blocks  110  are used to draw out the electrodes of the light-emitting diode chip C and to assemble pins thereto. Outer surfaces of the fluorescent layer  20  and the wafer layer  40  are shrunk from the fluorescent layer  20  to the wafer layer  40  and form a slant S. The dielectric layer  90 , the metal circuit layer  100 , and the protective film  120  are extended to cover the slant S. To facilitate understanding, the predetermined direction is shown as direction D in  FIG. 2 , and in this case, the light-emitting diode chip C is a GaN-based light-emitting diode chip sequentially formed by a GaN layer  50 , an n-type GaN layer  60 , a quantum layer  70 , and a p-type GaN layer  80  along the direction D. The light-emitting diode chip C is provided with gaps corresponding to the conductive blocks  110 . The dielectric layer  90 , the metal circuit layer  100 , and the protective film  120  respectively define openings corresponding to the gaps to expose the conductive blocks  110 , to achieve electrical connection to external components via the conductive blocks  110 . The light-emitting diode chip C can be chosen from numerous and various structures similar to those described above. 
         [0012]    In the embodiment of the disclosure, the transparent layer  10  is used as a supporting and light-transmitting unit. The monochromatic light emitted from the light-emitting diode chip C can be converted into white light after passing through the fluorescent layer  20  due to the mechanism of fluorescence. The dielectric layer  90  is provided to prevent short-circuits on the wafer layer  40 . The outer surfaces of the fluorescent layer  20  and the wafer layer  40  retreat along the direction D to form a slant S. The slant S can be used as a reflector with the metal circuit layer  100  and the protective film  120  coated on it, so that the light striking the slant S may have a greater chance to be reflected to the light emergent side This will contribute in increasing the efficiency of the light-emitting diode chip, as well as in preventing the color temperature or saturation of the emergent light being affected by light leakage. Moreover, the metal circuit layer  100  can also be used as a reflector when bonded to the wafer layer  40 , to further reduce the loss of light when transmitting. In an illustrated embodiment, the slant S is V-shaped, which can be easily achieved by line or linear cutting. It is understood that the slant S can also be shaped in other declining plane or surface. 
         [0013]    In the illustrated embodiment, the wafer layer  40  can be a sapphire layer. The fluorescent layer  20  is a light conversion layer with a phosphor-mixed ratio. The monochromatic light emitted from the light-emitting diode chip of a sapphire layer can be converted into white light on passing through the fluorescent layer  20 . The color temperature or saturation of the emergent light can be adjusted by changing the kinds of phosphorescent materials, or the mixing ratio of phosphorescent materials, or the thickness of the fluorescent layer  20 . 
         [0014]    The protective film  120  can be made of silicon oxide, silicon nitride, or a combination of them to form a passivation layer for protecting the metal circuit layer  100 . The metal circuit layer  100  can be compounded by multi-layers of patterned metal wires. 
         [0015]    As shown in  FIG. 4  and  FIG. 5 , a method for manufacturing light-emitting diode chip packages comprises the following steps. 
         [0016]    In step S 1 , growing parts are deposited along a predetermined direction on a wafer layer  40  to form a light emitting diode chip C. In an illustrated embodiment, the light-emitting diode chip C is a GaN-based light-emitting diode chip, in which case the step S 1  specifically comprises step S 101  and step S 102  as follows. 
         [0017]    In step S 101 , a GaN layer  50 , an n-type GaN layer  60 , a quantum layer  70 , and a p-type GaN layer  80  are sequentially grown along the predetermined direction on a wafer layer  40 ; 
         [0018]    In step S 102 , fixing gaps are opened by etching the GaN layer  50 , the n-type GaN layer  60 , the quantum layer  70 , and the p-type GaN layer  80  to draw out the electrodes of the light-emitting diode chip C. 
         [0019]    In step S 2 , a transparent layer  10  is bonded to the wafer layer  40 , wherein the transparent layer  10  is precoated with a fluorescent layer  20 . In an embodiment, the transparent layer  10  can be bonded to the wafer layer  40  via a bonding layer  30  disposed between them. Alignment equipment is not necessary since there is no precision alignment required in the bonding procedure. The transparent layer  10  and the wafer layer  40  may align with each other by their edges. 
         [0020]    In step S 3 , outer surfaces of the fluorescent layer  20  and the wafer layer  40  are cut to form a slant S so as to retreat along the predetermined direction. The slant S may be in V-shaped, which can be easily processed by linear cutting, or the slant S may also be shaped in another declining plane or surface, as long as the light striking the slant S is reflected to the light emergent side. 
         [0021]    In step S 4 , a dielectric layer  90 , a metal circuit layer  100  and a protective film  120  are sequentially coated on the slant S along the predetermined direction. The slant S can be used as a reflector together with the metal circuit layer  100 . 
         [0022]    In step S 5 , conductive blocks  110  are formed on the wafer layer  40  to draw out the electrodes of the light-emitting diode chip C. The conductive blocks  110  may be formed by soldering or bumping process, or by gold lugs soldered to the wafer layer  40 . 
         [0023]    In an exemplary embodiment of the disclosure, the wafer layer  40  in the step S 1  may be a sapphire wafer slice. Cutting positions are preset on the fluorescent layer and the wafer layer in step S 3  in accordance with the required dimensions of a light-emitting diode chip package, and further step S 6  after step S 5  is as follows. 
         [0024]    In step S 6 , individual light-emitting diode chip packages are obtained by laser cutting or blade cutting at the preset cutting positions. A fracturing procedure may also be involved after the cutting, thereby reducing the clamping processes and improving the productivity. The cutting positions and the fixing gaps can be formed at same time in the step S 1 . 
         [0025]    In another exemplary embodiment of the disclosure, a step S 401  is comprised between the step S 4  and the step S 5  as follows. 
         [0026]    In step S 401 , a traceability mark may be added to the protective film  120  to confer traceability on the light-emitting diode chip packages. The traceability mark can be formed by laser printing or lithographic printing. 
         [0027]    The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of a light-emitting diode chip. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, including in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.