Abstract:
A circuit ( 200 ) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN 1,  CN 2,  CP 1,  CP 2 ) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

Description:
PRIORITY CLAIM TO INTERNATIONAL PATENT APPLICATION  
         [0001]    This patent application claims priority to French Patent Application Number 01 09190 filed on Jul. 11, 2001.  
         TECHNICAL FIELD OF THE INVENTION  
         [0002]    The invention relates to a clock circuit protected against voltage or current spikes. The invention relates especially to any integrated circuit of which at least one element uses a clock signal for its operation, such as for example (but not exclusively) flip-flop type circuits, latch type circuits or, more generally, logic circuits using a clock signal.  
         BACKGROUND OF THE INVENTION  
         [0003]    The constant and gradual miniaturization of electronic circuits is giving rise to increasingly efficient and ever smaller circuits. This means, however, that the circuits are becoming increasingly sensitive to their environment and especially to logic random events caused by an additional supply of energy from outside the circuit.  
           [0004]    A logic random event is a specific change in state or a transitional state (voltage and/or current spike) at the point of an integrated circuit. By definition, a random event is unpredictable or hardly predictable. Logic random events may have different origins.  
           [0005]    A logic random event is induced, for example, by the impinging of a charged energy article on a point of an integrated circuit. A random factor of this time is known as a “single event upset” or SEU. This type of random event appears in integrated circuits used for space applications, because of radiation encountered outside the earth&#39;s protective atmospheric and magnetospheric layers. This type of random event is also increasingly frequent in integrated circuits for terrestrial applications, especially for the finer technologies such as the 0.25 μm, 0.18 μm and 0.12 μm technologies.  
           [0006]    A logic random event may also be induced by localized capacitive coupling between two layers of one and the same integrated circuit. In this case, the term “glitch” is often used.  
           [0007]    A random event, whatever its cause, is generally expressed by a voltage and/or current spike on a digital or analog signal at a disturbed point of the circuit (a point of impingement in the case of an SEU, a coupling point in the case of a glitch, etc.).  
           [0008]    If C denotes the equivalent capacitance of the circuit downstream from the disturbed point of the circuit, then the variation in voltage ΔV at the disturbed point considered is written ΔV=ΔQ/C, ΔQ being the variation in charge resulting from the impingement or the coupling.  
           [0009]    A random event may have consequences of varying importance for the circuit that it disturbs.  
           [0010]    For example, for a downstream circuit using only logic signals, if the voltage variation ΔV is small enough to cause no change in the state of the disturbed logic signal, then the disturbance disappears in a fairly short time without any consequence for the downstream circuit.  
           [0011]    If, on the contrary, the voltage variation ΔV is greater, and especially if it is sufficient to modify the value of the logic signal, then the consequences may be great: a random event may thus cause an inverter to switch over or a SRAM type memory cell to get reprogrammed etc.  
           [0012]    The clock circuit of an integrated circuit is generally constituted (FIG. 1) by a tree-like structure comprising different arms  111  to  117  enabling the supply, by a single initial CI, of all the elements  121  to  128  of the integrated circuit. Buffers (most usually inverter amplifiers)  131  to  139  are generally placed along the different arms of the clock circuit in order to control firstly the reductions in the level of the signal due to losses along the arms and, secondly, phase differences generated by the different lengths of arms.  
           [0013]    The consequences of a random event on a circuit such as the clock circuit may be great since it may disturb several elements of the circuit simultaneously, depending on the arm of the clock circuit on which the random event appears. Indeed, a random event on an arm of the clock circuit may cause for example a switching or dual switching of the clock signal supplying one or more elements of the integrated circuit. A first consequence thereof is that these elements get desynchronized from the other elements of the integrated circuit. A second consequence is that the downstream circuits could be modified: there could be a change in the state of a memory, a flip-flop circuit etc.  
           [0014]    In practice, for a buffer located far upstream from the clock circuit, for example the buffer  131 , the capacitive charge at output of this buffer is great because it is constituted by the sum of the capacitive charges of the circuits downstream from the buffer considered. Consequently, a random event appearing at the input of an upstream buffer does not disturb the downstream circuits because the associated variation in voltage ΔV is low or even very low, the capacitive charge C being high.  
           [0015]    On the contrary, for a buffer located far downstream from the clock circuit or even at the input of an element of the integrated circuit, such as for example the buffers  134 ,  125 , the resulting capacitive charge C is low. Therefore, a random event appearing at the input of a downstream buffer is transmitted to the output of this buffer, and it is liable to disturb the working of the downstream circuit or circuits if they are not protected.  
           [0016]    It is therefore indispensable to protect the clock circuit of an integrated circuit to prevent any disturbance of the downstream circuits using the clock signal.  
         SUMMARY OF THE INVENTION  
         [0017]    It is an object of the invention to propose a circuit for protection against random events.  
           [0018]    It is another object of the invention to propose a clock circuit using a protection circuit of this kind.  
           [0019]    It is also an object of the invention to propose a clock circuit producing identical or inverse synchronous clock signals to limit the risk of the cumulative disturbance of several signals simultaneously.  
           [0020]    With these goals in view, the invention relates to a protection circuit to receive an initial clock signal and send at least one resultant clock signal to a downstream circuit.  
           [0021]    According to the invention, the protection circuit comprises:  
           [0022]    an input circuit receiving the initial clock signal and producing two intermediate clock signals that are images of the initial clock signal,  
           [0023]    a recombination circuit to give a first resulting clock signal that is:  
           [0024]    the image of the intermediate signals if said intermediate signals are identical, or  
           [0025]    inactive if the intermediate signals are different from each other.  
           [0026]    The term “inactive signal” should be understood here to be a signal that does not disturb a downstream circuit, the output of the recombination circuit that produces it being, in this case, a high-impedance circuit.  
           [0027]    The invention also relates to a clock circuit for an integrated circuit comprising a protection circuit such as the one described here above.  
           [0028]    Thus, if a random event disturbs the working of the protection circuit according to the invention, then an inactive clock signal is given at output of the protection circuit. The disturbance is not transmitted to the downstream circuit: the operation of the downstream circuit is blocked for a few instants until the disappearance of the disturbance. There is therefore no risk of an undesired operation of the downstream circuit.  
           [0029]    Preferably, the protection circuit is connected between a downstream circuit using a clock signal and the end of an arm of the clock circuit giving the clock signal to the downstream circuit. The point of the clock circuit most sensitive to the random events is thus protected.  
           [0030]    The input circuit used for the protection circuit according to the invention comprises:  
           [0031]    a first buffer comprising an input to which the initial clock signal is applied, and an output to give one of the intermediate clock signals,  
           [0032]    a second buffer comprising an input connected to the input of the first buffer and an output to give the other one of the intermediate signals.  
           [0033]    The input circuit thus separates the initial clock signal into two intermediate clock signals which are identical in normal operation of the circuit. The first buffer and second buffer are preferably distant from each other in the drawing of the circuit. Thus the same random event cannot simultaneously disturb both buffers. Thus, if a random event disturbs the circuit then only one of the intermediate clock signals is liable to be disturbed.  
           [0034]    The recombination circuit of the protection circuit that is an object of the invention, for its part, comprises a first complex inverter comprising a first input and a second input to receive respectively both of the intermediate signals, and an output at which the first resultant clock signal is given. As will be seen more clearly hereinafter in a description of an exemplary embodiment, the first complex inverter produces a first resultant clock signal which is:  
           [0035]    the inverse of the intermediate clock signals when these signals are identical,  
           [0036]    inactive (or at high impedance) if they are different.  
           [0037]    Thus, a disturbance appearing at one of the intermediate signals is not transmitted to the resultant signal, which is momentarily inactive. The term “inactive signal” must be understood here to mean a signal that does not disturb a downstream circuit. In practice here, when the intermediate clock signals are different, the first complex inverter is off so that its output is at high impedance: the resultant signal is thus kept at its previous value because of the presence of a low capacitance at output of the first inverter, which is inherent in the inverter.  
           [0038]    According to a preferred embodiment of the invention, the recombination circuit also comprises a second complex inverter, comprising a first input and a second input to respectively receive both the intermediate signals, and an output at which a second resultant clock signal is given.  
           [0039]    The first and second complex inverters are preferably identical, so that the first resultant signal and second resultant signal are identical if the protection circuit is not disturbed by a random event. If, on the contrary, a disturbance appears then it disturbs only one of the two resultant signals and the other one can be used by the downstream circuit.  
           [0040]    Preferably again, as a complement to the first complex inverter and the second complex inverter, the recombination circuit comprises a third complex inverter, comprising a first input and a second input to respectively receive the first resultant clock signal and the second resultant clock signal, and an output at which a third resultant clock signal is given.  
           [0041]    The third resultant clock signal is:  
           [0042]    the inverse of the first resultant signal if the first resultant signal and the second resultant signal are identical,  
           [0043]    inactive if not.  
           [0044]    According to this embodiment, in normal operation, there are thus three signals available at output of the protection circuit, the third signal being complementary to the first two. If, on the contrary, the circuit is disturbed, then at most two of the resultant signals are at high impedance, and the third one therefore remains available.  
           [0045]    According to another embodiment, as a complement to the first complex inverter and the second complex inverter, the recombination circuit comprises a first simple inverter comprising an input to receive the first resultant clock signal and an output at which the third resultant clock signal is given, the first simple inverter also comprising:  
           [0046]    a fifth P type transistor receiving a power supply voltage at a source, and  
           [0047]    a sixth N type transistor, a drain of which is connected to a drain of the fifth transistor, and a source of which is connected to the ground of the circuit,  
           [0048]    a gate of the fifth transistor and a gate of the sixth transistor being connected together to the input of the first simple inverter, the common drain of the fifth transistor and of the sixth transistor being connected to the output of the first simple inverter.  
           [0049]    The recombination circuit also preferably comprises a second simple inverter comprising an input to receive the second resultant clock signal and an output at which a fourth resultant clock signal is given.  
           [0050]    According to this embodiment, there are four resultant clock signals available at output of the recombination circuit. In normal operation, they are identical in sets of two. If, on the contrary, a random event appears, then only a restricted number of output signals is inactive. The other output signals can be used is by the downstream circuit.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0051]    The invention will be understood more clearly and other features and advantages shall appear from the following description of exemplary embodiments of a clock circuit according to the invention. The description is made with reference to the appended drawings, of which:  
         [0052]    [0052]FIG. 1 shows a functional diagram of a known clock circuit of an integrated circuit,  
         [0053]    [0053]FIG. 2 shows an embodiment of a protected buffer according to the invention, and  
         [0054]    FIGS.  3  to  5  show exemplary embodiments of an element of the circuit of FIG. 2.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0055]    The circuit  200  of FIG. 2 is a buffer protected against the random events according to the invention. It has an input  201  to which the initial clock signal CI is applied, and three outputs at which resultant signals CN 1 , CN 2 , CP 1  are given.  
         [0056]    The circuit  200  comprises an input circuit  210  and a recombination circuit  220 . The input circuit produces two intermediate clock signals CK 1 , CK 2  from the initial clock signal CI. The recombination circuit combines the intermediate clock signals CK 1 , CK 2  to obtain the resulting clock signal CN 1 :  
         [0057]    CN 1  is the inverse of CK 1  if CK 1  and CK 2  are identical.  
         [0058]    CN 1  is inactive (high impedance) if CK 1  and CK 2  are different from each other.  
         [0059]    Thus, if the signals CK 1 , CK 2  are not disturbed by a random event, then they are identical and the recombination circuit gives a resultant signal CN 1  which is the inverse of CK 1 . On the contrary, if either of the signals CK 1  or CK 2  is disturbed by a random event, then the resulting signal CN 1  is at high impedance. The signal CN 1  will then take a value that is the inverse of that of CN 1  as soon as the disturbance has ended.  
         [0060]    It must be noted that if the signals CK 1  and CK 2  were to be disturbed simultaneously, then the disturbance would be transmitted on the signal CN 1 . However, this signal is almost non-existent inasmuch as it assumes that two random events of equal importance disturb the integrated circuit, simultaneously and at two distinct points of the integrated circuit.  
         [0061]    The circuit  220  also gives the signal CN 2 , which has the same properties as CN 1 , and the signal CP 1 , which has the following properties:  
         [0062]    CP 1  is equal to CK 1  if CK 1  and CK 2  are identical,  
         [0063]    CP 1  is inactive (at high impedance) if CK 1  and CK 2  are different from each other.  
         [0064]    It must be noted that, in a simplified embodiment, the buffer  200  gives a single signal CN 1 . A flip-flop type circuit uses, for example, two complementary clock signals CN, CP but other logic circuits use only one or, on the contrary, more than two of them. The number of clock signals produced by the circuit  200  is thus a function of the use made thereof in the downstream circuits.  
         [0065]    The input circuit  210  comprises two buffers  211 ,  212 . The buffer  211  has one input to which the signal CI is applied, and one output; the buffer  211  produces the intermediate signal CK 1 . The buffer  212  comprises one input connected to the input of the buffer  211  and, at an output, it gives the second intermediate signal CK 2 .  
         [0066]    The buffers  211 ,  212  herein are simple inverters, giving a signal at output that is the inverse of the signal that they receive at their input. The signals CK 1 , CK 2  obtained here are therefore identical if they are not disturbed by a random event.  
         [0067]    The inverters may be replaced by any type of buffer that can be used to propagate and, if necessary, amplify and/or phase-shift a received signal, for example in a clock circuit: inverter or non-inverter buffer, buffer comprising several series-connected inverters, buffer memory, flip-flop circuit etc.  
         [0068]    The recombination circuit  220  comprises two inputs  221 ,  222  connected respectively to the output of the buffer  211  and to the output of the buffer  213 . At outputs  223  to  225 , the recombination circuit produces the resultant clock signals CN 1 , CN 2 , CP 1 .  
         [0069]    The recombined signals given by the circuit  200  are independent of each other and their number varies as a function of the requirements of the downstream circuit using them and/or as a function of the degree of overall protection of the integrated circuit to be obtained.  
         [0070]    [0070]FIG. 3 is a first exemplary embodiment of a circuit  220  that produces three resultant signals CN 1 , CN 2 , CP 1  from the signals CK 1 , CK 2 .  
         [0071]    The circuit has three complex inverters  310 ,  320 ,  330 .  
         [0072]    The complex inverter  310  has two inputs  311 ,  312 , to which the signals CK 1 , CK 2  are applied, and one output at which a signal CN 1  is provided.  
         [0073]    The complex inverter  310  has two P type transistors T 1 , T 2  and two N type transistors T 3 , T 4  that are series-connected. A power supply voltage VDD is applied to a source of the transistor T 1  which has a drain connected to a source of the transistor T 2 . A source of the transistor T 3  is connected to the drain of the transistor T 4 , a source of which is connected to a ground of the circuit.  
         [0074]    A gate of the transistor T 1  and a gate of the transistor T 3  are connected together to the input  311 ; a gate of the transistor T 2  and a gate of the transistor T 4  are connected together to the input  312 . Finally, a drain of the transistor T 2  and a drain of the transistor T 3  are connected together to the output  313 .  
         [0075]    The complex inverter  310  works as follows:  
         [0076]    If CK 1  and CK 2  are identical, then:  
         [0077]    if CK 1 =CK 2 =0, then T 3 , T 4  are off and T 1 , T 2  are on simultaneously and CN 1  is equal to VDD, i.e. it is equal to a logic “1”, or  
         [0078]    if CK 1 =CK 2 =1, then T 1 , T 2  are off and T 3 , T 4  are on simultaneously: CN 1  is equal to GND, i.e. it is equal to a logic “0”.  
         [0079]    Inversely, if CK 1  and CK 2  are different from each other, then the transistors T 1 , T 2  or T 3 , T 4  are never on simultaneously, and the output  313  remains indeterminate, at high impedance.  
         [0080]    The complex inverter  310  in fact produces the resultant clock signal CN 1 , which is the inverse of CK 1  (if CK 1  and CK 2  are identical) or inactive (if CK 1  and CK 2  are different from each other).  
         [0081]    The complex inverter  320  has two inputs  321 ,  322  to which the signals CK 1 , CK 2  are applied. The circuit  320  produces a second resultant clock signal CN 2  at an output  323 . The circuit  320  is made similarly to the complex inverter  310 , and it therefore works in similarly: CN 2  is the inverse of CK 1  if CK 1  and CK 2  are identical, or CN 2  is at high impedance if CK 1  and CK 2  are different from each other.  
         [0082]    It will be noted that, since the inverters  310 ,  320  are identical, the signals CN 1 , CN 2  are identical in normal operation. If, on the contrary, one of the signals CK 1  or CK 2  is disturbed, then the signals CN 1 , CN 2  are both at high impedance, in an indeterminate state. It will also be noted that, if a random event disturbs the working of either of the inverters  310  or  320 , then only one of the signals CN 1  or CN 2  is at high impedance, the other signal remaining undisturbed.  
         [0083]    The complex inverter  330  has two inputs  331 ,  332  respectively connected to the output  313  of the inverter  310  to receive the signal CN 1 , and to the output  323  of the inverter  320  to receive the signal CN 2 . The circuit  330  produces a third resultant clock signal CP 1  at an output  333 .  
         [0084]    The circuit  330  is made similarly to the complex inverter  310 , and therefore works similarly:  
         [0085]    CP 1  is the inverse of CN 1  if CN 1  and CN 2  are identical  
         [0086]    CP 1  is inactive (at high impedance) if CN 1  and CN 2  are different from each other.  
         [0087]    It will be noted that, if CN 1  or CN 2  is disturbed (both cannot be disturbed at the same time), then CP 1  is at high impedance.  
         [0088]    [0088]FIG. 4 is a second exemplary embodiment of a circuit  220  according to the invention, which produces four resultant signals CN 1 , CN 2 , CP 1 , CP 2  from the signals CK 1 , CK 2 . The circuit has a complex inverter  410 , and three simple inverters  420 ,  430 ,  440 .  
         [0089]    The complex inverter  410  has two inputs  411 ,  412 , to which the signals CK 1 , CK 2  are applied and an output  413  at which the signal CN 1  is given. The circuit  410  is made similarly to the complex inverter  310 , and therefore works similarly: CN 1  is the inverse of CK 1  if CK 1  and CK 2  are identical, or CN 1  is at high impedance if CK 1  and CK 2  are different from each other.  
         [0090]    The simple inverter  420  has an input  421  connected to the output  413  of the inverter  410 , and an output  422  at which the signal CP 1  is produced. Here, the signal CP 1  has the following value:  
         [0091]    CP 1  is the inverse of CN 1  if CN 1  is active,  
         [0092]    CP 1  is inactive (at high impedance) if CN 1  is inactive.  
         [0093]    The simple inverter  430  comprises a connected input  431  to which the signal CK 1  is applied and an output  432  at which the signal CN 2  is produced. The signal CN 2  has the following value:  
         [0094]    CN 2  is the inverse of CK 1  if CK 1  is active,  
         [0095]    CN 2  is inactive (at high impedance) if CK 1  is inactive.  
         [0096]    The simple inverter  440  has an input  441  connected to the output  432  of the inverter  410 , and an output  432  at which the signal CP 2  is produced. The signal CP 2  has the following value:  
         [0097]    CP 2  is the inverse of CN 2  if CN 2  is active,  
         [0098]    CP 2  is inactive (at high impedance) if CN 2  is inactive.  
         [0099]    Thus, in this example:  
         [0100]    if the signals CK 1 , CK 2  and the elements  410 ,  420 ,  430 ,  440  are not disturbed, then CN 1 =CN 2  and these two signals are the inverse of CK 1 =CK 2 , and CP 1 =CP 2 =CK 1 .  
         [0101]    if the signal CK 1  or the signal CK 2  is disturbed by a random event, then the signals CN 2 , CP 2  are disturbed but the signals CN 1 , CP 1  are at high impedance; this makes it possible to turn off the downstream circuits.  
         [0102]    [0102]FIG. 5 shows a third exemplary embodiment of a circuit  220 , which produces four resultant signals CN 1 , CN 2 , CP 1 , CP 2  from the signals CK 1 , CK 2 . The circuit has two complex inverters  510 ,  520  and two simple inverters  530 ,  540 .  
         [0103]    The complex inverter  510  has two inputs  511 ,  512  to which the signals CK 1 , CK 2  are applied and an output  513  at which the signal CN 1  is given. The circuit  510  is made similarly to the complex inverter  310 , and therefore works similarly: CN 1  is the inverse of CK 1  (if CK 1  and CK 2  are identical) or CN 1  is at high impedance (if CK 1  and CK 2  are different from each other).  
         [0104]    The complex inverter  520  has two inputs  521 ,  522  to which the signals CK 1 , CK 2  are applied and one output  523  at which the signal CN 2  is given. The inverter  520  is made similarly to the complex inverter  510 , and therefore works similarly: CN 2  is the inverse of CK 1  (if CK 1  and CK 2  are identical) or is at high impedance (if CK 1  and CK 2  are different from each other).  
         [0105]    The simple inverter  530  has an input  531  connected to the output  513  of the inverter  510 , and an output  532  at which the signal CP 1  is produced. The signal CP 1  has the following value:  
         [0106]    CP 1  is the inverse of CN 1  if CN 1  is active,  
         [0107]    CP 1  is inactive (at high impedance) if CN 1  is inactive.  
         [0108]    The simple inverter  540  comprises an input  541  connected to the output  523  of the inverter  520 , and an output  542  at which the signal CP 2  is produced. The signal CP 2  has the following value:  
         [0109]    CP 2  is the inverse of CN 2  if CN 2  is active,  
         [0110]    CP 2  is inactive (at high impedance) if CN 2  is inactive.  
         [0111]    As can be seen in the examples of FIGS.  2  to  5 , a buffer  200  protected according to the invention has the following characteristics: if a random event appears at a point of the circuit  200 , or if one of the intermediate clock signals CK 1 , CK 2  or the initial clock signal CI is disturbed by a random event, then at least one of the resultant clock signals CN 1 , CN 2 , CP 1 , CP 2  is at high impedance. The operation of the downstream circuits can therefore be turned off in a localized way during the disturbance.  
         [0112]    Thus, a disturbance appearing at a point of the circuit  200  or else upstream from this circuit is never transmitted to the downstream circuits which are thus protected by the circuit  200 .