Abstract:
A switching controller or regulator (implemented as an integrated circuit) which is operable in any selected one of multiple two modes, including an oscillator mode in which it generates switch control signals for turning on a power switch in response to internally generated clock pulses, a sync mode in which it generates the switch control signals in response to pulses supplied from external circuitry, and preferably also a shutdown mode in which it consumes little or no power and does not generate switch control signals. In the oscillator and sync modes, the controller or regulator also generates additional control signals for turning off the power switch each time after it is turned on, so as to regulate the duty cycle of the power switch. Preferably, the controller or regulator chip has only a single external pin for receiving control signals for causing the chip to enter a sequence of the available operating modes, and it includes a level shifter, a sync timer, a shutdown timer, and a controllable oscillator, all connected to such pin. A multiplexer, operating under control of the sync timer, receives the outputs of the level shifter and oscillator, and selects one of these outputs in response to a control signal from the sync timer. Other aspects of the invention are a DC-to-DC converter including a switching controller or regulator chip of the described type and circuitry external to the chip for generating a regulated output potential in response to an input potential, and a method for performing DC-to-DC conversion using any embodiment of the switching controller or regulator chip.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to switching power supply circuitry. Specifically, the invention relates to a switching controller or regulator (implemented as an integrated circuit) for use in a DC-to-DC converter in which a power switch switches on in response to &#34;on&#34; signals from the controller or regulator chip (and in which the power switch switches off in response to &#34;off&#34; signals from the controller or regulator chip), where the controller or regulator chip is operable in any selected one of at least two modes, including a mode in which the chip generates the &#34;on&#34; signals in response to internally generated clock pulses, and another mode in which the chip generates the &#34;on&#34; signals in response to pulses supplied from external circuitry. 
     2. Description of the Related Art 
     FIG. 1 is a conventional DC-to-DC converter which includes current mode switching controller 1 which is implemented as an integrated circuit, and boost converter circuitry external to controller chip 1. The boost converter circuitry comprises NMOS transistor N1 (which functions as a power switch), inductor L, current sense resistor R s , Schottky diode D, capacitor C out , feedback resistor divider R F1 , and R F2 , compensation resistor R c , and compensation capacitor C c , connected as shown. The FIG. 1 converter produces a regulated DC output voltage V out  across load R o , in response to input DC voltage V in . 
     Controller chip 1 includes oscillator 2 (having a first output and a second output), comparator 8, driver 6 which produces an output potential V DR  at pad 12 (to which the gate of switch N1 is coupled), latch 4 (having &#34;set&#34; terminal coupled to oscillator 2, &#34;reset&#34; terminal coupled to the output of comparator 8, and an output coupled to the input of driver 6), error amplifier 10 (having a non-inverting input maintained at reference potential V ref ), and circuit 9 (having a first input coupled to the second output of oscillator 2, a second input coupled to pad 13, and an output coupled to the inverting input of comparator 8). 
     Pad 13 is at potential V c , which is determined by the output of error amplifier 10 (in turn determined by the difference between the instantaneous potential at Node A and the reference potential V ref ) and the values of external resistor R c  and capacitor C c . Reference potential V ref  is set (in a well known manner) by circuitry within chip 1, and is normally not varied during use of the circuit. In order to set the regulated level of the output voltage V out , resistors R F1  and R F2  with the appropriate resistance ratio R F1  /R F2  are employed. 
     Oscillator 2 asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positive-going leading pulse edge of this pulse train sets latch 4. Each time latch 4 is set, a control signal asserted by driver 6 (the potential V DR  asserted by driver 6 to the gate of transistor N1) causes transistor N1 to turn on, which in turn causes current I L  from the source of N1 to increase in ramped fashion. Although transistor N1 turns on at times in phase with the periodic clock pulse train, it turns off at times (which depend on the relation between reference potential R ref  and the instantaneous potential at Node A) that have phase that is independent relative to that of the pulses of the periodic clock pulse train. 
     Oscillator 2 asserts ramped voltage V osc  (which periodically increases at a fixed ramp rate and then decreases with a waveform as indicated) at its second output. Circuit 9 asserts the potential V c  -V osc  to the inverting input of comparator 8. Assertion of the potential V c  -V osc  (rather than V c ) to comparator 8 is necessary for stability. 
     The non-inverting input of comparator 8 is at the feedback potential V s  =I L  R s , which increases in ramped fashion in response to each &#34;set&#34; of latch 4 by oscillator 2. When V s  =V c  -V osc  (after latch 4 has been set), the output of comparator 8 resets latch 4, which in turn causes the potential V DR  asserted by driver 6 to the gate of transistor N1 to turn off transistor N1. Thus, by the described use of both signals output from oscillator 2 and feedback asserted to error amplifier 10 from Node A, controller chip 1 switches transistor N1 on and off with timing that regulates the output potential V out  of the FIG. 1 circuit. 
     Other conventional DC-to-DC converters which include a current mode switching controller implemented as an integrated circuit (as does the FIG. 1 circuit) also include circuitry (e.g., buck converter circuitry) other than boost converter circuitry that is external to the controller chip. Typical buck controller circuitry differs from the boost converter circuitry of FIG. 1 in that it includes an NMOS transistor (replacing NMOS transistor N1 of FIG. 1) whose source is coupled through an inductor to the output node (whereas in FIG. 1 the drain of transistor N1 is coupled through diode D to the output node, and inductor L is coupled between the input potential V in  and the source of N1), a Schottky diode connected between ground and the source of N1 (replacing diode D of FIG. 1), a sense resistor connected between the input potential V in  and the drain of the transistor (rather than between ground and the source of N1 as in FIG. 1), and a boost capacitor coupled between the controller chip and the source of the transistor. 
     We shall use the expression &#34;switching regulator&#34; chip herein to denote a circuit which performs the functions of a &#34;switching controller&#34; chip but which also includes an on-board power switch. In contrast, a &#34;switching controller&#34; chip does not include an on-board power switch and must be used with an external power switch (as controller chip 1 of FIG. 1 is used with an NMOS transistor N1 which is external to chip 1). Switching controller chip 1 of FIG. 1 is an example of a &#34;current mode&#34; switching controller chip. There are other types of switching controller and regulator chips (such as voltage mode switching controllers) which can be implemented in accordance with the invention, some of which work without an external sense resistor while others require an external sense resistor. 
     Some conventional DC-to-DC converters differ from the conventional circuit of FIG. 1 in that they include a current mode switching regulator chip in place of a current mode switching controller chip. The current mode switching regulator chip in each such converter does not include a sense resistor, and instead is used with an external sense resistor (such as resistor R s  of FIG. 1). For example, one such converter employs a current mode switching regulator chip that differs from chip 1 of FIG. 1 in that counterparts to NMOS transistor N1 and resistors R f1  and R f2  are implemented on-board the regulator chip. In this type of converter, the circuitry external to the regulator chip does not include an external power switch, but it does include an external sense resistor (e.g., an external sense resistor identical to resistor R s  of FIG. 1). 
     It would be desirable to implement improved versions of conventional switching regulator (or controller) chips, in which the improved controller or regulator chip is operable in any selected one of at least two modes, including an oscillator mode in which the improved chip generates switch control signals (for turning on a power switch) in response to internally generated clock pulses, and a sync mode in which the chip generates the switch control signals in response to pulses supplied from external circuitry. For example, the pulses supplied from external circuitry could occur periodically at a user-specified frequency, or they could be indicative of a user-specified synchronization waveform. It would also be desirable for such an improved controller or regulator chip to enter a shutdown mode (in which it consumes little or no power, and does not generate switch control signals) in response to an externally supplied control signal. However, until the present invention it had not been known how to implement such an improved controller (regulator) chip so that only a single external pin is required to send control signals to the chip to cause it to enter either of the oscillator and sync modes (or any of the oscillator, sync, and shutdown modes). 
     SUMMARY OF THE INVENTION 
     In a class of embodiments, the invention is a switching controller or regulator (e.g., a current mode switching controller or regulator) implemented as an integrated circuit which is operable in any selected one of at least two modes, including an oscillator mode in which it generates switch control signals (for turning on a power switch) in response to internally generated clock pulses, and a sync mode in which it generates the switch control signals in response to pulses supplied from external circuitry. In each of the oscillator and sync modes, the controller (or regulator) also generates additional switch control signals for turning off the power switch (which is typically an NMOS transistor) each time after it is turned on, so as to regulate the duty cycle of the power switch. In preferred embodiments, the controller (or regulator) chip is operable (in response to externally supplied control signals) in any selected one of three modes: a shutdown mode (in which it consumes little or no power, and does not generate switch control signals); an oscillator mode (of the mentioned type); and a sync mode (of the mentioned type). 
     Preferably the controller (or regulator) chip is implemented to have only a single external pin for receiving the control signals which cause the chip to enter any of its operating modes (e.g., the oscillator and sync modes, or the oscillator, sync, and shutdown modes), and each sequence of control signals which cause the chip to enter a sequence of the available operating modes. In preferred embodiments, the inventive controller (regulator) chip includes a level shifter, a sync timer, a shutdown timer, and a controllable oscillator, all connected in parallel with the external control pin. A multiplexer (operating under control of the sync timer) receives the outputs of the level shifter and controllable oscillator, so that either of these outputs can be passed through the multiplexer in response to a control signal from the sync timer. In some embodiments, the controllable oscillator asserts a clock pulse train whose frequency is determined by the value of an external resistor coupled to the chip&#39;s external control pin. 
     Another aspect of the invention is a DC-to-DC converter which includes a switching controller or regulator chip of any of the types mentioned in the previous paragraph, and circuitry (typically including a current sense resistor) external to the controller or regulator chip for generating a regulated DC output potential in response to a DC input potential. 
     The invention is especially useful where it is impractical or undesirable to implement a controller (or regulator) chip with more than a single pin dedicated for connection to both external mode control circuitry and external circuitry for supplying power switch setting pulses. 
     For convenience, the expression &#34;switching controller&#34; integrated circuit (or chip) is used in the claims to denote an integrated circuit in the broad class of integrated circuits consisting of both switching regulators (each including an on-board power switch) and switching controllers (which do not include on-board power switches, but are used with external power switches to perform the same functions performed by current mode switching regulators). The invention pertains both to current mode switching controller chips and other switching controller chips (such as voltage mode switching controller chips), and to switching controller chips which work without external sense resistors as well as switching controller chips which require external sense resistors. 
     Another aspect of the invention is a method for performing DC-to-DC conversion using any embodiment of the inventive switching controller (or regulator) chip and external circuitry coupled to the controller (or regulator) chip. The method includes the step of asserting control signals to a single pin of the controller (or regulator) chip to cause the chip to operate in a sequence of selected ones of at least two modes, including an oscillator mode in which the controller (or regulator) chip generates switch control signals (for turning on a power switch) in response to internally generated clock pulses, a sync mode in which the controller (or regulator) chip generates the switch control signals in response to pulses supplied from external circuitry, and preferably also a shutdown mode in which the controller (or regulator) chip consumes little or no power, and does not generate switch control signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional DC-to-DC converter including external boost controller circuitry, but including no soft start circuitry. 
     FIG. 2 is a block diagram of elements of a preferred embodiment of a current mode switching controller designed in accordance with the present invention. 
     FIG. 3 is a set of waveforms generated by (and supplied to) controller chip 102 of FIG. 2 in typical operation (other than in a shutdown mode). 
     FIG. 4 is a set of waveforms generated by (and supplied to) controller chip 102 of FIG. 2 during transitions from the oscillator mode to the shutdown mode and from the shutdown mode to the oscillator mode. 
     FIG. 5 is a set of waveforms generated by (and supplied to) controller chip 102 of FIG. 2 during transitions from the sync mode to the shutdown mode and from the shutdown mode to the sync mode. 
     FIG. 6 is a schematic diagram of a DC-to-DC converter which includes a regulator chip (regulator chip 103) designed in accordance with the present invention. 
     FIG. 7 is a schematic diagram of a DC-to-DC converter which includes a controller chip (controller chip 104) designed in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the inventive current mode switching controller (implemented as an integrated circuit) will be described with reference to FIG. 2 (and the waveforms shown in FIGS. 3-5). Then, a variation on controller chip 102 of FIG. 2 will be described with reference to FIG. 6, and a DC-to-DC converter which includes another variation on controller chip 102 of FIG. 2 will be described with reference to FIG. 7. 
     Controller chip 102 of FIG. 2 is identical to controller chip 101 of FIG. 1, except in that it includes oscillator 20 (which replaces oscillator 2 of FIG. 1) and includes the following elements that are not present in chip 101: external pin 25, level shifter 21, sync timer 22, shutdown timer 23, and multiplexer 24, connected as shown in FIG. 2. 
     Current mode switching controller chip 102 asserts, at the output of multiplexer 24, &#34;set pulses&#34; (for a latch such as latch 4 of FIG. 1) either in response to signals generated (at a frequency specified by an external signal received at pin 25) by internal oscillator 20, or signals (generated by level shifter 21) which are replicas of an externally generated synchronization waveform received at pin 25. Chip 102 is also configured to enter a shutdown mode in response to an externally generated shutdown control signal received at pin 25. 
     Thus, in response to signals received at single external pin 25, controller chip 102 enters any of the following three operating modes: 
     1. an &#34;oscillator mode,&#34; in which &#34;set pulses&#34; are generated by oscillator 20. Oscillator 20 is configured to assert at its output a clock pulse train having frequency F, where F is proportional to the inverse of the resistance of external resistor R 1  (which is coupled to pin 25) when external potential V p  is ground potential. The pulses of this clock pulse train are the &#34;set pulses,&#34; which are used for periodically setting latch 4 (shown in FIG. 1) so as to trigger the periodic switching on of a power switch. In the oscillator mode, multiplexer 24 is controlled (in response to a control bit from sync timer 22) to pass through the set pulses from oscillator 20 to the &#34;set&#34; terminal of latch 4; 
     2. a &#34;sync&#34; mode, in which level shifter 21 generates &#34;set pulses&#34; by translating the levels of externally generated pulses that are asserted to pin 25 (to CMOS logic levels, for example), so that the set pulses output from level shifter 21 are replicas of the externally generated pulses; and 
     3. a &#34;shutdown&#34; mode, in which controller 102 powers down and is put in a state in which it does not assert control signals to a power switch (for turning the power switch off and on) and draws no more than a very small bias current on the order of 10 μA. 
     With reference to FIG. 2, V p  is an external voltage which is applied to pin 25 of controller chip 102 through external resistor R 1 . 
     Pin 25 is at potential V i . 
     The output of sync timer 22 is a control signal (labeled &#34;sync out&#34; in FIG. 2) indicative of a logical 1 if V i , the potential at a first input of timer 22, is less than reference potential V r1  (asserted to the other input of timer 22) for a time longer than T 1 . Otherwise, the output of sync timer 22 is a control signal indicative of a logical 0. Oscillator 20 is enabled when the output of sync timer 22 indicates a logical 1, and is disabled when the output of sync timer 22 indicates a logical 0. Also, the output of sync timer 22 is asserted to multiplexer 24. Multiplexer 24 selects the output of oscillator 20 (labeled &#34;osc set&#34; in FIG. 2) when the output of sync timer 22 indicates a logical 1, and multiplexer 24 selects the output of level shifter 21 (labeled &#34;sync set&#34; in FIG. 2) when the output of sync timer 22 indicates a logical 0. 
     When enabled, oscillator 20 asserts at its output a clock pulse train having the same waveform as that of the clock pulse train output by oscillator 2 (of FIG. 1), and having frequency F. The frequency F is proportional to the inverse of the resistance of external resistor R 1  (which is coupled to pin 25) when external potential V p  is ground potential. By coupling a resistor R 1  having appropriate resistance to pin 25, the frequency F of oscillator 20&#39;s output pulse train is set. When oscillator 20 is enabled, multiplexer 24 selects the output of oscillator 20 (labeled &#34;osc set&#34; in FIG. 2), and passes &#34;osc set&#34; through (i.e., to the set terminal of latch 4) to trigger the periodic switching on of the power switch. 
     When oscillator 20 is disabled, multiplexer 24 selects the output of level shifter 21 (labeled &#34;sync set&#34; in FIG. 2), and passes &#34;sync set&#34; through (i.e., to the set terminal of latch 4) to trigger the periodic switching on of the power switch. This &#34;sync&#34; mode operation occurs when V i , the potential at pin 25, exceeds reference potential V r1  at least once during each elapsed time T 1 . Typically, external potential V p  is asserted with a square wave waveform (and with frequency greater than 1/T 1 ), so that pin 25 is at a potential V i  varying with the same square wave waveform and frequency, to cause controller 102 to enter the &#34;sync&#34; mode. In the &#34;sync&#34; mode, level shifter 21 translates the levels of this square wave potential V i  to CMOS logic levels (to generate &#34;sync set&#34; with a square wave waveform at the output of level shifter 21). Such a square wave &#34;isync set&#34; signal is passed through multiplexer 24, and periodically sets latch 4 (shown in FIG. 1) so as to trigger the periodic switching on of the power switch. 
     The output of shutdown timer 23 is a control signal (labeled &#34;shutdown&#34; in FIG. 2) that is indicative of a logical 1 if V i , the potential at a first input of timer 23, is greater than reference potential V r2  (asserted to the other input of timer 23) for a time longer than T 2 . Otherwise, the output of shutdown timer 23 is a control signal indicative of a logical 0. Chip 102 responds to the &#34;shutdown&#34; signal indicating a logical 1 by entering the shutdown mode, in which it powers down (so it draws no more than a very small bias current, typically on the order of 10 μA) and is in a state in which it does not assert control signals to switch on the power switch. When the &#34;shutdown&#34; signal indicates a logical 0, chip 102 operates in one of the described &#34;oscillator&#34; and &#34;sync&#34; modes. 
     FIG. 3 is a set of waveforms generated by (and supplied to) controller chip 102 in typical operation of controller chip 102. FIG. 3 shows V p  at ground potential (zero volts) during an initial period &#34;A&#34; and a final period &#34;C,&#34; and V p  varying as a square wave during intermediate period &#34;B.&#34; 
     It is assumed that during periods A and C, V i  (the potential at pin 25) has been less than reference potential V r1  for a time longer than T 1 . Thus, controller chip 102 is in the oscillator mode during periods A and C. In this mode, control signal &#34;sync out&#34; (asserted by sync timer 22) is at supply potential V dd  above ground and is thus indicative of a logical 1. Thus, the signal &#34;set&#34; output from multiplexer 24 is the clock pulse train &#34;osc set&#34; output from oscillator 20. The clock pulse train &#34;osc set&#34; has a frequency F which is proportional to 1/R 1 . 
     During period B, each of V p  (the external potential) and V i  (the potential at pin 25) is a square wave, and V i  exceeds reference potential Vr 1  for some portion of each elapsed time T 1 . Thus, controller chip 102 is in the sync mode during period B. In this mode, control signal &#34;sync out&#34; (asserted by sync timer 22) is at ground potential and is thus indicative of a logical 0. Thus, the signal &#34;set&#34; that is output from multiplexer 24 is a replica of V p  (with the &#34;set&#34; signal having been translated by level shifter 21 so as to have peak to peak amplitude V dd , rather than the peak to peak amplitude of V p . It will be apparent that sync timer 22 must be implemented so that the time T 1  is longer than the maximum time that potentials V i  and V p  remain low (i.e., at ground potential), without V i  rising above potential V r1 , during controller chip 102&#39;s sync mode. 
     FIG. 4 is a set of waveforms generated by (and supplied to) controller chip 102 during transitions from the oscillator mode to the shutdown mode and from the shutdown mode to the oscillator mode. FIG. 4 shows V p  at ground potential (zero volts) during an initial period &#34;C&#34; and a final period &#34;E,&#34; and V p  at a high potential during intermediate period &#34;D.&#34; FIG. 4 assumes that during periods C and E, V i  (the potential at pin 25) has been less than reference potential V r1  for a time longer than T 1 , and that V i  is less than reference potential V r2 , Thus, controller chip 102 is in the oscillator mode during periods C and E. 
     At a time T 2  prior to the start of period D (still with reference to FIG. 4), V p  increases to a potential that is sufficiently high to cause potential V i  to exceed the reference potential V r2 . Thus, at the start of period D, the level of the &#34;shutdown&#34; signal (asserted at the output of shutdown timer 23) increases so that the &#34;shutdown&#34; signal becomes indicative of a logical 1. At the end of period D, V p  decreases to a potential sufficiently low to cause potential V i  to fall below reference potential V r2 , so that the &#34;shutdown&#34; signal becomes indicative of a logical 0. As a result, controller chip 102 operates in the shutdown mode during period D. 
     FIG. 5 is a set of waveforms generated by (and supplied to) controller chip 102 of FIG. 2 during transitions from the sync mode to the shutdown mode and from the shutdown mode to the sync mode. FIG. 5 shows that V p  oscillates (as a square wave) between ground potential (zero volts) and a high potential during an initial period &#34;F&#34; and a final period &#34;H.&#34; and that V p  remains at the high potential during intermediate period &#34;G.&#34; In response, V i  (the potential at pin 25) also oscillates as a square wave during periods &#34;F&#34; and &#34;H,&#34; and V i  remains at a high potential during period &#34;G.&#34; FIG. 5 assumes that during periods F and H, V i  exceeds reference potential V r1  for at least part of each elapsed time T 1 , and that V i   
     falls below reference potential V r2  for at least part of each elapsed time T 2 . Thus, controller chip 102 is in the sync mode during periods F and H. Shutdown timer 23 is implemented so that time T 2  is longer than the period (inverse frequency) with which V p  oscillates (during controller 102&#39;s oscillator mode). 
     At a time T 2  prior to the start of period G (still with reference to FIG. 5), V p  ceases oscillating and remains at its high level, which is a potential sufficiently high to cause potential V i  to exceed the reference potential V r2 . Thus, at the start of period G, the level of the &#34;shutdown&#34; signal (asserted at the output of shutdown timer 23) increases so that the &#34;shutdown&#34; signal becomes indicative of a logical 1. At the end of period G, V p  again oscillates, so that potential V i  falls below reference potential V r2  for at least part of each elapsed time T 2 , and the &#34;shutdown&#34; signal becomes indicative of a logical 0. As a result, controller chip 102 operates in the shutdown mode during period G. 
     FIG. 6 is a diagram of current mode switching regulator chip 103, which is a variation on controller 102 of FIG. 2. Regulator chip 103 includes an internal power switch (not shown) whereas controller chip 102 is used with an external power switch, but regulator chip 103 generates the same control signals for turning the power switch off and on as does chip 102. Regulator chip 103 includes the same circuitry (elements 20, 21, 22, 23, 24, and 25) shown in FIG. 2, and operates in oscillator, sync, and shutdown modes in the same way as does controller chip 102. In both controller chip 102 and regulator chip 103, a feedback loop is used to turn off the power switch, thus regulating the output voltage of the overall DC-to-DC converter which includes the chip. 
     Next, with reference to FIG. 7, we describe a DC-to-DC converter which includes controller chip 104, and buck controller circuitry external to chip 104. Controller chip 104 of FIG. 7 is identical to controller chip 102 of FIG. 2, except in minor respects apparent to those of ordinary skill in the art (including in that it has a pin coupled to boost capacitor C B ) required for it to control external buck controller circuitry rather than external boost controller circuitry. The buck controller circuitry of FIG. 7 differs from the boost converter circuitry of FIG. 1 in that the source of NMOS transistor N1 is coupled through inductor L1 to the output node (whereas in FIG. 1 the drain of transistor N1 is coupled through diode D to the output node, and inductor L is coupled between the input potential V i , and the source of N1), Schottky diode D1 is connected between ground and the source of N1 (replacing diode D of FIG. 1), sense resistor R sense  is connected between the input potential V in  and the drain of N1 (rather than between ground and the source of N1 as in FIG. 1), and boost capacitor C B  is coupled between chip 101 and the source of transistor N1. 
     Controller chip 104 includes elements 20, 21, 22, 23, and 24 of FIG. 2 (which are connected as shown in FIG. 2, but are not shown in FIG. 7 for simplicity), with the pin labeled &#34;Mode&#34; in FIG. 7 corresponding to pin 25 of FIG. 2. Chip 104 differs from chip 102 of FIG. 2 only in minor respects apparent to those of ordinary skill in the art (including in that it has a pin coupled to boost capacitor C B ). Chip 104 of FIG. 7 functions in essentially the same manner as does chip 102 of FIG. 2, including by turning on transistor N1 by setting a latch (i.e., latch 4 of FIG. 1) in response to pulses from multiplexer 24 and turning off transistor N1 by resetting the latch in response to a comparison of V c  -V osc  (where V osc  is a ramped voltage produced by an oscillator and V c  is the potential at the pin labeled &#34;FB&#34;) with a feedback potential indicative of the potential V s  at Node B (between resistor R sense  and the drain of N1). After latch 4 within chip 104 has been set, the latch 4 resets (causing driver 6 within chip 104 to assert a potential V DR  to the gate of transistor N1 which turns off transistor N1) when V s  =V c  -V osc . 
     In alternative embodiments, the invention is a DC-to-DC converter which includes a current mode switching controller chip (which embodies the invention, and is capable of entering any of multiple operating modes in response to signals asserted to a single pin thereof) and external circuitry (e.g., boost controller circuitry) other than the buck controller circuitry of FIG. 7. 
     In other embodiments, the invention is a DC-to-DC converter which includes a current mode switching regulator chip rather than a current mode switching controller chip (with &#34;current mode switching regulator&#34; denoting a circuit which performs all functions of a &#34;current mode switching controller&#34; but which also includes an on-board power switch, in contrast with a &#34;current mode switching controller&#34; chip, which does not include an on-board power switch and must be used with an external power switch), and in which the power switch is implemented on-board the regulator chip (rather than as an external power switch). For example, one such embodiment is a variation on that of FIG. 7, in which current mode switching controller chip 104 is replaced by current mode switching regulator chip which includes all elements of chip 104 and also an integrated circuit implementation of NMOS transistor N1 (which functions as a power switch). 
     Although only a number of preferred embodiments have been described in detail herein, those having ordinary skill in the art will certainly understand that many modifications are possible without departing from the teachings hereof. All such modifications are intended to be encompassed within the following claims.