Abstract:
A data bus and data bus protocol for transferring messages is presented. The bus and bus protocol eliminate the need for a separate reset line. The bus and bus protocol transmit messages and messages separators on the same line.

Description:
FIELD OF THE INVENTION 
     The invention relates to the field of information transfer. In particular, the invention relates to the field of data buses. 
     BACKGROUND OF THE INVENTION 
     Serial data buses send data bits on one line. Additional lines may be included for transmitting clock, handshaking, and reset signals that indicate, among other things, when the data line output has stabilized and is no longer switching from one state to another. Additionally, data buses use these lines to separate messages. The HPIB, a parallel data bus, has special lines to indicate the beginning and end of a message. Some serial data buses use a reset line to identify the beginning and end of message. Other serial data buses eliminate the reset lines by using a header/trailer scheme to identify new messages. One serial data bus combines the clock signal and data on one line and uses a separate reset line to identify the beginning and end of messages. Hardware is used to extract the clock signal. Once the clock signal is extracted it is used to extract the data. This scheme has the disadvantage of requiring extensive hardware to extract the clock signal from the data/clock line. Also this scheme requires a reset line. 
     A separate line for signaling the beginning of a new message has several disadvantages. In addition to the reset wire, hardware is needed to drive the wire, to send the information, and to receive the information. This additional hardware increases computer system cost and increases computer system failure rate. Using headers and trailers to identify the beginning and end of messages has the disadvantage of increasing the amount of time required to send a message and consuming bus bandwidth (where bandwidth is the maximum possible number of signal transitions per second). Headers and trailers have the further disadvantage of requiring the message to be encoded so that the header or trailer cannot occur in a message. Message encoding further decreases bus bandwidth. 
     SUMMARY OF THE INVENTION 
     The present invention signals the end of one message and the beginning of another without using a reset line or the header/trailer scheme. Message separators identify the end of one message and the beginning of another. The present invention transmits message separators and message data bits on the same line and in alternating fashion. The present invention transmits the messages separators during a first interval and message data bits during a second interval. The first and second intervals can be the first half cycle and second half cycle of a clock signal sent on a clock line. When the message separator has a first polarity, the message data bits following it continue an existing command. When the message separator has a second polarity, the message data bits following it begin a new message. 
     The present invention can be implemented as a precharged data bus. In this configuration, a bus master transmits the message separators during the first interval and the message data bits during the second interval to various bus slaves. When the bus master has sent a message to a bus slave giving the bus slave permission, the bus slave can also transmit message data bits during the second interval. However, only the bus master can transmit during the first interval. The bus master announces a new message by discharging the data line during the first interval. This produces message separators having a second polarity. The bus master announces the continuation of an existing message by precharging the data line during the first interval. This produces message separators having a first polarity. 
     The method and apparatus for transferring information according to the present invention has the advantage of requiring less hardware. The hardware reduction decreases system cost and failure rate. When the present invention is implemented as a precharged data bus, it obtains an unambiguous message separator without reducing the data rate or adding additional hardware. This unambiguous message separator results from the bus master&#39;s exclusive control of the data line during message separator transmission. If any erroneous bus operation occurs when the message data bits are sent, the erroneous operation can be stopped by the bus master sending a message separator of the second polarity. Additionally, when the present invention is implemented as a precharged data bus, it obtains the benefits of a precharged data bus. These benefits arise because only the bus master can send message separators. The benefits include reduced bus contention, reduced hardware wince only the bus master sends message separators, and reduced bus capacitance. The bus capacitance is reduced because the bus slave&#39;s bus driving circuitry only needs to be able to discharge the bus. The reduced bus capacitance allows the bus to run as much as three times faster. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the transmission of messages and message separators according to the preferred embodiment of the present invention. 
     FIG. 1B shows the transmission of message and message separators according to an alternate embodiment of the invention. 
     FIG. 2 shows an apparatus that transmits messages and message separators according to the preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     This description assigns two part numbers to the elements. The first part refers to the figure number and the second part refers to the element. 
     The method according to the preferred embodiment of the present invention sends message data bits 1-3 and message separators 1-1, 1-9 on the same precharged data line. The message separators 1-1, 1-9 are transmitted during the first interval 1-5 and the message data bits 1-3 are transmitted during the second interval 1-7. The clock signal creates the first interval 1-5 and the second interval 1-7. 
     The precharged data line, in accordance with the preferred embodiment of the invention, is shown in FIG. 1A. When continuing a message, the precharged data line is precharged during the first interval 1-5 to produce the message separator 1-1 having a first polarity. When beginning a new message, the precharged data line is discharged during the second interval 1-1 to produce the message separator 1-9 having a second polarity. Message data bits 1-3 are always sent during the second interval 1-7. Thus, in the preferred embodiment of the invention, one message separator 1-1 is sent for each message data bit 1-3. 
     The method and apparatus according to the preferred embodiment of the invention is implemented in a system similar to that shown in FIG. 2. FIG. 2 represents a memory system with a block memory architecture described in U.S. patent application, High Yield Semiconductor Memory Devices, Ser. No. 847,411, filed on Apr. 3, 1986 and incorporated herein by reference. This memory system has a memory system controller 2-1 and numerous memory block controllers 2-3. Each memory block controller 2-3 controls a block of memory. The memory system controller 2-1 controls all of the memory block controllers 2-3. In the preferred embodiment of the present invention, the precharged data line and clock line are connected between the memory system controller 2-1 and the memory block controllers 2-3. The memory system controller 2-1 is the bus master and the memory block controllers 2-3 are the bus slaves. Only the bus master, the memory system controller 2-1, can precharge the data line during the first interval 1-5 to create the message separators 1-1. If this memory system has six different commands, then three bits are required to identify the commands. FIG. 1A shows the transmission of a message separator 1-11 having a second polarity. This message separator 1-11 identifies the beginning of a new message, a reset. The following message data bit 1-13 is a zero and is followed by a message separator 1-15 of the first polarity which signifies the continuation of the present message. The next two message data bits 1-17 and 1-21 0 and 1 complete the command 001. The two message data bits 1-25 and 1-29 are the data. The data is followed by a message separator 1-31 having a second polarity that identifies the end of the present message and the beginning of the next command. 
     The apparatus, according to the present invention, can be constructed by connecting a data line between the bus master and the bus slaves. The bus master and bus slave used by the present invention are similar to those used in other buses. A clock line can be connected between the bus master and bus slaves. The clock can be of the type commonly used in other buses.