Abstract:
To provide a bandgap reference circuit capable of shortening a start time at power-on in a circuit lowered in power consumption. There is provided a bandgap reference circuit using an op amplifier to generate a reference voltage, which is equipped with a first current source connected between a power supply terminal and an operating current input terminal of the op amplifier, a second current source having one end connected to the power supply terminal, and a switch connected between the other end of the second current source and the operating current input terminal of the op amplifier, and in which a switch is turned on at power-on and turned off after starting of the reference voltage.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2016-084270 filed on Apr. 20, 2016, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
     Field of the Invention 
       [0002]    The present invention relates to a bandgap reference circuit and a DCDC converter equipped therewith. 
       Background Art 
       [0003]    The recent electronic devices, particularly, a smart phone, a portable device, a wearable device, etc. have been required to have low power consumption in order to prolong an operating time of a battery-driven product. 
         [0004]    In the electronic devices as described above, a DCDC converter such as a switching regulator, an LDO regulator or the like has been used as a power supply device which supplies a power supply to a microcomputer, an AP (Application Processor), a memory, a sensor, etc. The DCDC converter outputs a constant voltage to an output terminal regardless of a voltage fluctuation at an input terminal and is required to highly maintain efficiency even though a current supplied from the output terminal to a load widely fluctuates from a low current to a large current. As to a device required to have low power consumption, it becomes particularly important to maintain high efficiency in a light load current region. 
         [0005]    Such a DCDC converter requiring high efficiency at a light load needs to reduce power consumption of a bandgap reference circuit used within the DCDC converter. A problem however arises in that when power consumption is lowered, the time necessary to start up the bandgap reference circuit becomes long, so that the time up to the start of a switching operation of the DCDC converter becomes long. 
         [0006]    It has been proposed to such a problem in Patent Document 1 that a PMOS transistor having a gate and drain commonly connected to an output terminal of a bandgap reference circuit is added to the output terminal, and a current is supplied to the output terminal by the PMOS transistor during a period until the voltage of the output terminal reaches a prescribed level from the time of power-on to thereby shorten a start time of the bandgap reference circuit. 
       PATENT DOCUMENT 1 
       [0007]    Japanese Patent Application Laid-Open No. 2010-160700 
       SUMMARY OF THE INVENTION 
       [0008]    In the method in Patent Document 1, however, the threshold voltage of the PMOS transistor must be larger than the difference between a power supply voltage and the voltage of the output terminal. 
         [0009]    Although depending on the voltage value of the power supply voltage, the voltage of the output terminal is raised by the PMOS transistor immediately after power-on, there may be a case where the PMOS transistor is turned off before the voltage of the output terminal rises up to a desired voltage value. 
         [0010]    Further, since the voltage of the output terminal is raised by the normal operation of the bandgap reference circuit after the PMOS transistor is turned off, the effect of the PMOS transistor is not obtained. 
         [0011]    The present invention has been made in view of the foregoing problems and aims to provide a bandgap reference circuit capable of starting with low power consumption and in a short time, and a DCDC converter equipped therewith. 
         [0012]    In order to solve the above problems, there is provided a bandgap reference circuit according to the present embodiment, which uses an op amplifier to generate a first reference voltage. The bandgap reference circuit is equipped with a first current source connected between a power supply terminal and an operating current input terminal of the op amplifier, a second current source having one end connected to the power supply terminal, a switch connected between the other end of the second current source and the operating current input terminal of the op amplifier, and a control circuit which generates a control signal controlling on/off of the switch. The switch is turned on when the control signal is a first state and turned off when the control signal is a second state. 
         [0013]    A DCDC converter according to the present embodiment is equipped with the bandgap reference circuit and an error amplifier having an inversion input terminal inputted with a feedback voltage obtained by dividing an output voltage, and a non-inversion input terminal inputted with the first reference voltage. 
         [0014]    A DCDC converter according to another embodiment is equipped with the bandgap reference circuit. The control circuit brings the control signal into a first state at power-on and brings the control signal into a second state, based on the completion of a soft start executed from the time of the power-on. 
         [0015]    A DCDC converter according to a further embodiment is equipped with the bandgap reference circuit. The control circuit brings the control signal into a first state in a PWM mode, and brings the control signal into a second state in a PFM mode. 
         [0016]    According to a bandgap reference circuit according to the present embodiment, a switch is turned on with a control signal as a first state upon power-on to supply operating currents to an op amplifier from both of a first current source and a second current source and thereby raise a first reference voltage to a desired voltage value in a short time (i.e., start the first reference voltage). Thereafter, the switch is turned off with the control signal as a second state, thereby making it possible to suppress power consumption while shortening a start time. 
         [0017]    Further, the bandgap reference circuit according to the present embodiment can particularly be suitably applied to a DCDC converter of low power consumption. Even in this case, a start time at power-on can be shortened. Further, in a PWM mode (at heavy load), the response of the first reference voltage can be enhanced by turning on the switch. In a PFM mode (at light load), power consumption can be suppressed by turning off the switch. It is thus possible to provide a DCDC converter capable of high efficiency and stable operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a circuit diagram of a bandgap reference circuit according to an embodiment of the present invention; 
           [0019]      FIG. 2  is a circuit diagram illustrating one example of a DCDC converter equipped with the bandgap reference circuit of  FIG. 1 ; and 
           [0020]      FIG. 3  is a circuit diagram illustrating another example of the DCDC converter equipped with the bandgap reference circuit of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0021]    Embodiments of the present invention will hereinafter be described with reference to the accompanying drawings. 
         [0022]      FIG. 1  is a circuit diagram of a bandgap reference circuit  100  according to the present embodiment. 
         [0023]    The bandgap reference circuit  100  according to the present embodiment is comprised of a reference voltage generation circuit  10  and a control circuit  11  which generates a control signal CONT, and generates a reference voltage VREF 1  at a reference voltage output terminal  3 . 
         [0024]    The reference voltage generation circuit  10  is equipped with an op amplifier  101 , an output transistor  102  comprised of a PMOS transistor, resistive elements  103  to  105 , diodes  106  and  107 , current sources  108  and  109 , and a switch  110 . 
         [0025]    The current source  108  is connected between a power supply terminal  1  supplied with a power supply voltage VDD and an operating current input terminal  101   in  of the op amplifier  101 . The current source  109  has one end connected to the power supply terminal  1 . The switch  110  is connected between the other end of the current source  109  and the operating current input terminal  101   in  of the op amplifier  101  and is on/off-controlled by the control signal CONT. 
         [0026]    The output transistor  102  has a source connected to the power supply terminal  1 , a drain connected to the reference voltage output terminal  3 , and a gate connected to an output terminal of the op amplifier  101 . 
         [0027]    The resistive elements  104  and  105  and the diode  107  are connected in series between the reference voltage output terminal  3  and a ground terminal  2 . The resistive element  103  and the diode  106  are connected in series between the reference voltage output terminal  3  and the ground terminal  2 . 
         [0028]    The op amplifier  101  has an inversion input terminal connected to a connecting point of the resistive elements  104  and  105 , and a non-inversion input terminal connected to a connecting point of the resistive element  103  and the diode  106 . 
         [0029]    With such a configuration, the reference voltage VREF 1  is generated at the reference voltage output terminal  3 . 
         [0030]    The operation of the bandgap reference circuit  100  according to the present embodiment will next be described. 
         [0031]    First, when the power supply voltage VDD is applied, the control circuit  11  brings the control signal CONT into a first state (e.g., a HIGH level). Thus, the switch  110  is turned on so that the operating current input terminal  101   in  of the op amplifier  101  is supplied with currents not only from the current source  108 , but also from the current source  109 . 
         [0032]    Since the op amplifier  101  is operated by the operating currents inputted to the operating current input terminal  101   in,  the op amplifier  101  is capable of quick operation by being supplied with the operating currents from the two current sources  108  and  109  as described above. Thus, it is possible to raise the reference voltage VREF 1  to a desired voltage value in a short time after the application of power. 
         [0033]    Thereafter, the control circuit  11  brings the control signal CONT into a second state (e.g., a LOW level), based on the raising of the reference voltage VREF 1  to the desired voltage value. Thus, the switch  110  is turned off so that the operating current input terminal  101   in  of the op amplifier  101  is supplied with the operating current only from the current source  108 . Therefore, after the reference voltage VREF 1  is started after power-on, power consumption can be suppressed. 
         [0034]    Incidentally, the configuration of switching the control signal CONT from the first state to the second state by the control circuit  11  can be realized as follows. 
         [0035]    The control circuit  11  is configured to measure in advance the time from power-on to reaching of the reference voltage VREF 1  to the desired voltage value in the state in which the switch  110  is turned on, count the time by a timer from the time of power-on, and switch the control signal CONT from the first state to the second state, based on reaching of an elapsed time from the time of power-on to the pre-measured time. 
         [0036]    Thus, according to the bandgap reference circuit  100  according to the present embodiment, it is possible to shorten a start time and suppress power consumption. 
         [0037]    Examples in which the bandgap reference circuit  100  according to the present embodiment is applied to DCDC converters will next be described using  FIGS. 2 and 3 . 
         [0038]      FIG. 2  is a circuit diagram of a DCDC converter  200  which is one example of the DCDC converter equipped with the bandgap reference circuit  100  of  FIG. 1 . 
         [0039]    Since the basic configuration of the DCDC converter  200  is general, its detailed description will be omitted here. A description will be made about how the bandgap reference circuit  100  is used in the DCDC converter  200 . 
         [0040]    The DCDC converter  200  of the present example is equipped with a soft start circuit  201  which outputs a soft start voltage VREF_SS for executing a soft start. 
         [0041]    Two non-inversion input terminals of an error amplifier  202  are respectively inputted with a reference voltage VREF 1  and a soft start voltage VREF_SS generated from the bandgap reference circuit  100 . An inversion input terminal of the error amplifier  202  is inputted with a feedback voltage VFB obtained by dividing an output voltage VOUT of the DCDC converter  200 . 
         [0042]    The error amplifier  202  compares the lower one of the reference voltage VREF 1  and the soft voltage start voltage VREF_SS and the feedback voltage VFB and outputs an error voltage VERR to a comparator  203 . 
         [0043]    Although the soft start voltage VREF_SS gradually rises after power-on, the feedback voltage VFB and the soft start voltage VREF_SS are compared by the error amplifier  202  when the soft start voltage VREF_SS is lower than the reference voltage VREF 1 , and the reference voltage VREF 1  does not affect the error voltage VERR as the output of the error amplifier  202 . 
         [0044]    Then, when a prescribed soft start time elapses, the soft start voltage VREF_SS becomes higher than the reference voltage VREF 1 . Thus, thereafter, the feedback voltage VFB and the reference voltage VREF 1  are compared by the error amplifier  202 , and the soft start voltage VREF_SS does not exert influence on the error voltage VERR as the output of the error amplifier  202 . 
         [0045]    On the other hand, in the bandgap reference circuit  100  in the DCDC converter  200  of the present example, the control circuit  11  is configured to have a comparator  211  and a reference voltage source  212 . The comparator  211  has an inversion input terminal inputted with the soft start voltage VREF_SS, and a non-inversion input terminal inputted with a reference voltage VREF 2  of the reference voltage source  212 . The reference voltage VREF 2  is a prescribed voltage which becomes the reference of completion of the soft start. 
         [0046]    After power-on, the bandgap reference circuit  100  is operated in the following manner simultaneously with the execution of the soft start such as described above. 
         [0047]    Since the soft start voltage VREF_SS serves as the voltage which gradually rises from the ground potential after power-on, the soft start voltage VREF_SS is lower than the reference voltage VREF 2  immediately after power-on. Therefore, the comparator  211  outputs a signal of a HIGH level. That is, the comparator  211  brings the control signal CONT into the first state. Consequently, the switch  110  illustrated in  FIG. 1  is turned on to assume a state in which the currents are supplied from both of the current source  108  and the current source  109  to the operating current input terminal  101   in  of the op amplifier  101 . Thus, the reference voltage VREF 1  inputted to the error amplifier  202  is started in a short time after power-on. 
         [0048]    Thereafter, when the soft start voltage VREF_SS further rises and becomes higher than the reference voltage VREF 2 , the comparator  211  outputs a signal of a LOW level. That is, the comparator  211  brings the control signal CONT into the second state. Consequently, the switch  110  illustrated in  FIG. 1  is turned off to assume a state in which the current is supplied to the operating current input terminal  101   in  of the op amplifier  101  only from the current source  108 . Thus, after power-on, power consumption of the bandgap reference circuit  100  can be suppressed after the reference voltage VREF 1  is started. 
         [0049]    Here, since it is necessary that the reference voltage VREF 2  of the reference voltage source  212  which configures the control circuit  11  is a voltage which becomes the reference of completion of the soft start, and the reference voltage VREF 1  completely reaches a desired voltage value when the soft start is completed and the object to be compared with the feedback voltage VFB in the error amplifier  202  is switched from the soft start voltage VREF_SS to the reference voltage VREF 1 , the reference voltage VREF 2  is preferably set to a voltage value slightly higher than the reference voltage VREF 1 . 
         [0050]    Thus, according to the DCDC converter  200  of the present example, the control signal CONT which controls the switch  110  in the bandgap reference circuit  100  by using the signal used in the soft start executed from the time of power-on can be switched from the first state at the time of power-on to the second state, based on the completion of the soft start. 
         [0051]      FIG. 3  is a circuit diagram of a DCDC converter  300  which is another example of the DCDC converter equipped with the bandgap reference circuit  100  of  FIG. 1 . Since the basic configuration of the DCDC converter  300  is general in a manner similar to the above DCDC converter  200 , its detailed description will be omitted. 
         [0052]    The DCDC converter  300  of the present example is configured to switch a switch  110  in a bandgap reference circuit  100  in synchronism with the switching between a PWM mode and a PFM mode. 
         [0053]    Specifically, a control circuit  11  of the bandgap reference circuit  100  is equipped with a comparator  311  and a reference voltage source  312 . The comparator  311  has an inversion input terminal inputted with a reference voltage VREF 3  of the reference voltage source  312 , and a non-inversion input terminal inputted with an error voltage VERR being an output of an error amplifier  302 . 
         [0054]    The error amplifier  302  has a non-inversion input terminal inputted with a reference voltage VREF 1  generated by the bandgap reference circuit  100 , and an inversion input terminal inputted with a feedback voltage VFB obtained by dividing an output voltage VOUT of the DCDC converter  300 . The error amplifier  302  compares the reference voltage VREF 1  and the feedback voltage VFB and outputs the error voltage VERR to a comparator  303 . 
         [0055]    The error voltage VERR becomes a high potential as the load connected to the DCDC converter  300  gets heavy, and becomes a low potential as the load gets light. Therefore, the reference voltage VREF 3  is made into a prescribed voltage as a reference for switching between the PWM mode and the PFM mode to thereby switch a control signal CONT to a first state and a second state, based on the voltage value of the error voltage VERR. 
         [0056]    With such a configuration, the comparator  311  outputs a signal of a HIGH level in the PWM mode in which the error voltage VERR is higher than the reference voltage VREF 3 . That is, the comparator  311  brings the control signal CONT into the first state. Thus, the switch  110  illustrated in  FIG. 1  is turned on to assume a state in which currents are supplied from both of the current sources  108  and  109  to the operating current input terminal  101   in  of the op amplifier  101 . 
         [0057]    On the other hand, the comparator  311  outputs a signal of a LOW level in the PFM mode in which the error voltage VERR is lower than the reference voltage VREF 3 . That is, the comparator  311  brings the control signal CONT into the second state. Thus, the switch  110  illustrated in  FIG. 1  is turned off to assume a state in which a current is supplied to the operating current input terminal  101   in  of the op amplifier  101  only from the current source  108 . 
         [0058]    In the PWM mode in which the load is a heavy load, switching is continuously performed, and charging and discharging are increased through a gate capacitance of a differential input transistor which configures the error amplifier  302 . Therefore, the reference voltage VREF 1  corresponding to the output of the bandgap reference circuit  100  also becomes easy to vary. According to the present example, however, since the operating current of the op amplifier  101  can be increased in the PWM mode, the reference voltage VREF 1  can be immediately returned to a desired voltage value even though it varies. 
         [0059]    Further, in the PFM mode in which the load is a light load, power consumption can be reduced by reducing the operating current of the op amplifier  101 . 
         [0060]    Thus, according to the DCDC converter  300  of the present example, the response of the reference voltage VREF 1  can be enhanced in the PWM mode (at the heavy load). In the PFM mode (at the light load), the efficiency of the DCDC converter  300  can be improved by operating the bandgap reference circuit  100  with low current consumption. 
         [0061]    Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. It is needless to say that various changes can be made thereto within the scope not departing from the gist of the present invention. 
         [0062]    For example, in addition to the output signal CONT of the comparator  311  in the DCDC converter  300  illustrated in  FIG. 3  being inputted to the reference voltage generation circuit  10  in the bandgap reference circuit  100  of the DCDC converter  200  illustrated in  FIG. 2  to switch on/off of the switch  110  illustrated in  FIG. 1  at power-on and after start-up, the DCDC converter  300  can also be configured to switch on/off of the switch  110  even in the PWM mode and PFM mode at its normal operation. 
         [0063]    Further, although the control signal CONT is generated by the control circuit  11  in the DCDC converter  300  illustrated in  FIG. 3 , a signal for switching the PWM mode and the PFM mode may be directly inputted to the reference voltage generation circuit  10  as the control signal CONT where the signal is generated separately, so as to control on/off of the switch  110 .