Abstract:
An interface for translating data of different voltages includes an input terminal structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as an output terminal structured to provide an output from the interface a first circuit portion powered by a power supply having the first voltage level, a second circuit portion is powered by a power supply having a second voltage level, and a power supply detection circuit structured to accept a detection signal and to maintain a correct output at the output terminal even after the power supply having the first voltage level no longer supplies the first voltage level to the interface.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention is directed toward an interface latch for translating data from a first to a second supply voltage level, and more particularly to an transfer buffer interface latch having input and output terminals, and supplied with a first and a second voltage supply.  
           [0003]    2. Description of the Related Art  
           [0004]    In some integrated devices used in the audio radio field, it is very important to reduce the energy concentrated in a particular range of frequencies that could be propagated and could disturb other electronic applications. Even the clock switching in certain digital circuits could accumulate energy around the fundamental and harmonic frequency, which would result in decreased performance of the radio.  
           [0005]    One solution to reduce this undesired effect is to reduce the power supply voltage in areas where the switching activity is higher. When using circuits with different power supplies, interfaces to transmit data from circuits having a low voltage supply to circuits having a high voltage supply must be provided.  
           [0006]    Generally, these interfaces use transfer level buffers able to convert logic states from low voltage to high voltage and vice-versa.  
           [0007]    In some electronic devices the power supplies may not be constant, in that the specifications of the device may require that some power supplies are cleared during the work cycle. A difficult problem exists therefore in transferring data from a digital circuit having a low power supply to a digital circuit having a high power supply when the duty cycle of the low power supply is exceedingly short.  
           [0008]    A general block diagram showing the process for switching logic levels between two supply voltages is seen in FIG. 1. A system  10  for switching includes a set of low-voltage logic  12  coupled to and providing an input to a transfer level buffer  14 . The output of the transfer level buffer  14  is supplied to a high-voltage logic  16 .  
           [0009]    A more specific diagram showing an example of a transfer level buffer is shown in FIG. 2. This well-known transfer level buffer interface  20  for shifting data levels between two different supply voltages is used to convert data signals that have a low voltage supply to data signals that have a high voltage supply. The data signals for the high voltage supply is sometimes referred to as the voltage supply of the load. The data input to the transfer level buffer  20  will either be LOW (0 volts) or HIGH-3 V (3 volts), while the output with either be LOW (0 volts) or HIGH-5 V (5 volts). In this way, the data level of input circuitry having a 3 volt power supply is changed to the data level of the load circuitry having a 5 volt power supply.  
           [0010]    In FIG. 2, a high supply  22  is a higher voltage supply than a low supply  24 . A ground reference  26  is typically referenced at 0 volts. An input  30  accepts a data signal from the low supply circuitry, and an output  32  provides a data signal to the high supply circuitry.  
           [0011]    The high supply  22  directly supplies two transistors, M 5  and M 6 , which are coupled in turn to M 4  and M 7 , respectively. Transistors M 4 , M 5 , M 6  and M 7  are all PMOS transistors. An NMOS transistor M 2  is coupled between the transistor M 7  and the ground  26 . An input signal from the input  30  is connected directly to the gates of M 7  and M 2 . Another NMOS transistor M 0  is coupled between M 4  and the ground  26 . The output terminal  32  is placed between the transistors M 4  and M 0 .  
           [0012]    The low supply  24  supplies a PMOS transistor M 3 , which is coupled to an NMOS transistor M 1 , which is in turn coupled to the ground  26 . The gates of the transistors M 1  and M 3  are linked together and to the input  30 . The combination of M 1  and M 3  makes an inverter, with the inverter input being the signal on input  30 , and the inverter output being the connection between the transistors M 1  and M 3 . This inverter output is coupled to and drives the gates of M 0  and M 4 .  
           [0013]    The operation of the transfer level buffer  20  of FIG. 2 will now be discussed. When the signal on the input  30  is LOW, the gates of transistors M 1 , M 2 , M 3 , M 6  and M 7  are supplied with 0 volts. The gates of transistors M 0  and M 4  are set to voltage of the low supply  24  (Low supply voltage, or LSV) because the transistor M 3  is ON, while the transistor M 1  is off. M 5  is set to the voltage of the high supply  22  (High supply voltage or HSV). Because of this biasing, M 6  and M 7 , are both ON, and cause the transistor M 5  to switch OFF. Because M 0  is driven with the LSV, M 0  is ON and ensures that the signal at the output  32  will be LOW. Therefore, when the signal on the input  30  is LOW, the signal on the output  32  of the transfer level buffer  20  is also LOW.  
           [0014]    Conversely, when the signal on the input  30  is HIGH-LSV, which means it is at the voltage of the low supply  24 , the gates of the gates of M 1 , M 2 , M 3  and M 7  are also driven with the LSV. The gates of M 0 , M 4 , and M 5  are supplied with a LOW signal, while M 6  is driven with the HSV. Because of this biasing, M 4  and M 5 , are both ON, and M 0  is OFF, which causes the output  32  to rise to HIGH-HSV, the level of the high supply  22 . Thus, when the signal on the input  30  is HIGH-LSV, the signal on the output  32  of the transfer level buffer  20  is HIGH-HSV.  
           [0015]    In this way, the transfer level buffer  20  provides at its output  32  voltage signals of 0 volts or 5 volts (or whatever the high supply  22  voltage is), while its input  30  accepts inputs of 0 volts or 3 volts (or whatever the low supply  24  voltage is).  
           [0016]    One major problem with the transfer level buffer  20  is that it is unable to provide the proper signals at its output  32  if the low power supply  24  is removed. For instance, if the low supply  24  shut off because the electronic device that includes the transfer level buffer  20  required a short duty cycle of the low supply, there is no way to produce the necessary LOW and HIGH-HSV signals on the output  32  of the interface  20 .  
           [0017]    The underlying technical problem of this invention is to maintain an output at the transfer level buffer even when the low voltage supply switches off, thereby overcoming the limitations of prior art solutions for transfer level buffers.  
         BRIEF SUMMARY OF THE INVENTION  
         [0018]    The disclosed embodiment of the present invention provides a particular latch architecture in the transfer level buffer, and an additional circuit portion that is operative when it receives a signal that indicates the low voltage supply has shut down.  
           [0019]    In accordance with one embodiment of the invention, an interface for translating data of different voltages is provided. The interface includes an input terminal structured to accept an input from a circuit at a first voltage level; an output terminal structured to provide an output from the interface; a first circuit portion powered by a power supply generating the first voltage level; a second circuit portion powered by a power supply generating a second voltage level that is higher than the first voltage level; and a power supply detection circuit structured to accept a detection signal, the detection circuit coupled to the first and second circuit portions and further structured to maintain a correct output at the output terminal after the power supply generating the first voltage level no longer supplies the first voltage level.  
           [0020]    In accordance with another embodiment of the invention, a method of translating data having a first data level to a second data level is provided. The method includes powering a first portion of a circuit with a power supply generating a first voltage operating level; powering a second portion of the circuit with a power supply generating a second voltage operating level; providing an input signal on an input terminal; generating an output at the second voltage operating level on an output terminal responsive to the input signal; and latching data from the input signal prior to interruption of the power supply having the first voltage operating levels to maintain the output at the second voltage operating level. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    The features and advantages of a device according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.  
         [0022]    [0022]FIG. 1 is a general block diagram showing a transfer level device, along with its inputs and outputs according to the prior art.  
         [0023]    [0023]FIG. 2 is a schematic diagram showing in detail a transfer level device of the prior art.  
         [0024]    [0024]FIG. 3 is a schematic diagram showing a transfer data buffer latch embodying the invention.  
         [0025]    [0025]FIGS. 4A, 4B and  4 C are charts showing various voltages at different times in a tested embodiment of the transfer data buffer latch of FIG. 3. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]    The present invention is useful to convert digital data driven by buffers supplied by low voltage to digital data loads operating at a higher voltage, even when the low voltage supply is interruptible.  
         [0027]    With using the prior art transfer level buffer  14  of FIG. 1, if the low voltage logic  12  were to lose its voltage supply, the high voltage logic  16  would no longer continue to work correctly. However, with the use of the inventive transfer level buffer latch, the high voltage logic could continue to work because the data input to the inventive transfer level buffer latch is latched once it is received. This latching and data translating is due to the particular structure of the inventive transfer level buffer latch  50 , shown in FIG. 3 and described below.  
         [0028]    This transfer level buffer latch  50  is specifically tailored to convert 3 v logic to 5 v digital data, but could also be used in any application supplied by different voltage supplies other than those used in the present embodiment. The changing of supply voltages and other changes easily made by those skilled in the art to adapt the inventive circuit to other voltage levels is specifically considered part of the invention.  
         [0029]    The transfer level buffer latch  50  includes a low voltage supply SUPPLYLOW, providing for example, 3 volts, and a high voltage supply SUPPLYHIGH, providing, for example 5 volts. It also includes an input terminal  52  for accepting either a LOW or a HIGH-LSV signal and an output terminal  62  for transmitting a LOW or a HIGH-HSV signal. There is also a ground reference, GND, which is typically referenced to 0 volts.  
         [0030]    A signal VCCOFF is an indicator signal that could have a LOW logic level of 0 volts, or a HIGH logic level of either 3 v or 5 v. The signal VCCOFF signals the absence of the low voltage supply SUPPLYLOW. As used in the transfer level buffer latch  50 , the signal VCCOFF has a HIGH logic signal if the SUPPLYLOW is not present, and a LOW logic signal if the SUPPLYLOW is present.  
         [0031]    The transfer level buffer latch  50  includes two PMOS transistors M 16 , M 17  coupled directly to the SUPPLYLOW. The transistor M 16  is coupled to the GND through two NMOS transistors M 18  and M 12 . The transistors M 16 , M 17 , and M 18  all have gate terminals coupled to and are driven by the signal on the input terminal  52 .  
         [0032]    Coupled directly to the SUPPLYHIGH are two PMOS transistors M 14  and M 15 . Drain terminals of the transistors M 14  and M 17  are coupled together by an NMOS transistor M 22 . The junction of the transistors M 22  and M 14  is labeled node  54 . The gate of transistor M 22  is coupled to the gate of the transistor M 12 , and both of these transistors M 22 , M 12  are driven by the signal on the output  62 , the operation of which will be further described below.  
         [0033]    The drain terminal of the transistor M 14  is also coupled to a PMOS transistor M 13 , which is in turn coupled to an NMOS transistor M 11 . A source of the transistor M 11  is connected to ground. Control gates of the transistors M 11  and M 13  are coupled together and are driven by the signal on the input terminal  52 .  
         [0034]    The transistor M 15  is coupled to ground through the combination of NMOS transistors M 19  and M 10 . A node  56  between the transistors M 13  and M 11  is coupled to the gates of the transistors M 15  and M 19 . A control gate of the transistor M 10  is driven by a node  58  between the transistors M 16  and M 18 . Placed between the drains of the transistors M 15  and M 19  is the output terminal  62 .  
         [0035]    A subcircuit for ensuring proper operation even if the low power supply is interrupted is formed of NMOS transistors M 20  and M 21  and a terminal for accepting the signal VCCOFF. The transistor M 20  has its drain coupled to the input terminal  52 , and its source coupled to ground. The transistor M 21  has its drain coupled between the transistors M 19  and M 10 , and also has its source coupled to ground. The signal VCCOFF, which goes HIGH when the low power supply is interrupted, drives both the control gates of both transistors M 20  and M 21 .  
         [0036]    The operation of the transfer level buffer latch  50  will now be discussed.  
         [0037]    Operation as a buffer when the input is LOW  
         [0038]    When the SUPPLYLOW is 3 v and the SUPPLYHIGH is 5 v, the transfer level buffer latch  50  behaves like a buffer, having inputs and outputs similar to the interface  20  described above with reference to FIG. 2. This insures compatibility with circuits previously including the interface  20 .  
         [0039]    When the signal at the input terminal  52  is LOW, the NMOS transistors M 11  and M 18  are OFF. The PMOS transistors M 13 , M 16  and M 17  are ON, and this causes M 10  to turn ON, because its gate is then coupled to the SUPPLYLOW through M 16 . In this case, to drive the output terminal  62  LOW, the transistor M 19  must be ON while the transistor M 15  is OFF.  
         [0040]    If the last previous state of the output of the transfer level buffer latch  50  was LOW, M 14  would still be ON, causing the node  56  to be coupled to SUPPLYHIGH through M 13  and M 14 . Thus, the node  56  would turn the transistor M 15  OFF and turn the transistor M 19  ON, and thereby force the signal on the output  62  to LOW, the desired state when the signal on the input  52  is LOW.  
         [0041]    If the previous state of the transfer level buffer latch  50  was HIGH-HSV, the NMOS transistor M 22  would be ON, and the node  54  would be coupled to SUPPLYLOW through the transistors M 17  and M 22 . Because the input signal at the input terminal  52  was LOW, the node  56 , being at a voltage of SUPPLYLOW less the voltage drops through M 17 , M 22  and M 13 , would still be high enough to turn the transistor M 15  OFF and turn the transistor M 19  ON, and thereby force the signal on the output  62  to also be LOW.  
         [0042]    Therefore, no matter what the previous state of the transfer level buffer latch  50 , when a LOW signal is presented on the input terminal  52 , a LOW signal will be generated on the output terminal  62 .  
         [0043]    Operation as a buffer when the input is HIGH  
         [0044]    When the signal on the input terminal is HIGH-LSV, the NMOS transistors M 11  and M 18  are ON, while the PMOS transistors M 13 , M 16 , and M 17  are OFF. Because the node  56  would be LOW, the NMOS transistor M 19  would be turned OFF while the PMOS transistor M 15  would be turned ON. In this state M 22  is ON, being coupled to SUPPLYHIGH through the transistor M 15 . The node  58  would be LOW, because M 16  is OFF, while M 18  and M 12  are ON, therefore the transistor M 10  would also be OFF. Because M 15  is on, while M 19  and M 10  are OFF, the signal on the output terminal  62  is necessarily HIGH-HSV.  
         [0045]    Therefore, when a HIGH-LSV signal is presented on the input terminal  52 , a HIGH-HSV signal will be generated on the output terminal  62 .  
         [0046]    A special feature exists in the transfer level buffer latch  50  in that, when the output is HIGH-HSV, the NMOS transistor M 22  is turned ON. This leaves it ready to charge the node  54  as soon as the signal on the input terminal  52  goes LOW. This configuration allows transfer level buffer latch  50  to propagate signals faster than if it did not have this configuration.  
         [0047]    Operation as a latch when the input is LOW  
         [0048]    When the SUPPLYLOW is LOW, meaning that the low power supply has been interrupted, but the SUPPLYHIGH remains at 5 volts, transfer level buffer latch  50  behaves like a latch.  
         [0049]    In the previous example, when the transfer level buffer latch  50  behaved as a buffer, that is, when the SUPPLYLOW is HIGH-LSV and when the signal input at the input terminal  52  is LOW, transistors M 10 , M 13 , M 14 , M 16 , M 17  and M 19  were ON and transistors M 11 , M 15 , M 18  and M 22  were OFF. If the SUPPLYLOW then switches to LOW, that is the low power supply was interrupted, turned off or shut down, all of the connection signals maintain the previous values except for the signal at the node  58 . The node  58  was HIGH because it was coupled through M 16  to SUPPLYLOW, but when SUPPLYLOW went to 0 volts, node  58  also drops. However, if node  58  is not high enough to keep M 10  ON, the output node  62  would no longer be coupled to ground through M 10 .  
         [0050]    When the SUPPLYLOW is interrupted, the subcircuit made of transistors M 20  and M 21  substitute the function of the node  58 , by bypassing the transistor M 10  and coupling the transistor M 19  to ground directly through the transistor M 21 . Because VCCOFF is HIGH when SUPPLYLOW is interrupted, M 21  is turned ON and couples the transistor M 19  to ground.  
         [0051]    When the SUPPLYLOW is interrupted, the data present on the input node  62  may also be interrupted, because it also may be provided by digital logic powered by the 3 volt supply. Even though in this example the signal on the input gate  52  is LOW, it may have a tendency to float or not provide sure data. To compensate for this, VCCOFF also drives M 20  to clamp the gates of M 11  and M 13  to ground, which insures that the node  56  stays HIGH, because it is supplied through transistor M 14 . Because node  56  is HIGH, transistor M 15  is OFF and transistor M 19  is ON. Also, as discussed above, transistor M 21  is ON, thereby pulling the output node  62  to LOW.  
         [0052]    Thus, even when the SUPPLYLOW is interrupted or lost, transfer level buffer latch  50  can still produce a LOW output at the output node  62  when it receives a LOW signal on the input node  52 .  
         [0053]    Operation as a latch when the input is HIGH  
         [0054]    When the transfer level buffer latch  50  behaved as a buffer and when the signal at the input terminal  52  is HIGH, transistors M 11 , M 12 , M 15  and M 18  were ON, and transistors M 10 , M 13 , M 14 , M 16 , M 17  and M 19  were OFF. Now if SUPPLYLOW goes to LOW because it is shut down, all the connection signals maintain the previous values except for the signal on the input terminal  52 . In this case, this signal will most likely drop to 0 volts because of the loss of the power supply for the digital logic that produced the signal.  
         [0055]    To maintain the HIGH-HSV signal at the output node  62 , the transistor M 15  must remain ON, while the transistor M 19  must remain OFF; this entails driving both the gates of M 15  and M 19  LOW by keeping a LOW signal on node  56 .  
         [0056]    This condition ensured by the operation of the transistor M 20 . This transistor, when VCCOFF is HIGH, pulls the gates of transistors  13  and  17  to ground, which turns them ON. The transistor M 22  is also ON because it is driven by the HIGH-HSV signal on the output node  62 . Therefore, the node  56  is coupled to the SUPPLYLOW, which is now 0 volts, through the transistors M 17 , M 22  and M 13 . This configuration keeps node  56  LOW, and consequently keeps the signal on the output node at HIGH-HSV.  
         [0057]    Thus, even when the SUPPLYLOW is interrupted or lost, the transfer level buffer latch  50  can still produce a HIGH output at the output node  62  when it receives a HIGH signal on the input node  52 .  
         [0058]    An embodiment of the transfer level buffer latch  50  was tested by the applicant, and the results shown in FIGS. 4A, 4B, and  4 C. FIGS. 4A, 4B, and  4 C are related graphs showing outputs of a simulated transfer level buffer latch  50 , with different signals on the input node  52 . FIG. 4A represents the voltage at the low voltage power supply, SUPPLYLOW. Three separate tests cases were run, all with similar results. Notice that, around 0.017 seconds, the SUPPLYLOW drops from 3 volts to 0 volts.  
         [0059]    [0059]FIG. 4B shows the signal on the output node  62  of the transfer level buffer latch  50  when the signal on the input node is HIGH. In that case, once the SUPPLYLOW drops from 3 volts to 0 volts, the voltage on the output node  62  drops only slightly, from 5 volts to between 4.89 and 4.94 volts. Therefore, even when there is no low voltage power supply, the transfer level buffer latch  50  continues to provide the correct output. FIG. 4C shows, similarly, the signal on the output node  62  when the signal on the input node  26  is LOW. In this case, even when there is the SUPPLYLOW is removed, the transfer level buffer latch  50  continues to provide the correct output.  
         [0060]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims and the equivalents thereof.