Abstract:
An overcurrent protection circuit and DC power supply that are subtly affected by process and device differences, have small input and output voltage drops, and set maximum and short-circuit current values. In a normal operation mode, a first operational amplifier and an output transistor keep the output voltage constant. In a current limiting mode, when a large current is input to an input terminal due to transient response, a second detection transistor and a third operational amplifier control a second control transistor to keep the maximum current of the output transistor constant. When voltage decreases during a foldback mode, a first detection transistor and a second operational amplifier control a first control transistor to control short-circuit current of the output transistor. A second operational amplifier decreases output current in accordance with the output voltage with a current source that maintains constant mutual conductance.

Description:
BACKGROUND OF THE ART  
       [0001]     The present invention relates to an overcurrent protection circuit for preventing overcurrent by limiting output current to be less than or equal to a predetermined value.  
         [0002]     In many cases, a conventional constant voltage circuit includes an overcurrent protection circuit just in case the output terminal of the constant voltage circuit short-circuits. When the output current from the output terminal becomes greater than or equal to a predetermined value, an overcurrent protection circuit of one type interrupts the output, an overcurrent protection circuit of another type locks the output to prevent the output current from increasing anymore, and an overcurrent protection circuit of a further type gradually reduces the output voltage and the output current. For the circuit that interrupts the output, an operation to recover the interrupted output is required. For the circuit that permits continuous flow of a peak current, its output transistor is adversely affected when the peak current, at which the overcurrent protection operation is started, is set at a large value. Further, the output is not sufficiently large when the peak current is set at a small value.  
         [0003]     The circuit that gradually reduces the output current has a foldback voltage-current characteristic, and is called a foldback current limiting circuit. In the foldback current limiting circuit, the output voltage starts decreasing and the output current also starts decreasing when the current value reaches a peak current value. The value of a short-circuit current is smaller than the peak current value when the voltage of the output terminal is zero. As a result, when the horizontal axis represents current and the vertical axis represents voltage, the voltage-current relationship shows a foldback characteristic. An overcurrent protection circuit having such a foldback voltage-current characteristic ensures protection of the output transistor and enables the current amount when the overcurrent protection operation is started to be relatively large. This enables the output to be increased.  
         [0004]     A technique relating to a stabilizing power supply circuit, which has a foldback current-voltage characteristic and sets a small output current when a ground fault occurs in the output, has been proposed to reduce heat loss and enable the circuit to be easily realized by an integrated circuit (refer to, for example, Japanese Laid-Open Patent Publication No. 7-182055). The circuit described in this publication is shown in correspondence with the present invention in  FIG. 4 . The stabilizing power supply circuit includes an output transistor and a current detection resistor, which are connected between an input terminal and an output terminal. The stabilizing power supply circuit further includes an error amplifier and a first output control transistor for comparing the voltage of the output terminal with a reference voltage and controlling the output transistor. The stabilizing power supply circuit further includes a comparator and a second output control transistor for detecting the voltages at the two terminals of the current detection resistor and controlling the output transistor. In this way, the stabilizing power supply circuit separately sets the overcurrent detection point and the output current when a ground fault occurs in the output terminal. This reduces the power consumed by the output transistor when a ground fault occurs in the output terminal and prevents heat generation or breakage of the circuit, which would be caused by a fault occurring in the output terminal.  
         [0005]     A technique relating to an overcurrent protection circuit that does not have a current detection resistor on its output path has been proposed (refer to, for example, Japanese Laid-Open Patent Publication No. 11-103524). The circuit described in this publication is shown in correspondence with the present invention in  FIG. 5 . This overcurrent protection circuit includes an output transistor for outputting current supplied to a load, a drive transistor for controlling the amount of current flowing through the output transistor, and a feedback means for controlling the drive transistor in accordance with the value of output voltage supplied to the load. The overcurrent protection circuit detects current corresponding to the current flowing through the load. When the detected current is greater than or equal to a predetermined value, the overcurrent protection circuit controls the drive transistor to limit the output current of the output transistor. In this way, the overcurrent protection circuit directly controls the current of the drive transistor in accordance with the detected current value. This configuration enables the overcurrent protection function to be realized using an independent reference voltage. Thus, the overcurrent protection function is less dependent on the voltage of the transistor, the input voltage, and the output voltage. Further, the overcurrent protection circuit does not required a current detection resistor to be arranged in its current path that leads to the output terminal, and a current mirror circuit may be arranged in a path through which current proportional to the output current flows.  
         [0006]     A technique relating to a constant voltage power supply circuit, which enable its overcurrent limiting function with respect to overload and its short-circuit current limiting function with respect to output short-circuiting to be set freely in a manner independent of each other, has been proposed (refer to, for example, Japanese Laid-Open Patent Publication No. 2002-169618). The circuit described in this publication is shown in correspondence with the present invention in  FIG. 6 . In the constant voltage power supply circuit, an output transistor is controlled based on the output of an error amplifier. Load current is detected by a current detection circuit. Voltage generated based on the detected load current and the output of a voltage detection circuit detecting output voltage are input into a comparator having an offset. Then, the output transistor is controlled based on the output of the comparator.  
         [0007]     In the circuit according to the technique described in Japanese Laid-Open Patent Publication No. 7-182055, the resistor, which detects the current, consumes much power. If current is decreased, detection would become difficult. When detecting current with a resistor, the resistance would have to be accurate. However, it is difficult to manufacture a small resistor having a precise absolute value during a semiconductor fabrication process. From this viewpoint, it would be difficult for the circuit described in Japanese Laid-Open Patent Publication No. 7-182055 to be realized by an integrated circuit.  
         [0008]     In the circuit described in Japanese Laid-Open Patent Publication No. 11-103524, it may be difficult to detect short-circuit current depending on the voltage condition or changes in the environment in which the detection transistor. Further, the value of the short-circuit current, which is determined using the absolute value of the resistor, may greatly differ depending on the resistance of the resistor.  
         [0009]     Likewise, in the circuit in Japanese Laid-Open Patent Publication No. 2002-169618, it may be difficult to detect short-circuit current depending on the voltage condition or changes in the environment in which the detection transistor. Further, the value of the short-circuit current changes when the threshold voltage of the transistor and the resistance of the resistor change.  
       SUMMARY OF THE INVENTION  
       [0010]     It is an object of the present invention to provide an overcurrent protection circuit and a DC power supply, which are subtly affected by fabrication processes differences between devices, which have small drops in input and output voltages, and which enable the setting of a maximum current value and a short-circuit current value.  
         [0011]     One aspect of the present invention is an overcurrent protection circuit provided with an output control device including a control terminal for controlling power between an input terminal and an output terminal of the overcurrent protection circuit. A first comparator, connected to the control terminal of the output control device, compares a reference voltage with voltage of the output terminal and outputs a comparison result. First and second detection devices, each of which includes a control terminal sharing the comparison result, detect a proportional current value that is proportional to current flowing through the output control device. A second comparator, connected to an output terminal of the first detection device, compares the proportional current value with a first reference current value provided by a first current source. A first control device, connected to an output terminal of the second comparator, controls voltage of the control terminal of the output control device. A second current source, connected to an output terminal of the second detection device, provides a second reference current value. A third comparator compares voltage of the output terminal of the second detection device with voltage of an output terminal of the output control device. A second control device, connected to an output terminal of the third comparator, controls voltage of the control terminal of the output control device.  
         [0012]     Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:  
         [0014]      FIG. 1  is a circuit diagram of an overcurrent protection circuit according to a preferred embodiment of the present invention;  
         [0015]      FIG. 2  is a graph showing the current-voltage characteristic of the overcurrent protection circuit of the preferred embodiment;  
         [0016]      FIG. 3  is a circuit diagram of an overcurrent protection circuit according to a further embodiment of the present invention;  
         [0017]      FIG. 4  is a circuit diagram of a circuit in the prior art;  
         [0018]      FIG. 5  is a circuit diagram of a circuit in the prior art; and  
         [0019]      FIG. 6  is a circuit diagram of a circuit in the prior art. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     First Embodiment  
       [0020]     An overcurrent protection circuit CLC having a P-channel MOS (metal oxide semiconductor) configuration according to a first embodiment of the present invention will now be described with reference to  FIG. 1 . The overcurrent protection circuit CLC includes an input terminal IN, to which an input voltage Vin is applied, and an output terminal OUT, to which an output voltage Vout is applied. The overcurrent protection circuit CLC includes an output transistor P 5 , which functions as an output control device and which is arranged between the input terminal IN and the output terminal OUT. The input voltage Vin input to the input terminal IN is output from the output terminal OUT via the output transistor P 5 . Output current Iout is determined by a load connected to the output terminal OUT.  
         [0021]     The output terminal OUT is further connected to a positive input terminal of an operational amplifier A 1 , which functions as a first comparator. Reference voltage Vref is input to a negative input terminal of the operational amplifier A 1 . An output terminal of the operational amplifier A 1  is connected to a gate terminal (control terminal) of the output transistor P 5 .  
         [0022]     A current detection circuit is further connected to the gate terminal of the output transistor P 5 . More specifically, the current detection circuit comprises a transistor P 1 , which functions as a first detection device, and a transistor P 3 , which functions as a second detection device. The gates of the transistors P 1  and P 3  are connected to a line connecting the output terminal of the operational amplifier A 1  and the gate terminal of the output transistor P 5 .  
         [0023]     The transistor P 3  has a source terminal connected to the input terminal IN and a drain terminal connected to current sources i 0  and i 2 , which function as a second current source. The current source i 0  has a second current value, and the current sources i 2  has a third current value. A switch S 1  is arranged between the drain terminal of the transistor P 3  and the current source i 2 . In a normal mode, the switch S 1  is closed. The switch S 1  operates in cooperation with a switch S 0 , which will be described later. The switch S 1  and the switch S 0  function as a switch unit.  
         [0024]     Further, a positive input terminal of an operational amplifier A 3 , which functions as a second comparator, is connected between the drain terminal of the transistor P 3  and the current source i 0 . A negative input terminal of the operational amplifier A 3  is connected to the output terminal OUT. An output terminal of the operational amplifier A 3  is connected to the gate terminal of a transistor P 4 , which functions as a second control device. The transistor P 4  has a source terminal connected to the input terminal IN and a drain terminal connected to the gate terminal of the output transistor P 5 .  
         [0025]     The transistor P 1  has a source terminal connected to the input terminal IN and a drain terminal connected to the output terminal OUT via a resistor R 0 . Further, the drain terminal of the transistor P 1  is connected to a negative input terminal of an operational amplifier A 2 . A positive input terminal of the operational amplifier A 2  is connected to a current source gm and a current source i 1 , which function as a first current source. The current sources gm and i 1  are connected to the output terminal OUT via a resistor R 1 . The current source i 1  has a first current value, and the current source gm has a current value that maintains constant mutual conductance. The switch S 0  is connected to the current source gm. In the normal mode, the switch S 0  is closed. The current supplied by the current source i 1  and the current supplied by the current source i 0  are determined in accordance with the size ratio of the transistor P 1  and the transistor P 3  so that current controlled by the operational amplifier A 2  and a transistor P 2  (in a “foldback mode” described later) and current controlled by the operational amplifier A 3  and the transistor P 2  (in a “current limiting mode” described later) are smoothly connected. In this embodiment, the size ratio of the transistor P 1  and the transistor P 3  is set to 1:1. When R 0 =R 1  is satisfied, the current source i 1  and the current source i 0  that are used supply the same current. In the same manner, the maximum value of the control current supplied by the current source gm is equalized with the current supplied by the current source i 2 .  
         [0026]     An output terminal of the operational amplifier A 2  is connected to a gate terminal of the transistor P 2 , which functions as a first control device. The transistor P 2  has a source terminal connected to the input terminal IN and a drain terminal connected to the gate terminal of the output transistor P 5 .  
         [0027]     In this embodiment, P-channel MOS transistors are used as the transistor P 1 , the transistor P 3 , and the output transistor P 5 . The size ratio of the transistor P 1 , the transistor P 3 , and the output transistor P 5  is set to 1:1:n. The transistor P 1  and the transistor P 3  detect a proportional current value that is proportional to the current flowing through the output transistor P 5 . Further, P-channel MOS transistors are used as the transistor P 2  and the transistor P 4 . In this embodiment, the source terminal of each transistor functions as an input terminal, and the drain terminal of each transistor functions as an output terminal.  
         [0028]     The operation of the overcurrent protection circuit CLC will now be discussed. The circuit operation will be described in the order of normal operation mode, current limiting mode, foldback mode, and charge mode.  
         [0029]     [Normal Operation Mode] 
         [0030]     In the normal operation mode, the operational amplifier A 1  and the output transistor P 5  are operated. More specifically, the operational amplifier A 1  compares the output voltage Vout of the output terminal OUT with the reference voltage Vref, and inputs the comparison result to the gate terminal of the output transistor P 5 . This controls the output transistor P 5  so that the output voltage Vout is equal to the reference voltage Vref. As a result, an operation range satisfying Vout=Vref is formed as shown in  FIG. 2 .  
         [0031]     [Current Limiting Mode] 
         [0032]     The current limiting mode is set when a large current is input to the input terminal IN during the normal operation mode. In the first embodiment, the size ratio of the transistor P 3  and the output transistor P 5  is set to 1:n, as described above. Thus, the transistor P 3  detects 1/n of the output current Iout that flows through the output transistor P 5 . If the switch S 1  closed, the operational amplifier A 3  controls the transistor P 4  to be off when the output current Iout flowing through the output transistor P 5  is less than or equal to n*(i0+i2) based on a second reference current value (i0+i2).  
         [0033]     When the output current Iout flowing through the output transistor P 5  exceeds n*(i0+i2), the operational amplifier A 3  controls the current flowing through the transistor P 4  to limit the current flowing through the output transistor P 5 . More specifically, the operational amplifier A 3  first lowers the gate voltage of the transistor P 4 . This raises the gate voltage of the output transistor P 5 . As a result, the output transistor P 5 , which is a P-channel MOS transistor, adjusts the maximum current Imax to be n*(i0+i2).  
         [0034]     The operational amplifier A 3  maintains the drain voltage of the transistor P 3  at the same potential as the drain voltage of the output transistor P 5 . This enables the ratio of the currents flowing through the two transistors to constantly be 1:n irrespective of the drop voltage. As a result, the maximum current Imax is adjusted to be constant in the range of the operational voltages of the current sources (i 0  and i 2 ) and the operational amplifier A 3 . This forms the operation range of the current limiting mode, as shown in  FIG. 2 .  
         [0035]     [Foldback Mode] 
         [0036]     Next, the foldback mode will be described. The foldback mode is set when the voltage further decreases in the current limiting mode. In this embodiment, the size ratio of the transistor P 1  and the output transistor P 5  is set to 1:n. Thus, the transistor P 1  detects 1/n of the output current Iout that flows through the output transistor P 5 .  
         [0037]     Accordingly, voltage of Vout+R0*Iout/n is applied to the negative input terminal of the operational amplifier A 3 .  
         [0038]     If the switch S 0  is closed, voltage of Vout+R1*(i1+gm) is applied to the positive input terminal of the operational amplifier A 3  based on a first reference current value (i1+gm), which is the sum of the first current value and the control current value maintaining constant mutual conductance.  
         [0039]     When R0*Iout/n&lt;R1*(i1+gm) is satisfied, the operational amplifier A 2  controls the transistor P 2  to be off.  
         [0040]     When R0*Iout/n&gt;R1*(i1+gm) is satisfied, the operational amplifier A 2  controls the current flowing through the transistor P 2  to satisfy Iout/n*R0=R1*(i1+gm).  
         [0041]     As a result, the output current Iout becomes equal to (i1+gm)*n*R1/R0.  
         [0042]     The current source gm supplies current proportional to the output voltage Vout. The maximum value of the current source gm is i2*R0/R1. Thus, when the output voltage Vout is zero, that is, when short-circuiting occurs, the current supplied from the current source gm is zero. In this case, the operational amplifier A 2  controls the transistor P 2  so as to satisfy Iout (=Ishort)=n*i1*R1/R0(=n*i0).  
         [0043]     In this operation mode, the voltage generated at the resistor R 0  is smaller than the source-drain voltage VDS of the transistor P 1 . Thus, the transistor P 1  and the output transistor P 5  have substantially the same source-drain voltage VDS. As a result, the transistor P 1  and the output transistor P 5  maintain the current ratio of  1 :n. This forms the operation range of the foldback mode, as shown in  FIG. 2 .  
         [0044]     [Charge Mode] 
         [0045]     If the load is a capacitor load, when power is turned on or when the setting of the voltage Vref is changed, the power supply current needs to be prevented from becoming excessive. Thus, the charge mode is set by opening the switch S 0  and the switch S 1 . In this case, the maximum current Imax is limited to n*i0.  
         [0046]     The current source gm is disconnected. Thus, the operational amplifier A 2  controls the output current so that Iout (=Ishort) becomes equal to n*i0. In the same manner, the operational amplifier A 3  controls the output current so that Iout (=Ishort) becomes equal to n*i0. As a result, the foldback mode is not set, and the operation range of the charge mode is formed as shown in  FIG. 2 .  
         [0047]     This embodiment has the advantages described below.  
         [0048]     In this embodiment, the input is output via the output transistor P 5  during the normal operation mode. The output transistor P 5  is controlled by the operational amplifier A 1 , and the output voltage is fed back to the operational amplifier A 1 . Thus, the internal resistance viewed from the output side is lowered. With this configuration, the drop voltage of the output transistor P 5  is lowered by the output transistor P 5 , which is sufficiently large with respect to the output current. Thus, this section consumes less power. Further, a P-channel MOS transistor is used as the output transistor P 5  in this embodiment. Thus, another power supply for turning on the output transistor P 5  is not necessary. If an N-channel MOS transistor is used as the output transistor, potential that is greater than the input voltage Vin becomes necessary to control the output transistor. In this manner, the internal resistance is lowered to reduce power consumption.  
         [0049]     In this embodiment, the current detection circuit is connected to the gate terminal of the output transistor P 5 . The output transistor P 5  controls the output current Iout and the output voltage Vout via the transistors P 1  and the transistor P 3 . These transistors comprise P-channel MOS transistors. Accordingly, the overcurrent protection circuit may easily be manufactured during a normal semiconductor fabrication process.  
         [0050]     In this embodiment, when the output current Iout of the output transistor P 5  exceeds n*(i0+i2) during the current limiting mode, the operational amplifier A 3  controls the current flowing through the transistor P 4  to limit the current flowing through the output transistor P 5 . This adjusts the maximum current Imax to be equal to n*(i0+i2). The operational amplifier A 3  maintains the drain voltage of the transistor P 3  at the same potential as the drain voltage of the output transistor P 5 . This enables the ratio of the currents flowing through the two transistors to constantly be 1:n irrespective of the drop voltage. As a result, the maximum current Imax is adjusted to be constant within the range of the operational voltages of the current sources i 0  and i 2  and the operational amplifier A 3 .  
         [0051]     In this embodiment, the transistor P 1  detects 1/n of the output current Iout that flows through the output transistor P 5  during the foldback mode. The detected current is then compared with the current supplied from the current sources (i 1  and gm), and the transistor P 2  is controlled in accordance with the comparison result. The current source gm supplies current proportional to the output voltage Vout. The maximum value of the current supplied by the current source gm is i2*R0/R1. This enables the output current Iout to become equal to the short-circuit current Ishort=n*i0 when the output is short-circuited.  
         [0052]     In this embodiment, the switches (S 1  and S 0 ) are connected to the current sources (i 2  and gm), respectively. The charge mode is set by opening the switches. When the load is a capacitor load or when the reference voltage Vref is set at a large value to increase the output voltage, the overcurrent protection circuit realizes a characteristic that does not set the foldback mode.  
         [0053]     In this embodiment, each current source is a current mirror circuit. This easily acts as the overcurrent protection circuit with semiconductor devices.  
       Second Embodiment  
       [0054]     An overcurrent protection circuit CLC having an N-channel MOS configuration according to a second embodiment of the present invention will now be described with reference to  FIG. 3 . The overcurrent protection circuit CLC includes an input terminal IN, to which an input voltage Vin is applied, and an output terminal OUT, to which an output voltage Vout is applied. The overcurrent protection circuit CLC includes an output transistor N 5 , which is arranged between the input terminal IN and the output terminal OUT. The input voltage Vin input to the input terminal IN is output from the output terminal OUT via the output transistor N 5 . The output current Iout is determined by a load connected to the output terminal OUT.  
         [0055]     The output terminal OUT is further connected to a positive input terminal of an operational amplifier A 1 . A reference voltage Vref is input to a negative input terminal of the operational amplifier A 1 . An output terminal of the operational amplifier A 1  is connected to the gate terminal of the output transistor N 5 .  
         [0056]     A current detection circuit is further connected to the gate terminal of the output transistor N 5 . More specifically, the current detection circuit comprises a transistor N 1  and a transistor N 3 . The gate terminals of the transistors N 1  and N 3  are connected to a line connecting the output terminal of the operational amplifier A 1  and the gate terminal of the output transistor N 5 .  
         [0057]     The transistor N 3  has a drain terminal connected to the input terminal IN and a source terminal connected to current sources i 0  and i 2 . A switch S 1  is arranged between the source terminal of the transistor N 3  and the current source i 2 . In a normal mode, the switch S 1  is closed. Further, a positive input terminal of an operational amplifier A 3  is connected between the source terminal of the transistor N 3  and the current source i 0 . The output terminal OUT is connected to a negative input terminal of the operational amplifier A 3 . An output terminal of the operational amplifier A 3  is connected to the gate terminal of a transistor N 4 . The transistor N 4  has a source terminal that is grounded and a drain terminal connected to the gate terminal of the output transistor N 5 .  
         [0058]     The transistor N 1  has a drain terminal connected to the input terminal IN and a source terminal connected to the input terminal IN via a resistor R 0 . Further, the drain terminal of the transistor N 1  is connected to a negative input terminal of an operational amplifier A 2 . A positive input terminal of the operational amplifier A 2  is connected to a current source gm and a current source i 1 . The current sources gm and i 1  are connected to the input terminal IN via the resistor R 1 . A switch S 0  is connected to the current source gm. In the normal mode, the switch S 0  is closed. The current supplied by the current source i 1  and the current supplied by the current source i 0  are determined in accordance with the size ratio of the transistor N 1  and the transistor N 3  so that current controlled by the operational amplifier A 2  and a transistor N 2  (in a “foldback mode”) and current controlled by the operational amplifier A 3  and the transistor N 2  (in a “current limiting mode”) are smoothly connected. In this embodiment, the size ratio of the transistor N 1  and the transistor N 3  is set to 1:1. When R0=R1 is satisfied, the current source i 1  and the current source i 0  that are used supply the same current. In the same manner, the maximum value of the control current supplied by the current source gm is equalized with the current supplied by the current source i 2 .  
         [0059]     The output terminal of the operational amplifier A 2  is connected to the gate terminal of the transistor N 2 . The transistor N 2  has a source terminal that is grounded and a drain terminal connected to the gate terminal of the output transistor N 5 .  
         [0060]     In this embodiment, N-channel MOS transistors are used as the transistor N 1 , the transistor N 3 , and the output transistor N 5 . The size ratio of the transistor N 1 , the transistor N 3 , and the output transistor N 5  is set to 1:1:n. Further, N-channel MOS transistors are used as the transistor N 2  and the transistor N 4 .  
         [0061]     In the same manner as in the first embodiment, the input is output via the output transistor N 5  during the normal operation mode in this embodiment. Thus, the internal resistance is lowered and the power consumption is reduced. Further, the operation of the operational amplifier A 1  keeps the output voltage Vout equal to the reference voltage Vref.  
         [0062]     In the same manner as in the first embodiment, the operational amplifier A 3  controls the current flowing through the transistor N 4  to limit the current flowing through the output transistor N 5  in the current limiting mode when the output current Iout of the output transistor N 5  exceeds n*(i0+i2) so that the maximum current Imax is adjusted to n*(i0+i2). The operational amplifier A 3  maintains the source voltage of the transistor N 3  at the same potential as the source voltage of the output transistor N 5 . This enables the ratio of the currents flowing through the two transistors to constantly be 1:n irrespective of the drop voltage. As a result, the maximum current Imax is adjusted to be constant within the range of operational voltages of the current sources i 0  and i 2  and the operational amplifier A 3 .  
         [0063]     In the same manner as in the first embodiment, the transistor N 1  detects 1/n of the output current Iout flowing through the output transistor N 5  in the foldback mode. The detected current is then compared with the current supplied from the current sources (i 1  and gm), and the transistor N 2  is controlled in accordance with the comparison result. The current source gm supplies current proportional to the output voltage Vout. The maximum value of the current supplied by the current source gm is i2*R0/R1. This enables the output current Iout to become equal to the short-circuit current Ishort=n*i0 when the output is short-circuited.  
         [0064]     In the same manner as in the first embodiment, the switches (S 1  and S 0 ) are connected to the current sources (i 2  and gm), respectively. The charge mode is set by opening the switches. When the load is a capacitor load, the power is turned on, or the setting of the reference voltage Vref is changed, the foldback mode is not set and the power supply current is prevented from becoming unnecessarily excessive.  
         [0065]     In this embodiment, the current detection circuit is connected to the gate terminal of the output transistor N 5 , and the output current Iout and the output voltage Vout are controlled via the transistor N 1  and the transistor N 3 . These transistors comprise N-channel MOS transistors. Accordingly, the overcurrent protection circuit may easily be manufactured during a normal semiconductor fabrication process using N-channel MOS transistors.  
         [0066]     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms.  
         [0067]     In the above embodiments, an external power supply is arranged outside the overcurrent protection circuit CLC. However, a voltage supply may be incorporated to form a DC power supply.  
         [0068]     The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.