Abstract:
A CPU system employs a general-purpose peripheral LSI circuit and a high-speed memory for the peripheral LSI circuit. A selector determines whether access from a CPU is directed to an internal circuit of the peripheral LSI circuit or an SDRAM. If the access is directed to the SDRAM, the selector stores a bus signal in a timing adjusting circuit and then reads the stored bus signal at a rate that is at least twice the rate at which the bus signal has been stored. An SDRAM interface accesses the SDRAM with the read bus signal. The internal circuit accesses the SDRAM while bus arbitration is being carried out between the internal circuit and the SDRAM interface.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a CPU system with a peripheral LSI circuit to which an SDRAM is connected, and more particularly to a CPU system that permits the CPU to access an SDRAM connected to a peripheral LSI circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    Some CPU systems have a peripheral LSI circuit such as a graphics LSI circuit for enabling the computer to have various functions. Such CPU systems may have a unified memory architecture to reduce the size and cost thereof. The unified memory architecture allows a memory for a peripheral LSI circuit, such as a graphics memory, and a main memory to be realized as one memory. One approach to construct a unified memory architecture is to arrange a CPU system such that the CPU is capable of accessing a memory for a peripheral LSI circuit.  
           [0005]    As shown in FIG. 1 of the accompanying drawings, a conventional CPU system has CPU  5 , peripheral LSI circuit  6 , and SDRAM  7 . CPU  5  serves as a main processor of the conventional CPU system. Peripheral LSI circuit  6  has wait control bus interface  61 , selector  62 , SDRAM interface  63 , and internal circuit  64 .  
           [0006]    Wait control bus interface  61  is connected to the bus of CPU  5 , and performs a read/write process in response to access from CPU  5  to peripheral LSI circuit  6 . In the read/write process, wait control bus interface  61  places CPU  5  in a wait mode according to a wait control process in view of the period of time that is required for a response from SDRAM  7  to be transmitted to CPU  5 . Selector  62  is a selector for relaying an exchange with wait control bus interface  61  to a selected one of SDRAM interface  63  and internal circuit  64 . Specifically, when access is made from CPU  5  to SDRAM  7 , selector  62  selects SDRAM interface  63 , and when access is made from CPU  5  to internal circuit  64 , selector  62  selects internal circuit  64 . SDRAM interface  63  is connected to SDRAM  7  and receives a bus signal from and sends a bus signal to SDRAM  7 .  
           [0007]    Internal circuit  64  is a circuit for realizing the functions of peripheral LSI circuit  6 , and has a structure that may differ depending on the application of peripheral LSI circuit  6 . Internal circuit  64  may have a processor therein. SDRAM  7  is connected to peripheral LSI circuit  6  by SDRAM interface  63 , and can be accessed from CPU  5  via peripheral LSI circuit  6 .  
           [0008]    In the conventional CPU system shown in FIG. 1, peripheral LSI circuit  6  with the wait control general-purpose bus performs the wait control process in view of the period of time that is required for a response from SDRAM  7  to be transmitted to CPU  5 , and allows CPU  5  to access SDRAM  7  that is connected to peripheral LSI circuit  6 .  
           [0009]    [0009]FIG. 2 of the accompanying drawings shows another conventional CPU system. The conventional CPU system shown in FIG. 2 has CPU  5 , peripheral LSI circuit  8 , and SDRAM  7 . CPU  5  serves as a main processor of the conventional CPU system. Peripheral LSI circuit  8  has selector  81 , SDRAM interface  82 , and internal circuit  83 .  
           [0010]    Selector  81  is a selector for relaying an exchange with CPU  5  to a selected one of SDRAM interface  82  and internal circuit  83 . Specifically, when access is made from CPU  5  to SDRAM  7 , selector  81  selects SDRAM interface  82 , and when access is made from CPU  5  to internal circuit  83 , selector  62  selects internal circuit  83 .  
           [0011]    Internal circuit  83  is a circuit for realizing the functions of peripheral LSI circuit  8 , and has a structure that may differ depending on the application of peripheral LSI circuit  8 . Internal circuit  83  may have a processor therein. SDRAM  7  is connected to peripheral LSI circuit  8  by SDRAM interface  82 , and can be accessed from CPU  5  via peripheral LSI circuit  8 .  
           [0012]    In the conventional CPU system shown in FIG. 2, selector  81  switches over access from CPU  5  based on the address contained therein to allow CPU  5  to access SDRAM  7  that is connected to peripheral LSI circuit  8 .  
         SUMMARY OF THE INVENTION  
         [0013]    It is an object of the present invention to provide a CPU system which is of a low cost and a reduced circuit scale and which includes a general-purpose peripheral LSI circuit and a high-speed memory for the peripheral LSI circuit.  
           [0014]    To achieve the above object, a CPU system according to the present invention has a CPU, a peripheral LSI circuit, and an SDRAM.  
           [0015]    The peripheral LSI circuit has a first interface connected to an SDRAM interface of the CPU and a second interface for accessing an external circuit. The peripheral LSI circuit determines whether access from the CPU via the first interface is directed to an internal circuit of the peripheral LSI circuit or the external circuit. If the access from the CPU is directed to the external circuit, then the peripheral LSI circuit stores a first bus signal from the first interface, adjusts the timing of the stored first bus signal and reads the first bus signal to generate a second bus signal having a rate which is at least twice the rate of the first bus signal, and accesses the external circuit from the second interface with the second bus signal. The SDRAM is connected to the second interface and accessible by the second bus signal.  
           [0016]    Since the first interface is the same as the interface of the SDRAM, the CPU system can be constructed of a general-purpose peripheral LSI circuit that can be connected to a CPU having an interface with the SDRAM.  
           [0017]    Because the peripheral LSI circuit adjusts the timing of access to the SDRAM, the CPU is capable of accessing the SDRAM with the same timing that it would access an SDRAM directly connected to the CPU.  
           [0018]    According to one aspect of the invention, the internal circuit can access the SDRAM while bus arbitration is being carried out between the internal circuit and the SDRAM interface. As the internal circuit of the peripheral LSI circuit can access the SDRAM, the CPU system can employ a unified memory architecture. Because the second interface has a rate that is at least twice the rate of the first interface, the bandwidth of the memory for the peripheral LSI circuit is at least twice the bandwidth of the main memory for the CPU.  
           [0019]    According to one aspect of the invention, a double data rate SDRAM takes the place of the SDRAM.  
           [0020]    According to another aspect of the invention, there is also provided a peripheral LSI circuit connectable to a CPU for realizing predetermined functions, comprising an internal circuit, a selector, a timing adjusting circuit, and an SDRAM interface.  
           [0021]    The internal circuit realizes the predetermined functions. The selector determines whether access from the CPU is directed to the internal circuit or an external circuit. The selector reads data from or writes data in the internal circuit if the access from the CPU is directed to the internal circuit. The selector sends the access from the CPU as a first bus signal if the access from the CPU is directed to the external circuit. The timing adjusting circuit stores the first bus signal and reads the stored first bus signal with predetermined timing to generate and output a second bus signal having a rate which is at least twice the rate of the first bus signal. The SDRAM interface accesses an SDRAM connected as the external circuit with the second bus signal from the timing adjusting circuit.  
           [0022]    According to one aspect of the invention, in the peripheral LSI circuit, the internal circuit comprises an access circuit for accessing the SDRAM and an arbitration circuit for carrying out bus arbitration between the access circuit and the SDRAM interface.  
           [0023]    According to one aspect of the invention, in the peripheral LSI circuit, a double data rate SDRAM is connected as the external circuit in place of the SDRAM.  
           [0024]    The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    [0025]FIG. 1 is a block diagram of a conventional CPU system which adjusts the timing to access an SDRAM connected to a peripheral LSI circuit according to a wait control process;  
         [0026]    [0026]FIG. 2 is a block diagram of a conventional CPU system which allows access to an SDRAM connected to a peripheral LSI circuit by operating a selector based on the address;  
         [0027]    [0027]FIG. 3 is a block diagram of a CPU system according to an embodiment of the present invention;  
         [0028]    [0028]FIG. 4 is a timing chart of a write process for a CPU to write data in an SDRAM in the CPU system shown in FIG. 3;  
         [0029]    [0029]FIG. 5 is a timing chart of a read process for the CPU to read data from the SDRAM in the CPU system shown in FIG. 3; and  
         [0030]    [0030]FIG. 6 is a block diagram of a CPU system according to another embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]    As shown in FIG. 3, a CPU system according to an embodiment of the present invention comprises CPU  1 , peripheral LSI circuit  2 , and SDRAM  3 .  
         [0032]    CPU  1  serves as a main processor of the CPU system. Peripheral LSI circuit  2  has interface assembly  21  and internal circuit  22 . Interface assembly  21  comprises selector  211 , timing adjusting circuit  212 , SDRAM interface  213 , and clock generator  214 .  
         [0033]    Selector  211  can be connected to an SDRAM interface of CPU  1 , and operates in the same manner as SDRAM  3  with respect to CPU 1 . Selector  211  performs a read/write process on SDRAM  3  or internal circuit  22  in response to access from CPU  1  to peripheral LSI circuit  2 .  
         [0034]    Timing adjusting circuit  212  comprises an FIFO memory for writing data from CPU  1  and reading data to SDRAM  3  and an FIFO memory for writing data from SDRAM  3  and reading data to CPU  1 . Timing adjusting circuit  212  adjusts the timing of access from CPU  1 , and controls a bus signal for SDRAM  3 . A clock signal for the bus that is connected to SDRAM  3  has a rate that is at least twice the rate of a clock signal for the bus that is connected to CPU  1 .  
         [0035]    SDRAM interface  213  is connected to SDRAM  3 , and inputs a bus signal from and outputs a bus signal to SDRAM  3 .  
         [0036]    Clock generator  214  generates a clock signal based on the clock signal for the bus connected to CPU  1  at a rate that is at least twice the rate of the clock signal for the bus connected to CPU  1  and supplies the generated clock signal to SDRAM interface  213  for use by the bus connected to SDRAM  3 .  
         [0037]    Internal circuit  22  is a circuit for realizing the main functions of peripheral LSI circuit  2 , and has a structure that may differ depending on the application, e.g., graphics application, of peripheral LSI circuit  2 . Internal circuit  22  may have a processor therein.  
         [0038]    SDRAM  3  is connected to peripheral LSI circuit  2  by SDRAM interface  213 , and can be accessed from CPU  1  via peripheral LSI circuit  2 .  
         [0039]    [0039]FIG. 4 shows a timing chart of a write process for CPU  1  to write data in SDRAM  3  in the CPU system. FIG. 5 shows a timing chart of a read process for CPU  1  to read data from SDRAM  3  in the CPU system. FIGS. 4 and 5 illustrate clock signal CK 1 , command signal C 1 , address signal A 1 , and data signal D 1  that are included in the bus signal for CPU  1 , and clock signal CK 2 , command signal C 2 , address signal A 2 , and data signal D 2  that are included in the bus signal for SDRAM  3 .  
         [0040]    The CPU system according to the present embodiment operates as follows: When peripheral LSI circuit  2  receives an active command (ACT) on command signal C 1  and a row address (Row) on address signal A 1 , peripheral LSI circuit  2  determines whether the access from CPU  1  is directed to SDRAM  3  or internal circuit  22 . If the access is directed to internal circuit  22 , then selector  211  relays subsequent access to internal circuit  22 . If the access is directed to SDRAM  3 , then timing adjusting circuit  212  adjusts the timing of the access and sends signals to the bus connected to SDRAM  3 .  
         [0041]    As shown in FIG. 4, in the write process for CPU  1  to write data in SDRAM  3 , after peripheral LSI circuit  2  sends an active command on command signal C 2  for SDRAM  3  and a row address (Row) on address signal A 2 , the CPU system delays the issuance of a next command to SDRAM  3  until sufficient data (Dout) are received from CPU  1 . After sufficient data are received from CPU  1 , the CPU system outputs a write command (WRITE) on command signal C 2 , sends a column address (Col) on address signal A 2 , and sends data (Dout) on data signal D 2 , thus writing data in SDRAM  3 . When the write process for CPU  1  to write data in SDRAM  3  is delayed, a clock enable (CKE) signal may be controlled to place the CPU system in a power-down mode, or a precharge command may be applied to bring the CPU system back into an idle mode.  
         [0042]    As shown in FIG. 5, in the read process for CPU  1  to read data from SDRAM  3 , when peripheral LSI circuit  2  receives a read command (READ) on command signal C 1  and a column address (Col) on address signal A 1  from CPU  1 , peripheral LSI circuit  2  starts accessing SDRAM  3 .  
         [0043]    The bus signal for SDRAM  3  operates with a clock at a rate that is at least twice (twice in FIG. 5) the rate of the bus signal for CPU  1 . Therefore, data (Din) are read with data signal D 2  for SDRAM  3  in order to meet the timing to output data (Din) on data signal D 1  for CPU  1  at CAS latency=2, and stored in timing adjusting circuit  212 . The stored data are read from timing adjusting circuit  212  in synchronism with the timing for CPU  1 , and are sent on data signal D 1 .  
         [0044]    Since the portion of peripheral LSI circuit  2  which is connected to CPU  1  comprises an SDRAM interface, the CPU system can be constructed of peripheral LSI circuit  2  that can be connected to any CPUs having an SDRAM interface. Thus, peripheral LSI circuit  2  may be connected to many CPUs.  
         [0045]    Furthermore, because peripheral LSI circuit  2  adjusts the timing to access SDRAM  3 , CPU  1  can access SDRAM  3  that is connected to peripheral LSI circuit  2  with the same timing that it would access an SDRAM directly connected to CPU  1 . As a result, the data transfer rate is not lowered.  
         [0046]    The CPU system according to the present embodiment allows CPU  1  to access SDRAM  3  by the process of burst data access or single data access.  
         [0047]    Inasmuch as CPU  1  can access SDRAM  3  for burst data with the timing adjusted by peripheral LSI circuit  2 , it is possible to transfer data at a high rate.  
         [0048]    As shown in FIG. 6, a CPU system according to another embodiment of the present invention has CPU  1 , peripheral LSI circuit  4 , and SDRAM  3 . CPU  1  and SDRAM  3  shown in FIG. 6 are identical to those of the CPU system shown in FIG. 3.  
         [0049]    Peripheral LSI circuit  4  has interface assembly  41  and internal circuit  42 . Interface assembly  41  comprises selector  411 , timing adjusting circuit  412 , SDRAM interface  413 , and clock generator  414 .  
         [0050]    Selector  411  can be connected to an SDRAM interface of CPU  1 , and operates in the same manner as SDRAM  3  with respect to CPU 1 . Selector  411  performs a read/write process on SDRAM  3  or internal circuit  42  in response to access from CPU  1  to peripheral LSI circuit  4 .  
         [0051]    Timing adjusting circuit  412  comprises an FIFO memory for writing data from CPU  1  and reading data to SDRAM  3  and an FIFO memory for writing data from SDRAM  3  and reading data to CPU  1 . Timing adjusting circuit  412  adjusts the timing of access from CPU  1 , and controls a bus signal for SDRAM  3 . A clock signal for the bus that is connected to SDRAM  3  has a rate that is at least twice the rate of a clock signal for the bus that is connected to CPU  1 .  
         [0052]    SDRAM interface  413  is connected to SDRAM  3 , and is arbitrated by an external circuit to receive a bus signal from and send a bus signal to SDRAM  3 .  
         [0053]    Clock generator  414  generates a clock signal based on the clock signal for the bus connected to CPU  1  at a rate that is at least twice the rate of the clock signal for the bus connected to CPU  1 . Clock generator  414  supplies the generated clock signal to SDRAM interface  413  for use by the bus connected to SDRAM  3 .  
         [0054]    Internal circuit  42  is a circuit for realizing the main functions of peripheral LSI circuit  4 , and has access circuit  421  and arbitration circuit  422 . Access circuit  421  allows internal circuit  42  to access SDRAM  3 . Arbitration circuit  422  performs bus arbitration between SDRAM interface  412  and access circuit  421  for access to SDRAM  3 .  
         [0055]    The CPU system shown in FIG. 6 allows CPU  1  to access SDRAM  3  and also allows internal circuit  42  in peripheral LSI circuit  4  to access SDRAM  3 . As a result, the CPU system can employ a unified memory architecture, and can be reduced in size and cost.  
         [0056]    The bus signal for the SDRAM  3  is of a rate that is at least twice the rate of the bus signal for CPU  1 . Consequently, in a unified memory architecture, the bandwidth of the memory for peripheral LSI circuit  4  is at least twice the bandwidth of the main memory for CPU  1 . If a large bandwidth is preferable for a graphics LSI circuit, for example, the memory for peripheral LSI circuit  4  can have a large bandwidth without involving a difficult design task for speeding up the entire bus of CPU  1 .  
         [0057]    The principles of the present invention are also applicable to a CPU system which uses a memory, e.g., a DDR SDRAM (double data rate SDRAM), for transferring data in synchronism with positive- and negative-going edges of clock signals.  
         [0058]    While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.