Abstract:
Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a memory system and a data channel initialization method for the memory system.  
         [0003]     A claim of priority is made to Korean Patent Application No. 2004-14586, filed on Mar. 4, 2004, the disclosure of which is incorporated herein in its entirety by reference.  
         [0004]     2. Description of the Related Art  
         [0005]     As the operational speed of semiconductor memory devices has increased, data channel initialization has become vital for stable communication between a memory controller and a memory device. A conventional memory system is disclosed, for example, in U.S. Patent Application No. U.S. 2003/0026162A1.  
         [0006]     In order to initialize a data channel, the conventional semiconductor memory device is equipped with extra pins, and a channel delay is adjusted by repeating data write and data read operations in the semiconductor memory device. However, the disadvantage of this system is the increased number of pins, and the requirement of an additional circuit to perform initialization.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention provides a memory system capable of initializing a data channel at high speed without increasing pin count for an associated semiconductor memory device and without using an additional circuit performing initialization.  
         [0008]     According to an aspect of the present invention, there is provided a memory system comprising a memory module having a plurality of semiconductor memory devices, a memory controller to control the semiconductor memory devices; and a data channel and a command/address channel connected between the semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality semiconductor memory devices are controlled by the memory controller.  
         [0009]     According to another aspect of the present invention, there is provided a data channel initialization method for a memory system comprising initializing a plurality of semiconductor memory devices by applying a write command from a memory controller to the plurality of semiconductor memory devices and writing a low frequency data bit pattern from the memory controller to the plurality of semiconductor memory devices.  
         [0010]     The method is provided by applying a read command from the memory controller to the plurality of semiconductor memory devices and reading the written data bit pattern from the plurality of semiconductor memory devices, checking delay times of a period defined from a time when the read command is output by the memory controller to a time when first valid data from the data bit patterns read from each of the plurality of he semiconductor memory devices arrives at the memory controller, determining read latencies for the plurality of semiconductor memory devices according to a checking result such that a longest one of the delay times becomes identical with other delay times, and providing the read latencies to the plurality of semiconductor memory devices.  
         [0011]     The method is further provided by comparing a first data bit pattern of the low frequency data bit pattern written in the plurality of semiconductor memory devices with first data bit patterns of the data bit patterns read from the plurality of semiconductor memory devices, and determining write latencies for the plurality of semiconductor memory devices according to a comparison result such that the first data bit pattern of the written low frequency data bit pattern becomes identical with the first data bit patterns of the data bit patterns read from the plurality of semiconductor memory devices, and providing the write latencies to the semiconductor memory devices. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     Aspects of the present invention will become more apparent by the description of exemplary embodiments with reference to the attached drawings in which:  
         [0013]      FIG. 1  is a schematic diagram illustrating a memory system according to an embodiment of the present invention;  
         [0014]      FIG. 2  is a timing diagram illustrating a write data bit pattern in a data channel initialization method according to an embodiment of the present invention;  
         [0015]      FIG. 3  is a timing diagram illustrating a read data bit pattern in a data channel initialization method according to an embodiment of the present invention;  
         [0016]      FIG. 4  is a flow chart illustrating a data channel initialization method according to an embodiment of the present invention; and  
         [0017]      FIG. 5  is an operational timing diagram of a data channel initialization method according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     The attached drawings illustrate preferred embodiments of the present invention and are presented to allow those of ordinary skill in the art to gain a sufficient understanding of the present invention.  
         [0019]     Throughout the drawings, like reference numerals in the drawings denote like elements.  
         [0020]     Referring to  FIG. 1 , a memory system includes: a plurality of DRAMs  110  through  117 ; a memory module  11  equipped with a column/address buffer  118 ; a memory controller  13  to control DRAMs  110  through  117  and column/address buffer  118 ; data channels DQ 0  through DQ 7  connected between DRAMs  110  through  117  and memory controller  13 ; and a command/address channel C/A.  
         [0021]     In particular, memory controller  13  controls read latencies for DRAMs  110  through  117  and write latencies for DRAMs  110  through  117 .  
         [0022]     Accordingly, each of DRAMs  110  through  117  has a predetermined output delay time based on a corresponding read latency, and outputs data to data channels DQ 0  through DQ 7 . Each of DRAMs  110  through  117  also has a predetermined input delay time based on a corresponding write latency, and inputs data from the data channel DQ 0  through DQ 7 .  
         [0023]     Hereinafter, referring to  FIGS. 2 through 5 , a data channel initialization method according to an embodiment of the present invention will be described.  
         [0024]      FIG. 2  is a timing diagram illustrating a write data bit pattern adapted for use in a data channel initialization method according to an embodiment of the present invention.  FIG. 3  is a timing diagram illustrating a read data bit pattern adapted for use in a data channel initialization method according to an embodiment of the present invention.  
         [0025]     First, during a read operation, a low frequency write data bit pattern DQ Pattern A having a form of 111100001111 . . . is simultaneously transmitted and written to DRAMs  110  through  117  from memory controller  13  via data channel DQ 0  through DQ 3 . In this case, depending on the position of DRAMs  110  through  113 , different data values are written in DRAMs  110  through  113 .  
         [0026]     In DRAM 0   110 , a write data bit pattern is written in response with CLK 0 ; in DRAM 1   111 , a write data bit pattern is written in response with CLK 1 ; in DRAM 2   112 , a write data bit pattern is written in response with CLK 2 ; and in DRAM 3   113 , a write data bit pattern is written in response with CLK 3 . Here, CLK 0  indicates a clock signal CLK arriving at DRAM 0   110 ; CLK 1  indicates a clock signal CLK arriving at DRAM 1   111 ; CLK 2  indicates a clock signal CLK arriving at DRAM 2   112 ; and CLK 3  indicates a clock signal CLK arriving at DRAM 3   113 .  
         [0027]     Next, in order to estimate the positions of DRAMs  110  through  113 , data bit patterns written in DRAMs  110  through  113  are read again from DRAMs  110  through  113 . When the read data bit pattern is different from the written data bit pattern, a write latency is controlled in memory controller  13  such that the read data bit pattern is identical with the written data bit pattern, and the controlled written latency is provided to DRAMs  110  through  113 .  
         [0028]     A write data bit pattern is transformed into a write data bit pattern DQ Pattern B having a form of 111000111 . . . , and the write operations and read operations, described above, are repeated. When the write operations and the read operations are repeated until the write data bit pattern is identical with a bit time, i.e., during a half cycle of clock signal CLK, that is to say, until the write data bit pattern becomes a write data bit pattern DQ Pattern D, a time difference tD between a time when the write data bit pattern DQ Pattern arrives at DRAM 3   113  and a time when command/address C/A arrives at DRAM 3   113  is compensated by the bit time.  
         [0029]     As described above, time difference tD is roughly compensated by the bit time, and then, a time sampling point is finely compensated, thereby transferring a sampling point location to the center of data.  
         [0030]      FIG. 4  is a flow chart illustrating a data channel initialization method according to an embodiment of the present invention.  FIG. 5  is an operational timing diagram of a data channel initialization method according to an embodiment of the present invention. For explanation purposes, only timing diagrams for memory controller  13 , DRAM 0   110 , and DRAM 3   113  are illustrated in  FIG. 5 .  
         [0031]     First, DRAMs  110  through  113  are initialized (S 1 ). Namely, DRAMs  110  through  113  are powered-up; a Mode Register Set (MRS) is set; and a Burst Length (BL) and a CAS latency are set.  
         [0032]     Next, a write command WC is applied to DRAMs  110  through  113  by memory controller  13  via command/address channel C/A, and the same low frequency data bit patterns 11110000 . . . are simultaneously transmitted and written to DRAMs  110  through  113  from memory controller  13  via data channels DQ 0  through DQ 3  (S 2 ).  
         [0033]     Referring to  FIG. 5 , when write command WC and data bit pattern 11110000 . . . are output from memory controller  13  at a time T 1 , write command WC arrives at DRAM 0   110  via command/address channel C/A after a delay time t 0 -C/A, and arrives at DRAM 3  after a delay time t 3 -C/A; and data bit pattern 11110000 . . . arrives at DRAM 0   110  and DRAM 3   113  via channel DQ 0  through DQ 3  after the same delay time tDQ. Accordingly, before the data channel initialization, data  1110  is sampled and stored in DRAM 0   110 , and data  1000  is sampled and stored in DRAM 3   113 .  
         [0034]     Next, a read command RC is applied to DRAMs  110  through  113  by memory controller  13  via command/address channel C/A, and data bit pattern is read again from DRAMs  110  through  113  via data channels DQ 0  through DQ 3  (S 3 ).  
         [0035]     Referring to  FIG. 5 , when read command RC is output from memory controller  13  at a time T 2 , read command RC arrives at DRAM 0   110  via command/address channel C/A after delay time t 0 -C/A, and arrives at DRAM 3   113  after t 3 -C/A. Accordingly, data  1110  stored in DRAM 0   110  is output, and data  1000  stored in DRAM 3   113  is output. For convenience, it is assumed that when read command RC is applied to DRAMs, data is instantly output.  
         [0036]     Data bit pattern 1110 read from DRAM 0   110  and data bit pattern 1000 read from DRAM 3   113  arrive at memory controller  13  via data channel DQ 0  through DQ 3  after the same delay time tDQ.  
         [0037]     Next, delay times tx 0  and tx 3  are checked by memory controller  13 . Delay times tx 0  and tx 3  are defined from point in time T 2  when read command RC is output from memory controller  13  to a time when first valid data “1” of the data bit patterns read from DRAMs  110  through  113  arrives at memory controller  13  (S 4 ).  
         [0038]     Next, based on the result of the check, in order to synchronize the longest delay time tx 3  with the delay time tx 0 , memory controller  13  determines the read latency of DRAMs  110  through  113 , and provides the read latencies of DRAMs  110  through  113  to DRAMs  110  through  113  (S 5 ).  
         [0039]     Accordingly, each of DRAMs  110  through  113  outputs data, having an output delay time different from each other based on their respective read latencies, which are determined differently from each other. Finally, delay times tx 0  and tx 3  become identical with each other.  
         [0040]     Next, a first bit pattern 1111 of low frequency data bit pattern 11110000 . . . written in DRAMs  110  through  113  is compared with first bit patterns of the data bit patterns read from DRAMs  110  through  113  by memory controller  13  (S 6 ).  
         [0041]     Based on the result of the comparison, to synchronize first data bit pattern 1111 of the low frequency data bit pattern with the first data bit patterns of the data bit patterns read from DRAMs  110  through  113 , memory controller  13  determines a write latency of DRAMs  110  through  113  and provides the write latency to DRAMs  110  through  113  (S 7 ).  
         [0042]     Accordingly, each of DRAMs  110  through  113  inputs write data, having an input delay time different from each other according to the respective write latencies differently determined from each other. As a result, first data bit pattern 1111 of the low frequency data bit pattern is identical with the first data bit patterns of the data bit patterns read from DRAMs  110  through  113 .  
         [0043]     As described above, in the memory system according to an embodiment of the present invention, a time difference tD between a time when write data bit pattern DQ Pattern arrives at DRAMs and a time when a command/address C/A arrives at the DRAMs is compensated. In other words, write data bit pattern DQ Pattern is sequentially changed, and a data channel is initialized. Accordingly, additional pins for an associated semiconductor memory device are not required, and an additional circuit to perform initialization is also not required.  
         [0044]     While the present invention has been shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the following claims.