Abstract:
A drive circuit suitable for driving an inductive load such as an isolation transformer is disclosed having a driver stage and associated feedback circuitry. The driver stage has at least one output for connecting to the load and is switchable between a drive mode and an idle mode of operation. In the drive mode of operation, the driver stage produces a data output signal at the output which corresponds to a data input signal received by the driver stage. In the idle mode, the driver stage produces an idle signal, in response to a control signal, which functions to discharge the conductive load. The feedback circuit produces the control signal in response to the idle signal and adjusts the control signal so that the idle output signal will approach a predetermined neutral level. The inductor will proceed to discharge and, once discharged, will shift the idle voltage. The shift in voltage will cause the feedback action to terminte, thereby preventing the feedback action from introducing charging current into the inductor which would adversely effect the transmission of further data.

Description:
TECHNICAL FIELD 
     The present invention relates generally to data communications and more particularly to a driver circuit for use in local area networks and the like having feedback circuitry for limiting undershoot and overshoot resulting from an inductive load. 
     BACKGROUND OF THE INVENTION 
     In data communication applications, it is frequently necessary to transmit data to inductive loads. For example, data transceivers used in local area networks (LANs) include data driver circuits having outputs which are connected to an isolation transformer. Such isolation transformers present an inductive load which causes the output of the driver to either undershoot or overshoot. Standards have been developed, such as in Ethernet applications, which specify the maximum amount of permissible overshoot and undershoot. 
     Attempts have been made to develop data driver circuits which comply with the undershoot/overshoot specifications, but which are also capable of rapidly discharging the inductive load. Referring to the drawings, FIG. 1 shows a conventional driver circuit of the type used in Ethernet LAN applications. 
     The conventional driver circuit 10 includes an output drive stage 18 having a pair of data inputs on lines 24 and 28 which receive data input signals RXOP and RXON, respectively. The driver stage includes a differential amplifier input comprised of transistors Q 5  and Q 6  having resistive loads R 3  and R 4 . The output of the differential amplifier drives a pair of emitter-follower configured transistors Q 9  and Q 10 . 
     The differential output of the drive stage is at the emitters of transistors Q 9  and Q 10  which are connected to lines 32 and 34, respectively. The output lines are coupled to the primary winding of an isolation transformer (not depicted) having a resistor connected in parallel. The transformer and parallel resistor equivalent circuit 20 is represented by inductor L and resistor R L . The differential output signals are RXP and RXN. 
     When a data packet is transmitted to the transceiver, driver circuit 10 in the transceiver receives the data packet on inputs 24 and 28 as signals RXOP and RXON. The data packet is retransmitted by the driver circuit and appears at lines 32 and 34 as output signals RXP and RXN. 
     For LAN protocols such as Ethernet, an idle period is required between transmission of data packets. During the idle period, inputs RXON and RXOP, and thus outputs RXP and RXN, are initially held at their respective maximum values. Outputs RXP and RXN must be maintained at these values for a predetermined time period referred to as the high time t high . Period t high  must be at least 200 nanoseconds and no longer than 8 microseconds. Ideally, the inductive load is discharged by the end of the idle period. 
     The driver circuit is forced to the idle mode by an enable signal coupled to line 26. The enable signal is generated by a receive squelch circuit (not depicted) which senses the presence of a data packet. The enable signal is caused to go high (a logic &#34;1&#34;) when a data packet is being received and is caused to go low (a logic &#34;.0.&#34;) when a data packet terminates. The idle period commences when the enable signal goes low. 
     The conventional driver circuit includes a switch circuit 12 which receives the enable signal on line 26 and an associated time delay circuit 14 which determines the duration of the high time t high . Switch circuit 12 includes a differential comparator circuit made up of transistors Q 2  and Q 3 , with transistor Q 2  biased by a pair of resistors R 6  and R 5  connected between the supply voltage and ground. The enable signal is coupled to the base of transistor Q 3  such that Q 3  is conductive when the enable signal is high (a data packet is being received) and non-conductive when the enable signal is low. 
     Time delay circuit 14 includes a resistor R 1  and capacitor C connected in parallel between the positive supply voltage and the collector of transistor Q 3 . The RC time constant of R 1  and C will provide a time delay as will be described. 
     The collector of transistor Q 3  is also coupled to the base of a transistor Q 4  which, in turn, drives the bases of a pair of transistors Q 7  and Q 8 . The collectors of transistors Q 7  and Q 8  are connected to the collectors of transistors Q 5  and Q 6 , respectively, and the emitters of the four transistors are connected in common. 
     The operation of the conventional drive circuit will be described in connection with FIG. 1 and the timing diagram of FIG. 2. The top waveform represents the enable signal and the next waveform represents a mode control signal present at node 33 of FIG. 1. The lower waveforms represent the differential data outputs RXP and RXN driving the inductive load. 
     When a data packet is being received, the enable signal is caused to go high as shown at point A. The high enable signal will turn on transistor Q 3  and cause the collector of Q 3  to drop, thereby charging capacitor C of the time delay circuit. The low Q 3  collector voltage will also turn off transistors Q 4 , Q 7  and Q 8 . 
     When transistors Q 7  and Q 8  are off, the output driver stage 18 is free to retransmit the received data packet to lines 32 and 34 as can be seen by waveforms RXP and RXN of FIG. 1. The typical data modulation scheme prescribes that a data transition, occur at every bit, therefore the output signal has substantially no D.C. component which would tend to charge the inductive load. At the end of the data packet, the receive squelch detects the absence of data and causes the enable signal to go low at point B. As a result, Q 3  is turned off. This is the beginning of the high time period t high . 
     Capacitor C will then proceed to discharge through resistor R1. The collector of transistor Q 3  will slowly rise, thereby causing the emitter of transistor Q 4  to rise. This will cause the mode control signal at node 33 to increase as can be seen by the FIG. 2 waveform. 
     At the same time the enable signal goes low, the source (not depicted) of input data RXOP and RXON on lines 24 and 28 will force the input data to remain at their respective maximum values. This will cause the output data signals RXP and RXN to remain at their respective maximum values as shown in FIG. 2. During this specified high period t high , the data output signals have a substantial D.C. component which charges the inductive load L. 
     Eventually, the mode control voltage at node 33 will have increased sufficiently to turn on transistors Q 7  and Q 8 . Transistors Q 7  and Q 8  will then draw current from load resistors R3 and R 4  thereby reducing the differential output signals RXP and RXN as shown at point C. This is the end of the high time period t high . 
     It is desireable that the outputs RXP and RXN both approach the midlevel value and remain there throughout the idle period while the inductor L discharges. However, because of the presence of the load inductor L, there will be a tendency for the positive signal RXP to undershoot and the negative signal RXN to overshoot as shown in FIG. 2 at point D by a very substantial amount. The amount of undershoot/overshoot can be reduced by reducing the high time period t high , but the period must be at least as long as the specified minimum period. 
     One conventional approach to reducing undershoot/overshoot is to employ a continuously active feedback circuit which monitors the data output signals and limits the amount of overshoot/undershoot. However, once the inductive load becomes substantially discharged, the load appears as a D.C. short circuit. The continuously active feedback circuit will attempt to force the output voltage to some minimum value which is determined by various factors including the inherent offset voltages which are present in any feedback system. This minimum value will invariably differ from the actual voltage across the discharged inductor. The feedback network will attempt to force the inductor voltage to the offset voltage thereby introducing large currents into the inductor. These currents will leave the isolation transformer inductance partially charged, thereby adversely affecting the operation of the transformer when the next data packet is received. 
     The present invention overcomes the above-noted shortcomings of prior art drive circuits. The magnitude of the overshoot/undershoot can be positively maintained within stringent specifications, yet the inductive load will be allowed to quickly discharge before receipt of the next data packet. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings. 
     SUMMARY OF THE INVENTION 
     A drive circuit for driving an inductive load, such as the primary winding of an isolation transformer, is disclosed. The drive circuit includes driver stage means having at least one output for coupling to the load. The output may be either single-ended or differential. 
     The driver stage means is switchable between a drive mode and an idle mode. When in the drive mode, a data output signal is produced at the output which is responsive to a data input signal. In the idle mode, the driver stage means produces an idle output signal at the output which is responsive to a control signal. 
     The drive circuit further includes feedback means for generating the control signal in response to the idle output signal and for adjusting the control signal so as to cause the idle output signal to approach a predetermined neutral level by way of feedback action. During this period, the overshoot/undershoot of the idle output signal is limited and the inductive load is permitted to discharge. 
     The feedback means further functions to terminate the feedback action while the driver stage is in the idle mode, after the idle output signal has reached the neutral level. This occurs, for example, when the inductive load is substantially discharged and becomes a D.C. short circuit at which time the feedback action is terminated, thereby preventing the driver stage from introducing current into the discharged inductive load. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional drive circuit used for driving an inductive load, such as the primary winding of an isolation transformer. 
     FIG. 2 depicts various waveforms which illustrate the operation of the conventional FIG. 1 drive circuit. 
     FIG. 3 is a block diagram of one embodiment of the invention which utilizes differential input and output signals. 
     FIG. 4 depicts various waveforms illustrating the operation of the FIG. 3 drive circuit. 
     FIG. 5 is a schematic diagram of the first embodiment drive circuit. 
     FIG. 6 is a schematic diagram of a portion of the output stage and associated load of the first embodiment drive circuit, with various voltages labeled. 
     FIG. 7 is a schematic diagram of an improved error amplifier/time delay circuit for precisely controlling the duration of the high time period t high . 
     FIG. 8 is a block diagram of a second embodiment drive circuit having a single-ended data input and a single-ended data output. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring again to the drawings, a first embodiment drive circuit is depicted in FIG. 3. The drive circuit receives differential input signals RXOP and RXON on lines 27 and 29 which provides corresponding differential output signals RXP and RXN. The drive circuit includes an output driver stage 18 connected to an inductive load, such as the primary winding of an isolation transformer, represented by an equivalent circuit 20. A resistor is connected in parallel with the primary winding. The equivalent circuit includes an inductor L and parallel resistor R L . 
     The output data signal RXP on line 35 is fed back to the non-inverting input of an error amplifier 17. Output data signal RXN on line 37 is also fed back to the error amplifier after having been summed with an offset voltage produced by an offset voltage generator 40. Line 37 is connected to the positive terminal of generator 40, with the negative terminal of the generator being connected to the inverting input of error amplifier 17 by way of line 42. 
     The error amplifier 17 receives an enable signal on line 26 which is produced by a receive squelch circuit (not depicted). The output of the error amplifier 17 controls a time delay circuit 14 which forwards a delayed control signal on line 30 to the output driver stage 18. 
     Operation of the first embodiment driver circuit will now be described in connection with FIG. 3 and the timing diagram of FIG. 4. When differential input data RXOP and RXON are being received, the receive squelch (not depicted) will cause the enable signal to go high thereby overriding the operation of error amplifier 17. This occurs at time A in FIG. 5. Circuitry not shown will reset the time delay circuit thereby causing the delay control signal on line 30 to drop in magnitude. 
     The low magnitude delayed control signal will not affect the operation of the output driver stage 18 so that the input data RXOP and RXON will be retransmitted as output data RXP and RXN. The FIG. 4 timing diagram shows an output data differential signal which represents the voltage difference between output signals RXP and RXN. 
     When the input data (data packet) terminates at time B, the receive squelch causes the enable signal to go low. The low enable signal removes the override from error amplifier 17, thereby rendering the error amplifier operational. When the override is removed, amplifier 17 also actuates the time delay circuit 14 which causes the delayed control signal on line 30 to increase in magnitude in accordance with an RC time constant. 
     Also at time B, it can be seen that the input data RXOP and RXON are forced by circuitry not shown to go to their respective maximum values. This causes the output data differential signal (the difference between RXP and RXN) to go to a maximum value. Thus, signal RXOP (FIG. 3) goes to the maximum high value and signal RXON goes to the maximum low value. This is the beginning of the high time period t high . 
     The delayed control signal continues to increase in magnitude until it reaches a predetermined threshold voltage at time C. The time period from point B to point C is the high time period t high  which must fall within a specified minimum and maximum values, as previously explained. 
     During period t high , the polarity and magnitude of the differential feedback signal applied to the inputs of error amplifier 17 is such that the noninverting amplifier input on line 35 exceeds the inverting input on line 42 by a considerable amount. Amplifier 17 and time delay circuit 14 are implemented so that the differential feedback signal magnitude at this time will not affect the increase in the delayed control signal. Accordingly, the control signal will continue to increase as shown in the FIG. 4 timing diagram. 
     At time C, the delayed control signal will reach a predetermined threshold voltage. At this point, the control signal will start to disable the output of the output driver stage 18 by forcing positive output signal RXP to drop and negative output signal RXN to increase. This will cause, by definition, the output data differential signal to drop in magnitude as inductor L proceeds to discharge. This action also causes the differential feedback signal, the difference in magnitude between the voltages applied to the error amplifier inputs, to also decrease. 
     The magnitude of the output data differential signal will decrease to zero volts and then change from a positive to a negative polarity. The change in polarity indicates that the negative going output signal RXP has proceeded to slightly undershoot the midlevel signal point and the positive going output signal RXN has proceeded to slightly overshoot the midlevel point. 
     At time D, the magnitude of the negative polarity output data differential signal is equal to the offset voltage V OS  produced by generator 40. The differential feedback signal applied to the error amplifier 17 is at substantially zero volts at this point. Error amplifier 17 will then proceed to operate in a linear mode and provide negative feedback so as to limit any further increase in the magnitude of the delayed control signal. The negative feedback action will hold the differential output of the output driver stage at the offset voltage, sometimes referred to as the neutral level, while the inductor L has an opportunity to further discharge. 
     Once the inductor has discharged, it will appear as an effective D.C. short circuit. This will cause the output data differential signal to approach the zero volt level as shown at point E. This will also cause the differential feedback signal to depart from zero volts and approach the offset voltage V OS  produced by generator 40. The error amplifier 17 will switch back to a nonlinear mode and will no longer be able to control the magnitude of the delayed control signal. The time delay circuit 14 will then further increase the magnitude of the delayed control signal, as can be seen in FIG. 4. However, the driver stage is implemented in a manner such that it is not capable of responding to the increased delay control signal, as will be explained in greater detail below. Thus, feedback action is no longer provided and the output data differential signal will remain at zero volts. 
     The inductive load L of the isolation transformer is fully discharged and will not adversely impact receipt of the next data packet. Further, the magnitude of the undershoot/overshoot has been limited to the offset voltage produced by generator 40 and is independent of the duration of the high time period t high . 
     FIG. 5 is a schematic diagram of the FIG. 3 first embodiment drive circuit. The output driver stage 18 includes a differential amplifier made up of transistors Q 5  and Q 6  and load resistors R 3  and R 4 . The bases of transistors Q 5  and Q 6  are connected to lines 27 and 29 which carry the data input signals RXOP and RXON, respectively. Load resistors R 3  and R 4  of differential amplifier drive a pair of emitter followers which include transistors Q 9  and Q 10 . The emitters of transistors Q 9  and Q 10  provide the output data signals RXP and RXN on lines 35 and 37, respectively. 
     Differential feedback signals are produced at resistors R 5  and R 6 , each having a terminal connected to the respective differential outputs on lines 35 and 37. Resistor R 5  is connected to a current source I 4  which provides a level-shifting voltage. Similarly, resistor R 6  is connected to a current source I 5 , equal to current source I 4 , which provides a level-shifting voltage. 
     The offset voltage generator 40 is implemented by making resistor R 6  slightly larger than R 5  so that the voltage drop across R 6  is greater than that across R 5  by an amount equal to the desired offset voltage V OS . 
     The error amplifier 17 includes a pair of transistors Q 1  and Q 2  having bases connected to lines 42 and 35a, respectively, which carry the levelshifted differential feedback signals The emitters of Q 1  and Q 2  are connected to a common current source I 1 . The collector of Q 1  is connected to the positive power supply by way of a parallel connection of resistor R 1  and capacitor C which make up the time delay circuit 14. The collector of Q 2  is connected directly to the power supply. 
     Error amplifier 17 also includes a transistor Q 3  having an emitter and collector connected to the emitter and collector, respectively, of transistor Q1. The base of Q 3  is connected to line 26 which carries the enable signal. 
     The collectors of Q 1  and Q 3  are also connected to the base of an emitter follower-configured transistor Q 4 . The collector of Q 4  is connected to the positive supply and the emitter is connected to the common bases of a pair of transistors Q 7  and Q 8  by way of a resistor R 2 . A current source I 2  is connected between resistor R 2  and the circuit common to provide level shifting. Line 30 at the bases of transistors Q 7  and Q 8  carries the delayed control signal. 
     The collector and emitter of transistor Q 7  are connected in common with the collector and emitter, respectively, of transistor Q 5  of the output driver stage 18. Similarly, the collector and emitter of transistor Q 8  are connected in common with the collector and emitter, respectively, of transistor Q 6  of the output driver stage. 
     A brief description of the operation of the various components shown in FIG. 5 which comprise the first embodiment drive circuit will now be given with reference also to the FIG. 4 timing diagram. When a data packet is being received, the receive squelch causes the enable signal to go high as shown at point A of FIG. 4. This will cause transistor Q 3  to turn on and alter the charge on the timing capacitor C of the time delay circuit 14. This also causes the delayed control signal at line 30 to drop in magnitude. Since the collector of transistor Q 1  is pulled down by enable transistor Q 3 , the error amplifier 17 is effectively overridden and cannot function. 
     The low delayed control signal at line 30 will hold transistors Q 7  and Q 8  off. Accordingly, the collectors of Q 5  and Q 6  are free to change and the output driver stage 18 is permitted to retransmit the received data packet as shown by the input data differential signal and the output data differential signal in FIG. 4. 
     At the end of the data packet, at point B, the enable signal is caused to go low by the receive squelch. In addition, the data inputs RXOP and RXON are both forced to their respective maximum states, with RXON held at a low level and RXOP held at a high level. Thus, the input data differential signal will be at a maximum positive value. At this point, the data output signal RXN will be at its maximum negative value and output RXP will be at its maximum positive value. Accordingly, the output data differential signal will also be at a maximum positive value. Thus, the feedback signal on line 42 will be at a low value and the feedback signal on line 35a will be at a high value. This is represented by the positive differential feedback signal of FIG. 4 which will cause transistors Q 1  and Q 2  of the error amplifier 17 to be off and on, respectively. In addition, transistor Q 3  will be turned off by the low enable signal. 
     Since the data input signal RXOP is held high and input signal RXON is held low, transistor Q 6  will be conductive and transistor Q 5  will be off. The magnitude of the delayed control signal will be relatively low, therefore, transistors Q 7  and Q 8  will also be off. Accordingly, all of the current sunk by current source I 3  will be provided by transistor Q 6 . Thus, the collector of voltage of Q 6  will be at a minimum value and the collector of voltage of Q 5  will be at a maximum value. 
     Since transistors Q 3  and Q 1  of error amplifier 17 are both off, capacitor C will be free to discharge through resistor R 1 . This will cause the delayed control signal on line 30 to slowly increase beginning at point B. This is the beginning of the high time period t high . 
     At point C of FIG. 4, the delayed control signal is of sufficient magnitude to start to turn on transistors Q 7  and Q 8 . The delayed control signal is now at the previously noted threshold level. Transistors Q 7  and Q 8  will proceed to turn on and will conduct equal amounts of current. The total current flow through Q 7 , Q 8 , Q 5  and Q 6  will remain constant and will be equal to the current drawn by current source I 3 . Q 5  is off because the data input signal RXON is forced low. Accordingly, the current flow through Q 6  will be reduced by an amount equal to that drawn by Q 7  and Q 8 . The current flow drawn by Q 7  will cause the voltage at the collector of Q 5  to drop to a lower voltage level. This will cause the output data signal RXP to drop. 
     Although current through Q 8  will be provided by resistor R 4 , the total current flow through R 4  will decrease. Q 8  will draw one unit of current from R 4 , but the current flow through Q 6  will be reduced by two units since the total current flow to current source I 3  must remain constant. Thus, the net change will be a drop in current flow through resistor R 4  of one unit. The voltage at the collector of Q 6  will increase, thereby causing the data output signal RXN to increase in voltage. Thus, the increase in the delayed control signal on line 30 will begin to reduce the output data differential signal as shown in FIG. 4 at point C. This is the end of the high time period t high . 
     During the period immediately following point C, where the output data differential signal approaches zero volts, the magnitude of the differential feedback signal will be positive. Thus, transistor Q 1  will remain fully off and transistor Q 2  will remain fully on. Accordingly, the error amplifier 17 is not in the linear active region and will not control the magnitude of the delayed control signal at line 30. Rather, the magnitude of the control signal will continue to be controlled by the RC network of the time delay circuit 14. 
     As the current flow through transistors Q 7  and Q 8  increases due to the increase in the magnitude of the delayed control signal, the current flow through transistors Q 7  and Q 8  will approach the value of the current source I 3 . The current flow through transistor Q 6  will drop and the current flow through resistor R 3  will increase while the flow through resistor R 4  will decrease by an equal amount. Thus, the collector voltages of transistors Q 5  and Q 6  will approach equality. 
     FIG. 6 shows part of the FIG. 5 circuitry with various voltages labeled. The voltage difference between the collectors of transistors Q5 and Q 6  is labeled V D  and the base-emitter voltages of transistors Q 9  and Q 10  are labeled V BE9  and V BE10 , respectively. The output differential voltage is equal to self-induced EMF voltage of inductor L and is designated V L . As voltage V D  decreases in magnitude, the voltage across the inductor V L , as shown in FIG. 6 will eventually reverse polarity. This occurs just prior to point D of FIG. 4. The inductor voltage V L  will approach the offset voltage which time (point D of FIG. 4) the differential feedback signal will be at zero volts. Accordingly, the inputs to error amplifier 17 will be equal. Transistor Q 1  of the error amplifier 17 will become active and will limit any further increase in the base voltage of transistor Q 4 . Thus, the error amplifier 17 will proceed to control the magnitude of the delayed control signal through feedback action. In addition to providing a time delay, resistor R L  and capacitor C function to frequency compensate the feedback loop. 
     Typical voltage values may be helpful in explaining the operation of the subject drive circuit when feedback action commences. The voltages shown in FIG. 6 vary in accordance with the following equation: 
     
         V.sub.D =V.sub.BE9 -V.sub.L -V.sub.BE10                    (1) 
    
     Assume, by way of example, that the offset voltage V OS  produced by generator 40 is 60 millivolts and the base-emitter voltage V BE9  is nominally 700 millivolts when transistor Q 9  is fully conductive. Further assume that the collector voltage of Q 5  has almost approached the collector voltage of Q 6  so that V D  is 50 millivolts. When the inductor voltage V L , the output differential voltage, is equal to the offset voltage of 60 millivolts, equation (1) indicates that the base-emitter voltage V BE10  will be only 590 millivolts in comparison to the nominal 700 millivolts when the transistor is fully conductive. 
     Since the base-emitter voltage V BE10  is substantially less than the base-emitter voltage when the transistor is fully conductive, transistor Q 10  will be only slightly conductive. Stated differently, the self induced EMF voltage V L  will raise the emitter voltage of Q 10 , thereby causing transistor Q 10  to turn off to a large extent. Current drawn by current source I 5  will then be provided by inductor L rather than transistor Q 10 . Any further tendency of voltage V L  to exceed the offset voltage V OS  produced by generator 40 will result in a slight decrease in the delayed control signal because of feedback. The slight decrease will increase the voltage V D  which will cause transistor Q 10  to become even less conductive. This will cause additional current from source I 5  to become available to discharge inductor L and maintain the output differential voltage at the desired offset level V OS . 
     The differential output voltage will be held at a negative offset voltage V OS  until inductor L has completely discharged. At point E (FIG. 4), the inductor is substantially discharged and effectively becomes a D.C. short circuit. At this point transistors Q 7  and Q 8  will cause equal amounts of current to flow through resistors R 3  and R 4  so that the differential voltage V D  (FIG. 6) will be zero volts. 
     The change in the differential output voltage toward zero volts will cause the differential feedback signal to approach the offset voltage V OS . This action will cause transistor Q 1  of the error amplifier 17 to turn off. Capacitor C will resume discharging, causing the delayed control signal to increase in magnitude. This will cause transistors Q 7  and Q 8  to turn on an additional amount so that the two transistors are conducting all of the current supplied to current source I 3 . 
     It can be seen that it is not possible for the differential voltage V D  to change polarity, because of the manner in which the driver stage is implemented. Accordingly, the feedback loop is not capable of forcing the output data differential signal to be equal to the offset voltage V OS . Feedback action no longer occurs. At this point, the effective inductance L of the isolation transformer has been fully discharged. 
     Because the feedback loop does not attempt to force the voltage of the output data differential signal to equal the offset voltage V OS , the subject drive circuit does not introduce currents into the transformer primary which would adversely affect the capability of the transformer to handle the next data packet. As previously noted, prior art drive circuits utilizing continuously active feedback circuits will have a tendency to compensate for any offset inherent in the feedback loop by constantly attempting to slightly adjust the voltage across the transformer primary. Even very small changes in voltage across the transformer will tend to introduce undesired current flow through the transformer. 
     The magnitude of the offset voltage V OS  should be selected to be equal to or less than the maximum specified undershoot/overshoot. The larger the value of V OS , the more quickly the inductor L will discharge. At minimum, the value of V OS  should exceed the maximum value of any inherent offset in the feedback network so as to ensure that feedback action will terminate once the voltage of the inductor has reached substantially zero volts when the inductor is fully discharged. 
     As previously noted, the high time period t high  must typically comply with a specification which sets the minimum and maximum duration of the period. Although it is desireable to minimize the high time period t high , the period is not always well controlled, particularly if the drive circuit is implemented in monolithic integrated circuit form. By way of example, due to process variations and the like, the time period t high  provided by the time delay circuit 14 and the error amplifier 17 may vary by ±50%. Accordingly, drive circuits are typically designed to have a nominal high time period t high  substantially in excess of the specified minimum period to insure that the specified minimum period is met under worst case conditions. 
     FIG. 8 shows an alternative error amplifier/time delay circuit which provides a more precise high time period t high . Accordingly the nominal period can be set closer to the minimum specified, as desired. 
     The alternative error amplifier/time delay circuit includes transistors Q 1  and Q 2  having common emitters connected to a current source I 1 , with the bases of the two transistors connected to feedback lines 42 and 35a. The collector of transistor Q 1  is connected to a node 31. 
     Node 31 is connected to the base of transistor Q 4 , one terminal of a timing capacitor C and to the output of a current source I 7 . The collector of transistor Q 2  is connected to the other terminal of capacitor C and to the emitter and collector of transistors Q 11  and Q 12 , respectively. A Schottky diode D is connected in parallel with capacitor C. 
     Biasing voltages are provided by the combination of resistors R 7  and R 8  and a current source I 6  connected in series between the positive supply and ground. The base of transistor Q 12  is connected between resistor R 8  and the current source and the base of transistor Q 11  is connected between resistors R 7  and R 8 . 
     In operation, with reference also being made to the timing diagram of FIG. 4, the base voltages of transistors Q 11  and Q 12  are fixed with respect to the power supply. The electrode of capacitor C is connected to the emitter of transistor Q 11  and is clamped by the forward biased base-emitter junction of transistor Q 11 . 
     When the enable signal on line 26 goes high (point A), transistor Q 3  is turned on thereby discharging capacitor C. The free capacitor C electrode connected to node 31 will be pulled down until the base-emitter junction of transistor Q 12  is forward biased so as to clamp the voltage at the node. 
     When the enable signal goes low (point B), transistor Q 3  is turned off. At this point, transistor Q 1  of the error amplifier will also be off because of the polarity of the feedback signals on lines 35a and 42. This is the beginning of the high time period t high . 
     Once transistor Q 1  is off, capacitor C will become charged by current source I 7 . This will cause the voltage at node 31 to linearly increase. The voltage at node 31 will increase until the delayed control signal at node 30 reaches the threshold voltage (point C). This is the end of the high time period t high . 
     At the threshold voltage, transistor Q 4  will cause transistors Q 7  and Q 8  to turn on, thereby causing the outputs of the drive circuit to approach the mid-level point. Eventually, feedback will cause transistor Q 1  of the error amplifier to turn on thereby preventing the voltage at nodes 30 and 31 from increasing further (point D). 
     Once the inductor has been substantially discharged (point E), the feedback signal will again become positive causing transistor Q 1  to turn back off. Current source I 7  will then proceed to continue charging capacitor C until the voltage at node 31 exceeds the emitter voltage of Q:: by approximately 500 millivolts. At that point, Schottky diode D will become forward biased, thereby clamping the voltage. 
     The duration of the high time period t high  is as follows: ##EQU1## where C is the capacitance of capacitor C; 
     ΔV is the magnitude of the voltage swing of node 31; and 
     I 7  is the magnitude of the current source I 7 . 
     Current sources I 2  and I 6  provide current developed by an internal (to the integrated circuit) reference voltage V REF  (not depicted) and an internal resistor R INT  (not depicted). Current source I 7  provides current developed by the internal reference voltage V REF  and a precision external resistor R EXT  (not depicted). The voltage V 1  at the beginning of the ΔV voltage swing is equal to the supply voltage minus the sum of the voltage drops across internal resistors R 7 , R 8  and the base-emitter voltage of transistor Q 12 . Accordingly, voltage V 2  is proportional to the reference voltage V REF  and the internal resistances as follows: 
     
         V.sub.1 α(R.sub.7 +R.sub.8)I.sub.6                   (3) 
    
     or ##EQU2## 
     Since resistors R 7 , R 8  and R INT  track one another, voltage V 1  will be proportional to the reference voltage V REF  as follows: 
     
         VαV.sub.REF                                          (5) 
    
     The voltage V 2  at the end of the ΔV voltage swing is the voltage at node 31 when the delayed control signal at line 30 reaches the threshold voltage. At this point, the voltage at the bases of transistor Q 7  and Q 8  will be equal to the high data input R XOP  applied to the base of transistor Q 6  which is forced high at this time. The voltage V 2  at node 31 will be equal to the threshold voltage at node 30 plus the voltage drop across R 2  and the base-emitter junction of transistor Q 4 . Accordingly, voltage V 1  will be approximately proportional to the external reference voltage V REF  and internal resistor R 2  as follows: 
     
         V.sub.2 αR.sub.2 I.sub.2                             (6) 
    
     or ##EQU3## 
     Since resistor R 2  and R INT  will track one another, voltage V 2  is proportional to the reference voltage as follows: 
     
         V.sub.2 αV.sub.REF                                   (8) 
    
     It can be seen from equations (2), (5) and (6) that the high time period t high  is proportional to the external resistor R EXT  and the capacitor C as follows: ##EQU4## where k is a proportionality constant. or ##EQU5## 
     Thus, the high time period t high  will vary with the capacitor C and the external precision resistor R EXT  only. The period will not be substantially affected by variations in the values of the internal resistors. The variations in period t high  are held to ±15% as compared to ±50% for conventional time delay circuits as shown in FIG. 1. 
     Referring to the block diagram of FIG. 8, a second embodiment of the invention is disclosed. This embodiment is a single-ended drive circuit, as opposed to the first embodiment differential circuit. The second embodiment is powered to positive and negative supply voltages. 
     The drive circuit includes an output driver stage 18 which receives the data packets or other form of input data on line 25 and retransmits the data packet to the output on line 44. Line 44 is coupled to a load 20 which represents the primary of an isolation transformer together with a parallel resistor R L . The effective inductance of the transformer is represented by inductor L. 
     The second embodiment drive circuit includes an error amplifier -7 which is controlled by an enable signal on line 26. One input of the amplifier, the non-inverting input, is connected to ground and the second input (the inverting input) is connected to the data output line 44 by way of an offset voltage generator 40. 
     The output of amplifier 17 controls a time delay circuit 14 which produces a delayed control signal on line 30. The delayed control signal functions to force the output of the output driver stage 18 to ground depending upon the level of the signal. 
     The enable signal is present (high) when data are being received on line 25 by the output driver stage 18. The high enable signal will override the operation of the error amplifier 17 so that the level of the feedback signal on line 42 will be ignored. Under these conditions, with the enable signal high, the error amplifier 17 and the time delay circuit 14 will not interfere with the transmission of data through the output driver stage 18. 
     When the data packet transmission is completed, the data input of line 25 goes to a fixed high value. In addition, the enable signal on line 26 is caused to go low thereby removing the error amplifier 17 override. Accordingly, amplifier 17 becomes operational, but does not yet control the operation of the driver stage 18. 
     The low enable signal will also cause the error amplifier to actuate the time delay circuit 14 which will, in turn, cause the delayed control signal at line 30 to start to rise. This is the beginning of the high time period t high . The increase in the delayed control signal voltage will be controlled by an RC network in circuit 14. At this point, the data output on line 44 of the output driver stage is at a high voltage which is greatly in excess of the offset voltage V OS  produced by generator 40. Accordingly, the voltage on line 42 applied to the inverting input of amplifier 17 will exceed zero volts. 
     The delayed control signal at line 30 will eventually reach a threshold voltage. At that time, the output drive stage will respond to the control signal and the output of the stage will proceed to be shut down. This action will cause the output voltage on line 44 to drop as the inductor proceeds to discharge. This is the end of the high time period t high . 
     Eventually, the output voltage across inductor L will drop to zero volts and then will undershoot zero volts by going negative. Once the magnitude of the undershoot is equal to the offset voltage provided by generator 40, the input voltage to the inverting input of amplifier 17 will be at zero volts and the amplifier will become linear. Amplifier 17 will respond by preventing the control voltage from increasing further. 
     By way of feedback action, the magnitude of the control voltage at line 30 will be maintained at a level sufficient to maintain the output voltage on line 44 at a negative value equal to the offset voltage V OS . During this period, the inductor will discharge. 
     Once the discharge has been completed, the inductor L will become a D.C. short circuit and will force the output on line 44 to zero volts. The feedback voltage on line 42 will go positive by V OS . This action will prevent the error amplifier from further controlling the output of the output driver stage. Eventually, the output of the stage will be forced to zero volts by the inductor, thereby ending the sequence. 
     Thus, two embodiments of a novel drive circuit have been disclosed along with a time delay circuit/error amplifier. Although the invention has been described in some detail, it is to be understood that variations changes can be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.