Abstract:
In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump and the second charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

Description:
BACKGROUND  
       [0001]     The phase-locked loop (PLL) is a versatile electronic circuit used in a wide variety of applications, including frequency synthesis, clock recovery, clock multiplication, and clock regeneration. In large, high-speed integrated circuits (including application-specific integrated circuits, field-programmable gate arrays, network processors, and general purpose microprocessors), PLLs have become commonplace. On-chip phase-locked loop clock multipliers are used on these chips to generate a high-frequency clock signal that is a multiple of, and in phase with, a system clock or I/O clock. PLLs may also be used on these chips to resynchronize and realign clocks in deep clock distribution trees to reduce clock skew.  
         [0002]      FIG. 1  illustrates an example block diagram of a PLL  100 . The PLL  100  includes a phase-frequency detector (PFD)  110 , a charge pump (CP)  120 , a filter (e.g., low pass filter (LPF))  130 , and an oscillator  140 . The output frequency of the oscillator  140  is controlled by one or more input control signals. In operation, the PLL  100  adjusts the oscillator  140  to match (in both frequency and phase) a reference input  160 . The PLL  100  may also include a divider  150  on a feedback loop from the oscillator  140  to the PFD  110 . The divider  150  takes PLL output  165  and divides it by N so that the divided signal  170  is compared to the reference input. This enables the PLL output  165  to be N times higher in frequency than the reference input  160 , allowing the PLL  100  to perform frequency multiplication.  
         [0003]     A self-biased PLL (SBPLL) is used to create on-chip PLLs that have low jitter and are relatively insensitive to integrated circuit process variations, supply voltage and operating temperature (PVT). However, a major weakness of the SBPLL is that the oscillator output is subject to amplitude variability and common mode disturbances during dynamic operation of the PLL (e.g., acquisition, locking). In particular, operational correction can lead to the front-end oscillator amplifier and the following amplifying stages (the so-called “post-oscillator amplifiers”) being biased out of their optimal range (sweet spot), causing pulse evaporation (truncation, or dropped output clocks) and functional failure. This problem manifests as a non-monotonic oscillator control surface (output frequency versus control inputs) which may lead to one or more of the following: long lock time or lock failure due to positive feedback, sensitivity to power supply noise, and functional sensitivity to large reference and/or feedback clock noise.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]     The features and advantages of the various embodiments will become apparent from the following detailed description in which:  
         [0005]      FIG. 1  illustrates an example phase-locked loop circuit, according to one embodiment;  
         [0006]      FIG. 2  illustrates an example self-biased phase-locked loop circuit, according to one embodiment;  
         [0007]      FIG. 3A  illustrates example bias generators for a self-biased phase-locked loop circuit, according tone embodiment;  
         [0008]      FIG. 3B  illustrates example bias generators for a self-biased phase-locked loop circuit, according to one embodiment;  
         [0009]      FIG. 4  illustrates an example of a multi-stage oscillator, according to one embodiment; and  
         [0010]      FIG. 5  illustrates an example of a stage of an oscillator, according to one embodiment.  
     
    
     DETAILED DESCRIPTION  
       [0011]      FIG. 2  illustrates an example of an embodiment of a self-biased phase-locked loop (SBPLL)  200 . The SBPLL  200  includes a phase-frequency detector (PFD)  210 , a charge pump (CP)  220 , a filter (e.g., LPF)  230 , a bias generator (BG)  240 , and an oscillator  250 , and may include a divider  260 . The output frequency of the oscillator  250  is controlled by one or more control inputs. In some embodiments, the oscillator  250  may be voltage controlled (voltage controlled oscillator (VCO)). In other embodiments, the oscillator  250  may be current controlled, or controlled by a combination of one or more current inputs and/or one or more voltage inputs.  
         [0012]     The SBPLL  200  uses negative feedback to adjust the oscillator  250  such that the frequency of an oscillator output  255  or a divided oscillator output  265  matches (in both frequency and phase) a reference input  270 . The PFD  210  compares the frequency and phase difference between the reference signal  270  and the oscillator/divided oscillator output  255 / 265  and generates one or more output signals based on this difference. As illustrated, the PFD  210  may generate an UP signal  212  or a DOWN signal  214 . The PFD  210  generates UP signals  212  when the frequency (phase) of the oscillator/divided oscillator output  255 / 265  is lower than (lags) the reference signal  270 . The PFD  210  generates DOWN signals  214  when the frequency (phase) of the oscillator/divided oscillator output  255 / 265  is higher than (leads) the reference signal  270 . The UP and DOWN signals (charge pulses)  212 ,  214  generated are based on the amount of lag or lead respectively. The CP  220  and the LPF  230  smooth and condition the pulses from the PFD  210  and generate two control signals, a proportional control signal  232  and an integrating control signal  234 .  
         [0013]     The integrating control signal  234  represents the net accumulated (integrated) charge from the previously generated UP signals  212  and DOWN signals  214 . The integrating control signal  234  also represents the dominant pole of the transfer function for the PLL  200 . The proportional control signal  232  represents, more directly, the instantaneous UP signals  212  and DOWN signals  214 . The proportional control  232  also represents the zero of the transfer function for the PLL  200 . The proportional control signal  232  and the integrating control signal  234  are fed to the BG  240 . The BG  240  processes these signals and generates control/bias signals, PBias  242  and NBias  244 .  
         [0014]      FIG. 3A  illustrates a schematic of a portion of an example embodiment of a SBPLL  300 . The SBPLL  300  includes a charge pump  310  (e.g.,  220  of  FIG. 2 ), a filter  320  (e.g.,  230 ), a bias generator  330  (e.g.,  240 ), and an oscillator  340  (e.g.,  250 ). The charge pump  310  includes an integrating charge pump (CP 1 )  312  and a proportional charge pump (CP 2 )  314 . The CP 1   332  produces an integrating control signal  316  and the CP 2   314  produces a proportional control signal  318 . The filter  320  includes a capacitor  322  to filter the integrating control signal (filtered integrating control signal  326 ) and a capacitor  324  to filter the proportional control signal (filtered proportional control signal  328 ). The bias generator  330  includes an NBias generator  350  and a PBias generator  360 . The NBias generator  350  includes an operational amplifier  352  and transistors  354 ,  356 , and  358 . According to one embodiment, the transistors  354  and  356  may be NMOS FETs and the transistor  358  may be a PMOS FET connected as a diode. The PBias generator  360  includes transistors  362 ,  364 , and  366 . According to one embodiment, the transistors  362  and  364  may be NMOS FETs and the transistor  366  may be a PMOS FET connected as a diode.  
         [0015]     The integrating control signal  316  from CP 1   312  passes through the filter  320  (drives capacitor  332 ). The filtered integrating control signal  326  is received by the Nbias generator  350  (as one input of the operational amplifier  352 ). An output  359  of the Nbias generator  350  is provided to the Pbias generator  360  (gate of transistor  362 ) and an “N” input of the oscillator  340 . The proportional control signal  318  from the CP 2   314  passes through the filter  320  (drives a capacitor  334 ). The filtered integrating control signal  328  is provided to the Pbias generator  360 . An output  368  of the Pbias generator  360  is provided to a “P” input of the oscillator  340 .  
         [0016]     A portion of the filtered integrating control  326  signal is fed to the “P” input of the oscillator  340  via the NBias generator  350  and the Pbias generator  360  (transistors  362 ,  364 ). This provides some amount of biasing balance in the oscillator oscillatory signals. However, the filtered proportional control signal  328  is fed only to the “P” input of the oscillator  340 . This tends to unbalance the oscillator bias during transitions in the proportional control. In fact, the oscillator  340  may act as a common mode amplifier to the “P” input, causing common mode shift and amplitude shrink in oscillator output  342 , and stress to the post-oscillator path. Common mode shift and amplitude shrink in the oscillator output  343  manifests as a non-monotonic oscillator control surface (output frequency versus control inputs). A non-monotonic oscillator control surface may lead to one or more of the following: pulse evaporation (truncation, or dropped output clocks), long lock time or lock failure due to positive feedback, sensitivity to power supply noise, and functional sensitivity to large reference and/or feedback clock noise.  
         [0017]      FIG. 3B  illustrates a schematic of a portion of an example embodiment of a SBPLL  370  for reducing the oscillator common mode gain. The SBPLL  370  is similar to the SBPLL  300  of  FIG. 3A  in that it includes the charge pump  310 , the filter  320 , and the oscillator  340 . The SBPLL  370  also includes a bias generator  380 . The bias generator  380  includes an Nbias generator  390  and the Pbias generator  360  of  FIG. 3A . The Nbias generator  390  includes the operational amplifier  352 , and the transistors  354 ,  356 ,  358 . The Nbias generator  390  also includes a transistor  392  (coupling transistor) in parallel to the transistor  358 . The transistor  392  receives the filtered proportional control signal  328 . Receiving the filtered proportional control signal  328  provides a modified feedback path from the CP 2   314  to the N input of the oscillator  340 . The modified feedback reduces the oscillator common mode gain.  
         [0018]     The feedback path transfers a portion of the filtered proportional control signal  328  to the N input of the oscillator  340  via the Nbias generator  390  as output  394 . The filtered proportional control signal  328  is added to the N input of the oscillator  340  in a direction, and with an amplitude, that minimizes the oscillator  340  signal attenuation to stabilize the common mode amplification. The portion of the filtered proportional control signal  328  coupled into the oscillator  340  via the NBias generator  390  may be determined by a ratio of the number of coupling transistors to the total number of coupling transistors and diode-connected transistors (acting as resistive elements). As illustrated in  FIG. 3B , the portion of filtered proportional control  328  coupled into the NBias generator  390  is approximately 50% based on the use of one coupling transistor  392  and one diode-connected transistor  358  (1 coupling divided by total of 2 (1 coupling plus 1 diode)).  
         [0019]     The feedback of output from the CP 2   314  into the Nbias generator  390  stabilizes the behavior of the oscillator  340  during a perturbation in the phase-locked loop. During an event where the output of the CP 2   334  drops to a lower voltage, the oscillator  340  increase in frequency is accompanied by stable output common mode with little attenuation.  
         [0020]      FIG. 4  illustrates an embodiment of an oscillator  400  (e.g.,  340  of FIGS.  3 A-B). The oscillator  400  includes a plurality of stages  410  (five stages are illustrated) organized as a ring oscillator. Each stage feeds its output to the input of the succeeding stage, with the output of the final stage feeding back to the input of the first stage. The oscillator receives a Pbias input  420  (e.g.,  368  of FIGS.  3 A-B) and an Nbias input  430  (e.g.,  359  of  FIG. 3A, 394  of  FIG. 3B ) and provides an output  440  (e.g.,  342  of FIGS.  3 A-B).  
         [0021]      FIG. 5  illustrates an embodiment of an oscillator stage  500  (e.g.,  410  of  FIG. 4 ). The oscillator stage  500  includes a differential pair of transistors  505 ,  510 , a current source (current tail) transistor  535 , transistor pairs  540  and  545  acting as voltage controlled resistors, transistors  550  and  555  acting as load capacitors, and transistors  560  and  565  acting as metal options to provide a means for adjusting, during device fabrication, the maximum frequency of the oscillator. A Pbias input  570  (e.g.,  420  of  FIG. 4 ) is provided to the transistor pairs  540  and  545 . An Nbias input  580  (e.g.,  430  of  FIG. 4 ) is provided to the current source transistor  535 . Differential inputs  515  and  520  from a previous oscillator stage are provided to the differential transistor pair  505 ,  510 . Differential outputs  525  and  530  are provided to a next oscillator stage.  
         [0022]     Although the various embodiments have been illustrated by reference to specific embodiments, it will be apparent that various changes and modifications may be made. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment.  
         [0023]     Different implementations may feature different combinations of hardware, firmware, and/or software. It may be possible to implement, for example, some or all components of various embodiments in software and/or firmware as well as hardware, as known in the art. Embodiments may be implemented in numerous types of hardware, software and firmware known in the art, for example, integrated circuits, including ASICs and other types known in the art, printed circuit broads, components, etc.  
         [0024]     The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.