Abstract:
A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    This disclosure relates to polyphase decimation Finite Impulse Response (FIR) filters and to methods for polyphase decimation FIR filtering. More particularly, the disclosure relates to polyphase decimation FIR filters and methods which exhibit low power consumption and small chip area. 
         [0003]    2. Discussion of Related Art 
         [0004]    Multi-rate systems have been used in digital signal processing (DSP) and continue to find applications in new and emerging areas. Small area and low power consumption are important criteria in the design of DSP systems. These criteria necessitate efficient implementation of basic building blocks of multi-rate signal processing, namely decimators and interpolators. FIR filters are usually preferred in multi-rate systems over infinite impulse response (IIR) filters because of their inherent stability, easily-designed linear phase response and computational efficiency. Polyphase decomposition of an FIR filter is a power efficient technique as it allows operation of subfilters at lower data rates and also computation of only useful output samples in the case of decimation. 
         [0005]    Multiplication is a major source of power dissipation in FIR filters. Techniques have been proposed to achieve low power multipliers. A differential coefficient technique has been proposed to reduce coefficient precision in single rate FIR filters. Notwithstanding these developments, there is a need for improved decimation FIR filters. 
       SUMMARY 
       [0006]    According to one embodiment, a polyphase decimation FIR filter apparatus comprises an integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples. The integrator circuit has a pole at dc and therefore can experience overflow. The use of two&#39;s complement arithmetic resolves this overflow situation by keeping the integrator word width equal to the maximum word width that can appear at the filter output for a given input. If we denote the input bit precision by L and the maximum fixed point gain of the filter by G, then the integrator word width=L+G. Using two&#39;s complement binary format in the following filter and the same word width, with the filter transfer function being H(z)·(1−z −1 ), where H (z) is the original filter z−domain transfer function, outputs can be computed correctly. 
         [0007]    In embodiments the polyphase FIR filter circuit uses a plurality of independent multiplier accumulator circuits operating concurrently on input samples. Each multiplier accumulator circuit performs multiply and accumulate operations for k input cycles, where k is a decimation factor, using sets of k coefficients. After every k input cycles, the coefficients of the multiplier accumulator circuits are changed, but the multiplier accumulator circuits continue accumulating the results. One of the multiplier accumulator circuits is selected to produce an output value after every k input cycles. Thereafter, that particular multiplier accumulator circuit is reset and starts accumulating results from a next set of samples and a next set of coefficients. The sets of coefficients applied to each of the multiplier accumulator circuits and the multiplier accumulator circuit selected for output change in a cyclic manner every k input cycles. 
         [0008]    In some embodiments, a polyphase decimation FIR filter apparatus comprises: a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit comprising: a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    For a better understanding of the embodiments, reference is made to the accompanying drawings, which are incorporated herein by reference and in which: 
           [0010]      FIG. 1  is a schematic block diagram of a conventional FIR filter; 
           [0011]      FIG. 2  is a schematic block diagram of a decimation FIR filter in accordance with embodiments; 
           [0012]      FIG. 3A  is a schematic block diagram of a decimation FIR filter in accordance with additional embodiments; 
           [0013]      FIG. 3B  is a graph of coefficient value as a function of filter tap for an FIR filter having 325 taps and a coefficient size of 15 bits; 
           [0014]      FIG. 3C  is a graph of coefficient value as a function of filter tap using the differential coefficient method; 
           [0015]      FIG. 4  is a schematic block diagram of the third order integrator of  FIG. 3A , in accordance with embodiments; 
           [0016]      FIG. 5  is a schematic block diagram of a polyphase FIR filter circuit in accordance with embodiments; 
           [0017]      FIG. 6  is a schematic block diagram of a multiplier accumulator circuit shown in  FIG. 5 , in accordance with embodiments; 
           [0018]      FIG. 7  is a schematic block diagram of a multiplier accumulator circuit shown in  FIG. 5 , in accordance with additional embodiments; 
           [0019]      FIG. 8  is a flowchart of a process performed by the polyphase FIR filter circuit of  FIG. 5 , in accordance with embodiments; and 
           [0020]      FIG. 9  is a table that provides synthesis results of an example FIR filter. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    A block diagram of a conventional FIR filter  100  is shown in  FIG. 1 . The FIR filter  100  includes multipliers  110 , summing units  120  and delay elements  130 . The number of multipliers  110  corresponds to the number of filter taps in the FIR filter  100 . Input signal samples x(n) are multiplied by respective filter coefficients h k  in multipliers  110  and the results, in each stage except the first stage, are summed with the delayed results from the previous stage to provide an output y(n). 
         [0022]    The input signal samples x(n) and the coefficients h k  are multi-bit values. The multiplication performed by multipliers  110  in conventional FIR filters is a major source of power dissipation. Further, the power dissipation increases as the number of filter taps in the FIR filter increases. 
         [0023]    Conventional polyphase decimation filters for decimation by k include k subfilters. In the polyphase subfilters, a set of k successive input samples is convolved with sets of k coefficients, each coefficient taken from one of the k subfilters, in calculation of an output. The sets of coefficients are as follows: 
         [0024]    First set: h[0], . . . ,h[k−2], h[k−1] 
         [0025]    Second set: h[k], . . . ,h[2k−2], h[2k−1] and 
         [0026]    Third set: h[Mk−k+1], . . . ,h[Mk−2], h[Mk−1], 
         [0027]    where k is the decimation factor and M is the number of subfilters. 
         [0028]    The partial response to one set of inputs is combined with the response to subsequent sets of inputs until the set of input samples is shifted out of the filter. This fact can be exploited to build a filter structure in which computation can be carried out in independent circuits which are multiplier accumulators. The proposed polyphase decimation FIR filter architecture uses M independent multiplier accumulator circuits operating concurrently on input samples x(n), where M is the number of filter taps T in the filter divided by the decimation factor k. 
         [0029]    A schematic block diagram of a decimation FIR filter apparatus in accordance with embodiments is shown in  FIG. 2 . FIR filter apparatus  200  includes an integrator circuit  210  and a polyphase FIR filter circuit  220  connected in series. The integrator circuit  210  and the polyphase FIR filter circuit  220  operate in a modulo N configuration. The integrator circuit  210  receives an input word of P bits and provides an output of N bits to FIR filter circuit  220 . The polyphase FIR filter circuit  220  provides an output of N bits, where N is greater than P. The FIR filter apparatus  200  performs decimation by a decimation factor k. As discussed below, the decimation factor k may be programmable. 
         [0030]    The FIR filter apparatus  200  of  FIG. 2  takes advantage of a differential coefficient method to minimize the word length of the filter coefficients without compromising the frequency response of the filter, so that the multiply operation consumes less power than in conventional FIR filters. The differential coefficient method exploits the correlation between consecutive coefficients of an FIR filter and uses the difference between the coefficients which can be represented in smaller word lengths than full precision coefficients. The integrator circuit  210  and the FIR filter circuit  220  are discussed in detail below. 
         [0031]    An implementation of the FIR filter apparatus  200  is shown in  FIG. 3A . The FIR filter apparatus  200  includes a third order integrator circuit  310  and a polyphase FIR filter circuit  320 . The third order integrator circuit  310  and the FIR filter circuit  320  operate in a modulo 22 bit configuration. The third order integrator circuit  310  receives input samples x(n) of 6 bits and provides integrated input samples x i (n) of 22 bits to FIR filter circuit  320 . The FIR filter circuit  320  may utilize new filter coefficients which are derived as the third order difference of the original filter coefficients. The FIR filter circuit  320  provides output samples y(m) of 22 bits. The FIR filter circuit  320  also performs decimation by a decimation factor k. Thus, the filter apparatus  200  of  FIG. 3A  produces one output sample y(m) for every k input samples x(n). By way of example only, the FIR filter circuit  320  may perform decimation by a decimation factor of 24. 
         [0032]    The differential coefficient method is described with reference to  FIGS. 3B and 3C . An original FIR coefficient set having a coefficient size of 15 bits for a 325 tap FIR filter having an output precision of 22 bits for an input precision of 6 bits and a decimation factor of 24 is shown in  FIG. 3B . As shown, the coefficients have a wide range of values. The new FIR filter coefficients using the differential coefficient method are shown in  FIG. 3C . The new FIR filter coefficients of  FIG. 3C  represent the difference between consecutive coefficients and are represented by a 4 bit word length. 
         [0033]    In the example shown all the coefficients of the new FIR filter coefficients that have values of +/−1, 2, 3, 4 or 0, except for coefficients at the ends of the FIR filter. The vertical scale of  FIG. 3C  is expanded relative to the vertical scale of  FIG. 3B . By representing the coefficients with a small number of bits, the circuitry of the FIR filter can be simplified substantially. 
         [0034]    An implementation of integrator circuit  210  in accordance with embodiments is shown in  FIG. 4 . The integrator circuit  210  includes a first stage  410 , a second stage  412  and a third stage  414  connected in series. As described above, the integrator circuit  210  receives input samples x(n) of 6 bits and provides integrated input samples x i (n) of 22 bits to FIR filter circuit  220 . 
         [0035]    Each of the stages  410 ,  412  and  414  includes a summing unit  420  and a register  424 , which, in the example of  FIG. 4 , is a 22-bit register. A first input of each summing unit  420  receives input values and a second input of each summing unit  420  receives the output of register  424 . The output of the summing unit  420  is provided to register  424 , and the output of register  424  is provided to the following stage or to the FIR filter circuit  220 . 
         [0036]    A schematic block diagram of FIR filter circuit  220  in accordance with embodiments is shown in  FIG. 5 . The FIR filter circuit  220  includes a plurality of multiplier accumulator (MAC) circuits  510 ,  512 , . . .  520 , an output selector  530  and a controller  540 . The FIR filter circuit  220  performs decimation by a decimation factor k, such that the output sample rate is reduced by the factor k with respect to the input sample rate. The decimation is indicated in  FIG. 5  by decimation blocks  550 . However in practice, the decimation may be effected by operation of the MAC circuits  510 ,  512 , . . .  520  and the output selector  530 , such that no circuitry is associated with decimation blocks  550 . 
         [0037]    Each of the MAC circuits  510 ,  512 , . . .  520  receives integrated input samples x i (n) from integrator circuit  210  at a first input and receives filter coefficient values at a second input. The values are multiplied and accumulated as described below. Each of the MAC circuits  510 ,  512 , . . .  520  performs multiply and accumulate operations for k input cycles using sets of k coefficients. After every k input cycles, the coefficients of the MAC are changed, but the MAC circuits continue accumulating the results. One of the MAC circuits is selected for producing an output value y(m) after every k input cycles. Thereafter, that MAC circuit is reset and starts accumulating results from a next set of samples and a next set of coefficients. The sets of coefficients applied to each MAC circuit and the MAC circuit selected for output change in a cyclic manner. The selection of coefficients to be applied to each of the MAC circuits and the MAC circuit selected for output are controlled by the controller  540 . 
         [0038]    The FIR filter circuit  220  may include M MAC circuits, where M is based on the number of filter taps T in a particular FIR filter and the decimation factor k. In particular, the number M of MAC circuits in the FIR filter circuit  220  may be the number of filter taps T divided by the decimation factor k, rounded to the next higher integer if necessary. 
         [0039]    As shown in  FIG. 5 , the filter coefficients h are divided into M sets of coefficients and the sets of coefficients are applied to respective MAC circuits  510 ,  512 , . . .  520 . In particular, a first set of coefficients h k-1 , h k-2 , . . . h 0  is applied to MAC circuit  510  during a first period of k input cycles; a second set of coefficients h 2k-1 , h 2k-2 , . . . h k  is applied to MAC circuit  512  during the first period; and a last set of coefficients h Mk-1 , h Mk-2 , . . . h (M-1)k  is applied to MAC circuit  520  during the first time period. During consecutive time periods of k input cycles, the sets of coefficients are applied to successive MACs in a rotating manner as shown in  FIG. 5 . 
         [0040]    During each period of k input cycles, the integrated input samples x i (n)are multiplied in each MAC circuit by the respective coefficient values in a convolution operation. Thus, for example in MAC circuit  510  integrated input sample x i ( 0 ) is multiplied by coefficient h 0 , input sample x i ( 1 ) is multiplied by coefficient h 1 , etc., and the results are accumulated. After each period of k input cycles, the sets of coefficients applied to each MAC circuit are changed, as indicated by the second and following rows of coefficients in  FIG. 5 , and the MAC circuits continue to accumulate results. Every k input cycles, the output selector  530  selects one of the MAC circuits  510 ,  512 , . . .  520  for output, so that output values y(m) are produced at a rate which is reduced by the decimation factor k with respect to the rate of input samples. After a MAC circuit output is selected by output selector  530 , that MAC circuit is reset and begins accumulating a new set of input values multiplied by coefficients. 
         [0041]    A schematic block diagram of a multiplier accumulator circuit  510  in accordance with embodiments is shown in  FIG. 6 . The MAC circuits  512 , . . .  520  may have the same configuration. As shown in  FIG. 6 , multiplier accumulator circuit  510  includes a multiple constant multiplication (MCM) circuit  610 , a data selector  620  and an accumulator  630 . The MCM circuit  610  receives the input data values and performs multiplication of the input data values by the small word length coefficient values. As discussed above, the coefficients can be represented in small word lengths by utilizing a differential coefficient method which corresponds to the difference between coefficients rather than the full coefficient values. The MCM circuit  610  may perform multiplication of the data values by the small word length coefficients using shift and add operations rather than multipliers. Each MCM block MCM 1 , MCM 2 , etc shown in MCM circuit  610  can be implemented for each set of coefficients [h 0 , h k , . . . ,h (M-1)k ], [h k-1 , h 2k-1 , . . . , h Mk-1 ], etc respectively. 
         [0042]    The MCM circuit  610  provides multiple outputs corresponding to the data input value multiplied by several coefficient values. The data selector  620  selects an appropriate output of the MCM circuit  610  to be provided to accumulator  630 . The accumulator  630  includes a summing unit  640  and a register  650 . The summing unit  640  sums the value from data selector  620  with the value contained in register  650  and stores the new value in register  650 , thereby performing accumulation of the values. 
         [0043]    A schematic block diagram of multiplier accumulator circuit  510  in accordance with additional embodiments is shown in  FIG. 7 . MAC circuits  512 , . . .  520  may utilize the same circuit. In the embodiment of  FIG. 7 , the MCM circuit  610  and the data selector  620  of  FIG. 6  are replaced by a multiplier  710  and a coefficient memory  720 , such as a ROM (read only memory). The data input values are supplied to a first input of multiplier  710  and the coefficient values are supplied by coefficient ROM  720  to a second input of multiplier  710 . The multiplier  710  multiplies the data values by the corresponding coefficient values and provides outputs to accumulator  630 . The accumulator  630  accumulates the input values as discussed above. The coefficient ROM is addressed to provide sets of coefficient values as described above in connection with  FIG. 5 . The multiplier  710  may be relatively straightforward in view of the fact that the coefficient values from coefficient ROM may have only 2 or 3 bits. 
         [0044]    As indicated above, the decimation factor k of the polyphase FIR filter circuit may be programmable. The decimation factor k may be programmed by operating the FIR filter circuit with different coefficient values corresponding to different decimation factors. The decimation factor may be selected by an input signal to controller  540 . The controller  540  then controls the MCM circuit  610  of  FIG. 6  or the coefficient memory  720  of  FIG. 7  to provide the appropriate coefficient values corresponding to the selected decimation factor k. 
         [0045]    The polyphase FIR circuit can be implemented using the implementations of the multiplier accumulator circuits described herein and using many other implementations. The polyphase FIR filter circuit can be implemented in transpose or direct form, a transpose implementation being described herein. However, the polyphase FIR filter circuit is not limited to the disclosed implementations. 
         [0046]    A flowchart of a process performed by the polyphase FIR filter circuit of  FIG. 5  in accordance with embodiments is shown in  FIG. 8 . The process of  FIG. 8  may be controlled by the controller  540 . 
         [0047]    In act  810 , coefficient sets are applied to respective MAC circuits  510 ,  512 , . . .  520 . With reference to  FIG. 5 , the coefficient sets in the first row of coefficient sets are applied to respective MAC circuits  510 ,  512 , . . .  520 . In act  820 , the MAC circuits  510 ,  512 , . . .  520  multiply successive integrated input samples x i (n) by successive coefficients of the respective coefficient sets and the results are accumulated by the respective MAC circuits. 
         [0048]    In act  830 , a determination is made as to whether results have been accumulated for k input cycles. As indicated, processing for each input cycle includes multiplying the integrated input sample x i (n) by the coefficient value and accumulating the result. If it is determined in act  830  that results have not been accumulated for k input cycles, the process returns to act  820  to process the next integrated input sample. 
         [0049]    If it is determined in act  830  that results have been accumulated for k input cycles, an output value y(m) is provided from a selected MAC circuit. In particular, the output selector  530  selects one of the MAC circuits  510 ,  512 , . . .  520  to provide an output value. 
         [0050]    In act  850 , the controller  540  selects next coefficient sets to be applied to MAC circuits  510 ,  512 , . . .  520 . For example, the coefficient sets in the second row of  FIG. 5  may be applied to the respective MAC circuits. 
         [0051]    In act  860 , the controller  540  resets the current MAC circuit which has been selected to provide an output value and then selects a next MAC circuit to provide an output value after the next k input cycles. The process then returns to act  820  and integrated input samples are multiplied by coefficient values and accumulated as described above. 
         [0052]    A table providing synthesis results for an example filter is shown in  FIG. 9 . The table compares results for a conventional filter and the proposed filter. The example is a decimation FIR filter having a tap length of  308  and a decimation factor of 22. The table shows the combinational circuit area, the sequential circuit area, the overall circuit area, the total dynamic power and the critical path slack. As shown, the FIR filter described herein has a large savings in combinational area, which results in the large overall savings in area and power. When the same filter is used to implement multiple decimation ratios, the combinational logic used to implement different sets of coefficients will be huge. Therefore the percent saving in combinational area accrued by the disclosed FIR filter will far outweigh the percent increase in sequential area leading to a drastic overall saving. Although the critical path slack is not greatly affected, a timing analysis shows that the major contribution to critical path is from the MAC adder which can be easily pipelined for high frequency operation. 
         [0053]    Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.