Abstract:
A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to integrated circuits and more specifically to determining that the clock frequency of an integrated circuit is not within reference frequency. 
       BACKGROUND OF THE INVENTION 
       [0002]    Integrated circuits utilize clock signals for a variety of purposes. It is important that the clock signal be within a specified frequency range during operation of the circuit. Typically the clock signal will operate within a specified reference frequency range or within specification if the clock signal is outside of the range an error signal will be generated. It is desirable that a system be in place to monitor the frequency of the clock signal to provide an indication of whether the clock signal is within the specified range. Accordingly, what is needed is a system and method that provides good results in behavior and security performance, good behavior at high frequencies, low and very low frequencies (to avoid for example step by step working), and is insensitive to the input clock duty cycle. In addition, it is desired that the method and system has low power consumption, and provides a simpler and more effective solution for determining whether an input clock signal is within specification. The present invention addresses such a need. 
       SUMMARY OF THE INVENTION 
       [0003]    A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a block diagram of an integrated circuit. 
           [0005]      FIG. 1A  illustrates a simple block diagram of a frequency monitoring circuit in accordance with the present invention. 
           [0006]      FIG. 2A  shows an example where the clock signal is within the specified range. 
           [0007]      FIG. 2B  shows an example when the input clock is not within the frequency range. 
           [0008]      FIG. 3  is a functional diagram of an embodiment of a frequency cell monitor in accordance with the present invention. 
           [0009]      FIG. 4  is a timing diagram that illustrates an input clock signal in which the input clock is within specification. 
           [0010]      FIGS. 5-8  are timing diagrams that illustrate the operation of the frequency cell monitors of  FIG. 3 . 
           [0011]      FIG. 9  is a timing diagram that illustrates the clock frequency is out of specification. 
           [0012]      FIG. 10  is a timing diagram that illustrates the error flag indication is active when period is less than the delay indicating that the frequency of the input clock signal is within the specified frequency range. 
           [0013]      FIG. 11  is a timing diagram that illustrates the error flag indications for both even and odd pulses as well as the combined error flag indication. 
           [0014]      FIG. 12  is a diagram of an implementation of a frequency monitor cell in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    The present invention relates generally to integrated circuits and more specifically to determining that the clock frequency of an integrated circuit is not within reference frequency. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein. 
         [0016]      FIG. 1  is a block diagram of an integrated circuit  10 . The integrated circuit  10  could be, for example, a digital signal processor, a microcontroller or a variety of other devices that are part of an electronic device. Accordingly, typically the integrated circuit has one or more functional units  12  located therewithin. In addition, it is generally desirable to provide a frequency monitor  14  to provide an indication of the frequency of a clock signal on the functional unit  12  within the circuit  10 . 
         [0017]      FIG. 1A  illustrates a simple block diagram of the frequency monitoring circuit  14  in accordance with the present invention. As is seen, an input clock signal is delayed by delay element  15  to provide a reference signal (clock+τ(delay)). The reference signal and the input clock signal are provided to a signal processing unit  16 . The signal processing unit  16  then processes the input signal and the reference signal to provide an output signal indicative of the condition of the clock signal. What is meant by the condition of a signal is whether the signal is inside or outside of the specified frequency range. 
         [0018]      FIG. 2A  shows an example where the clock signal is within the specified frequency range. As is seen, when the period of the input signal (T) is greater than the delay (τ) the input clock is within the specified frequency. In this embodiment as is seen if the delay is active during the rising edge of input clock, the output clock is within specification. 
         [0019]      FIG. 2B  shows an example when the input clock is not within the frequency range. As is seen the clock frequency is fast on the rising edge of the clock signal, therefore the input clock is not within specification. 
         [0020]    Accordingly, as is seen, a frequency monitor is provided that accurately determines if an input clock is within a specified frequency. To describe a preferred embodiment of a frequency monitored cell in accordance with the present invention, refer now to the following description with the accompanying figures. 
         [0021]      FIG. 3  is a functional diagram of an embodiment of a frequency cell monitor  100  in accordance with the present invention. The monitor  100  includes a divider  102  on which separates the clock into even clock pulses and odd clock pulses. The even clock pulses are provided to delay  104   a  and the odd clock pulses are provided to delay  104   b.  To be fully independent of the input signal duty cycle, the input clock signal  102  is divided by two. In an embodiment the even and odd clock pulses are the even clock pulses derived from the input clock utilizing a divider-by-2 (D-latch). 
         [0022]    These delayed odd and even pulses along with the input signals (clock  2 A and clock  2 B) are then provided to frequency period monitors. They are combined together via an AND mechanism  108  to provide an indication of the condition of the clock signal. To describe the operation of this the frequency monitor in more detail refer now to the following. 
         [0023]      FIG. 4  is a timing diagram that illustrates an input clock signal in which the input clock is within specification (period  202 ). Outside of the frequency range (period  204 ) and the input clock signal is back within specification (period  206 ). 
         [0024]    The following examples illustrate providing an indication of the odd pulses as shown in  FIG. 3 . The corresponding indication is provided for the even pulses to provide the output signal indicative of the error flag. 
         [0025]    Accordingly, as is seen in  FIG. 5 , the clock signal is divided by 2 to provide a plurality of odd pulses,  252 ,  254  and  256 , that include the delays.  FIGS. 6 ,  7  and  8  are the same as  FIG. 5  but the delayed clock/2 signal pulses  352 ,  354  and  356  (shown in  FIG. 6 ) are provided. Accordingly if the period T is less than the delay then the error flag will be low indicating that the input clock signal is within the specified frequency range. 
         [0026]      FIG. 9  is a timing diagram that illustrates the input clock frequency being out of specification. As is seen in this figure, the period is greater than the delay indicating therefore the error flag is low. Finally,  FIG. 10  is a timing diagram that illustrates the error flag indication is active when period is less than the delay indicating that the frequency of the input clock signal is within the specified frequency range. 
         [0027]      FIG. 11  is a timing diagram that illustrates the error flag indications for both even and odd pulses as well as the combined error flag indication. 
         [0028]      FIG. 12  is a diagram of an implementation of a frequency monitor cell  400  in accordance with the present invention. The cell  400  includes the following: 
         [0029]    Control circuit  402 ,  404   a  and  404   b.  This control circuit ( 404   a  and  404   b ) divides the input clock signal into odd and even pulses and controls the clear signal. 
         [0030]    Delay cells  406   a  and  406   b.  In one embodiment, the delays are provided by inverters controlled by current (bias), and loaded by capacitors. The spread of the frequency depends principally on the accuracy of the generated delay. 
         [0031]    Check cells  408   a  and  408   b  verify if the clock signal (respectively odd and even signal) is within or not within the specification. 
         [0032]    Bias cell  412 . The bias cell  412  delivers a current reference (low voltage current bias). 
         [0033]    Signal processing elements  410 . The signal processing elements  410  are utilized to provide an indication that the input signal is within specification. 
       ADVANTAGES 
       [0034]    The frequency monitor in accordance with the present invention provides good results in behavior and security performance, good behavior at high frequencies, and is insensitive to the input clock duty cycle. The frequency monitor in accordance with the present invention has low power consumption, and provides a simpler and more effective solution for determining whether an input clock signal is within specification. Finally, the frequency monitor in accordance with the present invention is adaptable to a variety of architectures. 
         [0035]    Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. The frequency monitor in accordance with the present invention can be utilized in a variety of devices such as a microcontroller, digital signal processor or other types of integrated circuits. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.