Abstract:
A charge transfer amplifier that performs amplification without a selective coupling to a precharge reference voltage. In lieu of the selective precharge coupling, the drain of the PMOS transistor is selectively coupled to Vss during the reset and precharge phases. In addition, the drain of the NMOS transistor is selectively coupled to Vss during the reset phase, and is selectively coupled to Vdd during the precharge phase. The drain of the PMOS transistor is capacitively coupled through a first intermediate capacitor to the output terminal of the charge transfer amplifier. The drain of the NMOS transistor is capacitively coupled through a second intermediate capacitor to the output terminal. During the amplify phase, the drains of the NMOS and PMOS transistor are permitted to float except for any charge flow through the respective transistor.

Description:
BACKGROUND OF THE INVENTION 
     1. The Field of the Invention 
     The present invention relates to circuits and methods for amplifying electrical signals. More specifically, the present invention relates to circuits and methods for performing amplification by charge transfer without using a reference voltage. 
     2. The Prior State of the Art 
     There are many circuits and methods conventionally available for amplifying an electrical signal. One type of amplifier is called a charge transfer amplifier. Charge transfer amplifiers operate on the principle of capacitive charge sharing. Voltage amplification is achieved by transferring a specific amount of charge between appropriately sized capacitors through an active device. 
     FIG. 1 illustrates a charge transfer amplifier  100  that utilizes an NMOS transistor MN 1  to transfer charge between capacitors CT and CO. The operation of the NMOS charge transfer amplifier  100  will now be described in order to illustrate the basic principle of charge transfer amplification. 
     The NMOS charge transfer amplifier  100  operates on an amplifier cycle involving three phases including a reset phase, a precharge phase, and an amplify phase. FIG. 2 is a signal timing diagram for two input signals S 1  and S 2  with respect to the phase that the NMOS charge transfer amplifier  100  is operating in whether that phase be (a) the reset phase, (b) the precharge phase or (c) the amplify phase. The two input signals S 1  and S 2  control corresponding switches /S 1  and /S 2  of FIG.  1 . FIG. 2 also shows a clock signal CLK. It is apparent that each amplifier cycle takes two complete clock cycles. The reset and precharge phases each take a half clock cycle, and the amplify phase takes a full clock cycle. 
     Throughout this application, signal S 1  controls switch S 1  (not yet described) and switch /S 1 , and signal S 2  controls switch S 2  (not yet described) and switch /S 2 . Although signal S 3  is not yet described and is not used in conventional charge transfer amplifiers, signal S 3  controls switch S 3  (not yet described). The slash symbol “/” in the value of a switch indicates that the switch is closed when the corresponding control signal is low, and open when the corresponding control signal is high. Conversely, the absence of a slash symbol “/” in the value of a switch indicates that the switch is open when the corresponding control signal is low, and closed when the corresponding control signal is high. Similar nomenclature is used throughout this application for all the switches illustrated and/or described herein. 
     The cycle begins with the (a) reset phase in which the signal S 1  is low indicating that the switch /S 1  is closed, and in which the signal S 2  is low indicating that the switch /S 2  is closed. Since the switch /S 1  is closed, the upper terminal of capacitor CT (i.e., node  101 ) is discharged through the switch /S 1  to voltage Vss. Switch /S 2  is closed indicating that the upper terminal of capacitor CO (i.e., node  102 ) is forced to a precharge reference voltage V PR . 
     After the reset phase is the (b) precharge phase in which the signal S 1  is high indicating that switch /S 1  is open, and in which the signal S 2  is low indicating that the switch /S 2  remains closed. Thus, the upper terminal of the capacitor CO (i.e., node  102 ) remains charged to the precharge reference voltage V PR . This precharge reference voltage V PR  is high enough that current flows from node  102  to the capacitor CT (and node  101 ) through the NMOS transistor MN 1 . For example, if the precharge reference voltage V PR  is at least equal to the input voltage V IN  at the gate of the NMOS transistor MN 1 , then the discharge continues until the voltage at the capacitor CT increases to be equal to the input voltage V IN  minus the threshold voltage (hereinafter “V TN ”) of the NMOS transistor MN 1 . At that point, the NMOS transistor MN 1  enters the cutoff region and current flow to the capacitor CT substantially ceases. Thus, at the end of the precharge phase, the capacitor CO ideally has a voltage of V PR  while the capacitor CT has a voltage of V IN −V TN . 
     After the precharge phase is the (c) amplify phase in which both signals S 1  and S 2  are high indicating that both switches /S 1  and /S 2  are open. During the amplify phase, an incrementally positive input voltage change ΔV IN  applied at the gate of the NMOS transistor MN 1  will cause the NMOS transistor MN 1  to turn on thereby allowing current to flow through the NMOS transistor MN 1  until the NMOS transistor MN 1  is again cutoff. For small incrementally positive voltage changes ΔV IN , the NMOS transistor MN 1  will cutoff when the voltage on the upper terminal of the capacitor CT (i.e., node  101 ) increases by the incrementally positive voltage change ΔV IN . The amount of charge transferred to the capacitor CT in order to produce this effect is equal to the incrementally positive voltage change ΔV IN  times the capacitance C T  of the capacitor CT. 
     Since the charge ΔV IN ×C T  transferred to the capacitor CT came from node  102  through transistor MN 1 , the charge ΔV IN ×C T  was drawn from the capacitor CO. Thus, the voltage at the capacitor CO and the output voltage V OUT  will change by ΔV IN ×(C T /C 0 ). If the capacitance C T  is greater than the capacitance C 0 , amplification occurs. 
     One advantage of the NMOS charge transfer amplifier  100  is that the voltage gain and power consumption may be controlled by setting the capacitance of the capacitors CO and CT as well as by setting the capacitance ratio C T /C 0 . 
     Another advantage of charge transfer amplifiers in general is that the circuit performance is generally unaffected by the absolute values of the supply voltage Vss and Vdd as long as these voltages permit proper biasing during the reset and precharge phases. In other words, charge transfer amplifiers have high supply voltage scalability in that no changes are needed for a charge transfer amplifier to operate using a wide range of supply voltages Vss and Vdd. Although the NMOS charge transfer amplifier  100  has these advantages, there are at least two disadvantages to amplifying using the NMOS charge transfer amplifier  100 . 
     First, amplification only occurs if the input gate voltage change ΔV IN  is positive. A negative gate voltage change ΔV IN  would only cause the NMOS transistor MN 1  to enter deeper into the cutoff region. Thus, charge transfer between node A and node B would be stifled thereby preventing amplification. 
     Second, leakage currents inherent in transistor MN 1  will alter the expected zero-bias (i.e., no input signal) conditions on capacitors CT and CO during the amplify phase. This leakage current may be caused by current undesirably leaking from the source/drain diffusion regions of the NMOS transistor MN 1  into the substrate in which they are formed. Leakage current may also be caused by current flowing between the source and drain terminals of the NMOS transistor MN 1  even though the NMOS transistor MN 1  is substantially cutoff. Either way, this leakage current effectively produces a voltage error at the output terminal that introduces amplification error. 
     FIG. 3 shows a conventional CMOS charge transfer amplifier  300  that substantially overcomes the above-described limitations of the NMOS charge transfer amplifier  100 . The CMOS charge transfer amplifier  300  includes an NMOS charge transfer amplifier  301  that is similar to the NMOS charge transfer amplifier  100  described above, except that a switch S 1  is provided between the source of the NMOS transistor MN 1  and the charge transfer capacitor CT L . This inhibits leakage current in the NMOS transistor MN 1  during the reset phase. 
     For clarity, the NMOS charge transfer amplifier  301  is shown in FIG. 3 as being enclosed by a dotted box. The CMOS charge transfer amplifier  300  also includes a partially overlapping PMOS charge transfer amplifier  302  which is shown in FIG. 3 enclosed by a dashed box for clarity. The PMOS charge transfer amplifier  302  shares the voltage input line  303 , the voltage output line  304  and the precharge line  305  with the NMOS charge transfer amplifier  301 . 
     The PMOS charge transfer amplifier  302  is structured similar to the NMOS charge transfer amplifier  301  except that the PMOS charge transfer amplifier  302  uses a PMOS transistor MP 1  instead of an NMOS transistor MN 1  for transferring charge between capacitors. Also, node  201  of the PMOS charge transfer amplifier  302  is reset to a high voltage Vdd instead of the low voltage Vss and is capacitively coupled to the high voltage Vdd instead of the low voltage Vss. 
     The general operation of the PMOS charge transfer amplifier  302  for negative input voltage changes ΔV IN  is similar to the operation of the NMOS charge transfer amplifier  301  for positive voltage changes ΔV IN . Thus, the input signals S 1  and S 2  of FIG. 2 are used in the operation of the CMOS charge transfer amplifier  300 . Due to the complementary nature of the NMOS charge transfer amplifier  301  and the PMOS charge transfer amplifier  302 , the CMOS charge transfer amplifier  300  amplifies for both positive and negative input voltage changes ΔV IN  thereby overcoming one of the two described limitations of the NMOS charge transfer amplifier  100 . Furthermore, the effect of the leakage current may be minimized by sizing the NMOS transistor MN 1  and the PMOS transistor MP 1  so that the leakage currents match closely. While the match is never perfect or even predictable, the overall voltage error is usually lowered relative to the voltage error of the NMOS charge transfer amplifier  100  alone. 
     As apparent from FIG. 3, there are five different voltages involved with the CMOS charge transfer amplifier  300 . The input voltage V IN  and the output voltage V OUT  are, of course, inherent to the operation of an amplifier. The supply voltages Vdd and Vss are readily available to the circuit as a whole. Thus, there is very little cost in making these supply voltages available to the CMOS charge transfer amplifier  300 . The precharge reference voltage V PR  is also conventionally part of the charge transfer amplifier and is conventionally provided at a mid-supply level approximately midway between the supply voltages Vdd and Vss. 
     Conventional charge transfer amplifiers use the precharge reference voltage V PR  for at least two good reasons. First, by supplying the precharge reference voltage V PR  at mid-supply between Vdd and Vss, the output voltage V OUT  is also precharged to mid-supply during the precharge phase. During the amplify phase, ΔV IN  causes the output voltage V OUT  to change slightly. However, the output voltage V OUT  is still generally centered at mid-supply. This is important for circuitry subsequent to the CMOS charge transfer amplifier  300 . Such subsequent circuitry may include, for example, a dynamic latch comparator or another amplifier, and will typically have a limited range of allowable input voltage levels. An input voltage centered at mid-supply is typically within that limited range of allowable input voltage levels for subsequent circuitry. 
     The second good reason for using a mid-supply precharge reference voltage V PR  is that this ensures proper self-biasing of the transistors MN 1  and MP 1  of the CMOS charge transfer amplifier  300  during the precharge and amplify phases. For these two reasons, the use of a precharge reference voltage V PR  is standard in conventional charge transfer amplifiers. 
     Generating a voltage such as V PR  that differs from the supply voltages Vdd and Vss poses logistical problems for many types of circuits. Generating the precharge reference voltage V PR  off-chip may increase the overall size of the amplifier package. Generating the precharge reference voltage on-chip consumes valuable die real estate. Whether implemented on-chip or off-chip, the generation of the precharge reference voltage V PR , results in Direct Current (or “DC”) power dissipation and some degree of design complexity. 
     Accordingly, what is desired are circuits and methods for performing charge transfer amplification without using a precharge reference voltage V PR . 
     SUMMARY OF THE INVENTION 
     The foregoing problems in the prior state of the art have been successfully overcome by the present invention, which is directed to circuits and methods performing charge transfer amplification without using a precharge reference voltage. 
     The charge transfer amplifier has a first supply voltage source (e.g., Vdd) and a second supply voltage source (e.g., Vss) that has a lower voltage than the first supply voltage source. The charge transfer amplifier also includes a PMOS transistor and an NMOS transistor that share a common gate terminal that is coupled to the input terminal. The charge transfer amplifier further includes a first input capacitor CT U  capacitively coupling a first node (e.g., node A of FIG. 4) to a fixed voltage, a second input capacitor CT L  capacitively coupling a second node (e.g., node B) to a fixed voltage, a first intermediate capacitor CR U  capacitively coupling the output terminal to the drain of the PMOS transistor (e.g., node DP), and a second intermediate capacitor CR L  capacitively coupling the output terminal to the drain of the NMOS transistor (e.g., node DN). 
     The charge transfer amplifier has an amplification cycle that includes a reset phase, a precharge phase, and an amplify phase. During the reset phase, a relatively fixed voltage (V REF ) is applied to the input terminal of the charge transfer amplifier. Node A is reset to Vdd, and node B, node DP, node DN, and the output terminal are reset to Vss. Optionally, node A is isolated from the source of the PMOS transistor, and node B is isolated from the source of the NMOS transistor during the reset phase to thereby reduce or prevent leakage current. 
     During the precharge phase, node A is disconnected from Vdd and connected to the source of the PMOS transistor. Node B is disconnected from Vss and connected to the source of the NMOS transistor. Node DN is coupled to Vdd. This result in charge from node A passing through the PMOS transistor and to the node DP until the voltage at node A equals the gate voltage minus the threshold voltage of the PMOS transistor, at which point the PMOS transistor becomes cutoff. Also, charge from node DN passes through the NMOS transistor and to the node B until the voltage at node B equals the gate voltage minus the threshold voltage of the NMOS transistor, at which point the NMOS transistor becomes cutoff. 
     During the amplify phase, an incremental voltage change is applied to the common gate terminal. Also the drain of the PMOS transistor is disconnected from Vss, and the drain of the NMOS transistor is disconnected from Vdd. For positive incremental voltage changes, the NMOS transistor temporarily exits the cutoff region and conducts charge from node DN to node B. This results in a voltage decrease at the output terminal that is proportional to the positive incremental voltage change. For negative incremental voltage changes, the PMOS transistor temporarily exits the cutoff region and conducts charge from node A to node DP. This result in a voltage increase at the output terminal that is proportional to the negative incremental voltage change. 
     The charge transfer amplification is performed without a precharge reference voltage. Accordingly, the increased package size due to on-chip implementation of the precharge reference voltage and/or the use of the die space occupied by the precharge reference voltage source may be avoided thus resulting in a more compact charge transfer amplifier. 
     Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order that the manner in which the above-recited and other advantages of the invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which: 
     FIG. 1 is a circuit diagram of a conventional NMOS charge transfer amplifier; 
     FIG. 2 is a timing diagram of several waveforms used to operate switches that control the NMOS charge transfer amplifier of FIG. 1, and to operate switches that control the CMOS charge transfer amplifier of FIG. 3; 
     FIG. 3 is a circuit diagram of a conventional CMOS charge transfer amplifier; 
     FIG. 4 is a circuit diagram of a reference-free charge transfer amplifier in accordance with the present invention; 
     FIG. 5 illustrates an example input coupling circuit that may be used to impose preferred conditions to the input voltage of FIG. 4; 
     FIG. 6 is a flowchart showing the overall operation of the reference-free charge transfer amplifier; 
     FIG. 7 is a timing diagram of several waveforms used to operate switches that control the reference-free charge transfer amplifier in accordance with the present invention; 
     FIG. 8 is a timing diagram of several waveforms showing voltage states at various nodes of the differential-mode charge transfer amplifier during operation; and 
     FIG. 9 illustrates the principles of the present invention incorporated into a differential-mode charge transfer amplifier. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention is described below by using diagrams to illustrate either the structure or processing of embodiments used to implement the circuits and methods of the present invention. Using the diagrams in this manner to present the invention should not be construed as limiting of the scope of the invention. Specific embodiments are described below in order to facilitate an understanding of the general principles of the present invention. Various modifications and variations will be apparent to one of ordinary skill in the art after having reviewed this disclosure. 
     FIG. 4 illustrates a reference-free charge transfer amplifier  400  in accordance with the present invention. The reference-free charge transfer amplifier  400  includes a few components that are similar to those described with respect to the CMOS charge transfer amplifier  300 . In particular the components outside of the dashed box  401  are similar to corresponding components in the conventional CMOS charge transfer amplifier  300 . However, as will be apparent from the following description, the similarities end there. 
     The circuit within the dashed box  401  represents a significant advancement in the art and represents an example of a means for self-biasing the charge transfer amplifier without using a precharge reference voltage source. The means for self-biasing accomplishes self biasing while still providing for a generally mid-supply centered voltage at the output terminal  304 . In particular, the drain of the PMOS transistor MP 1  (node DP) is selectively coupled to voltage source Vss through switch /S 2 . The drain of the PMOS transistor MP 1  is capacitively coupled to the output terminal  304  through an upper reference capacitor CR U . The drain of the NMOS transistor MN 1  (node DN) is selectively coupled to voltage source Vss through switch /S 1 , and is selectively coupled to voltage source Vdd through switch S 3 . The drain of the NMOS transistor MN 1  is also capacitive coupled to the output terminal  304 , but through a lower reference capacitor CR L . 
     Those skilled in the art will recognized that any switch illustrated and/or described herein may be replaced by more than one switch in order to obtain identical functionality. For example, in FIG. 4, switch /S 2  selectively couples node DP to Vss. However, two switches (e.g., switch /S 1  and switch S 3 ) in parallel, selectively coupling node DP to Vss will provide an identical result. Wherever a single switch is illustrated in this description, those skilled in the art will recognize that that single switch may symbolically represent multiple switches and still be within the principles of the present invention. 
     The reference-free charge transfer amplifier  400  operates in an amplification cycle that includes three phases: the reset phase, the precharge phase, and the amplify phase. During the reset phase and the precharge phase, the input voltage at the input terminal  303  (called herein both V IN  and V GATE ) is preferably kept as fixed as possible until a voltage step ΔV IN  is applied at the input terminal  303  at the beginning of the amplify phase. FIG. 5 illustrates an input coupling circuit  500  that may accomplish these preferred input voltage conditions. The input coupling circuit  500  includes a reference voltage source V REF  that represents the input voltage V IN  during the reset and precharge phases. The reference voltage source V REF  may be coupled to the input voltage line  303  of the reference-free charge transfer amplifier  400  through a switch /S 2 . An amplification voltage V AMP  represents the input voltage V IN  during the amplify phase. The amplification voltage V AMP  is coupled to the input voltage line  303  through the switch S 2 . The incremental input voltage change ΔV IN  is equal to V AMP  minus V REF . 
     FIG. 6 is a flowchart of the overall operation of the reference-free charge transfer amplifier  400 . The amplifier  400  operates in an amplification cycle that includes a reset step  610 , a precharge step  620 , and an amplify step  630 . Each step or phase is implemented by the manipulation of one or more of the switches S 1 , /S 1 , S 2 , /S 2  and S 3  illustrated in FIG.  4 . FIG. 7 illustrates several timing signals S 1 , S 2  and S 3  used to operate corresponding switches S 1 , /S 1 , S 2 , S 2  and S 3  in order to implement (a) the reset step, (b) the precharge step, and (c) the amplify step of FIG.  6 . 
     In the reset step  610 , the reference-free charge transfer amplifier is reset. Specifically, the switches of FIG.  4  and FIG. 5 have the configuration defined in Table 1. 
     
       
         
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Switch 
                 Status 
               
               
                   
                   
               
             
             
               
                   
                 S1 
                 Open 
               
               
                   
                 /S1 
                 Closed 
               
               
                   
                 S2 
                 Open 
               
               
                   
                 /S2 
                 Closed 
               
               
                   
                 S3 
                 Open 
               
               
                   
                   
               
             
          
         
       
     
     Referring to FIG. 5, with these reset settings, a relatively fixed voltage V REF  is applied to the input line  303  (act  611 ) via the switch /S 2 . Accordingly, V GATE  is V REF  during the reset phase. 
     Referring to FIG. 4, node A is reset to Vdd through switch /S 1  (act  612 ). Nodes B, DP, DN, and the output terminal  304  are reset to Vss (act  613 ) through respectively switches /S 1 , /S 2 , /S 1  and /S 1 . Current through the PMOS transistor MP 1  and the NMOS transistor MN 1  is blocked during the reset phase due to switch S 1  being open. The isolation of node A but is not essential for the operation of the amplifier  400 . 
     FIG. 8 illustrates waveforms showing the voltage states at the input terminal  303  (i.e., V GATE ), node A, node B, node DP, node D, and the output terminal (i.e., V OUT ). These waveforms are shown with respect to (a) the reset step  610 , (b) the precharge step  620  and (c) the amplify step  630 . 
     In the precharge step  620 , the reference-free charge transfer amplifier is precharged. Specifically, the switches of FIG.  4  and FIG. 5 have the configuration defined in Table 2. 
     
       
         
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Switch 
                 Status 
               
               
                   
                   
               
             
             
               
                   
                 S1 
                 Closed 
               
               
                   
                 /S1 
                 Open 
               
               
                   
                 S2 
                 Open 
               
               
                   
                 /S2 
                 Closed 
               
               
                   
                 S3 
                 Closed 
               
               
                   
                   
               
             
          
         
       
     
     Referring to FIG. 5, with these precharge settings, there is no change in the settings for switch S 2  and switch /S 2 . According, the relatively fixed voltage V REF  remains applied to the input line  303 . Accordingly, V GATE  remains V REF  during the precharge phase. 
     Referring to FIG. 4, nodes A and B are disconnected from their respective supply voltages Vdd and Vss (act  621 ) due to the opening of switch /S 1 . In addition, nodes A and B are coupled to the source terminals of the respective transistors MP 1  and MN 1  (act  622 ) due to the closing of switch S 1 . Node DP remains coupled to Vss through the switch /S 2 . However, node DN is decoupled from voltage Vss due to the opening of switch /S 1 , and is instead coupled to voltage Vdd (act  623 ) due to the closing of switch S 3 . Thus, the voltage at node DN increases sharply from Vss to Vdd at the beginning of the precharge phase as is illustrated in FIG.  8 . 
     Note that in this state at the beginning of the precharge phase, the source of the PMOS transistor MP 1  is initially at Vdd while the drain of the PMOS transistor is at Vss. Accordingly, if the gate voltage V GATE  is equal to a common-mode voltage (V CMI ) approximately midway between the supply voltages Vss and Vdd, current will flow from node A, through the PMOS transistor MP 1  and to the node DP until the voltage at node A is equal to the gate voltage (e.g., V CMI ) minus the threshold voltage of the PMOS transistor V TP , at which point the PMOS transistor MP 1  becomes substantially cutoff. Accordingly, FIG. 8 shows that the voltage at node A exponentially decays during the precharge phase to a value of V CMI  minus the threshold voltage of the PMOS transistor V TP . Note that the source to drain voltage for the PMOS transistor MP 1  (Vdd−Vss) is greater that the source to drain voltage for the PMOS transistor in the convention amplifier  300  (Vdd−V PR ) Accordingly, precharge occurs faster using the a amplifier  400  than in the prior art amplifier  300 . This makes faster operating frequencies possible. 
     With regards to the NMOS transistor MN 1 , the source of the NMOS transistor MN 1  begins the precharge phase at Vss while the drain of the NMOS transistor MN 1  is soon at Vdd. Accordingly, if the gate voltage V GATE  is equal to a common-mode voltage (V CMI ) approximately midway between the supply voltages Vss and Vdd, current will flow from node DN, through the NMOS transistor MN 1  and to the node B until the voltage at node B is equal to the gate voltage (e.g., V CMI ) minus the threshold voltage of the NMOS transistor V TN , at which point the NMOS transistor MN 1  becomes substantially cutoff. Accordingly, FIG. 8 shows that the voltage at node B has inverse exponentially decay during the precharge phase to a value of V CMI  minus the threshold voltage of the NMOS transistor V TN . The faster precharge times are also possible for the NMOS transistor MN 1  due to the drain of the NMOS transistor MN 1  being precharged to Vdd, while the source remains at Vss. 
     The sharp increase in the voltage at node DN causes the voltage V OUT  at the output terminal to increase due to capacitive interpolation between Vss and Vdd, according to the following equation.          V   OUT     =     Vss   +       (     Vdd   -   Vss     )                       C   R         2        C   R       +     C   0                                    
     where, 
     C R  is the capacitance of each of capacitors CR U  and CR L ; and 
     C O  is the capacitance of the capacitor CO. 
     The final value of V OUT  after the precharge phase becomes the common mode input voltage for subsequent circuitry. If C O  were zero, the common mode output voltage would be exactly mid-supply assuming that the threshold voltage of PMOS transistor (i.e., V TP ) is the negative of the threshold voltage of the NMOS transistor (i.e., V TN ). If C O  was zero, V OUT  would be exactly mid-supply. However, assuming that there was some output capacitance C O , the e V OUT  would fall somewhere below mid-supply. CO is illustrated as a load capacitor for modeling purposes. However, CO often takes the form of parasitic input capacitance for subsequent circuitry  410 . The subsequent circuitry  410  may be, for example, a dynamic latch comparator or another amplifier. When used with a subsequent dynamic latch comparator, the reference-free charge transfer amplifier facilitates an efficient voltage comparator. 
     Since the output capacitor CO often takes the form of parasitic capacitance, it may be difficult to control the value of C O . Accordingly, in order to be as close to mid-supply as practicable, it would be best to make C R  large enough that the attenuation due to C O  is not too great. For example, if C O  was 100 fF, C R  was 200 fF, Vdd was 5.0 V and Vss was 0.0 V, then the above-equation would indicate that the output voltage would be 2.0 V. This is likely to accommodate the common-mode input requirements for many types of subsequent circuitry. 
     Note that the output voltage Vour during the precharge phase is tied directly to the fixed supply voltages Vss and Vdd. Accordingly, the output voltage V OUT  remains fixed to the value calculated in the above-equation during the precharge phase. 
     In the amplify step  630 , the reference-free amplifier  400  is used to perform amplification. Specifically, the switches of FIG.  4  and FIG. 5 have the configuration defined in Table 3. 
     
       
         
               
               
               
             
           
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                 Switch 
                 Status 
               
               
                   
                   
               
             
             
               
                   
                 S1 
                 Closed 
               
               
                   
                 /S1 
                 Open 
               
               
                   
                 S2 
                 Closed 
               
               
                   
                 /S2 
                 Open 
               
               
                   
                 S3 
                 Open 
               
               
                   
                   
               
             
          
         
       
     
     Referring to FIG. 5, with these precharge settings, the amplification voltage V AMP  is applied (act  631 ) to the input line  303  of the amplifier  400 , resulting in a step voltage change of ΔV IN  where ΔV IN  equals V AMP  minus V REF . This step voltage change at the beginning of the amplify phase is illustrated in FIG. 8 for V GATE . 
     Referring to FIG. 4, nodes DP and DN are both floating (act  632 ) except for potential charge paths through transistors MP 1  and MN 1  since switch /S 1 , /S 2  and S 3  are all open. For positive values of ΔV IN  as in the situation illustrated in FIG. 8, the NMOS transistor MN 1  becomes incrementally biased thus temporarily exiting the cutoff region. This allows current to flow from node DN through NMOS transistor MN 1  to node B until the voltage at node B rises by ΔV IN . Thus, as illustrated in FIG. 8 for the amplify phase, the voltage at node B increases from V CMI  minus V TN  to V CMI  minus V TN  plus ΔV IN . 
     Since node DN is floating, the voltage at node DN also decreases thereby pulling down the voltage V OUT  at the output terminal  304 , and the voltage at node DP through capacitive coupling. Also, since node DP is floating, the PMOS transistor MP 1  becomes only more cutoff when ΔV IN  is positive. 
     For negative values of ΔV IN , the PMOS transistor MP 1  becomes incrementally biased thus temporarily exiting the cutoff region. This allows current to flow from node A through PMOS transistor MP 1  to node DP until the voltage at node A decreases by ΔV IN . Thus, the voltage at node A will decrease from V CMI  minus V TN  to V CMI  minus V TN  plus ΔV IN . Note that ΔV IN  is a negative number in this case. Accordingly, adding a negative number results in an overall voltage decrease. Since node DP is floating, the voltage at node DP increases thereby pulling up the voltage V OUT  at the output terminal  304 , and the voltage at node DN through capacitive coupling. 
     The two intermediary capacitors CR U  and CR L  introduce parasitic capacitance with respect to the output terminal  304 . Accordingly, the reference-free amplifier  400  has a slightly decreased gain for a given C T  and C O  as compared to the conventional CMOS charge transfer amplifier  300 . In addition, the reference-free amplifier  400  consumes slightly more dynamic power than the conventional CMOS charge transfer amplifier  300 . However, in many applications, these drawbacks are more than compensated for by the benefits of not have to supply a precharge reference voltage. 
     The means for self-biasing  401  illustrated in FIG. 4 may be used to replace any selective coupling to a precharge voltage in any circuit. For example, a differential-mode charge transfer amplifier is described in commonly-owned U.S. Pat. No. 6,249,181 entitled “Differential-Mode Charge Transfer Amplifier” and issued to William J. Marble on Jun. 19, 2001 (hereinafter called “the issued patent”), and which is incorporated herein by reference in its entirety. FIG. 9 illustrates a differential-mode charge transfer amplifier in which the principles of the present invention may be employed. The differential mode charge transfer amplifier  900  is composed of two CMOS charge transfer amplifiers CMOS CTA 1  and CMOS CTA 2 , each having the means for self-biasing  401  applied to the node where the conventional differential-mode charge transfer amplifier described in the issued patent was selectively coupled to the precharge reference voltage. 
     Accordingly, the principles of the present invention allow for circuits and methods for performing charge transfer amplification without requiring a precharge reference voltage. Having described the general principles of the present invention, a number of variations, modifications and deletions will be apparent to those of ordinary skill in the art. For example, although node A is described as being capacitively coupled to supply voltage Vdd, and node B is described as being capacitively coupled to supply voltage Vss, these nodes may be coupled to any voltage source. The more fixed that voltage source, the better the performance of the charge transfer amplifier. Those skilled in the art will recognize that it is impossible to obtain a fixed voltage to an infinite degree of precision. Any voltage source, even those considered fixed, will have some level of variation. 
     The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.