Abstract:
A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present invention is related to U.S. patent application Ser. No. ______, entitled “Voltage Controlled Delay Loop with Central Interpolator,” filed contemporaneously herewith and incorporated by reference herein. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention is related to techniques for clock and data recovery (CDR) and, more particularly, to methods and apparatus for digital control of the generation and selection of different phases of a clock signal.  
       BACKGROUND OF THE INVENTION  
       [0003]     In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase of an incoming data stream and one or more of the clock signals are selected for data recovery.  
         [0004]     A number of existing digital CDR circuits use voltage controlled delay loops (VCDL) to generate a number of clocks having the same frequency and different phase for data sampling (i.e., oversampling). For example, published International Patent Application No. WO 97/14214, discloses a compensated delay locked loop timing vernier. The disclosed timing vernier produces a set of timing signals of similar frequency and evenly distributed phase. An input reference clock signal is passed through a succession of delay stages. A separate timing signal is produced at the output of each delay stage. The reference clock signal and the timing signal output of the last delay stage are compared by an analog phase lock controller. The analog phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. Based on the results of the oversampled data, the internal clock is delayed so that it provides data sampling adjusted to the center of the “eye.” The phase of the VCDL is adjusted to keep up with phase deviations of the incoming data.  
         [0005]     While such voltage controlled delay loops effectively generate the sampling clocks and control the delay stages to maintain alignment of the reference clock signal and the last timing signal, they suffer from a number of limitations, which if overcome, could further improve the utility of such voltage controlled delay loops. For example, the analog implementation of the phase lock controller is complex and generally cannot be easily ported from one technology to another. In addition, digital-to-analog conversion is required to convert the digital phase adjustment control into analog signal control. A need therefore exists for voltage controlled delay loops with digital phase control.  
       SUMMARY OF THE INVENTION  
       [0006]     Generally, a voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.  
         [0007]     The injection point control of the present invention allows a desired phase relationship to be maintained between the reference clock and a sample clock. The granularity of the disclosed voltage controlled delay loop is equal to the delay associated with each delay element.  
         [0008]     A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  illustrates an exemplary conventional clock recovery circuit;  
         [0010]      FIG. 2  illustrates the transitions in a data stream;  
         [0011]      FIG. 3  illustrates a VCDL having coarse phase control in accordance with the present invention; and  
         [0012]      FIG. 4  is a schematic block diagram of an exemplary implementation of the VCDL of  FIG. 3 . 
     
    
     DETAILED DESCRIPTION  
       [0013]     The present invention provides voltage controlled delay loops with digital phase control. The present invention controls the phase offset from the reference clock to the data sampling clock by shifting the injection point of the reference clock into the voltage controlled delay loop.  
         [0014]      FIG. 1  illustrates an exemplary conventional clock recovery circuit  100 . As shown in  FIG. 1 , the clock recovery circuit  100  produces a clock signal with a predetermined number of phases, T 0 , S 0 , . . . T i , S i , discussed below in conjunction with  FIG. 2 . The exemplary clock recovery circuit  100  includes a reference clock signal (for example,  2  GHz) generated by a phase locked loop (PLL)  110  and applied to the input of a voltage controlled delay line  120 . As shown in  FIG. 1 , the voltage controlled delay loop  120  interacts with two control loops  150 ,  160 . The first phase control loop  150  is comprised of a VCDL phase detector  130 , a digital filter  140  and a current steering DAC  145 . Generally, the first control loop  150  adjusts the delays of the voltage controlled delay loop  120 . The reference signal and the output of the VCDL  120  are applied to the VCDL phase detector  130  which provides phase detection by producing an output representative of the phase difference that is applied to a filter  140  whose digital output is converted to an analog voltage by the DAC  145  to control the delay in the stages of the voltage controlled delay loop  120 .  
         [0015]     The second data control loop  160  is comprised of a preamplifier  165 , a data sampling block  170 , an optional data decimator  175 , a parallel data and clock output block  180  and a second order proportional and integral (PI) filter  190 . The serial data is received and amplified by the preamplifier  165  and applied to the data sampling block  170 . The data sampling block  170  samples the data using the plurality of phases, T 0 , S 0 , . . . T i , S i . The data samples are then applied to the optional data decimator  175  that drops the data rate, for example, by a factor of two. In addition, the data sampling block  170  provides a recovered bit clock output that is applied to the data decimator  175 , parallel data and clock output block  180  and second order PI filter  190 . The parallel data and clock output block  180  outputs the sampled serial data and recovered lower frequency clock as parallel data (usually 16 or 20 bit wide) and clock. The second order PI filter  190  interprets the transition and sample information associated with the, T 0 , S 0 , . . . T i , S i  samples to generate phase control information for the VCDL  120 . Generally, the phase control information ensures that the transitions are maintained close to the transition points (see  FIG. 2 ).  
         [0016]      FIG. 2  illustrates the transitions in a data stream  200 . As shown in  FIG. 2 , the data is ideally sampled in the middle between two transition points. The phases T i , S i  generated by the VCDL  120  are adjusted to align with the transitions and sample points, respectively. Thus, the internal clock is delayed so that the data sampling is adjusted to the center of the “eye,” in a known manner.  
         [0017]     According to one aspect of the present invention, coarse phase control is provided. In order to control the phase offset between the PLL frequency and data sampling (S i ) and transition sampling (T i ), the injection point of the PLL frequency into the VCDL  120  is shifted.  
         [0018]      FIG. 3  illustrates a VCDL  300  having coarse phase control in accordance with the present invention. As shown in  FIG. 3 , the exemplary VCDL  300  is generally comprised of a succession of a number, such as 16, delay elements  310 - 1  through  310 - 16  interconnected in a loop. The exemplary VCDL  300  also includes 16 inputs  320 - 1  through  320 - 16  that are each connected to an associated delay line  310 - i . The correlation between the various phases T i , S i  generated by the VCDL  300  to the delay elements  310  is also shown in  FIG. 3 . As shown in  FIG. 3 , the injection point where the PLL signal is applied to the VCDL can be shifted in accordance with the present invention to any input  320 - i.    
         [0019]      FIG. 4  is a schematic block diagram of an exemplary implementation of the VCDL  300  of  FIG. 3 . As shown in  FIG. 4 , the exemplary VCDL  300  is generally comprised of a succession of delay elements  310 - i  interconnected in a loop. Thus, the output of the final delay element in the loop, such as element  310 - 16  in an implementation having  16  delay elements, is connected to the input of the first delay element  310 - 1  in the loop, in a known manner. Each delay element, such as the delay element  310 - i , is comprised of a multiplexer  410 - i  and a delay stage  420 - i . Each multiplexer  410 - i  receives the PLL signal at one input and the output of the previous stage at a second input. An injection point control signal controls the multiplexers  410 - i , such that one selected multiplexer  410  selects the PLL input and all other multiplexers  410  select the input from the previous stage. In this manner, the injection point control is a “one hot” encoded signal ensuring that the PLL frequency is injected into one and only delay element  420 - i.    
         [0020]     The delay stages  420 - i  may be embodied, for example, using current mode logic (CML) delay stages. In the exemplary implementation having  16  delay elements, each delay stage  420 - i  should provide a delay equal to one-eighth of the unit interval (i.e., the width of the “eye” in  FIG. 2 ). The exemplary CML delay stages  420 - i  employ a current steering technique using currents generated by a digital-to-analog converter  450  and bias block  460 , in a known manner.  
         [0021]     The VCDL  300  of  FIGS. 3 and 4  provides a particular phase relation between the PLL frequency and the sampling clocks for each possible injection point. The change in the injection point allows for a control of this phase relation. Among other benefits of the disclosed digital implementation of the present invention is that it provides better linear control of the phase adjustments, and easier transition from one technology to another.  
         [0022]     A plurality of identical die are typically formed in a repeated pattern on a surface of the wafer. Each die includes a device described herein, and may include other structures or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.  
         [0023]     It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.