Abstract:
A memory access selection circuit including a microprocessor, address, data and control multiplexers, a random access memory, storage circuits and related logic circuitry. This circuit allows both an external processor and the microprocessor to receive data from and transmit data to, the random access memory. The microprocessor controls access of the external processor to the random access memory by controlling and monitoring the multiplexer and storage circuits. This prevents erroneous data, address and control signals from appearing at the memory when switching between the microprocessor and the external processor as sources to the memory.

Description:
FIELD OF THE INVENTION 
     The present invention relates to memory circuits and more particularly to a memory access selection circuit for controlling access of multiple processors to a single memory. 
     BACKGROUND OF THE INVENTION 
     Memory circuits are often used as buffers to store data for and from various input/output (I/O) devices such as terminals, printers or modems. These memories are often accessed by multiple processors. However, in order to prevent erroneous address, data or control signals, access to the memory must be controlled, such that only one processor has access to the memory at any particular time. 
     Such memory access control typically requires complex timing and logic circuitry. 
     Accordingly, it is the object of the present invention to provide a novel memory access selection circuit which does not utilize complex timing and logic circuitry. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a memory access selection circuit is provided for use in a computer system which includes an external processor, operative to provide external read and write signals, and further operative to receive and transmit data in association with said external read and write signals, respectively. The memory access selection circuit of this invention includes an internal processor operative to provide internal read and write signals, and further operative to receive and transmit data in association with the internal read and write signals, respectively. This processor also provides enable, disable and first and second select signals. 
     A memory is also included and it is operative to transmit data in response to the enable signal and the internal or external read signal. The memory is further operative to receive data in response to the enable signal and the internal or external write signal. 
     Multiplexing means is connected to the internal and external processors and the memory. It is operative in response to the first select signal to connect the internal processor to the memory, thereby allowing the internal processor to transmit data to, and receive data from, the memory, in association with the internal write and read signals, respectively. The multiplexing means is further operative in response to the second select signal to connect the external processor to the memory, thereby allowing the external processor to transmit data to, and receive data from, the memory, in association with the external write and read signals, respectively. 
    
    
     DESCRIPTION OF THE DRAWING 
     The single FIGURE of the accompanying drawing is a schematic diagram of a memory access selection circuit in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the accompanying drawing the memory access selection circuit of the present invention is shown. MICROPROCESSOR 10 is shown connected to DECODER 20 via decoder data leads DD1 and DD2 and decoder write lead DWR. MICROPROCESSOR 10 is also connected to bi-directional DATA MULTIPLEXER 30 via internal data leads, ID1-ID8, and it is further connected to ADDRESS AND CONTROL MULTIPLEXER 40 via internal address leads, IAD1-IADn, and internal read and write leads, IRD and IWR, respectively. MICROPROCESSOR 10 is also shown connectable to I/O DEVICES via output data leads OD1-OD8. 
     EXTERNAL PROCESSOR 50 is shown connected to DATA MULTIPLEXER 30 via external data leads ED1-ED8. It is also shown connected to ADDRESS AND CONTROL MULTIPLEXER 40 via external address leads EAD1-EADn, and external read and write leads, EDR and EWR. EXTERNAL PROCESSOR 50 is further connected to inverters 61 and 71 via the release (RLS) and request (REQ) leads, respectively. These inverters are connected to the set (S) input of latches 60 and 70 (storage circuit), respectively. 
     DECODER 20 is connected to the set (S) and reset (R) inputs of enable latch 80 and the set (S) and reset (R) inputs of select latch 90. These latches operate as a storage circuit. The Q output of latch 80 is connected to AND gate 110 and random access memory (RAM) 100 which is also connected to DATA MULTIPLEXER 30 via data leads D1-D8, and ADDRESS AND CONTROL MULTIPLEXER 40 via address leads AD1-ADn and read and write leads RD and WR, respectively. 
     The Q output of select latch 90 is connected to MICROPROCESSOR 10, DATA MULTIPLEXER 30, ADDRESS AND CONTROL MULTIPLEXER 40, inverter 120, the reset (R) input of latch 60, and AND gate 110. Inverter 120 is connected to the reset (R) input of latch 70. The reset outputs, Q, of latches 60 and 70 are connected to OR gate 130 and the reset (Q) output of latch 60 is also connected to AND gate 110. AND gate 110 operates as an acknowledge signaling circuit, and latches 60 and 70, and OR gate 130 operate as an interrupt signaling circuit. The output of AND gate 110 is connected via the ACK lead to EXTERNAL PROCESSOR 50 and the output of OR gate 130 is connected via the INT lead to MICROPROCESSOR 10. Microprocessor 10, decoder 20, and latches 80 and 90 operate as an internal processor. 
     The normal mode of operation is for EXTERNAL PROCESSOR 50 to have control of RAM 100 via ADDRESS AND CONTROL MULTIPLEXER 40 and DATA MULTIPLEXER 30. EXTERNAL PROCESSOR 50 can then cause data to be transmitted to the various I/O DEVICES by first transmitting external data to RAM 100 via DATA MULTIPLEXER 30. Upon completion of such data transfer EXTERNAL PROCESSOR 50 releases control of RAM 100 via these multiplexers, thereby allowing MICROPROCESSOR 10 to gain control of RAM 100, retrieve the memory data from it, and transmit that data to the desired I/O DEVICE. When MICROPROCESSOR 10 has finished transmitting data to the I/O DEVICE, it releases control of the multiplexers and RAM 100, and EXTERNAL PROCESSOR 50 again gains control of them. 
     Similarly, if data is to be received from an I/O DEVICE, MICROPROCESSOR 10 gains control of RAM 100 via the multiplexers, transmits internal data to RAM 100 and then releases control of it and the multiplexers. EXTERNAL PROCESSOR 50 then gains control of RAM 100 via the multiplexers and retrieves the memory data from it. 
     In order for EXTERNAL PROCESSOR 50 to transmit data to an I/O DEVICE, it must first gain control of RAM 100. To do this EXTERNAL PROCESSOR 50 provides a logic level 1 request signal on its request (REQ) lead. This signal is inverted to a logic level 0 signal by inverter 71 and applied to the set (S) input of latch 70, thereby causing it to set and provide a logic level 0 first service-requested signal at its Q output. This logic level 0 signal appears at the second input of OR gate 130 which then provides a logic level 1 interrupt signal on its INT lead. This logic level 1 interrupt signal is detected by MICROPROCESSOR 10 which then applies logic level 0 signals to decoder data leads, DD1 and DD2, and a positive pulse to decoder write lead (DWR). DECODER 20 responds to these signals by applying a logic level 0 first control signal to the reset (R) input of enable latch 80. This latch then provides a logic level 0 disable signal at its Q output. This logic level 0 signal disables RAM 100 and causes AND gate 110 to apply a logic level 0 signal to the ACK lead. EXTERNAL PROCESSOR 50 is then disabled from attempting to access RAM 100, since its internal protocol requires a logic level 1 acknowledge signal on the ACK lead before attempting such access. 
     MICROPROCESSOR 10 then applies logic level 0 and 1 signals to the DD1 and DD2 leads, respectively, and an associated positive pulse to the DWR lead. DECODER 20 responds to these signals by applying a logic level 0 second control signal to the set (S) input of select latch 90. This latch then provides a logic level 1 first select signal at its Q output. ADDRESS AND CONTROL MULTIPLEXER 40 responds to this logic level 1 first select signal by connecting external address (EAD1-EADn), read (ERD) and write (EWR) leads to RAM 100. Similarly, DATA MULTIPLEXER 30 responds to this logic level 1 first select signal by connecting the external data (ED1-ED8) leads to RAM 100. MICROPROCESSOR 10 then applies logic level 1 and 0 signals to the DD1 and DD2 leads, respectively, and a positive pulse to the DWR lead. DECODER 20 responds to these signals by applying a logic level 0 third control signal to the set (S) input of enable latch 80. This latch then provides a logic level 1 enable signal at its Q output. This signal, which enables RAM 100, also appears at the third input of AND gate 110. 
     The logic level 1 first select signal from the Q output of select latch 90 is inverted to a logic level 0 signal by inverter 120 and applied to the reset (R) input of request latch 70. This latch then resets and applies a logic level 1 signal to the second input of OR gate 130, causing it to remove the logic level 1 interrupt signal on the INT lead. Under these conditions, release latch 60 is reset and a logic level 1 signal appears at the first input of gate 110. Since the logic level 1 first select and enable signals also appear at the second and third inputs, respectively, of gate 110, this gate then applies a logic level 1 acknowledge signal to the ACK lead. This signal informs EXTERNAL PROCESSOR 50 that it may now access RAM 100. 
     Upon completion of transmission of data between EXTERNAL PROCESSOR 50 and RAM 100, EXTERNAL PROCESSOR 50 then applies a logic level 1 release signal to the release (RLS) lead. This logic level 1 signal is inverted to a logic level 0 signal by inverter 61 and applied to the set (S) input of release latch 60. This latch then sets and provides a logic level 0 second service-requested signal at its Qoutput. This logic level 0 signal causes OR gate 130 to provide a logic level 1 interrupt signal on the INT lead and also causes AND gate 110 to remove the acknowledge signal by applying a logic level 0 signal to the ACK lead. The removal of the acknowledge signal again prevents EXTERNAL PROCESSOR 50 from accessing RAM 100. 
     MICROPROCESSOR 10 responds to the interrupt signal by applying logic level 0 signals to the DD1 and DD2 leads and a positive pulse to the DWR lead. DECODER 20 responds to these signals by applying a logic level 0 signal to the reset (R) input of enable latch 80, thereby causing it to reset and remove the enable signal by providing a logic level 0 signal at its Q output. This signal causes RAM 100 to be disabled. 
     MICROPROCESSOR 10 then applies logic level 1 signals to the DD1 and DD2 leads and a positive pulse to the DWR lead. DECODER 20 responds to these signals by applying a logic level 0 fourth control signal to the reset (R) input of select latch 90, causing it to reset and provide a logic level 0 second select signal at its Q output. ADDRESS AND CONTROL MULTIPLEXER 40 responds to this logic level 0 signal by connecting the internal address (IAD1-IADn) read (IRD) and write (IWR) leads to RAM 100. Similarly, DATA MULTIPLEXER 30 responds to this logic level 0 signal by connecting the internal data (ID1-ID8) leads to RAM 100. This logic level 0 signal at the Q output of select latch 90 also appears at the reset (R) input of release latch 60, causing it to reset and thereby providing a logic level 1 signal at its Q output. OR gate 130 detects this logic level 1 signal and removes the interrupt signal by applying a logic level 0 signal to the INT lead. The logic level 0 signal at the Q output of select latch 90 also appears at the second input of AND gate 110, causing the acknowledge signal to remain reset by holding a logic level 0 signal on the ACK lead. 
     MICROPROCESSOR 10 then applies logic level 1 and 0 signals to the DD1 and DD2 leads, respectively, and a positive pulse to the DWR lead. DECODER 20 responds to these signals by applying a logic level 0 signal to the set (S) input of enable latch 80, thereby causing it to set and provide a logic level 1 enable signal at its Q output. This enable signal enables RAM 100 and MICROPROCESSOR 10 can then transmit data between RAM 100 and selected I/O DEVICES. 
     Upon completion of such data transfers, MICROPROCESSOR 10 returns control of RAM 100 to EXTERNAL PROCESSOR 50. This is done by disabling RAM 100, selecting EXTERNAL PROCESSOR 50 and enabling RAM 100. The signaling required to do this is identical to the signaling previously described in response to a request (REQ) signal. 
     The memory access circuit of the present invention thus allows control of a random access memory to be transferred between multiple processors. Even though the state of the processors&#39; signals cannot be guaranteed during such transfers, the memory access control circuit of the present invention ensures that only valid data, address and control signals appear at the random access memory while the RAM is enabled. 
     It will be obvious to those skilled in the art that numerous modifications of the present invention can be made without departing from the spirit of the invention which shall be limited only by the scope of the claims appended hereto.