Abstract:
An apparatus is described comprising a chamber containing liquid. A side of the chamber is thermally coupled to a semiconductor chip. The side of the chamber has thermally conductive carbon nanotubes oriented perpendicular to the side&#39;s surface. The carbon nanotubes transfer heat drawn from the semiconductor chip into the liquid, causing it to boil and spread heat laterally across the top face of the chamber. The top face of the chamber may be thermally connected to an external heat sink if necessary. This device allows for a greatly improved ability to transfer heat from the hot spots of a semiconductor device to the ambient medium.

Description:
FIELD OF THE INVENTION  
       [0001]     The field of invention relates generally to heat removal; and, more specifically, to an improved thermally conductive channel between a semiconductor chip and an external thermal interface  
       BACKGROUND  
       [0002]     The power consumption of electrical circuitry has emerged as, perhaps, the single largest threat to the continued advancement of semiconductor technology and its ability to craft new markets through the shrinking of transistor device size. Simply put, the smaller a transistor can be made, the more power will be consumed per transistor (owing to the transistor&#39;s faster speed and substrate leakage) and the more transistors can be fit onto a single chip of silicon. The combination of more transistors per chip and greater power consumption per transistor has resulted in some of the more advanced semiconductor chips under development exhibiting excessive heat dissipation.  
         [0003]     Therefore, semiconductor chip developers are devoting significant resources to the study and development of higher performance yet cost effective chip cooling technologies. Traditionally, cost effective chip cooling has meant “air-cooled” heat sinks.  
         [0004]     As a general perspective, chip cooling technologies are actually more accurately viewed as a heat removal systems. Here, heat generated by a semiconductor chip is transferred to an “external thermal interface”; and, then, the external thermal interface “externally” convects, conducts or radiates the heat to some medium (typically air) that is not deemed part of the semiconductor chip and its associated packaging. Here, the ability to transfer heat “externally” from the semiconductor chip and its packaging corresponds, in turn, to its cooling.  
         [0005]     According to air-cooled heat sink approaches, the external thermal interface is a heat sink made of thermally conductive fins that rise above the surface of the semiconductor chip&#39;s package. The heat dissipated by a semiconductor chip is channeled to the heat sink&#39;s fins. As a general rule, cooling efficiency improves as the surface area of a heat transferring material increases. With respect to heat sinks, the fins of the heat sink effectively create an expanded external thermal interface surface area over which the semiconductor chip&#39;s heat is externally convected and/or radiated.  
         [0006]     When air is blown through the heat sink&#39;s fins, heat is transferred from the fins to the air so as to effectively remove heat from the semiconductor chip and its associated packaging. Unfortunately, the traditional air-cooled mechanism described above—although cost effective—may not exhibit sufficient performance for future high performance and/or high density semiconductor chips.  
     
    
     FIGURES  
       [0007]     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:  
         [0008]      FIGS. 1   a  and  1   b  show semiconductor chips and their respective hot spots;  
         [0009]      FIG. 2  shows an improved thermally conducting channel for use between a semiconductor chip and an external thermal interface;  
         [0010]      FIG. 3  shows an alternate embodiment to that of  FIG. 2  in which a liquid flow flows through the chamber;  
         [0011]      FIG. 4  shows a cross section of a packaged die.  
     
    
     DETAILED DESCRIPTION  
       [0012]      FIGS. 1   a  and  1   b  attempt to graphically depict a particular challenge that, if overcome, could possibly lead to higher performance yet reasonably affordably chip cooling technologies. The particular challenge is uniformly spreading out heat generated from specific regions of the chip that generate excessive heat (commonly referred to as “hot spots”) as the heat is carried to the external thermal interface.  
         [0013]      FIG. 1   a  shows a temperature profile of a first semiconductor chip and  FIG. 1   b  shows a temperature profile of a second semiconductor chip that is differently designed than the first (e.g., the first semiconductor chip may be a microprocessor and the second semiconductor chip may be a memory controller). Concentric rings are observed on both chips. The smaller the region bounded by a ring, the more heat generated within the ring as compared to larger surrounding rings.  
         [0014]     Hot spots are generally created by regions of circuitry operating at high speed. Typically, a digital circuit region will tend to generate more heat as its constituent transistors: 1) are packed more densely; 2) operate faster, and, 3) push/pull more current. The smallest rings observed in  FIGS. 1   a  and  1   b  therefore correspond to regions of the respective circuit designs that unfortunately excel in all three factors listed above as compared to the circuit designs&#39; other regions. Comparing  FIGS. 1   a  and  1   b , concentric rings reside at different locations owing to the different transistor designs designed into the two chips.  
         [0015]     Owing to inefficiencies in the thermal channel that exists between a semiconductor chip and its heat sink, present day generically designed heat sink approaches do not respond well to semiconductor chip “hot spots”. More precisely stated, the thermal conductive channel that exists between the external thermal interface (i.e., the heat sink) and the semiconductor chip conducts heat from different regions of the chip differently. As such, certain regions of the semiconductor chip will enjoy lower thermal resistance between themselves and the external thermal interface than other less fortunate regions.  
         [0016]     If a “hot spot” happens to reside in a region that does not enjoy lower thermal resistance between itself and the external thermal interface, the effected heat transfer from the hot spot may be insufficient to keep the semiconductor chip within acceptable thermal operating limits. The problem can be lessened at least somewhat by custom designing the thermal conductive channel between the semiconductor chip and the external thermal interface on a chip-design by chip-design basis.  
         [0017]     Thus, for example, a first conductive channel could be designed for the semiconductor chip of  FIG. 1   a  that provides for the lowest thermal resistance at the hot spot regions observed in  FIG. 1   a , and, a second conductive channel could be designed for the semiconductor chip of  FIG. 1   b  that provides for the lowest thermal resistance at the hot spot regions observed in  FIG. 1   b . A problem, however, is that the above solution is essentially a “custom” design for each chip, and, custom implementations tend to be more expensive than generic implementations that are theoretically suitable for any chip.  
         [0018]      FIG. 2  provides a depiction of an improved conductive channel that resides between a semiconductor chip  201  and its external thermal interface (e.g., a heat sink that is thermally coupled to layer  214 ). The improved conductive channel effectively operates by what can be referred to as “uniform condensation”. Here, vapor molecules from a pool of liquid  208  that is heated by any semiconductor chip region condense on the underside  211  of the lid of a chamber that contains the liquid and its vapor. Both the boiling of the liquid and the condensation of its vapor corresponds to a heat transfer process that together remove heat from the semiconductor chip  201 .  
         [0019]     Importantly, the vapor molecules scatter randomly within the chamber  207 . As such, the location where a vapor molecule condenses on the lid underside  211  should be effectively random relative to the semiconductor chip region whose heat nucleated the vapor molecule.  
         [0020]     Thus, through this process, heat generated from a particular semiconductor chip region should be uniformly distributed across the lid underside  211 . All regions of the semiconductor chip should therefore enjoy approximately the same thermal resistance between themselves and the external thermal interface; and, as a result, custom thermal packaging solutions can be avoided. Immediately following is a more thorough discussion of the principles of operation of the technique depicted in  FIG. 2 .  
         [0021]     According to the depiction of  FIG. 2 , a semiconductor chip/die  201  with “flip-chip” technology in the form of a ball grid array (which is partially comprised of ball contacts  202 ) is shown. Thus, the metallurgy and I/O contacts for the device are located on the underside of die  201 . Atop the side of the die opposite that of its interconnect metallurgy sits the bottom floor  203  of a chamber that contains a pool of liquid  208 . The floor layer  203  includes, akin to a heat-sink structure, vertical studs  213  of thermally conductive material.  
         [0022]     Any thermally conductive stud will radiate heat generated by the semiconductor chip in a region of the semiconductor chip  201  that is, approximately, directly beneath the stud. The thermal transfer properties of the thermally conductive studs are similar to those described in the background with respect to heat sink implementations. That is, the efficiency of heat transfer from the semiconductor chip  201  into the liquid  208  is improved because the thermally conductive studs effectively correspond to a greater surface area of the chamber&#39;s floor layer  203 .  
         [0023]      FIG. 2  corresponds to a cross section depiction, and, as an example, cross sections of two regions of circuitry  209   1 ,  209   2  that generate hot spots are encircled. Assuming at least some correlation between the heat generated at a particular region of circuitry and the particular layer of the chamber&#39;s lower layer  203  where the resulting, transferred heat is observed, it is expected that the studs rising above the chamber&#39;s lower layer  203  in chamber regions  210   1 ,  210   2  will correspondingly increase the temperature of the liquid  208  to a value that is higher than other chamber regions that do not reside above a hot spot.  
         [0024]     For simplicity, these regions  210   1 ,  210   2  have been drawn to include nucleated “bubbles” that result from heat being transferred from the studs within regions  210   1 ,  210   2  residing above hot spots  209   1 ,  209   2  into liquid  208 . That is, the liquid inside regions  210   1 ,  210   2  have been depicted as boiling above hot spots  209   1 ,  209   2 . It should be understood that in many practical implementations the design point of operation within the chamber is expected to be simply that the liquid above a hot spot will nucleate bubbles  208  more rapidly than other “non hot spot” regions.  
         [0025]     As discussed above in some detail, the vaporization of the liquid  208  above the hot spot regions  209   1 ,  209   2  will result in the generation of vapor molecules above the liquid  208  within region  207  of the chamber. Owing to their high kinetic energy, the vapor molecules will effectively travel randomly within chamber region  207 , resulting in the condensation of at least some vapor molecules on the “ceiling” of the chamber  211  (note “drops” of liquid such as drops  212 ). The spread or distribution on the ceiling  211  of condensing vapor molecules that were generated from a particular region of the liquid (e.g., those from region  210   1 ) is expected to be largely random. Hence, heat generated from a particular hot spot (e.g., hot spot  209   1 ) is expected to be randomly distributed across the ceiling  211  of the chamber.  
         [0026]     Because the heat from a particular hot spot is uniformly distributed across the ceiling  211  of the chamber, the heat transfer from the particular hot spot is effectively distributed more uniformly to the external thermal interface. Importantly, this principle should apply to any hot spot irregardless of its location. As such, the approach of  FIG. 2  should be capable of cooling any semiconductor chip irregardless of its design and corresponding hot spot location profile. Therefore, the use of custom designed cooling structures can be avoided.  
         [0027]     In one embodiment, the chamber is first formed prior to its attachment to the semiconductor die  201 . For example, walls  204 ,  205  are affixed to a first layer of material used for floor layer  203 . Then, liquid is added to the chamber and lid  206  is applied over walls  204 ,  205  to seal the chamber. In an embodiment, the floor layer  203 , walls  204 ,  205  and lid  206  are each comprised of Silicon (Si). In a further embodiment, a Si lid  206  is directly bonded to the Si chamber walls. The liquid may be comprised of various solutions such as water, alcohols, refrigerants or flourinerts such as FC-77.  
         [0028]     In further or related embodiments the lid  206  has its exterior surface “processed” for efficient thermal coupling to an external thermal interface such as a heat sink. For example, the top surface of the lid  206  may be micro-machined or etched to effectively increase its surface area. Moreover or in the alternative, a layer  214  of thermally conductive material (e.g., metal) may be coated on the top surface of the lid  206 . The coating  214  may be a multi-layer structure such as a first layer of metal beneath a second Indium alloy layer.  
         [0029]     The studs  213  of floor layer  203  are comprised, in at least one embodiment, of carbon nanotubes. Here, it is generally understood in the art that carbon nanotubes may have different electrical properties. Examples include “conducting” and “semiconducting” carbon nanotubes. Generally, similar to other conducting materials, conducting carbon tubes have high thermal conductivities. Thus, in a further embodiment, the studs  213  of floor layer  203  include conducting carbon nanotubes. The use of conducting carbon nanotubes (as opposed to, for example, insulating carbon nanotubes) should enhance the transfer of heat from chamber floor layer  203  to liquid  208 .  
         [0030]     According to at least one approach, a chamber floor layer  203  with conducting carbon nanotubes  213  is formed by growing vertically oriented carbon nanotubes upon a substrate (such as a substrate comprised of Si). The substrate is used to implement chamber floor layer  203  and the vertically grown conducting carbon nanotubes correspond to studs  213 .  
         [0031]     Processes for vertically growing carbon nanotubes on a substrate (such as a substrate comprised of Si) have already been published in the art, see Z. Y. Juang, et al., 2004, “The effects of ammonia on the growth of large-scale patterned aligned carbon nanotubes using thermal chemical vapor deposition method”,  Diamond and Related Materials , Vol, 13, no. 4-8 pp. 1203-1209; H. Konishi, et al., 2004, “Growth control of carbon nanotubes on silicon carbide surfaces using the laser irradiation effect”,  Thin Solid Films , Vol. 464-465, pp. 295-298, and Ki-Hong Lee, et al., 2004, “Silicon enhanced carbon nanotube growth on nickel films by chemical vapor deposition”  Solid State Communications , Vol. 129, No. 9, pp. 583-587, each of which presents different methods for the growth of carbon nanotubes on various types of surfaces.  
         [0032]     According to one carbon nanotube growth technique, carbon nanotubes are spontaneously grown by placing a substrate coated with Nickel (Ni) into a plasma furnace containing ammonia gas and acetylene. A controlled electrical arc is passed through the sample, spontaneously causing growth of aligned nanotubes, see Z. F. Ren et al., 1998, “Synthesis of Large Arrays of Well-Aligned Carbon Nanotubes on Glass”,  Science , Vol. 282, pp. 1105-1107.  
         [0033]     Another interesting feature of using vertically oriented carbon nanotubes for studs  213  is the granularity at which the carbon nanotubes might be displaced on the surface of the chamber floor. To the extent that the heights reached by the vertically oriented carbon tubes are “short” and, as a consequence, their role of effectively increasing the surface area of the chamber floor layer  203  is less than impressive, note that that their lack of height is at least partially compensated for by the density at which they can be packed together. That is, given that carbon nanotubes are extremely small particles, they add to the effective surface area of the chamber floor layer  203  more by the number of surface perturbations that they effect rather than by the height of these perturbations.  
         [0034]      FIG. 3  shows an alternate embodiment to that of  FIG. 2  in which a liquid flow flows through the chamber  307 . Here, an input liquid flow  320  is provided at a liquid flow input and an output liquid flow  321  is produced at a liquid flow output. The liquid flow through the chamber helps to more efficiently remove heat from the chamber and the semiconductor die. Here, approximately uniform heat removal can still be accomplished if the currents of liquid flow through the chamber is approximately uniform. In a further embodiment, the liquid flow is directed to some type of heat exchanging device (not shown in  FIG. 3 ) that accepts warmed liquid from output  321  and converts the warmed liquid into cooled liquid. The liquid is retuned to the chamber  307  along with or from piping separate to that at which the input liquid flow  320  is provided.  
         [0035]     Note that each of items  301 ,  302 ,  303 ,  304 ,  305 ,  306 ,  307 ,  308 ,  309 ,  310 ,  311 ,  312 ,  313 , and  314  can behave similar to their respective counterparts  201 ,  202 ,  203 ,  204 ,  205 ,  206 ,  207 ,  208 ,  209 ,  210 ,  211 ,  212 ,  213 , and  214  discussed with respect to  FIG. 2 .  
         [0036]      FIG. 4  shows a cross section of a more complete packaged. According to the depiction of  FIG. 4 , a semiconductor die  401  is bonded to a substrate  430 . The interface between the die  401  and the substrate  430  typically contains electrical input/output connections (I/Os) such as C4 connections formed on the die  401  and bonded to pads on the substrate  430 . The external I/Os for the package can be implemented as leads or balls that emerge from the side or bottom of the substrate and that are electrically connected to the aforementioned pads by way of wiring formed within the substrate  430 .  
         [0037]     The die may be any type of die product such as a processor (e.g., general purpose processor, digital signal processor), memory device (e.g., Static Random Access Memory (SRAM) chip; Dynamic Random Access Memory (DRAM) chip) or non standard product offering Application Specific Integrated Circuit (ASIC) (i.e., a semiconductor chip not sold on the open market with its own part number or other identifier that identifies the chip alone) such as those commonly used to implement the switching and/or routing function within networking hardware equipment (e.g., switches, routers).  
         [0038]     Atop the die  401 , the complete chamber  400  containing liquid is shown. A cross section of the die  401  and chamber  400  may be as depicted in  FIG. 2  or  3 . The chamber  400  and die  401 , in an embodiment may be Si—Si fusion bonded together. Atop the chamber  400  is an (optional) external thermal interface such as a heat sink. Recall from above that the top of the chamber  400  may have its exterior surface “processed” for efficient thermal coupling to the external thermal interface. For example, the top surface of the chamber may be micro-machined or etched to effectively increase its surface area. Moreover or in the alternative, a layer of thermally conductive material (e.g., metal) may be coated on the top surface of the chamber  400 . The coating may be a multi-layer structure such as a first layer of metal beneath a second Indium alloy layer.  
         [0039]     In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.