Abstract:
A CAM system includes an integrated circuit chip having: logic &amp; control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit chip, provides a first supply voltage to the first voltage supply pad, wherein the logic &amp; control circuitry is powered by the first supply voltage. A second voltage supply, external to the integrated circuit chip, provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, wherein the second supply voltage is less than the first supply voltage.

Description:
FIELD OF THE INVENTION 
     The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to a system and method for reducing power consumption with CAM arrays. 
     RELATED ART 
     The majority of the power consumption within a CAM array results from signal switching on the search lines and the match lines coupled to the CAM cells. In general, a search operation involves pre-charging a plurality of match lines, wherein each match line is associated with a corresponding row of the CAM array. Search data is applied to search lines of the CAM array, wherein each search line or search line pair is associated with a corresponding column of the CAM array. A match line is discharged to indicate a non-matching condition if the data stored in the corresponding row of CAM cells does not match the applied search data. 
     Providing a low voltage swing on the search lines and match lines reduces power consumption within the CAM array. However, circuits that produce low voltage output signals, such as pulse-width generators and charge pumps, can be complicated and difficult to control. Moreover, circuits capable of receiving the low voltage signals as inputs, such as specialized sense amplifiers, can also be complicated and consume more power than necessary. 
     The actual value of the low voltage swing (i.e., the voltages applied to the search lines and match lines) is determined by performing simulations. The results of these simulations are used to determine the final design of the CAM array. The CAM array is then fabricated on silicon, using this final design. While it is desirable to minimize the voltage swing on the search lines and match lines to reduce power consumption, if this voltage swing is reduced too low, then the CAM array will fail to operate reliably. It is difficult to measure in simulations how low the voltage swing can be reduced without resulting in failure of the CAM array. If the voltage swing is reduced too much, such that CAM failure occurs, then the CAM array must be re-designed (and re-fabricated). Conversely, if the voltage swing is reduced too little, then the CAM array will exhibit unnecessarily high power consumption. 
     It would therefore be desirable to have a CAM array that overcomes the above-described deficiencies. 
     SUMMARY 
     Accordingly, the present invention reduces power requirements of a CAM system by limiting the voltage swing of signals transmitted on the search lines and/or the match lines of the CAM array using an external CAM core power supply for search line and/or match line related circuits. The external CAM core power supply allows a user to easily adjust the voltage swing in the search line and/or match line related circuits, thereby adjusting trade-offs between operating speed/reliability and power consumption. By supplying the search line and/or match line related circuits from a power supply located external to the chip that includes the CAM array, the voltage swing can be safely and easily adjusted in a real silicon device. 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a CAM system in accordance with one embodiment of the present invention. 
         FIG. 2  is a flow diagram illustrating the manner in which the nominal value of the V CORE  supply voltage is selected in accordance with one embodiment of the present invention. 
         FIGS. 3A ,  3 B,  3 C,  3 D and  3 E are block diagrams of CAM systems in accordance with alternate embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a CAM system  150  in accordance with one embodiment of the present invention. CAM system  150  includes a CAM device  100 , an external V DD  voltage supply  110  and an external V CORE  voltage supply  120 . CAM device  100  can be, for example, a packaged integrated circuit die (chip), which is fabricated using conventional semiconductor processing techniques. 
     CAM device  100  includes word line control circuit  101 , bit line control circuit  102 , search line control circuit  103 , match line control circuit  104 , CAM array  105 , V DD  supply pad  111 , V CORE  supply pad  121  and logic &amp; control circuitry  130 . In general, logic &amp; control circuitry  130  includes conventional circuitry that may support or supplement CAM array  105  and the associated control circuits  101 - 104 . 
     CAM array  105  includes M rows and N columns of CAM cells. Each CAM cell in CAM array  105  is labeled  10   R,C , wherein R is the row number of the cell, and C is the column number of the cell. Thus, array  105  includes CAM cells  10   1,1 - 10   M,N . These CAM cells can be, for example, binary or ternary CAM cells. Although CAM cells  10   1,1 - 10   M,N  are illustrated as having a NOR-type configuration, it is understood that these CAM cells can have a NAND-type configuration in other embodiments. 
     Each row of CAM cells is coupled to a corresponding word line. More specifically, rows  1  through M of CAM array  105  are coupled to word lines W 1 -W M , respectively. Word lines W 1 -W M  are coupled to word line control circuit  101 . 
     Each row of CAM cells is also coupled to a corresponding match line. More specifically, rows  1  through M of CAM array  105  are coupled to match lines M 1 -M M , respectively. Match lines M 1 -M M  are coupled to match line control circuit  104 . 
     Each column of CAM cells is coupled to a corresponding complementary bit line pair. More specifically, columns  1  through N of CAM array  105  are coupled to bit line pairs B 1 -B 1#  to B N -B N# , respectively. 
     Bit line pairs B 1 -B 1#  to B N -B N# , are coupled to bit line control circuit  102 . 
     Each column of CAM cells is also coupled to a corresponding complementary search line pair. More specifically, columns  1  through N of CAM array  105  are coupled to search line pairs S 1 -S 1#  to S N -S N# , respectively. Search line pairs S 1 -S 1#  to S N -S N# , are coupled to search line control circuit  103 . 
     Word line control circuit  101 , bit line control circuit  102  and logic &amp; control circuitry  130  are coupled to V DD  supply pad  111 . V DD  supply pad  111  is coupled to receive a V DD  supply voltage from external V DD  voltage supply  110 . Thus, word line control circuit  101 , bit line control circuit  102  and logic &amp; control circuitry  130  operate in response to the V DD  supply voltage. 
     Search line control circuit  103  and match line control circuit  104  are coupled to V CORE  supply pad  121 . V CORE  supply pad  121  is coupled to receive a V CORE  supply voltage from external V CORE  voltage supply  120 . Thus, search line control circuit  103  and match line control circuit  104  operate in response to the V CORE  supply voltage. In general, the V CORE  supply voltage is less than the V DD  supply voltage. Selection of the V CORE  supply voltage is described in more detail below. 
     Note that the connection between V CORE  supply pad  121  and external V CORE  voltage supply  120  can be made, for example, through a printed circuit board, wherein the V CORE  supply pad  121  is connected to the printed circuit board by a pin or a solder ball in a manner well known by those of ordinary skill in the art. 
     Also note that while only one V CORE  supply pad  121  and one V DD  supply pad  111  is illustrated in  FIG. 1 , it is understood that CAM device  100  may include multiple V CORE  supply pads and/or multiple V DD  supply pads in alternate embodiments of the present invention. 
     Word line control circuit  101  and bit line control circuit  102  implement read and write operations to CAM array  105  in a well-known manner, which is briefly described below. Word line control circuit  101  and bit line control circuit  102  may be collectively referred to as read/write access circuitry. 
     To perform a write operation, bit line control circuit  102  applies the data to be written on bit line pairs B 1 -B 1#  to B N -B N# . Word line control circuit  101  activates a word line signal on the word line of the row to be written. Under these conditions, the data provided on the bit lines is written to the CAM cells of the selected row. As described above, word line control circuit  101  and bit line control circuit  102  operate in response to the V DD  supply voltage. In one embodiment, the complementary bit lines have a signal swing from ground (0 Volts) to the V DD  supply voltage. For example, bit line control circuit  102  may provide a logic ‘1’ data value on complementary bit line pair B 1 -B 1#  by applying the V DD  supply voltage to bit line B 1 , and coupling complementary bit line B 1#  to ground. In one embodiment, the word lines also have a signal swing from ground to the V DD  supply voltage. For example, word line control circuit  101  may activate the word line W 1  by applying the V DD  supply voltage to this word line, and de-activate the word line W 1  by coupling this word line to ground. 
     To perform a read operation, word line control circuit  101  activates a word line of the row to be read, and bit line control circuit  102  activates internal sense amplifiers (not shown), which are coupled to complementary bit line pairs B 1 -B 1#  to B N -B N# . Under these conditions, the data stored in the CAM cells of the selected row is applied to the complementary bit line pairs. The enabled sense amplifiers within bit line control circuit  102  amplify the data signals on the bit line pairs, such that these data signals have a full signal swing equal to the V DD  supply voltage. For example, a sense amplifier that detects a logic ‘1’ data value on complementary bit line pair B 1 -B 1#  will pull bit line B 1  up to the V DD  supply voltage, and pull complementary bit line B 1#  down to ground. 
     Word line control circuit  101  and bit line control circuit  102  implement read and write operations to CAM array  105  in a well-known manner, which is briefly described below. Word line control circuit  101  and bit line control circuit  102  may be collectively referred to as read/write access circuitry. 
     After data has been written to CAM array  105 , search line control circuit  103  and match line control circuit  104  may implement search operations to CAM array  105  in the manner described below. Search line control circuit  103  and match line control circuit  104  may be collectively referred to as comparison access circuitry. 
     As described above, both search line control circuit  103  and match line control circuit  104  operate in response to the V CORE  supply voltage. Match line control circuit  104  initially pre-charges match lines M 1 -M M  to the V CORE  supply voltage. Search line control circuit  103  then applies search data to the complementary search line pairs S 1 -S 1#  to S N -S N# . In accordance with one embodiment of the present invention, the search data signals have a full signal swing equal to the V CORE  supply voltage. For example, search line control circuit  103  may apply a logic ‘1’ search data value on complementary search line pair S 1 -S 1#  by applying the V CORE  supply voltage to search line S 1 , and coupling the complementary search line S 1#  to ground. Under these conditions, the search data values are compared with the data values stored in CAM cells. If the search data value applied to a CAM cell does not match the data value stored in the CAM cell, then the CAM cell discharges the associated match line to ground, thereby indicating a non-match condition. However, if the search data value applied to a CAM cell matches the data value stored in the CAM cell, then the CAM cell does not discharge the associated match line to ground. If each CAM cell in a given row stores a data value that matches the applied search data value, then the match line associated with this row is not discharged, and remains charged at (or near) the V CORE  supply voltage to identify a matching condition. Note that the maximum signal swing on the match lines M 1 -M M  is advantageously limited to the V CORE  supply voltage. 
     Match line control circuit  104  includes comparator circuitry that monitors the match lines to determine which (if any) of the match lines remain charged at the end of the search operation, thereby identifying any rows that store data that matches the applied search data. Match line control circuit  104  may also include a priority encoder that identifies the matching row having the highest assigned priority. As is well known in the art, the address of this highest priority matching row can be used to access another memory (not shown). 
     Because the signals transmitted on the search lines and the match lines have a full signal swing equal to the V CORE  supply voltage, search line control circuit  103  and match line control circuit  104  do not require special circuitry to drive and receive low swing signals. 
     Reducing the signal swing on the search lines S 1 -S 1#  to S N -S N#  and the match lines M 1 -M M  advantageously reduces the power consumed during search operations. For example, assume that CAM device  100  operates in response to a V DD  supply voltage of 1.0 Volts and a V CORE  supply voltage of 0.7 Volts. During search operations, the power consumption of CAM device  100  is reduced by about 49% (i.e., 0.7*0.7) with respect to a conventional CAM device that operates the search line control circuit  103  and the match line control circuit  104  in response to the V DD  supply voltage of 1.0 Volts. 
     In order for CAM device  100  to operate at the same speed as the conventional CAM device, the search line control circuit  103  and the match line control circuit  104  can be over-designed. In one embodiment, the transistors that operate in response to the V CORE  supply voltage must be made larger than the transistors that operate in response to the V DD  supply voltage. That is, the widths of timing-critical transistors that operate in response to the V CORE  supply voltage are made larger to allow these transistors to meet the same speed performance as the transistors that operate in response to the V DD  supply voltage. Because the search line and match line capacitances are dominated by wire and CAM cell capacitances, over-designing the search line control circuit  103  and the match line control circuit  104  will not add significant capacitance to the CAM device  100 . 
     Because there is a trade-off between silicon layout area and power savings, the circuitry selected to operate in response to the V CORE  supply voltage is preferably limited to the most power consuming circuitry of the chip. 
       FIG. 2  is a flow diagram  200  illustrating the manner in which the nominal value of the V CORE  supply voltage is selected in accordance with one embodiment of the present invention. After CAM device  100  has been designed, fabricated and packaged, this CAM device is coupled to the external V DD  voltage supply  110 , such that the word line control circuit  101  and the bit line control circuit  102  receive the V DD  supply voltage (Step  201 ). 
     The CAM device  100  is also coupled to an adjustable external V CORE  voltage supply  120 , such that the search line control circuit  103  and the match line control circuit  104  receive the V CORE  supply voltage (Step  202 ). The V CORE  supply voltage is selected to have an initial value, which is less than or equal to the V DD  supply voltage (Step  202 ). The initial value of the V CORE  supply voltage is selected to have a value greater than the expected final V CORE  supply voltage. 
     The operating characteristics of the CAM device  100  are then tested at the selected V DD  and V CORE  voltages (Step  203 ). More specifically, test data is written to the CAM array  105 , and search operations are then performed to determine whether matching and non-matching conditions are reliably detected at the selected operating speed. If testing indicates that search operations can be reliably performed at the selected operating speed (Step  204 , Yes branch), then the V CORE  voltage supply  120  is adjusted to reduce the V CORE  supply voltage (Step  205 ). Processing then returns to Step  203 , wherein the operating characteristics of the CAM device  100  are tested at the reduced V CORE  supply voltage. 
     This process repeats until the V CORE  supply voltage is reduced to a voltage wherein the search operations cannot be reliably performed at the selected operating speed (Step  204 , No branch). At this time, a final value of the V CORE  supply voltage is selected from the V CORE  supply voltages that provided reliable performance at the selected operating speed (Step  206 ). The V CORE  voltage supply  120  used to supply the CAM device  100  during normal operation of CAM system  150  is configured to provide this final value of the V CORE  supply voltage. As a result, CAM system  150  is controlled to operate reliably at a desired speed, with minimum power consumption. 
     In an alternate embodiment of the present invention, Step  203  can be modified such that the CAM device is tested to determine the fastest reliable operating speed for the selected V CORE  supply voltage. The final value of the V CORE  supply voltage would then be selected to be the lowest V CORE  supply voltage that provided reliable operation at the desired operating speed of CAM device  150 . 
     In alternate embodiments of the present invention, other combinations of word line control circuit  101 , bit line control circuit  102 , search line control circuit  103  and match line control circuit  104  are operated in response to the V CORE  supply voltage.  FIGS. 3A ,  3 B,  3 C,  3 D and  3 E are block diagrams that illustrate the manner in which the V CORE  supply voltage may be applied to the control circuits  101 - 104  in accordance with alternate embodiments of the present invention. Similar elements are labeled with similar reference numbers in FIGS.  1  and  3 A- 3 E. Note that the logic &amp; control circuitry  103  is coupled to receive the V DD  supply voltage in each of the alternate embodiments represented by  FIGS. 3A-3E . Also note that at least one of the search line control circuit  103  and the match line control circuit  104  is supplied with the V CORE  supply voltage in each of these alternate embodiments. 
     As illustrated in  FIG. 3A , the V CORE  supply voltage may be used to operate search line control circuit  103 , while the word line control circuit  101 , bit line control circuit  102  and match line control circuit  104  operate in response to the V DD  supply voltage. In this embodiment, power savings are realized due to the reduced swing of the search line signal S 1 -S 1#  to S N -S N# . Match line signals M 1 -M M  undergo a full signal swing equal to the V DD  supply voltage, which may result in more reliable determination of match/non-match conditions. 
     As illustrated in  FIG. 3B , the V CORE  supply voltage may be used to operate match line control circuit  104 , while the word line control circuit  101 , bit line control circuit  102  and search line control circuit  103  operate in response to the V DD  supply voltage. In this embodiment, power savings are realized due to the reduced swing of the match line signals M 1 -M M . Search line signals S 1 -S 1#  to S N -S N#  undergo a full signal swing equal to the V DD  supply voltage, which may result in faster determination of match/non-match conditions. 
     As illustrated in  FIG. 3C , the V CORE  supply voltage may be used to operate bit line control circuit  102 , search line control circuit  103  and match line control circuit  104 , while the word line control circuit  101  operates in response to the V DD  supply voltage. In this embodiment, power savings are realized due to the reduced swing of the bit line signals B 1 -B 1#  to B N -B N# , the search line signals S 1 -S 1#  to S N -S N# , and the match line signals M 1 -M M . Word line signals W 1 -W M  undergo a full signal swing equal to the V DD  supply voltage, which may result in faster and more reliable read and write operations. 
     As illustrated in  FIG. 3D , the V CORE  supply voltage may be used to operate word line control circuit  101 , search line control circuit  103  and match line control circuit  104 , while the bit line control circuit  102  operates in response to the V DD  supply voltage. In this embodiment, power savings are realized due to the reduced swing of the word line signals W 1 -W M , the search line signals S 1 -S 1#  to S N -S N# , and the match line signals M 1 -M M . Bit line signals B 1 -B 1#  to B N -B N#  undergo a full signal swing equal to the V DD  supply voltage, which may result in faster and more reliable read and write operations. 
     As illustrated in  FIG. 3E , the V CORE  supply voltage may be used to operate word line control circuit  101 , bit line control circuit  102 , search line control circuit  103  and match line control circuit  104 . In this embodiment, power savings are realized due to the reduced swing of the word line signals W 1 -W M , the bit line signals B 1 -B 1#  to B N -B N# , the search line signals S 1 -S 1#  to S N -S N# , and the match line signals M 1 -M M . 
     Although the present invention has been described in connection with various embodiments, it is understood that variations of these embodiments would be obvious to one of ordinary skill in the art. Thus, the present invention is limited only by the following claims.