Abstract:
A Schottky diode is integrated into a planar or trench topology MOSFET having parallel spaced source regions diffused into spaced base stripes. The diffusions forming the source and base stripes are interrupted to permit the drift region to extend to the top of the die and receive a Schottky barrier metal and the source contact. The MOSFET and Schottky share the same drift region, and the pitch between base and source stripes is not changed to receive the Schottky structure.

Description:
FIELD OF THE INVENTION 
   This invention relates to semiconductor devices and more specifically relates to a power MOSFET and Schottky diode integrated in a common chip. 
   BACKGROUND OF THE INVENTION 
   It is frequently desirable to integrate a Schottky diode and MOSFET into a common chip or die and package. For example, in a synchronous buck converter circuit, the low side FET requires a low R dson , a low V f  (forward voltage drop) in the third quadrant and a low reverse recovery charge. 
   Such devices have been proposed in the past in both planar and trench topologies. For example, such a device is proposed by B. J. Baliga and Dev Alok Girdhar; Paradigm Shift In Planar Power MOSFET Technology, Power Electronics, page 24, November 2003. This device has the disadvantage of changed cell pitch and relatively poor use of silicon area. 
   It is also known to have laterally displaced MOSFET areas and Schottky areas, as in the IRF6691 device of International Rectifier, the assignee of the present application. This structure however, has a significant die area penalty because the drift region of the 2 devices is not shared. 
   Still another monolithic Schottky and MOSFET is shown in U.S. Pat. No. 6,987,305 (IR-2014). 
   It would be very desirable to provide a monolithic Schottky and FET which preserves die area and can be fabricated with a minimum change in process as compared to that used to make the MOSFET, and which employs a space saving termination structure. 
   BRIEF DESCRIPTION OF THE INVENTION 
   In accordance with the invention, a Schottky structure is inserted in short sections along the length of interrupted source and base diffusion strips of a MOSFET junction pattern. The elongated source strips can be formed in the silicon surface of a planar MOSFET, or in the mesas of a MOSFET in a trench type topology. The novel structure is formed by adding a single mask for masking the P −  base region at spaced region to permit the underlying N −  body to reach the surface to be contacted by the source/Schottky contact to form the Schottky portion of the device. 
   The pitch of the source stripes need not change to accommodate the Schottky and the same N −  drift region accommodates both the Schottky and MOSFET for a reduced area penalty. Further, a reduced area termination is also created. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a cross-section of one cell of a planar device in which a Schottky region is inserted along the length of the source strip, as shown in  FIG. 2 . 
       FIG. 2  is a top view of the planar cell of  FIG. 1 , showing the placement of the Schottky element. 
       FIG. 3  is a cross-section of one cell of a trench MOSFET in which a Schottky region is inserted along the length of the source strips in the mesas, as shown in  FIG. 4 . 
       FIG. 4  is a top view of  FIG. 3  showing the Schottky regions inserted gaps in the source strips. 
       FIG. 5  is an isometric view of a die containing an embodiment of the invention, along with the novel termination structure. 
       FIG. 6  is a schematic cross section of  FIG. 5  taken across section line  6 - 6  in  FIG. 5  to show the Schottky structure in the trench FET strips. 
       FIG. 7  is a schematic cross-section of  FIG. 5  perpendicular to the FET trench strips. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Referring first to  FIGS. 1 and 2 , there is shown a planar embodiment in which a small segment of a silicon wafer (or die)  20  has the conventional N +  substrate  21  and an N −  drift region  22  which is usually an epitaxially deposited silicon layer. A plurality of parallel spaced P type base strips, one of which is shown as P −  strip  23  are diffused into drift region  22 , and a plurality of N +  source strips, one of which is shown as strip  24  are diffused into the P base in the usual manner. A gate oxide  25  is formed over the invertible channel region  26  between source  24  and base  23  and a conductive polysilicon gate electrode  27  is formed atop oxide  25 . An insulation layer  28 , usually TEOS, covers and insulates conductive gate  27  from source electrode  29 , usually aluminum. 
   In accordance with one aspect of the invention, the length of N +  source strip  24  and base diffusion  23  are interrupted as shown in  FIG. 2  and a Schottky device  40  is formed at that location. More specifically, the base diffusion  23  and source diffusion are blocked in area  40  and a Schottky contact is made to the exposed N −  drift in area  40 . If desired, a conductive silicide barrier can be first formed atop the exposed N −  drift region, and covered by the aluminum contact. One or more such Schottky contacts may be formed in each of the base and source strips in  FIGS. 1 and 2 . 
     FIGS. 3 and 4  show an embodiment in which the Schottky diode can be incorporated into a trench type MOSFET. Thus, the starting silicon  20  has the usual N +  substrate  21  and N −  layer  22 . A P type channel diffusion  48  is formed in the top surface of layer  22  and an N +  source layer is formed atop channel region  48 . Plural spaced source trenches  50 ,  51  and a gate trench  52  are formed through source layer  49  and P channel region  48  and into silicon layer  22  as shown in  FIG. 3 . These trenches are then filled with insulation, for example, oxide bodies  53 ,  54  and  55  respectively, which is etched to receive conductive polysilicon source bodies  56  and  57  and a conductive gate polysilicon  58  respectively. A thin gate oxide (or nitride) is left between channel  48  and source bodies  56 ,  57  and gate  58 . A conductive source electrode, usually aluminum is deposited atop the wafer or die, in contact with source diffusions  49  and source polysilicon masses  56  and  57 . 
   As shown in  FIG. 4 , the source and base diffusions are patterned by suitable masks so that the N −  region  22  reaches the device surface at Schottky areas  60  and  61  where they can be contacted by the source  49  or some other Schottky forming metal layer. Thus, the novel Schottky structures are formed in the mesas between trenches  50  and  52  with no reduction in device pitch due to integrating Schottky devices and with little interference with the manufacturing process. 
     FIGS. 5 ,  6  and  7  show a further trench embodiment of the invention,  FIG. 5  showing the structure in partial isometric form, with the device termination. Thus, the starting wafer  20  has an N +  substrate  21 , and N −  epitaxially formed layer (drift region)  22 . A P −  base diffusion  48  is formed in layer  22  and an N +  source diffusion  49  is formed in base layer  48 . Further P +  base contact diffusions  70  are also formed, as usual. 
   The device active region is formed of a plurality of spaced trenches  71 ,  72 , and a termination trench  73  is also formed and surrounds the die. An oxide layer  80  overlies the surface of base  48  at the outer periphery of the die and into termination trench  73 . 
   Trenches  71  and  72  are lined with gate oxides  81  and  82  respectively and are filled with conductive polysilicon gates  83  and  84  respectively. Insulation caps  85  and  86  seal and insulate the tops of polysilicon stripe masses  83  and  84 . 
   A further conductive polysilicon mass  90  fills termination trench  76 . 
   As best shown in  FIGS. 6 and 7  short sections of the P base  48  and N +  source  49  and SP +  contact region  70  are eliminated along the length of the P base to expose a Schottky area  90  at which the N− epi region  22  reaches the surface of die  20 . Preferably, a thin conductive silicide, for example titanium silicide contacts the surface of region  90  and the N +  and P +  regions  49  and  70 , forming a Schottky barrier to N −  silicon  22  in area  90 . 
   A contact metal, for example, aluminum is then deposited atop the chip and, as shown in  FIG. 5 , is etched to form source contact  100  and gate contact bus  101 . Source contact  100  contacts source regions  49  and SP +  regions  70 , and gate bus  100  contacts trench polysilicon ring  90 . Note that the ends of polysilicon strips  83 ,  84  extend to and contacted by gate aluminum bus  90 . 
   Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.