Abstract:
An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.

Description:
[0001]     This application is a Continuation of Ser. No. 11/153,587, filed Jun. 14, 2005. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field  
         [0003]     The present invention relates to a circuit and associated method to compare contents of counter circuits.  
         [0004]     2. Related Art  
         [0005]     Electrical circuits are typically required to compare different electrical signals comprising data. Comparing different electrical signals comprising data may be time consuming and require extensive circuitry which may be costly. Therefore there is a need to provide a simple low cost electrical circuit to compare different electrical signals comprising data.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention provides an electrical circuit, comprising:  
         [0007]     a first counter circuit A for receiving a first enable signal INC_A and generating a first output signal SIG_A;  
         [0008]     a second counter circuit B for receiving a second enable signal INC_B and generating a second output signal SIG_B, wherein the first enable signal INC_A and the second enable signal INC_B are for comparing the first output signal SIG_A to the second output signal SIG_B;  
         [0009]     a flip-flop circuit for generating a first status signal definining a first relationship between said first output signal SIG_A and said second output signal SIG_B; and  
         [0010]     a logic circuit for generating a second status signal definining a second relationship between said first output signal SIG_A and said second output signal SIG_B, wherein the logic circuit electrically connects said first counter circuit A and said second counter circuit B to said flip-flop circuit, wherein an output of said first counter circuit A is electrically connected to a first input of said logic circuit, wherein an output of said second counter circuit B is electrically connected to a second input of said logic circuit, and wherein an output of said logic circuit is electrically connected to an enable input E on said flip-flop circuit.  
         [0011]     The present invention provides a method, comprising:  
         [0012]     providing an electrical circuit comprising a first counter circuit A, a second counter circuit B, a flip-flop circuit, and a logic circuit, wherein an output of said first counter circuit A is electrically connected to a first input of said logic circuit, wherein an output of said second counter circuit B is electrically connected to a second input of said logic circuit, and wherein an output of said logic circuit is electrically connected to an enable input E on said flip-flop circuit;  
         [0013]     receiving by said first counter circuit A, a first enable signal INC_A;  
         [0014]     generating by said first counter circuit A, a first output signal SIG_A;  
         [0015]     receiving by said second counter circuit B, a second enable signal INC_B;  
         [0016]     generating by said second counter circuit B, a second output signal SIG_B;  
         [0017]     comparing by said first enable signal INC_A and said second enable signal INC_B, said first output signal SIG_A to said second output signal SIG_B;  
         [0018]     generating by said flip-flop circuit, a first status signal definining a first relationship between said first output signal SIG_A and said second output signal SIG_B; and  
         [0019]     generating by said logic circuit, a second status signal definining a second relationship between said first output signal SIG_A and said second output signal SIG_B.  
         [0020]     The present invention provides a method for forming an electrical circuit, comprising:  
         [0021]     providing a first counter circuit, a second counter circuit, a flip-flop circuit, and a logic circuit;  
         [0022]     electrically connecting an output of said first counter circuit to a first input of said logic circuit;  
         [0023]     electrically connecting an output of said second counter circuit to a second input of said logic circuit; and  
         [0024]     electrically connecting an output of said logic circuit to an enable input E on said flip-flop circuit.  
         [0025]     The present invention provides a computer program product, comprising a computer usable medium having a computer readable program code embodied therein, said computer readable program code comprising an algorithm adapted to implement a method for simulating a formation of an electrical circuit, said method comprising the steps of:  
         [0026]     providing a first counter circuit, a second counter circuit, a flip-flop circuit, and a logic circuit;  
         [0027]     electrically connecting an output of said first counter circuit to a first input of said logic circuit;  
         [0028]     electrically connecting an output of said second counter circuit to a second input of said logic circuit; and  
         [0029]     electrically connecting an output of said logic circuit to an enable input E on said flip-flop circuit.  
         [0030]     The present invention provides a method for simulating a formation of an electrical circuit, comprising integrating computer-readable code into a computing system, wherein the code in combination with the computing system is capable of performing the steps of:  
         [0031]     providing a first counter circuit, a second counter circuit, a flip-flop circuit, and a logic circuit;  
         [0032]     electrically connecting an output of said first counter circuit to a first input of said logic circuit;  
         [0033]     electrically connecting an output of said second counter circuit to a second input of said logic circuit; and  
         [0034]     electrically connecting an output of said logic circuit to an enable input E on said flip-flop circuit.  
         [0035]     The present invention provides advantageously provides a simple low cost electrical circuit to compare different electrical signals comprising data. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0036]      FIG. 1  illustrates an a schematic of an electrical circuit, in accordance with embodiments of the present invention.  
         [0037]      FIG. 2  illustrates a modified schematic of the electrical circuit of  FIG. 1 , in accordance with embodiments of the present invention.  
         [0038]      FIG. 3  illustrates a modified schematic of the electrical circuit of  FIG. 2 , in accordance with embodiments of the present invention.  
         [0039]      FIG. 4  illustrates a computer system used for simulating a formation of an electrical circuit, in accordance with embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0040]      FIG. 1  illustrates an a schematic of an electrical circuit  2 , in accordance with embodiments of the present invention. The electrical circuit  2  comprises a flip-flop circuit  11 , counter circuits: Counter A and Counter B, AND gates  15 ,  18 , and  22  and a logic circuit  17 . The logic circuit  17  comprises exclusive NOR gates (XNOR)  4 ,  6 ,  9 , and  10  and an AND gate  12 . The logic circuit  17  may comprise, inter alia, a comparator circuit. Counter A and counter B are each electrically coupled to an input of logic circuit  17 . An output of logic circuit  17  is electrically coupled to an enable input E of the flip-flop circuit  11 . An output of the AND gate  18  is electrically coupled to a data input D of the flip-flop circuit  11 . Outputs Q and Q′ of the flip-flop circuit  11  are electrically coupled to inputs of the AND gates  15  and  22  respectively. There are many circuit applications that require comparison of contents (e.g., contents A 0 , A 1 , A 2 , and A 3  with contents B 0 , B 1 , B 2 , and B 3 ) within two counters (e.g.,Counter A and Counter B). In most cases, both counters will be reset (i.e., initialized with a logic low) or preset with a known value (for example, see  FIG. 2  and  FIG. 3 ) when the hardware (e.g., electrical circuit  2 ) is initialized. During operation of the circuit  2 , the counters will be incremented/decremented independently based on different conditions. There may be a requirement (i.e., within a logic circuit) to compare counter contents and provide a relationship between the contents to make a decision in a logic circuit.  
         [0041]     The electrical circuit  2  compares an output signal SIG_A (i.e., counter A contents) from counter A with an output signal SIG_B (i.e., counter B contents) from counter B and generates a status signal(s) (e.g., signal SIG_A&gt;B, signal SIG_A&lt;B, signal SIG_A=B) definining a relationship between the output signal SIG_A and the output signal SIG_B.  FIG. 1  illustrates output signal SIG_A comprising a four-bit word A 0  . . . A 3  and output signal SIG_B comprising a four-bit word B 0  . . . B 3  for illustration purposes. Note that the circuit  2  may be adapted to compare content of any size from counter A with content of any size from counter B.  
         [0042]     The status signals SIG_A&gt;B, SIG_A&lt;B, and SIG_A=B are generated using the following procedure. At an initial condition (e.g., a hardware initialization), counter A and counter B are each reset to a logical low. Signals INC_A and INC_B each represent an enable signal. Signal INC_A is applied to counter A. Signal INC_B is applied to counter B. When signal INC_A comprises a logical high, counter A contents (i.e., output signal SIG_A) are incremented by one during each clock cycle. When signal INC_B comprises a logical high, counter B contents (i.e., output signal SIG_B) are incremented by one during each clock cycle. The signals INC_A and INC_B along with the logic circuit  17  are used to generate a first relationship between output signal SIG_A and output signal SIG_B and represented by an signal SIG_A=B. The signal SIG_A=B indicates that counter A contents (i.e., SIG_A) are equal to counter B contents (i.e., SIG_B). The signal SIG_A=B is located on an output of the AND gate  12 . The signal SIG_A=B may be applied to external logic circuitry that requires a signal to indicate that counter A contents are equal to counter B contents. Additionally, the signal SIG_A=B is applied to an enable input on the flip-flop circuit  11  to enable the flip-flop circuit  11  to generate another status signal(s) (e.g., signal SIG_A&gt;B or signal SIG_A&lt;B) definining a relationship between the output signal SIG_A and the output signal SIG_B. The signals INC_A and INC_B are additionally applied to inputs of the AND gate  18  thereby creating an output signal SIG_D from the AND gate  18  that is applied to a data input D on the flip-flop circuit  11 . The signal SIG_A=B is additionally applied to each of the AND gates  15  and  22 . The signals INC_A and INC_B applied to the inputs of the AND gate  18  and the signal SIG_A=B applied to the enable input E on the flip-flop circuit  11  are used to control the flip-flop circuit  11  to generate the signal SIG_A&gt;B and signal SIG_A&lt;B on outputs of AND gates  15  and  22  respectively. The signals INC_A and INC_B applied to the inputs of the AND gate  18  determine the output signal SIG_D and in turn the output signal SIG_D updates the flip-flop circuit  11  based on the a logic state of the signals INC_A and INC_B. The signal SIG_A=B applied to the enable input E on the flip-flop circuit  11  enables or disables the flip-flop circuit  11  dependent upon a logic state of the signal SIG_A=B. The signals SIG_A&gt;B and SIG_A&lt;B are generated when one counter content crosses the other (i.e., Counter A and Counter B). Both counters contents become equal for at least one clock cycle before the cross over condition. With this condition, the signal SIG_A=B changes to signal SIG_A&gt;B or signal_A&lt;B. Although the circuit  2  comprises both the AND gates  15  and  22 , note that the circuit  2  may comprise only AND gate  15  in a case where only the SIG_A&gt;B is required or the circuit  2  may comprise only AND gate  22  in a case where only the SIG_A&lt;B is required. Table 1 below illustrates a truth table denoting signal logic levels (i.e., logic high: 1 and logic low: 0) for signal SIG_A=B applied to the enable input E of the flip-flop circuit  11 , signal logic levels for the signals INC_A and INC_B applied to the inputs of the AND gate  18 , and signal logic levels for the signal SIG_D applied to the data input D of the flip-flop cicuit  11 . The logic levels are used to control the flip-flop circuit  11  to generate the signal SIG_A&gt;B and signal SIG_A&lt;B on outputs of AND gates  15  and  22  respectively. Signal SIG_D applied to the data input D of the flip-flop cicuit  11 .  
                                   TABLE 1                                   A = B   INC_A   INC_B   D                           0   x   x   D(n − 1)           1   0   0   0           1   0   1   0           1   1   0   1           1   1   1   0                      
 
         [0043]     As illustrated in Table 1, when signal SIG_A=B is at a logic low (i.e, logic 0), the flip-flop circuit  11  content will hold a current value (i.e., flip-flop circuit  11  contents will not be changed). When signal SIG_A=B is at logic high (i.e., logic 1), the flip-flop circuit  11  content is updated according to a logic state of the signals INC_A and INC_B.  
         [0044]     The AND gate  15  is used to block an output signal SIG_Q from the output Q of the flip-flop circuit  11  when counter A contents equals counter B contents (i.e., signal SIG_A=B is generated). At this point, signal SIG_A=B comprises a logic high and blocks the flip-flop circuit  11  output (i.e., the signal SIG_Q from the output Q of the flip-flop circuit  11 ) from reaching the signal SIG_A&gt;B (signal SIG_A=B output is a logic high when counter A contents equals counter B contents). Since signal SIG_A=B is high when counter A and counter B comprise equal content, the flip-flop circuit  11  will be updated only in a next clock cycle and the signal SIG_A&gt;B is generated on an output of the AND gate  15 . Likewise, the signal SIG_A&lt;B is generated on an output of the AND gate  22 . Table 2 below illustrates a truth table denoting signal logic levels for signals SIG_A&gt;B, SIG_A&lt;B, and SIG_A=B dependent upon the relationship between the contents counter A and counter B.  
                           TABLE 2                       Relationship                   Between Counter       Contents   SIG_A &gt; B   SIG_A &lt; B   SIG_A = B                   counter A &gt; counter B   1   0   0       counter A &lt; counter B   0   1   0       counter A = counter B   0   0   1                  
 
         [0045]      FIG. 2  illustrates a modified schematic of the electrical circuit  2  of  FIG. 1  represented by a circuit  15 , in accordance with embodiments of the present invention. In contrast with the electrical circuit  2  of  FIG. 1 , the circuit  15  of  FIG. 2  comprises a signal PRE_A applied to the counter A and a signal PRE_B applied to the counter B. Additionally, the signals PRE_A and PRE_B are applied to the flip-flop circuit  11 . The signal PRE_A is applied to a preset input PRE on the flip-flop circuit  11 . The signal PRE_B is applied to a reset input RST on the flip-flop circuit  11 . The signals PRE_A and PRE_B are used to set or reset the flip-flop circuit  11  respectively if one of the counters Counter A or Counter B is preset with a value during initialization of the circuit  15 . During a reset function, if a value (i.e., for content) is preset in the Counter A, the flip-flop circuit  11  will be set indicating that Counter A content is larger than counter B content. Likewise, presetting a value (i.e., for content) in Counter B will reset the flip-flop circuit  11 .  
         [0046]      FIG. 3  illustrates a modified schematic of the electrical circuit  15  of  FIG. 2  represented by a circuit  32 , in accordance with embodiments of the present invention. In contrast with the electrical circuit  15  of  FIG. 2 , the circuit  32  of  FIG. 3  comprises a signal RST_A applied to the Counter A and a signal RST_B applied to the Counter B. Additionally, the circuit  32  comprises OR gates  25  and  28  electrically coupled to the flip-flop circuit  11 . The OR gate  25  is coupled to a input PRE on the flip-flop circuit  11 . The OR gate  28  is coupled to an input RST on the flip-flop circuit  11 . The signals PRE_A and RST_B are applied to the OR gate  25 . The signals PRE_B and RST_A are applied to the OR gate  28 . The signals RST_A and RST_B are the reset signals for Counter A and Counter B respectively. Whenever Counter B is reset, the flip-flop circuit  11  is set to indicate that Counter A content is larger than counter B content. Signal RST_B is ORed with signal PRE_A (i.e., through the OR gate  25 ) and applied on the input PRE of the flip-flop circuit  11 . Likewise, signal RST_A signal is ORed with signal PRE_B (i.e., through the OR gate  28 ) and applied the input RST of the flip-flop circuit  11 . The aforementioned process will assure that when Counter A is reset, the flip-flop circuit  11  will also be reset to reflect a new status.  
         [0047]      FIG. 4  illustrates a computer system  90  used for simulating a formation of an electrical circuit, in accordance with embodiments of the present invention. The computer system  90  comprises a processor  91 , an input device  92  coupled to the processor  91 , an output device  93  coupled to the processor  91 , and memory devices  94  and  95  each coupled to the processor  91 . The input device  92  may be, inter alia, a keyboard, a mouse, etc. The output device  93  may be, inter alia, a printer, a plotter, a computer screen, a magnetic tape, a removable hard disk, a floppy disk, etc. The memory devices  94  and  95  may be, inter alia, a hard disk, a floppy disk, a magnetic tape, an optical storage such as a compact disc (CD) or a digital video disc (DVD), a dynamic random access memory (DRAM), a read-only memory (ROM), etc. The memory device  95  includes a computer code  97 . The computer code  97  includes an algorithm for simulating a formation of an electrical circuit. The processor  91  executes the computer code  97 . The memory device  94  includes input data  96 . The input data  96  includes input required by the computer code  97 . The output device  93  displays output from the computer code  97 . Either or both memory devices  94  and  95  (or one or more additional memory devices not shown in  FIG. 4 ) may be used as a computer usable medium (or a computer readable medium or a program storage device) having a computer readable program code embodied therein and/or having other data stored therein, wherein the computer readable program code comprises the computer code  97 . Generally, a computer program product (or, alternatively, an article of manufacture) of the computer system  90  may comprise said computer usable medium (or said program storage device).  
         [0048]     Thus the present invention discloses a process for deploying or integrating computing infrastructure, comprising integrating computer-readable code into the computer system  90 , wherein the code in combination with the computer system  90  is capable of performing a method for simulating a formation of an electrical circuit.  
         [0049]     While  FIG. 4  shows the computer system  90  as a particular configuration of hardware and software, any configuration of hardware and software, as would be known to a person of ordinary skill in the art, may be utilized for the purposes stated supra in conjunction with the particular computer system  90  of  FIG. 4 . For example, the memory devices  94  and  95  may be portions of a single memory device rather than separate memory devices.  
         [0050]     While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.