Abstract:
A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority benefit of French patent application number 12/50950, filed on Feb. 1, 2012, which is hereby incorporated by reference to the maximum extent allowable by law. 
       BACKGROUND 
       [0002]    1. Technical field 
         [0003]    The present disclosure relates to integrated circuits comprising transistors distributed in several levels. Such integrated circuits comprise a stack of at least two semiconductor layers separated by an insulating layer. This is often referred to as three-dimensional (3D) integration, and 3D integrated circuits. 
         [0004]    2. Discussion of the Related Art 
         [0005]    Increasing the component density in integrated circuits generally is a constant concern. A solution is to manufacture integrated circuits comprising components distributed in several levels of semiconductor layers. 
         [0006]      FIG. 1  is a cross-section view schematically showing an example of a 3D integrated circuit comprising transistors distributed in two levels, the integrated circuit being formed on an SOI-type (“Silicon-On-Insulator”) wafer  1 . 
         [0007]    Wafer  1  comprises a semiconductor substrate  3  covered with an insulating layer  5 , currently called BOX (“Buried OXide”), itself coated with a semiconductor layer  7 . A conductive layer  4 , called rear electrode, may be present in wafer  1  under insulating layer  5 . 
         [0008]    A MOS transistor T 1  formed in semiconductor layer  7  is illustrated. Transistor T 1  comprises a conductive gate  9  insulated from the upper surface of semiconductor layer  7  by a gate insulator  11 . Spacers  13  surround gate  9 . Source and drain areas  15  extend in layer  7  on either side of gate  9 . In the following description, transistor T 1  is called the lower transistor. 
         [0009]    An insulating layer  29  separates semiconductor layer  7  comprising transistor T 1  from another semiconductor layer,  17 , comprising other MOS transistors such as transistor T 2 . Transistor T 2  comprises a gate  19  arranged on a gate insulator  21 , spacers  23 , and source and drain regions  25 . An insulating layer  33  covers semiconductor layer  17  and transistor T 2 . In the following description, transistor T 2  is called the upper transistor. 
         [0010]    Contacts  35  crossing insulating layer  33  provide access to source and drain regions  25  and to gate  19  of transistor T 2 . Contacts crossing insulating layer  33  and insulating layer  29 , not shown, provide access to source and drain regions  15  and to gate  9  of transistor T 1 . 
         [0011]    An example of a method enabling to obtain an integrated circuit such as that illustrated in  FIG. 1  is the following. 
         [0012]    MOS transistors such as transistor T 1  are formed on a wafer  1  by implementing manufacturing steps currently used for MOS transistor manufacturing. Once transistors T 1  have been formed, an insulating layer  30  is deposited above the upper surface of semiconductor layer  7  of wafer  1  and above transistors T 1 , after which insulating layer  30  is leveled. 
         [0013]    One of the surfaces of another semiconductor wafer, covered with an insulator layer  31 , is then applied on insulating layer  30 , to obtain a bonding between wafer  1  comprising transistors T 1  and covered with layer  30  and the other wafer. After the bonding, the other wafer is thinned to obtain the desired thickness for semiconductor layer  17 . 
         [0014]    At this stage of the process, above semiconductor layer  7  comprising transistors T 1 , a stack of an insulating layer  29 , formed of insulating layers  30  and  31 , and of a semiconductor layer  17  has been obtained. Manufacturing steps currently used for the manufacturing of MOS transistors are then implemented to manufacture MOS transistors such as transistor T 2  in semiconductor layer  17 . 
         [0015]    In certain applications, it is desirable to be able to dynamically and independently adjust the threshold voltage of the lower transistor and the threshold voltage of the upper transistor. 
         [0016]    The threshold voltage of lower transistor T 1  may be adjusted by applying a variable voltage to rear electrode  4 . 
         [0017]    Rear electrode  4  is generally formed by high-energy implantation of dopant elements in wafer  1  before the forming of transistor T 1 . After this implantation step, an anneal for activating the dopant elements is performed, generally at a relatively high temperature, for example, at a temperature greater than 900° C. 
         [0018]    Since semiconductor layer  17  supporting upper transistor T 2  is separated from semiconductor layer  7  supporting lower transistor T 1  by an insulating layer  29 , it is not possible to implant dopant elements in insulating layer  29  to also form a rear electrode under upper transistor T 2  in order to adjust its threshold voltage. 
       SUMMARY 
       [0019]    An embodiment provides an integrated circuit comprising transistors distributed in several levels, and enabling to dynamically adjust the threshold voltage of transistors located in an upper level. 
         [0020]    Another embodiment provides a method for manufacturing an integrated circuit comprising transistors distributed in several levels, and enabling to dynamically adjust the threshold voltage of transistors located in an upper level. 
         [0021]    Thus, an embodiment provides a method for manufacturing an integrated circuit, comprising the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer. 
         [0022]    According to an embodiment, the method further comprises, after the step of forming of the second transistors on the second semiconductor layer, a step of deposition of a third insulating layer on the second semiconductor layer and the second transistors, and a step of forming of a contact crossing the third insulating layer and the second insulating layer all the way to the conductive layer. 
         [0023]    According to an embodiment, the first insulating layer is made of silicon oxide and has a thickness ranging between 20 and 100 nm between the gates of the first transistors and the conductive layer, and the second insulating layer is made of silicon oxide and has a thickness ranging between 10 and 25 nm 
         [0024]    According to an embodiment, the conductive layer is made of a metallic material selected from the group comprising titanium, tantalum, and tungsten. 
         [0025]    According to an embodiment, the conductive layer is made of doped polysilicon. 
         [0026]    According to an embodiment, the method further comprises, before the step of bonding the semiconductor wafer to the second insulating layer, a step of forming of a fourth insulating layer on the semiconductor wafer. 
         [0027]    According to an embodiment, the first semiconductor layer is the upper portion of another semiconductor wafer. 
         [0028]    An embodiment provides an integrated circuit comprising, in stacked fashion: a first semiconductor layer comprising at least one first transistor; a first insulating layer; a conductive layer; a second insulating layer; and a second semiconductor layer comprising at least one second transistor. 
         [0029]    According to an embodiment, the conductive layer is connected to a pad capable of receiving a bias voltage. 
         [0030]    The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIG. 1 , previously described, is a cross-section view schematically showing an example of a 3D integrated circuit; 
           [0032]      FIG. 2  is a cross-section view schematically showing a 3D integrated circuit comprising two stacked semiconductor layers, in which the threshold voltage of the transistors located on the semiconductor layer of the upper level is adjustable; and 
           [0033]      FIGS. 3A to 3E  are cross-section views schematically showing successive steps of a method for manufacturing a 3D integrated circuit of the type illustrated in  FIG. 2 . 
       
    
    
       [0034]    For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of integrated circuits, the various drawings are not to scale. 
       DETAILED DESCRIPTION 
       [0035]      FIG. 2  is a cross-section view schematically showing a 3D integrated circuit formed on a wafer  41 . 
         [0036]    Wafer  41  for example is an SOI-type wafer, comprising a semiconductor substrate  43 , for example, made of silicon, covered with an insulating layer  45 , for example, made of silicon oxide, itself covered with a semiconductor layer  47 , for example, made of silicon. Wafer  41  may also be a so-called solid semiconductor substrate, for example, a silicon wafer. A conductive layer  44 , called rear electrode, generally obtained by drive in, may be present in wafer  41 , between insulating layer  45  and substrate  43 . 
         [0037]    As an example of order of magnitude, in the case of an SOI wafer, the thickness of insulating layer  45  ranges between 10 and 145 nm, and for example is on the order of  25  nm, and the thickness of semiconductor layer  47  for example ranges between 3 and 100 nm 
         [0038]    Semiconductor layer  47  comprises MOS transistors such as transistor T 3 . Transistor T 3  comprises a gate  49  arranged on a gate insulator  51 , spacers  53 , and source and drain regions  55 . 
         [0039]    In the case where layer  47  has a low thickness, for example, ranging between 3 and 15 nm, for example, on the order of 6 nm, the epitaxy is resumed above layer  47 , after the forming of gate  49  and spacers  53 , to obtain a semiconductor layer  57  above source and drain regions  55 . Semiconductor layer  57  enables to form a contacting silicide layer on source and drain regions  55  while maintaining a sufficient thickness for the source and drain regions. The total thickness of layers  55  and  57  for example ranges between 20 and 30 nm, and for example is on the order of 25 nm. 
         [0040]    An insulating layer  59  covers the upper surface of semiconductor layer  47  (or  57 ) and transistor T 1 . A conductive layer  61  covers insulating layer  59 . Conductive layer  61  is made of a metallic material, for example titanium (Ti), tantalum (Ta), or tungsten (W), or of doped polysilicon. An insulating layer  63  covers conductive layer  61 . 
         [0041]    As an example, insulating layer  59  is made of silicon oxide and the thickness of the portion of insulating layer  59  placed between gate  49  of transistor T 3  and conductive layer  61  ranges between 20 and 100 nm, and for example is on the order of 25 nm. Insulating layer  63  is for example made of silicon oxide and has a thickness for example ranging between 10 and 25 nm, for example, on the order of 15 nm. 
         [0042]    A semiconductor layer  67  is located above insulating layer  63  and comprises other MOS transistors such as transistor T 4 . Transistor T 4  comprises a gate  69  arranged on a gate insulator  71 , spacers  73 , and source and drain regions  75 . Under gate  69  and between source and drain  75  is defined a channel region  76 . Like for transistor T 3 , the epitaxy may have been resumed to form a semiconductor layer  77  above source and drain regions  75 . 
         [0043]    The thickness of semiconductor layer  67  for example ranges between 3 and 15 nm, and for example is on the order of  6  nm The thickness of layer  77  for example ranges between 10 and 20 nm and for example is on the order of 15 nm. 
         [0044]    An insulating layer  83  covers the upper surface of the structure. Contacts  85  crossing insulating layer  83  provide access to source and drain regions  75  and to gate  69  of transistor T 4 . 
         [0045]    Conductive layer  61  extends at least under channel region  76  of transistor T 4 , to obtain an electrostatic coupling between conductive layer  61  and channel region  76  to be able to adjust the threshold voltage of transistor T 4 . Conductive layer  61  is interrupted where contacts providing access to source and to drain  55  of lower transistor T 3  are formed. 
         [0046]    A contact  89  crossing insulating layers  83  and  63  provides access to conductive layer  61 . Contact  89  is connected to a pad capable of receiving a bias voltage. Thus, a variable voltage can be applied on conductive layer  61 . 
         [0047]    The nature of the insulating material(s) of layer  63  as well as its thickness are selected to provide a good electrostatic coupling between conductive layer  61  and channel region  76  of upper transistor T 4 . 
         [0048]    Thus, a modification of the voltage applied on conductive layer  61  enables to adjust the threshold voltage of upper transistor T 4 . Further, conductive layer  61  behaves as an electrostatic shield between lower transistor T 3  and upper transistor T 4 . 
         [0049]      FIGS. 3A to 3E  are cross-section views schematically showing successive steps of a method for manufacturing a 3D integrated circuit of the type illustrated in  FIG. 2 . 
         [0050]      FIG. 3A  shows an SOI-type wafer  41  on which MOS transistors such as transistor T 3  have been formed. A rear electrode  44  has been formed by implantation of dopant elements in wafer  41  before the forming of transistor T 3 . After this implantation step, an anneal for activating the dopant elements has been performed, for example at a temperature ranging between 900 and 1,100° C., for example, on the order of 900° C. Steps currently used for the manufacturing of MOS transistors have then been implemented to manufacture MOS transistor T 3 . 
         [0051]      FIG. 3B  illustrates a step of deposition of an insulating layer  59  above semiconductor layer  47  (or  57 ) and above transistor T 3 . The deposition of insulating layer  59  is for example performed by high-density plasma deposition (HDP) from a precursor of tetraethoxysilane (Si(OC 2 H 5 ) 4 ), commonly called TEOS. After having been deposited, layer  59  has been leveled, for example, by chem.-mech. polishing. 
         [0052]      FIG. 3C  illustrates the structure after deposition of a conductive layer  61 , for example, by chemical vapor deposition (CVD), above the upper surface of insulating layer  59 . An insulating layer  62 , for example, made of silicon oxide, has then been formed above conductive layer  61 . 
         [0053]      FIG. 3D  illustrates a step of bonding of one of the surfaces of another wafer  42 , for example, a silicon substrate, preferably previously covered with an insulating layer  64 , on the upper surface of the structure in the state illustrated in  FIG. 3C . 
         [0054]      FIG. 3E  illustrates the structure after thinning of wafer  42 , which has enabled to obtain a semiconductor layer  67  of desired thickness. The thickness of semiconductor layer  67  for example ranges between  3  and  15  nm, and for example is on the order of  6  nm Steps currently used for the manufacturing of MOS transistors have then been implemented to form MOS transistors such as transistor T 4  on semiconductor layer  67 . 
         [0055]    After the deposition of an insulating layer  83  above layer  67  (or  77 ) and transistor T 4 , the forming of contacts providing access to the sources, drains, and gates of transistors T 3  and T 4 , and the forming of a contact  89  providing access to conductive layer  61 , a structure of type illustrated in  FIG. 2  is obtained. 
         [0056]    An advantage of an integrated circuit of the type illustrated in  FIG. 2  is that conductive layer  61  between the upper level transistor and the lower level transistor creates an electrostatic isolation between the two transistors. 
         [0057]    An advantage of a method of the type described in relation with  FIGS. 3A to 3E  is that the upper level structure is formed without implying any high-temperature processing. 
         [0058]    Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, although a 3D integrated circuit manufactured on an SOI-type structure has been described, a so-called solid semiconductor substrate, for example, made of silicon, may be used. Further, although a 3D integrated circuit comprising MOS transistors distributed in two levels of semiconductor layers, the present invention of course applies to the case of a stack of more than two semiconductor layer levels. 
         [0059]    Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. 
         [0060]    Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.