Abstract:
A voltage regulator apparatus includes an error amplifier that amplifies a voltage difference between a reference and a sampled output voltage of the voltage regulator apparatus. A driver amplifier has an input that is responsive to the amplified voltage difference to produce a gate driving voltage at its output. An output transistor having a drain, a gate, and a source is also included. The gate is responsive to the gate driving voltage to produce a regulated output voltage at the source. To stabilize the voltage regulator apparatus, a Miller compensation capacitor is provided to feed a sample of the regulated output voltage back to the input of the driver amplifier; and additionally, an Ahuja compensation circuit is provided to feed back a portion of the regulated output voltage back to the input of the driver amplifier.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of U.S. Provisional Application Ser. No. 60/436,079, filed on Dec. 23, 2002, which is hereby incorporated by reference in its entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to voltage regulators, and more particularly to compensation for voltage regulators. 
   BACKGROUND OF THE INVENTION 
   Referring now to  FIG. 1 , a low drop-out (LDO) voltage regulator  10  includes an error amplifier  12 , a transistor  14 , and a voltage divider including resistors R 1 , R 2 . An output voltage of voltage regulator  10  is controlled by a feedback connection V FB . A reference voltage V REF  and a resistive ratio of resistors R 1  and R 2  determine the value of the output voltage. Transistor  14  may be a PMOS transistor, which provides the required load current. 
   A minimum permissible drop out voltage defines the maximum efficiency of the voltage regulator  10 . The minimum drop out voltage of voltage regulator  10  is proportional to a minimum overdrive voltage that is required to keep transistor  14  in saturation. Lower drop-out voltages tend to decrease the stability of voltage regulator  10 , because a lower drop out voltage requires the use of a larger transistors  14  with both a higher gate parasitic capacitance C par  and a higher transconductance g m . Larger transistors are also required to accommodate higher maximum load currents, which increases driver amplifier load capacitance C par . For example, C par  may be in the range of 400 pF to 800 pF in this application. 
   At least two low frequency poles must be considered when the frequency response of voltage regulator  10  is evaluated. One pole is located at output V OUT  of voltage regulator  10  and the other pole is located at gate  16  of transistor  14 . A phase margin of a feedback loop including error amplifier  12 , transistor  14 , and voltage divider R 1  and R 2  can become negative when other parasitic poles are close to two low frequency poles, which may cause the feedback loop to be unstable. The impedance seen from a drain  18  of transistor  14  is high under light load conditions (i.e., relatively large R L ) and is inversely proportional to the load current. The output pole is not isolated from the loading conditions. 
   The output pole cannot be made dominant because it varies widely with the load current through R L  (from 0 to 800 mA in this application) and load capacitance C L  (from 2 μF up to 100 μF in this application). The situation may worsen if voltage regulator  10  drives a purely resistive load. For example, if the load resistance is 10 ohms and the load capacitance is 2 μF, then the load pole is located at about 8 kHz. Thus, for an open loop gain of 500, the system gain bandwidth will increase to 4 MHz. This gain bandwidth is very high and requires a relatively high current in the error amplifier and/or buffer between it and the pass device. Otherwise, the pole introduced by the capacitance of gate  16  of the transistor  14  will decrease the system phase margin. For load capacitor compensation (external compensation), the loop gain cannot be too high (typically, total voltage regulator  10  open loop gain is around 400 to 500), but lower open loop gain provides correspondingly worse load and line regulation. 
   Miller compensation can be used to provide increased stability of voltage regulator  10 . Referring now to  FIG. 2 , a driver amplifier  20  with an inner loop or feedback path including Miller capacitor C m  is inserted between output  22  of error amplifier and gate  16  of transistor  14 . Driver amplifier  20  is a high bandwidth buffer with low output impedance and a selected gain. Driver amplifier  20  increases the efficiency of Miller compensation by boosting the effective transconductance of transistor  14  to A 1 g mL , and also helps to overcome the effect of large capacitance C g  at gate  16  of transistor  14  on pole splitting. 
   Voltage regulator  10 A thus has two loops or feedback paths. The first is an outer loop  24  from a positive input  26  of error amplifier  12  to an input  28  of driver amplifier  20  to gate  16  of transistor  14 , and closed through drain  18  of transistor  14  and R 2 . A second, inner loop  30  from V OUT1  to gate  36  of transistor  14  is closed through drain  18  of transistor  14  and Miller capacitor C M . For voltage regulator  10 A to be stable, both inner loop  30  and outer loop  24  must be stable. 
   More particularly, with respect to outer loop  24 , the dominant pole at V out1  is at
 
ω P1 =1/( r   0   A   1   g   mL   r   L   C   m )  (1)
 
the second pole at V out  is at:
 
ω P2   =A   1   g   mL   /C   L   (2)
 
and the third pole at V ga  is at:
 
ω P3 =1/( r   1   C   g ).  (3)
 
Miller compensation introduces a zero:
 
ω Zm   =−A   1   g   mL   /C   m .  (4)
 
   There are high frequency poles and zeros in driver amplifier  20 . The transfer function from V REF  to V OUT  is:
 
 A   v ( s )= A   0 *(1− s/ω   Zm )/[(1+ s/ω   P1 )(1+ s/ω   P2 )(1+ s/ω   P3 )],  (5)
 
where A 0 =g m0 r 0 A 1 g mL r L , is the total open loop gain of the voltage regulator. Let ω u  represent the unity gain bandwidth frequency and ω t  the gain bandwidth, A 0 ω d . Then for a two-pole system, the unity gain-bandwidth and phase margin (PM) relationship is:
 
ω u =ω t  sin ( PM )  (6)
 
or
 
ω u =ω P2 /tan ( PM ).  (7)
 
   The zero due to Miller compensation is located at a very high frequency. If it is assumed that the third pole is located at relatively high frequency with respect to the unity gain bandwidth, outer loop  24  can be treated as a two-pole system. The gain bandwidth is written:
 
ω t   =A   0 ω P1   =g   m0 /(2ω C   m )  (8)
 
From equations (6) and (8), the unity gain bandwidth is given by:
 
ω u   =g   m0  sin ( PM )/ C   m   (9)
 
The relation between second pole position, unity gain bandwidth and phase margin can be obtained from eq. (2), (7) and (9):
 
 A   1   g   mL   /C   L   =g   m0  sin ( PM ) tan ( PM )/ C   m   (10)
 
Thus, the gain of the driver amplifier  20  can be estimated for a given load condition, compensation and load capacitances and loop phase margin.
 
   A high gain bandwidth driver amplifier is needed to maintain a reasonable phase margin of the outer loop. For a given load capacitance C L , doubling the gain of driver amplifier  20  will double the gain bandwidth. The output impedance of driver amplifier  20  must be reduced by half to keep the same phase margin. At the same time all parasitic poles and zeros in driver amplifier  20  must be pushed to higher frequencies. 
   With respect to inner loop  30  stability, the inner loop has a pole at V out1 :
 
ω P1 =1/( r   0   C   m ),  (11)
 
a pole at V out :
 
ω P2 =1/( r   L   C   L ),  (12)
 
and a pole at V ga :
 
ω P3 =1/( r   1   C   g )  (13)
 
There is a zero located at zero frequency due to the AC coupling. Since A 1  is in inner loop  30 , the poles and zeros in driver amplifier  20  are also in inner loop  30 . We assume these poles are located at very high frequencies. Because inner loop  30  is AC coupled, it does not participate in any DC activity. The loop gain of inner loop  30  will go up with increasing frequency as a result of the AC-coupling zero. In the frequency range of pole P 1 , the gain becomes flat. The gain in this frequency range is:
 
 A′   0   =A   1   g   mL   r   L   (14)
 
Inner loop  30  starts to participate from this point, in the sense that the pole at frequency ω P2  is a dominant pole of inner loop  30 . The maximum gain of the inner loop is A′ 0 , which can be reached if pole frequencies ω P1  and ω P2  are sufficiently separated. The gain bandwidth product is:
 
ω′ t   =A   1   g   mL   /C   L   (15)
 
Eq. (15) indicates that the gain bandwidth product of inner loop  30  is the second pole of outer loop  24 . Higher A 1  and g mL , and lower C L  make inner loop  30  more difficult to stabilize.
 
   From the analysis of standard Miller compensation, it is known that to make voltage regulators  10  or  10 A stable, it is necessary for gain A 1  to be high and/or the value of g mL  large. At the same time, it is necessary to push the gate pole of transistor  14  to a high frequency, to make the output impedance of driver amplifier  20  low enough. However, it is difficult to design a high gain, low impedance driver amplifier  20  with low power consumption. 
   Ahuja compensation can be used to increase the stability of inner loop  30 . This stability is achieved by pushing the load pole to a higher frequency by the ratio of capacitive gain C a /C p , keeping the other pole positions in outer loop  24  unchanged. 
   Referring now to  FIG. 3 , there is a dominant pole at V out1  at a frequency:
 
ω P1 =1/( r   0   A   1   g   mL   r   L   C   a )  (16)
 
There is a second pole at V out  at a frequency:
 
ω P2 =( C   a   /C   p )* A   1   g   mL   /C   L   (17)
 
There is also a third pole at V ga  at a frequency:
 
ω P3 =1/( r   1   C   g )  (18)
 
Ahuja compensation introduces a zero-pole pair, each canceling the other:
 
ω Za , ω Pa   =g   ma   /C   a   (19)
 
If the high frequency poles and zeros in driver amplifier  20  are ignored, the transfer function of voltage regulator  10 B is written:
 
 A   v ( s )= A   0 /[(1+ s/ω   P1 )(1+ s/ω   P2 )(1+ s/ω   P3 )]  (20)
 
   Similarly to Miller compensation, the third pole due to pass device gate capacitor C g  can be pushed to relatively high frequency. The outer loop gain bandwidth is written:
 
ω t   =g   m0   /C   a   (21)
 
   The gain bandwidth obtained using Ahuja compensation is the same as that obtained using Miller compensation, but the second pole in Ahuja compensation is larger by the ratio of (C a /C p ). Therefore for the same phase margin, the required gain A 1  of driver amplifier  20  can be reduced. 
   One might hope that the reduction in A 1  by capacitive gain would make the design of driver amplifier  20  easier. However, the effects of C a  and C p  on inner loop  30  stability must be taken into account. Referring to a simplified circuit  32  shown in  FIG. 4 , the transfer function from V IN  to V OUT  can be written:
 
 V   OUT   /V   IN   =g   ma   sC   a /[( sC   a   +g   ma   +g   dw )( sC   p   +g   up )]  (22)
 
   There are two poles and one zero in this circuit. The zero is located at DC because of AC coupling. One pole is formed by C P  and r up , and the other pole is introduced by Ahuja compensation. In the present case, g ma &gt;&gt;g dw  and g up . From eq. (22), it is apparent that the gain of the circuit represented in  FIG. 4  will keep increasing with frequency up to the frequency range of the pole formed by C p  and r up . Thus C p  cannot be made too small, otherwise the gain will be too large, making the loop more difficult to stabilize. If, in a frequency range of interest, SC p &gt;&gt;g up , then eq. (22) can be reduced to:
 
 V   OUT   /V   IN =( C   a   /C   p )* g   ma /( sC   a   +g   ma )  (23)
 
The same amount of capacitive gain, (C a /C p ), appears in inner loop  30 . Thus, in agreement with the Miller compensation case, the gain bandwidth product of the inner loop is the same as the second pole location of the outer loop. Ahuja compensation creates a new pole in inner loop  30 . The new pole is located at:
 
ω a   =g   ma   /C   a   (24)
 
   In addition to the load pole and the gate  16  pole of transistor  14 , inner loop  30  is a three-pole system. Normally the frequency position of the pole ω a  is below that of the gate  16  pole of transistor  14 . To have a stable circuit  10 B, this pole must either by moved to a higher frequency or be canceled by a zero. To move this pole to a much higher frequency, for example, in the range of 10 to 100 MHz, g ma  might be made very large. Although making g ma  larger does, in fact, work in this regard, this approach requires both additional circuits and more power to operate the additional circuits. 
   In summary, inner loop  30  has a pole at V out1  at frequency:
 
ω P1 =1/( r   0   C   p ),  (25)
 
a pole at V out :
 
ω P2 =1/( r   L   C   L ),  (26)
 
a pole at V a :
 
ω P3   =g   ma   /C   a ,   (27)
 
and a pole at V ga :
 
ω P4 =1/( r   1   C   g ).  (28)
 
   As in the Miller compensation case, AC coupling capacitor C a  introduces a zero at zero frequency. There are also poles and zeros in driver amplifier  20  that should be placed at very high frequencies. To make inner loop  30  stable, parasitic capacitance C p  cannot be very small, as it is used to cancel the AC-coupling zero. If C p  is small, inner loop  30  will have high gain in the frequency range of the P 1  pole. For a given pole P 2  position, the P 4  pole has to be placed at a higher frequency, thus making the design of driver amplifier  20  considerably more difficult. Inner loop  30  will be unstable even for relatively small capacitive gain (C a /C p ) due to the existence of the third pole P 3 . 
   SUMMARY OF THE INVENTION 
   A voltage regulator apparatus includes an error amplifier that amplifies a voltage difference between a reference and a sampled output voltage of the voltage regulator apparatus. A driver amplifier has an input that is responsive to the amplified voltage difference to produce a gate driving voltage at its output. An output transistor has a drain, a gate, and a source. The gate is responsive to the gate driving voltage to produce a regulated output voltage at the source of the output transistor. To stabilize the voltage regulator apparatus, a Miller compensation capacitor feeds the regulated output voltage back to the input of the driver amplifier. An Ahuja compensation circuit feeds the regulated output voltage back to the input of the driver amplifier. 
   Circuit component values are selected so that a zero resulting from the Miller compensation capacitor at least partially cancels a pole resulting from the Ahuja compensation. 
   In other configurations, a voltage regulator has an outer loop and an inner loop. The outer loop includes an error amplifier having an output that communicates with an input of a driver amplifier and a regulated voltage output that communicates with an output of the driver amplifier. The outer loop further includes an outer feedback path from the regulated voltage output to an input of the error amplifier that maintains the regulated voltage output in accordance with a reference voltage. The voltage regulator also includes an inner loop. The inner loop includes a first feedback path and a second feedback path around the driver amplifier. In the inner loop, a zero produced by the first feedback path at least partially cancels a pole produced by the second feedback path. Also, in some configurations, the first feedback path includes a Miller compensation capacitor and the second feedback path includes an Ahuja compensation circuit. 
   Yet other configurations provide a method for regulating voltage. The method includes comparing a sampled DC voltage to a reference voltage to generate a correction signal, amplifying the correction signal utilizing a driver amplifier, and controlling a gate voltage of a pass transistor utilizing the amplified correction signal to generate a regulated output voltage. The sampled DC voltage is related to the regulated output voltage. The method also includes feeding back a first portion of the regulated output voltage to the driver amplifier utilizing a Miller compensation capacitor and feeding back a second portion of the regulated output voltage to the driver amplifier utilizing an Ahuja compensation circuit. 
   The interaction of poles and zeros provided by the combination of two feedback paths in a single voltage regulator voltage regulator advantageously simplifies the design of the voltage regulator, at least in part by easing driver amplifier requirements for high gain, low impedance and low power consumption. More particularly, in some configurations, at least one zero introduced by one of the feedback paths is used to cancel a pole introduced by the other to increase stability of the voltage regulator. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1  is a schematic diagram of a prior art low drop-out (LDO) voltage regulator; 
       FIG. 2  is a schematic diagram of a prior art LDO voltage regulator utilizing Miller compensation; 
       FIG. 3  is a schematic diagram of a prior art LDO voltage regulator utilizing Ahuja compensation; 
       FIG. 4  is a schematic diagram of a simplified circuit for the inner loop analysis of Ahuja compensation; 
       FIG. 5  is a schematic diagram representative of LDO voltage regulator configurations of the present invention incorporating both Miller compensation and Ahuja compensation; 
       FIG. 6  is a schematic diagram of a simplified circuit for the inner loop analysis of combined Miller and Ahuja compensation; and 
       FIG. 7  is a schematic diagram representative of various configurations of driver amplifier suitable for use as the driver amplifier in some configurations of LDO voltage regulators of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. 
   As used herein, “Miller effect” refers to the use of feedback capacitance to lower an input pole frequency. “Miller compensation” refers to a feedback topology in which a “Miller feedback capacitor” (or “Miller capacitor”) provides feedback to the input of an amplifier from a later stage, such as the output of the amplifier, or the output of the amplifier as further buffered and/or amplified. Miller compensation makes a system&#39;s open loop transfer function approximate simple first order dynamics over a wide range by creating a dominant pole. 
   As used herein, an “Ahuja compensation circuit” refers to a feedback topology that includes an “Ahuja feedback capacitor” (or “Ahuja capacitor”) providing feedback to the input of an amplifier from a later stage, such as the output of the amplifier or the output as further buffered and/or amplified. However, unlike Miller compensation, the Ahuja capacitor feeds back to a node joining a first current source and a source of a transistor. The input of the amplifier compensated by the Ahuja compensation circuit is at a node joining a drain of the transistor and a second current source. 
   Referring now to  FIG. 5 , to cancel the effect of the third pole P 3  in Ahuja compensation, both Ahuja and Miller compensation are used. A left half-plane (LHP) zero is created by this mixed frequency compensation. The LHP zero effectively cancels pole P 3  and compensates the phase of inner loop  30 . Miller compensation capacitor C m  and Ahuja compensation capacitor C a  are used for frequency compensation. Inner loop analysis shows that a LHP zero is created by this configuration, which tracks the pole introduced by Ahuja compensation. The net effect of this zero is to cancel the pole and compensate the phase. The values of C m , C a  and its ratio are selected in accordance with outer loop  24  and inner loop  30  stability requirements. 
   The dominant pole of the outer loop at V out1  is at a frequency:
 
ω P1 =1 /[r   0   A   1   g   mL   r   L ( C   a   +C   m )],  (29)
 
the second pole at V out  is at:
 
ω P2 =( C   a   /C   m )* A   1   g   mL   /C   L ,  (30)
 
and the third pole at V ga  is at:
 
ω P3 =1/( r   1   C   g ).  (31)
 
Ahuja compensation introduces a zero-pole pair in which the zero and pole cancel one another:
 
ω Za , ω Pa   =g   ma   /C   a .  (32)
 
Miller compensation introduces a zero at:
 
ω Zm   =−g   mL   /C   m .  (33)
 
   Outer loop  24  can be treated approximately as a two-pole system as in both the Miller compensation and Ahuja compensation cases. More specifically, ω Zm  and ω P3  are a high frequency zero and pole, respectively, so that their effects can be ignored in the analysis of outer loop  24 . The gain bandwidth product is given by:
 
ω t   =g   m0 /( C   a   +C   m ),  (34)
 
and the unity gain bandwidth is:
 
ω u   =g   m0  sin ( PM )/( C   a   +C   m )  (35)
 
Driver amplifier  20  gain A 1  can be obtained from an expression written:
 
( C   a   /C   m ) A   1   g   mL   /C   L   =g   m0  sin ( PM ) tan ( PM )/ C   m ,  (36)
 
where PM is a specified phase margin.
 
   To determine the stability of inner loop  24 , a simplified circuit  34  in  FIG. 6  is provided. The transfer function from V IN  to V OUT  can be written:
 
 V   OUT   /V   IN =[( s   2   C   a   C   m   +g   ma   sC   a +( g   ma   +g   dw ) sC   m ]/[( sC   a   +g   ma   +g   dw )( sC   m   +g   up )]  (37)
 
There are two poles and two zeros in this system. The transfer function can be simplified if g ma &gt;&gt;g dw :
 
 V   OUT   /V   IN =[( sC   a /( sC   m   +g   up )]*[ sC   m   +g   ma ( C   m   +C   a )/ C   a ]/( sC   a   +g   ma )  (38)
 
From eq. (38), the pole and zero frequencies are:
 
ω P1 =1/( r   up   C   m )  (39)
 
ω P2   =g   ma   /C   a   (40)
 
ω Z1 =0  (41)
 
ω Z2 =(1+ C   a   /C   m )* g   ma   /C   a   (42)
 
where ω Z2  is a left hand plane zero located at higher frequency than ω P2  by the factor of (1+C a /C m ). The maximum gain of the loop is (1+C a /C m ).
 
   The inner loop  30  pole at V out1  is found at:
 
ω P1 =1/( r   0   C   m ),  (43)
 
the pole at V out  is at:
 
ω P2 =1/( r   L   C   L ),  (44)
 
the pole at V a  is at:
 
ω P3   =g   ma   /C   a ,  (45)
 
and the pole at V ga  is at:
 
ω P4 =1/( r   1   C   g ).  (46)
 
There are also zeros at DC and at the frequency:
 
ω Z =(1+ C   a   /C   m )* g   ma   /C   a   (47)
 
   The LHP zero can partially cancel the pole at frequency ω P3  due to Ahuja compensation if these two are not far away from each other. The Ahuja capacitor and the Miller capacitor may be selected so that the LHP zero and the pole at ω P3  at least partially compensate one another. The LHP zero also compensates inner loop  30  phase, thus providing additional stability.
 
 A   0,max   =A   1   g   mL   r   L (1+ C   a   /C   m )  (48)
 
   The capacitive gain (1+C a /C m ) cannot be too large, otherwise it is difficult to make inner loop  30  stable. In some configurations, the ratio C a /C m  is less than about 3. The frequency response and phase margin are determined mainly by frequencies ω P2 , ω P3 , ω P4  and ω Z . For given load conditions, the ratio of C a  and C m , and A 1 , the output impedance of the driver amplifier can be estimated by the following equation:
 
 r   1 =( C   L   /A   1   g   mL   C   g )/(1+ C   a   /C   m )  (49)
 
   For example, consider a configuration in which I load =0 μA and I dc =100 μA, as this is the worst case configuration for stability of outer loop  24 . For this configuration, choose C L =20 μF, C a =20 pF, C m =8 pF and C g =500 pF. Also, g m0 =1.2 μS and g mL =2.4 mS. Using eq. (36), the required A 1  of driver amplifier  20  for outer loop phase margin equal to 20° is:
 
 A   1 =( g   m0   /g   mL )*( C   L /( C   m   +C   a ))*( C   m   /C   a )*sin ( PM )*tan ( PM )=17.
 
The output impedance of driver amplifier  20  can be estimated using eq. (49). The value g mL =4.9 S is used for load current I load =800 mA case. Thus, r 1 =137 Ω.
 
   Equivalent series resistance (ESR) introduces a LHP zero at 1/(2 πr esr C L ). In some configurations, the ESR is in the range of few tens of mini-ohms. Some configurations of the present invention, however, handle ESRs up to 1 ohm. The ESR zero can improve the outer loop  24  phase margin. However the ESR zero also appears in inner loop  30 , where it expands the inner loop  30  bandwidth to higher frequency. The inner loop gain becomes flat in the frequency range of the ESR zero, and the next pole located at higher frequency brings it down. If driver amplifier  20  output impedance is very small, the gate  16  pole will be located at a relatively high frequency. Then loop bandwidth will be pushed to close to the parasitic poles of driver amplifier  20 . The inner loop  30  phase margin will become negative. Thus, ESR can result in stability problems for voltage regulator  100 . The output impedance of driver amplifier  20 , capacitive gain factor C a /C m , and inner loop  30  phase margin are functions of the ESR, and thus, these parameters should be selected in accordance with the process technology used and the required ESR range. 
   Referring now to  FIG. 7 , driver amplifier  20  may be a wide band amplifier, which provides a gain of about 18 along with low output impedance (about 100 to 200 Ω). A nested structure is used to lower the output impedance of amplifier  20 . The nested structure in some configurations includes four series-connected amplifiers  40 ,  42 ,  44 , and  46 . A feedback resistance R F1  is located between an output of the fourth amplifier  46  and an input of the second amplifier  42 . Another feedback resistance R F2  is located between an output of the third amplifier  44  and its input. The gain and output impedance of amplifier  20  are written:
 
 A   1   =g   m1   R   F1   (50)
 
and
 
 Z   out =1/( g   m2   R   F2   g   m4 ),  (51)
 
respectively. The gain and the output impedance of amplifier  20  can be changed separately and efficiently by selecting resistor values R F1 , R F2  and g m1 , g m2 , g m3 , and g m4 . However, these values cannot be made too large, otherwise the parasitic poles and zeros associated with these resistors go to low frequencies too close to the gate  16  pole. The output impedance selected should not be too low, as there has to be some amount of separation in frequency between gate  16  pole and parasitic poles to make voltage regulator  100  inner loop  30  stable in the presence of 1 Ω ESR.
 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.