Abstract:
An apparatus and method for processing input/output data in a communication system is disclosed. By adding a controller that adjusts timing intervals between a first buffer having a first timing interval and a second buffer having a second timing interval, buffer usage can be minimized.

Description:
PRIORITY  
       [0001]     This application claims priority under 35 U.S.C. § 119(a) to an application filed in the Korean Intellectual Property Office on Jan. 18, 2006 and assigned Serial No. 2006-5406, the contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention generally relates to an apparatus and method for processing input/output data in a communication system, and in particular, to a transport channel demultiplexer and a demultiplexing method for a Wideband Code Division Multiple Access (WCDMA) system.  
         [0004]     2. Description of the Related Art  
         [0005]     Generally, a Universal Mobile Telecommunications System (UMTS) transport channel demultiplexer performs column-permutation on data that has been written by a transmitter in a transport channel buffer in the row direction and then reads the column-permutated data in the column direction, whereby primary interleaving is automatically performed.  
         [0006]      FIG. 1  illustrates a general example of primary interleaving, i.e., column permutation in which columns of data that has been rate-matched by a transmitter are exchanged.  
         [0007]     In  FIG. 1 , a Transmission Timing Interval (TTI) is assumed to be 40 ms and the number of frames per TTI is defined as a parameter N_TTI that is assumed to be 4. After primary interleaving, data is output sequentially along a direction indicated by a ‘READ’ arrow as illustrated in  FIG. 1 . The output data per frame undergoes secondary interleaving and then is transmitted to a receiver. The receiver then performs secondary deinterleaving on frame data received every 10 ms while storing the deinterleaved frame data in a Radio Frequency (RF) buffer.  
         [0008]     Referring to  FIG. 1 , for the data that is transmitted to the receiver after the secondary interleaving, a first 10 ms frame includes data (0, 4, 8, 12, 16, 20, 24, 28), a second 10 ms frame includes data (2, 6, 10, 14, 18, 22, 26, 30), a third 10 ms frame includes data (1, 5, 9, 13, 17, 21, 25, 29), and a fourth 10 ms frame includes data (3, 7, 11, 15, 19, 23, 27, 31). Thus, these 10 ms frames are by turns stored in and output from the RF buffer of the receiver, which is configured as a double buffer.  
         [0009]      FIG. 2  is a block diagram of a general transport channel demultiplexer of the receiver.  
         [0010]     As illustrated in  FIG. 2 , in the receiver, data stored in an RF buffer  210  is sequentially read and then written in a position corresponding to an address generated by a write address generator  251  of a second buffer controller  250  in a transport channel buffer  220  in the column direction. To this end, the write address generator  251  of the second buffer controller  250  generates an address that is incremented by N_TTI=4 at a time. A read address generator  252  of the second buffer controller  250  sequentially increments a read address after completion of the write operation, whereby primary deinterleaving is finished.  
         [0011]     A rate dematching process in the receiver may be classified into no rate control, zero insertion for convolutionally coded data, zero insertion for turbo coded data, and reduction.  
         [0012]     For convenience of explanation, zero insertion for convolutionally coded data and reduction will be described.  
         [0013]     Data that has been punctured in the transmitter is adjusted by zero insertion. Reduction involves combining data that has been repeated during rate matching of the transmitter.  
         [0014]     More specifically, data of the transport channel buffer  220  illustrated in  FIG. 2  is sequentially read, and a rate dematching algorithm is executed for each read data in order to cause an E_val calculator  261  of rate dematcher  260  to calculate a parameter E_val used for zero insertion or data combining through multiplexer  280 . In zero insertion and reduction, the read address generator  252  of the second buffer controller  250  and a write address generator  271  of a third buffer controller  270  operate based on E_val calculated by the E_val calculator  261 .  
         [0015]     In zero insertion, for E_val&gt;0, the read data is written in a position corresponding to a write address of a decoding input buffer  230  and the write address of the decoding input buffer  230  and a read address of the transport channel buffer  220  are incremented, while for E&lt;=0, ‘0’ is written in the position corresponding to the write address of the decoding input buffer  230  and then the write address of the decoding input buffer  230  is incremented.  
         [0016]     In reduction, for E_val&gt;0, the read data is written in the position corresponding to the write address of the decoding input buffer  230  and the write address of the decoding input buffer  230  and the read address of the transport channel buffer  220  are incremented, while for E_val&lt;=0, the read address of the transport channel buffer  220  is incremented and then data combining is performed in the position corresponding to the write address of the decoding input buffer  230 .  
         [0017]      FIG. 3  is a timing diagram for primary deinterleaving, rate dematching, and decoding for a single transport channel having TTI=40 ms.  
         [0018]     As illustrated in  FIG. 3 , for a single transport channel having TTI=40 ms, primary deinterleaving is performed every 10 ms and rate dematching and decoding are performed every TTI.  
         [0019]     As discussed above, in the general transport channel demultiplexer of the receiver, since primary deinterleaving is performed every 10 ms and rate dematching and decoding are performed every TTI, a transport channel buffer is required for storing data that undergoes primary deinterleaving. The size of the transport channel buffer used to store the data is about 0.2 million gate count, increasing an area and power consumption.  
       SUMMARY OF THE INVENTION  
       [0020]     An object of the present invention is to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an object of the present invention is to provide an apparatus and method for controlling data input/output operations by adding a simple controller between two buffers having different timing intervals.  
         [0021]     Another object of the present invention is to provide a demultiplexer and a demultiplexing method, in which primary deinterleaving and rate dematching are performed at the same time by adding a controller between two buffers having different timing intervals.  
         [0022]     According to one aspect of the present invention, there is provided a transport channel demultiplexer for a Wideband Code Division Multiple Access (WCDMA) system. The transport channel demultiplexer includes a Radio Frequency (RF) buffer for storing radio frame data that is transmitted every first timing interval, a rate dematching processor for performing rate dematching with respect to output data of the RF buffer, a decoding input buffer whose output terminal is connected to an input terminal of a decoder and for deinterleaving and then storing data that is processed by the rate dematching processor and then input every second timing interval that is greater by an integer multiple than the first timing interval and outputting the stored data to the decoder, and a controller for defining a counter according to the second timing interval and detecting data every first timing interval and then transmitting the detected data to the rate dematching processor.  
         [0023]     According to another aspect of the present invention, there is provided a demultiplexing method of a transport channel demultiplexer for a Wideband Code Division Multiple Access (WCDMA) system. The demultiplexing method includes storing radio frame data that is transmitted every first timing interval after performing secondary deinterleaving with respect to the radio frame data, performing rate dematching with respect to the stored radio frame data, receiving the rate-dematched radio frame data every second timing interval that is greater by an integer multiple than the first timing interval, performing primary deinterleaving with respect to the received radio frame data, and storing the primary-deinterleaved radio frame data, and outputting the primary-deinterleaved radio frame data to a decoder. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]     The above and other features and advantages of an exemplary embodiment of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0025]      FIG. 1  illustrates general column permutation with respect to data that has been rate-matched by a transmitter;  
         [0026]      FIG. 2  is a block diagram of a general transport channel demultiplexer of a receiver;  
         [0027]      FIG. 3  is a timing diagram for primary deinterleaving, rate dematching, and decoding for a single transport channel having TTI=40 ms;  
         [0028]      FIG. 4  is a block diagram of a transport channel demultiplexer of a receiver according to the present invention;  
         [0029]      FIG. 5  is a timing diagram for primary deinterleaving, rate dematching, and decoding according to of the present invention;  
         [0030]      FIG. 6  is a timing diagram for zero insertion in case of TTI=40 ms according to the present invention;  
         [0031]      FIG. 7  is a flowchart illustrating zero insertion according to the present invention;  
         [0032]      FIG. 8  is a timing diagram illustrating an operation for TTI=40 ms and a first radio frame according to the present invention;  
         [0033]      FIG. 9  is a flowchart illustrating an operation for TTI=40 ms and a first radio frame according to the present invention;  
         [0034]      FIG. 10  is a timing diagram illustrating an operation for TTI=40 ms and a radio frame following a first radio frame according to the present invention;  
         [0035]      FIG. 11  is a flowchart illustrating an operation for TTI=40 ms and a radio frame following a first radio frame according to the present invention;  
         [0036]      FIG. 12  is a timing diagram illustrating an operation for TTI=10 ms according to the present invention; and  
         [0037]      FIG. 13  is a flowchart illustrating an operation for TTI=10 ms according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0038]     The following detailed construction and elements are provided to assist in a comprehensive understanding of the invention. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiment described herein can be made without departing from the scope and spirit of the invention. Also, descriptions of well-known functions and constructions are omitted for clarity and conciseness and like reference numerals refer to like features throughout the specification.  
         [0039]      FIG. 4  is a block diagram of a transport channel demultiplexer of a receiver for efficient buffer usage according to the present invention.  
         [0040]     As illustrated in  FIG. 4 , the transport channel demultiplexer includes a Radio Frequency (RF) buffer  410 , a decoding input buffer  430 , a first buffer controller  440 , a rate dematcher  460 , a second buffer controller  470 , a multiplexer  480 , and a controller  490 .  
         [0041]     The RF buffer  410  stores radio frame data. The multiplexer  480  inserts a zero into data that is output from the RF buffer  410 , combines data, or stores the output data of the RF buffer  410  in the decoding input buffer  430  according to the control of the rate dematcher  460 . The decoding input buffer  430  performs primary deinterleaving and rate dematching with respect to input data and stores the resulting data.  
         [0042]     The rate dematcher  460  executes a rate dematching algorithm and includes an E_val calculator  461  for calculating E_val. E_val is a parameter for generating a rate dematching pattern used for a general rate dematching algorithm. The controller  490  includes a TTI counter  491  that increments a count separately for each TTI and a frame detector  492  that detects frame data. A Prev_E_val calculator  462  is connected between the controller  490  and the rate dematcher  460  in order to calculate Prev_E_val by delaying E_val by 1 clock.  
         [0043]     The first buffer controller  440  includes a write address generator  441  that generates a write address for secondary deinterleaving and a read address generator  442  that generates a read address of the RF buffer  410  using the output value of the TTI counter  491 . Similarly, the second buffer controller  470  includes a write address generator  471  and a read address generator  472 . The write address generator  471  generates a write address of the decoding input buffer  430  according to E_val generated by the rate dematching algorithm.  
         [0044]     Conventionally, as illustrated in  FIGS. 2 and 3 , data is primary-deinterleaved every 10 ms and then stored in a transport channel buffer, and the stored data is rate-dematched every TTI and then stored in a decoding input buffer. However, in the present invention, data stored in the RF buffer  410  undergoes primary deinterleaving and rate dematching at the same time every 10 ms and then is stored in the decoding input buffer  430 .  FIG. 5  is a timing diagram for primary deinterleaving, rate dematching, and decoding according to the present invention.  
         [0045]     Hereinafter, primary deinterleaving and rate dematching according to the present invention will be described in detail with reference to the drawings. Separate descriptions will be made regarding a case where primary deinterleaving and zero insertion are performed and a case where primary deinterleaving and data combining are performed.  
         [0046]      FIG. 6  is a timing diagram for zero insertion in case of TTI=40 ms according to the present invention.  
         [0047]     As illustrated in  FIG. 6 , an output value CNT of the TTI counter 491 illustrated in  FIG. 4  is output every clock CLK. When E_val generated by the rate dematching algorithm is greater than 0, ‘0’, ‘3’, ‘2’, and ‘1’ are repetitively output as CNT. When E_val generated by the rate dematching algorithm is less than or equal to 0, an immediately previous value is maintained. A read address R_ADDR generated by the read address generator  442  of the first buffer controller  440  is incremented each time CNT=0. A write address W_ADDR generated by the write address generator  471  of the second buffer controller  470  is incremented every clock.  
         [0048]     As mentioned previously, the write address is incremented every clock, but a write signal WRITE indicating the execution of a write operation in the decoding input buffer  430  is enabled only when CNT=0 or E_val&lt;=0, i.e., E_val=0.  
         [0049]      FIG. 7  is a flowchart illustrating zero insertion in case of TTI=40 ms according to the present invention.  
         [0050]     As illustrated in  FIG. 7 , in zero insertion, E_val is calculated after CNT is set to 0 in step S 701 . In step S 702 , E_val is checked. For E_val&gt;0, CNT is checked in step S 703 . For CNT&gt;0, the write address is incremented and the write signal is set to 0 in step S 704 . In case of CNT&lt;=0, data that has been read from the RF buffer  410  is written in the decoding input buffer  430  after the write address and the read address are incremented and the write signal is set to 1, in step S 705 .  
         [0051]     If E_val&lt;=0 in step S 702 , CNT&gt;0 at all times and thus CNT does not need to be checked. In step S 706 , 0 is written in the decoding input buffer  430  after the write address is incremented and the write signal is set to 1.  
         [0052]     It is checked if there is no data input to the RF buffer  410  in step S 707 . If there is no input data, zero insertion is terminated. If there is input data, it is checked if CNT=0 in step S 708 . CNT is reset to 3 in step S 710  in case of CNT=0 and CNT is decremented by 1 in step S 709  in case of CNT≠0, and then the process returns to step S 701 .  
         [0053]     Zero insertion described above can be arranged in the form of a table as shown below.  
                                                             TABLE 1                       E_val   CNT   R_ADDR   W_ADDR   Write   Write operation                                &gt;0   &gt;0   +0   ++   0   No operation       &gt;0   =0   ++   ++   1   Read data-write                           operation       &lt;=0   &gt;0   +0   ++   1   Zero insertion       &lt;=0   =0   Not Avail.   Not Avail.   Not Avail.   X                  
 
         [0054]     Next, a case where primary deinterleaving and data combining are performed will be described in detail. For convenience of explanation, data combining will be described for TTI=40 ms, like in zero insertion.  
         [0055]     Data combining according to the present invention may differ with a case where TTI&gt;10 ms, e.g., TTI=20 ms, 40 ms, or 80 ms, and the current frame is a first radio frame, a case where TTI&gt;10 ms, e.g., TTI=20 ms, 40 ms, or 80 ms, and the current frame is not the first radio frame, and a case where TTI=10 ms, i.e., one physical radio frame exists in one TTI.  
         [0056]     Thus, prior to data combining, the frame detector  492  of  FIG. 4  determines whether the current frame is a first radio frame and there is one radio frame per TTI.  
         [0057]      FIG. 8  is a timing diagram illustrating an operation for TTI=40 ms and a first radio frame according to the present invention.  
         [0058]     As illustrated in  FIG. 8 , in the first radio frame, the write signal WRITE is set to 1 when the output value CNT of the TTI counter  491  is 0 or the output value E_val of the rate dematcher  460  is less than 0. At this time, the controller  490  performs a control operation in such a way to not only read data of the radio frame and write the read data in the decoding input buffer  430  but also to previously write ‘0’ in a position in which data combining is to be performed to prevent data combining with garbage data.  
         [0059]      FIG. 9  is a flowchart illustrating an operation for TTI=40 ms and a first radio frame according to the present invention.  
         [0060]     As illustrated in  FIG. 9 , E_val is calculated, Pre_E_val is set to the same value as the calculated E_val, and CNT is set to 0 in step S 901 . It is checked if TTI=10 ms in step S 902 . If so, the process goes to step (b) to be described later. If not, it is checked if the current data is first frame data in step S 903 . If not, the process goes to step (a) to be described later. If the current data is first frame data, E_val is checked in step S 904 . For E_val&gt;0, CNT is checked in step S 906 . In case of CNT&gt;0, the write address is incremented, the write signal is set to 0, and no write operation is performed in step S 907 . For CNT&lt;=0, the read address and the write address are incremented, the write signal is set to 1, and the read data is written in step S 908 .  
         [0061]     If E_val&lt;=0 in step S 904 , CNT is checked in step S 905 . For CNT&gt;0, the write signal is set to 1 and ‘0’ is written in step S 909 . For CNT&lt;=0, the read address is incremented, the write signal is set to 1, and read data is written in step S 910 .  
         [0062]     Next, it is checked if there is no input data in step S 911 . If there is no input data, data combining is terminated. If there is input data, it is checked if CNT=0 in step S 912 . CNT is reset to 3 in case of CNT=0 in step S 913  and CNT is decremented by 1 in case of CNT≠0 in step S 914 , and then the process returns to step S 901 .  
         [0063]     The operation described above can be arranged in the form of a table as shown below.  
                                                                     TABLE 2                       Prev_E_val   E_val   CNT   R_ADDR   W_ADDR   Write   Write operation                                −   &gt;0   &gt;0   +0   ++   0   No operation       −   &gt;0   =0   ++   ++   1   Read data-write                               operation       −   &lt;=0   &gt;0   +0   +0   1   Zero insertion       −   &lt;=0   =0   ++   +0   1   Read data-write                               operation                  
 
         [0064]      FIG. 10  is a timing diagram illustrating an operation for TTI=40 ms and a radio frame following a first radio frame according to the present invention.  
         [0065]     As illustrated in  FIG. 10 , for radio frames following the first radio frame, the write signal WRITE indicating the execution of a write operation in the decoding input buffer  430  is set to 1 only when CNT=0. In addition, for the radio frames following the first radio frame, the controller  490  illustrated in  FIG. 4  operates based on Prev_E_val as well as E_val. In other words, the controller  490  enables data combining when any one of E_val and Prev_E_val is less than 0. For other cases, the controller  490  performs a control operation in such a way to store data read from the RF buffer  410  in the decoding input buffer  430 .  
         [0066]      FIG. 11  is a flowchart illustrating an operation for TTI=40 ms and a radio frame following a first radio frame according to the present invention.  
         [0067]     As illustrated in  FIG. 11 , TTI is checked and it is checked if the current frame is a first radio frame in steps S 901  through S 903  of  FIG. 9 . If the current frame is not the first radio frame in step S 903 , Prev_E_val is checked in step S 1101 . For Prev_E_val&gt;0, E_val is checked in step S 1102 . For E_val&gt;0, CNT is checked in step S 1105 . In case of CNT&gt;0, the write address is incremented, the write signal is set to 0, and no write operation is performed in step S 1107 . In case of CNT&lt;=0, the read address and the write address are incremented, the write signal is set to 1, and read data is written in step S 1108 .  
         [0068]     If E_val&lt;=0 in step S 1102 , CNT is checked in step S 1103 . For CNT&gt;0, the write signal is set to 0 and no write operation is performed in step S 1109 . For CNT&lt;=0, the read address is incremented, the write signal is set to 1, and the read data is combined with previous data that is stored in the RF buffer  410  immediately before the read data, i.e., data combining is performed, in step S 1110 .  
         [0069]     If Prev_E_val&lt;=0 in step S 1101 , E_val is checked in step S 1104 . For E_val&gt;0, CNT is checked in step S 1106 . For CNT&gt;0, the write address is incremented, the write signal is set to 0, and no write operation is performed in step S 1111 . For CNT&lt;=0, the read address and the write address are incremented, the write signal is set to 1, and data combining is performed in step S 1112 . If E_val&lt;=0 in step S 1104 , no operation is performed.  
         [0070]     Thereafter, the process goes to step S 911  of  FIG. 9 .  
         [0071]     The operation discussed above can be arranged in the form of a table as shown below.  
                                                                     TABLE 3                       Prev_E_val   E_val   CNT   R_ADDR   W_ADDR   Write   Write operation                                &gt;0   &gt;0   &gt;0   +0   ++   0   No operation       &lt;=0   &gt;0   &gt;0   +0   ++   0   No operation       &gt;0   &lt;=0   &gt;0   +0   +0   0   No operation       &gt;0   &gt;0   =0   ++   ++   1   Read data-write                               operation       &lt;=0   &gt;0   =0   ++   ++   1   Data combining       &gt;0   &lt;=0   =0   ++   +0   1   Data combining                  
 
         [0072]      FIG. 12  is a timing diagram illustrating an operation for TTI=10 ms according to the present invention.  
         [0073]     As illustrated in  FIG. 12 , in case of TTI=10 ms, the current frame is composed of a single radio frame and thus the transport channel demultiplexer according to the present invention operates similarly to a conventional transport channel demultiplexer including a transport channel buffer. In other words, for TTI=10 ms, the output value CNT of the TTI counter  491  included in the controller  490  of  FIG. 4  is 0 at all times and thus the write signal WRITE is 1 at all times. In this case, if Prev_E_val&lt;0, the controller  490  performs a control operation in such a way to combine the read data with previous data that is stored in the RF buffer  410  immediately before the read data.  
         [0074]      FIG. 13  is a flowchart illustrating an operation for TTI=10 ms according to the present invention.  
         [0075]     As illustrated in  FIG. 13 , steps S 901  and S 902  of  FIG. 9  are performed and if TTI=10 ms in step S 902 , E_val is checked in step S 1301 . For E_val&gt;0, Prev_E_val is checked in step S 1302 . For Prev_E_val&gt;0, the read address and the write address are incremented, the write signal is set to 1, and read data is written in step S 1303 . For Prev_E_val&lt;=0, the read address and the write address are incremented, the write signal is set to 1, and data combining is performed in step S 1304 .  
         [0076]     If E_val&lt;=0 in step S 1301 , the read address is incremented, the write signal is set to 1, and read data is written in step S 1305 .  
         [0077]     Next, it is checked if there is no input data in step S 1306 . If there is no input data, data combining is terminated. If there is input data, the process goes back to step S 901  of  FIG. 9 .  
         [0078]     The operation described above can be arranged in the form of a table as shown below.  
                                                                     TABLE 4                       Prev_E_val   E_val   CNT   R_ADDR   W_ADDR   Write   Write operation                                &gt;0   &gt;0   =0   ++   ++   1   Read data-write                               operation       &lt;=0   &gt;0   =0   ++   ++   1   Data combining       &gt;0   &lt;=0   =0   ++   +0   1   Read data-write                               operation                  
 
         [0079]     According to the present invention, when a control logic including a TTI counter, a frame detector, and the like is assumed to have a size of 50 thousand gate, about 150 thousand gate can be reduced when compared to an intuitive structure in hardware implementation. In other words, significant memory reduction can be achieved with a small increase in the size of the control logic. Furthermore, by reducing an area with memory reduction, power consumption can also be reduced in chip implementation.  
         [0080]     The above-described exemplary embodiment of the present invention can also be implemented by, without being limited to an apparatus and a method, a program for implementing functions corresponding to the present invention or a recording medium having the program recorded thereon. Such implementation can be easily construed as within the scope of the present invention by those skilled in the art to which the present invention pertains.  
         [0081]     While the present invention has been shown and described with reference to a certain exemplary embodiment of the present invention thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims and their equivalents.  
         [0082]     For example, although a demultiplexer for a WCDMA system is described in an exemplary embodiment of the present invention, the present invention can also be applied to an input/output data processor of a general communication system in a structure in which a controller is formed between two buffers having different transport timing intervals.