Abstract:
A semiconductor package which is improved in thinness and heat radiation and a method for making the same. The package includes a semiconductor chip electrically connected to leads of a leadframe via input and output bond pads. The leadframe may have a ground ring formed therein. The leads and semiconductor chip are at least partially encapsulated by an encapsulant. The semiconductor chip and leads have bottom surfaces which are externally exposed to improve heat radiation and reduce the thickness of the package. The package is made by placing the leadframe having leads onto adhesive tape, affixing a semiconductor chip into an open space on the leadframe, pressurizing the leadframe and chip downwardly for securement to the adhesive tape, electrically connecting input bond pads and output bond pads on the chip to the leads; at least partially encapsulating the leads and semiconductor chip; removing the tape from the bottom surfaces of the leads and chip; and cutting the leadframe to form the package. In an alternate embodiment, a chip paddle is connected to the leadframe and the semiconductor chip is secured to the chip paddle via an adhesive.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Technical Field of the Invention  
           [0002]    The present invention relates to a packaged semiconductor, a semiconductor package and a method for fabricating the package, and more particularly but not by way of limitation, to a thin semiconductor package having improvements in heat radiation and a method for manufacturing the same.  
           [0003]    2. History of Related Art  
           [0004]    It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal lead frames for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the lead frame are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.  
           [0005]    As set forth above, the semiconductor package therein described incorporates a lead frame as the central supporting structure of such a package. A portion of the lead frame completely surrounded by the plastic encapsulant is internal to the package. Portions of the lead frame extend internally from the package and are then used to connect the package externally. More information relative to lead frame technology may be found in Chapter 8 of the book  Micro Electronics Packaging Handbook,  (1989), edited by R. Tummala and E. Rymaszewski and incorporated by reference herein. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.  
           [0006]    Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.  
           [0007]    According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1×1 mm to 10×10 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLP type semiconductor packages are generally manufactured in the same manner.  
           [0008]    Such conventional semiconductor packages are not without problems. Specifically, a typical semiconductor package is difficult to make slim because the thickness of the internal leads is equivalent to the thickness of the chip paddle. Further, the mounting of the semiconductor chip on the chip paddle increases the overall thickness of the package. The thickness is increased because of the input/output pads on the semiconductor chip mounted on the chip paddle are positioned at a higher level than the internal leads, thereby increasing the loop height of the conductive wires. The increased height may contribute to wire sweeping, caused by the encapsulation material during encapsulation.  
           [0009]    In addition, mounting the semiconductor chip on a chip paddle having an externally exposed bottom surface has poorer heat radiation than having a direct externally exposed bottom surface of the semiconductor chip.  
           [0010]    Finally, after the chip-mounting step and wire-bonding step are performed, the semiconductor package is encapsulated only after the leadframe is positioned on a mold. Thus, although the leadframe is in close contact with the lower mold die, some encapsulation material infiltrates through the interface between the leadframe and the lower mold die, resulting in the formation of so-called “flash”. An extra de-flashing step must then generally be executed.  
         SUMMARY OF THE INVENTION  
         [0011]    In one embodiment of the present invention, there is provided a semiconductor package comprising a semiconductor chip having an upper surface and a bottom surface. A plurality of input bond pads and output bond pads on the upper surface of the semiconductor chip and along the circumference of the semiconductor chip are electrically connected to the semiconductor chip. A chip paddle may be provided which has a top surface, a side surface and a bottom surface. The chip paddle is bonded to the bottom surface of the semiconductor chip by an adhesive. The chip paddle has corners, a circumference and a half-etched section at the lower edge of the chip paddle along the chip paddle circumference.  
           [0012]    A lead frame is provided having a plurality of tie bars. Each of the tie bars has a side surface and a bottom surface. The plurality of tie bars are connected to the corners of the chip paddle. The plurality of the tie bars externally extend from the chip paddle and have a half-etched section. A plurality of dam bars are provided on the lead frame help limit flow of encapsulation material on the leadframe.  
           [0013]    A plurality of internal leads connect to the leadframe. Each of the leads has a side surface and a bottom surface. The leads are radially formed at regular intervals along and spaced apart from the circumference to the chip paddle and extend towards the chip paddle. Each of the leads has a step shaped half-etched section facing the chip paddle.  
           [0014]    A plurality of via conductive wires are electrically connected to and between the plurality of leads and the semiconductor chip. Encapsulating material encapsulates the semiconductor chip, conductive wires, chip paddle, and the leads to form a package body. The flow of the encapsulation material is limited by the dam bars formed on the leadframe. The dam bars also serve to stabilize the leads on the leadframe. After encapsulation, the chip paddle, leads, and tie bars are externally exposed at respective side and bottom surfaces.  
           [0015]    A ground ring may be provided on the leadframe having an upper surface and a lower surface. The conductive wires may be connected to the ground ring, which is exposed at the lower surface. The ground ring may further serve to function as a power ring. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    A more complete understanding of the method and apparatus of the present invention may be obtained by reference to the following detailed description when taken in conjunction with the accompanying Drawings wherein:  
         [0017]    [0017]FIG. 1A is a cross-section of a semiconductor package made in accordance with one embodiment of the present invention;  
         [0018]    [0018]FIG. 1B is a cross-section of the semiconductor package of FIG. 1A with a ground ring included in the package;  
         [0019]    [0019]FIG. 2A is a cross-section of an alternate embodiment of a semiconductor package made in accordance with the teachings of the present invention;  
         [0020]    [0020]FIG. 2B is a cross-section of the semiconductor package of FIG. 2A with a ground ring included in the package;  
         [0021]    [0021]FIG. 3 is a top plan view of a leadframe;  
         [0022]    FIGS.  4 - 9  are side-elevation cross-sections of a preferred embodiment of the semiconductor package of the present invention from the initial to final construction; and  
         [0023]    FIGS.  10 - 14  are side-elevation cross-sections of an alternate embodiment of the semiconductor package of the present invention from the initial to final construction. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]    Referring first to FIGS. 1A and 1B, there is shown a cross sectional illustration of one embodiment of a semiconductor package  10  construed in accordance with the principles of the present invention. The semiconductor package  10  includes a corner  12  and bottom surface  15 . The semiconductor package  10  further includes a semiconductor chip  20  having an upper surface  30 , a circumference  40  and a bottom surface  50 . A plurality of input bond pads  60  and output bond pads  70  are disposed on the upper surface  30  of the semiconductor chip  20 . Conductive wires  75 , including but not limited to gold or aluminum wires, electrically connect the semiconductor chip  20  to the respective input bond pads  60  or output bond pads  70 .  
         [0025]    In an alternate embodiment best seen in FIGS. 2A and 2B, a chip paddle  80  having a upper surface  90 , a side surface  100  and a bottom surface  110  is secured to the bottom surface  50  of the semiconductor chip  20  via an adhesive  120 . The chip paddle  80  has corners  130 , a circumference  140  and may include a half-etched section  150 . The half-etched section  150  is located at a lower edge  160  of the chip paddle  80 .  
         [0026]    Referring now to FIG. 3, a leadframe  170  is shown having a plurality of tie bars  180  and a side surface  190 . The tie bars  180  are connected to the corners  130  of the chip paddle  80  and externally extend from the chip paddle  80 . The leadframe  170  also includes a plurality of dam bars  220 .  
         [0027]    A plurality of leads  230  are connected to the leadframe  170  and have an upper surface  235 , a side surface  240  and a bottom surface  250 . In a first embodiment seen in FIGS. 1A and 1B, the leads  230  are radially formed at regular intervals along the semiconductor chip circumference  40  and spaced apart from the circumference  40  of the semiconductor chip  20 . The leads  230  extend towards the chip  20  and have a half-etched section  260  facing the chip  20 .  
         [0028]    In an alternate embodiment best seen in FIGS. 2A and 2B, the leads  230  are radially formed at regular intervals along the chip paddle circumference  140  and spaced apart from the circumference  140  of the chip paddle  80 . The leads  230  extend towards the chip paddle  80 , such that each of the plurality of leads  230  has a half-etched section  260  facing the chip paddle  80 .  
         [0029]    Referring back to FIGS. 1B and 2B, there is shown a ground ring  262  formed in package  10 . The ground ring  262  is positioned between the semiconductor chip  20  and the plurality of leads  230 , and may be interchangeably used as a power ring should circumstances require. Conductive wires  75  can connect the ground ring  262  to the respective input bond pads  60  or output bond pads  70 , depending on the application. As seen in FIG. 1B, the upper surface  264  of the ground ring  262  is planar with the upper surface  30  of the semiconductor chip  20  and the upper surface  235  of the leads  230 . However, as seen in FIG. 2B, the upper surface  264  of the ground ring  262  may be planar with the upper surface of the chip paddle  80  to minimize package thickness. Likewise, the upper surface  235  of the leads  230  is planar with the upper surface  30  of the semiconductor chip  20  (FIGS. 1A and 1B) to minimize package thickness. In the alternate embodiments shown in FIGS. 2A and 2B, the upper surface  235  of the leads  230  is planar with the upper surface  90  of the chip paddle  80  to reduce package thickness.  
         [0030]    Referring generally now to FIGS. 1A and 3, to enclose the semiconductor package  10 , encapsulation material  280  at least partially encapsulates the semiconductor chip  20 , conductive wires  70 , and leads  230 . In the alternate embodiment shown in FIGS. 2A and 2B, the encapsulation material  280  encapsulates the chip paddle  80  as well. Likewise, for the embodiments shown in FIGS. 1B and 2B, the encapsulation material  280  encapsulates the ground ring  262 .  
         [0031]    Referring now to FIGS. 1 through 3 in general, dam bars  220  limit the flow of the encapsulation material  280  on the leadframe  170  and provide stability to the leads  230  on the leadframe  170 . In the respective embodiment during encapsulation, the chip paddle  80 , leads  230 , and tie bars  180  may be externally exposed at peripheral side and bottom surfaces. The externally exposed portions of chip paddle  80 , leads  230 , and tie bars  180  may, but do no necessarily have to be, electroplated with corrosion-minimizing materials such as but not limited to, tin lead, tin, gold, nickel palladium, tin bismuth, or any other similar material known in the art. The respective half-etched sections  150 ,  260  of the chip paddle  80  and leads  230  are provided to increase the bonding strength of the encapsulation material  280  in the package  10 . It is contemplated that the respective half-etched sections  150 ,  260  may be eliminated without departing from the scope and spirit of this invention.  
         [0032]    Referring now to FIGS.  4 - 9  in general, there is shown a cross-section of the semiconductor package  10  of FIG. 1A. It is to be recognized that the method for constructing the semiconductor package  10  of FIG. 1A may be used for constructing the embodiment shown in FIG. 1B without departing from the principles of this invention. The leadframe, although not shown in these figures, having leads  230  and a space  290  large enough to accommodate a semiconductor chip  20 , is first placed upon an adhesive tape  300 . Next, a semiconductor chip  20  is fixed to the adhesive tape  300  within the space  290  as best seen in FIG. 5. The semiconductor chip  20  and the leads  230  are pressurized downwardly onto the tape  300  at a suitable temperature to make the tape  300  firmly adhere to the semiconductor chip  20  and leads  230 .  
         [0033]    As shown in FIG. 6, the input bond pads  60  and output bond pads  70  of the semiconductor chip  20  are next electrically connected to the leads  230  via conductive wires  75 . Upper surface  235  of leads  230  may, but do not necessarily have to be, electroplated with a material that enhances electrical conductivity such as, for example, gold or silver. Typically, the conductive wires  75  are connected via an automated process, but may be connected in any alternate method in the industry.  
         [0034]    The semiconductor chip  20 , conductive wires  75 , and leads  230  are then at least partially encapsulated with the encapsulation material  280 , which may be an epoxy molding compound or a liquid encapsulation material, thereby forming a package body  10  as seen in FIG. 7. Referring to FIG. 8, the adhesive tape  300  is next removed from the bottom surface  15  of the package  10 . The leads  230  are next severed from the leadframe (not shown) by cutting through the dam bars (not shown) or neighboring areas of the package body  10  best seen in FIG. 9 as a singulation step. It is to be noted that this singulation step may occur before the adhesive tape  300  is removed.  
         [0035]    After formation of the package body  10 , a marking process (not shown) may be carried out by the use of ink or lasers. The removal of the adhesive tape  300  allows the semiconductor chip  20  and leads  240  to be exposed to the outside, thereby improving heat radiation. By adhering the adhesive tape  250  to the bottom surfaces  15 ,  250  of the semiconductor chip  20  and leads  230 , respectively, flashes, which are typically formed during the molding process are not generated, thereby eliminating or reducing any further deflashing steps.  
         [0036]    After the removal of the adhesive tape  300 , a predetermined thickness of solder (not shown) may be plated over the bottom surface  250  of the of the leads  230  to allow easy fusion of the package  10  to a motherboard (not shown).  
         [0037]    Referring now generally to FIGS.  10 - 14 , there are shown cross-sections of the semiconductor package  10  of FIG. 2A during various stages of construction. It is to be recognized that the method for constructing the semiconductor package  10  of FIG. 2A may be used for constructing the embodiment shown in FIG. 2B without departing from the principles of this invention. The leadframe (not shown) having leads  230  and a chip paddle  80  is first placed upon an adhesive tape  300  best seen in FIG. 10. The chip paddle  80  and the leads  230  are pressurized downwardly onto the tape  300  at a suitable temperature to make the tape  300  firmly adhere to the chip paddle  80  and leads  230 .  
         [0038]    As shown in FIG. 11, the semiconductor chip  20  is bonded to the upper surface  90  of the chip paddle  80  via an adhesive  120 . The input pads  60  and output pads  70  of the semiconductor chip  20  are next electrically connected to the leads  230  via conductive wires  75 . Upper surfaces  235  of leads  230  may, but do not necessarily have to be, electroplated with a material that enhances electrical conductivity such as, for example, gold or silver. Typically, the conductive wires  75  are connected via an automated process, but may also be connected in any alternate method in the industry.  
         [0039]    The semiconductor chip  20 , chip paddle  80 , conductive wires  75 , and leads  230  are then at least partially encapsulated with the encapsulation material  280 , which may be thermoplastics or thermoset resins, with thermoset resins including, for example, silicones, phenolics, and epoxies. The encapsulation material  280  forms a package body  10  as seen in FIG. 12.  
         [0040]    Referring to FIG. 13, the adhesive tape  300  is next removed from the bottom surface  15  of the package  10 . The leads  230  are next severed from the leadframe (not shown) by cutting through the dam bars (not shown) or neighboring areas of the package body  10  best seen in FIG. 14 in a singulation step. It is noted that this singulation step may occur before the adhesive tape  300  is removed.  
         [0041]    Once the package body  10  is formed, a marking process (not shown) may be carried out by the use of ink or lasers. The removal of the adhesive tape  300  allows the chip paddle  80  and leads  230  to be exposed to the outside, thereby improving heat radiation. By adhering the adhesive tape  300  to the bottom surfaces  110 ,  250  of the chip paddle  80  and leads  230 , respectively, flashes, which are typically formed during the molding process, are not generated, thereby eliminating or reducing any further deflashing steps. Bottom surfaces  110 ,  250  of the chip paddle  80  and leads  230 , may be electroplated with corrosion-minimizing materials such as, but not limited to, tin lead, tin, gold, nickel palladium, tin bismuth, or other similar materials known in the art.  
         [0042]    After the removal of the tape  300 , a predetermined thickness of solder (not shown) may be plated over the bottom surface  250  of the of the leads  230  to allow easy fusion of the package  10  to a motherboard (not shown).  
         [0043]    In such a semiconductor package as described and shown in FIGS. 1A and 1B, the bottom surface  15  of the semiconductor chip  20  is in the same plane as the bottom surface  250  of the leads  230 , so that the semiconductor package  10  is thin by limiting the height level of the conductive wires  75 . In addition, the direct exposure of the semiconductor chip  20  provides for higher thermal radiation.  
         [0044]    The following applications are all being filed on the same date as the present application and all are incorporated by reference as if wholly rewritten entirely herein:  
                                       Attorney       First Named       Docket No.   Title of Application   Inventor                   45475-00014   Lead Frame for Semiconductor   Young Suk           Package and Mold for Molding the   Chung           Same       45475-00017   Method for Making a Semiconductor   Tae Heon Lee           Package Having Improved Defect           Testing and Increased Production   Yield       45475-00018   Near Chip Size Semiconductor   Sean Timothy           Package   Crowley       45475-00022   End Grind Array Semiconductor   Jae Hun Ku           Package       45475-00026   Leadframe and Semiconductor Package   Tae Heon Lee           with Improved Solder Joint Strength       45475-00027   Semiconductor Package Having   Tae Heon Lee           Reduced Thickness       45475-00029   Semiconductor Package Leadframe   Young Suk           Assembly and Method of Manufacture   Chung       45475-00030   Semiconductor Package and Method   Young Suk           Thereof   Chung                  
 
         [0045]    It is thus believed that the operation and construction of the present invention will be apparent from the foregoing description of the preferred exemplary embodiments. It will be obvious to a person of ordinary skill in the art that various changes and modifications may be made herein without departing from the spirit and the scope of the invention.