Abstract:
An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.

Description:
BACKGROUND  
       [0001]    One type of memory includes a controller and one or more memory devices communicatively coupled to the controller. The memory devices may include volatile memory devices and/or non-volatile memory (NVM) devices. The volatile memory devices may include random access memory (RAM) devices, such as dynamic random access memory (DRAM) devices, synchronous dynamic random access memory (SDRAM) devices, double data rate synchronous dynamic random access memory (DDR-SDRAM) devices, low power SDRAM (e.g., MOBILE-RAM) devices, or other suitable memory devices. The non-volatile memory devices may include RAM devices, such as flash memory devices, resistive memory devices (e.g., phase change memory devices, magnetic memory devices), or other suitable RAM devices. The non-volatile memory devices may also include read-only memory (ROM) devices, such as programmable read-only memory (PROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, or other suitable ROM devices. 
         [0002]    A memory including a controller and one or more memory devices may include a single data bus, which is shared between all the memory devices and coupled to the controller. The controller writes data to each of the memory devices and reads data from each of the memory devices through the shared data bus. 
         [0003]    A typical power-up sequence for the memory proceeds as follows. First, power is applied to the controller. With power applied to the controller, the controller starts to power-up the memory devices. After a short time, the controller supply voltage, such as V DD , becomes stable. A short time after the controller supply voltage stabilizes, the controller clock becomes stable. Then, after a set time from the stabilization of the controller clock, such as 200 μs, the controller can begin accessing the memory devices. The wait time between the controller clock stabilizing and the controller beginning to access the memory devices is provided to insure that all the memory devices have completed their power-up sequences. 
         [0004]    Typically, DRAM devices complete their power-up sequences earlier (e.g., at about 100 μs) than the controller wait time. In addition, the power-up sequences for non-volatile memory devices are typically less than for volatile memory devices (e.g., about 30 μs). 
         [0005]    For these and other reasons, there is a need for the present invention 
       SUMMARY  
       [0006]    One embodiment provides an integrated circuit. The integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0007]    The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
           [0008]      FIG. 1  is a block diagram illustrating one embodiment of a system. 
           [0009]      FIG. 2  is a timing diagram illustrating one embodiment of the timing of signals for a power-up sequence of the memory. 
           [0010]      FIG. 3  is a block diagram illustrating another embodiment of a memory. 
           [0011]      FIG. 4  is a schematic diagram illustrating one embodiment of a data mask signal input and output circuit within the controller. 
           [0012]      FIG. 5  is a timing diagram illustrating another embodiment of the timing of signals for a power-up sequence of the memory. 
       
    
    
     DETAILED DESCRIPTION  
       [0013]    In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “tailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
         [0014]      FIG. 1  is a block diagram illustrating one embodiment of a system  100 . System  100  includes a host  102  and a memory  106   a . Host  102  is electrically coupled to memory  106   a  through memory communications path  104 . Memory  106   a  includes a controller  108 , a data bus  110 , and memory devices  112   a - 112   c . Controller  108  is electrically coupled to memory devices  112   a - 112   c  through data bus  110 . In other embodiments, memory  106   a  includes any suitable number of memory devices  112 . 
         [0015]    During the power-up sequence for memory  106   a , controller  108  receives signals from memory devices  112   a - 112   c  indicating when each memory device  112   a - 112   c  has completed its power-up sequence. In one embodiment, once all memory devices  112   a - 112   c  have completed their power-up sequences, controller  108  may begin accessing each of the memory devices  112   a - 112   c . In another embodiment, in which one of the memory devices  112   a - 112   c  is a non-volatile memory device, once the non-volatile memory device has completed its power-up sequence, controller  108  may begin accessing the non-volatile memory device while the remaining memory devices are completing their power-up sequences. 
         [0016]    In one embodiment host  102  includes a computer (e.g., desktop, laptop, handheld), portable electronic device (e.g., cellular phone, personal digital assistant (PDA), MP3 player, video player) or any other suitable device that uses memory. Host  102  includes logic, firmware, and/or software for accessing memory  106   a . In one embodiment, host  102  includes a microcontroller, microprocessor, or other suitable device capable of passing a clock signal, address signal, command signals, and data signals to memory  106   a  through memory communication path  104 . Host  102  passes the clock signal, address signals, command signals, and data signals to memory  106   a  through memory communication path  104  to read data from and write data to memory  106   a.    
         [0017]    Memory  106   a  includes circuits for communicating with host  102  through memory communication path  104  and for reading and writing data in memory  106   a . Memory  106   a  responds to memory read requests from host  102  and passes the requested data to host  102 . Memory  106   a  responds to write requests from host  102  and stores data in memory  106   a  passed from host  102 . 
         [0018]    Controller  108  includes a microprocessor, microcontroller, or other suitable logic circuitry for controlling the operation of memory  106   a . Controller  108  controls read and write operations to memory devices  112   a - 112   c . Controller  108  receives data read from memory devices  112   a - 112   c  through data bus  110  and passes data to write to memory devices  112   a - 112   c  through data bus  110 . In one embodiment, data bus  110  includes eight data lines (DQ&lt; 0 : 7 &gt;). In other embodiments, data bus  110  includes any suitable number of data lines, such as 16, 32, or 64. 
         [0019]    Each memory device  112   a - 112   c  is a volatile memory device or a non-volatile memory (NVM) device. The volatile memory devices may include random access memory (RAM) devices, such as dynamic random access memory (DRAM) devices, synchronous dynamic random access memory (SDRAM) devices, double data rate synchronous dynamic random access memory (DDR-SDRAM) devices, low power SDRAM (e.g., MOBILE-RAM) devices, or other suitable memory devices. The non-volatile memory devices may include RAM devices, such as flash memory devices, resistive memory devices (e.g., phase change memory devices, magnetic memory devices), or other suitable RAM devices. The non-volatile memory devices may also include read-only memory (ROM) devices, such as programmable read-only memory (PROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, or other suitable ROM devices. 
         [0020]    In one embodiment, each memory device  112   a - 112   c  is assigned a data line of data bus  110  or another suitable signal line of the memory device on which each memory device  112   a - 112   c  outputs a “ready” or “not ready” signal. The “ready” signal is output by a memory device  12   a - 112   c  once the memory device has completed its power-up sequence. In one embodiment, memory device  112   a  is assigned to data line DQ&lt; 0 &gt;, memory device  112   b  is assigned to data line DQ&lt; 1 &gt;, and memory device  112   c  is assigned to data line DQ&lt; 2 &gt;. Data or signal lines of each memory device  112   a - 112   c  that are not assigned to output the “ready” or “not ready” signal for the memory device are not driven and are set to a high impedance to prevent shorts. 
         [0021]    Upon initialization of a power-up of memory  106   a , each memory device  112   a - 112   c  outputs a “not ready” signal on their assigned data or signal line. Once a memory device  112   a - 112   c  has completed its power-up sequence, the memory device  112   a - 112   c  outputs a “ready” signal on their assigned data or signal line. In one embodiment, the “ready” signal is a logic high signal and the “not ready” signal is a logic low signal. In another embodiment, the “ready” signal is a logic low signal and the “not ready” signal is a logic high signal. Once controller  108  receives a “ready” signal from each memory device  112   a - 112   c , controller  108  may begin accessing the memory devices  112   a - 112   c . Once controller  108  begins accessing the memory devices  112   a - 112   c , the data or signal lines assigned to each memory device  112   a - 112   c  for providing the “ready” or “not ready” signal revert to passing data or other signals between controller  108  and each memory device  112   a - 112   c.    
         [0022]      FIG. 2  is a timing diagram  120  illustrating one embodiment of the timing of signals for a power-up sequence of memory  106   a . Timing diagram  120  includes V DD  signal  122 , clock (CK) and inverted clock (bCK) signals  124  provided by controller  108 , command signal  126  provided by controller  108 , DQ&lt; 2 &gt; signal  128  assigned to memory device  112   c , DQ&lt; 1 &gt; signal  130  assigned to memory device  112   b , and DQ&lt; 0 &gt; signal  132  assigned to memory device  112   a.    
         [0023]    Host  102  initiates the power-up sequence of memory  106   a  at  134 . In response to initiating the power-up sequence, V DD  signal  122  begins to increase to its preset voltage. Once V DD  signal  122  reaches a specific voltage, such as two times the threshold voltage (V th ) as indicated at  136 , controller  108  initializes the power-up sequences of memory devices  112   a - 112   c . In response to initializing the power-up sequences of memory devices  112   a - 112   c , memory device  112   a  outputs a logic low DQ&lt; 0 &gt; signal  132  on the DQ&lt; 0 &gt; data line of data bus  110 , memory device  112   b  outputs a logic low DQ&lt; 1 &gt; signal  130  on the DQ&lt; 1 &gt; data line of data bus  110 , and memory device  112   c  outputs a logic low DQ&lt; 2 &gt; signal  128  on the DQ&lt; 2 &gt; data line of data bus  110 . The logic low DQ&lt; 0 &gt; signal  132 , the logic low DQ&lt; 1 &gt; signal  130 , and the logic low DQ&lt; 2 &gt; signal  128  indicate to controller  108  that memory devices  112   a - 112   c  have not completed their power-up sequences and are therefore “not ready.” At  138 , CK and bCK signals  124  are stabilized. With CK and bCK signals  124  stabilized and memory devices  112   a - 112   c  “not ready,” controller  108  does not issue any commands as indicated on command signal  126  at  140 . 
         [0024]    In response to memory device  112   a  completing its power-up sequence, memory device  112   a  transitions DQ&lt; 0 &gt; signal  132  from a logic low “not ready” to a logic high “ready” as indicated at  144 . In response to memory device  112   b  completing its power-up sequence, memory device  112   b  transitions DQ&lt; 1 &gt; signal  130  from a logic low “not ready” to a logic high “ready” as indicated at  142 . In response to memory device  112   c  completing its power-up sequence, memory device  112   c  transitions DQ&lt; 2 &gt; signal  128  from a logic low “not ready” to a logic high “ready” as indicated at  146 . 
         [0025]    In response to all memory devices  112   a - 112   c  providing “ready” signals, controller  108  determines that all memory devices  112   a - 112   c  have completed their power-up sequences. In response to controller  108  determining that all memory devices  112   a - 112   c  have completed their power-up sequences, controller  108  begins accessing memory devices  112   a - 112   c  as indicated at  148 . In one embodiment, where memory devices  112   a - 112   c  are DRAM devices, controller  108  begins accessing memory devices  112   a - 112   c  by issuing a precharge all (PCHA) command on command signal  126  at  150 . In one embodiment, the time as indicated at  139  between the CK and bCK signals  124  stabilizing and the precharge all command is less than 200 μs. 
         [0026]      FIG. 3  is a block diagram illustrating another embodiment of a memory  106   b . Memory  106   b  is similar to memory  106   a  previously described and illustrated with reference to  FIG. 1 , except memory  106   b  includes data mask (DM) line or signal path  114 . In addition, memory device  112   a  is a non-volatile memory device, such as a flash memory device, and memory devices  112   b  and.  112   c  are volatile memory devices, such as DRAM memory devices. 
         [0027]    Controller  108  is electrically coupled to non-volatile memory device  112   a  and DRAM memory devices  112   b  and  112   c  through data bus  110  and DM signal path  114 . Non-volatile memory device  112   a  has a shorter power-up sequence than DRAM memory devices  112   b  and  112   c . In one embodiment, non-volatile memory device  112   a  is assigned a data line of data bus  110  or another suitable signal line of the memory device on which memory device  112   a  outputs a “ready” or “not ready” signal. The “ready” signal is output by memory device  112   a  once memory device  112   a  has completed its power-up sequence. In one embodiment, memory device  112   a  is assigned to data line DQ&lt; 0 &gt;. In other embodiments, memory device  112   a  is assigned to another suitable data or signal line. In this embodiment, each DRAM memory device  112   b  and  112   c  outputs a “ready” or “not ready” signal on DM signal path  114 . The “ready” signal is output by a memory device  112   b  and I  12   c  once the memory device has completed its power-up sequence. 
         [0028]    Upon initialization of a power-up sequence of memory  106   b , non-volatile memory device  112   a  outputs a “not ready” signal on its assigned data or signal line and DRAM memory devices  112   b  and  112   c  each output a “not ready” signal on DM signal path  114 . Once memory device  112   a  has completed its power-up sequence, memory device  112   a  outputs a “ready” signal on its assigned data or signal line. In one embodiment, the “ready” signal is a logic high signal and the “not ready” signal is a logic low signal. In another embodiment, the “ready” signal is a logic low signal and the “not ready” signal is a logic high signal. Once controller  108  receives the “ready” signal from memory device  112   a , controller  108  may begin accessing memory device  112   a . Once controller  108  begins accessing memory device  112   a , the data or signal line assigned to memory device  112   a  for providing the “ready” signal reverts to passing data or other signals between controller  108  and each memory device  112   a - 112   c.    
         [0029]    Once a memory device  112   b  and  112   c  has completed its power-up sequence, the memory device outputs a “ready” signal on DM signal path  114 . The “ready” signal is provided by setting the DM output to a high impedance and the “not ready” signal is provided by setting the DM output to logic low. Once controller  108  receives a “ready” signal from both memory devices  112   b  and  112   c  (i.e., the DM outputs of both memory devices  112   b  and  112   c  are set to high impedance), controller  108  may begin accessing the memory devices  112   b  and  112   c . Once controller  108  begins accessing the memory devices  112   b  and  112   c , DM signal path  114  reverts to passing mask data between controller  108  and each memory device  112   a - 112   c.    
         [0030]      FIG. 4  is a schematic diagram illustrating one embodiment of a data mask signal input and output circuit  160  within controller  108 . Circuit  160  includes a power source  168 , a switch  170 , a resistor  172 , an output buffer  174 , and an input buffer  176 . Power source  168  is electrically coupled to one side of switch  170 . The control input of switch  170  receives a data mask termination (DM_term) signal on DM_term signal path  162 . The other side of switch  170  is electrically coupled to one side of resistor  172 . The other side of resistor  172  is electrically coupled to the output of output buffer  174  and the input of input buffer  176  through DM signal path  114 . The input of output buffer  174  receives a data mask output (DM_out) signal on DM_out signal path  164 . The output of input buffer  176  provides a data mask input (DM_in) signal on DM_in signal path  166 . 
         [0031]    In response to a logic high DM_term signal on DM_term signal path  162 , switch  170  is closed to electrically couple power source  168  to resistor  172 . In response to a logic low DM_term signal on DM_term signal path  162 , switch  170  is opened to electrically decouple power source  168  from resistor  172 . In another embodiment, the logic levels of the DM_term signal for opening and closing switch  170  are reversed. Buffer  174  buffers the DM_out signal on DM_out signal path  164  to provide the DM signal on DM signal path  114  during write operations. Buffer  176  buffers the signal on DM signal path  114  to provide the DM_in signal on DM_in signal path  166  during the power-up sequence of memory  106   b.    
         [0032]    During the power-up sequence of memory  106   b , controller  108  provides a signal on DM_term signal path  162  to close switch  170  such that power source  168  is coupled to resistor  172 . In response to at least one of DRAM memory devices  112   b  and  112   c  outputting a logic low “not ready” signal on DM signal path  114 , the DM_in signal on DM_in signal path  166  is logic low. In response to both DRAM memory devices  112   b  and  112   c  setting their DM outputs to a high impedance “ready,” DM signal path  114  is driven logic high through resistor  172  by power source  168 . Therefore, the DM_in signal on DM_in signal path  166  is logic high. 
         [0033]    In response to a logic high DM_in signal on DM_in signal path  166 , controller  108  provides a signal on DM_term signal path  162  to open switch  170  to disconnect power supply  168  from resistor  172 . Also in response to a logic high DM_in signal on DM_in signal path  166 , controller  108  begins accessing DRAM memory devices  112   b  and  112   c . During write operations, controller  108  may provide data mask signals on DM_out signal path  164  to pass to memory devices  112   a - 112   c  through DM signal path  114 . 
         [0034]      FIG. 5  is a timing diagram  180  illustrating one embodiment of the timing of signals for a power-up sequence of memory  106   b . Timing diagram  180  includes V DD  signal  122 , CK and bCK signals  124  provided by controller  108 , command signal  126  provided by controller  108 , DM signal  182  on DM signal path  114 , and DQ&lt;x&gt; signal  184  assigned to memory device  112   a , where “x” is one of the data lines of data bus  110 . 
         [0035]    Host  102  initiates the power-up sequence of memory  106   a  at  134 . In response to initiating the power-up sequence, V DD  signal  122  begins to increase to its preset voltage. Once V DD  signal  122  reaches a specific voltage, such as two times the threshold voltage (V th ) as indicated at  136 , controller  108  initializes the power-up sequences of memory devices  112   a - 112   c . In response to initializing the power-up sequences of memory devices  112   a - 112   c , memory device  112   a  outputs a logic low DQ&lt;x&gt; signal  184  on the DQ&lt;x&gt; data line of data bus  110 , memory device  112   b  outputs a logic low DM signal  182  on DM signal path  114 , and memory device  112   c  outputs a logic low DM signal  182  on. DM signal path  114 . The logic low DQ&lt;x&gt; signal  184  and the logic low DM signal  182  indicate to controller  108  that memory devices  112   a - 112   c  have not completed their power-up sequences and are therefore “not ready.” At  138 , CK and bCK signals  124  are stabilized. With CK and bCK signals  124  stabilized and memory devices  112   a - 112   c  “not ready,” controller  108  does not issue any commands as indicated on command signal  126  at  140 . 
         [0036]    In response to non-volatile memory device  112   a  completing its power-up sequence, memory device  112   a  transitions the DQ&lt;x&gt; signal  184  from a logic low “not ready” to logic high “ready” as indicated at  186 . In response to non-volatile memory device  112   a  completing its power-up sequence, controller  108  begins accessing non-volatile memory device  112   a  as indicated at  188 . 
         [0037]    In response to both memory devices  112   b  and  112   c  completing their power-up sequences, memory devices  112   b  and  112   c  transition the DM signal  182  from a logic low “not ready” to a logic high “ready” as indicated at  190 . In response to the logic high DM signal  182 , controller  108  determines that both memory devices  112   b  and  112   c  have completed their power-up sequences. In response to controller  108  determining that both memory devices  112   b  and  112   c  have completed their power-up sequences, controller  108  begins accessing memory devices  112   b  and  112   c  as indicated at  148 . In one embodiment, controller  108  begins accessing memory devices  112   b  and  112   c  by issuing a precharge all (PCHA) command on command signal  126  at  150 . In one embodiment, the time as indicated at  139  between the CK and bCK signals  124  stabilizing and the precharge all command is less than 200 μs. 
         [0038]    Embodiments of the present invention provide a memory including multiple memory devices sharing a common data bus. A controller coupled to the memory devices receives signals indicating when the memory devices have completed their power-up sequences. The controller may begin accessing a memory device once it has completed its power-up sequence. Since the controller does not wait a set time after the controller clock becomes stable before accessing the memory devices, the memory may be accessed sooner than typical memories. 
         [0039]    Although specific embodiments have been illustrated and described. herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.