Abstract:
An internal voltage generation circuit utilizing dual comparison signal generators and dual drivers to drive the internal voltage to a selected level. The second driver is responsive to a control signal derived from both of the comparison signal generators. The internal voltage generation circuit overcomes a problem with prior art circuits that may not permit the internal voltage to be driven to the selected level over a range of power supply voltages.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2012-0150095, filed on Dec. 20, 2012, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as though fully set forth herein. 
       BACKGROUND 
       [0002]    The present invention relates generally to semiconductor integrated circuits and, more particularly, to internal voltage generation circuits. 
         [0003]    In general, a semiconductor memory device receives a power supply voltage VDD and a ground voltage VSS from an external device to generate internal voltages used in operation of internal circuits of the semiconductor memory device. The internal voltages for operating the internal circuits of the semiconductor memory device may include a core voltage VCORE supplied to a memory core region, a high voltage VPP used to drive or overdrive word lines or the like, and a back-bias voltage VBB applied to a bulk region (or a substrate) of NMOS transistors in the memory core region. 
         [0004]    The core voltage VCORE may be a positive voltage which is less than the power supply voltage VDD supplied by the external device. Thus, the core voltage VCORE may be generated by reducing the power supply voltage VDD to a certain level. In contrast, the high voltage VPP may be greater than the power supply voltage VDD, and the back-bias voltage VBB may be a negative voltage which is less than the ground voltage VSS. Thus, charge pump circuits may be required to generate the high voltage VPP and the back-bias voltage VBB. 
         [0005]      FIG. 1  is a circuit diagram illustrating a conventional internal voltage generation circuit of the prior art. 
         [0006]    As illustrated in  FIG. 1 , the conventional internal voltage generation circuit is configured to include a comparator  1  and a driver  2 . 
         [0007]    The comparator  1  may compare a voltage level of a node ND 10  between two resistors R 1  and R 2 , which are serially connected to an output node having an internal voltage VINT, with a reference voltage VREF to generate a comparison signal COMP. The comparison signal COMP may be enabled to have a logic “low” level when the voltage level of the node ND 10  is less than the reference voltage VREF. 
         [0008]    The driver  2  may turn on a PMOS transistor P 1  to pull up the internal voltage VINT to a power supply voltage VDD when the comparison signal COMP is enabled to have a logic “low” level. If the internal voltage VINT is pulled up, the level of the node ND 10  may also be pulled up. Accordingly, the driver  2  may continuously pull up the internal voltage VINT until the level of the node ND 10  is equal to the reference voltage VREF. 
         [0009]    However, if the power supply voltage VDD applied to the driver  2  is less than a target level of the internal voltage VINT, it may be impossible to drive the internal voltage VINT to the target level over the power supply voltage VDD. 
       SUMMARY 
       [0010]    In an embodiment, an internal voltage generation circuit includes a first internal voltage driver and a second internal voltage driver. The first internal voltage driver is configured to drive an internal voltage to a first power supply voltage when the internal voltage is less than a first target level, and the second internal voltage driver is configured to drive the internal voltage to a second power supply voltage when the internal voltage is greater than or equal to the first target level and is less than a second target level. 
         [0011]    In accordance with another embodiment, an internal voltage generation circuit includes a first comparison signal generator configured to be driven by a first power supply voltage and configured to compare an internal voltage with a first reference voltage to generate a first comparison signal, a second comparison signal generator configured to be driven by a second power supply voltage and configured to compare the internal voltage with a second reference voltage to generate a second comparison signal, a first driver configured to be driven by the first power supply voltage and configured to drive the internal voltage in response to the first comparison signal, a pull-up signal generator configured to generate a pull-up signal enabled when both the first and second comparison signals are disabled, and a second driver configured to be driven by the second power supply voltage and configured to drive the internal voltage in response to the pull-up signal. 
         [0012]    In accordance with another embodiment, An internal voltage generation circuit includes a first comparison signal generator that compares an internal voltage with a first reference voltage to generate a first comparison signal, a second comparison signal generator that compares the internal voltage with a second reference voltage to generate a second comparison signal, a first driver that drives the internal voltage in response to the first comparison signal and a second driver that drives the internal voltage in response to a control signal derived from the first and second comparison signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The above and other features and advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein: 
           [0014]      FIG. 1  is a circuit diagram illustrating a conventional internal voltage generation circuit of the prior art; 
           [0015]      FIG. 2  is a block diagram illustrating a configuration of an internal voltage generation circuit in an embodiment in accordance with the present invention; and 
           [0016]      FIG. 3  is a circuit diagram of the internal voltage generation circuit illustrated in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Hereinafter, embodiments in accordance with the present invention will be explained in more detail with reference to the accompanying drawings. Although the present invention is described with reference to a number of example embodiments thereof, it should be understood that numerous other modifications and variations may be devised by one skilled in the art that will fall within the spirit and scope of the invention. 
         [0018]    As illustrated in  FIG. 2 , the internal voltage generation circuit in an embodiment in accordance with the present invention may be configured to include a first internal voltage driver  10  and a second internal voltage driver  20 . The first internal voltage driver  10  may drive an internal voltage VINT to a first power supply voltage VDD 1  when the internal voltage VINT is less than a first target level. The second internal voltage driver  20  may drive the internal voltage VINT to a second power supply voltage VDD 2  when the internal voltage VINT is greater than or equal to the first target level and is less than a second target level. The first power supply voltage VDD 1  may be set to be greater than the second power supply voltage VDD 2 , and the first and second power supply voltages VDD 1  and VDD 2  may be supplied by an external device. Further, the first power supply voltage VDD 1  may be greater than a target level of the internal voltage VINT. 
         [0019]    The first target level may be set to drive the internal voltage VINT to the first power supply voltage VDD 1 , and the second target level may be set to drive the internal voltage VINT to the second power supply voltage VDD 2 . Detailed discussions of the first and second target levels will be provided subsequently. 
         [0020]    Configurations of the first and second internal voltage drivers  10  and  20  will be described more fully hereinafter with reference to  FIGS. 2 and 3 . 
         [0021]    The first internal voltage driver  10  may be configured to include a first comparison signal generator  11  and a first driver  12 . 
         [0022]    The first comparison signal generator  11  may be driven by the first power supply voltage VDD 1 . The first comparison signal generator  11  may be configured to include a first comparator  110  ( FIG. 3 ) that compares a first divided voltage VDIV 1  with a first reference voltage VREF 1  to generate a first comparison signal COMP 1  when an enablement signal EN is enabled to have a logic “high” level, and a first voltage divider  111  that divides the internal voltage VINT using resistors R 10  and R 11 , which are serially connected, to generate the first divided voltage VDIV 1  when the enablement signal EN is enabled to have a logic “high” level. 
         [0023]    That is, the first comparison signal generator  11  may generate the first comparison signal COMP 1 , enabled to have a logic “low” level, when the first divided voltage VDIV 1  is less than the first reference voltage VREF 1 . The first comparison signal generator  11  may generate the first comparison signal COMP 1 , disabled to have a logic “high” level, when the first divided voltage VDIV 1  is greater than or equal to the first reference voltage VREF 1 . In an embodiment, the resistors  10  and  11  may have the same resistance value, such that the first divided voltage VDIV 1  is set to one-half of the internal voltage VINT. Further, the enablement signal EN may be enabled to have a logic “high” level for operation of the internal voltage generation circuit. 
         [0024]    The first driver  12  may pull up the internal voltage VINT to the first power supply voltage VDD 1  when the first comparison signal COMP 1  is enabled to have a logic “low” level. 
         [0025]    The second internal voltage driver  20  may be configured to include a second comparison signal generator  21 , a pull-up signal generator  22  and a second driver  23 . 
         [0026]    The second comparison signal generator  21  may be driven by the second power supply voltage VDD 2 . The second comparison signal generator  21  may be configured to include a second comparator  210  ( FIG. 3 ) that compares a second divided voltage VDIV 2  with a second reference voltage VREF 2  to generate a second comparison signal COMP 2  when the enablement signal EN is enabled to have a logic “high” level, and a second voltage divider  211  that divides the internal voltage VINT using resistors R 20  and R 21 , which are serially connected, to generate the second divided voltage VDIV 2  when the enablement signal EN is enabled to have a logic “high” level. That is, the second comparison signal generator  21  may generate the second comparison signal COMP 2 , disabled to have a logic “high” level, when the second divided voltage VDIV 2  is less than the second reference voltage VREF 2 . The second comparison signal generator  21  may generate the second comparison signal COMP 2 , enabled to have a logic “low” level, when the second divided voltage VDIV 2  is greater than or equal to the second reference voltage VREF 2 . In an embodiment, the resistors  20  and  21  may have the same resistance value such that the second divided voltage VDIV 2  is set to one-half of the internal voltage VINT. Further, the second reference voltage VREF 2  may be set to be greater than the first reference voltage VREF 1 . 
         [0027]    The pull-up signal generator  22  may generate a pull-up signal PU which is enabled to have a logic “low” level when both the first and second comparison signals COMP 1  and COMP 2  are disabled to have a logic “high” level. 
         [0028]    The second driver  23  may pull up the internal voltage VINT to the second power supply voltage VDD 2  when the pull-up signal PU is enabled to have a logic “low” level. 
         [0029]    The first and second target levels are discussed in detail in the following paragraphs. 
         [0030]    The first target level may be a level for driving the internal voltage VINT to the first power supply voltage VDD 1  when the first and second divided voltages VDIV 1  and VDIV 2  (having a level substantially equal to one-half of the internal voltage VINT) are generated to have a level less than the first reference voltage VREF 1 . Thus, the first target level may be set to have a level which is twice that of the first reference voltage VREF 1 . 
         [0031]    The second target level may be a level for driving the internal voltage VINT to the second power supply voltage VDD 2  when the first and second divided voltages VDIV 1  and VDIV 2  (having a level substantially equal to one-half of the internal voltage VINT) are generated to have a lower level than the second reference voltage VREF 2 . Thus, the second target level may be set to have a level which is twice that of the second reference voltage VREF 2 . 
         [0032]    Hereinafter, operation of the internal voltage generation circuit as set forth above will be described in conjunction with an example wherein the second power supply voltage VDD 2  is less than a target level of the internal voltage VINT and the internal voltage VINT is less than the first target level. 
         [0033]    The first voltage divider  111  ( FIG. 3 ) of the first comparison signal generator  11  may generate the first divided voltage VDIV 1 , having a level less than the first reference voltage VREF 1 , when the internal voltage VINT is less than the first target level. The second voltage divider  211  of the second comparison signal generator  21  may generate the second divided voltage VDIV 2 , having a level less than the second reference voltage VREF 2 , when the internal voltage VINT is less than the first target level. 
         [0034]    The first comparator  110  of the first comparison signal generator  11  may compare the first divided voltage VDIV 1 , less than the first reference voltage VREF 1 , with the first reference voltage VREF 1  to generate the first comparison signal COMP 1  having a logic “low” level. The second comparator  210  of the second comparison signal generator  21  may compare the second divided voltage VDIV 2 , less than the second reference voltage VREF 2 , with the second reference voltage VREF 2  to generate the second comparison signal COMP 2  having a logic “high” level. 
         [0035]    The pull-up signal generator  22  may execute a NAND operation of the first comparison signal COMP 1  having a logic “low” level and the second comparison signal COMP 2  having a logic “high” level to generate the pull-up signal PU having a logic “high” level. 
         [0036]    The first driver  12  may receive the first comparison signal COMP 1 , having a logic “low” level, to drive the internal voltage VINT to the first power supply voltage VDD 1 . The second driver  23  may receive the pull-up signal PU, having a logic “high” level, such as not to drive the internal voltage VINT to the second power supply voltage VDD 2 . That is, the first driver  12  may drive the internal voltage VINT to the first power supply voltage VDD 1  until the internal voltage VINT is generated to have the first target level. 
         [0037]    As described above, the internal voltage generation circuit according to an embodiment may drive the internal voltage VINT to the first power supply voltage VDD 1 , having a level greater than the second power supply voltage VDD 2 , to converge the internal voltage VINT to the target level when the second power supply voltage VDD 2  is less than the target level of the internal voltage VINT. 
         [0038]    Hereinafter, an operation of the internal voltage generation circuit as set forth above will be described in conjunction with an example wherein the second power supply voltage VDD 2  is greater than a target level of the internal voltage VINT, and the internal voltage VINT is greater than or equal to the first target level and is less than the second target level. 
         [0039]    The first voltage divider  111  ( FIG. 3 ) of the first comparison signal generator  11  may generate the first divided voltage VDIV 1 , having a level greater than the first reference voltage VREF 1 , and having a level less than the second reference voltage VREF 2 , when the internal voltage VINT is greater than or equal to the first target level, and is less than the second target level. The second voltage divider  211  of the second comparison signal generator  21  may generate the second divided voltage VDIV 2 , having a level greater than the first reference voltage VREF 1 , and having a level less than the second reference voltage VREF 2 , when the internal voltage VINT is greater than or equal to the first target level, and is less than the second target level. 
         [0040]    The first comparator  110  of the first comparison signal generator  11  may compare the first divided voltage VDIV 1 , greater than the first reference voltage VREF 1 , with the first reference voltage VREF 1 , to generate the first comparison signal COMP 1  having a logic “high” level. The second comparator  210  of the second comparison signal generator  21  may compare the second divided voltage VDIV 2 , less than the second reference voltage VREF 2 , with the second reference voltage VREF 2 , to generate the second comparison signal COMP 2  having a logic “high” level. 
         [0041]    The pull-up signal generator  22  may execute a NAND operation of the first comparison signal COMP 1  having a logic “high” level and the second comparison signal COMP 2  having a logic “high” level to generate the pull-up signal PU having a logic “low” level. 
         [0042]    The first driver  12  may receive the first comparison signal COMP 1 , having a logic “high” level, such as not to drive the internal voltage VINT any more. The second driver  23  may receive the pull-up signal PU, having a logic “low” level, to drive the internal voltage VINT to the second power supply voltage VDD 2 . That is, the second driver  23  may drive the internal voltage VINT to the second power supply voltage VDD 2  until the internal voltage VINT is generated to have the second target level. 
         [0043]    As described above, the internal voltage generation circuit in an embodiment in accordance with the present invention may drive the internal voltage VINT to the second power supply voltage VDD 2  to converge the internal voltage VINT to the target level when the second power supply voltage VDD 2  is greater than the target level of the internal voltage VINT. 
         [0044]    While certain embodiments have been described above, it will be understood by those skilled in the art that the embodiments described are by way of example only. Accordingly, the internal voltage generation circuits described herein should not be limited based on the described embodiments. Rather, the internal voltage generation circuits described herein should only be limited in light of the claims that follow, when taken in conjunction with the above description and accompanying drawings.