Abstract:
In one embodiment, a semiconductor storage device includes a memory cell, a sense amplifier, a bit line, a pre-charge circuit, and a power-supply-voltage switching circuit. The memory cell is configured to store data. The sense amplifier is configured to amplify a signal from the memory cell. The bit line is configured to transmit the signal from the memory cell to the sense amplifier. The pre-charge circuit is configured to pre-charge the bit line. The power-supply-voltage switching circuit is configured to switch a voltage of a power supply and to actuate the sense amplifier after the bit line is pre-charged by the pre-charge circuit, wherein the power-supply-voltage switching circuit is configured to switch the voltage of the power supply to be larger than a voltage during the pre-charge by the pre-charge circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-66369, filed on Mar. 18, 2009; the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor storage device, and, more particular, is suitably applied to a method of realizing a reduction in power consumption of an SRAM by using power supplies that generate a plurality of voltages. 
     2. Description of the Related Art 
     According to the progress in reduction of power consumption of system LSIs in recent years, a reduction in power consumption of SRAMs are also in progress. As a method of reducing power consumption of an SRAM, there is a method of using a high-voltage power supply only for SRAM cells and a part of word line control circuit and using a low-voltage power supply for other circuits. A high power reduction effect can be obtained by this method because the voltage of a voltage power supply for bit lines can be reduced. 
     For example, Japanese Patent Application Laid-Open No. H9-282890 discloses a method of boosting a first voltage applied to an SRAM to a higher second voltage to actuate a memory cell array and a decoder with the first voltage and actuate a sense amplifier with the second voltage. 
     However, in the method of reducing the voltage of a voltage power supply for bit lines to realize a reduction in power consumption of an SRAM, because a pre-charge power supply has to be shared with a sense amplifier connected to the bit lines, a voltage power supply for the sense amplifier is also reduced in voltage. Therefore, sensing speed of the sense amplifier substantially drops to cause a reduction in speed of the SRAM. 
     In the method disclosed in Japanese Patent Application Laid-Open No. H9-282890, because a high-voltage power supply is used for the sense amplifier, a voltage power supply for bit lines connected to the sense amplifier is also increased in voltage to cause an increase in power consumption. 
     BRIEF SUMMARY OF THE INVENTION 
     A semiconductor storage device according to an embodiment of the present invention comprises: a memory cell that stores data; a sense amplifier that amplifies a signal read out from the memory cell; a bit line that transmits the signal read out from the memory cell to the sense amplifier; a pre-charge circuit that pre-charges the bit line; and a power-supply-voltage switching circuit that switches, after the bit line is pre-charged by the pre-charge circuit, a voltage of a power supply for actuating the sense amplifier. 
     A semiconductor storage device according to an embodiment of the present invention comprises: a memory cell that stores data; a local sense amplifier that amplifies a signal read out from the memory cell; a bit line that transmits the signal read out from the memory cell to the local sense amplifier; a first pre-charge circuit that pre-charges the bit line; a global bit line that transmits the signal amplified by the local sense amplifier; a second pre-charge circuit that pre-charges the global bit line; a global sense amplifier that amplifies the signal transmitted by the global bit line; a driving circuit that drives the global bit line based on the signal amplified by the local sense amplifier; and a power-supply-voltage switching circuit that switches, after the global bit line is pre-charged by the second pre-charge circuit, a voltage of a power supply for actuating the driving circuit. 
     A semiconductor storage device according to an embodiment of the present invention comprises: a memory cell that stores data; a local sense amplifier that amplifies a signal read out from the memory cell; a bit line connected to the memory cell; a sense bit line that transmits a signal read out to the bit line to the local sense amplifier; a first pre-charge circuit that pre-charges the bit line; a second pre-charge circuit that pre-charges the sense bit line; a global bit line that transmits the signal amplified by the local sense amplifier; a third pre-charge circuit that pre-charges the global bit line; a global sense amplifier that amplifies the signal transmitted by the global bit line; a driving circuit that drives the global bit line based on the signal amplified by the local sense amplifier; and a power-supply-voltage switching circuit that switches, after the sense bit line is pre-charged by the second pre-charge circuit, a voltage of a power supply for actuating the local sense amplifier. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a schematic configuration of a semiconductor storage device according to a first embodiment of the present invention; 
         FIG. 2  is a block diagram of a schematic configuration of a bank BA shown in  FIG. 1 ; 
         FIG. 3  is a timing chart of the operation of a local sense amplifier LA shown in  FIG. 2 ; 
         FIG. 4  is a block diagram of a schematic configuration of a semiconductor storage device according to a second embodiment of the present invention; and 
         FIG. 5  is a timing chart of the operation of a local sense amplifier LA and a global sense amplifier GA shown in  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Exemplary embodiments of the present invention are explained in detail below with reference to the accompanying drawings. The present invention is not limited by the embodiments. 
       FIG. 1  is a block diagram of a schematic configuration of a semiconductor storage device according to a first embodiment of the present invention.  FIG. 2  is a block diagram of a schematic configuration of a bank BA shown in  FIG. 1 . 
     In  FIG. 2 , memory cells MC, each of which stores data for one bit, are provided in the semiconductor storage device. The memory cells MC are arrayed in a matrix shape in a row direction and a column direction. 
     In each of the memory cells MC, P-channel field effect transistors (hereinafter, “P-ch transistors”) M 41  and M 42  and N-channel field effect transistors (hereinafter, “N-ch transistors”) M 43  to M 46  are provided. The P-ch transistor M 41  and the N-ch transistor M 43  are connected in series and a gate of the P-ch transistor M 41  and a gate of the N-ch transistor M 43  are connected to each other to form an inverter. The P-ch transistor M 42  and the N-ch transistor M 44  are connected in series and a gate of the P-ch transistor M 42  and a gate of the N-ch transistor M 44  are connected to each other to form an inverter. An output of one of the pair of inverters is connected to an input of the other inverter to form a flip-flop. 
     The gate of the P-ch transistor M 41 , the gate of the N-ch transistor M 43 , a drain of the P-ch transistor, and a drain of the N-ch transistor M 44  are connected to a bit line BL&lt;i&gt; via the N-ch transistor M 45 . The gate of the P-ch transistor M 42 , the gate of the N-ch transistor M 44 , a drain of the P-ch transistor M 41 , and a drain of the N-ch transistor M 43  are connected to a bit line BLB&lt;i&gt; via the N-ch transistor M 46 . 
     A gate of the N-ch transistor M 45  and a gate of the N-ch transistor M 46  are connected to a word line WL. 
     High-voltage power supplies VCS are used as power supplies for actuating the memory cells MC. Sources of the P-ch transistors M 41  and M 42  are connected to the high-voltage power supplies VCS. 
     With the bit lines BL&lt;i&gt; and BLB&lt;i&gt; set as a pair, a cluster CL is formed by a plurality of memory cells MC in the column direction connected to the bit lines BL&lt;i&gt; and BLB&lt;i&gt;. Bit lines BL&lt;i+1&gt; and BLB&lt;i+1&gt; are arranged beside the bit lines BL&lt;i&gt; and BLB&lt;i&gt;, whereby clusters CL are arrayed in the row direction. As shown in  FIG. 1 , banks BA are formed by the clusters CL arrayed in the row direction. The banks BA are arrayed in the column direction and the row direction. A pair of global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are provided in common to a plurality of banks BA arrayed in the column direction. 
     In each of the clusters CL, as shown in  FIG. 2 , a pre-charge circuit PC 1  that pre-charges the bit lines BL&lt;i&gt; and BLB&lt;i&gt; of the cluster CL is provided. P-ch transistors M 11  to M 13  are provided in the pre-charge circuit PC 1 . Gates of the P-ch transistors M 11  to M 13  are connected to one another. The P-ch transistor M 13  is connected between the bit lines BL&lt;i&gt; and BLB&lt;i&gt;. A drain of the P-ch transistor M 11  is connected to the bit line BL&lt;i&gt;. A drain of the P-ch transistor M 12  is connected to the bit line BLB&lt;i&gt;. 
     A low-voltage power supply VDD is used as a power supply for actuating the pre-charge circuit PC 1 . Sources of the P-ch transistors M 11  and M 12  are connected to the low-voltage power supply VDD. The low-voltage power supply VDD is set to a voltage lower than that of the high-voltage power supply VCS. P-ch transistors M 14  and M 15  that select the cluster CL from the banks BA are provided at a post stage of the pre-charge circuit PC 1 . The P-ch transistor M 14  is inserted in the bit line BL&lt;i&gt;. The P-ch transistor M 15  is inserted in the bit line BLB&lt;i&gt;. A gate of the P-ch transistor M 14  and a gate of the P-ch transistor M 15  are connected to each other. 
     The bit lines BL&lt;i&gt;, BLB&lt;i&gt;, BL&lt;i+1&gt;, BLB&lt;i+1&gt;, . . . of the clusters CL are respectively connected to sense bit lines SABL and SABLB via the P-ch transistors M 16  and M 17 . 
     A local sense amplifier LA that amplifies signals read out from the memory cells MC and a pre-charge circuit PC 2  that pre-charges the sense bit lines SABL and SABLB are connected to the sense bit lines SABL and SABLB. 
     P-ch transistors M 20  and M 21  and N-ch transistors M 22  to M 24  are provided in the local sense amplifier LA. The P-ch transistor M 20  and the N-ch transistor M 22  are connected in series and a gate of the P-ch transistor M 20  and a gate of the N-ch transistor M 22  are connected to each other to form an inverter. The P-ch transistor M 21  and the N-ch transistor M 23  are connected in series and a gate of the P-ch transistor M 21  and a gate of the N-ch transistor M 23  are connected to each other to form an inverter. An output of one of the pair of inverters is connected to an input of the other inverter to form a flip-flop. 
     The gate of the P-ch transistor M 21 , the gate of the N-ch transistor M 23 , a drain of the P-ch transistor M 20 , and a drain of the N-ch transistor  22  are connected to the sense bit line SABL. The gate of the P-ch transistor M 20 , the gate of the N-ch transistor M 22 , a drain of the P-ch transistor M 21 , and a drain of the N-ch transistor M 23  are connected to the sense bit line SABLB. Sources of the N-ch transistors M 22  and M 23  are connected to a drain of the N-ch transistor M 24 . 
     P-ch transistors M 25  to M 27  are provided in the pre-charge circuit PC 2 . Gates of the P-ch transistors M 25  to M 27  are connected to one another. The P-ch transistor M 27  is connected between the sense bit lines SABL and SABLB. A drain of the P-ch transistor M 25  is connected to the sense bit line SABL. A drain of the P-ch transistor M 26  is connected to the sense bit line SABLB. 
     The low-voltage power supply VDD is used as a power supply for actuating the pre-charge circuit PC 2 . Sources of the P-ch transistors M 25  and M 26  are connected to the low-voltage power supply VDD. 
     The sense bit lines SABL and SABLB are connected to global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; via driving circuits R 1  and R 2 , respectively. 
     The driving circuits R 1  and R 2  can drive the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt;, respectively, based on a signal amplified by the local sense amplifier LA. A P-ch transistor M 28  and N-ch transistors M 1  and M 29  are provided in the driving circuit R 1 . The P-ch transistor M 28  and the N-ch transistor M 29  are connected in series and a gate of the P-ch transistor M 28  and a gate of the N-ch transistor M 29  are connected to each other to form an inverter. 
     The gate of the P-ch transistor M 28  and the gate of the N-ch transistor M 29  are connected to the sense bit line SABL. A drain of the P-ch transistor M 28  and a drain of the N-ch transistor M 29  are connected to a gate of the N-ch transistor M 1 . A drain of the N-ch transistor M 1  is connected to the global bit line GBL&lt;k&gt;. 
     A P-ch transistor M 30  and N-ch transistors M 2  and M 31  are provided in the driving circuit R 2 . The P-ch transistor M 30  and the N-ch transistor M 31  are connected in series and a gate of the P-ch transistor M 30  and a gate of the N-ch transistor M 31  are connected to each other to form an inverter. 
     The gate of the P-ch transistor M 30  and the gate of the N-ch transistor M 31  are connected to the sense bit line SABLB. A drain of the P-ch transistor M 30  and a drain of the N-ch transistor M 31  are connected to a gate of the N-ch transistor M 2 . A drain of the N-ch transistor M 2  is connected to the global bit line GBLB&lt;k&gt;. 
     As shown in  FIG. 1 , a global sense amplifier GA that amplifies signals transmitted through the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; and a pre-charge circuit PC 3  that pre-charges the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are connected to the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt;. 
     P-ch transistors M 3  to M 5  are provided in the pre-charge circuit PC 3 . Gates of the P-ch transistors M 3  to M 5  are connected to one another. A P-ch transistor M 5  is connected between the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt;. A drain of the P-ch transistor M 3  is connected to the global bit line GBL&lt;k&gt; and a drain of the P-ch transistor M 4  is connected to the global bit line GBLB&lt;k&gt;. 
     The low-voltage power supply VDD is used as a power supply for actuating the pre-charge circuit PC 3 . Sources of the P-ch transistors M 3  and M 4  are connected to the low-voltage power supply VDD. 
     In  FIG. 2 , a power-supply-voltage switching circuit SL 1  that switches, after the sense bit lines SABL and SABLB are pre-charged by the pre-charge circuit PC 2 , the voltage of a power supply for actuating the local sense amplifier LA and the driving circuits R 1  and R 2  is provided in the semiconductor storage device. The power-supply-voltage switching circuit SL 1  can supply the low-voltage power supply VDD to the local sense amplifier LA and the driving circuits R 1  and R 2  when a sense amplifier enable signal SAE 1  for allowing the operation of the local sense amplifier LA is off. The power-supply-voltage switching circuit SL 1  can supply the high-voltage power supply VCS to the local sense amplifier LA and the driving circuits R 1  and R 2  when the sense amplifier enable signal SAE 1  is on. 
     P-ch transistors M 18  and M 19  and an inverter IV 1  are provided in the power-supply-voltage switching circuit SL 1 . The low-voltage power supply VDD is connected to a source of the P-ch transistor M 18 . The high-voltage power supply VCS is connected to a source of the P-ch transistor M 19 . Drains of the P-ch transistors M 18  and M 19  are connected to drains of the P-ch transistors M 20 , M 21 , M 28 , and M 30 . 
     The sense amplifier enable signal SAE 1  is input to gates of the P-ch transistors M 16  to M 18  and the N-ch transistor M 24  via a buffer BA 1 . The sense amplifier enable signal SAE 1  is input to a gate of the P-ch transistor M 19  via the buffer BA 1  and the inverter IV 1 . 
       FIG. 3  is a timing chart of the operation of the local sense amplifier LA shown in  FIG. 2 . 
     In  FIG. 3 , before data is read out from the memory cell MC shown in  FIG. 2 , a pre-charge signal Pre is maintained at a low level. When the pre-charge signal Pre is at the low level, the P-ch transistors M 11  to M 13  are turned on and the low-voltage power supply VDD is connected to the bit lines BL&lt;i&gt; and BLB&lt;i&gt;. The bit lines BL&lt;i&gt; and BLB&lt;i&gt; are pre-charged to increase potentials thereof to the voltage of the low-voltage power supply VDD. 
     When the pre-charge signal Pre is at the low level, the P-ch transistors M 25  to M 27  are turned on and the low-voltage power supply VDD is connected to the sense bit lines SABL and SABLB. The sense bit lines SABL and SABLB are pre-charged to increase potentials thereof to the voltage of the low-voltage power supply VDD. 
     When the pre-charge signal Pre is at the low level, the P-ch transistors M 3  to M 5  shown in  FIG. 1  are turned on and the low-voltage power supply VDD is connected to the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt;. The global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are pre-charged to increase potentials thereof to the voltage of the low-voltage power supply VDD. 
     Before data is read out from the memory cell MC, the sense amplifier enable signal SAE 1  is maintained at the low level. When the sense amplifier enable signal SAE 1  is maintained at the low level, the N-ch transistor M 24  is turned off, the operation of the local sense amplifier LA is stopped, and the P-ch transistors M 16  and M 17  are turned on. The signal read out from the memory cell MC is maintained to be capable of being transmitted to the sense bit lines SABL and SABLB via the bit lines BL&lt;i&gt; and BLB&lt;i&gt;. 
     When the sense amplifier enable signal SAE 1  is maintained at the low level, the P-ch transistor M 18  is turned on, the sense amplifier enable signal SAE 1  is inverted by the inverter IV 1 , and the P-ch transistor M 19  is turned off. Therefore, a power supply voltage Vir_supp output from the power-supply-voltage switching circuit SL 1  is switched to the low-voltage power supply VDD and the low-voltage power supply VDD is supplied to the P-ch transistors M 20 , M 21 , M 28 , and M 30 . Consequently, the local sense amplifier LA and the driving circuits R 1  and R 2  are actuated by the low-voltage power supply VDD. 
     When data is read out from the memory cell MC shown in  FIG. 2 , a clock signal CLK changes from the low level to a high level (time t 1 ). When the clock signal CLK changes from the low level to the high level, the pre-charge signal Pre changes from the low level to the high level and the P-ch transistors M 11  to M 13 , M 25  to M 27 , and M 3  to M 5  are turned off. 
     When the P-ch transistors M 11  to M 13  are turned off, the pre-charge of the bit lines BL&lt;i&gt; and BLB&lt;i&gt; is stopped. When the P-ch transistors M 25  to M 27  are turned off, the pre-charge of the sense bit lines SABL and SABLB is stopped. When the P-ch transistors M 3  to M 5  are turned off, the pre-charge of the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; is stopped. 
     When the clock signal CLK changes from the low level to the high level, the potential on the word line WL shown in  FIG. 2  changes from the low level to the high level (time t 2 ). When the potential on the word line WL changes from the low level to the high level, the N-ch transistors M 45  and M 46  are turned on. One of the bit lines BL&lt;i&gt; and BLB&lt;i&gt; is discharged according to data stored in the memory cell MC. The potential on one of the bit lines BL&lt;i&gt; and BLB&lt;i&gt; drops. 
     When the clock signal CLK changes from the low level to the high level, a cluster selection signal CSL&lt;i&gt; changes from the high level to the low level. The bit lines BL&lt;i&gt; and BLB&lt;i&gt; are selected out of the bit lines BL&lt;i&gt;, BLB&lt;i&gt;, BL&lt;i+1&gt;, BLB&lt;i+1&gt;, . . . to which the sense bit lines SABL and SABLB are connected. 
     The potentials on the bit lines BL&lt;i&gt; and BLB&lt;i&gt; are transmitted to the sense bit lines SABL and SABLB via the P-ch transistors M 14  to M 17 . The potential on one of the sense bit lines SABL and SABLB also drops according to the drop in the potential on one of the bit lines BL&lt;i&gt; and BLB&lt;i&gt;. 
     For example, after the elapse of a predetermined time from the start of discharge of the bit line BLB&lt;i&gt;, the sense amplifier enable signal SAE 1  changes from the low level to the high level (time t 3 ). When the sense amplifier enable signal SAE 1  changes from the low level to the high level, the N-ch transistor M 24  is turned on and the local sense amplifier LA is actuated. The P-ch transistors M 16  and M 17  are turned off and the bit lines BL&lt;i&gt; and BLB&lt;i&gt; and the sense bit lines SABL and SABLB are disconnected. 
     When the sense amplifier enable signal SAE 1  changes from the low level to the high level, the P-ch transistor M 18  is turned off, the sense amplifier enable signal SAE 1  is inverted by the inverter IV 1 , and the P-ch transistor M 19  is turned on. Therefore, the power supply voltage Vir_Supp output from the power-supply-voltage switching circuit SL 1  is switched to the high-voltage power supply VCS. The high-voltage power supply VCS is supplied to the P-ch transistors M 20 , M 21 , M 28 , and M 30 . The local sense amplifier LA and the driving circuits R 1  and R 2  are actuated by the high-voltage power supply VCS. 
     When the local sense amplifier LA is actuated by the high-voltage power supply VCS, the detection of the voltages on the sense bit lines SABL and SABLB is performed at high speed compared with the detection performed when the local sense amplifier LA is actuated by the low-voltage power supply VDD. When the driving circuits R 1  and R 2  are actuated by the high-voltage power supply VCS, the discharge of the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; is performed at high speed compared with the discharge performed when the driving circuits R 1  and R 2  are actuated by the low-voltage power supply VDD. 
     The voltages on the sense bit lines SABL and SABLB amplified by the local sense amplifier LA are input to the driving circuits R 1  and R 2 , respectively (time t 4 ). When the voltage on the sense bit line SABL is input to the driving circuit R 1 , the voltage is inverted by the inverter including the P-ch transistor M 28  and the N-ch transistor M 29 . An inverted voltage GBL_n of the voltage is input to the gate of the N-ch transistor M 1 . When the voltage on the sense bit line SABLB is input to the driving circuit R 2 , the voltage is inverted by the inverter including the P-ch transistor M 30  and the N-ch transistor M 31 . An inverted voltage GBLB_n of the voltage is input to the gate of the N-ch transistor M 2 . 
     When the inverted voltages GBL_n and GBLB_n are input to the gates of the N-ch transistors M 1  and M 2 , respectively, the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are discharged according to the inverted voltages GBL_n and GBLB_n. The potential on one of the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; also drops according to the drop in the potential on one of the sense bit lines SABL and SABLB. The potentials on the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are input to the global sense amplifier GA and amplified by the global sense amplifier GA. 
     After the bit lines BL&lt;i&gt; an BLB&lt;i&gt;, the sense bit lines SABL and SABLB, and the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are pre-charged by the low-voltage power supply VDD, the local sense amplifier LA and the driving circuits R 1  and R 2  are actuated by the high-voltage power supply VCS. This makes it possible to realize an increase in speed of the local sense amplifier LA and the driving circuits R 1  and R 2  without increasing electric power consumed by the bit lines BL&lt;i&gt; and BLB&lt;i&gt;, the sense bit lines SABL and SABLB, and the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt;. Therefore, it is possible to improve readout operation speed while suppressing an increase in power consumption of an SRAM. 
     The P-ch transistors M 16  and M 17  are inserted between the bit lines BL&lt;i&gt; and BLB&lt;i&gt; and the sense bit lines SABL and SABLB. The bit lines BL&lt;i&gt; and BLB&lt;i&gt; and the sense bit lines SABL and SABLB are disconnected when the local sense amplifier LA is actuated. This makes it unnecessary to discharge the bit lines BL&lt;i&gt; and BLB&lt;i&gt; with the local sense amplifier LA. This makes it possible to reduce a load on the local sense amplifier LA when a signal read out from the memory cell MC is amplified by the local sense amplifier LA. Therefore, it is possible to realize an increase in speed of the operation of the local sense amplifier LA. 
     In the method explained in the embodiment, after the bit lines BL&lt;i&gt; and BLB&lt;i&gt;, the sense bit lines SABL and SABLB, and the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are pre-charged by the low-voltage power supply VDD, the local sense amplifier LA and the driving circuits R 1  and R 2  are actuated by the high-voltage power supply VCS. However, one of the local sense amplifier LA and the driving circuits R 1  and R 2  can be actuated by the high-voltage power supply VCS. 
     The method explained in the embodiment is applied to a hierarchical bit line structure in which the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are provided above the bit lines BL&lt;i&gt; and BLB&lt;i&gt;. However, the method can be applied to a single layer bit line structure in which the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are not provided above the bit lines BL&lt;i&gt; and BLB&lt;i&gt;. 
     In the method explained in the embodiment, the power supply for the local sense amplifier LA connected to the sense bit lines SABL and SABLB, which can be disconnected from the bit lines BL&lt;i&gt; and BLB&lt;i&gt;, is switched. However, a power supply for a sense amplifier directly connected to the bit lines BL&lt;i&gt; and BLB&lt;i&gt; can be switched. 
       FIG. 4  is a block diagram of a schematic configuration of a semiconductor storage device according to a second embodiment of the present invention. 
     In  FIG. 4 , a power-supply-voltage switching circuit SL 2  that switches, after the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; are pre-charged by the pre-charge circuit PC 3 , the voltage of the power supply for actuating the global sense amplifier GA is provided in the semiconductor storage device in addition to the components shown in  FIGS. 1 and 2 . 
     P-ch transistors M 60  and M 61  and N-ch transistors M 62  to M 64  are provided in the global sense amplifier GA. The P-ch transistor M 60  and the N-ch transistor M 62  are connected in series and a gate of the P-ch transistor M 60  and a gate of the N-ch transistor M 62  are connected to each other to form an inverter. The P-ch transistor M 61  and the N-ch transistor M 63  are connected in series and a gate of the P-ch transistor M 61  and a gate of the N-ch transistor M 63  are connected to each other to form an inverter. An output of one of the pair of inverters is connected to an input of the other inverter to form a flip-flop. 
     The gate of the P-ch transistor M 61 , the gate of the N-ch transistor M 63 , a drain of the P-ch transistor M 60 , and a drain of the N-ch transistor M 62  are connected to a global bit line GBL&lt;k&gt;. The gate of the P-ch transistor M 60 , the gate of the N-ch transistor M 62 , a drain of the P-ch transistor M 61 , and a drain of the N-ch transistor M 63  are connected to the global bit line GBLB&lt;k&gt;. Sources of the N-ch transistors M 62  and M 63  are connected to a drain of the N-ch transistor M 64 . 
     The power-supply-voltage switching circuit SL 2  can supply the low-voltage power supply VDD to the global sense amplifier GA when a sense amplifier enable signal SAE 2  for allowing the operation of the global sense amplifier GA is off. The power-supply-voltage switching circuit SL 2  can supply the high-voltage power supply VCS to the global sense amplifier GA when the sense amplifier enable signal SAE 2  is on. 
     P-ch transistors M 58  and M 59  and an inverter IV 2  are provided in the power-supply-voltage switching circuit SL 2 . The low-voltage power supply VDD is connected to a source of the P-ch transistor M 58 . The high-voltage power supply VCS is connected to a source of the P-ch transistor M 59 . Drains of the P-ch transistors M 58  and M 59  are connected to sources of the P-ch transistors M 60  and M 61 . 
     The sense amplifier enable signal SAE 2  is input to a gate of the P-ch transistor M 58  and a gate of the N-ch transistor M 64  via a buffer BA 2 . The sense amplifier enable signal SAE 2  is input to a gate of the P-ch transistor M 59  via the buffer BA 2  and the inverter IV 2 . 
       FIG. 5  is a timing chart of the operation of the local sense amplifier LA and the global sense amplifier GA shown in  FIG. 4 . 
     In  FIG. 5 , when the voltages on the sense bit lines SABL and SABLB amplified by the local sense amplifier LA are input to the driving circuits R 1  and R 2 , respectively, the operation same as that shown in  FIG. 3  is performed until the potential on one of the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; also drops according to the drop in the potential on one of the sense bit lines SABL and SABLB (time t 1  to t 4 ). 
     Subsequently, for example, after the elapse of a predetermined time from the start of discharge of the global bit line GBLB&lt;k&gt;, the sense amplifier enable signal SAE 2  changes from the low level to the high level (time t 5 ). When the sense amplifier enable signal SAE 2  changes from the low level to the high level, the N-ch transistor M 64  is turned on and the global sense amplifier GA is actuated. 
     When the sense amplifier enable signal SAE 2  changes from the low level to the high level, the P-ch transistor M 58  is turned off, the sense amplifier enable signal SAE 2  is inverted by the inverter IV 2 , and the P-ch transistor M 59  is turned on. Therefore, a power supply for the P-ch transistors M 60  and M 61  is switched from the low-voltage power supply VDD to the high-voltage power supply VCS. The global sense amplifier GA is actuated by the high-voltage power supply VCS. 
     When the global sense amplifier GA is actuated by the high-voltage power supply VCS, the detection of the voltages on the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; is performed at high speed compared with the detection performed when the global sense amplifier GA is actuated by the low-voltage power supply VDD. 
     This makes it possible to actuate the local sense amplifier LA, the driving circuits R 1  and R 2 , and the global sense amplifier GA with the high-voltage power supply VCS after pre-charging the bit lines BL&lt;i&gt; and BLB&lt;i&gt;, the sense bit lines SABL and SABLB, and the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt; with the low-voltage power supply VDD. This also makes it possible to realize an increase in speed of the local sense amplifier LA, the driving circuits R 1  and R 2 , and the global sense amplifier GA without increasing electric power consumed by the bit lines BL&lt;i&gt; and BLB&lt;i&gt;, the sense bit lines SABL and SABLB, and the global bit lines GBL&lt;k&gt; and GBLB&lt;k&gt;. Consequently, it is possible to improve readout operation speed while suppressing an increase in power consumption of an SRAM even when the hierarchical bit line structure is used. 
     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.