Abstract:
A method for starting the modulation of a frequency converter, which method comprises the steps of receiving reference voltage (s a , s b , s c ; U ref ), generating output switch commands from the reference voltages. The generation of output switch commands comprises further a step, in which the ratio (d z ) of active time (T 0+ ) in a modulation period (T s ) of selected zero vector and the total active time (T 0+ +T 0− ) of zero vectors in a modulation period is changed from a first predetermined ratio, which is substantially 0 or 1, to a second predetermined ratio, which is substantially 0.5.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The invention relates to a method for starting the modulation of a frequency converter. More specifically, the invention relates to a method for starting the pulse width modulation of a frequency converter when the frequency converter is equipped with a common-mode output filter.  
         [0002]     The output voltage of a pulse-width modulated (PWM) inverter may cause problems in motor drives. Harmonics at the switching frequency and its multiples give rise to additional losses and acoustic noise in the motor, and pulse reflections expose the motor insulations to additional voltage stresses.  
         [0003]     These problems can be reduced by adding a sinusoidal LC filter having the cut-off frequency well below the switching frequency to the output of the inverter. Furthermore, to avoid capacitive leakage currents and bearing currents, the filter can be designed to reduce the common-mode voltage.  
         [0004]      FIG. 1  shows an output filter that reduces both common-mode (CM) and differential-mode (DM) voltages. The similar topology was originally disclosed in H. Akagi, H. Hasegawa, and T. Doumoto, “Design and performance of a passive EMI filter for use with a voltage-source PWM inverter having sinusoidal output voltage and zero common-mode voltage,”  IEEE Trans. Power Electron.,  vol. 19, no. 4, pp. 1069-1076, July 2004.  
         [0005]     An LC filter, consisting of a three-phase inductor L f  and three capacitors C f , attenuates high frequencies of the differential-mode inverter output voltage. A CM inductor L c , capacitor C c  and resistor R c  form a common-mode filter, which provides a route for the CM current and reduces the CM voltage at the motor terminals.  
         [0006]     However, the common-mode filtering presents a problem. The filter may cause severe oscillation when the modulation is started. Due to the abrupt start of a pulsating CM voltage and zero initial values of the CM voltage and current in the filter, the CM inductor L c  may get saturated in the start. The saturated CM inductor causes high current peaks, which may trigger the overcurrent protection. The problem has been reported in N. Hanigovszki, “EMC output filters for adjustable speed drives,” Ph. D. dissertation, Inst. Energy Techn., Aalborg Univ., Aalborg, Denmark, March 2005 for a slightly different filter topology.  
         [0007]      FIG. 2 ( a ) shows a modulation start of a 2.2-kW induction motor drive (400 V, 5.0 A, 50 Hz) equipped with the output filter shown in  FIG. 1 . The highest current peak exceeds 30 A, and the CM inductor becomes saturated. In the worst cases, the oscillation continued for several seconds.  
         [0008]     One solution for the starting problem was disclosed in the above Hanigovszki reference. This solution is based on additional hardware, which comprises a dynamic damping circuit consisting of an additional winding of the common-mode inductor, a full-bridge rectifier, a filtering capacitor and a resistive load. The damping circuit solves the starting problem, but it may affect the overall filter performance. Furthermore, the additional hardware makes the damping circuit less attractive with respect to physical size of the hardware and also to expenses.  
       BRIEF DESCRIPTION OF THE INVENTION  
       [0009]     It is an object of the present invention to provide a method that avoids the above-mentioned drawbacks and enables trouble-free starting of a pulse width modulated drive. This object is achieved by a method of the invention that is characterized by what is stated in independent claim  1 .  
         [0010]     The invention is based on the idea that the average common mode voltage generated by the frequency converter is abruptly set to its minimum or maximum value and then slowly ramped to zero at the start. The CM voltage can be controlled by means of the zero vector. In suboscillation PWM method the selection can be carried out by manipulating voltage references and in space vector PWM (SVPWM) method by dividing the active times of zero vectors such that required effect is achieved. 
     
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0011]     The invention will now be described in more detail by means of preferred embodiments and with reference to the attached drawings, in which  
         [0012]      FIG. 1  shows a circuit diagram of frequency converter and output filter,  
         [0013]      FIG. 2  shows experimental results showing common-mode voltage and common-mode current without (a) and with (b) the method of invention,  
         [0014]      FIG. 3  shows implementation of the method of the invention in connection with suboscillation PWM,  
         [0015]      FIG. 4  shows the principle of suboscillation (a) and symmetric suboscillation (b), and  
         [0016]      FIG. 5  shows switching states for the same voltage vector with different values of d z . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]     In the method of the invention, the on-durations or active times of zero vectors are controlled. During the switching period T s , the on-durations of the zero vectors 111 and 000 are denoted by T 0+  and T 0− , respectively. A relative duty cycle of the 111 zero vector is defined as  
               d   z     =       T     0   +           T     0   -       +     T     0   +                   (   1   )             
 
         [0018]     The ramping of the average CM voltage is achieved by ramping d z  from substantially 0 or 1 to substantially 0.5. Preferably the ramping is done from 0 or 1 to 0.5. The final value d z =0.5 corresponds to the known space vector PWM method, presented in T. Svensson, “On modulation and control of electronic power converters,” Ph. D. dissertation, Chalmers Univ. of Tech, Gothenburg, Sweden, 1988. When d z  is 0.5, both zero vectors are used the same time in a switching period. It should be noted, that in the above equation (1) the relative duty cycle of zero vector 111 is presented. In similar manner the equation could be written for zero vector 000. The fact that the relative duty cycle is ramped from 0 to 0.5 means also that the relative duty cycle of the other zero vector is simultaneously ramped from 1 to 0.5, since the sum of the relative duty cycles of different zero vectors is 1.  
         [0019]     The starting algorithm can be implemented, for example, in the following way in connection with common suboscillation pulse width modulation.  FIG. 3  illustrates a triangle-intersection technique with zero-sequence signal injection. The triangle-intersection technique is well known as such. The inputs to the modulator are the scaled voltage reference signals  
                 s   x     =       2   ⁢     u   x   *         u   dc         ,     x   =   a     ,   b   ,   c           (   2   )             
 
         [0020]     where u x * is the reference phase voltage and u dc  is the dc-link voltage. The scaling scales the phase voltages to be in the range of −1 to 1. The peak-to-peak amplitude of the triangle carrier signal is 2. The outputs of the modulator are the switching states for each phase S a , S b , S c , which means that the output switches are controlled according to these switching states.  
         [0021]     The zero-sequence signal s 0  can be calculated from d z  and the scaled voltage reference signals as 
 
 s   0 =2 d   z −1− d   z max( s   a   , s   b   , s   c )+( d   z −1)min( s   a   , s   b   , s   c )   (3) 
 
         [0022]     The zero-sequence signal is added to each scaled voltage reference signal. When a zero sequence signal is added in the above manner, the phase-to-phase voltages are not affected. Thus when a three-phase motor is controlled, the motor sees no difference when a zero sequence signal is added.  
         [0023]     The equation (3) is based on the principles of symmetrical suboscillation, which is disclosed in T. Svensson, “On modulation and control of electronic power converters,” Ph. D. dissertation, Chalmers Univ. of Tech, Gothenburg, Sweden, 1988. The equation (3) takes into account the changing relative duty cycle d z  and the minimum and maximum values of scaled voltage references.  
         [0024]     In  FIG. 4   a ) suboscillation i.e. sine-triangle comparison is used and the upper plot shows the scaled reference voltages s a , s b , s c  and the triangle carrier. The lower plots show the switching states S a , S b , S c  for each phase.  
         [0025]     In  FIG. 4   b ) symmetrical suboscillation is used, where a zero-sequence signal is added to the scaled voltage references, and the modulation is done with the modified voltage references s′ a , s′ b , s′ c . Similarly lower plots present the switching states. Both switching states of  FIGS. 4   a ) and  4   b ) produce the same voltage vector. Thus the voltage is not affected.  FIGS. 4   a ) and  4   b ) are presented to understand the meaning of the symmetrical suboscillation. The lower plots of  FIG. 4   b ) are obtained by adding to the scaled voltage references a zero sequence signal calculated as  
               s   0     =           -     min   ⁡     (     sa   ,   sb   ,   sc     )         -     max   ⁡     (     sa   ,   sb   ,   sc     )         2     .             (   4   )             
 
 The minimum and maximum are taken account to ensure that the modified voltage references s′ a , s′ b , s′ c  stay in the range of the triangle carrier. 
 
         [0026]      FIG. 5  shows switching states for the same voltage vector when equation (3) is used to calculate the zero-sequence signal and the value of d z  is changed. When d z  is 0, only one zero vector is used. Similarly when d z  is 1 the other zero vector is used. The situation where d z  is 0.5 corresponds to symmetrical suboscillation, where the zero vectors are used equally.  
         [0027]     In connection with a space vector PWM the method of the invention can be used in a following way. In normal space vector PWM the active times for switches can be calculated as  
                 t   1     =       T   s     ⁢            U   _     ref          ⁢       3       u   d       ⁢     sin   ⁡     (       π   3     -   α     )           ⁢     
     ⁢       t   2     =       T   s     ⁢            U   _     ref          ⁢       3       u   d       ⁢     sin   ⁡     (   α   )           ⁢     
     ⁢       t   0     =       T   s     -     t   1     -     t   2                 (   5   )             
 
         [0028]     where t 1  and t 2  are the active times of active vectors and to is the active time for zero vectors, T s  is the modulation period, U ref  is the reference voltage vector and α is the angle of the voltage vector. The traditional SVPWM presented in H. W. van der Broeck, H.-C. Skudelny, and G. V. Stanke, “Analysis and realization of a pulsewidth modulator based on voltage space vectors,”  IEEE Trans. Ind. Applicat.,  vol. 24, no. 1, pp. 142-150, January/February 1988 is achieved with the following switch sequence when the angle of the voltage vector is in the first sector, i.e. between voltage vectors U 1  and U 2 .  
                         U   _     0     ⁢     〈       t   0     4     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     1     ⁢     〈       t   1     2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     2     ⁢     〈       t   2     2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     7     ⁢     〈       t   0     4     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     7     ⁢     〈       t   0     4     〉     ⁢           ⁢   …                   U   _     2     ⁢     〈       t   2     2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     1     ⁢     〈       t   1     2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     0     ⁢     〈       t   0     4     〉               ︸     T   s               (   6   )             
 
         [0029]     In the method of the invention the switching times t 1 , t 2  and t 0  are as above. The relative active times of the zero vectors are changed according to the invention. By defining the active time of zero vector U 0  to be T 0−  in one modulation period. Correspondingly the active time of zero vector U 7  is then T 0+ . The relative duty cycle of zero vector U 0  is then  
               d   z     =         T     0   +           T     0   -       +     T     0   +           =         T     0   +         t   0       .               (   7   )             
 
         [0030]     By adapting the above we get implementation of the method of the invention in accordance with SVPWM and the switching sequence will be  
                     U   _     0     ⁢     〈         (     1   -     d   z       )     ⁢     t   0       2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     1     ⁢     〈       t   1     2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     2     ⁢     〈       t   2     2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     7     ⁢     〈         d   z     ⁢     t   0       2     〉     ⁢           ⁢   …     ⁢     
     ⁢         U   _     7     ⁢     〈         d   z     ⁢     t   0       2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     2     ⁢     〈       t   2     2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     1     ⁢     〈       t   1     2     〉     ⁢           ⁢   …   ⁢           ⁢       U   _     0     ⁢       〈         (     1   -     d   z       )     ⁢     t   0       2     〉     .         ⁢                   (   8   )             
 
         [0031]     The method of invention can thus be implemented in various PWM-methods.  
         [0032]      FIG. 2 ( b ) illustrates how the starting algorithm works. The CM voltage is abruptly set to its minimum value by selecting d z =0 at t=0 s. The ramping of the CM voltage is done by ramping d z  from 0 to 0.5 between t=0 . . . 20 ms. The severe oscillation is avoided. Only the first CM current peak (amplitude about 13 A) remains. A significant improvement is obtained at the start.  
         [0033]     It is obvious to a person skilled in the art that while technology advances, the basic idea of the invention can be implemented in many different ways. The invention and its embodiments are thus not restricted to the examples described above, but can vary within the scope of the claims.