Abstract:
This invention relates to a real time clock recovery circuit. The clock recovery circuit requires three inputs, a bit serial data received input (BSD), a quarter bit delayed (QBT) and a three quarter bit delayed (TQBT) signal. The three inputs are derived from a single raw input that becomes the received input (BSD) signal. QBT and TQBT are delay line versions of the BSD signal. The three inputs (BSD, QBT and TQBT, and the complement of these signals) are ANDed together to detect low frequencies. The generated signal indicative of the low frequency, QBT and TQBT generate a recovered clock by state sequencing of an R-S latch. The type of bit serial data stream which may be inputted to the circuit of the present invention is double frequency encoded data streams, including Manchester or diphase encoded.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to digital data transmission systems and more particularly, to a circuit for deriving timing signals from a serial digital data stream and a method therefor whereby the timing signals may be subsequently utilized by a receiver to decode and deserialize the received data stream. 
     In transmitting serial digital data, it is necessary to provide a series of clock pulses in addition to the data pulses in order to synchronize the coding of the transmitted serial digital data at a receiving terminal or the receiver. In prior-known transmitting schemes, two transmission lines or paths, or two channels were required for this purpose, one for the data signal and one for the clocking signal. In attempting to avoid the requirement for a dual transmission path (or two channels), self-clocking codes evolved as a result of combining the clock and data signals. The Manchester code is one such self-clocking code. Manchester encoders accept clock and data and combine them into a single output which may be transmitted by a single transmission line to the receiving terminal. When the self-clocking data (i.e., the serial digital data stream) arrives at the receiving terminal, it is processed by a decoder which extracts separately both data and clock from the input self-clocking code. 
     The clock recovery circuits of the prior art generally are formed by directing the serial digital data stream into AND or NAND gates causing a clock output, and when the conditions for setting disappear, the output resets. The circuit of the present invention requires a specific condition, or set of conditions, to set a latch and another condition, or set of conditions, to reset the latch yielding a symmetrical recovered clock. As a result of utilizing a latch requiring specific set conditions and specific reset conditions, there is provided by the circuit of the current invention a high-speed real time clock recovery circuit. In addition, the circuit of the current invention provides a significant desensitivity to delay line tap to tap variations and further yields a recovered clock symmetry that is less sensitive to the bit skew of the raw input serial digital data stream. Further, the circuit of the current invention generates a signal indicative of when a low frequency has occurred in the serial digital data stream, which signal is subsequently utilized in a data recovery circuit for Manchester code or diphase code. 
     SUMMARY OF THE INVENTION 
     Therefore, there is provided in the present invention, a clock recovery circuit having an input terminal adapted to receive a raw serial data stream having a defined bit time, the raw serial data stream being the resultant combination of a data signal and a clock signal. The clock recovery circuit comprises a signal generator which includes logic for shifting the raw serial data stream by one-quarter bit time thereby providing a second input signal. There is also included in the signal generator, logic for shifting the raw serial data stream by three-quarters of a bit time thereby providing a third input signal. Detecting logic is included for detecting transitions in the second input signal or the third input signal to provide an output signal having a transition occurring at each of the detected transitions, the output signal being the clock signal recovered from the raw serial data stream. 
     The detecting logic includes a latch having an output terminal for providing the output signal. A first signal is generated which indicates whether a low frequency of the input signal has occurred during the bit time just about to expire. The detecting logic further includes a plurality of NOR-gates for triggering the latch. The plurality of NOR-gates generates a trigger signal upon detection of a transition in the second input signal or in the third input signal, thereby causing a transition in the output signal of said latch, the output signal being the clock signal. 
     A method for recovering the clock signal comprises the steps of deriving a shaped serial data stream from a raw serial data stream thereby providing a first input signal. Then the first input signal is shifted by one-quarter bit time thereby providing a second input signal. The first input signal is also shifted by three-quarters of a bit time thereby providing a third input signal. Transitions are then detected in the second input signal or the third input signal to provide an output signal having a transition occurring at each of the detected transitions, the output signal being the clock signal recovered from the raw serial data stream. 
     From the foregoing, it can be seen that it is a primary object of the present invention to provide a novel clock recovery circuit. 
     It is another object of the present invention to provide a novel clock recovery circuit utilizing an input serial digital data stream being of the double frequency encoded data type. 
     It is yet another object of the present invention to provide a clock recovery circuit that is less sensitive to bit skewing of the raw input serial digital data stream. 
     It is still another object of the present invention to provide a clock recovery circuit which is insensitive to relatively high amounts of bit distortion. 
     It is still a further object of the present invention to provide a clock recovery circuit which provides a very fast clock recovery resolution for any technology. 
     It is still a further object of the present invention to provide a clock recovery circuit which provides a recovered clock signal which is highly symmetrical. 
     These and other objects of the present invention will become more apparent when taken in conjunction with the following description, and attached drawings, wherein like characters indicate like parts and which drawings form a part of the present application. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the clock recovery circuit of the present invention; 
     FIG. 2 is a logic diagram of the preferred embodiment of the last low frequency generator circuit utilized in the clock recovery circuit of the present invention; 
     FIG. 3 is a timing diagram of specified signals inputted to, and generated by, the clock recovery circuit of the present invention; and 
     FIG. 4 is a logic diagram of the preferred embodiment of the latch triggering logic and latch circuits. 
    
    
     DETAILED DESCRIPTION 
     The clock recovery circuit of the present invention is shown in block diagram form in FIG. 1. The clock signal (RF) is recovered from a serial digital data stream as the output of a latch 1. 
     Within a receiving terminal there is included within the clock recovery circuit of the present invention, a signal generator 4 which generates three digital signals and their respective complement (or bar) signals, these digital signals being derived from a raw serial data input signal which combines the data and clock signals. The digital signals comprise the bit serial data signal (BSD) which is a demodulated, shaped, version of the raw serial data input signal using regeneration techniques well known in the art, the quarter bit time signal (QBT) which is a version of BSD delayed by a quarter of a bit time, the three-quarter bit time signal (TQBT) which is a version of BSD delayed by three-quarters of a bit time, and the respective complement or inverted signals BSD, QBT, and TQBT (the inverted signals also denoted herein by a slash following the signal designation, e.g. BSD/, QBT/, and TQBT/). Techniques for generating the digital signals and the respective complement signals are well known in the art; hence, the signal generator 4 will not be discussed further herein. In order to achieve the high speed of operation (i.e., data rates in the order of 24 MHz. which, due to the double frequency encoding, can result in pulse widths in the order of 15 ns), the respective complement signals must be symmetrical in time in order to avoid glitches in the clock. That is, when the QBT signal starts going high, QBT starts going low within approximately 1 ns, i.e. less than one gate delay. The same symmetry also applies in the opposite direction for the QBT signal, and also for the TQBT signal. The digital signals BSD, BSD, QBT, QBT, TQBT, and TQBT are inputted to a last low frequency (LLF) generator 3, together with the complement of the recovered clock signal RFx/. The output of LLF generator 3 is the last low frequency (LLF) signal and its complement signal LLF. The LLF signal indicates, by a change of state, when a low frequency of the BSD signal has occurred within a bit time. The operation of LLF generator 3 will be described in further detail hereinunder. The LLF signal is also applicable for and facilitates the decoding of, an inputted serial digital data stream coded in either Manchester code or diphase code. In such an application, the LLF signal can then be transmitted to the data recovery circuits (not shown) within the receiving subsystem in order to recover the data. The latch 1 is set or reset by the output of latch triggering logic 2. Digital signals QBT, QBT, TQBT, and TQBT are combined by latch triggering logic 2 with the LLF and LLF signals, and the complement of the recovered clock RFx/, for generating the set and reset signals of latch 1. The operation of the latch triggering logic 2 will be explained in detail hereinunder. 
     The LLF signal is derived by the last low frequency generator 3 and will be described in conjunction with FIGS. 2 and 3. The last low frequency generator 3 combines the BSD and BSD signals with the QBT and TQBT signals and their complement signals simultaneously while the recovered clock RF is a logic one (high). The last low frequency generator 3 of the preferred embodiment is shown in FIG. 2. An LLF latch 31 is set and reset in accordance with the following equations: 
     
         LLF=RFx/·(BSD·QBT·TQBT) 
    
     
         LLF=RFx/·(BSD·QBT·TQBT) 
    
     When the signals BSD, QBT are a logic one (high), and RFx/ is a logic zero (low), the output of NOR-gate 32 is a logic zero (or low). Inverter 33 will invert the output of NOR-gate 32 resulting in a logic one input to NOR-gate 34. When the TQBT signal is low, the output of NOR-gate 34 is low, the LLF latch 31 being reset, i.e. LLF=0, due to LLF/ being high. At the same time, the QBT and BSD inputs to NOR-gate 36 are low, the RFx/ signal still is low, which results in the output of NOR-gate 36 being a logic one; hence, the output of inverter 37 and the input to NOR-gate 38 is low. Since TQBT is low, TQBT is high, yielding a low output from NOR-gate 38. This condition is shown in FIG. 3 just prior to time T 1 . At time T 1 , TQBT goes high and TQBT goes low. This results in the output of NOR-gate 38 going high, causing LLF/ to go low and LLF to go high, thereby setting LLF latch 31. As can be seen from the above condition, NOR-gates 32 and 34 together with inverter 33 yield the resultant AND function for the TQBT, QBT and BSD signals for setting LLF latch 31, and NOR-gates 36 and 38 together with inverter 37 give the AND function for the TQBT, QBT, and BSD signals for resetting the LLF latch 31. The setting and resetting of LLF latch 31 is performed in accordance with the above equations, the conditions being satisfied at discrete times T 1  through T 6  as shown in FIG. 3. 
     An examination of the waveforms of FIG. 3 shows the BSD waveform having a low frequency during bit times 1, 4, 5, 7, 9 and 10. A low frequency is said to occur when, at the three-quarter bit time mark, no change of state of the BSD signal has occurred during that bit time period. LLF transitions therefore occur during the corresponding bit times. This is shown by the LLF waveform at times T 1 , T 2 , T 3 , T 4 , T 5 , and T 6  and is consistent with the above equations. Every change in the state of LLF indicates a low frequency of the data has occurred in the current bit time, the LLF signal making a transition at the three-quarter point within the bit time. 
     The latch 1 and latch triggering logic 2 will now be described in conjunction with FIGS. 3 and 4. The latch 1 and latch triggering logic 2 of the preferred embodiment is shown in FIG. 4. The latch 1 is an R-S latch comprised of NOR-gates 11 and 12 in a cross-coupled configuration. The output of NOR-gate 11 is inverted by inverter 13, the output of inverter 13 being the recovered clock signal, RF. The output of NOR gate 12 is fed through a NOR-gate 14, the output of NOR-gate 14 being the inverted recovery clock signal RFx/, the x denoting a slight delay from the RF clock signal. The RESET input to NOR-gate 14 is low in normal operation, (a logic zero), thereby enabling NOR-gate 14 for the normal clock recovery function. 
     The latch triggering logic 2 is comprised of NOR-gate 21 through NOR-gate 26. The outputs of NOR-gates 21, 22 are coupled to the inputs of NOR-gate 11 for providing a set signal of latch 1. The output of NOR-gates 23, 24, 25, 26 are coupled to NOR-gate 12 for providing a reset signal for latch 1. The latch 1 is set and reset by the combined LLF, QBT and TQBT signals and their inverted signals by NOR-gate 21 through NOR-gate 24. A change of state in the LLF signal while RF is high forces RF low. This function is accomplished by NOR-gates 25, 26. 
     The setting and resetting of latch 1 is performed by the NOR-gate 21 through NOR-gate 26 in accordance with the equations set forth in Table 1. 
     
                       TABLE 1______________________________________               TIME OCCURRENCEEQUATION            SHOWN IN FIG. 3______________________________________ 1. ##STR1##           T.sub.A 2. ##STR2##           T.sub.C, T.sub.E, T.sub.G 3. ##STR3##           T.sub.I 4. ##STR4##           T.sub.D, T.sub.F 5. ##STR5##           T.sub.H 6. ##STR6##           T.sub.B______________________________________ 
    
     Table 1 correlates all the combinations of the set-reset conditions with a time occurrence T A  through T I  shown in FIG. 3. For example, equation 1 in Table 1 specifies the RF signal will be high (i.e., the latch 1 will be set) when QBT is high, and TQBT and LLF are low. Referring to FIG. 3, just prior in time to T A  at time T A  &#39;, QBT, TQBT, and LLF are low, yielding RF low. At time T A , QBT has gone high resulting in RF going high. Examination of the waveforms of FIG. 3 can be similarly performed to correlate the condition of the signals at times T B  through T I  with the equations of Table 1. Further, the set-reset of latch 1 for times not specifically delineated between times T H  and T I  can be correlated to one of the equations of Table 1. 
     By further examination of the waveforms of FIG. 3, it will be obvious to one skilled in the art that due to the quarter bit time and three-quarter bit time delay utilized in the generation of the recovered clock signal by the present invention, the maximum amount of bit distortion allowable in the serial digital data input is in a range of +25% to -25% of a bit time. Although the above discussion is specifically directed to Manchester encoded data, it will be recognized by those skilled in the art that the circuit of the present invention is applicable to double frequency encoded data streams, including Manchester and diphase encoded data streams. 
     While there has been shown what is considered to be the preferred embodiment of the invention, it will be manifest that many changes and modifications can be made therein without departing from the essential spirit and scope of the invention. It is intended, therefore, in the annexed claims, to cover all such changes and modifications which fall within the true scope of the invention.