Abstract:
A method and apparatus are disclosed for enhancing the pipeline instruction transfer and execution performance of a computer architecture by reducing instruction stalls due to branch and jump instructions. Trace cache within a computer architecture is used to receive computer instructions at a first rate and to store the computer instructions as traces of instructions. An instruction execution pipeline is also provided to receive, decode, and execute the computer instructions at a second rate that is less than the first rate. A mux is also provided between the trace cache and the instruction execution pipeline to select a next instruction to be loaded into the instruction execution pipeline from the trace cache based, in part, on a branch result fed back to the mux from the instruction execution pipeline.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE 
   This application also makes reference to, claims priority to and claims the benefit of U.S. provisional patent application serial No. 60/422,149 filed on Oct. 29, 2002. 

   BACKGROUND OF THE INVENTION 
   In modern computer architectures, trace cache is often used to attempt to reduce branch penalty cycles caused by a mis-prediction of branch instructions and to de-couple the latency associated with any unconditional jumps. 
   Trace cache is typically used to store traces of instructions to be executed, one after another, in a pipelined instruction execution architecture. Different traces may correspond to different possible sequences of instructions that may or may not be executed depending on conditional outcomes of certain instructions such as branch instructions or outcomes of unconditional jump instructions. 
   A branch instruction is a computer instruction that may have two possible outcomes. The two outcomes are branch or don&#39;t branch. When the result of a branch instruction is to branch, then the instruction architecture abandons the current instruction sequence and branches to a different instruction sequence. When the result is not to branch, the instruction architecture stays on the same instruction sequence path. 
   In the case of an unconditional jump instruction, when the jump instruction is executed, the instruction architecture always jumps to the new instruction sequence associated with the jump instruction. 
   In either case, conditional branch or unconditional jump, delays may be encountered in the instruction execution pipeline if the computer architecture must go further back in the instruction pipeline to access the next sequence of instructions to branch to or jump to. These delays effectively cause stalls in the instruction execution pipeline while the instruction execution pipeline waits for the next correct instruction to be loaded into its instruction register. 
   In a typical instruction pipeline within a computer architecture, an instruction cache grabs computer instructions from a memory. The instruction cache may feed individual instructions into an instruction register or may feed a trace cache to build up traces of instructions within the trace cache. Once an instruction is loaded into an instruction register, it is decoded and executed using associated data loaded into a data register for that instruction. The result of the executed instruction is written back to a register. 
   A typical instruction pipeline in a computer architecture may use a branch predictor to attempt to predict the outcome of a branch instruction based on a trace history built up in trace cache. Prediction accuracies of 90% or better may be achieved. However, for those instances when the branch prediction is incorrect, additional delays and stalls may be experienced. 
   Research with respect to trace cache has focused on various implementation details such as how to construct continuous traces, using single or multiple branch predictors to improve the trace cache performance, and filling algorithms for loading the trace cache. Also, instead of constructing multiple branch predictors, multiple branches of traces may be constructed in trace cache. 
   The circuit delay associated with a branch mis-prediction may then be reduced by going back only to trace cache and accessing the correct trace instead of suffering additional delays by having to go back to the instruction cache or the memory. The only delay suffered is then just that associated with the mis-prediction into trace cache. Therefore, by constructing parallel branches of traces in trace cache, the circuit delay from making the branch decision to the instruction fetch may be reduced. However, instruction execution pipeline stalls may still occur with such a configuration (when the branch prediction is incorrect). 
   It is desirable to further reduce the chance of delays and stalls occurring in the instruction execution pipeline of a computer architecture. It is also desirable to eliminate the branch predictor altogether such that only correct instructions/traces are loaded into the instruction execution pipeline. 
   Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings. 
   BRIEF SUMMARY OF THE INVENTION 
   Certain embodiments of the present invention provide a method and apparatus to enhance the performance of a computer architecture. In particular, certain embodiments provide for reducing instruction execution pipeline stalls due to branch instructions and jump instructions executed by the computer architecture. 
   A method of the present invention provides an instruction transfer bandwidth between an instruction cache and a trace cache within a computer architecture that is greater than an instruction execution bandwidth of the computer architecture. Results of executed branch instructions are fed back and used along with the instruction transfer bandwidth to feed correct instructions into the instruction execution pipeline of the computer architecture such that the chance of an instruction execution stall occurring within the instruction execution pipeline is greatly reduced. 
   Apparatus of the present invention provides a trace cache within a computer architecture to receive computer instructions at a first rate and to store the computer instructions as traces of instructions. An instruction execution pipeline is also provided to receive, decode, and execute the computer instructions at a second rate that is less than the first rate. A mux is also provided between the trace cache and the instruction execution pipeline to select a next instruction to be loaded into the instruction execution pipeline from the trace cache based, in part, on a branch result fed back to the mux from the instruction execution pipeline. 
   Certain embodiments of the present invention afford an approach to reduce the occurrence of stalls in an instruction execution pipeline in a computer architecture by enhancing the pipelined instruction transfer bandwidth with respect to the instruction execution bandwidth and by using trace cache to store instructions corresponding to the results of branch and jump instructions before the branch and jump instructions are executed. 
   These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic block diagram of an instruction pipeline in a computer architecture in accordance with an embodiment of the present invention. 
       FIG. 2  is a more detailed schematic block diagram of a portion of the instruction pipeline of  FIG. 1  in accordance with an embodiment of the present invention. 
       FIG. 3  is a schematic diagram of a trace fifo used in the instruction pipeline of  FIG. 1  and  FIG. 2  in accordance with an embodiment of the present invention. 
       FIG. 4  is an illustration of several possible options for achieving an enhanced data transfer rate between instruction cache and trace cache in the instruction pipeline of  FIG. 1  in accordance with possible embodiments of the present invention. 
       FIG. 5  is an exemplary illustration of a program counter sequence with a branch instruction and comprising three traces of instructions in accordance with an embodiment of the present invention. 
       FIG. 6  is an exemplary illustration of an ideal instruction sequence with branch instructions and a single branch delay slot in accordance with an embodiment of the present invention. 
       FIG. 7  is an exemplary illustration of several possible sequences of instructions with branch instructions over eight clock cycles in accordance with an embodiment of the present invention. 
       FIG. 8  is an exemplary illustration of executing a particular path through the sequence of instructions of  FIG. 7  using the instruction pipeline of  FIG. 2  in accordance with an embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  is a schematic block diagram of an instruction pipeline  5  in a computer architecture in accordance with an embodiment of the present invention. The instruction pipeline  5  comprises a memory  10 , an instruction cache  20 , a trace cache  30 , an instruction register  40 , an instruction decoder  50 , a data register  60 , an instruction executor  70 , and a results register  80 . 
   During operation of the instruction pipeline  5  in accordance with an embodiment of the present invention, computer instructions are loaded from memory  10  into instruction cache  20  at a first data rate of 1×. The computer instructions are loaded from instruction cache  20  into trace cache  30  at a second higher data rate of 2× (twice the 1× data rate). The instructions are loaded from trace cache  30  into instruction register  40  at the 1× data rate. Therefore, the instruction transfer bandwidth of trace cache  30  is twice that of the rest of the pipeline. This means that, for every instruction that enters the instruction register  40  to be executed, the trace cache  30  may be loaded with two new instructions from instruction cache  20 . 
   Once an instruction is loaded into instruction register  40 , it is sent to instruction decoder  50  to be decoded. Data that is associated with the decoded instruction is loaded into data register  60  and then the decoded instruction and data are executed together in instruction executor  70 . When an instruction is executed, the result is written to results register  80 . 
   For example, if an instruction to be executed is “ADD R 1 , R 2 ”, then the instruction register  40  would be loaded with the “ADD” instruction and decoded by instruction decoder  50 . Data register  60  would be loaded with data values R 1  and R 2 . The instruction executor  70  would perform the operation “R 1 +R 2 ” and the result would be written to results register  80 . 
     FIG. 2  is a more detailed schematic block diagram of a portion of the instruction pipeline of  FIG. 1  in accordance with an embodiment of the present invention. Trace cache  30  may store multiple traces (e.g. trace  1  to trace  128 ). Instruction execution pipeline  90  is a portion of the instruction pipeline comprising instruction register  40 , instruction decoder  50 , and instruction executor  70  (In  FIG. 2 , instruction executor  70  is assumed to incorporate data register  60  and results register  80 ). A mux  35  interfaces trace cache  30  to instruction execution pipeline  90 . In  FIG. 1 , the mux  35  is not explicitly shown. 
   Trace cache  30  stores multiple traces in trace FIFO&#39;s.  FIG. 3  is an exemplary illustration of a trace FIFO  100  in accordance with an embodiment of the present invention. The trace FIFO  100  stores multiple computer instructions at various instruction indexes (e.g. instruction index  110 ) within the FIFO  100 . A particular string of instructions may form a trace  34  within the trace FIFO  100  over a number of instruction indexes. In  FIG. 3 , trace FIFO  100  includes 128 (0 to 127) instruction indexes and may, therefore, store up to 128 computer instructions. 
   The various traces that are stored in trace cache  20  are built up over time as the instruction pipeline is in operation. Traces are constructed within trace cache  30  according to the programmed instruction sequences and a set of rules that govern how to load trace cache from instruction cache when conditional branch instructions and unconditional jump instructions are encountered. In an embodiment of the present invention, trace cache  30  is managed by a free list manager (not shown) and a trace FIFO manager (not shown) in order to free up any unused traces and/or instruction indexes and load new traces or individual instructions in the freed up locations. 
   The instruction transfer bandwidth of the trace cache  30  is greater than the instruction execution bandwidth of the instruction execution pipeline  90  and the overall instruction pipeline  5 . In an embodiment of the present invention, two instructions may be loaded into trace cache for a single clock cycle of the instruction pipeline whereas only one instruction is loaded from memory  10  to instruction cache  20  during a single clock cycle and only one instruction is clocked through each stage of the instruction execution pipeline  90  for each clock cycle. 
     FIG. 4  is an illustration of several possible options for achieving an enhanced data transfer rate (bandwidth) between instruction cache and trace cache in the instruction pipeline of  FIG. 1  in accordance with possible embodiments of the present invention. In option A  21 , two hardware ports may be used between instruction cache  20  and trace cache  30 . Each port is able to handle one 32-bit instruction. The configuration is able to grab any two instructions from instruction cache  20  and transfer the two instructions to trace cache  30  within one clock cycle. 
   Option B  22  and option C  23  each use one hardware port to transfer two 32-bit instructions in one clock cycle. In the case of option B  22 , two sequenced 32-bit words may be transferred at one time corresponding to two successive address locations within instruction cache  20 . For example, address  0  and address  1  may be transferred within one clock cycle and address  2  and address  3  may be transferred within the next clock cycle. However, address  1  and address  2  may not be transferred together within the same clock cycle in the option B configuration. Option A  21  would allow address  1  and address  2  to be transferred within the same clock cycle using the two ports. 
   Option C  23  relies on arranging addresses in an even and odd configuration and requiring that, during a given clock cycle, one even and one odd instruction be transferred. As a result, address  0  (even) and address  1  (odd) may be transferred together, address  2  (even) and address  3  (odd) may be transferred together, and address  1  (odd) and address  2  (even) may be transferred together. Option C  23 , like option B  22  uses only one hardware port and, therefore, requires less hardware than Option A  21 . 
   Therefore, it may be seen that options A, B, and C each allow two instructions to be transferred from instruction cache  20  to trace cache  30  within one clock cycle, resulting in an instruction transfer bandwidth between the two caches that is twice the overall instruction pipeline bandwidth. However, each option requires making different tradeoffs between configuration complexity and flexibility of instruction transfers. 
     FIG. 5  is an exemplary illustration of a program counter sequence with a branch instruction and comprising three traces of instructions in accordance with an embodiment of the present invention. When the program counter of the computer architecture gets to PC  2 , a branch instruction is encountered. Depending on the result of the branch instruction, the program counter will either go next to PC  3  (no branching) and the next instruction (instr  3 ) will be executed, or the program counter will branch to PC  4 , skipping instr  3  and executing instr  4 . 
   The possible sequences of instructions may be represented in trace cache as three separate traces (trace  1 , trace  2 , and trace  3 ) as shown in  FIG. 5 . Trace  1  is executed through and including the branch instruction at PC  2 . If the result of the branch instruction is to branch, then trace  2  is loaded from trace cache  30  into the instruction execution pipeline  90  where instructions  4  and  5  are executed next. If the result of the branch instruction is not to branch, then trace  3  is loaded from trace cache  30  into instruction execution pipeline  90  where instructions  3 ,  4 , and  5  are executed next. 
   Again,  FIG. 5  is an ideal illustration that assumes that, after a branch instruction is executed, the next instruction that is executed is based on the result of the branch instruction. However, in a real pipelined architecture, branch delay slots are often used to prevent stalls of the instruction execution pipeline. When branch delay slots are used, the next instruction executed after a branch instruction is not necessarily the result of the branch instruction. For example, for a single branch delay slot implementation, the instruction in the sequence immediately after the branch instruction will always be executed, whether or not the result of the branch instruction is to branch or not. 
   Referring again to  FIG. 2 , in an embodiment of the present invention, a current pointer  31  points to the current trace of instructions that is being fed into instruction execution pipeline  90 . When a branch instruction enters instruction execution pipeline  90 , a branch pointer points to a branch trace  32  corresponding to the branch instruction. When the branch instruction is executed by instruction executor  70 , the result of the branch instruction  36  is fed back to the mux  35 . Flip flops or memory  33  contain the next instruction corresponding to the current pointer  31  and the next instruction corresponding to the branch pointer  32 . The fed back branch result  36  selects the next instruction to load through the mux  35  into instruction register  40 . 
   If the result of the branch instruction is not to branch, then the next instruction that is loaded is the next instruction in the trace that the current pointer  31  is pointing to. If the result of the branch instruction is to branch, then the next instruction that is loaded is the next instruction in the trace that the branch pointer  32  is pointing to. 
   As a result, only correct next instructions are ever loaded into the instruction register  40  of the instruction execution pipeline  90 . The increased instruction transfer bandwidth into trace cache  30  ensures that both instruction options corresponding to branching or not branching are both present in trace cache before the branch instruction is actually executed. Therefore, no branch predictors are needed and the computer architecture generally does not ever have to go further back in the instruction pipeline architecture further than trace cache to get the next correct instruction to be executed. As a result, the possibility of a stall in the instruction execution pipeline due to a branch instruction is reduced. Similarly, for an unconditional jump instruction, when the unconditional jump instruction is loaded into instruction register  40 , trace cache is loaded with the trace corresponding to the jump instruction before the jump instruction is executed by the instruction executor  70 . 
     FIG. 6  illustrates a sequence of even and odd instructions. In an ideal scenario, when A* 0 , a branch instruction, is loaded into instruction register  40 , trace cache  30  is loaded with instructions C* 0  and C* 1 . C* 0  and C* 1  are the possible outcome instructions of branch instruction A* 0 . Instruction B 0  is a single branch delay instruction that is executed in the instruction execution pipeline before either C* 0  or C* 1  are executed. As a result, after A* 0  is executed in instruction executor  70 , B 0  is then decoded and loaded into the instruction executor  70  to be executed and either C* 0  or C* 1  may be loaded into the instruction register  40  based on the outcome of the branch instruction A* 0 . 
   Depending on the configuration of the interface between the instruction cache  20  and trace cache  30  (see  FIG. 4 ), however, instructions C* 0  and C* 1  may not be able to be loaded into trace cache  30  at the same time (i.e. in a single clock cycle) if they do not correspond to sequential address locations within instruction cache  20 . Option B  22  of  FIG. 4 , for example, may preclude the loading of C* 0  and C* 1  at the same time. 
     FIG. 7  and  FIG. 8  illustrate a sequence of events in an instruction pipeline in accordance with an embodiment of the present invention where, for example, C* 0  and C* 1  may not be loaded into trace cache at the same time.  FIG. 7  shows a set of possible sequences of instruction paths that may be taken over eight clock cycles.  FIG. 8  illustrates one such possible path taken and how the various instructions are loaded into trace cache  30  and piped through the instruction execution pipeline  90  in accordance with an embodiment of the present invention. As may be seen in  FIG. 2 , the instructions are piped through the instruction execution pipeline as 32-bit words  45  and  55  according to an embodiment of the present invention. 
   The example starts off with B 0 , C* 0 , and D 0  loaded into trace cache  30  from instruction cache  20  when branch instruction A* 0  is loaded into instruction register  40  during clock cycle  1  as shown in  FIG. 8 . C* 0  and C* 1  are the possible next instructions to be executed as a result of branch instruction A* 0 . 
   In clock cycle  2 , A* 0  is decoded in instruction decoder  50  and B 0  is loaded into instruction register  40  since B 0  is a branch delay slot instruction and must be executed before either C* 0  or C* 1 . Also in clock cycle  2 , C* 1  and D 1  are loaded into trace cache  30  from instruction cache  20 . In the example of  FIG. 8 , it is assumed that C* 0  and C* 1  are even instructions but are not in sequential address locations. Also, it is assumed that D 0  and D 1  are odd instructions but are not in sequential address locations. It is assumed that C* 0  and D 0  are in sequential address locations and C* 1  and D 1  are in sequential address locations. 
   In clock cycle  3 , A* 0  is executed in instruction executor  70 , B 0  is decoded in instruction decoder  50 , and C* 1  is loaded into instruction register  40  from trace cache  30 . In this example, C* 1  was the result of the branch instruction A* 0  and was selected by feedback signal  36  through mux  35 . Also in clock cycle  3 , E* 1  and F 1  are loaded into trace cache. 
   Continuing with the example of  FIG. 8 , in clock cycle  4 , B o  is executed, C* 1  is decoded, and D 1  is loaded from trace cache  30  into instruction register  40  since D 1  is a branch delay slot instruction that must be executed before either E* 1  or E* 3 , the possible outcomes of branch instruction C* 1 , are executed. Also in clock cycle  4 , E* 3  and F 3  are loaded into trace cache  30 . 
   In clock cycle  5 , C* 1  is executed, D 1  is decoded, and E* 1  (the result of branch instruction C* 1  in this example) is loaded into instruction register  40 , again selected with the feedback signal  36  through the mux  35 . Also in clock cycle  5 , G 1  and H 1  are loaded into trace cache. 
   In clock cycle  6 , D 1  is executed, E* 1  is decoded, F 1  is loaded into instruction register  40  since F 1  is a branch delay slot instruction and must be executed after branch instruction E* 1 . Also in clock cycle  6 , G 4  and H 4  or loaded into trace cache. 
   In clock cycle  7 , E* 1  is executed, F 1  is decoded, and G 4  is loaded into instruction register  40 . It is assumed in the example that G 4  is the result of branch instruction E* 1 . 
   It may be seen from the following example that the next correct instruction that needs to be loaded into instruction register  40  is always available from trace cache  30  during the appropriate clock cycle. The computer architecture generally does not have to wait to go back to instruction cache  20  or memory  10  in order to retrieve a next instruction to be put into the instruction execution pipeline. As a result, the occurrence of instruction stalls in the instruction execution pipeline  90  are greatly reduced if not totally eliminated. 
   Other embodiments of the present invention are not restricted to a single branch delay slot or to an instruction transfer bandwidth that is only double that of the overall instruction pipeline bandwidth. For example, one embodiment could load trace cache with three instructions in a single clock cycle even though only one instruction is actually executed in a single clock cycle. 
   The various elements of the instruction pipeline  5  may be combined or separated according to various embodiments of the present invention. For example, data register  60  and results register  80  may be integrated into instruction executor  70 . Also, mux  35  could be integrated into instruction execution pipeline  90 . 
   In summary, certain embodiments of the present invention afford an approach to reduce instruction pipeline stalls in a computer architecture due to branch and jump instructions. The occurrence of instruction execution pipeline stalls are reduced by enhancing the pipelined instruction transfer bandwidth with respect to the instruction execution bandwidth and by storing all possible instruction outcomes, associated with any particular branch or jump, in trace memory before execution of the particular branch or jump instruction. 
   While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.