Abstract:
A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source region and an elevated drain region. The method includes providing an amorphous semiconductor material and crystallizing the amorphous semiconductor material without damaging a high-k gate dielectric layer. The semiconductor material can be silicided. A shallow source drain implant can also be provide.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This patent application is related to U.S. application Ser. No. 09/405,831, filed on Sep. 9, 1999, by Yu, entitled “A Process for Manufacturing MOS Transistors Having Elevated Source and Drain Regions,” U.S. application Ser. No. 09/255,546, filed on Feb. 22, 1999, by Yu entitled “Locally Confined Deep Pocket Process for ULSI MOSFETS,” U.S. application Ser. No. 09/397,217 filed on Sep. 16, 1999 by Yu et al. entitled “Source/Drain Doping Technique for Ultra-Thin-Body SOI MOS Transistors,” and U.S. application Ser. No. 09/384,121 filed on Aug. 27, 1999, by Yu entitled “CMOS Transistors Fabricated in Optimized RTA Scheme.” This patent application is also related to U.S. application Ser. No. 09/609,613 filed on Jul. 5, 2000 herewith by Yu entitled “A Process for Manufacturing MOS Transistors having Elevated Source and Drain Regions.” This patent application is also related to U.S. patent application Ser. No. 09/781,039, filed on an even date herewith by Yu, entitled “Low Temperature Process to Locally High-K Gate Dielectric,” U.S. patent application Ser. No. 09/779,985, filed on an even date herewith by Yu, entitled “Replacement Gate Process for Transistor Having Elevated Source and Drain,” U.S. patent application Ser. No. 09/780,043, filed on an even date herewith by Yu, entitled “Fully Depleted SOI Transistor with Elevated Source and Drain,” U.S. patent application Ser. No. 09/779,988, filed on an even date herewith by Yu, entitled “Low Temperature Process for Transistors with Elevated Source and Drain,” and U.S. patent application Ser. No. 09/779,986, filed on an even date herewith by Yu, entitled “A Low Temperature Process For A Thin Film Fully Depleted SOI MOSFET.” All of the above patent applications are assigned to the assignee of the present application. 
    
    
     BACKGROUND OF THE INVENTION 
     The present application relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present application relates to a method of manufacturing integrated circuits having transistors with elevated source and drain regions and high-k gate dielectrics. 
     Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. An ultra-large scale integrated circuit can include over 1 million transistors. 
     The ULSI circuit can include CMOS field effect transistors (FETS) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous). 
     The drain and source regions generally include a thin extension (shallow source and drain extensions) that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller. 
     Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions. 
     After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking capability of the silicon dioxide spacers. 
     As the size of transistors disposed on ICs decreases, transistors with shallow and ultra-shallow source/drain extensions become more difficult to manufacture. For example, a small transistor may require ultra-shallow source and drain extensions with a junction depth of less than 30 nanometer (nm). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically downward into the bulk semiconductor substrate. Also, conventional ion implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate. 
     The source region and drain regions can be raised by selective silicon (Si) epitaxy to make connections to source and drain contacts less difficult. The raised source and drain regions provide additional material for contact silicidation processes and reduce deep source/drain junction resistance and source/drain series resistance. However, the epitaxy process that forms the raised source and drain regions generally requires high temperatures exceeding 1000° C. (e.g., 1100-1200° C.). These high temperatures increase the thermal budget of the process and can adversely affect the formation of steep retrograde well regions and ultra shallow source/drain extensions. 
     The high temperatures, often referred to as a high thermal budget, can produce significant thermal diffusion which can cause shorts between the source and drain region (between the source/drain extensions). The potential for shorting between the source and drain region increases as gate lengths decrease. 
     In addition, high temperature processes over 750 to 800° C. can cause dielectric materials with a high dielectric constant (k) to react with the substrate (e.g., silicon). High-k (k&gt;8) gate dielectrics are desirable as critical transistor dimensions continue to decrease. The reduction of critical dimensions requires that the thickness of the gate oxide also be reduced. A major drawback to the decreased gate oxide thickness (e.g., &lt;30 Å) is that direct tunneling gate leakage current increases as gate oxide thickness decreases. To suppress gate leakage current, material with a high dielectric constant (k) can be used as a gate dielectric instead of the conventional gate oxides, such as thermally grown silicon dioxide. 
     High-k gate dielectric materials have advantages over conventional gate oxides. A high-k gate dielectric material with the same effective electrical thickness (same capacitive effect) as a thermal oxide is much thicker physically than the conventional oxide. Being thicker physically, the high-k dielectric gate insulator is less susceptible to direct tunnel leakage current. Tunnel leakage current is exponentially proportional to the gate dielectric thickness. Thus, using a high-k dielectric gate insulator significantly reduces the direct tunneling current flow through the gate insulator. 
     High-k materials include, for example, aluminum oxide (Al 2 O 3 ), titanium dioxide (TiO 2 ), and tantalum pentaoxide (TaO 5 ). Aluminum oxide has a dielectric constant (k) equal to eight (8) and is relatively easy to make as a gate insulator for a very small transistor. Small transistors often have a physical gate length of less than 80 nm. 
     Thus, there is a need for an integrated circuit or electronic device that includes transistors not susceptible to shorts caused by dopant thermal diffusion. Further still, there is a need for transistors with elevated source and drain regions manufactured in an optimized annealing process. Even further still, there is a need for elevated source and drain regions which are formed in a low thermal budget (low temperature) process. Yet further, there is a need for a transistor with elevated source and drain regions and a high-k gate dielectric. Yet even further, there is a need for a process of forming a transistor with elevated source and drain regions and a high-k gate dielectric in a low thermal budget process. 
     SUMMARY OF THE INVENTION 
     An exemplary embodiment relates to a method of manufacturing an integrated circuit. The integrated circuit includes a gate structure on a substrate. The substrate includes a shallow source extension and a shallow drain extension. The gate structure includes a gate conductor above a high-k gate dielectric. The method includes steps of: providing the gate structure on the substrate, forming a shallow amorphous region in the substrate, providing spacers on sidewalls of the gate structure, and etching the substrate to remove at least a portion of the shallow amorphous region. The method also includes steps of: providing an amorphous semiconductor layer above the substrate and over the gate structure, removing a portion of the amorphous semiconductor material to expose the gate structure, and forming a single crystalline semiconductor material from the amorphous semiconductor material and a remaining portion of the shallow amorphous region via a laser annealing process. 
     Another exemplary embodiment relates to a method of manufacturing an ultra-large scale integrated circuit including a transistor. The method includes providing a gate structure on a top surface of a substrate, providing a pair of spacers for the gate structure, depositing an amorphous semiconductor material above the top surface of the substrate, removing the amorphous semiconductor material to a level below a bottom surface of the cap layer, and crystallizing the amorphous semiconductor material. The gate structure includes a gate conductor and a cap layer. The amorphous semiconductor material is crystallized in an annealing process. The annealing process is prevented from overheating a high-k gate dielectric within the gate structure. 
     Yet another exemplary embodiment relates to a process of forming a transistor with elevated source and drain regions. The process includes providing a gate structure, providing an amorphization implant to a substrate, providing a spacer structure to the gate structure, depositing an amorphous semiconductor material above the substrate and the gate structure, and crystallizing the amorphous semiconductor material to form single crystalline material. The gate structure includes a high-k gate dielectric above the substrate. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Exemplary embodiments will hereafter be described with reference to the accompanying drawings, wherein like numerals denote like elements, and: 
     FIG. 1 is a cross-sectional view of a portion of an integrated circuit in accordance with an exemplary embodiment of the present invention, the integrated circuit including a transistor with elevated source and drain regions and a high-k gate dielectric; 
     FIG. 2 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1, showing a gate stack formation step, a shallow amorphization implant step, and a shallow source and drain extension dopant implant step; 
     FIG. 3 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 2, showing a spacer structure formation step; 
     FIG. 4 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 3, showing an anisotropic etching step; 
     FIG. 5 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 4, showing an amorphous semiconductor deposition step; 
     FIG. 6 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1, showing a chemical mechanical polish (CMP) step and a laser annealing step; and 
     FIG. 7 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1, showing a chemical etching step and a siliciding step. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to FIG. 1, a portion  10  of an integrated circuit (IC) includes a transistor  12  which is disposed on a semiconductor substrate  14 , such as, a wafer. Semiconductor substrate  14  is preferably a bulk P-type silicon substrate. Alternatively, substrate  14  can be any type of IC substrate including a gallium arsenide (GaAs), germanium, or a semiconductor-on-insulator (SOI) substrate (e.g., a silicon-on-glass substrate). 
     Transistor  12  can be a P-channel or N-channel metal oxide semiconductor field effect transistor (MOSFET) and is described below as an N-channel transistor. Transistor  12  includes a gate structure  18 , an elevated source region  22 , and an elevated drain region  24 . Regions  22  and  24  extend from a top surface  21  (above a top surface  27  of substrate  14 ) to a bottom  55  in substrate  14 . Regions  22  and  24  are 200-1000 Å deep (from surface  21  to bottom  55 ) and include a source extension  23 , a drain extension  25 , a deep source region  33 , and a deep drain region  35 . For an N-channel transistor, regions  22  and  24  are heavily doped with N-type dopants (e.g., 5×10 19 -1×10 20  dopants per cubic centimeter). For a P-channel transistor, regions  22  and  24  are heavily doped with P-type dopants (5×10 19 -1×10 20  dopants per cubic centimeter). 
     Extensions  23  and  25  are preferably ultra-shallow extensions (e.g., junction depth is less than 20 nanometers (nm), 100-250 Å), which are thinner than regions  33  and  35 . Extensions  23  and  25  are connected to regions  33  and  35 , respectively, and are disposed partially underneath gate structure  18 . Regions  33  and  35  are preferably more than 100 Å thick (e.g. 150 to 300 Å) from surface  21  to surface  27 . 
     A channel region  41  underneath gate structure  18  separates extensions  23  and  25 . Region  41  can be doped according to device parameters. For example, region  41  can be doped according to a super steep retrograded well region. 
     Ultra-shallow extensions  23  and  25  help transistor  12  achieve substantial immunity to short-channel effects. Short-channel effects can degrade the performance of transistor  12  as well as the manufacturability of the IC associated with transistor  12 . Regions  22  and  24  and extensions  23  and  25  have a concentration of 10 19  to 10 20  dopants per cubic centimeter. An appropriate dopant for a P-channel transistor is boron, boron diflouride, or iridium, and an appropriate dopant for an N-type transistor is arsenic, phosphorous, or antimony. 
     Gate stack or structure  18  includes a gate dielectric layer  34  and a gate conductor  36 . Dielectric layer  34  is preferably comprised of a high-k dielectric material. Layer  34  is preferably a 2-10 nm thick conformal layer of tantalum pentaoxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), titanium dioxide (TiO 2 ) or other material having a dielectric constant (k) over 8. Dielectric layer  34  can be deposited by CVD over substrate  14 . Layer  34  can be a 20-40 nm thick layer of amorphous Ta 2 O 5  material. 
     Layer  34  is preferably conformally deposited in a metal organic CVD process after any necessary high temperature annealing steps to prevent crystallization of amorphous Ta 2 O 5  material. Alternatively, layer  34  can be formed according to the process of U.S. Pat. No. 6,100,120. 
     After dielectric layer  34  is deposited, a 30-40 nm thick layer of gate conductor  36  is deposited above dielectric layer  34  in a low temperature process by CVD. Gate conductor  36  is preferably a metal, such as TiN. Alternatively, conductor  36  can be polysilicon or polysilicon/germanium. 
     Conductor  36  is preferably deposited by chemical vapor deposition (CVD) or sputter deposition and selectively etched by plasma dry etching to form the particular structure for transistor  12 . Gate structure  18  has a height or thickness of 500-2000 Å. 
     Gate structure  18  is disposed over channel region  41 . Gate structure  18  can also include oxide liners or spacers  62 . Spacers  62  abut sidewalls of gate conductor  36 . Spacers  62  are preferably silicon dioxide or silicon nitride (Si 3 N 4 ) having a width of 50-100 Å and a thickness (height) of 500-2000 Å. Spacers  62  provide an insulative buffer between conductor  36  and regions  22  and  24 . 
     A silicide layer  56  is deposited or sputtered on top of source region  22  and drain region  24 . Preferably, layer  56  is a nickel silicide (WSi x ). Alternatively, layer  56  can be any type of refractory metal and silicon combination, such as, a cobalt silicide, tungsten silicide, or other silicide material. Preferably, layer  56  is 150-300 Å thick. Metal contacts  68  can be coupled to layer  56  through insulating layer  48  to connect regions  22  and  24  to conductive lines  70 . 
     Transistor  12  can be an N-channel or a P-channel field effect transistor, such as, a metal oxide semiconductor field effect transistor (MOSFET). Transistor  12  is at least partially covered by insulative layer  48  and is preferably part of an ultra-large scale integrated (ULSI) circuit that includes one million or more transistors. 
     With reference to FIGS. 1-7, the fabrication of transistor  12 , including high-k gate dielectric layer  34 , elevated source region  22  and elevated drain region  24 , is described as follows. The advantageous process allows deep source and drain regions  33  and  35  to be formed with appropriate dopant activation without adversely affecting layer  34 . The process also reduces the lateral spread of dopants into channel  41  and thereby reduces susceptibility to short circuits between extensions  23  and  25 . 
     With reference to FIG. 2, transistor  12  includes a gate stack or gate structure  18  including a cap layer  80 , a gate conductor  36  and a gate dielectric layer  34 . Preferably, gate dielectric layer  34  is deposited or formed on top of surface  27  and conductor  36  is deposited or formed over layer  34 . Cap layer  80  is deposited on top of gate conductor  36  by CVD. Layer  80 , conductor  36  and layer  34  are selectively etched to leave gate structure  18  on a top surface  27  of substrate  14 . Preferably, conductor  36  is 500 to 2000 Å thick above a 10 to 60 Å thick layer  34 . Layer  80  is preferably a 150 to 300 Å thick layer of silicon nitride (Si 3 N 4 ). Alternatively, layer  80  can be other materials. 
     Layer  80  serves to protect conductor  36  and layer  34  during subsequent processing. For example, layer  80  can protect layer  34  during laser annealing and etching processes associated with the formation of transistor  12 . 
     After gate structure  18  is formed, substrate  14  is subject to a shallow amorphization implant to form an amorphization or amorphous region  40 . Amorphous region  40  can be created by subjecting substrate  14  to an ion implantation technique. Ion implantation can be performed by implantation devices manufactured by companies, such as, Verion Company of Palo Alto, California, Genius Company, and Applied Materials, Inc. Region  40  is preferably a shallow or thin amorphous region or layer of substrate  14  (e.g., a depth between 100 and 500 Å). The implantation technique can charge semiconductor ions, preferably, electrically neutral species (such as, silicon, germanium, or xenon ions) to approximately 10-100 kilo-electron volts (keVs) and implant them into substrate  14 . The silicon, germanium or xenon ions change the single crystal silicon associated with substrate  14  into amorphous silicon at region  40 . Region  40  corresponds to source and drain regions  22  and  24 . 
     After region  40  is formed, substrate  14  is subjected to a follow-up dopant implant (a shallow source drain extension dopant implant). Preferably, N-type or P-type dopants are provided by ion implantation to a depth of 100-250 Å below surface  27 . The dopants can be implanted in a conventional ion implantation technique (e.g., as ions at 500-1000 keV at a dose of 2×10 14 -1×10 15  dopants per square centimeter). The source drain extension dopant implant is for the formation of extensions  23  and  25  (FIG. 1) in substrate  14 . 
     In FIG. 3, portion  10  is subjected to a spacer formation process which creates spacers  62  on sidewalls  90  of gate structure  18 . Preferably, spacers  62  are narrow and are formed in a low temperature process (less than 400° C. to avoid recrystallization of region  40 ). Spacers  62  are preferably 50-200 Å wide (e.g., left to right) and 500-2000 Å thick (e.g., top (from a top surface of layer  80 ) to bottom (to top surface  37 )). Spacers  62  are formed in a conventional deposition and etch-back process. 
     In FIG. 4, after spacers  62  are formed, substrate  14  is subjected to an etching or removal process to remove portions of region  40 . Preferably, the removal process lowers a top surface of substrate  14  from its original top surface  27 . The etching technique can be a plasma dry etching technique in the location of regions  22  and  24  (deep regions  33  and  35 ) (FIG. 1) which removes 200 to 400 Å of material from substrate  14 . Cap layer  80  and spacers  62  protect layer  34  during this anisotropic etching process. 
     In FIG. 5, after gate structure  18  is formed including spacers  62  and substrate  14  is etched, portion  10  is subjected to a deposition process which provides an amorphous semiconductor layer  53  above substrate  14 . Layer  53  is preferably a 2000-5000 Å thick film of the same material as substrate  14  (e.g., silicon). Alternatively, layer  53  can be or include other semiconductor materials such as germanium. Layer  53  can be deposited by low pressure, chemical vapor deposition (LPCVD) at temperatures of less than 450° C. (400-450° C.). Layer  53  corresponds to portions of regions  33  and  35  above top surface  27  of substrate  14  (See FIG.  1 ). 
     Layer  53  is preferably an in-situ doped silicon material. Layer  53  is in-situ doped utilizing non-neutral dopants. Preferably, non-neutral dopants, such as, phosphorous (P), boron (B), arsenic (As), antimony (Sb), indium (In), and gallium (Ga). The dopants correspond to source region  22  and drain region  24  (FIG.  1 ). 
     After layer  53  is deposited, an amorphous material border  85  is located between layer  53  and substrate  14 . Border  85  includes the portion of region  40  that remains after the etching of substrate  14  described with reference to FIG.  4 . The remaining portion of region  40  corresponds to shallow source and drain extensions  23  and  25  discussed below with reference to FIG.  1 . 
     In FIG. 6, after layer  53  is provided over substrate  14 , layer  53  is subject to a planarization process, such as, a chemical mechanical polish (CMP). The CMP step removes layer  53  to expose cap layer  80  above gate conductor  36  in structure  18 . After the CMP step to expose layer  80 , an overetch technique can further lower layer  53  without lowering layer  80 . Preferably, layer  53  is overetched so that a surface  72  of layer  53  is lower than a surface  74  of gate conductor  36 . The overetch can be part of the same CMP process used to expose layer  53  or can be a dry or wet etch process. A top surface  76  of cap layer  80  is preferably 300-500 Å above surface  72 . The overetching step prevents bridging during subsequent silicidation steps described below with reference to FIG.  7 . 
     In FIG. 6, after overetching, layer  53  is subjected to an annealing process. The annealing process changes the structure of layer  53  from an amorphous state to a single crystalline state (e.g., melts layer  53  which subsequently recrystallizes). Substrate  14  below border  85  acts as a seed layer for layer  53 . Preferably, a laser technique is utilized to crystallize layer  53 . 
     In one embodiment, the annealing process is an excimer laser process (e.g.,  308  nanometer wavelength) for a pulse duration of approximately 1-20 ns. The annealing technique using an excimer laser can raise the temperature of layer  53  to the melting temperature of layer  53  (1100° C. for silicon). The melting temperature of layer  53  in the amorphous state is significantly lower than that of substrate  14  which is in a crystalline state. For example, the melting temperature of amorphous silicon is 1100° C. and the melting temperature of a single crystalline silicon substrate (C—Si) is 1400° C. Preferably, the annealing process is controlled so that layer  53  is fully melted and substrate  14  is not melted. After the energy associated with the annealing process is removed, layer  53  is recrystallized as a single crystalline material. 
     The melting associated with the annealing step allows dopants in layer  53  and the remaining portions of region  40  to become activated during the recrystallization. Regions  40  are melted and recrystallized during the annealing step. Preferably, the annealing step utilizes an excimer laser beam to selectively heat locations associated with regions  22  and  24  without significantly heating layer  34 . Further, cap layer  80  provides protection on top of metal gate conductor  36  so that layer  34  remains cool during laser exposure. The laser annealing is prevented from overheating layer  34 . 
     In FIG. 7, layer  56  is formed above regions  22  and  24  and conductor  36 . Layer  56  is preferably formed in a self-aligned silicide process. The process is preferably a low temperature 400-500° C. nickel silicide process. Layer  56  can be CoSi 2 , TiSi, NiSi 2 , etc. Elevated source and drain regions, regions  22  and  24 , allow space for layer  56  to form, thereby decreasing source/drain contact resistance. 
     Layer  56  is preferably 150-300 Å thick and approximately 30-50 percent of its thickness consumes layer  53 . With reference to FIG. 1, after layer  56  is formed, layer  48  is deposited in accordance with a tetraethylorthosilicate (TEOS) process. Preferably, layer  48  is 5000-15000 Å thick. After layer  48  is deposited, conventional MOSFET fabrication processes can be utilized to form contacts  68 , lines  70 , vias, interconnects, and other devices necessary for portion  10  of the integrated circuit. 
     It is understood that while the detailed drawings, specific examples, material types, thicknesses, dimensions, and particular values given provide a preferred exemplary embodiment of the present invention, the preferred exemplary embodiment is for the purpose of illustration only. The method and apparatus of the invention is not limited to the precise details and conditions disclosed. For example, although specific types of structures are shown, other structures can be utilized. Various changes may be made to the details disclosed without departing from the scope of the invention which is defined by the following claims.