Abstract:
Disclosed is a delay locked loop (DLL) for use in a semiconductor memory device, which has the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise. The DLL includes a controllable delay modification unit for delaying a clock signal fed thereto to produce a time-delayed signal, a comparator for comparing the time-delayed signal from the modification block and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal, and a delay control unit for counting the number that the corresponding output signal is activated, and producing a signal for controlling the addition or the subtraction of the time delay to the modification unit, if the counted value satisfies a predetermined condition.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a semiconductor memory device; and, more particularly, of a delay locked loop having the ability to drastically eliminate noise. 
     DESCRIPTION OF THE PRIOR ART 
     In general, a delay locked loop (DLL) circuit reduces a skew between a clock signal and data or between an external clock and an internal clock, which is used in synchronizing an internal clock of a synchronous memory to an external clock without incurring any error. Specifically, a timing delay is incurred when an external clock is used internally to a system, and the delay locked loop controls the timing delay to synchronize the internal clock to the external clock. 
     FIG. 1 is a schematic block diagram of a conventional delay locked loop. 
     A clock signal Clock_ 1  is input to a controllable delay modification unit  100  which delays the input signal by a certain time period and produces a time-delayed signal Delayed_clock to a comparator  110 . The comparator  110  compares the time-delayed signal Delayed clock and a reference signal Clock_reference, and determines if the time delay should be increased (added) or decreased (subtracted), to produce one of an addition signal Add_delay or a subtraction signal Subtract_delay. The addition signal Add_delay or the subtraction signal Subtract-delay output from the comparator  110  is fed back to the controllable delay modification unit  100 . Based on the addition signal or the subtraction signal, the controllable delay modification unit  100  modifies the time delay until the reference signal Clock_reference and the time-delayed signal Delayed_clock are synchronous in phase. 
     As mentioned above, the prior art is designed so that the comparator  110  determines if the time delay fed thereto from the controllable delay modification unit  100  should be increased or decreased and returns the result to the controllable delay modification unit  100  to thereby allow the time delay to be adjusted. 
     However, the prior art has a drawback that it is very sensitive to a power supply noise, random noise, radiation noise or other irregular noise. That is, the erroneous determination of the comparator  110  due to such noises causes an output signal to be fed back to the controllable delay modification unit  100  to be erroneous. As a result, the controllable delay modification unit  100  controls the time delay based on the erroneous signal, resulting in an unintended problem. 
     SUMMARY OF THE INVENTION 
     It is, therefore, a primary object of the present invention to provide a delay locked loop having the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise. 
     In accordance with a preferred embodiment of the present invention, there is provided a delay locked loop for use on a semiconductor memory device, which comprises: a controllable delay modification unit for delaying a clock signal fed thereto to produce a time-delayed signal; a comparator for comparing the time-delayed signal from the modification unit and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal; and a delay control unit for counting occurrences of the corresponding output signal and producing a signal for controlling the addition or the subtraction of the time delay to the controllable delay modification unit, if the counted value is larger than a predetermined value. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
     FIG. 1 shows a schematic block diagram of a conventional delay locked loop; 
     FIG. 2 is a schematic block diagram of a delay locked loop incorporating a delay control unit therein in accordance with preferred embodiments of the present invention; 
     FIG. 3 is a detailed block diagram of the delay control unit in accordance with a preferred embodiment of the present invention; 
     FIG. 4 is a detailed block diagram of the delay control unit in accordance with another preferred embodiment of the present invention; 
     FIG. 5 is a connection diagram illustrating a scheme which implements the addition/subtraction determination block through the use of bi-directional shift registers, in accordance with a preferred embodiment of the present invention; 
     FIG. 6 is a connection diagram illustrating another scheme which implements the addition/subtraction determination block through the use of bi-directional shift registers, in accordance with another preferred embodiment of the present invention; and 
     FIG. 7 is a block diagram of the addition/subtraction determination block implemented with a typical counter in accordance with another preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     There is shown in FIG. 2 a schematic block diagram of a delay locked loop incorporating a delay control unit therein in accordance with preferred embodiments of the present invention. 
     In FIG. 2, a clock signal Clock_ 1  is input to a controllable delay modification unit  200 , which produces a time-delayed signal Delayed_clock to a comparator  210 . The comparator  210  compares the time-delayed signal Delayed_clock from the controllable delay modification unit  200  and a reference signal Clock_reference, each being input thereto via terminals IN_CLOCK and REFERENCE respectively, and determines whether a time delay should be increased or decreased. The output of the comparator  210  is an addition signal Add_delay_i representing the increase of the time delay or a subtraction signal Sub_delay_i representing the decrease of the time delay, which is forwarded to a delay control unit  220 . 
     The delay control unit  220  handles an erroneous delay determination that may be induced by noise introduced by a power supply or a system. Specifically, the delay control unit  220  controls the controllable delay modification unit  200  only if at least two consecutive determinations for the time delay satisfy a predetermined condition. When the condition is satisfied, the delay control unit  220  outputs one of the addition signal Add_delay_i and the subtraction signal Sub_delay_i provided thereto from the comparator  210  to the controllable delay modification unit  200 . Thus, the controllable delay modification unit  200  increases or decreases the time delay based on the signal from the delay control unit  220 . 
     FIG. 3 is a detailed block diagram of the delay control unit in accordance with a preferred embodiment of the present invention. 
     The delay control unit in accordance with a preferred embodiment of the present invention includes an addition/subtraction determination block  300  and a reset signal generation block  310 . The addition signal Add_delay_i and the subtraction signal Sub_delay_i from the comparator  210  shown in FIG. 2 are relayed to the addition/subtraction determination block  300  which counts an input signal to produce one of signals Add_delay and Sub_delay for adjusting the time delay. The signal Add_delay represents that the time delay is in need of increase and the signal Sub_delay represents that the time delay is in need of decrease. The signals Add_delay and Sub delay are relayed to the reset signal generation block  310 , which produces a reset signal for initializing the addition/subtraction determination block  300 . 
     The addition/subtraction determination block  300  may be implemented with a counter. Specifically, if the addition signal Add_delay_i is input to the addition/subtraction determination block  300 , the addition/subtraction determination block  300  increases the counter by one. Similarly, if the subtraction signal Sub_delay_i is input, the addition/subtraction determination block  300  decreases the counter by one. Thus, the addition/subtraction determination block  300  produces the signal Add_delay if the counted value reaches a first predetermined value, and produces the signal Sub_delay if it reaches a second predetermined value. 
     FIG. 4 is a detailed block diagram of the delay control unit in accordance with another preferred embodiment of the present invention. 
     The delay control unit in accordance with another preferred embodiment of the present invention includes an addition/subtraction determination block  400  and a reset signal generation block  410 . The addition signal Add_delay_i and the subtraction signal Sub_delay_i from the comparator  210  shown in FIG. 2 is input to the addition/subtraction determination block  400  which counts an input signal to produce one of signals Add_delay and Sub_delay for adjusting the time delay. The signal Add_delay represents that the time delay is in need of increase and the signal Sub_delay represents that the time delay is in need of decrease. In contrast to the delay control unit shown in FIG. 3, inputs to the reset signal generation block  410  shown in FIG. 4 are the signal Add_delay_i or Sub_delay_i from the comparator  210  and the signal Add_delay or Sub-delay from the addition/subtraction determination block  400 . Based on these signals, the reset signal generation block  410  produces a reset signal for initializing the addition/subtraction determination block  400 . 
     The addition/subtraction determination block  400  may be implemented with a counter. Specifically, if the addition signal Add_delay_i is input to the addition/subtraction determination block  400 , the addition/subtraction determination block  400  increases the counter by one. Similarly, if the subtraction signal Sub_delay_i is input, the addition/subtraction determination block  400  decreases the counter by one. Thus, the addition/subtraction determination block  400  produces the signal Add_delay if the counted value reaches a first predetermined value, and produces the signal Sub_delay if it reaches a second predetermined value. 
     The input of the addition signal Add_delay_i and the subtraction signal Sub_delay_i allows the reset signal generation block  410  to reset the addition/subtraction determination block  400  if the addition signal followed by the subtraction signal is input thereto and vice-versa. Specifically, if a continuous number of the addition signal input to the reset signal generation block  410  exceeds a first predetermined number, the reset signal is produced to increase the time delay, and if a continuous number of the subtraction signal input to the reset signal generation block  410  exceeds a second predetermined number, the reset signal is produced to decrease the time delay. 
     FIG. 5 is a connection diagram illustrating a scheme which implements the addition/subtraction determination block through the use of bi-directional shift registers, in accordance with a preferred embodiment of the present invention. 
     In operation, the addition signal Add_delay_i and the subtraction signal Sub_delay_i from the comparator  210  show in FIG. 2, and the reset signal from the reset signal generation block  310  or  410  are input to each of a multiplicity of shift registers which are connected in series. The multiplicity of shift registers is divided into two groups  510  and  530 . The one group of shift registers  530  produces an output signal Add_delay_int and the second group of shift registers  510  produces an output signal Sub_delay_int, according to a counted value set by the input signals Add_delay_i and Sub_delay_i. Reset for the shift registers serially connected produces an initial value 1 or 0. In FIG. 5, a plurality of shift registers each having the initial value 0 is placed rightward and leftward of a shift register with the initial value 1. If the reset signal is input to the shift registers, each of the shift registers has a different initial value according to its type. 
     In FIG. 5, the first group of shift register  510  each being called a reset disable has an initial value set to be low, and a shift register  520  called a reset enable has an initial value set to be high. The output of the shift register  520  with the high state is moved rightward or leftward every occasion the addition signal Add_delay_i or Sub_delay_i is activated. Thereafter, if the shift register with the high state is placed right of the shift register  520 , the signal Add_delay_int is output to increase the time delay. On the other hand, if the shift register with the high state id placed left of the shift register  520 , the signal Sub_delay_int is output to decrease the time delay. Upon the input of the reset signal, the addition/subtraction determination block  300  or  400  is initialized. 
     FIG. 6 is a connection diagram illustrating another scheme which implements the addition/subtraction determination block through the use of bi-directional shift registers, in accordance with another preferred embodiment of the present invention. 
     In operation, the addition signal Add_delay_i and the subtraction signal Sub_delay_i from the comparator  210  shown in FIG. 2, and the reset signal from the reset signal generation block  410  are inputted to each of a multiplicity of shift registers which are connected in series. The multiplicity of the shift registers is divided into two groups  610  and  620 . The first group of the shift registers  620  produces an output signal Add_delay_int and the second group of the shift registers  610  produces an output signal Sub_delay_int, according to a counted value set by the input signals Add_delay_i and Sub_delay_i. Reset for the shift registers serially connected produces an initial value of high or low. In FIG. 6, the first group of shift registers  620  each having the initial value of high is placed right of the second group, and the second group of shift registers  610  each having the initial value of low is placed left of the first group. 
     The addition/subtraction determination block shown in FIG. 6 is similar to that shown in FIG. 5 except that the first group of the shift registers  620  with an initial value of low and the second group of the shift registers  610  with an initial value of high are arranged in series without intervening any unit there between. That is, passing the values of low and high to the group of the shift registers placed right and left, respectively, produces the output signals Add_delay_int and Sub_delay_int. Accordingly, the addition/subtraction determination block shown in FIG. 6 has a simplified structure in contrast with that shown in FIG.  5 . 
     FIG. 7 is a block diagram of the addition/subtraction determination block implemented with a typical counter in accordance with another preferred embodiment of the present invention. 
     Referring to FIG. 7, the addition/subtraction determination block of the present invention includes an addition delay counter  710 , an addition delay decoder  730 , a subtraction delay counter  720 , a subtraction delay decoder  740 , and a first and second OR gate  750  and  760 . 
     The addition delay counter  710  receives the addition signal Add_delay_i from the comparator  210  shown in FIG.  2  and counts the number of occurrences of the received signal to produce a counted value. The addition delay decoder  730  receives the counted value from the addition delay counter  710  and determines if the counted value has reached a first predetermined value. When reached, the addition delay decoder  730  outputs the addition signal Add_delay_int to the controllable delay modification unit  200  shown in FIG.  2 . The first OR gate  750  performs an OR operation on the final addition signal Add_delay_int from the addition delay decoder  730  and the subtraction signal Sub_delay_i, to thereby produce a first reset signal for resetting the addition delay counter  710 . 
     The subtraction delay counter  720  receives the subtraction signal Sub_delay_i from the comparator  210  shown in FIG.  2  and counts the number of occurrences of the received signal to produce a counted value. The subtraction delay decoder  740  receives the counted value from the subtraction delay counter  720  and determines if the counted value has reached a second predetermined value. If the counted value has reached the second predetermined value, the subtraction delay decoder  740  outputs the final output signal Sub_delay_int to the controllable delay modification unit  200  shown in FIG.  2 . The second OR gate  760  performs an OR operation on the subtraction signal Sub_delay_int from the subtraction delay decoder  740  and the addition signal Add_delay_i, to thereby produce a second reset signal for resettling the subtraction delay counter  720 . 
     There are two cases to reset the addition delay counter  710  as follows: a) when the subtraction signal Sub_delay_i is applied during the consecutive incoming of the addition signal Add_delay_i, and b) when the counted value of the consecutive addition signals exceeds the first predetermined value. Similarly, there are two cases to reset the subtraction delay counter  720  as follows: a) when the addition signal Add_delay_i is applied during the consecutive incoming of the subtraction signal Sub_delay_i, and b) when the counted value of the consecutive subtraction signals exceeds the second predetermined value. 
     As mentioned above, the present invention employs a delay control unit having the ability to selectively perform an addition and subtraction function on a time delay based on a predetermined condition, to thereby drastically reduce or eliminate a power supply noise, random noise or other irregular noise. 
     Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.