Abstract:
An input data recovery circuit is applied for asynchronous serial data transmission such as USB, SATA, or PCI-E. The input data recovery circuit includes two-tier switches controlled by the switching state of input data signal and pulse signals. The input data recovery circuit further includes pulse generator for producing pulse signals to trigger the input data signal and correctly recover the input data signal. The input data recovery circuit can be applied to equipment with high speed protocol because accumulated error between data sending end and data receiving end can be prevented.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an input-signal recovery circuit, especially to an input-signal recovery circuit recovering data signal by input data signal and asynchronous serial bus data reception system. 
         [0003]    2. Description of Prior Art 
         [0004]    The most serous problem for a data reception system using asynchronous serial bus is the frequency mismatch between a data transmitting end and a data receiving end. More particularly the data transmitting end and the data receiving end do not have common signal clock like that of the asynchronous serial bus, and error is accumulated when frequency mismatch is present therebetween. 
         [0005]      FIG. 1  shows a related art data reception system using asynchronous serial bus, which is filed by the same applicant in U.S. with application Ser. No. 12/393,737. As shown in this figure, the data reception system uses a pulse generator  120  to receive an input data signal Dr and then sends first pulse signals Vp 1  to nth pulse signals Vpn to a switch set  130 . The on/off of the switch set  130  is controlled by the switching state of the input data signal Dr and falling edge of the pulse signal Vp. 
         [0006]      FIG. 2  shows the flowchart for the operation of the switch set  130  shown in  FIG. 1 , this flowchart ensures only one switch in the switch set  130  is turned on at one time, while other switches are turned off. The on/off of the switches is controlled by the switching state of the input data signal Dr and falling edge of the pulse signal Vp. 
         [0007]      FIG. 3   a  shows the circuit diagram for the data switch detector  110  in  FIG. 1 .  FIG. 3   b  shows the truth table for XOR gate  112 .  FIG. 3   c  shows the waveforms for the data switch detector  110 . The input data signal Dr is delayed by a half-period buffer  111 , which outputs an internal signal Va, the internal signal Va and the input data signal Dr are sent to input ends of the XOR gate  112  to generate an output signal Vdsd. More particularly, the output signal Vdsd with half-period duration is generated when data switching (namely, logic change) between binary 1 and binary 0 is present in the input data signal Dr. 
         [0008]      FIG. 4   a  shows the circuit diagram of the first logic circuit  120  in the pulse generator shown in  FIG. 1 .  FIG. 4   b  shows the waveforms for the first logic circuit  120 . Similar to the data switch detector  110 , the input data signal Dr is delayed by a half-period buffer  121  to generate an internal signal V 1   b . The internal signal V 1   b  is delayed by another half-period buffer  122  to generate another internal signal V 1   c . The internal signals V 1   b  and V 1   c  are sent to input ends of an XOR gate  123  to generate a first pulse signal Vp 1 . In other word, after half-period delay, first pulse signal Vp 1  with half-period pulse width (in terms of logic high level) is generated when data switching between binary 1 and binary 0 is present in the input data signal Dr. 
         [0009]    Similarly, the internal signal V 1   c  output by the half-period buffer  122  is used as input signal for the logic circuit of next stage. In this manner, the second pulse signal Vp 2  to the n-th pulse signal Vpn can be generated. 
         [0010]      FIG. 5  shows waveforms for explaining the operation of the logic circuit with first pulse signal Vp 1  to the fourth pulse signal Vp 4 , where the pulse signals Vp 1 ˜Vp 4  are delayed each other by one period. The control for the switches SW 1 ˜SWn in the switch set  130  can be manifested with reference to this figure and also to  FIG. 2 . It should noted that only four switches SW 1 ˜SW 4  are shown in  FIG. 5  and the shaded regions indicate logic 1 level. A final pulse signal Vp can be obtained to trigger the flip-flop  140 , which also receives the input data signal Dr, thus obtaining an output data signal Dout. 
         [0011]      FIG. 6  is another viewpoint for  FIG. 5  where the switch conduction state and pulse signal are combined for better demonstration. The pulse signals Vp 1 ˜Vp 4  indicate the input pulse signal to the switches SW 1 ˜SW 4 , respectively. Taking the waveform for SW 1  (&amp;Vp 1 ) as example, the arrow “↑” indicates a rising edge for the first pulse signal Vp 1 . The number in the waveform means the ordinal number for the input data signal Dr. Similarly, Vp 2 ˜Vp 4  indicate the second to fourth pulse signals in SW 2 (&amp;Vp 2 )˜SW 4 (&amp;Vp 4 ). 
         [0012]    To fetch the correct signal, the rising edge of the final pulse signal Vp should be within the input data signal Dr. Provided that the max bit number for successive signal with unchanged logic state is n, and the rule for fetching the correct signal is 
         [0000]      ( n− 1)· T &lt;( n− ½)·(2· Td 05)&lt; n·T  
 
         [0000]      →( n− 1)· T &lt;( n− ½)·( T+ΔT )&lt; n·T  
 
         [0000]      →(−½)· T /( n− ½)&lt;Δ T &lt;(½)· T /( n− ½)
 
         [0013]    Where ΔT=2. Td 05 −T, and Td 05  is the delay time for the half-period buffer and T is the period for the input data. 
         [0014]    This rule imposes a limit for ΔT (namely, the difference between two times of the delay time for the half-period buffer and the period for the input data). More particularly, ΔT cannot be too large to cause fetching error for the input data signal Dr. Therefore, ΔT is an important design parameter for the present invention. 
         [0015]    Moreover, another parameter Tf 2   s  (the delay time of pulse falling-edge to switch turn-on/turn-off) is also important design parameter for the present invention. If ΔT&gt;0 and Tf 2   s  is too short, as shown in  FIG. 7 , after the falling edge of the first switch SW 1 , the rising edge of the second switch SW 2  will fetch the tail of the second pulse signal Vp 2 , which is corresponding to the previous data (namely, the input data signal Dr is logic high). As a result, an additional pulse (unwanted pulse) is generated and data is erroneously fetched. Therefore, the related art circuit should obey the rule of Tf 2   s  being larger than ΔT. 
       SUMMARY OF THE INVENTION 
       [0016]    It is an object of the present invention to provide an input data recovery circuit is applied for asynchronous serial data transmission, the input data recovery circuit employs two tiers of switches to overcome the problem occurred in the related art. 
         [0017]    Accordingly, the input data recovery circuit according to the present invention provides two sub switch sets and a main switch set in the pulse generator. The switches in the two sub switch sets and the main switch set are respectively controlled by the data switching state and the triggering of pulse signals, thus correctly outputting the pulse signals from the pulse generator. 
         [0018]    Therefore, the input data recovery circuit according to the present invention can overcome the limitation Tf 2   s  (the delay time of pulse falling-edge to switch turn-on/turn-off) being larger than ΔT, and the new limitation is Tf 2   s &gt;0. Because no negative delay time is present in practical circuit, there will be no additional pulse in the input data recovery circuit according to the present invention. 
     
    
     
       BRIEF DESCRIPTION OF DRAWING 
         [0019]    The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which: 
           [0020]      FIG. 1  shows a related art data reception system using asynchronous serial bus. 
           [0021]      FIG. 2  shows the flowchart for the operation of the switch set shown in  FIG. 1 . 
           [0022]      FIG. 3   a  shows the circuit diagram for the data switch detector in  FIG. 1 . 
           [0023]      FIG. 3   b  shows the truth table for XOR gate. 
           [0024]      FIG. 3   c  shows the waveforms for the data switch detector. 
           [0025]      FIG. 4   a  shows the circuit diagram of the first logic circuit in the pulse generator shown in  FIG. 1 . 
           [0026]      FIG. 4   b  shows the waveforms for the first logic circuit. 
           [0027]      FIG. 5  shows waveforms for explaining the operation of the logic circuit. 
           [0028]      FIG. 6  is another viewpoint for  FIG. 5  where the switch conduction state and pulse signal are combined for better demonstration. 
           [0029]      FIG. 7  depicts the unwanted pulse if ΔT&gt;0 and Tf 2   s  is too short. 
           [0030]      FIG. 8  shows the circuit diagram of the input data recovery circuit according to a preferred embodiment of the present invention. 
           [0031]      FIG. 9   a  shows the flowchart for the sub switch sets. 
           [0032]      FIG. 9   b  shows the flowchart for the main switch set. 
           [0033]      FIG. 10   a  shows the circuit diagram for the first set of logic circuit. 
           [0034]      FIG. 10   b  shows the truth table for the first set of logic circuit. 
           [0035]      FIG. 10   c  shows the waveforms for the first set of logic circuit. 
           [0036]      FIG. 11  shows the waveforms of the pulse signals and the switching status of switches. 
           [0037]      FIG. 12  depicts the waveforms for the condition with that ΔT&gt;0 and Tf 2   s  is too short. 
           [0038]      FIG. 13   a  shows the flowchart for the switch control according to another embodiment of the present invention. 
           [0039]      FIG. 13   b  shows the switching control of the main switch set according to another preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0040]      FIG. 8  shows the circuit diagram of the input data recovery circuit according to a preferred embodiment of the present invention. The input data recovery circuit according to the present invention comprises two input ends and one output end, where the two input ends receive an input data signal Dr and a delay control signal, respectively, and the output end outputs a data output signal Dout. The input data recovery circuit according to the present invention further comprises a data switch detector  810 , a pulse generator  820 , a high-pass sub switch set  831 , a low-pass sub switch set  832 , a main switch set  840 , and a switch control circuit  860 . The two input ends of the pulse generator  820  receive the input data signal Dr and the delay control signal, respectively. The pulse generator  820  then outputs a plurality of high pulse signals Vp 1 H˜VpnH and a plurality of low pulse signals Vp 1 L˜VpnL to the corresponding high-pass sub switches SW 1 H˜SWnH and the corresponding low-pass sub switches SW 1 L˜SWnL in the sub switch sets  831  and  832 , respectively. The data switch detector  810  senses the switching state of the input data signal Dr and controls the on/off of the switches in the sub switch sets  831  and  832  through the switch control circuit  860  and the triggering of the pulse signals. 
         [0041]    In the high-pass sub switch set  831 , all output ends of the high-pass sub switches SW 1 H˜SWnH are commonly connected to a high-pass output end, where the high-pass output end is electrically connected to a high-pass input end in a high-pass main switch SWH in the main switch set  840 . In the high-pass sub switch set  831 , all output ends of the low-pass sub switches SW 1 L˜SWnL are commonly connected to a low-pass output end, where the low-pass output end is electrically connected to a low-pass input end in a low-pass main switch SWL in the main switch set  840 . When the switches in the sub switch sets  831  and  832  are turned on sequentially, the pulse signals Vp 1 H˜VpnH, Vp 1 L˜VpnL are output to the main switch set  840  to function as an input high-pass pulse signal VpH and an input low-pass pulse signal VpL, respectively. The main switch set  840  outputs a final pulse signal Vp, which depends on the conduction state of the main switch set  840 . 
         [0042]    The final pulse signal Vp output by the main switch set  840  is sent to the clock input end of the flip-flop  850  to trigger the input data signal Dr input to the flip-flop  850 , thus correctly outputting the data output signal Dout. Moreover, the final pulse signal Vp output by the main switch set  840  is also sent to the switch control circuit  860  to control the on/off of the switches in the sub switch sets  831  and  832 . 
         [0043]    The sub switch sets  831  and  832  and the main switch set  840  are controlled with reference to the flowchart shown in  FIG. 9   a  and the schematic diagram shown in  FIG. 9   b . As shown in  FIG. 9   a , the switching of the sub switch sets  831  and  832  is similar to that shown in  FIG. 2  except that the corresponding sub switches in the sub switch sets  831  and  832  are turned on simultaneously. When a logic change is present in the input data signal Dr (namely from logic 0 to logic 1 and vice versa), the flow is back to the state where the first sub switches SW 1 H (SW 1 L) are on, and the triggering of the final pulse signal Vp is not necessary. When the input data signal Dr maintains the same logic state (namely, no logic high/low change), the second sub switches SW 2 H (SW 2 L), the third sub switches SW 3 H (SW 3 L), . . . , the n-th sub switches SWnH (SWnL) are sequentially turned on by the triggering of the falling edge of the final pulse signal Vp. 
         [0044]      FIG. 9   b  shows the switching of the switches in the main switch set  840 , where only one of the switches is on for the same time (namely, either the high-pass main switch SWH is on or the low-pass main switch is on). When the input data signal Dr is logic high, the high-pass main switch SWH is on; when the input data signal Dr is logic low, the low-pass main switch SWL is on. In other word, the on/off state of the main switch set  840  is directly controlled by the logic state of the input data signal Dr. 
         [0045]    The circuit diagram, the truth table and the input/output waveform for the data switch detector  810  in  FIG. 8  are similar to those shown in  FIGS. 3   a - 3   c . The data switch detector  810  comprises a half-period delay buffer  811  and an XOR gate  812 . The two inputs of the half-period delay buffer  811  receive the input data signal Dr and the delay control signal, and the data switch detector  810  outputs an internal signal. The input data signal Dr and the internal signal are sent to two input ends of the XOR gate  812  to generate an output signal Vdsd. More particularly, output signal Vdsd with half-period duration is generated when data switching between binary 1 and binary 0 is present in the input data signal Dr. The output signal Vdsd is then sent to the switch control circuit  860 , and then connected to the sub switch sets  831  and  832  for controlling switches therein. 
         [0046]      FIG. 10   a  shows the circuit diagram of the first set of logic circuit in the pulse generator  820 , where the pulse generator  820  comprises a plurality sets of logic circuits and sequentially generates the first pulse signals Vp 1 H, Vp 1 L, . . . , to the n-th pulse signals VpnH, VpnL after receiving the input data signal Dr. The first set of logic circuit generates the first high-pass pulse signal Vp 1 H and the first low-pass pulse signal Vp 1 L, and then sends the signals to the first high-pass sub switch SW 1 H in the high-pass sub switch set  831 , and the first low-pass sub switch SW 1 L in the low-pass sub switch set  832 , respectively. As shown in  FIG. 10   c , the first high-pass pulse signal Vp 1 H is a pulse with high-period of logic high state with half-period delay when the input data signal Dr is changed from logic 0 to logic 1. The first high-pass pulse signal Vp 1 H is within the first period when the input data signal Dr is changed from logic 0 to logic 1. Similarly, the first low-pass pulse signal Vp 1 L is within the first period when the input data signal Dr is changed from logic 1 to logic 0. 
         [0047]    Each set of logic circuit in the pulse generator  820  comprises two half-period delay buffers  821  and  822 , and two AND gates  823 ,  824  (each AND gate has a non-inverted input end and an inverted input end). The first half-period delay buffer  821  is electrically connected to the non-inverted input end of the first AND gate  823  and the inverted input end of the second AND gate  824 . The second half-period delay buffer  822  is electrically connected to the inverted input end of the first AND gate  823  and the non-inverted input end of the second AND gate  824 . As shown in  FIG. 10   a , one input of the first half-period delay buffer  821  in the first set of logic circuit is electrically connected to the input data signal Dr, while one input of the second half-period delay buffer  822  is electrically connected to the output of the first half-period delay buffer  821 . Moreover, the other inputs of the first half-period delay buffer  821  and the second half-period delay buffer  822  are connected to the delay control signals. 
         [0048]      FIG. 10   b  shows the truth table for the first set of logic circuit in the pulse generator  820  shown in  FIG. 10   a , and the  FIG. 10   c  shows the waveform for the first set of logic circuit in the pulse generator  820  shown in  FIG. 10   a . The input data signal Dr is delayed by the first half-period delay buffer  821  to form an internal signal V 1   d , and the internal signal V 1   d  is delayed by the second half-period delay buffer  822  to form another internal signal V 1   e . The two internal signals V 1   d  and V 1   e  are sent to the two AND gates  823 ,  824  with truth table feature shown in  FIG. 10   b  to output the first high-pass pulse signal Vp 1 H and the first low-pass pulse signal Vp 1 L, respectively. The first high-pass pulse signal Vp 1 H is logic high (“1”) with half-period and having half-period delay after the first period when the input data signal Dr is changed from logic 0 to logic 1. Similarly, the first low-pass pulse signal Vp 1 L is logic high (“1”) with half-period and having half-period the first period after the input data signal Dr is changed from logic 1 to logic 0. 
         [0049]    In the second set of logic circuit in the pulse generator  820 , the input of the first half-period delay buffer is electrically connected to the output of the second half-period delay buffer of previous set. The second set of logic circuit comprises a second half-period delay buffer and two AND gates as the first set of logic circuit to output the second high-pass pulse signal Vp 2 H and the second low-pass pulse signal Vp 2 L, respectively. In similar manner, the other sets of logic circuits can be formed to provide the high-pass pulse signals Vp 3 H-VpnH and the low-pass pulse signals Vp 3 L-VpnL, respectively. 
         [0050]      FIG. 11  shows the waveforms of the pulse signals and the switching status of switches, where all the pulse signals Vp 1 H˜VpnH, Vp 1 L˜VpnL, VpH, VpL and Vp are shown and the switching status of all switches SW 1 H˜SWnH, SW 1 L˜SWnL, SWH and SWL are shown. It should be noted only four sets of switches SW 1 H˜SW 4 H, SW 1 L˜SW 4 L, Vp 1 H˜Vp 4 H, Vp 1 L˜Vp 4 L are demonstrated in  FIG. 11  for simplicity, and the implementation of the present invention can have other numbers of switches. 
         [0051]    Taking the waveform for SW 1 H(&amp;Vp 1 H) as example, the shaded pulse means that the high-pass first switch SW 1 H is on and the signal Vp 1 H is the input pulse signal for the high-pass first switch SW 1 H. The arrow “t” indicates a rising edge for the first high-pass pulse signal Vp 1 H. The number in the waveform means the ordinal number for the input data signal Dr. Taking the waveform for SWH(&amp;VpH) as example, the shaded pulse means that the high-pass main switch SWH is on and the signal VpH is the input pulse signal for the high-pass main switch SWH. 
         [0052]    The cooperation of the two sub switch sets  831  and  832  and the main switch set  840  will be explained with reference to  FIG. 11 . There are four successive logic high signals (with four-bit duration) in the beginning of the input data signal Dr, and the first to the fourth high pulse signals Vp 1 H˜Vp 4 H are sequentially generated. The first to fourth high pulse signals Vp 1 H˜Vp 4 H are sequentially processed by the first to fourth high-pass sub switches SW 1 H˜SW 4 H to form a high pulse signal VpH for the high pass main switch SWH, and the high pulse signal VpH functions as the final pulse signal Vp for the flip-flop  850 . Namely, the final pulse signal Vp has four successive pulses in the four bit duration. The final pulse signal Vp is sent to the flip-flop  850  to trigger the input data signal Dr input to the flip-flop  850 . Therefore, the flip-flop  850  can correctly output the data output signal Dout, where the output signal Dout is the final output for the input data recovery circuit of the present invention. 
         [0053]    Similarly, when there are four successive logic low signals (with four-bit duration) appeared in the input data signal Dr, the first to the fourth low pulse signals Vp 1 L˜Vp 4 L are sequentially generated. The first to fourth low pulse signals Vp 1 L˜Vp 4 L are sequentially processed by the first to fourth low-pass sub switches SW 1 L˜SW 4 L to form a low pulse signal VpL for the low pass main switch SWL and the low pulse signal VpL functions as the final pulse signal Vp for the flip-flop  850 . Namely, the final pulse signal Vp has four successive pulses in the four bit duration. The final pulse signal Vp is sent to the flip-flop  850  to trigger the input data signal Dr input to the flip-flop  850 . Therefore, the flip-flop  850  can correctly output the data output signal Dout, where the output signal Dout is the final output for the input data recovery circuit of the present invention. 
         [0054]      FIG. 12  shows the waveforms of some pulse signals according to the present, which is counterpart shown in  FIG. 7 , where unwanted pulse is not generated by the condition of ΔT&gt;0 and over-short Tf 2   s  (The delay time of pulse falling-edge to switch turn-on/turn-off). In  FIG. 12 , by the falling-edge triggering of the final pulse signal Vp (or the first low pulse signal Vp 1 L), the on status of the first sub switch SW 1 H/SW 1 L is switched to the on status of the second sub switch SW 2 H/SW 2 L. At this time, the low-pass main switch SWL is on and the high-pass main switch SWH is off. The tail of the second high-pass pulse signal Vp 2 H (corresponding to the previous Dr with logic 1) coincides with the second high-pass sub switch SW 2 H and does not coincide with the high-pass main switch SWH. Therefore, unwanted pulse is not generated and data error does not occur. 
         [0055]    In the present invention, the falling edge of the final pulse signal Vp is used to trigger the two sub switch sets  831  and  832 . Therefore, half-period delay is present between the rising edge of the final pulse signal Vp (which is used to trigger the input data signal Dr) and the triggering for the sub switch sets  831  and  832 . The unwanted pulse does not occur even when ΔT&gt;0 and Tf 2   s  is short.  FIG. 13   a  shows the flowchart for the switch control according to another embodiment of the present invention, which is similar to that in  FIG. 9 . In  FIG. 13   a , the triggering time for the sub switch sets  831  and  832  is advanced by half-period. When the rising edge of the final pulse signal Vp triggers the input data signal Dr, the rising edge also triggers the sub switch sets  831  and  832  to change the on status thereof. The parameter Tf 2   s  becomes Tr 2   s  (The delay time of pulse rising-edge to switch turn-on/turn-off). It is found that the pulse width (on time) of the final pulse signal Vp is T/2 when Tr 2   s  is larger than T/2, and the pulse width (on time) of the final pulse signal Vp is Tr 2   s  when Tr 2   s  is smaller than T/2. In those situations, the pulse width (on time) of the final pulse signal Vp is sufficient (equal to T/2 or Tr 2   s ), and unwanted pulse does not occur. 
         [0056]    As shown in  FIG. 13   a , the switching of the sub switch sets  831  and  832  is advanced by half period and the input data recovery circuit can be used for higher-speed application.  FIG. 13   b  shows the switching control of the main switch set according to another preferred embodiment of the present invention. It can be seen that the main switch set is directly controlled by the switching status of the input data signal Dr. 
         [0057]    Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.