Abstract:
Provided is a memory chip array comprising a plurality of cell arrays and at least one predecoder commonly connected to the plurality of cell arrays, wherein the memory chip array promotes an efficient arrangement structure of the memory chip array and is minimized in area.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2008-0010291, filed on Jan. 31, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a memory chip array, and more particularly, to a memory chip array with optimized arrangement by forming a predecoder commonly connected to memory arrays on a region of a memory chip array. 
         [0004]    2. Description of the Related Art 
         [0005]    As industries and multimedia field develop, a demand for large-capacity information devices being used in computers or telecommunication apparatus is gradually increasing. Due to such a demand, information devices having high integration are being researched and developed. 
         [0006]    Semiconductor memory devices have been reducing the size of elements and continuously maximizing the portion integration within a plane given through attempts such as making in a three-dimensional structure. Recently, the size of a portion element has been reduced down to tens of nanometers, and thus the industry faces a great challenge in terms of miniaturizing portion elements. 
         [0007]      FIG. 1A  is a plan view illustrating a memory chip structure according to prior art. Referring to  FIG. 1A , for example, a row decoder  13  including a predecoder  11  and a row select  12  are formed on a first side of a memory cell array  10 , and a sense amplifier and a column decoder  14  are formed on a second side of the memory cell array  10 . The row decoder  13  and the column decoder  14  are formed individually at every cell array in the memory chip array. The memory chip having such a structure may be formed by, for example, fabricating the row decoder  13 , the column decoder  14 , and a sense amplifier and the like on a silicon surface, and fabricating a cell array thereon. Recently, a stackable memory structure with a three-dimensional configuration has been introduced. As shown in  FIG. 1B , a row decoder R and a column decoder C were arranged on a silicon surface in an alternating manner, and a memory array A was arranged thereon. Such a checkerboard patterned arrangement is known as an arrangement that efficiently utilizes a silicon area. 
         [0008]    Such prior art includes several problems. First, referring to  FIG. 1B , the edges of memory cells have reduced utilization due to the fabrication of the row decoders R and the column decoders C with half a block size. Second, referring to  FIG. 1A , each row decoder  13  is divided into multiple decoders, and among the multiple decoders, the predecoder  11  is located between the cell arrays  10 . By having the predecoder  11  for every cell array  10 , the overall area of the memory chip array is increased. In order to overcome such problems, a method has been introduced, wherein only the row decoder  13  is formed below the memory cell array, and the sense amplifier and the column decoder  14  are arranged between the cell array blocks or the like. In this case, however, the area of the sense amplifier and the column decoder  14  are significantly large, and thus the overall area of the memory chip array may become larger. Moreover, only a single layered active circuit plane can be formed, and thus forming a multi-layered memory array is limited. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention provides a memory chip array structure having an arrangement structure such that the area of the memory chip array is minimized. 
         [0010]    According to an aspect of the present invention, there is provided a memory chip array including a predecoder commonly connected to the plurality of cell arrays. 
         [0011]    The memory chip array includes a row select formed at each side of the cell arrays. 
         [0012]    The memory chip may further include a sense amplifier and a column decoder formed at the bottom of the cell arrays. 
         [0013]    According to another aspect of the present invention, there is provided a memory chip array comprising: 
         [0014]    a plurality of cell arrays storing information; 
         [0015]    a row select formed at a side of each of the cell arrays; and 
         [0016]    a predecoder commonly connected to the plurality of cell arrays. 
         [0017]    The predecoder may be formed on both sides of the plurality of cell arrays. 
         [0018]    The memory chip array may further include a logic portion formed on a region of the memory chip array. 
         [0019]    The logic portion may be formed on the center region of the memory chip array, and the cell arrays are formed on both sides of the logic portion. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
           [0021]      FIGS. 1A and 1B  are plan views illustrating memory chip array structures according to prior art; 
           [0022]      FIG. 2  is a plan view illustrating a memory chip array according to an embodiment of the present invention; 
           [0023]      FIG. 3  is a diagram illustrating a circuit configuration of the memory chip array of  FIG. 2 ; and 
           [0024]      FIGS. 4 to 7  are diagrams illustrating overall configurations of a memory chip array, according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0025]    Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. However, it should be understood that the sizes of each region in the drawings are somewhat exaggerated for the purpose of the description. 
         [0026]    A memory chip array according to an embodiment of the present invention bears a configuration where only a circuit associated with column movement such as a column decoder and a sense amplifier is disposed at the bottom of a cell array, and a circuit associated with a row is disposed between a plurality of cell arrays and the edges of a chip. Here, a decoder circuit associated with a row uses a multi-partitioned decoder to dispose predecoders with a relatively large area on a side of a plurality of cell arrays, such that a predecoder output can be commonly received by several row select circuits. As a result, by repeatedly disposing only the row select circuits with a small area, the overall area of a memory chip area can be minimized. 
         [0027]      FIG. 2  is a plan view illustrating a memory chip array according to an embodiment of the present invention. Referring to  FIG. 2 , a row decoder including a predecoder  21  and a row select  22  is formed on a first side of a cell array  20 , and a sense amplifier, which is a circuit associated with a column movement, and a column decoder  23  are disposed on a bottom region of the cell array  20 . 
         [0028]    A description comparing a memory chip array according to an embodiment of the present invention and a conventional memory chip array is as follows. 
         [0029]    A conventional memory chip array according to the prior art of  FIG. 1A  requires a decoder circuit in a row direction, and circuits controlling data input/output such as sense amplifier and column decoder that are a little smaller than the row decoder in the direction of a column must be disposed between cell arrays, and therefore a large area is needed. 
         [0030]    The prior art of  FIG. 1B  requires additional row decoders and column decoders disposed along the edges of the entire chip, therefore the area occupied is increased. And the row decoder and the column decoder for a single cell array exist on the bottom of the adjacent cell array, making the connection complex, and ensuring a space between the cell arrays for connection is separately required. 
         [0031]    The memory chip array according to the present invention includes a row decoder that is partitioned into the predecoder  21  and the row select  22 , and the predecoder  21  is formed on a predetermined region of the memory chip array. Therefore, unlike  FIG. 1A , a plurality of cell arrays  20  are connected with a single predecoder  21 , and thus, the area occupied by the predecoder  21  is minimized and space utilization can be maximized. 
         [0032]    Furthermore, only the circuits associated with column direction on the bottom of the cell array  20 , for example the sense amplifier and the column decoder  23  are disposed, and on a remaining area of the cell array  20 , a VPP (internal voltage increase) generating device or an IVC (internal voltage-decreasing circuit) generator and a detection circuit or the like is disposed. Therefore, the area occupied by the memory chip array can be greatly reduced as compared to the structure with the column decoder  14  disposed outside the cell arrays  10  as shown in  FIG. 1A . 
         [0033]      FIG. 3  is a diagram illustrating a circuit configuration of the memory chip array of  FIG. 2 . Assuming that a single cell array block  30  includes 256 row lines (RL&lt; 0 &gt;, RL&lt; 1 &gt; . . . RL&lt; 255 &gt;), the case where RL&lt; 0 &gt; is selected may be described as follows. First, P 0  is selected from among  64  predecoders  31 . Then, if A 0  is selected from among  4  A wires (A 0 , A 1 , A 2 , and A 3 ), RL&lt; 0 &gt; is enabled, and the remaining row lines RL&lt; 1 &gt;, RL&lt; 2 &gt;, and RL&lt; 3 &gt; enter into a disabled state. The predecoders  31  are not only applied to a single row select  32  and the single cell array block  30 , but also to a row select  32 ′ and a cell array block  30 ′ beside thereto. As a result, several row selects share predecoder generating input signals. 
         [0034]    The overall configurations of a memory chip array according to  FIG. 3  are illustrated in  FIG. 4 to 7 . 
         [0035]    Referring to  FIG. 4 , a plurality of cell arrays  40  storing information are formed on a memory chip array M, and row selects  42 , corresponding to row decoders, are each formed on a side of the plurality of cell arrays  40 . A sense amplifier, which is a circuit associated with a column direction, and a column decoder  43  are formed on the bottom of each of the cell arrays  40 . Predecoders  41  are formed on one side of the plurality of cell arrays  40  so as to be connected commonly to the plurality of cell arrays  40 . Moreover, a logic portion L, interpreting the commands, is formed on a predetermined region of the memory chip array M. 
         [0036]    The logic portion L and the predecoders  41  on the memory chip array M may be formed on selective regions. 
         [0037]      FIG. 5  illustrates a structure of predecoders  51   a  and  51   b  formed on both sides of a plurality of cell arrays  50 , unlike the structure of the memory chip array M of  FIG. 4 . 
         [0038]    Referring to  FIG. 5 , a plurality of cell arrays  50  are formed on a memory chip array M, and row selects  52 , corresponding to row decoders, are each formed on a side of the plurality of cell arrays  50 . On a bottom of each of the cell arrays  50 , a sense amplifier, which is a circuit associated with a column direction and a column decoder  53 , is formed. Moreover, the predecoders  51   a  and  51   b  are formed on both sides of the plurality of cell arrays  50  so as to be commonly connected to the cell arrays  50 . Also, a logic portion L, interpreting commands, is formed on a predetermined region of the memory chip array M. 
         [0039]      FIG. 6  illustrates a structure where the logic portion L is formed on a center region of the memory chip array M, in contrast to the memory chip array M according to  FIGS. 4 and 5 . 
         [0040]    Referring to  FIG. 6 , the logic portion L is formed on the center region of the memory chip array M, and a plurality of cell arrays  60  are formed on the left and the right sides of the logic portion L. Row selects  62 , corresponding to row decoders, are each formed on one side of the plurality of cell arrays  60 , and a sense amplifier, which is a circuit associated with column direction and a column decoder  63 , are formed on the bottom of each cell array  60 . The predecoders  61   a  and  61   b  are formed on one side of the plurality of cell arrays  60  so as to be commonly connected to the plurality of cell arrays  60 . 
         [0041]      FIG. 7  illustrates a structure where predecoders  71   a ,  71   b ,  71   c  and  71   d  are formed on both sides of a plurality of cell arrays  70 , in contrast to the structure of the memory chip array M according to  FIG. 6 . 
         [0042]    Referring to  FIG. 7 , a logic portion L is formed on a center region of the memory chip array M, and the plurality of cell arrays  70  are formed on the left and the right sides of the logic portion L. Row selects  72 , corresponding to row decoders, are each formed on one side of the plurality of cell arrays  70 , and a sense amplifier, which is a circuit associated with column direction and a column decoder  73 , are formed on the bottom of each cell array  70 . The predecoders  71   a ,  71   b ,  71   c , and  71   d  are formed on both sides of the plurality of cell arrays  70  so as to be commonly connected to the plurality of cell arrays  70 . 
         [0043]    As described previously, the memory chip array according to an embodiment of the present invention includes row selects from among row decoders on one side of the cell arrays storing information, and predecoders are formed so as to be commonly connected to the plurality of cell arrays. Moreover, by disposing only the circuits associated with column movement, such as column decoders and sense amplifiers, the overall chip array area can be minimized. 
         [0044]    The stackable memory device may be applicable as a media for various products. 
         [0045]    The present invention has the following effects. 
         [0046]    First, by forming the predecoders, among the row decoders, on a predetermined region of the memory chip array and commonly connected to every cell array, the efficiency of the memory chip array can be optimized. 
         [0047]    Second, by disposing only the circuits, such as a sense amplifier and column decoders requiring a large area, on the bottom region of the cell arrays and associated with the column direction, the overall area of the memory chip area can be reduced. 
         [0048]    While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.