Abstract:
A second order analog filter based on transconductance amplifiers and capacitors (gmC) has good linearity at low operating voltage by using linear active transconductance amplifiers with gains determined by physical resistors and output current mirrors in a positive feedback configuration to allow the implementation of complex poles in the transfer function.

Description:
TECHNICAL FIELD 
     The invention relates generally to electronic signal processing, and more particularly, to analog filters. 
     BACKGROUND 
     Analog filters play a very important role in communication systems and, more generally, in any analog signal processing system. Since any realizable filter transfer function can be decomposed in a factor of second order sections and first order sections, a very important building block is a second order filter that permits the implementation of complex filter poles. The emphasis in filter design is to implement such second order transfer functions with minimal power dissipation, at low supply voltage, while still maintaining tuning capability and a certain required linearity. In particular, gmC filters, which are based on transconductance amplifiers (gm) working on capacitive loads (C), have very good characteristics at high signal frequencies and are widely used in RF communication systems. 
     One exemplary second order filter implementation is shown in  FIG. 1 . An equivalent circuit targeting low voltage supply applications is further shown in  FIG. 2 . In the above circuit diagrams, the high efficiency comes from the use of a simple MOS device as a transconductance element. Very good high frequency performance is achieved by the lack of intermediate nodes with associated parasitic poles. 
     An analysis of the equivalent small signal circuit illustrated in  FIG. 3  indicates a second order transfer function, if gm 1 =gm 2 =gm 3 , 
                       V   out       V   in       =     1     1   +       sC   1       g   m       +         s   2     ⁢     C   1     ⁢     C   2         g   m   2                   (   1   )               
where: M 201 , M 202 , M 203 , and M 204  are assumed matched and having a common transconductance value gm;
   C   1   =C   221 /2;   C   2   =C   222 /2. 
     Depending on the relative values of C 1  and C 2 , the second order transfer function in Equation (1) may have a real pole or complex conjugate poles. This choice is made possible by the positive feedback of devices M 211  and M 212 . 
     The circuits in  FIG. 1  and  FIG. 2  appear to have two main drawbacks, which the present invention tries to address in detail in several embodiments described below. First, the transfer characteristic and the pole location depend on the transconductance of simple MOS devices. This transconductance value is hard to control over process and especially over temperature. For the circuit in  FIG. 2 , it is especially difficult to ensure that M 211  and M 212  devices have the same transconductance as the M 201  and M 202  devices. If the transconductance values do not match, the circuit may latch up due to positive feedback at low frequencies. On the other hand, if the M 211  and M 212  have a transconductance intentionally lower than M 201  and M 202  transconductance, the complex poles are harder to achieve and control. 
     A second drawback appears to be that the signal linear range is limited by the gate-to-source overdrive. The transconductance is highly non-linear due to the simple MOS devices used and the input and output signals occur directly across the gate to source pins of these MOS devices. If the bias currents are used to adjust the transconductance values over process corner variations (for pole location tuning), this has a compounding effect on limiting the signal linear range. A process fast corner, for example, requires less bias current for a given required transconductance, which means even less gate-to-source overdrive voltage and equivalent reduced linear range. On the slow process corner, the higher bias current required and related larger voltage drops may be limited by power supply level. 
     It is desirable, therefore, to provide an efficient second order gmC filter implementation without the aforementioned drawbacks. 
     SUMMARY 
     In accordance with one embodiment of the present invention, a second order analog gmC filter is implemented with two transconductance amplifiers, with one of these transconductance amplifiers having a matched dual current output, one of which is used in a positive feedback configuration to allow an effective implementation of complex poles. Very good linearity may be achieved by using linear active transconductance amplifiers, where the respective transconductance value is determined by matched physical resistors. The transconductance value and pole location are independent from the individual MOS device characteristics and bias currents, and the linear range is dependent only on the physical resistor value used and the bias currents. Thus, the pole location/filter frequency corner and the linear range are decoupled and may be chosen and adjusted independently. 
     In an alternate embodiment of the present invention, a second order analog gmC filter may implement transmission zeros in the transfer characteristic to allow the implementation of Chebyshev type II or elliptic filters. 
     In yet another embodiment of the present invention, the MOS devices used in the linear transconductance amplifiers can be cascoded to improve output impedance and overall linearity. 
     These and other features of the present invention will be apparent from consideration of the following detailed description of the invention and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a conventional second order gmC filter. (Prior Art) 
         FIG. 2  is a schematic diagram of a conventional second order gmC filter suitable for low voltage applications. (Prior Art) 
         FIG. 3  is a schematic diagram illustrating the small signal equivalent diagram of the circuits shown in  FIG. 1  and  FIG. 2 . (Prior Art) 
         FIG. 4  is a small signal equivalent diagram of a second order gmC filter, according to one embodiment of the present invention. 
         FIG. 5  is a schematic diagram of a second order gmC filter, according to one embodiment of the present invention. 
         FIG. 6  is a small signal equivalent diagram of a second order gmC filter, according to an alternate embodiment of the present invention. 
         FIG. 7  is a schematic diagram of a second order gmC filter, according to an alternate embodiment of the present invention. 
         FIG. 8  is a small signal equivalent diagram of a second order gmC filter, according to yet another alternate embodiment of the present invention. 
         FIG. 9  is a schematic diagram of a second order gmC filter, according to yet another alternate embodiment of the present invention. 
         FIG. 10  is a schematic diagram of a second order gmC filter, according to yet another alternate embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 4  is a small signal equivalent diagram of a second order gmC filter, according to one embodiment of the present invention. Referring to  FIG. 4 , in one embodiment, an analog second order filter with a transfer function having complex poles may be implemented with a first transconductance amplifier gm 401 , having a first capacitor load C 421 , and a second transconductance amplifier gm 402  with two substantially equal current outputs and a second load capacitor C 422 . Considering gm the common gain in the transconductance amplifiers gm 401  and gm 402 , the transfer function of the circuit shown in  FIG. 4  may be calculated as follows: 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       out 
                     
                     
                       V 
                       in 
                     
                   
                   = 
                   
                     1 
                     
                       1 
                       + 
                       
                         
                           sC 
                           421 
                         
                         
                           g 
                           m 
                         
                       
                       + 
                       
                         
                           
                             s 
                             2 
                           
                           ⁢ 
                           
                             C 
                             421 
                           
                           ⁢ 
                           
                             C 
                             422 
                           
                         
                         
                           g 
                           m 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Other transfer functions can be realized if the two outputs of the second transconductance amplifier are intentionally set at a ratio different than unity. However, as a condition of stability, the following relation needs to be preserved:
 
gm 402 ≦gm 401   (3)
 
     From a practical implementation point of view, it is desirable to control the value of the transconductance gain and to maximize the signal linear range. One such implementation for a fully differential circuit is shown in  FIG. 5 . In one embodiment, the MOS devices M 501  and M 502  and the current sources I 531  and I 532  form a buffer with a very low impedance output. Since the current through the MOS device M 501  is forced to be substantially equal to I 531  current source by the feedback connection of M 503 , the M 501  gate-to-source voltage is independent (to the first order, neglecting M 501  body effect and finite output impedance) of the input level and, therefore, the node A accurately follows the alternating current (AC) variations at the input node inp. 
     In one embodiment, the series resistor R 505  together with the input buffer just described form a very linear transconductor, with a transconductance gain determined by the resistor value R 505 . Node C in  FIG. 5  plays the role of the intermediate node in  FIG. 4 . Since the node A follows the input node voltage variation, the AC current injected into node C by the resistor R 505  is calculated as follows: 
     
       
         
           
             
               
                 
                   
                     I 
                     505 
                   
                   = 
                   
                     
                       
                         V 
                         inp 
                       
                       - 
                       
                         V 
                         C 
                       
                     
                     
                       R 
                       505 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     The equivalence with the circuit in  FIG. 4  is determined by the equation below: 
     
       
         
           
             
               
                 
                   
                     gm 
                     401 
                   
                   = 
                   
                     1 
                     
                       R 
                       505 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     In one embodiment, a linear transconductance circuit is also implemented with MOS devices M 511 , M 5   541 , and M 543 , the current sources I 551 , I 553  and I 555 , and the resistor R 515 . The local feedback connection with M 541  forces a constant current through M 511 , determined by the current source I 511 . Since the drain-to-source current through M 511  is largely independent of the voltage level at the C node, the level at node E will follow the AC variations at the node C. The current injected into the output node outp by the resistor R 515  is calculated as follows: 
     
       
         
           
             
               
                 
                   
                     I 
                     515 
                   
                   = 
                   
                     
                       
                         V 
                         C 
                       
                       - 
                       
                         V 
                         outp 
                       
                     
                     
                       R 
                       515 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     The equivalence with the circuit in  FIG. 4  is determined by the equation below: 
     
       
         
           
             
               
                 
                   
                     gm 
                     402 
                   
                   = 
                   
                     1 
                     
                       R 
                       515 
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     Moreover, since the M 511  current is constant, all the AC current in the resistor R 515  is supplied by M 541 . In one embodiment, using a matched device M 543 , a replica of the current through the R 515  is injected into the node D, which has the same function as node C in the fully differential circuit, but has opposite signal polarity. A similar analysis holds for the other side of this fully differential circuit. 
     In one embodiment, given the following matched devices:
 
M 541 =M 543 ;
 
M 542 =M 544 ;
 
R 505 =R 506 =R 515 =R 516 =R;
 
the overall transfer function of this circuit may be calculated with the equation below:
 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       out 
                     
                     
                       V 
                       in 
                     
                   
                   = 
                   
                     1 
                     
                       1 
                       + 
                       
                         2 
                         · 
                         s 
                         · 
                         R 
                         · 
                         
                           C 
                           521 
                         
                       
                       + 
                       
                         4 
                         · 
                         
                           s 
                           2 
                         
                         · 
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           521 
                         
                         · 
                         
                           C 
                           522 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     Although the parameters in the transfer function given by the equation (8) can be modified if a ratio different than 1 is used between M 541 /M 542  and M 543 /M 544  or the R 505 /R 506  and R 515 /R 516 , for stability is important to follow the relation given by equation (3), which further translates into 
                     1     R   505       ≤       1     R   515       ·       gm   542       gm   541                 (   9   )               
and the equivalent for the other side of the differential circuit.
 
     In another embodiment of the present invention, as illustrated in  FIG. 6 , transmission zeros may be implemented by using a feed-through capacitor C 623  between the input node and the output node. The transfer function 
                       V   out       V   in       =       1   +         s   2     ⁢     C   621     ⁢     C   623         g   m   2           1   +       sC   621       g   m       +         s   2     ⁢       C   621     ⁡     (       C   622     +     C   623       )           g   m   2                   (   10   )               
has complex conjugate transmission zeros that may implement Chebyshev type II or elliptic filters.
 
     The transistor level implementation shown in  FIG. 7  is equivalent to the circuit presented in  FIG. 6 . In one embodiment, the connection of transmission zeros capacitors C 723  and C 724  is actually taken from the outputs of the input buffers (nodes A and B) rather than the input nodes inp and inn, since the buffer output impedance is very low and controlled. 
     In one embodiment, given the following matched devices:
 
M 741 =M 743 ;
 
M 742 =M 744 ;
 
R 705 =R 706 =R 715 =R 716 =R;
 
C 723 =C 724 ,
 
     the overall transfer function of this circuit may be calculated with the equation below: 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       out 
                     
                     
                       V 
                       in 
                     
                   
                   = 
                   
                     
                       1 
                       + 
                       
                         2 
                         · 
                         
                           s 
                           2 
                         
                         · 
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           721 
                         
                         · 
                         
                           C 
                           723 
                         
                       
                     
                     
                       1 
                       + 
                       
                         2 
                         · 
                         s 
                         · 
                         R 
                         · 
                         
                           C 
                           721 
                         
                       
                       + 
                       
                         2 
                         · 
                         
                           s 
                           2 
                         
                         · 
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           721 
                         
                         · 
                         
                           ( 
                           
                             
                               2 
                               · 
                               
                                 C 
                                 722 
                               
                             
                             + 
                             
                               C 
                               723 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
     Other transfer function implementations are possible by changing the connection of the feed-through capacitor. In one example, a real transmission zero may be implemented with the circuit shown in  FIG. 8 . In this embodiment, a feed-through capacitor C 823  is coupled between the input and the filter internal node. The transfer function 
                       V   out       V   in       =       1   +       sC   823       g   m           1   +       s   ⁡     (       C   821     +     C   823       )         g   m       +         s   2     ⁢       C   822     ⁡     (       C   821     +     C   823       )           g   m   2                   (   12   )               
has a real transmission zero.
 
     The transistor level implementation shown in  FIG. 9  is equivalent to the circuit in  FIG. 8 . In one embodiment, the connection of transmission zeros capacitors C 923  and C 924  is actually taken from the outputs of the input buffers (nodes A and B) rather than the input nodes inp and inn, since the buffer output impedance is very low and controlled. 
     In one embodiment, given the following matched devices:
 
M 941 =M 943 ;
 
M 942 =M 944 ;
 
R 905 =R 906 =R 915 =R 916 =R;
 
C 923 =C 924 ;
 
the overall transfer function of this circuit is calculated with the equation below:
 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       out 
                     
                     
                       V 
                       in 
                     
                   
                   = 
                   
                     
                       1 
                       + 
                       
                         s 
                         · 
                         R 
                         · 
                         
                           C 
                           923 
                         
                       
                     
                     
                       1 
                       + 
                       
                         s 
                         · 
                         R 
                         · 
                         
                           ( 
                           
                             
                               2 
                               · 
                               
                                 C 
                                 921 
                               
                             
                             + 
                             
                               C 
                               923 
                             
                           
                           ) 
                         
                       
                       + 
                       
                         2 
                         · 
                         
                           s 
                           2 
                         
                         · 
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           922 
                         
                         · 
                         
                           ( 
                           
                             
                               2 
                               · 
                               
                                 C 
                                 921 
                               
                             
                             + 
                             
                               C 
                               923 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
     An enhanced version of the proposed circuit is shown in  FIG. 10 , where the transistors in the current mirror are cascoded to increase the output impedance and overall linearity. 
     It is understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented. 
     Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. 
     Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. 
     The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. 
     The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal. 
     In the foregoing description, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.