Abstract:
The amplitude and phase errors of the modulation and demodulation in a transceiver are corrected by a self-calibration procedure in which a test signal is applied to the baseband input of the transmitter, and the output of the modulator is looped back to the input of the demodulator. The amplitude and phase errors of the resulting signal at the baseband output of the receiver are detected, and the contributions of the transmitter and receiver to the errors are separated and resolved into amplitude and phase components. Adjustments are then made to the amplitude and phase balance in the transmit and receive signal paths to correct the errors.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of provisional patent application Ser. No. 60/570,131, filed May 11, 2004, the disclosure of which is hereby incorporated by reference in its entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to a radio frequency (RF) transceiver, and more particularly relates to a calibration of a RF transceiver. 
   BACKGROUND OF THE INVENTION 
   In a radio-frequency transceiver, mismatches between in-phase (I) and quadrature (Q) baseband signal paths result in amplitude and phase errors that degrade the quality of the transmitted or received signal. In a transceiver without calibration, amplitude and phase errors up to 0.3 dB and 3°, respectively, can occur. This is acceptable for many radio frequency (RF) communication systems, such as wireless local area networks (LANs) based on the IEEE standard 802.11b. However, in order to achieve an acceptable error vector magnitude for the IEEE wireless LAN standards 802.11a and 802.11g, the transceiver must achieve ≦0.1 dB amplitude error and ≦1° phase error, thereby requiring some form of calibration. 
   The amplitude and phase errors of an integrated transceiver can be corrected either by an end-of-line calibration or by self-calibration. End-of-line calibration is a one-time calibration performed at the end of the manufacturing process of the transceiver chip or of the circuit board on which it is mounted and generally requires the use of circuitry external to the transceiver. For self-calibration, the calibration is performed repeatedly throughout the operating lifetime of the transceiver chip or circuit board, and the entire calibration circuitry is on-chip. In addition to being either end-of-line calibration or self-calibration, calibration can be performed with either a continuous-wave (CW) signal or a modulated signal. 
   Compared to an end-of-line calibration, self-calibration has the advantages that the calibration does not increase the cost or duration of the manufacturing process or require additional equipment. In addition, self-calibration avoids the need for a non-volatile memory to store the calibration settings, and it automatically corrects any drift of the amplitude and phase errors during the operating lifetime of the transceiver. 
   In typical CW calibration procedures, the transmitter is calibrated by applying sinusoidal test signals of equal amplitude and frequency with a 90° phase difference to the baseband inputs of the transceiver, measuring the spectrum of the RF output signal, and adjusting the control inputs for the amplitude and phase balance so as to minimize the amplitude of the suppressed sideband. The receiver is calibrated in an analogous manner by applying a single tone, which is offset from the carrier frequency, to the RF input, measuring the relative amplitude and phase of the resulting sinusoidal signals at the baseband outputs, and adjusting the control inputs such that the amplitudes of the baseband outputs are equal and the phase difference between the baseband outputs is equal to 90°. 
   In this type of calibration, the control inputs are adjusted in an iterative manner, alternating between amplitude and phase adjustments, until the amplitude of the suppressed sideband at the transmitter output and the amplitude and phase errors at the receiver outputs are within defined limits. This technique becomes too complicated if separate adjustment of the baseband and carrier components of the phase error is needed to achieve desired accuracy. The complication arises from the fact that the measurement procedure must not only alternate between three control inputs (amplitude error, baseband phase error and carrier phase error), but also between upper-sideband (I leads Q) and lower-sideband (I lags Q) test signals. 
   In principle, after the transmitter is calibrated, the transmitter output could be used as the test signal for the receiver. However, any remaining errors in the transmitter would result in a residual unwanted sideband and degrade the calibration accuracy of the receiver. Thus, in practice, a separate, single-tone RF signal source is needed to calibrate the receiver by the method described above. For self-calibration, implementing such a source on-chip with the necessary frequency accuracy would require an additional phase-locked loop (PLL), which is undesirable. 
   Thus, there remains a need for a transceiver including self-calibration circuitry that shortens and simplifies the calibration procedure. 
   SUMMARY OF THE INVENTION 
   The amplitude and phase errors of the modulation and demodulation in a transceiver are corrected by a self-calibration procedure in which a test signal is applied to the baseband input of the transmitter, and the output of the modulator is looped back to the input of the demodulator. The amplitude and phase errors of the resulting signal at the baseband output of the receiver are detected, and the contributions of the transmitter and receiver to the errors are separated and resolved into amplitude and phase components. Adjustments are then made to the amplitude and phase balance in the transmit and receive signal paths to correct the errors. 
   Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 

   
     BRIEF DESCRIPTION OF THE DRAWING FIGURES 
     The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention. 
       FIG. 1  illustrates a typical transceiver known in the art; 
       FIG. 2  is a block diagram illustrating amplitude and phase errors associated with the transmitter of the transceiver of  FIG. 1 ; 
       FIG. 3  is a block diagram illustrating amplitude and phase errors associated with the receiver of the transceiver of  FIG. 1 ; 
       FIG. 4  illustrates a transceiver including loopback circuitry and calibration circuitry according to one embodiment of the present invention; 
       FIG. 5  illustrates one embodiment of the measurement circuitry of the calibration circuitry illustrated in  FIG. 4 ; 
       FIG. 6  illustrates another embodiment of a transceiver including loopback circuitry and calibration circuitry according to the present invention; 
       FIG. 7  illustrates a phase shifter of the loopback circuitry of  FIG. 6 ; 
       FIG. 8  illustrates one embodiment of the test signal generator of  FIGS. 4 and 6 ; 
       FIG. 9  illustrates one embodiment of the baseband filters of  FIG. 6 ; and 
       FIG. 10  illustrates circuitry for generating transmit and receive carrier signals according to one embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
   The present invention provides calibration for a radio frequency (RF) transceiver. Before further discussing the present invention, it is beneficial to discuss the inherent errors of a typical transceiver  10  illustrated in  FIG. 1 . The transceiver  10  can be partitioned into a baseband processor  12  and a radio section  14 . In the radio section  14 , a transmitter  16  receives baseband transmit signals (I T  and Q T ) from the baseband processor  12  and outputs a corresponding RF transmit signal (X T ) to an antenna  18  via switch  20 . The radio section also includes a receiver  22  that receives a received RF signal (X R ) from the antenna  18  and outputs corresponding baseband receive signals (I R  and Q R ) to the baseband processor  12 . 
   A modulated signal can be expressed as the weighted sum of two orthogonal carriers:
 
 X ( t )= I ( t )cos(ω c   t )− Q ( t )sin(ω c   t )  (1)
 
where ω c  is the carrier frequency, t is time, and the weighting functions I(t) and Q(t) are the orthogonal components of the baseband signal. In the transceiver  10 , the transmitter  16  includes a modulator, which generates the transmit signal (X T ) from orthogonal baseband transmit signals (I T ) and (Q T ), and the receiver  22  includes a demodulator, which generates the orthogonal baseband receive signals (I R ) and (Q R ) from the received RF signal (X R ). Thus, for an ideal transceiver  10 ,
 
 X   T ( t )= I   T ( t )cos(ω c   t )− Q   T ( t )sin(ω c   t )  (2)
 
 X   R ( t )= I   R ( t )cos(ω c   t +θ)− Q   R ( t )sin(ω c   t +θ)  (3)
 
where θ is a phase offset between the transmit and receive carriers ω c , which is unimportant in normal operation. For a non-ideal transceiver  10 ,
 
 X   T ( t )= I′   T ( t )cos(ω c   t )− Q′   T ( t )sin(ω c   t )  (4)
 
 X   R ( t )= I′   R ( t )cos(ω c   t +θ)− Q′   R ( t )sin(ω c   t +θ)  (5)
 
where I′ T  and Q′ T  are the inputs to an ideal transmitter that would generate the same transmit signal (X T ) as the non-ideal transmitter  10 , and I′ R  and Q′ R  are the outputs of an ideal receiver for the same received signal (X R ) as the non-ideal receiver  10 . Deviations from ideal behavior are attributable partly to noise and non-linearity in the transceiver  10 , and partly to other effects that are associated with mismatches between nominally identical sections of the signal path. The purpose of the invention is to correct the modulation and demodulation errors associated with such mismatches.
 
   The mismatch errors of the transmitter  16  occur only in the modulator and the stages preceding the modulator in the transmit signal path and can be represented as shown in  FIG. 2 . There are three distinct errors: an amplitude error a T , which causes the baseband transmit signal (I T ) to be amplified by a factor 1+a T  relative to the baseband transmit signal (Q T ) (Block  16 A), a baseband phase error φ T , which causes the baseband transmit signal (I T ) to be advanced in phase by φ T  relative to the baseband transmit signal (Q T ) (Block  16 B), and a carrier phase error θ T , which causes the magnitude of the phase difference between the nominally orthogonal carriers to be 90°+θ T  (Block  16 C). Multiplication circuitries  16 D and  16 E operate to modulate the baseband transmits signals (I T  and Q T ), and the modulated baseband signals are combined by adder  16 F to provide the modulated transmit signal (X T ). If
 
 I   T =cos(ω b   t )  (6)
 
 Q   T =±sin(ω b   t )  (7)
 
where ω b  is a constant, then
 
 I′   T ≈(1 +a   T )cos(ω b   t+φ   T ±θ T )  (8)
 
 Q′   T ≈±sin(ω b   t )  (9)
 
The baseband phase error φ T  and the carrier phase error θ T  add if the baseband transmit signal (I T ) leads the baseband transmit signal (Q T ), and subtract if I T  lags Q T .
 
   The mismatch errors of the receiver  22  occur only in the demodulator and the stages following the demodulator in the receive signal path and can be modeled as shown in  FIG. 3 . There are three distinct errors: an amplitude error a R , which causes the baseband receive signal (I R ) to be amplified by a factor 1+a R  relative to the baseband receive signal (Q R ) (Block  22 A), a baseband phase error φ R , which causes the baseband receive signal (I R ) to be advanced in phase by φ R  relative to the baseband receive signal (Q R ) (Block  22 B), and a carrier phase error θ R , which causes the magnitude of the phase difference between the nominally orthogonal carriers to be 90°+θ R  (Block  22 C). Multipliers  22 D and  22 E operate to demodulate the modulated receive signal X R . If
 
 X   R =2 cos [(ω c ±ω b ) t]   (10)
 
then
 
 I   R ≈(1 +a   R )cos(ω b   t+φ   R ±θ R ∓θ)  (11)
 
 Q   R ≈±sin(ω b   t ∓θ).  (12)
 
If the frequency of the received signal (X R ) is greater than the carrier frequency ω c , then the baseband receive signal (I R ) leads the baseband receive signal (Q R ), and the baseband phase error φ R  and the carrier phase error θ R  add. If the frequency of the received signal (X R ) is less than the carrier frequency ω c , then I R  lags Q R , and the baseband phase error φ R  and the carrier phase error θ R  subtract.
 
   In a transceiver without calibration, amplitude and phase errors of up to 0.3 dB for 1+a T  and 1+a R , and 3° for φ T ±θ T  and φ R ±θ R  can occur. This is acceptable for many RF communication systems, such as wireless LANs based on the IEEE standard 802.11b. However, in order to achieve an acceptable error vector magnitude for the IEEE wireless LAN standards 802.11a and 802.11g, the transceiver  10  must achieve values ≦0.1 dB for 1+a T  and 1+a R , and ≦1° for φ T ±θ T  and φ R ±θ R , which requires some form of calibration. 
     FIG. 4  illustrates a transceiver  24  providing I/Q calibration according to one embodiment of the present invention. In general, the transceiver  24  includes a baseband processor  26 , transmit and receive circuitry  28 , loopback circuitry  30 , calibration circuitry  32 , amplification and processing circuitry  34 , and an antenna  36 . In normal transmit operating mode, the modulated transmit signal X T  from the transmit and receive circuitry  28  is passed to the amplification and processing circuitry  34 , which operates to upconvert and amplify the modulated transmit signal X T  prior to transmission via the antenna  36 . In normal receive operating mode, the amplification and processing circuitry  34  operates to amplify and downconvert a received signal to provide the modulated receive signal X R , which is passed to the transmit and receive circuitry  28  for demodulation. 
   In addition to its normal transmit and receive operating modes, the transceiver  24  has a calibration mode in which the loopback circuitry  30  forms a loopback signal path between a modulator  38  and a demodulator  40  of the transmit and receive circuitry  28 . The loopback circuitry  30  may include any or none of the circuitry that follows the modulator  38  and precedes the demodulator  40  in normal operation, and may also include additional circuitry, such as switches and a phase shifter, as described in more detail below. A control input to the loopback circuitry  30  allows a phase shift of the loopback circuitry  30  to be switched between two values differing by 90°. Once the loopback circuitry  30  completes the loopback signal path, the calibration circuitry  32  operates to provide a test signal to the transmit and receive circuitry  28 . Based on the test signal, the transmit and receive circuitry  28  generates a transmit signal X T . Instead of passing the transmit signal X T  to the amplification and processing circuitry  34 , the loopback circuitry  30  passes the transmit signal X T  to the demodulator  40  of the transmit and receive circuitry  28  as a receive signal X R . Based on the receive signal X R , the transmit and receive circuitry  28  provides orthogonal baseband receive signals I R  and Q R , which are provided to the calibration circuitry  32 . After a series of measurements and calculations, the calibration circuitry  32  generates control signals a T , φ T , θ T , a R , φ R , θ R  for calibrating the transmit and receive circuitry  28 . 
   The control signals a T , φ T , θ T , a R , φ R , θ R  are used to adjust a transmit amplitude error a T , transmit baseband phase error φ T , transmit carrier phase error θ T , receive amplitude error a R , receive baseband phase error φ R  and receive carrier phase error θ R  of the transmit and receive circuitry  28 . The adjustment of a T  and φ T  is implemented in the modulator  38  or in analog baseband circuitry  42 , which precedes the modulator  38 . Generally, the analog baseband circuitry  42  may include circuitry such as filters or buffer amplifiers. The adjustment of θ T  is implemented in circuitry that generates orthogonal transmit carriers for modulation, which may be considered part of the modulator  38  in  FIG. 4 . The adjustment of a R  and φ R  is implemented in the demodulator  40  or in the analog baseband circuitry  42 . The adjustment of θ R  is implemented in circuitry that generates orthogonal receive carriers for demodulation, which is considered to be part of the demodulator  40  in  FIG. 4 . 
   The calibration circuitry  32  includes a baseband test signal generator  44 , a measurement circuitry  46 , and control circuitry  48 . In calibration mode, the test signal generator  44  drives the baseband transmit signals I T  and Q T  with two signals (S 1 , S 2 ) of the same waveform shape and frequency and having a time offset of one quarter of a period. Thus, the fundamentals of I T  and Q T  are of equal amplitude and frequency with a phase difference of essentially 90°. A control signal (LEAD/LAG CONTROL) is provided to the test signal generator  44  and controls the test signal generator  44  such that I T  leads Q T  or I T  lags Q T , which may be accomplished by interchanging the two signals (S 1 , S 2 ). The measurement circuitry  46  measures an amplitude ratio and phase difference of the fundamentals of baseband receive signals I R  and Q R . The control circuitry  48  provides the control signal (LEAD/LAG CONTROL) to the test signal generator  44 , provides a phase switch control signal (PHASE CONTROL) to the loopback circuitry  30 , calculates the errors a T , φ T , θ T , a R , φ R  and θ R  based on the output of the measurement circuitry  46 , provides the control signals for a T , φ T , θ T , a R , φ R  and θ R  to the transmit and receive circuitry  28 , and controls the sequence of steps in the calibration procedure. 
   In one embodiment, the errors a T , φ T , θ T , a R , φ R  and θ R  are calculated from a series of six measurements that are performed during the calibration. Let the measurements be numbered from 1 to 6, as shown in Table 1 below. Although the measurements are numbered from 1 to 6, the measurements may be made in any order. In measurements 1 to 4, the settings of the control signals for a T , φ T , θ T , a R , φ R  and θ R  are at predefined initial values, such as power-on default values or values from a previous calibration. In measurement 1, I T  leads Q T . In measurement 2, I T  lags Q T , and the phase shift of the loopback circuitry  30  is the same as in measurement 1. In measurement 3, I T  leads Q T , and the phase shift of the loopback circuitry  30  differs by 90° from its value in measurements 1 and 2. In measurement 4, I T  lags Q T , and the phase shift of the loopback circuitry  30  is the same as in measurement 3. In measurements 5 and 6, all settings are the same except that of the control input for a T . For this example, I T  leads Q T , and the phase shift of the loopback circuitry  30  is the same as its value in measurements 1 and 2. In measurement 5, the control input for a T  is set to a minimum limit. In measurement 6, the control input for a T  is set to a maximum limit. 
   
     
       
             
           
             
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Example of settings in measurement sequence 
             
           
        
         
             
                 
                 
                 
                 
               Settings of 
             
             
               Measurement 
               I T  leads or 
               Loopback 
               Setting of 
               φ T , θ T , 
             
             
               number 
               lags Q T   
               phase shift 
               a T   
               a R , φ R , θ R   
             
             
                 
             
             
               1 
               Leads 
               +45° 
               Initial 
               Initial 
             
             
               2 
               Lags 
               +45° 
               Initial 
               Initial 
             
             
               3 
               Leads 
               −45° 
               Initial 
               Initial 
             
             
               4 
               Lags 
               −45° 
               Initial 
               Initial 
             
             
               5 
               Leads 
               +45° 
               Minimum 
               Initial 
             
             
               6 
               Leads 
               +45° 
               Maximum 
               Initial 
             
             
                 
             
           
        
       
     
   
   In each measurement, the receive baseband signals I R  and Q R  are of the form
 
 I   R =(1+α n )cos(ω b   t+ψ   n +Γ n )  (13)
 
 Q   R =±sin(ω b   t+Γ   n )  (14)
 
where total amplitude error α n  and total phase error ψ n  represent the combined effect of a T , φ T , θ T , a R , φ R  and θ R  in measurement n and Γ n  is the phase offset between the transmit and receive baseband signals. The phase offset Γ n  is not relevant to the calibration procedure. Let the phase shift of the loopback circuitry  30  in measurements 1 and 2 be Φ +  at ω c +ω b  and Φ −  at ω c −ω b . Then
 
 e   1   =a   R   +j (φ R +θ R )+[ a   T   +j (φ T +θ T )]exp(− j 2Φ)  (15)
 
 e   2   =a   R   +j (φ R −θ R )+[ a   T   +j (φ T −θ T )]exp(+ j 2Φ)  (16)
 
 e   3   =a   R   +j (φ R +θ R )−[ a   T   +j (φ T +θ T )]exp(− j 2Φ)  (17)
 
 e   4   =a   R   +j (φ R −θ R )−[ a   T   +j (φ T −θ T )]exp(+ j 2Φ)  (18)
 
where
 
 e   n =α n   +jψ   n   (19)
 
Φ=½(Φ + +Φ − )−θ  (20).
 
Swapping the signals (S 1 , S 2 ) driving I T  and Q T  inverts the contributions of the carrier phase errors θ T  and θ R  to the error vector e n , thereby allowing the carrier phase errors θ T  and θ R  to be separated from the baseband phase errors φ T  and φ R . Changing the phase shift of the loopback circuitry  30  by 90° inverts the contributions of the transmit errors a T , φ T , and θ T , thereby allowing the transmit errors a T , φ T , and θ T  to be separated from the receive errors a R , φ R , and θ R . The effect of the phase shift in the loopback circuitry  30  and the phase difference θ between the transmit and receive carriers is to rotate the combined contribution of the transmit errors a T , φ T , and θ T  by ±2Φ, so that a correction for this rotation is needed in order to separate the amplitude component a T  from the phase components φ T  and θ T  of the combined transmit error. Measurements 5 and 6 enable this correction to be made.
 
   Let a T  be equal to a TMIN  at the minimum adjustment setting for a T  and a TMAX  at the maximum adjustment setting for a T . If the relative phase of I T  and Q T  and the phase shift of the loopback circuitry  30  are the same in measurements 5 and 6 as in measurement 1, for example, then it follows from Equation 15 that
 
 e   5   =a   R   +j (φ R +θ R )+[ a   Tmin   +j (φ T +θ T )]exp(−2 j Φ)  (21)
 
 e   6   =a   R   +j (φ R +θ R )+[ a   Tmax   +j (φ T +θ T )]exp(−2 j Φ)  (22)
 
Hence, the required rotation angle is given by
 
2Φ=−arg( e   6   −e   5 ),  (23)
 
where the arg( ) function returns the polar angle of a rectangular coordinate pair represented by a complex number, and from Equations 15 to 18, it follows that
 
 a   R =¼ Re ( e   1   +e   2   +e   3   +e   4 )  (24)
 
φ R =¼ Im ( e   1   +e   2   +e   3   +e   4 )  (25)
 
θ R =¼ Im ( e   1   −e   2   +e   3   −e   4 )  (26)
 
 a   T =¼ Re [( e   1   −e   3 )exp(2 j Φ)+( e   2   −e   4 )exp(−2 j Φ)]  (27)
 
φ T =¼ Im [( e   1   −e   3 )exp(2 j Φ)+( e   2   −e   4 )exp(−2 j Φ)]  (28)
 
θ T =¼ Im [( e   1   −e   3 )exp(2 j Φ)−( e   2   −e   4 )exp(−2 j Φ)]  (29)
 
   After calculating the errors a T , φ T , θ T , a R , φ R  and θ R , the control circuitry  48  updates the settings of the control signals for a T , φ T , θ T , a R , φ R  and θ R  to correct these errors. Depending on the amount by which the settings are changed and the accuracy of the adjustment circuitry, further measurement and update cycles may be needed until the errors are as close to zero as the resolution and range of the adjustments will allow. Also, changes that are smaller than the measured errors have the advantage of de-emphasizing noise. In normal operation of the transceiver  24  after calibration, the control circuitry  48  maintains the settings of a T , φ T , θ T , a R , φ R  and θ R  that were established at the conclusion of the calibration procedure. 
   The control circuitry  48  of the calibration circuitry  32  of  FIG. 4  provides both a full and an incremental calibration. The full calibration is performed in one uninterrupted time interval, during which the error measurements and adjustment updates are performed as many times as are needed to ensure that the errors are fully minimized. The incremental calibration is performed as a sequence of partial calibrations in separate time intervals, and the update of the error adjustments occurs after a defined number of partial calibrations. 
   In normal transmit and receive operation of the transceiver  24 , the data traffic occurs in separate packets. In addition to its transmit, receive and calibration modes, the transceiver  24  also has an idle mode that it enters during short intervals between data packets, and a reset mode that it enters after being powered up and during long intervals without data traffic. In one embodiment, a full calibration is initiated automatically when the transceiver  24  enters idle mode from reset mode. In one embodiment, a partial incremental calibration, which is short enough to fit into the minimum interval between data packets, is initiated automatically when the transceiver  24  enters idle mode from transmit or receive mode. The purpose of the incremental calibration is to correct any drift in the amplitude and phase errors due to temperature changes since a previous full calibration. 
   The calibration procedure can be divided into three steps. Referring to table 1 above, in step 1, measurements 5 and 6 are performed to determine Φ using Equation 23. In step 2, measurements 1 to 4 are performed to determine e 1  to e 4  in Equations 24 to 29. In step 3, a T , θ T , φ T , a R , θ R  and φ R  are calculated, and the corresponding adjustment inputs are updated to correct the errors. In one embodiment, the magnitude of the correction is approximately one half of the measured error. The full calibration performs the steps in the sequence 1-2-3-2-3-2-3-2-3. In one embodiment, the full calibration takes approximately 81 μs. The incremental calibration performs the steps in the sequence 1-2-3-1-2-3-1-2-3- . . . In one embodiment, each partial calibration is performed in a time interval of 5.5 μs or less. After a predetermined number of partial calibrations have been performed, the error adjustments are updated. 
     FIG. 5  illustrates one embodiment of the measurement circuitry  46 . In this embodiment, the measurement circuitry  46  includes an analog-to-digital converter (ADC)  50 , two multipliers  52  and  54 , four accumulators  56 – 62  and two coordinate rotation digital computers (CORDICs)  64  and  66 , designated as a master CORDIC and a slave CORDIC. The ADC  50  alternately samples I R  and Q R  based on an I/Q select signal (I/Q SELECT), thereby providing measurements of each of the signals I R  and Q R  with equal gain. The multipliers  52  and  54  multiply the ADC output with sine and cosine functions at the baseband signal frequency ω b . For each of the multipliers  52  and  54 , there are two accumulators  56 ,  58  and  60 ,  62 , respectively. The accumulators  56  and  60  integrate the result of the multiplication of I R  with the sine or cosine function, and the accumulators  58  and  62  integrate the result of the multiplication of Q R  with the sine or cosine function. The integration is performed over an integer number of periods of the baseband frequency ω b , such that at the end of the integration, the outputs of the accumulators are equal to the real and imaginary parts of the complex Fourier coefficients of the fundamentals of I R  and Q R . 
   Let the Fourier coefficients of the fundamentals of I R  and Q R  be I cos +jI sin  and Q cos +jQ sin  respectively. From Equations 13 and 14, it follows that
 
 I   cos =(1+α n )cos(ψ n +Ψ)  (30)
 
 I   sin =−(1+α n )sin(ψ n +Ψ)  (31)
 
 Q   cos =±cos Ψ  (32)
 
 Q   sin =±sin Ψ  (33)
 
where ψ is the phase offset between I R  and Q R  and the cosine and sine functions with which they are multiplied. The master CORDIC  64  rotates I cos +jI sin  until its imaginary part is equal to zero, and the slave CORDIC  66  rotates Q cos +jQ sin  by the same amount. Let the output of the master CORDIC  64  be I′ cos +jI′ sin  and the output of the slave CORDIC  66  be Q′ cos +jQ′ sin . Then
 
 I′   cos =1+α n   (34)
 
 I′   sin =0  (35)
 
 Q′   cos =±cos ψ n   (36)
 
 Q′   sin =∓sin ψ n   (37)
 
In this way, the values of e n =α n +jψ n  that are needed to calculate a T , φ T , θ T , a R , φ R  and θ R  using Equations 24 to 29 are obtained. The parameter 2Φ in Equation 29 is determined by rotating e 6 −e 5  until its imaginary part is equal to zero. The resulting value is stored and used to perform the de-rotations of e 1  to e 4  by ±2Φ in Equations 26 to 28.
 
   In one embodiment, the ADC  50  in the measurement circuitry  46  is of the successive approximation type, with a resolution of 8 bits and a sample rate of 34 Msamples/s, and is clocked at the carrier frequency ω C , with 11 clock periods per sample. Since the ADC input switches between I R  and Q R  on successive samples, each is sampled at 17 Msamples/s. The integration in the accumulators  56 – 62  is performed over an interval of 2 μs, which is equal 34 sampling periods and 10 periods of the baseband frequency. In this embodiment, the sample rate has the advantage that most of the harmonics of the baseband test signals S 1  and S 2  from the test signal generator  44  are rejected by the integration process. 
     FIG. 6  shows a second embodiment of the transceiver  24  of the present invention. The transceiver  24  is may be used in wireless LANs based on the IEEE standard 802.11g. A heterodyne architecture is used in both the transmit and receive signal paths, with a common intermediate frequency (IF). In one embodiment, the common IF frequency is 374 MHz. In this embodiment, the loopback circuitry  30  includes an IF band-pass filter  68  that is shared by the transmit and receive signal paths. 
   In normal transmit operating mode, the signal path for the transmit signals I T  and Q T  to the antenna  36  includes low-pass baseband filters  70  and  72 , the modulator  38 , the IF band-pass filter  68 , a variable-gain amplifier (VGA)  74 , an up-conversion mixer  76 , a driver amplifier  78 , a power amplifier (PA)  80  and a transmit-receive switch  82 . In normal receive operating mode, the signal path from the antenna  36  to the receive signals I R  and Q R  includes the transmit-receive switch  82 , a low-noise amplifier (LNA)  84 , a down-conversion mixer  86 , the IF band-pass filter  68 , a VGA  88 , the demodulator  40 , and low-pass baseband filters  90  and  92  for each of the signals I R  and Q R . 
   In calibration mode, the modulator  38 , the demodulator  40 , the baseband filters  70 ,  72 ,  90 , and  92  and the calibration circuitry  32  are enabled. The loopback circuitry  30  implements the loopback path by enabling the receive VGA  88  and disabling the down-conversion mixer  86 , so that the modulator  38  drives the demodulator  40  via the IF filter  68  and the receive VGA  88 . Since the transmit VGA  74 , the up-conversion mixer  76 , the driver amplifier  78 , the PA  80  and the LNA  84  are not needed in calibration mode, they may also disabled. 
   One embodiment of phase switching circuitry  94  in the loopback circuitry  30  is implemented by an RC (resistor-capacitor) element, as shown in  FIG. 7 . As illustrated, the phase switching circuitry  94  includes resistor (R), capacitor (C), and switches (SW 1 –SW 3 ) arranged as shown. By forcing the first and second switches (SW 1  and SW 2 ) to their respective first positions (1), the phase switching circuitry  94  is configured as a high-pass filter with a cut-off frequency nominally equal to the IF carrier frequency. By forcing the first and second switches (SW 1  and SW 2 ) to their respective second positions (2), the phase switching circuitry  94  is configured as a low-pass filter with a cut-off frequency nominally equal to the IF carrier frequency. Because the cut-off frequency is the same for each configuration, the difference in phase shift between the two configurations is 90°. In normal operation of the transceiver  24 , the phase switching circuitry  94  is by-passed by closing the third switch (SW 3 ) to avoid degrading the performance of the receiver. 
     FIG. 8  illustrates one embodiment of the test signal generator  44  of  FIGS. 4 and 6 . A local oscillator  96  generates a reference frequency (F REF ). The reference frequency (F REF ) may also be used by the transceiver  24  to generate frequencies for upconversion and downconversion. The reference frequency (F REF ) is divided by four using two cascaded dividers  98  and  100 . In one embodiment, the dividers  98  and  100  are master-slave toggle flip-flops. The orthogonal outputs of the second divider  100  control switches SW 4  and SW 5 , thereby switching the outputs of the test signal generator  44  between a low and a high reference voltage, resulting in square waves with 90° phase difference. Switches SW 6  and SW 7  are controlled such that the output signal S 1  either leads or lags the output signal S 2 . The use of the dividers  98  and  100 , which in this embodiment divide by two, ensures that the accuracy of the output phase difference is independent of the duty cycle of the reference frequency (F REF ). The technique of switching between the same low and high reference voltages at each output ensures equal amplitudes for the two output waveforms. With a carefully optimized layout, the test signal generator  44  can achieve an amplitude matching accuracy of 0.01 dB and a phase accuracy of 0.1°. 
   The transmit and receive amplitude errors a T  and a R  are adjusted by switching additional resistors in parallel with gain-determining resistors in the analog baseband signal paths.  FIG. 9  illustrates one embodiment of the baseband filters  70 ,  72 ,  90 , and  92 . In this embodiment, each of the baseband filters  70 ,  72 ,  90 , and  92  is implemented as active RC, third order Bessel filter  102 . The filter  102  includes resistors R 1 –R 3  and capacitors C 1 –C 3  arranged as shown. In this embodiment, the transmit and receive amplitude errors a T  and a R  are adjusted by adjusting a resistance of a variable resistor R V . The variable resistor R V  may be a single variable resistor or plurality of resistors switchably connected to the filter  102 . The transmit and receive baseband phase errors φ T  and φ R  are adjusted by varying a bias current of an amplifier  104 , thereby changing the gain-bandwidth product of the amplifier  104  and thus the cut-off frequency and phase shift of the filter  102 . 
   The baseband phase errors are a function of the baseband frequency. In one embodiment, calibration is performed at a baseband frequency of near the middle of the band of the baseband signals I T , Q T , I R , and Q R . For example, the baseband signals I T , Q T , I R , and Q R  may have a bandwidth of 8.5 MHz and the calibration is performed at 5 MHz. The choice of a calibration frequency near the middle of the band reflects the fact that the phase accuracy relates to the average phase error over the bandwidth of the modulated signal. The technique of adjusting the baseband phase errors φ T  and φ R  by changing the bandwidth of the baseband filters  70 ,  72 ,  90 , and  92  reflects the fact that the dominant cause of the baseband phase errors φ T  and φ R  is mismatch between the baseband filters  70 ,  72 ,  90 , and  92 . 
     FIG. 10  illustrates one embodiment of carrier generation circuitry  106 , which generates the orthogonal carriers used by the modulator  38  and demodulator  40 . The circuitry  106  includes a frequency synthesizer  108  operating at twice the carrier frequency ω C  and that drives dividers  110  and  112 . In one embodiment, the dividers  110  and  112  are in the form of a master-slave toggle flip-flop. Based on the output of the frequency synthesizer  108  the dividers  110  and  112  generate orthogonal transmit and receive carriers each at the carrier frequency ω C  for modulator  38  and demodulator  40 , respectively. The transmit and receive carrier phase errors θ T  and θ R  are adjusted by introducing an offset voltage at the input of the dividers  110  and  112 , which shifts the positive and negative zero crossings of the input waveform in opposite directions in time, and hence shifts the phase of the divider outputs relative to each other. 
   In one embodiment, a 5-bit adjustment with a nominal least significant bit (LSB) step of 0.04 dB and a nominal range of −0.60 dB to +0.60 dB is provided for each of 1+a T  and 1+a R , and a 4-bit adjustment with a nominal LSB step of 0.4° and a nominal range of −2.8° to +2.8° is provided for φ T , θ T , φ R  and θ R . These ranges allow sufficient margin for mismatches in the signal path circuitry before calibration and for the tolerances of the adjustment circuitry, and the resolutions allow sufficient margin for errors in the generation of I T  and Q T  and in the measurement of I R  and Q R . Further, the calibration according to the present invention reduces amplitude errors to ≦0.1 dB for 1+a T  and 1+a R  and the phase errors to ≦1° for φ T ±θ T  and φ R ±θ R . 
   The transceiver  24  of  FIGS. 4 and 6  provides substantial opportunity for variation without departing from the spirit and scope of the present invention. For example, the control circuitry  48  may use the transmit VGA  74  to control the gain in the loopback circuitry  30  such that the amplitude of the baseband receive signals I R  and Q R  at the input of the measurement circuitry  46  is close to full-scale, thereby maximizing the accuracy of analog-to-digital conversion within the measurement circuitry  46 . As another example, the adjustment of one or more of the transmit amplitude error a T , transmit baseband phase error φ T , receive amplitude error a R  and receive baseband phase error φ R  may be implemented in the baseband processor  26 . As another example, the baseband test signals S 1  and S 2  may be generated at a different point before the modulator  38  in the transmit signal path other than the point shown in  FIGS. 4 and 6 . As another example, the receive baseband signals I R  and Q R  may be measured at any point at or after the outputs of the demodulator  40  in the receive signal path. Also, the baseband test signals S 1  and S 2  may be generated in the baseband processor  26  using the same circuitry as is used to generate the transmit signals I T  and Q T  in normal operation, so that the calibration also corrects the contribution of the baseband processor  26  to the transmit amplitude and phase errors a T , φ T , and θ T  The receive baseband signals I R  and Q R  may be measured in the baseband processor  26  using the same circuitry as is used to process the receive signals I R  and Q R  in normal operation, so that the calibration also corrects the contribution of the baseband processor  26  to the receive amplitude and phase errors a R , φ R , and θ R . The transmit errors a T , φ T , and θ T  may be separated from the receive errors a R , φ R , and θ R  by swapping the orthogonal carriers ( FIG. 10 ) in either the modulator  38  or the demodulator  40 , which is equivalent to switching the phase shift of the loopback circuitry  30  by 90°. The combined effect of the phase shift of the loopback circuitry  30  and the phase difference between the transmit and receive carriers can be measured by switching the adjustment settings for any of the following between any two different values: transmit amplitude error a T , transmit baseband phase error φ T , and transmit carrier phase error θ T . The calibration circuitry  32  may control the gain at any point in the signal path in order to control the signal amplitude at the point where the receive baseband signals I R  and Q R  are measured. 
   Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.