Abstract:
In one embodiment, an integrated circuit (IC) such as a programmable logic device includes a plurality of IC input terminals and an input buffer having a buffer input terminal and a buffer output terminal. A multiplexer is adapted to selectively couple an IC input terminal to the buffer input terminal or to couple the buffer output terminal to the buffer input terminal.

Description:
RELATED APPLICATION DATA 
   This application is a continuation of U.S. application Ser. No. 12/107,883, filed Apr. 23, 2008, which is incorporated by reference in its entirety. 

   TECHNICAL FIELD 
   The present invention relates generally to electrical circuits and, more particularly, to power management techniques for programmable logic devices. 
   BACKGROUND 
   A programmable logic device (PLD, e.g., a field programmable gate array (FPGA) or a complex programmable logic device (CPLD)) may be used in a variety of applications and may provide certain advantages over other types of devices. For example, a PLD offers the advantage of being reprogrammable in the field (e.g., a field update, with the PLD in its operational environment). 
   A conventional PLD may be designed for low power applications (e.g., referred to as low power, ultra low power, or zero power PLD) and may provide, for example, a very low standby current (SICC) and consume very little power when PLD signals are not active. For example, PLD signals may include signals to input buffers (e.g., via an input pin) and signals within the PLD (e.g., signals being driven by the input buffers). 
   A common technique to reduce PLD power usage is to deactivate certain signals, as needed, which are not required to be active. A conventional PLD approach may statically and/or dynamically allow a user of the PLD to deactivate certain internal PLD signals. However, a drawback with this conventional approach is that it only addresses internal PLD signals and does not address power usage of the input buffers or associated circuitry. 
   As a result, there is a need for improved power management techniques for PLDs. 
   SUMMARY 
   In accordance with one embodiment of the present invention, an integrated circuit (IC) such as a programmable logic device includes a plurality of IC input terminals; an input buffer having a buffer input terminal and a buffer output terminal; and a multiplexer adapted to selectively couple an IC input terminal to the buffer input terminal or to couple the buffer output terminal to the buffer input terminal. 
   The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a block diagram illustrating an example of a programmable logic device in accordance with an embodiment of the present invention. 
       FIG. 2  shows a block diagram illustrating an example of a programmable logic device in accordance with an embodiment of the present invention. 
       FIG. 3  shows a block diagram illustrating an example of a circuit implementation for a portion of the programmable logic device of  FIG. 1  or  FIG. 2  in accordance with an embodiment of the present invention. 
       FIG. 4  shows a block diagram illustrating an example of a circuit implementation for a portion of the programmable logic device of  FIG. 1  or  FIG. 2  in accordance with an embodiment of the present invention. 
       FIG. 5  shows a block diagram illustrating an implementation example for signal generation within the programmable logic device of  FIG. 1  or  FIG. 2  in accordance with an embodiment of the present invention. 
   

   Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. 
   DETAILED DESCRIPTION 
     FIG. 1  shows a block diagram illustrating a programmable logic device (PLD)  100  in accordance with an embodiment of the present invention. PLD  100  (e.g., a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other type of programmable device) may generally include input/output (I/O) blocks  102  and logic blocks  104  (e.g., also referred to as programmable logic blocks (PLBs), programmable functional units (PFUs), generic logic blocks (GLBs), or programmable logic cells (PLCs)). I/O blocks  102  provide I/O functionality (e.g., supports one or more I/O and/or memory interface standards) for PLD  100 , while programmable logic blocks  104  provide logic functionality (e.g., LUT-based logic or logic gate array-based logic) for PLD  100 . 
   PLD  100  may also include blocks of memory  106  (e.g., blocks of EEPROM, block SRAM, and/or flash memory), clock-related circuitry  108  (e.g., PLL and/or DLL circuits), configuration logic  110  (e.g., for startup, decryption, encryption, multiple-boot support, such as dual boot support, and/or error detection), a configuration port  112 , configuration memory  114 , special function blocks  116  (e.g., DSP blocks or other forms of multiply and accumulate circuit functionality), and/or routing resources  118 . In general, the various elements of PLD  100  may be used to perform their intended functions for the desired application, as would be understood by one skilled in the art. 
   For example, configuration port  112  may be used for programming PLD  100 , such as memory  106  and/or configuration memory  114  or transferring information (e.g., various types of data and/or control signals) to/from PLD  100  as would be understood by one skilled in the art. For example, configuration port  112  may include a first programming port (which may represent a central processing unit (CPU) port, a peripheral data port, a serial peripheral interface, and/or a sysCONFIG programming port) and/or a second programming port such as a joint test action group (JTAG) port (e.g., by employing standards such as Institute of Electrical and Electronics Engineers (IEEE) 1149.1 or 1532 standards). Configuration port  112  typically, for example, may be included to receive configuration data and commands to support serial or parallel device configuration and information transfer. 
   In general, it should be understood that the elements are illustrated in block form for clarity and that certain elements, such as for example configuration memory  114  or routing resources  118 , would typically be distributed throughout PLD  100 , such as in and between logic blocks  104 , to perform their conventional functions (e.g., storing configuration data that configures PLD  100  or providing interconnect structure within PLD  100 , respectively). 
   Furthermore, it should be understood that the number and placement of the various elements, such as I/O blocks  102 , logic blocks  104 , memory  106 , clock-related circuitry  108 , configuration logic  110 , configuration port  112 , configuration memory  114 , special function blocks  116 , and routing resources  118 , are not limiting and may depend upon the desired application. For example, special function blocks  116  are optional and various other elements of PLD  100  may not be required or may be of a simplified version or related type of circuit based upon the desired application or design specification (e.g., for the type of programmable device selected), as would be understood by one skilled in the art. 
   PLD  100 , as noted herein, may represent any type of programmable device. For example, PLD  100  may represent a CPLD and be implemented as a PLD  200  as shown in  FIG. 2  in accordance with an embodiment of the present invention. Thus, as shown in  FIG. 2 , PLD  200  may include I/O blocks  102 , logic blocks  104 , and routing resources  118  (e.g., a global routing pool (GRP) and/or output routing pools (ORPs)). As an example, one or more I/O blocks  102  may be organized into I/O banks, such as shown for an I/O bank  202  (e.g., I/O bank  0 ) and an I/O bank  204  (e.g., I/O bank  1 ). 
   In accordance with one or more embodiments of the present invention, one or more I/O blocks  102  (within PLD  100  and/or PLD  200 ) may be implemented with techniques disclosed herein to reduce power consumption. For example,  FIG. 3  shows a block diagram illustrating a circuit  300 , which may be implemented within a portion of one or more I/O blocks  102  in accordance with an embodiment of the present invention. Circuit  300  includes a multiplexer  304  and an input buffer  306 . 
   Multiplexer  304  (e.g., a two-to-one multiplexer) may be disposed between an input terminal  302  (e.g., input or I/O pin to PLD  100  or  200 ) and input buffer  306 . Consequently, if multiplexer  304  is controlled (e.g., by a user of the PLD) to select path  1 , then input terminal  302  is coupled to input buffer  306  (e.g., input buffer  306  is coupled to input terminal  302  in a conventional fashion). However, if multiplexer  304  is controlled to select path  0 , then an output terminal  308  of input buffer  306  is coupled to its input terminal  310  (via the path  0  of multiplexer  304  as shown in  FIG. 3 ), which isolates input terminal  302  from input buffer  306 . 
   The implementation of multiplexer  304  with input buffer  306 , in accordance with an embodiment, may be referred to herein as a power guard (PG) technique and may allow a user to selectively isolate input buffer  306  within I/O block  102  from input terminal  302 . Thus, any active signal received by input terminal  302  (e.g., toggling of the input terminal  302 ) may be blocked from being received by input buffer  304  and, therefore, there is no resulting power consumption (e.g., no dynamic ICC or dynamic power consumption) by input buffer  304  due to this active signal. Furthermore, with input buffer  304  isolated from input terminal  302 , other internal signals that may be provided, for example, by input buffer  304  to routing resources  118  (e.g., to GRP) or to logic blocks  104  (e.g., to macrocells within logic blocks  104 ) may also be isolated from activity on input terminal  302 , which may provide further dynamic power savings. Thus, input buffer  304  may be isolated along with internal signals that may be driven by input buffer  304  or internal signals and circuit elements otherwise associated with (e.g., downstream of) input buffer  304  (e.g., downstream buffers and associated signals are likewise isolated). 
   Multiplexer  304  may be controlled in a conventional fashion by applying a control signal on a control terminal  312  of multiplexer  304 . The control signal on control terminal  312  may be provided, in accordance with an embodiment, via logic  314  (e.g., an OR gate) that may receive one or more signals. For example, an input enable (IE) signal (e.g., a global input enable (GIE) signal) may be provided via logic  314  to dynamically (e.g., after configuration and during a user mode of operation of the PLD) control multiplexer  304  based on user control or by logic during user mode of operation. As discussed further herein, the IE signal may be generated based on a global output enable (GOE) signal in accordance with an embodiment. As another example, a disable fuse (DF) signal (e.g., power guard disable fuse or PGDF) may be provided from a fuse  316  (e.g., any type of volatile or nonvolatile memory cell, such as a static random access memory cell or a flash memory cell, respectively) via logic  314  to statically (e.g., set during configuration of the PLD) control multiplexer  304 . 
   As another example,  FIG. 4  shows a block diagram illustrating a circuit  400 , which may be implemented within a portion of one or more I/O blocks  102  (e.g., of  FIG. 1  or  FIG. 2 ) in accordance with an embodiment of the present invention. Circuit  400  may represent an I/O cell within I/O block  102 , with circuit  400  including various techniques discussed in reference to  FIG. 3 . 
   Circuit  400  includes input terminal  302 , multiplexer  304 , and input buffer  306  and further includes a multiplexer  404  and an output buffer  406 . The discussion for multiplexer  304  and input buffer  306 , as set forth in reference to  FIG. 3 , will not be repeated. However, it is noted that logic  314  for this example is represented by an AND gate, with logic values of the input enable (IE) signal and the disable fuse (DF) signal being applied appropriately, as desired, to control multiplexer  304 , as would be understood by one skilled in the art. 
   Multiplexer  404  may represent an output multiplexer that receives various output enable signals  408  that may be selected to control output buffer  406 . A programmable I/O bus maintenance circuit  402  may also be provided, as would be understood by one skilled in the art. 
     FIG. 5  shows a block diagram illustrating a circuit  500 , which represents an implementation example for signal generation for PLD  100  ( FIG. 1 ) or PLD  200  ( FIG. 2 ) in accordance with an embodiment of the present invention. Circuit  500 , for example, illustrates a four-bit wide global output enable (GOE) bus  502  (e.g., derived from a four-bit internal global OE product term (PT) bus and two dual purpose input/output (I/O) or GOE pins), which in conjunction with a global fuse circuit block  504  (e.g., including various multiplexers and fuses) may provide various GOE signals (e.g., GOE 1  through GOE 3 ) and the GIE signal (e.g., the IE signal of  FIG. 3  or  FIG. 4 ), as would be understood by one skilled in the art. 
   Systems and methods are disclosed herein to provide improved power management techniques in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment of the present invention, techniques are disclosed to reduce PLD standby current within a PLD. As a specific example for an embodiment, an enable signal may be used to optionally isolate inputs (e.g., input buffers and/or input terminal signals, such as for clock, data, or other types of buffers and input terminals), such that if inputs are toggled there would not be a resulting internal dynamic power consumption (e.g., this technique may be referred to herein as a power guard (PG) for a PLD (e.g., a CPLD)). The enable signal, for example, may be provided by a global control signal (e.g., internally generated dynamically or statically) or by a static local (or global) control signal (e.g., via an SRAM cell (fuse)), which enables or disables the PG technique for selected inputs (e.g., mutually exclusive with the GOE 3  signal for an example disclosed herein). 
   In general for example, some conventional approaches fail to isolate PLD signals from toggling pins on the system board and thus, do not provide adequate dynamic power savings as discussed herein. In contrast for some embodiments, the PG technique may allow a user to reduce the dynamic power, even if I/Os that may be tied to traces on the system board are still toggling (e.g., resulting in dynamic ICC within a conventional PLD). 
   The techniques (e.g., PG techniques) may be implemented to reduce power usage by selectively and dynamically (i.e., after configuration and during user operation) disabling various signals (e.g., signals associated with input buffers and signals being driven by input buffers or associated with signals being driven by input buffers). As a specific example for one embodiment, Table 1 shown below illustrates an example for using techniques disclosed herein for various situations to reduce power consumption within a PLD implemented with techniques (e.g., PG techniques) disclosed herein (e.g., in reference to  FIGS. 4 and 5 ). 
   In general in accordance with an embodiment, the GIE signal may represent a global signal that dynamically enables or disables the input buffer participation in the PG feature for the I/O or input terminals that have the PG feature enabled by the PGDF fuse. The GIE signal may be generated, as a specific example, from the GOE 3  signal. For example for an embodiment, a PLD with the PG feature may be compatible with prior designs by simply using only the GOE 3  signal and not using the GIE signal (e.g., unused, tied to logical low (0)). As another example for an embodiment, the PG feature may be used, while the GOE 3  signal is not used (e.g., for enabling/disabling output buffers), and thus the GIE signal may be used to enable/disable participation of selected input buffers for the PG feature. As another example for an embodiment, the PG feature and the GOE 3  signal may be used, with the GOE 3  signal controlling certain selected output buffers (e.g., enabled when the GOE 3  signal is at a logical high (=1) and disabled otherwise) and the GIE signal controlling certain selected input buffers (e.g., inputs enabled when the GIE signal is at a logical high (=1) and disabled to save dynamic power when the GIE signal is at a logical low (=0)). 
   
     
       
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
               Situation 
               GIE Signal 
               PGDF Fuse 
               Comments 
             
             
                 
             
           
           
             
               User Does 
               Not Asserted 
               Provides 
               Use PG feature to 
             
             
               Not Use 
               (e.g., tied low 
               Logical Low 
               reduce dynamic 
             
             
               PG 
               (= 0)) 
               (= 0) for unused 
               ICC for output- 
             
             
               Feature 
                 
               input 
               only I/Os and/or 
             
             
                 
                 
               terminals; 
               unused input 
             
             
                 
                 
               Provides 
               terminals 
             
             
                 
                 
               Logical High 
             
             
                 
                 
               (= 1) for used 
             
             
                 
                 
               input terminals 
             
             
                 
                 
               or I/O 
             
             
               User uses 
               Tied to a live 
               Provides 
               PG feature 
             
             
               PG 
               signal via GOE3 
               Logical High 
               selected to 
             
             
               Feature 
               PT; 
               for input 
               reduce power 
             
             
                 
               User&#39;s logic 
               terminals or 
               consumption on 
             
             
                 
               may drive 
               I/Os that do 
               unused input 
             
             
                 
               GOE3 = GIE = 0 to 
               not participate 
               terminals or I/Os 
             
             
                 
               disable 
               in PG feature 
               if the GTE 
             
             
                 
               selected output 
               (PG disabled); 
               signal = 0 
             
             
                 
               and input 
               Provides 
             
             
                 
               buffers to 
               Logical Low 
             
             
                 
               reduce power 
               (= 0) for input 
             
             
                 
               consumption 
               terminals or 
             
             
                 
                 
               I/Os that 
             
             
                 
                 
               participate in 
             
             
                 
                 
               PG feature via 
             
             
                 
                 
               the GTE signal; 
             
             
                 
                 
               Provides 
             
             
                 
                 
               Logical Low 
             
             
                 
                 
               (= 0) for unused 
             
             
                 
                 
               input terminals 
             
             
                 
                 
               or I/Os 
             
             
               Blank 
               Not Asserted 
               Provides 
               Provides 
             
             
               Device - 
               (e.g., tied low 
               Logical High 
               conventional PLD 
             
             
               Bulk 
               (= 0)) 
               (= 1) 
               functionality 
             
             
               Erase 
             
             
                 
             
           
        
       
     
   
   In accordance with an embodiment and referring generally to  FIGS. 1-5 , a device  150  (e.g., a computer as shown in  FIG. 1 ) may be used to run PLD design tool software stored in memory  152  ( FIG. 1 ) to perform the PLD design process and to generate configuration data and program the PLD (e.g., PLD  100  or PLD  200 ) according to the techniques disclosed herein, as would be understood by one skilled in the art. Memory  152  may be a permanent memory (e.g., a fixed hard drive) within device  150  or may represent portable memory (e.g., portable hard drive, compact disk, flash memory, or other type of memory) capable of storing the PLD design tool software and couplable to device  150  to allow access to the information within memory  152 . As a specific example, the PLD design tool software would incorporate the techniques disclosed herein, as would be understood by one skilled in the art, to permit a user to set the PGDF fuse, generate the desired internal signals (e.g., the GIE signal), and configure the PLD (e.g., including I/O blocks  102 , logic blocks  104 , and routing resources  118 ) to perform the functions desired by a user. 
   Embodiments described above illustrate but do not limit the invention. For example, the input buffer and multiplexer in other embodiments need not be implemented within an I/O block. It should also be understood that numerous modifications and variations are possible in accordance with the principles of the present invention. Accordingly, the scope of the invention is defined only by the following claims.