Abstract:
A computer program product for verifying an asynchronous circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps of (a) and (b). The step (a) includes the step of carrying out a function simulation of an asynchronous circuit based on circuit information of the asynchronous circuit including a sequential circuit stored in a storage device. The step (b) includes the step of monitoring an output value from an output node of the sequential circuit every unit time, and setting the output value in n time as a value of a metastable state, when the output vale in the n time is changed from the output value in (n−1) time.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to an apparatus, a method and a program for verifying an asynchronous circuit. More particularly, the present invention relates to an apparatus, a method and a program for verifying an asynchronous circuit, which execute function simulations at a language level for verifying the asynchronous circuit.  
         [0003]     2. Description of the Related Art  
         [0004]     The recent advancement of a semiconductor technology has been outstanding. For example, with an advancement of ultra-fine structure, a size of a circuit installed in a semiconductor chip has been increasing. This size increasing leads to increase processing time for a function simulation, when a computer executes a circuit design. In the function simulation, when an asynchronous circuit is included in a simulation target, an asynchronous input signal, whose cycle should be variable, is supplied to a function simulator. That results in further increase of the processing time.  
         [0005]     As a solution to this problem, a conventional technique of Japanese Laid Open Patent Application (JP-P 2003-233638A) discloses a method for verifying an asynchronous circuit and its program. This method of verifying the asynchronous circuit verifies the asynchronous circuit constituted by sequential circuits which are verification targets by using a function simulation apparatus of a language level. This is characterized in that: transiently storing an input data for each event occurring time in one clock cycle for inner array elements preliminarily provided in the sequential circuits to hold values of the input data correspondingly to a plurality of times; when an active edge of a clock signal is detected, if the input data is changed from a value in a time previous of the active edge detection, defining this state as a metastable state; generating and outputting a value of the metastable state, and outputting the input data of any one time among the input data transiently stored for each event generation time, after a next one time.  
         [0006]     Japanese Laid Open Patent Application (JP-P 2003-233638A) will be described in detail below.  FIG. 1  is a flowchart showing the method for verifying the asynchronous circuit in the conventional technique.  FIG. 1  shows an operation flow of a function simulation for sequential circuits, operated in a computer.  
         [0007]     At first, at S 111 , the sequential circuit holds a value Din of an input data at a current time in an inner array element D[0]. Here, the inner array element is the array element possessed by each of flip-flop (hereinafter referred to as FF)  1 , FF 2  and FF 3  of the sequential circuits. The inner array element holds the value of the input data Din in each FF, correspondingly to n number of times. The inner array element D has n number of array elements. The symbol n is assumed to be a value smaller than the number of events in one clock cycle used in the function simulation. The inner array element holds the input data value as follows. That is, in the inner array element, as time advances, the value is sequentially shifted such that the value of D[0] is shifted to D[1] and the value of D[n−1] is shifted to D[n]. Thus, the inner array element holds the values D[0] to D[n] corresponding to the n number of times.  
         [0008]     Next, in a clock signal active edge detecting process at S 112 , an edge detection of the clock signal supplied to the sequential circuit is carried out. If an edge is detected (S 112 : Yes), an input data change detecting process at S 113  is carried out. If the edge is not detected (S 112 : No), the processes of S 123  and S 122  are carried out.  
         [0009]     In the input data change detecting process at S 113 , the change detection in the input data supplied to the sequential circuit is carried out. If the change is detected (S 113 : Yes), a metastable state detecting process at S 114  is carried out. If the change is not detected (S 113 : No), the processes at S 120 , S 121  and S 122  are carried out.  
         [0010]     In the metastable state detecting process at S 114 , a value of a metastable state flag is checked. If the value of the metastable state flag is “true”=it is in the metastable state (S 114 : Yes), the metastable state flag is set to “false” at S 115 . After that, at S 116 , as the input data to the sequential circuit, the value of any element m of the inner array element D[m] (0≦m≦n) held at the foregoing S 111  is held in a storage variable d. In succession, at S 117 , the value in the metastable state is generated by using a random number, and the generated value is held as a variable meta. Finally at S 118 , the value of the metastable state of the variable meta is outputted to an output Qout of the sequential circuit. Also, if the value of the metastable state flag is not “false”=it is not in the metastable state (S 114 : No), the metastable state flag is set to “true” at S 119 . Then, the processes at S 116 ,  5117  and S 118  similar to the above-mentioned explanation are performed in turn.  
         [0011]     However, the metastable state implies that the output signal becomes unstable (metastable) because a setup time or a hold time does not meets the requirement of the input signal of a latch or flip-flop (FF). When an external asynchronous signal is synchronized in the flip-flop, a time when the input signal is changed is not identified. Thus, it is difficult to avoid the occurrence of the metastable state. However, if a situation of the occurrence of the metastable state can be checked, it is possible to design the configuration of the circuit where there is no problem even though the metastable state may occur. Here, the value of the metastable state is exemplified as a random number, any fixed value, a pseudo random number based on a certain initial value, and the like.  
         [0012]     In the processes at S 120 , S 123 , the value of the metastable state flag is set to the value showing that it is not in the metastable state=“false”, similarly to the foregoing S 115 . In the process at S 121 , the value of the input data Din to the sequential circuit is hold in the variable d, similarly to the foregoing S 116 . In the process at S 122 , the value held in the variable d is outputted to the output Qout of the sequential circuit. Consequently, in the process at S 116  after the metastable state detecting process at S 114 , the operation for holding the input data different from each other, between the sequential circuits where the same data signals triggered by the same clock signal are used as the input data. In addition, in the series of the processes at S 117  and S 118 , the operation for outputting the value of the metastable state can be carried out in the event that the value of the input data is changed from the value of the previous time when the clock signal is active.  
         [0013]     Also, in the series of the processes at S 120 , S 121  and S 122  after the input data change detecting process at S 113 , the operation can be carried out in the case that the value of the input data is not changed from the value of the previous time when the clock signal is active. In addition, in the series of the processes at S 123 , S 122  after the clock signal active edge detecting process at S 112 , the operation can be carried out when the clock signal is inactive. Thus, after the value of the metastable state is outputted, it is possible to carry out the operation for outputting the held input data from the inner array element after a next one time.  
         [0014]      FIG. 2  is a view showing a conventional configuration of a function block to carry out the operation flow of  FIG. 1 . A sequential circuit  101  simulates the usual FF operation, correspondingly to the sequential circuits FF 1  to FF 3 . The sequential circuit  101  includes an input data holder  102 , a metastable state value generator  103  and a switching controller  104 . The input data holder  102  holds the input data Din. The metastable state value generator  103  generates the metastable state value. The switching controller  104  determines an output Dout of the sequential circuit, in accordance with the function simulation operation flow of  FIG. 1 , at a basic cycle unit, on the basis of the held input data and the generated metastable state value. Here, the basic cycle is equal to or less than one cycle of the clock.  
         [0015]     A case of applying the function simulation operation flow of  FIG. 1  to a certain asynchronous circuit will be described below.  
         [0016]      FIG. 3  is a circuit diagram showing an example of the asynchronous circuit to which the function simulation operation flow is applied. This asynchronous circuit includes FF 1 , FF 2  and FF 3  as the sequential circuits, and an adder ALU 1 . An input data D 1  of FF 1  is a value after +1 is added to an output data Q 1  of FF 1  by the adder ALU 1 . An input data D 2  of FF 2  and an input data D 3  of FF 3  are an output data Q 1  of FF 1 . A clock signal CLK 1  is sent to FF 1 . A clock signal CLK 2  is sent to FF 2  and FF 3 . That is, the input signal of FF 1  is the clock signal CLK 1  and the input data D 1 , and its output signal is the output data Q 1 . The input signal of FF 2  is the clock signal CLK 2  and an input data D 2  (=Q 1 ), and its output signal is an output data Q 2 . The input signal of FF 3  is the clock signal CLK 2  and an input data D 3  (=Q 1 ), and its output signal is an output data Q 3 . Also, a metastable state flag MF 1  of FF 1 , a metastable state flag MF 2  of FF 2  and a metastable state flag MF 3  of FF 3  are defined.  
         [0017]      FIG. 4  is a timing chart showing states of each signal in the function simulation operation flow. The lateral axis indicates a time. Here, CLK 1 , D 1 , Q 1 , and MF 1  are mainly related to FF 1 . CLK 2 , D 2 , Q 2 , and MF 2  are mainly related to FF 2 . CLK 2 , D 3 , Q 3 , and MF 3  are mainly related to FF 3 . As shown in  FIG. 4 , the clock signal CLK 1  is assumed to be changed for each 3 number of times, and the clock signal CLK 2  is assumed to be changed for each 4 number of times.  
         [0018]     At first, in the sequential circuit FF 1 , the value, in which +1 is added to the output Q 1  (=0) of Qout of FF 1  by the adder ALU 1 , is supplied as the input data D 1  (=1). Then, the values in the 3 number of times, in short, the value (=1) at the time t 0 , the value (=1) at the time t 1  and the value (=1) at the time t 2  are held in the inner array element (S 111 ). Next, at the time t 3 , a rising edge of CLK 1  is active (S 112 : Yes), and the value (=1) of D 1  is changed from the value of the previous time (namely, the value (=0) of the initial state of FF 1 ) (S 113 : Yes). Here, in the initial state, MF 1  is “false” (=0) (S 114 : No). Thus, the value of the metastable state flag MF 1  of FF 1  at the time t 3  becomes “true” (=1) (S 119 ). Then, the value (for example, =1) at any time (for example, =time t 2 ) in the inner array element of FF 1  is selected as a usual value d (S 116 ). After that, the value meta (=6) of the metastable state is generated (S 117 ), and the value (=6) of the metastable state is outputted from Qout to Q 1  (S 118 ).  
         [0019]     In succession, at the time t 4 , the rising edge of CLK 1  becomes inactive (S 112 , No). Thus, the value of the metastable state flag MF 1  of FF 1  becomes “false” (−0) (S 123 ). After that, the value at any time selected in the inner array element of FF 1 , namely, the usual value d (=1) is outputted as the output Q 1  (S 122 ).  
         [0020]     Similarly, at the times t 9 , t 10 , the times t 15 , t 16  and the times t 21 ,  22 , in one clock cycle, the value of the metastable state flag MF 1  becomes “true” (=1) (S 119 ). Then, at the output Q 1  of Qout, the values (respectively, 4, 4 and 5) of the metastable states are outputted (S 118 ). After that, the value at any one time between the 3 number of times held in the inner array element (=d) is outputted as the usual value (S 122 ).  
         [0021]     Next, the sequential circuit FF 2  receives the input data D 2  having the same value as the output Q 1  of FF 1 . Then, similarly to FF 1 , the values between the 3 number of times of the input data D 2 , in short, the value (=0) at the time t 1 , the value (=0) at the time t 2  and the value (=6) at the time t 3  are held in the inner array element (S 111 ). Next, at the time t 4 , a rising edge of CLK 2  is active (S 112 : Yes), and the value (=6) of D 2  is changed from the value of the previous time (namely, the value (=0) of the initial state of FF 2 ) (S 113 : Yes). Here, in the initial state, MF 2  is “false” (=0) (S 114 : No). Thus, the value of the metastable state flag MF 2  of FF 2  at the time t 4  is “true” (=1) (S 119 ). Then, the value (for example, =0) at any time (for example, =time t 1 ) in the inner array element of FF 2  is selected as the usual value d (S 116 ). After that, the value meta (=3) of the metastable state is generated (S 117 ), and the value (=3) of the metastable state is outputted from Qout to Q 2  (S 118 ).  
         [0022]     In succession, at the time t 5 , the rising edge of CLK 3  becomes inactive (S 112 : No). Thus, the value of the metastable state flag MF 2  of FF 2  becomes “false” (=0) (S 123 ). After that, the value at any time selected in the inner array element of FF 2 , namely, the usual value d (=0) is outputted as the output Q 2  (S 122 ).  
         [0023]     At the times t 12 , t 13  and the times t 20 , t 21 , when the rising edge of CLK 2  is active (S 112 : Yes), there is no change in the value of D 2  (S 113 : No) Thus, in one clock cycle, the value of the metastable state flag MF 2  becomes “false” (=0) (S 120 ), and at the output Q 2  of Qout, the value of the finally held time (t 11 /t 19 ) in the 3 number of times (t 9 , t 10 , t 11 /t 17 , t 18 , t 19 ) held (S 121 ) in the inner array element is outputted as the usual value d (S 122 ).  
         [0024]     Next, the sequential circuit FF 3  receives the input data D 3  having the same value as the output Q 1  of FF 1 . Then, similarly to FF 1 , the values between the 3 number of times of the input data D 3 , in short, the value (=0) at the time t 1 , the value (=0) at the time t 2  and the value (=6) at the time t 3  are held in the inner array element (S 111 ). Next, at the time t 4 , the rising edge of CLK 2  is active (S 112 : Yes), and the value (=6) of D 3  is changed from the value of the previous time (namely, the value (=0) of the initial state of FF 3 ) (S 113 : Yes). Here, in the initial state, MF 3  is “false” (=0) (S 114 : No). Thus, the value of the metastable state flag MF 3  of FF 3  at the time t 4  is “true” (−1) (S 119 ). Then, the value (for example, =6) at any time (for example, =time t 3 ) in the inner array element of FF 3  is selected as the usual value d (S 116 ). After that, the value meta (=7) of the metastable state is generated (S 117 ), and the value (=7) of the metastable state is outputted from Qout to Q 3  (S 118 ).  
         [0025]     In succession, at the time t 5 , the rising edge of CLK 2  becomes inactive (S 112 : No). Thus, the value of the metastable state flag MF 3  of FF 3  becomes “false” (=0) (S 123 ). After that, the value at any time selected in the inner array element of FF 3 , namely, the usual value d (=6) is outputted as the output Q 3  (S 122 ).  
         [0026]     At the times t 12 , t 13  and the times t 20 , t 21 , when the rising edge of CLK 2  is active (S 112 : Yes), there is no change in the value of D 3  (S 113 : No). Thus, in one clock cycle, the value of the metastable state flag MF 3  becomes “false” (=0) (S 120 ), and at the output Q 3  of Qout, the value of the finally held time (t 11 /t 19 ) in the 3 number of times (t 9 , t 10 , t 11 /t 17 , t 18 , t 19 ) held (S 121 ) in the inner array element is outputted as the usual value d (S 122 ).  
         [0027]     Here, the sequential circuits FF 2 , FF 3  at the time t 4  capture the values of the output Q 1  of FF 1 , which are the same data signal, through the rising edge of CLK 2  as the input data D 2 , D 3 . However, the values selected at any time from the inner array element held as the values in the 3 number of times, respectively, are the different values, such as the value (=0) of the time t 1  at FF 2  and the value (=6) of the time t 3  at FF 3 . Thus, this indicates the occurrence of the phenomenon that the values held between the sequential circuits FF 2 , FF 3  are different.  
         [0028]     This fact indicates that at the timing of the time t 4 , when a time difference between a signal transmission delay of the input data D 2  to FF 2  and a signal transmission delay of the input data D 3  to FF 3  is simulated, the same data signal triggered by the same clock signal involves a trouble operation caused by a timing problem between the input sequential circuits.  
         [0029]     Also, the value (=6) of the D 3  selected as the usual value by FF 3  is the value of the metastable state generated in the sequential circuit FF 1 . Thus, this implies that the originally expected input data, namely, the value different from the value (=1) of the output Q 1  at the time t 4  is inputted to FF 3 . Thus, from the time t 5  to the time t 12 , this asynchronous circuit results in the trouble operation. The change of CLK 1  at the time t 3  and the change of CLK 2  at the time t 4  indicate the timings when the trouble operation occurs in this asynchronous circuit.  
         [0030]     As mentioned above, the method of verifying the asynchronous circuit in Japanese Laid Open Patent Application (JP-P 2003-233638A) discloses the operation of the circuit configuration where the output data of the plurality of sequential circuits, in which the cycles of the clock signals are different, mutually serve as the input data of the sequential circuits.  
         [0031]     The foregoing conventional method of verifying the asynchronous circuit determines the output values of the sequential circuits, in accordance with the function simulation operation flow (conventional algorithm), on the basis of the input data to the sequential circuit FF and the value of the metastable state, in one basic cycle unit of the function simulation. That is, a reset signal that can be supplied to the sequential circuit FF is not considered. For this reason, this verifying method does not change the output value for the sequential circuit including the asynchronous reset signal. Thus, it is difficult to properly execute the function simulation of the sequential circuit while considering the asynchronous reset signal. A technique that can properly execute the function simulation of the sequential circuit regardless of the reset signal and the clock signal is desired.  
         [0032]     The conventional method of verifying the asynchronous circuit requires the inner array elements D[0] to D[n] to hold the input data before the n number of times, and they are required for each sequential circuit having the different cycle of the clock signal. For this reason, as the circuit size of the verification target becomes bigger, the memory amount consumed for the inner array elements when the circuit simulation is executed becomes greater. Usually, there is the limit in the memory resource of the computer for executing the function simulation. For this reason, its amount limit leads to the restriction on the circuit size to which the conventional technique can be applied. A technique that can execute the circuit simulation in which the memory use amount is suppressed is desired.  
       SUMMARY OF THE INVENTION  
       [0033]     In order to achieve an aspect of the present invention, the present invention provides a computer program product for verifying an asynchronous circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following: (a) carrying out a function simulation of an asynchronous circuit based on circuit information of the asynchronous circuit including a sequential circuit stored in a storage device; and (b) monitoring an output value from an output node of the sequential circuit every unit time, and setting the output value in n time as a value of a metastable state, when the output vale in the n time is changed from the output value in (n−1) time.  
         [0034]     In the present invention, the output value is monitored, and just after the output vale of the output node of the sequential circuit is changed, the output value is set to the value of the metastable state. This leads to be able to carry out the function simulation in the metastable state regardless of the reset signal and clock signal and so on. As a result, regardless of the configuration difference among the sequential circuits such as the existence or nonexistence of the reset signal, the function simulation can be properly executed. Further, it is unnecessary to have the inner array elements D[0] to D[n] for holding the output value of n number of times. Therefore, the circuit simulation can be carried out suppressing the memory consumption amount. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0035]     The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:  
         [0036]      FIG. 1  is a flowchart showing the method for verifying the asynchronous circuit in the conventional technique;  
         [0037]      FIG. 2  is a view showing a conventional configuration of a function block to carry out the operation flow of  FIG. 1 ;  
         [0038]      FIG. 3  is a circuit diagram showing an example of the asynchronous circuit to which the function simulation operation flow is applied;  
         [0039]      FIG. 4  is a timing chart showing states of each signal in the function simulation operation flow;  
         [0040]      FIG. 5  is a block diagram showing the configuration of the apparatus for verifying the asynchronous circuit in the embodiment according to the present invention;  
         [0041]      FIG. 6  is a function block diagram showing the configuration of the apparatus for verifying the asynchronous circuit in the embodiment according to the present invention;  
         [0042]      FIG. 7  is a flowchart showing the method (the program) for verifying the asynchronous circuit in the embodiment according to the present invention;  
         [0043]      FIG. 8  is a timing chart showing the state of each signal in the method (the program) for verifying the asynchronous circuit in the embodiment according to the present invention;  
         [0044]      FIG. 9  is a description example of an RTL (Register Transfer Level) source where the connection node of the sequential circuit FF 2  and the sequential circuit FF 3  are connected to the same connection node;  
         [0045]      FIG. 10  is a description example of the RTL source changed so that the connection node of the sequential circuit FF 2  and the connection node of the sequential circuit FF 3  are independent of each other; and  
         [0046]      FIG. 11  is a flowchart showing a method that verifies a circuit including an asynchronous circuit in an RTL description by using the program for verifying the asynchronous circuit according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0047]     The invention will be now described herein with reference to illustrative embodiments. Those t skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.  
         [0048]     Embodiments of an apparatus, a method and a program for verifying an asynchronous circuit according to the present invention will be described below with reference to the attached drawings.  
         [0049]     At first, the embodiment of the configuration of the apparatus for verifying the asynchronous circuit according to the present invention will be described.  FIG. 5  is a block diagram showing the configuration of the apparatus for verifying the asynchronous circuit in the embodiment according to the present invention. An apparatus  20  for verifying an asynchronous circuit includes a computer  21 , a storing device  22 , a displaying device  23  and an input device  24 . The computer  21  is an information processor exemplified as a work station and a personal computer. The computer  21  includes a CPU  31  and a memory  32  and transmits and receives the information (data) to and from the storing device  22 , the displaying device  23  and the input device  24 . The storing device  22  includes verification circuit data  41  indicating circuits to be verified (to be simulated), a function simulator A  42  including an existing function simulator, and a function simulator B  43  including a function simulator according to the present invention. The verification circuit data  41 , the function simulator A  42  and the function simulator B  43  are, for example, loaded in the memory  32  and executed by the CPU  31 .  
         [0050]      FIG. 6  is a function block diagram showing the configuration of the apparatus for verifying the asynchronous circuit in the embodiment according to the present invention. The apparatus for verifying the asynchronous circuit includes: sequential circuits  1 - 1 ,  1 - 2  to ( 1 - n ) (n is an integer of 2 or more); switching controllers  4 - 1 ,  4 - 2  to ( 4 -( n− 1)) and metastable state value generators  3 - 1 ,  3 - 2  to ( 3 -( n− 1).  
         [0051]     The sequential circuits  1 - 1 ,  1 - 2  to ( 1 - n ) correspond to the sequential circuits FF 1 , FF 2  to FFn and simulate the usual FF operations. The sequential circuits  1 - 1 ,  1 - 2  to ( 1 - n ) include input data holders  2 - 1 ,  2 - 2  to ( 2 - n ), respectively. The input data holders  2 - 1 ,  2 - 2  to ( 2 - n ) hold the input data Din. An output from the sequential circuit  1 - i  (i is an integer of 1≦i≦( n− 1)) at the former stage and an input to the sequential circuit  1 -( i+ 1) at the latter stage are connected through nets (hereafter, referred to as connection node)  11 - 1 ,  11 - 2  to ( 11 -( n− 1).  
         [0052]     Each of the switching controllers  4 - 1 ,  4 - 2  to ( 4 -( n− 1)) is installed in the course of the connection node  11  between the sequential circuits  1  adjacent to each other. For example, the switching controller  4 - 1  is installed in the course of the connection node  11 - 1  between the sequential circuit  1 - 1  and the sequential circuit  1 - 2 . The value of the input data Din of the connection node  11  is monitored. Then, if the value is changed, the value is replaced by the metastable state value in one basic cycle time. If the value is not changed, the value itself is defined as the input data. The metastable state value generators  3 - 1 ,  3 - 2  to ( 3 -( n− 1)) generate and supply the metastable state values to the switching controllers  4 - 1 ,  4 - 2  to ( 4 -( n− 1)), respectively.  
         [0053]     The sequential circuits  1 - 1 ,  1 - 2  to ( 1 - n ) and the connection nodes  11 - 1 ,  11 - 2  to ( 11 -( n− 1)) correspond to the function simulator A  42 . The function simulator A  42  simulates the circuit operation of the circuit (the verification circuit data  41 ) of a verification target. The switching controllers  4 - 1 ,  4 - 2  to ( 4 -( n− 1)) and the metastable state value generators  3 - 1 ,  3 - 2  to ( 3 -( n− 1)) correspond to the function simulator B  43  of the present invention.  
         [0054]     The method (the program) for verifying the asynchronous circuit in the embodiment according to the present invention will be described below.  FIG. 7  is a flowchart showing the method (the program) for verifying the asynchronous circuit in the embodiment according to the present invention.  FIG. 7  shows the function simulation operation flow of the asynchronous circuit. Here, the sequential circuits  1 - 1 ,  1 - 2 , the switching controller  4 - 1 , the metastable state value generator  3 - 1  and the connection node  11 - 1  in  FIG. 6  are exemplified and explained.  
         [0055]     At first, at  31 , the switching controller  4 - 1  holds the value of the connection node  11 - 1  outputted from the sequential circuit  1 - 1  as “Value”. Next, at S 2 , the switching controller  4 - 1  judges whether or not the value of the connection node  11 - 1  is changed. If the value of the connection node  11 - 1  is changed (S 2 : Yes), the switching controller  4 - 1  carries out a metastable state detecting process at S 3 . If the value of the connection node  11 - 1  is not changed (S 2 : No), the switching controller  4 - 1  carries out the processes at S 7 , S 8 .  
         [0056]     In the metastable state detecting process at S 3 , the switching controller  4 - 1  checks the value of a metastable state flag. If the value of the metastable state flag is “false”=it is not in the metastable state (S 3 ; Yes), then, at S 4 , the switching controller  4 - 1  sets the metastable state flag (sets to “true”). Incidentally, in the initial state, the value of the metastable state flag is “false”. If the value of the metastable state flag is “true”=it is in the metastable state (S 3 : No), the switching controller  4 - 1  carries out the processes at S 7 , S 8 .  
         [0057]     After that, at S 5 , the metastable state generator  3 - 1  generates the value of the metastable state by using a random number, and holds its value as a variable meta. At S 6 , the switching controller  4 - 1  sets the variable meta of the value of the metastable state to the value of the connection node  11 - 1 . Then, the switching controller  4 - 1  outputs to the input of the sequential circuit  1 - 2 .  
         [0058]     If the value of the connection node  11 - 1  is not changed (S 2 : No), or if the value of the metastable state flag is “true”=it is in the metastable state (S 3 : No), then, at S 7 , the switching controller  4 - 1  clears the flag showing the metastable state (sets to “false”). Then, at S 8 , the switching controller  4 - 1  sets the value of the connection node  11 - 1 , which is held as “Value” at S 3 , in its original state to the value of the connection node  11 - 1 . Then, the switching controller  4 - 1  outputs the value to the input of the sequential circuit  1 - 2 .  
         [0059]     Next, the operation of the method (the program) for verifying the asynchronous circuit in the embodiment according to the present invention will be described below with reference to the asynchronous circuit in  FIG. 3  as an example.  FIG. 8  is a timing chart showing the state of each signal in the method (the program) for verifying the asynchronous circuit in the embodiment according to the present invention. Its lateral axis indicates the time.  
         [0060]     At first, the operation regarding the sequential circuit FF 2  will be described below. CLK 2 , D 2 , MF 2 , Value 2, and Q 2  are mainly related to the sequential circuit FF 2 .  
         [0061]     At times t 0 , t 1 , t 2  and t 3 , the value of the connection node D 2  is updated and held to Value 2 (0→0→0→1) (S 1 ). Then, at the time t 3 , if the value of the connection node D 2  is changed from 0 to 1 (S 2 : Yes), the value of the metastable state flag MF 2  of the sequential circuit FF 2  is checked (S 3 ). If the metastable state flag MF 2  is “false” (S 3 : Yes), the metastable state flag MF 2  is set to “true” (S 4 ). Then, the value=M 1  of the metastable state is generated (S 5 ). After that, the value=M 1  of the metastable state is set for the connection node D 2  (S 6 ). Then, M 1  is inputted to Din of the sequential circuit FF 2 . Next, at a time t 4 , since the value of the connection node D 2  is not changed (S 2 : No), the metastable state flag MF 2  is set to “false” (S 7 ). The value (=1) held as Value 2 is set for the connection node D 2  ( 38 ). At that time, since CLK 2  is changed to a rising change (active edge), the sequential circuit FF 2  latches the value (=M 1 ) of the connection node D 2  (Q 2 =M 1 ).  
         [0062]     Next, the operation regarding the sequential circuit FF 3  will be described below. CLK 2 , D 3 , MF 3 , Value 3, and Q 3  are mainly related to the sequential circuit FF 3 .  
         [0063]     At the times t 0 , t 1 , t 2  and t 3 , the value of the connection node D 3  is updated and held to Value 3 (0→0→0→1) (S 1 ). Then, at the time t 3 , if the value of the connection node D 3  is changed from 0 to 1 (S 2 : Yes), the value of the metastable state flag MF 3  of the sequential circuit FF 3  is checked (S 3 ). If the metastable state flag MF 3  is “false” (S 3 : Yes), the metastable state flag MF 3  is set to “true” (S 4 ). Then, the value=M 5  of the metastable state is generated (S 5 ). After that, the value=M 5  of the metastable state is set for the connection node D 3  (S 6 ). Then, M 5  is inputted to Din of the sequential circuit FF 3 . Next, at the time t 4 , since the value of the connection node D 3  is not changed (S 2 : No), the metastable state flag MF 3  is set to “false” (S 7 ). The value (=1) held as Value 3 is set for the connection node D 3  (S 8 ). At that time, since CLK 2  is changed to the rising change (active edge), the sequential circuit FF 3  latches the value (=M 5 ) of the connection node D 3  (Q 3 =M 5 ).  
         [0064]     In this way, in the connection nodes D 2  and D 3  to which the values of the output Q 1  of the sequential circuit FF 1  are set, the different values (M 1  and M 5 ) of the metastable states are latched, respectively. Thus, it is possible to equivalently represent the difference of signal delays caused by the difference between the interconnection lengths.  
         [0065]     According to the present invention, it is possible to correctly execute the function simulation of the plurality of sequential circuits including the asynchronous reset signal and clock signal. That is, irrespectively of the circuit configuration of the asynchronous circuit, the function simulation can be carried out, and the asynchronous circuit can be correctly verified.  
         [0066]     Also, according to the present invention, for each connection net, it is changed so as to use the value of its net and the value of the metastable state. Thus, it does not require the inner array elements D[0] to D[n] to hold the input data n number of times before, which was required in the conventional technique. Hence, it is possible to suppress the increase in the memory consumption amount that implies the computer resource.  
         [0067]     In the circuit diagram of the asynchronous circuit shown in  FIG. 3 , there is a case that the connection node of the sequential circuit FF 2  and the connection node of the sequential circuit FF 3  become equal. In that case, before applying the operation flow of the method (the program) for verifying the asynchronous circuit according to the present invention in  FIG. 7 , it is preferred to add the process for separating the connection node of the sequential circuit FF 2  and the connection node of the sequential circuit FF 3 .  
         [0068]      FIG. 9  is a description example of an RTL (Register Transfer Level) source where the connection node of the sequential circuit FF 2  and the sequential circuit FF 3  are connected to the same connection node.  FIG. 10  is a description example of the RTL source changed so that the connection node of the sequential circuit FF 2  and the connection node of the sequential circuit FF 3  are independent of each other.  
         [0069]      FIG. 9  is described such that, when the active edge of a clock signal ck 12  is detected, an output signal Q 1  of the sequential circuit FF 1  is outputted to an output Q 2  of the sequential circuit FF 2  and an output Q 3  of the sequential circuit FF 3 . On the other hand,  FIG. 10  is changed such that, after the output signal Q 1  of the sequential circuit FF 1  is outputted to independent inner variables Q 1 _t 1  and Q 1 _t 2 , they are outputted to the output Q 2  of the sequential circuit FF 2  and the output Q 3  of the sequential circuit FF 3 , respectively.  
         [0070]     In the method of verifying the asynchronous circuit according to the present invention in  FIG. 7 , even if the plurality of sequential circuits are connected to the same net (connection node), the processes are carried out within the same processing flow. For this reason, when the plurality of sequential circuits are connected to the same net, it is impossible to consider the difference of the signal delays caused by the difference between the interconnection lengths, among the plurality of sequential circuits. As the method for avoiding this, it is possible to carry out the present invention for each connection net connected to each of the sequential circuits, by separating the connection net (connection node) as shown in  FIG. 10 . In this case, the correlative state between the metastable state value generated from the random number and the value of the connection node before the change is equivalent to the consideration of the difference of signal delays between the sequential circuits. Thus, the expected function simulation result is obtained.  
         [0071]      FIG. 5  shows the system configuration view when the method of verifying the asynchronous circuit according to the present invention is assembled into the computer system as the program. Here, an example of a case when this verifying program is used to verify the circuit including the asynchronous circuit described in the RTL will be described.  FIG. 11  is a flowchart showing the method which uses the program for verifying the asynchronous circuit according to the present invention and verifies the circuit including the asynchronous circuit in the RTL description.  
         [0072]     At first, the RTL (Resister Transfer Level) description is used to design the circuit (S 11 ). Next, whether or not the plurality of sequential circuits exists in the same net within the designed circuit is judged (S 12 ). If the plurality of sequential circuits exist in the same net (S 112 : Yes), as shown in  FIG. 10 , the process for separating the connection node is carried out such that the connection nodes of the respective sequential circuits are independent of each other (S 13 ). If the plurality of sequential circuits do not exist in the same net (S 12 : No), the process at S 13  is not carried out, and the operation flow proceeds to the process at S 14 . In succession, each separated connection node is checked whether or not the connection node is the asynchronous connection node. Here, the asynchronous connection node is the connection node, through which the output (data) of the sequential circuit that the cycle of the clock signal is different is connected to the next sequential circuit via the combination circuit and the like. Then, the asynchronous connection node is extracted (S 14 ). For example, an EDA (Electronic Design Automation) tool available commercially can be used for the extraction in the process at this S 14 . Next, for the connection node extracted at S 14 , the function simulator B  43  monitors the value determined by the function simulator A  42  as mentioned above. Then, in the case that the value of the connection net is changed, the function simulator B  43  replaces the value of the connection net by the value of the metastable state in one basic cycle time. In the other cases, the function simulator B  43  uses the value itself of the connection net as the input data signal (S 15 ). The detail of S 15  is as explained in  FIGS. 7 and 8 . After that, until all of the circuit verifications are completed by using the above-explained method, the operation flow returns to S 11 , and the processes are repeatedly executed (S 16 ).  
         [0073]     By using the program for verifying the asynchronous circuit according to the present invention as mentioned above, it is possible to correctively verify the asynchronous circuit as mentioned above, irrespectively of the circuit configuration, and also suppress the increase in the memory consumption amount.  
         [0074]     According to the present invention, it is possible to suitably execute the simulation by suppressing the memory use amount without any consideration of the difference between the sequential circuit configurations.  
         [0075]     It is apparent that the present invention is not limited to the above embodiment, which may be modified and changed without departing from the scope and spirit of the invention.