Abstract:
A high frequency mixer circuit is used as a down converter in which an RF signal and an LO signal are mixed to generate an IF signal, or as an up converter in which an IF signal and an LO signal are mixed to generate an RF signal. The high frequency mixer circuit has a wiring layout wherein wiring lines for propagating LO signals intersect only one of the wiring lines for propagating RF signals or IF signals.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     The entire disclosure of Japanese Patent Application No. 2005-34394 including the specification, claims, drawings, and abstract is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a high frequency mixer circuit in which isolation between signals is improved.  
         [0004]     2. Description of the Related Art  
         [0005]     In wireless communication, a frequency conversion circuit (high frequency mixer circuit) is commonly used to down-convert a received radio frequency signal (RF signal) to an intermediate frequency signal (IF signal) having a lower frequency, or to up-convert an IF signal to an RF signal having a higher frequency.  
         [0006]     As an example of a high frequency mixer circuit, a quad ring circuit  100  as shown in  FIG. 2  is known in the art. The quad ring circuit  100  has transistors Tr 1  and Tr 2 , and transistors Tr 3  and Tr 4 . Sources of the transistors Tr 1  and Tr 2  are directly connected to each other, and are connected to a first terminal T RF1  for RF signals. Sources of the transistors Tr 3  and Tr 4  are directly connected to each other, and are connected to a second terminal T RF2  for RF signals. Gates of the transistor Tr 1  and the transistor Tr 4  are connected to a first terminal T LO1  for local oscillation signals (LO signals). Gates of the transistor Tr 2  and the transistor Tr 3  are connected to a second terminal T LO2  for LO signals. Drains of the transistor Tr 1  and the transistor Tr 3  are connected to a first terminal T IF1  for IF signals. Drains of the transistor Tr 2  and the transistor Tr 4  are connected to a second terminal T IF2  for IF signals.  
         [0007]     By inputting an RF signal having a frequency f RF  to a point between the first and second terminals T RF1  and T RF2  for RF signals, and inputting an LO signal having a frequency f LO  to a point between the first and second terminals T LO1  and T LO2  for LO signals, an IF signal obtainedby down conversion to a frequency (f RF -f LO ) is output from a point between the first and second terminals T IF1,  and T IF2  for IF signals. Also, by inputting an IF signal having a frequency f IF  to a point between the first and second terminals T IF1  and T IF2  for IF signals, and inputting a local oscillation signal having a frequency f LO  to a point between the first and second terminals T LO1  and T LO2  for LO signals, an RF signal obtained by up conversion to a frequency (f IF +f LO ) is output from a point between the first and second terminals T RF1  and T RF2  for RF signals.  
         [0008]      FIG. 3  shows a circuit diagram of the quad ring circuit  100 . Referring to  Fig. 3 , wiring used in a case where the transistor Tr 1  is formed in an upper right region, the transistor Tr 2  is formed in an upper left region, the transistor Tr 3  is formed in a lower right region, and the transistor Tr 4  is formed in a lower left region will be described below.  
         [0009]     By introducing a dopant into a surface of a semiconductor substrate, source regions S and a drain region D (shown by broken lines in  FIG. 3 ) are formed in each of the regions where the transistors Tr 1  through Tr 4  are to be formed. In each of the transistors Tr 1  through Tr 4 , gate electrodes G are disposed in regions between the source regions S and the drain region D. The transistors Tr 1  through Tr 4  are each formed in this manner.  
         [0010]     In the source regions, drain regions, and gate electrodes of the transistors Tr 1  through Tr 4 , wiring is formed using a multi-layered metal wiring technique. Connection terminals are extended from the gate electrodes G of the transistor Tr 1  in a direction toward the transistor Tr 2 , connection terminals are extended from the gate electrodes G of the transistor Tr 4  in a direction toward the transistor Tr 3 , and a wiring line L 1  is laid out from the respective connection terminals through between the transistors Tr 2  and Tr 4  to the first terminal T LO1  for LO signals that is located on the left side of the transistor Tr 4 . Connection terminals are extended from the gate electrodes G of the transistor Tr 2  in a direction toward the transistor Tr 1 , connection terminals are extended from the gate electrodes G of the transistor Tr 3  in a direction toward the transistor Tr 4 , and a wiring line L 2  is laid out from the respective connection terminals through between the transistors Trl and Tr 2  to the second terminal T LO2  for LO signals that is located on the left side of the transistor Tr 2 . The wiring lines L 1  and L 2  are formed in a multi-layered manner with an insulating layer interposed therebetween.  
         [0011]     A wiring line L 3  is extended from the source regions S of the transistor Tr 1  in a direction away from the transistor Tr 3 , and is extended from the source regions S of the transistor Tr 2  in a direction away from the transistor Tr 4 . The source regions S of the transistor Tr 1  and the source regions S of the transistor Tr 2  are electrically connected to each other, and the wiring line L 3  is laid out from the respective source regions S to the first terminal T RF1  for RF signals that is located on the right side of the transistor Tr 1 . A wiring line L 4  is extended from the source regions S of the transistor Tr 3  in a direction away from the transistor Tr 1 , and is extended from the source regions S of the transistor Tr 4  in a direction away from the transistor Tr 2 . The source regions S of the transistor Tr 3  and the source regions S of the transistor Tr 4  are electrically connected to each other, and the wiring line L 4  is laidout from the respective source regions S to the second terminal T RF2  for RF signals that is located on the right side of the transistor Tr 3 . The wiring lines L 3  and L 4  are formed in a multi-layered manner on the wiring line L 2  and a wiring line L 5 , respectively, with an insulating film interposed therebetween.  
         [0012]     The wiring line L 5  is extended from the drain region D of the transistor Tr 1  in a direction away from the transistor Tr 2 , and is extended from the drain region D of the transistor Tr 3  in a direction away from the transistor Tr 4 . The drain region D of the transistor Tr 1  and the drain region D of the transistor Tr 3  are electrically connected to each other, and the wiring line L 5  is laid out from the respective drain regions D to the first terminal T IF1  for IF signals that is located below the transistor Tr 3 . A wiring line L 6  is extended from the drain region D of the transistor Tr 2  in a direction away from the transistor Trl, and is extended from the drain region D of the transistor Tr 4  in a direction away from the transistor Tr 3 . The drain region D of the transistor Tr 2  and the drain region D of the transistor Tr 4  are electrically connected to each other, and the wiring line L 6  is laid out from the respective drain regions D to the second terminal TIF 2  for IF signals that is located below the transistor Tr 4 . The wiring lines L 5  and L 6  are formed in a multi-layered manner on the wiring lines L 4  and L 1 , respectively, with an insulating film interposed therebetween.  
         [0013]     However, the layout of the wiring lines L 1  through L 6  as shown in  FIG. 3  includes a region “a” in which the wiring line L 2  for LO signals and the wiring line L 3  for RF signals overlap each other with an insulating film interposed therebetween, and a region “b” in which the wiring line L 1  for LO signals and the wiring line L 6  for IF signals overlap each other with an insulating film interposed therebetween. The conditions in the regions “a” and “b” are equivalent to the conditions in which a wiring line for RF signals or a wiring line for IF signals is connected to a wiring line for LO signals through a capacitor in a high frequency band.  
         [0014]     With this being the situation, in the regions “a” and “b”, an LO signal having a high signal strength is mixed with an RF signal or an IF signal having a relatively low signal strength. Therefore, such high frequency mixer circuits have a problem in that the isolation between different signals is reduced.  
       SUMMARY OF THE INVENTION  
       [0015]     According to one aspect of the present invention, there is provided a high frequency mixer circuit intended for use as a down converter in which a radio frequency signal and a local oscillation signal are mixed to generate an intermediate frequency signal, or as an up converter in which an intermediate frequency signal and a local oscillation signal are mixed to generate a radio frequency signal, the high frequency mixer circuit having a wiring layout wherein first and second wiring lines for propagating local oscillation signals intersect only one of the wiring lines for propagating radio frequency signals or intermediate frequency signals. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     A preferred embodiment of the present invention will be described in further detail based on the following drawings, wherein:  
         [0017]      FIG. 1  shows an example of a wiring layout of a high frequency mixer circuit according to an embodiment of the present invention;  
         [0018]      FIG. 2  shows a structure of a quad ring circuit; and  
         [0019]      FIG. 3  shows a wiring layout of a related art quad ring circuit. 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENT  
       [0020]     A high frequency mixer circuit according to an embodiment of the present invention is expressed as, for example, an equivalent circuit identical to the quad ring circuit  100  shown in  FIG. 2 . In other words, the present embodiment will be described taking as an example a case wherein the high frequency mixer circuit is a quad ring circuit having transistors Tr 1  and Tr 2 , and transistors Tr 3  and Tr 4 . However, the present invention is not limited to such an embodiment, and the technical idea of the present invention can also be applied to other types of structures of high frequency mixer circuits.  
         [0021]      FIG. 1  shows a circuit diagram of a high frequency mixer circuit (quad ring circuit)  200  according to thepresent embodiment. Referring to  FIG. 1 , wiring used in a case where the transistor Tr 1  is formed in an upper right region, the transistor Tr 2  is formed in an upper left region, the transistor Tr 3  is formed in a lower right region, and the transistor Tr 4  is formed in a lower left region will be described below. In  FIG. 1 , respective regions are shown hatched in order to clearly define their shape.  
         [0022]     By introducing a dopant into a surface of a semiconductor substrate, source regions S and a drain region D (shown by broken lines in  FIG. 1 ) are formed in each of the regions where the transistors Tr 1  through Tr 4  are to be formed. According to the present embodiment, the source regions S are disposed above and below the drain region D to be spaced apart from the drain region D by a predetermined distance with the drain region D being located at the center. In each of the transistors Tr 1  through Tr 4 , gate electrodes G are disposed in regions between the source regions S and the drain region D. According to the present embodiment, two gate electrodes G are provided for each of the transistors Tr 1  through Tr 4 .  
         [0023]     In the source regions, drain regions, and gate electrodes of the transistors Tr 1  through Tr 4 , wiring is formed using a multi-layered metal wiring technique. Connection terminals are extended from the gate electrodes G of the transistor Tr 1  in a direction toward the transistor Tr 2 , and connection terminals are extended from the gate electrodes G of the transistor Tr 4  in a direction toward the transistor Tr 3 . A wiring line L x   1  is extended from both the gate electrodes G of the transistors Tr 1  and Tr 4  to be passed through between the transistors Tr 2  and Tr 4 , and is connected to a first terminal T LO1  for LO signals that is located on the left side of the transistor Tr 4 .  
         [0024]     Connection terminals are extended from the gate electrodes G of the transistor Tr 2  in a direction toward the transistor Tr 1 , and connection terminals are extended from the gate electrodes G of the transistor Tr 3  in a direction toward the transistor Tr 4 . A wiring line L x   2  is extended from both the gate electrodes G of the transistors Tr 2  and Tr 3  to be passed through between the transistors Tr 2  and Tr 4 , and is connected to a second terminal T LO2  for LO signals that is located on the left side of the transistor Tr 2 .  
         [0025]     The wiring lines L x   1  and Lx 2  are formed in a multi-layered manner with an insulating layer interposed between the wiring layers of these wiring lines. Further, it is preferable that the wiring lengths of the wiring lines as measured from the first and second terminals T LO1  and T LO2  for LO signals to the gate electrodes G of the transistors Tr 1  through Tr 4  are set to be approximately equal to each other. Thus, the symmetry of LO signals can be maintained.  
         [0026]     A wiring line L 3  is extended from the source regions S of the transistor Tr 1  in a direction away from the transistor Tr 3 , and is extended from the source regions S of the transistor Tr 2  in a direction away from the transistor Tr 4 . The wiring line L 3  is formed in a multi-layered manner as a wiring layer different from the wiring layers of the gate electrodes, wiring line L x   1 , andwiring line L x   2  with an insulating film interposed therebetween. When each of the transistors Tr 1  and Tr 2  is provided with a plurality of source regions S, the source regions S are connected to each other.  
         [0027]     The source regions S of the transistor Tr 1  and the source regions S of the transistor Tr 2  are electrically connected through the wiring line L 3 . The wiring line L 3  is passed outside a region in which the transistors Tr 1  and Tr 2  are laid out, and is connected from the respective source regions S to a first terminal T RF1  for RF signals that is located on the right side of the transistor Tr 1 .  
         [0028]     A wiring line L 4  is extended from the source regions S of the transistor Tr 3  in a direction away from the transistor Tr 1 , and is extended from the source regions S of the transistor Tr 4  in a direction away from the transistor Tr 2 . The wiring line L 4  is formed in a multi-layered manner as a wiring layer different from the wiring layers of the gate electrodes, wiring line L x   1 , and wiring line L x   2  with an insulating film interposed therebetween. When each of the transistors Tr 3  and Tr 4  is provided with a plurality of source regions S, the source regions S are connected to each other.  
         [0029]     The source regions S of the transistor Tr 3  and the source regions S of the transistor Tr 4  are electrically connected through the wiring line L 4 . The wiring line L 4  is passed outside a region in which the transistors Tr 3  and Tr 4  are laid out, and is connected from the respective source regions S to a second terminal T RF2  for RF signals that is located on the right side of the transistor Tr 3 .  
         [0030]     A wiring line L 5  is extended from the drain region D of the transistor Tr 1  in a direction away from the transistor Tr 2 , and is extended from the drain region D of the transistor Tr 3  in a direction away from the transistor Tr 4 . The wiring line L 5  is formed in a multi-layered manner as a wiring layer different from thewiring layers of the gate electrodes andwiring lines L x   1  through L 4  with an insulating film interposed therebetween.  
         [0031]     The drain region D of the transistor Tr 1  and the drain region D of the transistor Tr 3  are electrically connected through the wiring line L 5 . The wiring line L 5  is passed outside a region in which the transistors Tr 1  and Tr 3  are laid out, and is connected from the respective drain regions D to a first terminal T IF1  for IF signals that is located below the transistor Tr 3 .  
         [0032]     A wiring line L 6  is extended from the drain region D of the transistor Tr 2  in a direction away from the transistor Tr 1 , and is extended from the drain region D of the transistor Tr 4  in a direction away from the transistor Tr 3 . The wiring line L 6  is formed in a multi-layered manner as a wiring layer different from thewiring layers of thegate electrodes andwiring lines L x   1  through L 4  with an insulating film interposed therebetween.  
         [0033]     The drain region D of the transistor Tr 2  and the drain region D of the transistor Tr 4  are electrically connected through the wiring line L 6 . The wiring line L 6  is passed outside a region in which the transistors Tr 2  and Tr 4  are laid out, and is connected from the respective drain regions D to a second terminal T IF2  for IF signals that is located below the transistor Tr 4 .  
         [0034]     With this structure, it is preferable that the wiring lengths of the wiring lines as measured from the first and second terminals T RF1  and T RF2  for RF signals to the source regions S of the transistors Tr 1  through Tr 4  are set to be approximately equal to each other. Further, it is also preferable that the wiring lengths of the wiring lines as measured from the first and second terminals T IF1  and T IF2  for IF signals to the drain regions D of the transistors Tr 1  through Tr 4  are set to be approximately equal to each other. Thus, the symmetry of RF signals and IF signals can be maintained.  
         [0035]     It is to be noted that the order of multi-layering in which the wiring lines L x   1  through L 6  are layered is not limited to any particular order, and it is not necessary to stack the layers in the order described above. Further, it is preferable that the insulating films provided between the wiring layers of the gate electrodes andwiring lines L x   1  through L 6  each have a film thickness that falls within a range in which a sufficient dielectric strength is achieved between each pair of the layers.  
         [0036]     In the high frequency mixer circuit  200  according to the above-described embodiment, the wiring line L x   2  for LO signals and the wiring line L 6  for IF signals overlap each other in a region “c” with an insulating film interposed therebetween, and the wiring line L x   1  for LO signals and the wiring line L 6  for IF signals overlap each other in a region “d” with an insulating film interposed therebetween. Thus, in the regions “c” and “d” where LO signals and IF signals overlap, the wiring line L 6  is coupled to the wiring lines L x   1  and L x   2  through an insulating film that functions as a capacitor.  
         [0037]     However, because LO signals propagating along the wiring lines L x   1  and L x   2 , respectively, have opposite phases to each other, the influence on IF signals in the region “c” and the influence on IF signals in the region “d” compensate each other, and therefore the influence of LO signals on IF signals can be reduced to an extremely low level.  
         [0038]     With this structure, it is preferable that, by providing the region “c” and the region “d” close to each other, the wiring length of the wiring line as measured from the terminal T LO2  for LO signals to the region “c” and the wiring length of the wiring line as measured from the terminal T LO1  for LO signals to the region “d” are set to be approximately equal to each other. It is further preferable that the distance between the region “c” and the region “d” is set to be less than a wavelength of LO signals, and it is more preferable that the distance between the region “c” and the region “d” is set to be less than one tenth of the wavelength of LO signals. As a result, phase shifts of LO signals occurring between the wiring line L x   1  and the wiring line L x   2  due to the arrangement of the region “c” and the region “d” are reduced, and it is therefore possible to cause LO signals to have approximately opposite phases to each other in the region “c” and the region “d”.  
         [0039]     It is to be noted that, although a wiring line for LO signals and a wiring line for IF signals are laid out to overlap each other in the above-described embodiment, the present invention is not limited to such an embodiment. Alternatively, a wiring line for LO signals and a wiring line for RF signals may also be laid out to overlap each other. However, because IF signals generally have a stronger signal strength than RF signals, it is more preferable that a wiring line for LO signals and a wiring line for IF signals are laid out to overlap each other.  
         [0040]     Further, although the above-described embodiment is described with reference to a circuit structure that uses MESFETs, the present invention is not limited to such an embodiment. The circuit of the present invention may, for example, also be formed using MOSFET type transistors.  
         [0041]     As described above, according to one aspect of the present invention, it is preferable that a high frequency mixer circuit comprises a quad ring circuit with four transistors, the transistors being respectively laid out in corners of a rectangular region on a substrate, wherein two gates of the transistors are connected to each other through a first wiring line, other two remaining gates of the transistors are connected to each other through a second wiring line, and the first wiring line and the second wiring line are both laid out to pass through between two of the transistors.  
         [0042]     Further, by laying out wiring lines such that a wiring line for LO signals intersects only one of wiring lines for RF signals or IF signals, mixing of LO signals with RF signals or IF signals is reduced, and therefore the isolation between signals can be improved. Although it is also possible to obtain the above-described effects in a high frequency circuit other than a high frequency mixer circuit, the effects are remarkable particularly in a high frequency mixer circuit because, in most cases, the signal strength of LO signals is stronger than the signal strengths of RF signals and IF signals in a high frequency mixer circuit. Further, in a quad ring circuit, because a wiring line for LO signals always intersects a wiring line for RF signals or IF signals, the wiring layout of the present invention can be applied without exception.  
         [0043]     Further, it is preferable that a pair of wiring lines for propagating radio frequency signals have approximately equal wiring lengths. Still further, it is preferable that a pair of wiring lines for propagating intermediate frequency signals have approximately equal wiring lengths.