Abstract:
A semiconductor memory device includes a random-access memory which has at least one redundancy column for replacing a defective column; a serial output circuit receives data read out in parallel from the random-access memory and serially outputs the received data redundancy circuit replaces data of the defective column with data from the redundancy column.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device having a redundancy circuit. 
     2. Description of the Related Art 
     Some types of semiconductor memory devices consist of a combination of a random-access memory (RAM) and a shift register group. This type of semiconductor memory device is, in general, used as an image memory. The shift register group is attached to the RAM for high-speed read-out of the data stored therein. The RAM is, for example, provided between a central processing unit (CPU) and a cathode-ray tube display (CRT). The data stored in the RAM is read out in parallel and input to the shift registers in accordance with control of a system. The read-out data is output serially from the shift registers to the CRT. 
     This type of semiconductor memory device thus enables both low-speed random access by the CPU and high-speed serial data transmission between the RAM and the CRT. In this regard, however, there has been no disclosure of a circuit giving a redundancy function to the RAM. In other words, while there is a well-known RAM having a redundancy circuit, there is no RAM having both a high-speed serial data output function and a redundancy function. Yet, a redundancy circuit is essential to raise the yield in production of a RAM. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a semiconductor memory device having a serial output circuit for performing a high-speed data read-out and having a redundancy circuit for raising the yield. 
     In accordance with the present invention, there is provided a semiconductor memory device including a RAM having at least one redundancy column for replacing a defective column and a serial output means for receiving in parallel data read out of the RAM and serially outputting the received data. A redundancy circuit is provided for replacing data of the defective column serially output from the serial output means with data from the redundancy column. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention; 
     FIG. 2 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention; 
     FIG. 3 is a block diagram of a semiconductor memory device according to a third embodiment of the present invention; and 
     FIG. 4 is a block diagram of a semiconductor memory device according to a fourth embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A semiconductor memory device according to the present invention will be explained in detail with reference to the accompanying drawings. 
     FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 represents a column decoder, 2 a row decoder, 3 an image memory (RAM), 4 a multiplexer, 5 a counter, 6 a redundancy read-only memory (redundancy ROM), and 7 a comparator. Reference letters SA 1  to SA n  represent sense amplifiers, RSA a redundancy sense amplifier, DC 1  a drive circuit, SR 1  to SR n  shift registers, and RA a redundancy amplifier. In the RAM 3, MC is a memory cell connected between word lines WL and bit lines BL and BL. The bit lines BL are connected to the corresponding shift registers SR 3  through a transfer gate TG, and the word lines WL are connected to the row decoder 2. The slanted line portion in the RAM 3 indicates the redundancy column. 
     The redundancy circuit according to the embodiment of the present invention is formed by the drive circuit DC 1 , the redundancy sense amplifier RSA, the redundancy amplifier RA, the multiplexer 4, the counter 5, the redundancy ROM 6, and the comparator 7. 
     In the inspection of the manufacture of the RAM, when a defective column is found, the column address indicating the defective column is stored in the redundancy ROM and the redundancy ROM is enabled. That is, the redundancy ROM 6 is enabled to provide the column address (or addresses) corresponding to the defective column (or columns) of the RAM 3. Storage of the defective column address in the redundancy ROM 6 is performed by cutting a polycrystalline silicon fuse. This technique is a well-known. There are two known methods for cutting a polycrystalline silicon fuse, i.e., one method utilizing a laser beam and another method utilizing electrical current. 
     The semiconductor memory device according to the present invention basically operates such that when a defective column in the RAM is accessed by an address ADD sent from the CPU, the defective column is immediately changed to the redundancy column in the memory area indicated by the slanted line. That is, this memory area is reserved for a redundancy function. Accordingly, even if a defective column is found in the RAM, the device can operate as a normal memory. 
     The operation of this device will be explained in detail hereinafter. 
     If a defect is found in the column corresponding to, for example, the sense amplifier SA 2 , the corresponding column address is stored in the redundancy ROM 6. 
     In the random access mode, during a read-out operation when the input address ADD from the CPU is applied to the column decoder 1 and the comparator 7, if a defective column address is not included in the input address, data corresponding to the input address is output from the RAM to the data bus DB through the corresponding sense amplifiers and output from the amplifier AMP 0 . During a writing operation, write data corresponding to the input address is input to the RAM from the data bus DB. 
     Assume a defective column address corresponding to the sense amplifier SA 2  is included in the input address. The comparator 7 compares the input column addresses with the stored defective column address in the redundancy ROM 6. When one of the input column addresses coincides with the stored defective column address, a coincidence signal COM is input to the drive circuit DC 1  and an inverted coincidence signal COM is input to the column decoder 1. When the coincidence signal COM is input to the drive circuit DC 1 , the drive circuit DC 1  activates the redundancy sense amplifier RSA and the redundancy column is employed. Accordingly, data from the data bus DB is read out from or written into the RAM using the redundancy column instead of the defective column. 
     During a serial output mode, data stored in the RAM is simultaneously read out in parallel to the shift registers SR 1  to SR n  through the transfer gates TG. Accordingly, data corresponding to the defective column is also read out to one of the shift registers, for example, to the shift register SR 2 . Each shift register sequentially transfers the input data to the next shift register every clock signal S CLK . Finally, the input data is shifted to the final shift register SR n  and input to the multiplexer 4. Data corresponding to the redundancy column, i.e., the correct data, is latched in the redundancy amplifier RA. When the data corresponding to the defective column, i.e., the defective data, is shifted to the multiplexer 4 (that is, the data of the shift register SR 2  is transferred to the multiplexer 4 through the shift register SR n ), the multiplexer 4 replaces the defective data with the correct data latched in the redundancy amplifier RA for output to the CRT. Accordingly, correct serial outputs S OUT  can be obtained at a high speed. 
     The data replacement operation in the multiplexer 4 will be explained in more detail below. 
     As mentioned above, the defective column address is previously stored in the redundancy ROM 6. That is, the number of the defective column with respect to the final column (final shift register SR n ) is stored in the redundancy ROM 6. The number of columns between the final column and the defective column is read out from the redundancy ROM 6 and input to the counter 5. Accordingly, the counter 5 is initially set to that number of columns after it is preset by the transfer gate signal STG. 
     The clock signal S CLK  is input to the counter 5 and input in parallel to the shift registers SR 1  to SR n . The counter 5 subtracts one from the number of columns initially set every clock signal S CLK . At the same time, the data of the shift register is shifted to the next shift register every clock signal S CLK . When the count becomes &#34;0&#34;, the counter 5 outputs a coincidence signal SCOM to the multiplexer 4. At this time, since the defective data shifted by the shift registers arrives at the multiplexer 4, the multiplexer 4 can replace the defective data with the correct data based on the coincidence signal SCOM. Accordingly, serial output of the correct data can be obtained from the multiplexer 4 and transmitted to the CRT. 
     When the transfer gate control signal STG is ON, all transfer gates TG are simultaneously turned ON so as to transfer the data from the RAM in parallel into the shift registers SR 1  to SR n . 
     FIG. 2 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention. In FIG. 2, the same reference numerals and letters as in FIG. 1 indicate the same elements. In this embodiment, a decoder 8, flip-flop circuits FF 1  to FF n , gates G 1  to G n , and data bus RDB are provided instead of the multiplexer 4 and the counter 5 shown in FIG. 1. 
     As mentioned above, the defective column address is previously stored in the redundancy ROM 6. 
     In this embodiment, in the random access mode, the same read/write operations of the redundancy column as in FIG. 1 are performed. Accordingly, explanations of these operations will be omitted. 
     In the serial output mode, when data corresponding to the defective column is read out from the RAM to one of the shift registers, for example, to the shift register SR 2 , the defective data is replaced by the correct data sent from the redundancy amplifier RA through the redundancy data bus RDB and the gate G 2  during the first shift operation. That is, the information regarding the defective column address stored in the redundancy ROM 6 is applied to the decoder 8. The decoder sets the corresponding flip-flop circuit. In this case, the flip-flop circuit FF 2  is set by the decoder 8. Since all flip-flop circuits FF 1  to FF n   have been reset in the initial state, only the flip-flop circuit FF 2  is set, and the corresponding gate G 2  is turned ON by the output of the flip-flop circuit FF 2 . Other gates G 1  and G 3  to G n  are turned OFF. 
     Accordingly, as explained above, the correct data latched in the redundancy amplifier RA is sent to the output of the shift register SR 2  through the data bus RDB and the defective data is replaced with the correct data. Consequently, the correct serial outputs can be obtained from the final shift register SR n  and transmitted to the CRT. 
     FIG. 3 is a block diagram of a semiconductor memory device according to another embodiment of the present invention. In this case, an additional redundancy column (slanted portion) is added to the memory area in the RAM 3. As can be understood, the yield of the RAM can be raised by the additional redundancy column over the single redundancy column shown in FIGS. 1 and 2. In FIG. 3, reference letter m represents an m-bit address along with the additional column, the redundancy sense amplifier RSA 2 , the drive circuit DC 2 , the comparator COMP4, and the redundancy ROM 2 are newly added to the redundancy circuit. 
     In the same way as explained above, a second defective column address is previously stored in the redundancy ROM 2. Of course, the first defective column address is previously stored in the redundancy ROM 1. 
     In this embodiment, in the random access mode, the same read/write operations of the redundancy columns shown in FIG. 1 are performed. Accordingly, explanation of the operations will be omitted. 
     Reference letters PR 1  to PR 2  m represent so-called pointers functioning as a ring counter in the serial output mode. Reference letters FF 1  to FF 2  m represent flip-flop circuits. The pointers and flip-flop circuits perform the same function as the shift register group shown in FIGS. 1 and 2. Each of the pointers PR 1  to PR 2  m can shift the signal &#34;1&#34; in response to the clock signal S CLK . That is, the signal &#34;1&#34; is sequentially shifted from the first pointer PR 1  to the final pointer PR 2  m. Accordingly, only one pointer becomes &#34;1&#34;. The other pointers become &#34;0&#34;. In this case, a preset means may be provided in order to preset the pointer PR 1  so as to become &#34;1&#34; at the start position of the serial operation. When a pointer becomes &#34;1&#34;, the corresponding gate is turned ON and the data latched in the flip-flop circuit is read out through the data bus SDB. Accordingly, the data in the RAM is sequentially read out through the shift data bus SDB by the sequential turning ON of each gate in response to the signal &#34;1&#34; of the pointer. 
     If defective data is latched in the flip-flop circuit FF 2 , when the pointer PR 2  becomes &#34;1&#34;, the gate G 2  is turned ON and the defective data is sent to the multiplexer MPX through the amplifier AMP 1 . Also, when the pointer PR 2  becomes &#34;1&#34;, the gate G R1  is turned ON by the coincidence signal SCOM1 sent from the comparator COMP1. Accordingly, the correct data latched in the redundancy flip-flop circuit RFF 1  is read out to the amplifier AMP 2  through the gate G R1  and the redundancy data bus RDB. Since the coincidence signal SCOM1 is simultaneously input to the multiplexer MPX, the multiplexer MPX can replace the defective data with the correct data. 
     In this case, as explained in FIG. 1, the coincidence signal SCOM1 is generated when the comparator COMP1 compares the number of the defective column address stored in the redundancy ROM 1 with the number of the m-bit counter and detects coincidence therebetween. The m-bit counter is preset by the transfer gate signal STG. 
     As can be understood, the same explanations apply to the second redundancy column using the redundancy ROM 2, the comparator COMP2, and the coincidence signal SCOM2. 
     This method using pointers can reduce power consumption compared with the method using shift registers shown in FIGS. 1 and 2. This is because each shift register must sequentially transfer data to the next shift register. Conversely, only one selected point need transfer data to the output. 
     FIG. 4 is a block diagram of a semiconductor memory device according to still another embodiment of the present invention. In FIG. 4, the same structure as that of FIG. 3 is used for the random access mode. 
     During the serial output mode, the shift data bus SDB is used for the redundancy data bus RDB. Accordingly, the redundancy data bus RDB is eliminated and the redundancy flip-flop circuits RFF 1  and RFF 2  are connected to the shift data bus SDB through the gates G R1  and G R2 . 
     In this embodiment, the gate corresponding to the defective data, for example, the gate G 2 , is not turned ON since the corresponding pointer PR 2  does not output the signal &#34;1&#34;. In this case, all pointers become &#34;0&#34; because the clock signal S CLK  is not applied to them. Alternatively, the gate G R1  is turned ON at the same time based on the coincidence signal SCOM1 so that the correct data latched in the redundancy flip-flop circuit RFF 1  is output to the amplifier AMP 1  through the gate G R1  and the shift data bus SDB. Regarding the pointers coupled to the column decoder, since the start position of the signal &#34;1&#34; pointer can be arbitrarily selected by the column decoder, the corresponding gate can be turned ON so that the data stored in the RAM can be read out from the corresponding column. That is, an arbitrary head address can be designated by the pointer. This is advantageous for so-called &#34;scrolling&#34; of the image data. As can be understood, advantages similar to those of the embodiment shown in FIG. 3 are obtained by this embodiment.