Abstract:
A driver stage uses a primary driver and a secondary driver to balance drive current when transmitting a new data bit different than bits consecutively transmitted immediately previous to the new data bit. The primary driver activates one of a pull-down device and a pull-up device whenever transmitting a data bit. The secondary driver activates one of its pull-down device and a pull-up device when two or more consecutive are detected to be transmitted. In this case, current flow of the driver stage induced by the first of the consecutive bits is reduced by the secondary driver.

Description:
BACKGROUND OF INVENTION  
         [0001]    As shown in FIG. 1, a typical computer system  10  has, among other components, a microprocessor  12 , one or more forms of memory  14 , integrated circuits  16  having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths  18 , e.g., wires, buses, etc., to accomplish the various tasks of the computer system  10 .  
           [0002]    When an integrated circuit ( 16  in FIG. 1) communicates with another integrated circuit, i.e., “chip-to-chip communication,” data is transmitted in a series of binary 0&#39;s and 1&#39;s from a transmitting circuit to a receiving circuit. Accordingly, at any particular time, a data signal received at the receiving circuit may have a low voltage potential representative of a binary ‘0’ or a high voltage potential representative of a binary ‘1.’ 
           [0003]    [0003]FIG. 2 shows a portion of a typical transmission system  20 . The transmission system  20  includes a transmitting circuit  22 , a data channel (also known as a “board trace”)  24 , and a receiving circuit  26 . Generally, circuit-to-circuit wireline communication occurs by one circuit transmitting data and another circuit receiving the data over wires implemented on a computer board on which the sending and receiving circuits are disposed. As shown in FIG. 2, the transmitting circuit  22  drives data into the data channel  24  using the a driver stage  28  formed by a first driver  30  and a second driver  32 . The receiving circuit  26  receives the data at the other end of the data channel  24  using some receiving device  34 .  
           [0004]    As mentioned above, in data signaling, a data bit is driven into the data channel  24  using specific voltage levels, i.e., logic high and logic low. In binary transmission, in which data is coded as a series of 1&#39;s and 0&#39;s, a ‘1’ could be represented by any voltage above a particular value and a ‘0’ could be represented by any voltage below a particular value.  
           [0005]    [0005]FIG. 3 shows a schematic of the driver stage  28  shown in FIG. 2. The first driver  30  is formed using a pull-up device  36  and a pull-down device  38 , and the second driver  32  is formed using a pull-up device  40  and a pull-down device  42 . Those skilled in the art will understand that the inputs to the driver  30  and the second driver  32  are controlled separately in order to control, among other things, crow bar currents and voltage swing levels on the data channel  24 . When activated, each of the pull-up and pull-down devices  36 ,  38 ,  40 , and  42  effectively form a resistance, and when deactivated, each of the pull-up and pull-down devices  36 ,  38 ,  40 , and  42  form an open circuit, or +infinite resistance.  
           [0006]    [0006]FIG. 4 shows different states of the driver stage  28 . When the driver stage  28  drives a ‘1,’ the pull-up devices  36  and  40  of the first and second drivers  30  and  32 , respectively, are switched ‘on,’ or otherwise activated, and the pull-down devices  38  and  42  of the first and second drivers  30  and  32 , respectively, are switched ‘off,’ or otherwise deactivated. This arrangement of the pull-up and pull-down devices  36 ,  38 ,  40 , and  42  causes the driver stage  28  to pull up the voltage value on the data channel  24 .  
           [0007]    Alternatively, when the driver stage  28  drives a ‘0,’ the pull-down devices  38  and  42  of the first and second drivers  30  and  32 , respectively, a reswitched ‘on,’ or otherwise activated, and the pull-up devices  36  and  40  of the first and second drivers  30  and  32 , respectively, are switched ‘off,’ or otherwise deactivated. This arrangement of the pull-up and pull-down devices  36 ,  38 ,  40 , and  42  causes the driver stage  28  to pull down the voltage value on the data channel  24 .  
           [0008]    As discussed with reference to FIG. 4, the driver stage  28 , when driving a ‘1,’ places a voltage step on the data channel  24 . However, because the data channel  24  is typically lossy at high frequencies, the voltage step generated by the driver stage  28  suffers skin effect and dielectric loss. Losses in long data channels do not only introduce attenuation of data signal integrity, but more significantly, cause signal distortion. Such distortion results in intersymbol interference (ISI), which is described below.  
           [0009]    A significant factor in achieving the highest possible data rate relates to the signal to noise ratio present at the receiving circuit. The noise present at the receiving circuit includes noise introduced by the data channel and noise attributable to interference from preceding bits of data. Such interference is ISI. ISI is a distortion in the received signal resulting from the temporal spreading and consequent overlap of individual signal pulses and to the degree that the receiving circuit cannot reliably distinguish between changes of state. It follows that at a certain threshold, intersymbol interference compromises the integrity of the data signal at the receiving circuit.  
           [0010]    All of the effects discussed above that result from signal attenuation along the data channel leads to data jitter, which means that data does not reach a receiving circuit at the same time with respect to a clock signal for every data bit sent. This leads to uncertainty in data capture at the receiving circuit. Moreover, when a series of 1&#39;s or 0&#39;s are transmitted over a long data channel, jitter is amplified because the voltage swing at the receiving circuit increases or decreases depending on the number of consecutive 1&#39;s or 0&#39;s transmitted.  
           [0011]    To this end, FIG. 5 shows a behavior of a data signal  50  in the transmission system  20  shown in FIG. 2 and using a driver stage  28  as described with reference to FIGS. 3 and 4. In the bit sequence shown in FIG. 5, the transmittal of the first four bits, ‘0101,’ to the data channel ( 24  in FIGS. 2, 3, and  4 ) from the driver stage ( 28  in FIGS. 2, 3, and  4 ) occurs by switching the state of the driver stage ( 28  in FIGS. 2, 3, and  4 ) between the ‘0’ arrangement and ‘1’ arrangement shown in FIG. 4. The next several bits transmitted by the driver stage ( 28  in FIGS. 2, 3, and  4 ) are 0&#39;s, and thus, the driver stage ( 28  in FIGS. 2, 3, and  4 ) remains in the ‘0’ arrangement shown in FIG. 4 for some amount of time.  
           [0012]    As shown in FIG. 5, as the driver stage ( 28  in FIGS. 2, 3, and  4 ) remains in the ‘0’ arrangement shown in FIG. 4, the data signal  50  drifts to a voltage value below the ‘0’ threshold. Then, when the driver stage ( 28  in FIGS. 2, 3, and  4 ) is again required to transmit a ‘1,’ the voltage step driven onto the data channel ( 24  in FIGS. 2, 3, and  4 ) by the driver stage ( 28  in FIGS. 2, 3, and  4 ) results in the data signal  50  reaching a voltage value less than that reached previously when driving a ‘1.’ Accordingly, as discussed above, such signal attenuation leads to ISI and increased data jitter.  
           [0013]    [0013]FIG. 6 shows a behavior of a data signal  51  in the transmission system  20  shown in FIG. 2 and using a driver stage  28  as described with reference to FIGS. 3 and 4. In the bit sequence shown in FIG. 6, the transmittal of the first four bits, ‘0101,’ to the data channel ( 24  in FIGS. 2, 3, and  4 ) from the driver stage ( 28  in FIGS. 2, 3, and  4 ) occurs by switching the state of the driver stage ( 28  in FIGS. 2, 3, and  4 ) between the ‘0’ arrangement and ‘1’ arrangement shown in FIG. 4. The next several bits transmitted by the driver stage ( 28  in FIGS. 2, 3, and  4 ) are 1&#39;s, and thus, the driver stage ( 28  in FIGS. 2, 3, and  4 ) remains in the ‘1’ arrangement shown in FIG. 4 for some amount of time.  
           [0014]    As shown in FIG. 6, as the driver stage ( 28  in FIGS. 2, 3, and  4 ) remains in the ‘1’ arrangement shown in FIG. 4, the data signal  51  drifts to a voltage value above the ‘1’ threshold. Then, when the driver stage ( 28  in FIGS. 2, 3, and  4 ) is again required to transmit a ‘0,’ the voltage drop driven onto the data channel ( 24  in FIGS. 2, 3, and  4 ) by the driver stage ( 28  in FIGS. 2, 3, and  4 ) results in the data signal  51  reaching a voltage value greater than that reached previously when driving a ‘0.’ Accordingly, similar to the situation discussed with reference to FIG. 5, such signal attenuation leads to ISI and increased data jitter.  
         SUMMARY OF INVENTION  
         [0015]    According to one or more embodiments of the present invention, a transmission system comprises: a driver stage operatively connected to a data channel, where the driver stage comprises a primary driver arranged to induce a first current flow in the driver stage dependent upon detection of a first data bit to be transmitted to the data channel, and a secondary driver arranged to reduce the first current flow dependent upon detection of a second data bit to be transmitted to the data channel, where the first data bit is logically equal to the second data bit; and a receiving circuit operatively connected to the data channel.  
           [0016]    According to one or more embodiments of the present invention, a method for transmitting a data signal using a driver circuit comprises: detecting for a pattern of bits on the data signal; when consecutive bits of the same value are detected, inducing partial current flow in the driver circuit in a direction opposite to a flow of current induced by the driver circuit when the first of the consecutive bits was detected; and transmitting the data signal.  
           [0017]    According to one or more embodiments of the present invention, an apparatus comprises: means for propagating a signal between at least two circuits; means for driving the signal onto the means for propagating, where the means for driving comprises primary means for driving on the signal a first bit, where a first flow of current is induced in the means for driving when driving the first bit, and secondary means for reducing the first flow of current in the means for driving when a second bit of the same logic value as the first bit is transmitted; and means for receiving the data signal.  
           [0018]    Other aspects and advantages of the invention will be apparent from the following description and the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0019]    [0019]FIG. 1 shows a typical computer system.  
         [0020]    [0020]FIG. 2 shows a portion of a typical transmission system.  
         [0021]    [0021]FIG. 3 shows a typical driver stage.  
         [0022]    [0022]FIG. 4 shows states of the driver stage shown in FIG. 3.  
         [0023]    [0023]FIG. 5 shows a behavior of a data signal in the transmission system shown in FIG. 2 and using the driver stage shown in FIG. 3.  
         [0024]    [0024]FIG. 6 shows a behavior of a data signal in the transmission system shown in FIG. 2 and using the driver stage shown in FIG. 3.  
         [0025]    [0025]FIG. 7 shows a driver stage in accordance with an embodiment of the present invention.  
         [0026]    [0026]FIG. 8 shows states of a driver stage in accordance with an embodiment of the present invention.  
         [0027]    [0027]FIG. 9 shows a state of a driver stage in accordance with an embodiment of the present invention.  
         [0028]    [0028]FIG. 10 shows a behavior of a data signal using the driver stage shown in FIG. 8.  
         [0029]    [0029]FIG. 11 shows a state of a driver stage in accordance with an embodiment of the present invention.  
         [0030]    [0030]FIG. 12 shows a behavior of a data signal using the driver stage shown in FIG. 10. 
     
    
     DETAILED DESCRIPTION  
       [0031]    Embodiments of the present invention relate to a transmission system driver stage that balances drive current so as to improve data transmission across the transmission system.  
         [0032]    A driver stage in accordance with embodiments of the present invention uses a primary driver and a secondary driver. Collectively, the driver stage uses two pull-down devices (or units) and two pull-up devices (or units), where one pair including a pull-up device and a pull-down device is weaker in strength than the another pair including the other pull-up device and the other pull-down device. The primary driver is used to drive every data bit onto a data channel. When two consecutive bits of the same state are detected, one of the pull-up device and the pull-down device in the secondary driver is activated to induce current flow on the data channel in a direction opposite to that induced by the primary driver when the first of the consecutive bits was detected.  
         [0033]    [0033]FIG. 7 shows a driver stage  59  in accordance with an embodiment of the present invention. The driver stage  59  includes a primary driver  60  and a secondary driver  62 . The primary driver  60  uses a pull-up device  64  and a pull-down device  66 , and the secondary driver  62  uses a pull-up device  68  and a pull-down device  70 . Note that unlike the driver stage shown in FIG. 3, the pull-up device  64  and pull-down device  66  in the primary driver  60  (corresponding to the first driver  30  in FIG. 3) are stronger than the pull-up device  68  and the pull-down device  70  in the secondary driver  62  (corresponding to the second driver  32  in FIG. 3). When activated, each of the pull-up and pull-down devices  64 ,  66 ,  68 , and  70  effectively form a resistance, and when deactivated, each of the pull-up and pull-down devices  64 ,  66 ,  68 , and  70  form an open circuit, or infinite resistance.  
         [0034]    Referring now to FIG. 8, when the driver stage  59  shown in FIG. 7 is required to transmit alternating data bits, i.e., 01&#39;s and 10,&#39; the driver stage  59  toggles between the ‘0’ arrangement and ‘1’ arrangement shown in FIG. 7. As shown in FIG. 7, whenever the transmittal of alternating data bits is detected, the pull-up device  68  and the pull-down device  70  in the secondary driver  62  are deactivated, or switched ‘off,’ and the primary driver  60  is solely used to drive the data bits onto a data channel  61 .  
         [0035]    When transmitting a ‘0’ in an alternating data bit pattern, the pull-up device  64  in the primary driver  60  is deactivated, or switched ‘off,’ and the pull-down device  66  in the primary driver  60  is activated, or switched ‘on.’ This ‘0’ arrangement causes the driver stage  59  to pull down the voltage on the data channel  61 .  
         [0036]    When transmitting a ‘1’ in an alternating data bit pattern, the pull-up device  64  in the primary driver  60  is activated, or switched ‘on,’ and the pull-down device  66  in the primary driver  60  is deactivated, or switched ‘off.’ This ‘1’ arrangement causes the driver stage  59  to pull up the voltage on the data channel  61 .  
         [0037]    Referring now to FIG. 9, when consecutive 0&#39;s are detected to be transmitted, the driver stage  59  is controlled to enter the arrangement shown in FIG. 9. Particularly, when consecutive 0&#39;s are transmitted, the pull-up device  68  in the secondary driver  62  is activated, or switched ‘on,’ in addition to the pull-down device  66  in the primary driver  60  already being activated due to the detection of at least one ‘0.’ Because the pull-up device  68  in the secondary driver  62  is activated, current flow is induced as shown by the arrow in FIG. 9 in a direction opposite to that induced by the primary driver  60  when the first of the consecutive 0&#39;s was detected (those skilled in the art will understand that the direction of the main current flow occurs from the data channel  61  through device  66  to ground). This arrangement thus balances the drive current in the driver stage  59 . When a ‘1’ is transmitted (after consecutive 0&#39;s), pull-up device  64  is activated, and because some of the current is already flowing in a direction now induced by the driver stage  59 , the magnitude of current change is reduced, thereby reducing power supply bounce on the data channel  61 , which, in turn leads to improved edge rates. The effect of such an arrangement on the behavior of a data signal both at the driver side and the receiver side is shown by the data signal  65  in FIG. 10.  
         [0038]    Referring now to FIG. 11, when consecutive 1&#39;s are detected to be transmitted, the driver stage  59  is controlled to enter the arrangement shown in FIG. 11. Particularly, when consecutive 1&#39;s are transmitted, the pull-down device  70  in the secondary driver  62  is activated, or switched ‘on,’ in addition to the pull-up device  64  in the primary driver  60  already being activated due to the detection of at least one ‘1.’ Because the pull-down device  70  in the secondary driver  62  is activated, current flow is induced as shown by the arrow in FIG. 11 in a direction opposite to that induced by the primary driver  60  when the first of the consecutive 1&#39;s was detected. This arrangement thus balances the drive current in the driver stage  59 . When a ‘0’ is transmitted (after consecutive 1&#39;s), pull-down device  66  is activated, and because some of the current is already flowing in a direction now induced by the driver stage  59 , the magnitude of current change is reduced, thereby reducing power supply bounce on the data channel  61 , which, in turns, leads to improved edge rates. The effect of such an arrangement on the behavior of a data signal at both the driver stage and the receiver stage is shown by the data signal  67  in FIG. 12.  
         [0039]    Advantages of the present invention may include one or more of the following. In one or more embodiments, because the magnitude of current change is reduced when a new data bit is transmitted after a consecutive series of data bits, power supply bounce on a data channel propagating the data bits may be reduced. Accordingly, improved edge rates may be achieved.  
         [0040]    In one or more embodiments, because the magnitude of current change is reduced when using a driver stage that balances drive current, delay variation may be reduces, thereby leading to reduced data jitter.  
         [0041]    In one or more embodiments, because the magnitude of current change is reduced when using a driver stage that balances drive current, signal loss typical on a data channel at a high frequency may be reduced.  
         [0042]    While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.