Abstract:
A flash memory device has an improved pre-program function. The flash memory device comprises memory cell blocks each including wordlines, bitlines, and memory cells sharing common source lines; an erase controller generating a pre-program control signal in response to an erase command; and a voltage selection circuit selecting one of first and second common source voltages in response to one among the pre-program control signal, a read command, and a program command and outputting the selected voltage to a global common source line.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
   The present application claims priority to Korean Patent Application No. 10-2005-20189, filed on Mar. 10, 2005, which is incorporated by reference. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to a semiconductor memory device and method of controlling an operation thereof and specifically, to a flash memory device and method for controlling a pre-program operation. 
   In general, a flash memory device is operable in a read operation, a program operation, and an erase operation. The erase operation is accomplished with Fowler-Nordheim tunneling effect induced at an insulation film between a P-well and a floating gate of a memory cell. By the erase operation, data stored in all memory cells in a memory cell block are erased at a time. The erase operation is carried out in the unit of memory cell block. There would be memory cells that have been already erased (i.e., memory cells programmed with data ‘0’). As the pre-erased memory cells have low threshold voltages, it would produce over-erasure when the erase operation is resumed (i.e., the threshold voltages are lowered too much). Therefore, in purpose of preventing such a result, the procedure of erasing the flash memory device includes a pre-program operation to adjust the threshold voltages of the whole memory cells on a first predetermined voltage level by preliminarily programming the whole memory cells before the erase operation. Meanwhile, the erasing speed of the memory cells included in the flash memory device may vary in accordance with manufacturing process conditions. In other words, there would be memory cells with faster erasing speed and memory cells with slower erasing speed. Thus, if an erasing time is established to the memory cells with the slower erasing speed, the memory cells with the faster erasing speed may be over-erased. In order to prevent such a result, the erasing procedure includes a post-program operation to adjust the threshold voltages of the whole memory cells on a second predetermined voltage levels by conducting a program operation for the whole memory cells for a predetermined time after the erase operation. 
     FIG. 1  is a circuit diagram illustrating memory cell blocks and bitline selection circuits, explaining a pre-program operation in a conventional flash memory device. Referring to  FIG. 1 , there are disclosed memory cell blocks MR 1 ˜MRN (N is an integer) and the bitline selection circuit  10 . For simplification of the drawing, there are just disclosed memory cells that are connected to a pair of bitlines BLe and BLo, among memory cells included in each of the memory cell blocks MR 1 ˜MRN. For example, while executing the pre-program operation for the memory cell block MR 1 , a power source voltage VCC is applied to a drain selection line DSL and a ground voltage 0V is applied to a source selection line SSL. As a result, a drain selection transistor DST of the memory cell block MR 1  is turned on while a source selection transistor SST is turned off. A high voltage HVP (e.g., 15˜20V) is applied to wordlines WL 0 ˜WLM (M is an integer). Thus, memory cells C 0 ˜CM of the memory cell block MR 1  are turned on. And, the power source voltage VCC is applied to a common source line CSL and NMOS transistors N 1  and N 2  of the bitline selection circuit  10  are turned on to apply a signal VIRPWR to the bitlines BLe and BLo. During this, the signal VIRPWR has a voltage level of 0 and NMOS transistors N 3  and N 4  of the bitline selection circuit  10  are turned off in response to selection signals BSLe and BSLo. As a result, a great voltage gap is generated between drains and gates of the memory cells C 0 ˜CM (M is an integer), which causes injection of electrons to floating gates of the memory cells C 0 ˜CM to conduct the pre-program operation. 
   As aforementioned, the memory cells C 0 ˜CM are pre-programmed by the voltage of 0V applied to the bitlines BLo and BLe. Meanwhile, as the bitlines BLe and BLo are shared by all the memory cell blocks MR 1 ˜MRN, they have very large loading capacitance. Thus, it increases the time for sufficiently discharging the bitlines BLo and BLe to 0V in response to the signal VIRPWR, increasing the amount of current consumption. Further, the parasitic capacitance, under the bitlines BLe and BLo, caused by the high voltage HVP applied to the wordlines WL 0 ˜WLM acts to further increase the discharging time and current consumption. Therefore, in the pre-program operation in the conventional flash memory device, the discharging time of the bitlines BLe and BLo increases to make the whole erasing time longer and current consumption larger. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention is directed to flash memory devices. An embodiment of the present invention provides a flash memory device capable of reducing a pre-program time and current consumption by separating bitlines from memory cells and applying program bias voltages through a common source line during a pre-program operation. 
   Another embodiment of the present invention is directed to a method of controlling a pre-program operation in flash memory device, capable of reducing a pre-program time and current consumption by separating bitlines from memory cells and applying program bias voltages through a common source line during the pre-program operation. 
   An aspect of the present invention is to provide a flash memory device comprising: memory cell blocks each including wordlines, bitlines, and memory cells sharing common source lines; an erase controller generating a pre-program control signal in response to an erase command; and a voltage selection circuit selecting one of first and second common source voltages in response to one among the pre-program control signal, a read command, and a program command and outputting the selected voltage to a global common source line. Preferably, the global common source line is connected to the common source line of each of the memory cell blocks, and memory cells of the memory cell block in a pre-program operation are isolated from the bitlines but connected to the common source line, and wordline bias voltages are applied to the wordlines of the memory cells for the pre-program operation. 
   Another aspect of the present invention is to provide a method for controlling a pre-program operation of a flash memory device, the method comprising the steps of: generating a pre-program control signal in response to an erase command; supplying a common source voltage of a ground voltage level to a global common source line, which is connected to a common source line of each of memory cell blocks, in response to the pre-program control signal; selecting one or a part of the memory cell blocks in response to a row address signal; connecting memory cells of the selected memory cell block(s) to the common source line from bitlines; and supplying wordline bias voltages, for a pre-program operation, to wordlines connected to gates of the memory cells of the selected memory cell block(s). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings: 
       FIG. 1  is a circuit diagram illustrating memory cell blocks and bitline selection circuits, explaining a pre-program operation in a conventional flash memory device; 
       FIG. 2  is a block diagram illustrating a flash memory device in accordance with an embodiment of the present invention; 
       FIG. 3  is a detailed circuit diagram illustrating memory cell blocks, a block selection circuit, a bitline selection circuit, a first voltage selection circuit, and a second voltage selection circuit, those shown in  FIG. 2 ; 
       FIG. 4  is a sectional diagram illustrating a cell string shown in  FIG. 3 ; and 
       FIG. 5  is a graphic diagram showing a distribution profile of threshold voltages of memory cells by the pre-program operation of the flash memory device according to the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numerals refer to like elements throughout the specification. 
     FIG. 2  is a block diagram illustrating a flash memory device in accordance with an embodiment of the present invention. Referring to  FIG. 2 , the flash memory device  100  is comprised of an input buffer  101 , a control logic circuit  102 , a device controller  103 , a high voltage controller  104 , memory cell blocks MB 1 ˜MBK (K is an integer), an X-decoder  105 , a block selection circuit  106 , a first voltage selection circuit  107 , a second voltage selection circuit  108 , a bitline selection circuit  109 , a page buffer  110 , a Y-decoder  111 , and a data input/output buffer  112 . The input buffer  101  receives a command signal CMD and an address signal ADD and then outputs them to the control logic circuit  102 . The control logic circuit  102  receives the command signal CMD or the address signal ADD in response to external control signals/WE,/RE, ALE, and CLE. The control logic circuit  102  generates one among an erase command ERS, a read command READ, and a program command PGM in response to the command signal CMD. The control logic circuit  102  also generates row and column address signals, RADD and CADD, on basis of the address signals ADD. 
   The erase controller  103  generates one among a pre-program control signal PRPGM, an erase control signal ERSC, and a post-program control signal PSPGM in response to the erase command ERS. Alternatively, the flash memory device  100  may include a pre-program controller (not shown) instead of the erase controller  103 , which generates the pre-program control signal PRPGM in response to the erase command ERS. 
   The high voltage generator  104  generates a drain selection line voltage VGD, a source selection line voltage VGS, and wordline bias voltages VW 1 ˜VWJ (J is an integer) in response to one among the pre-program control signal PRPGM, the erase control signal ERSC, and the post-program control signal PSPGM, or one of the read command READ and the program command PGM and a row decoding signal RDEC. Preferably, the high voltage generator  104  generates the drain selection line voltage VGD of the ground voltage level (i.e., 0V), the source selection line voltage VGS of a predetermined voltage (e.g., 0.5˜10V), and the wordline bias voltages VW 1 ˜VWJ of a voltage level (15˜20V) for programming in response to the pre-program control signal PRPGM and the post-program control signal PSPGM. 
   In addition, the high voltage generator  104  generates the drain selection line voltage VGD, the source selection voltage VGS, and the wordline bias voltages VW 1 ˜VWJ, of the ground voltage level (i.e., 0V), in response to the erase control signal ERSC. The high voltage generator  104  generates the drain and source selection line voltages VGD and VGS with a high voltage level (e.g., 4.5V), one group of the wordline bias voltages VW 1 ˜VWJ with the ground voltage level, and the other group of the wordline bias voltages in the high voltage level, responding to the read command READ and the row decoding signal RDEC. The high voltage generator  104  generates the drain selection line voltage VGD with the power source voltage level VCC, the source selection line voltage VGS with the ground voltage level, one group of the wordline bias voltages VW 1 ˜VWJ in a program voltage (e.g., 18V), and the rest of the wordline bias voltages in a pass voltage (e.g., 10V), responding to the program command PGM and the row decoding signal RDEC. 
   The high voltage generator  104  outputs the drain selection line voltage VGD, the source selection line voltage VGS, the wordline bias voltages VW 1 ˜VWJ to a global drain selection line GDSL, a global source selection line GSSL, and global wordlines GWL 1 ˜GWLJ (J is an integer). Further, the high voltage generator  104  generates one among bulk voltages VCB 1  and VCB 2  and applies the bulk voltage to the P-well of the memory cells of each memory cell block in response to one among the pre-program control signal PRPGM, the erase control signal ERSC, the post-program control signal PSPGM, the read command READ, and the program command PGM. Preferably, the high voltage generator  104  generates the bulk voltage VCB 1  in response to the erase control signal ERSC, and generates the bulk voltage VCB 2  in response to one among the pre-program control signal PRPGM, the post-program control signal PSPGM, the read command READ, and the program command PGM. The bulk voltage VCB 1  is a high voltage (e.g., 20V) while the bulk voltage VCB 2  is the ground voltage. 
   The X-decoder  105  decodes the row address signal RADD and outputs the row decoding signal RDEC. The block selection circuit  106  selects one or a part of the memory cell blocks MB 1 ˜MBK in response to the row decoding signal RDEC. The first voltage selection circuit  107  selects one of first and second common source voltages VCS 1  and VCS 2  and outputs the selected one to the global common source line GCSL, in response to one among the pre-program control signal PRPGM, the erase control signal ERSC, the post-program control signal PSPGM, the read command READ, and the program command PGM. Preferably, the first voltage selection circuit  107  selects the first common source voltage VCS 1  in response to one among the pre-program control signal PSPGM, the erase control signal ERSC, the post-program control signal PSPGM, and the read command READ. Further, the first voltage selection circuit  107  selects the second common source voltage VCS 2  in response to the program command PGM. The global common source line GCSL is connected to common source lines CSL 1 ˜CSLK of the memory cell blocks MB 1 ˜MBK. 
   The second voltage selection circuit  108  selects one of first through third voltages VP 1 ˜VP 3  in response to one among the pre-program control signal PRPGM, the erase control signal ERSC, the post-program control signal PSPGM, the read command READ, and the program command PGM. Preferably, the second voltage selection circuit  108  selects the first voltage VP 1  in response to one among the pre-program control signal PRPGM, the erase control signal ERSC, and the post-program control signal PSPGM. And, the second voltage selection circuit  108  selects the second voltage VP 2  in response to the read command READ and selects the third voltage VP 3  in response to the program command PGM. 
   The bitline selection circuit  109  applies the control voltage VIRPWR to a part or all of the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon (n is an integer) shared by the memory cell blocks MB 1 ˜MBK, in response to the column decoding signal CDEC or one among the pre-program control signal PRPGM, the erase control signal ERSC, and the post-program control signal PSPGM. Further, the bitline selection circuit  109  connects or disconnects a part or all of the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon with page buffer  110  in response to the column decoding signal CDEC or one among the pre-program control signal PRPGM, the erase control signal ERSC, and the post-program control signal PSPGM. Preferably, the bitline selection circuit  109  supplies the control voltage VIRPWR to all of the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon and disconnects the all of the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon from the page buffer  110 , in response to the pre-program control signal PRPGM or the post-program control signal PSPGM. The structures and operation of the page buffer  110 , the Y-decoder  111 , and the data input/output buffer  112  are well known by those skilled in the art, so it will not be described. 
     FIG. 3  is a detailed circuit diagram illustrating the memory cell blocks, the block selection circuit, the bitline selection circuit, the first voltage selection circuit, and the second voltage selection circuit, from those shown in  FIG. 2 . Each of the memory cell blocks MB 1 ˜MBK includes the wordlines WL 1 ˜WLJ, the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon, and memory cells MC 1 ˜MCJ (J is an integer) sharing the common source line (one of CSL 1 ˜CSLK). The structures and operations of the memory cell blocks MB 1 ˜MBK are similar to each other, so it will be described with respect to those of the memory cell block MB 1  as a representative. The memory cell blocks MB 1  includes pluralities of cell strings STe 1 ˜STen and STo 1 ˜STon. Each of the cell strings STe 1 ˜STen and STo 1 ˜STon includes the drain selection transistor DST, the memory cells MC 1 ˜MCJ and the source selection transistor SST. The memory cells MC 1 ˜MCJ are connected in series and the drain selection transistors DST is connected between the bitline BLe 1  and the drain of the memory cell MC 1 . The source selection transistor SST is connected between the common source line CSL 1  and the source of the memory cell MCJ. The gates of the drain selection transistors DST of the cell strings STe 1 ˜STen and STo 1 ˜STon are connected to the drain selection line DSL, and the drains are connected to the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon. The gates of the memory cells MC 1 ˜MCJ of the cell strings STe 1 ˜STen and STo 1 ˜STon are coupled to the wordlines WL 1 ˜WLJ. The gates of the source transistors SST of the cell strings STe 1 ˜STen and STo 1 ˜STon are coupled to the source selection line SSL, and the sources are connected to the common source line CSL 1 . 
   The block selection circuit  106  is connected with the drain selection lines DSL of the memory cell blocks MB 1 ˜MBK, the wordlines WL 1 ˜WLJ, the source selection lines SSL, the global selection line GDSL, the global wordlines GWL 1 ˜GWLJ, and the global source line GSSL. The block selection circuit  106  selects one of a part of the memory cell blocks MB 1 ˜MBK in response to the row decoding signal RDEC. The block selection circuit  106  connects the drain selection line(s) DSL of the selected memory cell block(s) to the global drain selection line GDSL, connects the source selection line(s) SSL of the selected memory cell block(s) to the global source selection line GSSL, and connects the wordlines WL 1 ˜WLJ of the selected memory cell block(s) each to the global wordlines GWL 1 ˜GWLJ. 
   The first voltage selection circuit  107  is comprised of a first selection signal generator  121  and switches SW 11  and SW 12 . The first selection signal generator  121  generates selection signals SEL 11  and SEL 12  in response to one among the read command READ, the pre-program control signal PRPGM, the erase control program ERSC, the post-program control signal PSPGM, and the program command PGM. Preferably, the first selection signal generator  121  enables the selection signal SEL 11  but disables the selection signal SEL 12 , in response to one among the read command READ, the pre-program control signal PRPGM, the erase control program ERSC, and the post-program control signal PSPGM. Further, the first selection signal generator  121  enables the selection signal SEL 12  but disables the selection signal SEL 11 , in response to the program command PGM. The switches SW 11  and SW 12  may be implemented with NMOS transistors. The switch SW 11  is connected between the first common source voltage VCS 1  and the global source line GCSL, being turned on or off in response to the selection signal SEL 11 . The switch SW 12  is connected between the second common source voltage VCS 2  and the global source line GCSL, being turned on of off in response to the selection signal SEL 12 . The global source line GCSL is connected to the common source lines CSL 1 ˜CSLK of the memory cell blocks MB 1 ˜MBK. Preferably, the first common source voltage VCS 1  may be set on the ground voltage (i.e., 0V) and the second common source voltage VCS 2  may be set on the power source voltage VCC. 
   The second voltage selection circuit  108  is comprised of a second selection signal generator  122  and switches SW 21 , SW 22  and SW 23 . The second selection signal generator  122  generates selection signals SEL 21 , SEL 22 , and SEL 23  in response to one among the read command READ, the pre-program control signal PRPGM, the erase control program ERSC, the post-program control signal PSPGM, and the program command PGM. Preferably, the second selection signal generator  122  enables the selection signal SEL 21  but disables the selection signals SEL 22  and SEL 23 , in response to one among the pre-program control signal PRPGM or the post-program control signal PSPGM. Further, the second selection signal generator  122  enables the selection signal SEL 22  but disables the selection signals SEL 21  and SEL 23 , in response to the read command READ or the erase control signal ERSC. Further, the second selection signal generator  122  enables the selection signal SEL 23  but disables the selection signals SEL 21  and SEL 22 , in response to the program command READ. 
   The switch SW 21  is connected between the first voltage VP 1  and the bitline selection circuit  109 , being turned on or off in response to the selection signal SEL 21 . When the switch SW 21  is turned on, the first voltage VP 1  is applied to the bitline selection circuit  109  as the control voltage VIRPWR. The switch SW 22  is connected between the second voltage VP 2  and the bitline selection circuit  109 , being turned on or off in response to the selection signal SEL 22 . When the switch SW 22  is turned on, the second voltage VP 2  is applied to the bitline selection circuit  109  as the control voltage VIRPWR. The switch SW 23  is connected between the third voltage VP 3  and the bitline selection circuit  109 , being turned on or off in response to the selection signal SEL 23 . When the switch SW 23  is turned on, the third voltage VP 3  is applied to the bitline selection circuit  109  as the control voltage VIWR. Preferably, the first voltage VP 1  may be set on the ground voltage or a positive voltage lower than the power source voltage VCC. The second voltage VP 2  may be set on the ground voltage, and the third voltage VP 3  may be set on the power source voltage VCC. 
   The bitline selection circuit  109  is comprised of a selection control circuit  123 , bitline control circuits BLC 1 ˜BLCn (n is an integer), and bitline selection circuits SL 1 ˜SLn (n is an integer). The selection control circuit  123  generates bitline control signals DCHe 1 ˜DCHen and DCHo 1 ˜DCHon and bitline selection signals BSLe 1 ˜BSLen and BSLo 1 ˜BSLon in response to one the column decoding signal CDEC or one among the pre-program control signal PRPGM, the erase control signal ERSC, and the post-program control signal PSPGM. Preferably, the selection control circuit  123  partially enables the bitline control and selection signals, DCHe 1 ˜DCHen and DCHo 1 ˜DCHon, and BSLe 1 ˜BSLon and BSLo 1 ˜BSLon, in response to the column decoding signal CDEC. As a result, the control voltage VIRPWR is partially supplied to the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon. The bitlines among Ble 1 ˜BLen and BLo 1 ˜BLon, which are supplied with the control voltage VIRPWR, are connected to the page buffer  110  (refer to  FIG. 2 ). 
   The selection control circuit  123  enables all the bitline control signals DCHe 1 ˜DCHen and DCHo 1 ˜DCHon but disables all the bitline selection signals BSLe 1 ˜BSLen and BSLo 1 ˜BSLon, in response to one among the pre-program control signal PRPGM, the erase control signal ERSC, and the post-program control signal PSPGM. As a result, the control voltage VIRPWR is applied to all the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon, and the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon are isolated from the page buffer  110 . 
   The bitline control circuits BLC 1 ˜BLCn supply the control voltage VIRPWR to a part or all of the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon in response to the bitline control signals DCHe 1 ˜DCHen and DCHo 1 ˜DCHon. As the structures and operations of the bitline control circuits BLC 1 ˜BLCn are similar to each other, it will be described through the bitline control circuit BLC 1  as an example. The bitline control circuit BLC 1  is comprised of NMOS transistors N 1  and N 2 . The drain and source of the NMOS transistor N 1  are connected each to the bitline BLe 1  and the control voltage VIRPWR, and the gate thereof is supplied with the bitline control signal DCHe 1 . The NMOS transistor N 1  is turned on or off in response to the bitline control signal DCHe 1 . Preferably, when the bitline control signal DCHe 1  is enabled, the NMOS transistor N 1  is turned on to precharge the bitline BLe 1  to the level of the control voltage VIRPWR. The drain and source of the NMOS transistor N 2  are connected each to the bitline BLo 1  and the control voltage VIRPWR, and the gate thereof is supplied with the bitline control signal DCHo 1 . The NMOS transistor N 2  is turned on or off in response to the bitline control signal DCHo 1 . Preferably, when the bitline control signal DCHo 1  is enabled, the NMOS transistor N 2  is turned on to precharge the bitline BLo 1  to the level of the control voltage VIRPWR. 
   The selection circuits SL 1 ˜SLn connects or disconnects the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon partially or entirely with the page buffer  10  in response to the bitline selection signals BSLe 1 ˜BSLen and BSLo 1 ˜BSLon. As the structures and operations of the bitline selection circuits SL 1 ˜SLn are similar to each other, it will be described through the bitline selection circuit SL 1  as an example. The bitline selection circuit SL 1  is comprised of NMOS transistors N 3  and N 4 . The drain and source of the NMOS transistor N 3  are connected each to the bitline BLe 1  and a sensing node SN, and the gate thereof is supplied with the bitline selection signal BSLe 1 . The sensing node SN is connected to the page buffer  110 . The NMOS transistor N 3  is turned on or off in response to the bitline selection signal BSLe 1 . Preferably, when the bitline selection signal BSLe 1  is enabled, the NMOS transistor N 3  is turned on to connect the bitline BLe 1  to the sensing node SN. As a result, the bitline BLe 1  is connected to the page buffer  110 . The drain and source of the NMOS transistor N 4  are connected each to the bitline BLo 1  and the sensing node SN, and the gate thereof is supplied with the bitline selection signal BSLo 1 . The NMOS transistor N 4  is turned on or off in response to the bitline selection signal BSLo 1 . Preferably, when the bitline selection signal BSlo 1  is enabled, the NMOS transistor N 4  is turned on to connect the bitline BLo 1  to the sensing node SN. As a result, the bitline BLo 1  is connected to the page buffer  110 . 
   Now, it will be described about the pre-program operation of the flash memory device  100  in more detail. First, the control logic circuit  102  generates the erase command ERS in response to the command signal CMD and the external control signals/WE,/RE, ALE, and CLE, and generates the row address signal RADD with reference to the address signal. The erase controller  103  generates the pre-program control signal PRPGM in response to the erase command ERS. Responding to the pre-program control signal PRPGM, the high voltage generator  104  generates the drain selection line voltage VGD, the source selection line voltage VGS, and the wordline bias voltages VW 1 ˜VWJ. While this, the high voltage generator  104  outputs the drain selection line voltage VGD with the ground voltage level and outputs the source selection line voltage VGS with a voltage level higher than the drain selection line voltage VGD. For instance, the source selection line voltage VGS may be set on a voltage in the range of 0.5˜10V. The high voltage generator  104  also outputs the wordline bias voltages VW 1 ˜VWJ with a voltage level (e.g., 15˜20V) for the pre-program operation. The high voltage generator  104  applies the drain selection line voltage VGD to the global drain selection line GDSL and applies the source selection line voltage VGS to the global source selection line GSSL. Further, the high voltage generator  104  applies the wordline bias voltages VW 1 ˜VWJ each to the global wordlines GWL 1 ˜GWLJ. 
   The X-decoder  105  decodes the row address signal RADD and outputs the row decoding signal RDEC. The block selection circuit  106  selects one or a part of the memory cell blocks MB 1 ˜MBK in response to the row decoding circuit RDEC. For instance, when the block selection circuit  106  selects the memory cell block MB 1 , it connects the drain selection line DSL of the memory cell block MB 1  to the global drain selection line GDSL, the source selection line SSL of the memory cell block MB 1  to the global source selection line GSSL, and the wordlines WL 1 ˜WLJ each to the global wordlines GWL 1 ˜GWLJ. As a result, the drain selection line voltage VGD, the source selection line voltage VGS, the wordline bias voltages VW 1 ˜VWJ are applied to the drain selection line DSL, the source selection line SSL, and the wordlines WL 1 ˜WLJ, respectively. The drain selection transistors DST of the memory cell block MB 1  are turned off in response to the drain selection line voltage VGD, so that the memory cells MC 1 ˜MCJ of each of the cell strings STe 1 ˜STen and STo 1 ˜STon are isolated from the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon. And, as the source selection transistors SST of the memory cell block MB 1  are turned on in response to the source selection line voltage VGS, the memory cells MC 1 ˜MCJ of each of the cell strings STe 1 ˜STen and STo 1 ˜STon are connected to the common source line CSL 1 . The wordline bias voltages VW 1 ˜VWJ are applied to the gates of the memory cells MC 1 ˜MCJ of each of the cell strings STe 1 ˜STen and STo 1 ˜STon. Meanwhile, the block selection circuits  106  isolates the drain selection line DSL, the source selection line SSL, and the wordlines WL 1 ˜WLJ from the global drain selection line GDSL, the global source selection line GSSL, and the global wordlines GWL 1 ˜GWLJ. 
   The first voltage selection circuit  107  selects the first common source voltage VCS 1  of the ground voltage level in response to the pre-program control signal PRPGM, and applies the first common source voltage VCS 1  to the global source line GCSL connected to the common source line CSL 1 . Referring to  FIG. 3 , the first selection signal generator  121  enables the selection signal SEL 11  and disables the selection signal SEL 12 , in response to the pre-program control signal PRPGM. As a result, the switch SW 11  is turned on to supply the first common source voltage VCS 1  to the global source line GCSL and the switch SW 12  is turned off. Thus, the first common source voltage VCS 1  of the ground voltage level is applied to the common source line CSL 1 . 
   The second voltage selection circuit  108  selects the first voltage VP 1 , which has the ground voltage level, or a positive voltage level lower than the power source voltage VCC, in response to the pre-program control signal PRPGM, and applies the first voltage VP 1  to the bitline control circuits BLC  1 ˜BLCn of the bitline selection circuit  109  as the control voltage VIRPWR. 
   The selection control circuit  123  of the bitline selection circuit  109  enable all the bitline control signals DCHe 1 ˜DCHen and DCHo 1 ˜DCHon but disable all the bitline selection signals BSLe 1 ˜BSLen and BSLo 1 ˜BSLon, in response to the pre-program control signal PRPGM. The bitline control circuits BLC 1 ˜BLCn supply the control voltage VIRPWR to the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon in response to the bitline control signals DCHe 1 ˜DCHen and DCHo 1 ˜DCHon. As a result, the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon are precharged to the control voltage VIRPWR. And, responding to the bitline selection signals BSLe 1 ˜BSLen and BSLo 1 ˜BSLon, the bitline selection circuits SL 1 ˜SLn isolate the bitlines BLe 1 ˜BLen and BLo 1 ˜BLon from the page buffer  110 . Thus, the memory cells MC 1 ˜MCJ of the memory cell block MB 1  are programmed at the same time, while the memory cells of the rest memory cell blocks MB 2 ˜MBK are prohibited from being programmed. 
     FIG. 4  illustrates the cell string STe 1  of the memory cell block MB 1 . Referring to  FIG. 4 , after forming an N-well  132  and an P-well  133  in a substrate  131 , a drain region  134 , a source region  135 , and pluralities of impurity regions  136  are formed in the P-well  133 . The drain region  134  is connected to the bitline BLe 1  through a drain contact  141 , and the source region  135  is connected to the common source line CSL 1 . Control gates  139  of the memory cells MC 1 ˜MCJ are connected to the wordline bias voltages VW 1 ˜VWJ of the voltage 15˜20V for the pre-program operation. The gate  137  of the drain selection transistor DST is coupled to the drain selection line DSL, and supplied with the drain selection line voltage VGD of the ground voltage level through the drain selection line DSL. Thus, the drain selection transistor DST is turned off. The gate  138  of the source selection transistor SST is connected to the source selection line SSL, supplied with the source selection line voltage VGS of the voltage 0.5˜10V through the source selection line SSL. Thus, the source selection transistor SST is turned on. As a result, by the source selection transistor SST, the first common source voltage VCS 1  of the ground voltage level applied to the common source line CS 1  is transferred to the memory cells MC 1 ˜MCJ. During this, the common source line CS 1  is connected only to the memory cell block MB 1 , not to all the memory cell blocks MB 1 ˜MBK. Comparative to this, the bitline BLe 1  is shared by the memory cell blocks MB 1 ˜MBK. Thus, the loading capacitance of the common source line CSL 1  is much lower than that of the bitline BLe 1 . From this reason, the common source line CSL 1  is able to be discharged to the ground voltage level faster than the bitline BLe 1 . And, since the common source line CSL 1  does not cross the wordlines W 11 ˜WLJ, the common source line CSL can be quickly discharged to the ground voltage level without affecting the wordline bias voltages VW 1 ˜VWJ. But, during the pre-program operation, the ground voltage may not be quickly transferred to the memory cells MC 1 ˜MCJ due to the large loading capacitance of the bitline BLe 1  and the drain contact  141  when the ground voltage is transferred to the memory cells MC 1 ˜MCJ through the bitline BLe 1  and the drain contact  141 . Further, when the ground voltage is transferred to the memory cells MC 1 ˜MCJ through the bitline BLe 1 , the bitline BLe 1  is affected from the wordline bias voltages VW 1 ˜VWJ applied to the wordlines WL 1 ˜WLK fabricated under the bitline BLe 1 . As a result, it takes a longer time for discharging the bitline BLe 1  to the ground voltage level. Therefore, it is possible to reduce the pre-program time and current consumption in supplying the ground voltage to the memory cells MC 1 ˜MCJ through the bitline BLe 1  more than through the common source line CSL 1 . 
     FIG. 5  is a graphic diagram showing a distribution profile of threshold voltages of memory cells by the pre-program operation of the flash memory device according to the present invention. Referring to  FIG. 5 , the curve A plots the distribution profile of the threshold voltage V TH  of the memory cells before the pre-program operation, being in the range Vt 1 ˜Vt 2 . The curve B plots the distribution profile of the threshold voltage V TH  of the memory cells after the pre-program operation, being in the range Vt 3 ˜Vt 4 . The voltage range Vt 3 ˜Vt 4  is an ideal range capable of preventing the threshold voltages of the memory cells from being lowered excessively when the memory cells are being erased. As illustrated by the broken arrow, the threshold voltages of the memory cells of the memory cell block to be erased by the pre-program operation in the flash memory device  100  are distributed within the ideal voltage range. 
   The present invention shortens a pre-program time and reduces current consumption by separating bitlines from memory cells and applying program bias voltages through the common source line 
   Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitution, modifications and changes may be thereto without departing from the scope and spirit of the invention.