Abstract:
In pattern synchronization for correctly regenerating received data, which is performed in an optical receiver for receiving an optical signal that has been subjected to quadrature phase modulation, signal conduction is quickly established without using duplicate combinations of bit shifting and pattern changing. A control method that does not involve verifying the duplicate combinations generated in modulation formats and pattern synchronization search orders. Specifically, a signal check circuit ( 40 ) performs data verification of data multiplexed by a MUX circuit ( 38 ) for multiplexing two data strings, and a bit shift pattern change control circuit ( 41 ) controls a bit shift circuit ( 36 ) and a pattern changing circuit ( 37 ) based on a result of the data verification and detects a correct combination of correct regenerated data to establish the signal conduction. At this time, for the bit shift circuit ( 36 ) and the pattern changing circuit ( 37 ), the duplicate combinations are not verified.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority from Japanese application JP 2011-013717 filed on Jan. 26, 2011, the content of which is hereby incorporated by reference into this application. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an optical receiver used in optical communication, and more particularly, to an optical receiver capable of quickly establishing signal conduction in phase-modulated optical transmission. 
         [0004]    2. Description of the Related Art 
         [0005]    In recent years, in a wavelength multiplexing optical transmission system, in order to increase a transmission rate per channel while maintaining a wavelength interval between channels, it has been a challenge to increase a frequency utilization efficiency. Therefore, researches are being made to employ, instead of on-off keying (OOK) which have conventionally been used widely, a modulation format such as quadrature phase shift keying (QPSK) that provides narrow occupied bandwidth and high frequency utilization efficiency, for example. 
         [0006]    Further, in the field of optical transmission, from the viewpoints of easy demodulation and optical fiber transmission characteristics, a return-to-zero differential quadrature phase shift keying (RZ-DQPSK) modulation format in which the QPSK modulation signal is differentially encoded and then RZ encoded is expected to be employed widely, for example. 
         [0007]    As an example, in an optical receiver of the RZ-DQPSK modulation format, a delay interferometer (DLI) and a dual balanced receiver are used to add two quadrature phase components of received light waves with a delay of 1 time slot and then convert the added components to electric signals in two lanes that are proportional to amplitudes of the components for quadrature phase demodulation. Further, in order to regenerate one original data signal from the two electric signals, establishment of orthogonality of two lanes of the DLI and establishment of pattern matching (polarity inversion and lane swapping) of data signals associated with multilevel phase modulation of DQPSK are needed. Examples of the synchronization methods include methods disclosed in JP 2006-270909 A. 
       SUMMARY OF THE INVENTION 
       [0008]    Of the orthogonality and the pattern matching described above, in order to establish the pattern matching, it is necessary to multiplex data strings in two lanes back to one data string, and then to judge whether or not the content of the data string is correct. At this time, in order to multiplex the data strings in the two lanes in synchronized timing, the two electric signals regenerated by a demodulator need to be subjected to clock extraction, identification, and regeneration by using clock data recovery (CDR) circuits, and then to synchronization and multiplexing. At this time, the two electric signals are originally generated from one input signal and hence have the same data rate. However, phases of the electric signals are skewed and fluctuate due to disturbances that occur in the modulator/demodulator and a transmission line. In order to reduce the effects of the phase fluctuation on the transmission characteristics, it is necessary to subject the two electric signals once to the clock extraction, identification, and regeneration by the CDR circuits that operate independently of each other, and then to perform synchronization and multiplexing based on one of the clocks. 
         [0009]    At this time, the skew fluctuation between the two electric signals described above and the phase fluctuation of clock recovery circuits of the two CDR circuits can be absorbed by a synchronization circuit. However, in that case, the skew between the electric signals and the skew between the recovered clocks of the two CDR circuits at the time point when the synchronization is fixed lead to certain bit shifts in the two synchronized lanes and affect the arrangement of output data after multiplexing. Therefore, pattern matching needs to be set so that the bit shift between data lanes, the lane swapping, and the polarity inversion are performed while monitoring the polarity inversion and lane swapping described above as well as the contents of the multiplexed data strings, to thereby realize a combination that regenerates the correct data string. 
         [0010]    The bit shift amount is determined by performances of the modulator and the demodulator and configurations of the two CDR circuits, and also changes due to the fluctuations in the performances as well as configurations and variations in the operation environment. Therefore, depending on the conditions, the number of combinations that need to be verified is increased. Further, in a receiving circuit having a configuration in which data strings regenerated by the two CDR circuits are further parallelized, and then the synchronization and the pattern matching are performed, the bit shift accompanying the parallelization may also be generated, with the result that the number of combinations that need to be verified at the time of the pattern matching is further increased. 
         [0011]    As described above, in order to multiplex the data strings regenerated by at least two independent CDR circuits, to thereby quickly establish the conduction of the clock recovery signal, the important issue is to reduce the number of combinations that need to be verified for pattern matching that can regenerate the correct data string. 
         [0012]    It is an object of the present invention to provide an optical receiver capable of quickly establishing the signal conduction in a case where the signal conduction is to be establishedbymultiplexing at least two data strings regenerated from the optical signal that has been subjected to quadrature phase modulation. 
         [0013]    In order to solve the above-mentioned problem, it is necessary to omit combinations that provide the same effect on the arrangement and the polarity of the multiplexed data strings, of combinations of the bit shift, the lane swapping, and the polarity inversion in verifying the pattern matching, and to monitor whether the multiplexed data string is regenerated correctly. Therefore, in order to solve the above-mentioned problem, according to the present invention, there is provided an optical receiver for receiving an optical signal that has been subjected to quadrature phase modulation, including: at least two independent CDR circuits for extracting clock and identifying and regenerating data from a regenerated electric signal; a synchronization circuit for synchronizing outputs of the at least two independent CDR circuits; a bit shift circuit; a pattern changing circuit having a lane swapping function and a polarity inversion function; a multiplexing circuit for multiplexing at least two data strings; a signal check circuit for performing data verification of multiplexed data; and a bit shift pattern change control circuit having functions of controlling the bit shift circuit and the pattern changing circuit based on a result of the data verification, detecting a correct combination of correct regenerated data, and establishing signal conduction, wherein the bit shift pattern change control circuit controls so as to omit the data verification of overlapping data among the multiplexed data. 
         [0014]    As an example, at least two electric signals regenerated from the optical signal that has been subjected to the quadrature phase modulation are input to the at least two independent CDR circuits, respectively. The at least two of first data strings output from the at least two independent CDR circuits, respectively, are input to the synchronization circuit. The at least two of second data strings output from the synchronization circuit are input to a circuit including the bit shift circuit and the pattern changing circuit to perform bit shifting of data strings. The multiplexing circuit multiplexes the at least two of third data strings output via the circuit. The bit shift pattern change control circuit repeatedly changes control contents of the bit shift circuit and the pattern changing circuit until the result of the data verification becomes a predetermined result, and detects the correct combination of the correct regenerated data to establish the signal conduction. Specifically, when multiplexed data in a case where the bit shift circuit and the pattern changing circuit are controlled with a first control content and multiplexed data in a case where the bit shift circuit and the pattern changing circuit are controlled with a second control content are the same, the bit shift pattern change control circuit controls the bit shift circuit and the pattern changing circuit with one of the first control content and the second control content. 
         [0015]    Further, according to an aspect of the present invention, the bit shift pattern change control circuit may control so as to verify data which consist of the bit shift of the multiplexed data, the polarity inversion of the multiplexed data, and the bit shift and the polarity inversion of the multiplexed data. Further, according to an aspect of the present invention, the bit shift circuit may be provided in a preceding stage of the pattern changing circuit, and the bit shift pattern change control circuit may control so as to verify one of an odd number of bits and an even number of bits among the multiplexed data. As an example, the at least two independent CDR circuits include two CDR circuits. Two electric signals regenerated from the optical signal that has been subjected to the quadrature phase modulation are input to the two CDR circuits, respectively. Two of first data strings output from the two CDR circuits, respectively, are input to the synchronization circuit. Two of second data strings output from the synchronization circuit are input to a circuit including the bit shift circuit to perform bit shifting of one data string of the two of second data strings output from the synchronization circuit and the pattern changing circuit, respectively, The multiplexing circuit multiplexes two of third data strings output via the circuit. The bit shift pattern change control circuit controls the bit shift circuit to set a bit shift amount used in performing the bit shifting of the one data string to one of an even number of bits and an odd number of bits, and repeatedly changes control contents of the bit shift circuit and the pattern changing circuit until the result of the data verification becomes a predetermined result, and detects the correct combination of the correct regenerated data to establish the signal conduction. 
         [0016]    According to the present invention, it is possible to reduce the number of combinations of pattern matching that are needed when the at least two data strings, which are regenerated from the optical signal that has been subjected to quadrature phase modulation by using, for example, the DLI, the dual balanced receiver, and the at least two CDR circuits that operate independently of each other, are multiplexed to regenerate one original data string, to thereby quickly establish the signal conduction. 
         [0017]    The combinations that provide the same effect are determined by the signal modulation format. The combinations that provide the same effect change also depending on the order of the bit shifting, the lane swapping, and the polarity inversion, but the number of combinations which duplicate and need no verification is the same for the maximum range of bit shift which is verified for the pattern matching. Further, the same effects may be obtained in the optical receiver for regenerating, in the optical communication not only of the RZ-DQPSK modulation format described above but also of a modulation format using the quadrature phase modulation such as QPSK, the electric signals using the at least two CDR circuits that operate independently of each other. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    In the accompanying drawings: 
           [0019]      FIG. 1  is a block diagram illustrating a configuration of an optical receiver according to the present invention; 
           [0020]      FIG. 2  is a diagram illustrating an example of an I data string and a Q data string; 
           [0021]      FIG. 3A  is a diagram illustrating changes of the I data string and the Q data string; 
           [0022]      FIG. 3B  is a diagram illustrating changes of the I data string and the Q data string; 
           [0023]      FIG. 3C  is a diagram illustrating changes of the I data string and the Q data string; 
           [0024]      FIG. 3D  is a diagram illustrating changes of the I data string and the Q data string; 
           [0025]      FIG. 4A  is a diagram illustrating changes of the I data string and the Q data string; 
           [0026]      FIG. 4B  is a diagram illustrating changes of the I data string and the Q data string; 
           [0027]      FIG. 4C  is a diagram illustrating changes of the I data string and the Q data string; 
           [0028]      FIG. 4D  is a diagram illustrating changes of the I data string and the Q data string; and 
           [0029]      FIG. 4E  is a diagram illustrating changes of the I data string and the Q data string. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0030]    Hereinafter, an embodiment of the present invention is described with reference to the accompanying drawings. The embodiment described below uses the RZ-DQPSK format. 
         [0031]      FIG. 1  is a diagram illustrating an example of a configuration according to the embodiment of the present invention, and is a block diagram illustrating a configuration of an optical receiver  3  according to the embodiment of the present invention. On an optical transmitter  1  side, an input signal  10  is converted by a modulator  11  into an RZ-DQPSK optical signal, and the RZ-DQPSK optical signal is input through a transmission line  2  to a demodulator  30  of the optical receiver  3 . Specifically, the modulator  11 , which is an RZ-DQPSK modulator, performs RZ-DQPSK modulation to convert the input signal  10  into the RZ-DQPSK optical signal, and the RZ-DQPSK optical signal is input through the transmission line  2  to the demodulator  30 . In the demodulator  30 , the RZ-DQPSK optical signal is subjected to quadrature phase demodulation to be converted to electric signals in two lanes. Specifically, in the demodulator  30 , the RZ-DQPSK optical signal is converted to an electric signal in an I lane  33  and an electric signal in a Q lane  34 . The two electric signals in the I lane  33  and the Q lane  34  are input to two clock data recovery circuits  31  and  32  (hereinafter, referred to as CDR circuits  31  and  32 ) that operate independently of each other, respectively, to be regenerated as two data strings. A synchronizing circuit  35  absorbs any skew so that the two data strings become two synchronized parallel data strings (I data string and Q data string to be described later). Thereafter, the two synchronized parallel data strings pass through a bit shift circuit  36  and a pattern changing circuit  37  (polarity inversion and lane swapping) and are restored as one data string  39  by a MUX circuit  38 . The bit shift circuit  36  performs bit shifting of at least one parallel data string in accordance with an instruction from a bit shift pattern change control circuit  41  to be described later. In this embodiment, the bit shift circuit  36  performs bit shifting of a parallel data string of the Q lane. Further, the pattern changing circuit  37  subjects at least one of the parallel data strings to the polarity inversion and the lane swapping in accordance with an instruction from the bit shift pattern change control circuit  41 . 
         [0032]    The restored data string  39  is monitored by a signal check circuit  40  so as to be correctly restored as the original input signal  10  to the transmission side. When the data string is regenerated with a wrong combination of bit shifting and pattern changing, the data string is passed through the bit shift pattern change control circuit  41  so that the bit shifting and the pattern changing are controlled to be changed to another combination, and the regenerated data is verified. The pattern changing is repeated until the regenerated data output finally regenerates the input signal data correctly. Specifically, the signal check circuit  40  repeatedly performs data verification of the restored data string  39  so that the restored data string  39  is restored as the input signal  10 . Then, the bit shift pattern change control circuit  41  repeatedly changes the content of the bit shifting and the content of the pattern changing until an affirmative data verification result is obtained. Specifically, the bit shift pattern change control circuit  41  repeatedly changes the control contents of the bit shift circuit  36  and the pattern changing circuit  37  until the signal conduction is established. 
         [0033]    At this time, the bit shift pattern change control circuit  41  omits combinations that provide the same effect on the arrangement and the polarity of the data string after being multiplexed by the MUX circuit  38 , and gives combinations of the bit shifting and the pattern changing. Specifically, the bit shift pattern change control circuit  41  uses, when there are a plurality of control contents of the bit shift circuit  36  and the pattern changing circuit  37  with which the data array of the restored data string  39  becomes a certain data array, only one control content of the plurality of control contents is used. In other words, when the data string  39  obtained by controlling the bit shift circuit  36  and the pattern changing circuit  37  with a certain control content and the data string  39  obtained by controlling the bit shift circuit  36  and the pattern changing circuit  37  with another control content are the same, the bit shift pattern change control circuit  41  does not perform control of the bit shift circuit  36  and the pattern changing circuit  37  with one of the control contents. This way, the combination that regenerates the correct data string may be found faster, and the signal conduction may be quickly established. 
         [0034]    Note that, in this figure, the verification of the data pattern is performed after the MUX circuit  38 . However, the multiplexing by the MUX circuit  38  may not be performed and corresponding pattern verification may be performed after multiplexing two data strings. 
         [0035]    The maximum value of the bit shifting necessary for finding the combination that regenerates the correct data string is determined by the modulation format, the demodulation format, and the amount of skews generated in the modulator, the demodulator, and the CDR circuits. When the two independent CDR circuits  31  and  32  illustrated in this figure are used, the maximum value is about ±2 bits. Changes of the I data string and the Q data string (see  FIG. 2 ) due to the bit shifting and the pattern changing in this case are illustrated in  FIGS. 3A to 3D , which are used to describe the same patterns and the pattern checking method. The numerals in the patterns of the figures indicate the arrangement of the input data string. The symbol “inv” after the numerals indicates polarity inversion of the data. 
         [0036]    Table A 1  of  FIG. 3A  shows the Q data string and the I data string when the Q data string is shifted by −2 bits, Table A 2  of  FIG. 3A  shows the Q data string and the I data string when the Q data string is shifted by −2 bits and then the polarity of the I data string is inverted, Table A 3  of  FIG. 3A  shows the Q data string and the I data string when the Q data string is shifted by −2 bits and then the polarity of the Q data string is inverted, and Table A 4  of  FIG. 3A  shows the Q data string and the I data string when the Q data string is shifted by −2 bits and then the polarities of both the data strings are inverted. In addition, Table a 1  of  FIG. 3A  shows the Q data string and the I data string when the lane swapping is further performed in the case shown in Table A 1  of  FIG. 3A , Table a 2  of  FIG. 3A  shows the Q data string and the I data string when the lane swapping is further performed in the case shown in Table A 2  of  FIG. 3A , Table a 3  of  FIG. 3A  shows the Q data string and the I data string when the lane swapping is further performed in the case shown in Table A 3  of  FIG. 3A , and Table a 4  of  FIG. 3A  shows the Q data string and the I data string when the lane swapping is further performed in the case shown in Table A 4  of  FIG. 3A . 
         [0037]    Further, Table B 1  of  FIG. 3A  and Table B 1  of  FIG. 3B  show the Q data string and the I data string when the Q data string is shifted by −1 bit, Table B 2  of  FIG. 3A  and Table B 2  of  FIG. 3B  show the Q data string and the I data string when the Q data string is shifted by −1 bit and then the polarity of the I data string is inverted, Table B 3  of  FIG. 3A  and Table B 3  of  FIG. 3B  show the Q data string and the I data string when the Q data string is shifted by −1 bit and then the polarity of the Q data string is inverted, and Table B 4  of  FIG. 3A  and Table B 4  of  FIG. 3B  show the Q data string and the I data string when the Q data string is shifted by −1 bit and then the polarities of both the data strings are inverted. In addition, Table b 1  of  FIG. 3A  and Table b 1  of  FIG. 3B  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table B 1  of  FIG. 3A  and Table B 1  of  FIG. 3B , Table b 2  of  FIG. 3A  and Table b 2  of  FIG. 3B  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table B 2  of  FIG. 3A  and Table B 2  of  FIG. 3B , Table b 3  of  FIG. 3A  and Table b 3  of  FIG. 3B  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table B 3  of  FIG. 3A  and Table B 3  of  FIG. 3B , and Table b 4  of  FIG. 3A  and Table b 4  of  FIG. 3B  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table B 4  of  FIG. 3A  and Table B 4  of  FIG. 3B . 
         [0038]    Further, Table C 1  of  FIG. 3B  and Table C 1  of  FIG. 3C  show the Q data string and the I data string when the Q data string is shifted by 0 bits, Table C 2  of  FIG. 3B  and Table C 2  of  FIG. 3C  show the Q data string and the I data string when the polarity of the I data string is inverted, Table C 3  of  FIG. 3B  and Table C 3  of  FIG. 3C  show the Q data string and the I data string when the polarity of the Q data string is inverted, and Table C 4  of  FIG. 3B  and Table C 4  of  FIG. 3C  show the Q data string and the I data string when the polarities of both the data strings are inverted. In addition, Table c 1  of  FIG. 3B  and Table c 1  of  FIG. 3C  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table C 1  of  FIG. 3B  and Table C 1  of  FIG. 3C , Table c 2  of  FIG. 3B  and Table c 2  of  FIG. 3C  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table C 2  of  FIG. 3B  and Table C 2  of  FIG. 3C , Table c 3  of  FIG. 3B  and Table c 3  of  FIG. 3C  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table C 3  of  FIG. 3B  and Table C 3  of  FIG. 3C , and Table c 4  of  FIG. 3B  and Table c 4  of  FIG. 3C  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table C 4  of  FIG. 3B  and Table C 4  of  FIG. 3C . 
         [0039]    Further, Table D 1  of  FIG. 3C  and Table D 1  of  FIG. 3D  show the Q data string and the I data string when the Q data string is shifted by +1 bit, Table D 2  of  FIG. 3C  and Table D 2  of  FIG. 3D  show the Q data string and the I data string when the Q data string is shifted by +1 bit and then the polarity of the I data string is inverted, Table D 3  of  FIG. 3C  and Table D 3  of  FIG. 3D  show the Q data string and the I data string when the Q data string is shifted by +1 bit and then the polarity of the Q data string is inverted, and Table D 4  of  FIG. 3C  and Table D 4  of  FIG. 3D  show the Q data string and the I data string when the Q data string is shifted by +1 bit and then the polarities of both the data strings are inverted. In addition, Table d 1  of  FIG. 3C  and Table d 1  of  FIG. 3D  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table D 1  of  FIG. 3C  and Table D 1  of  FIG. 3D , Table d 2  of  FIG. 3C  and Table d 2  of  FIG. 3D  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table D 2  of  FIG. 3C  and Table D 2  of  FIG. 3D , Table d 3  of  FIG. 3C  and Table d 3  of  FIG. 3D  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table D 3  of  FIG. 3C  and Table D 3  of  FIG. 3D , and Table d 4  of  FIG. 3C  and Table d 4  of  FIG. 3D  show the Q data string and the I data string when the lane swapping is further performed in the case shown in Table D 4  of  FIG. 3C  and Table D 4  of  FIG. 3D . 
         [0040]    Table E 1  of  FIG. 3D  shows the Q data string and the I data string when the Q data string is shifted by +2 bits, Table E 2  of  FIG. 3D  shows the Q data string and the I data string when the Q data string is shifted by +2 bits and then the polarity of the I data string is inverted, Table E 3  of  FIG. 3D  shows the Q data string and the I data string when the Q data string is shifted by +2 bits and then the polarity of the Q data string is inverted, and Table E 4  of  FIG. 3D  shows the Q data string and the I data string when the Q data string is shifted by +2 bits and then the polarities of both the data strings are inverted. In addition, Table e 1  of  FIG. 3D  shows the Q data string and the I data string when the lane swapping is further performed in the case shown in Table E 1  of  FIG. 3D , Table e 2  of  FIG. 3D  shows the Q data string and the I data string when the lane swapping is further performed in the case shown in Table E 2  of  FIG. 3D , Table e 3  of  FIG. 3D  shows the Q data string and the I data string when the lane swapping is further performed in the case shown in Table E 3  of  FIG. 3D , and Table e 4  of  FIG. 3D  shows the Q data string and the I data string when the lane swapping is further performed in the case shown in Table E 4  of  FIG. 3D . 
         [0041]      FIGS. 3A to 3E  illustrate cases where pattern changing is performed in the order of the bit shifting, the polarity inversion, and the lane swapping. As apparent from the figures, the lane swapping results in the same data string as the data string obtained when the Q lane is shifted by −1 bit. Therefore, the data pattern obtained by shifting ±1 bit overlap the data obtained without shifting or by shifting ±2 bits, and hence the pattern checking may be omitted. To the contrary, when the lane swapping is omitted and bit shifting is performed by 0 bits, ±1 bit, and ±2 bits, it is also possible to omit the pattern checking and quickly verify the combination of the bit shifting and the pattern changing that correctly regenerates the data string. 
         [0042]    For example, both in the case of Table A 2  of  FIG. 3A  and in the case of Table b 2  of  FIG. 3A , when the I data string and the Q data string are multiplexed, the data array becomes “4, 1inv, 6, 3inv, 8, 5inv, 10, 7inv”. Therefore, both in the case where the bit shift circuit  36  and the pattern changing circuit  37  are controlled with the control content that “the Q data string is shifted by −2 bits and the polarity of the I data string is inverted” and in the case where the bit shift circuit  36  and the pattern changing circuit  37  are controlled with the control content that “the Q data string is shifted by −1 bit, the polarity of the I data string is inverted, and the lane swapping is performed”, the same data string is obtained after the multiplexing. Therefore, the bit shift pattern change control circuit  41  controls the bit shift circuit  36  and the pattern changing circuit  37  with only one of the control contents. In the case of this embodiment, the bit shift pattern change control circuit  41  performs bit shifting so that the bit shift amount is an even number of bits. Therefore, the bit shift pattern change control circuit  41  controls the bit shift circuit  36  and the pattern changing circuit  37  with the control content that “the Q data string is shifted by −2 bits and the polarity of the I data string is inverted”, but does not control the bit shift circuit  36  and the pattern changing circuit  37  with the control content that “the Q data string is shifted by −1 bit, the polarity of the I data string is inverted, and the lane swapping is performed”. Note that, the bit shift pattern change control circuit  41  may perform bit shifting so that the bit shift amount is an odd number of bits instead of an even number of bits. 
         [0043]    Also, for example, both in the case of Table B 2  of  FIG. 3B  and in the case of Table c 2  of  FIG. 3B , when the I data string and the Q data string are multiplexed, the data array becomes “2, 1inv, 4, 3inv, 6, 5inv, 8, 7inv, 10, 9inv”. Therefore, the bit shift pattern change control circuit  41  controls the bit shift circuit  36  and the pattern changing circuit  37  with the control content that “the polarity of the I data string is inverted and the lane swapping is performed”, but does not control the bit shift circuit  36  and the pattern changing circuit  37  with the control content that “the Q data string is shifted by −1 bit and the polarity of the I data string is inverted”. Further, for example, both in the case of Table C 2  of  FIG. 3C  and in the case of Table d 2  of  FIG. 3C , when the I data string and the Q data string are multiplexed, the data array becomes “1inv, 2, 3inv, 4, 5inv, 6, 7inv, 8, 9inv, 10”. Therefore, the bit shift pattern change control circuit  41  controls the bit shift circuit  36  and the pattern changing circuit  37  with the control content that “the polarity of the I data string is inverted”, but does not control the bit shift circuit  36  and the pattern changing circuit  37  with the control content that “the Q data string is shifted by +1 bit, the polarity of the I data string is inverted, and the lane swapping is performed”. Also, for example, both in the case of Table D 2  of  FIG. 3D  and in the case of Table e 2  of  FIG. 3D , when the I data string and the Q data string are multiplexed, the data array becomes “3inv, 2, 5inv, 4, 7inv, 6, 9inv, 8”. Therefore, the bit shift pattern change control circuit  41  controls the bit shift circuit  36  and the pattern changing circuit  37  with the control content that “the Q data string is shifted by +2 bits, the polarity of the I data string is inverted, and the lane swapping is performed”, but does not control the bit shift circuit  36  and the pattern changing circuit  37  with the control content that “the Q data string is shifted by +1 bit and the polarity of the I data string is inverted”. 
         [0044]    Hereinabove, referring to  FIGS. 1 ,  2 , and  3 A to  3 D, there has been exemplified the checking method in the case where the pattern changing is performed in the order of the bit shifting, the polarity inversion, and the lane swapping. When the order is changed, the combinations of overlapping control contents change, but the number of the combinations is the same.  FIGS. 4A to 4E  illustrate arrangements and polarities of the two data strings in the I and Q lanes when the pattern changing is performed in the order of the polarity inversion, the lane swapping, and the bit shifting, in the manner similar to  FIGS. 3A to 3D . 
         [0045]    Table a 1  of  FIG. 4A  shows the I data string and the Q data string when the lane swapping is performed and then the Q data string is shifted by −2 bits, Table a 2  of  FIG. 4A  shows the I data string and the Q data string when the lane swapping is performed, and then the polarity of the Q data string is inverted and the Q data string is shifted by −2 bits, Table a 3  of  FIG. 4A  shows the I data string and the Q data string when the lane swapping is performed, and then the polarity of the I data string is inverted and the Q data string is shifted by −2 bits, and Table a 4  of  FIG. 4A  shows the I data string and the Q data string when the lane swapping is performed, and then the polarities of both the data strings are inverted and the Q data string is shifted by −2 bits. Table A 1  of  FIG. 4A  shows the I data string and the Q data string when the Q data string is shifted by −2 bits, Table A 2  of  FIG. 4A  shows the I data string and the Q data string when the polarity of the I data string is inverted and then the Q data string is shifted by −2 bits, Table A 3  of  FIG. 4A  shows the I data string and the Q data string when the polarity of the Q data string is inverted and then the Q data string is shifted by −2 bits, and Table A 4  of  FIG. 4A  shows the I data string and the Q data string when the polarities of both the data strings are inverted and then the Q data string is shifted by −2 bits. 
         [0046]    Table b 1  of  FIG. 4B  shows the I data string and the Q data string when the lane swapping is performed and then the Q data string is shifted by −1 bit, Table b 2  of  FIG. 4B  shows the I data string and the Q data string when the lane swapping is performed, and then the polarity of the Q data string is inverted and the Q data string is shifted by −1 bit, Table b 3  of  FIG. 4B  shows the I data string and the Q data string when the lane swapping is performed, and then the polarity of the I data string is inverted and the Q data string is shifted by −1 bit, and Table b 4  of  FIG. 4B  shows the I data string and the Q data string when the lane swapping is performed, and then the polarities of both the data strings are inverted and the Q data string is shifted by −1 bit. Table B 1  of  FIG. 4B  shows the I data string and the Q data string when the Q data string is shifted by −1 bit, Table B 2  of  FIG. 4B  shows the I data string and the Q data string when the polarity of the I data string is inverted and then the Q data string is shifted by −1 bit, Table B 3  of  FIG. 4B  shows the I data string and the Q data string when the polarity of the Q data string is inverted and then the Q data string is shifted by −1 bit, and Table B 4  of  FIG. 4B  shows the I data string and the Q data string when the polarities of both the data strings are inverted and then the Q data string is shifted by −1 bit. 
         [0047]    Table c 1  of  FIG. 4C  shows the I data string and the Q data string when the lane swapping is performed, Table c 2  of  FIG. 4C  shows the I data string and the Q data string when the lane swapping is performed and then the polarity of the Q data string is inverted, Table c 3  of  FIG. 4C  shows the I data string and the Q data string when the lane swapping is performed and then the polarity of the I data string is inverted, and Table c 4  of  FIG. 4C  shows the I data string and the Q data string when the lane swapping is performed and then the polarities of both the data strings are inverted. Table C 1  of  FIG. 4C  shows the I data string and the Q data string when the Q data string is shifted by 0 bits, Table C 2  of  FIG. 4C  shows the I data string and the Q data string when the polarity of the I data string is inverted, Table C 3  of  FIG. 4C  shows the I data string and the Q data string when the polarity of the Q data string is inverted, and Table C 4  of  FIG. 4C  shows the I data string and the Q data string when the polarities of both the data strings are inverted. 
         [0048]    Table d 1  of  FIG. 4D  shows the I data string and the Q data string when the lane swapping is performed and then the Q data string is shifted by +1 bit, Table d 2  of  FIG. 4D  shows the I data string and the Q data string when the lane swapping is performed, and then the polarity of the Q data string is inverted and the Q data string is shifted by +1 bit, Table d 3  of  FIG. 4D  shows the I data string and the Q data string when the lane swapping is performed, and then the polarity of the I data string is inverted and the Q data string is shifted by +1 bit, and Table d 4  of  FIG. 4D  shows the I data string and the Q data string when the lane swapping is performed, and then the polarities of both the data strings are inverted and the Q data string is shifted by +1 bit. Table D 1  of  FIG. 4D  shows the I data string and the Q data string when the Q data string is shifted by +1 bit, Table D 2  of  FIG. 4D  shows the I data string and the Q data string when the polarity of the I data string is inverted and then the Q data string is shifted by +1 bit, Table D 3  of  FIG. 4D  shows the I data string and the Q data string when the polarity of the Q data string is inverted and then the Q data string is shifted by +1 bit, and Table D 4  of  FIG. 4D  shows the I data string and the Q data string when the polarities of both the data strings are inverted and then the Q data string is shifted by +1 bit. Table e 1  of  FIG. 4E  shows the I data string and the Q data string when the lane swapping is performed and then the Q data string is shifted by +2 bits, Table e 2  of  FIG. 4E  shows the I data string and the Q data string when the lane swapping is performed, and then the polarity of the Q data string is inverted and the Q data string is shifted by +2 bits, Table e 3  of  FIG. 4E  shows the I data string and the Q data string when the lane swapping is performed, and then the polarity of the I data string is inverted and the Q data string is shifted by +2 bits, and Table e 4  of  FIG. 4E  shows the I data string and the Q data string when the lane swapping is performed, and then the polarities of both the data strings are inverted and the Q data string is shifted by +2 bits. Table E 1  of  FIG. 4E  shows the I data string and the Q data string when the Q data string is shifted by +2 bits, Table E 2  of  FIG. 4E  shows the I data string and the Q data string when the polarity of the I data string is inverted and then the Q data string is shifted by +2 bits, Table E 3  of  FIG. 4E  shows the I data string and the Q data string when the polarity of the Q data string is inverted and then the Q data string is shifted by +2 bits, and Table E 4  of  FIG. 4E  shows the I data string and the Q data string when the polarities of both the data strings are inverted and then the Q data string is shifted by +2 bits. 
         [0049]    In this case, bit shifting to the negative side has overlapping patterns (control contents) in no bit shifting and bit shifting in the positive side. Specifically, the data string obtained when the I data string and the Q data string are multiplexed is the same for the case of Table A 1  of  FIG. 4A  and the case of Table d 1  of  FIG. 4D , for the case of Table A 2  of  FIG. 4A  and the case of Table d 2  of  FIG. 4D , for the case of Table A 3  of  FIG. 4A  and the case of Table d 3  of  FIG. 4D , for the case of Table A 4  of  FIG. 4A  and the case of Table d 4  of  FIG. 4D , for the case of Table a 1  of  FIG. 4A  and the case of Table D 1  of  FIG. 4D , for the case of Table a 2  of  FIG. 4A  and the case of Table D 2  of  FIG. 4D , for the case of Table a 3  of  FIG. 4A  and the case of Table D 3  of  FIG. 4D , and for the case of Table a 4  of  FIG. 4A  and the case of Table D 4  of FIG.  4 D. Similarly, the data string obtained when the I data string and the Q data string are multiplexed is the same for the case of Table B 1  of  FIG. 4B  and the case of Table c 1  of  FIG. 4C , for the case of Table B 2  of  FIG. 4B  and the case of Table c 2  of  FIG. 4C , for the case of Table B 3  of  FIG. 4B  and the case of Table c 3  of  FIG. 4C , for the case of Table B 4  of  FIG. 4B  and the case of Table c 4  of  FIG. 4C , for the case of Table b 1  of  FIG. 4B  and the case of Table C 1  of  FIG. 4C , for the case of Table b 2  of  FIG. 4B  and the case of Table C 2  of  FIG. 4C , for the case of Table b 3  of  FIG. 4B  and the case of Table C 3  of  FIG. 4C , and for the case of Table b 4  of  FIG. 4B  and the case of Table C 4  of  FIG. 4C . Therefore, verification of the bit shifting on the side of the bit shifting on the negative side becomes unnecessary. In this case also, the number of combinations of omittable patterns (control contents) when the verification is performed to a certain bit shift value is the same. 
         [0050]    Note that, embodiments of the present invention are not limited to the embodiment described above. For example, the present invention is applicable not only to the case where the signal conduction is to be established in the optical receiver including the two CDR circuits, but also to a case where the signal conduction is to be established in an optical receiver including at least two CDR circuits. Specifically, the present invention is applicable not only to the case where the signal conduction is to be established by multiplexing the two data strings regenerated by the two CDR circuits, but also to a case where the signal conduction is to be established by multiplexing at least two data strings regenerated by at least two CDR circuits. 
         [0051]    While there have been described what are at present considered to be certain embodiments of the invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claims cover all such modifications as fall within the true spirit and scope of the invention.