Abstract:
An SOI device, and a method for producing the SOI device, for use in an SRAM memory having enhanced stability. The SRAM is formed with a wider W and a fully-depleted FET. The wider FET is extended by an expitaxial silicon sidewall, and the performance of the FET is improved.

Description:
FIELD OF THE INVENTION  
       [0001]     The invention relates to MOSFET device structures, and in particular to SRAM devices employing Silicon-On-Insulator technology.  
       BACKGROUND OF THE INVENTION  
       [0002]     Silicon-On-Insulator (SOI) technology has been investigated for SRAM chips for several years. Advantages of the technology include simplified layout, avoidance of latch-up, reduced leakage currents and junction capacitances, and thus faster speeds and lower power consumption. For memories, the reduction of the junction capacitance lowers the bitline capacitance, which is a major limiting factor in memory performance.  
         [0003]     SOI for SRAMs has been investigated in both fully-depleted and partially-depleted processes. The fully-depleted process is more difficult to perform but has certain desired circuit behaviors, including less history dependence and less parasitic bipolar currents. A fully-depleted device has an ultrathin silicon film used such that the depletion layer extends through the entirety of the film, eliminating the floating-body effect and providing superior short-channel behavior.  
       SUMMARY OF THE INVENTION  
       [0004]     In one aspect, the invention is related to a method for producing an SOI device for use in an SRAM memory having enhanced stability over that found in the prior art. The SRAM is formed with a wider W and a fully-depleted FET. The wider FET is extended by an expitaxial sidewall, and the performance of the FET is improved. In another aspect, the invention is related to a product produced by the above method. Advantages will be apparent from the description that follows, including the figures. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]      FIG. 1  shows an SOI system on which may be built an SRAM according to an embodiment of the invention.  
         [0006]      FIG. 2  shows the system of  FIG. 1  on which has been deposited a silicon oxide layer, a polysilicon layer, and a resist feature according to an embodiment of the invention.  
         [0007]      FIG. 3  shows the system of  FIG. 2  in which certain of the polysilicon has been removed, and in which more resist has been applied according to an embodiment of the invention.  
         [0008]      FIG. 4  shows the system of  FIG. 3  in which certain areas of the resist have been stripped and a layer of silicon nitride deposited according to an embodiment of the invention.  
         [0009]      FIG. 5  shows results of shallow trench patterning for the logic area, as well as deposition over the SRAM cell area according to an embodiment of the invention.  
         [0010]      FIG. 6  shows results of a silicon oxide deposition over the logic area according to an embodiment of the invention.  
         [0011]      FIG. 7  shows results of a silicon oxide etch back according to an embodiment of the invention.  
         [0012]      FIG. 7A  shows a perspective view of a device according to the embodiment of  FIG. 7 , showing the (perpendicular) views along which the two center devices in the logic area are taken.  
         [0013]      FIG. 8  shows results of a silicon oxide removal according to an embodiment of the invention.  
         [0014]      FIG. 8A  shows a perspective view of a device according to the embodiment of  FIG. 8 , showing the (perpendicular) views along which the two center devices in the logic area are taken.  
         [0015]      FIG. 9  shows results of a silicon reactive ion etching (RIE) step according to an embodiment of the invention.  
         [0016]      FIG. 9A  shows a perspective view of a device according to the embodiment of  FIG. 9 , showing the (perpendicular) views along which the two center devices in the logic area are taken.  
         [0017]      FIG. 10  shows results of a silicon nitride fill according to an embodiment of the invention.  
         [0018]      FIG. 11  shows results of a silicon nitride chemical-mechanical-polishing (CMP) step according to an embodiment of the invention.  
         [0019]      FIG. 12  shows results of polysilicon and silicon oxide removal steps according to an embodiment of the invention.  
         [0020]      FIG. 13  shows results of a silicon epitaxial growth and CMP, as well as silicon nitride removal, according to an embodiment of the invention.  
         [0021]      FIG. 13A  shows a perspective view of a device according to the embodiment of  FIG. 13 , showing the (perpendicular) views along which the two center devices in the logic area are taken.  
         [0022]      FIG. 14  shows results of MOSFET gate formation according to an embodiment of the invention.  
         [0023]      FIG. 14A  shows a perspective view of a device according to the embodiment of  FIG. 14 , showing the (perpendicular) views along which the two center devices in the logic area are taken.  
         [0024]      FIG. 15  shows results of MOSFET contact formation according to an embodiment of the invention.  
         [0025]      FIG. 16  shows the finished product.  
         [0026]      FIG. 16A  shows a perspective view of a device according to the embodiment of  FIG. 16 , showing the (perpendicular) views along which the two center devices in the logic area are taken. 
     
    
       [0027]     Note that in all figures, like shading represents like elemental composition or like compounds. Not all elements have reference numerals, for clarity.  
       DETAILED DESCRIPTION  
       [0028]      FIG. 1  shows an SOI system on which may be built devices according to an embodiment of the invention. In particular, a silicon substrate  26  is provided with a buried oxide layer  24 , and a silicon thin film  22  is present above the buried oxide layer  24 . The silicon thin film  22  is typically less than about 50 nm thick. The thickness of the buried oxide layer  24  may range from about 100 nm to about 200 nm.  
         [0029]     The buried oxide layer  24  may be formed in various ways, including via converting the silicon to a silicon oxide (SiO 2 ) using a heavy oxygen implant. Following this, an epitaxial layer may be grown on top of the oxide. In another technique, bonding of different wafers may also be employed. Another technique is via direct deposition on the substrate followed by a recrystallization process to create the silicon thin film  22 .  
         [0030]     Referring to  FIG. 2 , the system of  FIG. 1  is shown on which has been deposited a silicon oxide layer  36 , a polysilicon layer  28 , and a resist feature  30 . The silicon oxide layer  36  has a thickness typically in the range from about 5 nm to about 20 nm. The polysilicon layer  28  has a thickness typically in the range from about 150 nm to about 300 nm. The resist feature  30  begins the process of patterning of the polysilicon layer in the SRAM cell area  20 .  
         [0031]     The silicon oxide layer  36  may be deposited in a number of ways, including via TEOS sources or various types of deposition or thermal growth technologies, including vapor deposition, CVD, etc. The polysilicon layer  28  may be deposited in a number of ways, including via silane processes, LPCVD, etc. The resist feature  30  is applied via known processes.  
         [0032]      FIG. 3  shows the system of  FIG. 2  in which most of the polysilicon layer  28  has been removed via etching, and in which more resist  29  has been applied. The polysilicon layer  28  may be etched via, e.g., plasma etching or reactive ion etching (RIE), as well as via other techniques. The resist feature  29  is applied via known processes, and in this step the same is applied over most of the logic area. Due to the presence of resist feature  30 , polysilicon feature  32  remains following the etching step.  
         [0033]      FIG. 4  shows the system of  FIG. 3  in which certain areas of the resist have been stripped and a layer of silicon nitride deposited. In particular, a step of shallow-trench silicon RIE has been performed at the SRAM area, followed by stripping of the resist  29  and deposition of a silicon nitride layer  34 . In particular, shallow trench patterning has been applied in the SRAM cell area at locations indicated by trench  37 . The silicon nitride layer may be deposited via APCVD, LPCVD, PECVD, etc.  
         [0034]      FIG. 5  shows results of shallow trench patterning for the logic area, as well as deposition over the SRAM cell area. In particular, a layer of resist  38  is applied and patterned over the top of the SiN layer  34 . The resist may be applied and patterned via known processes.  
         [0035]      FIG. 6  shows results of a silicon nitride RIE and a silicon oxide deposition over the logic area. In particular, a step of silicon nitride RIE is performed to remove silicon nitride not under the resist. Then, a layer of silicon oxide  40  is deposited over the resulting structure. The thickness of the silicon oxide layer  40  may be from about 50 nm to about 150 nm.  
         [0036]     The silicon nitride layer  34  may be etched by RIE or by other techniques as desired. The silicon oxide layer  40  may be deposited in a number of ways, including via TEOS sources or various types of deposition, including vapor deposition, CVD, etc.  
         [0037]      FIG. 7  shows results of a silicon oxide etch back. In particular, the figure shows that silicon nitride layer  34  has been etched back in certain areas. This etch back may be performed via a SiO2 RIE method. Following the etch back, a layer of resist  42  is applied and patterned in known manner. The SiO2 layer  40  remains only on the sidewall of SiN layer  34 . This sidewall may be located beneath the channel.  
         [0038]      FIG. 7A  shows a perspective view of certain of the devices in the logic area. In particular, it shows two perpendicular views, one each of the two center devices. The view along the length is shown by the leftmost of the center two devices; the cross-sectional view by the rightmost of the center two devices. There are physically at least two such devices in the logic area, but for clarity the two representative and equivalent devices are employed to show the longitudinal and cross-sectional views. It is noted here that the same description applies to  FIGS. 8A, 9A ,  13 A,  14 A, and  16 A.  
         [0039]      FIG. 8  shows results of a silicon oxide removal step. The resist layer  42  protects the silicon oxide of the leftmost of the center two devices, and so this silicon oxide layer remains. However, the remainder of the silicon oxide has been removed. Following this step, the resist  42  is stripped away.  
         [0040]     The removal of the silicon oxide may be performed via an oxide RIE method. Wet techniques may also be used but are more difficult due to the small design.  
         [0041]      FIG. 9  shows results of a silicon reactive ion-etching (RIE) step. In particular, a silicon RIE step is employed to remove the silicon layer  22  as it appears between the devices. As a result, a portion of the buried oxide layer  24  is exposed. As such, the RIE should be anisotropic such that the sidewall of layer  40  is not attacked.  
         [0042]      FIG. 10  shows results of a silicon nitride fill. In particular, a thick layer of silicon nitride  35  is deposited over the logic area and SRAM cell area. The silicon nitride layer  35  may be deposited via APCVD, PECVD, etc. The thickness of the silicon nitride layer may be between about 300 nm and 70 nm.  
         [0043]      FIG. 11  shows results of a silicon nitride chemical-mechanical-polishing (CMP) step. This process flattens the wafer surface and in this case removes much of the silicon nitride layer  35 . In some cases, an etch back technique may be employed to replace the CMP procedure.  
         [0044]      FIG. 12  shows results of polysilicon and silicon oxide removal steps. In particular, the polysilicon layer  32  has been removed, and the silicon oxide layer  40  has also been removed.  
         [0045]     The polysilicon layer  32  may be removed by, e.g., RIE or wet etching. The silicon oxide layer  40  may also be removed by wet etching, such as by a BOE solution. Systems of HF+HNO3+H2O may be employed for removal of the polysilicon layer. Systems of HF+H2O or NH4OH+HF+H2O may be employed for removal of the SiO layer.  
         [0046]      FIG. 13  shows results of a silicon epitaxial growth and CMP, as well as silicon nitride removal. In particular, silicon epitaxial growth is employed to grow the silicon layer  21 . A further step of CMP may then be employed to smooth the wafer top to a planar surface. Finally, the silicon nitride layers  34  and  35  may be removed. Typically, silicon nitride layers may be removed via wet or dry etching.  
         [0047]      FIG. 14  shows results of MOSFET gate formation. In particular, the gate electrode  42  may be deposited via appropriate masking over the device of  FIG. 13 . The gate may be of known type, including metal, doped polysilicon, policide, etc. Such gate electrodes are typically deposited in known manner, and typically as thermal oxides. As may be seen, a layer of silicon oxide  39  is formed over certain areas of the surface prior to the gate electrode deposition. The silicon oxide layer  39  may be deposited in a number of ways, including via TEOS sources or various types of deposition, including vapor deposition, CVD, etc. It should be noted that if the gate dielectric is a high-K material, CVD may also be employed to deposit the gate oxide.  
         [0048]      FIG. 15  shows results of MOSFET contact formation. In particular, a spacer layer  46  is deposited in certain areas using appropriate masking. The spacer layer  46  may be formed by CVD, and is generally SiO2 or SiN or both. A silicide layer  44  is then deposited in certain areas via appropriate masking. Silicide deposition is typically performed via PVD (sputtering).  
         [0049]      FIG. 16  shows the finished product. In achieving this finished product, contacts  50  and layer  48  are made via an appropriate contact masking process as is known. Layer  48  is typically Si02, and a CVD method may be used to deposit the same. The contacts  50  may be a W/TiN system, where the TiN is deposited via CVD or PVD and the W by CVD.  
         [0050]     The invention has been described with respect to certain embodiments. However, the invention is not to be limited to those embodiments described; rather, the invention is limited solely by the claims appended hereto, and equivalents thereof.