Abstract:
A decoding method for low density generator matrix codes is disclosed, which decodes a bit information sequence that is transmitted after encoding with LDGC, the method comprises: S 1 : filling L−K known bits in a received code word sequence R and deleting code word symbols erased by a channel in R, and getting R e ; S 2 : deleting rows corresponding to the code word symbols erased by a channel from a transposed matrix G ldgct  of an LDGC generator matrix, and getting G e ; S 3 : obtaining I t  according to relation G e ×I t =R e ; S 4 : obtaining s t  according to relation G ldgct (0:L−1,0:L−1)×I t =s t , and getting an original information sequence of K bits by deleting the filled L−K known bits from s t . The present disclosure can significantly reduce the storage overhead of a decoder, accelerate the decoding speed, and allow LDGC to be more smartly used in high speed communication systems.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This patent application is a U.S. national phase application of International Patent Application No. PCT/CN2008/072684, filed Oct. 14, 2008, which claims priority to China Patent Application No. 200810096993.1, filed May 14, 2008, each of which is hereby incorporated by reference herein in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to the field of data encoding and decoding, and particularly to a decoding method and device for low density generator matrix codes. 
       BACKGROUND 
       [0003]    A purpose of channel encoding is to ensure reliable transmission of information, the complexity of implementation of a channel encoding scheme mainly lies at a decoding end, and a decoder is typically a critical part of the channel encoding scheme. A decoder can be either implemented using hardware, i.e. using hardware logic units to construct the decoder; or implemented using software, i.e. using a general processor (CPU) to implement the decoder through programs; a decoder can also be implemented using an implementation method combining software and hardware. 
         [0004]    Low Density Generator Matrix Codes (LDGC) generally mean: their generator matrix is a sparse binary matrix (i.e. matrix elements are comprised of 0 and 1 alone) of Class I codes, including structured LDGC and non-structured LDGC such as Raptor codes, etc. 
         [0005]    The LDGC is suitable for performing forward error correction (FEC) to an erasure channel. During a data transmission process, if a data packet received at a receiving end has any check error, an erroneous data segment is discarded, which is equivalent to performing erasing. LDGC can effectively countermine loss of data. 
         [0006]    Also, LDGC is a kind of linear block code, all elements in its generator matrix (encoding matrix) come from a two element field (GF(2) field), i.e. the elements in the generator matrix are comprised of 0 and 1 alone; and its nonzero elements are typically sparse, i.e. the number of “1”s in the matrix only accounts for a very small percentage in the total number of elements in the matrix; moreover, LDGC is also a kind of system code, i.e. a first K bits of code words generated by encoding K-bit information bits by using an LDGC generator matrix are the same as the information bits. All calculations involved during the LDGC encoding/decoding process are calculations in the GF(2) field. 
         [0007]    A generator matrix of structured LDGC also has other characteristics, and can be obtained by expanding and modifying a very small basic matrix; in particular, a square matrix to which its first L rows correspond is generally an upper triangular or lower triangular matrix. While a generator matrix of LDGC that do not have any structured feature such as Raptor codes is a random binary matrix. Gldgc will be used below for collectively indicating an LDGC generator matrix, when it is necessary to indicate LDGC generator matrices separately, G struct  will be used for indicating a transposition of a generator matrix of structured LDGC, G random  will be used for indicating a transposition of a generator matrix of LDGC that do not have any structured feature (the matrix can be referred to as a non-structured LDGC generator matrix), and in particular G random  will include a generator matrix of Raptor codes. 
         [0008]    In the following statements, any “vector” or “matrix” with a subscript of a small letter t will all indicate a transposition of an original “vector” or “matrix”, such vector or matrix and its transposition look exactly the same in their contents, and sometimes can indicate the same object. For example, G ldgct  is defined as a transposition of G ldgc , I t  as a transposition of I, and R t  as a transposition of R, because either I or R is a row vector, herein both I t  and R t  are column vectors; in the following, G struct  and G random  will be used respectively to indicate their separate generator matrix G ldgct  after transposition. 
         [0009]      FIG. 1  is a schematic illustration of G ldgct , which is an LDGC generator matrix after transposition. As shown in  FIG. 1   a , a square matrix to which a first L rows in a structured LDGC generator matrix G struct  correspond is generally an upper triangular or lower triangular matrix. As shown in  FIG. 1   b , a square matrix to which a first L rows of Raptor codes correspond is a random matrix, which does not have the characteristics of an upper triangular or lower triangular matrix. Wherein x and y in the figure may be 0. 
         [0010]    The encoding with LDGC involves first obtaining intermediate variables by using a corresponding relationship between information bits (i.e. data to be sent) and intermediate variables in system codes, and then obtaining after-encoding code words by multiplying the intermediate variables with a generator matrix. Specifically speaking, an encoding process involves first generating a sequence s of L bits by filling d=L−K known bits in an original information sequence m of K bits, then obtaining an intermediate variable sequence I of L bits by solving a system of equations according to the relation of the system of equations: I×G ldgc (0: L−1, 0: L−1)=s, then obtaining a code word sequence C′ ldgc  of N+d bits (containing d filled bits) by multiplying the intermediate variables with a generator matrix, i.e. I×G ldgc (0: L−1, 0: N+d−1), the d filled bits in C′ ldgc  do not need to be transmitted, therefore what is really transmitted is a code word sequence C ldgc  of N bits. After C ldgc  passed through a channel (may be erased), a code word sequence received at a receiving end is R. Wherein s is a vector of 1×L; I is a vector of 1×L; R is a vector of 1×N, and its transposition R is a vector of N×1; G ldgc (0: L−1, 0: L−1) is an L×L square matrix, which is generally an upper triangular or lower triangular matrix, and G ldgc (0: L−1, 0: N+d−1) is an L×(N+d) matrix. For the detailed process of encoding, please refer to the patent “An encoding method and device, a decoding method and device for low density generator matrix code”. 
         [0011]      FIG. 2  is a flowchart of a decoding method for low density generator matrix codes. As shown in  FIG. 2 , the decoding process includes the following steps: 
         [0012]      201 : obtaining R e  by filling a known bit sequence of the length of d=L−K in the corresponding positions of a received code word sequence R t , such as 1, 1, . . . , 1, and by deleting code word symbols erased by a channel; 
         [0013]    wherein K is the length of original information bits, and L is the encoded length of the original information bits after filling. 
         [0014]      202 : obtaining an erasure generator matrix G e  by performing row erasing (deleting) processing to G ldgct  according to how the received code word sequence R t  has been erased. 
         [0015]      FIG. 3  is a schematic illustration of performing erasing processing to the generator matrix according to how the received code word sequence R t  has been erased. As shown in  FIG. 3 , the first L rows of the generator matrix G e  after erasing processing no longer represent a lower triangular square matrix. 
         [0016]    Assuming that X T  symbols: {r i , r j , . . . , r p  . . . r x } in R=(r 0 , r 1 , . . . r N+d−1 ) T  after filling a known bit sequence has been erased by a channel; wherein X L  symbols {r i , r j , . . . , r p } in the first L symbols have been erased by a channel; then Xset={i, j, . . . , p, . . . , x}; Xset L ={i, j, . . . p}. G e  is simply obtained by erasing the {i, j, . . . , p, . . . , x}-th rows in G ldgct  accordingly, and now because several rows have been erased, the matrix in G e  is no longer exactly diagonalized, as shown in  FIG. 3(   c ). 
         [0017]      203 : obtaining an intermediate variable I t  by solving a system of equations G e ×I t =R e ; 
         [0018]      204 : obtaining s t  according to the relation of the system of equations G ldgct (0:L−1,0:L−1)×I t =s t , and obtaining an original information sequence m of K bits by deleting the filled d known bits from s t , thereby completing LDGC decoding. 
         [0019]    During the above-mentioned decoding process, the most critical step is obtaining the intermediate variable I t , and this would typically require solving a large scale system of binary linear equations. As far as engineering is concerned, methods such as Gauss elimination or iteration can be used for solving a system of linear equations; according to the characteristics of LDGC, the Gauss elimination method is more suitable for LDGC decoding. Therefore, the speed of the Gauss elimination process will directly affect the speed of LDGC decoding. 
         [0020]    During the process of obtaining the intermediate variable I t  according to the relation of a system of equations G ldgct (0: N+d−1,0: L−1)×I t =R t  (G ldgct  is written as G e  and R t  is written as R e  when there is channel erasure, and the above-mentioned relation of a system of equations is G e ×I t =R e ), the ongoing Gauss elimination has to perform three kinds of elementary transformations to G ldgct  (written as G e  when there is channel erasure), i.e. “row permutation, row addition and column permutation”. According to the principles of linear algebra, in order to ensure the correctness of the system of equations, while performing elementary transformation to G ldgct  (G e ), it is necessary to perform the following corresponding processing to I t  and R t  (or R e  when there is channel erasure): 
         [0021]    1) row permutation, if the i-th row and the j-th row of G ldgct  (G e ) are permuted, the i-th bit and the j-th bit of R t  (R e ) need to be permuted; 
         [0022]    2) row addition, if the i-th row and the j-th row of G ldgct  (G e ) are added, the i-th bit and the j-th bit of R t  (R e ) need to be added (addition modulo 2); 
         [0023]    3) column permutation, if the i-th column and the j-th column of G ldgct  (G e ) are permuted, the i-th bit and the j-th bit of I t  need to be permuted. 
         [0024]    Because the final result required is to get I t , while the elements in I t  have been permuted correspondingly during column permutation of G ldgct  (G e ), it is necessary to record how the I t  has been permuted to make it easier for the subsequent inverse permutation process. As far as engineering is concerned, how the I t  has been permuted can be recorded through an array. However, R is not the data ultimately desired, so it can be processed directly, and it is not necessary to record how it has been processed. 
         [0025]    Because these transformation relationships are strictly corresponding to each other, and the complexity of Gauss elimination is mainly reflected in the processing of G ldgct  (G e ), for easy descriptions below, for any elementary transformation against G ldgct  (G e ), the corresponding processing to I t  and R t  (R e ) has to be performed in strict accordance with the above-mentioned three situations. In order to focus on key points, the description of processing to I t  and R t  (R e ) may be simplified below sometimes. 
         [0026]    Generally, the complexity (amount of calculation) in the implementation of Gauss elimination is mainly reflected in the “row addition” operation of the matrix. Because all elements of G ldgct  come from the GF(2) field, the addition operation of two rows in G ldgct  (G e ) is the “addition modulo 2” operation, for example, 
         [0027]    row_i, which is the contents of the i-th row, is: (1,0,0,0,0,1,0,1); 
         [0028]    row_j, which is the contents of the j-th row, is: (1,1,0,0,0,1,1,1); 
         [0029]    If an operation that uses row_i to eliminate row_j happens during Gauss elimination process, this is equivalent to: 
         [0000]      row 13    j =row —   i +row —   j =(1,0,0,0,0,1,0,1)+(1,1,0,0,0,1,1,1)=(0,1,0,0,0,0,1,0); 
         [0030]    herein “+” means addition (addition modulo 2) in the GF(2) field; 
         [0031]    It is seen from the above-example that because all elements in G ldgct  come from the GF(2) field, that is the value of an element can only be either 0 or 1, if these 0 and 1 elements are stored directly, that is each bit element occupies one storage unit or occupies one processor word (which is generally 32 bits), when the code length is large, G ldgct  (G e ) would require a very big storage space; moreover, the row addition operation is very time-consuming because it has to perform addition modulo 2 to each element, respectively. 
       SUMMARY 
       [0032]    The technical problem that the present disclosure intends to resolve is providing a decoding method and device for low density generator matrix codes, which can overcome disadvantages of the prior art, reduce storage space occupied by the LDGC generator matrix, and increase operation speed. 
         [0033]    In order to solve the above-mentioned problem, the present disclosure provides a decoding method for low density generator matrix codes, which decodes received a bit information sequence that is transmitted after encoding with LDGC, and the method comprises: 
         [0034]    S 1 : filling L−K known bits in a received code word sequence R and deleting code word symbols erased by a channel in R, and getting R e ; 
         [0035]    S 2 : deleting rows corresponding to the code word symbols erased by a channel from a transposed matrix G ldgct  of an LDGC generator matrix, and getting G e ; wherein using WNum processing words to sequentially store all or part of same-position matrix elements of each row in G e , and each processing word is used for storing WWid matrix elements of G e ; 
         [0036]    S 3 : obtaining I t  according to relation G e ×I t =R e ; 
         [0037]    S 4 : obtaining s t  according to relation G ldgct (0:L−1,0:L−1)×I t =s t , and getting an original information sequence of K bits by deleting the filled L−K known bits from s t ; 
         [0038]    the G ldgct  is a GF(2) field matrix of N+L−K rows and L columns, WWid is the word width of the processing word, WNum=ceil(P/WWid), and P is the number of matrix elements of each row in G e  that are stored by using one bit of the processing word. 
         [0039]    Moreover, in step S 3 , I t  may be obtained by using Gauss elimination method; and during the Gauss elimination process, for the matrix elements of each row in G e  that are stored by using one bit of the processing word, row addition of corresponding rows may be accomplished by performing XOR operation to the processing words corresponding to two rows in G e . 
         [0040]    Moreover, a square matrix corresponding to the first L rows in G ldgct  may be a lower triangular matrix; 
         [0041]    step S 3  may include the following substeps: 
         [0042]    S 31 : generating 
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         [0000]    by performing column permutation to G e , wherein A is an M-order lower triangular matrix, and recording corresponding relationship of column permutation between G e  and G a ; 
         [0043]    S 32 : obtaining I t ′ according to relation G a ×I t ′=R e , and getting I t  by performing inverse permutation to I t ′ according to the corresponding relationship of column permutation; 
         [0044]    wherein P is column number of matrices C and B, the processing words are used for sequentially storing all matrix elements of each row in C and B, and each bit of each processing word is used for sequentially storing WWid matrix elements of C and B. 
         [0045]    Moreover, M=L−X L , where X L  is the number of bits erased by a channel in the first L code word symbols of R; and P=X L . 
         [0046]    Moreover, assuming that Xset L  is a set of serial numbers of erased code word symbols in the first L code word symbols of R after filling L−K known bits, and the number of serial numbers in the set is X L ; 
         [0047]    in step S 31 , columns of G e  whose column serial numbers fall within Xset L  are moved to the rightmost side of G e , and subsequent columns whose column serial numbers do not fall within Xset L  are sequentially filled in vacated positions of corresponding columns, and G a  is obtained. 
         [0048]    The present disclosure also provides a decoding device for low density generator matrix codes, which comprises: a filling and erasing unit, a Gauss elimination unit, and an information sequence generating unit, wherein 
         [0049]    the filling and erasing unit, is used for generating and outputting R e  by filling L−K known bits in a received code word sequence R and by deleting code word symbols erased by a channel; and for generating and outputting G e  by deleting rows corresponding to the code word symbols erased by a channel from a transposed matrix G ldgct  of an LDGC generator matrix; wherein WNum processing words are used for sequentially storing all or part of same-position matrix elements of each row in G e , and each processing word stores WWid matrix elements of G e ; 
         [0050]    the Gauss elimination unit, is used for obtaining and outputting I t  by performing Gauss elimination to G e  according to relation G e ×I t =R e ; 
         [0051]    the information sequence generating unit, is used for receiving the I t  outputted by the Gauss elimination unit; obtaining s t  according to relation G ldgct (0:L−1,0:L−1)×I t =s t , and outputting an original information sequence of K bits after deleting L−K known bits from s t ; 
         [0052]    the G ldgct  is a GF(2) field matrix of N+L−K rows and L columns, WWid is the word width of the processing word, WNum=ceil(P/WWid), and P is the number of matrix elements of each row in G e  that are stored by using one bit of the processing word. 
         [0053]    Moreover, the Gauss elimination unit may obtain the I t  by using Gauss elimination method; and during the Gauss elimination process, for the matrix elements of each row in G e  that are stored by using one bit of the processing word, may accomplish row addition of corresponding rows by performing XOR operation to the processing words corresponding to two rows in G e . 
         [0054]    Moreover, a square matrix corresponding to the first L rows in G ldgct  may be a lower triangular matrix; 
         [0055]    the device may further comprise a column permutation unit, which is used for generating 
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         [0000]    by performing column permutation to G e  outputted by the filling and erasing unit, wherein A is an M-order lower triangular matrix, and for outputting information on corresponding relationship of column permutation between G e  and G a ; 
         [0056]    the Gauss elimination unit may obtain I t ′ according to relation G a ×I t ′=R e , and may obtain and output I t  by performing inverse permutation to I t ′ according to the information on the corresponding relationship of column permutation outputted by the column permutation unit; 
         [0057]    wherein, P is column number of matrices C and B, the processing words are used for sequentially storing all matrix elements of each row in C and B, and each bit of each processing word is used for sequentially storing WWid matrix elements of C and B. 
         [0058]    Moreover, M=L−X L , where X L  is the number of bits erased by a channel in the first L code word symbols of R; and P=X L . 
         [0059]    Moreover, assuming that Xset L  may be a set of serial numbers of erased code word symbols in the first L code word symbols of R after filling L−K known bits, and the number of serial numbers in the set is X L ; 
         [0060]    the column permutation unit moves columns of G e  whose column serial numbers fall within Xset L  to the rightmost side of G e , and sequentially fills subsequent columns whose column serial numbers do not fall within Xset L  in vacated positions of corresponding columns, and obtains G a . 
         [0061]    The LDGC decoding method of the present disclosure can fully use the characteristics of the LDGC generator matrix and the characteristics of the processor in its ability to process multiple bits in parallel, and utilize one “word” (referred to as a processing word) of the processor to store and represent elements whose number is “processor word width” in the decoding LDGC generator matrix; compared to those storage structures and data representation methods in which the elements of an LDGC generator matrix are directly stored, the present disclosure can significantly reduce the storage overhead of a decoder, accelerate the decoding speed, and allow LDGC to be more smartly used in high speed communication systems. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0062]      FIG. 1  is a schematic illustration of G ldgct  which is an LDGC generator matrix after transposition; 
           [0063]      FIG. 2  is a flowchart of a decoding method for low density generator matrix codes; 
           [0064]      FIG. 3  is a schematic illustration of performing erasing processing to the generator matrix according to how the received code word sequence R has been erased; 
           [0065]      FIG. 4  is a flowchart of a decoding method for low density generator matrix codes according to the first embodiment of the present disclosure; 
           [0066]      FIG. 5  is a flowchart of a decoding method for low density generator matrix codes according to the second embodiment of the present disclosure; 
           [0067]      FIG. 6  is a schematic illustration of performing column permutation to the erasure generator matrix G e ; 
           [0068]      FIG. 7  is a schematic illustration of a decoding device for low density generator matrix codes according to an embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0069]    It is known from the above that because the matrix elements of the LDGC generator matrix (including G struct  and G random ) are comprised of 0 and 1 alone, and the row addition operation involved in Gauss elimination is addition modulo 2, it is practical to use only one bit to store and represent a matrix element and use XOR (i.e. bitwise XOR) to replace addition modulo 2 of each matrix element, thereby quickly implementing row addition operations of the LDGC generator matrix. 
         [0070]    For example, 
         [0071]    representing row_i, which is the contents of the i-th row as: 10000101; 
         [0072]    representing row_j, which is the contents of the j-th row as: 11000111; 
         [0073]    the addition of the contents of the i-th row and that of the j-th row can be equivalent to: 
         [0000]      row_j=row_i ⊕ row_j=10000101 ⊕ 011000111=01000010; 
         [0074]    where the “ ⊕ ” mentioned above means XOR operation. 
         [0075]    The present disclosure is described in detail below according to the attached drawings and embodiments; it should be noted that the present disclosure only addresses the decoder implementation method based on software or a combination of software and hardware. 
         [0076]      FIG. 4  is a flowchart of a decoding method for low density generator matrix codes according to the first embodiment of the present disclosure; this embodiment addresses a general purpose decoding method for structured and non-structured LDGC generator matrices (G struct  and G random ). As shown in  FIG. 4 , the method includes the following steps: 
         [0077]      401 : obtaining R e  by filling a known bit sequence of the length of d=L−K in the corresponding positions of a received code word sequence R, and by deleting code word symbols erased by a channel; 
         [0078]    wherein K is the length of original information bits, and L is the encoded length of the original information bits after filling. 
         [0079]    Assuming that X T  symbols: {r i , r j , . . . , r p  . . . r x } in R t =(r 0 , r 1 , . . . , r N+d−1 ) T  after filling a known bit sequence has been erased by a channel; wherein X L  symbols {r i , r j , . . . , r p } in the first L symbols have been erased by a channel; then Xset={i, j, . . . , p, . . . , x}; Xset L ={i, j, . . . p}. 
         [0080]      402 : obtaining an erasure generator matrix G e  by performing row erasing (deleting) processing to G ldgct  according to how the received code word sequence R t  has been erased; wherein each row of G e  is represented by using WNum processor words (referred to as processing word), of course, each row of G ldgct  can also be represented by using WNum processor words; 
         [0081]    assuming Xset={i, j, . . . , p, . . . , x}; Xset L ={i, j, . . . p}, obtaining G e  by erasing the {i, j, . . . , p, . . . , x}-th rows in G ldgct  accordingly. 
         [0082]    Because each row of G e (G ldgct ) contains L elements, WNum=ceil(L/WWid); WWid is the processor word width (which generally is 8, 16, 32, 64, in the unit of bit); i.e. using one processing word to sequentially store and represent WWid consecutive elements in G e  (G ldgct ); 
         [0083]    when L is not an integral multiple of WWid, the last processing word of each row contains the last mod(L,WWid) elements of that row, and the rest Z=WWid-mod(L,WWid) bits of that processing word can be cleared; 
         [0084]    the ceil means rounding-up operation, and mod means modulo operation. 
         [0085]    Ultimately, G e  (G ldgct ) can be represented by using a two-dimensional array, and each element in the two-dimensional array is a processing word. The total number of elements of the two-dimensional array is: (N+d−X t )×WNum; where X T  is the number of rows erased. It is therefore known that the above-mentioned matrix representation method of the present disclosure can be used for saving a lot of storage space. 
         [0086]    For example, when the processor word width WWid=32, each row of G e  (G ldgct ) contains L=2000 elements, therefore ceil(2000/32)=63 processing words are needed to represent each row of G e  (G ldgct ); because 2000 is not an integral multiple of 32, mod(2000,32)=16, the last processing word only has 16 significant bits, the rest 32−16=16 bits of the processing word are insignificant, and they can be cleared. 
         [0087]      403 : obtaining an intermediate variable I t  by solving a system of equations G e ×I t =R e ; 
         [0088]    during the process of obtaining the intermediate variable I t  by using the Gauss elimination method, the “row addition” operation involved is accomplished by using the XOR instructions of the processor; therefore a complete row addition operation can be replaced by an XOR operation of WNum processing words, which is equivalent to perform row addition operation in parallel with a degree of parallelism of WWid, thereby dramatically increasing the operation speed of “row addition” operation. 
         [0089]      404 : obtaining s t  according to the relation of the system of equations G ldgct (0:L−1,0:L−1)×I t =s t , and obtaining an original information sequence m of K bits by deleting the filled d known bits from s t , thereby completing LDGC decoding. 
         [0090]      FIG. 5  is a flowchart of a decoding method for low density generator matrix codes according to the second embodiment of the present disclosure; this embodiment is a decoding method for a structured LDGC generator matrix (G struct ), and can use processing words alone to store part of elements of each row in G struct  after the processing of erasure and column permutation. As shown in  FIG. 5 , the method includes the following steps: 
         [0091]      501 : obtaining R e  by filling a known bit sequence of the length of d=L−K in the corresponding positions of a received code word sequence R t , and by deleting code word symbols erased by a channel; 
         [0092]    wherein K is the length of original information bits, and L is the encoded length of the original information bits after filling. 
         [0093]    Assuming that X T  symbols: {r i , r j , . . . , r p  . . . r x } in R t =(r 0 , r 1 , . . . r N+d−1 ) T  after filling a known bit sequence has been erased by a channel; wherein X L  symbols {r i , r j , . . . r p } in the first L symbols have been erased by a channel; then Xset={i, j, . . . , p, . . . , x}; Xset L ={i, j, . . . p}. 
         [0094]      502 : obtaining an erasure generator matrix G e  by performing row erasing (deleting) processing to G ldgct  according to how the received code word sequence R t  has been erased; 
         [0095]    assuming Xset={i, j, . . . , p, . . . , x}; Xset L ={i, j, . . . p}, obtaining G e , by erasing the {i, j, . . . , p, . . . , x}-th rows in G ldgct  accordingly. 
         [0096]      503 : performing column permutation to the erasure generator matrix G e , making M-order square matrix with (0, 0) as its vertex in G e  to be a lower triangular matrix, and denoting the permuted matrix of G e  as permutation generator matrix G a ; also recording corresponding relationship of column permutation between G e  and G a , which is used for performing inverse operation to I t ′ that is generated by the corresponding permutation operation performed to I t  during the above-mentioned column permutation process. 
         [0097]      FIG. 6  is an schematic illustration of performing column permutation to the erasure generator matrix G e . 
         [0098]    Specifically, in order to obtain a lower triangular matrix, columns of G e  whose column serial numbers fall within Xset L  are moved to the rightmost side of G e , and subsequent columns whose column serial numbers do not fall within Xset L  are sequentially filled in vacated positions of corresponding columns, then the permutation generator matrix is obtained: 
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         [0099]    Wherein matrix A is an M-order square matrix, all elements on its diagonal line are nonzero elements, and it has the characteristic of a strictly lower triangular matrix; matrix C is a matrix of the size of M×(L−M); matrix D is a matrix of (N−K−(X T −X L ))×M; matrix B is a matrix of (N−K−(X T −X L ))×(L−M), where M=L−X L . 
         [0100]      504 : representing each row of B and C in G a  by using WNum processor words; 
         [0101]    because the length of each row of B and C is Xset L , assuming that the processor word width is WWid, then 
         [0000]        WNum=ceil ( Xset   L   /WWid ). 
         [0102]    If Xset L  is not an integral multiple of WWid, the last processing word of each row contains the last mod(Xset L ,WWid) elements of that row; and the rest Z=WWid-mod(Xset L , WWid) bits of that processing word can be cleared. 
         [0103]    Therefore, B and C can be represented by using a two-dimensional array, respectively, and each element in the two-dimensional array is a processing word. The total number of elements of the two-dimensional array corresponding to matrix C is: M×WNum; the total number of elements of the two-dimensional array corresponding to matrix B is: (N−K−(X T −X L ))×WNum. 
         [0104]    For example, the row length of B and C is Xset L =200; assuming that the processor word width WWid=32, then 
         [0105]    WNum=ceil(Xset L /WWid)=ceil(200/32)=7; i.e. each row of B and C needs to be stored and represented with 7 processing words. 
         [0106]    Because 200 is not an integral multiple of 32, mod(Xset L ,WWid)=mod(200,32)=8, the last processing word contains 8 significant bits, the rest 32−8=24 bits of the processing word are insignificant, and they can be cleared. 
         [0107]    Therefore, matrix C can be stored and represented by using a two-dimensional array with the total number of elements of M×7, and matrix B can be stored and represented by using a two-dimensional array with the total number of elements of (N−K−(X T −X L ))×7; compared to existing technologies where C is represented by using a two-dimensional array with the total number of elements of M×200, and B is represented by using a two-dimensional array with the total number of elements of (N−K−(X T −X L ))×200, a lot of storage space is saved. 
         [0108]    It should be noted that because the nonzero elements in matrices A and D can be obtained through direct calculation by using a formula defined by a constructive generator matrix during encoding, A and D actually do not need to be stored, and during the process of elimination performed to A and D, the positions of the nonzero elements can be obtained through direct calculation by using the formula defined by the constructive generator matrix during encoding, and then “row addition” is performed according to the positions of these nonzero elements. Of course, the same method can also be used for storing and representing A and D. While B and C can be seen as random sparse matrices, therefore for the row addition operation performed to them, it is only allowed to add corresponding elements one by one. Row addition capability of software processing can be optimized to the best level by using one processing word to represent data structure of WWid elements. 
         [0109]      505 : obtaining an intermediate variable I t ′ by solving a system of equations G a ×I t ′=R e ; and I t  can simply be obtained by performing inverse permutation according to the permutation relationship from I t  to I t ′ (i.e. the column permutation relationship from G e  to G a ). 
         [0110]    During the process of obtaining the intermediate variable I t  by using the Gauss elimination method, the “row addition” operation involving matrices B and C is accomplished by using the XOR instructions of the processor; therefore a complete row addition operation can be replaced by an XOR operation of WNum processing words, which is equivalent to perform row addition operation in parallel with a degree of parallelism of WWid, thereby dramatically increasing the operation speed of “row addition” operation. 
         [0111]      506 : obtaining s t  according to the relation of the system of equations G ldgct (0:L−1)×I t =s t , and obtaining an original information sequence m of K bits by deleting the filled d known bits from s t , thereby completing LDGC decoding. 
         [0112]      FIG. 7  is a schematic illustration of a decoding device for low density generator matrix codes according to an embodiment of the present disclosure. As shown in  FIG. 7 , the device comprises: a filling and erasing unit, a column permutation unit, a Gauss elimination unit, and an information sequence generating unit. 
         [0113]    The filling and erasing unit, is used for generating and outputting R e  by filling d=L−K known bits in a received code word sequence R and by deleting code word symbols erased by a channel; and for generating and outputting G e  by deleting rows corresponding to the code word symbols erased by a channel from a transposed matrix G ldgct  of an LDGC generator matrix; 
         [0114]    wherein for a structured and non-structured LDGC generator matrix, the filling and erasing unit uses WNum processing words to sequentially store all or part of matrix elements of each row in G e , each processing word stores WWid matrix elements of G e ; WWid is the word width of a processing word, and WNum=ceil(Len/WWid). Len is the number of elements in a row that need to be represented by using processing words. 
         [0115]    The column permutation unit, is used for performing column permutation to the G e  outputted by the filling and erasing unit, making M-order square matrix A with elements of the 0-th row and the 0-th column as its vertex in G e  to be a lower triangular matrix, generating and outputting 
         [0000]    
       
         
           
             
               
                 G 
                 a 
               
               = 
               
                 [ 
                 
                   
                     
                       A 
                     
                     
                       C 
                     
                   
                   
                     
                       D 
                     
                     
                       B 
                     
                   
                 
                 ] 
               
             
             , 
           
         
       
     
         [0000]    and outputting information on corresponding relationship of column permutation between G e  and G a ; 
         [0116]    M=L−X L , where X L  is the number of bits erased by a channel in the first L symbols of R. 
         [0117]    The column permutation unit can move columns of G e  whose column serial numbers fall within Xset L  to the rightmost side of G e , and sequentially fill subsequent columns whose column serial numbers do not fall within Xset L  in vacated positions of corresponding columns, then obtain G a . For a non-structured LDGC generator matrix, this unit is an optional unit. 
         [0118]    The Gauss elimination unit, is used for obtaining and outputting I t  by performing Gauss elimination to the G e  outputted by the filling and erasing unit according to the relation G e ×I t =R e ; or obtaining I t ′ by performing Gauss elimination to the G a  outputted by the column permutation unit according to the relation G a ×I t ′=R e , and obtaining and outputting I t  by performing inverse permutation to I t ′ according to the information on corresponding relationship of column permutation outputted by the column permutation unit. 
         [0119]    The information sequence generating unit, is used for receiving the I t  outputted by the Gauss elimination unit; obtaining s t  according to the relation G ldgct (0:L−1,0:L−1)×I t =s t , and outputting an original information sequence of K bits after deleting d known bits from s t . 
         [0120]    It is known from the above that for an LDGC generator matrix, the decoding method and device of the present disclosure can be used for accelerating processing speed of Gauss elimination. 
         [0121]    Based on the fundamental principle of the present disclosure, the above-mentioned embodiments can also have many types of variations: 
         [0122]    For an LDGC generator matrix of another shape, for example, when the first L rows form an upper triangular matrix, the decoding method of the present disclosure can be used after transforming it into a lower triangular matrix.