Abstract:
An output voltage adjustment circuit for buck circuits includes a microcontroller, first to eighth keys, and a display unit. The first to eighth keys input voltage adjustment signals to the microcontroller. A first input pin of the microcontroller is connected to a voltage output terminal. A second resistor is connected between the first input pin of the microcontroller and ground. A first to a sixth input/output pin of the microcontroller are connected to the display unit. A first to an eighth output pin of the microcontroller are connected to a pulse width modulation (PWM) controller. The first to eighth keys are selectively activated to provide voltage adjustment signals to the microcontroller, sampling output voltages of the voltage output terminal, comparing with a predetermined voltage, controlling the PWM controller to fine tune the duty cycle to output a stable voltage from the voltage output terminal. The display unit displays the voltages on the voltage output terminal.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a buck circuit, and particularly to an output voltage adjustment circuit for buck circuits. 
     2. Description of Related Art 
     Conventional buck circuits output voltages in response to the control of a PWM (pulse width modulation) controller, wherein the PWM controller is enabled by output control signals from a CPU disposed on a computer motherboard. However, the output voltages of conventional buck circuits are not stable when buck circuits need to output different stable voltages to perform tests during the design and testing of a computer motherboard. Consequently, conventional buck circuits cannot meet the needs of output voltages, and the CPU disposed on the motherboard is susceptible to damage during the testing process. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
         FIG. 1  is a circuit diagram of a buck circuit connected to an output voltage adjustment circuit for buck circuits of the present disclosure. 
         FIG. 2  is a circuit diagram of a preferred embodiment of an output voltage adjustment circuit for buck circuits of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     As shown in  FIG. 1  and  FIG. 2 , an output voltage adjustment circuit  100  for buck circuits of the present disclosure is utilized to adjust the output voltages of a buck circuit  200 . The buck circuit  200 , disposed on a circuit board (not shown) includes a PWM controller  20 , a PWM driving unit  21 , field effect transistors Q 1  and Q 2 , a voltage input terminal Vin and a voltage output terminal Vout. The PWM controller  20  is connected to the output voltage adjustment circuit  100 . The PWM driving unit  21  is connected to the PWM controller  20  and the gate of the field effect transistors Q 1  and Q 2  for receiving the control signals output by the PWM controller  20  and providing low potential driving signals and high potential driving signals to the field effect transistors Q 1  and Q 2  to turn the field effect transistors Q 1  and Q 2  on and off, respectively. The drain of the field effect transistors Q 2  is connected to the voltage input terminal Vin. The source of the field effect transistors Q 1  is connected to ground, and the drain of the field effect transistors Q 1  is connected to the source of the field effect transistors Q 2 . The node between the drain of the field effect transistors Q 1  and the source of the field effect transistor Q 2  is connected to one terminal of the inductance L and the other terminal of the inductor L is connected one terminal of a capacitor C 0 . The other terminal of the capacitor C 0  is grounded. The voltage output terminal Vout is connected between the inductance L and the capacitor C 0 , so as to output a driving voltage to other components and connect to the output voltage adjustment circuit  100 . 
     A preferred embodiment of the output voltage adjustment circuit  100  includes a microcontroller  10 , resistors R 4 -R 6 , capacitors C 1 -C 4 , a quartz oscillator X 1 , a key unit  30 , and a display unit  40 . The key unit  30  includes keys K 1 -K 12  and resistors R 1 -R 3 . The keys K 1 -K 12  are arranged in a 4 by 3 array, wherein the keys K 1 -K 8  are utilized to input voltage adjustment signals to the microcontroller  10 , the keys K 10 -K 12  are functional keys ‘enter’, ‘cancel’, and ‘start’, respectively. The key K 9  is idle. 
     An input pin RA 0  of the microcontroller  10  is connected to the voltage output terminal Vout of the buck circuit  200  through the resistor R 5 . The resistor R 6  is connected in series between the input pin RA 0  of the microcontroller  10  and ground. The clock pin OCS 1  of the micro controller  10  is connected to ground through a capacitor C 4 , and the clock pin OCS 2  thereof is connected to ground through a capacitor C 3 . The quartz oscillator X 1  is connected in series between the clock pins OCS 1  and OCS 2  of the microcontroller  10 . The input/output pins RC 2 -RC 7  of the microcontroller  10  are connected to the display unit  40 . The output pins RB 0 -RB 7  of the microcontroller  10  are connected to the PWM controller  20 . A voltage pin VCC of the microcontroller  10  is connected to a voltage source CV and one terminal of the resistor R 4 . The other terminal of the resistor R 4  is connected to one terminal of the capacitor C 2  and the other terminal of the capacitor C 2  is grounded. A voltage pin MP of the microcontroller  10  is connected to a node between the resistor R 1  and the capacitor C 2 . The capacitor C 1  is connected between the voltage pin VCC of the micro controller  10  and ground. An input pin RA 5  of the microcontroller  10  is connected to the voltage source VC through the resistor R 1 , an input pin RC 0  thereof is connected to the voltage source VC through the resistor R 2 , and an input pin RC 1  thereof is connected to the voltage source VC through the resistor R 3 . 
     First terminals of the keys K 1 , K 2 , and K 3  are connected to an input pin RA 1  of the microcontroller  10 . A second terminal of the key K 1  is connected to a node between the resistor R 1  and the input pin RA 5  of the microcontroller  10 . A second terminal of the key K 2  is connected to a node between the resistor R 2  and an input pin RC 0  of the microcontroller  10 . A second terminal of the third key K 3  is connected to a node between the resistor R 3  and the input pin RC 1  of the microcontroller  10 . First terminals of the keys K 4 , K 5  and K 6  are connected to an input pin RA 2  of the microcontroller  10 . A second terminal of the key K 4  is connected to a node between a second terminal of the key K 1  and the input pin RA 5  of the microcontroller  10 . A second terminal of the key K 5  is connected to a node between a second terminal of the key K 2  and an input pin RC 0  of the microcontroller  10 . A second terminal of the key K 6  is connected to a node between a second terminal of the key K 3  and the input key RC 1  of the microcontroller  10 . First terminals of the keys K 7 , K 8 , and K 9  are connected to an input pin RA 3  of the microcontroller  10 . A second terminal of the key K 7  is connected to a node between a second terminal of the key K 4  and an input pin RA 5  of the microcontroller  10 . A second terminal of the key K 8  is connected to a node between a second terminal of the key K 5  and an input pin RC 0  of the microcontroller  10 . A second terminal of the key K 9  is connected to a node between a second terminal of the key K 6  and the input pin RC 1  of the microcontroller  10 . First terminals of the keys K 10 -K 12  are connected to the input pin RA 4  of the microcontroller  10 . A second terminal of the key K 10  is connected to a node between a second terminal of the key K 7  and the input pin RA 5  of the microcontroller  10 . A second terminal of the key K 11  is connected to a node between a second terminal of the key K 8  and the input pin RC 0  of the microcontroller  10 . A second terminal of the key K 12  is connected to a node between a second terminal of the key K 9  and the input pin RC 1  of the microcontroller  10 . 
     During operation, the computer motherboard is powered on to enable the buck circuit  200  and the output voltage adjustment circuit  100 , and the key unit  30  is enabled by the key K 12 . An 8-bit binary signal is provided to the microcontroller  10  through selective activation of the keys K 1 -K 8 . For instance, a 0.8V voltage can be output from the buck circuit by activation of the keys K 1 -K 4  to input a signal ‘1111’. Concurrently, since the keys K 5 -K 8  are not activated, the microcontroller  10  receives a ‘0000’ signal by default. The key K 10  can be activated so that the microcontroller  10  receives a binary signal ‘11110000’ and outputs the received signal to the PWM controller  20 . As a result, the PWM controller  20  can drive the PWM driving unit  21  by which the field effect transistors Q 1  and Q 2  can receive low potential driving signals and high potential driving signals therefrom, adjusting the output voltage of the voltage output terminal Vout. For instance, if the current output voltage is 0.785V, the microcontroller  10  samples the output voltages provided to the microcontroller  10  through the resistors R 5  and R 6 , comparing the output voltages with a predetermined voltage. If the sampled voltage is different from the predetermined voltage, the microcontroller  10  outputs a control signal to direct the PWM controller  20  to tune a duty cycle, so that the voltages output from the voltage output terminal Vout become identical to the predetermined voltage, such as 0.8V. When the duty cycle output by the PWM controller  20  is greater, the voltages output from the buck circuit  200  increase as well. On the contrary, when the duty cycle output by the PWM controller  20  is smaller, the voltages output from the buck circuit  200  decrease as well. The voltages output from the voltage output terminal Vout are shown by the display unit  40 . If the voltage output from the voltage output terminal Vout is to be changed to, for instance, 0.6V, the keys K 1 -K 8  have to be reconfigured so that the microcontroller  10  correspondingly samples the voltages output from the voltage output terminal Vout and outputs control signals to direct the PWM controller  20  to fine tune a duty cycle, then a 0.6V voltage is output from the voltage output terminal Vout and shown by the display unit  40 . The details of the operations are identical to those described and are omitted. As well, during activation of the keys K 1 -K 8 , the key K 11  can be activated to cancel the current operation, and the key K 12  can be activated to enable the key unit  30 . 
     The output voltage adjustment circuit  100  provides different voltage adjustment signals to the microcontroller  10  through selective activation of the keys of the key unit  30 . The microcontroller  10  in turn samples the output voltages from the voltage output terminal Vout, comparing the output voltages to a predetermined voltage, outputting control signals accordingly to direct the PWM controller  20  to fine tune the duty cycle so that the voltage output terminal Vout outputs a stable voltage as required. 
     While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.