Abstract:
An electronic component including a number of insulated-gate field effect transistors, said transistors belonging to at least two distinct subsets by virtue of their threshold voltage, wherein each transistor includes a gate that has two electrodes, namely a first electrode embedded inside the substrate where the channel of the transistor is defined and a second upper electrode located above the substrate facing buried electrode relative to channel and separated from said channel by a layer of dielectric material and wherein the embedded electrodes of all the transistors are formed by an identical material, the upper electrodes having a layer that is in contact with the dielectric material which is formed by materials that differ from one subset of transistors to another.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority benefit of French patent application number 11/54929, filed on Jun. 7, 2011, which is hereby incorporated by reference to the maximum extent allowable by law. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The invention relates to the technical field of microelectronics and relates more particularly to a new insulated-gate field effect transistor (or MOSFET) structure and relevant manufacturing methods. 
         [0004]    2. Discussion of the Related Art 
         [0005]    In the field of circuits that contain MOSFET transistors, reduced dimensions have resulted in changes in the structure of the actual transistors in order to overcome the problem of parasitic phenomena that are capable of impairing the performance of components. 
         [0006]    Thus, there is an alternative solution for fabricating the channel of transistors without employing silicon doping techniques. This solution involves using composite gate structures referred to as “double-gate” structures in which the channel of the transistor is delimited by two opposite-facing gates. A first part of the gate is therefore located on the upper face of the substrate whereas the second part of the gate is embedded in the substrate and this makes it possible to avoid using doped silicon at the edges of the channel. 
       SUMMARY 
       [0007]    In certain applications, there may be a need for transistors that have slightly different characteristics, especially in terms of their threshold voltage. 
         [0008]    One embodiment provides an electronic component comprising a number of insulated-gate field effect transistors, said transistors belonging to at least two distinct subsets by virtue of their threshold voltage, in which each transistor has two gates, namely a first gate embedded or buried in the substrate where the channel of the transistor is defined and a second gate, or upper gate, located above the substrate facing the buried gate relative to the channel and separated from said channel by a layer of dielectric material and wherein the buried gates of all the transistors are formed by an identical material, the upper gates having a layer that is in contact with the dielectric material which is formed by a material that differs from one subset of transistors to another. 
         [0009]    Obviously, this principle can be extended to as many subsets of threshold voltages as required. Thus, in practice, the transistors can, for instance, be divided up into three distinct subsets. 
         [0000]    According to other embodiments:
 
The upper gates can be formed by stacking layers of different materials, with the number of layers differing from one subset of transistors to another.
 
The material of the buried gates can be different from the materials of the upper gates of all the subsets of transistors.
 
The material of the buried gates can belong to the group of materials used to form the upper gates.
 
         [0010]    In various embodiments, for NMOS type transistors, the material of the upper gate of a first subset may be chosen from the group comprising aluminum and molybdenum. The material of the upper gate of a second subset may be chosen from the group comprising tantalum nitride and titanium nitride. The material of the upper gate of a third subset may be chosen from the group comprising titanium nitride and cobalt disilicide (CoSi 2 ). 
         [0011]    In other embodiments, for PMOS type transistors, the material of the upper gate of a first subset may be chosen from the group comprising nickel, gold and platinum. The material of the upper gate of a second subset may be chosen from the group comprising silicon and nickel. The material of the upper gate of a third subset may be chosen from the group comprising titanium nitride and cobalt disilicide (CoSi 2 ). 
         [0012]    Such a structure can be obtained using several alternative methods depending on the desired technology. Thus, according to another embodiment, there is provided a method for manufacturing a number of insulated-gate field effect transistors on a semiconductor substrate which involves: 
         [0013]    Making a recessed opening in the substrate located underneath the channel of each transistor; 
         [0014]    Above each channel, producing upper gate structures having at least two types of metallic materials defining at least two subsets of transistors that have different thresholds voltages; 
         [0015]    Depositing, in the recessed openings, a dielectric material then filling the openings with an identical metallic material for all the transistors in order to define a buried gate structure. 
         [0000]    Different versions can be envisaged depending on the desired or available materials, applications and technologies. In practice, one can deposit the metallic materials of the upper gate structures by successively depositing different metal layers with the number of deposited layers defining the subset to which the transistor belongs.
 
In a first embodiment:
 
         [0016]    One forms the openings then one fills them with a sacrificial material; 
         [0017]    One produces the upper gate structures, including the metallic materials; 
         [0018]    One removes the sacrificial material from the openings; 
         [0019]    One fills the recessed openings with a metallic material. 
         [0000]    In a second embodiment: 
         [0020]    One forms upper gate structures by using a sacrificial material instead of electrodes; 
         [0021]    One produces recessed openings; 
         [0022]    One removes the sacrificial material from the upper gate structures; 
         [0023]    One deposits the metallic materials of the upper gate structure; 
         [0024]    One fills the recessed openings with a metallic material. 
         [0000]    In a third embodiment: 
         [0025]    One produces the recessed openings and the areas that form the locations of the upper gate structures at the same time; 
         [0026]    One deposits the metallic materials of the upper gate structures in said areas; 
         [0027]    One fills the recessed openings with a metallic material. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    Certain aspects of the embodiments and the resulting advantages will be readily apparent from the description of the following embodiments, reference being made to the accompanying drawings in which: 
           [0029]      FIG. 1  is a transverse cross-sectional view of a set of three transistors produced according to a first embodiment. 
           [0030]      FIGS. 2 to 15  are cross-sectional views showing the sequencing of the various steps involved in manufacturing a set of three transistors in accordance with a first example of the manufacturing method. 
           [0031]      FIGS. 13A ,  14 A and  15 A are longitudinal cross-sectional views of the transistors shown in  FIGS. 13 ,  14  and  15  respectively in the same state of manufacture. 
           [0032]      FIGS. 16 ,  17  and  18  are transverse, longitudinal and top cross-sectional views respectively of a transistor as fabricated using the first example of the manufacturing method and shown at the time when the gate, source and drain contacts are created. 
           [0033]      FIG. 19  is a view similar to  FIG. 17  showing a subsequent step in producing the gate contact. 
           [0034]      FIGS. 18 to 27  are transverse cross-sectional views showing the sequencing of the various steps involved in manufacturing in accordance with a second example of the manufacturing method. 
           [0035]      FIGS. 28 to 36  are transverse cross-sectional views of a single transistor showing the sequencing of the first steps in a third example of the manufacturing method. 
           [0036]      FIGS. 37 to 41  are transverse cross-sectional views of a set of three transistors shown as the sequence of manufacturing steps in the third example of the manufacturing process gradually progresses, starting from steps subsequent to that shown in  FIG. 36 . 
           [0037]    Obviously, the various elements shown in the Figures are depicted exclusively to make the embodiments easier to understand. Certain elements that have no direct bearing on the embodiments may therefore have been omitted. Similarly, the dimensions and proportions of each of the elements shown are indicated only with a view to making the embodiments easier to understand and may differ from actual dimensions and proportions. 
       
    
    
     DETAILED DESCRIPTION 
       [0038]    As illustrated in  FIG. 1 , the set of three transistors shown has an essentially common structure. Each transistor  1 ,  2 ,  3  comprises a channel  10  produced in a semiconductor substrate  11 . The various transistors  1 ,  2 ,  3  are separated from each other by deep insulating  30  trenches  12 . The transistor comprises a double-gate structure either side of channel  10 . A first gate  14  is buried in the substrate and has, around its periphery, a high relative permittivity dielectric layer  15  which separates channel  10  from the deposited metal  16  that fills the corresponding volume. 
         [0039]    Above substrate  11 , the second gate structure or upper gate structure  17  has an electrode  20  that rests on a layer of high relative permittivity dielectric material  19  which itself rests on an insulating oxide layer  18  which itself rests on the substrate and, more especially, the area that forms channel  10 . Classically, upper gate structure  17  comprises vertical walls  22  that are used to electrically insulate it from the rest of the component. 
         [0040]    Above electrode  20 , upper gate  17  comprises a conductive filler material  21  that can be one of several kinds as described later on. 
         [0041]    According to one embodiment, the material that forms electrode  20 , i.e. the material is in contact with the layer of high relative permittivity dielectric material  19 , may be  10  different between the buried gate and the upper gate but it may also be identical in certain cases as described later on. 
         [0042]    According to another embodiments, the material that forms electrode  20  of the upper gate varies from one transistor  1 ,  2 ,  3  to the next in order to define several and, in the case shown, three subsets of transistors that have different properties. 
         [0043]    The term “different materials” is taken to mean materials that have different work functions. This may involve materials that are chemically different or materials that are chemically identical or similar but which differ in respect of one particular property, especially thickness. One example is titanium nitride (TiN) which, depending on its thickness, may exhibit work function variation. 
         [0044]    Using materials that have different work functions makes it possible to create transistors that have different threshold voltages and this can prove useful in certain applications. 
         [0045]    By way of example, for NMOS type transistors, one can choose aluminum or molybdenum as a material that has a low work function and this will result in transistors that have a relatively low threshold voltage. 
         [0046]    An intermediate work function level can be obtained by using tantalum nitride or titanium nitride which provide a threshold voltage that is also intermediate. 
         [0047]    For higher threshold voltages, one can choose materials that have higher work functions such as cobalt disilicide (CoSi 2 ) or titanium nitride which are used in greater thicknesses than in the previous example. 
         [0048]    In the case of a PMOS transistor, one can, for instance, use titanium nitride or cobalt disilicide as a low work function material giving a high threshold voltage because of the majority carrier type for PMOS transistors. 
         [0049]    Using a material that has an intermediate work function, such as nickel silicide, makes it possible to obtain an intermediate threshold voltage. Materials with a high work function such as nickel, gold or platinum make it possible to obtain lower threshold voltages. 
         [0050]    Obviously, other examples of materials may be used provided this principle is respected, thus keeping to the spirit of the invention. 
         [0051]    One can advantageously choose a material that has an intermediate work function for the buried gate structures, especially if one does not wish to give overall preference to a high or low threshold voltage. 
         [0052]    As already mentioned, various implementation methods can be used to obtain the  10  transistor structures mentioned above. 
         [0053]    A first example of the method is described in  FIGS. 2 to 19 . 
         [0054]    In a first step shown in  FIG. 2 , a crystalline silicon substrate  11  is initially processed by making deep insulating trenches  12  in order to define the locations of the various transistors  1 ,  2 ,  3 . 
         [0055]    In a second step shown in  FIG. 3 , wet etching, using hydrochloric acid for example, is used to remove the silicon between insulating trenches  12 . This etching forms openings  25  having a depth equivalent to the total thickness of the channel of the transistor and the thickness of the buried gate structure. 
         [0056]    In a third step shown in  FIG. 4 , the volumes  25  thus created are filled by epitaxially  20  growing a first sacrificial layer  26  based on a mixture of silicon and germanium. A germanium proportion of 25 to 35% is preferred in order to obtain a compromise, firstly, between the selectiveness of the process of etching the mixture relative to silicon and, secondly, the risks of silicon dislocation at the interface with this mixture. 
         [0057]    The thickness of the sacrificial layer  26  of silicon/germanium is equivalent to the  25  thickness of the future buried gate. Then a layer  27  of silicon is epitaxially grown. As shown in  FIG. 4 , the silicon of the future channel just reaches the level of insulating trenches  12 . 
         [0058]    Then, as shown in  FIG. 5 , one deposits, on top of the substrate thus reformed, the layers that will form the lower part of the gate, namely a first oxide layer  30  that rests on silicon  27  of the channel, then a layer  31  of high relative permittivity dielectric material.  30  Finally, one deposits a first layer  32  of a first metal that covers all the locations of transistors  1 - 3  without distinction. Prior to this stage, all the transistors are processed without differentiation. 
         [0059]    In a subsequent step, shown in  FIG. 6 , one deposits a photolithography resin  35  which is then removed from vertically above two of the three transistors in order to protect metal layer  32  deposited on first transistor  1  by an etching step intended to remove this metal layer from the other two transistors  2 ,  3 . 
         [0060]    Subsequently and as shown in  FIG. 7 , one deposits a second layer  33  of metal after removing resin  35  which previously protected metal layer  32  of first transistor  1 . This metal is different from the metal deposited on first transistor  1 . It is this metal that is in contact with the dielectric layer of transistor  2  and whose work function will therefore determine the threshold voltage of transistor  2 . 
         [0061]    In a subsequent step shown in  FIG. 8 , one deposits a resin  36  which is then removed, only leaving resin on the second metal layer  33  deposited on first transistor  1  and second transistor  2 . The second metal layer deposit is then removed from vertically above the third transistor  3  so as to expose the layer  31  of dielectric material. 
         [0062]    Depositing a third metal layer  37  makes it possible, as shown in  FIG. 9 , to produce the electrode of third transistor  3  using a material that is different from the materials of the electrodes of first transistor  1  and second transistor  2 . 
         [0063]    Then, as shown in  FIG. 10 , one removes the metal layers from the three transistors  1 ,  2 ,  3  in order to preserve only stacks  41 ,  42 ,  43  produced in the central part in order to define the three gate structures. Protective walls or spacers  45 ,  46  can thus be produced in order to protect the gate electrode and, more generally speaking, the gate structure of the rest of the component during the subsequent steps of the method. 
         [0064]    Note that the gate structures thus defined extend longitudinally from one transverse insulating trench to another so that they do not rest exclusively on silicon layer  11  which forms the channel of the transistor but protrude slightly although this is not apparent in the Figures that show transverse cross-sectional views. 
         [0065]    In a subsequent step shown in  FIG. 11 , anisotropic etching is performed to form openings  51 ,  52  by removing the silicon of upper layer  27  and the sacrificial material  26  in vertical alignment with those areas that are not covered by the gate structures. 
         [0066]    Then, as shown in  FIG. 12 , one fills volumes  51  ;  52  thus created by epitaxially growing silicon that forms future source junctions  55  and drain junctions  56 . Note that sacrificial material  26  is preserved in the volume that will constitute the future buried gate. 
         [0067]    In a subsequent step shown in  FIG. 13 , insulating trenches  12  are etched to a depth substantially equivalent to the deepest level of sacrificial material  26 . This etching is preferably isotropic etching in order to also remove those parts of the insulating trenches that are covered by the gate structures, as stated above, and defines volumes  58 ,  59  that are visible in  FIG. 13A . This actually makes it possible to provide access to the ends of the volumes of sacrificial material  26  which are below the upper gate structure. 
         [0068]    Then, as shown in  FIG. 14 , one etches the sacrificial material, typically using a tetrafluoromethane (CF 4 ) or sulfur hexafluoride (SF 6 ) plasma. This forms openings  60  which are intended to accommodate the future buried gates, as shown in  FIG. 14A . 
         [0069]    Then, as shown in  FIG. 15 , one deposits a layer  65  of high permittivity material which lines openings  60 . Then one fills these openings with a deposited metal  63 . 
         [0070]    Thus, as shown in  FIG. 15A , the lower gate structure extends over the same length as the upper gate structure and fills volumes  64 ,  65  located between insulating trenches  12  and  10  the ends  44  of the upper gate structures. 
         [0071]    In a subsequent step, one conventionally forms a silicided layer in vertical alignment with the source and drain junctions so as to facilitate electrical contact. One also deposits spacers  54  in order to improve the insulation of the transistor. 
         [0072]    Subsequently and as shown in  FIGS. 16 ,  17 ,  18 , one produces contacts with the source and drain holes and the gate. In order to achieve this and as shown in  FIG. 16 , after depositing a dielectric layer  70 , one forms vertical holes  71 ,  72 ,  73  which open out on the silicided areas created in vertical alignment with the source and drain junctions. 
         [0073]    The holes that relate to the contacts of the source and drain junctions are then protected, as a subsequent step is required in order to link the buried gates structure and the upper gate structure. 
         [0074]    As shown in  FIG. 18 , a mask  79  is placed over holes  71 ,  73  in which the contacts for the source and drain will be produced. Then, as shown in  FIG. 19 , additional etching is performed at the level of hole  72  formed in the gate contact so as to remove high permittivity layers  31 ,  65  and oxide layer  30  which separates the electrodes of the two gate structures. 
         [0075]    The contacts are then produced in a conventional manner that is familiar to those skilled in the art. 
         [0076]    An alternative manufacturing method is described in  FIGS. 20 to 27 . 
         [0077]    In this case, the method starts with steps that are identical to those described in  FIGS. 3 ,  4  and  5  of the first embodiment up to the formation of silicon layer  127  that will form the channel of the various transistors  101 ,  102 ,  103 . 
         [0078]    Thus, in a step subsequent to that shown in  FIG. 20 , one forms sacrificial gate structures  111 ,  112 ,  113  by depositing a layer  115  of silica and a layer  116  of polysilicon which are subsequently preserved only in the locations of the future gates, it being understood that silica layer  115  will remain in the final component whereas polysilicon layer  116  is used as a sacrificial material. 
         [0079]    Then, one proceeds in a way that is similar to  FIGS. 11 to 14  in the first embodiment in order to etch the areas of the future source and drain junctions, use epitaxial growth in order to form these junction regions, etch deep insulating trenches  1 ,  2  and remove the silicon/germanium-based sacrificial material that fills volume  160  of the future buried gates. This produces the structure shown in  FIG. 21 . 
         [0080]    Then, in a step shown in  FIG. 22 , one deposits a dielectric material  130  in order to fill the volumes located between sacrificial gate structures  111 ,  112 ,  113 . This assembly is then planarized in order to expose polysilicon layers  116  which form the sacrificial material of future upper gates  111 ,  112 ,  113 . 
         [0081]    Then, as shown in  FIG. 23 , polysilicon areas  116  are then removed, opening up volumes  141 ,  142 ,  143  for the future upper gates, thus making it possible to deposit a layer  131  of high relative permittivity dielectric material. This material is deposited in the bottom of the future upper gates as well as over the entire periphery of the opening that will accommodate the future buried gate in order to form layer  165  that will separate the substrate from the electrode of the buried gate. 
         [0082]    In a subsequent step shown in  FIG. 24 , a photolithography resin  150  is deposited, making it possible to protect the volumes  142 ,  143  for future upper gates for two transistors  102 ,  103 . One deposits a non-compliant first metal in the free space  141  for first transistor  101 . The non-compliant nature of this deposited layer  132  makes it possible to prevent this metal being deposited in other areas where it is not wanted, especially in the location of the future buried gates. 
         [0083]    When electrode  132  of the upper gate of the first transistor has been thus formed, one can, as shown in  FIG. 25 , remove the resin mask that protects the second transistor in order to subsequently also deposit a non-compliant layer  133  of a second metal that is different from the metal that was deposited in the upper gate of the first transistor. Note that a similar layer  134  is also deposited on electrode  132  of the gate of the first transistor. 
         [0084]    Similarly and as shown in  FIG. 26 , one then deposits a layer  137  of a third metal in order to form the electrode of the gate of the third transistor. This third metal is also deposited in the free spaces for the upper gates of the two other transistors. 
         [0085]    Then, as shown in  FIG. 27 , one deposits a compliant metal  163  in order to fill the volumes formed by the openings for the buried gates. 
         [0086]    Note that it is also possible for this compliant metal to be deposited at the same time as one of the three metals  132 ,  133 ,  137  deposited for the upper gates and this makes it possible to eliminate one manufacturing step. 
         [0087]    In this second embodiment, one reaps the benefit of producing the gate structure after the steps that involve annealing and this ensures that the dielectric properties of the gates are preserved. Another advantage of the method corresponding to this embodiment is that it makes it possible to define the gates more accurately. 
         [0088]    An alternative that constitutes a third implementation method can also be used as shown in  FIGS. 28 to 41 . 
         [0089]    In this example, because the first steps are common to all the transistors regardless of the set to which they will eventually belong, only a single transistor is represented in  FIGS. 28 to 36 . 
         [0090]    Thus, as shown in  FIG. 28 , one uses, as already stated, a crystalline silicon substrate  211  in which insulating trenches  212  have been made. 
         [0091]    Then, as shown in  FIG. 29 , one etches the silicon, using hydrochloric acid for example, in order to define volume  225  in which the lower gate will be placed. 
         [0092]    Then, as already stated and shown in  FIG. 30 , one epitaxially grows a deposited mixture of silicon/germanium  226 , then a layer  227  of silicon that will form the future channel of the transistor. 
         [0093]    Then, as shown in  FIG. 31 , one isotropically etches insulating trenches  212  so as to reveal the edges of previously deposited layers  226  of silicon/germanium sacrificial material. Plasma etching, typically based on fluorine compounds, is then used to remove this sacrificial material as shown in  FIG. 31 . 
         [0094]    In a subsequent step shown in  FIG. 32 , one deposits a compliant layer  215  of hydrogen silsesquioxane (HSQ) used as a resin which therefore fills volume  216  opened up underneath layer  227  which forms the channel of the transistor. 
         [0095]    As shown in  FIG. 33 , this resin is exposed to specific radiation after applying a protective mask in vertical alignment with the future gates. This exposure to radiation transforms this HSQ layer into silica, apart from area  221  for the future gates which was protected from the radiation. 
         [0096]    These areas  221  are then removed as shown in  FIG. 34  so as to define two empty volumes  228 ,  229  that define the location of the future upper gate and the location of the buried gate. 
         [0097]    Then, as shown in  FIG. 35 , these volumes  228 ,  229  each accommodate sacrificial gate structures formed by a layer  218 ,  219  of silica (SiO 2 ) and a layer  220 ,  221  of polysilicon. 
         [0098]    As shown in  FIG. 36 , the silica originating from the HSQ resin is removed, then one deposits a dielectric material  222  inside the opening made as well as on the upper layer where one then forms, by etching, spacers  223  of the future upper gate. 
         [0099]    Then, as shown in  FIG. 37 , one deposits  230  a dielectric material between the spacers of the future upper gates. 
         [0100]    After planarizing in order to expose previously deposited polysilicon areas  220 , one then etches these polysilicon areas that are used as a sacrificial material and this opens up volume  252  for the future buried gates and volume  251  for the future upper gates. 
         [0101]    Then, as shown in  FIG. 38 , and in a way similar to that stated in the above examples, one deposits a layer  231 ,  265  of high relative permittivity dielectric material which lines the bottom of volume  254  for the future upper gate and volume  252  for the future buried gate. 
         [0102]    Then, after depositing a resin mask  250  that protects two of the three transistors  202 ,  203 , one deposits a non-compliant first metal layer  232  in the bottom of the future upper gate of first transistor  201  so as to form the electrode of the upper gate. 
         [0103]    Then, as shown in  FIG. 39 , after removing part of protective mask  250 , one also deposits a non-compliant layer of a second metal  233  that covers the electrode of the upper gate of first transistor  201  and covers the dielectric material  231  located at the bottom of the upper gate of the second transistor. 
         [0104]    Then, as shown in  FIG. 40 , after removing the resin mask, one deposits a non-compliant layer of the third metal  237  which thus creates the electrode of the upper gate of third transistor  203 . 
         [0105]    Then, as shown in  FIG. 41 , one deposits a compliant layer of metal  263  that forms the electrode of all the buried gates. Note that this material can be identical to one of the three metals previously used to produce the electrodes of the upper gate, in which case the latter may also be deposited compliantly. 
         [0106]    Obviously, other incidental steps or steps that are not directly related to the invention can be used but they are not described here insofar as they have no direct impact on the invention. 
         [0107]    The above descriptions show that the method according to the invention and the transistor structure thus obtained make it possible to achieve good electrostatic immunity inside the channel because the method makes it possible to use silicon channels that are not doped thanks to the presence of the double-gate structure. 
         [0108]    This advantage is combined with the ability to produce transistors that have different threshold voltage levels depending on the selected materials. 
         [0109]    Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.