Abstract:
The invention is an error correcting system which calculates the error locations, that is, finds the roots of the error locator equation: 
     
       1+δ.sub.1 *x+δ.sub.2 *x.sup.2 +δ.sub.3 x.sup.3 + . . . 
     
      +δ v-1  *x v-1  +δ v  *x v  =0    (1) 
     where &#34;+&#34; and &#34;*&#34; represent Galois Field addition and Galois Field multiplication, respectively, and &#34;v&#34; is the number of errors in the data by substituting the error location equation coefficients into a succession of v error location formulas along with successive values of x to determine if the various x&#39;s are roots of equation (1). When the first root is found, extraction of the root corresponds to reducing the degree of equation (1) by one, to (v-1), and also to reducing the number of error location formulas by one to (v-1). Thus substitution in the error location formulas of further values of x to find the next root requires one fewer addition operation and one fewer multiplication operation. When another root is found, the error location formulas are further reduced by one. This procedure is repeated until, depending on the system utilized, all v roots are found or v is reduced to a value of 2, 3 or 4, and a fast-decoding method is utilized to find the remaining roots.

Description:
This is a continuation of application Ser. No. 193,381 filed May 12, 1988 now abandoned. 
    
    
     FIELD OF INVENTION 
     This invention relates to error correction code decoding mechanisms in general and more particularly to the decoding of Bose-Chaudhuri-Hocquenghem (BCH) error correction codes, including Reed-Solomon error correction codes. 
     DESCRIPTlON OF PRIOR ART 
     The importance of error correction coding of data in digital computer systems has increased greatly as the density of the data recorded on mass storage media, more particularly magnetic disks, has increased. With higher recording densities, a tiny imperfection in the recording surface of a disk can corrupt a large amount of data. In order to avoid losing that data, error correction codes (&#34;ECC&#39;s&#34;) are employed to, as the name implies, correct the erroneous data. 
     Before a string of data symbols is recorded on a disk, it is mathematically encoded to form ECC symbols. The ECC symbols are then appended to the data string to form code words--data symbols plus ECC symbols--and the code words are then stored on the disk. When the stored data is to be retrieved from the disk, the code words are mathematically decoded. During decoding any errors in the data are detected and, if possible, corrected through manipulation of the ECC symbols [For a detailed description of decoding see Peterson and Weldon, Error Correction Codes, 2d Edition, MIT Press, 1972]. 
     Stored digital data can contain multiple errors. One of the most effective types of ECC used for the correction of multiple errors is a Reed-Solomon code [For a detailed description of Reed-Solomon codes, see Peterson and Weldon, Error Correction Codes]. Error detection and correction techniques for Reed-Solomon ECC&#39;s are well known. Id. One such technique begins with again encoding the data string in the retrieved code word to generate ECC symbols and then comparing these ECC symbols with the ECC symbols in the retrieved code word, i.e. the ECC symbols generated by the pre-storage encoding of the data, to detect any errors in the retrieved code word data. [For a detailed discussion of this error detection technique, see U.S. Pat. No. 4,413,339 issued to Riggle and Weng]. 
     The comparison of the two sets of ECC symbols is made by exclusive OR&#39;ing (&#34;XOR&#39;ing&#34;) them. If there are no errors in the retrieved code word data, the XOR&#39;ing will produce a string of symbols containing only zeros. If there are errors in the retrieved data, the result of the XOR&#39;ing will be non-zero and error correction will be then performed, if possible. If the number of non-zero symbols which result from the XOR&#39;ing is less than the number of errors the code is designed to correct, all the errors are in the ECC symbols, i.e. there are no errors in the data string, and no error correction is required. If the number of non-zero resulting symbols is equal to or greater than the number of errors the code is designed to correct, the retrieved data string contains one or more errors and error correction is then performed. 
     In order to correct the data errors, the locations and the magnitudes or &#34;values&#34; of the errors must be determined. The first step in determining the error locations and the error values is to form error syndrome equations from the results of the XOR&#39;ing of the ECC symbols. [For a detailed discussion of the generation of the error syndromes refer to U.S. Pat. No. 4,413,339 issued to Riggle and Weng]. The error syndromes are then used to generate polynomials which, when evaluated, will identify the location and the value of each of the errors. Alternatively the error syndromes may be formed by using the entire retrieved code word. This will avoid the steps of re-encoding the retrieved data and comparing the ECC symbols with the retrieved ECC symbols. However, error syndromes must then be generated for every code word, even those without errors, although in the latter case the syndromes will be identically zero. Where there are errors, i.e. the error syndromes are not zero, the syndromes are then used to locate and correct any errors in exactly the same manner as the syndromes formed from the results of the XOR&#39;ing of the ECC symbols. The choice between these two arrangements may, for example, depend on whether the syndromes are generated in software or hardware. 
     The calculation of the values of the errors is necessarily dependent on their locations. The error locations are calculated by using the error syndromes to generate an error locator polynomial δ(x) of degree v, where v is the number of errors. The solutions or roots of the equation δ(x)=0 designate the locations of the errors. These roots are of the form x i  =α i , where α is the primitive element of the Galois Field GF(p q ) used to encode the data. 
     The roots of the error locator equation are typically found using a Chien search. The Chien search systematically tries each element x of GF(p q ) as a possible solution to δ(x)=0. Each time a new value of x is tried, v Galois Field multiplication operations and v Galois Field addition operations are performed to determine if x is a solution. Once all v roots have been found, they are substituted into an error evaluator polynomial Φ(x) and the corresponding error magnitudes, or values are calculated. The data can then be corrected by multiplying the erroneous data symbol by a correction symbol to produce an error-free data symbol. 
     The time it takes to perform error correction significantly affects the rate at which data can be retrieved from a storage device. As the potential for errors in stored data increases with the use of higher recording densities, slow error correction has a material effect on the average speed with which the data can be retrieved. The increased data retrieval time in turn limits the speed of all computer applications that require the retrieval of stored data. This speed limitation occurs at a time when computer system technology advances have otherwise made possible faster data transfer operations. 
     Thus there is a need for an error correction technique that can be performed more quickly than the methods currently in use. Such a technique will enable computer systems to operate at the faster rates permitted by the advances in the state of the art computer technology. 
     SUMMARY OF THE INVENTION 
     The invention is an error correcting system which calculates the error locations with a reduced number of operations. The error correcting system can thus more quickly correct the errors. Basically, each time a root of the error locator equation is found, the equation is modified to reduce the number of Galois Field multiplication and addition operations that are required to evaluate as possible solutions the remaining values of x. The modification, in effect, reduces the degree of the equation. All of the roots of the equation may be found using this technique, or the technique may be used to find several of the roots and a fast-decode method designed specifically for solving equations having two, three or four roots may be used to find the remaining roots. 
     In brief summary the error locator equation is: 
     
         1+δ.sub.1 *x+δ.sub.2 *x.sup.2 +δ.sub.3 x.sup.3 +. . . +δ.sub.v-1 *x.sup.v-1 +δ.sub.v *x.sup.v =0    (1) 
    
     where &#34;+&#34; and &#34;*&#34; represent Galois Field addition and Galois Field multiplication, respectively, and &#34;v&#34; is the number of errors in the data. As described below, the coefficients of equation (1) are substituted into a succession of v error location formulas along with successive values of x, to determine if the various x&#39;s are roots of equation (1). Since equation (1) is of degree v, each such determination requires v multiplication and v addition operations. When the first root is found, extraction of the root corresponds to reducing the degree of equation (1) by one, to (v-1), and also to reducing the number of error location formulas by one to (v-1). Thus substitution in the error location formulas of further values of x to find the next root requires one fewer addition operation and one fewer multiplication operation. 
     Thereafter, when another root is found, the error location formulas are further reduced by one. This procedure is repeated until, depending on the system utilized, all v roots are found or v is reduced to a value of 2, 3 or 4, and a fast-decoding method is utilized to find the remaining roots. 
     Reducing the number of multiplication and addition operations required to find the remaining roots of the error locator equation each time a root is found speeds-up the error correction process. The faster errors in the data can be corrected, the faster the data can be transmitted to the remainder of the data processing system. This is particularly important as data is recorded at increased densities, leading to more errors, and thus requiring more error correction. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     This invention is pointed out with particularity in the appended claims. The above and further advantages of this invention may be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a functional block diagram of a decoding system built in accordance with a first embodiment of the invention; 
     FIGS. 2A-B are flow charts of the steps involved in the operation of the first embodiment of the invention; 
     FIG. 3 is a functional block diagram of a decoding system built in accordance with a second embodiment of the invention; and 
     FIGS. 4A-B are flow charts of the steps involved in the operation of a second embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     It should be understood that all addition and multiplication operations performed by the inventive system are Galois Field operations and that the Galois Fields are of the form GF(p q ). 
     Conventional techniques are used to generate the error syndromes from the data and then to generate the error locator equation, δ(x)=0. 
     With reference to FIGS. 1 and 2, an error correcting system 8 evaluates δ(x) at various values of x using the following set of error location formulas: ##EQU1## where δ i  =x and the terms δ j  &#39; are modifications of the δ j  terms, not derivatives of these terms (step 50). Successive values of δ j  &#39; are calculated from the previous values until the value of δ v  &#39; is determined. If δ v  &#39; is equal to ZERO for a particular x, x is a root of equation (1) (steps 51, 56). 
     Formulas 2 1  -2 v  are evaluated using registers 10 1  -10 v  (generally referred to by the numeral 10), Galois Field multipliers 12 1  -12 v  (generally referred to by the numeral 12) and Galois Field adders 14 1  -14 v  (generally referred to by the numeral 14). To begin, the coefficients of equation (1) are stored in registers 10, a counter 18 and a comparator 30 are initialized to v, and an α register 38 is initialized to a first value of x, x=α i  where i is typically zero. 
     Register 38 applies the first x value to each of the multipliers 10 and to the adder 14 1 . The adder 14 1  calculates the sum: 
     
         δ.sub.1 &#39;=δ.sub.1 +α.sup.1. 
    
     This sum is applied to both to a register 16 where it is stored and to a multiplier 12 1  which, when clocked by a clock 34 through gates 26 as discussed in more detail below, calculates the product: 
     
         δ.sub.1 &#39;*α.sup.i 
    
     This product is applied to adder 14 2 , which calculates the sum, δ 2  &#39;. The value of δ 2  &#39; is stored in a register 16, and it is also used to calculate the product δ 2  &#39;*α i . This product is then used to calculate δ 3  &#39; and the value of δ 3  &#39; is stored in register 16. The sums δ j  &#39; and the products δ j  &#39;*α i  are similarly calculated for each coefficient using the multipliers 12 and the adders 14, and the each of the values of δ j  &#39; are in turn stored in the register 16. 
     Register 16 is addressed by counter 18, which is set to the value v. Thus the register 16 applies the contents of the storage location addressed by the counter to its output. Accordingly, when the term δ v  &#39; is applied to the register 16, it appears also at its output. This output is then applied to a zero compare 20 where it is compared to ZERO. If δ v  &#39; equals ZERO, indicating that α i  is a root of the error location equation, the output of the zero compare 20 is asserted. If δ v  &#39; does not equal ZERO, indicating α i  is not a root of the error locator equation, the output of the zero compare 20 is not asserted. 
     Clock 34 controls the timing of the various multipliers and gates using three timers, namely t 1 , t 2 , and t 3 , to avoid race conditions. Timer t 1  clocks counter 28 which, in effect, counts the number of multiplication operations performed in calculating δ v  &#39;. Timer t 2 , which is slightly slower than t 1 , clocks gates 26 which in turn clock multipliers 12. Timer t 3 , which is slightly slower than timer t 2 , acts as an input to an AND gate 32. 
     To begin calculating the formulas 2 1  -2 v , the sum δ 1  &#39; is calculated by adder 14 1  as described above and the sum is applied to multiplier 12 1 . Timer t 1  clocks counter 28, and the counter applies a count of one, signalling the first of v multiplication operations, to the gates 26. Thereafter the gates 26, when clocked by timer t 2 , apply a clock pulse to the first multiplier 12 1  and the first product, δ 1  &#39;*α i , is calculated. The output of counter 28 is also applied to the comparator 30, where it is compared to v. The comparator 30 asserts its output when the count equals v, indicating the occurrence of the &#34;vth&#34; multiplication operation. If the count of counter 28 is not equal to v, the output of the comparator 30 remains de-asserted. 
     Assuming that the count does not equal v, the first product calculated by multiplier 12 is applied to adder 14 2  which adds it to δ 2  to produce the sum δ 2  &#39;. This sum is stored in the register 16 and is also applied to multiplier 12 2 . Timer t 1  clocks the counter 28, which increases the count to two, indicating that the second multiplication is to occur. The output of counter 28 is applied to gates 26 which, when subsequently clocked by timer t 2 , clock multiplier 12 2  which then calculates the product: 
     
         δ.sub.2 &#39;*α.sup.i. 
    
     This product is applied to adder 14 3  which calculates the sum δ 3  &#39;, and the sum is again stored in register 16. The same series of addition and multiplication operations continue and the sums δ j  &#39; are stored in the register 16 until the count of counter 28 equals v, indicating the start of the calculation of formula (2 v ). When the count of counter 28 equals v, the output of the comparator 30, which is comparing the count to v, is asserted. The output is applied to one input of an AND gate 32, which has a second input connected to timer t 3 . Thus when timer t 3  is pulsed, the output of the AND gate 32 is asserted. 
     The output is applied to one input of AND gate 22, which has a second input connected to the output of zero compare 20. If the sum δ v  &#39; is equal to ZERO, that is, x is a root, the output of AND gate 22 will then be asserted. Otherwise, if δ v  &#39; is not equal to ZERO, the output of the zero compare 20 remains de-asserted and thus the output of AND gate 22 is not asserted. 
     If x is not a root of equation (1), a new value of x is substituted into formulas 2 1  -2 v  and the sum δ v  &#39; is calculated and compared to ZERO to determine if it is a root (steps 52-54). Thus the asserted output of AND gate 32 is applied, through delay 33, to (i) reset the clock 34, (ii) load a new value of x=α i+1  from calculator 36 into register 38, and (iii) enable calculator 36 to calculate a new value of x. The value of x loaded into register 38 is then evaluated as a possible root, in the manner described above. This evaluation involves v multiplication operations and v addition operations. 
     If x is a root, the coefficients of equation (1), and accordingly the formulas 2 1  -2 v , are modified and the degree of equation (1), that is, the value of v, is reduced by one (steps 58-60). Thereafter, a new value of x is substituted into the modified formulas 2 1  -2 v  and a new sum δ v  &#39; is calculated (steps 62-64). With further reference to FIG. 3, if x is a root the sum δ v  &#39; is equal to ZERO and the output of the zero compare 20 is asserted. This output is applied to one input of AND gate 22. The second input of AND gate 22 is connected to the output of AND gate 32 which is asserted at the next t 3  clock pulse. Thus, two gate delays after t 3  is pulsed, the output of AND gate 22 is asserted. 
     The asserted output of AND gate 22 is applied simultaneously to (i) a memory 40, which stores the value α i  as a root; (ii) the counter 18, which decrements its count to v-1; and (iii) the registers 10, which load the sums δ j  &#39;. The output of gate 22 is also applied a short time later, through delay 24, to the comparator 30, which decrements the value of v stored therein by one. Thereafter, clock 34 is reset through delay 33 and a new value of x=α i+1  is loaded into the α register 38. The calculator 36 is also enabled to begin calculating a new value of x=α i+1 . 
     When timer t 1  is pulsed, the evaluation operations begin, using the modified coefficients, δ j  &#39;, and the new value of x. The evaluation involves one less multiplication operation and one less addition operation. Thus the time required for the evaluation is reduced from the time taken to evaluate the previous value of x as a root. 
     Each value of x=α i+1  calculated by calculator 36 is checked against the code block length, not exceeding P 1  -1, to determine if the value is a &#34;new&#34; value of x (steps 54,64). If i+1 is less than or equal to the code block length, the value of x=α i+1  is a new value. If, however, i+1 is greater than the code length, the calculated value of x=α i+1  corresponds to an error location outside of the code length. If the value of x calculated by calculator 36 is not a &#34;new&#34; x value, it indicates that all the roots of equation (1) can not be found and thus the error locations can not all be determined to be within the code length. Thus calculator 38 notifies a system controller (not shown) that the data is uncorrectable (steps 55, 65). 
     All the roots of equation 1 which are of the form x=α i  can be found using the technique described above. However, known methods of finding the roots of degree 2, 3 or 4 equations in FG(p q ) may be used to find the remaining roots (steps 70-71, FIG. 2B). The particular method used will depend on system design. 
     A second embodiment uses a direct modification of the Chien search to find the roots of the error locator equation. With respect to FIGS. 3 and 4, an error correcting system 99 iteratively evaluates δ(x) by first adding the coefficients of equation (1) to produce the sum S v  and comparing the sum to ONE (step 150-152). Thereafter δ(x) is evaluated using the following set of iterative error location formulas: ##EQU2## (step 166). Thus new values of δ j  are calculated each iteration and after i iterations the formulas have calculated δ k  =δ k (original) *(α k ) i . After each iteration the δ j  terms are added to produce the sum S v  (step 168). If S v  is equal to ONE for a particular iteration, for example the i th  iteration, x=α i  is a root (step 171). 
     Formulas 3 1  -3 v  are evaluated using registers 100 1  -100 v  (generally referred to by the numeral 100), Galois Field multipliers 102 1  -102 v  (generally referred to by the numeral 102) and Galois Field adders 104 1  -104 v  (generally referred to by the numeral 104). To begin, the coefficients of equation (1) are stored in registers 100, a counter 108 and a comparator 120 are each initialized to v, and a register 126 is initialized to a first value of i=0. 
     The multipliers, counters and timers are clocked by a clock 124, which operates in the same manner as the clock 34 described above with reference to FIG. 1. Each intermediate sum, S j , calculated in adders 104 is applied to a register 106 which is addressed by counter 108. When the sum S v  is applied to the register 106, it appears at the output, also. The sum S v  is then compared to ONE in a one compare 110. If the sum S v  equals ONE, x=α i  is a root of equation (1). If the sum S v  does not equal ONE, x=α i  is not a root. 
     If x is not a root of equation (1), formulas 3 1  -3 v  are iteratively updated and the sum S v  is calculated (steps 166-168). The sum is then compared to ONE to determine if the x corresponding to the particular iteration is a root (step 170). Accordingly, system 99 operates in a manner similar to the system described with reference to FIG. 1. Thus the clock 124 is reset and the formulas are iteratively updated, corresponding to the earlier-described system trying a new value of x. The new sum Sv is then evaluated to determine if x is a root. This evaluation involves v multiplication operations and v addition operations. 
     If x is a root, the coefficients of formulas 3 1  -3 v  are modified and the degree of the equation, that is, the value of v, is reduced by one (steps 156-158). This reduces the number of multiplication and addition operations required to evaluate the formula for the next iteration. The coefficients δ j  are modified as follows: ##EQU3## where the terms δ j  &#39; are modifications of the δ j  terms, not derivatives of these terms (step 156). The modified coefficients are then substituted into formulas 3 1  -3 v  and the formulas are evaluated for an associated next value of x. 
     With further reference to FIG. 3, if the sum S v  is equal to ONE if x=α i  is a root and the output of the one compare 110 is asserted. Thus the output of AND gate 112 is asserted two gate delays after the output of AND gate 122 is asserted at the next t 3  clock pulse. The asserted output of AND gate 112, which signifies that x=α i  is a root of equation (1), is applied simultaneously to (i) a memory 130, which stores the value α i  as a root; (ii) the counter 108, which decrements its count to v-1; and (iii) a counter 126, which, through gates 128, enables successive registers 100 to load the associated sums δ j . The output of gate 112 is also applied a short time later, through delay 123, to the comparator 120, which decrements the value of v stored therein by one. 
     Thereafter, clock 124 is reset through delay 123, and the evaluation operations begin, using the modified coefficients, when timer t 1  is pulsed. The evaluation involves one less multiplication operation and one less addition operation. Thus the time required for the evaluation is reduced from the time taken to evaluate the iteration corresponding to the previous value of x. 
     The value of i in register 26, which is updated for each iteration is continuously checked against the code block length, P q  -1, to determine if the value is a &#34;new&#34; value of x (step 164) in the same manner as calculator 36 described with reference to FIG. 1. If x is a new value, an i th  iteration will be performed. If x is not a &#34;new&#34; value, it indicates that all the roots of equation (1) can not be found in GF(p q ) and thus the error locations can not all be determined. The system controller is thus notified that the data is uncorrectable (step 165). 
     All the roots of equation 1 of the form x=α i  can be found using the technique described above. However, known methods of finding the roots of degree 2, 3 or 4 equations in GF(p q ) may be used to find the remaining roots (step). The particular method used will depend on system design. 
     The foregoing description has been limited to two specific embodiments of this invention. It will be apparent, however, that variations and modifications may be made to the invention, with the attainment of some or all of the advantages of the invention. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.