Abstract:
A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as the electroprocessing is performed on the conductive layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 11/232,718, filed Sep. 21, 2005, which is incorporated herein by reference in its entirety. 

   FIELD 
   The present invention generally relates to semiconductor processing technologies and, more particularly, to an electrodeposition process employing selective formation of contact layers on substrates. 
   BACKGROUND 
   Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. The interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. The interconnects formed in different layers can be electrically connected using vias or contacts. A metallization process can be used to fill such features, i.e., via openings, trenches, pads or contacts by a conductive material. 
   Copper (Cu) and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The preferred method of copper metallization is electroplating.  FIG. 1  shows a substrate  10  prepared for an electroplating process. The substrate  10  is an exemplary surface portion on a front surface of the wafer W shown in  FIG. 2 , which includes a border region between the edge of the surface and the rest of the surface or the central surface region of the wafer W. Referring back to  FIG. 1 , for interconnect fabrication, the substrate  10  includes a dielectric layer  12  having features  14 , such as vias and trenches, formed in it. The substrate  10  is typically coated with a barrier layer  16  and a seed layer  18 . Typical barrier layer materials include tungsten, tantalum, titanium, their alloys, and their nitrides. The barrier layer  16  coats the substrate to ensure good adhesion and acts as a barrier to prevent diffusion of the copper into the dielectric layers and into the semiconductor devices. The seed layer  18 , which is often a copper layer, is deposited on the barrier layer  16 . The seed layer  18  forms a conductive material base for the copper film growth during the subsequent copper deposition. As shown at the left side of  FIG. 1 , to enable copper deposition from a copper containing electrolyte, an electrical contact is connected to the seed layer  18  and a potential difference is established between an electrode and the seed layer  18 . 
   The copper seed layers for copper interconnects are typically deposited by physical vapor deposition (PVD) techniques. As the feature size goes to 32 nanometers (nm) and below, seed layers in the thickness range of 5-20 nm will be desirable to coat such tiny features. The most common problem associated with such thin seed layer deposition is poor step coverage, which may give rise to discontinuities in the seed layer and related defects especially within the smallest features having the highest aspect ratios. Due to imperfect conformality, the seed layer thickness at the lower portions or on the side-walls of the vias and trenches may be very low, such as less than 3 nm, or the seed layer at such locations may be discontinuous. Thin portions of the seed layer may contain large amounts of oxide phases that are not stable in plating solutions. During the subsequent copper deposition process, such defective areas cause unwanted voids in the copper filling, leading to inadequately filled vias and trenches, high resistance and short lifetime for the interconnect structure. Oxidation problems are further exacerbated by exposure of seed layers to outside conditions as the wafers coated with seed layers are transported from the seed deposition unit to an electrochemical deposition unit for copper fill. 
   Establishing an electrical connection to such thin seed layers presents another difficulty. When such delicate layers are physically touched by electrical contacts they may get smeared, scratched, lifted up or otherwise damaged. Damaged areas of seed layers do not conduct electricity adequately. Therefore, any discontinuity or damaged area in the seed layer around the perimeter of the workpiece or wafer causes variations in the density of the delivered current, which in turn negatively impacts the plating uniformity. 
   As technology nodes are reduced to 32 nm and below, one option is to eliminate the use of the copper seed layer and deposit copper directly on the barrier layer or on a nucleation layer, such as a ruthenium (Ru) layer. In this case, the resistivity of the barrier layer or the nucleation layer is much larger (by at least a factor of 5) than the resistivity of the copper layer. Consequently, when an electrical contact is made to this high resistivity layer for the purpose of electrodepositing a copper layer, the contact resistance is expected to be larger than the contact resistance with a copper seed layer. When the density of current passed through contacts made to high resistivity thin layers is large, heating occurs at points where the electrical contacts physically touch the thin layers. Excessive voltage drop at these locations, in addition to sparking and heating, causes damage to the thin barrier layer and/or the nucleation layer, thus exacerbating the problem even further and causing additional non-uniformities in the deposited copper layers. 
   To this end, there is a need for alternative methods to enable deposition of conductors, such as copper, on workpieces or wafers comprising very thin seed layers or barrier/nucleation layers without causing damage to such thin layers and without causing non-uniformities in the deposited conductor thickness. 
   SUMMARY 
   According to one aspect of the invention, a method is provided for manufacturing contact structures on a surface of a substrate to conduct electricity from a contact member to the surface when the surface is electroprocessed. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as electroprocessing is performed on the conductive layer. 
   According to another aspect of the invention, a method is provided for applying an electrochemical process to a surface of a wafer. The method comprises forming a conductive layer on the surface of the wafer. A portion of the conductive layer is selectively coated by a contact layer. The contact layer is brought in contact with a contact member in order to connect the contact layer to a power supply. An electrical potential is applied to the contact member. 
   According to another aspect of the invention, a method is provided for applying an electrochemical process to a surface of a wafer. The method comprises forming a conductive layer on the surface of the wafer. A contact layer in contact with a portion of the conductive layer is provided. The contact layer is brought in contact with a contact member in order to connect the contact layer to a power supply. An electrical potential is applied to the contact member. 
   According to yet another aspect of the invention, a structure for electroprocessing a substrate is provided. The structure comprises a conductive layer formed on a surface of the substrate. A removable contact layer is formed on the conductive surface along an edge region of the substrate. A contact member touches the removable contact layer and connects the removable contact layer to a power supply during electroprocessing of the substrate. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic cross section of a conductive region of a wafer surface configured to conduct current to an edge region of the wafer surface, in accordance with a prior art method; 
       FIG. 2  is a schematic plan view of the conductive surface of the wafer in  FIG. 1 , showing the edge region where electrical contacts are placed; 
       FIG. 3  is a schematic cross section of the edge region of a conductive surface of a wafer comprising a contact layer through which current is conducted, in accordance a with preferred embodiment of the invention; 
       FIG. 4  is a schematic cross section of the conductive surface shown in  FIG. 3 , wherein a conductor layer has been formed on the conductive surface, in accordance with a preferred embodiment of the invention; 
       FIG. 5  is a schematic cross section of the conductive surface shown in  FIG. 4 , wherein the contact layer has been removed from the edge region, in accordance with a preferred embodiment of the invention; 
       FIGS. 6A-6B  are schematic cross sections of the contact layer, in accordance with a preferred embodiment of the invention; 
       FIG. 7  is a schematic cross section of a conductive surface of a wafer comprising a barrier layer and a contact layer formed on the barrier layer, wherein a conductor layer is partially formed on the barrier layer, in accordance with a preferred embodiment of the invention; 
       FIG. 8  is a schematic cross section of the conductive surface of  FIG. 7 , wherein plating has continued and been planarized, in accordance with a preferred embodiment of the invention; and 
       FIG. 9  is a schematic cross section of the conductive surface of  FIG. 7 , wherein plating has continued and the conductive layer is left non-planar, in accordance with a preferred embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   The present invention provides methods of forming an electrical contact layer or a contact layer on wafers to conduct electricity to a conductive surface of a wafer to enable electrochemical processing of the wafer. Electrochemical processing includes, but is not limited to, processes such as electrochemical deposition (ECD), electrochemical mechanical deposition (ECMD), electropolishing and electrochemical mechanical polishing (ECMP). Preferably, the electrical contact layer is a temporary layer partially covering the conductive wafer surface. 
   The conductive surface of the wafer may comprise any conductive material, for example a seed layer or a barrier layer material, or any other conductive material, such as a nucleation layer that enhances the nucleation capability of metal to be processed, such as, e.g., Cu. 
   Ruthenium is known to be such a nucleation layer. In the illustrated embodiments, the contact layer will be utilized for copper electrodeposition and will be formed on a copper seed layer and on a barrier layer which is often tantalum (Ta), tantalum nitride (TaN), or both. The contact layer may extend along the circumference of the wafer in a continuous or discontinuous manner. An electrical contact member connects the contact layer to a power supply. The electrical contact member may be engaged with the contact layer in a dynamic or static manner. In dynamic manner, relative motion is established between the contact layer and the contact member as the electricity is conducted to the contact layer. In static manner, the contact member is placed on the contact layer and is stationary on the contact layer. 
     FIG. 3  shows an exemplary substrate  100  on which a contact layer  102  or a disposable layer of the present invention is formed. For purposes of clarity, the substrate  100  exemplifies an edge portion of a wafer (not to scale), which may be identical to the wafer W shown in  FIG. 2 . In this example, the contact layer  102  is preferably utilized for the electrodeposition of metals, preferably Cu. According to preferred embodiments, a barrier layer  114  overlies a surface  112  of a dielectric layer  110 , which further overlies and becomes part of the substrate  100 . The substrate  100  comprises a plurality of features, such as a via  104 , a mid-sized trench  106  and a large trench  108 , all formed in the dielectric layer  110  using conventional techniques. A copper seed layer  116  comprising a surface  118  is formed on the barrier layer  114 . The barrier layer  114  and the seed layer  116  cover the surface of the wafer in its entirety, including the edge or the circumference region of the front surface. The barrier layer  114  and the seed layer  116  may also wrap around the side bevel of the wafer. For purposes of clarity only, the edge region of the front surface in the figures is shown without features  104 ,  106  and  108 , though in practice the features  104 ,  106  and  108  may extend into the edge region. 
   The contact layer  102  may fully or partially cover the edge region on the surface  116  along the perimeter of the wafer W. Further, it is possible to build the contact layer  102  along the bevel of the wafer W or along the edge of the back surface of the wafer W as long as the contact layer  102  is in contact with the seed layer  116 . It would be appreciated that the term “edge region” in the preferred embodiments defines an area from the back edge through the bevel and front edge of the wafer W. 
   The contact layer  102  may be selectively formed on any or all of these locations in a continuous or a discontinuous manner. The contact layer  102  may have a width in the range of 0.5-5 mm and a thickness in the range of 0.1-100 micrometers (μm). The contact layer  102  can be formed using a variety of processes. In some preferred embodiments, the contact layer  102 , which is preferably a conductive tape or, more preferably, a thin copper tape, is disposed along the edge region using a conductive adhesive or a mechanical clamp. In an alternative embodiment, a thin conductive paste comprising conductors such as, e.g., Cu, Ni, Ag, or Au may be applied to the edge region to form the contact layer  102 . In yet another embodiment, the contact layer  102  is formed by electrodeposition, chemical vapor deposition (CVD), or PVD, in addition to appropriate masking techniques to protect the central region of the wafer W from such deposition. In other words, the contact layer  102  is selectively applied to the edge region without application of IC components on the central region. 
   With reference to  FIGS. 3 and 4 , after forming the contact layer  102  on the surface  118  of the seed layer  116 , a conductive layer  122  is electrodeposited on the seed layer  116  by applying an electrical potential difference between a contact member  120  and an electrode (not shown) while wetting the seed layer  116  and the electrode by a process solution (e.g., electrolyte). In the preferred embodiments, the conductive layer  122  is preferably made of metal or, more preferably, Cu. The contact member  120  and the electrode are connected to the terminals of a power supply  121 . The wafer W can be supported by a wafer carrier (not shown) and may be rotated during electrodeposition. The contact member  120  may be dynamically engaged with the contact layer  102 , and a relative motion may be established between the contact member  120  and the contact layer  102  (hence the substrate). 
   With continued reference to  FIG. 4 , during electrodeposition the conductive layer  122  may grow on the edge region and on the contact layer  102 . In some preferred embodiments, the contact layer  102  is used with stationary contacts or other edge-excluding contacts. Such stationary contacts prevent material from depositing onto the contact layer  102  at the point(s) (not shown in  FIG. 4 ) where the contact member  120  is in physical contact with the contact layer  102 . Electrodeposition on the contact layer  102  may be avoided by shielding the contact layer  102  or portions thereof from the electrolyte using seals or clamps with seals. The conductive layer  122  may be deposited using electrochemical deposition (ECD) or a planar electrodeposition method, such as electrochemical mechanical deposition (ECMD). For the sake of example only, an ECMD-deposited planar conductive layer is marked by dotted line A. ECMD refers to a process in which the wafer surface is swept by a pad intermittently during plating, resulting in faster growth inside vias and trenches (or spaces), and leaving a planar conductive surface A. 
   With reference to  FIG. 5 , after electrodepositing the conductive layer  122 , the edge portion of the conductive layer  122  and the contact layer  102  are removed using an edge bevel removal (EBR) process. The EBR process exposes the barrier layer  114  at the edge region. During an EBR process, an etching solution is applied to the edge region of an electrodeposited layer  122  on the wafer. The conductor, which is often thick and comprises defects at the wafer edges, is removed from the outer edge of the wafer. 
   According to preferred embodiments, the EBR process removes the conductive layer  122 , the contact layer  102  and the seed layer  116  (which is often indistinguishable from the electrodeposited layer  122 ) at the edge region in a single step. In other embodiments, material removal from the edge region of the wafer W may be achieved by physically removing (e.g., peeling) the contact layer  102  after the electrodeposition step. Upon physically removing the contact layer by, e.g., peeling, any material overlying the contact layer  102  is concurrently removed. 
   After the EBR process, the substrate  100  may be annealed and the conductive layer  122  subsequently planarized by chemical mechanical polishing (CMP). During consecutive CMP processing steps, the seed layer  116  and barrier layer  114  on the upper surface  112  of the dielectric layer  110  are planarized, leaving conductive material isolated within the features  104 ,  106  and  108 . 
   With reference to  FIGS. 6A and 6B , in other preferred embodiments of the invention, an alternative contact layer structure is formed on an edge region  200  of the wafer W. The surface of the wafer W comprises a barrier layer  202  and a seed layer  204  deposited on a dielectric layer  206 . The contact layer  208  is sufficiently thick to enable growth of the conductive layer  210  next to the contact layer  208  during electrodeposition. Following electrodeposition, the contact layer  208  is removed using, e.g., the EBR process described above. In some preferred embodiments, the contact layer  208  is initially formed on the barrier layer  202  and the seed layer  204  is subsequently deposited on the barrier layer  202  and the contact layer  208 . 
   The contact layer examples described in the above embodiments can also be used for electropolishing or electrochemical mechanical polishing conductive surfaces of wafers. For example, in electropolishing (or electroplanarization), electrical contacts are placed on edge regions of the surface and a positive potential is applied through an electrode. Material removal occurs electrochemically and, if applicable, mechanically by applying a polishing pad to the surface. Due to the placement of the contact members on the edge of the wafer, during material removal the edge region may be thinned at a rate that is sufficiently greater than the rate at which the rest of the conductive surface is thinned, which may result in non-uniform removal or planarization of the surface. This over-thinning of the edge can be alleviated by adding contact layers to the conductive surface along the edge regions of the wafer and making electrical contact to the contact layers by contact elements. During material removal, contact members physically contact the contact layers, thus protecting the conductive surface under the contact layer from premature removal. 
   With reference to  FIGS. 7 and 8 , in other preferred embodiments, a conductor is electrodeposited on a barrier layer  310  using a contact layer  312  on the barrier layer  310 . In some preferred embodiments, a nucleation layer (not shown) may be used instead of, or in addition to, the barrier layer  310 . The electrical contact made to the contact layer  312 , which is formed as described above, is preferably more robust and of lower resistance than the barrier layer  310  and/or the nucleation layer. Consequently, electrodeposition through the application of substantially large voltages and densities of current to the contact layer  312  does not damage the barrier layer  310 .  FIG. 7  illustrates the initial stage of an electrodeposition process on a substrate  300  comprising a dielectric layer  301 . The dielectric layer  301  comprises a plurality of features, such as, e.g., a via  302 , a mid-sized trench  304  and a large trench  306 . 
   According to the preferred embodiments, the surface  308  of the dielectric layer  301  and the features  302 ,  304 ,  306  are coated with a barrier layer  310 . The barrier layer  310  may act as a nucleation layer or may have an additional thin nucleation layer (not shown) on its surface. The surface of the substrate  300  is shown near an edge portion of a wafer, such as the one shown in  FIG. 2 . A contact layer  312 , which partially or fully covers the edge of the substrate  300 , is initially formed on the barrier layer  310 . A contact member  314  connects the contact layer  312  to a power supply  316  which is also connected to an electrode (not shown). As an electrical potential difference is established between the contact layer  312  and the electrode, a first layer  317  of conductive material (e.g., Cu) is conformally deposited on the barrier layer  310 . The first layer is substantially thin such that the features  302 ,  304  and  306  are coated conformally but not filled. This initial stage of the process may require current of low density, which may be about 0.01-10 milliamperes per square centimeter (mA/cm 2 ). 
   Next, a gap-fill electrodeposition process fills the features  302 ,  304  and  306  with conductive material. The empty space within the features is filled by the application of a deposition current of about 5-60 mA/cm 2 , which is applied through the contact layer  312  in physical contact with the thin conductive layer  317  ( FIG. 7 ) previously deposited on the barrier layer  310 . This is followed by either using a planar electrodeposition process (e.g., ECMD) to form a planar conductive layer  318  or using an electrochemical deposition process to form a non-planar conductive layer  320 , as shown in  FIGS. 8 and 9 , respectively. 
   Although various preferred embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications of the exemplary embodiment are possible without materially departing from the novel teachings and advantages of the invention.