Abstract:
An HVAC system is assigned a network identification for subsequent use within a communication network upon receipt of a formatted signal containing the network identification. The HVAC system stores the network identification in nonvolatile memory. The HVAC system also preferably stores a verification image of the communicated network identification so that any reading back of the network identification can be validated through comparison with the stored verification image.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to the control of heating, ventilating and air conditioning systems through the use of a communication network. In particular, this invention relates to how an HVAC system is identified within a communication network. 
     The use of a communication network to convey control information via a common communication bus to heating and/or cooling systems connected to the bus is well known. Such networks are often used when one wishes to implement a hierarchical control of several heating or cooling systems. A central or master controller in such a hierarchical control will normally communicate with the individual heating or cooling systems connected thereto via a common control bus. It is often necessary in such instances to separately identify each heating or cooling system so that they can be separately addressed by the central or master controller. This has been heretofore accomplished by physically setting a series of address switches within each heating or cooling system. The physically set switches define a binary address that can be used by the system to identify itself to the central or master controller. Such a physical setting of the address switches to define an address or network communication identification can be time consuming when setting up a network of heating or cooling systems that is to be subject to the hierarchical control of a central or master controller. This time consuming approach is, however, usually justified on the basis that each such system must be able to rely on this fixed identification or address at all times including instances where power is lost and all systems must be again brought up to an appropriate level of control following restoration of power. 
     OBJECTS OF THE INVENTION 
     It is an object of the invention to provide each HVAC system within a communication network with the capability of being quickly, easily, and reliably assigned a particular network communication identification. 
     SUMMARY OF THE INVENTION 
     The above and other objects of the invention are achieved by providing a heating or cooling system with a receiver capable of receiving a signal that defines a network identification to be assigned to the heating or cooling system. The signal containing network identification is in a format recognizable by a programmed processor associated with the receiver. The programmed processor sets a network identifier variable within a program being executed by the processor equal to the received network communication identification. The value of this variable is thereafter preferably stored in at least one particular addressable memory location of a non-volatile memory associated with the programmed processor. A verification image of this stored value is also preferably generated and stored in another portion of the same addressable memory location so as to be recallable along with the stored value of this variable. The thus stored value of the network communication identification and its verification image must be successfully read back in order for the stored value to be used by the programmed processor following a power outage. In this regard, the stored value must have a predetermined relationship with the stored verification image in order for the processor to use the value. The processor will otherwise proceed to use a default value that will at least allow some network communications to take place with the particular heating or cooling system. 
     In accordance with another aspect of the invention, the particular value of the variable and its verification image are stored in more than one particular addressable memory location. In the event that the value and its respective verification image read stored in a first addressable memory location does not demonstrate the predetermined mathematical relationship, the processor will proceed to read and compare the stored value and verification image from at least one additional addressable storage locations. After exhausting all possible read and compares, the processor will set the network identifier equal to a default value. 
     In accordance with another aspect of the invention, the network identification for the particular HVAC system is preferably transmitted to the system by a hand held transmitter. This allows a person to assign an identification to an HVAC system even if it is not easily accessible. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the present invention will be apparent from the following description in conjunction with the accompanying drawings in which: 
     FIG. 1 illustrates a plurality of HVAC systems each connected via a common control bus to an HVAC systems controller; 
     FIG. 2 illustrates a particular HVAC system having a processor connected to the control bus of FIG. 1 and being furthermore connected to an HVAC unit for providing conditioned air; 
     FIG. 3 illustrates the storage of information for the HVAC system of FIG. 2 in a memory associated with the processor of FIG. 2; 
     FIGS. 4A-4F illustrate a process executable by the processor of FIG. 2 for reading information from as well as writing information to the memory associated with the processor; and 
     FIG. 5 illustrates a look up table used by the processor in executing the process of FIGS. 4A-4F. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, an HVAC systems controller 10 is connected to an HVAC system 12 and an HVAC system 14 via a control bus 16. Each HVAC system receives control information from the HVAC systems controller 10 or, in the alternative, from a hand held remote control device 18. The HVAC system 12 receives the remote control signal at an infrared receiver 20 whereas the HVAC system 14 receives the remote control signal at an infrared receiver 22. The HVAC system 12 provides conditioned air through a ventilated opening 24 whereas the HVAC system 14 provides conditioned air via a ventilated opening 26. It is to be appreciated that there may be many more HVAC systems connected to the control bus 16. These HVAC systems may be installed in one large room or in several rooms of a building that is to be air conditioned by the various systems. Control information is normally provided to each individual system by the HVAC system controller 10 identifying a particular HVAC system through a network identification and thereafter communicating information to that particular system having that particular network identification. 
     Referring now to FIG. 2, the internal configuration of the HVAC system 12 is illustrated. A processor 28 within the HVAC system 12 receives control information from either the control bus 16 or from an infrared receiver interface 30 associated with the infrared receiver 20. Control information is received from either source in a predefined format. The formatted information is to be stored in a particular manner in a control memory 32 associated with the processor 28. The control memory 32 is preferably a non-volatile memory such as an electrically erasable programmable read only memory (EEPROM). Control information stored in such a memory will survive a power outage. The processor utilizes the stored control information in the memory 32 to control a particular HVAC unit 34 within the HVAC system 12. The HVAC unit 34 may be one of several different types of HVAC units. 
     Referring to the remote control device 18, this device is preferably programmed so as to scroll through various displayed network identifications upon depression of a selection button. The person depressing the selection button selects a particular displayed identification by releasing the selection button. The selected network identification is transmitted to the receiver 20 upon depression of another button. The signal coming from the remote control device will have a particular signal format that can be recognized by the programmed processor. In particular, the signal format will preferably begin with a header byte identifying the control parameter being transferred. The header byte will be followed by a byte containing the value of the network identification. The final byte will be a check sum of the header byte and the byte containing the value of the denoted control parameter. The infrared receiver interface 30 generates an interrupt pulse &#34;P&#34; to an interrupt input of the processor as the infrared signal is being received from the remote control. The infrared receiver interface generates pulses of encoded bits representing the aforementioned bytes from the infrared signal and sends these pulses to the processor following the interrupt pulse. The processor reads the header pulses defining the header byte as well as the data pulses defining the value of the network identification and the check sum pulses. The processor will store the header byte and the network identification value byte in a software buffer for later reading by the processor provided the check sum condition is satisfied. 
     It is to be appreciated that in addition to the above discussed receipt of the network identification, other control information can be similarly delivered to the processor 28 from either the systems controller 10 or the remote control device 18. In this regard, other pieces of control information having an identifiable header byte and a control parameter value byte and a check sum byte can be transmitted to and read by the processor 28 in the same manner as heretofore discussed for the network identification. 
     Referring now to FIG. 3, an example of how control information for the HVAC system 12 is to ultimately be stored in memory 32 is illustrated. The examplary control information is stored in addressable memory locations having address indexes numbered zero through eleven. It is to be understood that these address indexes can represent or easily be mapped to the particular addresses of these memory locations. Each addressable memory location has a stored control parameter value in a lower byte portion of the addressable location and a stored verification image value in each upper byte portion of the same addressable memory location. 
     The control parameter value for the network identification of the HVAC system 12 is preferably stored in the lower byte portions of three successive memory locations having address indexes nine through eleven. The verification image of this control parameter value is preferably stored in the upper byte portions of these memory locations. The verification images for each of the thus stored control parameter values are the twos complement of these stored control parameter values. 
     Referring now to FIG. 4A, a process for reading the various control parameter values stored in the memory 32 begins with a step 40 that indicates that electrical power has been provided to the processor 28. The processor 28 proceeds to a step 42 and sets the memory address index &#34;i&#34; equal to zero. The processor proceeds in steps 44 through 68 to successively read the upper and lower bytes from address locations zero through eight and compares these bytes for being in compliance with the particular mathematical relationship that is required for these bytes. In the event that the particular mathematical relationship is satisfied for a particular location, the processor will proceed to set a denoted variable equal to the lower byte of the memory location under examination. The processor preferably uses a look up table such as is set forth in FIG. 5 to identify the particular variable that is to be set equal to the lower byte of memory locations zero through five. This is not required for memory locations six through nine. In the event that the lower and upper bytes of all locations for a particular variable do not demonstrate an appropriate mathematical relationship when read, the processor proceeds to set the particular variable equal to a default value. 
     The processor will ultimately proceed from either step 64 or step 68 to a step 69 and set the memory address index &#34;i&#34; equal to nine. Inquiry is made in a step 70 as to whether the memory address index, &#34;i&#34; is equal to eleven. Since the memory address index will initially equal nine, the processor will proceed to a step 72 and read both the lower and upper bytes from the particular memory address location identified by this memory address index &#34;i&#34;. The processor proceeds in a step 74 to inquire whether the thus read upper byte from the memory address location &#34;i&#34; is equal to the twos compliment of the lower byte read from the same memory address location. 
     Referring to FIG. 3, the verification image stored in the upper byte portion of each addressable location identified by memory address indexes nine through eleven should be the twos compliment of the network identification value. The above will not be the case if the value of the network identification or its twos compliment verification image are not properly read from the memory location under examination. In this case, the processor 28 will proceed out of step 74 along the no path to a step 82 and increment the memory address index &#34;i&#34; by one. The processor will thereafter return to step 70 and again proceed to step 72 if the new memory address index does not equal eleven. Assuming that the memory address index has merely been incremented from nine to ten, the processor will proceed to step 74 and read the lower and upper bytes from the memory address location indicated by the memory address index &#34;i&#34; equal to ten. The processor will again inquire in step 74 as to whether the upper byte is equal to the twos compliment of the lower byte stored in this particular memory address location. Assuming that the network identification value and its ones compliment verification image is correctly read from this addressable location, the processor will proceed from step 74 to step 76 and inquire as to whether the lower byte is within a specific range of permissible values. The permissible range of values for the network identification will preferably be part of the look up table of FIG. 5 and hence can be immediately associated with the memory location from which the network identification was read. In the event that the lower byte from the addressable memory location identified by the current memory address index &#34;i&#34; is not within range, the processor will proceed along the no path out of step 76 and again increment the memory address index &#34;i&#34; in step 82 before returning to step 70. Assuming the memory address index has now been incremented to eleven, the processor will proceed to step 72 and again read the lower and upper bytes from the corresponding memory location. Inquiry will next be made as to whether the upper byte is equal to the twos compliment of the lower byte in step 74. Assuming a twos complement relationship of these values, the processor will proceed to step 76 and again inquire as to whether the lower byte is within the predetermined range of permissible values for the network identification. If the read value of the lower byte stored in memory storage location eleven is within range of the permissible values for the network identification parameter, the processor will proceed to a step 78 and set a flag variable denoted as VALID --  ID equal to true. It will thereafter set a variable denoted as NTWK --  ID equal to the lower byte value in a step 80. Referring to steps 84 and 86, it is to be noted that if all memory address locations having the memory address indexes nine through eleven do not have a properly stored and read network identification value and a corresponding twos compliment verification image, then the processor will proceed in step 84 to set the NTWK --  ID variable equal to a default value. The processor proceeds to step 86 wherein the flag variable VALID --  ID is set equal to false. 
     It is to be appreciated that as a result of potentially reading up to three storage locations having the memory address indexes nine through eleven, the processor will have had an opportunity to verify a correct reading of the upper and lower bytes from at least one of these storage locations. For any such verification, the processor will also need to find that the value of a verified lower byte is within the permissible range for the network identification stored in these locations. In such a case, the processor will have set the VALID --  ID flag variable equal to true in a step 78 and set the NTWK --  ID control variable equal to the value of the lower byte in the particular storage location which passed the successive tests of steps 74 and 76. In the event that none of the byte values read from the storage locations nine through eleven passed the steps dictated by steps 74 and 76, then the processor will have set the NTWK --  ID variable equal to a default value from the look up table in FIG. 5 and set the flag variable VALID --  ID equal to false. 
     The NTWK --  ID control variable will preferably appear in a communication protocol program executed by the processor 28 when it wishes to identify itself to the systems controller 10. In this regard, the systems controller 10 will have been programmed to query the HVAC systems 12 and 14 for a match of possible network identifications within a range of possible network identifications stored in the systems controller 10. This range will preferably correspond to the permitted range of values in step 76. When the systems controller sends out the particular network identification corresponding to the value of the NTWK --  ID variable, the HVAC system 12 will respond and identify itself as being the particular HVAC system having the assigned network identification. This allows the systems controller to thereafter effectively communicate with the HVAC system 12 using the particular network identification. 
     The processor will proceed out of either step 80 or step 86 to a step 88 wherein the flag variable noted as MEM --  WRIT will be set equal to true. The processor proceeds from setting MEM --  WRIT equal to true in step 88 to a step 90 wherein an inquiry is made as to whether MEM --  WRIT is equal to true. MEM --  WRIT will have been set equal to true in step 88 so as to thereby cause the processor to proceed to a step 92. As will become apparent hereinafter, the process beginning with step 92 is directed to writing values and respective verification images of values to the memory 32 under a variety of circumstances. 
     Referring to step 92, the memory address index &#34;i&#34; is set equal to zero. Another index &#34;j&#34; which will be used to track the number of write attempts to a particular memory location in the memory 32 is also set equal to zero. The processor proceeds in steps 94 through 132 to examine memory locations zero through eight to determine whether the read upper and lower bytes of each memory location have the required mathematical relationship. The processor proceeds to write the current value of the variable associated with the memory location if the same becomes necessary. This will occur if either the read upper and lower bytes do not satisfy the required mathematical relationship or the read lower byte does not equal the current value of the corresponding variable. At such time as the memory address index &#34;i&#34; equals nine, the processor will proceed from step 132 to a step 134. 
     Referring to step 134, the processor reads the lower and upper byte portions of the storage location indicated by the current memory address index &#34;i&#34;. The processor proceeds in a step 136 to inquire as to whether the upper byte portion of the memory location equals a twos compliment of the lower byte portion of the read memory location. Referring to FIG. 3, the upper byte value for a memory location having a memory address index of nine, ten or eleven should have a twos compliment verification image stored therein. If the read upper and lower bytes have this relationship in any memory location having one of the aforementioned address indexes, then the processor will proceed to a step 138 and inquire as to whether the lower byte value is equal to the present value of the NTWK --  ID control variable being used by the processor 28. In the event that the lower byte value read from the memory 32 at the particular address storage location does not equal the value of the NTWK --  ID control variable, the processor proceeds along the no path out of step 138 to a step 140. Referring again to step 136, in the event that the upper byte does not have the correct twos compliment relationship with the read lower byte value for any memory location having one of the address indexes of nine, ten or eleven, the processor will also proceed out of step 136 to step 140. 
     Referring to step 118, the processor inquires as to whether VALID --  ID equals true. It will be remembered from steps 72 through 78 that VALID --  ID will be true if the processor has previously successfully read and verified the relationship of upper byte to lower byte for at least one of the storage locations nine through eleven and has moreover verified that the lower byte is within a permissible range. Assuming that VALID --  ID is true, the processor will proceed along the yes path to a step 142 wherein the value of the NTWK --  ID variable in the processor 28 is written to the lower byte portion of the memory location identified by the current memory address index &#34;i&#34;. The processor now proceeds to step 144 and writes the twos compliment of the value of the NTWK --  ID variable in the processor 28 to the upper byte portion of the same memory location. The processor proceeds to set RE --  RUN equal to true in step 124. The write attempt index &#34;j&#34; is incremented by one in step 148 before proceeding to inquire in step 150 as to whether this write attempt index &#34;j&#34; is equal to five. If it is not, the processor will proceed back to step 134 and again read the lower and upper byte portions of the memory location identified by the memory address index &#34;i&#34;. To the extent that the write steps 142 and 144 were not previously successful or if the read step 134 is incorrect, the processor will so note in either step 136 or step 138. In either case, the processor will again implement steps 140 through 150 wherein another write will be attempted to this particular memory location. The processor will continue to attempt to write to this memory location until the write attempt index &#34;j&#34; equals five in step 150 or until the upper byte has the twos complement relationship to the lower byte as required in step 136 and the lower byte is equal to the present value of NTWK --  ID in the processor 28 as required in step 138. After any successful write has been verified in steps 136 and 138 or after five successive write attempts, the processor will proceed to a step 152 and increment the memory address index &#34;i&#34; by one and again set the write attempt index &#34;j&#34; equal to zero. The processor will next inquire in step 154 as to whether the memory address index &#34;i&#34; is equal to eleven. As long as the memory index address &#34;i&#34; has not been incremented to eleven, the processor will again re-execute steps 134 through 152 and attempt to verify that a correct value of NTWK --  ID has been written to the respective lower byte location and that the twos compliment thereof has been correctly written to the upper byte location. When all three memory address locations have been read and written to if necessary and thereafter verified or if the process has been attempted up to five times for each memory location, then the processor will proceed out of step 154 to a step 156. 
     Referring to step 156, the processor inquires whether the RE --  RUN flag is equal to true. This flag will have been set equal to true in either step 106, 124 or step 146 if there has been a write to any particular memory location. If this has occurred, the processor will proceed to a step 158 and set RE --  RUN equal to false. The processor thereafter proceeds to step 160 and inquires as to whether a communication has been received for any of the variables identified by variable index &#34;k&#34; numbered zero through five. It is to be understood that such a communication will be received in a recognizable format allowing the processor to store a header byte identifying the control parameter followed by a byte of information containing the value of the control parameter in a software buffer. The processor will read any received header bytes in the software buffer in step 160 and note whether any of the header byte codes identify a control parameter stored in one of the memory locations having an address index of zero through five. If a header byte code corresponds to any such control parameter, the processor will note the corresponding indexed &#34;k&#34; variable from the look up table in FIG. 5. 
     In the event that a communication has not been received for any of these variables, the processor will proceed to a step 168 and inquire as to whether a communication has been received for the UNIT --  TYPE control variable. This will be accomplished by examining the header bytes in the software buffer to ascertain whether any of these bytes identify a parameter value having been received for the UNIT --  TYPE control variable. 
     Assuming that no communications have been received for the UNIT --  TYPE control variable, the processor will proceed along the no path out of step 168 to a step 176 wherein inquiry is made as to whether a communication has been received for the NTWK --  ID variable. This will be accomplished by examining any header byte stored in the software buffer memory to ascertain whether any of these header bytes indicates that a network identification has been received from the remote control device 18. If a header byte code corresponds to the code for the network identification parameter, the processor will associate the corresponding NTWK --  ID variable therewith through the look up table in FIG. 5. The processor will proceed to set the NTWK --  ID variable equal to the stored network identification byte associated with this header byte in step 178 before proceeding to set MEM --  WRIT and VALID --  ID equal to true in steps 180 and 182. The processor will proceed to step 166 and hence back to step 90. The processor will now proceed through steps 92 through 136 as has been previously discussed and will possibly note that the lower byte of memory address location having a memory address index of nine will not equal the current value of the NTWK --  ID variable in a step 138. This will prompt the normal writing of the current value of the NTWK --  ID variable to the memory locations nine through eleven in steps 142 through 154. The RE --  RUN will be set equal to true in step 146 if this occurs. The processor will now proceed through steps 156 and 158 and set RE --  RUN equal to false. 
     Referring again to steps 160, 168 and 176, the processor will proceed along the no paths out of each of these steps if no communications have been received by the processor for any of the noted variables. The processor will proceed out of step 176 to step 166 and execute any control routines before again returning to step 90. Since MEM --  WRIT remains true, the processor will again proceed through steps 92 to 156. Assuming that all verifications are successfully made at the first reading of all upper and lower bytes from all memory locations, the processor will note that the RE --  RUN is false in step 156. This will prompt the processor to proceed to a step 184 and set MEM --  WRIT equal to false. Assuming no communications have been received for indexed variables zero through five or for the UNIT --  TYPE or NTWK --  ID control variables, the processor will proceed through steps 160, 168 and 176 to step 90. Since MEM --  WRIT is now false, the processor will proceed along the no path out of step 90 to step 160. It is to be appreciated that the processor will continue to execute only steps 160, 168, 176, 166 and hence go back to step 90 until a communication has been received for any monitored variable. Any change in value of any variable associated with the memory locations having memory address indexes zero through eleven will prompt the reading and writing to either the single memory location for variables zero through five or the three designed memory locations for the UNIT --  TYPE control variable or the three designated memory locations for the NTWK --  ID variable. This reading and writing should result in a unique verification image being written to three separate memory locations for the UNIT --  TYPE control variable and the three separate memory locations for the NTWK --  ID variable. In the event such readings and writings are subject to a high electrical noise environment, then readings followed by writings will occur up to five successive times for each memory location. When repeated reading and writings are required to any of these locations, the processor will continue to note that a rerun condition is present and hence the entire process will be repeated until all memory locations are correctly read and verified the first time. 
     Referring again to step 40 in the event that power is turned off or lost at any time, the processor will note when power is again turned on. The processor will proceed to set the indexed variables associated with the memory locations having memory address indexes zero through five equal to read lower byte portions of these respective locations in steps 44 through 50. The processor will proceed next to steps 52 through 68 and examine as many of the addressable memory locations having memory address indexes of six through eight as is necessary to pass the tests dictated by steps 56 and 60. When a pair of upper and lower byte portions of one of these memory locations have the appropriate ones complement relationship required in step 56 and when the lower byte of the same location is within range in step 60, the processor will proceed to step 64 and set the UNIT --  TYPE variable equal to the value of the lower byte portion of the particular memory location. In the event that none of the addressable memory locations have upper and lower byte portions that will pass the tests dictated by steps 56 and 60, the processor will proceed to step 66 and set the UNIT --  TYPE variable equal to a default value. 
     Referring to steps 70 through 86, the processor will proceed to examine as many of the addressable memory locations having memory address indexes of nine through eleven as is necessary to pass the tests dictated by steps 74 and 76. This should normally result in the NTWK --  ID variable being set equal to the lower byte portion of the first addressable memory location which passes the tests dictated by steps 74 and 76. If no such memory locations pass these tests, then the NTWK --  ID variable is set equal to the default value in step 84. 
     It is to be appreciated from the above that a process has been disclosed for accurately reading and writing the values of NTWK --  ID and the UNIT --  TYPE variable to a number of memory locations associated with each variable. The writing of the values of these variables is also accompanied by a corresponding writing of the verification image to second portions of the same memory locations. A writing to any of these locations is accompanied by a reading of all memory locations wherein values have been stored to verify that the values and corresponding verification images of all variables have been correctly stored. Readings followed by writings will continue to occur until all recorded values and respective verification images can be read without any error. 
     It is to be appreciated that a particular embodiment of the invention has been described. Alterations, modifications and improvements thereto will readily occur to those skilled in the art. Accordingly, the foregoing description is by way of example only and the invention is to be limited only by the following claims and equivalents thereto.