Abstract:
A receiving apparatus includes: a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data; a storing means for storing the decoded data; a second decoding means for applying decoding processing employing the outer code to the decoded data; and a control means for controlling storage and output of the decoded data in and from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a receiving apparatus, a receiving method, a computer program, and a receiving system, and, more particularly to a receiving apparatus, a receiving method, a computer program, and a receiving system that make it possible to prevent a loss of data when frame data in which an inner code and an outer code are used as error correction codes is decoded. 
         [0003]    2. Description of the Related Art 
         [0004]    As a standard of the terrestrial digital broadcast, there is the DVB-T2 standard (the Second-Generation European Terrestrial Digital Broadcast Standard). The DVB-T2 standard is described in a so-called BlueBook (DVB BlueBook A122) (DVB BlueBook A122 Rev. 1, Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2), Sep. 1, 2008, Web Page of DVB, [retrieved on Aug. 5, 2009], Internet &lt;URL: http://www.dvb.org/technology/standards/&gt;). 
         [0005]    In a transmission system of the DVB-T2 standard, a concatenated code of an inner code and an outer code is used as an error correction code. In the DVB-T2 standard, an LDPC code is used as the inner code and a BCH code is used as the outer code. 
         [0006]    An apparatus on a reception side first applies LDPC decoding processing to received data to be decoded and, thereafter, applies BCH decoding processing to the data. The apparatus once stores data of a result of the LDPC decoding processing in a buffer and applies the BCH decoding processing to the data stored in the buffer. The buffer in which the data obtained as a result of the LDPC decoding processing is stored is hereinafter referred to as LDPC output buffer as appropriate. 
       SUMMARY OF THE INVENTION 
       [0007]      FIG. 1  is a diagram of a structure example of a code frame (FECFRAME) specified by the DVB-T2 standard. 
         [0008]    As shown in  FIG. 1 , one code frame includes BBFRAME, BCHFEC, and LDPCFEC. In the DVB-T2 standard, as code frames having such a structure, a Normal frame and a Short frame having different frame lengths are specified. 
         [0009]      FIGS. 2A and 2B  are diagrams of encoding parameters of the Normal frame and the Short frame. The encoding parameters shown in  FIGS. 2A and 2B  are the same as those described in the standard V1.2.0c Table 5(a), (b). 
         [0010]    As shown in  FIG. 2A , concerning the Normal frame, for example, when an LDPC code rate is 1/2, LDPC code length is 64800 bits and BCH code length is 32400 bits. The LDPC code length is equivalent to the length of BBFRAME, BCHFEC, and LDPCFEC as shown in  FIG. 1 . The BCH code length is equivalent to the length of BBFRAME and BCHFEC as shown in  FIG. 1 . 
         [0011]    As shown in  FIG. 2B , concerning the Short frame, for example, when the LDPC code rate is 1/2, the LDPC code length is 16200 bits and the BCH code length is 7200 bits. 
         [0012]    As a capacity of the LDPC output buffer, at least 54000 bits as a maximum data amount likely to be stored in the LDPC output buffer is secured. When the LDPC code rate of the Normal frame is ⅚, the BCH code length is 54000 bits, which is the maximum data amount likely to be stored in the LDPC output buffer. 
         [0013]    Such a Normal frame or a Short frame is sequentially input to an error-correction processing unit of the receiving apparatus. The Normal frame and the Short frame are frequently switched. Parameters of the code frames are complicatedly transmitted. Therefore, for example, the code length of a BCH code input to a BCH code decoder also frequently changes. This means that time necessary for BCH decoding processing frequently changes. 
         [0014]      FIG. 3  is a diagram of an example of input timing of code frames. 
         [0015]    Time t 1  in  FIG. 3  represents timing when data of a decoding result of a first Normal frame is output from a LDPC code decoder to the LDPC output buffer. Time t 2  represents timing when data of a decoding result of a second Normal frame is output from the LDPC code decoder to the LDPC output buffer. 
         [0016]    Time t 3  represents timing when data of a decoding result of a first Short frame input following the second Normal frame is output from the LDPC code decoder to the LDPC output buffer. Time t 4  and subsequent times respectively represent timings when data of decoding results of second and subsequent Short frames are output from the LDPC code decoder to the LDPC output buffer. 
         [0017]    Time necessary for output of data of an LDPC decoding result is substantially proportional to a data amount of a code frame to be subjected to LDPC decoding processing. For example, time from time t 1  to time t 2  is time necessary for output of data of an LDPC decoding result of the first Normal frame. Time from time t 3  to time t 4  is time necessary for output of data of an LDPC decoding result of the first Short frame. 
         [0018]    Therefore, as shown in  FIG. 3 , when a code frame to be input is switched from a Normal frame to a Short frame, situations explained below occur because a frame interval of the Short frame is short compared with a frame interval of the Normal frame. 
       Situation 1 
       [0019]    While data of a Normal frame is output from the LDPC output buffer to the BCH code decoder, when data of the next Short frame is output from the LDPC code decoder to the LDPC output buffer, a loss of the frames occur because of overwrite of a control signal. 
         [0020]    Control signals including parameters used for decoding of code frames are added to the code frames as attribute information. The control signals are output from the LDPC code decoder to the LDPC output buffer together with data of the code frames and stored in the LDPC output buffer. For example, when a control signal for a Normal frame stored in the LDPC output buffer is overwritten with data of the next Short frame output from the LDPC code decoder, it is difficult to perform the BCH decoding or the like of the Normal frame and a loss of the frames occur. 
       Situation 2 
       [0021]    When, although output of data of a Normal frame from the LDPC output buffer to the BCH code decoder is completed, data of plural Short frames are continuously output from the LDPC code decoder to the LDPC output buffer during BCH decoding processing for the Normal frame, a loss of the frames occurs because of overwrite of the data of the Short frame and a control signal. 
         [0022]    It is conceivable to prepare an LDPC output buffer having a large capacity or prepare plural LDPC output buffers in order to prevent such a loss of frames. However, this is disadvantageous in terms of cost. 
         [0023]    Therefore, it is desirable to make it possible to prevent a loss of data when frame data in which an inner code and an outer code are used as error correction codes is decoded. 
         [0024]    According to an embodiment of the present invention, there is provided a receiving apparatus including: a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data; a storing means for storing the decoded data; a second decoding means for applying decoding processing employing the outer code to the decoded data output from the storing means; and a control means for controlling storage of the decoded data in the storing means and output of the decoded data from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data transmitted following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means. 
         [0025]    The frame data can be data of a Normal frame or data of a Short frame specified in DVB-T2. 
         [0026]    Four storage areas in which the decoded data of a decoding result of data of a singularity of the Normal frame can be stored over the plural areas or the decoded data of a decoding result of data of a singularity of the Short frame can be stored in each of the areas can be provided in the storing means. 
         [0027]    The first frame data can be the data of the Normal frame and the second frame data can be the data of the Short frame. In this case, while the control means causes the storing means to output the first decoded data to the second decoding means, when the first decoding means starts the output of the second decoded data, the control means can cause a singularity of the storage area, in which the first decoded data finished to be output is stored, to store the second decoded data. 
         [0028]    According to the embodiment, there is also provided a receiving method for a receiving apparatus including a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data, a storing means for storing the decoded data, and a second decoding means for applying decoding processing employing the outer code to the decoded data output from the storing means, the receiving method including the step of: controlling storage of the decoded data in the storing means and output of the decoded data from the storing means to suspend, while causing the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data transmitted following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means. 
         [0029]    According to the embodiment, there is also provided a computer program for causing a computer to execute processing for a receiving apparatus including a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data, a storing means for storing the decoded data, and a second decoding means for applying decoding processing employing the outer code to the decoded data output from the storing means, the computer program causing the computer to execute processing including the step of: controlling storage of the decoded data in the storing means and output of the decoded data from the storing means to suspend, while causing the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data transmitted following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means. 
         [0030]    According to another embodiment of the present invention, there is provided a receiving system including: an acquiring means for acquiring a signal transmitted via a transmission channel; and a transmission channel decoding processing means for applying processing including error correction processing to the signal acquired by the acquiring means, wherein the transmission channel decoding processing means includes a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data, a storing means for storing the decoded data, a second decoding means for applying decoding processing employing the outer code to the decoded data output from the storing means, and a control means for controlling storage of the decoded data in the storing means and output of the decoded data from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data transmitted following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means. 
         [0031]    According to still another embodiment of the present invention, there is provided a receiving system including: a transmission channel decoding processing means for applying processing including error correction processing to a signal acquired via a transmission channel; and an information source decoding processing means for applying processing for decoding transmission target data to the signal processed by the transmission channel decoding processing means, wherein the transmission channel decoding processing means includes a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data, a storing means for storing the decoded data, a second decoding means for applying decoding processing employing the outer code to the decoded data output from the storing means, and a control means for controlling storage of the decoded data in the storing means and output of the decoded data from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data transmitted following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means. 
         [0032]    According to yet another embodiment of the present invention, there is provided a receiving system including: a transmission channel decoding processing means for applying processing including error correction processing to a signal acquired via a transmission channel; and an output means for outputting an image or sound on the basis of the signal processed by the transmission channel decoding processing means, wherein the transmission channel decoding processing means includes a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data, a storing means for storing the decoded data, a second decoding means for applying decoding processing employing the outer code to the decoded data output from the storing means, and a control means for controlling storage of the decoded data in the storing means and output of the decoded data from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data transmitted following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means. 
         [0033]    According to still yet another embodiment of the present invention, there is provided a receiving system including: a transmission channel decoding processing means for applying processing including error correction processing to a signal acquired via a transmission channel; and a recording means for recording the signal processed by the transmission channel decoding processing means, wherein the transmission channel decoding processing means includes a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data, a storing means for storing the decoded data, a second decoding means for applying decoding processing employing the outer code to the decoded data output from the storing means, and a control means for controlling storage of the decoded data in the storing means and output of the decoded data from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data transmitted following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means. 
         [0034]    In the embodiments of the present invention, the control means controls storage of the decoded data in the storing means and output of the decoded data from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data transmitted following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means. 
         [0035]    According to the embodiments of the present invention, it is possible to prevent a loss of data when frame data in which an inner code and an outer code are used as error correction codes is decoded. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0036]      FIG. 1  is a diagram of a structure example of a code frame specified by the DVB-T2 standard; 
           [0037]      FIGS. 2A and 2B  are diagrams of encoding parameters for a Normal frame and a Short frame; 
           [0038]      FIG. 3  is a diagram of an example of input timing of code frames; 
           [0039]      FIG. 4  is a block diagram of a configuration example of an error correction processing unit provided in a receiving apparatus according to an embodiment of the present invention; 
           [0040]      FIG. 5  is a diagram of an example of code frames input to the error correction processing unit; 
           [0041]      FIG. 6  is a diagram of an example of states of a data buffer; 
           [0042]      FIG. 7  is a diagram of another example of the states of the data buffer; 
           [0043]      FIG. 8  is a diagram of an example of a timing chart of flags; 
           [0044]      FIG. 9  is a diagram of another example of the timing chart of the flags; 
           [0045]      FIG. 10  is a diagram of a configuration example of a control signal buffer; 
           [0046]      FIG. 11  is a flowchart for explaining processing by an LDPC decoding unit; 
           [0047]      FIG. 12  is a flowchart for explaining processing by a BCH decoding unit; 
           [0048]      FIG. 13  is a flowchart for explaining storage control processing by a buffer controller; 
           [0049]      FIG. 14  is a flowchart for explaining output control processing by the buffer controller; 
           [0050]      FIG. 15  is a block diagram of a configuration example a first embodiment of a receiving system; 
           [0051]      FIG. 16  is a block diagram of a configuration example of a second embodiment of the receiving system; 
           [0052]      FIG. 17  is a block diagram of a configuration example of a third embodiment of the receiving system; and 
           [0053]      FIG. 18  is a block diagram of a configuration example of a fourth embodiment of the receiving system. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     [Configuration Example of an Error Correction Processing Unit] 
       [0054]      FIG. 4  is a block diagram of a configuration example of an error correction processing unit  1  provided in a receiving apparatus according to an embodiment of the present invention. 
         [0055]    As shown in  FIG. 4 , the error correction processing unit  1  includes an LDPC decoding unit  11 , an LDPC output buffer  12 , a BCH decoding unit  13 , and a buffer controller  14 . The receiving apparatus including the error correction processing unit  1  is, for example, a receiving apparatus for a broadcast wave of the DVB-T2 standard. An A/D conversion circuit that converts a reception signal into digital data, a demodulation circuit that performs demodulation processing and equalization processing, and the like are provided at a pre-stage of the error correction processing unit  1 . 
         [0056]    Data of code frames having the structure shown in  FIG. 1  obtained by the processing performed in the A/D conversion circuit, the demodulation circuit, and the like and a control signal as attribute information of the code frames are input to the LDPC decoding unit  11 . 
         [0057]    In the control signal, besides the LDPC code rate, the LDPC code length, and the BCH code length shown in  FIGS. 2A and 2B , parameters used for processing in a circuit at a post-stage of the error correction processing unit  1  are also included. The LDPC decoding unit  11  and the BCH decoding unit  13  respectively perform processing according to the parameters included in the control signal. 
         [0058]    The LDPC decoding unit  11  applies, every time data of one code frame (a Normal frame or a Short frame) is input, LDPC decoding processing to the input data and sequentially outputs data of a decoding result to the LDPC output buffer  12 . The “data” output from the LDPC decoding unit  11  is data of a decoding result of the LDPC decoding processing. The LDPC decoding unit  11  outputs the control signal to the LDPC output buffer  12 . 
         [0059]    When the LDPC decoding unit  11  starts the LDPC decoding processing for a certain code frame, the LDPC decoding unit  11  outputs a code frame start flag f 1  that is a signal indicating that the LDPC decoding processing is started. While the LDPC decoding unit  11  is outputting data of the code frame to the LDPC output buffer  12 , the LDPC decoding unit  11  outputs a data valid flag f 2  that is a signal indicating that the data is output. The code frame start flag f 1  and the data valid flag f 2  output from the LDPC decoding unit  11  are supplied to the buffer controller  14 . 
         [0060]    The LDPC output buffer  12  includes a data buffer  21  and a control signal buffer  22 . The data buffer  21  stores the data supplied from the LDPC decoding unit  11 . The control signal buffer  22  stores the control signal supplied from the LDPC decoding unit  11 . 
         [0061]    The buffer controller  14  controls writing (storage) of the data and the control signal in the data buffer  21  and the control signal buffer  22  or readout (output) of the data and the control signal stored in the data buffer  21  and the control signal buffer  22 . 
         [0062]    The LDPC output buffer  12  is a RAM (Random Access Memory), data writing in which and data readout from which may be unable to be simultaneously performed. The data readout is disabled when the data writing is performed. The data writing is disabled when the data readout is performed. Details of the writing of the data and the control signal in the LDPC output buffer  12  and the readout of the data and the control signal stored in the LDPC output buffer  12  are explained later. 
         [0063]    When a code frame start flag f 4  is supplied from the buffer controller  14 , the BCH decoding unit  13  sequentially receives data output from the data buffer  21  and stores the data in an internal buffer  31 . The code frame start flag f 4  is a signal indicating that output of data of a certain code frame stored in the data buffer  21  is started. 
         [0064]    The storage of the data in the internal buffer  31  is continued while a data valid flag f 5  is supplied from the buffer controller  14 . The data valid flag f 5  is a signal indicating that the data of the code frame is output from the LDPC output buffer  12 . 
         [0065]    After starting the reception of the data output from the data buffer  21 , the BCH decoding unit  13  starts output of an in-decoding flag f 3  that is a signal indicating that BCH decoding processing for the code frame is being performed. The in-decoding flag f 3  output from the BCH decoding unit  13  is supplied to the buffer controller  14 . 
         [0066]    When the storage of the data of the code frame (data to be subjected to the BCH decoding processing) in the internal buffer  31  is completed, the BCH decoding unit  13  applies the BCH decoding processing to the data and sequentially outputs data of a decoding result to a circuit at a post-stage. When the BCH decoding processing for the code frame ends, the BCH decoding unit  13  ends the output of the in-decoding flag f 3 . 
         [0067]    The BCH decoding unit  13  receives the control signal output from the control signal buffer  22  and outputs the control signal to the circuit at the post-stage at timing same as timing for outputting the data of the BCH decoding result. 
         [0068]    As explained above, in the error correction processing unit  1 , the LDPC output buffer  12  that stores an output of the LDPC decoding unit  11  is prepared and a configuration for transferring data for one code word of an LDPC code (one code frame) to the BCH decoding unit  13  after storing the data in the LDPC output buffer  12  is adopted. Consequently, the internal buffer  31  for one code word of a BCH code only has to be prepared in the BCH decoding unit  13 . 
         [0069]    Since the BCH decoding unit  13  includes only the buffer for one code word, the BCH decoding unit  13  outputs the in-decoding flag f 3  while the BCH decoding unit  13  is performing the BCH decoding processing. While the in-decoding flag f 3  is output, data of a LDPC decoding result of the next code frame of a code frame subjected to the BCH decoding is not output from the LDPC output buffer  12  to the BCH decoding unit  13 . 
       [Timing for Writing and Readout of Data] 
       [0070]    Timing for storage of data in the data buffer  21  and output of data stored in the data buffer  21  performed according to control by the buffer controller  14  is explained below. The control signal is explained later. 
         [0071]      FIG. 5  is a diagram of an example of code frames input to the error correction processing unit  1 . 
         [0072]    As shown in  FIG. 5 , following a predetermined code frame, a Normal frame NF 0  and Short frames SF 0  to SF 3  are input to the error correction processing unit  1  in order and processing is performed. 
         [0073]    At timing when a code frame to be input is switched from a Normal frame to a Short frame, as explained above, in some case, a loss of frames occur because, for example, data of the Short frame is output to the LDPC output buffer before processing of the Normal frame is completed. 
         [0074]    In the error correction processing unit  1 , while data of a Normal frame is output from the data buffer  21 , when output of data of an LDPC decoding result of a Short frame as the next code frame of the Normal frame is started in the LDPC decoding unit  11 , the output of the data of the Normal frame is suspended and the data of the Short frame is preferentially stored in the data buffer  21 . When the storage of the data of the Short frame is completed, the suspended output of the data of the Normal frame is resumed. 
         [0075]    An entire storage area of the data buffer  21  is divided into plural areas. Storage of data or output of data can be controlled for each of the areas. 
         [0076]      FIG. 6  is a diagram of an example of areas formed in the data buffer  21 . 
         [0077]    When LDPC code rates are the same, a ratio of code lengths of a BCH code of a Normal frame and a BCH code of a Short frame is about 4:1 ( FIGS. 2A and 2B ). A capacity of the data buffer  21  is secured according to the code length of the Normal frame. Therefore, it can be said that areas for four frames are present in terms of the code length of the Short frame. 
         [0078]    Therefore, the entire storage area of the data buffer  21  is divided into four areas A 1  to A 4 . A BCH code of one Short frame can be stored in each of the areas and a BCH code of one Normal frame can be stored over the plural areas. 
         [0079]    The data buffer  21  at the left end of  FIG. 6  indicates a state in which storage of data of the Normal frame NF 0  is completed. Data output from the LDPC decoding unit  11  by the LDPC decoding processing applied to the Normal frame NF 0  are stored in the areas A 1 , A 2 , A 3 , and A 4  in order. The data buffer  21  changes to a state shown at the left end of  FIG. 6 . 
         [0080]    After the storage of the data of the Normal frame NF 0  is completed, output of the data of the Normal frame NF 0  is started. The output data of the Normal frame NF 0  are sequentially received by the BCH decoding unit  13 . The output of the data is performed, for example, in order of the storage of the data. 
         [0081]    The data buffer  21  shown at the destination of an arrow # 1  in  FIG. 6  indicates a state in which the output of the data of the Normal frame NF 0  is performed halfway. When output of the data stored in the area A 2  is completed following the data stored in the area A 1  and output of the data stored in the area A 3  is performed halfway, the data buffer  21  changes to the state shown at the destination of the arrow # 1  in  FIG. 6 . 
         [0082]    While the output of the data of the Normal frame NF 0  is performed, the LDPC decoding unit  11  starts the LDPC decoding processing for the Short frame SF 0  input following the Normal frame NF 0 . Data of a decoding result of the LDPC decoding processing for the Short frame SF 0  are sequentially output from the LDPC decoding unit  11  to the data buffer  21 . 
         [0083]    For example, when the output of the data of the decoding result of the LDPC decoding processing for the Short frame SF 0  is started in the state shown at the destination of the arrow # 1 , the output of the data of the Normal frame NF 0  is suspended and storage of the data of the Short frame SF 0  supplied from the LDPC decoding unit  11  is started. The data of the Short frame SF 0  is written in, for example, the area A 1  of the areas A 1  and A 2  that are areas in which the data of the Normal frame NF 0  is stored. 
         [0084]    The data buffer  21  shown at the destination of an arrow # 2  in  FIG. 6  indicates a state in which the storage of the data of the Short frame SF 0  is completed. When the storage of the data of the Short frame SF 0  is completed, the suspended output of the data of the Normal frame NF 0  is resumed. Output of the data of the Normal frame NF 0  stored in the area A 4  is performed following the data of the Normal frame NF 0  stored in the area A 3 . 
         [0085]    After the output of the data of the Normal frame NF 0  is completed, the BCH decoding unit  13  starts the BCH decoding processing for the Normal frame NF 0 . While the BCH decoding processing for the Normal frame NF 0  is performed, the BCH decoding unit  13  outputs the in-decoding flag f 3 . While the in-decoding flag f 3  is output, output of data of the Short frame SF 0  and subsequent code frames stored in the data buffer  21  is not performed. 
         [0086]    While the in-decoding flag f 3  is output from the BCH decoding unit  13 , the LDPC decoding unit  11  performs the LDPC decoding processing for the Short frames SF 1 , SF 2 , and SF 3 . Data of LDPC decoding results of the Short frames output from the LDPC decoding unit  11  are sequentially written in a free area of the data buffer  21 . 
         [0087]      FIG. 7  is a diagram of states in which data of the Short frames SF 1 , SF 2 , and SF 3  are stored following the Short frame SF 0 . 
         [0088]    The data buffer  21  at the left end of  FIG. 7  indicates a state in which in which output of the data of the Normal frame NF 0  is completed. When the output of the data of the Normal frame NF 0  stored in the areas A 3  and A 4  of the data buffer  21  shown at the destination of the arrow # 2  in  FIG. 6  is completed, only the data of the Short frame SF 0  is stored in the area A 1 . 
         [0089]    Data of an LDPC decoding result of the Short frame SF 1  output from the LDPC decoding unit  11  is stored in, for example, the area A 2  that is a free area of the data buffer  21 . 
         [0090]    The data buffer  21  shown at the destination of an arrow # 1  in  FIG. 7  indicates a state in which storage of the data of the Short frame SF 1  is completed. 
         [0091]    It is assumed that the BCH decoding processing for the Normal frame NF 0  is not completed in the BCH decoding unit  13  and the output of the in-decoding flag f 3  is continued. Data output from the LDPC decoding unit  11  according to the LDPC decoding processing for the Short frames SF 2  and SF 3  are sequentially written in the free areas A 3  and A 4  of the data buffer  21 . 
         [0092]    The data buffer  21  shown at the destination of an arrow # 12  in  FIG. 7  indicates a state in which storage of the data of the Short frames SF 2  and SF 3  is completed. 
         [0093]    When the BCH decoding processing for the Normal frame NF 0  is completed in the BCH decoding unit  13  and the output of the in-decoding flag f 3  ends, the data of the Short frames are output from the LDPC output buffer  12  in order of the storage of the data. The BCH decoding unit  13  applies the BCH decoding processing to the data. 
         [0094]    In this way, in the error correction processing unit  1 , the storage area of the LDPC output buffer  12  is divided into four. While data of a Normal frame is output from the LDPC output buffer, when the LDPC decoding unit  11  outputs data of a Short frame, the output of the data of the Normal frame is suspended and the data of the Short frame is stored in a free area from which the output of the data of the Normal frame ends. After the data of the Short frame is stored, the output of the data of the Normal frame is resumed, whereby a loss of the code frames can be prevented. 
         [0095]    A writing area is adaptively controlled as shown in  FIG. 7 , whereby data of maximum four Short frames can be stored in the data buffer  21 . 
         [0096]      FIG. 8  is a diagram of a timing chart of flags output from the units when a code frame to be input is switched from a Normal frame to a Short frame. 
         [0097]    Time t 11  is timing when output of data of an LDPC decoding result of the Normal frame NF 0  is started. At time t 11 , the LDPC decoding unit  11  outputs the code frame start flag f 1 . 
         [0098]    At time t 11 , output of the data valid flag f 2  indicating that the output of the data of the Normal frame NF 0  is performed is started. The data of the Normal frame NF 0  output from the LDPC decoding unit  11  at time t 11  and subsequent times are sequentially stored in the data buffer  21 . 
         [0099]    Time t 12  is timing when the output of the data of the Normal frame NF 0  from the LDPC decoding unit  11  is completed. At time t 12 , the output of the data valid flag f 2  is ended. A state shown at the left end of  FIG. 6  indicates a state of the data buffer  21  at time t 12 . 
         [0100]    At time t 12 , the buffer controller  14  outputs the code frame start flag f 4  and output of the data valid flag f 5  indicating that the output of the data of the Normal frame NF 0  is performed is started. Data of the Normal frame NF 0  output from the data buffer  21  at time t 12  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0101]    The BCH decoding unit  13  that starts reception of the data of the Normal frame NF 0  outputs the in-decoding flag f 3  at timing immediately after the time t 12 . 
         [0102]    Time t 13  is timing when the LDPC decoding processing is applied to the Short frame SF 0  input following the Normal frame NF 0  and output of data of an LDPC decoding result is started. At time t 13 , the LDPC decoding unit  11  outputs the code frame start flag f 1 . 
         [0103]    At time t 13 , output of the data valid flag f 2  indicating that the output of the data of the Short frame SF 0  is performed is started. Data of the Short frame SF 0  output from the LDPC decoding unit  11  at time t 13  and subsequent times are sequentially stored in the data buffer  21 . 
         [0104]    According to the start of the storage of the data of the Short frame SF 0  at time t 13 , the output of the data of the Normal frame NF 0  from the data buffer  21  and the output of the data valid flag f 5  performed so far are ended. In other words, the output of the data of the Normal frame NF 0  is suspended. The state shown at the destination of the arrow # 1  in  FIG. 6  indicates a state of the data buffer  21  at time t 13 . 
         [0105]    Time t 14  is timing when the output of the data of the Short frame SF 0  from the LDPC decoding unit  11  is completed. At time t 14 , the output of the data valid flag f 2  is ended. The state shown at the destination of the arrow # 2  in  FIG. 6  indicates a state of the data buffer  21  at time t 14 . 
         [0106]    At time t 14 , output of the data valid flag f 5  indicating that the output of the data of the Normal frame NF 0  is performed is started. In other words, the output of the data of the Normal frame NF 0  is resumed. Data of the Normal frame NF 0  output from the data buffer  21  at time t 14  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0107]    Time t 15  is timing when output of data of an LDPC decoding result of the Short frame SF 1  input following the Short frame SF 0  is started. At time t 15 , the LDPC decoding unit  11  outputs the code frame start flag f 1 . 
         [0108]    At time t 15 , output of the data valid flag f 2  indicating that the output of the data of the Short frame SF 1  is performed is started. Data of the Short frame SF 1  output from the LDPC decoding unit  11  at time t 15  and subsequent times are sequentially stored in the data buffer  21 . 
         [0109]    According to the start of the storage of the data of the Short frame SF 1  at time t 15 , the output of the data of the Normal frame NF 0  from the data buffer  21  and the output of the data valid flag f 5  performed so far are ended. In other words, the output of the data of the Normal frame NF 0  is suspended again. 
         [0110]    In this example, the output of the data of the Normal frame NF 0  stored in the data buffer  21  is suspended at the timing when the output of the data of the Short frame SF 0  is started and the timing when the output of the data of the Short frame SF 1  is started. 
         [0111]    Time t 16  is timing when the output of the data of the Short frame SF 1  from the LDPC decoding unit  11  is completed. At time t 16 , the output of the data valid flag f 2  is ended. 
         [0112]    At time t 16 , output of the data valid flag f 5  indicating that the output of the data of the Normal frame NF 0  is performed is started. In other words, the output of the data of the Normal frame NF 0  is resumed. Data of the Normal frame NF 0  output from the data buffer  21  at time t 16  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0113]    Time t 17  is timing when the output of the data of the Normal frame NF 0  from the data buffer  21  is completed. At time t 17 , the output of the data valid flag f 5  is ended. The BCH decoding processing applied to the data of the Normal frame NF 0  is started at time t 17 . 
         [0114]    Time t 18  is timing when the BCH decoding processing for the Normal frame NF 0  ends. At time t 16 , the output of the in-decoding flag f 3  is ended. 
         [0115]    At time t 16 , the buffer controller  14  outputs the code frame start flag f 4  and output of the data valid flag f 5  indicating that the output of the data of the Short frame SF 0  is performed is started. Data of the Short frame SF 0  output from the data buffer  21  at time t 16  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0116]    The BCH decoding unit  13  that starts reception of the data of the Short frame SF 0  outputs the in-decoding flag f 3  at timing immediately after time t 18 . 
         [0117]    Time t 19  is timing when the output of the data of the Short frame SF 0  from the data buffer  21  is completed. At time t 19 , the output of the data valid flag f 5  is ended. The BCH decoding processing applied to the data of the Short frame SF 0  is started at time t 19 . 
         [0118]    Time t 20  is timing when the BCH decoding processing for the Short frame SF 0  ends. At time t 20 , the output of the in-decoding flag f 3  is ended. 
         [0119]    At time t 20 , the buffer controller  14  outputs the code frame start flag f 4  and output of the data valid flag f 5  indicating that the output of the data of the Short frame SF 1  is performed is started. Data of the Short frame SF 1  output from the data buffer  21  at time t 20  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0120]    The BCH decoding unit  13  that starts reception of the data of the Short frame SF 1  outputs the in-decoding flag f 3  at timing immediately after time t 20 . 
         [0121]    Time t 21  is timing when the output of the data of the Short frame SF 1  from the data buffer  21  is completed. At time t 21 , the output of the data valid flag f 5  is ended. The BCH decoding processing applied to the data of the Short frame SF 1  is started at time t 21 . 
         [0122]      FIG. 9  is a diagram of a timing chart of flags output from the units when the Short frames SF 0  to SF 3  are input following the Normal frame NF 0 . 
         [0123]    Time t 31  is timing when the output of the data of the Normal frame NF 0  from the data buffer  21  is completed. At time t 31 , the output of the data valid flag f 5  is ended. The BCH decoding processing applied to the data of the Normal frame NF 0  is started at time t 31 . 
         [0124]    In  FIG. 9 , timing for output of the data of the Normal frame NF 0  from the LDPC decoding unit  11 , timing for output from the data buffer  21 , and the like are not shown. The in-decoding flag f 3  indicating that the BCH decoding processing for the Normal frame NF 0  is being performed is output before time t 31 . 
         [0125]    Time t 32  is timing when output of data of an LDPC decoding result of the Short frame SF 0  is started. At time t 32 , the code frame start flag f 1  is output from the LDPC decoding unit  11 . 
         [0126]    At time t 32 , output of the data valid flag f 2  indicating that the output of the data of the Short frame SF 0  is performed is started. Data of the Short frame SF 0  output from the LDPC decoding unit  11  at time t 32  and subsequent times are sequentially stored in the data buffer  21 . 
         [0127]    Time t 33  is timing when the output of the data of the Short frame SF 0  from the LDPC decoding unit  11  is completed. At time t 33 , the output of the data valid flag f 2  is ended. The state shown at the left end of  FIG. 7  indicates a state of the data buffer  21  at time t 33 . 
         [0128]    Time t 34  is timing when output of data of an LDPC decoding result of the Short frame SF 1  is started. At time t 34 , the LDPC decoding unit  11  outputs the code frame start flag f 1 . 
         [0129]    At time t 34 , output of the data valid flag f 2  indicating that the output of the data of the Short flag SF 1  is performed is started. Data of the Short frame SF 1  output from the LDPC decoding unit  11  at time t 34  and subsequent times are sequentially stored in the data buffer  21 . 
         [0130]    Time t 35  is timing when the output of the data of the Short frame SF 1  from the LDPC decoding unit  11  is completed. At time t 35 , the output of the data valid flag f 2  is ended. The state shown at the destination of the arrow # 11  in  FIG. 7  indicates a state of the data buffer  21  at time t 35 . 
         [0131]    Time t 36  is timing when output of data of an LDPC result of the Short frame SF 2  is started. At time t 36 , the LDPC decoding unit  11  outputs the code frame start flag f 1 . 
         [0132]    At time t 36 , output of the data valid flag f 2  indicating that the output of the data of the Short frame SF 2  is performed is started. Data of the Short frame SF 2  output from the LDPC decoding unit  11  at time t 36  and subsequent times are sequentially stored in the data buffer  21 . 
         [0133]    Time t 37  is timing when the output of the data of the Short frame SF 2  from the LDPC decoding unit  11  is completed. At time t 37 , the output of the data valid flag f 2  is ended. 
         [0134]    Time t 38  is timing when output of data of an LDPC decoding result of the Short frame SF 3  is started. At time t 38 , the LDPC decoding unit  11  outputs the code frame start flag f 1 . 
         [0135]    At time t 38 , output of the data valid flag f 2  indicating that the output of the data of the Short frame SF 3  is performed is started. Data of the Short frame SF 3  output from the LDPC decoding unit  11  at time t 38  and subsequent times are sequentially stored in the data buffer  21 . 
         [0136]    Time t 39  is timing when the output of the data of the Short frame SF 3  from the LDPC decoding unit  11  is completed. At time t 39 , the output of the data valid flag f 2  is ended. 
         [0137]    The data of the Short frames output from the LDPC decoding unit  11  at the timings explained above during the BCH decoding processing of the Normal frame NF 0  are stored in the areas of the data buffer  21  as shown at the destination of the arrow # 12  in  FIG. 7 . 
         [0138]    Time t 40  is timing when the BCH decoding processing for the Normal frame NF 0  ends. At time t 40 , the output of the in-decoding flag f 3  is ended. 
         [0139]    At time t 40 , the buffer controller  14  outputs the code frame start flag f 4  and output of the data valid flag f 5  indicating that the output of the data of the Short frame SF 0  is performed is started. Data of the Short frame SF 0  output from the data buffer  21  at time t 40  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0140]    The BCH decoding unit  13  that starts reception of the data of the Short frame SF 0  outputs the in-decoding flag f 3  at timing immediately after time t 40 . 
         [0141]    Time t 41  is timing when the output of the data of the Short frame SF 0  from the data buffer  21  is completed. At time t 41 , the output of the data valid flag f 5  is ended. The BCH decoding processing applied to the data of the Short frame SF 0  is started at time t 41 . 
         [0142]    Time t 42  is timing when the BCH decoding processing for the Short frame SF 0  ends. At time t 42 , the output of the in-decoding flag f 3  is ended. 
         [0143]    At time t 42 , the buffer controller  14  outputs the code frame start flag f 4  and output of the data valid flag f 5  indicating that the output of the data of the Short frame SF 1  is performed is started. Data of the Short frame SF 1  output from the data buffer  21  at time t 42  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0144]    The BCH decoding unit  13  that starts reception of the data of the Short frame SF 1  outputs the in-decoding flag f 3  at timing immediately after time t 42 . 
         [0145]    Time t 43  is timing when the output of the data of the Short frame SF 1  from the data buffer  21  is completed. At time t 43 , the output of the data valid flag f 5  is ended. The BCH decoding processing applied to the data of the Short frame SF 1  is started at time t 43 . 
         [0146]    Time t 44  is timing when the BCH decoding processing for the Short frame SF 1  ends. At time t 44 , the output of the in-decoding flag f 3  is ended. 
         [0147]    At time t 44 , the buffer controller  14  outputs the code frame start flag f 4  and output of the data valid flag f 5  indicating that the output of the data of the Short frame SF 2  is performed is started. Data of the Short frame SF 2  read out from the data buffer  21  at time t 44  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0148]    The BCH decoding unit  13  that starts the reception of the data of the Short frame SF 2  outputs the in-decoding flag f 3  at timing immediately after time t 44 . 
         [0149]    Time t 45  is timing when the output of the data of the Short frame SF 2  from the data buffer  21  is completed. At time t 45 , the output of the data valid flag f 5  is ended. The BCH decoding processing applied to the data of the Short frame SF 2  is started at time t 45 . 
         [0150]    Time t 46  is timing when the BCH decoding processing for the Short frame SF 2  ends. At time t 46 , the output of the in-decoding flag f 3  is ended. 
         [0151]    At time t 46 , the buffer controller  14  outputs the code frame start flag f 4  and output of the data valid flag f 5  indicating that the output of the data of the Short frame SF 3  is performed is started. Data of the Short frame SF 3  read out from the data buffer  21  at time t 46  and subsequent times are sequentially stored in the internal buffer  31  of the BCH decoding unit  13 . 
         [0152]    The BCH decoding unit  13  that starts reception of the data of the Short frame SF 3  outputs the in-decoding flag f 3  at timing immediately after time t 46 . 
         [0153]    Time t 47  is timing when the output of the data of the Short frame SF 3  from the data buffer  21  is completed. At time t 47 , the output of the data valid flag f 5  is ended. The BCH decoding processing applied to the data of the Short SF 3  is started at time t 47 . 
       [Timing for Writing and Readout of a Control Signal] 
       [0154]      FIG. 10  is a diagram of an example of areas formed in the control signal buffer  22 . 
         [0155]    Like the data buffer  21 , an entire storage area of the control signal buffer  22  is divided into four areas A 11  to A 14 . A control signal for one code frame can be stored in each of the areas. When the Short frames SF 0  to SF 3  are stored in the areas A 1  to A 4  of the data buffer  21  as shown in  FIG. 7 , control signals for the Short frames SF 0  to SF 3  are respectively stored in the areas A 11  to A 14  of the control signal buffer  22 . 
         [0156]    At timing same as the timing for outputting the code frame start flag f 1 , i.e., timing for starting output of data of an LDPC decoding result of a certain code frame, the LDPC decoding unit  11  outputs a control signal for the code frame. Control signals output from the LDPC decoding unit  11  are sequentially stored in a free area of the control signal buffer  22 . 
         [0157]    The control signals stored in the control signal buffer  22  are output, in order of the storage, timing when the code frame start flag f 4  is output, i.e., output of data of a certain code frame from the data buffer  21  is started. The control signal buffer  22  is a memory of a FIFO (First In First Out) format. The control signals output from the control signal buffer  22  are received by the BCH decoding unit  13  and output to a circuit at a post-stage at timing same as timing for outputting data of a BCH decoding result. 
         [0158]    For example, output of data of the code frames and storage of the data are performed at the timings explained with reference to  FIG. 8 . In this case, a control signal for the Normal frame NF 0  is output from the LDPC decoding unit  11  at time t 11  and stored in, for example, the area A 11  that is a free area of the control signal buffer  22 . The control signal for the Normal frame NF 0  stored in the area A 11  is output to the BCH decoding unit  13  at time t 12 . 
         [0159]    The control signal for the Short frame SF 0  is output from the LDPC decoding unit  11  at time t 13  and stored in, for example, the area A 11  that is a free area of the control signal buffer  22 . 
         [0160]    A control signal for the Short frame SF 1  is output from the LDPC decoding unit  11  at time t 15  and stored in, for example, the area A 12  that is a free area of the control signal buffer  22 . At time t 15 , the control signal for the Short frame SF 0  is already stored in the area A 11 . 
         [0161]    The control signal for the Short frame SF 0  stored in the area A 11  is output to the BCH decoding unit  13  at time t 18 . The control signal of the Short frame SF 1  stored in the area A 12  is output to the BCH decoding unit  13  at time t 20 . 
         [0162]    In this way, the control signals are output from the LDPC decoding unit  11  in synchronization with the data of the code frames and stored in the control signal buffer  22 . After being temporarily stored in the control signal buffer  22 , the control signals are supplied to the BCH decoding unit  13  in synchronization with the data of the code frames. 
       [Operations of the Units] 
       [0163]    The operations of the LDPC decoding unit  11 , the BCH decoding unit  13 , and the buffer controller  14  that process data of code frames are explained below. Kinds of processing explained below are repeatedly performed in parallel in the units. 
         [0164]    First, processing by the LDPC decoding unit  11  is explained with reference to a flowchart shown in  FIG. 11 . This processing is performed every time data of each of the code frames is input. 
         [0165]    In step S 1 , the LDPC decoding unit  11  receives data of an input code frame. 
         [0166]    In step S 2 , the LDPC decoding unit  11  outputs the code frame start flag f 1  (outputs a value  1 ). 
         [0167]    In step S 3 , the LDPC decoding unit  11  starts output of the data valid flag f 2 . 
         [0168]    In step S 4 , the LDPC decoding unit  11  applies the LDPC decoding processing to the input code frame and outputs data of a decoding result. 
         [0169]    In step S 5 , the LDPC decoding unit  11  determines whether the LDPC decoding processing for the code frame to be subjected to the LDPC decoding processing ends. When the LDPC decoding unit  11  determines that the LDPC decoding processing does not end, the LDPC decoding unit  11  returns to step S 4  and repeats the LDPC decoding processing. 
         [0170]    On the other hand, when the LDPC decoding unit  11  determines in step S 5  that the LDPC decoding processing for the code frame to be subjected to the LDPC decoding processing ends, in step S 6 , the LDPC decoding unit  11  ends the output of the data valid flag f 2  (starts output of a value 0) and ends the processing. 
         [0171]    Processing by the BCH decoding unit  13  is explained below with reference to a flowchart shown in  FIG. 12 . 
         [0172]    In step S 11 , the BCH decoding unit  13  determines whether the code frame start flag f 4  is supplied (whether a value of the code frame start flag f 4  is  1 ). The BCH decoding unit  13  stays on standby until the BCH decoding unit  13  determines that the code frame start flag f 4  is supplied. 
         [0173]    When the BCH decoding unit  13  determines in step S 11  that the code frame start flag f 4  is supplied, in step S 12 , the BCH decoding unit  13  starts output of the in-decoding flag f 3 . 
         [0174]    In step S 13 , the BCH decoding unit  13  receives data supplied from the data buffer  21  and causes the internal buffer  31  to store the data. 
         [0175]    In step S 14 , the BCH decoding unit  13  determines whether the data valid flag f 5  is supplied. When the BCH decoding unit  13  determines that the data valid flag f 5  is supplied, the BCH decoding unit  13  returns to step S 13  and continues storage of data supplied from the data buffer  21 . 
         [0176]    On the other hand, when the BCH decoding unit  13  determines in step S 14  that the data valid flag f 5  is not supplied (a value of the data valid flag f 5  is 0), in step S 15 , the BCH decoding unit  13  determines whether data for one frame is stored in the internal buffer  31 . 
         [0177]    When the BCH decoding unit  13  determines in step S 15  that the data for one frame is not stored in the internal buffer  31 , the BCH decoding unit  13  returns to step S 14  and repeats the same processing. When the output of data from the data buffer  21  to the BCH decoding unit  13  is suspended because output of data of an LDPC decoding result of the next code frame is started, even if a value of the data valid flag f 5  is 0, the BCH decoding unit  13  determines that the data for one frame is not stored in the internal buffer  31 . 
         [0178]    On the other hand, when the BCH decoding unit  13  determines in step S 15  that the data for one frame is stored in the internal buffer  31 , in step S 16 , the BCH decoding unit  13  applies the BCH decoding processing to the data stored in the internal buffer  31  and outputs data of a decoding result. 
         [0179]    In step S 17 , the BCH decoding unit  13  determines whether the BCH decoding processing for the code frame to be subjected to the BCH decoding processing ends. When the BCH decoding unit  13  determines that the BCH decoding processing does not end, the BCH decoding unit  13  returns to step S 16  and repeats the BCH decoding processing. 
         [0180]    When the BCH decoding unit  13  determines instep S 17  that the BCH decoding processing for the code frame to be subjected to the BCH decoding processing ends, in step S 18 , the BCH decoding unit  13  ends the output of the in-decoding flag f 3  and ends the processing. 
         [0181]    Processing by the buffer controller  14  for controlling storage of data in the data buffer  21  is explained below with reference to a flowchart shown in  FIG. 13 . 
         [0182]    The processing shown in  FIG. 13  is started when the code frame start flag f 1  is supplied. When the code frame start flag f 1  is supplied while processing shown in  FIG. 14  explained later is performed, the processing shown in  FIG. 13  is performed in an interruptive manner. 
         [0183]    In step S 31 , the buffer controller  14  determines whether the data valid flag f 5  is output. 
         [0184]    When the buffer controller  14  determines in step S 31  that the data valid flag f 5  is output, in step S 32 , the buffer controller  14  ends the output of the data valid flag f 5 . For example, when the processing shown in  FIG. 13  is started in an interruptive manner while data is output from the data buffer  21  to the BCH decoding unit  13 , the buffer controller  14  determines that the data valid flag f 5  is output. When the buffer controller  14  determines in step S 31  that the data valid flag f 5  is not output, step S 32  is skipped. 
         [0185]    In step S 33 , the buffer controller  14  causes the data buffer  21  to store data of an LDPC decoding result output from the LDPC decoding unit  11  in a free area of the data buffer  21 . 
         [0186]    In step S 34 , the buffer controller  14  determines whether the data valid flag f 2  is supplied from the LDPC decoding unit  11 . 
         [0187]    When the buffer controller  14  determines in step S 34  that the data valid flag f 2  is supplied, the buffer controller  14  returns to step S 33  and repeatedly causes the data buffer  21  to store data of an LDPC decoding result. When the buffer controller  14  determines in step S 34  that the data valid flag f 2  is not supplied, the buffer controller  14  ends the processing. 
         [0188]    Processing by the buffer controller  14  for controlling output of data stored in the data buffer  21  to the BCH decoding unit  13  is explained below with reference to a flowchart shown in  FIG. 14 . 
         [0189]    The processing shown in  FIG. 14  is started when data for one frame is stored in the data buffer  21 . 
         [0190]    Instep S 51 , the buffer controller  14  determines whether the in-decoding flag f 3  is supplied from the BCH decoding unit  13 . The buffer controller  14  stays on standby until the buffer controller  14  determines that the in-decoding flag f 3  is not supplied. 
         [0191]    When the buffer controller  14  determines in step S 51  that the in-decoding flag f 3  is not supplied, in step S 52 , the buffer controller  14  outputs the code frame start flag f 4 . 
         [0192]    In step S 53 , the buffer controller  14  starts output of the data valid flag f 5 . 
         [0193]    In step S 54 , the buffer controller  14  outputs the data of the code frame to be output stored in the data buffer  21 . 
         [0194]    In step S 55 , the buffer controller  14  determines whether all the data of the code frame to be output are output. When the buffer controller  14  determines that not all of the data are output, the buffer controller  14  returns to step S 54  and repeats the output of data. 
         [0195]    On the other hand, when the buffer controller  14  determines in step S 55  that all the data of the code frame to be output are output, in step S 56 , the buffer controller  14  ends the output of the data valid flag f 5  and ends the processing. 
         [0196]    Since the processing explained above is performed in the units, it is possible to prevent a loss of code frames. 
         [0197]    In the case mainly explained above, a code frame to be input is switched from a Normal frame to a Short frame. However, when the code frame to be input is switched from the Short frame to the Normal frame, since a frame interval of the Normal frame is long compared with a frame interval of the Short frame, it is not particularly necessary to perform processing for, for example, suspending the output of data from the data buffer  21 . 
         [0198]    The processing for code frames of the DVB-T2 standard is explained above. However, the present invention is also applicable when data of other code frames in which a concatenated code of an inner code and an outer code is used as an error correction code and plural code frame lengths are specified is processed. 
       [Modifications] 
       [0199]      FIG. 15  is a block diagram of a configuration example of a first embodiment of a receiving system to which the error correction processing unit  1  is applied. 
         [0200]    The receiving system shown in  FIG. 15  includes an acquiring unit  101 , a transmission channel decoding processing unit  102 , and an information source decoding processing unit  103 . 
         [0201]    The acquiring unit  101  acquires a signal via a not-shown transmission channel such as a terrestrial digital broadcast, a satellite digital broadcast, a CATV network, the Internet, or other networks and supplies the signal to the transmission channel decoding processing unit  102 . 
         [0202]    The transmission channel decoding processing unit  102  applies transmission channel decoding processing including error correction to the signal acquired by the acquiring unit  101  via the transmission channel and supplies a signal obtained as a result of the transmission channel decoding processing to the information source decoding processing unit  103 . The error correction processing unit  1  shown in  FIG. 4  is included in the transmission channel decoding processing unit  102 . 
         [0203]    The information source decoding processing unit  103  applies, to the signal subjected to the transmission channel decoding processing, information source decoding processing including processing for expanding compressed information to original information and acquiring transmission target data. 
         [0204]    In some case, compression encoding for compressing information is applied to the signal acquired by the acquiring unit  101  via the transmission channel in order to reduce data amounts of an image, sound, and the like. In that case, the information source decoding processing unit  103  applies, to the signal subjected to the transmission channel decoding processing, the information source decoding processing such as the processing for expanding compressed information to original information. 
         [0205]    When the compression encoding is not applied to the signal acquired by the acquiring unit  101  via the transmission channel, the information source decoding processing unit  103  does not perform the processing for expanding compressed information to original information. As the expansion processing, for example, there is MPEG decoding. In some case, the information source decoding processing includes descrambling or the like besides the expansion processing. 
         [0206]    The receiving system shown in  FIG. 15  can be applied to, for example, a television tuner that receives a digital television broadcast. Each of the acquiring unit  101 , the transmission channel decoding processing unit  102 , and the information source decoding processing unit  103  can be configured as one independent apparatus (hardware (an IC (Integrated Circuit), etc.)) or a software module). 
         [0207]    A set of the acquiring unit  101 , the transmission channel decoding processing unit  102 , and the information source decoding processing unit  103  can be configured as one independent apparatus. A set of the acquiring unit  101  and the transmission channel decoding processing unit  102  can be configured as one independent apparatus. A set of the transmission channel decoding processing unit  102  and the information source decoding processing unit  103  can also be configured as one independent apparatus. 
         [0208]      FIG. 16  is a block diagram of a configuration example of a second embodiment of the receiving system to which the error correction processing unit  1  is applied. 
         [0209]    Among components shown in  FIG. 16 , components corresponding to the components shown in  FIG. 15  are denoted by the same reference numerals and explanation of the components is omitted as appropriate. 
         [0210]    The configuration of the receiving system shown in  FIG. 16  is the same as the configuration shown in  FIG. 15  in that the receiving system includes the acquiring unit  101 , the transmission channel decoding processing unit  102 , and the information source decoding processing unit  103 . The configuration of the receiving system is different from the configuration shown in  FIG. 15  in that an output unit  111  is provided anew. 
         [0211]    The output unit  111  is, for example, a display device that displays an image or a speaker that outputs sound. The output unit  111  outputs an image, sound, or the like output from the information source decoding processing unit  103  as a signal. In other words, the output unit  111  displays an image or outputs sound. 
         [0212]    The receiving system shown in  FIG. 16  can be applied to, for example, a television that receives a television broadcast provided as a digital broadcast or a radio receiver that receives a radio broadcast. 
         [0213]    When the compression encoding is not applied to a signal acquired by the acquiring unit  101 , a signal output by the transmission channel decoding processing unit  102  is directly supplied to the output unit  111 . 
         [0214]      FIG. 17  is a block diagram of a configuration example of a third embodiment of the receiving system to which the error correction processing unit  1  is applied. 
         [0215]    Among components shown in  FIG. 17 , components corresponding to the components shown in  FIG. 15  are denoted by the same reference numerals and explanation of the components is omitted. 
         [0216]    The configuration of the receiving system shown in  FIG. 17  is the same as the configuration shown in  FIG. 15  in that the receiving system includes the acquiring unit  101  and the transmission channel decoding processing unit  102 . The configuration of the receiving system is different from the configuration shown in  FIG. 15  in that a recording unit  121  is provided anew. 
         [0217]    The recording unit  121  records a signal (e.g., a TS packet of TS of MPEG) output by the transmission channel decoding processing unit  102  in a recording (storage) medium such as an optical disk, a hard disk (a magnetic disk), or a flash memory (causes the recording medium to store the signal). 
         [0218]    The receiving system shown in  FIG. 17  can be applied to a recorder apparatus or the like that records a television broadcast. 
         [0219]    It is also possible that the information source decoding processing unit  103  is provided and the recording unit  121  records a signal subjected to the information source decoding processing by the information source decoding processing unit  103 , i.e., an image or sound obtained by decoding. 
         [0220]    The series of processing explained above can be executed by hardware or can be executed by software. When the series of processing is executed by the software, a computer program forming the software is installed in a computer incorporated in a dedicated hardware, a general-purpose personal computer, or the like from a program recording medium. 
         [0221]      FIG. 18  is a block diagram of a configuration example of hardware of a computer that executes the series of processing according to a computer program. 
         [0222]    A CPU (Central Processing Unit)  151 , a ROM (Read Only Memory)  152 , and a RAM (Random Access Memory)  153  are connected to one another by a bus  154 . 
         [0223]    An input and output interface  155  is further connected to the bus  154 . An input unit  156  including a keyboard or a mouse and an output unit  157  including a display or a speaker are connected to the input and output interface  155 . A storing unit  158  including a hard disk or a nonvolatile memory, a communication unit  159  including a network interface, and a drive  160  that drives a removable medium  161  are connected to the input and output interface  155 . 
         [0224]    In the computer configured as explained above, the CPU  151  loads, for example, a computer program stored in the storing unit  158  to the RAM  153  via the input and output interface  155  and the bus  154  and executes the computer program, whereby the series of processing is performed. 
         [0225]    The computer program executed by the CPU  151  is provided while being recorded in, for example, the removable medium  161  or via a wired or wireless transmission medium such as a local area network, the Internet, or a digital broadcast and installed in the storing unit  158 . 
         [0226]    The computer program executed by the computer may be a computer program in which the processing is performed in time series according to the order explained in this specification or may be a computer program in which the processing is performed in parallel or at necessary timing such as timing when the computer program is invoked. 
         [0227]    Embodiments of the present invention are not limited to the embodiments explained above. Various modifications of the embodiments are possible without departing from the spirit of the present invention. 
         [0228]    The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2009-247757 filed in the Japan Patent Office on Oct. 28, 2009, the entire contents of which is hereby incorporated by reference.