Abstract:
A motherboard includes a first signal module and a second signal module, a first switch module and a second switch module, a first enable module and a second enable module, an input interface, and a control module. The control module outputs different control signal to the first and second switch modules. The first switch is used to connect the first enable module to the first signal module or to the input interface corresponding to the control signals. The second switch is used to connect the second enable module to the second signal module or to the input interface corresponding to the control signals.

Description:
FIELD 
       [0001]    The subject matter herein generally relates to a motherboard with multiple chips. 
       BACKGROUND 
       [0002]    When needing to be programmed, a chip on a motherboard should be removed first. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
           [0004]      FIG. 1  is a circuit diagram of an embodiment of a motherboard. 
           [0005]      FIG. 2  is a circuit diagram of power terminals of the motherboard in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0006]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure. 
         [0007]    Several definitions that apply throughout this disclosure will now be presented. 
         [0008]    The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently coupled or releasably coupled. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
         [0009]    The disclosure will now be described in relation to an electronic device with a power switch system. 
         [0010]      FIG. 1  shows an embodiment of a motherboard  100 . The motherboard  100  can comprise a first signal module  11 , a second signal module  12 , a first switch module  21 , a second switch module  22 , a first enable module  31 , a second enable module  32 , an input interface  40  and a control module  50 . 
         [0011]    A first signal terminal of the first switch module  21  is coupled to a first signal terminal of the first signal module. A first signal of the second switch module  22  is coupled to a first signal terminal of the second signal module  12 . A third signal module of the second switch module  22  is coupled to a third terminal of the first switch module  21 . 
         [0012]    The first signal terminal of the first enable module  31  is coupled to the second signal terminal of the first switch module  21 . A first signal terminal of the second enable module  32  is coupled to a second signal terminal of the second switch module  22 . 
         [0013]    The input interface  40  is coupled to a first input terminal of the first switch module  21 . The input interface  40  is coupled to a first input terminal of the second switch module  22 . 
         [0014]    The control module  50  is coupled to a third signal terminal of the first switch module  21 . The control module  50  is also coupled to a third signal terminal of the second switch module  22 . When the control module  50  outputs a first control signal to the first switch module  21 , the second signal terminal of the first switch module  21  is coupled to the first signal terminal of the first switch module  21 . When the control module  50  outputs a second control signal to the first switch module  21 , the second signal terminal of the first switch module  21  is coupled to the third signal terminal of the first switch module  21 . 
         [0015]    When the control module  50  outputs the first control signal to the second switch module  22 , the second signal terminal of the second switch module  22  is coupled to the first signal terminal of the second switch module  22 . When the control module  50  outputs the second control signal to the second switch module  22 , the second signal terminal of the second switch module  22  is coupled to the third signal terminal of the second switch module  22 . 
         [0016]    In the embodiment, the first switch module  21  can comprise a first switch chip U 1 . The second switch module  22  can comprise a second switch chip U 2 . The first enable module  31  can comprise a first enable chip U 3 . The second enable module  32  can comprise a second enable chip U 4 . 
         [0017]    A signal pin  1  of the first switch chip U 1  is coupled to a signal pin  1  of the first signal module  11 . A signal pin  2  of the first switch chip U 1  is coupled to a signal pin  2  of the first enable chip U 3 . A signal pin  3  of the first switch chip U 1  is coupled to a signal pin  3  of the second switch chip U 2 . The signal pin  3  of the first switch chip U 1  is also coupled to a signal pin  1  of the input interface  40 . A ground pin  4  of the first switch chip U 1  is grounded through a resistor R 1 . The ground pin  4  of the first switch chip U 1  is also coupled to a signal pin  1  of the control module  50 . A power pin  5  of the first switch chip U 1  is coupled to a power terminal V 1 . 
         [0018]    A signal pin  1  of the second switch chip U 2  is coupled to a signal pin  1  of the first signal module  11 . A signal pin  2  of the second switch chip U 2  is coupled to a signal pin  2  of the second enable chip U 4 . A ground pin  4  of the second switch chip U 2  is grounded through a resistor R 2 . The ground pin  4  of the second switch chip U 2  is also coupled to a signal pin  3  of the control module  50 . A power pin  5  of the second switch chip U 2  is coupled to the power terminal V 1 . 
         [0019]    A power pin  2  of the input interface  40  is coupled to a power terminal V 2 . A ground pin  3  of the input interface  40  is grounded. 
         [0020]    A power pin  2  of the control module  50  is coupled to the power terminal V 2 . 
         [0021]    A power pin  1  of the first enable chip U 3  is coupled to a power terminal V 3 . A ground pin  3  of the first enable chip U 3  is grounded. 
         [0022]    A power pin  1  of the second enable chip U 4  is coupled to a power terminal V 3 . A ground pin  3  of the second enable chip U 4  is grounded. 
         [0023]    In the embodiment, the first enable chip U 3  and the second enable chip U 4  are flash memory chips. The first enable chip U 3  can be programmed to enable the first signal module  11 . The second enable chip U 4  can be programmed to enable the second signal module  12 . 
         [0024]    When the input interface  40  is coupled to a programmer, the power terminal V 2  receives a voltage from the programmer. The signal pin  1  of the input interface  40  receives a signal for programming. The power pin  2  of the control module  50  receives the voltage from the programmer. 
         [0025]    When the input interface  40  is not coupled to the programmer, the power terminal V 2  does not receive the voltage. The ground pin  4  of the first switch chip U 1  is grounded through the resistor R 1 . The ground pin  4  of the first switch chip U 1  is at a low level. The signal pin  1  of the first switch chip U 1  is coupled to the signal pin  2  of the first switch chip U 2 . The ground pin  4  of the second switch chip U 2  is grounded through the resistor R 2 . The ground pin  4  of the second switch chip U 2  is at a low level. The signal pin  1  of the second switch chip U 2  is coupled to the signal pin  2  of the second switch chip U 2 . 
         [0026]    When the first enable chip U 3  is to be programmed, the power pin  2  of the control module  50  is coupled to the signal pin  1  of the control module  50 . The ground pin  4  of the first switch chip U 1  is at a high level. The signal pin  1  of the first switch chip U 1  is coupled to the signal pin  3  of the first switch chip U 1 . The signal for programming is transmitted to the first enable chip U 3  through the first switch chip U 1 . 
         [0027]    When the second enable chip U 3  is to be programmed, the power pin  2  of the control module  50  is coupled to the signal pin  3  of the control module  50 . The ground pin  4  of the second switch chip U 2  is at a high level. The signal pin  1  of the switch chip U 2  is coupled to the signal pin  3  of the second switch chip U 2 . The signal for programming is transmitted to the second enable chip U 4  through the second switch chip U 2 . 
         [0028]      FIG. 2  shows an embodiment of the power terminals V 1 -V 3  of the motherboard in  FIG. 1 . The power terminal V 2  is grounded through a resistor R 3  and a resistor R 4  in that order. A node A between the resistor R 3  and the resistor R 4  is coupled to a grid of a field effect transistor (FET) Q 1 . A source of the FET Q 1  is grounded. A drain of FET Q 1  is coupled to the power terminal Q 1  through a resistor R 5 . The drain of the FET Q 1  is also coupled to a grid of a FET Q 2 . A drain of the FET Q 2  is coupled to the power terminal V 3 . A source of the FET Q 2  is coupled to a cathode of a diode D. An anode of the diode D is coupled to the power terminal V 2 . 
         [0029]    When the power terminal V 2  does not receive the voltage from the programmer, the grid of the FET Q 1  is at a low level. The source of the FET Q 1  is disconnected from the drain of the FET Q 1 . The power terminal V 1  outputs a high level signal to the grid of the FET Q 2 . The source of the FET Q 2  is coupled to the drain of the FET Q 2 . The power terminal V 3  receives a voltage from the power terminal V 1 . 
         [0030]    When the power terminal V 2  receives the voltage from the programmer, the grid of the FET Q 1  is at a high level. The drain of the FET Q 1  is coupled to the source of the FET Q 1 . The power terminal V 1  is grounded through the resistor R 5 . The grid of the FET Q 2  is at a low level. The source of the FET Q 2  is disconnected from the drain of the FET Q 2 . The power terminal V 2  outputs the voltage from the programmer to the power terminal V 3  through the diode D. 
         [0031]    In the embodiment, the control module  50  is a jumper. In other embodiments, the control module  50  can be a single-pole double-throw switch. 
         [0032]    In the embodiment, the FET Q 1  is an n-channel FET. The FET Q 2  is an n-channel FET. 
         [0033]    While the disclosure has been described by way of example and in terms of the embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.