Abstract:
A line-driver receives as an input a Manchester-encoded digital data signal, which is then converted into an analog signal by a wave-shaping circuit. The wave-shaping circuit comprises a bank of current sources with a combined output, each current source being actuated by a switch controlled by a switching signal. The current sources are each scaled by a coefficient, and are actuated in a selected sequence during each input data pulse, thereby generating as a combined output a staircase pulse signal with n steps for each input data pulse.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to improvements in analog finite impulse response (FIR) based line-drivers, and more particularly to advantageous aspects of an analog-FIR-based filter embedded in a line-driver, by which wave-shaping, filtering and pre-equalization for the data stream are implemented. 
     2. Description of the Prior Art 
     According to the international standard ISO/IEC 8802-3 (ANSI/IEEE std 802-3, clause 14.3.1.2.1), any harmonics of a transmitted signal for an all-ones Manchester (return-to-zero) encoded signal have to be at least 27 dB below the fundamental, which in a 10 Base-T system is 10 MHz. For a 5 MHz signal (periodic “10” or “01” binary data), the high-frequency components of the signal have to be enhanced, thus increasing the transmission distance. This is typically called “pre-equalization.” The amount of the pre-equalization should be such that the eye-diagram of the signal at the output of the twisted-pair model (ISO 8802.3) stays inside the voltage template shown in FIG. 14-9 of ISO 8802-3. In addition, it is required that the signal amplitude for a 100 Ω resistive load stay between 2.2 V to 2.8 V (i.e., 2.5 V±12%). 
     FIG. 1 shows a known configuration, in which the preceding requirements are met by a four-pin driver requiring four off-chip resistors and a differential off-chip filter (ATT1MX10 data sheet, August 1997). It is possible to integrate the transmit filters onto the chip by using continuous-time techniques, such as a Gm-C filter technique. However, the cut-off frequencies of continuous-time filters move from their desired value due to process and temperature conditions. To maintain the cut-off frequency of the continuous-time filter, a process plus temperature tuning mechanism has to be employed. Furthermore, designing a continuous-time filter to accommodate a large output swing (5 V peak-to-peak±12%) with a power supply of 5 V±10% is very difficult and expensive. In addition, to accommodate the pre-equalization, a second parallel continuous-time filter is required, or at least the input-stage of the filter has to be replicated. This has the disadvantage of increasing the power consumption of the driver. 
     SUMMARY OF THE INVENTION 
     The present invention integrates an analog finite impulse response (FIR) filter and a pre-equalization function for high-speed data communication. These functions are advantageously embedded within a line driver. 
     In a preferred embodiment, the line-driver receives as an input a Manchester-encoded digital data signal, which is then converted into an analog signal by a wave-shaping circuit. The wave-shaping circuit comprises a bank of current sources with a combined output, each current source being actuated by a switch controlled by a switching signal. The current sources are each scaled by a coefficient, and are actuated in a selected sequence during each input data pulse, thereby generating as a combined output a staircase pulse signal with n steps for each input data pulse. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a diagram of a prior-art four-pin line driver. 
     FIG. 2 shows a diagram of a model of the wave-shaping and filtering blocks for a line driver according to the present invention. 
     FIG. 3 shows a graph of the FIR filter output for the maximum Manchester-encoded input data pulse rate, i.e., where the input data is all-ones or all-zeros. 
     FIG. 4 shows the main structure of an FIR DAC according to the present invention, using only N-channel devices. 
     FIG. 5 shows a graph of the control signals for the circuit of FIG. 4 for generating the output shown in FIG.  3 . 
     FIG. 6 shows an FIR DAC main circuit according to the present invention, using complementary P-channel and N-channel devices. 
     FIG. 7 shows a graph of the control signals for the circuit of FIG. 6 for generating the output shown in FIG.  3 . 
     FIG. 8 shows a graph of a pre-equalization approach in according with the present invention. 
     FIG. 9 shows an FIR DAC circuit according to the present invention for implementing the pre-equalization scheme shown in FIG.  8 . 
     FIG. 10 shows a graph of the control signals for the FIG. 9 circuit for generating the pre-equalized output shown in FIG.  8 . 
    
    
     DETAILED DESCRIPTION 
     The disclosure in Barraclough, U.S. Pat. No. 5,739,707, issuing from U.S. patent application Ser. No. 08/685,080, owned by the same assignee as the present invention, is hereby incorporated by reference. 
     FIG. 2 shows a model for an analog-FIR-based filter according to the present invention for use in a 10 Base-T driver. The input  10  to the filter is signal x(t), which is Manchester-encoded bipolar (±1) pulse, which is a bipolar representation for digital HIGH and LOW levels (hereafter represented as HI and LO) for the input signal. FIR filter  12 , combined with zero-order hold circuit  14 , generates as an output a staircase pulse with T s  sec time intervals (resolution) from each Manchester-encoded pulse. The wave-shaped signal travels through n steps from 0 V to +1 V or to −1 V (normalized) at the start of transmission. Then, depending on the input data, the signal can travel from one peak to another through n steps within a 50 ns period. Alternatively, the signal can experience some droop for pre-equalization, as discussed below. The staircase pulse signal output of the FIR filter  12  is then converted to a continuous waveform analog output  18  by a smoothing filter circuit  16 . 
     The n-step levels are chosen such that the all-ones (or all-zeros) wave-shaped waveform resembles a 10 MHz sinusoidal waveform as follows:                a   k     =       sin                   (     2      π                     f   o     ·     T   2     ·     k   n         )       =     sin                   (       π                 k     n     )                 (     EQ                 1     )                                
     where 
     k=0 to n−1         f   o     =     1   T                            
     ƒ o  is the fundamental frequency of the waveform, i.e., the digital bit rate. For the 10 Base-T example, the fundamental frequency is 10 MHz (or a period of 100 ns). 
     FIG. 3 shows a graph of outputs a 0 -a 7  of the FIR filter, where n=8. From EQ 1, it can easily be shown that for n=8: 
     
       
         ( a   0   , a   1   , a   2   , a   3   , a   4   , a   5   , a   6   , a   7 )=(0, 0.383, 0.7071, 0.9239, 1, 0.9239, 0.7071, 0.383)  ((EQ 2) 
       
     
     where the a k  coefficients represent the sinusoidal samples normalized to 1.0. 
     In a preferred embodiment of the present invention, the FIR coefficients b 0 -b 7  required to generate outputs a 0 -a 7  are derived as follows. As explained above, at the start of transmission, the output signal travels from 0 V (rest condition) to +1 V or to −1 V (normalized) depending upon the polarity of the input Manchester pulse. Therefore, in steady state, the FIR coefficients are defined from the maximum peak value of the signal (normalized to 1). From FIG.  3  and EQ 1, the FIR coefficients, which arc the difference of two subsequent samples, are derived as follows:                b   k     =       sin        (       π   2     +       π                 k     n       )       -     sin        (       π   2     +       π        (     k   +   1     )       n       )                 (     EQ                 3     )                                
     where 
     k=0 to n−1 
     For n=8, i.e., in an 8-tap FIR, the coefficients are as follows: 
     
       
         ( b   0   , b   1   , b   2   , b   3   , b   4   , b   5   , b   6   , b   7 )=(0.076, 0.217, 0.324, 0.383, 0.383, 0.324, 0.217, 0.076)  (EQ 4) 
       
     
     In a preferred embodiment of the present invention, the coefficients arc hard placed by scaling of transistors in a current-steering digital-to-analog converter (DAC), using leg pairs to provide each required pulse level. Thus, the realized n-leg DAC coefficients are as follows:                c   k     =       1   2          b   k               (     EQ                 5     )                                
     for 
     k=0 to n−1 
     So, for n=8, we have 
     
       
         ( c   0   , c   1   , c   2   , c   3   , c   4   , c   5   , c   6   , c   7 )=(0.0380, 0.1085, 0.1620, 0.1915, 0.1915, 0.1620, 0.0185, 0.0380)  (EQ 6) 
       
     
     For all-ones or all-zeros data (10 MHz in 10 Base-T), where a +1 level follows a −1 level every cycle, starting from a peak level (+1 or −1) first the current in the (c 0 , c 7 ), (c 1 , c 6 ), (c 2 , c 5 ), and (c 3 , c 4 ) leg pairs of the DAC are turned off sequentially in order with          T   S     =       1     f   s       =     T     2      n                                
     intervals. As defined above, T is the digital bit rate, i.e., 10 MHz, and n is the number of FIR taps. The leg pairs are then turned on in reverse order, i.e., the (c 3 , c 4 ), (c 2 , c 5 ), (c 1 , c 6 ), and (c 0 , c 7 ). It will be seen that the actuation of leg pairs in this sequence results in the desired outputs a 0 -a 7 . It should be noted that the polarity or sign of the signal changes at zero-crossings. 
     FIG. 4 shows one implementation of this current-steering DAC to implement the above-described FIR filter, with a main structure using only N-channel devices. The FIG. 4 circuit includes a bank of current sources c 0 -c 7 , which arc turned on and off by associated NMOS transistors (shown as switches) controlled by signals cnt 0  to cnt n−1  Tail currents c 0 -c 7  of the DAC arc scaled according to the coefficients given in EQ 5. 
     As further shown in FIG. 4, output selection circuitry is provided. The polarity of the Manchester-encoded pulse is changed by the sign signals represented by sgn p  and sgn n  in FIG.  4 . The sign signals control differential FET pairs Q 0p /Q n -Q (n−1)p /Q (n−1)n . Depending upon which FET is on, each current source provides one of two outputs, a positive output or a negative output. The circuit provides as a first output I p  the combined positive outputs from the current sources and as a second output I n  the combined negative outputs. The circuitry of FIG. 4 is typically implemented on an integrated circuit although other implementations are possible. 
     FIG. 5 shows a graph of the FIR DAC control signals that are used with the FIG. 4 to produce the desired sinusoidal output. The control signals are spaced by        1     f   s                            
     time intervals, for the case n=8. At the beginning of the cycle shown in the graph, the input pulse is +1 V (HI). Because the input pulse is positive, sgn p  is on and sgn n  is off. Control signals cnt 0 -cnt 7  are actuated in pairs to effect the DAC leg-pair sequence described above. When the input pulse drops to −1 V (LO), sgn n  is turned on. Note that, in order to achieve a more linear output signal (ideally sinusoidal), the sign signals are non-overlapping. Thus, sgn p  is turned off one time interval before sgn n  is turned on, and vice versa. Finally, it should be noted that the control signals shown in FIG. 5 are for the Manchester-encoded pulse representing all-ones (or all-zeros), i.e., the maximum frequency, and does not result in any pre-equalization. 
     FIG. 6 shows another embodiment of the present invention, using both P-channel and N-channel devices. The use of both P-channel and N-channel devices eliminates the requirement for sign signals sgn p  and sgn n . However, in order to achieve a bipolar signal (±1) as shown in FIG. 6, a new set of control signals must be added. As shown in FIG. 6, for each cnr k  control signal, it is necessary to generate a signal represented by cnt kp  in which k is the coefficient index andp (for prime) is a label to distinguish this control signal from its cnr k  counterpart. In order to control the P-channel devices, the inverted version of both original and prime control signals represented by {overscore (cnt)} k  and {overscore (cnt)} kp  must also be used. The control signals in FIG. 6 are such that the current in each cell always flows either from the top right current source (P-device) to the bottom left current source (N-device). It should be noted that all four current sources in each cell can be turned on at the same time; however, this increases power consumption. 
     FIG. 7 shows a graph of the control signals in the P- and N-channel architecture shown in FIG. 6, again for the case n=8. The control signals shown in FIG. 7 are for the Manchester-encoded pulse representing all-ones (or all-zeros) Manchester-encoded data (i.e., the maximum frequency) and do not result in any pre-equalization. With reference to FIG.  7  and FIG. 5, it is apparent that combining control signals cnt k  and cnt kp  in FIG. 7 (complementary P- and N-channel structure) using an OR function results in control signal cnt k  in FIG. 5 (N-channel structure only). 
     Thus far, it has been assumed that the input data is a Manchester-encoded pulse representing all-ones or all-zeros, which results in the period waveform shown in FIG. 5 (for the all N-channel structure shown in FIG. 4) or the one shown in FIG. 7 (for the complementary P- and N-channel structure shown in FIG.  6 ). But, as mentioned above, in order to increase the transmission distance, the present invention further provides a pre-equalization mechanism. 
     FIG. 8 shows a pre-equalization technique according to the present invention, where some pre-equalization is produced by an arbitrary weight, α%. Where there are two consecutive identical input data pulse levels, the resultant unfiltered pre-equalized signal exhibits amplitude droop by the equalization weight, α%. When the consecutive identical data pulses are positive, this droop is from +1 to 1−α during the second repeated pulse level. When the input data pulses are negative, this droop is from −1 to −1+α. According to the present invention, the wave-shaping technique described above is used to generate first and second analog signals a(t) and b(t), which are each multiplied by sign signal sgn(t) and then summed to produce the desired pre-equalized analog signal c(t). 
     As shown in FIG. 8, signals a(t) and b(t) are periodic waveforms, having respective peak values of 1−α and α. Thus, the combined peak values of the waveforms a(t) and b(t) is 1 (normalized). Signal a(t) is shaped to make a sinusoidal peak-to-peak transition during the first of two consecutive input pulses, and then to hold the peak value for the second consecutive input pulse. Signal b(t) is shaped to have a zero value during the first half of the first input pulse, followed by a sinusoidal zero-to-peak transition during the second half of the first input pulse, and then a sinusoidal peak-to-zero transition during the second input pulse. Because all transitions in waveforms a(t) and b(t) are sinusoidal, the same FIR coefficients can be used to generate these waveforms as were used in the embodiments of the invention described above. Of course, as discussed below, changes must be made to the sequence in which the control signals are actuated. 
     FIG. 9 shows a preferred embodiment of a circuit implementation for this method of producing pre-equalized analog signal c(t). The FIG. 9 circuit includes two sub-circuits, Part A and Part B. Each sub-circuit is similar to the circuit shown in FIG. 4, but with different current scaling. The FIG. 6 circuit, which includes complementary P-channel and N-channel current sources, can be used for the Part A and Part B sub-circuits as well. The Part A sub-circuit is used to generate analog signal a(t), and the Part B sub-circuit is used to generate analog signal b(t). The transistor sizes for Part A are scaled by a factor of 1−α. The transistor sizes for the Part B are scaled by a factor of α. For the special case where α=½ (i.e., 50% pre-equalization), Part A and Part B are identical, which makes the design and physical realization of the circuit much more straightforward. As shown in FIG. 9, both sub-circuits include output selection circuitry comprising FET pairs Q a0p /Q a0n -Q a(n−1)p /Q a(n−1)n  and Q b0p /Q b0n -Q b(n−1)p /Q b(n−1)n , which are used to separate the positive and negative outputs of the Part A and Part B sub-circuits, which are combined to produce outputs I p  and I n . Because Part A and Part B of the circuit each produce a fraction of the output current such that the total normalized peak current is 1, there is no excessive power consumption, as would be the case if one wanted to use a conventional continuous-time filter approach in which extra Gm-C filters or op-amps would be needed to accomplish the pre-equalization. 
     FIG. 10 shows a graph of the control signals for pre-equalization for the waveform shown in FIG. 8, representing a 5 MHz period in 10 Base-T. As shown in FIG. 10, the control signals represented by cnt ak  in the Part A and cnt bk  in the Part B sub-circuits shown in FIG. 9 to generate signals a(t) and b(t) arc different. However, their signs are the same, which simplifies the control method. 
     The method used for pre-equalization can be summarized, considering the following four cases: 
     Case 1: The level of the pulse switches from the previous level to the opposite level (+1→−1) or (−1→+1). This is the case of the Manchester-encoded pulse representing all-ones or all-zeros data. 
     Starting from a peak level, all control signals in both sub-circuits Part A and Part B are high. The control signals go off sequentially in order as follows (where ↑ and ↓ represent, respectively, a switch turning on or off): 
     (cnt a0 , cnt a7 )↓, (cnt a1 , cnt a6 )↓, (cnt a2 , cnt a5 )↓, (cnt a3 , cnt a4 )↓ 
     The control signals then turn on sequentially in reverse order: 
     (cnt a3 , cnt a4 )↑, (cnt a2 , cnt a5 )↑, (cnt a1 , cnt a6 )↑, (cnt a0 , cnt a7 )↑ 
     The sign control signals change at the zero-crossing point, i.e., for (+1→−1) transition sgn p ↓ and at the next step sgn n ↑ to guarantee the non-overlapping performance for the sign signals. The opposite action for the sign signal happens for (−1→+1) transition sgn n ↓ and at the next step sgn p ↑. It should be noted that for this case, every control signal in the Part B sub-circuit is identical to its counterpart in the Part A sub-circuit (i.e., cnt ak  and cnt bk  are alike). 
     Case 2: The level of the pulse is the same as the previous one (+1→+1) or (−1→−1). This is the case in which the pre-equalization must be working. 
     Starting from a peak level, all control signals in both sub-circuit Part A and sub-circuit Part B are high. The following events happen in the following sequence: 
     cnt b7 ↓, cnt b6 ↓, cnt b5 ↓, cnt b4 ↓, cnt b3 ↓, cnt b2 ↓, cnt b1 ↓, cnt b0 ↓ 
     Then at the next step: 
     (cnt a0 , cnt a7 )↓, (cnt a1 , cnt a6 )↓, (cnt a2 , cnt a5 )↓, (cnt a3 , cnt a4 )↓ 
     Then, the sign control signals change at the zero-crossing point, as was described in Case 1. 
     Case 3: This case addresses the start of packet (start of transmissions), where the level of the pulse travels from zero (rest) to +1 or −1 , i.e., (0→+1) or (0→−1). 
     Starting from zero level, both control signals in sub-circuit Part A and sub-circuit Part B are actuated in the following sequence: 
     (cnt a0 , cnt b0 )↑, (cnt a1 , cnt b1 )↑, (cnt a2 , cnt b2 )↑, (cnt a3 , cnt b3 )↑, 
     (cnt a4 , cnt b4 )↑, (cnt a5 , cnt b5 )↑, (cnt a6 , cnt b6 )↑, (cnt a7 , cnt b7 )↑ 
     At the start of the transmission, the sign control signals are set accordingly. Basically, sgn p ↑ and sgn n ↓ for +1 and sgn p ↓ and sgn n ↑ for −1 occur simultaneously. 
     Case 4: This case addresses the end of packet (end of transmission), where the level of the pulse travels from +1 or −1 to zero (rest), i.e., (+1→0) or (−1→0). 
     Starting from either +1 or −1 level: both control signals in sub-circuit Part A and sub-circuit Part B are actuated in the following sequence: 
     (cnt a7 , cnt b7 )↓, (cnt a6 , cnt b6 )↓, (cnt a5 , cnt b5 )↓, (cnt a4 , cnt b4 )↓, 
     (cnt a3 , cnt b3 )↓, (cnt a2 , cnt b2 )↓, (cnt a1 , cnt b1 )↓, (cnt a0 , cnt b0 )↓ 
     The sign control signals stay unchanged. 
     Every other event of data is a subset of the four cases described above and can be derived accordingly. 
     While the foregoing description includes detail which will enable those skilled in the art to practice the invention, it should be recognized that the description is illustrative in nature and that many modifications and variations thereof will be apparent to those skilled in the art having the benefit of these teachings. It is accordingly intended that the invention herein be defined solely by the claims appended hereto and that the claims be interpreted as broadly as permitted by the prior art.