Abstract:
A showerhead electrode includes inner and outer steps at an outer periphery thereof, the outer step cooperating with a clamp ring which mechanically attaches the electrode to a backing plate.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to a showerhead electrode used as an upper electrode in a plasma processing chamber in which semiconductor components can be manufactured. 
       SUMMARY 
       [0002]    A showerhead electrode used as an upper electrode of a capacitively coupled plasma processing chamber comprises a circular plate having a plasma exposed surface on a lower face thereof and a mounting surface on an upper face thereof. The lower face includes inner and outer steps at an outer periphery of the plate. The inner step has a smaller diameter than the outer step and the outer step is located between the inner step and the mounting surface. The outer step is configured to mate with an inwardly extending flange of a clamp ring and the inner step is configured to mate with an inner step of an outer electrode which surrounds the showerhead electrode such that an inner tapered surface of the outer electrode extends from the outer edge of the plasma exposed surface. The mounting surface includes a plurality of alignment pin recesses configured to receive alignment pins arranged in a pattern matching alignment pin holes in a backing plate against which the plate is held by the clamp ring and the plate includes process gas outlets arranged in a pattern matching gas supply holes in the backing plate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]      FIGS. 1A-D  show details of the showerhead electrode wherein  FIG. 1A  shows a front planar view showing the plasma exposed surface of the electrode  504  with the 13 rows of gas holes,  FIG. 1B  shows a front planar view of the upper face  522  with the 13 rows of gas holes and 6 pin holes  520 ,  FIG. 1C  shows a side view with the inner step closest to the plasma exposed surface and the outer step closest to the upper face of the electrode, and  FIG. 1D  shows an enlarged view of detail D of  FIG. 1C . 
       
    
    
     DETAILED DESCRIPTION 
       [0004]    The fabrication of an integrated circuit chip typically begins with a thin, polished slice of high-purity, single-crystal semiconductor material substrate (such as silicon or germanium) called a “wafer.” Each wafer is subjected to a sequence of physical and chemical processing steps that form the various circuit structures on the wafer. During the fabrication process, various types of thin films may be deposited on the wafer using various techniques such as thermal oxidation to produce silicon dioxide films, chemical vapor deposition to produce silicon, silicon dioxide, and silicon nitride films, and sputtering or other techniques to produce other metal films. 
         [0005]    After depositing a film on the semiconductor wafer, the unique electrical properties of semiconductors are produced by substituting selected impurities into the semiconductor crystal lattice using a process called doping. The doped silicon wafer may then be uniformly coated with a thin layer of photosensitive, or radiation sensitive material, called a “resist.” Small geometric patterns defining the electron paths in the circuit may then be transferred onto the resist using a process known as lithography. During the lithographic process, the integrated circuit pattern may be drawn on a glass plate called a “mask” and then optically reduced, projected, and transferred onto the photosensitive coating. 
         [0006]    The lithographed resist pattern is then transferred onto the underlying crystalline surface of the semiconductor material through a process known as etching. Vacuum processing chambers are generally used for etching and chemical vapor deposition (CVD) of materials on substrates by supplying an etching or deposition gas to the vacuum chamber and application of a radio frequency (RF) field to the gas to energize the gas into a plasma state. 
         [0007]    A reactive ion etching system typically consists of an etching chamber with an upper electrode or anode and a lower electrode or cathode positioned therein. The cathode is negatively biased with respect to the anode and the container walls. The wafer to be etched is covered by a suitable mask and placed directly on the cathode. A chemically reactive gas such as CF 4 , CHF 3 , CClF 3 , HBr, Cl 2  and SF 6  or mixtures thereof with O 2 , N 2 , He or Ar is introduced into the etching chamber and maintained at a pressure which is typically in the millitorr range. The upper electrode is provided with gas hole(s), which permit the gas to be uniformly dispersed through the electrode into the chamber. The electric field established between the anode and the cathode will dissociate the reactive gas forming plasma. The surface of the wafer is etched by chemical interaction with the active ions and by momentum transfer of the ions striking the surface of the wafer. The electric field created by the electrodes will attract the ions to the cathode, causing the ions to strike the surface in a predominantly vertical direction so that the process produces well-defined vertically etched sidewalls. The etching reactor electrodes may often be fabricated by bonding two or more dissimilar members with mechanically compliant and/or thermally conductive adhesives, allowing for a multiplicity of function. 
         [0008]      FIGS. 1A-D  show details of showerhead electrode  504 . The electrode  504  is preferably a plate of high purity (less than 10 ppm impurities) low resistivity (0.005 to 0.02 ohm-cm) single crystal silicon with alignment pin holes  520  in an upper face (mounting surface)  522  which receive alignment pins  524  and steps in an outer edge  526  which mate with a clamp ring (not shown) and an inner lip of an outer electrode (not shown). Gas holes  528  of suitable diameter and/or configuration (e.g., 0.017 inch diameter holes) extend from the upper face to the lower face (plasma exposed surface)  530  and can be arranged in any suitable pattern. In the embodiment shown, the gas holes are arranged in 13 circumferentially extending rows with 4 gas holes in the first row located about 0.25 inch from the center of the electrode, 10 gas holes in the second row located about 0.7 inch from the center, 20 gas holes in the third row located about 1.25 inches from the center, 26 gas holes in the fourth row located about 1.95 inches from the center, 30 gas holes in the fifth row located about 2.3 inches from the center, 36 gas holes in the sixth row located about 2.7 inches from the center, 40 gas holes in the seventh row located about 3.05 inches from the center, 52 gas holes in the eighth row located about 3.75 inches from the center, 58 gas holes in the ninth row located about 4.1 inches from the center, 62 gas holes in the tenth row located about 4.5 inches from the center, 70 gas holes in the eleventh row located about 5.2 inches from the center, 74 gas holes in the twelfth row located about 5.45 inches from the center and 80 holes in the thirteenth row located about 5.75 inches from the center. 
         [0009]    The upper face of the electrode includes 6 alignment pin holes  520  with 3 pin holes near the center and 3 pin holes near the outer edge of the electrode. The pin holes can have diameters of about 0.116 inch. The 3 central pin holes are radially aligned and include a pin hole about 0.160 inch deep at the center of the electrode and 2 pin holes about 0.200 inch deep located about 1.6 inches from the center pin hole at locations between the third and fourth row of gas holes. The outer pin holes are about 0.100 inch deep and include one pin hole radially aligned with the central pin holes about 6 inches from the center pin hole and two other pin holes offset 97.5° and 170° therefrom with the second and the third outer pin holes the same distance from the center pin hole but offset 92.5° from each other. 
         [0010]    The outer steps include an inner step  532  and an outer step  534  machined into the silicon plate so as to extend completely around the silicon plate. In a preferred embodiment, the silicon plate has a thickness of about 0.400 inch and an outer diameter of about 12.560 inch, the inner step  532  has an inner diameter of about 12.004 inches, an outer diameter of about 12.135 inch and extends about 0.13 inch into the plasma exposed surface  530  and the outer step  534  has an inner diameter of about 12.135 inches and an outer diameter of about 12.560 inches and extends about 0.24 inch into the plasma exposed surface  530 . The inner step  532  has a vertical surface  532   a  about 0.13 inch long and a horizontal surface  532   b  about 0.065 inch long and the outer step  534  has a vertical surface  534   a  about 0.11 inch long and a horizontal surface  534   b  about 0.218 inch long. 
         [0011]      FIG. 1A  shows a front planar view showing the plasma exposed surface  530  of the electrode  504  with the 13 rows of gas holes.  FIG. 1B  shows a front planar view of the upper face  522  with the 13 rows of gas holes and 6 pin holes  520 .  FIG. 1C  shows a side view with the inner step closest to the plasma exposed surface and the outer step closest to the upper face of the electrode.  FIG. 1D  shows an enlarged view of detail D of  FIG. 1C  showing the inner and outer steps with 6 rounded corners provided at the outer edge of the upper face  522 , the outer edge of the lower face  530  and transitions between the horizontal and vertical surfaces  532   a,    532   b,    534   a,    534   b  with corners of each other and the upper and lower faces  522 ,  530  (e.g., rounded with a 0.025 inch radius). 
         [0012]    While the invention has been described in detail with reference to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made, and equivalents employed, without departing from the scope of the appended claims.