Abstract:
A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously. Avoiding concurrent activity of the enable signals eliminates contention on the tri-state output bit lines, and thereby prevents the mutually coupled tri-state bit lines output from the first and second tri-state buffers from being active at the same time. Placing a delay between activity minimizes contention on the mutually coupled, buffered bit line.

Description:
RELATED APPLICATIONS 
   This application relates to co-pending application, Ser. No. 11/237,064 filed Sep. 27, 2005, entitled “HIGH PERFORMANCE LATCH-BASED RANDOM ACCESS MEMORY (LBRAM) TRI-STATE BANKING ARCHITECTURE,” by David Vinke, Bret A. Oeltjen, and Ekambaram Balaji, which is incorporated herein by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to data storage devices, and more particularly to a memory device that can utilize latch cells and tri-state buffering of bit lines depending on enable signals produced from a portion of an address signal at dissimilar times to avoid contention among the buffered bit lines. 
   2. Description of the Related Art 
   There is increased use of memories in application specific integrated circuits (ASICs) today, and the trend is for even more memory use per ASIC. There is also a trend for increased use of small memories which are often implemented as latch-based random access memories (LBRAMS). Key issues with LBRAMs include performance and required die area. 
   A common method to implement memories on ASICs is to use static random access memories (SRAMs) that include an array of bit cells surrounded by logic to read data from, and write data to, the bit cells. In general, SRAM bit cells are organized in groups such that all bit cells in a group are connected to a pair of bit lines. The bit lines are used to write data to the bit cells and to read data from the bit cells. Typically, special sense amplifiers are used to sense small voltage swings on the bit lines to determine whether the bit cell is storing a logic 1 or a logic 0. Using a small voltage swing has the advantage of allowing a smaller bit cell and faster read times. However, the area overhead associated with the sense amplifiers can be a large drawback for small memories. Furthermore, SRAMs are susceptible to many more defects than standard logic and so require special built-in self test (BIST) test logic to test for defects. For smaller memories the die areas required to implement the BIST logic may be larger than the memory itself. 
   Due to the relatively large die areas required by SRAMs, small memories are often implemented as LBRAMs. A typical LBRAM includes an array of latch cells surrounded by logic to read data from, and write data to, the latch cells. The latch cells are typically organized into groups with all latch cells in a group connected to a common bit line. Unlike SRAM bit lines, latch cell bit lines use standard logic 1 and logic 0 voltage levels. As a result, standard logic can be connected directly to the bit lines to read the data. This reduces the area overhead to implement the memory, and for small memories the area of an LBRAM is much smaller than a comparable SRAM. 
   The main drawback with using full voltage swings on the bit lines is that transitions from one logic level to another take longer, negatively impacting memory performance. As a result of the slow transitions, known LBRAMs are often slower than, or at best match the performance of, comparable SRAMs. However, as latch cells are quite similar to standard logic, and full voltage swings are used on the bit lines, LBRAMs are not susceptible to any more defects than standard logic cells, and the BIST logic overhead required with SRAMs can be avoided. For example, LBRAMs can be smaller than comparable SRAMs at memory sizes up to 8K total data bits. 
   It would be beneficial to have a random access memory (RAM) structure that has a read access time that is sufficiently less than known LBRAM structures and/or requires a smaller die area than known LBRAM structures. 
   SUMMARY OF THE INVENTION 
   A disclosed random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: 
       FIG. 1  is a diagram of a portion of a 8×4 latch-based random access memory (LBRAM); 
       FIG. 2  is a diagram of one embodiment of an LBRAM having a latch array divided into 2 banks according to a multiplexer (mux) banking architecture; 
       FIG. 3  is a diagram of one embodiment of an LBRAM having a latch array divided into 2 banks according to a tri-state banking architecture; 
       FIG. 4  is a diagram of one embodiment of a tri-state buffer that can be used to form tri-state buffers of the LBRAM of  FIG. 3  to improve the performance of the LBRAM; 
       FIG. 5  is a diagram of one embodiment of enable signal generation logic of the LBRAM of  FIG. 3  wherein the latch array of the LBRAM is divided into 4 banks; 
       FIG. 6  is a diagram of another embodiment of the enable signal generation logic of  FIG. 5  having fewer logic gates; 
       FIG. 7  is a timing diagram for the embodiment of the enable signal generation logic of  FIG. 6 ; and 
       FIG. 8  is a diagram of one embodiment of an LBRAM implemented using the tri-state banking architecture of  FIG. 3 . 
   

   While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1  is a diagram of a portion of a conventional 8×4 latch-based random access memory (LBRAM)  10 . The conventional LBRAM  10  has a decode unit  12  coupled to a latch array  14 . The latch array  14  includes a two-dimensional array of latch cells  16 , wherein each of the latch cells  16  includes a latch. The latch array  14  has 8 word lines 18 and 4 bit lines  20 . The decode unit  12  receives a 3-bit address signal including address bits A 2 , A 1 , and A 0 . The address bits A 2 , A 1 , and A 0  are ordered, wherein address bit A 2  is the highest-ordered address bit, and the address bit A 0  is the lowest-ordered address bit. The decode unit  12  is coupled to the 8 word lines of the latch array  14 , and activates one of the word lines  18  according to the 3-bit address signal. 
   In the LBRAM  10  of  FIG. 1  the latch cells  16  of the latch array  14  are grouped by bit number in rows, and by word number in columns. Each of the latch cells  16  in each row has an output connected to a corresponding one of the bit lines  20 . Each of the latch cells  16  in each column is activated when the corresponding word line is activated, and drives the corresponding bit line with a data value stored by the latch. Accordingly, only one of the latch cells  16  drives each of the bit lines  20  at any given time. 
   The use of full voltage swings (i.e., in excess of 1.5 volts, or possibly as little as 1.0 volts) on the bit lines  20  causes transitions from one logic level to the other to be relatively slow, negatively impacting performance of the LBRAM  10 . In addition, electrical loading on each of the bit lines  20  also slows signal transitions. One of the latch cells  16  connected to each of the bit lines  20  is active and drives the bit line, while the other latch cells  16  connected to the bit line are inactive. The amount of time required for signals on the bit lines  20  to transition from one logic level to the other is determined by the ability of the latch cells  16  to drive the bit lines  20 . 
   In general, the electrical loading on each of the bit lines  20  has two parts: a gate load from the inactive latch cells  16  with outputs connected to the bit line, and a wire load from the conductor (e.g., metal interconnect) forming the bit line. One problem with the LBRAM  10  of  FIG. 1  is that as the number of latch cells  16  is increased, the electrical loading on each of the bit lines  20  increases proportionally, and performance falls off quickly. 
     FIG. 2  is a diagram of one embodiment of a 2 n ×m LBRAM  30  having a latch array  34  divided into 2 banks  34 A and  34 B, wherein bit lines of each of the banks  34 A and  34 B are relatively short and signal transitions on the bit lines occur more quickly. Each of the banks  34 A and  34 B includes a two-dimensional array of latch cells  36 , wherein each of the latch cells  36  includes a latch. The bank  34 A has 2 n−1  word lines  38  and m bit lines  40 . The similar bank  34 B also has 2 n−1  word lines  42  and m bit lines  44 . The LBRAM  30  has 2 decode units  32 A and  32 B, each receiving the (n−1) highest-ordered bits of an n-bit address signal A. 
   The latch cells  36  of each of the banks  34 A and  34 B may be grouped by bit number in rows, and by word number in columns. Each of the latch cells  36  in each row of the bank  34 A has an output connected to a corresponding one of the bit lines  40 , and each of the latch cells  36  in each row of the bank  34 B has an output connected to a corresponding one of the bit lines  44 . Each of the latch cells  36  in each column of the bank  34 A is activated when the corresponding one of the word lines  38  is activated, and drives the corresponding one of the bit lines  40  with a data value stored by the latch. Similarly, each of the latch cells  36  in each column of the bank  34 B is activated when the corresponding one of the word lines  42  is activated, and drives the corresponding one of the bit lines  44  with a data value stored by the latch. 
   The decode unit  32 A is coupled to the 2 n−1  word lines  38  of the bank  34 A, and the decode unit  32 B is coupled to the 2 n−1  word lines  42  of the bank  34 B. The decode unit  32 A activates the word lines  38  of the bank  34 A according to the (n−1) lowest-ordered bits of the n-bit address signal A, and the decode unit  32 B activates the word lines  42  of the bank  34 B according to the (n−1) lowest-ordered bits of the n-bit address signal A. Although a separate decode unit is required for each of the banks  34 A and  34 B, each of the decode units  32 A and  32 B decodes only half the total number of words in the LBRAM  30 . 
   In the embodiment of  FIG. 2 , the LBRAM  30  includes m multiplexers having input nodes connected to corresponding bit lines of the banks  34 A and  34 B. Each of the m multiplexers receives the highest-ordered bit AN of the n-bit address signal A at a control node, and uses the address bit AN to select between logic signals on the corresponding bit lines. Each of the m multiplexers also receives a corresponding bit of a test data signal TD at a third input node, and a test signal T at a second control node. As indicated in  FIG. 2 , each of the multiplexers performs a logic inversion function. When the test signal T is active or asserted, each of the m multiplexers produces the logical complement of the corresponding bit of the test data signal TD at an output node. 
   One of the m multiplexers (muxes) of the LBRAM  30  is shown in  FIG. 2  and labeled  46 . In the embodiment of  FIG. 2 , the multiplexer (mux)  46  is a 3:1 mux in order to facilitate a test mode. In other embodiments, the mux  46  may be a 2:1 mux. The mux  46  has an input node coupled to the corresponding bit line  40 A of the bank  34 A, another input node coupled to the corresponding bit line  44 A of the bank  34 B, and a third input node coupled to receive a bit TD 0  of the test data signal TD. The mux  46  has a control node coupled to receive the highest-ordered bit AN of the n-bit address signal A, and another control node coupled to receive the test signal T. When the test signal T is active or asserted, the mux  46  produces the logical complement of the corresponding bit TD 0  at the output node as an output signal D 0 . When the test signal T is inactive or deasserted, the mux  46  produces the logical complement of either a signal on the corresponding bit line  40 A of the bank  34 A, or the logical complement of a signal on the corresponding bit line  44 A of the bank  34 B, as the output signal D 0  is dependent upon a logic value of the address bit AN. 
   In the LBRAM  30  of  FIG. 2 , the m bit lines  40  and  44  in the respective banks  34 A and  34 B are not coupled directly, but are coupled through the m muxes including the mux  46 . The advantage of this approach is that fewer latch cells are connected to the bit lines  40  and  44 , and the bit lines  40  and  44  are shorter than they would otherwise be. As a result, both gate loading and wire loading on the bit lines  40  and  44  are reduced over the loadings on the bit lines  20  of the LBRAM  10  of  FIG. 1 , allowing the signal transition times on the bit lines  40  and  44  to be significantly faster than on the bit lines  20 . 
   Typically, the banks  34 A and  34 B are positioned close to one another on a surface of a semiconductor substrate, and the m muxes including the mux  46  are positioned between the two banks  34 A and  34 B. The decode unit  32 A is positioned near the bank  34 A, and the decode unit  32 B is positioned near the bank  34 B. LBRAMs with larger numbers of banks can easily be implemented using the mux banking architecture of  FIG. 2 . 
   In general, the reduction in signal transition times on bit lines achieved by dividing a latch array into multiple banks as in  FIG. 2  increases with the number of banks. This benefit is offset, however, by the cost of the added delay through the muxes. The LBRAM  30  of  FIG. 2  with 2 banks  34 A and  34 B can use simple 2:1 muxes to couple the bit lines  40  of the bank  34 A to the corresponding bit lines  44  of the bank  34 B. When more banks are used, however, the mux function must be implemented with more complicated muxes such as 4:1 or 8:1 muxes, or with several levels of 2:1 muxes. In either case, the mux delay is increased when many banks are used. For example, using one logic technology it was determined that for LBRAMs the cost of the mux delay can exceed the benefit of the bit line transition time reduction if the latch array is divided into more than 16 banks. It was also determined that the fastest read access time is typically obtained if only 4 banks are used. 
   For example, assume an LBRAM like the LBRAM  30  of  FIG. 2  with 16 banks. Also assume the muxing function is 17:1 to accommodate the bit lines of the 16 banks and the test mode. The muxing logic can be implemented in a single stage cell, or using a number of stages of 2:1 muxes. A disadvantage of a single stage cell is that the bit lines of all the 16 banks must be routed to the cell, and some may be quite long. A disadvantage of using the stages of 2:1 muxes is that each stage adds extra delay. For the 16 banks and the 17:1 muxing function, 5 stages of 2:1 muxes are required (4 stages to mux the bit lines of the 16 banks, and an additional 2:1 mux stage for the test mode). 
     FIG. 3  is a diagram of one embodiment of a 2 n ×m LBRAM  60  having a latch array  64  divided into 2 banks  64 A and  64 B, wherein a shorter read access time is achieved by implementing bit line signal selection logic using tri-state buffers. Each of the banks  64 A and  64 B includes a two-dimensional array of latch cells  66 , wherein each of the latch cells  66  includes a latch. The bank  64 A has 2 n−1  word lines  68  and m bit lines  70 . The similar bank  64 B also has 2 n−1  word lines  72  and m bit lines  74 . The LBRAM  60  has 2 decode units  62 A and  62 B, each receiving the (n−1) highest-ordered bits of the n-bit address signal A. 
   The latch cells  66  of each of the banks  64 A and  64 B are grouped by bit number in rows, and by word number in columns. Each of the latch cells  66  in each row of the bank  64 A has an output connected to a corresponding one of the bit lines  70 , and each of the latch cells  66  in each row of the bank  64 B has an output connected to a corresponding one of the bit lines  74 . Each of the latch cells  66  in each column of the bank  64 A is activated when the corresponding one of the word lines  68  is activated, and drives the corresponding one of the bit lines  70  with a data value stored by the latch. Similarly, each of the latch cells  66  in each column of the bank  64 B is activated when the corresponding one of the word lines  72  is activated, and drives the corresponding one of the bit lines  74  with a data value stored by the latch. 
   The decode unit  62 A is coupled to the 2 n−1  word lines  68  of the bank  64 A, and the decode unit  62 B is coupled to the 2 n−1  word lines  72  of the bank  64 B. The decode unit  62 A activates the word lines  68  of the bank  64 A according to the (n−1) highest-ordered bits of the n-bit address signal A, and the decode unit  62 B activates the word lines  72  of the bank  64 B according to the (n−1) highest-ordered bits of the n-bit address signal A. Although a separate decode unit is required for each of the banks  64 A and  64 B, each of the decode units  62 A and  62 B decodes only half of the total number of words in the LBRAM  60 . 
   In the embodiment of  FIG. 3 , the LBRAM  60  includes enable signal generation logic  76  coupled to each of m selection logic units. One of the m selection logic units is shown in  FIG. 3  and labeled  78 . All of the m selection logic units are structured and operate similarly. The enable signal generation logic  76  receives the lowest-ordered bit A 0  of the n-bit address signal A, and uses the bit A 0  to produce 2 enable signals E 0  and E 1 . 
   In the embodiment of  FIG. 3 , the selection logic unit  78  includes 2 tri-state buffers  80  and  82 , an optional tri-state buffer  84 , a tri-state bit line  86 , and an inverter gate (i.e., inverter)  88 . The tri-state buffer  80  has an input node coupled to the bit line  70 A of the bank  64 A, an enable node coupled to receive the enable signal E 1 , and an output node coupled to the tri-state bit line  86 . The tri-state buffer  82  has an input node coupled to the bit line  74 A of the bank  64 B, an enable node coupled to receive the enable signal E 0 , and an output node coupled to the tri-state bit line  86 . The optional tri-state buffer  84 , included in the embodiment of  FIG. 3  to facilitate the test mode, has an input node coupled to receive the bit TD 0  of the test data signal TD, an enable node coupled to receive the test signal T, and an output node coupled to the tri-state bit line  86 . The inverter  88  has an input node coupled to the tri-state bit line  86 , and produces the logical complement of a logic level on the tri-state bit line  86  as an output signal “D 0 ” at an output node. The output signal D 0  is indicative of a data value stored in the latch array  64  and accessed via the address signal A. 
   In the embodiment of  FIG. 3 , the enable signals E 1  and E 0  and the test signal T are active high, meaning they are active or asserted when a high logic level (i.e., a logic 1 level), and inactive or deasserted when a low logic level (i.e., a logic 0 level). In general, the tri-state buffer  80  drives the tri-state bit line  86  to a logic level on the bit line  70 A when the enable signal E 1  is active (when the address bit A 0  is a logic 0 and T is inactive). Although not directly shown in  FIG. 3 , implicit in signal E 1  is that E 1  is active when A 0  is inactive and signal T is inactive. Similarly, the tri-state buffer  82  drives the tri-state bit line  86  to a logic level on the bit line  74 A when the enable signal E 0  is active (when the address bit A 0  is a logic 1 and T is inactive), and the tri-state buffer  84  drives the tri-state bit line  86  to a logic level of the received bit TD 0  of the test data signal TD when the test signal T is active. Also not directly shown in  FIG. 3 , signal E 0  is active when A 0  is active and signal T is inactive. 
   In the embodiment of  FIG. 3 , the enable signal generation logic  76  produces the lowest-ordered bit A 0  of the n-bit address signal A as the enable signal E 0 . The enable signal generation logic  76  includes an inverter  90  having an input node coupled to receive the lowest-ordered bit A 0  of the n-bit address signal A. The inverter  90  produces the logical complement of the bit A 0  as the enable signal E 1  at an output node. 
   When the test signal T is active or asserted, the selection logic unit  78  produces the logical complement of the corresponding bit TD 0  of the test data signal TD at the output node as the output signal D 0 . When the test signal T is inactive or deasserted, the selection logic unit  78  produces either the logical complement of a signal on the corresponding bit line  70 A of the bank  64 A, or the logical complement of a signal on the corresponding bit line  74 A of the bank  64 B, as the output signal D 0  dependent upon a logic value of the address bit A 0 . 
   It is noted that in the LBRAM embodiments of  FIGS. 2 and 3 , any of the address bits can be used to select between data provided by the multiple banks via bit lines. In the LBRAM  10  of  FIG. 2 , the highest-ordered address bit is used to select between data provided by the multiple banks. In the LBRAM  60  of  FIG. 3 , the lowest-ordered address bit is advantageously used to select between data provided by the multiple banks as the sizes of the banks can be made equal. As this may not be readily apparent, an explanation follows. 
   In the embodiment of  FIG. 3 , the LBRAM  60  has 2 n  words (i.e., the number of words in the LBRAM  60  is a power of 2), and each of the decode units  62 A and  62 B receives the highest-ordered address bits AN, A(N−1) . . . A 1 . In other embodiments of the LBRAM  60 , however, the number of words may not a power of  2 . In this situation, using the lowest-ordered address bit to select between data provided by the multiple banks results in equally sized banks. For example, assume the LBRAM  60  is a 6×m memory containing 6 words, and the latch array  64  is divided into 2 banks as in  FIG. 3 . Three address bits A 2 , A 1 , and A 0  are needed to access the 6 words, and the 6 words in the LBRAM  60  are accessed at addresses 000, 001, 010, 011, 100, and 101. Accessing latch cells at addresses 110 and 111 is not recommended as they may provide indeterminate data depending on the implementation. 
   If the highest-ordered address bit A 2  is used to select between data provided by the banks  64 A and  64 B as in  FIG. 3 , and address bits A 1  and A 0  are provided to each of the decode units  62 A and  62 B, then data at addresses 000, 001, 010, and 011 is stored in the bank  64 A, and is selected when address bit A 2  is a logic 0. The data at addresses 100 and 101 is stored in the bank  64 B, and is selected when the address bit A 2  is a logic 1. As a result, the bank  64 A is a 4×m bank, and the bank  64 B is a 2×m bank. 
   If, on the other hand, the lowest-ordered address bit A 0  is used to select between data provided by the banks  64 A and  64 B as in  FIG. 3 , and address bits A 2  and A 1  are provided to each of the decode units  62 A and  62 B, then data at addresses 000, 010, 100 is stored in the bank  64 A, and is selected when address bit A 0  is a logic 0. The data at addresses 001, 011, and 101 is stored in the bank  64 B, and is selected when the address bit A 0  is a logic 1. The banks  64 A and  64 B are advantageously equally sized 3×m banks. 
   Using the tri-state banking architecture of  FIG. 3 , larger numbers of banks can be implemented by simply connecting a tri-state buffer between a bit line of each bank and a corresponding tri-state bit line. For example, a 16-bank version can be implemented with 17 tri-state buffers having output nodes connected to each tri-state bit line. In this situation, the performance is significantly better than with the 5 mux stages required for the mux banking architecture of  FIG. 2 . The main advantage of the tri-state banking architecture of  FIG. 3  over the mux banking architecture of  FIG. 2  is that time delays for additional mux stages are replaced by a single tri-state buffer delay. (It is noted that this advantage is somewhat offset with the increased loading on each tri-state bit line as more tri-state buffers are connected.) 
   In general, the LBRAM  60  of  FIG. 3  includes a 2 n ×m latch array  64  divided to form p banks, wherein n, m, and p are integers, and n≧1, m≧1, and p≧2. Each of the p banks comprises (2 n−1 ×m) latch cells each configured to store data, 2 n−k  word lines where k=log 2 (p), and m bit lines. The LBRAM  60  also includes p decode units each coupled to the 2 n−k  word lines of a corresponding one of the p banks. Each of the p decode units is adapted to receive the highest-ordered (n−k) bits of an n-bit address signal and to activate one of the 2 n−k  word lines of the corresponding one of the p banks dependent upon the highest-ordered (n−k) bits of the address signal. The LBRAM  60  also includes enable signal generation logic adapted to receive the lowest-ordered k bits of the n-bit address signal and to generate p enable signals dependent upon the lowest-ordered k bits of the address signal. 
   In the embodiment of  FIG. 3 , the LBRAM  60  also includes a first set of m tri-state buffers each having an input node coupled to a different one of the m bit lines of one of the p banks, an enable node coupled to receive one of the p enable signals, and an output node coupled to a different one of m tri-state bit lines. The LBRAM  60  also includes a second set of m tri-state buffers each having an input node coupled to a different one of the m bit lines of another one of the p banks, an enable node coupled to receive one of the p enable signals, and an output node coupled to a different one of the m tri-state bit lines. The LBRAM  60  produces an output signal in response to the n-bit address signal and dependent upon a logic level of the tri-state bit line, wherein the output signal is indicative of a data value stored in the 2 n ×m latch array and accessed via the n-bit address signal. 
     FIG. 4  is a diagram of one embodiment of a tri-state buffer  100  that can be used to form the tri-state buffers  80 ,  82 , and/or  84  of the LBRAM  60  of  FIG. 3  to improve the performance of the LBRAM  60 . In the embodiment of  FIG. 4 , the tri-state buffer  100  includes a NAND gate  102 , a NOR gate  104 , a p-channel metal oxide semiconductor (PMOS) transistor  106 , and an n-channel metal oxide semiconductor (NMOS) transistor  108 . One input node of the NAND gate  102  is coupled to receive an enable signal E, and another input node of the NAND gate  102  is coupled to a bit line of a corresponding bank of a latch array and receives a data signal D from the corresponding bank. An output node of the NAND gate  102  is coupled to a gate terminal of the PMOS transistor  106 . 
   The NOR gate  104  also has an input node coupled to the bit line of the bank of the latch array that also receives the data signal D. Another input node of the NOR gate  104  is coupled to receive the logical complement of the enable signal E, labeled EB in  FIG. 4 . An output node of the NOR gate  104  is coupled to a gate terminal of the NMOS transistor  108 . 
   The PMOS transistor  106  and the NMOS transistor  108  are coupled in series between a positive power supply voltage VDD and a common ground power supply voltage. The PMOS transistor  106  has a source terminal coupled to VDD and a drain terminal coupled to an output node  110  of the tri-state buffer  100 . The NMOS transistor  108  has a drain terminal coupled to the output node  110  and a source terminal coupled to the common ground power supply voltage. The output node  110  is coupled to a tri-state bit line corresponding to the bit lines of the bank of the latch array. 
   In the LBRAM  60  of  FIG. 3 , all of the m tri-state buffers associated with the bank  64 A receive the enable signal E 1 , and all of the m tri-state buffers associated with the bank  64 B receive the enable signal E 0 . A single inverter can be use to invert the enable signal E 1 , and another inverter can be used to invert the enable signal E 0 . The inverted enable signal E 1  can be provided to the m tri-state buffers associated with the bank  64 A, and the inverted enable signal E 0  can be provided to the m tri-state buffers associated with the bank  64 B. The main advantage of using the tri-state buffer  100  is that the area and width of the tri-state buffer  100  is reduced over other known tri-state buffer implementations. The decreased width of the tri-state buffer  100  allows banks of latch arrays to be placed closer together as less space is needed. Use of the tri-state buffer  100  has a positive impact on performance due to reduced wire lengths of the tri-state bit lines. 
   The read access times and die areas of selected LBRAM configurations were computed for both the mux banking architecture of  FIG. 2  and the tri-state banking architecture of  FIG. 3 . The results are summarized in Tables 1 and 2 below. 
   
     
       
             
           
             
             
             
             
           
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Read Access Times For Several LBRAM Configurations 
             
           
        
         
             
                 
               Read Access Time (ns) 
                 
                 
             
             
               Configuration 
               Mux Banking 
               Tri-state Banking 
               % difference 
             
             
                 
             
           
        
         
             
               1 
               1.70 
               1.33 
               −21.76% 
             
             
               2 
               1.67 
               1.28 
               −23.35% 
             
             
               3 
               1.69 
               1.37 
               −18.93% 
             
             
               4 
               2.11 
               1.48 
               −29.86% 
             
             
               5 
               2.10 
               1.48 
               −29.52% 
             
             
               6 
               2.18 
               1.51 
               −30.73% 
             
             
               7 
               1.14 
               0.79 
               −30.70% 
             
             
               8 
               1.13 
               0.80 
               −29.20% 
             
             
               9 
               1.17 
               0.85 
               −27.35% 
             
             
               10 
               1.40 
               0.94 
               −32.86% 
             
             
               11 
               1.42 
               0.93 
               −34.51% 
             
             
               12 
               1.46 
               1.00 
               −31.51% 
             
             
                 
             
           
        
       
     
   
   
     
       
             
           
             
             
             
             
           
             
             
             
             
           
         
             
               TABLE 2 
             
           
           
             
                 
             
             
               Die Areas For Several LBRAM Configurations 
             
           
        
         
             
                 
               Area (sq. μm) 
                 
                 
             
             
               Configuration 
               Mux Banking 
               Tri-state Banking 
               % difference 
             
             
                 
             
           
        
         
             
               1 
               33590.41 
               42287.24 
               25.89% 
             
             
               2 
               78686.94 
               113845.72 
               44.68% 
             
             
               3 
               120442.98 
               145445.84 
               20.76% 
             
             
               4 
               65732.82 
               80741.79 
               22.83% 
             
             
               5 
               155378.19 
               187830.91 
               20.89% 
             
             
               6 
               227357.94 
               279621.57 
               22.99% 
             
             
               7 
               42492.99 
               56943.88 
               34.01% 
             
             
               8 
               96177.07 
               126285.12 
               31.30% 
             
             
               9 
               146707.92 
               164166.12 
               11.90% 
             
             
               10 
               80632.19 
               95756.82 
               18.76% 
             
             
               11 
               175460.77 
               212361.07 
               21.03% 
             
             
               12 
               267646.78 
               314124.77 
               17.37% 
             
             
                 
             
           
        
       
     
   
   For each of the architectures, the number of banks in an LBRAM was chosen to give the best performance. For the mux banking architecture of  FIG. 2 , 2 or 4 banks usually gave the best performance. For the tri-state banking architecture of  FIG. 3 , 8 or 16 banks usually gave the best performance. The data in Tables 1 and 2 show that while the tri-state banking architecture of  FIG. 3  reduces read access time by 20–35%, that performance increase comes at a cost of a 20–35% increase in die area. Table 1 shows that the tri-state banking architecture of  FIG. 3  is the only LBRAM architecture capable of read access times of less than 1 nanosecond (ns). 
   A concern with any tri-state implementation like the tri-state banking architecture of  FIG. 3  is buffer contention. If two tri-state buffers driving the same tri-state bit line are enabled at the same time, a large power draw could occur which may cause voltage droop (IVD) problems in the LBRAM or for nearby circuitry. In the tri-state banking architecture of  FIG. 3 , each tri-state bit line is coupled to an output node of one tri-state buffer from each bank, and is driven by only one tri-state buffer at any given time. Which tri-state buffer drives the tri-state bit line is determined by the enable signals provided to the enable nodes of the tri-state buffers. The enable signals are generated by the enable signal generation logic  76  (see  FIG. 3 ). Switching between tri-state buffers driving the tri-state bit line is an issue as there could be some overlap between the enable signals. The timing of the enable signals is preferably controlled such that there is no overlap. 
     FIG. 5  is a diagram of one embodiment of the enable signal generation logic  76  of the LBRAM  60  of  FIG. 3  wherein the latch array  64  of the LBRAM  60  is divided into 4 banks. In the embodiment of  FIG. 5 , the enable signal generation logic  76  receives the lowest-ordered address bits A 1  and A 0 , and uses the address bits A 1  and A 0  to generate 4 enable signals E 0 , E 1 , E 2 , and E 3 . Each of the enable signals E 0 , E 1 , E 2 , and E 3  is applied to the enable nodes of the tri-state buffers coupled between the bit lines of one of the banks of the latch array  64  and a corresponding one of the tri-state bit lines. 
   In the embodiment of  FIG. 5 , the enable signals E 0 , E 1 , E 2 , and E 3  and the test signal T are active high, meaning they are active or asserted when the high logic level (i.e., the logic 1 level), and inactive or deasserted when the low logic level (i.e., the logic 0 level). In general, the enable signal generation logic  76  of  FIG. 5  generates the enable signals E 0 , E 1 , E 2 , and E 3  such that no two of the enable signals E 0 , E 1 , E 2 , and E 3  are ever in an active state (i.e., the logic 1 level) simultaneously. More specifically, the enable signal generation logic  76  of  FIG. 5  generates the enable signals E 0 , E 1 , E 2 , and E 3  such that a period of time occurs between a transition of one of the enable signals E 0 , E 1 , E 2 , and E 3  from the active state (i.e., the logic 1 level) to an inactive state (i.e., the logic 0 level) and a subsequent transition of the another one of the enable signals E 0 , E 1 , E 2 , and E 3  from the inactive state (i.e., the logic 0 level) to the active state (i.e., the logic 1 level). 
   In the embodiment of  FIG. 5 , the enable signal generation logic  76  delays the rising edges of each of the enable signals E 0 , E 1 , E 2 , and E 3  by the delay time of one inverter, and does not delay the falling edges of the enable signals E 0 , E 1 , E 2 , and E 3 . As a result, the enable signal generation logic  76  delays the rising edges of each of the enable signals E 0 , E 1 , E 2 , and E 3  such that the period of time occurring between a transition of one of the enable signals E 0 , E 1 , E 2 , and E 3  from an active state to an inactive state and a subsequent transition of the another one of the enable signals E 0 , E 1 , E 2 , and E 3  from the inactive state to the active state is substantially the delay time of one inverter. For reasons described below, the enable signal generation logic  76  of  FIG. 5  preferably generates the enable signals E 0 , E 1 , E 2 , and E 3  such that that the period of time occurring between a transition of one of the enable signals E 0 , E 1 , E 2 , and E 3  from an active state to an inactive state and a subsequent transition of the another one of the enable signals E 0 , E 1 , E 2 , and E 3  from the inactive state to the active state is greater than or equal to about 40 nanoseconds. 
   In the embodiment of  FIG. 5 , the enable signal generation logic  76  includes 4 AND gates each producing one of the enable signals E 0 , E 1 , E 2 , and E 3 . Each of the 4 AND gates has an input node coupled to receive the logical complement of the test signal T described above. When the test signal T is active or asserted (i.e., a logic 1), all 4 of the enable signals E 0 , E 1 , E 2 , and E 3  are inactive or deasserted (i.e., a logic 0). When the test signal T is a logic 0, the enable signal generation logic  76  produces the enable signals E 0 , E 1 , E 2 , and E 3  dependent upon the address bits A 1  and A 0 . 
   In the embodiment of  FIG. 5 , the enable signal generation logic  76  includes an inverter  120  producing the logical complement of the address signal A 0 , and another inverter  122  in series with the inverter  120  producing a signal A 0 D that is a delayed version of the address signal A 0 . The enable signal generation logic  76  of  FIG. 5  also includes a third inverter  124  producing the logical complement of the address signal A 1 , and a fourth inverter  126  in series with the inverter  124  producing a signal A 1 D that is a delayed version of the address signal A 1 . 
   The enable signal generation logic  76  of  FIG. 5  includes AND logic  128  that receives both the address signal A 0  and the delayed version A 0 D at input nodes, and logically ANDs the A 0  and A 0 D along with other signals to produce the enable signal E 1 . AND logic  130  receives both the address signal A 1  and the delayed version A 1 D at input nodes, and logically ANDs the signals A 1  and A 1 D along with other signals to produce the enable signal E 2 . AND logic  132  receives the address signals A 0  and A 1  and the respective delayed versions A 0 D and A 1 D at input nodes, and logically ANDs the signals A 0 , A 1 , A 0 D, and A 1 D, along with the logical complement of the test signal T, to produce the enable signal E 3 . As a result, the enable signal generation logic  76  generates the enable signals E 0 , E 1 , E 2 , and E 3  such that transitions of the enable signals E 0 , E 1 , E 2 , and E 3  from the inactive state to the active state are delayed by a period of time that is the essentially the delay time of the inverters  122  and  126 . 
     FIG. 6  is a diagram of another embodiment of the enable signal generation logic  76  of  FIG. 5  having fewer logic gates. As in the embodiment of  FIG. 5 , the enable signal generation logic  76  of  FIG. 6  receives the test signal T described above and produces the enable signals E 0 , E 1 , E 2 , and E 3  such that when the test signal T is a logic 1, all 4 of the enable signals E 0 , E 1 , E 2 , and E 3  are a logic 0. When the test signal T is a logic 0, the enable signal generation logic  76  of  FIG. 6  produces the enable signals E 0 , E 1 , E 2 , and E 3  dependent upon the address bits A 1  and A 0 . 
   In the embodiment of  FIG. 6 , the enable signal generation logic  76  includes an inverter  140  producing the logical complement of the address signal A 0 , and another inverter  142  in series with the inverter  140  producing the signal A 0 D that is the delayed version of the address signal A 0 . The enable signal generation logic  76  of  FIG. 6  also includes a third inverter  144  producing the logical complement of the address signal A 1 , and a fourth inverter  146  in series with the inverter  144  producing the signal A 1 D that is the delayed version of the address signal A 1 . 
   An AND gate  148  of the enable signal generation logic  76  of  FIG. 6  receives both the address signal A 0  and the delayed version A 0 D at input nodes, and logically ANDs the A 0  and A 0 D along with the logical complement of the test signal T to produce an intermediate signal A 0 T. Another AND gate  150  receives both the address signal A 1  and the delayed version A 1 D at input nodes, and logically ANDs the signals A 1  and A 1 D along with the logical complement of the test signal T to produce another intermediate signal A 1 T. An AND gate  152  receives the intermediate signal A 0 T and logically ANDs the intermediate signal A 0 T with another signal to produce the enable signal E 1 . Another AND gate  154  receives the intermediate signal A 1 T and logically ANDs the intermediate signal A 1 T with another signal to produce the enable signal E 2 . An AND gate  156  receives the intermediate signals A 0 T and A 1 T and logically ANDs the intermediate signals A 0 T and A 1 T to produce the enable signal E 3 . As a result, the enable signal generation logic  76  generates the enable signals E 0 , E 1 , E 2 , and E 3  such that transitions of the enable signals E 0 , E 1 , E 2 , and E 3  from the inactive state to the active state are delayed by a period of time that is the essentially the delay time of the inverters  142  and  146 . 
     FIG. 7  is a timing diagram for the embodiment of the enable signal generation logic  76  of  FIG. 6 . In the timing diagram of  FIG. 7 , a rising edge of a waveform of one of the enable signals E 0 , E 1 , E 2 , and E 3  signifies a transition of the enable signal from an inactive state to an active state, and a falling edge of the signal waveform signifies a transition of the enable signal from the active state to the inactive state. In  FIG. 7 , a period of time T 1  exists between a falling edge of the enable signal E 0  and a subsequent rising edge of the enable signal E 1 . A period of time T 2  exists between a falling edge of the enable signal E 1  and a subsequent rising edge of the enable signal E 3 , and a period of time T 3  exists between a falling edge of the enable signal E 3  and a subsequent rising edge of the enable signal E 2 . A period of time T 4  exists between a falling edge of the enable signal E 2  and a subsequent rising edge of the enable signal E 0 . The periods of time T 1 , T 2 , T 3 , and T 4  are all substantially equal to the delay time of one inverter. It is noted that in  FIG. 7  at most one of the enable signals E 0 , E 1 , E 2 , and E 3  is in the active state at any given time. 
   Generally speaking, in the embodiments of  FIGS. 5 and 6 , the enable signal generation logic  76  produces delayed versions of the address signals A 1  and A 0 , wherein the delayed versions of the address signals A 1  and A 0  are delayed in time by a delay time. The enable signal generation logic  76  uses the address signals A 1  and A 0 , and the delayed versions of the address signals A 1  and A 0 , to generate the enable signals E 0 , E 1 , E 2 , and E 3  such that transitions of the enable signals E 0 , E 1 , E 2 , and E 3  from the inactive state to the active state are delayed by a period of time that is a portion of the delay time. 
   It is noted that the enable signal generation logic  76  of  FIGS. 5 and 6  can easily be extended for situations where the latch array  64  of the LBRAM  60  of  FIG. 3  is divided into more banks such as, for example, 8 banks or 16 banks. 
   The enable signal generation logic  76  of  FIGS. 5 and 6  was simulated to determine a minimum period of time between one bank enable becoming inactive and another becoming active. The results for several LBRAM configurations are shown in Table 3 below. 
   
     
       
             
           
             
             
             
           
             
             
             
           
         
             
               TABLE 3 
             
           
           
             
                 
             
             
               Average Current Draws for Certain Time Periods Between Active Bank 
             
             
               Enables For Several LBRAM Configurations 
             
           
        
         
             
                 
               Time Periods Between 
                 
             
             
               Configuration 
               Active Bank Enables (ns) 
               Average Current (mA) 
             
             
                 
             
           
        
         
             
               1 
               84.54 
               5.56 
             
             
               2 
               101.45 
               1.85 
             
             
               3 
               36.04 
               57.78 
             
             
                 
             
           
        
       
     
   
   The data in Table 3 indicates that the average current draw of an LBRAM increases rapidly when the period of time between a transition of one of the enable signals from an active state to an inactive state and a subsequent transition of the another one of the enable signals from the inactive state to the active state is less than about 40 nanoseconds. Accordingly, the enable signal generation logic  76  of  FIG. 5  preferably generates the enable signals E 0 , E 1 , E 2 , and E 3  such that that the period of time occurring between a transition of one of the enable signals E 0 , E 1 , E 2 , and E 3  from an active state to an inactive state and a subsequent transition of the another one of the enable signals E 0 , E 1 , E 2 , and E 3  from the inactive state to the active state is greater than or equal to 40 nanoseconds. 
   Further simulations were conducted to determine the average current draws of LBRAMs using the tri-state banking architecture of  FIG. 3  as compared to the mux banking architecture of  FIG. 2 . The results for several LBRAM configurations are shown in Table 4 below. 
   
     
       
             
           
             
             
             
           
             
             
             
             
           
         
             
               TABLE 4 
             
           
           
             
                 
             
             
               Average Current Draws For Several LBRAM Configurations 
             
           
        
         
             
                 
               Average current (mA) 
                 
             
           
        
         
             
                 
                 
               Tri-state Banking with 
                 
             
             
               Configuration 
               Mux Banking 
               Contention Avoidance 
               % Difference 
             
             
                 
             
             
               1 
               0.087 
               0.092 
               +5.84% 
             
             
               2 
               0.325 
               0.340 
               +4.85% 
             
             
               3 
               1.383 
               1.277 
               −7.69% 
             
             
                 
             
           
        
       
     
   
   The results in Table 4 show that there is no excessive power draw during operation of LBRAMs implemented using the tri-state banking architecture of  FIG. 3 . 
   LBRAMs implemented using the tri-state banking architecture of  FIG. 3  were implemented on a test chip to validate the architecture. The LBRAMs were connected to form oscillating loops with an oscillation period equal to twice the read access time. Several test chip units were manufactured and the oscillation periods measured. The test chip also included a special process monitor circuit measuring the variation in transistor performance caused by manufacturing process variations. This transistor performance measurement is denoted as “Kp.” The oscillator loops were simulated, and the simulated oscillation period was adjusted for the Kp measurement for each test chip unit. The following Table 5 summarizes the measurements and simulations: 
   
     
       
             
           
             
             
             
           
             
             
             
             
           
         
             
               TABLE 5 
             
           
           
             
                 
             
             
               Oscillation Periods for Several LBRAM Units 
             
           
        
         
             
                 
               Oscillation Period (us) 
                 
             
           
        
         
             
               Unit 
               Measured 
               Simulated and Kp adjusted 
               % Difference 
             
             
                 
             
             
               1 
               1.18 
               1.15284030 
               −2.30% 
             
             
               2 
               1.18 
               1.13625274 
               −3.71% 
             
             
               3 
               1.11 
               1.11539029 
               +0.49% 
             
             
                 
             
           
        
       
     
   
   The results in Table 5 show that the expected read access time is matched very closely by the actual performance of LBRAMs that utilize the tri-state banking architecture of  FIG. 3 . In particular this indicates that the tri-state banking architecture of  FIG. 3  has prevented any negative impact of tri-state buffer contention on performance. 
     FIG. 8  is a diagram of one embodiment of an LBRAM  170  implemented using the tri-state banking architecture of  FIG. 3 . The LBRAM  170  includes a latch array  172  divided into multiple banks (e.g., 2, 4, 8, or 16 banks) including banks  172 A and  172 B. Each of the banks  172 A and  172 B includes a two-dimensional array of latch cells, wherein each of the latch cells includes a latch. Each of the banks  172 A and  172 B has multiple word lines and multiple bit lines. The latch cells of each of the banks  172 A and  172 B are grouped by bit number in rows, and by word number in columns. Each of the latch cells in each row of the bank  172 A has an output connected to a corresponding one of the bit lines of the bank  172 A, and each of the latch cells in each row of the bank  172 B has an output connected to a corresponding one of the bit lines of the bank  172 B. 
   The LBRAM  170  also includes write decode logic  174  divided into multiple write decode units including a write decode unit  174 A and a write decode unit  174 B. The write decode unit  174 A is coupled to the word lines of the bank  172 A, and the write decode unit  174 B is coupled to the words lines of the bank  172 B. During a write operation, each of the write decode units  174 A and  174 B receives a portion of a write address signal (e.g., the highest-ordered bits of the write address signal), and activates the word lines of the respective banks  172 A and  172 B according to the portion of a write address signal. 
   The LBRAM  170  also includes read decode logic  176  divided into multiple read decode units including a read decode unit  176 A and a read decode unit  176 B. The read decode unit  176 A is coupled to the word lines of the bank  172 A, and the read decode unit  176 B is coupled to the words lines of the bank  174 B. During a read operation, each of the read decode units  176 A and  176 B receives a portion of a read address signal (e.g., the highest-ordered bits of the read address signal), and activates the word lines of the respective banks  172 A and  172 B according to the portion of a read address signal. 
   During a read operation, the latch cells in one of the columns of each the banks  172 A and  172 B are activated when the corresponding word lines are activated. Each activated latch cell drives the corresponding bit line with a data value stored by the latch. Enable signal generation logic of the LBRAM  170  receives one or more of the lowest-ordered bits of the read address signal, and uses the lowest-ordered bits of the read address signal to produce multiple enable signals. The enable signals are provided to each of multiple selection logic units. Each of the selection logic units includes tri-state buffers that select between signals driven on corresponding bit lines, and each selection logic unit produces an output signal that is the logical complement of the selected bit line signal. 
   It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to be a novel random access memory (RAM) wherein a latch array is divided into multiple banks. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.