Abstract:
A bit-and-one-half analog to digital converter comprises a switched capacitor circuit, including an opamp, that receives an analog input voltage and generates a residual analog output voltage. The switched capacitor circuit samples the analog input voltage during a sampling phase and generates the residual analog output voltage during an integration phase. A comparator generates a digital output based on the analog output voltage generated by the switched capacitor circuit. A current source communicates with the opamp and is operable to supply a first bias current to the opamp during the sampling phase and a second bias current that is greater than the first bias current to the opamp during the integration phase.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a divisional of U.S. patent application Ser. No. 10/313,369 now U.S. Pat. No. 6,839,015, filed on Dec. 6, 2002. The disclosure of the above application is incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates to a multi-stage pipelined analog to digital converter, and more particularly to a method for reducing power consumption of each stage of an analog to digital converter. 
   BACKGROUND OF THE INVENTION 
   Multi-stage pipelined analog to digital converters (ADC) provide efficient high speed conversion of analog signals to digital equivalents. A representative multi-stage pipelined ADC  10  is shown in  FIG. 1 . The ADC  10  generally includes a plurality of converter stages, such as stages  11 ,  12  and  13 , arranged in series relative to each other. Each converter stage operates by comparing an analog input voltage to thresholds provided by reference signals Vrefp and Vrefn. As a result, each converter stage provides one or more bits of digital data to a digital correction circuit  15 . The digital correction circuit  15 , in turn, resolves the digital output from each stage into a digital output  16  that corresponds to an analog input  17 . 
     FIG. 2  is a generalized block diagram of each converter stage. In operation, each stage accepts an analog input voltage and generates a residual analog voltage and a digital stage output. In particular, each stage applies the analog input voltage to a multiplying digital to analog converter (MDAC)  19  to generate the residual analog voltage. The residual analog voltage is then provided to a comparator  18 , which generates the digital stage output. The residual analog voltage also serves as input to subsequent converter stages. This arrangement is also referred to herein as a bit-and-one-half analog to digital converter. 
   Each converter stage may include a switched capacitor circuit as shown in  FIG. 3 . The switched capacitor circuit operates in accordance with a two cycle clock with phases designated as Φ 1  and Φ 2 . During a sampling phase, input capacitors C 1  and C 2  are charged by an input voltage V in . In this phase, an operational amplifier  21  does not perform a function. During a subsequent integration phase, the switched capacitor circuit generates a residual output voltage. More specifically, the charge stored by the input capacitors is integrated by the operational amplifier  21  to generate an output voltage V out . In other words, the operational amplifier  21  is active every other clock cycle. The same bias current is continuously supplied to the operational amplifier  21 . 
   SUMMARY OF THE INVENTION 
   An analog to digital converter includes a first charging circuit that is selectively charged by an input voltage. A first opamp has one input that selectively communicates with the first charging circuit. A first current source selectively generates a first bias current for the first opamp during a first phase and a second bias current that is not equal to the first bias current for the first opamp during a second phase. 
   In other features, the first bias current is less than the second bias current. The first bias current is zero and the second bias current is greater than zero. The first opamp is operated in an integrating mode during the second phase. 
   In still other features, a first switching circuit communicates with the one input of the first opamp, the first charging circuit and the first current source. The first switching circuit charges the first charging circuit using the input voltage and operates the first current source to supply the first bias current to the first opamp during the first phase. The first switching circuit isolates the first charging circuit from the input voltage, operates the first opamp in an integrating mode and operates the first current source to supply the second bias current to the first opamp during the second phase. 
   In still other features, the first current source is a variable current source that selectively provides the first and second bias currents during the first and second phases, respectively. Alternately, the first current source includes two current sources. Only one of the two current sources is connected to the first opamp during the second phase. 
   In yet other features, a second charging circuit is selectively charged by an output of the first opamp. A second opamp has one input that selectively communicates with the second charging circuit. A second current source selectively generates the second bias current for the second opamp during the first phase and the first bias current for the second opamp during the second phase. 
   In still other features, a second switching circuit communicates with the one input of the second opamp, the second charging circuit and the second current source. The second switching circuit charges the second charging circuit using the output of the second opamp, operates the second opamp in an integrating mode and operates the second current source to supply the second bias current to the second opamp during the first phase. The second switching circuit isolates the second charging circuit from the output of the first opamp and operates the second current source to supply the first bias current to the second opamp during the second phase. The first charging circuit includes at least one capacitor. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1  is a block diagram depicting a conventional multi-stage pipelined analog to digital converter (ADC) according to the prior art; 
       FIG. 2  is a block diagram an exemplary converter stage residing in the multi-stage ADC according to the prior art; 
       FIG. 3  is a block diagram of a conventional switched capacitor circuit which may be implemented in a converter stage of the multi-stage ADC according to the prior art; 
       FIG. 4A  is a block diagram of a first switched capacitor circuit with reduced power consumption in accordance with the present invention; 
       FIG. 4B  is a flowchart illustrating the operation of the circuit in  FIG. 4A ; 
       FIG. 5  illustrates a current mirror according to the prior art; 
       FIG. 6A  is a diagram of a second switched capacitor circuit with reduced power consumption in accordance with the present invention; 
       FIG. 6B  is a flowchart illustrating the operation of the circuit in  FIG. 6A ; 
       FIG. 7A  is a diagram of a third switched capacitor circuit with reduced power consumption in accordance with the present invention; 
       FIG. 7B  is a flowchart illustrating the operation of the circuit in  FIG. 7A ; 
       FIG. 8A  illustrates a circuit having regular and/or irregular periodic active and inactive phases during operation and a power supply that supplies first and second bias signals during the regular and/or irregular periodic active and inactive phases, respectively; 
       FIG. 8B  illustrates exemplary regular periodic active and inactive phases for the circuit in  FIG. 8A  and exemplary first and second bias signals during the regular periodic active and inactive phases, respectively; 
       FIG. 8C  illustrates exemplary irregular periodic active and inactive phases for the circuit in  FIG. 8A  and exemplary first and second bias signals during the irregular periodic active and inactive phases, respectively; 
       FIG. 9A  illustrates multiple circuits having regular and/or irregular periodic active and inactive phases during operation and one or more power supplies that supply first and second bias signals during the regular and/or irregular periodic active and inactive phases, respectively; 
       FIG. 9B  illustrates exemplary regular and/or irregular periodic active and inactive phases for each of the circuits in  FIG. 9A  and exemplary first and second bias signals during the regular and/or irregular periodic active and inactive phases, respectively; 
       FIG. 10A  illustrates a square-waveform bias signal and a zero bias signal for the active and inactive phases, respectively; 
       FIG. 10B  illustrates the square-waveform bias signal of  FIG. 10A  and a non-zero bias signal for the active and inactive phases, respectively; 
       FIG. 11A  illustrates a stepped bias signal and a zero bias signal for the active and inactive phases, respectively; 
       FIG. 11B  illustrates the stepped bias signal of  FIG. 11A  and a non-zero bias signal for the active and inactive phases, respectively; 
       FIG. 12A  illustrates a linearly changing bias signal and a zero bias signal for the active and inactive phases, respectively; 
       FIG. 12B  illustrates the linearly changing bias signal of  FIG. 12A  and a non-zero bias signal for the active and inactive phases, respectively; 
       FIG. 13A  illustrates an exponentially changing bias signal and a zero bias signal for the active and inactive phases, respectively; 
       FIG. 13B  illustrates the exponentially changing bias signal of  FIG. 13A  and a non-zero bias signal for the active and inactive phases, respectively; 
       FIG. 14A  illustrates a stair-stepped bias signal and a zero bias signal for the active and inactive phases, respectively; and 
       FIG. 14B  illustrates the stair-stepped bias signal of  FIG. 14A  and a non-zero bias signal for the active and inactive phases, respectively. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. 
   Referring now to  FIG. 4A , a partial schematic of two exemplary converter stages  41 ,  42  of a multi-stage pipelined analog to digital converter are shown. For simplicity only two stages are shown; however, it is readily understood that an analog to digital converter may employ more converter stages. For instance, a nine bit analog to digital converter employs seven such converter stages. Moreover, it is readily understood that the operational schemes of the present invention are applicable to such converters. 
   Each converter stage includes a switched capacitor circuit and a comparator. As noted above, each switched capacitor circuit operates in accordance with a two cycle clock. During a first clock cycle, switches designated Φ 1  are closed and switches designated Φ 2  are open; whereas, during a second clock cycle, switches Φ 1  are open and switches Φ 2  are closed. 
   During the first clock cycle, input capacitors C 11 , C 12  of the first stage  41  are charged by an input voltage V in . This process is also referred to herein as the sampling phase. Concurrently, the charged stored (from a previous clock cycle) in the input capacitors C 21 , C 22  of the second stage  42  is integrated by the operational amplifier OP 2  of the second stage  42  to generate a residual output voltage V out2 . This residual output voltage V out2  is based on reference voltages as well as digital output from the comparator. This process is also referred to herein as the integration phase. It should be noted that the operational amplifier OP 1  of the first stage  41  is not active during this clock cycle. 
   Conversely, during the second clock cycle, input capacitors C 21 , C 22  of the second stage  42  are charged by an input voltage V out1 ; whereas, the charged stored in the input capacitors C 11 , C 12  of the first stage  41  is integrated by the operational amplifier OP 1  of the first stage  41  to generate a residual output voltage V out1 . The residual output voltage V out1  from the first stage serves as the input voltage to the second stage as shown in  FIG. 4A . 
   In accordance with the present invention, each operational amplifier is only biased during the integration phase to reduce power consumption. Referring to  FIGS. 4A and 4B , a current source  44  may be electrically connected to each of the operational amplifiers OP 1 , OP 2 . In addition, switching elements  46 ,  47  may be located between the current source  44  and each of the operational amplifiers OP 1 , OP 2 . During the first clock cycle or phase (as determined in step  50 ), a bias current is supplied to the operational amplifier OP 2  of the second stage  42 , but not to the operational amplifier OP 1  of the first stage  41  (as shown in step  52 ). Conversely, during the second clock cycle, a bias current is supplied to the operational amplifier OP 1  of the first stage  41 , but not to the operational amplifier OP 2  of the second stage  42  (as shown in step  52 ). In other words, each operational amplifier is biased only during its active phase, thereby reducing the power consumption of the circuit. 
   An exemplary circuit for biasing the operational amplifiers is depicted in  FIG. 5 . In particular, a biasing circuit  60  employs a current mirror configuration as is well known in the art. In operation, transistors  62 , 64  serve as switching elements, which control when a bias current is applied to a given operational amplifier. However, it is readily understood that other circuit configurations for biasing the operational amplifiers are within the broader aspects of the present invention. 
   In alternate embodiments depicted in  FIGS. 6A and 7A , a fractional portion of the bias current may be supplied to each of the operational amplifiers during the sampling phase. In other words, each operational amplifier is supplied with a full bias current during its integration phase and with a fractional portion of the full bias current during its sampling phase. Although not limited thereto, the fractional biasing current can be 25% of the full bias current. By supplying a fractional portion of bias current, the operational amplifiers are able to maintain a common mode state during the sampling phase. The present invention reduces power consumption of the circuit while maintaining the response of the operational amplifier residing therein. 
   Referring to  FIGS. 6A and 6B , variable current sources  70  may be electrically connected to each of the operational amplifiers OP 1 , OP 2 . During the first clock cycle or phase (as determined in step  74 ), the variable current source  70  of the second stage provides a bias current having a high level to the operational amplifier OP 2  of the second stage  42  (as shown in step  76 ). The variable current source of the first stage provides a low bias current to the operational amplifier OP 1  of the first stage  41  (as shown in step  76 ). 
   During the second clock cycle or phase (as determined in step  74 ), the variable current source  70  provides a bias current having a high level to the operational amplifier OP 1  of the first stage  42  (as shown in step  78 ). The variable current sources  70  provide a low bias current to the operational amplifier OP 2  of the second stage  41  (as shown in step  78 ). In other words, one operational amplifier is biased by a high current level during its active phase and the other operational amplifier is biased by a low current level during its inactive phase, and vice-versa, to reduce the power consumption of the circuit. 
   The variable current sources  70  may receive clock information such as a clock signal, Φ 1  and/or Φ 2  as an input. In  FIG. 6A , the variable current source  70  of the first stage receives Φ 2  and the variable current source of the second stage receives Φ 1 . As can be appreciated, the variable current sources may receive other signals that will allow the variable current source to determine when the associated stage is active or inactive. 
   Referring to  FIGS. 7A and 7B , two current sources I 1  and I 2  may be selectively connected to each of the operational amplifiers OP 1 , OP 2  depending upon the active/inactive phase of the stage. One of the two current sources is associated with a switch that closes during the active stage and opens during the inactive stage. During the first clock cycle or phase (as determined in step  84 ), the operational amplifier OP 2  of the second stage  42  (as shown in step  86 ) is biased by both current sources I 1  and I 2 . The operational amplifier OP 1  of the first stage  41  (as shown in step  86 ) is biased by one current source I 2 . 
   During the second clock cycle or phase (as determined in step  84 ), the operational amplifier OP 2  of the second stage  42  (as shown in step  76 ) is biased by one current source I 2 . The operational amplifier OP 1  of the first stage  41  (as shown in step  76 ) is biased by both current sources I 1  and I 2 . In other words, one operational amplifier is biased by a high current level during its active phase and the other operational amplifier is biased by a low current level during its inactive phase, and vice-versa, to reduce the power consumption of the circuit. 
   Referring now to  FIG. 8A , a circuit  100  having active and inactive phases during operation is shown. The active and inactive phases can be regularly periodic, or in other words, alternating at regular intervals. Alternately, the active and inactive phases can be irregularly periodic, or in other words, alternating between active and inactive phases at different intervals. A power supply  110  supplies first and second bias signals during the regular and/or irregular periodic active and inactive phases of the circuit  100 , respectively. The second bias signal is lower than the first bias signal to reduce power consumption. The second bias signal can be lower during the inactive phase because the inactive phase occurs after an active phase. The circuit has already settled during the active state and is operating in steady state. When the circuit transitions to the inactive state, the circuit needs less power to operate. 
   The circuit  100  may provide phase feedback information to the power supply  110  if needed. The power supply  110  can be a current source such as those described above, a voltage source or any other suitable power supply. The power supply  110  can include two power supplies that are switched in a manner similar to current sources shown above in  FIG. 7A  or a variable or multiple output power supply similar to the variable current sources shown in  FIG. 6A . Example circuits  100  include switched capacitor filters such as those described in U.S. Pat. No. 6,400,214, filed Aug. 28, 2000 to Aram et al., which is hereby incorporated by reference in its entirety and digital to analog converters such as those described above. 
   Referring now to  FIG. 8B , exemplary regular periodic active and inactive phases for the circuit in  FIG. 8A  are shown. The power supply  110  generates first and second bias signals during the regular periodic active and inactive phases, respectively. Referring now to  FIG. 8C , exemplary irregular periodic active and inactive phases for the circuit in  FIG. 8A  are shown. The power supply  110  provides first and second bias signals during the irregular periodic active and inactive phases, respectively. 
     FIG. 9A  illustrates a circuit  120  including multiple sub-circuits  122 - 1 ,  122 - 2 , . . . , and  122 -n having active and inactive phases during operation. The active and inactive phases of the sub-circuits  122 - 1 ,  122 - 2 , . . . , and  122 -n may be in-phase and/or out-of-phase with respect to one another. The active and inactive phases may be regular and/or irregular periodic. One or more power supplies  126 - 1 ,  126 - 2 , . . . , and  126 -n supply the first and second bias signals during the active and inactive phases, respectively. A single power supply  128  with multiple outputs may be used to provide outputs to each stage of the circuit  120 . The circuit  120  and/or the sub-circuits  122 - 1 ,  122 - 2 , . . . , and  122 -n may provide phase feedback signals to the power supplies  126 - 1 ,  126 - 2 , . . . , and  126 -n if needed. Interconnections between the sub-circuits  126  may be varied from those shown. The circuit  120  may or may not be pipelined. 
   Referring now to  FIGS. 10A–14B , exemplary first and second bias signals are shown that can be used to bias the circuits shown in  FIGS. 1–9 . Generally, the first bias signals occur during the active phase and have a signal level that is higher than the second bias signal that occurs during the inactive phase. The first and second bias signals can be regular or irregular periodic. The first and/or second signals can also be square-waveform or constant signals, stepped signals, linearly changing signals and/or non-linearly changing signals. 
   Referring now to  FIGS. 10A and 10B , exemplary constant signals are shown.  FIG. 10A  illustrates a square-waveform bias signal and a zero bias signal for the active and inactive phases, respectively.  FIG. 10B  illustrates the square-waveform bias signal of  FIG. 10A  and a non-zero bias signal for the active and inactive phases, respectively. 
   Referring now to  FIGS. 11A and 11B , exemplary stepped signals are shown.  FIG. 11A  illustrates a stepped bias signal and a zero bias signal for the active and inactive phases, respectively. The stepped bias signal may include a high startup level followed by a lower steady-state level.  FIG. 11B  illustrates the stepped bias signal of  FIG. 11A  and a non-zero bias signal for the active and inactive phases, respectively. 
   Referring now to  FIGS. 12A and 12B , exemplary linearly changing signals are shown.  FIG. 12A  illustrates a linearly changing bias signal and a zero bias signal for the active and inactive phases, respectively.  FIG. 12B  illustrates the linearly changing bias signal of  FIG. 12A  and a non-zero bias signal for the active and inactive phases, respectively. 
   Referring now to  FIGS. 13A and 13B , exemplary non-linearly changing signals are shown.  FIG. 13A  illustrates an exponential bias signal and a zero bias signal for the active and inactive phases, respectively.  FIG. 13B  illustrates the exponential bias signal of  FIG. 13A  and a non-zero bias signal for the active and inactive phases, respectively. 
   Referring now to  FIGS. 14A and 14B , other exemplary non-linearly changing signals are shown.  FIG. 14A  illustrates a stair-stepped bias signal and a zero bias signal for the active and inactive phases, respectively.  FIG. 14B  illustrates the stair-stepped bias signal of  FIG. 14A  and a non-zero bias signal for the active and inactive phases, respectively. 
   As can be appreciated by skilled artisans, the present invention significantly reduces power consumption for devices having active and inactive periods. In addition, skilled artisans will appreciate that other bias waveforms can be used for the active and inactive phases in addition to those examples shown in  FIGS. 10A–14B . Furthermore, the active and inactive phases need not have the same periods, for example as shown in  FIGS. 14A and 14B . The duration of the active and/or inactive period may also vary from one active phase and/or inactive phase to another. While the first bias waveforms in  FIGS. 11A–14B  are increasing waveforms, decreasing waveforms can also be used. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.