Abstract:
An integrated circuit dual port memory provides a preferred port which is always granted priority of memory access when memory access requests arrive simultaneous from both ports of the dual port memory. To implement this priority scheme, the memory request signal from the preferred port controls a multiplexor to select the input signals from the preferred port over the input signals from the non-preferred port. The memory request signal from the preferred port also serves as a busy signal to block a simultaneous memory access by the non-preferred port. In one embodiment, memory request signals of both ports are latched into registers clocked by the same clock signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to memory integrated circuits and, in particular, relates to multiport memory integrated circuits. 
     2. Discussion of the Related Art 
     In a high performance computer system, a dual-ported memory allows simultaneous memory access by, for example, both the central processor (CPU) and certain input and output (I/O) peripheral circuits. An example of such a computer system 100 is shown in FIG. 1. As shown in FIG. 1, computer system 100 comprises CPU 101, memory system 102, and I/O system 103. CPU 101 accesses memory system 102 via bus 104, and I/O system 103 accesses memory system 102 via bus 105. In computer system 100, both ports of a dual port memory are provided the same priority. Thus, when simultaneous memory accesses are pending at both ports, an arbitration circuit is necessary to resolve the order in which the memory is accessed. However, in many applications requiring a shared memory, e.g. in digital signal processors, certain devices often require immediate access on-demand. In those applications, a delay resulting from an existing memory access by another device, or due to latency in the arbitration circuit, may lose data unacceptably. 
     Various integrated circuit components have been designed to be used in a conventional memory array of a dual-port memory system. Such components include (i) QS7316 dual port random access memory (RAM), available from Quality Semiconductor Inc., Santa Clara, Calif.; (ii) M79018DX and M78004PX dual port RAMs, both available from AT&amp;T Technologies Inc., Allentown, Pa., and (iii) various dual port SRAMs, e.g. IDT7133, from Integrated Device Technology, Inc., Santa Clara, Calif. 
     The QS7316 dual-port RAM referenced above is a clock-based dual port RAM supporting both random access and burst mode access from either or both ports. In the QS7316 dual-port RAM, neither port has a priority over the other port. However, the initial access latency in the QS7316 dual-port RAM is two to four clock cycles. The additional latency is required to synchronize accesses from both ports. Under burst mode, each port can be accessed every cycle after the initial access. The disadvantage of this component is the latency which is incurred when accessing either port. 
     The M79018DX and M78004PX components grant equal priority to the two ports of each component. Unlike the Q7316 integrated circuit, neither the M79018DX nor the M78004PX requires a clock signal input. However, in each of the M79018DX and the M78004PX components, memory access at one port can be held up for a long time period, while the memory access at the other port completes. 
     In the IDT7133 integrated circuit component, on-chip arbitration logic sets a busy flag to delay memory access by one of the ports, when simultaneous memory accesses from both ports occur. Under this scheme, memory access from either port may be blocked by the busy flag and be subject to an indefinite delay. 
     SUMMARY OF THE INVENTION 
     According to the present invention, a structure and a method allowing unrestricted memory access from a preferred port of a dual port memory are disclosed. 
     In one embodiment, whenever simultaneous memory accesses from both ports of a dual port memory are requested, a priority circuit in the dual port memory grants, at an edge of a clock signal, memory access to a preferred port, while providing a &#34;busy&#34; signal to block memory access by the other lower priority port. In this embodiment, registers are provided to store the data and the memory address associated with the blocked memory access. The stored data and address of the blocked memory access allows the blocked memory access to proceed immediately when the memory access at the preferred port is completed. 
     The present invention allows unrestricted memory access from the preferred port without incurring the latency characteristic of prior art arbitration circuits, and without requiring the memory access at the preferred port to wait for the completion of a prior memory access at the lower priority port. The present invention is suitable for an application in which memory access by one device is time-critical, such as in some real-time or digital signal processing applications. 
     The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a computer system 100 having a conventional dual-ported memory architecture. 
     FIG. 2 shows the organization of a dual port memory 200, in accordance with the present invention. 
     FIG. 3 is a timing diagram illustrating various write memory cycles of dual port memory 200. 
     FIG. 4 is a timing diagram illustrating various read memory cycles of dual port memory 200. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     One embodiment of the present invention is illustrated in FIG. 2. In this embodiment, an integrated circuit provides a dual port memory 200 that is accessible by ports A and B. In FIG. 2, port A is shown on the left hand side, and port B is shown on the right hand side. 
     As shown in FIG. 2, memory array 201 is accessed by an address presented on address bus 231. During a write operation, data on data bus 232 is written into memory array 201 when signal WR is asserted on lead 233. During a read operation, data stored at the accessed memory location is provided on data output bus 234. 
     Data from port A to be written into memory array 201 are provided on data bus 251 and received into latch 216 when latch enable signal LE(A) on lead 270 becomes active. Likewise, data from port B to be written into memory array 201 are provided on data bus 252 and received into latch 215 when latch enable signal LE(B) on lead 271 becomes active. 
     At port A, an access type signal R/W(A) and address signals Address(A) are respectively provided on lead 253 and address bus 254. A control signal CS(A) on lead 255 is asserted when a memory access request is pending at port A. A clock signal CLK provided on lead 256 enables register 217 to store signals Address(A), CS(A), and R/W(A). As an output signal (on lead 258) of register 217, control signal CS(A) directs, during a memory access from port A, multiplexer 202 to select as its output signals on data bus 232, lead 235 and address bus 231, respectively, latch 216&#39;s output data signals Data(A) on bus 259, register 217&#39;s output signal R/W(A) signal on lead 260 and register 217&#39;s output address signals Address(A) on bus 261. The signal on lead 235 is gated with the clock signal CLK to provide the WR signal on bus 233. When a memory access from port A is pending, signal CS(A) is provided on lead 262 as a Busy signal to block memory access from port B. 
     Output enable signal OE(A) on lead 257 is asserted at the end of a read memory cycle to enable buffer 206 to place the data in latch 205 onto data bus 251. Latch 205 latches the output data of memory array 201 on data bus 234 during a read memory access from port A. 
     At port B, a memory request signal MemReq(B) on lead 263 indicates a pending memory request. Register 214 receives memory request signal MemReq(B) from lead 263, address signals Address(B) from address bus 264, and access type signal R/W(B) from lead 265. Output enable signal OE(B) on lead 266 enables buffer 208 to place latch 207&#39;s output data on bus 267 onto data bus 252. 
     When Busy is not asserted, i.e. there is not a memory access pending from port A, and the last memory access from port A is completed, the CS(A) signal is inactive, so that multiplexer 202 selects latch 215&#39;s output data signals Data(B) for output on bus 232, register 214&#39;s access type signal R/W(B) for output on lead 235, and register 214&#39;s address signals Address(B) for output on bus 231. 
     When a memory access from port B arrives during a memory cycle in which signal Busy is inactive, memory access is granted to port B. When a memory request from port B arrives in a memory cycle during which Busy is active, the memory access from port B is blocked, since the output of gate 271 is at logic low. Signal Busy also prevents latch 207 from latching the output data of memory array 201 on output data bus 234 by forcing, the output signal of AND gate 209 on lead 268 to logic low. The memory access from port B is not allowed to proceed until Busy is deasserted, enabling signal MemReq(B) to be received into register 214. 
     Since port A is always provided priority when memory accesses are requested from both ports simultaneously, i.e. prior to a rising clock edge of clock signal CLK, the present invention is suitable for use in applications in which one device requiring access to a memory system cannot afford to wait for the completion by another device accessing the memory. In the present embodiment, since the same clock signal is used to clock registers 214 and 217, a request in preferred port A is granted access with no latency incurred. 
     FIG. 3 is a timing diagram illustrating various write memory cycles of dual port memory 200. As shown in FIG. 3, at time t 1 , a write memory request arrives at port A, asserting CS(A), and providing the address signals Address(A) and access type signal R/W(A). In response to this memory request from port A, signal Busy is asserted. 
     At time t 1 , no memory request from port B is pending. The data provided on data bus 251 is written into memory array 201 at the end of the memory cycle of time t 1 . 
     At time t 2 , a write memory request arrives at port B, asserting signals MemReq(B) and R/W(B), and providing address signals Address(B). Since no memory request from port A is pending, signal Busy is inactive. Consequently, the data provided on data bus 252 is written into memory array 201 at the end of the memory cycle of t 2 . 
     At time t 3 , both memory access request signals CS(A) and MemReq(B) are asserted. Consequently, signal Busy is asserted and memory access from port B is blocked. However, data on data bus 252 is received into latch 215, and the address signals Address(B) and the access type signal R/W(B) are received into register 214. During the memory cycle of t 3 , data received from data bus 251 (Data(A)) are written into memory array 201. 
     At time t 4 , another memory access from port A blocks the pending memory access request at time t 3  from port B. 
     At time t 5 , a port A memory request is not pending, so that signal Busy deasserted after the rising edge of the system clock CLK. Consequently, the pending memory request from port B at time t 3 , which is stored in latch 215 and register 214, is allowed to proceed, so that the data in latch 215 is written into memory array 201. 
     During the memory cycle of time t 6 , the MemReq(B) signal is not asserted and there is no pending memory access from port A. Thus, to memory array 201, the memory cycle of time t 6  is treated like a read memory cycle from port B. However, latch 207 is not enabled, so that the data on memory bus 234 is simply disregarded. The memory cycle of time t 7  is a regular write cycle from port B. 
     FIG. 4 shows various read cycles of dual port memory 200. As shown in FIG. 4, at time t 1 , memory request signal CS(A) from port A is asserted. In response to signal CS(A), signal Busy is asserted to block any memory access from port B. At the same time, type access signal R/W(A) on lead 253 indicates a read access to the address provided on address bus 254. As a result of the active Busy signal, multiplexor 202 selects the address signals Address(A) on address bus 261 the access type signal R/W(A) on lead 260, which have previously been received into register 217 from address bus 254 and lead 253 respectively. The data output of memory array 201 at output bus 234 is provided at a later time during the memory cycle of t 1 . 
     At time t 2 , memory request signal MemReq(B) is asserted. Since there is not a pending request from port A, the read operation from port B is allowed to proceed. As a result, the data output of memory array 201 is available on data bus 234 at the latter part of the memory cycle of t 2 . Output signal OE(B) places via buffer 208 on data bus 252 the output data of data bus 234. 
     At time t 3 , both memory access request signals CS(A) and MemReq(B) from ports A and B are asserted. In response to signal CS(A), signal Busy is asserted to block memory access by port B. However, the address signals Address(B) and access type signal R/W(B) from port B are received into register 214. The output data of memory array 201, corresponding to the read memory request from port A, are provided on data bus 234 at the latter part of the memory cycle of time t 3 . 
     At time t 4 , the read memory request stored in register 214 remains blocked, due to another memory request from port A asserting signal CS(A). The output data of memory array 201, corresponding to port A&#39;s read memory access, are made available on data bus 234 at the latter part of the memory cycle of time t 4 . 
     At time t 5 , no memory access request arrives at port A. Accordingly, the memory request from port B, which is pending since time t 3 , is allowed to proceed. The output data of memory array 201, corresponding to port B&#39;s read memory access request of time t 3 , are made available on data bus 234 at the latter part of the memory cycle of time t 5 . 
     At time t 7 , a read memory access request arrives from port B. Since no pending memory access is pending from port A, read operation proceeds in the same manner as the read access of memory cycle of time t 2 . 
     The detailed description provided above is intended to be illustrative of the disclosed embodiments, and is not intended to be limiting of the present invention. Numerous modifications and variations are possible within the scope of the present invention. The present invention is defined by the following claims appended hereto.