Abstract:
A chopper type comparator, for comparing a first analog input signal voltage and a second analog input signal voltage to each other, includes an input portion for inputting the first and second analog input signals, respectively, and selectively outputting the first and second analog input signals, and a comparison portion for providing a result of comparison of the first and second analog input signals. The comparison portion includes a capacitor connected to a selected output of the input means at one terminal of the capacitor, an inverter having an MOS FET and of which an input side thereof connected to the other terminal of the capacitor, a path connected in parallel between the input and an output of the inverter across a analog switch, a switch control portion for controlling an electrical connection state of the analog switch in response to selection of the output of the input portion, the analog switch having a suppressing portion for suppressing transmission of a voltage variation to the input side of the inverter from the output side thereof across the analog switch.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to comparators, and in particular, to chopper type comparators. 
     2. Prior Art 
     Chopper type comparators are conventionally known, for example, the circuit having a design such as that shown in FIG. 1. In the illustrated circuit, analog input voltage terminals 1 and 2 are provided, to each of which respective analog input voltage V 1  and V 2  are supplied. The analog input voltage terminal 1 connects to an analog switch 3 which is in turn made up of an N channel MOS (metal oxide semiconductor) transistor 3 1  and a P channel MOS transistor 3 2 . The analog switch 3 is constructed such that when a gate a is low and a gate b is high in terms of the voltage levels applied thereto, current is conducted therethrough, whereas when the gate a is high and the gate b is low, current is not conducted. 
     A control input voltage terminal 4 is provided, to which a control input voltage V c  is supplied. The control input voltage V c  is inverted in an inverter 5. An analog switch 6 connects to the output terminal of the analog switch 3. The analog switch 6 is made up of an N channel MOS transistor 6 1  and a P channel MOS transistor 6 2 , and is identical in structure and operation to the analog switch 3 described above. 
     One terminal of a capacitor 7 connects to the output terminals of the analog switch 3 and the analog switch 6 at a terminal T 1 . The other terminal of the capacitor 7 connects to the input terminal of an inverter 8 and with one terminal of an analog switch 9 at a terminal T 2 . As the analog switches 3 and 6, the analog switch 9 is made up of an N channel MOS transistor 9 1  and a P channel MOS transistor 9 2 . Each of elements 7 through 9 described above together form a comparator unit 10. In certain implementations of the kind of the chopper type comparator shown in FIG. 1, the multiple comparator units 10 are incorporated and connected together thereby forming a multiple-stage comparator. An output terminal 11 for the comparator unit 10 and for the chopper type comparator as a whole is provided, which is connected to the output terminal of the inverter 8 as well as with the analog switch 9. 
     With the chopper type comparator as described above, the gate a of the analog switch 3 and that of the analog switch 9 and and the gate b of the analog switch 6 are all directly connected to the control input voltage terminal 4, whereas the gate b of the analog switch 3 and that of the analog switch 9 and the gate a of the analog switch 6 are all directly connected to the output of the inverter 5 wherein the control input voltage V c  applied at the control input voltage terminal 4 is inverted. As a result, when the control input voltage V c  applied at the control input voltage terminal 4 is low in terms of the voltage level applied thereto, the gate a of the analog switch 3 and that of the analog switch 9 and the gate b of the analog switch 6 are all in a low state and the gate b of the analog switch 3 and that of the analog switch 9 and the gate a of the analog switch 6 are all in a high state. Conversely, when the control input voltage V c  applied at the control input voltage terminal 4 is high, the gate a of the analog switch 3 and that of the analog switch 9 and the gate b of the analog switch 6 are all in a high state and the gate b of the analog switch 3 and that of the analog switch 9 and the gate a of the analog switch 6 are all in a low state. 
     Because of the features described in the preceding paragraph, the analog switches 3 and 9 are always in the same state and the analog switch 6 is always in the opposite state compared with the analog switches 3 and 9. In other words, when the control input voltage V c  applied at the control input voltage terminal 4 is low, the analog switch 6 is nonconductive and the analog switches 3 and 9 are conductive, whereas when the control input voltage V c  applied at the control input voltage terminal 4 is high, the analog switch 6 is conductive and the analog switches 3 and 9 are nonconductive. 
     Accordingly, when the analog input voltages V 1  and V 2  are simultaneously applied to the analog input voltage terminals 1 and 2, respectively, and the control input voltage V c  applied at the control input voltage terminal 4 is low, the analog input voltage V 1  is output from the analog switch 3 and applied to the capacitor 7 at the terminal T 1 . The opposite terminal T 2  of the capacitor 7 is connected directly with one terminal of the analog switch 9, and with the other terminal of the analog switch 9 after being electronically inverted in the inverter 8. Because the analog switch 9 is conductive when the control input voltage Vc is low, a short circuit is effectively formed between the terminal T 2  and the terminal T 3 . 
     The above mentioned inverter 8 consists of a CMOS (complementary metal oxide) circuit constructed in turn from complementary FETs (complementary field effect transistors). When the properties of the FETs incorporated in the CMOS circuit making up the inverter 8 are highly uniform, and when the control input voltage V c  applied at the control input voltage terminal 4 is low, the voltage at the terminals T 2  and T 3  is one half of a supplied power source voltage V DD  which is supplied to the inverter 8, in other words, the voltage between the terminals T 2  and T 3  is equal to (1/2)·V DD . Under these conditions, the potential difference across the capacitor 7 is equal to (V1- (1/2)·V DD . In response to this potential difference across the capacitor 7, that is, in response to this potential difference between the terminals T 1  and T 2 , an electrical charge is accumulated in the capacitor 7. 
     When the control input voltage V c  applied at the control input voltage terminal 4 is then caused to jump to high, the gate a of the analog switch 3 and that of the analog switch 9 and the gate b of the analog switch 6 are then all in a high state and the gate b of the analog switch 3 and that of the analog switch 9 and the gate a of the analog switch 6 are all in a low state. Accordingly, the analog switch 6 becomes conductive and the analog switches 3 and 9 become nonconductive, for which reason the analog input voltage V 2  output from the analog switch 6 is applied to the capacitor 7 at the terminal T 1 . Because the analog switch 9 is nonconductive and thus acts as an open circuit when the control input voltage V c  is high, the opposite terminal T 2  of the capacitor 7 at the terminal T 2  is effectively connected only with the input terminal of the inverter 8, and the output terminal of the inverter 8 is effectively connected only with the output terminal 11. 
     Before the control input voltage V c  applied at control input voltage terminal 4 was caused to jump to high, the potential difference across the capacitor 7 was equal to V 1  -(1/2)·V DD . thus the charge accumulated in the capacitor 7 was in response to a potential difference of (V 1  -(1/2)·V DD ) thereacross. When the control input voltage V c  jumps to high, and the voltage at the terminal T 1  therefore changes to V 2 , the voltage at terminals T 2  then becomes to (V 2  -V 1  +(1/2)·V DD ). 
     Referring to FIG. 2 which shows a graph of the characteristic curve of the output voltage V out  of the inverter 8 as a function of the input voltage V in  thereof, it can be seen that the slope is greatest when the analog switch 9 is in the conducting state, that is, when the inverter 8 is connected as a short circuit. For this reason, when the input voltage V in  is in the vicinity of (1/2)·V DD , small changes in the magnitude thereof result in large changes in the output voltage V out . In consideration of these characteristics, it can be seen that when V 2  &gt;V 1 , the output voltage level at the terminal T 3  of the inverter 8 will be low, whereas when V 1  &gt;V 2 , that of the terminal T 3  will be high. Based on these characteristics, comparison of the magnitude of the voltage V 1  relative to the magnitude of the voltage V 2  can be carried out. By connecting a plural of the comparator units 10 such as multiple stages, the overall gain of the chopper type comparator can be increased. 
     With this type of conventional chopper type comparator, when the analog switch 9 is turned on or off, in particular, when analog switch 9 transits from a conducting state to a nonconducting state, spike noise is mixed with the analog input voltage through the gate electrostatic capacitance, and is thereby made to introduce the spike noise. Thus, the potential at terminal T 2  deviates from (1/2)·V DD  by a voltage variation ΔV A . 
     Furthermore, with this kind of chopper type comparator, when the potential at the terminal T 3  at the output lead of the inverter 8 changes from (1/2)·V DD  to high, or from (1/2)·V DD  to low, via junction capacitance in the analog switch 9, the change in potential at the terminal T 3  leads to a change of potential at the terminal T 2  by the voltage variation ΔV A . 
     When the above described voltage variation ΔV A  is greater than V 2  -V 1 , it becomes impossible to compare the potential of T 3  and T 2 . For this reason, it is important to minimize the magnitude of any voltage variation ΔV A  so as to provide sufficiently accurate comparator operation. By selecting the capacitor 7 such that the capacitance thereof is relatively large relative to the charge of the gate electrostatic capacitance and the junction capacitance of the analog switch 9, the magnitude of the voltage variation ΔV A  can be diminished. Herein, the junction capacitance of the analog switch 9 is defined as four parts; that is, a PN junction capacitance which exists between a source and a substrate in P channel; a PN junction capacitance which exists between a drain and a substrate in P channel; a PN junction capacitance which exists between a source and a substrate in N channel and a PN junction capacitance which exists between a drain and a substrate in an N channel. 
     Thus, by increasing the capacitance of the capacitor 7 in the type of the conventional chopper type comparator shown in FIG. 1, the accuracy thereof was improved. Increasing the capacitance of the capacitor 7, however, has the effect of prolonging the time required for charging and discharging the capacitor 7, thereby leading to a marked loss in ability to carry out high speed comparisons which is decidedly undesirable. 
     SUMMARY OF THE INVENTION 
     In consideration of the above, it is an object of the present invention to provide a chopper type comparator which is capable of carrying out highly accurate comparisons with an extremely rapid response. 
     So as to achieve the above stated object, the present invention provides a chopper type comparator for comparing voltage of a first analog input signal and voltage of a second analog input signal each other, comprising: input means for inputting the first and second analog input signals respectively and selectively outputting the first and second analog input signals; comparison means for providing a result of comparison of the first and second analog input signals, comprising, a capacitor connected to a selected output of the input means at one terminal of the capacitor, an inverter having an MOS field effect transistor and of which an input side thereof connected to the other terminal of the capacitor, a path connected in parallel between the input and an output of inverter across a analog switch, switch control means for controlling an electrical connection state of the analog switch in response to selection of the output of the input means, the analog switch having a suppressing means for suppressing transmission of a voltage variation to the input side of the inverter from the output side thereof across the analog switch, wherein the analog switch further comprises a circuit capable of suppressing spike noise when the analog switch opens and closes. 
     With this device, through opening and closing operation of the above described first, second and multiple serially connected third analog switches, the first analog input voltage which is applied to the first analog switch and the second analog input voltage which is applied to the second analog switch are compared, and a comparison voltage is output. With this chopper type comparator, when the multiple serially connected third analog switches close, an electrical connection is created between the input and output terminals of the above mentioned inverter, thus effectively creating a short circuit across the inverter. When the multiple serially connected third analog switches open, the potential at each interconnection point between two adjacent third analog switches is equal to the potential when the input and output terminals of the above mentioned CMOS inverter are connected to one another, whereby variation of the potential at the output terminal of the inverter has no effect on the potential at the input terminal of the thereof. 
    
    
     BRIEF EXPLANATION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing the layout of a conventional chopper type comparator. 
     FIG. 2 is a graph which demonstrates the input-output characteristics of an inverter 8 which can be seen as a component of the conventional chopper type comparator shown in the circuit diagram of FIG. 1. 
     FIG. 3 is a circuit diagram showing the layout of a chopper type comparator of a first preferred embodiment of the present invention. 
     FIG. 4 is a circuit diagram showin the layout of a chopper type comparator of a second preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, a chopper type comparator of the first preferred embodiment of the present invention will be described with reference to FIG. 3. In FIG. 3, components which correspond to components in the conventional circuit shown in FIG. 1 will retain the original identifying numeral, and their description will not be repeated. 
     As the diagram shows, analog switch 12 and 13 are provided to be connected in series with respect to each another, and together, are arranged in parallel with CMOS inverter 8. An analog switch 12 is a MOS semiconductor and is made up of a transistor 12 1  and transistor 12 2 . Each of transistor 12 1  and transistor 12 2  is an N channel type and a P channel type, and each has an identical gate surface area A. On the other hand, conventional analog switches, that is, the analog switch switches 3, 6, and 9 are designed such that the resistance of P channel type transistor in conducting is equal to that of N channel type transistor, so that P channel type transistor is made physically larger than N channel type transistor because the mobility of the electrical charge in P channel type transistor is different from that of N channel type transistor. Thus, the gate surface areas of the conventional transistors are not equal to each other. The gate a of the analog switch 12 is connected to the control voltage input terminal 4 and the gate b is connected to the output terminal of the inverter 5. The input terminal of the analog switch 12 connects to the output terminal of an analog switch 13, and the output terminal of the analog switch 12 connects to the output terminal of the inverter 8 at the terminal T 3 . 
     The analog switch 13 is also an MOS semiconductor and is made up of a transistor 13 1  and a transistor 13 2 , each of which comprises an N channel type and a P channel type, and an identical gate surface area which is one half of the gate surface area of transistor 12 1  and transistor 12 2 . The gate a of the analog switch 13 is connected to the gate b of the analog switch 12, and the gate b of the analog switch 13 is connected to the gate a of the analog switch 12. The input terminal of analog switch 13 is connected to the input terminal of the inverter 8 and to the terminal T 2  of the capacitor 7. Additionally, the input and output terminals of the analog switch 13 are connected together, thereby forming a short circuit. 
     Through the above described construction, when a first and second analog input voltage V 1  and V 2  are simultaneously supplied to the analog input voltage terminal 1 and the analog input voltage terminal 2, respectively, and a control voltage V c  which is low is applied to the control voltage input terminal 4, the gate a of the analog switch 3, the gate b of the analog switch 6, the gate a of the analog switch 12 and the gate b of the analog switch 13 are each in a low state. Since the output terminal of the inverter 5 is high under these circumstances, the gate b of the analog switch 3, the gate a of the analog switch 6, the gate b of the analog switch 12 and the gate a of the analog switch 13 are each in a high state. Accordingly, the analog switches 3 and 12 is in a conductive state, and analog switch 6 are each in a nonconductive state. 
     With the device of the present invention, because the gate surface area of the N channel and the gate surface area of the P channel of the analog switch 12 both have areas A, the magnitude of the spike noise which penetrates the electrostatic capacitance is smaller than the conventional type when analog switch 12 is in a conductive state. Due to the fact that the analog switch 13 is incorporated into the device of the present invention, residual noise due to differing junction capacitance is extremely small. By virtue of the fact that the analog switch 13 is on/off, the spike noise ΔV A  generated by the analog switch 12 is deleted by using the noise, having reverse polarity to the spike noise ΔV A , which is generated by the analog switch 13, because the voltage applied to the gate of the analog switch 12 is the reverse of that to the analog switch 13. 
     Since the analog switch 3 is in a conductive state, the analog input voltage V 1  is output from the analog switch 3 and applied to the capacitor 7 at the terminal T 1 . The opposite terminal of the capacitor 7 at the terminal T 2  connects directly with one terminal of the analog switch 12, and with the other terminal of the analog switch 12 through the inverter 8. Since the analog switch 12 is conductive when the control input voltage V c  is low, a short circuit is effectively formed between the terminal T 2  and the terminal T 3 . 
     Accordingly, the voltage between terminals T 2  and T 3  is one half of a supplied power source voltage V DD , in other words, the voltage between terminals T 2  and T 3  is equal to (1/2)·V DD . Under these conditions, the spike noise is extremely small and no voltage variation ΔV A  develops. With the circuit as thus described, the potential difference across the capacitor 7 is equal to (V 1  -(1/2)·V DD ). In response to this potential difference across the capacitor 7, that is, in response to this potential difference across terminals T 1  and T 2 , a corresponding electrical charge is accumulated in the capacitor 7. 
     When the control input voltage V c  applied at control input voltage terminal 4 is then caused to jump to high, the gate a of the analog switch 3 and that of the analog switch 12 and the gate b of the analog switch 6 and that of the analog switch 13 are then all in a high state. Because the output of the inverter 5 is low, the gate b of the analog switch 3 and that of the analog switch 12 and the gate a of the analog switch 6 and that of the analog switch 13 are all in a low state. Accordingly, the analog switches 6 and 13 become conductive and the analog switches 3 and 12 become nonconductive. 
     With the device of the present invention, because the gate surface area of the N channel and the gate surface area of the P channel of the analog switch 12 both have area A/2, the magnitude of the spike noise which penetrates the electrostatic capacitance is smaller than the conventional type when analog switch 13 is in a conductive state. Due to the fact that the analog switch 13 is incorporated into the device of the present invention, residual noise due to differing junction capacitance is extremely small. 
     Since the analog switch 6 is in a conductive state, the analog input voltage V 2  is output from the analog switch 6 and applied to the capacitor 7 at the terminal T 1 . In this state, the potential difference across the capacitor 7 is equal to (V 1  -(1/2)·V DD ). In response to this potential difference across the capacitor 7, that is, in response to this potential difference across terminals T 1  and T 2 , a corresponding electrical charge is accumulated in the capacitor 7. Accordingly, the lead of the capacitor 7 at the terminal T 2  has a potential which varies from (1/2)·V DD  to (V 2  -V 1  +(1/2)·V DD ). 
     In consideration of these characteristics, it can be seen that when V 2  &gt;V 1 , the terminal T 3  at the output lead of the inverter 8 will be low, whereas when V 1  &gt;V 2 , the terminal T 3  will be high. Based on these characteristics, comparison of the magnitude of voltage V 1  relative to the magnitude of voltage V 2  can be carried out. With this type of chopper type comparator, due to the fact that the analog switch 12 and the analog switch 13 are provided, when the analog switch 12 opens or closes, the amount of spike noise generated is exceedingly small. As a result, not only is the rate at which comparison operations can be carried out improved, but furthermore, a capacitor having relatively low capacitance can be employed for the capacitor 7 for which reason comparison accuracy can be considerably improved. 
     In this first preferred embodiment of the present invention as thus described, the analog switch 12 is an MOS and is made up of a transistor 12 1  and transistor 12 2 , each of which has an N channel and P channel, and an identical gate surface area A, whereas the analog switch 13 is an MOS semiconductor and is made up of a transistor 13 1  and transistor 13 2 , each of which has an N channel and P channel, and an identical gate surface area 1/2A which is one half of the gate surface area of transistors 12 1  and transistor 12 2 . As long as a circuit for suppressing the spike noise generated by the opening and closing of the analog switch 12 is included, however, the configuration of the analog switch 12 and that of the analog switch 13 are interchangeable. It is possible to use the circuit which is disclosed by present inventor in Japanese Patent Application Laid-Open No. Heisei 2-67817 etc., for example, as the circuit described above. 
     In the following, a chopper type comparator of the second preferred embodiment of the present invention will be described with reference to FIG. 4. In FIG. 4, components which correspond to components in the chopper type comparator of the first preferred embodiment of the present invention shown in FIG. 3 will retain the original identifying numeral, and their description will be abbreviated. Comparing the device of this second preferred embodiment with the device of the first preferred embodiment, it can be seen that the analog switch 13 is replaced by an analog switch 14 and an inverter 15. 
     The analog switch 14 is a MOS semiconductor and is made up of a transistor 14 1  and transistor 14 2 . A gate a of the analog switch 14 is connected to the control voltage input terminal 4 and the gate b connects to the output terminal of the inverter 5. The input terminal of the analog switch 14 connects to the output terminal of the analog switch 12 at the terminal T 4 , and the output terminal of the analog switch 14 connects to the output terminal of the inverter 8 at the terminal T 3 . 
     At the terminal T 4  where the output terminal of the analog switch 12 connects to the input terminal of the analog switch 14, a CMOS fabricated inverter 15 is also connected. As FIG. 4 shows, the input and output terminals of the inverter 15 are connected together to form a short circuit across the device. The characteristics of this inverter 15 are identical to those of the inverter 8 which was described earlier. 
     As FIG. 4 shows, a first analog input voltage V 1  is supplied to the analog input voltage terminal 1 which connects directly with the analog switch 3, and a control voltage V c  is applied to the control voltage input terminal 4 which connects to the inverter 5. When the control voltage V c  which is low is applied to the control voltage input terminal 4, the gate a of the analog switch 3, the gate b of the analog switch 6, the gate a of the analog switch 12 and the gate a of the analog switch 14 are all in a low state. Since the output terminal of the inverter 5 is high under these circumstances, the gate b of the analog switch 3, the gate a of the analog switch 6, the gate b of the analog switch 12 and the gate b of the analog switch 14 are all in a high state. Accordingly, the analog switch 3, 12 and 14 are all in a conductive state, and the analog switch 6 is in a nonconductive state. 
     As a result, when a first and second analog input voltage V 1  and V 2  are simultaneously supplied to the analog input voltage terminal 1 and the analog input voltage terminal 2, respectively, and a control voltage V c  which is low is applied to the control voltage input terminal 4, since the analog switch 3 is in a conductive state, the analog input voltage V 1  is output from the analog switch 3 and applied to the capacitor 7 at the terminal T 1 . A short circuit is effectively formed across the input terminal of the inverter 8 which connects to the opposite terminal of the capacitor 7 at the terminal T 2  and the output terminal of the inverter 8 at the terminal T 3  since the analog switch 12 and the analog switch 14 are both open in this state. 
     Accordingly, the voltage between terminals T 2  and T 3  is one half of a supplied power source voltage V DD , in other words, the voltage between terminals T 2  and T 3  is equal to (1/2)·V DD . With the circuit as thus described, the potential difference across the capacitor 7 is equal to (V 1  -(1/2)·V DD ). In response to this potential difference across the capacitor 7, that is, in response to this potential difference across terminals T 1  and T 2 , a corresponding electrical charge is accumulated in the capacitor 7. 
     When the control input voltage V c  applied at the control input voltage terminal 4 is then caused to jump to high, the gate a of the analog switch 3 and those of the analog switch 12 and the analog switch 14 and the gate b of the analog switch 6 are all in a high state. Because the output of the inverter 5 is low, the gate b of the analog switch 3 and those of the analog switch 12 and the analog switch 14 and the gate a of the analog switch 6 are all in a low state. Accordingly, the analog switch 6 is conductive and the analog switches 3, 12 and 14 are nonconductive. 
     Since the analog switch 6 is in a conductive state, analog input voltage V 2  is output from the analog switch 6 and applied to the capacitor 7 at the terminal T 1 . At this time, the initial potential difference across the capacitor 7 is equal to (V 1  -(1/2)·V DD ), in response to which a corresponding electrical charge is accumulated in the capacitor 7. Accordingly, the lead of the capacitor 7 at the terminal T 2  has a potential which varies from (1/2)·V DD  to (V 2  -V 1  +(1/2)·V DD ). 
     In consideration of these characteristics, it can be seen that when V 2  &gt;V 1 , the terminal T 3  at the output lead of the inverter 8 will be low, whereas when V 1  &gt;V 2 , the terminal T 3  will be high (as shown in FIG. 2). At the terminal T 4  where the analog switch 12 and the analog switch 14 are interconnected, because the inverter 15 which has its input and output leads shorted is also connected to the terminal T 4 , the potential at this point is 1/2V DD . As a result, variation of potential at output terminal T 3  of inverter 8 has no effect on the potential at the input terminal T 2  of inverter 8, whereby the generation of noise is prevented. In other words, in order to suppress the transmitting in which the effect of a voltage variation caused by voltage applied to the terminal T 3  in off-timing of the analog switch 12 is not transmitted to the side of the terminal T 2 , the input side of the inverter 15 from the output side thereof across the analog switch 12, that is, a potential at the terminal T 4  is required to hold the constant potential which is equal to (1/2)·V DD . Thus, the analog switch 12 is connected to the analog switch 14 in series, so that the analog switch 12 and the analog switch 14 are both in on-timing, thereby being in the short state, while in off-timing the potential of the terminal T 4  becomes (1/2)·V DD , the analog switch 14 is off and separates from the terminal T 3  and the terminal T 4 . 
     Through the above described operations, the analog input voltages V 1  and V 2  can be compared. As thus described, the analog switch 12 and the analog switch 14 are connected in series, and the serially connected the analog switches 12 and 14 are together connected in parallel with the inverter 8. Because the inverter 15 with its input and output leads shorted is connected to the terminal T 4  where the analog switches 12 and 14 are interconnected, the potential at this point is (1/2)·V DD , and generation of spike noise by the opening or closing operation of the analog switch 12 is prevented. Accordingly, rapid comparison operations are possible, and a capacitor having low capacitance can be used for the capacitor 7, thereby permitting further improvements in speed and accuracy. 
     Although only the two analog switches, the analog switches 12 and 14 were connected in series, and together connected in parallel with the inverter 8, more than two analog switches can be serially connected, together in a parallel arrangement with the inverter 8. Further, although the inverter 15 was connected to the interconnection of the analog switches 12 and 14 at the terminal T 4  so as to achieve a potential at this point of (1/2)·V DD , other types of circuits and components can be used in place of the inverter 15 if they cause the potential at the terminal T 4  to equal that at the input terminal of the inverter 8 at the terminal T 2 .