Abstract:
A CMOS buffer circuit for preventing a short circuit current of an output buffer transistor that drives a load including a pre-driving stage, formed of even-numbered inverters connected in series, and the respective inverters are preferably designed to exponentially increase the driving capability; an output buffer driving stage, including a pull-up PMOS driving stage, which outputs a first signal, in response to an output signal of the pre-driving stage and an output signal of the pull-down NMOS driving stage and a pull-down NMOS driving stage, which outputs a second signal, in response to an output signal of the pre-driving stage and an output signal of the pull-up PMOS driving stage; and an output stage, an inverter formed of the pull-up PMOS transistor driven by the first signal and a pull-down NMOS transistor driven by the second signal, which drives a load connected to an output of the inverter.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to a complementary metal oxide silicon (CMOS) buffer circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    CMOS buffer circuits are mainly used for driving devices connected to an output stage thereof, particularly, devices having capacitance. If a signal bus in a memory has to drive a large load, or a clock signal has to drive a large load within a chip in a circuit only formed of logic devices, buffer circuits are needed for the bus signal and the clock signal.  
           [0005]    In the case of CMOS very large scale integration (CMOS VLSI), as the integration density increases, capacitance load on the clock signal becomes larger, and particularly in the case of a data output buffer, a load capacitor located outside the chip must be driven. However, the power consumption of the buffer circuit for the bus signal or the clock signal to drive a large load capacitance takes a very large part of entire power consumption of the chip.  
           [0006]    Generally, the power consumption of the CMOS circuit can be divided into dynamic power consumption and short circuit power consumption. The dynamic power consumption is inevitable due to the electric characteristics of the CMOS buffer circuit, but the short circuit power consumption results in unnecessarily wasted power. Accordingly, it is preferable to eliminate the short circuit power consumption.  
           [0007]    [0007]FIG. 1 illustrates a circuit diagram showing a conventional CMOS buffer circuit, and FIG. 2 illustrates a waveform diagram of signals in the conventional buffer circuit illustrated in FIG. 1 when it is being driven.  
           [0008]    Referring to FIG. 1, the conventional CMOS buffer circuit includes a plurality of inverters connected in series, and each of the inverters sequentially increases the output driving ability, so that the inverters are designed to finally drive a large capacitance.  
           [0009]    However, in the conventional CMOS buffer circuit illustrated in FIG. 1, there is a regular time interval, in which a PMOS transistor (M 11 ) and an NMOS transistor (M 12 ) turn on at the same time due to a gradual voltage slope with respect to time of a signal N 1  for driving two transistors (M 11  and M 12 ). The voltage slope of the signal becomes more gradual as the driven load becomes larger, so that the interval in which the two transistors turn on at the same time becomes longer. During this interval, a short circuit current flows through both the PMOS transistor (M 11 ) and the NMOS transistor (M 12 ). The size of two transistors (M 11  and M 12 ) is generally very large. Thus, the short circuit current corresponding to the two transistors is considerably large.  
           [0010]    Referring to FIG. 2, a time interval t 1  and a time interval t 2  are intervals in which the two transistors (M 11  and M 12 ) are on at the same time, and show that a considerable current flows depending on the size of the two transistors (M 11  and M 12 ). In the time interval t 1 , in which a signal N 1  is in transition from a high “H” state to a low “L” state, a regular current unnecessarily flows in the NMOS transistor (M 12 ). In the same way, in the time interval t 2 , in which the signal N 1  is in transition from the “L” state to the “H” state, an unnecessary current flows in the PMOS transistor (M 11 ).  
         SUMMARY OF THE INVENTION  
         [0011]    To solve the above problems, it is a feature of an embodiment of the present invention to provide a CMOS buffer circuit for preventing unnecessary short circuit current.  
           [0012]    Accordingly, to provide the above feature, there is provided a CMOS buffer circuit including a pre-driving stage, an output buffer driving stage, and an output stage.  
           [0013]    The pre-driving stage is formed of an even number of inverters, and each of the inverters is preferably designed to make the output driving capability of input signals increase exponentially.  
           [0014]    The output buffer driving stage includes a pull-up PMOS driving stage and a pull-down NMOS driving stage. The pull-up PMOS driving stage drives a pull-up PMOS transistor of the output stage, and the pull-down NMOS driving stage drives a pull-down NMOS transistor of the output stage. Since the output signals of the pull-up PMOS driving stage and pull-down NMOS driving stage have the same frequency, and the duty cycle of the pulses are differently devised, an interval in which the pull-up PMOS transistor and pull-down NMOS transistor of the output stage turn on at the same time is prevented.  
           [0015]    The output stage is an inverter formed of the pull-up PMOS transistor and pull-down NMOS transistor, and drives a load connected to the output of the inverter.  
           [0016]    These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    The above features and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:  
         [0018]    [0018]FIG. 1 illustrates a circuit diagram showing an example of a conventional CMOS buffer circuit according to the prior art;  
         [0019]    [0019]FIG. 2 illustrates a waveform diagram of signals of the conventional CMOS buffer circuit illustrated in FIG. 1 according to the prior art;  
         [0020]    [0020]FIG. 3 illustrates a circuit diagram of a CMOS buffer circuit according to a preferred embodiment of the present invention; and  
         [0021]    [0021]FIG. 4 illustrates a waveform diagram for explaining the operation of the circuit illustrated in FIG. 3 according to a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    Korean Patent Application No. 00-55482, filed Sep. 21, 2000, and entitled, “CMOS Buffer Circuit,” is incorporated herein by reference in its entirety.  
         [0023]    A preferred embodiment of the present invention will be described in greater detail with reference to the appended drawings, wherein like reference numerals in different drawings indicate like members.  
         [0024]    Referring to FIG. 3, the CMOS buffer circuit according to a preferred embodiment of the present invention includes a pre-driving stage  310 , an output buffer driving stage  350 , and an output stage  340 .  
         [0025]    The pre-driving stage  310  is comprised of two inverters IN 1  and IN 2  in series. Preferably, the driving capability of the inverter IN 2  connected to the output of the inverter IN 1  is designed to increase exponentially with respect to the inverter IN 1 , which receives an external signal IN.  
         [0026]    The output buffer driving stage  350  includes a pull-up PMOS driving stage  320  for controlling the gate voltage of a pull-up PMOS transistor (M 31 ) of the output stage  340 , and a pull-down NMOS driving stage  330  for controlling the gate voltage of a pull-down NMOS transistor (M 32 ) of the output stage  340 .  
         [0027]    The pull-up PMOS driving stage  320  includes three MOS transistors (M 33 , M 34 , and M 35 ), and an inverter IN 3 . One end of a MOS transistor (M 33 ), which is a PMOS transistor, is connected to a high source voltage (V DD ), the other end is connected to an output  200 , and an output signal of the pre-driving stage  310  is applied to the gate of MOS transistor (M 33 ). One end of a MOS transistor (M 34 ), which is an NMOS transistor, is connected to the output terminal  200 , the other end is connected to the NMOS transistor (M 35 ), and an output signal of the inverter IN 3 , that is a third signal  500 , is applied to the gate of MOS transistor (M 34 ). One end of the MOS transistor (M 35 ), which is an NMOS transistor, is connected to the NMOS transistor (M 34 ), the other end is connected to a low source voltage (V SS ), and an output signal of the pre-driving stage  310  is applied to the gate of MOS transistor (M 35 ). The inverter IN 3  receives an output signal of the pull-down NMOS driving stage  330 , that is a second signal  300 , and produces an output signal, that is the third signal  500 .  
         [0028]    The pull-down NMOS driving stage  330  includes three MOS transistors (M 36 , M 37 , and M 38 ), and an inverter IN 4 . One end of MOS transistor (M 36 ), which is a PMOS transistor, is connected to the high source voltage (V DD ), the other end is connected to the PMOS transistor  37 , and an output signal of the pre-driving stage  310  is applied to the gate; one end of MOS transistor (M 37 ), which is a PMOS transistor, is connected to the output  300  of the pull-down NMOS driving stage  330 , the other end is connected to the PMOS transistor (M 36 ), and an output signal of the inverter IN 4 , that is a fourth signal  400 , is applied to the gate; and one end of MOS transistor (M 38 ), which is NMOS transistor, is connected to the output  300  of the pull-down NMOS driving stage  330 , the other end is connected to the source voltage (V SS ), and an output signal of the pre-driving stage  310  is applied to the gate. The inverter IN 4  produces an output signal, that is the fourth signal  400  by receiving an output signal of the pull-up PMOS driving stage  320 , that is a first signal  200 .  
         [0029]    The output stage  340  is formed of a PMOS transistor (M 31 ) and an NMOS transistor (M 32 ). One end of the PMOS transistor (M 31 ) is connected to the high source voltage (V DD ), the other end is connected to an output terminal  100 , and an output signal of the pull-up PMOS driving stage  320 , that is the first signal  200 , is applied to the gate. One end of the NMOS transistor (M 32 ) is connected to the low source voltage (V SS ), the other end is connected to the output terminal  100 , and an output signal of the pull-down NMOS driving stage  330 , that is the second signal  300 , is applied to the gate.  
         [0030]    Hereinafter, according to a preferred embodiment of the present invention, the operation of the CMOS buffer circuit will be described in greater detail with reference to FIG. 3.  
         [0031]    If an input signal (IN) is in an “L” state, a specified time passes, and the output terminal  100  maintains the “L” state. In this state, if the input signal (IN) is transited to the “H” state, the transistors (M 35  and M 38 ) turn on, and the second signal  300  is transited to the “L” state. Therefore, the NMOS transistor (M 32 ) of the output stage  340  turns off, but the voltage of the output terminal  100  maintains the previous state due to the electrical characteristics of the load capacitance. However, the first signal  200  is transited to the “L” state after the inverting delay time of the fed-back second output signal  300  and the turn-on delay time of the NMOS transistor (M 34 ). Here, finally the PMOS transistor (M 31 ) of the output stage  340  turns on, so that the voltage of the output terminal  100  becomes “H.” In other words, after the second signal  300  is transited to the “L” state, and a specified time passes, the first signal  200  is transited to the “L” state. Therefore, if the input signal (IN) is transited from the “L” state to the “H” state, the two transistors (M 31  and M 32 ) of the output stage do not turn on at the same time.  
         [0032]    The case where the input signal (IN) is transited from the “H” state to the “L” state will now be examined. If the input signal (IN) is in “H” state, a specified time passes, and the output terminal  100  becomes the “H” state. Here, if the input signal (IN) is transited to the “L” state, the PMOS transistors (M 33  and M 36 ) turn on, so that first signal  200  is transited to the “H” state. Accordingly, the PMOS transistor (M 31 ) of the output stage  340  turns off, but the voltage of the output terminal  100  maintains the previous state, the “H” state, due to the electrical characteristics of the load capacitance. However, the second signal  300  is transited to the “H” state after the inverting delay time of the fed-back first signal  200  and the turn-on delay time of the NMOS transistor (M 37 ). Here, finally the NMOS transistor M 32  of the output stage  340  turns on, so that the voltage of the output terminal  100  becomes the “L” state. In other words, after the first signal  200  is transited to the “H” state, and a specified time passes, the second signal  300  becomes the “H” state. Therefore, if the input signal (IN) is transited from the “H” state to the “L” state, the two transistors (M 31  and M 32 ) of the output stage  340  do not turn on at the same time, so that a short circuit current is not generated.  
         [0033]    [0033]FIG. 4 shows a signal transition timing diagram in which transitions are indicated with arrows.  
         [0034]    First, if the input signal (IN) is transited from the “L” state to the “H” state, the second signal  300  is transited to the “L” state, and sequentially the output node  500  of the inverter IN 3  is transited to the “H” state, the first signal  200  is transited to the “L” state, the output node  400  of the inverter IN 4  is transited to the “H” state, and finally due to the “L” state of the first signal  200 , the output terminal  100  is transited to the “H” state. Here, because the output signal  400  of the inverter IN 4  does not have a direct influence on the voltage of the output node  100 , it is not shown by the arrows illustrating the signal flow. Therefore, the gate signal of the pull-up PMOS transistor (M 31 ), the first signal  200 , is not transited to the “L” state until the gate signal of the pull-down NMOS transistor (M 32 ), the second signal  300 , is transited to the “L” state, so that the two transistors (M 31  and M 32 ) do not turn on at the same time.  
         [0035]    Second, if the input signal (IN) is transited from the “H” state to the “L” state, the first signal  200  is first transited to the “H” state, and sequentially the output node  400  of the inverter IN 4  to the “L” state, the second signal  300  is transited to the “H” state, the output node  500  of the inverter IN 3  is transited to the “L” state, and finally due to the “H” state of the second signal  300 , the output terminal  100  is transited to the “L” state. Here, because the output signal  500  of the inverter IN 3  does not have a direct influence on the voltage of the output node  100 , it is not shown by the arrows illustrating the signal flow. Therefore, the gate signal of the pull-down NMOS transistor (M 32 ), the third output signal  300  is not transited to the “H” state until the gate signal of the pull-up PMOS transistor (M 31 ), the second output voltage  200  is transited to the “H” state, so that the two transistors (M 31  and M 32 ) do not turn on at the same time, and there is no consumption of the short circuit current thereby.  
         [0036]    As described, the CMOS buffer circuit according to the present invention has an advantage in that the power consumption of the short circuit can be prevented.  
         [0037]    The present invention has been described with reference to a preferred embodiment illustrated in the drawings; however, this is only one example, and various changes and other embodiments of the present invention may be made by one of ordinary skill in the art without departing from the spirit and scope of the invention as defined by the appended claims.