Abstract:
A cache memory circuit is disclosed that includes a store hit buffer that buffers write operations to the cache memory circuit and that removes write operations from the critical speed path for the cache memory array. The store hit buffer includes circuitry for determining whether a read operation to the cache memory circuit is targeted for the write operation stored in the store hit buffer and circuitry for merging the write operation from the store hit buffer with the read operation.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention pertains to the field of integrated circuit devices. More particularly, this invention relates to cache memory circuits. 
     2. Background 
     A cache memory is a random access memory that buffers data from a main memory. A cache memory is typically employed to provide high bandwidth memory accessing to a processor. Typically, such a cache memory reflects selected locations of the main memory. A typical prior cache memory contains a memory array that is usually organized into a set of cache blocks. The cache blocks are typically referred to as cache lines. A cache memory is usually smaller than the corresponding main memory. As a consequence, each cache line stored in the cache memory includes a corresponding address tag that identifies the main memory location for that cache line. 
     Prior cache memories typically implement a pipelined write architecture. In such a cache memory, a write operation requires two clock cycles. During a first cycle of the write operation, the processor transfers an address and a data value for the write operation to the cache memory. The cache memory typically latches the address and the data value into a set of pipeline registers. During a second cycle of the write operation, the cache memory transfers the data value and associated address tags into the memory array. 
     A prior pipelined write architecture for a cache memory typically provides high input bandwidth during write operations. Such an architecture enables the processor to supply a new write data value to the cache memory during each clock cycle while the cache memory transfers the previous write data value into the memory array. 
     Unfortunately, a pipelined write architecture typically causes a wait state in the cache memory for a read operation that immediately follows a write operation. Such a wait state usually occurs while the cache memory transfers the write data value of the preceding write operation into the memory array. A wait cycle is typically required because the read operation may be targeted for the same cache line as the preceding write operation that is buffered in the write pipeline registers. The cache memory must transfer the buffered write operation to the memory array before the subsequent read operation can be processed. Unfortunately, such wait cycles decrease the overall throughput to such a prior cache memory. 
     Other prior cache memories implement single cycle non-pipelined write operations. In this type of cache memory, the processor supplies the write data value to the cache memory early in the write cycle in order to enable the cache memory to transfer the write data value to the memory array during the same cycle. Unfortunately, single cycle cache memories stress the write timing of the processor. As a consequence, such prior single cycle cache memories are typically limited to lower input bandwidths than cache memories having a pipelined write architecture. 
     SUMMARY AND OBJECTS OF THE INVENTION 
     One object of the present invention is to enable high bandwidth read and write accesses to a cache memory. 
     Another object of the present invention is enable one cycle read and one cycle write operations from a processor to a cache memory. 
     Another object of the present invention is to provide a cache memory that does not impose a cache access wait state if a read operation immediately follows a write operation wherein the read and write operations target the same cache line. 
     A further object of the present invention is to relax the timing constraints for cache memory design by removing cache memory writes from the critical speed path to the cache memory array. 
     Another object of the present invention is to buffer a write operation to a cache memory and to perform the buffered write operation during a later cycle to the cache memory array with relaxed timing constraints. 
     Another object of the present invention is to access the buffered write operation and to merge the buffered data with cache array data for a read operation targeted for the same cache line as the buffered write operation. 
     Another object of the present invention is to merge the buffered data with cache array data for a read operation without causing delays in the critical speed path for the read operation. 
     These and other objects of the invention are provided by a cache memory circuit comprising a memory array for buffering a set of cache lines and a set of corresponding address tags. The cache memory circuit includes a store hit buffer coupled to receive and store a write operation to the cache memory circuit. The store hit buffer comprises circuitry for determining whether a read operation to the cache memory circuit is targeted for the write operation stored in the store hit buffer. The cache memory circuit further comprises circuitry for merging the write operation from the store hit buffer with the read operation. 
     Other objects, features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which: 
     FIG. 1 illustrates an integrated circuit die that contains a processor that communicates with a cache memory over an address bus and a data bus during read and write operations. 
     FIG. 2 illustrates the cache memory of the present invention in one embodiment which comprises a memory array, a set of sense amplifier circuits, a set of read/write circuits, and an addressing circuit. 
     FIG. 3 illustrates a read/write circuit for one embodiment which comprise a store hit buffer that includes a write buffer circuit, a control buffer circuit and a comparator. 
     FIG. 4 illustrates the timing of a read operation to a cache memory for one embodiment, showing the timing of the cache line data generated by a sense amplifier circuit, the timing of 2:1 mux data lines, the timing of match signals, and the timing of a selected data bit. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 illustrates an integrated circuit die  220  that contains a processor  222  and the cache memory  10 . The processor  222  communicates with the cache memory over an address bus  18  and a data bus  16  during read and write operations to the cache memory  10 . The read and write operations each comprise one clock cycle. 
     During write operations, the processor  222  transfers a write address to the cache memory  10  over the address bus  18 , and transfers the corresponding write data over the data bus  16  during the same clock cycle. The cache memory  10  buffers the write operation in a store hit buffer. During read operations, the processor  222  transfers a read address to the cache memory  10  over the address bus  18 , and receives the corresponding read data over the data bus  16  during the same clock cycle. The cache memory  10  contains circuitry for accessing the store hit buffer for the preceding write operation during address tag matching time of the read operation. 
     FIG. 2 illustrates the cache memory  10  of one embodiment of the present invention. The cache memory  10  comprises a memory array  12 , a set of sense amplifier circuits  20 - 22 , a set of read/write circuits  30 - 32 , and an addressing circuit  14 . The cache memory  10  is arranged as a four-way, set associative cache comprising a plurality of sets referred to as SET 0  through SETN. 
     The memory array  12  provides an array of memory cells that store cache line data and associated address tags. For one embodiment, the memory array  12  provides storage for 128K cache lines and corresponding address tags for the cache lines. 
     The sense amplifier circuits  20 - 22  each contain a set of sense amplifiers that sense cache line data and address tags from the memory array  12  over the bit lines of the memory array  12 . The sense amplifier circuit  20  senses cache line data from the memory array  12  over a set of data bit lines  40  and senses the corresponding address tags over a set of address tag bit lines  50 . Similarly, the sense amplifier circuits  21  and  22  sense cache line data from the memory array  12  over sets of cache data bit lines  41  and  42 , respectively. The sense amplifier circuits  21  and  22  sense address tags from the memory array  12  over sets of address tag bit lines  51  and sets of address tag bit lines  52 , respectively. 
     The sense amplifier circuits  20 - 22  differentially sense and amplify the corresponding cache data bit lines and address tag bit lines and provide the sensed cache line data and address tags to the read/write circuits  30 - 32 . The sets of bit lines  40 - 42  each comprise bit lines of the memory array  12  that provide the four way storage of a single cache line data bit in the memory array  12 . The bit lines  50 - 52  each comprise sets of bit lines of the memory array  12  that provide four way address tags for the corresponding cache line data on the bit lines  40 - 42 . For one embodiment, each of the four way address tags comprises 20 bits. 
     The read/write circuits  30 - 32  each receive the four way cache line data bits and associated four way address tags from the sense amplifier circuits  20 - 22 . The read/write circuits  30 - 32  each select the appropriate cache line data according to a tag compare address  92  generated by the addressing circuit  14 . The read/write circuit  30  receives a set of four way cache data bits  60  and corresponding four way address tags on line  70  from the sense amplifier circuit  20 . The read/write circuit  30  generates a selected data bit on line  80  from the cache data bits  60  according to the tag compare address  92 . The read/write circuit  30  compares the four way address tags on lines  70  to the tag compare address  92  to select one of the cache data bits  60  as the selected data bit on line  80 . 
     The read/write circuit  31  receives a set of four way cache data bits  61  and corresponding four way address tags on lines  71  from the sense amplifier circuit  21 . The read/write circuit  31  compares the tag compare address  92  with the four way address tags on lines  71  to select one of the cache data bits  61  for the selected data bit on line  81 . Similarly, the read/write circuit  32  receives a set of four way data bits  62  and the corresponding four way address tags on lines  72  from the sense amplifier circuit  22  and generates a selected data bit on line  82  by comparing the tag compare address  92  with each of the four way address tags on lines  72 . 
     The addressing circuit  14  receives read and write access addresses for the cache memory  10  over an address bus  18 . The addressing circuit  14  generates the tag compare address  92  for each read access address received over the address bus  18  during a read operation to the cache memory  10 . The addressing circuit  14  also generates a set address  90  that specifies one of the sets SET 0  through SETN for the read operation to the cache memory  10 . 
     During a write operation to the cache memory  10  the addressing circuit  14  receives a write address over the address bus  18 . The addressing circuit  14  then generates the set address  90  that specifies one of the sets SET 0  through SETN as the target for the write operation. The addressing circuit  14  also generates a set of write control signals  94 . The write control signals  94  specify one of the four ways of the selected set SET 0  through SETN for the write operation. The write control signals  94  also include the byte enable signals for the cache line data written to the cache memory  10  over the data bus  16 . 
     FIG. 3 illustrates the read/write circuit  30  for one embodiment. The read/write circuits  31  and  32  are each substantially similar to the read/write circuit  30 . The read/write circuit  30  comprises a store hit buffer  200  that includes a write buffer circuit  120 , a control buffer circuit  122  and a comparator  124 . The read/write circuit  30  further comprises a set of 2 to 1 (2:1) multiplexers  110 - 113 , a four way multiplexer  115  and a set of comparators  130 - 133 . 
     The store hit buffer  200  buffers each write operation received from the processor  222  over the data bus  16  and address bus  18 . If a read operation issued by the processor  222  is targeted for data stored in the store hit buffer  200 , then the data from the store hit buffer  200  is substituted for data from the memory array  12 . The access time to the store hit buffer  200  is masked by the normal address tag matching interval of the cache line read access. The buffered write operation in the store hit buffer  200  is written to the memory array  12  during a write cycle. 
     The write buffer circuit  120  buffers a write data bit  104  received over the data bus  16  during a write operation. For one embodiment, the write buffer circuit  120  is implemented by a set of latches. For another embodiment, the write buffer circuit  120  implements a set of master/slave flip flops. 
     The control buffer circuit  122  buffers a write way signal  106 , a set of byte enable signals  108 , and the set address  90  for each write operation to the cache memory  10 . The write way signal  106  specifies one of the four ways of the cache memory  10  for each write operation. The byte enable signals  108  correspond to the cache line data written to the cache memory  10  over the data bus  16  during each write operation. For one embodiment, the control buffer circuit  122  comprises a set of master/slave flip flops. 
     The 2:1 multiplexers  110 - 113  are each controlled by a set of buffered byte enable signals  160  from the control buffer circuit  122  and a set compare result  164  from the comparator  124 . The set compare result  164  indicates whether a read operation to the cache memory  10  is targeted for the cache line data buffered in the write buffer circuit  120 . The comparator  124  generates the set compare result  164  by comparing a buffered set address  162  (the address of the last write operation) from the control buffer circuit  122  with the set address  90 . 
     The 2:1 multiplexers  110 - 113  select either the buffered data bit  166  from the write buffer circuit  120  or one of the corresponding four way cache line data bits  60  received from the sense amplifier circuit  20 . The four way cache line data bits  60  comprise a set of cache line data bits  100 - 103 . The multiplexer  110  selects either the cache line data bit  100  or the buffered data bit  166 . The multiplexer  111  selects either the cache line data bit  101  or the buffered data bit  166 . The multiplexer  112  selects either the cache line data bit  102  or the buffered data bit  166 , and the multiplexer  113  selects either the cache line data bit  103  or the buffered data bit  166 . 
     If the set address  90  for a read operation to the cache memory  10  matches the buffered set address  162  for the cache line bit stored in the write buffer circuit  120 , then the set compare result  164  causes one of the 2:1 multiplexers  110 - 113  to select the buffered data bit  166 . The selected data bit is transferred to the four way multiplexer  115  over a set of 2:1 mux data lines  170 - 173 . 
     If the set address  90  for a read operation to the cache memory  10  does not match the buffered set address  162  for the cache line bit stored in the write buffer circuit  120 , then the set compare result  164  causes the 2:1 multiplexers  110 - 113  to select the cache line data bits  100 - 103  for transfer to the four way multiplexer  115  over the 2:1 mux data lines  170 - 173 . 
     The comparators  130 - 133  each compare the tag compare address  92  to one of the four way address tags  70  received from the sense amplifier circuit  20 . The four way address tags  70  comprise a set of address tags  140 - 143 . 
     The comparator  130  generates a match signal  150  by comparing the address tag  140  to the tag compare address  92 . The comparator  131  generates a match signal  151  by comparing the address tag  141  with the tag compare address  92 . Similarly, the comparator  132  generates a match signal  152  by comparing the address tag  142  with the tag compare address  92  and the comparator  133  generates a match signal  153  by comparing the address tag  143  with the tag compare address  92 . 
     The match signals  150 - 153  control the four way multiplexer  115 . The four way multiplexer  115  generates a selected data bit  80  for transfer over the data bus  16  during a read operation from the cache memory  10  by the processor  222 . The four way multiplexer  115  selects a cache line data bit for a read operation from among the 2:1 mux data lines  170 - 173  according to the match signals  150 - 153 . 
     FIG. 4 illustrates the timing of a read operation to the cache memory  10  for one embodiment. The diagram shows the timing of the cache line data on lines  60 - 62  generated by the sense amplifier circuits  20 - 22  (CACHE LINE DATA), the timing of the 2:1 mux data lines  170 - 173  (2:1 MUX DATA), the timing of the match signals  150 - 153  (MATCH SIGNALS), and the timing of the selected data bit  80  (SELECTED DATA). 
     Prior to time  201 , the comparator  124  compares the buffered set address  162  with the set address  90  for the read transaction and generates the set compare result  164 . Starting at time  201 , the cache line data  60 - 62  from the sense amplifier circuits  20 - 22  indicates the state of the addressed cache line for the read operation in the memory array  12 . The interval between times  201  and  202  corresponds to a propagation delay for the multiplexers  110 - 113 . 
     Thereafter at time  203 , the comparators  130 - 133  generate the match signals  150 - 153  according to the tag compare address  92  for the read operation. At time  204 , the selected data bit  80  is valid. The interval between times  203  and  4  corresponds to a propagation delay from the control input to the output of the multiplexer  115 . The comparison time for the comparators  130 - 133  to generate the match signals  150 - 153  masks the propagation delay for the multiplexers  110 - 113 . 
     In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are accordingly to be regarded as illustrative rather than a restrictive sense.