Abstract:
Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be operable during a first operational mode and inoperable during a second operational mode. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates generally to testing and more specifically to testing a dual mode interface, such as a bilingual 1394 firewire port.  
         [0002]     Firewire, also known as IEEE 1394, is a personal computer and digital audio/video serial bus interface standard for high speed communications. Firewire currently supports data transfer rates up to 400 Mbps (in 1394a) and 800 Mbps (in 1394b), and the maximum data transfer rate possible with firewire 1394b is 1600 Mbps and likely to increase to 3200 Mbps. A single firewire port can typically be used to connect up to 63 external devices. In addition to its high speed, firewire also supports isochronous data—delivering data at a guaranteed rate. This makes firewire ideal for devices that need to transfer high levels of data in real-time, such as video devices.  
         [0003]     A dual mode, or bilingual, 1394 firewire port (also referred to below as a bilingual firewire port) can operate in two different modes corresponding to the two different data rates described above. Specifically, a bilingual firewire port can operate at both speeds—1394a and 1394b—depending on the application. When the bilingual firewire port operates at the slower data transfer rates of 100, 200, or 400 Mbps, the bilingual firewire port operates in a “legacy mode”. When the bilingual firewire port operates at the higher data transfer rate of 800 Mbps, the bilingual firewire port operates in a “beta mode”. There is typically a method to set the bilingual firewire port to a particular mode, such as by causing a particular pin of the firewire port to have a voltage greater than a predetermined value for one mode and less than the predetermined value for the other mode. The voltage is set by control logic or an external signal.  
         [0004]     One problem is that it is difficult to test the firewire port at its normal beta mode operating speed(s). Automated test equipment used in a non-invasive fashion (i.e., testing the firewire port using an external device not inserted onto the firewire port circuit itself) cannot normally communicate at the fast data rates of a beta mode firewire port. Further, the interface between the test equipment and the firewire port can introduce parasitic loading on the high-speed firewire port, thereby degrading performance. Therefore, firewire ports are traditionally tested using automated test equipment that communicates at a lower data rate relative to the firewire&#39;s beta mode operating data rates to determine that the firewire port is functional. This testing, however, does not test the firewire port for proper operation at the maximum data rates.  
         [0005]     Another method of testing a bilingual firewire port is in an invasive fashion in which test circuitry is inserted onto the circuit board of the firewire port itself during manufacturing testing of the firewire port. For example, test circuitry may be inserted on input/output data lines of the firewire port to analyze the data being transmitted/received by the firewire port. This technique, however, is undesirable because it adds parasitic loading on the firewire port and can alter the operation of the components.  
         [0006]     Therefore, there remains a need to enable testing of a bilingual firewire port at the maximum speed which the bilingual firewire port operates and in a non-invasive fashion.  
       BRIEF SUMMARY OF THE INVENTION  
       [0007]     The present invention provides for non-invasive testing of a dual mode interface at the interface&#39;s maximum data rate. The testing of the interface at its maximum data rate is typically enough to warrant that the dual mode interface can also operate at its lower data rate(s).  
         [0008]     In accordance with the principles of the present invention, a dual mode interface includes a first strobe circuit and a second strobe circuit configured to be operable during a first operational mode and inoperable during a second operational mode. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate the signal line in response to receipt of a test signal.  
         [0009]     In one embodiment, the second strobe circuit of the dual mode interface includes an AND gate whose output activates the signal line. The AND gate has a first input that is activated when the dual mode interface operates in the first operational mode and a second input as the switch element.  
         [0010]     In one embodiment, the second data circuit includes an input for receiving input data transmitted at a rate corresponding to a rate associated with the first operational mode of the dual mode interface. The first data circuit can include an output for transmitting output data in response to the second data circuit receiving the input data. The dual mode interface also includes data lines enabling communications between the first strobe circuit and the first data circuit and data lines enabling communications between the second data circuit and the second strobe circuit.  
         [0011]     In one embodiment, the dual mode interface is a bilingual firewire port where the first operational mode is a beta mode and the second operational mode is a legacy mode.  
         [0012]     In operation, the dual mode interface receives a test signal and input data at an input of the second data circuit, and transmits the input data from the second data circuit to the second strobe circuit. The input data is transmitted over the signal line to the first strobe circuit in response to the test signal. Output data is then transmitted over the signal line to an output of the first data circuit.  
         [0013]     The input data is also transmitted from the first strobe circuit to the first data circuit. In one embodiment, the dual mode interface receives a first operational mode signal so that the dual mode interface operates in its first operational mode (e.g., its beta mode).  
         [0014]     In one embodiment, the output data is compared with the input data. If the output data is equal to the input data, then the dual mode interface is operating correctly. If the dual mode interface is operating incorrectly, the output data is unequal to the input data.  
         [0015]     These and other advantages of the invention will be apparent to those of ordinary skill in the art by reference to the following detailed description and the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]      FIG. 1  is a block diagram of a bilingual 1394 firewire port;  
         [0017]      FIG. 2  is a more detailed block diagram of a bilingual 1394 firewire port;  
         [0018]      FIG. 3  shows a block diagram of a dual mode interface in accordance with an embodiment of the invention;  
         [0019]      FIG. 4  shows a flowchart of the steps performed by a dual mode interface when receiving a test signal in accordance with an embodiment of the invention; and  
         [0020]      FIG. 5  is a more detailed block diagram of a dual mode interface in accordance with an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0021]      FIG. 1  shows a block diagram of an embodiment of a bilingual  1394  firewire port  100 . As described above, the firewire port  100  can operate in a legacy mode or a beta mode.  
         [0022]     The bilingual firewire port  100  typically includes a first strobe circuit  104  in communication with a first data circuit  108 . The first strobe circuit  104  includes two inputs  110   a ,  110   b  and two outputs  112   a ,  112   b . The first data circuit  108  includes two inputs  114   a ,  114   b  and two outputs  118   a ,  118   b.    
         [0023]     The bilingual firewire port  100  also includes a second data circuit  120  and a second strobe circuit  124 . The second data circuit  120  includes two inputs  128   a ,  128   b  and two outputs  132   a ,  132   b . The second strobe circuit  124  also includes two inputs  136   a ,  136   b  and two outputs  140   a ,  140   b.    
         [0024]     Data is communicated out of and into the firewire port  100  via data lines  144   a ,  144   b ,  148   a ,  148   b . In particular, the first strobe circuit&#39;s outputs  112   a ,  112   b  transmit a strobe (i.e., clock) over a first pair of data lines  144   a ,  144   b  to the first data circuit&#39;s inputs  114   a ,  114   b  while the second data circuit&#39;s outputs  132   a ,  132   b  transmit data over a second pair of data lines  148   a ,  148   b  to the second strobe circuit&#39;s inputs  136   a ,  136   b . Further, data can be input/output from/to an external device in communication with the firewire port  100 , such as a computer, via one or more of the data lines  144   a ,  144   b ,  148   a ,  148   b.    
         [0025]     When operating in the legacy mode, the bilingual firewire port  100  has both transmitters (i.e., the first strobe circuit  104  and the second data circuit  120 ) operating at the same time or both receivers (i.e., the first data circuit  108  and the second strobe circuit  124 ) operating at the same time. If both transmitters are operating at the same time, then the first transmitter (i.e., the first strobe circuit  104 ) traditionally transmits a strobe (i.e., clock) and the other transmitter (i.e., the second data circuit  120 ) traditionally transmits data. When the receivers (i.e., the first data circuit  108  and the second strobe circuit  124 ) are operating, one receiver (i.e., the first data circuit  108 ) receives the strobe (from the first strobe circuit  104 ) and the other receiver (i.e., the second strobe circuit  124 ) receives data from the second data circuit  120 . The transmission or generation of a clock signal in the legacy mode enables the firewire port  100  to operate in legacy mode without requiring use of a clock and data recovery (CDR) circuit.  
         [0026]     When operating in beta mode, however, a CDR circuit is employed to generate a clock from the data. As a result, only the first and second data circuits  108 ,  120  are operable to transmit or receive data. The inoperable strobe circuits  104 ,  124  are not being used during the beta mode and are therefore idle.  
         [0027]      FIG. 2  shows a more detailed block diagram of an embodiment of a bilingual firewire port  200 . The bilingual firewire port  200  includes a strobe output circuit  204  that provides a clock signal when the bilingual firewire port  200  operates in legacy mode. The strobe output circuit  204  is connected to TPA and TPAN twisted pair data lines  208   a ,  208   b . The strobe output circuit  204  includes a legacy strobe input pin  206  for receiving a clock signal. When the bilingual firewire port  200  operates in beta mode, the strobe output circuit  204  (and, for example, its input pins) are unused.  
         [0028]     A data input circuit  212  receives the data from data lines  208   a ,  208   b  and includes a legacy data output pin  216  and a beta data output pin  220 . When the bilingual firewire port  200  operates in legacy mode, the output data is transmitted over the legacy data output pin  216 . When the bilingual firewire port  200  operates in beta mode, the output data is transmitted over the beta data output pin  220 .  
         [0029]     The bilingual firewire port  200  also includes a data output circuit  224 . The data output circuit  224  has the same design and components as the strobe output circuit  204  (e.g., the same number of input and output pins). The data output circuit  224  has a legacy data input pin  228  and a beta data input pin  232 . These pins  228 ,  232  are the input pins for the different modes. The data output circuit  224  also includes a BMODE pin  236 . The BMODE pin  236  is set to high when the bilingual firewire port  200  operates in beta mode and is set to low when the bilingual firewire port  200  operates in legacy mode. The BMODE pin  236  is typically set by control logic or an external test signal. The output of the data output circuit  224  is transmitted over TPB and TPBN twisted pair data lines  240   a ,  240   b  (generally  240 ).  
         [0030]     The data transmitted by the data output circuit  224  is available to be received by a strobe input circuit  244 . The strobe input circuit  244  has the same receiver design and components as the data input circuit  212 . As a result, the strobe input circuit  244  has two output pins  248 ,  252 . The strobe input circuit  244  provides a clock signal when the bilingual firewire port  200  operates in legacy mode. The strobe input circuit  244  includes legacy strobe output pin  248  for transmitting the clock signal as output. The second output pin  252  of the strobe input circuit  244  is unused and unconnected because the strobe input circuit  244  is used to transmit the clock signal (which occurs on the legacy strobe output pin  248 ) during operation in legacy mode.  
         [0031]      FIG. 3  shows a block diagram of a dual mode interface  300  in accordance with an embodiment of the invention. Dual mode interface  300  includes first strobe circuit  304  in communication with a first data circuit  308  and a second data circuit  312  in communication with a second strobe circuit  316 . The first strobe circuit  304  has two outputs  320   a ,  320   b  and two inputs  324   a ,  324   b  and the second strobe circuit  316  has two outputs  328   a ,  328   b  and two inputs  332   a ,  332   b . Similarly, the first data circuit  308  has two inputs  336   a ,  336   b  and two outputs  340   a ,  340   b  and the second data circuit  312  has two inputs  344   a ,  344   b  and two outputs  348   a ,  348   b . The outputs  320   a ,  320   b  of the first strobe circuit  304  and the inputs  336   a ,  336   b  of the first data circuit  308  are connected to respective data lines  352   a ,  352   b . Similarly, the outputs  348   a ,  348   b  of the second data circuit  312  and the inputs  332   a ,  332   b  of the second strobe circuit  316  are connected to respective data lines  356   a ,  356   b.    
         [0032]     As described above, the first strobe circuit  304  is not used by (i.e., inoperable) the dual mode interface  300  when operating in beta mode because no strobe (i.e., clock) is needed from the first strobe circuit  304 . Thus, the inputs  324   a ,  324   b  of the first strobe circuit  304  are typically unused (i.e., inoperable) when the dual mode interface  300  operates in its first operational mode (e.g., its beta mode).  
         [0033]     As described above, the second strobe circuit  316  is not used by the dual mode interface  300  when operating in its first operational mode (e.g., beta mode) because no strobe (i.e., clock) is needed from the second strobe circuit  316 . Thus, the outputs  328   a ,  328   b  of the second strobe circuit  316  are typically unused when the dual mode interface  300  operates in beta mode.  
         [0034]     In accordance with an embodiment of the present invention, output  328   b  of the second strobe circuit  316  (typically unused when the dual mode interface  300  operates in its first operational mode) is connected to input  324   b  of the first strobe circuit  304  (also typically unused when the dual mode interface  300  operates in its first operational mode), thereby providing a loopback connection for the dual mode interface  300 . This connection is shown with dashed signal line  358 . This signal line (also referred to below as a loopback connection)  358  enables non-invasive testing of the dual mode interface  300  at its maximum operating speed (when operating in the first operational mode).  
         [0035]      FIG. 4  shows a flowchart of the steps performed by the dual mode interface  300  when receiving input test data in accordance with an embodiment of the invention. Input  344   b  of the second data circuit  312  receives input data  360  in step  404 . Input data  360  is data transmitted at a data rate associated with the first operational mode data rate. The data may be a single bit, multiple bits, or a data stream. In one embodiment, a CDR circuit receives a parallel input at a low data rate (relative to the maximum data rate of the dual mode interface operating in its first operational mode) and converts it to a serial data stream transmitted at the data rate associated with the first operational mode.  
         [0036]     The dual mode interface  300  then determines whether it is operating in its first operational mode (e.g., beta mode) in step  408 . If the dual mode interface  300  is not operating in beta mode, the test pauses until the dual mode interface  300  receives input to switch it to beta mode. In one embodiment, the dual mode interface  300  operates in beta mode when a particular pin is set high.  
         [0037]     Once in beta mode, the second data circuit  312  transmits the input data  360  over the data line  356   a  and to the second strobe circuit  316 . The second strobe circuit  316  then determines whether loopback is enabled in step  416 . The second strobe circuit  316  performs this analysis by determining whether a loopback enabling pin, or switch element,  364  is set high (i.e., the voltage associated with the pin  364  is above a predetermined value). If the pin  364  is not set high, then the second strobe circuit  316  waits until the pin  364  is set high.  
         [0038]     Once the loopback enabling pin  364  is set high, the second strobe circuit  316  transmits the input data  360  over the loopback connection  358  to the input  324   b  of the first strobe circuit  304  in step  420 . The first strobe circuit  304  receives the input data  360  and sends it out over the data lines  352   a ,  352   b  in step  424 . The first data circuit  308  receives the input data  360  from the data lines  352   a ,  352   b  and transmits output data  368  in step  428 . The output data  368  is then compared in step  432  with the input data  360  that was transmitted to the second data circuit  312 . In one embodiment, if the two signals are the same, then the dual mode interface  300  is operating correctly and has been tested at its maximum beta mode speed. If the signals do not match, then there may be a problem with the dual mode interface  300 .  
         [0039]      FIG. 5  is a more detailed block diagram of a dual mode interface  500 . The dual mode interface  500  includes a data input circuit  504 , a data output circuit  508 , a strobe input circuit  512 , and a strobe output circuit  516 . The dual mode interface  500  also includes a loopback connection  520  connecting an output  524  of the strobe input circuit  512  with an input  528  of the strobe output circuit  516 .  
         [0040]     In one embodiment, an AND gate  532  is added to the strobe input circuit  512 . The AND gate  532  includes a BMODE input  536  and a LPBKEN input  540 . The BMODE input  536  is set high to put the dual mode interface  500  in the first operational mode (e.g., beta mode). Thus, the loopback connection  520  is not active unless the dual mode interface  500  is operating in the first operational mode. The loopback connection  520  is also not activated until the dual mode interface  500  is put into a test mode. The dual mode interface  500  can only operate in the test mode when the dual mode interface  500  is put into the first operational mode. The test mode is triggered by setting the LPBKEN input pin  540  high using a test signal. Once this pin  540  is set high, the signal line  520  is enabled to transmit data between the strobe input circuit  512  and the strobe output circuit  516  when the dual mode interface  500  is operating in the first operational mode.  
         [0041]     In one embodiment, AND gate  544  is added to the data input circuit  504  so that the two input circuits  504 ,  512  are mirrored. This mirroring often facilitates consistent and faster manufacturing because the components and layouts are the same for the two input circuits  504 ,  512 . Further, with the same components and layout, both input circuits  504 ,  512  will typically provide consistent timing when receiving an input and transmitting an output while operating in legacy mode.  
         [0042]     The foregoing Detailed Description is to be understood as being in every respect illustrative and exemplary, but not restrictive, and the scope of the invention disclosed herein is not to be determined from the Detailed Description, but rather from the claims as interpreted according to the full breadth permitted by the patent laws. It is to be understood that the embodiments shown and described herein are only illustrative of the principles of the present invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention. Those skilled in the art could implement various other feature combinations without departing from the scope and spirit of the invention.