Abstract:
An apparatus and method for a voltage reference circuit with improved precision. The voltage reference circuit utilizes threshold voltage difference between a pair of MOSFETs. A voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage, includes a first current mirror with a first NMOS transistor and a second NMOS transistor wherein said first NMOS transistor threshold voltage is not equal to said second NMOS transistor threshold voltage, a second current mirror with a first PMOS transistor, a second and third PMOS transistor configured to be coupled to said power supply node, a current source configured to be provide current to said second current mirror, an amplifier configured with a first and second input configured to be connected to the drains of said first NMOS transistor and said second NMOS transistor and, a feedback loop configured to be the output of said amplifier.

Description:
BACKGROUND 
     1. Field 
     The disclosure relates generally to a voltage reference circuit and, more particularly, to a voltage reference circuit device for a high precision thereof. 
     2. Description of the Related Art 
     Voltage reference circuits are a type of circuit used in conjunction with semiconductor devices, integrated circuits (IC), and other applications. Voltage reference circuits can be classified into different categories. These can include (a) bandgap reference circuits, (b) circuits based on MOSFET transistor threshold voltage differences, (c) MOSFET threshold voltage and mobility compensated circuits, (d) current mode circuits, and (e) MOSFET beta multiplier networks. 
       FIG. 1  is an example of a prior art circuit  100  with ground (e.g. VSS)  101 , and negative power supply VCC  102 . The n-channel MOSFET devices T 1   110  and T 2   120  are used as reference MOS transistors. The transistor T 3   130  is a MOSFET device with an n-type doped MOSFET gate structure. N-channel MOSFET T 2   120  also has a long MOSFET channel. The MOSFET T 3   130  current is “mirrored” by the current mirror formed by the two MOSFET devices T 4   140  and T 5   150 . The current mirror formed by p-channel MOSFET devices T 4   140  and T 5   150  adjusts itself to the value corresponding to the cross-point of the characteristics of MOSFET device T 1   110  and MOSFET device T 3   130 . The MOSFET devices T 7   170 , T 8   180  and T 9   190  establishes a second current mirror network which forces equal currents through the MOSFET devices T 1   110  and T 2   120 . To initiate the start-up of the circuit, n-channel MOSFET device T 6   160  conducts current when the power supply is switched on, which is provided by a positive gate voltage from the capacitor C  103 . The leaky poly-silicon diode D  104  discharges through the capacitor C  103  and cuts off the n-channel MOSFET device T 6   160 . This circuit works properly when the power supply voltage exceeds V CC &gt;1.5V. The prior art needs six MOSFETs, T 1   110 , T 2   120 , T 5   150 , T 7   170 , T 8   180 , and T 9   190 . In order to get a high precision output voltage, the electrical properties of these devices must have precise matching. To achieve accurate matching characteristics, the transistors must be large to minimize semiconductor manufacturing variation (e.g. photolithography and etch variations, across chip linewidth variation (ACLV), and material changes). Additionally, transistors T 1   110  and T 2   120  have threshold voltage variations and mismatch which leads to a voltage reference difference due to the voltage difference of each drain voltage. The disadvantages of this implementation to achieve a voltage reference circuit with high precision is the number of transistors, the physical size of the transistors, chip area, and cost. 
     U.S. Pat. No. 7,564,225 to Moraveji et al describes a voltage reference circuit that utilizes a work function difference between p+ gate and n+ gate to generate a pre-determined reference voltage. Additionally, the pre-determined reference voltage can be pre-adjusted using gate materials with different work functions. 
     U.S. Pat. No. 7,727,833 to Dix describes a voltage reference from an operational amplifier having identical PMOS transistors with each having a different gate dopant. The difference between the two threshold voltages is then used to create the voltage reference equal to the difference. The two PMOS transistors are configured as a differential pair. 
     U.S. Pat. No. 8,264,214 to Ratnakumar et al shows a low-voltage reference circuit which has a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region. 
     In the previously published article, “MOS Voltage Reference Base on Polysilicon Gate Work Function Difference,” IEEE Journal of Solid-State Circuit, Volume SC-15, No. 3, June 1980, a voltage reference circuit is discussed that operates on MOSFET gate work-function differences. 
     In the previously published article “CMOS Voltage Reference Based on Gate Work Function Differences in Poly-Si Controlled by Conductivity Type and Impurity Concentration,” IEEE Journal of Solid-State Circuit, Volume 38, No. 6, June 2003, the voltage reference circuit operates on differences in the conductivity and impurity concentration. 
     In these prior art embodiments, the solution to improve the operability of a low voltage reference circuit utilized various alternative solutions. 
     It is desirable to provide a solution to address the disadvantages of operation of a voltage reference circuit. 
     SUMMARY 
     A principal object of the present disclosure is to provide a voltage reference circuit which allows for operation of a circuit that is less costly. 
     A principal object of the present disclosure is to provide a voltage reference circuit which allows operation of a circuit that is reduced in size. 
     A principal object of the present disclosure is to provide a voltage reference circuit which allows for improvement in accuracy. 
     A principal object of the present disclosure is to provide a voltage reference circuit which allows for less dependency on power supply voltage. 
     Another further object of the present disclosure is to provide a voltage reference circuit which allows for improvement in accuracy due to maintaining drain voltage matching. 
     Another further object of the present disclosure is to provide a voltage reference circuit which allows for improvement in accuracy due to maintaining drain voltage matching even though source voltage nodes and source voltage are not matched. 
     Another further object of the present disclosure is to provide a voltage reference circuit with fewer transistors. 
     Another further object of the present disclosure is to provide a voltage reference circuit with fewer transistors allowing for improved matching. 
     Another further object of the present disclosure is to provide a voltage reference circuit with fewer transistors that is smaller and still maintain accuracy. 
     In summary, a voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage, comprising of a voltage network comprises a first current mirror with a first NMOS transistor and a second NMOS transistor wherein said first NMOS transistor threshold voltage is not equal to said second NMOS transistor threshold voltage, a second current mirror with a first PMOS transistor, a second PMOS transistor and third PMOS transistor configured to be coupled to said power supply node, wherein the first PMOS transistor is coupled to the gate of the second PMOS transistor, and third PMOS transistor wherein said second PMOS transistor and third PMOS transistor drains are coupled to said first NMOS transistor drain and said second NMOS transistor drain, a current source configured to be provide current to said second current mirror, an amplifier configured with a first and second input configured to be connected to the drains of said first NMOS transistor and said second NMOS transistor; and, a feedback loop configured to be the output of said amplifier. 
     In addition, a method of a voltage reference circuit comprises the following steps, (a) providing a voltage reference circuit comprises a first MOSFET current mirror with a threshold voltage difference, a second MOSFET current mirror, an amplifier, a feedback loop, and an output signal, (b) establishing a drain voltage difference from said first MOSFET current mirror with a threshold voltage difference, (c) feeding the MOSFET drain voltages of said first MOSFET current mirror with a threshold voltage difference to the inputs of said amplifier, (d) establishing an amplifier output signal from said amplifier; and, lastly (e) feeding the amplifier output signal to a feedback loop. 
     Other advantages will be recognized by those of ordinary skill in the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure and the corresponding advantages and features provided thereby will be best understood and appreciated upon review of the following detailed description of the disclosure, taken in conjunction with the following drawings, where like numerals represent like elements, in which: 
         FIG. 1  is a prior art example of a voltage reference circuit; 
         FIG. 2  is a circuit schematic of a voltage reference circuit in accordance with an embodiment of the disclosure; 
         FIG. 3  is a circuit schematic of a voltage reference circuit in accordance with an embodiment of the disclosure; 
         FIG. 4  is a circuit schematic of a voltage reference circuit in accordance with an embodiment of the disclosure; 
         FIG. 5  is a circuit schematic of a voltage reference circuit in accordance with an embodiment of the disclosure; 
         FIG. 6  is a circuit schematic of a voltage reference circuit in accordance with an embodiment of the disclosure; 
         FIG. 7  is a circuit schematic of a voltage reference circuit in accordance with an embodiment of the disclosure; 
         FIG. 8  is a circuit schematic of a voltage reference circuit in accordance with an embodiment of the disclosure; and, 
         FIG. 9  is a method for providing a voltage reference circuit in accordance with an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  is a circuit schematic of a voltage reference circuit  200  in accordance with an embodiment of the disclosure. The threshold voltage of n-channel metal oxide semiconductor (MOS) N 1   210  is higher than that of n-channel MOS N 2   220  and the difference between these threshold voltages appears at output node O  237  if p-channel MOS P 2   245  and p-channel MOS P 3   250  have good matching in terms of their electrical characteristics. The currents flowing through p-channel MOS P 2   245  and p-channel MOS P 3   250  are not necessarily equal but the ratio of them should be constant. So the gate areas of p-channel MOS P 2   245  and p-channel MOS P 3   250  are needed to be big to reduce random variation which worsens the matching of currents of the p-channel MOS P 2   245  and p-channel MOS P 3   250 . The n-channel MOS N 1   210  and n-channel MOS N 2   220  also need to be big so that the difference of threshold voltages between two transistors n-channel MOS N 1   210  and n-channel MOS N 2   220  are stable. 
     Mentioned above, in this circuit, high precision matching is required only on two pairs, the p-channel MOS pair P 2 -P 3  (P 2   245  and P 3   250 ) and the n-channel MOS pair N 1 -N 2  (N 1   210  and N 2   220 ); this means only four big transistors are needed in the circuit. 
     The amplification gain, A 1   230  is the only required voltage gain and its large input offset is tolerated, so the size of this amplifier could be quite small and it has no area impact. No matching properties are required on the p-channel MOS P 1   240  and the n-channel MOS N 3   225  because they are a bias voltage source and auto-controlled resistor respectively. 
     The power supply, VDD  201 , by being independent of output voltage O (e.g. power supply voltage independence) is another merit of this invention. In the circuit, drain voltages of p-channel MOS P 2   245  and the p-channel MOS P 3   250  are always controlled to be equal in magnitude as a result of the negative feedback loop. This is inclusive of the voltage amplification gain A 1   230  and n-channel MOS N 3   225 , so the current ratio between the two p-channel MOS transistors, P 2   245  and P 3   250 , are independent of the power supply voltage VDD. As a result, output voltage is not sensitive to the power supply voltage VDD. 
       FIG. 3  is a circuit schematic of a voltage reference circuit  300  in accordance with a further embodiment of the disclosure. In some cases, the gain of loop on A 1   330 -N 3   325 -N 2   320  might be too large in magnitude in order to get enough phase margin. Then the loop gain could be decreased by putting a resistor between the source of the n-channel MOS N 3   325  and the ground  302 . The embodiment  300  comprises a VDD  301  and ground VSS  302 . A current mirror is formed with transistor N 1   310  and transistor N 2   320 . Differential inputs for amplifier A 1   330  are input  327  and input  329  connected to the drain of the N 1   310 , and N 2   320 . A second current mirror is formed with p-channel MOSFET P 1   340 , P 2   345 , and P 3   350 . The current source  303  establishes a current Is and is connected to the p-channel MOSFET current mirror. The amplifier A 1   330  provides a feedback signal  335  to n-channel MOSFET N 3   325 . The drain of N 3   325  is coupled to output O  337  and whose source is connected to resistor R  355 . 
       FIG. 4  is a circuit schematic of a voltage reference circuit  400  in accordance with another embodiment of the disclosure. This is another method to decrease the loop gain. The embodiment  400  comprises a VDD  401  and ground VSS  402 . A current mirror is formed with transistor N 1   410  and transistor N 2   420 . Differential inputs for amplifier A 1   430  are input  427  and input  429  connected to the drain of the N 1   410 , and N 2   420 . The drain of N 2   420  is coupled to the gate of n-channel MOSFET N 4   455 . A second current mirror is formed with p-channel MOSFET P 1   440 , P 2   445 , and P 3   450 . The current source  403  establishes a current Is and is connected to the p-channel MOSFET current mirror. The amplifier A 1   430  provides a feedback signal  435  to n-channel MOSFET N 3   425 . The drain of N 3   425  is coupled to output O  437 . In this circuit, the n-channel MOSFET device N 4   455  is added instead of the resistor R  355  of  FIG. 3 . The resistor R  355  of  FIG. 3  might need a large area due to the magnitude of the resistor value. In that case, using an n-channel metal oxide field effect transistor (NMOSFET) N 4   455  is less physical area compared to a resistor element. 
       FIG. 5  is a circuit schematic of a voltage reference circuit  500  in accordance with another embodiment of the disclosure. Another method to decrease the loop gain is achieved with this circuit embodiment. The embodiment  500  comprises a VDD  501  and ground VSS  502 . A current mirror is formed with transistor N 1   510  and transistor N 2   520 . Differential inputs for amplifier A 1   530  are input  527  and input  529  connected to the drain of the N 1   510 , and N 2   520 . A second current mirror is formed with p-channel MOSFET P 1   540 , P 2   545 , and P 3   550 . The current source  503  establishes a current Is and is connected to the p-channel MOSFET current mirror. The amplifier A 1   530  provides a feedback signal  535  to p-channel MOSFET P 4   525 . If the threshold voltage of the p-channel MOS P 4   525  is low, it doesn&#39;t affect the voltage of output O  537 , and as a result, this circuit will have good output accuracy and good stability (e.g. because of lowest loop gain). 
       FIG. 6  is a circuit schematic of a voltage reference circuit  600  in accordance with an embodiment of the disclosure. The embodiment  600  comprises a VDD  601  and ground VSS  602 . A current mirror is formed with transistor N 1   620  and transistor N 2   625 . Differential inputs for amplifier A 1   630  are input  627  and input  629  connected to the drain of the N 1   620 , and N 2   625 . A second n-channel current mirror is formed with transistor N 4   610  and transistor  615 . A third current mirror is formed with p-channel MOSFET P 1   640 , P 4   645 , P 2   647  and P 3   650 . The current source  603  establishes a current Is and is connected to the p-channel MOSFET current mirror. The amplifier A 1   630  provides a feedback signal  635  connecting to the gate of n-channel MOSFET N 3   633 . The drain of N 3   633  and N 5   615  is connected to output O  637 . In this circuit, n-channel MOS N 4   610 , the n-channel MOS N 5   615  and p-channel P 4   645  is added to the first embodiment. These transistors do not require high matching properties to other MOSFETs, and can be physically small. The n-channel N 5   615  is sinking equal to or less current than the source current of the p-channel MOS (PMOS) P 3   650 . The voltage gain A 1   630  control current of the n-channel N 3   630  are such that the n-channel currents of the third and fifth transistor (In 3 +In 5 ) are equal to p-channel current of the third PMOS Ip 3 . N-channel current of the third NMOS In 3 , n-channel current of the fifth NMOS In 5  and p-channel transistor current Ip 3  are drain currents of transistors N 3   633 , N 5   615  and P 3   650 , respectively. In this embodiment, the controllable range of current of the n-channel MOSFET N 3  is allowed to be narrow, so the loop gain is less than that in the first embodiment. The maintaining of stability in this embodiment is easier. 
       FIG. 7  is a circuit schematic of a voltage reference circuit  700  in accordance with an embodiment of the disclosure. The embodiment  700  comprises a VDD  701  and ground VSS  702 . A current mirror is formed with transistor N 1   720  and transistor N 2   725 . Differential inputs for amplifier A 1   730  are input  727  and input  729  connected to the drain of the N 1   720 , and N 2   725 . A second n-channel current mirror is formed with transistor N 4   710  and transistor  715 . A third current mirror is formed with p-channel MOSFET P 1   740 , P 4   745 , P 2   747  and P 3   750 . The current source  703  establishes a current Is and is connected to the p-channel MOSFET current mirror. The amplifier A 1   730  provides an output signal O  735  and feedback signal  737 . In this embodiment  700 , n-channel MOSFET N 4   710 , and N 5   715  and p-channel MOSFET P 4   745  do not require high-matching properties, and as a result, can be small (e.g. note that this is the same as in true in the previous embodiment). The current of the n-channel MOS (NMOS) N 5   715  should be less than the current of the p-channel MOS (PMOS) P 3   750  and the sum of the current of N 5   715  and the sink current of amplifier A 1   730  without load current is equal to the current of the  750 . In this circuit, the output voltage O  735  is just the output of amplifier A 1   730 . As a result, the output impedance can be very low and the circuit can drive a heavier load than other embodiments of this invention 
       FIG. 8  is a circuit schematic of a voltage reference circuit  800  in accordance with an embodiment of the disclosure. The embodiment  800  comprises a VDD  801  and ground VSS  802 . A current mirror is formed with transistor N 1   820  and transistor N 2   825 . Differential inputs for amplifier A 1   830  are input  827  and input  829  connected to the drain of the N 1   820 , and N 2   825 . A second current mirror is formed with p-channel MOSFETs P 1   840 , P 2   845 , and P 3   850 . The current source  803  establishes a current Is and is connected to the p-channel MOSFET current mirror. The amplifier A 1   830  provides an output signal O  835  and feedback signal  837 . In this embodiment  800 , N 4 , N 5  and P 4  of  FIG. 7  are not required. The output current range of amplifier A 1   835  is required wider than that of the previous embodiment ( FIG. 7 ) but the low output impedance is also expected as in the previous embodiment ( FIG. 7 ). The interesting feature of this circuit is that even though the output of this embodiment is the output of the amplifier A 1   830  itself, the offset voltage of the amplifier doesn&#39;t affect the voltage of O  835 . The above is true in a first order sense, but if the channel conductance of one of  720 ,  725 ,  747  and  750  at least is significantly large, then there is a second order impact on O  835  due to an offset on amplifier A 1   830  which would cause the drain source voltage difference. 
       FIG. 9  is a method for providing a voltage reference circuit in accordance with an embodiment of the disclosure. A method of a voltage reference circuit  900  comprises the steps, the first step  910  ( a ) providing a voltage reference circuit comprises a first MOSFET current mirror with a threshold voltage difference, a second MOSFET current mirror, an amplifier, a feedback loop, and an output signal, the second step  920  ( b ) establishing a drain voltage difference from said first MOSFET current mirror with a threshold voltage difference, the third step  930  ( c ) feeding the MOSFET drain voltages of said first MOSFET current mirror with a threshold voltage difference to the inputs of said amplifier, the fourth step  940  ( d ) establishing an amplifier output signal from said amplifier; and, the last step  950  ( e ) feeding the amplifier output signal to a feedback loop. 
     It is recognized by those skilled in the art that the embodiments in this disclosure can be implemented with the substitution of n-channel as p-channel MOSFETs and p-channel MOSFETs as n-channel MOSFETs with the modifications in the power supply and ground connections. It is also understood by those skilled in the art that the following disclosure can be achieved using other types of field effect transistor structures, such as lateral diffused MOS (LDMOS). In advanced technologies, it is also understood that the embodiments can be formed using FINFET devices instead of planar MOSFETs. 
     Other advantages will be recognized by those of ordinary skill in the art. The above detailed description of the disclosure, and the examples described therein, has been presented for the purposes of illustration and description. While the principles of the disclosure have been described above in connection with a specific device, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the disclosure.