Abstract:
An asymmetry detection circuit having a simple circuit configuration, capable of realizing reliable detection without dependance on the signal level, and capable of realizing high precision asymmetry detection almost completely free of any influence from a voltage offset or the like, and a detection method of same, wherein a capacitor cuts off a direct current component of an input signal and passes alternating current component, a bias voltage is added to the alternating current component in accordance with a constant voltage of a constant voltage source to generate an APL clamp signal, a comparator compares the signal with a constant voltage and outputs a pulse voltage signal representing a duty ratio of the signal in the APL value, a voltage/current conversion circuit outputs a current signal to charge or discharge a capacitor to generate an integrated signal, and a filter eliminates the alternating current component of the integrated signal and outputs the direct current component as an asymmetry detection signal.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to an asymmetry detection circuit for detecting the asymmetry of alternating current signals and a detection method of the same.  
           [0003]    2. Description of the Related Art  
           [0004]    In an asymmetry correction circuit or the like, in order to correct the asymmetry of alternating current signals, first the asymmetry of an input signal must be detected.  
           [0005]    Conventionally, the asymmetry of alternating current signals has been detected by comparing bias voltages of the signals with an intermediate potential of a signal amplitude. FIG. 4 shows an example of the conventional asymmetry detection circuit. As illustrated, this asymmetry detection circuit  200  is comprised by peak hold circuits  210  and  220 , an intermediate voltage detection circuit  230 , and an asymmetry processing circuit  240 .  
           [0006]    The peak hold circuit  210  holds the upper limit value (positive peak level S PK1 ) of an input signal S in , while the peak hold circuit  220  holds the lower limit value (negative peak level S PK2 ) of the same input signal S in .  
           [0007]    The intermediate voltage detection circuit  230  detects the intermediate voltage of the input signal S in  in accordance with the positive peak level S PK1  and the negative peak level S PK2  found by the peak hold circuits  210  and  220 .  
           [0008]    Here, assume that for example the input signal S in  has the waveform shown in FIG. 5. The peak hold circuit  210  detects the positive peak level S PK1  of this input signal S in , while the peak hold circuit  220  detects the negative peak level S PK2 . The intermediate voltage detection circuit  230  finds an intermediate voltage V 2  of the input signal S in  by the following equation based on the positive and negative peak levels S PK1  and S PK2  and outputs a signal S M  indicating the intermediate voltage to the asymmetry processing circuit  240 . 
             V   2 =( S   PK1   −S   PK2 )/2  (1) 
           [0009]    Namely, the intermediate voltage V 2  is the voltage in the middle of the positive peak level S PK1  and the negative peak level S PK2  of the input signal S in  in the waveform of the input signal S in  shown in FIG. 5 and is a voltage value where a=b stands as illustrated.  
           [0010]    The asymmetry processing circuit  240  calculates the asymmetry of the signal S in  according to the bias voltage V 1  of the input signal S in  and the intermediate voltage V 2  thereof.  
           [0011]    The asymmetry of alternating current signals is defined as a ratio of upper and lower peak voltages with respect to a direct current voltage level by which a duty ratio of the alternating current signals becomes 50%. The asymmetry processing circuit  240  can calculate the asymmetry of the input signal S in  based on the bias voltage V 1  of the input signal S in  and the intermediate voltage V 2  detected by the intermediate voltage detection circuit  230  according to this definition.  
           [0012]    Summarizing the problem to be solved by the invention, in a conventional asymmetry detection circuit, in order to find the asymmetry of an input signal, first the positive and negative peak levels of the signal are detected by the peak hold circuits, then the intermediate voltage V 1  of the signal amplitude is detected in accordance with the result. Therefore, the positive peak hold circuit and the negative peak hold circuit become necessary. The precision of the found intermediate voltage is largely governed by the holding characteristics of these circuits.  
           [0013]    On the other hand, there is no problem so far as the voltage applied to the alternating current signal as the reference bias voltage V 1  is clear, but if an offset or the like of the signal occurs in the middle of the path, the precision of the bias voltage V 1  is lowered. For example, when viewed by the path up to a comparison circuit for comparing the bias voltage V 1  and the intermediate voltage V 2  of the amplitude of the signal (not illustrated, for example existing inside the asymmetry processing circuit  240 ), the precision of the two are liable to differ and the precision of detection of the asymmetry is liable to fall due to an offset occurring in the peak hold circuit for finding the intermediate voltage V 2 .  
           [0014]    In order to prevent such a fall of the precision of detection of asymmetry, correction must be carried out in each circuit or the precision of detection of each circuit block must be raised, so there are disadvantages of an increased complexity of the system, sensitivity to fluctuations of measurement conditions or the signal level, and a susceptability to interference.  
         SUMMARY OF THE INVENTION  
         [0015]    An object of the present invention is to provide an asymmetry detection circuit having a simple circuit configuration, capable of realizing reliable detection without depending upon the signal level, and capable of realizing high precision asymmetry detection almost entirely free from the influence of voltage offset or the like, and a detection method of the same.  
           [0016]    To attain the above object, according to a first aspect of the invention, there is provided an asymmetry detection circuit having an alternating current separation means for outputting an alternating current component of an input signal, a clamping means for adding a predetermined bias voltage to the alternating current signal obtained from said alternating current separation means, a comparing means for comparing the output of said clamping means with a reference voltage in accordance with said bias voltage and outputting a pulse signal in accordance with a duty ratio of the output signal of said clamping means in accordance with the related comparison result, a voltage/current converting means for converting said pulse signal to a current signal, an integrating means for integrating said current signal and outputting an integrated signal, and a filter for eliminating the alternating current component of said integrated signal and outputting a direct current component.  
           [0017]    Preferably, said alternating current separation means comprises a capacitor cutting off the direct current component.  
           [0018]    Preferably, said integrating means comprises a capacitor charged or discharged by said current signal.  
           [0019]    Preferably, said filter comprises a low pass filter.  
           [0020]    According to a second aspect of the present invention, there is provided an asymmetry detection method for detecting the asymmetry of an input signal, comprised by the steps of cutting off a direct current component of said input signal and outputting an alternating current component, adding a predetermined bias voltage to said alternating current component and clamping said input signal by the related bias voltage, comparing said clamped signal and the reference voltage in accordance with said bias voltage and outputting a pulse signal representing the duty ratio of said clamped signal in accordance with the related comparison result, converting said pulse signal to a current signal, integrating said current signal and outputting an integrated signal, and eliminating the alternating current component of said integrated signal and outputting the direct current component. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the attached drawings, wherein:  
         [0022]    [0022]FIG. 1 is a circuit diagram of an embodiment of an asymmetry detection circuit according to the present invention;  
         [0023]    [0023]FIG. 2 is a waveform diagram showing a definition of asymmetry;  
         [0024]    [0024]FIG. 3 is a waveform diagram showing a principle of asymmetry detection in the present embodiment;  
         [0025]    [0025]FIG. 4 is a circuit diagram showing an example of a conventional asymmetry detection circuit; and  
         [0026]    [0026]FIG. 5 is a waveform diagram showing a principle of detection of the conventional asymmetry detection circuit. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0027]    [0027]FIG. 1 is a circuit diagram of an embodiment of an asymmetry detection circuit according to the present invention.  
         [0028]    As illustrated, an asymmetry detection circuit  100  of the present embodiment is constituted by a duty ratio detection circuit  110 , a filter  120 , and a capacitor  130  (C 2 ).  
         [0029]    The duty ratio detection circuit  110  is comprised by a capacitor  140  (C 1 ), resistor  150  (R 1 ), constant voltage source  160  (V 2 ), comparator  170 , and voltage/current converter (V/I converter)  180 .  
         [0030]    Below, an explanation will be given of the configurations and functions of parts of the asymmetry detection circuit of the present invention by referring to FIG. 1.  
         [0031]    In the duty ratio detection circuit  110 , the capacitor  140  cuts off the direct current component of the input signal S in  and allows only the alternating current component to pass through.  
         [0032]    The constant voltage source  160  supplies any constant voltage V 2  as the reference voltage.  
         [0033]    The capacitor  140 , the resistor  150 , and the constant voltage source  160  give a bias voltage in accordance with the constant voltage V in  to the input signal S in  as an average picture level (APL) value. Namely, the input signal S in  is clamped according to the constant voltage V 2 .  
         [0034]    As illustrated, the input signal S in  is input to one input terminal T in1  of the comparator  170  via the capacitor  140 . The resistor  150  and the constant voltage source  160  are connected in series between the input terminal T in1  of the comparator  170  and a reference potential (ground potential) GND. A middle point of connection of the resistor  150  and the constant voltage source  160  is connected to the other input terminal T in2  of the comparator  170 .  
         [0035]    For this reason, a signal S AC  obtained by APL clamping the input signal S in  is applied to the input terminal T in1  of the comparator  170 , and the constant voltage V 2  is input as the reference voltage to the input terminal T in2 .  
         [0036]    The comparator  170  compares the signal S AC  and the reference voltage V 2  and outputs a pulse voltage signal V CMP  in accordance with the result of comparison. In the comparator  170 , the reference voltage for comparison of the signal S AC  is the APL value. Therefore, as a result of comparison of these signals, a voltage pulse V CMP  in accordance with the duty ratio in the APL value is output.  
         [0037]    The voltage/current conversion circuit  180  converts the input voltage signal to a current signal. Namely, the voltage/current conversion circuit  180  outputs a current I C  in accordance with the voltage V CMP  output by the comparator  170 .  
         [0038]    The capacitor  130  is charged or discharged by the current I C  output by the voltage/current conversion circuit  180 . Due to this, an integrated voltage V C  is obtained from the terminal of the capacitor  130  in accordance with the output current I C .  
         [0039]    The integrated voltage V C  obtained by the capacitor  130  is input to the filter  120 . The filter  120  is comprised by for example a low pass filter. By the low pass filter, the alternating current signal component contained in the integrated voltage V C  is eliminated. As a result, the direct current component contained in the integrated voltage V C  is output. The direct current component is output as an asymmetry detection result S ASYM  of the input signal S in .  
         [0040]    Next, an explanation will be made of the principle of asymmetry detection in the present embodiment by referring to the waveform diagrams shown in FIG. 2 and FIG. 3.  
         [0041]    [0041]FIG. 2 is a waveform diagram of the definition of asymmetry of alternating current signals. The asymmetry of the alternating current signals is defined as the ratio between the upper limit peak value and the lower limit peak value with respect to the direct current voltage value by which the duty ratio becomes 50%.  
         [0042]    As illustrated, it is assumed that the duty ratio becomes 50% when the alternating current signal S in  is clamped by the voltage V 1 . At this time, when the upper limit value of the signal S in  that is, the positive peak level, is A, and the lower limit value, that is, the negative peak level, is B with respect to the voltage V 1 , the asymmetry ASYM of the signal S in  is found by the following equation: 
         ASYM=( A−B )/( A+B )×100%  (2) 
         [0043]    According to equation (2), the case where the asymmetry ASYM is 0% arises when the upper limit value and the lower limit value are equal and A=B. Namely, when the asymmetry ASYM is 0%, the alternating current signals exhibit completely vertically symmetrical shapes.  
         [0044]    Here, consider a triangle with a bottom side set at the duty ratio and with a height set at the peak value (upper limit value or lower limit value). As areas of this triangle, a positive side area S p  and a negative side area S n  can be found as follows. 
           S   p =50 ×A /2  (3) 
           S   n =50× A /2  (4) 
         [0045]    [0045]FIG. 3 shows the area S p  and the area S n  with respect to the case where the input signal S in  has the APL value (voltage V 2 ).  
         [0046]    When the asymmetry is 0, S p  and S n  found according to equations (3) and (4) satisfy the following equation: 
           S   p   =S   n   (5) 
         [0047]    On the other hand, when the asymmetry is a number other than 0, S p  and S n  found according to equations (3) and (4) satisfy the following equation: 
           S   p   ≠S   n   (6) 
         [0048]    On the other hand, the APL value is the average value of the alternating current signals, so is a direct current voltage value always satisfying equation (5). When the asymmetry is a number other than 0, A is not equal to B. In the APL value, by equation (5), the duty ratio does not become equal to 50%.  
         [0049]    Namely, even if the peak level of the alternating current signals is not monitored, by monitoring the duty ratio in the APL value of the alternating current signals, the asymmetry of the alternating current signals can be detected.  
         [0050]    Below, an explanation will be made of the operation of the asymmetry detection in the asymmetry detection circuit of the present embodiment by referring to FIG. 1.  
         [0051]    First, the input alternating current signal S in  is input to the duty ratio detection circuit  110 . In the duty ratio detection circuit  110 , the direct current component of the input signal S in  is cut off by the capacitor  140 . Further, by the resistor  150  and the constant voltage source  160 , the signal S AC  APL clamped at the constant voltage V 2  is obtained and input to the input terminal T in1  of the comparator  170 . The constant voltage V 2  is input as a comparison reference voltage to the input terminal T in2  of the comparator  170 .  
         [0052]    In the comparator  170 , signals input to the input terminals T in1  and T in2  are compared. As a result of comparison, a voltage pulse V CMP  indicating the duty ratio in the APL value is output. Namely, the duty ratio of the input signal S in  with respect to the APL value is represented by the pulse width of the output pulse signal V CMP  of the comparator  170 .  
         [0053]    The voltage pulse signal V CMP  output from the comparator  170  is input to the voltage/current conversion circuit  180 . As a result of the conversion, a current signal I C  in accordance with the voltage pulse signal V CMP  is output.  
         [0054]    The capacitor  130  is charged or discharged by the current signal I C . Namely, the current signal I C  is integrated, and a voltage V C  is obtained as the integrated signal from the terminal of the capacitor  130 .  
         [0055]    By the filter  120 , the alternating current component of the integrated signal V C  is eliminated, and only the direct current component is output. This output signal indicates the asymmetry of the input signal S in  and is output as the asymmetry detection signal S ASYM .  
         [0056]    As explained above, according to the present embodiment, by just using a simple circuit, it is possible to reliably detect the asymmetry of the input signal. Also, in the duty ratio detection circuit, since the APL value is given by the constant voltage source, the signal S AC  obtained by clamping the input signal S in  by the APL value is generated, and further the signal S AC  and the voltage V 2  of the constant voltage source serving as the reference voltage are compared by the comparator  170 , the duty ratio can be correctly detected. By the voltage/current conversion circuit  180 , the duty ratio detection result is converted to the current signal I C , the integrated signal V C  is found by the capacitor  130  in accordance with that, and the asymmetry can be detected in accordance with the direct current component of the integrated signal. For this reason, it is possible to reliably detect the asymmetry almost completely free of any influence from fluctuation of the signal. Further, the circuit configuration is extremely simple. For example, for the comparison circuit  170 , voltage/current conversion circuit  180 , and the filter  120 , it is not necessary to use particularly limited elements. Already existing elements can be used. Therefore, development and manufacturing costs of a system including an asymmetry detection circuit can be kept low.  
         [0057]    Summarizing the effects of the invention, as explained above, according to the asymmetry detection circuit of the present invention and the detection method of the same, asymmetry can be reliably detected by a simple circuit configuration and the result of detection of asymmetry is obtained based on the result of integration of the signal, so not only can the detection result be output as a voltage signal, but also reliable detection can be realized without dependance on the fluctuation of level of the input signal.  
         [0058]    Further, according to the present invention, there is almost no influence of direct current offset of the input signal and offset occurring in the signal processing circuit, so there is the advantage that a high precision can be held in the result of detection of asymmetry.  
         [0059]    While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention.