Abstract:
A semiconductor device that includes an adaptive phase locked loop with improved loop stability and a faster locking rate. In one embodiment, this is accomplished in a manner that does not require an additional second charge pump for loop stability, and therefore the resulting phase locked loop of the present invention consumes less chip die area. In another embodiment, multiple charge pumps are used and the resulting response time for locking is improved over that which can be achieved by conventional embodiments.

Description:
RELATED APPLCATIONS  
       [0001]     This application claims priority under 35 U.S.C. 119 to Korean Patent Application KR2004-24570, filed Apr. 9, 2004, the contents of which are incorporated herein by reference, in their entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     Communication between integrated circuit systems commonly requires that the phase and/or frequency of an input signal be matched, or “locked” to a local signal, such as a clock signal. A typical system for accomplishing this is the phase-locked loop (PLL).  
         [0003]      FIG. 1  is a block diagram of a conventional phase locked loop configuration. The conventional PLL  11  includes a phase frequency detector (PFD)  10 , a first charge pump (CP)  12 , an operational amplifier  16 , and a voltage controlled oscillator (VCO)  18 . An optional second charge pump (CP)  14  may also be included.  
         [0004]     The phase frequency detector  10  measures a phase difference between a received reference clock signal RCLK and a feedback clock signal VCLK. In response to the difference in phase between the clock signals, the phase frequency detector  10  generates an up control signal up and a down control signal dn, which are provided to the first charge pump  12 . The first charge pump  12 , in turn, charges and discharges a first capacitor C p  of a loop filter in response to the up control signal up and down control signal dn, in turn generating a loop filter control voltage V p . The loop filter control voltage V p  is provided to the VCO to determine the output frequency of the VCO  18 .  
         [0005]     In combination, the first charge pump  12  and first capacitor provide a pole for the feedback loop, however, it is preferred that a loop-stabilizing zero also be included in order to maintain stability in the phase locked loop. A resistor can be placed in series with the first capacitor C p  for this purpose. This embodiment, however, is prone to process and temperature variation, which, in turn, can lead to variable operation characteristics. In addition, the value of the series resistor is difficult to adjust and reproduce accurately.  
         [0006]     In an alternative embodiment shown in  FIG. 1 , a zero for the feedback loop is provided by the combination of the second charge pump  14 , the operational amplifier  16 , and a second capacitor C c . The second charge pump  14  receives the up control signal up and down control signal dn, and, in response, charges and discharges the second capacitor C c . The operational amplifier  16  receives at a positive input terminal the loop filter control voltage V p , and provides, at an output terminal, a VCO control voltage V c , that is applied to the second capacitor C c . A closed-loop negative feedback signal is provided between the output terminal and negative input terminal of the operational amplifier  16 . The VCO control voltage V c  is applied to the VCO to determine the output frequency of the VCO  18 .  
         [0007]     While the configuration of  FIG. 1  provides for a relatively stable phase locked loop operation, the current I p  that is provided by the first charge pump  12  is fixed, and therefore, the locking time period for the loop is less than optimal. Also, the second charge pump  14  used in combination with the operational amplifier  16  to improve loop stability requires a large area of the chip die, leading to manufacturing inefficiencies.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention is directed to a semiconductor device that includes an adaptive phase locked loop with improved loop stability and a faster locking rate. In one embodiment, this is accomplished in a manner that does not require an additional second charge pump for loop stability, and therefore the resulting phase locked loop of the present invention consumes less chip die area. In another embodiment, multiple charge pumps are used and the resulting response time for locking is improved over that which can be achieved by conventional embodiments.  
         [0009]     In a first aspect, the present invention is directed to a phase locked loop. A first charge pump receives first and second control signals generated in response to a comparison of phases of a reference clock signal and a feedback signal and, in response, generates a first charge pump signal. A loop filter includes an operational amplifier having a first input that receives the first charge pump signal, second and third inputs that receive the first and second control signals respectively, and a fourth input that receives a control voltage, and an output that generates the control voltage in response to the signals provided at the first, second, third and fourth inputs. A voltage controlled oscillator receives the control voltage and, in response, generates the feedback clock signal.  
         [0010]     In one embodiment, a phase detector receives the reference clock signal and the feedback clock signal, compares their respective phases, and generates the first and second control signals in response to the comparison. In another embodiment, a phase-frequency detector receives the reference clock signal and the feedback clock signal, compares their respective phases and frequencies, and generates the first and second control signals in response to the comparison.  
         [0011]     In another embodiment, the first control signal comprises an up control signal and wherein the second control signal comprises a down control signal. The first control signal is activated in response to the rising edge of the reference clock signal and the second control signal is activated in response to the rising edge of the feedback clock signal.  
         [0012]     In another embodiment, the operational amplifier comprises: a first transistor, coupled between a first voltage supply and a first node, and a gate of which is coupled to a drain of which at a first node; a second transistor, coupled between the first voltage supply and a second node, and a gate of which is coupled to the first node; a third transistor and a fourth transistor coupled in series between the first node and a third node, a gate of one of the third and fourth transistors being coupled to the first control signal and a gate of the other of the third and fourth transistors being coupled to the first charge pump signal; a fifth transistor, coupled between the first node and the third node, and a gate of which is coupled to the first charge pump signal; a sixth transistor and a seventh transistor coupled in series between the second node and the third node, a gate of one of the sixth and seventh transistors being coupled to the second control signal and a gate of the other of the sixth and seventh transistors being coupled to the control voltage signal; an eighth transistor, coupled between the second node and the third node, a gate of which is coupled to the control voltage signal; and a ninth transistor, coupled between the third node and a ground reference voltage, and a gate of which receives a voltage bias signal. The first and second transistors comprise PMOS transistors, and the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors comprise NMOS transistors.  
         [0013]     In another embodiment, the voltage bias signal is derived from the first charge pump signal  
         [0014]     In another embodiment, the first charge pump comprises a first current source and a first charge pump transistor in series between a first voltage supply and a first node, and a second charge pump transistor and a second current source in series between the first node and a ground reference voltage, the first charge pump transistor being activated in response to the first control signal and the second charge pump transistor being activated in response to the second control signal, the first charge pump providing the charge pump signal at the first node. The first charge pump transistor comprises a PMOS transistor and the first control signal comprises an inverted up control signal; the second charge pump transistor comprises an NMOS transistor and the second control signal comprises a down control signal.  
         [0015]     In another embodiment, the operational amplifier of the loop filter comprises a first operational amplifier and the control voltage generated by the first operational amplifier comprises a first control voltage, and a second operational amplifier receives the first control voltage at a first input and that generates a second control voltage that is provided to the voltage controlled oscillator, a second input of the second operational amplifier receiving the second control voltage via a feedback path.  
         [0016]     In another embodiment, the phase locked loop further comprises: a pulse width filter that receives the first control signal, and in response, generates a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period; and that receives the second control signal, and in response, generates a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; and a second charge pump that receives the first and second auxiliary control signals and, in response, generates an auxiliary charge pump signal, the auxiliary charge pump signal being applied to the first input of the operational amplifier in combination with the first charge pump signal. A control signal generator receives the first and second auxiliary control signals and, if either of the first and second auxiliary control signals is active, generates a third control signal, and the operational amplifier includes a fifth input that receives the third control signal, and generates the control voltage further in response to the third control signal. In another embodiment, the control signal generator comprises an OR gate, a first input of which receives the first auxiliary control signal, a second input of which receives the second auxiliary control signal, and an output of which provides the third control signal.  
         [0017]     In another embodiment, the operational amplifier comprises: a first transistor, coupled between a first voltage supply and a first node, and a gate of which is coupled to a drain of which at a first node; a second transistor, coupled between the first voltage supply and a second node, and a gate of which is coupled to the first node; a third transistor and a fourth transistor coupled in series between the first node and a third node, a gate of one of the third and fourth transistors being coupled to the first control signal and a gate of the other of the third and fourth transistors being coupled to the first charge pump signal; a fifth transistor and a sixth transistor coupled in series between the first node and the third node, a gate of one of the fifth and sixth transistors being coupled to the third control signal and a gate of the other of the fifth and sixth transistors being coupled to the first charge pump signal; a seventh transistor, coupled between the first node and the third node, a gate of which is coupled to the charge pump signal; a eighth transistor and a ninth transistor coupled in series between the second node and the third node, a gate of one of the eighth and ninth transistors being coupled to the second control signal and a gate of the other of the eighth and ninth NMOS transistors being coupled to the control voltage signal; a tenth transistor and an eleventh transistor coupled in series between the second node and the third node, a gate of one of the tenth and eleventh transistors being coupled to the third control signal and a gate of the other of the tenth and eleventh transistors being coupled to the control voltage signal; a twelfth transistor, coupled between the second node and the third node, and a gate of which is coupled to the control voltage signal; and a thirteenth transistor, coupled between the third node and a ground reference voltage, and a gate of which receives a voltage bias signal. The first and second transistors comprise PMOS transistors, and wherein third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, and thirteenth transistors comprise NMOS transistors.  
         [0018]     In another embodiment, the pulse width filter comprises first, second and third transistors in series between a first voltage supply and a ground reference voltage, gates of the first and second transistors receiving one of the first and second control signals; a delay circuit receiving the one of the first and second control signals to generate a delayed control signal, the control signal being applied to a gate of the third transistor; a corresponding one of the first and second auxiliary control signals being provided at a node between the first and second transistors.  
         [0019]     In another embodiment, the second charge pump comprises a third current source and a third charge pump transistor in series between a first voltage supply and a second node, and a fourth charge pump transistor and a fourth current source in series between the second node and a ground reference voltage, the third charge pump transistor being activated in response to the first auxiliary control signal and the second charge pump transistor being activated in response to the second auxiliary control signal, the second charge pump providing the auxiliary charge pump signal at the second node. The third charge pump transistor comprises a PMOS transistor and the first auxiliary control signal comprises an inverted auxiliary up control signal and the fourth charge pump transistor comprises an NMOS transistor and the second control signal comprises the auxiliary down control signal.  
         [0020]     In another embodiment, the loop filter further includes a first capacitor between the first input of the operational amplifier and a ground reference voltage and a second capacitor between the output of the operational amplifier and the ground reference voltage.  
         [0021]     In another aspect, the present invention is directed to a phase locked loop comprising: a phase detector that receives a reference clock signal and a feedback clock signal, compares a difference in phase between the reference clock signal and the feedback clock signal, and generates first and second control signals in response to the comparison; a first charge pump that receives the first and second control signals and that, in response, generates a first charge pump signal; a pulse width filter that receives the first control signal, and in response, generates a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period, and that receives the second control signal, and in response, generates a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; and a second charge pump that receives the first and second auxiliary control signals and, in response, generates an auxiliary charge pump signal; a loop filter that receives the first charge pump signal and, in response, generates a control voltage, the loop filter comprising an operational amplifier having a first input that receives in combination the first charge pump signal and the auxiliary charge pump signal, second and third inputs that receive the first and second control signals respectively, and a fourth input that receives a control voltage, and an output that generates the control voltage in response to the signals provided at the first, second, third and fourth inputs; and a voltage controlled oscillator that receives the control voltage and, in response, generates the reference clock signal.  
         [0022]     In one embodiment, a control signal generator receives the first and second auxiliary control signals and if either of the first and second auxiliary control signals is active, generates a third control signal, and the operational amplifier includes a fifth input that receives the third control signal, and generates the control voltage further in response to the third control signal. The control signal generator comprises an OR gate, a first input of which receives the first auxiliary control signal, a second input of which receives the second auxiliary control signal, and an output of which generates the third control signal  
         [0023]     In one embodiment, when the phase locked loop operates in a first mode of operation, the reference clock signal and the feedback clock signal are substantially locked and when the phase locked loop operates in a second mode of operation, the reference clock signal and the feedback clock signal are out of phase by at least a predetermined amount; and wherein, when the phase locked loop operates in the first mode, the first charge pump is active and the second charge pump is inactive; and when the phase locked loop operates in the second mode of operation, the first charge pump is active and the second charge pump is active.  
         [0024]     In another aspect, the present invention is directed to a phase locked loop comprising: a phase detector that receives a reference clock signal and a feedback clock signal, compares a difference in phase of the reference clock signal and the feedback clock signal, and generates first and second control signals in response to the comparison; a first charge pump that receives the first and second control signals and that, in response, generates a first charge pump signal; a pulse width filter that receives the first control signal, and in response, generates a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period, and that receives the second control signal, and in response, generates a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; a second charge pump that receives the first and second auxiliary control signals and, in response, generates a second charge pump signal; a third charge pump that receives the first and second control signals and, in response, generates a third charge pump signal; a fourth charge pump that receives the first and second control signals and the first and second auxiliary control signals and, in response, generates a fourth charge pump signal; a loop filter comprising an operational amplifier having a first input that receives in combination the first charge pump signal and the second charge pump signal, having a second input that receives in combination the third charge pump signal, the fourth charge pump signal and a control voltage signal, and having an output that generates the control voltage signal in response to the signals provided at the first and second inputs; and a voltage controlled oscillator that receives the control voltage and, in response, generates the reference clock signal.  
         [0025]     In one embodiment, when the phase locked loop operates in a first mode of operation, the reference clock signal and the feedback clock signal are substantially locked and when the phase locked loop operates in a second mode of operation, the reference clock signal and the feedback clock signal are out of phase by at least a predetermined amount; and wherein, when the phase locked loop operates in the first mode, the first charge pump, third charge pump and fourth charge pump are active and the second charge pump is inactive; and when the phase locked loop operates in the second mode of operation, the first charge pump, second charge pump and third charge pump are active and the fourth charge pump is inactive.  
         [0026]     In one embodiment, the first charge pump comprises a first current source and a first charge pump transistor in series between a first voltage supply and a first node, and a second charge pump transistor and a second current source in series between the first node and a ground reference voltage, the first charge pump transistor being activated in response to the first control signal and the second charge pump transistor being activated in response to the second control signal, the first charge pump providing the first charge pump signal at the first node.  
         [0027]     In one embodiment, the second charge pump comprises a third current source and a third charge pump transistor in series between a first voltage supply and a second node, and a fourth charge pump transistor and a fourth current source in series between the second node and a ground reference voltage, the third charge pump transistor being activated in response to the first auxiliary control signal and the second charge pump transistor being activated in response to the second auxiliary control signal, the second charge pump providing the second charge pump signal at the second node.  
         [0028]     In one embodiment, the third charge pump comprises a fifth current source and a fifth charge pump transistor in series between a first voltage supply and a third node, and a sixth charge pump transistor and a sixth current source in series between the third node and a ground reference voltage, the fifth charge pump transistor being activated in response to the first control signal and the sixth charge pump transistor being activated in response to the second control signal, the third charge pump providing the third charge pump signal at the third node.  
         [0029]     In one embodiment, the fourth charge pump comprises a seventh current source and seventh and eighth charge pump transistors in series between a first voltage supply and a fourth node, and ninth and tenth charge pump transistors and an eighth current source in series between the third node and a ground reference voltage, the seventh charge pump transistor being activated in response to the first control signal, the eighth charge pump transistor being activated in response to the first auxiliary control signal, the ninth charge pump transistor being activated in response to the second auxiliary control signal and the tenth charge pump transistor being activated in response to the second control signal, the fourth charge pump providing the fourth charge pump signal at the fourth node.  
         [0030]     In another aspect, the present invention is directed to a memory device comprising: a plurality of addressable memory cells, each cell comprising a data storage element; a decoder that receives an address from an external source, and that generates a row signal and a column signal for accessing at least one of the addressable memory cells; and a phase locked loop. The phase locked loop comprises: a first charge pump that receives first and second control signals generated in response to a comparison of phases of a reference clock signal and a feedback signal and that, in response, generates a first charge pump signal; a loop filter comprising an operational amplifier having a first input that receives the first charge pump signal, second and third inputs that receive the first and second control signals respectively, and a fourth input that receives a control voltage, and an output that generates the control voltage in response to the signals provided at the first, second, third and fourth inputs; and a voltage controlled oscillator that receives the control voltage signal and, in response, generates the feedback clock signal.  
         [0031]     In one embodiment, the operational amplifier of the loop filter comprises a first operational amplifier and wherein the control voltage generated by the first operational amplifier comprises a first control voltage, and further comprising a second operational amplifier that receives the first control voltage at a first input and that generates a second control voltage that is provided to the voltage controlled oscillator, a second input of the second operational amplifier receiving the second control voltage via a feedback path.  
         [0032]     In another embodiment, the memory device further comprises: a pulse width filter that receives the first control signal, and in response, generates a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period; and that receives the second control signal, and in response, generates a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; and a second charge pump that receives the first and second auxiliary control signals and, in response, generates an auxiliary charge pump signal, the auxiliary charge pump signal being applied to the first input of the operational amplifier in combination with the first charge pump signal.  
         [0033]     In another embodiment, the memory device further comprises a control signal generator that receives the first and second auxiliary control signals and that, if either of the first and second auxiliary control signals is active, generates a third control signal, and wherein the operational amplifier includes a fifth input that receives the third control signal, and generates the control voltage further in response to the third control signal.  
         [0034]     In another aspect, the present invention is directed to a memory device comprising: a plurality of addressable memory cells, each cell comprising a data storage element; a decoder that receives an address from an external source, and that generates a row signal and a column signal for accessing at least one of the addressable memory cells; and a phase locked loop. The phase locked loop comprises a phase detector that receives a reference clock signal and a feedback clock signal, compares a difference in phase of the reference clock signal and the feedback clock signal, and generates first and second control signals in response to the comparison; a first charge pump that receives the first and second control signals and that, in response, generates a first charge pump signal; a pulse width filter that receives the first control signal, and in response, generates a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period, and that receives the second control signal, and in response, generates a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; a second charge pump that receives the first and second auxiliary control signals and, in response, generates a second charge pump signal; a third charge pump that receives the first and second control signals and, in response, generates a third charge pump signal; a fourth charge pump that receives the first and second control signals and the first and second auxiliary control signals and, in response, generates a fourth charge pump signal; a loop filter comprising an operational amplifier having a first input that receives in combination the first charge pump signal and the second charge pump signal, having a second input that receives in combination the third charge pump signal, the fourth charge pump signal and a control voltage signal, and having an output that generates the control voltage signal in response to the signals provided at the first and second inputs; and a voltage controlled oscillator that receives the control voltage signal and, in response, generates the reference clock signal.  
         [0035]     In another aspect, the present invention is directed to a memory system comprising: a memory controller that generates command and address signals; and a memory module comprising a plurality of memory devices, the memory module receiving the command and address signals and in response storing and retrieving data to and from the memory device, wherein each memory device comprises: a plurality of addressable memory cells, each cell comprising a data storage element; a decoder that receives an address from an external source, and that generates a row signal and a column signal for accessing at least one of the addressable memory cells; and a phase locked loop. The phase locked loop comprises: a first charge pump that receives first and second control signals generated in response to a comparison of phases of a reference clock signal and a feedback signal and that, in response, generates a first charge pump signal; a loop filter comprising an operational amplifier having a first input that receives the first charge pump signal, second and third inputs that receive the first and second control signals respectively, and a fourth input that receives a control voltage, and an output that generates the control voltage in response to the signals provided at the first, second, third and fourth inputs; and a voltage controlled oscillator that receives the control voltage signal and, in response, generates the feedback clock signal.  
         [0036]     In one embodiment, the operational amplifier of the loop filter comprises a first operational amplifier and wherein the control voltage generated by the first operational amplifier comprises a first control voltage, and further comprising a second operational amplifier that receives the first control voltage at a first input and that generates a second control voltage that is provided to the voltage controlled oscillator, a second input of the second operational amplifier receiving the second control voltage via a feedback path.  
         [0037]     In another embodiment, the memory system further comprises: a pulse width filter that receives the first control signal, and in response, generates a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period; and that receives the second control signal, and in response, generates a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; and a second charge pump that receives the first and second auxiliary control signals and, in response, generates an auxiliary charge pump signal, the auxiliary charge pump signal being applied to the first input of the operational amplifier in combination with the first charge pump signal.  
         [0038]     In another embodiment, the memory system further comprises a control signal generator that receives the first and second auxiliary control signals and that, if either of the first and second auxiliary control signals is active, generates a third control signal, and wherein the operational amplifier includes a fifth input that receives the third control signal, and generates the control voltage further in response to the third control signal.  
         [0039]     In another aspect, the present invention is directed to a memory system comprising: a memory controller that generates command and address signals; and a memory module comprising a plurality of memory devices, the memory module receiving the command and address signals and in response storing and retrieving data to and from the memory device, wherein each memory device comprises: a plurality of addressable memory cells, each cell comprising a data storage element; a decoder that receives an address from an external source, and that generates a row signal and a column signal for accessing at least one of the addressable memory cells; and a phase locked loop. The phase locked loop comprises: a phase detector that receives a reference clock signal and a feedback clock signal, compares a difference in phase of the reference clock signal and the feedback clock signal, and generates first and second control signals in response to the comparison; a first charge pump that receives the first and second control signals and that, in response, generates a first charge pump signal; a pulse width filter that receives the first control signal, and in response, generates a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period, and that receives the second control signal, and in response, generates a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; a second charge pump that receives the first and second auxiliary control signals and, in response, generates a second charge pump signal; a third charge pump that receives the first and second control signals and, in response, generates a third charge pump signal; a fourth charge pump that receives the first and second control signals and the first and second auxiliary control signals and, in response, generates a fourth charge pump signal; a loop filter comprising an operational amplifier having a first input that receives in combination the first charge pump signal and the second charge pump signal, having a second input that receives in combination the third charge pump signal, the fourth charge pump signal and a control voltage signal, and having an output that generates the control voltage signal in response to the signals provided at the first and second inputs; and a voltage controlled oscillator that receives the control voltage signal and, in response, generates the reference clock signal.  
         [0040]     In another aspect, the present invention is directed to a method comprising: receiving at a first charge pump first and second control signals generated in response to a comparison of phases of a reference clock signal and a feedback signal and, in response, generating a first charge pump signal; receiving at an operational amplifier the first charge pump signal at a first input, receiving the first and second control signals respectively at second and third inputs of the operational amplifier, and receiving a control voltage at a fourth input of the operational amplifier, and generating, at an output of the operational amplifier, the control voltage in response to the signals provided at the first, second, third and fourth inputs; and receiving the control voltage signal at a voltage controlled oscillator, and, in response, generating the feedback clock signal.  
         [0041]     In one embodiment of the method, the operational amplifier comprises a first operational amplifier and wherein the control voltage generated by the first operational amplifier comprises a first control voltage, and further comprising receiving at a second operational amplifier the first control voltage at a first input and generating a second control voltage that is provided to the voltage controlled oscillator, a second input of the second operational amplifier receiving the second control voltage via a feedback path.  
         [0042]     In another embodiment, the method further comprises: receiving at a pulse width filter the first control signal, and in response, generating a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period; and receiving at the pulse width filter the second control signal, and in response, generating a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; and receiving at a second charge pump the first and second auxiliary control signals and, in response, generating an auxiliary charge pump signal, the auxiliary charge pump signal being applied to the first input of the operational amplifier in combination with the first charge pump signal.  
         [0043]     In another embodiment, the method further comprises: receiving at a control signal generator the first and second auxiliary control signals and, if either of the first and second auxiliary control signals is active, generating a third control signal, and receiving at a fifth input of the operational amplifier the third control signal, and generating at the output of the operational amplifier the control voltage further in response to the third control signal.  
         [0044]     In another aspect, the present invention is directed to a method comprising: receiving at a phase detector, a reference clock signal and a feedback clock signal, comparing a difference in phase of the reference clock signal and the feedback clock signal, and generating first and second control signals in response to the comparison; receiving at a first charge pump the first and second control signals and, in response, generating a first charge pump signal; receiving at a pulse width filter the first control signal, and in response, generating a first auxiliary control signal when the first control signal is active for greater than a first predetermined time period, and receiving the second control signal, and in response, generating a second auxiliary control signal when the second control signal is active for greater than a second predetermined time period; receiving at a second charge pump the first and second auxiliary control signals and, in response, generating a second charge pump signal; receiving at a third charge pump the first and second control signals and, in response, generating a third charge pump signal; receiving at a fourth charge pump the first and second control signals and the first and second auxiliary control signals and, in response, generating a fourth charge pump signal; receiving at a loop filter comprising an operational amplifier in combination at a first input the first charge pump signal and the second charge pump signal, receiving in combination at a second input the third charge pump signal, the fourth charge pump signal and a control voltage signal, and generating at an output the control voltage signal in response to the signals provided at the first and second inputs; and receiving at a voltage controlled oscillator the control voltage signal and, in response, generating the reference clock signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0045]     The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.  
         [0046]      FIG. 1  is a block diagram of a conventional phase locked loop configuration.  
         [0047]      FIG. 2  is a block diagram of an embodiment of a phase locked loop configuration in accordance with the present invention.  
         [0048]      FIG. 3  is a detailed schematic diagram of the operational amplifier of the phase locked loop of  FIG. 2 , in accordance with the present invention.  
         [0049]      FIG. 4A  is a first timing diagram of signals of the phase locked loop of  FIG. 2 , in the case where the reference clock signal leads the feedback output clock signal, in accordance with the present invention.  
         [0050]      FIG. 4B  is a second timing diagram of signals of the phase locked loop of  FIG. 2 , in the case where the reference clock signal lags the feedback clock signal, in accordance with the present invention.  
         [0051]      FIG. 5  is a block diagram of a second embodiment of a phase locked loop configuration in accordance with the present invention.  
         [0052]      FIG. 6  is a block diagram of a third embodiment of a phase locked loop configuration in accordance with the present invention.  
         [0053]      FIG. 7  is a detailed schematic diagram of the pulse width filter (PWF) of the third phase locked loop embodiment of  FIG. 6 , in accordance with the present invention.  
         [0054]      FIG. 8A  is a first timing diagram of signals of the pulse width filter of the third phase locked loop embodiment of  FIG. 2 , in the case where the reference clock signal leads the output clock signal, in accordance with the present invention.  
         [0055]      FIG. 8B  is a second timing diagram of signals of the pulse width filter of the third phase locked loop embodiment of  FIG. 2 , in the case where the reference clock signal lags the output clock signal, in accordance with the present invention.  
         [0056]      FIGS. 9A and 9B  are detailed schematic diagrams of the first  44  and second  46  charge pumps (CP) respectively of the third phase locked loop embodiment of  FIG. 6 , in accordance with the present invention.  
         [0057]      FIG. 10  is a detailed schematic diagram of the operational amplifier of the third phase locked loop embodiment of  FIG. 6 , in accordance with the present invention.  
         [0058]      FIG. 11  is a block diagram of a fourth embodiment of a phase locked loop configuration in accordance with the present invention.  
         [0059]      FIGS. 12A and 12B  are detailed schematic diagrams of the third and fourth charge pumps respectively of the fourth phase locked loop embodiment of  FIG. 11 , in accordance with the present invention.  
         [0060]     FIGS.  13 A_ 1  and  13 A_ 2  are timing diagrams of signals of the fourth phase locked loop embodiment of  FIG. 11 , illustrating the first mode of operation of the fourth embodiment, in accordance with the present invention.  
         [0061]     FIGS.  13 B_ 1  and  13 B_ 2  are additional timing diagrams of signals of the fourth phase locked loop embodiment of  FIG. 11 , illustrating the first and second modes of operation of the fourth embodiment, in accordance with the present invention.  
         [0062]      FIG. 14  is a waveform diagram, illustrating the step response of the third phase locked loop embodiment of  FIG. 6 , in accordance with the present invention, as compared to the response of the conventional apparatus.  
         [0063]      FIG. 15  is a block diagram of a memory system in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0064]      FIG. 2  is a block diagram of an embodiment of a phase locked loop (PLL) configuration in accordance with the present invention. The PLL  21  includes a phase frequency detector (PFD)  20 , a first charge pump (CP)  22 , an operational amplifier  24 , and a voltage controlled oscillator (VCO)  26 .  
         [0065]     The phase frequency detector  20  measures a phase difference between a received reference clock signal RCLK and a feedback clock signal VCLK. In response to the difference in phase between the clock signals, the phase frequency detector  20  generates an up control signal up and a down control signal dn, which are provided to the first charge pump  22 . The first charge pump  22 , in turn, charges and discharges a first capacitor C p  of a loop filter in response to the up control signal up and down control signal dn, in turn generating a loop filter control voltage or first charge pump voltage V p . The first charge pump voltage V p  is provided as an input to the multiple-input operational amplifier  24  (in this case, a four-input operational amplifier) at a positive input terminal. In addition, the up control signal up is provided to a positive input terminal of the multiple-input operational amplifier  24  and the down control signal dn is provided to a negative input terminal of the multiple-input operational amplifier  24 . Also, a negative feedback loop of the operational amplifier is provided between an output of the operational amplifier  24  and a negative input terminal of the operational amplifier  24 .  
         [0066]     The output of the operational amplifier  24  is applied to a second capacitor C c , and the resulting voltage across the second capacitor C c  is applied to the VCO  26  as a VCO control voltage V c  to determine the output frequency of the VCO  26 . The output signal of the VCO  26  is applied to the phase frequency detector  20  as the feedback clock signal VCLK.  
         [0067]     In this embodiment of the present invention, in combination, the first charge pump  22  and first capacitor C p  provide a pole for the feedback loop. A loop-stabilizing zero is provided by the operational amplifier  24  receiving the down control signal dn and up control signal up. The control voltage V c  for the VCO  26  is provided solely by the output of the multiple-input operational amplifier  24 . In this manner, a loop-stabilizing zero is provided without the inclusion of a resistor, which has the limitations described above in connection with the conventional embodiment. In addition, a second charge pump is not necessary in this embodiment for providing the loop-stabilizing zero, and therefore circuit size can be reduced.  
         [0068]      FIG. 3  is a detailed schematic diagram of the operational amplifier  24  of the phase locked loop of  FIG. 2 , in accordance with the present invention. The operational amplifier  24  includes a first PMOS transistor P 1 , a source of which is connected to a first voltage source Vcc, and a gate and drain of which are connected to a first node a. A second PMOS transistor P 2 , has a source that is connected to the first power source Vcc, a gate that is connected to the first node a, and a drain that is connected to a second node b. A first NMOS transistor N 1  and a second NMOS transistor N 2  are coupled in series between the first node a and a third node c, a gate of one of the first and second NMOS transistors, for example transistor N 1 , being coupled to the up control signal up and a gate of the other of the first and second NMOS transistors, for example transistor N 2 , being coupled to the first charge pump signal V p . The order of the series of the first and second NMOS transistors N 1 , N 2  can be reversed. A third NMOS transistor N 3  includes a drain that is coupled to the first node a, a gate that is coupled to the first charge pump signal V p , and a source that is coupled to the third node c. A fourth NMOS transistor N 4  and a fifth NMOS transistor N 5  are coupled in series between the second node b and the third node c, a gate of one of the fourth and fifth NMOS transistors, for example transistor N 4 , being coupled to the down control signal dn and a gate of the other of the fourth and fifth NMOS transistors, for example transistor N 5 , being coupled to the second node b. The order of the series of the fourth and fifth NMOS transistors N 4 , N 5  can be reversed. A sixth NMOS transistor N 6  includes a drain that is coupled to the second node b, a gate that is coupled to the second node b, and a source that is coupled to the third node c. A seventh NMOS transistor N 7 , has a drain that is coupled to the third node c, a source that is coupled to a ground reference voltage, and a gate of which receives a voltage bias signal V b . The voltage bias signal V b  is generated by a voltage bias generator  28 , which receives the first charge pump signal V p , and, in response to the voltage level of the first charge pump signal V p , generates the voltage bias signal V b .  
         [0069]     In this manner, the operational amplifier  24  includes a single output, namely the second node b, which provides the control voltage V c  for the VCO. The operational amplifier also includes four inputs, namely, the up control signal up and the first charge pump signal V p , which are received at positive input terminals of the operational amplifier, and the down control signal dn and the control voltage V c  for the VCO (the output signal of the operational amplifier  24 ), which are received at negative input terminals of the operational amplifier  24 .  
         [0070]     In other embodiments, such as those discussed below, the operational amplifier  24  can include additional, or fewer, positive and negative input terminals of a number that depends on the application of the phase locked loop.  
         [0071]     When the up control signal up is enabled, the output voltage of the second node b becomes larger than that of the first node a. This is because, while the up control signal up is enabled, the channel width between the first node a and the third node c becomes larger than the channel width between the second node b and the third node c, because the first NMOS transistor N 1  is activated by the active up control signal up, and the fourth NMOS transistor N 4  is deactivated because the down control signal dn is inactive during this time. Under these conditions, the offset voltage (V p −V c ) has a negative voltage value.  
         [0072]     For the opposite case, when the down control signal dn is enabled (accordingly, the up control signal up becomes disabled), the output voltage of the second node b becomes smaller than that of the first node a. This is because, while the down control signal down is enabled, the channel width between the first node a and the third node c becomes smaller than the channel width between the second node b and the third node c, because the first NMOS transistor N 1  is deactivated by the inactive up control signal up, and the fourth NMOS transistor N 4  is activated because the down control signal dn is active during this time. Under these conditions, the offset voltage (V p −V c ) has a positive voltage value.  
         [0073]     The offset voltage (V p −V c ), Vos, can be represented as Vos=(Iop/Gm)*(Δw/w), where lop is the current flowing through the seventh NMOS transistor N 7 , Gm is the conductance of the operational amplifier, W is the channel width of the N 3  and N 6  transistors of  FIG. 3 , and Δw is the channel width of the N 2  and N 5  transistors of  FIG. 3   
         [0074]     An advantage of the present first embodiment of the present invention lies in that the voltage V c  provided at the output of the operational amplifier  24  is provided solely by the operational amplifier  24  and thus, no additional charge pump is needed for this purpose.  
         [0075]      FIG. 4A  is a first timing diagram of signals of the phase locked loop of  FIG. 2 , in the case where the reference clock signal RCLK leads the feedback clock signal VCLK, in accordance with the present invention. At the rising edge of the RCLK signal, the up control signal up is activated by the phase frequency detector  20 . With activation of the up control signal up, the first charge pump  22  causes the first charge pump signal V p  to charge the first capacitor C p , and thus V p  increases at a first rate and the VCO control voltage V c  increases at a second rate that is faster than the first rate due to the negative offset voltage of the operational amplifier  24 . Following this, at the rising edge of the VCLK signal, the down control signal down is activated by the phase frequency detector  20 . With activation of the down control signal down, the first charge pump  22  causes the first charge pump signal V p  to maintain the charge of the capacitor C p , and thus V p  remains the same and the VCO control voltage V c  begins to decrease until it is approximately equal to the negative offset voltage (Vp−Vc) of the operational amplifier  24 . The overlap time of the up control signal up and the down control signal dn signal is determined by the internal delay of the phase frequency detector. The overlap time is fixed and does not vary according to the input condition.  
         [0076]     This process repeats until the feedback clock signal VCLK is aligned with, and therefore locked with, the reference clock signal RCLK.  
         [0077]      FIG. 4B  is a second timing diagram of signals of the phase locked loop of  FIG. 2 , in the case where the reference clock signal RCLK lags the feedback clock signal VCLK, in accordance with the present invention. At the rising edge of the VCLK signal, the down control signal down is activated by the phase frequency detector  20 . With activation of the down control signal down, the first charge pump  22  causes the first charge pump signal V p  to discharge the first capacitor C p , and thus V p  decreases at a first rate and the VCO control voltage V c  decreases at a second rate that is faster than the first rate due to the positive offset voltage of the operational amplifier  24 . Following this, at the rising edge of the RCLK signal, the up control signal up is activated by the phase frequency detector  20 . With activation of the up control signal up, the first charge pump  22  causes the first charge pump signal V p  to maintain the charge of the capacitor C p , and thus V p  remains the same, and the VCO control voltage V c  begins to increase until it is approximately equal to the positive offset voltage (Vp−Vc) of the operational amplifier  24 . This process repeats until the feedback clock signal VCLK is aligned with, and therefore locked with, the reference clock signal RCLK.  
         [0078]     In this manner, the direct application of the up control signal up and the down control signal dn to the operational amplifier affects the difference in effective channel widths between the first node a and third node c, and between the second node b and third node c. In the case where the up control signal up is activated, the effective channel width of the N 3  transistor is increased by activation of the N 1  transistor. Thus, a negative offset voltage is applied to the operational amplifier. In the case where the down control signal dn is activated, the effective channel width of the N 6  transistor is increased by activation of the N 4  transistor. Thus, a positive offset voltage is applied to the operational amplifier.  
         [0079]      FIG. 5  is a block diagram of a second embodiment of a phase locked loop configuration in accordance with the present invention. In this configuration, the VCO control voltage V c  is applied to a positive input terminal of a second operational amplifier  30 . The output terminal of the second operational amplifier  30  provides a third voltage Vz that is fed back to a negative input terminal of the second operational amplifier  30  to provide a negative feedback loop. The third voltage Vz is applied to an input of the VCO  26  as a control voltage for the VCO. The third voltage Vz provided in this embodiment, has reduced jitter, as compared to the control voltage V c , which leads to more stable operation in the phase locked loop. Also, the second operational amplifier  30  operates as a current buffer for the VCO control voltage V c  signal, to ensure that sufficient current is provided to the VCO  26 .  
         [0080]      FIG. 6  is a block diagram of a third embodiment of a phase locked loop configuration in accordance with the present invention. In this embodiment, the phase locked loop circuit  41  includes a phase frequency detector (PFD)  40 , a first charge pump (CP)  44 , an operational amplifier  50 , and a voltage controlled oscillator (VCO)  52 . As in the first and second embodiments of  FIGS. 2 and 5  above, the phase frequency detector  40  measures a phase difference between a received reference clock signal RCLK and a feedback clock signal VCLK. In response to the difference in phase between the clock signals, the phase frequency detector  40  generates an up control signal up and a down control signal dn, which are provided to the first charge pump  44 . The first charge pump  44 , in turn, generates a first current I 1  which is applied to a first capacitor C p  of a loop filter in response to the up control signal up and down control signal dn to charge and discharge the capacitor C p . The first charge pump voltage V p , or the voltage across the capacitor C p , is provided as an input to the multiple-input operational amplifier  50  (in this case, a five-input operational amplifier) at a positive input terminal. In addition, the up control signal up is provided directly to a positive input terminal of the multiple-input operational amplifier  50  and the down control signal dn is provided directly to a negative input terminal of the multiple-input operational amplifier  50 . Also, as in the first and second embodiments above, a negative feedback loop of the operational amplifier is provided between an output of the operational amplifier  50  at node V c  and a negative input terminal of the operational amplifier  50 .  
         [0081]     The third embodiment of  FIG. 6  further includes a pulse width filter (PWF)  42  and a second charge pump  46 . The pulse width filter  42  receives the up control signal up and down control signal dn, and, in turn, generates an auxiliary up control signal aup and an auxiliary down control signal adn. The auxiliary up control signal aup and the auxiliary down control signal adn are applied to the second charge pump  46 , which outputs second current signal I 2  which, along with the first current signal I 1  of the first charge pump  44 , is applied to the first capacitor C p  of the loop filter in response to the auxiliary up control signal aup and auxiliary down control signal adn to charge and discharge the capacitor C p  l Thus, the first combined current Ia applied to the capacitor C p  is equal to the combined output currents of the first and second charge pumps, Ia=I 1 +I 2 .  
         [0082]     The auxiliary up control signal aup and auxiliary down control signal adn are further provided to a control signal generator  48  that, in response, generates a control signal con. In one embodiment, the control signal generator  48  comprises an OR gate. The control signal con is in turn applied to both a positive input terminal and a negative input terminal of the multiple-input operational amplifier  50 . When the phase error of the input signal is large, the first combined current Ia is increased due to the large increase in the second current signal I 2 . The loop bandwidth of the PLL is also increased due to the increase in the level of the second current signal I 2 . In this case, to ensure stable operation, the zero position of the PLL should also be increased, which means that the amount of offset in the operational amplifier should be decreased. By applying the control signal con to the positive and negative input terminals of the operational amplifier  50  under these conditions, this reduces the amount of offset in the operational amplifier by increasing the effective width of the input transistors N 3 , N 6 .  
         [0083]      FIG. 7  is a detailed schematic diagram of the pulse width  4  filter (PWF)  42  of the third phase locked loop embodiment of  FIG. 6 , in accordance with the present invention. In  FIG. 7 , an exemplary pulse width filter  42  that receives the up control signal up and generates an auxiliary up control signal aup is presented. A similar circuit can be used for processing the down control signal dn to generate an auxiliary down control signal adn.  
         [0084]     In this embodiment, a third PMOS transistor P 3 , and eighth and ninth NMOS transistors N 8 , N 9  are connected serially between the voltage source Vcc and the ground reference voltage. A delay circuit DL including a plurality of inverters I 1 , I 2 , I 3 , I 4  delay the up control signal up, and apply a resulting delayed up signal dup to the gate of the ninth NMOS transistor N 9 . The up control signal up is applied to the gates of the third PMOS transistor P 3  and the eighth NMOS transistor N 8 . A signal at a node d between the third PMOS transistor P 3  and the eighth NMOS transistor N 8  is applied to a fifth inverter I 5 , the output of which is the auxiliary up control signal aup. The auxiliary up control signal aup is further applied to a sixth inverter I 6 , the output of which is an inverted auxiliary up control signal aup.  
         [0085]     The pulse width filter of  FIGS. 6 and 7  enables locking of the phase locked loop at an accelerated pace. When the up control signal is active, and has at least a predetermined pulse width, the transistors N 8  and N 9  are activated at the same time. Thus, the resulting auxiliary up control signal aup, is of a short pulse duration, the length of which is the difference in pulse length between the duration of the up control signal up less the predetermined delay length of the delay circuit DL. The delay length of the delay circuit is controlled by the number of inverters included in the delay chain. The same operation applies to generation of the auxiliary down control signal adn.  
         [0086]      FIG. 8A  is a first timing diagram of signals of the pulse width filter  42  of the third phase locked loop embodiment of  FIG. 2 , in the case where the reference clock signal leads the feedback clock signal, in accordance with the present invention. In this case, at the rising edge of the up control signal up, the delayed up control signal dup is activated following the predetermined delay of the inverter chain. At activation of the delayed up control signal dup, the up control signal up is still active, and therefore, the signal at node d is changed from a high level to a low level, and the corresponding auxiliary up control signal aup, become active at a high level. The auxiliary up control signal aup remains active until the up control signal up becomes inactive, at its falling edge.  
         [0087]      FIG. 8B  is a second timing diagram of signals of the pulse width filter  42  of the third phase locked loop embodiment of  FIG. 2 , in the case where the reference clock signal lags the output clock signal, in accordance with the present invention. In this case, the up control signal is a relatively short pulse, and does not remain active long enough to span the delay of the delay circuit DL. For this reason, the signal at node d is not changed to a low level, and accordingly, the auxiliary up control signal aup does not become active. In this case, assuming the down control signal dn is activated, the corresponding auxiliary down control signal adn becomes activated for a short pulse duration in a manner similar to the auxiliary up control signal aup of  FIG. 8A .  
         [0088]      FIGS. 9A and 9B  are detailed schematic diagrams of the first  44  and second  46  charge pumps (CP) respectively of the third phase locked loop embodiment of  FIG. 6 , in accordance with the present invention. The first charge pump  44  of  FIG. 9A  includes a first current source Ip, a fourth PMOS transistor P 4 , a tenth NMOS transistor N 10  and a second current source Ip in series between the voltage source Vcc and the ground voltage. An inverted up control signal upb is applied to a gate of the fourth PMOS transistor P 4  and the down control signal dn is applied to a gate of the tenth NMOS transistor N 10 . The signal at a node between the fourth PMOS transistor P 4  and the tenth NMOS transistor N 10  is provided as the first current I 1 . The charge pump  44  of  FIG. 9A  is applicable as the first charge pump  44  of  FIG. 6  and as the charge pump  22  of  FIG. 2  and  FIG. 5  (and as charge pump  64  of  FIG. 11 , discussed below).  
         [0089]     The second charge pump  46  of  FIG. 9B  includes a third current source (n-1)Ip, a fifth PMOS transistor P 5 , an eleventh NMOS transistor N 11  and a fourth current source (n-1)Ip in series between the voltage source Vcc and the ground voltage. An inverted auxiliary up control signal aupb is applied to a gate of the fifth PMOS transistor P 5  and the auxiliary down control signal adn is applied to a gate of the eleventh NMOS transistor N 11 . The third and fourth current sources (n-1)Ip are preferably larger in size than the first and second current sources Ip, thus the value n is greater than 2. The signal at a node between the fifth PMOS transistor P 5  and the eleventh NMOS transistor N 11  is provided as the first current I 2 . The charge pump  46  of  FIG. 9B  is applicable as the charge pump  46  of  FIG. 6  (and as the second charge pump  68  of  FIG. 11 , discussed below).  
         [0090]      FIG. 10  is a detailed schematic diagram of an embodiment of the operational amplifier  50  of the third phase locked loop embodiment of  FIG. 6 , in accordance with the present invention. The operational amplifier  50  of  FIG. 10  is similar in structure and operation to the operational amplifier  24  of  FIG. 3 , in that it includes the first and second PMOS transistors P 1 , P 2 , the first through seventh NMOS transistors N 1 , N 2 , . . . , N 7 , and the bias voltage generator  28 . In addition, the operational amplifier  50  further includes a twelfth NMOS transistor N 12  and a thirteenth NMOS transistor N 13  coupled in series between the first node a and the third node c. Also, a fourteenth NMOS transistor N 14  and a fifteenth NMOS transistor N 15  are coupled in series between the second node b and the third node c. The control signal con is applied to a gate of the twelfth NMOS transistor N 12  (i.e., a positive input terminal of the operational amplifier  50 ), and to a gate of the fourteenth NMOS transistor N 14  (i.e., a negative input terminal of the operational amplifier  50 ). The charge pump voltage V p , or the voltage across the capacitor C p , is applied to the gates of NMOS transistors N 13 , N 2  and N 3 . The output voltage V c  is applied to the gates of NMOS transistors N 15 , N 5  and N 6 .  
         [0091]     The above-described third embodiment of  FIGS. 6-10  allows for first and second modes of operation in the phase locked loop  41 . When the phase locked loop  41  is in a first mode of operation, the input clock PCLK and feedback clock VCLK signals are substantially locked and therefore have a relatively small frequency difference and relatively small phase difference. Accordingly, the up control signal up and the down control signal dn have a relatively short pulse. With short pulses in the up and down control signals up, dn, the auxiliary up and auxiliary down control signals aup, adn, are not activated, and therefore operation of the second charge pump  46  and the control signal generator  48  is disabled.  
         [0092]     When the phase locked loop  41  is however in a second mode of operation, the input clock PCLK and feedback clock VCLK signals have a relatively large frequency difference and/or relatively large phase difference. Accordingly, the up control signal up or the down control signal dn has a relatively large pulse width. With a large pulse width in the up or down control signal up, dn, the corresponding auxiliary up and auxiliary down control signal aup, adn, is activated, and therefore operation of the second charge pump  46  and the control signal generator  48  is enabled. Thus, in the second mode of operation, both first and second charge pumps  44 ,  46 , are activated. In this mode, the second current I 2  is generated by the second charge pump  46  of a value that is larger than the value of the first current I 1  (a positive value in the case of the up control signal up being generated, and a negative value in the case of the down control signal dn being generated). Thus, the first combined current Ia applied to the capacitor C p , is much larger in this case for more rapidly charging (in the case of an up control signal up being generated) or discharging (in the case of a down control signal dn being generated) the capacitor C p . Accordingly the voltage V p  changes at a greater rate, and thus the output voltage V c  changes at a greater rate. In this manner, the response time for locking the input clock PCLK and the feedback clock VCLK in the present embodiment is much improved.  
         [0093]      FIG. 11  is a block diagram of a fourth embodiment of a phase locked loop configuration in accordance with the present invention. In this embodiment, the phase locked loop circuit  61  includes a phase frequency detector (PFD)  60 , a first charge pump (CP)  64 , an operational amplifier  72 , and a voltage controlled oscillator (VCO)  74 . As in the first, second, and third embodiments of  FIGS. 2, 5 , and  6  above, the phase frequency detector  60  measures a phase difference between a received reference clock signal RCLK and a feedback clock signal VCLK. In response to the difference in phase between the clock signals, the phase frequency detector  60  generates an up control signal up and a down control signal dn, which are provided to the first charge pump  64 . The first charge pump  64 , in turn, generates a first current I 1  which is applied to a first capacitor C p  of a loop filter in response to the up control signal up and down control signal dn to charge and discharge the capacitor C p . The first charge pump voltage V p , or the voltage across the capacitor C p , is provided as an input to the operational amplifier  72  (in this case, a two-input operational amplifier) at a positive input terminal. Also, as in the first, second, and third embodiments above, a negative feedback loop of the operational amplifier is provided between an output of the operational amplifier  72  and a negative input terminal of the operational amplifier  72 .  
         [0094]     As in the third embodiment of  FIG. 6 , the fourth embodiment of  FIG. 11  further includes a pulse width filter (PWF)  62  and a second charge pump  68 . The pulse width filter  42  receives the up control signal up and down control signal dn, and, in turn, generates the auxiliary up control signal aup and the auxiliary down control signal adn, in the manner described above. The auxiliary up control signal aup and the auxiliary down control signal adn are provided to the second charge pump  68 , which provides a second current I 2  which, in combination with the first current I 1  of the first charge pump  64 , is applied as first combined current Ia to the first capacitor C p  of the loop filter in response to the auxiliary up control signal aup and auxiliary down control signal adn to charge and discharge the capacitor C p . Thus, the first combined current Ia applied to the capacitor C p  is equal to the combined output currents of the first and second charge pumps, Ia=I 1 +I 2 .  
         [0095]     The up control signal up and down control signal dn are further provided to a third charge pump  66 , which generates an output current I 3 , The up control signal up, down control signal dn, auxiliary up control signal aup and auxiliary down control signal adn are further applied to a fourth charge pump  70  which generates a fourth output current I 4 . The second combined current Ib of the third output current I 3  and fourth output current I 4  is applied to the second capacitor C c  at the output node of the operational amplifier  72 , Ib=I 3 +I 4 .  
         [0096]      FIGS. 12A and 12B  are detailed schematic diagrams of the third and fourth charge pumps  66 ,  70  respectively of the fourth phase locked loop embodiment of  FIG. 11 , in accordance with the present invention. The third charge pump  66  of  FIG. 12A  includes a fifth current source Ic/n, a sixth PMOS transistor P 6 , a sixteenth NMOS transistor N 16  and a sixth current source Ic/n in series between the voltage source Vcc and the ground voltage. An inverted up control signal uph is applied to a gate of the sixth PMOS transistor P 6  and the down control signal dn is applied to a gate of the sixteenth NMOS transistor N 16 . The signal at a node between the sixth PMOS transistor P 6  and the sixteenth NMOS transistor N 16  is provided as the third current I 3 . The current value Ic represents the sum of the output currents of the third charge pump  66  and the fourth charge pump  70  when the auxiliary up control signal aup and auxiliary down control signal adn are each deactivated. This case is discussed with reference to FIGS.  13 A_ 1  and  13 A_ 2  below. In this case Ib=Ic. The current value Ic/n represents the sum of the output currents of the third charge pump  66  and the fourth charge pump  70  when one of the auxiliary up control signal aup and auxiliary down control signal adn is activated. This case is discussed with reference to FIGS.  13 B_ 1  and  13 B_ 2  below. In this case Ib=Ic/n, because only the third charge pump  66  is activated, and not the fourth charge pump  70 .  
         [0097]     The fourth charge pump  70  of  FIG. 12B  includes a seventh current source ((n-1)/n)Ic, a seventh PMOS transistor P 7 , an eighth PMOS transistor P 8 , a seventeenth NMOS transistor N 17 , an eighteenth NMOS transistor N 18  and a eighth current source ((n-1)/n)Ic in series between the voltage source Vcc and the ground voltage. An inverted up control signal upb is applied to a gate of the seventh PMOS transistor P 7 , the auxiliary up control signal aup is applied to a gate of the eighth PMOS transistor P 8 , an inverted auxiliary down control signal adnb is applied to a gate of the seventeenth NMOS transistor N 17  and the down control signal dn is applied to a gate of the eighteenth NMOS transistor N 18 . The seventh and eighth current sources ((n-1)/n)Ic are preferably larger in size than the fifth and sixth current sources Ic/n, thus the value n is greater than 2. The signal at a node between the eighth PMOS transistor P 8  and the seventeenth NMOS transistor N 17  is provided as the fourth current I 4 .  
         [0098]     FIGS.  13 A_ 1  and  13 A_ 2  are timing diagrams of signals of the fourth phase locked loop embodiment of  FIG. 11 , illustrating the first mode of operation of the fourth embodiment, in accordance with the present invention. FIGS.  13 B_ 1  and  13 B_ 2  are additional timing diagrams of signals of the fourth phase locked loop embodiment of  FIG. 11 , illustrating the first and second modes of operation of the fourth embodiment, in accordance with the present invention.  
         [0099]     With reference to  FIG. 13A _ 1 , in a first mode of operation, the reference clock signal RCLK leads the feedback clock signal VCLK by a small amount, in accordance with the present invention. In this case, the up control signal up is a relatively short pulse, and does not remain active long enough to span the delay of the delay circuit DL of the pulse width filter  62 . For this reason, the auxiliary up control signal aup does not become active, as described above. The first combined positive current signal Ia is provided in this case solely by the first charge pump  64 , as the second charge pump  68  is inactive. The level of the first combined current signal Ia is equal to Ip. The second combined positive current signal Ib is provided in this case by the combined currents I 3 , I 4  of the third charge pump  66  and the fourth charge pump  70  which are both active. The level of the second combined current signal Ib is thus equal to Ic.  
         [0100]     With reference to  FIG. 13A _ 2 , in the first mode of operation, the reference clock signal RCLK lags the feedback clock signal VCLK by a small amount, in accordance with the present invention. In this case, the down control signal dn is a relatively short pulse, and does not remain active long enough to span the delay of the delay circuit DL of the pulse width filter  62 . For this reason, the auxiliary dn control signal adn does not become active, as described above. The first combined negative current signal Ia is provided in this case solely by the first charge pump  64 , as the second charge pump  68  is inactive. The level of the first combined current signal Ia is equal to −Ip. The second combined negative current signal Ib is provided in this case by the combined negative currents I 3 , I 4  of the third charge pump  66  and the fourth charge pump  70  which are both active. The level of the second combined current signal Ib is thus equal to −Ic.  
         [0101]     With reference to  FIG. 13B _ 1 , in a second mode of operation, the reference clock signal RCLK leads the feedback clock signal VCLK by a relatively large amount, in accordance with the present invention. In this case, the up control signal up is a relatively large pulse, and remains active for a long enough time period to span the delay of the delay circuit DL of the pulse width filter  62 . For this reason, the auxiliary up control signal aup becomes active, as described above. During a first time period T 1 , the phase locked loop  61  operates in the first mode of operation described above, because the auxiliary up control signal aup has not yet become active. During a second time period T 2 , following the first time period, the phase locked loop  61  operates in a second mode of operation, initiated by the rising edge of the auxiliary up control signal aup.  
         [0102]     Still referring to  FIG. 13B _ 1 , during the first time period T 1 , the first combined positive current signal Ia is provided solely by the first charge pump  64 , as the second charge pump  68  is initially inactive. The level of the first combined current signal Ia is equal to Ip during this time period. In addition, during the first time period T 1 , the second combined positive current signal Ib is provided by the combined currents I 3 , I 4  of the third charge pump  66  and the fourth charge pump  70  which are both active. The level of the second combined current signal Ib is thus equal to Ic during this time period.  
         [0103]     Still referring to  FIG. 13B _ 1 , during the second time period T 2 , the first combined positive current signal Ia is provided by both the first charge pump  64  and the second charge pump  68 , as the second charge pump  68  has become active. The level of the first combined current signal Ia is equal to the combination of Ip, which is the output I 1  of the first charge pump  64 , and (n-1)Ip, which is the output I 2  of the second charge pump  68  during this time period, which is a combined total current of (n)Ip. In addition, during the second time period, the second combined positive current signal Ib is provided in this case solely by current I 3  of the third charge pump  66  which is active during this time period, and not by the fourth charge pump  70 , which has become inactive during this time period. The level of the second combined current signal Ib is thus equal to Ic/n during this time period.  
         [0104]     With reference to  FIG. 13B _ 2 , in a second mode of operation, the reference clock signal RCLK lags the feedback clock signal VCLK by a relatively large amount, in accordance with the present invention. In this case, the down control signal dn is a relatively large pulse, and remains active for a long enough time period to span the delay of the delay circuit DL of the pulse width filter  62 . For this reason, the auxiliary down control signal adn becomes active, as described above. During a first time period T 1 , the phase locked loop  61  operates in the first mode of operation described above, because the auxiliary down control signal adn has not yet become active. During a second time period T 2 , following the first time period, the phase locked loop  61  operates in the second mode of operation, initiated by the rising edge of the auxiliary down control signal adn.  
         [0105]     Still referring to  FIG. 13B _ 2 , during the first time period T 1 , the first combined negative current signal Ia is provided solely by the first charge pump  64 , as the second charge pump  68  is initially inactive. The level of the first combined negative current signal Ia is equal to −Ip during this time period. In addition, during the first time period T 1 , the second combined negative current signal Ib is provided by the combined currents I 3 , I 4  of the third charge pump  66  and the fourth charge pump  70  which are both active. The level of the second combined current signal Ib is thus equal to −Ic during this time period.  
         [0106]     Still referring to  FIG. 13B _ 2 , during the second time period T 2 , the first combined negative current signal Ia is provided by both the first charge pump  64  and the second charge pump  68 , as the second charge pump  68  has become active. The level of the first combined current signal Ia is equal to the combination of −Ip, which is the output I 1  of the first charge pump  64 , and −(n-1)Ip, which is the output  12  of the second charge pump  68  during this time period, which is a combined total current of −(n)Ip. In addition, during the second time period, the second combined negative current signal Ib is provided in this case solely by current I 3  of the third charge pump  66  which is active during this time period, and not by the fourth charge pump  70 , which has become inactive during this time period. The level of the second combined current signal Ib is thus equal to −Ic/n during this time period.  
         [0107]     In this manner, during a first mode of operation of the fourth embodiment of the present invention, when the input clock RCLK and feedback clock VCLK are relatively similar in phase and frequency, and are therefore substantially locked, the second charge pump  68  is inactive, and the first, third, and fourth charge pumps  64 ,  66 ,  70  are active. Thus, the first combined current Ia is relatively small, and the second combined current Ib is relatively large.  
         [0108]     In contrast, when the input clock RCLK and feedback clock are dissimilar in phase and frequency, the auxiliary up/down control signals are activated, for a time period during which the phase locked loop enters a second mode of operation. When operating in the second mode, the first, second and third charge pumps  64 ,  68 ,  66 , are active, and the fourth charge pump  70  is inactive. Thus, in the second mode, the first combined current Ia is relatively large, and the second combined current Ib is relatively small.  
         [0109]     In this manner, the offset voltage of the operational amplifier  72  is controlled by application of the second combined current signal Ib. This has a similar affect on the operation of the operational amplifier to that of the con signal applied in the  FIG. 6  embodiment above.  
         [0110]      FIG. 14  is a waveform diagram, illustrating the step response of the third phase locked loop embodiment of  FIG. 6 , in accordance with the present invention, as compared to the response of the conventional apparatus. It can be seen in this diagram that locking is achieved in the response of the present invention  91  at a faster rate than that of the conventional embodiment  93 . In addition, once locking is achieved, a steady state of operation is achieved at a faster rate by the embodiment of the present invention.  
         [0111]     The present invention is applicable to integrated circuits of all types, including memory devices and memory systems. In a memory device embodiment, the memory device includes a plurality of addressable memory cells, each cell comprising a data storage element. A decoder receives an address from an external source, and that generates a row signal and a column signal for accessing at least one of the addressable memory cells. A phase locked loop configured in accordance with embodiments of the present invention can be provided on the memory device for receiving signals that are transmitted from external, off-chip sources.  
         [0112]      FIG. 15  is a block diagram of a memory system in accordance with the present invention. The memory system includes a memory controller  100  that generates command (COM) and address signals (BA (bank address) and ADD) and a memory module  300 . The memory module  300  comprises a plurality of memory devices  300 - 1 ,  300 - 2 , . . . ,  300 - n,  and receives the command (COM) and address signals (BA, ADD). In response, the memory module  300  stores and retrieves data (Din/Dout) to and from the memory devices  300 - 1 ,  300 - 2 , . . . ,  300 - n.  A phase locked loop in accordance with the present invention can be provided on the memory devices for receiving signals that are transmitted from external, off-chip sources.  
         [0113]     While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.