Abstract:
Analog multiplexer circuits with CMOS control signals and with low signal feed-through and high bandwidth are described. These circuits emphasize low parasitic capacitance through circuit layout techniques and the use of smaller size n-channel transistors where possible. These circuits can be used for both single-ended and differential configurations. Two embodiments of the circuit are discussed allowing for optimal selection of multiplexers in application requirements ranging from lower-to-higher bandwidth and small-to-large input signal size.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     This invention relates to fast analog multiplexers with CMOS control signals and particularly to the elimination of cross-signal feed-through in these high speed circuits.  
         [0003]     2. Brief Description of the Known Art  
         [0004]      FIG. 1   a  shows the simplest type of conventional analog multiplexer  1  (MUX) built with CMOS switches. Here, the MUX switches are comprised of n-channel MOS transistors  2 - 4  and p-channel MOS transistors  5 - 7 , connected in parallel to form a CMOS switch. This shows a n-to-1 MUX with input signals sig 1 , sig 2 , . . . sig n connected to MUX switches  2 / 5 ,  3 / 6 , and  4 / 7 , respectively. The output of the MUX switches are connected together and become the output of the MUX circuit. The MUX switches are controlled by placing complementary control voltages on the transistor gates, as shown. The logic circuit for generating these control signals is comprised of two inverters  8  and  9 , as shown in  FIG. 1   b . As example, for operation between 0 volts and positive power supply VDD, the switches are turned “ON” and “OFF” at their gates, as follows:  
                                                                 n-Channel   p-Channel           Transistor   Transistor                                    ON   V DD     0 V       OFF   0 V   V DD                             where V DD  is the positive power supply (e.g. +5V) and 0V is ground. 
 
 By having the n-channel and p-channel transistors connected in parallel, the circuit can handle signals from 0 to V DD  volts, as illustrated in  FIG. 1   c . In this figure, V sig  is plotted on the abscissa and the ON resistance of the switches, R SW , is plotted on the ordinate. The transistors tend to be “ON” over the following voltage ranges, respectively: 
    n-channel: 0→[V DD −V th     (n-ch)   ]    p-channel V DD →[0+V th     (p-ch)   ]
 
 This means that for small signals the n-channel transistor is primarily used and for large signals the p-channel transistor is primarily used. Also, the ON resistance, R SW , tends to be optimal (lowest) in mid-signal range where both parallel transistors are ON. 
         
         [0008]     The primary problem with analog multiplexers of this type, used to select one of several input signals, is that they often have undesirable signal feed-through where an attenuated level of an unselected signal appears as part of the output signal. This feed-through is due primarily to the parasitic capacitances, C gd  and C gs , associated with the CMOS transistors used to implement the switches. As a result, this undesirable feed-through causes a degradation at the output of both the signal-to-noise ratio (SNR) and the signal-to-distortion ratio (SDR) for the selected signal at the output of the MUX.  
         [0009]     Thus, there is a need for an improved high speed MUX which eliminates the cross-signal feed-through problems of the prior art. The invention and embodiment disclosed herein address this need.  
         [0010]     For reference, U.S. Pat. Nos. 5,744,995 discusses multi-input multiplexers and U.S. Pat. No. 5,598,114 discusses high-speed multiplexers.  
       SUMMARY OF THE INVENTION  
       [0011]     This invention addresses the shortcomings of prior art analog multiplexers, depending on the application, to provide low-distortion, high-speed solutions. The objective is to provide high-speed multiplexers which eliminates cross-signal feed-through at the circuit&#39;s output. These designs take into account such parameters as input signal level, signal bandwidth, common mode operation, parasitic capacitance, and transistor layout.  
         [0012]     The circuits of this invention use N-MOS/P-MOS transistor pairs for signal switches and additional N_MOS transistors to effectively shunt the unselected signal paths to circuit ground, thereby considerably reducing the amount of undesired signal presence at the circuit&#39;s output.  
         [0013]     Two embodiments of the invention address the signal feed-through issue with CMOS circuitry; one for limited bandwidth applications and one for small signal applications. For small signal applications, the P-MOS transistors in the signal switches of these circuits are eliminated, leaving only the N-MOS transistors, to provide improved bandwidth and lower signal feed-through. All of the techniques of this invention can be applied to both single-ended and/or differential configurations.  
         [0014]     Also, the layout of CMOS transistors with reduced parasitic capacitance, used in the implementation of the circuits of this invention, are included in the discussion.  
     
    
     BRIEF DISCRIPTION OF THE DRAWINGS  
       [0015]     The included drawings are as follows:  
         [0016]      FIG. 1   a  shows a schematic for a simple analog MUX with CMOS control. (prior art)  
         [0017]      FIG. 1   b  shows a typical schematic of the control logic for an analog MUX. (prior art)  
         [0018]      FIG. 1   c  illustrates the switching characteristics for the n-channel and p-channel transistors commonly used in the analog MUX circuitry. (prior art)  
         [0019]      FIG. 2  shows the schematic for a CMOS MUX of this invention with improved input signal feed-through.  
         [0020]      FIG. 3  shows the schematic for a small-signal, high-bandwidth, single-ended CMOS MUX of this invention with improved input signal feed-through.  
         [0021]      FIG. 4  shows the schematic for a small-signal, high-bandwidth, differential CMOS MUX of this invention with improved input signal feed-through.  
         [0022]      FIGS. 5   a  and  5   b  illustrate the layout of the CMOS transistors of this invention with reduced parasitic output capacitance for use in analog multiplexer applications.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0023]      FIG. 2  shows one embodiment for a CMOS MUX  10  with improved signal feed-through characteristics. The circuit is comprised of an input pair of n-channel  11 - 13 /p-channel  17 - 19  MOS transistor switches and an output pair of n-channel  14 - 16 /p-channel  20 - 22  MOS transistor switches connected in series at each input and additional n-channel MOS transistors  23 - 25  connected, as pull-down devices, between each series transistor pair and circuit ground. Input signals Sig 1 , Sig 2 , and Sig n  are connected to transistors pairs  11 / 17 ,  12 / 18 , and  13 / 19 , respectively. The outputs of MOS transistor pairs  14 / 20 ,  15 / 21 , and  16 / 22  are tied together to form a low feed-through output signal. Each of the series n-channel MOS transistors  11 - 16  are driven at the gate by logic control signals, S n , while the series p-channel MOS transistors  17 - 22  and n-channel MOS pull-down transistors  23 - 25  are driven by logic control signals, {overscore (S n )}, which are complementary to the above  11 - 16 . As a result, the overall effect of this circuit arrangement is as though there were individual switches, with low signal feed-through, for each input signal.  
         [0024]     In operation, when one signal is selected, all other signals are shunted to ground by their associated pull-down transistors, such that feed-through from the unselected signals is eliminated at the output. For example, if Sig 2  is selected, then MOS pull-down transistor switch  24  is OFF, allowing the Sig 2  signal to pass through to the output while MOS pull-down transistors  23  and  25  are ON, shunting any feed-through from signals Sig 1  and Sig n  to ground and preventing any feed-through of these unselected signals at the output. Either the n-channel or p-channel MOS transistor can be selected as the ON switch, depending on the level of the input signal.  
         [0025]     This circuit is limited to rather low bandwidth applications due to the total RC time constant associated with each switch. For example, switch SW 1   x    11 / 17  has an ON resistance of R 1X  and a total parasitic capacitance C 1X  at node N 1  and switch SW 1   y    14 / 20  has an ON resistance of R 1Y  and a total parasitic capacitance C 1Y  at the output node. Therefore, the total RC time constant for Sig 1  is given as: 
 
R 1X ·C 1X +R 1Y ·C 1Y  
 
 For a given switch control level and common mode signal, the switch ON resistance can be reduced by increasing the widths of both the N-MOS and P-MOS transistors. However, this reduction in ON resistance is typically accompanied by an increase in the drain-to-bulk and source-to-bulk parasitic capacitance. But, an optimum design can be found for a limited number of signals that are joined together at the MUX output for a given application. 
 
         [0026]     In a second embodiment of the circuit  26 , for the case of small signal applications where the input signal is a small fraction of the MUX supply voltage, the switch bandwidth can be improved by modifying the circuit as shown in  FIG. 3 . Since the mobility of electrons is approximately three times greater than that for holes, the problem with the ON switch resistance discussed above is magnified by the fact that P-MOS device sizes must be made three times or more the size of the N-MOS devices to overcome this mobility difference. However, this larger size for the P-MOS devices results in larger parasitic capacitance which in turn increases the RC time constant and reduces the switch bandwidth. In this circuit, used primarily for small signal applications, the p-channel MOS transistors  17 - 22  (in  FIG. 2 ) are eliminated completely so that the series switches consists of only n-channel MOS transistor switches  11 - 16  and the n-channel MOS shunting transistors  23 - 25 . Otherwise, the circuit configuration is the same as in  FIG. 2 . In this circuit the parasitic capacitance is reduced by as much as 50%, assuming the signal common mode level is closer to the MUX ground and the peak-to-peak signal level is a small fraction of the MUX supply voltage. This configuration is applicable as long as the signal voltage level (V cm +V sig ) produces enough V gs  for the series N-MOS transistors  11 - 16  to maintain a low ON resistance.  
         [0027]     The circuits discussed above are shown for single-ended signal applications. However, all these circuits can be implemented for fully differential operation, as illustrated in  FIG. 4  for the small signal circuit discussed above. This circuit is essentially comprised of two of the single-ended circuits  26  coupled so as to provide for differential inputs signals Sig 1 +/Sig 1 −, Sig 2 +/Sig 2 −, Sig n +/Sig n − and a differential output signal Sig 0 +/Sig 0 −.  
         [0028]     The parasitic capacitance in these high-speed MUX circuits can be further reduced by using an even number of “fingers” in the circuit layout of the series output transistors SW 1   y    14 , SW 2   y    15 , SWny  16 , as illustrated in  FIGS. 5   a  and  5   b .  FIG. 5   a  shows a typical layout for a single finger N-MOS transistor which is comprised of a source  27 , a gate  28 , and a drain  29 . In this case the source and drain capacitances are equal and given as the area of the gate width (w) and drain/source length (x), as follows: 
 
 C   S   =C   D   =x·w  
 
 On the other hand, for the lower capacitance layout of this invention, shown in  FIG. 5   b , the gate and source are split into two parts, or “fingers”, so that the transistor is comprised of sources  30  and  31 , gates  32  and  33 , and drain  34 , and the capacitance-to-area relationship becomes:  
                 C   D     =       ⁢     x   ·     w   2         ,           ⁢   and                   C   S     =       ⁢       2   ·   x   ·     w   2       =     x   ·   w         ,             ⁢             ⁢     so   ⁢           ⁢   that                   C   S     =       ⁢     2   ·       C   D     .                 
 
 This means that a two “finger” device has a drain-to-bulk parasitic capacitance, C dB , that is one-half the source capacitance, C S , and as a result the total output capacitance is reduced by at least 50%. This layout can be used to obtain a significant boost, where the bandwidth of the MUX circuit is at least doubled. 
 
         [0029]     While the invention has been described in the context of two preferred embodiments, it will appear to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.