Abstract:
A low-cost high-speed programmable rasterizer accepting an input set of functionals representing a triangle, clipping planes and a scissoring box, and producing multiple spans per clock cycle as output. A Loader converts the input set from a general form to a special case form accepted by a set of Edge Generators, the restricted input format accepted by the Edge Generators contributing to their efficient hardware implementation.

Description:
BACKGROUND 
   1. Field 
   Invention relates generally to rasterizers and, more particularly, to accelerating the conversion of primitives defined by vertexes to equivalent images composed of pixel patterns that can be stored and manipulated as sets of bits. 
   2. Related Art 
   Raster displays are commonly used in computer graphics systems. These displays store graphics images as a matrix of the smallest picture elements that can be displayed on a screen (“pixels”) with data representing each pixel being stored in a display buffer. This data specifies the display attributes for each pixel on the screen such as the intensity and color of the pixel. An entire image is read from the display buffer and displayed on the screen by sequentially scanning out horizontal rows of pixel data or “scan lines.” 
   Raster display systems commonly use polygons as basic building blocks or “primitives” for drawing more complex images. Triangles are a common basic primitive for polygon drawing systems, since a triangle is the simplest polygon and more complex polygons can be represented as sets of triangles. The process of drawing triangles and other geometric primitives on the screen is known as “rasterization.” 
   An important part of rasterization involves determining which pixels fall within a given triangle. Rasterization systems generally step from pixel to pixel in various ways and determine whether or not to “render,” i.e. to draw into a frame buffer or pixel map, each pixel as part of the triangle. This, in turn, determines how to set the data in the display buffer representing each pixel. Various traversal algorithms have been developed for moving from pixel to pixel in a way such that all pixels within the triangle are covered. 
   Rasterization systems sometimes represent a triangle as a set of three edge-functions. An edge function is a line equation representing a straight line, which serves to subdivide a two-dimensional plane. Edge functions classify each point within the plane as falling into one of three regions: the region “inside” of the triangle, the region “outside” of the triangle or the region representing the line itself. The type of edge function that will be discussed has the property that points “inside” of the triangle have a value greater than zero, points “outside” have a value less than zero, and points exactly on the line have a value of zero. This is shown in  FIG. 1   a . Applied to rasterization systems, the two-dimensional plane is represented by the graphics screen, points are represented by individual pixels, and the edge function serves to subdivide the graphics screen. 
   The union of three edges, or more particularly three half-planes, each of which is specified by edge functions, create triangles. It is possible to define more complex polygons by using Boolean combinations of more than three edges. Since the rasterization of triangles involves determining which pixels to render, a tiebreaker rule is generally applied to pixels that lie exactly on any of the edges to determine whether the pixels are to be considered interior or exterior to the triangle. 
   As shown in  FIG. 1   b , each pixel has associated with it a set of edge variables (e 0 , e 1  and e 2 ) which are proportional to the signed distance between the pixel and the three respective edges. The value of each edge variable is determined for a given triangle by evaluating the three edge functions, f 0 (x,y), f 1 (x,y) and f 2 (x,y) for the pixel location. It is important to note that it can be determined whether or not a pixel falls within a triangle by looking at only the signs of e 0 , e 1  and e 2 . 
   In determining which pixels to render within a triangle, typical rasterization systems compute the values of the edge variables (e 0 , e 1  and e 2 ) for a given set of three edge functions and a given pixel position, and then use a set of increment values (Δe outside , Δe inside , etc.) to determine the edge variable values for adjacent pixels. The rasterization system traverses the triangle, adding the increment values to the current values as a traversal algorithm steps from pixel to pixel. 
   With reference again to  FIG. 1   a , a line is illustrated that is defined by two points: (X,Y) and (X+dX, Y+dY). As noted above, this line can be used to divide the two dimensional space into three regions: all points “outside” of, “inside” of, and exactly on the line. The edge f(x,y) can be defined as f(x,y)=(x−X)dY−(y−Y)dX. This function has the useful property that its value is related to the position of the point (x,y) relative to the edge defined by the points (X,Y) and (X+dX, Y+dY): 
   f(x,y)&gt;0 if (x,y) is “inside”; 
   f(x,y)=0 if (x,y) is exactly on the line; and 
   f(x,y)&lt;0 if (x,y) is “outside”. 
   Existing rasterization systems commonly use this function, since it can be computed incrementally by simple addition: f(x+1,y)=f(x,y)+dY and f(x,y+1)=f(x,y)−dX. 
   A variety of different traversal algorithms are presently used by different rasterization systems in the rendering process. Any algorithm guaranteed to cover all of the pixels within the triangle can be used. For example, some solutions involve following the sides of the triangle while identifying a horizontal or vertical span of pixels therein. Following the sides of the triangle is adequate for the triangle edges, but if the triangle is clipped by a near or far plane, these boundaries are not known explicitly and cannot be followed as easily as the triangle edges. Other methods test individual pixels one at a time. In the recent past multiple pixels are tested in parallel to speed up the rasterization process. 
   Some conventional rasterizers use span-based pixel generation and contain edge and span interpolators based on the well-known Bresenham algorithm. The speed of those rasterizers depends on the interpolation speed. Furthermore, they require a complicated setup process. In most cases such rasterizers interpolate many associated parameters such as color, texture, etc. with appropriate hardware. Increasing the speed of such rasterizers requires a significant increase in the number and complexity of the interpolators, an approach not suitable for commercial products. In the case of clipping support, the structure of such rasterizers is too complex for efficient implementation. 
   Another approach is to use area rasterizers based on a definition of inner and outer pixels, grouped into blocks, with checking corner pixels&#39; equation values to define inner, border and outer blocks. This approach may accelerate the generation of bit-masks of inner blocks, but the border blocks either need to be processed pixel by pixel or need a significant amount of dedicated hardware for processing those pixels in parallel. 
   Accordingly, there is a need for a low-cost high-speed rasterizer having a simple and uniform structure and capable of generating multiple spans per clock cycle. 
   SUMMARY 
   Invention describes a low-cost high-speed programmable rasterizer. The rasterizer accepts as input a set of functionals representing a triangle, clipping planes and a scissoring box, and produces multiple spans per clock cycle as output. A Loader converts the input set, as expressed in one of a number of general forms, to an expression conforming to a special case format as accepted by a set of Edge Generators. The restricted input format accepted by the Edge Generators contributes to their efficient hardware implementation. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1   a  is a diagram illustrating a half-plane, according to an embodiment of the present invention. 
       FIG. 1   b  is a diagram illustrating a triangle defined by three half-planes, according to an embodiment of the present invention. 
       FIG. 1   c  is a diagram illustrating a polygon defined by a set of half-planes, according to an embodiment of the present invention. 
       FIG. 1   d  is a diagram illustrating an opened half-plane and a closed half-plane, according to an embodiment of the present invention. 
       FIG. 2  is a diagram illustrating normals in quadrants and the definition of “right” and “left” half-planes, according to an embodiment of the present invention. 
       FIG. 3  is a diagram illustrating a wire-frame triangle, according to an embodiment of the present invention. 
       FIG. 4  is a flow diagram illustrating a method for the moving-down process in preparation the Bresenham setup, according to an embodiment of the present invention. 
       FIG. 5  is a flow diagram illustrating the foregoing method for the Bresenham setup process, according to an embodiment of the present invention. 
       FIG. 6  is a flow diagram illustrating a method for the Bresenham walk process, according to an embodiment of the present invention. 
       FIG. 7  is a block diagram illustrating a Span Generator, according to an embodiment of the present invention. 
       FIG. 8  is a block diagram illustrating a Loader (without shifters), according to an embodiment of the present invention. 
       FIG. 9  is a block diagram illustrating {tilde over (b)} and {tilde over (c)} values wrapping before they are loaded into an Edge Generator, according to an embodiment of the present invention. 
       FIG. 10   a  is a block diagram illustrating an Edge Generator, according to an embodiment of the present invention. 
       FIG. 10   b  is a block diagram illustrating an Edge Generator during the moving-down phase, according to an embodiment of the present invention. 
       FIG. 10   c  is a block diagram illustrating an Edge Generator during the Bresenham setup phase, according to an embodiment of the present invention. 
       FIG. 11   a  is a block diagram illustrating a Scissoring Box origin, according to an embodiment of the present invention. 
       FIG. 11   b  is a block diagram illustrating a Scissoring Box, according to an embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   The following servers as a glossary of terms as defined herein: 
   
       
       Triangle Intersection of three half-planes, wherein each half-plane is “open” or “closed”. 
       Polygon Intersection of a triangle and the clipping half-planes (shown in  FIG. 1   c ), wherein each clipping half-plane is “open” or “closed”. 
       “Open” half-plane A half-plane which satisfies the inequality (as shown in  FIG. 1   d )
 
 a·x+b·y+c&gt; 0  (1)
 
       “Closed” half-plane A half-plane which satisfies the inequality (as shown in  FIG. 1   d )
 
 a·x+b·y+c≧ 0  (2)
 
       Half-plane functional An expression describing a half-plane or a line
 
 f ( x, y )= a·x+b·y+c   (3)
 
       “Right” half-plane A half-plane described by a functional
 
 f ( x, y )= a·x+b·y+c , where a&lt;0         a=0         b&lt;0  (4)
 
       “Left” half-plane A half-plane described by a functional
 
 f ( x, y )= a·x+b·y+c , where a&gt;0         a=0         b&gt;0  (5)
 
       Scissoring box A rectangle representing a part of the view-port where polygon are actually drawn. 
       Bounding box A smallest rectangle to fit the intersection of a triangle and the scissoring box 
       Extended bounding box A bounding box, which horizontal size is the smallest power of 2, which is greater or equal to the size of the bounding box 
       w The horizontal size of the bounding box
 
 w=x   max   −x   min   (6)
 
       W The horizontal size of the extended bounding box, for which it could be expressed as:
 
W=2 ceiling (log     2      w)   (7)
 
       x Representation of the integer horizontal coordinate inside the bounding box expressed in current grid units 
       y Representation of the integer vertical coordinate inside the bounding box expressed in current grid units 
       x min  Representation of the minimal horizontal coordinate of the bounding box 
       y min  Representation of the minimal vertical coordinate of the bounding box 
       a, b, c Integer coefficients of the functional of the half-plane 
       ã, {tilde over (b)}, {tilde over (c)} Integer coefficients of the functional transformed to the bounding box relative coordinates according to the special case of the edge functional 
       “Edge” of a “left” half-plane The set of points (x i , y i ) satisfying the expression 
     
  
   
     
       
         
           
             
               
                 
                   
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       “Left” edge “Edge” of a “left” half-plane 
       “Edge” of a “right” half-plane The set of points (x i , y i ) satisfying the expression 
     
  
   
     
       
         
           
             
               
                 
                   
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       “Right” edge “Edge” of a “right” half-plane 
       “Edge” of a half-plane If the half-plane is a “right” half-plane, then the “edge” of the “right” half-plane, otherwise the “edge” of the “left” half-plane 
       “Edge” of a polygon “Edge” of one of the half-planes forming the polygon 
       Wire-frame A disjunction of three parallelograms based on the three edges of the triangle 
       “Width” of a wire-frame Integer number, which expresses in the current grid units projection of the width of the wire-frame line to a minor direction axis of the current grid. 
       d The width of the wire-frame line 
       Edge Generator EG State machine to generate an edge of a half-plane, which computes a sequence of x coordinate values in order of incrementing y coordinate associated with one of the functionals 
       Loader Pipelined device to transform input functionals to the form, which is convenient for EG to work 
       Sorter Pipelined device to compute the intersection of half-planes, edges of which are generated by several EG 
       Span buffer Temporary storage for spans before tiling 
       Tiling Process of making tiles 
       Tile Set of 8×8 pixels, aligned by x and y coordinates 
       Tile Generator TG State machine to produce tiles from spans in Span Buffer 
       Moving Down Phase of the EG when EG is adding {tilde over (b)} value to the functional value each clock until the functional value is positive 
       SHORT Data type to define signed 22-bit numbers 
       LONG Data type to define signed 42-bit numbers 
       BITN Data type to define unsigned N-bit numbers 
       BITNS Data type to define signed N-bit numbers
 
Triangle Edge Definition
 
We assume that triangle edge functions are defined as
 
     
  
                       F   i     ⁡     (     x   ,   y     )       =           a   i     ·   x     +       b   i     ·   y     +     c   i       =     det   ⁢           ⁢     (           x   j           x   k         x             y   j           y   k         y           1       1       1         )           ,     i   =   0     ,   1   ,   2           (   12   )               
wherein j=(i+1) mod 3, k=(i+2) mod 3 and [x i , y i ], i=0, 1, 2 are triangle vertex coordinates in a standard window coordinate system expressed in the units of the main grid (see above). If the functionals are set up as “implicit” clipping functionals, they should be converted to this format as well.
 
End Points
 
For a right edge and a given span y i  the interpolator should produce x i  such that
 
                   x   i     =       max     x   ∈   Z       ⁢     {     x   :         a   ·   x     +     b   ·     y   i       +   c     &gt;   0       }               (   13   )               
such an x i  point for a≠0 is the last (inclusive) point of the span.
 
For a left edge and a given span y i  the interpolator should produce x i  such that
 
                   x   i     =       min     x   ∈   Z       ⁢     {     x   :         a   ·   x     +     b   ·     y   i       +   c     ≥   0       }               (   14   )               
such an x i  point for a≠0 is the first (inclusive) point of the span.
 
If we have a=0 then the edge (left or right) is horizontal, thus the end points of the span for the functional will be x 0 =0 and x 0 =W.
 
General Cases for the Edge Generator
 
In general case we have opened right half-planes and closed left half-planes, classified as follows, also shown in  FIG. 2 :
 
                                                   Normal               Case #   Half-plane   quadrant   A   B                   1   Right open   II   &lt;0   ≧0       2   Right open   III   &lt;0   &lt;0       3   Right open   III   =0   &lt;0       4   Left closed   IV   &gt;0   ≦0       5   Left closed   I   &gt;0   &gt;0       6   Left closed   I   =0   &gt;0       7   Whole   n/a   =0   =0           bounding           box is           inside or           outside the           plane                    
A Loader  102  transforms a functional given according to a general case into a functional given by the special case, with the special case and the general cases described as follows:
 
Special Case for the Edge Generator
 
The Edge Generator  103  (shown in  FIG. 7 ) operates within a discrete space with integer coefficients. To simplify the work of the Edge Generator  103 , the Edge Generator  103  is designed to draw an edge of a closed right half-plane (i.e. a right edge), whose normal is located in quadrant II since we have a&lt;0 and b≧0. For an edge with a&lt;0 we have:
 
                   f   ⁡     (     x   ,   y     )       =         a   ·   x     +     b   ·   y     +   c     =       0   ⁢           ⇒           ⁢   x     =         -     b   a       ·   y     -     c   a                   (   15   )               
from which we calculate
 
   
     
       
         
           
             
               
                 
                   
                     
                       
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                       ⁢ 
                       
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                         ⁢ 
                         
                             
                         
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                 ( 
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   The Edge Generator  103  works in a vertical stripe [x min , x max ] using an x coordinate relative to x min  which satisfies 0≦x≦W, wherein W=2 m  is the size of the extended bounding box. As described below, the setup division starts as soon as the functional changes sign from negative to positive and f(0, y)≧0, hence resulting in x 0 ≧0. Also, Δx≧0 according to the above assumption that a&lt;0 and b≧0. 
   It is possible that the value of the functional ƒ is negative when the Edge Generator  103  starts operating (i.e. when y=0). In this case, the x 0  value could be negative and hence does not need to be computed, since we are only interested in the exact x 0  values which satisfy 0≦x 0 ≦W. 
   The completion of the moving-down process is followed by calculating x 0 =floor(−c/a) and Δx=floor(−b/a) using a division process performed by the divider. Since the divider starts operating when the functional value changes its sign from negative to positive, we can assume that at the start of the division process ƒ(0, y)≧0. To calculate x 0  and Δx the divider operates under the assumption that
 
a&lt;0, b≧0  (17)
 
and uses a simple adder-based divider. Since a&lt;0, we take
 
 c   i −(− a   i )≡ c   i   +a   i  
 
 b   i −(− a   i )≡ b   i   +a   i   (18)
 
into consideration start with
 
 c   0   =f ( x, y ),  a   0   =ã ·2 m+1   , b   0   ={tilde over (b)}, x   00   =Δx   0 =0  (19)
 
and then iterate as follows:
 
                         c     i   +   1       =       c   i     +     {             a   i     ,         c   i     +     a   i       ≥   0                 0   ,         c   i     +     a   i       &lt;   0                               x       0   ⁢   i     +   1       =         x     0   ⁢   i       ·   2     +     {           1   ,         c   i     +     a   i       ≥   0                 0   ,         c   i     +     a   i       &lt;   0                               b     i   +   1       =       b   i     +     {               a   i     ,         b   i     +     a   i       ≥   0                 0   ,         b   i     +     a   i       &lt;   0             ,     i   =   0     ,   1   ,   …   ⁢           ,   m                       Δ   ⁢           ⁢     x     i   +   1         =       Δ   ⁢           ⁢       x   i     ·   2       +     {           1   ,         b   i     +     a   i       ≥   0                 0   ,         b   i     +     a   i       &lt;   0                               a     i   +   1       =       a   i     2                   (   20   )               
describing the fully functional step-by-step integer divider.
 
Case 1: Right Open Half-plane and A&lt;0           B≧0
 
The difference between this case and the special case is only that the half-plane is open.
 
Therefore we need to find

                   x   0     =       max     x   ∈   Z       ⁢     {     x   :         a   ·   x     +     b   ·   y     +   c     &gt;   0       }               (   21   )               
Since the coefficients and variables are integer,
 
                   x   0     =       max     x   ∈   Z       ⁢     {     x   :         a   ·   x     +     b   ·   y     +   c   -   1     ⁢           ≥   0       }               (   22   )               
and therefore
 
                     x   0     =       max     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢     a   ·   x       +     b   ·   y     +     c   ~       ≥   0     }         ,       c   ~     =     c   -   1               (   23   )               
which reduces this case to the special case. Thus, in this case the Loader  102  (shown in  FIG. 7 ) subtracts 1 from c before starting the Edge Generator  103 .
 
Case 2: Right Open Half-plane and A&lt;0           B&lt;0
 
Again we need to find

                   x   0     =       max     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢     a   ·   x       +     b   ·   y     +   c     &gt;   0     }               (   24   )               
Substituting x=W−{tilde over (x)} we have
 
                   x   0     =     W   -       min       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :       -     a   ·     x   ~       +     b   ·   y     +   c   +     W   ·   a       &gt;   0     }                 (   25   )               
and computing maximum in the complimentary semi-plane
 
                   x   0     =     W   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :       -     a   ·     x   ~       +     b   ·   y     +   c   +     W   ·   a       ≤   0     }       -   1             (   26   )               
and rewriting the constraint and collecting appropriate terms we have
 
                   x   0     =     W   -   1   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :     ⁢     a   ·     x   ~         -     b   ·   y     -   c   -     W   ·   a       ≥   0     }                 (   27   )               
and finally
 
                   x   0     =     W   -   1   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :     ⁢       a   ~     ·     x   ~         +       b   ~     ·   y     +     c   ~       ≥   0     }                 (   28   )               
where
   ã=a, {tilde over (b)}=−b, {tilde over (c)}=−c−W·a   (29) 
which reduces this case to the special case.
 
Case 3: Right Open Half-plane and A=0           B&lt;0
 
Whereas in the previous case for a&lt;0         b&lt;0 we had

                   x   0     =     W   -   1   -       max       x     ~   ~       ∈   Z       ⁢     {           x   ~     ⁢     :     ⁢       a   ~     ·     x   ~         +       b   ~     ·   y     +     c   ~       ≥   0     }                 (   30   )               
wherein
   ã=a, {tilde over (b)}=−b, {tilde over (c)}=−c−W·a   (31) 
In this case we have a=0, which means that (30) does not have a maximum. However the division algorithm described above (16) is stable in the case of a zero denominator, producing in this case
   {tilde over (x)}   0 =2 ·W −1             x   0   =W −1 −{tilde over (x)}   0   =−W   (32) 
after the completion of the division algorithm, indicating that the x value reaches the other edge of the bounding box and that the Edge Generator  103  will draw a horizontal line.
 
Case 4: Left Closed Half-plane and A&gt;0         B≦0
 
Again we want to find

                   x   0     =       min     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢     a   ·   x       +     b   ·   y     +   c     ≥   0     }               (   33   )               
or equivalently
 
                   x   0     =       min     x   ∈   Z       ⁢     {         x   ⁢     :       -     a   ·   x     -     b   ·   y     -   c     ≤   0     }               (   34   )               
Substituting a=−ã, b=−{tilde over (b)} and computing the maximum in the complimentary semi-plane, we have
 
                   x   0     =         max     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢       a   ~     ·   x       +       b   ~     ·   y     -   c     &gt;   0     }       +   1             (   35   )               
Since the coefficients and variables are integer, we have
 
                   x   0     =         max     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢       a   ~     ·   x       +       b   ~     ·   y     -   c   -   1     ≥   0     }       +   1             (   36   )               
and therefore
 
                   x   0     =         max     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢       a   ~     ·   x       +       b   ~     ·   y     +     c   ~       ≥   0     }       +   1             (   37   )               
wherein
   ã=−a, {tilde over (b)}=−b, {tilde over (c)}=−c− 1  (38) 
reducing to the special case.
 
Case 5: Left Closed Half-plane and A&gt;0           B&gt;0
 
We want to find

                   x   0     =       min     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢     a   ·   x       +     b   ·   y     +   c     ≥   0     }               (   39   )               
Substituting x=W−{tilde over (x)} we have
 
                   x   0     =     W   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :       -     a   ·     x   ~       +     b   ·   y     +   c   +     W   ·   a       ≥   0     }                 (   40   )               
and therefore
 
                   x   0     =     W   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :     ⁢       a   ~     ·     x   ~         +       b   ~     ·   y     +     c   ~       ≥   0     }                 (   41   )               
wherein
   ã=−a, {tilde over (b)}=b, {tilde over (c)}=c+W·a   (42) 
reducing to the special case.
 
Case 6: Left Closed Half-plane and A=0           B&gt;0
 
In the previous case for a&gt;0         b&gt;0 we had

                   x   0     =     W   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :     ⁢       a   ~     ·     x   ~         +       b   ~     ·   y     +     c   ~       ≥   0     }                 (   43   )               
wherein
   ã=−a, {tilde over (b)}=b, ã=c+W·a   (44) 
In this case we have a=0 resulting in (43) having no maximum. However, the division algorithm described above (16) is again stable in this case of zero denominator, resulting in
   {tilde over (x)}   0 =2 ·W −1             x   0   =W −1 −{tilde over (x)}   0 =0  (45) 
after the division algorithm completes, indicating that the x value reaches the other edge of the bounding box and that the Edge Generator  103  will draw a horizontal line.
 
Case 7: The Plane of the Polygon is Parallel to the Clipping Plane and A=0         B=0

   This case indicates that the plane of the polygon is parallel to one of the clipping planes. In this case the sign of c determines whether the plane of the polygon is visible or not. If c&lt;0, then the entire bounding box is invisible. The Edge Generator  103  will function normally, but all spans will be marked as being “outside the bounding box”. Otherwise, all spans will be marked as being “inside the bounding box”. 
   Wire-Frame Support 
   The next two cases involve wire-frame support.  FIG. 3  is a diagram illustrating a wire-frame of a triangle, according to one embodiment of the present invention. The wire-frame of a triangle is a disjunction of three parallelograms, each of which represents an edge of the triangle. We assume that a wire-frame to be drawn comprises a one-pixel line width. The wire-frame support reliably works in the following conditions: (a) no over-sampling (i.e. the current grid is the same as the pixel grid), and (b) the width of the wire-frame is one unit of the current grid (i.e. one pixel according to the foregoing assumption). If the wire-frame support works for any other mode (either over-sampling is on or the width is more than one) we consider the availability of those modes a bonus, which we suppose to get almost for free. 
   We restrict the wire-frame mode as not comprising any clipping functionals besides a frustum. This means that a wire-framed triangle comprises (a) three functionals representing the triangle edges and (b) the bounding box. 
   A wire-framed triangle comprises three parameters for drawing: 
   
       
       Width The width of an edge, expressed as the number of pixels to be covered by a triangle edge in the minor direction. A Span Generator  101  (shown in  FIG. 7 ) correctly processes a wire-frame with a one-pixel width. 
       Edge flag Draw-edge flag (one bit per edge). Each edge of the triangle is equipped with a draw-edge flag, indicating whether the edge is to be drawn. 
       Extension Bounding box extension. If the draw-edge flag is set for an edge, the bounding box is extended by half of the wire-frame line width.
 
The wire-frame is an intersection of the “tight” bounding box and an exclusive intersection of two closed-edges triangles. Since the original functionals specify the center-line of each edge of the wire-framed triangle, the functionals for the wire-frame are offset by half of the wire-frame width in the “minor” direction, i.e. in the direction of that coordinate whose coefficient in the functional has a smaller absolute value:
 
Case 8: Right Closed Half-plane for Wire-frame and A&lt;0         B≧0
 
There is no difference between this case and the special case, so we need to make no corrections for this case
 
     
  
                   x   0     =       max     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢     a   ·   x       +     b   ·   y     +   c     ≥   0     }               (   46   )               
Case 9: Right Closed Half-plane for Wire-frame and A≦0           B&lt;0
 
Again we need to find

                   x   0     =       max     x   ∈   Z       ⁢     {         x   ⁢     :     ⁢     a   ·   x       +     b   ·   y     +   c     ≥   0     }               (   47   )               
Substituting x=W−{tilde over (x)}
 
                   x   0     =     W   -       min       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :       -     a   ·     x   ~       +     b   ·   y     +   c   +     W   ·   a       ≥   0     }                 (   48   )               
and computing maximum in the complimentary semi-plane
 
                   x   0     =     W   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :       -     a   ·     x   ~       +     b   ·   y     +   c   +     W   ·   a       &lt;   0     }       -   1             (   49   )               
and rewriting the constraint and collecting appropriate terms we results in
 
                   x   0     =     W   -   1   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :     ⁢     a   ·     x   ~         -     b   ·   y     -   c   -     W   ·   a       &gt;   0     }                 (   50   )               
and finally
 
                   x   0     =     W   -   1   -       max       x   ~     ∈   Z       ⁢     {           x   ~     ⁢     :     ⁢       a   ~     ·     x   ~         +       b   ~     ·   y     +     c   ~       ≥   0     }                 (   51   )               
wherein
   ã=a, {tilde over (b)}=−b, {tilde over (c)}=−c−W·a −1  (52) 
reducing once again to the special case.
 
The Loader
 
   The Edge Generator  103  works under the assumption of the special case described above, allowing significant reduction of its hardware and resulting in faster operation. The Loader  102  is the element which transforms a general case to the special case, converting an input functional described by a general case into a form expected by the special case, thereby allowing the Edge Generator  103  to compute edge values correctly and efficiently. 
   The Loader  102  accepts as inputs a functional and a bounding box offset, and produces a set of coefficients a, b, and c according to the special case for the Edge Generator  103 . 
   We have:
 
 F ( x, y )= a·x′+b·y′+c′ 
 
X∈[x min , x max ], [y min , y max ]  (53)
 
Since the functional coefficients are expressed in the main grid and the x, y coordinates are expressed in the over-sampling grid, we have a grid ratio of s=2 6+[0, 1, 2]  and will convert the c′ value to the over-sampling grid. The particular conversion depends on the type of the half-plane at hand. For a closed half-plane the conversion is as follows:
 
                   f   ⁡     (     x   ,   y     )       =           a   ·     x   ′       +     b   ·     y   ′       +     c   ′       ≥   0     ⇒             (   54   )                       a   ·   s   ·   x     +     b   ·   s   ·   y     +     c   ′       ≥   0     ,           ⁢       x   ′     =     s   ·   x       ,           ⁢       y   ′     =       s   ·   y     ⇒         ⁢                                         a   ·   x     +     b   ·   y     +       c   ′     s       ≥   0     ⇒                                 a   ·   x     +     b   ·   y     +   c     ≥   0     ,           ⁢     c   =     floor   ⁢           ⁢     (       c   ′     s     )                                 
For an opened half-plane the conversion is as follows:
 
   
     
       
         
           
             
               
                 
                   f 
                   ⁡ 
                   
                     ( 
                     
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                     ) 
                   
                 
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                 ( 
                 55 
                 ) 
               
             
           
           
             
               
                 
                   
                     
                       
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                     0 
                   
                   , 
                   
                       
                   
                   ⁢ 
                   
                     
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                       s 
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                       x 
                     
                   
                   , 
                   
                       
                   
                   ⁢ 
                   
                     
                       y 
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                         s 
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                 ⁢ 
                 
                     
                 
               
             
             
               
                   
               
             
           
           
             
               
                 
                   
                     
                       a 
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                       x 
                     
                     + 
                     
                       b 
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                 ⁢ 
                 
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                   = 
                   
                     ceiling 
                     ⁢ 
                     
                         
                     
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                       ( 
                       
                         
                           c 
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                         s 
                       
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   It is an advantageous aspect of the present invention that two or more Edge Generators  103  may participate in span generation for the same functional. In one embodiment of the present invention, wherein k=1 (respectively 2 or 4) Edge Generators  103  participate in the span generation for the same functional, we want the first span of the 2 (respectively 4 or 8) spans generated per clock cycle to be aligned by y coordinate by 2 (respectively 4 or 8) accordingly. To accomplish this, denote 
                 y   ~     min     =       floor   ⁢             ⁢             (       y   min       k   ·   2       )     ·   k   ·   2       ,         
and substitute {tilde over ({tilde over (x)}=x−x min , {tilde over ({tilde over (y)}=y−y min , {tilde over ({tilde over (c)}=c−a·x min −b·{tilde over (y)} min  to obtain
   f ( {tilde over ({tilde over (x)}, {tilde over ({tilde over (y)} )= a·{tilde over ({tilde over (x)}+b·{tilde over ({tilde over (y)}+{tilde over ({tilde over (c)}   (56) 
The size of the bounding box is (x max −x min )·(y max −y min ). Here we take
   m =ceiling (log 2 ( x   max   −x   min ))  (57) W=2 m   (58) 
Observing the above cases, taking (23), (52), (38) and (42) in consideration and uniting common expressions results in
   ã=−|a|   (59)   {tilde over ({tilde over (b)}=−|b|   (60) 
                   c   ~     =     {               c     ~   ~       -   1     ,           a   &lt;     0   ⋀   b     ≥   0                   -     c     ~   ~         -     a   ·   W       ,           a   ≤     0   ⋀   b     &lt;   0                   -     c     ~   ~         -   1     ,           a   &gt;     0   ⋀   b     ≤   0                   c     ~   ~       +     a   ·   W       ,           a   ≥     0   ⋀   b     &gt;   0                     (   61   )               
The number of c values generated according to the foregoing description corresponds to the number of spans that are to be generated per clock cycle, wherein an Edge Generator  103  generates two spans per clock cycle. Each Edge Generator&#39;s  103  spans are to be aligned by y such that the first span is even (i.e. y min  mod 2=0) and the second is odd (i.e. y min  mod 2=1). If the y min  of the bounding box is odd, span generation starts from y min −1. To accomplish that, denote
   c   0   0   ={tilde over (c)}−{tilde over ({tilde over (b)}· ( y   min  mod 2)   c   1   0   =c   0   0   +{tilde over ({tilde over (b)}     {tilde over (b)} =2 ·{tilde over ({tilde over (b)}   (62) 
In the case of more than one Edge Generator  103  participating in span generation for the functional, we need to have more than one set of initial values for the spans. Assuming the number of Edge Generators  103  is k (wherein k=1, 2 or 4), the set of initial values is given by
 c j   i   =c   j   0 +2 ·{tilde over ({tilde over (b)}·i, i= 1 , . . . , k, j= 0, 1   {tilde over (b)}=k·{tilde over ({tilde over (b)}   (63) 
and the Edge Generators  103  participating in the span generation for the given functional are loaded with the initial values of c j   i , {tilde over (b)} and ã.
 
Moving Down
 
Before the Bresenham traversal, an Edge Generator  103  performs two operations: moving-down and Bresenham setup. The initial values are
   f ( {tilde over (x)}, {tilde over (y)} )= ã·{tilde over (x)}+{tilde over (b)}·{tilde over (y)}+{tilde over (c)}, {tilde over (x)} =0 , {tilde over (y)} =0  (64) 
with the goal of computing for each given {tilde over (y)}
 
                       x   ~     0     =     floor   ⁢             ⁢             (     -           b   ~     ·     y   ~       +     c   ~         a   ~         )       ,           ⁢       c   ~     ≥   0             (   65   )               
Additionally, an Edge Generator  103  generates an {tilde over (x)} inside the bounding box. Therefore, if x 0  is outside the bounding box, x 0  is substituted by 0 or W such that
 
                   x   ~     =     {           0   ,               x   ~     0     &lt;   0                   x   ~     0     ,               x   ~     0     ∈     [     0   ,   W     ]                 W   ,               x   ~     0     &gt;   W                     (   66   )               
After converting to a special case within the bounding box, we have f({tilde over (x)}, {tilde over (y)})&lt;0 for the points above the edge (represented by the functional) and f({tilde over (x)}, {tilde over (y)})≧0 on or below the edge, wherein “above” refers to smaller y coordinates and “below” refers to greater y coordinates. We also have b≧0 and a&lt;0 as given by the special case conditions.
 
     FIG. 4  is a flow diagram illustrating a method for the moving-down process in preparation the Bresenham setup, according to an embodiment of the present invention. The moving-down process starts  200  with {tilde over (y)} k =0. If  201  the functional value f(0, {tilde over (y)} k )≧0 the moving-down process is complete  202 . Otherwise  203 , move down along the {tilde over (x)}=0 border of the bounding box by adding  204  {tilde over (b)} to the functional value at the rate of one increment per clock cycle (wherein {tilde over (b)}≧0 and a {tilde over (b)} increment of the functional value corresponds to incrementing y by 1 until ƒ(0, {tilde over (y)} k )≧0  201  (wherein k&gt;i), at which point the moving-down process is  202  complete. The moving-down process is represented by the following iterative description:
 {tilde over (y)} 0 =0   f   0   =f (0, 0)= ã ·0 +{tilde over (b)} ·0 +{tilde over (c)}={tilde over (c)}     f   i   =f (0 , i )= {tilde over (b)}·i+f   0   ={tilde over (b)} ·( i −1)+{tilde over (b)}+f 0   =f   i−1   +{tilde over (b)}   (67) 
Bresenham Setup
 
   The moving-down process is followed by the Bresenham setup process. The purpose of the Bresenham setup is to find the two values 
                   x   0     =       max     x   ∈   Z       ⁢     {           x   ~     ⁢     :     ⁢       a   ~     ·     x   ~         +       b   ~     ·       y   ~     k       +     c   ~       ≥   0     }               (   68   )               
and
 
                   Δ   ⁢           ⁢   x     =     floor   ⁢           ⁢     (     -       b   ~       a   ~         )               (   69   )               
Furthermore, since
   {tilde over (b)}·{tilde over (y)}   k   +{tilde over (c)}=f (0 , {tilde over (y)}   k )  (70) 
we obtain
 
                   x   0     =     floor   (       f   ⁡     (     0   ,       y   ~     k       )         -     a   ~         )             (   71   )               
The division algorithm described above (see Special Case) is modified as follows for more efficient hardware implementation:
   c   0   =f (0 , {tilde over (y)}   k ),  a   0   =ã ·2 m+1   , b   0   ={tilde over (b)}, x   00   =Δx   0 =0  (72) 
with the following steps describing the iterations:
 
                           c     i   +   1       =     2   ·     {               c   i     +     a   0       ,               c   i     +     a   0       ≥   0                 c   i     ,               c   i     +     a   0       &lt;   0                             x       0   ⁢   i     +   1       =       2   ·     x     0   ⁢   i         +     {           1   ,               c   i     +     a   0       ≥   0               0   ,               c   i     +     a   0       &lt;   0                             b     i   +   1       =     2   ·     {               b   i     +     a   0       ,               b   i     +     a   0       ≥   0                 b   i     ,               b   i     +     a   0       &lt;   0                             Δ   ⁢           ⁢     x     i   +   1         =         2   ·   Δ     ⁢           ⁢     x   i       +     {           1   ,               b   i     +     a   0       ≥   0               0   ,               b   i     +     a   0       &lt;   0                       ,     i   =   1     ,   2   ,   …   ⁢           ,     m   +   1             (   73   )               
The values e 0 =c m+1 =f(0, {tilde over (y)} k ) mod |a| and r 0 =b m+1 =|b| mod |a| are used in the Bresenham walk (described below) for calculating the Bresenham error. The value
 
             x   0     =     floor   (       f   ⁡     (     0   ,       y   ~     k       )         -     a   ~         )           
is the x value for the first span after the moving-down process.
 
The value
 
             Δ   ⁢           ⁢   x     =     floor   (     -       b   ~       a   ~         )           
is the span-to-span x-increment value.  FIG. 5  is a flow diagram illustrating the foregoing method for the Bresenham setup process, according to an embodiment of the present invention.
 
Bresenham Walk
 
   The Bresenham walk is the process following the moving-down and Bresenham setup processes. After the Bresenham setup we have
 
 ã·{tilde over (x)}+{tilde over (b)}·{tilde over (y)}+{tilde over (c)} =0  (74)
 
wherein
 
 e   0   =f (0 , {tilde over (y)}   k ) mod |a|  (75)
 
                   x   0     =     floor   (       f   ⁡     (     0   ,       y   ~     k       )         -     a   ~         )                               r   0     =          b        ⁢           ⁢   mod   ⁢           ⁢        a                                    Δ   ⁢           ⁢   x     =     floor   (     -       b   ~       a   ~         )                           and                               a   ~     ·       x   ~     n       +       b   ~     ·       y   ~       n   +   k         +     c   ~       =           a   ~     ·       x   ~     n       +       b   ~     ·       y   ~       n   +   k         +     f   ⁡     (     0   ,       y   ~     k       )       -       b   ~     ·       y   ~     k         =     0   ⇔               (   76   )                     a   ~     ·       x   ~     n       +       b   ~     ·       y   ~     n       +     f   ⁡     (     0   ,       y   ~     k       )         =   0           (   77   )               
and we want to find
 
                             x   ~     n     =           -       b   ~       a   ~         ·       y   ~     n       -       f   ⁡     (     0   ,       y   ~     k       )         a   ~         ⇔                     x   ~     n     =           f   ⁡     (     0   ,       y   ~     0       )            a          +            b             a          ·       y   ~     n         ⇔                     x   ~     n     =         x   0     +       e   0          a          +     Δ   ⁢           ⁢     x   ·   n       +         r   0          a          ·   n       ⇔                     x   ~     n     =           x   ~       n   -   1       +     Δ   ⁢           ⁢   x     +         e     n   -   1       +     r   0            a            ⇒                     x   ~     n     =         x   ~       n   -   1       +     Δ   ⁢           ⁢   x     +     {           0   ,               e     n   -   1       +     r   0       &lt;        a                    1   ,               e     n   -   1       +     r   0       ≥        a                                  e   n     =       e     n   -   1       +     r   0     -     {           0   ,               e     n   -   1       +     r   0       &lt;        a                         a        ,               e     n   -   1       +     r   0       ≥        a                            ,     n   =   1     ,   2   ,   …   ⁢           ,     h   -     y   k               (   78   )               
wherein h represents a height of the bounding box and y k  represents the value of the y coordinate at the Bresenham setup point. To simplify the hardware, the error value is decremented by |a| at the beginning of the Bresenham walk, after which e n  can be compared to 0, with the comparison being simpler to implement in hardware. We also calculate
   r   i   =r   0   −|a|     {tilde over (e)}   0   =e   0   +r   0   −|a|   (79) 
after which the Bresenham walk is more simply described as follows:
 
                             x   ~     n     =         x   ~       n   -   1       +     Δ   ⁢           ⁢   x     +     {           0   ,               e   ~       n   -   1       &lt;   0               1   ,               e   ~       n   -   1       ≥   0                               e   ~     n     =         e   ~       n   -   1       +     {             r   0     ,               e   ~       n   -   1       &lt;   0                 r   1     ,               e   ~       n   -   1       ≥   0                       ,     n   =   1     ,   2   ,   …   ⁢           ,     h   -     y   k               (   80   )                 FIG. 6  is a flow diagram illustrating a method for the Bresenham walk process, according to an embodiment of the present invention.
 
Span Generator Structure
 
     FIG. 7  is a block diagram illustrating the Span Generator  101 , according to an embodiment of the present invention. The Span Generator  101  comprises
         An Input Interface  105     3 Loaders  102     12 Edge Generators  103     4 cascaded 3-input Sorters  104     An Output Interface  106     A scissoring box module  107         
   Input Interface  105  packs input functionals for passing to the three Loaders  102 . Loaders  102  perform Edge Generator  103  initialization. Edge Generators  103  generate “left” and “right” edges, which are then sorted in tournament Sorters  104 . The Sorters&#39;  104  output is directed via Output Interface  106  to a Tile Generator (TG), the TG for converting a set of spans into a sequence of tiles, wherein a tile refers to a rectangle set of pixels to be rendered. 
   Advantageously, the Span Generator  101  solves the following issues: 
   
       
       
         
           1. The Span Generator  101  produces spans for a triangle having up to 15 functionals. The X and Y clipping is performed by the scissoring box module  107 , and thus 11 functionals remain. For reasons described in items 3 and 4, there are 12 Edge Generators  103  in the Span Generator  101  architecture. 
           2. The Span Generator  101  generates at least two spans per clock cycle, presenting a doubling of performance when compared to generating one span per clock cycle, for 30% more cost. 
           3. In the case of a reduced set of functionals (i.e. fewer than 7 or 8) the Span Generator  101  can generate more than two spans per clock cycle. In this case we use two Edge Generators  103  to process the same functional. The Loaders  102  setup the Edge Generators  103  at different spans according to the initial offsets of the respective Edge Generators  103 . Analogously, in the case of fewer than 4 functionals, the span generation rate reaches eight spans per clock cycle. 
           4. The Loaders  102  provide the maximal Span Generator  101  performance for the most general case, which is a case involving 3 functionals. Thus the Span Generator  101  comprises 3 Loaders  102 , wherein a Loader  102  can load four Edge Generators  103  sequentially. 
           5. For non-adaptive over-sampling with a rotating grid, the Span Generator  101  perform clipping by several half-planes with a known tangent, a process that can be done using a separate device.
 
External Assumptions of Data Formats
 
         
       
     
  
                                                                     Bits for               Range   representation   Comment                                    Window size,   [0 . . . 2 12  − 1] × [0 . . . 2 12  − 1]   12   To be able to draw into 4096 × 4096       pixels           texture       Maximum   2 2      2   Not the same as vertex subpixel grid, it       divisions of           is coarser. The functional coefficients       oversampling           will be given in the vertex subpixel grid       grid per pixel           while the x, y coordinates are in the                   oversampling one.       Window size,   [0 . . . 2 14 ] × [0 . . . 2 14 ]   15   Extreme window&#39;s pixels in rotated grid       over-samples           coordinates       Vertex X, Y after   [0 . . . 2 14  + 1] × [0 . . . 2 14  + 1]   15   We need one more grid position on the       clipping, over-           right and bottom as otherwise the last       samples.           column (raw) of pixels cannot be drawn                   (with tight clipping) because of                   open/close convention, hence a value of                   2 14  + 1 is possible here       Subpixel vertex   [0 . . . 2 8  − 1]    8   Main grid for the triangle setup       position, per pixel       (subpixel               bits)       Vertex X, Y after   [0 . . . 2 20  + 1] × [0 . . . 2 20  + 1]   21   We need one more grid position on the       clipping, sub-           right and bottom as otherwise the last       pixels units.           column (raw) of pixels cannot be drawn                   (with tight clipping) because of                   open/close convention, hence a value of                   2 20  + 1 is possible here                    
Internal Data Formats
 
                                                                     Bits for               Range   representation   Comment                                    Edge functional   [−2 20  − 1 . . . 2 20  + 1]   21 + sign   See below       coefficients a i , b i ,       see below       Edge functional   ±(2 40  + 2 21  + 1)   41 + sign   See below       coefficients (in a       window       coordinate system       after setup) c i  (see       below)       Bounding box   [0 . . . 2 14 ]   15   Bounding box origin is inclusive; it       origin (x min , y min )           values the first x position to draw and       in oversampling           the first span to draw (if span is not       grid units           empty).                   The bounding box is defined as an                   original bounding box of a triangle                   intersected with the scissoring box. If no                   scissoring box exists, then the window                   box is used as a scissoring box.       Edge functional   ±(2 40  + 2 35  + 2 21  + 2 15  + 1)   41 + sign       coefficients after       shifting to the       bounding box       system c i , see       below       Bounding box   [0 . . . 2 14  + 1]   15   Bounding box max point is inclusive; it       maximum point           values the last x position to draw and the       (x max , y max )           last span to draw (if span is not empty).       Non adjusted   [0 . . . 2 14  + 1]   15   The box with the width of 0 can have a       bounding box           single pixel column inside, since both       width x max  − x min             sides of the box are inclusive.       Extended   2 [0 . . . 15]      4   Adjusted (extended) bounding box is       bounding box           used in the interpolator, since the width       width x max  − x min             is to have a value of a power of two.       rounded to the           Note: the extended box can be wider       next power of 2           then the window.                    
Input Interface
 
The Span Generator  101  has the following input interface:
 
                                   Field   Length,           name   bit   Description                   L    1   The signal to start loading the first three functionals       M    1   Mode: 0 - standard, 1 - wire-frame       R    8   The width of the wire-frame line in the current grid               units       F    4   The number of the functionals. In the case of the wire-               frame mode, the three LSB are the mask for drawing               the edges (0 indicates do not draw, 1 indicates draw),               and MSB is a request to extent the bounding box by               W/2 in all directions       A   22 × 3   The value of the a coefficients for the 11 functionals. 0               if the particular functional is not present       B   22 × 3   The value of the b coefficients for the 11 functionals. 0               if the particular functional is not present       C   42 × 3   The value of the c coefficients for the 11 functionals. 0               if the particular functional is not present       X0   15   The start x value for the left edge of the scissoring box       X1   15   The start x value for the right edge of the scissoring               box       Y   15   The value of the y coordinate in the top corner of the               scissoring box       Y0   15   The value of the y coordinate in the left corner of the               scissoring box       Y1   15   The value of the y coordinate in the right corner of the               scissoring box       Y2   15   The value of the y coordinate in the bottom corner of               the scissoring box       T    2   The tangent of the slope of the left edge of the               scissoring box, according to the following:               00 The right edge is vertical               01 The tangent is 1               10 The tangent is 2               11 The tangent is 3       XMIN   15   The value of the x coordinate for the left edge of the               bounding box       XMAX   15   The value of the x coordinate for the right edge of the               bounding box       YMIN   15   The value of the y coordinate for the top edge of the               bounding box       YMAX   15   The value of the y coordinate for the bottom edge of               the bounding box                    
Wire-frame
 
   We assume the wire-frame will be done as three functionals for edges inside the tight bounding and scissoring boxes. That means we do not support clipping planes for wire-frame. The span generation for the wire-frame mode does not take anything special besides the Loader  102  should supply corrected functional values for two nested triangles. The inner triangle is a set of points on the current grid, which should be excluded from the outer triangle. For an edge f(x, y)=a·x+b·y+c, the functional values for that two triangles will be
 
ƒ 1 ( x, y )= a·x+b·y+c+w /2 —outer edge
 
ƒ 2 ( x, y )= a·x+b·y+c−w /2 —inner edge
 
where w is a width of the wireframe edges.
 
Loader
 
     FIG. 8  is a block diagram illustrating a Loader  102  (without shifters), according to an embodiment of the present invention. Loader  102  comprises the following inputs: 
   
     
       
             
             
           
         
             
                 
                 
             
           
           
             
                 
               SHORT xMin, yMin, xMax, yMax, a, b; 
             
             
                 
               LONG c; 
             
             
                 
               SHORT nF;  // the number of the functionals 
             
             
                 
               and outputs 
             
             
                 
               SHORT c0l, c0h, c1l, c1h, bl, bh, al, ah, m; 
             
             
                 
               BOOL dir, cor 
             
             
                 
                 
             
           
        
       
     
   
   Initially, a Loader  102  determines the global values, which are the same for all of the functionals in the polygon. To accomplish this, the Loader  102  computes the parameters of the bounding box: 
                                               SHORT w = xMax − xMin;               m = ceiling (log2 (w));           SHORT W = 1 &lt;&lt; m;   // 2**m           SHORT h = yMax − yMin;           SHORT k = (nF &gt; 6)? 1 : (nF &gt; 3);           SHORT aT, bT;   // ã and {tilde over (b)}                        
Then for each functional the Loader  102  computes
 
   
     
       
             
             
           
         
             
                 
                 
             
           
           
             
                 
               nCase = (a &lt; 0 &amp;&amp; b &gt;= 0)? 1 : 
             
             
                 
                (a &lt;= 0 &amp;&amp; b &lt; 0)? 2 : 
             
             
                 
                (a &gt; 0 &amp;&amp; b &lt;= 0)? 4 : 
             
             
                 
                (a &gt;= 0 &amp;&amp; b &gt; 0)? 5 : 0; 
             
             
                 
                      // but the “0” is redundant 
             
             
                 
               BOOL cor = (nCase &gt; 3)? 1 : 0; 
             
             
                 
               BOOL dir = (nCase &lt; 2 ∥ ncase &gt; 4)? 0 : 1; 
             
             
                 
               LONG cT2 = c − a * xMin − b * yMin;  // {tilde over ({tilde over (c)})} 
             
             
                 
               switch (nCase) { 
             
             
                 
                case 1: 
             
             
                 
                 aT = a; 
             
             
                 
                 bT = b; 
             
             
                 
                 cT = cT2 − 1;             // {tilde over (c)} 
             
             
                 
                 break; 
             
             
                 
                case 2: 
             
             
                 
                 aT = a; 
             
             
                 
                 bT = −b; 
             
             
                 
                 cT = −cT2 − a * W; 
             
             
                 
                case 4: 
             
             
                 
                 aT = −a; 
             
             
                 
                 bT = −b; 
             
             
                 
                 cT = −cT2 − a; 
             
             
                 
                case 5: 
             
             
                 
                 aT = −a; 
             
             
                 
                 bT = −b; 
             
             
                 
                 cT = cT2 + a * W; 
             
             
                 
                } 
             
             
                 
                 
             
           
        
       
     
   
   The Loader  102  then computes two separate functional values for two sequential spans, and in the case of having k=1, 2, 4 Edge Generators  103  per functional, the Loader  102  also computes values for all other two or six sequential spans: 
   
     
       
             
             
           
         
             
                 
                 
             
           
           
             
                 
               c [0] = cT − bT * (yMin % 2); 
             
             
                 
               c [1] = c [0] + bT; 
             
             
                 
               for (i = 1; i &lt; k; i ++) { 
             
             
                 
                c [i * 2 ] = c [i * 2 − 2] + 2 * bT; 
             
             
                 
                c [i * 2 + 1] = c [i * 2 − 1] + 2 * bT; 
             
             
                 
                } 
             
             
                 
               bT &lt;&lt;= k; 
             
             
                 
                 
             
           
        
       
     
   
     FIG. 9  is a block diagram illustrating {tilde over (b)} and {tilde over (c)} values wrapping before they are loaded into an Edge Generator  103 , according to an embodiment of the present invention. The division algorithm is described above (see Special Case). But if it is performed literally then the ã value needs to be scaled before division multiplying it by 2 m , which scales ã out of short range. Nevertheless each clock of division effective length of subtraction is still in the short range, thus instead of scaling the ã value, the f(0, {tilde over (y)} k ) value is scaled by 2 −m  before the division and then instead of dividing the scaled ã value by 2 each clock, the scaled f(0, {tilde over (y)} k ) value is multiplied by 2. While a 
             Δ   ⁢           ⁢   x     =     floor   (     -       b   ~       a   ~         )           
value is also needed, the {tilde over (b)} value is also pre-scaled. The scaled f(0, {tilde over (y)} k ) value is longer than the non-scaled value. However, this does not necessitate a longer adder for performing the moving-down process: The least significant bits of the scaled f(0, {tilde over (y)} k ) value are wrapped to the most significant bits (i.e. a cyclic rotation instead of an arithmetical shift), resulting in the scaled f(0, {tilde over (y)} k ) value being expressed within the same bit-length as the non-scaled value. To avoid carry propagation from MSB to LSB, invert the sign bit before loading data into an Edge Generator  103 . In the case of f(0, {tilde over (y)} k )&lt;0 this bit would be 0 and would not propagate a carry. To detect if f(0, {tilde over (y)} k )≧0, compare this bit to 1. The {tilde over (b)} value is scaled in a similar way, with the difference that it is not wrapped.
 
   At the first clock cycle of the division process, Edge Generator  103  determines whether one of the f(0, {tilde over (y)} k ) or {tilde over (b)} values exceed the boundaries, i.e. it determines whether the division result would be greater than or equal to W. For that purpose, the real scale factor is not m, but m+1. The division works in the above-described way, but if the result is not below W, either x 0  will be beyond the bounding box limit or the result after the first Bresenham step would be beyond the bounding box limit. 
   The Loader  102  loads the Edge Generators  103  sequentially, starting from the first three functionals of each triangle, with the first functional loaded into the first Edge Generator  103 , and so on. If there are only three functionals, the Loader  102  loads other Edge Generators  103  with the functional values for other three groups of spans on the next sequential clock cycles. 
   Considering the input interface and the approach of loading several Edge Generators  103  at subsequent clock cycles, the pseudo-code for the Loader  102  is as follows: 
                                                                                                                                                             template &lt;int N&gt;           void Loader&lt;N&gt; ( //pipelined, performed each clock                // input interface:            bool L, // the first clock of loading the L = 1            bool M, // M = 1 in the wire-frame mode            BIT2 Os,// oversampling grid to pixel grid relation:                // 0 − 4x, 1 − 2x, 2 − 1x            BIT8 R, // the width of a wire-frame line            BIT4 F, // the number of functionals, edge mask in wire-           frame mode            SHORT A, // the first coefficient            SHORT B, // the second coefficient            LONG C,  // the free member            BIT21 XMIN,  // the left edge of the bounding box            BIT21 YMIN,  // the top edge of the bounding box            BIT21 XMAX,  // the right edge of the bounding box            BIT21 YMAX,  // the bottom edge of the bounding box            BIT21 XFUN,  // the X coordinate of the zero functional           point            BIT21 YFUN // the Y coordinate of the zero functional           point            ) {                 BIT3 toGo = (L)? 4 : toGo − 1;   // counts the           number of               // functionals to           load                 BIT3 nClk = (L)? 0 : nClk + (toGo != 0);   // counts           loading                // clocks                 if (L) {             bool wf = M,             BIT8 wW = R,             BIT15 xMIN = ((xMIN &gt;&gt; 5)             BIT4 nFunct = F,             BIT2 k = (wf)? 2 : (nFunct &lt; 4)? 4 : (nFunct &lt; 7)? 2 :           1;             BIT21 w = XMAX − XMIN;             BIT21 h = YMAX − YMIN;             BIT4 m = ceiling (log2 (w));                  BIT16 W = 1 &lt;&lt; m;   // 2**m                  BIT15 xMin = XMIN;             BIT15 yMin = YMIN;             }            BIT3 nCase =             (A &lt; 0 &amp;&amp; B &gt;= 0)? 1 :             (A &lt;= 0 &amp;&amp; B &lt; 0)? 2 :             (A &gt; 0 &amp;&amp; B &lt;= 0)? 4 :             (A &gt;= 0 &amp;&amp; B &gt; 0)? 5 :             0; // redundant, not used            BOOL cor = nCase &gt; 3;            BOOL dir = nCase &gt;= 2 &amp;&amp; nCase &lt; 5;                 SHORT aT = (A &gt;= 0)? −A : A;   // ã            SHORT b2T = (B &lt; 0)? −B : B;   // {tilde over ({tilde over (b)})}            LONG cT2 = C −   // {tilde over ({tilde over (c)})}             A * (xMin − XFUN) −             B * ((yMin &amp; −(k &lt;&lt; 1) − YFUN);   // align spans by Y                 cT2 &gt;&gt;= (6 + Os);   // shift to           get                 LONG CT = ((dir)? −cT2 : cT2)   // {tilde over (c)}             + (nCase == 1 ∥ nCase == 4)? −1 :             (dir)? −A &lt;&lt; m : A &lt;&lt; m;            LONG c [8];            LONG b [4];            c [7] = c [5] + (b2T &lt;&lt; 1);   // pipelining            c [6] = c [4] + (b2T &lt;&lt; 1);            c [5] = c [3] + (b2T &lt;&lt; 1);            c [4] = c [2] + (b2T &lt;&lt; 1);            c [3] = c [1] + (b2T &lt;&lt; 1);            c [2] = c [0] + (b2T &lt;&lt; 1);            c [0] = cT − (yMin &amp; 1)? b2T : 0;            c [1] = c [0] + b2T;            SHORT bT = b2T &lt;&lt; (1 &lt;&lt; k);   // &lt;&lt; 2, 4, 8                        
Edge Generator
 
     FIG. 10   a  is a block diagram illustrating an Edge Generator, according to an embodiment of the present invention. The Edge Generator  103  comprises four 24-bit adders and eight 24-bit registers. An adder has the outputs of two registers as inputs, wherein the inputs of the registers are multiplexed: 
   
     
       
             
             
           
         
             
                 
                 
             
           
           
             
                 
               SHORT reg [8]; 
             
             
                 
               bool carry [4]; 
             
             
                 
               SHORT add [4]; 
             
             
                 
               add [0] = req [0] + reg [4] + carry [0]; 
             
             
                 
               add [1] = reg [1] + reg [5] + carry [1]; 
             
             
                 
               add [2] = reg [2] + reg [4] + carry [2]; 
             
             
                 
               add [3] = reg [3] + reg [7] + carry [3]; 
             
             
                 
               for (i = 0; i &lt; 8; i ++) 
             
             
                 
                reg [i] = some_function (add [k], reg [k], ...); 
             
             
                 
                 
             
           
        
       
     
   
   The registers&#39; outputs are supplied directly to inputs of adders to minimize a delay at the adders. The structure of multiplexers allows us to minimize a delay at them also, the maximal post-adder delay supposed to be not more than 3×1 multiplexer. 
   Besides the implementation of the general functionality, the multiplexers are also performing loading and stalling operations by writing a new set of data or a previous state of an Edge Generator  103  back to registers. 
   The basic functionality of an Edge Generator  103  comprises three main phases: moving-down, Bresenham setup and Bresenham walk. There are also seven interim states, which are: load, stall, first clock of moving down, transfer from moving down to Bresenham setup, two different clocks of transfer from Bresenham setup to Bresenham walk and finally first clock of the Bresenham. 
   An Edge Generator  103  has the following inputs: 
   
     
       
             
             
           
         
             
                 
                 
             
           
           
             
                 
               SHORT c0l, c0h, c1l, c1h, bl, bh, al, ah, m; 
             
             
                 
               BOOL dir, cor, load, stall; 
             
             
                 
                 
             
           
        
       
     
   
   When the load signal is set, the Edge Generator  103  stores the input values in internal registers and resets its state. When the stall signal is set, the Edge Generator  103  registers retain their content for the current clock cycle. 
   Edge Generator: Moving Down 
     FIG. 10   b  is a block diagram illustrating an Edge Generator  103  during the moving-down phase, according to an embodiment of the present invention. The functional value is accumulated in the register, which was loaded with the value of {tilde over (c)} at the start. At this phase each Edge Generator  103  performs the following: 
                                           while (c &lt; 0) {            c = c + b;            }                        
Applying this to the hardware, we obtain:
 
   
     
       
             
             
           
             
             
             
             
           
             
             
             
             
           
             
             
           
             
             
           
             
             
           
             
             
           
             
             
           
             
             
           
             
             
           
             
             
           
             
             
           
             
             
           
             
             
           
         
             
                 
                 
             
           
           
             
                 
               // at loading stage 
             
           
        
         
             
                 
               SHORT 
               mm 
               = bitlength (SHORT) − logm − 1; 
             
             
                 
               SHORT 
               mask_b 
               = 1 &lt;&lt; mm; 
             
             
                 
               SHORT 
               mask_a 
               = mask_b − 1; 
             
             
                 
               SHORT 
               mask_o 
               = −1 &lt;&lt; (mm − 1); 
             
           
        
         
             
                 
               SHORT 
               clock 
               = 0, repeat = 1;; 
             
           
        
         
             
                 
               bool pl, ph, rl = 0, rh = 0; 
             
             
                 
               while (repeat) { 
             
           
        
         
             
                 
               pl = rl 
             
             
                 
               ph = rh; 
             
             
                 
               if (clock == 0) { 
             
           
        
         
             
                 
               clock = 1; 
             
             
                 
               if (ch &amp; mask_b) { 
             
           
        
         
             
                 
               repeat = 0; 
             
             
                 
               continue; 
             
             
                 
               } 
             
           
        
         
             
                 
               rl = carry (cl + bl + ph); 
             
             
                 
               cl += bl; 
             
             
                 
               } 
             
           
        
         
             
                 
               else { 
             
           
        
         
             
                 
               rl = carry (cl + bl + ph); 
             
             
                 
               cl += bl + ph; 
             
           
        
         
             
                 
               if ((ch &amp; mask_a | masK_o) == −1 &amp;&amp; rl)   { 
             
           
        
         
             
                 
               repeat = 0; 
             
             
                 
               continue; 
             
             
                 
               } 
             
           
        
         
             
                 
               rh = carry (ch + bh + pl); 
             
             
                 
               ch += bh + pl; 
             
             
                 
               } 
             
           
        
         
             
                 
               } 
             
             
                 
                 
             
           
        
       
     
   
   The masks are for preliminary zero crossing detection, and their use allows avoiding “backing-down” the functional value, since the data is not written back to ch and the LSBs of ch remain intact. The masks also allow detection of a zero crossing one clock cycle earlier. 
   Setup 
     FIG. 10   c  is a block diagram illustrating an Edge Generator during the Bresenham setup phase, according to an embodiment of the present invention. The division algorithm was described above under “Special Case”, and is implemented as follows: 
                                           // after moving down           setup:           ch &amp;= ~ (mask_a | mask_b);           // setup           while (m != 0) {            BOOL c0l_c = carry (c0l + a);            if (!c0l_c) c0l += a;            c0l &lt;&lt;= 1;            c0l |= carry (c0h &lt;&lt; 1);            c0h &lt;&lt;= 1;            c0h |= !c0l_c;            BOOL c1l_c = carry (c1l + a);            if (!c1l_c) c1l += a;            c1l &lt;&lt;= 1;            c1l |= carry (c1h &lt;&lt; 1);            c1h &lt;&lt;= 1;            c1h |= !c1l_c;            BOOL bl_c = carry (bl + a);            if (!c0l_c) c0l += a;            bl &lt;&lt;= 1;            bl |= carry (bh &lt;&lt; 1);            bh &lt;&lt;= 1;            bh |= !bl_c;            m = m − 1;            }                        
Bresenham Walk
 
   After the Bresenham setup process completes, the four values ch, cl, bh and bl are produced, indicating the Bresenham error, x 0 , positive correction value and Δx, respectively. To perform edge generation we also need a negative correction value r 1 . The Loader  102  sets the Boolean variables dir and cor. Setting the variable dir to 1 indicates that the Edge Generator  103  subtracts the x value from W. Setting the cor variable to 1 indicates that the Edge Generator  103  adds 1 to the x value. If the x value overflows, an appropriate flag is set depending on the value of the dir variable. 
                                                                                                                   // after setup                SHORT fm = (1 &lt;&lt; m) − 1;   // negation mask =           W − 1           SHORT nm = (dir)? fm : 0;   // negate if dir           == 1           SHORT om = ~fm;   //   overflow mask to                detect x &lt; 0 or x &gt;= W           #define er ch           #define x0 cl           #define r0 bh           #define r1 a           #define dx bl           x0 = (nm {circumflex over ( )} x0) + cor; // x0 = W − 1 − x0 + cor           if (dir)             dx = ~dx;                r1 = a + b;    // a is negative, so r1 = |b| − |a|           // er = er + a;   // but we perform it later at first clock of           //   // Bresenham                // at this point some values are moving to different           registers           // according to general structure of the EG           // first clock           SHORT clock = 0;           BOOL uf = false, ov = false;           while (1) {             if (x0 &amp; om)                    if (dir) uf = true;   // x0 must be           negative               else  ov = true; //   x0 must be &gt;= W             if (uf ∥ ov) continue;//   do not update                registers             if (clock == 0) {               clock = 1;               x0 += dx + dir;               er += r1;               }             else {               x0 += dx + (er &gt;= 0)? 1 − dir : dir;               er += (er &gt;= 0)? r1 : r0;               }             }                        
Divider-by-3
 
   For the Scissoring Box, a divider-by-3 is used to multiply the y offset by ⅓. A pseudo-code for a 15-bit divider-by-3 is as follows: 
                                                                                                                                                                                               #define bit(a,n,m) ((a &gt;&gt; n) &amp; ((1 &lt;&lt; (m − n + 1)) − 1))             // not correct in terms of the ANSI C, but works in our           case           #define bitrev(a) (((a &amp; 2) &gt;&gt; 1) | ((a &amp; 1) &lt;&lt; 1))           #define simp(a,b,c,d) ((~d &amp; ~c &amp; b | c &amp; a | d &amp; ~b &amp; ~a)           &amp; 1)             // single-bit operation           #define remh(a,b) simp (a, a &gt;&gt; 1, b, b &gt;&gt; 1)           #define reml(a,b) simp (a &gt;&gt; 1, a, b &gt;&gt; 1, b)           #define rems(a,b) ((remh (a, b) &lt;&lt; 1) | reml (a, b))           #define sim1(a,b,c) ((~c &amp; b | c &amp; ~b &amp; ~a) &amp; 1)             // single-bit operation           #define sim2(a,b,c) ((~c &amp; a | c &amp; b   ) &amp; 1)             // single-bit operation           #define remc(a,b) sim1 (a, a &gt;&gt; 1, b)           #define remd(a,b) sim2 (a, a &gt;&gt; 1, b)           #define reme(a,b) ((remc (a, b) &lt;&lt; 1) | remd (a, b))           #define remf(a,b) bitrev (reme (bitrev (a), b))           bit16 div (bit15 a) {           bit15 c = a &amp; 0x2aaa, d = a &amp; 0x1555;             c = (c &amp; ~(d &lt;&lt; 1)) | (~(c &gt;&gt; 1) &amp; d);  // canonise           bit1                a14 = bit (a, 14, 14),           a13 = bit (a, 13, 13),           a11 = bit (a, 11, 11),           a09 = bit (a,  9,  9),           a07 = bit (a,  7,  7),           a05 = bit (a,  5,  5),           a03 = bit (a,  3,  3),           a01 = bit (a,  1,  1);                bit2 part0 [ 7] = {                bit (c,  0,  1), //bits 00, 01           bit (c,  2,  3), //bits 02, 03           bit (c,  4,  5), //bits 04, 05           bit (c,  6,  7), //bits 06, 07           bit (c,  8,  9), //bits 08, 09           bit (c, 10, 11), //bits 10, 11           bit (c, 12, 13) //bits 12, 13           },                bit2 part1 [ 8] = {                rems (part0 [ 1], part0 [ 0]),           reme (part0 [ 1], a01   ),           rems (part0 [ 3], part0 [ 2]),           reme (part0 [ 3], a05   ),           rems (part0 [ 5], part0 [ 4]),           reme (part0 [ 5], a09   ),           remf (part0 [ 6], a14   ),           a13 &amp; ~a14           },                bit2 part2 [ 8] = {                rems   (part1 [ 2], part1 [ 0]),           rems   (part1 [ 2], part1 [ 1]),           rems   (part1 [ 2], part0 [ 1]),           reme   (part1 [ 2], a03   ),           rems   (part1 [ 6], part1 [ 4]),           remh   (part1 [ 6], part1 [ 5]),           reml   (part1 [ 6], part0 [ 5]),           remc   (part1 [ 6], all    ),           },                bit2 part3 [8] = {                rems   (part2 [ 4], part2 [ 0]),           remh   (part2 [ 4], part2 [ 1]),           reml   (part2 [ 4], part2 [ 2]),           remh   (part2 [ 4], part2 [ 3]),           reml   (part2 [ 4], part1 [ 2]),           remh   (part2 [ 4], part1 [ 3]),           reml   (part2 [ 4], part0 [ 3]),           remc   (part2 [ 4], a07   )           };                bit14 m = bit (a, 0, 13) {circumflex over ( )} (                ((part3 [ 0] &amp; 1) &lt;&lt;  0) |           ((part3 [ 1] &amp; 1) &lt;&lt;  1) |           ((part3 [ 2] &amp; 1) &lt;&lt;  2) |           ((part3 [ 3] &amp; 1) &lt;&lt;  3) |           ((part3 [ 4] &amp; 1) &lt;&lt;  4) |           ((part3 [ 5] &amp; 1) &lt;&lt;  5) |           ((part3 [ 6] &amp; 1) &lt;&lt;  6) |           ((part3 [ 7] &amp; 1) &lt;&lt;  7) |           ((part2 [ 4] &amp; 1) &lt;&lt;  8) |           ((part2 [ 5] &amp; 1) &lt;&lt;  9) |           ((part2 [ 6] &amp; 1) &lt;&lt; 10) |           ((part2 [ 7] &amp; 1) &lt;&lt; 11) |           ((part1 [ 6] &amp; 1) &lt;&lt; 12) |           ((part1 [ 7] &amp; 1) &lt;&lt; 13));                return (m &lt;&lt; 2) | part3 [0]; // pack the reminder                together                }                        
Scissoring Box and Synchronization
 
     FIG. 11   a  is a block diagram illustrating a Scissoring Box origin, according to an embodiment of the present invention. The Span Generator  101  comprises a Scissoring Box module  107  for providing scissoring by a view-port, rotated relative to the x and y axes by an angle with tangent 0, 1, ½ and ⅓ (hereinafter also referred to as tangent 0, 1, 2, 3, respectively). The vertical coordinate y 0  of the upper-left corner of the rotated Scissoring Box is 0, and the horizontal coordinate x 1  of the lower-left corner is also 0. Optionally, the Scissoring Box can be used in an optional embodiment of the present invention having an over-sampling scheme. 
   The Scissoring Box has its origin specified by four points. The coordinates of the points are calculated by the driver (i.e. the software controlling the graphics chip) and stored in registers. The y coordinate of the upper corner is y 0 =0. The Scissoring Box device performs calculation of the initial Scissoring Box coordinates for the first span. After that, the Scissoring Box device calculates up to eight Scissoring Box coordinates per clock cycle for current spans. 
     FIG. 11   b  is a block diagram illustrating a Scissoring Box, according to an embodiment of the present invention. The device to draw the Scissoring Box generates spans between two edges of the Scissoring Box. Two parts of the Scissoring Box generate both edges using the information about starting values of x and y coordinates, y coordinates of corners and rotation angle tangent: 
                                           void ScissoringBox (            SHORT x0,  //starting left x            SHORT x1,  //starting   right x            SHORT y,  //starting y (Ymin)            SHORT y0, //y coordinate for left corner            SHORT y1, //y coordinate for right corner            SHORT y2, //ending y (Ymax)            char t){ //2-bit tangent expression            char cnt0 = t, cnt1 = t;            while (y &lt; y2) {             bool m0 = y &gt;= y0;             x0 += (t)? ((m0)? t : (cnt0)? 0 : −1) : 0;             cnt0 = (m0)? t : (cnt0)? cnt0 − 1 : cnt0;             bool m1 = y &lt; y1;             x1 += (t)? ((m1)? t : (cnt1)? 0 : −1) : 0;             cnt1 = (m1)? t : (cnt1)? cnt1 − 1 : cnt1;             }            }                        
The pair of the coordinates x 0 , x 1  is then sorted among the edge coordinates by Edge Generator  103 .
 
Sorter
 
   As illustrated in  FIG. 7 , a Sorter  104  is a four-input tree compare/multiplex hardware device, three inputs of which are coupled to outputs of three Edge Generators  103  operating within the same clock cycle, and one input of which is coupled to an output of the Sorter  104  operating in the previous clock cycle. In an embodiment comprising four groups of Edge Generators  103  there are four Sorters  104 . Each Edge Generator  103  delivers the direction of a half-plane (left or right) as a tag for the x coordinate value. A Sorter  104  compares x values for edges of different types separately. 
                                                         typedef struct   { //the output of an EG             int x,   //the position             bool uf, ov;   //beyond the bounding box             bool dir;   //left (0) or right (1)                  } edge_out;           class temp_span {           public:             int x0, x1; //left and right             bool uf0, ov0;// left beyond the bounding box             bool uf1, ov1;// right beyond the bounding box             temp_span ( ) :               x0 = 0, x1 = 0,               uf0 = false, ov0 = false,               uf1 = false, ov1 = false { };             temp_span (edge_out ed) : temp_span ( ) {               if (ed. dir){// if the edge is right, then it is the           maximal x                 x1 = ed. x;                 uf1 = ed. uf;                 ov1 = ed. ov;                 }               else   {// if the edge is left , then it is the           minimal x                 x0 = ed. x;                 uf0 = ed. uf;                 ov0 = ed. ov;                 }               };             };           temp_span sort_two (             temp_span s0,             temp_span s1             ) {             temp_span result;             bool x0m = s0. uf0 ∥ s1. ov0 ∥ // compare flags               (!s1. uf0 &amp;&amp; !s0. ov0 &amp;&amp; s0. x0 &lt; s1. x0); // and           values             bool x1m = s0. ov1 ∥ s1. uf1 ∥               (!s1. ov1 &amp;&amp; !s0. uf1 &amp;&amp; s0. x1 &gt;= s1. x1);             result. x0 = (x0m)? s1. x0 : s0. x0; // max of left             result. uf0 = (x0m)? s1. uf0 : s0. uf0;             result. ov0 = (x0m)? s1. ov0 : s0. ov0;             result. x1 = (x1m)? s1. x1 : s0. x1; // min of           right             result. uf1 = (x1m)? s1. uf1 : s0. uf1;             result. ov1 = (x1m)? s1. ov1 : s0. ov1;             return result;             }           temp_span sorter {             temp_span s0, //The output of the previous Sorter             edge_out  x1, //The first EG output             edge_out  x2, //The second EG output             edge_out  x3 //The third EG output             ) {             temp_span s1 (x1), s2 (x2), s3 (x3);             return sort_two (               sort_two (s0, s1),               sort_two (s2, s3)               );             }                        
Span Buffer Interface
 
   The Span Buffer interface (also known as the Output Interface  106  shown in  FIG. 7 ) converts the last Sorter output to absolute coordinates (note that the values are bounding box relative from the Loaders  102  through the Sorters  104 ) and packs them into the Span Buffer. 
   At this point of the span generation process, the computed values comprise the output of the last Sorter s3 and the bypassed outputs of the three other Sorters s0, s1 and s2. Also available are the current y coordinate, the x min  and X max  parameters of the bounding box, and k=1, 2, 4 representing the number of Edge Generators  103  computing spans for the same functional. Also note that the Sorters  104  are doubled, since at the lowest rate there are two spans generated per clock cycle, and therefore two spans are processed per clock cycle in parallel. 
   
     
       
             
             
           
             
             
             
           
             
             
           
         
             
                 
                 
             
           
           
             
                 
               bool wf;    //wire-frame mode wf == true 
             
             
                 
               bool update = true; //when a new triangle starts SB should 
             
             
                 
               get new y 
             
             
                 
               SHORT xMax, xMin; 
             
             
                 
               SHORT y;    //from the current y counter 
             
             
                 
               SHORT w = xMax − xMin;    // The real 
             
             
                 
               bounding box size 
             
             
                 
               typedef struct { 
             
           
        
         
             
                 
               x0, x1; 
               // the values −1 and −2 are reserved for 
             
             
                 
                 
               // uf and ov accordingly. 
             
             
                 
               } span; 
             
           
        
         
             
                 
               SHORT sb_cnt = 0; //the counter of position in SB row 
             
             
                 
               span spare_buffer [16]; 
             
             
                 
               void WriteNextToSB ( 
             
             
                 
                 span sp, //span to write 
             
             
                 
                 SHORT pos, //position in the SB row 
             
             
                 
                 bool next //next row 
             
             
                 
                 ); 
             
             
                 
               void move_sb_cnt ( ) { 
             
             
                 
                 sb_cnt ++; 
             
             
                 
                 if (sb_cnt &gt;= 8) { 
             
             
                 
                  Span_Buffer. Write (       // see TG doc 
             
             
                 
               for description 
             
             
                 
                   spare_buffer, 
             
             
                 
                   y &amp; (0xfffffff0 ∥ wf &lt;&lt; 3),  // y is aligned 
             
             
                 
                   update, // update y if necessary 
             
             
                 
                   wf,   // wire-frame 
             
             
                 
                   update); 
             
             
                 
                  update = false; 
             
             
                 
                  sb_cnt = 0; 
             
             
                 
                 } 
             
             
                 
               } 
             
             
                 
               void sb_interface ( 
             
             
                 
                 temp_span s [8], //two first - from the first level 
             
             
                 
               Sorter, 
             
             
                 
                        // two next - from second level, etc. 
             
             
                 
                 SHORT  y,  //from the y counter 
             
             
                 
                 SHORT  xmin, //from the input 
             
             
                 
                 SHORT  xmax, //from the input 
             
             
                 
                 SHORT  k //from the input 
             
             
                 
                 ) { 
             
             
                 
                 int j; 
             
             
                 
                 span sp [8]; //temporary spans 
             
             
                 
                 //actually the following is performed at Sorters outputs 
             
             
                 
                 for (j = 0; j &lt; 8; j ++)     { 
             
             
                 
                  sp [j]. x0 = 
             
             
                 
                   (s [j]. ov0)? MAX_INT : 
             
             
                 
                   (s [j]. uf0)? −1 : 
             
             
                 
                   (s [j]. x0 &gt; w)? MAX_INT : s [j]. x0 + xMin; 
             
             
                 
                  sp [j]. x1 = 
             
             
                 
                   (s [j]. ov1)? MAX_INT : 
             
             
                 
                   (s [j]. uf1)? −1 : 
             
             
                 
                   (s [j]. x1 &gt; w)? MAX_INT : s [j]. x1 + xMin; 
             
             
                 
                  } 
             
             
                 
                 if (update) { 
             
             
                 
                  sb_cnt = y &amp; (wf)? 0x7 : 0xf; 
             
             
                 
                  for (j = 0; j &lt; 16) 
             
             
                 
                   spare_buffer [j]. x0 = spare_buffer [j]. x1 = 0; 
             
             
                 
                  } 
             
             
                 
                 if (wf) { 
             
             
                 
                   bool empty [4]; //empty flags for all 4 spans of the 
             
             
                 
                         // internal triangle 
             
             
                 
                   for (j = 0; j &lt; 4; j ++) { 
             
             
                 
                    empty [j] = 
             
             
                 
                     s [j + 4]. x0 == MAX_INT ∥ 
             
             
                 
                     s [j + 4]. x1 == −1 ∥ 
             
             
                 
                     s [j + 4]. x0 &gt; s [j + 4]. x1; 
             
             
                 
                    spare_buffer [sb_cnt + j ]. x0 = sp [j]. x0; 
             
             
                 
                    if (empty [j]) { 
             
             
                 
                     spare_buffer [sb_cnt + j ]. x1 = sp [j ]. 
             
             
                 
               x1; 
             
             
                 
                     spare_buffer [sb_cnt + j + 8]. x0 = MAX_INT; 
             
             
                 
                     spare_buffer [sb_cnt + j + 8]. x1 = −1; 
             
             
                 
                     } 
             
             
                 
                    else { 
             
             
                 
                     spare_buffer [sb_cnt + j ]. x1 = sp [j + 4]. 
             
             
                 
               x0; 
             
             
                 
                     spare_buffer [sb_cnt + j + 8]. x0 = sp [j + 4]. 
             
             
                 
               x1; 
             
             
                 
                     spare_buffer [sb_cnt + j + 8]. x1 = sp [j ]. 
             
             
                 
               x1; 
             
             
                 
                     } 
             
             
                 
                   move_sb_cnt ( ); 
             
             
                 
                   } 
             
             
                 
                   sb_cnt = (sb_cnt + 4); 
             
             
                 
                   return; 
             
             
                 
                   } 
             
             
                 
                  for (j = (k − 1) * 2; j &lt; k * 2; j ++) { 
             
             
                 
                   if (k == 2 &amp;&amp; j == 4)    // when k == 2 we 
             
             
                 
               use first and third 
             
             
                 
                     j == 6;    // sorters outputs 
             
             
                 
                   spare_buffer [sb_cnt] = sp [j]; 
             
             
                 
                   move_sb_cnt ( ); 
             
             
                 
                   } 
             
             
                 
                  } 
             
             
                 
                 
             
           
        
       
     
   
   Foregoing described embodiments of the invention are provided as illustrations and descriptions. They are not intended to limit the invention to precise form described. In particular, it is contemplated that functional implementation of invention described herein may be implemented equivalently in hardware, software, firmware, and/or other available functional components or building blocks, and that networks may be wired, wireless, or a combination of wired and wireless. The pseudo-code fragments represent high-level implementation examples and are intended to illustrate one way of implementing functionalities described herein. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of invention not be limited by this Detailed Description, but rather by Claims following.