Abstract:
The present invention discloses a pixel structure, a TFT (Thin Film Transistor) array substrate, and a liquid crystal display panel, and the pixel structure is optimized on the base of the existing FFS (Fringe Field Switching) pixel, the IPS (In Plane Switching) and FFS structures are integrated for enhancing a lateral drive electric field of liquid crystal, the refresh rate is improved and the power consumption is reduced. The pixel structure is formed on a substrate and the pixel structure includes: a first electrode and a second electrode insulated from each other and located on different layers; and a third electrode, the first electrode and the third electrode are being on different layers and applied a same potential, wherein electric fields parallel to the substrate are respectively generated between the first electrode and the second electrode and between the third electrode and the second electrode.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of priority to Chinese patent application number 201310170051.4, entitled “PIXEL STRUCTURE, TFT ARRAY SUBSTRATE, AND LIQUID CRYSTAL DISPLAY PANEL”, filed with the Chinese Patent Office on May 9, 2013, the contents of which is incorporated herein by reference in its entirety. 
       TECHNICAL FIELD 
       [0002]    The present invention relates to the field of display and particularly to a pixel structure, a TFT (Thin Film Transistor) array substrate, and a liquid crystal display panel. 
       BACKGROUND OF THE INVENTION 
       [0003]    A liquid crystal display panel is one of currently predominant display panels. The display modes generally include a Twisted Nematic (TN) mode, a Vertical Alignment (VA) mode, an In Plane Switching (IPS) mode, a Fringe Field Switching (FFS) mode, etc., wherein the IPS/FFS mode liquid crystal display panels have a wide range of applications due to their superior wide viewing angle and other characteristics. 
         [0004]    The existing FFS mode liquid crystal display panel typically includes a color filter substrate and a TFT array substrate disposed opposite to each other, and a liquid crystal layer disposed between them.  FIG. 1  is a schematic structural top view of an FFS mode TFT array substrate in the prior art. As shown in  FIG. 1 , the FFS mode TFT array substrate in the prior art includes a substrate  100  and a pixel array disposed on the substrate  100 . The pixel array includes a plurality of scan lines  101 ; a plurality of data lines  102 , wherein the data lines  102  and the scan lines  101  intersect each other and are insulated from each other; TFTs  103  at the intersections of the scan lines  101  and the data lines  102 ; and a pixel structure disposed in a pixel area defined by adjacent scan lines  101  and adjacent data lines  102 . Reference can be made to  FIG. 1  and  FIG. 2   a  for a specific structure of the pixel structure, where  FIG. 2   a  is a sectional view along A-A′ in FIG.  1 . As shown in  FIG. 1  and  FIG. 2   a , the pixel structure includes a plurality of strip-shaped pixel electrodes  104 , a sheet-shaped common electrode  105  and an insulating layer  106  disposed between the pixel electrodes  104  and the common electrode  105  to insulate the pixel electrodes  104  from the common electrode  105 ; and an electric field parallel to the substrate  100  is generated between the pixel electrodes  104  and the common electrode  105 . Of course, alternatively, the pixel electrode  104  can be sheet-shaped and located under the insulating layer  106 , and the common electrodes  105  may be strip-shaped and located above the insulating layer  106 ; or both the pixel electrodes  104  and the common electrodes  105  may be strip-shaped and arranged alternately (as shown in  FIG. 2   b ). 
         [0005]    The lateral electric field Ex in the FFS mode pixel in the prior art is weak, therefore, in order to achieve the same display effect, the power consumption is increased and the refresh rate is decreased. The Chinese Patent Application No. CN201120313955.4 discloses a technology to enhance the lateral electric field by modifying the height of the pixel, etc., however the manufacturing process is complex and the cost is high. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    Accordingly, in order to solve at least one of the technical problems of weak lateral electric field Ex in the IPS/FFS mode pixel, high power consumption, complex manufacturing process, high cost and low refresh rate, the present invention provides a pixel structure formed on a substrate, the pixel structure including: a first electrode and a second electrode insulated from each other and located on different layers; and a third electrode, the first electrode and the third electrode are being on different layers and applied a same potential, wherein electric fields parallel to the substrate are respectively generated between the first electrode and the second electrode and between the third electrode and the second electrode. 
         [0007]    An embodiment of the present invention further provides a TFT array substrate including a pixel array, wherein each pixel includes a pixel structure, the pixel structure includes: a first electrode and a second electrode insulated from each other and located on different layers; and a third electrode, the first electrode and the third electrode are being on different layers and applied a same potential; wherein electric fields parallel to the substrate are respectively generated between the first electrode and the second electrode and between the third electrode and the second electrode. 
         [0008]    An embodiment of the present invention further provides a liquid crystal display panel including a TFT array substrate, a color filter substrate disposed in opposition to the TFT array substrate, and a liquid crystal layer disposed between the TFT array substrate and the color filter substrate; wherein the TFT array substrate includes a pixel array, each pixel includes a pixel structure, the pixel structure includes: a first electrode and a second electrode insulated from each other and located on different layers; and a third electrode, the first electrode and the third electrode are being on different layers and applied a same potential; wherein electric fields parallel to the substrate are respectively generated between the first electrode and the second electrode and between the third electrode and the second electrode. 
         [0009]    An embodiment of the present invention further provides a liquid crystal display device including the foregoing liquid crystal display panel. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a schematic structural top view of an FFS mode TFT array substrate in the prior art; 
           [0011]      FIG. 2   a  is a sectional view along A-A′ in  FIG. 1 ; 
           [0012]      FIG. 2   b  is another sectional view along A-A′ in  FIG. 1 ; 
           [0013]      FIG. 3  is a schematic structural sectional view of a liquid crystal display panel according to a first embodiment of the present invention; 
           [0014]      FIG. 4  is a schematic structural top view of a TFT array substrate according to a second embodiment of the present invention; 
           [0015]      FIG. 5  is a first sectional view along B-B′ in  FIG. 4 ; 
           [0016]      FIG. 6  is a second sectional view along B-B′ in  FIG. 4 ; 
           [0017]      FIG. 7  is a third sectional view along B-B′ in  FIG. 4 ; 
           [0018]      FIG. 8  is a schematic structural top view of a pixel structure according to a fourth embodiment of the present invention; 
           [0019]      FIGS. 9   a,    9   b,  and  9   c  are first sectional views along C-C′ in  FIG. 8 ; 
           [0020]      FIG. 10  is a second sectional view along C-C′ in  FIG. 8 ; 
           [0021]      FIG. 11  is a third sectional view along C-C′ in  FIG. 8 ; 
           [0022]      FIG. 12  is a fourth sectional view along C-C′ in  FIG. 8 ; 
           [0023]      FIG. 13  is a fifth sectional view along C-C′ in  FIG. 8 ; 
           [0024]      FIG. 14  is a schematic comparative diagram between the distribution of a lateral electric field of the pixel structure illustrated in  FIG. 5  and the distribution of a lateral electric field of the pixel structure illustrated in  FIG. 2   b;  and 
           [0025]      FIG. 15  is a schematic comparative diagram between the distribution of a lateral electric field of the pixel structures illustrated in  FIGS. 10 and 11  and the distribution of a lateral electric field of the pixel structure illustrated in  FIG. 2   a.    
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0026]    A main idea of the present invention is to optimize the pixel structure on the base of the existing FFS pixel, to integrate the IPS and FFS structures, to enhance a lateral driving electric field of liquid crystals, to improve a refresh rate, simplify the manufacturing process, reduce the manufacturing cost and to reduce the power consumption. 
       First Embodiment 
       [0027]    A schematic structural sectional view of a liquid crystal display panel according to the first embodiment of the present invention is illustrated in  FIG. 3 . The liquid crystal display panel includes a TFT array substrate  11 , a color filter substrate  12  disposed opposite to the TFT array substrate  11 , and a liquid crystal layer  13  disposed between the TFT array substrate  11  and the color filter substrate  12 . 
         [0028]    The first embodiment of the present invention further provides a liquid crystal display device including the liquid crystal display panel illustrated in  FIG. 3 . 
         [0029]    The TFT array substrate  11  in the first embodiment of the present invention may employ a TFT array substrate to be described in a second embodiment of the present invention below and the pixel structures included in the TFT array substrate  11  in the first embodiment of the present invention may employ pixel structures to be described in a third, a fourth, a fifth and a sixth embodiments of the present invention. 
       Second Embodiment 
       [0030]    A schematic structural top view of a TFT array substrate according to the second embodiment of the present invention is illustrated in  FIG. 4 . The TFT array substrate  11  includes a substrate  110  and a pixel array on the substrate  110 . The pixel array includes a plurality of scan lines  111 , a plurality of data lines  112  intersecting with the scan lines  111  and insulated from the scan lines  111 , TFTs  113  at the intersections of the scan lines  111  and the data lines  112 , and a pixel structure disposed in a pixel area defined by adjacent scan lines  111  and adjacent data lines  112 . The gate of the TFT  113  is electrically connected to the scan line  111 , the source of the TFT  113  is electrically connected to the data line  112 , and the drain of the TFT  113  is electrically connected to a pixel electrode in the pixel structure. 
         [0031]    Reference can be made to  FIG. 4  and  FIG. 5  for a specific structure of the pixel structure, where  FIG. 5  is a sectional view along B-B′ in  FIG. 4 . As shown in  FIG. 4  and  FIG. 5 , the pixel structure includes a sheet-shaped first electrode (i.e., a pixel electrode)  115  and strip-shaped second electrodes (i.e., common electrodes)  117  (typically more than one), both of which are insulated from each other and being on different layers; and a first insulating layer  116  located between the first electrode  115  and the second electrodes  117  and insulating the first electrode  115  from the second electrodes  117 . The sheet-shaped first electrode  115  is located under the first insulating layer  116 , and the strip-shaped second electrodes  117  are located above the first insulating layer  116 . An electric field parallel to the substrate  110  is generated between the first electrode  115  and the second electrodes  117 , so that liquid crystal molecules in a liquid crystal layer  13  are rotated in a plane parallel to the substrate  110 . It shall be noted that in the present application, the concept of “parallel” will not be limited to being absolutely parallel, but shall be extended as appropriate to being substantially parallel. The electric field generated between the first electrode  115  and the second electrodes  117  is typically not absolutely parallel to the substrate  110 , but includes a horizontal electric field component and a vertical electric field component. 
         [0032]    The pixel structure further includes strip-shaped third electrodes (i.e., pixel electrodes)  114  (typically more than one), the first electrode  115  and the strip-shaped third electrodes (i.e., pixel electrodes)  114  are being on different layers and applied a same potential. The strip-shaped third electrodes (i.e., pixel electrodes)  114  are located above the first insulating layer  116 . As shown in  FIG. 4 , the strip-shaped third electrodes  114  and the strip-shaped second electrodes  117  are located on the same layer, insulated from each other and arranged alternately. The third electrodes  114  are typically electrically connected to the drains of TFTs  113  through via holes (not illustrated) throughout the first insulating layer  116 . An electric field parallel to the substrate  110  is generated between the third electrodes  114  and the second electrodes  117 . That is, the electric fields parallel to the substrate  110  are respectively generated between the first electrode  115  and the second electrodes  117  and between the third electrodes  114  and the second electrodes  117 . The second electrodes  117  and the third electrodes  114  are located above the first electrode  115 . 
         [0033]    Moreover, in an appropriate variant of this embodiment, both the first electrode  115  and the third electrodes  114  may be common electrodes, and the second electrodes  117  may be pixel electrodes. The first electrode  115  and the third electrodes  114  may be exchanged in location. 
         [0034]    A schematic comparative diagram between the distribution of a lateral electric field of the pixel structure illustrated in  FIG. 5  according to the second embodiment and the distribution of a lateral electric field of the pixel structure illustrated in  FIG. 2   b  in the prior art is illustrated in  FIG. 14 . In  FIG. 14 , the upper diagram is the distribution of a lateral electric field of the pixel structure illustrated in  FIG. 5  according to the second embodiment, and the lower diagram is the distribution of a lateral electric field of the pixel structure illustrated in  FIG. 2   b  in the prior art. As shown in comparison of the upper and lower diagrams in  FIG. 14 , the peak of the lateral electric field of the pixel structure according to the second embodiment is about 1.2 e −16 , and the peak of the lateral electric field of the pixel structure in the prior art is about 0.7*0.5 e −16 =0.35 e −16 , the peak of this embodiment is about 34 times as great as that in the prior art, thus the lateral electric field of the pixel structure according to the second embodiment has been greatly enhanced compared to the lateral electric field of the pixel structure in the prior art. 
       Third Embodiment 
       [0035]    A top view of a pixel structure according to the third embodiment of the present invention is illustrated in  FIG. 4 , and a sectional view thereof along B-B′ can be further illustrated in  FIG. 6 . As shown in  FIG. 4  and  FIG. 6 , the pixel structure includes a sheet-shaped first electrode (i.e., a pixel electrode)  115  and strip-shaped second electrodes (i.e., common electrodes)  117  (typically more than one) insulated from the first electrode  115  and located on a different layer from the first electrode  115 ; and a first insulating layer  116  located between the first electrode  115  and the second electrodes  117  for insulating the first electrode  115  from the second electrodes  117 . The sheet-shaped first electrode  115  is located under the first insulating layer  116 , and the strip-shaped second electrodes  117  are located above the first insulating layer  116 . An electric field parallel to the substrate  110  is generated between the first electrode  115  and the second electrodes  117 , so that liquid crystal molecules in a liquid crystal layer  13  are rotated in a plane parallel to the substrate  110 . It shall be noted that in the present application, the concept of “parallel” will not be limited to being absolutely parallel, but shall be extended as appropriate to being substantially parallel. The electric field generated between the first electrode  115  and the second electrodes  117  is typically not absolutely parallel to the substrate  110 , but includes a horizontal electric field component and a vertical electric field component. 
         [0036]    The pixel structure further includes strip-shaped third electrodes (i.e., pixel electrodes)  114  (typically more than one), the first electrode  115  and the strip-shaped third electrodes (i.e., pixel electrodes)  114  are being on different layers and applied a same potential. The strip-shaped third electrodes (i.e., pixel electrodes)  114  are located above the first insulating layer  116 . In the  FIG. 6 , a second insulating layer  118  is disposed between the strip-shaped third electrodes  114  and the strip-shaped second electrodes  117  which are located on different layers and arranged alternately. The third electrodes  114  are typically electrically connected to the drains of TFTs  113  through via holes (not illustrated)throughout the first insulating layer  116  and the second insulating layer  118 . An electric field parallel to the substrate  110  is generated between the third electrodes  114  and the second electrodes  117 . That is, the electric fields parallel to the substrate  110  are respectively generated between the first electrode  115  and the second electrodes  117  and between the third electrodes  114  and the second electrodes  117 . The second electrodes  117  and the third electrodes  114  are located above the first electrode  115 . 
         [0037]    In  FIG. 6 , an example is illustrated, in which the third electrodes  114  are located above the second insulating layer  118 , the second electrodes  117  are located between the second insulating layer  118  and the first insulating layer  116 , and the first electrode  115  is located under the first insulating layer  116 , that is, the third electrodes  114  and the first electrode  115  are located respectively on two sides of the second electrodes  117 , but alternatively, the second electrodes  117  are located above the second insulating layer  118 , the third electrodes  114  may be located between the second insulating layer  118  and the first insulating layer  116 , and the first electrode  115  may be located under the first insulating layer  116 , that is, both the third electrodes  114  and the first electrode  115  may be located under the second electrodes  117  (as illustrated in  FIG. 7 ). 
         [0038]    Moreover, in an appropriate variant of this embodiment, both the first electrode  115  and the third electrodes  114  may be common electrodes, and the second electrodes  117  may be pixel electrodes. The first electrode  115  and the third electrodes  114  may be exchanged in location. 
       Fourth Embodiment 
       [0039]    A schematic structural top view of a pixel structure according to the fourth embodiment of the present invention is illustrated in  FIG. 8 , and a schematic structural sectional view thereof along C-C′ is illustrated in  FIG. 9   a,    FIG. 9   b  and  FIG. 9   c.    
         [0040]    As shown in  FIG. 8  and  FIG. 9   a,  the pixel structure includes strip-shaped first electrodes (i.e., pixel electrodes)  115  (typically more than one) and strip-shaped second electrodes (i.e., common electrodes)  117  (typically more than one) insulated from the first electrodes  115  and located on a different layer from the first electrodes  115 ; and the first electrodes  115  are located on one side (i.e., underside) of a first insulating layer  116 , and the second electrodes  117  are located on the other side (i.e., upper side) of the first insulating layer  116 ; and an electric field parallel to the substrate  110  is generated between the first electrodes  115  and the second electrodes  117 , so that liquid crystal molecules in a liquid crystal layer  13  are rotated in a plane parallel to the substrate  110 . It shall be noted that in the present application, the concept of “parallel” will not be limited to being absolutely parallel, but shall be extended as appropriate to being substantially parallel. The electric field generated between the first electrodes  115  and the second electrodes  117  is typically not absolutely parallel to the substrate  110 , but includes a horizontal electric field component and a vertical electric field component. 
         [0041]    The pixel structure further includes strip-shaped third electrodes (i.e., pixel electrodes)  114  (typically more than one), the first electrode  115  and the strip-shaped third electrodes (i.e., pixel electrodes)  114  are being on different layers and applied a same potential. In the  FIG. 9   a , the strip-shaped third electrodes  114  are located on the one side (i.e., upper side) of the first insulating layer  116 , said one side of the first insulating layer  116  is opposite to the first electrodes  115 ; a second insulating layer  118  is disposed between the strip-shaped third electrodes  114  and the strip-shaped second electrodes  117  which are located on different layers and arranged alternately; and the strip-shaped first electrodes  115  and the strip-shaped second electrodes  117  are arranged alternately. The strip-shaped first electrodes  115  and the strip-shaped third electrodes  114  are preferably disposed opposite to each other. The third electrodes  114  are located above the second insulating layer  118 , the second electrodes  117  are located between the second insulating layer  118  and the first insulating layer  116 , and the first electrodes  115  are located under the first insulating layer  116 . 
         [0042]    The third electrodes  114  are typically electrically connected to the drains of TFTs  113  through via holes (not illustrated) throughout the first insulating layer  116  and the second insulating layer  118 . An electric field parallel to the substrate  110  is generated between the third electrodes  114  and the second electrodes  117 . That is, the electric fields parallel to the substrate  110  are respectively generated between the first electrodes  115  and the second electrodes  117  and between the third electrodes  114  and the second electrodes  117 . 
         [0043]    Moreover, in an appropriate variant of this embodiment, both the first electrodes  115  and the third electrodes  114  may be common electrodes, and the second electrodes  117  may be pixel electrodes. The first electrodes  115  and the third electrodes  114  may be exchanged in location. In the fourth embodiment, an example is illustrated in which the second electrodes  117  and the third electrodes  114  are located above the first insulating layer  116 , and the first electrodes  115  are located under the first insulating layer  116 , but alternatively, the second electrodes  117  and the third electrodes  114  may be located under the first insulating layer  116 , and the first electrodes  115  may be located above the first insulating layer  116  (as illustrated in  FIG. 9   b ), or in other embodiments, the second electrodes  117  may be located above the second insulating layer  118 , the third electrodes  114  may be located between the second insulating layer  118  and the first insulating layer  116 , and the first electrodes  115  may be located under the first insulating layer  116  (as illustrated in  FIG. 9   c ). 
       Fifth Embodiment 
       [0044]    A top view of a pixel structure according to the fifth embodiment of the present invention is illustrated in  FIG. 8 , and a sectional view thereof along C-C′ is illustrated in  FIG. 10 . As shown in  FIG. 8  and  FIG. 10 , the pixel structure includes strip-shaped first electrodes (i.e., pixel electrodes)  115  (typically more than one) and strip-shaped second electrodes (i.e., common electrodes)  117  (typically more than one) insulated from the first electrodes  115  and located on a different layer from the first electrodes  115 ; a first insulating layer  116  and a second insulating layer  118 ; and strip-shaped third electrodes (i.e., pixel electrodes)  114  (typically more than one), the first electrode  115  and the strip-shaped third electrodes (i.e., pixel electrodes)  114  are being on different layers and applied a same potential. The first electrodes  115  are located between the first insulating layer  116  and the second insulating layer  118 , and the second electrodes  117  and the third electrodes  114  are located respectively on the outsides of the first insulating layer  116  and the second insulating layer  118 . 
         [0045]    An electric field parallel to the substrate  110  is generated between the first electrodes  115  and the second electrodes  117 , so that liquid crystal molecules in a liquid crystal layer  13  are rotated in a plane parallel to the substrate  110 . It shall be noted that in the present application, the concept of “parallel” will not be limited to being absolutely parallel, but shall be extended as appropriate to being substantially parallel. The electric field generated between the first electrodes  115  and the second electrodes  117  is typically not absolutely parallel to the substrate  110 , but includes a horizontal electric field component and a vertical electric field component. 
         [0046]    In the  FIG. 10 , the second insulating layer  118  is disposed between the strip-shaped third electrodes  114  and the strip-shaped first electrodes  115  which are located on different layers and arranged alternately, and preferably the third electrodes  114  and the first electrodes  115  are disposed opposite to each other. That is, the third electrodes  114  are located above the second insulating layer  118 , the first electrodes  115  are located between the second insulating layer  118  and the first insulating layer  116 , and the second electrodes  117  are located under the first insulating layer  116 . The third electrodes  114  are typically electrically connected to the drains of TFTs  113  through via holes (not illustrated)throughout the first insulating layer  116  and the second insulating layer  118 . An electric field parallel to the substrate  110  is generated between the third electrodes  114  and the second electrodes  117 . That is, the electric fields parallel to the substrate  110  are generated between the first electrodes  115  and the second electrodes  117  and between the third electrodes  114  and the second electrodes  117 , respectively. The first electrodes  115  and the third electrodes  114  are located above the second electrodes  117 . 
         [0047]    In  FIG. 10 , an example is illustrated in which the third electrodes  114  are located above the second insulating layer  118 , the first electrodes  115  are located between the second insulating layer  118  and the first insulating layer  116 , and the second electrodes  117  are located under the first insulating layer  116 , but alternatively, the second electrodes  117  may be located above the first insulating layer  116 , the first electrodes  115  may be located between the second insulating layer  118  and the first insulating layer  116 , and the third electrodes  114  may be located under the second insulating layer  118  (as illustrated in  FIG. 11 ). 
         [0048]    Moreover, in an appropriate variant of this embodiment, both the first electrodes  115  and the third electrodes  114  may be common electrodes, and the second electrodes  117  may be pixel electrodes. The first electrodes  115  and the third electrodes  114  may be exchanged in location. 
         [0049]    A schematic comparative diagram between the distribution of the lateral electric field of the pixel structure illustrated in  FIG. 10  and  FIG. 11  according to the fifth embodiment and the distribution of the lateral electric field of the pixel structure illustrated in  FIG. 2   a  in the prior art is illustrated in  FIG. 15 . In  FIG. 15 , the upper diagram is the distribution of the lateral electric field of the pixel structure illustrated in  FIG. 10  and  FIG. 11  according to the fifth embodiment, and the lower diagram is the distribution of the lateral electric field of the pixel structure illustrated in  FIG. 2   a  in the prior art. As shown in comparison of the upper and lower diagrams in  FIG. 15 , the peak of the lateral electric field of the pixel structure according to the fifth embodiment is about 1.0 e −16 , and the peak of the lateral electric field of the pixel structure in the prior art is about 0.5*0.5 e −16 =0.25 e −16 , the peak of this embodiment is about 4 times as great as that in the prior art, thus the lateral electric field of the pixel structure according to the fifth embodiment has been greatly enhanced compared to the lateral electric field of the pixel structure in the prior art. 
       Sixth Embodiment 
       [0050]    A top view of a pixel structure according to the sixth embodiment of the present invention is illustrated in  FIG. 8 , and a sectional view thereof along C-C′ can be further illustrated in  FIG. 12 . As shown in  FIG. 8  and  FIG. 12 , the pixel structure includes strip-shaped first electrodes (i.e., pixel electrodes)  115  (typically more than one) and strip-shaped second electrodes (i.e., common electrodes)  117  (typically more than one) insulated from the first electrodes  115  and located on a different layer from the first electrodes  115 ; and a first insulating layer  116  located between the first electrodes  115  and the second electrodes  117  and insulating the first electrodes  115  from the second electrodes  117 . An electric field parallel to the substrate  110  is generated between the first electrodes  115  and the second electrodes  117 , so that liquid crystal molecules in a liquid crystal layer  13  are rotated in a plane parallel to the substrate  110 . It shall be noted that in the present application, the concept of “parallel” will not be limited to being absolutely parallel, but shall be extended as appropriate to being substantially parallel. The electric field generated between the first electrodes  115  and the second electrodes  117  is typically not absolutely parallel to the substrate  110 , but includes a horizontal electric field component and a vertical electric field component. 
         [0051]    The pixel structure further includes strip-shaped third electrodes (i.e., pixel electrodes)  114  (typically more than one), the first electrode  115  and the strip-shaped third electrodes (i.e., pixel electrodes)  114  are being on different layers and applied a same potential. In the  FIG. 12 , the strip-shaped third electrodes  114  and the strip-shaped first electrodes  115  are located on different layers and preferably disposed opposite to each other; the strip-shaped third electrodes  114  and the strip-shaped second electrodes  117  are located on a same layer; the strip-shaped first electrodes  115  and the strip-shaped second electrodes  117  are arranged alternately; and the strip-shaped third electrodes  114  and the strip-shaped second electrodes  117  are arranged alternately. The third electrodes  114  are typically electrically connected to the drains of the TFTs  113  through via holes (not illustrated) throughout the first insulating layer  116 . An electric field parallel to the substrate  110  is generated between the third electrodes  114  and the second electrodes  117 . That is, the electric fields parallel to the substrate  110  are generated between the first electrodes  115  and the second electrodes  117  and between the third electrodes  114  and the second electrodes  117 , respectively. 
         [0052]    In  FIG. 12 , an example is illustrated in which the third electrodes  114  and the second electrodes  117  are located above the first insulating layer  116 , and the first electrodes  115  are located under the first insulating layer  116 , but alternatively, the third electrodes  114  and the second electrodes  117  may be located under the first insulating layer  116 , and the first electrodes  115  may be located above the first insulating layer  116  (as illustrated in  FIG. 13 ). 
         [0053]    Moreover, in an appropriate variant of this embodiment, the first electrodes  115  and the third electrodes  114  may be common electrodes, and the second electrodes  117  may be pixel electrodes. The first electrodes  115  and the third electrodes  114  may be exchanged in location. 
         [0054]    In the embodiments mentioned above, the strip-shape may be a straight strip-shape, a “V” strip-shape, a zigzag strip-shape, etc. 
         [0055]    Evidently those skilled in the art can make various modifications and variations to the present invention without departing from the scope of the present invention. Thus the present invention is also intended to encompass these modifications and variations thereto so long as the modifications and variations come into the scope of the claims appended to the present invention and their equivalents.