Abstract:
NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.

Description:
[0001]    RELATED PATENT APPLICATION  
         [0002]    TSMC98-527, A COMBINED NMOS AND SCR ESD PROTECTION DEVICE title filing date:______, Serial number:______, assigned to a common assignee. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0003]    1. Field of the Invention  
           [0004]    The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to the protection of high voltage NMOS transistors by parasitic silicon controlled rectifiers (SCR) which carry equal currents.  
           [0005]    2. Description of the Related Art  
           [0006]    The protection of integrated circuits from electrostatic discharge (ESD) is a subject which has received a lot of attention from circuit designers because of the serious damage that ESD can wreak as device dimensions are reduced. Workers in the field and inventors have proposed many solutions, many trying to solve the problem of protecting sub-micron devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The main thrust of ESD protection for MOS devices is focused on the use of parasitic npn and pnp bipolar transistors which together form a lateral silicon controlled rectifier (SCR). Unwanted as this SCR normally is, it can safely discharge dangerous ESD voltages as long as its trigger voltage is low enough to protect those MOS devices of which it is a part.  
           [0007]    The following publications discuss lateral SCR structures for ESD protection circuits:  
           [0008]    “Lateral SCR Devices with Low-Voltage High-Current Triggering Characteristics for Output ESD Protection in Submicron CMOS Technology,” Ker, IEEE Transactions On Electron Devices, Vol.45, No.4, April 1999, pp.849-860.  
           [0009]    “Grounded-Gate nMos Transistor Behavior Under CDM ESD Stress Conditions,” Verhaege et al., IEEE Transactions On Electron Devices, Vol.44, No.11, November1997, pp. 1972-1980.  
           [0010]    “Design Methodology and Optimization of Gate-Driven NMOS ESD Protection Circuits in Submicron CMOS Processes,” Chen et al., IEEE Transactions On Electron Devices, Vol.45, No.12, December 1998, pp. 2448-2456.  
           [0011]    “The State of the Art of Electrostatic Discharge Protection: Physics, Technology, Circuits, Design, Simulation, and Scaling,” Voldman, IEEE Journal of Solid-State Circuits, Vol.34, No.9, September 1999, pp.1272-1282.  
           [0012]    “The Mirrored Lateral SCR (MILSCR) as an ESD Protection Structure: Design and Optimization Using 2-D Device Simulation,” Delage et al., IEEE Journal of Solid-State Circuits, Vol.34, No.9, September 1999, pp.1283-1289.  
           [0013]    [0013]FIG. 1 is a cross-sectional schematic of a high voltage protection device layout of the prior art and FIG. 2 is the equivalent circuit. FIG. 1 shows a semiconductor wafer  100  with a p-substrate  102  having two n-wells  104 , and  105 , where n-wells  104  and  105  are NMOS drains. Implanted in n-well  104  are n+ diffusions  106 ,  108 , and p+ diffusion  110  (all connected together via connection  122 ). Implanted into p-substrate  102  are p+ diffusion  112  and n+ diffusion  114  to one side of n-well  106 , and n+ diffusion  116  to the other side of n-well  104 . Diffusions  112 ,  114 , and  116  are all connected to a reference potential  124  (typically ground). NMOS transistor T 1  is formed by n-well  104 , n+ diffusion  114  (source), and gate  118 . NMOS transistor T 2  is formed by n-well  104 , n+ diffusion  116  (source), and gate  120 . SCR 1  consists of parasitic bipolar pnp transistor Q 1  and parasitic bipolar npn transistor Q 2  which are formed by p-substrate  102 , n-well  104  and diffusions  110 , and  114 . SCR 2  consists of parasitic bipolar pnp transistor Q 1  and parasitic bipolar npn transistor Q 3  which are formed by p-substrate  102 , n-well  104  and diffusions  108 , and  116 . Resistors R 1 , R 3 ′ and R 3 ″ are equivalent resistors for the intrinsic resistance of the p-substrate  102  material. Resistors R 2 , and R 4  are equivalent resistors for the intrinsic resistance of the n-well  104  material. Another set of NMOS transistors are arranged in a mirror image around n+ diffusion  116 .  
           [0014]    [0014]FIG. 2, the equivalent circuit of FIG. 1, shows typical parasitic silicon controlled rectifiers SCR 1  and SCR 2 , which are comprised of Q 1 , Q 2 , R 1  and R 2 , and Q 1 , Q 2 , R 3 ′ and R 4 , respectively. Note that in the figures like parts are identified by like numerals. Connected in parallel between connection  122  and reference potential  124  are shown the NMOS transistors T 1  and to T 2  which are protected by the action of the SCRs. Note that SCR 1  sees a different resistance (R 1 ) than SCR  2  (R 1 +R 3 ′, where R 3 ′ is between Nodes A and B). Therefore SCR 2  turns on easier and has to dissipate more current than SCR 1 . The non-uniform current distribution is very undesirable, because it limits the maximum voltage that the ESD protection device can withstand. The number of NMOS transistors is not limited to the two shown but depends on the current capacity desired and may be more than two as indicated in FIG. 1.  
           [0015]    Other related art is described in the following U.S. Patents which propose low voltage lateral SCRs (LVTSCR), modified lateral SCRs (MLSCR), PMOS-trigger lateral SCRs (PTLSCR), NMOS-trigger lateral SCRs (NTLSCR), and modified PTLSCRs and NTLSCRs to control electrostatic discharge:  
           [0016]    U.S. Pat. No. 5,959,820 (Ker et al.) describes a cascode low-voltage triggered SCR and ESD protection circuit.  
           [0017]    U.S. Pat. No. 5,905,288 (Ker) describes an output ESD protection circuit with high-current-triggered lateral SCR.  
           [0018]    U.S. Pat. No. 5,872,379 (Lee) describes a low voltage turn-on SCR for ESD protection.  
           [0019]    U.S. Pat. No. 5,754,381 (Ker) provides a modified PTLSCR and NTLSCR, and bypass diodes for protection of the supply voltage and output pad of an output buffer.  
           [0020]    The trigger voltage is the low snap-back trigger voltage of a short-channel PMOS (NMOS) device.  
           [0021]    U.S. Pat. No. 5,754,380 (Ker et al.) is similar to U.S. Pat. No. 5,754,381 above but without bypass diodes. The invention requires a smaller layout area than conventional CMOS output buffers with ESD protection.  
           [0022]    U.S. Pat. No. 5,745,323 (English et al.) shows several embodiments for protecting semiconductor switching devices by providing a PMOS transistor which turns on when an electrostatic discharge occurs at the output of the circuit.  
           [0023]    U.S. Pat. No. 5,576,557 (Ker et al.) provides ESD protection for sub-micron CMOS devices supplying discharge paths at V dd  and V ss  using two LVTSCRs. In addition a PMOS device is used in conjunction with one LVTSCR and an NMOS device with the other LVTSCR. Inclusion of the PMOS and NMOS devices allows lowering of the trigger voltage to 11-13 Volt.  
           [0024]    U.S. Pat. No. 5,572,394 (Ker et al.) describes a CMOS on-chip four-LVTSCR ESD protection scheme for use in Deep submicron CMOS integrated circuits.  
           [0025]    U.S. Pat. N 0 . 5,455,436 (Cheng) describes an SCR ESD protection circuit with a non-LDD NMOS structure with a lower avalanche breakdown level than the LDD NMOS device of an output buffer.  
           [0026]    It should be noted that none of the above-cited examples of the related art provide a symmetrical layout of components of the ESD device with a resultant uniform distribution of currents in the parasitic SCRs and thus achieving a combination of high  
           [0027]    Human Body Model (HBM) ESD Passing Voltage equal to the machine limit of 8 kVolt and a Machine Model voltage of 800V/850 Volt.  
         SUMMARY OF THE INVENTION  
         [0028]    It is an object of the present invention to provide an ESD device for protecting NMOS high power transistors where the SCR protection device and the NMOS transistors are integrated.  
           [0029]    Another object of the present invention is to provide uniform current distribution in the parasitic SCRs associated with the NMOS transistors to provide increased ESD protection limits for the NMOS circuits.  
           [0030]    A further object of the present invention is to provide HBM ESD Passing Voltage which equals the machine limit of 8,000 Volt.  
           [0031]    A yet further object of the present invention is to provide Machine Model ESD Voltage with a pass/fail range of 800/850 Volt.  
           [0032]    These objects have been achieved by designing the ESD device with its two NMOS transistors and its attendant parasitic SCRs in a completely symmetrical arrangement so that the currents are completely uniform in the components which are symmetrical (such as resistors and parasitic bipolar transistor). This symmetry is achieved specifically by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion insures that the resistance seen by both SCRs is the same, thus insuring that the current through both SCRs is identical, thereby creating identical turn-on conditions for both SCRs. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0033]    [0033]FIG. 1 is a cross-sectional view of NMOS transistors and their associated parasitic SCRs of the prior art.  
         [0034]    [0034]FIG. 2 is an equivalent circuit diagram of FIG. 1.  
         [0035]    [0035]FIG. 3 is a cross-sectional view of NMOS transistors with their associated parasitic SCRs (showing the symmetric layout of parasitic resistors R 1  and R 3 ) of the preferred embodiment of the present invention.  
         [0036]    [0036]FIG. 4 is an equivalent circuit diagram of FIG. 3.  
         [0037]    [0037]FIG. 5 is a block diagram of the method of the invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0038]    We now describe the preferred embodiment of an integrated circuit and a method of fabrication of an electrostatic discharge (ESD) device where the latter is part of high voltage NMOS transistors and where the ESD device, in the form of two parasitic SCRs, is integrated with these NMOS transistors.  
         [0039]    Referring now to FIG. 3, we show the preferred embodiment of the present invention. FIG. 3 is a cross-sectional view of two n-channel metal oxide semiconductor (NMOS) transistors with two parasitic silicon controlled rectifiers (SCR), where the SCRs are created by p+ diffusion  110  in NMOS drain  104 . Similar to FIG. 1, the number of NMOS transistors is not limited to the two NMOS transistors discussed(T 1  and T 2 ). A second set of NMOS transistors can be realized by mirror imaging (around p+ diffusion  113 ) the layout of transistors T 1  and T 2 . FIG. 3 shows two additional NMOS transistors and associated parasitic SCR ESD protection devices (SCR 3 , SCR 4 ) which are duplicated by mirroring around the third p+ diffusion  113 . It is obvious to those skilled in the art that any number of ESD protection devices can be created similarly to meet the current requirements of the circuit. In the figures (FIGS. 1, 2,  3 , and  4 ) like parts are identified by like numerals.  
         [0040]    In FIG. 3, the ESD protection and the high voltage NMOS transistors comprise a semiconductor wafer  100  with a p-substrate  102  with n-well  104  formed in the p-substrate. N-well  104  forms the drain of first and second NMOS transistors T 1  and T 2 .  
         [0041]    First and second n+ diffusions  106 ,  108  are implanted in n-well  104 . Between diffusions  106  and  108  is implanted a first p+ diffusion  108 . Second and third p+ diffusion  112 ,  113  are implanted in p-substrate  102  at opposite sides of n-well  104 . A third n+ diffusion  114  is implanted in the p-substrate between n-well  104  and second p+ diffusion  112 , the third n+ diffusion  114  representing the source of first NMOS transistor T 1 . A fourth n+ diffusion  116  is implanted in the p-substrate between n-well  104  and third p+ diffusion  113 , the fourth n+ diffusion  116  representing the source of the second NMOS transistor T 2 . A first gate  118  formed between n-well  104  and third n+ diffusion  114  represents the gate of first NMOS transistor T 1 . A second gate  120  formed between n-well  104  and fourth n+ diffusion  116  represents the gate of second NMOS transistor T 2 . Diffusions  106 ,  108 , and  110  are connected together by conductive means  122 . Diffusions  112 ,  113 ,  114 , and  116  are tied to a reference potential  124  (typically ground). Note that p+ diffusion  110  provides symmetry for the NMOS transistors, and, more importantly, newly added p+ diffusion  113  provides symmetry for SCR 1  and SCR 2 , by connecting R 3  from the base of Q 3  to reference voltage  124 , thus creating a mirror image with R 1 , and thereby ensuring that the two SCRs conduct the same current.  
         [0042]    The structure as described creates a first parasitic silicon controlled rectifier SCR 1  and a second parasitic silicon controlled rectifier SCR  2 . Still referring to FIG. 3, SCR  1  further comprises:  
         [0043]    a first parasitic pnp bipolar transistor Q 1 , having its emitter, base, and collector formed by first p+ diffusion  110 , n-well  104 , and p-substrate  102 , respectively,  
         [0044]    a first parasitic npn bipolar transistor Q 2 , having its emitter, base, and collector formed by third n+ diffusion  114 , p-substrate  102 , and n-well  104 , respectively,  
         [0045]    a first parasitic resistor R 1  between second p+ diffusion  112  and p-substrate  102 , where R 1  represents the intrinsic resistance of the p-substrate between the base of Q 2  and diffusion  112 ,  
         [0046]    a second parasitic resistor R 2  between first n+ diffusion  106  and n-well  104 . R 2  represents the intrinsic resistance of the n-well between the base of Q 1 /collector of Q 2  and diffusion  106 . SCR 2  further comprises:  
         [0047]    first parasitic pnp bipolar transistor Q 1 , as described above,  
         [0048]    a second parasitic npn bipolar transistor Q 3 , having its emitter, base, and collector formed by fourth n+ diffusion  116 , p-substrate  102 , and n-well  104 , respectively;  
         [0049]    a third parasitic resistor R 3  between third p+ diffusion  113  and p-substrate  102 , where R 3  represents the intrinsic resistance of the p-substrate between the base of Q 3  and diffusion  113 ,  
         [0050]    a fourth parasitic resistor R 4  between second n+ diffusion  108  and n-well  104 . R 4  represents the intrinsic resistance of the n-well between the base of Q 1 /collector of Q 3  and diffusion  108 .  
         [0051]    The benefits of the present invention will be further demonstrated by inspection of FIG. 4, which is the equivalent circuit diagram of FIG. 3. FIG. 4 shows transistors T 1  and T 2  connected between conductive rail  122  and reference potential  124 . SCR 1  and SCR 2  are connected similarly between rails  122  and  124 . FIG. 4 reveals the symmetry of SCR 1  and SCR 2 , where transistor Q 1  is shared between the two SCRs. Resistor R 3  is now connected between Node B and p+ diffusion  113 , whereas in the prior art (see FIG. 2) resistor R 3 ′ was connected between Nodes A and B, and resistor R 3 ″ was connecting the base of transistor Q 3  with the base of its mirror image transistor Q 3 ′. R 3 ′, thus contributed to an uneven current distribution. Note that in FIG. 4 the path from the collector of Q 1  to Q 2  to R 1  to rail  124  is identical to the path from the collector of Q 1  to Q 3  to R 3  to rail  124 . Therefore, the current from Q 1  via Q 2 , R 1 , and  124  is the same as the current from Q 1  via Q 3 , R 3  to rail  124 . In addition to the asymmetry of the prior art just described, there is in FIG. 2 another asymmetry which has been eliminated by the present invention. In FIG. 2 bipolar parasitic transistor Q 3  is connected via parasitic resistor R 3 ″ to the mirror image transistor Q 3 ′. In contrast, in FIG. 4 resistor R 3  is tied to p+ diffusion  113  and therefore uncoupled from the “mirror image resistor R 3 m” which is created when p+ diffusion  113  is the centerline for the mirror image of another set of NMOS transistors and parasitic SCRs. Diffusions  106 ,  108 ,  110 ,  112 ,  113 ,  114 , and  116  are indicated for clarification of FIGS. 2 and 4.  
         [0052]    Because in the prior art (per FIGS. 1 and 2 ): 
           R   1 + R   3 ′&gt; R   1   
         [0053]    SCR 2  turns on easier and has to dissipate more current. In the new device (per FIGS. 3 and 4) the turn-on condition for SCR 1  and SCR 2  is identical because: 
           R   1 = R   3   
         [0054]    i.e., the same amount of current is dissipated by SCR 1  and SCR 2 .  
         [0055]    It follows from the above that the preferred embodiment of the present invention provides these advantages:  
         [0056]    a) The current distribution between the first SCR (SCR 1 ) and the second SCR (SCR 2 ) is uniform.  
         [0057]    b) The turn-on time for both SCRs is the same.  
         [0058]    c) The turn-on conditions for both SCRs are identical.  
         [0059]    Experiments conducted with the circuit of the invention are tabulated in Table 1. They indicate an increase of the Human Body Model pass/fail voltage from 6 kV/6.5 kV of the prior art to 8 kV, which is the machine limit. The specification calls for a pass/fail voltage of 2 kV. Table 1 also shows that the Machine Model voltage increased from 350V/400 V for the device of the prior art to 800V/850 V for the invention (the Machine Model involves higher currents).  
                               TABLE 1                                       Human Body Model               Summary   pass/fail voltage   Machine Model                           old structure   6 kV/6.5 kV   350V/400V           new structure   8 kV   800V/850V                      
 
         [0060]    We now discuss the method of this invention of protecting high voltage n-channel metal oxide (NMOS) semiconductor transistors from electrostatic discharge (ESD) by parasitic silicon controlled rectifiers (SCR), by reference to FIG. 5.  
         [0061]    a) BLOCK  51  describes forming an n-well in a p-substrate, where the n-well is the drain of a first and a second NMOS transistor.  
         [0062]    b) in BLOCK  52  a first and second n+ diffusions is implanted in the n-well.  
         [0063]    c) in BLOCK  53  a first p+ diffusion is implanted between the two n+ diffusions of the previous step.  
         [0064]    d) next there follows in BLOCK  54  the implanting of a second and a third p+ diffusion in the p-substrate at opposite sides of the n-well.  
         [0065]    e) in BLOCK  55  there is implanted a third and a fourth n+ diffusion (the source for each of the two transistors) in the p-substrate between the n-well and the p+ diffusions of the previous step and adjacent to them.  
         [0066]    f) in BLOCK  56  a gate is formed for each of the two NMOS transistors between the n-well and the third and fourth n+ diffusions at either side of the n-well.  
         [0067]    g) BLOCK  57  connects through conductive means the drains of the two transistors.  
         [0068]    h) BLOCK  58  connects the sources of the two transistors and the two adjacent p+ diffusions to a reference potential.  
         [0069]    Note that the components described in the steps above from BLOCK  53  through  58  are arranged symmetrically around the p+ diffusion  110 . This symmetrical layout insures that SCR 1  and SCR 2  are also arranged symmetrically, including the number and size of the parasitic resistances R 1 -R 4  and the parasitic bipolar transistors. This symmetrical layout ensures a uniform current distribution in the two parasitic SCRs which results in turn-on conditions for SCR 1  and SCR 2  being identical. The uniform current distribution has been confirmed through scanning electron microscopy (SEM) which shows a uniform photo-emission (e-/hole recombination) of the “four fingers” of a layout designed according to the principles of the present invention. In similar SEM photos of devices designed according to the principles of the prior art, only two fingers (the inner ones) show a significant dissipation of current.  
         [0070]    The method of the present invention, therefore, protects the first and said second NMOS transistor mentioned in BLOCK  51  from ESD because the current distribution of a first and second intrinsic parasitic SCR is even. The method of the present invention also allows the aforementioned first and said second NMOS transistors to be duplicated by mirroring them around either the second or third p+ diffusion (refer to BLOCK  54 ).  
         [0071]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.