Abstract:
The load of the cascode amplifier is varied by connecting another (secondary) load in parallel with the original load. The secondary load is connected through a MOSFET switch. During the High Gain Mode the MOSFET switch is OFF and the secondary load is electrically isolated from the main load, whereas in the Low Gain Mode the switch is turned ON and the secondary load appears across the primary load, reducing the effective load impedance. The secondary load is AC coupled such that the DC bias current does not pass through the secondary load and hence the Noise Figure (NF) and linearity (IIP 3 ) performance are better in the Low Gain Mode. A number of such switchable loads can be connected across the load to obtain programmability.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates generally to the control of the gain of amplifiers or other high frequency blocks such as filter attenuators etc., by switching the load impedance. The invention in particular relates to controlling the gain of a Low Noise Amplifier (LNA).  
           [0003]    2. Description of the Related Art  
           [0004]    The problem of gain control versus the noise figure (NF) of low noise amplifiers as frequencies go steadily higher in the Giga Hertz range is a continuing challenge to all workers in this field. We now describe a circuit of the related art by referring to FIG. 1. FIG. 1 is taken from U.S. Pat. No. 6,046,640 (Brunner), discussed below, and is referred there to as FIG. 6. The circuit is a switched-gain cascode amplifier, including an input stage  26 , a loading network  24 , first and a second cascode transistors Q 22 , Q 23 , and a bias signal generator  22 . The input stage  26  receives a bias signal V BIAS  and the input signal V IN . The loading network  24  is coupled to a power supply voltage V CC  and provides an output signal V OUT  to a load. The input to the base of the first cascode transistor is a gain control signal V G . The input to the base of the second cascode transistor is a base control signal V BC . As mentioned the load is connected to the loading network  24  which attenuates the output signal by a different amount depending on which input terminal the signal is switched to. Listed below are related patents and a publication which bear on this problem:  
           [0005]    U.S. Pat. No. 6,466,095 B1 (Susuki) dated Oct. 15, 2002, Power Amplifier:—relates to gain variation and power amplification, whereas our invention, described below, is for a low noise amplifier (LNA). Unlike the LNA, the Power Amplifier (PA) is a large signal block, i.e., it deals with higher signal power. The main performance criterion for a PA is efficiency while for the LNA the main performance criterion is the Noise Figure (NF). In addition, the circuit of the PA itself is different from the LNA. The PA gain control scheme is also entirely different and can not be applied to the LNA.  
           [0006]    U.S. Pat. No. 6,392,492 B1 (Yuan) dated May 21, 2002, High Linearity Cascode Low Noise Amplifier, and EP 0 977 352 A2 (Fong), Noise Figure and Linearity Improvement Technique using Shunt Feedback:—both patents are for LNAs and teach techniques to improve the Noise Figure and linearity of the LNA in its normal (High Gain) mode of operation, whereas our invention proposes a gain control circuit for the LNA. The proposed Variable Gain LNA achieves the best Noise Figure in the High Gain mode and best linearity (surely better than the achievable linearity of the quoted patents) in the Low Gain mode. In addition, the reduced gain in the Low Gain mode greatly reduces the linearity requirements of the following blocks like Mixers, Filters etc, resulting in a power-efficient overall receiver. Reduced gain also reduces the dynamic range of the AGC circuit, which helps to improve the Signal to Noise Ratio (SNR).  
           [0007]    U.S. Pat. No. 6,046,640 (Brunner) dated Apr. 4, 2000, Switched-Gain Cascode Amplifier Using Loading Network for Gain Control:—this patent also is about Variable Gain LNAs. This circuit bypasses both AC and DC signals to ground in the Low Gain mode, whereas our proposed circuit bypasses only the AC signal to ground thereby not wasting the DC power. The main advantage of doing so in our scheme is that the Noise Figure and Linearity in the Low Gain mode is improved substantially. Also the input impedance is unaffected and the gain flatness is improved during gain variation. Another advantage is that one can get any amount of gain control with this circuit. Based on the requirement, the circuit can be optimized for the gain variation or the linearity or both in the Low Gain mode.  
           [0008]    Related Publication: Gain Controllable Very Low Voltage (≦1 V) 8-9 GHz Integrated CMOS LNA&#39;s, T. K. K. Tsang and M. N. El-Gamal,”  IEEE RFIC Symposium  2002. The scheme  8  proposed in this publication controls the gate bias of the PMOS transistor in the folded cascode topology and does not sacrifice the NF in Low Gain mode. A parallel tank circuit is used from VDD to the amplifier which needs lots of care to achieve in a commercially packaged LNA. The gain control scheme which we propose not only achieves a better NF but also a superior third order intercept point (IIP 3 ) in the Low Gain mode.  
         SUMMARY OF THE INVENTION  
         [0009]    It is an object of at least one embodiment of the present invention to provide a circuit and a method where the load of the cascode amplifier is varied by connecting another (secondary) load in parallel with the original load through a switch which also acts as a voltage controlled resistor.  
           [0010]    It is another object of the present invention to provide a number of such switchable loads which are connected across the load to obtain programmability of the gain.  
           [0011]    It is yet another object of the present invention to vary the load impedance as a function of a control voltage.  
           [0012]    It is still another object of the present invention to improve the noise figure and to reduce the linearity requirements in low gain mode.  
           [0013]    It is a further object of the present invention to use the bias current effectively in the low gain mode.  
           [0014]    These and many other objects have been achieved by connecting a secondary load through a MOSFET switch. During the High Gain Mode the MOSFET switch is OFF and the secondary load is electrically isolated from the main load, whereas in the Low Gain Mode the switch is turned ON and the secondary load appears across the primary load, thereby reducing the effective load impedance. The secondary load is AC coupled such that the DC bias current does not pass through the secondary load and hence the Noise Figure (NF) and linearity (IIP 3 ) performance are better in the Low Gain Mode.  
           [0015]    These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 is a circuit diagram of a switched-gain amplifier of the related art.  
         [0017]    [0017]FIG. 2 is a circuit diagram showing the principle of the present invention.  
         [0018]    [0018]FIG. 3 is circuit diagram of a first preferred embodiment of the present invention.  
         [0019]    [0019]FIG. 4. is circuit diagram of another preferred embodiment of the present invention.  
         [0020]    [0020]FIG. 5 is a block diagram of the method of the present invention. 
     
    
       [0021]    Use of the same reference number in different figures indicates similar or like elements.  
       DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0022]    Referring now to FIG. 2 we describe the general principle of the invention. The Variable Gain  16  low noise amplifier (LNA)  10  comprises a cascode amplifier stage  12  and a gain control circuit  14 . The cascode amplifier stage comprises in series between the positive and negative terminal of a power supply, respectively Vdd and ground (GND) by way of illustration, a primary load L L , transistors M 2  and M 1 , inductor Ls and a current source I D , which has capacitor Cs shunted across it. Input RFin is coupled via inductor Lg and capacitor Cg to the gate of transistor M 1 . In addition, input Bias is coupled to the gate of transistor M 1  for biasing M 1 . The gate of transistor M 2  is coupled to Vdd. The junction J between transistor M 2  and load L is coupled via capacitor C O  to the output node P of the LNA. Coupled between output node P and the negative terminal of the power supply (ground) is gain control circuit  14 . Gain control circuit  14  typically comprises, in series between output node P and ground, a capacitor Cx, transistor M 3 , and a secondary load Lx. The gate of transistor M 3  is coupled to a control voltage Vc. The gate bias voltage is the gain control voltage Vc and is varied from 0 to Vdd.  
         [0023]    When Vc=0 V, M 3  is OFF and the gain control circuitry offers a high impedance at P with respect to ground. Hence, the output of the LNA is delivered to the next stage and the whole LNA operates in High Gain mode. When Vc=Vdd, M 3  will be in the ON state and offers a low resistance between its drain and source. Now, the secondary load appears effectively across the load of the LNA, thereby reducing the overall load impedance and hence results in reduced gain of the LNA. In other words, part of the output of the first stage is shunted to ground and therefore the overall gain is reduced.  
         [0024]    The advantage of this scheme is that the drain current of M 1  and M 2  (and thus the gate overdrive) remains the same, even in the Low Gain mode and hence the Noise Figure (NF) and third order intercept point (IIP 3 ) performance of the first stage is not sacrificed. In fact, there is a slight improvement in IIP 3  of the first stage due to the reduced gain. In order to maintain the gain flatness, the impedance Z OI  at output node P with respect to ground must remain in the same quadrant (in the real and imaginary plane) in the desired frequency band when M 3  is ON as well as OFF. When M 3  is OFF, this impedance is due only to the primary load L L . In the absence of the secondary load, Z OI  would not be in the same plane due to the presence of Cgs and Csb of M 3 , when M 3  is ON. Hence the secondary load Lx is adjusted to keep Z OI  in the same plane.  
         [0025]    When Vc takes on values between 0 and 1.8V, M 3  acts as a voltage controlled resistor. Therefore the load impedance is varied as a function of Vc and thus the gain can be varied continuously by varying the control voltage Vc. The size of M 3  determines the amount of gain control that can be achieved.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0026]    [0026]FIG. 3 shows a Variable Gain LNA  10  in one of its simple forms. FIG. 3 is similar to FIG. 2, except that a) a decoupling capacitor C D  is coupled between Vdd and ground, b) loads L L  and Lx are shown as inductors, c) resistive means Rb is coupled between the gate of M 3  and Vc, and c) capacitor Cb is coupled between the gate of M 3  and ground.  
         [0027]    The LNA is matched to the input impedance through Lg, Ls and the gate-to-source capacitance Cgs (not shown) of M 1  for the desired frequency band of operation. Capacitor Cs is used to provide RF ground to Ls. Transistors M 1  (Common Source) and M 2  (Common Gate) form the cascode amplifier. Cd is the decoupling capacitor. Inductive Load L L  is used rather than a resistive load as the inductive load offers lower NF and better IIP 3 . The overlap transistor gate-to-drain capacitance Cgd (not shown) of M 2  and the load inductance L L  determine the output impedance Z OI . Usually the input impedance of the following stage is optimized for gain and gain flatness with respect to this Z OI . The network consisting of Cx, M 3 , Lx, Rb and Cb is the gain control circuitry. Cx blocks the DC current from entering the gain control circuit since we want to bypass only the AC signal to ground through M 3  and Lx. M 3  acts as a voltage controlled resistor controlled by Vc.  
         [0028]    When M 3  is OFF, Z OI  is inductive because of Lx. In the absence of the secondary load, when M 3  is ON, Z OI  becomes capacitive due to the presence of Cgs and Csb (not shown) of M 3 . The secondary load inductor Lx ensures that Z OI  is inductive even when M 3  is ON. Since Z OI  remains inductive for all values of Vc the gain flatness is not affected. The low pass network consisting of Rb and Cb at the gate of M 3  is to isolate the RF from DC. By adding a resistive means (not shown) in series with Lx, one can trade off gain and IIP 3 . In fact, Lx can be replaced by any RLC network based on the requirements of IIP 3  and gain step. Since the drain current of M 1  and M 2  does not pass through M 3  for all values of Vc, the NF and IIP 3  are even better when M 3  is ON (Low Gain Mode).  
       Modifications of the Preferred Embodiment  
       [0029]    In a second preferred embodiment of the present invention the primary and secondary loads L L  and Lx are RLC networks consisting of series and parallel combinations of all the three elements or two or one of the RLC elements. In fact, the secondary load Lx is added to get the gain flatness and in its simplest form can be replaced by a short.  
         [0030]    In a third preferred embodiment of the present invention the switching means shown as NMOSFETs can be PMOSFETs or can be implemented in BJT or BiCMOS technology as well.  
         [0031]    In a fourth preferred embodiment of the present invention this technique of bypassing the signal through a voltage-controlled resistive means can be used for any CMOS, BJT or BiCMOS circuit like a filter, Mixer, Power Amplifier etc and is not limited to a LNA.  
         [0032]    In a fifth preferred embodiment of the present invention a number of such gain control circuits are combined into a gain control block  16  and connected as shown in FIG. 4 for gain programmability. FIG. 4 is similar to FIG. 2 as far as the cascode amplifier stage  12  is concerned but has gain control block  16  coupled to the output node P. In addition, capacitor Cout is coupled between output node P and the primary load (not shown) of the next stage. Gain control block  16  comprises an analog-to-digital converter (ADC) and decoder  18 , which is driven by analog control signals. Coupled between output node P and the ADC&amp;Decoder  18  are a plurality of control circuits ranging from  1 ,  2 , to n, comprising switching means S 1 , S 2 , to Sn and secondary loads SL 1 ,  16  SL 2  to SLn. Where switching means ‘n’ in series with secondary load ‘n’ are coupled between output node P and ground. ADC&amp;Decoder  18  has ‘n’ outputs, where outputs  1 ,  2 , to n go to the gate of switching means  1 ,  2 , to n, respectively. It is thus possible to activate any or all (there are n 2  combinations) of the secondary loads. Decoders of this type are well known to those skilled in the art and need not to be explained further. This allows complete programmability of the secondary load.  
         [0033]    Referring now to FIG. 5, we describe the method of varying the gain of a low noise amplifier:  
         [0034]    Block  1  provides a cascode amplifier stage driving a primary load;  
         [0035]    Block  2  couples a secondary load across the primary load at the output of the cascode amplifier stage;  
         [0036]    Block  3  couples a switching means between the secondary load and the output of the cascode amplifier stage;  
         [0037]    Block  4  applies a control voltage to the switching means to vary the impedance of the switching means;  
         [0038]    Block  5  switches the switching means into the OFF state, thereby switching the low noise amplifier into a high gain mode;  
         [0039]    Block  6  switches the switching means into the ON state, thereby switching the low noise amplifier into a low gain mode, and  
         [0040]    Block  7  couples a plurality of secondary loads across the primary load.  
         [0041]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.