Abstract:
Disclosed is a column select signal adjusting circuit capable of reducing interference between bit lines and data lines and a semiconductor memory device having the same. The column select signal voltage adjusting circuit includes a driving voltage generating unit for producing a driving voltage when the write signal is activated, wherein a voltage level of the driving voltage produced when the write signal is activated is higher than a voltage level of the driving voltage produced when the write signal is inactivated, and a column select signal driving unit for outputting a column select signal by driving a decoding signal to the voltage level of the driving voltage.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2008-0023029, filed on Mar. 12, 2008, in the Korean Intellectual Property Office, which is incorporated by reference in its entirety as set forth in full. 
       BACKGROUND 
       [0002]    The embodiments described here relate to a semiconductor integrated circuit and, more particularly, to a column select signal adjusting circuit and a semiconductor memory apparatus having the same. 
         [0003]    Generally, a semiconductor memory apparatus includes a plurality of memory cells so that data write and read operations are carried out in the memory cells of the semiconductor memory apparatus. 
         [0004]    Bit lines and bit bar lines are used to store and read out the data in and from the semiconductor memory apparatus and hierarchical data lines are required to process a large amount of data in the semiconductor memory apparatus. 
         [0005]    However, a conventional bit line and bit bar line is shorter than a data line and a data bar line which is disposed at a high rank. Accordingly, parasite capacitance of the bit line and the bit bar line is lower than that of the data line and the data bar line. 
         [0006]    At this time, there is no problem when the data are transferred from the data line and the data bar line, which have a relative large amount of parasite capacitance, to the bit line and the bit bar line having the relative small amount of parasite capacitance. 
         [0007]    However, in the case where the data are transferred from the bit line and the bit bar line, which have the relative small amount of parasite capacitance, to the data line and the data bar line which have the relative large amount of parasite capacitance, the voltage levels of the bit line and the bit bar line are varied due to the data line and the data bar line. This variation in the voltage levels of the bit line and the bit bar line can vary the data value stored in the memory cell. 
       SUMMARY OF THE INVENTION 
       [0008]    A column select signal adjusting circuit capable of reducing interference between bit lines and data lines and a semiconductor memory device having the same is described herein. 
         [0009]    In one aspect, a column select signal voltage adjusting circuit of a semiconductor memory device include a driving voltage generating unit configured to receive a reference voltage and produce a driving voltage which has a voltage level corresponding to the reference voltage and configured to produce the driving voltage, which has a voltage level of an external voltage, in response to a write signal, a column select signal driving unit for outputting a column select signal by driving a decoding signal to the voltage level of the driving voltage. 
         [0010]    In another aspect, a column select signal voltage adjusting circuit of a semiconductor memory device includes a driving voltage generating unit for producing a driving voltage when the write signal is activated, wherein a voltage level of the driving voltage produced when the write signal is activated is higher than a voltage level of the driving voltage produced when the write signal is inactivated, and a column select signal driving unit for outputting a column select signal by driving a decoding signal to the voltage level of the driving voltage. 
         [0011]    In further another aspect, a semiconductor memory device includes a column select signal voltage adjusting circuit for producing a column select signal when the write signal is activated, wherein a voltage level of the column select signal produced when the write signal is activated is higher than a voltage level of the column select signal produced when the write signal is inactivated, and a data transfer switching unit for connecting a pair of bit lines to a pair of data lines in response to the column select signal. 
         [0012]    These and other features, aspects, and embodiments are described below in the section “Detailed Description.” 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0013]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0014]      FIG. 1  is a schematic block diagram illustrating a semiconductor memory device according to one embodiment; 
           [0015]      FIG. 2  is a block diagram illustrating a column select signal voltage adjusting circuit of  FIG. 1 ; 
           [0016]      FIG. 3  is a circuit diagram illustrating a structure of an example of a driving voltage generating unit of  FIG. 2 ; 
           [0017]      FIG. 4  is a circuit diagram illustrating a structure of another example of a driving voltage generating unit of  FIG. 2 ; and 
           [0018]      FIG. 5  is a circuit diagram illustrating a structure of an example of a column select signal driving unit of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION  
       [0019]    As shown in  FIG. 1 , a semiconductor memory apparatus according to one embodiment can include a pair of bit lines BL and BLB, a memory cell  10 , a sense amplifier  20 , a data transfer switching unit  50 , a column select signal adjusting circuit  500 , and a pair of data lines data_line and data_lineb. 
         [0020]    The memory cell  10  can include a first transistor N 1  coupled to a word line WL and the bit line BL and a capacitor C 1  coupled to the first transistor N 1 . When the word line WL is activated, the capacitor C 1  of the memory cell  10  stores data or the stored data are transferred to the bit line BL. 
         [0021]    The sense amplifier  20  can amplify a voltage difference between the bit line BL and the bit bar line BLB. The voltage difference is generated when the data are transferred to the bit line BL. 
         [0022]    The data transfer switching unit  50  can selectively transfer the voltage levels of the bit line BL and the bit bar line BLB, which is amplified by the sense amplifier  20 , to the data line data_line and the data bar line data_lineb, respectively. The data transfer switching unit  50  can include two transistors N 2  and N 3  which couple the bit line BL and the bit bar line BLB to the data line data_line and the data bar line data_lineb, respectively. These two transistors N 2  and N 3  can be used as switches in response to a column select signal YS from the column select signal adjusting circuit  500 . 
         [0023]    Referring to  FIG. 2 , the column select signal adjusting circuit  500  can include a driving voltage generating unit  100  and a column select signal driving unit  200 . 
         [0024]    The driving voltage generating unit  100  can be configured to generate a driving voltage drive_voltage in response to a write signal WTB. For example, the driving voltage generating unit  100  can generate the driving voltage drive_voltage at a relative high voltage level when the write signal WTB is activated and can generate the driving voltage drive_voltage at a relative low voltage level when the write signal WTB is inactivated. The driving voltage generating unit  100  can output the driving voltage drive_voltage at a voltage level of an external voltage VDD when the write signal WTB is activated and can output the driving voltage drive_voltage at a voltage level which is lower than that of the external voltage VDD when the write signal WTB is inactivated. 
         [0025]    As shown in  FIG. 3 , the driving voltage generating unit  100  can include a division voltage generating unit  110 , a division voltage output unit  120 , and an external voltage output unit  130 . 
         [0026]    The division voltage generating unit  110  can be configured to generate a division voltage Vd by dividing the external voltage VDD. The division voltage generating unit  110  can include a first resistor R 11  and a second resistor R 12 . The external voltage VDD is applied to one end of the first resistor R 11 . One end of the resistor R 12  is coupled to the other end of the resistor R 11  and the other end of the resistor R 12  is coupled to a ground voltage terminal VSS. At this time, the division voltage Vd is output from a connection node between the first resistor R 11  and the second resistor R 12 . 
         [0027]    The division voltage output unit  120  can be configured to output the division voltage Vd, as the driving voltage drive_voltage, when the write signal WTB is inactivated at a high level. The division voltage output unit  120  can include a first transistor N 11  which outputs through a source the division voltage Vd as the driving voltage drive_voltage, which is applied to a drain in response to the write signal WTB applied to a gate thereof. 
         [0028]    The external voltage output unit  130  can be configured to output the external voltage as the driving voltage drive_voltage when the write signal WTB is activated at a low level. The external voltage output unit  130  can include a second transistor P 11  which outputs through a drain the external voltage VDD, as the driving voltage drive_voltage, which is applied to a source in response to the write signal WTB applied to a gate thereof. 
         [0029]    Referring to  FIG. 3 , in the division voltage generating unit  110 , the voltage division rate of the external voltage VDD can be determined by the resistance values of the resistors R 11  and R 12 . The division voltage generating unit  110  divides the external voltage VDD according to the determined voltage division rate. In the case where the write signal WTB is inactivated at a high level, the division voltage Vd is output as the driving voltage drive_voltage. Meanwhile, when the write signal WTB is activated at a low level, the external voltage VDD is output as the driving voltage drive_voltage. 
         [0030]    As a result, when the write signal WTB is activated, the driving voltage generating unit  100  according to an example of one embodiment can generate the driving voltage drive_voltage which is higher than that produced when the write signal WTB is inactivated. 
         [0031]    Furthermore, as shown in  FIG. 4 , a driving voltage generating unit  100 ′ according to another example of the driving voltage generating unit of  FIG. 2  can include a voltage generating unit  110 ′ and a voltage supply unit  120 ′. 
         [0032]    The voltage generating unit  110 ′ can include a comparator  111 , a driver  112 , and a voltage dividing unit  113 . 
         [0033]    The comparator  111  can be configured to compare a reference voltage Vref with a division voltage V_dv when an enable signal En is activated and then generate a detection signal det. 
         [0034]    This comparator  111  can include a first inverter IV 11  and first to fifth transistors N 11  to N 13 , P 11  and P 12 . The first inverter IV 11  receives the enable signal En. The reference signal Vref is applied to a gate of the first transistor N 11 . The division voltage V_dv is applied to a gate of the second transistor N 12 . The third transistor N 13  has a gate to which an output signal of the first inverter IV 11  is applied, a drain which is connected to sources of the first and second transistors N 11  and N 12 , and a source to which a ground voltage (VSS) terminal is connected. The fourth transistor P 11  has a gate to which the enable signal En is applied, a source which is connected to the external voltage (VDD) terminal, and a drain to which a drain of the first transistor N 11  is connected. The fifth transistor P 12  has a gate to which the enable signal En is applied, a source which is connected to the external voltage (VDD) terminal, and a drain to which a drain of the second transistor N 12  is connected. At this time, the detection signal det is output from a connection node between the first and fourth transistors N 11  and P 11 . 
         [0035]    The driver  112  can be configured to output the driving voltage drive_voltage by driving the external voltage VDD according to the voltage level of the detection signal det. The driver  112  can include a sixth transistor P 13 . The sixth transistor P 13  has a gate to which the detection signal det is applied, a source to which the external voltage VDD is applied, and a drain through which the driving voltage drive_voltage is output. 
         [0036]    The voltage dividing unit  113  can be generated the division voltage V_dv by dividing the driving voltage drive_voltage. The voltage dividing unit  113  can include a first resistor R 11 ′ and a second resistor R 12 ′. The external voltage VDD is applied to one end of the first resistor R 11 ′. One end of the resistor R 12 ′ is coupled to the other end of the resistor R 11 ′ and the other end of the resistor R 12 ′ is coupled to the ground voltage (VSS) terminal. At this time, the division voltage V_dv is output from a connection node between the first resistor R 11 ′ and the second resistor R 12 ′. 
         [0037]    When the write signal WTB is activated, the voltage supply unit  120 ′ outputs the driving voltage drive_voltage at the voltage level of the external voltage VDD, by applying the external voltage VDD to an output node of the voltage generating unit  110 ′. The voltage supply unit  120 ′ can include a seventh transistor P 14  and the seventh transistor P 14  has a gate to which the write signal WTB is applied, a source to which the external voltage VDD is applied, and a drain which is connected to the output node of the voltage generating unit  110 ′. 
         [0038]    The operation of the driving voltage generating unit  100  of  FIG. 4  will be described in detail below. First, if the enable signal En is activated, the comparator  111  is enabled. The enabled comparator  111  can compare the reference voltage Vref with the division voltage V_dv and then produces the detection signal det. For example, the comparator  111  activates the detection signal det at a low level when the reference voltage Vref is higher than the division voltage V_dv. Furthermore, the comparator  111  can be configured to inactivate the detection signal det at a high level when the reference voltage Vref is lower than the division voltage V_dv. 
         [0039]    The driver  112  can be configured to drive the external voltage VDD according to the voltage level of the detection signal det, thereby outputting the driving voltage drive_voltage. For example, the driving operation of the driver  112  is not carried out when the detection signal det is inactivated at a high level. On the other hand, the driver  112  drives the external voltage VDD when the detection signal det is activated at a low level. The drivability of the driver  112  is controlled by the voltage level of the detection signal det. The reason why the driver  112  is controlled by the voltage level of the detection signal det is that the driver  112  includes the turn-on strength of the sixth transistor P 13  is determined by the gate voltage signal (i.e., the detection signal det). Accordingly, the driving voltage drive_voltage, which is output from the driver  112 , is lower than the external voltage VDD. 
         [0040]    The voltage dividing unit  113  can be configured to generate the division voltage V_dv by dividing the driving voltage drive_voltage. 
         [0041]    Therefore, when the division voltage V_dv is higher than the reference voltage Vref, the detection signal det is inactivated and then the driving operation is not carried out by the driver  112 . Furthermore, when the division voltage V_dv is lower than the reference voltage Vref, the detection signal det is activated and then the driving operation is carried out by the driver  112 . Accordingly, the driving voltage drive_voltage which is generated by only the voltage generating unit  110 ′ is lower than the external voltage VDD. 
         [0042]    If the write signal WTB, which is activated at a ground voltage level, is input into the voltage supply unit  120 , the external voltage VDD is applied to the output terminal of the voltage generating unit  110 ′. That is, the driving voltage drive_voltage is the same as the external voltage VDD. When the driving voltage drive_voltage goes to the external voltage VDD, the comparator  111  outputs the inactivated detection signal det and there is no an output signal from the voltage generating unit  110 ′. 
         [0043]    As a result, the driving voltage generating unit  100  can be configured to output the driving voltage drive_voltage of which the voltage level is lower than that of the external voltage VDD. However, while the write signal WTB is activated, the driving voltage generating unit  100  outputs the external voltage VDD as the driving voltage drive_voltage. 
         [0044]    The column select signal driving unit  200  can be configured to output the driving voltage drive_voltage, as a column select signal YS, in response to an enabled decoding signal dec which is provided from a column decoder (not shown). At this time, the decoding signal dec can be generated by decoding address signals. 
         [0045]    As shown in  FIG. 5 , the column select signal driving unit  200  can include a second inverter IV 21  and a third inverter IV 22 . 
         [0046]    The second inverter IV 21  inverts the decoding signal dec and the third inverter IV 22 , which receives an output signal of the second inverter IV 21 , outputs the column select signal YS. At this time, the driving voltage drive_voltage is applied to the third inverter IV 22 . 
         [0047]    The third inverter IV 22  can include a ninth transistor P 21  and a tenth transistor N 21 . The ninth transistor P 21  has a gate to which the output signal of the second inverter IV 21  is applied and a source to which the driving voltage drive_voltage is applied. The tenth transistor N 21  has a gate to which the output signal of the second inverter IV 21  is applied, a drain to which an output signal of the ninth transistor P 21  is applied, and a source which is connected to the ground voltage (VSS) terminal. At this time, the column select signal YS is outputted from a connection node between the ninth transistor P 21  and the ninth transistor N 21 . 
         [0048]    The operation of the column select signal voltage adjusting circuit according to one embodiment will be described in detail 
         [0049]    The column select signal driving unit  200  outputs the driving voltage generating unit  100 , as the column select signal YS, in response to the enabled decoding signal dec. That is, the column select signal driving unit  200  outputs the column select signal YS, which is lower than the external voltage VDD, when the write signal WTB is inactivated and, therefore, the column select signal YS may be the division voltage drive_voltage. When the write signal WTB is activated, the column select signal driving unit  200  outputs the column select signal YS at the voltage level of the external voltage VDD. 
         [0050]    The turn-on states of the transistor N 2  and N 3 , which implement the data transmission switching unit  50  of  FIG. 5 , can be determined by the voltage level of the column select signal YS. For example, when the voltage level of the column select signal YS is lower than the external voltage VDD, the turn-on strength of the transistors N 2  and N 3  becomes low. Here, the turn-on strength can mean the turn-on speed of the transistors or an amount of current flowing into the transistors. 
         [0051]    Accordingly, in the case where the data are transferred from the pair of bit lines to the pair of the data, the division voltage V_dv, which is lower than the external voltage VDD, is inputted, as the column select signal YS, into the data transmission switching unit  50 . Therefore, the turn-on strength of the transistors in the data transmission switching unit  50  becomes low and thus the parasite capacitance is less influenced on the pair of bit lines BL and BLB. 
         [0052]    As a result, at the read operation of the semiconductor memory apparatus, the data line interference caused by the bit line can be prevented. 
         [0053]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.