Abstract:
A Viterbi decoding apparatus receives a plurality of block data in time order, and transmits a block data group including the plurality of block data. Then, the Viterbi decoding apparatus applies a Viterbi decoding algorithm to the block data group and outputs some block data of the block data group. In this way, it is possible to provide a Viterbi decoding apparatus that can operate at a high speed and improve a data transmission rate.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of Korean Patent Application No. 10-2007-0130384 filed in the Korean Intellectual Property Office on Dec. 13, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    (a) Field of the Invention 
         [0003]    The present invention relates to a Viterbi decoding method and apparatus. Particularly, the present invention relates to a Viterbi decoding method and apparatus in an ultra-wideband system. 
         [0004]    The present invention was supported by the IT R&amp;D program of MIC/IITA [2006-S-071-02, Development of USB solution for High-speed Multimedia Transmission]. 
         [0005]    (b) Description of the Related Art 
         [0006]    Convolutional codes have been commonly used as channel codes for correcting transmission errors during wire/wireless data communication, and Viterbi decoders have been generally used to decode data with channels that are encoded by these convolutional codes. The Viterbi decoder has advantages in that it has high performance and a simple hardware structure. 
         [0007]    However, it is difficult for the existing Viterbi decoder to operate at a high speed in a communication system requiring a high-speed operation, and it is difficult to improve a data transmission rate. 
         [0008]    The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention has been made in an effort to provide a Viterbi decoding apparatus that can operate at a high speed and improve a data transmission rate. 
         [0010]    According to an aspect of the invention, a Viterbi decoding method includes: receiving a plurality of block data in time order; transmitting a first block data group including the plurality of block data; applying a Viterbi decoding algorithm to the first block data group and outputting some block data of the first block data group; receiving a plurality of additional block data connected with the plurality of block data in time order; transmitting a second block data group including the plurality of additional block data and some block data of the first block data group; and applying the Viterbi decoding algorithm to the second block data group and outputting some block data of the second block data group. 
         [0011]    The receiving of the plurality of block data may include receiving an even number of block data in time order, and the receiving of the plurality of additional block data may include receiving an even number of additional block data in time order. 
         [0012]    The even number of block data may be four block data, the even number of additional block data may be two additional block data, and the second block data group may include two of the four block data and the two additional block data. 
         [0013]    The second block data group may include two of the four block data that are received late in time order. 
         [0014]    The outputting of some block data of the first block data group may include outputting the second block data and third block data of the first block data group that are received in time order. 
         [0015]    The outputting of some block data of the second block data group may include outputting the second block data and the third block data of the second block data group that are received in time order. 
         [0016]    The Viterbi decoding algorithm may be a block processing Viterbi decoding algorithm. 
         [0017]    According to another aspect of the invention, there is provided a Viterbi decoding apparatus that receives data from a depuncturer including two memory buffers and outputting the data from the depuncturer using output clocks which is equal to or higher than input clocks, and performs decoding. The Viterbi decoding apparatus includes a distributor, a plurality of memory banks, a plurality of switches, and a plurality of decoders. The distributor receives a plurality of bits from the depuncturer, and distributes the received plurality of bits to each block data unit. The plurality of memory banks receive block data corresponding to some of the plurality of bits from the distributor in a predetermined order, and store the received block data. The plurality of switches are connected to some of the plurality of memory banks, and output the block data stored in one of the connected memory banks. The plurality of decoders are connected to some of the plurality of switches, receive a plurality of block data from the connected switches, process the plurality of block data according to a Viterbi decoding algorithm, and output some of the plurality of block data. 
         [0018]    Some or all of the plurality of decoders may be used according to the number of bits simultaneously inputted to the distributor. 
         [0019]    The plurality of memory banks may be an even number of memory banks, and the plurality of switches may be an even number of switches. Odd-numbered switches of the even number of switches may be connected in parallel to odd-numbered memory banks of the even number of memory banks, and even-numbered switches of the even number of switches may be connected in parallel to even-numbered memory banks of the even number of memory banks. 
         [0020]    The plurality of decoders may be sliding block Viterbi decoders using a block processing Viterbi decoding method. 
         [0021]    The plurality of memory banks may include eight memory banks, the plurality of switches may include eight switches, and the plurality of decoders may include two decoders. 
         [0022]    Each of the two decoders may have transmission capacity that is half the maximum transmission capacity of the Viterbi decoding apparatus. 
         [0023]    The Viterbi decoding apparatus according to the above-mentioned aspect of the invention can operate at a high speed using a block processing decoding method and improve a data rate. Further, it is possible to control the operation of the Viterbi decoding apparatus according to a data rate and thus reduce power consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIG. 1  is a diagram illustrating the structure of transmitting/receiving apparatuses of an ultra-wideband system following an MB-OFDM scheme according to an exemplary embodiment of the present invention. 
           [0025]      FIG. 2  is a diagram illustrating the input and output of a depuncturer when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is 53.3 Mbps. 
           [0026]      FIG. 3  is a diagram illustrating the input and output of the depuncturer when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is 480 Mbps. 
           [0027]      FIG. 4  is a diagram illustrating the input and output of the depuncturer when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is 960 Mbps. 
           [0028]      FIG. 5  is a diagram illustrating the structure of a Viterbi decoding unit according to the exemplary embodiment of the present invention. 
           [0029]      FIG. 6  is a diagram illustrating the operation of the Viterbi decoding unit decoding depunctured data when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is 480 Mbps or less. 
           [0030]      FIG. 7  is a diagram illustrating the operation of the Viterbi decoding unit decoding the depunctured data when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is more than 480 Mbps. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0031]    In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. 
         [0032]    It will be understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. In addition, the terms “-er”, “-or”, and “module” described in the specification mean units for processing at least one function and operation and can be implemented by hardware components or software components and combinations thereof. 
         [0033]    Hereinafter, a Viterbi decoding method and apparatus according to exemplary embodiments of the present invention will be described with reference to the accompanying drawings. 
         [0034]    First, transmitting/receiving apparatuses of an ultra-wideband system following a multi-band orthogonal frequency division multiplexing (MB-OFDM) scheme according to an exemplary embodiment of the present invention will be described with reference to  FIGS. 1 to 4 . 
         [0035]      FIG. 1  is a diagram illustrating the structure of the transmitting/receiving apparatuses of the ultra-wideband system following the MB-OFDM scheme according to the exemplary embodiment of the present invention. 
         [0036]    As shown in  FIG. 1 , the transmitting apparatus of the ultra-wideband system according to the exemplary embodiment of the present invention includes a scrambler  100 , a convolutional encoder  110 , a puncturer  120 , an interleaver  130 , a constellation encoder  140 , a symbol mapping unit  150 , an inverse Fast Fourier transform (IFFT) arithmetic unit  160 , and a transmitter  170 . 
         [0037]    The scrambler  100  receives source data composed of a plurality of bits, scrambles the source data, and outputs the scrambled data. 
         [0038]    The convolutional encoder  110  encodes the scrambled data using convolution codes and outputs the encoded data. 
         [0039]    The puncturer  120  punctures the encoded data, that is, converts a data coding rate, and outputs the punctured data. In this case, the ultra-wideband system has a basic data coding rate of ⅓, and the puncturer  120  punctures the encoded data having the basic data coding rate and outputs the punctured data having a data coding rate of ½, ⅝, or ¾. 
         [0040]    The interleaver  130  interleaves the punctured data, and outputs the interleaved data. The interleaved data is composed of a plurality of bits. 
         [0041]    The constellation encoder  140  encodes the interleaved data and outputs a plurality of symbols. The constellation encoder  140  may encode the interleaved data using a quadrature phase shift keying (QPSK) method, a dual carrier modulation (DCM) method, or a 16-quadrature amplitude modulation (16-QAM) method. 
         [0042]    The symbol mapping unit  150  maps a plurality of symbols, and outputs a plurality of frequency domain symbols. The symbol mapping unit  150  may map a plurality of symbols to a plurality of frequency domain symbols using time spread or frequency spread effects. 
         [0043]    The IFFT arithmetic unit  160  performs inverse fast Fourier transform (IFFT) on a plurality of frequency domain symbols and outputs orthogonal frequency division multiplexing (OFDM) signals. 
         [0044]    The transmitter  170  transmits the OFDM signals to the receiving apparatus through an antenna. The transmitter  170  may convert digital OFDM signals into analog OFDM signals, amplify the analog OFDM signals, and transmit the amplified signals. 
         [0045]    The data rates supported by the ultra-wideband system according to the exemplary embodiment of the present invention are shown in Table 1. 
         [0000]    
       
         
               
               
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                   
                   
                 Encoded 
                   
                   
               
               
                 Data rate 
                 Modulation 
                 Coding 
                 bit/6 OFDM 
                 Frequency 
                 Time 
               
               
                 (Mbps) 
                 method 
                 rate 
                 symbols 
                 spreading 
                 spreading 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 53.3 
                 QPSK 
                 ⅓ 
                 300 
                 YES 
                 YES 
               
               
                 80 
                 QPSK 
                 ½ 
                 300 
                 YES 
                 YES 
               
               
                 106.7 
                 QPSK 
                 ⅓ 
                 600 
                 NO 
                 YES 
               
               
                 160 
                 QPSK 
                 ½ 
                 600 
                 NO 
                 YES 
               
               
                 200 
                 QPSK 
                 ⅝ 
                 600 
                 NO 
                 YES 
               
               
                 320 
                 DCM 
                 ½ 
                 1200 
                 NO 
                 NO 
               
               
                 400 
                 DCM 
                 ⅝ 
                 1200 
                 NO 
                 NO 
               
               
                 480 
                 DCM 
                 ¾ 
                 1200 
                 NO 
                 NO 
               
               
                 640 
                 16QAM 
                 ½ 
                 2400 
                 NO 
                 NO 
               
               
                 800 
                 16QAM 
                 ⅝ 
                 2400 
                 NO 
                 NO 
               
               
                 960 
                 16QAM 
                 ¾ 
                 2400 
                 NO 
                 NO 
               
               
                   
               
             
          
         
       
     
         [0046]    As shown in Table 1, a modulation method, a coding rate, encoded bits per 6 OFDM symbols, the decision of whether to perform frequency spreading, and the decision of whether to perform time spreading depend on the data rate. 
         [0047]    As shown in  FIG. 1 , the receiving apparatus of the ultra-wideband system according to the exemplary embodiment of the present invention includes a receiver  200 , a synchronizing unit  210 , a fast Fourier transform (FFT) arithmetic unit  220 , a symbol demapping unit  230 , an equalizer  240 , a constellation decoder  250 , a deinterleaver  260 , a depuncturer  270 , a Viterbi decoding unit  280 , and a descrambler  290 . 
         [0048]    The receiver  200  receives the OFDM signal transmitted from the transmitting apparatus. The receiver  200  may amplify the received OFDM signal and convert analog OFDM signals into digital OFDM signals. 
         [0049]    The synchronizing unit  210  synchronizes the received OFDM signal and outputs the synchronized OFDM signal. The synchronizing unit  210  may perform frame synchronization for detecting the start of a signal, symbol synchronization for detecting the start of a symbol, and frequency synchronization for finding a phase error. 
         [0050]    The FFT arithmetic unit  220  performs fast Fourier transform (FFT) on the synchronized OFDM signal, and outputs a plurality of frequency domain symbols. 
         [0051]    The symbol demapping unit  230  demaps the plurality of frequency domain symbols and outputs a plurality of symbols. The symbol demapping unit  230  may effectively remove time spread and frequency spread to demap a plurality of frequency domain symbols into a plurality of symbols. 
         [0052]    The equalizer  240  equalizes the channels of a plurality of symbols and outputs a plurality of channel-equalized symbols. 
         [0053]    The constellation decoder  250  decodes the plurality of channel-equalized symbols and outputs decoded data including a plurality of bits. The constellation decoder  250  may perform soft decision decoding on the plurality of channel-equalized symbols and output decoded data. 
         [0054]    The deinterleaver  260  deinterleaves the decoded data and outputs deinterleaved data including a plurality of bits. The deinterleaver  260  includes two memory blocks, performs reading in one of the memory blocks, and performs writing in the other memory block. Since the deinterleaver  260  has two memory blocks, it can make an input clock different from an output clock. 
         [0055]    The depuncturer  270  depunctures the deinterleaved data and outputs depunctured data including a plurality of bits. The depuncturer  270  has a dual buffer structure that uses two memory buffers. The depuncturer  270  may use different input and output clocks, and selects different input and output bits. The output of the deinterleaver  260  and the output of the depuncturer  270  depending on the data rate are shown in Table 2. 
         [0056]    (Table 2) 
         [0000]    
       
         
               
               
               
             
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
             
             
               
                   
                   
               
               
                   
                 Output of deinterleaver 
                 Output of depuncturer 
               
             
          
           
               
                   
                   
                   
                 Number 
                   
                   
                 Number 
               
               
                 Data rate 
                 Clock 
                 Number 
                 of 
                 Clock 
                 Number 
                 of 
               
               
                 (Mbps) 
                 (MHz) 
                 of bits 
                 repeats 
                 (MHz) 
                 of bits 
                 repeats 
               
               
                   
               
             
          
           
               
                 53.3 
                 132 
                 4 
                 3 
                 264 
                 6 
                 2 
               
               
                 80 
                 132 
                 4 
                 2 
                 264 
                 6 
                 2 
               
               
                 106.7 
                 132 
                 4 
                 3 
                 264 
                 6 
                 2 
               
               
                 160 
                 132 
                 4 
                 2 
                 264 
                 6 
                 2 
               
               
                 200 
                 132 
                 4 
                 4 
                 264 
                 6 
                 5 
               
               
                 320 
                 132 
                 4 
                 2 
                 264 
                 6 
                 2 
               
               
                 400 
                 132 
                 4 
                 4 
                 264 
                 6 
                 5 
               
               
                 480 
                 132 
                 4 
                 4 
                 264 
                 6 
                 6 
               
               
                 640 
                 264 
                 4 
                 2 
                 264 
                 12 
                 1 
               
               
                 800 
                 264 
                 4 
                 8 
                 264 
                 12 
                 5 
               
               
                 960 
                 264 
                 4 
                 4 
                 264 
                 12 
                 3 
               
               
                   
               
             
          
         
       
     
         [0057]    The output of the deinterleaver and the output of the depuncturer corresponding to each data rate may be determined as shown in Table 2. In this case, the output of the deinterleaver and the output of the depuncturer depend on a clock, the number of bits, and the number of repeats. 
         [0058]    In Table 2, when the number of bits is 6, the coding rate of the convolutional code is ⅓, which means that the number of bits subjected to convolutional coding is 2. Similarly, when the number of bits is 12, the number of bits subjected to convolutional coding is 4. 
         [0059]    The output of the deinterleaver corresponds to the input of the depuncturer. 
         [0060]    Next, the input and output of the depuncturer according to the exemplary embodiment of the present invention will be described with reference to  FIGS. 2 ,  3 , and  4 . 
         [0061]      FIG. 2  is a diagram illustrating the output and input of the depuncturer when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is 53.3 Mbps. 
         [0062]    As shown in  FIG. 2 , the depuncturer  270  according to the exemplary embodiment of the present invention includes a first buffer  271  and a second buffer  273 . 
         [0063]    The first buffer  271  sequentially receives a first input  271   a,  a second input  271   b,  and a third input  271   c.  The first input  271   a,  the second input  271   b,  and the third input  271   c  correspond to three 4-bit data at a rate of 132 MHz that are output from the deinterleaver  260  when the data rate is 53.3 Mbps, as shown in Table 2. 
         [0064]    The second buffer  273  sequentially outputs a first output  273   a  and a second output  273   b.  The first output  273   a  and the second output  273   b  correspond to two 6-bit data at a rate of 264 MHz that are output from the depuncturer  270  when the data rate is 53.3 Mbps, as shown in Table 2. 
         [0065]    In this case, when writing data to the first buffer  271 , the depuncturer  270  may output data of the second buffer  273 . Then, when the next data is input, the depuncturer  270  may write data to the second buffer  273  and output data of the first buffer  271 . In this way, the first buffer  271  and the second buffer  273  may alternately perform reading and writing while data is continuously input. 
         [0066]      FIG. 3  is a diagram illustrating the output and input of the depuncturer when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is 480 Mbps. 
         [0067]    As shown in  FIG. 3 , the depuncturer  270  according to the exemplary embodiment of the present invention includes the first buffer  271  and the second buffer  273 . 
         [0068]    The first buffer  271  sequentially receives the first input  271   a,  the second input  271   b,  the third input  271   c,  and a fourth input  271   d.  The first input  271   a,  the second input  271   b,  the third input  271   c,  and the fourth input  271   d  correspond four 4-bit data at a rate of 132 MHz that are output from the deinterleaver  260  when the data rate is 480 Mbps, as shown in Table 2. 
         [0069]    Each of four bits included in each of the first input  271   a,  the second input  271   b,  the third input  271   c,  and the fourth input  271   d  is written to a portion of the first buffer  271  along any one of the first to fourth paths, and the other portion of the first buffer  271  is filled with dummy bits. 
         [0070]    The second buffer  273  sequentially outputs the first output  273   a,  the second output  273   b,  a third output  273   c,  a fourth output  273   d,  a fifth output  273   e,  and a sixth output  273   f.  The first output  273   a,  the second output  273   b,  the third output  273   c,  the fourth output  273   d,  the fifth output  273   e,  and the sixth output  273   f  correspond to six 6-bit data at a rate of 264 MHz that are output from the depuncturer  270  when the data rate is 480 Mbps, as shown in Table 2. 
         [0071]    In this case, the first buffer  271  and the second buffer  273  may alternately perform reading and writing while data is continuously input. 
         [0072]      FIG. 4  is a diagram illustrating the output and input of the depuncturer when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is 960 Mbps. 
         [0073]    As shown in  FIG. 4 , the depuncturer  270  according to the exemplary embodiment of the present invention includes the first buffer  271  and the second buffer  273 . 
         [0074]    The first buffer  271  sequentially receives the first input  271   a,  the second input  271   b,  the third input  271   c,  and the fourth input  271   d.  The first input  271   a,  the second input  271   b,  the third input  271   c,  and the fourth input  271   d  correspond to four 4-bit data at a rate of 264 MHz that are output from the deinterleaver  260  when the data rate is 960 Mbps, as shown in Table 2. 
         [0075]    Each of four bits included in each of the first input  271   a,  the second input  271   b,  the third input  271   c,  and the fourth input  271   d  is written to a portion of the first buffer  271  along any one of the first to fourth paths, and the other portion of the first buffer  271  is filled with dummy bits. 
         [0076]    The second buffer  273  sequentially outputs the first output  273   a,  the second output  273   b,  and the third output  273   c.  The first output  273   a,  the second output  273   b,  and the third output  273   c  correspond to three 12-bit data at a rate of 264 MHz that are output from the depuncturer  270  when the data rate is 960 Mbps, as shown in Table 2. 
         [0077]    In this case, the first buffer  271  and the second buffer  273  may alternately perform reading and writing while data is continuously input. 
         [0078]    Next, the transmitting/receiving apparatuses of the ultra-wideband system following the MB-OFDM scheme according to the exemplary embodiment of the present invention will be described referring to  FIG. 1  again. 
         [0079]    The Viterbi decoding unit  280  decodes depunctured data and outputs decoded data including a plurality of bits. When the number of bits of the depunctured data is 6, the Viterbi decoding unit  280  may decode the depunctured data and output 2-bit decoded data. When the number of bits of the depunctured data is 12, the Viterbi decoding unit  280  may decode the depunctured data and output 4-bit decoded data. The Viterbi decoding unit  280  may be called a Viterbi decoding device or a Viterbi decoder. 
         [0080]    The descrambler  290  descrambles the decoded data and output source data. 
         [0081]    Next, the Viterbi decoding unit according to the exemplary embodiment of the present invention will be described in detail with reference to  FIG. 5 . 
         [0082]      FIG. 5  is a diagram illustrating the structure of the Viterbi decoding unit according to the exemplary embodiment of the present invention. 
         [0083]    As shown in  FIG. 5 , the Viterbi decoding unit  280  according to the exemplary embodiment of the present invention includes a distributor  281 , eight memory banks  283   a,    283   b,    283   c,    283   d,    283   e,    283   f,    283   g,  and  283   h,  eight switches  285   a,    285   b,    285   c,    285   d,    285   e,    285   f,    285   g,  and  285   h,  and two decoders  287   a  and  287   b.    
         [0084]    The distributor  281  is connected to the eight memory banks, that is, the first memory bank  283   a,  the second memory bank  283   b,  the third memory bank  283   c,  the fourth memory bank  283   d,  the fifth memory bank  283   e,  the sixth memory bank  283   f,  the seventh memory bank  283   g,  and the eighth memory bank  283   h.    
         [0085]    The first switch  285   a,  the third switch  285   c,  the fifth switch  285   e,  and the seventh switch  285   g  are connected to the first memory bank  283   a,  the third memory bank  283   c,  the fifth memory bank  283   e,  and the seventh memory bank  283   g,  respectively, and the second switch  285   b,  the fourth switch  285   d,  the sixth switch  285   f,  and the eighth switch  285   h  are connected to the second memory bank  283   b,  the fourth memory bank  283   d,  the sixth memory bank  283   f,  and the eighth memory bank  283   h,  respectively. 
         [0086]    The distributor  281  receives depunctured data having a plurality of bits, and distributes the plurality of bits included in the depunctured data to the eight memory banks  283   a,    283   b,    283   c,    283   d,    283   e,    283   f,    283   g,  and  283   h.  Each of the eight memory banks  283   a,    283   b,    283   c,    283   d,    283   e,    283   f,    283   g,  and  283   h  can store L bits, and the distributor  281  sequentially distributes L bits to each memory bank, starting from the first memory bank  283   a.    
         [0087]    Each of the eight memory banks  283   a,    283   b,    283   c,    283   d,    283   e,    283   f,    283   g,  and  283   h  receives L bits from the distributor  281 , and transmits the received L bits to some of the eight switches  285   a,    285   b,    285   c,    285   d,    285   e,    285   f,    285   g,  and  285   h.  Hereinafter, the L bits stored in one memory bank are referred to as block data. 
         [0088]    The first memory bank  283   a,  the third memory bank  283   c,  the fifth memory bank  283   e,  and the seventh memory bank  283   g  transmit the stored block data to the first switch  285   a,  the third switch  285   c,  the fifth switch  285   e,  and the seventh switch  285   g,  respectively. 
         [0089]    The second memory bank  283   b,  the fourth memory bank  283   d,  the sixth memory bank  283   f,  and the eighth memory bank  283   h  transmit the stored block data to the second switch  285   b,  the fourth switch  285   d,  the sixth switch  285   f,  and the eighth switch  285   h,  respectively. 
         [0090]    Each of the eight switches  285   a,    285   b,    285   c,    285   d,    285   e,    285   f,    285   g,  and  285   h  receives one or more block data, switches the received block data, and outputs a piece of block data. 
         [0091]    The first decoder  287   a  receives the block data from the first switch  285   a,  the second switch  285   b,  the third switch  285   c,  and the fourth switch  285   d,  processes the received four block data according to a Viterbi decoding algorithm, and outputs two block data. 
         [0092]    The second decoder  287   b  receives the block data from the fifth switch  285   e,  the sixth switch  285   f,  the seventh switch  285   g,  and the eighth switch  285   h,  and processes the received four block data according to the Viterbi decoding algorithm, and outputs two block data. 
         [0093]    The first decoder  287   a  and the second decoder  287   b  may correspond to block processing Viterbi decoding units using a block processing Viterbi decoding method. The first decoder  287   a  and the second decoder  287   b  may correspond to sliding block Viterbi decoders included in the block processing Viterbi decoding units. 
         [0094]    Next, the operation of the Viterbi decoding unit according to the exemplary embodiment of the present invention will be described with reference to  FIG. 6  and  FIG. 7 . 
         [0095]      FIGS. 6A and 6B  are diagrams illustrating the operation of the Viterbi decoding unit decoding depunctured data when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is 480 Mbps or less. 
         [0096]    When the data rate is equal to or lower than 480 Mbps, as shown in Table 2, the depuncturer  270  simultaneously outputs 6 bits of a plurality of bits included in the depunctured data, and the Viterbi decoding unit  280  simultaneously receives 6 bits of depunctured data. 
         [0097]    The distributor  281  of the Viterbi decoding unit  280  sequentially distributes L bits of the plurality of bits included in the depunctured data to each memory bank from the first memory bank  283   a  to the eighth memory bank  283   h.  When the distribution of bits up to the eighth memory bank  283   h  is completed, the distributor  281  distributes the depunctured data to the first memory bank  283   a  again. 
         [0098]    Then, each of the eight memory banks  283   a,    283   b,    283   c,    283   d,    283   e,    283   f,    283   g,  and  283   h  stores the L bits distributed by the distributor  281 . The L bits stored in one memory bank are referred to as block data (Bn, n=0, 1, 2, 3, . . . ). 
         [0099]      FIG. 6A  is a diagram illustrating block data stored in the eight memory banks  283   a,    283   b,    283   c,    283   d,    283   e,    283   f,    283   g,  and  283   h  with time. 
         [0100]    As shown in  FIG. 6A , when a time T 1  is required for one memory bank to write a piece of block data Bn, the first memory bank  283   a  receives the first block data B 0  from the distributor  281  and stores it during the period from 0 to T 1 . The second memory bank  283   b  receives the second block data B 1  from the distributor  281  and stores it during the period from T 1  to 2T 1 . 
         [0101]    The third memory bank  283   c  stores the third block data B 2  during the period from 2T 1  to 3T 1 , the fourth memory bank  283   d  stores the fourth block data B 3  during the period from 3T 1  to 4T 1 , and the fifth memory bank  283   e  stores the fifth block data B 4  during the period from 4T 1  to 5T 1 . In addition, the sixth memory bank  283   f  stores the sixth block data B 5  during the period from 5T 1  to 6T 1 , the seventh memory bank  283   g  stores the seventh block data B 6  during the period from 6T 1  to 7T 1 , and the eighth memory bank  283   h  stores the eighth block data B 7  during the period from 7T 1  to 8T 1 . 
         [0102]    Thereafter, the first to eight memory banks  283   a  to  283   h  store the next block data in the above-mentioned time order. In this case, each memory bank deletes the previously stored block data and stores new block data. 
         [0103]      FIG. 6B  is a diagram illustrating the input and output of the first decoder  287   a.    
         [0104]    As shown in  FIG. 6B , first, the first decoder  287   a  receives the first block data B 0 , the second block data B 1 , the third block data B 2 , and the fourth block data B 3 , processes the received block data B 0 , B 1 , B 2 , and B 3  according to the Viterbi decoding algorithm, and outputs the second block data B 1  and the third block data B 2 . 
         [0105]    In this case, after the time 4T 1  has elapsed, the first decoder  287   a  may receive the first block data B 0  stored in the first memory bank  283   a,  the second block data B 1  stored in the second memory bank  283   b,  the third block data B 2  stored in the third memory bank  283   c,  and the fourth block data B 3  stored in the fourth memory bank  283   d  through the first switch  285   a,  the second switch  285   b,  the third switch  285   c,  and the fourth switch  285   d,  respectively. 
         [0106]    Then, the first decoder  287   a  receives the third block data B 2 , the fourth block data B 3 , the fifth block data B 4 , and the sixth block data B 5 , processes the received block data B 2 , B 3 , B 4 , and B 5  according to the Viterbi decoding algorithm, and outputs the fourth block data B 3  and the fifth block data B 4 . 
         [0107]    In this case, after the time 6T 1  has elapsed, the first decoder  287   a  may receive the third block data B 2  stored in the third memory bank  283   c,  the fourth block data B 3  stored in the fourth memory bank  283   d,  the fifth block data B 4  stored in the fifth memory bank  283   e,  and the sixth block data B 5  stored in the sixth memory bank  283   f  through the first switch  285   a,  the second switch  285   b,  the third switch  285   c,  and the fourth switch  285   d,  respectively. 
         [0108]    Thereafter, the first decoder  287   a  receives four block data, processes the four block data according to the Viterbi decoding algorithm, and outputs two block data, using the same method as described above. 
         [0109]    The outputs of the four switches  285   a,    285   b,    285   c,  and  285   d  connected to the first decoder  287   a  with time may be shown as in Table 3. 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 3 
               
             
             
               
                   
                   
               
               
                   
                 Time 
               
             
          
           
               
                   
                 &lt;4T 1   
                 4T 1   
                 6T 1   
                 8T 1   
                 10T 1   
                 12T 1   
                 . . . 
               
               
                   
                   
               
             
          
           
               
                 Switch 
                 OFF 
                 0 
                 1 
                 2 
                 3 
                 0 
                 . . . 
               
               
                 selection 
               
               
                 Output 
                   
                 283a 
                 283c 
                 283e 
                 283g 
                 283a 
                 . . . 
               
               
                 of 285a 
               
               
                 Output 
                   
                 283b 
                 283d 
                 283f 
                 283h 
                 283b 
                 . . . 
               
               
                 of 285b 
               
               
                 Output 
                   
                 283c 
                 283e 
                 283g 
                 283a 
                 283c 
                 . . . 
               
               
                 of 285c 
               
               
                 Output 
                   
                 283d 
                 283f 
                 283h 
                 283b 
                 283d 
                 . . . 
               
               
                 of 285d 
               
               
                   
               
             
          
         
       
     
         [0110]      FIGS. 7A and 7B  are diagrams illustrating the operation of the Viterbi decoding unit decoding depunctured data when the data rate of the ultra-wideband system according to the exemplary embodiment of the present invention is higher than 480 Mbps. 
         [0111]    When the data rate is higher than 480 Mbps, as shown in Table 2, the depuncturer  270  simultaneously outputs 12 bits of a plurality of bits included in the depunctured data, and the Viterbi decoding unit  280  simultaneously receives 12 bits of depunctured data. 
         [0112]    The distributor  281  of the Viterbi decoding unit  280  sequentially distributes L bits of the plurality of bits included in the depunctured data to each memory bank from the first memory bank  283   a  to the eighth memory bank  283   h.  When the distribution of bits up to the eighth memory bank  283   h  is completed, the distributor  281  distributes the depunctured data to the first memory bank  283   a  again. 
         [0113]    Then, each of the eight memory banks  283   a,    283   b,    283   c,    283   d,    283   e,    283   f,    283   g,  and  283   h  stores the L bits distributed by the distributor  281 . The L bits stored in one memory bank is referred to as block data (Bn, n=0, 1, 2, 3, . . . ). 
         [0114]      FIG. 7A  is a diagram illustrating block data stored in the eight memory banks  283   a,    283   b,    283   c,    283   d,    283   e,    283   f,    283   g,  and  283   h  with time. 
         [0115]    As shown in  FIG. 7A , when a time T 2  is required for one memory bank to write a piece of block data Bn, the first memory bank  283   a  receives the first block data B 0  from the distributor  281  and stores it during the period from 0 to T 2 . The second memory bank  283   b  receives the second block data B 1  from the distributor  281  and stores it during the period from T 2  to 2T 2 . 
         [0116]    The third memory bank  283   c  stores the third block data B 2  during the period from 2T 2  to 3T 2 , the fourth memory bank  283   d  stores the fourth block data B 3  during the period from 3T 2  to 4T 2 , and the fifth memory bank  283   e  stores the fifth block data B 4  during the period from 4T 2  to 5T 2 . In addition, the sixth memory bank  283   f  stores the sixth block data B 5  during the period from 5T 2  to 6T 2 , the seventh memory bank  283   g  stores the seventh block data B 6  during the period from 6T 2  to 7T 2 , and the eighth memory bank  283   h  stores the eighth block data B 7  during the period from 7T 2  to 8T 2 . 
         [0117]    Thereafter, the first to eight memory banks  283   a  to  283   h  store the next block data in the above-mentioned time order. In this case, each memory bank deletes the previously stored block data and stores new block data. 
         [0118]      FIG. 7B  is a diagram illustrating the input and output of the first decoder  287   a  and the second decoder  287   b.    
         [0119]    As shown in  FIG. 7B , first, the first decoder  287   a  receives the first block data B 0 , the second block data B 1 , the third block data B 2 , and the fourth block data B 3 , processes the received block data B 0 , B 1 , B 2 , and B 3  according to the Viterbi decoding algorithm, and outputs the second block data B 1  and the third block data B 2 . 
         [0120]    In this case, after the time 4T 2  has elapsed, the first decoder  287   a  may receive the first block data B 0  stored in the first memory bank  283   a,  the second block data B 1  stored in the second memory bank  283   b,  the third block data B 2  stored in the third memory bank  283   c,  and the fourth block data B 3  stored in the fourth memory bank  283   d  through the first switch  285   a,  the second switch  285   b,  the third switch  285   c,  and the fourth switch  285   d,  respectively. 
         [0121]    Then, the second decoder  287   b  receives the third block data B 2 , the fourth block data B 3 , the fifth block data B 4 , and the sixth block data B 5 , processes the received block data B 2 , B 3 , B 4 , and B 5  according to the Viterbi decoding algorithm, and outputs the fourth block data B 3  and the fifth block data B 4 . 
         [0122]    In this case, after the time 6T 2  has elapsed, the second decoder  287   b  may receive the third block data B 2  stored in the third memory bank  283   c,  the fourth block data B 3  stored in the fourth memory bank  283   d,  the fifth block data B 4  stored in the fifth memory bank  283   e,  and the sixth block data B 5  stored in the sixth memory bank  283   f  through the fifth switch  285   e,  the sixth switch  285   f,  the seventh switch  285   g,  and the eighth switch  285   h,  respectively. 
         [0123]    Then, the first decoder  287   a  receives the fifth block data B 4 , the sixth block data B 5 , the seventh block data B 6 , and the eighth block data B 7 , processes the received block data B 4 , B 5 , B 6 , and B 7  according to the Viterbi decoding algorithm, and outputs the sixth block data B 5  and the seventh block data B 6 . 
         [0124]    In this case, after the time 8T 2  has elapsed, the first decoder  287   a  may receive the fifth block data B 4  stored in the fifth memory bank  283   e,  the sixth block data B 5  stored in the sixth memory bank  283   f,  the seventh block data B 6  stored in the seventh memory bank  283   g,  and the eighth block data B 7  stored in the eighth memory bank  283   h  through the first switch  285   a,  the second switch  285   b,  the third switch  285   c,  and the fourth switch  285   d,  respectively. 
         [0125]    Then, the second decoder  287   b  receives the seventh block data B 6 , the eighth block data B 7 , the ninth block data B 8 , and the tenth block data B 9 , processes the plurality of received block data B 6 , B 7 , B 8 , and B 9  according to the Viterbi decoding algorithm, and outputs the eighth block data B 7  and the ninth block data B 8 . 
         [0126]    In this case, after the time 10T 2  has elapsed, the second decoder  287   b  may receive the seventh block data B 6  stored in the seventh memory bank  283   g,  the eighth block data B 7  stored in the eighth memory bank  283   h,  the ninth block data B 8  stored in the first memory bank  283   a,  and the tenth block data B 9  stored in the second memory bank  283   b  through the fifth switch  285   e,  the sixth switch  285   f,  the seventh switch  285   g,  and the eighth switch  285   h,  respectively. 
         [0127]    Thereafter, each of the first decoder  287   a  and the second decoder  287   b  receives four block data, processes the four block data according to the Viterbi decoding algorithm, and outputs two block data, using the same method as described above. 
         [0128]    The outputs of the four switches  285   a,    285   b,    285   c,  and  285   d  connected to the first decoder  287   a  and the outputs of the four switches  285   e,    285   f,    285   g,  and  285   h  connected to the second decoder  287   b  may be shown as in Table 4. 
         [0129]    (Table 4) 
         [0000]    
       
         
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 4 
               
               
                   
               
               
                 Time 
                 &lt;4T 2   
                 4T 2   
                 6T 2   
                 8T 2   
                 10T 2   
                 12T 2   
                 14T 2   
                 16T 2   
                 . . . 
               
               
                   
               
             
             
               
                 Switch 
                 OFF 
                 0 
                 0 
                 2 
                 2 
                 0 
                 0 
                 2 
                 . . . 
               
               
                 selection 
               
               
                 Output 
                   
                 283a 
                 283a 
                 283e 
                 283e 
                 283a 
                 283a 
                 283e 
                 . . . 
               
               
                 of 285a 
               
               
                 Output 
                   
                 283b 
                 283b 
                 283f 
                 283f 
                 283b 
                 283b 
                 283f 
                 . . . 
               
               
                 of 285b 
               
               
                 Output 
                   
                 283c 
                 283c 
                 283g 
                 283g 
                 283c 
                 283c 
                 283g 
                 . . . 
               
               
                 of 285c 
               
               
                 Output 
                   
                 283d 
                 283d 
                 283h 
                 283h 
                 283d 
                 283d 
                 283h 
                 . . . 
               
               
                 of 285d 
               
               
                 Switch 
                 OFF 
                 OFF 
                 3 
                 3 
                 1 
                 1 
                 3 
                 3 
               
               
                 selection 
               
               
                 Output 
                   
                   
                 283c 
                 283c 
                 283g 
                 283g 
                 283c 
                 283c 
               
               
                 of 285e 
               
               
                 Output 
                   
                   
                 283d 
                 283d 
                 283h 
                 283h 
                 283d 
                 283d 
               
               
                 of 285f 
               
               
                 Output 
                   
                   
                 283e 
                 283e 
                 283a 
                 283a 
                 283e 
                 283e 
               
               
                 of 285g 
               
               
                 Output 
                   
                   
                 283f 
                 283f 
                 283b 
                 283b 
                 283f 
                 283f 
               
               
                 of 285h 
               
               
                   
               
             
          
         
       
     
         [0130]    The above-described exemplary embodiments of the present invention can be applied to programs that allow computers to execute functions corresponding to the configurations of the exemplary embodiments of the invention or recording media including the programs as well as the method and apparatus. Those skilled in the art can easily implement the applications from the above-described exemplary embodiments of the present invention. 
         [0131]    While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.