Abstract:
Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first-type edges of a first signal to generate a first detection signal. The second edge detector is for detecting the first-type edges of a second signal to generate a second detection signal. The pulse reshaping controller is for receiving the first detection signal and the second detection signal, and for generating a first control signal to the first edge detector and generating a second control signal to the second edge detector. In addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This continuation application claims the benefit of co-pending U.S. patent application Ser. No. 11/278,814, filed on Apr. 6, 2006 and included herein by reference. 
    
    
     BACKGROUND 
     The present disclosure relates to phase frequency detectors, and more particularly, to phase frequency detectors having limited output pulse width. 
     Phase-locked loop (PLL) can be applied in a variety of applications, such as clock/data recovery, frequency or phase modulation/demodulation, and generating clocks with stable frequency. In general, a conventional PLL includes a phase frequency detector (PFD) for detecting phase difference and frequency difference between a reference signal and a feedback signal; a charge-pump for generating an output current according to the detection result of the PFD; and a loop filter for adjusting the operation of a voltage-controlled oscillator (VCO) according to the output current until the frequency and phase of the feedback signal match that of the reference signal. 
     Typically, the loop bandwidth of the conventional PLL is designed one order of magnitude less than the frequency of the reference signal in order to maintain the loop stability. As the frequency of the reference signal decreases, the loop bandwidth of the PLL should be lowered correspondingly. In such a scheme, a large capacitor is required by the loop filter to suppress the jitter of the VCO. As a result, the circuitry area and volume is significantly increased. 
     SUMMARY 
     It is therefore an objective of the present disclosure to provide phase frequency detectors having limited output pulse width and associated methods to solve the above-mentioned problems. 
     An exemplary embodiment of a phase frequency detector is disclosed. The phase frequency detector includes: a first edge detector for detecting first-type edges of a first signal to generate a first detection signal; a second edge detector for detecting the first-type edges of a second signal to generate a second detection signal; and a pulse reshaping controller for receiving the first detection signal and the second detection signal. The pulse reshaping controller generates a first control signal to the first edge detector and a second control signal to the second edge detector; in addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller. 
     Another exemplary embodiment of a phase frequency detector is disclosed. The phase frequency detector includes: a first edge detector for detecting an edge of a first signal to generate a first detection signal; a second edge detector for detecting an edge of a second signal to generate a second detection signal; and a pulse reshaping controller for generating a first output signal and a second output signal according to the first and the second detection signal. A pulse width difference between the first output signal and the second output signal represents an equivalent output pulse width, and the equivalent output pulse width is clamped when a phase difference between the first signal and the second signal exceeds a predetermined degree. 
     An exemplary embodiment of a method for phase frequency detection is disclosed. The method includes: detecting an edge of a first signal to generate a first output signal; detecting an edge of a second signal to generate a second output signal, wherein a pulse width difference between the first output signal and the second output signal represents an equivalent output pulse width; delaying at least one of the first and the second output signal and generating at least a control signal; and limiting the equivalent output pulse width according to at least the control signal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a phase frequency detector for use in a phase-locked loop (PLL) according to an exemplary embodiment. 
         FIG. 2  and  FIG. 3  are timing diagrams illustrating the operations of the phase frequency detector of  FIG. 1  with respect to different cases. 
         FIG. 4  is an illustration of the input-output characteristic of the phase frequency detector of  FIG. 1  according to an exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     Please refer to  FIG. 1 , which shows a block diagram of a phase frequency detector  100  for use in a phase-locked loop (PLL) according to an exemplary embodiment. The phase frequency detector  100  comprises combination logic  170 , two edge detectors  110  and  120 , two latch units  130  and  140 , two delay units  150  and  160 , and two logic units  180  and  190 . As shown, the first latch unit  130  is coupled to the first edge detector  110  and the first delay unit  150 ; the second latch unit  140  is coupled to the second edge detector  120  and the second delay unit  160 ; the combination logic  170  is coupled to the first latch unit  130  and the second latch unit  140 ; the first logic unit  180  is coupled to the first edge detector  110 , the first delay unit  150 , and the combination logic  170 ; and the second logic unit  190  is coupled to the second edge detector  120 , the second delay unit  160 , and the combination logic  170 . 
     In operations, the phase frequency detector  100  receives a reference signal CLK_REF and a feedback signal CLK_FB, which is generated from the PLL, and generates two output signals UP and DN to control the charge/discharge operation of a charge pump, which is the following stage of the phase frequency detector  100 . Hereinafter, implementations and operations of the components of the phase frequency detector  100  will be described in more detail. 
     The first edge detector  110  is arranged for detecting first-type edges of the reference signal CLK_REF to generate a first detection signal DS 1 , and for changing the level of the first detection signal DS 1  according to a first control signal CS 1 . The second edge detector  120  is arranged for detecting the first-type edges of the feedback signal CLK_FB to generate a second detection signal DS 2 , and for changing the level of the second detection signal DS 2  according to a second control signal CS 2 . In practice, the first-type edges mentioned above are either rising edges or falling edges. 
     Preferably, the edge detectors  110  and  120  are edge-trigger edge detectors. In one embodiment, the first and second control signals CS 1  and CS 2  serve as reset signals for respectively resetting the first edge detector  110  and the second edge detector  120 . In such a scheme, the first edge detector  110  sets the first detection signal DS 1  to logic low during the active period of the first control signal CS 1 , and the second edge detector  120  sets the second detection signal DS 2  to logic low during the active period of the second control signal CS 2 . In practice, both the first control signal CS 1  and the second control signal CS 2  may be low active, but this is merely an example rather than a restriction of the practical implementations. 
     In the phase frequency detector  100 , the first latch unit  130  is arranged for latching the first detection signal DS 1  to generate a first output signal UP, and the second latch unit  140  is arranged for latching the second detection signal DS 2  to generate a second output signal DN. In addition, the first latch unit  130  changes the level of the first output signal UP according to a third control signal CS 3 . Similarly, the second latch unit  140  changes the level of the second output signal DN according to the third control signal CS 3 . In this embodiment, the third control signal CS 3  serves as a reset signal for resetting both the first latch unit  130  and the second latch unit  140 . Thus, during the active period of the third control signal CS 3 , the first latch unit  130  and the second latch unit  140  respectively set the first output signal UP and the second output signal DN to logic low state. Preferably, the third control signal CS 3  is low active, but this is merely an example rather than a restriction of the practical implementations. 
     In a preferred embodiment, the edge detectors  110  and  120  are implemented with D-type flip-flops as illustrated in  FIG. 1 . As shown in  FIG. 1 , the first edge detector  110  comprises a data input terminal coupled to logic “high”; a clock input terminal coupled to the reference signal CLK_REF; a data output terminal for providing the first detection signal DS 1 ; and a control input terminal Ci coupled to the first control signal CS 1 . Similarly, the second edge detector  120  comprises a data input terminal coupled to logic “high”; a clock input terminal coupled to the feedback signal CLK_FB; a data output terminal for providing the second detection signal DS 2 ; and a control input terminal Ci coupled to the second control signal CS 2 . 
     Additionally, the first and second latch units  130  and  140  may also be implemented with D-type flip-flops as shown in  FIG. 1 . In this embodiment, the first latch unit  130  comprises a data input terminal coupled to logic “high”; a clock input terminal coupled to the data output terminal of the first edge detector  110  for receiving the first detection signal DS 1 ; a data output terminal for providing the first output signal UP; and a control input terminal Ci coupled to the third control signal CS 3 . The second latch unit  140  comprises a data input terminal coupled to logic “high”; a clock input terminal coupled to the data output terminal of the second edge detector  120  for receiving the second detection signal DS 2 ; a data output terminal for providing the second output signal DN; and a control input terminal Ci coupled to the third control signal CS 3 . 
     The first delay unit  150  is arranged for applying a first delay on the first output signal UP to generate a first delayed signal D 1 . The second delay unit  160  is arranged for applying a second delay on the second output signal DN to generate a second delayed signal D 2 . In a preferred embodiment, the first delay and the second delay are substantially the same, so the first and second delay units  150  and  160  can be designed substantially the same. Please note that this configuration is merely a preferred embodiment and not a restriction of the practical implementations. For example, in another embodiment, the phase frequency detector  100  further comprises a delay setting unit (not shown) coupled to the first delay unit  150  and/or the second delay unit  160  for programming the first and/or second delay. 
     On the other hand, the combination logic  170  is designed for performing a predetermined logical operation on the first output signal UP and the second output signal DN to produce the third control signal CS 3 , which is employed to control the first and second latch units  130  and  140 . For example, the combination logic  170  may perform a logic AND operation on the first output signal UP and the second output signal DN to generate the third control signal CS 3 . 
     In the phase frequency detector  100 , the first logic unit  180  is employed for performing a first logical operation on the first delayed signal D 1  and the third control signal CS 3  to generate the first control signal CS 1 , and the second logic unit  190  is employed for performing a second logical operation on the second delayed signal D 2  and the third control signal CS 3  to generate the second control signal CS 2 . Preferably, the first and second logical operations are substantially the same. For example, each of the first logic unit  180  and the second logic unit  190  of this embodiment is realized by a logic AND gate as shown in  FIG. 1 . 
     Please refer to  FIG. 2  and  FIG. 3 , which are timing diagrams illustrating the operations of the phase frequency detector  100  with respect to different cases. For the purpose of explanatory convenience in the following description, it is herein assumed that the first delay provided by the first delay unit  150  and the second delay provided by the second delay unit  160  are both Td. As illustrated in  FIG. 2 , in the case where a phase difference T between the reference signal CLK_REF and the feedback signal CLK_FB is less than the delay Td provided by the first and second delay units  150  and  160 , the equivalent output pulse width of the phase frequency detector  100  is proportional to the phase difference T between the reference signal CLK_REF and the feedback signal CLK_FB. Specifically, the difference between the first output signal UP and the second output signal DN is proportional to the phase difference T. 
     On the contrary, as illustrated in  FIG. 3 , in the case where the phase difference T between the reference signal CLK_REF and the feedback signal CLK_FB is greater than the delay Td of the first and second delay units  150  and  160 , the pulse width of the first output signal UP is limited in the delay Td and not proportional to the phase difference T between the reference signal CLK_REF and the feedback signal CLK_FB. In other words, the phase frequency detector  100  has a limited equivalent output pulse width under such a situation. 
       FIG. 4  is an illustration of the input-output characteristic of the phase frequency detector  100  according to an exemplary embodiment. In  FIG. 4 , the x-axis is the degree of phase difference between the reference signal CLK_REF and the feedback signal CLK_FB and the y-axis is the equivalent output voltage of the phase frequency detector  100 , which corresponds to the pulse width difference between the first output signal UP and the second output signal DN. As shown, when the degree of phase difference between the reference signal CLK_REF and the feedback signal CLK_FB is between −Th 1  and Th 1 , the equivalent output voltage of the phase frequency detector  100  is proportional to the degree of phase difference. On the other hand, when the degree of phase difference between the reference signal CLK_REF and the feedback signal CLK_FB is located within an interval ranging from Th 1  to  360 , the equivalent output voltage of the phase frequency detector  100  is clamped at a predetermined value V L . Similarly, the equivalent output voltage of the phase frequency detector  100  is clamped at another predetermined value −V L  when the degree of phase difference between the reference signal CLK_REF and the feedback signal CLK_FB is between −Th 1  and − 360 . The threshold degree Th 1  is determined by the delay Td provided by the first and second delay units  150  and  160 . 
     Since the equivalent output pulse width of the phase frequency detector  100  is clamped when the phase difference between the reference signal CLK_REF and the feedback signal CLK_FB is greater than the delay Td, the maximum output current generated by the charge pump following the phase frequency detector  100  is restricted at a certain value. It should be appreciated by those skilled in the art that the output voltage generated by a loop filter (not shown) following the charge pump is also clamped at a certain level when the phase difference T between the reference signal CLK_REF and the feedback signal CLK_FB is greater than the delay Td. As a result, the required capacitance of the loop filter for suppressing the jitter of the voltage-controlled oscillator (VCO) in the PLL is significantly reduced. 
     Please note that each of the first, second, and third control signals CS 1 , CS 2 , and CS 3  in the foregoing embodiments are level trigger signals, however, this is merely a preferred embodiment rather than a restriction of the practical implementations. In practice, those control signals may be designed as edge trigger signals. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.