Abstract:
A common-mode feedback circuit is provided. An amplifier with a common-mode feedback circuit is compensated by adding a compensating unit so that the amplifier totally has two poles and one zero in its frequency response. Accordingly, the gain of the amplifier is not sacrificed, and both the stability and the phase margin of the circuit are improved.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to an amplifier, and more particularly, to an amplifier with a common-mode feedback (CMFB) circuit. 
   2. Description of the Related Art 
   Regarding a fully differential operational amplifier (FD Op-Amp) with a feedback circuit, the feedback circuit determines only differential output voltages, but does not affect common-mode output voltages. Thus, an additional circuit is required for the FD Op-Amp to control the common-mode output voltage V cmo , so that the common-mode output voltage V cmo  approaches a reference voltage value (usually halfway between two operating voltages). Referring to  FIG. 1 , a FD Op-Amp with a common-mode feedback circuit  100  comprises a FD Op-Amp  110 , a common-mode detector  120  and a CMFB amplifier  130 . Both the common-mode detector  120  and the CMFB amplifier  130  form a common-mode feedback circuit. The configuration and the operation of the common-mode feedback circuit are described on pages 816-835 of a book entitled “Analysis and Design of Analog Integrated Circuits,” by Gray et al, 4th Edition, 2001, Wiley, and on pages 314-324 of a book entitled “Design of Analog CMOS Integrated Circuits,” by Razavi, 2001, McGraw Hill. 
   The FD Op-Amp with a CMFB circuit  100  needs to be well compensated; otherwise, a noise injection into the common-mode output voltage V cmo  could cause the common-mode output voltage V cmo  to ring or oscillate. Usually, the compensation method for amplifier  100  can be classified as source degeneration and current reduction. The source degeneration compensation is to provide a resistor coupled between two transistors at two input terminals of the CMFB amplifier  130 , enhancing stability by reducing the gain of the CMFB amplifier  130 . The current reduction compensation is to reduce the amount of the control current of the FD Op-Amp  110  to 1/N (N is an integer and N&gt;&gt;1) so as to enhance circuit stability.  FIG. 2  shows two frequency responses, one is an uncompensated FD Op-Amp with a CMFB circuit and the other is a compensated FD Op-Amp with a CMFB circuit using above-mentioned compensation method. Referring to  FIG. 2 , it is obvious that the compensated FD Op-Amp using above-mentioned compensation method sacrifices larger gain and larger bandwidth in order to obtain stability. 
   SUMMARY OF THE INVENTION 
   In view of the above-mentioned problems, an object of the invention is to provide a compensating device into the CMFB circuit so as to add an additional pole and an additional zero in the frequency response. And such compensation method can maintain amplifier gain, improves phase margins and enhances circuit stability. 
   To achieve the above-mentioned object, the amplifier comprise: an operational amplifier having a first output terminal and a second output terminal for amplifying an input signal and generating an output signal; a common-mode detector coupled between the first output terminal and the second output terminal for detecting a common-mode output voltage of the output signal; and, a common-mode feedback amplifier for generating a control signal to the operational amplifier in accordance with a reference voltage, comprising: a first transistor for receiving the common-mode output voltage; a second transistor for receiving the reference voltage; and, a first compensating capacitor for compensating the amplifier. 
   Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: 
       FIG. 1  is a block diagram of a conventional FD Op-Amp with a CMFB circuit. 
       FIG. 2  shows the frequency responses of an uncompensated FD Op-Amp with a CMFB circuit and a compensated FD Op-Amp with a CMFB circuit according to the prior art. 
       FIG. 3  shows a frequency response of an uncompensated FD Op-Amp with a CMFB circuit and a frequency response of a compensated FD Op-Amp with a CMFB circuit according to the present invention. 
       FIG. 4  is a block diagram of an amplifier according to a first embodiment of the present invention. 
       FIG. 5  is a block diagram of an amplifier according to a second embodiment of the present invention. 
       FIG. 6  is a block diagram of an amplifier according to a third embodiment of the present invention. 
       FIG. 7  is a block diagram of an amplifier according to a fourth embodiment of the present invention. 
       FIG. 8  is a block diagram of an amplifier according to a fifth embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The amplifier with a CMFB circuit of the invention will be described with reference to the accompanying drawings. 
     FIG. 3  shows a frequency response of an uncompensated FD Op-Amp with a CMFB circuit and a frequency response of a compensated FD Op-Amp with a CMFB circuit according to the present invention. Referring to  FIG. 3 , originally, an uncompensated FD Op-Amp with a CMFB circuit has two poles P 1 , P 2  in its frequency response. In order to keep the gain, a pole P 3  and a zero N 1  are introduced to improve phase margins and enhance circuit stability. A total of two poles P 1 , P 3  and one zero N 1  are produced in the frequency response, whereas the pole P 2  is moved to a higher frequency region (not shown). Thus, the invention adds an additional circuit to create the pole P 3  and the zero N 1 . The additional circuit is implemented with a combination of capacitors and resistors, as will be described in the following five embodiments. 
     FIG. 4  is a block diagram of an amplifier according to a first embodiment of the present invention. Referring to  FIG. 4 , an amplifier  400  comprises a FD Op-Amp  110 , a common-mode detector  420 , a CMFB amplifier  430  and a compensating unit Z 1 . Wherein, the common-mode detector  420  and the CMFB amplifier  430  form a CMFB circuit  440  and the FD Op-Amp  110  is a two-stage Op-Amp used to amplify an input signal V in  and output a differential signal (V on −V op ). The common-mode detector  420 , including two identical resistors R 1  and two identical capacitors C 1 , is employed to detect a common-mode output voltage (V cmo =(V on +V op )/2). The CMFB amplifier  430  comprises a current source  431 , two PMOS transistors  432 ,  433  and two NMOS transistors  434 ,  435 . The current source  431  supplies a current to the CMFB amplifier  430 . The CMFB amplifier  430  uses the gate of the transistor  433  to receive a reference voltage V ref  and uses the gate of the transistor  432  to receive the common-mode output voltage V cmo  to generate a control signal (measured at the source of the transistor  432 ) to the FD Op-Amp  110 . The control signal generated by CMFB amplifier  430  is used to modify the CMFB output voltage V cmo , to thereby force the CMFB output voltage V cmo  and the reference voltage V ref  to be equivalent. According to the first embodiment, the compensating unit Z 1  is a compensating capacitor C 2 , coupled between the gate of the transistor  432  and an operating voltage V ss , and used to compensate the amplifier  400 . After the compensating capacitor C 2  is added to the CMFB amplifier  430 , a pole P 3  and a zero N 1  are created in the frequency response of the amplifier  400 . The transfer function of the amplifier  400  can be expressed as 
               T   ⁡     (   s   )       =         V   cmo         (       V   op     +     V   on       )     /   2       =         1     sC   2           R   1     //       C   1     +     1     sC   2             =         1     sC   2             R   1       1   +       sR   1     ⁢     C   1           +     1     sC   2           =       1   +       sR   1     ⁢     C   1           1   +       sR   1     ⁡     (       C   1     +     C   2       )                   ,         
where a zero frequency is
 
             ω             ⁢     N   ⁢           ⁢   1         =     1             ⁢       R             ⁢   1       ⁢           ⁢     C             ⁢   1                   
and a pole frequency is
 
   
     
       
         
           
             ω 
             
               p 
               ⁢ 
               
                   
               
               ⁢ 
               3 
             
           
           = 
           
             
               1 
               
                 
                   R 
                   1 
                 
                 ⁡ 
                 
                   ( 
                   
                     
                       C 
                       1 
                     
                     + 
                     
                       C 
                       2 
                     
                   
                   ) 
                 
               
             
             . 
           
         
       
     
   
   According to the transfer function T(s), modifying the capacitance value of the compensating capacitor C 2  can cause the zero frequency ω N1  to be several times higher than the pole frequency ω P3 . As the capacitance value of the compensating capacitor C 2  increases, the phase margin also increases, resulting in a more stable amplifier  400 . In one embodiment, capacitor C 2  can be designed larger than capacitor C 1 . Note that both the zero N 1  and the pole P 3  are required to be located well below the unit gain frequency according to the uncompensated frequency response. 
     FIG. 5  is a block diagram of an amplifier according to a second embodiment of the present invention. Referring to  FIG. 5 , compared with the first embodiment, a CMFB amplifier  530  in the second embodiment additionally includes a compensating unit Z 2  coupled between two nodes E, F of the CMFB amplifier  530  to compensate the amplifier  500 . The compensating unit Z 2  comprises two identical capacitors C 3  and a compensating resistor R 2 . The gain of the amplifier  500  is A V1 =g m r 0 , where g m , r 0  are the conductance of the PMOS transistor  432  and the output resistor of the NMOS transistor  434 , respectively. After the compensating unit Z 2  is added, the gain of the amplifier  500  is 
   
     
       
         
           
             
               A 
               
                 V 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 2 
               
             
             = 
             
               
                 
                   g 
                   m 
                 
                 ⁡ 
                 
                   ( 
                   
                     
                       r 
                       0 
                     
                     // 
                     
                       Z 
                       2 
                     
                   
                   ) 
                 
               
               = 
               
                 
                   
                     g 
                     m 
                   
                   ⁡ 
                   
                     ( 
                     
                       
                         r 
                         0 
                       
                       // 
                       
                         ( 
                         
                           
                             1 
                             
                               sC 
                               3 
                             
                           
                           + 
                           
                             R 
                             2 
                           
                         
                         ) 
                       
                     
                     ) 
                   
                 
                 = 
                 
                   
                     g 
                     m 
                   
                   ⁢ 
                   
                     
                       
                         
                           sR 
                           2 
                         
                         ⁢ 
                         
                           C 
                           3 
                         
                         ⁢ 
                         
                           r 
                           0 
                         
                       
                       + 
                       
                         r 
                         0 
                       
                     
                     
                       
                         s 
                         ⁡ 
                         
                           ( 
                           
                             
                               
                                 R 
                                 2 
                               
                               ⁢ 
                               
                                 C 
                                 3 
                               
                             
                             + 
                             
                               
                                 r 
                                 0 
                               
                               ⁢ 
                               
                                 C 
                                 3 
                               
                             
                           
                           ) 
                         
                       
                       + 
                       1 
                     
                   
                 
               
             
           
           , 
         
       
     
   
   where the zero frequency is 
             ω     N   ⁢           ⁢   1       =     1       R   2     ⁢     C   3               
and the pole frequency is
 
   
     
       
         
           
             ω 
             
               P 
               ⁢ 
               
                   
               
               ⁢ 
               3 
             
           
           = 
           
             
               1 
               
                 
                   C 
                   3 
                 
                 ⁡ 
                 
                   ( 
                   
                     
                       R 
                       2 
                     
                     + 
                     
                       r 
                       0 
                     
                   
                   ) 
                 
               
             
             . 
           
         
       
     
   
   Thus, after the compensating unit Z 2  is added to the CMFB amplifier  530 , the compensated frequency response maintains the same gain as the uncompensated frequency response does (as shown in  FIG. 3 ); moreover, an additional pole and an additional zero are introduced, making the phase margin of the compensated amplifier  500  more ideal than that of a uncompensated amplifier. In addition, according to the gain A V2 , modifying the ratio of the compensating resistor R 2  to the compensating resistor r 0  can cause the zero frequency ω N1  to be several times higher than the pole frequency ω P3 . As the resistance value of the compensating resistor r 0  increases, the phase margin also increases, resulting in a more stable amplifier  500 . 
     FIG. 6  is a block diagram of an amplifier according to a third embodiment of the present invention. Referring to  FIG. 6 , compared with two above-mentioned embodiments, a CMFB amplifier  630  in the third embodiment additionally includes a compensating unit Z 3 , coupled between a node G and the ground voltage V ss , to compensate the amplifier  600 . The compensating unit Z 3  comprises a compensating capacitor C 3  and a compensating resistor R 2 . The compensating resistor R 2  is respectively coupled between a terminal of the compensating capacitor C 3  and the drain of the transistor  432  while the other terminal of the compensating capacitor C 3  is coupled to the ground voltage V ss . It should be noted that a differential compensating unit Z 2  is employed in the CMFB amplifier  530  to achieve the goal of additionally creating both the zero N 1  and the pole P 3 , whereas a single-ended compensating unit Z 3  is employed in the CMFB amplifier  630  to achieve the same goal. Since the gain A V2  derived from the amplifier  500  is the same as that derived from the amplifier  600 , the description is omitted herein. 
     FIG. 7  is a block diagram of an amplifier according to a fourth embodiment of the present invention. Referring to  FIG. 7 , compared with the above-mentioned embodiments, a CMFB amplifier  730  in the fourth embodiment additionally includes a compensating unit Z 4 , coupled between two nodes T, S (at the drains of the transistors  432 ,  433 ), to compensate the amplifier  700 ; moreover, the connectivity between transistors  434 ,  435  is quite different. The compensating unit Z 4  comprises a compensating capacitor C 3 , a compensating resistor R 2  and two identical compensating resistors R 3 . One of two identical compensating resistors R 3  is coupled between the drain and the gate of the NMOS transistor  434  while the other is coupled between the drain and the gate of the NMOS transistor  435 . 
   After the compensating unit Z 4  is added, the gain of the amplifier  700  can be derived as follows. 
   
     
       
         
           
             A 
             
               V 
               ⁢ 
               
                   
               
               ⁢ 
               3 
             
           
           = 
           
             
               
                 g 
                 m 
               
               ⁡ 
               
                 ( 
                 
                   
                     r 
                     0 
                   
                   // 
                   
                     Z 
                     4 
                   
                 
                 ) 
               
             
             = 
             
               
                 g 
                 m 
               
               ⁡ 
               
                 ( 
                 
                   
                     
                       r 
                       0 
                     
                     // 
                     
                       ( 
                       
                         
                           1 
                           
                             sC 
                             3 
                           
                         
                         + 
                         
                           R 
                           2 
                         
                       
                       ) 
                     
                   
                   // 
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                 
                 ) 
               
             
           
         
       
     
     
       
         
           
             For 
             ⁢ 
             
                 
             
             ⁢ 
             
               R 
               3 
             
             ⁢ 
             
               &lt;&lt; 
               
                 r 
                 0 
               
             
           
           , 
           
             
               A 
               
                 V 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 3 
               
             
             = 
             
               
                 g 
                 
                   
                       
                   
                   ⁢ 
                   m 
                 
               
               ⁢ 
               
                 
                   
                       
                   
                   ⁢ 
                   
                     
                       
                         sR 
                         
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         C 
                         
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         R 
                         
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                     
                     + 
                     
                       R 
                       
                         
                             
                         
                         ⁢ 
                         3 
                       
                     
                   
                 
                 
                   
                       
                   
                   ⁢ 
                   
                     
                       s 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         R 
                         
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         C 
                         
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                     
                     + 
                     
                       
                         sR 
                         3 
                       
                       ⁢ 
                       
                         C 
                         3 
                       
                     
                     + 
                     1 
                   
                 
               
             
           
           , 
         
       
     
   
   where the zero frequency is 
             ω     N   ⁢           ⁢   1       =     1       R   2     ⁢     C   3               
and the pole frequency is
 
   
     
       
         
           
             ω 
             
               p 
               ⁢ 
               
                   
               
               ⁢ 
               3 
             
           
           = 
           
             
               1 
               
                 
                   C 
                   3 
                 
                 ⁡ 
                 
                   ( 
                   
                     
                       R 
                       2 
                     
                     + 
                     
                       R 
                       3 
                     
                   
                   ) 
                 
               
             
             . 
           
         
       
     
   
   According to the gain A V3 , modifying the ratio of the compensating resistor R 2  to the compensating resistor R 3  can cause the zero frequency ω N1  to be several times higher than the pole frequency ω P3 . As the resistance value of the compensating resistor R 3  increases, the phase margin also increases, resulting in a more stable amplifier  700 . Comparing two gains A V2 , A V3 , the resistor r 0  in the CMFB amplifier  430  is not a real resistor, and its resistance value must be obtained by program simulation. By contrast, the compensating resistor R 3  in the CMFB amplifier  430  has a specified resistance value. Now assume that R 3 &lt;&lt;r 0 . the added compensating resistor R 3  is used in substitution for the resistor r 0  upon deriving the gain A V3 . 
     FIG. 8  is a block diagram of an amplifier according to a fifth embodiment of the present invention. Referring to  FIG. 8 , compared with the above-mentioned embodiments, a CMFB amplifier  830  in the fifth embodiment additionally includes a compensating unit Z 5 , coupled between two nodes X, Y and the ground voltage V ss , to compensate the amplifier  800 . The compensating unit Z 5  comprises a compensating capacitor C 3 , a compensating resistor R 2  and two identical compensating resistors R 3 . In this embodiment, the connectivity between the compensating capacitor C 3  and the compensating resistor R 2  is the same as that shown in  FIG. 6  while the connectivity between two identical compensating resistors R 3  is the same as that shown in  FIG. 7 . Since the gain A V3  derived from the amplifier  800  is the same as that derived from the amplifier  700 , the description is omitted herein. 
   The invention is not limited to the use of MOSFETs as described in the above-mentioned embodiments. In practical applications, a PMOS differential amplifier, including two PMOS transistor  432 ,  433  in the CMFB amplifier  430 ,  530 ,  630 ,  730 ,  830 , can be substituted by two PNP bipolar junction transistors (BJT). Likewise, two NMOS transistor  434 ,  435  can be substituted by two NPN BJTs. If all transistors in the CMFB amplifier are implemented with BJTs, all transistors in the FD Op-Amp  110  should be implemented with BJTs as well. Besides, since the CMFB circuit  440  is used to force the output common-mode voltage (the node A in each embodiment) to equal the reference voltage V ref  substantially, related methods to generate the reference voltage V ref , such as using a reference voltage V ref  generator or a voltage division, are also within the scope of the invention. 
   While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention should not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.