Abstract:
Methods for power factor correction (PFC) and for reducing conduction losses and switching losses in a power converter as well as the power converter and phase management circuitry for the power converter. The power converter includes a first PFC pre-regulator interleaved with at least one additional PFC pre-regulator, and a step down converter. The average input power is measured downstream of the front end at the step down converter and the average current sense signal is compared to a reference voltage. Each additional PFC pre-regulator is disable when output power generated by the front end is less than a first pre-designated rated power level and each additional PFC pre-regulator is enabled when the output power is greater than a second pre-designated rated power level.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This patent application is a continuation-in-part of U.S. patent application Ser. No. 12/133,080 of the same title filed on Jun. 4, 2008 and claims priority from U.S. Provisional Patent Application No. 60/941,844 also of the same title filed on Jun. 4, 2007. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0002]    Not Applicable 
       BACKGROUND OF THE INVENTION 
       [0003]    Interleaved power factor correction techniques are being used, primarily, to reduce conduction losses in connection with power factor correction (PFC) pre-regulators and to increase power densities by reducing total inductor magnetic volume. Interleaving PFC pre-regulators, in which two or more PFC pre-regulators are operated out-of-phase, is commonly employed in applications such as—for the purpose of illustration and not limitation—power supplies for personal computers, computer server power supplies, and in industrial AC to DC power conversion. 
         [0004]    Efficiency improvements using interleaved techniques, however, are only observed at higher power levels where conduction losses dominate over switching losses. However, this technique increases parasitic switch/field-effect transistor (FET) capacitance, which increases switching losses and reduces light load efficiency. 
         [0005]    For example, referring to  FIG. 1 , a typical AC to DC converter  10  with interleaved PFC pre-regulators includes a first stage (Stage  1 ) structured and arranged to provide interleaved PFC AC to DC conversion and a second stage (Stage  2 ) structured and arranged to provide DC to DC conversion. The first stage includes a first PFC pre-regulator  12  (Phase  1 ) and at least one additional PFC pre-regulator  14  (Phase  2 ) that are interleaved. The number of additional pre-regulator  14  is related to the number of desired phases. Hence, a two phase system (as shown in  FIG. 1 ) will have a first PFC pre-regulator  12  (Phase  1 ) interleaved with a second PFC pre-regulator  14  (Phase  2 ); while and a three phase system (not shown) will have a first PFC pre-regulator  12  interleaved with a second PFC pre-regulator  14  and with a third PFC pre-regulator (not shown). 
         [0006]    The interleaved PFC pre-regulators  12  and  14  are adapted to provide AC to DC power conversion. Each of the interleaved pre-regulators  12  and  14  is structured and arranged to include an inductive element L 1  and L 2  and a current blocking device, such as diode D 1  and D 2 . Those of ordinary skill in the art can appreciate that other means of blocking current besides diodes can be used. 
         [0007]    In pertinent part, each of the interleaved PFC pre-regulators  12  and  14  further includes a switching device  13  and  30 , which is shown as field effect transistors (FETs) Q 1  and Q 2 , and a gate driving device  11  and  28 . The gate driving devices  11  and  28  are adapted for opening, i.e., turning OFF, and closing, i.e., turning ON, the corresponding gates of the switching devices  13  and  30 . Those of ordinary skill in the art can appreciate that other switching device types can also be used. 
         [0008]    The front end (AC to DC conversion) stage (Stage  1 ) of the power converter  10  is generally followed by a second downstream (DC to DC conversion) stage (Stage  2 ). The second stage includes a peak current mode controlled step down converter  16 , such as a step down converter, a fly-back converter, and the like, that is adapted to step down the regulated boost voltage (V BOOST ) to a more usable voltage. The step down converter  16  includes a transformer  19 , a current sense resistor  17 , and a switching device  15 . For simplicity, efficient operation of the step down converter  16  can be controlled using peak current mode control techniques that are known to the art. 
         [0009]    A problem with this configuration, however, is that, at lighter power loads, conduction losses are negligible and switching losses dominate. Recalling that, heretofore, interleaving PFC pre-regulators have been used to reduce conduction losses, traditional interleaving of PFC pre-regulators  12  and  14  reduces efficiency at lighter power loads. 
         [0010]    To improve efficiency at these lighter power loads and to reduce switching losses, it would be desirable to provide means and methods for selectively turning OFF the second PFC pre-regulator  14  and any other PFC pre-regulators (not shown) during instances of lighter power loads and turning ON or leaving ON the additional PFC pre-regulator(s)  14  during instances of higher power loads. 
       SUMMARY OF THE INVENTION 
       [0011]    Methods for power factor correction (PFC) and for improving efficiency of a power converter at lighter power loads are disclosed. Also disclosed are power converters and phase management circuitry for power converters. The power converter includes a first PFC pre-regulator that is interleaved with at least one additional PFC pre-regulator, and a downstream step down converter. The phase management circuitry is structured and arranged to measure the average input power downstream of the front end, which is to say at the step down converter. The average current signal is processed and compared to a reference voltage. The phase management circuitry disables each of the at least one additional PFC pre-regulators when the output power generated by the step down converter is less than a first pre-designated rated power level, resulting in single mode or single phase operation, and enables each of the at least one additional interleaved PFC pre-regulator when the output power generated by the step down converter is greater than a second pre-designated rated power level, resulting in multiple mode or multiple phase operation. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0012]    The invention will be more fully understood by reference to the following Detailed Description of the invention in conjunction with the Drawings, of which: 
           [0013]      FIG. 1  shows a schematic of a two stage off line power converter having an interleaved power factor correction pre-regulator front end and a downstream step down converter in accordance with the prior art; 
           [0014]      FIG. 2  shows a schematic of phase management circuitry for power factor correction in accordance with the present invention; and 
           [0015]      FIG. 3  shows illustrative waveforms resulting from the phase management circuitry. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    U.S. Provisional Patent Application No. 60/941,844 filed on Jun. 4, 2007 and U.S. patent application Ser. No. 12/133,080 filed on Jun. 4, 2008 are incorporated herein in their entirety by reference. 
         [0017]    Phase management circuitry and a power converter using the same as well as methods for phase management and/or for power factor correction (PFC) are disclosed. Referring to  FIG. 1  and  FIG. 2 , a multiple phase, multiple stage power converter  10  and phase management circuitry  20  for the same are, respectively, shown. The multiple phase, multiple stage power converter  10  includes a first PFC pre-regulator  12  and an additional PFC pre-regulator  14  for each additional desired phase and a step down converter  16  at the Stage  2 . The first PFC pre-regulator  12  and an additional PFC pre-regulator  14  are interleaved in the front end of the power converter  10 . The step down converter is electrically coupled to both of the first PFC pre-regulator  12  and each additional PFC pre-regulator  14 . 
         [0018]    The phase management circuitry  20  is adapted to selectively turn ON and turn OFF each additional PFC pre-regulator  14  of the second phase (Phase  2 ) and any additional phase(s). More specifically, the phase management circuitry  20  is adapted to selectively turn ON and turn OFF each additional PFC pre-regulator  14  based on an average current sense signal (V RS ) developed across the current sense resistor  17  of the second stage (Stage  2 ). Indeed, advantageously, since the total output (V BOOST ) generated by the interleaved converters  12  and  14  is well regulated, the average current sense signal (V RS ) developed across the current sense resistor  17  provides a measure of the average output power of the power converter  10 . Although the total output is referred to as a V BOOST , connoting a boost converter, the invention is not to be construed as being limited to interleaved boost converters. Rather, the present invention could also be applied to any multiple node power stage converters, e.g., buck converters, fly-back converters, and the like. 
         [0019]    Because the total output (V BOOST ) is well regulated and because the average current sense signal (V RS ) provides a measure of the average output power of the power converter  10 , the average current sense signal (V RS ) of the power converter  10  can be used to control the phase management circuitry  20 . More specifically, the average current sense signal (V RS ) developed across the step down converter&#39;s  16  current sense resistor  17  can be used by the phase management circuitry  20  to turn ON each of the additional PFC pre-regulator(s)  14  during periods of relatively heavy power loading and to turn OFF the additional PFC pre-regulator(s)  14  during periods of relatively light power loading. A relatively light power load is a power load that is less than about 30 percent of the total output power. 
         [0020]    The phase management circuitry  20  shown in  FIG. 2  is for a two phase interleaved power converter  10 . However, the principles and techniques disclosed herein also are applicable for multiple phase interleaved PFC control. The phase management circuitry  20  includes a filtering unit  22 , an amplifying unit  24 , a comparing device  26 , and a gate driving integrated circuit  28 . All or some portions of the phase management circuitry  20  can be integrated into the gate driver  28  shown in  FIG. 1 , into the interleaved PFC controller  18  shown in  FIG. 1  or can be a stand alone device. 
         [0021]    Referring to  FIG. 2 , the filtering unit  22  is structured and arranged to produce a DC voltage (V 1 ) from the average current sense signal (V RS ) across the current sense resistor  17 . The filtering unit  22  can include a resistive element (R 1 ) and a capacitive element (C 1 ) that are structured and arranged to form a low pass filter, e.g., a low pass filter having a low frequency pole at approximately 273 Hz. 
         [0022]    Because the magnitude of the DC voltage (V 1 ) is generally less than 1V, an amplifying unit  24  is desired. The amplifying unit  24  is adapted to amplify the DC voltage (V 1 ) to a gained up average current sense signal (V 2 ) that can be more easily monitored and compared to a reference voltage (V 3 ). The amplifying unit  24  can be structured and arranged to include, for example, electrical components such as a non-inverting differentiating amplifier (A 1 ) and a feedback network that includes resistive elements (R 3  and R 2 ). 
         [0023]    The comparing device  26 , e.g., a hysteretic comparator, is adapted to generate logic high (HI) or low (LO) signals (V 4 ) for enabling and disabling the additional PFC pre-regulator  14  based on a comparison between the gained up average current sense signal (V 2 ) and a reference voltage (V 3 ). The comparing device  26  can include an inverting differential amplifier (A 2 ) and a feedback network that includes resistive elements (R 5  and R 6 ). A bias voltage (V BIAS ) and resistive elements (R 4  and R 5 ) can be used to control the magnitude of the reference voltage (V 3 ). 
         [0024]    The logic high (HI) or low (LO) signals (V 4 ) generated by the comparing device  26  are provided as input to the gate driving integrated circuit  28 . Optionally, resistive elements R 7  and R 8  can be included to form a voltage divider, to attenuate the logic high (HI) or low (LO) signals (V 4 ), to protect the gate driving integrated circuit  28 . 
         [0025]    The divided voltage (V 4 ) and a gate driving control signal (V GD2 ) generated by the interleaved PFC controller  18  are introduced as input to a logic device, e.g., an AND gate  29 , in a gate driving integrated circuit  28 . Accordingly, the gate driving integrated circuit  28  is structured and arranged to activate, i.e., turn ON, and deactivate, i.e., turn OFF, the switching device  30  of the second PFC pre-regulator  14  based on the logic high (HI) or low (LO) signals (V 4 ) of the comparing device  26 . 
         [0026]    When output (V 4 ) generated by the hysteretic comparator  26  is a logic high (HI), the front end of the power converter  10  operates in a single phase mode of operation, which means that the gate driving integrated circuit  28  will open, i.e., turn OFF, the gate of the switching device  30  so that only the first PFC pre-regulator  12  contributes to the boost voltage (V BOOST ) at the second stage (Stage  2 ). Alternatively, when output (V 4 ) generated by the hysteretic comparator  26  is a logic low (LO), the power converter  10  operates in a multi-phase mode of operation, i.e., the power converter  10  will operate in multiple phases. More particularly, the gate driving integrated circuit  28  will close, i.e., turn ON, the gate of the switching device  30  of the additional PFC pre-regulator  14  so that both the first PFC pre-regulator  12  and the additional PFC pre-regulator  14  contribute to the boost voltage (V BOOST ) at the second stage (Stage  2 ). 
       EXAMPLES 
       [0027]    A power converter  10  and phase management circuitry  20  therefor were evaluated in a 250 W application in which the boost voltage (V BOOST ) was 390V. The step down converter  16  was theoretically switching at 100 kHz. The current sense resistor  17  of the step down converter  16  was arbitrarily established at 0.33 ohms(Ω). The bias voltage (V BIAS ) was set to 12V. 
         [0028]    The phase management circuit  20  was programmed to turn OFF the second (Phase  2 ) PFC pre-regulator  14  when the power supply is operating at less than 29% of the power converter&#39;s rated power and to turn ON the second (Phase  2 ) PFC pre-regulator  14  when the step down converter  16  is operating at greater than 32% of the power supply&#39;s rated power. 
         [0029]    As shown in the calculations below, resistive element R 3  of the amplifying unit  24  is sized to amplify the average current sense signal and, moreover, is selected so that gained up average current sense signal (V 2 ) will operate between 0 and 10V. In order for the circuitry to turn ON and turn OFF the gate of the switching device  30  of the second PFC pre-regulator  14  (Phase  2 ), the efficiency (η) of the second power stage should be taken into consideration. The efficiency of the second stage is assumed to be 86%. Accordingly, as shown below, resistive element R 3  would need to be 39 kΩ based on load demands and the step down converter&#39;s  16  efficiency. 
         [0000]    
       
         
           
             
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         [0000]    As shown in the calculations below, resistive element R 5  of the comparing device  26  is sized to select the approximate power level at which the gate of the switching device  30  of the second (Phase  2 ) PFC pre-regulator  14  will be disabled, i.e., when V 2 =V 3 . Accordingly, in this example, resistive element R 5  was selected so that the switching device  30  of the second (Phase  2 ) PFC pre-regulator  14  would be turned OFF at a power level of approximately 30% of the full load power. A standard value resistor of 3.3 kΩ was chosen for R 5 . 
         [0000]    
       
         
           
             
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         [0030]    Resistor R 6  of the comparator device  26  sets up the converter hysteresis and can be adjusted for an individual application. 
         [0000]    
       
         
           
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         [0031]    As shown above, in this example, the converter had roughly 288 mV of hysteresis. Thus, the switching device  30  of the second PFC pre-regulator  14  is designed to turn ON when the power converter  10  is operating at 32% of its rated output power and to turn OFF when operating below 29% of the power converter&#39;s  10  rated output power. 
       Results of Computer Modeling 
       [0032]    A simplified SPICE model was simulated to evaluate the exemplary phase management circuitry  20 . The output power (POUT) was varied from 0 W to 250 W and back to 0 W over a 40 ms period. 
         [0033]    Referring to  FIG. 3 , the resulting waveforms for the output power (POUT), the DC voltage of the average current sense signal (V 1 ), the gained up average current sense signal (V 2 ), the reference voltage (V 3 ), the voltage at the gate of switching device  13  of the first PFC pre-regulator  12  (VGQ 1 ), the gate drive signal at the gate of switching device  30  of the second PFC pre-regulator  14  (VGD 2 ), and the voltage at the gate of switching device  30  of the second PFC pre-regulator  14  (VGQ 2 ) are shown. 
         [0034]    As is evident from the waveform of the voltage at the gate of switching device  30  of the second PFC pre-regulator  14  (VGQ 2 ), the second PFC pre-regulator  14  turns ON when the gained up average current sense signal (V 2 ) was greater than 32% of its maximum programmed value of 10V and turned OFF when the gained up averaged current sense signal (V 2 ) was approximately 29% of its maximum programmed value of 10V. Referring to the output power (POUT) waveform, due to time delays, e.g., delays caused by the low pass filter  22 , the second PFC pre-regulator  14  turned ON at 82 W and turned OFF at 70 W, which are approximately 33% and 28% of the supply&#39;s  10  rated output power. The time delay is shown in the offset of the peaks of the POUT waveform  30  and the V 2  waveform  35 . The maximum time delay caused by the filter  22  is less than 1.1 msec, which only had a minor effect on the simulated system. 
         [0035]    It will be apparent to those of ordinary skill in the art that modifications to and variations of the above-described system and method may be made without departing from the inventive concepts described herein. Accordingly, the invention should not be controlled except by the scope and spirit of the appended claims.