Abstract:
A power saving dimming apparatus for gas discharge lamps activates a system of gas discharge lamps through a phototransistor network sensitive to the infrared spectrum rather than the normal visible spectrum. The phototransistor network allows power to be supplied to the apparatus, resulting in the turning on of the lamps whenever daylight conditions exist which are insufficient to produce infrared light. When power is applied to the apparatus, either at initial turn on or after a momentary interruption, the apparatus applies full power to the primaries of the lamp ballasts for a preselected time period, thus ensuring all the lamps in the system light. After the preselected time period has passed, the apparatus automatically dims the lamps and maintains them in the dimmed state.

Description:
RELATED APPLICATIONS 
     This patent application is a continuation of U.S. patent application Ser. No. 08/215,205 filed Mar. 21, 1994, now U.S. Pat. No. 6,124,684 which is a file wrapper continuation of U.S. patent application Ser. No. 07/988,730 filed Dec. 10, 1992 now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 07/809,388 filed Dec. 17, 1991, now abandoned; the entire disclosures of all applications are expressly incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an apparatus for automatically controlling the starting and the subsequent dimming of a plurality of gas discharge lamps using standard commercially available lamp/ballast combinations. More specifically, but not by way of limitation, the apparatus allows gas discharge lamps (fluorescent, mercury vapor, metal halide, or high pressure sodium) to be started at full power and then automatically dimmed with no further operator intervention. Furthermore, after power is restored following a momentary power outage, the apparatus will restart the lamps at full power and then automatically readjust them to their prior dimmed setting. 
     2. Description of the Related Art 
     Various methods and apparatus presently exist to start gas discharge lamps. One such method starts fluorescent lamps utilizing starter switch “S” connected to both electrodes of a lamp (see FIG.  1 ). Initially, starter switch “S” is closed in order to conduct the applied electrical current to each electrode. Current is applied directly to each electrode so that the electrodes will be heated to thermionic emission temperature. Once the electrodes reach their thermionic emission temperature, the switch is opened, and the lamp starts. 
     However, because switches utilized in the above method and apparatus must be periodically replaced, starterless circuits have been devised. A starterless circuit such as that shown in FIG. 2, applies AC current to a lamp ballast which may be either a conventional transformer or an autotransformer. In either case, a portion of the transformer&#39;s output is tapped for each electrode to produce a current that heats the electrodes to thermionic emission temperature. Again, once the electrodes reach thermionic emission temperature, the lamps will start. 
     Gas discharge lamps such as high pressure sodium (HPS) lamps also require a starter switch to provide an initial high voltage pulse across both electrodes of the lamps. In the starter switch shown in FIG. 4, the output of the ballast is applied to an igniter which applies full power to both electrodes of the lamp, thereby heating the electrodes to thermionic emission temperature and starting the lamp. 
     For reasons of both energy efficiency and consumer preference, it is desirable to incorporate dimming devices into fluorescent and high intensity discharge (HID) lamp circuits. Such dimming devices, which are well known in the art, generally use solid-state components such as silicon controlled rectifiers (SCRs) or triacs to block portions of each half-cycle of the incoming AC voltage. By only allowing portions of each half-cycle to be conducted to the ballast, the amount of power delivered is thereby reduced. 
     However, a problem with such dimming devices, when applied in gas discharge lamps, is that full power is needed to start each lamp because of their high thermionic emission temperatures, and the particular starters required as discussed above. Additionally, after any power interruption, even a momentary one, all HID lamps (mercury vapor, metal halide, and high pressure sodium) require a cool down period during which full power is supplied before they will restrike. That period varies from about one minute for high pressure sodium lamps to between ten and fifteen minutes for metal halide lamps. Thus, the above dimming devices when activated will not be able to originally start or restart HID lamps. To start the HID lamps, a user must first manually apply full power to the ballast to start the lamps and then manually adjust the dimming device to the desired level. The dimming device, therefore, cannot be left at the desired setting because at every start-up or restart, a manual readjustment is required. 
     In an attempt to solve the above problem, an apparatus that utilizes special fluorescent ballasts (see FIG. 3) has been developed. The special fluorescent ballasts are provided with sections which continuously furnish power to the cathodes of the lamps, thereby maintaining the thermionic emission temperature of the cathodes. Unfortunately, these devices are costly and require extra wiring to control the dimming of the lamp. 
     Additionally, other devices currently exist for regulating gas discharge lamps. Such devices are typically installed in series between the ballast and the lamp. These devices range from the addition of one or more capacitors or reactive devices to the installation of more sophisticated solid-state circuitry such as that disclosed in U.S. Pat. No. 4,147,961, issued on Apr. 3, 1979 to Elms, and U.S. Pat. No. 4,147,962, issued on Apr. 3, 1979 to Engel. 
     Unfortunately, the devices disclosed in the above patents suffer several disadvantages. First, installation requires opening each fixture and installing additional components, thus significantly increasing initial costs. Second, extra control leads may be required in each fixture to allow a variance in the energy savings or lighting levels. That requirement makes a retrofit application very costly because it is often difficult to pull additional conductors through a conduit already filled to capacity. Furthermore, both the lamp fixtures and the conduits could be at a height requiring special equipment for installation. Third, the number and cost of individual components susceptible to failure create maintenance problems. Finally, and most importantly, full power will most likely not be available to the lamps at start up, resulting in a failure of the devices to start the lamps. 
     A dimming device which attempts to deal with the problem of starting of gas discharge lamps is disclosed in U.S. Pat. No. 4,287,455. The &#39;455 device employs power switch SCRs that are gated by a unijunction transistor via a control switch SCR and a pair of optocouplers. To produce appropriate phase control, the power switch SCRs are non-conducting until the unijunction transistor fires a pulse. The unijunction transistor, however, will not fire until a group of capacitors connected to its emitter are charged to a required value. The charging of the capacitors is accomplished by transforming and rectifying the incoming AC voltage using a transformer and rectifying bridge circuit, and then feeding the rectified voltage to the capacitors through a potentiometer. Thus, the phase portion of the incoming AC voltage which is conducted to the load depends upon the values of the capacitors and the setting of the potentiometer. To provide automatic starting when the device is set to dim the lamps, the capacitors coupled to the unijunction transistor also receive charging current through a charging diode that is further connected to the collector of a starting transistor. Additionally, a pair of capacitors is connected to the base of the starting transistor. When the pair of capacitors is charged, the transistor is turned on which reverse biases the charging diode, thus, no longer enabling the capacitors connected to the unijunction transistor to be charged via that pathway. Therefore, when power is initially applied to the device, the capacitors coupled to the unijunction transistor are charged via both the charging diode pathway as well as the potentiometer pathway. That supplemental charging causes the triggering of the unijunction transistor earlier in the AC cycle than in normal dimming operation. The &#39;455 device is supposed to deliver enough power to start the lamps before the starting transistor turns on. 
     However, full power is never directly applied to the load during the starting operation. Instead, the power switch SCRs are simply triggered earlier in the AC half-cycle than in the normal dimming operation. Thus, whether enough power is delivered to start the lamps depends upon the load. That is, with enough lamps connected to the device, it will be unable to supply sufficient power to light all the lamps. In that situation, only full power will start the lamps. 
     Furthermore, a portion of the charging current for the capacitors connected to the unijunction transistor always flows through the potentiometer. At a high dim setting, the triggering of the unijunction transistor occurs late in the AC cycle, even during the starting operation. Again, depending on the load, the resulting amount of power transmitted may not be enough to start the lamps. Thus, the &#39;455 device makes it impractical to furnish full power to HID lamps for the time necessary to allow the cool-down period before the lamps will restrike. Additionally, the capacitors connected to the starting transistor must discharge enough to turn off the starting transistor before the starting operation can take place. That is supposed to occur whenever power is removed from the device, however, a power outage of sufficiently short duration may extinguish the lamps while preventing the capacitors from sufficiently discharging. In that case, the lamps would have been restarted manually. 
     Another dimming device is disclosed in U.S. Pat. No. 5,043,635, issued on Aug. 27, 1991 to Talbott. It has similar shortcomings as the device described above. That is, if a power outage of only a few seconds occurs, the lamps under the control of &#39;635 device must be restarted manually. 
     Another dimming device is disclosed in U.S. Pat. No. 4,950,96 issued to Sievers, the inventor of the present invention. During sustained operation, the &#39;963 device provides lamp dimming by delivering power to the lamp only during portions of the AC cycle. Timing capacitors contained in a bridge circuit, when charged to the threshold voltage of a diac, discharge during a half-cycle into the gate of a triac causing the triac to conduct the incoming AC line to the lamp. Diodes, also contained in the bridge circuit, allow the timing capacitors to be reset during the opposite half-cycle. The &#39;963 device is further provided with potentiometers that are used to adjust the charging times of the charging capacitors and, therefore, the amount by which the lamp is dimmed. However, during system power up or a momentary power failure, the &#39;963 device provides full power to light or relight the lamp. Upon power up, a timer is initialized and begins operation. While the timer is operating, a signal turns on a transistor which turns on an opto-isolator causing the triac to deliver the full wave AC power to the lamp. After the timer times out, the transistor is turned off, thereby allowing the bridge circuit to automatically take over to deliver the reduced AC power. 
     The &#39;963 device is an improvement over conventional dimming devices because the amount the lamp is dimmed after the full power warm up period expires may be set once and will remain set without further adjustment. Unfortunately, because the &#39;963 device goes from a full power warm up period directly to its dimmed level in a one-step reduction of power, it does not operate properly when used to control HID lamps. When the &#39;963 device is used with high pressure sodium lamps, many lamps may extinguish after the one-step dimming process. 
     All of the above described dimming devices, by utilizing SCRs or triacs, introduce harmonics into the system and result in low power factor operation of the circuit. Both factors cause problems with the utility company serving the particular installation using a dimming device. In some instances, the use of the dimming devices affects the system to such an extent that additional charges may be accrued which offset any savings realized. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the present invention to provide a dimming apparatus, connectable to the primary supply of the ballast of an ordinary gas discharge lamp (fluorescent, mercury vapor, metal halide, or high pressure sodium), which provides a degree of dimming while allowing the lamp to be started at full power utilizing zero-cross electronics. The dimming function may take place step-wise encompassing one or more stages or through a continuous reduction of power as necessary for the proper operation of the lamps. 
     It is a further object of the present invention to provide a dimming apparatus that applies full power to the lamp or lamps upon initial starting or momentary power interruption with no dependence upon the dimming level or the applied load or the length of interruption. 
     It is another object of the present invention to provide a dimming apparatus that operates while at full power and in the dimmed mode at an industry accepted high power factor while introducing minimal harmonics to the system. 
     It is still a further object of the present invention to provide a solid-state light detection circuit utilizing a phototransistor that is only sensitive to the infrared light spectrum. 
     It is still another object of the present invention to provide a circuit for maintaining full power operation or returning to the lamps to full power from a dimmed state without turning the system off. 
     Still other features and advantages of the present invention will become evident to those skilled in the art in light of the following. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram depicting a starter circuit for a fluorescent lamp. 
     FIG. 2 is a schematic diagram depicting a starterless ballast circuit for a fluorescent lamp. 
     FIG. 3 is a schematic diagram depicting a dimmable ballast circuit for a fluorescent lamp. 
     FIG. 4 is a schematic diagram depicting a starter circuit for a high pressure sodium lamp. 
     FIGS.  5 A 1  and  5 A 2  are a schematic diagrams depicting the automatic light dimming system of the present invention in an embodiment which dims mercury vapor, metal halide, or high pressure sodium lamps utilizing a step-wise power reduction. 
     FIGS.  5 B 1  and  5 B 2  are a schematic diagrams depicting the automatic light dimming system of the present invention in an embodiment which dims mercury vapor, metal halide, or high pressure sodium lamps utilizing a continuous power reduction. 
     FIG. 6 is a block diagram depicting the component configuration of the automatic light dimming system according to both embodiments of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIGS.  5 A 1 ,  5 A 2 ,  5 B 1 ,  5 B 2 , and  6 , the automatic light dimming system of the present invention will be described. FIGS.  5 A 1  and  5 A 2  are a schematic diagrams showing the embodiment of the automatic light dimming system of the present invention which dims mercury vapor, metal halide, or high pressure sodium lamps utilizing a step-wise power reduction. FIGS.  5 B 1  and  5 B 2  are a schematic diagrams showing the embodiment of the automatic light dimming system of the present invention which dims mercury vapor, metal halide, or high pressure sodium lamps utilizing a continuous power reduction. In both embodiments of the present invention, power supply  10 , photocell control  20 , on/off control  30 , timer circuit  40 , and circuit program control  60  comprise the same circuits (see FIGS.  5 A and B). Furthermore, to ensure the automatic light dimming system of the present invention operates independent of the applied load, the AC line voltage is applied directly across variable level control  70  by the current carrying common line (see FIG.  6 ). That is, variable level control  70  is connected in parallel with autotransformer  80  through its connection to the AC input and the low-voltage tap of autotransformer  80 . Additionally, a plurality of lamps are connected across the current carrying common line (see FIG.  6 . Each lamp is provided with a ballast (not shown) to provide current regulation. 
     Power Supply 
     The incoming AC line voltage is applied to the primary of step-down transformer T 1  through a circuit network comprising fuse F 1  and transient voltage suppressor VS 1  (see FIGS.  5 A 1  and  5 B 1 ). The output from the secondary of T 1  is applied to two terminals of full-wave bridge rectifier BR 1 . The rectified output of rectifier BR 1  provides power to photocell control  20 , maximum level control  50 , on/off control  30 , timer circuit  40 , circuit program control  60 , and variable level control  70  through a voltage regulation network comprising capacitor C 1 , C 2 , C 3  zener diode Z 1 , diode D 1 , and fixed voltage regulator VR 1 . LED 1  receives power from bridge circuit BR 1  through resistor R 1  and functions to indicate power is available to each of the above control circuits. The negative terminal of BR 1  is connected to photocell control  20 , on/off control  30 , timer  40 , maximum level control  50 , and circuit program control  60  to form a floating ground which is electrically isolated from the rest of the circuit. 
     Photocell Control 
     Photocell control  20  operates to control the application of the output from rectifier BR 1  to on/off control  30 , timer circuit  40 , maximum level control  50 , circuit program control  60 , and variable level control  70 . Photocell control  20  comprises, phototransistor PQ 1 , transistor Q 1 , and NOR gate chip IC 1  (a National Semiconductor CD4001C NOR gate chip in both embodiments of the present invention). Phototransistor PQ 1  comprises an infrared light sensitive transistor positioned remote from both NOR gate chip IC 1  and transistor Q 1 . Phototransistor PQ 1  operates in response to available infrared rays to regulate the output from pin  10  of NOR gate chip IC 1  in order to control conduction from transistor Q 1 . The turning on and off of transistor Q 1  controls the delivery of power from rectifier BR 1  to on/off control  30 , timer circuit  40 , maximum level control  50 , circuit control  60 , and variable level control  70 . That is, during daylight hours when it is desirable to turn off the lamps, infrared rays which comprise a portion of the light spectrum strike phototransistor PQ 1  causing it to turn on. The turning on of phototransistor PQ 1  allows current flow through it from the junction of R 2  and R 3 , thus, switching the input of pins  1  and  2  of ICI from a logical “1” state to a logical “0” state. As a result, the output from pin  10  changes to a logical “0”, thereby turning off or keeping off Q 1 . With Q 1  turned off, no current flows from rectifier BR 1  to on/off control  30 , timer circuit  40 , maximum level control  50 , circuit program control  60 , and variable level control  70 , and, accordingly, the lamps are turned off and kept off. 
     Conversely, during the early morning, evening, and night hours, infrared rays cease to strike phototransistor PQ 1  because they are either no longer in the light spectrum or the light spectrum has been removed (i.e sundown). Without the infrared rays, phototransistor PQ 1  is turned off and current no longer flows through it. Instead, current flows through pins  1  and  2  of chip IC 1 , thereby, raising their inputs to a logical “1” state. A logical “1” input at pins  1  and  2  of NOR gate chip IC 1  results in the output of a logical “1” from pin  10  of NOR gate ICI. Current then flows through R 6  to the base of transistor Q 1 , thus turning it on. With transistor Q 1  turned on, current flows through it from rectifier BR 1  to on/off control  30 , timer circuit  40 , maximum level control  50 , circuit program control  60 , and variable level control  70 , and, accordingly, the lamps are turned on and kept on. 
     Switch S 1  is provided to allow manual operation of the system. Closing switch S 1 , thus coupling pins  13  and  14  together raises the input into pins  12  and  13  to a logical “1” state and causes the output of pin  10  to go high regardless of the status of phototransistor PQ 1 . Transistor Q 1  is then turned on and current flows from the positive terminal of BR 1  to on/off control  30 , the timer circuit  40 , maximum level control  50 , circuit program control  60 , and variable level control  70 . Circumventing phototransistor PQ 1  permits manual operation of the system for maintenance or testing purposes. 
     Additionally, resistor R 7  and capacitor C 7  form an RC integrator circuit which offers a delay in the activation and deactivation of transistor Q 1 , thereby preventing momentary changes in infrared ray availability from causing nuisance switching of the system. Furthermore, resistors R 4  and R 5 ; capacitors C 4 , C 5 , and C 6 ; and diode D 2  act as a filtering network to prevent hysteresis. 
     On/Off Control 
     On/off control  30  connects the incoming AC line voltage to the lamps in order to turn them on or off. On/off control  30  comprises SCR 1  (silicon controlled rectifier), SCR 2  (silicon controlled rectifier), triac TR 1 , and optically isolated triac driver OC 2  (a Motorola MOC3021 optically isolated triac driver in both embodiments of the present invention). On/off control  30  turns the system on and off in response to the output from transistor Q 1 . That is, the emitter of transistor Q 1  is connected through resistor R 15  to the light emitting diode side of optically isolated triac driver OC 2 . When transistor Q 1  is turned on as described above, current flows through the light emitting diode which drives a phototriac internal to optically isolated triac driver OC 2  to deliver voltage to the gate of triac TR 1  through resistor R 16 . As a result, TR 1  turns on and conducts current into the gates of SCR 1  and SCR 2  in order to turn them on. With SCR 1  and SCR 2  turned on, the current carrying common line is electrically connected to the lamps, and because at this point SCR 3  and SCR 4  (described herein) are also activated, power will be delivered to the lamps, thus lighting them. Conversely, when transistor Q 1  turns off as described above, SVR 1  and SCR 2  are turned off, thereby breaking the electrical connection between the current carrying common line and the lamps, removing power and causing them to extinguish. 
     Furthermore, resistor R 17  and capacitor C 11  are provided to form a snubber network which helps prevent false triggering of the SCRs caused by the lamps which are an inductive circuit. On/off control  30 , therefore, serves as a solid-state relay utilizing SCR 1  and SCR 2  as the main power-handling switching devices. 
     Timer Circuit 
     Timer circuit  40  produces a clock signal which is utilized to drive the decade counter/divider which comprises circuit program control  60  (described herein). Timer circuit  40  comprises timer IC 2  which in both embodiments of the present invention is a National Semiconductor CD4541B programmable timer. Timer IC 2  contains an internal oscillator circuit designed for use with an external capacitor and two resistors designated in FIGS. 5A and B as capacitor C 8  and resistors R 8  and R 9 , respectively. The RC network of capacitor C 8  and resistors RS and R 9  operates to determine the frequency of the internal oscillator which drives the internal counter of timer IC 2 . Power for timer IC 2  is supplied at pin  14  from the emitter of transistor Q 1  when it is turned on as described above. Furthermore, pins  12  and  13  are connected to the emitter of transistor Q 1  in order to select the counter state internal to timer IC 2  which divides the oscillator frequency by 2 16 , thereby producing a clock signal from pin  8  having the desired period. Pin  10  is connected to transistor Q 1  to control the multicycle mode operation of timer IC 2 . When the internal counter of timer IC 2  times out, the output of timer IC 2  at pin  8  changes state. The timed out output at pin  8  has been selected to be high (logical “1”). Thus, as the counter continually sets, times out, and resets, the output from pin  8  constantly changes state, thereby producing a clock signal which is fed into pin  14  of decade counter IC 3  in order to control circuit program control  60 . 
     Circuit Program Control 
     In both embodiments of the present invention, circuit program control  60  comprises decade counter IC 3 , which is a National Semiconductor CD4017B decade counter/divider having  10  sequentially activated outputs. These outputs which will be referred to as decade counter outputs “0-9” correspond to pins  3 ,  2 ,  4 ,  7 ,  10 ,  1 ,  5 ,  6 ,  9 , and  11  of decade counter IC 3 , respectively. Decade counter outputs “0-9” are normally in the logical “0” or low state and only advance to a logical “1” or high state when activated by decade counter IC 3 . During operation, decade counter IC 3  sequentially activates and then subsequently deactivates each one of decade counter outputs “0-9” in response to the positive/leading edges of the clock signal input into its pin  14  from pin  8  of timer IC 2 . Thus, each one of decade counter outputs “0-9” is sequentially activated to produce a high signal for one full clock cycle (i.e., clock period). 
     Specifically, for the beginning of a sequence, once decade counter IC 3  receives a positive edge of the clock signal input from timer IC 2 , it activates decade counter output “0”, thereby producing a logical “1” or high output on pin  3 . At the receipt of the next positive edge of the clock signal, decade counter output “0” is deactivated, thus placing a logical “0” back on pin  3 , and decade counter output “1” is activated to produce a logical “1” or high output on pin  2 . Accordingly, as each subsequent positive edge of the input clock signal is received, decade counter IC 3  deactivates the presently activated decade counter output and activates the next decade counter output in the sequence. In normal operation, decade counter IC 3  continually sequences from decade counter output “0” to decade counter output “9” and then back to decade counter output “0” so that another full sequence may begin. 
     However, in both embodiments of the present invention, only one progression from decade counter output “0” to decade counter output “9” is desired. Accordingly, decade counter output “9” is connected to the base of transistor Q 2  through resistor R 13 . Thus, when decade counter output “9”, the last output in the sequence, is activated, a logical “1” is applied to the base of Q 2 , thereby turning it on. With transistor Q 2  turned on, current from the emitter of Q 1  flows through Q 2  and diode D 5  to apply a logical “1” to pin  13 . A high input at pin  13  causes decade counter IC 3  to “freeze” in its present state. That is, decade counter IC 3  will not sequence through decade counter outputs “0-9” as long as pin  13  receives a high input. Decade counter IC 3 , therefore, will effectively be held with decade counter output “9” (pin  11 ) activated, and the rest of decade counter outputs “0-8” deactivated until decade counter IC 3  receives a reset signal. 
     Pin  15  of decade counter IC 3  is the decade counter reset. Upon the receipt of a reset signal at pin  15 , decade counter IC 3  deactivates decade counter output “9” or, alternatively, any one of decade counter outputs “0-8” which is presently activated. Decade counter IC 3  will then perform a completely new sequence, starting with decade counter output “0” and finishing with decade counter output “9” as described above. 
     However, if the reset signal is received from maximum level control  50  (described herein), decade counter IC 3  will not sequence but will, instead, “freeze”) with either decade counter output “0” or decade counter output “13” activated, thus permitting continuous delivery of full power to the lamps. Full power will be supplied to the lamps until maximum level control  50  is removed from the system. Once maximum level control  50  is removed from the system, decade counter IC 3  will perform another complete sequence as described above. 
     Pin  15  of decade counter IC 3  is further connected to the emitter of Q 1  through the RC differentiator network of capacitor CI 10  and resistor R 12  by way of diode D 4  to provide resetting of decade counter IC 3  upon either initial power application or the reapplication of power when a momentary power outage has occurred. Upon the application of power, transistor Q 1  will provide a logical “1” or a high signal to pin  15  because C 10  is initially discharged and cannot charge instantaneously. That is, the time period during which C 10  charges is sufficient to provide a reset signal to decade counter IC 3 . However, once C 10  fully charges, current no longer flows to pin  15 , thus removing the logical “1” and permitting decade counter IC 3  to begin operation under control of the clock signal from timer IC 2  as previously described. 
     The emitter of Q 1  is further connected to pin  16  of decade counter IC 3  in order to supply power to the chip. Pin  8  functions as the ground pin and, thus, is connected to the floating ground formed at the negative terminal of bridge rectifier BR 1 . 
     Autotransformer 
     Autotransformer  80  is connected in parallel with variable level control  70  and functions to supply voltage to the lamps at a reduced level once variable level control  70  (described herein) has been removed from the system. After variable level control  70  has been turned off, autotransformer  80  assumes all responsibility for the delivery of voltage to the lamps. Autotransformer  80  will maintain the lamps lit at their minimum lighting level until a system reset, a power outage followed by return of power, or the activation of maximum level control  50 . If any of the above occur, variable level control  70  will be activated to start the lamps at full power and then dim them as described herein. Autotransformer  80  offers high-power-factor operation while eliminating the possible problems encountered by the harmonic distortion introduced by the phase-control SCRs in the dimming system. 
     Variable Level Control (A) 
     As discussed previously, if a one-step reduction in voltage were employed such as in the case of immediately switching in autotransformer  80  after a full power start-up, loss of the arc in the HID lamps most likely will result. Accordingly, variable level control  70 A (See FIG.  5 A 2 ) is placed in parallel with the high input and low output terminals of autotransformer  80  to function as a solid-state means whereby the power delivered to the lamps may be reduced from full to partial over a period of time. 
     Referring specifically to FIG.  5 A 2 , the embodiment of variable level control  70  which utilizes step-wise control of the dimming from a full-power level to a dimmed level as established by autotransformer  80  will be described. Full power lighting of the lamps followed by a step-wise reduction is performed by variable level control  70 A (FIG.  5 A 2 ) under the control of circuit program control  60 . To allow for the initial full-power starting of the lamps, the base of transistor Q 10  is connected through resistor R 18  and diodes D 6  and D 7  to decade counter output “0” (pin  3 ) and decade counter output “1” (pin  2 ) of decade counter IC 3 . The collector of transistor Q 10  is connected to the cathode of the LED portion of optically isolated zero-crossing triac driver OCl 0 , which in this embodiment, is a Motorola MOC3043 triac driver. The anode of the LED portion of optically isolated zero-crossing triac driver OC 10  is connected to the cathode of the LED portion of optically isolated triac driver OC 11 , which in this embodiment is a Motorola MOC3012 optically isolated triac driver. In turn, the anode the LED portion of optically isolated triac driver OC 11  is connected to the emitter of transistor Q 1  through resistor R 26 . The emitter of transistor Q 10  is connected to LED  10  which, in turn, is connected to ground and functions to indicate the system is operating at full power. 
     Upon the application of power to the system through transistor Q 1  as previously described, decade counter IC 3  is triggered by timer IC 2  to activate decade counter output “0”. When decade counter output “0” is high, current flows to the base of transistor Q 10  turning it on. With transistor Q 10  turned on, a complete current path exists which permits current to flow from transistor Q 1  through the LED portion of optically isolated triac driver OC 11  to the LED portion of optically isolated triac driver OC 10 , thus lighting the LED portion of optically isolated triac driver OC 10 . The lighting of the LED portion of optically isolated triac driver OC 10 , in turn, causes the phototriac internal to optically isolated triac driver OC 10  to activate and, thus, deliver voltage to the gates of SCR 3  and SCR 4 , thereby turning them on. As previously described with reference to on/off control  30 , SCR 1  and SCR 2  are also turned on in response to system activation. Therefore, because SCR 1  and SCR 2  are always on and SCR 3  and SCR 4  have been turned on, power from the incoming AC line is delivered to the lamps. Furthermore, full power is applied to the lamps because with both decade counter outputs “0” and “1” connected to the base of transistor Q 10 , transistor Q 10  remains on and, thus, SCR 3  and SCR 4  remain on for a time period sufficient to deliver full-wave AC voltage. That is, even though decade counter IC 3  progresses from decade counter output “0” (pin  3 ) to decade counter output “1” (pin  2 ) as previously described, transistor Q 10  will remain on, thereby maintaining SCR 3  and SCR 4  for a time period sufficient to ensure that full power start-up of the lamps occurs. 
     Capacitor C 13  and resistor R 39  form a snubbing network to prevent false triggering of SCR 3  and SCR 4  caused by the inductive load (i.e. the lamps). Furthermore, triac driver OC 10  is employed in this embodiment because its zero-crossing feature only allows SCR 3  and SCR 4  to turn on at the zero voltage point of the incoming AC voltage, which facilitates the supply of full RMS voltage to the system while at the same time prevents damage to individual system components caused as a result of system start-up at the peak voltage point of the incoming AC voltage. 
     The progression of decade counter IC 3  from decade counter output “1” (pin  2 ) to decade counter output “2” (Pin  4 ) turns off transistor Q 10  which removes full power from the lamps and allows activation of the step-wise power reduction circuit of variable level control  70 A. Once transistor Q 10  is turned off, the incoming AC line no longer delivers full wave AC voltage to the lamps. Instead, the incoming AC line delivers the AC voltage to the lamps in partial waveforms under the control of bridge circuit BR 2  Bridge circuit BR 2  is connected between the terminals of the incoming AC line and functions in conjunction with triac TR 2 ; diac  1 ; and the network formed by transistors Q 3 -Q 9 , optically isolated triac drivers OC 3 -OC 9 , and resistors R 32 -R 38  to turn on SCR 3  and SCR 4  only during portions of each half-cycle of the incoming AC voltage waveform, thus facilitating the application of reduced power to the lamps. 
     Bridge circuit BR 2  comprises timing capacitor C 12  and the resistor network of potentiometer R 28  and resistors R 31  and R 29 , which connects timing capacitor C 12  to the AC input line. Bridge circuit BR 2  further comprises diodes D 30 -D 33  and resistors R 27  and R 30  which cause timing capacitor C 12  to be reset to the same voltage level after each positive or negative half-cycle of the incoming AC voltage, thus reducing the hysteresis effect. The delivery of AC voltage to bridge circuit BR 2  results in the charging of timing capacitor C 12 . Once timing capacitor C 12  charges to the breakover voltage of diac  1  during either the positive or negative half of the AC cycle, diac  1  turns on. The amount of time required to charge timing capacitor C 12  to the breakover voltage of diac  1  is regulated by the voltage-dropping network comprised of potentiometer R 28  and resistors R 31  and R 29  as well as parallel resistors R 33 -R 39  (described herein). With diac  1  turned on, timing capacitor C 12  discharges into the gate of triac TR 2  through optically isolated triac driver OC 11  and diac  1 , resulting in the turning on of triac TR 2 . The turning on of triac TR 2  allows it to apply the incoming AC voltage to the gates of SCR 3  and SCR 4 , thereby turning them on. Once SCR 3  and SCR 4  are turned on, the incoming AC voltage is applied directly across the lamps. However, because SCR 3  and SCR 4  turn off at zero current, i.e. when the incoming AC signal reaches zero as it changes polarity, only a portion of the incoming AC waveform is conducted to the lamps. That is, when SCR 3  and SCR 4  are activated, the portion of the incoming AC voltage signal, either the positive or negative half-cycle, remaining from the point of activation of the SCRs to the zero current or crossover point of the AC signal is conducted to the lamps. SCR 3  and SCR 4  are activated along the incoming half-cycle of the AC signal because a portion of that half-cycle signal is used to charge timing capacitor C 12  to the breakover voltage of diac  1 . Accordingly, variable level control  70 A provides reduced power and, thus dimming to the lamps. 
     The bases of transistors Q 9 -Q 3  are connected through resistors R 19 -R 25 , respectively, to decade counter outputs “2-8”, respectively. The emitters of transistors Q 9 -Q 3  are connected to LEDs  9 - 3 , respectively, which in turn are connected to ground and function to indicate the specific transistor activated. The collectors of transistors Q 9 -Q 3  are connected to the cathodes of the LED portions of optically isolated triac drivers OC 9 -OC 3 , respectively. In this embodiment, optically isolated triac drivers OC 9 -OC 3  are Motorola MOC3012 optically isolated triac drivers. Similarly to optically isolated triac driver OC 10 , the anodes of the LED portions of optically isolated triac drivers OC 9 -OC 3  are connected to the cathode of the LED portion of optically isolated triac driver OC 11 . Additionally, the phototriacs internal to optically isolated triac drivers OC 9 -OC 3  are connected along different points of the resistor network comprising resistors R 38 -R 32  in order to provide a variable resistance to bridge circuit BR 2 . 
     In operation, variable level control  70 A functions to reduce the power delivered from the incoming AC line in a step-wise fashion so that the light output of the lamps will gradually be reduced to an operator-selected dimmed level. To accomplish the delivery of reduced power, variable level control  70 A changes the charging time of timing capacitor C 12  in multiple steps specifically, as described above, the charging of timing capacitor C 12  to the breakover voltage of diac  1  controls when SCR 3  and SCR 4  are activated. Thus, by step-wise increasing the time required for timing capacitor C 12  to reach the breakover voltage of diac  1 , variable level control  70 A activates SCR 3  and SCR 4  at discrete points which occur consistently later along the half-cycle of the incoming AC signal. Accordingly, as SCR 3  and SCR 4  are consistently fired later and later along the half-cycle of the incoming AC signal, the power delivered to the lamps is reduced to the operator-selected value. 
     The level to which the lamps are dimmed is determined by the resistance value to which potentiometer R 28  is adjusted. That is, as the resistance of potentiometer R 28  is increased, the charging time of timing capacitor C 12  increases. That results in the firing of SCR 3  and SCR 4  at a point later along the half-cycle of the incoming AC signal. Thus, when potentiometer R 28  is adjusted to it maximum resistance level, the lamps are provided with the least power and, therefore, are the most dimmed. Furthermore, the altering of the resistance encountered by bridge circuit BR 2  as it charges timing capacitor C 12  provides the step-wise reduction of the power delivered to the lamps. 
     Specifically, when decade counter output “1” (pin  2 ) is deactivated and decade counter output “2” (pin  4 ) is activated, full power start-up of the lamps is finished, and the step-wise reduction of power begins. With decade counter output “2” (pin  4 ) advanced to a high state by decade counter IC 3 , current flows to the base of transistor Q 9 , turning it on. The activation of transistor Q 9  allows current to flow through the LED portion of optically isolated triac driver OC 9  from transistor Q 1 . The lighting of the LED portion of optically isolated triac driver OC 9  activates the phototriac internal to OC 9  and switches resistor R 38  into bridge circuit BR 2 . The added resistance of resistor R 38  in bridge circuit BR 2  increases the time required for timing capacitor C 12  to charge to the breakover voltage of diac  1 . Consequently, SCR 3  and SCR 4  are fired after the beginning of the incoming AC signal half-cycle, resulting in less than full power being applied to the lamps. However, the resistance value of resistor R 38  is such that the charging time of timing capacitor C 12  is not greatly affected, and therefore, a large portion of the AC signal is conducted to the lamps. 
     When decade counter output “2” (pin  4 ) is deactivated and decade counter output “3” (pin  7 ) is activated, transistor Q 9  turns off, and current flows to the base of transistor Q 8 , turning it on. The activation of transistor Q 8  allows current to flow through the LED portion of optically isolated triac driver OC 8  from transistor Q 1 . The lighting of the LED portion of optically isolated triac driver OC 8  activates the phototriac internal to OC 8  and switches both resistors R 38  and R 37  into bridge circuit BR 2 . The added resistance of resistors R 38  and R 37  in bridge circuit BR 2  again increases the time required for timing capacitor to charge to the breakover voltage of diac  1 . Consequently, SCR 3  and SCR 4  are fired later than before in the incoming AC signal half-cycle, resulting in even less power being applied to the lamps. 
     As decade counter IC 3  progresses to decade counter output “4”, resistor R 36  is added to bridge circuit BR 2 , and the time required to charge timing capacitor C 12  to the breakover voltage of diac  1  again increases. SCR 3  and SCR 4  are turned on later in the AC half-cycle and even less power is delivered to the lamps. 
     As decade counter IC 3  progresses through decade counter outputs 5-8, resistors R 35 -R 32  are sequentially added to bridge circuit BR 2  similar to the addition of resistors R 38 -R 36  as described above. With each added resistance, the charging time of capacitor C 12  is increased, resulting in less and less power being delivered to the lamps as SCR 3  and SCR 4  are switched on later and later in the AC half-cycle. When decade counter IC 3  finally reaches decade counter output “8”, the lamps are dimmed to the level set by potentiometer R 28 . Accordingly, as decade counter IC 3  progresses through its decade counter output sequence, power to the lamps is reduced in a step-wise fashion as a result of the switching in of resistors R 38 -R 32 . 
     However, when decade counter IC 3  advances to decade counter output “9” (pin  11 ), the sequencing of decade counter IC 3  ceases and decade counter outputs “0-8” are locked in their low state as previously described in the description of decade counter IC 3 . 
     With decade counter outputs “0-8” turned off, transistors Q 10 -Q 3  are turned off, effectively removing variable level control  70 A from the system. With variable level control  70 A removed from the system, autotransformer  80  takes over to deliver the reduced power to the lamps as described above. Furthermore, removal of variable level control  70 A is desirable because all of its heat-generating devices are off and will only be activated during actual operation of variable level control  70 A. 
     When decade counter output “9” (pin  11 ) of decade counter IC 3  is activated, variable level control  70 A is removed from the system because the base of transistor Q 2  is connected to decade counter output “9” (pin  11 ) of decade counter IC 3  through resistor R 13 . With decade counter output “9” (pin  11 ) activated, current flows through resistor R 13  to the base of transistor Q 2 , thereby turning it on. With transistor Q 2  on, current flows from the emitter of Q 1  through diode D 5  to pin  13  of decade counter IC 3  causing decade counter IC 3  to “lock” with decade counter output “9” (pin  11 ) activated, current from transistor Q 1  also flows through resistor R 14  to LED 2 , which is connected to ground and functions to indicate the system is operating in a reduced power mode. 
     Maximum Level Control Means (A) 
     FIG.  5 A 2  shows maximum level control  50 A used with the step-wise power reduction circuit of variable level control  70 A. Maximum level control  50 A comprises optically isolated transistor OC 1 , current limiting resistor R 10 , switch S 2 , and diode D 3 . In this embodiment, OC 1  is a Motorola 4N35 optically isolated transistor. The anode of the internal LED of optically isolated transistor OC 1  is connected to the emitter of Transistor Q 1 . When switch S 2  is closed, current flows through the internal LED of optically isolated transistor OC 1 , thus activating the phototransistor internal to optically isolated transistor OC 1 . With the phototransistor internal to optically isolated transistor OC 1  activated, current flows from the emitter of optically isolated transistor OC 1  through D 3  to pin  15  of decade counter IC 3 . A high signal applied to pin  15  causes decade counter IC 3  to reset, thereby activating decade counter output “0” (pin  3 ). Furthermore, as long as switch S 2  remains closed, decade counter IC 3  will remain locked with decade counter output “0” activated. As previously described, a high signal from decade counter output “0” will result in full power being applied to the lamps. Therefore, the lamps will remain fully lit until switch S 2  is opened. 
     In this embodiment, switch S 2  may comprise a manually operated switch, an electrically operated switch connected to a time clock, a computer operated relay, or a photocell. For example, an electrically operated switch such as a solenoid activated switch could be connected to a time clock which activates and deactivates the solenoid at certain times to regulate full power operation of the lamps. That is, at a certain time in the mid-morning, the clock could turn off the solenoid which opens the switch and allows the lamps to be dimmed using variable level control  70 A as described above. However, at a certain time in the evening, the clock could activate the solenoid which closes the switch and brings the lamps up to full power as described above. 
     Variable Level Control Level Means (B) 
     Again as discussed previously, if a one-step reduction in voltage were employed such as in the case of immediately switching in autotransformer  80  after a full power start-up, loss of the arc in the HID lamps most likely will result. Accordingly, variable level control  70 B is placed in parallel with the high input and low output terminals of autotransformer  80  to function as a solid-state means whereby the power delivered to the lamps may be reduced from full to partial over a period of time. 
     Referring specifically to FIG.  5 B 2 , the embodiment of variable level control  70  which utilizes continuous control of the dimming from a full-power level to a dimmed level as established by autotransformer  80  will be described. To allow for the initial full-power starting of the lamps, the base of transistor Q 8  is connected through resistor R 200  to diodes D 70 -D 110  which, in turn, are connected to decade counter outputs “0-4” of decade counter IC 3 , respectively. The emitter of transistor Q 80  is connected to ground through LED  40 , which functions to indicate the system is operating at full power. The collector of transistor Q 80  is connected to the cathode of the LED portion of optically isolated zero-crossing triac driver OC 80 , which in this embodiment is a Motorola MOC3043 optically isolated zero-crossing triac driver. The anode of the LED portion of optically isolated zero-crossing triac driver OC 80  is connected to the cathode of the LED portion of optically isolated transistor OC 5  which in this embodiment is a Motorola 4N35 optically isolated transistor. The anode of the LED portion of optically isolated transistor OC 50  is connected through resistor R 22  to the emitter of transistor Q 1 . 
     With either an initial application of power or a system reset as described above, transistor Q 1  turns on to provide system power. As a result, decade counter IC 3  under the control of timer IC 2  begins its sequence at decade counter output “0”. A high output from decade counter output “0” delivers current to the base of transistor Q 80 , thus turning it on. The activation of transistor Q 8  allows current to flow from the emitter of transistor Q 1  to the LED portion of optically isolated transistor OC 50  through resistor R 220 , and then to the LED portion of optically isolated zero-crossing triac driver OC 8 . The lighting of the LED portion of optically isolated zero-crossing triac driver OC 80 , in turn, activates the phototriac internal to optically isolated zero-crossing triac driver OC 80  to apply voltage across the gates of SCR 30  and SCR 40 , thus turning them on. As previously described with reference to on/off control  30 , SCR 1  and SCR 2  are also turned on in response to system activation. Therefore, because SVR 1  and SCR 2  are always on and SCR 30  and SCR 40  have been turned on, power from the incoming AC line is delivered to the lamps. Furthermore, full power is applied to the lamps because with decade counter outputs “0-4” connected to the base of transistor Q 80 , transistor Q 80  remains on for four decade counter sequences, resulting in SCR 30  and SCR 40  remaining on for a time period sufficient to deliver full wave AC voltage. That is, even though decade counter IC 3  progresses from decade counter output “0” to decade counter output “4” as previously described, transistor Q 80  will remain on, thereby maintaining SCR 30  and SCR 40  for a time period sufficient to ensure that full power start-up of the lamps occurs. 
     Capacitor C 150  and Resistor R 380  form a snubbing network that prevents false triggering of SCR 30  and SCR 40  caused by the lamps which are an inductive load. Furthermore, optically isolated zero-crossing triac driver OC 80  is employed in this embodiment because its zero-crossing feature only allows SCR 30  and SCR 40  to turn on at the zero voltage point of the incoming AC voltage signal, which facilitates the supply of full RMS voltage to the system while at the same time prevents damage to individual system components caused as a result of system start-up at the peak voltage point of the incoming AC voltage signal. 
     In addition to its connection to the base of transistor Q 8 , decade counter output “4” (pin  10 ) is connected to the base of transistor Q 4  through diode D 170  and resistor R 240 . Thus, when decade counter output “4” is activated by decade counter IC 3 , transistor Q 80  not only remains on as described above but transistor Q 40  is also turned on. With transistor Q 40  turned on, current from transistor Q 1  flows through transistor Q 40  to the LED portion of optically isolated transistor OC 30  and then to the LED portion of optically isolated transistor OC 60  in order to activate both optically isolated transistors. In this embodiment, optically isolated transistor OC 30  is a Motorola H11D1 optically isolated transistor, while optically isolated transistor OC 60  is a Motorola 4N35 optically isolated transistor. The activation of optically isolated transistor OC 30  permits bridge rectifier BR 20  to supply current to the base of transistor Q 50  through the phototransistor internal to optically isolated transistor OC 30 . Bridge rectifier BR 2 , further, supplies current through transistor Q 50  to the phase control circuit (described herein) of variable level control  70 B. 
     Supply of current to the phase control circuit during the activation of decade counter output “4” permits charging of capacitor C 120  to its full charge because optically isolated transistor OC 50  is already activated, as previously described. Bridge rectifier BR 20 , therefore, charges C 120  through transistor Q 50 , resistor R 280 , diode D 180 , the phototransistor internal to optically isolated transistor OC 50 , and resistor R 300  to a voltage level as determined by zener diode Z 20 . Accordingly, upon the deactivation of decade counter output “4” the phase-control circuit is ready to begin operation at its maximum setting because capacitor C 120  has been fully charged to the voltage level determined by zener diode Z 20 . 
     The progression of decade counter IC 3  from decade counter output “4” (pin  10 ) to decade counter output “5” (pin  1 ) removes current from the base of transistor Q 80 . With transistor Q 8  turned off, full power is no longer supplied to the lamps because the incoming AC line no longer delivers full wave AC voltage to the lamps. Instead, the incoming AC line delivers the AC voltage to the lamps, in partial waveforms under the control of the phase control circuit of variable level control  70 B. 
     Specifically, the deactivation of decade counter output “4” (pin  10 ) and the activation of decade counter output “5” (pin  1 ) removes current from optically isolated transistor OC 50  and stops the charging of capacitor C 120 . Decade counter output “5” (pin  1 ) is also connected to the base of transistor Q 40  through diodes D 120  and D 160  and resistor R 240  and, therefore, maintains transistor Q 40  turned on to provide current to the phase control circuit from bridge rectifier BR 20  as previously described. Furthermore, decade counter output “5” (pin  1 ) is connected to the base of transistor Q 60  to turn it on. With transistor Q 60  turned on, current flows from transistor Q 1  to the LED portion of optically isolated transistor OC 40 , thus activating it. That current flow also lights LED  30  to indicate the phase control circuit of variable level control  70 B is operating. 
     Phase control of triac TR 20  is obtained by charging capacitor C 130  through resistor R 250  and potentiometer R 330  from the voltage level established by zener diode Z 30 . When capacitor C 130  has charged to the firing voltage (i.e. the peak voltage) of unijunction transistor UJT 1 , unijunction transistor UJT 1  turns on, resulting in the discharge of C 130  through the emitter of unijunction transistor UJT 1 . C 130  discharges through unijunction transistor UJT 1  until the voltage it develops drops below the cut-off (i.e. the valley voltage) of unijunction transistor UJT 1 . The discharge of capacitor C 130  through unijunction transistor UJT 1  creates a pulse signal which activates the LED portion of optically isolated triac driver OC 70  via optically isolated transistor OC 60  and resistor R 350 . Current flows through the phototransistor internal to optically isolated transistor OC 60  because it was previously activated as described above. In this embodiment, optically isolated triac driver OC 70  is a Motorola MOC3021 optically isolated triac driver. With optically isolated triac driver OC 70  pulsed on, resistors R 350  and R 390  and capacitor C 140  provide the filtered AC gate voltage which is necessary to activate triac TR 20 . The activation of triac TR 20  causes it to apply the incoming AC voltage across the gates of SCR 30  and SCR 40 , thus turning them on. As a result of SCR 30  and SCR 40  being turned on, the incoming AC signal is conducted to the lamps. 
     However, because SCR 30  and SCR 40  turn off at zero current, i.e. when the incoming AC signal reaches zero as it changes polarity, only a portion of the incoming AC waveform is conducted to the lamps to keep them lit. That is, when SCR 30  and SCR 40  are activated, the portion of the incoming AC signal, either the positive or negative half-cycle, remaining from the point of activation of the SCRs to the zero current or crossover point of the AC signal is conducted to the lamps. After SCR 30  and SCR 40  turn off at the zero current point, the above cycle repeats. Capacitor C 130  continues to charge until it fires unijunction transistor UJT 1 , which activates SCR 30  and SCR 40  at a point along the next half-cycle of the incoming AC signal in order to conduct a partial waveform as described above. Accordingly, with the phase control circuit activated, only partial power is applied to the lamps through SCR 30  and SCR 40 . 
     To provide control of the amount of power delivered to the lamps, or in other words, to control the amount by which the lamps are dimmed, the phase control circuit is supplied with potentiometer R 330 . The value to which potentiometer R 330  is adjusted determines the time required for capacitor C 130  to charge to the firing voltage of unijunction transistor UJT 1 , which in turn, governs the point along the incoming AC signal where SCR 30  and SCR 40  will be activated. For example, the greater the resistance of potentiometer R 330 , the longer the time required for capacitor C 13  to charge to the firing voltage of unijunction transistor UJT 1 . Accordingly, the point at which SCR 30  and SCR 40  turn on and, thus, the amount of power delivered to the lamps is controlled by adjusting the value of the resistance of potentiometer R 330 . 
     However, at initial start-up or restart after a momentary power loss, it is necessary to start at full power. Furthermore, it is necessary to gradually reduce the power to the desired dimming level to which potentiometer R 330  is adjusted because if potentiometer R 330  was adjusted to provide a large amount of dimming, and such a dimming was executed in a single drastic power reduction, the lamps would most likely extinguish. To solve the above problem, capacitor C 120  is charged during the full power starting of the lamps as described above to provide a continuous and smooth power reduction to the dimming level set by the adjustment of potentiometer R 330 . Specifically, when decade counter IC 3  advances from decade counter output “4” (pin  10 ) to decade counter output “5” (pin  1 ), capacitor C 120  is fully charged and, therefore, provides biasing voltage and current to transistor Q 70  in order to turn it on. Furthermore, because optically isolated transistor OC 40  has been turned on as previously described, capacitor C 120  also discharges through resistors R 280  and R 290  and the phototransistor internal to optically isolated transistor OC 40  to ground. That discharge rate is determined by the values of R 280  and R 290 . As C 120  discharges, transistor Q 70  provides voltage and current to capacitor C 130  in addition to the voltage and current provided by bridge rectifier BR 20  via transistor Q 50 , resistor R 250 , and potentiometer R 330 . As a result of the increased voltage and current, capacitor C 130  charges to the firing voltage of unijunction transistor UJT 1  more quickly than if voltage and current were only supplied via the circuit path containing potentiometer R 330 . When unijunction transistor UJT 1  fires, both capacitor C 120 , via transistor Q 70 , and capacitor C 130  discharge into the emitter of unijunction transistor UJT 1  to create the pulse current which causes the activation of SCR 3  and SCR 4 . Initially, as C 120  is more fully charged, it provides more voltage and current to capacitor C 130 , and consequently, unijunction transistor UJT 1  fires quickly. As a result, a large portion of the half-cycle of the incoming AC signal is delivered to the lamps. However, as C 120  discharges, the voltage and current it supplies gradually decreases which causes capacitor C 130  to charge more and more slowly, thus causing SCR 30  and SCR 40  to gradually be turned on later and later along each half-cycle of the incoming AC signal. Finally, when capacitor C 120  is discharged, transistor Q 70  turns off and capacitor C 130  only charges via the circuit path including potentiometer R 330  as previously described. By using capacitor C 120  to alter the firing of unijunction transistor UJT 1 , SCR 30  and SCR 40  may be initially fired early in each half-cycle of the incoming AC signal and then fired at points later in each half-cycle, until finally capacitor C 120  is discharged, and capacitor C 130  controls the firing of unijunction transistor UJT 1  at the minimum level set by the value of potentiometer R 330 . Therefore, the phase control circuit including capacitor C 130  allows a continuous, gradual and smooth phase and power reduction of the lamps. 
     When decade counter output “5” (pin  1 ) of decade counter IC 3  is activated the periodic activation of SCR 30  and SCR 40  as described above begins. Furthermore, because decade counter outputs “6-8” are also connected to transistor Q 40  through diode D 160  and transistor Q 60  through resistor R 210  via their respective diodes D 130 -D 150 , the aforementioned phase control circuit operates during each on period of decade counter outputs “6-8”. That is, during the activation decade counter outputs “5-8”, the power applied to the lamps is continuously, gradually, and smoothly diminished until it reaches the minimum level established by potentiometer R 330  as previously described. Therefore, by the end of the activation period of decade counter output “8”, the power output to the lamps is at level low enough to allow autotransformer  80  to provide the power to the lamps without the lamps being extinguished. 
     When decade counter IC 3  activates decade counter output “9” (pin  11 ), the sequencing of decade counter IC 3  ceases and decade counter outputs “0-8” are locked in their low state as previously described in the description of decade counter IC 3 . With decade counter outputs “0-8” turned off, transistors Q 80 , Q 40 , and Q 60  are turned off, effectively removing the solid-state phase control from the system. Removal of the phase control circuit is desirable because all of its heat-generating devices are off and will only be activated during actual operation of the phase control circuit. 
     Furthermore, when decade counter output “9” of IC 3  is activated, current flows through resistor R 130  to the base of transistor Q 20 , thereby turning it on. With transistor Q 20  on, current flows from the emitter of Q 1  through diode D 50  to pin  13  of decade counter IC 3  causing decade counter IC 3  to “lock” with decade counter output “9” (pin  11 ) activated. Current from transistor Q 1  also flows through resistor R 140  to LED 20 , which is connected to ground and functions to indicate the system is operating in a reduced power mode. 
     Maximum Level Control Means (B) 
     FIG. 5B shows maximum level control  50 B utilized with the continuous power reduction circuit of variable level control  70 B. Maximum level control  50 B in this embodiment comprises optically isolated transistor OC 10 , resistor R 100 , switch S 20 , diode D 30 , and a differentiator comprising capacitor C 90  and resistor R 110 . In this embodiment, optically isolated transistor OC 100  is a Motorola 4N35 optically isolated transistor. The emitter of transistor Q 1  is connected to the LED internal to optically isolated transistor OC 100 , which in turn, is connected to ground through resistor R 100  and switch S 20 . The emitter of transistor Q 1  is further connected to the collector of the phototransistor internal to optically isolated transistor OC 100 . The emitter of the phototransistor internal to optically isolated transistor OC 100  is connected to the collector of transistor Q 3  and also to ground through capacitor C 9  and resistor R 11 . Additionally, the emitter of transistor Q 30  is connected to pin  13  of decade counter IC 3 . Resistor R 180  connects transistor Q 30  to ground so that decade counter IC 3  will not be damaged during the resetting of the system. 
     When S 20  is closed, current flows through the internal LED of optically isolated transistor OC 100 , thus activating it. With optically isolated transistor OC 1  turned on, the phototransistor internal to it delivers current from the emitter of transistor Q 1  to capacitor C 90  and resistor R 110 , resulting in a pulse being applied to pin  15  of decade counter IC 3  through diode D 30 . That pulse applied at pin  15  resets decade counter IC 3 . The reset of decade counter IC 3  begins its operation at the first decade counter output which is decade counter output “0”. The activation of decade counter output “0” applies full power to the lamps as previously described. However, if switch S 20  remains closed when decade counter output “3” (pin  7 ) is activated by decade counter IC 3 , the phase control circuit will not be activated and the lamps will remain at full power. With switch S 20  closed and decade counter output “3” activated, current flows through resistor R 19  to the base of transistor Q 30  in order to turn it on. With transistor Q 30  turned on, current from the emitter of the phototransistor internal to optically isolated transistor OC 100  flows through transistor Q 30  and diode D 60  to pin  13  of decade counter IC 3 . A high input received at pin  13  causes decade counter IC 3  to “lock” in the particular stage of the sequence at which it is presently operating. In this instance, decade counter IC 3  is frozen with decade counter output  11311  activated. A high signal from decade counter output  11311  turns on transistor Q 80  which functions to deliver full power to the lamps as previously described. As long as switch S 20  remains closed, transistor Q 80  will remain on and full power will be delivered to the lamps. However, after switch S 20  is opened, optically isolated transistor OC 1  turns off, thereby stopping the current flow through transistor Q 30  to pin  13  of decade counter IC 3 . Once pin  13  no longer receives a high input, decade counter IC 3  becomes “unlocked”, and the decade counter output sequence continues with the activation of decade counter output “4” . After decade counter output “5” is activated, the phase-reduction circuit will dim the lamps as described above. 
     In this embodiment, switch S 20  may comprise a manually operated switch, an electrically operated switch connected to a time clock, a computer operated relay, or a photocell. For example, an electrically operated switch such as a solenoid activated switch could be connected to a time clock which activates and deactivates the solenoid at certain times to regulate full power operation of the lamps. That is, at a certain time in the mid-morning, the clock could turn off the solenoid which opens the switch and allows the lamps to be dimmed using variable level control  70 B as described above. However, at a certain time in the evening, the clock could activate the solenoid which closes the switch and brings the lamps up to full power as described above. 
     Although the invention has been described in conjunction with the foregoing specific embodiments, many alternatives, variations,, and modifications should be apparent to those of ordinary skill in the art. Those alternatives, variations, and modifications are intended to fall within the spirit and scope of the appended. claims.