Abstract:
A video monitoring system using daisy chain is disclosed. A video monitoring system uses daisy chain, which can display more than four divided screens on one display screen with a simple configuration of the video monitoring system by bypassing video signals captured by a plurality of video cameras through many stages.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present application is a continuation-in-part of the earlier filed non-provisional application, having U.S. application Ser. No. 10/332,207, filed on Jan. 3, 2003, which is incorporated herein in its entirety. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to a video monitoring system, and more particularly to a video monitoring system using daisy chain.  
       DESCRIPTION OF THE RELATED ART  
       [0003]     A conventional video monitoring system is installed in a general house, department store, bank, factory, exhibition hall, etc. to monitor visitors and prevent a burglary. The conventional video monitoring system comprises a plurality of video cameras for capturing video signals corresponding to objects of monitored areas, a signal processor for processing video signals captured by video cameras, and a video display device for displaying video images corresponding to the processed video signals on one display screen having divided display screens.  
         [0004]     The conventional video monitoring system reduces video data corresponding to video signals captured by four video cameras according to a scaling reduction ratio and displays video images corresponding to the reduced video data on the one display screen containing four divided screens. Here, the one display screen containing the four divided screens is referred to as a quad screen. According to a quad screen combination, video images corresponding to video signals inputted from video cameras can be displayed on the four divided display screens, eight divided display screens or sixteen divided display screens divided within one full display screen.  
         [0005]     For example, where video signals can be displayed on the sixteen divided screens on the basis of the quad screen combination, four quad units QUAD 1 -QUAD 4  are configured as shown in  FIG. 1 . In this case, frame memories fm 1 -fm 4  are provided to configure the respective quad screens. A frame memory fm 5  and a quad unit QUAD 5  are provided to combine quad video data from the four quad units QUAD 1 -QUAD 4  to process the combined quad video data so that sixteen video images corresponding to the processed video data are displayed on the sixteen divided screens.  
         [0006]     Therefore, as the number of quad units is increased, the number of frame memories is increased in order to configure the sixteen divided screens. A last stage of the conventional video monitoring system includes another quad unit QUADS for processing the quad video data from the respective quad units in addition to the four quad units QUAD 1 -QUAD 4  and another frame memory fm 5  for configuring the sixteen divided screens in addition to the frame memories fm 1 -fm 4 . There is a problem in that a configuration of the conventional video monitoring system is complicated to configure with more than the four divided screens, and costs for system construction are increased.  
       SUMMARY OF THE INVENTION  
       [0007]     Therefore, the present invention has been made in view of the above problems, and the present invention provides a video monitoring system using daisy chain, which can display more than four divided screens on one display screen with a simple configuration of the video monitoring system by bypassing video signals captured by a plurality of video cameras through many stages.  
         [0008]     The present invention also provides a video monitoring system using daisy chain, which can display a plurality of channel video images on divided screens within one display screen by arbitrarily extending the number of divided screens with a single memory.  
         [0009]     In accordance with an aspect of the present invention, a video monitoring system for configuring and displaying one or more divided screens corresponding to one or more video signals captured by one or more cameras, comprises:  
         [0010]     A/D (Analog/Digital) converters for converting channel video signals outputted from the video cameras into digital video data; 
        one or more slave video signal processors coupled by daisy chain for reducing the digital video data of each channel outputted from the A/D converters through a video source channel, collecting the digital video data of the video source channel outputted through a first bypass channel placed at a front stage of a slave video signal processor and the digital video data of the video source channel outputted through a second bypass channel placed at the front stage of the slave video signal processor, and outputting the collected video data to the second bypass channel;     a master video signal processor for reducing another digital video data outputted from the A/D converters through the video source channel, recording another digital video data and the digital video data outputted from the first bypass channel and the second bypass channel coupled to a last slave video signal processor among the slave video signal processors, in a frame memory, and configuring and outputting video data corresponding to multiple channel divided screens; and     a D/A (Digital/Analog) converter for converting the video data corresponding to the multiple channel divided screens into analog video signals and outputting the analog video signals to a video display device.        
 
         [0014]     The slave video signal processor reduces the digital video data of the video source channel corresponding to the video signals captured by each video camera and then outputs the reduced digital video data. The slave video signal processor bypasses the digital video data from another slave video signal processor placed at its front stage, thereby outputting the bypassed digital video data to another slave video signal processor placed at its rear stage. The master video signal processor may record the digital video data of the video source channel corresponding to the video signals captured by respective video cameras and the digital video data bypassed from the slave video signal processor placed at its front stage in the frame memory, thereby configuring multiple channel divided screens and then outputting the configured multiple channel divided screens. Therefore, the video monitoring system may display the multiple channel divided screens with a simple configuration of the system. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0016]      FIG. 1  is a view showing a configuration of a conventional video monitoring system including a plurality of quad units;  
         [0017]      FIG. 2  is a view showing a configuration of a video monitoring system using daisy chain in accordance with a first embodiment of the present invention;  
         [0018]      FIG. 3  is a block diagram illustrating a video signal processor for implementing the video monitoring system shown in  FIG. 2 ;  
         [0019]      FIG. 4  is a view explaining a signal transfer procedure when the video signal processor shown in  FIG. 3  is employed as a slave video signal processor;  
         [0020]      FIG. 5  is a view explaining a signal transfer procedure when the video signal processor shown in  FIG. 3  is employed as a master video signal processor;  
         [0021]      FIG. 6  is a view showing a configuration of a video monitoring system using daisy chain in accordance with a second embodiment of the present invention; and  
         [0022]      FIG. 7  is a view showing a configuration of a video monitoring system using daisy chain in accordance with a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]     Now, exemplary embodiments of the present invention will be described in detail with reference to the annexed drawings. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.  
         [0024]      FIG. 2  is a view showing a configuration of a video monitoring system using daisy chain in accordance with a first embodiment of the present invention. In more detail,  FIG. 2  is a view showing a configuration of a video monitoring system for displaying sixteen divided display screens on a video display device.  
         [0025]     As shown in  FIG. 2 , the video monitoring system for displaying the sixteen divided display screens comprises three slave video signal processors  18 ,  20  and  22  and one master video signal processor  24 . The slave video signal processors  18 ,  20  and  22  and master video signal processor  24  will be described below and can be composed of the same components as one another.  
         [0026]     Referring to  FIG. 2 , A/D (Analog/Digital) converters  10 ,  12 ,  14  and  16  are coupled to video source channels of the slave video signal processors  18 ,  20  and  22  and master video signal processor  24 . The A/D (Analog/Digital) converters  10 ,  12 ,  14  and  16  convert channel video signals outputted from video cameras vc 1 -vc 16  into digital video data.  
         [0027]     The slave video signal processors  18 ,  20  and  22  reduce the digital video data of each channel outputted from the A/D converters  10 ,  12  and  14  through the video source channels and then output the reduced digital video data to a first bypass channel V 1 , V 3  and V 5 . The slave video signal processors  18 ,  20  and  22  collect the digital video data of the video source channels outputted through the first bypass channel N.C., V 1  and V 3  and the digital video data outputted through a second bypass channel N.C., V 2  and V 4  and then output the collected digital video data to the second bypass channel V 2 , V 4  and V 6 , respectively. The slave video signal processors  18 ,  20  and  22  are coupled to one another by the daisy chain.  
         [0028]     The master video signal processor  24  reduces the digital video data outputted from the A/D converters  16  through a video source channel. The master video signal processor  24  records the digital video data outputted from the first bypass channel V 5  and the second bypass channel V 6  coupled to the third slave video signal processor  22 , placed at a front stage of the master video signal processor  24  to be described below, in a frame memory  26 . The frame memory  26  stores the digital video data for configuring multiple divided display screens. For reference, a memory controller equipped with the master video signal processor  24  controls access to the frame memory  26 .  
         [0029]     A D/A (Digital/Analog) converter  28  converts the video data corresponding to the multiple divided display screens outputted from the master video signal processor  24  into analog video signals. For reference, “N.C.” of  FIG. 1  is an abbreviation of “No Connection”. Configurations of the slave video signal processors  18 ,  20  and  22  and master video signal processor  24  in the video monitoring system will be described below in detail.  
         [0030]      FIG. 3  is a block diagram illustrating a master or slave video signal processor for implementing the video monitoring system shown in  FIG. 2 . In accordance with an embodiment of the present invention, the slave video signal processors  18 ,  20  and  22  and master video signal processor  24  comprise video input controllers  30 , horizontal/vertical scalers  32 , input buffers  34 , a memory controller  36 , an output buffer  38 , a video output controller  40  and a bypass buffer  42 , respectively, as shown in  FIG. 2 .  
         [0031]     The video input controllers  30  extend digital video data outputted from the A/D converters  10  coupled to the video source channel, and separate and control horizontal and vertical synchronous signals.  
         [0032]     After receiving digital video data outputted from each of the A/D converters  10  coupled to the video source channel, the video input controllers  30  separate the digital video data into luminance component data and chrominance component data to expand a data bus. That is, the luminance component and the chrominance component of the video data, when inputted, are contained in one bus in a time-sharing manner, but are separated from each other and individually outputted in 8-bit bus by the video input controllers  30 . In addition, the video input controllers  30  extract and output horizontal and vertical synchronous signals which are then used for image size reduction or divided image synthesis. In the video signal processors, the number of video input controllers  30  is the same as the number of A/D converters  10 .  
         [0033]     The horizontal/vertical scalers  32  downscale a screen on which to display the digital video data outputted from the video input controllers  30 , in a horizontal direction and/or a vertical direction so that the digital video data outputted from the video input controllers  30  can be stored to be displayed on divided display screens. It is clear that the horizontal/vertical scalers  32  reduce the digital video data by performing interpolation between adjacent digital video data on the basis of reduction ratios. The reduction ratios in the horizontal and vertical directions can be varied on the basis of the number of divided display screens to be displayed on a video display device. For instance, a final display of a 4-division screen can be achieved through reduction by half in both a horizontal and a vertical direction and, in the case of a 16-division screen, quarter reduction is performed in both a horizontal and a vertical direction. In the embodiment of the present invention, it is assumed that each slave video signal processor configures the four divided display screens. In the video signal processors, the number of horizontal/vertical scalers  32  is the same as the number of video cameras.  
         [0034]     The input buffer  34  temporarily stores the video data outputted from the horizontal/vertical scalers  32  and then outputs the video data through two channels. One of the two channels is a first bypass channel (Bypass video Out) and the other channel is needed in the memory controller  36  reading the video data.  
         [0035]     The memory controller  36  reads the screen-downscaled digital video data from the input buffer  34  in burst units_and records the read video data at frame memory addresses designated channel by channel. The digital image data collected from the bypass buffer  42  is recorded at the designated frame memory addresses to configure multi-channel divided screen data. The recorded video data is read out so that it can be displayed in real time. In accordance with the present invention, the slave video signal processors  18 ,  20  and  22  are not directly connected to the memory controller  36  and only the master video signal processor  24  is directly connected to the memory controller  36 . In the slave video signal processor  18 ,  20  and  22 , accordingly, a video signal is directly outputted, in its current state, from the input buffer  34  to the first bypass video channel (Bypass video out) without using the memory controller  36 .  
         [0036]     The output buffer  38  temporarily stores the video data corresponding to one display screen. The video output controller  40  combines supplementary information (including time information, channel information, etc.) with the video data of the one display screen outputted from the output buffer  38  to output the supplementary information and the video data. The video data outputted from the video output controller  40  is converted into analog video signals by the D/A converter  28  and then the analog video signals are outputted to the video display device.  
         [0037]     At last, the bypass buffer  42  receives the video data from a first bypass channel (Bypass Video In) and a second bypass channel (Bypass Video In) coupled to a slave video signal processor placed at its front stage and then, outputs the stored video data through one channel in a time division multiplexing manner. That is, without undergoing a process such as the synthesis of divided images, the data is directly outputted. At this time, the data is outputted into the memory controller  36  when it is used in the master video signal processor or into the first bypass channel when it is used in the slave video signal processor.  
         [0038]     As described above, the slave video signal processors  18 ,  20  and  22  and the master video signal processor  24  in accordance with the embodiment of the present invention can be composed of the same components as one another. However, where the video signal processor is employed as the slave video signal processor, it can employ only the video data outputted through the first bypass channel coupled to an output terminal of the input buffer  34 .  
         [0039]      FIG. 4  is a view explaining a signal transfer procedure when the video signal processor shown in  FIG. 3  is employed as a slave video signal processor.  FIG. 5  is a view explaining a signal transfer procedure when the video signal processor shown in  FIG. 3  is employed as a master video signal processor.  
         [0040]     In other words, when the video signal processor shown in  FIG. 3  is employed as the slave video signal processor, the digital video data inputted through the video source channels is transferred to another slave video signal processor or the master video signal processor placed at the rear stage of the slave video signal processor through a video input controller  30 , a horizontal/vertical scaler  32 , an input buffer  34  and a first bypass channel (Bypass Video Out). Then, the slave video signal processor collects the digital video data inputted through the first bypass channel and a second bypass channel coupled to another slave video signal processor placed at its front stage and then outputs it through the second bypass channel. That is, because the slave video signal processor collects the video data inputted through the video source channel placed at its front stage, it can be configured as shown in  FIG. 4  or  FIG. 3 . Herein, to collect digital video data means that the digital video data is outputted in its current state after order adjustment alone, without actually undergoing a processing procedure. For instance, inputted data is outputted in a multiplexing manner.  
         [0041]     The video signal processor shown in  FIG. 5  represents the case in which the video signal processor shown in  FIG. 3  is operated as the master video signal processor. Video signals outputted from video cameras vc 13 -vc 16  are inputted into a video source channel through A/D converters  10 . Then, the digital video data inputted through the video source channels is stored in a frame memory  26  through video input controllers  30 , horizontal/vertical scalers  32  and input buffers  34 . The digital video data outputted through bypass channels V 5  and V 6 , coupled to another slave video signal processor placed at the front stage of the video signal processor shown in  FIG. 5 , is stored in the frame memory  26  through a bypass buffer  42  by a frame controller  36 . Accordingly, the video data stored in the frame memory  26  is controlled by the memory controller  36  and externally outputted through an output buffer  38  and video output controller  40 .  
         [0042]     The operation of the video monitoring system shown in  FIG. 2  where the slave video signal processors  18 ,  20  and  22  and the master video signal processor  24  are coupled by the daisy chain will be described below.  
         [0043]     First, video signals captured by four video cameras vc 1 -vc 4  are converted into digital video data by A/D converters  10 . Then, the digital video data is inputted into a video source channel coupled to the slave video signal processor  18 . Then, the slave video signal processor  18  reduces and outputs the video data appropriate to configure the four divided display screens. The reduced video data is outputted to a first bypass channel V 1  through input buffers  34  and then transferred to the slave video signal processor  20 . Because no video signal processor is connected to the front stage of the slave video signal processor  18 , there is no data to be transferred to the slave video signal processor  20  through a second bypass channel V 2 .  
         [0044]     On the other hand, video signals captured by four video cameras vc 5 -vc 8  are converted into digital video data by A/D converters  12 . Then, the digital video data is inputted into a video source channel coupled to the slave video signal processor  20 . Then, the slave video signal processor  20  reduces and outputs the video data appropriate to configure the four divided display screens. The reduced video data is outputted to the first bypass channel V 3  (vc 5 -vc 8 ) through input buffers  34  and then transferred to the slave video signal processor  22 . After processing the video signals captured by the video cameras vc 1 -vc 4 , the slave video signal processor  20  receives the digital video data through the first bypass channel V 1  coupled to the slave video signal processor  18  placed at its front stage. The digital video data is transferred to the second bypass channel V 4  (vc 1 -vc 4 ) through the bypass buffer  42 .  
         [0045]     After processing video signals captured by the video cameras vc 5 -vc 8 , the slave video signal processor  22  receives the reduced video data through the first bypass channel V 3 . Further, after processing video signals captured by the video cameras vc 1 -vc 4 , the slave video signal processor  22  receives the reduced video data through the second bypass channel V 4 . The video data outputted from two bypass channels V 3  and V 4  is collected in the bypass buffer  42  and then transferred to the master video signal processor  24  through the second bypass channel V 6  (vc 1 -vc 8 ). The digital video data inputted into the video source channel coupled to the slave video signal processor  22  is transferred to the master video signal processor  24  through the first bypass channel V 5  (vc 9 -vc 12 ) according to the above described operation.  
         [0046]     Accordingly, the bypass buffer  42  within the master video signal processor  24  collects the digital video data (vc 1 -vc 12 ) inputted through the first bypass channel V 5  and the second bypass channel V 6  and then outputs it to the memory controller  36 . The digital video data of the video source channel corresponding to the video signals captured by the video cameras vc 13 -vc 16  is reduced and then transferred to the memory controller  36 . The memory controller  36  within the master video signal processor  24  records and stores the digital video data of sixteen channels at designation addresses of the frame memory  26 , thereby configuring the sixteen divided display screens. The video data corresponding to the sixteen divided display screens stored in the frame memory  26  is accessed by the memory controller  36  and then transferred to an external D/A converter  28  through the video output controller  40 , thereby displaying the sixteen divided display screens on the video display device.  
         [0047]     Because the present invention does not have to configure frame memories within every video signal processor for configuring sixteen divided display screens and also does not have to configure an additional video signal processor for configuring the sixteen divided display screens at a last stage of a video monitoring system, the system can be simply configured.  
         [0048]     Further, because video signal processors having the same components as one another are alternatively employed as a slave video signal processor or master video signal processor, the construction of the system can be facilitated and the system can be simply extended or reduced.  
         [0049]     Although the video monitoring system configuring and displaying the sixteen divided display screens has been described above, it can display twelve divided display screens by coupling two slave video signal processors  18  and  20  and one master video signal processor  24  through the daisy chain as shown in  FIG. 6 . Further, the video monitoring system can display eight divided display screens by coupling one slave video signal processor  18  and one master video signal processor  24  through daisy chain as shown in  FIG. 7 .  
         [0050]     Therefore, the present invention is not limited to the above-described embodiments, but the present invention is defined by the claims which follow, along with their full scope of equivalents.  
         [0051]     Because the present invention does not have to configure frame memories within every video signal processor for configuring sixteen divided display screens and also does not have to configure an additional video signal processor for configuring the sixteen divided display screens at a last stage of a system, the system can be simply configured.  
         [0052]     Further, because video signal processors having the same components as each other are alternatively employed as a slave video signal processor or master video signal processor, the construction of the system can be facilitated and the system can be simply extended or reduced.