Abstract:
An electrical test circuit includes a bridge configuration having two paths between two nodes, a buffer, and a capacitor. An output of the buffer is coupled to one of the paths, the buffer is adapted to either provide a defined potential or a high impedance, the capacitor is connected to the output of the buffer, and a signal of a device under test is adapted to be coupled to another one of the paths. One of the nodes of the bridge configuration can be supplied with a first current, and the other one of the nodes of the bridge configuration can be supplied with a second current.

Description:
[0001]     This application is a divisional of co-pending U.S. application Ser. No. 10/864,123, filed 9 Jun. 2004, which is incorporated by reference herein in its entirety. 
     
    
     BACKGROUND  
       [0002]     So-called active-load circuits are often used within test systems for terminating signals of a device under test with a programmable current. Such test circuits are present e.g. on a plug-in card of the test systems. Such plug-in cards, however, are usually only applicable for digital signals of the device under test, and if an analog signal of the device under test is to be tested, different plug-in cards have to be applied.  
       SUMMARY  
       [0003]     It is an object of the invention to provide an improved active-load circuit. The object is solved by the independent claims. Preferred embodiments are shown by the dependent claims.  
         [0004]     The circuit according to the present invention may be used for testing digital signals as well as analog signals. In connection with analog signals, the buffer is switched into its high impedance state and the value of the analog signal can be sampled with the help of the capacitor. The sampled voltage may then be converted into a digital value. As well, a time duration or a corresponding digital count value may be generated corresponding to the sampled voltage.  
         [0005]     According to embodiments of the invention, an electrical test circuit with a bridge configuration comprises four diodes, wherein a common connection point of the anode and the cathode of two of the four diodes is connected with an output of a buffer, wherein a common connection point of the cathode and the anode of the two other diodes is coupled with a signal of a device under test, wherein a common connection point of the anodes of two of the four diodes may be supplied with a first current, wherein a common connection point of the cathodes of the other two diodes may be supplied with a second current. A capacitor is connected to the output of the buffer, and the buffer is provided to be switched into a high impedance state.  
         [0006]     The term buffer&#39; as used herein shall represent any kind of circuit allowing to either provide a defined potential or a high impedance to a node. Such buffer can be accomplished e.g. by standard buffer circuits as well known in the art, or by a switchable voltage source (e.g. a voltage source in series with a switch coupled to the node, so that with closed switch the voltage source is coupled to the node and with open switch the voltage source is decoupled from the node).  
         [0007]     The bridge configuration can be any kind of circuit having a first and a second paths between a first and a second node. The first path having a third node and the second path having a forth node. In case a potential at the third node exceeds a potential at the forth node, a first current provided at the first node will be drawn at the forth node. In case the potential at the third node is lower than the potential at the forth node, a second current provided at the second node will be drawn at the forth node.  
         [0008]     The invention can be partly or entirely embodied or supported by one or more suitable software programs, which can be stored on or otherwise provided by any kind of data carrier, and which might be executed in or by any suitable data processing unit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     Other objects and many of the attendant advantages of the present invention will be readily appreciated and become better understood by reference to the following detailed description when considering in connection with the accompanied drawing(s). Features that are substantially or functionally equal or similar will be referred to with the same reference sign(s).  
         [0010]      FIG. 1  shows a schematic circuit diagram of a first embodiment of an electric test circuit according to the invention;  
         [0011]      FIG. 2  shows a schematic time diagram of signals of the test circuit of  FIG. 1 ;  
         [0012]      FIG. 3  shows a schematic circuit diagram of a second embodiment of an electric test circuit according to the invention; and  
         [0013]      FIG. 4  shows a schematic time diagram of signals of the test circuit of  FIG. 3 . 
     
    
     DETAILED DESCRIPTION  
       [0014]     In  FIG. 1 , a test circuit  10  is shown that may be part of a test system for testing digital and/or analog signals. The test circuit  10  may be implemented within a so-called pin-electronics chip, which may be mounted on a plug-in card of the test system. The test circuit  10  is a so-called active-load circuit and is provided for terminating one of the signals of the device under test with a programmable current.  
         [0015]     The test circuit  10  comprises a bridge configuration  11  built up by four diodes D 1 , D 2 , D 3 , and D 4 . An output of a buffer B 1  is connected with the common connection point of the cathode of the diode D 1  and the anode of the diode D 3 . At this common connection point, a voltage Vx is present. The common connection point of the cathode of the diode D 2  and the anode of the diode D 4  is connected via a resistor RD with a pin DUT that carries the signal of the device under test (DUT). At this common connection point, a voltage VD is present.  
         [0016]     The common connection point of the anodes of the diodes D 1  and D 2  is connected with a switch SW 1 , which is connected with a current source providing a current  1   i.  In a first position of the switch SWi, the current  1   i  flows into the bridge configuration  11 , whereas in a second position of the switch SWi current flow into the bridge configuration  11  is disabled e.g. in that the current source is grounded.  
         [0017]     The common connection point of the cathodes of the diodes D 3  and D 4  is connected with a switch  5 W 2  which is connected with a current source providing a current  12 . In a first position of the switch  5 W 2 , the current  12  flows out of the bridge configuration  11 , whereas in a second position of the switch  5 W 2  current flow into the bridge configuration  11  is disabled e.g. in that the current source is grounded.  
         [0018]     At least in connection with the described testing of analog signals, the values of the currents  1   i  and  12  are preferably provided to be at least substantially identical. The switches SWi and  5 W 2  are switched by a signal LDEN preferably provided by the test system. Furthermore, the test system supplies a fixed voltage VCOM to an input of the buffer Bi. This voltage VCOM defines a level for differentiating between a binary “1 “and a binary “0” of the signal of the device under test, which is present at the pin DUT in case of testing digital signals.  
         [0019]     If the signal LDEN is low or off, the switches SWi and SW 2  are grounded and do not connect the current sources with the bridge configuration  11 . The test circuit  10 , therefore, does not represent a load for the signal of the device under test.  
         [0020]     If the signal LDEN is high or on, the switches SW 1  and  5 W 2  connect the current sources for the currents  11  and  12  with the bridge configuration  11 . Therefore, the device under test being connected at the pin DUT is loaded by the current  12  if the voltage at the pin DUT is sufficiently higher than the voltage VCOM, and the device under test is loaded by the current —|| if the voltage at the pin DUT is sufficiently lower than the voltage VCOM. The device under test being connected at pin DUT is therefore terminated with the currents  12  and −||, depending on the voltage of the device under test.  
         [0021]     The test circuit  10  furthermore comprises a capacitor C 1  that is connected from the output of the buffer Bi to preferably ground. It is also possible that the capacitor C 1  is built up by parasitic capacitances being present at the output of the buffer  81 . The output of the buffer  81  is also connected to the input of a buffer B 2 , which provides a signal SAM at its output. The buffer B 1  is provided with a control signal HZ that enables the buffer  81  to be switched into a high impedance state.  
         [0022]     In  FIG. 2 , the voltages Vx and VD as well as the signal LDEN are shown over the time. For the following description, it is assumed that the buffer B 1  is switched into its hig impedance state.  
         [0023]     If the signal LDEN is high or on, i.e. if the switches SW 1  and  5 W 2  connect the current sources to the bridge configuration  11 , then the voltage Vx follows the voltage VD. This is shown in section A of  FIG. 2 . When the signal LDEN changes to low or off, then the last value of the voltage Vx before the change of the state of the signal LDEN will remain as the voltage Vx. This voltage Vx will remain substantially fixed due to the capacitor C 1 . This is shown in section B of  FIG. 2 .  
         [0024]     The voltage Vx is preferably amplified by the buffer B 2  and provided as the signal SAM. This signal SAM, therefore, is an analog value representing the voltage VD at the point in time at which the change of the state of the signal LDEN (from high to low, or on to off) took place. By switching the signal LDEN from on to off, the voltage VD may therefore be sampled. The resulting signal SAM may be provided to an analog/digital-converter in order to convert it into a digital value.  
         [0025]     If the signal LDEN is high or on again, the voltage Vx follows the voltage VD again. By switching the signal LDEN off again, the sampling of the voltage VD results again in a new signal SAM, as illustrated above. This is shown in sections C and D of  FIG. 2 .  
         [0026]     As a result, the test circuit  10  is able to create a sampled analog signal SAM of the signal of the device under test being connected at the pin DUT by switching the buffer  81  in a high impedance state and by switching the signal LDEN off.  
         [0027]     The sampled analog signal SAM thus represents the voltage VD at the point in time of switching the signal LDEN off.  
         [0028]     In  FIG. 3 , a test circuit  20  is shown which is similar to the test circuit  10  of  FIG. 1 . Therefore, identical features are characterized by identical reference numerals. As well, reference is made to the description above.  
         [0029]     Compared to the test circuit  10  of  FIG. 1 , the test circuit  20  of  FIG. 3  does not comprise the buffer  82  and the signal SAM. Instead, the test circuit  20  of  FIG. 3  comprises a switch  5 W 3  that is connected with the output of the buffer  81  and with a current source for providing a current IR. In a first position of the switch  5 W 3 , the current source is preferably grounded. In a second position of the switch  5 W 3 , the current source for providing the current IR is connected with the output of the buffer B 1 . The switch SW 3  is switched by the signal LDEN.  
         [0030]     Furthermore, the output of the buffer  81  is connected with an (preferably inverted as shown in  FIG. 3 ) input of a comparator CP. This (inverted) input is connected via a diode Dx with a (preferably non-inverted as shown in  FIG. 3 ) input of the comparator CP. This (non-inverted) input is supplied with a threshold voltage VTH. The output of the comparator CP provides a digital signal EOR.  
         [0031]     If the current IR is sufficiently smaller than the current  1   i,  then the switch  5 W 3  may be unnecessary, and the current  11  may be connected directly to the output of the buffer  81 .  
         [0032]     In  FIG. 4 , the voltages Vx and VD as well as the signals LDEN and EOR are shown over the time. For the following description, it is assumed that the buffer  81  is switched into its high impedance state.  
         [0033]     If the signal LDEN is high or on, i.e. if the switches SWi and  5 W 2  connect the current sources to the bridge configuration  11  and if the switch  5 W 3  grounds the current source for the current IR, then the voltage Vx follows the voltage VD. This is shown in section A of  FIG. 4 .  
         [0034]     When the signal LDEN changes to low or off, then the signal Vx starts to decrease/increase from its last value Vi before the change of the state of the signal LDEN took place. The point in time of this change of the signal LDEN is characterized by reference sign Tia. The decrease/increase of the voltage Vx is linear like a ramp and is defined by the current IR and the capacitor C 1 . This is shown in section B of  FIG. 4 .  
         [0035]     When the voltage Vx becomes equal to the threshold voltage VTH, the signal EOR changes from a binary “0” to a binary “1”. This point in time is characterized by reference sign T 1   b.  The time duration between the points in time Tia and Tib is characterized by reference sign TD 1 .  
         [0036]     If the signal LDEN is switched on again, the signal EOR is set to a binary “0” again and the voltage Vx follows the voltage VD again. This is shown in section C of  FIG. 4 . As soon as the signal LDEN is switched off again, the described decrease of the voltage Vx starts again and the signal EOR changes from a binary “0” to a binary “1” again. This results in a time duration TD 2  between the points in time T 2   a  and T 2   b.    
         [0037]     Due to the linear decrease of the voltage Vx, the time durations TD 1  and TD 2  correspond to the values V 1  and V 2  of the voltage Vx at the point in time at which the signal LDEN changes. These time durations TD 1  and TD 2  may then be forwarded to a period counter or other means for time-measurements, so that the time durations TD 1  and TD 2  are converted into digital count values.  
         [0038]     As a result, the test circuit  20  is able to create time durations TD 1  and TD 2  from the signal of the device under test being connected at the pin DUT by switching the buffer  81  in a high impedance state and by switching the signal LDEN off. These time durations TD 1  and TD 2  may then be converted (e.g. into digital count values) corresponding to the values V 1  and V 2  of the voltage as sampled at the pin DUT in the points in time at which the signal LDEN is switched off.