Abstract:
A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

Description:
BACKGROUND 
       [0001]    Technical Field 
         [0002]    The present disclosure generally relates to semi-floating gate devices for use in semiconductor memory applications. 
         [0003]    Description of the Related Art 
         [0004]    A FinFET is an electronic switching device in which a conventional planar semiconducting channel is replaced by a semiconducting fin that extends outward from a top surface of a silicon substrate. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance and reduced current leakage than is possible with a planar transistor. FinFETs are described in further detail in U.S. Pat. No. 8,759,874, and U.S. Patent Application Publication US2014/0175554, assigned to the same assignee as the present patent document. 
         [0005]    A vertical GAA FET is a linear, or 1-D, device in the form of a nanowire, oriented transverse to planar front and back surfaces of the silicon substrate. The nanowire includes source, channel, and drain regions that are grown epitaxially. One or more annular gates surround the channel region, capacitively controlling current flow through the channel from all sides. GAA FETs are described in further detail in U.S. patent application Ser. Nos. 14/588,337 and 14/675,536, assigned to the same assignee as the present patent document. 
         [0006]    Floating gate transistors are used in non-volatile semiconductor memory applications such as flash memory and electrically programmable read only memory (EPROM) devices. A conventional floating gate (FG) transistor memory cell is a variant of a metal-oxide-semiconductor field effect transistor (MOSFET) device. In a MOSFET, a voltage applied to a control gate electrode controls current flow in a channel between source and drain terminals. The control gate is separated from the channel by a gate dielectric. In a floating gate transistor, a second, floating, gate is inserted in the dielectric between the channel region and the control gate. The floating gate is thus electrically isolated, so that charge placed onto the floating gate is trapped. The control gate can then be used either to inject charge onto, or to extract charge from, the floating gate to change the bit state of the memory cell, via a tunneling effect. Depending on its polarity, charge trapped on the floating gate will then either permit or block current flow in the channel. 
         [0007]    A semi-floating gate (SFG) transistor is shown schematically in  FIG. 2 a   , and in cross-section in  FIG. 2 b   , as described in “A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation,” P. F. Wang et al.,  Science  v. 341, August 2013. The SFG transistor differs from a FG transistor in that the second gate is coupled to the drain, forming a p-n junction diode. Thus, the electric potential of the SFG transistor is not truly floating, but instead is semi-floating. In one implementation, the control gate is also extended to form an embedded tunneling FET (TFET) that biases the p-n diode accordingly, to charge or discharge the SFG transistor. Thus, the SFG transistor includes three devices in one: a MOS transistor, a p-n diode, and a TFET. A conventional SFG transistor is capable of operating at low voltages, less than 2.0 V, and high speeds, on the order of a nanosecond, to complete a write operation. Thus, SFG transistors appear to be promising in that they reduce power consumption while increasing the speed of volatile memory devices. However, a disadvantage of the SFG transistor shown in  FIGS. 2 a  and 2 b    is that the extensions made to form the p-n diode and the TFET increase the footprint of the device, which limits the memory density of a SFG transistor array. 
       BRIEF SUMMARY 
       [0008]    A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate. The source, drain, and channel are vertically aligned, on top of one another in either a fin configuration or a gate all-around vertical nanowire configuration. In the fin configuration, current flow between the source and the drain is influenced from two sides of the channel by a control gate and a semi-floating gate. In the vertical nanowire configuration, current flow is influenced radially by concentric wrap-around gates. In both configurations, the semi-floating gate is adjacent to the channel. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical SFG FET device. 
         [0009]    The vertical SFG FET further includes a vertical TFET, and a vertical p-n diode. A vertical TFET suitable for low-power, low-voltage applications is disclosed in U.S. patent application Ser. Nos. 14/675,298 and 14/675,536, assigned to the same assignee as the present patent document. Fabrication of the vertical SFG FET is compatible with conventional CMOS manufacturing processes, including replacement metal gate (RMG) and self-aligned contact (SAC) processes. Low-power operation allows the vertical SFG FET to provide a high current density, or “current per footprint” on a chip, compared with conventional planar devices. Hence, the vertical SFG FET provides improvements in memory density as well as improving speed and power consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0010]    In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. 
           [0011]      FIG. 1  is a circuit schematic diagram of a conventional floating gate transistor used in volatile memory products, according to the prior art. 
           [0012]      FIG. 2A  is a circuit schematic diagram representing a semi-floating gate (SFG) transistor that includes an embedded TFET, such as the devices described herein. 
           [0013]      FIG. 2B  is a schematic diagram showing the terminals and doped regions of a tunneling field effect transistor (TFET) such as those described herein. 
           [0014]      FIG. 3  is a flow diagram showing steps in a method of fabricating a vertical semi-floating gate FET as illustrated in  FIGS. 4-13 , according to one embodiment described herein. 
           [0015]      FIGS. 4-13  are cross-sectional views of a vertical semi-floating gate FET at successive steps during fabrication, using the method outlined in  FIG. 3 . 
           [0016]      FIG. 4  shows layers that will make up the vertical SFG FET, according to one embodiment described herein. 
           [0017]      FIG. 5  shows the N ++  source region and the N −  channel region of the vertical SFG FET, according to one embodiment described herein. 
           [0018]      FIG. 6  shows the channel region with a gate dielectric and sidewall spacers, according to one embodiment described herein. 
           [0019]      FIG. 7  shows the channel region of  FIG. 6  after formation of a p-n diode, according to one embodiment described herein. 
           [0020]      FIG. 8  shows a vertical SFG FET after formation of the semi-floating gate, according to one embodiment described herein. 
           [0021]      FIGS. 9, 10  show the vertical SFG FET of  FIG. 8  after formation of an extension of the channel region, according to one embodiment described herein. 
           [0022]      FIG. 11  shows the vertical SFG FET of  FIG. 10  after formation of the control gate, according to one embodiment described herein. 
           [0023]      FIG. 12  shows the vertical SFG FET of  FIG. 11  after formation of a cap over the control gate, according to one embodiment described herein. 
           [0024]      FIG. 13  shows the vertical SFG FET of  FIG. 12  after formation of the N ++  drain region, according to one embodiment described herein. 
           [0025]      FIG. 14  is a flow diagram showing steps in an alternative method of fabricating a vertical SFG FET as illustrated in  FIGS. 15-18 , according to one embodiment described herein. 
           [0026]      FIGS. 15-18  are cross-sectional views of a vertical SFG FET at successive steps during fabrication, using the method outlined in  FIG. 14 . 
           [0027]      FIG. 15  shows the vertical SFG FET of  FIG. 9  after formation of the N ++  drain region, according to one embodiment described herein. 
           [0028]      FIG. 16  shows the vertical SFG FET of  FIG. 15  after formation of sidewall spacers, according to one embodiment described herein. 
           [0029]      FIG. 17  shows the vertical SFG FET of  FIG. 16  after recessing the control gate, according to one embodiment described herein. 
           [0030]      FIG. 18  shows the vertical SFG FET of  FIG. 17  after formation of a contact hole accessing the N ++  drain region, according to one embodiment described herein. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]    In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure. 
         [0032]    Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.” 
         [0033]    Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure. 
         [0034]    Reference throughout the specification to integrated circuits is generally intended to include integrated circuit components built on semiconducting substrates, whether or not the components are coupled together into a circuit or able to be interconnected. Throughout the specification, the term “layer” is used in its broadest sense to include a thin film, a cap, or the like, and one layer may be composed of multiple sub-layers. 
         [0035]    Reference throughout the specification to conventional thin film deposition techniques for depositing silicon nitride, silicon dioxide, metals, or similar materials include such processes as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electro-less plating, and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. For example, in some circumstances, a description that references CVD may alternatively be done using PVD, or a description that specifies electroplating may alternatively be accomplished using electro-less plating. Furthermore, reference to conventional techniques of thin film formation may include growing a film in-situ. For example, in some embodiments, controlled growth of an oxide to a desired thickness can be achieved by exposing a silicon surface to oxygen gas or to moisture in a heated chamber. 
         [0036]    Reference throughout the specification to conventional photolithography techniques, known in the art of semiconductor fabrication for patterning various thin films, includes a spin-expose-develop process sequence typically followed by an etch process. Alternatively or additionally, photoresist can also be used to pattern a hard mask (e.g., a silicon nitride hard mask), which, in turn, can be used to pattern an underlying film. 
         [0037]    Reference throughout the specification to conventional etching techniques known in the art of semiconductor fabrication for selective removal of polysilicon, silicon nitride, silicon dioxide, metals, photoresist, polyimide, or similar materials includes such processes as wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical-mechanical planarization (CMP) and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. In some instances, two such techniques may be interchangeable. For example, stripping photoresist may entail immersing a sample in a wet chemical bath or, alternatively, spraying wet chemicals directly onto the sample. 
         [0038]    Specific embodiments are described herein with reference to semi-floating gate devices that have been produced; however, the present disclosure and the reference to certain materials, dimensions, and the details and ordering of processing steps are exemplary and should not be limited to those shown. 
         [0039]    Turning now to the figures,  FIG. 1  shows a conventional circuit schematic representation of a floating gate transistor  100 . The floating gate transistor  100  includes a source  102 , a drain  104 , a control gate  106 , and a floating gate  108 . In operation, current flows through a channel  105  between the source  102  and the drain  104  in response to a voltage applied to the control gate  106 . A gate dielectric separating the control gate  106  from the channel  105  includes two layers—a first dielectric layer  107  separating the control gate  106  from the floating gate  108 , and a second dielectric layer  109  separating the floating gate  108  from the channel  105 . There are no direct electrical connections to the floating gate  108 . The voltage on the floating gate  108  floats, according to the influence of nearby electric charge. However, charge on the floating gate  108  can be altered by applying a voltage to the control gate  106 , causing electrons to tunnel from the control gate  106 , through the first dielectric layer  107 , to the floating gate  108 . Such a tunneling process is known by those skilled in the art as Fowler-Nordheim tunneling. 
         [0040]      FIG. 2A  shows a circuit schematic representation of a semi-floating gate (SFG) transistor  110 , such as the vertical SFG transistors described herein. 
         [0041]    The semi-floating gate transistor  110  includes an N ++  source  112 , an N ++  drain  114 , a control gate  116 , and a semi-floating gate  118 . In operation, current flows through an N −  channel  115  between the N ++  source  112  and the N ++  drain  114 . A second gate dielectric  117  separates the control gate  116  from the semi-floating gate  118 . A first gate dielectric  119  separates the semi-floating gate  118  from the N −  channel  115 . One end of the semi-floating gate  118  is electrically coupled to the N ++  drain  114  via a p-n diode  120  and an embedded tunneling FET (TFET)  130 , while the other end is floating. Thus, the semi-floating gate transistor  110  includes three devices in one: an MOS transistor, the TFET  130 , and the p-n diode  120 . When the voltage on the control gate  116  is negative, the TFET turns on and a tunneling current flows from the N ++  drain  114  to the semi-floating gate  118 , thereby charging the semi-floating gate  118 . When the voltage on the control gate  116  is positive, the p-n junction diode  120  is forward-biased and current flows from the semi-floating gate  118  to the N ++  drain  114 , thereby discharging the semi-floating gate  118 . 
         [0042]      FIG. 2B  shows an integrated n-channel implementation of the TFET  130  shown schematically in  FIG. 2A . The n-channel TFET  130  includes a TFET source terminal  132  that is heavily p-doped, a drain terminal  134  that is n-doped, a gate terminal  136 , a gate dielectric  138 , and a TFET channel  140  that is lightly n-doped. The n-channel TFET  130  operates in response to a positive voltage applied to the gate terminal  136 . Instead of being an n-p-n transistor, the n-channel TFET  130  is a p ++ -n − -n ++  device. Such a doping profile causes energy bands characterizing the silicon at the p ++ -n −  junction to be arranged so as to allow charge carriers to tunnel through the junction. Tunneling efficiency is improved when silicon germanium (SiGe) is used as the p ++  material. The TFET  130  is integrated into the semi-floating gate transistor  110  by coupling the TFET source terminal  132  to the semi-floating gate  118 , and the drain terminal  134  to the N ++  drain  114 . 
         [0043]      FIG. 3  shows steps in an inventive method  200  of fabricating a vertical SFG FET  270  that implements the vertical semi-floating gate transistor  110  as a nanoscale integrated circuit device, according to one embodiment. A p-n diode  120  and a TFET  130  are integrated into the structure of the vertical SFG FET. The completed vertical SFG FET  110   a  produced by the method  200  is shown in  FIG. 13 . An embodiment of the vertical SFG FET  110   b  that can be fabricated by a modified method  300  is shown in  FIG. 18 . Steps in the method  200  are further illustrated by  FIGS. 4-13 , and described below. 
         [0044]    At  202 , with reference to  FIG. 4 , a bulk silicon substrate  222  is doped to form a film stack  220  having multiple layers, according to one embodiment. The film stack  220  includes a heavily doped N ++  source region layer  224 , an intrinsic silicon layer  226 , and a lightly doped N −  channel region layer  228 . In one embodiment, dopants are incorporated into the N ++  source region layer  224  by ion implantation into a top surface  225  of the silicon substrate  222  and then annealed to drive in the N ++  source region dopants to a selected depth in the range of about 20-30 nm below the substrate surface  225 . Alternatively, the N ++  source region layer  224  can be formed by epitaxial growth from the bulk silicon substrate  222 , in which positive dopants such as boron ions can be introduced in-situ, during the epitaxy process. The source region dopant concentration is targeted at about 1.0 E20 cm −3 . Once the source region dopants are incorporated, a 10-15 nm layer of intrinsic silicon layer  226  is epitaxially grown from the surface  225  of the N ++  source region layer  224 . Then, the N −  channel region layer  228  can be grown epitaxially from a top surface  227  of the layer of intrinsic silicon layer  226 . The thickness of the channel region layer  228  is in the range of about 20-30 nm and the concentration of negative dopants is about 1.0 E19 cm −3 . Alternatively, the intrinsic silicon layer  226  can be made thicker, and the channel region layer  228  can be implanted in a top portion of the intrinsic silicon layer  226 . 
         [0045]    At  204 , with reference to  FIG. 5 , a vertical structure  229  is patterned in the film stack  220 , according to one embodiment. The vertical structure  229  can be directly patterned using, for example, a silicon nitride (SiN) hard mask  230 , conventional extreme ultraviolet (EUV) lithography, and conventional etching techniques. In one embodiment, the SiN hard mask  230  can be patterned to define a 2-D vertical structure  229  configured as a fin. In one embodiment, the SiN hard mask  230  can be patterned to define a 1-D vertical structure  229  configured as a nanowire. Accordingly, the vertical structure  229  as shown in cross-section in the Figures represents both the fin and the nanowire configurations. The doped layers  224 ,  226 , and  228  are then etched to form the N −  channel  115  and the N ++  source  112 . The hard mask  230  has a thickness in the range of about 30-50 nm. The etching process continues beyond the intrinsic silicon layer  226  so as to shape the N ++  source  112 , but stopping before the boundary of the silicon substrate  222  is reached. The remaining partial N ++  source region layer  224  that extends across the silicon substrate  222  will later serve as a front side contact landing pad providing electrical access to the N ++  source  112 . The resulting vertical structure  229  has a width, or critical dimension, in the range of about 6-15 nm. 
         [0046]    Alternatively, the narrow vertical structure  229  may be patterned using a self-aligned sidewall image transfer (SIT) technique. The SIT process is capable of defining very high aspect ratio vertical structures  229  using sacrificial SiN sidewall spacers as the hard mask  230 . According to the SIT technique, a mandrel, or temporary structure, is formed first, on top of the channel region layer  228 . Then a silicon nitride film is deposited conformally over the mandrel and planarized, forming sidewall spacers on the sides of the mandrel. Then the mandrel is removed, leaving behind a pair of narrow sidewall spacers that serve as the hard mask  230 . Using such a technique, very narrow mask features can be patterned in a self-aligned manner, without lithography. The SIT technique is also well known in the art and therefore is not explained herein in detail. The vertical structure  229  thus formed will serve as a lightly-doped channel region of the SFG FinFET devices. 
         [0047]    After the vertical structure  229  is formed, a thick layer of silicon dioxide (SiO 2 )  232  is deposited and initially is planarized, using a chemical-mechanical planarization (CMP) process, to stop on the hard mask  230 . The rest of the vertical structure  229  is then revealed by recessing the oxide layer  232  down to the top of the N ++  source region layer  224  using, for example, a proprietary chemical oxide removal (COR) process available from Tokyo Electron America of Austin, Tex. Alternatively, the oxide recess can be performed using a proprietary silicon-cobalt-nickel oxide etching process available from Applied Materials Corporation of Santa Clara, Calif. After the oxide recess process is complete, the oxide layer  232  has a thickness within the range of about 10-20 nm. 
         [0048]    At  206 , with reference to  FIG. 6 , a gate dielectric film  234  is formed on the sidewalls of the vertical structure  229 , according to one embodiment. A thin, 2-5 nm dielectric layer is deposited conformally to cover the vertical structure  229 , the oxide layer  232 , and the hard mask  230 , followed by deposition of a conformal SiN hard mask layer (not shown). The gate dielectric layer  234  can be made of, for example, SiO 2 . Next, horizontal portions of the SiN hard mask are removed using a reactive ion etching process that has high selectivity to both silicon and oxide. The etching process is then continued to “pull down” the SiN, leaving behind the sidewall spacer  236 , as shown in  FIG. 6 , which extends about half way up both sides of the lightly doped channel region layer  228 . Because the gate dielectric layer  234  is so thin, horizontal portions of the gate dielectric layer  234  are also removed during the SiN pull-down process, leaving behind a portion of the vertical gate dielectric layer  234  that serves as the first gate dielectric  119 . The sidewall spacer  236  will act as a mask during subsequent step  208 . 
         [0049]    At  208 , with reference to  FIG. 7 , a TFET and a p-n diode are formed, according to one embodiment. First, in preparation for epitaxial growth, an optional cleaning step can be performed using hydrochloric acid (HCl). This is known in the art as an ‘SC1 epi pre-clean.’ Then, P ++ -doped SiGe regions that form the TFET source terminal  132  are epitaxially grown from exposed sidewalls of the N −  channel  115  that are not covered by the sidewall spacer  236 . P ++  dopants, e.g., a high concentration of boron atoms, are incorporated in-situ into the epitaxial SiGe, to form p-n junctions with the N −  channel  115 , at the sidewall of the vertical structure  229 . After formation of the P ++ -doped SiGe regions, the remaining sidewall spacer  236  can be removed by exposure to phosphoric acid. 
         [0050]    At  210 , with reference to  FIG. 8 , the semi-floating gate  118  is formed, according to one embodiment. First, a polysilicon layer  240  is deposited on the oxide layer  232 , and planarized to stop on the hard mask  230 . The polysilicon layer  240  is then patterned to define the semi-floating gate  118 , which abuts the first gate dielectric  119  on either side of the vertical structure  229 . 
         [0051]    At  212 , with reference to  FIGS. 9 and 10 , the TFET channel  140  is formed, according to one embodiment. First, a thick oxide layer  242  is deposited and planarized to stop on the hard mask  230  as shown in  FIG. 9 . Then, the hard mask  230  is removed, creating a trench, at the bottom of which an upper surface of the N −  channel  115  is exposed. A trench epitaxial growth process then produces a lightly doped N −  silicon film that serves as the TFET channel  140 . A concentration of arsenic or phosphorous dopants that are incorporated, in-situ, into the epitaxial silicon, is in the range of about 2.0-3.0 E19 cm −3 , which is slightly more than the concentration of dopants in the N −  channel  115 . 
         [0052]    At  214 , with reference to  FIGS. 9-11 , the control gate  116  is formed, according to one embodiment. First, the remaining volume of the trench, occupied by the TFET channel  140 , is filled with a SiN plug  246 . Then, the thick oxide layer  242  is removed, as shown in  FIG. 10 . Next, a thin high-k gate dielectric layer  248  is conformally deposited over exposed surfaces of the oxide layer  232 , the semi-floating gate  118 , sidewalls of the TFET channel  140 , and the SiN plug  246 , in a stair-step pattern, as shown in  FIG. 11 . In one embodiment, the high-k gate dielectric layer  248  is a 2-5 nm thick film of a high-k material such as, for example, halfnium oxide (HfO 2 ). Next, a dummy polysilicon layer  250  is formed in contact with the high-k gate dielectric layer  248 . The dummy polysilicon layer  250  serves as a form for sidewall spacers. The high-k gate dielectric layer  248  and the dummy polysilicon layer  250  are then patterned together so that they extend along the surface of the oxide layer  232  to a distance of about 30 nm out from the center of the vertical structure  229 . Next, SiN sidewall spacers  252  are formed on the sides of the dummy polysilicon layer  250 . The sidewall spacers  252  can be formed in the usual way that entails blanket-depositing SiN over the gate structure, followed by a highly anisotropic SiN etch process that consumes all of the SiN on horizontal surfaces, while leaving behind most of the SiN on the vertical surfaces, thus forming the characteristic curved spacers shown in  FIG. 11 . The as-deposited SiN thickness is desirably in the range of about 6-12 nm. 
         [0053]    At  216 , with reference to  FIGS. 11-13 , the dummy polysilicon layer  250  is replaced with a metal control gate  116  and the N ++  drain  114  is formed on top of the fin  229 , according to one embodiment. First, the existing structure is covered with a dielectric layer  258 , e.g., SiO 2 , and planarized to stop on the SiN plug  246 , as shown in  FIG. 12 . Next, with the sidewall spacers  252  in place and being supported by the dielectric layer  258 , the entire dummy polysilicon layer  250  can be stripped away, for example, in an ammonium hydroxide (NH 4 OH) bath, and replaced with metal to form the control gate  116 . The control gate  116  is a work function metal, for example, a bi-metallic layer in which a first layer is made of titanium nitride (TiN) and/or titanium carbide (TiC) and a second layer is made of tungsten (W). The work function metal is initially deposited and planarized to the top of the sidewall spacer. Then the work function metal and the high-k gate dielectric layer  248  are recessed to match the height of the TFET channel  140 , thus completing formation of the second gate dielectric  117  and the control gate  116 . Then, the space between the tops of the sidewall spacers  252  is filled with an additional layer of SiN  262  up to the top surface of the SiN plug  246 , as shown in  FIG. 12 . Next, the dielectric layer  258  is extended, e.g., SiO 2 , is deposited on top of the existing structure, and then patterned to form a V-shaped trench  266  that extends downward through the dielectric layer  258  and the SiN plug  246 , to the TFET channel  140 . The N ++  drain  114  is then epitaxially grown to partially fill the V-shaped trench  266 . During the epitaxial growth, the N ++  drain  114  is doped in-situ with negative dopants, e.g., phosphorous or arsenic, to a concentration of about 2.0-3.0 E  20 . The remaining empty volume of the V-shaped trench  266  can later accept a metal drain contact. Meanwhile, contacts to the lateral extension of the N ++  source region layer  224  and the control gate  116  can be made in a similar fashion by forming trenches through the dielectric layer  258  and the SiN  262 , according to known methods. The completed vertical semi-floating gate FET  110   a  is shown in  FIG. 13 . 
         [0054]      FIG. 14  shows an inventive alternative method  300  of fabricating a vertical semi-floating gate FET  110   b  according to one embodiment in which the N ++  drain  114  is self-aligned. The completed vertical SFG FET  110   b  produced by the method  300  is shown in  FIG. 18 . The steps  302 - 312  correspond to steps  202 - 212  in the method  200 . However, the steps  314 - 316  are in the reverse order of steps  214 - 216 , wherein the N ++  drain  114  is formed first, followed by formation of the control gate  116 . 
         [0055]    At  314 , with reference to  FIG. 15 , the N ++  drain  114  is grown epitaxially directly following the epitaxial growth that forms the TFET channel  140 , for example, by simply extending the time interval of the epitaxial growth process while increasing the in-situ dopant concentration. 
         [0056]    At  316 , with reference to  FIGS. 15-18 , the dummy polysilicon layer  250  is formed as a mold for the sidewall spacers  252 , and then the dummy polysilicon layer  250  is removed and replaced with metal to form the metal control gate  116 . First, the space above the N ++  drain  114  is filled with the SiN plug  246  and planarized down to the top surface of the thick oxide layer  242 , before removing the thick oxide layer  242 . With reference to  FIG. 16 , the high-k gate dielectric layer  248  and the dummy polysilicon layer  250  are then deposited and patterned as described above, followed by formation of the SiN sidewall spacers  252  in the usual way, as is known in the art. With reference to  FIG. 17 , the dummy polysilicon layer  250  is then partially recessed, to a level below the N ++  drain  114 , to allow recessing the high-k gate dielectric layer  248  from the sides of the N ++  drain  114 , e.g., using a hydrofluoric acid-based wet etch. The remaining dummy polysilicon layer  250  is then stripped and replaced with the work function metal and tungsten, as described above, and planarized to the level of the SiN plug  246 . The work function metal is then recessed down to the level of the bottom surface of the N ++  drain  114 . The remaining space above the metal control gate  116  is then filled with SiN, and the structure is covered with the dielectric layer  258  to produce the final structure shown in  FIG. 18 . As described above, contacts can be etched through the various oxide and SiN layers to access the source, control gate, and drain terminals from the front side of the wafer, by methods well known in the art. 
         [0057]    By comparing the schematics shown in  FIGS. 2 a  and 2 b    with the completed devices  110   a ,  110   b  shown in  FIGS. 13 and 18 , respectively, a correspondence can be drawn between the terminals of the schematic and the various regions of the integrated vertical SFG FET. Embodiments  110   a ,  110   b  of the integrated vertical SFG FET include the highly doped N ++  source  112  on the bottom, the lightly-doped N −  channel  115  within the vertical structure  229 , and the N ++  drain  114  that is heavily doped to have a same polarity as that of the N −  channel  115  and the N ++  source  112 . The N −  channel  115  extends between the source and drain regions  112 ,  114 . In the fin configuration, the semi-floating gate  118  abuts the fin from two sides. Likewise, the control gate  116  abuts the semi-floating gate  118  so as to attract or repel charge on the semi-floating gate  118  in response to an applied voltage. The metal control gate  116  is L-shaped so as to form an embedded TFET at the drain end of the device. In the nanowire configuration, the semi-floating gate  118  and the control gate  116  wrap around the nanowire in a concentric arrangement. The P ++ -doped SiGe region that serves as the TFET source terminal  132  is positioned between the N −  channel  115  and the semi-floating gate  118 , at the drain end of the N −  channel  115 , thus forming a p-n junction diode between the P ++ -doped SiGe and the N ++  drain  114 . 
         [0058]    It will be appreciated that, although specific embodiments of the present disclosure are described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not limited except as by the appended claims. 
         [0059]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. 
         [0060]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.