Abstract:
Disclosed is a method and circuit for synchronizing dual data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second parallel data buses, respectively, coupled thereto. The receiving circuit compares first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion. The receiving circuit stores into a first FIFO, all first-stream multibit data portions that follow the identified first-stream multibit data portion. The receiving circuit also compares second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion. The receiving circuit stores into a second FIFO, all second-stream multibit data portions that follow the identified second-stream multibit data portion.

Description:
BACKGROUND OF THE INVENTION 
   Local switching networks (e.g., a switching network contained within an office building) may include a switching fabric that couples end-devices via line cards. The term “switching fabric” describes a distributed switching matrix that establishes a circuit through which data may be transmitted. A switching fabric may include a stored programmable control that seeks out a suitable combination of time slots and multiplexed highways for establishing a communication circuit between end devices. Multiple highways can simultaneously exist. The term “end device” may include desktop computers, printers, routers, other networking equipment, etc. 
     FIG. 1  illustrates relevant portions of an exemplary local switching network  100 . In  FIG. 1 , local switching network  100  includes a switching fabric  102  (e.g., a cross-bar switching fabric) coupled to line cards  104  through  108 . Each of the line cards may be coupled to one or more end devices or other networks.  FIG. 1  shows line card  104  coupled to end devices  110  through  114 , line card  106  coupled to end devices  116  through  120 , and line card  108  coupled to end devices  122  through  126 . 
   Local switching network  100  shown in  FIG. 1  may employ one of many different communication protocols enabling data communication between one or more end devices  110  through  126  via line cards  104  through  108  and switching fabric  102 .  FIG. 1  will be described with reference to a communications protocol in which end devices communicate with each other by transferring data frames. Each data frame includes one or more lines of data. 
   Line cards  104  through  108  are coupled to switching fabric  102  via one or more serial data links. In  FIG. 1  line card  104  is coupled to switching fabric  102  via serial downlink  128  and serial up-link  130 ; line card  106  is coupled to switching fabric  102  via serial downlink  132  and serial up-link  134 ; and line card  108  is coupled to switching fabric  102  via serial downlink  136  and serial up-link  138 . Each of line cards  104  through  108  is coupled to its respective end devices via a common bus. Line card  104  is coupled to end devices  110  through  114  via common bus  140 ; line card  106  is coupled to end devices  116  through  120  via common bus  142 ; and line card  108  is coupled to end devices  122  through  126  via common bus  144 . 
     FIG. 2   a  illustrates components of line card  104  of  FIG. 1  relevant to the discussion of the present invention. More particularly,  FIG. 2   a  shows line card  104  having circuit  150  coupled to circuit  152  via data buses  154   a  and  154   b . Although not shown, each of the data buses  154   a  and  154   b  includes a plurality of conductive lines or traces formed on a printed circuit board for transmitting data bit signals between circuits  150  and  152 . Circuit  150  is shown coupled to end devices  110  through  114  via common bus  140 . Circuit  152  is shown coupled to serial up-link  130 . 
   In operation, circuit  150  receives frames of data lines from end devices  110  to  114  via common bus  140 . Although not shown, line card  104  includes circuitry which analyzes the received data lines to determine whether they are to be routed locally to one of the end devices  110  through  114 , or via switching fabric  102  to one of the end devices coupled to line cards  106  or  108 . If line card  104  determines that the received frames are to be routed locally, the received frames are transmitted back to one of the end devices  110  through  114  via common bus  140 . If line card  104  determines that the received frames are to be routed to one of the end devices coupled to line cards  106  or  108 , then circuit  150  transmits the received frames via data buses  154   a  and  154   b . Circuit  152  reformats the frames received from circuit  150  for subsequent transmission to fabric  102  via serial up-link  130 . Circuit  152  may also add routing information to each frame or data line thereof prior to their transmission to switching fabric  102 . 
     FIG. 2   b  illustrates components of circuits  150  and  152  shown in  FIG. 2   a  that are relevant to discussion of the present invention. Circuit  150  includes a data line FIFO  160  coupled to a plurality of input/output (IO) devices  162  and a plurality of IO devices  164 . For ease of illustration,  FIG. 2   b  shows only one of the IO devices  162  and one of the IO devices  164 . Circuit  152  includes a data line FIFO  170  connected to the plurality of IO devices  172  and the plurality of IO devices  174 . For ease of illustration,  FIG. 2   b  shows only one of the IO devices  172  and one of the IO devices  174 . 
   Operational aspects of transmitting data between circuits  150  and  152  will be described with respect to  FIG. 2   b . In general, FIFO  160  sequentially receives data lines from one of the end devices  110  through  114 . FIFO  160  temporarily stores the received data lines until they are ready to be transmitted to circuit  152 . When ready, FIFO  160  outputs a data line with each transition edge (i.e., rising or falling edge) of a clock provided thereto. Equally sized upper and lower portions of each data line are simultaneously provided to IO devices  162  and IO devices  164 , respectively. IO devices  162  and IO devices  164  transmit the upper and lower portions, respectively, to data buses  154   a  and  154   b , respectively, with each transition edge of the clock signal provided thereto. Data buses  154   a  and  154   b , in turn, transmit in parallel the upper and lower portions to IO devices  172  and IO devices  174 , respectively, of circuit  152 . With each transition edge of the clock or clocks provided to IO devices  172  and IO devices  174 , the upper and lower portions transmitted by data buses  154   a  and  154   b , respectively, are reassembled and stored in FIFO  170 . 
   The operation of circuits  150  and  152  described above presumes no relative delay in the transmission of corresponding upper and lower portions of data lines between FIFOs  160  and  170 . In practice, the transmission of data line portions between FIFO  160  and FIFO  170  is subject to one or more relative delays. For example, variations in temperature of components of IO devices  162  and  164 , variations in power supply voltage provided to IO devices  162  and  164 , or physical variations of the transistors that form IO devices  162  and  164 , may result in IO devices  162  transmitting the upper portion of a data line before or after transmission of the corresponding lower portion of the data line by IO devices  164 . The traces of data bus  154   a  on average may be longer or shorter than the average length of traces of data bus  154   b  such that the data bus transmission time for the upper portion of data lines may be greater or smaller than the data bus transmission time of the corresponding lower portion. The clock signal provided to IO devices  162  may be delayed with respect to the clock signal provided to IO devices  164 . IO devices  172  and  174 , like their counterparts  10  devices  162  and  164 , are subject to variations in operating temperature and variations in the power supply provided thereto. The transistors that form IO devices  172  and  174  may differ physically. Additionally, the clock signal provided to IO devices  172  may be delayed with respect to the clock signal provided to IO devices  174 . As a result of one or more of the above delay factors, IO devices  172  may gate the upper portion of a data line received via data bus  154   a  before or after IO devices  174  gate the corresponding lower portion received via data bus  154   b.    
     FIG. 2   c  illustrates the potential effects of relative delays in transmission of corresponding upper and lower data line portions between FIFO  160  and FIFO  170 .  FIG. 2   c  shows contents of FIFO  160  at time t=t 0 . More particularly, FIFO  160  stores n data lines destined to be transmitted via data buses  154   a  and  154   b  to FIFO  170 . In FIFO  160 , Ax and Bx represent the upper and lower portions of each data line Dx, respectively. For example, data lines A 1  and B 1  represent the upper and lower portions of data line D 1 , respectively.  FIG. 2   c  also illustrates FIFO  170  after data lines D 1  through Dn have been transmitted as described above. For purposes of explanation, it will be presumed that transmission of the upper portion of each data line between FIFO  160  and FIFO  170  is delayed with respect to the corresponding lower portion. Because of the relative delay, corresponding upper and lower data line portions are not reassembled by circuit  152  into valid data lines prior to storage in FIFO  170 .  FIG. 2   c  shows the contents of FIFO  170  after transmission of the data lines D 1  through Dn. As can be seen in  FIG. 2   c , the data lines stored in FIFO  170  are invalid since they consist of noncorresponding upper and lower portions. 
   SUMMARY OF THE INVENTION 
   Disclosed is a method and circuit for synchronizing dual data buses. It is noted that the method and circuit may used to synchronize more than two data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second parallel data buses, respectively, coupled thereto. The receiving circuit compares first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion. The receiving circuit stores into a first FIFO, all first-stream multibit data portions that follow the identified first-stream multibit data portion. The receiving circuit also compares second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion. The receiving circuit stores into a second FIFO, all second-stream multibit data portions that follow the identified second-stream multibit data portion. One multibit portions are stored in the first and second FIFOs, the first and second FIFOs sequentially output multibit data portions for subsequent concatenation. 

   
     BRIEF DESCRIPTION OF THE FIGURES 
     The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying figures. The use of the same reference number throughout the figures designates a like or similar element. 
       FIG. 1  illustrates and exemplary local switching network; 
       FIG. 2   a  illustrates relevant components of a line card contained in  FIG. 1 ; 
       FIG. 2   b  illustrates relevant components of circuits contained within the line card of  FIG. 2   a;    
       FIG. 2   c  illustrates operational aspects of the circuits shown in  FIG. 2   b;    
       FIG. 3  illustrates relevant portions of a local switching network employing one embodiment of the present invention; 
       FIG. 4  illustrates relevant portions of a line card employed within the network of  FIG. 3 ; 
       FIG. 5  illustrates relevant portions of the circuits contained within the line card of  FIG. 4 ; and 
       FIGS. 6  though  9  illustrate operational aspects of the circuits shown in  FIG. 5 . 
   

   While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the figures and will herein be described in detail. However, the figures and detailed description thereto are not intended to limit the invention to the particular form disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
   DETAILED DESCRIPTION 
     FIG. 3  illustrates relevant portions of a local switching network  200  employing the present invention. The present invention should not be limited to use within a switching network. Rather, the present invention will find application in systems where data is transmitted between separate circuits via two or more data buses. 
   Local switching network  200  includes a switching fabric (e.g., a cross-bar switching fabric) coupled to line cards  204  through  208 . Line card  204  is coupled to end devices  210  through  214 ; line card  206  is coupled to end devices  216  through  220 ; and line card  208  is coupled to end devices  222  through  226 . Devices or circuits can be coupled together either directly, i.e., without any intervening device or circuit, or indirectly, with one or more intervening devices or circuits. As used herein, the terms “connected devices” or “connected circuits” means two or more devices or circuits directly connected together with no intervening device or circuit. The term “coupled” includes the term “connected” within its definition. 
   The local switching network  200  shown in  FIG. 3  may employ one of many different communication protocols enabling data communication between one or more end devices  210  through  226  via line cards  204  through  208  and switching fabric  202 . The switching network  200  shown in  FIG. 3  will be described as employing a communications protocol in which end devices communicate with each other by transferring data frames via the line cards and the switching fabric. End devices (e.g., end devices  210  and  214 ) can locally communicate with each other without having to transmit frames via the line cards and switching fabric. 
   Line cards  204  through  208  are coupled to switching fabric via one or more serial data links. In  FIG. 3 , line card  204  is coupled to switching fabric  202  via serial downlink  228  and serial up-link  230 ; line card  206  is coupled to switching fabric  202  via serial downlink  232  and serial up-link  234 ; and line card  208  is coupled to switching fabric  202  via serial downlink  236  and serial up-link  238 . Line cards  204  through  208  communicate with their respective end devices via a common bus. Line card  204  communicates with end devices  210  through  214  via common bus  240 ; line card  206  communicates with end devices  216  through  220  via common bus  242 ; and line card  208  communicates with end devices  222  through  226  via common bus  244 . 
     FIG. 4  illustrates portions of line card  204  relevant to one embodiment of the present invention. In  FIG. 4 , line card  204  includes a circuit  250  coupled to a circuit  252  via a pair of source-synchronous data buses  254   a  and  254   b . It should also be understood that the present invention should not be limited to circuits coupled via source-synchronous data buses. Rather, data buses other than source-synchronous data buses may be employed between circuits  250  and  252 . Data buses  254   a  and  254   b  transmit data line portions from circuit  250  to circuit  252  as will be more fully described below. A separate pair of data buses (not shown) is provided for transmitting data line portions from circuit  252  to circuit  250 . The present invention will be described with respect to the transmission of data line portions from circuit  250  to circuit  252 , it being understood that the present invention may find application with respect to transmission of data line portions from circuit  252  to circuit  250 . 
   Each of the data buses  254   a  and  254   b  includes a plurality of conductive lines or traces for transmitting data portions. A data portion consists of a plurality of data bits. Additionally, each of the data buses  254   a  and  254   b  includes a trace for conducting a strobe or clock. Data buses  254   a  and  254   b  are capable of simultaneously transmitting data portions and clocks. The traces of data buses  254   a  and  254   b  may be formed on a printed circuit board (not shown). 
   In operation, circuit  250  receives data lines from end devices  210  through  214  via common bus  240 . Although not shown, line card  204  includes circuitry which analyzes the received data lines to determine whether they are to be routed locally to one of the end devices  210  through  214 , or via switching fabric  202  to one of the end devices coupled to line cards  206  or  208 . If circuitry of line card  204  determines that the received data lines are to be routed locally, the received data lines are transmitted back to one of the end devices  210  through  214  via common bus  240 . If circuitry of line card  204  determines that the received data lines are to be routed to one of the end devices coupled to line cards  206  or  208 , then, as will be more fully described below, circuit  250  transmits the received data lines to circuit  252  via data buses  254   a  and  254   b . Data lines are transmitted to circuit  252  in data portions of equal size. More particularly, corresponding upper and lower portions of each data line are transmitted to circuit  252  via data buses  254   a  and  254   b , respectively. Circuit  252  then reassembles corresponding upper and lower data portions back into data lines for subsequent processing. 
   Transmission of upper data line portions between circuits  250  and  252  is presumed delayed with respect to the transmission of corresponding lower data line portions. Without the present invention, upper and lower portions of data lines transmitted to circuit  252  may be improperly reassembled. Circuits  250  and  252  operate to insure that the received upper and lower data line portions are properly reassembled into valid data lines notwithstanding relative delay in their transmission. Circuits  250  and  252  operate in this manner after a data transmission synchronizing function (more fully described below), is performed. 
     FIG. 5  illustrates relevant portions of one embodiment of circuits  250  and  252  shown in  FIG. 4 . More particularly, circuit  250  shown in  FIG. 5  includes a data line FIFO  260  configured to receive data lines from one of the end devices  210  through  214 . FIFO  260  stores the received data lines until they are ready to be transmitted to circuit  252 . Circuit  250  also includes a multiplexer  262 . Multiplexer  262  couples its output to programmable memory  264  or to FIFO  260  depending on the state of a control signal generated by a control circuit  266 , as will be more fully described below. Lastly, circuit  250  includes a plurality of IO devices  270   a  and a plurality of IO devices  270   b . For ease of illustration,  FIG. 5  shows only one of the IO devices  270   a  and one of the devices  270   b . Each of the IO devices  270   a  is coupled to a respective trace of data bus  254   a , while each of the IO devices  270   b  is coupled to a respective trace of data bus  254   b . IO devices  270   a  and IO devices  270   b  transmit data portions to circuit  250  via buses  254   a  and  24   b , respectively. 
   Circuit  252  includes a plurality of IO devices  272   a  and a plurality of IO devices  272   b . For purposes of illustration,  FIG. 5  shows only one IO device  272   a  and one IO device  272   b . Each IO device  272   a  is coupled to a respective trace of data bus  254   a , while each IO device  272   b  is coupled to a respective trace of data bus  254   b . IO devices  272   a  and IO devices  272   b  receive data portions via data buses  254   a  and  254   b , respectively. Circuit  252  of  FIG. 5  further includes FIFOs  274   a  and  274   b , the data inputs of which are coupled to IO devices  272   a  and IO devices  272   b , respectively. FIFOs  274   a  and  274   b  take form in synchronizing FIFOs, it being understood that the present invention should not be limited thereto. Although not shown, respective clock signals of source-synchronous data buses  254   a  and  245   b  are provided as write clocks for synchronizing FIFOs  274   a  and  274   b , respectively. The read clock provided to synchronizing FIFOs  274   a  and  273   b  may be derived from one of the clock signals provided by source-synchronous data bus  254   a  or  254   b.    
   Circuit  252  also includes a FIFO  276 , the input of which is coupled to the data outputs of FIFOs  274   a  and  274   b . Lastly, circuit  252  includes a NAND gate  284 , compare circuits  286   a  and  286   b , and programmable memory device  288 . NAND gate  284  has inputs coupled to outputs of compare circuits  286   a  and  286   b , and an output coupled to read-enable inputs of FIFOs  274   a  and  274   b . The outputs of compare circuits  286   a  and  286   b  are also coupled to respective write-enable inputs of FIFOs  274   a  and  274   b . Inputs of compare circuit  286   a  are coupled to a programmable memory device  288  and to the plurality of IO devices  272   a , while inputs of compare circuit  286   b  are coupled to a programmable memory device  288  and to the plurality of IO devices  272   b . Thus, data portions received by IO devices  272   a  are subsequently provided to both compare circuit  286   a  and FIFO  274   a , and data portions received by IO devices  272   b  are subsequently provided to compare circuit  286   b  and FIFO  274   b.    
   Circuits  250  and  252  perform the synchronizing function mentioned above in response to receiving a RESET instruction at the same point in time from a device external to circuits  250  and  252 . The RESET instruction is provided to control circuit  266  and to compare circuits  286   a  and  286   b . In response to the RESET instruction, control circuit  266  generates a control signal that instructs multiplexer  262  to couple the output of programmable memory  264  to IO devices  270   a  and IO devices  270   b . Programmable memory  264  includes a predefined code. The predefined code is concatenated with itself before being provided to multiplexer  262 . Thus, IO devices  270   a  and IO devices  270   b  each receive the predefined code stored in memory  264  in response to control circuit  266  receiving the RESET instruction. IO devices  270   a  and IO devices  270   b  each transmit the predefined code to data buses  254   a  and  254   b , respectively, upon a transition edge of a clock provided thereto. Before the next transition edge of the clock provided to IO devices  270   a  and IO devices  270   b , control circuit  266  generates a signal instructing multiplexer  262  to couple the output of FIFO  260  to IO devices  270   a  and IO devices  270   b . Thereafter, multiplexer  262  transmits data lines outputted from FIFO  260  in a line-by-line manner. The upper and lower portions of each data line are provided to IO devices  270   a  and IO devices  270   b , respectively. IO devices  270   a  and IO devices  270   b , respectively, transmit upper and lower portions of data lines to data buses  254   a  and  254   b , respectively, with each transition edge of the clock provided thereto. 
   Normally, compare circuits  286   a  and  286   b  assert respective write-enable signals that enable FIFOs  274   a  and  274   b , respectively, to receive and store data portions transmitted by data buses  254   a  and  245   b , respectively, and IO devices  272   a  and IO devices  272   b , respectively. NAND gate  284  asserts a read-enable signal in response to receiving the write-enable signals from compare circuits  286   a  and  286   b . The read-enable signal enables FIFOs  274   a  and  274   b  to output multibit data portions for concatenation and subsequent storage in FIFO  276 . If either of the compare circuits  286   a  and  286   b  assert a write disable signal, then NAND gate  284  asserts a read disable signal that disables FIFOs  274   a  and  274   b  from outputting data portions. 
   As noted, compare circuits  286   a  and  286   b  receive the RESET instruction at the same time control circuit  266  receives the RESET instruction. In response, compare circuits  286   a  and  286   b  assert respective write disable signals. The write disable signals disable FIFOs  274   a  and  274   b  from storing multibit data portions received from data buses  254   a  and  254   b , respectively, and IO devices  270   a  and IO devices  270   b , respectively. Because compare circuits  286   a  and  286   b  assert write disable signals, NAND gate  284  generates a read disable signal which disables read access to FIFOs  274   a  and  274   b . Thus, in response to receiving the RESET instruction, compare circuits  286   a  and  286   b  directly or indirectly disable read and write access to FIFOs  274   a  and  282   b.    
   Compare circuit  286   a  continues to assert its write disable signal until it detects a match between a data portion received from data bus  254   a  via IO devices  272   a  and a predefined code stored in programmable memory  288 . Likewise, compare circuit  286   b  continues to assert its write disable signal until it detects a match between a data portion received from data bus  254   b  via IO devices  272   b  and the predefined multibit code stored in programmable memory  288 . The predefined code stored in programmable memory  288  equals the predefined code stored in programmable memory  264 . 
   When compare circuit  286   a  detects a match between the predefined code in memory  288  and a data portion received from data bus  254   a  via IO devices  272   a , compare circuit  286   a  continuously asserts a write-enable signal that enables FIFO  274   a  to receive and store the data portions received from data bus  254   a  that follow the data portion that matches the predefined code in memory  288 . In an alternative embodiment, FIFO  274   a  may receive and store the data portion that matches the predefined code in memory  288  in addition to the data portions that follow. Similarly, when compare circuit  286   b  detects a match between the predefined code in memory  288  and a data portion received from data bus  254   b  via IO devices  272   b , compare circuit  286   b  continuously asserts a write-enable signal that enables FIFO  274   b  to receive and store the data portions received from data bus  254   b  that follow the data portion that matches the predefined code in memory  288 . In another alternative embodiment, FIFO  274   b  may receive and store the data portion that matches the predefined code in memory  288  in addition to the data portions that follow. When both the write-enable signals are asserted by compare circuits  286   a , NAND gate  284  generates a read-enable signal. FIFOs  274   a  and  274   b , in response to receiving the read-enable signal, begin outputting multibit data portions in parallel with each edge transition of the read clock provided thereto. The multibit data portions outputted by FIFOs  274   a  and  274   b  are concatenated and subsequently stored in FIFO  276 . 
     FIG. 6  through  FIG. 9  illustrate the effects of synchronizing data transmission between circuits  250  and  252  via data buses  254   a  and  254   b . The synchronization process begins when control circuit  266  and compare circuits  286   a  and  286   b  receive the RESET instruction.  FIG. 6  shows the contents of FIFOs  266 ,  274   a ,  274   b , and  276  when RESET instruction is received. 
   Compare circuits  286   a  and  286   b  along with NAND gate  284  assert signals that disable write and read access to FIFOs  274   a  and  274   b  in response to compare circuits  286   a  and  286   b  receiving the RESET instruction. IO devices  270   a  and  270   b  transmit the predefined code stored in memory  264  in response to control circuit  266  receiving the RESET instruction. For purposes of explanation, it will be presumed that the predefined code transmitted via data bus  254   a  arrives at inputs to compare circuit  286   a  and FIFO  274   a  before the predefined code transmitted via data bus  254   b  arrives at inputs to compare circuit  286   b  and FIFO  274   b . This presumption extends to corresponding upper and lower portions of data lines transmitted via data buses  254   a  and  254   b.    
   At some time after the compare circuits  286   a  and  286   b  receive the RESET instruction, compare circuit  286   a  detects a match between the predefined code in memory  288  and the predefined code transmitted by IO devices  270   a  via data bus  254   a . In response, compare circuit  286   a  continuously asserts a write-enable signal. FIFO  274   a , in response to receiving the write-enable signal from compare circuit  286   a , stores all data portions provided thereto that follow the predefined code.  FIG. 7  shows the contents of FIFOs  266 ,  274   a ,  274   b  and  276  just after the first data portion is stored in FIFO  274   a . Due to the relative delay in transmission of corresponding upper and lower portions of data lines, FIFO  274   a  will begin to store upper portions of data lines before FIFO  274   b  stores lower portions of data lines. 
   Eventually, compare circuit  286   b  detects a match between the predefined code in memory  288  and the predefined code transmitted by IO devices  270   b  via data bus  254   b . In response, compare circuit  286   b  continuously asserts a write-enable signal. FIFO  274   a , in response to receiving the write-enable signal from compare circuit  286   b , stores all data portions provided thereto that follow the predefined code.  FIG. 8  shows the contents of FIFOs  266 ,  274   a ,  274   b  and  276  just after the first data portion is stored in FIFO  274   a . It can be seen that FIFO  274   a  stores two data portions, while FIFO  274   b  stores only one data portion. As can be expected, the first portions read from FIFOs  274   a  and  274   b  will be corresponding upper and lower portions of a data line. 
   The compare circuits  286   a  and  286   b  continuously assert the write-enable signals, as noted above. With both write-enable signals asserted by compare circuits  286   a  and  286   b , NAND gate  284  asserts a read-enable signal. In response, FIFOs  274   a  and  274   b  output respective data portions on each transition edge of a read clock provided thereto for concatenation and subsequent storage in FIFO  276 .  FIG. 9  shows the contents of FIFOs  266 ,  274   a ,  274   b  and  276  after the read-enable signal is asserted. As can be seen in  FIG. 9 , the first data line stored in FIFO  276  represents a concatenation of the first data lines. 
   Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the spirit and scope of the invention as defined by the appended claims.