Abstract:
A structure and method for measuring leakage current. The structure includes: a body formed in a semiconductor substrate; a dielectric layer on a top surface of the silicon body; and a conductive layer on a top surface of the dielectric layer, a first region of the dielectric layer having a first thickness and a second region of the dielectric layer between the conductive layer and the top surface of the body having a second thickness, the second thickness different from the first thickness. The method includes, providing two of the above structures having different areas of first and the same area of second or having different areas of second and the same area of first dielectric regions, measuring a current between the conductive layer and the body for each structure and calculating a gate tunneling leakage current based on the current measurements and dielectric layer areas of the two devices.

Description:
FIELD OF THE INVENTION 
   The present invention relates to the field of semiconductor transistors; more specifically, it relates to a silicon-on-insulator field effect transistor and a structure and method for measuring gate-tunnel leakage parameters of field effect transistors. 
   BACKGROUND OF THE INVENTION 
   Silicon-on-insulator (SOI) technology employs a layer of mono-crystalline silicon overlaying an insulation layer on a supporting bulk silicon wafer. Field effect transistors (FETs) are fabricated in the silicon layer. SOI technology makes possible certain performance advantages, such as a reduction in parasitic junction capacitance, useful in the semiconductor industry. 
   To accurately model SOI FET behavior, gate tunneling current from the gate to the body of the FET in the channel region must be accurately determined. This current is difficult to measure because construction of body-contacted SOI FETs utilize relatively large areas of non-channel region dielectric which adds parasitic leakage current from the gate to non-channel regions of the FET. The parasitic leakage current can exceed the channel region leakage current, making accurate modeling impossible. 
   Therefore, there is a need for a silicon-on-insulator field effect transistor with reduced non-channel gate to body leakage and a structure and method for measuring tunnel leakage current of a silicon-on-insulator field effect transistors. 
   SUMMARY OF THE INVENTION 
   The present invention utilizes SOI FETs having both thin and thick dielectric regions under the same gate electrode, the thick dielectric layer disposed adjacent to under the gate electrode over the SOI FET body contact, as tunneling leakage current measurement devices. The thick dielectric layer minimizes parasitic tunneling leakage currents that otherwise interfere with thin dielectric tunneling current measurements from the gate electrode in the channel region of the SOI FET. 
   A first aspect of the present invention is a structure comprising: a silicon body formed in a semiconductor substrate; a dielectric layer on a top surface of the silicon body; and a conductive layer on a top surface of the dielectric layer, a first region of the dielectric layer between the conductive layer and the top surface of the silicon body having a first thickness and a second region of the dielectric layer between the conductive layer and the top surface of the silicon body having a second thickness, the second thickness different from the first thickness. 
   A second aspect of the present invention is a method of measuring leakage current, comprising: providing a first and a second device, each device comprising: a silicon body formed in a semiconductor substrate; a dielectric layer on a top surface of the silicon body, a first region of the dielectric layer having a first thickness and a second region of the dielectric layer having a second thickness, the first thickness less than the second thickness; a conductive layer on a top surface of the dielectric layer; a dielectric isolation extending from a top surface of the semiconductor substrate into the semiconductor substrate on all sides of the silicon body; a buried dielectric layer in the semiconductor substrate under the silicon body, the dielectric isolation contacting the buried dielectric layer; a first region of the conductive layer extending in a first direction and a second region of the conductive layer extending in a second direction, the second direction perpendicular to the first direction; and the first region of the conductive layer disposed over the first region of the dielectric layer and an adjacent first portion of the second region of the dielectric layer, the second region of the conductive layer disposed over a second portion of the second region of the dielectric layer, the second portion of the second region of the dielectric layer adjacent to the first portion of the second region of the dielectric layer; and performing measurements of current flow between the conductive layer and the silicon body for each of the first and second devices. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
       FIG. 1A  is a top view of an SOI FET according to first and second embodiments of the present invention; 
       FIG. 1B  is a cross-section through line  1 B— 1 B of  FIG. 1A ; 
       FIG. 1C  is a cross-section through line  1 C— 1 C of  FIG. 1A ; 
       FIG. 1D  is a cross-section through line  1 D— 1 D of  FIG. 1A ; 
       FIG. 2  is a top view of an exemplary tunneling gate current measure structure according to the first embodiment of the present invention; 
       FIG. 3  is a top view of an exemplary tunneling gate current measure structure according to a second embodiment of the present invention; 
       FIG. 4A  is a top view of an SOI FET according to third and fourth embodiments of the present invention; 
       FIG. 4B  is a cross-section through line  4 B— 4 B of  FIG. 4A ; 
       FIG. 5  is a top view of an exemplary tunneling gate current measure structure according to the third embodiment of the present invention; and 
       FIG. 6  is a top view of an exemplary tunneling gate current measure structure according to the fourth embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1A  is a top view of an SOI FET according to first and second embodiments of the present invention. In  FIG. 1A , an FET  100  includes a silicon body  105 , a “T” shaped conductive layer  110  having a first region  115  and a integral second region  120  perpendicular to first region  115 , and a dielectric layer (e.g. a gate dielectric layer), a thin dielectric region  125  (e.g. a thin gate dielectric region) and a thick dielectric region  130  (e.g. a thick gate dielectric region). Thick dielectric region  130  is shown by the dashed lines. Thin and thick dielectric regions  125  and  130  may formed from a single integral dielectric layer, from two separate but abutting dielectric layers or thick region  130  may include a second dielectric layer over an underlying first dielectric layer while thin region  125  just includes the second dielectric layer. First and second source/drains  135  and  140  are formed in body  105  on opposite sides of first region  115  of conductive layer  110 . A body contact region  145  is formed in body  105  adjacent to a side  150  of second region  120  of gate  110  away from first region  115  of gate  110 . Body  105  is surrounded by trench isolation (TI)  155 . A first stud contact  160  contacts gate  110  and a second stud contact  165  contacts body contact region  145  of body  105 . 
   For an N-channel FET (NFET) device body  105  is doped P− except for first and second source/drain regions  135  and  140  which are doped N+ and body contact region  145  which is doped P+. For a P-channel FET (PFET) device body  105  is doped N− except for first and second source/drain regions  135  and  140  which are doped P+ and body contact region  145  which is doped N+. 
   First region  115  of conductive layer  110  has a width W and a length L. Thick dielectric region  130  extends from second region  120  of conductive layer  110  a distance D (e.g. has a width D) under first region  115  of conductive layer  110 . 
     FIG. 1B  is a cross-section through line  1 B— 1 B of  FIG. 1A . In  FIG. 1B , trench isolation  155  physically contacts a buried oxide layer (BOX)  170 . BOX  170  in turn physically contacts a silicon substrate  175 . Thus body  105  is electrically isolated from silicon substrate  175  or any adjacent devices. In  FIG. 1B , an interlevel dielectric layer  180  is formed over conductive layer  110  and stud first and second contacts  160  and  165  extend through interlevel dielectric layer  180 . An optional metal silicide contact  185  is formed between first stud contact  160  and conductive layer  110  and an optional metal silicide contact  190  is formed between second stud contact and body contact region  145 . Examples of metal silicides include titanium silicide, tantalum silicide, tungsten silicide, platinum silicide and cobalt silicide. 
   Thin dielectric region  125  has a thickness T 1  and thick dielectric region  130  has a thickness T 2 . In one example T 1  is between about 0.8 nm and about 1.5 nm. In one example T 2  is between about 2 nm and about 3 nm. Thin dielectric region  125  may comprise silicon dioxide, silicon nitride, a high K material, metal oxides, Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , metal silicates, HfSi x O y , HfSi x O y N z  and combinations thereof. Thick dielectric region  130  may also comprise silicon dioxide, silicon nitride, a high K material, metal oxides, Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , metal silicates, HfSi x O y , HfSi x O y N z  and combinations thereof. Thick and thin dielectric regions  125  and  130  may comprise the same or different materials. A high K dielectric material has a relative permittivity above 10. 
   There are three tunneling current leakage paths from conductive layer  110  into body  105 . The first leakage path (for tunneling leakage current I 1 ) is from first region  115  of conductive layer  110 , through thin dielectric region  125  to body  105 . The second leakage path (for tunneling leakage current I 2 ) is from first region  115  of conductive layer  110 , through thick dielectric region  130  to body  105 . The third leakage path (for tunneling leakage current I 3 ) is from second region  120  of conductive layer  110 , through thick dielectric region  130  to body  105  and body contact region  145 . 
     FIG. 5C  is a cross-section through line  1 C— 1 C of  FIG. 1A . In  FIG. 5C , first and second source/drains  135  and  140  are aligned to opposite sidewalls  195  and  200  respectively of first region  115  of conductive layer  110 . For clarity, no spacers are illustrated in  FIG. 5C  (or  FIGS. 1A ,  1 B or  1 D), however, the invention is applicable to devices fabricated with spacers. Spacers are thin layers formed on the sidewalls of gate electrodes and source/drains are aligned to the exposed sidewall of the spacer rather than the sidewall of the gate electrode as is well known in the art. 
     FIG. 5D  is a cross-section through line  1 D— 1 D of  FIG. 1A . In  FIG. 5D , it should be noted that thick dielectric region  130  does not extend under all of second region  120  of conductive layer  110 . 
   Returning to  FIGS. 1A and 1B , gate tunneling leakage current density J is a function of the dielectric layer material, the dielectric layer material and the voltage across the dielectric layer (for an FET this is VT). In the following discussion reference to both  FIGS. 1A and 1B  will be helpful. The total gate to body tunneling leakage current I GB  (hereafter gate tunneling leakage) of FET  100  is equal to I 1 +I 2 +I 3  as shown in  FIG. 1B . The tunneling leakage current density of thin dielectric region  125  is, J 1  and of thick dielectric region  130  is J 2 . In general, gate tunneling leakage current I is equal to J times the area of the dielectric in a particular region. Therefore, gate tunneling leakage current I 1  is equal to J 1 ·L(W−D). Gate tunneling leakage  12  is equal toJ 2  ·L·D. Gate tunneling leakage  13  is equal to J 2 ·A·B. (A is shown in  FIG. 1A .) The total gate tunneling leakage of SOI FET  100  is given by:
 
 I   GB   =L   1   ·L ( W−D )+ J   2   ·L·D+J   2   ·A·B   (1)
 
   When used as a measurement structure, SOI FET  100  is designed so that 13 remains constant, and the relations L−(W−D)&gt;L·D and T 2 &gt;T 1  are chosen to make I 1 &gt;I 2 . 
     FIG. 2  is a top view of an exemplary tunneling gate current measure structure according to the first embodiment of the present invention. In  FIG. 2 , a test structure  210  includes a first SOI FET  215  and a second SOI FET  220 . First SOI FET  215  is similar to SOI FET  100  of  FIG. 1A , except first region  115  of conductive layer  110  has a width WA as opposed to a width W in  FIG. 1A . Second SOI FET  220  is similar to first SOI FET  215  except first region  115  of conductive layer  110  has a width WB as opposed to a width WA. In the first embodiment of the present invention WA can not be equal to WB, the goal being having two otherwise identical SOI FETs with different thin dielectric areas. 
   The total gate tunneling leakage current of SOI FET  215  (assuming the current through second region  120  of conductive layer  110  is negligible as discussed supra in reference to  FIGS. 1A and 1B ) can be expressed as I GBA =I 1A +I 2A +I 3A  where I 1A =J 1 ·L(WA−D), I 2A =J 2 ·L·D and I 3A =J 2 ·A·B to give:
 
 I   GBA   =J   1   ·L ( WA−D )+ J   2   ·L·D+J   2 ·A·B  (2)
 
   and the total gate tunneling leakage current of SOI FET  220  can be expressed as I GBB =I 1B +I 2B +I 3B  where I 1B =J 1 ·L(WB−D), I 2A =J 2 ·L·D, and I 3A =J 2 ·A·B to give:
 
 I   GBB   =J   1   ·L ( WB−D )+J 2   ·L·D+J   2 ·A·B  (3)
         and subtracting I GBA  from I GBB  and rearranging gives:
 
 I   GBA   −I   GBB =J 1   ·L ( WA−WB ).  (4)
       

   Since both I GBA  and I GBB  may be measured by applying a voltage across and then measuring a current flowing through stud contacts  160  and  165  and with WA, WB, A and B as known values (design value plus fabrication bias) J 1  can be solved for. With J 1  known, I 1  for any SOI FET having a same thin dielectric layer as thin dielectric region  125  can be calculated. J 2  and I 2  may then be calculated as well. I GBA  and I GBB  are measured at the same voltage. In one example, I GBA  and I GBB  are measured at the threshold voltage (VT) of a conventional (single thickness gate dielectric) SOI FET. 
     FIG. 3  is a top view of an exemplary tunneling gate current measure structure according to a second embodiment of the present invention. In  FIG. 3 , a test structure  225  includes a first SOI FET  230  and a second SOI FET  235 . First SOI FET  230  is similar to SOI FET  100  of  FIG. 1A , except thick dielectric region  130  extends from second region  120  of conductive layer  110  a distance DA under first region  115  of conductive layer  110  (e.g. a region of thick dielectric region  130  under second region  120  of conductive layer  110  has a width DA) as opposed to a distance D in  FIG. 1A . Second SOI FET  235  is similar to first SOI FET  230  except thick dielectric region  130  extends from second region  120  of conductive layer  110  a distance DB (e.g. a region of thick dielectric region  130  under second region  120  of conductive layer  110  has a width DA) under first region  115  of conductive layer  110  as opposed to distance DA. In the second embodiment of the present invention DA can not be equal to DB, the goal being having two otherwise identical SOI FETs with different thin dielectric areas. 
   The total gate tunneling leakage current of SOI FET  230  can be expressed as I GBA =I 1A +I 2A +I 3A I 1A =J 1 ·L(W−DA), I 2A =J 2 ·L·Dl , and I 3A =J 2 ·A·B to give:
 
I GBA   =J   1   ·L ( W−DA )+ J   2   ·L·DA+J   2   ·A·B   (5)
         and the total gate tunneling leakage current of SOI FET  235  can be expressed as I GBB =I 1B −I 1B  where I 1B =J 1 ·L(W−DB), I 1B =J 2 ·L·DB, and I 1A =J 2 ·A·B, to give:
 
 I   GBB   =J   1   −L ( W−DB )+ J   2   ·L·DB+J   2   ·A·B.   (6)
       

   Since both I GBA  and I GBB  may be measured by applying a voltage across and then measuring a current flowing through stud contacts  160  and  165  and with L, W, DA, and DB, A, B as known values (design value plus fabrication bias) and equations (5) and (6) provide two equations with two unknowns, J 1  and J 2  can be solved for. With, J 1  and J 2  known, I 1  and I 2  for any SOI FET having a same thin dielectric layer as thin dielectric region  125  can be calculated. 
     FIG. 4A  is a top view of an SOI FET according to third and fourth embodiments of the present invention. In  FIG. 4A , an SOI FET  240  is similar to SOI FET of  FIG. 1A  with the following exceptions: 
   SOI FET  240  is essentially symmetrical about a central axis  245  passing through and perpendicular to both body  105  and a conductive layer  110 A is “H” shaped. First region  115  of conductive layer  110 A is positioned between integral second and third regions  120  that perpendicular to first region  115 . Thin dielectric region  125  is positioned between first and second thick dielectric layers  130  (defined by the dashed lines). First and second body contact regions  145  are formed in body  105  adjacent to a sides  150  of first and second regions  120  of gate  110 A. A first stud contact  160  contacts gate  110  and a first and second stud contacts  165  contact body contact regions  145 . First region  115  of conductive layer  110 A has a width W and a length L. Thick dielectric region  130  extends from first and second regions  120  of conductive layer  110 A distances D under first region  115  of conductive layer  110 A. 
   When used a s measurement structure, SOI FET  240  is designed so that 13 remains constant, and L-(W−D)&gt;L·D and T 2 &gt;T 1  making I 1 &gt;I 2 . 
     FIG. 4B  is a cross-section through line  4 B— 4 B of  FIG. 4A . In  FIG. 4B , there are five tunneling current leakage paths from conductive layer  110 A into body  105 . The first leakage path (for tunneling leakage current I 1 ) is from first region  115  of conductive layer  110 , through thin dielectric region  125  to body  105 . The second and third leakage paths (for tunneling leakage currents  12 ) are from first region  115  of conductive layer  110 , through first and second thick dielectric layers  130  to body  105 . The fourth and fifth leakage path (for tunneling leakage currents  13 ) are from second and third regions  120  of conductive layer  110 , through respective first and second thick dielectric layers  130  to body  105  and respective body contact regions  145 . 
     FIG. 5  is a top view of an exemplary tunneling gate current measure structure according to the third embodiment of the present invention. In  FIG. 5 , a test structure  250  includes a first SOI FET  255  and a second SOI FET  260 . First SOI FET  250  is similar to SOI FET  240  of  FIG. 4A , except first region  115  of conductive layer  110  has a width WA as opposed to a width W in  FIG. 4A . Second SOI FET  260  is similar to first SOI FET  255  except first region  115  of conductive layer  110 A has a width WB as opposed to a width WA. In the third embodiment of the present invention WA can not be equal to WB, the goal being having two otherwise identical SOI FETs with different thin dielectric areas. 
   Equation (1) I GBA −I GBB   =J   1 L(WA−WB) derived for the first embodiment of the present invention is applicable to the third embodiment of the present invention. The third embodiment of the present invention eliminates errors in gate tunneling leakage induced at the edge of body  105  under gate  110  of  FIG. 2  by eliminating that edge. 
   Again both I GBA  and I GBB  are measured by applying a voltage across and then measuring a current flowing through stud contacts  160  and  165  and in one example, I GBA  and I GBB  are measured at the threshold voltage (VT) of a conventional (single thickness gate dielectric) SOI FET. 
     FIG. 6  is a top view of an exemplary tunneling gate current measure structure according to the fourth embodiment of the present invention. In  FIG. 6 , a test structure  265  includes a first SOI FET  270  and a second SOI FET  275 . First SOI FET  270  is similar to SOI FET  240  of  FIG. 4A , except thick dielectric layers  130  extend from second and third regions  120  of conductive layer  110 A distances DA under either side of first region  115  of conductive layer  110 A as opposed to a distance D in  FIG. 4A . Second SOI FET  275  is similar to first SOI FET  270  except thick dielectric region  130  extends from second and third regions  120  of conductive layer  110 A distances DB under either side of first  115  of conductive layer  110 A as opposed to distance DA. In the fourth embodiment of the present invention DA can not be equal to DB, the goal being having two otherwise identical SOI FETs with different thin dielectric areas. 
   The following two equations in two unknowns, J 1  and J 2  may be derived in a similar manner to equations (5) and (6) supra:
 
 I   GBA   =J   1   ·L ( W−DA )+2 ·J   2   ·L·DA+ 2 ·J   2   ·A·B   (7)
 
 I   GBA   =J   1   ·L ( W−DB )+2 ·J   2   ·L·DB+ 2 ·J   2   ·A·B.   (8)
 
   Again both I GBA  and I GBB  are measured by applying a voltage across and then measuring a current flowing through stud contacts  160  and  165  and in one example, I GBA  and I GBB  are measured at the threshold voltage (VT) of a conventional (single thickness gate dielectric) SOI FET. 
   The fourth embodiment of the present invention eliminates errors in gate tunneling leakage induced at the edge of body  105  under gate  110  of  FIG. 3  by eliminating that edge. 
   Thus, the present invention provides a silicon-on-insulator field effect transistor with reduced non-channel gate to body leakage and a structure and method for measuring tunnel leakage current of silicon-on-insulator field effect transistors. 
   The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.