Abstract:
A doped polysilicon structure may be formed without the need to etch doped polysilicon. The patterned polysilicon may be covered, an opening may be formed in the polysilicon covering, and then the polysilicon may be doped through the opening. As a result, awkward etching of doped polysilicon may be avoided in some cases.

Description:
BACKGROUND  
         [0001]    This invention relates generally to the formation of polysilicon structures including the formation of polysilicon gate electrodes.  
           [0002]    Conventionally, polysilicon gate electrodes are formed by depositing polysilicon over a substrate that may be covered with a suitable gate dielectric. The polysilicon material is then doped, for example, using an ion implantation process.  
           [0003]    It is then necessary to define the polysilicon electrodes from the doped polysilicon layer using etching techniques. However, etching doped polysilicon presents significant challenges. These challenges include known profile and differential etch bias issues.  
           [0004]    Thus, there is a need to find a way to form polysilicon structures, such as gate electrodes, without necessitating the etching of heavily doped polysilicon material. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    [0005]FIG. 1 is an enlarged cross-sectional view of an embodiment of the present invention at an early stage of manufacture;  
         [0006]    [0006]FIG. 2 is an enlarged cross-sectional view corresponding to FIG. 1 at a subsequent stage in accordance with one embodiment of the present invention;  
         [0007]    [0007]FIG. 3 is an enlarged cross-sectional view corresponding to FIG. 2 at a subsequent stage in accordance with one embodiment of the present invention;  
         [0008]    [0008]FIG. 4 is an enlarged cross-sectional view at a subsequent stage in accordance with one embodiment of the present invention; and  
         [0009]    [0009]FIG. 5 is an enlarged cross-sectional view at a subsequent stage in accordance with one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0010]    Referring to FIG. 1, a semiconductor substrate may have a polysilicon material formed over a suitable gate dielectric. The substrate may, for example, be a silicon substrate and the gate dielectric may be an oxide, for example. The polysilicon material may then be patterned to form the polysilicon gate material  14  over a gate dielectric  12 , all positioned over a substrate  10 , as shown in FIG. 1. Because the polysilicon material is undoped or substantially undoped when etched, it may be more easily etched and patterned to define the shape shown in FIG. 1.  
         [0011]    By “substantially undoped,” it is intended to refer to a polysilicon material that either has no doping or doping at levels substantially lower than the doping levels utilized to form doped polysilicon gate electrodes that are either n-type or p-type. Generally, these gate electrodes are considered heavily doped and have doping concentrations of greater than 1E18 atoms per cm 3 .  
         [0012]    The gate material  14  may be covered by a relatively thinner layer  16  and a relatively thicker layer  18 . In one embodiment the layer  16  may be an insulator such as silicon dioxide. The layer  18  may, for example, be an insulator such as silicon nitride or a combination of layers of silicon nitride and silicon dioxide, as two examples.  
         [0013]    The structure shown in FIG. 2 may be subjected to a conventional planarization step such as a chemical mechanical planarization (CMP) operation. The planarization may utilize the thinner layer  16  as a planarization stop in one embodiment. Thus, as shown in FIG. 2, the upper portion of the thicker layer  18  may be removed down to the height of the uppermost portion of the thinner layer  16 .  
         [0014]    The exposed portion of the thinner layer  16  may then be removed using any suitable technique. One suitable technique is a wet etch using hydrofluoric or H 3 PO 4  etchant, for example. The resulting structure, shown in FIG. 3, has the upper portion of the thinner layer  16  removed and possibly a little bit of the gate material  14 . In case some of the gate material  14  is removed, the initial structure of the gate electrode  14  may be slightly higher than is needed to account for the ensuing loss of material.  
         [0015]    In an embodiment in which polysilicon gate electrodes for complementary metal oxide semiconductor (CMOS) technologies are involved, a photodefinition process may be used to define n-type and p-type areas. The n-type areas may include n-type doped polysilicon gate electrodes and the p-type areas may include p-type doped polysilicon gate electrodes.  
         [0016]    An ion implantation or other doping process may be utilized to appropriately dope the polysilicon material  14 . For example, when the n-type areas are doped, a suitable dopant may be utilized to dope the gate material  14  in the p-type doped areas with the n-type areas covered and with the p-type areas covered, a suitable dopant may be utilized to dope the n-type areas. It may be appreciated that since the doping is done after the definition of the gate material  14 , the need to etch heavily doped polysilicon may be largely, if not completely, avoided.  
         [0017]    Referring to FIG. 4, a suitable etching process may be utilized to remove the thicker layer  18 . For example, a wet etch may be utilized in one embodiment.  
         [0018]    Referring to FIG. 5, the horizontal portion of the thinner insulator  16  may then be removed using an anisotropic etch process, such as a dry etch in one embodiment. As a result, a portion of the thinner layer  16  may remain and this may function as a sidewall spacer in some embodiments.  
         [0019]    Alternatively, the thinner layer  16  may be completely removed, for example, using an isotropic etch such as an isotropic wet etch.  
         [0020]    In some embodiments, polysilicon material may be defined and patterned without the need to etch heavily doped polysilicon. As a result, the quality and feasibility of the etching process may be improved in some situations.  
         [0021]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.