Abstract:
A telecommunications node architecture is disclosed that comprises multiple switching units that are connected to transceiver banks in a novel topology to enhance the reliability of the telecommunications network. Furthermore, the architecture of the illustrative embodiment facilitates redundancy in a high-bandwidth add/drop multiplexor environment.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to telecommunications in general, and, more particularly, to an architecture for a composite add/drop multiplexor, which is commonly used in high-speed backbone networks (e.g., SONET/SDH networks, etc.).  
         BACKGROUND OF THE INVENTION  
         [0002]    The first generation of optical fiber systems in the public telephone network used proprietary architectures, equipment line codes, multiplexing formats, and maintenance procedures. This diversity complicated the task of the regional Bell operating companies (“RBOCs”)and the interexchange carriers (e.g., AT&amp;T, Spring, MCI, etc.) who needed to interface their equipment with these diverse systems.  
           [0003]    To ease this task, Bellcore initiated an effort to establish a standard for connecting one optical fiber system to another. That standard is officially named the Synchronous Optical Network, but it is more commonly called “SONET.” The international version of the domestic SONET standard is officially named the Synchronous Digital Hierarchy, but it is more commonly called “SDH.” 
           [0004]    Although differences exist between SONET and SDH, those differences are mostly in terminology. In most respects, the two standards are the same and, therefore, virtually all equipment that complies with either the SONET standard or the SDH standard also complies with the other. Therefore, for the purposes of this specification, the SONET standard and the SDH standard shall be considered interchangeable and the acronym/initialism “SONET/SDH” shall be defined as either the Synchronous Optical Network standard or the Synchronous Digital Hierarchy standard, or both.  
         SUMMARY OF THE INVENTION  
         [0005]    The present invention is a telecommunications node architecture that avoids some of the costs and disadvantages associated with node architectures in the prior art. For example, the illustrative embodiment comprises redundant add/drop multiplexors that are connected to transceiver banks in a novel topology to enhance the reliability of the node.  
           [0006]    The illustrative embodiment comprises:  
           [0007]    (1) a first line transceiver bank;  
           [0008]    (2) a second line transceiver bank;  
           [0009]    (3) a first switching unit comprising:  
           [0010]    (a) a first input for receiving a first line signal from the first line transceiver bank,  
           [0011]    (b) a first output for transmitting a second line signal to the second line transceiver bank,  
           [0012]    (c) a second input for receiving a third line signal from the second line transceiver bank, and  
           [0013]    (d) a second output for transmitting a fourth line signal to the first line transceiver bank; and  
           [0014]    (4) a second switching unit comprising:  
           [0015]    (a) a first input for receiving the first line signal from the first line transceiver bank,  
           [0016]    (b) a first output for transmitting a fifth line signal to the second line transceiver bank,  
           [0017]    (c) a second input for receiving the third line signal from the second line transceiver bank, and  
           [0018]    (d) a second output for transmitting a sixth line signal to the first line transceiver bank. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]    [0019]FIG. 1 depicts a block diagram of the illustrative embodiment of the present invention.  
         [0020]    [0020]FIG. 2 depicts a block diagram of node  101 - i,  as shown in FIG. 1.  
         [0021]    [0021]FIG. 3 depicts a block diagram of switch complex  201 , as shown in FIG. 2.  
         [0022]    [0022]FIG. 4 depicts a block diagram of switching unit  301 - b,  as shown in FIG. 3.  
         [0023]    [0023]FIG. 5 depicts a block diagram of add/drop multiplexor  401 , as shown in FIG. 4.  
         [0024]    [0024]FIG. 6 depicts a block diagram of line transceiver bank  302 - 1 , as shown in FIG. 3.  
         [0025]    [0025]FIG. 7 depicts a block diagram of line transceiver bank  302 - 2 , as shown in FIG. 3.  
         [0026]    [0026]FIG. 8 depicts a block diagram of line transceiver bank  402 - 1 , as shown in FIG. 4.  
         [0027]    [0027]FIG. 9 depicts a block diagram of line transceiver bank  402 - 2 , as shown in FIG. 4.  
         [0028]    [0028]FIG. 10 depicts a block diagram of tributary transceiver bank  303 , as shown in FIG. 3.  
         [0029]    [0029]FIG. 11 depicts a block diagram of tributary transceiver bank  403 , as shown in FIG. 4.  
         [0030]    [0030]FIG. 12 depicts a block diagram the first illustrative embodiment of loop-back transceiver  601 - q,  as shown in FIG. 6.  
         [0031]    [0031]FIG. 13 depicts a block diagram the second illustrative embodiment of loop-back transceiver  601 - q,  as shown in FIG. 6.  
         [0032]    [0032]FIG. 14 depicts a block diagram the third illustrative embodiment of loop-back transceiver  601 - q,  as shown in FIG. 6.  
         [0033]    [0033]FIG. 15 depicts an alternative representation of switching unit  301 - b,  as shown in FIG. 3.  
         [0034]    [0034]FIG. 16 depicts an alternative representation of switch complex  201 , as shown in FIG. 2.  
     
    
     DETAILED DESCRIPTION  
       [0035]    [0035]FIG. 1 depicts a block diagram of the illustrative embodiment of the present invention, telecommunications network  100 , which is a SONET/SDH ring network operating as a bi-directional line switched ring (“BLSR”). In accordance with the illustrative embodiment, telecommunications network  100  comprises four nodes, nodes  101 - 1  through  101 - 4 , that are interconnected by two sets of optical fibers, each of which carries a SONET/SDH OC-768 signal. Therefore, each node comprises two OC-768 line inputs and two OC-768 line outputs.  
         [0036]    Although the illustrative embodiment uses the SONET/SDH protocol, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention that use other protocols, such as dense wavelength division multiplexing (“DWDM”). Although the illustrative embodiment is a ring network, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention in which some or all of the nodes are interconnected in a mesh or non-ring topology. Although the illustrative embodiment operates as a bi-directional line switched ring, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention that operate in a different fashion (e.g., as a unidirectional path switched ring, as a four-fiber ring, etc.). Although the illustrative embodiment comprises four nodes, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention that comprise a different number of nodes. Although the illustrative embodiment carries OC-768 SONET/SDH frames, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention that carry other SONET/SDH rate frames.  
         [0037]    As shown in FIG. 1, node  101 - i,  for i=1 to 4, is capable of receiving sixteen (16) OC-192 tributaries on tributary bus  121 - i,  and of spawning sixteen (16) OC-192 tributaries on tributary bus  122 - i.  Although each node in the illustrative embodiment comprises the same number of tributaries, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention in which some or all of the nodes have a different number of tributaries. Although each tributary operates at an OC-192 data rate, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention in which some of the tributaries have a different data rate (e.g., OC-48, OC-12, OC-3, etc.). Although each node is capable of receiving sixteen (16) tributaries, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention in which some or all of the nodes are capable of receiving a different number of tributaries. Although each node is capable of spawning sixteen (16) tributaries, it will be clear to those skilled in the art, after reading this disclosure, how to make and use embodiments of the present invention in which some or all of the nodes are capable of spawning a different number of tributaries.  
         [0038]    In accordance with the illustrative embodiment of the present invention, node  101 - i  is capable of functioning as an add/drop multiplexor and  
         [0039]    i. a switch, or  
         [0040]    ii. a time-slot interchanger, or  
         [0041]    iii. both i and ii.  
         [0042]    In functioning as an add/drop multiplexor, node  101 - i  is capable of:  
         [0043]    i. adding an STS-1 from any tributary to one or more lines, or  
         [0044]    ii. dropping an STS-1 from a line to one or more tributaries, or  
         [0045]    iii. both i and ii.  
         [0046]    In functioning as a switch, node  101 - i  is capable of routing any STS-1 from any line or tributary to:  
         [0047]    i. one or more lines, or  
         [0048]    ii. one or more tributaries,  
         [0049]    iii. both i and ii.  
         [0050]    Because node  101 - i  is capable of receiving an STS-1 signal from one tributary and switching or copying it onto another tributary, and because this is an important aspect of the illustrative embodiment, it is given the name “hairpinning.” For the purposes of this specification, the term “hairpinning” is defined as the receipt by a node of a signal on one tributary and the outputting of the signal onto another tributary.  
         [0051]    In functioning as a time-slot interchanger, node  101 - i  is capable of moving or copying any STS-1 from any time slot in any line or tributary to one or more other time slots in the same line or tributary.  
         [0052]    [0052]FIG. 2 depicts a block diagram of the salient components of node  101 - i,  which comprises switch complex  201 , electro/optical converter  202 - j,  for j=1 and 2, and electro/optical converter  203 , interconnected as shown.  
         [0053]    Node  101 - i  receives:  
         [0054]    1. one (1) OC-768 SONET/SDH line signal from node  101 - j  via optical fiber  112 - j - i,    
         [0055]    2. one (1) OC-768 SONET/SDH line signal from node  101 - k  via optical fiber  111 - k - i , and  
         [0056]    3. sixteen (16) OC-192 SONET/SDH tributary signals via tributary bus  121 - i,  and  
         [0057]    transmits:  
         [0058]    1. one (1) OC-768 SONET/SDH signal to node  101 - j  via optical fiber  111 - i - j,    
         [0059]    2. one (1) OC-768 SONET/SDH signal to node  101 - k  via optical fiber  112 - i - k , and  
         [0060]    3. sixteen (16) OC-192 SONET/SDH tributary signals via tributary bus  122 - i;    
         [0061]    wherein k=4 and j=2 when i=1, k=1 and j=3 when i=2, k=2 and j=4 when i=3, and k=3 and j=1 when i=4.  
         [0062]    Optical/electrical boundary  251  delimits the two regions within node  101 - i  wherein the line and tributary signals are carried by different physical phenomenon. In particular, the line and tributary signals in optical region  253  are carried optically, in well-known fashion, and the line and tributary signals in electrical region  252  are carried electrically, also in well-known fashion. It will be clear to those skilled in the art, however, and after reading this disclosure, how to make and use embodiments of the present invention in which some or all of the tributaries are carried electrically or electromagnetically (e.g., via wireless, etc.).  
         [0063]    Electro/optical converter  202 - j  and  203  perform conversion between optical signals and electrical signals in well-known fashion. Electro/optical converter  202 - j  performs an optical-to-electrical conversion on line signals traveling from optical region  253  to electrical region  252  and an electrical-to-optical conversion on line signals traveling from electrical region  252  to optical region  253 . Electro/optical converter  203  performs an optical-to-electrical conversion on tributary signals traveling from optical region  253  to electrical region  252  and an electrical-to-optical conversion on tributary signals traveling from electrical region  252  to optical region  253 .  
         [0064]    Switch complex  201  receives:  
         [0065]    1. one (1) OC-768 SONET/SDH line signal from electro/optical converter  202 - 1  via bus  211 - 1 ,  
         [0066]    2. one (1) OC-768 SONET/SDH line signal from electro/optical converter  202 - 2  via bus  211 - 2 , and  
         [0067]    3. sixteen (16) OC-192 SONET/SDH tributary signals from electro/optical converter  203  via tributary bus  221 , and  
         [0068]    transmits:  
         [0069]    1. one (1) OC-768 SONET/SDH signal to electro/optical converter  202 - 1  via bus  212 - 1 ,  
         [0070]    2. one (1) OC-768 SONET/SDH signal to electro/optical converter  202 - 2  via bus  212 - 2 , and  
         [0071]    3. sixteen (16) OC-192 SONET/SDH tributary signals to electro/optical converter  203  via tributary bus  222 .  
         [0072]    When the number of bits per second to be processed by an add/drop multiplexor is low, it is feasible to fabricate the add/drop multiplexor on a single integrated circuit using state-of-the-art technology. In contrast, when the number of bits per second to be processed by a add/drop multiplexor is high, it is not feasible to fabricate the add/drop multiplexor on a single integrated circuit using state-of-the-art technology because the input/output bandwidth and number of devices on the integrated circuit are too limited.  
         [0073]    In accordance with the illustrative embodiment, switch complex  201  receives 40 gigabits per second on each of lines  211 - 1  and  211 - 2  and 160 gigabits per second on tributary bus  221  and, therefore, must process a total of 240 gigabits per second. This is too many bits per second to be processed by a single contemporary integrated circuit with the flexibility and reliability afforded by the illustrative embodiment. Therefore, the overall task of processing the 240 gigabits per second must be partitioned into a plurality of subtasks that are distributed among a plurality of integrated circuits.  
         [0074]    Partitioning the overall task of processing 240 gigabits per second into a plurality of subtasks suitable for distribution among a plurality of integrated circuits is not simple or obvious because the subtasks do not naturally lend themselves to the limitations in inherent in multiple integrated circuits that are not found in a single integrated circuit. In other words, a digital circuit design that is suitable for implementation on one integrated circuit might not, depending on the circumstances, be suitable for implementation on two integrated circuits.  
         [0075]    First, the bandwidth within one integrated circuit is far greater than the bandwidth between multiple integrated circuits. For example, a five-thousand lead bus is far more feasible within one integrated circuit than it is between two integrated circuits. In other words, by partitioning digital circuit into a plurality of integrated circuits, a bandwidth bottleneck is imposed between the various integrated circuits. In some applications, the bandwidth bottleneck is not a problem. In an add/drop multiplexor such as that disclosed herein, the bandwidth bottleneck is a problem and is exacerbated when the add/drop multiplexor is capable of hairpinning.  
         [0076]    Second, the timing within a single integrated circuit is far more synchronous than is the timing across a plurality of integrated circuits. In some low clock speed applications, the potential asynchrony is not a problem. In an add/drop multiplexor such as that disclosed herein that operates at gigahertz clock rates over inches or feet, the potential asynchrony might be catastrophic.  
         [0077]    Third, the design and manufacture of each fully-custom integrated circuit is expensive, and, therefore, the partitioning of the overall task needs to consider this fact.  
         [0078]    Fourth, some architectures will partition the overall task more reliably, more flexibly, and more-easily scalable than some other architectures and all of these issues must be considered.  
         [0079]    With these considerations in mind, the logic within switch complex  201  is partitioned into a plurality of integrated circuits and functional units as described below and with respect to FIGS. 3 through 16.  
         [0080]    [0080]FIG. 3 depicts a block diagram of the salient components of switch complex  201 , which comprises switching unit  301 - b , for b=1 and 2, line transceiver bank  302 - m,  for m=1 and 2, and tributary transceiver bank  303 , interconnected as shown.  
         [0081]    Switching unit  301 - b  receives:  
         [0082]    one (1) OC-768 SONET/SDH line signal from line transceiver bank  302 - 1  via bus  311 - 1 - b , which is a 3.125 GHz 16-bit bus,  
         [0083]    one (1) OC-768 SONET/SDH line signal from line transceiver bank  302 - 2  via bus  311 - 2 - b , which is a 3.125 GHz 16-bit bus, and  
         [0084]    sixteen (16) OC-192 SONET/SDH tributary signals from tributary transceiver bank  303  via bus  321 - b , which is a 3.125 GHz 32-bit bus, and  
         [0085]    transmits:  
         [0086]    one (1) OC-768 SONET/SDH line signal to line transceiver bank  302 - 1  via bus  312 - 1 - b , which is a 3.125 GHz 16-bit bus,  
         [0087]    one (1) OC-768 SONET/SDH line signal to line transceiver bank  302 - 2  via bus  312 - 2 - b , which is a 3.125 GHz 16-bit bus, and  
         [0088]    sixteen (16) OC-192 SONET/SDH tributary signals to tributary transceiver bank  303  via bus  322 - b , which is a 3.125 GHz 32-bit bus.  
         [0089]    Switching units  301 - 1  and  301 - 2  are redundant, which enables a hot-swappable, robust architecture in which both switching units are running—except when one has been removed for repair or upgrade—but the output of only one of the switching units is used by switch complex  201  at any given moment. For example, when the output of switching unit  301 - 1  is used by switch complex  201  and fails, then switch complex  201  uses the output of switching unit  301 - 2 . It is the task of line transceiver bank  302 - m  and tributary transceiver bank  303  to ensure that the signal path through node  101 - i  carries traffic through the active switching unit. It will be clear to those skilled in the art, after reading this disclosure, how to make and use equipment that can detect a failure, reassign active status to a new switching unit, and to subsequently reroute the signal path through the new active switching unit. Although switch complex  201  comprises two switching units, it will also be clear to those skilled in the art, after reading this disclosure, how to make and use systems having more than two switching units.  
         [0090]    Switching unit  301 - 1  and  301 - 2  are separate system components, such as separate circuit cards, for reasons related to fault tolerance and ease of maintenance that are well known to those skilled in the art. Line transceiver bank  302 - m  and tributary transceiver bank  303  are also separate system components. It will be clear to those skilled in the art that “separate system components” can refer to other configurations wherein switching unit  301 - b , line transceiver bank  302 - m , and tributary transceiver bank are all separated in some way (e.g., multiple integrated circuits, multiple cabinets, etc.).  
         [0091]    The design of switching unit  301 - b  is described below and with respect to FIGS. 4, 5,  15 , and  16 .  
         [0092]    The design of line transceiver bank  302 - 1  is described in detail below and with respect to FIGS. 6, 12 through  14 , and  16 .  
         [0093]    The design of line transceiver bank  302 - 2  is described in detail below and with respect to FIGS. 7, 12 through  14 , and  16 .  
         [0094]    The design of tributary transceiver bank  303  is described in detail below and with respect to FIGS. 10, 12 through  14 , and  16 .  
         [0095]    [0095]FIG. 4 depicts a block diagram of the salient components of switching unit  301 - b , which comprises add/drop multiplexor  401 , line transceiver bank  402 - n , for n=1 and 2, and tributary transceiver bank  403 , interconnected as shown.  
         [0096]    Add/drop multiplexor  401  receives:  
         [0097]    one (1) OC-768 SONET/SDH line signal from line transceiver bank  402 - 1  via bus  411 - 1 , which is a 1.25 GHz 32-bit bus,  
         [0098]    one (1) OC-768 SONET/SDH line signal from line transceiver bank  402 - 2  via bus  411 - 2 , which is a 1.25 GHz 32-bit bus, and  
         [0099]    sixteen (16) OC-192 SONET/SHD tributary signals from tributary transceiver bank  403  via bus  421 , which is a 1.25 GHz 128-bit bus, and  
         [0100]    transmits:  
         [0101]    one (1) OC-768 SONET/SDH line signal to line transceiver bank  402 - 1  via bus  412 - 1 , which is a 1.25 GHz 32-bit bus,  
         [0102]    one (1) OC-768 SONET/SDH line signal to line transceiver bank  402 - 2  via bus  412 - 2 , which is a 1.25 GHz 32-bit bus, and  
         [0103]    sixteen (16) OC-192 SONET/SDH tributary signals to tributary transceiver bank  403  via bus  422 , which is a 1.25 GHz 128-bit bus.  
         [0104]    Add/drop multiplexor  401  is capable of functioning as:  
         [0105]    i. an add/drop multiplexor, or  
         [0106]    ii. a switch, or  
         [0107]    iii. a time-slot interchanger, or  
         [0108]    iv. any combination of i, ii, and iii.  
         [0109]    Furthermore, add/drop multiplexor  401  is capable of:  
         [0110]    i. adding an STS-1 from any tributary to one or more lines, or  
         [0111]    ii. dropping an STS-1 from a line to one or more tributaries, or  
         [0112]    iii. both i and ii.  
         [0113]    And still furthermore, add/drop multiplexor  401  is capable of routing any STS-1 from any line or tributary to:  
         [0114]    i. one or more lines, or  
         [0115]    ii. one or more tributaries,  
         [0116]    iii. both i and ii.  
         [0117]    And yet furthermore, add/drop multiplexor  401  is capable of moving or copying any STS-1 from any time slot in any line or tributary to one or more other time slots in the same line or tributary.  
         [0118]    The design of add-drop multiplexor  401  is described in detail below and with respect to FIGS. 5, 15, and  16 .  
         [0119]    The design of line transceiver bank  402 - 1  is described in detail below and with respect to FIGS. 8 and 12 through  16 .  
         [0120]    The design of line transceiver bank  402 - 2  is described in detail below and with respect to FIGS. 9 and 12 through  16 .  
         [0121]    The design of tributary transceiver bank  303  is described in detail below and with respect to FIGS. 10, 12 through  15  and  16 .  
         [0122]    [0122]FIG. 5 depicts a block diagram of the salient components of add/drop multiplexor  401 , which comprises constituent add/drop multiplexor  501 - p , for p=1 and 2. In accordance with the illustrative embodiment, constituent add/drop multiplexor (‘CAD”)  501 - p  is an integrated circuit.  
         [0123]    Constituent add/drop multiplexor  501 - 1  receives:  
         [0124]    one (1) OC-768 SONET/SDH line signal from line transceiver bank  402 - 2  via bus  411 - 2 , which is a 1.25 GHz 32-bit bus,  
         [0125]    one (1) OC-768 SONET/SDH line signal from constituent add/drop multiplexor  501 - 2  via line  510 - 2 - 1 , which is a 1.25 GHz 32-bit bus, and  
         [0126]    eight (8) OC-192 SONET/SHD tributary signals from tributary transceiver bank  403  via one-half of bus  421  which is a 1.25 GHz 128-bit bus, and  
         [0127]    transmits:  
         [0128]    one (1) OC-768 SONET/SDH line signal to line transceiver bank  402 - 1  via bus  412 - 1 , which is a 1.25 GHz 32-bit bus,  
         [0129]    one (1) OC-768 SONET/SDH line signal to constituent add/drop multiplexor  501 - 2  via line  510 - 1 - 2 , which is a 1.25 GHz 32-bit bus, and  
         [0130]    eight (8) OC-192 SONET/SHD tributary signals to tributary transceiver bank  403  via one-half of bus  422  which is a 1.25 GHz 128-bit bus.  
         [0131]    Constituent add/drop multiplexor  501 - 2  receives:  
         [0132]    one (1) OC-768 SONET/SDH line signal from line transceiver bank  402 - 1  via bus  411 - 1 , which is a 1.25 GHz 32-bit bus,  
         [0133]    one (1) OC-768 SONET/SDH line signal from constituent add/drop multiplexor  501 - 1  via line  510 - 1 - 2 , which is a 1.25 GHz 32-bit bus, and  
         [0134]    eight (8) OC-192 SONET/SHD tributary signals from tributary transceiver bank  403  via one-half of bus  421  which is a 1.25 GHz 128-bit bus, and  
         [0135]    transmits:  
         [0136]    one (1) OC-768 SONET/SDH line signal to line transceiver bank  402 - 2  via bus  412 - 2 , which is a 1.25 GHz 32-bit bus,  
         [0137]    one (1) OC-768 SONET/SDH line signal to constituent add/drop multiplexor  501 - 1  via line  510 - 2 - 1 , which is a 1.25 GHz 32-bit bus, and  
         [0138]    eight (8) OC-192 SONET/SHD tributary signals to tributary transceiver bank  403  via one-half of bus  421  which is a 1.25 GHz 128-bit bus.  
         [0139]    Like add/drop multiplexor  401 , constituent add/drop multiplexor  501 - p  is capable of functioning as:  
         [0140]    i. an add/drop multiplexor and  
         [0141]    ii. a switch, or  
         [0142]    iii. a time-slot interchanger, or  
         [0143]    iv. any combination of i, ii, and iii.  
         [0144]    Furthermore, constituent add/drop multiplexor  501 - p  is capable of:  
         [0145]    i. adding an STS-1 from any tributary to one or more lines, or  
         [0146]    ii. dropping an STS-1 from a line to one or more tributaries, or  
         [0147]    iii. both i and ii.  
         [0148]    And still furthermore, constituent add/drop multiplexor  501 - p  is capable of routing any STS-1 from any line or tributary to:  
         [0149]    i. one or more lines, or  
         [0150]    ii. one or more tributaries,  
         [0151]    iii. both i and ii.  
         [0152]    And yet furthermore, constituent add/drop multiplexor  501 - p  is capable of moving or copying any STS-1 from any time slot in any line or tributary to one or more other time slots in the same line or tributary.  
         [0153]    In accordance with the illustrative embodiment, constituent add/drop multiplexor  501 - 1  and constituent add/drop multiplexor  501 - 2  are each fabricated as identical integrated circuits.  
         [0154]    It will be clear to those skilled in the art how to make and use add/drop multiplexor  401 . For example, one architecture for making and using add/drop multiplexor  401  is taught in U.S. patent application Ser. No. 09/973,972, entitled “Composite Add/Drop Multiplexor,” filed on Nov. 9, 2001, which is incorporated by reference.  
         [0155]    It will be clear to those skilled in the art how to make and use constituent add/drop multiplexor  501 - p . For example, one architecture for making and using constituent add/drop multiplexor  501 - p  is taught in U.S. patent application Ser. No. 09/974,448, entitled “Switching Network,” filed on Oct. 10, 2001, which is incorporated by reference.  
         [0156]    [0156]FIG. 6 depicts a block diagram of line transceiver bank  302 - 1 , which comprises four loop-back transceivers, loop-back transceiver  601 - q,  for q=1 to 4. In accordance with the illustrative embodiment, two loop-back transceivers are fabricated on a single integrated circuit. Therefore, line transceiver bank  302 - 1  comprises two integrated circuits.  
         [0157]    In line transceiver bank  302 - 1 , transceiver  601 - q  receives:  
         [0158]    1. a fraction of an OC-768 SONET/SDH signal from electro/optical converter  202 - 1  via bus  601 - q - 1  of 8-bit width,  
         [0159]    2. a fraction of an OC-768 SONET/SDH signal from switching unit  301 - 2  via bus  601 - q - 3  of 4-bit width, and  
         [0160]    3. a fraction of an OC-768 SONET/SDH signal from switching unit  301 - 1  via bus  601 - q - 4  of 4-bit width, and  
         [0161]    transmits:  
         [0162]    1. a fraction of an OC-768 SONET/SDH signal to electro/optical converter  202 - 1  via bus  601 - q - 2  of 8-bit width,  
         [0163]    2. a fraction of an OC-768 SONET/SDH signal to switching unit  301 - 1  via bus  601 - q - 5  of 4-bit width, and  
         [0164]    3. a fraction of an OC-768 SONET/SDH signal to switching unit  301 - 2  via bus  601 - q - 6  of 4-bit width.  
         [0165]    Line transceiver bank  302 - 1  performs a number of functions, which include:  
         [0166]    i. serializing the OC-768 SONET/SDH signal from electro/optical converter  202 - 1 ,  
         [0167]    ii. adding parity bits to the OC-768 SONET/SDH signal from electro/optical converter  202 - 1  so that forward error correction can be performed on the signal by both switching unit  301 - 1  and  301 - 2 ,  
         [0168]    iii. adding framing bits to the OC-768 SONET/SDH signal from electro/optical converter  202 - 1  so that frame, word, and symbol synchronization can be facilitated by both switching unit  301 - 1  and  301 - 2 ,  
         [0169]    iv. transmitting the serialized OC-768 SONET/SDH signal from electro/optical converter  202 - 1  to both switching unit  301 - 1  and  301 - 2 ,  
         [0170]    v. deserializing the OC-768 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 ,  
         [0171]    vi. performing forward error correction on the OC-768 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 ,  
         [0172]    vii. performing bit, symbol, and word synchronization on the OC-768 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 , and  
         [0173]    viii. selecting whether the OC-768 SONET/SDH signal from switching unit  301 - 1  or from switching unit  301 - 2  is output to electro/optical converter  202 - 1  via bus  212 - 1 .  
         [0174]    The design and operation of loop-back transceiver  601 - q  is described below and with respect to FIGS. 12 through 14.  
         [0175]    [0175]FIG. 7 depicts a block diagram of line transceiver bank  302 - 2 , which comprises four loopback transceivers, loop-back transceiver  601 - q , for q=5 to 8. In accordance with the illustrative embodiment, two loop-back transceivers are fabricated on a single integrated circuit. Therefore, line transceiver bank  302 - 2  comprises two integrated circuits.  
         [0176]    In line transceiver bank  302 - 2 , transceiver  601 - q  receives:  
         [0177]    1. a fraction of an OC-768 SONET/SDH signal from electro/optical converter  202 - 2  via bus  601 - q - 1  of 8-bit width,  
         [0178]    2. a fraction of an OC-768 SONET/SDH signal from switching unit  301 - 2  via bus  601 - q - 3  of 4-bit width, and  
         [0179]    3. a fraction of an OC-768 SONET/SDH signal from switching unit  301 - 1  via bus  601 - q - 4  of 4-bit width; and  
         [0180]    transmits:  
         [0181]    1. a fraction of an OC-768 SONET/SDH signal to electro/optical converter  202 - 2  via bus  601 - q - 2  of 8-bit width,  
         [0182]    2. a fraction of an OC-768 SONET/SDH signal to switching unit  301 - 1  via bus  601 - q - 5  of 4-bit width, and  
         [0183]    3. a fraction of an OC-768 SONET/SDH signal to switching unit  301 - 2  via bus  601 - q - 6  of 4-bit width.  
         [0184]    Line transceiver bank  302 - 2  performs a number of functions, which include:  
         [0185]    i. serializing the OC-768 SONET/SDH signal from electro/optical converter  202 - 2 ,  
         [0186]    ii. adding parity bits to the OC-768 SONET/SDH signal from electro/optical converter  202 - 2  so that forward error correction can be performed on the signal by both switching unit  301 - 1  and  301 - 2 ,  
         [0187]    iii. adding framing bits to the OC-768 SONET/SDH signal from electro/optical converter  202 - 2  so that frame, word, and symbol synchronization can be facilitated by both switching unit  301 - 1  and  301 - 2 ,  
         [0188]    iv. transmitting the serialized OC-768 SONET/SDH signal from electro/optical converter  202 - 2  to both switching unit  301 - 1  and  301 - 2 ,  
         [0189]    v. deserializing the OC-768 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 ,  
         [0190]    vi. performing forward error correction on the OC-768 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 ,  
         [0191]    vii. performing bit, symbol, and word synchronization on the OC-768 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 , and  
         [0192]    viii. selecting which OC-768 SONET/SDH signal from switching unit  301 - 1  or  301 - 2  is output to electro/optical converter  202 - 2  via bus  212 - 2 .  
         [0193]    The design and operation of loop-back transceiver  601 - q  is described below and with respect to FIGS. 12 through 14.  
         [0194]    [0194]FIG. 8 depicts a block diagram of line transceiver bank  402 - 1 , which comprises four loop-back transceivers, loop-back transceiver  601 - q , for q=9 to 12. In accordance with the illustrative embodiment, two loop-back transceivers are fabricated on a single integrated circuit. Therefore, line transceiver bank  402 - 1  comprises two integrated circuits.  
         [0195]    In line transceiver bank  402 - 1 , transceiver  601 - q  receives:  
         [0196]    1. a fraction of an OC-768 SONET/SDH signal from add/drop multiplexor  401  via bus  601 -( q - 8 )- 1  of 8-bit width, and  
         [0197]    2. a fraction of an OC-768 SONET/SDH signal from line transceiver bank  302 - 1  via bus  601 -( q - 8 )- 4  of 4-bit width; and  
         [0198]    transmits:  
         [0199]    1. a fraction of an OC-768 SONET/SDH signal to add/drop multiplexor  401  via bus  601 -( q - 8 )- 2  of 8-bit width,  
         [0200]    2. a fraction of an OC-768 SONET/SDH signal to line transceiver bank  302 - 1  via bus  601 -( q - 8 )- 5  of 4-bit width.  
         [0201]    Line transceiver bank  402 - 1  performs a number of functions, which include:  
         [0202]    i. serializing the OC-768 SONET/SDH signal from add/drop multiplexor  401 ,  
         [0203]    ii. adding parity bits to the OC-768 SONET/SDH signal from add/drop multiplexor  401  so that forward error correction can be performed on the signal by line transceiver bank  302 - 1 ,  
         [0204]    iii. adding framing bits to the OC-768 SONET/SDH signal from add/drop multiplexor  401  so that frame, word, and symbol synchronization can be facilitated by line transceiver bank  302 - 1 ,  
         [0205]    iv. transmitting the serialized OC-768 SONET/SDH signal from add/drop multiplexor  401  to line transceiver bank  302 - 1 ,  
         [0206]    v. deserializing the OC-768 SONET/SDH signal from line transceiver bank  302 - 1 ,  
         [0207]    vi. performing forward error correction on the OC-768 SONET/SDH signal from line transceiver bank  302 - 1 ,  
         [0208]    vii. performing bit, symbol, and word synchronization on the OC-768 SONET/SDH signals from line transceiver bank  302 - 1 , and  
         [0209]    viii. looping back, when necessary or advantageous, the OC-768 SONET/SDH signal from bus  412 - 1  to bus  411 - 1 .  
         [0210]    The loop-back function, in particular, when combined with the serializing and deserializing functions, enables switch complex  201  to be functionally flexible, scalable, hot-swappable, and hot-sparable. The design and operation of loop-back transceiver  601 - q  is described below and with respect to FIGS. 12 through 14.  
         [0211]    [0211]FIG. 9 depicts a block diagram of line transceiver bank  402 - 2 , which comprises four loop-back transceivers, transceiver  601 - q , for q=13 to 16. In accordance with the illustrative embodiment, two loop-back transceivers are fabricated on a single integrated circuit. Therefore, line transceiver bank  402 - 2  comprises two integrated circuits.  
         [0212]    Loop-back transceiver  601 - q  receives:  
         [0213]    1. a fraction of an OC-768 SONET/SDH signal from add/drop multiplexor  401  via bus  601 -( 12 - q )- 1  of 8-bit width, and  
         [0214]    2. a fraction of an OC-768 SONET/SDH signal from line transceiver bank  302 - 1  via bus  601 -( 12 - q )- 4  of 4-bit width; and  
         [0215]    transmits:  
         [0216]    1. a fraction of an OC-768 SONET/SDH signal to add/drop multiplexor  401  via bus  601 -( 12 - q )- 2  of 8-bit width,  
         [0217]    2. a fraction of an OC-768 SONET/SDH signal to line transceiver bank  302 - 2  via bus  601 -( 12 - q )- 5  of 4-bit width.  
         [0218]    Line transceiver bank  402 - 2  performs a number of functions, which include:  
         [0219]    i. serializing the OC-768 SONET/SDH signal from add/drop multiplexor  401 ,  
         [0220]    ii. adding parity bits to the OC-768 SONET/SDH signal from add/drop multiplexor  401  so that forward error correction can be performed on the signal by line transceiver bank  302 - 2 ,  
         [0221]    iii. adding framing bits to the OC-768 SONET/SDH signal from add/drop multiplexor  401  so that frame, word, and symbol synchronization can be facilitated by line transceiver bank  302 - 2 ,  
         [0222]    iv. transmitting the serialized OC-768 SONET/SDH signal from add/drop multiplexor  401  to line transceiver bank  302 - 2 ,  
         [0223]    v. deserializing the OC-768 SONET/SDH signal from line transceiver bank  302 - 2 ,  
         [0224]    vi. performing forward error correction on the OC-768 SONET/SDH signal from line transceiver bank  302 - 2 ,  
         [0225]    vii. performing bit, symbol, and word synchronization on the OC-768 SONET/SDH signals from line transceiver bank  302 - 2 , and  
         [0226]    viii. looping back, when necessary or advantageous, the OC-768 SONET/SDH signal from bus  412 - 2  to bus  411 - 2 .  
         [0227]    The loop-back function, in particular, when combined with the serializing and deserializing functions, enables switch complex  201  to be functionally flexible, scalable, hot-swappable, and hot-sparable. The design and operation of loop-back transceiver  601 - q  is described below and with respect to FIGS. 12 through 14.  
         [0228]    [0228]FIG. 10 depicts a block diagram of tributary transceiver bank  303 , which comprises sixteen loop-back transceivers, loop-back transceiver  601 - q , for q=17 to 32. In accordance with the illustrative embodiment, two loop-back transceivers are fabricated on a single integrated circuit. Therefore, tributary transceiver bank  303  comprises eight integrated circuits.  
         [0229]    In tributary transceiver bank  303 , transceiver  601 - q  receives:  
         [0230]    1. one (1) OC-192 SONET/SDH signal from electro/optical converter  203  via bus  601 -( q - 16 )- 1  of 8-bit width,  
         [0231]    2. one (1) OC-192 SONET/SDH signal from switching unit  301 - 1  via bus  601 -( q - 16 )- 3  of 4-bit width, and  
         [0232]    3. one (1) OC-192 SONET/SDH signal from switching unit  301 - 2  via bus  601 -( q - 16 )- 4  of 4-bit width; and  
         [0233]    transmits:  
         [0234]    1. one (1) OC-192 SONET/SDH signal to electro/optical converter  203  via bus  601 -( q - 16 )- 2  of 8-bit width,  
         [0235]    2. one (1) OC-192 SONET/SDH signal to switching unit  301 - 1  via bus  601 -( q - 16 )- 5  of 4-bit width, and  
         [0236]    3. one (1) OC-192 SONET/SDH signal to switching unit  301 - 2  via bus  601 -( q - 16 )- 6  of 4-bit width.  
         [0237]    Tributary transceiver bank  303  performs a number of functions, which include:  
         [0238]    i. serializing the sixteen (16) OC-192 SONET/SDH signals from electro/optical converter  203 ,  
         [0239]    ii. adding parity bits to the sixteen (16) OC-192 SONET/SDH signals from electro/optical converter  202 - 1  so that forward error correction can be performed on the signal by both switching unit  301 - 1  and  301 - 2 ,  
         [0240]    iii. adding framing bits to the sixteen (16) OC-192 SONET/SDH signals from electro/optical converter  202 - 1  so that frame, word, and symbol synchronization can be facilitated by both switching unit  301 - 1  and  301 - 2 ,  
         [0241]    iv. transmitting all sixteen (16) OC-192 SONET/SDH signals from electro/optical converter  202 - 1  to both switching unit  301 - 1  and  301 - 2 ,  
         [0242]    v. deserializing the sixteen (16) OC-192 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 ,  
         [0243]    vi. performing forward error correction on the sixteen (16) OC-192 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 ,  
         [0244]    vii. performing bit, symbol, and word synchronization on the sixteen (16) OC-192 SONET/SDH signals from both switching unit  301 - 1  and  301 - 2 , and  
         [0245]    viii. selecting whether the sixteen (16) OC-192 SONET/SDH signals from switching unit  301 - 1  or from switching unit  301 - 2  is output to electro/optical converter  203  via bus  222 .  
         [0246]    The design and operation of loop-back transceiver  601 - q  is described below and with respect to FIGS. 12 through 14.  
         [0247]    [0247]FIG. 11 depicts a block diagram of tributary transceiver bank  403 , which comprises sixteen loop-back transceivers loop-back transceiver  601 - q , for q=33 to 48. In accordance with the illustrative embodiment, two loop-back transceivers are fabricated on a single integrated circuit. Therefore, tributary transceiver bank  403  comprises eight integrated circuits.  
         [0248]    Loop-back transceiver  601 - q  receives:  
         [0249]    1. one (1) OC-192 SONET/SDH signal from add/drop multiplexor  401  via bus  601 -( q - 24 )- 1  of 8-bit width, and  
         [0250]    2. one (1) OC-192 SONET/SDH signal from tributary transceiver bank  303  via bus  601 -( q - 24 )- 4  of 4-bit width; and  
         [0251]    transmits:  
         [0252]    1. one (1) OC-192 SONET/SDH signal to add/drop multiplexor  401  via bus  601 -( q - 24 )- 2  of 8-bit width, and  
         [0253]    2. one (1) OC-192 SONET/SDH signal to tributary transceiver bank  303  via bus  601 -( q - 24 )- 5  of 4-bit width.  
         [0254]    Tributary transceiver bank  403  performs a number of functions, which include:  
         [0255]    i. serializing the sixteen (16) OC-192 SONET/SDH signals from add/drop multiplexor  401  for transmission to tributary transceiver  303 ,  
         [0256]    ii. adding parity bits to the sixteen (16) OC-192 SONET/SDH signals from add/drop multiplexor  401  so that forward error correction can be performed on the signals by tributary transceiver  303 ,  
         [0257]    iii. adding framing bits to the sixteen (16) OC-192 SONET/SDH signals from add/drop multiplexor  401  so that frame, word, and symbol synchronization can be facilitated by tributary transceiver  303 ,  
         [0258]    iv. transmitting all sixteen (16) OC-192 SONET/SDH signals from add/drop multiplexor  401  to tributary transceiver  303 ,  
         [0259]    v. deserializing the sixteen (16) OC-192 SONET/SDH signals from tributary transceiver  303 ,  
         [0260]    vi. performing forward error correction on the sixteen (16) OC-192 SONET/SDH signals from tributary transceiver  303 ,  
         [0261]    vii. performing bit, symbol, and word synchronization on the sixteen (16) OC-192 SONET/SDH signals from tributary transceiver  303 ,  
         [0262]    viii. transmitting eight (8) of the sixteen (16) OC-192 signals to constituent add/drop multiplexor  501 - 1  (shown in FIG. 5), and  
         [0263]    ix. transmitting the other eight (8) of the sixteen (16) OC-192 signals to constituent add/drop multiplexor  501 - 2  (which is also shown in FIG. 5).  
         [0264]    The design and operation of loop-back transceiver  601 - q  is described below and with respect to FIGS. 12 through 14.  
         [0265]    [0265]FIGS. 12, 13, and  14  each depict block diagrams of three alternative embodiments of loop-back transceiver  601 - q.    
         [0266]    Each of the three alternative embodiments comprises a serializer, serializer  1101 , that serializes a series of 8-bit words into a series of 4-bit words. It will be clear to those skilled in the art how to make and use serializer  1101 . For example, U.S. patent application Ser. No. 10/011,938, entitled “Serializer,” filed on Dec. 5, 2001, which is incorporated by reference, teaches a serializer that is suitable for use with some embodiments of the present invention. Although loop-back transceiver  601 - q  serializes 8-bit words into 4-bit words and adds parity and framing bits, it will be clear to those skilled in the art, after reading this specification, how to make and use transceivers that serialize words of different than 8-bit widths into words of different than 4-bits widths.  
         [0267]    Each of the three alternative embodiments comprises one or more deserializers, deserializer  1102 - 1 ,  1102 - 2 , and  1101 - 3 , that deserialize a series of 4-bit words into a series of 8-bit words. It will be clear to those skilled in the art how to make and use deserializer  1102 - 1 ,  1102 - 2 , and  1101 - 3 . For example, U.S. patent application Ser. No. 09/909,499, entitled “Deserializer,” filed on Jul. 20, 2001, which is incorporated by reference, teaches a deserializer that is suitable for use with some embodiments of the present invention. Although loop-back transceiver  601 - q  deserializes 4-bit words into 8-bit words, it will be clear to those skilled in the art, after reading this specification, how to make and use transceivers that deserialize words of other than 4-bit widths into words of other than 8-bit widths.  
         [0268]    Whenever system components on different assemblies communicate, the bit error rate for signals transmitted between the components tends to be higher than for system components that are fabricated on one assembly. Similarly, whenever system components on different assemblies communicate, the skew for signals transmitted between the components tends to be greater than for system components that are fabricated on one assembly. In accordance with the illustrative embodiment, line transceiver bank  402 - 1  is fabricated on a different assembly than is line transceiver bank  302 - 1 , line transceiver bank  402 - 2  is fabricated on a different assembly than is line transceiver bank  302 - 2 , and tributary transceiver bank  303  is fabricated on a different assembly than is tributary transceiver bank  403 . Therefore, line transceiver bank  302 - 1 ,  302 - 2 ,  402 - 1 , and  402 - 2 , and tributary transceiver banks  303  and  403  incorporate mechanisms for forward error correction and symbol and word synchronization. It will be clear to those skilled in the art how to make and use these mechanisms. For example, U.S. patent application Ser. No. 10/014,371, entitled “Forward Error Correction and Framing Protocol,” filed Jan. 8, 2002, which is incorporated by reference, teaches a protocol for use with a serializer for adding parity and framing bits to a serialized bit stream so that forward error correction and symbol and word synchronization can be performed.  
         [0269]    [0269]FIG. 12 depicts the first illustrative embodiment of loop-back transceiver  601 - q , which comprises serializer  1101 , deserializer  1102 - 1 , deserializer  1102 - 2 , and multiplexor  1103 .  
         [0270]    Serializer  1101  serializes the series of 8-bit words on bus  601 - q - 1  into a series of 4-bit words. Serializer  1101  also adds parity bits to the signal on bus  601 - q - 1  to enable forward error correction and also adds framing bits to the signal on bus  601 - q - 1  to enable frame, word, and symbol synchronization.  
         [0271]    The output signal of serializer  1101  is passed through two drivers for driving the output signal off of loop-back transceiver  601 - q  via two different sets of pads associated with each of buses  601 - q - 5  and  601 - q - 6 .  
         [0272]    Deserializer  1102 - 1  deserializes the series of 4-bit words on bus  601 - q - 3  into a series of 8-bit words. Deserializer  1102 - 1  also performs forward error correction and frame, word, and symbol synchronization on the series of 4-bit words on bus  601 - q - 3 .  
         [0273]    Deserializer  1102 - 2  deserializes the series of 4-bit words on bus  601 - q - 4  into a series of 8-bit words. Deserializer  1102 - 2  also performs forward error correction and frame, word, and symbol synchronization on the series of 4-bit words on bus  601 - q - 4 .  
         [0274]    All of the deserializers in a transceiver bank cooperate to perform word synchronization, as is taught in U.S. patent applications Ser. Nos. 09/909,499 and 10/014,371.  
         [0275]    Multiplexor  1103  selects the signal on bus  601 - q - 2  from the output signal of deserializer  1102 - 1 , the output signal of deserializer  1102 - 2 , and the signal on bus  601 - q - 1 . When multiplexor  1103  selects the signal on bus  601 - q - 2  from the signal on bus  601 - q - 1 , the signal is looped back into the relevant add/drop multiplexor. This is useful for providing a conduit when performing automatic protection switching. Multiplexor  1103  also enables line transceiver bank  302 - 1  and  302 - 2  and tributary transceiver bank  303  to decide whether to use the output of switching unit  301 - 1  or  301 - 2 , which is useful in enabling switch complex  201  to be hot-swappable and hot-sparable.  
         [0276]    [0276]FIG. 13 depicts the second illustrative embodiment of loop-back transceiver  601 - q  which comprises serializer  1101 , deserializer  1102 - 1 , deserializer  1102 - 2 , and deserializer  1102 - 3 , and multiplexor  1103 . Serializer  1101  serializes the series of 8-bit words on bus  601 - q - 1  into a series of 4-bit words. Serializer  1101  also adds parity bits to the signal on bus  601 - q - 1  to enable forward error correction and also adds framing bits to the signal on bus  601 - q - 1  to enable frame, word, and symbol synchronization.  
         [0277]    The output signal of serializer  1101  is passed through two drivers for driving the output signal off of loop-back transceiver  601 - q  via two pads, corresponding to bus  601 - q - 5  and  601 - q - 6 .  
         [0278]    Deserializer  1102 - 1  deserializes the series of 4-bit words on bus  601 - q - 3  into a series of 8-bit words. Deserializer  1102 - 1  also performs forward error correction and frame, word, and symbol synchronization on the series of 8-bit words on bus  601 - q - 3 .  
         [0279]    Deserializer  1102 - 2  deserializes the series of 4-bit words on bus  601 - q - 4  into a series of 8-bit words. Deserializer  1102 - 2  also performs forward error correction an frame, word, and symbol synchronization on the signal on bus  601 - q - 4 .  
         [0280]    Deserializer  1102 - 3  deserializes the series of 4-bit words output by serializer  1101  into a series of 8-bit words. Deserializer  1102 - 3  also performs forward error correction and frame, word, and symbol synchronization on the output signal of serializer  1101 .  
         [0281]    Multiplexor  1103  selects the signal on bus  601 - q - 2  from the output signals of deserializer  1102 - 1 , deserializer  1102 - 2 , and deserializer  1102 - 3 . When multiplexor  1103  selects the signal on bus  601 - q - 2  from the signal on bus  601 - q - 1 , the signal is looped back into the relevant add/drop multiplexor. This is useful for providing a conduit when performing automatic protection switching. Multiplexor  1103  also enables line transceiver bank  302 - 1  and  302 - 2  and tributary transceiver bank  303  to decide whether to use the output of switching unit  301 - 1  or  301 - 2 , which is useful in enabling switch complex  201  to be hot-swappable and hot-sparable.  
         [0282]    [0282]FIG. 14 depicts the third illustrative embodiment of loop-back transceiver  601 - q,  which comprises serializer  1101 , deserializer  1101 - 1 , deserializer  1101 - 1 , multiplexor  1104 , and multiplexor  1105 . Serializer  1101  serializes the series of 8-bit words on bus  601 - q - 1  into a series of 4-bit words. Serializer  1101  also adds parity bits to the signal on bus  601 - q - 1  to enable forward error correction and also adds framing bits to the signal on bus  601 - q - 1  to enable frame, word, and symbol synchronization.  
         [0283]    The output signal of serializer  1101  is passed through two drivers for driving the output signal off of loop-back transceiver  601 - q  via two pads, corresponding to bus  601 - q - 5  and  601 - q - 6 .  
         [0284]    Multiplexor  1105  selects the input into deserializer  1102 - 1  from the output of serializer  1101  and the series of 4-bit words on bus  601 - q - 3 .  
         [0285]    Deserializer  1102 - 1  deserializes the output series of 4-bit words of multiplexor  1105  into a series of 8-bit words. Deserializer  1102 - 1  also performs forward error correction and frame, word, and symbol synchronization on the output signal of multiplexor  1105 .  
         [0286]    Deserializer  1102 - 2  deserializes the series of 4-bit words on bus  601 - q - 4  into a series of 8-bit words. Deserializer  1102 - 2  also performs forward error correction and frame, word, and symbol synchronization on the signal on bus  601 - q - 4 .  
         [0287]    Multiplexor  1104  selects the signal on bus  601 - q - 2  from the output signal of deserializer  1102 - 1  and the output signal of deserializer  1102 - 2 .  
         [0288]    When multiplexor  1104  selects the signal on bus  601 - q - 2  from the signal on bus  601 - q - 1 , the signal is looped back into the relevant add/drop multiplexor. This is useful for providing a conduit when performing automatic protection switching. Multiplexor  1103  also enables line transceiver bank  302 - 1  and  302 - 2  and tributary transceiver bank  303  to decide whether to use the output of switching unit  301 - 1  or  301 - 2 , which is useful in enabling switch complex  201  to be hot-swappable and hot-sparable.  
         [0289]    There are advantages to each of the three alternative embodiments of loop-back transceiver  601 - q  as they are depicted in FIGS. 12, 13, and  14 . In the first illustrative embodiment depicted in FIG. 12, the loop-back bus requires a minimal change in hardware, requiring no additional deserializer or multiplexor and resulting in relatively low cost for the loop-back bus. Specifically, to support the loop-back bus, multiplexor  1103  must handle three input signals instead of two.  
         [0290]    In the second illustrative embodiment depicted in FIG. 13, the loop-back bus is achieved by using a frame-encoded signal at the output of serializer  1101 . This method offers high reliability, important for high-speed applications in particular. Since the looped back signal is passed through a deserializer, as are the serialized inputs to loop-back transceiver  601 - q , there is a lack of relative delay between the unserialized inputs to multiplexor  1103 .  
         [0291]    In the third illustrative embodiment depicted in FIG. 14, the loop-back bus is also achieved by using a frame-encoded signal at the output of serializer  1101 . This method offers high reliability, important for high-speed applications in particular. This looped-back signal must then be selected by multiplexor  1105  and deserialized. This approach is attractive if multiplexor  1105  can be implemented at low cost and if the relative delay into multiplexor  1104  is tolerable.  
         [0292]    Input  601 - q - 3  is not used in the loop-back transceivers used in line transceiver  402 - 1 ,  402 - 2 , and tributary transceiver  403 .  
         [0293]    [0293]FIG. 15 depicts a block diagram of switching unit  301 - b , in which the interconnections between add/drop multiplexor  401 , line transceiver bank  402 - 1 , and line transceiver bank  402 - 2  are shown so as to highlight the criss-cross nature of the loop-back mechanism in switching unit  301 -b. Note that the buses interconnecting add/drop multiplexor  401  with line transceiver block  402 - 1  and with line transceiver block  402 - 2  are in a criss-cross pattern. The criss-cross pattern is a characteristic of the architecture in the illustrative embodiment of the present invention, in which loop-back transceiver  601 - q  processes signals bi-directionally, constituent add/drop multiplexor  501 - 1  processes line signals traveling from right to left (as depicted), and constituent add/drop multiplexor  501 - 2  processes line signals traveling from left to right (as depicted).  
         [0294]    [0294]FIG. 16 depicts a block diagram of the functional signal flows through switch complex  201 . FIG. 16 depict the buses throughout switch complex  201 , in relation to the four (4) constituent add/drop multiplexors (“CADM”) and the eight logical multiplexors in switch complex  201 .  
         [0295]    Constituent add/drop multiplexor  1601 - 1  is constituent add/drop multiplexor  501 - 1  in switching unit  301 - 1 . Constituent add/drop multiplexor  1601 - 2  is constituent add/drop multiplexor  501 - 2  in switching unit  301 - 1 . Constituent add/drop multiplexor  1601 - 3  is constituent add/drop multiplexor  501 - 1  in switching unit  301 - 2 . Constituent add/drop multiplexor  1601 - 4  is constituent add/drop multiplexor  501 - 2  in switching unit  301 - 2 .  
         [0296]    Multiplexor  1611  - 1  is the aggregate multiplexor found in the loop-back transceivers in line transceiver bank  402 - 1  in switching unit  301 - 1 . Multiplexor  1611 - 2  is the aggregate multiplexor found in the loop-back transceivers in line transceiver bank  402 - 2  in switching unit  301 - 1 . Multiplexor  1611 - 3  is the aggregate multiplexor found in the loop-back transceivers in line transceiver bank  402 - 1  in switching unit  301 - 2 . Multiplexor  1611 - 4  is the aggregate multiplexor found in the loop-back transceivers in line transceiver bank  402 - 2  in switching unit  301 - 2 .  
         [0297]    Multiplexor  1621 - 1  is the aggregate multiplexor found in the loop-back transceivers in line transceiver  302 - 1  and multiplexor  1621 - 2  is the aggregate multiplexor found in the loop-back transceivers in line transceiver  302 - 2 .  
         [0298]    Multiplexor  1631 - 1  and multiplexor  1631 - 2  are together found in the loop-back transceivers in tributary transceiver bank  303 .  
         [0299]    It is to be understood that the above-described embodiments are merely illustrative of the present invention and that many variations of the above-described embodiments can be devised by those skilled in the art without departing from the scope of the invention. It is therefore intended that such variations be included within the scope of the following claims and their equivalents.