Abstract:
A low power differential amplifier powered by a plurality of unequal power supply voltages. The input stage operates at a higher power supply voltage so as to maintain its transistors in operational states of saturation while providing a sufficient dynamic signal voltage range. The output stage operates at a lower power supply voltage while providing a sufficient dynamic signal current range.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to differential amplifiers, and in particular, to differential amplifiers operating in a low power circuit environment. 
     2. Description of the Related Art 
     Referring to FIGS. 1A and 1B, switched capacitor circuits are well known in the art. Such circuits can be used to provide various signal filtering or integration functions and typically have two phases, or states, of operation: a sample phase Oa and a holding phase  10   b . As is well known in the art, switches (not shown) driven by nonoverlapping clock signal phases (not shown) cause input and feedback capacitances coupled to the input terminals  11   a ,  11   b  of the differential amplifier  12 , to switch between reception of the positive Vinp and negative Vinn phases of the differential input signal Vin, and circuit ground GND, thereby feeding back the positive Voutp  13   a  and negative Voutn  13   b  signal phases of the output signal Vout. Load capacitances Cload couple the output signal terminals  13   a ,  13   b , to circuit ground GND. 
     As is further well known, modern complementary metal oxide semiconductor (CMOS) processes are continuing to scale down in terms of power supply voltage magnitudes. Indeed, some circuits are now expected to operate at power supply voltages at or below one volt. Particularly for the amplifier  12  in a switched capacitor circuit, such low power supply voltages result in lost headroom for the analog amplifier circuitry. 
     Referring to FIG. 2, a typical implementation of the differential amplifier  12  includes two circuit branches  12   a ,  12   b  formed by the serial connections of transistors M 2  and M 4  and transistors M 1  and M 3 , powered by a power supply voltage VDD and driven by a tail current source  14 , which together produce a total amplifier bias current of 2*Islew. When used in the switched capacitor circuit  10 , the overall circuitry has one pole at a dominant pole position, and a feedback factor associated with the switched capacitors C. (It should be understood that this simplified analysis ignores the input capacitance of the differential amplifier circuit  12 .) 
     At low power supply VDD voltages, it is difficult to maintain the transistors M 1 , M 2 , M 3 , M 4  of the amplifier  12  in their respective operational states of saturation. This difficulty increases significantly when cascode devices are added to the P-MOS and N-MOS portions of the circuit  12 . Accordingly, high DC gain cannot be achieved. Moreover, simply increasing the power supply voltage VDD to improve headroom will significantly increase power dissipation of the circuit  12 . 
     Referring to FIG. 3, the aforementioned dominant pole causes the open loop gain bandwidth product GBW′ for the amplifier  12  to be a function of the transconductance gm of the input transistors M 1 , M 2  and the switched and load Cload capacitances. The feedback factor f, which is equal to 0.5 for equal valued switched capacitances C, affects the closed loop gain bandwidth product GBW accordingly (GBW=GBW′*f). 
     SUMMARY OF THE INVENTION 
     In accordance with the presently claimed invention, a low power differential amplifier is powered by a plurality of unequal power supply voltages. The input stage operates at a higher power supply voltage so as to maintain its transistors in operational states of saturation while providing a sufficient dynamic signal voltage range. The output stage operates at a lower power supply voltage while providing a sufficient dynamic signal current range. 
     In accordance with one embodiment of the presently claimed invention, a low power differential amplifier powered by a plurality of unequal power supply voltages includes power supply terminals, telescopic differential amplifier circuitry and voltage follower circuitry. A first power supply terminal conveys a first power supply voltage having a first voltage magnitude. A second power supply terminal conveys a second power supply voltage having a second voltage magnitude which is less than the first voltage magnitude. The telescopic differential amplifier circuitry, coupled to the first power supply terminal, responds to reception of the first power supply voltage and an input differential signal by providing an intermediate differential signal corresponding to the input differential signal. The voltage follower circuitry, coupled to the second power supply terminal and the telescopic differential amplifier circuitry, responds to reception of the second power supply voltage and the intermediate differential signal by providing an output differential signal corresponding to the intermediate differential signal. 
     In accordance with another embodiment of the presently claimed invention, a low power differential amplifier powered by a plurality of unequal power supply voltages includes power means, differential amplifier means and voltage follower means. A first power means is for conveying a first power supply voltage having a first voltage magnitude. A second power means is for conveying a second power supply voltage having a second voltage magnitude which is less than the first voltage magnitude. The differential amplifier means is for receiving the first power supply voltage and an input differential signal and responding thereto by generating an intermediate differential signal corresponding to the input differential signal. The voltage follower means is for receiving the second power supply voltage and the intermediate differential signal and responding thereto by generating an output differential signal corresponding to the intermediate differential signal. 
     In accordance with still another embodiment of the presently claimed invention, a low power differential amplifier powered by a plurality of unequal power supply voltages includes power supply terminals and amplifier circuitries. A first power supply terminal conveys a first power supply voltage having a first voltage magnitude and a first power supply current having a first current magnitude. A second power supply terminal conveys a second power supply voltage having a second voltage magnitude and a second power supply current having a second current magnitude, wherein the first voltage magnitude is greater than the second voltage magnitude and the first current magnitude is less than the second current magnitude. First amplifier circuitry, coupled to the first power supply terminal, responds to reception of the first power supply voltage, the first power supply current and an input differential signal by providing an intermediate differential signal corresponding to the input differential signal. Second amplifier circuitry, coupled to the second power supply terminal and the first amplifier circuitry, responds to reception of the second power supply voltage, the second power supply current and the intermediate differential signal by providing an output differential signal corresponding to the intermediate differential signal. 
     In accordance with yet another embodiment of the presently claimed invention, a low power differential amplifier powered by a plurality of unequal power supply voltages includes power means and amplifier means. A first power means is for conveying a first power supply voltage having a first voltage magnitude and a first power supply current having a first current magnitude. A second power means is for conveying a second power supply voltage having a second voltage magnitude and a second power supply current having a second current magnitude, wherein the first voltage magnitude is greater than the second voltage magnitude and the first current magnitude is less than the second current magnitude. A first amplifier means is for receiving the first power supply voltage, the first power supply current and an input differential signal and responding thereto by generating an intermediate differential signal corresponding to the input differential signal. 
     A second amplifier means is for receiving the second power supply voltage, the second power supply current and the intermediate differential signal and responding thereto by generating an output differential signal corresponding to the intermediate differential signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B are circuit schematic diagrams of the sample and hold phases of a conventional switched capacitor circuit. 
     FIG. 2 is a schematic diagram of a conventional differential amplifier circuit. 
     FIG. 3 is a graph depicting the gain versus frequency characteristic of the circuit of FIG. 2 when used in the circuit of FIGS. 1A and 1B. 
     FIG. 4 is a schematic diagram of a differential amplifier circuit in accordance with one embodiment of the presently claimed invention. 
     FIG. 5 is a graph of the gain versus frequency characteristic of the circuit of FIG. 4 when used in the circuit of FIGS. 1A and 1B. 
     FIG. 6 is a schematic diagram of a differential amplifier circuit in accordance with another embodiment of the presently claimed invention. 
     FIG. 7 is a schematic diagram of a differential amplifier circuit in accordance with still another embodiment of the presently claimed invention. 
     FIG. 8 is a schematic diagram of a differential amplifier circuit in accordance with yet another embodiment of the presently claimed invention. 
    
    
     DETAILED DESCRIPTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
     Further, while the following discussion is in a context of certain arrangements of N-type and P-type metal oxide semiconductor field effect transistors (e.g., N-MOSFETs M 1 , M 2 , M 5  and M 6 , and P-MOSFETs M 3 , M 4 , M 7 , M 8 , M 9  and M 10 , respectively) powered by a positive power supply voltage VDD (where VSS is a negative voltage or ground GND potential), it will be readily understood by one of ordinary skill in the art that corresponding circuit arrangements can be implemented in accordance with well known circuit design techniques in which the N-MOSFETs are replaced with P-MOSFETs, the P-MOSFETs are replaced with N-MOSFETs, and powered is provided by a negative power supply voltage VSS (where VDD is a positive voltage or ground GND potential). 
     Referring to FIG. 4, a differential amplifier  112  in accordance with one embodiment of the presently claimed invention is powered by multiple unequal power supply voltages. The input stage  116  includes two circuit branches  116   a ,  116   b  formed by the serial connections of transistors M 2  and M 4  and transistors M 1  and M 3 , powered by the higher of the two power supply voltages VDD HI, and driven by a tail current source  120  sinking the lower of the two bias currents Ibis (discussed in more detail below). In accordance with well known circuit principles, transistors M 3  and M 4  serve as load devices for the input transistors M 1 , M 2 , and are biased in on states by a bias voltage Vbias. 
     The output stage  118  includes two output circuit branches  118   a ,  118   b  formed by the serial connections of transistor M 5  and current source  122   a  and transistor M 6  and current source  122   b . Each of these circuit branches  118   a ,  1118   b  is powered by the lower of the two power supply voltages VDD LO and conducts the higher of the two power supply currents Islew which is sunk by the current sources  122   a ,  122   b . Compensation capacitances Cc coupled between the gate and drain terminals of the output transistors M 5 , M 6  establish the open loop gain bandwidth product GBW′ for the circuit  112 . 
     Referring to FIG. 5, the differential amplifier  112  of FIG. 4, when used in the switched capacitor circuit of FIGS. 1A and 1B, can be designed to maintain the same open loop gain bandwidth product GBW′ as the circuit  12  of FIG. 2, which is a function of the load Cload and switched capacitances and feedback factor f. The output stage  118  serves as a level shifting stage by nature of the voltage follower action of output transistors M 5  and M 6 . This output stage  118  does not significantly load the input stage  116  because the gate-to-source capacitance Cgs of the output transistors M 5 , M 6  is bootstrapped by the source follower operation of these transistors M 5 , M 6 . Accordingly, the output, or load, capacitance for the input stage  116  is small, and is primarily that of the overlap capacitance of the output transistors M 5 , M 6  (i.e., the capacitance formed by the inherent overlap of the gate terminal and the drain and source regions of the transistor) plus the three gate-to-drain capacitances Cgd of the transistors at the output terminals  117   a ,  117   b  of the input stage  116  (i.e., transistors M 1 , M 3  and M 5  at terminal  117   a , and transistors M 2 , M 4  and M 6  at terminal  117   b ). As a result, the input stage  116  can be biased with a very low bias current Ibias for the desired gain bandwidth product, thereby significantly reducing the power required from the power supply VDD HI. For example, since the input stage  116  can run on such a very low current, the higher power supply voltage VDD HI can be sourced by a power supply typically used for the input and output circuit functions of the host integrated circuit, or alternatively, it can be generated by any of a number of well known voltage generating techniques such as those used in charge pumps. 
     As is well known, a switched capacitor system, such as that depicted in FIGS. 1A and 1B, requires a minimum output current equal to the slew rate requirements. Accordingly, this current requirement determines the value of the output currents Islew driving the output transistors M 5 , M 6 . Hence, for the conventional single stage amplifier  12  (FIG. 2) the bias current was twice this amount, i.e.,  2 *Islew. However, in the two-stage design  112  of FIG. 4, each circuit branch  118   a ,  118   b  of the output stage is biased with such a current Islew. Since these circuit branches  118   a ,  118   b  are powered from the lower power supply voltage, the power dissipated by these circuit branches  118   a ,  18   b  is significantly lower than the power dissipated by the single stage amplifier  12 . Accordingly, with a sufficient voltage difference between the higher VDD HI and lower VDD LO power supply voltages, the total power dissipated in the two stage amplifier  112  can be significantly below that of the single stage amplifier  12 . 
     Referring to FIG. 5, when the amplifier circuit  112  of FIG. 4 is used in a switched capacitor system, such as that shown in FIGS. 1A and 1B, a pole is created in the open loop transfer function of the two-stage amplifier circuit  112  at the same frequency as for the single stage amplifier  12  (FIG. 2) before modification by the feedback factor f. The frequency of this pole is a function of the transconductance gm of the output transistors M 5 , M 6  and the load Cload and switched capacitances of the switched capacitor network (FIGS.  1 A and  1 B). 
     As represented below, the phase margin pm can be calculated as 90 degrees minus the arctangent of frequency divided by the frequency ωp of the pole. When the feedback factor is applied, the gain bandwidth product GBW is affected, but the frequency ωp of the pole is not. Therefore, if the frequencies of the pole cop and open loop gain bandwidth product GBW′ are equal, then the quotient ω/ωp is simply equal to the feedback factor f. In the ideal case, when the feedback factor equals 0.5, the phase margin pm equals 63 degrees and the signal peaking is −0.4 decibels. 
     
       
         
               
               
             
           
               
                   
               
             
             
               
                 Phase Margin = 
                 90 − arctan (ω/ωp) 
               
               
                 GBW′ = 
                 ωp 
               
               
                 Phase Margin = 
                 90 − arctan (f) 
               
               
                 = 
                 90 − arctan (C/(2C)) 
               
               
                 = 
                 90 − arctan (C/(2C)) 
               
               
                 = 
                 90 − arctan (0.5) 
               
               
                 = 
                 63 degrees 
               
               
                 Peaking = 
                 20 * log 10  (1/[sqrt((1 + cos (pm − 180)) 2  + 
               
               
                   
                 (sin (pm − 180)) 2 )]) 
               
               
                 = 
                 −0.4 dB 
               
               
                   
               
             
          
         
       
     
     With peaking virtually zero, settling behavior is optimized and bandwidth is maximized. In practice, however, the feedback factor is generally larger, thereby further improving the phase margin pm. Further, since the output transistors M 5 , M 6  are not critical in determining signal offsets or system noise, they can be biased more aggressively than the input transistors M 1 , M 2 , thereby increasing their respective transconductances gm. This further increases the frequency of the pole, thereby further improving the phase margin pm. 
     Referring to FIG. 6, a differential amplifier circuit  212  in accordance with another embodiment of the presently claimed invention improves upon the circuit  112  of FIG. 4 by adding cascode transistors M 7 , M 8 , M 9 , M 10  to increase the signal gain of the first stage  216 . In a conventional switched capacitor system, such as that shown in FIGS. 1A and 1B, a feedback loop will be provided for the amplifier  12  such that the tail current source  14  (FIG. 2) is provided a control voltage (not shown) such that the common mode voltage appearing at the output terminals  13   a ,  13   b  is maintained at a desired value. However, with the two-stage amplifier design of the presently claimed invention, no such feedback loop or control is necessary. 
     It will be recognized that the common mode output voltage at the output terminals  217   a ,  217   b  of the input stage  216  will be equal to the common mode output voltage at the output terminals  13   a ,  13   b  of the output stage  118  plus one gate-to-source voltage Vgs of the output transistors M 5 , M 6 . Depending upon the magnitude of the power supply voltage VDD HI powering the input stage  216 , this common mode output voltage of the input stage  216  may be too high or too low as compared to the desired headroom for the transistors forming the input stage  216 . 
     Referring to FIG. 7, a differential amplifier circuit  312  in accordance with still another embodiment of the presently claimed invention includes additional bias circuitry  314  to modify, e.g., equalize, the common mode output voltages at the output terminals  217   a ,  217   b  of the input stage  216  and the output terminals  13   a ,  13   b  of the output stage  118 . This bias circuitry  314  includes two circuit branches  314   a ,  314   b , each of which can include a resistor R connected in series between the input  216  and output  118  stages, plus serially connected current sourcing  316  and sinking  318  circuits between the power supply terminals VDD HI, VSS/GND, substantially as shown. Depending upon the desired amount of modification or equalization of the common mode output voltages, any one or two or all three additional circuit elements R,  316 ,  318  may be used to adjust the effective common mode output voltage of the first stage  216 . For example, for the effective common mode output voltage of the input stage  216  to appear equal to the common mode output voltage of the output stage  118 , the product of the resistance R and the difference current Ip-In will be substantially equal to the gate-to-source voltages Vgs of the output transistors M 5 , M 6 . 
     Referring to FIG. 8, the differential amplifier circuit  312  of FIG. 7 can be controlled using a replica bias circuit  400  in accordance with well known replica biasing techniques. The common mode output voltages at the output terminals  217   a ,  217   b ,  13   a ,  13   b  of the input  216  and output  118  stages are monitored and used to provide control signals  401   ap ,  401   an ,  401   bp ,  401   bn  for the current sources  316   a ,  318   a ,  316   b ,  318   b  of the compensation circuit  314  so as to establish the desired difference current Ip-In such that the first stage  216  maintains the desired effective common mode output voltage. 
     While the use of this additional biasing circuitry  314  may degrade the output impedance of the first stage  216 , since capacitively loaded source follower circuits generally exhibit an effectively negative input resistance at their gate terminals, with proper adjustment, the addition of a small resistance R between the input  216  and output  118  stages can improve the transient signal response overall. An upper limit of the value of the resistance R will be determined by the tolerable amount of phase response degradation caused by an additional transfer function pole that becomes more active as the product R*Cc of the resistance R and compensation capacitance Cc becomes increases. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.