Abstract:
A method for forming a fine-pitch flip chip assembly interconnects fine pitch devices after they have been connected to a carrier substrate. A die having a plurality of conductive sections, such as solder balls, is attached to a conductive layer of the substrate. An interconnect pattern is then formed in the conductive layer to connect the conductive sections and generate electronic functionality to the assembly. By forming the interconnect pattern after the device have been connected to the carrier, the invention provides precise alignment between the devices and the interconnect pattern without actually aligning the two components during the assembly process.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to semiconductor devices, and more particularly to an assembly and method for constructing chip assemblies having fine pitch interconnections. 
     2. Description of the Related Art 
     Currently, electronic devices require faster and more compact systems that pack a greater number of components into a smaller chip substrate area. The increased number of components on the chip increases the number of interconnections in the finite spaced offered by the chip. Interconnections are usually conducted via bonding pads or solder bumps through a flip-chip technique. Reducing the distance between the bonding pads, or the “pitch” increases the number of interconnects available on the chip, thereby increasing packaging density and reducing packaging weight. Fine pitch assemblies often rely on the ability to etch or deposit very fine traces onto a carrier material to create the interconnects. 
     FIGS. 1 and 2 illustrate conventionally-known flip-chip technology used to physically and electrically connect two microchips together. FIG. 1 shows two chips  100  and  102  that are bonded together via solder bumps or bonding pads  104  and  106 , respectively. As can be seen in the Figure, the solder bumps  104 ,  106  are aligned together so that corresponding solder bumps  104 ,  106  on each chip  100 ,  102  touch only each other and not any other solder bumps  104 ,  106 . If the solder bumps  104 ,  106  are spaced a relatively large distance apart, that is, if the pitch P allows sufficient spacing in between the solder bumps, alignment is relatively simple even if an automated process is used. The pitch P of the solder bumps  104 ,  106  using this method cannot be reduced to less than 25 microns, making the structure and method shown in FIGS. 1 and 2 unsuitable for applications require very fine pitch structures. 
     More particularly, if the pitch is reduced beyond the alignment capabilities of the bonding pad structure, the likelihood of misalignment increases as can be seen in FIG.  2 . Misalignment can often occur simply because of the difficulty that automated systems have in aligning the solder bumps with the required precision, often causing a given solder bump or bonding pad to touch two other solder bumps or pads to form a undesirable bridge connection. Attempts to increase the precision of alignment between the solder bumps may slow the manufacturing process to such a degree that the overall yield is too low for cost-effective manufacturing. 
     There is a need for a fine pitch flip chip assembly process that allows cost-effective manufacturing of flip-chip assemblies without encountering the alignment problems present in known processes. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a flip chip method and assembly that is suitable for fine pitch devices. The invention includes applying a conductive layer on a substrate and then forming an interconnect pattern on the conductive layer of the substrate after the conductive portions of a die have been attached to the conductive layer on the substrate. In one embodiment, the die is attached to a substrate having a base layer that supports the conductive layer. A portion of the base layer is cut away to expose the conductive layer, and then the interconnect pattern is etched into the conductive layer via a laser. A sealing layer may be deposited over the exposed conductive layer after etching to protect the interconnect pattern and/or act as a heat sink for the assembly. 
     Because the interconnect pattern is formed only after the die has been attached to the substrate, the alignment between the conductive portions of the die and the pattern is automatically conducted during the pattern formation process. As a result, there is no need to precisely align the die with any portion of the substrate as the die and substrate are connected together, making the production of fine pitch devices more cost-effective without sacrificing accurate alignment between the conductive portions of the die and the interconnect pattern on the substrate. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a representative diagram of a known flip-chip assembly; 
     FIG. 2 is another representative diagram of a known flip-chip assembly; 
     FIG. 3 is a top view of the assembly before die attachment; 
     FIG. 4 is a side section view of the assembly in FIG. 3 taken along line  4 — 4  after die attachment; 
     FIG. 5 is a side section view of the assembly in FIG. 4 after the assembly has been flipped; 
     FIG. 6 is a side section view of the assembly in FIG. 5 after removing a portion of the base layer of the assembly; 
     FIG. 7 is a side section view of the assembly after an interconnect pattern has been formed and 
     FIG. 8 is a side section view of the assembly after an insulating layer has been disposed on the assembly. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 3 is a top view of a substrate  300  having a conductive pattern  302  disposed on a base layer  304 . The substrate  300  preferably begins as a two-layer structure with a conductive material disposed on the base layer  304 . Portions of the conductive material are then etched away from the base layer  304  to form a conductive pattern  302 . The conductive pattern  302  includes a die attachment area  306  on which a die can be placed. The conductive pattern  302  itself can be frame-shaped, as shown in FIG. 3, or it can include a solid plane of conductive material in the center area of the pattern. The choice of using a frame-shaped or a solid die attachment area  306  depends on the specific interconnect pattern that will eventually be formed in the assembly. If the interconnect pattern will be used to connect solder balls or other conductive pads located only at the periphery of the die, then applying the conductive material in a frame-shaped pattern is sufficient and will reduce the total amount of conductive material that needs to be eventually removed to form the interconnect pattern. If the interconnect pattern is expected to cover areas away from the periphery of the die and closer to the center of the die, the conductive material can be distributed over a greater portion, or even over the entire area, of the die attachment area  306 . 
     As can be seen in FIG. 3, the die attachment area  306  does not have an interconnect pattern and is not separated into discrete bonding pads or conductive traces; instead, the die attachment area  306  is a continuous plane of conductive material on the substrate  300  at the areas where the die will contact the conductive layer  302 . 
     FIGS. 4 and 5 are side cutaway views, along line  4 — 4  in FIG. 3, of the substrate  300  after a die component  400  is attached to the die attachment area  306 . As can be seen in FIGS. 4 and 5, the die  400  has a plurality of solder balls  402  or other conductive protrusions. During manufacturing, the die  400  is flipped and attached to the substrate  300  so that the solder balls  402  contact the conductive die attachment area  306 . Once the die  400  is attached to the substrate  300 , the entire assembly  404  is flipped to obtain the structure shown in FIGS. 4 and 5, such that the die  400  is at the bottom of the assembly  404  and the base layer  304  of the substrate is at the top of the assembly  404 . 
     Referring to FIGS. 6 and 7, once the assembly  404  has been flipped to place the base layer  304  at the top of the assembly  404 , a laser, such as a CO 2  laser, or other means is used to cut away a window  600  in the base layer  304  and expose the conductive die attachment area  306  on top of the die  400  and the solder balls  402 . As noted in FIG. 3, the conductive material in the die attachment area  306  is preferably continuous at the locations where the solder balls  402  are attached and does not have any pattern thereon that requires alignment with the solder balls  402 . 
     After the window  600  is formed by removing a portion of the base layer  304 , a laser or other means cuts away portions of the conductive material in the die attachment area  306  to form a fine pitch interconnect pattern  700 . As can be seen in FIG. 7, the laser removes the conductive material joining the solder balls  402  so that the solder balls are coupled to the substrate  300  in accordance with the specific interconnections designed to accomplish the electrical functions of the chip assembly  400 . The conductive material that remains after the fine pitch interconnect pattern  700  is etched creates the interconnection between the die  400  and the substrate  300 . Because conductive material  302  between the solder balls  402  is removed after the die  400  is joined to the substrate  300 , there is no need to align the solder balls  402  with any conductive pads on the substrate; instead, the solder balls  402  are automatically and precisely aligned with the fine pitch interconnect pattern  700  after unnecessary conductive material between the solder balls  402  is etched away. The alignment of the laser system with the interconnect pattern to be etched in the conductive material  302  can be conducted via fiducial marks on the base layer  304  of the substrate  300  to instruct the laser etching system which portions of the conductive material  302  to remove to form the interconnect pattern  700  and which portions to leave behind. For example, the location of the solder balls  402  can be obtained using an X-ray and then correlated with the location of the fiducial marks to guide the laser etching system. 
     Note that although the above description specifies using a laser to remove the base layer  304  and conductive material  302 , other material removal methods can also be used, such as chemical etching. Because precision is not as large of a factor in removing the base layer, chemical etching, an excimer laser, or a frequency-quadrupled YAG laser can all be used to create the window  600 . The interconnect pattern requires greater precision; therefore, a YAG laser at prime frequency or a CO 2  laser system may be more appropriate for removing the conductive material to form the pattern. 
     Once the fine pitch interconnect pattern  700  has been formed, a sealing material  800  is deposited in the window portion  600  of the base layer  304  over the interconnect pattern  700 , as can be seen in FIG.  8 . The sealing material  800  can be used to insulate and protect the conductors of the assembly  400 . The sealing material  800  itself can be any material that can flow easily around and through the interconnect pattern  700  and surround the solder balls  402  and pattern  700 . For added functionality, the sealing material  800  can be a high thermal conductivity material, thereby acting as a heat sink to direct heat away from the die  400 . 
     By forming the fine pitch interconnect pattern  700  after the die  400  has been connected to the substrate  300  rather than attempting to align solder balls  402  on the die  402  with the interconnect pattern  700 , the inventive method allows assembly of fine pitch flip chips without requiring any precision alignment steps between the solder balls and pattern on the substrate. The conductive material removal process in essence creates precise alignment between the conductive portions of the die and the interconnect pattern without actually carrying out an alignment process. As a result, the yield from the inventive process tends to be larger than other fine pitch chip assembly methods and can be automated more easily. 
     While the invention has been specifically described in connection with certain specific embodiments thereof, it is to be understood that this is by way of illustration and not of limitation, and the scope of the appended claims should be construed as broadly as the prior art will permit.