Abstract:
This invention provides a circuit and a method for discharging a high voltage to ground level from a circuit node especially in intergrated circuits. The invention relates to a high voltage discharge circuit which prevents semiconductor latch-up and prevents semiconductor damage during the discharge process. In addition, the discharge process takes a short amount of time. A feedback mechanism from the drains of the FETs through inverters back to gate #2 of the dual-gated FETs causes the individual drains of series connected FETs to discharge rapidly. The discharge mechanism of this invention minimizes the voltage times current power and therefore protects the integrated devices from damage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a circuit and a method for discharging high voltage nodes to ground. 
     More particularly this invention relates to a high voltage discharge circuit which prevents semiconductor latch-up and prevents semiconductor damage during the discharge process. 
     2. Description of Related Art 
     Integrated circuits typically are made up of electrically alterable memory and flash memory. For the program and erase operations of these writable memories, an internal high voltage is needed. For example, there are high voltages on some internal nodes of flash memories during program and erase operations. These high-voltage nodes have to be carefully discharged to ground after the program or erase operations are completed. These high voltages must be discharged. If they are allowed to persist in the high density integrated circuit chip environment, the devices could latch-up or could be damaged. 
     The typical prior art circuit for discharging on-chip high voltages consists of a serial connection of N channel metal oxide semiconductor field effect transistors, NMOS FETs. This serial path of NMOS FETs will discharge the high voltage in a timely fashion and without damage to the serial FETs themselves. However, this prior art circuit can only discharge the high voltage down to a voltage of N times the threshold voltage of an NMOS device, Vt. In the example of 4 serially connected NMOS FETs discharging the high voltage, the resultant voltage level would be approximately 4 times 0.6 volts or 2.4 volts. 
     Similarly, in a prior art discharge circuit which has an NMOS load device connected in series with another NMOS discharge device, the high voltage can be discharged close to ground. However, with only one discharge device, the discharge current must be kept small due to the large high discharge voltage at the drain of the NMOS FET device. If the NMOS load device has a large current and a large discharge voltage, the NMOS FETs can be damaged. Therefore, in this second prior art circuit, the discharge current must be reduced. The reduced discharge current will produce a slow discharge circuit. 
     U.S. Pat. No. 5,289,025 (Lee) “Integrated Circuit Having a Boosted Node” describes a circuit to allow connection of a MOS transistor source/drain region to a voltage boosted above the main power supply. Typical uses include clock driver circuits in microprocessors, row lines in dynamic and static memory chips, and substrate bias generators. 
     U.S. Pat. No. 5,767,729 (Song) “Distribution Charge Pump for Nonvolatile Memory Device” describes a charge pump circuit for a nonvolatile memory, such as an EEPROM. The voltage on an internal node capacitance progressively rises over subsequent clock pulses until the node reaches a boosted voltage level which is higher than the power supply voltage. 
     U.S. Pat. No. 6,011,409 (Huang et al.) “Input/Output Buffer Capable of Accepting An Input Logic Signal Higher in Voltage Level Than the System Voltage” discloses an I/O circuit capable of accepting a voltage exceeding the chip supply. 
     BRIEF SUMMARY OF THE INVENTION 
     It is the objective of this invention to provide a circuit and a method for discharging high voltage in a short amount of time from the nodes of circuits especially integrated circuits. 
     It is further an object of this invention to prevent latch-up or damage of devices and circuits during the careful discharge of the high voltage to ground. 
     The objects of this invention are achieved by a high voltage discharge circuit which is made up of a series connected group of NMOS Field effect transistors FETs. The connection from the high voltage node to be discharged to ground via a series of four connected NMOS FETs. Inverters are connected from the drains of the NMOS FETs to the gates of the series connected NMOS FETs, which have two gates for each FET device. The input of the inverters are connected to the drains of the four series connected FETs and the output of the inverters is connected to gate #1 of the four dual-gated FETs. The drains of the four series connected FETs are connected to gate #2 of the dual-gated FETs. The drain of the first series connected FET is connected to the highest voltage node. The source of the first series connected FET is connected to the drain of the second series connected FET. The source of the second series connected FET is connected to the drain of the third series connected FET. The source of the third series connected FET is connected to the drain of the fourth series connected FET. The source of the fourth series connected FET is connected to the drain of a bias FET device. The source of the bias FET is connected to ground. The gate of the bias FET is connected to a voltage bias. The bias FET conducts a discharge current to ground. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The FIGURE shows a circuit illustrating the high voltage discharge apparatus of this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Refer to the figure for the main circuit embodiment of this invention. The high voltage node  102  to be discharged is shown. It is connected to the top-most FET device  110 , shown in a series connection of several FET devices in the FIGURE. Four of the series connected FET devices  110 ,  120 ,  130 , &amp;  140  are dual-gated FETs. They have two gate terminals per FET device. A dual-gated FET is really two transistors A and B with a common drain and a common source. One of the two transistors, A, has the common drain connected to its gate, while the other of the two transistors, B, has its gate connected to an outside logic signal. Transistor A is a diode-connected FET, while Transistor B is a logical switch NMOS FET. 
     The bottom-most dual-gated FET device  140  in the FIGURE has its source  142  connected to the drain of a single gated bias FET  150 . The gate of this bias FET  155  is connected to a bias voltage, Vbias. The source of the bias FET is connected to ground  160 . The current through the bias FET  150  is the discharge current  165 . 
     The drain of the first dual-gated FET  140  is connected to the source of the second dual-gated FET  130 . The drain of the first dual-gated FET  140  is also connected to the first gate  132  of this first FET  140 . The drain of the first dual-gated FET  140  is also connected to the input of an inverter  145 . The output of this inverter  145  is connected to the second gate  148  of the dual-gated FET  140 : 
     The drain of the second dual-gated FET  130  is connected to the source of the third dual-gated FET  120 . The drain of the second dual-gated FET  130  is also connected to the first gate  122  of this second FET  130 . The drain of the second dual-gated FET  130  is also connected to the input of an inverter  135 . The output of this inverter  135  is connected to the second gate  138  of the dual-gated FET  130 . 
     The drain of the third dual-gated FET  120  is connected to the source of the fourth dual-gated FET  110 . The drain of the third dual-gated FET  120  is also connected to the first gate  112  of this third FET  120 . The drain of the third dual-gated FET  120  is also connected to the input of an inverter  125 . The output of this inverter  125  is connected to the second gate  128  of the dual-gated FET  120 . 
     The drain of the fourth dual-gated FET  110  is connected to the high voltage node to be discharged  102 . The drain of the fourth dual-gated FET  110  is also connected to the first gate  102  of this fourth FET  110 . The drain of the fourth dual-gated FET  110  is also connected to the input of an inverter  115 . The output of this inverter  115  is connected to the second gate  118  of the dual-gated FET  110 . 
     In this high voltage discharge circuit, the lower voltage caused by the voltage discharging on the drain  142  of the single-gated bias FET  150  causes the first dual-gated FET to turn on. This occurs since the drain  142  of the single-gated bias FET  150  is the same node  142  as the source of the first dual-gated FET  140 . Lowering the voltage at the source  142  of dual-gated FET  140  causes the Vgs, gate to source to exceed the FET threshold voltage, Vt. This results in the turning ON of FET  140  and the discharging of the voltage on the drain  132  of the first dual-gated FET  140 . 
     In this high voltage discharge circuit, the lower voltage caused by the voltage discharging on the drain  132  of the first dual-gated FET  140  causes the output  148  of the first inverter  145  to go high further discharging the drain  132  of the first dual-gated FET  140 . 
     In this high voltage discharge circuit, the lower voltage caused by the voltage discharging on the drain  132  of the dual-gated bias FET  140  causes the second dual-gated FET  130  to turn ON. This occurs since the drain  132  of the first dual-gated bias FET  140  is the same node  132  as the source of the second dual-gated FET  130 . Lowering the voltage at the source  132  of dual-gated FET  130  causes the Vgs, gate to source to exceed the FET threshold voltage, Vt. This results in the turning ON of FET  130  and the discharging of the voltage on the drain  122  of the second dual-gated FET  130 . 
     In this high voltage discharge circuit, the lower voltage caused by the voltage discharging on the drain  122  of the second dual-gated FET  130  causes the output  138  of the second inverter  135  to go high further discharging the drain  122  of the second dual-gated FET  130 . 
     In this high voltage discharge circuit, the lower voltage caused by the voltage discharging on the drain  122  of the dual-gated bias FET  130  causes the third dual-gated FET  120  to turn ON. This occurs since the drain  122  of the second dual-gated bias FET  130  is the same node  122  as the source of the third dual-gated FET  120 . Lowering the voltage at the source  122  of dual-gated FET  120  causes the Vgs, gate to source to exceed the FET threshold voltage, Vt. This results in the turning ON of FET  120  and the discharging of the voltage on the drain  112  of the third dual-gated FET  120 . 
     In this high voltage discharge circuit, the lower voltage caused by the voltage discharging on the drain  112  of the third dual-gated FET  120  causes the output  128  of the third inverter  125  to go high further discharging the drain  112  of the third dual-gated FET  120 . 
     In this high voltage discharge circuit, the lower voltage caused by the voltage discharging on the drain  112  of the dual-gated bias FET  120  causes the fourth dual-gated FET  110  to turn ON. This occurs since the drain  112  of the third dual-gated bias FET  120  is the same node  112  as the source of the fourth dual-gated FET  110 . Lowering the voltage at the source  112  of dual-gated FET  110  causes the Vgs, gate to source to exceed the FET threshold voltage, Vt. This results in the turning ON of FET  110  and the discharging of the voltage on the drain  102  of the fourth dual-gated FET  110 . This drain  102  is also the high voltage node to be discharged. 
     In this high voltage discharge circuit, the lower voltage caused by the voltage discharging on the drain  102  of the fourth dual-gated FET  110  causes the output  118  of the fourth inverter  115  to go high further discharging the drain  102  of the fourth dual-gated FET  110 . 
     The key advantage of the circuit of this invention over the prior art is that it can discharge a high voltage to ground, not to a voltage of N times the Vt, threshold voltage where N are the number of serial connected NMOS FET discharge devices connected in series to ground. The circuit of this invention can achieve the discharging of high voltage to ground, because the inverter logic circuits connected from the drains to the gates of transistor B of the dual-gated NMOS devices allow the voltage to discharge to ground off of the intermediate nodes  112 ,  122 ,  132 ,  142  of the serially connected NMOS FETs in the figure. 
     The discharging of the high voltage through the four dual-gated FETs and the single gated bias FET takes a relatively short time, since the feedback path from the drains of the dual-gated FETs through an inverter back to gate # 2  of the dual-gated FET causes a rapid pull down of the voltage from the drains of each of the series connected dual-gated FETs. In addition, beside the short time it takes to discharge a high voltage from a node, another advantage of this invention is that during discharge, the drain to source voltage Vds, of each NMOS device in the series chain is small {Vds&lt;(High Voltage/4)}. Therefore, latch-up or damage to the individual FETs will not occur. 
     While this invention has been particularly shown and described with Reference to the preferred embodiments thereof, it will be understood by those Skilled in the art that various changes in form and details may be made without Departing from the spirit and scope of this invention.