Abstract:
A high power DC-DC converter uses wide bandgap semiconductor switches and capacitors as a charge pump to convert a DC input to a DC output of a different potential. Each capacitor is connected to the output of one of the stages of the charge pump. A wide bandgap semiconductor switch is connected between the input and output of each stage, and the conductive state of the switch is controlled by a circuit that compares voltage at the input and output of the stage. A multiphase drive alternates drive voltage applied to the capacitors to cause charge to be passed from stage-to-stage through the charge pump.

Description:
BACKGROUND 
       [0001]    The present application relates to high power electrical circuitry. More particularly, the application relates to a DC-DC converter capable of producing kilowatt range DC output power. 
         [0002]    DC-DC converters are used to convert input DC power to output DC power at a different potential level. The DC output power may have the same or opposite polarity and may have either a higher or lower potential than the input DC power. 
         [0003]    High power DC-DC converters can require operation at elevated temperatures. Electrical circuits using silicon semiconductor devices are generally limited to temperatures up to about 125° C. At higher temperatures, charge can leak across PN junctions of silicon devices. Even at temperatures below 125° C., silicon devices that require high power dissipation require a heat sink or active cooling systems, or both, in order to protect the devices from being damaged. Heat sinks and active cooling systems take up space and add weight. 
         [0004]    One commonly used type of DC-DC converter converts the input power from DC to AC, and then convert the AC power back to DC at a different potential and/or polarity. Transformers also add volume and weight to the DC-DC converter. 
         [0005]    There is a continuing demand for electronic circuits that are smaller in size and have fewer components. 
       SUMMARY 
       [0006]    A multistage charge pump converts a DC power input to a DC power output of a different potential by transferring charge from stage-to-stage. Each stage of the charge pump includes an input, an output, a wide bandgap semiconductor switch connected between the input and output, a charge storage capacitor having one terminal connected to the output, and a switch control circuit that controls the conductive state of the switch as a function of potential unbalance between the input and output of the stage. A multiphase driver applies alternating potential drive signals to the other terminal of each capacitor to cause charge to be transferred sequentially from stage-to-stage between the DC power input and the DC power output. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is an electrical schematic diagram of a high power charge pump DC-DC converter. 
           [0008]      FIG. 2  is an electrical schematic diagram of a high power charge pump DC-DC converter having additional charge transfer stages. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]      FIG. 1  shows charge pump  10 , which converts an input voltage Vref to an output voltage Vo which is approximately equal to Vref+2Vdc. Charge pump  10  makes use of high temperature wide bandgap semiconductor switches of, for example, silicon carbide or gallium nitride. Charge pump  10  is capable of power conversion at the kilowatt level and can operate in a wide temperature range from, for example, about −200° C. to about 300° C. 
         [0010]    Charge pump  10  includes input source  12 , charge transfer stages  14 ,  16 , and  18 , H bridge driver  20 , smoothing capacitor Cs, and final output capacitor Cf. 
         [0011]    First stage  14  includes wide bandgap semiconductor switch S 1 , comparator CMP 1 , driver DS 1 , and capacitor C 1 . Switch S 1  is normally an off semiconductor switch having first and second main current carrying electrodes connected to nodes n 0  and n 1 , respectively. Comparator CMP 1  has its positive (+) input connected to node n 0  and its negative (−) input connected to node n 1 . When potential at node n 0  exceeds potential at n 1 , comparator CMP 1  provides an output to driver DS 1 , which in turn provides an input to the control electrode of switch S 1  to cause switch S 1  to turn on. Capacitor C 1  has one terminal connected to node n 1  and its other terminal connected to driver  20  to receive first phase drive signal φ 1 . 
         [0012]    Second stage  16  includes wide bandgap switch S 2 , comparator CMP 2 , driver SD 2 , and capacitor C 2 . The main current carrying electrodes of switch S 2  are connected to nodes n 1  and n 2 . Comparator CMP 2  senses the potential difference between nodes n 1  and n 2 , and turns on switch S 2  when the potential at node n 1  exceeds the potential at node n 2 . Capacitor C 2  has one terminal connected to node n 2 , and the other terminal connected to driver  20 . C 2  receives second phase drive signal φ 2 , which is the inverse of (i.e., 180° out of phase with) drive signal φ 1 . 
         [0013]    Final stage  18  includes wide bandgap semiconductor switch Sf, comparator CMPf, driver DSf, and final or output capacitor Cf. The main current carrying electrodes of switch Sf are connected to nodes n 2  and nf. Comparator CMPf senses potential difference between nodes n 2  and nf, and causes switch Sf to turn on when the potential at node n 2  exceeds the potential at node nf. Capacitor Cf has one terminal connected to node nf, and the other terminal connected to ground. 
         [0014]    Driver  20  is an H bridge circuit formed by transistors Q 1 -Q 4  and drivers DQ 1 -DQ 4 . In the embodiment shown in  FIG. 1 , transistors Q 1 -Q 4  are shown as field effect transistors (FETs), although in other embodiments bipolar transistors and other transistors can be used. The drains of transistors Q 1  and Q 4  are connected to bus voltage Vdc. The source of Q 1  is connected to the drain of Q 2  at node  22 , and the source of Q 3  is connected to the drain of Q 4  at node  24 . The sources of Q 2  and Q 4  are connected to ground. Drive signal φ 1  is produced at node  24  and drive signal φ 2  is produced at node  22 . In some cases, transistors Q 1 -Q 4  of H bridge  20  may also be wide bandgap semiconductor transistors. 
         [0015]    H bridge circuit  20  receives clock signals CLK and  CLK  as inputs. Clock signal CLK is supplied to drivers DQ 1  and DQ 4 , while clock signal  CLK  is provided to drivers DQ 2  and DQ 3 . Clock signals CLK and  CLK  are high frequency 50% duty cycle signals. The clock frequency of signals CLK and  CLK  may be, for example, on the order of 1 MHz. 
         [0016]    When clock signal CLK goes high, transistors Q 1  and Q 4  turn on. At the same time, clock signal  CLK  goes low, causing transistors Q 2  and Q 3  to turn off. As a result, node  22  is connected through transistor Q 1  to Vdc, and node  24  is connected through Q 4  to ground. Thus drive signal φ 1  to capacitor C 1  is at ground potential, and drive signal φ 2  to capacitor C 2  is at Vdc. 
         [0017]    When CLK goes low and  CLK  goes high, transistors Q 1  and Q 4  turn off and transistors Q 2  and Q 3  turn on. As a result, node  22  and drive signal φ 2  go to ground potential. Node  24  and drive signal φ 1  go to potential Vdc. 
         [0018]    Input node n 0  of charge pump  10  is connected to input voltage Vref. When φ 1  switches from Vdc to ground, capacitor C 1  causes the potential at n 1  to decrease. As a result, the potential at node n 0  exceeds the potential at node n 11 , and comparator CMP 1  turns on switch S 1 . This allows charge to be transferred from node n 0  to node n 11 , where it is stored on capacitor C 1 . 
         [0019]    At the same time, the rise in drive signal φ 2  from ground to Vref causes the potential at node n 2  to exceed the potential at node n 1 . As a result, comparator CMP 2  causes switch S 2  to be turned off, and no charge transfer occurs between nodes n 1  and n 2  while drive signal φ 2  is at Vdc. 
         [0020]    The rise in potential at node n 2  caused by drive signal φ 2  going to Vdc causes the potential at node n 2  to be higher than the potential at node nf. As a result, comparator CMPf turns on switch Sf, which allows charge to be transferred from node n 2  to node nf, where it is stored at capacitor Cf. 
         [0021]    When drive signal φ 1  switches from ground to Vdc, the rise in potential at node n 1  results in switch S 1  being turned off by comparator CMP 1 . No charge transfer occurs between nodes n 0  and n 1  while drive signal φ 1  is at Vdc. 
         [0022]    At the same time, the rise in potential of n 1  as a result of drive signal φ 1  corresponds to a reduction in potential of node n 2  as a result of drive signal φ 2  going from Vdc to ground. As a result, the potential at node n 1  exceeds the potential at node n 2 , and comparator CMP 2  turns on switch S 2 . Charge is then transferred from capacitor C 1  to capacitor C 2  through switch S 2 . 
         [0023]    With φ 2  at ground, the potential at node nf exceeds the potential at node n 2 . As a result, switch Sf is turned off by comparator CMPf. 
         [0024]    The cycling of drive signals φ 1  and φ 2  continues, with charge being transferred from node n 0  to n 1  and from node n 2  to nf during one half of the drive cycle, and charge being transferred from node n 1  to n 2  during the other half of the drive cycle. The resulting output voltage Vo at node nf is≈Vref+2Vdc, less voltage loss occurs across switches S 1 , S 2 , and Sf and switches Q 1 -Q 4  when they are turned on. Because these voltage drops are very small, output voltage Vo is≈Vref+2Vdc. 
         [0025]    A larger increase from input voltage Vref to output voltage Vo can be achieved by adding additional pairs of charge transfer stages.  FIG. 2  shows charge pump  10 ′, which is generally similar to charge pump  10  of  FIG. 1 , except that first stage  14 A and third stage  14 B are driven by drive signal φ 1 , while second and fourth stages  16 A and  16 B are driven by drive signal φ 2 . 
         [0026]    Third stage  14 B includes wide bandgap semiconductor switch S 3 , comparator CMP 3 , driver DS 3 , and capacitor C 3 . Similarly, fourth stage  16 B includes wide bandgap semiconductor switch S 4 , comparator CMP 4 , driver DS 4 , and capacitor C 4 . Third stage  14 B is connected to nodes n 2  and n 3 , while fourth stage  16 B is connected to nodes n 3  and n 4 . Final stage  18  is connected between node n 4  and node nf. 
         [0027]    When drive signal φ 1  is low (ground) and drive signal φ 2  is high (Vdc), charge is being transferred from node n 0  to node n 1  through switch S 1 , from node n 2  to node n 3  through switch S 3 , and from node n 4  to node nf through switch Sf. Switches S 2  and S 4  are turned off. 
         [0028]    When drive signal φ 2  is at Vdc and drive signal φ 2  is at ground, switches S 1 , S 3 , and Sf are turned off and switches S 2  and S 4  are turned on. Charge transfer occurs from node n 1  to node n 2  through switch Sf and from node n 3  to node n 4  through switch S 4 . As drive signals φ 1  and φ 2  alternate back and forth between Vdc and ground, charges transferred in a bucket brigade type fashion from input node n 0  to output node nf. 
         [0029]    The output voltage produced by charge pump  10 ′ is equal to Vref+4Vdc minus voltage drops of switches S 1 -S 4  and Sf. Since the voltage drop of each of the wide bandgap semiconductor switches in their on state is very low, Vo≈Vref+4Vdc. 
         [0030]    A further increase in output voltage can be achieved by adding an additional pair of stages. With three stages driven by signal φ 1  and three stages driven by signal φ 2 , output voltage Vo is≈Vref +6Vdc. Each additional pair of φ 1  and φ 2  driven stages adds approximately 2Vdc to the output voltage. 
         [0031]    In one embodiment, capacitors C 1 , C 2  . . . Cf are approximately 100 microfarad capacitors. Smoothing capacitor Cs has a higher capacitance, such as about 1000 microfarad. 
         [0032]    The charge pump disclosed provides DC-to-DC conversion without the need for transformers or other inductors. As a result, a reduction in size and weight can be achieved. The capacitors used in the charge pump generally will consume less space, and weigh less than a transformer that may be used for a DC-DC converter comparable voltage power capability. 
         [0033]    Operation at a higher temperature is possible with circuits that use silicon carbide semiconductor devices. Heat transfer from a body to its surrounding environment by thermal radiation is proportional to T 4 , where T is the body&#39;s temperature. By operating at a higher temperature, switches S 1 -Sf provide increased heat transfer. As a result, smaller, lighter heat sinks can be used, and active cooling systems may be reduced or eliminated. The charge pump of the present invention can handle voltages ranging from several hundred volts to the kilovolt range and power in the kilowatt range, in some cases exceeding 30 kilowatts of output power. This can be achieved while satisfying a demand for smaller size and a reduction in the number of components. Those skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the disclosure.