Abstract:
A semiconductor memory device improves test reliability by suppressing unnecessary leakage component in a USMC test which checks if data is normally transferred by extending a time margin between an active signal input time and a bit line sensing time. The semiconductor memory device includes at least one inner voltage adjusting unit for adjusting an inner voltage for limiting leakage portion that is generated in the semiconductor memory device during the USMC test by using a USMC signal for starting the USMC test and a termination signal for terminating the USMC test. The inner voltage adjusting unit includes a bulk bias voltage adjusting unit for supplying a bulk bias voltage to a cell transistor in the semiconductor memory device.

Description:
FIELD OF INVENTION  
       [0001]     The present invention relates to a semiconductor memory device; and, more particularly, to an apparatus for improving reliability of a USMC(Unlimited Sensing Margin Control) test of a semiconductor memory device and a method thereof.  
       DESCRIPTION OF PRIOR ART  
       [0002]     In general operation of a semiconductor memory device, when a word line is made to be active, a bit line sense amplifier senses a level of a bit line signal by charge-sharing on the bit line based on data that is stored in the cell coupled to the active word line in a predetermined time. That is, the conduction is not maintained for so long time without charge-sharing on the bit line based on data that is stored in the cell coupled to the active word line. However, as the semiconductor memory device is used in the course of time, its probability of malfunction increases. Therefore, semiconductor memory device manufacturers carry out a predetermined test for checking whether data is normally transferred or not by intentionally extending a time margin between an active signal input time and the bit line sensing time than the normal operation case. This is referred to as a USMC (Unlimited Sensing Margin Control) test, hereinafter.  
         [0003]     In this test, the semiconductor memory device that has more leakage current portion on the bit line than a predetermined value may sense wrong data. From this, the semiconductor memory device that can guarantee normal operation for a predetermined time can be determined.  
         [0004]     However, because a threshold voltage Vt of a transistor in the semiconductor memory device is decreased as the semiconductor memory device has a higher speed, the leakage current portion on the bit line is increased, which leads reliability problem for the USMC test result.  
         [0005]     The USMC test described above is for checking if there is excessive leakage current on the bit line. The process for the USMC test is as follows. First, any one of word lines is made to be active. Then, it is checked if data that is outputted from the cell is transferred through the bit line as it should by detecting the level of the bit line after a predetermined time.  
         [0006]     Referring to  FIG. 1 , there is a schematic diagram showing a cell array of the semiconductor memory device, which is divided into the cell array for storing data and a peripheral part for controlling the cell array. It will be described in detail for the USMC test with reference to  FIG. 1 .  
         [0007]     The cell array includes capacitors C 1 , C 2 , C 3 , . . . for storing data, cell transistors T 1 , T 2 , T 3 , . . . for acting as switches, word lines WL 1 , WL 2 , WL 3 , . . . for controlling gate voltages of the cell transistors T 1 , T 2 , T 3 , . . . , bit lines BL, BL/ for acting as paths for data that is outputted from the capacitors C 1 , C 2 , C 3 , . . . through the cell transistors T 1 , T 2 , T 3 , . . . to a sense amplifier  230  and data that is stored to the capacitors C 1 , C 2 , C 3 , . . . through the cell transistors T 1 , T 2 , T 3 , . . . from the sense amplifier  230 , the sense amplifier  230  for detecting the levels of the bit lines BL, BL/, and a bit line equalizing unit for equalizing the levels of the bit line and the bit line-bar BL, BL/ by using a bit line equalization signal BLEQ.  
         [0008]     For example, when the word line WL 1  goes to “H” state to turn on the transistor T 1 , data in the capacitor C 1  is sensed through the bit line. In this case, some portion of charge in the capacitor C 1  is transferred to the bit line through the cell transistor T 1 , which should not make potential change on the bit line-bar but some potential change on the bit line. However, as the threshold voltages of the cell transistors are reduced, leakage current is generated at the cell transistors T 2 , T 3  that should be off, which leads charge is leaked from the capacitors that are coupled to those transistors to affect the potential on the bit line BL and the bit line-bar BL/. Such a leakage portion has a non-negligible effect on the USMC test as the semiconductor memory device has a higher speed and is highly integrated. In other words, because the leakage portion that is generated when the cell transistors that are not related to the USMC test are turned off and the leakage portion that is generated by the transistor in the sense amplifier is increased, the USMC test cannot be performed accurately, which affects the reliability of the USMC test.  
         [0009]      FIG. 2  is a circuit diagram for a USMC test in prior art in which a bulk bias voltage VBB generator  240  of a cell transistor does not use a USMC signal USMC for the USMC test, and a termination signal term. That is, the bulk bias voltage VBB generator that is provided in the substrate of the cell transistor exists separately from a USMC logic circuit  210 . Accordingly, the level of the bulk bias voltage VBB is not changed depending on the test mode. Here, the bulk bias voltage VBB is a voltage that is inputted into the substrate of the cell transistor.  
         [0010]     First, it will be described for the detailed operation of the USMC logic circuit  210  in prior art as shown in  FIG. 3 .  
         [0011]     The active signal atv in  FIG. 3  is a word line signal that has a transition from a “L” level to a “H” level when a row address is inputted into the semiconductor memory device from an external device or a word line is to be selected to refresh the state of data that is stored at the capacitor. That is, the active signal atv does high-transition when the word line signal is made to be active. The USMC signal USMC is a signal for starting the USMC test. That is, when the USMC signal has a transition to the “H” state, the USMC test is started. The termination signal term is a signal for terminating the USMC test. When the term signal has a transition to the “H” state, the sense amplifier operates to start detecting the level of the bit line signal.  
         [0012]     Referring to  FIG. 3 , in the normal operation, both of the USMC signal USMC and the termination signal term are in the “L” state so as to transfer the active signal atv as a sense amplifier active signal sa_atv. That is, in the normal operation, when the word line signal is made to be active, the sense amplifier operates accordingly.  
         [0013]     On the other hand, when the USMC signal has a transition to the “H” state for the USMC test, an output of a NOR gate N 1  has the “L” state regardless of the state of the active signal atv, but an output of a NOR gate N 2  has the “H” state because the termination signal term is not yet active. Consequently, the sense amplifier active signal sa_atv automatically has the “L” state as the USMC signal USMC has a transition to the “H” state. When the termination signal term is made to be active to the “H” state for detecting the level of the bit line after a predetermined time, the output of the NOR gate N 2  goes to the “L” state regardless of the USMC signal USMC and the active signal atv, and the final output, the sense amplifier active signal sa_atv, goes to the “H” state to start detection of the sense amplifier.  
         [0014]      FIG. 4  is an exemplary diagram showing one embodiment of a generator for an RTO signal and an SB signal.  
         [0015]     The generator  220  for the RTO signal and the SB signal receives the sense amplifier active signal sa_atv and the bit line equalization signal bleq. The bit line equalization signal bleq is a signal for pre-charging the bit line and the bit line-bar when the bit line sense amplifier blsa does not sense and is further applied to the generator  220  for the RTO signal and the SB signal to pre-charge the RTO signal and the SB signal to the Vblp level.  
         [0016]     That is, when active, because the bit line equalization signal bleq is in the “L” state, the RTO signal output and the SB signal output are separated from each other. When pre-charge, the bit line equalization signal bleq goes to the “H” state so as to turn on the transistor that receives the bit line equalization signal bleq to its gate, which makes the RTO signal output and the SB signal output pre-charged to the Vblp.  
         [0017]     When the sense amplifier active signal sa_atv goes to the “H” state, the high data level of the cell Vcore is applied to the RTO signal output and the low data level of the cell Vss is applied to the SB signal output.  
         [0018]     In the USMC test, because it is active, the bit line equalization signal bleq goes to the “L” state to separate the RTO signal output from the SB signal output, but the voltage level of the bit line is not detected because the sense amplifier active signal sa_atv is in the “L” state for a predetermined time. After a while, when the termination signal term is inputted, the sense amplifier active signal sa_atv goes again to the “H” state so as to detect the voltage level of the bit line.  
         [0019]     Next, it will be described for the operation of the VBB generator  240  in prior art as shown in  FIG. 5 .  
         [0020]     Serially-coupled PMOS transistors P 1  to P 4  function as resistors. Here, the PMOS transistors P 1 , P 2  that receive the fixed voltage VSS at their gates function as a fixed resistor, and the PMOS transistors P 3 , P 4  that receive the bulk bias voltage VBB function as a variable resistor. That is, as the level of the bulk bias voltage goes down, the resistance of the PMOS transistors P 3 , P 4  is decreased. To the contrary, as the level of the bulk bias voltage VBB arises, the resistance of the PMOS transistor P 3 , P 4  is increased.  
         [0021]     On the other hand, the power voltage VCC is an arbitrary high voltage power that is used for voltage division of the PMOS transistors P 1  to P 4 . By adjusting the resistance of the PMOS transistors P 3 , P 4 , the power voltage VCC is made to have a value to let the input signal of the inverter INV 1  be capable of controlling the operation of a voltage pump VBB_PUMP. That is, when the bulk bias voltage VBB is higher than a target value, the input of the inverter INV 1  is made to go to the “H” state. When the bulk bias voltage VBB arrives at the target value, the input of the inverter INV 1  is made to go to the “L” state. Therefore, when the bulk bias voltage VBB is higher than the target value, the input signal bb_en of the voltage pump VBB_PUMP goes to the “H” state so that the voltage pump VBB_PUMP can operate.  
         [0022]     When the bulk bias voltage VBB decreases to the target value depending on the operation of the voltage pump VBB_PUMP, the gate inputs of the PMOS transistors P 3 , P 4  decreases so as to make the resistance of the PMOS transistors be reduced. Accordingly, the input of the inverter INV 1  goes to the “L” state so as to make the input signal bb_en of the voltage pump VBB_PUMP the “L” state, which stops the operation of the voltage pump VBB_PUMP.  
         [0023]     When the level of the bulk bias voltage VBB goes again up, the resistance of the PMOS transistors P 3 , P 4  increases and, accordingly, the input of the inverter INV 1  goes to the “H” state to perform pumping operation for decreasing the bulk bias voltage VBB.  
         [0024]     As described above, because the conventional voltage pump operates only when the bulk bias voltage VBB is higher than a predetermined value, it is not effective for suppressing leakage current of the cell transistors in the USMC test.  
       SUMMARY OF INVENTION  
       [0025]     It is, therefore, an object of the present invention to provide a semiconductor memory device for improving test reliability by suppressing unnecessary leakage component in a USMC test.  
         [0026]     In accordance with an aspect of the present invention, there is provided a semiconductor memory device for improving reliability of a USMC(Unlimited Sensing Margin Control) test, comprising at least one inner voltage adjusting unit for adjusting an inner voltage for limiting leakage portion that is generated in the semiconductor memory device during the USMC test by using a USMC signal for starting the USMC test and a termination signal for terminating the USMC test.  
         [0027]     In accordance with another aspect of the present invention, there is provided a method for adjusting an inner voltage in a semiconductor memory device for improving reliability of a USMC(Unlimited Sensing Margin Control) test, comprising the steps of a) generating a control signal by using a USMC signal for starting the USMC test and a termination signal for terminating the USMC test; and b) adjusting the inner voltage under control of the control signal to limit leakage portion that is generated in the semiconductor memory device during the USMC test. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0029]      FIG. 1  is a schematic diagram showing a cell array in a semiconductor memory device;  
         [0030]      FIG. 2  is a circuit diagram for a USMC test in prior art;  
         [0031]      FIG. 3  is a USMC logic diagram in prior art;  
         [0032]      FIG. 4  is an exemplary diagram showing one embodiment of a generator for a RTO signal and an SB signal;  
         [0033]      FIG. 5  is a diagram showing a VBB generator in prior art;  
         [0034]      FIG. 6  is a schematic diagram for a USMC test in accordance with the present invention;  
         [0035]      FIG. 7  is a circuit diagram showing a bulk bias voltage generator for a USMC test in accordance with one embodiment of the present invention; and  
         [0036]      FIG. 8  is a circuit diagram showing a bulk bias voltage generator for a USMC test in accordance with another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF INVENTION  
       [0037]     Hereinafter, a data output control circuit for use in a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings.  
         [0038]      FIG. 6  is a schematic diagram for a USMC test in accordance with the present invention, which is similar to the conventional USMC test except that a bulk bias voltage VBB generator  640  further includes a bulk bias voltage adjusting unit to adjust a target level of the bulk bias voltage VBB by using a USMC signal and a termination signal term in a USMC test.  
         [0039]      FIG. 7  is a circuit diagram showing a bulk bias voltage generator for a USMC test in accordance with one embodiment of the present invention.  
         [0040]     The bulk bias voltage generator for the USMC test according to one embodiment of the present invention includes the bulk bias voltage adjusting unit. The bulk bias voltage adjusting unit includes a control signal generating unit  641  for adjusting the level of the bulk bias voltage in the USMC test, and a resistor unit  646  for adjusting a resistance in response to the control signal from the control signal generating unit  641 .  
         [0041]     The control signal generating unit  641  includes an inverter INV 3  receiving the termination signal term, and a NAND gate NAND 1  receiving the output of the inverter INV 3  and the USMC signal. The resistor unit  646  includes a PMOS transistor P 5  between a PMOS transistor P 4  and the ground voltage VSS, and a NMOS transistor N 1  coupled parallel to the PMOS transistor P 5  for using the output of the control signal generating unit  641  as its gate signal. It is desirable to use high resistance long channel PMOS transistors for the PMOS transistors P 1 -P 5 . On the other hand, in order to reduce the turn-on resistance of the NMOS transistor N 1 , it is desirable to use a transistor having a shorter channel length than the PMOS transistors P 1 -P 5  as the NMOS transistor N 1 . It will be described for the operation of the bulk bias voltage generator.  
         [0042]     In the normal operation, because both of the USMC signal USMC and the termination signal term are all “L” state, the output of the control signal generating unit  641  goes to the “H” state so as to make the NMOS transistor N 1  turned on and, accordingly, the current that passed through the PMOS transistors P 3 , P 4  passes through the NMOS transistor N 1  without going through the PMOS transistor P 5 . At this time, the bulk bias voltage VBB generator operates as the conventional case.  
         [0043]     On the other hand, In the USMC test, when the USMC signal USMC goes to the “H” state to make the output of the control signal generating unit  641  be the “L” state, the NMOS transistor N 1  in the resistor unit  646  is turned off and, accordingly, the current that passed through the PMOS transistors P 3 , P 4  goes through the PMOS transistor P 5  to the ground voltage VSS. That is, in the USMC test, the resistance between the node node 1  and the ground voltage is increased to make the voltage level on the node node 1  increase. Accordingly, it makes the threshold point at which the inverter INV 1  recognizes the “H” state be lower so as to have a lower the target level of the bulk bias voltage of the bulk bias voltage pump VBB_PUMP than the conventional target level.  
         [0044]     To the contrary, when it is started to detect the bit line voltage when the USMC test is terminated, the termination signal term goes to the “H” state to make the output of the control signal generating unit  641  be the “H” state and, accordingly, the NMOS transistor N 1  in the resistor unit  646  is turned on to let the bulk bias voltage generator  640  operate normally.  
         [0045]      FIG. 8  is a circuit diagram showing a bulk bias voltage generator for a USMC test in accordance with another embodiment of the present invention, which includes a bulk bias voltage adjusting unit.  
         [0046]     The bulk bias voltage adjusting unit includes a control signal generating unit  642  for adjusting the level of the bulk bias voltage in the USMC test, and a resistor unit  647  for adjusting a resistance in response to the control signal from the control signal generating unit  642 . Here, The bulk bias voltage adjusting unit in  FIG. 8  is similar to the bulk bias voltage adjusting unit in  FIG. 7  except that the PMOS transistor P 5  in the resistor unit  647 , which receives the output of the control signal generating unit  642  that is as same as the control signal generating unit  641  in  FIG. 7 , is coupled parallel to the PMOS transistor P 1 .  
         [0047]     The operation of the bulk bias voltage generator as shown in  FIG. 8  is similar to the operation of the bulk bias voltage generator as shown in  FIG. 7 .  
         [0048]     In the normal operation, because both of the USMC signal USMC and the termination signal term are all “L” state, the output of the control signal generating unit  642  goes to the “H” state so as to make the PMOS transistor P 5  be turned off.  
         [0049]     In the USMC test, when the USMC signal USMC goes to the “H” state to make the output of the control signal generating unit  642  be the “L” state, the PMOS transistor P 5  in the resistor unit  647  is turned on and, accordingly, the voltage level on the node node 2  increase. Accordingly, it makes to reduce the target level of the bulk bias voltage VBB.  
         [0050]     When the USMC test is terminated, the termination signal term goes to the “H” state to make the output of the control signal generating unit  642  be the “H” state and, accordingly, the bulk bias voltage generator  640  operates normally.  
         [0051]     As described above, by making the level of the bulk bias voltage VBB reduced in the USMC test, the leakage component at the cell transistors that are coupled to the inactive word lines can be reduced. Further, because the bulk bias voltage VBB is applied to the bit line transistors or the transistors in the sense amplifier  230  as the bulk bias, the leakage component at this part can be suppressed.  
         [0052]     On the other hand, the bulk bias voltage generators in  FIGS. 7 and 8  are applicable to a negative voltage VBBW generator in which a negative voltage VBBW is generated to apply to the gates of the cell transistors coupled to the inactive word lines in a negative word line scheme. In other words, by using a negative voltage pump VBBW_PUMP instead of the bulk bias voltage pump VBB_PUMP, the leakage component at the cell transistors can be suppressed with those generators in  FIGS. 7 and 8 .  
         [0053]     Further, the leakage component at the cell transistors can be suppressed by adjusting both of the negative voltage VBBW that is applied to the gates of the cell transistors in the negative word line scheme and the bulk bias voltage VBB that is applied to the substrates of the cell transistors.  
         [0054]     Further, the leakage component at the cell transistors can be suppressed by changing the target level of the plate voltage VPP that is applied to the gates of the cell transistors that are coupled to the active word lines in the USMC test. In this case, the plate voltage VPP may be used as the bulk bias voltage of the RTO PMOS transistor of the sense amplifier so that the leakage component at the RTO PMOS transistor can be suppressed by adjusting the level of the plate voltage VPP.  
         [0055]     As described above, the leakage component that is generated at the cell transistors in the USMC test can be suppressed according to the present invention. Further, the leakage component that is generated at the sense amplifier of the semiconductor memory device can be suppressed according to the present invention. Accordingly, the USMC test can be performed accurately.  
         [0056]     The present application contains subject matter related to the Korean patent application No. KR 2004-40321, filled in the Korean Patent Office on Jun. 3, 2004, the entire contents of which being incorporated herein by reference.  
         [0057]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.