Abstract:
An interface comprises a storage device controller that controls data flow from a Serial ATA bus to a storage device. A configurable bridge circuit is configured in one of a plurality of operating modes including a device bridge mode, and converts Parallel ATA information received on a Parallel ATA bus to Serial ATA information output to the Serial ATA bus when in the device bridge mode.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 10/339,897 filed on Jan. 10, 2003. The disclosure of the above application is incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     This invention relates to Serial Advanced Technology Attachment (SATA) input/output (I/O) assemblies. 
     BACKGROUND 
     The Parallel ATA (Advanced Technology Attachment) specification has defined the standard storage interface for PCs since the early 1980s. Parallel ATA provides low cost, broad operating system support, and steady evolution. Over time, parallel ATA has continuously evolved to support higher speed and performance. However, due to several reasons, including performance headroom, cabling issues, and voltage tolerance requirements, a new storage interface known as Serial ATA has recently been created. 
     Serial ATA may combine software transparency, low cost, scalability, and design flexibility to overcome the limitations of parallel ATA. Point-to-point data rates of 1.5 Gbps may be attainable with Serial ATA. Although SATA provides many benefits over PATA, there remains a large installed user-base of PATA compatible storage devices and computers. To continue to use the existing PATA compatible storage devices, bridge devices have been developed to interface PATA devices to SATA compatible computer systems. 
       FIG. 1  shows a conventional computer system  10  that communicates information via a SATA link  11 . The computer system  10  includes a device bridge  12  to interface a PATA storage device  14  to a host controller  16  through a host bridge  18 . The device bridge  12  and the host bridge  18  may each convert PATA formatted information to SATA formatted information and SATA formatted information to PATA formatted information. The device bridge  12  and the host bridge are generally not interchangeable due to differences in the header information that each of the bridges  12  and  18  generate when converting information between the SATA to PATA formats. 
     SUMMARY 
     In one aspect, an interface circuit for interfacing a Parallel ATA bus to a storage device. The interface circuit including a storage device controller in communication with the storage device to control a flow of information between the storage device and a Serial ATA bus. The Serial ATA bus to carry information having a Serial ATA format. A bridge circuit configured as a host bridge to interface between the Serial ATA bus and the Parallel ATA bus. The host bridge to convert Serial ATA information to Parallel ATA information and to convert Parallel ATA information to Serial ATA information. 
     The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram of a conventional interface circuit. 
         FIG. 2  is a block diagram of an aspect of an interface circuit. 
         FIG. 3  is a block diagram of an emulation aspect of an interface circuit. 
         FIG. 4  is a block diagram of a hot plug aspect of an interface circuit. 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
       FIG. 2  shows an aspect of an interface circuit  50  for controlling the communication of streams of information between a PATA compliant bus  54  and a SATA compliant bus  58 . The interface circuit  50  may be implemented in any type of assembly such as on a single semiconductor die and as a multi-chip module. A Complementary Metal Oxide Semiconductor (CMOS) fabrication process is particularly suitable for fabricating the interface circuit  50 , however any type of fabrication process may be used. 
     A hard disk controller  56  controls the flow of information between the SATA compliant bus  58  and a storage device  52 . The storage device  52  may be any device for storing information such as a hard disk drive (HDD) and a CD-ROM. The hard disk controller  56  may be any type of controller that may interface to a SATA compliant bus. The SATA compliant bus  58  is suitable for carrying information that is formatted in accordance with the SATA standard. 
     A bridge circuit  60  is connected between the Serial ATA compliant bus  58  and the Parallel ATA compliant bus  54 . The bridge circuit  60  may be selected to be in a host mode or a device mode in which the bridge circuit operates respectively as a host bridge or a device bridge. In this aspect, the bridge circuit  60  operates as a host bridge to enable the use of low-cost, widely available Parallel ATA connectivity while using a high-speed Serial ATA controller  56  to interface to the storage device  52 . The bridge circuit  60  may receive Serial ATA commands communicated over the Serial ATA compliant bus  58 . The bridge circuit  60  may decode the commands and convert them to Parallel ATA device commands. For responses from the Parallel ATA bus  54 , the bridge circuit  60  may decipher, process, and convert the responses to Serial ATA protocol and communicate the responses over the Serial ATA compliant bus  58 . 
     A mode select input  62  of the bridge circuit  60  may set the operating mode of the bridge circuit  60 . Supported operating modes may include modes such as host mode and device mode. In host mode, the bridge circuit  60  operates as a host bridge. In device mode, the bridge circuit  60  operates as a device bridge. The mode select input  62  is preferably a single digital input and may advantageously be set at any time during the operation of the interface circuit  50 . However, the mode select input  62  may also be implemented as one or more digital and analog inputs or be received via a Universal Asynchronous Receiver-Transmitter (UART). 
       FIG. 3  shows an aspect of an interface circuit  70  for controlling the communication of streams of information between a PATA compliant bus  72  and two or more SATA compliant buses  74 . The interface circuit  70  advantageously supports emulation of master/slave mode for attached storage devices  76  such as hard disk drives (HDDs) and CD-ROMs. The storage devices  76  may be PATA compliant or SATA compliant devices. For storage devices that are PATA compliant, bridge circuits  78  configured for device mode may interface between the SATA compliant buses  74  and PATA compliant buses  80  that connect to the storage devices  76 . The bridge circuits  78  may include a mode select function that is set to device mode, or may be a single-mode bridge device. 
     An emulation circuit  82  may include two or more bridge circuits  84  to emulate master/slave mode for the storage devices  76 . Each of the bridge circuits  84  connects between the PATA compliant bus  72  and corresponding ones of the SATA compliant buses  74 . Each of the bridge circuits  84  may include a mode select input and an emulation select input. 
     The mode select input may receive a mode signal to set the bridge circuit  84  to either a host mode or a device mode. In this aspect, the bridge circuit  84  is preferably set to the host mode. When in host mode, the emulation select input may receive an emulation signal to set the bridge circuit  84  to an emulation state such as master, slave, and master/slave. The bridge circuit  84  emulates a storage device as a function of the emulation state indicated by the emulation signal. 
       FIG. 4  shows an aspect of an interface circuit  100  for controlling the communication of streams of information that flow between PATA compliant buses  102   a  and  102   b  and a SATA compliant bus  104 . The interface circuit  100  is particularly suitable for a hot plugging operation between a host  106  and a storage device  108 . Bridge circuits  110  and  112  correspond to the host  106  and the storage device  108 . Each of the bridge circuits  110  and  112  may include a mode input  114  and a hot plug enable input  116 . The mode input  114  may receive a mode signal to set the operating mode of the corresponding bridge circuit to a host mode or a device mode. The bridge circuits  110  and  112  are preferably configured in host mode and device mode respectively to correspond to the host  106  and the storage device  108 . 
     The hot plug enable input  116  may receive a hot plug signal to enable or disable a hot plug mode. The bridge circuits  110  and  112  may also receive one or more of the hot plug signal and the mode signal via a communication device such as a UART. During hot plug mode, the bridge circuits may monitor the SATA compliant bus  104  to determine whether the SATA compliant bus has been disconnected or connected. For example, the bridge circuits may sense activity on the SATA compliant bus  104  to determine whether a hot plugging operation such as connecting or disconnecting has occurred. 
     In response to detecting a disconnecting operation, a signal may be sent to the operating system associated with the host  106  indicating that the storage device  108  has been disconnected. The bridges  110  and  112  may then monitor the SATA compliant bus  104  for activity such as an out of band (OOB) sequence. If activity is detected on the SATA compliant bus  104 , the operating system may be notified and the bridges  110  and  112  may independently initiate operations to establish a communication link between the host  106  and the storage device  108  such as resetting the PHY associated with each bridge  110  and  112 . 
     A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, a UART may be included in a bridge circuit for communicating information. The UART may receive inputs such as mode select, master/slave emulation, and hot plug enable and communicate those inputs to other circuits in the bridge circuit. Accordingly, other embodiments are within the scope of the following claims.