Abstract:
A class AB output stage includes first (M P ) and a second (M N ) output transistors having sources coupled to first (V DD ) and second reference voltages, respectively, drains coupled to an output ( 13 ), and gates coupled to first ( 11 A) and second ( 12 A) conductors, respectively. Portions of first (I IN1 ) and a second (I IN2 ) input currents are sourced via a first input conductor ( 11 ) and a second input conductor ( 12 ), respectively, into and from sources of first (M 2 ) and second (M 4 ) transistors, respectively. Gates of the first (M 2 ) and second (M 4 ) transistors are coupled to the first and second conductors, respectively. First (V refP ) and second (V refN ) bias voltages are applied to gates of third (M 1 ) and fourth (M 3 ) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates generally to operational amplifiers operable from low supply voltages, and especially to class AB output stages which are operable from supply voltages as low as 1 volt. 
         [0002]    Various known circuits for CMOS amplifier output stages are operable from fairly low supply voltages, i.e., as low as roughly 2 volts, and also are operable over a relatively large supply voltage range. The relevant prior art is believed to include U.S. Pat. No. 6,657,495 “Operational Amplifier Output Stage and Method” issued Dec. 2, 2003 to Ivanov et al. and U.S. Pat. No. 7,088,182 “Class AB Output Stage Circuit with Stable Quiescent Current” issued Aug. 8, 2006 to Ivanov. 
         [0003]    “Prior Art”  FIG. 1  herein shows an operational amplifier  1  including a rail-to-rail differential input stage  2  which feeds into a folded cascode stage  3 . Folded cascode stage  3  supplies a current I IN1  through conductor  11  to one input of a class AB output stage  4 . Folded cascode stage  3  also sinks a current I IN2  through conductor  12  from the other input of class AB output stage  4 . The currents I IN1  and I IN2  are dependent on the differential input voltage Vin + -Vin − . Typically, the magnitude of the threshold voltage V TP  of P-channel transistors is slightly greater than the magnitude of the threshold voltage V TN  of N-channel transistors in a CMOS integrated circuit. Therefore, for a typical CMOS integrated circuit, the minimum supply voltage V DD  at which operational amplifier  1  of  FIG. 1  is operable is equal to the sum of the voltage drops across P-channel transistors  4 F and  4 G and the voltage drop across current source  4 H, which at normal temperatures is in the range from roughly 2.2 volts to 2.5 volts, assuming the lower supply voltage V SS  is at ground. Furthermore, it is believed that no other prior art class AB output stages are capable of operating at voltages less than approximately 1.5 volts. 
         [0004]    There is increasing demand for low-cost, low-power CMOS operational amplifiers which are operable from supply voltages as low as approximately 1 volt and which also are operable over a supply voltage range of at least about 0.9 to 5.0 volts in order to allow power to be supplied by various common batteries. However, no satisfactory solutions to this need have been found in the available literature. All of the closest prior art very-low-voltage class AB output stages are characterized by poor linearity, limitation of the output current, poor stability of the class AB current, and/or unacceptable complexity. It would be highly desirable to have a class AB output stage for a CMOS amplifier operating at a supply voltage as low as 1.0 volts or less using current state-of-the-art CMOS manufacturing processes. 
         [0005]    Thus, there is an unmet need for a CMOS class AB output stage that is operable at power supply voltages at least as low as approximately 0.9 to 1.0 volts. 
         [0006]    There also is an unmet need for a CMOS class AB output stage that is operable at power supply voltages as low as approximately 0.9 to 1.0 volts and also is operable at a power supply voltage as high as approximately 5 volts. 
         [0007]    There also is an unmet need for a CMOS class AB output stage that is operable at power supply voltages as low as approximately 0.9 to 1.0 volts and which is not characterized by poor linearity and/or limitations of the amount of output current and/or poor stability of the output current. 
         [0008]    There also is an unmet need for a CMOS class AB output stage that is operable at power supply voltages as low as approximately 0.9 to 1.0 volts and which has a simple circuit configuration less complex than the closest prior art low voltage class AB output stages. 
       SUMMARY OF THE INVENTION 
       [0009]    It is an object of the invention to provide a CMOS class AB output stage that is operable at power supply voltages at least as low as approximately 0.9 to 1.0 volts. 
         [0010]    It is another object of the invention to provide a CMOS class AB output stage that is operable at power supply voltages as low as approximately 0.9 to 1.0 volts and also is operable at a power supply voltage as high as approximately 5 volts. 
         [0011]    It is another object of the invention to provide a CMOS class AB output stage that is operable at power supply voltages as low as approximately 0.9 to 1.0 volts and which is not characterized by poor linearity and/or limitations of the amount of output current and/or poor stability of the output current. 
         [0012]    It is another object of the invention to provide a CMOS class AB output stage that is operable at power supply voltages as low as approximately 0.9 to 1.0 volts and which has a circuit configuration less complex than the closest prior art low voltage class AB output stages. 
         [0013]    Briefly described, and in accordance with one embodiment, the present invention provides a class AB output stage includes a first output transistor (M P ) having a source coupled to a first reference voltage (V DD ), a drain coupled to an output ( 13 ), and a gate coupled to a first conductor ( 11 A), and a second output transistor (M N ) having a source coupled to a second reference voltage (V SS ), a drain coupled to the output conductor, and a gate coupled to a second conductor ( 12 A). A portion of a first input current (I IN1 ) flows into a first input conductor ( 11 ) and the source of a first transistor (M 2 ) having a gate coupled to the first conductor and a portion of a second input current (I IN2 ) flows out of the source of a second transistor (M 4 ) having a gate coupled to the second conductor through a second input conductor ( 12 ). A first bias voltage (V refP ) is applied to a gate of a third transistor (M 1 ) having a source coupled to the first input conductor and a drain coupled to the second conductor, and a second bias voltage (V refN ) is applied to a gate of a fourth transistor (M 3 ) having a source coupled to the second input conductor and a drain coupled to the first conductor. 
         [0014]    In one embodiment, the invention provides circuitry including a class AB output stage ( 4 - 1 ), the class AB output stage including a first output transistor (M P ) having a first electrode coupled to a first reference voltage (V DD ), a second electrode coupled to an output conductor ( 13 ), and a control electrode coupled to a first conductor ( 11 A), and a second output transistor (M N ) having a first electrode coupled to a second reference voltage (V SS ), a second electrode coupled to the output conductor ( 13 ), and a control electrode coupled to a second conductor ( 12 A). A first transistor (M 2 ) has a first electrode coupled to a first input conductor ( 11 ) conducting a first input current (I IN1 ), a second electrode coupled to the first conductor ( 11 A), and a control electrode coupled to the first conductor ( 11 A). A second transistor (M 4 ) has a first electrode coupled to a second input conductor ( 12 ) conducting a second input current (I IN2 ), a second electrode coupled to the second conductor ( 12 A), and a control electrode coupled to the second conductor ( 12 A). A third transistor (M 1 ) has a first electrode coupled to the first input conductor ( 11 ), a second electrode coupled to the second conductor ( 12 A), and a control electrode coupled to a first bias voltage conductor ( 17 ) to receive a first bias voltage (V refP ). A fourth transistor (M 3 ) has a first electrode coupled to the second input conductor ( 12 ), a second electrode coupled to the first conductor ( 11 A), and a control electrode coupled to a second bias voltage conductor ( 18 ) to receive a second bias voltage (V refN ). A first bias circuit ( 15 ) produces the first bias voltage (V refP ) and a second bias circuit ( 16 ) produces the second bias voltage (V refN ). A folded cascode stage ( 3 ) coupled between the first (V DD ) and second (V SS ) reference voltages produces the first (I IN1 ) and second (I IN2 ) input currents in response to an input signal. 
         [0015]    In a described embodiment, the first (M 2 ) and third (M 1 ) transistors have threshold voltages lower in magnitude than a threshold voltage of the first output transistor (M P ), and the second (M 4 ) and fourth (M 3 ) transistors have threshold voltages lower in magnitude than a threshold voltage of the second output transistor (M N ) in order to allow the folded cascode stage ( 3 ) to produce the first (I IN1 ) and second (I IN2 ) input currents. 
         [0016]    In a described embodiment, the first output transistor (M P ) is a P-channel transistor, the second output transistor (M N ) is a N-channel transistor, the first electrodes are drains, the second electrodes are sources, and the control electrodes are gates. The first (M 2 ) and third (M 1 ) transistors are P-channel transistors and the second (M 4 ) and fourth (M 3 ) transistors are N-channel transistors. The first bias circuit ( 15 ) includes a P-channel fifth transistor (M Pref ) having a source coupled to the first reference voltage (V DD ) and a gate and drain coupled to a first current source (I P ) by the first reference voltage conductor ( 17 ) to produce the first bias voltage (V refP ) thereon. The second bias circuit ( 15 ) includes a N-channel sixth transistor (M Nref ) having a source coupled to the second reference voltage (V SS ) and a gate and drain coupled to a second current source (I N ) by the second reference voltage conductor ( 18 ) to produce the second bias voltage (V refN ) thereon. 
         [0017]    In a described embodiment, the first current source (I P ) is scaled with respect to a channel width of the first output transistor (M P ) so as to match a desired value of a quiescent current in the first output transistor (M P ), and current produced by the second current source (I N ) is scaled with respect to a channel width of the second output transistor (M N ) so as to match a desired value of a quiescent current in the second output transistor (M N ). The first bias voltage (V refP ) corresponds to a gate voltage of the first output transistor (M P ), and the second bias voltage (V refN ) corresponds to a gate voltage of the second output transistor (M N ). 
         [0018]    In a described embodiment, the first ( 15 ) and second ( 16 ) bias circuits adjust the first (V refP ) and second (V refN ) bias voltages in response to changes in an output voltage (Vout) produced on the output conductor ( 13 ) to stabilize quiescent current in the output transistors. 
         [0019]    In a described embodiment, the class AB output stage includes a fifth transistor (M 2 B) having a first electrode coupled to the first input conductor ( 11 ), a second electrode coupled to the second conductor ( 12 A), and a control electrode coupled to the first conductor ( 11 A), and also includes a sixth transistor (M 4 B) having a first electrode coupled to the second input conductor ( 12 ), a second electrode coupled to the first conductor ( 11 A), and a control electrode coupled to the second conductor ( 12 A). A channel width of the first transistor (M 2 A) is approximately 10 times a channel width of the fifth transistor (M 2 B) and a channel width of the second transistor (M 4 A) is approximately 10 times a channel width of the sixth transistor (M 4 B). The fifth transistor (M 2 B) has a threshold voltage lower in magnitude than the threshold voltage of the first output transistor (M P ), and the sixth transistor (M 4 B) has a threshold voltage lower in magnitude than the threshold voltage of the second output transistor (M N ). The first output transistor (M P ) and the fifth transistor (M 2 B) are P-channel transistors, the second output transistor (M N ) and the sixth transistor (M 4 B) are N-channel transistors, the first electrodes are drains, the second electrodes are sources, and the control electrodes are gates. The first (M 2 A), third (M 1 ), and fifth (M 2 B) are PNP transistors the first electrodes of which are emitters, of the second electrodes of which are collectors, and the control electrodes of which are bases. 
         [0020]    In one embodiment, first body electrode biasing circuitry (D 1 ,I 1 ) is coupled to body electrodes of the first (M 2 A) and third (M 1 ) transistors to reduce threshold voltages thereof, and second body electrode biasing circuitry (D 2 ,I 2 ) is coupled to body electrodes of the second (M 4 A) and fourth (M 3 ) transistors to reduce threshold voltages thereof. In one embodiment, the class AB output stage ( 4 - 3 ) includes a P-channel fifth transistor (M 2 B) having a first source coupled to the first input conductor ( 11 ), a drain coupled to the second conductor ( 12 A), and a gate coupled to the first conductor ( 11 A), and also includes a N-channel sixth transistor (M 4 B) having a source coupled to the second input conductor ( 12 ), a drain coupled to the first conductor ( 11 A), and a gate coupled to the second conductor ( 12 A). A body electrode of the fifth transistor (M 2 B) is coupled to the first body electrode biasing circuitry (D 1 ,I 1 ), and a body electrode of the sixth transistor (M 4 B) is coupled to the second body electrode biasing circuitry (D 2 ,I 2 ). 
         [0021]    In one embodiment, the invention provides a method of operating a class AB output stage ( 4 - 1 ) at a low supply voltage (V DD -V SS ), including providing a first output transistor (M P ) having a first electrode coupled to a first reference voltage (V DD ), a second electrode coupled to an output conductor ( 13 ), and a control electrode coupled to a first conductor ( 11 A), and a second output transistor (M N ) having a first electrode coupled to a second reference voltage (V SS ), a second electrode coupled to the output conductor ( 13 ), and a control electrode coupled to a second conductor ( 12 A), sourcing at least a portion of a first input current (I IN1 ) flowing in a first input conductor ( 11 ) through first and second electrodes of a first transistor (M 2 ) having a control electrode coupled to the first conductor ( 11 A) and sinking at least a portion of a second input current (I IN2 ) flowing in a second input conductor ( 12 ) through first and second electrodes of a second transistor (M 4 ) having a control electrode coupled to the second conductor ( 12 A), and applying a first bias voltage (V refP ) to a control electrode of a third transistor (M 1 ) having a first electrode coupled to the first input conductor ( 11 ) and a second electrode coupled to the second conductor ( 12 A), and applying a second bias voltage (V refN ) to a control electrode of a fourth transistor (M 3 ) having a first electrode coupled to the second input conductor ( 12 ) and a second electrode coupled to the first conductor ( 11 A). In a described embodiment, the method includes scaling current produced by the first current source (I P ) with respect to a channel width of the first output transistor (M P ) so as to match a desired value of a quiescent current in the first output transistor (M P ), and scaling current produced by the second current source (I N ) with respect to a channel width of the second output transistor (M N ) so as to match a desired value of a quiescent current in the second output transistor (M N ). The first bias voltage (V refP ) is produced so that it corresponds to a gate voltage of the first output transistor (M P ), and the second bias voltage (V refN ) is produced so that it corresponds to a gate voltage of the second output transistor (M N ). 
         [0022]    In one embodiment, the invention provides a low voltage class AB output stage including a first output transistor (M P ) having a first electrode coupled to a first reference voltage (V DD ), a second electrode coupled to an output conductor ( 13 ), and a control electrode coupled to a first conductor ( 11 A), and a second output transistor (M N ) having a first electrode coupled to a second reference voltage (V SS ), a second electrode coupled to the output conductor ( 13 ), and a control electrode coupled to a second conductor ( 12 A), means for sourcing at least a portion of a first input current (I IN1 ) flowing in a first input conductor ( 11 ) through first and second electrodes of a first transistor (M 2 ) having a control electrode coupled to the first conductor ( 11 A) and for sinking at least a portion of a second input current (I IN2 ) flowing in a second input conductor ( 12 ) through first and second electrodes of a second transistor (M 4 ) having a control electrode coupled to the second conductor ( 12 A), and means for applying a first bias voltage (V refP ) to a control electrode of a third transistor (M 1 ) having a first electrode coupled to the first input conductor ( 11 ) and a second electrode coupled to the second conductor ( 12 A), and applying a second bias voltage (V refN ) to a control electrode of a fourth transistor (M 3 ) having a first electrode coupled to the second input conductor ( 12 ) and a second electrode coupled to the first conductor ( 11 A). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a schematic diagram of a prior art operational amplifier including a class AB output stage 
           [0024]      FIG. 2  is a schematic diagram of a basic implementation of the present invention. 
           [0025]      FIG. 3  is a schematic diagram of another implementation of the present invention. 
           [0026]      FIG. 4  is a schematic diagram of another embodiment of the present invention. 
           [0027]      FIG. 5  is a schematic diagram of yet another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0028]      FIG. 2 , which illustrates a basic implementation of the present invention, shows amplifier circuitry  10 - 1  including the above described prior art folded cascode circuit  3  coupled to a class AB output stage  4 - 1  according to the present invention. Output stage  4 - 1  includes P-channel output transistor M P  having its source connected to V DD  and its gate connected to conductor  11 A and its drain connected to conductor  13 , which conducts output voltage Vout. Conductor  13  also is connected to the drain of N-channel output transistor M N . The source of output transistor M N  is connected to V SS , which may be at ground. The gate of output transistor M N  is connected to conductor  12 A. An output current lout flows through conductor  13 . Output transistors M P  and M N  both have “standard” threshold voltages. 
         [0029]    Conductor  11 A is connected to the gate and drain of a “low” threshold voltage (LVT) P-channel transistor M 2  which has its source connected by conductor  11  to one output of folded cascode circuit  3 , details of which are shown in  FIG. 1 . Similarly, conductor  12 A is connected to the gate and drain of a low threshold voltage (indicated by “LVT” in the drawings)-channel transistor M 4  which has its source connected by conductor  12  to the other output of folded cascode circuit  3 . Conductor  11  also is connected to the source of low threshold voltage P-channel transistor M 1 , the drain of which is connected by conductor  12 A to the gate and drain of low threshold voltage transistor M 4  and the gate of output transistor M N . Conductor  12  also is connected to the source of low threshold voltage-channel transistor M 3 , the drain of which is connected by conductor  11 A to the gate and drain of low threshold voltage transistor M 2  and the gate of output transistor M P . 
         [0030]    The gate of low threshold voltage transistor M 1  is connected by conductor  17  to a bias circuit  15  which includes P-channel transistor M Pref  and current source I P . Transistor M Pref  has its source connected to V DD  and its gate and drain connected by conductor  17  to a first terminal of current source I P , the other terminal of which is connected to V SS . A bias voltage V refP  is provided on conductor  17 . Similarly, the gate of low threshold voltage transistor M 3  is connected by conductor  18  to a reference circuit  16  which includes N-channel transistor M Nref  and current source I N . Transistor M Nref  has its source connected to V SS  and its gate and drain connected by conductor  18  to a first terminal of current source I N , the other terminal of which is connected to V DD . A bias V refN  is produced on conductor  18 . 
         [0031]    The bias voltages V refP  and V refN  generated by bias voltage circuits  15  and  16  at the gates of transistors M 1  and M 3 , respectively, must appropriately correspond to or “match” (but not ordinarily be equal to) the gate voltages of output transistors M P  and M N , respectively, when they are operating at their lowest current levels, i.e., at their quiescent current levels. (The drain to source voltages of transistor M Pref  and output transistor M P  are not matched.) The current sources I P  and I N  match the minimum (quiescent) current values in output transistors M P  and M N , respectively, in the sense that transistor geometries of the current sources are appropriately scaled with respect to geometries of output transistors M P  and M N , so as to match the desired value of the quiescent currents in output transistors M P  and M N . The minimum current value I P  flows through transistor M Pref  and the minimum current value I N  flows through transistor M Nref , and similarly, the gate to source voltage V GS  of transistor M Pref  matches the V GS  of transistor M P , and the gate to source voltage V GS  of M Nref  matches V GS  of transistor M N  when they are both conducting the minimum (quiescent) current at the same time. 
         [0032]    Output voltage Vout and output current lout are controlled in response to the input currents I IN1  and I IN2  produced by folded cascode circuit  3 . The shoot-through current of class AB output stage  4 - 1  is determined by the reference voltages VrefP and VrefN, which can be generated by conventional reference voltage circuits as shown or by more complex reference voltage circuitry which tracks and adjusts VrefP and VrefN in response to changes in V DD  and/or Vout in order to make the quiescent current in the output transistors more stable with respect to power supply voltages and/or output voltage variations. 
         [0033]    In order to have adequate voltage “head room” to allow I IN1  to be sourced by P-channel transistors  3 C and  3 G ( FIG. 1 ) of folded cascode stage  3  and also to allow N-channel transistors  3 F and  3 B of folded cascode stage  3  to “sink” I IN2 , it is necessary that the threshold voltages V TP  and V TN  of P-channel transistor M 2  and N-channel transistor M 4 , respectively, be smaller than the threshold voltages of the corresponding output transistors M P  and M N , respectively. In some CMOS manufacturing processes, both low threshold voltage (indicated on the drawings by “LVT”) P-channel transistors and low threshold voltage N-channel transistors are available. However, in some other CMOS manufacturing processes low threshold voltage transistors are not available, but other options in accordance with the present invention are available as in subsequently described  FIGS. 4 and 5 . 
         [0034]    Transistor M P  usually has a larger threshold voltage than output transistor M N  by, for example, about 200 millivolts, and the gate of transistor M P  will be at nearly the same voltage as conductor  12  through which folded cascode output current I IN2  flows. If the V GS  voltage of output transistor M P  needs to increase but the voltage at the gate thereof is below the voltage of conductor  12  during normal operation, class AB stage  4 - 1  becomes non-operational. 
         [0035]    The minimum value of V DD  at which class AB output stage  4 - 1  of  FIG. 2  is operable, assuming V SS  is at ground, is given by the expression 
         [0000]        V   DD (min)= V   GSP +( V   GSN   −V   GSN ( LVT ), 
         [0000]    which can be as low as 0.9 volts at normal integrated circuit operating temperature. The voltage on the source of transistor M 4  is equal to V GSN −V GSN (LVT), and the source-drain voltage of transistor M 3  is equal to zero. The voltage on conductor  12  through which I IN2  flows is equal to the difference between the threshold voltages V GSN −V GSN (LVT) of M N  and M 4 . Similarly, the voltage on conductor  11  through which I IN1  flows is equal to the difference between the threshold voltages V GSP −V GSP (LVT) of M P  and M 2 . 
         [0036]    A complete shutdown of one of output transistors M P  and M N  in  FIG. 2  can occur when the other output transistor conducts a large current. For example, assuming a very large input current I IN2  (which flows through N-channel transistors  3 F and  3 B of folded cascode stage  3 ) and also assuming a small current I IN1 , the large value of I IN2  pulls the gate and drain of transistor M 2  down to a low voltage level. All of current I IN1  flows through transistors M 2  and M 3  and the transistors  3 F and  3 B of folded cascode circuit  3 . This means that the gate of transistor M 4 , and hence the gate of transistor M N , are very low and therefore transistor M N  is completely turned off. There is no current through transistor M 1  because under these conditions all of the current I IN1  flows through transistor M 2 . Consequently, there is no current available to flow through transistor M 4  to generate a gate voltage on conductor  12 A to keep output transistor M N  at least slightly turned on. 
         [0037]    Referring next to  FIG. 3 , class AB output stage  4 - 2  of amplifier circuitry  10 - 2  is similar to that in class AB output stage  4 - 1  of  FIG. 2 , except that P-channel transistor M 2  of  FIG. 2  has in effect been “split” into two low threshold voltage transistors including transistor M 2 A and transistor M 2 B in  FIG. 3  . Both of transistors M 2 A and M 2 B have their gates connected to conductor  11 A and their sources connected to conductor  11 . The W/L (channel-width-to-channel-length) ratio of transistor M 2 A is much larger, e.g. 10 times larger, than that of transistor M 2 B. The drain of transistor M 2 A is connected to conductor  11 A. The drain of transistor M 2 B is connected to conductor  12 A. Similarly, N-channel transistor M 4  of  FIG. 2  has been “split” into two low threshold voltage transistors, including transistor M 4 A and transistor M 4 B in  FIG. 3 , both of which have their gates connected to conductor  12 A and their sources connected to conductor  12 . The W/L (channel-width-to-channel-length) ratio of transistor M 4 A is much larger, e.g. 10 times larger, then that of transistor M 4 B. The drain of transistor M 4 A also is connected to conductor  12 A. The drain of transistor M 4 B is connected to conductor  11 A. Transistors M 1 , M 2 , M 2 A, M 2 B, M 4 A, and M 4 B are low threshold voltage transistors, as indicated by “LTV” in the drawings. 
         [0038]    In class AB output stage  4 - 2  of  FIG. 3 , under the condition that I IN2  is very large, the input current I IN1  is split between transistors M 2A  and M 2B , so there is a small amount of I IN1  flowing through transistor M 2A  to the gate of transistor M N  and the folded cascode circuit  3 . That portion of I IN1  produces a voltage on conductor  12 A which keeps keep transistor M N  turned slightly on. Analogous operation occurs to keep output transistor M P  turned slightly on if I IN1  is very large and I IN2  is very small. 
         [0039]    The currents I IN1  and I IN2  which determine the output voltage Vout in turn are determined by the differential input voltage (Vin + -Vin − ) applied to the input stage  2  of amplifier  1  in  FIG. 1 . Vout typically also is determined by a main external feedback loop (not shown) of the operational amplifier. In class AB stage  4 - 2  of  FIG. 3 , the smallest of the two currents of the output transistors is determined in response to “local feedback” through the path including transistor M 2A  for output transistor M P  and through the path including transistor M 4A  for output transistor M N . This local feedback results in the benefit of keeping the quiescent current of the stages stable without affecting the output voltage Vout and output current lout defined by the operational amplifier input voltage. 
         [0040]      FIG. 4  shows a class AB output stage  4 - 3  which is useful in the case wherein the CMOS manufacturing process can not provide a low threshold voltage P-channel transistor but can provide a PNP transistor having a V BE  voltage (base-emitter voltage) which is less than the P-channel transistor threshold voltage V TP . Class AB output stage  4 - 3  of  FIG. 4  is essentially the same as output stage  4 - 2  of  FIG. 3 , except that Class AB output stage  4 - 3  of  FIG. 4  includes PNP transistors Q 2 A and Q 2 B in place of P-channel transistors M 2 A and M 2 B, respectively, of  FIG. 3 . The bases of PNP transistors Q 2 A and Q 2 B are connected to conductor  11 A. The emitter of transistor Q 2 A is connected directly to conductor  11 , and the emitter of transistor Q 2 B is coupled by a degeneration resistor R E  to conductor  11 . The collector of transistor Q 2 A is connected to conductor  11 A, and a drain of transistor Q 2 B is connected to conductor  12 A. The difference in the approximately 0.6 volt V BE  voltage of PNP transistors Q 2 A and Q 2 B and the approximately 0.9 volt V TP  threshold voltage of output transistor M P  provides the voltage headroom needed for transistors  3 C and  3 G of folded cascode circuit  3  to generate the current I IN1 . The operation of the class AB output stage  4 - 3  of  FIG. 4  is essentially the same as the class AB output stage  4 - 2  of  FIG. 3 . 
         [0041]      FIG. 5  shows a class AB output stage  4 - 4  that is useful in the case wherein the CMOS manufacturing process can not provide low threshold voltage P-channel or N-channel transistors or bipolar transistors having lower V BE  voltages which are lower in the magnitude than the corresponding CMOS transistor threshold voltages. Referring to  FIG. 5 , P-channel transistors M 1 , M 2 B, and M 2 A and the N-channel transistors M 3 , M 4 B, and M 4 A are connected as in  FIG. 3 , but the body electrodes of P-channel transistors M 1 , M 2 B, and M 2 A are connected by conductor  21  to the anode of a diode D 1  having its anode connected to V DD  through which a bias current I 1  flows. (Alternatively, the bias voltage produced on conductor  21  could instead be produced by some other suitable reference voltage circuit.) Similarly, the body electrodes of N-channel transistors M 3 , M 4 B, and M 4 A are connected by conductor  22  to the anode of a diode D 2  (or other suitable reference voltage circuit) having its anode connected to V SS  through which a bias current I 2  flows. This provides a forward voltage bias of the PN junctions between the body regions and source regions of the MOS transistors and decreases their threshold voltages, thereby allowing class AB output stage  4 - 4  of  FIG. 5  to operate essentially the same as output stage  4 - 3  of  FIG. 3 . 
         [0042]    In contrast to prior art, the present invention provides a class AB output stage having simple, efficient, highly linear class AB current control operation from a low supply voltage less than approximately 1 volt. Furthermore, present invention provides local feedback loops around output devices of a class AB output stage for controlling minimum currents in output transistors M P  and M N . 
         [0043]    While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. For example, the invention could be useful in an integrated circuit in which output transistors M P  and M N  are bipolar transistors if their V BE  (base-emitter) voltages are greater than the threshold voltages of the corresponding low threshold voltage transistors.