Abstract:
A high-frequency input circuit for two inputs has a pair of first and second pi variable attenuation circuits each composed of three P-I-N diodes, some of which are shared by both of the circuits. The P-I-N diodes serve as attenuator elements in the attenuation circuits and also as switching elements for switching between the first and second attenuation circuits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a high-frequency input circuit such as that often used in television tuners, which has a circuit for switching high frequencies and a variable attenuation circuit for controlling the amount of signals transmitted and more particularly to such a high-frequency input circuit including P-I-N diodes which serve as switching elements in the high-frequency switching circuit and also as variable resistance elements for controlling the amount of signal transmission. 
     2. Prior Art 
     Conventional high-frequency input circuits for such devices as television tuners have a high-frequency switching circuit between two inputs and a variable attenuation circuit for controlling the amount of input signals transmitted. The switching circuit typically has switching diodes, and the variable attenuation circuit often has P-I-N diodes, with the circuits arranged independently for each input. Accordingly, the number of diodes used is quite large, resulting in a large losses due to diode resistance in the forward direction. The greater the number of diodes, the greater the number of parts necessary for applying bias voltages to the diodes, with the result that the overall circuit arrangement is expensive to construct. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a high-frequency input circuit for two inputs which is simple in construction. 
     Another object of the present invention is to provide a high-frequency input circuit for two inputs which is devoid of the traditional switching diodes. 
     Still another object of the present invention is to provide a high-frequency input circuit for two inputs which has P-I-N diodes that constitute a variable attenuator and serves also as switching diodes. 
     Still another object of the present invention is to provide a high-frequency input circuit for two inputs which includes a minimum number of diodes with resultant reduced loss of diode resistance in the forward direction. 
     According to the present invention, a pair of pi variable attenuation circuits each composed of three P-I-N diodes serving as attenuator elements and also as switching elements for switching the attenuation circuits is provided, with some of the P-I-N diodes being shared by the attenuation circuits. 
     The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawing which shows a preferred embodiment by way of an illustrative example. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The sole FIGURE is a circuit diagram of a high-frequency input circuit for two inputs which is constructed in accordance with an embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A high-frequency input circuit illustrated in the drawing comprises a first pi circuit having P-I-N diodes D 1 , D 2  and D 3  for controlling input signals from a first input terminal 1, and a second pi circuit having P-I-N diodes D 4 , D 5  and D 3  for controlling input signals from a second input terminal 2, the first and second circuits being connected in parallel to each other with the diode D 3  shared by both of the circuits. Each of the first and second circuits receives the respective input signals and controls the amount of signal transmitted by signals supplied to SW terminals 3 or 4, a power supply terminal 5 and an AGC (automatic gain control) terminal 6. 
     With such a circuit arrangement, to allow signals from the first input terminal 1 to pass and to block signals from the second terminal 2, the SW terminal 3 is grounded and voltages such as 15 V, 7 V and 8 V (in the illustrated embodiment) are applied to the SW terminal 4, the AGC terminal 6, and the power supply terminal 5, respectively. As a result, the P-I-N diode D 1  is short-circuited, and the P-I-N diodes D 2 , D 5 , D 4  and D 3  are cut off. The input signals from the input terminal 1 are allowed to pass through the P-I-N diode D 1  without being attenuated to an output terminal 7, while the input signals from the input terminal 2 are blocked by the P-I-N diode D 4 . 
     To variably attenuate the input signals from the input terminal 1, the voltage applied to the AGC terminal 6 is reduced gradually from 7 V with the potentials at the SW terminals 3, 4 and the power supply terminal 5 being left as they are. The voltage at the emitter of a transistor T 1 , that is, the voltage V 4  at the anode of the P-I-N diode D 1  is reduced and the current flowing therethrough is likewise reduced, so that the diode D 1  has an increased resistance. The diode D 1  is now shifted from the condition in which it is short-circuited to the condition in which it is conductive. As the voltage at the AGC terminal 6 is lowered, the emitter voltage of the transistor T 1 , that is, the anode voltage V 4  and cathode voltage V 3  of the P-I-N diode D 1  are lowered until they are below the bleeder voltage formed by resistors R 5 , R 3 , R 4 , R 6  and R 7 , that is, the anode voltages V 1  and V 2  of the P-I-N diodes D 2  and D 3 , whereupon the latter are shifted from the cut-off to the conductive condition with their resistances being gradually reduced. 
     Thus, the input signals from the input terminal 1 can be attenuated as desired by the voltage applied to the AGC terminal 6. During this time, the P-I-N diodes D 5  and D 4  remain cut off regardless of the AGC voltage. 
     To allow the signals from the second input terminal 2 to pass and to block the signals from the input terminal 1, the SW terminal 4 is grounded and voltages such as 15 V, 7 V and 8 V are applied respectively to the SW terminal 3, the AGC terminal 6 and the power supply terminal 5. As a result, the P-I-N diode D 4  is short-circuitted, and the P-I-N diodes D 2 , D 5 , D 3  and D 1  are cut off. The input signals from the input terminal 2 are allowed to pass through the P-I-N diode D 4  without being attenuated to the output terminal 7, while the input signals from the input terminal 1 are blocked by the P-I-N diode D 1 . 
     To attenuate the input signals from the input terminal 2, the voltage at the AGC terminal 6 is lowered gradually from 7 V with the potentials at the SW terminals 3, 4 and the power supply terminal 5 remaining as they are. The voltage at the emitter of the transistor T 1 , that is, the anode voltage V 4  of the P-I-N diode D 4  is reduced and the current flowing therethrough is likewise reduced, so that the diode D 4  has an increased resistance and is now shifted from the condition in which it is conductive. As the voltage at the AGC terminal 6 is lowered, the emitter voltage of the transistor T 1 , that is, the anode voltage V 4  and cathode voltage V 5  of the P-I-N diode D 4  are lowered until they are below the bleeder voltage formed by the resistors R 5 , R 3 , R 4 , R 6  and R 7 , that is, the anode voltages V 2  and V 1  of the P-I-N diodes D 3  and D 5 , whereupon the P-I-N diodes D 3  and D 5  are shifted from the cut-off to the conductive condition with their resistances being reduced. Thus, the input signals from the input terminal 2 can be attenuated as desired by the voltage applied to the AGC terminal 6. During this time, P-I-N diodes D 2  and D 1  remain cut off regardless of the AGC voltage. 
     In the drawing, the capacitors designated at C 1  -C 8  are coupling capacitors and bypass capacitors, the resistors R 1  -R 9  are current-setting resistors and bias resistors, and L 1  -L 3  designates choke coils. 
     Representative values for the parts illustrated in the drawing are as follows: 
     D 1  -D 5  : 1SV82 (TOSHIBA) 
     T 1  : 2SC1622 (NEC) 
     C 1  -C 8  : 1 (nF) 
     R 1 ,R 2  : 330 (Ω) 
     R 3  : 400 (Ω) 
     R 4  : 500 (Ω) 
     R 5 ,R 6  : 1.2 (KΩ) 
     R 7  : 150 (Ω) 
     R 8  : 3.3 (KΩ) 
     R 9  : 470 (Ω) 
     With the arrangement according to the present invention, only one P-I-N diode D 1  or D 4  is inserted at a time in a signal transmission path, reducing a loss due to diode resistance connected in series. With a minimized loss, the HF input circuit of the present invention finds effective use for VHF, UHF and higher frequency bands.