Abstract:
In one embodiment, a high speed bi-directional driver/receiver is provided. When a first component driving data onto a bi-directional bus switches to receiving data from the bus, a second component drives the last logic value received back onto the bus. The first component then disengages its driver circuit and engages a center-tapped line termination circuit, but in order to avoid glitches, the line termination is engaged at a controlled slew rate. The controlled slew rate is generated through a combination of variably sized transistors connected with a voltage source and a charge accumulation node. By controlling which transistors are turned on, the rate at which the node accumulates a charge can be adjusted. When the termination circuit is to be activated, the charge, which is accumulating at a controlled rate, is connected to the gate of the termination transistors, thereby controlling the change in impedance of the termination resistors to avoid voltage glitches on the transmission line. In one embodiment, slew rate control circuitry may be shared between a compensated driver control and a compensated termination control to provide compensated slew rate control to both the drivers and the line termination.

Description:
FIELD OF THE INVENTION 
     The present disclosure pertains to the field of signal transfer between components. More particularly, the present disclosure pertains to slew rate control of line termination devices used on bi-directional transmission lines. 
     BACKGROUND OF THE INVENTION 
     Termination techniques are employed to improve the signal quality of communications between components by reducing signal degradation due to transmission line artifacts such as reflection or ringing. One termination technique is known as source termination. 
     Source termination is illustrated in FIG. 1 a . In source termination, a transmission line,  113 , is terminated through use of a resistance,  115 , at the driver or source end,  110 , of the transmission line. Typically this resistance is provided by the active device in the driver. When a signal is transmitted by a driver,  112 , it propagates along the transmission line until it reaches a receiver,  114 . A reflection occurs at the receiver end of the transmission line,  111 , due to an impedance discontinuity and the reflected signal propagates back along the transmission line in a direction toward the driver. When the reflected signal reaches the driver, it is absorbed by the source terminator,  115 . 
     One problem with source termination, is that it limits the frequency at which signals can be transmitted, since a driver must wait for previous signal reflections to propagate before transmitting new signals. If a new signal is transmitted before the reflections die down, signal degradation due to jitter may result. 
     An alternative technique is called center-tapped termination (CTT). The CTT technique is illustrated in FIGS. 1 b  and  1   c . CTT is used to absorb or avoid reflections at the receiver end of the transmission line,  121 , by providing two equal resistances: one,  126 , tied to a voltage source VCC and the other,  127 , tied to a ground voltage source. Thus the receiver end of the transmission line is biased to a central voltage of VCC/2. 
     Since a component,  130  or  131 , on a bi-directional transmission line,  133 , may act as a receiver at one time and as a driver at another time, the CTT device  135  may be turned off when the component is acting as a driver  132 , and the CCT device  136  may be turned on when the component is acting as a receiver  134 . 
     One problem with this technique is that during the time when receiving devices are turning on their termination CTT devices and a driver is turning off its CTT devices a glitch may occur. A graph of the voltage levels on a transmission line as seen by a receiver is shown in FIG. 2. A glitch,  202 , results from a new CTT device turning on as the old driver turns off. When the driver turns off the line may tend to float to the bias voltage level of VCC/2. One danger is that receivers on the transmission line may mistake the glitch,  202 , for a new valid signal level,  204 , transmitted by the new driver. 
     Another technique used to improve signal quality is known as slew rate control. An example of one prior method, discussed in U.S. Pat. No. 5,977,790, is shown in FIG.  3 . In the circuit shown, a signal, SEL, is used to select between two driver circuits. One of the driver circuits employs devices M 1  and M 2  to drive the voltage accumulated at PAD to the same logic level as the value received at the input, DATA. The other driver circuit employs devices M 5  and M 6  to drive the desired voltage accumulated at PAD, but through a resistance, RT, thereby producing a selected slew rate, which is different than that of the first driver circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings. 
     FIG. 1 a  shows a source termination technique. 
     FIG. 1 b  shows a center-tapped termination technique. 
     FIG. 1 c  shows center-tapped termination on a bi-directional transmission line. 
     FIG. 2 shows a graph of the voltage level seen on a transmission line as the direction of transmission switches, producing a voltage glitch. 
     FIG. 3 shows a prior art driver with slew rate selection. 
     FIG. 4 shows one embodiment of a bi-directional driver/receiver device with compensated slew rate control circuitry. 
     FIG. 5 shows one embodiment of drivers and terminators for use in a bi-directional driver/receiver device. 
     FIG. 6 a  shows one embodiment of a compensated slew rate control circuit for controlling driver circuitry in a bi-directional driver/receiver device. 
     FIG. 6 b  shows one embodiment of a compensated slew rate control circuit for controlling terminator circuitry in a bi-directional driver/receiver device. 
     FIG. 6 c  shows one embodiment of a compensated slew rate control circuit for controlling driver and terminator circuitry in a bi-directional driver/receiver device using the circuits disclosed in FIGS. 6 a  and  6   b.    
     FIG. 7 shows one detailed embodiment of a bi-directional driver/receiver device with some slew rate control circuitry reused for both drivers and terminators. 
     FIG. 8 shows another embodiment of a bi-directional driver/receiver device with compensated slew rate control circuitry. 
     FIG. 9 shows another embodiment of drivers and terminators for use in a bi-directional driver/receiver device. 
     FIG. 10 shows one embodiment of a compensated slew rate control circuit for controlling terminator circuitry in a bi-directional driver/receiver device. 
     FIG. 11 shows another embodiment of a compensated slew rate control circuit for both drivers and terminators in a bi-directional driver/receiver device with some reuse of slew rate control circuitry. 
     FIG. 12 shows another embodiment of a bi-directional driver/receiver device with compensated slew rate control circuitry. 
     FIG. 13 shows another embodiment of drivers and terminators for use in a bi-directional driver/receiver device. 
     FIG. 14 a  shows another embodiment of a compensated slew rate control circuit for controlling driver circuitry in a bi-directional driver/receiver device. 
     FIG. 14 b  shows another embodiment of a compensated slew rate control circuit for controlling terminator circuitry in a bi-directional driver/receiver device. 
     FIG. 14 c  shows a compensated slew rate control circuit including driver compensated slew rate control,  1410 , and terminator compensated slew rate control,  1420 , for use in a bi-directional driver/receiver device without reuse of slew rate control circuitry. 
     FIG. 15 a  shows an alternative compensated slew rate control circuit including driver compensated slew rate control,  1410 , and terminator compensated slew rate control,  1520 , for use in a bi-directional driver/receiver device, which allows for some reuse of slew rate control circuitry. 
     FIG. 15 b  details one embodiment of a compensated slew rate control circuit,  1520 , for controlling terminator circuitry in a bi-directional driver/receiver device with some reuse of the slew rate control circuitry of driver compensated slew rate control,  1410 . 
     FIG. 16 shows one embodiment of a computer system comprising a plurality of components, each component having a slew rate control circuit for controlling terminator circuitry. 
     FIG. 17 shows one possible method for switching transmission direction of a bi-directional transmission line with slew rate controlled activation of line termination. 
    
    
     DETAILED DESCRIPTION 
     These and other embodiments of the present invention may be realized in accordance with the following teachings and it should be evident that various modifications and changes may be made in the following teachings without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense and the invention measured only in terms of the claims. 
     A process, voltage and temperature (PVT) compensated slew rate control is disclosed for turning on and turning off line terminators. Through its use, consistent performance targets may be realized across generational process differences and various operating conditions. In addition, sharing of PVT compensated slew rate generation circuitry between a driver control generation block and a termination control generation block is disclosed. Benefits that may result from use of these techniques include reduction of the circuit area required, improvement of signal quality and synchronization of slew rates for drivers and terminators. 
     FIG. 4 depicts portions of an embodiment of a bi-directional driver/receiver device  400  with compensated slew rate control circuitry  401 . The control signals generated in control generation block  401  are used to selectively engage and disengage drivers and terminators  402  at PVT compensated slew rates. 
     The drivers and terminators  402  are connected with a transmission line  403  to transmit signals to or receive signals from other devices (not shown). These other devices may have similar or dissimilar process or thermal characteristics. Transmission line  403  may represent a wire or a conductive trace in a printed circuit board, a multi-chip module, a layer of an integrated circuit, a bus, a package or some other device. The PVT slew rate compensated drivers and terminators may be part of a central processing unit, a cache memory subsystem, a memory controller, a graphics subsystem, or some other device. 
     Slew rate control block  401  receives a driver enable signal, EN; a data signal, DATA; a termination enable signal, TEN; resistance adjustment or impedance adjustment selectors for controlling the number of p-type transistors, RP 0  and RP 1 , or n-type transistors, RN 0  and RN 1 , activated in the driver; and a selector, TSEL, to adjust the termination impedance relative to the driver. The slew rate control block also receives slew adjustment selectors, SH[ 0 - 1 ] and SL[ 0 - 1 ]. From these inputs, slew rate control block  401  produces slew rate controlled compensation inputs for the drivers CP 0 , CP 1 , CN 0 , and CN 1 , and for the terminators, PT and NT, in block  402 . In response to these slew rate controlled compensation inputs, driver/terminator block  402  engages or disengages the selected drivers or terminators to interact with transmission line  403 . 
     FIG. 5 illustrated one embodiment of a circuit implementing drivers  532  and terminators  535  for use in a bi-directional driver/receiver device. Driver/terminator block  502  receives slew rate controlled compensation inputs CP 0  and CP 1  to tune the impedance and control the rate at which the p-type transistors of the driver are engaged or disengaged. Likewise, slew rate controlled compensation inputs CN 0  and CN 1 , tune the impedance and control the rate at which the n-type transistors of the driver are engaged or disengaged. The inputs PT and NT control the rate at which the terminators are engaged or disengaged. Transistor sizes, Kp, Jp and Ip for the p-type devices, and Kn, Jn, and In for the n-type devices may be selected empirically to provide desired combinations of impedance and speed. 
     Typically, as the drivers are engaged, the terminators are disengaged. One embodiment provides for independent control of driver and terminator slew rates during engagement or disengagement or both. One possible set of circuits, which can produce these slew rate controlled compensation inputs is shown in FIGS. 6 a  and  6   b.    
     FIG. 6 a  illustrates a compensated slew rate control circuit  610  to receive data and enable signals, DATA and EN, for turning on compensated driver circuit  532  to transmit data on a transmission line. Compensated slew rate control circuit  610  also receives resistance adjustment selectors for controlling the number and sizes of p-type transistors, RP 0  and RP 1 , or n-type transistors, RN 0  and RN 1 , made active in the driver. 
     Compensated slew rate control circuit  610  also receives high active slew adjustment selectors, SH[ 0 - 1 ], and low active slew adjustment selectors, SL[ 0 - 1 ], to adjust the rate at which driver transistors will be activated. When the p-type drivers are activated, a charge accumulates at up-slew node, US, due to the gate capacitance of the driver and according to which of the n-type devices are selected by SH 0  and SH 1 . Accordingly, the speed at which node, US, is pulled down through the resistance selected by SH 0  and SH 1  determines the rate at which the p-type transistors in the driver are activated. Similarly, the rate at which a charge accumulates at down-slew node, DS, according to the resistance selected by low active slew adjustment selectors SL 0  and SL 1 , determines the rate at which the n-type transistors in the driver are activated. Thus, from these inputs, slew rate control block  401  produces slew rate controlled compensation inputs CP 0 , CP 1 , CN 0 , and CN 1 . 
     FIG. 6 b  discloses a slew rate control circuit  620  for controlling terminator circuitry  535  in a bi-directional driver/receiver device. According to the resistance selected by SH 0  and SH 1 , the voltage level at node, US, is pulled down at a controlled rate and hence the p-type termination transistor controlled by control signal, PT, is activated at a controlled rate. Likewise, the voltage level at node, DS, is pulled up at a rate determined by a resistance selected by SL 0  and SL 1  and hence the n-type termination transistor controlled by control signal, NT, is activated at a controlled rate. Of course it should be clear to one skilled in the art of circuit design that the slew rates of deactivation could be controlled is a similar manner. It should also be clear that the circuit shown could be modified in implementation details without departing from the subject matter claimed by the applicant. 
     FIG. 6 c  shows one possible embodiment of a compensated slew rate control circuit  601  for controlling driver and terminator circuitry through combining the compensated slew rate control circuit  610  for controlling driver circuitry with a slew rate control circuit  620  for controlling terminator circuitry. 
     FIG. 7 discloses another detailed embodiment of a bi-directional driver/receiver device with compensated slew rate control circuitry for both drivers and terminators. Compensated slew rate control circuit  701  makes use of the same slew rate control circuitry for both the driver controls, CP 0 , CP 1 , CN 0  and CN 1 , and the terminator controls, PT and NT, to activate the drivers and terminators of block  702  at controlled rates. 
     FIG. 8 illustrates another embodiment of a bi-directional driver/receiver device  800  with compensated slew rate control circuitry  801  for controlling compensated drivers and compensated terminators  802  connected with transmission line  803 . 
     FIG. 9 details one possible embodiment of drivers  932  and terminators  935  for use in a bi-directional driver/receiver device such as the one shown in FIG.  8 . In block  902 , p-type transistor sizes, Kp, Jp, Ip and Hp, and the n-type transistor sizes, Kn, Jn, In, and Hn, may be selected to provide desirable impedance and speed combinations for various processes, and operating conditions. Impedance of driver outputs and terminators can be controlled independently through selection of compensation control signals, CP 0 , CP 1 , CN 0  and CN 1 , and PT 0 , PT 1 , NT 0  and NT 1  respectively. 
     FIG. 10 details one possible embodiment of a compensated slew rate control circuit  1020  for controlling terminator circuitry  935  in a bi-directional driver/receiver device. The compensation control circuitry of block  1020  receives termination enable signal, TEN, for turning on compensated terminator circuit  935 . Compensated slew rate control circuit  1020  also receives resistance adjustment selectors for controlling the number and sizes of p-type transistors, RP 0  and RP 1 , or n-type transistors, RN 0  and RN 1 , that are made active. The termination select signal, TSEL, permits resistance adjustment selectors to be used differently than in the driver compensation circuitry  610  by effectively shifting the signals by one bit. 
     Compensated slew rate control circuit  1020  also receives high active slew adjustment selectors, SH[ 0 - 1 ], and low active slew adjustment selectors, SL[ 0 - 1 ], to adjust the rate at which terminator transistors will be activated. Again, the speed at which node, US′, is pulled down through the resistance selected by SH 0  and SH 1  determines the rate at which the p-type transistors in termination circuitry  935  are activated. Similarly, the rate at which a charge accumulates at down-slew node, DS′, according to the resistance selected by low active slew adjustment selectors SL 0  and SL 1 , determines the rate at which the n-type transistors in termination circuitry  935  are activated. Thus, from these inputs, slew rate control block  801  produces slew rate controlled compensation inputs PT 0 , PT 1 , NT 0 , and NT 1 . 
     FIG. 11 details another embodiment of a compensated slew rate control circuit  1101 for both drivers and terminators in the bi-directional driver/receiver device of FIG. 8 with some reuse of slew rate control circuitry to control the rates at which drivers  932  and terminators  935  are activated. Of course it would be clear to one skilled in the art, that the deactivation rates of either or both sets of devices could be controlled in a similar manner. It would also be clear that the functionality implemented herein with NAND gates and NOR gates could be implemented in a variety of ways—pass gates for example. These and other possible modifications could be made by those skilled in the art without departing from the subject matter claimed by the applicant as the invention. 
     FIG. 12 shows yet another embodiment of a bi-directional driver/receiver device  1200  with compensated slew rate control circuitry  1201  to control drivers and terminators  1202  connected with transmission line  1203 . 
     FIG. 13 illustrates details of the drivers and terminators, which are suitable for use in bi-directional driver/receiver device of FIG.  12 . The sizes, Kp and Kn, of default driver transistors may be determined empirically for suitability of use with the fastest anticipated process, temperature and voltage characteristics. Similarly, the sizes, Jp and Jn, of default terminator transistors may be empirically determined by the fastest anticipated process and operating conditions. The other transistor sizes may be binary-weighted to allow 2 n  total impedance combinations to be selected using n selection control signals. Therefore, termination circuitry  1335  provides for 2 4  or 16 impedance selections and driver circuitry  1332  provides for 2 5  or 32 impedance selections. The default devices, controlled by CPA and CNA for the drivers and PTA and NTA for the terminators, represent the highest active impedance selection and will always be activated when the corresponding p-type or n-type transistors are activated. 
     FIG. 14 a  shows one embodiment of a compensated slew rate control circuit  1410  for controlling driver circuitry  1332  in the bi-directional driver/receiver device of FIG.  12 . 
     FIG. 14 b  shows one embodiment of a compensated slew rate control circuit  1420  for controlling terminator circuitry  1335  in the bi-directional driver/receiver device of FIG.  12 . Again, compensated slew rate control circuit  1420  provides for shifting of resistance adjustment selectors by one bit so to use combinations differently in termination compensation circuitry  1420  than in driver compensation circuitry  1410 . The speed at which node, US′, is pulled down through the resistance selected by SH[ 0 - 4 ] determines the rate at which the p-type transistors in termination circuitry  1335  are activated. Similarly, the rate at which a charge accumulates at down-slew node, DS′, according to the resistance selected by low active slew adjustment selectors SL[ 0 - 4 ], determines the rate at which the n-type transistors in termination circuitry  1335  are activated. Thus, from these inputs, slew rate control circuitry  1420  produces slew rate controlled compensation inputs PT[ 0 - 3 ], NT[ 0 - 3 ], PTA and NTA. 
     FIG. 14 c  diagrams a compensated slew rate control circuit  1401  comprising driver compensated slew rate control  1410  and terminator compensated slew rate control  1420  circuitry in a bi-directional driver/receiver device without reuse of compensated slew rate circuitry. 
     FIG. 15 a  shows an alternative compensated slew rate control circuit  1501 comprising driver compensated slew rate control  1410  and terminator compensated slew rate control  1520  in a bi-directional driver/receiver device, the current embodiment providing for some reuse of compensated slew rate circuitry. 
     FIG. 15 b  details one embodiment of a compensated slew rate control circuit  1520  for controlling terminator circuitry  1335  in a bi-directional driver/receiver device with some reuse of compensated slew rate circuitry. The up-slew accumulation node, US, of compensated slew rate control circuit  1410  is connected with the pre-drive NAND and NOT gates instead of connecting them with a common ground. The down-slew accumulation node, DS, of the compensated slew rate control circuit  1410  is connected with the predrive NOR and NOT gates instead of connecting them with Vcc. Therefore the speed at which node, US, is pulled down through the resistance selected by SH[ 0 - 4 ] determines the rate at which the p-type transistors in termination circuitry  1335  are activated, and the rate at which a charge accumulates at down-slew node, DS, according to the resistance selected by low active slew adjustment selectors SL[ 0 - 4 ], determines the rate at which the n-type transistors in termination circuitry  1335  are activated 
     FIG. 16 illustrates one embodiment of a computer system including a multiple components, each having a slew rate control circuit for controlling the rate at which terminator circuitry is engaged. Of course, it should be noted that is would be possible to assemble such a computer system having only one component, a central processing unit (CPU) for example, having a slew rate control circuit for controlling the engagement of terminators. Other components could include: receivers, which could always remain terminated; or drivers, which could simply be disabled without activating any termination circuitry; or numerous other components using termination techniques known in the art, which do not include slew rate controlled activation or deactivation. 
     FIG. 16 depicts three components, which have slew rate controlled termination: a memory controller  1621 , a CPU  1630 , and a cache  1631 . These components as well as other components and communication structures have been illustrated by way of example and not limitation. CPU  1630 , is connected with transmission line  1633  to transmit or receive signals to or from cache  1631 . CPU  1630  is also connected with transmission line  1623  to transmit or receive signals to or from memory controller  1621 . Memory controller  1621  is also connected with local memory  1610  and with transmission line  1633  to transmit or receive signals to or from cache  1631 . Transmission lines,  1623  or  1633 , could either or both be conductive lines or traces, which are part of  1600 , and  1600  could be a multi-chip module, or a single die, or an assembly of components on a printed circuit board, or any other reasonable device, assembly or combination of assemblies used in the art. 
     FIG. 17 shows one possible method for switching a transmission direction of a bi-directional transmission line with slew rate controlled activation of line termination. This embodiment of the method illustrates slew rate controlled activation but could also include slew rate controlled deactivation. A first driver that is prepared to transmit a final signal and to relinquish control of the transmission line or lines, would be in Switch-bus-state-D and would proceed to transmit the last signal,  1701 , and release control of the transmission line,  1702 . A first receiver, needing to transmit signals as a driver on the transmission line, would be in Switch-bus-state-R and would proceed to receive the last transmitted signal,  1711 , and request control of the transmission line. The first driver would then proceed to postdrive the transmission line,  1703 , to the same logic level as the last signal transmitted,  1701 . The first receiver would proceed to deactivate termination circuits,  1713 , and predrive the transmission line at a controlled slew rate,  1714 , to the same logic level that the first driver is postdriving the transmission line,  1703 . The first driver would proceed to activate its termination circuitry at a controlled slew rate,  1704 , and deactivate its driver circuits,  1705 . At this point, the first driver is ready to receive,  1706 , and the first receiver is ready to transmit,  1715 . The first receiver proceeds to transmit signals,  1716 , becoming a second driver, and the first driver receives the signals transmitted,  1707 , becoming a second receiver. This continues until the second driver is ready to transmit a last signal and relinquish control of the transmission line, moving to Switch-bus-state-D, or the second receiver needs to transmit signals as a driver on the transmission line, moving to Switch-bus-state-R. 
     Although several embodiments are specifically illustrated and described herein, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. For example, CTT has been described and illustrated, but certainly slew rate control can be applied to activation of other types of termination circuitry. Slew rate control during deactivation could also be used for termination circuitry. Additionally, even though compensated control circuitry of a certain type was illustrated, other types of compensated control circuitry, predrive circuitry, or other activation or deactivation technologies could be used in conjunction with slew rate control.