Abstract:
A method for fabricating a semiconductor lighting chip includes steps: providing a substrate with an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a second semiconductor layer and an active layer located between the first semiconductor layer and the second semiconductor layer; dipping the epitaxial layer into an electrolyte to etch surfaces of the epitaxial layer and form a number of holes on the epitaxial layer; and forming electrodes on the epitaxial layer.

Description:
1. TECHNICAL FIELD 
       [0001]    The disclosure generally relates to a method for fabricating semiconductor lighting chips. 
       2. DESCRIPTION OF RELATED ART 
       [0002]    In recent years, due to excellent light quality and high luminous efficiency, light emitting diodes (LEDs) have increasingly been used as substitutes for incandescent bulbs, compact fluorescent lamps and fluorescent tubes as light sources of illumination devices. 
         [0003]    The LED generally includes a lighting chip, which includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer subsequently formed on a substrate. When a voltage is applied between the n-type semiconductor layer and the p-type semiconductor layer, hole-electron capture will happen at the active layer, and energy is released in the form of light. However, part of the light emitted by the active layer will be reflected by an interface between the lighting chip and the external environment, therefore reducing light extraction efficiency of the lighting chip. 
         [0004]    Therefore, a method for fabricating a semiconductor lighting chip with satisfied light extraction efficiency is desired to overcome the above described shortcoming. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0006]      FIG. 1  is a diagram showing a first step of a method for fabricating a semiconductor lighting chip according to an embodiment of the present disclosure. 
           [0007]      FIG. 2  is a diagram showing a second step of a method for fabricating a semiconductor lighting chip according to an embodiment of the present disclosure. 
           [0008]      FIG. 3  is a diagram showing a third step of a method for fabricating a semiconductor lighting chip according to an embodiment of the present disclosure. 
           [0009]      FIG. 4  is a diagram showing a fourth step of a method for fabricating a semiconductor lighting chip according to an embodiment of the present disclosure. 
           [0010]      FIG. 5  is a diagram of the fourth step in  FIG. 4 , but showing in another aspect. 
           [0011]      FIG. 6  is an isometric view of a semiconductor lighting chip, after the fourth step in  FIG. 4 . 
           [0012]      FIG. 7  is a diagram showing a fifth step of a method for fabricating a semiconductor lighting chip according to an embodiment of the present disclosure. 
           [0013]      FIG. 8  is a diagram showing a sixth step of a method for fabricating a semiconductor lighting chip according to an embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    An embodiment of a method for fabricating semiconductor lighting chips will now be described in detail below and with reference to the drawings. 
         [0015]    Referring to  FIG. 1 , a wafer  10  is firstly provided. The wafer  10  includes a substrate  20  and an epitaxial layer  30  formed on the substrate  20 . Material of the substrate  20  can be selected from a group consisting of sapphire, SiC, Si, and GaN. In this embodiment, the substrate  20  is made of sapphire, and a thickness of the substrate  20  is about 430 μm. The epitaxial layer  30  is formed on the substrate  20  by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HYPE). The epitaxial layer  30  includes a first semiconductor layer  32 , an active layer  34  and a second semiconductor layer  36  subsequently grown on the substrate  20 . When a voltage is applied between the first semiconductor layer  32  and the second semiconductor layer  36 , hole-electron capture will happen at the active layer  34 , and energy is released in the form of light. In this embodiment, the first semiconductor layer  32  is an n-type GaN layer, which has a thickness of about 4 μm. The active layer  34  is a multiple quantum well (MQW) GaN layer, which has a thickness of about 0.1 μm. The second semiconductor layer  36  is a p-type semiconductor layer, which has a thickness of about 0.125 μm. For reducing dislocation defects of the epitaxial layer  30 , a buffer layer  40  is formed between the epitaxial layer  30  and the substrate  20  to reduce lattice mismatching between the epitaxial layer  30  and the substrate  20 . The buffer layer  40  is made of material with a lattice constant matching that of the epitaxial layer  30 . In this embodiment, the buffer layer  40  is made of AIN, which has a thickness of about 20 nm. 
         [0016]    Referring to  FIG. 2 , etching regions are defined on an upper surface of second semiconductor layer  36  by photolithography and the etching regions are then removed to form a number of grooves  300 . The grooves  300  extends from an upper surface of the second semiconductor layer  36  downward to the interior of the first semiconductor layer  32  to expose part of the first semiconductor layer  32 . 
         [0017]    Referring to  FIG. 3 , a cladding layer  50  is formed on a bottom surface of each groove  300  by vacuum evaporation or sputtering, therefore covering the part of the first semiconductor layer  32  exposed to external environment. In this embodiment, the cladding layer  50  is made of SiO 2  for preventing the first semiconductor layer  32  from being etched to a rough surface in the following process. In this embodiment, an upper face of the cladding layer  50  is lower than the active layer  34 . 
         [0018]    Referring to  FIGS. 4-6 , the wafer  10  is put into an electrolyte  60  to etch the epitaxial layer  30 . The wafer  10  functions as an anode, and a conductive bar  62  made of Pt is inserted in the electrolyte  60  and functions as a cathode. For securing the wafer  10 , the wafer  10  is clamped by a fixture  70  before dipped into the electrolyte  60 . The fixture  70  includes a first clamping section  72  and a second clamping section  74  spaced from the first clamping section  72 . The wafer  10  is sandwiched between the first clamping section  72  and second clamping section  74  with first clamping section  72  abutting against the upper surface of the second semiconductor layer  36  and the second clamping section  74  abutting against the bottom surface of the substrate  20 . In this embodiment, the first clamping section  72  acts as a positive electrode, from which a current is capable of being transmitted to the electrolyte  60  through the epitaxial layer  30 . When a voltage is applied to the cathode and the anode, the electrolyte  60  is activated by current and etches the epitaxial layer  30 . Therefore, a number of holes  302  are formed in lateral surfaces of the epitaxial layer  30 , as referring to  FIG. 8 . A diameter of the holes  302  is configured between 1 nm and 100 nm to reduce totally reflection of light in the lateral surfaces of the epitaxial layer  30 , therefore increasing light extraction efficiency of the lighting chip. A depth of the holes  302  can be adjusted by controlling an etching time of the epitaxial layer  30 . The longer the epitaxial layer  30  is etched, the deeper the holes  302  are. In addition, a value of the applied voltage and a doping concentration of the epitaxial layer  30  have outstanding effects to the formation of the holes  302 . With the increase of the applied voltage or the doping concentration of the epitaxial layer  30 , more holes  302  will be formed when the epitaxial layer  30  is etched by the electrolyte  60 . However, the value of the applied voltage can not exceed a certain critical value, or else an electro-polishing phenomenon will happen and holes cannot be effectively formed. Besides, the value of the applied voltage can not be too low, or else the electrolyte  60  can not effectively etch the epitaxial layer  30 . Preferably, the value of the applied voltage is between 10V and 20V. In this embodiment, the electrolyte  60  is made of oxalic acid, which can effectively react with the epitaxial layer  30  to form holes  302  in the lateral surfaces of the epitaxial layer  30 . Because the upper surfaces of the second semiconductor layer  36  and the first semiconductor layer  32  is protected by the first clamping section  72  and the cladding layer  50  respectively, the holes  302  are only formed in the lateral surface of the epitaxial layer  30 . 
         [0019]    After the etching process, the wafer  10  is taken out from the fixture  70  and cleaned. Referring to  FIG. 7 , the cladding layer  50  in the grooves  300  is removed to expose the first semiconductor layer  32 . Because of the etching of the electrolyte  60 , rough surfaces  310  is formed on the lateral sides of each grooves  300 . The rough surface  310  extends from the upper surface of the second semiconductor layer  36  to the upper surface of the cladding layer  50 . 
         [0020]    Referring to  FIG. 8 , a number of second electrodes  82  and first electrodes  80  are formed on the upper surfaces of the second semiconductor layer  36  and the first semiconductor layer  32  respectively, and then the substrate  20  is cut along the grooves  300  by laser cutting or mechanical cutting, therefore dividing the wafer  10  into a number of individual lighting chips. Because of the covering of the cladding layer  50 , the upper surface of the first semiconductor layer  32  remains smooth, and a connection between the first electrode  80  and the first semiconductor layer  32  is strengthened. Similarly, because of the covering of the first clamping section  72 , the surface of the second semiconductor layer  36  remains smooth, and a connection between the second electrode  82  and the second semiconductor layer  36  is strengthened. Therefore, a nonuniform current distribution caused by uneven surfaces is prevented. In addition, for distributing current uniformly from the second electrode  82  to the second semiconductor layer  36 , a transparent conductive layer (not shown) is previously formed on the upper surface of the second semiconductor layer  36  before the second electrode  82  is formed. The transparent conductive layer can be made of Indium tin oxide (ITO) or Ni/Au alloy permitting transition of the light. 
         [0021]    Because a number of holes  302  are formed on the lateral surfaces of the semiconductor lighting chip, the holes  302  can reduce the totally reflection of light in the lateral surfaces of the lighting chip. Therefore, more light will travel to external environment and light extraction efficiency of the semiconductor lighting chip can be improved. 
         [0022]    Besides, the electrolyte  60  is made of oxalic acid, which can effectively etch the GaN layer and form a number of holes  302  in the lateral surfaces of the epitaxial layer  30  without a mask. Therefore, the manufacture of the semiconductor lighting chip is relatively simple. 
         [0023]    In addition, in the etching by the electrolyte  60 , the wafer  10  can be effectively secured by the fixture  70 . After the etching is finished, the wafer  10  can be released by loosening the fixture  70 . Therefore, the fixture  70  can facilitate the manufacture of semiconductor lighting chip. Besides, in the etching of the epitaxial layer  30 , part of the fixture  70  acts as an anode which directly contacts the upper surface of the semiconductor lighting chip. Therefore, the fixture  70  can both conduct current to the wafer  10  and protect the semiconductor lighting chip. The multi-functions fixture  70  has relatively low cost and high reliability. 
         [0024]    It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the disclosure.