Abstract:
A method for enhancing power bus for I/O libraries in ASIC designs is disclosed. An I/O assignment for I/O circuits to be utilized in an ASIC design is initially generated. Each I/O circuit may obtain power from either a primary I/O power bus or a secondary I/O power bus. A determination is then made as to whether or not the I/O assignment meets certain predetermined power distribution requirements. In a determination that the I/O assignment does not meet the predetermined power bus distribution requirements, a power enhancement cell is added. The power enhancement circuit includes at least one metal line for connecting the primary I/O power bus to the secondary I/O power bus in order for the I/O assignment to meet the power bus distribution requirements.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Technical Field  
           [0002]    The present invention relates to integrated circuit designs in general, and in particular to application specific integrated circuit (ASIC) designs. Still more particularly, the present invention relates to a method for enhancing a power bus in input/output regions of an ASIC device.  
           [0003]    2. Description of the Related Art  
           [0004]    Generally speaking, there are two types of integrated circuit (IC) devices according to the types of market to which they are sold. The first type of IC devices is referred to as commodity IC devices and the second type of IC devices is referred to as application specific IC (ASIC) devices. Because commodity IC devices, such as dynamic random access memories, can be sold in vast quantities to a large number of customers, dedicated mask sets are typically employed to fabricate commodity IC devices. The relatively large one-time or non-recurring engineering costs associated with the design and layout of dedicated mask sets can typically be justified by the extremely large number of units over which the non-recurring costs can be distributed.  
           [0005]    In contrast, ASIC devices refer to, as the name implies, devices that are customized for the needs of a particular application or a particular customer. Because of the inherently limited market associated with ASIC devices, non-recurring engineering costs have a more dramatic impact on the per-unit cost for each ASIC device. In order to keep the non-recurring costs low, ASIC design methodology is highly structured and highly dependent upon reuse of building block components in order to be cost and resource efficient. Templates for top-level chip power bus and chip-to-package interconnect are one example of building block component reuses. Top-level chip power templates typically define the size of a chip, locations of all interconnect points between the chip and its package, the layout of the power bus system for the chip, and the physical area where input/output (I/O) circuits can be placed on the chip. Most ASIC libraries have a standard set of templates, which includes top-level chip power templates, that are expected to be used on the majority of customer designs. A template is chosen by an ASIC designer based on quantity of logic, number of I/O circuits, expected power dissipation, and performance requirements. The template decision is made no later than when the technology dependent gate level description of a logic model needs to be combined with the I/O circuit placement information for floor planning and timing. From an ASIC designer&#39;s point of view, the optimal I/O placement is where there is a short, direct path between the I/O circuit and the logic connected to the I/O circuit. Unfortunately, the ASIC designer must also consider the I/O supply voltages needed, I/O power requirements, power bus, electromigration and I/O noise issues. These constraints often provide difficulties for the ASIC designer to place I/O circuits in an optimal fashion.  
           [0006]    For example, current ASIC technologies provide the ability to have a secondary power supply voltage, in addition to a primary power supply voltage, in the I/O area of a peripheral footprint chip. Such ability allows an ASIC designer the flexibility of using industry standard I/O circuits that require a supply voltage other than the primary internal logic voltage. In order to provide such dual power bus flexibility, the power bus metal widths have to be limited to support double power buses within a fixed amount of silicon area. The result is reduced current carrying capability on each of the two power buses. This is not a problem when most ASIC designers are assumed to use both the primary and the secondary I/O power supply voltages that split the current amount required from those two power buses. However, there are many situations when the ASIC designer uses I/O circuits that only require the primary supply voltage. In those situations, it may be necessary to electrically enhance the primary supply bus in order to meet the I/O current demands. Consequently, it would be desirable to provide a method for enhancing a power bus in ASIC designs without incurring the cost of chip template customization.  
         SUMMARY OF THE INVENTION  
         [0007]    In accordance with a preferred embodiment of the present invention, an I/O assignment for I/O circuits to be utilized in an ASIC design is initially generated. Each I/O circuit may obtain power from either a primary I/O power bus or a secondary I/O power bus. A determination is then made as to whether or not the I/O assignment meets certain predetermined power distribution requirements. If a group of I/O circuits only uses the primary power supply and there is a determination that the I/O assignment of this group of I/O circuit does not meet the predetermined power bus distribution requirements, a power enhancement circuit is added. The power enhancement circuit includes at least one metal line for connecting the primary I/O power bus to the secondary I/O power bus in order for the I/O assignment to meet the power bus distribution requirements.  
           [0008]    All objects, features, and advantages of the present invention will become apparent in the following detailed written description.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0010]    [0010]FIG. 1 is a high-level design flow diagram for building an ASIC device, in accordance with a preferred embodiment of the present invention;  
         [0011]    [0011]FIG. 2 is a block diagram of an ASIC device, in accordance with a preferred embodiment of the present invention;  
         [0012]    [0012]FIG. 3 is a high-level logic flow diagram for a method to enhance a power bus in I/O regions of an ASIC device, in accordance with a preferred embodiment of the present invention;  
         [0013]    [0013]FIG. 4 is a block diagram of a power bus enhancement circuit, in accordance with a preferred embodiment of the present invention;  
         [0014]    [0014]FIG. 5 is a block diagram of two power buses and package pads connected together to provide additional parallel power paths to a chip, in accordance with a preferred embodiment of the present invention; and  
         [0015]    [0015]FIG. 6 is a block diagram of a computer system in which a preferred embodiment of the invention can be executed.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0016]    Referring now to the drawings and in particular to FIG. 1, there is depicted a high-level design flow diagram for building an application specific integrated circuit (ASIC) device, in accordance with a preferred embodiment of the present invention. Starting at block  10 , the behavior of an ASIC device in an abstract sense is defined, as shown in block  11 . At this point of the process, the specific implementation of the ASIC device is left undefined and the interrelationships among various circuit elements that will ultimately define the ASIC device are temporarily ignored in order to achieve a manageable model. The design of the ASIC device may be entered with a schematic capture editor or other suitable tools that are well-known in the art. An ASIC designer then attempts to describe the behavioral model of the ASIC device, as depicted in block  11 , with a hardware description language (HDL), as shown in block  12 . HDL is a highly specialized software language optimized for describing various elements and the interrelationships among the elements of an electronic device. Well-known HDLs include Verilog HDL and VHDL, as they are familiar to those skilled in the field of integrated circuit design. After the ASIC device has been suitably described in HDL format, a behavioral synthesis tool is employed to produce an register-transfer logic (RTL) representation of the ASIC device, as depicted in block  13 . An RTL description represents a lower level of abstraction than the behavioral model without incorporating all of the individual electronic elements that will ultimately comprise the ASIC device. An RTL description, for example, describes the ASIC device in terms of digital registers, clocking circuits, and logic elements that are combined to implement the desired function of the ASIC device.  
         [0017]    The RTL description is then compiled into a technology dependent gate level netlist, as shown in block  14 . From the RTL description, a gate level description of the ASIC device is achieved through a gate level synthesis. At the gate level, the ASIC device is described in greater detail than in the RTL description using a combination of common logic gates and circuits such as AND gates, OR gates, XOR gates, counters, adders, and other common logic gates. After a gate level description of the ASIC device has been achieved, suitable electronic design automation (EDA) tools can be employed to produce a netlist consisting of the list of circuit elements required to produce the ASIC device and the interconnections among the listed circuit elements.  
         [0018]    At this point, the gate level netlist is merged with the I/O placement information in preparation for floor planning, as shown in block  15   a.  The primary goal of floor planning is to produce an initial layout that can meet timing and has no wiring congestion problems. Floor planning is usually an iterative process back through RTL optimization and compile to gate level netlist, as depicted in block  16 . Concurrent with the floor planning process, an electrical analysis of the I/O placement is performed, as shown in block  15   b.  I/O placement stability is key to minimizing the number of iterations through the floor planning process, so it is important to remedy any I/O placement problems as early as possible. From the netlist, suitable placement and routing programs can be used to layout the ASIC device in an actual physical design that can be achieved with the process technology chosen for the fabrication of the ASIC device, as depicted in block  17 . After the physical design has been produced, a mask set is generated and the ASIC device is then fabricated.  
         [0019]    With reference now to FIG. 2, there is depicted a block diagram of an ASIC device, in accordance with a preferred embodiment of the present invention. As shown, an ASIC device  20  includes a chip logic area  21  and multiple I/O slots  22  located at the edges of chip logic area  21 . Each I/O slot  22  is preferably equipped with a first power bus  23 , a second power bus  24 , and a ground bus  25 . First power bus  23 , second power bus  24 , and ground bus  25  are provided to chip logic area  21  of ASIC device  20  in a form of a power bus template. Each power bus template is preferably designed to fit a particular chip size, as it is understood by those skilled in the art. An I/O circuit can be placed in each of I/O slots  22 , as desired by an ASIC designer.  
         [0020]    When a specific power bus enhancement on a power bus template is needed to support a particular current (and noise) requirement of a particular I/O circuit, the prior art solution is to customize the power bus template of the entire chip. Such solution is not very cost-effective, not to mention very time-consuming. The present invention provides a library circuit element that can be automatically inserted into the I/O placement netlist to enhance the power bus of the I/O circuits such that custom work on the power bus template for the chip is eliminated.  
         [0021]    Referring now to FIG. 3, there is depicted a high-level logic flow diagram for a method to enhance a power bus in I/O circuits for ASIC designs, in accordance with a preferred embodiment of the present invention. Such method is performed during the floor planning stage and the I/O assignment stage of an ASIC design flow that are illustrated in block  15   a  and block  15   b,  respectively, from FIG. 1. First, an I/O assignment for I/O circuits that use a primary power bus or a secondary power bus is generated, as shown in block  31 . The I/O slot locations and I/O circuit types are preferably included in the I/O assignment. The I/O assignment is then used in floor planning of chip logic, as depicted in block  32 . Electrical analysis, such as I/O power bus loading, is then performed on the I/O assignment, as shown in block  33 . If the requirements of the electrical analysis are met, then the process is completed, as depicted in block  35 . Electrical analysis may includes a variety of requirements. For example, whether or not a V dd  power bus is overloaded would be one of the requirements. Otherwise, if any of the requirements of the electrical analysis is not met, and the I/O circuit group not meeting requirements uses only the primary power supply (V dd ), then one or more power bus enhancement circuits are inserted into the I/O assignment at recommended intervals, as shown in block  34 . A preferred embodiment of a power bus enhancement circuit is illustrated in FIG. 4. After the power bus enhancement circuit has been inserted, electrical analysis should be performed again, and changes made to the  110  assignment are reflected in the floor plan of the chip.  
         [0022]    With reference now to FIG. 4, there is illustrated a block diagram of a power bus enhancement circuit, in accordance with a preferred embodiment of the present invention. As shown, a power bus enhancement circuit  40  includes multiple metal straps  41  for connecting a primary power bus, such as primary power bus  23 , to a secondary power bus, such as secondary power bus  24 , within an I/O slot. Metal straps  41  electrically connect primary power bus  23  to secondary power bus  24  in order to allow the power (or current) requirement of a group of I/O circuits to be met. In FIG. 4, a capacitor  42  is also added between secondary power bus  24  and a ground bus  25  within power bus enhancement circuit  40 . Capacitor  42  is not required for power bus enhancement circuit  40  to function, but is added for providing additional decoupling capacitance to power buses  23 ,  24 .  
         [0023]    Referring now to FIG. 5, there is illustrated a cross-sectional view of two power buses and package pads connected together to provide additional parallel power paths to an ASIC chip, in accordance with a preferred embodiment of the present invention. As shown, primary power bus  23  and secondary power bus  24  are connected together via a power bus enhancement circuit within an I/O slot  70 . As a result, power supply noise and electromigration effects on the metal buses are reduced.  
         [0024]    As has been described, the present invention provides a method for enhancing a power bus in I/O regions of an ASIC device without customization of the power bus template. The present invention provides an I/O circuit with a power bus enhancement circuit that connects a primary supply bus to a secondary supply bus to effectively double the current capability of the I/O power bus and to reduce the overall inductance. Such I/O circuit, which includes the power bus enhancement circuit, can be inserted in any I/O slot location on an ASIC chip to allow an ASIC designer the flexibility of enhancing the power bus where needed. In addition, with the present invention, the package pads connected to the secondary bus are available to bring more power to the primary bus through the package.  
         [0025]    With reference now to FIG. 6, there is depicted a block diagram of a computer system in which a preferred embodiment of the invention can be executed. Within a computer system  50 , a main processor  51  is coupled to a main memory  52  and to a multiple-function I/O processor (MFIOP)  54 . Main processor  51  may include a single processor or multiple processors. Several peripheral storage devices such as a diskette drive  56 , a tape drive  57 , and direct access storage devices (DASDs)  58 , are controlled by MFIOP  54 . In addition, MFIOP  54  provides communications to other devices via communication ports such as COMM 1 and COMM 2.  
         [0026]    Attached to a system bus  59  are a workstation controller  53  and a communications  1 /O processor (CIOP)  55 . Workstation controller  53  provides communications between main processor  51  and workstations  60  that may be connected to computer system  50 . CIOP  55  provides communications to other devices via communication ports such as COMM3, COMM4, and COMM5.  
         [0027]    It is also important to note that although the present invention has been described in the context of a fully functional computer system, those skilled in the art will appreciate that the mechanisms of the present invention are capable of being distributed as a program product in a variety of forms, and that the present invention applies equally regardless of the particular type of signal bearing media utilized to actually carry out the distribution. Examples of signal bearing media include, without limitation, recordable type media such as floppy disks or CD ROMs and transmission type media such as analog or digital communications links.  
         [0028]    While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.