Abstract:
A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode.

Description:
TECHNICAL FIELD 
     This subject matter relates generally to electronics, and more particularly to single ended to fully differential conversion structures. 
     BACKGROUND 
     High-performance analog circuits are usually implemented in discrete-time circuits, often as switched capacitor (SC) circuits. In a typical circuit architecture, switched capacitors are often integrated because of their small area and high speed. Inherent errors of the capacitors and switches, however, can limit the linearity performance of such circuits. Generally incorporated with an analog-to-digital converter (ADC), these structures can achieve high resolution conversion for low frequency signals, such as Sigma Delta converters. 
     The inherent errors in conventional SC structures are mainly due to three reasons: charge injection, non-linearity of CMOS switches and capacitor mismatching. Therefore, a tradeoff is often made with respect to speed, accuracy, power consumption and design flexibility. In addition, noise contribution from power supplies should be minimized. Since fully differential circuits have a high common mode rejection, noise contribution from power supplies is an issue for single-ended structures. Nevertheless, fully differential structures require fully differential amplifiers with common mode feedback circuitry to center the output signals around the common mode level of the system. This part of the structure can be challenging to design for high-speed discrete-time operations. 
     One design technique used to perform single ended to fully differential conversion is the charge and transfer technique (also called charge-redistribution). In charge and transfer designs, analog input voltages are sampled into sampling capacitors in a first phase, then transferred to integration capacitors in a second phase. In a third phase, the integration capacitors are discharged (reset), thus ready to hold the next sampled charges. This design can operate as a simple sample and hold circuit and as an integrator if the feedback capacitors are not reset in each phase. This property is used in oversampling ADCs such as Sigma Delta converters which perform noise shaping to achieve high resolution conversions. 
     There exist conventional circuits which are capable of providing single ended to fully differential conversions. Some of these conventional circuits require high oversampling which limits the input bandwidth. Other conventional circuits only use positive input and shunt negative input to ground. Therefore, noise immunity (kT/C) and capacitor matching accuracy can differ from one mode to the other. 
     Other conventional circuits use only the one capacitor (or one branch of the sampling structure) to sample the input, thus, KT/C is double. Moreover, the transfer function for single ended conversion is different than the transfer function for fully differential conversion. 
     SUMMARY 
     A dual mode (sample and hold mode and integrator mode), single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches (e.g., CMOS switches) which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode. The structure is fully symmetrical in that the positive side and the negative side of the structure has the same number and types of circuit devices. In single ended conversion, the single ended input signal can be applied into Vin+ or Vin− terminals. Both the positive and negative branches of the structure can transform a positive input sample into a negative output (+Q to −Q). 
     The dual mode conversion is advantageous because the transfer function of the structure remains the same in both conversion and sample and hold modes. Positive and negative branches of the structure are functional in both modes (i.e., both input capacitors are used for sampling), which provides identical capacitor matching and gain scaling (Cs/CF ratio), resulting in improved distortion (THD). The structure can receive a single ended input signal and provide an output signal balanced about the common mode level of a fully differential circuit. Unlike conventional solutions, the structure does not have a limited input data rate because the same differential voltage is sampled into both sampling capacitors (sampling capacitors on each side or branch) without introducing time delay between two successive samples. 
     The structure can be incorporated into a variety of clock pulsed, mixed mode systems which need analog input signal adaptation. For example, the disclosed structure can be implemented as a front end of a high data rate pipeline ADC. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic diagram of a fully differential integrator structure for performing sample and hold operations. 
         FIG. 1B  is a schematic diagram illustrating operation of the structure of  FIG. 1A  in a sampling phase. 
         FIG. 1C  is a schematic diagram illustrating operation of the structure  FIG. 1A  in a transferring phase (hold phase). 
         FIG. 1D  illustrates non-overlapping waveforms for triggering sampling and transferring phases. 
         FIGS. 1E-1G  illustrate input voltages and output voltages when the structure of  FIG. 1A  operates either as a sample and hold or as an integrator. 
         FIG. 2A  is a schematic diagram of an example dual mode, single ended to fully differential converter structure. 
         FIG. 2B  is a schematic diagram of the structure of  FIG. 2A  operating in fully differential conversion mode. 
         FIG. 2C  is a schematic diagram of the structure of  FIG. 2A  operating in a sampling phase in differential to differential conversion. 
         FIG. 2D  is a schematic diagram of the structure of  FIG. 2A  operating in a transferring phase in differential to differential conversion. 
         FIGS. 2E-2G  are schematic diagrams of the structure of  FIG. 2A  operating in a sampling phase in single-ended to differential conversion. 
         FIG. 2H  is a schematic diagram of the structure of  FIG. 2A  operating in a transferring phase in single-ended to differential conversion. 
         FIGS. 2I-2K  are schematic diagrams of the structure of  FIG. 2A  operating in a sampling phase in single-ended to differential conversion. 
         FIG. 2L  is a schematic diagram of the structure of  FIG. 2A  operating in a transferring phase in single-ended to differential inverted conversion. 
         FIG. 3  illustrates input/output waveforms for a sample and hold mode of the structure of  FIG. 2A . 
     
    
    
     DETAILED DESCRIPTION 
     Example Sample &amp; Hold Circuit 
       FIG. 1A  is a schematic diagram of a fully differential integrator structure  100  for performing sample and hold operations. The fully differential structure is inherently immune to power supply noise and can achieve a high common mode rejection ratio. The fully differential structure includes a high gain, fully differential amplifier  102 . The high gain, fully differential amplifier  102  is coupled to common mode feedback circuitry  104  to maintain a common mode level of output of the differential amplifier  102  at a predetermined level. Structures using common mode feedback circuitry require that the input differential signal be such that the signal applied to the negative input terminal is the same as the signal applied to the positive terminal but inverted. For example, if the input signal, V diff , is a sine wave, then the first half of the sine wave cycle is positive as applied to the first input terminal, the second input terminal should have a sine wave applied thereto with its first half being negative, as shown in  FIG. 1A . Accordingly, the common mode voltage, V, can be written as a function of the input signals applied to the positive and negative terminals: 
     
       
         
           
             
               
                 
                   
                     
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     In some implementations, the fully differential integrator structure  100  includes switches S 1 -S 10  (e.g., CMOS switches), sampling capacitors C sp , C sn  (collectively, referred to as sampling capacitors C s ) for positive and negative sides, respectively, of the block  100 , differential amplifier  102  and feedback capacitors C fp , C fn  (collectively, referred to as feedback capacitors C f ). 
     Referring to  FIGS. 1B and 1D , in a sampling phase, when phase  1  (Phi 1 ) is high, switches S 1 , S 2 , S 6  and S 8  are closed and inputs V inp  and V inn  are sampled across sampling capacitors C sp , C sn . Inputs and outputs of the fully differential amplifier  102  are shorted to reset feedback capacitors, C f , to operate as a sample and hold. 
     In a transferring phase (hold phase), when phase  2  (Phi 1 ) is high, S 3 , S 4 , S 5  and S 7  are closed and the sampled inputs in capacitors, C s , are transferred across feedback capacitors C f . As shown in  FIG. 1C , the inputs and outputs of the fully differential amplifier  102  are coupled together through the feedback capacitors, C f . Positive charges +Q are transferred from the sampling capacitors, C s , to the feedback capacitors C f . The Z transform of the system function is given by: 
     
       
         
           
             
               
                 
                   
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     The structure  100  can either operate as a sample and hold or as an integrator. For example, assuming that the input is a DC level voltage with amplitude of 100 mV ( FIG. 1E ), the output of the structure  100  when operating as a sample and hold and as an integrator are shown in  FIGS. 1F and 1G , respectively. 
     Dual Mode, Single Ended to Fully Differential Converter 
       FIG. 2A  is a schematic diagram of an example dual mode, single ended to fully differential converter structure  200 . The structure  200  is similar to the structure  100  in  FIG. 1A . The structure  200 , however, includes four additional switches (S 9 , S 10 , S 11 , S 12 ). By having both positive and negative inputs applied on each sampling capacitor, C sp , C sn , positive and negative charges +Q and −Q can be sampled on both (positive and negative) sides of the structure  200 . By inverting the sampled charge on one side, the structure  200  can provide single ended to fully differential conversion. Note that Phi 1   ds  is equivalent to Phi 1  in both fully differential mode and single ended mode, Phi 1   d  is equivalent to Phi 1  in fully differential mode only, Phi 1   s  is equivalent to Phi 1  in single ended mode only, and OFF is always open (placed for symmetry reasons). 
     In some implementations, differential amplifier  202  has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal. The negative output terminal is coupled to the positive input terminal through feedback capacitor  204 . The positive input terminal and negative output terminal of the differential amplifier  202  are coupled to bypass switch S 13  which is operable for bypassing feedback capacitor  204  during a sampling phase (Phi 1 ). The positive output terminal of the differential amplifier  202  is coupled to the negative input terminal of the differential amplifier  202  through feedback capacitor  206 . The negative input terminal and positive output terminal are coupled to bypass switch S 14  which is operable for bypassing feedback capacitor  206  during the sampling phase. 
     Referring to a positive side or branch of the converter structure  200 , a first node  212  is coupled to a positive input terminal of the converter structure  200 , switch S 1 , switch S 9 , switch S 5 , and sampling capacitor  208 . Switch S 1  is operable for coupling the positive input terminal of the converter structure  200  to the first node  212  during the sampling phase. Switch S 9  is operable for coupling a reference voltage (V ref ) to the first node  212  during the sampling phase. Switch S 5  is operable for coupling a common mode voltage (V cm ) to the first node  212  during a transfer phase (Phi 2 ), which occurs after the sampling phase. 
     A second node  214  is coupled to sampling capacitor  208 , switch S 3 , switch S 10  and switch S 6 . Switch S 3  is operable for coupling the positive input terminal of the differential amplifier  202  to the second node  214  during the transferring phase. Switch S 6  is operable for coupling the reference voltage to the second node  214  during the sampling phase. Switch S 10  is operable for coupling the negative input terminal of the converter structure  200  (Vin−) to the second node  214  during the sampling phase. 
     Referring to a negative side or branch of the converter structure  200 , a third node  216  is coupled to a negative input terminal of the converter structure  200 , switch S 2 , switch S 11 , switch S 7 , and sampling capacitor  210 . Switch S 2  is operable for coupling the negative input terminal of the converter structure  200  to the third node  216  during the sampling phase. Switch  11  is operable for coupling the reference voltage to the third node  216  during the sampling phase. Switch S 7  is operable for coupling the common mode voltage to the third node  216  during the transferring phase. 
     A fourth node  218  is coupled to sampling capacitor  210 , switch S 4 , switch S 12 , switch S 8 , and the negative input terminal of the differential amplifier  202 . Switch S 4  is operable for coupling the negative input terminal of the differential amplifier  202  to the fourth node  218  during the transferring phase. Switch S 8  is operable for coupling the reference voltage to the fourth node  218  during the sampling phase. Switch S 12  operable for coupling the positive input terminal of converter structure  200  to the fourth node  218  during the sampling phase. 
     Fully Differential Conversion Mode 
       FIG. 2B  is a schematic diagram of the structure  200  of  FIG. 2A  operating in fully differential conversion mode. In fully differential conversion mode, switches S 9 , S 10 , S 11  and S 12  are open, resulting in structure  200  being the same as structure  100  shown in  FIG. 1A . The structure  100  operates in the same manner as structure  100  to adapt an external input signal into a sampled system. 
     Sampling Phase 
       FIG. 2C  is a schematic diagram of the structure  200  of  FIG. 2A  operating in a sampling phase. In this example sampling phase, Phi 1  is high and Phi 1  is low ( FIG. 3 ). Switches S 1 , S 2 , S 6 , S 8 , S 13  and S 14  are closed and switches S 3 , S 4 , S 5 , S 7 , S 9 , S 10 , S 11  and S 12  are open. In sampling phase, both inputs, V in+ , V in−  are sampled into sampling capacitors, C s , by a differential voltage of ΔV=V in −V ref . Reference voltage, V ref , can be different from the amplifier common mode voltage, V cm . Thus, DC level shifting can be assured. 
     Transferring Phase 
     Hold Phase 
       FIG. 2D  is a schematic diagram of the structure  200  of  FIG. 2A  operating in a transferring phase (hold phase). In this example transferring phase, Phi 1  is low and Phi 1  is high ( FIG. 3 ). Switches S 3 , S 4 , S 5 , S 7  are closed and switches S 1 , S 2 , S 9 , S 10 , S 11 , S 12 , S 13  and S 14  are open. In transferring phase, voltage difference ΔV is transferred from sampling capacitors, C s , to feedback (or holding) capacitors, C f , with a DC level shifting equal to V ref −V cm . If V ref =V cm , no DC level shifting occurs. 
     Single Ended To Fully Differential Conversion Mode 
       FIGS. 2E-2H  are schematic diagrams of the structure  200  of  FIG. 2A  operating in a sampling phase. In single ended to fully differential conversion, the positive side or branch of the structure maintains the same functioning, as shown in  FIG. 2E . For example, switches S 1 , S 6 , S 13  are closed and switches S 3 , S 5 , S 9  and S 10  are open. This results in a positive charge, +Q, being charged into the sampling capacitor, Csp. On the negative side or branch of the structure switches S 11 , S 12 , S 14  are closed and switches S 2  and S 8  are open. This configuration results in a negative charge −Q being charged into the sampling capacitor, Csn. 
     However, the negative branch inverts the sampling charge +Q into −Q by applying V in  on the other side of the sampling capacitor C sn , as shown in  FIG. 2F .  FIG. 2G  shows the differential amplifier and feedback circuits in sampling phase. 
     Referring to  FIG. 2H , in a transferring phase, two opposite charges +Q and −Q are transferred into feedback capacitors C fp  and C fn , respectively, resulting in a fully differential output signal with an inherent gain of 2. For example, the differential output voltage is given by (ν outp −ν outn )=+Q/C f −(−Q/C f )=2Q/C f . As can be seen in  FIG. 3 , the output signals, v op , v on , satisfy the requirement of a fully differential signal. The transfer function is given by: 
     
       
         
           
             
               
                 
                   
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                     ⁡ 
                     
                       ( 
                       Z 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           outdiff 
                         
                         ⁡ 
                         
                           ( 
                           z 
                           ) 
                         
                       
                       
                         
                           V 
                           indiff 
                         
                         ⁡ 
                         
                           ( 
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                           ) 
                         
                       
                     
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                       2 
                       ⁢ 
                       
                         
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                           s 
                         
                         
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                           f 
                         
                       
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                             z 
                             1 
                           
                           
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                                 1 
                               
                             
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                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
       FIGS. 2I-2K  are schematic diagrams of the structure of  FIG. 2A  operating in a sampling phase. These figures illustrate the structure is fully symmetrical. Not only can the negative branch of the structure transform a positive input sample into a negative output (+Q to −Q), the positive branch of the structure can perform the transform as well, as illustrated in  FIGS. 2I-2K . 
       FIG. 2L  is a schematic diagram of the structure of  FIG. 2A  operating in a transferring phase. In a transferring phase, two opposite charges −Q and +Q are transferred into feedback capacitors C fp , and C fn , respectively, resulting in a fully differential output signal with an inherent gain of −2. For example, the differential output voltage is given by ν outp −ν outn )=−Q/C f −(+Q/C f )=−2Q/C f . 
       FIG. 3  illustrates input/output waveforms for a sample and hold mode of the structure of  FIG. 2A . In a first half of a first CLK cycle, Phi 1  is high and Phi 2  is low. V in  is at +amp (amplitude). V outp  and V outn  are at and the differential output (V outp −V outn ) is 0. In a second half of the first CLK cycle, Phi 1  is low and Phi 2  is high. V in  is at +amp. V outp  is at +amp and V outn  is amp and the differential output (amp+−(−amp)) is 2 amp. 
     Similarly, in a first half of a second CLK cycle following the firs CLK cycle, Phi 1  is high and Phi 2  is low. V in  is at +amp (amplitude). V outp  and V outn  are at V cm  and the differential output (V outp −V outn ) is 0. In a second half of the second CLK cycle, Phi 1  is low and Phi 2  is high. V in  is at +amp. V outp  is at +amp and V outn  is −amp and the differential output (+amp−(−amp)) is +2 amp.