Abstract:
A method and system are disclosed for synchronizing two or more engines in a graphics processing unit (GPU). When issuing a command to an engine, a central processing unit (CPU) writes an event value representing the command into an element of an event memory associated with the engine. After executing the command, the engine modifies the content of the event memory in order to recognize the completion of the command execution. The CPU acquires the command execution status by reading the modified content of the event memory. With precise knowledge of the command execution status, the CPU can issue commands to various engines independently, hence the engines can run parallel.

Description:
PRIORITY DATA  
       [0001]     This application claims the benefits of U.S. patent application Ser. No. 60/727,668, which was filed on Oct. 18, 2005, and entitled “Smart CPU Sync Technology for MultiGPU Solution.” 
       CROSS REFERENCE  
       [0002]     This application also relates to U.S. Patent application entitled “METHOD AND SYSTEM FOR DEFERRED COMMAND ISSUING IN A COMPUTER SYSTEM”, U.S. Patent Application entitled “TRANSPARENT MULTI-BUFFERING IN MULTI-GPU GRAPHICS SUBSYSTEM”, and U.S. Patent Application entitled “EVENT MEMORY ASSISTED SYNCHRONIZATION IN MULTI-GPU GRAPHICS SUBSYSTEM”, all of which are commonly filed on the same day, and which are incorporated by reference in their entirety. 
     
    
     BACKGROUND  
       [0003]     The present invention relates generally to computer graphics subsystems, and, more particularly, to the synchronization of various parallel engines inside a graphics processing unit.  
         [0004]     A graphics processing unit, or GPU, is a dedicated graphics processing device in a computer system or game console. It is a common practice for a GPU to contain several parallel processing structures, or engines, to carry out dedicated functions in order to improve GPU&#39;s performance. For instance, 3D engine only provides real-time 3D rendering. Other engines include 2D engine and master-image-transfer (MIT) engine, etc.  
         [0005]     Even though these engines can run independently, they often lack adequate synchronization mechanisms among themselves in traditional computer systems, i.e., after an engine finishes a task, it has no mechanism to provide a notification of such an event. To facilitate a switch from one engine to another, the central processing unit, or CPU, has to insert a wait-engine-idle command, which blocks commands for other engines, hence hinders the engines to run fully parallel.  
         [0006]     Such issues become a performance bottleneck especially in multi-GPU and multi-buffer applications. For instance, assuming there is a master GPU and one or more slave GPUs associated therewith, and in the slave GPU, after a 3D engine finishes a frame rendering, its master-image-transfer (MIT) engine begins to bit-block-transfer (BLT) the frame to a master GPU buffer. Ideally the 3D engine should be able to render a next frame right after the current rendering finishes, but without the proper synchronization mechanism, the 3D engine has to wait for the MIT engine to complete its BLT before proceeding to the next frame rendering. Here the term, “master GPU”, refers to a GPU having a direct connection to a display driver. The term, “slave GPU”, refers to a GPU that has no direct connection with the display driver and has to transfer its rendered image to the master GPU for display.  
         [0007]     It is therefore desirable for a computer system to have synchronization means to allow various engines inside a GPU to run parallel to improve efficiency.  
       SUMMARY  
       [0008]     In view of the foregoing, a method and system are disclosed for synchronizing two or more engines in a graphics processing unit (GPU) to allow the engines to run parallel.  
         [0009]     According to one embodiment of the present invention, when issuing a command to an engine, a central processing unit (CPU) writes an event value corresponding to the command into an element of an event memory associated with the engine. After executing the command, the engine modifies the content of the event memory in order to recognize the completion of the command execution. The CPU acquires the command execution status by examining the modified content of the event memory. With the precise knowledge of the command execution status, the CPU can issue commands to various engines independently, hence the engines can run parallel.  
         [0010]     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is a block diagram of a part of a computer system with allocated event memories for event tracking.  
         [0012]      FIG. 2  is a flow chart illustrating the operations of the event memory updating and command issuing.  
     
    
     DESCRIPTION  
       [0013]     A method and system are disclosed below for synchronizing two or more engines in a graphics processing unit (GPU) in a computer system to allow the GPU to improve its efficiency. Detailed information with regard to the operation of the GPU in the computer system is further described in U.S. Patent application entitled “METHOD AND SYSTEM FOR DEFERRED COMMAND ISSUING IN A COMPUTER SYSTEM”, and U.S. Patent Application entitled “TRANSPARENT MULTI-BUFFERING IN MULTI-GPU GRAPHICS SUBSYSTEM”, and U.S. Patent Application entitled “EVENT MEMORY ASSISTED SYNCHRONIZATION IN MULTI-GPU GRAPHICS SUBSYSTEM”, all of which are commonly filed on the same day, and which are incorporated by reference in their entirety.  
         [0014]      FIG. 1  is a block diagram of a part of a computer system  100  that has a graphics processing unit (GPU)  110 . Inside the GPU  110 , there is number of engines for various tasks, such as 3D rendering engine  120 , 2D graphics engine  130 , video processing engine  140  and master-image-transfer (MIT) engine  150 . A set of event memories  160  are allocated from either PCI Express or video memory or some other memory space for storing the GPU engine event status. The event memories  160  have n number of memories  170  through  176  with each one dedicated to a particular engine. For instance, event memory  170  is for the 3D engine  120 , event memory  172  is for the 2D engine  130 , event memory  174  is for the video engine  140  and event memory  176  is for the MIT engine  150 . Within each event memory, there are various elements. For example, as shown in  FIG. 1 , there are m+1 number of elements, with a particular one dedicated as a read element, such as R 1  in event memory  170 , and the rest m elements are write elements, such as W 1 [0:m−1] in event memory  170 . Every time when an engine command needs to be traced, and upon issuing of the command to the engine, the CPU writes a predetermined value corresponding to the command into a write-element of an event memory for that engine and let the engine copy the value in the write-element to a read-element of the same event memory. By checking the read-element alone, the CPU is aware of the completion of the command execution. Note that if the engine does not have a COPY command, it is the driver&#39;s duty to let each engine do the COPY action. E.g. driver can let MIT engine do MIT to do the COPY, or let 2D engine do a bitBlt to do the COPY, or let 3D engine use the write memory as a texture and the read memory as a render target to do a render to do the COPY.  
         [0015]      FIG. 2  is a flow chart detailing the command status recording and checking operations for the computer system shown in  FIG. 1 . Referring to both  FIGS. 1 and 2 , the CPU  180  first directs its attention to an event memory associated with an engine inside a GPU that has a command in need of tracing in step  210 . In step  220  the CPU  180  has to make sure that a command represented by an event value stored in a current write address has been executed. For example, W 1 [0:m−1] is checked first if the value stored there is associated with a command being traced. The following is a pseudo-code for a program that will be explained with regard to  FIG. 2 : 
        waiting for event(curEventValu+1−m)     WriteElement[curWriteAddress]=curEventValu++    curWriteAddress++    curWriteAddress %=(m)          
         [0020]     According to an embodiment of the present invention, assuming event values representing particular engine commands are incrementally assigned, and curEventValu stands for a current event value, and m is the number of write-elements in the event memory, then event (curEventValu+1−m) corresponds to a command issued m number of command cycle earlier. Step  220  can be expressed as: waiting for event (curEventValu+1−m) is completed.  
         [0021]     Step  220  is added because of the limited number (m) of the write-elements in the event memory, and the need to prevent a value associated with an unexecuted command in the event memory from being overwritten. Alternatively, if the number m is sufficiently large so that the chance of overwriting values for unexecuted commands is so slim that it can be ignored, then the step  220  can be skipped. Similarly, the number of write-elements can also be dynamically assigned in order to avoid the danger of unexpected overwriting, and this step  220  can also be eliminated.  
         [0022]     Next step  230  in  FIG. 2  is to write the current event value (curEventValu), associated with a new command, to the current write address (curWriteAddress) of the event memory, and then increase the curEventValu by one in step  234 . These steps can be expressed as: *WriteElement[curWriteAddress]=curEventValu++.  
         [0023]     In step  238  the CPU  180  issues the new command to an engine, and instructs the engine to modify the content of the designated event memory. For instance, it may instruct the engine to copy the value in the write element at the address, curWriteAddress, to a dedicated read element upon finishing the execution of the command in step  240 . After executing the command, this particular engine does the copying as instructed without any participation by CPU  180 . Alternatively, the CPU can also instruct the content of the designated event memory to be changed to a particular predetermined value.  
         [0024]     Step  250  is to increase the current write address, or curWriteAddress, by one for this particular engine. The expression for step  250  is: curWriteAddress++.  
         [0025]     Step  260  is to take a remainder of the incremented current write address divided by the number of write-elements, or m. The purpose of this step is that when the curWriteAddress is increased larger than m, it will be reset to the beginning as there are only m numbers of write addresses. Step  260  can also be expressed as: curWriteAddress %=(m).  
         [0026]     The CPU can quickly check the read element of the designated memory space, and in this way, every time when the CPU examines the value of a read element, it can exactly know which engine has finished a command execution.  
         [0027]     As shown, for synchronizing two or more engines in a graphics processing unit, an event value representing a command issued to an engine is written into an element of an event memory, such as the write element. The content of the event memory containing the event value may be modified recognizing a completion of the command execution by the engine. The modified content of the event memory is then read by a central processing unit to acquire the command execution status, wherein the CPU coordinates command issuing to all the engines based on the command execution status of each engine.  
         [0028]     This invention provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and methods are described to help clarify the disclosure. These are, of course, merely examples and are not intended to limit the disclosure from that described in the claims.