Abstract:
A memory device comprises a contact and a pillar-shaped structure on the contact. The pillar-shaped structure includes a conductive inner element surrounded by a memory outer layer. A transition region is located at the memory outer layer above said contact. The conductive element may directly contact said contact.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation of U.S. patent application Ser. No. 11/538,677, filed 4 Oct. 2006 (Attorney Docket No. MXIC 1713-1). 
         [0002]    The present application is related to the following U.S. patent applications: application Ser. No. 11/375,942 filed on 15 Mar. 2006 entitled Pipe Shaped Phase Change Memory (Attorney Docket No. MXIC 1629-4); Application No. 60/752,138 filed on 19 Dec. 2005 entitled Phase Change Memory Cell and Manufacturing Method (Attorney Docket No. MXIC 1686-1); and application Ser. No. 11/375,816 filed on 15 Mar. 2006 entitled Manufacturing Method for Pipe-Shaped Electrode Phase Change Memory (Attorney Docket No. MXIC 1715-1); the entire contents of each of which are incorporated herein by reference. 
     
    
     PARTIES TO A JOINT RESEARCH AGREEMENT 
       [0003]    International Business Machines Corporation, a New York corporation; Macronix International Corporation, Ltd., a Taiwan corporation; and Infineon Technologies A.G., a German corporation, are parties to a Joint Research Agreement. 
       BACKGROUND OF THE INVENTION 
       [0004]    1. Field of the Invention 
         [0005]    The present invention relates to high density memory devices based on programmable resistive or other memory material, like phase change based memory materials, and to methods for manufacturing such devices. 
         [0006]    2. Description of Related Art 
         [0007]    Chalcogenide materials are widely used in read-write optical disks. These materials have at least two solid phases, generally amorphous and generally crystalline. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change. 
         [0008]    Chalcogenide materials also can be caused to change phase by application of electrical current. This property has generated interest in using programmable resistive material to form nonvolatile memory circuits. 
         [0009]    One direction of development has been toward using small quantities of programmable resistive material, particularly in small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000. 
         [0010]    In phase change memory, data is stored by causing transitions in the phase change material between amorphous and crystalline states using current. Current heats the material and causes transitions between the states. The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the active phase change material element in the cell. One problem associated with phase change memory devices arises because the magnitude of the current required for reset operations depends on the volume of phase change material that must change phase. Thus, cells made using standard integrated circuit manufacturing processes have been limited by the minimum feature size of manufacturing equipment. Thus, techniques to provide sublithographic dimensions for the memory cells must be developed, which can lack uniformity or reliability needed for large scale, high density memory devices. 
         [0011]    One approach to controlling the size of the active area in a phase change cell is to devise very small electrodes for delivering current to a body of phase change material. This small electrode structure induces phase change in the phase change material in a small area like the head of a mushroom, at the location of the contact. See, U.S. Pat. No. 6,429,064, issued Aug. 6, 2002, to Wicker, “Reduced Contact Areas of Sidewall Conductor;” U.S. Pat. No. 6,462,353, issued Oct. 8, 2002, to Gilgen, “Method for Fabricating a Small Area of Contact Between Electrodes;” U.S. Pat. No. 6,501,111, issued Dec. 31, 2002, to Lowrey, “Three-Dimensional (3D) Programmable Device;” U.S. Pat. No. 6,563,156, issued Jul. 1, 2003, to Harshfield, “Memory Elements and Methods for Making Same.” 
         [0012]    Accordingly, an opportunity arises to devise methods and structures that form memory cells with structures that have small active regions of programmable resistive material using reliable and repeatable manufacturing techniques. 
       SUMMARY OF THE INVENTION 
       [0013]    A first example of a memory device comprises a contact and a pillar-shaped structure on the contact. The pillar-shaped structure includes a conductive inner element surrounded by a memory outer layer. A transition region is located at the memory outer layer above said contact. The conductive element directly contacts said contact. In some examples the pillar-shaped structure comprises a second conductive inner element and a dielectric element separating the second conductive inner element from the conductive inner element, with the dielectric element and the second conductive inner element being surrounded by the memory outer layer. 
         [0014]    A second example of a memory device comprises a center electrode, tubular memory element and a second electrode. The tubular memory element surrounds the center electrode with the center electrode in contact with a first electrode. The tubular memory element has a transition region. The second electrode is electrically connected to the center electrode via the tubular memory element. The energy passing between the center and second electrodes is concentrated within the transition region so to facilitate changing an electrical property state of the tubular memory element. In some examples the memory device further comprises a second center electrode in contact with the second electrode and a dielectric element separating the second center electrode from the center electrode. In some examples the tubular memory element surrounds the dielectric element, the center electrode and the second center electrode. 
         [0015]    A third example of a memory device comprises a first electrode, a center electrode and a memory element. The center electrode is on the first electrode and has a circumferentially extending outer surface. The memory element has a circumferentially extending first surface. The memory element surrounds the circumferentially extending outer surface and electrically connects the circumferentially extending first surface to a second electrode. In some examples the memory device further comprises a second center electrode, a second electrode and a dielectric element. The second center electrode is in contact with the second electrode and the dielectric element separates the second center electrode from the center electrode. In some examples the memory element is a tubular memory element and surrounds the dielectric element, the center electrode and the second center electrode. 
         [0016]    An integrated circuit including a memory array is described comprising a plurality of such memory cell devices with access transistors, arranged in a high density array of rows and columns. The access transistors comprise source and drain regions in a semiconductor substrate, and a gate coupled to word lines along rows of memory cells. The memory cells are formed in a layer above the access transistors on the integrated circuit, with a bottom electrode contacting the drain of a corresponding access transistor. Bit lines are formed using a layer of metallization above the memory cells contacting the top electrodes on the memory devices along columns of memory cells in the array. In an embodiment described, two rows of memory cells share source contacts, with a common source line coupled to the source contact and extending generally parallel to the word lines through the array. 
         [0017]    A reliable memory cell structure is provided with a low reset current, which is manufacturable using the standard lithographic and deposition processes. The cell structure is particularly suited to integration with CMOS circuitry on a large scale integrated circuit device. 
         [0018]    Other aspects and advantages of the technology described herein can be understood with reference to the figures and the detailed description which follow. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  is a cross-sectional view of an embodiment of a memory cell device in which the memory element comprises a circumferentially-extending portion surrounding a dielectric material as well as bottom and top electrode extensions. 
           [0020]      FIG. 2  is a simplified cross-sectional view of taken a long line  2 - 2  of  FIG. 1 . 
           [0021]      FIG. 3  is a circuit schematic of a memory array including memory cells like those shown in  FIG. 1 . 
           [0022]      FIG. 4  is a block diagram of an integrated circuit device including memory cell devices as in  FIG. 1  and other circuitry. 
           [0023]      FIG. 5  is a cross-sectional view of a two cell array structure for an embodiment of the invention. 
           [0024]      FIGS. 6-15  illustrate respective stages in a manufacturing process for a memory cell array structure as in  FIG. 5 . 
           [0025]      FIGS. 16 and 17  illustrate alternative embodiments of portions of the memory cell device of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0026]    The following description of the invention will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals. 
         [0027]      FIG. 1  is a simplified cross-sectional view of a memory cell device  10 . Device  10  includes a bottom or first electrode  12  and a top or second electrode  14  connected by a circumferentially extending, sometimes called pipe-shaped, memory element  16 . Memory element  16 , in this embodiment, surrounds bottom and top electrode members or extensions  17  and  18  and dielectric material  20 , the dielectric material extending between electrode extensions  17 ,  18 . Memory element  16  is also surrounded by a dielectric material  26 . Therefore, memory element  16  has an interior housing bottom and top electrode extension  17 ,  18  and dielectric material  26 . 
         [0028]    The central portion  22  of memory element  16  acts as a transition region for the memory element. Assuming memory element is a phase change material such as GST, discussed below, the transition between or among different electrical property states will typically occur at this central portion  22  due at least in part to the better thermal isolation from electrodes  12 ,  14 . 
         [0029]    In this embodiment memory material  16  is a tube-like, pipe-shaped, fully circumferentially extending structure. See  FIG. 2 . However, in some embodiments and under some processing procedures, memory material  16  may not extend completely around all or part of one or more of dielectric material  20 , bottom electrode extension  17  and top electrode extension  18 . The use of circumferentially extending memory material  16  increases the efficiency of memory material  16  by reducing the volume of the memory material that transitions between electrical property states when compared to a cylindrical volume of memory material. When memory material  16  is a phase change material, it reduces the power and current requirement for reset of the phase change material. In addition, better process uniformity after trimming (see  FIGS. 9 and 10 ) is also achieved using circumferentially extending memory material  16 . 
         [0030]    Dielectric materials  20 ,  26  may include silicon oxide, silicon oxynitride, silicon nitride, Al 2 O 3 , other low K (low permitivity) dielectrics, or an ONO or SONO multi-layer structure. Alternatively, dielectric materials  20 ,  26  may comprise an electrical insulator including one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C. In preferred devices, dielectric materials  20 ,  26  have a low thermal conductivity, less than about 0.014 J/cm*K*sec. In other preferred embodiments, when memory element  16  is made from a phase change material, one or both of the thermally insulating dielectric materials  20 ,  26  have a thermal conductivity less than that of the amorphous state of the phase change material, or less than about 0.003 J/cm*K*sec for a phase change material comprising GST. Representative thermally insulating materials include materials that are a combination of the elements silicon Si, carbon C, oxygen O, fluorine F, and hydrogen H. Examples of thermally insulating materials which are candidates for use for the thermally insulating dielectric materials  20 ,  26  include SiO 2 , SiCOH, polyimide, polyamide, and fluorocarbon polymers. Other examples of materials which are candidates for use for the thermally insulating dielectric materials  20 ,  26  include fluorinated SiO 2 , silsesquioxane, polyarylene ethers, parylene, fluoro-polymers, fluorinated amorphous carbon, diamond like carbon, porous silica, mesoporous silica, porous silsesquioxane, porous polyimide, and porous polyarylene ethers. In other embodiments, the thermally insulating structure comprises a gas-filled void for thermal insulation. A single layer or combination of layers within dielectric materials  20 ,  26  can provide thermal and electrical insulation. 
         [0031]    Typical dimensions for memory cell device  10  of  FIG. 1  are as follows. Tubular memory element  16  preferably has a wall thickness of less than 30 nm, typically about 10 nm. Tubular memory element  16  preferably has an interior surface diameter  3  of less than 50 nm, typically about 30 nm. Tubular memory element  16  preferably has a length  5  of less than 100 nm, typically about 50 nm. Diameters  2 ,  4  are typically 40 nm and 90 nm respectively. Heights  6  and  7  are typically 50 nm and 40 nm respectively. Diameter  4  is typically a minimum lithographic size while diameter  3  is preferably a sub lithographic size achieved through the lithographic trimming procedure discussed with reference to  FIGS. 8-10 . Other dimensions and ranges of dimensions may also be used. 
         [0032]    A memory cell device  10  as described herein is readily manufacturable using standard lithography and thin film deposition technologies, without requiring extraordinary steps to form sub-lithographic patterns, while achieving very small dimensions for the region of the cell that actually changes resistivity during programming. In embodiments of the invention, the memory material may be a programmable resistive material, typically a phase change material, such as Ge 2 Sb 2 Te 5  or other materials described below. The region in the memory element  16  that changes phase is small; and accordingly, the magnitude of the reset current required for changing the phase is very small. 
         [0033]    Embodiments of memory cell device  10  include phase change based memory materials, including chalcogenide based materials and other materials, for memory element  16 . Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as Te a Ge b Sb 100-(a+b) , where a and b represent atomic percentages that total 100% of the atoms of the constituent elements. One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. (Ovshinsky &#39;112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge 2 Sb 2 Te 5 , GeSb 2 Te 4  and GeSb 4 Te 7 . (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky &#39;112 at columns 11-13, which examples are hereby incorporated by reference. 
         [0034]    Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These phase change materials are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly. 
         [0035]    Phase change materials can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state, and is referred to as a reset pulse. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state, and is referred to as a program pulse. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined empirically, without undue experimentation, specifically adapted to a particular phase change material and device structure. 
         [0036]    The following are short summaries describing four types of resistive memory materials. 
         [0037]    1. Chalcogenide Material
       Ge x Sb y Te z      x:y:z=2:2:5   Or other compositions with x: 0˜5; y: 0˜5; z: 0˜10   GeSbTe with doping, such as N—, Si-, Ti-, O—, C—, Al-, Ta- and their composites, or other element doping may also be used.   Formation method: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N 2 , and/or He, etc at the pressure of 1 mtorr˜100 mtorr. The deposition is usually done at room temperature. The collimater with aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. On the other hand, the combination of DC bias and the collimater can be used simultaneously.   The post deposition annealing treatment with vacuum or N2 ambient is sometimes needed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges 100 C to 400 C with an anneal time of less than 30 minutes.   The thickness of chalcogenide material depends on the design of cell structure. In general, a chalcogenide material with thickness of higher than 8 nm can have a phase change characterization so that the material exhibits at least two stable resistance states.       
 
         [0045]    2. CMR (Colossal Magnetoresistance) Material
       Pr x Ca y MnO 3      x:y=0.5:0.5   Or other compositions with x: 0˜1; y: 0˜1   Another CMR material that includes Mn oxide may be used   Formation method: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N 2 , O 2 , and/or He, etc. at the pressure of 1 mtorr˜100 mtorr. The deposition temperature can range from room temperature to ˜600 C, depending on the post deposition treatment condition. A collimater with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. On the other hand, the combination of DC bias and the collimater can be used simultaneously. A magnetic field of several tens of gauss to as much as a Tesla (10,000 gauss) may be applied to improve the magnetic crystallized phase.   The post deposition annealing treatment with vacuum or N 2  ambient or O 2 /N 2  mixed ambient may be needed to improve the crystallized state of CMR material. The annealing temperature typically ranges 400 C to 600 C with an anneal time of less than 2 hours.   The thickness of CMR material depends on the design of cell structure. The CMR thickness of 10 nm to 200 nm can be used to be the core material.   A buffer layer of YBCO (YBaCuO 3 , a kind of high temperature superconductor material) is often used to improve the crystallized state of CMR material. The YBCO is deposited before the deposition of CMR material. The thickness of YBCO ranges 30 nm to 200 nm.       
 
         [0054]    3. 2—Element Compound
       Ni x O y ; Ti x O y ; Al x O y ; W x O y ; Zn x O y ; Zr x O y ; Cu x O y ; etc   x:y=0.5:0.5   Other compositions with x: 0˜1; y: 0˜1   Formation method:   1. Deposition: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N 2 , O 2 , and/or He, etc. at the pressure of 1 mtorr˜100 mtorr, using a target of metal oxide, such as Ni x O y ; Ti x O y ; Al x O y ; W x O y ; Zn x O y ; Zr x O y ; Cu x O y ; etc. The deposition is usually done at room temperature. A collimater with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. If desired, they combination of DC bias and the collimater can be used simultaneously.   The post deposition annealing treatment with vacuum or N 2  ambient or O 2 /N 2  mixed ambient as sometimes needed to improve the oxygen distribution of metal oxide. The annealing temperature ranges 400 C to 600 C with an anneal time of less than 2 hours.   2. Reactive deposition: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar/O 2 , Ar/N 2 /O 2 , pure O 2 , He/O 2 , He/N 2 /O 2  etc. at the pressure of 1 mtorr˜100 mtorr, using a target of metal oxide, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The deposition is usually done at room temperature. A collimater with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several ten to several hundred volts is also used. If desired, the combination of DC bias and the collimater can be used simultaneously.   The post deposition annealing treatment with vacuum or N 2  ambient or O 2 /N 2  mixed ambient is sometimes needed to improve the oxygen distribution of metal oxide.   The annealing temperature ranges 400 C to 600 C with an anneal time of less than 2 hours.   3. Oxidation: By a high temperature oxidation system, such as furnace or RTP system. The temperature ranges from 200 C to 700 C with pure O 2  or N 2 /O 2  mixed gas at a pressure of several mtorr to 1 atm. The time can range several minute to hours. Another oxidation method is plasma oxidation. An RF or a DC source plasma with pure O 2  or Ar/O 2  mixed gas or Ar/N 2 /O 2  mixed gas at a pressure of 1 mtorr to 100 mtorr is used to oxidize the surface of metal, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The oxidation time ranges several seconds to several minutes. The oxidation temperature ranges room temperature to 300 C, depending on the degree of plasma oxidation.       
 
         [0065]    4. Polymer Material
       TCNQ with doping of Cu, C 60 , Ag etc.   PCBM-TCNQ mixed polymer   Formation method:   1. Evaporation: By thermal evaporation, e-beam evaporation, or molecular beam epitaxy (MBE) system. A solid-state TCNQ and dopant pellets are co-evaporated in a single chamber. The solid-state TCNQ and dopant pellets are put in a W-boat or a Ta-boat or a ceramic boat. A high electrical current or an electron-beam is applied to melt the source so that the materials are mixed and deposited on wafers. There are no reactive chemistries or gases. The deposition is done at a pressure of 10-4 torr to 10-10 torr. The wafer temperature ranges from room temperature to 200 C.   The post deposition annealing treatment with vacuum or N 2  ambient is sometimes needed to improve the composition distribution of polymer material. The annealing temperature ranges room temperature to 300 C with an anneal time of less than 1 hour.   2. Spin-coat: By a spin-coater with the doped-TCNQ solution at the rotation of less than 1000 rpm. After spin-coating, the wafer is put to wait the solid-state formation at room temperature or temperature of less than 200 C. The waiting time ranges from several minutes to days, depending on the temperature and on the formation conditions.       
 
         [0072]    Useful characteristics of a programmable resistive type of memory material, like a phase change material, include the material having a resistance which is programmable, and preferably in a reversible manner, such as by having at least two solid phases that can be reversibly induced by electrical current. These at least two phases include an amorphous phase and a crystalline phase. However, in operation, the programmable resistive material may not be fully converted to either an amorphous or crystalline phase. Intermediate phases or mixtures of phases may have a detectable difference in material characteristics. The two solid phases should generally be bistable and have different electrical properties. The programmable resistive material may be a chalcogenide material. A chalcogenide material may include GST. In following sections of the disclosure, the phase change or other memory material is often referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory cell as described herein is Ge 2 Sb 2 Te 5 . 
         [0073]      FIG. 3  is a schematic illustration of a memory array, which can be implemented as described herein. In the schematic illustration of  FIG. 3 , a common source line  28 , a word line  23  and a word line  24  are arranged generally parallel in the Y-direction. Bit lines  41  and  42  are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in block  45  are coupled to the word lines  23 ,  24 . An X-decoder and a set of sense amplifiers in block  46  are coupled to the bit lines  41  and  42 . The common source line  28  is coupled to the source terminals of access transistors  50 ,  51 ,  52  and  53 . The gate of access transistor  50  is coupled to the word line  23 . The gate of access transistor  51  is coupled to the word line  24 . The gate of access transistor  52  is coupled to the word line  23 . The gate of access transistor  53  is coupled to the word line  24 . The drain of access transistor  50  is coupled to the bottom electrode member  32  for memory element  35 , which has top electrode member  34 . The top electrode member  34  is coupled to the bit line  41 . Likewise, the drain of access transistor  51  is coupled to the bottom electrode member  33  for memory element  36 , which has top electrode member  37 . The top electrode member  37  is coupled to the bit line  41 . Access transistors  52  and  53  are coupled to corresponding memory elements as well on bit line  42 . It can be seen that the common source line  28  is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. In other embodiments, the access transistors can be replaced by diodes, or other structures for controlling current flow to selected devices in the array for reading and writing data. 
         [0074]      FIG. 4  is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit line  75  includes a memory array  60  implemented using circumferentially extending memory elements, on a semiconductor substrate. A row decoder  61  is coupled to a plurality of word lines  62 , and arranged along rows in the memory array  60 . A column decoder  63  is coupled to a plurality of bit lines  64  arranged along columns in the memory array  60  for reading and programming data from the side wall pin memory cells in the array  60 . Addresses are supplied on bus  65  to column decoder  63  and row decoder  61 . Sense amplifiers and data-in structures in block  66  are coupled to the column decoder  63  via data bus  67 . Data is supplied via the data-in line  71  from input/output ports on the integrated circuit  75  or from other data sources internal or external to the integrated circuit  75 , to the data-in structures in block  66 . In the illustrated embodiment, other circuitry  74  is included on the integrated circuit, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the thin film fuse phase change memory cell array. Data is supplied via the data-out line  72  from the sense amplifiers in block  66  to input/output ports on the integrated circuit  75 , or to other data destinations internal or external to the integrated circuit  75 . 
         [0075]    A controller implemented in this example using bias arrangement state machine  69  controls the application of bias arrangement supply voltages  68 , such as read, program, erase, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller. 
         [0076]      FIG. 5  depicts a cross-section of a pair of memory cell devices  10  formed on a semiconductor substrate. The structure of  FIG. 5  includes a memory cell access layer  56  and a memory cell layer  58 . Memory cell layer  58  includes a top electrode layer (bit line)  59  which, together with top electrode extensions  18 , create the top electrodes  14  of  FIG. 1 . Isolation structures such as shallow trench isolation STI dielectric trenches (not shown) isolate pairs of rows of memory cell access transistors. The access transistors are formed by common source region  76  in the substrate, and drain regions  78  and  80  in the substrate. Polysilicon word lines  82  and  84  form the gates of the access transistors. A dielectric fill layer  86  is formed over the polysilicon word lines  82 ,  84 . Contact plug structures  88  and  90  contact individual access transistor drains, and in the illustrated example, common source line  92  contacts source regions along a row in the array. In other embodiments, the common source line is implemented by a doped region in the substrate, such as an n+ doped region with optionally a silicide on the surface. The plug structure  88  acts as a terminal contacting the access transistor for bottom electrode  12  of memory cell device  10 . Plug structure  90  acts as a terminal contacting the access transistor for bottom electrode  12  of memory cell device  10 . 
         [0077]    It is preferred that all or part of the portions of bottom and top electrodes  12 ,  14  contacting memory element  16  comprise an electrode material, such as TiN, or another conductor selected for compatibility with the phase change material of memory element  16 . In the embodiment of  FIG. 1 , top electrode  14 , including top electrode extension  18 , and bottom electrode extension  17  are all made of TiN while the remainder of bottom electrode  12  comprises tungsten. Other types of conductors can be used for the plug structures and the top and bottom electrodes structures, including for example aluminum and aluminum alloys, TiN, TaN, TiAlN or TaAlN. Other conductors that might be used comprise one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, Ru and O. In some embodiments, such as described below with reference to  FIGS. 16 and 17 , all or parts of top and bottom electrode extensions  18 ,  17  may comprise a memory material, typically the same memory material as for memory element  16 . 
         [0078]    Memory cell device  10  and its method of manufacture will be described with reference to  FIGS. 6-15  and then back to  FIG. 5 . Referring now to  FIG. 6 , memory cell access layer  56  is seen to have a generally flat upper surface  96 . Upper surface  96  is partially defined by surfaces  98  at the ends of plugs  88 ,  90 . Next, as shown in  FIG. 7 , a layer  100  of an electrode material is deposited on upper surface  96  followed by a dielectric material layer  102  and then another layer  104  of an electrode material. Layers  100 ,  102 ,  104  are used to create bottom electrode extension  17 , dielectric material  20  and top electrode extension  18 , respectively.  FIG. 8  illustrates result of depositing a lithographic mask  106  on layer  104  aligned with electrode surfaces  98  of plugs  88 ,  90 . Both plugs  88  and  90  and the associated masks  106  have generally cylindrical cross-sectional shapes; however, other cross-sectional shapes, regular or irregular polygons and shapes having curved and/or straight sections are also possible with other embodiments. The width of mask  106  is preferably the minimum lithographic size associated with the lithographic process used. 
         [0079]      FIG. 9  illustrates results of a mask trimming step to reduce the lateral dimension, which is the width or diameter, of lithographic mask  106  to a sub lithographic dimension. The width or diameter of trimmed mask  108  is well below the minimum lithographic feature size used to create mask  106 . Trimming is typically by a photoresist oxygen plasma trimming process but may be by other processes. For example, silicon oxide hard mask processing can also be used. See, for example, U.S. Pat. No. 6,869,542 which discusses hard mask integrated etch processing. 
         [0080]    Those portions of layers  100 ,  102  and  104  not protected by trimmed lithographic mask  108  are shown in  FIG. 10  to have been etched away leaving, in this embodiment, generally cylindrical stacks  110  of materials including bottom electrode extension  17 , dielectric material  20  and top electrode extension  18 . 
         [0081]      FIG. 11  illustrates result of the deposition of a layer  112  of a memory material, as discussed above typically GST, from which memory element to  16  is made. Layer  112  of memory material covers the circumferentially extending the outer surfaces  113  of material stacks  110 .  FIG. 12  shows results of the deposition of a layer  114  of a dielectric material onto layer  112 . Dielectric material  26  is made from layer  114 . Dielectric material  26  acts as a thermal isolation dielectric material. Thereafter, as shown in  FIG. 13 , excess dielectric material of layer  114  not needed for thermal isolation dielectric material  26  is removed by an anisotropic reactive ion etch to leave the side wall dielectric material  26 . 
         [0082]      FIG. 14  illustrates results of a dielectric fill-in step in which a dielectric material  116 , such as SiO 2 , is deposited on the structure of  FIG. 13 . Two or more of dielectric materials  20 ,  26  (layer  114 ) and  116  may be the same material or may be different dielectric materials. 
         [0083]      FIG. 15  shows the results of a chemical mechanical polishing procedure on the structure of  FIG. 14 . Thereafter electrode material is deposited on the structure of  FIG. 15  to form top electrode layer  59  resulting in the structure of  FIG. 5 . 
         [0084]    In operation, current flows on a path including a terminal in an access device in contact with plug  88 , through bottom electrode  12 , through memory element  16 , and through top electrode  14 . An active region  120 , see  FIG. 1 , located along central portion  22  of memory element  16 , is the location at which the phase change occurs due to heat caused by the current flow. Active region  120  is at this location because it is spaced apart from the bottom and top electrodes  12 ,  14 , which act as heat sinks, as well as because it is thermally isolated through the use of dielectric materials  20  and  26 . Active region  120  is very small, reducing the magnitude of current needed for reset. 
         [0085]      FIGS. 16 and 17  illustrate alternative embodiments of portions of the memory cell device  10  of  FIG. 1 . The structure of  FIG. 16  differs from the structure of  FIG. 1  in that memory element  16  is a straight cylinder, as opposed to a cylinder with a flange portion at bottom electrode  12 . Each of bottom and top electrode extension  17  and  18  of the structure of  FIG. 16  includes a memory material portion  122  and a TiN portion  124  to provide thermal isolation for the memory material relative to the electrodes. In  FIG. 17  memory material portions  122  constitute the entire bottom and top electrode extensions  17 ,  18 . In the embodiments of  FIGS. 16 and 17 , one or both of memory material portions  122  may be the same memory material used for memory element  16 , but need not be so. The memory material for memory material portions  122  preferably has a lower thermal resistance than the memory material used for the side wall memory element  16 . 
         [0086]    The above descriptions may have used terms such as above, below, top, bottom, over, under, et cetera. These terms are used to aid understanding of the invention are not used in a limiting sense. 
         [0087]    While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. 
         [0088]    Any and all patents, patent applications and printed publications referred to above are incorporated by reference.