Abstract:
An apparatus converting three bits of binary data (B 1 , B 2 , B 3 ) into two ternary symbols (T 1 , T 2 ), in which even numbered pars of the ternary symbols (T 1 , T 2 ), where (T1=T2), are replaced by a pair of ternary symbols (T&#39; 1 , T&#39; 2 ) which do not correspond to any of the three bits of binary data (B 1 , B 2 , B 3 ). The replacement occurs when the respective symbols in a respective pair of ternary symbols (T 1 , T 2 ) are in the same ternary level; hence, a run-length of the same symbol can be restricted to four or less. Furthermore, the digital sum variation (DSV) is controlled in every synchronous block which is composed by the above-mentioned replaced output, thereby allowing a 3B-2T code which does not contain a DC component to be obtained. Moreover, inversion or noninversion of the synchronous pattern can be easily determined by distinguishing whether control of the DSV is applied or not to the synchronous block.

Description:
FIELD OF THE INVENTION AND RELATED ART STATEMENT 
     1. Field of the Invention 
     The present invention relates to a code conversion apparatus for generating a ternary code which is utilized for transmission and recording of a digital signal. 
     2. Description of the Related Art 
     A block arrangement as shown in FIG. 11 is conventionally used in order to record a digital signal. In the block arrangement, a data portion which is designated by &#34;information&#34; is added to a SYNC portion which is designated by &#34;synchronous pattern&#34;. The synchronous pattern is a synchronous signal for designating a head of the block, and the block is called a SYNC block. The block identifies a group of data which is punctuated every predetermined number of bits. Generally, the SYNC block is converted to a channel code having characteristics which are suitable for use with a recording and playback system, and the SYNC block is transmitted and is recorded. 
     At the present time, various channel codes are used, and one of them is a 3B-2T code which is a ternary code. The 3B-2T code is obtained by conversion of three bits of binary data (B 1 , B 2 , B 3 ) (Bi: 0, 1, i=1-3) which is composed by three bits to a pair of symbols (T 1 , T 2 ) (Ti: 0, 1, 2, i=1, 2) which are composed by ternary values. 
     A code conversion table for generating the 3B-2T code is shown in Table 1. Referring to Table 1, eight pairs of two symbols (T 1 , T 2 ) which are selected from nine pairs thereof are made to correspond one-to-one to eight pairs of bit patterns which are composed by three bits of binary data (B 1 , B 2 , B 3 ). Hence, symbol patterns which are composed of two symbols corresponding to the bit patterns which are composed of three bits are formed by one-to-one correspondence. 
     
                       TABLE 1______________________________________3B                      2TNo.     B.sub.1    B.sub.2                    B.sub.3  T.sub.1                                 T.sub.2______________________________________1       0          0     0        0   02       0          0     1        0   13       0          1     0        0   24       0          1     1        1   05       1          0     0        1   16       1          0     1        1   27       1          1     0        2   08       1          1     1        2   19       x          x     x        2   2______________________________________ 
    
     In the above-mentioned case, when one bit interval is designated by t b , one symbol interval t s  after 3B-2T conversion is shown by the following equation: 
     
         t.sub.s =3/2t.sub.b. 
    
     Therefore, a symbol frequency f s  (=1/t s ) corresponding to a bit frequency f b  (=1/t b ) is shown by 2/3f b , and a frequency bandwidth in 3B-2T code is reduced to 2/3 of that of the binary code. As a result, when the 3B-2T code is used, since a noise power is low and the symbol interval t s  is longer than the bit interval t b , the 3B-2T code has advantages in that it is resistant to variation in time axis such as peak-shift or jitter over the binary code. 
     As mentioned above, though the 3B-2T code is fundamentally superior as a channel code, there is a serious problem as shown hereinafter in its practical use. 
     Since the 3B-2T code contains a DC component, when a signal is transmitted through a rotary-transformer such as in a digital VTR, waveforms in both recording and playback are distorted by the influence of the DC component cut-off characteristics of the rotary transformer. As a result, a symbol error rate in playback is seriously diminished. In the case of the ternary code, on the other hand, if Digital Sum Variation (hereinafter referred to as DSV) which is defined by a difference between a number N 2  of symbols &#34;2&#34; and a number N 0  of symbols &#34;0&#34; in a sequence of symbols is always definite, the DC component is not contained. 
     Furthermore, as shown in Table 1, appearance of consecutive like symbols in the conventional 3B-2T code is high in probability, and a self-clocking function for recovering the clock from the playback signal is not realized. This is a serious defect for a channel code to be used for high density recording. 
     OBJECT AND SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a 3B-2T code which is suitable for high density recording and which overcomes the above-noted drawbacks of the prior art. 
     An apparatus for 3B-2T code conversion for converting three binary data bits (B 1 , B 2 , B 3 ) to two ternary symbols (T 1 , T 2 ) in accordance with the present invention additionally comprises: 
     detecting means for detecting a state wherein continuous occurrence of the same symbol exceeds four, and 
     replacing means for replacing an even numbered pair of ternary symbols (T 1 , T 2 , where T 1  =T 2 ), to ternary symbols (T&#39; 1 , T&#39; 2 ) which do not correspond to any of said three binary data bits (B 1 , B 2 , B 3 ) detected by said detecting means. 
     As a result, a run-length of the same symbols is limited to four and below, and a 3B-2T code which is superior in clock recovery ability is realized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a replacing circuit of an embodiment in accordance with the present invention; 
     FIG. 2 is a waveform showing a 3B-2T code of the present invention in comparison with the conventional 3B-2T code; 
     FIG. 3 is a timing chart showing operation of the circuit as shown in FIG. 1; 
     FIG. 4 is a block diagram of a circuit for controlling inversion or noninversion of data which is composed in a block; 
     FIG. 5 is a timing chart showing operation of the circuit as shown in FIG. 4; 
     FIG. 6 is a block diagram of a decoding circuit for decoding data which is composed in a block which is controlled by the circuit as shown in FIG. 1; 
     FIG. 7 is a block diagram of the circuit for inserting inversion or noninversion information of the data which is composed in a block; 
     FIG. 8 is a block diagram of the decoding circuit of the data which is composed in a block and which is controlled by inversion or noninversion; 
     FIG. 9 is a timing chart showing operation of the circuit as shown in FIG. 8; 
     FIG. 10 is a block diagram of a circuit for decoding a replaced sequence of symbols to the original sequence of symbols; 
     FIG. 11 is a figure showing an arrangement of a SYNC block of the prior art. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     &lt;First embodiment&gt; 
     The present invention achieves the above-mentioned code conversions using the circuit of FIG. 1. In FIG. 1, when plural pairs of ternary symbols as shown in the first or fifth line in Table 1 exist sequentially, the circuit of FIG. 1 may be used for realizing replacing means wherein even numbered pairs of symbols thereof are replaced by a pair of symbols as shown in the ninth line of Table 1. 
     The respective recording waveforms of the conventional 3B-2T code and a new 3B-2T code in accordance with the present invention are shown in FIG. 2. Referring to FIG. 2, level changes can be generated in sections of the new 3B-2T code of the present invention wherein level changes do not exist in the conventional code. In FIG. 2, three binary data bits (B 1 , B 2 , B 3 ) designate the input of three binary data bits, two ternary symbols (T 1 , T 2 ) designating the conventional 3B-2T code which is converted in accordance with Table 1, and two ternary symbols (T 1  &#39;, T 2  &#39;) designating the 3B-2T code in accordance with the present invention, where the mark &#34;*&#34; designates portions of the conventional 3B-2T code which are replaced in accordance with the present invention. 
     A block diagram of a circuit for achieving the present embodiment is shown in FIG. 1, and a timing chart showing operation of the circuit of FIG. 1 is shown in FIG. 3. Hereinafter, operation of the circuit as shown in FIG. 1 is elucidated by referring to FIG. 3. The input sequence of three binary data bits to the circuit shown in FIG. 1 is identical with that which is used in the example as shown in FIG. 2 and is shown in the following equation: 
     
         (B.sub.1, B.sub.2, B.sub.3)=(1, 0, 1), (0, 0, 0), (0, 0, 0), (1, 0, 0), (1, 0, 0). 
    
     At first, No. 1 detector 1 outputs an output &#34;1&#34; when three binary data bits (B 1 , B 2 , B 3 ) equal to a three bit pattern as shown in the first line of Table 1 is received, and it outputs an output &#34;0&#34; when three binary data bits (B 1 , B 2 , B 3 ) do no equal the three bit pattern in the first line of Table 1. No. 5 detector 2 outputs &#34;1&#34; when the three binary data bits (B 1 , B 2 , B 3 ) equal the three bit pattern as shown in the fifth line of Table 1, and it outputs output &#34;0&#34; when the three binary data bits (B 1 , B 2 , B 3 ) do not equal the three bit pattern as shown in the fifth line of Table 1. Thus, when the three binary data bits (B 1 , B 2 , B 3 ) equal the three binary data bits (1, 0, 1), an output of the No. 1 detector 1 is &#34;0&#34; and an output of the No. 5 detector 2 is also &#34;0&#34;. 
     Therefore, an output of AND gate 4 becomes &#34;0&#34; regardless of an output of D-flip-flop 3, which holds the output of No. 1 detector 1 corresponding to the last three binary data bits (B 1 , B 2 , B 3 ). In a similar manner, an output of AND gate 6 becomes &#34;0&#34; regardless of an output of D-flip-flop 5, which holds an output of the No. 5 detector 2 corresponding to the last three binary data bits (B 1 , B 2 , B 3 ). 
     After this process, D-flip-flop 7 for holding an output of AND gate 4, D-flip-flop 8 for holding an output of AND gate 6, D-flip-flops 3 and 5 and D-flip-flop 9 for holding the inputted three binary data bits (B 1 , B 2 , B 3 ) read and hold respective data which are applied to the respective inputs at a clock f 3B  of three bits per period. Consequently, an output of D-flip-flop 9 becomes the three binary data bits (1, 0, 1), and the outputs of D-flip flops 3, 5, 7 and 8 become &#34;0&#34;. Therefore, an output of OR gate 10 for calculating the logical OR of D-flip flops 7 and 8 also becomes &#34;0&#34;. 
     3B-2T converter 11 is a circuit for conventional 3B-2T conversion for generating two ternary code symbols (T 1 , T 2 ), in accordance with Table 1 and corresponding to the three binary data bits (B 1 , B 2 , B 3 ) from D-flip-flop 9. In the present state, since the three binary data bits (B 1 , B 2 , B 3 ) are (1, 0, 1), a two symbol ternary code (1, 2) is produced in the output of 3B-2T converter 11. 
     Switch 12 selects the output of 3B-2T converter 11 when the output of OR gate 10 is &#34;0&#34;, and it selects an output of No. 9 generator 13, which always generates a symbol pattern shown in the ninth line of Table 1, in which the two ternary code symbols (T 1 , T 2 ) are (2, 2), when the output of the OR gate 10 is &#34;1&#34;. 
     When the three binary data bits (B 1 , B 2 , B 3 ) are (1, 0, 1) as mentioned above, since the output of OR gate 10 is &#34;0&#34;, the two ternary code symbols (1, 2) from 3B-2T converter 11 are produced at the output 12-a of switch 12. 
     The second three binary data bit sequence (B 1 , B 2 , B 3 ) are (0, 0, 0) is next received. An output of the No. 1 detector 1 becomes &#34;1&#34;, but since the output of D-flip-flop 3 is &#34;0&#34;, the output of AND gate 4 becomes &#34;0&#34;. Furthermore, since the output of No. 5 detector 2 is &#34;0&#34;, the output of AND gate 6 also becomes &#34;0&#34;. 
     The outputs of the respective D-flip-flops after reading this new data into respective D-flip-flops at clock f 3B  are the inputted three binary data bits (0, 0, 0) on D-flip-flop 9, &#34;1&#34; on the D-flip-flop 3, &#34;0&#34; on D-flip-flop 7, &#34;0&#34; on D-flip-flop 5 and &#34;0&#34; on D-flip-flop 8, respectively. Therefore, the output of OR gate 10 becomes &#34;0&#34;, and the output of the 3B-2T converter 11 becomes the two ternary code symbols (0, 0) in accordance with Table 1. Thus, the output of the switch 12 becomes the two ternary code symbols (0, 0). 
     The third three binary data bit sequence (B 1 , B 2 , B 3 ) are (0, 0, 0) is next received. Since the output of the No. 1 detector 1 equals to &#34;1&#34; and the output of D-flip-flop 3 equals to &#34;1&#34;, the output of AND gate 4 becomes &#34;1&#34;. Furthermore, the output of AND gate 6 becomes &#34;0&#34;. Therefore, outputs of the respective D-flip-flops after clock f 3B  become as follows: 
     D-flip-flop 9: three binary data bits (0, 0, 0), 
     D-flip-flop 3: &#34;1&#34;, 
     D-flip-flop 7: &#34;1&#34;, 
     D-flip-flop 5: &#34;0&#34;, 
     D-flip-flop 8: &#34;0&#34;. 
     The output of the 3B-2T converter 11 is the two ternary code symbols (0, 0) corresponding to the three binary data bits (0, 0, 0), but since the output of OR gate 10 is &#34;1&#34;, switch 12 selects the output of No. 9 generator 13. Thus, the ternary code symbols (2, 2) arise in the output of the switch 12. On the other hand, the output &#34;1&#34; of D-flip-flop 7 resets the output of No. 1 detector 1 to &#34;0&#34;: 
     The fourth three binary data bit sequence (B 1 , B 2 , B 3 ) are (0, 0, 0) is next received the output of the No. 1 detector 1 is &#34;1&#34; in its normal state, the output of the No. 1 detector 1 becomes &#34;0&#34; by a reset signal &#34;1&#34; from D-flip flop 7, and the output of AND gate 4 also becomes &#34;0&#34;. Furthermore, the output of AND gate 6 becomes &#34;0&#34;. A dotted line in FIG. 3 shows a section of &#34;0&#34; which is made by the reset signal, from a state of &#34;1&#34; corresponding to the normal state. 
     After the above-mentioned process, the outputs of respective D-flip-flops become as follows at clock f 3B  : 
     D-flip-flop 9: three binary data bits (0, 0, 0), 
     D-flip-flop 3: &#34;0&#34;, 
     D-flip-flop 7: &#34;0&#34;, 
     D-flip-flop 5: &#34;0&#34;, 
     D-flip-flop 8: &#34;0&#34;. 
     Therefore, the output of OR gate 10 is &#34;0&#34;, and the output two ternary code symbols (0, 0) of 3B-2T converter 11 corresponding to three binary data bits (0, 0, 0) are issued on the output of switch 12. 
     When the fifth three binary data bit sequence (B 1 , B 2 , B 3 ) are (1, 0, 0) is received, the output of No. 5 detector 2 is &#34;1&#34;, and since the output of the D-flip-flop 5 is &#34;0&#34;, the output of AND gate 6 becomes &#34;0&#34;. On the other hand, since the output of No. 1 detector 1 is &#34;0&#34;, the output of AND gate 6 also becomes &#34;0&#34;. 
     After this process, the outputs of the respective flip-flops become as follows at clock f 3B  : 
     D-flip-flop 9: three binary data bits (1, 0, 0), 
     D-flip-flop 3: &#34;0&#34;, 
     D-flip-flop 7: &#34;0&#34;, 
     D-flip-flop 5: &#34;1&#34;, 
     D-flip-flop 8: &#34;1&#34;. 
     Therefore, the output of OR gate 10 is &#34;1&#34;, and the two ternary code symbols (2, 2) from No. 9 generator 13 arise at the output of switch 12. On the other hand, since the output of the No. 5 detector 2 becomes &#34;0&#34; by the reset signal &#34;1&#34; from D-flip-flop 8, even if the next three binary data bits (B 1 , B 2 , B 3 ) are (1, 0, 0), replacement by the output of No. 9 generator 13 is not made. 
     As mentioned above, according to the circuit as shown in FIG. 1 and the timing chart in FIG. 3, only even numbered pairs of plural consecutive symbols as shown in the fifth line of Table 1 are replaced. The same replacement can be applied to the pairs of symbols as shown in the ninth line of Table 1 in a similar manner. 
     A second embodiment of a circuit for code conversion in accordance with the present invention is shown in FIG. 4. The output of the circuit as shown in FIG. 1 is given to the circuit of FIG. 4 in the first embodiment, and it represents a symbol sequence which is composed in a block as shown in FIG. 11. 
     Counter 14 in FIG. 4 counts a difference DP of the number between symbol &#34;2&#34; and symbol &#34;0&#34; in the input block. Hold circuit 15 holds an output of counter 14 as one unit of every block. An output Y of inversion control circuit 16 equals &#34;1&#34; when all &#34;1&#34; and &#34;0&#34; of the respective blocks which are issued therefrom are reversed, it equals &#34;0&#34; when &#34;1&#34; and &#34;0&#34; are not reversed on the basis of output DP of hold circuit 15 and the output of hold circuit 17, which holds a value of the DSV at the last bit of the last block. Inversions control circuit 16 is operated in accordance with Table 1 in the above-mentioned process. 
     The output Y of inversion control circuit 16 is applied to an inversion control input of inverter 18. An output of one block delay circuit 19 is applied to another input of the inverter 18. Consequently, data which are composed in a block and which are controlled by inversion (Y=1) or noninversion (Y=0) as to the value of Y are issued to the output of inverter 18. 
     The output Y of inversion control circuit 16 is simultaneously applied to a select input of switch 20. Switch 20 selects output DP of hold circuit 15 when output Y equals &#34;0&#34; and selects an output of polarity inversion circuit 21 which changes DP to -DP when output Y equals &#34;1&#34;. The output DP&#39; of switch 20 (=DP:Y=0, =-DP:Y=1) is added to the output DSV of hold circuit 17 in adder 22, and is read into hold circuit 17. As a result, the DSV is maintained within a definite value without an increase of recording density by use of the circuit as shown in FIG. 4. 
     A timing chart showing operation of the circuit shown in FIG. 4 is shown in FIG. 5. Referring to FIG. 5, expression B j  designates a j numbered block, expression DP j  is a difference of numbers of &#34;2&#34; and &#34;0&#34; in the block B j , expression DSV j-1  designates the value of DSV until the last bit of block B j-1 , and expression B j  designates a block wherein all &#34;2&#34;s of the block B j  are inverted to &#34;0&#34; and all &#34;0&#34;s thereof is inverted to &#34;2&#34;s. Referring to FIG. 4 and FIG. 5, data which is composed in a block which maintains DSV in a definite value can be generated. 
     A decoder of the data which is composed in a block in the above-mentioned process is elucidated hereafter. For example, in a block diagram of the decoder as shown in FIG. 6, comparators 24 and 25 detect whether a synchronous pattern which is read in shift register 23 was inverted. If the reproduced synchronous pattern is not what is inverted, the detection signal of the synchronous pattern (hereinafter referred to as detection signal) is output only from comparator 24. On the contrary, if the detection signal is what is inverted, the detection signal is output only from comparator 25. 
     The detection signal from comparator 24 is inputted to the R input of R-S flip-flop 26, and the detection signal from comparator 25 is inputted to S input of R-S flip-flop 26. Hence, when the detection signal is output from the output of comparator 24, output Q of R-S flip-flop 26 becomes &#34;0&#34;. When the detection signal is output from the output of comparator 25, output Q of R-S flip-flop 26 becomes &#34;1&#34;. As a result, data groups which are transmitted through shift register 23 are controlled for inversion (Q=1) or noninversion (Q=0) corresponding to the outpt Q of R-S flip-flop 26. Inverter 27 accomplishes the above-mentioned control. As mentioned above, the data which is composed in a block and which is controlled under its DSV can be correctly decoded by using the decoder in accordance with the present invention as shown in FIG. 6. 
     This embodiment of the present invention thus can be realized by a very simple and small-scaled circuit as shown in FIG. 4 and FIG. 6. This embodiment thus provides a code without a substantial DC component without the requirement of increasing the recording density. Using such a simple circuit is also superior in practicality. 
     In the above-described embodiment, though inverse and noninverse processing of the data groups are operated in every block, the operation of inversion or noninversion is accomplished to the respective small blocks which are divided from a block, as well and in order to designate which small block is controlled, a suitable synchronous pattern is selected so that the DSV can be controlled in a smaller unit. 
     &lt;Second embodiment&gt; 
     In a circuit of the second embodiment, inversion or noninversion information for a sequence of symbols for holding the DSV within a definite value is inserted in other portions besides the synchronous pattern. In the present embodiment, even if burst error arises in the synchronous pattern, a previous sequence of symbols from playback data before inversion is correctly decoded. 
     More particularly, when the synchronous pattern detection signal S j  corresponding to block B j  cannot be detected due to symbol error of the synchronous pattern of block B j , the embodiment is effective to jointly use synchronous signal back up means for backing up the synchronous signal back up means for backing up the synchronous signal corresponding to block B j  by using detection signal S j-1  of prior block B j-1  of block B j  or a detection signal S j+1  of following block B j+1  of block B j . 
     An example of a circuit block diagram for embodying the third embodiment is shown in FIG. 7. The output of the circuit as shown in FIG. 1 is inputted to the circuit as shown in FIG. 7, and the latter circuit acts to insert inversion or noninversion information of data which is composed in block into a blank space of a block, for example, in a portion of the postamble in addition to the synchronous pattern. 
     Referring to FIG. 7, inversion information generating circuit 28 generates a symbol pattern of symbols Im which is equal to numbers of &#34;2&#34; and &#34;0&#34;, for example, 20202020 (Im=8). Counter 29 outputs &#34;1&#34; during symbols Im from a starting point of the postamble in every block. In that time, and only when the output of the counter 29 is &#34;1&#34;, the inversion information generating circuit 28 sequentially outputs a symbol pattern of symbols Im. Therefore, after the finish of issuing of the symbol pattern of symbols Im, the output of counter 29 becomes &#34;0&#34;. 
     On the other hand, the symbol pattern from inversion information generating circuit 28 is controlled for inversion or noninversion of the output Y of inversion control circuit 16 as shown in FIG. 1 in an inverter 30. In other words, the symbol pattern (Y=0) which is output by inversion information generating circuit 28 or a symbol pattern (Y=1), wherein all &#34;2&#34;s of the symbol pattern are inverted to &#34;0&#34;s and all &#34;0&#34; thereof are inverted to &#34;2&#34;, are issued from the output of inverter 30. 
     Switch 31 selects an output of inverter 18 as shown in FIG. 1 when the output of counter 29 is &#34;0&#34;, and when the output of counter 29 is &#34;1&#34;, selects the output of inverter 30. Hence, the output of inversion information generating circuit 28 or the inverted pattern thereof can be inserted between the starting point of the postamble and symbols Im in the output of switch 31. Furthermore, if the symbol pattern is inserted, a difference of numbers of &#34;2&#34; and &#34;0&#34; in the block can be held at a constant value, because a condition for inversion or noninversion of the block is maintained by selection of the symbol pattern which has the same number of &#34;2&#34;s and &#34;0&#34;s as a symbol pattern which is generated in inversion information generating circuit 28. 
     &lt;Third embodiment&gt; 
     The present embodiment relates to a decoder for correctly decoding a previous sequence of symbols before inversion control by the playback data, and additionally to a decoder using a synchronous signal protection means as described hereinafter. 
     Namely, in the synchronous signal protection means of the present invention, when synchronous pattern detecting signal S j  corresponding to the block B j  cannot be detected due to a symbol error in the synchronous pattern of block B j , a synchronous signal to the block B j  is backed up by using a detecting signal S j-1  of a block B j-1  which is immediately preceding the block B j  or a detecting signal S j+1  of a block B j+1  which is following the block B j . 
     Such a decoder is elucidated referring to the block diagram of FIG. 8. The decoder as shown in FIG. 8 has three functions as will be described below. 
     The first function is to detect whether the synchronous pattern is inverted or not, and also whether the data which is composed in a block is decoded responding to the detected signal when the synchronous pattern is detected in a manner as with the decoder shown in FIG. 4. 
     The second function is to decide a position of the synchronous pattern by a protection synchronous signal from the synchronous signal protection circuit and to decode the data which is composed in the block by distinguishing which original synchronous pattern is similar to the synchronous pattern when the synchronous pattern has an error so that detection in the comparator is impossible. 
     The third function is to stop decoding by distinction of the synchronous pattern, and to decode the data which is composed in a block by using inversion information which is inserted by other means when the synchronous pattern has numerous error symbols. 
     The number of symbols in the synchronous pattern is designated by S s , the number of symbols in one block is designated by N s , and furthermore, and inverted synchronous pattern is designated by S p . Under the above-mentioned designation, shift register 32 in FIG. 8 has a number of stages S s , comparator 33 outputs &#34;1&#34; only when the output of shift register 32 equals the synchronous pattern S p , and comparator 34 output &#34;1&#34; only when the output of shift register 32 equals the synchronous pattern S p . Shift register 32 and comparators 33 and 34 are the main circuits for achieving the first function. 
     Shift register 35 has stages number of S s , and counting circuit 36 counts a coincided number of symbols in comparison between the output of shift register 35 and synchronous pattern S p  and holds them. Comparison circuit 37 outputs &#34;1&#34; when an output of counter 36 is X or more, and outputs &#34;0&#34; during a period which is shorter than one block with it is less than X. The value of X is suitable to be a minimum value which is not less than (S s  +1)/2. 
     Counter 38 counts the number of coinciding symbols in comparison between the output of shift register 35 and synchronous pattern S p  and holds the number. Comparison circuit 39 outputs &#34;1&#34; when the output of counter 38 is X or more, and outputs &#34;0&#34; during a period which is shorter than one block when it is less than X. 
     Furthermore, delay circuit 40, OR gates 41, 42 and two block delay circuit 43 generate signals, which show all symbols of the synchronous pattern and which exist in shift register 35. Delay circuit 40 delays the output of shift register 32 during one block. Therefore, when all symbols of the synchronous pattern of block B j+1 , which is numbered as j+1 when it exists in shift register 32, all symbols of the synchronous pattern of block B j  which is preceding to block B j+1  exist in shift register 35. At that time, a logical OR of the synchronous signals for block B j+  1, B j  and B j-1  is issued on the output of OR gate 41. It is a logical OR of the following three synchronous signals, namely, the synchronous signals which are outputs from comparators 34 and 35 for the synchronous pattern of block B j+1 , the synchronous signal which is intermediate output of 2-block delay circuit 43, which output is made by delaying an output of OR gate 42 for the synchronous pattern by one block, and the synchronous signal which is issued on the output of OR gate 42 for the synchronous pattern of block B j+1 . 
     Therefore, except for the case that errors exist in the synchronous pattern of three consecutive blocks or more, a point of time wherein all symbols of the synchronous pattern exist in shift register 35 can be specified. Furthermore, since the number N s  of symbols of the synchronous pattern is at most 50 symbols and an error rate of the symbols is at worst 1×10 -3 , a reliability wherein the error of the synchronous pattern arises in three consecutive blocks is very low, and hence, practicality of the present embodiment is not spoiled. 
     Shift register 35, counters 36 and 38, comparison circuits 37 and 39, delay circuit 40, OR gates 41 and 42 and 2-block circuit 43 are thus the main circuits for achieving the above-mentioned second function. 
     The output of comparator 37 is directly connected to input R of R-S flip-flop 44, and the output of comparator 39 is directly connected to input S of R-S flip-flop 44. Output Q of R-S flip-flop 44 equals to &#34;0&#34; when its input R is &#34;1&#34;, and equals to &#34;1&#34; when its input S is &#34;1&#34;. Also, the output of switching circuit 45 is &#34;0&#34; when both outputs of comparison circuits 37 and 39 are &#34;0&#34;, and &#34;1&#34; in another case. The output of switching circuit 45 is held during one block. 
     Usually, the reliability when random errors concentrate on the synchronous pattern is very low, and the number of error symbols in the synchronized pattern is at most three symbols in the case of the random error. Therefore, it is sufficient to set the value X to be three or four in comparison circuits 37 and 39. 
     On the other hand, in the case of a digital VTR, a burst error is generated in trick play or due to drop out. When the burst error is generated at the head of the block and the head part is lost, a pattern which is very different from the right synchronous pattern exists at the head symbol pattern of the block i.e., at a position wherein the synchronous pattern should exist. 
     As mentioned above, since concentration of the random error in the synchronous pattern is very low in probability, when the difference of five or six symbols exists between patterns which exists at a position wherein synchronous patterns of the block should be and the right synchronous pattern, a burst error is deemed to have been generated. In the above-mentioned case, it makes no sence to decide which synchronous pattern of S p  or S p  is analogous with this symbol pattern. Therefore, in the embodiment, the operation for detecting inversion/noninversion information of data, which is composed in a block from a synchronous pattern, is not accomplished for a synchronous pattern wherein both outputs of comparator 37 and 39 in FIG. 8 become zero. However, inversion information of symbol Im which is inserted by the circuit of FIG. 5 is detected and is decoded. Delay circuit 46, shift register 47, counter 48 and comparison circuit 49 are used for the above-mentioned process. 
     Timing is selected by delay circuit 46 so that all inversion and noninversion information of symbol Im are contained in shift register 47 having Im stages at a point of time wherein the output of OR gate 41 becomes zero. Counter 48 counts and a number of coinciding symbols between the data of shift register 47 at the point of time and the symbol pattern for inversion information and noninversion information, for noninverted symbol Im. Comparison circuit 49 outputs &#34;0&#34; when output of counter 48 is less than Im/2, and outputs &#34;1&#34; during one block when the output of counter 48 is Im/2 or more. 
     Switch 50 selects output Q of R-S flip-flop 44 when an output of switching circuit 45 is &#34;1&#34;, and selects an output of comparison circuit 49 when the output of switching circuit 45 is &#34;0&#34;. Hence, correctly decoded data, which is composed in a block, is issued from the output of inversion circuit 51 wherein when the outputs of shift register 35 and switch 50 are inputted. 
     A timing chart showing the operation of the present embodiment as shown in FIG. 8 is shown in FIG. 9. In FIG. 9, a block numbered by j is designated by B j , and a block, wherein all &#34;2&#34;s in the block B j  are inverted, is designated by B j . Furthermore, each block is composed by a synchronous pattern S p , a group of data designated as &#34;data&#34;, inversion information I and postamble &#34;*&#34;. Outputs of the respective shift registers 32, 35 and 47 in FIG. 8 are shown by output waveforms on the last stage of the respective shift registers. Star marks &#34;*&#34; in FIG. 9 designate parts which are influenced by burst error. 
     Correct decoding can be achieved by using the circuit as shown in FIG. 8 in spite of error in the synchronous pattern as shown in FIG. 9. Dotted lines in FIG. 9 show synchronous pulses which cannot be detected due to interference from outside, and a chain line shows a portion where the value cannot be known. 
     &lt;Fourth embodiment&gt; 
     This embodiment relates to a circuit for decoding an original sequence of symbols from a sequence of symbols which is replaced by the process as shown in the first embodiment, and furthermore, for decoding a sequence of bits corresponding to these symbols. 
     In 3B-2T code conversion in accordance with the present invention, for pairs of symbols as shown on the first line or the fifth line of Table 1, when these pairs continue, even numbered pairs of symbols are replaced by a pair of symbols as shown in the ninth line of Table 1. Therefore, the three original bits are correctly decoded by a process wherein the pair as shown in the ninth line is replaced by a pair of the last symbol in playback. 
     The above-mentioned decoding is elucidated on a decoding circuit in FIG. 10. Referring to FIG. 10, a reproduced sequence of symbols is transmitted to 2T-3B converter 52 and No. 9 detector 53. 
     In the 2T-3B converter 52, a pair of reproduced ternary symbols (T 1 , T 2 ) is inversely converted to three binary data bits (B 1 , B 2 , B 3 ) in accordance with Table 1. No. 9 detector 53 outputs &#34;1&#34; when the pair of reproduced ternary symbols (T 1 , T 2 ) equals to the symbol pattern of the ninth line of Table 1, and outputs &#34;0&#34; when the pair of reproduced ternary sumbols (T 1 , T 2 ) is not equal to the symbol pattern of the ninth line of Table 1. Switch 54 selects the output of 2T-3B converter 52 when the output of No. 9 detector 53 is &#34;0&#34;, and selects the output of D-flip-flop 55, which holds the output which is one pair ago of 2T-3B converter, when the output of No. 9 detector 53 is &#34;1&#34;. 
     Hence, the output of 2T-3B converter 52 becomes an output of the decoder if the pair of reproduced ternary symbols (T 1 , T 2 ) is not equal to the symbol pattern of the ninth line of Table 1, and a three bit pattern corresponding to the pair of reproduced symbols which is one pair ago is selected and is decoded if the pair of reproduced ternary (T 1 , T 2 ) is equal to a symbol pattern of the ninth line in Table 1. That is to say, the three original bits are correctly decoded, and also introduction of the ninth symbol pattern which has no one-to-one correspondence to the three bit pattern is avoided. 
     As to 2T-3B converter 52 in FIG. 10, when a pair of reproduced symbols is a symbol pattern of the ninth line of Table 1, the output may be freely selected by the three-bit pattern. Since two pairs of a single pattern of the ninth line in the output are not consecutively issued, it is not issued from the decoder. 
     Thus, as mentioned above, in the present invention the new 3B-2T code having a self-clock function is easily achieved without losing the excellent features of the conventional 3B-2T code. Moreover, 3B-2T code which does not contain a DC component is obtainable by a simple circuit. Therefore, the code in accordance with the present invention is suitable for a digital VTR, which requires the self-clock function and the code having no DC component. Furthermore, the code is freely applicable to other systems wherein high density recording is required. 
     As mentioned above, in the present invention, a new 3B-2T code which is superior to the conventional 3B-2T code is realized by a simple circuit, and high practical effect is obtained.