Abstract:
A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.

Description:
FIELD 
     This disclosure relates to error checking and in particular to use of Cyclic Redundancy Check for error checking. 
     BACKGROUND 
     A polynomial is a mathematical expression of one or more algebraic terms, for example, “a+bx+cx 2 ”, each of which consists of a constant (a, b or c) multiplied by one or more variables (x) raised to a nonnegative integral power. A fixed size remainder of binary division of a data block by an n-bit polynomial may be used to verify that there were no transmission errors when transmitting the data block from a source to a destination. An n-bit polynomial applied to a data block of arbitrary length detects any single error burst that is less than or equal to n bits. 
     The fixed size remainder is computed for a data block at a source and is transmitted with the data block. The n-bit polynomial is applied to the received data block at the destination to re-compute the fixed size remainder and the recomputed fixed size remainder is compared with the fixed size remainder transmitted with the data block to verify that there were no transmission errors. 
     A Cyclic Redundancy Check (CRC) is a term that is given to both a fixed size remainder (a residue of binary division of an arbitrary length data block by a fixed size polynomial) and the function to produce the fixed size remainder. There are a plurality of n-bit polynomials that are used to compute a CRC. Most commonly used CRCs use the Galois finite field GF (2) having a finite field of two elements, 0 and 1. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, in which like numerals depict like parts, and in which: 
         FIG. 1  illustrates an embodiment of a plurality of reduction stages used to compute a residue from a 64-bit input and a 32-bit CRC; 
         FIG. 2  illustrates an embodiment of the CRC circuit shown in  FIG. 1 . 
         FIG. 3  illustrates an embodiment of the first three reduction stages shown in  FIG. 2 ; 
         FIG. 4  illustrates an embodiment of a 8×32 multiplier that applies a one level application of Karatsuba (KA); 
         FIG. 5  illustrates an embodiment of a 16×32 multiplier that applies a one level application of Karatsuba (KA); 
         FIG. 6  illustrates an embodiment of a 16×32 multiplier that applies a two level application of Karatsuba (KA); and 
         FIG. 7  is a flowgraph illustrating an embodiment of a method for selecting an optimal multiplication algorithm to be used a reduction stage used to compute a CRC residue. 
     
    
    
     Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims. 
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a system  100  that includes an embodiment of a Cyclic Redundancy Check (CRC) unit  104  that computes a fixed size remainder (a residue of binary division of an arbitrary length data block by a fixed size polynomial) according to the principles of the present invention. 
     The system  100  includes a processor  101 , a Memory Controller Hub (MCH)  102  and an Input/Output (I/O) Controller Hub (ICH)  104 . The MCH  102  includes a memory controller  106  that controls communication between the processor  101  and memory  110 . The processor  101  and MCH  102  communicate over a system bus  116 . 
     The processor  101  may be any one of a plurality of processors such as a single core Intel® Pentium IV® processor, a single core Intel Celeron processor, an Intel® XScale processor or a multi-core processor such as Intel® Pentium D, Intel® Xeon® processor, or Intel® Core® Duo processor or any other type of processor. 
     The memory  110  may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronized Dynamic Random Access Memory (SDRAM), Double Data Rate 2 (DDR2) RAM or Rambus Dynamic Random Access Memory (RDRAM) or any other type of memory. 
     The ICH  104  may be coupled to the MCH  102  using a high speed chip-to-chip interconnect  114  such as Direct Media Interface (DMI). DMI supports 2 Gigabit/second concurrent transfer rates via two unidirectional lanes. The ICH  104  includes the CRC unit  104 . The ICH  104  may also include a storage I/O controller  120  for controlling communication with at least one storage device  112  coupled to the ICH  104 . The storage device  112  may be, for example, a disk drive, Digital Video Disk (DVD) drive, Compact Disk (CD) drive, Redundant Array of Independent Disks (RAID), tape drive or other storage device. The ICH  104  may communicate with the storage device  112  over a storage protocol interconnect  118  using a serial storage protocol such as, Serial Attached Small Computer System Interface (SAS) or Serial Advanced Technology Attachment (SATA). 
       FIG. 2  illustrates an embodiment of the CRC circuit shown in  FIG. 1 . Computing a CRC requires calculating the remainder resulting from the division of the input data by a generator value. In the embodiment shown in  FIG. 2 , a CRC is computed for a 32-bit segment  220  of a data stream. The 32-bit segment  220  is shifted by 32-bits  124  and an XOR operation  128  is performed with the 32-bit segment  202  and any pre-existing residue (remainder)  222  which is also shifted by 32-bits  226 . The XORed result (input data) and the k-bits of the respective pre-computed polynomials g i (x) are used to compute the CRC residue in stages  206   a - 206   f  Successive stages  206   a - 206   e  reduce input data by i-bits until a residue value is output by stage  206   f . The residue is fed back  222  for use in processing the next 32-bit segment  220  of the data stream. The residue remaining after the final message portion  220  is applied is the CRC residue determined for the data stream as a whole. The CRC residue can either be appended to the data stream or compared with a received CRC value in the data stream to determine whether data corruption likely occurred. 
       FIG. 3  illustrates an embodiment of the first three reduction stages  206   a ,  206   b ,  206   c  shown in  FIG. 2 . Pre-computed (fixed value) polynomials g16, g8 and g4 are derived from the 32-bit CRC and are each stored in a respective one of three storage elements  302   a ,  302   b ,  302   c . The pre-computed polynomials are multiples of the 32-bit CRC polynomial over Galois Field (GF)(2). The storage elements  302   a , . . . ,  302   c  may be registers or memory locations in a memory such as Dynamic Random Access Memory (DRAM), flash memory or any other type of memory. 
     The pre-computed polynomials g16, g8 and g4 are used to successively reduce a block of data (data segment) into smaller intermediate values in order to produce a CRC residue. The form of the pre-computed polynomials allows the plurality of stages to perform many of the calculations in parallel by processing mutually exclusive regions of the block of data in parallel. Performing calculations in parallel reduces the time to compute the CRC residue. For example, for a 32-bit input data block, g16 reduces the 16 Most Significant Bits of the 32-bit input data block, g8 reduces the next 8 MSBs and g4 reduces the next 4 MSBs. These reductions may be referred to as the various stages of the reduction. 
     Referring to  FIG. 3 , in the embodiment shown for a 64-bit input data segment, the first reduction stage  206   a  receives a 64-bit input data segment and reduces the input data segment using the g16 polynomial. First, a 16×32 multiply operation is performed with the 16 Most Significant Bits (MSB)s of the input data segment and the 32-bit polynomial g16. Next, an Exclusive OR (XOR) operation is performed on the 48-bit result of the multiply operation and the 48 Least Significant Bits (LSB)s of the input data segment to compute a 48-bit output from the first reduction stage  206   a.    
     The second reduction stage  104 - 2  receives a 48-bit input data segment from the first stage  206   a  and reduces the input data segment using the g8 polynomial. First, an 8×32 multiply operation is performed using the 8 MSBs of the input data segment and the 32-bit g8 polynomial. Next, an XOR operation is performed using the 40-bit result of the multiply operation and the 40 Least Significant Bits (LSB)s of the input data segment to compute a 40-bit output that is forwarded to the third reduction stage  206   c.    
     The third reduction stage  206   c  receives a 40-bit input from the second stage  206   b  and reduces the input data segment using the g4 polynomial. First, a 4×32 multiply operation is performed with the 4 MSBs of the 40-bit input data segment and the 32-bit g4 polynomial. Then, the third reduction stage performs an XOR operation with the 36-bit result of the multiply operation and the 36 Least Significant Bits (LSB)s of the 40-bit input to provide a 36 bit output that is forwarded to a next reduction stage  206   d  ( FIG. 2 ) to continue to compute the residue. 
     The use of storage elements  302   a , . . . ,  302   c  to store pre-computed polynomials allows the 32-bit CRC to be selectable (programmable) through selection of the appropriate pre-computed polynomials that are loaded into the storage elements. 
     As shown in  FIG. 3 , each reduction stage  206   a , . . . ,  206  operates on operands with sizes (number of bits) that are asymmetric, that is, the multiplier and multiplicand have a different number of bits and the multiplier is decreased by half in each successive reduction stage (16, 8, 4). The sizes of the operands (multiplier, multiplicand) become more asymmetric with each successive stage. For example, the sizes of the input operands (multiplicand, multiplier) to the multiply operation in the various stages are 32:16 (first stage), 32:8 (second stage) and 32:4 (third stage). 
     The multiply operations in the reduction stages  206   a - 206   c  may be performed by a classical carry-less multiplication of the form i*32, however this is suboptimal. In an embodiment of the present invention, each of the plurality of reduction stages to produce a residue for a block of data is optimized to decrease area used to perform the reduction while maintaining the same delay through the plurality of reduction stages  206   a , . . .  206   f.    
     The schoolbook method to multiply two polynomials is to multiply each term of a first polynomial by each term of a second polynomial. For example, a first polynomial of degree 1 with two terms a 1 x+a 0  may be multiplied by a second polynomial of degree 1 with two terms b 1 x+b 0  by performing four multiply operations and three addition operations to produce a polynomial of degree 2 with three terms as shown below:
 
( a   1   x+a   0 )( b   1   x+b   0 )= a   1   b   1   x   2 +( a   0   b   1   x+a   1   b   0   x )+ a   1   b   1  
 
     The number of multiply operations and Arithmetic Logical Unit (ALU) operations increases with the number of terms in the polynomials. For example, using the schoolbook method, the number of multiply operations to multiply two polynomials each having n terms is n 2  and the number of additions is (n−1) 2 . 
     The Karatsuba algorithm (KA) reduces the number of multiply operations compared to the schoolbook method by multiplying two two-term polynomials (A(x)=(a 1 x+a 0 ) and B(x)=(b 1 x+b 0 )), each having two coefficients ((a 1 ,a 0 ) and (b 1 b 0 )), using three scalar multiplications instead of four multiplications as shown below:
 
 C ( x )=( a   1   x+a   0 )( b   1   x+b   0 )= a   1   b   1   x   2 +(( a   0   +a   1 )( b   0   +b   1 )− a   0   b   0   −a   1   b   1 )+ a   0   b   0  
 
     Thus, four additions and three multiplications are required to compute the result C(x) of multiplying two two-term polynomials using the Karatsuba algorithm. The KA algorithm relies on the ability to perform shift operations faster than a standard multiplication operation. 
     The KA algorithm is typically applied to symmetric multiplications, where the operands (multiplier and multiplicand) are the same size. However, the multiply operations in reduction stages  206   a , . . . ,  206   c  are asymmetric. Furthermore, a naïve application of KA increases the critical path significantly while reducing area. In addition, there may be a number of levels of application of KA that typically range between 2 and 4. The number of levels is limited by the smaller of the operand sizes. For example, one or two levels of application of KA are optimal for computing the product of a 16-bit multiplier by a 32-bit multiplicand and one level of application of KA is optimal for computing the product of an 8-bit multiplier by a 32-bit multiplicand. A classical multiplier is optimal for computing a product of a 4-bit multiplier and a 32-bit multiplicand. In an embodiment of the present invention, the type of multiplication technique, multi-stage KA, single-stage KA or classical multiplier is selected for each stage based on the operand size. 
       FIG. 4  illustrates an embodiment of an 8×32 multiplier that applies a one level application of Karatsuba (KA). The 8×32 multiplier may be used in the second reduction stage  206   b  shown in  FIG. 3 . As discussed earlier, the input data segment is reduced by 8-bits in the second reduction stage  206   b . To perform the reduction by 8-bits, the multiplier applies a one level application of KA to perform a multiply operation on a 32-bit multiplicand (represented by A in  FIG. 4 ) and an 8-bit multiplier (represented by B in  FIG. 4 ). 
     The Karatsuba algorithm (KA) reduces the number of multiply operations compared to the schoolbook method by multiplying two two-term polynomials (A(x)=(a 1 x+a 0 ) and B(x)=(b 1 x+b 0 )), each having two coefficients ((a 1 ,a 0 ) and(b 1 b 0 )), using three scalar multiplications instead of four multiplications as shown below:
 
 C ( x )=( a   1   x+a   0 )( b   1   x+b   0 )= a   1   b   1   x   2 +(( a   0   +a   1 )( b   0   +b   1 )− a   0   b   0   −a   1   b   1 )+ a   0   b   0  
 
     Thus, four additions and three multiplications (that is, (1) a 1 b 1 , (2) a 0 b 0 , and (3) ((a 0 +a 1 )(b 0 +b 1 )) are required to compute the result C(x) of multiplying two two-term polynomials using the Karatsuba algorithm. 
     As shown in  FIG. 4 , the 32-bit multiplicand A is subdivided into eight 4-bit elements labeled a 7 -a 0  and the 8-bit multiplier B is subdivided into two 4-bit elements labeled b 1  and b 0 . The product C is A×B which is computed by applying KA to the following groups of elements of A and B: 
     (1) b 1 , b 0  and a 1 , a 0 ; 
     (2) b 1 , b 0  and a 2 , a 3 ; 
     (3) b 1 , b 0  and a 5 , a 4 ; and 
     (4) b 1 , b 0  and a 7 , a 6  in the order shown in  FIG. 4 . 
     The following four products (P 0 -P 3 ) are computed by applying KA to elements in A and B.
 
 P 0=( a   1   x+a   0 )( b   1   x+b   0 )= a   1   b   1   x   2 +(( a   0   +a   1 )( b   0   +b   1 )− a   0   b   0   −a   1   b   1 )+ a   0   b   0  
 
 P 1=(( a   3   x+a   2 )( b   1   x+b   0 )= a   3   b   1   x   2 +(( a   2   +a   3 )( b   0   +b   1 )− a   2   b   0   −a   3   b   1 )+ a   2   b   0 )2 8  
 
 P 2=(( a   5   x+a   4 )( b   1   x+b   0 )= a   5   b   1   x   2 +(( a   4   +a   5 )( b   0   +b   1 )− a   4   b   0   −a   1   b   5 )+ a   4   b   0 )2 16  
 
 P 3=(( a   7   x+a   6 )( b   1   x+b   0 )= a   7   b   1   x   2 +(( a   6   +a   7 )( b   0   +b   1 )− a   6   b   0   −a   7   b   1 )+ a   6   b   0 )2 24  
 
     As shown, P 1  is shifted by eight bits, P 2  is shifted by 16-bits and P 3  is shifted by 24 bits. The products are then XORed to provide a 40-bit result C(x).
 
 C ( x )= P 0+ P 1+ P 2+ P 3.
 
     The worst case path for each product P 0 -P 3  is the term that includes both multiplication and addition, for example, ((a 6 +a 7 )(b 0 +b 1 ) when computing P 3  or ((a 2 +a 3 )(b 0 +b 1 ) when computing P 1 . 
     With a straightforward construction of an XOR tree after the core multipliers for the Karatsuba algorithm, the critical path delay of the multiplication circuit is the delay of the XOR operations before the core multipliers, delay of the core multiplier and the delay of the XOR tree. This may be reduced through the use of the asymmetric property of the Karatsuba Multiplier. For example, there are a different number of multiplication levels for computing different bits of the 40-bit result C(39:0). As shown in  FIG. 4 , the critical path is asymmetric with the lower order four bits C(3:0) of the result have one level of computation, C(7:0) and C(39:36) have four levels of computation, C(35:8) have five levels of computation. Also, as shown in  FIG. 3 , the Most Significant Bits (MSB)s of the input to each stage, for example, input[63:48] in the first level and input[47:0] in the next level are in the critical path because they are input to a multiplier with multiple levels of computation whereas the Least Significant Bits (LSBs) are only input to accumulators. 
     Thus, a critical path may be reduced for a particular bit or bits of the product by bypassing a multiplier. For example, any of product bits C[35:8] may be computed through a redundant set of XOR gates instead of through the Karatsuba multiplier, that is, the Karatsuba multiplier may be bypassed for these particular bits. The set of XOR gates may be used to compute C[35]=a 35 *b 0 +a 34 *b 1 +a 33 * b 0 +a 35 *b 2  . . . a 0 *b 35  to reduce this critical path. 
       FIG. 5  illustrates an embodiment of a 16×32 multiplier that applies a one level application of Karatsuba (KA). The 16×32 multiplier may be used in the first reduction stage  206   a  shown in  FIG. 3 . As discussed earlier, the input data segment is reduced by 16-bits in the first reduction stage  206   a . To perform the reduction by 16-bits, the multiplier applies a one level application of KA to perform a multiply operation on a 32-bit multiplicand (represented by A in  FIG. 5 ) and an 16-bit multiplier (represented by B in  FIG. 5 ). 
     As shown in  FIG. 5 , the 32-bit multiplicand A is subdivided into four 8-bit elements labeled a 4 -a 0  and the 16-bit multiplier B is subdivided into two 8-bit elements labeled b 1  and b 0 . The product C is A×B which is computed by applying KA to the following groups of elements of A and B: 
     (1) b 1 , b 0  and a 1 , a 0 ; and 
     (2) b 1 , b 0  and a 2 , a 3 ; in the order shown in  FIG. 4 . 
     The following two products (P 0 -P 1 ) are computed by applying KA to elements in A and B.
 
 P 0=( a   1   x+a   0 )( b   1   x+b   0 )= a   1   b   1   x   2 +(( a   0   +a   1 )( b   0   +b   1 )− a   0   b   0   −a   1   b   1 )+ a   0   b   0  
 
 P 1=(( a   3   x+a   2 )( b   1   x+b )= a   3   b   1   x   2 +(( a   2   +a   3 )( b   0   +b   1 )− a   2   b   0   −a   3   b   1 )+ a   2   b   0 )2 16  
 
     As shown, P 1  is shifted by sixteen bits. The products are then XORed to provide a 48-bit result C(x).
 
 C ( x )= P 0+ P 1+ P 2+ P 3.
 
     The worst case path for each product P 0 -P 1  is the term that includes both multiplication and addition, for example, ((a 2 +a 3 )(b 0 +b 1 ) when computing P 1 . As discussed in conjunction with  FIG. 4 , the critical path delay may be reduced through the use of the asymmetric property of the Karatsuba Multiplier. 
       FIG. 6  illustrates an embodiment of a 16×32 multiplier that applies a two level application of Karatsuba (KA). The 16×32 multiplier may be used in the first reduction stage  206   a  shown in  FIG. 3 . As discussed earlier, the input data segment is reduced by 16-bits in the first reduction stage  206   a . To perform the reduction by 16-bits, the multiplier applies a two level application of KA to perform a multiply operation on a 32-bit multiplicand (represented by A in  FIG. 6 ) and an 16-bit multiplier (represented by B in  FIG. 6 ). 
     As shown in  FIG. 6 , the 32-bit multiplicand A is subdivided into eight 4-bit elements labeled a 7 -a 0  and the 16-bit multiplier B is subdivided into four 4-bit elements labeled b 3 -b 0 . The product C is A*B which is computed by applying a two level KA  600  to the following groups of elements of A and B to compute (b 3 : b 0 )*(a 3 :a 0 ) which is a symmetric multiplication, that is, each operand has the same number of bits: 
     (1) b 1 , b 0  and a 1 , a 0 ; and 
     (2) b 1 , b 0  and a 2 , a 3 . 
     Then applying a two level KA  602  to the following groups of elements of A and B to compute (b 3 :b 0 )*(a 7 :a 4 ) which is also symmetric multiplication, that is, each operand has the same number of bits: 
     (1) b 1 , b 0  and a 4 , a 5 ; and 
     (2) b 1 , b 0  and a 6 , a 7 . 
     Both two level KAs  600 ,  602  are performed in the same manner with different groups of elements of A and B. Thus, only one of the two level KAs, two level KA  600  will be described here. 
     A first level KA is applied to elements b 3 :b 0  in B and elements a 3 :a 0  in A to generate first level KA elements  604 - 1 ,  604 - 2 ,  604 - 3  and  604 - 4  as shown in  FIG. 6 . A second level KA is then applied to each of these first level KA elements  604 - 1 ,  604 - 2 ,  604 - 3  and  604 - 4 . These second level KAs are labeled  606 ,  608 ,  612  and  614  in  FIG. 6  for ease of reference. A KA is applied to elements a 3 , b 3 , a 2 , b 2  and a separate KA is applied to elements a 1 , b 1 , a 0 , b 0  generated by the first level KA in second level KA labeled  606 . A KA is applied to first level KA element  604 - 2  in second level KA labeled  608 . A KA is applied to first level KA element  604 - 3  in second level KA labeled  610 . A KA is applied to first level KA element  604 - 4  in second level KA labeled  612 . 
     The worst case path is the term that includes both multiplication and addition, for example, (a 3 +a 2 +a 1 +a 0 ).(b 3 +b 2 +b 1 +b 0 ). As discussed earlier in conjunction with  FIG. 4 , the critical path delay may be reduced through the use of the asymmetric property of the Karatsuba Multiplier. 
     The area savings are even greater as the number of bits in the CRC polynomial is increased, for example, a 64 bit CRC polynomial instead of a 32 bit CRC polynomial. The reduction in area is dependent on the size of the CRC reduction circuit. 
       FIG. 7  is a flowgraph illustrating an embodiment of a method for selecting an optimal multiplication algorithm to be used a reduction stage that is used to compute a CRC residue. 
     At block  700 , if the size of the multiplier for the reduction stage is greater than four, processing continues with block  702 . If not, processing continues with block  704 . 
     At block  702 , if the size of the multiplier is greater than eight, processing continues with block  706 . If not, processing continues with block  708 . 
     At block  704 , a classical multiplication technique is selected to compute the product in the reduction stage. 
     At block  706 , a one level application of Karatsuba (KA) is selected to compute the product in the reduction stage. 
     At block  708 , either a one level application of Karatsuba or a two-level application of Karatsuba is selected to compute the product in the reduction stage. 
     It will be apparent to those of ordinary skill in the art that methods involved in embodiments of the present invention may be embodied in a computer program product that includes a computer usable medium. For example, such a computer usable medium may consist of a read only memory device, such as a Compact Disk Read Only Memory (CD ROM) disk or conventional ROM devices, or a computer diskette, having a computer readable program code stored thereon. 
     While embodiments of the invention have been particularly shown and described with references to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of embodiments of the invention encompassed by the appended claims.