Abstract:
A fluid control circuit system is capable of maintaining fluid within a fluid tank at a desired level using electronic sensors and control circuitry, where the control circuitry and actuators are configured for low power consumption, thus allowing operation to be powered by a self contained internal power supply. To provide appropriate fluid control, the system includes a fluid sensor indicating if fluid is at a predetermined level, control circuitry attached to the fluid sensor, a latching solenoid attached to the control circuitry and also attached to a fluid control valve, and an internal power supply to power all electrical components.

Description:
[0001]    This application claims the benefit of Provisional Application No. 60/892,359 filed Mar. 1, 2007. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an electronic toilet tank monitor utilizing a bistable latching solenoid control circuit to operate solenoid actuated valves. More generally, the present invention relates to a control circuit for controlling bistable latching solenoids used to control actuated valves. 
         [0004]    2. Discussion of the Related Art 
         [0005]    Certain common flush toilets include a water tank positioned above a toilet bowl. The tank holds enough water so that when the water in the tank is released into the bowl fast enough, the water will activate a siphon in the drain line of the toilet. In addition to requiring a certain volume of water, it is critical that the water is released into the bowl within a relatively small time frame, generally about 3 seconds in order to activate the siphon to flush the water out of the toilet bowl and into the drain pipe. After flushing the water out of the toilet, it is necessary to again fill the tank with the same volume of water. Current tank level controls on toilets use mechanical means to achieve the desired amount of water in the tank. 
         [0006]    The flush mechanisms include a handle on the exterior of the tank that is mechanically coupled to a chain, which is connected to a flush valve within the tank. When a user pushes on the handle, the chain is pulled, thereby lifting the flush valve. This moves the flush valve out of the way, revealing a drain hole that is generally about 2- to 3-inches (5.08- to 7.62-cm) in diameter. Uncovering the drain hole allows the water to enter the toilet bowl. In addition to the volume of water in the tank and the diameter of the drain hole, the height of the water in the tank impacts the speed with which the water is released from the tank into the toilet bowl. 
         [0007]    In many toilets, the toilet bowl has been molded so that the water enters the rim, and some of it drains out through holes in the rim. A good portion of the water flows down to a larger hole at the bottom of the bowl. This hole is known as the siphon jet. It releases most of the water directly into the siphon tube. Because all of the water in the tank enters the bowl in about three seconds, it is enough to fill and activate the siphon effect, and all of the water and waste in the bowl is sucked out. 
         [0008]    Once the tank has emptied, the flush valve is repositioned over the drain hole in the bottom of the tank, so the tank can be refilled with water. A refill mechanism is then used to refill the tank to a predetermined height so it is ready for the next flush. The refill mechanism includes a valve that turns the water on and off. In current toilets, the valve is controlled by a filler or ball float. When the water level in the tank is low, the filler float or ball float falls. The valve is thereby opened in order to refill the tank and the toilet bowl. As the water level in the tank rises, the filler float or ball float also rises. Once the water level has reached the desired height as determined by the buoyancy of the float, the valve is switched into the closed position. An overflow tube within the tank allows excess water in the tank to be drained into the bowl to prevent the tank from overflowing. 
         [0009]    In alternative embodiments, level indicators are electromechanical devices that work in combination with some control circuits, systems, and the like. Naturally, these types of devices require electrical power to operate. However, the known mechanical design used for refill mechanisms (discussed above) does not require electrical connections at the toilet. As such, existing toilets are not equipped with a constant power source. Further, bathroom facilities do not presently include power source which would be convenient to the installed toilet (such as outlets in close proximity). In addition, electro-mechanical level indicators used in toilet tank refilling mechanisms must function even during power outages. Based on the foregoing, there is a need for a toilet tank water control system that does not require a constant external power supply. 
         [0010]    Based on the high frequency of toilet use, there exists a need for a mechanically reliable toilet tank water control system that can be operated at low power consumption levels. 
         [0011]    Solenoids are well known electromechanical devices used to convert electrical energy into mechanical energy and particularly into short stroke mechanical motion. As such, solenoids have long been employed to actuate valves in response to an electrical signal. Typical applications of these solenoid valves include controlling fluid flow, gas flow, and the like. Conventional (non-latching) solenoids require a continuous energized state to maintain actuation. 
         [0012]    To decrease the power dissipated by the solenoid, and particularly in applications where the solenoid is to be retained in the actuated position for significant time periods, latching mechanisms can be used to hold the mechanical output of the solenoid in one position or the other without requiring continuous power to the solenoid. Self-latching solenoid actuated valves are known in the art. Despite advances in self-latching solenoid actuated valves, there continues to be a need for smaller, faster acting self-latching solenoid actuated valves with low power consumption. 
         [0013]    Bistable actuators have been used to provide some reduction in power consumption. With the introduction of new actuator designs, there has been the introduction of new control circuitry. Some known circuits for controlling bistable actuators have been integrated into actuators intended to replace conventional solenoid actuators for controlling water flow. While these integrated latching actuators consume substantially less power in the actuated state than conventional solenoid actuators, input signals to the latching actuators must remain on at all times in order to keep the actuators in position. Maintaining the coil of the actuator in an energized state in order to maintain the actuator in a predetermined position increases overall power consumption. Accordingly, there exists a need for a bistable latching solenoid control circuit with minimal power requirements for actuating a water flow valve. 
       SUMMARY OF THE INVENTION 
       [0014]    It is one object of the present invention to provide a refill mechanism that can reliably control water level in toilet tanks by controlling the inflow of water. Such a refill mechanism will receive with input signals provided by toilet tank level indicators appropriately positioned in the tank to signal when predetermined water levels exist. It is another object of the present invention to provide a toilet tank water control system that does not require a constant power supply. It is yet another object of the present invention to provide a mechanically reliable toilet tank water control system that can be operated at low power consumption levels. It is still another object of the present invention to provide smaller, faster acting self-latching solenoid actuated valves with low power consumption. It is also an object of the present invention to provide a bistable latching solenoid control circuit with minimal power requirements for actuating a water flow valve. 
         [0015]    The present invention achieves many of the above-referenced advantages by utilizing a control system and control components which are specifically designed for power consumption concerns. More specifically, a bistable latching solenoid is utilized as the control for opening and closing a related water or fluid valve. By using a bistable latching solenoid, the valve can be opened and closed using small pulse signals from the control system. Most significantly, the control system is not required to continuously energize the solenoid, thus operating in a more energy efficient manner. In addition, the control circuitry is also specifically configured to conserve power and operate in an energy efficient manner. 
         [0016]    In addition to the power concern outlined above, fluid level sensing is achieved in a relatively straightforward and efficient manner. In one embodiment, this includes the use of two probes exposed within the tank capable of differentiating between the existence of fluid versus the existence of air. As such, when fluid covers both probes, the resistance therebetween changes which is detectable by the control circuitry. Naturally, other alternative fluid sensors could be utilized. 
         [0017]    These and other objects and advantages of the present invention are accomplished by the toilet tank electronic monitor and bistable latching solenoid control circuit in accordance with the present invention. The invention will be further described with reference to the following detailed description taken in conjunction with the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a perspective view of one embodiment of an overall fill tube assembly for the toilet tank electronic monitor in accordance with the present invention; 
           [0019]      FIG. 2  is top perspective view of the overall fill tube assembly of  FIG. 1  shown mounted in a toilet tank; 
           [0020]      FIG. 3  is a perspective view of a wired printed circuit board assembly connected to a power supply in accordance with the present invention; 
           [0021]      FIG. 4  is a perspective view of the printed circuit board assembly of  FIG. 3  shown wired to a solenoid; 
           [0022]      FIG. 5  is a perspective view of one embodiment of the printed circuit board in accordance with the present invention; 
           [0023]      FIG. 6  is an illustration of one embodiment of the operation of a latching valve in accordance with the present invention; 
           [0024]      FIG. 7  is a schematic block diagram of the bistable latching solenoid control circuit; 
           [0025]      FIG. 8  is a schematic circuit diagram of the bistable latching solenoid control circuit of  FIG. 7 ; and 
           [0026]      FIGS. 9(   a )-( c ) are timing diagrams of power preconditioning based on the various input signals. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    A toilet tank electronic monitor  10  in accordance with the present invention senses the presence or absence of water, i.e. the water level, in a toilet tank  28  ( FIG. 2 ) using detection pins. This detection methodology is thus used to control at least one flow valve via a control circuit. Referring to  FIG. 1 , the toilet tank electronic monitor  10  in accordance with the present invention includes a fill tube assembly  12 , a valve  14 , a solenoid  16  and a control box  18 . Fill tube assembly  12  includes a water conduit  20 , a water inlet end  22  and a valve inlet end  24 . While water conduit  20  is depicted as a generally tubular shape in the figures, those skilled in the art can appreciate that water conduit  20  can have various shapes and sizes to accommodate water feed to valve  14 . A water source is connected to water inlet end  22  such that water is supplied from water inlet end  22  through water conduit  20  into valve inlet end  24 . Water is provided to fill nozzle  26  only when valve  14  is in the open position. Fill tube assembly  12  can be comprised of any water resilient materials, including but not limited to copper, polyvinyl chloride (PVC), and the like. The components of fill tube assembly  12  can be individual components that are operably connected to one another, one integrated assembly, or a combination of both. 
         [0028]    Referring now to  FIG. 2 , the toilet tank electronic monitor  10  of the present invention is shown mounted in a toilet tank  28 . A handle  30  on the exterior of tank  28  is connected to a flush valve  32  via a connecting means  34 . Connecting means  34  can be a chain, a polymeric segment, a metal pole, or any such device that can be used to connect handle  30  to flush valve  32  while resisting corrosion and/or degradation due to being submerged in water. An overflow tube  36  is positioned within tank  28  such that tank fill nozzle  26  does not spray water directly into overflow tube  36 . However, a portion of the water fill will be directed to the overflow tube  36  to provide toilet bowl sidewall rinse during the tank refill. 
         [0029]    Referring now to  FIG. 3 , control box  18  is shown with a cover  38  removed to expose a power supply  40 . Power supply  40  shown in  FIG. 3  is a nine volt alkaline battery. Those skilled in the art can appreciate that various power supplies can be used, depending on the necessary requirements of the system. The present embodiment utilizes any power supply that provides at least 5 V DC, including but not limited to a plurality of 1.5 V batteries, a DC wall transformer, and the like. 
         [0030]    Referring now to  FIG. 4 , control box  18  is again shown with cover  38  removed to expose a printed circuit board assembly (PCBA)  42  therein. PCBA  42  includes level indicators  44  and contains the necessary circuitry to carry out the control functions of the present invention. PCBA  42  is also wired to solenoid  16  in order to provide appropriate power signals based on input readings of water level from level indicators  44 . In one embodiment, level indicators  44  utilize complimentary metal oxide silicon technology to sense the difference in resistance between air and water. This difference can then be used to establish a bistable input control for toggling solenoid  16 . Those skilled in the art can appreciate that different types of level indicators, including but not limited to laser level indicators, sonic level indicators, and the like, can be used in accordance with the present invention. 
         [0031]      FIG. 5  shows more detail of one embodiment of PCBA  42  in accordance with the present invention. The design and operation of this embodiment of PCBA  42  is discussed in greater detail below with regard to  FIGS. 7-9 . Those skilled in the art can appreciate that PCBA  42  can scaled up or down for use in various water flow valve and /or water level control applications. 
         [0032]    Referring again to  FIG. 1 , in one embodiment, valve  14  is a magnetically latching solenoid valve. In this embodiment, valve  14  may have an internal diaphragm that can be hydraulically maintained in the open position. In another embodiment, valve  14  is a custom valve with similar operating characteristics. 
         [0033]    Referring now to  FIGS. 1 and 6 , in one embodiment, solenoid  16  is 2/2 magnetically latching bistable solenoid having a coil resistance of 18±1 Ω and an operating voltage range of 6-12 V DC. Solenoid  16  in this embodiment can operate with latching valve  14  at a power down to 5 V DC and with a pulse width of 0.020 seconds (to close) and 0.060 seconds (to open). Operation under these parameters maximizes battery life for bistable latching solenoids. In position  1   46  on  FIG. 6 , if valve  14  is in the closed position and coil is supplied with voltage pulsed current  64  having a pulse width of 60 mS at inputs  60  and  62 , valve  14  is placed in the open position where it remains until supplied with additional power. Supply of additional power is shown in Position  2   48  of  FIG. 6 . Here, when valve  14  is opened by supplying current as occurs in position  1 , valve  14  can only be closed by again supplying pulsed current  66 . Valve  14  remains in the closed or off position until additional power is supplied again. Further detail regarding this operation is outlined in relation to the control circuitry discussed below. 
         [0034]    Those skilled in the art can appreciate that timing durations, solenoid driver devices, battery voltage, input control, and the like will be dependent upon application specific “latching solenoids” having unique operational requirements. Because various application specific “latching solenoids” can be used to control a variety of different types and sizes of flow valves, one embodiment of a bistable latching solenoid control circuit  50  in accordance with the present invention is discussed hereinafter without specifying particular timing durations, solenoid driver devices, battery voltage, input control, and the like. 
         [0035]    Referring now to  FIGS. 7 and 8 , there is shown a schematic diagram  52  of bistable latching solenoid control circuit  50 . The circled alphabetical references (A) through (L) are used as operational reference points referring to the application of power to circuit  50  and the power preconditioning that initializes operation of circuit  50 . These circled alphabetical references also correspond to information in the circuit diagram of  FIG. 8  and the timing diagram of  FIGS. 9(   a )-( c ) as follows: “A” represents an input stage. “B” represents an input pulse delay. “C” represents a power preset. “D” represents a two input Schmitt Trigger NAND gate. “E” represents a positive edge triggered one shot pulse. “F” represents a positive edge triggered one shot pulse inverter. “G” represents a positive triggered one shot pulse delay. “H” represents a negative edge triggered one shot pulse. “I” represents a negative edge triggered one shot pulse inverter. “J” represents a negative edge triggered one shot pulse delay. “K” represents a latching solenoid line  1  for unlatch control. “L” represents a latching solenoid line  2  for latch control. 
         [0036]    Referring in more detail to  FIG. 7 , schematic diagram  52  illustrates the existence of an input stage  70  which will receive a latched or unlatched signal at its input. Input stage  70  also receives power from battery  100  which has its output limited by a current limiting resister  102 . An output from input stage  70  is then passed to an input pulse delay  72  which will feed one side of a two input Schmitt Trigger NAND gate  76 . In addition, a power preset circuit  74  supplies a second input to Schmitt Trigger NAND gate  76  (in addition to any necessary power signals). The output from two input Schmitt Trigger NAND gate  76  is then provided to a pair of one shot pulse generators: negative edge triggered pulse generator  78  and positive edge triggered pulse generator  80 . As will be recognized, each of these circuits will generate pulses at appropriate times in response to received falling or rising edges of pulses, received at the respective input. Connected to the output of negative edge triggered pulse generator  78  is an inverter  92  along with a pulse delay circuit  94 . Inverter  92  feeds a high side MOSFET switch  98 , while pulse delay circuit  94  feeds a low side MOSFET switch  96 . Similarly, outputs from positive edge triggered one shot pulse generator  80  is provided to inverter  82  and pulse delay  84 . Inverter  82  then feeds high side MOSFET switch  86  while pulse delay circuit  84  will feed a low side MOSFET switch  88 . As discussed in greater detail below, each of these components cooperate with one another to provide appropriate control of latching solenoid  90 . 
         [0037]    Referring now to  FIGS. 8 and 9(   a )-( c ), component references (R 1 , C 1 , U 1 , and the like) are used to identify certain components of circuit  50  which are configured to carry out the desired operation. Further, these references are also referring to the application of power to circuit  50  and the power preconditioning that initializes operation. 
         [0038]    Circuit  50  depicted in  FIGS. 7-9(   a )-( c ) is designed using complimentary metal oxide silicon (CMOS) technology for water level indication and Schmitt Trigger gating to obtain low frequency operation and low power consumption ideal for battery applications. Those skilled in the art can appreciate that various level indication and gating technology can be used when designing circuit  50  for various applications, including but not limited to control of substances other than water. 
         [0039]    Circuit  50  performs one of two stable control operations based upon the input state “unlatch” or “latch” for latching style solenoids. Circuit  50  is powered by a single DC power source. When the DC power is applied to the circuit it will perform a solenoid “unlatch” operation as part of its power preconditioning initialization state. After the power preconditioning operation the circuit will respond to its input state. If the input state is “unlatch” then no further operation is performed. If the input state is “latch” then the circuit will perform the “latch” solenoid operation routine. 
         [0040]    The “unlatch” and “latch” input control commands each initialize one fixed pulse to trigger the bistable latching solenoid. The input pulse is time delayed which limits how fast circuit  50  can toggle between the two input control states preventing both circuit paths from simultaneously actuating the solenoid operation. Bistable control of the latching solenoid requires bi-directional electrical current. In between a change of input states, circuit  50  will default to sleep mode for low power consumption. 
         [0041]    Referring now to  FIGS. 9(   a )-( c ) there is depicted a timing diagram which illustrates operation in accordance with the design of circuit  50  in the present invention. T 1  through T 9  along the top of the  FIG. 9(   a ) are used to identify timing events. The timing events show the specific logic level states (“0” or “1”) for timing identifiers listed along the left side of  FIGS. 9(   a )-( c ). These timing identifiers correlate with circled alphabetical references (A) through (L) and also correspond to like indicators on  FIGS. 7 and 8 . 
         [0042]    Referring specifically to  FIG. 9(   a ), there is shown a timing diagram for the application of power to circuit  50  and the power preconditioning that initializes operation of circuit  50  where the input state is set to “LATCH.” Timing Event T 1  represents the application of DC power to circuit  50 . As previously discussed, circuit  50  can be powered by a single DC power supply source (+V BATT). When power is applied to circuit  50 , input bias voltage level (A) will begin to charge capacitor C 2  through resistor R 7  (B). Likewise, the applied power will begin to charge capacitor C 3  through resistor R 5  (C). In the power preconditioning stage, the input to U 1 C pin  9  will be at logic level “0” (C) until the capacitor C 3  charge voltage exceeds the Logic Threshold Value (LTV) (Timing Event T 5 ). Similarly, until the capacitor C 2  charge voltage exceeds the LTV (Timing Event T 6 ) the input to U 1 C pin  8  will be logic level “0” (B). As will be appreciated, U 1 C corresponds to the two input Schmitt Trigger NAND gate  76  as illustrated in  FIG. 7 . 
         [0043]    With both inputs to U 1 C equal to logic level “0” the U 1 C pin  10  output (D) will be logic level “1” triggering the positive edge triggered “one shot” pulse (E). (Again, corresponding to pulse generator  80  shown in  FIG. 7 .) The positive edge triggered “one shot” pulse (E) will begin to charge capacitor C 6  through resistor R 12 . The inverted positive edge triggered “one shot” pulse will bias the high side MOSFET Q 3  into conduction (F). The pulse is inverted by UC 2  (inverter  82 ) to provide this signal. 
         [0044]    Timing Event T 2  represents the beginning of the “UNLATCH” solenoid pulse. This is provided by an appropriate delay using pulse delay  84 . Specifically, when capacitor C 6  charge voltage exceeds the LTV of the U 3 A pin  1 &amp; 2  input the delayed positive edge triggered “one shot” pulse (G) will bias the low side MOSFET Q 4  into conduction initializing the latching solenoid “UNLATCHED” state (K). 
         [0045]    Timing Event T 3  represents the end of the “UNLATCH” solenoid pulse. When the positive edge triggered “one shot” pulse (E) completes the one pulse time period it will switch to logic level “0”. The inverted positive edge triggered “one shot” pulse (F) will bias the high side MOSFET Q 3  into non-conduction de-energizing the solenoid (K) and causing a “free wheeling current,” or inductive kickback, from the inductive load of the solenoid. 
         [0046]    Timing Event T 4  represents dampening of the free wheeling current, or inductive kickback, from the solenoid. The positive triggered “one shot” pulse (E) logic “0” will begin to discharge capacitor C 6  through resistor R 12 . When capacitor C 6  discharge voltage drops below the LTV the delayed positive edge triggered “one shot” pulse (G) will bias the low side MOSFET Q 4  into non-conduction and the unlatch cycle of the solenoid is complete. During the time period between T 3  and T 4  the MOSFET Q 4  remains conductive allowing its internal “drain to source” protection zener diode to forward conduct the “free wheeling current” caused by the inductive load of the solenoid. 
         [0047]    Timing Event T 5  represents the end of power preconditioning. When the capacitor (C 3 ) charge voltage exceeds the LTV (from Timing Event T 1 ) the input to U 1 C pin  9  will be logic level “1” (C). As illustrated, Capacitor C 3  and resister R 5  correlate to power preset circuit  74 . The circuit will remain in this state until further events are encountered. 
         [0048]    Timing Event T 6  represents operation of the solenoid with “LATCH” as the input command. This change will be in response to a change at the input, thus indicating that fluid is no longer present at the desired level. When the capacitor (C 2 ) charge voltage exceeds the LTV (from Timing Event T 1 ) the input to U 1 C pin  8  will be logic level “1” (B). With both inputs to U 1 C set to logic level “1” the U 1 C pin  10  output (D) will be logic level “0” and will trigger the negative edge triggered “one shot” pulse (H), which is generated by the components making up pulse generator  78 . The negative edge triggered “one shot” pulse (H) will begin to charge capacitor C 4  through resistor R 6  of pulse delay  94 . The inverted negative edge triggered “one shot” pulse (inverted by inverter  92 ) will bias the high side MOSFET Q 1  into conduction (I). 
         [0049]    Timing Event T 7  represents the beginning of the “LATCH” solenoid pulse. When capacitor C 4  charge voltage exceeds the LTV of the U 1 D pin  12 &amp; 13  input delayed negative edge triggered “one shot” pulse (J) will bias the low side MOSFET Q 2  into conduction initializing the latching solenoid “LATCHED” state (L). 
         [0050]    Timing Event T 8  represents the end of the “LATCH” solenoid pulse. When the negative edge triggered “one shot” pulse (H) completes the one pulse time period it will switch to logic “0”. The inverted negative edge triggered “one shot” pulse (I) will bias the high side MOSFET Q 1  into non-conduction de-energizing the solenoid (L) and causing a “free wheeling current” (inductive kickback) from the inductive load of the solenoid. 
         [0051]    Timing Event T 9  represents dampening of the “free wheeling” current from the Solenoid. The negative edge triggered “one shot” pulse (H) logic level “ 0 ” will begin to discharge capacitor C 4  through resistor R 6 . When capacitor C 4  discharge voltage drops below the LTV the delayed negative edge triggered “one shot” pulse (J) will bias the low side MOSFET Q 2  into non-conduction and the latch cycle of the solenoid is complete. During the time period between T 8  and T 9  the MOSFET Q 2  remains conductive allowing its internal “drain to source” protection zener diode to forward conduct the “free wheeling current” caused by the inductive load of the solenoid. 
         [0052]    Referring now to  FIG. 9(   b ), there is shown a timing diagram for operation of circuit  50  when the input changes to the “UNLATCH” state. Referring now to  FIG. 9(   c ), there is shown a timing diagram for operation of circuit  50  when the input changes again to the “LATCH” state. 
         [0053]    While the invention has been described with reference to the specific embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention. The terms and descriptions used herein are set forth by way of illustration only and are not meant as limitations. Those skilled in the art will recognize that these and other variations are possible within the spirit and scope of the invention as defined in the following claims and their equivalents.