Abstract:
This invention concerns with such methods to form the film of semiconductor device, without degrading any desirable characteristics of the device, that enables the endpoint detection pertaining to the polishing process of either the conductive film or the insulating film. This invention includes such three processing steps: (1) to form DLC film  3 , (2) to an form insulating film  6  upon a DLC film  3 , (2) to expose a plasma gas containing fluorine to the DLC film  3 , (3) to an form insulating film  6  upon the DLC film  3 , and (4) to polish the insulating film  6  by means of Chemical Mechanical Polishing (CMP), and to stop the polishing at the point in time when the DLC film  3  appears at the surface of the substrate.

Description:
BACK GROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to a method to form a DLC film used as an etching stopping film or a polishing stopping film for forming a semiconductor device.  
           [0003]    2. Description of the Prior Art  
           [0004]    In recent years, industry&#39;s need for higher speed, larger integration semiconductor device is intense. Accordingly, the innovations in process technologies for producing more fine and/or multilevel interconnections are being sought.  
           [0005]    In order to produce such semiconductor device that have very fine and/or multilevel interconnection, a planarization technique which involves an interlayer insulating film or metal embedded in the insulating film is essential.  
           [0006]    Chemical Mechanical Polishing (CMP), to fill up conducting substance for interconnection into grooves of the insulating film, and/or to fill up insulating substance for isolation into trenches of the substrate, is one of the planarization techniques.  
           [0007]    An example of the implementation of such planarization technique is a Cu-embedded interconnection technique by means of CMP. The Cu-embedded interconnection technique is regarded a promising material for interconnection of integrated circuit (IC) because of the following two reasons:  
           [0008]    (1) it is highly reliable in operations at high current densities, and  
           [0009]    (2) it can shorten the signal-propagation-delay time of ICs due to Cu&#39;s low resistivity characteristic.  
           [0010]    To form Cu-embedded interconnection, a technique called “damascening” is being used.  
           [0011]    Damascening process proceeds as follows: First, grooves are formed into the insulating film. Second, a barrier metal is deposited upon all over the insulating film. Then, a conductive film made of copper or other appropriate substance is deposited upon all aver the insulating film. Finally, the conductive film is polished by means of CMP to be embedded in the grooves of the insulating film.  
           [0012]    There is also a technique called “dual damascening”. Dual damascening process enables the simultaneous formation of both an upper interconnection and contacts through via holes connecting the upper interconnection of the insulating film with an under interconnection. Dual damascening process proceeds as follows: First, not only grooves for interconnection, but also via holes are formed into an insulating film before forming a conductive film. Second, the conductive film is deposited all over the insulating to cover the grooves and the via holes. Finally, the conductive film is polished by means of CMP to be embedded into the grooves and via holes.  
           [0013]    The control over the amount of polishing the conductive film should be complete and sufficiently accurate. If any conductive film on the surface of the insulating film remains, it may cause undesirable short-circuiting in the produced semiconductor device. Consequently, the device may fail in its tests or in its performances. If the polishing continues in excess beyond the point of the complete removal of the conductive film right upon the insulating film, an over etching of the conductive film occurs at the areas where the conductive film is exposed, and the effect of so called “dishing” results. Often, the dishing effect increases the resistance of interconnection larger than the designed value, and/or causes unstable electrical contacts between interconnections.  
           [0014]    Therefore, it is extremely desirable to create such a film right upon the insulating film that facilitates a clear, exact end-point detection during the process of polishing the conductive film deposited right upon such created film.  
           [0015]    Likewise, it is extremely desirable, too, to form such a film that facilitates a clear, exact end-point detection when polishing with CMP technique the insulating film that was deposited in the trenches dug on the surface of the semiconductor substrate.  
           [0016]    Even when such film remains in the semiconductor device to be produced, however, the film should not degrade any targeted characteristics of the semiconductor device.  
         SUMMARY OF THE INVENTION  
         [0017]    This invention has been made in view of above problem in the prior art and it is an object of the present invention to provide a method for forming a film of the semiconductor device that facilitate the exact end-point detection for the polishing process of conductive film or insulating film without compromising any of the desirable performance of the semiconductor device.  
           [0018]    In the invented methods, Diamond Like Carbon (DLC) film is used during the process of either etching or polishing the insulating film, as not only the etching stopper, but also the polishing stopper, respectively.  
           [0019]    Similarly, in the invented methods, DLC film is used during the process of either etching or polishing the conductive film, as not only the etching stopper, but also the polishing stopper, respectively.  
           [0020]    The value of Spinel hardness of DLC film is 2,800, approximately, and is much larger than those of SiO 2  film&#39;s (800) or Si 3 N 4  film&#39;s (1,200). Specifically, since the selectivity of etching SiO 2  with respect to etching DLC is very high, the DLC film has the exceptionally desirable characteristics as the stopper, for etching or polishing SiO 2  film.  
           [0021]    The value of dielectric constant of DLC film is about 2.7, and is very low as compared to those values of SiO 2  film&#39;s (4.0) and Si 3 N 4  film&#39;s (8.4). Hence, the propagation delay time of the signal transmitted through the interconnection is not affected at all effectively by the existence of such DLC film.  
           [0022]    Further more, the leak current through the DLC film can be remarkably decreased, as it is exposed in a plasma gas containing fluorine after its formation. The gas mentioned in the previous sentence can be either one of such fluorine gases as C 2 F 6 , C 3 F 8 , NF 3 , CF 4  or SF 6 .  
           [0023]    By said exposing operation, we can prevent any performance degradation of semiconductor device to be produced with the invented methods, even if the DLC film remains in the semiconductor device as a part of an insulating film, after it has been used as either the etching stopper or the polishing stopper.  
           [0024]    Since, the DLC film can be used as the stopper of either etching or polishing not only the insulating film but also the conductive film, said DLC film is applicable to the formation of interconnection using dual damascening technique, also. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    [0025]FIGS. 1A to  1 D are sectional views for explaining the first and the second embodiment of the present invention. They are provided for explaining the methods to form films, in which the DLC film is used as etching stopper.  
         [0026]    [0026]FIGS. 2A to  2 F relate to the third embodiment of this invention. These figures are provided for explaining the methods to form films, in which the DLC film is used as etching stopper.  
         [0027]    [0027]FIGS. 3A to  3 F relate to the fourth embodiment of this invention. These figures are provided for explaining the methods to form films, in which the DLC film is used as etching stopper. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0028]    Embodiments of the present invention are explained hereinafter, referring to FIG. 1A to FIG. 3F.  
         [0029]    (A) The First Embodiment  
         [0030]    The first embodiment of the present invention relates to the method to embed the insulating film into trenches by making use of DLC (Diamond Like Carbon) film as the etching stopper.  
         [0031]    As illustrated in FIG. 1A, the process proceeds as follows:  
         [0032]    Firstly, a PAD SiO 2  film  2  of 10 nm in thickness is formed by using thermal oxidation upon a Si substrate  1 .  
         [0033]    Secondly, a DLC film  3  of 150 nm in thickness is deposited by using DC (Direct Current) plasma CVD(Chemical Vapor Deposition), electroplating, or sputtering.  
         [0034]    As for the other methods for forming DLC film  3 , micro wave plasma CVD and Ion Beam Sputtering are well used.  
         [0035]    Thirdly, as shown in FIG. 1A, a resist film  4  is deposited and then a patterning of the resist film  4  is carried out by making use of a mask that is not shown in the figure.  
         [0036]    Fourthly, a dry etching of the DLC film  3  is performed by using O 2  gas plasma as well as by using the patterned resist film  4  as the masking resist against the dry etching.  
         [0037]    The condition of the dry etching is as follows, for example:  
         [0038]    (1) to introduce O 2  gas into reactor chamber at the flow rate of 800 sccm,  
         [0039]    (2) to set the gas pressure in the reactor chamber at 1 Torr,  
         [0040]    (3) to set RF power for the plasma creation at 150 W,  
         [0041]    (4) to apply an 150 W of low-frequency-bias power to Si substrate  1 ,  
         [0042]    (5) to create the plasma O 2  gas with the foregoing conditions, and  
         [0043]    (6) to expose the substrate in the plasma O 2  gas for 30 seconds.  
         [0044]    With the condition described hereinbefore, the DLC film  3  can be etched off selectively.  
         [0045]    Fifthly, the SiO 2  film  2  is etched off selectively with a wet etching method using a solution containing hydrofluoric acid or the like to be exposed the surface of the Si substrate  1 .  
         [0046]    Sixthly, the Si substrate  1  is etched with a dry etching method using a gas containing chlorine or the like. As the result of the dry etching, a trench  5  is formed at the surface of the Si substrate  1 , as illustrated in FIG. 1B.  
         [0047]    Seventhly, a SiO 2  film  6  is formed with CVD method as shown in FIG. 1C.  
         [0048]    Eighthly, the SiO 2  film  6  is polished by using CMP method.  
         [0049]    Finally, the polishing of the SiO 2  film  6  is stopped at the time when DLC film  3  appears at the surface of the substrate  1 .  
         [0050]    In this manner, the SiO 2  film  6  is embedded into the trench  5  to accomplish both of the surface planarization and the electrical isolation of the Si substrate  1  simultaneously.  
         [0051]    The DLC film  3  which is formed in such a way, has the following characteristics:  
         [0052]    (1) spinel hardness of around 2,800,  
         [0053]    (2) no moisture absorbing tendency, and  
         [0054]    (3) dielectric constant of around 2.7.  
         [0055]    Since the value of Spinel hardness of DLC film is much larger than that of SiO 2  film which is around 800 or of Si 3 N 4  film which is around 1,200, the etching selectivity of DLC film with respect to SiO 2  film is higher than the etching selectivity of Si 3 N 4  with respect to the same. Spinel hardness is one criterion for the selectivity ratio in mechanical polishing. However we should take the selectivity ratio in chemical polishing into consideration, also, in order to evaluate the selectivity as a whole.  
         [0056]    As far as the permitivity is concerned, the value of dielectric constant of DLC film is significantly smaller than that of SiO 2  film which is about 4.0 or Si 3 N 4  film which is about 8.4. Consequently, DLC film can shorten the signal propagation delay caused by interconnection capacitance. Furthermore, the adhesion strength between DLC film and SiO 2  film is sufficiently strong.  
         [0057]    (B) The Second Embodiment  
         [0058]    The description of the second embodiment that relates to the method to embed an insulating film into trenches by making use of DLC film as the etching stopper, is given in this section.  
         [0059]    The distinct point in the second embodiment from the first embodiment is the existence of the process in which the DLC film  3  is exposed in the plasma containing fluorine gas.  
         [0060]    The actual condition of the plasma exposing process is as follows:  
         [0061]    (1) to introduce NF 3  gas, after forming the DLC film  3  into reactor chamber at the flow rate of 200 sccm,  
         [0062]    (2) to set the gas pressure in the reactor chamber at about 1 Torr,  
         [0063]    (3) to set RF power for the plasma creation at about 150 W,  
         [0064]    (4) to apply a 0 W of low-frequency-bias-power to Si substrate  1 ,  
         [0065]    (5) to create the plasma of NF 3  gas with the foregoing conditions, and  
         [0066]    (6) to expose the substrate in the plasma of NF 3  for 30 seconds.  
         [0067]    As the result of the treatment described hereinbefore, the leak current through the DLC film  3  decreased to 1.5 pA/mm 2  from 0.5 nA/mm 2  of the leak current of the same before the plasma process.  
         [0068]    The decrease of the leak current of DLC film is able to improve the performance of the semiconductor device. Accordingly, we are able to use the DLC film  3  as an insulating film even if it remains in the semiconductor device after it have been utilized as the etching stopper.  
         [0069]    Though the gas used in the explanation given just hereinbefore, is NF 3 , it can be either one of such fluorine gases as C 2 F 6 , C 3 F 6 , CF 4  or SF 6  instead.  
         [0070]    (C) The Third Embodiment  
         [0071]    In this section, the description of the third embodiment that relates to the method to form Cu interconnection by means of single damascening technique at which DLC film is used as etching stopper is given referring to the FIGS. 2A to  2 F.  
         [0072]    Firstly, as shown in FIG. 2A, a PAD SiO 2  film  8  of 10 nm in thickness is formed upon a Si substrate  7  by means of thermal oxidation, then a DLC film  9  of 150 nm in thickness is formed thereupon. Secondly, as shown in FIG. 2B, the DLC film  9  is exposed in NF 3  plasma so as to improve the quality of the DLC film.  
         [0073]    Thirdly, as shown in FIG. 2C, a SiO 2  film  10  is formed by CVD method, and then a DLC film  11  is formed thereupon. Fourthly, as shown in the same FIG. 2C, the DLC film  11  is exposed in NF 3  plasma in order to improve the quality of the DLC film.  
         [0074]    Fifthly, as shown in FIG. 2D, a resist film  12  is deposited, and then the resist film  12  is patterned by making use of a mask that is not shown in the figure.  
         [0075]    Sixthly, as shown in the same FIG. 2D, an opening  13  where the surface of the Si substrate  7  is exposed, is formed by etching the DLC film  11 , the SiO 2  film  10 , the DLC film  9  and the PAD SiO 2  film  8  off in turn, using the patterned resist film  12  as the masking resist against the etching.  
         [0076]    Seventhly, the resist film  12  is removed from the entire surface of the substrate and then, as shown in FIG. 2E, a TiN film  14  is formed as the barrier film by using sputtering method.  
         [0077]    Eighthly, as shown in the same FIG. 2E, a Cu film  15  is deposited so as to fill up the opening  13  at least by either one of such means as CVD, electroplating or sputtering.  
         [0078]    Finally, as shown in FIG. 2F, the Cu film  15  as well as the TiN film  14  are polished by using CMP and the polishing is stopped at the point where DLC film  11  appears at the surface of the substrate. Thus, we can accomplish not only embedding the Cu film  15  into the opening  13 , but also the surface planarization, simultaneously.  
         [0079]    The existence of these DLC films greatly contributes to shortening the signal propagation delay of the semiconductor device by the following three facts:  
         [0080]    (1)the quality of both DLC film  9  and DLC film  11  is improved through the invented process,  
         [0081]    (2) the dielectric constant of DLC film is as low as 2.7, and  
         [0082]    (3) they can remain existing in the semiconductor device to be produced upon and underneath the SiO 2  film  10 , even after they had been used as the end point detector in the process of polishing the Cu film  15  by CMP method.  
         [0083]    The interlayer insulating film used in the foregoing explanation is SiO 2  film, however, of course, it can be such an insulator made of either an organic substance or an inorganic substance instead, that may have a lower dielectric constant than that of SiO 2  in order to shorten the signal propagation delay time further.  
         [0084]    The embodiment described in this section is applicable also to via contact which is to connecte the one interconnection on the interlayer insulating film to the other interconnection under the interlayer insulating film through the opening of the interlayer insulating film.  
         [0085]    (D) The Fourth Embodiment  
         [0086]    In this section, the description of the fourth embodiment that relates to the method to form Cu interconnection by means of dual damascening technique at which DLC film is used as etching stopper is given referring to the FIGS. 3A to  3 F.  
         [0087]    Firstly, as shown in FIG. 3A, a PAD SiO 2  film  17  of 10 nm in thickness is formed upon Si substrate  16  by means of thermal oxidation, and then a DLC film  18  of 150 nm in thickness is formed thereupon. Secondly, the quality of DLC film  18  is improved by exposing it in NF 3  plasma.  
         [0088]    Thirdly, as shown in the same FIG. 3A, a SiO 2  film  19  of 500 nm in thickness is formed by CVD method, then a DLC film  20  150 nm in thickness is formed thereupon. Fourthly, the quality of DLC film  20  is improved by exposing it in NF 3  plasma.  
         [0089]    Fifthly, as shown in the same FIG. 3A, a SiO 2  film  21  of 500 nm in thickness is formed by CVD method, then a DLC film  22  of 150 nm in thickness is formed thereupon. Sixthly, the quality of DLC film  22  is improved by exposing it in NF 3  gas. Seventhly, a resist film  23  is formed, then, as shown in the same FIG. 3A, a patterning of the resist film  23  is carried out by making use of a mask that is not shown in the figure.  
         [0090]    Eighthly, as shown in FIG. 3B, grooves  24  for interconnection are formed by etching off both DLC film  22  and the SiO 2  film  21 , using such patterned resist film  23  as the masking resist against the etching.  
         [0091]    Ninthly, a resist film  25  is formed then, as shown in FIG. 3C, and a patterning of the resist film  25  is carried out by making use of a mask that is not shown in the figure.  
         [0092]    Tenthly, as shown in FIG. 3D, an opening  26  that exposes the surface of the Si substrate  16  is formed by etching the DLC film  20 , the SiO 2  film  19 , the DLC film  18  and the PAD SiO 2  film  17  off.  
         [0093]    Eleventhly, the resist film  25  is removed from the entire surface of the substrate, and then, as shown in FIG. 3E, a TiN film  27  is formed as the barrier film by sputtering method. Twelvethly, a Cu film  28  is deposited so as to fill up the opening  26  as well as grooves  24 , by either one of such means as CVD, electroplating or sputtering  
         [0094]    Finally, as shown in FIG. 3F, the Cu film  28  is polished as well as the TiN film  27  by means of CMP, until the point in time when the DLC film  22  appears, and the polishing at that point. Thus, we can accomplish not only embedding the Cu film  28  into both the opening  26  and the groove  24 , but also the surface planarization simultaneously.  
         [0095]    The existence of these DLC films greatly contributes to shortening the signal propagation delay of the semiconductor devices by the following three facts:  
         [0096]    (1) the quality of the DLC film  18 , the DLC film  20  and the DLC film  22  is improved through the invented process of gas plasma containing fluorine,  
         [0097]    (2) the dielectric constant of those DLC films is as low as 2.7, and  
         [0098]    (3) they remain existing in the semiconductor device to be produced, accompanied with SiO 2  film  19  and SiO 2  film  21 , even after they had been used as the endpoint detector in the process of polishing the Cu film by CMP method.  
         [0099]    (E) Other Embodiments  
         [0100]    In the foregoing sections of this document, we described the invention in detail with respect to the each embodiment of the present invention. The claim of this invention is not limited to the embodiments described hereinbefore but the variations to the foregoing embodiments shall be included in the scope of this invention so long as the variations can be regarded within the extent of engineering changes to the each embodiment.  
         [0101]    For example, the DLC film formed underneath a conductive film such as Cu (copper) can be utilized as etching stopper of the conductive film.