Abstract:
Disclosed is a power supply with a control circuit comprising a capacitively coupled bridge circuit ( 10 ) for using a low-voltage circuit to operate a high-voltage circuit. The invention maintains isolation between the high-and low voltage sections by using a capacitor ( 20 ).

Description:
RELATED APPLICATIONS 
     This application is a divisional application of U.S. patent application Ser. No. 09/976,700 now U.S. Pat. No. 6,657,274, entitled “APPARATUS FOR CONTROLLING A HIGH VOLTAGE CIRCUIT USING A LOW VOLTAGE CIRCUIT” and filed on Oct. 11, 2001 with Comeau, Alain R., listed as inventor, the entirety of the application which is hereby specifically incorporated by reference. 
    
    
     TECHNICAL FIELD 
     This invention relates to a power supply circuit, and more specifically, to a capacitively coupled bridge circuit for using a low-voltage circuit section to control a high-voltage circuit section while maintaining isolation between the high- and low-voltage sections. 
     BACKGROUND OF THE INVENTION 
     In many electronic systems a low voltage source is often needed to control a corresponding high voltage source. One such need, for example, is commonly found in a device known as an Implantable Cardiac Defibrillator (ICD), in which a high voltage pulse is controlled by a low voltage integrated circuit (° C.). In many instances, delivery of the higher voltage is accomplished by way of a non-complementary high voltage switching matrix encompassing a bridge configuration. This switching element frequently employs N-channel Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs), or Insulated Gate Bipolar Transistors (IGBTs), or Silicon Controlled Rectifiers (SCR) depending on the design specifications. 
     In order to enhance the overall performance of a system that involves low-to-high voltage transfer, isolation between both the voltage-generating and voltage-delivering functions is crucial. In a bridge or a switching matrix configuration having N-Channel MOSFETs or IGBTs, for instance, the transistor gate voltage needs to be higher than, or independent of, the switching voltage. The low voltage section of the system cannot, therefore, be used to provide the gate voltage directly. Therefore, an alternative method of maintaining and transferring the necessary gate voltage must be implemented. 
     In the art, two known methods are used to achieve level shifting and input-to-output isolation. The first involves using a transformer in combination with a full-wave bridge rectifier circuit; the other involves circuits using opto-couplers. 
     Although transformers combined with diode rectifiers may be adequate for shifting voltage levels, design considerations limit their use in certain situations. First, transformers are bulky, and hence, are unsuitable in certain applications where minimizing the three-dimensional space of the device is critical, such as in an ICD. Similarly, transformers are discrete devices, and thus, cannot be incorporated in a CMOS integrated circuit (IC). 
     Opto-couplers, on the other hand, suffer from the same size impediments as isolation transformers. Moreover, in dual- or multi-channel design applications, optocouplers are susceptible to signal distortion and cross talk. 
     Accordingly, a power supply that delivers a high power output controlled by low power input while simultaneously capacitively isolating the two sources would be advantageous. Such a device would also have the advantage of being readily integrated into standard CMOS IC production processes. The performance characteristics and small size of IC embodiments of such a device would be particularly advantageous for use in small-size applications such ICD&#39;s. 
     SUMMARY OF THE INVENTION 
     The invention provides a power supply with integral control circuit for providing a low-voltage control signal with capacitive coupling to a high-voltage section having an output for powering a load. The power supply is adapted to operate the high-voltage section in response to a signal firm the low-voltage section. 
     According to one aspect of the invention, the integral control circuit and capacitive coupling are implemented as a single IC. 
     According to another aspect of the invention, the integral control circuit is implemented as a full bridge rectifier driver circuit. 
     Embodiments of the invention disclosed include implantable cardiac defibrillator circuits where a bridge section capacitively couples the low-voltage section to the high-voltage section. 
     The invention provides several technical advantages over the prior art. The capacitive coupling used by the invention is smaller and less expensive to implement than isolation devices used in the arts. The remainder of the accompanying bridge circuit provides advantages in terms of operational characteristics, manufacturing techniques, and size. The invention is particularly advantageous for use in applications concurrently demanding fast response, a high degree of portability, and reliable isolation of high- and low-voltage circuit components. One example of such an application is an implantable cardiac defibrillator. Further advantages will become apparent to those skilled in the arts upon review of the following description, figures and claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the invention including its features, advantages and specific embodiments, reference is made to the following detailed description along with accompanying drawings in which: 
         FIG. 1  is a block diagram showing an example of the components of the invention; 
         FIG. 2  is a circuit diagram showing a close-up schematic view of the bridge section of the invention of  FIG. 1 ; 
         FIG. 3  is a block diagram showing an example of an implantable cardiac defibrillator embodiment of the invention; 
         FIG. 4  is a cross sectional side view of a preferred embodiment of diode D 1  of  FIG. 2 ; 
         FIG. 5  is a cross sectional side view of a preferred embodiment of diodes D 2  and D 3  of  FIG. 2 ; and 
         FIG. 6  is a cross sectional side view of a preferred embodiment of transistor M 1  of FIG.  2 . 
     
    
    
     References in the detailed description correspond to like references in the figures unless otherwise noted. The figures are not to scale and some features may appear minimized or exaggerated to illustrate the invention. 
     DETAILED DESCRIPTION 
     In  FIG. 1  is shown a block diagram of an example of the invention in the form of a full image driver circuit  10 . A low voltage section  12  provides a relatively low voltage control signal to a bridge section  14 . Preferably, the control signal is an oscillating signal within a frequency range (FOSC) of about 1 MHz-10 MHz, at about 6V-24V, although other generating frequencies may be employed. As shown in  FIG. 1 , the bridge section  14  may have a high portion  16  and a low portion  18 , which are functionally and physically mirror-images of one another, providing a full bridge driver circuit  10 . The bridge section  14  may be contained on a single IC. Isolation capacitors  20  are used to couple the low voltage section  12  with the bridge portion  14 . The isolation capacitors  20  are preferably included on an IC with the bridge portion  14 , although they may be alternatively external, or included on an IC with the low voltage section  12 . The isolation capacitors  20  are selected to withstand the maximum peak voltage of the high voltage portion  22 . The high voltage portion  22  is coupled to a load  24 . In the preferred embodiment, the high voltage section  22  supplies about 800V-1000V to the load  24 . 
     In general, the bridge portion  14  of the invention  10  provides an isolating and controlling connection between the low voltage section  12  and the high voltage section  22 . The invention  10  is designed to provide electrical isolation through the use of an isolation capacitor  20 . The components and configuration of the bridge portion  14 , further shown and described below, provide a circuit  10  with desirable rise- and fall-time (t rise  and T fall ) characteristics as well as size and integration advantages at the invention. 
     Now referring to  FIG. 2 , a close up view of a bridge section  14  of the invention is shown. In the preferred embodiment, the isolation capacitor  20  is included on an IC also containing the bridge section  14 . The isolation capacitor  20  is coupled to the low voltage section  12  on one side and to the remainder of the bridge section  14  at node N 3 . In the preferred embodiment, the substrate is used as the input (node N 3 ) to facilitate implementation of the high voltage isolation capacitor  20  directly in the CMOS process, if desired, without any modifications to other components, e.g., D 1 , D 2 , D 3 , and M 1 . For the isolation capacitor  20 , reliability at high voltage is required since this device effectively provides the high voltage isolation between the low voltage section  12  and the high voltage section  22 . The capability of the isolation capacitor  20  to withstand high voltages is preferably achieved by adjusting the thickness of dielectric between the top metal plate and the substrate, as well as by usual high voltage layout rules for surrounding circuitry and guard rings. An isolation capacitor  20  in the range of 50-100 pF able to withstand about 800V-1000V is presently preferred. 
     A forward-biased diode D 1   26  is connected to node N 3  as are first and second reverse-biased diodes D 2   28  and D 3   30 . At the opposing terminal of the forward-biased diode D 1   26 , at node N 4 , a resistor R 2   32  and capacitor C 2   34  pair join the opposing terminal of the first reverse-biased diode D 2   28  at node N 5 . Capacitor C 2   34  must be fairly well isolated from the input signal (node N 3 ) present on the substrate to prevent the low voltage section  12  input signal from bypassing the first reverse-biased diode D 2   28 . This is preferably achieved by using a double polysilicon capacitor. 
     The parasitic capacitance between the substrate and the bottom polysilicon plate is on the order of 10% of the inter-poly capacitance. In addition to being reasonably isolated from the substrate, the use of a double polysilicon capacitor allows the choice of connecting the bottom plate to node N 4  or to node N 5 . Transistor M 1   36  itself provides a parasitic capacitance between N 4  and N 3 . It is, therefore, desirable to place additional parasitic capacitance, preferably 5-20 pF, between node N 5  and node N 3 . Thus, a configuration where the capacitor C 2   34  bottom plate is tied to node N 5  is preferred. Resistor R 2   32  optimized along with C 2   34 , to provide a time constant (Trc) appropriate for the oscillation frequency (Fosc) range used. Typically Trc is 3 to 10 times longer than the inverse minimum frequency used (e.g., 1 MHz to 10 MHz). Parasitic capacitance coupling to node N 3  is reduced when R 2   32  is made of polysilicon and furthermore if the polysilicon has a higher sheet resistance reducing the size, and therefore parasitic capacitance, resulting in a resistor of smaller area A resistor R 2   32  of about 500 KΩ to 3 MΩ is presently preferred, as it provides acceptably low parasitic capacitance. 
     A transistor M 1   36 , preferably an NMOSFET, has its source connected to node N 4  and its gate connected to node N 5 . Also connected to node N 4  is a power transistor Q 1   38 . It can be seen that at node N 6  the drain of the NMOSFET transistor M 1   36  is connected to the remaining terminal of the second reverse-biased diode  30 . Node N 6  is ultimately connected to the load  24  through a second transistor Q 2   40  of the high voltage section  22 . 
     With continued reference to  FIG. 2 , the operation of the invention can be understood by following an electrical path through the bridge portion  14  beginning with the low voltage section  12  output signal passing through the isolation capacitor  20  at node N 2  Those skilled in the arts will readily perceive that the mirror image bridge  14  ( FIG. 1 ) functions in a like manner with the clock cycles reversed, forming a full bridge rectifier circuit  10 . The invention may be practiced in full or half bridge configurations. 
     If the control signal output by the low voltage Section  12  is off (EN_HI is off), node N 2  is at ground. Capacitor C 2   34  couples any voltage on node N 4  to the gate of transistor M 1   36 , node N 5 . As voltage between nodes N 4  and N 6  (N 5  is approximately the same voltage as on N 4 ) rises above the threshold voltage of M 1   36 , M 1   36  will begin conducting and short the gate of Q 1   38  to the source (N 4  to N 6 ), effectively limiting the node N 4 -N 6  voltage difference to about 1V. Preferably M 1   36  has a threshold voltage of about 0.7V and Q 1   38  has a threshold voltage between 2.5 and 5.5 Volt. This difference in turn-on voltage effectively means that Q 1   38  remains off in the event of a voltage spike on node N 8  while the control signal is low. 
     To provide protection for fast rising surges in the high voltage section  22 , a normally-off NMOSFET is preferred for M 1   36 . If a positive spike were to arise on the high voltage drain of Q 1   38 , there would be a risk that the parasitic collector-gate capacitance (N 8  to N 4 ) could feed a substantial portion of this peak to the Q 1   38  gate, possibly turning on Q 1   38  at an inappropriate time. The configuration shown in  FIG. 2  provides inherent protection against this undesirable turn-on. During normal OFF state operation, any transient attempt to charge the Q 1   38  gate results in transistor M 1   36  turning on before the gate of Q 1   38  reaches its threshold voltage. This is because the threshold of transistor M 1   36  is only about 0.7V while that of transistor Q 1   38  is about 2.5 to 5.5V. Transitor M 1   36  effectively acts as an AC coupled forward diode in this configuration limiting the voltage across nodes N 4 -N 6  to about 1.0V. 
     If the low voltage section  12  control signal is on (EN_HI on), typically the control signal oscillates at Fosc=10 MHz-20 MHz), and there is a charge transfer from node N 3  to node N 4  via the forward-biased diode  26 . This charge is stored in the parasitic gate-source capacitance of Q 1   38 . When N 3  goes negative with respect to N 4 , there is a charge transfer to the isolation capacitor  20  from N 6  and from N 5  via N 3 . Node N 5  then slowly discharges towards N 4  with a time constant (Trc) determined by the value of the resistor R 2   32  and by the total capacitance at node N 5 . The total capacitance is typically dominated by C 2   34 . The time constant determined by R 2   32  and C 2   34  is preferably made substantially longer than the inverse frequency of the incoming AC signal on N 2  so as to maintain the voltage on N 5  as close to that of N 6  as possible, ensuring that M 1   36  stays in an OFF-state. Under the condition Trc&gt;&gt;1/Fosc the gate-emitter voltage (N 4 -N 6 ) of Q 1   38  increases and eventually reaches its turn-on voltage. The gate-emitter capacitance of Q 1   38 , diode D 3   30  and diode D 1   26  ensures that node N 4  follows node N 6  to the high voltage. Once M 1   36  has reached its turn-on voltage, the circuit  14  acts as an AC source follower, thereby pushing N 6  up by the peak-to-peak value, the AC voltage (minus a few diode forward drops) at node N 2  for every clock cycle. Hence, shorter rise time is achieved with high node N 2  AC voltage and high frequency. 
     Once N 6  has reached a value close to that of node N 8  (high voltage section  22 ), then the AC current from node N 2  fails to further push up node N 4 . This node is then charged with the full swing of AC voltage (N 2 ). Note that at this point voltage at node N 4  exceeds voltage at node N 8 . Thus, circuit  10  turns on Q 1   38  from a capacitively isolated low voltage source  12 . While in this state, little current is consumed by the bridge section  14  as C 2   20  and the gate of Q 1   38  are fully charged. 
     When the oscillator stops (setting EN_HI to ground), node N 5  discharges towards node N 4 . When N 5 -N 6  voltage goes beyond the M 1   36  threshold voltage, M 1   36  turns on shorting N 4  and N 6  which, in turn, leak the charge from the gate of Q 1   38  and turns it off. 
       FIG. 3  depicts the invention embodied in an implantable cardiac defibrillator, denoted generally as  50 , in an epicardial implantation. Those skilled in the arts will appreciate that the invention may be used with various types of atrial, ventrical, or other defibrillators using various implantation configurations. The device  50  is connected to leads  11  positioned inside the heart  13  used to deliver electrical impulses, sense the cardiac rhythm, or pace the heart  13 . 
     To implement the bridge circuit  14  and the high voltage isolation capacitor  20  on the same integrated circuit, certain characteristics are desirable for the components.  FIGS. 4-8  show cross-sections of preferred embodiments of these bridge circuit  14  components for use with the invention. 
     Referring to  FIG. 4 , the forward-biased diode D 1   26  must effectively reverse block the full voltage swing at node N 2 . In most CMOS processes, P−/N− well diodes provide high breakdown voltage. Unfortunately, these diodes (P-well/N-substrate) are prohibitively slow for high-speed applications, such as cardiac defibrillators. Therefore, it is preferred to use a N+/P-well bipolar transistor in a diode configuration. This provides a high voltage diode D 1   26  capable of operating at high speeds yet adaptable to standard CMOS fabrication processes. 
     In addition to blocking reverse voltage, diode D 1   26  must be fast enough to switch the AC control signal from node N 2 . A problem which can arise with normal simple diodes P+/N− for example, is that the injected forward current, holes in the N− material, is available only after the minority carriers have recombined, resulting in a delay. This delay makes such devices relatively slow. Faster switching is achieved if a bipolar connection is used. The minority carrier flow is only through the base  40  and the current is readily available once it reaches the collector (N− substrate). These devices are, therefore, much faster than the simple bipolar diodes. Proper polarity for the diode is obtained when the substrate (P−) is connected to the N−/well (and the P-base). Alternatively, diode device D 1   26  may be made using Schottky junction metal-semiconductors. 
     Referring now to  FIG. 5 , reverse-biased diodes D 2   28  and D 3   30  have the same voltage breakdown and speed requirements as diode D 1   26 , but they must function when connected with the opposite polarity. Adequate performance may be maintained by connecting the P− well  52  to the emitter (N+)  54 , resulting in a base-emitter diode with the emitter  54  tied to the well node  52 . The base  53  is then tied to the N-substrate  56 . Diodes made using minimum design rules provide little parasitic capacitance while having enough forward drive capability and enough speed. For D 2   28  and D 3   30 , it is preferred to substitute P-well/N-substrate transistors connected with the base-collector common (N+). 
       FIG. 6  depicts a preferred embodiment of transitor M 1   36 . M 1   36  is a moderate-voltage NMOSFET (−20V) made in a well  62  to isolate it from the input low voltage control signal. The preferred configuration allows the source junction  64  to be isolated from the substrate  66 , reducing the risk of latch-up. Such a configuration lets a parasitic diode (D 1   26 ) come between the drain  68  and the substrate  66 , which is in parallel with D 1   26 . However, D 1   26  is a fast-switching diode compared to the well diode, and in AC, D 1   26  dominates current flow. The drawback from the parasitic drain diode D 3   30  at M 1   36  is added junction capacitance, which reduces reverse voltage (AC current) isolation. For this reason, M 1   36  is preferably kept small. Since transistor M 1   36  is only active during the fall time (t fall ), it is important to ensure that proper discharge with fast enough drop rate is present. Fast drop rate and fast rise rate are required to prevent the power driving transistor Q 1   38  from thermal runaway, which would destroy it. Specification for this minimum rise-fall time should be in line with the requirements of the transistor used for Q 1   38 . In the preferred embodiment, t rise  and t fall  are less than about 50 uSec from 1000V. The P-well  68  of M 1   36  is tied to the most negative node in the circuit, which is node N 6 , the Q 1   38  emitter (FIG.  2 ). This node (N 6 ) also corresponds to the source connection  64  of M 1   36 . A N+ buried layer  70  under the N-well eliminates vertical NPN action when the drain-substrate diode D 1   26  is forward biased. Such a configuration creates a collected current at the source  64  and reduces the charge build-up at node N 4 . 
     While the invention has been described with regard to specific and illustrative embodiments, this description and the following claims are not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments as well as other embodiments of the invention will become apparent to persons skilled in the art upon reference to the description and is intended that such variations be encompassed and included within the meaning and scope of the following claims.