Abstract:
In one embodiment, an interface facilitates communication of data between a source block and a sink block. The interface comprises a first register element that receives data from the source block via an input line, wherein the first register element changes value when a clock enable signal is applied to the first register element and maintains its value when the clock enable signal is not applied; a first multiplexer coupled to the input line and an output of the first register element; and a first shift register for receiving a signal from the sink block indicating that the sink block is retrieving data from the interface; wherein the first shift register outputs a delayed version of the signal from the sink block to provide the clock enable signal to the first register element and to control an output of the first multiplexer.

Description:
TECHNICAL FIELD  
       [0001]     The present application is generally related to an interface for communicating data between logic blocks.  
       BACKGROUND  
       [0002]     When designing electronic devices, data is typically communicated between respective logic devices of a device. However, the timing of the operation of the various devices may vary thereby complicating the exchange of data. Accordingly, it is frequently desirable to provide an interface between logic devices to facilitate data communication.  
         [0003]      FIG. 1  depicts a conventional system using first in, first out (FIFO) interface  101  disposed between digital-to-analog converter (DAC)  102  and memory  103 . DAC  102  operates, in real time, and receives digital samples from FIFO  101  at frequency F o . FIFO  101  provides a signal to memory  103  whenever FIFO  101  is not full and, in response, memory  103  provides data to FIFO  101 . Accordingly, FIFO  101  “pulls” data from memory  103 . Also, memory  103  operates at a frequency of F m  which is greater or equal to F o . Accordingly, data is always available in FIFO  101  for provision to DAC  102 . Although the use of FIFO interfaces in this manner operates reasonably well, FIFO interfaces possess limitations. In particular, FIFO interfaces require circuit designs to include greater complexity than desired and also impose a degree of latency.  
       SUMMARY  
       [0004]     Some representative embodiments are directed to an interface for communicating data between logic blocks and a method of operation. In some representative embodiments, data is communicated according to “data pull” flow control. Specifically, a pull signal is asserted upon the retrieval of data to indicate that additional data should be made available upon the next clock cycle. In some representative embodiments, one or several delay elements are used by the interface to delay the assertion of a pull signal by a “sink” block from the assertion of a pull signal by the interface to a “source” block. Additionally, in some representative embodiments, one or several register elements are used to hold data until the next assertion of the pull signal by the sink block. A multiplexer is used to control the output from the register elements to the sink block. In alternative embodiments, a look-up table or suitable combinatorial logic is used to control the multiplexer using the history of pull signal assertions by the sink block.  
         [0005]     By using the delayed assertions of the pull signal in this manner, data may pass directly from the source block to the sink block when the pull signal is continuously asserted. Also, when the pull signal transitions from being asserted to not being asserted, the delay ensures that a data element from the source will be immediately available upon the next assertion of the pull signal. Specifically, the delayed pull signal causes an additional data element to be obtained from the source block and stored in a register element until the next assertion of the pull signal. Accordingly, the delay of the pull signal in conjunction with the operation of the multiplexer enables data pull flow control to occur in a cascaded manner between multiple logic blocks without restricting the frequencies of the respective pull signals. Additionally, the physical implementation of interfaces may involve substantially less complexity and latency than traditional FIFO interfaces. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIG. 1  depicts a system having a traditional FIFO interface.  
         [0007]      FIG. 2  depicts a timing diagram of data pull flow control.  
         [0008]      FIG. 3  depicts a system that employs data pull flow control.  
         [0009]      FIG. 4  depicts a register element that may be employed within interfaces according to some representative embodiments.  
         [0010]      FIG. 5  depicts an interface according to one representative embodiment.  
         [0011]      FIG. 6  depicts a timing diagram associated with the interface shown in  FIG. 5 .  
         [0012]      FIGS. 7 and 8  depict interfaces according to alternative embodiments.  
         [0013]      FIG. 9  depicts values for a look-up table for the interface shown in  FIG. 8  according to one representative embodiment.  
         [0014]      FIGS. 10-12  depict ambidextrous interfaces according to alternative embodiments. 
     
    
     DETAILED DESCRIPTION  
       [0015]     Some representative embodiments are directed to interfaces that are compliant with a data pull flow control method. To illustrate an example of data pull flow control, reference is made to  FIG. 2 . The operation of data pull flow control occurs using system clock  201 . A pull assertion signal  202  (denoted by Pull i ) signifies that data  203  present on the data line(s) will be taken on the next rising edge and new data is to be made available for the next data pull assertion.  
         [0016]     Initially, data D s  is present on the data line. Pull assertion  211  only lasts one clock cycle and, accordingly, only one data element is taken. Specifically, pull assertion  211  occurs to obtain the data from the data line at rising edge  221  thereby causing data D s  to be replaced by data D s+1 . Pull assertion  212  lasts two clock cycles and causes data D s+1  and D s+2  to be taken at rising edges  222  and  223 , respectively. Likewise, pull assertion  213  lasts three clock cycles and causes data D s+3  through D s+5  to be taken.  
         [0017]      FIG. 3  depicts system  300  that employs data pull flow control in a cascaded manner. Data originates from data source  304  and is processed by interpolators  302  and  303 . The interpolated data is provided to DAC  301  to generate an analog signal. DAC  301  is the final data sink in system  300 , i.e., no further propagation of the digital data occurs after DAC  301 . DAC  301  provides a pull assertion signal (denoted by Pull In) according to the system clock that operates at frequency F S . Interpolator  302  generates K 2  output samples for every input sample. Interpolator  302  provides a pull assertion signal (denoted by Pull  12 ) every K 2  clock cycles to interpolator  303 . Interpolator  303  generates K 1  output samples for every input sample. Interpolator  303  provides a pull assertion signal (denoted by Pull Out) every K 1 *K 2  clock cycles to data source  304 .  
         [0018]     As seen in  FIG. 3 , the data pull flow control is complicated by the fact that the control signals propagate in the opposite direction as the data signals. Depending upon the state of the data flow, it is possible that a pull signal initiated from DAC  301  would need to be propagated to data source  304  within a single clock cycle. The ability to propagate the signal to the original source block may not be possible depending upon circuit complexity (especially if multiple logic blocks are cascaded). Additionally, if K 1 or K   2  is not an integer (e.g., rational resampling is performed), the combinatorial relationships between the pull signals of the various logic devices can be complex.  
         [0019]      FIG. 4  depicts a notational convention that is used to reduce the complexity of other FIGURES of interfaces adapted according to some representative embodiments. Register element  400  depicts a register (denoted by z −1 ) with two “heavy” lines used to communicate data and one “lighter” line that is associated with a clock enable signal. In operation, register element  400  retains its stored value when the clock enable signal is not present and changes its stored value when the clock enable signal is present. Corresponding structure  450  represents a physical implementation of the operation of register element  400 . Corresponding structure  450  includes multiplexer  452  coupled to input data line  454  and coupled to the output of register  451 . The output of multiplexer  452  is controlled by the signal present on line  453 . When the signal is high, multiplexer  452  outputs the data received via line  454 . When the signal is low, multiplexer  452  outputs the data received from the output of register  451  thereby feeding back the data to register  451 .  
         [0020]      FIG. 5  depicts synchronous interface  500  adapted for data pull flow control according to one representative embodiment. Interface  500  receives data from a prior logic block (not shown) and provides data to a subsequent logic block (not shown). When the subsequent logic block retrieves data (Data R ), the subsequent logic block asserts the Pull R  signal to request that the next data element be made available at the next clock cycle. Interface  500  retrieves the data elements from the prior logic block using the Data L  line. Interface  500  asserts the Pull L  signal when it retrieves data to ensure that the next data element is available at the next clock cycle.  
         [0021]     Interface  500  comprises shift register  501  to provide a delay between the assertion of the Pull R  signal and the assertion of the Pull L  signal. Additionally, the delayed pull signal is used to control register element  400  and multiplexer  504  via lines  502  and  503  respectively. By using the delayed pull signal in this manner, interface  500  is operable to enable data elements to pass directly from the prior logic block to the subsequent block when the Pull R  signal is continuously asserted. Also, when the Pull R  signal transitions from being asserted to not being asserted, the delay ensures that a data element from the prior subsequent block will be immediately available upon the next assertion of the Pull R  signal. Specifically, the delayed pull signal causes an additional data element to be obtained from the prior logic block and stored in register element  400  until the next assertion of the Pull R  signal. Accordingly, the delay of the pull signal in conjunction with the operation of multiplexer  504  and register element  400  enables data pull flow control to occur in a cascaded manner without restricting the frequencies of the respective pull signals.  
         [0022]      FIG. 6  depicts timing diagram  600  associated with the operation of interface  500 . Timing diagram  600  illustrates the system clock, the Pull R  signal, the Pull L  signal, the Data L  signal, the output of register element  400  which is provided to the first input (MUX 0 ) of multiplexer  504 , and the Data R  signal. Initially, the respective pull signals are not asserted. The Data R  signal and the MUX 0  signal have a value of D N . The Data L  signal has a value of D N+1  as provided from the block prior to interface  500 .  
         [0023]     The Pull R  signal is initially asserted at time  601  and, hence, the logic block that is subsequent to interface  500  retrieves data element D N . The Pull L  signal is then asserted at the next clock cycle (time  602 ) due to the delay provided by shift register  501 . At that time, multiplexer  504  outputs the value (D N+1 ) present on its other input (MUX 1 ) which is the Data L  signal. Specifically, control line  503  of multiplexer  504  receives the delayed pull signal thereby causing multiplexer  504  to output the value of its second input line. Accordingly, the Data R  signal changes value to D N+1 . At time  602 , the value of register element  400  changes to the value (D N+1 ) of the Data L  signal, because its clock enable signal is the delayed pull signal. Also, at time  602 , the Pull R  signal is no longer asserted.  
         [0024]     At time  603 , the block preceding interface  500  makes the next data element available (the Data L  signal changes to value D N+2 ). Due to the delay provided by shift register  501 , the Pull R  signal is not asserted. Also, due to the delay provided by shift register  501 , multiplexer  504  switches to its first input (MUX 0 ) which is received from register element  400 . Register element  400  outputs the value received in the previous cycle (D N+2 ). Also, because the clock enable signal is no longer provided to register element  400 , register element  400  maintains its value and, hence, the Data L  signal remains at a value of D N+2 .  
         [0025]     The effect of multiple cycle assertions of the Pull R  signal can been seen in reference of times  605 - 608 . Interface  500  operates in substantially the same manner as previously described, except, upon the repetition of the assertion of the Pull R  signal, multiplexer  504  allows data to flow directly from the prior block to the subsequent block.  
         [0026]     As shown in  FIG. 7 , interface  700  operates according to data pull flow control according to another embodiment. Interface  700  operates in substantially the same manner as interface  500  except interface  700  comprises register elements  400 -A,  400 -B, and  400 -C. Interface  700  addresses the additional delay through the multiplexer, eliminates phantom transitions, and unloads the output pull register. Although interface  700  does not satisfy a strict “registered-in, registered-out” requirement (the pull signal gates the source register), interface  700  is suitable for most internal applications (e.g., with an ASIC or FPGA).  
         [0027]     Interface  800  (as shown in  FIG. 8 ) performs registered-in, registered-out operations and is suitable for synchronously clocked interfaces according to another representative embodiment. Interface  800  comprises shift register  501 - 1  to register-out data from the source block to the sink block. Also, interface  800  comprises shift register  501 - 3  to register-in the pull signals from the sink block to the source block. Interface  800  further comprises registers  501 - 2  and  501 - 4  on the sink block side that correspond to registers  501 - 1  and  501 - 3 . Additionally, interface  800  comprises register  501 - 9  to store the data before additional processing by the sink block.  
         [0028]     Because of shift registers  501 - 1  through  501 - 4 , there is a four clock cycle delay before the assertion of the Pull o  signal and the availability of new data. Interface  800  comprises register elements  400 - 1  through  400 - 4 , shift registers  501 - 5  through  501 - 8 , look-up table  801 , and multiplexer  802  to address the four cycles of delay. Register elements  400 - 1  through  400 - 4  enable four data elements to be stored between disjoint assertions of the Pull o  signal to enable a data element to be immediately available when needed.  
         [0029]     Depending upon the pattern of assertions of the Pull o  signal, different patterns of register elements  400  will have valid data. For example, if the Pull o  signal has been continuously asserted for a long time, only the output of shift register  501 - 2  will be associated with valid data. Alternatively, if the Pull o  signal has not been asserted for a long time, all of registers elements  400 - 1  through  400 - 4  will have valid data. Shift registers  501 - 5  through  505 - 8  maintain a history of the recent states of the Pull o  signal. The outputs of shift registers  501 - 5  through  505 - 8  are provided to look-up table  801 . The purpose of look-up table  801  is to identify the proper location of data when the Pull o  signal is asserted. Look-up table  801  may be implemented using table  900  shown in  FIG. 9 . In one embodiment, the look-up value is defined by the number of assertions of the Pull o  signal within the past four clock cycles. Other logic designs may be employed to perform the determination if desired. For example, combinatorial logic may be employed. Alternatively, logic  801  may increment, decrement, and maintain a count depending upon the outputs of shift registers  501 - 5  through  501 - 8 . Specifically, if the left most signal is asserted and the right most signal is not asserted, the count is incremented. If the left most signal is asserted and the right most signal is not asserted, the count is decremented. If both are in the same state, the count is maintained.  
         [0030]     In addition, some representative embodiments may provide an interface for “ambidextrous” interfaces. Ambidextrous interfaces generally refer to interfaces in which data flow control is communicated according to the coincidence of “data valid” signals (data is ready to the communicated) and “data requested” signals (pull signals). Interface  1000  shown in  FIG. 10  depicts a general case of ambidextrous data flow control according to one representative embodiment. Data i    1003  is received from a source block when the source block indicates that it has data available by asserting DV i  signal  1005  and when the interface asserts DR o  signal  1004 . Data o    1006  is communicated from interface  1000  to the sink block when interface  1000  indicates that data is available using DV o  signal  1008  and when the sink block indicates that it is ready for data using DR i  signal  1007 .  
         [0031]     The internal elements of interface  1000  operate in a similar manner to the internal elements of interface  800 . Interface  1000  includes a plurality of register elements  400  (K+L) to hold data when appropriate and to enable data to pass through interface  1000  when appropriate. A subset of register elements  400  may be disposed on both sides of the interface plane between the source device and the sink device. Also, a subset of register elements  400  are coupled to multiplexer  1003 . A plurality (K+L) of shift registers  501  buffer DR i  signals  1007  and a subset of those shift registers  501  are coupled to binary weight computation logic  1001 . From the outputs of the subset of shift registers  501 , binary weight computation  1001  determines the location of the next valid data element and controls multiplexer  1003  accordingly. Additionally, a plurality (K+L) of shift registers  501  buffer DR i  signals  1007  and a subset of shift registers  501  are coupled to multiplexer  1002 . Also, binary weight computation  1001  controls multiplexer  1002  to provide values associated with DV o  signal  1008 .  
         [0032]     Interface  1000  may be considered a general case from which other interfaces may be derived. Specifically, interfaces  500 ,  700 ,  800 ,  1100  and  1200  are all special cases of interface  1000 . Also,  FIGS. 11 and 12  depict related ambidextrous interfaces  1100  and  1200  according to some representative embodiments. Ambidextrous interface  1100  is an ambidextrous design that is similar to the registered-in, registered-out design of interface  800 . Likewise, ambidextrous interface  1200  is an ambidextrous design that is similar to the design of interface  700 .  
         [0033]     By implementing interfaces using delayed assertions of pull signals, some representative embodiments may provide a number of advantages. For example, data may continuously pass from a source block to a sink block when the pull signal is continuously asserted. Also, when the pull signal transitions from being asserted to not being asserted, the delay ensures that a data element from the source will be immediately available upon the next assertion of the pull signal. Specifically, the delayed pull signal causes one or several additional data elements to be obtained from the source block and stored in appropriate register element(s) until the next assertion of the pull signal. Also, by suitably controlling a multiplexer coupled to the register elements, data pull flow control may occur in a cascaded manner between multiple logic blocks without restricting the frequencies of the respective pull signals. Additionally, the physical implementation of interfaces may involve substantially less complexity and latency than traditional FIFO interfaces.