Abstract:
A driver ( 300 ) which meets wide common mode voltage requirements is provided. Output passgates ( 310 ) protect sensitive line driver circuitry ( 305 ) from extreme bus voltages; enabling/disabling circuits ( 315, 316 ) detect fault conditions to ensure the line driver is disabled when needed, and pull-ups ( 320 ) assist in line driver start up by preventing negative voltage conditions on the bus driven by the line driver.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field of the Invention 
     The present invention relates generally to the field of transistor circuits and more particularly to a low voltage differential signal driver. 
     2. Description of the Related Art 
     Various standards have been promulgated in the field of data transmission. One type of data transmission is differential data transmission in which the difference in voltage levels between two signal lines form the transmitted signal. Differential data transmission is commonly used for data transmission rates greater than 100 megabits per second (Mbps) over long distances. 
     One application of differential data transmission is in a network using a bus to which multiple driver sources are attached. In one type of conventional circuit, the multiple drivers are connected to a common bus, in which only one driver may transmit at a time. The remaining drivers are typically in a high impedance state so as to not overload the bus. Since large positive and negative common mode signals may appear at the driver output terminals connected to a bus system, the maintenance of a high impedance over a wide common mode voltage range independent of whether the driver is powered or not, is desirable. Large positive and negative common mode signals seen across a bus can be caused by ground offsets among various drivers, which could drive the bus to voltage levels that could prove damaging to other devices attached on the bus. 
     In a multipoint system it is desirable to have a robust driver capable of withstanding a wide common mode range. Each driver in the system should also be very high impedance when disabled, so the leakage currents of disabled drivers do not degrade the transmission of data. Also, the driver should not be allowed to supply excessive currents which could damage the bus itself. 
     An example of a conventional low voltage differential signal (LVDS) driver circuit  100  is shown in FIG.  1 A. The output terminals  102  and  104  form a pair of single-ended signals, one of which is the inverse of the other. The difference between these two signals constitutes the differential signal. This signal is essentially the voltage across the resistive load between y and z, which is either positive or negative depending on the direction of current flow across the load. The LVDS driver circuit  100  includes a direct current constant current source I 0  and sink I 1  coupled to voltage supply VCC and ground, respectively, and four n-channel metal, oxide semiconductor (NMOS) switches MN 0 , MN 1 , MN 5  and MN 6 . The four transistor switches MN 0 , MN 1 , MN 5  and MN 6  are controlled by input voltage signals pos  106  and neg  108 , and direct current through a load resistance between output pins y and z as indicated by arrows  110  and  112 . The input voltage signals pos and neg are typically rail-to-rail voltage swings. 
     The gates of NMOS switches MN 0  and MN 6  are coupled together to receive input voltage signal pos. Similarly, the gates of NMOS switches MN 1  and MN 5  are coupled together to receive input voltage signal neg. 
     For operation of the LVDS driver circuit  100 , two of the four NMOS switches turn on at a time to steer current from current source I 0  to generate a voltage across a resistive load between outputs y and z. To steer current through the resistive load in the direction indicated by arrow  110 , input signal neg goes high turning on NMOS switches MN 1  and MN 5 . When input signal neg goes high, input signal pos goes low to keep NMOS switches MN 0  and MN 6  off during the time NMOS switches MN 1  and MN 5  are on. Conversely, to steer current through the resistive load in the direction indicated by arrow  112 , input signal pos goes high and is applied to transistor switches MN 0  and MN 6  to make them conduct. Input signal neg goes low to keep MNOS switches MN 1  and MN 5  off during this time. As a result, a full differential output voltage swing can be achieved. 
     Circuit  120  is a typical common mode voltage regulator type circuit designed to regulate the center point of the driver circuit  100  during normal operation and FIG. 1B illustrates predriver logic which enables the pos and neg signals. The aforementioned drive circuit has a limited output voltage range over which the circuit functions properly. 
     SUMMARY OF THE INVENTION 
     The present invention achieves technical advantages in providing a differential signal to an external bus which can be driven by a plurality of devices. The invention includes a line driver configured to enable transmission of a differential output signal to the external bus. The invention further includes a voltage limiter which is electrically coupled to the line driver and the bus to limit voltage on the line driver. The voltage limiter and line driver can be enabled and disabled in response to voltage conditions on the external bus. A pull-up circuit can be provided to assist start-up of the line driver by preventing a negative voltage condition on the external bus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawings wherein: 
     FIG. 1A illustrates a low voltage differential signal driver circuit; 
     FIG. 1B illustrates predriver logic for the low voltage differential signal driver circuit of FIG. 1A; 
     FIG. 2 illustrates a block diagram of a differential driver in accordance with an embodiment of the present invention; 
     FIG. 3A illustrates a first circuit diagram portion of a differential driver in accordance with an embodiment of the present invention; 
     FIG. 3B illustrates a second circuit diagram portion of the differential driver of FIG. 3A; and 
     FIG. 3C illustrates a third circuit diagram portion of the differential driver of FIGS. 3A and 3B. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The numerous innovative teachings of the present application will be described with particular reference to the presently preferred exemplary embodiments. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses and innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features, but not to others. 
     The current proposed M-LVDS standard (Project Number PN-4828-2000 for Multipoint Data Interchange) specifies low-voltage differential signaling drivers and receivers for data interchange across half-duplex or multipoint data bus structures. The current revision of the proposed standard calls for a data transmission driver with an extended common mode voltage range of −1.4 to 3.8 V. In addition to requiring an output leakage current less than 32 μA through this range during high-impedance or power-off states, the M-LVDS standard also specifies a maximum output current of 43 mA per pin when the driver output terminals are short-circuited to a variable voltage source from −1 to 3.4 V. This requirement is designed to limit current output to a common bus during contention between multiple drivers. 
     Most low-voltage differential drivers, like the one illustrated in FIG. 1, have output stages consisting of a current source and sink with a switching H bridge (MN 0 , MN 1 , MN 5 , MN 6 ) which controls the direction of current flow through a differential load, connected between pins y and z. This topology is incapable of withstanding the excessive output voltages required by the aforementioned M-LVDS standard. For example, applying a large negative voltage (such as −1V) to the output will turn on NMOS backgate diodes to ground, resulting in excessive output currents. During tri-state, a large enough negative voltage could result in a Vt drop from the grounded gate to the source, turning on a transistor that has been disabled. On the opposite extreme of the voltage requirement, a large positive voltage can result in device breakdown by exceeding Vgs limits. In order to achieve a signaling rate of several hundred Mbps and run off a 3.3 V supply, fast switching 3V devices are preferably used in the H bridge of the driver. However, in some processes, these devices may not be rated high enough for proper operation. For example, 3 V MOS are only rated to a maximum Vgs of 3.6 V for certain 0.6 u BiCMOS processes, which is below the maximum positive output voltage of 3.8 V of the current proposed M-LVDS standard. 
     FIG. 2 illustrates a block circuit diagram  200  of an exemplary embodiment of the present invention. The circuit  200  includes a driver circuit  205 , 5V devices  210 , detection and enabling/disabling circuitry  215 , and pull-ups  220 . The driver circuit  205  can be, for example, the low voltage differential driver  100  shown in FIGS. 1A and 1B. The circuitry of the driver circuit  205  is electrically protected from extreme voltage requirements (such as associated with the aforementioned M-LVDS standards) by a voltage limiter implemented, for example, by passgates  210 . For example, the passgates  210  can be configured to limit voltages at the output nodes of the driver circuit  205  to a MOS threshold voltage below Vcc. Thus, 3V MOS type components can be used in the extended common mode voltage range without exceeding the electrical operating rating of the components. The passgates have a breakdown voltage exceeding the common mode voltage requirements. The passgates  210  are also configurable to limit the leakage current generally experienced from internal circuits. The detection and enable/disable circuit  215  is configured to detect an electrical condition on the bus which could damage and/or compromise proper operation of the drive circuit  205 , such as a negative voltage condition. The detection and enable/disable circuit  215  is further configured to enable enable/disable signaling to both the passgate  210  and the driver circuit  205  upon detection of a compromising electrical condition. The pull-ups  220  are used to pull bus voltage up to a level high enough to overcome negative voltage sensing circuitry (not shown) of the detection and enable/disable circuit  215  for a driver startup condition when the bus has been initialized to a negative value. For example, when the driver circuit  205  is signaled to drive during an initialized negative voltage condition on the bus, the negative voltage sensing circuitry may disable the driver circuit from driving if the pull-ups  220  do not pull-up the bus voltage to overcome the disablement threshold. 
     Referring now to FIGS. 3A,  3 B and  3 C (herein collectively referred to as FIG. 3) there is shown an exemplary embodiment of a differential driver apparatus  300  in accordance with the present invention. The differential driver apparatus  300  includes a driver  305  (e.g., the same driver  100  of FIGS. 1A and 1B) that is suitably protected to withstand the electrical requirements of the aforementioned M-LVDS standard. Also shown are output passgates  310 , detection circuitry  315 , enabling/disabling circuitry  316 , pull-ups  320  and reference circuit  330 . 
     The driver circuit  305  includes predriver logic circuitry and common mode voltage regulator circuitry. The passgates  310  are provided as two MOS type devices MN 9  and MN 10  which protect internal driver circuitry and limit leakage current. When the pass gates MN 9  and MN 10  are enabled, they block high voltages, limiting the voltage at internal nodes yint and zint to a MOS threshold voltage below VCC. This voltage limiting is acceptable because the maximum output voltage at these nodes is less than 1.6V during normal operation. During tri-state, the pass gates MN 9  and MN 10  are disabled, thereby blocking positive and negative voltage from the internal nodes and preventing overstress and excessive tri-state leakage from internal circuits. As high voltage devices, MN 9  and MN 10  can withstand the wider voltage range of the M-LVDS standard. 
     Regarding the backgate protection circuitry  312 , when the bus is pulled below ground, the backgates of the NMOS devices MN 10  and MN 9  are suitably biased to prevent excessive leakage currents from the parasitic backgate diode. Under normal operation, nbgy and nbgz, the backgate nodes, are connected to ground through MN 23  and MN 29  respectively. When the bus goes below ground, the MN 22  and MN 30  devices are turned on, connecting the backgate and the bus together, and shorting out the parasitic diode. 
     In addition to the pass gates MN 9  and MN 10 , the differential driver  300  includes circuitry to determine if the pass gates should be disabled to protect parts of the driver circuit  305 . The driver circuit  305  and passgates  310  are disabled when the enable input signal en* is high (driver in tri-state) and also when the voltage on the output at either of the pins y or z is pulled below ground while en* is low (driver enabled). The later case arises during a fault condition when the driver circuit  305  is enabled but the bus has been pulled to a negative value because of shorting or driver contention, for example. In this case, the driver circuit  305  is disabled to prevent damage to internal circuits and the bus caused by excessive output currents. 
     The enabling/disabling circuitry  316  implements the above-described enabling/disabling scheme. When the signal enbus is high, nodes eny and enz are pulled high, enabling passgates MN 9  and MN 10 . When enbus is low, eny and enz are pulled low, disabling the passgates. If the output voltage on y or z goes below ground while the passgates are disabled, corresponding MOS devices MN 2  and MN 8  of circuit  316  turn on and couple the bus voltage to enz and eny respectively. This shorts the gate and drain of passgates MN 9  and MN 10 , keeping them disabled. 
     When enz and eny are coupled to a negative bus voltage, additional leakage current could come from the devices used to pull-up and pull-down the nodes. The blocking devices MP 7 , MN 11 , MP 6 , and MN 3  are shut off when enz and eny are below ground (gnd), protecting the pull-downs MN 7  and MN 4  from negative voltage and preventing leakage to ground through MN 7  and MN 4  and their respective backgate diodes. 
     The level of enbus, the signal which enables or disables the driver circuit  305 , is determined by the detection circuitry  315 . The signal enbus is only high, enabling the driver circuit  305  and passgate  310 , when the active-low enable input signal en* is activated low and the bus voltage is positive, in other words,        enbus   =         en   *     _     ·       negbus   _     .                              
     Using deMorgan&#39;s Theorem, the equivalent expression is          enbus   =         en   *     +   negbus     _       ,                          
     which is implemented in the circuit by NOR gate  301 . The signal negbus acts as a detection flag for the voltage on the bus, going high when the bus voltage is negative and going low when the bus voltage is above ground. 
     The detection flag is generated through the various through-gates and pull-up devices of the detection circuit  315 . Normally, negbus*, the inversion of negbus, is pulled to VCC through MP 9 . The two pull-downs MP 1  and MP 5  are kept off by the weak pull-ups on their gates. When y and z are at about zero volts or below, the through-gates MN 12  and MN 13  respectively turn on, passing the voltage of y and z respectively to the gates of the pull-downs MP 1  and MP 5 . The pull-downs (either or both) can then turn on and pull negbus* to ground. When the bus is below ground, the weak pull-ups MP 8  and MP 10  will be a source of leakage, however, they can be suitably sized to leak only a few microamps. 
     In some situations, the bus may be initialized to a negative voltage, possibly because it was driven by a different driver with a negative ground offset, for example. In such circumstances, if the driver  305  is newly enabled using the enable input signal en*, the driver circuit  305  will not begin driving because a negative bus voltage will be detected by the detection circuitry  315  which will prevent the differential driver  300  from driving. 
     This situation can be avoided by operation of the pull-ups  320  which are connected to the outputs of the differential driver apparatus  300 . Each of the pull-ups at  320  includes a NMOS switch in series with a PMOS switch. Whether or not the PMOS switch is enabled is independent of the bus voltage. The pull-ups  320  are switched according to the regular enable input signal en*, so that when the driver circuit  305  should be enabled, the pull-ups  320  are enabled as well. Furthermore, when the driver circuit  305  is disabled, the pull-ups  320  are disabled, thereby eliminating the pull-up  320  as an additional source of leakage. Again, all devices are 5V tolerant and the two NMOS devices MN 14  and MN 15  have backgate protection circuits  312 . When the bus is pulled below ground, the backgates of the NMOS devices MN 14  and MN 15  are suitably biased to prevent excessive leakage currents from the parasitic backgate diode. Under normal operation, nbgy and nbgz, the backgate nodes, are connected to ground through MN 23  and MN 29  respectively. When the bus goes below ground, the MN 22  and MN 30  devices are turned on, connecting the backgate and the bus together, and shorting out the parasitic diode. 
     In some embodiments, the pull-ups  320  conduct a maximum of 3 mA of pull-up current, pulling the voltage of nodes y and z up to a maximum voltage of about 300 mV. This voltage level is high enough to overcome the negative voltage sensing circuitry of the detection circuit  315 , allowing the driver to turn on. This voltage level is also low enough so that when the driver is operating normally, the voltage on y and z is too high to generate an adequate Vgs on MN 14  and MN 15 , thus, the pull-up devices will be in cutoff and will not interfere with the normal operation of the driver. 
     The reference circuit  330  provides a predetermined reference voltage to selected transistor devices in the detection circuitry  315  and pull-ups circuitry  320 . In the detection circuitry  315 , the reference circuitry  330  approximately biases the gates of MN 12  and MN 13  to the turn on threshold. Thus, when pins y and z are near ground, the devices will begin to turn on. The reference circuit  330  provides a bias of 1.2 V to the gates of MN 14  and MN 15  in the pull-ups circuitry  320 . This limits the amount of pullup current supplied by the pullup devices, limits the voltage to which they can pull the bus up to a Vt below 1.2 V, and ensures that the pullups will not interfere with the normal operation of the driver since there will not be a large enough Vgs on MN 14  and MN 15  when the driver is running. 
     Although a preferred embodiment of the method and system of the present invention has been illustrated in the accompanied drawings and described in the foregoing Detailed Description, it is understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.