Abstract:
Switch cells consist of an array of power switches and passive components which can replace the main switches in many power topologies, allowing reduced switching loss without altering the power topology directly. The switch cell topology discussed herein utilizes a saturable resonant inductor to reduce the size and power loss of the cell. Additionally, the cell transfers energy stored in the inductor into a capacitor for efficient energy storage during the cell&#39;s conduction region. This energy is then transferred back to the system when the cell turns off, thus reducing the total switching energy.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to and is a continuation-in-part of U.S. Provisional Patent Application Ser. No. 61/836,887, filed on Jun. 19, 2013 entitled NONLINEAR RESONANT SWITCH CELL which is hereby incorporated by reference in its entirety. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     This invention was made with government support under want NNX11CA66C awarded by the National Aeronautics and Space Administration. The United States government has certain rights in the invention. 
    
    
     REFERENCE TO A MICROFICHE APPENDIX 
     Not Applicable. 
     RESERVATION OF RIGHTS 
     A portion of the disclosure of this patent document contains material which is subject to intellectual property rights such as but not limited to copyright, trademark, and/or trade dress protection. The owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent files or records but otherwise reserves all rights whatsoever. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to improvements in switch cells. More particularly, the invention relates to improvements particularly suited for providing debris protection of the vehicle mirror while also displaying decorative elements such as athletic team emblems or colors on vehicle side view mirrors. In particular, the present invention relates specifically to a flexible body suitable for installation over a vehicle mirror. 
     2. Description of the Known Art 
     As will be appreciated by those skilled in the art, switch cells are known in various forms. Soft-switched cells are an attractive means of reducing switching loss in power converters since the energy recovery method only needs to be developed once and the cell can then be reused on many types of power topologies. Some cell topologies can even absorb energy from the power topology&#39;s circuit elements such as the winding capacitance of a power transformer. In these cases, the cell may require slight tuning for each topology to achieve optimal energy recovery. Quasi-resonant switch cells offer simple circuit topologies and control; however, they exhibit high nonlinearity, their characteristics vary widely with changing loads, and they cannot be used with pulse width modulation (PWM). Snubbers can also decrease switching loss by reducing the amount of overlap between the power switch voltage and current. Snubbers are less efficient than quasi resonant cells because they only achieve pseudo soft switching i.e., overlapping is not completely eliminated. Many cell topologies, allow inductive energy to circulate within the cell which dissipates the stored energy in the semiconductor devices over time. The topology presented herein aims to mitigate some of these issues. 
     Articles disclosing information relevant to switch cells include: REFERENCES:
     [1] Cho, J. G.; Cho, G. H.; “Cyclic quasi-resonant converters: a new group of resonant converters suitable for high performance DC/DC and AC/AC conversion applications,” Proceedings of the IECON &#39;90, pp. 956-963 vol. 2, 27-30 Nov. 1990.   [2] S. Ben-Yaakov and G. Ivensky, “Passive lossless snubbers for high frequency PWM converters,” IEEE Applied Power Electronics conference, APEC-99, Dallas, 1999.   [3] M. L. Martins, J. L. Russi, and H. L. Hey, “Novel synthesis methodology for resonant transition PWM converters,” 8th Brazilian Power Electronics Conference, COBEP 2005.   [4] Yu-Ming Chang; Jia-You Lee; Wen-Inne Tsai; York-Yih Sun; “An H-soft-switched cell for single-switch nonisolated DC-to-DC converters,” Proceedings of the IECON &#39;93, pp. 1077-1082 vol. 2, 15-19 Nov. 1993.   

     Each of these articles is hereby expressly incorporated by reference in their entirety. 
     From these prior references it may be seen that these prior art patents are very limited in their teaching and utilization, and an improved switch cell is needed to overcome these limitations. 
     SUMMARY OF THE INVENTION 
     Switch cells consist of an array of power switches and passive components which can replace the main switches in many power topologies, allowing reduced switching loss without altering the power topology directly. The present invention is directed to an improved switch cell using a saturable resonant inductor to reduce the size and power loss of the cell. Additionally, the cell transfers energy stored in the inductor into a capacitor for efficient energy storage during the cell&#39;s conduction region. This energy is then transferred back to the system when the cell turns off, thus reducing the total switching energy. These and other objects and advantages of the present invention, along with features of novelty appurtenant thereto, will appear or become apparent by reviewing the following detailed description of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       In the following drawings, which form a part of the specification and which are to be construed in conjunction therewith, and in which like reference numerals have been employed throughout wherever possible to indicate like parts in the various views: 
         FIG. 1  shows the schematic diagram of the nonlinear switch cell. 
         FIG. 2  shows operational modes of the nonlinear switch cell. 
         FIG. 3  shows the key waveforms for the nonlinear switch cell. 
         FIG. 4  shows a size comparison of a 20 A pulsed, 40 uH saturable inductor (left) and a 20 A continuous, 40 uH linear inductor (right). 
         FIG. 5  shows an actual circuit with auxiliary switches, S 1 -S 3  (left) and main switch, Sm (right). 
         FIG. 6  shows auxiliary and main switches mounted with the switch cell&#39;s gate driver PCB. 
         FIG. 7  shows the power waveforms for the switch cell during turn-on (top) and turn-off (bottom). 
         FIG. 8  shows the power waveforms for the recovery circuitry. 
         FIG. 9  shows a comparison of switching energy vs. drain current between a single JFET (dashed) and the switch cell (solid) at 80 V (orange), 160 V (green), and 320 V (red). 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As shown in  FIG. 1  of the drawings, one exemplary embodiment of the present invention is generally shown as a nonlinear switch cell  100 . The cell  100  can replace main switch positions in many topologies of switching power converters. The energy recovery sink  102  portion of this diagram represents an energy sink within the power system. The cell  100  redirects a portion of the switching energy into this sink  102  during both turn-on and turn-off. This could include the input power bus, the converter&#39;s output, or an auxiliary power supply for the power system&#39;s controller and/or gate drivers. 
     The nonlinear resonant switch cell  100  includes a switch cell drain connection  150 , a switch cell source connection  152 , with a first junction gate field-effect transistor  154  with a first jfet drain  156 , a first jfet source  158 , and a first jfet gate  160 , the first jfet drain  156  is electrically connected to the switch cell drain connection  150 . Also included is a second junction gate field-effect transistor  162  with a second jfet drain  164 , a second jfet source  166 , and a second jfet gate  168 , the second jfet source  166  is electrically connected to the switch cell source connection  152 . Further shown is a third junction gate field-effect transistor  170  with a third jfet drain  172 , a third jfet source  174 , and a third jfet gate  176  with the third jfet drain  172  electrically connected to the first jfet source  158 , and the third jfet source  174  electrically connected to the switch cell source connection  152 . The resonant inductor  180  is shown with a first inductor terminal  182  and a second inductor terminal  184  and the first inductor terminal  182  is electrically connected to the first jfet source  158 . The second inductor terminal  184  is electrically connected to the second jfet drain  164 . Next is the recovery capacitor  190  with a first capacitor terminal  192  and a second capacitor terminal  194 . The first capacitor terminal  192  is electrically connected to the switch cell drain connection  150 . A drain clamp diode  200  is shown with a clamp anode  202  and a clamp cathode  204 . The clamp anode  202  is electrically connected to the second inductor terminal  184  and the clamp cathode  204  is electrically connected to the second capacitor terminal  194 . Still further, an energy transfer diode  210  is shown with a transfer anode  212  and a transfer cathode  214 . The transfer anode  212  is electrically connected to the second capacitor terminal  194 . Finally, an energy recovery component  102  is shown with a first terminal  220  and a second terminal  222  and the first terminal  220  is electrically connected to the transfer cathode  214  and the second terminal  222  electrically connected to the switch cell source connection  152 . 
     Optionally, one or more parallel connected main junction gate field-effect transistor  250  can be added with each main junction gate field-effect transistor including a main drain  252 , a first main source  254 , and a main gate  256 . Each main drain  252  is electrically connected to the switch cell drain connection  150 , and each main source  254  is electrically connected to the switch cell source connection  152 . 
     The key feature of this switch cell topology is the use of a nonlinear or saturable resonant inductor, Lr. In its linear region, Lr will have very high inductance which can virtually eliminate current rise in power switches during turn-on. When Lr saturates, its inductance becomes very low, causing the current through it to increase rapidly. If the saturation time is timed well with the transition time of the power switch, the switch will transition under a very effective pseudo zero current switching event. This allows significant reduction in the inductor&#39;s volume, weight, and power loss. Another benefit is that the saturable inductor will fully transition much faster than a linear inductor, allowing higher switching frequencies. The main requirement for using a saturable inductor in a switch cell is insurance of flux resetting. When the inductor saturates in one direction, its flux density will remain near saturation, also known as the remnance point, even under zero magnetization. Thus, at the next switching event the inductor will not be able to pass through its linear region because it is already virtually saturated. Most of the switch cell topologies surveyed could not reverse the flux in the inductor, and none were able to accomplish flux reversal efficiently. Portions of the topology presented here are designed specifically for efficient flux reversal of Lr. 
     The main power switches Sm shown as parallel main switch  250  is optional if lower on-resistance is desired. Removal of Sm may be desirable to reduce complexity of the cell&#39;s gate driver circuitry. If Sm is removed, all of the drain current flows through S 1  and S 3  in the ON state. It is desirable to have S 1  and S 3  be fast devices to reduce the size of Lr. However, this has the effect of increasing on-resistance and, thus, power dissipation of these components during conduction. Sm can be a much larger device with low on-resistance. Its larger drain-source capacitance will present more stored energy; however, some of that energy can be absorbed by the cell and redirected to the energy recovery circuit. Since this redirection is imperfect, switching losses will continue to increase with increasing size of Sm and the optimal sizing of Sm will eventually reach a maximum. 
     The nine operational modes of the switch cell are displayed in  FIG. 2  and the corresponding key waveforms are shown in  FIG. 3 . The mode diagrams are analyzed in a clamped inductive circuit, which is a standard means of measuring switching loss in power devices. The clamped inductance is assumed to be large enough that the load current, Io, does not change significantly in the switching period. Power switch capacitances are shown in the mode diagrams to clarify transient current paths. The waveforms assume that the energy recovery voltage is half of the bus voltage, Vo. The modes are explained as follows: 
     Mode 1. (t 0 , t 1 ): This mode is the switch cell&#39;s OFF state. S 1  and Sm are off and the load current is flowing through the freewheeling diode of the clamped inductive test setup. S 2  and S 3  are on to prevent any ringing at the drain from affecting Lr. 
     Mode 2. (t 1 , t 2 ) This mode initiates the switch cell&#39;s turn-on process. S 3  is turned off to insert dead time between the transition of S 3  and S 1  in the next mode. 
     Mode 3. (t 2 , t 3 ): S 1  turns on with pseudo zero current switching since Lr is at 0 A and cannot change instantaneously. With sufficiently large inductance of Lr, the contribution of switching loss due to load current is insignificant. Energy required to transition the capacitances of S 1  and S 3  are the main source of loss in this mode. When S 1  fully turns on, Vo is applied across Lr. This increases its flux density until it reaches saturation at t 2 +tsat. After saturation, Lr reduces to a very small inductance, allowing a rapid increase in current through S 1 , Lr, and S 2 . The time t 3 −t 2  is defined by the time required to saturate Lr and increase its current to Io. 
     Mode 4. (t 3 , t 4 ): When ILr reaches Io the freewheeling diode becomes reversed biased and the drain voltage begins to fall. Energy stored in the capacitances of Sm and S 2  are transferred into Lr. When the drain voltage equals −VCr, clamp diode D 2  conducts and clamps the +side of Cr to ground. D 2  has an anode A and a cathode C as understood in the art and as shown in the schematic of  FIG. 1 . Energy stored in Cr is transferred into Lr. The transferred capacitive energy manifests as increased current over Io in Lr. The time t 4 −t 3  is defined by the time required to reach steady state on the drain voltage. 
     Mode 5. (t 4 , t 5 ): The drain voltage fully transitions low. Sm and S 3  are turned on with true zero voltage switching. Sm will most likely be physically located far away from the rest of the cell since it is a larger device. The resulting parasitic inductance will cause the current to rise slowly in Sm and may span several modes. Thus, S 3  “catches” S 1  in this mode, preventing the drain from transitioning high in the next mode where the main current path would otherwise be redirected away from ground. The time t 5 −t 4  is defined by the time required to fully turn on S 3 . 
     Mode 6. (t 5 , t 6 ): S 2  turns off under pseudo zero voltage switching. ILr charges the capacitance of S 2  and Cr through D 2 . ILr decreases as the energy stored in Lr is transferred into Cr and S 2 . If the energy in Lr is enough to make VCr increase to the energy recovery voltage, D 1  will forward bias and any remaining energy will be delivered to the energy recovery circuitry. D 1  has an anode A and a cathode C as understood in the art of diodes as shown in  FIG. 1 . The time t 6 −t 5  is defined by the time required to fully deplete ILr to zero. 
     Mode 7. (t 6 , t 7 ): This mode completes the switch cell&#39;s turn-on process. The voltage on S 2  is retained by S 2 &#39;s capacitance. This voltage is applied across Lr, which reverses its magnetization until it saturates in the opposite direction. This causes the voltage on S 2  to fall to ground. The energy transferred from S 2 &#39;s capacitance is dissipated as conduction loss in Lr, S 2  and S 3  in the next mode. The time t 7 −t 6  is defined by the time required to fully transition the voltage on S 2  to zero. 
     Mode 8. (t 7 , t 8 ): This mode is the switch cell&#39;s ON state. S 2  is turned on with true zero voltage switching. S 2  prevents a possible oscillation with Lr and S 2 &#39;s capacitance, and preserves the polarity of flux density in Lr. The latter is especially important since a flux reversal at this point would cause Lr to instantly saturate at the next turn-on, thus eliminating the pseudo zero current switching of S 1 . 
     Mode 9. (t 8 , t 9 ): This mode is the switch cell&#39;s turn-off state. S 1  and Sm are turned off with pseudo zero voltage switching. If D 1  is already forward biased, the drain current instantly transfers to Cr, delivering current to the energy recovery circuitry and discharging Cr. S 3  must remain on during this transient to prevent the capacitance of S 1  from pulling up the voltage across Lr, which could cause flux reversal. The time t 9 −t 8  is defined by the time required to fully transition the drain voltage to Vo. 
     Switch Cell Fabrication 
       FIG. 4  shows the saturable resonant inductor (left) along next to a U.S. dime coin with an equivalent linear inductor (right). The current through the saturable inductor is pulsed; therefore, its wire diameter can be greatly reduced. Most of the switch cell topologies implementing linear inductors allow the main current to pass through them continuously, thus requiring a larger wire size. The saturable inductor has 10× lower power loss and 77× smaller volume than the linear inductor. Since the reduction in volume is greater than the reduction in power loss, the temperature rise of the saturable inductor is higher. Depending on operating conditions, the saturable inductor may require attachment to the power system&#39;s heatsink. 
       FIG. 5  shows the packaged auxiliary switches, S 1 -S 3  (left) and the main switch, Sm (right), which consists of twelve power devices of the same size as the auxiliary devices. The switches are packaged on direct bond copper (DBC) substrates in a metal package and passivated with a high voltage gel. Each device is a SemiSouth 1200 V 50 mΩ SiC junction gate field-effect transistor JFET with a source (S) a drain (D) and a gate (G) commonly understood in the art and as labeled in  FIG. 1 . These devices require local gate-source capacitors to reduce ringing and chance of parasitic turn-on during transients on their drains. Zener diodes are also included in the package to prevent voltage spikes on the gates. Cr is also included in the package to reduce parasitic inductance between Cr and the auxiliary switches. 
       FIG. 6  shows the auxiliary and main switches mounted with the cell&#39;s gate driver PCB. The gate driver requires only the PWM signal generated by the power system&#39;s controller. On-board circuitry generates all of the timing and sequencing required to operate the switch cell properly. The gate driver includes two volt-second detectors to determine the optimal timing of modes  3  and  7 . One monitors the bus voltage to determine the saturation time of Lr during turn-on. The other monitors the energy recovery voltage to determine saturation time during flux reset. The gate driver includes additional, fixed timing circuitry to provide deadtime between S 1  and S 3  in mode 2 and overlapping of S 2  and S 3  in mode 5. The output stages of the gate driver increase the voltage and current levels needed to drive the power devices. All output stages are referenced to ground, except the output for S 1  which must be isolated or level shifted. 
     Switch Cell Testing 
     The power waveforms for the switch cell are shown in  FIG. 7  during turn-on (top) and turn-off (bottom).  FIG. 8  shows the power waveforms for the recovery circuitry. The turn-on sequence initiates at ˜100 ns. The inductor then saturates at ˜150 ns, causing the drain voltage to fall and current to rise. At ˜400 ns the inductor current is transferred into Cr and the recovery circuitry. At turn-off the main current redirects from the switch cell into the recovery circuitry. 
       FIG. 9  shows a comparison of switching energy vs. drain current between a single JFET (dashed) and the switch cell (solid) at 80 V (orange), 160 V (green), and 320 V (red). At 80 V the switch cell has minimal improvement and is actually less efficient at higher current levels. At 160 V the switch cell outperforms the single JFET at all current levels. At 320 V the switch cell achieves up to 4.3× reduction in switching loss compared to the single JFET. 
     From the foregoing, it will be seen that this invention well adapted to obtain all the ends and objects herein set forth, together with other advantages which are inherent to the structure. It will also be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims. Many possible embodiments may be made of the invention without departing from the scope thereof. Therefore, it is to be understood that all matter herein set forth or shown in the accompanying drawings is to be interpreted as illustrative and not in a limiting sense. 
     When interpreting the claims of this application, method claims may be recognized by the explicit use of the word ‘method’ in the preamble of the claims and the use of the ‘ing’ tense of the active word. Method claims should not be interpreted to have particular steps in a particular order unless the claim element specifically refers to a previous element, a previous action, or the result of a previous action. Apparatus claims may be recognized by the use of the word ‘apparatus’ in the preamble of the claim and should not be interpreted to have ‘means plus function language’ unless the word ‘means’ is specifically used in the claim element. The words ‘defining,’ having,′ or ‘including’ should be interpreted as open ended claim language that allows additional elements or structures. Finally, where the claims recite “a” or “a first” element of the equivalent thereof, such claims should be understood to include incorporation of one or more such elements, neither requiring nor excluding two or more such elements.