Abstract:
Non-volatile memory devices include an array of phase-changeable memory cells, which have first phase-changeable material patterns therein, and at least one phase-changeable fuse element. This phase-changeable fuse element includes a second phase-changeable material pattern therein with a higher crystallization temperature relative to the first phase-changeable material patterns in the array of phase-changeable memory cells. This higher crystallization temperature may be greater than about 300° C. According to additional embodiments of the present invention, the at least one phase-changeable fuse element includes a composite of the second phase-changeable material pattern and a third phase-changeable material pattern, which is formed of the same material at the first phase-changeable material patterns.

Description:
REFERENCE TO PRIORITY APPLICATION 
       [0001]    This U.S. non-provisional patent application claims priority to Korean Patent Application No. 10-2008-0071755, filed Jul. 23, 2008, the contents of which are hereby incorporated herein by reference. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to integrated circuit devices and, more particularly, to non-volatile memory devices and methods of forming same. 
       BACKGROUND 
       [0003]    With the advance in electronic industries such as mobile communications and computers, there is a demand for semiconductor devices having characteristics such as fast read/write operations, nonvolatility, and a low operation voltage. However, currently used memory devices such as SRAM devices, DRAM devices, and flash memory devices cannot meet all the characteristics. Since a unit cell of a DRAM device includes one capacitor and one transistor configured to control the capacitor, the DRAM device has a larger unit cell area than a NAND flash memory device. A DRAM device is a volatile memory device requiring a refresh operation because data is stored in a capacitor of the DRAM device. An SRAM device is another volatile memory device having a high operation speed. A unit cell of an SRAM device typically includes six transistors. Therefore, the SRAM device suffers from the disadvantage that the unit cell occupies a considerably large area. Among current memory devices, flash memory devices (especially, NAND flash memory devices) can provide the highest integration density while being nonvolatile memory devices. Nonetheless, it is well known that these flash memory devices have the drawback of low operation speed. 
         [0004]    In this regard, recent studies have focused on memory devices which can execute read/write operations at high speed, have nonvolatile characteristics, need not execute a refresh operation, and have a low operation voltage. Phase change random access memory (PRAM) devices are attractive candidates as nonvolatile memory devices which are capable of meeting the above technical demands. Since PRAM devices can update information approximately 10 13  times or more, they have a long life and are able to execute a high-speed operation of approximately 30 nanoseconds. 
         [0005]    A phase change pattern of a PRAM device can exhibit at least two distinguishable states, i.e., a crystalline state and an amorphous state and at least one intermediate state therebetween. Thus, the phase change pattern can be used as a memory element. The amorphous state has a higher resistivity than the crystalline state, and the intermediate state has a resistivity between those of the amorphous and crystalline states. 
       SUMMARY 
       [0006]    Non-volatile memory devices according to some embodiments of the present invention include an array of phase-changeable memory cells, which have first phase-changeable material patterns therein, and at least one phase-changeable fuse element. This phase-changeable fuse element includes a second phase-changeable material pattern therein with a higher crystallization temperature relative to the first phase-changeable material patterns in the array of phase-changeable memory cells. This higher crystallization temperature may be greater than about 300° C. According to additional embodiments of the present invention, the at least one phase-changeable fuse element includes a composite of the second phase-changeable material pattern and a third phase-changeable material pattern, which is formed of the same material at the first phase-changeable material patterns. In this composite, the second phase-changeable material pattern is in contact with the third phase-changeable material pattern. In particular, the second phase-changeable material pattern may have a U-shaped cross-section with a recess therein and this recess may be filled with the third phase-changeable material pattern. 
         [0007]    Additional embodiments of the invention include an integrated circuit device having a fuse element therein. This fuse element may be formed as a phase-changeable fuse element containing at least two different phase-changeable materials having unequal crystallization temperatures. In particular, the fuse element may be formed so that a first one of the at least two different phase-changeable materials has a recess therein that is at least partially filed by a second one of the at least two different phase-changeable materials having a lower crystallization temperature relative to the first one of the at least two different phase-changeable materials. The integrated circuit device may also include an array of phase-changeable memory cells that are devoid of one of the at least two different phase-changeable memory cells having a higher crystallization temperature. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIGS. 1 through 5  are cross-sectional views of memory devices according to embodiments of the present invention, respectively. 
           [0009]      FIGS. 6A through 6D  are cross-sectional views illustrating a method of forming a memory device according to an embodiment of the present invention. 
           [0010]      FIGS. 7A through 7F  are cross-sectional views illustrating a method of forming a memory device according to another embodiment of the present invention. 
           [0011]      FIGS. 8A through 8E  are cross-sectional views illustrating a method of forming a memory device according to yet another embodiment of the present invention. 
           [0012]      FIGS. 9A through 9E  are cross-sectional views illustrating a method of forming a memory device according to further another embodiment of the present invention. 
           [0013]      FIGS. 10A and 10B  are cross-sectional views illustrating a method of forming a memory device according to still another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0014]    PRAM devices may employ chalcogenide-based materials. As integration density of PRAM devices continues to increase, an error occurrence frequency may increase. The PRAM devices may adopt a redundancy structure to overcome yield reduction resulting from the error occurrence. Conventionally, a fuse element may be used in adopting the redundancy structure. The fuse element may be formed by a physical cutting process using laser or an electrical cutting process using current. In the physical cutting process, an area of a fuse box and processing steps may increase with increase of integration density. Fuse phase change elements according to embodiments of the present invention may be used in a fuse element. The fuse phase change elements may be programmed and repeatedly repaired even if error occurs after being packaged. A PRAM package process may include an infrared reflow step, which may be conducted at a temperature ranging from 220 to 270 degrees centigrade. For this reason, phase change of the fuse phase change element must not occur during the infrared reflow step. A cell phase change element and the fuse phase change element may be different in temperature characteristic. A phase change pattern of the cell phase change element may be formed of germanium-antimony-tellurium (GeSbTe or GST). A phase change pattern of the fuse phase change element may be formed of indium-antimony-tellurium (InSbTe) which is higher than the GST. 
         [0015]    The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like numbers refer to like elements throughout. 
         [0016]      FIG. 1  is a cross-sectional view of an electric device according to an embodiment of the present invention. 
         [0017]    Referring to  FIG. 1 , a substrate  100  may include a cell region A and a fuse region B. A fuse phase change element  10   f  may be disposed at the fuse region B, and a cell phase change element  10   c  may be disposed at the cell region A. The fuse phase change element  10   f  may include a fuse bottom interconnection  112   f  disposed at the fuse region B, a fuse phase change pattern  130   f  disposed on the fuse bottom interconnection  112   f,  and a fuse top interconnection  160   f  disposed on the fuse phase change pattern  130   f.  The cell phase change element  10   c  may include a cell bottom interconnection  112   c  disposed at the cell region A, a cell phase change pattern  130   c  disposed on the cell bottom interconnection  112   c,  and a cell top interconnection  160   c  disposed on the cell phase change pattern  130   c.  A crystallization temperature of the fuse phase change pattern  130   f  may be higher than that of the cell phase change patter  130   c.    
         [0018]    The substrate  100  may be a semiconductor substrate or a dielectric substrate and include at least one selected from the group consisting of a silicon substrate, a germanium substrate, and a silicon-on-insulator (SOI) substrate. The substrate  100  may include a cell region A and a fuse region B. The substrate  100  may include a bottom structure (not shown), which may include a diode or a transistor. A bottom interlayer dielectric  110  may be disposed on the substrate  100  and made of silicon oxide. Bottom interconnections  112   c  and  112   f  may be disposed in bottom contact holes  114   c  and  114   f  penetrating the bottom interlayer dielectric  110 , respectively. The bottom interconnections  112   c  and  112   f  may include a conductive pad. The bottom interconnections  112   c  and  112   f  may include at least one selected from the group consisting of metal, metal compound, and doped semiconductor. The bottom interconnections  112   c  and  112   f  may include a cell bottom interconnection  112   c  disposed at the cell region A and a fuse bottom interconnection  112   f  disposed at the fuse region B, respectively. The bottom interconnections  112   c  and  112   f  may be electrically connected to the bottom structure. Top surfaces of the bottom interconnections  112   c  and  112   f  may have the same height as a top surface of the bottom interlayer dielectric  110 . 
         [0019]    An intermediate interlayer dielectric  120  may be disposed on the bottom interconnections  112   c  and  112   f  and/or the bottom interlayer dielectric  110 . Intermediate contact holes  126   c  and  126   f  may be disposed through the intermediate interlayer dielectric  120  to expose the bottom interconnections  112   c  and  112   f,  respectively. The intermediate contact holes  126   c  and  126   f  may include a cell intermediate contact hole  126   c  formed at the cell region A and a fuse intermediate contact hole  126   f  formed at the fuse region. The intermediate dielectric  120  may be made of silicon oxide. 
         [0020]    Bottom electrode spacers  122   c  and  122   f  may be disposed on sidewalls of the intermediate contact holes  126   c  and  126   f,  respectively. The bottom electrode spacers  122   c  and  122   f  may include silicon nitride or silicon oxynitride. The bottom electrode spacers  122   c  and  122   f  may include a cell bottom electrode spacer  122   c  disposed at the cell region A and a fuse bottom electrode spacer  122   f  disposed at the fuse region B. A thermal conductivity of the bottom electrode spacers  122   c  and  122   f  may be lower than that of the intermediate interlayer dielectric  120 . 
         [0021]    Bottom electrodes  124   c  and  124   f  may be disposed in the intermediate contact holes  126   c  and  126   f,  respectively. The bottom electrodes  124   c  and  124   f  may be provided to heat the phase change patterns  130   c  and  130   f,  respectively. The bottom electrodes  124   c  and  124   f  may include a cell bottom electrode  124   c  disposed at the cell region A and a fuse bottom electrode  124   f  disposed at the fuse region B. The bottom electrodes  124   c  and  124   f  may include at least one selected from the group consisting of metal nitride, metal, metal oxynitride, silicide, and conductive carbon. Specifically, the bottom electrodes  124   c  and  124   f  may include at least one selected from the group consisting of Ti, Ta, Mo, W, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, TaSiN, TaAlN, TiW, TiSi, TaSi, TiON, TiAlON, WON, and TaON. A sectional area of the respective bottom electrodes  124   c  and  124   f  may be smaller than that of the respective phase change patterns  130   c  and  130   f.  If the bottom electrodes  124   c  and  124   f  decrease in size, a contact area may be reduced to increase contact resistance. Therefore, in case the contact resistance is high, the bottom electrodes  124   c  and  124   f  may rise to a high temperature even with a low current. The cell bottom interconnection  112   c  may be electrically connected to the cell bottom electrode  124   c,  and the fuse bottom interconnection  112   f  may be electrically connected to the cell bottom electrode  124   f.    
         [0022]    The phase change patterns  130   c  and  130   f  may be disposed on the bottom electrodes  124   c  and  124   f,  respectively. The phase change patterns  130   c  and  130   f  may include a cell phase change pattern  130   c  disposed at the cell region A and a fuse phase change pattern  130   f  disposed at the fuse region B. The phase change pattern  130   c  and  130   f  may extend in parallel with the top interconnections  160   c  and  160   f.    
         [0023]    In an alternative embodiment, the phase change patterns  130   c  and  130   f  may be island-shaped, contact plug-shaped or line-shaped patterns. The phase change patterns  130   c  and  130   c  may have various shapes. 
         [0024]    The cell phase change pattern  130   c  of the cell region A may include at least one selected from the group consisting of Ge—Sb—Te, Sb—Te, As—Sb—Te, and Sb—Se. Specifically, the cell phase change pattern  130   c  may be made of Ge 2 Sb 2 Te 5 . The cell phase change pattern  130   c  may include one selected from the group consisting of As—Sb—Te-metal compound, As—Ge—Sb—Te-metal compound, metal-Sb—Te-metal compound,  5 A group element-Sb—Te-metal compound,  6 A group element-Sb—Te-metal compound,  5 A group element-Sb—Se-metal compound, and  6 A group element-Sb—Se-metal compound. There may be various ratios of the compounds. Specifically, the  5 A group element may be nitrogen (N) or phosphorous (P), and the  6 A group element may be oxygen (O) or sulfur (S). 
         [0025]    The fuse phase change pattern  130   f  of the fuse region B may include at least one selected from the group consisting of In—Sb—Te,  5 A group element-In—Sb—Te compound, and  6 A group element-In—Sb—Te compound. A crystallization temperature of the fuse phase change pattern  130   f  may be higher than that of the cell phase change pattern  130   c.  The fuse phase change pattern  130   f  may include a first fuse phase change pattern  132   f  and a second fuse phase change pattern  134   f.  A crystallization temperature of the first fuse phase change pattern  132   f  may be higher than that of the second fuse phase change pattern  134   f.  The crystallization temperature of the first fuse phase change pattern  132   f  may be at least 300 degrees centigrade. The fuse phase change pattern  130   f  may use a material of a high crystallization temperature, and the cell phase change pattern  130   c  may use a material having excellent characteristics as a memory device. The second fuse phase change pattern  134   f  may be made of the same material as the cell phase change pattern  130   c.  Side surfaces of the first and second fuse phase change patterns  132   f  and  134   f  may be aligned to each other. The first fuse phase change pattern  132   f  may be heated by the fuse bottom electrode  124   f  to result in phase change thereof. A resistance state of the first fuse phase change pattern  132   f  may be unchanged due to an infrared reflow process. The fuse phase change element may be used as a one-time program cell. 
         [0026]    Top electrodes  136   c  and  136   f  may be disposed on the cell phase change pattern  130   c  and the fuse phase change pattern  130   f,  respectively. The top electrodes  136   c  and  136   f  may include a cell top electrode  136   c  disposed at the cell region A and a fuse top electrode  136   f  disposed t the fuse region B. The top electrode  136   c  and  136   f  may include at least one selected from the group consisting of metal, metal nitride, and metal oxynitride. Specifically, the top electrodes  136   c  and  136   f  may include at least one selected from the group consisting of Ti, Ta, Mo, W, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, TaSiN, TaAlN, TiW, TiSi, TaSi, TiON, TiAlON, WON, and TaON. Side surfaces of the top electrodes  136   c  and  136   f  may be aligned to those of the phase change patterns  130   c  and  130   f.    
         [0027]    Hard mask patterns  138   c  and  138   f  may be formed on the top electrodes  136   c  and  136   f,  respectively. The hard mask patterns  138   c  and  138   f  may include a cell hard mask pattern  138   c  formed at the cell region A and a fuse hard mask pattern  138   f  formed at the fuse region B. The hard mask patterns  138   c  and  138   f  may include one or both of silicon nitride and silicon oxynitride. Side surfaces of the cell phase change pattern  130   c,  the cell top electrode  136   c,  and the cell hard mask pattern  138   c  may be aligned to one another. Side surfaces of the fuse phase change pattern  130   f,  the fuse top electrode  136   f,  and the fuse hard mask pattern  138   f  may be aligned to one another. The hard mask patterns  138   c  and the  138   f  may be used as an etch stopper. The hard mask patterns  138   c  and  138   f  may act as at least one selected from the group consisting of a diffusion barrier layer, an oxidation barrier layer, and a heat transfer barrier layer. 
         [0028]    A protection layer  142  may be disposed to conformally cover the top surfaces of the hard mask patterns  138   c  and  138   f,  the top electrodes  136   c  and  136   f,  the phase change patterns  130   c  and  130   f,  the side surfaces of the top electrodes  136   c  and  136   f,  and the top surface of the intermediate interlayer dielectric  120 . The protection layer  142  may prevent the material of the phase change patterns  130   c  and  130   f  from diffusing out or reacting to another material. The protection layer  142  may be made of silicon nitride. 
         [0029]    A top interlayer dielectric  140  may be disposed on the protection layer  142 . The top interlayer dielectric  140  may be made of silicon oxide. A top surface of the top interlayer dielectric  140  may be higher than that of the hard mask patterns  138   c  and  138   f.  The top surface of the top interlayer dielectric  140  may be planarized. Top contact holes  156   c  and  156   f  may be formed through the top interlayer dielectric  140 , the protection layer  142 , and the hard mask patterns  138   c  and  138   f  to expose the top electrodes  136   c  and  136   f.  The top contact holes  156   c  and  156   f  may include a cell top contact hole  156   c  formed at the cell region A and a fuse top contact hole  156   f  formed at the fuse region B. Top contact plugs  150   c  and  150   f  may be disposed in the top contact holes  156   c  and  156   f,  respectively. The top contact plug  150   c  and  150   f  may include a cell top contact plug  150   c  filling the cell top contact hole  156   c  and a fuse top contact plug  150   f  filling the fuse top contact hole  156   f.  The top contact plugs  150   c  and  150   f  may be made of a conductive material. The top contact plugs  150   c  and  150   f  may include, for example, tungsten (W). The top contact plug  150   c  may have a multi-layer structure including a barrier material  152   c  and a conductive material  154   c  which are sequentially stacked, and the top contact plug  150   f  may have a multi-layer structure including a barrier material  152   f  and a conductive material  154   f  which are sequentially stacked. 
         [0030]    Top interconnections  160   c  and  160   f  may be disposed on the top interlayer dielectric  140 . The top interconnections  160   c  and  160   f  may be electrically connected to the top contact plugs  150   c  and  150   f,  respectively. The top interconnections  160   c  and  160   f  may include at least one selected from the group consisting of metal, metal compound, and doped semiconductor. The top interconnections  160   c  and  160   f  may have a multi-layer structure including a barrier layer  162 , a conductive layer  164 , and a barrier layer  166  which are stacked in the order named. The top interconnections  160   c  and  160   f  may include a cell top interconnection  160   c  disposed at the cell region A and a fuse top interconnection  160   f  disposed at the fuse region B. The fuse top interconnection  160   f  may be electrically connected to a fuse controller (not shown). 
         [0031]      FIG. 2  is a cross-sectional view of an electric device according to another embodiment of the present invention. 
         [0032]    Referring to  FIG. 2 , a substrate  200  may include a cell region A and a fuse region B. A fuse phase change element  10   f  may be disposed at the fuse region A, and a cell phase change element  10   c  may be disposed at the cell region A. The fuse phase change element  10   f  may include a fuse bottom interconnection  212   f  disposed at the fuse region A, a fuse phase change pattern  230   f  disposed on the fuse bottom interconnection  230   f,  and a fuse top interconnection  260   f  disposed on the fuse phase change pattern  230   f.  The cell phase change element  10   c  may include a cell bottom interconnection  212   c  disposed at the cell region A, a cell phase change pattern  230   c  disposed on the cell bottom interconnection  212   c,  and a cell top interconnection  260   c  disposed on the cell phase change pattern  230   c.  A crystallization temperature of the fuse phase change pattern  230   f  may be higher than that of the cell phase change pattern  230   c.  A cell bottom electrode  224   c  may be disposed between the cell phase change pattern  230   c  and the cell bottom interconnection  214   c,  and a fuse bottom electrode  224   f  may be disposed between the fuse phase change pattern  230   f  and the fuse bottom interconnection  214   f.    
         [0033]    The substrate  200  may a semiconductor substrate or a dielectric substrate and may include at least one selected from the group consisting of a silicon substrate, a germanium substrate, and a silicon-on-insulator (SOI) substrate. The substrate  100  may include a cell region A and a fuse region B. The substrate  100  may include a bottom structure (not shown), which may include a diode or a transistor. 
         [0034]    A bottom interlayer dielectric  210  may be disposed on the substrate  200 . The bottom interlayer dielectric  210  may be made of silicon oxide. A top surface of the bottom interlayer dielectric  210  may be planarized. Bottom interconnections  212   c  and  212   f  may be disposed in bottom contact holes  214   c  and  214   f  penetrating the bottom interlayer dielectric  210 , respectively. The bottom interconnections  212   c  and  212   f  may include a conductive pad. The bottom interconnections  212   c  and  212   f  may include at least one selected from the group consisting of metal, metal compound, and doped semiconductor. The bottom interconnections  212   c  and  212   f  may include a cell bottom interconnection  212   c  disposed at the cell region A and a fuse bottom interconnection  212   f  disposed at the fuse region B. The top surface of the bottom interlayer dielectric  210  may have the same height as that of the bottom interconnections  212   c  and  212   f.    
         [0035]    An intermediate interlayer dielectric  220  may be disposed on the bottom interconnections  212   c  and  212   f  and/or the bottom interlayer dielectric  210 . The intermediate interlayer dielectric  220  may be made of silicon oxide. Intermediate contact holes  226   c  and  226   f  may be disposed trough the intermediate interlayer dielectric  220  to expose the bottom interconnections  212   c  and  212   f.  The intermediate contact holes  226   c  and  226   f  may include a cell intermediate contact hole  226   c  formed at the cell region A and a fuse intermediate contact hole  226   f  formed at the fuse region B. The intermediate interlayer dielectric  220  may be made of silicon oxide. Bottom electrode spacers  222   c  and  222   c  may be disposed on sidewalls of the intermediate contact holes  226   c  and  226   f,  respectively. The bottom electrode spacer  222   c  and  222   f  may include silicon nitride or silicon oxynitride. The bottom electrode spacers  222   c  and  222   f  may include a cell bottom electrode spacer  222   c  disposed at the cell region A and a fuse bottom electrode spacer  222   f  disposed at the fuse region B. Bottom electrodes  224   c  and  224   f  may be disposed in the intermediate contact holes  226   c  and  226   f,  respectively. The bottom electrodes  224   c  and  224   f  may be provided to heat the phase change patterns  230   c  and  230   f,  respectively. The bottom electrodes  224   c  and  224   f  may include a cell bottom electrode  224   c  disposed at the cell region A and a fuse bottom electrode  224   f  disposed at the fuse region B. Top surfaces of the bottom electrodes  224   c  and  224   f  may have same height as a top surface of the intermediate interlayer dielectric  220 . The bottom electrodes  224   c  and  224   f  may include at least one selected from the group consisting of metal nitride, metal, metal oxynitride, silicide, and conductive carbon. Specifically, the bottom electrodes  224   c  and  224   f  may include at least one selected from the group consisting of Ti, Ta, Mo, W, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, TaSiN, TaAlN, TiW, TiSi, TaSi, TiON, TiAlON, WON, and TaON. A sectional area of the respective bottom electrodes  124   c  and  124   f  may be smaller than that of the respective phase change patterns  130   c  and  130   f.  A thermal conductivity of the bottom electrode spacers  222   c  and  222   f  may be lower than that of the intermediate interlayer dielectric  220 . 
         [0036]    A top interlayer dielectric  240  may be disposed on the intermediate interlayer dielectric  220  and made of silicon oxide. Phase change contact holes  236   c  and  236   f  may be formed through the top interlayer dielectric  240  to expose the bottom electrodes  224   c  and  224   f,  respectively. The phase change contact holes  236   c  and  236   f  may include a cell phase change contact hole  236   c  formed at the cell region A and a fuse phase change contact hole  236   f  formed at the fuse region B. Phase change spacers  231   c  and  231   f  may be formed on sidewalls of the phase change contact holes  236   c  and  236   f,  respectively. The phase change spacers  231   c  and  231   f  may include a silicon nitride layer or a silicon oxynitride layer. A thermal conductivity of the phase change spacers  231   c  and  231   f  may be lower than that of the top interlayer dielectric  240 . The phase change spacers  231   c  and  231   f  may act as a diffusion barrier layer. The phase change spacers  231   c  and  231   f  may include a cell phase change spacer  231   c  disposed at the cell region A and a fuse phase change spacer  231   f  disposed at the fuse region B. The phase change patterns  230   c  and  230   f  may be disposed in the phase change contact holes  236   c  and  236   f,  respectively. The phase change patterns  230   c  and  230   f  may include a cell phase change pattern  230   c  disposed at the cell region A and a fuse phase change pattern  230   f  disposed at the fuse region B. 
         [0037]    According to an alternative embodiment, the phase change patterns  230   c  and  230   f  are not limited to contact plug-shaped patterns. The phase change patterns  230   c  and  230   f  may have a line shape. The phase change patterns  230   c  and  230   f  may extend in parallel with the top interconnections  260   c  and  260   c.    
         [0038]    The cell phase change pattern  230   c  of the cell region A may include at least one selected from the group consisting of Ge—Sb—Te, Sb—Te, As—Sb—Te, and Sb—Se. Specifically, the cell phase change pattern  230   c  may be made of Ge 2 Sb 2 Te 5 . The cell phase change pattern  130   c  may include one selected from the group consisting of As—Sb—Te-metal compound, As—Ge—Sb—Te-metal compound, metal-Sb—Te-metal compound,  5 A group element-Sb—Te-metal compound,  6 A group element-Sb—Te-metal compound,  5 A group element-Sb—Se-metal compound, and  6 A group element-Sb—Se-metal compound. There may be various ratios of the compounds. Specifically, the  5 A group element may be nitrogen (N) or phosphorous (P), and the  6 A group element may be oxygen (O) or sulfur (S). The cell phase change pattern  230   c  may have the shape of inverse truncated cone. 
         [0039]    The fuse phase change pattern  230   f  may include a first fuse phase change pattern  232   f  and a second fuse phase change pattern  234   f.  A crystallization temperature of the first fuse phase change pattern  232   f  may be higher than that of the second fuse phase change pattern  234   f.  The crystallization temperature of the first fuse phase change pattern  232   f  may be at least 300 degrees centigrade. The fuse phase change pattern  130   f  may use a material of a high crystallization temperature, and the cell phase change pattern  130   c  may use a material having excellent characteristics as a memory device. The first fuse phase change pattern  232   f  may be a pot-shaped pattern and be in contact with a side surface of the fuse phase change pattern  232   f.  A bottom surface of the first fuse phase change pattern  232   f  may be in contact with a top surface of the fuse bottom electrode  224   f.  The second fuse phase change pattern  234   f  may be disposed to fill the inside of the first fuse phase change pattern  232   f  and have the shape of inverse truncated cone. The top surface of the first fuse phase change pattern  232   f  may have the same height as that of the second fuse phase change pattern  234   f.    
         [0040]    The first fuse phase change pattern  232   f  may include at least one selected from the group consisting of In—Sb—Te,  5 A group element-In—Sb—Te compound, and  6 A group element-In—Sb—Te compound. A crystallization temperature of the first fuse phase change pattern  232   f  may be higher than that of the cell phase change pattern  230   c.  The second fuse phase change pattern  234   f  may be made of the same material as the cell phase change pattern  230   c.  Current flowing to the fuse bottom electrode  224   f  may result in phase change of the first fuse phase change pattern  232   f.  A resistance state of the first fuse phase change pattern  232   f  may be unchanged due to an infrared reflow process. The fuse phase change element may be used as a one-time program cell. 
         [0041]    Top interconnections  260   c  and  260   f  may be disposed on the phase change pattern  230   c  and  230   f,  respectively. The top interconnections  260   c  and  260   f  may include a cell top interconnection  260   c  disposed at the cell region A and a fuse top interconnection  260   f  disposed at the fuse region B. The top interconnections  260   c  and  260   f  may be electrically connected to the phase change patterns  230   c  and  230   f,  respectively. The top interconnections  260   c  and  260   f  may include at least one selected from the group consisting of metal, metal compound, and doped semiconductor. The cell top interconnection  260   c  may have a multi-layer structure including a diffusion barrier layer  262   c,  a metal layer  264   c,  and a diffusion barrier layer  266   c  which are sequentially stacked, and the fuse top interconnection  260   f  may have a multi-layer structure including a diffusion barrier layer  262   f,  a metal layer  264   f,  and a diffusion barrier layer  266   f  which are sequentially stacked. 
         [0042]      FIG. 3  is a cross-sectional view of an electric device according to yet another embodiment of the present invention. 
         [0043]    Referring to  FIG. 3 , the electric device has a similar structure to the electric device described in  FIG. 2 . Thus, duplicate explanations thereof may be omitted. A substrate  300  may include a cell region A and a fuse region B. A fuse phase change element  10   f  may be disposed at the fuse region B, and a cell phase change element  10   c  may be disposed at the cell region A. The fuse phase change element  10   f  may include a fuse bottom interconnection  312   f  disposed at the fuse region B, a fuse phase change pattern  330   f  disposed on the fuse bottom interconnection  312   f,  and a fuse top interconnection  360   f  disposed on the fuse change pattern  330   f.  The cell phase change element  10   c  may include a cell bottom interconnection  312   c  disposed at the cell region A, a cell phase change pattern  330   c  disposed on the cell bottom interconnection  312   c,  and a cell top interconnection  360   c  disposed on the cell phase change pattern  330   c.  A crystallization temperature of the fuse phase change pattern  330   f  may be higher than that of the cell phase change pattern  330   c.    
         [0044]    A bottom interlayer dielectric  310  may be disposed on the substrate  300 . The bottom interconnections  312   c  and  312   f  may be disposed in the bottom interlayer dielectric  310 . An intermediate interlayer dielectric  320  may be disposed on the bottom interlayer dielectric  310 . Bottom electrodes  324   c  and  324   f  may be disposed in the intermediate interlayer dielectric  320 . The bottom electrodes  324   c  and  324   f  may be electrically connected to the bottom interconnections  312   c  and  312   f,  respectively. The bottom electrodes  324   c  and  324   f  may include a cell bottom electrode  324   c  disposed at the cell region A and a fuse bottom electrode  324   f  disposed at the fuse region B. Bottom electrode spacers  322   c  and  322   f  may be disposed between the cell bottom electrode  324   c  and the intermediate interlayer dielectric  320  and between the fuse bottom electrode  324   f  and the intermediate interlayer dielectric  320 , respectively. The bottom electrode spacers  322   c  and  322   f  may include a cell bottom electrode spacer  322   c  disposed at the cell region A and a fuse bottom electrode spacer  322   f  disposed at the fuse region B. 
         [0045]    A top interlayer dielectric  340  may be disposed on the intermediate interlayer dielectric  320 . Phase change patterns  330   c  and  330   f  may be disposed in the top interlayer dielectric  340 . The phase change patterns  330   c  and  330   f  may include a cell phase change pattern  330   c  disposed at the cell region A and a fuse phase change pattern  330   f  disposed at the fuse region B. 
         [0046]    The cell phase change pattern  330   c  may be a pot-shaped pattern. The inside of the cell phase change pattern  330  may be filled with a cell top electrode  336   c.  A height of the cell phase change pattern  330   c  may have the same height as that of the cell top electrode  336   c.    
         [0047]    The fuse phase change pattern  330   f  may include a first fuse phase change pattern  332   f  and a second fuse phase pattern  334   f.  The pot-shaped second phase change pattern  332   f  may be disposed in the pot-shaped first fuse phase change pattern  332   f.  A fuse top electrode  336   f  may be disposed in the pot-shaped second fuse phase change pattern  334   f.  A top surface of the fuse phase change pattern  330   f  may have same height as that of the fuse top electrode  336   f.  A crystallization temperature of the first fuse phase change pattern  332   f  may be higher than that of the second fuse phase change pattern  334   f.  The second fuse phase change pattern  334   f  may be made of the same material as the cell phase change pattern  330   c.    
         [0048]    According to an alternative embodiment, the phase change patterns  330   c  and  330   f  may extend in a direction of the top interconnections  360   c  and  360   f.  There may be various shapes of the phase change patterns  330   c  and  330   f.    
         [0049]    The top interconnections  360   c  and  360   f  may be disposed on the top electrodes  336   c  and  336   f  and the phase change patterns  330   c  and  330   f.  The top interconnections  360   c  and  360   f  may include a cell top interconnection  360   c  disposed at the cell region A and a fuse top interconnection  360   f  disposed at the fuse region B. The cell top interconnection  360   c  may have a multi-layer structure including a diffusion barrier layer  362   c,  a metal layer  364   c,  and a diffusion barrier layer  366   c  which are sequentially stacked, and the fuse top interconnection  360   f  may have a multi-layer structure including a diffusion barrier layer  362   f,  a metal layer  364   f,  and a diffusion barrier layer  366   f  which are sequentially stacked. 
         [0050]      FIG. 4  is a cross-sectional view of an electric device according to further another embodiment of the present invention. 
         [0051]    Referring to  FIG. 4 , the electric device has a similar structure to the electric device described in  FIG. 3 . Thus, duplicate explanations thereof may be omitted. A substrate  400  may include a cell region A and a fuse region B. A fuse phase change element  10   f  may be disposed at the fuse region B, and a cell phase change element  10   c  may be disposed at the cell region A. The fuse phase change element  10   f  may include a fuse bottom interconnection  412   f  disposed at the fuse region B, a fuse phase change pattern  432   f  disposed on the fuse bottom interconnection  412   f,  and a fuse top interconnection  460   f  disposed on the fuse phase change pattern  432   f.  The cell phase change element  10   c  may include a cell bottom interconnection  412   c  disposed at the cell region A, a cell phase change pattern  434   c  disposed on the cell bottom interconnection  412   c,  and a cell top interconnection  460   c  disposed on the cell phase change pattern  434   c.  A crystallization temperature of the fuse phase change pattern  432   f  may be higher than that of the cell phase change pattern  434   c.    
         [0052]    A bottom interlayer dielectric  410  may be disposed on the substrate  400 . The bottom interconnections  412   c  and  412   f  may be disposed in the bottom interlayer dielectric  410 . An intermediate interlayer dielectric  420  may be disposed on the bottom interlayer dielectric  410 . 
         [0053]    Phase change patterns  430   c  and  430   f  may be disposed in the intermediate interlayer dielectric  430 . A cell phase change spacer  432   c  may be disposed on a sidewall of the cell phase change pattern  430   c,  and a fuse phase change spacer  432   f  may be disposed on a sidewall of the fuse phase change pattern  430   f.  Phase change of the phase change patterns  430   c  and  430   f  may be made not by heat transferred to the phase change patterns  430   c  and  430   f  from a separate heater but by current flowing to the phase change patterns  430   c  and  430   f.  The cell phase change pattern  430   c  may include at least one selected from the group consisting of Ge—Sb—Te, Sb—Te, As—Sb—Te, and Sb—Se. The fuse phase change pattern  430   f  may include one selected from the group consisting of In—Sb—Te,  5 A group element-In—Sb—Te compound, and  6 A group element-In—Sb—Te compound. 
         [0054]    The top interconnections  460   c  and  460   f  may include a cell top interconnection  460   c  disposed at the cell region A and a fuse top interconnection  460   f  disposed at the fuse region B. The cell top interconnection  460   c  may have a multi-layer structure including a diffusion barrier layer  462   c,  a metal layer  464   c,  and a diffusion barrier layer  466   c  which are sequentially stacked, and the fuse top interconnection  460   f  may have a multi-layer structure including a diffusion barrier layer  462   f,  a metal layer  464   f,  and a diffusion barrier layer  466   f  which are sequentially stacked. 
         [0055]      FIG. 5  is a cross-sectional view of an electric device according to further another embodiment of the present invention. 
         [0056]    Referring to  FIG. 5 , the electric device has a similar structure to the electric device described in  FIG. 2 . A substrate  500  may include a cell region A and a fuse region B. A fuse phase change element  10   f  may be disposed at the fuse region B, and a cell phase change element  10   c  may be disposed at the cell region A. The fuse phase change element  10   f  may include a fuse bottom interconnection  512   f  disposed at the fuse region B, a fuse bottom electrode  524   f  disposed on the fuse bottom interconnection  512   f,  a fuse phase change pattern  530   f  disposed on the fuse bottom electrode  524   f,  and a fuse top interconnection  560   f  disposed on the fuse phase change pattern  530   f.  The cell phase change element  10   c  may include a cell bottom interconnection  512   c  disposed at the cell region A, a cell bottom electrode  524   c  disposed on the cell bottom interconnection  512   c,  a cell phase change pattern  530   c  disposed on the cell bottom electrode  524   c,  and a cell top interconnection  560   c  disposed on the cell phase change pattern  530   f.  A crystallization temperature of the fuse phase change pattern  530   f  may be higher than that of the cell phase change pattern  530   c.    
         [0057]    A bottom interlayer dielectric  510  may be disposed on the substrate  500 . Bottom interconnections  512   c  and  512   f  may be disposed in the bottom interlayer dielectric  510 . The bottom interconnections  512   c  and  512   f  may include a cell bottom interconnection  512   c  disposed at the cell region A and a fuse bottom interconnection  512   f  disposed at the fuse region B. 
         [0058]    A top interlayer dielectric  540  may be disposed on the bottom interlayer dielectric  510 . 
         [0059]    Bottom electrodes  524   c  and  524   f  and the phase change patterns  530   c  and  530   f  may be sequentially stacked in the top interlayer dielectric  540 . The bottom electrodes  524   c  and  524   f  may include a cell bottom electrode  524   c  disposed at the cell region A and a fuse bottom electrode  524   f  disposed at the fuse region B. The phase change patterns  530   c  and  530   f  may include a cell phase change pattern  530   c  disposed at the cell region A and a fuse phase change pattern  530   f  disposed at the fuse region B. 
         [0060]    A cell phase change spacer  531   c  may be disposed on sidewalls of the cell phase change pattern  530   c  and the cell bottom electrode  524   c,  and a fuse phase change spacer  531   f  may be disposed on sidewalls of the phase change patterns  530   f  and the fuse bottom electrode  524   c.  Heat generated from the bottom electrode  524   c  and  524   f  is transferred to the phase change patterns  530   c  and  530   f,  leading to phase change of the phase change patterns  530   c  and  530   f.    
         [0061]    The top interconnections may include a cell top interconnection  560   c  disposed at the cell region A and a fuse top interconnection  560   f  disposed at the fuse region B. The cell top interconnection  560   c  may has a multi-layer structure including a diffusion barrier layer  562   c,  a metal layer  564   c,  and a diffusion barrier layer  566   c  which are sequentially stacked, and the fuse top interconnection  560   f  may have a multi-layer structure including a diffusion barrier layer  562   f,  a metal layer  564   f,  and a diffusion barrier layer  566   f  which are sequentially stacked. 
         [0062]      FIGS. 6A through 6D  are cross-sectional views illustrating a method of forming an electric device according to an embodiment of the present invention. 
         [0063]    Referring to  FIG. 6A , a substrate  100  may include a fuse region A and a cell region B. A bottom interlayer dielectric  110  is formed on the substrate  100 . The bottom interlayer dielectric  110  may be formed by means of chemical vapor deposition (CVD) or spin coating. The bottom interlayer dielectric  110  may be formed of silicon oxide. A top surface of the bottom interlayer dielectric  110  may be planarized. The bottom interlayer dielectric  110  may be patterned to form bottom contact holes  114   c  and  114   f,  which may include a cell bottom contact hole  114   c  formed at the cell region A and a fuse bottom contact hole  114   f  formed at the fuse region B. The cell contact hole  114   c  and the fuse contact hole  114   f  may be formed at the same time. A bottom interconnection layer (not shown) may be deposited to cover the bottom contact holes  114   c  and  114   f  and the bottom interlayer dielectric  110 . The substrate  100  including the deposited bottom interconnection layer may be planarized to form bottom interconnections  112   c  and  112   f,  which may include a cell bottom interconnection  112   c  formed at the cell region A and a fuse bottom interconnection  112   f  formed at the fuse region B. The planarization of the substrate  100  including the deposited bottom interconnection layer may be done by means of a chemical mechanical polishing (CMP) process or an etch-back process. 
         [0064]    Referring to  FIG. 6B , a first intermediate interlayer dielectric  120  and a second intermediate interlayer dielectric  122  may be sequentially stacked on the bottom interconnections  114   f  and  114   c  and the bottom interlayer dielectric  110 . The first intermediate interlayer dielectric  120  may be formed of silicon oxide, and the second intermediate interlayer dielectric  122  may be formed of silicon nitride or silicon oxynitride. By patterning the second and first intermediate interlayer dielectrics  122  and  120 , intermediate contact holes  126   c  and  126   f  may be formed to expose the bottom interconnections  112   c  and  112   f,  respectively. The intermediate interlayer contact holes  126   c  and  126   f  may include a cell intermediate contact hole  126   c  formed at the cell region A and a fuse intermediate contact hole  126   f  formed at the fuse region B. 
         [0065]    Referring to  FIG. 6C , a bottom electrode spacer layer (not shown) may be conformally formed on the intermediate contact holes  126   c  and  126   f  and the second intermediate interlayer dielectric  122 . The bottom electrode spacer layer may be formed of silicon nitride. The bottom electrode spacer layer may be anisotropically etched to form bottom electrode spacers  122   c  and  122   f  at sidewalls of the intermediate contact holes  126   c  and  126   f.  The bottom electrode spacers  122   c  and  122   f  may include a cell bottom electrode spacer  122   c  formed at the cell region A and a fuse bottom electrode spacer  122   f  formed at the fuse region B. 
         [0066]    Referring to  FIG. 6D , a bottom electrode layer (not shown) may be deposited to fill the intermediate contact holes  126   c  and  126   f.  The substrate  100  may be planarized down to a top surface of the first intermediate interlayer dielectric  120  to form bottom electrodes  124   c  and  124   f,  which may include a cell bottom electrode  124   c  formed at the cell region A and a fuse bottom electrode  124   f  formed at the fuse region B. Top surfaces of the bottom electrode spacers  122   c  and  122   f  may have same height as those of the bottom electrodes  124   c  and  124   f.    
         [0067]    Returning to  FIG. 1 , a first phase change layer (not shown) is deposited on the substrate  100 . The first phase change layer at the cell region A is patterned to be removed. A second phase change layer (not shown), a top electrode layer (not shown), and a hard mask layer (not shown) may be sequentially stacked. The hard mask layer, the top electrode layer, and the second phase change layer at the cell region A may be successively patterned to form a cell hard mask pattern  138   c,  a cell top electrode  136   c,  and a cell phase change pattern  130   c.  The hard mask layer, the top electrode layer, and the second phase change layer at the fuse region B may be successively patterned to form a fuse hard mask pattern  138   f,  a fuse top electrode  136   f,  and a fuse phase change pattern  130   f.  The fuse phase change pattern  130   f  may include a first fuse phase change pattern  132   f  and a second fuse phase change pattern  134   f.    
         [0068]    A protection layer  142  may be conformally formed on the hard mask patterns  138   c  and  138   f  and the first intermediate interlayer dielectric  120 . The protection layer  142  may be made of silicon nitride. A top interlayer dielectric  140  may be formed on the substrate  100  where the protection layer  142  is formed. A top surface of the top interlayer dielectric  140  may be planarized and may be higher than top surfaces of the hard mask patterns  138   c  and  138   f.  The top interlayer dielectric  140  may be patterned down to top surfaces of the top electrodes  136   c  and  136   f  to form top contact holes  156   c  and  156   f,  which may include a cell top contact hole  156   c  formed at the cell region A and a fuse top contact hole  156   f  formed at the fuse region B. A conductive layer (not shown) may be formed on the top contact holes  156   c  and  156   f  and the top interlayer dielectric  140 . The conductive layer may be formed to fill the top contact holes  156   c  and  156   f.  The substrate  100  including the deposited conductive layer may be planarized to form top contact plugs  150   c  and  150   f,  which may include a cell top contact plug  150   c  formed at the cell region A and a fuse top contact hole  150   f  formed at the fuse region B. The cell top contact plug  150   c  may have a multi-layer structure including a diffusion barrier layer  154   c  and a conductive layer  152   c  which are sequentially stacked, and the fuse top contact plug  150   f  may have a multi-layer structure including a diffusion barrier layer  154   f  and a conductive layer  152   f  which are sequentially stacked. 
         [0069]    A top interconnection layer (not shown) may be formed on the substrate  100  where the top contact plugs  150   c  and  150   f  are formed. The top interconnection layer may be patterned to form top interconnections  160   c  and  160   f,  which may include a cell top interconnection  160   c  formed at the cell region A and a fuse top interconnection  160   f  formed at the fuse region B. Each of the cell top interconnection  160   c  and the fuse top interconnection layer  160   f  may include a multi-layer structure including a diffusion barrier layer  162 , an interconnection layer  164 , and a diffusion barrier layer  166  which are sequentially stacked. 
         [0070]      FIGS. 7A through 7F  are cross-sectional views illustrating a method of forming an electric device according to another embodiment of the present invention. 
         [0071]    Referring to  FIG. 7A , a substrate  200  may include a fuse region A and a cell region B. A bottom interlayer dielectric  210  is formed on the substrate  200 . The bottom interlayer dielectric  210  may be formed by means of chemical vapor deposition (CVD) or spin coating. The bottom interlayer dielectric  210  may be formed of silicon oxide. A top surface of the bottom interlayer dielectric  210  may be planarized. The bottom interlayer dielectric  210  may be patterned to form bottom contact holes  214   c  and  214   f,  which may include a cell bottom contact hole  214   c  formed at the cell region A and a fuse bottom contact hole  214   f  formed at the fuse region B. The cell contact hole  214   c  and the fuse contact hole  214   f  may be formed at the same time. A bottom interconnection layer (not shown) may be deposited to cover the bottom contact holes  214   c  and  214   f  and the bottom interlayer dielectric  210 . The substrate  200  including the deposited bottom interconnection layer may be planarized to form bottom interconnections  212   c  and  212   f,  which may include a cell bottom interconnection  212   c  formed at the cell region A and a fuse bottom interconnection  212   f  formed at the fuse region B. The planarization of the substrate  200  including the deposited bottom interconnection layer may be done by means of a chemical mechanical polishing (CMP) process or an etch-back process. 
         [0072]    Referring to  FIG. 7B , a first intermediate interlayer dielectric  220  and a second intermediate interlayer dielectric  222  may be sequentially stacked on the bottom interconnections  214   f  and  214   c  and the bottom interlayer dielectric  210 . The first intermediate interlayer dielectric  220  may be formed of silicon oxide, and the second intermediate interlayer dielectric  222  may be formed of silicon nitride or silicon oxynitride. By patterning the second and first intermediate interlayer dielectrics  222  and  220 , intermediate contact holes  226   c  and  226   f  may be formed to expose the bottom interconnections  212   c  and  212   f,  respectively. The intermediate interlayer contact holes  226   c  and  226   f  may include a cell intermediate contact hole  226   c  formed at the cell region A and a fuse intermediate contact hole  226   f  formed at the fuse region B. 
         [0073]    Referring to  FIG. 7C , a bottom electrode spacer layer (not shown) may be conformally formed on the interlayer contact holes  226   c  and  226   f  and the second intermediate interlayer dielectric  222 . The bottom electrode spacer layer may be formed of silicon nitride. The bottom electrode spacer layer may be anisotropically etched to form bottom electrode spacers  222   c  and  222   f  on sidewalls of the intermediate contact holes  226   c  and  226   f.  The bottom electrode spacers  222   c  and  222   f  may include a cell bottom electrode spacer  222   c  formed at the cell region A and a fuse electrode spacer  222   f  formed at the fuse region B. 
         [0074]    A bottom electrode layer (not shown) is deposited to fill the intermediate contact holes  226   c  and  226   f.  The substrate  200  may be planarized down to a top surface of the first intermediate interlayer dielectric  220  to form bottom electrodes  224   c  and  224   f,  which may include a cell bottom electrode  224   c  and a fuse bottom electrode  224   f.    
         [0075]    Referring to  FIG. 7D , a top interlayer dielectric  240  may be formed on the top electrodes  224   c  and  224   f.  The top interlayer dielectric  240  may be formed of silicon oxide. The top interlayer dielectric  140  may be patterned down to top surfaces of the bottom electrodes  224   c  and  224   f  to form phase change contact holes  236   c  and  236   f,  which may include a cell phase change contact hole  236   c  formed at the cell region A and a fuse phase change contact hole  236   f  formed at the fuse region B. 
         [0076]    A phase change spacer layer (not shown) may be conformally formed on the phase change contact holes  236   c  and  236   f  and the top interlayer dielectric  240 . The phase change spacer layer may be anisotropically etched to form phase change spacers  231   c  and  231   f  on sidewalls of the phase change contact holes  236   c  and  236   f.  The phase change spacers  231   c  and  231   f  may include a cell phase change spacer  231   c  formed at the cell region A and a fuse phase change spacer  231   f  formed at the fuse region B. Each of the phase change spacers  231   c  and  231   f  may be formed of silicon nitride. A first phase change layer  232  may be conformally formed on the substrate  200  where the phase change spacers  231   c  and  231   f  are formed. 
         [0077]    In an alternative embodiment, each of the phase change contact holes  236   c  and  236   f  may have the shape of a trench. The phase change spacers  231   c  and  231   f  may be formed on the sidewall of the trench. 
         [0078]    Referring to  FIG. 7E , the first phase change layer  232  at the cell region A may be removed, which may be done by means of anisotropic etching. A second phase change layer  234  may be deposited on the substrate  200  to fill the phase change contact holes  236   c  and  236   f.    
         [0079]    Referring to  FIG. 7F , the substrate  200  including the deposited second phase change layer  234  may be planarized down to a top surface of the top interlayer dielectric  240  to form top phase change patterns  230   c  and  230   f,  which may include a cell top phase change pattern  230   c  formed at the cell region A and a fuse top phase change pattern  230   f  formed at the fuse region B. The fuse phase change pattern  230   f  may include a first fuse phase change pattern  232   f  and a second phase change pattern  234   f.    
         [0080]    In an alternative embodiment, phase change patterns  230   c  and  230   f  may be line-shaped phase change patterns filling the trench-shaped phase change contact holes  236   c  and  236   f,  respectively. 
         [0081]    Returning to  FIG. 2 , a top interconnection layer (not shown) may be formed on the phase change patterns  230   c  and  230   f.  The top interconnection layer may be patterned to form top interconnections  260   c  and  260   f,  which may include a cell top interconnection  260   c  formed at the cell region A and a fuse top interconnection  260   f  formed at the fuse region B. Each of the cell top interconnection  260   c  and the fuse top interconnection  260   f  may have a multi-layer structure including a diffusion barrier layer  262 , an interconnection layer  264 , and a diffusion barrier layer  266  which are sequentially stacked. 
         [0082]      FIGS. 8A through 8E  are cross-sectional views illustrating a method of forming an electric device according to yet another embodiment of the present invention. 
         [0083]    Referring to  FIG. 8A , a substrate  300  may include a fuse region A and a cell region B. A bottom interlayer dielectric  310  is formed on the substrate  300 . The bottom interlayer dielectric  310  may be formed by means of chemical vapor deposition (CVD) or spin coating. The bottom interlayer dielectric  310  may be formed of silicon oxide. A top surface of the bottom interlayer dielectric  310  may be planarized. The bottom interlayer dielectric  310  may be patterned to form bottom contact holes  314   c  and  314   f,  which may include a cell bottom contact hole  314   c  formed at the cell region A and a fuse bottom contact hole  314   f  formed at the fuse region B. The cell contact hole  314   c  and the fuse contact hole  314   f  may be formed at the same time. A bottom interconnection layer (not shown) may be deposited to cover the bottom contact holes  314   c  and  314   f  and the bottom interlayer dielectric  310 . The substrate  300  including the deposited bottom interconnection layer may be planarized to form bottom interconnections  312   c  and  312   f,  which may include a cell bottom interconnection  312   c  formed at the cell region A and a fuse bottom interconnection  312   f  formed at the fuse region B. The planarization of the substrate  300  including the deposited bottom interconnection layer may be done by means of a chemical mechanical polishing (CMP) process or an etch-back process. 
         [0084]    Referring to  FIG. 8B , a first intermediate interlayer dielectric  320  and a second intermediate interlayer dielectric  322  may be sequentially stacked on the bottom interconnections  314   f  and  314   c  and the bottom interlayer dielectric  310 . The first intermediate interlayer dielectric  320  may be formed of silicon oxide, and the second intermediate interlayer dielectric  322  may be formed of silicon nitride or silicon oxynitride. By patterning the second and first intermediate interlayer dielectrics  322  and  320 , intermediate contact holes  326   c  and  326   f  may be formed to expose the bottom interconnections  312   c  and  312   f,  respectively. The intermediate interlayer contact holes  326   c  and  326   f  may include a cell intermediate contact hole  326   c  formed at the cell region A and a fuse intermediate contact hole  326   f  formed at the fuse region B. 
         [0085]    Referring to  FIG. 8C , a bottom electrode spacer layer (not shown) may be conformally formed on the interlayer contact holes  326   c  and  326   f  and the second intermediate interlayer dielectric  322 . The bottom electrode spacer layer may be formed of silicon nitride. The bottom electrode spacer layer may be anisotropically etched to form bottom electrode spacers  322   c  and  322   f  on sidewalls of the intermediate contact holes  326   c  and  326   f.  The bottom electrode spacers  322   c  and  322   f  may include a cell bottom electrode spacer  322   c  formed at the cell region A and a fuse electrode spacer  322   f  formed at the fuse region B. 
         [0086]    Referring to  FIG. 8D , a bottom electrode layer (not shown) may be deposited to fill the intermediate contact holes  326   c  and  326   f.  The substrate  300  may be planarized down to a top surface of the first intermediate interlayer dielectric  320  to form bottom electrodes  324   c  and  324   f,  which may include a cell bottom electrode  324   c  formed at the cell region A and a fuse bottom electrode  324   f  formed at the fuse region B. 
         [0087]    Referring to  FIG. 8E , a top interlayer dielectric  340  may be formed on the bottom electrodes  324   c  and  324   f.  The top interlayer dielectric  340  may be formed of silicon oxide. The top interlayer dielectric  340  may be patterned down to top surfaces of the bottom electrodes  324   c  and  324   f  to form phase change contact holes  331   c  and  331   f.  The first phase change layer  332  may be conformally formed on the phase change contact holes  331   c  and  331   f  and the top interlayer dielectric  340 . The first phase change layer  331  at the cell region A may be removed by means of anisotropic etching. A second phase change layer  334  may be conformally formed on the phase change contact holes  331   c  and  331   f  and the top interlayer dielectric  340 . The second phase change layer  334  may not fill up the phase change contact holes  331   c  and  331   f.  A top electrode layer  336  may be formed on the second phase change layer  334 . In an alternative embodiment, each of the phase change contact holes  331   c  and  331   f  may have the shape of a trench. 
         [0088]    Returning to  FIG. 3 , the substrate  300  may be planarized down to a top surface of the top interlayer dielectric  340  to form phase change patterns  330   c  and  330   f  and top electrodes  336   c  and  336   f.  The phase change patterns  330   c  and  330   f  may include a cell phase change pattern  33   c  formed at the cell region A and a fuse phase change pattern  330   f  formed at the fuse region B. The fuse phase change pattern  330   f  may include a first phase change pattern  332   f  and a second phase change pattern  334   f.  A top interconnection layer (not shown) may be formed on the phase change patterns  330   c  and/or the top electrodes  336   c  and  336   f.  The top interlayer connection layer may be patterned to form top interconnections  360   c  and  360   f,  which may include a cell top interconnection  360   c  formed at the cell region A and a fuse top interconnection  360   f  formed at the fuse region B. Each of the cell top interconnection  360   c  and the fuse top interconnection  360   f  may have a multi-layer structure including a diffusion barrier layer  362 , an interconnection layer  364 , and a diffusion barrier layer  366  which are sequentially stacked. In an alternative embodiment, the phase change patterns  330   c  and  330   f  may be a line-shaped patterns filling the trench-shaped phase change contact holes  331   c  and  331   f,  respectively. 
         [0089]      FIGS. 9A through 9E  are cross-sectional views illustrating a method of forming an electric device according to further another embodiment of the present invention. 
         [0090]    Referring to  FIG. 9A , a substrate  400  may include a fuse region A and a cell region B. A bottom interlayer dielectric  410  is formed on the substrate  400 . The bottom interlayer dielectric  410  may be formed by means of chemical vapor deposition (CVD) or spin coating. The bottom interlayer dielectric  410  may be formed of silicon oxide. A top surface of the bottom interlayer dielectric  410  may be planarized. The bottom interlayer dielectric  410  may be patterned to form bottom contact holes  414   c  and  414   f,  which may include a cell bottom contact hole  414   c  formed at the cell region A and a fuse bottom contact hole  414   f  formed at the fuse region B. The cell contact hole  414   c  and the fuse contact hole  414   f  may be formed at the same time. A bottom interconnection layer (not shown) may be deposited to cover the bottom contact holes  414   c  and  414   f  and the bottom interlayer dielectric  410 . The substrate  400  including the deposited bottom interconnection layer may be planarized to form bottom interconnections  412   c  and  412   f,  which may include a cell bottom interconnection  412   c  formed at the cell region A and a fuse bottom interconnection  412   f  formed at the fuse region B. The planarization of the substrate  400  including the deposited bottom interconnection layer may be done by means of a chemical mechanical polishing (CMP) process or an etch-back process. 
         [0091]    Referring to  FIG. 9B , a first intermediate interlayer dielectric  420  and a second intermediate interlayer dielectric  422  may be sequentially stacked on the bottom interconnections  414   f  and  414   c  and the bottom interlayer dielectric  410 . The first intermediate interlayer dielectric  420  may be formed of silicon oxide, and the second intermediate interlayer dielectric  422  may be formed of silicon nitride or silicon oxynitride. By patterning the second and first intermediate interlayer dielectrics  422  and  420 , intermediate contact holes  424   c  and  424   f  may be formed to expose the bottom interconnections  412   c  and  412   f,  respectively. The intermediate interlayer contact holes  424   c  and  424   f  may include a cell intermediate contact hole  424   c  formed at the cell region A and a fuse intermediate contact hole  424   f  formed at the fuse region B. 
         [0092]    Referring to  FIG. 9C , a phase change spacer layer (not shown) may be conformally formed on the intermediate contact holes  424   c  and  424   f  and the second intermediate interlayer dielectric  422 . The phase change spacer layer may be formed of silicon nitride. The phase change spacer layer may be anisotropically etched to form phase change spacers  431   c  and  431   f  at sidewalls of the intermediate contact holes  424   c  and  424   f.  The phase change spacers  431   c  and  431   f  may include a cell phase change spacer  431   c  formed at the cell region A and a fuse phase change spacer  431   f  formed at the fuse region B. 
         [0093]    Referring to  FIG. 9D , a first phase change layer  432  may be formed to fill the intermediate contact holes  424   c  and  424   f.  The first phase change layer  432  at the cell region A may be removed by means of anisotropic etching. A second phase change layer  434  may be formed on the substrate  400  to fill the cell intermediate contact hole  424   c.    
         [0094]    Referring to  FIG. 9E , the substrate  400  may be planarized down to a top surface of the first intermediate interlayer dielectric  420  to form a cell phase change pattern  430   c  at the cell region A and a fuse phase change pattern  430   f  at the fuse region B. A crystallization temperature of the fuse phase change pattern  430   f  may be higher than that of the fuse phase change pattern  430   c.  The fuse phase change pattern  430   f  may be made of Ge 2 Sb 2 Te 5 . The cell phase change pattern  430   c  may include one selected from the group consisting of As—Sb—Te-metal compound, As—Ge—Sb—Te-metal compound, metal-Sb—Te-metal compound,  5 A group element-Sb—Te-metal compound,  6 A group element-Sb—Te-metal compound,  5 A group element-Sb—Se-metal compound, and  6 A group element-Sb—Se-metal compound. There may be various ratios of the compounds. Specifically, the  5 A group element may be nitrogen (N) or phosphorous (P), and the  6 A group element may be oxygen (O) or sulfur (S). The fuse phase change pattern  430   f  may include at least one selected from the group consisting of In—Sb—Te,  5 A group element-In—Sb—Te compound, and  6 A group element-In—Sb—Te compound. 
         [0095]    Returning to  FIG. 4 , a top interconnection layer may be formed on the phase change patterns  430   c  and  430   f.  The top interconnection layer may be patterned to form top interconnections  460   c  and  460   f,  which may include a cell top interconnection  460   c  formed at the cell region A and a fuse top interconnection  460   f  formed at the fuse region B. Each of the cell top interconnection  460   c  and the fuse top interconnection  460   f  may have a multi-layer structure including a diffusion barrier layer  462 , an interconnection layer  464 , and a diffusion barrier layer  466  which are sequentially stacked. 
         [0096]      FIGS. 10A and 10B  are cross-sectional views illustrating a method of forming an electric device according to still another embodiment of the present invention. 
         [0097]    Referring to  FIG. 10A , a substrate  500  may include a fuse region A and a cell region B. A bottom interlayer dielectric  510  is formed on the substrate  500 . The bottom interlayer dielectric  510  may be formed by means of chemical vapor deposition (CVD) or spin coating. The bottom interlayer dielectric  510  may be formed of silicon oxide. A top surface of the bottom interlayer dielectric  510  may be planarized. The bottom interlayer dielectric  510  may be patterned to form bottom contact holes  514   c  and  514   f,  which may include a cell bottom contact hole  514   c  formed at the cell region A and a fuse bottom contact hole  514   f  formed at the fuse region B. The cell contact hole  514   c  and the fuse contact hole  514   f  may be formed at the same time. A bottom interconnection layer (not shown) may be deposited to cover the bottom contact holes  514   c  and  514   f  and the bottom interlayer dielectric  510 . The substrate  500  including the deposited bottom interconnection layer may be planarized to form bottom interconnections  512   c  and  512   f,  which may include a cell bottom interconnection  512   c  formed at the cell region A and a fuse bottom interconnection  512   f  formed at the fuse region B. The planarization of the substrate  500  including the deposited bottom interconnection layer may be done by means of a chemical mechanical polishing (CMP) process or an etch-back process. 
         [0098]    A top interlayer dielectric  540  may be formed on the bottom interlayer dielectric  510 . The top interlayer dielectric  540  may be patterned down to top surfaces of the bottom interconnections  512   c  and  512   f  to form phase change contact holes  536   c  and  536   f.  A phase change spacer layer (not shown) may be conformally formed on the phase change contact holes  536   c  and  536   f  and the top interlayer dielectric  540 . The phase change spacer layer may be anisotropically etched to form phase change spacers  531   c  and  531   f  on sidewalls of the phase change contact holes  536   c  and  536   f.  A bottom electrode layer  524  may be deposited to fill the phase change contact holes  536   c  and  536   f.  In an alternative embodiment, each of the phase change contact holes  536   c  and  536   f  may have the shape of a trench. 
         [0099]    Referring to  FIG. 10B , the bottom electrode layer may be etched back to form bottom electrodes  524   c  and  524   f,  which may include a cell bottom electrode  524   c  formed at the cell region A and a fuse bottom electrode  524   f  formed at the fuse region B. Top surfaces of the bottom electrodes  524   c  and  524   f  may be lower than a top surface of the top interlayer dielectric  540 . A first phase change layer  532  may be deposited on the phase change contact holes  536   c  and  536   f  and the top interlayer dielectric  540 . The first phase change layer  532  may be patterned to remove the first phase change layer  532  at the cell region A. The patterning of the first phase change layer  532  may include isotropic etching. A second phase change layer  534  may be deposited to fill the phase change contact holes  536   c  and  536   f.  A crystallization temperature of the first phase change layer  532  may be higher than that of the second phase change layer  534 . 
         [0100]    Returning to  FIG. 5 , the second phase change layer  534  and the first phase change layer  532  may be planarized down to a top surface of the top interlayer dielectric  540  to form a cell phase change pattern  530   c  at the cell region A and a fuse phase change pattern  530   f  at the fuse region B. The planarization of the second phase change layer  534  and the first phase change layer  532  may be done by means of chemical mechanical polishing (CMP). The fuse phase change pattern  530   c  may include a first fuse phase change pattern  532   c  and a second fuse phase change pattern  534   c.  In an alternative embodiment, the phase change patterns  530   c  and  530   f  may be line-shaped patterns filling the trench-shaped phase change contact holes  536   c  and  536   f,  respectively. 
         [0101]    A top interconnection layer may be formed on the phase change patterns  530   c  and  530   f.  The top interconnection layer may be patterned to form top interconnections  560   c  and  560   f,  which may include a cell top interconnection  560   c  formed at the cell region A and a fuse top interconnection formed at the fuse region B. The cell top interconnection  560   c  may have a multi-layer structure including a diffusion barrier layer  562   c,  an interconnection layer  564   c,  and a diffusion barrier layer  566   c  which are sequentially stacked, and the fuse top interconnection  560   f  may have a multi-layer structure including a diffusion barrier layer  562   f,  an interconnection layer  564   f,  and a diffusion barrier layer  566   f  which are sequentially stacked. 
         [0102]    Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made without departing from the scope and spirit of the invention.