Abstract:
A semiconductor memory device may include bit line coupled to a sense amplifier and an auxiliary sensing unit to drive an output line in response to the voltage of the bit line during a read operation. In some embodiments, the auxiliary sensing unit may include a differential amplifier arranged to compare the voltage of the bit line to a reference voltage. A method of reading a memory cell may include precharging a bit line, transferring charge from the memory cell to the bit line, activating a sense amplifier coupled to the bit line, and comparing the voltage of the bit line to a reference voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of Korean Patent Application No. 10-2005-0106395, filed on Nov. 8, 2005 which is incorporated by reference.  
       BACKGROUND  
       [0002]     In general, memory devices such as dynamic random access memory (DRAM) use charge sharing that occurs between a capacitance component of a bit line and a memory cell capacitor when data is written to or read from a memory cell. In particular, data can be read from the memory cell by sense-amplifying a voltage difference generated between two bit lines using charge sharing.  
         [0003]      FIG. 1  is a prior art circuit diagram illustrating a semiconductor memory device having a conventional sense amplifier structure. Referring to  FIG. 1 , the semiconductor memory device includes a memory cell array  10 , a sense amplifier  20 , an equalization transistor unit  30 , and a column select gate pair  40 .  
         [0004]     The memory cell array  10  includes a plurality of memory cells (not shown). Each memory cell includes a transistor which is gated by a word line voltage and a cell capacitor which stores data. When a memory cell to be written or read is connected to a first bit line BL  1 , read and write operations are performed as follows.  
         [0005]     First, the equalization transistor unit  30  is turned on by a precharge control signal PEQ, so bit lines BL 1  and BL 2  are precharged to a precharge voltage VBL.  
         [0006]     Thereafter, a word line of the memory cell to be read is activated, and charge sharing occurs between a cell capacitor included in the memory cell and the first bit line BL 1 . As a result, a voltage difference is generated between the bit line pair BL 1  and BL 2 . A pull-up transistor MP 1  and a pull-down transistor MN 1  are turned on by control signals LAPG and LANG, respectively. Through the operation of the sense amplifier  20 , when high-level data is stored in the memory cell, the first bit line BL 1  is driven to a pull-up voltage Vint, and the second bit line BL 2  is driven to a pull-down voltage Vss. The pull-down voltage Vss is generally a ground voltage. A first column gate of the column select gate pair  40  is turned on by an activated first column selection signal CSL 1 , and transmits a voltage signal from the first bit line BL 1  to a first input-output line IO 1 . Similarly, a second column gate is turned on by an activated second column selection signal CSL 2 , and transmits a voltage signal from the second bit line BL 2  to a second input-output line IO 2 .  
         [0007]     A write operation is performed in a similar manner to the read operation. Data signals input from the input-output lines IO 1  and IO 2  are transmitted through the first bit line BL 1  of the memory cell array  10  via the column select gate pair  40 .  
         [0008]     If high-level data is to be written in the memory cell, a signal having a voltage corresponding to the pull-up voltage Vint is transmitted through the first input-output line IO 1 , and a signal having a voltage corresponding to the pull-down voltage Vss is transmitted through the second input-output line IO 2 .  
         [0009]     The write operation will now be described with reference to  FIG. 2  which is a prior art circuit diagram illustrating a general memory cell. Referring to  FIG. 2 , the memory cell includes a transistor T 1  and a cell capacitor C 1 . A gate electrode of the transistor T 1  is connected to a first word line WL 1 . A first electrode of the transistor T 1  is connected to a first bit line BL 1 , and a second electrode of the transistor T 1  is connected to the cell capacitor C 1 . The cell capacitor C 1  is connected between a second electrode of the transistor T 1  and a pull-down voltage Vss.  
         [0010]     As described above, when high-level data is written to the memory cell, the pull-up voltage Vint is applied to the first electrode of the transistor T 1 . The transistor T 1  is turned on by a word line voltage input to the first word line WL 1 , and the pull-up voltage Vint is applied to a first electrode of the capacitor C 1 . Accordingly, the capacitor C 1  stores the high-level data.  
         [0011]     If the word line WL 1  were to be driven with the pull-up voltage Vint, the voltage Vc applied to the first electrode of the capacitor C 1  would end up being lower than the pull-up voltage Vint due to the threshold voltage of the transistor T 1 . Therefore, a power supply voltage Vpp, which is higher than the pull-up voltage Vint, is generally used to drive the first word line WL 1 . The use of an elevated word line voltage, however, results in increased power consumption.  
         [0012]     Meanwhile, the data stored in the memory cell may be lost due to leakage current. To prevent this, periodical refresh operations are required. In particular, high-level data is more vulnerable to leakage current than low-level data when stored in the memory cell.  
         [0013]     As describe above, when a voltage corresponding to the pull-up voltage Vint is applied to a cell capacitor in order to store high-level data, data retention time decreases, and thus a refresh period also decreases. As the refresh period decreases, more power is required to retain the data.  
       SUMMARY  
       [0014]     Some of the inventive principles of this patent disclosure relate to a semiconductor memory device having a bit line coupled to a sense amplifier and an auxiliary sensing unit to drive an output line in response to the voltage of the bit line during a read operation. In some embodiments, the auxiliary sensing unit may include a differential amplifier arranged to compare the voltage of the bit line to a reference voltage.  
         [0015]     Some additional inventive principles of this patent disclosure relate to a method of reading a memory cell in which charge is transferred from the memory cell to a bit line, a sense amplifier coupled to the bit line is activated, the voltage of the bit line is compared to a reference voltage, and an output line is driven in response to the comparison. The output line may be driven to a first state if the difference between the voltage of the bit line and the reference voltage is greater than or equal to a detection voltage, and driven to a second state if the difference is less than the detection voltage. In some embodiments, the sense amplifier may be activated before the voltage of the bit line is compared to the reference voltage during a read operation.  
         [0016]     Some additional inventive principles of this patent disclosure relate to a memory device including an equalization transistor unit to precharge a pair of bit lines to a precharge voltage, a sense amplifier to sense a voltage difference between the bit lines, a pair of column select gates coupled between the bit lines and a pair of input-output lines, and a first differential amplifier having a first input coupled to a first one of the bit lines, a second input coupled to a reference voltage, and two outputs coupled to the input-output lines. The first differential amplifier may drive its outputs to a first state if the voltage difference between the first bit line and the reference voltage reaches a detection voltage, and to a second state if the difference does not reach the detection voltage. In some embodiments, the detection voltage includes a minimum detectable voltage difference between the first and second inputs of the first differential amplifier, and may further include an offset voltage of the first differential amplifier.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]      FIG. 1  is a circuit diagram illustrating a semiconductor memory device having a conventional sense amplifier structure.  
         [0018]      FIG. 2  is a circuit diagram illustrating a general memory cell.  
         [0019]      FIG. 3  is a circuit diagram illustrating an embodiment of a semiconductor memory device according to some of the inventive principles of this patent disclosure.  
         [0020]      FIG. 4  is a timing diagram illustrating an embodiment of a data read operation of the semiconductor memory device of  FIG. 3  according to some of the inventive principles of this patent disclosure.  
         [0021]      FIG. 5  is a timing diagram illustrating an embodiment of a data write operation of the semiconductor memory device of  FIG. 3  according to some of the inventive principles of this patent disclosure.  
         [0022]      FIG. 6  is a block diagram illustrating an embodiment of an enable signal generator used in a semiconductor memory device according to some of the inventive principles of this patent disclosure. 
     
    
     DETAILED DESCRIPTION  
       [0023]     The attached drawings for illustrating exemplary embodiments of the present invention are referred to in order to gain a sufficient understanding, but the inventive principles are not limited to these exemplary embodiments.  
         [0024]      FIG. 3  is a circuit diagram illustrating an embodiment of a semiconductor memory device in accordance with some of the inventive principles of this patent disclosure. Referring to  FIG. 3 , the semiconductor memory device includes a memory cell array  110 , an equalization transistor unit  120 , a sense amplifier  130 , a column select gate pair  150 , and an auxiliary sensing unit which, in this embodiment, is implemented with a differential amplifier unit  140 .  
         [0025]     The memory cell array  110  includes a plurality of memory cells. For example, a first memory cell  111  and a second memory cell  112 , which are respectively connected to bit line pair BL 1  and BL 2 , are shown in  FIG. 3 . Each of the memory cells  111  and  112  includes a transistor and a cell capacitor. A voltage Vc is applied to a first electrode of the cell capacitor. A gate of the transistor in the first memory cell  111  is connected to a first word line WL 1 , and a gate of the transistor in the second memory cell  112  is connected to a second word WL 2 .  
         [0026]     The equalization transistor unit  120  is connected to the bit line pair BL 1  and BL 2 , and precharges the bit line pair BL 1  and BL 2  to a precharge voltage. The equalization transistor unit  120  is controlled by a precharge control signal PEQ. In the embodiment of  FIG. 3 , the precharge voltage corresponds to the sum of a reference voltage Vref and a detection voltage ΔV.  
         [0027]     The sense amplifier  130  is connected between the bit line pair BL 1  and BL 2 , and senses a voltage difference between the bit line pair BL 1  and BL 2 . The sense amplifier  130  includes a PMOS transistor portion and an NMOS transistor portion. The PMOS transistor portion is connected to a pull-up transistor T 11 , which is gated by a pull-up control signal LAPG. Similarly, the NMOS transistor portion is connected to a pull-down transistor T 12 , which is gated by a pull-down control signal LANG.  
         [0028]     The auxiliary sensing unit in the embodiment of  FIG. 3  is implemented with a differential amplifier unit  140  which includes a first differential amplifier  141  and a second differential amplifier  142 . A first input node of the first differential amplifier  141  is connected to the first bit line BL 1 , and a second input node thereof is connected to the reference voltage Vref. The output nodes of the first differential amplifier  141  are connected to an input-output line pair IO 1  and IO 2 .  
         [0029]     In addition, a first input node of the second differential amplifier  142  is connected to the second bit line BL 2 , and a second input node thereof is connected to the reference voltage Vref. The output nodes of the second differential amplifier  142  are connected to the input-output line pair IO 1  and IO 2 .  
         [0030]     The first differential amplifier  141  outputs a high-level data signal through the input-output line pair IO 1  and IO 2 , when a voltage at the first bit line BL 1  is higher than the reference voltage Vref by at least the detection voltage ΔV. In other words, when data stored in the memory cell  111  is high-level data, a signal having a voltage Vint is output through the first input-output line IO 1 , and a signal having a voltage Vss is output through the second input-output line IO 2 .  
         [0031]     Similarly, the second differential amplifier  142  also outputs a high-level data signal through the input-output line pair IO 1  and IO 2 , when a voltage at the second bit line BL 2  is higher than the reference voltage Vref by at least the detection voltage ΔV. In other words, when data stored in the memory cell  112  is high-level data, the signal having the voltage Vss is output through the first input-output line IO 1 , and the signal having the voltage Vint is output through the second input-output line IO 2 .  
         [0032]     A first enable signal RCSL 1  controls the operation of the first differential amplifier  141  and a second enable signal RCSL 2  controls the operation of the second differential amplifier  142 .  
         [0033]     The column select gate pair  150  is connected to the bit line pair BL 1  and BL 2  and the input-output line pair IO 1  and IO 2 . A first column gate T 13  may be coupled between the first bit line BL 1  and the first input-output line IO 1 , and a second column gate T 14  may be coupled between the second bit line BL 2  and the second input-output line IO 2 .  
         [0034]     The operation of the semiconductor memory device having the aforementioned structure according to an embodiment of the present invention will now be described with reference to  FIG. 4 .  
         [0035]      FIG. 4  is a timing diagram illustrating a data read operation of the semiconductor memory device of  FIG. 3  in accordance with some of the inventive principles of this patent disclosure. The timing diagram shows a case where data of the memory cell  111  connected to the first bit line BL 1  is read.  
         [0036]     Referring to  FIG. 4 , a precharge control signal PEQ is first activated, which turns on the transistors of the equalization transistor unit  120 . As a result, the bit line pair BL 1  and BL 2  is precharged to a specific precharge voltage. When the bit line pair BL 1  and BL 2  is precharged, the precharge voltage becomes equal to a sum of a reference voltage Vref and a detection voltage ΔV.  
         [0037]     The detection voltage ΔV may be at least equal to a minimum voltage difference detectable by a differential amplifier included in the differential amplifier unit  140 . The minimum voltage difference may include an offset voltage of the differential amplifier. For example, when the minimum detectable voltage difference of the differential amplifier is 100 mV under normal operating conditions, and the offset voltage of the differential amplifier is 30 mV, then the detection voltage ΔV has to be 130 mV or higher. In this case, the precharge voltage becomes the sum of the reference voltage Vref and 130 mV.  
         [0038]     After the precharge operation of the bit line pair BL 1  and BL 2  is completed based on the aforementioned precharge voltage, the precharge control signal PEQ is deactivated. Thereafter, a first word line WL 1  is activated to read data of the first memory cell  111 . This turns on the transistor included in the first memory cell  111  and thus charge sharing occurs between the cell capacitor of the first memory cell  111  and a capacitance component of the first bit line BL 1 .  
         [0039]     In order for the first memory cell  111  to be read as high-level data, the voltage Vc stored in the cell capacitor has to be equal to or greater than the sum of the reference voltage Vref and the detection voltage ΔV. This is because, when a first bit line voltage input to a first input node of the first differential amplifier  141  is greater than the reference voltage Vref by at least as much as the detection voltage ΔV, the first differential amplifier  141  outputs a high-level data signal through a differential amplification of the two input signals.  
         [0040]     Thereafter, a pull-up control signal LAPG and a pull-down control signal LANG are activated, thereby enabling the sense amplifier  130 . Here, if the voltage Vc stored in the cell capacitor of the first memory cell  111  is Vref+ΔV, the first bit line voltage is almost equal to the voltage stored in the cell capacitor. Thus, even after charge sharing occurs, the first bit line voltage is maintained at approximately the level of Vref+ΔV.  
         [0041]     Thereafter, the first enable signal RCSL 1  is activated, thereby enabling the first differential amplifier  141  of the differential amplifier unit  140 . In addition, the first column select signal WCSL 1  and the second column select signal WSCL 2  are activated, thereby turning on first and second column select gates T 13  and T 14  of the column select gate pair  150 , respectively.  
         [0042]     As described above, in the first differential amplifier  141 , a first bit line voltage is input to a positive input node, and a reference voltage Vref is input to a negative input node. If the first bit line voltage is greater than the reference voltage Vref by at least as much as the detection voltage ΔV, a high-level data signal is output through the input-output line pair IO 1  and IO 2 . Accordingly, if the first bit line has a voltage of Vref+ΔV or more, the first differential amplifier  141  amplifies the voltage (the first bit line voltage and the reference voltage) input to the two input nodes, and outputs the high-level data signal through the input-output line pair IO 1  and IO 2 . An output node of the first differential amplifier  141  is connected to the input-output line pair IO 1  and IO 2 . When a high-level data signal is the output, the output node of the first differential amplifier  141  may output a voltage signal corresponding to Vint through the first input-output line IO 1 , and output a voltage signal corresponding to Vss through the second input-output line IO 2 .  
         [0043]     Even when the charge stored in the capacitor of memory cell  111  is partially lost due to a leakage current after the capacitor is charged to the voltage Vint to store high-level data in the first memory cell  111 , the semiconductor memory device may detect that the data stored in the first memory cell  111  is high-level as long as the voltage of the cell capacitor is equal to or greater than Vref+ΔV. In other words, even if charge stored in the cell capacitor is lost to some extent, the data can be accurately detected, and thus a refresh period for preserving the data can be extended. The more the reference voltage Vref drops, the more the data is accurately detected, even when the charge is lost significantly.  
         [0044]     Further, since the data can be accurately detected even if the charge loss is significant in the cell capacitor, a word line voltage connected to the memory cell can be lowered. For example, for the first word line WL 1  voltage input to a gate electrode of the transistor included in the first memory cell  111 , the pull-up voltage Vint may be input which is lower than the power supply voltage Vpp which is conventionally used. This is because the data stored in the memory cell can be detected even when a voltage applied to a first electrode of the cell capacitor decreases due to a threshold voltage of the transistor.  
         [0045]     By respectively turning on the first and second column select gates T 13  and T 14  of the column select gate pair  150 , a voltage signal output through the input-output line pair IO 1  and IO 2  can be transmitted to the first memory cell  111 . This is a write back operation, through which the data of the first memory cell  111  can be prevented from being lost right after a data read operation.  
         [0046]     Even when low-level data is stored in the first memory cell  111 , the data can be read by the aforementioned operation. In the process of reading the low-level data, charge sharing occurs between the cell capacitor of the first memory cell  111  and the first bit lint BL 1 , and a voltage of the first bit lint BL 1  decreases.  
         [0047]     Referring to  FIG. 4 , when the low-level data (data “0”) is read, a sufficient voltage difference is generated between the bit line pair BL 1  and BL 2  due to the charge sharing, and thus the sense amplifier  130  carries out an amplification operation. As a result, the first bit line voltage input to a first input node of the first differential amplifier  141  becomes lower than the reference voltage Vref by as much as the detection voltage ΔV. In this case, the first differential amplifier  141  outputs the low-level data signal through the input-output line pair IO 1  and IO 2 . As shown in  FIG. 4 , when the low-level data is read, after the first bit line voltage becomes lower than the reference voltage Vref by as much as the detection voltage ΔV, the first enable signal RCSL 1  may be activated to enable the first differential amplifier  141 .  
         [0048]     The operation of the first memory cell  11  of  FIG. 3  has been described above. The second memory cell  112  and other memory cells (not shown) may perform the same operation to achieve the same effect.  
         [0049]     Now, a data write operation of the semiconductor memory device will be described with reference to  FIG. 5 . The write operation will be described with reference to the first memory cell  111 , but similar operations can be performed for other cells as well.  
         [0050]      FIG. 5  is a timing diagram illustrating a data write operation of the semiconductor memory device of  FIG. 3  in accordance with some of the inventive principles of this patent disclosure. Referring to  FIG. 5 , a first word line W 1 , is activated after a precharge operation is completed, and a first column select signal WCSL 1  and a second column select signal WCSL 2  are activated. As a result, the column select gate pair  150  turns on.  
         [0051]     A data signal input through the input-output line pair IO 1  and IO 2  is input to the bit line pair BL 1  and BL 2  through the column select gate pair  140 . A voltage difference is generated between the bit line pair BL 1  and BL 2 .  
         [0052]     Thereafter, a pull-up control signal LAPG and a pull-down control signal LANG are activated, thereby turning on the pull-up transistor T 11  and the pull-down transistor T 12 , and data is stored in the memory cell  111  by using a voltage of an amplified bit line pair BL 1  and BL 2 . In the process of the data write operation, the first enable signal RCSL 1  and the second enable signal RCSL 2  are respectively deactivated, and thus the differential amplifier unit  140  does not operate.  
         [0053]      FIG. 6  is a block diagram illustrating an enable signal generator used in a semiconductor memory device according to an embodiment of the present invention. An enable signal generator  200  outputs a first enable signal RCSL 1  to a first differential amplifier  141 , and outputs a second enable signal RCSL 2  to a second differential amplifier  142 . The first differential amplifier  141  generates signals DIO 1  and DIO 2  according to a differential amplification operation, and outputs the signals DIO 1  and DIO 2  to an input-output line pair IO 1  and IO 2 , respectively. The second differential amplifier  142  also outputs the signals DIO 1  and DIO 2  through the input-output line pair IO 1  and IO 2 .  
         [0054]     During a read operation of the first memory cell  111 , the enable signal generator  200  outputs an activated first enable signal RCSL 1 , and outputs a deactivated second enable signal RCSL 2 . As a result, the first differential amplifier  141  is enabled, and the second differential amplifier  142  is disabled.  
         [0055]     Further, in a read operation of the second memory cell  112 , the enable signal generator  200  deactivates the first enable signal RCSL 1  and activates the second enable signal RCSL 2 . As a result, the first differential amplifier  141  is disabled, and the second differential amplifier  142  is enabled.  
         [0056]     On the other hand, in a write operation of the first and second memory cells  111  and  112 , both the first and second enable signals RCSL 1  and RCSL 2  are deactivated. As a result, the first differential amplifier  141  and the second differential amplifier  142  are disabled.  
         [0057]     Accordingly, in the present invention, a word line may be driven at a low voltage, and even if charge stored in a cell capacitor is lost to some extent, the data may be accurately sensed. Moreover, refresh rate of the capacitor may also be reduced. Therefore, less power may be consumed, and data retention features may be improved.  
         [0058]     While the inventive principles of this patent disclosure have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the appended claims.