Abstract:
A method and system for generating a set of computer instructions to implement a logical operation to be performed on a plurality of bitmaps. A Boolean equation is specified that has a plurality of terms that use Boolean operations. Subsets of computer instructions are generated that implement each of the Boolean operations of the terms. When executing a routine to display a bitmap (bitBLT routine), a logical operation and a plurality of bitmaps are specified. The routine determines which of the generated subsets of computer instructions are needed to implement the specified logical operation. The determined subsets of computer instructions are then retrieved and combined to form the set of computer instructions that implements a logical operation. The set of computer instructions can then be executed to effect a display of a bitmap with the specified logical operation.

Description:
TECHNICAL FIELD 
     This invention relates generally to a computer system for displaying bitmaps, and more particularly, a method and apparatus for combining multiple bitmaps. 
     BACKGROUND OF THE INVENTION 
     The output devices of personal computers often include bitmap graphics devices. A bitmap graphics device typically includes a graphics adapter, which has a display memory, and a display screen. The bitmap graphics device inputs a bitmap to be displayed and then displays that bitmap on the display screen. A bitmap is a matrix of bits that defines an image that is to be displayed in a rectangular area on a display screen. Each bit in a bitmap corresponds to one picture element (pixel) on the display screen. To display computer output data, a bitmap graphics device reads the bitmap stored in the display memory and renders the corresponding image on the display screen. If a bit in the display memory is 1, then the bitmap graphics device turns on the corresponding pixel on the display screen. If a bit in the display memory is 0, then the bitmap graphics device turns off the corresponding pixel on the display screen. By changing the contents of the display memory, for instance, by loading a new bitmap, a computer program can effect a change on the display screen. 
     A computer program typically generates a bitmap in program memory, and then copies the bitmap to the display memory. Copying from program memory to display memory can be relatively time-consuming because bitmaps are often quite large and can contain one million or more bits. To improve performance and facilitate computer programming, typical graphically-oriented operating systems provide routines that are optimized to copy bitmaps from program memory to display memory. These routines are known as bit block-transfer (bitBLT) routines. In general, these bitBLT routines can read as input a source bitmap and a destination bitmap, which is typically in display memory. These bitBLT routines copy the source bitmap to the destination bitmap in an efficient manner. 
     BitBLT routines are optimized to copy a computer word of data at a time, rather than just a single bit at a time. A computer word is a number of bits that the computer operates on as a unit. Computer words typically comprise 8, 16, or 32 bits. 
     FIGS. 1A and 1B are diagrams of a display memory showing the results of various bitBLT operations. FIG. 1A shows the display memory before executing the bitBLT routine, and FIG. 1B shows the display memory after executing the bitBLT routine. FIGS. 1C and 1D are diagrams of the display screen corresponding to FIGS. 1A and 1B, respectively. 
     FIG. 2 is a diagram showing sample source bitmaps of an image of an arrow. The outlined arrow bitmap 201 is a matrix of bits that is 32 bits high by 32 bits wide. To display the outlined arrow bitmap 201 on the display screen at location 111, a program, when calling a bitBLT routine, would specify that the outlined arrow bitmap 201 is the source bitmap and specify that the display memory bitmap 101 is the destination bitmap corresponding to location 111 on the display screen. The bitBLT routine then copies the outlined arrow bitmap 201 to the display memory bitmap 101. When the outlined arrow bitmap 201 is copied to the display memory bitmap 101, the bits in the 32 by 32 bit matrix in the display memory bitmap 101 are overwritten by the outlined arrow bitmap 201 as shown by display memory bitmap 105. To display the solid arrow bitmap 202 on the display screen at location 112, a program would specify that the solid arrow bitmap 202 is the source bitmap and specify that the display memory bitmap 102 is the destination bitmap corresponding to location 112 on the display screen. The bitBLT routine then copies the solid arrow bitmap 202 to the display memory bitmap 102. The bits in the 32 by 32 bit matrix in the display memory bitmap 102 are overwritten by the solid arrow bitmap 202, as shown by display memory bitmap 106. 
     In certain situations, a program may want to display an arrow that is transparent. A transparent arrow is shown displayed at location 117 on the display screen. The transparent arrow is an arrow in which the underlying screen display is left intact except for the outline of the arrow. To provide this capability, typical bitBLT routines, in addition to copying bitmaps, permit Boolean logic operations to be performed on a bit-by-bit basis on the source and destination bitmaps. For example, to generate the transparent arrow as shown at location 117, the program specifies the outlined arrow bitmap 201 as the source bitmap, the display memory bitmap 103 as the destination bitmap, and the AND operation when invoking the bitBLT routine. The bitBLT routine retrieves each bit from the outlined arrow bitmap 201 and the corresponding bit from the display memory bitmap 103, performs the AND operation on the bits, and stores the result in the display memory bitmap 103, resulting in the display memory bitmap 107. 
     Although the bitBLT routines that perform copying and Boolean operations on source and destination bitmaps provide considerable flexibility, there are certain computer graphics operations that require invoking these bitBLT routines more than once. For example, if a program were to output an arrow as shown at location 118, the program would first invoke the bitBLT routine specifying the solid arrow bitmap 202 as the source bitmap, the display memory bitmap 104 as the destination bitmap, and the AND operation. The program would then invoke the bitBLT routine specifying the arrow bitmap 203 as the source bitmap, the display memory bitmap 104 as the destination bitmap, and the exclusive-OR operation. The invoking of the bitBLT routine twice results in each bit in the destination bitmap 108 being read from and written to twice. When a destination bitmap is large, the reading and writing of each bit twice can result in unacceptable performance. 
     Because copying large bitmaps can be expensive, typical bitBLT routines have been generalized to allow two source bitmaps to be designated, along with a destination bitmap and a Boolean operation. For example, to generate the arrow at location 118, the invoking program would designate solid arrow bitmap 202 as the first source bitmap (S 1 ), arrow bitmap 203 as the second source bitmap (S 2 ), and display memory bitmap 104 as the destination bitmap (D), along with Boolean operations that specify S 1  is to be logically ANDed with D, and that the result is to be logically exclusive-ORed with S 2 . In standard Boolean algebra notation, that function would be specified as: 
     
         (S.sub.1 &amp; D)⊕S.sub.2 
    
     where &amp; represents the Boolean AND operator and where ⊕ represents the Boolean exclusive-OR operator. 
     Although it is possible to develop bitBLT routines that provide Boolean operations on an arbitrary number of source bitmaps, in practice, bitBLT routines typically support only two source bitmaps. When two source bitmaps are designated, the three bitmaps S 1 , S 2 , and D can be combined using Boolean operators in 256 unique ways. Each way of combining the three bitmaps is referred to as a logical operation or a raster operation. 
     
                       TABLE I______________________________________S.sub.1  1     1     1   1   0   0   0   0S.sub.2  1     1     0   0   1   1   0   0    BooleanD      1     0     1   0   1   0   1   0    Function______________________________________Result:  0     0     0   0   0   0   0   0    0  0     0     0   1   0   0   0   1    (S.sub.2 |D)&#39;  0     0     1   1   0   0   1   1    S.sub.2 &#39;  0     1     0   0   0   1   0   0    S.sub.2 &amp; D&#39;  0     1     0   1   0   1   0   1    D&#39;  0     1     0   1   1   0   1   0    S.sub.1 ⊕ D  0     1     1   0   0   1   1   0    S.sub.2 ⊕ D  0     1     1   0   1   1   0   0    (S.sub.2 &amp; D) ⊕ S.sub.1  1     0     0   0   1   0   0   0    S.sub.2 &amp; D  1     0     1   1   1   0   1   1    S.sub.1 &#39;|D  1     1     0   0   0   0   0   0    S.sub.2 &amp; S.sub.1  1     1     0   0   1   1   0   0    S.sub.2  1     1     1   0   1   1   1   0    S.sub.2 |D  1     1     1   1   0   0   0   0    S.sub.1  1     1     1   1   1   0   1   1    S.sub.2 &#39;|S.sub.1                                       |D  1     1     1   1   1   1   1   1    1______________________________________ 
    
     Table I shows a subset of the 256 logical operations which designate how the S 1 , S 2 , and D bitmaps can be combined. The column entitled &#34;Boolean Function&#34; shows the Boolean function, comprised of bitmaps and Boolean operators, which generates the corresponding result. 
     
                       TABLE II______________________________________S.sub.1  S.sub.2          D         S.sub.1 &amp; D                          (S.sub.1 &amp; D) ⊕ S.sub.2______________________________________0        0     0         0     00        0     1         0     00        1     0         0     10        1     1         0     11        0     0         0     01        0     1         1     11        1     0         0     11        1     1         1     0______________________________________ 
    
     For example, to generate display memory bitmap 108, the program specifies the bit string &#34;01101100&#34; (hexadecimal 6C H ) as the logical operation to be performed. The logical operation 6C H  specifies the result for each of the eight possible combination of values for S 1 , S 2 , and D. Table II shows the values of the input bitmaps and the intermediate and final results achieved by the Boolean function corresponding to logical operation 6C H . 
     
                       TABLE III______________________________________for h = 0, Heightfor w = 0, Width   D[h,w] = (S.sub.1 [h,w] &amp; D[h,w]) ⊕ S.sub.2 [h,w]endforendfor______________________________________ 
    
     Table III illustrates pseudocode for the bitBLT routine that implements the logical operation 6C H . The variable Height represents the number of rows in each bitmap and the variable Width represents the number of columns of bits in each bitmap divided by the word width. In this example, the width of each bitmap is assumed to be an integral number of computer words. 
     
                       TABLE IV______________________________________                   MOV   h, height   outerloop:      MOV   w, width   innerloop:      MOV   di, S.sub.1 [h,w]                                     common                   MOV   si, S.sub.2 [h,w]                   MOV   dx, D[h,w]logical                 MOV   ax, dioperation-   --              AND   ax, dxspecific                XOR   ax, si                   MOV   D[h,w], ax                   DEC   w                   JNZ   innerloop   common                   DEC   h                   JNZ   outerloop______________________________________ 
    
     Table IV shows Intel 80386 assembly language pseudocode that implements the logical operation 6C H . Typical prior art bitBLT routines may have a separate section of code to implement each of the 256 logical operations. However, some bitBLT routine implementations recognize that a portion of the code is common to all logical operations and a portion of the code is logical operation-specific. As shown in Table IV, the three middle statements are the logical operation-specific code for the logical operation 6C H . In this code, these three statements load the ax register with S 1  bitmap, logically AND the D bitmap into the ax register, and then logically exclusive-OR the S 2  bitmap with the ax register. The five statements preceding and the five statements following the logical operation-specific code control the looping through the bitmaps and are common to all logical operations. 
     To improve performance, prior art bitBLT routines store the logical operation-specific code for each of the 256 logical operations in a table and store just one copy of the common code. When the bitBLT routine is called with a logical operation designation, such as 6C H , the bitBLT routine generates the code to implement the logical operation by retrieving the appropriate logical operation-specific code from the table and combining the retrieved code with the common code. The bitBLT routine then executes the generated code to perform the logical operation. The process of generating the code to execute is referred to as bitBLT compiling. 
     These prior art bitBLT routines generate efficient code at execution time. However, these routines require the storage of 256 logical operation-specific code segments. In addition, it can take considerable programming effort to develop and test these 256 code segments. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method and system for generating efficient code for a bitBLT routine. 
     It is another object of the present invention to provide a method and system developing a bitBLT routine that reduces the of number code segments that need to be stored. 
     It is another object of the present invention to provide an apparatus for performing logical operations on a plurality of bitmaps. 
     These and other objects, which will become apparent as the invention is more fully described below, are obtained by a method and system for generating computer code to implement logical operations to be performed on a plurality of bitmaps. In a preferred embodiment, a Boolean equation is specified having a plurality of terms defined by Boolean operations. Code segments are generated that implement each of the Boolean operations of the terms. When executing a bitBLT routine, a logical operation and a plurality of bitmaps are specified. The bitBLT routine determines which of the generated code segments are needed to implement the specified logical operation. The determined code segments are then retrieved and combined to form the computer code that implements a logical operation. The computer code can then be executed to effect a bitBLT with a logical operation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B are diagrams of a display memory showing the results of various bitBLT operations. 
     FIGS. 1C and 1D are diagrams of the display screen corresponding to FIGS. 1A and 1B, respectively. 
     FIG. 2 is a diagram showing sample source bitmaps of an image of an arrow. 
     FIG. 3 is a flow diagram of a routine to generate the compiled code that is executed by the bitBLT routine. 
     FIG. 4 is a schematic diagram of a hardware implementation of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention provides a method and system for implementing a bitBLT routine which reduces the storage requirements of the routine and provides for more rapid developing of the routine. In a preferred embodiment, a bitBLT routine that accommodates two source bitmaps and a destination bitmap stores 8 code segments and a mapping table, rather than the 256 logical operation-specific code segments used in prior art systems. 
     The present invention recognizes that each of the 256 logical operations can be represented by the following equation: 
     
         F(S.sub.1, S.sub.2, D)=α.sub.0 ·1⊕α.sub.1 ·S.sub.1 ⊕α.sub.2 ·S.sub.2 ⊕α.sub.3 ·D⊕α.sub.4 ·S.sub.1 S.sub.2 ⊕α.sub.5 ·S.sub.1 D⊕α.sub.6 ·S.sub.2 D⊕α.sub.7 ·S.sub.1 S.sub.2 D           Equation 1 
    
     where α 0  . . . α 7  are logical operation-specific coefficients of the equation, where ⊕ represents the Boolean exclusive-OR operator, where · or juxtaposition represent the Boolean AND operator, and where logical 1, S 1 , . . . , S 1  S 2  D are the 8 terms of the equation referred to as terms 0 through 7. 
     Each one of the 256 logical operations can be represented by Equation 1 with a unique set of coefficients. For example, the logical operation 6C H  can be represented by the set of coefficients α 0  =0, α 1  =0, α 2  =1, α 3  =0, α 4  =0, α 5  =1, α 6  =0, α 7  =0 (00100100 2  or 24 H ). The following equation shows the logical operation 6C H  as expressed in Equation 1 with the coefficients 24H: 
     
         F6C.sub.H (S.sub.1, S.sub.2, D)=0·1⊕0·S.sub.1 ⊕1·S.sub.2 ⊕0·D⊕0·S.sub.2 ⊕1·S.sub.1 D⊕0·S.sub.2 D⊕0·S.sub.1 S.sub.2 D                                                 Equation 2 
    
     Since the value 0 logically ANDed with any other value results in 0, the above equation can be simplified to the following equation: 
     
         F6C.sub.H (S.sub.1, S.sub.2, D)=S.sub.2 ⊕S.sub.1 D     Equation 3 
    
     For each of the 256 logical operations, there is a unique set of coefficients which generate the logical operation. 
     In a preferred embodiment, the present invention stores 8 code segments, one for each term in Equation 1, and stores the coefficients to each of the 256 logical operations into a mapping table called a coefficient table. When the bitBLT routine receives a logical operation, it retrieves the coefficients corresponding to the logical operation designator from a coefficient table, retrieves the code segments corresponding to the terms with a coefficient equal to 1, and combines the retrieved code segments with common code to generate the compiled code. 
     
                       TABLE V______________________________________CodeSeg[0]           NOT axCodeSeg[1]           XOR ax,diCodeSeg[2]           XOR ax,siCodeSeg[3]           XOR ax,dxCodeSeg[4]           MOV bx,di                AND bx,si                XOR ax,bxCodeSeg[5]           MOV bx,di                AND bx,dx                XOR ax,bxCodeSeg[6]           MOV bx,si                AND bx,dx                XOR ax,bxCodeSeg[7]           MOV bx,di                AND bx,si                AND bx,dx                XOR ax,bx______________________________________ 
    
     Table V shows eight Intel 80386 assembly language code segments which correspond to each of the eight terms of Equation 1. The common code is the same as used in prior systems, except that the ax register is cleared before the logical operation specific-code is executed. 
     Continuing with the above example, when the bitBLT routine receives the logical operation 6C H , it uses the 6C H  as an index into the coefficient table to retrieve the value 24 H , which represents the set of coefficients to be applied to Equation 1. The bitBLT routine then retrieves the code segments for term 2 and term 5 (the coefficient 24 H  indicating that coefficients α 2  and α 5  are set to 1) and combines those code segments with the common code to form the compiled code. Table VI shows the logical operation-specific code generated for logical operation 6C H . 
     In a preferred embodiment, the present invention also stores eight alternate code segments, one for each term in Equation 1. When the bitBLT routine retrieves code segments, the first code segment of the complied code is an alternate code segment. The alternate code segments are optimized to be the first code segment executed as part of the compiled code. In particular, the first code segments store the value of the term into the ax register, rather than exclusively ORing the value of the term into the ax register. Thus, it is not necessary to load the ax register with a zero value in the common code, except when the coefficients are &#34;00000000&#34; which indicate that none of the code segments are to be used and the result is 0. Also, the use of alternate code segments produces smaller compiled code and improved performance. Alternate Table V shows Intel 80386 assembly language code for the eight alternate code segments. 
     
                       ALTERNATIVE TABLE V______________________________________AltCodeSeg[0]      MOV ax,OFFFFhAltCodeSeg[1]      MOV ax,diAltCodeSeg[2]      MOV ax,siAltCodeSeg[3]      MOV ax,dxAltCodeSeg[4]      MOV ax,di              AND ax,siAltCodeSeg[5]      MOV ax,di              AND ax,dxAltCodeSeg[6]      MOV ax,si              AND ax,dxAltCodeSeg[7]      MOV ax,di              AND ax,si              AND ax,dx______________________________________ 
    
     
                       TABLE VI______________________________________CodeSeg[2]      [     XOR         ax,si                 MOV         bx,diCodeSeg[5]      us,5  AND         bx,dx                 XOR         ax,bx______________________________________ 
    
     FIG. 3 is a flow diagram of a routine to generate the compiled code that is executed by the bitBLT routine. This routine inputs a logical operation and generates the compiled code which implements the logical operation. Table VI shows the compiled code that is generated when the logical operation is 6C H . The routine uses the common code, the code segment table, and the coefficient table. In step 401, the routine retrieves the coefficients from the coefficient table indexed by the logical operation. The coefficient table contains one entry for each of the 256 logical operations. Each entry contains the coefficients that implement the logical operation for Equation 1. 
     
                       TABLE VII______________________________________      MOV h, heightouterloop: MOV w, widthinnerloop: MOV di,S.sub.1 [h,w]  Before      MOV si,S.sub.2 [h,w]  Common      MOV dx,D[h,w]         Code      MOV ax,0      XOR ax, si            Logical      MOV bx, di            Operation      AND bx, dx            6C.sub.H Code      XOR ax, bx      MOV D[h,w], ax      DEC w                 After      JNZ inner loop        Common      DEC h                 Code      JNZ outer loop______________________________________ 
    
     In step 402, the routine retrieves the Before Common Code as shown in Table VII and stores that code as part of the compiled code. In steps 403-408, the routine loops, determining whether each retrieved coefficient is a 0 or a 1. If the coefficient is a 1, then the routine retrieves the corresponding code segment from the code segment table of Table V and adds the retrieved code segment to the compiled code. In step 403, the routine initializes index i to 0. Index i is used to reference the coefficients and corresponding code segments. In step 404, if coefficient α i  is equal to 1, then the code segment for that coefficient is to be retrieved and the routine continues at step 405, else the routine continues at step 407. In step 405, the routine retrieves the code segment corresponding to coefficient α i  from the code segment table. In step 406, the routine adds the retrieved code segment to the compiled code. In step 407, the routine increments index i to point to the next coefficient. In step 408, if index i equals 8, then all the coefficients have been processed and the routine continues at step 409, else the routine loops to step 404 to check the next coefficient. In step 409, the routine retrieves the After Common Code as shown in Table VII and adds it to the compiled code. The routine then returns. 
     
                       TABLE VIII______________________________________for α = 0, 255logical.sub.-- op = 0for S.sub.1 = 1, 0for S.sub.2 = 1, 0for D = 1, 0   logical.sub.-- op =            logical.sub.-- op * 2+(α.sub.0 ⊕ α.sub.1            S.sub.1 ⊕            α.sub.2 S.sub.2 ⊕ α.sub.3 D            ⊕α.sub.4 S.sub.1 S.sub.2 ⊕            α.sub.5 S.sub.1 D ⊕ α.sub.6 S.sub.2 D            ⊕ α.sub.7 S.sub.1 S.sub.2 D)endforendforendforCoefficient.sub.-- Table[logical.sub.-- op] = αendfor______________________________________ 
    
     In one embodiment, the coefficient table is generated by the algorithm shown in Table VIII. This algorithm generates a unique 8-bit logical operation for each of the 256 possible coefficients and then stores the coefficient in the coefficient table indexed by the logical operation. When the logical operation-specific code is generated, the logical operation is used as an index into the coefficient table to retrieve the corresponding coefficient. 
     In a preferred embodiment, the Before Common Code of Table VII is optimized to load only those bitmaps which are actually used by the logical operation-specific code. For example, if the logical operation 3C H  is specified, then the coefficient 60 H  is retrieved from the coefficient table. The resulting minimized equation is: 
     
         F3C.sub.H (S.sub.1, S.sub.2, D)=S.sub.1 ⊕S.sub.2 
    
     Since this equation does not use the D bitmap, the Before Common Code does not need to load the bits from the D bitmap into the dx register. The Before Common Code can thus be tailored so that the bits from the D bitmap are only loaded when coefficients 5, 6, or 7 are set. Similarly, the bits from the S 1  and S 2  bitmaps need only be loaded when their corresponding coefficients are set. In addition, typical bitBLT routines check the validity of the S 1 , S 2 , and D bitmaps before executing the compiled code. If, however, a logical operation does not require the loading of the S 1  and S 2  bitmaps, then this validity checking does not need to be performed. The validity checking of the D bitmap typically needs to be performed as it is accessed when storing the result in the After Common Code. 
     FIG. 4 is a schematic diagram of a hardware implementation of the present invention. The hardware includes logical operation register 501, coefficient table read-only memory (ROM) 502, parallel-to-serial shift registers 503, 504, and 505, AND gates 511-517, parity generator 520, and serial-to-parallel shift register 521. The logical operation register 501 outputs (α 0  . . . α 7 ) address the coefficient table ROM 501, which is a 256×8 bit ROM. The coefficient table ROM contains the set of coefficients for Equation 1 generated by the pseudocode of Table VIII at the address corresponding to the logical operation. The dataline α 0  is input to the parity generator 520 and datalines α 1  through α 7  are input to AND gates 511 through 517, respectively. The dataline S 1  from shift register 503 is input into AND gates 511, 514, 515, and 517. The dataline S 2  from shift register 504 is input into AND gates 512, 514, 516, and 517. The dataline D from shift register 505 is input into AND gates 513, 515, 516, and 517. The output from the AND gates 511 through 517 are input to the parity generator 520. The output of the parity generator 520 is input into the shift register 521. 
     In operation, logical operation register 501 is loaded with the logical operation to be performed. Coefficient table ROM 502 translates the logical operation to the corresponding coefficients. Shift registers 503, 504, and 505 are loaded with data from bitmaps S 1 , S 2 , and D, respectively. The AND gates 511-517 generate the results of seven of the terms of Equation 1 which are input into parity generator 520. The eighth term is generated by the α 0  data line which is input directly into the parity generator 520. The parity generator 520 performs an equivalent of the logical exclusive-OR operations of Equation 1. The output of parity generator 520 is input into shift register 521. The logical operation is performed by sequentially loading shift registers 503, 504, 505 with data from bitmaps S 1 , S 2 , and D, respectively. The shift registers 503, 504, 505 are then shifted sequentially to datalines S 1 , S 2 , and D. For each shift of the shift registers 503, 504, 505, the output of parity generator 520 is the result of the logical operation stored in the logical operation register 501. The output of the parity generator 520 is input into the shift register 521, which stores the result of the logical operation, which can then be written to a display memory. In an alternate embodiment, the coefficient mapping is performed in software, and the coefficient table ROM 502 is not needed. Rather, the logical operation register 501 is loaded with the coefficients directly. 
     Although the function of Equation 1 is used in a preferred embodiment, one skilled in the art will appreciate that other equations of eight terms could be used as well. For example, the following equation: 
     
         F(S.sub.1, S.sub.2, D)=λ.sub.0 S.sub.1 S.sub.2 D+λ.sub.1 S.sub.1 S.sub.2 D&#39;+λ.sub.2 S.sub.1 S.sub.2 &#39;D+λ.sub.3 S.sub.1 S.sub.2 &#39;D&#39;+λ.sub.4 S.sub.1 &#39;S.sub.2 D+λ.sub.5 S.sub.1 &#39;S.sub.2 D&#39;+λ.sub.6 S.sub.1 &#39;S&#39;.sub.2 D+λ.sub.7 S.sub.1 &#39;S.sub.2 &#39;D&#39;                                      Equation 4 
    
     where λ 0  . . . λ 7  represent the coefficients, where + represents the Boolean inclusive-OR operator, where &#39; indicates the Boolean complement operator, and where juxtaposition indicates the Boolean AND operator. A code segment is generated for each term of Equation 4. Using Equation 4, no translation is necessary to generate the coefficients. The coefficients correspond to the logical operation. When using Equation 4, similar optimizations can be used to determine whether to load certain bitmaps. 
     Although the present invention has been described in terms of preferred embodiments, it is not intended that the invention be limited to these embodiments. For example, the present invention can be used with color bitmaps (multiplanar) by applying the compiled code to each plane. In addition, one skilled in the art would recognize that the methods of the present invention can be applied to bitBLT routines that use more than two source bitmaps. For example, a bitBLT routine with three source bitmaps would use an equation of 16 terms and store 16 code segments, rather than the 65,536 logical operation specific-code segments that prior art methods would employ. Modifications within the spirit of the invention will be apparent to those skilled in the art. The scope of the present invention is defined by the claims that follow.