Abstract:
With electric valves (7) having several series-connected thyristore (T1 . . . Tn; T1&#39; . . . Tn&#39;), individual thyristors may become defective, so that they do not withstand the blocking voltage applied to them. For the simplified checking of such defects, a process is specified which does not require any individual monitoring on the spot, i.e. for high potential. For this purpose, in the blocked state of the valve (7), all thyristors of one current direction, apart from at least one thyristor being tested, are triggered within a predeterminable triggering interval. If a valve current (i R ) then flows, an indicating and registering device (A1 . . . An) indicates in which thyristor stage the defect has occurred. This status check is preceded by a preliminary test in which it is checked whether all thyristor triggering channels are in order. All thyristors are triggered in this test. If no valve current (i R ) occurs, a triggering channel fault signal (S U0 ) is generated.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a new and improved process for fault monitoring of an electric valve containing at least two series-connected thyristors. 
     According to a process for fault monitoring of an electric valve such as known, for example, from the GEC Journal of Science and Technology, Vol. 48, No. 3, 1982, pp. 135-140, a 12-pulse bridge circuit for 270 kV, 1852 A (500 MW), 125 thyristors per valve are connected in series. Two 4-kV thyristors of 56 mm diameter are connected in parallel on each thyristor level. With 24 valves, the thyristor failure rate during 25 a is to be less than 0.1 per year. The triggering signals for each thyristor are transmitted via optical waveguides. The fault status of each thyristor level is indicated there by a luminescent diode. It is monitored whether the thyristors still are able to block and whether a break-over diode repeatedly responds. Such a response of the break-over diode indicates a fault in the triggering channel; the information can be transmitted to the remote control station at ground potential. 
     Owing to the generation of the fault status signals at high potentialand the double conversion of the signals (electrical-optical-electrical), this monitoring system is expensive and too complex, in particular for magnetically triggered valves where triggering is via pulse transformers. Optical waveguides for information transmission may break. 
     In thyristor protection circuits such as known, for example, from the German Company Periodical &#34;BBC Nachrichten&#34; (BBC News), Vol. 59, No. 3/4 (1977), pages 152 through 158, break-over diodes, so-called BOD elements are utilized. 
     For actuating thyristors, it is known to use a triggering pulse control unit such as known, for example, from IFAC Control In Power Electronics and Electrical Drives, Lausanne, Switzerland, 1983, pages 493 through 500, in particular page 500, FIG. 5. 
     SUMMARY OF THE INVENTION 
     Therefore, with the foregoing in mind it is a primary object of the present invention to provide a new and improved process for fault monitoring of electrical valves containing at least two thyristors and which process is not afflicted with the drawbacks and limitation of the prior art processes. 
     Another significant object of the present invention is directed to a new and improved process for fault monitoring of electrical valves containing at least two series-connected thyristors and which process can be carried out using a considerably simpler manner of fault-indicating signal transmission as compared to the prior art processes. 
     A further important object of the present invention is directed to a new and improved process for fault monitoring of electrical valves containing at least two series-connected thyristors and which process does not require multiple signal conversion on special signal lines for transmitting the fault status from each thyristor stage or level to a control station at ground potential. 
     Now in order to implement these and still further objects of the invention, which will become more readily apparent as the description proceeds, the fault monitoring process of the pressent development is manifested, among others things, by the steps that, in a blocked state of the electric valve, the at leat two series-connected thyristors associated with one current direction are triggered with the exception of at least one thyristor within a pedetermined triggering interval. 
     It is one advantage of the inventive process that the elimination of signal lines dispenses with one source of faults. This consequently achieves a higher availability of the valve. By avoidance of the complex process of thyristor monitoring on the spot, and thus of the expenditure for signal transmission from high potential to ground, costs are also saved. Instead of many individual measurements (thyristor voltages), a single measurement (valve current) suffices. 
     In an advantageous further development of the inventive process, it is checked whether all thyristor triggering channels are in order in a preliminary test before the status monitoring of an individual thyristor or a thyristor stage is non-periodically monitored. In the blocked state of the electric view, the at least two thyristors associated with the one current direction are then triggered and a triggering channel fault signal is generated if no valve current subsequently flows through the electric valve. In this manner, all thyristors can be monitored in a simple way for any triggering channel defects. This means no increased voltage stress of the thyristors in a normal case, but only in the case of a triggering channel defect. Since the check is not carried out periodically and the fault is immediately detected, this increased stress can be tolerated. 
     Preferably, in the presence of at least one break-over element having a predetermined break-over voltage, the at least one thyristor or thyristor stage is triggered when the voltage at such thyristor or thyristor stage exceeds the break-over voltage. Such triggering may also take place at a test voltage smaller than the break-over voltage of the break-over element. In this manner, the individual overvoltage protection of the thyristors or thyristor stages enable carrying out the status monitoring operation for the intact thyristors without any risk thereto. 
     Advantageously a triggering channel fault signal is generated if the harmonic currents of the valve current through the electric valve exceeds a predetermined limiting value for such harmonic current. This has the advantage that, with a valve connected in series with a capacitor, all triggering channels can be checked for faults in the triggered valve state, i.e. periodically. As soon as, in the triggered state, a triggerIng channel is defective (no regular triggering pulse at a thyristor), a periodic break-over element triggering of the defective thyristor takes place, the valve triggering moment being delayed altogether slightly. This results in the excitation of harmonic currents of natural frequency of the capacitor bank, which is switched by the valve, in some cases in all three valve branches of a three-phase system. To determine periodic break-over element triggering, all that is then required is analysis of the current of one of the three alternating current phases. 
     In a further advantageous manner of carrying out the inventive process, the triggering of the at least two thyristors takes place at a test triggering angle according to the equation: 
     
         α.sub.p =180°-arc sin ((k·n.sub.p ·U.sub.K)/√2·U)), 
    
     wherein: 
     k is a safety factor &lt;1, in particular=0.7, n p  the number of deliberately not triggered thyristors, 
     U K  the break-over voltage of a break-over element, and 
     U an effective no-load voltage. 
     There is thus achieved the beneficial effect that, in a valve connected in series with a choke, undesirable valve triggerings, i.e. those resulting in false alarms, are reliably avoided in the range above the break-over voltage of a break-over element. 
     In the case of an electric valve which is operated in connection with a constantly charged capacitor bank, the thyristors or thyristor stages are selectively triggered at a test triggering angle according to the equation: 
     
         α.sub.p =90°+arc cos (1-ΔU/(√2·U)), 
    
     wherein, U is a positive effective no-load voltage and ΔU is a minimum triggering voltage, or the equation: 
     
         α.sub.p =270°+arc cos (1-ΔU/(√2·U)), 
    
     wherein U is a negative effective no-load voltage and ΔU the minimum triggering voltage. 
     In a preferred further development of the inventive process, each thyristor or thyristor stage is checked by a cyclic interchange or sequence of the triggering pulses such that at least one thyristor or thyristor stage does not receive a triggering pulse in successive checking cycles. There is thus made possible a complete check of all n thyristor levels within n/2 periods of the system voltage with a valve in series connection with a choke and within n perios with a valve in series connection with a capacitor. 
     Preferably, the duration of the aforementioned triggering pulses is in the range of 5 ms to 200 ms. Such short-time triggering pulses ensure that no undesirable triggering can occur in the range of valve voltage&gt;break-over voltage. 
     In the case of magnetically triggered electric valves or thyristor switches, a triggering pulse is not delivered until the electric valve voltage is at least 100 V and smaller than k·n p  ·U K , wherein k is a safety factor smaller than 1, in particular equal to 0.7, n p  represents the number of deliverately not triggered thyristors or thyristor stages, and U k  is the break-over voltage of the respective break-over element. There is thus enabled a particularly simplified status monitoring. Determining the moment at which to deliver the test trigger is particularly simple if the capacitor voltage in the blocked state of the valve always has approximately the same value. This is the case if the capacitors are periodically recharged to the peak value of the system voltage via the thyristors of the correct current direction (dependent on the polarity of the capacitor voltage). In this case, the test trigger pulse can be derived from the phase relationship of the system voltage. The valve voltage need no longer be measured inorder to determine the correct triggering moment. 
     In the case of status monitoring an electric valve in series connection with a capacitor, there is obtained the advantage that the electric valve can be a thyristor switch in which each thyristor is connected in anti-parallel with either a further thyristor or a diode, such as in so-called semi-controlled electrical valves. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be better understood and objects other than those set forth above will become apparent when consideration is given to the following detailed description thereof. Such description makes reference to the annexed drawings wherein throughout the various figures of the drawings there have been generally used the same reference characters to denote the same or analogous components and wherein: 
     FIG. 1 shows a test circuit for fault monitoring of an electric valve with voltage-dependent protection devices for each thyristor level or stage of the valve, 
     FIG. 2 shows the protective triggering device used in the test circuit according to FIG. 1, 
     FIG. 3 shows voltage conditions in the series connection of the electric valve or thyristor switch and a choke, 
     FIG. 4 shows signal representations a-c of the AC voltage and of the triggering pulses for a series connection according to FIG. 3, 
     FIG. 5 shows voltage conditions in the series connection of the electric valve or thyristor switch and a capacitor, 
     FIG. 6 shows signal representations a-b of the AC voltage and of the triggering pulses for a series connection according to FIG. 4 with positive capacitor voltage, 
     FIG. 7 shows signal representations a-b corresponding to FIG. 6 with negative capacitor voltage, and 
     FIG. 8 shows a signal representation of the AC voltage at an AC switch with harmonics which are caused by periodic triggering of a break-over element of the protective device according to FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Describing now the drawings, it is to be understood that only enough of the construction of the test circuit for fault monitoring of an electrical valve has been shown as is needed for those skilled in the art to readily understand the underlying principles and concepts of the present development, while simplifying the showing of the drawings. Turning attention now specifically to FIG. 1 of the attached drawings, the test circuit illustrated therein by way of example and not limitation will be seen to comprise an electric valve or a thyristor switch or controller 7 of a static reactive-power compensation system for a single-phase AC system with an AC voltage source 1, which can be connected to ground potential via a reactor 3, a current transformer 6, for the detection of a valve current i R , and the electric valve 7. The reactor 3 can, as connected by broken lines, be an inductive resistor or a choke 2 or a capacitor or a capacitor bank 4. 
     The AC switch 7 has n unipolar, series-connected thyristors T1, T2 . . . Tn, a thyristor T1&#39;, T2&#39; . . . Tn&#39; being connected in antiparallel with each of these thyristors. In the event that the reactor 3 is a capacitor 4, instead of an antiparallel thyristor, an antiparallel diode may be used. 
     Every two such antiparallel-connected semi-conductor components form a thyristor stage which is connected to a voltage-dependent protective device 8, shown more closely in FIG. 2. If the AC voltage at a thyristor stage exceeds a predeterminable value, the break-over voltage U K , cf. FIG. 7, a protective triggering signal is applied to the control inputs of the two thyristors of the thyristor stage. The normal triggering of the thyristors T1 . . . Tn, T1&#39; . . . Tn&#39; of the thyristor switch 7 takes place by means of a triggering pulse control unit 16, which is common to all and at ground potential, and the output signal S16 of which is applied to first inputs of n AND gates U1&#39;, U2&#39; . . . Un&#39;. Each thyristor stage is assigned an AND gate, the output of the respective AND gate being connected to the control signal inputs of the two thyristors of the thyristor stage via optical waveguides and an optical signal converter (not shown). Second, negated inputs of the AND gates U1&#39; . . . Un&#39; are connected to succesive outputs 1 . . . n of a shift register 18. The utputs 1 . . . n of the shift register 18 are, furthermore, in each case connected to a first input of an AND gate U1, U2 . . . Un, the output signals S U1  . . . S Un  of which are applied to indicating and registering devices A1 . . . An. Furthermore, a first output, denoted by 0, and a second output, denoted by 0&#39;, of the shift register 18 are connected via an OR gate 32 to a first input of an AND gate U0, the output signal S U0  of which is applied to an indicating and registering device A0. 
     The output signal S6 of the current transformer 6 is monitored in an AC comparator 17 for exceeding of a predeterminable current limit value i G  of preferably ≧1% of the nominal current of i R . The output of the AC comparator 17 is connected to a negated second input of the AND gate U0 and to non-negated second inputs of the AND gates U1 . . . Un. Furthermore, the output of the triggering pulse control unit 16 is connected to non-negated third inputs of the AND gates U0 . . . Un. The output of the current transformer 6 is, furthermore, as indicated by broken lines, connected to the input of the indicating and registering device A0 via a bandpass filter 9, a filter current comparator 10, an integrator 11 and a further comparator 12. The bandpass filter 9 is tuned to a pass frequency ##EQU1## where L=inductance of the damping choke (not shown) in the supply line to the thyristor switch and C=capacitance of the capacitor bank 4 (per phase with a multiphase AC voltage source 1). On the output side, the bandpass filter 9 delivers a harmonics-containing filter current I n  where n=f/f N , f N  =50 Hz=system frequency. This filter current I n  is monitored in the filter current comparator 10 for exceeding of a predeterminable filter current limit value I nG  of preferably 10% of the nominal current of i R . The integrator 11 serves to delay the output signal of the filter current comparator 10 by a predeterminable period, in order to suppress a transient response of the filter current comparator 10. The comparator 12 monitors the output signal of the integrator 11 for exceeding of a predeterminable total filter current limit value I nGS , which characterizes a periodic triggering of thyristors of the AC switch 7 by the protective triggering device 8 and is indicated in the indicating and registering device A0. 
     The AC voltage U R  of the AC voltage source 1 is applied to an AC voltage zero detector 13 via a voltage transformer 5. In the event that the reactor 3 is a choke 2, an AC voltage zero detector 13 whose output signal S13 assumes the value &#34;1&#34; at every voltage passage through zero is used. If the reactor 3 is a capacitor 4, an AC voltage zero detector 13 is used whose output signal S13 only assumes the value &#34;1&#34; if U R  =0 and, simultaneously, dU R  /dt&gt;0, i.e. at every 0° passage through zero. 
     The output of the AC voltage zero detector 13 is connected to the input of the triggering pulse control unit 16, via a delay element 14 with predeterminable delay T p  and an electronic switch 15 and is also connected to the clock input of the shift register 18 and to a first input of an AND gate 33. The delay T P  corresponds to a test triggering angle α P , which defines the test triggering moment for the thyristors T1 . . . Tn, T1&#39; . . . Tn&#39;. The test triggering moment is to be chosen such that a valve voltage applied at the thyristor switch 7 is U 7  &lt;k·n P  ·U K , k=safety factor &lt;1, preferably=0.7, n P  =number of the intentionally not-triggered thyristors, U K  =protective voltage of a thyristor stage. 
     If the thyristor switch 7 is connected in series with a capacitor 4, it must be additionally ensured that sufficient triggering voltage is available, preferably a minimum triggering voltage of 100 V. In this respect, the following relationship applies for the test triggering angle α P  : ##EQU2## where U C  =capacitor voltage, U=effective no-load voltage U R (max) /2 (phase-phase), ΔU=minimum triggering voltage, α=0 for U=0 (beginning of a system period). 
     If the thyristor switch 7 is connected in series with a choke 2, the normal range for a triggering angle α is given by the relationship: 90°&lt;α&lt;180°. The following applies for the test triggering angle α P  : ##EQU3## Table 1 gives the valve voltage U 7  at the thyristor switch 7, the test triggering angle α P  and the valve current i R  for the status monitoring of a thyristor switch 7 in series with a choke 2, for a nominal current of i R  =2560·√2 A. 
     
                       TABLE 2______________________________________    U.sub.7  α.sub.P                          Safety MarginExample  kV       Electrical Degrees                          ms______________________________________1        16.3      95          1.52        7.29      98          2.03        4.86     100          2.5______________________________________ 
    
     Table 2 gives the valve voltage U 7 , the test triggering angle α P  and the safety margin for the status monitoring of a thyristor switch 7 in series with a capacitor 4. 
     
                       TABLE 1______________________________________  α.sub.P i.sub.R  Electrical Degrees                AEx-   U.sub.7        1 blocking                  2 blocking                          1 blocking                                  2 blockingample kV     thyristor thyristors                          thyristor                                  thyristors______________________________________1     16.3   173       166      31      1272     7.39   164       147     128      5363     4.86   156       125     293     1330______________________________________ 
    
     The protective voltage U K  was 4 kV. The triggering pulse must disappear at a sufficiently early time (about 500 μs) before expiry of the safety margin. 
     During the test, the switch 15 is in the position indicated by broken lines, otherwise in the position indicated by solid lines, the presetting of the normal triggering angle α coming from a control device (not shown), as is known for example for German Patent Specification, 2,653,333. The triggering angle α can be used to adjust with infinite variability the reactive power of the static reactive-power compensator. 
     19 denotes an RS bistable element, to the setting input of which a test start signal P is applied by an operator or by a master control device (not shown). The resetting input of the RS bistable element 19 is connected to the n output of the shift register 18 via a delay element 31 with predeterminable time delay of, for example, a quarter period of the system voltage. The delay is chosen such that a fault in the nth thyristor stage can still be reliably indicated and stored. The Q output signal of the RS bistable element 19 is applied on the one hand via a monostable, non-retriggerable bistable element 20 to a second input of the AND gate 33, and on the other hand to the switch 15, which is in the position indicated by broken lines while Q=&#34;1&#34;. The output of the AND gate 33 is connected to a setting input S of the shift register 18. The duration of the output signal &#34;1&#34; of the bistable element 20 is chosen such that only one signal S13=&#34;1&#34; can set a &#34; 1&#34; in the shift register 18 via its setting input. The Q output of the RS bistable element 19 is connected to the resetting input of the shift register 18. Q=&#34;1&#34; sets the output 0 . . . n of the shift register 18 to &#34;0&#34;. 
     In FIG. 2, identical parts are provided with the same reference symbols as in FIG. 1. 21-28 denote diodes, 29 denotes an ohmic resistance and 30 denotes a break-over diode with a predeterminable break-over voltage U K  of, for example, 4 kV. If the break-over voltage U K  is exceeded, the voltage breaks down at the break-over diode 30 and the break-over diode becomes conductive. 
     In the event that the anode of T1 and the cathode connected to it of T1&#39; are positive, the cathode of T1 and the anode connected to it of T1&#39; are negative and the voltage at this thyristor stage is &gt;U K , the control electrode of T1 is supplied with biasing current via the components 21, 25, 29, 30, 38 and 23, and thus the thyristor T1 is triggered. 
     With opposite potential at the thyristor stage, the control electrode of T1&#39; is supplied with biasing current via the components 24, 26, 29, 30, 27 and 22, and thus the thyristor T1&#39; is triggered. 
     In the following, the function of the test circuit is to be explained in connection with FIGS. 3-8. In FIGS. 4, 6 and 7, voltage U is plotted on the ordinate and time t is plotted on the abscissa. FIGS. 4, 4, 6 and 7 show triggering signals S16 as a function of time t. 
     Testing of a valve 7 in series connection with a choke 
     Testing is carried out sporadically; with a thyristor switch 7 in series with a choke 2 only when the normal control circuit is interrupted for the duration of monitoring and the valve is blocking, in particular at night. 
     Preliminary tests (function of the triggering channels) 
     Before a status check of the individual thyristor stages is carried out, it is established in a preliminary test whether all triggering channels are in order, i.e. whether all thyristors in one current direction trigger at the triggering moment. Then a current has to flow through the valve 7 for approximately half a system period. The preliminary test is explained in connection with FIGS. 3 and 4, a choke 2 being connected in series with the valve 7 and the AC voltage U R  being equal to the valve voltage U 7 . To initiate the preliminary test, a short test start signal P is applied to the setting input S of the RS bistable element 19. This makes Q=&#34;1&#34;, and causes a &#34;1&#34; signal to be applied to the output of the bistable element 20. If then a signal S13=&#34;1&#34; arrives at the shift register 18 from the AC voltage zero detector 13, for example when there is a 0° zero passage at moment t 0 , a &#34;1&#34; is set in the shift register, applied to its 0 output and thus to the first input of the AND gate U0. With Q=&#34;1&#34;, the switch 15 is directed into the position illustrated by broken lines. After a period Tp, corresponding to the triggering angle α p , the triggering pulse control unit 16 delivers a triggering signal S16=&#34;1&#34; at moment t x  with a valve voltage U 7  =U.sub. p, cf. FIGS. 4 and 4, to the AND gates U1&#39;-Un&#39; and to the AND gate U0. Since the outputs 1-n of the shift register have the logical value &#34;0&#34; at this moment, the negated, second inputs of the AND gates U1&#39;-Un&#39; are prepared, i.e. at logical &#34;1&#34;, so that the triggering signal S16 triggers all positively biased thyristors T1 . . . Tn, provided that the triggering channels are in order. There then flows a valve current i R , so that the AC current comparator 17 responds. The output signal S17 of the latter assumes the logical value &#34;1&#34; and holds its output signal S U0  at &#34;0&#34; via the negated second input of the AND gate U0. If one of the thyristors T1 . . . Tn has not triggered, no valve current flows, and S U0  =&#34;1&#34; causes a triggering channel fault indication in the indicating and registering device A0 and is stored there. The third input of the AND gate U0 is delayed, in order that no triggering channel fault signal S U0  =&#34;1&#34; can occur between the arrival of the triggering signal S16=&#34;1&#34; and the arrival of the signal S17=&#34;1&#34;. 
     In the event that, instead of the 0° zero passage, the AC voltage zero detector 13 has detected a 180° zero passage at moment t 180 , there is consequently positive potential at the thyristor T1&#39; . . . Tn&#39;, so that these thyristors receive a triggering pulse at the moment t y  with a test voltage -U p , cf. FIG. 4. The zero passage of U R  at the moment t 360  again corresponds to that at the moment t 0 . 
     Both events described are cases of the first voltage zero passage of the preliminary test. With the next, i.e. the second, voltage zero passage of U R , S13=&#34;1&#34; generates a clock signal for the shift register 18, which causes its output 0&#39; to become &#34;1&#34; and all other outputs have the logical value &#34;0&#34;. In this state, the second thyristor half is triggered and checked, i.e. if, for example, the thyristors T1 . . . Tn are triggered during the first voltage zero passage, the thyristors T1&#39; . . . Tn&#39; are triggered during the second voltage zero passage. Thus, a half period of the system AC voltage is required per valve branch for preliminary testing. With intact triggering channels, a small valve current flows during this time. 
     Status check (testing for thyristor defects) 
     The preliminary test is followed by the status check for thyristor defects in the individual thyristor stages. In the voltage range U p  &lt;U K , all thyristors apart from one in each case are briefly triggered by the triggering pulse control unit 16 at the test triggering angle α p . 
     With the third clock pulse S13=&#34;1&#34;, the output 1 of the shift register 18 becomes &#34;1&#34;, while all other outputs have the logical value &#34;0&#34;. This causes the AND gate U1&#39; to block via its negated second input, while the AND gates U2&#39; . . . Un&#39; allow the triggering signals S16=&#34;1&#34; to pass, so that the thyristor stages T2, . . . Tn, Tn&#39;T2&#39; . . . receive triggering pulses, but not the thyristor stage T1, T1&#39;. If the thyristor stage T1, T1&#39; is in order, no valve current i R  flows, otherwise the AC comparator 17 responds and generates, via the prepared AND gate U1, a status error signal S U1  &#34;1&#34;, which is indicated and registered in the indicating and registering device A1. 
     With the subsequent 4th zero passage of U R , and thus 4th clock pulse, the output 2 of the shift register 18 is set to the logical value &#34;1&#34; etc. up to output n, whereby all thyristor stages are successively checked. Once the last output n has assumed the logical value &#34;1&#34;, the shift register 18 is reset via the delay element 31 and the RS bistable element 19 to its original state, in which all outputs 0, 0&#39;, 1 . . . n have the logical value &#34;0&#34;--until a new test. At the same time, the switch 15 is brought into its normal position, indicated by solid lines. 
     A defective thyristor represents a short-circuit. The indicating and registering devices A1 . . . An indicate the thyristor stage in which the short-circuit occurred. Provided that only one thyristor stage is reported defective, in general operation of the valve can be allowed to continue, since usually at least one redundant thyristor stage per valve is provided. Altogether, the status check takes n half-periods for one single-phase valve. 
     With a three-phase system, checking can be carried out in parallel with each phase conductor, so that at most one system period more is necessary for the entire status check. During the period of the preliminary test and the status check, the valve 7 is not available for normal operation. If the valve is intact, no current flows during the status check. 
     Testing of a valve 7 in series connection with a capacitor 
     FIG. 5 shows the voltages with such a circuit. After disconnection, the valve voltage U 7  displays a profile corresponding to a (1-cos ωt) function, cf. for example the Swiss Company Periodical Brown Boveri Mitteilungen (Brown Boveri Information) 3 (1982) pp. 85-89, in particular p. 87. In this case, there is a time domain or triggering time interval d in which the momentary valve voltage U 7  is smaller than the permissible thyristor voltage or smaller than U K , cf. FIG. 7. 
     Preliminary test 
     Method (a); 
     Let us assume that the valve 7 was conductive a short time ago and was blocked. The valve 7 is subsequently briefly triggered in the time domain d described, with U 7  &lt;U K . With intact triggering channels, the valve 7 must trigger and carry the full current for a half period (with semi-controlled valves, for one period), which can take place by monitoring of the valve current i R  in the way described above. This test is possible at any time during normal operation as soon as the valve has been normally blocked by the triggering pulse control unit 16. One period is required for testing. 
     Method (b): 
     This method is based on determination of the fact that, with defective triggering channel, retriggering has to take place via the break-over diode 30 and consequently harmonic current of the natural resonance of the capacitor bank is induced, cf. FIG. 8. This method does not require any intervention in the valve control, but merely presupposes that the valve 7 is switched on for a sufficiently long time (a number of system periods), for reliable recognition. 
     In the event of a periodic protective triggering, the output signal of the comparator 12 has the logical value &#34;1&#34;, so that the indicating and registering device A0 indicates a triggering channel fault. 
     Status check 
     Presupposing that all triggering channels are functioning properly, the status check can be carried out as described before in the same voltage range with U 7  &lt;U K . A maximum of n system periods are required for the check. The check may be made during normal operation as soon as the triggering pulse control unit 16 has effected a normal disconnection of the capacitor bank 4. If thyristors are defective, the check results in current flowing for a full period in each case. 
     Instead of having a common triggering signal supply for both thyristors of a thyristor stage, an individual triggering signal supply may be provided for each thyristor. 
     It goes without saying that the functions described above of the test circuit can be accomplished by a high-speed computer. 
     With a large number of series-connected thyristors, it may be advantageous in the status check not to apply a triggering signal to two test thyristors at the same time. 
     While there are shown and described present preferred embodiments of the invention, it is to be distinctly understood that the invention is not limited thereto, but may be otherwise variously embodied and practiced within the scope of the following claims.