Abstract:
A charge processing circuit which integrates charge at an output node that is representative of an input charge provided at an input node. The circuit includes a precharge path coupled to the input node, the precharge path operable for setting the potential of the input node to a fixed precharge potential prior to introduction of input charge to the input node. A sensing path is coupled to the input and output nodes which is operable for returning the potential of the input node to the fixed precharge potential subsequent to introduction of input charge to the input node. A feedback element has an input coupled to the sensing path and the precharge path, the feedback element operable for setting said fixed precharge potential. In another embodiment there is provided a method of integrating charge at an output node of a charge processing circuit that is representative of input charge provided at an input node. The method includes replenishing charge at the input node; draining charge from the input node; stopping the draining of charge from the input node in response to a feedback element detecting when the input node reaches a fixed precharge potential; introducing an input charge on the input node from a source; draining charge from the input node onto the output node; and stopping the draining of charge from the input node in response to a feedback element detecting when the input node reaches the fixed precharge potential.

Description:
SPONSORSHIP INFORMATION 
     This invention was made in part with funding from the U.S. Air Force under Contract No. F19628-95-C-0002. The government has certain rights in the invention. 
    
    
     BACKGROUND OF THE INVENTION 
     The invention relates to the field of charge integrating devices. 
     Charge generation is necessary whenever CCD signal processing circuitry must interface with voltage-domain signals. A variety of techniques are well known for generating charge packets from voltages. In all of these, an input diffusion is used to provide a source of electrons and the amount of charge that is collected from this source is controlled by either the source potential or the voltages on an initial set of register gates. 
     The surface channel fill-and-spill technique, shown diagrammatically in FIG. 1, is the most commonly used method of charge generation. FIG. 1A is a schematic diagram of a conventional fill-and-spill charge generator circuit  100 , and FIGS. 1B-1E are associated potential diagrams for a second, third, fourth and first phase, respectively. In this approach, the input signal v s  is provided to gate G 2  and a fixed reference level V r  is placed on G 1 . During the fill phase in FIG. 1B, node f g  is pulsed low and charge is injected into the channel regions underneath G 1  and G 2 . During the spill phase in FIG. 1C, f g  is returned to a high potential so that excess charge from the output well spills back. The spill transition occurs rapidly at first, but then slows considerably as it nears completion. The long time constant associated with this spill transition limits the speed at which the fill-and-spill circuit can be operated. In addition to its limited speed, the fill-and-spill technique has the disadvantages that it provides poor linearity and does not perform accurate sampling. 
     Charge-domain signals can be used by non-CCD elements in two ways. The first method, referred to as destructive sensing, involves transferring the charge packet onto a receiving element. In this case, the charge packet is consumed by the operation. The second method, referred to as nondestructive sensing, involves creating a separate representation of the charge packet, without altering the original, so that multiple nondestructive operations can be performed on the same charge packet. 
     A schematic diagram of a conventional nondestructive floating gate amplifier circuit  200  is illustrated in FIG.  2 A. FIGS. 2B-2E are associated potential diagrams for a first, second, third and fourth phase, respectively. The circuit includes a sensing gate G 4  within a CCD channel. The sensing gate and the barrier that precedes it are not clocked. In preparation for receiving charge, node v g  is preset to the intermediate bias level V h  during the time that the G 4  channel is empty. The precharge is then turned off and v g  is left floating. During the next phase, a charge packet is transferred underneath G 4  by lowering the voltages on G 1  and G 2 . As charge collects underneath G 4 , it couples through the gate-to-channel capacitance and causes the potential on v g  to fall. The clocked v g  waveform is then buffered to form the voltage-domain output v b . 
     This approach to charge sensing has the disadvantage that nonlinearity is introduced by voltage dependence of its various capacitances. It also is not compatible with low voltage operation. because unclocked CCD gates, G 3  and G 4 , reside in the charge transfer path. Finally this circuit provides only a limited signal range before charge collects underneath G 3  and is not sensed by the floating gate. 
     SUMMARY OF THE INVENTION 
     Accordingly, the invention provides a charge processing circuit which integrates charge at an output node that is representative of an input charge provided at an input node. The circuit includes a precharge path coupled to the input node, the precharge path operable for setting the potential of the input node to a fixed precharge potential prior to introduction of input charge to the input node. A sensing path is coupled to the input and output nodes which is operable for returning the potential of the input node to the fixed precharge potential subsequent to introduction of input charge to the input node. A feedback element has an input coupled to the sensing path and the precharge path, the feedback element operable for setting said fixed precharge potential. 
     In accordance with another embodiment of the invention, there is provided a method of integrating charge at an output node of a charge processing circuit that is representative of input charge provided at an input node. The method includes replenishing charge at the input node; draining charge from the input node; stopping the draining of charge from the input node in response to a feedback element detecting when the input node reaches a fixed precharge potential; introducing an input charge on the input node from a source; draining charge from the input node onto the output node; and stopping the draining of charge from the input node in response to a feedback element detecting when the input node reaches the fixed precharge potential. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a schematic diagram of a conventional fill-and-spill charge generator circuit; and FIGS. 1B-1E are associated potential diagrams for a second, third, fourth and first phase, respectively; 
     FIG. 2A is a schematic diagram of a conventional nondestructive floating gate amplifier circuit; and FIGS. 2B-2E are associated potential diagrams for a first, second, third and fourth phase, respectively; 
     FIG. 3A is a schematic diagram of an exemplary embodiment of a DDS charge generator in accordance with the invention; and FIGS. 3B-3E are associated energy level diagrams for a fill phase, a spill phase, a collection phase and a sensing phase, respectively; 
     FIGS. 4A-4E are voltage waveforms for a sample-and-hold portion for the example of a linear input ramp for a DDS charge generator; 
     FIGS. 5A-5D are simplified linear models of a DDS charge generator in accordance with the invention, during each of the four phases: a fill phase, spill phase, collection phase and sensing phase, respectively; 
     FIG. 6A is a schematic diagram of an exemplary embodiment of a DDS wire transfer circuit; and FIGS. 6B-6E are associated energy level diagrams for a fill phase, spill phase, collection phase and sensing phase, respectively; 
     FIG. 7A is a schematic diagram of an exemplary embodiment of a DDS sensing circuit with charge output in accordance with the invention; and FIGS. 7B-7E are associated energy level diagrams for a fill phase, spill phase, collection phase and sensing phase, respectively; 
     FIG. 8A is a schematic diagram of an exemplary embodiment of a DDS charge sensing circuit with voltage output in accordance with the invention; and FIGS. 8B-8E are associated energy level diagrams for a fill phase, spill phase, collection phase and sensing phase, respectively; and 
     FIG. 9A is a schematic diagram of an exemplary embodiment of a DDS D/A and subtraction circuit in accordance with the invention; and FIGS. 9B-9E are associated energy level diagrams for a fill phase, spill phase, collection phase and sensing phase, respectively. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Speed and linearity are improved for a dynamic double-sampling (DDS) technique in accordance with the invention by turning off spill and sensing transitions before they enter subthreshold, and by sensing charge over a time-varying, rather than a static, cascode barrier. At the same time, the useful operating range is increased to nearly the full scale and the impact of spill and sensing clock jitter is reduced. Parasitic capacitor voltage dependence is decreased as well. 
     FIG. 3A is a schematic diagram of an exemplary embodiment of a DDS charge generator  300  in accordance with the invention. FIGS. 3B-3E are associated energy level diagrams for a fill phase, a spill phase, a collection phase and a sensing phase, respectively. The primary voltage-mode portion of this circuit is the sample-and-hold stage  302  formed from capacitors C 1  and C 2  and transistors M 3 , M 4 , M 2 , and M 5 . In addition, there is a feedback amplifier A 1  ( 304 ) that computes the difference between f g  and the fixed reference voltage, V r . A signal-dependent voltage source  306 , which drives the bulk of M 5 , is also included. Other circuit elements operate in the charge domain. 
     A series of precharge transistors connect capacitor C 2  to the diffusion D 1  and a series of sensing transistors connect it to an output well, G 5 . Two gates, both labeled G 24 , are shown on either side of an input diffusion D 2 . These elements are shown as separate gates in the figure, but can also be implemented as a single gate. A secondary static sensing path  308 , formed from G 8 , G 9 , and G 10 , is located between the input diffusion and the output well. Its cascode gate G 8  is tied to the fixed bias V h ′. 
     The following description of circuit operation references three figures. First, energy level diagrams for the charge-domain portion are provided in FIGS. 3B-3E. Second, voltage waveforms for the sample-and-hold portion are included in FIGS. 4A-4D for the example of a linear input ramp. Exemplary voltage waveforms for a DDS charge generator, signals v i , v m , and v f  are shown in FIGS. 4A-4C, and signals f g  and f b  follow identical paths during phases  2  and  4  as shown in FIGS. 4D-4E. 
     FIGS. 5A-5D are simplified linear models of a DDS charge generator in accordance with the invention, during each of the four phases: a fill phase, spill phase, collection phase and sensing phase, respectively. Capacitor C p1 , included in this model, represents parasitic junction and routing capacitances on node v f . Capacitor C p2  models capacitance of the cascode channel, underneath G 24  and G 8 , as well as parasitic junction and routing capacitances on f g . Saturation and subthreshold modes of G 24  are modeled by resistor R 24  in series with a voltage source. The value of this voltage source is (A(V r −f g )−V th ), where A represents the amplifier gain. This simple model provides a qualitatively accurate description of circuit operation. 
     Phase  1  is referred to as the fill phase. Signal v m  tracks the ramp on the analog input v i  and the intermediate node v f  is clamped to the bias V c . When the sensing node f g  is pulled low, to V p , the region underneath G 24  is flooded with charge, and electrons consumed during the previous generation cycle are replenished. The charge packet underneath G 5 , which was generated during the previous cycle, is transferred forward upon the transition of G 1  and G 5  to ground. Charge can not flow backward during this transfer because of the built-in threshold offset between barrier and storage gates. 
     Phase  2  is the spill phase. M 1  is turned off and f g  is left floating. Initially, the voltage on f g  is much lower than that on V r  and the amplifier output f b  is saturated at its high level, V h . After the potential on G 3  is raised and the precharge path is enabled, electrons flow from f g  to the drain, V d . Current flow is determined by the value of (f b −f g ), the gate-to-source voltage of G 24 . Initially, this voltage is large, G 24  is in saturation, and the voltage on f g  rises rapidly. However, as f g  rises, currents are reduced and the process slows considerably. Once f g  approaches V r , the amplifier output falls and G 24  transitions quickly through subthreshold and is shut off. 
     For simplicity in the analysis below, the amplifier is modeled with a linear transfer characteristic, and its saturation at high and low levels is ignored. The value of f g  as a function of time during the spill process is                  f   g          (   t   )       =           V   p                 -     (     t   -   H     )       /     τ   2           +       (         AV   r     -     v   th         A   +   1       )          (     1   -            -     (     t   -   H     )       /     τ   2           )                   H       ≤   t   ≤     2        H   .                 (   1   )                                
     A comparison between the time constant                τ   2     =         R   24          (       C   p2     +     C   2       )         (     A   +   1     )               (   2   )                                
     for this operation with that in a circuit with fb held at a constant value shows that the time constant for the circuit is a factor of (A+1) times faster, and the incomplete portion of the transition in Eq. (1) is attenuated by a factor of e A+1 . 
     To a very good approximation, the precharge path is completely shut off for the remainder of the cycle withfg floating at a level of                  f   g          (     2      H     )       =       (         AV   r     -     v   th         A   +   1       )     .             (   3   )                                
     The final voltage on f b  is                  f   b          (     2      H     )       =       (     A     A   +   1       )            (       V   r     +     v   th       )     .               (   4   )                                
     Nodes v m  and v f  are actively driven during this phase and are not impacted by the transition on f g . At the end of phase 2 they have values 
     
       
           v   m (2 H )= v   i (2 H )= V   s   (5) 
       
     
     and 
     
       
           v   f (2 H )= V   c .  (6) 
       
     
     Variable V s  is used to refer to the analog input v i  at the end of the sampling operation, at time 2H. 
     Phase 3 is referred to as the collection phase. G 5  is raised in anticipation of receiving charge and the precharge path is closed by lowering G 3 . Meanwhile v m , which was previously tied to the analog input, is clamped to ground. The falling transition on v m , 
     
       
           v   m (2 H +Δ)− v   m (2 H )=− V   s ,  (7) 
       
     
     is assumed to complete during a short time, Δ. It couples through C 1  and C 2  onto v f  and f g . Node v f  falls toward a final voltage of 
     
       
           v   f (2 H +Δ)= V   c   −V   s   K   1 ,  (8) 
       
     
     where the unitless constant K 1  is defined as                K   1     =         C   1       (       C   p1     +         C   2          C   p2           C   2     +     C   p2         +     C   1       )       .             (   9   )                                
     The voltage on f g  also falls from its precharged level to                  f   g          (       2      H     +   Δ     )       =         f   g          (     2      H     )       -       V   s          K   1              C   2       (       C   2     +     C   p2       )       .                 (   10   )                                
     The channel capacitance of G 24  is included in C p2  because charge fills this region during both the fill and collection phases. 
     For optimum performance, the amplifier should remain saturated at its high level V h  during the entire collection phase. To assure this condition, the input signal range is limited to                V   s     &gt;       (         v   th       A   +   1       -       V   r       A        (     A   +   1     )           )            (         C   2     +     C   p2           C   2          K   1         )     .               (   11   )                                
     Meanwhile, the potential on G 9  is high and the secondary sensing path through G 8  and G 9  is open. The voltage on f g  rises toward the channel potential underneath G 8 . Eventually G 8  enters subthreshold and current gradually ceases. The rising transition on f g  during this time is described by                    f   g          (   t   )       =           (         f   g          (     2      H     )       -       V   s          K   1            C   2       (       C   2     +     C   p2       )           )                 -     (     t   -     2      H       )       /     τ   3           +       (       V   h   ′     -     v   th   ′       )          (     1   -            -     (     t   -     2      H       )       /     τ   3           )                   2      H       ≤   t   ≤     3      H         ,           (   12   )                                
     where the time constant τ 3  is                τ   3     =         R   8          (       C   p2     +         C   2          (       C   1     +     C   p1       )           C   1     +     C   2     +     C   p1           )       .             (   13   )                                
     The final phase, phase 4, is referred to as the sensing phase. The sensing path is enabled by raising the voltage on G 1 . Immediately thereafter, any charge remaining on f g  from the collection phase is transferred to the output well. The resulting transition on f g  is similar to that during the spill phase. The amplifier output f b  is originally clamped at its high level, V h . Current flow, determined by (f b −f g ), slows as f g  approaches V r . Once fb begins to fall, G 24  transitions rapidly through subthreshold and is shut off. 
     The value of f g  as a function of time is given by                  f   g          (   t   )       =             f   g          (     3      H     )                   -     (     t   -     3      H       )       /     τ   4           +       (         AV   r     -     v   th         A   +   1       )          (     1   -            -     (     t   -     3      H       )       /     τ   4           )                   3      H       ≤   t   ≤     4        H   .                 (   14   )                                
     Like the spill transition, the time constant, τ 4 , for the sensing transition,                  τ   4     =         R   24       (     A   +   1     )            (       C   p2     +         C   2          (       C   1     +     C   p1       )           C   1     +     C   2     +     C   p1           )         ,           (   15   )                                
     is a factor of (A+1) times faster than that of a circuit where the f b  signal is held at a constant bias. 
     Since v f  is floating during phase 4, it rises in response to the level                  v   f          (   t   )       =           v   f          (     3      H     )       +       (         f   g          (   t   )       -       f   g          (     3      H     )         )            C   2         C   1     +     C   p1     +     C   2                       3      H       ≤   t   ≤     4        H   .                 (   16   )                                
     In contrast to f g , the value of v f  at the end of the sensing phase differs from its precharged value. 
     After the sensing path is closed, f g  remains floating for the remainder of the cycle at a level                  f   g          (     4      H     )       =       (         AV   r     -     v   th         A   +   1       )     .             (   17   )                                
     The feedback signal f b  remains at the voltage                  f   b          (     4      H     )       =       (     A     A   +   1       )            (       V   r     +     v   th       )     .               (   18   )                                
     Current I s  is integrated in both the primary and secondary output wells over the sensing and collection phases. The sum of these two packets represents the final output,                Q   o     =       (         f   g          (     4      H     )       -       f   g          (       2      H     +   Δ     )         )            (       C   p2     +         (       C   1     +     C   p1       )          C   2           C   1     +     C   2     +     C   p1           )     .               (   19   )                                
     Combining Eqs. 19, 14 and 10, and retaining only the most significant terms yields the result                Q   o     =         V   s          C   1            C   2         C   1     +     C   2     +     C   p1           +       (         (         AV   r     -     v   th         A   +   1       )          (              -   H     /     τ   4         -            -   H     /     τ   2           )       -       V   p                 -   H     /     τ   2           +       (       V   h   ′     -     v   th   ′       )                 -   H     /     τ   4             )            (       C   p2     +         (       C   1     +     C   p1       )          C   2           C   1     +     C   2     +     C   p1           )     .                 (   20   )                                
     When the assumptions H&gt;&gt;τ 2 , H&gt;&gt;τ 4 , and C p1 =0 apply, the result in Eq. 20 is simplified to                Q   o     =         V   s          (         C   1          C   2           C   1     +     C   2         )       .             (   21   )                                
     This depends only on the sampled input signal and on C 1  and C 2 . Although v th , A, and V r  determine the precharge and sensing values of this circuit in Eqs. 1 and 14, they do not impact the result in Eq. 21 because both precharge and sensing are performed with respect to these same values. Matching between different circuits does not depend critically on any of these parameters. 
     Spill and sensing transitions in a DDS circuit are, to a good approximation, performed to completion and the approximations H&gt;&gt;τ 2 , H&gt;&gt;τ 4  are nearly always valid. The values of f g  at the end of the spill and sensing phases are then equal, speed-dependent distortion can be eliminated, and parasitic capacitance, C p2 , has no impact on the output. 
     None of the bias voltages V d , V c , V h , V r , or V p  influence the result in Eq. 21. Bias V p  should be low enough that charge can fill the region underneath G 24  during the fill operation. Any level, such as ground, that is less than V h −v th  is acceptable. Bias V d  should be high enough that it can remove electrons from f g  during the spill operation. It is typically held at the most positive supply. The level of V c  must be high enough that v f  (3H) remains greater than zero for all possible values of V s . Similarly, the levels of V h  and V r  must be high enough that f g (3H) , given by Eq. 12, remains greater than zero at all times. 
     The DDS charge generator  300  of FIG. 3A includes two blocks: a sample-and-hold front end, and a dynamic double-sampling core. The purpose of the sample-and-hold block is to produce a displacement charge proportional to the analog input voltage, v i . The purpose of the DDS core is to integrate this displacement charge in a CCD output well. The DDS technique can also be applied to a number of other circuit functions, in addition to charge generation. In this approach, the sample-and-hold block is removed and an alternative source of electrons is provided to the DDS input. Examples of such circuits, including wire transfer, charge sensing, charge subtraction, and D/A conversion are presented hereinafter. 
     Wire transfer circuits provide an additional degree of flexibility by allowing charge packets to be transferred between nonadjacent or distant wells, via a metal line. To incorporate dynamic double sampling into a wire transfer circuit, the output from a CCD register is connected to the input of a DDS core as shown in FIG.  6 A. FIG. 6A is a schematic diagram of an exemplary embodiment of a DDS wire transfer circuit  600 . FIGS. 6B-6E are associated energy level diagrams for a fill phase, spill phase, collection phase and sensing phase, respectively. A CCD register  602 , formed by gates G 11 , G 12 , and G 13 , serves as the source of electrons. A DDS core unit  604  reconstructs incoming charge packets by integrating their electrons in a receiving well. 
     The operation of the circuit  600  is similar to that of the DDS charge generator  300 . It is illustrated using the energy level diagrams of FIGS. 6B-6E. During the fill phase, a new supply of charges is provided to the circuit when f g  is pulled low to V p . Gate G 12  is off at this time to prevent charge from flooding backward into the source register. During the spill phase, f g  is reset high to a level of                  f   g          (     2      H     )       =         V   p                 -   H     /     τ   2           +       (         AV   r     -     v   th         A   +   1       )            (     1   -            -   H     /     τ   2           )     .                 (   22   )                                
     The time constant for this transition is                  τ   2     =         R   24          C   p2         (     A   +   1     )         ,           (   23   )                                
     where C p2  represents parasitic junction and routing capacitances on f g  as well as channel capacitance of gates G 24 , G 8 , and G 13 . 
     During the collection phase, a quantity of charge Q s  is transferred onto f g  by lowering the potential of G 11 . The potential on f g  falls in response, and charge flows through the secondary sensing path, into the secondary receiving well G 10 . The voltage on f g  is restored to a high level of                  f   g          (     3      H     )       =         (         f   g          (     2      H     )       +       Q   s       C   p2         )                 -   H     /     τ   3           +       (       V   h   ′     -     v   th   ′       )            (     1   -            -   H     /     τ   3           )     .                 (   24   )                                
     During the sensing phase, charge, any remaining on the wire transfer node, flows through G 24  to the primary output well, G 5 . The final value of f g  is                  f   g          (     4      H     )       =           f   g          (     3      H     )                   -   H     /     τ   4           +       (         AV   r     -     v   th         A   +   1       )            (     1   -            -   H     /     τ   4           )     .                 (   25   )                                
     The time constant for the sensing transition, τ 4 , equals that for the spill transition, τ 2 . 
     Combining Eqs. 22, 24 and 25, and eliminating higher-order exponential terms, yields the resultant charge packet 
     
       
           Q   o   =Q   s −( V   h   ′−v   th   ′+V   p ) e   −H/τ     4     C   p2 .  (26) 
       
     
     In most cases, the approximation H&gt;&gt;τ 4  is valid for this circuit and the first term, which represents a constant offset, is negligible. The result is then identically equal to the input Q s , regardless of any parasitic capacitances. 
     Nondestructive charge sensing is used when a charge packet must be used multiple times. It replicates the original packet in either charge or voltage form, but does not alter the original in the process. The dynamic double-sampling technique can be applied to nondestructive charge sensing. FIG. 7A is a schematic diagram of an exemplary embodiment of a DDS sensing circuit  700  with charge output in accordance with the invention. FIGS. 7B-7E are associated energy level diagrams for a fill phase, spill phase, collection phase and sensing phase, respectively. 
     The circuit  700  is configured by connecting floating gate G 13  from within a CCD register  702 , to the input of a DDS core unit  704 . Input charge is provided by coupling signal electrons from the floating gate channel to the DDS sensing node. These carriers are integrated in a CCD well by the DDS core unit to reconstruct the original charge packet. 
     The operation of circuit  700  occurs as follows. During the fill phase, f g  is pulled low to V p . This serves two purposes. First, it provides a new supply of electrons to the DDS core unit  704 . Second, it presets the floating gate low and forces electrons, underneath it from a previous cycle, to be transferred forward. 
     During the spill phase, f g  is preset high to a level of                  f   g          (     2      H     )       =         V   p                 -   H     /     τ   2           +       (         AV   r     -     v   th         A   +   1       )            (     1   -            -   H     /     τ   2           )     .                 (   27   )                                
     The time constant for this transition is                  τ   2     =         R   24       (     A   +   1     )            (       C   p2     +         C   gc          C   cs         (       C   gc     +     C   cs       )         )         ,           (   28   )                                
     where C p2  represents parasitic junction and routing capacitances on f g  as well as channel capacitance of G 24  and G 8 . The second term in this expression corresponds to effective capacitance of the CCD well when it is empty. The high potential on the floating gate at this time leaves it well situated to receive charge during the following phase. 
     At the beginning of the collection phase, the floating gate well contains no charge. Its storage capacity, which is proportional to the difference between the channel potentials of G 13  and G 12 , is approximately equal to 
     
       
         | Q|   max =( V   r   −v   th1 −4+ v   th2 )( C   gc   +C   cs ).  (29) 
       
     
     Variables v th1  and v th2  refer to threshold voltages of the first and second level gates and 4V represents the high level of the φ b2  clock. A quantity of charge Q s  is transferred underneath the floating gate by lowering the potential of G 11 . The floating gate potential falls temporarily in response and its storage capacity is reduced to approximately                     Q        max     =       (       V   r     +         Q   s          (       C   gc           C   gc          C   p2       +       C   cs          (       C   gc     +     C   p2       )           )                       (       C   gc         C   gc     +     C   cs         )       -     v   th1     -   4   +     v   th2       )            (       C   gc     +     C   cs       )     .               (   30   )                                
     When Q s  is large, this reduction in storage capacity may cause some electrons to be temporarily stored underneath the G 12  barrier, where they are no longer sensed by the floating gate. However, as charge flows through the secondary sensing path, the voltage on f g  rises, storage capacity is restored, and electrons are once again confined to the floating gate. At the end of collection, the level on the floating gate is                  f   g          (     3      H     )       =         (         f   g          (     2      H     )       +       Q   s            C   gc           C   gc          C   p2       +       C   cs          (       C   gc     +     C   p2       )               )                 -   H     /     τ   3           +       (       V   h   ′     -     v   th   ′       )            (     1   -            -   H     /     τ   3           )     .                 (   31   )                                
     During the sensing phase, any charge that remains on f g  is passed to the primary output well, and the potential on f g  rises to its final value of                  f   g          (     4      H     )       =           f   g          (     3      H     )                   -   H     /     τ   4           +       (         AV   r     -     v   th         A   +   1       )            (     1   -            -   H     /     t   4           )     .                 (   32   )                                
     The time constant for this transition is                  τ   4     =         R   24       (     A   +   1     )            (       C   p2     +       (       C   gc     +     C   cs       )          FK   eff         )         ,           (   33   )                                
     The factor FK eff  is used to translate storage capacity into effective capacitance seen by the gate. 
     Combining Eqs. 27, 31 and 32, and eliminating higher-order exponential terms, yields the resultant charge packet                Q   o     =         Q   s            C   gc         C   gc     +     C   cs           -       (       V   h   ′     -     v   th   ′     +     V   p       )                 -   H     /     τ   4                C   p2     .                 (   34   )                                
     In most cases, the approximation H&gt;&gt;τ 4  is valid and this expression can be simplified to                Q   o     =       Q   s              C   gc         C   gc     +     C   cs         .               (   35   )                                
     The output packet depends on capacitances of the CCD well, but does not depend on parasitics on the floating gate node. 
     The nondestructive sensing circuit  700  of FIG. 7A produces an output charge that is a replica of its input packet. A modified version of this circuit, shown in FIG. 8A, can be used to produce an output voltage instead. FIG. 8A is a schematic diagram of an exemplary embodiment of a DDS charge sensing circuit  800  with voltage output in accordance with the invention. FIGS. 8B-8E are associated energy level diagrams for a fill phase, spill phase, collection phase and sensing phase, respectively. The circuit  800  is configured by connecting floating gate G 13  from within a CCD register  802 , to the input of a DDS core unit  804 . 
     In the configuration of circuit  800 , the final well G 7  that was otherwise used to store the result, is replaced by a capacitor, C 3 . In this circuit, charge packets described by Eq. 35 are generated and stored in the wells of G 5  and G 10 . During phases  3  and  4 , the output node v o  is precharged to V c . During phase  1 , the result is transferred onto v o  by lowering the potential of G 5  and G 10 . The potential on v o  after all charge has transferred is given by                v   o     =       V   c     +         Q   s       C   3                C   gc         C   gc     +     C   cs         .                 (   36   )                                
     One advantage of DDS charge sensing is that it has the same voltage requirements as a simple CCD register because its floating gates are clocked to the same levels as other CCD gates. Two other advantages of DDS charge sensing are that it provides greater storage capacity in its floating gate wells and permits a large output voltage swing. Signals are converted to voltages on the output v o , rather than within the CCD register. Storage capacity is also improved because the floating gate is a virtual ground and output swing does not reduce storage capacity. 
     An operation that is commonly required in A/D conversion is subtraction of the output from a multiplying D/A from an incoming analog signal. DDS circuit techniques can be used to perform this function. In a DDS approach, an input quantity of positive charge, generated through capacitor elements, is combined on a wire with an incoming packet of negative charge, from a CCD register. The D/A full scale can be either a time-varying voltage or a constant reference voltage. Since diffusions are necessary on the wire, the operation is nondepleted and subject to thermal noise, coupling, and clock feedthrough. However, DDS subtraction has the advantage that its positive charge is formed through polysilicon capacitors. These capacitors provide good element-to-element matching and low voltage dependence, which is important if the D/A full-scale is a time varying signal. DDS subtraction also has the advantage that its incoming negative signal is not subject to nonlinearities due to capacitor voltage dependence. 
     A circuit for performing this function is shown in FIG.  9 A. FIG. 9A is a schematic diagram of an exemplary embodiment of a DDS D/A and subtraction circuit  900  in accordance with the invention. FIGS. 9B-9E are associated energy level diagrams for a fill phase, spill phase, collection phase and sensing phase, respectively. 
     A CCD register  902 , formed by gates G 11 , G 12 , and G 13 , serves as the source of electrons. Its output is connected to the input of a DDS core unit  904 . N-bit D/A conversion is performed by an array of (2 N −1) identically sized units  906 , each one consisting of a clamp-and-sample circuit  908  in series with a capacitor C 1 . The D/A elements provide positive charge to the input of the DDS core unit. The resulting combination of negative and positive charge is integrated in receiving well G 5 . The DDS core of this circuit differs from that used for charge generation in that the secondary sensing path is eliminated. 
     The operation of this circuit is similar to that of the DDS wire transfer described earlier. During the fill phase, f g  is pulled low to V p  to provide a new supply of electrons to the circuit. Gate G 12  is off at this time to prevent charge from flooding backward into the source register. Meanwhile the array of signals v f (i), within the D/A, is forced low by the precharge through M 3 . 
     The D/A precharge remains on during the spill phase. Node f g  is reset to a level of                  f   g          (     2      H     )       =         V   p                 -   H     /     τ   2           +       (         AV   r     -     v   th         A   +   1       )            (     1   -            -   H     /     τ   2           )     .                 (   37   )                                
     The time constant for this transition is                τ   2     =           R   24          (         (       2   N     -   1     )          C   1       +     C   p2       )         (     A   +   1     )       .             (   38   )                                
     Capacitor C p2  represents parasitic junction and routing capacitances on f g  as well as channel capacitance of G 24  and G 13 . 
     During the collection phase, a quantity of charge Q s  is transferred onto f g  by lowering the potential of G 11 . At the same time, the digital inputs w(i), which are in a thermometer code format, are used to selectively assert some of the signals v f (i). When w(i) is high, a positive transition of V c  is introduced across C 1 (i). When w(i) is low, the capacitor voltage remains unchanged. Electrons, from the source register, are cancelled by positive displacement charge, and f g  is restored to a higher voltage. The resulting potential on f g  from the combination of these competing effects is                  f   g          (     3      H     )       =         f   g          (     2      H     )       +           Q   s     +       ∑     i   =   0         2   N     -   1              w        (   i   )            C   1          V   c             (         (       2   N     -   1     )          C   1       +     C   p2       )       .               (   39   )                                
     During the sensing phase, the net charge on f g  flows through G 24  to the output well, and the potential on f g  rises to its final value of                  f   g          (     4      H     )       =           f   g          (     3      H     )                   -   H     /     τ   4           +       (         AV   r     -     v   th         A   +   1       )            (     1   -            -   H     /     τ   4           )     .                 (   40   )                                
     The time constant for the sensing transition, τ 4 , equals that for the spill transition, τ 2 . 
     Combining Eqs. 37, 39 and 40, and eliminating higher-order exponential terms, yields the resultant charge packet                Q   o     =         (       Q   s     +       ∑     i   =   0         2   N     -   1              w        (   i   )            C   1          V   c           )          (     1   -            -   H     /     τ   4           )       -       (           AV   r     -     v   th         A   +   1       -     V   p       )                     -   H     /     τ   4              (         (       2   N     -   1     )          C   1       +     C   p2       )       .                 (   41   )                                
     The approximation H&gt;&gt;τ 4  is nearly always valid for this circuit and the first term, which represents a constant offset, is negligible. The result is then identically equal to the difference between the input charge Q s  and the D/A displacement charge, regardless of parasitics on the wire transfer node, f g . 
     A pair of DDS sensing circuits  700  can also be used to implement comparison. In this approach, two differential input packets are each replicated, using a DDS replicator circuit. The resulting packets are stored in CCD receiving wells and are translated to voltages at the input to a CMOS comparator during the following phase. This circuit can also incorporate differential amplification and common-mode rejection in the charge domain using the feedback techniques. 
     The resolution of this technique is greater than that for a configuration that performs charge-to-voltage translation on the floating gates. First, it supports a larger signal range so that the impact of comparator or amplifier input-offset voltages is reduced. Second, matching in the charge-to-voltage translation is improved because gains are determined by polysilicon capacitors and are only weakly dependent on CCD well capacitances. 
     Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.