Abstract:
An output circuit including an input terminal; an output terminal; a PMOS transistor connected with a positive side of a power voltage and the output terminal; a NMOS transistor connected with a negative side of the power supply voltage and the output terminal; a first inverter, to which a gate voltage of the PMOS transistor is input and which exhibits hysteresis in threshold voltage; and a second inverter, to which a gate voltage of the NMOS transistor is input and which exhibits hysteresis in threshold voltage, wherein an OR logic signal of the input signal and a signal obtained by inverting an output signal from the second inverter is input to a gate of the PMOS transistor, and an AND logic signal of the input signal and a signal obtained by inverting an output signal from the first inverter is input to a gate of the NMOS transistor.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an output circuit. More particularly, the present invention relates to an output circuit having a CMOS configuration. 
         [0003]    2. Discussion of the Related Art 
         [0004]    Conventional output circuits having a CMOS configuration, which have been used for synchronous rectification type step-down DC-DC converters, have the following drawback. Specifically, when a control signal is input to gates of a PMOS transistor and a NMOS transistor, which gates are connected with each other, and the control signal changes from a low level to a high level or vice versa, there is a period in which both the PMOS transistor and NMOS transistor are in an ON state at the same time, resulting in flow of a large current therethrough (hereinafter referred to as a through current or a through current problem). Thereby, problems in that the consumption current seriously increases and a large noise is produced in the power source are caused. 
         [0005]    In attempting to prevent occurrence of the through current problem, such an output circuit as illustrated in  FIG. 1  is used.  FIG. 2  is a timing chart illustrating the waveforms of voltage at several portions of the circuit illustrated in  FIG. 1 . 
         [0006]    Referring to  FIG. 2 , a character IN denotes a level (i.e., a high level H or a low level L) of the input terminal of the circuit; a character PH denotes the gate voltage of a PMOS transistor M 101 ; a character A denotes an input signal input to a second input terminal of a NAND circuit  114 ; a character B denotes an input signal input to a second input terminal of an NOR circuit  111 ; a character NL denotes a gate voltage of a NMOS transistor M 102 ; a character M 101  denotes an ON or OFF state of the PMOS transistor M 101 ; a character M 102  denotes an ON or OFF state of the NMOS transistor M 102 ; and a character OUT denotes a level (i.e., a high level H or a low level L) of the output terminal OUT of the output circuit. 
         [0007]    When the input terminal IN is on a low level L, the output signal of the NAND circuit  114  is on a high level. Therefore, the output signal output from an inverter  115  is on a low level and the gate voltage NL of the NMOS transistor M 102  is on a low level. Therefore, the NMOS transistor M 102  is in an OFF state. In addition, since the gate voltage NL of the NMOS transistor M 102  is on the low level, the input signal B input to the second input terminal of the NOR circuit  111  attains a low level, and the output signal output from the NOR circuit  111  attains a high level. Further, since the output signal output from an inverter  112  is on a low level, the gate voltage PH of the PMOS transistor M 101  is on a low level. Therefore, the PMOS transistor M 101  is in an ON state. Furthermore, since the gate voltage PH of the PMOS transistor M 101  is input to the second input terminal of the NAND circuit  114  via a buffer circuit  113 , the input signal A input to the second input terminal of the NAND circuit  114  is on a low level. 
         [0008]    When the input terminal IN attains a high level H, the output signal from the NOR circuit  111  attains a low level, and the output signal from the inverter  112  attains a high level. In this regard, a gate capacitance of the PMOS transistor  101  is charged, and thereby it takes a certain time until the gate voltage PH of the PMOS transistor M 101  attains a high level as illustrated in  FIG. 2 . When the gate voltage PH of the PMOS transistor M 101  reaches a half voltage (i.e., Vdd/2) of a power supply voltage Vdd, the output signal A from the buffer circuit  113  inverts and attains a high level. In this regard, a capacitor C 101  is charged, and thereby the output signal A from the buffer circuit  113  gradually increases as illustrated in  FIG. 2 . 
         [0009]    When the gate voltage PH of the PMOS transistor M 101  increases and exceeds a threshold voltage Vtp, the PMOS transistor M 101  achieves an OFF state. At this time, the input signal A has not yet reached the half voltage Vdd/2, and the gate voltage NL of the NMOS transistor M 102  is still on the low level. Therefore, the NMOS transistor M 102  maintains the OFF state. Accordingly, production of a through current can be prevented. 
         [0010]    When the voltage of the output signal from the buffer circuit  113  further increases and reaches the half voltage Vdd/2, the output signal from the NAND circuit  114  attains a low level and thereby the output signal from the inverter  115  attains a high level. In this regard, the gate capacitance of the NMOS transistor M 102  is charged, and thereby the gate voltage NL of the NMOS transistor M 102  gradually increases as illustrated in  FIG. 2 . When the gate voltage NL of the NMOS transistor M 102  reaches a threshold voltage Vtn, the NMOS transistor M 102  achieves an ON state. When the gate voltage NL further increases and reaches the half voltage Vdd/2, the output signal from the buffer circuit  116  attains a high level. In this regard, a capacitor C 102  is charged, and therefore it takes a certain time until the input signal B attains a high level as illustrated in  FIG. 2 . Even when the input signal B input to the second input terminal of the NOR circuit  111  attains a high level, the output signal from the NOR circuit  111  does not change because the input signal IN is already on the high level H. 
         [0011]    When the input terminal IN attains the low level, the output signal from the NAND circuit  114  attains the high level, and the output signal from the inverter  115  attains the low level. In this regard, the gate capacitance of the NMOS transistor M 102  is discharged, and therefore it takes a certain time until the gate voltage NL attains a low level. When the gate voltage NL of the NMOS transistor M 102  decreases and reaches the half voltage Vdd/2, the output signal from a buffer circuit  116  inverts and attains a low level. In this regard, the capacitor C 102  is discharged, and therefore it takes a certain time until the output signal B attains the low level as illustrated in  FIG. 2 . 
         [0012]    When the gate voltage NL of the NMOS transistor M 102  decreases and reaches the threshold voltage Vtn, the NMOS transistor M 102  achieves the OFF state. At this time, the voltage of the input signal B has not yet decreased to the half voltage Vdd/2 and the gate voltage PH of the PMOS transistor M 101  is still on the high level. Therefore, the PMOS transistor M 101  maintains the OFF state. Thus, production of a through current can be prevented even when the input terminal IN changes to the low level L. 
         [0013]    Further, when the voltage of the input signal B decreases and reaches the half voltage Vdd/2, the NOR circuit  111  attains the high level and the output signal from the inverter  112  attains the low level. In this regard, the gate capacitance of the PMOS transistor M 101  is discharged, the gate voltage PH gradually decreases as illustrated in  FIG. 2 . When the gate voltage PH decreases and reaches the threshold voltage Vtn, the PMOS transistor M 101  achieves the ON state. When the gate voltage PH further decreases and reaches the half voltage Vdd/2, the output signal from a buffer circuit  113  attains a high level. In this regard, the capacitor C 101  is charged, and therefore it takes a certain time until the output signal A attains the low level as illustrated in  FIG. 2 . When the output signal from the buffer circuit  113  attains the low level, the input signal A to the NAND circuit  114  attains a low level but the output signal from the NAND circuit  114  is not changed because the input terminal IN is already on the low level. 
         [0014]    Thus, it is impossible for the circuit illustrated in  FIG. 1  that both the PMOS transistor and the NMOS transistor are on the ON state at the same time when the level of the signal input to the input terminal IN changes. Therefore, production of a through current can be prevented. However, occurrence of the problem in that both the PMOS transistor and the NMOS transistor are on the ON state at the same time is prevented by using a delay circuit utilizing the output current of the buffer circuit  113  and charging and discharging of the capacitor C 101 , and utilizing the output current of a buffer circuit  116  and charging and discharging of the capacitor C 102 . Therefore, it is necessary to set the delay time of the delay circuit to be longer than the times in which the PMOS transistor M 101  and the NMOS transistor M 102  are on the ON state. Therefore, the output circuit cannot perform high speed processing. In order to shorten the delay time, the precision of the delay time has to be enhanced. Specifically, since it is necessary for the output circuit to use a regulator circuit for trimming, etc., the area of the chip increases, resulting in increase of manufacturing costs of the output circuit because additional manufacturing processes are necessary. 
         [0015]    In attempting to remedy the drawbacks, published unexamined Japanese patent application No. 2000-49586 discloses an output circuit without a delay circuit, which is illustrated in  FIG. 3 . 
         [0016]    In the output circuit illustrated in  FIG. 3 , reference voltages Vthp and Vthn are set to be not greater than the threshold voltage of the PMOS transistor M 101  and the threshold voltage of the NMOS transistor M 102 , respectively. The gate voltage PH of the PMOS transistor M 101  is compared with the reference voltage Vthp by a comparator  124 . When the gate voltage PH reaches the voltage at which the PMOS transistor M 101  achieves an OFF state, the comparator  124  outputs a high level signal to open the gate of an AND circuit  125 . In addition, the gate voltage NL of the NMOS transistor M 102  is compared with the reference voltage Vthn by a comparator  126 . When the gate voltage NL reaches the voltage at which the NMOS transistor M 102  achieves an OFF state, the comparator  126  outputs a high level signal to open the gate of a NAND circuit  123 . Thus, occurrence of the problem in that both the PMOS transistor and the NMOS transistor are on the ON state at the same time can be prevented, resulting in prevention of production of a through current. 
         [0017]    However, the output circuit illustrated in  FIG. 3  has a drawback in that since two reference voltages are set and two comparators are used, the size of the circuit increases, resulting in increase of the size of the chip, thereby increasing the manufacturing costs of the circuit. 
         [0018]    Because of these reasons, a need exists for an output circuit, which can perform high speed processing without increasing the chip size. 
       SUMMARY OF THE INVENTION 
       [0019]    As an aspect of the present invention, an output circuit for generating a binary output signal on the basis of an output signal is provided, which includes: 
         [0020]    an input terminal configured to receive the input signal; 
         [0021]    an output terminal configured to output the binary output signal; 
         [0022]    a PMOS transistor connected with a positive side of a power supply voltage and the output terminal; 
         [0023]    a NMOS transistor connected with a negative side of the power supply voltage and the output terminal; 
         [0024]    a first inverter, to which a gate voltage of the PMOS transistor is input and which exhibits hysteresis in threshold voltage; and 
         [0025]    a second inverter, to which a gate voltage of the NMOS transistor is input and which exhibits hysteresis in threshold voltage,
       wherein an OR logic signal of the input signal and a signal obtained by inverting an output signal from the second inverter is input to a gate of the PMOS transistor, and an AND logic signal of the input signal and a signal obtained by inverting an output signal from the first inverter is input to a gate of the NMOS transistor.       
 
         [0027]    These and other objects, features and advantages of the present invention will become apparent upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]      FIG. 1  is a schematic diagram illustrating a background output circuit; 
           [0029]      FIG. 2  is a timing chart illustrating waveforms at several portions of the background output circuit illustrated in  FIG. 1 ; 
           [0030]      FIG. 3  is a schematic diagram illustrating another background output circuit; 
           [0031]      FIG. 4  is a schematic diagram illustrating an output circuit of an embodiment of the present invention; 
           [0032]      FIG. 5  is a schematic view for explaining hysteresis of threshold voltages of inverters used for the output circuit illustrated in  FIG. 4 ; 
           [0033]      FIG. 6  is a timing chart illustrating waveforms at several portions of the output circuit illustrated in  FIG. 4 ; and 
           [0034]      FIG. 7  is a schematic diagram illustrating a synchronous rectification step-down switching regulator for which the output circuit of the present invention is used; 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0035]    The output circuit of the present invention will be explained by reference to drawings. 
         [0036]      FIG. 4  is a schematic diagram illustrating an example of the output circuit of the present invention. 
         [0037]    Referring to  FIG. 4 , an output circuit  1  produces a binary signal Sout on the basis of an input signal Sin input to an input terminal IN and outputs the binary signal Sout from an output terminal OUT. 
         [0038]    As illustrated in  FIG. 4 , the output circuit  1  includes a PMOS transistor M 1 , a NMOS transistor M 2 , a NOR circuit  2 , a NAND circuit  3 , and inverters  4 - 9 . For example, when the output circuit  1  is used for synchronous rectification step-down switching regulators, the PMOS transistor M 1  serves as a switching transistor, and the NMOS transistor M 2  serves as a synchronous rectification transistor. The output terminal OUT is connected with a terminal of an inductor. In this regard, the inverter  5  serves as the first inverter, and the inverter  8  serves as the second inverter. 
         [0039]    The input signal Sin is input to a first input terminal of each of the NOR circuit  2  and the NAND circuit  3 . An output terminal of the NOR circuit  2  is connected with a gate of the PMOS transistor M 1  via the inverter  4 . In addition, an output terminal of the inverter  4  is connected with a second input terminal of the NAND circuit  3  via series circuits of the inverters  5  and  6 . An output terminal of the NAND circuit  3  is connected with a gate of the NMOS transistor M 2  via the inverter  7 . Further, an output terminal of the inverter  7  is connected with a second input terminal of the NOR circuit  2  via series circuits of the inverters  8  and  9 . The PMOS transistor M 1  and the NMOS transistor M 2  are serially connected between a power supply voltage Vdd and a ground voltage GND. In addition, the junction of the PMOS transistor M 1  and the NMOS transistor M 2  serves as the output terminal OUT. 
         [0040]    In the output circuit having such a configuration, the inverters  5  and  8  exhibit hysteresis in threshold voltage. 
         [0041]      FIG. 5  is a schematic view for explaining hysteresis of threshold voltages of the inverters  5  and  8 . Namely,  FIG. 5  illustrates the relationship between the input voltage and the output voltage in the inverters  5  and  8 . Specifically, when the input voltage increases, the output voltage changes along a line indicated by a narrow with a black solid head. In contrast, when the input voltage decreases, the output voltage changes along a line indicated by a normal arrow. 
         [0042]    The hysteresis in threshold voltage will be explained in detail by reference to  FIG. 5 . When the input voltage is 0 v, the output voltage is on a high level, i.e., the output voltage is Vdd. When the input voltage increases and reaches a voltage VH, the output voltage attains a low level (i.e., 0 v). In addition, even when the input voltage further increases from VH to Vdd, the output voltage remains at 0 v. In contrast, when the input voltage decreases from the power supply voltage Vdd toward a voltage VL lower than the voltage VH, the output voltage remains at the low level (i.e., 0 v). However, when the input voltage reaches the voltage VL, the output voltage returns to the high level (i.e., Vdd). Even when the input voltage decreases from the voltage VL to 0 v, the output voltage remains at the high level (i.e., Vdd). The voltage VH (hereinafter sometimes referred to as the higher level threshold voltage) is set so as to be almost equal to the threshold voltage of the PMOS transistor M 1 , and the voltage VL (hereinafter sometimes referred to as the lower level threshold voltage) is set so as to be almost equal to the threshold voltage of the NMOS transistor M 2 . 
         [0043]      FIG. 6  is a timing chart illustrating the waveforms at several portions of the output circuit illustrated in  FIG. 4 . In  FIG. 6 , a character PH denotes the gate voltage of the PMOS transistor M 1 ; a character SA denotes an input signal input to the second input terminal of the NAND circuit  3 ; a character SB denotes an input signal input to the second input terminal of the NOR circuit  2 ; a character NL denotes the gate voltage of the NMOS transistor M 2 ; a character M 1  denotes an ON or OFF state of the PMOS transistor M 1 ; and a character M 2  denotes an ON or OFF state of the NMOS transistor M 2 . 
         [0044]    Next, the operation of the output circuit  1  illustrated in  FIG. 4  will be explained by reference to  FIG. 6 . 
         [0045]    When the input signal Sin is on a low level, the output signal from the NAND circuit  3  is on a high level. Therefore, the output signal from the inverter  7  is on a low level, and the gate voltage NL is on a low level. Accordingly, the NMOS transistor M 2  achieves an OFF state. 
         [0046]    In addition, since the gate voltage NL of the NMOS transistor M 2  is on the low level, the input signal SB input to the second input terminal of the NOR circuit  2  is on a low level, and the output signal from the NOR circuit  2  is on a high level. Further, since the output signal from the inverter  4  is on a low level, the gate voltage PH is also on a low level and the PMOS transistor M 1  achieves an ON state. Furthermore, since the gate voltage PH of the PMOS transistor M 1  is input to the second input terminal of the NAND circuit  3  via the inverters  5  and  6 , the input signal SA to the second input terminal of the NAND circuit  3  is on a low level. 
         [0047]    When the input signal Sin attains a high level, the output signal from the NOR circuit  2  attains a low level and the output signal from the inverter  4  attains a high level. In this regard, the gate capacitance of the PMOS transistor M 1  is charged, and therefore it takes a certain time until the gate voltage PH reaches a high level as illustrated in  FIG. 6 . When the gate voltage PH of the PMOS transistor M 1  reaches the higher level threshold voltage VH, the level of the output signal from the inverter  5  is inverted and the inverted output signal is input as a high level input signal SA to the second input terminal of the NAND circuit  3  via the inverter  6 . 
         [0048]    In this regard, since the higher level threshold voltage VH is set to be almost equal to the threshold voltage Vtp of the PMOS transistor M 1 , the input signal SA input to the second input terminal of the NAND circuit  3  attains a high level. Therefore, when the gate of the NAND circuit is opened, the PMOS transistor M 1  is in the OFF state. Since the gate voltage NL of the NMOS transistor M 2  does not change at this time, the NMOS transistor M 2  remains in the OFF state. Therefore, when the input signal Sin is changed from the low level to the high level, production of a through current can be prevented. 
         [0049]    When the input signal SA input to the second input terminal of the NAND circuit  3  attains the high level, the output signal from the NAND circuit  3  attains a low level and the output signal from the inverter  7  attains a high level because the input signal Sin input to the first terminal of the NAND circuit  3  is already on the high level. In this regard, since the gate capacitance of the NMOS transistor M 2  is charged, the gate voltage NL gradually increases as illustrated in  FIG. 6 . When the gate voltage NL reaches the threshold voltage Vtn of the NMOS transistor M 2 , the NMOS transistor M 2  achieves an ON state. Since the PMOS transistor M 1  has already achieved an OFF state at this time, a through current is not flown. When the gate voltage NL further increases and reaches the high voltage VH, the level of the output signal from the inverter  8  is inverted, thereby allowing the input signal SB to the second input terminal of the NOR circuit  2  to attain a high level. However, since the input signal Sin is already on the high level, the gate voltage PH of the PMOS transistor M 1  does not change. 
         [0050]    When the input signal Sin attains a low level, the output signal from the NAND circuit  3  attains the high level and the output signal from the inverter  7  is inverted to attain the low level. In this regard, the gate capacitance of the NMOS transistor M 2  is discharged, and therefore it takes a certain time until the gate voltage NL reaches the low level as illustrated in  FIG. 6 . When the gate voltage NL of the NMOS transistor M 2  decreases to the lower level threshold voltage VL, the output signal from the inverter  8  is inverted to attain a high level, thereby allowing the input signal SB to the second input terminal of the NOR circuit  2  to attain the low level. 
         [0051]    In this regard, the lower level threshold voltage VL is set to be substantially equal to the threshold voltage Vtn of the NMOS transistor M 2 . Therefore, when the gate of the NOR circuit  2  is opened while the input signal SB to the NOR circuit  2  is on the low level, the NMOS transistor M 2  is in the OFF state. Since the gate voltage PH of the PMOS transistor M 1  has not yet changed at this time, the PMOS transistor M 1  remains at the OFF state. Therefore, production of a through current can be prevented in the transition process of the input signal Sin of from the high level to the low level. 
         [0052]    When the input signal SB input to the second input terminal of the NOR circuit  2  attains the low level, the output signal from the NOR circuit  2  attains the high level and the output signal from the inverter  4  attains the low level because the input signal Sin has already achieved the low level. In this regard, the gate capacitance of the PMOS transistor M 1  is discharged, and therefore the gate voltage PH gradually decreases as illustrated in  FIG. 6 . When the gate voltage PH reaches the threshold voltage Vtp of the PMOS transistor M 1 , the PMOS transistor M 1  achieves the ON state. Since the NMOS transistor M 2  is already in the OFF state at this time, production of a through current can be prevented. When the gate voltage PH further decreases and reaches the lower level threshold voltage VL, the output signal from the inverter  5  is inverted to attain a high level, thereby allowing the input signal SA to the second input terminal of the NAND circuit  3  to attain the low level. In this regard, since the input signal Sin is already on the low level, the gate voltage NL of the NMOS transistor M 2  does not change. 
         [0053]      FIG. 7  is a schematic view illustrating a synchronous rectification type step-down switching regulator, for which the output circuit  1  illustrated in  FIG. 4  is used. 
         [0054]    A switching regulator  21  illustrated in  FIG. 7  converts a power supply voltage Vdd to a predetermined voltage, and outputs the voltage, as an output voltage Vout, to a load  20  from an output terminal OUT 1  thereof. 
         [0055]    The switching regulator  21  includes the output circuit  1 ; a reference voltage generating circuit  22 ; resistors R 21  and R 22  used for detecting the output voltage; an inductor L 21 ; a smoothing capacitor C 21 ; a resistor R 23  and capacitors C 22  and C 23  for use in phase compensation; an error amplification circuit  23 ; an oscillating circuit  24 ; and a PWM comparator  25 . 
         [0056]    The reference voltage generating circuit  22  generates and outputs a predetermined reference voltage Vref. The resistors R 21  and R 22  for use in detecting the output voltage divide the output voltage Vout to generate and output a divided voltage VFB. The error amplification circuit  23  amplifies the difference in potential between the divided voltage VFB and the reference voltage Vref to generate and output an output signal EAo. 
         [0057]    The oscillating circuit  24  generates and outputs a predetermined triangular waveform signal TW. The PWM comparator  25  generates a pulse signal Sin for performing PWM controlling using the output signal EAo output from the error amplification circuit  23  and the triangular waveform signal TW, and outputs the pulse signal Sin to the output circuit  1 . 
         [0058]    The inductor L 21  is connected with an output terminal of the output circuit  1  and the output terminal OUT 1 , and the resistors R 21  and R 22  are serially connected with the output terminal OUT 1  and a ground GND while the capacitor C 21  is connected therebetween. Therefore, the divided voltage VFB is output from the connection point between the resistors R 21  and R 22 . In addition, the capacitor C 22  for phase compensation is connected in parallel with the resistor R 21 . In the error amplification circuit  23 , the divided voltage VFB is input to an inverting input terminal and the reference voltage Vref is input to a non-inverting input terminal. The output terminal of the error amplification circuit  23  is connected with an inverting input terminal of the PWM comparator  25 . 
         [0059]    A series circuit constituted of the resistor R 23  and capacitor C 23  is connected with the output terminal of the error amplification circuit  23  and the ground GND, and therefore the series circuit serves as a phase compensating circuit. The triangular wave-form signal TW is input to a non-inverting input terminal of the PWM comparator  25 , and the pulse signal Sin output from the PWM comparator  25  is input to the output circuit  1 . 
         [0060]    When the output voltage Vout from the switching regulator  21  having such configuration increases, the voltage of the output signal EAo from the error amplification circuit  23  decreases, and thereby the duty cycle of the output signal Sin from the PWM comparator  25  is decreased. As a result, the time during which the output signal Sout from the output circuit  1  is on the high level is shortened, and the time during which the output signal Sout from the output circuit  1  is on the low level is prolonged. Thus, controlling such that the output voltage Vout from the switching regulator  21  is decreased is performed. 
         [0061]    In contrast, when the output voltage Vout from the switching regulator  21  having such configuration decreases, the voltage of the output signal EAo from the error amplification circuit  23  increases, and thereby the duty cycle of the output signal Sin from the PWM comparator  25  is increased. As a result, the time during which the output signal Sout from the output circuit  1  is on the high level is prolonged, and the time during which the output signal Sout from the output circuit  1  is on the low level is shortened. Thus, controlling such that the output voltage Vout from the switching regulator  21  is increased is performed. By repeating such operations, the output voltage Vout is controlled to be a predetermined voltage. 
         [0062]    As mentioned above, the output circuit of the present invention does not cause the through current problem in that both the PMOS transistor M 1  and NMOS transistor M 2  achieve an ON state at the same time in the transition process of the input signal Sin of from the high level to the low level or vice versa, and thereby a through current is produced. In addition, since the output circuit of the present invention does not use a delay circuit unlike conventional output circuits, the output circuit has advantages such that it is unnecessary to adjust the delay time of the delay circuit and high speed processing can be performed. 
         [0063]    Further, the output circuit of the present invention uses an inverter exhibiting hysteresis instead of the reference voltages and comparators used for the conventional output circuit illustrated in  FIG. 3 . Therefore, the output circuit can prevent occurrence of the through current problem, although the output circuit is a simple circuit. 
         [0064]    Furthermore, the higher level threshold voltage of each of the inverters  5  and  8  is set to be substantially equal to the threshold voltage of the PMOS transistor M 1  and the lower level threshold voltage of the threshold voltage of each of the inverters  5  and  8  is set to be substantially equal to the threshold voltage of the NMOS transistor M 2 . Therefore, occurrence of the through current problem can be securely prevented. 
         [0065]    Additional modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced other than as specifically described herein. 
         [0066]    This document claims priority and contains subject matter related to Japanese Patent Application No. 2007-238274, filed on Sep. 13, 2007, the entire contents of which are herein incorporated by reference.