Abstract:
The present invention relates to a dynamically testable programmable logic array in an unprogrammed state which adds some circuit components to the static test logic. The static test logic provides the capability to detect stuck-at faults at the input of each logic gate of the programmable logic array, and is inoperative during normal operation of the programmable logic array. The added circuit components cause selected inputs to the product array to partially enable the product array, whereby the remaining inputs to the product array are a function of the inputs to the programmable logic array, thereby providing the dynamic test capability.

Description:
RELATED APPLICATIONS 
     The present application is related to the following U.S. patent applications, which are assigned to Honeywell Information Systems Inc., the assignee of the present application, the references listed below being incorporated by reference herein: 
     (a) &#34;Programmable Logic Array with Test Capability in the Unprogrammed State by David W. Still and Peter C. Economopoulos, Ser. No. 446,816 filed 12/3/82; and 
     (b) &#34;A Method of Programming a Programmable Logic Device by Vaporization of Metallized Links,&#34; by David W. Still and Peter C. Economopoulos, Ser. No. 451,134 filed 12/20/82. 
     BACKGROUND OF THE INVENTION 
     This invention relates to a logic circuit, and more particularly to the dynamic testability of a programmable logic array. 
     In the design of logic circuits, programmable logic arrays (PLA) have become increasingly more important for designing combinational logic circuits. These programmable logic arrays offer a greater variety and flexibility in logic design while lowering parts count and inventory requirements, and are also proving to be very cost effective. With programmable logic devices, a designer can customize a reliable, high volume integrated circuit to fit a specific application, and quickly. 
     However, until recently, little has been done to test the programmable logic array in the unprogrammed state. This is due in part to the unavailability of an adequate number of test points on the chip. The various testing techniques devised require augmenting the PLA with a substantially large amount of additional logic which can interfere with the normal operation of the PLA logic or which requires and dissipates additional power even while the PLA is operating normally. 
     The related application of paragraph (a) above presents a novel approach for providing static (or dc) test capability of a programmable logic array in the unprogrammed state with some small amount of added logic which is inoperative and dissipates no added power while the PLA is operating in its normal environment. 
     Presently, ac, or dynamic, testing is either not performed or is performed after the programmable logic array is programmed. Thus, it is apparent that ac testing of programmed programmable logic arrays (or devices) require individualized test procedures or routines. Since many programmed combinations may be available, the number of individualized test routines can be quite high. 
     Hence, it would be highly desirable to ac test a programmable logic array in an unprogrammed state. The present invention presents a novel approach for providing dynamic (or ac) test capability of a programmable logic array in the unprogrammed state. Some additional circuit components are added to the test logic of the programmable logic array to provide the dynamic test capability without comprising the static test capability. 
     SUMMARY OF THE INVENTION 
     Therefore, there is supplied a dynamically testable programmable circuit array, having a plurality of input terminals, each input terminal adapted to receive one of a plurality of input signals. The programmable circuit array comprises an input buffer, having a plurality of output terminals and inverted output terminals, the input buffer being operatively connected to the input terminal, which outputs equivalent input signals and inverted input signals, the equivalent input signals forming a first output group and the inverted input signal forming a second output group. The programmable circuit array also includes a programmable product array element which is operatively connected to the output terminals of the input buffer for generating a plurality of product terms. A programmable sum array element is included for combining the plurality of product terms to generate a plurality of sum terms, each of the plurality of sum terms being an output of the programmable circuit array. Test logic is also included which causes one of the output groups to have a predetermined logic state. 
     The product array element includes a plurality of AND gates, each AND gate coupled to receive a respective input signal, and each AND gate having associated therewith a fusible link. The sum array element includes a plurality of OR gates, each OR gate coupled to receive a respective product term, and each input of each OR gate having associated therewith a fusible link. An input buffer can also be included to provide the input signal and the complement of the input signal to the product array element. The output can include a plurality of exclusive-OR elements each exclusive-OR element coupled to a respective output, and each exclusive-OR element having a fusible link, thereby providing a programmable capability to the output signal whereby the output can be in a normal or inverted state. 
     Accordingly, it is an object of the present invention to provide a programmable logic array having test capability. 
     It is another object of the present invention to provide a programmable logic array having one hundred percent test capability. 
     It is still a further object of the present invention to provide a programmable logic device having dynamic test capability of the programmable logic device in the unprogrammed state. 
     It is still another object of the present invention to provide a programmable logic device having one hundred percent test capability for detecting stuck-at faults occurring at all the gate inputs of the programmable logic array chip. 
     It is still a further object of the present invention to provide a programmable logic device having dynamic test capability of the programmable logic device in the unprogrammed state without compromising the static test capability. 
    
    
     These and other objects of the present invention will become more apparent when taken in conjunction with the following description and attached drawings, wherein like characters indicate like parts, and which drawings form a part of the present application. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a programmable logic array of the prior art; 
     FIG. 2 shows a functional logic diagram of a programmable logic array; 
     FIG. 3 shows a circuit diagram of an input buffer and pulldown logic; 
     FIG. 4 shows a circuit diagram of the pulldown logic modified to provide dynamic test capability; 
     FIG. 5 shows a circuit diagram of a product array of the programmable logic array; 
     FIG. 6 shows a logic equivalent of the sum gates; and 
     FIG. 7 shows the circuit diagram of a sum array and a selector network. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, there is shown a programmable logic array (PLA) 100 of the prior art containing an input block 10 providing input terminals for receiving input signals I 1 , I 2 , operatively connected to a first fusible links network 20 of a product (AND) array 40, which in turn outputs product terms P 1  and P 2 . The product terms are operatively connected through a second fusible links network 30 of a sum (OR) array 50 providing outputs Z 1 , Z 2 . The input block 10 comprises input buffers 1, 2 each having an output and an inverted (or complement) output, the inverted output having the circle denoting the inversion function. The product array 40 comprises two, four-input AND gates 3, 4, each input of each AND gate 3, 4 having a fusible link connected to each input of the AND gates 3, 4, the fusible links forming the first fusible link network 20. Each input of each AND gate 3, 4 is operatively connected to a respective output of input block 10. The sum array 50 comprises two OR gates 5, 6, each OR gate 5, 6 having two inputs each of which is operatively connected to a respective product P1, P2. Each input of each OR gate has associated therewith a fusible link, these fusible links comprising a second fusible links network 30. The PLA 100 can be programmed by vaporizing (i.e., the fusible link is electrically opened thereby breaking or opening the circuit) each link as desired to generate the desired logic output terms Z 1  and Z 2 . 
     Prior to programming PLA 100 it is desirable to test the PLA 100 in the unprogrammed state. (Programming a PLA 100 may also be denoted herein by the terms customizing or personalizing a PLA.) Since the inputs to AND gate 3 will include the terms I 1  and I 1 , and since I 1  ·I 1  =0, AND gate 3 can never be fully tested. 
     Referring to FIG. 2, there is shown a functional logic drawing of a PLA 101 which includes test logic for providing static (or dc) test capability which tests the PLA 101 in the unprogrammed state, the test logic for providing the static test capability of the PLA also being described in the related application of paragraph (a) referred to above. The PLA 101 includes input buffers 1, 2 operatively connected to two four-input AND gates 3, 4 through fusible links 21-28, the inputs to each AND gate denoted 1-4, and each AND gate outputs respective product terms P 1 , P 2  (also denoted as A, B.) Each product term is operatively connected to two-input OR gates 5, 6 through respective fusible links 31-34, the inputs to each OR gate denoted 1, 2, and each OR gate outputs respective output terms Z 1 , Z 2 . 
     Static testing of PLA 101 in the unprogrammed state is performed by setting predetermined select 1 control signals TT and TC and predetermined select 2 control signals T 1  and T 2 , varying the input signals, I 1  and I 2 , to input buffer 1, 2 to various combinations of logic 1 and logic 0, and verifying output signals Z 1  and Z 2  for each combination of input signal I 1  and I 2 . By setting select 1 control signal TT to a logic zero and TC to a logic one, pull down logic 7 operates to force input gate 1,2 complement outputs 12&#39; and 14&#39; to a logic one. By setting control signals T 1  and T 2  to a logic 1 and logic 0 respectively, selector 8 causes line B&#39; to have a predetermined logic state, i.e., a logic 0, while line A&#39; operates normally, i.e., the signal on line A&#39; follows the signal on line A, which is the product signal P 1 . 
     The testing procedure will now be described in conjunction with FIG. 2 and Table 1. Step 1 of the test procedure sets input signals I 1  and I 2  to a logic 1. The outputs of input buffer 1 are respectively a logic 1 and logic 0 on lines 11 and 12, respectively. The output signal of input buffer 2 is a logic 1 and logic 0 on lines 13 and 14, respectively. Because the pulldown logic 7 forces the complement output 12&#39; and 14&#39; to a logic 1 all four outputs 11&#39; through 14&#39; of pulldown logic 7 are all at logic 1. Since all four inputs to the AND gates 3, 4 are logic ones, the outputs of AND gates 3, 4 (A, B) are both at logic one. The A&#39; output of selector 8 will be a logic 1, since control signal T 1  has been set to a logic 1 thereby allowing the signal on line A&#39; to follow the signal on line A. Since control signal T 2  has been set to a logic zero, the B&#39; output of selector 8 is forced to a logic zero. Hence, the one input of OR gates 5, 6 will have a logic 1 and the two input of OR gates 5, 6 will have a logic 0. Since one input of the OR gate is conditioned (the one input of both OR gates 5, 6 have a logic one), the Z 1  and Z 2  outputs will both be a logic 1. The logic levels thus described are in accordance with step 1 of Table 1. 
     
                       TABLE 1______________________________________Step I.sub.1      I.sub.2            TT   TC   A   B   T.sub.1                                   T.sub.2                                       A&#39;  B&#39;   Z.sub.1                        Z.sub.2______________________________________1    1     1     0    1    1   1   1    0   1   0    1                        1                        2 0 1 0 1 0 0 1 0 0 0 0 0                        3 1 0 0 1 0 0 1 0 0 0 0 0                        4 0 0 1 0 1 1 1 0 1 0 1 1                        5 1 0 1 0 0 0 1 0 0 0 0 0                        6 0 1 1 0 0 0 1 0 0 0 0 0                        7 1 1 0 1 1 1 0 1 0 1 1 1                        8 0 1 0 1 0 0 0 1 0 0 0 0                        9 1 0 0 1 0 0 0 1 0 0 0 0                        10  0 0 1 0 1 1 0 1 0 1 1 1                        11  1 0 1 0 0 0 0 1 0 0 0 0                        12  0 1 1 0 0 0 0 1 0 0 0 0______________________________________ 
    
     Steps 2 and 3 vary the input signals I 1  and I 2  verifying the one input of OR gates 5, 6, and verifying the 1 and 4 input of AND gate 3, respectively. Step 1 and Step 4 also check the true output and complement output of input buffer 1, 2 respectively. Steps 4, 5 and 6 reverse the select 1 control signals thereby forcing the true output of input buffer 1, 2 to a logic 1, namely 11&#39; and 13&#39; are forced to a logic 1. This permits steps 5 and 6 to verify the proper functioning of the 2 and 3 input of AND gate 3. Steps 7-12 essentially repeat steps 1-6 above but the select 2 control signals, T 1  and T 2 , are reversed. In this case, selector 8 forces line A&#39; to a logic 0 and allows the signal on line B&#39; to follow the input signal B, thereby verifying the functioning of the 2 input of OR gates 5,6. In addition, steps 8, 9, 11, 12 verify the proper functioning of inputs 1, 4, 2, and 3 of AND gate 4, respectively. 
     The circuit of the input buffer 1, 2 is shown in FIG. 3. The PLA 101 shown in FIG. 3 is implemented in current mode logic (CML) technology. Negative logic is utilized in PLA 101. In the preferred embodiment, a logic 0 is 0 volts and a logic 1 is -0.5 volts or -500 millivolts (-0.5 V or -500 MV). Typical component values are as follows: 
     resistors 201, 202, 203--50 ohms 
     resistor 204--10,000 ohms 
     resistors 205, 206--560 ohms 
     resistor 207--270 ohms 
     resistor 208--50 ohms 
     resistor 209--10,000 ohms 
     resistor 210--50 ohms 
     resistors 211, 212--2,000 ohms 
     V e  --3.3 volts 
     V 1  --0.26 volts 
     V 3  --2.25 volts 
     Also shown in FIG. 3 is the circuit diagram of pulldown logic 7. The true output lines 11, 13 of input buffer 1, 2 are tied through diodes 71, 73 to the TT select 1 control line. Similarly, the complement output 12, 14 of input gates 1, 2 are each tied through diodes 72, 74, to TC control line of select 1 control signal. The control signals TT, TC operate to pull down the respective line to a logic 1. The TT, TC control signal operate such that the line varies between 0 volts and -1 volts, 0 volts corresponding to a logic zero and a -1 volt corresponding to a logic 1. 
     In order to provide dynamic (or ac) test capability of the PLA 101, pulldown logic 7 is modified by including additional circuit components. Referring to FIG. 4, there is shown a circuit diagram of the preferred embodiment of the present invention whereby the test logic, i.e., pulldown logic 7, is modified by the inclusion of the additional circuit components. A resistor 213 is connected to node 76 of TC line 77 through a fusible link 75. The resistor is also connected to the voltage source V e . It is to be appreciated by those skilled in the art that the fusible links referenced herein may be any type of link which may be broken electrically or otherwise. For example, the fusible links can include metallized links which also form a normal transmission or connection path which may be vaporized by laser techniques. 
     As mentioned above, V e  is nominally -3.3 volts, and resistor 213 is selected such that when terminals TC and TT are floating, node 76 is at a logic 1. A typical value for resistor 213 in the preferred embodiment is 93 ohms, and node 76 will typically have a value of -1.0 to -1.5 volts. When select 1 control signal TC is set to 0 volts, diode 72, 74 may or may not conduct depending on the value of the signal on line 12, 14. The value of the signal on line 12, 14 is -0.5 volts, the respective diodes 72, 74 are back biased and the input lines 12&#39;, 14&#39;, are -0.5 volts or a logic one. If the value of the signal on line 12, 14 is 0 volts, diodes 72, 74 are inoperative and the input lines 12&#39;, 14&#39; are 0 volts or a logic 0. When the select 1 control signal TC is set to -1 volts, the diodes 72, 74 will conduct independent of the signal level of line 12, 14 such that line 12&#39;, 14&#39; will be pulled down to a logic one. Hence, the test logic of pulldown logic 7 is operative for static testing as described above even with the inclusion of the added circuit components. 
     During static testing, which is generally performed on each integrated circuit chip of a wafer, the terminals (or pads) TC and TT are accessible for connection to a test source which provides the select 1 control signals TT and TC. However, after the wafer is scribed and the integrated circuits are each individually mounted, the terminals TC and TT are not accessible since an additional layer has been added, known as a pasivation layer. As a result, terminals TC and TT are floating, and node 76 will be at -1.0 to -1.5 volts. As a result, line 12&#39;, 14&#39; will be about -0.5 to -1.0 volts, or a logic one, after accounting for approximately a 0.5 volt drop across diode 72, 74. 
     Referring back to FIG. 2, inputs 2, 4 to AND gates 3, 4 will be at a logic one. Inputs 1, 3 to AND gates 3, 4 are a function of inputs I 1  and I 2 . By setting I 2  to a logic one, and providing a pulse input to input I 1  a resulting pulse output at Z 1  results, and the time delay can be measured. Similarly, I 1  can be set to a logic 1 and a pulse input provided at input I 2 , and the output pulse at Z 2  can be observed and the resulting time delay measured. It is obvious to one skilled in the art that the measurements can be manual, i.e., a dual-trace scope connected to the input terminals I 1 , I 2  and connected to the output terminals Z 1 , Z 2 , and the delay observed by a test operator, or can be by automated equipment designed to measure time delay known to those skilled in the art. Since all the inputs to all the AND gates and OR gates are included, i.e., the PLA is in the unprogrammed state, the measured time delay is a worst-case time delay. 
     After the dynamic testing has been performed, the fusible links 21-28, and the fusible links 31-34, can be broken as desired to yield the desired programmed programmable logic device. In addition, during the programming process, one additional link must be broken, namely, fusible link 75. Breaking fusible link 75 allows input line 12&#39; 14&#39; to correspond to the respective input signal at I 1 , I 2 . 
     The circuit diagram of the product array 40 is shown in FIG. 5. Resistors 401-404 are typically 100 ohms. The fusible links 21-28 are shown and correspond to the fusible links of FIG. 2. Still referring to FIG. 5, the product terms P 1  and P 2  are shown as the output of their respective AND gates 3, 4. Although only two input buffers have been shown and discussed thus far, it will be understood by those skilled in the art that more input buffers may be implemented. Two 4-input AND gates have been discussed thus far. It will be appreciated and understood by those skilled in the art that more AND gates may be implemented resulting in an increased number of product terms. The circuit diagram shown in FIG. 5 can be expanded to increase the number of product terms up to P n  by adding a like number of circuits in each vertical column. For additional input buffers additional input lines can be added to increase the number of inputs to each respective AND gate. 
     The sum array 50 is implemented utilizing Boolean equivalent: ##EQU1## Hence, the OR gates 5, 6 are each implemented logically as shown in FIG. 6. Although the selector 8 is functionally placed at the input of the OR gates 5, 6 as shown in FIG. 2, the selector logic 8 is more readily positioned and more easily implemented in CML (current mode logic) as shown in FIG. 6 and will be described in further detail hereinunder. 
     FIG. 7 shows the circuit diagram of the sum array 50 and the selector 8 which corresponds to FIG. 6. Inverters 51 and 52 receive the product inputs P 1  and P 2 , respectively. Each inverter 51, 52 may be implemented utilizing the circuit diagram of the input buffer 1 utilizing only the complement output. The output of each inverter 51, 52 is operatively coupled to the AND array 53 through selector 8. 
     Selector 8 comprises a diode 81, 82 coupled to the output of its respective inverter 51, 52. Each diode 81, 82 has coupled thereto a 6-emitter transistor 83, 84 the six emitters of each transistor being selectively coupled to six of the twelve select 2 control signals. The twelve individual select 2 control signals are denoted T 1  through T 6  and T 1  through T 6 . Twelve signals are required to select the forty product terms in the preferred embodiment. If any of the select 2 control signals is set to a -2 volts, the input line 85, 86 will be pulled down to a -0.7 volts or a logic 1, which is the functional equivalent of pulling down A&#39; or B&#39; to a logic 0. In the testing process all transistors but one will be pulled down. The emitter connections for transistor 83 are connected to select 2 control signals T1, T2, T3, T4, T5, and T6 and transistor 84 is connected to select 2 control signal T 1 , T 2 , T 3 , T 4 , T 5 , and T 6 . Thus when select control signal T1-T6 are respectively at logic 000000 (and T1-T6 are therefore at logic 111111), all the emitter connections of transistor 83 will be at a logic 0 (0 volts) thereby enabling line 85. All the other lines, 86, will have at least one emitter connected to a logic 1, or -2 volts thereby holding line 86 to a logic 1 (for example, emitter T 6  of transistor 84 connected to T 6  which is a logic 1 or -2 volts). When T 1  -T 6  are at logic 000001, transistor 84 will be selected. Thus, only one product turn will be enabled by selector logic 8 as discussed above. 
     The circuit diagram of AND gate 53 shown in FIG. 7 has a similar configuration to the product array 40 as discussed above. Fusible links 31 and 32 correspond to the fusible links of OR gate 5 of FIG. 2. Likewise, fusible links 33 and 34 correspond to the fusible links of OR gate 6 of FIG. 2. Still referring to FIG. 7, inverter 54 forms part of the sum array 50 as discussed above in connection with Boolean equivalent. Inverter 54 may be an exclusive OR, containing a fusible link 35 to yield the inverted output Z 1 . Although only two OR gates have been discussed it will be understood by those skilled in the art that a greater number of OR gates 5, 6 may be added. 
     Twelve OR gates are implemented in the preferred embodiment of the sum array 50 resulting in a programmable logic array PLA 101 containing 22 inputs, 12 outputs and 40 P-terms, i.e., 22 input buffers, 40 AND gates, and 12 OR gates. The static testing of PLA 101 requires 1,840 steps. The test sequence is shown in Table 2 and 2A. Test No. 1-46 is conducted in accordance with numbers 1-46, test number 47-92 consists of repeating the test sequence of numbers 1-46 of Table 2 varying the select 2 control inputs as indicated in Table 2A. Test Nos. 93-138, etc. are repeated until 1,840 steps have been completed. This sequence checks the inputs of all the gates of the PLA 101. It will be appreciated by those skilled in the art that the steps may be done manually or may be implemented using automated means, such as computer driven test signals. 
     The dynamic testing of PLA 101 requires the 44 steps of Table 2B. 
     While there has been shown what is considered to be the preferred embodiment of the invention, it will be manifest that many changes and modifications can be made therein without departing from the essential spirit and scope of the invention. It is intended, therefore, in the annexed claims, to cover all such changes and modifications which fall within the true scope of the invention. 
     
         TABLE 2   &#34;0&#34; = 0.0 V &#34;0&#34; = 0.0 V &#34;1&#34; = -0.5 V N &#34;1&#34; = -1.2 V I I I I I I I I I I I I I I I I I I I I I I Z Z Z Z Z Z Z Z Z Z Z Z U T T 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 0 0 0 0 0 0 0 0 0 1 1 1 M T C 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2    1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1  1  2 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0  3 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0  4 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0  5 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0  6 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0  7 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0  8 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0  9 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 10 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 11 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 12 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 13 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 14 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 15 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 16 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 18 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 19 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 20 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 21 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 22 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 23 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 24 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 25 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 46 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 
    
     
                                           TABLE 2A__________________________________________________________________________                        1&#34;0&#34; = 0.0 V                   &#34;0&#34; = 0.0 V&#34;1&#34; = -2.0 V                  &#34;1&#34; = -1.2 V                                   &#34;0&#34; = 0.0 VTest  T T T T T T T T T T T T T    T    &#34;1&#34; = -0.5 VNumber 1 2 3 4 5 6 1 2 3 4 5 6 T    C    INPUTS                                        OUTPUTS__________________________________________________________________________ 1-46 0 0 0 0 0 0 1 1 1 1 1 1 TEST TEST TEST TEST47-92 0 0 0 0 0 1 1 1 1 1 1 0 ALL  ALL  ALL  ALL 93-138 0 0 0 0 1 0 1 1 1 1 0 1 CASES                              CASES                                   CASES                                        CASES139-184 0 0 0 0 1 1 1 1 1 1 0 0185-230 0 0 0 1 0 0 1 1 1 0 1 1231-276 0 0 0 1 0 1 1 1 1 0 1 0277-322 0 0 0 1 1 0 1 1 1 0 0 1323-368 0 0 0 1 1 1 1 1 1 0 0 0369-414 0 0 1 0 0 0 1 1 0 1 1 1415-460 0 0 1 0 0 1 1 1 0 1 1 0461-506 0 0 1 0 1 0 1 1 0 1 0 1507-552 0 0 1 0 1 1 1 1 0 1 0 0553-598 0 0 1 1 0 0 1 1 0 0 1 1599-644 0 0 1 1 0 1 1 1 0 0 1 0645-690 0 0 1 1 1 0 1 1 0 0 0 1691-736 0 0 1 1 1 1 1 1 0 0 0 0737-782 0 1 0 0 0 0 1 0 1 1 1 1783-828 0 1 0 0 0 1 1 0 1 1 1 0829-874 0 1 0 0 1 0 1 0 1 1 0 1875-920 0 1 0 0 1 1 1 0 1 1 0 0921-966 0 1 0 1 0 0 1 0 1 0 1 1 967-1012 0 1 0 1 0 1 1 0 1 0 1 01013-1058 0 1 0 1 1 0 1 0 1 0 0 11059-1104 0 1 0 1 1 1 1 0 1 0 0 01105-1150 0 1 1 0 0 0 1 0 0 1 1 11151-1196 0 1 1 0 0 1 1 0 0 1 1 01197-1242 0 1 1 0 1 0 1 0 0 1 0 11243-1288 0 1 1 0 1 1 1 0 0 1 0 01289-1334 0 1 1 1 0 0 1 0 0 0 1 11335-1380 0 1 1 1 0 1 1 0 0 0 1 01381-1426 0 1 1 1 1 0 1 0 0 0 0 11427-1472 0 1 1 1 1 1 1 0 0 0 0 01473-1518 1 0 0 0 0 0 0 1 1 1 1 11519-1564 1 0 0 0 0 1 0 1 1 1 1 01565-1610 1 0 0 0 1 0 0 1 1 1 0 11611-1656 1 0 0 0 1 1 0 1 1 1 0 01657-1702 1 0 0 1 0 0 0 1 1 0 1 11703-1748 1 0 0 1 0 1 0 1 1 0 1 01749-1794 1 0 0 1 1 0 0 1 1 0 0 11795-1840 1 0 0 1 1 1 0 1 1 0 0 0__________________________________________________________________________ 
    
     
                                           TABLE 2B__________________________________________________________________________N I I I I I I I I I I I I I I I I I I I I I IU 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1       1                                       2                                       2                                       2M 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8       9                                       0                                       1                                       2__________________________________________________________________________ 1  0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       1 3  1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       1 4  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       1 5  1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       1 6  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       1 7  1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       1 8  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       1 9  1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       110  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       111  1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       112  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       113  1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       114  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       115  1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       116  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       117  1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       118  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       119  1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1       1                                       1                                       1                                       120  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       121  1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1       1                                       1                                       1                                       122  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       123  1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1       1                                       1                                       1                                       124  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       125  1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1       1                                       1                                       1                                       126  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       127  1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1       1                                       1                                       1                                       128  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       129  1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1       1                                       1                                       1                                       130  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       131  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1       1                                       1                                       1                                       132  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       133  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1       1                                       1                                       1                                       134  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       135  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0       1                                       1                                       1                                       136  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       137  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       0                                       1                                       1                                       138  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       139  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       0                                       1                                       140  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       141  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       0                                       142  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       143  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       044  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       1                                       1                                       1                                       1__________________________________________________________________________