Abstract:
A digital flash charger controller includes a transformer, a power supply element, and an application-specific integrated circuit (ASIC). A secondary side of the transformer is electrically connected to an energy storage device, and the power supply element is used to supply an electric power to a primary side of the transformer. The ASIC outputs a pulse-width-modulation (PWM) signal to control whether the electric power is input to the primary side, and the ASIC converts a sensing signal generated at the secondary side of the transformer to a digital signal, and tracks a sensing negative edge of the sensing signal according to the digital signal to adjust a cutoff time of the PWM signal, such that the next pulse positive edge approaches the corresponding sensing negative edge.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a flash light charging circuit, and more particularly to a digital flash charger controller capable of enabling a pulse positive edge to approach a sensing negative edge. 
     2. Related Art 
     For a recently common charging circuit, a power supply is combined with a transformer in most cases, and an adjusting device is disposed at a primary side of the transformer, so as to adjust an output current and complete the charging and discharging function of the circuit at the same time. In the recent design field, in most cases, a designer selects to dispose a charging integrated chip (IC) at the primary side of the transformer, so as to implement the charging circuit. 
     A conventional method is mainly to use the charging IC to form the charging circuit, and use analog elements for voltage and current measurements. Therefore, the method is easily affected by noises, resulting in distortion of measured data. Furthermore, the charging IC, and resistors, capacitors, and other passive elements required to be arranged at measure points occupy quite a large area and consume large numbers on a circuit board. Based on the above, for a circuit for charging and discharging a flash light by using the charging IC, the operational complexity is high, and the fabrication cost and working performance are worth being considered. 
     SUMMARY OF THE INVENTION 
     In view of the above, the present invention is a digital flash charger controller, which can not only solve the problem in the prior art that when analog elements are used for voltage and current measurements, the measured data is easily affected by noises, resulting in distortion, but also can replace the conventional charging IC with a logic circuit, so as to reduce the number of used elements and area consumption on a circuit board. 
     The present invention provides a digital flash charger controller, configured to charge an energy storage device. The digital flash charger controller comprises a transformer, a power supply element, and an application-specific integrated circuit (ASIC). The transformer has a primary side and a secondary side, in which the secondary side is electrically connected to the energy storage device. The power supply element is used to output an electric power. The ASIC is used to output a pulse-width-modulation (PWM) signal to control whether the electric power is input to the primary side. The PWM signal has a pulse positive edge and a cutoff time. A sensing signal is generated at the secondary side in response to the primary side, and the sensing signal has a sensing negative edge. The ASIC converts the sensing signal to a digital signal, and tracks the sensing negative edge according to the digital signal to adjust the cutoff time, and the next pulse positive edge approaches the corresponding sensing negative edge. 
     Therefore, in the digital flash charger controller according to the present invention, the ASIC can be used to modulate the cutoff time of the PWM signal, such that the next pulse positive edge of the PWM signal approaches the corresponding sensing negative edge, thereby achieving a high charging and discharging efficiency. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description given herein below for illustration only, and thus are not limitative of the present invention, and wherein: 
         FIG. 1  shows a digital flash charger controller according to an embodiment of the present invention; 
         FIGS. 2A to 2C  are respectively waveform diagrams according to an embodiment of the present invention; 
         FIG. 3A  shows an ASIC according to a first embodiment of the present invention; 
         FIG. 3B  shows an ASIC according to a second embodiment of the present invention; 
         FIG. 3C  shows an ASIC according to a third embodiment of the present invention; 
         FIG. 3D  shows an ASIC according to a fourth embodiment of the present invention; 
         FIG. 3E  shows an ASIC according to a fifth embodiment of the present invention; 
         FIG. 4A  is a schematic view of sampling according to the first embodiment of the present invention; 
         FIG. 4B  is a schematic view of a pulse positive edge approaching a sensing negative edge according to  FIG. 4A ; 
         FIG. 4C  is a schematic view of sampling according to the third embodiment of the present invention; 
         FIG. 4D  is a schematic view of a pulse positive edge approaching a sensing negative edge according to  FIG. 4C ; 
         FIG. 5A  is a data comparison reference diagram of sampling methods according to the first embodiment and the second embodiment of the present invention; and 
         FIG. 5B  is a data comparison reference diagram of sampling methods according to the third embodiment and the fourth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows a digital flash charger controller according to an embodiment of the present invention. Referring to  FIG. 1 , the digital flash charger controller  100  comprises a transformer  10 , an ASIC  20 , and a power supply element  30 . The power supply element  30  is connected to a primary side  11  of the transformer  10 , the power supply element  30  supplies an input voltage V in  (or called an electric power), and the transformer  10  transforms the input voltage and outputs an output voltage V o  through a secondary side  12  thereof. The secondary side  12  is connected to an energy storage device, and charges the energy storage device through the input voltage V in , supplied by the power supply element  30 . For example, the energy storage device may be a capacitor  50  as shown in  FIG. 1 . 
     The ASIC  20  is disposed between the primary side  11  and the secondary side  12 , and is used to generate a PWM signal V PWM  to control whether the input voltage V in  is input to the primary side  11 . According to an embodiment of the present invention, the capacitor  50  is further connected to a flash light, such that the digital flash charger controller  100  charges the flash light. 
     Referring to  FIGS. 2A to 2C , when the PWM signal V PWM  is just switched to a low level, a secondary-side switching current I s  has a maximum secondary-side switching current value I spk , and at this time, a sensing signal V FB  is formed at the secondary side  12  of the transformer  10  in response to the secondary-side switching current I s . When the secondary-side switching current I s  gradually decreases along with the charging time of the capacitor  50  (that is, the time during which the PWM signal V PWM  is at the low level), and the secondary-side switching current I s  finally returns to zero, the sensing signal V FB  gradually disappears, which is defined as a sensing negative edge V− of the sensing signal V FB . 
     Therefore, a time point at which the PWM signal V PWM  is switched from the low level to a high level is a pulse positive edge P+, a time point at which the PWM signal V PWM  is switched from the high level to the low level is a pulse negative edge P−, and the PWM signal V PWM  has a working time T on  and a cutoff time T off . The working time T on  and the cutoff time T off  are respectively time intervals in which the PWM signal V PWM  is at the high level and the low level. 
     Referring to  FIG. 3A , the ASIC  20  comprises an analog-to-digital converter  32 , a PWM controller  34 , and a PWM signal generator  36 . The analog-to-digital converter  32  is used to convert the sensing signal V FB  to a digital signal, sample the sensing signal V FB , and respectively output the digital signal along with different sampling time points. 
     According to a first embodiment of the present invention, the PWM controller  34  comprises a first register  310 , a second register  320 , a differentiator  330 , a first comparator  340 , an indication controller  350 , and a multiplexer  360  and a flip-flop  370  connected between the first register  310  and second register  320  and the analog-to-digital converter  32 . 
     As shown in  FIG. 4A , a user may previously set a positive edge sampling time T+ and a negative edge sampling time T− through software before operations, such that the indication controller  350  triggers sampling at a first sampling time point T 1 , that is, a positive edge sampling time T+ after the pulse negative edge P− of the PWM signal V PWM . 
     Next, after the PWM signal V PWM  finishes the on-going duty cycle T D , and reaches the pulse positive edge P+, the working time T on , and the pulse negative edge P− again, the indication controller  350  triggers sampling at a second sampling time point T 2 , a negative edge sampling time T− after the pulse negative edge P−. 
     Digital signals obtained at the two sampling time points are respectively a component signal V CMP  and an offset signal V OFF . The differentiator  330  is used to obtain a difference value between the component signal V CMP  and the offset signal V OFF , and output a differential signal V DIFF . The first comparator  340  is used to compare the differential signal V DIFF  with a maximum tolerance signal V DUP  and a minimum tolerance signal V DWN . 
     As shown in  FIG. 5A , when the differential signal V DIFF  is larger than the maximum tolerance signal V DUP  (that is, Case-A in the figure), the first comparator  340  outputs a hit indication signal V IND , that is, the offset signal V OFF  sampled by the analog-to-digital converter  32  is a low-level value of the sensing signal V FB . Therefore, the indication controller  350  updates the negative edge sampling time T− and the cutoff time T off  according to the hit indication signal V IND . Here, according to the first embodiment of the present invention, as shown in  FIG. 4A , the next negative edge sampling time T′− is one modulation time interval T Δ  shorter than the previous negative edge sampling time T−. The cutoff time T′ off  of the PWM signal V PWM  is equal to the previous negative edge sampling time T−. 
     Similarly, the analog-to-digital converter  32  performs sampling at a third sampling time point T 3 , the negative edge sampling time T′− after the pulse negative edge P−. If at this time, as shown in  FIG. 5A , the differential signal V DIFF  is smaller than the minimum tolerance signal V DWN  (that is, Case-C in the figure), the indication signal V IND  output by the first comparator  340  is not-hit, that is, the offset signal V′ OFF  sampled by the analog-to-digital converter  32  at the third sampling time point T 3  is a high-level value of the sensing signal V FB . Therefore, the indication controller  350  updates the negative edge sampling time T− and the cutoff time T off  again according to the not-hit indication signal V IND . Here, as shown in  FIG. 4A , the next negative edge sampling time T″− is half a modulation time interval T Δ  longer than the previous negative edge sampling time T′−. The cutoff time T″ off  of the PWM signal V PWM  is half a modulation time interval T Δ  longer than the previous cutoff time T off . 
     Next, the signal processing procedure is performed again based on the offset signal V″ OFF  obtained by the analog-to-digital converter  32  at the fourth sampling time point T 4 , such that the indication controller  350  successively modulates and updates the cutoff time T off  of the PWM signal V PWM  and the negative edge sampling time T− according to the hit or not-hit indication signal V IND . Since the modulation time interval T Δ  may previously be set through software, and is successively halved and decreased along with the time, the user may determine through software in advance that the modulation time interval T Δ  is decreased to a lower limit value within a certain time. As the modulation time interval T Δ  is successively decreased and converged each time, as shown in  FIG. 4B , the pulse positive edge P+ of the PWM signal V PWM  finally approaches the sensing negative edge V− of the sensing signal V FB  generated after the previous cutoff time T off , and the duty cycle T D  of the PWM signal V PWM  is also fixed, and the ASIC  20  according to the embodiment of the present invention continues to track the sensing negative edge V− of the sensing signal V FB  till the position of the sensing negative edge V− of the sensing signal V FB  is changed. 
     In addition, in order to increase the data accuracy, the PWM controller  34  further comprises more than one multiplexer  360  and flip-flop  370 , and a filter  380 .  FIG. 3B  shows an ASIC according to a second embodiment of the present invention. Referring to  FIG. 3B , the PWM controller  34   a  comprises a first register  310 , a second register  320 , a differentiator  330 , a first comparator  340 , an indication controller  350 , and a filter  380 , multiplexers  360  and flip-flops  370  connected between the first register  310  and second register  320  and the analog-to-digital converter  32 . 
     Furthermore, in an ASIC according to a third embodiment of the present invention, as shown in  FIG. 3C , the PWM controller  34   b  comprises a second register  320 , a second comparator  342 , an indication controller  350 , and a multiplexer  360  and a flip-flop  370  connected between the second register  320  and the analog-to-digital converter  32 . 
     Referring to  FIG. 4C , the user may previously set a negative edge sampling time T− through software, so as to ensure that the analog-to-digital converter  32  samples a low-level value of the sensing signal V FB  at the first sampling time point T 1 . 
     The digital signal obtained by the analog-to-digital converter  32  at the first sampling time point T 1  is the offset signal V OFF , and the offset signal V OFF  may be stored in the second register  320  after being triggered by an end of convert signal in  FIG. 3C . The second comparator  342  is used to compare the offset signal V OFF  with a maximum critical signal V THH  and a minimum critical signal V THL . 
     As shown in  FIG. 5B , when the offset signal V OFF  is smaller than the minimum critical signal V THL  (that is, Case-A in the figure), the second comparator  342  outputs the hit indication signal V IND . Therefore, the indication controller  350  updates the negative edge sampling time T− and the cutoff time T off  according to the hit indication signal V IND . Here, as shown in  FIG. 4C , the next negative edge sampling time T′− is one modulation time interval T Δ  shorter than the previous negative edge sampling time T−. The cutoff time T′ off  of the PWM signal V PWM  is equal to the previous negative edge sampling time T−. 
     Similarly, the analog-to-digital converter  32  performs sampling at the second sampling time point T 2 , the negative edge sampling time T′− after the pulse negative edge P−. Here, the offset signal V OFF  sampled by the analog-to-digital converter  32  is stored in the second register  320  after being triggered by the end of convert signal. Then, referring to  FIG. 5B , if the second comparator  342  compares that the offset signal V′ OFF  sampled by the analog-to-digital converter  32  at the second sampling time point T 2  is larger than the maximum critical signal V THH  (that is, Case-C in the figure), the second comparator  342  outputs the not-hit indication signal V IND . Therefore, the indication controller  350  updates the negative edge sampling time T− and the cutoff time T off  according to the not-hit indication signal V IND . Here, the next negative edge sampling time T″− is half a modulation time interval T Δ  longer than the previous negative edge sampling time T′−. The cutoff time T′ off  of the PWM signal V PWM  is half a modulation time interval T Δ  longer than the previous cutoff time T′ off . 
     Next, the offset signal V″ OFF  obtained by the analog-to-digital converter  32  at the third sampling time point T 3  is stored in the second register  320 , and then is compared by the second comparator  342  with the maximum critical signal V THH  and the minimum critical signal V THL . The cutoff time T off  of the PWM signal V PWM  and the negative edge sampling time T− are successively modulated and updated according to the hit or not-hit indication signal V IND  output by the second comparator  342 . 
     As the modulation time interval T Δ  is successively decreased and converged each time, as shown in  FIG. 4D , the pulse positive edge P+ of the PWM signal V PWM  finally approaches the sensing negative edge V− of the sensing signal V FB  generated after the previous cutoff time T off , and the duty cycle T D  of the PWM signal V PWM  is also fixed. 
     In addition, in order to increase the data accuracy, the PWM controller  34   b  further comprises more than one multiplexer  360  and flip-flop  370 , and a filter  380 .  FIG. 3D  shows an ASIC according to a fourth embodiment of the present invention. Referring to  FIG. 3D , the PWM controller  34   c  comprises a second register  320 , a second comparator  342 , an indication controller  350 , and a filter  380 , multiplexers  360  and flip-flops  370  connected between the second register  320  and the analog-to-digital converter  32 . 
     In addition, according to a fifth embodiment of the present invention, the second embodiment ( FIG. 3B ) may be combined with the fourth embodiment ( FIG. 3D ), so as to achieve a preferred embodiment.  FIG. 3E  shows an ASIC according to the fifth embodiment of the present invention. Referring to  FIG. 3E , the sampling principle of the PWM controller  34   d  is a combination of the second embodiment and the fourth embodiment of the present invention, except that the PWM controller  34   d  according to this preferred embodiment further comprises a multiplexer  400 . 
     Therefore, in the digital flash charger controller according to the embodiments of present invention, the sensing signal is sampled by the analog-to-digital converter, and according to two algorithms, the pulse positive edge of the PWM signal is enabled to approach the sensing negative edge of the sensing signal, such that the transformer returns to the primary side for charging, thereby achieving a high working efficiency of the digital flash charger controller.