Abstract:
The present invention discloses one or more network components within a telecommunication network wherein said network is a serial bitstream network and the network components are comprising one or more inverse multiplexers, wherein said multiplexer(s) is/are TDM bonding multiplexers and said multiplexer(s) utilize(s) spare bits and/or FAS bits in a protocol for control of specific functions of the inverse multiplexer(s). The invention further includes a method for inverse multiplexing of one or more serial bitstreams within a telecommunication network wherein said method uses spare bit and/or frame alignment signals from a protocol to: measure differential delay between transmission lines at the receiving end, and/or secure timeslot integrity by compensation for individual link delay, and/or secure correct transmitter and receiver timeslot sequence by link identification, and/or monitor channel availability by block error checking.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to inverse multiplexing within telecommunication, and in particular to inverse multiplexing with TDM Bonding. 
       BACKGROUND OF THE INVENTION 
       [0002]    For digital transmission with bit rates not available on standards like E1/E2/E3 and T1/T2/T3 a flexible bandwidth can be provided with inverse multiplexing. The aggregate bitstream is split in a cyclic manner into several transmission links (E1/T1) and recombined in the remote end. In cable transmission systems the transmission range will be dependent on line bit rate, as seen with SHDSL, hence an increased transmission range will be possible by inverse multiplexing over multiple lines with lower bit rates. The increased range will reduce the complexity between two inverse multiplexers within the network because of the reduced number of repeaters necessary, further, less complexity/components means less service and maintenance, and hence an increased reliability. 
       KNOWN SOLUTIONS 
       [0003]    A known solution is inverse multiplexing with ATM bonding. The ATM inverse multiplexing involves multiplexing and demultiplexing of ATM cells in a cyclic fashion among multiple links to form a higher bandwidth.  FIG. 1  shows ATM inverse multiplexing. 
         [0004]    ATM inverse multiplexing has its basis in ATM networks where each ATM cell has a length of 53 byte with 5-byte header and 48 byte payload. For TDM networks use, the TDM bitstream has to be circuit emulated into an ATM cellstream by ATM circuit emulation.  FIG. 2  shows an ATM inverse multiplexer with circuit emulation. 
         [0005]    The serial bitstream is segmented into ATM cells. However, in ATM with circuit emulation (AAL-1) there is a need of 1 extra byte, Sequence Number field (SN) and Sequence Number Protection (SNP), hence ATM CE-cells have the length of 53-bytes including 47 bytes payload and 6 bytes overhead. Filling up the ATM payload with bits from the serial bitstream creates delay. On lower bit rates this delay can be prohibitive. The efficiency ratio for Circuit emulation is poor with an overhead of approximately 12.5%. 
         [0006]    To meet the requirements of low transmission delay, a minimized overhead, an increased working range, a reduced number of repeaters, reduced service and maintenance, an increased reliability and robustness, as well as higher availability for the transmission systems, a new and inventive mechanism of inverse multiplexing using TDM bonding is disclosed. Compared to the complexity of ATM the invention has among others the following characteristics:
       Low transmission delay   Secure timeslot integrity by compensation for individual link delay   Secure correct transmitter and receiver timeslot sequence by link identification   Monitor channel availability by block error checking (CRC)   By monitoring CRC and RAi E-bit dynamically. Adapt transmission rate to available bandwidth. This will ensure that transmission lines can be disconnected in a controllable fashion, thus avoiding loosing all the bandwidth but only a fraction, where the fraction is the number of disconnected transmissions lines divided by the total number of transmission lines.       
 
         [0012]    These and other features will be met by the present invention. 
       SUMMARY OF THE INVENTION 
       [0013]    It is an object of the present invention to provide a method and a system avoiding the above described problems. 
         [0014]    The features defined in the independent claims enclosed characterize this method. 
         [0015]    In particular, the present invention provides a method and a system within inverse multiplexing, said system comprises one or more network components within a telecommunication network, wherein said network is a serial bitstream network and the network component(s) is/are comprising one or more inverse multiplexers wherein said multiplexer(s) are/is TDM bonding multiplexers. Said method describes a method for inverse multiplexing of one or more serial bitstreams within a telecommunication network wherein said method uses spare bit and/or frame alignment signals from a protocol to: 
         [0016]    measure differential delay between transmission lines at the receiving end, and/or 
         [0017]    secure timeslot integrity by compensation for individual link delay, and/or 
         [0018]    secure correct transmitter and receiver timeslot sequence by link identification, and/or 
         [0019]    monitor both end of the channel for availability by block error checking and local and remote alarm indications. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0020]    In order to make the invention more readily understandable, the discussion that follows will refer to the accompanying drawing. 
           [0021]      FIG. 1  shows ATM inverse multiplexing as known from the prior art. 
           [0022]      FIG. 2  shows an ATM inverse multiplexer with circuit emulation as known from the prior art. 
           [0023]      FIG. 3  shows a basic frame. 
           [0024]      FIG. 4  shows the differential delay between transmission lines at the receiving end. 
           [0025]      FIG. 5  shows TDM bonding of a 2.048 Mbit/s bitstream on 4 cable pairs with SHDSL transmission according to a first embodiment of the present invention, transporting 512 kbyte payload on each pair. 
           [0026]      FIG. 6  shows the transport of 8 Mbit/s on 4 E1 lines through a SDH or PDH network according to a second embodiment of the present invention. 
           [0027]      FIG. 7  shows a typical practical use of the inverse multiplexer in an SDH access multiplexer for mixed service with TDM and IP/ATM according to a third embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]    The present invention discloses an arrangement and a method for the use of said arrangement, where the arrangement&#39;s main feature is its versatility and flexibility within inverse multiplexing and particularly within inverse multiplexing with TDM bonding. In the following a detailed description of the present invention with support in the accompanying drawings is given. 
         [0029]    FAS with Basic frame is in accordance with ITU rec. G.704. The Basic frame can be used as a “building block” in a hierarchical system where several basic frames can constitute of parts in a multiframe; a multiframing of 8&#39;2 basic frames is also in line with the G.704. The spare bits in the multiframe are used for the control of the specific functions of the inverse multiplexer in accordance with the present invention. Table 1 shows the structure of the G.704 basic frame. 
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
               
               
               
               
               
             
               
               
             
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Structure of the G.704 basic frame (Ts0). 
               
             
          
           
               
                   
                 Bit number 
               
             
          
           
               
                 Alternate frames 
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
                 7 
                 8 
               
               
                   
               
               
                 Frame containing the 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                 frame alignment signal 
               
             
          
           
               
                   
                 Frame alignment signal 
               
             
          
           
               
                 Frame not containing the 
                 1 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                 frame alignment signal 
               
               
                   
               
             
          
         
       
     
         [0030]    It is bit number 2 in the table, that decides whether it is a frame alignment signal or not. If this bit is set to 0 (zero) we will have a frame alignment signal. 
         [0031]    A basic frame is always 125 μs ( FIG. 3 ), and the length of the payload will be decided by the bit rate, thus the higher the bit rate the bigger the payload. 
         [0000]    
       
         
               
             
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 shows the G.704 multiframing. 
               
             
          
           
               
                   
                 Sub- 
                   
                   
               
               
                   
                 Multiframe 
                 Frame 
                 Bits 1 to 8 of the frame 
               
             
          
           
               
                   
                 (SMF) 
                 number 
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
                 7 
                 8 
               
               
                   
                   
               
             
          
           
               
                 Multi- 
                 I 
                 0 
                 C 1   
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                 frame 
                   
                 1 
                 0 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                   
                   
                 2 
                 C 2   
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                   
                   
                 3 
                 0 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                   
                   
                 4 
                 C 3   
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                   
                   
                 5 
                 1 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                   
                   
                 6 
                 C 4   
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                   
                   
                 7 
                 0 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                   
                 II 
                 8 
                 C 1   
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                   
                   
                 9 
                 1 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                   
                   
                 10 
                 C 2   
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                   
                   
                 11 
                 1 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                   
                   
                 12 
                 C 3   
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                   
                   
                 13 
                 E 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                   
                   
                 14 
                 C 4   
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
               
               
                   
                   
                 15 
                 E 
                 1 
                 A 
                 S a4   
                 S a5   
                 S a6   
                 S a7   
                 S a8   
               
               
                   
               
             
          
         
       
     
         [0032]    Applying a number of transmission lines between nodes will result in a differential delay between the lines as indicated in  FIG. 4 . The FAS-multiframe gives the reference for measurement of differential delay between transmission lines in the receiving end. In table 2, bit column 1 is the time compensation bit for multiframes, hence maximum differential delay is the length of the multiframe which equals to 2 mS. The FAS can either run in Basic frame or multiframing. In Basic frame the maximum delay is 125 μs. Link capacity adjustment can be done by the use of the CRC-4, E-bit and A-bit for the monitoring of channel availability. 
         [0033]    The Sa bit can be utilized as line identification bit to compensate for pair crossing; this is of particular interest where cable systems having short time delay is used. The principle will work for up to 32 lines, in that it is 5 Sa bits available, if pair crossing is detected, this will be compensated for at the receiving end. 
         [0034]    Alternatively, the spare bit can be used for sequence numbering forming a multi-multiframe pattern of up to 32 multiframes. A delay compensation of 32×2 mS=64 mS can be achieved. The length of the payload is variable from N=1 and upwards, depending on bit rate, in that a basic frame is 125 μs, if standards are applied, E1 . . . T1. . . , the payload will increase step by step depending on the bit rate adapted to these standards. In  FIGS. 5 ,  6  and  7  examples of the use of the inverse multiplexer are shown. 
         [0035]    The shown c bits in table 2 indicate the checksum. 
         [0036]    For the TDM inverse multiplexer, the transmission overhead is limited to 3% compared to the ATM with 12.5%. Transmission delay is kept at a minimum as there are no cells to be filled up. For ATM based inverse multiplexer, the aggregate will be reduced to less than 7.264 Mbit/s. 
       A First Preferred Embodiment of the Invention 
       [0037]    With reference to  FIG. 5 , TDM bonding of a 2.048 Mbit/s bitstream (E1) on 4 cable pairs with SHDSL transmission is shown. Employing the traditional solution for this scenario would mean a reduced node to node range; hence there would have been an increased need of repeaters, compared with the first preferred embodiment of the present invention. A reduced bit rate employing 4 lines will increase the working range and thus decrease the need of repeaters. Less repeaters means less service and maintenance, as well as increased quality. Employing the solution with ATM inverse multiplexer with circuit emulation, will, as earlier described, increase the complexity as well as introducing unnecessary transmission delay given that each cell of 47 bytes has to be filled up with traffic, before transmitted. 
         [0038]    The solution shown in  FIG. 5 , on the contrary, gives an effective utilization of the network capacity. 
         [0039]    As shown in the figure, one or more 2.048 Mbit/s TDM bitstreams are transported between two or more nodes, employing the present invention. The bitstream(s) is/are bonded in the block assigned TDM bonding according to the methods depicted in table 1 and 2 and the accompanying text. After the bonding process we will have four lines each with a payload of 512 kbit/s, derived from 
         [0000]      2.048  Mbit/s/ 4=512  kbit/s,    
         [0000]    adding to the payload is the FAS of 64 kbit/s resulting in a bit transfer rate of 576 kbit/s per pair of cables and 8 byte payload and 1 byte overhead per frame. ATM inverse multiplexing would have given an overhead to payload ratio of 6/8. 
       A Second Preferred Embodiment of the Invention 
       [0040]    With reference to  FIG. 6  a second preferred embodiment of the present invention is shown. In this figure one or more 8 Mbit/s bitstreams are transported over a PDH or SDH network between two or more nodes/networks, employing the present invention. The TDM bonding of the original bitstream results in 4 E1 lines, where each of these lines has a bit transfer rate of 2.048 Mbit/s. Each basic frame has, FAS included, a length of 125 μs, thus the basic frame is of 32 bytes length, derived from the expression: 
         [0000]      (2.048 Mbit/s*125 μs)/8. 
         [0000]    The payload is of 31 bytes length, whereas the overhead is of 1 byte length per frame, resulting in a payload transfer rate per line of: 
         [0000]      ((32−1)*8)bit/125  μs= 1.984  Mbit/s.    
         [0000]    The overhead ratio is held at a minimum compared to what is the case in traditional solutions; it is given from 
         [0000]      (2.048-1.984)Mbit/s/1.984 Mbit/s˜3%. 
         [0000]    The aggregate payload bit transfer rate is 
         [0000]      4*1.984  Mbit/s= 7.936 
         [0041]    and the transmission delay is kept at a minimum as there are no cells to be filled up. For ATM Based inverse multiplexer, the aggregate will be reduced to less than 7.264 Mbit/s. 
         [0042]    As depicted in  FIG. 6 , the transmission between the two or more TDM bonding mux&#39;es is over a SDH or PDH network. Within this network there can be several network components such as switches, repeaters etc., all of whom might add to the differential delay at the receiving end. Thus, the present invention&#39;s capability for delay compensation can be of uttermost importance. 
       A Third Preferred Embodiment of the Invention 
       [0043]    In  FIG. 7  a typical practical use of the inverse multiplexer in an SDH access multiplexer for mixed service with TDM and IP/ATM is shown. 
         [0044]    The STM-1 multiplexer can be used for combined E1 TDM channels, mapped into VC-12 and for E1 channels forming a transparent high capacity data channel via the inverse multiplexer, also mapped into VC-12. 
         [0045]    In  FIG. 7 , 16 E1 lines are forming a 32 Mbit/s transparent channel which can be used for packet transmission like IP or ATM. 
         [0046]    The hybrid solution shown can be expanded to cover signal lines with bit transfer rates different from those shown in this and the previous examples, furthermore solutions employing other virtual containers may be applied, as well as E1/E2/E3 and T1/T2/T3 signals. Wherever the bonding technique described with support in table 1 and 2 is applicable, the present invention will be applicable. 
         [0047]    The preferred embodiments above are meant to make the invention more readily understandable. However, wherever TDM signals are applied between a transmitter and a receiving end, and one wishes to reduce the bit rate between the transmitter and the receiver without reducing the overall bandwidth, as long as there are enough spare bits for ?-t handling, the present invention is applicable. 
         [0048]    Note that while in the foregoing, a detailed description of particular embodiments of the present invention has been provided, it is to be understood that equivalents are to be included within the scope of the invention as claimed. 
       Abbreviations 
       [0049]    AAL ATM Adaptation Layer. A collection of standardized protocols that provide services to higher layers by adapting user traffic to a cell format. The AAL is divided into the Convergence Sublayer (CS) and the Segmentation and Reassembly (SAR) sublayer. 
         [0050]    AAL-1 ATM Adaptation Layer Type 1. Protocol standard used for the transport of Constant Bit Rate (CBR) traffic (for example, audio and video) and for emulating TDM-based circuits (for example, DS1, E1). 
         [0051]    ATM Asynchronous Transfer Mode. A broadband switching and multiplexing, connection-oriented, high performance and cost-effective integrated technology for supporting B-ISDN services (i.e. multimedia). Since no clock control is necessary it is called asynchronous (see also STM). Information is transmitted at very high rates (up to hundreds of Mbps) in fixed-size packets called cells. Traffic streams are distinguished and supported according to different QoS classes. 
         [0052]    CE Circuit emulation. A virtual-circuit (VC) service offered to end-users where the characteristics of an actual, digital bit-stream (for example, video traffic) line are emulated (for example, a 2 Mbps or 45 Mbps signal). 
         [0053]    CRC Cyclic Redundancy Check. A bit error detection technique that employs a mathematical algorithm, which calculates on the basis of the transmitted bits, a value which it attached to the information bits in the same packet. The receiver, using the same algorithm, recalculates that value and compares it to the value received. If the two values do not agree the transmitted packet is then considered to be in error. 
         [0054]    DS-1 Digital Signal 1. Physical Interface for digital transmission at the rate of 1,544 Mbps. Also known as T-1 standard, DS-1 can simultaneously support 24 DS-0 circuits. 
         [0055]    E1 European Digital Signal 1. European standard for digital physical interface at 2.048 Mbps. 
         [0056]    E2 European Digital Signal 2. Data signal that carries four multiplexed E-1 signals. Effective data rate is 8448 Mbps. 
         [0057]    E3 European Digital Signal 3. European standard for digital physical interface at 34.368 Mbps. It can simultaneously support 16 E-1 circuits. 
         [0058]    FAS Frame Alignment signal. 
         [0059]    PDH Plesiochronous Digital Hierarchy. A hierarchy that refers to the DS-1, DS-1, DS-2 and DS-3 interfaces for digital transmission. Originally developed to efficiently carry digitized voice over twisted pair. 
         [0060]    RAi Remote Alarm identification. 
         [0061]    SDH Synchronous Digital Hierarchy. A hierarchy that designates signal interfaces for very high-speed digital transmission over optical fibre links. 
         [0062]    SHDSL Single-pair high speed Digital Subscriber Line. 
         [0063]    SN Sequence number. Part of the header of the SAR-PDU (2 bits in AAL1, 4 bits in AAL3/4). SN is used as a sequence counter for detecting lost, out-of-sequence or misinserted SAR-PDU&#39;s. 
         [0064]    SNP Sequence Number Protection. A 4-bit field in the header of the AAL1 SAR-PDU. This field contains the CRC and the parity bit fields. 
         [0065]    T1 A TDM digital channel carrier that operates at a rate of 1.544 Mbps. Known also as a repeater system, it is often referred as DS-1. 
         [0066]    T2 The North American standard for DS-2 (Digital Signal Level 2). T-2 operates at a signaling rate of 6.312 Mbps, and has four times the capacity of T-1. It is generally used only in carrier backbone network. 
         [0067]    T3 A TDM digital channel carrier that operates at 44.736 Mbps. It can multiplex 28 T1 signals. The term is often used to refer to DS-3. 
         [0068]    TDM Time-Division Multiplexing. A technique for splitting the total bandwidth (link capacity) into several channels to allow bit streams to be combined (multiplexed). The bandwidth allocation is done by dividing the time axis into fixed-length slots; a particular channel can then transmit only during a specific time slot. 
         [0069]    VC Virtual container. Definition: A VC is the information structure used to support path layer connections in the SDH. It consists of information payload, and path overhead (POH) information fields organized in a block frame structure which repeats every 125 or 500 microseconds. Alignment information to identify VC frame start is provided by the server network layer. Two types of VCs have been identified:
       a) Lower order VC: VC-n (n=1, 2, 3); this element comprises a single C-n (n=1, 2, 3) plus the lower order VC POH appropriate to that level.   b) Higher order VC: VC-n (n=3, 4). This element comprises either a single C-n (n=3, 4) or an assembly of tributary unit groups (TUG-2s or TUG-3s), together with VC POH appropriate to that level.       
 
         [0072]    VC-11 Virtual Container of SDH with 1544 kbit/s transmission rate. 
         [0073]    VC-12 Virtual Container 12, the termination of a higher order VC for the purpose of adding, dropping, or cross-connecting any individual lower order VC or VC group. 2048 kbit/s.