Abstract:
A system and a method for calculating a value for the “Band Zero” (B) contribution to the processing of a digital signal by processing the separate parts of the signal at separate times. The method increases operating speed of a feedback circuit, for example, by providing a processing path ( 402   f ) that is not on the main high-speed processing path of a system such as a read channel of a disk drive. By processing the most time-consuming determination “in parallel,” the high-speed portion of processing is able to maintain an optimum throughput. The method also lends itself to processing in those applications where more than one mode is used. For example, when used in a read channel ( 113 ) of a disk drive ( 100 ) employing a FIR filter, three modes are desired: FIR-bypass, acquisition, and data tracking. Being able to switch easily among the three modes provided for in a read channel ( 113 ) of a disk drive ( 100 ) demonstrates the adaptability of the method and supporting structure to a broad class of feedback circuits used in systems employing high throughput rates.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application claims the benefit of prior filed copending provisional application Ser. No. 60/122,219, filed Mar. 1, 1999. 
     This application is a continuation-in-part of copending patent application 09/224,364, filed Dec. 31, 1998, which is a continuation-in-part of copending patent application 09/256,568, filed Feb. 24, 1999, which is a continuation-in-part of copending patent application 09/258,045, filed Feb. 25, 1999, which is a continuation-in-part of copending patent application 09/256,420, filed Feb. 24, 1999, which is a continuation-in-part of copending patent application 09/258,594, filed Feb. 26, 1999, which is a continuation-in-part of copending patent application 09/258,827, filed Feb. 25, 1999, all of which are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to improvements in systems, methods, and circuits for increasing throughput rate and operational speed of a signal processor, and more particularly, to improvements in systems, methods, and circuits to perform the processing necessary to determine “band zero” of a digital signal while separated from the high-speed path in which other parts of the signal are being processed. 
     2. Relevant Background 
     In the construction of mass data storage devices, or the like, in particular in the construction of the data channel used in digital magnetic recording systems, or the like, there has been significant recent interest in Partial Response Maximum-Likelihood (PRML) signaling techniques. The most common PRML systems are PR 4 ML (a partial response class  4 ) and EPR 4 ML (extended partial response class  4 ). Maximum-likelihood detectors, which use a Viterbi algorithm, are generally used in these partial response channels. 
     The various partial response techniques are generally referred to by the particular partial response target that it uses. For example, a PR 4  partial response target is (1−D)* (1+D), and an EPR 4  partial response target is (1−D)*(1+D) 2 , where D is a delay operator equal to e jωt , where ω is frequency, and t is delay time. Recently an EEPR 4  (or E 2 PR 4 ) response level has been introduced in which the EEPR 4  partial response target is (1−D)*(1+D) 3 . 
     In general, the various partial response techniques that are employed use different sampling times at which the signal that is derived from the disk drive transducer are sampled and measured. A PR 4  Partial Response System typically results in data that is contained in three separate bands, often referred to as band  1 , band  0 , and band − 1 . An EPR 4  technique results in sampling bands commonly referred to as band  2 , band  1 , band  0 , band − 1 , band − 2 . The data within the bands is not contained on a single time band value, but instead, have a distribution about the centerline of the band. 
     In the past, processing the data to separate it into its respective bands required considerable data processing with serial comparisons. Thus, calculation of band data is usually a data processing bottleneck since the subsequent steps rely on it and cannot be performed until the band has been calculated. Therefore, with increased emphasis on high-speed data acquisition and processing, this band determination processing is being regarded as one of the processes that slows the overall processing time for the data. 
     In general, a “digital signal” is a signal that conveys a discrete number of values at discrete times. This is in contrast an “analog signal,” i.e., a signal that conveys an infinite number of values on a time continuum. A signal having a digital form may be generated from an analog signal through sampling and quantizing the analog signal. Sampling an analog signal refers to “chopping” the signal into discrete time periods and capturing an amplitude value from the signal in selected ones of those periods. The captured value becomes the value of the digital signal during that sample period. Such a captured value is referred to as a sample. 
     Quantizing refers to approximating a sample with a value that may be represented on a like digital signal. For example, a sample may lie between two values characterized upon the digital signal. The value nearest (in absolute value) to the sample may be used to represent the sample. Alternatively, the sample may be represented by the lower of the two values between which the sample lies. After quantization, a sample from an analog signal may be conveyed as a digital signal. This is the resultant signal soon which the digital circuit may operate. 
     A digital signal processor (DSP) transforms an input digital signal to an output digital signal. For the digital filter, the transformation involves filtering out undesired portions of the received digital signal. An original analog signal may be represented as a sum of a plurality of sinusoids. Each sinusoid oscillates at a particular and unique frequency. Filtering is used to remove certain frequencies from an input signal while leaving other frequencies intact. 
     Programs executing on digital circuits often do so in “real-time.” Real-time programs can be regarded as programs that must execute within a certain time interval. Regardless of whether a program executes in a large period of time or a small period of time, the result of executing the program is the same. However, if real-time programs attempt to execute in an amount of time longer than the required time interval, then they no longer will compute the desired result. 
     Programs executing on a digital circuit are real-time programs, since the instructions manipulate a sample of a digital signal during the interval preceding the receipt of the next sample. If the program cannot complete manipulating a sample before the next sample is provided, then the program will eventually begin to “lose” samples. A lost sample does not get processed; therefore, the output signal of the digital circuit will no longer contain all of the information from the input signal provided to the digital circuit. This potential for losing samples is reduced by a preferred embodiment of the present invention, while maintaining a required throughput rate. 
     A digital circuit may be programmed to modify signals. The number of instructions required to do this is relatively fixed. The digital circuit must be capable of executing this relatively fixed number of instructions on any given sample before the next sample of the series is provided. 
     Besides considering the throughput of a digital circuit, most all of the design parameters have associated cost factors that should be considered. One important cost factor is the silicon area needed to “house” the digital circuit. Those circuits that are manufactured on a relatively small silicon chip are less expensive than those requiring a large chip. Therefore, an easily manufacturable, small (low cost) digital circuit is desirable. 
     A “pipelining” method may be used to achieve better filter performance at high input data rates. One cost of using this method, however, is increased latency. At very high speeds, such as are being seen with newer systems, conventional pipelining falls subject to the law of diminishing returns. The pipelining “overhead” now consumes a larger percentage of the benefits gained from higher clock speeds. The overhead consists of a required latching or reclocking stage for every pipelining command. Generally, the performance improvement for one level of pipelining is less than two while the “on-chip” cost increase is greater than two. All the while this is occurring at the very high clock rate of the input data. The preferred embodiment of the present invention addresses the clock rate limitation imposed by a high data rate input signal, in particular during feedback control operations. 
     SUMMARY OF THE INVENTION 
     A preferred embodiment of the present invention provides a system and method for increasing the speed of operation of a high-speed digital circuit, by providing separate paths for processing parts of the input signal, without appreciably increasing “on-chip” real estate. 
     Processing parts of a signal in separate paths enables optimization of he high-speed portion of a digital circuit, providing adequate time for processing each sample in the high-speed portion. By having one path operate on a calculation intensive portion of the processing and providing for certain operations to be made common to each path, required on-chip area is also reduced compared to conventional digital circuits of comparable performance. 
     A preferred embodiment of the present invention Is implemented for use by a timing recovery circuit. In a preferred embodiment of the present invention, the signal that is being processed within a timing recovery loop has been previously encoded in a partial response (PR) architecture for further processing in a maximum likelihood (ML) detector, such as a Viterbi Detector. Further, the use of simple two-way multiplexers, i.e., +1 and −1, in a preferred embodiment of the present invention on the high-speed path(s) facilitates higher operating frequency. 
     Some of the salient advantages of the present invention are that it: 
     significantly increases throughput and operational speed. 
     reduces required silicon area on the chip, considering the performance improvement. 
     uses simpler multiplexers. 
     reduces latency. 
     enables separate circuit paths to share functions. 
     reduces fabrication cost. 
     enables optimum processing on high-speed portions of a digital circuit. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The invention is illustrated in the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a disk drive and its read channel circuit, together with inputs and outputs therefrom in which the system and method in accordance with a preferred embodiment of the invention may be employed. 
     FIG. 2 is a block diagram of a portion of the read channel circuit of FIG.  1 . 
     FIG. 3 is a block diagram showing a conventional phase lock loop therefrom in which the system and method in accordance with a preferred embodiment of the invention may be employed. 
     FIG. 4 is a detailed block diagram of a portion of a phase detector in a data-tracking mode according to a preferred embodiment of the invention. 
     FIG. 5 depicts a gain gradient circuit having a band zero determination aside function similar to that of the phase detection circuit shown in FIG.  4 . 
     In the various figures of the drawings, like reference numerals are used to denote like or similar parts. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a diagram of a portion of the parts of a mass data storage device  100 , including part of its read channel circuitry  113 . The hard disk drive  101  contains several magnetic disks  111 , each containing data on its magnetic surface  117 , and each associated with an arm  103  controlled by a voice coil motor  104 . The arms are connected to a spindle  102  that is rotated by a spindle motor (not shown). 
     At the outer end of each arm  103  lies a read/write head  105  for reading from and writing to a respective one of the disks  111 . A magnetic disk output signal  112  from read/write head  105  is input to a preamplifier  115  that, in turn, outputs amplified signal  116  to read channel cIrcuit  113 . The output signal is transmitted on a path  119  from the read channel circuit  113  to a controller or digital signal processor  114 . A preferred embodiment of the present invention is contained within the read channel circuitry  113 . 
     With reference now additionally to FIG. 2, additional details of the read channel circuit  113  of FIG.  1  and circuitry for applying time and gain control are shown. FIG. 2 is provided as an example of a method of providing timing and gain control, permitting an understanding of the concepts leading to a preferred embodiment of the present invention. 
     Shown as an input to the circuit  113  is the output signal  116  of preamplifier  115  of FIG. 1 that conditioned the read signal  112  from the disk  111 . The analog circuitry  204  may be, for example, an analog CTF filter, which provides gain amplification and initial signal conditioning during signal processing within the read channel circuitry  113 . A conditioned analog signal is provided on path  205  from the analog circuitry  204  to an analog-to-digital converter (ADC)  202 . A preferred embodiment includes a 6-bit digital signal output from ADC  202  on path  206  to a FIR filter  207  having taps (not shown), each associated with a coefficient  208  provided by source (not shown) external to the read channel circuitry  113 . An 8-bit filtered digital output signal is provided on path  209  to a detector  210  for output on path  119  to the digital signal processor  114 . 
     In one embodiment, a second path  211  is provided for feedback purposes to a band/error detection circuit  212 . It is the modification to the band/error circuit  212  that comprises one example of a preferred embodiment of the present invention. The band/error detection circuit  212  has a first output, which is a 5-bit error signal on path  213  and a second output, which is a 3-bit signal hand on path  214 , to a gradient circuit  203  containing timing and gain gradient circuits (not separately shown). 
     An output signal is provided from the gradient block  203  on path  215  to automatic gain control (AGC) circuitry  216  from a gain gradient circuit within the block  203 . From the AGC  216  an adjustment, or feedback, signal is provided on path  221  to the analog circuitry  204 . Another output signal from the timing gradient circuit in block  203  is sent on path  219  to a phase locked loop (PLL)  201 . From the PLL  201 , a feedback of phase adjustment signal is sent on path  220  to the ADC  202 . 
     With reference now additionally to FIG. 3, a block diagram of a timing recovery loop  300  is shown. The digital PLL  201  employs a VCO  301  to generate the sampling clock for the ADC  202 , which, as described above, receives an input from the analog circuitry  204  along path  205 . In order to lock the PLL  201  to a required sampling frequency and phase, a sinusoidal signal (not shown) at one-fourth the sampling frequency (¼T, where T is the bit period) is injected into the ADC  202 . An error is computed using the results from timing gradient (TG) circuit(s) (not shown, but included in block  203  of FIG.  2 ). 
     Timing gradient calculator  302  provides an input over path  304  to a proportional-and-integral (P&amp;I) loop filter  303  that is connected via path  305  to the VCO  301 . In turn, the VCO  301  receives a reference signal from an external source (not shown) over path  306 . The VCO  301  provides adjustment or feedback signals over paths  507  to the timing gradient calculators  302  as well as to the ADC  202 , as described above. It should be noted that what is conventionally termed as a phase detector is included herein. In the final stages of ADC  202  and the timing gradient calculators as depicted by dashed block  310 . FIG. 3 is provided as an example of a method of providing timing and phase control, permitting an understanding of the concepts leading to a preferred embodiment of the present invention. 
     FIG. 4 depicts a preferred embodiment of the present invention operating in data-tracking mode. Viewing the top half of FIG. 4, i.e., the EVEN bit stream, FIR_DTO_E  432  on path  402  is processed on path  402   a , with a most significant bit (MSB) ( 7 ) being provided to determine the sign SIGN_E at XNOR gate  403  together with signal CTK  2   433  on path  404 . The clock signal CLK  2  is also provided to the bottom “mirrored” half of circuit  400  along path  404   a . Details of the construction and operation of the mirrored circuit halves are set forth in copending patent application Ser. No. 09/256,420, filed Feb. 24, 1999, incorporated herein by reference. It should be noted that XNOR gate  403  and XOR gate  423  are used only when there is internal parallelism, i.e., if an external parallel structure is used, the gates  403  and  423  would not have to be used. 
     Following path  402  to paths  402   b  and  402   c , however, four MSBs of signal FIR_DTO_E  432  are provided to overflow detection circuit OVDET  405 . Also provided to OVDET  405  is a semi-static control signal MODE (e.g., PR  4  vs. EPR  4  mode selection) from an external controller (not shown) on path  406 . The 2-bit signal BAND_OV_E is output from OVDET  405  on path  407  as an input to 3-way multiplexer  408 , i.e., multiplexer  408  is capable of handling bit values 1, 0, and −1. 
     On paths  402 ,  402   b ,  402   d  and  402   e , 5 bits of FIR_DTO_E  432  of the 4-bit remaining signal are provided as signal ERR_E to multiplexer  408  for selection by the control signal BAND_OV_E, provided on path  407 . The binary designators 01111 (selected through the value of +1) and 10001 (selected through the value of −1) are used by multiplexer  408 . 
     The output from the multiplexer  408  is provided as a 5-bit signal on path  411   a  to circuit NEG  412 , where it is negated and passed via path  411   c  as a “signed” 6-bit signal to a simple two-way multiplexer  413 . Also provided to multiplexer  413  is a 1-bit signal SIGN_CK_O over path  424 . SIGN_CK_O is generated by processing a 1-bit signal SIGN_ 0  sent along path  401  with the signal CLK  2   433  sent along path  404  to XOR gate  423 , with SIGN_CK_ 0  being the output of XOR gate  423 . The output from multiplexer  408  is also sent directly to multiplexer  413  as band overflow corrected error 5-bit signal ERR_OV_E on path  411   b.    
     The 4 MSBs of signal FIR_DTO_E are provided over paths  402 ,  402   b ,  402   d , and  402   f  to a separate Band Zero (B) detector  409  for processing as the high-speed portion of signal processing has been accomplished. Also provided to circuit B  409  on path  410  is signal MODE from an external controller (not shown) having the same function as signal MODE placed on path  406  described above. Providing signal MODE separately is necessary because the Band Zero detector  409  has been “separated” from all other calculations in the high-speed portion of the circuit. 
     Output from B circuit  409  is provided as a 1-bit signal BRAND_Z_over path  414  to a multlplexer  415 . Also provided directly to multiplexer  415  is a 6-bit signal BANDZ_ERR_E over paths  416  and  416   a  from multiplexer  413 . Over paths  416  and  416   b  signal BANDZ_ERR_E is provided to summer  417  where it is combined with a signal over path  426  from the “mirror” processing of the odd bit stream FIR_DTO_ 0   431  (starting as an 8-bit signed signal at path  401 ). The output of the summer  417  is transmitted over path  418  for selection in multiplexer  415  of signals BAND_Z_E on path  414  and BANDZ_ERR_E on paths  416  and  416   a , as well as the mirror signals BAND_Z_ 0  on path  425  and BANDZ_ERR_E on paths  426  and  426   a.    
     A 6-bit signal is sent from the multiplexer  415  to register  420  over path  419 . Also, incut to register  420  is a clock signal CLK, at the full period T, over path  421 . Signal TC is provided as a 6-bit output over path  422  for use in a timing recovery loop or PLL (not shown). Note that this signal has been processed so that not only will the timing gradient control the timing recovery but also match the proper band of operation in the case where more than one PRML architectures is implemented, e.g., PR 4  and EPR 4 , in a system such as a read channel of a mass data storage device. Note that separation of the B determination as depicted in boxes  450  and  451  allows processing on the high-speed portion of circuit  400  to be optimized. 
     It can be seen from FIG. 4 that the upper and lower halves of the circuit simultaneously processes their respective input signals along two paths. The input signal on each respective path is of unknown value, although the data may lie in one of three bands. The first band is referred to as “band  0 ” and has a zero value. The second band is referred to as “band  1 ”, and has values above the values of band  0 . The third band is referred to as band − 1 , and has a values below band  0 . Although the circuit of FIG. 4 is described in the context of processing data that lies within one of three bands, it should be understood that the invention is applicable to processing signals having values in more than three bands, for example, five bands, as may encountered in an EPR 4  tracking mode, and so on, with appropriate modifications that will be evident to those having ordinary skill in the art. As mentioned above, in any event, the data recovered from the transducer of the mass data storage device with which the circuit is associated may lay in a random distributed pattern about the center line of the respective band in which it lies. 
     The selection of an EPR 4  or PR 4  mode is made by the mode signal applied at mode inputs  406  and  410 , and the corresponding inputs in the lower half of the circuit. As mentioned, the operation of the circuit  400  in the embodiment illustrated is intended for use in the data tracking mode of a PR 4  mode signal, although with appropriate modifications, the circuit may be used in the data acquisition mode of an EPR 4  mode signal. 
     As can be seen, the input signal on line  402  is processed first in the signal processing section denoted by the dotted line  453  that includes the overflow detector  405  and multiplexers  408  and  413 . The processing in this section determines the value of the modulated error by the “hasty” band of the input signal and ascribes to it a predetermined sign, for purposes described below in detail. More particularly, at least a portion of the input signal on line  402  is conducted via line  402   e  to a multiplexer  408 , and, additionally, to an overflow detector  405 . 
     In the data tracking mode of operation, the overflow detector  405  determines whether the signal on line  402 C exceeds a predetermined band value in either direction from −1 or 1 in the PR 4  mode and −2 or 2 in the EPR 4  mode. That is, the overflow detector  405  serves both as an overflow and underflow detector to determine whether the input signal exceeds the predetermined over and underflow limits. The meaning of the overflow or underflow condition is that the particular data point that is being processed lies above or below the band  1  or band − 1  range in the PR 4  mode (−2 or 2 for the EPR 4  case). In that event, the overflow detector  405  sends a signal on line  407  to the multiplexer  408  to thereby select an overflow or underflow value, as shown. The particular overflow and underflow values selected, therefore, serve as maximum and minimum values that the data may assume as it is being processed. Otherwise, the data on line  402   e  is simply passed through the multiplexer  408  for further processing. 
     Simultaneously with the data processing in section  453 , at least a portion of the data is further processed in the second path denoted by the dotted line box  450 . More particularly, the input signal on line  402  is processed to determine whether it belongs to band  0 , or, is centered about  0 . Thus, if both of the input signals belong to band  0 , the multiplexer  415  is controlled to provide a 0 value output on output line  419 . 
     Thus, since the band  0  data is determined concurrently with processing of the input signal portions that belong to any of the bands, which is now simpler than the processisng of the prior art, the overall processing time for processing the input signal on line  402  is significantly reduced. Since the value determination is reduced from, for example, three band values to two band values, the overall processing time is reduced. 
     As noted above, the circuit  400  of FIG. 4 has upper and lower substantially identical mirror halves. The circuit indicated is designed to effect the following equation: 
     
       
           TG   k   =B   k   E   k−1   −B   k−1   E   k   =T   k−1   +T   k   (1) 
       
     
     in which: 
     k is a current time interval, 
     k−1 is an immediately preceding time interval, 
     TG k  is a time gradient signal for a current time interval, 
     B k  is a current band signal value in which B k ε {−1,0,1} 
     E k−1  is a preceding error signal of an immediately preceding time interval, 
     B k−1  is a band signal value of an immediately preceding time interval in which B k−1  ε {−1,0,1 }, 
     E k , is an error signal of a current time interval, and T k  and T k−1  are band modulated errors. 
     It can be seen that equation (1) involves the sum or the modulated errors of a current bit value as well as immediately preceding bit value. These two terms are denoted odd and even values, so that for each time in a series of successive time sequences, the current value and next immediately preceding value can be determined. The sign of the products in equation (1) is controlled by the clocked exclusive-nor gate  403  and exclusive-or gate  423  so that the sum of the successive terms that is generated by the summer  417  produces an output that provides the value of the above set forth equation. 
     It can be appreciated that one circuit shown in FIG. 4 provides for the determination of three bands of signal values. This may be useful, for example, in the acquisition mode of an EPR 4  signal, or in the tracking mode of a PR 4  signal. Through the use of the band  0  detector circuits to control the multiplexer  415 , the speed of the circuit  400  can be increased still further. More particularly, since the value of the signal at the output of the band  0  detectors is either 0 or 1, a rapid selection can be made between the inputs provided on lines  416 ,  426 ,  418  and  418 , together with a value of 0, according to the following table: 
     
       
         
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Output = 
                 If z k  = 
                 And z k−1  = 
               
               
                   
                   
               
             
             
               
                   
                 T k−1  + T k   
                 0 
                 0 
               
               
                   
                 T k−1   
                 0 
                 1 
               
               
                   
                 T k   
                 1 
                 0 
               
               
                   
                 0 
                 1 
                 1 
               
               
                   
                   
               
             
          
         
       
     
     Thus, the input signals on lines  402  and  401  represent the present and immediately preceding data values that have been detected from the transducer of the mass data storage device with which the circuit  400  is associated. Once the circuit has determined an output value TG and the next sampled data value acquired, which becomes the current value, and the roles of the input lines  401  and  402  are reversed with regard to the presentation of the current and immediately preceding value. 
     Algorithmically, the calculation according to equation (1) above can be accomplished according to the following alogorithm: 
     1a ) calculate B k ˜ and B k−1 ˜ 
     2a ) calculate Z k , Z k−1    
     1b ) compute T k−1 ˜=B k ˜E k−1 , T k ˜=B k−1 ˜E k    
     1c ) add TG k ˜=T k−1 ˜+T k ˜ 
     3) finally, select the TG k  output according to the table set forth above, in which: 
     k is a current time interval, 
     k−1 is an immediately preceding time interval, 
     TG k ˜ is a time gradient signal for a current time interval, 
     B k ˜ is a current “hasty” band signal value in which B k ˜ ε {−1,0,1} 
     E k−1 ˜, preceding error signal of an immediately preceding time interval, 
     B k−1 ˜ is a “hasty” band signal value of an immediately preceding time interval in which B k−1 ˜ ε {−1,0,1}, 
     E k ˜, is an error signal of a current time interval, 
     T k ˜ and T k−1 ˜ are band modulated errors, and z k  is 1 if the sample belongs to band  0 . 
     Note in certain applications, the previous sample variables may be calculated during previous clock cycles. 
     Compare the separate similar B determination circuits  503  and  504 FIG. 5 of a gain gradient circuit  500  operating in the data-tracking mode. The difference between a gain gradient circuit in data-tracking mode and a timing recovery circuit such as  400  of FIG. 4 lies in the simpler overflow circuitry and band modulation circuitry  510  as compared to overflow circuitry shown in the dotted section  453  of the timing gradient circuit  400  of FIG.  4 . 
     Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.