Abstract:
A LCD is disclosed, including a gate line formed on an insulating substrate with a segment having one side protruding to form a protrusion region and an indentation region facing the protrusion region, an active layer formed on the segment of the gate line, a pixel electrode formed on the protruding side of the segment, a source line extending substantially perpendicular to the gate line to cross the overlapped region of the active layer and the gate line and prolonging beyond the edges of the active layer, and a drain line coupled to the pixel electrode and extending substantially parallel to the source line to cross the overlapped region of the active layer and the gate line The LCD is capable of preventing deviation in gate-drain parasitic capacitance to reduce difference in luminance between divisional exposure regions. The invention further discloses a method for manufacturing the same.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to a liquid crystal display (LCD) and more particularly to a structure for a LCD capable of suppressing variation in gate-drain parasitic capacitance.  
         [0003]     2. Description of the Related Art  
         [0004]     Flat panel displays, especially LCDs, have advanced in recent years and gradually take the place of traditional cathode ray tube (CRT) displays. Active matrix LCDs utilizing thin film transistors (TFTs) occupy a major portion of LCDs due to display performance better than passive matrix LCD, and have become the focus of current research.  
         [0005]      FIG. 1  is a plane view of a pixel unit  10  in a conventional TFT-LCD. The pixel unit comprises a gate line  11  disposed horizontally on an insulating substrate, wherein the gate line  11  has a protruding region serving as a gate electrode  12 . An active layer, formed of amorphous silicon or the like, is formed on the gate electrode  12 . A source line  14  extends perpendicularly across the gate line  11  and has a protruding region acting as a source electrode  15 . A drain line  16  connected to a pixel electrode  18  extends in parallel with the gate line  11  to cross the gate electrode  12  and has a drain electrode  17 . The pixel electrode  18  is generally formed of a transparent conductive material having good conductivity, such as indium-tin-oxide or indium-zinc oxide.  
         [0006]     During photolithography, machine variance causes the overlapped region of source electrode  15 /drain electrode  17  and the gate electrode  12  to exceed allowances.  FIG. 2  is a plane view of the pixel unit  10  in which the source electrode  15 /drain electrode  17  deviating to the right due to the exposure process. Compared to  FIG. 1 , the overlapped region of the source electrode  15  and the gate electrode  12  is larger while the overlapped region of the drain electrode  17  and the gate electrode  12  is smaller in  FIG. 2 . Accordingly, in  FIG. 2  the gate-source parasitic capacitance (hereafter referred to as C GS ) is increased while gate-drain parasitic capacitance (hereafter referred to as C GD ) is decreased. Conversely, when the deviations of the exposure process cause the source electrode  15  and the drain electrode  17  deviate to the left (not shown by a figure), C GS  is decreased while C GD  is increased.  
         [0007]      FIG. 3  shows an equivalent circuit of a pixel unit in a TFT-LCD to illustrate the effect of C GD  on LCD illumination. G represents a gate electrode, S represents a source electrode, D represents a drain electrode, C LC  represents a liquid crystal capacitance, and C S  represents a storage capacitance, wherein the two capacitances C LC  and C S  are connected in parallel between a pixel electrode P and a common electrode C. When the TFT-LCD is turned on, the gate electrode G is applied with a relatively high voltage V GH , and the relation between the total charge Q 1  in the TFT-LCD and voltage V P1  of the pixel P is expressed as: 
   Q   1   =C   GD ( V   P1   −V   GH )+( C   LC   +C   S )( V   P1   −V   COM )  (1),  
 wherein V COM  denotes the voltage of the common electrode. 
 
         [0008]     Conversely, when the TFT-LCD is turned off, the gate electrode G is applied with a relatively low voltage V GL , and the relation between the total charge Q 2  in the TFT-LCD and the voltage V P2  at the pixel P is expressed as: 
 
 Q   2   =C   GD ( V   P2   −V   GL )+( C   LC   +C   S )( V   P2   −V   COM )  (2). 
 
         [0009]     Due to charge conservation, that is,  Q   1   =Q   2 , it is derived from formulae (1) and (3) as:  
                     Δ   ⁢           ⁢     V   P       ≡       ⁢       V     P   ⁢           ⁢   1       -     V     P   ⁢           ⁢   2                     =       ⁢       (       V   GH     -     V   GL       )     ⁢       (       C   GD     /     (       C   CL     +     C   CS     +     C   GD       )       )     .                     (   3   )             
 
         [0010]     As shown in formula (3), ΔV p , so-called kickback voltage, is dependent on C GD . Since LCD illustration is controlled by adjusting the voltage of the pixel P, there arises a problem with non-uniformity of LCD illumination deviation of C GD  caused by machine variance. In more serious cases, so-called “mura” phenomenon occurs. However, resolution of exposure machines is restricted within some range. Consequently, non-uniformity of LCD illustration occurs.  
         [0011]     In consideration of the above-mentioned problem, a structure for a TFT-LCD capable of suppressing a variation in gate-drain parasitic capacitance, preventing illumination non-uniformity and enhancing display quality is called for.  
       BRIEF SUMMARY OF THE INVENTION  
       [0012]     The invention discloses a TFT-LCD capable of preventing deviation in gate-drain parasitic capacitance, thereby reducing difference in luminance between divisional exposure regions of a LCD. The invention further discloses a method for manufacturing the same.  
         [0013]     The invention provides a LCD comprising a gate line, an active layer, a pixel electrode, a source line, and a drain line. The gate line is formed on an insulating substrate, and has a segment with one side protruding to form a protrusion region and an indentation region facing the protrusion region. The active layer is formed on the segment of the gate line. The pixel electrode is formed on the protruding side of the segment. The source line extends substantially perpendicular to the extension direction of the gate line, across the overlapped region of the active layer and the gate line, and beyond the edges of the active layer. The drain line, coupled to the pixel electrode, extends substantially parallel to the extension direction of the source line to cross the overlapped region of the active layer and the gate line.  
         [0014]     The invention provides another LCD comprising a gate line, first and second active layers, first and second pixel electrodes, a source line, and first and second drain lines. The gate line is formed on an insulating substrate, and has a segment with both sides protruding to form first and second protrusion regions and an open region formed between the first and second protrusion regions to separate the segment into first and second portions. The first and second active layers are respectively formed on the first and second portions of the gate line. The first and second pixel electrodes are respectively formed on one side of the segment. The source line extends substantially perpendicular to the extension direction of the gate line to cross the respective overlapped regions of the first and second active layers and the gate line. The first and second drain lines, respectively coupled to the first and second pixel electrodes, extend substantially parallel to the extension direction of the source line. The first drain line crosses the overlapped region of the firstactive layer and the first portion. Similarly, the second drain line crosses the overlapped region of the second active layer and the second portion.  
         [0015]     The invention provides a method for manufacturing a LCD comprising forming a gate line on an insulating substrate, wherein the gate line has a segment with one side protruding to form a protrusion region and an indentation region facing the protrusion region, forming an active layer on the segment of the gate line, forming a source line, and a drain line such that the source line extends substantially perpendicular to the extension direction of the gate line, across the overlapped region of the active layer and the gate line, and beyond the edges of the active layer, and the drain line extends from a predetermined pixel-electrode region to form a pixel electrode substantially parallel to the extension direction of the source line to cross the overlapped region of the active layer and the gate line, and forming the pixel electrode in the predetermined pixel-electrode region.  
         [0016]     The invention provides another method for manufacturing a LCD comprising forming a gate line on an insulating substrate, wherein the gate line has a segment with both sides protruding to form first and second protrusion regions and an open region formed between the first and second protrusion regions to separate the segment into first and second portions, respectively forming first and second active layers on the first and second portions of the gate line, forming a source line on the first and second active layers and the insulating layers and first and second drain lines on the insulating substrate and respectively on the first and second active layers such that the source line extends substantially perpendicular to the extension direction of the gate line to cross the respective overlapped region of the first and second active layers and the gate line, and the first and second drain lines extend respectively from first and second predetermined pixel-electrode regions respectively to form first and second pixel electrodes, substantially parallel to the extension direction of the source line to respectively cross the respective overlapped regions of the first and second active layers and first and second portions, and respectively forming the first and second pixel electrode in the first and second predetermined pixel-electrode regions. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0018]      FIG. 1  is a plane view of a pixel unit in a conventional TFT-LCD;  
         [0019]      FIG. 2  is a plane view of the pixel unit in which the source electrode/drain electrode deviates to the right due to deviations in the exposure process;  
         [0020]      FIG. 3  shows an equivalent circuit of a pixel unit in a TFT-LCD to illustrate the effect of C GD  on illumination;  
         [0021]      FIGS. 4A and 4B  are plane views of a pixel unit in a LCD in accordance with embodiments of the invention;  
         [0022]      FIGS. 5A-5E  are cross-sections at different steps in a fabrication process of a pixel unit in  FIG. 4A   
         [0023]      FIGS. 6A-6E  are plane views at different steps in a fabrication process of a pixel unit of the invention corresponding to  FIGS. 5A-5E .  
         [0024]      FIG. 7  is a plane view of a pixel unit in a LCD in accordance with an embodiment of the invention; and  
         [0025]      FIGS. 8A-8E  are plane views at different steps in a fabrication process of a pixel unit in  FIG. 7 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     Referring to  FIG. 4A , a plane view of a pixel unit  40  in a LCD in accordance with an embodiment of the invention. As shown in the figure, in the pixel unit  40 , a gate line  41  is formed on an insulating substrate (not shown), wherein a segment of the gate line  41  has one side curving outwards to form a protrusion region  41   a  and another side curving inwards to form an indentation region  41   b  facing the protrusion region  41   b . The segment serves as a gate electrode  42 . An active layer  43  is formed on the gate electrode  42 . A source line  44  extends substantially perpendicular to the gate line  41 , across the overlapped region of the active layer  43  and the gate line  41  to form a source electrode  45  on the active layer  43 , and prolongs beyond the boundary of the active layer  43 . A drain line  46 , coupled to a pixel electrode  48 , extends substantially parallel to the source line  44  from the protrusion region  41   a  to the indentation region  41   b , across the overlapped region of the active layer  43  and the gate line  41  to forming a drain electrode  47  on the active layer  43 . A channel region is defined between the source electrode  45  and drain electrode  47  within the active layer  43 . It is noted that in the figure the source line  44  bends slightly to the drain line  46 . However, the source line  44  can be a straight line or extend substantially perpendicular to the gate line  41 .  
         [0027]     It can be seen that when size of the component varies with process resolution, the parasitic capacitor C GD  does not change accordingly. As shown in the figure, directions parallel and perpendicular to the gate line  41  are respectively denoted as X and Y. If exposure machine has an error of ±D X  along the direction X, distance between the boundaries of the source line  44  and the overlapped region of the active layer  43  and gate line  41  along the direction X is L X1 , and distance between the boundaries of the drain line  46  and the overlapped region of the active layer  43  and gate line  41  along the direction X is L X2 , then both distances L X1  and L X2  are required to be longer than distance D X . Similarly, if exposure machine has an error of ±D Y  along the direction Y, and distance between the boundaries of the drain line  46  and the overlapped region of the active layer  43  and gate line  41  along the direction Y is L Y , then distance L Y  is required to be longer than distance D Y . If the above requirements are satisfied in a design, the overlapped region of the source electrode/drain electrode  45 / 47  and the gate line  42  and hence the parasitic capacitor C GD  can be fixed no matter the direction of the error of the exposure machine.  
         [0028]     Further, to meet low resistance requirements of the gate line  41 , the width of the gate line  41  can be increased, as shown in a pixel unit  40 ′ of  FIG. 4B , an open region  41   b  thus facing the protrusion region  41   a.    
         [0029]      FIGS. 5A-5E  and  6 A- 6 E shows fabrication process of a pixel unit of the invention using the LCD shown in  FIG. 4A  as an example.  FIGS. 6A-6E  are plane views of the fabrication process and  FIGS. 5A-5E  are respective cross-sections along a line AA′ in  FIGS. 6A-6E .  
         [0030]     First, referring to  FIG. 5A , a conductive film  41  is formed on an insulating substrate (such as a glass substrate)  50 . The conductive film  41  is low resistant metal such as Al or Cr or alloy thereof, having a single or multiple layer structure formed by a conventional deposition such as sputtering. Next, the conductive film  41  is patterned by photolithograph etching, such that a gate line  41  having a gate electrode  42  is formed on the insulating substrate  50 . As shown in  FIG. 6A , the gate line  41  has a segment with one side curving outwards to form a protrusion region  41   a  and an indentation region  41   a  facing the protrusion region  41   b . The segment serves as the gate electrode  42 .  
         [0031]     Next, referring to  FIGS. 5B and 5C , a gate insulation film (such as a nitride layer)  52  and a semi-conductor layer  43  of an amorphous silicon material (such as a N-doped amorphous silicon) are sequentially formed on the entire upper surface of the resulting structure by a traditional deposition procedure such as plasma enhanced chemical vapor deposition (PECVD) process. Next, the semiconductor layer  43  is patterned to form an active layer  43  on the gate electrode  42  and the gate insulation film  52 .  
         [0032]     Next, referring to  FIGS. 5C and 6C , a conductive film is formed on the entire upper surface of the resulting structure. The conductive film  41  is low resistance metal such as Al or Cr or alloy thereof, having a single or multiple layer structure formed by a conventional deposition such as sputtering. Next, the conductive film is patterned by photolithograph etching, such that a source line  44  and a drain line  46  are formed, wherein the source line  44  and the drain line  46  respectively have a source electrode  45  and a drain electrode  47  on the active layer  43 . In  FIG. 5C , the pattering is realized such that source line  44  extends substantially perpendicular to the gate line  41  and crosses the overlapped region of the active layer  43  and the gate line  41 , and such that the drain line  46  extends substantially parallel to the gate line  41  from a predetermined pixel-electrode region where a pixel electrode is predetermined to be formed, crossing the overlapped region of the active layer  43  and the gate line  41 .  
         [0033]     Next, referring to  FIGS. 5D and 6D , a passivation film  55 , such as a nitride material, is formed on the entire upper surface of the resulting structure by conventional deposition such as PECVD. A contact hole  61  (not shown in  FIG. 5D  but shown in  FIG. 6D ) is sequentially formed within the passivation film  55  by photolithography etching such that a partial region of the drain line  46  is exposed.  
         [0034]     Next, referring to  FIGS. 5E and 6E , a transparent conductive layer having good transmissivity such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) is formed on the upper surface of the resulting structure. The transparent conductive layer is sequentially patterned by etching so as to be connected to the exposed surface of the drain line and form a pixel electrode  48  on a partial region of the drain line  46  and the contact hole, and extends in the passivation film  55  adjacent to the active layer  43  and the TFT. The pixel electrode  48  is connected to the drain line  46  via the contact hole  56  in the passivation film  55 .  
         [0035]     It is noted that the structure can extend to form a double-TFT LCD for the purpose of increasing conduction current.  FIG. 7  is a plane view of such a pixel unit in a LCD comprising two shunted TFT transistors in accordance with an embodiment of the invention.  
         [0036]     As shown in  FIG. 7 , in a pixel unit  70 , a gate line  71  is disposed horizontally on an insulation substrate. A segment of the gate line  71  has two sides curving outwards to respectively form a first and second protrusion region  71   a   1 , and  71   a   2 , and has an open region  71   b  between the first and second protrusion regions  71   a   1  and  71   a   2  to separate the segment into first and second portions respectively serving as first and second gate electrode  72   1 , and  72   2 . A first and second active layer  73   1  and  73   2  are respectively formed on the first and second electrodes  72   1 , and  72   2 . A source line  74  extends substantially perpendicular to the gate line  71 , crossing the overlapped region of the first active layer  73   1  and the first portion of the gate line  71  and the overlapped region of the second active layer  73   2  and the second portion of the gate line  71 , and forming first and second source electrodes  75   1  and  75   2  respectively thereon. A first source line  76   1 , extends substantially parallel to the source line  74  from a first pixel electrode  78   1  to cross the overlapped region of the first active layer  73   1  and the first portion of the gate line  71 , forming a first drain electrode  77   1 , thereon. Similarly, a second source line  762  extends substantially parallel to the source line  74  from a second pixel electrode  781  to cross the overlapped region of the second active layer  73   1  and the second portion of the gate line  71 , forming a second drain electrode  77   2  thereon. Channels are defined respectively between the first source electrode  75   1  and the first drain electrode  77   1  in the first active layer  73   1  and between the second source electrode  75   2  and the second drain electrode  77   2  in the second active layer  73   2 .  
         [0037]     The structure is a double-TFT transistor comprising two shunted first and second TFT transistors. The first TFT transistor comprises first gate electrode  72   1 , first active layer  73   1 , first source electrode  75   1  and first drain electrode  77   1 . The second TFT transistor comprises second gate electrode  72   2 , second active layer  73   2 , second source electrode  75   2  and second drain electrode  77   2 . It is noted that the drain line  44  bends slightly to the drain line  46  in the figure. However, the source line  74  can be a straight line or extend substantially perpendicular to the gate line  71 .  
         [0038]     It is seen that when size of the components are determined according to process resolution, the parasitic capacitor C GD  will not change with process variance. As shown, distances between the boundaries of the source line  74  and the overlapped regions of the two active layer  73   1 / 73   2  and gate line  71  along the direction X are L X11  and L X21 , respectively, and distances between the boundaries of the drain lines  76   1 , and  76   2  and the overlapped regions of the active layer  73   1  and  73   2  and gate line  71  are L X2l  and L X22  respectively along directions X, and are L Y1  and L Y2  respectively along direction Y. If exposure machine has errors of ±D X  and ±D Y  respectively along the directions X and Y, then when the distances LX 11 , LX 12 , LX 21  and LX 22  are designed longer than the distance D X , and L Y1  and L Y2  longer than the distance L Y , the overlapped region of the first source electrode/drain electrode  73   1 / 76   1 , and the gate line  71 , the overlapped region of the second source electrode/drain electrode  73   2 / 76   2  and the gate line  71 , and hence the parasitic capacitor C GD  of the first and second TFT transistors are nearly fixed.  
         [0039]     An LCD having double TFT transistors has fabrication process similar to that of the LCD having a single TFT transistor shown in  FIG. 4A .  FIGS. 8A-8E  are plane views of a pixel unit of the LCD shown in  FIG. 7  at different steps in a fabrication process. The cross-section is not described for brevity.  
         [0040]     First, a conductive film is formed on an insulating substrate (such as a glass substrate). The conductive film is low resistant metal such as Al or Cr or alloy thereof, having a single or multiple layer structure formed by conventional deposition such as sputtering. Next, the conductive film is patterned by photolithograph etching, such that a gate line  71  is formed on the insulating substrate. As shown in  FIG. 8A , the gate line  71  has a segment with both boundaries curving outwards to form first and second protrusion regions  71   a   1 , and  71   a   2  and having an open space separating the segment into a first and second gate electrode  72   1 , and  72   2 .  
         [0041]     Next, a gate insulation film (such as a nitride layer) is formed, and a semi-conductor layer of an amorphous silicon material (such as a N-doped amorphous silicon) is sequentially formed on the entire upper surface of the resulting structure by conventional deposition such as plasma enhanced chemical vapor deposition (PECVD) method. Next, the semiconductor layer is patterned to form first and second active layers  73   1  and  73   2  respectively on the first and second gate electrodes  72   1 , and the neighboring gate insulation film, as shown in  FIG. 8B .  
         [0042]     Next, a conductive film is formed on the entire upper surface of the resulting structure. The conductive film is low resistant metal such as Al or Cr or alloy thereof, having a single or multiple layer structure formed by conventional deposition as sputtering. Next, the conductive film is patterned by photolithograph etching, such that a source line  74  and a first and second drain line  76   1 , and  76   2  are formed. Referring to  FIG. 8C , the pattering is performed such that source line  74  extends substantially perpendicular to the gate line  71  to cross the overlapped regions of the active layers  73   1  and  73   2  and the gate line  71 , and such that the first and second drain line  76   1  and  76   2  extend substantially parallel to the gate line  74 , each from a predetermined pixel-electrode region at one side of the gate line  71  where a pixel electrode is predetermined to be formed, crossing the overlapped region of the first and second active layers  73   1  and  73   2  and the gate line  71  respectively.  
         [0043]     Next, a passivation film  55 , such as a nitride material, is formed on the entire upper surface of the resulting structure by conventional deposition such as PECVD. First and second contact holes  86   1  and  86   2  are sequentially formed within the passivation film  55  by photolithography etching, such that respective partial regions of the first and second drain lines  76   1 and  76   2  are exposed.  
         [0044]     Next, a transparent conductive layer having good transmissivity such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) is formed on the upper surface of the resulting structure. The transparent conductive layer is sequentially patterned by an etching method so as to be connected to the exposed surfaces of the first and second drain lines  76   1  and  76   2  and forms a first and second pixel electrode  78   1  and  78   2 . Referring to the  FIG. 8E , the pattering process is performed such that the first pixel electrode  86   1  is formed on a partial region of the first drain line  76   1 , the first contact hole  86   1  and the passivation film adjacent to the first TFT. Similarly, the second pixel electrode  86   2  is formed on a partial region of the second drain line  76   2 , the second contact hole  86   2 , and the passivation film adjacent to the second TFT. Accordingly, the first pixel electrode  78   1  is connected to the first drain line  76   1  via the first contact hole  86   1 , and similarly, the second pixel electrode  78   2  is connected to the second drain line  76   2  via the second contact hole  86   2 .  
         [0045]     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.