Abstract:
A new technology for simultaneously performing the previously separate functions of analog phase-tracking and A/D conversion, represented by a family of systems referred to as delta-sigma frequency-to-digital converters (ΔΣFDCs). Each system uses coarse analog phase measurements, quantization noise shaping, and decimation filtering to perform instantaneous frequency-to-digital conversion. Because they operate on instantaneous frequency in the manner that ΔΣ modulators operate on amplitude, they share many of the benefits enjoyed by ΔΣ modulator-based A/D converters such as reduced analog circuit requirements and amenability to VLSI implementation.

Description:
FIELD OF THE INVENTION 
     The invention relates to analog-to-digital (A/D) converters and phase-tracking devices, specifically a device that performs both functions simultaneously. 
     BACKGROUND OF THE INVENTION 
     Phase-locked loops are used in a multitude of communications and instrumentation applications performing phase-tracking operations such as phase-coherent demodulation, carrier tracking, timing recovery, bit synchronization, and Doppler measurement. Because of the trend toward digital signal processing, it is increasingly necessary to perform analog-to-digital conversion in addition to phase-tracking. Usually, this is done by combining traditional A/D converters with either analog or digital phase-locked loops. The drawback is that relatively precise analog circuitry is required for even moderate levels of digital conversion accuracy. The current invention employs a novel technique for simultaneously performing phase-tracking and A/D conversion with the goals of reducing analog circuit complexity and sensitivity to non-ideal component behavior. Theoretical and computer simulation results indicate that systems based on the technique can be developed that have comparable performance to the traditional approach with significantly less complex and precise analog circuitry. 
     The technique gives rise to a family of systems that will be referred to as delta-sigma frequency-to-digital converters (ΔΣFDCs). Like a phase-locked loop, each ΔΣFDC tracks the phase and frequency of its input signal. However, unlike a phase-locked loop, it performs coarse analog phase measurements using a one-bit A/D converter (i.e., a hard limiter) sampled at many times the Nyquist rate of the signal bandwidth, and employs quantization noise shaping and decimation filtering to obtain an accurate digital estimate of the instantaneous frequency of its input. Accordingly, ΔΣFDCs operate on instantaneous frequency in a similar manner to the way delta-sigma (ΔΣ) modulator-based A/D converters operate on amplitude. Hence, they share many of the benefits enjoyed by ΔΣ modulator-based A/D converters such as reduced analog circuit requirements and amenability to very large scale integration (VLSI) implementation. 
     SUMMARY OF INVENTION 
     The invention is a new technology for simultaneously performing the previously separate functions of analog phase-tracking and A/D conversion. The advantage over the traditional approach of performing the functions separately is significantly reduced analog circuit complexity and cost. The invention is represented by a family of systems referred to as delta-sigma frequency-to-digital converters (ΔΣFDCs). Each system uses coarse analog phase measurements, quantization noise shaping, and decimation filtering to perform instantaneous frequency-to-digital conversion. Because they operate on instantaneous frequency in a similar manner to the way that ΔΣ modulators operate on amplitude, they share many of the benefits enjoyed by ΔΣ modulator-based A/D converters such as reduced analog circuit requirements and amenability to VLSI implementation. 
     Phase-tracking problems are ubiquitous in communications and instrumentation applications, and the trend toward digital signal processing fueled by advances in modern VLSI processes is rapidly necessitating the juxtaposition of phase-tracking and A/D conversion functions in many applications. Just as ΔΣ modulation made possible the development of extremely accurate monolithic A/D converters without trimmed components, it is likely that the current technique will give rise to high precision monolithic frequency-to-digital converters that are similarly robust. The ΔΣFDC could become an important building block for modern, integrated receivers in communications and instrumentation. 
    
    
     The invention is pointed out with particularity in the appended claims. The above and further objects, features and advantages of the invention may be better understood by referring to the following detailed description, which should be read in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings, 
     FIG. 1A is an example first-order ΔΣFDC modulator loop. 
     FIG. 1B is an example single-loop second-order ΔΣFDC modulator loop. 
     FIG. 1C is an example multistage second-order ΔΣFDC modulator loop. 
     FIGS. 2A, 2B and 2C represents the analysis of the operation of the first-order modulator loop on the frequency modulation of x r  (t). 
     FIG. 3 is the simplest type of single-loop second-order ΔΣFDC modulator loop. 
     FIG. 4 shows the processing performed by the single-loop modulator loops of FIG. 1B and FIG. 3 on φ(n). 
     FIG. 5 shows the processing performed by the multistage second-order modulator loop of FIG. 1C on φ(n). 
     FIGS. 6A, 6B and 6C illustrate modified versions of the modulator loops shown in FIGS. 1A, 1B and 1C that employ sampling phase detectors and all-digital number controlled oscillators (NCOs). 
     FIG. 7 shows a Mathworks Simulink implementation modular of the loop in FIG. 6B. 
     FIGS. 8, 9 and 10 show the results of the simulation in FIG. 7 for the no channel noise, 9 dB signal to channel noise ratio, and 3 dB signal to channel noise ratio cases. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     A variety of structures based on the idea can be found each representing performance tradeoffs. Certain of the structures are described in this section to illustrate different aspects of the underlying principle. A heuristic explanation of their operation is provided along with theoretical results and computer simulations. 
     In the following, it will be assumed that each ΔΣFDC operates on a signal of the form: ##EQU1## where A is a constant amplitude, f c  is a constant carrier frequency, φ(t) is a frequency modulation signal with bandwidth B&lt;&lt;f c , and n(t) is an undesired noise term that will be referred to as channel noise. The purpose of each of the ΔΣFDCs presented below is to produce an accurate digitized estimate of φ(t). 
     The high level anatomy of a ΔΣFDC is similar to that of a ΔΣ modulator-based A/D converter in that it comprises a modulator loop and a lowpass decimation filter. The modulator loop operates on the input signal, x r  (t), and produces a coarsely quantized sequence at a sample rate many times the Nyquist rate of φ(t). As discussed below, the output can be considered the sum of three components: a component corresponding to φ(t), a component corresponding to n(t), and a component corresponding to quantization error. The component corresponding to φ(t) is restricted to a low frequency portion of the spectrum because of the high sampling rate. As will be shown, the modulator loop shapes the spectra of the other components so that most of the their power resides at high frequencies. The decimation filter functions as a lowpass digital filter of bandwidth B followed by a decimator. The purpose of the lowpass filtering is to preserve the component corresponding to φ(t) while removing the out-of-band portions of the other components. Decimation reduces the output sample rate to the Nyquist rate of φ(t). The result is a multi-bit digitized representation of φ(t). 
     It is the modulator loop that is the core of the ΔΣFDC. The remainder of this section will describe the basic ΔΣFDC modulator loop principle along with various preliminary results and simulations. First, three ΔΣFDC modulator loops that illustrate different aspects of the basic idea will be presented and analyzed in the absence of channel noise. Then, their behavior in the presence of channel noise will be discussed. Finally, the amenability of the structures to VLSI implementation will be considered. 
     Three Example Modulator Loops 
     The three example ΔΣFDC modulator loops to be discussed below are shown in FIGS. 1A, 1B and 1C. The structures each operate on x r  (t) and produce a coarsely quantized sequence at sample rate f s . By virtue of the sample-and-holds each modulator loop is composed of both continuous-time and discrete-time portions. In practice, signals following the sample-and-holds are still continuous-time signals except that they are only updated at the sample times. However, the following abuse of notation will be made. If it is convenient to refer to a sampled-and-held variable, say y(t), as the corresponding discrete-time sequence, it will be denoted as y(n) and should be interpreted as the value of y(t) just after the n th  sample time. 
     In each of the modulator loops, the quantization is performed by one or more hard limiters. These are one-bit midrise quantizers that produce a positive one when their inputs are non-negative and a negative one otherwise. Multi-bit quantizers could also be used to perform the quantization. Each structure employs at least one phase detector and voltage controlled oscillator (VCO). For now it will suffice to assume that each phase detector produces a voltage equal to a positive constant, K p , times the difference in phase of its two analog inputs (ignoring any amplitude modulation). Similarly, for now each VCO will be assumed to produce a continuous-phase sinusoid with instantaneous frequency equal to f c  plus a positive constant, K v , times its input voltage. Once the basic idea has been presented, the issues surrounding the use of practical phase detectors and VCOs will be discussed. 
     First-Order Modulator Loop Behavior 
     The simplest of the three modulator loops is the first-order structure shown in FIG. 1A. It consists of a phase detector 1, a sample-and-hold 2, a hard limiter 3, and a VCO 4. To understand how it operates, it is illustrative to first consider the following simple case. Suppose that φ(t)=φ 0  is a constant where |φ 0  |&lt;K v , and that n(t) is zero. Thus, x r  (t) is a pure sinusoid of frequency f c  +φ 0 . At each sample time, the output of the sample-and-hold is updated with the difference between the phase of x r  (t) and the phase of the VCO output. If at some sample time this value is positive, the output of the hard limiter will be a positive one and the instantaneous frequency of the VCO will be updated (if necessary) to f c  -K v . Since f c  -K v  &lt;f c  +φ 0 , at some time in the future the output of the phase detector must go negative. Provided the sample rate, f s , is greater than 2 K v , the output of the sample-and-hold will also eventually go negative and the instantaneous frequency of the VCO will be updated to f c  +K v . Similarly, if at some sample time the output of the sample-and-hold is negative, the output of the hard limiter will be a negative one and the instantaneous frequency of the VCO will be updated (if necessary) to f c  +K v . Again provided f s  is greater than 2 K v , the output of the sample-and-hold will eventually go positive because f c  +K v  &gt;f c  +φ 0 . This argument is still valid if applied to sufficiently narrow-band angle modulated signals centered near f c . 
     By this reasoning, it is evident that the first-order modulator loop &#34;loosely&#34; tracks the phase and frequency of the input signal. To prove that the first-order ΔΣFDC produces a high-precision digital conversion of φ(t) in the absence of channel noise, it remains to show that the spectrum of the output component corresponding to quantization error occupies predominantly high frequencies while the component corresponding φ(t) is not spectrally distorted. As discussed above, this allows the lowpass decimation filter to remove much of the quantization error without significantly distorting the component of the output corresponding to φ(t). 
     The manner in which the first-order modulator loop processes φ(t) is shown in FIG. 2A. The integrator 5 following the input converts the frequency modulation term, φ(t), into an absolute phase. Similarly, the integrator 6 in the feedback loop converts the VCO frequency modulation into an absolute phase. The phase detector corresponds to the differencer 7 shown in the figure. The K v  and K p  scalar multipliers 8 arise from the VCO and phase detector gains, respectively. 
     Because integration is linear, the two integrators 5 and 6 in FIG. 2A can be moved to the right of the phase detector and combined 9 without changing the system as shown in FIG. 2B. Just after the n th  sample time, the output of the sample-and-hold must be ##EQU2## where T s  =1/f s  is the sampling interval. Since y(t) is a sampled-and-held signal, this equation can be rewritten as the difference equation: ##EQU3## It follows that the system of FIG. 2B can be redrawn in a discrete-time form as shown in FIG. 2C. The two systems are equivalent in the sense that they produce the same output sequences. Moreover, because f s  is much greater than the Nyquist ratio of φ(t), it follows that φ(n)≈φ(nT s ) with a high degree of accuracy. 
     Note that aside from the K v  T s  and K p  gain elements 10 and 11, the system shown in FIG. 2C is simply a first-order ΔΣ modulator [1]. The K p  gain element 11 has no effect on the behavior of the system because of the hard limiter, and it is easily verified that the K v  T s  gain element 10 does not effect the quantization noise shaping behavior of the system. Accordingly, the first-order ΔΣFDC modulator loop operates on the frequency modulation of its input signal in the same manner that a first-order ΔΣ modulator operates on the amplitude of its input signal. With the definition that quantization noise, ε(n), is the difference between the output and input of the hard limiter at time n, a network analysis shows that the output of the modulator loop is ##EQU4## where e(n)=ε(n)-ε(n-1). The sequence e(n) is the error at the output of the modulator loop due to the one-bit quantization performed by the hard limiter and is referred to as quantization error. The modulator loop thus subjects the quantization noise to the first-order highpass filter 1-z -1 . As a result, the quantization error has zero DC power and tends to be weighted toward high frequencies. 
     It follows that the first-order ΔΣFDC performs oversampling A/D conversion on the frequency modulation term φ(t). The oversampling ratio is f s  /f N , where f N  is the Nyquist rate of φ(t). Existing ΔΣ modulator results indicate that the precision of the A/D conversion should increase by approximately 1.5 bits [4] for every doubling of the oversampling ratio. This result is supported by computer simulations. 
     Higher-Order Modulator Loops 
     Having established the analogy between the first-order ΔΣFDC modulator loop and the first-order ΔΣ modulator, the next logical step is to search for ΔΣFDC modulator loops analogous to higher order ΔΣ modulators. By subjecting the quantization noise to sharper highpass filtering such structures hold the promise of greater conversion accuracy at a given oversampling ratio. As mentioned above, higher order ΔΣFDC modulator loops can be found. For example, the modulator loops shown in FIG. 1B and FIG. 1C are analogous to second-order ΔΣ modulators in that they each subject their quantization noise to the second-order highpass filter (1-z -1 ) 2 . However, before discussing these structures further, it is worth digressing to explain why the simplest method of generating a second-order ΔΣFDC modulator loop from the first-order loop does not lead to the most practical solution. 
     The simplest extension of the first-order ΔΣFDC modulator loop leading to a second-order structure is shown in FIG. 3. Just as in the case of the first-order modulator loop, the output of the sample-and-hold just after the n th  sample time is ##EQU5## It follows that the modulator loop operates on φ(n) as the single-loop second-order ΔΣ modulator shown in FIG. 4. However, this conclusion relies on the gain element 12 in the second feedback path of the modulator loop being exactly equal to K p  K v  T s . Unfortunately, the gain K p , of most practical phase detectors is input-amplitude dependent [3]. The explicit K p  -dependent gain element therefore causes a significant practical problem; some sort of automatic gain control (AGC) of x r  (t) would generally be required to maintain a constant phase detector gain. 
     This problem is avoided in the modulator loops of FIG. 1B and FIG. 1C. First consider the modulator loop shown in FIG. 1B. Following an analysis similar to that performed above for the first-order ΔΣFDC modulator loop, the output of this modulator loop&#39;s sample-and-hold just after the n th  sample time is ##EQU6## Drawing the system corresponding to this difference equation and rearranging things shows that like the modulator loop of FIG. 3 this modulator loop operates on φ(n) as the single-loop second-order ΔΣ modulator of FIG. 4. However, unlike the modulator loop of FIG. 3, it does not contain an explicit K p  -dependent gain element. The idea involves the equivalent of both frequency and phase modulating the VCO output. In the modulator loop of FIG. 1B, the transfer function 14 between the hard limiter 15 and the VCO 16 is 2-z -1 . Thus, the VCO is controlled by the sum of the hard limiter output, y(n), and its digital derivative, y(n)-y(n-1). The effect of the digital derivative is the modulate the phase of the VCO (as measured at each sample time) by ±K p  K v  T s . Thus the phase detector and VCO gains control the gain of both feedback paths in FIG. 4; any variation in phase detector gain affects both feedback paths equivalently, so the second-order quantization noise shaping property of the structure is preserved. 
     The modulator loop of FIG. 1C also performs second-order quantization noise shaping. To see this, proceed as above to find the output of the modulator loop&#39;s two sample-and-holds just after the n th  sample time. These are ##EQU7## The difference equations describe the system shown in FIG. 5 which is known to be a second-order multistage ΔΣ modulator [5]. 
     The modulator loop uses the same frequency and phase modulation principle as the modulator loop of FIG. 1B so its quantization noise shaping property is not affected by variations in the phase detector gain. The lower modulator loop stage 17 shown in FIG. 1C controls the frequency modulation of both VCOs while the upper modulator loop only controls the phase modulation of its own VCO. Hence, the frequency tracking dynamics are controlled solely by the lower modulator loop. The main significance of the multistage modulator approach is that is offers a systematic method of generating yet higher-order modulator loops. For example, three first-order modulator loops can be combined to achieve a three-stage third-order modulator. Similarly, a second-order modulator loop can be combined with a first-order modulator loop to achieve a two-state third-order modulator loop. 
     As in the case of the first-order modulator loop, existing ΔΣ modulator theory can be brought to bear on the second-order modulator loops shown in FIG. 1B and FIG. 1C and on those created by cascading combinations of the first and second-order modulator loops. For example, for the second-order modulator loops existing ΔΣ modulator results indicate that the precision of the digital conversion should increase by approximately 2.5 bits [4] for every doubling of the oversampling ratio. Again, this result is supported by computer simulations. 
     The Effect of Channel Noise 
     Now consider the effect of random channel noise. There are two basic types of performance degradation that can arise from channel noise. The first arises because the channel noise generates a frequency modulation term of its own in x r  (t) that the ΔΣFDC demodulates along with φ(t). This phenomenon is well known [6] and will not be discussed further since it affects all FM demodulators. The second arises from channel noise that passes to the output of the phase detector. 
     In the first-order modulator loop, such noise is injected just prior to the sample-and-hold 2, and is therefore sampled and subjected to the same first-order highpass filter, (1-z -1 ), seen by the quantization noise. Similar observations apply to the modulator loops of FIG. 1B and FIG. 1C. Therefore, like quantization error, this type of channel noise error will tend to be weighted toward high frequencies. However, the picture is more complicated. If the noise power is sufficiently high, the magnitude of the quantizer input can exceed the maximum magnitude of the quantizer output by more than half the quantization step size. This phenomenon is known as quantizer overload and results in performance degradation similar to that observed in ΔΣ modulators [4]. Moreover, high noise power levels can cause cycle slipping wherein the difference between the phase of x r  (t) and the VCO slips by one or more cycles in either direction. Both quantizer overload and cycle slipping can severely degrade performance if their frequency of occurrence is high. Nevertheless, simulations, some of which are discussed below, indicate that the ΔΣFDC is quite robust with respect to channel noise. 
     Practical Phase Detectors and VCOs 
     The discussion thus far has only considered modulator loops with ideal phase detectors and VCOs. A variety of practical phase detectors and VCOs capable of operating over an extremely wide range of frequencies exit and their characteristics are well understood [7]. Clearly the specifics of the phase detector must be considered in any meaningful channel noise analysis. ΔΣ modulators have been observed to be robust with respect to non-ideal circuit behavior [1], and because of their relationship to ΔΣ modulators it follows that ΔΣFDCs are similarly robust. For example, in the first-order ΔΣFDC modulator loop, it is not necessary for the phase detector to be linear or to have a constant gain because it is followed by the hard limiter. 
     An advantage of the invention relates to its amenability to VLSI implementation. Aside from the phase detector and VCO, the components that make up the ΔΣFDC modulator loops are the same as those used in ΔΣ modulators. As such, many of the VLSI design issues are similar and have been studied extensively. One approach is therefore to integrate all of the ΔΣFDC on a single mixed-mode CMOS VLSI integrated circuit except for the phase detector and VCO which would be implemented separately using higher-precision and possibly higher-frequency bipolar or GaAs processes. Since a multitude of phase detector and VCO circuits are widely available, well understood, and relatively inexpensive, this is a reasonable approach. 
     On the other hand, integrating the entire ΔΣFDC on a single low-cost mixed-mode VLSI integrated circuit offers the potential of increased reliability and decreased cost. However, because of the analog limitations imposed by fine-line VLSI processes, the appropriate selection of the phase detector and VCO are critical. One possibility is to use sampling phase detectors [3]. FIG. 6 shows modified versions of the three modulator loops of FIG. 1 using such phase detectors that are well suited to VLSI implementation. The phase detectors are implemented as one-bit A/D converters (voltage comparators) 18 and instead of VCOs the systems use all-digital number controlled oscillators (NCOs) 19. 
     Consider the first-order modulator loop of FIG. 6a. The system is simply a one-bit A/D converter 18 and an NCO 19 enclosed in a feedback loop. The A/D converter performs mid-rise quantization on the analog input signal; if the input signal is positive at a given sampling instant, the A/D converter outputs the equivalent of a one. Otherwise it outputs the equivalent of a negative one. The NCO generates the sampling clock for the A/D converter. It functions as a variable-length counter that generates pulses spaced at either N or N+1 periods of a master clock where N is some fixed positive integer. If the output of the A/D converter is one, the NCO waits N periods of the master clock before producing the next pulse. Otherwise, it waits N+1 periods. With the master clock frequency denoted as f m , its period denoted as T m  =1/f m , and the sequence of sample times denoted as {τ n  }, each sample time is chosen as ##EQU8## 
     Each of the modulator loops loosely tracks the zero crossings of x r  (t). The scheme requires that f m  and N be chosen such that f m  /(N+1)&lt;f c  &lt;f m  /N. When the phase of the NCO output leads that of the input signal, the A/D converter outputs a minus one. Similarly, when the phase of the NCO output lags that of the input signal, the A/D converter outputs a one. Therefore, the A/D converter acts as a phase detector followed by a hard limiter. By defining ##EQU9## and performing analyses similar to those performed above for the modulator loops of FIG. 1, it is easy to show that the modulator loops of FIG. 6 operate on φ(n) as first-order, single-loop second-order, and multistage second-order ΔΣ modulators, respectively. 
     There are two primary drawbacks to the modulator loops of FIG. 6. The first is that the master clock must run approximately N (typically 10≦N≦100) times faster than the carrier frequency of x r  (t), and the second is that some distortion is caused by the non-uniform sampling and integration interval of φ(t). For very narrow-band φ(t), a potential solution is to have the output of the NCO be one of two (or possibly more) phase-locked clock signals separated in frequency by 2 K v  Hz. The NCO would again drive a sampler, but the samples would be integrated for a period of 1/(2 K v ) and then re-sampled at the modulator loop sample rate f s  =2 K v . Such a system would be useful in radio frequency (RF) tone tracking and would be amenable to GaAs VLSI implementation. 
     Simulation Results 
     Simulation results indicate that these modulator loops perform well in the presence of channel noise. For example, FIG. 7 shows a Mathworks Simulink implementation of a ΔΣFDC based on the second-order modulator loop of FIG. 6b. Three simulations were performed with 
     
         φ(t)=(0.00024πf.sub.c) cos (0.006πf.sub.c t)-(0.0012πf.sub.c) sin (0.002πf.sub.c t), 
    
     an average sample rate of f c , N=25, and a digital filter cutoff frequency of 0.0023π. FIG. 8 shows the results for the case of no channel noise, and FIGS. 9 and 10 show the results for white Gaussian channel noise with input signal-to-noise ratios (SNRs) of 9 dB and 3 dB, respectively. In each case the input channel noise is shown on a vertical scale of ±2, the ΔΣFDC output is shown on a vertical scale of ±0.25, and the error (the difference between the ΔΣFDC output and φ(n)) is shown on a vertical scale of ±0.005. Aside from a scale factor the same channel noise sequences were used in the latter two simulations. 
     As is evident from the figures, this particular ΔΣFDC appears to perform well even for small input SNRs. In the absence of channel noise, the error plot is a result of quantization error alone, and the error power level is consistent with that expected for the corresponding second-order ΔΣ modulator [4]. As mentioned above, separate simulations have been performed by the Inventor that quantitatively support this conclusion. In the cases of 9 dB and 3 dB input SNR, the error plot contains components corresponding to quantization error and channel noise. In these cases, the error level is still seen to be small relative to output signal. The similarity between the error plots in the two cases is interesting and may indicate that much of the error arises from the frequency modulation imposed on x r  (t) by the channel noise as discussed above. Numerous similar simulation runs for each of the modulator loops of FIG. 6 with various input signals, channel noise levels, and loop parameters have been performed and also support the results outlined above. 
     Although particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and variations may readily occur to those skilled in the art. The preceeding descriptions of the invention are thus illustrative only. The invention is limited only as required by the following claims and equivalents thereto.