Abstract:
A dynamically expandable pipeline in a microprocessor. The present invention is used in a microprocessor or a microprocessor in a computer system. The present invention delays execution of a cacheable LOAD instruction by a bus controller for one cycle to allow sufficient time for &#34;hit or miss&#34; detection by a data cache unit. The present invention dynamically expands the instruction pipeline for cacheable LOAD instructions that &#34;miss&#34; an on-chip data cache when the LOAD is followed by another instruction that uses the bus controller. The dynamic pipeline allows time for the &#34;hit or miss&#34; detection by the data cache unit without unnecessarily degrading pipeline performance. The present invention offers increased overall microprocessor and computer system performance by allowing efficient implementation of an on-chip data cache. The present invention provides increased performance without undue or overly complex modifications to existing pipeline or data cache circuits.

Description:
This is a continuation of application Ser. No. 08/040,675 filed Mar. 31, 1993, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to the field of microprocessors and more specifically to pipelined microprocessors. 
     2. Prior Art 
     The design of an original microprocessor architecture requires a very large investment of time, money, and engineering effort. In order to maximize the profit realized over the lifetime of an architecture, proliferations of the original design are typically created to appeal to particular markets. A proliferation retains the &#34;core&#34; design of the original architecture, but enhances or adds to that design. For example, an original microprocessor design with a performance of 30 MIPs may be the perfect solution for the largest segment of the microprocessor market. However, other markets, such as laser printers, may demand a higher performance microprocessor. In this case, the original architecture could be enhanced to meet the performance requirements of the laser printer market by adding an on-chip data cache unit, speeding up the floating point unit, etc. The resulting proliferation may have a performance of 50 MIPs with slightly higher costs than the original. Proliferating an existing architecture is more attractive than creating a new design because the required investment is much smaller. 
     When an original architecture is defined, design choices and tradeoffs are necessarily made. In the design of a proliferation of the original architecture, problems imposed by the constraints of these original design choices are often encountered. Overcoming these constraints is often a challenging part of the design of a proliferation. 
     FIG. 1 illustrates a block diagram of a prior art microprocessor. Microprocessor 10 includes a processor core 12, a random access memory (RAM) 16, and a bus controller logic (BCL) 18, all coupled to a memory-side machine bus (MMB) 14. The processor core 12 generates an instruction pointer address, fetches the instruction at the instruction pointer address, decodes the instruction, and issues the decoded instruction to the functional units for execution. Bus controller logic 18 and an external memory 22 are coupled to a system bus 20. System bus 20 is used to transfer data between microprocessor 10 and external devices such as external memory 22. Bus controller logic 18 controls data transfers on system bus 20. When executing instructions, microprocessor 10 may operate on data retrieved either from random access memory 16 or external memory 22. 
     The memory-side machine bus 14 carries the control information and handles the local data transfers that occur during the fetching, issuing, and executing of memory instructions by the microprocessor pipeline. The fetching, issuing, and executing of instructions is pipelined in a &#34;fixed&#34; sequence of three stages or &#34;pipes&#34; as defined in Table I. Each stage is divided into two phases: phase 1 and phase 2. 
     
                       TABLE I______________________________________Pipeline for Fetching, Issuing, and Executing Instructions______________________________________Pipe 0:  Phase 1.  Generate Instruction Pointer (IP).Pipe 0:  Phase 2.  Fetch instruction at IP address.Pipe 1:  Phase 1.  Decode instruction.Pipe 1:  Phase 2.  Issue instruction.Pipe 2:  Phase 1.  Execute instruction.Pipe 2:  Phase 2.  Return.______________________________________ 
    
     During pipe 0, phase 1, the address of the next instruction is generated by processor core 12. This address is the instruction pointer (IP). During pipe 0, phase 2, the processor core 12 fetches the next instruction from the address indicated by the instruction pointer. The instruction is typically fetched from either external memory or an instruction cache. During pipe 1, phase 1, the instruction is decoded by the processor core 12. The processor core 12 determines, among other things, whether execution of the instruction uses machine-side memory bus 14. If the instruction uses the memory-side machine bus, then it is issued on memory-side machine bus 14 during pipe 1, phase 2. During issuance, the memory-side machine bus carries control information that indicates which of the possible units (RAM, BCL, or other) should execute the issued instruction. During pipe 2, phase 1, the appropriate coprocessor unit executes the issued instruction. For example, bus controller logic 18 executes a LOAD instruction by retrieving the required data from external memory 22. During pipe 2, phase 2, the return phase of the pipeline, data is returned to memory side machine bus 14 and transferred to the appropriate destination unit. Not all instructions return data during their pipe stage 2. Therefore, the return phase of the pipeline must be arbitrated to allow, for example, the bus controller to return data from external memory that was requested several instructions previously in the pipeline. 
     FIG. 1 shows an example of the operation of the pipeline of microprocessor 10 in waveforms PH1 24, MMBQ11 26, and BCLEXEQ21 28. (Note: Q11 means pipe 1, Phase 1; Q21 means pipe 2 phase 1.) PH1 24 indicates the phase of the pipeline. The pipeline is in phase 1 when PH1 24 is high and phase 2 when PH1 24 is low. MMBQ11 26 is the instruction decoding of pipe 1, phase 1. BCLEXEQ21 is the execution of pipe 2, phase 1. The waveforms of FIG. 1 illustrate a STORE, LOAD, FETCH sequence of instructions being decoded during pipe 1, phase 1 and executed during pipe 2, phase 1. A STORE instruction stores data to a memory. A LOAD instruction retrieves data from a memory. A FETCH is the loading of an instruction from external memory. 
     Microprocessor 10 has two possible &#34;targets&#34; that can execute or service an issued LOAD instruction: external memory 22 or internal RAM 16. Bus controller logic 18 is responsible for the detection and handling of this distinction. This detection is done in the same cycle in which the LOAD itself is issued, allowing bus controller logic 18 to begin executing a LOAD from external memory 22 in pipe 2, phase 1. In the case of a LOAD from RAM 16, the RAM will service the LOAD in pipe 2, phase 1. 
     During execution of a typical program, many of the data accesses by microprocessor 10 are data LOAD accesses from external memory 22. Microprocessor 10 may be forced to sit idle for some time waiting for a LOAD instruction to return data since accesses to external memory 22 are relatively slow. Therefore, one way to achieve a higher performance proliferation of the microprocessor 10 would be to include an on-chip data cache unit to circumvent the long access times needed to LOAD data from external memory 22. However, the fixed definition of the pipeline does not allow enough time for &#34;hit or miss&#34; detection by a data cache unit during a cacheable LOAD from external memory. 
     Addition of a data cache unit provides a third &#34;target,&#34; the data cache unit, that can execute a LOAD instruction. During a LOAD, a tag match operation is performed by the data cache unit to determine whether the required data resides in the data cache unit. This detection begins in pipe 1, phase 2 at the same time the LOAD is issued. Unfortunately, the tag match operation, or &#34;hit or miss&#34; detection, of a data cache unit requires too much time to be completed before execution of the LOAD instruction begins in pipe 2, phase 1. Therefore, it is not possible to tell bus controller logic 18 whether or not to execute the LOAD in the execution cycle. An additional &#34;dead&#34; cycle is required to give the &#34;hit or miss&#34; detection enough time to properly determine whether the bus controller logic will need to service the LOAD. Creating a permanent &#34;dead&#34; cycle in the pipeline is one way to solve the problem. But a permanent &#34;dead&#34; cycle in the pipeline would seriously degrade the performance of the microprocessor. 
     Therefore, a method and apparatus for dynamically expanding the pipeline of a microprocessor is needed. 
     SUMMARY OF THE INVENTION 
     The present invention is drawn to an apparatus, system, and method for using a microprocessor having a dynamically expandable pipeline. The microprocessor of the present invention comprises a core means, a bus controller means, a pipeline means, and a staller means. The core means and bus controller means are coupled to a local bus. The bus controller means is coupled to a system bus for transferring data external to the microprocessor. 
     The core means fetches, decodes, and issues instructions on the local bus and processes data. The bus controller means loads instructions and data from an external store to said microprocessor via a system bus for processing by the core means. The pipeline means causes a first pipe to execute at least a first operation during a cycle and a second pipe to execute at least a second operation during the cycle. The pipeline means repeatedly executes the normal cycle. During a cycle, the first pipe produces a first result that is operated on by the second pipe in the next cycle. The second pipe selectively causes the bus controller means to perform the second operation of the second pipe. 
     The present invention further includes a staller means for selectively delaying the execution of the second operation of the cycle until the next normal cycle to allow a third pipeline operation to be completed before the beginning of the execution of the second operation. 
     One object of the present invention is to improve the overall performance of a microprocessor by providing a dynamically expandable pipeline. The dynamically expandable pipeline improves performance of the microprocessor by providing sufficient time in the pipeline to perform the &#34;hit or miss&#34; detection of an on-chip data cache means without unnecessarily degrading the pipeline performance. 
     Another object of the present invention is to improve the performance of a computer system by providing a computer system that uses a microprocessor with a dynamically expandable pipeline. 
     Yet another object of the present invention is to increase the performance of microprocessor and computer systems without undue or overly complex modifications to existing pipeline or data cache circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a prior art microprocessor having a fixed pipeline. Waveforms of a STORE, LOAD, FETCH sequence of the pipeline are shown. 
     FIG. 2A is a block diagram of the preferred embodiment of the microprocessor of the present invention. 
     FIG. 2B is an illustration of the dynamically expandable pipeline of the preferred embodiment of the present invention. The waveforms illustrate the case of a cacheable LOAD &#34;miss&#34; that is followed immediately by an instruction that requires execution by the bus controller logic. 
     FIG. 2C illustrates the preferred embodiment of the present invention for the case of a cacheable LOAD &#34;miss&#34; that is followed immediately by an instruction that does not require execution by the bus controller logic. 
     FIG. 2D illustrates the preferred embodiment of the present invention for the case of a cacheable LOAD &#34;hit.&#34; 
     FIG. 2E illustrates the preferred embodiment of the present invention for the case of a non-cacheable LOAD. 
     FIG. 3 is a flowchart of the method of the preferred embodiment of the present invention, 
     FIG. 4 is a block diagram of one overall system embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A method and apparatus for dynamically expanding the pipeline of a microprocessor is described. In the following description, numerous specific details are set forth, such as pipeline cycles, in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the an that the present invention may be practiced without these specific details. In other instances, well-known methods and circuits are not described in detail in order not to obscure the present invention. It is understood that the present invention is comprised of transistor circuits that are readily manufacturable using well known CMOS (complementary metal-oxide semiconductor) technology. 
     The present invention addresses the problem of pipeline timing constraints encountered when attempting to utilize an on-chip data cache unit in a &#34;fixed&#34; pipeline microprocessor. More specifically, the present invention addresses the problem of not having enough time in a &#34;fixed&#34; pipeline to allow for data cache unit &#34;hit or miss&#34; detection to properly qualify an issued LOAD instruction such that the bus controller logic knows whether or not to execute the LOAD instruction in the following execution stage of the pipeline. The present invention can readily be used to improve the performance of new microprocessor architectures. 
     Overall Design of the preferred Embodiment of the Present Invention 
     FIG. 2A is a block diagram of the preferred embodiment of the present invention. Microprocessor 30 includes a processor core 32, a random access memory (RAM) 36, a bus controller logic (BCL) 38, a data cache unit (DCU) 44, an instruction latch 46, a MUX 48, a memory-side machine bus (MMB) 34, and a system bus 40. Processor core 32, random access memory 36, and data cache unit 44 are coupled to memory-side machine bus 34. Memory-side machine bus 34 allows a common data transfer and control path between units that are connected to it. MEMSCBOKU12 54, a scoreboarding control signal carried by memory-side machine bus 34, can be asserted by any unit coupled to the memory-side machine bus. Asserting MEMSCBOKU12 54 causes each unit coupled to the memory-side machine bus to maintain the current pipeline state for an additional cycle to effect a one cycle delay in the pipeline. Processor core 32 generates an instruction pointer address and fetches the instruction at the instruction pointer address. It then decodes the instruction to determine which functional unit of microprocessor 30 should execute the instruction. Data cache unit 44 stores copies of data that bus controller logic 38 retrieves from external memory 42 for subsequent use by processor core 32. Data cache unit 44 receives a CACHEABLEQ12 52 signal from bus controller logic 38. CACHEABLEQ12 52 indicates whether a given access issued by processor core 32 is to a cacheable region of memory. CACHEABLEQ12 52 causes data cache unit 44 to handle only cacheable data. Random access memory 36 is a memory for storing data. Instruction latch 46 is coupled to memory-side machine bus 34 for storing an issued instruction to allow it to be effectively re-circulated one cycle later under certain conditions. MUX 48 is coupled to receive the instruction latched in instruction latch 46 and also to receive an issued instruction from memory-side machine bus 34. The select input of MUX 48 is coupled to a DCULDMISSQ21 signal 50 from data cache unit 44. When DCULDMISSQ21 50 is high, indicating a &#34;miss,&#34; the re-circulated instruction in instruction latch 46 is driven at the mux output. When DCULDMISSQ21 50 is low, indicating that the previous instruction was not a cacheable LOAD which &#34;missed&#34; the data cache, the currently issued instruction on memory-side machine bus 34 is driven at the mux output. The output of MUX 48 is coupled to bus controller logic 38 allowing bus controller logic 38 to receive either the currently issued instruction from memory-side machine bus 34 or the re-circulated instruction stored in instruction latch 46. Bus controller logic 38 and an external memory 42 are coupled to a system bus 40. System bus 40 is used to transfer data between microprocessor 30 and external devices such as external memory 42. 
     FIG. 2B illustrates the waveforms of the dynamically expandable pipeline of microprocessor 30 for the case of a cacheable LOAD that &#34;misses&#34; data cache unit 44 followed by an instruction that requires execution by bus controller logic 38, i.e. a STORE, LOAD, or FETCH instruction. 
     In cycle [1], a cacheable LOAD instruction is issued on the memory-side machine bus 34 as shown by MMBQ11 58. In this same cycle, bus controller logic 38 drives CACHEABLEQ12 52 high indicating that the LOAD data is in a cacheable region of memory. Because the LOAD is cacheable, bus controller logic 38 also drives an internal signal, CACHECANQ12 60 high causing bus controller logic 38 to prevent both the execution of the instruction and the updating of the pipeline queue slots, thereby stalling the bus controller logic 38 for one cycle. The issued LOAD instruction is latched into instruction latch 46 for re-circulation in the next cycle, as shown on MMBQ21 62. Data cache unit 44 begins &#34;hit or miss&#34; detection in this cycle. 
     In cycle [2], the data cache unit finishes the &#34;hit or miss&#34; detection and drives DCULDMISSQ21 50 high to indicate a &#34;miss.&#34; DCULDMISSQ21 50 drives the select input of MUX 48. DCULDMISSQ21 50 being high selects the instruction latched in instruction latch 46 as the instruction issued to bus controller logic 38. In this same cycle, data cache unit 44 &#34;scoreboards&#34; the memory-side machine bus 34 by driving MEMSCBOKU12 54 low if and only if the currently issued instruction on the bus will use the bus controller logic 38, i.e. a LOAD, STORE, or FETCH instruction. &#34;Scoreboarding&#34; causes each unit to maintain the current pipeline state for one additional cycle to effectively delay the pipeline for one cycle. In this example, a FETCH is the currently issued cycle [2 ] instruction on memory-side machine bus 34 and MEMSCBOKU12 54 going low causes the memory-side machine bus 34 to be scoreboarded, thereby delaying issuance of the FETCH until cycle [3]. Bus controller logic 38 must ignore the scoreboarded FETCH instruction since it has to first execute the re-circulated cacheable LOAD &#34;miss&#34; from instruction latch 46. 
     In cycle [3], the pipeline is restored to normal execution. The scoreboarded FETCH instruction is reissued on MMBQ11 58 and the re-circulated LOAD instruction is executed by bus controller logic 38 as shown on BCLEXEQ21 64. 
     The waveforms of FIG. 2B show that a cacheable LOAD instruction that &#34;misses&#34; the data cache unit causes a one cycle delay in the bus controller logic to allow sufficient time for &#34;hit or miss&#34; detection. When the following instruction also requires use of the bus controller logic, a resource collision is created. To resolve this conflict, the following instruction is scoreboarded to allow execution one cycle later, the LOAD instruction is executed during the current cycle, and the scoreboarded instruction is executed one cycle later than normal. Therefore, in the case of a cacheable LOAD that &#34;misses&#34; the data cache unit and is followed by an instruction that requires use of the bus controller logic, there is a one cycle penalty in pipeline performance. 
     However, in the case of a cacheable LOAD that &#34;misses&#34; the data cache unit and is followed by an instruction that does not use the bus controller logic, the delay in the bus controller does not result in a delay in the pipeline as now discussed with reference to FIG. 2C. 
     FIG. 2C illustrates the waveforms of the dynamically expandable pipeline of microprocessor 30 for the case of a cacheable LOAD that &#34;misses&#34; data cache unit 44 but is followed by an instruction that does not use bus controller logic 38. 
     Cycle [1] for this case is identical to the cacheable LOAD &#34;miss&#34; case of FIG. 2B. A cacheable LOAD instruction is issued on MMBQ11 58. In this same cycle, bus controller logic 38 drives CACHEABLEQ12 52 high indicating that the LOAD data is in a cacheable region of memory. Because the LOAD is cacheable, bus controller logic 38 also drives an internal signal, CACHECANQ12 60 high causing bus controller logic 38 to prevent both the execution of the instruction and the updating of the pipeline queue slots, thereby stalling the bus controller logic for one cycle. The issued LOAD instruction is latched into instruction latch 46 for re-circulation in the next cycle, as shown on MMBQ21 62. Data cache unit 44 begins &#34;hit or miss&#34; detection in this cycle. 
     Cycle [2] for this case is similar to the cacheable LOAD &#34;miss&#34; case of FIG. 2B, except that no scoreboarding of the memory-side machine bus is performed. The data cache unit finishes the &#34;hit or miss&#34; detection and drives DCULDMISSQ21 50 high to indicate a &#34;miss.&#34; DCULDMISSQ21 50 being high selects the instruction latched in instruction latch 46 as the instruction issued to bus controller logic 38. MEMSCBOKU12 stays high preventing memory-side machine bus 34 from being scoreboarded. In this case, scoreboarding is not necessary because the currently issued LOADA instruction on the memory-side machine bus 34 bus does not use the bus controller logic 38. Therefore, there is no conflict with the bus controller logic 38 needing to simultaneously execute both the re-circulated instruction and the currently issued LOADA instruction on the memory-side machine bus 34. 
     In cycle [3], the bus controller is restored to normal execution; and the pipeline continues with normal execution. The LOAD instruction is re-circulated from instruction latch 46 and executed by bus controller logic 38 as shown on BCLEXEQ21 64. The LOADA instruction issued on memory-side machine bus 34 in cycle [2] is executed by another memory unit. And the FETCH instruction is issued on memory-side machine bus 34 (shown on MMBQ11 58) for subsequent execution by bus controller logic 38 in cycle [4]. 
     Therefore, the waveforms of FIG. 2C show that a cacheable LOAD instruction that &#34;misses&#34; the data cache unit causes a one cycle delay in the bus controller logic. However, because the following instruction does not require use of the bus controller logic, the bus controller delay does not result in any delay in the pipeline. 
     FIG. 2D illustrates the waveforms of the dynamically expandable pipeline of microprocessor 30 for the case of a cacheable LOAD that &#34;hits&#34; data cache unit 44 followed by a FETCH instruction that requires execution by bus controller logic 38. 
     Again, cycle [1] is the same cycle [1] of FIG. 2B. A cacheable LOAD instruction is issued on MMBQ11 58. In this same cycle, bus controller logic 38 drives CACHEABLEQ12 52 high indicating that the LOAD data is in a cacheable region of memory. Because the LOAD is cacheable, bus controller logic 38 also drives an internal signal, CACHECANQ12 60 high causing bus controller logic 38 to prevent both the execution of the instruction and the updating of the pipeline queue slots, thereby stalling the bus controller logic 38 for one cycle. The issued LOAD instruction is latched into instruction latch 46 for re-circulation in the next cycle, but is not actually used in the next cycle. Data cache unit 44 begins &#34;hit or miss&#34; detection in this cycle. 
     In cycle [2], the data cache unit finishes the &#34;hit or miss&#34; detection and drives DCULDMISSQ21 50 low to indicate a &#34;hit.&#34; DCULDMISSQ21 50 being low causes MUX 48 to select the currently issued FETCH instruction on memory-side machine bus 34 as the instruction issued to bus controller logic 38. In this case, the bus controller logic 38 does not need to execute the LOAD instruction because the required data can be returned from the data cache unit 44. Therefore, the delay in the bus controller logic results in no delay in the pipeline. 
     In cycle [3], the bus controller logic 38 and the pipeline continue normal execution. The FETCH instruction issued in cycle [2] is executed as shown on BCLEXEQ21 64. 
     Therefore, the waveforms of FIG. 2D show that a cacheable LOAD instruction that &#34;hits&#34; the data cache unit causes a one cycle delay in the bus controller logic, but no delay in the pipeline. Because of the &#34;hit,&#34; the data cache unit executes the LOAD instruction leaving the bus controller logic free to execute the following FETCH instruction with no delay in the pipeline. 
     Finally, FIG. 2E illustrates the waveforms of the dynamically expandable pipeline of microprocessor 30 for the case of a non-cacheable LOAD. In the case of non-cacheable LOADs, the present invention maintains normal pipeline execution. 
     In cycle [1], a non-cacheable LOAD instruction is issued on MMBQ11 58 as shown by MMBQ11 58. In this same cycle, bus controller logic 38 drives CACHEABLEQ12 52 low indicating that the LOAD data is in a non-cacheable region of memory. Because the LOAD is non-cacheable, bus controller logic 38 drives internal signal CACHECANQ12 60 low causing bus controller logic 38 to execute the LOAD instruction and update the pipeline queue slots. The bus controller logic is not delayed one cycle for this case. The issued LOAD instruction is latched into instruction latch 46 for re-circulation, but the re-circulated instruction is not used in the next cycle. Data cache unit 44 does not perform &#34;hit or miss&#34; detection in this case. 
     In cycle [2], the data cache unit drives DCULDMISSQ21 50 low to indicate that the current memory request is not a cacheable LOAD, and therefore does not need to be re-circulated. DCULDMISSQ21 50 being low selects the issued LOAD instruction on memory-side machine bus 34 to be issued to bus controller logic 38. MEMSCBOKU12 54 stays high preventing memory-side machine bus 34 from being scoreboarded. The bus controller logic 38 executes the non-cacheable LOAD instruction as shown on BCLEXEQ21 64. Here there is no delay in the bus controller logic or the pipeline. 
     In cycle [3], the bus controller logic 38 and the pipeline continue normal execution. The FETCH instruction issued in cycle [2] on MMBQ11 58 is executed by the bus controller logic 38 on BCLEXEQ21 64. 
     Therefore, the waveforms of FIG. 2E show that a non-cacheable LOAD is executed normally with no delay in the bus controller logic or the pipeline. 
     Operation of the Preferred Embodiment of the Present Invention 
     The major functions of the preferred embodiment of the present invention operate according to the flow diagram illustrated in FIG. 3. In its overall operation, the present invention: 1) dynamically stalls the bus controller logic for any cacheable LOAD instruction, 2) dynamically expands the pipeline only when a cacheable LOAD &#34;misses&#34; the data cache unit and is immediately followed by another instruction that requires use of the bus controller logic, and 3) maintains the normal fixed sequence of the pipeline for all non-cacheable LOADs and other memory accesses. 
     Referring now to FIG. 3, the method of the present invention begins at step 66 when a LOAD instruction is issued on the memory-side machine bus 34. In step 68, the bus controller logic 38 determines whether the LOAD access is to a cacheable region of memory and drives signal CACHEABLEQ12 52 accordingly. If the LOAD is non-cacheable (CACHEABLEQ12 52 low), then in step 70 the bus controller logic: 38 and the pipeline operate in the normal fixed sequence of Table I. If the LOAD is cacheable (CACHEABLEQ12 52 high), then in step 72 three operations occur: 1) the bus controller is stalled for one cycle by preventing both the execution of the LOAD and the updating of the pipeline queue slots, 2) the currently issued cacheable LOAD instruction on the memory-side machine bus 34 is latched into instruction register 46 for subsequent re-circulation, if needed, and 3) the data cache unit 44 starts &#34;hit or miss&#34; detection (tag match operation). 
     In step 74, the data cache unit 44 determines whether the LOAD &#34;hits&#34; or &#34;misses&#34; the data cache unit 44 and drives DCULDMISSQ21 50 accordingly. If the LOAD &#34;hits&#34; (DCULDMISSQ21 50 low) the data cache unit 44, then in step 76 three operations occur: 1) the data cache unit 44 executes the LOAD by retrieving the matching data and returns the data to memory-side machine bus 34, 2) MUX 48 selects the memory-side machine bus 34 as the source of the next instruction issued to the bus controller logic 38 (the re-circulated/latched LOAD in instruction latch 46 is ignored by bus controller logic 38), and 3) normal operation of the bus controller logic 38 and the pipeline is resumed. If the LOAD &#34;misses&#34; (DCULDMISSQ21 50 high) the data cache unit 44, then in step 78 two operations occur: 1) MUX 48 selects the re-circulated LOAD instruction in instruction latch 46 to be issued to bus controller logic 38 and 2) the next instruction is issued on memory-side machine bus 34. 
     In step 80, bus controller logic 38 determines whether the currently issued instruction on the memory-side machine bus 34 uses the bus controller. If it does not, then in step 82 pipeline execution proceeds without any delay by: 1) the bus controller unit 38 executes the re-circulated/latched LOAD instruction and 2) the current instruction on the memory-side machine bus 34 is executed by some unit other than the bus controller logic 38. If the currently issued instruction on memory-side machine bus 34 uses the bus controller logic 38, then in step 84 the LOAD instruction and the following instruction are executed with a one cycle delay in the pipeline in the following three operations: 1) the memory-side machine bus is scoreboarded, 2) the bus controller logic 38 executes the re-circulated/latched LOAD instruction, and 3) the scoreboarded instruction is executed by the bus controller logic 38. 
     Steps 70, 76, and 82 all proceed to step 86 where the method finishes by resuming normal execution of the bus controller logic and the pipeline. 
     Overall System and Environment of the Present Invention 
     The overall environment, or system, in which the preferred embodiment operates is now described. In general, the preferred the preferred embodiment of the present invention is used in digital computer systems comprising, as illustrated in FIG. 4, a system bus 40 for communicating information between the elements of the system, a microprocessor 30 coupled to system bus 40 for processing information and instructions, external memory 42 coupled to system bus 40 where the external memory can be either random access memory for storing information and instructions for the microprocessor or read only memory for storing static information and instructions for microprocessor 30, a data storage device 88 such as a magnetic disk and disk drive coupled with system bus 40 for storing program information and instructions, a display device 90 coupled to the system bus 40 for displaying information to the computer user, and an alphanumeric input device 92 coupled to the system bus 40 for communicating information and command selections to microprocessor 30. It is understood that some environments of the present invention may contain all or merely a portion of the above components. 
     Thus, a method and apparatus for dynamically expanding the pipeline of a microprocessor has been described.