Abstract:
Disclosed is a method and apparatus for converting an unstable receiver enable signal RXEN, which is based on a master clock which undergoes timing adjustments, to a stable receiver enable signal RXEN′ which is based on an externally applied clock signal. An externally applied clock signal at a frequency fc is divided by a factor N to produce N uniformly phase spaced clock signals. A clocking edge of a master clock signal which generates the receiver enable signal RXEN is associated with one of the N clocking signals which has a pulse which substantially envelopes the edge of the master clock signal which generates the RXEN signal. A new receiver enable signal RXEN′ is generated by the associated new clock signal. The receiver enable signal RXEN is therefore converted from a signal which has adjusted timing to RXEN′ which has no timing adjustment.

Description:
FIELD OF THE INVENTION 
     The present invention relates to digital circuits, particularly to digital circuits employed in memory devices in which an unstable clock signal, used to time certain memory operations, is transferred into a stable clock domain. 
     BACKGROUND DISCUSSION 
     It is well known to use an internal master clock signal MCLK in memory devices to time many internal operations which must be performed by the memory device. One of these operations is the enabling of entry data and data clock paths into the memory device. FIG. 1 illustrates the input paths for the data DQ and data clock DCLK signals. As illustrated, the data signal paths DQø . . . DQ 17  of a memory device are connected to respective receiver circuits  13  which are enabled by an applied signal RXEN. When the data signals are gated through receiver  13  by the signal RXEN, they pass through an adjustable delay device  17 , and then into respective latches  19 . The data applied to latches  19  are clocked into the memory device by the externally applied data clock signal DCLK. The latter signal is gated by and passes through receiver  21  when it is enabled by the receiver enable signal RXEN. 
     The DCLK signal, after passing through receiver  21  and delay  23 , is applied to the latches  19  to latch the data on the data paths DQø . . . DQ 17 . The data paths also include an output circuit for the memory device which includes output latch  15  which receives a clock signal for clocking data out of the memory device and a buffer  11  which applies the output data onto the respective data paths DQø . . . DQ 17 . 
     The receiver enable signal RXEN must be received at the receivers  13  and  21  prior to the time that the respective data signals, for receiver  13 , and DCLK signal for receiver  21 , are received The RXEN signal in turn is generated internally from a master clock signal MCLK which controls all of the internal operations of a memory device. The RXEN signal is generated upon receipt at the memory device of a WRITE command and in response to the next received edge of the MCLK signal. In order to properly control many of the internal operations of the memory device, the timing of the master clock signal MCLK is typically adjusted in response to temperature and/or voltage variations within the memory device. This in turn affects the timing of the generation of the signal RXEN. 
     FIG. 4 illustrates the typical relationship between an arriving DCLK signal and the RXEN signal. As shown, the RXEN signal should occur during a preamble portion of the DCLK signal before the first clock transition “ 0 ” which is used to latch in data on the data paths DQø . . . DQ 17  and before a certain additional period of time shown by the crosshatching in FIG. 4, which accommodates signal skew within the memory device. Thus, the receiver enable signal RXEN must occur before a period of time denoted as t 1  in FIG.  4 . 
     In cases of large variations in the timing of MCLK, there will also be corresponding large variations in the timing of the receiver enable signal RXEN as shown by the double headed arrow in FIG.  4 . It is possible in such cases that the RXEN signal is not generated sufficiently in advance of the time t 1  which may cause clocking transitions  0 ,  1 ,  2 ,  3  of DCLK to be incorrectly applied to the latch  19  relative to the data incoming on the data paths DQø . . . DQ 17 . This may cause improper operation of the memory device. It would be preferable if the RXEN signal were not subject to the timing variations which occur with signal MCLK. 
     SUMMARY OF THE INVENTION 
     The present invention provides a memory device and its method of operation in which the RXEN signal does not vary in response to variations in the signal MCLK. Instead, a clock edge of the MCLK signal which is used to generate the RXEN signal is associated with a clock signal which is derived from an externally received clock signal related to DCLK. The association is such that an edge of the MCLK signal which is used to generate the RXEN signal is placed at approximately the center of a pulse of the clock signal derived from the externally applied clock signal. The clock signal derived from the externally applied signal is then used to generate a new RXEN′ signal. Since the signal derived from the externally applied signal is always stable and does not move with variations in voltage and/or temperature as does the signal MCLK or the prior signal RXEN, the timing of the newly generated receiver enable signal is also stable and does not move in response to variations in voltage and/or temperature. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above described advantages and features of the invention, as well as others, will be better understood from the following detailed description of the invention which provided in connection with the accompanying drawings in which: 
     FIG. 1 illustrates a typical input data path of a memory device for both data and a data clock signal DCLK; 
     FIG. 2 illustrates a memory device circuit for generating an MCLK signal; 
     FIG. 3 illustrates a conventional RXEN signal produced by a MCLK signal, as well as new receiver enable signal RXEN′ produced in accordance with the invention; 
     FIG. 4 illustrates the timing and relationship between a prior art receiver enable signal RXEN and a received data clock signal DCLK; 
     FIG. 5 is a timing diagram illustrating the operation of a portion of the invention; 
     FIG. 6 is a timing diagram illustrating the operation of another portion of the invention; 
     FIG. 7 is a circuit for generating timing signals used in the invention; 
     FIG. 8 is a circuit for generating a new receiver enable signal RXEN′ in accordance with the invention; 
     FIG. 9 is a circuit illustrating the generation of multiplex selection signals in accordance with the invention; 
     FIG. 10 is a timing diagram illustrating the operation of the FIG. 8 circuit; 
     FIG. 11 is a timing diagram illustrating the operation of the FIG. 7 circuit; and 
     FIG. 12 is a block diagram of an exemplary processor system in which the invention may be used. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides respective enable signals RXEN′ and RXEN″ for the receivers  13  and  21  illustrated in FIG.  1 . The RXEN′ and RXEN″ signals for receivers  13  and  21  are derived by using the unstable receiver enable signal RXEN to generate stable receiver enable RXEN′ and RXEN″ signals which are keyed to an externally applied clock signal, the latter of which remains stable, even with variations in temperature and/or voltage of the memory device. 
     In order to understand the invention, the manner in which the master clock signal MCLK is conventionally derived in a memory device is illustrated with respect to FIG.  2 . FIG. 2 shows a circuit for deriving various clock signals used in the operation of a memory device. External clock signals CCLK and CCLK* are received at terminals  31  and  33  and provided through a buffer  35  to an adjustable delay circuit  37 , the output of which feeds the delayed CCLIK and CCLIK* signals into a tapped delay to line  41 . 
     The tapped delay line  41  has a plurality of taps which provide delayed clock signals  0  . . .  15  to multiplexers  43  which are capable of providing selected ones of the clock signals  0  . . .  15  to selected ones of buffers  45 . The buffers  45  in turn supply respective delayed clock signals CCLK and CCLK* to respective output latches  51  of data paths Dø . . . D 17  of a memory device. The output latches  51  in turn supply read data from a memory array to respective output buffers  53  and output terminals  55  and  57 . 
     One of the delayed signals from tapped delay line  41 , for example, one provided at the last stage of the tapped delay line  41 , is provided to multiplexer  43  in a manner in which the signal passes through the multiplexer without being switchable to a selected buffer  45 . This signal which passes through multiplexor  43  and through buffer  45  is the master clock signal MCLK which is used to time various operations within a memory device. 
     Another clock output signal, for example, at the beginning of tapped delay line  41  (tap  0 ), is also provided as a clock signal which passes straight through multiplexer  43  and buffer  45  as an input to input/output model circuit  47 . The input/output model circuit  47  is a circuit which is designed to provide a specific delay to the signals CCLK and CCLK* through adjustable delay circuit  37  in accordance with designed operating parameters of the memory device and in response to changes in operating voltage and/or temperature of the device. To this end, the clock signal at tap  0  supplied to input/output model circuit  47 , and after being adjusted based on the parameters of voltage and temperature, is provided as an input into phase detector  49  which receives at another input the clock signal CCLK, also relabeled BCLK (buffered clock). The output of the phase detector  49  is used to adjust the delay circuit  37  to attain a desired timing relationship of the clock signal CCLK in accordance with voltage and temperature variations experienced by the memory device. 
     FIG. 2 also illustrates a phase detector  39  which is used to adjust the length of the tapped delay line  41  such that it remains at a constant length, such as one clock cycle. Phase detector  39  operates by comparing the output to the input of the tapped delay line  41  and making the necessary adjustments thereto to ensure that the delay length remains stable. 
     As is evident from FIG. 2, the adjustable delay circuit  37  causes timing adjustments in the input signal to the tapped delay line  41 , which in turn cause like timing adjustments in the MCLK signal. 
     FIG. 3 illustrates how a conventional circuit uses the MCLK signal to generate a receiver enable signal RXEN. In a conventional memory device, a RXEN generator  61  is provided which contains control logic circuit  63 . The control logic circuit  63  is responsive to a WRITE command to generate, on the next occurrence of the MCLK clock signal, the receiver enable signal RXEN. In a conventional memory device this RXEN signal is used in the manner illustrated in FIG. 1 to operate receivers  13  and  21  to respectively gate in data and the data clock signal DCLK. 
     However, as noted earlier, the RXEN signal is an unstable signal in that its timing varies in accordance with time adjustments made to the MCLK signal by virtue of the variable delay circuit  37 . 
     The present invention converts the unstable receive enable signal RXEN to a pair of stable enable signals denoted RXEN′ and RXEN″, which respectively operate the data receiver  13  and receiver  21  in FIG.  1 . The receiver enable signals RXEN′ and RXEN″ can be seen as output signals in the circuit of FIG.  8 . However, before describing exemplary circuitry for implementing the invention, the overall operation of the invention will be illustrated with respect to the timing diagrams shown in FIGS. 5 and 6. 
     FIG. 5 illustrates the timing relationship between an externally received clock signal CCLK, and an internally generated clock signal BCLK which is generated at the output of the buffer amplifier  35  shown in FIG.  2 . The signal BCLK is supplied to a frequency divider circuit  59  in FIG. 2 which generates four frequency divided clock signals CLK  4  &lt; 0 : 3 &gt;. These latter signals are also illustrated in FIG. 5 as CLK  4  &lt; 0 &gt; CLK  4  &lt; 1 &gt;, CLK  4  &lt; 2 &gt; and CLK  4  &lt; 3 &gt;. In addition, frequency divider  59  also provides the CLK  4  &lt; 0 : 3 &gt; clock signals with phase offset from one another of one-half of a BCLK signal clock cycle. FIG. 5 also illustrates the MCLK clock signal with rising and falling transitional edges  0 ,  1 ,  2 ,  3 ,  0 , etc. Since data acquisition in an exemplary memory device containing the invention occurs on four successive clock edges, the labeling of the transitional edges of the MCLK signal is from  0  through  3 . 
     In operation, the invention associates each of the rising and falling  0  . . .  3  edges of the MCLK signal with one of the frequency divided clock signals CLK  4 . The association is made by associating one edge of the MCLK clock signal with one of the clock signals CLK  4  &lt; 0 : 3 &gt; which more closely has the MCLK clock edge positioned at a substantial central point of the pulse width of the CLK  4  signal. 
     As shown in FIG. 5, each of the clock edges  0 ,  1 ,  2 ,  3  of the MCLK clock signal is associated with a corresponding one of the CLK  4  clock signals. Thus, the MCLK signal edge  0  is associated with the CILK  4  &lt; 0 &gt; signal; the MCLK signal edge  1  is associated with the CLK  4  &lt; 1 &gt; signal; the MCLK signal edge  2  is associated with the CLK  4  &lt; 2 &gt; signal; and the MCLK signal edge  3  is associated with the CLK  4  &lt; 3 &gt; signal. 
     It should be noted that although FIG. 5 illustrates MCLK clock signal edges  0 ,  1 ,  2 ,  3  respectively associated with the CLK  4  &lt; 0 &gt;, CLK  4  &lt; 1 &gt;, CLK  4  &lt; 2 &gt;, and CLK  4  &lt; 3 &gt; signals, the MCLK clock edges need not map to the CLK  4  clock signals in this precise order. Again, an edge of the MCLIK signal is associated with that one of the CLK  4  signals where the edge is closest to the center of the pulse forming the CLK  4  signal. Also, although the invention is illustrated with four transitions of the MCLK signal  0  . . .  3  and four associated clock signals CLK  4  &lt; 0 : 3 &gt;, the number of transitions  0  . . .  3  of MCLK and associated number of clock signals can vary in accordance with circuit design. 
     Once the MCLK clock signal edges are associated with respective ones of the CLK  4  signals, the invention then relies on the CCLK  4  clock signal associated with the edge of the MCLK signal, e.g., MCLK edge  0 , which was used to generate RXEN to generate the RXEN′ and RXEN″ receiver enable signals. As shown in FIG. 6, the RXEN′ and RXEN″ signals are generated off a next edge of the BCLK signal following the next transition of the CCLK  4  &lt; 0 &gt; signal which occurs after the MCLK, edge  0 , signal which generated the RXEN signal. 
     Since a BCLK signal generated from a CCLK  4  signal is used for generating the receiver enable signals RXEN′ and RXEN″, any variations in timing of the MCLK signal or associated RXEN signal, depicted in FIG. 6 by the double headed arrow, do not affect the time at which the RXEN′ and RXEN″ signals are generated. This is because the CCLK  4  and BCLK signals are locked to the externally applied clock signal CCLK. Accordingly, the receiver enable signals are now tied to a signal derived from the external clock signal. This ensures that the receiver signals RXEN′ and RXEN″ will always be generated in a stable manner at a timing which allows receivers  13  and  21  to properly and respectively admit the data and data clock signal DCLK into the memory device. 
     It should be noted that although the conventional circuit illustrated in FIG. 1 used RXEN as an enable signal for both receivers  13  and  21 , in the invention two receiver enable signals are provided: one RXEN′ for enabling receiver  13 , and the other RXEN″ for enabling receiver  21 . The reason for the two enable signals will become more apparent from the discussion below. 
     Returning to FIG. 3, the circuitry for generating and using the timing relationships illustrated in FIGS. 5 and 6 is shown as logic circuit  65 . Logic circuit  65  receives a conventional RXEN signal from RXEN generator  61 , the data clock DCLK signal, the clock signal BCLK and the four divided clock signals CLK  4  &lt; 0 : 3 &gt;, and the master clock MCLK signal to generate the respective receiver enable signals RXEN′ and RXEN″. 
     The details of logic circuit  65  are illustrated in FIGS. 7,  8  and  9 . 
     FIG. 7 illustrates a circuit which is utilized to identify the successive clock edges  0 ,  1 ,  2 ,  3  of the master clock signal MCLK. It includes a reset generator  71  and a logic circuit  73 . The output of logic circuit  73  are respective signals Sø, S 1 , S 2 , S 3  which are respectively generated in response to the MCLK clock signal edges  0 ,  1 ,  2 ,  3 . Logic circuit  73  contains a counter and there is an arbitrary relationship at initialization of the counter between the edges of incoming clock signal MCLK and the output signals Sø, S 1 , S 2 , S 3 . 
     In order to associate a clock edge of the MCLK signal with a particular one of the CLK  4  &lt; 0 : 3 &gt; signals, reset generator  71  is provided. The reset generator receives each of the CLK  4  &lt; 0 : 3 &gt; signals and, when a predetermined logic state relationship exists among the four clock signals CLK  4  &lt; 0 : 3 &gt;, a reset signal is generated to logic circuit  73 , which causes a resetting of the counter so that the next edge of the MCLK signal will generate an output So the second edge will generate the output signal S 1 ; the third edge will generate the output signal S 2 ; and the fourth edge will generate the output signal S 3  in a repeating sequence. 
     After resetting has occurred, logic circuit  73  will provide an acknowledgment signal back to reset generator  71  to prevent generator  71  from generating any further reset signals. As a consequence, logic circuit  73  will continue to supply successive repeating output signals Sø . . . S 3  as the successive edges  0 ,  1 ,  2 ,  3  . . . of the MCLK clock signal are continually counted. 
     FIG. 11 illustrates the timing diagram of the operation of the FIG. 7 circuit. Originally the MCLK clock signal has arbitrarily assigned clock edges as illustrated at the top of FIG.  11 . When the reset generator  71  recognizes a predetermined pattern in the applied CLK  4  &lt; 0 :&gt; clock signals, e.g.,  1110  as illustrated in FIG. 11, it causes a resetting of the master clock counter within logic circuit  73  so that the next MCLK clock pulse is now counted as the first clock edge MCLK 0 . Thus, as shown at the bottom of FIG. 11, the MCLK clock signal has now been realigned so that the MCLK clock  0  signal is substantially at the center of the pulse of the CLK  4  &lt; 0 &gt; signal; the MCLK  1  edge is substantially at the center of the CLK  4  &lt; 1 &gt; signal; the MCLK  2  edge is substantially at the center of the CLK  4  &lt; 2 &gt; signal; and the MCLK  3  edge is substantially at the center of the CLK  4  &lt; 4 &gt; signal. 
     The association of a particular MCLK clock edge to a particular one of the CLK  4  &lt; 0 : 3 &gt; signals, as shown in FIG. 11, results in the output signals Sø . . . S 3  from logic circuit  73  respectively identifying the first, second third and fourth edges as realigned and associated with respective one of the CLK  4  &lt; 0 : 3 &gt; signals. 
     The manner in which the RXEN′ and RXEN″ signals are generated will now be described with reference to FIGS. 8 and 9. 
     FIG. 8 illustrates the receiver enable RXEN signal, wich is generated from one of the MCLK clock signal edges  0  . . .  3 , applied to respective one bit registers  75 ,  77 ,  79  and  81 . Each of these registers respectively receives, as a latching signal, one of the signals Sø . . . S 3  denoting a respective edge of the MCLK signal. The output of registers  75  and  79  are applied as inputs to a multiplexer  83 , while the outputs of the registers  77  and  81  are applied as inputs to multiplexer  85 . Multiplexer  83  also receives selection signals Sel&lt; 0 &gt;, Sel&lt; 1 &gt;, Sel&lt; 2 &gt; and Sel&lt; 3 &gt;, whereas multiplexer  85  receives selection signals Sel&lt; 4 &gt;, Sel&lt; 5 &gt;, Sel&lt; 6 &gt;, and Sel&lt; 7 &gt;. The selection signals are generated by the logic circuit  93  illustrated at FIG.  9 . 
     Logic circuit  93  receives each of the four CLK  4  &lt; 0 : 3 &gt; clock signals. The CLK  4  &lt; 0 : 3 &gt; signals are capable of indicating eight different binary states, with each of these binary states being used to generate one of the selection signals Sel&lt; 0 &gt; . . . Sel&lt; 7 &gt;. 
     Returning to FIG. 8, each of the registers  75 ,  77 ,  79  and  81  is loaded with the RXEN signal when a respective latch signal Sø . . . S 3  is applied to the register. Thus, when the RXEN signal is generated and is applied to the registers  75 ,  77 ,  79  and  81 , one of the registers will be loaded with the RXEN signal before the others. This register will be latched by the edge of the MCLK signal as represented by one of Sø, S 1 , S 2 , or S 3  which generated the receiver enable RXEN signal in RXEN generator  61 . 
     The register which first receives the RXEN signal is then coupled by one of multiplexers  83  or  85  in response to the selection signals Sel&lt; 0 : 7 &gt; to an input of latch  87 . Latch  87  is provided with a positive input and a negative input. The positive and negative inputs respectively cause the latch  87  to latch in response to a positive going or negative going edge of an applied clock signal BCLK, which is the same clock signal in FIG. 2 at the output of buffer  35 . 
     Accordingly, that register  75 ,  77 ,  79  or  81  which first receives the RXEN signal, identifies that clock edge  0 ,  1 ,  2 ,  3  of the MCLK clock signal which was used to generate the RXEN signal. Multiplexer  83  will pass any positive going edge of the clock signal used to generate the RXEN signal to latch  87 , while multiplexer  85  will pass any negative going edge of the MCLK clock signal used to generate RXEN to latch  87 . Latch  87  will therefore latch in response to the next positive or negative going edge of BCLK and provide an output signal RXEN′ as selected by either the positive or negative input to latch  87 . 
     The output signal RXEN′ then becomes a new receiver enable signal, which is now applied to receiver  13  for the data path DQø . . . DQ 17  receivers. In addition, the RXEN′ signal is applied to another logic circuit  91  which is used to generate the RXEN″ signal, which is applied to receiver  21  in FIG.  1 . 
     Logic circuit  91  receives the DCLK clock signal which is used to terminate the generation of the RXEN″ signal as soon as the DCLK clock signal finishes a data burst signal. Returning to FIG. 4, a data write burst DCLK signal includes a preamble portion and then four clock edges denoted  0 ,  1 ,  2 ,  3 . When the third clock edge DCLK  3  finishes, this is sensed by the RXEN″ logic circuit  91 , which then terminates the RXEN″ signal. Thus, the receiver enable signal RXEN′ will remain on somewhat longer than the RXEN″ receiver enable signal. Logic circuit  91  also receives the RXEN signal as an enable signal. 
     An exemplary operation of the FIG. 8 circuit is illustrated by the timing diagrams of FIG.  10 . The relationship of the clocking signal edges of the realigned master clock MCLK to the associated CLK  4  &lt; 0 &gt; signal is illustrated by the top two timing diagrams. Respective selection signals Sel&lt; 0 &gt; . . . Sel&lt; 7 &gt; are further illustrated. These are the signals generated by logic circuit  93  of FIG.  9 . The RXEN signal generated by logic circuit  61  of FIG. 3 is also illustrated. If we assume that register stage A 0  is the first stage to receive the RXEN signal, that is register  75  first receives the RXEN signal, then the multiplexer  83  in response to selection signal Sel&lt; 0 &gt; will generate an output on the positive input to latch  87 . This will cause latch  87  to produce RXEN′ in response to the next positive going input of the BCLK clock signal, which is also illustrated in FIG.  10 . The RXEN′ signal at the output of the latch  87  is also applied as an input to the logic  91  which generates RXEN″ receiver enable signal. 
     As demonstrated above, the invention converts an unstable receiver enable signal RXEN into stable signals RXEN′ and RXEN″ which are keyed to a stable externally applied clock signal CCLK. Accordingly, the receiver enable signals respectively applied to receivers  13  and  21  will stably receive write data on the data paths and the data clocking signal DCLK without regard to timing changes in the MCLK signal or associated receiver enable signal RXEN. The invention therefore provides a reliable entry of data into the memory array no matter what the voltage and temperature characteristics of the memory device, which are otherwise used to compensate the timing of the master clock signal MCLK. 
     The invention may be used in a processor system. As shown in FIG. 12, a processor system, such as a computer system, for example, generally comprises a central processing unit (CPU)  210 , for example, a microprocessor, that communicates with one or more input/output (I/O) devices  240 ,  250  over a bus  270 . The computer system  200  also includes random access memory (RAM)  260 , a read only memory (ROM)  280  and may include peripheral devices such as a floppy disk drive  220  and a compact disk (CD) ROM drive  230  which also communicate with CPU  210  over the bus  270 . At least RAM  260  is formed of one or more integrated circuit memory devices which contain the invention as described above with reference to FIGS. 3 and 5 through  11 . 
     While the invention has been described and illustrated with respect to exemplary embodiments, it should be apparent that many modifications and substitutions may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as limited by the foregoing description, but is only limited by the scope of the appended claims.