Abstract:
A power supply for a liquid crystal display panel, comprising a booster generating unit for generating a power voltage by boosting a system voltage comprising at least one operational amplifier for generating a common voltage and a gamma reference voltage, the booster further comprising at least one capacitor, at least one inductor, and at least one resistance arranged outside an integrated circuit, a common voltage generating unit having at least one operational amplifier, at least one resistance and at least one capacitor, wherein the at least one operational amplifier is located within the integrated circuit, and a gamma voltage generating unit having at least one operational amplifier and a resistance network wherein the resistance network is located outside the integrated circuit.

Description:
The present invention claims the benefit of Korean Patent Application No. 89290/2001 filed in Korea on Dec. 31, 2001, which is hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a liquid crystal display panel, and more particularly, to a power supply for a liquid crystal display panel supplying a common voltage and a gamma reference voltage by using one integrated circuit (IC) chip and having a gate on/off voltage generating unit. 
     2. Description of the Related Art 
     In general, a liquid crystal display panel displays a picture on a screen by adjusting light transmittance of a liquid crystal according to picture information. The liquid crystal display panel includes liquid crystal cells arranged in a matrix form and a switching device such as a TFT (thin film transistor) corresponding to the liquid crystal cells to switch picture information supplied to each liquid crystal cell. 
     A driving unit of the liquid crystal display panel controls the switching device to supply the picture information to the corresponding liquid crystal cells. In addition, the driving unit of the liquid crystal display panel controls picture information so as to have positive and negative electricity within a specific voltage level in order to restrain picture deterioration such as flickering or an afterimage, and lower a driving voltage. 
     In general the liquid crystal display panel has gamma characteristics wherein gradation of a picture is varied nonlinearly according to a voltage level of picture information. The gamma characteristics are caused by light transmittance of liquid crystal. Light transmittance of the liquid crystal is not linearly varied according to a voltage level of picture information, and gradation of a picture is not linearly varied according to light transmittance of the liquid crystal. Accordingly, in order to vary the gradation of the picture according to a voltage level of picture information, by applying a preset gamma voltage to the voltage level of the picture information as an offset voltage, the gamma characteristics can be compensated and deterioration of the picture can be prevented. 
     In order to generate a driving voltage for controlling the switching device, a common voltage having a specific voltage level and a gamma voltage for compensating the gamma characteristics, voltage generating circuits are disposed in the liquid crystal display panel, and are described with reference to the accompanying drawings. 
       FIG. 1  is a schematic view of a block construction of a liquid crystal display panel and a driving unit thereof according to the related art. In  FIG. 1 , a liquid crystal display apparatus includes a liquid display panel  10  having a picture display unit  13 , a gate driving unit  20 , and a data driving unit  30 , a timing controller  40  for controlling a driving timing of the gate driving unit  20  and the data driving unit  30 , and a power unit  50  for supplying a voltage to the liquid crystal display panel  10 , the gate driving unit  20 , the data driving unit  30 , and the timing controller  40  by receiving a 3.3V system voltage (V SYS ). 
     In the picture display unit  13  of the liquid crystal display panel  10 , liquid crystal cells are arranged on a region at which gate wiring placed in the horizontal direction at regular intervals and data wiring placed in the vertical direction at regular intervals cross each other. In addition, the gate driving unit  20  of the liquid crystal display panel  10  drives the liquid crystal cells arranged in a matrix form by the gate wiring units by sequentially applying scanning signals to the gate wiring, and the data driving unit  30  applies picture information to the liquid crystal cells operated according to the scanning signals received through the data wiring. 
     The timing controller  40  supplies a control signal (CS) to the gate driving unit  20  and supplies the control signal (CS) and picture information (DATA [R,G,B]) to the data driving unit  30 . The timing controller  40  controls a timing operation of the gate driving unit  20  and the data driving unit  30  by supplying a certain clock signal, a gate start signal, and a timing signal as the control signal (CS). 
     The power unit  50  includes a gate driving voltage generating unit  51  for supplying gate on/off voltages (V G-ON , V G-OFF ) to the gate driving unit  20 ; a common voltage generating unit  52  for supplying a common voltage (Vcom) to a common electrode (not shown) of the picture display unit  13 ; and a gamma voltage generating unit  53  supplying a gamma voltage (V GMA ) for compensating the gamma characteristics to the data driving unit  30 . 
       FIG. 2  is a circuit diagram of a gate driving voltage generating unit of  FIG. 1 . In  FIG. 2 , the gate driving voltage generating unit  51  includes a booster  61  for generating a reference voltage (V REF ) of 7V by boosting the 3.3V system voltage (V SYS ), and a first and a second pumping units  62 ,  63  for generating the gate on/off voltages (V G-ON , V G-OFF ) by pumping and clamping the reference voltage (V REF ) of the booster  61 . The booster  61  includes an 11th node (N 11 ) in which the 3.3V system voltage (V SYS ) is applied and an 11th capacitor (C 11 ) contacted to an earth potential (VSS) therebetween, a 12th node (N 12 ) in which the earth potential (VSS) is periodically applied by the switching device (SW) and an 11th inductor (L 11 ) contacted to the 11th node (N 11 ) therebetween, a 13th node (N 13 ) in which a forward 11th diode (D 11 ) is contacted to the 12th node (N 12 ) therebetween, a 12th capacitor (C 12 ) contacted to the earth potential (VSS) therebetween, an 11th and a 12th resistance (R 11 , R 12 ) contacted to the earth potential (VSS) therebetween in order to boost the 3.3V system voltage (V SYS ) to the 7V reference voltage (V REF ) and outputting it. 
     The first pumping unit  62  includes a 21st node (N 21 ) in which a 21st capacitor (C 21 ) is contacted to the 12th node (N 12 ) therebetween, and a forward 21st diode (D 21 ) is contacted to the 13th node (N 13 ) of the booster  61  therebetween, a 22nd node (N 22 ) in which a 22nd capacitor (C 22 ) is contacted to the 13th node (N 13 ) of the booster  61  therebetween, and a forward 22nd diode (D 22 ) is contacted to the 21st node (N 21 ) therebetween, a 23rd node (N 23 ) in which a 23rd capacitor (C 23 ) is contacted to the 12th node (N 12 ) of the booster  61  therebetween, and a forward 23rd diode (D 23 ) is contacted to the 22nd node (N 22 ) therebetween, and a 24th node (N 24 ) in which a forward 24th diode (D 24 ) is contacted to the 23rd node (N 23 ) therebetween, and a 24th capacitor (C 24 ) is contacted to the earth potential (VSS) therebetween to output a 21V gate ON voltage (V G-ON ) by pumping and clamping the 7V reference voltage (V REF ). 
     The second pumping unit  63  includes a 31st node (N 31 ) in which a 31st capacitor (C 31 ) contacted to the 12th node (N 12 ) of the booster  61  therebetween and a backward 31st diode (D 31 ) contacted to the earth potential (VSS) therebetween; and a 32nd node (N 32 ) in which a backward 32nd diode (D 32 ) is contacted to the 31st node (N 31 ) therebetween and a 32nd capacitor (C 32 ) contacted to the earth potential (VSS) therebetween to output a −7V gate OFF voltage (V G-OFF ) by pumping and clamping the 7V reference voltage (V REF ). 
       FIG. 3  is a circuit diagram of a circuit construction of a common voltage generating unit of  FIG. 1 . In  FIG. 3 , the common voltage generating unit  52  includes a 41st and a 42nd resistance (R 41 , R 42 ) for dividing a power voltage (VDD), a variable resistance (VR 41 ) and a 41st capacitor (C 41 ) contacted between the 41st and 42nd resistance (R 41 , R 42 ) and adjusting a level of the divided power voltage (VDD), and a 41st operational amplifier (OP-AMP 41 ) receiving the power Voltage (VDD) divided by the 41st and 42nd resistance (R 41 , R 42 ) and level-adjusted by the variable resistance (VR 41 ) and the 41st capacitor (C 41 ) through a non-inversion terminal (+), receiving back an output thereof through an inversion terminal (−), adjusting a level through the 43 rd resistance (R 43 ) and the 42nd capacitor (C 42 ) and outputting it as the common voltage (Vcom). The 41st and 42nd resistance (R 41 , R 42 ) generate a specific level common voltage (Vcom) by dividing the power voltage (VDD) and applying it to the non-inversion terminal (+) of the 41st operational amplifier (OP-AMP 41 ). In order to vary the level of the common voltage (Vcom), a resistance value of the variable resistance (VR 41 ) is varied. 
       FIG. 4  is a circuit diagram of a circuit construction of a gamma voltage generating unit of  FIG. 1 . In  FIG. 4 , the gamma voltage generating unit  53  includes a high level unit  71  for generating high level gamma voltage (V GMAH1 ˜V GMAH5 ) having an inverted electricity per 1 horizontal cycle (1 Hs) according to dot inversion driving; and a low level unit  72  for generating low level gamma voltage (V GMAL1 ˜V GMAL5 ). The high level unit  71  divides the power voltage (VDD 51 ) according to a resistance ratio of the serially contacted 51st˜56th resistance (R 51 ˜R 56 ) and generates the high level gamma voltage (V GMAH1 ˜V GMAH5 ) in the 51st˜55th nodes (N 51 ˜N 55 ). The high level gamma voltage (V GMAH1 ) of the 51st node (N 51 ) has a voltage level corresponding to a black level, the high level gamma voltage (V GMAH3 ) of the 53rd node (N 53 ) has a voltage level corresponding to an intermediate level, and the high level gamma voltage (V GMAH5 ) of the 55th node (N 55 ) has a voltage level corresponding to a white level. From the high level gamma voltage (V GMAH1 ) of the 51st node (N 51 ) to the high level gamma voltage (V GMAH5 ) of the 55th node (N 55 ), the voltage level is decreased. 
     In addition, the low level unit  72  divides the power voltage (VDD 52 ) according to a resistance ratio of the serially contacted 57th˜62nd resistance (R 57 ˜R 62 ) and respectively generates the low level gamma voltage (V GMAL1 ˜V GMAL5 ) in the 56th˜60th nodes (N 56 ˜N 60 ). The low level gamma voltage (V GMAL1 ) of the 56th node (N 56 ) has a voltage level corresponding to a black level, the low level gamma voltage (V GMAL3 ) of the 58th node (N 58 ) has a voltage level corresponding to an intermediate level, and the low level gamma voltage (V GMAL5 ) of the 60th node (N 60 ) has a voltage level corresponding to a white level. From the low level gamma voltage (V GMAL1 ) of the 56th node (N 56 ) to the low level gamma voltage (V GMAL5 ) of the 60th node (N 60 ), the voltage level is increased. 
     The high level gamma voltage (V GMAH1 ˜V GMAH5 ) and the low level gamma voltage (V GMAL1 ˜V GMAL5 ) are respectively applied to the non-inversion terminal (+) of the 51st˜the 60th operational amplifiers (OP-AMP 51 ˜OP-AMP 60 ) through a bus line. The output of the 51st˜the 60th operational amplifiers (OP-AMP 51 ˜OP-AMP 60 ) is returned to the inversion terminal (−) and is outputted to the data driving unit  30  as the gamma voltage (V GMA1 ˜V GMA10 ) through the 51st˜the 60th capacitors (C 51 ˜C 60 ) respectively disposed in the output end of the 51st˜the 60th operational amplifiers (OP-AMP 51 ˜OP-AMP 60 ). 
     As described above, in the power supply of the related art liquid crystal display panel, the gate on/off voltage, the common voltage and the gamma reference voltage generating circuit required for operation of the liquid crystal display panel are separately constructed. Accordingly, since three or four IC chips and additional parts are required, it is difficult to lower production costs and maintain competitive prices. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a power supply for a liquid crystal display panel that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
     An object of the present invention is to provide a power supply of a liquid crystal display panel which is capable of supplying a common voltage and a gamma reference voltage required for operation of a liquid crystal display panel with one IC chip including a gate on/off voltage generating unit. 
     Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a power supply for a liquid crystal display panel includes a switching device for generating a power voltage by boosting a system voltage, a booster disposing an operational amplifier for generating a common voltage and operational amplifiers for generating a gamma reference voltage inside and having capacitors, an inductor and resistance arranged outside except the switching device, a common voltage generating unit having resistance and capacitors arranged outside except the operational amplifier, and a gamma voltage generating unit having a resistance network arranged outside except the operational amplifiers. 
     In another aspect, a power supply for a liquid crystal display panel, includes a booster generating unit for generating a power voltage by boosting a system voltage including at least one operational amplifier for generating a common voltage and a gamma reference voltage, the booster further comprising at least one capacitor, at least one inductor, and at least one resistance arranged outside an integrated circuit, a common voltage generating unit having at least one operational amplifier, at least one resistance and at least one capacitor, wherein the at least one operational amplifier is located within the integrated circuit, and a gamma voltage generating unit having at least one operational amplifier and a resistance network wherein the resistance network is located outside the integrated circuit. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: 
         FIG. 1  is a schematic view of a block construction of a liquid crystal display panel and a driving unit thereof according to the related art; 
         FIG. 2  is a circuit diagram of a gate driving voltage generating unit of  FIG. 1 ; 
         FIG. 3  is a circuit diagram of a common voltage generating unit of  FIG. 1 ; 
         FIG. 4  is a circuit diagram of a gamma voltage generating unit of  FIG. 1 ; 
         FIG. 5  is a schematic diagram of an exemplary power supply of a liquid crystal display panel according to the present invention; 
         FIG. 6  is a circuit diagram of a circuit construction of a booster of  FIG. 5 , according to the present invention; 
         FIG. 7  is circuit diagram of an exemplary gate on/off voltage generating unit added to the circuit construction of  FIG. 6 , according to the present invention; 
         FIG. 8  is a circuit diagram of an exemplary circuit construction of a common voltage generating unit of  FIG. 5 , according to the present invention; and 
         FIG. 9  is a circuit diagram of another exemplary circuit construction of a gamma voltage generating unit of  FIG. 5 , according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Reference will be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. 
       FIG. 5  is an exemplary view illustrating a power supply of a liquid crystal display panel in accordance with an embodiment of the present invention. In  FIG. 5 , a booster  101  for generating a 7V power voltage (VDD) by boosting a 3.3V system voltage (V SYS ), a common voltage generating unit  102  for supplying the common voltage (Vcom) to the liquid crystal display panel, and partial construction elements of a gamma voltage generating unit  103  for supplying a gamma voltage (V GMA ) to the data driving unit to compensate gamma characteristics may be placed in one IC chip  100 . 
     Functions of input/output pins of the IC chip  100  may be described in following Table 1. 
     
       
         
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 I/O pins 
                 Characteristics 
               
               
                   
               
             
             
               
                 Vswl 
                 Channel 1 switch out pin 
               
               
                 FB 
                 Channel 1 feedback voltage from 
               
               
                   
                 fixed output voltage 
               
               
                 Vin 
                 Input supply voltage 
               
               
                 Vc 
                 Channel 1 frequency compensation, etc. 
               
               
                 SHDN 
                 Channel 1 shut\down pin. High is 
               
               
                   
                 enable/Low is disable 
               
               
                 SS 
                 Channel 1 soft-start pin 
               
               
                 NC 
                 NC or Switching Frequency 
               
               
                   
                 selection option pin 
               
               
                 GND 
                 Boost PWM Ground 
               
               
                 Vs+ 
                 Buffer (+) supply voltage 
               
               
                 Vs− 
                 Buffer (−) supply voltage 
               
               
                 Vcom-in 
                 Common-node buffer input pin 
               
               
                 Vcom-out 
                 Common-node buffer output pin 
               
               
                 GMA1-in~GMA4-in 
                 Gamma buffer input pin 
               
               
                 GMA1-out~GMA4-out 
                 Gamma buffer output pin 
               
               
                   
               
             
          
         
       
     
       FIG. 6  is a circuit diagram illustrating the booster of  FIG. 5 . In  FIG. 6 , in the booster  101 , the switching device (SW) of the booster  101  may be disposed in the IC chip  100 , except the diode (D 101 ), capacitors (C 101 , C 102 ), an inductor (L 101 ) and resistance (R 101 , R 102 ) are arranged outside. 
     The booster  101  may include a 101st node (N 101 ) in which the 3.3V system voltage (V SYS ) is applied and a 101st capacitor (C 101 ) which may be contacted to an earth potential (VSS) therebetween; a 102nd node (N 102 ) in which the earth potential (VSS) may be periodically applied by the switching device (SW) disposed in the IC chip  100  and a 101st inductor (L 101 ) which may be contacted to the 101st node (N 101 ) therebetween; and a 103rd node (N 103 ) in which a forward 101st diode (D 101 ) may be contacted to the 102nd node (N 102 ) therebetween, a 102nd capacitor (C 102 ) may be contacted to the earth potential (VSS) therebetween, a 101st and a 102nd resistance (R 101 , R 102 ) which may be serially contacted to the earth potential (VSS) therebetween in order to boost the 3.3V system voltage (V SYS ) as the 7V power voltage (VDD) and outputting it. 
       FIG. 7  is an exemplary view illustrating a gate on/off voltage generating unit added to the circuit construction of  FIG. 6 . In  FIG. 7  the gate on/off voltage generating unit, may have a first and a second pumping units for generating the gate on/off voltage, added to the circuit construction of  FIG. 6 . In  FIG. 7 , a first pumping unit  110  may include a 111th node (N 111 ) in which a 111th capacity (C 111 ) may be contacted to the 102nd node (N 102 ) therebetween and a forward 111th diode (D 111 ) which may be contacted to the 103rd node (N 103 ) of the booster  101  therebetween; a 112th node (N 112 ) in which a 112th capacitor (C 112 ) may be contacted to the 103rd node (N 103 ) of the booster  101  therebetween and a forward 112th diode (D 112 ) which may be contacted to the 111th node (N 111 ) therebetween; a 113th node (N 113 ) in which a 113th capacitor (C 113 ) may be contacted to the 102nd node (N 102 ) of the booster  101  therebetween and a forward 113th diode (D 113 ) which may be contacted to the 112th node (N 112 ) therebetween; and a 114th node (N 114 ) in which a forward 114th diode (D 114 ) may be contacted to the 113th node (N 113 ) therebetween and a 114th capacitor (C 114 ) which may be contacted to the earth potential (VSS) therebetween to output a 21V gate ON voltage (V G-ON ) by pumping and clamping the 7V power voltage (VDD). 
     A second pumping unit  120  may include a 121st node (N 121 ) in which a 121st capacitor (C 121 ) may be contacted to the 102nd node (N 102 ) of the booster  101  therebetween and a backward 121st diode (D 121 ) which may be contacted to the earth potential (VSS) therebetween; and a 122nd node (N 122 ) in which a backward 122nd diode (D 122 ) may be contacted to the 121st node (N 121 ) therebetween and a 122nd capacitor (C 122 ) which may be contacted to the earth potential (VSS) therebetween to output a −7V gate OFF voltage (V G-OFF ) by pumping and clamping the 7V power voltage (VDD). 
       FIG. 8  is a circuit diagram illustrating a circuit construction of the common voltage generating unit  102  of  FIG. 5 . In  FIG. 8 , in the common voltage generating unit  102 , a 131 operational amplifier (OP-AMP 131 ) of the common voltage generating unit  102  may be placed in the IC chip  100 , except that the resistance (R 131 ˜R 133 , VR 131 ) and capacitors (C 131 , C 132 ) may be arranged outside. 
     The common voltage generating unit  102  may include a 131st and a 132nd resistance (R 131 , R 132 ) for dividing the power voltage (VDD); a variable resistance (VR 131 ) and a 131st capacitor (C 131 ) contacted between the 131st and 132nd resistance (R 131 , R 132 ) and adjusting a level of the divided power voltage (VDD); and a 131st operational amplifier (OP-AMP 131 ) disposed in the IC chip  100 , receiving the power Voltage (VDD) divided by the 131st and 132nd resistance (R 131 , R 132 ) and level-adjusted by the variable resistance (VR 131 ) and the 131st capacitor (C 131 ) through a non-inversion terminal (+), receiving back an output thereof through an inversion terminal (−), adjusting a level through the 133rd resistance (R 133 ) and the 132nd capacitor (C 132 ) and outputting it as the common voltage (Vcom). The 131st and 132nd resistance (R 131 , R 132 ) generates a specific level common voltage (Vcom) by dividing the power voltage (VDD) and applying it to the non-inversion terminal (+) of the 131st operational amplifier (OP-AMP 131 ), in order to vary the level of the common voltage (Vcom), a resistance value of the variable resistance (VR 131 ) is varied. 
       FIG. 9  is a circuit diagram illustrating the gamma voltage generating unit  103  of  FIG. 5 . In  FIG. 9 , in the gamma voltage generating unit  103 , the 141˜150 operational amplifiers (OP-AMP 141 ˜OP-AMP 150 ) of the gamma voltage generating unit  103  are disposed in the IC chip  100 , except that the resistance networks (R 141 ˜R 152 ) are arranged outside. 
     The gamma voltage generating unit  103  includes a high level unit  130  for generating high level gamma voltage (V GMAH141 ˜V GMAH145 ) for generating a gamma voltage having an inverted electricity per 1 horizontal cycle according to dot inversion driving; and a low level unit  140  for generating low level gamma voltage (V GMAL141 ˜V GMAL145 ). 
     The high level unit  130  divides the power voltage (VDD 141 ) according to a resistance ratio of the serially contacted 141st˜146th resistance (R 141 ˜R 146 ) and respectively generates the high level gamma voltage (V GMAH141 ˜V GMAH145 ) in the 141st˜145th nodes (N 141 ˜N 145 ). The high level gamma voltage (V GMAH141 ) of the 141st node (N 141 ) has a voltage level corresponding to a black level, the high level gamma voltage (V GMAH143 ) of the 143rd node (N 143 ) has a voltage level corresponding to an intermediate level, and the high level gamma voltage (V GMAH145 ) of the 145th node (N 145 ) has a voltage level corresponding to a white level. From the high level gamma voltage (V GMAH141 ) of the 141st node (N 141 ) to the high level gamma voltage (V GMAH145 ) of the 145th node (N 145 ), the voltage level is decreased. 
     In addition, the low level unit  140  divides the power voltage (VDD 142 ) according to a resistance ratio of the serially contacted 147th˜152nd resistance (R 147 ˜R 152 ) and respectively generates the low level gamma voltage (V GMAL141 ˜V GMAL145 ) in the 146th˜150th nodes (N 146 ˜N 150 ). 
     The low level gamma voltage (V GMAL141 ) of the 146th node (N 146 ) has a voltage level corresponding to a black level, the low level gamma voltage (V GMAL143 ) of the 148th node (N 148 ) has a voltage level corresponding to an intermediate level, and the low level gamma voltage (V GMAL145 ) of the 150th node (N 150 ) has a voltage level corresponding to a white level. From the low level gamma voltage (V GMAL141 ) of the 146th node (N 146 ) to the low level gamma voltage (V GMAL145 ) of the 150th node (N 150 ), the voltage level is increased. 
     The high level gamma voltage (V GMAH141 ˜V GMAH145 ) and the low level gamma voltage (V GMAL141 ˜V GMAL145 ) are respectively applied to the non-inversion terminal (+) of the 141st˜the 150th operational amplifiers (OP-AMP 141 ˜OP-AMP 150 ) through a bus line, output of the 141st˜the 150th operational amplifiers (OP-AMP 141 ˜OP-AMP 150 ) is returned to the inversion terminal (−) and is outputted to the data driving unit as the gamma voltage (V GMA141 ˜V GMA150 ) through the 141st˜the 150th capacitors (C 141 ˜C 150 ) respectively disposed in the output end of the 141st˜the 150th operational amplifiers (OP-AMP 141 ˜OP-AMP 150 ). 
     As described above, in the power supply of the liquid crystal display panel in accordance with the present invention, by supplying the common voltage and the gamma reference voltage required for the operation of the liquid crystal display panel in one IC circuit and adding the gate on/off voltage generating unit, construction parts can be reduced, and accordingly production costs can be lowered and design can be simplified. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the power supply for the liquid crystal display panel without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.