Abstract:
A computer system and method for selectively supporting at least one registered dual inline memory module or at least one unbuffered dual inline memory module is disclosed. The computer system includes a printed circuit board, at least one registered/unbuffered dual mode dual inline memory module socket, a central processing unit for communicating three sets of clock signals to each of the registered/unbuffered dual mode dual inline memory module sockets, and a basic input/output system for detecting a memory type of a memory module inserted in each of the registered/unbuffered dual mode dual inline memory module sockets.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a computer system and method, and, more particularly, to a computer system and method for selectively supporting at least one registered dual inline memory module or at least one unbuffered dual inline memory module.  
         [0003]     2. Description of the Related Art  
         [0004]     Unbuffered dual inline memory modules (unbuffered DIMMs) and registered dual inline memory modules (registered DIMMs) are two common memory module types.  
         [0005]     Unbuffered DIMMs are dual inline memory modules that are not buffered, and are typically used for desktop computers. Unbuffered DIMMs have various benefits, such as being inexpensive, popular, and providing fast speeds and high performance characteristics.  
         [0006]     Registered DIMMs are dual inline memory modules whose address and control signals are registered, clocks are locked by phase locked loops (PLL), and are used for workstations and servers. Registered DIMMs provide better stability, but have the draw backs of slower speeds and higher prices; registered DIMMs are often used in products that require higher memory capacities.  
         [0007]     One important difference between registered DIMMs and unbuffered DIMMs is the required number of clock pins for the central processor. A registered DIMM only requires 1 clock pin for sending 1 set of clock signals, whereas the unbuffered DIMM requires 3 clock pins for sending 3 sets of clock signals. Therefore, if the central processor of the computer system is capable of only supporting registered DIMMs, such as an AMD K8 Opteron CPU, the computer system will be unable to use unbuffered DIMMs.  
         [0008]     However, registered DIMMs are more expensive and have slower speeds; if the computer system only supports registered DIMMs and not unbuffered DIMMs, the computer system will have fewer memory options and higher costs.  
         [0009]     Although, U.S. Pat. No. 6,711,464 discloses a technology that permits registered/buffered memory modules to be used as regular registered/buffered memory modules or as unbuffered memory modules by enabling or disabling the register or buffer of the registered/buffered memory module. But a computer system with this technology still requires more expensive registered memory modules to serve as unbuffered memory modules. Therefore, U.S. Pat. No. 6,711,464 does not resolve the issue of high costs.  
         [0010]     Therefore, it is desirable to provide a computer system and method for selectively supporting at least one registered dual inline memory module or at least one unbuffered dual inline memory module to mitigate and/or obviate the aforementioned problems.  
       SUMMARY OF THE INVENTION  
       [0011]     A main objective of the present invention is to provide a computer system and method for selectively supporting at least one registered dual inline memory module or at least one unbuffered dual inline memory module, which increases convenience and memory selection options.  
         [0012]     In order to achieve the above-mentioned objective, the present invention provides a computer system for selectively supporting at least one registered dual inline memory module or at least one unbuffered dual inline memory module. The computer system comprises a printed circuit board (PCB), at least one registered/unbuffered dual memory module socket, a processor, at least three sets of signal wires and a BIOS.  
         [0013]     The at least one registered/unbuffered dual memory module socket is disposed on the printed circuit board, wherein each registered/unbuffered dual mode memory module socket is configured for selectively accepting a registered memory module or an unbuffered memory module; the processor is disposed on the printed circuit board and is configured for sending three sets of clock signals to each registered/unbuffered dual mode memory module socket, wherein one set of clock signals is provided for the registered memory module and the unbuffered memory module to share, and the other sets of clock signals are provided for the unbuffered memory module; at least three sets of signal wires are disposed on the printed circuit board and are configured for sending three sets of clock signals from the processor to the registered/unbuffered dual mode memory module socket; and basic input/output system (BIOS) is disposed on the printed circuit board, the BIOS capable of detecting a memory type of a memory module inserted in each of the at least one registered/unbuffered dual mode memory module socket.  
         [0014]     In an embodiment, three clock pins of the processor are connected to three corresponding pins of each registered/unbuffered dual mode dual inline memory module socket to send the three sets of clock signals from the processor to each registered/unbuffered dual mode dual inline memory module socket. A Pitch of each of the at least three sets of signal wires substantially corresponds to pitch requirements of the registered memory module and pitch requirements of the unbuffered memory module.  
         [0015]     In one embodiment of the present invention, at least one unbuffered memory module socket is provided for accepting the registered memory module; or at least one unbuffered memory module socket is provided for accepting the unbuffered memory module.  
         [0016]     In one embodiment of the present invention, the registered memory module is a registered DIMM, and the unbuffered memory module is an unbuffered DIMM. Furthermore, the processor is a CPU.  
         [0017]     Furthermore, the present invention also provide a method for enabling a computer system to selectively accept at least one registered memory module or at least one unbuffered memory module, the computer system comprising a processor and a BIOS, the method comprises:  
         [0018]     1. configuring at least one registered/unbuffered dual memory module socket, wherein each registered/unbuffered dual memory module socket is configured for selectively accepting a registered memory module or an unbuffered memory module;  
         [0019]     2. sending at least three sets of clock signals to each registered/unbuffered dual memory module socket, wherein one set of clock signals is provided for the registered memory module and the unbuffered memory module to share, and the other sets of clock signals are provided for the unbuffered memory module; and  
         [0020]     3. providing at least three sets of signal wires for sending the at least three sets of clock signals to such that a pitch of each of the at least three sets of signal wires substantially corresponds to pitch requirements of the registered memory module and pitch requirements of the unbuffered memory module; and  
         [0021]     4. detecting each registered/unbuffered dual memory module socket to determine whether a registered memory module or an unbuffered memory module is inserted in the registered/unbuffered dual memory module socket.  
         [0022]     In one embodiment of the present invention, the method of the present invention further comprises:  
         [0023]     1. providing at least one registered memory module socket, wherein each registered memory module socket is configured for accepting a registered memory module; and  
         [0024]     2. sending a set of clock signals to each registered memory module socket for the registered memory module.  
         [0025]     Alternatively, in one embodiment of the present invention, the method of the present invention further comprises:  
         [0026]     1. providing at least one unbuffered memory module socket, wherein each unbuffered memory module socket is configured for accepting an unbuffered memory module; and  
         [0027]     2. sending a set of clock signals to each unbuffered memory module socket for the unbuffered memory module.  
         [0028]     Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]      FIG. 1  shows a computer system according to a first embodiment of the present invention.  
         [0030]      FIG. 2  shows a computer system according to a second embodiment of the present invention.  
         [0031]      FIG. 3  is a flowchart of the method of the first embodiment according to the present invention.  
         [0032]      FIG. 4  is a flowchart of the method of the second embodiment according to the present invention  
         [0033]      FIG. 5  is a flowchart of the method of a third embodiment according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0034]     In the prior art, the memory types of certain computer systems are limited by the types of CPUS. Consequently, although the socket shared by registered/unbuffered memory modules with the standards set by JEDEC (Joint Electron Device Engineering Council)has three clock pins, if the central processor in the computer system only supports registered DIMMs, as with the AMD K8 Opteron CPU, then the computer system cannot support unbuffered DIMMs. However, the present invention enables the processor to support both registered DIMMs and unbuffered DIMMs.  
         [0035]     Please refer to  FIG. 1 .  FIG. 1  shows a computer system supporting both registered memory modules and unbuffered memory modules in a first embodiment according to the present invention.  
         [0036]     As shown in  FIG. 1 , the computer system of the present invention comprises a printed circuit board  10 , two registered/unbuffered dual memory module sockets  20 ,  22 , a processor  30  and a BIOS  40 . The registered/unbuffered memory module sockets  20 ,  22 , the processor  30  and the BIOS  40  are all disposed on the printed circuit board  10 .  
         [0037]     In the first embodiment, the registered/unbuffered memory module sockets  20 ,  22  are registered/unbuffered DIMM sockets, which can be selectively used for accepting a registered DIMM (not shown) or an unbuffered DIMM (not shown). The processor  30  is a CPU, and the printed circuit board  10  is a motherboard.  
         [0038]     As shown in  FIG. 1 , the registered/unbuffered memory module socket  20  has 3 clock pins P 201 , P 202  and P 203 ; the registered/unbuffered memory module socket  22  has 3 clock pins P 221 , P 222  and P 223 ; and the processor  30  has 6 clock pins P 301 , P 302 , P 303 , P 304 , P 305  and P 306  individually corresponding to the 6 clock pins P 201 , P 202 , P 203  and P 221 , P 222 , P 223  of registered/unbuffered memory module sockets  20 ,  22 .  
         [0039]     The 6 clock pins P 301 , P 302 , P 303 , P 304 , P 305  and P 306  of the processor  30  can be electrically connected to the 6 clock pins P 201 , P 202 , P 203  and P 221 , P 222 , P 223  of registered/unbuffered memory module sockets  20 ,  22  via signal wires L 1 , L 2 , L 3 , L 4 , L 5  and L 6 , and respectively send three sets of clock signals to the registered/unbuffered memory module sockets  20 ,  22 . One set of clock signals (for example, the clock signal sent by the signal wires L 1  or L 4 ) is provided to the registered memory module and the unbuffered memory module to share, and the other two sets of clock signals (for example, the clock signal sent by the signal wires L 2 , L 3  or L 5 , L 6 ) are provided to the unbuffered memory module.  
         [0040]     Registered memory modules have looser pitch requirements on each pitch of the signal wires, while unbuffered memory modules have more strict pitch requirements on each pitch of the signal wires (i.e., allowing for smaller pitch errors). Therefore, in one embodiment of the invention, the signal wires L 1 , L 2 , L 3 , L 4 , L 5  and L 6  are configured for respectively matching the pitch requirements of each pitch of the signal wires of the registered memory module and the unbuffered memory module.  
         [0041]     When the registered/unbuffered memory module socket  20  or  22  accepts a registered memory module, a set of clock signals is provided to the registered memory module; and when the registered/unbuffered memory module socket  20  or  22  accepts an unbuffered memory module, three sets of clock signals are provided to the unbuffered memory module. Because the registered memory module only requires one set of clock signals and the unbuffered memory module requires three sets of clock signals, the configuration of the invention as shown in  FIG. 1  is capable of supporting both the registered memory module and the unbuffered memory module.  
         [0042]     As shown in  FIG. 1 , the BIOS  40  is also disposed on the printed circuit board  10  and electrically connected to the registered/unbuffered dual memory module sockets  20  and  22 , as well as to the processor  30 . When the registered/unbuffered dual memory module socket  20  or  22  has a registered memory module or an unbuffered memory module in it, the BIOS  40  is capable of identifying whether the module is a registered memory module or an unbuffered memory module, and then the computer system adjust settings to support a registered memory module or an unbuffered memory module as required. The BIOS  40  is used to identify the type of memory and finding the corresponding memory time parameters, but this is a well known technology, and therefore requires no further description.  
         [0043]     Although in the embodiment shown in  FIG. 1  there are only two registered/unbuffered dual memory module sockets  20  and  22 , the present invention is not be limited to this number, and as long as the processor  30  can support the required clock signals, the present invention can support more registered/unbuffered dual memory module sockets. Alternatively, the present invention may also have a registered memory module socket for only registered memory modules and/or an unbuffered memory module socket for only unbuffered memory modules.  
         [0044]     For example, as shown in  FIG. 2 , in a second embodiment, the processor  30  is an AMD K8 Opteron CPU and has 8 clock pins P 301 , P 302 , P 303 , P 304 , P 305 , P 306 , P 307  and P 308 , which are indicated as (U 24 , U 25 ), (AA 23 , Y 23 ), (AD 20 , AD 21 ), (J 23 , H 23 ), (T 23 , R 23 ), (L 25 , L 24 ), (AE 20 , AE 21 ) and (G 21 , G 20 ), and which are used for sending 8 sets of clock signals. The present invention can therefore have two registered/unbuffered dual memory module sockets  20  and  22  that are connected to 6 clock pins, and two registered memory module sockets  24  and  26  for only registered memory modules that are connected to the remaining 2 clock pins P 307  and P 308  via the signal wires L 7  and L 8  with their clock pins P 241  and P 242 ; a set of clock signals can thus be sent to each registered memory module socket  24  and  26 . The computer system of the present invention can thus selectively support two unbuffered memory modules, or two unbuffered memory modules and two registered memory modules, or four registered memory modules.  
         [0045]     The present invention provides a method for enabling a computer system to selectively accept at least one registered memory module or at least one unbuffered memory module. Please refer to  FIG. 3 .  FIG. 3  is a flowchart of the method in the first embodiment according to the present invention.  
         [0046]     As shown in  FIG. 3 , in step S 11 , at least one registered/unbuffered dual memory module socket is configured. Each registered/unbuffered dual memory module socket is configured for selectively accepting a registered memory module or an unbuffered memory module. For example, as shown in  FIG. 1 , there are two registered/unbuffered dual memory module sockets  20  and  22 .  
         [0047]     In step S 12 , three sets of clock signals are respectively sent to each registered/unbuffered dual memory module socket. One set of clock signals are provided for the registered memory module and the unbuffered memory module to share, and the other sets of clock signals are provided to the unbuffered memory module. For example, as shown in  FIG. 1 , the processor  30  respectively sends three sets of clock signals to the registered/unbuffered dual memory module sockets  20  and  22 .  
         [0048]     Moreover, in step S 12 , the signal wires for sending the clock signals are designed to match the pitch requirements of the registered memory module and the pitch requirements of the unbuffered memory module.  
         [0049]     Next, in step S 13 , each registered/unbuffered dual memory module socket undergoes detection to identify whether a registered memory module or an unbuffered memory module is inserted into the registered/unbuffered dual memory module socket. For example, as shown in  FIG. 1 , the BIOS  40  detects the registered/unbuffered dual memory module sockets  20  and  22  and identifies the type of the memory inserted into the module socket  20  and  22 .  
         [0050]     In one embodiment of the present invention, as shown in  FIG. 4 , in step S 14 , at least one unbuffered memory module socket is provided. Each unbuffered memory module socket is configured for accepting an unbuffered memory module. In step S 15 , a set of clock signals is sent to each registered memory module socket for the registered memory module. In step S 16 , the registered memory module socket undergoes detection to identify whether there is a registered memory module installed.  
         [0051]     Alternatively, as shown in  FIG. 5 , in step S 17 , at least one unbuffered memory module socket is provided. Each unbuffered memory module socket is configured for accepting an unbuffered memory module. In step S 18 , a set of clock signals is sent to each unbuffered memory module socket for the unbuffered memory module. In step S 19 , the unbuffered memory module socket undergoes detection to identify whether there is an unbuffered memory module installed.  
         [0052]     The method of the present invention enables computer systems to selectively accept at least one registered memory module and at least one unbuffered memory module.  
         [0053]     Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.