Abstract:
A method of stabilizing the DUV resist etch rate for a gate critical dimension, especially for a CD≦75 μm. More specifically, the present invention provides a method for stabilizing a deep ultraviolet (DUV) resist etch rate by utilizing the directly proportionate relationship between the lateral erosion and a vertical etch rate. The present invention method provides control of lateral erosion of the DUV resist by measuring the vertical etch rate component. The present invention method involves conditioning (seasoning) an etch chamber with a conditioning wafer having a unique stack which results in consistent and stable DUV resist etch rates. The present invention seasoning is applied before processing of a product wafer lot for providing better control of the gate CD targeting, and thereby eliminating a “first wafer” effect.

Description:
FIELD OF THE INVENTION 
     The present invention relates to small high density semiconductor devices. More particularly, the present invention relates to photoresist etching methods in the fabrication of semiconductor devices. Even more particularly, the present invention relates to stabilizing the a deep ultraviolet photoresist (hereinafter “resist”) etch rate for a gate critical dimension (hereinafter “CD”) of a semiconductor device. 
     BACKGROUND OF THE INVENTION 
     Currently, the need for high performance devices and low manufacturing cost has driven the semiconductor industry to higher density and smaller devices. In order to achieve the high density, the gate length of less than 100 nm is required. To cost-effectively achieve such gate lengths using current lithographic techniques is difficult, prompting the development of alternative methods. One such method of achieving smaller final CDs comprises lateral eroding of only a DUV resist before etching the gate material. This etch process involves several parameters (e.g., chemistry, system design, ion density, system pressure). Ion density is a function of applied power while the system pressure affects the mean free path of the ions. System pressures typically range from 0.4 mTorr to 50 mTorr while etch rates typically range from 600 Å/min to 2000 Å/min. 1  This method has been shown to be effective in minimizing the gate length to not less than 75 nm in a device; however, this DUV resist etch rate is found to be unstable and results in poor CD control. Due to cost concerns, the related art methods may involve seasoning a chamber with used polysilicon-only test wafers or resist-only coated wafers. This related art seasoning method provides only low and erratic resist etch rates which produces inconsistently etched layers, especially with respect to resist layers, in product wafers. Thus, wide spread etch rates lead to the related art problem of etch rate inconsistency. Therefore, a need exists for a method of stabilizing the DUV resist etch rate for a gate CD. 
       1 Peter Van Zant, Microchip Fabrication—A Practical Guide to Semiconductor Processing 3 rd  Ed., pp. 268-269 (1997).  
     BRIEF SUMMARY OF THE INVENTION 
     Accordingly, the present invention provides a method of stabilizing the DUV resist etch rate for a gate CD of ≦75 μm. More specifically, the present invention provides a method for stabilizing lateral erosion rate of the DUV resist by utilizing the directly proportionate relationship between the lateral erosion rate and a vertical etch rate: 
     
       
           R   L   =kR   V , 
       
     
     where R L  is the lateral erosion rate (i.e., trim rate) of the resist, R V  is the vertical resist etch rate, and k is, therefore, a constant defined by the ratio of the trim rate to the vertical resist etch rate for any given set of photoresist and etchant combinations and conditions. Since measuring the lateral erosion is difficult, the present invention method provides better control of the DUV resist etch rate by measuring the vertical etch rate component. The present invention method involves a unique conditioning (i.e., seasoning) procedure using a distinct formulation in a decoupled plasma source (DPS) polysilicon etch chamber which results in consistent and stable DUV resist etch rates. The present invention seasoning is applied before processing of the wafer lot for providing better control of the gate CD targeting, and thereby possibly eliminating a “first wafer” effect. 
     In general, the present invention method of stabilizing a resist etch rate for at least one product wafer having at least one gate, comprises: (a) conditioning an etch chamber with a volatilized polymeric material, and thereby reducing etch chamber wall effects on an etchant; (b) providing a pilot wafer; (c) etching the pilot wafer in the etch chamber using the etchant, in accordance with a given etching technique; (d) verifying an optimum etch chamber conditioning, and if the optimum etch chamber conditioning is acceptable, proceeding to step (e), otherwise reconditioning the etch chamber by returning to step (a); (e) providing the at least one product wafer; and (f) etching the at least one product wafer in the etch chamber using the etchant, in accordance with the given etching technique. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING(S) 
     For a better understanding of the present invention, reference is made to the below referenced accompanying drawings. 
     FIG. 1 a  is a cross-sectional view of a conditioning wafer, having a stack comprising a gate oxide layer, a polysilicon layer, a dielectric layer comprising a material such as silicon oxynitride or a silicon nitride, and a resist layer such as a DUV photoresist layer, before etching, in accordance with the present invention. 
     FIG. 1 b  is a cross-sectional view of a conditioning wafer, having a stack comprising a gate oxide layer, a polysilicon layer, a dielectric layer comprising a material such as silicon oxynitride or a silicon nitride, and a resist layer such as a DUV photoresist layer, after etching, in accordance with the present invention. 
     FIG. 1 c  is a cross-sectional view of at least one conditioning wafer, having a stack comprising a gate oxide layer, a polysilicon layer, a dielectric layer comprising a material such as silicon oxynitride or a silicon nitride, and a resist layer such as a DUV photoresist layer in an etch chamber being etched, thereby volatilizing a polymeric material for deposition onto the etch chamber wall, in accordance with the present invention. 
     FIG. 1 d  is a cross-sectional view of a pilot wafer in an etch chamber having a volatilized polymeric material deposited on the etch chamber wall, in accordance with the present invention. 
     FIG. 2 a  is a graph of the comparative DUV resist etch rate (Å/min) of a pilot wafer in terms of a date time-line before and after implementation of a conditioning wafer, in accordance with the present invention. 
     FIG. 2 b  comprises Table 1 which displays test data corresponding to the graph of FIG. 2, in accordance with the present invention. 
     FIG. 3 is flowchart of the method of stabilizing the DUV resist etch rate for a gate CD, in accordance with the present invention. 
     Reference numbers refer to the same or equivalent parts of the present invention throughout the several figures of the drawings. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 a  is a cross-sectional view of a conditioning wafer  10 , having a stack  20  comprising a gate oxide layer  21 , a polysilicon layer  22 , a dielectric layer  23  comprising at least one material selected from a group consisting essentially of a silicon oxynitride (SiON) or a silicon nitride (Si x N y , preferably silicon-rich silicon nitride, i.e., Si 3+n N 4 ), and a resist layer  24  such as a DUV photoresist layer, before etching, in accordance with the present invention. 
     FIG. 1 b  is a cross-sectional view of a conditioning wafer  10 , having a stack  20  comprising a gate oxide layer  21 , a polysilicon layer  22 , a dielectric layer  23  comprising at least one material selected from a group consisting essentially of a silicon oxynitride (SiON) or a silicon nitride (Si x N y , preferably silicon-rich silicon nitride, i.e., Si 3+n N 4 ), and a resist layer  24  such as a DUV photoresist layer, after etching, in accordance with the present invention. 
     FIG. 1 c  is a cross-sectional view of at least one conditioning wafer  10 , having a stack  20  comprising a gate oxide layer  21 , a polysilicon layer  22 , a dielectric layer  23  comprising at least one material selected from a group consisting essentially of a silicon oxynitride (SiON) or a silicon nitride (Si x N y , preferably silicon-rich silicon nitride, i.e., Si 3+n N 4 ), and a resist layer  24  such as a DUV photoresist layer in an etch chamber  30  being etched by an etchant  32 , thereby volatilizing a polymeric material  25  for deposition onto the etch chamber wall  31 , in accordance with the present invention. 
     FIG. 1 d  is a cross-sectional view of a pilot wafer  11  in the etch chamber  30  having the volatilized polymeric material  25  deposited on the etch chamber wall  31 , in accordance with the present invention. The volatilized polymeric material  25  may comprise some material emanating from the resist layer; and some material emanating from at least one layer selected from a group consisting essentially of the dielectric layer, the polysilicon layer, and the gate oxide layer. 
     FIG. 2 a  is a graph of the comparative DUV resist etch rate (Å/min) of a pilot wafer  11  in terms of a date time-line before and after implementation of a conditioning wafer  10 , in accordance with the present invention. 
     FIG. 2 b  comprises Table 1 which displays test data corresponding to the graph of FIG. 2, in accordance with the present invention. FIG. 2 b  tabulates a group of parameters which include average preconditioning etch rate, average post-conditioning etch rate, average etch rate change Δ, average etch rate, unified etch rate, and standard etch rate as a function of date and time as well as conditioning formulation and conditioning iterations. 
     FIG. 3 flowcharts a method M of stabilizing a resist etch rate for at least one product wafer having at least one gate, in accordance with the present invention, comprising: (a) conditioning an etch chamber  30  with a volatilized polymeric material  25 , and thereby reducing etch chamber wall effects on an etchant  32 , as indicated by block  100 ; (b) providing a pilot wafer  11 , as indicated by block  200 ; (c) etching the pilot wafer  11  in the etch chamber  30  using the etchant  32 , in accordance with a given etching technique, as indicated by block  300 ; (d) verifying an optimum etch chamber conditioning, and if the optimum etch chamber conditioning is acceptable, proceeding to step (e), otherwise reconditioning the etch chamber  30  by returning to step (a), as indicated by block  400 ; (e) providing the at least one product wafer  12 , as indicated by block  500 ; and (f) etching the at least one product wafer  12  in the etch chamber  30  using the etchant  32 , in accordance with the given etching technique, as indicated by block  600 , wherein said step (a) may comprise: (1) providing at least one stacked conditioning wafer  10  having a stack  20 ; (2) placing the at least one stacked conditioning wafer  10  in the etch chamber  30 ; and (3) etching the at least one stacked conditioning wafer  10  in the etch chamber  30  using an etchant  32 , in accordance with the given etching technique, thereby volatilizing the stack  20 , thereby forming the volatilized polymeric material  25 , and thereby depositing the volatilized polymeric material  25  on a wall  31  of the etch chamber  30 , wherein said step (d) may comprise measuring a vertical resist etch rate of the pilot wafer  11 , wherein the stack  20  may comprise: a gate oxide layer  21 ; a polysilicon layer  22 ; a dielectric layer  23  comprising at least one material selected from a group consisting essentially of a silicon oxynitride (SiON) or a silicon nitride (Si x N y , preferably silicon-rich silicon nitride, i.e., Si 3+n N 4 ); and a resist layer  24 , wherein the volatilized polymeric material  25  comprises: some material emanating from the resist layer  24 ; and some material emanating from at least one layer selected from a group consisting essentially of the dielectric layer  23 , the polysilicon layer  22 , and the gate oxide layer  21 , wherein the resist layer  24  may comprise a deep ultraviolet (DUV) photoresist, wherein the optimum etch chamber conditioning may comprise: a consistent resist etch rate; and a reliable gate critical dimension (CD), wherein the etch chamber  30  may comprise a decoupled plasma source (DPS) polysilicon etch chamber, wherein the at least one gate may have a length in the range of less than 75 nm, wherein the etchant  32  may comprise at least one material selected from a group consisting essentially of chlorine (Cl), hydrogen bromide (HBr), oxygen (O 2 ), carbon tetrafluoride (CF 4 ), helium (He), and argon (Ar), wherein the consistent vertical resist etch rate comprises a differential in a range of ±100 Å/min, and wherein the reliable gate CD variation comprises a differential in a range of ±10 nm. Also, in step (d), the vertical resist etch rate may be measured using the relationship discussed supra: R L =kR V , where R L  is the lateral erosion rate of the resist, R V  is the vertical resist etch rate, and k is a constant. 
     Information as herein shown and described in detail is fully capable of attaining the above-described object of the invention, the presently preferred embodiment of the invention, and is, thus, representative of the subject matter which is broadly contemplated by the present invention. The scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and is to be limited, accordingly, by nothing other than the appended claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described preferred embodiment and additional embodiments that are known to those of ordinary skill in the art are hereby expressly incorporated by reference and are intended to be encompassed by the present claims. 
     Moreover, no requirement exists for a device or method to address each and every problem sought to be resolved by the present invention, for such to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. However, it should be readily apparent to those of ordinary skill in the art that various changes and modifications in form, semiconductor material, and fabrication material detail may be made without departing from the spirit and scope of the inventions as set forth in the appended claims. No claim herein is to be construed under the provisions of 35 U.S.C. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for.”