Abstract:
The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a sense amplifier, and more particularly to a sense amplifier with a larger sensing voltage range. 
         [0003]    2. Description of the Related Art 
         [0004]    Non-volatile memory is the major memory product can conserve data without requiring power over a long period of time. In Magnetoresistive Ram (MRAM) and Resistive Ram (RRAM) for example, the logic state of data stored therein is determined by the resistance thereof. Because the resistance of logic state 1 and 0 are different, a sense amplifier is applied to sense the current of the memory cell by applying a fixed voltage thereon, thus, the accuracy of determining the logic state of the data stored in memory depends on the performance of the sense amplifier. Furthermore, the reading speed of memory is relevant to the performance of the sense amplifier. The shorter reading time is desirable and the reading time is also relevant to the current passing through the memory cell. 
         [0005]      FIG. 1  is a circuit diagram of a conventional sense amplifier. Control current source  11  is coupled to a high voltage source VDD and the drain and the gate of transistor N 11 . Resistor R is coupled to the source of transistor N 11  and a ground. Transistor P 11  has a source, a drain and a gate, wherein the source is coupled to the high voltage source VDD, the gate is coupled to the gate of transistor P 12  and the drain is coupled to the drain of transistor N 12 . Transistor P 12  has a source, a drain and a gate, wherein the source is coupled to the high voltage source VDD and the drain is coupled to the drain of transistor N 13 . The gate of transistor N 13  is coupled to the gate of transistor N 12 . Memory Cell  12  is coupled to the source of transistor N 12  and ground. Reference memory cell  13  is coupled to the source of transistor N 13  and ground. Memory cell  12  has an equivalent resistance R cell  and when a predetermined voltage is applied to the memory cell  12 , the current of the memory cell  12  is I cell . The reference memory cell  13  has two parallel resistors R max  and R min , and when the predetermined voltage is applied to the reference memory cell  13 , the current of R max  is I H  and the current of R min  is I L . Control current  11  outputs a control current I bias  which utilizes the different W/L values of transistors P 11  and P 12  (In  FIG. 1 , the W/L value of the transistor P 12  is twice the W/L value of the transistor P 11 ) to control the current flowing in through the transistor P 12  to be I ref  and the current flowing in through the transistor P 11  to be 
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         [0000]    Resistors R max  and R min  respectively have resistance when the data stored in memory cell  12  stores is logic 1 or logic 0, and when the predetermined voltage is applied to the memory cell  12 , the current passing through the memory cell  12  is respectively the current I H  or I L  In  FIG. 1 , the data stored in memory cell  12  is determined by applying the predetermined voltage to the memory cell  12  to make the memory cell current I cell  be I H  or I L , thus a differential voltage between node  14  and  15  is generated and a comparator  16  receives the differential voltage to determine what data is stored in the memory cell  12 . In  FIG. 1 , the reference current I ref  is the sum of I H  and I L , thus a half divider circuit is required and the layout area of the sense amplifier is increased. Moreover, the difference between the memory cell current I cell  and the reference current I ref  is not easily determined, thus, the speed and accuracy of the sense amplifier suffers. In  FIG. 1 , the current sensing range is 
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         [0000]    and if the difference between I H  and I L  is not easily determined, the sense amplifier of  FIG. 1  may be not sensitive enough and easily affected by noise. 
         [0006]      FIG. 2  is a circuit diagram of a conventional sense amplifier of U.S. Pat. No. 6,762,953. In  FIG. 2 , the outputs  22  and  23  of comparator  21  respectively receives current (I ref −I cell ) and current (I cell −I ref ), thus the current sensing range is larger than the current sensing range of the sense amplifier of  FIG. 1  (In  FIG. 1 , the current sensing range is I ref −I cell ). The reference current I ref  of  FIG. 2  is 
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         [0000]    however, thus a half divider circuit is required or the current mirror of the sense amplifier of  FIG. 2  is utilized to output half of the current I H  and I L . Although the current sensing range of  FIG. 2  is twice the current sensing range of the sense amplifier of  FIG. 1 , the sense amplifier of  FIG. 2  requires more transistors and greater layout area. Thus, a sense amplifier with a larger voltage sensing range and simple circuit design is desirable. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    The invention provides a sense amplifier coupled to a memory cell, comprising a first current mirror unit, a second current mirror unit, a first impedor, a second impedor and a third current mirror unit. The first current mirror unit coupled to a high voltage source outputs a first current via a first output and a second current via a second output based on a first reference current, wherein the first current is equal to the first reference current and the second current is two times the first current. The second current mirror unit coupled to the high voltage source outputs a reference current via a third output based on a second reference current, wherein the reference current is equal to the second reference current. The first impedor coupled to the second output and a low voltage source has a first impedance. The second impedor coupled to the third output and the low voltage source has the first impedance. The third current mirror unit coupled to the first output, the second output and the third output, takes the first current as a third reference current of the third current mirror to make the current passing through the first impedor equal to the first current and the current passing through the second impedor to be equal to the fourth current. 
         [0008]    The invention provides a sense amplifier coupled to a memory cell comprising a first impedor coupled to a low voltage source; a second impedor coupled to the low voltage source; a memory cell current source coupled to the low voltage source for providing a first current; a reference memory cell current source coupled to the low voltage source for providing a reference current; a first transistor having a first source, a first drain and a first gate, wherein the first source is coupled to the high voltage source, the first drain and the first gate are coupled to the memory cell current source; a second transistor having a second source, a second drain and a second gate, wherein the second source is coupled to the high voltage source, the second gate is coupled to the first gate and the second drain is coupled to the first impedor and the third current unit; a third transistor having a third source, a third drain and a third gate, wherein the third source is coupled to the high voltage source and the third gate is coupled to the first gate; a fourth transistor having a fourth source, a fourth drain and a fourth gate, wherein the fourth source is coupled to the high voltage source and the fourth drain is coupled to the second impedor; a fifth transistor having a fifth source, a fifth drain and a fifth gate, wherein the fifth source is coupled to the high voltage source, the fifth gate is coupled the fourth gate and the fifth drain and the fifth drain is coupled to the reference memory cell current source; a sixth transistor having a sixth source, a sixth drain and a sixth gate, wherein the sixth source is coupled to the low voltage source and the sixth drain is coupled to the first impedor and the second drain; a seventh transistor having a seventh source, a seventh drain and a seventh gate, wherein the seventh source is coupled to the low voltage source and the seventh drain is coupled to the third drain, the seventh gate and the sixth gate; a eighth transistor having a eighth source, a eighth drain and a eighth gate, wherein the eighth source is coupled to the low voltage source, the eighth gate is coupled to the seventh gate and the eighth drain is coupled to the second impedor and the fourth drain. 
         [0009]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0011]      FIG. 1  is a circuit diagram of a conventional sense amplifier. 
           [0012]      FIG. 2  is a circuit diagram of a sense amplifier disclosed in U.S. Pat. No. 6,762,953. 
           [0013]      FIG. 3  is a schematic diagram of an embodiment of a sense amplifier of the invention. 
           [0014]      FIG. 4  is a circuit diagram of an embodiment of the first current mirror  31  of  FIG. 3  of the invention. 
           [0015]      FIG. 5  is a circuit diagram of an embodiment of the second current mirror  32  of  FIG. 3  of the invention. 
           [0016]      FIG. 6  is a circuit diagram of an embodiment of the third current mirror  33  of  FIG. 3  of the invention. 
           [0017]      FIG. 7  is a circuit diagram of another embodiment of the sense amplifier of the invention. 
           [0018]      FIG. 8  is a circuit diagram of another embodiment of the sense amplifier of the invention. 
           [0019]      FIG. 9  is a circuit diagram of another embodiment of the sense amplifier of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0021]      FIG. 3  is a schematic diagram of an embodiment of a sense amplifier of the invention. The first current mirror unit  31  coupled to a high voltage source VDD has a first output  31   a  and a second output  31   b , and outputs a current I 1  via the second output  31   b  and a current I 2  via the first output  31   a  based on a current source (not shown in  FIG. 3 ), wherein I 2  is twice of I 1 . The second current mirror  32  coupled to the high voltage source has a output  32   a  and outputs a current I ref  via the output  32   a  based on a reference current source (not shown in  FIG. 3 ). The third current mirror  33  coupled to the first output  31   a , second output  31   b , output  32   a  and ground takes the current I 1  as the reference of the third current mirror  33 . The first impedor  34  coupled to the first output  31   a  and ground has impedance Z 1 . The second impedor  35  coupled to the output  32   a  and ground has impedance Z 2 . Since the third current mirror  33  takes the current I 1  as the reference current and the currents input to third current mirror  33  from the first output  31   a  and the output  32   a  are also the current I 1 , thus the current passing through the first impedor  34  is current I 1  and the current passing through the second impedor is (I ref −I 1 ). 
         [0022]    In this embodiment, the current I 1  is acquired by applying a predetermined voltage on a memory cell. When the data stored by the memory cell is logic 1, the current I 1  is I H  and when the data stored by the memory cell is logic 1, the current I 1  is I L . In this embodiment, the reference current I ref  is (I H +I L ). When the data stored by the memory cell is logic 1, the current I 1  is I H  and the current passing through the second impedor is I L , thus, the voltage of the node  37  is (I H ×Z 1 ) and the voltage of node  38  is (I L ×Z 2 ). The comparator  36  outputs a voltage difference (I H ×Z 1 −I L ×Z 2 ) based on the voltages of nodes  37  and  38 , and when the impedance Z 1  is equal to Z 2 , the voltage difference is (I H −I L )×Z 1 . 
         [0023]      FIG. 4  is a circuit diagram of an embodiment of the first current mirror  31  of  FIG. 3  of the invention. PMOS transistor T 1  has a first source, a first drain and a first gate, wherein the first source is coupled to the high voltage source VDD and the first gate and first drain are coupled to a memory cell source  41  for generating the memory cell current I 1 . PMOS transistor T 2  has a second source, a second drain and a second gate, wherein the second source is coupled to the high voltage source VDD, the second gate is coupled to the first gate and the second drain is coupled to the first output  31   a . PMOS transistor T 3  has a third source, a third drain and a third gate, wherein the third source is coupled to the high voltage source VDD, the third gate is coupled to the first gate and the third drain is coupled to the second output  31   b . In  FIG. 4 , the W/L of the transistor T 2  is twice the W/L of the transistor T 3 , thus the current passing through the transistor T 2  is twice the current passing through the transistor T 3 . 
         [0024]      FIG. 5  is a circuit diagram of an embodiment of the second current mirror  32  of  FIG. 3  of the invention. PMOS transistor T 4  has a fourth source, a fourth drain and a fourth gate, wherein the fourth source is coupled to the high voltage source VDD and the fourth drain is coupled to the output  32   a . PMOS transistor T 5  has a fifth source, a fifth drain and a fifth gate, wherein the fifth source is coupled to the high voltage source VDD, the fifth drain and fifth gate are coupled to the fourth gate and a reference memory cell current source  51  generating the reference current I ref . In  FIG. 5 , the W/L of the transistor T 4  is equal to the W/L of the transistor T 5 , thus, the output  32   a  outputs the reference current I ref . 
         [0025]      FIG. 6  is a circuit diagram of an embodiment of the third current mirror  33  of  FIG. 3  of the invention. NMOS transistor T 7  has a seventh source, a seventh drain and a seventh gate, wherein the seventh source and the seventh gate are coupled to the second output  31   b  for receiving the current I 1  and the seventh drain is coupled to ground. In the third current mirror  33 , the current passing through the transistor T 7 , I 1 , is taken as the reference current source of the third current mirror  33 . NMOS transistor T 6  has a sixth source, a sixth drain and a sixth gate, wherein the sixth source is coupled to ground, the sixth drain is coupled to the first output  31   a  and the sixth gate is coupled to the seventh gate. NMOS transistor T 8  has a eighth source, a eighth drain and a eighth gate, wherein the eighth drain is coupled to  32   a , the eighth gate is coupled to the seventh gate and the eighth source is coupled to ground. In  FIG. 6 , the W/L values of transistors T 6 , T 7  and T 8  are the same, thus, the current passing through the first impedor  34  is I 1  and the current passing through the second impedor, I 4 , is (I ref −I 1 ). 
         [0026]      FIG. 7  is a circuit diagram of another embodiment of the sense amplifier of the invention. The first source/drains of transistors T 71 , T 72 , T 73 , T 74  and T 75  are coupled to a high voltage source VDD. The gates of transistor T 71  and T 72  are coupled to the gate of transistor T 73 . The gate and the second source/drain of transistor T 71  are coupled to memory cell current source  71  generating the memory cell current I cell  by applying a predetermined voltage on a memory cell. When the data stored in the memory cell is logic 1, the current of the memory, by applying a predetermined voltage, is I H  and when the data stored in the memory cell is logic 0, the current of the memory, by applying a predetermined voltage, is I L . The second source/drain of transistor T 72  is coupled to the first source/drain of transistor T 76  and one node of first impedor  72 , wherein the first impedor  72  has impedance Z load . In  FIG. 7 , the W/L of transistor T 72  is twice the W/L of transistor T 73 , thus, the current passing through the transistor T 72  is twice the current passing transistor T 73 . The second source/drain of transistor T 73  is coupled to the first source drain and the gate of transistor T 77 . The gate of transistor T 74  is coupled to the gate and the second source/drain of transistor T 75 . The second source/drain of transistor T 74  is coupled to the first source/drain of transistor T 78  and one node of the second impedor, wherein the second impedor  73  has impedance Z load . The second source/drain of transistor T 75  is coupled to a reference current source  74  generating a reference current I ref  by applying the predetermined voltage on a reference memory cell. In  FIG. 7 , the reference current I ref  is the sum of I H  and I L . The second source/drain of transistors T 76 , T 77  and T 78  are connected to ground. 
         [0027]    When the data stored in the memory cell is logic 1, the current of the memory cell is I H  (I cell =I H ) A current mirror comprising transistors T 76 , T 77  and T 78  takes the current I H  passing through the transistor T 77  as the reference current, thus, the current passing through the transistor T 76  and the first impedor  72  is I H . Transistors T 74  and T 75  forms a current mirror, thus, the current passing through the transistor T 74  is the reference current I ref . The current I ref  is input to transistor T 78  and the second impedor  73 , and the current passing through the transistor T 78  is I H , thus, the current passing through the second impedor  73  is I L . Comparator  75  is coupled to the first impedor  72  and the second impedor  73  and outputs a voltage V out  based on the voltages V o  and V ob . In the present embodiment, the voltage V o  is (I H ×Z load ) and the voltage V ob  is (I L ×Z load ), thus, when the data stored in memory cell is logic 1, the sensing voltage range, V out , is (I H −I L )×Z load . 
         [0028]    When the data stored in the memory cell is logic 0, the current of the memory cell is I L  (I cell =I L ) A current mirror comprising transistors T 76 , T 77  and T 78  takes the current I L  passing through the transistor T 77  as the reference current, thus, the current passing through the transistor T 76  and the first impedor  72  is I L . Transistors T 74  and T 75  form a current mirror, thus, the current passing through the transistor T 74  is the reference current I ref . The current I ref  is input to transistor T 78  and the second impedor  73 , and the current passing through the transistor T 78  is I L , thus, the current passing through the second impedor  73  is I H . Comparator  75  is coupled to the first impedor  72  and the second impedor  73  and outputs a voltage V out  based on the voltages V o  and V ob . In the present embodiment, the voltage V o  is (I L ×Z load ) and the voltage V ob  is (I H ×Z load ), thus, when the data stored in memory cell is logic 1, the sensing voltage range, V out , is (I L −I H )×Z load . Compared with the sense amplifiers of  FIG. 1  and  FIG. 2 , the sense amplifier of  FIG. 7  increases the sensing voltage range and reduces the layout area. 
         [0029]      FIG. 8  is a circuit diagram of another embodiment of the sense amplifier of the invention. The first source/drains of transistors T 86 , T 87  and T 88  are coupled to a high voltage source VDD, and the gate of transistor T 86  is coupled to the gates of transistors T 87  and T 88 . The second source/drain of the transistor T 86  is coupled to the first source/drain of the transistor T 83 . The second source/drain of transistor T 83  is coupled to the first source/drain of transistor T 81  and the second impedor  83 . Memory cell current source  81  coupled to the high voltage source VDD, the first source/drain and gate of transistor T 81  generates a memory cell current I cell  by applying a predetermined voltage on a memory cell. When the data stored in the memory cell is logic 1, the current of the memory, by applying a predetermined voltage, is I H  and when the data stored in the memory cell is logic 0, the current of the memory, by applying a predetermined voltage, is I L . Reference current source  84  coupled to the high voltage source VDD, the first source/drain and gate of transistor T 81  generates a reference current I ref  by applying a predetermined voltage on a reference memory cell and in this embodiment, the reference current I ref  is the sum of I H  and I L . The second source/drains of transistors T 81 , T 82 , T 83 , T 84  and T 85  are coupled to ground, the gate of transistor T 81  is coupled to the gates of transistor T 82  and T 83 , and the gate of transistor T 84  is coupled to the gate of transistor T 85 . In  FIG. 8 , the W/L of transistor T 82  is twice the W/L of transistor T 81 , thus, the current passing through the transistor T 82  is twice the current passing transistor T 81 . Furthermore, the first impedor  82  and second impedor  83  have impedance Z load . 
         [0030]    When the data stored in the memory cell is logic 1, the current of the memory cell is I H  (I cell =I H ). A current mirror comprising transistors T 86 , T 87  and T 88  takes the current I H  passing through the transistor T 87  as the reference current, thus, the current passing through the transistor T 86  and the first impedor  82  is I H . Transistors T 84  and T 85  form a current mirror, thus, the current passing through the transistor T 84  is the reference current I ref . The current I ref  is input to transistor T 88  and the second impedor  83 , and the current passing through the transistor T 88  is I H , thus, the current passing through the second impedor  83  is I L . Comparator  85  is coupled to the first impedor  82  and the second impedor  83  and outputs a voltage V out  based on the voltages V o  and V ob . In the present embodiment, the voltage V o  is (VDD−I H ×Z load ) and the voltage V ob  is (VDD−I L ×Z load ), thus, when the data stored in memory cell is logic 1, the sensing voltage range, V out , is (I H −I L )×Z load . 
         [0031]    When the data stored in the memory cell is logic 0, the current of the memory cell is I L  (I cell =I L ) A current mirror made of transistors T 86 , T 87  and T 88  takes the current I L  passing through the transistor T 87  as the reference current, thus, the current passing through the transistor T 86  and the first impedor  82  is I L . Transistors T 84  and T 85  form a current mirror, thus, the current passing through the transistor T 84  is the reference current I ref . The current I ref  is input to transistor T 88  and the second impedor  83 , and the current passing through the transistor T 88  is I L , thus, the current passing through the second impedor  83  is I H . Comparator  85  is coupled to the first impedor  82  and the second impedor  83  and outputs a voltage V out  based on the voltages V o  and V ob . In the present embodiment, the voltage V o  is (VDD−I L ×Z load ) and the voltage V ob  is (VDD−I H ×Z load ), thus, when the data stored in memory cell is logic 1, the sensing voltage range, V out , is (I L −I H )×Z load . Compared with the sense amplifiers of  FIG. 1  and  FIG. 2 , the sense amplifier of  FIG. 7  increases the sensing voltage range and reduces the layout area. 
         [0032]      FIG. 9  is a circuit diagram of another embodiment of the sense amplifier of the invention. The first source/drains of transistors T 91 , T 92 , T 93 , T 94  and T 95  are coupled to a high voltage source VDD, the gate of transistor T 91  is coupled to the gates of transistors T 92  and T 93 , and the gate of transistor T 94  is coupled to the gate of transistor T 95 . Memory cell current source  91  coupled to the second source/drain and gate of transistor T 91  generates a memory cell current I cell  by applying a predetermined voltage on a memory cell. When the data stored in the memory cell is logic 1, the current of the memory, by applying a predetermined voltage, is I H  and when the data stored in the memory cell is logic 0, the current of the memory, by applying a predetermined voltage, is I L . The second source/drain of transistor T 91  is coupled to the first impedor  92  and comparator  95 , and the second source/drain of transistor T 93  is coupled to the first source/drain of transistor T 96  and the gates of transistors T 96  and T 98 . Reference current source  94  is coupled to the second source/drain and gate of transistor T 95 . The second source/drain of transistor T 94  is coupled to the first source/drain of transistor T 98 , the second impedor  93  and the comparator  95 . 
         [0033]    When the data stored in the memory cell is logic 1, the current of the memory cell is I H  (I cell =I H ). A current mirror made of transistors T 91 , T 92  and T 93  takes the current I H  passing through the transistor T 91  as the reference current, thus, the current passing through the transistor T 96  and the first impedor  92  is I H . Transistors T 94  and T 95  forms a current mirror, thus, the current passing through the transistor T 94  is the reference current I ref . The current I ref  is input to transistor T 98  and the second impedor  93 , and the current passing through the transistor T 98  is I H , thus, the current passing through the second impedor  93  is I L . Comparator  95  is coupled to the first impedor  92  and the second impedor  93  and outputs a voltage V out  based on the voltages V o  and V ob . In the present embodiment, the voltage V o  is (I L ×Z load ) and the voltage V ob  is (I H ×Z load ), thus, when the data stored in memory cell is logic 1, the sensing voltage range, V out , is (I H −I L )×Z load . 
         [0034]    When the data stored in the memory cell is logic 0, the current of the memory cell is I L  (I cell =I L ). A current mirror comprising transistors T 91 , T 92  and T 93  takes the current I L  passing through the transistor T 91  as the reference current, thus, the current passing through the transistor T 96  and the first impedor  92  is I L  Transistors T 94  and T 95  forms a current mirror, thus, the current passing through the transistor T 94  is the reference current I ref . The current I ref  is input to transistor T 98  and the second impedor  93  and the current passing through the transistor T 98  is I L , thus, the current passing through the second impedor  93  is I H  Comparator  95  is coupled to the first impedor  92  and the second impedor  93  and outputs a voltage V out  based on the voltages V o  and V ob . In the present embodiment, the voltage V o  is (I H ×Z load ) and the voltage V ob  is (I L ×Z load ), thus, when the data stored in the memory cell is logic 1, the sensing voltage range, V out , is (I L −I H )×Z load . Compared with the sense amplifiers of  FIG. 1  and  FIG. 2 , the sense amplifier of  FIG. 9  increases the sensing voltage range and reduces the layout area. 
         [0035]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.