Abstract:
A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to the field of electronic devices, and, more particularly, to programmable logic devices (PLDs) and methods/devices for testing the same.  
         BACKGROUND OF THE INVENTION  
         [0002]    PLDs are general-purpose logic devices which can be configured for various operations. Current developments in PLDs are making it possible to enhance the flexibility and complexity of these devices. Many PLDs provide complete system capabilities, including on-chip memories and a large variety and number of logic elements, that are electrically programmed for providing the desired operation by using configuration memory cells. To ensure correct implementation of functionality, it is desirable to have the ability to test the configured configuration memory cells for correctness of programming.  
           [0003]    U.S. Pat. No. 6,237,124 describes a method for testing the configuration memory by using cyclical redundancy checking (CRC). In this technique the CRC mechanism is used to check for a single event upset (SEU) in the configuration process of the static random access memory (SRAM) of a field programmable gate array (FPGA). In one particular SRAM-based FPGA architecture described in the patent, an erasable programmable read only memory (EPROM) resides on a printed circuit board near the FPGA. This EPROM stores the configuration data for programming the configuration SRAM for the FPGA core. An EPROM controller on the FPGA directs a data stream from the EPROM into the FPGA.  
           [0004]    The EPROM controller serializes the data stream from the EPROM into a data stream one bit wide. This data stream is synchronized to an internal clock and provides data to various portions of the FPGA architecture including control logic, row and column counters, a CRC circuit, and the configuration SRAM for the FPGA core. The CRC circuit tests the data stream from the EPROM to verify that it is correct. Also, the CRC circuit can test the data in the configuration SRAM after loading. A multiplexer selects whether the data to be checked by the CRC circuit is the input data stream or the data in the configuration SRAM. When incorrect configuration data is detected in the configuration SRAM of the FPGA core, the CRC circuit can signal the EPROM controller that an error has occurred. The EPROM controller can use this information to output an error signal from the FPGA and/or initiate a reload from the EPROM.  
           [0005]    The configuration circuitry described above may be adequate for configuring a conventional memory array, but it includes no mechanism by which the full configuration process could be tested. For example, the CRC bits or the frame check sequence bits loaded after every frame of data make it possible to check for an error that may occur in loading the data frames in the internal shift register. Yet, the data lines themselves could be faulty with bits stuck at logic 1 or stuck at logic 0. In such a case, the data may not have correctly reached its destination, and to verify whether it was correct or not would require tracing back every bit of stored data.  
         SUMMARY OF THE INVENTION  
         [0006]    An object of the invention is to provide bit-by-bit tracking of the data latched in the configurable data latch array.  
           [0007]    Another object of the invention is to enable testing of a PLD configuration memory in a relatively transparent manner.  
           [0008]    To achieve these and other objects, the present invention provides a PLD having the ability to test a configuration memory thereof either independently or during configuration. In particular, the PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage circuit for storing configuration data required to be stored in the selected column or row (or test data for testing the selected column or row). The PLD may further include an output data storage circuit for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.  
           [0009]    The test logic may deselect the inputs and outputs of the storage cells in the memory array from the columns or rows of the memory array during testing. The correct operation of the data lines of the memory array is verified by applying various test patterns including, “all 0”, “all 1”, “walking 0” and “walking 1” test patterns, and reading back and verifying the output from the memory array. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    Various objects and advantages of the invention will become more apparent in reference to the following description and the accompanying drawings, in which:  
         [0011]    [0011]FIG. 1A is schematic block diagram of a prior art configurable memory latch array;  
         [0012]    [0012]FIG. 1B is a schematic diagram of a prior art configuration memory cell;  
         [0013]    [0013]FIG. 2A is a schematic block diagram illustrating a PLD configuration memory in accordance with one embodiment of the present invention;  
         [0014]    [0014]FIG. 2B is a schematic block diagram of a PLD configuration memory in accordance with a second embodiment of the present invention;  
         [0015]    [0015]FIG. 2C is a circuit diagram illustrating a configuration memory cell according to the present invention; and  
         [0016]    [0016]FIG. 2D is a schematic diagram of control circuitry for selecting between the test and configuration modes in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]    For clarity of illustration and explanation, the present invention will be described with reference to an 8×8 configuration memory cell array for configuration of an array of logic modules and interconnect architecture. Yet, embodiments with other array structures are also contemplated by the present invention, as will be appreciated by those of skill in the art. The following description of the present invention is only illustrative and not in any way limiting.  
         [0018]    The configurable memory cells of a PLD are typically arranged in an array and loaded using serial bit streams of configuration data. Referring initially to FIG. 1A, a configuration memory array  100  according to the prior art is illustratively shown. The configuration memory array  100  includes memory cells M x,y , where x and y correspond to the row and column location, respectively, of each configuration memory cell.  
         [0019]    The configuration of data into the configuration memory array is achieved by shifting the bit stream of configuration data through a vertical shift register  101  controlled by a clocking mechanism  200  until a frame of data (8 bits wide in this example) has been shifted into bit register  101 . This frame of data is then released in parallel through horizontal data lines  100   7  to  100   0  into a column of configuration memory cells enabled by horizontal shift register  102 . The column is addressed by shifting a high/low bit to one of the selected vertical lines  100   8 - 100   15  via the flip-flop array  102  using one shift per frame. The loading of data is therefore performed in a serial in, parallel out (SIPO) mode. When the high/low bit shifts out to the extreme right, it causes the DONE signal (not shown) of the configuration logic to go high, which provides an indication that the configuration is complete.  
         [0020]    Turning now to FIG. 1B, the circuit diagram of a single memory cell  103  is now described. The memory cell M 0,0  includes a latch  103 - 2  formed by two back-to-back inverters  103 - 3  and  103 - 4  that stores a bit value passed by the pass transistor  103 - 1 . During configuration when the high bit is shifted to line  1035  the pass transistor  103 - 1  gets enabled and the information present at the line  103 - 6  is configured in the data latch. In the configuration block, the lines  103 - 5  and  103 - 6  are the outputs of shift registers  102  and registers  101  of FIG. 1A, respectively. This arrangement does not allow for the testing of the configured data latches.  
         [0021]    A simplified diagram of the configuration process according to the present invention is illustrated in FIG. 2A. The invention incorporates a mechanism for enabling the test of configuration data at any point in time during or after configuration without the need of additional circuitry. The memory includes a configuration memory array  106 , a vertical shift in register  104 , a vertical shift out register  107 , a horizontal shift register  105 , and a configuration logic block  201 . The vertical registers  104  and  107  are connected to the rows of the configurable cells via horizontal lines  106   0 - 106   7 , and the horizontal shift register  105  outputs are cascaded to the memory cell by vertical lines  106   8 - 106   15 . The horizontal shift register  105  is provided with two extra bit frames, which are used as dummy bits.  
         [0022]    The configuration logic block  201  generally includes input pins CONFIG, data bus DIN (0:7) and the clock signal CLK. The block  201  also internally includes various registers etc. During configuration, the data frame is loaded through data bus DIN into the configuration logic  201  and is latched into the various shift registers of the configuration logic. One of the shift registers of the configuration logic  201  then transfers the data frames to the vertical shift in register  104  under the control of clock signal VSR_CLK for the register  104  which is generated by configuration logic  201 . The data frame is shifted serially into the bit positions of vertical shift in register  104  using this clocking mechanism. Output bits of vertical shift in register  104  are connected to data lines  106   0  to  106   7 .  
         [0023]    Once the full data frame has been loaded into the register  104  and the CRC circuit flags no error, clock HSR_CLK is generated by configuration logic  201  for enabling the horizontal shift register  105  to address a particular column of the configuration memory array by shifting a high bit, one shift per frame, of data into it. Depending on which of the output bits of the horizontal shift register  105  is high, one of the data lines  106   8  to  106   15  connected to that bit position is enabled. This allows all the configuration memory cells present in that column to latch the data frame bits stored in the vertical shift in register  104 .  
         [0024]    Bits  105   0  and  105   1  of the horizontal shift register  105  are dummy bits and are not used to address any column. This is done because the first two frames that are loaded after the preamble are test frames to test the data lines for faults. These frames are not to be latched in the configuration memory cells, and to prevent this from happening bits  105   0  and  105   1  are prevented from reaching any of the columns when the horizontal shift register  105  starts functioning soon after the loading of the preamble. This is achieved by enabling the storing of data into configuration memory cells only when bit  105   2  goes high.  
         [0025]    To compensate for these additional frames the last frame address that is provided to the configuration logic  201  (to mark the end of the configuration process) is always greater by two than the actual address. The signal HSR_CLK also controls the parallel loading of data into the vertical shift out register  107 . Whenever the HSR_CLK goes high, the contents of vertical shift in register  104  get loaded in parallel to the vertical shift out register  107  through data lines  106   0  to  106   7 . The signal VSR_CLK is also directly connected to the vertical shift out register  107  and enables the serial shifting out of the previous data from the SOUT pin when the next data frame starts loading into the register  104 .  
         [0026]    Another embodiment of the invention is illustratively shown in FIG. 2B. This embodiment provides an extra control cell  108  and a TEST signal. All the cells of the control unit  108  are connected to lines  106   8 - 106   15 . The two outputs of the control cell E i  and T i  are connected across the entire configuration memory array. The output E i  enables a particular column for data entry, whereas the output T i  enables testing of a particular column of the data array.  
         [0027]    Turning now to FIG. 2C, the internal circuit of a single configuration memory cell structure M 0,0  of FIG. 2B is illustratively shown. Instead of directly attaching the data latch with the horizontal line  106   0 , it is routed through pass transistor  109 - 5  and a tri-state inverter  109 - 2 . This leaves the line  106   0  free both during configuration and testing. The signal E 0  connects to the gate terminal of pass transistor  109 - 5 , while the signal T 0  connects to the enable line of tri-state inverter  109 - 2 . The configuration memory cell  109 - 1  is formed by two back-to-back inverters  109 - 3  and  109 - 4 .  
         [0028]    A circuit diagram for one of the cells  108   0  of the control circuitry  108  is illustratively shown in FIG. 2D. The control circuitry includes two NAND gates  110 - 1  and  110 - 2 . First input terminals of  110 - 1  and  110 - 2  are connected to bit  105   2  via line  106   8 . The TEST signal coming from the configuration logic  201  is the second input terminal of the NAND gate  110 - 2 , and the inverted TEST signal becomes the second input terminal of  110 - 1 .  
         [0029]    To start the configuration, the CONFIG signal goes high for one clock cycle. This generates an internal RESET signal (not shown) that resets the registers of configuration logic  201 . The signal TEST is at logic 0 at the time of configuration. This disables all the tri-state inverters because the output Ti gets tied to 0. Before loading the actual data frames, some test bytes are loaded through the data input bus DIN. The first test byte is all 0&#39;s. Configuration logic  201  generates the VSR_CLK and the data bits start shifting serially into the vertical shift in register  104 .  
         [0030]    When the last bit of the frame Din 7  gets transferred into bit position  1047 , the signal VSR_CLK is disabled and HSR_CLK is generated causing the parallel loading of data bits  104   7  to  104   0  into bit positions  107   7  to  107   0  via data lines  106   7  to  106   0 . The stored data frame of the vertical shift out register  107  is then shifted out serially from the pin SOUT. If the data bits received from the vertical shift out register  107  include any bit as a logic  1  it would indicate that the data line connected to that particular bit position is stuck at logic 1 (because the data frame provided was all logic 0&#39;s). A test byte of all logic 1&#39;s may be used in a similar fashion for detecting “stuck at logic 0” faults. This completes the first phase of testing, which verifies that the data lines are working correctly.  
         [0031]    The configuration of the data then begins, and when the high bit is shifted into the horizontal shift register  105 , bit  105   2 , the resulting high signal at the gate of pass transistor  109 - 5  on line  15 , allows the configuration bit stored in  104  to enter the latch via data lines  106   0 , etc. In this mode, the signal TEST remains low resulting in output T i  remaining low, which causes the tri-state inverter  109 - 2  to be in the high impedance state.  
         [0032]    The output on line  15  depends on the value stored at the corresponding bit position of horizontal shift register  105 . If the bit is high, the corresponding signal line  106  becomes high, thus giving a high signal at output  15 . The gate of the pass transistor  109 - 5  is connected to line  15  and therefore,  109 - 5  turns on, allowing the value stored in the corresponding bit of the vertical shift in register  104  to get latched into  109 - 1  via data line  106   0 , etc. During configuration when the data frames are latched to an assigned data latch array, testing of the configured data is simultaneously carried-out as follows.  
         [0033]    After the first frame has been loaded into the vertical shift in register  104 , the clock signal HSR_CLK for the horizontal shift register  105  is generated. The decoding system of the configuration logic  201  causes bit  105   2  of the horizontal shift register  105  to go high, which enables the first column of the memory array  106  through the line  15 . The latches in that column as well as the vertical shift out register  107  store the bit values present in vertical shift in register bits  104   0  to  104   7 . The serial loading of the second data frame into the vertical shift in register  104  and the serial shifting out of the first frame from the vertical shift out register  107  occur simultaneously.  
         [0034]    This enables simultaneous verification of each frame of data. This process continues until all the frames have been loaded. This approach confirms that the configuration logic  201  as well as the vertical shift in register  104  are functionally correct. This is because there is always a possibility that the CRC method does not show any error in the configuration process, but the correct data frame may not reach the vertical shift in register  104 , or the vertical shift in register  104  may not be able to transfer data to the correct destination.  
         [0035]    After completion of the configuration and simultaneous testing, the latches or column of latches may be further checked individually by raising the TEST signal high. This is the actual testing mode in which each latched value is read back. Setting the signal TEST high causes signal  16  to go high, thus enabling the tri-state inverter  109 - 2 , and the bit stored in the latch  109 - 1  is read back by the vertical shift out register  107 . Also, since the signal TEST remains high, signal  15  stays low. The pass transistor  109 - 5  thus remains off, and the value stored in the latch  109 - 1  cannot be overwritten. The signal value of the signal  16  goes high, and the latched value can be read from the output of  109 - 2 .  
         [0036]    Configuration block  201  remains functional in this mode too because clock signals VSR_CLK and HSR_CLK are generated in the same way as in the configuration mode. The clock signal VSR_CLK and HSR_CLK enable the vertical shift out register  107  as well as the tri-state inverters synchronously activated for the testing purpose. The configuration block functions in the usual manner, and bit streams of logic O&#39;s can be sent through the input bus DIN. In fact, whatever data is sent through the input bus does not affect the bit values already stored. This is because the input side of each memory cell M x,y  remains off since the signal E i  remains tied to 0 due to the high value of the signal TEST.  
         [0037]    The horizontal shift register  105  enables the columns of the memory array one by one for reading through data lines T i . The selected column transfers its latched values through the tri-state inverters to data lines  106   0  to  106   7 , which then get loaded in parallel to the vertical shift out register  107 . The serial shifting out of the bit stream from vertical shift out register  107  provides the values stored in the individual latches of the particular column.  
         [0038]    In accordance with another embodiment of the present invention (not shown), another shift register may be used at the other end of the memory array, parallel to the horizontal shift register  105 . This is useful for testing the data lines running vertically upwards from horizontal shift register  105  even before the actual configuration process starts. This register may also be used at the time of configuration to shift out the values stored in the horizontal shift register  105 , which will indirectly test the address decoding system of the configuration logic. The present invention thus provides an efficient scheme for testing the configuration process by incorporating only slight modifications in the available configuration resources.  
         [0039]    It will be apparent to those skilled in the art that the foregoing is merely illustrative and not intended to be exhaustive or limiting, having been presented by way of example only and that various modifications can be made within the scope of the invention. For example, the configuration memory array could be of any desired size. Further, the vertical shift in register and vertical shift out register could be connected to rows instead of columns of the memory array, while the horizontal shift register is connected to columns instead of rows.  
         [0040]    Accordingly, the present invention is not to be considered limited to the specific examples chosen for purposes of explanation, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention as set forth in the claims.