Abstract:
A thermal-type flow meter for representing a flow rate of air by the frequency of a periodic signal, wherein abnormalities in the waveform of an output signal due to frequency variation is prevented while high-frequency noise is suppressed. The thermal-type flow meter pertaining to the present invention is provided with a plurality of switching elements connected in parallel, and varies a delay width between the switching elements in accordance with variation of the frequency of a periodic signal for representing a flow rate.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a thermal-type flow meter. 
       BACKGROUND ART 
       [0002]    A thermal-type flow meter is a sensor to measure a flow rate of flown air on the basis of a current necessary for returning a temperature of a heating wire which is changed by the ambient flowing air. The measured flow rate can be represented by aperiodic signal having a frequency corresponding to the flow rate for example. The periodic signal is input to an open drain circuit (or an open collector circuit; the same shall apply hereinafter) for example, and a frequency of a signal output from the open drain circuit is detected by a frequency measurement circuit, so that the flow rate can be detected. 
         [0003]    The open drain circuit turns on/off a switching element to output an output signal of a high/low level. The output signal corresponding to the flow rate represented by the frequency of the periodic signal can be output by turning on/off the switching element according to the frequency of the periodic signal. 
         [0004]    The output signal becomes a rectangular wave due to the configuration of the open drain circuit. Therefore, high-frequency noises are generated. As a means for relieving the high-frequency noises, it is considered that a plurality of switching elements are connected in parallel at multiple stages, and shifts timing for switching the switching elements so as to output the step-shape output signal. PTL 1 describes a specific example of the open drain circuit in which the switching timings of the respective switching elements are different. 
       CITATION LIST 
     Patent Literature 
       [0005]    PTL 1: JP 01-228214 A 
       SUMMARY OF INVENTION 
     Technical Problem 
       [0006]    A frequency of a periodic signal input to an open drain circuit changes according to a measured flow rate. Therefore, the ON/OFF period of the switching element of the open drain circuit is shortened when the frequency of the periodic signal is increased. 
         [0007]    In the technology disclosed in PTL 1, a delay time interval between the switching elements is constant. Therefore, when the frequency of the periodic signal is increased to some degree or more, the switching element at the first stage makes an operation of the next period before the switching element at the final stage operates. Therefore, there is a possibility that the output signal may be not changed from the high level to the low level in one period. In this case, it is difficult to detect a flow rate represented by the frequency of the periodic signal with accuracy. 
         [0008]    The invention has been made in view of the problems described above, and an object thereof is to provide a thermal-type flow meter which measures a flow rate of air using the frequency of the periodic signal, in which a waveform abnormality of the output signal caused by a frequency change can be avoided while suppressing high-frequency noises. 
       Solution to Problem 
       [0009]    A thermal-type flow meter according to the invention includes a plurality of switching elements connected in parallel, and changes a delay duration between the switching elements according to a frequency change of the periodic signal representing a flow rate. 
       Advantageous Effects of Invention 
       [0010]    According to a thermal-type flow meter of the invention, it is possible to suppress that a peak value and a frequency of an output signal become abnormal values even when the frequency of the periodic signal changes while suppressing high-frequency noises caused from a plurality of switching elements connected in parallel. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]      FIG. 1  is a diagram illustrating an exemplary waveform of an output signal in a case where an electromagnetic wave noise is suppressed using a low-pass filter. 
           [0012]      FIG. 2  is a diagram illustrating an exemplary waveform of an output signal in a case where a current flowing to an open drain circuit is limited using a current mirror circuit. 
           [0013]      FIG. 3  is a circuit diagram illustrating an example of the open drain circuit in which switching is delayed using a delay circuit. 
           [0014]      FIG. 4  is a waveform diagram of the output signal in a case where a signal pulse of a period T 1  is input to the open drain circuit of  FIG. 3 . 
           [0015]      FIG. 5  is a waveform diagram of the output signal in a case where the signal pulse of a period T 2  shorter than T 1  is input to the open drain circuit of  FIG. 3 . 
           [0016]      FIG. 6  is a waveform diagram of the output signal in a case where the signal pulse of a period T 3  (&lt;4 τ) is input to the open drain circuit of  FIG. 3 . 
           [0017]      FIG. 7  is a circuit diagram of an open drain circuit  1  according to a first 
           [0018]      FIG. 8  is a waveform diagram of an input signal Vi. 
           [0019]      FIG. 9  is a diagram illustrating an exemplary configuration of a frequency measurement circuit  2  which is connected to the open drain circuit  1 . 
           [0020]      FIG. 10  is a waveform diagram of an output voltage Vfo when the input signal Vi of a triangular wave is input to the open drain circuit  1  in a circuit configuration of  FIG. 9 . 
           [0021]      FIG. 11  is a diagram illustrating a waveform of the output voltage Vfo in a case where a period of the input signal Vi is changed in the circuit configuration of  FIG. 9 . 
           [0022]      FIG. 12  is a diagram illustrating an exemplary waveform in which an output signal Vfo does not intersect with a comparison voltage Vc. 
           [0023]      FIG. 13  is a circuit diagram of the open drain circuit  1  according to a second embodiment. 
           [0024]      FIG. 14  is a diagram illustrating a circuit configuration from which a current limit resistor connected to a drain terminal of a transistor Tr 3  is removed to be short-circuited to an output terminal Fo in the conventional open drain circuit illustrated in  FIG. 3 . 
           [0025]      FIG. 15  is a diagram illustrating a waveform of the output signal of the open drain circuit of  FIG. 14 . 
           [0026]      FIG. 16  is a diagram illustrating a waveform of the output signal of the open drain circuit  1  according to a third embodiment. 
           [0027]      FIG. 17  is a diagram illustrating a modification of the open drain circuit  1  according to the third embodiment. 
           [0028]      FIG. 18  is a diagram illustrating an exemplary waveform of the output signal in the circuit configuration of  FIG. 17 . 
           [0029]      FIG. 19  is a diagram illustrating a configuration of a thermal-type flow meter  100  according to a fourth embodiment. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
     Problems of Related Art 
       [0030]    In the following, problems in the related art will be first described in detail in order to help with understanding on the present invention, and then embodiments of the invention will be described. 
         [0031]    Countermeasures for radiation electromagnetic waves generated when an output signal indicating information using a frequency is output from an open collector circuit are as follows. 
         [0032]      FIG. 1  is an exemplary waveform of the output signal in a case where an electromagnetic wave noise is suppressed using a low-pass filter, The low-pass filter configured by a combination of an inductor, a capacitor, and a resistor is disposed in an output terminal of an open drain circuit. In this case, as illustrated in  FIG. 1 , a voltage is steeply changed at the beginning when the output signal falls down and rises up, and a high-frequency component is contained in the output signal. The waveform when the voltage V falls down is expressed by the following Equation 1, and the waveform when the voltage V rises up is expressed by the following Equation 2. Herein, A is a peak value, β is a time constant, α is a constant, and t is time, When the voltage starts to rise up or fall down, is set to 0. 
         [0000]        V=A *Exp(−β* t )+α  Equation 1
 
         [0000]        V=A *(1−Exp(−β* t ))+α  Equation 2
 
         [0033]      FIG. 2  is a diagram illustrating an exemplary waveform of the output signal in a case where a current flowing to the open drain circuit is limited using a current mirror circuit. In this case, the current is not limited when the voltage falls down as illustrated in  FIG. 2 . 
         [0034]    An ideal waveform as a periodic signal is a sinusoidal waveform. However, in a case where the frequency is output using the open drain circuit, a transistor of the output stage is turned ON/OFF, and the voltage of the output signal is received from an external voltage source. Therefore, a signal waveform output by the open drain circuit becomes a rectangular waveform as a principle. When a rectangular wave function X of a frequency f is subjected to Fourier expansion, the following Equation 3 is obtained. Herein, ω is set to 2πf. in other words, the rectangular wave is evaluated as a signal in which a sinusoidal wave having a frequency higher than necessary is mixed. 
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         [0035]    When the voltage is a rectangular wave, the current is also a rectangular wave. Therefore, Equation 3 represents a waveform of the current flowing into the output terminal of the open drain circuit. When the current I flows, a magnetic field H is generated around the current I as expressed in Equation 4. Herein, r represents a distance from the current. 
         [0000]        H=I /(2*π* r )  Equation 4
 
         [0036]    A relation between the magnetic field H and the electric field E is expressed by the following Equation 5 using Maxwell&#39;s equations. As a temporal variation of the magnetic field H becomes large, a stronger electric field E is generated. Herein, μ is magnetic permeability, and t is time. Therefore, when a rectangular current flows, a high-frequency electromagnetic wave is radiated even though the frequency is low, which affects a noise influence on the surrounding machines. 
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         [0037]    It can be seen that a small temporal variation of the current flowing to the output terminal of the open drain circuit is an effective countermeasure against the high-frequency noise from Equations 4 and 5. As a method of realizing the countermeasure, there is considered a method in which a plurality of open drain transistors are connected to the output terminal in parallel, a time difference is put at a switching timing of conducting the transistor, and the current flowing to the output terminal is switched in plural times. 
         [0038]    However, in a case where a sensor outputs a physical quantity according to a frequency of the periodic signal, an output frequency is not constant but temporally varies. Therefore, when the output frequency becomes high, the output waveform becomes abnormal. Such an abnormal waveform will be described below. 
         [0039]      FIG. 3  is a circuit diagram illustrating an example of the open drain circuit in which the time difference is put at the switching timing using a delay circuit as disclosed in PTL 1. In  FIG. 3 , three open drain transistors, each of which has a drain terminal connected with a current limit resistor, are connected to the output terminal in parallel. Delay circuits D having a delay time τ are disposed between the gates of three open drain transistors Tr 1 , Tr 2 , and Tr 3 , The source terminals of the open drain transistors Tr 1  to Tr 3  are earthed to the ground. The drain terminals of the open drain transistors Tr 1  to Tr 3  are connected to an output terminal Fo. A pull-up resistor Rp is connected to the drain terminal, the output signal is pulled up by a voltage Vp. 
         [0040]    The open drain transistors Tr 1  to Tr 3  are controlled by inputting the periodic signal (signal pulse) to the gate terminal. When the signal pulse to make the open drain transistors Tr 1  to Tr 3  conductive is input, the transistor Tri first comes to be conductive, the transistor Tr 2  conies to be conductive at a timing delay by τ, and then the transistor Tr 3  comes to be conductive at a timing further delayed by τ. When the signal pulse to make the open drain transistors Tr 1  to Tr 3  not conductive is input, the transistor Tr 1  first conies to be non-conductive, the transistor Tr 2  comes to be non-conductive at a timing delayed by τ and then the transistor Tr 3  comes to be non-conductive at a timing further delayed by τ. 
         [0041]      FIG. 4  is a waveform diagram of the output signal in a case where the signal pulse having a period T 1  is input to the open drain circuit of  FIG. 3 , When the open drain transistors Tr 1  to Tr 3  sequentially come to be conductive to cause the current to flow, an output voltage Vfo falls down. When the open drain transistors sequentially come to be non-conductive, the output voltage Vfo rises up. A period of the output signal is the same period T 1  as that of the signal pulse. 
         [0042]      FIG. 5  is a waveform diagram of the output signal in a case where the signal pulse having a period τ 2  shorter than TI is input to the open drain circuit of  FIG. 3 . Comparing to  FIG. 4 , the switching time interval is the same between the conduction and the non-conduction of each transistor since there is no change in the delay time τ. However, the waveform period becomes shorter than that in  FIG. 4 . 
         [0043]      FIG. 6  is a waveform diagram of the output signal in a case where the signal pulse having a period T 3  (&lt;4τ) is input to the open drain circuit of  FIG. 3 . In  FIG. 6 , the transistor Tr 1  performs the next switching operation before the transistor Tr 3  operates at 2τ after the transistor Tr 1  is switched. Therefore, since the open drain transistors Tr 1  to Tr 3  all are not in the same operation state (conduction or non-conduction), the signal waveform is not possible to reach an upper limit (Hi level) and a lower limit (Low level). In other words, the peak value of the output signal becomes small, and the period becomes shorter than T 3  and does not become constant. 
         [0044]    The invention relates to an open drain circuit in which a plurality of switching elements are connected to the output terminal in parallel to provide a time difference in operation timing of the respective switching elements so as to suppress a steep change in the waveform, and an object thereof is to avoid an abnormal waveform of the output signal as illustrated in  FIG. 6 . 
       First Embodiment 
       [0045]      FIG. 7  is a circuit diagram of an open drain circuit  1  according to a first embodiment of the invention. In  FIG. 7 , three open drain transistors Tr 1  to Tr 3  each are connected to the output terminal Fo through current limit resistors Rd 1  to Rd 3 . In an input terminal Vi, an input signal Vi is input to drive the transistors Tr 1  to Tr 3 . 
         [0046]    Voltages Vg 1  to Vg 3  obtained by dividing the input signal Vi using voltage-dividing resistors Rg 1  to Rg 4  are input to the gate terminals of the transistors Tr 1  to Tr 3 , respectively. Relations between Vi and Vg 1  to Vg 3  are represented by the following Equations 6 to 8. 
         [0000]        Vg 1 =Vi *( Rg 2+ Rg 3+ Rg 4)/( Rg 1 +Rg 2 +Rg 3 +Rg 4)  Equation 6
 
         [0000]        Vg 2 =Vi *( Rg 3+ Rg 4)/( Rg 1 +Rg 2 +Rg 3 +Rg 4)  Equation 7
 
         [0000]        Vg 3 =Vi*Rg 4/( Rg 1+ Rg 2+ Rg 3 +Rg 4)  Equation 8
 
         [0047]    Assuming that a gate-source voltage (threshold voltage Vth) where the drain-source of the transistor becomes conductive/non-conductive is the same in the respective transistors Tr 1  to Tr 3 , Vi when the gate-source voltage of each transistor becomes Vth is expressed by the following Equations 9 to 11 sequentially from Tr 1 . According to these equations, it can be seen that the values of Vi to switch the conduction/non-conduction of the respective transistors become different from each other. 
         [0000]        Vi=Vth *( Rg 1 +Rg 2 +Rg 3 +Rg 4)/( Rg 2 +Rg 3 +Rg 4)  Equation 9
 
         [0000]        Vi=Vth *( Rg 1 +Rg 2 +Rg 3 +Rg 4)/( Rg 3 +Rg 4)  Equation 10
 
         [0000]        Vi=Vth *( Rg 1 +Rg 2 +Rg 3 +Rg 4)/ Rg 4  Equation 11
 
         [0048]      FIG. 8  is a waveform diagram of the input signal Vi. Herein, a triangular wave is used for example. As illustrated in  FIG. 8 , the transistors Tr 1  to Tr 3  reach the threshold voltage Vth at different voltage values of the triangular wave. Therefore, the respective transistors are switched at timings different from each other. 
         [0049]      FIG. 9  is a diagram illustrating an exemplary configuration of a frequency measurement circuit  2  which is connected to the open drain circuit  1 . The frequency measurement circuit  2  is provided with a frequency meter  3 , a pull-up power source Vp, and the pull-up resistor Rp. An input terminal Input of the frequency meter  3  is connected to the output terminal Fo of the open drain circuit  1 , and further connected to the pull-up power source Vp through the pull-up resistor Rp. 
         [0050]      FIG. 10  is a waveform diagram of the output voltage Vfo when the input signal Vi of the triangular wave is input to the open drain circuit  1  in the circuit configuration of  FIG. 9 . The respective transistors are switched when the input signal Vi becomes the values represented by Equations 9 to 11. Therefore, the output voltage Vfo changes in a stepwise shape as illustrated in  FIG. 10 . 
         [0051]    The output voltage Vfo when the transistors Tr 1  to Tr 3  are in a non-conductive state is set to Vfo 0 , the output voltage Vfo when the transistor Tr 1  is in the conductive state and the transistors Tr 2  and Tr 3  are in the non-conductive state is set to Vfo 1 , the output voltage Vfo when the transistors Tr 1  and Tr 2  are in the conductive state and the transistor Tr 3  is in the non-conductive state is set to Vfo 2 , and the output voltage Vfo when the transistors Tr 1  to Tr 3  are in the conductive state is set to Vfo 3 . These output voltages are expressed by the following Equations 12 to 15, respectively. 
         [0000]      Vfo0=Vp  Equation 12
 
         [0000]        Vfo 1 =Vp*Rd 1/( Rd 1 +Rp )  Equation 13
 
         [0000]        Vfo 2 =Vp*Rd 12/( Rd 12 +Rp )  Equation 14
 
         [0000]        Vfo 3 =Vp*Rd 123/( Rd 123 +Rp )  Equation 15
 
         [0052]    In Equation 14,Rd 12  is a combined resistor obtained by connecting the resistors Rd 1  and Rd 2  in parallel, and expressed by the following Equation 16. In Equation 15, Rd 123  is a combined resistor obtained by connecting the resistors Rd 1  to Rd 3  in parallel, and expressed by the following Equation 17. 
         [0000]        Rd 12= Rd 1* Rd 2/( Rd 1+ Rd 2)  Equation 16
 
         [0000]        Rd 123 =Rd 1* Rd 2 *Rd 3/( Rd 1* Rd 2 +Rd 2* Rd 3 +Rd 3 *Rd 1)  Equation 17
 
         [0053]    According to Equations 13 to 15, it can be seen that Vfo 1 =Vfo 2 =Vfo 3 =0 when there is no current limit resistors Rd 1  to Rd 3  in  FIG. 1 , and the output waveform does not change in a stepwise shape so as to obtain a rectangular waveform in which a high-potential side becomes Vp and a low-potential side becomes 0 (V). 
         [0054]      FIG. 11  illustrates a waveform of the output voltage Vfo in a case where a period of the input signal Vi changes in the circuit configuration of  FIG. 9 . The time difference between the switching timings of the respective transistors when the period of Vi is T 1  is and the time difference between the switching timings when the period of Vi is τ 2  is τ 2 . As described in  FIG. 10 , the switching timings of Tr 1  to Tr 3  depend on the potential of Vi. Therefore, when the period of Vi (the triangular wave) changes, the time difference between the switching timings of the respective transistors is in proportion to the period. The relation between T 1 , τ 2 , τ 1 , and τ 2  in  FIG. 11  is expressed by the following Equation 18. 
         [0000]        T 1 /T 2=τ1/τ2  Equation 18
 
       First Embodiment: Summary 
       [0055]    As described above, the open drain circuit  1  according to the first embodiment is provided with the delay circuit (the voltage-dividing circuit in the first embodiment) which deviates the switching timings for each of the respective transistors Tr 1  to Tr 3 . The delay circuit causes the delay time interval t between the respective transistors to be changed according to the frequency of the input signal Vi with respect to the open drain circuit  1 . Therefore, the delay time interval  7  is also shortened when the period of the input signal Vi is shortened, so that it is possible to suppress an abnormality in waveform of the output signal as illustrated in  FIG. 6 . In other words, the information is represented by the frequency of the input signal Vi, and the frequency measurement circuit  2  measures the frequency. Therefore, in a case where the information is acquired, it is possible to suppress an abnormality in measurement as illustrated in  FIG. 6 . 
       Second Embodiment 
       [0056]    As shown in Equations 13 to 15 described in the first embodiment, the voltages Vfo 1  to Vfo 3  when the output voltage Vfo is switched in a stepwise shape are obtained by divided by the pull-up power source Vp using the pull-up resistor Rp and the current limit resistors Rd 1  to Rd 3 . The pull-up resistor Rp and the current limit resistors Rd 1  to Rd 3  may be manufactured by a semiconductor process in many cases. A resistor manufactured by the semiconductor process may have a deviation in resistance (for example, about=±20%). In addition, there is also deviation in temperature property of the resistance. The open drain circuit  1  and the frequency measurement circuit  2  are manufactured separately Therefore, the pull-up resistor Rp and the current limit resistors Rd 1  to Rd 3  have a large deviation in a ratio of resistance value and in a ratio of temperature property of the resistance. If there occurs such a deviation in resistance value, the following problems are caused in real products. 
         [0057]    In the frequency meter  3  of  FIG. 9 , the voltage Vc is set for comparison with the output voltage Vfo. The comparison voltage Vc is set to a voltage between 0 (V) and the pull-up voltage Vp. The frequency meter  3  measures a frequency and a period of an output signal Vfo by measuring a time when a magnitude relation between Vfo and Vc is changed. 
         [0058]      FIG. 12  is an exemplary waveform in which the output signal Vfo and the comparison voltage Vc do not intersect. In this case, the output voltage Vfo is always larger than the comparison voltage Vc. Therefore, the frequency meter  3  is not possible to measure the frequency of the output signal Vfo. As can be seen from Equations 13 to 15, when the resistance values of the current limit resistors Rd 1  to Rd 3  are increasingly deviated with respect to the resistance value of the pull-up resistor Rp, Vfo 1  to Vfo 3  are also increased, which causes a situation as illustrated in  FIG. 12 . In a second embodiment of the invention, an exemplary circuit coping with such a problem will be described. 
         [0059]      FIG. 13  is a circuit diagram of the open drain circuit  1  according to the second embodiment. The open drain circuit  1  of  FIG. 13  is configured such that the current limit resistor Rd 3  is not provided in the circuit configuration illustrated in  FIG. 7  and the drain terminal and the output terminal Fo of the transistor Tr 3  are short-circuited. In the circuit configuration of  FIG. 13 , the output voltage Vfo becomes 0 (V) when Tr 3  comes to a conductive state. Therefore. Vfo can become a potential lower than that of ye regardless of the deviation in resistance of the pull-up resistor Rp and the current limit resistors Rd 1  to Rd 3 . 
         [0060]      FIG. 14  illustrates a circuit configuration from which the current limit resistor connected to the drain terminal of the transistor Tr 3  is removed from the conventional open drain circuit illustrated in  FIG. 3 , and thus the drain terminal is short-circuited with the output terminal Fo. In the conventional circuit configuration, a defect described below will be caused when the drain terminal of the transistor Tr 3  is short-circuited with the output terminal Fo similarly to the second embodiment. 
         [0061]    In the circuit configuration of  FIG. 14 , an order of switching the transistors Tr 1  to Tr 3  from the non-conduction to the conduction is equal to the order from the conduction to the non-conduction. In other words, Tr 1  is first switched and Tr 3  is finally switched in either case. 
         [0062]    In a case where the open drain transistors Tr 1  to Tr 3  are switched from the non-conduction to the conduction, the output voltage Vfo is switched in a stepwise shape. On the contrary, in a case where the transistors are switched from the conduction to the non-conduction, Vfo remains at 0 (V) during a period when Tr 3  is in conduction even Tr 1  and Tr 2  are in non-conduction. Thereafter, Vfo becomes the same potential as that of the pull-up voltage Vp when Tr 3  is switched to the non-conduction. Tr 3  comes to the conductive state to cause the output terminal Fo to be short-circuited to GND. 
         [0063]      FIG. 15  is a diagram illustrating a waveform of the output signal of the open drain circuit of  FIG. 14 . In  FIG. 15 , the waveform is switched at one time without changing in a stepwise shape when the output waveform is switched from a low potential (low level) to a high potential (high level). When the output waveform is steeply switched in this way, the effect of reducing radiation noises may be lessened. 
         [0064]    In order to relieve such a steep change in output waveform illustrated in  FIG. 15 , Tr 3  having no current limit resistor is finally switched in a case where the open drain transistors Tr 1  to Tr 3  are switched from the non-conduction to the conduction, and Tr 3  having no current limit resistor is firstly switched in the case of the order of switching from the conduction to the non-conduction is switched. In the first and second embodiments using the frequency signal of the triangular wave as the input signal Vi, the order of switching the open drain transistors Tr 1  to Tr 3  from the non-conduction to the conduction is in reverse to the order from the conduction to the non-conduction. In other words, Tr 3  is finally switched in the case of switching from the non-conduction to the conduction, and Tr 3  is firstly switched in the case of switching from the conduction to the non-conduction. Therefore, in the open drain circuit  1  according to the first and second embodiments, it is possible to suppress the steep change in output waveform illustrated in  FIG. 15 . 
       Second Embodiment: Summary 
       [0065]    As described above, the open drain circuit  1  according to the second embodiment can suppress the problem as illustrated in  FIG. 12  in that the resistance values of the pull-up resistor Rp and the current limit resistors Rd 1  to Rd 3  are deviated. Furthermore, it is possible to suppress a steep change in output waveform as illustrated in  FIG. 15  in a case where the similar configuration is employed to the conventional open drain circuit. 
         [0066]    In the second embodiment, the drain terminal of Tr 3  has been short-circuited with the output terminal Fo, and the other transistors may be short-circuited in the same way. For example, the drain terminal of Tr 2  may be short-circuited with the output terminal Fo. However, it is desirable that the transistor at the final stage be short-circuited with the output terminal Fo from a viewpoint that the output signal Vfo is changed in stages as many as possible. 
       Third Embodiment 
       [0067]      FIG. 16  is a diagram illustrating a waveform of the output signal of the open drain circuit  1  according to a third embodiment of the invention. In  FIG. 16 , a plurality of time differences τ are provided in the switching timing between the respective open drain transistors. The time difference between Tr 1  and Tr 2  is τ 1 , and the time difference between Tr 2  and Tr 3  is τ 2 . Since T 1  and τ 2  are determined according to Equations 9 to 11, τ 1  and τ 2  can be adjusted as illustrated in  FIG. 16  by adjusting a voltage division ratio of the voltage-dividing resistors Rg 1  to Rg 4 . 
         [0068]    In  FIG. 16 , when the output voltage Vfo is switched from a high potential (high level) to a low potential (low level), a delay time interval (τ 1 ) of the switching element to be switched early is smaller than a delay time interval (τ 2 ) of the switching element to be switched later. On the other hand, When the output voltage Vfo is switched from the low potential to the high potential, the delay time interval (τ 2 ) of the switching element to be switched early is larger than the delay time interval (τ 1 ) of the switching element to be switched later. In other words, τ 1  and τ 2  both are constant. 
         [0069]      FIG. 17  is a diagram illustrating a modification of the open drain circuit  1  according to the third embodiment. There are provided a plurality of time differences of the switching timing between the respective switching elements as τ 1  and τ 2  of  FIG. 16 . Therefore, the time differences may be provided in timing when the threshold voltage Vth is output to the respective gate terminals. The open drain circuit  1  illustrated in  FIG. 17  is provided with a microcontroller  4  which realizes such a configuration. The microcontroller  4  receives the input signal Vi, calculates a desired timing of switching the respective transistors according to Vi, and outputs Vth to the gate terminals of the respective transistors at that timing. 
         [0070]      FIG. 18  is an exemplary waveform of the output signal in the circuit configuration of  FIG. 17 , In  FIG. 18 , when the output voltage Vfo is switched from the high potential to the low potential, the delay time interval (τ 1 ) of the switching element to be switched early is smaller than the delay time interval (τ 2 ) of the switching element to be switched later. On the other hand, in a case where the output voltage Vfo is switched from the low potential to the high potential, the delay time interval (τ 2 ) of the switching element to be switched early is smaller than the delay time interval (τ 1 ) of the switching element to be switched later. In other words, τ 1  and τ 2  change according to time. 
         [0071]    In an actual product using the open drain circuit  1 , a capacitor, a resistor, and a diode may be provided as a surge protection element and a protection element against static discharge. In order to making an optimal setting to reduce radiation noises in a state where these elements are provided, there may be needed a plurality of switching time differences as illustrated in  FIGS. 16 and 18 . The output waveform according to the third embodiment is suitable to such as case. 
       Fourth Embodiment 
       [0072]      FIG. 19  is a diagram illustrating a configuration of a thermal-type flow meter  100  according to a fourth embodiment of the invention. The thermal-type flow meter  100  is a sensor to measure a flow rate of air, and provided with a measuring element  5 , a signal generator  6 , and the open drain circuit  1  according to the first to third embodiments. The measuring element  5  measures a flow rate of air, and outputs a meter voltage Vm corresponding to the measurement result. The signal generator  6  generates a periodic signal expressing the measurement result indicated by the meter voltage Vm using a frequency, and outputs the periodic signal to the open drain circuit  1  as the input signal Vi. The thermal-type flow meter  100  shows the flow rate of air using the frequency of the periodic signal. Therefore, it is desirable that the open drain circuit  1  according to the first to third embodiments be used. 
         [0073]    The invention is not limited to the above embodiments, and includes various modifications. The above embodiments are merely given to describe the invention in detail to help easy understanding, and there is no need to provide all the configurations described above. For example, the following modifications can be considered. 
         [0074]    The above embodiments have been described on an assumption that a field effect transistor (FET) is used as the open drain transistor, but the same configuration of the invention can be employed even in a case where a bipolar transistor is used. In other words, the same configuration of the invention can be employed in a circuit configuration in which the output signal is switched in a stepwise shape between the high level and the low level at every time when the respective switching elements connected at multiple stages are switched. 
         [0075]    In the above embodiment, the triangular wave has been used as the input signal Vi, and the same configuration of the invention can be employed even in a case where other periodic signal such as a sinusoidal wave or a trapezoid wave is used. 
         [0076]    In the above embodiment, the description has been made about that the period of the input signal Vi is in proportion to the delay time  17 , but not limited to a linear proportion relation. Other correspondence relations may be employed as long as t is increased or decreased according to increase/decrease of Vi. 
       REFERENCE SIGNS LIST 
       [0000]    
       
           1  open drain circuit 
           2  frequency measurement circuit 
           3  frequency meter 
           4  microcontroller 
           5  measuring element 
           6  signal generator 
         Tr 1  to Tr 3  open drain transistor 
         Rg 1  to Rg 4  voltage-dividing resistor 
         Rd 1  to Rd 3  current limit resistor