Abstract:
An input buffer for an Ultradeep Sub Micron (UDSM) process which allows the UDSM process to interface with a 3V input. The input voltage is applied to a degenerated transistor which forms part of the input buffer. The input buffer effectively drops the input voltage to a voltage suitable for use by the core of the UDSM process.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to input buffers for Ultradeep Sub Micron (UDSM) processes and their voltage interfaces. 
       BACKGROUND 
       [0002]    Modern wireless handsets are required to interface with many peripherals to provide the diverse functionality required of modern communications. One such peripheral is a Multimedia Card (MMC) which allows storage of data from many different devices. 
         [0003]    In wireless handsets, 3V I/O operation at 50 MHz is required to communicate with these cards. Since the application processor resides on an Ultradeep Sub Micron (UDSM) process, the I/O buffers need to be designed in these processes. However, UDSM processes do not have 3V transistors in the default mask set, interfacing to a 3V input is difficult. 
         [0004]    Various aspects of UDSM technology are described in the article “Full Chip Verification of UDSM Designs”, R. Saleh et al., Proceedings of 1998 IEEE/ACM International Conference on Computer Aided Design, pp. 453-460, the teachings of which are hereby incorporated by reference. 
         [0005]    It is therefore an object of the present invention to design an input buffer for a UDSM process that can interface with higher input voltages. 
       SUMMARY OF THE INVENTION 
       [0006]    According to one aspect of the present invention, there is provided an input buffer for interfacing an input voltage to an Ultradeep Sub Micron (UDSM) process having a core capable of operating at a core voltage, lower than the input voltage, the input buffer comprising an input transistor for receiving the input voltage, wherein the input transistor is a degenerated transistor. 
         [0007]    In one aspect, the degenerated transistor is a degenerated drain extended transistor. In one form of this aspect, the degenerated drain extended transistor is degenerated by a second transistor. 
         [0008]    In another form of the present invention, the input buffer further comprises a third transistor, which in combination with the second transistor causes the input transistor to enter linear mode when the input signal is high and to enter subthreshold mode when the input signal is low. 
         [0009]    In one arrangement, the drain of the second transistor is connected to the source of the input transistor, the gate of the second transistor is connected to the source of the third transistor and the drain of the first transistor is connected to the gate of the third transistor. The gate of the second transistor may be connected to the gate of the third transistor via a capacitor. 
         [0010]    According to another aspect of the present invention, there is provided a method of interfacing an input voltage to an Ultradeep Sub Micron (UDSM) process having a core capable of operating at a core voltage, lower than the input voltage, the method comprising applying the input voltage to a transistor of an input buffer of the UDSM, wherein the input transistor is a degenerated transistor. 
         [0011]    In a further form, the method comprises causing the input transistor to enter linear mode when the input signal is high and to enter subthreshold mode when the input signal is low, thereby providing an upper limit for a voltage applied to the core. 
         [0012]    According to another aspect of the present invention, there is provided an Ultradeep Sub Micron (UDSM) process comprising the input buffer of the present invention. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0013]    The invention will now be described in detail with reference to the following figures in which: 
           [0014]      FIG. 1  shows an exemplary application for the present invention in an applications processor; 
           [0015]      FIG. 2  shows a circuit diagram of one embodiment of the present invention; and 
           [0016]      FIG. 3  shows various waveforms at different nodes in the circuit of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION  
       [0017]    The present invention will now be described in detail with reference to one or more embodiments of the invention, examples of which are illustrated in the accompanying drawings. The examples and embodiments are provided by way of explanation only and are not to be taken as limiting to the scope of the invention. Furthermore, features illustrated or described as part of one embodiment may be used with one or more other embodiments to provide a further new combination. 
         [0018]    It will be understood that the present invention will cover these variations and embodiments as well as variations and modifications that would be understood by a person skilled in the art. 
         [0019]      FIG. 1  shows an applications processor  10  for use in a wireless communications handset such as 2.5 G and 3 G wireless handsets and multimedia-enabled wireless PDAs. The processor  10  provides capability such as video conferencing, digital music, mobile-to-mobile gaming and mobile TV. The processor also integrates a 330 MHz ARM1136 RISC processor core, dedicated 2D/3D graphics hardware acceleration, high-speed system interconnect, a host of peripherals, and camera, display and memory subsystems. 
         [0020]    As can be seen in  FIG. 1 , application processor  10  also interfaces with Multimedia Card (MMC)  12  at SD/SDIO  11 . It is at this location that the present invention may be applied, although it will be noted that the invention could also be applied to Personal Computer Memory Card International Association (PCMCIA), UMTS Subscriber Identification Module (USIM) Interfaces as well as other interfaces and processors. 
         [0021]    UDSM processes contain transistors capable of taking about 1.8V across the gate terminal and about 3.3V across the drain source terminals. These transistors are known as drain extended transistors. An aspect of the invention uses these existing drain extended transistors to design the 3V input buffer. 
         [0022]    In one embodiment, the input buffer is designed to take an I/O VDD supply ranging from 2.7V to 3.3V. The V IL  for the input buffer ranges from −0.3V to 0.3*VDDIO. The V II I  for the input buffer ranges from 0.7*VDDIO to VDDIO+0.3. The input buffer therefore has to detect voltages ranging from—0.3V to 0.99V as low, and voltages ranging from 1.89V to 3.6V as high. It will be appreciated that the difference between V IL(max)  and V IH(min)  is only 0.9V. 
         [0023]    According to one aspect of the present invention, the input signal is coupled to the core of the UDSM process via the gate of a degenerated drain extended transistor. However, the input signal should ideally be coupled through the gate when the source of the transistor is not grounded. The source may be raised from ground by the use of another device. 
         [0024]    The circuit as shown in  FIG. 2  shows such an arrangement and provides the following functionality. Firstly, it couples the input signal through a degenerated transistor M 1 . Secondly, the drive of the input transistor M 1  scales with the input signal, and thirdly, the circuit shifts the level of the input signal down to the core logic level, shown as VDDCORE. 
         [0025]    In this configuration, transistor M 2  degenerates the input transistor M 1 . The source of the input transistor M 1  is a very low impedance node (designated as “MID” in  FIG. 2 ). It can be shown that the impedance R out  at this node is given by the equation: 
         [0000]        R   out =( gm 2/ gds 2)/ gm 1   (1) 
         [0000]    where the subscript number refers to the transistor number in  FIG. 2   
         [0026]    Since MID is a low impedance node, it responds very quickly to the input signal. Whenever the input signal goes high, MID follows the input signal due to the low impedance. 
         [0027]    Due to the configuration of the transistors M 2  and M 3 , transistor M 1  goes into linear mode when the input signal goes very high. This limits the value of MID to 2(V T +V GST ) (where V T  is the threshold voltage of the transistor). This can be designed to be within 1.8V. When the input signal is only at V II I(min) transistor M 1  enters saturation mode and the MID node goes to V INPUT −V T . This is high enough to be detected as a high by a first inverter  20 . When the input signal goes low, transistor M 1  cuts off, causing the current in resistor R 1  to go to zero. 
         [0028]    When this happens, node FB goes towards the VDDIO voltage, which is coupled to node FB 1  through transistor M 3 . This then significantly increases the drive voltage of transistor M 2 , which then quickly pulls down the MID node. 
         [0029]    The node MID is coupled to the core inverters  20  and  30  using transistor M 4 . This transistor ensures that the node MID 1  (the input to the core inverters) is always lower than 1.8−V T (M 4 ), which is within core transistor reliability limits. 
         [0030]    Capacitor C 1  is also provided at nodes FB and FB 1  to increase the speed of coupling between these nodes. 
         [0031]    the circuit of  FIG. 2 , exemplary component parts and values are as follows:
   M 1 —DENMOS_1P8V   M 2 —DENMOS_1P8V   M 3 —DENMOS_1P8V   M 4 —DENMOS_1P8V   R 1 —60k   R 2 —300k   
 
         [0038]      FIG. 3  shows various simulated waveforms appearing at the nodes INPUT, FB, MID, MID 1  and OUTPUT in the circuit of  FIG. 2 . It can be seen that the voltage at the output clearly mirrors the voltage at the input, but is shifted from a maximum voltage of 2.4V to a maximum voltage of 1.1V suitable for use by the core.