Abstract:
A polishing platen of a chemical mechanical polishing apparatus and a planarization method using the same are disclosed. The polishing platen is formed of a first plate connected to a second plate. By independently controlling a thermal expansion of the first and second plates, a shape of an upper surface of the platen can be controlled and selectively altered. This allows a more precise polishing process and formation of a more uniform wafer. In one embodiment, the first and second plates, each have a different thermal expansion coefficient.

Description:
[0001]    This application claims the benefit, under 35 U.S.C. §119, of Korean Application No. P2001-064016 filed on Oct. 17, 2001, which is herein fully incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a chemical mechanical polishing apparatus, and more particularly, to a polishing platen of a chemical mechanical polishing apparatus and a planarization method using the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving uniformity in wafer thickness by using a thermal expansion coefficient of the polishing platen.  
           [0004]    2. Discussion of the Related Art  
           [0005]    Generally, a wafer is treated with a series of repeated processes, such as photolithography, ionic diffusion, etching, chemical vapor deposition, and metallic deposition, ultimately resulting in the fabrication of a chip (e.g., a semiconductor device).  
           [0006]    A metallic line structure with a fine pattern is formed on the wafer treated with the above-mentioned processes. In fact, as the semiconductor device becomes highly integrated and functionalized, a multi-layered line structure consisting of a plurality of metal line structures, insulating layers, and interlayer line structures is formed on the wafer.  
           [0007]    Such multi-layered line structures require a technique for planarizing a wafer surface. This is because if a gap exists between the wafer and a mask located on the wafer a pattern formed on the wafer becomes irregular. When a plurality of different fine patterns are sequentially formed on a wafer, having an irregular shape, the fine patterns are improperly formed. For example, a projection lens will be unable to be focused correctly. Thus, a required fine pattern is not achieved because of a low accuracy of the focus.  
           [0008]    Accordingly, the definition of fine patterns may be enhanced by an initial planarization process of the irregular block of the wafer. Generally, planarization is carried out through a polishing process of the wafer surface.  
           [0009]    The planarization process may include a borophospho Silicate glass BPSG reflow method (whereby boron and phosphor are doped), a spin on glass SOG etch-back method, and a chemical mechanical polishing CMP method.  
           [0010]    In the BSPG reflow method, a BSPG layer is deposited on a surface of a semiconductor substrate and then annealed. In the SOG etch-back method, an SOG layer is additionally deposited on an insulating layer having a circuit pattern layer. The SOG layer is then etched in order to enhance the degree of planarization.  
           [0011]    In the CMP method, a wafer having a step difference is adhered onto a pad and polished by using a slurry. This method is advantageous in that an overall planarization process can be carried out at a low temperature. Recently, the method has been widely used for planarizing memory devices of 256 mega and 1 giga size. More specifically, in the CMP method, a pad and a slurry are used to polish the wafer. A polishing platen attached to the pad rotates while a head unit rotates and vibrates in order to provide constant pressure.  
           [0012]    The wafer is mounted on the head unit by either surface tension or vacuum. Due to a load of the head unit and the applied pressure, the wafer surface comes into contact with the pad. A processing liquid (i.e., the slurry) flows through fine gaps (i.e., pores of the pad) formed between the two contacting surfaces thereof. In a mechanical removal process, abrasive particles of the slurry and surface embossed portions of the pad are used. In a chemical removal process, slurry chemistry is used.  
           [0013]    In the CMP process, contact begins at an upper portion of a protruded part of the device due to the pressure between the pad and the wafer. Since the pressure is concentrated on this portion, a surface eliminating speed is increased. During the process, irregular blocks are evenly reduced throughout the entire wafer surface.  
           [0014]    One of oxide (SiO 2 ), polysilicon, and metallic layer is polished. Herein, a combined solution of a chemical etchant (i.e., a basic or acidic solution) and an etchant (i.e., alumina or silica) is used as abrasive.  
           [0015]    Basically, oxide layers and metallic layers are processed with the CMP process under an identical sequence and with identical equipment. However, different slurries are used in each of the processes.  
           [0016]    In an oxide layer CMP process, a slurry (including substances such as colloidal silica dispersed in an alkaline solution (i.e., KOH)) is used as an abrasive. In a metallic CMP process, abrasive slurries, such as KlO 3  and AlO 3 , are used.  
           [0017]    Generally, after a CMP process, particles and slurries produced during the process are removed with a double-sided brush scrubber DDS. All particles and residue produced on an oxide layer can be removed by using the DDS. However, those on a metallic layer cannot be completely removed with the DDS only. Therefore, a later cleaning process is necessary in order to remove all remaining slurries, metallic impurities, and particles. For a cleansing solution, one of deionized water (DI water), NH 4 OH H 2 O 2 :H 2 O compositions (hereinafter, referred to as SC-1) and HF solution is used.  
           [0018]    The related art CMP apparatus for fabricating a semiconductor device will now be explained with reference to the accompanying drawings. FIGS. 1 and 2 illustrate structures of a related art CMP apparatus for fabricating a semiconductor device. More specifically, FIG. 1 is a CMP apparatus with an air pressure applying method using air holes. FIG. 2 is a CMP apparatus with an air pressure applying method using an air membrane.  
           [0019]    As shown in FIGS. 1 and 2, a pad  12  is attached to a polishing platen  11 . A semiconductor wafer  14  is secured to a wafer carrier  13  and mounted on the pad  12 . The semiconductor wafer  14  is secured to the wafer carrier  13  by means of either surface tension or vacuum.  
           [0020]    The wafer carrier  13  rotates to cause friction with the pad  12 . Thus, a surface of the semiconductor wafer  14  secured to the wafer carrier  13  is polished.  
           [0021]    A lower portion of the wafer carrier  13  includes a wafer supporting layer (not shown) and a wafer supporting ring (not shown), which secures the semiconductor wafer  14 .  
           [0022]    In addition, a slurry  15  is supplied to the pad  12  in order to accurately polish the wafer  14 . After polishing the semiconductor wafer  14 , a cleansing solution is applied to the pad  12  in order to cleanse the pad  12  and the semiconductor wafer  14  and to prepare them for subsequent processes.  
           [0023]    In the related art CMP apparatus, air pressure  16 , supplied through air holes (as shown in FIG. 1) or a membrane  17  (as shown in FIG. 2), is applied to a portion of the wafer carrier  13 , whereby the semiconductor wafer  14  is secured during the CMP process. Thus, air pressure is applied to the back side of the wafer during polishing of the semiconductor wafer  14 .  
           [0024]    The polishing platen  11  is formed of metals that are highly resistant to corrosive conditions, such as stainless steel or aluminum.  
           [0025]    More specifically, the related art CMP apparatus polishes a semiconductor wafer by applying air pressure  16 , through air holes or a membrane  17 , to the back side of the wafer, thereby planarizing the wafer.  
           [0026]    However, the related art CMP has the following disadvantages. When the air pressure is increased to a level exceeding a set range, the wafer is pushed out of the wafer carrier, causing the wafer to break.  
           [0027]    In addition, using air pressure may have some limitations. It is impossible to increase polishing pressure on a specific region only. In other words, an almost equal amount of pressure is applied to the overall wafer, which prevents an effective control of wafer uniformity.  
         SUMMARY OF THE INVENTION  
         [0028]    Accordingly, the present invention is directed to a polishing platen of a chemical mechanical polishing apparatus, and a planarization method using the same, that substantially obviates one or more problems due to limitations and disadvantages of the related art.  
           [0029]    An object of the present invention is to provide a polishing platen of a chemical mechanical polishing apparatus, and a planarization method using the same, that can enhance wafer uniformity during a CMP process by using a thermal expansion coefficient of a metallic material that forms the polishing platen.  
           [0030]    Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof, as well as the appended drawings.  
           [0031]    To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a polishing platen of a chemical mechanical polishing (CMP) apparatus, which supports a pad holding a semiconductor wafer that rotates during a CMP process, includes an upper metallic plate, and a lower metallic plate, each having a different thermal expansion coefficient.  
           [0032]    In another aspect of the present invention, a planarization method of a CMP apparatus, which adsorbs under a state of vacuum a semiconductor wafer onto a pad using a wafer carrier, and which polishes a semiconductor wafer surface by rotating the wafer carrier and by causing friction between the pad and the semiconductor wafer using air pressure or a membrane, includes attaching to a lower portion of the pad a polishing platen. The platen is formed of an upper metallic plate and a lower metallic plate, each having a different thermal expansion coefficient. The method includes polishing the semiconductor wafer by applying different temperatures to the upper metallic plate and the lower metallic plate and by supplying a slurry on the pad, and supplying a cleansing solution on the pad in order to cleanse the pad and the semiconductor wafer after the polishing process of the semiconductor wafer.  
           [0033]    It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0034]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings:  
         [0035]    [0035]FIGS. 1 and 2 illustrate a chemical mechanical polishing (CMP) apparatus for fabricating a semiconductor device, in accordance wit the related art;  
         [0036]    [0036]FIG. 3 illustrates a state of a polishing platen of a CMP apparatus, according to the present invention before processing begins;  
         [0037]    [0037]FIGS. 4A and 4B and FIGS. 5A and 5B are cross-sectional views illustrating the varying shapes of the polishing platen of the CMP apparatus, according to the present invention and controlling principles to attain wafer uniformity; and  
         [0038]    [0038]FIG. 6 is a perspective view illustrating a structure of the polishing platen of the CMP apparatus, according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0039]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.  
         [0040]    The present invention provides a polishing platen which has a shape that can be controllably varied. The platen can be used in a CMP apparatus identical to that of the related art. The inventive platen includes two metallic plates of different thermal expansion coefficients attached to each another. By controlling a temperature of the upper and lower metallic plates of the polishing platen during a CMP process of the semiconductor wafer, the polishing platen&#39;s shape is modified. Thereby, the present invention allows an edge or middle portion of the semiconductor wafer to be selectively polished more aggressively.  
         [0041]    More specifically, as shown in FIGS. 1 and 2, the CMP apparatus includes a semiconductor wafer  14  adsorbed under a state of vacuum onto a pad  12  by means of a wafer carrier  13 . While the wafer carrier  13  rotates oscillates or otherwise moves, the pad  12  and the semiconductor wafer  14  produce friction by using air pressure  16  or a membrane  17  to polish a surface of the semiconductor wafer  14 .  
         [0042]    The polishing platen  11 , onto which the pad  12  is attached includes a first or an upper metallic plate and a second or lower metallic plate. The plates have different thermal expansion coefficients. Thus, a polishing process concentrated on a central or edge portion of the semiconductor wafer can be carried out in accordance with a difference in temperature.  
         [0043]    [0043]FIG. 3 illustrates a state before processing with a polishing platen of a CMP apparatus, according to the present invention. As shown in FIG. 3, an upper metallic plate  20  and a lower metallic plate  30 , having different thermal expansion coefficients, are attached to one another to form the polishing platen. The upper metallic plate  20  and the lower metallic plate  30  may be attached by an adhesive or a screw.  
         [0044]    The upper metallic plate  20  has a thermal expansion coefficient higher than that of the lower metallic plate  30 , or vice versa. For example, stainless steel or aluminum may be used as the upper metallic plate  20 , and cast iron may be used as the lower metallic plate  30 , or vice versa.  
         [0045]    [0045]FIGS. 4A and 4B and FIGS. 5A and 5B are cross-sectional views illustrating modified shapes of the polishing platen of the CMP apparatus, according to the present invention. The FIGs. also illustrate controlling principles to attain wafer uniformity during polishing.  
         [0046]    As shown in FIG. 4A, the above-described polishing platen includes an upper metallic plate  20  having a thermal expansion coefficient higher than that of a lower metallic plate  30 . Therefore, as shown in FIG. 4B, the polishing platen curves upwards into a convex shape, when the lower metallic plate  30  is set at a low temperature relative to the upper metallic plate  20 .  
         [0047]    Conversely, as shown in FIG. 5A, the polishing platen includes a lower metallic plate  30  having a thermal expansion coefficient higher than that of an upper metallic plate  20 . Therefore, as shown in FIG. 5B, the polishing platen curves downwards into a concave shape, when the upper metallic plate  20  is set at a low temperature relative to the lower metallic plate  30 .  
         [0048]    When the polishing platen of the CMP apparatus curves into a convex shape, as shown in FIG. 4B, polishing pressure increases at the central portion of the semiconductor wafer  40 . Therefore, a removal rate at the central portion of the semiconductor wafer  40  is increased relative to a removal rate at the edge portions of the semiconductor wafer  40 .  
         [0049]    Conversely, when the polishing platen of the CMP apparatus curves into a concave shape, as shown in FIG. 5B, polishing pressure increases at the edge portions of the semiconductor wafer  40 . Therefore, a removal rate at the edge portions of the semiconductor wafer  40  is increased relative to a removal rate at the central portion of the semiconductor wafer  40 .  
         [0050]    A heating line and a cooling line are embedded within the upper metallic plate  20  and the lower metallic plate  30 , thereby enabling accurate control of temperatures therein. During the CMP process of the semiconductor wafer, a difference in temperature is controlled between the upper metallic plate  20  and the lower metallic plate  30  of the polishing platen, thereby changing the shape of the polishing platen. Thus, the polishing pressure can be controlled at the central and edge portions of the semiconductor wafer. This control results in better uniformity of the wafer during the polishing process.  
         [0051]    For example, if the temperature of the upper metallic plate  20  is increased and the temperature of the lower metallic plate is decreased, the polishing platen turns into a convex shape (FIG. 4B). This shape causes the polishing pressure of the central portion on the semiconductor wafer to increase during the polishing process, thereby causing an increase in a removal rate at the central portion of the wafer.  
         [0052]    Conversely, if the temperature of the upper metallic plate  20  is decreased and the temperature of the lower metallic plate  30  is increased, the polishing platen turns into a concave shape (FIG. 5B). This shape causes the polishing pressure on the edge portions of the semiconductor wafer to increase during the polishing process, thereby causing an increase in a removal rate at the edge portions of the wafer.  
         [0053]    After the polishing process, a cleansing solution is applied to the semiconductor wafer for cleansing. The cleansing solution prepares the wafer for further processing.  
         [0054]    [0054]FIG. 6 is a perspective view illustrating a structure of the polishing platen of the CMP process, according to the present invention. As shown in FIG. 6, a heating line and a cooling line  50  are embedded within the upper metallic plate  20  and the lower metallic plate  30 . This arrangement enables unrestricted control of temperatures in the upper and lower metallic plates  20 ,  30 .  
         [0055]    As described above, the polishing platen of the CMP apparatus, and the planarization method using the same, have several advantages. Unlike the related art apparatus, polishing pressure can be controlled at a surface which comes into contact with a front side of the wafer. This improves uniformity of the wafer after polishing.  
         [0056]    In addition, the present invention uses a thermal expansion coefficient. Thus, the structure of the apparatus is simpler than an apparatus using air pressure, and the polishing pressure can be controlled more accurately.  
         [0057]    In an apparatus whereby air pressure is applied to a back side of the wafer in order to control wafer uniformity, the wafer may be pushed outside the wafer carrier when excess air pressure is applied. However, in the present invention, such risk can be avoided.  
         [0058]    Although a single heating and cooling line  50  is depicted in each of the upper and lower plates  20 ,  30 , it is envisioned that each plate could contained one line dedicated for heating and one line dedicated for cooling. A heating or cooling line could be an electrical wire, (e.g. a resistive heating wire), or a conduit. In the case of a conduit, a temperature controlled gas or fluid could be passed through the line to control the temperature of the respective plate  20  or  30 .  
         [0059]    Since the upper plate  20  has a different thermal expansion coefficient than the lower plate  30 , it is possible to cause a deformation on the upper surface of the upper plate  20  by controlling a common temperature to both the upper and lower plate. For example, if the upper plate  20  is formed of stainless steel and the lower plate  30  is formed of cast iron, a deformation of the upper platen will occur as the upper and lower plates incur a common temperature change.  
         [0060]    Furthermore, it is possible to form the upper and lower plates  20 ,  30  of a same material having a same thermal expansion coefficient. In this arrangement, if a temperature of the upper plate  20  is controlled (via a heating or cooling line) to be different than a temperature of the lower plate  30  (via a different heating or cooling line), the upper surface of the upper platen will be controllably deformed. However, in a preferred embodiment of the present invention, it can be observed that by forming the upper plate  20  of a material having a different thermal expansion coefficient than the lower plate  30 , and by additionally controlling a temperature differential between the upper and lower plates  20 ,  30 , that the deformation will be more pronounced.  
         [0061]    It will be apparent to those skilled in the art than various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.