Abstract:
A method for manufacturing a ceramic substrate is characterized in using a preformed trench, a patterned protective layer and a sand blasting process to manufacture a cavity in a ceramic substrate and control the cavity size and shape of the ceramic substrate. The ceramic substrate is collocated with a base substrate to form a package substrate for packaging a semiconductor chip. The manufacturing method set forth above can lower the manufacturing cost and raise the accuracy of the size and shape of the cavity of the ceramic substrate. The abovementioned method can reduce the fabrication cost and increase the precision of the shape and size of a ceramic substrate.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a ceramic substrate, particularly to a ceramic substrate cooperating with a base substrate to form a package substrate. 
         [0003]    2. Description of the Prior Art 
         [0004]    In comparison with an ordinary plastic leaded chip carrier (PLCC), a ceramic package substrate features better performance in heat resistance, yellowness resistance, heat dissipation and reliability. A ceramic package substrate is usually as the package substrate of a high power transistor chip. 
         [0005]    A common ceramic package substrate is normally fabricated into a one-piece component with a low-temperature co-fired ceramic (LTCC) technology. While there is a slight modification in the product, such as varying the carrying area or side wall of a ceramic package substrate, the mold of the ceramic package substrate needs modifying, or even redesigning and fabricating once again. Therefore, the fabrication cost of a ceramic package substrate is very high. Further, the size or shape of the cavities in the chip receiving area of a ceramic package substrate is very likely to be affected by material shrinkage during the sintering process. 
         [0006]    Therefore, the industry is eager to provide a ceramic substrate whose cavity is precisely controlled for a semiconductor chip package component. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention provides a ceramic substrate, a package substrate, a semiconductor chip package component and a manufacturing method thereof, wherein a preformed trench, a patterned protective layer and a sand blasting process are used to precisely control the size and shape of the cavities of a ceramic substrate, and wherein the ceramic substrate and a base substrate are fabricated into a package substrate for packaging a semiconductor chip. 
         [0008]    One embodiment of the present invention provides a package substrate for packaging a semiconductor chip. The package substrate comprises a base substrate and a ceramic substrate. A surface of the base substrate has an electric-conduction contact. The ceramic substrate has a first surface, a second surface and at least one cavity. The ceramic substrate is disposed on the surface of the base substrate with the first surface thereof facing the surface of the base substrate. The cavity penetrates the first surface and the second surface of the ceramic substrate, defining a chip receiving area on the surface of the base substrate and accommodating the electric-conduction contact. The cavity has a vertical portion and a gradually-varying portion. The vertical portion is near the first surface; the inner diameter of the vertical portion is equal to a first diameter of the cavity on the first surface. The gradually-varying portion is near the second surface; the inner diameter of the gradually-varying portion gradually increases from the first diameter to a second diameter of the cavity on the second surface. 
         [0009]    Another embodiment of the present invention provides a ceramic substrate, which is collocated with a base substrate to form a package substrate for packaging a semiconductor chip. A surface of the base substrate has an electric-conduction contact. The ceramic substrate has a first surface, a second surface and at least one cavity. The ceramic substrate is disposed on the surface of the base substrate with the first surface thereof facing the surface of the base substrate. The cavity penetrates the first surface and the second surface of the ceramic substrate, defining a chip receiving area on the surface of the base substrate and accommodating the electric-conduction contact. The cavity has a vertical portion and a gradually-varying portion. The vertical portion is near the first surface; the inner diameter of the vertical portion is equal to a first diameter of the cavity on the first surface. The gradually-varying portion is near the second surface; the inner diameter of the gradually-varying portion gradually increases from the first diameter to a second diameter of the cavity on the second surface. 
         [0010]    Yet another embodiment of the present invention provides a semiconductor chip package component, which comprises a package substrate, a semiconductor chip, and an encapsulant. The package substrate comprises a base substrate and a ceramic substrate. A surface of the base substrate has an electric-conduction contact. The ceramic substrate has a first surface, a second surface and at least one cavity. The ceramic substrate is disposed on the surface of the base substrate with the first surface thereof facing the surface of the base substrate. The cavity penetrates the first surface and the second surface of the ceramic substrate, defining a chip receiving area on the surface of the base substrate and accommodating the electric-conduction contact. The cavity has a vertical portion and a gradually-varying portion. The vertical portion is near the first surface; the inner diameter of the vertical portion is equal to a first diameter of the cavity on the first surface. The gradually-varying portion is near the second surface; the inner diameter of the gradually-varying portion gradually increases from the first diameter to a second diameter of the cavity on the second surface. The semiconductor chip is arranged on the chip receiving area and electrically connected with the electric-conduction contact. The encapsulant is disposed in the cavity to encapsulate the semiconductor chip and the electric-conduction contact. 
         [0011]    A further embodiment of the present invention provides a method for manufacturing a ceramic substrate having a cavity, which comprises steps: providing a ceramic substrate having a first surface and a second surface opposite the first surface; fabricating a preformed trench on the first surface of the ceramic substrate; fabricating a patterned protective layer in the second surface of the ceramic substrate; and sand-blasting the second surface of the ceramic substrate to form a cavity penetrating the first surface and the second surface, wherein the cavity has a vertical portion and a gradually-varying portion, and wherein the vertical portion is near the first surface and has an inner diameter equal to a first diameter of the cavity on the first surface, and wherein the gradually-varying portion is near the second surface and has an inner diameter gradually increasing from the first diameter to a second diameter of the cavity on the second surface. 
         [0012]    The present invention can precisely manufacture ceramic substrates respectively having cavities with different shapes and sizes, neither modifying the mold nor redesigning/re-fabricating the mold. The present invention can further use the ceramic substrates and the base substrate of a common specification to fabricate package chips for packaging semiconductor chips. Therefore, the present invention can reduce the fabrication cost and increase the precision of the shape and size of the cavity of a ceramic substrate. 
         [0013]    Below, embodiments are described in detail in cooperation with the attached drawings to make easily understood the objectives, technical contents, characteristics and accomplishments of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1   a  is a sectional view schematically showing a package substrate according to one embodiment of the present invention; 
           [0015]      FIG. 1   b  is an exploded view schematically showing a package substrate according to one embodiment of the present invention; 
           [0016]      FIG. 2  is a top view schematically showing a ceramic substrate according to one embodiment of the present invention; 
           [0017]      FIG. 3  is a top view schematically showing a ceramic substrate according to another embodiment of the present invention; 
           [0018]      FIG. 4  is a sectional view schematically showing a semiconductor chip package component according to one embodiment of the present invention; 
           [0019]      FIG. 5  is a flowchart of a method for manufacturing a ceramic substrate according to one embodiment of the present invention; 
           [0020]      FIGS. 6   a - 6   e  are diagrams schematically showing the steps of a method for manufacturing a ceramic substrate according to one embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0021]    Refer to  FIG. 1   a,    FIG. 1   b  and  FIG. 4 . In one embodiment, the package substrate  10  of the present invention is used to package a semiconductor chip  20 , whereby to form a semiconductor chip package component  1 . The package substrate  10  comprises a base substrate  12  and a ceramic substrate  14 . The base substrate  12  is made of a ceramic material, a polymeric material or a metallic material. For example, the base substrate  12  is fabricated with at least one of a low-temperature co-fired ceramic (LTCC) substrate, a high-temperature co-fired ceramic (HTCC) substrate, a direct bonded copper (DBC) substrate, and a direct plate copper (DPC) substrate. A surface  120  of the base substrate  12  has two electric-conduction contacts  122   a  and  122   b,  which are respectively connected with two electrodes of the semiconductor chip  20 . In one embodiment, the ceramic substrate  14  is fabricated with at least one of a low-temperature co-fired ceramic (LTCC) substrate and a high-temperature co-fired ceramic (HTCC) substrate. Distinct from the conventional technology that uses a plastic frame or a metallic substrate, the present invention adopts a ceramic substrate, which has a thermal expansion coefficient near that of semiconductor materials and features high thermal conductivity, high insulativity and high reliability. 
         [0022]    The ceramic substrate  14  has a first surface  140 , a second surface  142  opposite the first surface  140 , and at least one cavity  144 . The ceramic substrate  14  is disposed on the surface  120  of the base substrate  12  with the first surface  140  thereof facing the surface  120  of the base substrate  12 . The cavity  144  penetrates the first surface  140  to form a first diameter  141  and penetrates the second surface  142  to form a second diameter  143 , defining a chip receiving area on the surface  120  of the base substrate  12  and accommodating the electric-conduction contacts  122   a  and  122   b.  The cavity  144  has a vertical portion  145   a  and a gradually-varying portion  145   b.  The vertical portion  145   a  is near the first surface  140 ; the inner diameter of the vertical portion  145   a  is equal to the first diameter  141  of the cavity  144  on the first surface  140 . The gradually-varying portion  145   b  is near the second surface  142 ; the inner diameter of the gradually-varying portion  145   b  gradually increases from the first diameter  141  to the second diameter  143  of the cavity  144  on the second surface  142 . In one embodiment, the inner surface of the gradually-varying portion  145   b  of the cavity  144  is treated with a coarsening process, such as a sand blasting process, to have a coarse surface. In one embodiment, the inner surface of the gradually-varying portion  145   b  of the cavity  144  is fabricated into a planar surface or a curved surface to meet the requirement of optical design. The person having ordinary skill in the art should be able to modify or vary the feature of the inner surface to meet requirement. 
         [0023]    In one embodiment, each of the cross sections respectively corresponding to the first diameter  141  and the second diameter  143  has a circular shape (as shown in  FIG. 2 ), an elliptic shape, a rectangular shape, a polygonal shape or a combination thereof, depending on the size of the semiconductor chip  20 , the package process and the mechanism design of the package component. Refer to  FIG. 3 . In the embodiment shown in  FIG. 3 , the cross section corresponding to the first diameter  141  is fabricated into a rectangular shape with four corners thereof recessed outward, whereby the semiconductor chip  20  can be disposed on the chip receiving area more easily in the succeeding die-bonding process. In one embodiment, a positioning mark  146  is printed on the second surface  142  to facilitate the positioning process and the alignment process in the package process. 
         [0024]    Refer to  FIG. 4 . One embodiment of the present invention proposes a semiconductor chip package component  1 , wherein a semiconductor chip  20  is installed in the chip receiving area and electrically connected with two electric-conduction contacts  122   a  and  122   b  of the surface  120  of the base substrate  12  via a conventional bonding technology, such as an eutectic bonding technology or a flip chip bonding technology. The chip receiving area has been described above and will not repeat herein. The semiconductor chip  20  is a light emitting diode, a light-condensing solar chip, a transistor, an integrated circuit chip, an active element, a protective element or a passive element. Then, the semiconductor chip  20  and the electric-conduction contacts  122   a  and  122   b  are encapsulated with an encapsulant  30  to form the semiconductor chip package component  1 . The encapsulant  30  is made of at least one material selected from a group including epoxy, silicone and hybrid package materials. In one embodiment, the semiconductor chip  20  is a light emitting diode. In such a case, a wavelength conversion material, such as a phosphor, may be added to the encapsulant  30  to generate a required working wavelength, such as white light. It should be easily understood: the gradually-varying portion  145   b  of the ceramic substrate  14  can increase the light extraction efficiency. Besides, the coarsened inner surface of the gradually-varying portion  145   b  can mix and uniformize light. 
         [0025]    Refer to  FIG. 5  and  FIGS. 6   a - 6   e.  One embodiment of the present invention proposes a method for manufacturing a ceramic substrate having a cavity. In Step S 41 , provide a ceramic  14  having a first surface  140  and a second surface  142  opposite the first surface  140 , as shown in  FIG. 6   a.  Next, in Step S 42 , fabricate a preformed trench  50  in the first surface  140  of the ceramic substrate  14 , as shown in  FIG. 6   b.  In one embodiment, a laser beam is used to cut the trench  50 . Next, in Step S 43 , fabricate a patterned protective layer  40  on the second surface  142  of the ceramic substrate  14 , as shown in  FIG. 6   c.  In one embodiment, the patterned protective layer  40  is fabricated with a photolithography technology, a mask-pressing technology or another conventional technology, which is well known and can be practiced by person having ordinary skill in the art. Next, in Step S 44 , sand-blast the second surface  142  to form a cavity  144  interconnecting with the trench  50 , as shown in  FIG. 6   d.  The cavity  144  penetrates the first surface  140  and the second surface  142  and has a vertical portion  145   a  and a gradually-varying portion  145   b.  The vertical portion  145   a  is near the first surface  145   a.  The inner diameter of the vertical potion  145   a  is identical to the first diameter  141  of the cavity  144  on the first surface  140 . The gradually-varying portion  145   b  is near the second surface  142 . The inner diameter of the gradually-varying portion  145   b  gradually increases from the first diameter  141  to the second diameter  143  of the cavity  144  on the second surface  142 . 
         [0026]    In one embodiment, the beads used in the sand blasting process are made of silicon carbide (SiC) and have an average diameter of 80 μm. In one embodiment, the sand blasting process includes a first sand blasting step and a second sand blasting step, which respectively use different impact forces. For example, the first sand blasting step uses an impact force of about 2-5 Kg/cm 2 , and the second sand blasting step uses an impact force of about 1 Kg/cm 2  for finishing the cavity. It is easily understood: the gradually-varying portion  145   b  is realized by the sand blasting process, which coarsens the inner surface of the gradually-varying portion  145   b.    
         [0027]    In one embodiment, the ceramic substrate  14  is cleaned. For example, the ceramic substrate  14  is cleaned with a brushing process or a flushing process to remove the dirt and debris generated by the fabrication steps, such as the laser cutting step. In one embodiment, a positioning mark  146  is fabricated on the second surface  142  with a laser cutting technology, a pigment-applying technology, a screen-printing technology, or another conventional technology, which is well known and can be practiced by the person having ordinary skill in the art. In one embodiment, before the patterned protective layer  40  is removed, the size and shape of the cavity is examined to verify whether the size and shape of the cavity meets the requirement. If there are defective products, such as the products having cavities whose diameters are too small, the defective products are returned to the blasting step and reprocessed once again. Compared with the conventional technology that use molds and a single sintering process to fabricate ceramic substrates, the present invention need not abandon defective products but reworks the defective products, wherefore the present invention can promote the yield and reduce the fabrication cost. In one embodiment, the patterned protective layer  40  is peeled off directly, etched off, or washed off with a basic solution, as shown in  FIG. 6   e.    
         [0028]    In conclusion, the present invention proposes a ceramic substrate, a package substrate, a semiconductor chip package component and a manufacturing method thereof, wherein a preformed trench, a patterned protective layer and a sand blasting process are used to fabricate a cavity having precise size and shape in a ceramic substrate, and wherein the ceramic substrate is disposed on a base substrate to form a package substrate, and wherein the package substrate is used in packaging a semiconductor chip to form a semiconductor chip package component, and wherein the present invention adopts a ceramic substrate, which has a thermal expansion coefficient near that of semiconductor materials and features high thermal conductivity, high insulativity and high reliability. Compared with the conventional technology that uses different molds or modifies/redesigns molds to fabricate green ceramic compacts for ceramic substrates of different specifications and completes ceramic substrates in a single sintering process, the present invention is exempted from modifying molds or redesigning/re-fabricating molds. Further, the present invention uses a common base substrate in fabricating different ceramics. Furthermore, the present invention need not abandon defective products but reworks the defective products. Therefore, the present invention can increase the precision of the shape and size of the cavities of ceramic substrates, promote the yield and reduce the fabrication cost.