Abstract:
Provided is a memory device comprising a molecular adsorption layer. The memory device includes: a substrate; a source electrode and a drain electrode formed on the substrate and separated from each other; a carbon nanotube (CNT) layer electrically connected to the source electrode and the drain electrode; a memory cell contacting the CNT so as to store a charge from the CNT; and a gate electrode formed on the memory cell, wherein the memory cell comprises: a first insulating layer formed on the CNT; a molecular adsorption layer which is formed on the first insulating layer and acts as a charge storage layer; and a second insulating layer formed on the molecular adsorption layer.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     This application claims the benefit of Korean Patent Application No. 10-2004-0088916, filed on Nov. 3, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.  
         [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a non-volatile memory device using carbon nanotubes (CNTs) as charge transport channels and comprising a memory cell having a molecular adsorption layer.  
         [0004]     2. Description of the Related Art  
         [0005]     A memory device includes a memory cell for writing and reading information and a transistor for switching an electrical current flow during writing and reading of the information in the memory cell.  
         [0006]     CNTs have excellent electrical conductivity and thermal stability and may have a long length of the order of micrometers with a diameter ranging from several nanometers to several tens of nanometers. CNTs may be applied to nano electro mechanical system (NEMS) devices having microstructures. Extensive research has been conducted on the use of CNTs in various devices and they are now used in electric field emission devices, optical switches in the field of optical communication, biodevices, etc.  
         [0007]     Methods of manufacturing CNTs are well known in the art. Examples include arc discharge, pulsed laser vaporization, chemical vapor deposition, screen printing, spin coating.  
         [0008]     To use CNTs in a memory device, p-type and n-type transistors are required. However, conventional transistors using CNTs exhibit ambipolar properties in a specific atmosphere or vacuum. Such transistors having ambipolar properties cannot be used as electronic devices.  
         [0009]     A method of converting an ambipolar carbon nanotube field effect transistor (CNT FET) into a unipolar CNT FET is described in NANO LETTERS, 2004 Vol. 4, No. 5, PP 947-950. In this method, a gate oxide layer on a drain electrode side was etched and a portion of a silicon substrate below the etched region was “V” cut to realize a p-type CNT FET. However, the process of obtaining the unipolar CNT FET is very complex.  
         [0010]     Thus, there is a need to readily produce a p-type transistor using a CNT as a channel region.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention provides a memory device comprising a memory cell using a molecular adsorption layer as a charge storage layer, the molecular adsorption layer comprising an adsorbed molecular layer having an energy level within an energy band gap of a carbon nanotube (CNT).  
         [0012]     According to an aspect of the present invention, there is provided a memory device including: a substrate; a source electrode and a drain electrode formed on the substrate and separated from each other; a carbon nanotube (CNT) electrically connected to the source electrode and the drain electrode; a memory cell contacting the CNT so as to store a charge from the CNT; and a gate electrode formed on the memory cell, wherein the memory cell includes: a first insulating layer formed on the CNT; a molecular adsorption layer which is formed on the first insulating layer and acts as a charge storage layer; and a second insulating layer formed on the molecular adsorption layer.  
         [0013]     According to another aspect of the present invention, there is provided a memory device including: a conductive substrate; a memory cell formed on the conductive substrate; a source electrode and a drain electrode formed on the memory cell and separated from each other; a CNT formed on the memory cell and electrically connected to the source electrode and the drain electrode; wherein the memory cell includes: a first insulating layer formed on the substrate; a molecular adsorption layer which is formed on the first insulating layer and acts as a charge storage layer; and a second insulating layer formed on the molecular adsorption layer.  
         [0014]     According to yet another yet another aspect of the present invention, there is provided a memory device including: a substrate; a first insulating layer formed on the substrate; a source electrode and a drain electrode formed on the first insulating layer and separated from each other; a CNT electrically connected to the source electrode and the drain electrode; a gate electrode formed on the first insulating layer between the source electrode and the drain electrode and separated from the CNT; a molecular adsorption layer which is formed on the CNT and the first insulating layer and acts as a charge storage layer; and a second insulating layer formed on the molecular adsorption layer, wherein the first insulating layer, the molecular adsorption layer, and the second insulating layer composes a memory cell.  
         [0015]     The molecular adsorption layer may include a molecular layer having an energy level within an energy band gap of the CNT.  
         [0016]     The molecular layer may be one selected from the group consisting of oxygen, bromine, iodine, and TTF (tetrathiafulvalene).  
         [0017]     The molecular adsorption layer may include a base layer selected from the group consisting of amorphous carbon, CNT, boron nitride, and zeolite and the molecular layer may be adsorbed on the base layer.  
         [0018]     The first and second insulating layers may be made of PMMA or an oxide.  
         [0019]     The first and second insulating layers may be made of a high dielectric material.  
         [0020]     The CNT may have a surface doped with alkali metal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]     The above and other features and advantages of the present invention will be further described in exemplary embodiments with reference to the attached drawings in which:  
         [0022]      FIG. 1  is a cross-sectional view of a memory device comprising a molecular adsorption layer according to an embodiment of the present invention;  
         [0023]      FIG. 2  is a model view illustrating an oxygen molecule adsorbed on carbon nanotubes (CNTs);  
         [0024]      FIG. 3  is a graph showing results calculated using Ab initio program for a structure of a CNT layer having an oxygen molecule adsorbed thereon;  
         [0025]      FIG. 4  is a graph showing operational properties of a memory device according to an embodiment of the present invention and a memory device in vacuum;  
         [0026]      FIG. 5  is a graph showing p-type characteristics of a memory device according to an embodiment of the present invention;  
         [0027]      FIG. 6  is a I-V graph of the memory device illustrated in  FIG. 1 ;  
         [0028]      FIG. 7  is a cross-sectional view of a memory device according to another embodiment of the present invention;  
         [0029]      FIG. 8  is a top view of a memory device according to still another embodiment of the present invention; and  
         [0030]      FIG. 9  is a cross-sectional view taken along line IX-IX of the memory device illustrated in  FIG. 8 . 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0031]     Hereinafter, a representative memory device comprising a molecular adsorption layer according to embodiments of the present invention will be described in detail with reference to the attached drawings.  
         [0032]      FIG. 1  is a cross-sectional view of a representative memory device comprising a molecular adsorption layer according to an embodiment of the present invention.  
         [0033]     Referring to  FIG. 1 , an insulating layer  12 , for example, made of silicon oxide is formed on a conductive substrate  10 , for example, a highly doped silicon wafer. Electrodes  13  and  14  are formed on the insulating layer  12  and are separated from each other. A carbon nanotube (CNT)  20  is formed between the electrodes  13  and  14  and electrically connected to the electrodes  13  and  14 . The electrodes  13  and  14  function as a drain region and a source region, respectively, and the CNT  20  which has a semiconductor property functions as a channel region.  
         [0034]     A memory cell  30  is formed on the CNT  20  and a gate electrode  40  is formed on the memory cell  30 . The memory cell  30  is composed of a first insulating layer  32 , a second insulating layer  36 , and a charge storage layer  34 . The charge storage layer  34  stores charges, i.e., electrons and holes, and is interposed between the first insulating layer  32  and the second insulating layer  36 . The gate electrode  40  controls transportation of the charges from the CNT  20  to the charge storage layer  34 .  
         [0035]     The charge storage layer  34  may be also referred to as a charge trap site. The charge storage layer  34  has a structure in which a molecular layer made of a material selected from oxygen, bromine, iodine, and tetrathiafulvalene (TTF) is adsorbed on a porous material, for example, amorphous carbon, CNT, boron nitride, and zeolite.  
         [0036]     The first and second insulating layers  32  and  36  may be made of silicon oxide or polymethyl methacrylate (PMMA) and have a thickness ranging from several nanometers to several tens of nanometers.  
         [0037]     Alternatively, the first and second insulating layers  32  and  36  may be made of a high dielectric material, such as ZrO 2  and HfO 2  in order to increase gate coupling.  
         [0038]     The CNT  20  may be made of single-wall CNTs or double-wall CNTs.  
         [0039]      FIG. 2  is a model view illustrating an oxygen molecule adsorbed on CNTs.  
         [0040]     Referring to  FIG. 2 , the oxygen molecule is adsorbed apart by 3.3Å from a surface of the CNTs. In this case, a binding energy of the oxygen to the CNT wall is 0.1 eV and the oxygen molecule is adsorbed on the CNT wall with a weak binding energy.  
         [0041]      FIG. 3  is a graph showing results calculated using Ab initio program for a structure of the CNT  20  having an oxygen molecule adsorbed thereon.  
         [0042]     Referring to  FIG. 3 , a LUMO (lowest unoccupied molecular orbital) potential of the oxygen molecule is present between a valence band and a conducting band. Due to the LUMO of the oxygen molecule, a unipolar property described below is attained.  
         [0043]     The molecular layer made of oxygen which provides the unipolar property has an energy level within an energy band gap of the CNT. A molecular layer made of bromine, iodine, or tetrathiafulvalene (TTF) may also have the same function as the molecular layer made of oxygen.  
         [0044]      FIG. 4  is a graph showing operational properties of a memory device according to an embodiment of the present invention and a memory device in vacuum.  
         [0045]     Referring to  FIG. 4 , a memory device before adsorption of oxygen molecules, i.e., in vacuum, exhibits p-type characteristics, i.e., when a gate bias voltage V g  is applied in the negative direction, the transistor is turned on, and the memory device also exhibits n-type characteristics, i.e., when a gate bias voltage V g  is applied in the positive direction, the transistor is turned on. That is, the memory device exhibits ambipolar properties.  
         [0046]     The memory device according to the present embodiment, which has a molecular layer of oxygen, exhibits p-type characteristics, i.e., when a gate bias voltage V g  is applied in the negative direction, the transistor is turned on. Meanwhile, when a gate voltage V g  is applied in the positive direction, the transistor is not turned on. That is, the oxygen molecules adsorbed on the CNT prevents opening of an n-type channel. Thus, the memory device exhibits unipolar properties.  
         [0047]      FIG. 5  is a graph showing p-type characteristics of a memory device according to an embodiment of the present invention. Referring to  FIG. 5 , a change of a channel current I ds  which occurs while changing source/drain voltages applied to a memory cell manufactured using double-wall CNTs according to an embodiment of the present invention from −30 mV to 30 mV demonstrates that the memory device has p-type characteristics.  
         [0048]     It is interpreted that the memory device has the unipolar property since when the gate voltage is applied in the positive direction, a partially occupied LUMO of the oxygen molecule between the valence band and the conducting band is prevented from going down, that is, opening of an n-channel is prevented.  
         [0049]      FIG. 6  is a I-V graph of the memory device illustrated in  FIG. 1 .  
         [0050]     Referring to  FIG. 6 , when a predetermined voltage is applied to the electrodes  13  and  14  and a positive gate voltage V g  is applied to the gate electrode  40 , the charge is trapped in the charge storage layer  34 . In such a state, it is regarded that first data is written on the memory cell  30 . The first data may be “0” or “1”.  
         [0051]     When a negative gate voltage V g  is applied to the gate electrode  40 , the charge in the memory cell  30  is discharged. In such a state, it is regarded that second data is written on the memory cell  30 . The second data may be “1” or “0”.  
         [0052]     When a voltage is applied to the electrodes  13  and  14  and a current I ds  flowing through the CNT  20  is a predetermined value or more, it is regarded that the first data is read from the memory cell  30  and when a current I ds  flowing through the CNT  20  is the predetermined value or less, it is regarded that the second data is read from the memory cell  30 .  
         [0053]     Although a p-type memory device was explained in the present embodiment, the present invention is not limited thereto. When the CNT  20  is doped with alkali metal, for example, potassium, the memory device has n-type characteristics (see U.S. Patent Application No. 2003/0122133).  
         [0054]     A writing operation of the memory device having the n-type CNTs is the same as described above. In a reading operation, a current I ds  flowing through the CNT  20  when a predetermined gate voltage is applied to the gate electrode  40  is read.  
         [0055]      FIG. 7  is a cross-sectional view of a memory device according to another embodiment of the present invention.  
         [0056]     Referring to  FIG. 7 , a memory cell  130  is formed on a conductive substrate  110 , for example, a highly doped silicon wafer. Electrodes  113  and  114  are formed on the memory cell  130  and are separated from each other. A CNT  120  is formed between the electrodes  113  and  114  and electrically connected to the electrodes  113  and  114 . The electrodes  113  and  114  function as a drain region and a source region, respectively, and the CNT  120  which has a semiconductor property functions as a channel region. Reference numeral  150  denotes a passivation layer.  
         [0057]     The memory cell  130  is composed of a first insulating layer  132 , a second insulating layer  136 , and a charge storage layer  134 . The charge storage layer  134  stores charges, i.e., electrons and holes, and is interposed between the first insulating layer  132  and the second insulating layer  136 . The conductive substrate  110  functions as a gate electrode and controls transportation of the charges from the CNT  120  to the charge storage layer  134 .  
         [0058]     The charge storage layer  134  may be also referred to as a charge trap site. The charge storage layer  134  has a structure in which a molecular layer made of a material selected from oxygen, bromine, iodine, and TTF (tetrathiafulvalene) is adsorbed on a porous material, for example, amorphous carbon, CNT, boron nitride, and zeolite.  
         [0059]     The first and second insulating layers  132  and  136  may be made of silicon oxide or PMMA and have a thickness ranging from several nanometers to several tens of nanometers.  
         [0060]     Alternatively, the first and second insulating layers  132  and  136  may be made of a high dielectric material, such as ZrO 2  and HfO 2  in order to increase gate coupling.  
         [0061]     The CNT  120  may be made of single-wall CNTs or double-wall CNTs.  
         [0062]     Since operations of the memory device illustrated in  FIG. 7  are substantially identical to those of the memory device illustrated in  FIG. 1 , detailed descriptions thereof will not be repeated.  
         [0063]      FIG. 8  is a top view of a memory device according to still another embodiment of the present invention.  FIG. 9  is a cross-sectional view taken along line IX-IX of the memory device illustrated in  FIG. 8 .  
         [0064]     Referring to  FIGS. 8 and 9 , a first insulating layer  232  is formed on a conductive substrate  210 . Electrodes  213  and  214  are formed on the first insulating layer  232  and are separated from each other. A CNT  220  is formed between the electrodes  213  and  214  and electrically connected to the electrodes  213  and  214 . The electrodes  213  and  214  function as a drain region and a source region, respectively, and the CNT  220  which has a semiconductor property functions as a channel region. A gate electrode  240  is formed on the first insulating layer  232  and isolated from each side of the CNT  220 . A third insulating layer  216  is formed surrounding the CNT  220 . A charge storage layer  234  is formed on the first insulating layer  232 , the gate electrode  240 , and a second insulating layer  236  is formed on the charge storage layer  234 .  
         [0065]     A memory cell  230  is composed of the first insulating layer  232 , the second insulating layer  236 , and the charge storage layer  234 . The charge storage layer  234  stores charges, i.e., electrons and holes, and is interposed between the first insulating layer  232  and the second insulating layer  236 .  
         [0066]     The gate electrode  240  may be formed only one side of the CNT  220 . The gate electrode  240  controls transportation of the charges from the CNT  220  to the charge storage layer  234 .  
         [0067]     The charge storage layer  234  may be also referred to as a charge trap site. The charge storage layer  234  has a structure in which a molecular layer made of a material selected from oxygen, bromine, iodine, and TTF (tetrathiafulvalene) is adsorbed on a porous material, for example, amorphous carbon, CNT, boron nitride, and zeolite.  
         [0068]     The first and second insulating layers  232  and  236  may be made of silicon oxide or PMMA and have a thickness ranging from several nanometers to several tens of nanometers.  
         [0069]     Alternatively, the first and second insulating layers  232  and  236  may be made of a high dielectric material, such as ZrO 2  and HfO 2  in order to increase gate coupling.  
         [0070]     Since operations of the memory device illustrated in  FIG. 8  are substantially identical to those of the memory device illustrated in  FIG. 1 , detailed descriptions thereof will not be repeated.  
         [0071]     According to the present invention, by using as a memory region a charge storage layer in which a molecular layer having an energy level within an energy band gap of a CNT, which is used as a channel, is adsorbed on a porous material layer, for example, made of CNTs, a nano-scale non-volatile memory device can be obtained. Further, the charge storage layer can be applied to a memory device having a stable charge trap site.  
         [0072]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.