Abstract:
Methods, apparatus, and systems, for interfacing one or more storage devices with a plurality of bridge chips. An apparatus may include a memory, a communication bus coupled to a device, and a processor communicatively coupled to the communication bus and the memory. The processor may be configured to implement storage traffic between a storage device and a central processor via a first storage port of a first bridge chip of a plurality of bridge chips. The processor may be further configured to multiplex, by the first bridge chip, the storage traffic to at least one bridge chip of the plurality of bridge chips, and distribute data across the plurality of bridge chips to produce a data distribution enabling each of the bridge chips to communicate with each other.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation of U.S. non-provisional application Ser. No. 12/498,162, filed Jul. 6, 2009, wherein the foregoing application is incorporated by reference in its entirety for all purposes. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to storage systems, and more particularly to storage systems including bridge device topologies. 
       BACKGROUND 
       [0003]    Often, memory systems use a bridge chip topology for translating commands associated with one protocol to another protocol associated with a drive being utilized. Typical bridge device topologies include a bridge coupled to a drive. In these cases, the single bridge typically supports multiple output devices on multiple ports. 
         [0004]    If the drive is much faster than the bridge, then the performance of the drive is limited by the bridge and a single drive unit will not see the performance of the drive. Rather, the unit will see the performance of the bridge. There is thus a need for addressing these and/or other issues associated with the prior art. 
       SUMMARY 
       [0005]    A system, method, and computer program product are provided for interfacing one or more storage devices with a plurality of bridge chips. One or more storage devices are provided. Additionally, a plurality of bridge chips are provided. Furthermore, at least one multiplexing device is provided for interfacing the one or more storage devices with the plurality of bridge chips. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  shows a system for interfacing one or more storage devices with a plurality of bridge chips, in accordance with one embodiment. 
           [0007]      FIG. 2  shows a system for interfacing one or more storage devices with a plurality of bridge chips, in accordance with another embodiment. 
           [0008]      FIG. 3  shows a system for interfacing one or more storage devices with a plurality of bridge chips, in accordance with another embodiment. 
           [0009]      FIGS. 4A-4B  show systems for interfacing one or more storage devices with a plurality of bridge chips, in accordance with another embodiment. 
           [0010]      FIGS. 5A-5C  show systems for interfacing one or more storage devices with a plurality of bridge chips, in accordance with various embodiments. 
           [0011]      FIG. 6  shows a method for interfacing one or more storage devices with a plurality of bridge chips, in accordance with one embodiment. 
           [0012]      FIG. 7  illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]      FIG. 1  shows a system  100  for interfacing one or more storage devices with a plurality of bridge chips, in accordance with one embodiment. As shown, the system  100  includes one or more storage devices  102 . 
         [0014]    In the context of the present description, a storage device refers to any device capable of storing data. For example, in various embodiments, the storage device  102  may include, but is not limited to, a Serial ATA (SATA) drive, a Serial Attached SCSI (SAS) drive, a Fibre Channel (FC) drive, or a Universal Serial Bus (USB) drive, and/or any other storage device. 
         [0015]    Additionally, the system  100  includes a plurality of bridge chips  104 . In the context of the present description, a bridge chip refers to any device capable of performing a protocol translation. For example, in various embodiments, the bridge chips  104  may include an SAS/SATA bridge (e.g. an SAS to SATA bridge, etc.), a USB/SATA bridge (e.g. a USB to SATA bridge, etc.), an FC/SATA bridge (e.g. an FC to SATA bridge, etc.), PCI/PCIe to SAS/SATA bridge, or any device capable of performing a protocol translation. 
         [0016]    Furthermore, at least one multiplexing device  106  is provided for interfacing the one or more storage devices  102  with the plurality of bridge chips  104 . In the context of the present description, a multiplexing device refers to any device capable of performing multiplexing, For example, in various embodiments, the multiplexing device may include a multiplexer, a bridge chip, a bridge, or any other device (e.g. hardware and/or software, etc.) capable of performing multiplexing. 
         [0017]    In various embodiments, the interfacing may include a direct connection or an indirect connection. In either case, the multiplexing device  106  may provide an interface such that the storage devices  102  may communicate with the plurality of bridge chips  104 . In this way, multiple bridge chips may be utilized in a storage system. Thus, the resources associated with a bridge chip may be solely dedicated to a particular device (e.g. a port, translation function, etc.). Of course, the resources of the bridge chip may be allocated in any manner desired. 
         [0018]    More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing framework may or may not be implemented, per the desires of the user. It should be strongly noted that the following information is set forth for illustrative purposes and should not be construed as limiting in any manner, Any of the following features may be optionally incorporated with or without the exclusion of other features described. 
         [0019]      FIG. 2  shows a system  200  for interfacing one or more storage devices with a plurality of bridge chips, in accordance with another embodiment. As an option, the present system  200  may be implemented in the context of the details of  FIG. 1 . Of course, however, the system  200  may be implemented in any desired environment. it should also be noted that the aforementioned definitions may apply during the present description. 
         [0020]    As shown, the system  200  includes a storage device  202 . In this case, the storage device  202  includes a SATA drive. Additionally, the system  200  includes a plurality of bridge chips  204 . 
         [0021]    In various embodiments, the bridge chips may include an SAS/SATA bridge (e.g. an SAS to SATA bridge, etc.), a USB/SATA bridge (e.g. a USB to SATA bridge, etc.), an FC/SATA bridge (e.g. an FC to SATA bridge, etc.), or any device capable of performing a protocol translation. In this case, the bridge chips  204  include an SAS/SATA bridge. 
         [0022]    Furthermore, at least one multiplexer  206  is provided for interfacing the storage device  202  with the bridge chips  204 . In this case, the multiplexer  206  includes a SATA multiplexer. Additionally, the multiplexer  206  may include a plurality of ports. 
         [0023]    For example, the multiplexer  206  may include a plurality of input ports. The input ports may be connected to the storage device  202 . Additionally, the multiplexer  206  may include a plurality of output ports. The output ports may be connected to the plurality of bridge chips  204 . In this case, a number of the output ports may be divided equally and allocated to each of the bridge chips  204 . 
         [0024]    In one embodiment, the multiplexer  206  may be configured such that each of the plurality of ports are active at the same time. Furthermore, one of the plurality of bridge chips  204  may be connected to a group of the plurality of ports. 
         [0025]    As shown in  FIG. 2 , as an option, a communication link  208  may be provided between one or more of the bridge chips  204 . In one embodiment, the communication link  208  may be configured such that each of the bridge chips  204  are capable of communicating with the other bridge chips  204 . 
         [0026]    As an option, the communication link  208  may be configured to be utilized for error recovery. As another option, the communication link  208  may be configured to be utilized for vender unique communication. As shown further in  FIG. 2 , each of the plurality of bridge chips  204  may be dedicated to a single Serial Attached SCSI (SAS) port. 
         [0027]    In this way, storage systems using storage devices (e.g. SATA drives, etc.) that are much faster than an attached bridge will not be limited by the bridge. This may be accomplished by using multiple bridges connected to a multiplexing device. 
         [0028]    As shown in  FIG. 2 , a SATA multiplexer is utilized. All ports of the SATA multiplexer may be active at the same time. The bridge chips may then use all of their resources for a single SAS port. 
         [0029]    As noted, there may also be a communication path between the bridge chip for error recovery and other vendor unique communication. This may greatly improve the bridge performance for a single port since all the bridge resources may be used to drive one port and not two ports. It should be noted that the performance may then be based on multiple bridge chips and not one bridge chip. This allows each bridge chip to focus resources on a particular bridge function. 
         [0030]    In one embodiment, the SATA multiplexer may be implemented using a number of tags from a first port and a number of tags on a second port. The tags on a third port may then be dedicated to the storage device. For example, the multiplexer may be implemented using tags 0-15 from port A and 0-15 on the port B, and then queuing tags 0-31 on port C to the SATA drive. 
         [0031]      FIG. 3  shows a system  300  for interfacing one or more storage devices with a plurality of bridge chips, in accordance with another embodiment. As an option, the present system  300  may be implemented in the context of the functionality and architecture of  FIGS. 1-2 . Of course, however, the system  300  may be implemented in any desired environment. Again, the aforementioned definitions may apply during the present description. 
         [0032]    As shown, a SATA drive  302  is in communication with multiple bridge chips  304 . In this case, a SATA multiplexer  306  interfaces the SATA drive  302  and the bridge chips  304 . Further, multiple communication links  308  are provided. 
         [0033]    The communication links  308  may include any type of communication path capable of being used to communicate between bridge chips. In various embodiments, the communication links  308  may be utilized for error recovery, vendor unique communication, and/or any other type of communication between bridge chips. 
         [0034]    The bridge chips  304  are capable of using all of the resources for a single SAS port. As shown, each of the bridge chips  304  are dedicated to one SAS port  310 . This may greatly improve the bridge performance for a single port since all the bridge resources may drive only one port. 
         [0035]    It should be noted that any number of bridge chips may be utilized with one or more multiplexing devices. In one embodiment, the number of bridge chips used in the system may be equal to the number of SAS ports present. Of course, any number of bridge chips may be utilized. 
         [0036]      FIGS. 4A-4B  show systems  400  for interfacing one or more storage devices with a plurality of bridge chips, in accordance with another embodiment. As an option, the present systems  400  may be implemented in the context of the functionality and architecture of  FIGS. 1-3 . Of course, however, the systems  400  may be implemented in any desired environment. The aforementioned definitions may apply during the present description. 
         [0037]    As shown, a plurality of storage devices  402  are provided. Further, one or more bridge chips  404  dedicated to interfacing with devices coupled to the storage devices  402  (e.g. device ports, etc.) are provided. Additionally, one or more bridge chips  406  may be utilized as a multiplexing device. 
         [0038]    Thus, if the resources are maxed out on one of the bridge chips  404 , data may be distributed across the bridge chips  406 , where at least one of the bridge chips  406  include multiplexer type functionality. In another embodiment, a multiplexer may be utilized, and additionally, functions may be spread across multiple bridges. Accordingly, a bridge chip may be used instead of a multiplexer, or in addition to multiplexer to perform multiplexing functionality. 
         [0039]      FIGS. 5A-5C  show systems  500  for interfacing one or more storage devices with a plurality of bridge chips, in accordance with various embodiments. As an option, the present systems  500  may be implemented in the context of the functionality and architecture of  FIGS. 1-4 . Of course, however, the systems  500  may be implemented in any desired environment. Further, the aforementioned definitions may apply during the present description. 
         [0040]    As shown in  FIGS. 5A-5C , a plurality of storage devices  502  are provided. Further, a plurality of bridge chips  504  dedicated to interfacing with devices coupled to the storage devices  502  (e.g. device ports, etc.) are provided. Additionally, one or more bridge chips  506  may be utilized as a multiplexing device. 
         [0041]    If the resources are maxed out on one of the bridge chips  504 , data may be distributed across the multiple bridge chips  506 , where at least one of the bridge chips  506  include multiplexer type functionality. As shown in  FIG. 5C , a multiplexer  508  may be utilized, and additionally functions may be spread across the multiple bridges  506 . It should be noted that any of the bridge chips  504  and  506  may be linked to any other bridge chip using one or more communication links  510 . 
         [0042]      FIG. 6  shows a method  600  for interfacing one or more storage devices with a plurality of bridge chips, in accordance with one embodiment. As an option, the present method  600  may be implemented in the context of the functionality and architecture of  FIGS. 1-5 . Of course, however, the method  600  may be carried out in any desired environment. Once again, the aforementioned definitions may apply during the present description. 
         [0043]    As shown, a command is sent from one of a plurality of bridge chips. See operation  602 . The command may include any command capable of being sent from a bridge chip. For example, in various embodiments, the command may include a read command, a write command, a FORMAT command, and/or any other command. 
         [0044]    In one embodiment, the command may be a command that was translated from a first protocol to a second protocol. In this case, the bridge chip may have translated the command. Further, sending the command from the bridge chip may include relaying a command using the bridge chip. This relaying may include translating the command. 
         [0045]    The command is then received at one or more storage devices. See operation  604 . In this case, the command is communicated utilizing one or more multiplexing devices interfacing the one or more storage devices with the plurality of bridge chips. 
         [0046]    Thus, in one embodiment, the command may be received by one of the bridges in a first format associated with a first protocol. The bridge may then translate the command to a second format associated with a second protocol. 
         [0047]    The bridge may then send the command to the storage device. A multiplexing device may then receive the command sent by the bridge to the storage device and route the command signal to the storage device. In this case, the multiplexing device may be directly coupled to the storage device and the bridge chips (e.g. using a bus, etc.). The multiplexing device may also be indirectly coupled to the storage device and the bridge chips (e.g. through an intermediate device, etc.). 
         [0048]    In another embodiment, a command or data may be received by one of the bridges in a first format associated with a first protocol (e.g. a SATA protocol, etc.). In this case, the storage device may have sent the command or data. The bridge may then translate the command or data to a second format associated with a second protocol (e.g. an SAS protocol, etc.). 
         [0049]    The bridge may then send the command to another device coupled to, or in communication with, the bridge. A multiplexing device may then receive the command or data sent by the storage device to the bridge and route the command signal to the appropriate bridge. 
         [0050]      FIG. 7  illustrates an exemplary system  700  in which the various architecture and/or functionality of the various previous embodiments may be implemented. As shown, a system  700  is provided including at least one host processor  701  which is connected to a communication bus  702 . The system  700  also includes a main memory  704 . Control logic (software) and data are stored in the main memory  704  which may take the form of random access memory (RAM). 
         [0051]    The system  700  also includes a graphics processor  706  and a display  708 , i.e. a computer monitor. In one embodiment, the graphics processor  706  may include a plurality of shader modules, a rasterization module, etc. Each of the foregoing modules may even be situated on a single semiconductor platform to form a graphics processing unit (GPU). 
         [0052]    In the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (CPU) and bus implementation. Of course, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. 
         [0053]    The system  700  may also include a secondary storage  710 . The secondary storage  710  includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, etc. The removable storage drive reads from and/or writes to a removable storage unit in a well known manner. 
         [0054]    Computer programs, or computer control logic algorithms, may be stored in the main memory  704  and/or the secondary storage  710 . Such computer programs, when executed, enable the system  700  to perform various functions. Memory  704 , storage  710  and/or any other storage are possible examples of computer-readable media. 
         [0055]    In one embodiment, the architecture and/or functionality of the various previous figures may be implemented in the context of the host processor  701 , graphics processor  706 , an integrated circuit (not shown) that is capable of at least a portion of the capabilities of both the host processor  701  and the graphics processor  706 , a chipset (i.e. a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter. 
         [0056]    Still yet, the architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system  700  may take the form of a desktop computer, lap-top computer, and/or any other type of logic. Still yet, the system  700  may take the form of various other devices including, but not limited to, a personal digital assistant (PDA) device, a mobile phone device, a television, etc. 
         [0057]    Further, while not shown, the system  700  may be coupled to a network [e.g. a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, etc.] for communication purposes. 
         [0058]    While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.