Abstract:
The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to transient suppression and more specifically to a method and apparatus for providing transient suppression in a phase locked loop (PLL) clock synthesis circuit in a central processing unit (CPU). 
     BACKGROUND OF THE INVENTION 
     The frequency of clock signals used in typical high performance CPU&#39;s has been steadily increasing, causing an increase in the complexity of CPU&#39;s due in part to physical packaging techniques used to accommodate high frequency clock circuits including high frequency clock input/output (I/O) circuits. In direct conflict with the trend towards higher frequency clock signals, is the need, caused by economic pressures in the industry, to provide simpler designs for CPU packages. 
     To avoid the need for high frequency I/O clock signals in CPU packages, some high performance CPU&#39;s use on-chip clock synthesis, based on phase locked loop (PLL) technology, to generate the desired high frequency clock signals. In these CPU&#39;s, a lower frequency reference clock signal is provided to the CPU, and the PLL within the CPU generates a high frequency clock signal having a predetermined frequency and phase relationship with the reference clock signal. This scheme avoids the need for high frequency clock I/O signals. 
     In multiprocessor systems, and in systems that provide high speed interfaces to memory devices and other chips, there are typically stringent phase and frequency requirements for high speed clock signals generated within a CPU. Because of these stringent requirements, global clock buffers and clock frequency dividers in the CPU are typically contained within a phase locked loop in a CPU, rather than contained outside the loop where frequency divider value changes could be handled in a simpler manner. The inclusion of the frequency dividers and clock buffers within the phase locked loop can introduce transient errors in the output clock signal when the frequency divider values are changed. 
     It is desirable in computer systems to provide real time automatic management of power consumption. One of the ways in which computer systems manage power consumption is to control the frequency of CPU on-chip generated clock signals. Typically, in a standby, low power consumption mode of a computer system, clock frequencies are lowered by a factor of two, resulting in a reduction of power consumption by the CPU of approximately one-half. Clock frequencies are typically lowered using software controlled frequency dividers contained within the phase locked loop clock synthesis circuit of the CPU. These frequency dividers reduce an input clock signal by a divider value controlled by software. 
     As discussed above, the frequency dividers are contained within the phase locked loop to allow the CPU to meet stringent phase and frequency requirements imposed on the clock signals. As a result, when the values of the frequency dividers are changed, transients may be introduced into the phase locked loop, causing the relative phase and frequency of the clock signal generated by the PLL to vary. This variation can prevent proper operation of the CPU and/or cause failure of devices coupled to the CPU due to timing errors relative to the reference clock signal. 
     It is an object of the present invention to provide a reduction of the transient signals discussed above. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention is directed to a processor. The processor includes processing circuitry that processes data at rates determined by a frequency of a clock signal, and a phase locked loop circuit that receives an input signal having a frequency and phase and provides the clock signal to the processing circuitry. The processor also includes means for changing the frequency of the clock signal, and means for limiting transient signals from the phase locked loop circuit caused by changing the frequency of the clock signal. 
     In one version of the first aspect, the phase locked loop circuit has a control loop, and the means for limiting includes means for disabling the control loop for a period of time when the frequency of the clock signal changes. 
     In another version of the first aspect, the phase locked loop circuit includes a charge pump circuit within the control loop, and the means for disabling the control loop includes means for disabling an output of the charge pump circuit. 
     In another version of the first aspect, the phase locked loop circuit further includes an oscillator, disposed within the control loop, that receives an input control signal and provides an output signal having a frequency determined by the input control signal. 
     In still another version of the first aspect, the phase locked loop circuit further includes a loop filter, disposed in the control loop between the charge pump circuit and the oscillator. 
     In different versions of the first aspect, the oscillator is either a current controlled oscillator or a voltage controlled oscillator and the loop filter is constructed and arranged to provide a substantially constant current or voltage to the oscillator when the charge pump circuit is disabled. 
     In still another version of the first aspect of the present invention, the phase locked loop circuit further includes an input frequency divider that receives the input signal and an output frequency divider that is coupled to the oscillator to receive the output signal from the oscillator. Each of the input frequency divider and the output frequency divider has a control input that receives a divider value control signal, and each of the input frequency divider and the output frequency divider sets a frequency divider value in response to the divider value control signal. 
     In another version of the first aspect, the means for limiting includes means for coordinating a divider value change in the output frequency divider with a divider value change in the input frequency divider, and means for indicating to the output frequency divider when a divider value change is to occur in the input frequency divider. 
     A second aspect of the present invention is directed to a processor that includes processing circuitry that processes data at rates determined by a frequency of a clock signal, and a phase locked loop circuit that receives an input signal having a frequency and phase and provides the clock signal to the processing circuitry. The frequency and phase of the clock signal are related to the frequency and the phase of the input signal. The phase locked loop circuit includes a first frequency divider having a signal input that receives the input signal, a signal output that provides a first divided signal having a frequency related to the frequency of the input signal by a divider value of the first frequency divider, and a control output that provides an output control signal a predetermined period of time prior to a change in the divider value of the first frequency divider. The phase locked loop circuit also includes a second frequency divider having an input that receives an oscillator signal having a frequency, an output that provides the clock signal, and a control input, coupled to the control output of the first frequency divider to receive the output control signal. The frequency of the clock signal is determined based on the frequency of the oscillator signal and a divider value of the second frequency divider. The second frequency divider implements a change in divider value in response to receipt of the output control signal. 
     In one version of the second aspect of the present invention, the second frequency divider includes a delay circuit that delays implementation of a divider value change for a delay period after receipt of the output control signal, to coordinate a time at which a divider value change is implemented in the second frequency divider circuit with a time at which a divider value change is implemented in the first frequency divider. 
     In another version of the second aspect, the phase locked loop circuit further includes a frequency detection and correction circuit disposed in a control loop of the phase locked loop circuit between the first frequency divider and the second frequency divider. The frequency detection and correction circuit has an output that provides the oscillator signal. 
     In another version of the second aspect, the phase locked loop circuit further includes a third frequency divider, having a divider value, disposed in the control loop between the output of the second frequency divider and an input of the frequency detection and correction circuit. 
     In yet another version, a duration of the delay period is determined based on the divider value of the third frequency divider. 
     In still another version of the second aspect, the phase locked loop circuit further includes a buffer circuit disposed in the control loop between the third frequency divider and the input of the frequency detection and correction circuit. The buffer circuit is constructed such that a signal delay period through the buffer circuit is approximately equal to a signal delay period through the first frequency divider. 
     A third aspect of the present invention is directed to a processor that includes processing circuitry that processes data at rates determined by a frequency of a clock signal, and a phase locked loop circuit that receives an input signal having a frequency and phase and provides the clock signal to the processing circuitry. The frequency and phase of the clock signal are related to the frequency and the phase of the input signal. The phase locked loop circuit includes a first frequency divider having a signal input that receives the input signal and a signal output that provides a first divided signal having a frequency related to the frequency of the input signal by a divider value of the first frequency divider. The phase locked loop circuit also includes a second frequency divider having an input that receives an oscillator signal having a frequency, and an output that provides the clock signal. The frequency of the clock signal is determined based on the frequency of the oscillator signal and a divider value of the second frequency divider. The phase locked loop circuit further includes a frequency detection and correction circuit having a first input that receives the first divided signal, a second input, an output that provides the oscillator signal and a control input. The frequency detection and correction circuit is responsive to a control signal at the control input to provide the oscillator signal at a fixed frequency and phase for a predetermined period of time. 
     In one version of the third aspect, the control signal is generated by the processing circuitry when a change in the divider value of the first frequency divider and the divider value of the second frequency divider occurs during implementation of a change in the frequency of the clock signal. 
     In another version of the third aspect, the frequency detection and correction circuit includes a charge pump circuit having an output that is disabled for the predetermined period of time in response to the control signal. 
     In yet another version of the third aspect of the present invention, the frequency detection and correction circuit further includes an oscillator, coupled between the output of the charge pump circuit and the output of the frequency detection and correction circuit, that receives an input control signal and provides the oscillator signal. 
     In another version of the third aspect, the frequency detection and correction circuit further includes a loop filter, disposed between the output of the charge pump circuit and the input of the oscillator. 
     A fourth aspect of the present invention is directed to a method of providing a clock signal in a CPU. The method includes steps of using a phase locked loop circuit to generate an output signal having a frequency, changing the frequency of the output signal and limiting transient signals from the phase locked loop circuit caused by changing the frequency of the output signal. 
     In one version of the fourth aspect, the step of limiting includes a step of disabling a control loop of the phase locked loop circuit for a predetermined period of time. 
     In another version of the fourth aspect, the phase locked loop circuit includes a charge pump circuit, and the step of disabling includes a step of disabling the charge pump circuit. 
     In still another version of the fourth aspect of the invention, the step of limiting includes a step of maintaining the output signal at a substantially constant frequency for the predetermined period of time. 
     In another version of the fourth aspect of the invention, the phase locked loop circuit has an input for receiving an input signal having a period, and the predetermined period of time is approximately equal to the period of the input signal. In another version, the phase locked loop circuit includes a first frequency divider having a divider value and a second frequency divider having a divider value, and the step of changing includes a step of changing the divider value of the first frequency divider and the second frequency divider. 
     In still another version of the method of the fourth aspect of the present invention, the step of limiting includes a step of coordinating a time at which the divider value of the first frequency divider is changed with a time at which the divider value of the second frequency divider is changed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the present invention, reference is made to the drawings which are incorporated herein by reference and in which: 
     FIG. 1 is a block diagram of a central processing unit (CPU) having a phase locked loop; 
     FIG. 2 is a block diagram of a CPU having a phase locked loop in accordance with one embodiment of the present invention; 
     FIG. 3 is a schematic diagram of a charge pump circuit used in the phase locked loop of FIG. 2; 
     FIG. 4 is a block diagram of a CPU having a phase locked loop circuit in accordance with another embodiment of the present invention; 
     FIG. 5 is a flow chart of a method of suppressing transients in the phase locked loop circuit of FIG. 4; and 
     FIG. 6 is a timing diagram of signals generated in the phase locked loop circuit of FIG. 4. 
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention will now be described below with reference to a phase locked loop circuit used in a CPU for generating high frequency clock signals. As understood by those skilled in the art, embodiments of the present invention are not limited for use in CPU&#39;s, but rather, may be used with phase locked loops, and other circuits, in devices other than CPU&#39;s. 
     FIG. 1 shows a phase locked loop (PLL) circuit 12 and a PLL control state machine 14 both contained within a CPU 10. As understood by those skilled in the art, typical CPU&#39;s include substantial additional processing and logic circuitry which is not shown in FIG. 1 for simplicity. The PLL 12 is used to generate a global clock signal GCLK having a precise frequency and having an exact phase relationship with an input reference clock signal CLKIN. The PLL 12 includes a phase frequency detector 16, a charge pump 18, a loop filter 20, a voltage controlled oscillator (VCO) 22, global clock buffers 24, and four frequency dividers DIV --  X 26, DIV --  Z 28, DIV --  Y 30 and DIV --  1 32. As described further below, DIV --  1 does not actually provide the functionality of a divider, but rather, acts as a dummy cell for delay matching purposes. 
     The operation of the PLL will now be described. The input reference clock signal CLKIN initially passes through a frequency divider circuit Div --  X which divides the frequency of the input signal by a value X that is software selectable based on a signal received from the PLL control state machine 14. The phase frequency detector 16 compares the output signal from the divider Div --  X at point 6 in the block diagram with a signal at point 5 to detect any differences or error in phase and frequency between the two signals. As will be described further below, the frequency and phase of the signal at point 5 arc related to the phase and frequency of the output clock signal GCLK. The phase frequency detector generates output error signals 16a and 16b based on the error detected, and the charge pump circuit 18 and the loop filter 20 provide filtering and conditioning of the error signals and generate a VCO control signal 20a. 
     The loop filter is implemented using an integrator consisting primarily of a resistor in series with a capacitor. The values of the resistor and the capacitor determine a time constant of the loop filter. A control signal 21 from the PLL control state machine to the loop filter is used to control the effective value of the resistor to change the time constant of the loop filter to maintain stability of the phase locked loop, which could otherwise be degraded by changes in the effective gain of the phase locked loop caused by changes in the divider values of the frequency dividers. 
     The VCO 22 generates an output signal designated as VCO --  CLK having a frequency that is controlled by the voltage of the VCO control signal 20a. The operation of the phase frequency detector 16, charge pump 18, loop filter 20 and VCO 22 are well known in the art. 
     The output signal of the VCO passes through a software controlled frequency divider DIV --  Z 28 which divides the frequency of the VCO output signal by a value Z that is software selectable based on a signal received from the PLL control state machine 14. In the PLL shown in FIG. 1, the value of Z is equal to twice the value of X, the divider value of DIV --  X. The output signal of divider DIV --  Z is input to the global clock buffers 24. The global clock buffers 24 provide signal buffering of the input signal and provide sufficient drive capacity so that the output clock signal GCLK may be utilized by a number of circuits within the CPU and/or external to the CPU. 
     The output clock signal GCLK of the PLL 12 is provided at point 9. The output clock signal is also fed back through dividers DIV --  Y and DIV --  1 to point 5 at the input of the phase frequency detector 16. Divider DIV --  Y, similar to dividers DIV --  X and DIV --  Z, is a controllable frequency divider implemented using digital logic. Divider DIV --  Y differs from dividers DIV --  X and DIV --  Z in that the divider value Y of DIV --  Y is set by hardwired logic, contained within the CPU, using a signal 30a, and thus the value Y is fixed. The value Y may be controlled by software, if it is desirable in a particular implementation to vary the value of Y. 
     In one typical application, in a normal mode of operation of the CPU 10, the values X, Y and Z are respectively set to 1, 5 and 2, and the VCO 22 is configured such that the frequency of the VCO --  CLK is 10 times the frequency of the reference clock CLKIN. In this application, the frequency of the output clock GCLCK is 5 times the frequency of the input clock CLKIN, which has a frequency of 100 MHz. 
     Divider DIV --  1 is an optional circuit in the phase locked loop 12 and is used to provide a time delay approximately equal to the time delay of DIV --  X, so that any skew between the signals at points 4 and 7 is approximately equal to any skew between signals at points 5 and 6. In one embodiment, this facilitates using the signals at output pads, corresponding to points 4 and 7, as timing references. DIV --  1 is similar in configuration to DIV --  X except that, in one embodiment, the divider value of DIV --  1 is always set to 1. 
     As discussed above, for certain modes of operation of the CPU 10, it is desirable to have the capability of changing the frequency of the output clock frequency GCLK of the PLL. This can be accomplished in the CPU 10 by changing the divider values X and Z of dividers DIV --  X and DIV --  Z. 
     Dividers DIV --  X and DIV --  Z operate in timing domains independent of each other as a result of uncontrolled and unknown propagation delays of the signals around the phase locked loop, the largest of these delays occurring in the global clock buffers 24. In addition, the dividers DIV --  X and DIV --  Z are typically implemented using digital counters as known in the art, and when a command signal is received by a divider commanding a change in divider value, the change is not implemented until the digital counter within the divider completes a cycle and reaches its initial or reset state. The period of the counter cycle in typical applications is equal to the period of the output clock signal of the divider. Accordingly, when the control signal from the PLL control state machine is changed to change the divider values of DIV --  X and DIV --  Z, the time at which the change is effective at each of the dividers will not be synchronous and may be skewed by as much as one period of the output clock signal of divider DIV --  X . This causes an uncertainty in the frequency and phase of the output clock signal GCLK for a duration of up to one period of the output clock signal of divider DIV --  X. 
     In one embodiment of the present invention shown in FIG. 2, a CPU 100 has a phase locked loop 112 and a PLL control state machine 114, each of which has been modified to reduce the period of uncertainty of the frequency and phase of the output clock signal when the divider values of the dividers 26 and 28 are changed. In FIG. 2, components of the CPU 100 that are the same as components of the CPU 10 of FIG. 1 are represented using the same reference numerals. 
     In the CPU 100, the PLL control state machine 114 has been modified to add a control line 115 to the charge pump circuit. The PLL control state machine 114 asserts a control signal on control line 115 when the divider values of DIV --  X and DIV --  Z are to be changed to a new value to provide a new frequency value for the output clock GCLK. The charge pump circuit 118 has been modified to respond to the control signal by disabling the output of the charge pump circuit while the control signal is asserted. In one embodiment of the present invention, the control signal is used to gate the output of the charge pump circuit, such that when the control signal is asserted, the output of the charge pump is disabled for ten periods of the reference clock signal CLKIN. For a reference clock signal having a frequency of 100 MHz, this corresponds to a period of disablement of the charge pump of 100 ns. After ten periods of the reference clock signal, the divider value of both DIV --  X and DIV --  Z will have stabilized to new values, and the charge pump circuit is again enabled to produce an output clock signal GCLK having the new frequency value. Other periods of disablement, greater than and less than 10 clock periods, may be used in other embodiments of the invention. 
     As discussed above, the loop filter is implemented using a series resistor and capacitor configured as an integrator. When the output of the charge pump is disabled, the input voltage to the VCO is controlled by a voltage across the capacitor of the loop filter, which should remain essentially constant for this brief period (100 ns). With a constant input voltage to the VCO, the output frequency of the VCO will also remain essentially constant. The output frequency of the phase locked loop remains essentially constant when the charge pump circuit is first disabled, and changes to approximately the new frequency value when the change in the divider value of DIV --  Z becomes effective. For the application described above, in which the frequency of the output signal from the VCO is approximately ten times the frequency of the input clock signal, the divider value of DIV --  Z will change before the completion of one period of the reference clock signal, since the period of the input signal to DIV --  Z is less than the period of the reference clock signal. 
     When the charge pump circuit is enabled after a change in divider value of the frequency dividers, there may be some differences in phase and frequency between the input signals to the phase frequency detector at points 5 and 6. These differences arc caused primarily by leakage current in the loop filter when the charge pump circuit is disabled (causing the input voltage to the VCO to decrease), and possibly, to a lesser extent, by any change in frequency and/or phase in the reference clock signal while the charge pump circuit was disabled. Depending on the magnitude of the differences in the input signals to the phase frequency detector, there may be an undesirable brief undershoot or overshoot in the frequency of the output signal GCLK after a change in frequency. To reduce the magnitude of the undershoot or overshoot, the bandwidth of the PLL may be reduced, however, reductions in PLL bandwidth may cause the PLL to be more susceptible to power supply noise. 
     One implementation of a microprocessor having a phase locked loop with charge pump gating is described in a paper entitled &#34;A 600 MHz CMOS PLL Microprocessor Clock Generator With a 1.2 GHz VCO&#34; by Vincent R. von Kaenel, et al., ISSCC Digest of Technical Papers, February 1998, San Francisco, Calif., which is incorporated herein by reference. 
     The design of the charge pump circuit 118 will now be further described with reference to FIG. 3, which shows a schematic diagram of the charge pump circuit. The charge pump circuit 118 is designed to provide current to or draw current from the loop filter 20 over line 18a (signal IO) depending on the levels of signals received over control lines 16a and 16b from the phase frequency detector 16. Control line 16a provides complementary signals UP and UPB which are respectively asserted HIGH and LOW when the phase frequency detector senses a positive error, requiring the VCO to speed up. Control line 16b provides complementary control signals DOWN and DOWNB which are respectively asserted HIGH and LOW when the phase frequency detector senses a negative error requiring the VCO to slow down. 
     The charge pump circuit 118 includes a number of CMOS transistors 126, 128, 130, 132, 134 and 136 that are configured as switches, controlled by the input signals of the charge pump circuit, that control the output current 10 at control line 18a. The charge pump circuit 118 also includes two current mirror circuits 142 and 144 that provide bias currents to the CMOS transistors to set the peak current out of or into the loop filter 20 when the UP/UPB or DOWN/DOWNB signals are asserted. The mirror circuits are controlled by signals IPCP and INCP. The charge pump circuit 118 further includes inverters/buffers 142, 144 and 146 that receive a signal, identified as STOP, that is asserted by the PLL control state machine to disable the charge pump circuit 118 when the divider values of the frequency dividers 26 and 28 are changed. 
     The operation of the charge pump circuit 118 will now be described. When the DOWN signal is asserted, NMOS transistor 132 is turned on, NMOS transistor 136 is turned off and current is drawn by mirror circuit 144 from the loop filter through line 18a, thereby, lowering the control voltage to the VCO. Also, when the DOWN signal is asserted, the UP signal is in a low state, PMOS transistor 134 is turned on, PMOS transistor 126 is turned off and current IOB from mirror circuit 142 is dumped through line 18b. Line 18b is a &#34;waste&#34; output used to dump current from either mirror circuit 142 or 144 when it is not coupled to output 18a. NMOS transistor 130 and PMOS transistor 128 remain on unless the STOP signal is asserted as described below. 
     When the UP signal is asserted, PMOS transistors 126 and 134 are respectively turned on and off, and current is provided from mirror circuit 142 to the loop filter through line 18a, thereby raising the control voltage to the VCO. Also, when the UP signal is asserted, the DOWN signal is in a low state, NMOS transistors 136 and 132 are respectively turned on and off, and current is drawn from line 18b through mirror circuit 144. 
     When the divider values of the dividers 26 and 28 are to be changed to effect a change in frequency of the PLL output clock signal GCLK, the STOP signal is asserted by the PLL control state machine. The assertion of the STOP signal causes PMOS transistor 128 and NMOS transistor 130 to be turned off preventing any current in line 18a. When there is no current in line 18a, the control voltage to the VCO from the loop filter remains essentially constant as described above. After the divider values have changed, the STOP signal is no longer asserted, and the charge pump circuit operates under the control of signals UP and DOWN as described above. 
     In the embodiment of the invention described above, the control loop of the phase locked loop circuit is broken by disabling the charge pump circuit during a divider value change of the frequency dividers to reduce the period of frequency uncertainty in the output clock signal and to suppress the generation of transient signals. In other embodiments of the present invention, the control loop of the phase locked loop circuit may be broken in other ways or places to isolate the phase locked loop from transient signals. 
     In another embodiment of the present invention shown in FIG. 4, a CPU 200 has a phase locked loop 212 and a PLL control state machine 214, each of which has been modified, in a manner different from that of CPU 100, to reduce the period of uncertainty of the frequency and phase of the output clock signal GCLK when the divider values of the dividers 26 and 28 are changed. In FIG. 4, components of the CPU 200 that are the same as components of the CPU 10 of FIG. 1 are represented using the same reference numerals. 
     The PLL control state machine 214 has been modified from that used in CPU 10 to include an additional control line to divider DIV --  X that asserts a control signal SMLAST CYCLE prior to a change in the divider values of dividers DIV --  X and DIV --  Y. Divider DIV --  X has been modified to receive and respond to the control signal SMLAST --  CYCLE and to provide a control signal DIVXLAST --  CYCLE to divider DIV --  Z. Divider DIV --  Z has been modified to receive and respond to the control signal DIVXLAST --  CYCLE. In addition, dividers DIV --  X and DIV --  Z have been modified to receive the MODULE POWERUP --  CONTROL signal which is used to initialize counters in the dividers and to provide other startup signals to the phase locked loop circuit when the CPU is powered on. 
     The PLL 212 reduces the period of uncertainty of the frequency of the output clock signal GCLK by coordinating the time at which dividers DIV --  X and DIV --  Z change their divider values. In the embodiment shown in FIG. 4, the divider DIV --  X upon receipt of the control signal SMLAST --  CYCLE completes a present counter cycle, at which point it asserts the control signal DIVXLAST --  CYCLE, and then, after the completion of one additional counter cycle (one period of the output clock signal of divider DIV --  X), DIV --  X changes its divider value to that indicated by control signal COMMON --  FREQ --  DIV --  VALUES. In other embodiments, the number of counter cycles that DIV --  X waits prior to implementing a divider value change may be set to values other than one. 
     The control signal DIVXLAST --  CYCLE is sent to divider DIV --  Z, so that divider DIV --  Z knows when divider DIV --  X will change divider values, and as explained further below, divider DIV --  Z then attempts to coordinate its change in divider value with that of DIV --  X. 
     The process of coordinating the change in divider values in accordance with one embodiment of the present invention will now be explained further with reference to FIGS. 5 and 6, which respectively show a flow chart of the process 300 and a timing diagram for the process. 
     The process will be described for a change in divider values of both dividers DIV --  X and DIV --  Z from a value of 1 to a value of 2. 
     In the timing diagram of FIG. 6, five clock signals A, B, C, D and E, and three control signals DIVXLAST --  CYCLE, DIVZSYNCHLAST --  CYCLE and DIVZDLYLAST --  CYCLE are shown. The five clock signals represent clock signals in the phase lock loop circuit 212 of FIG. 4 at the corresponding points on the phase locked loop circuit. As discussed above, control signal DIVXLAST --  CYCLE is a control signal from DIV --  X to DIV --  Z. the assertion of which indicates that the divider value of DIV --  X will change after one more cycle. Control signal DIVZSYNCHLAST --  CYCLE is an internal signal of DIV --  Z, that represents control signal DIVXLAST --  CYCLE synchronized into the timing domain of DIV --  Z. DIVZDLYLAST --  CYCLE is also an internal control signal of DIV --  Z, the assertion of which indicates that the divider value of DIV --  Z will change after one more cycle of the VCO clock. 
     In a first step 302 of process 300, the PLL control state machine receives a request to decrease the output frequency of the PLL 212 by a factor of 2. Next, in step 304, the PLL control state machine asserts the SMLAST CYCLE control signal and indicates with control signal COMMON --  FREQ --  DIV --  VALUES that the divider value is to change to 2. This occurs at time T, in FIG. 6. Divider DIV --  X then waits (step 306) until it reaches its initial state at which point it can implement a divider value change. However, rather than implement the divider value change when the initial state is reached, DIV --  X asserts control signal DIVXLAST --  CYCLE at time T 2  (step 308), and waits (step 310) for the next point (which occurs at time T 4 ) at which it can implement a divider value change before doing so (step 312). 
     Divider DIV --  Z receives control signal DIVXLAST --  CYCLE in step 314, and waits until it reaches its initial state (step 316) at which point it can (but does not yet) implement a divider value change. When divider DIV --  Z reaches its initial state, control signal DIVZSYNCHLAST CYCLE is asserted. The period of time (identified as synch jitter in FIG. 6) that DIV --  Z waits prior to asserting DIVZSYNCHLAST --  CYCLE has a maximum duration, or uncertainty period, equal to one period of the output clock of the VCO. In FIG. 6, this period of time is shown as being approximately equal to one period of the output clock of the VCO to represent the case of maximum jitter. After asserting the DIVZSYNCHLAST --  CYCLE control signal, divider DIVZ waits (step 318) for three cycles of the output clock of divider DIV --  Z. and then asserts the DIVZDLYLAST --  CYCLE control signal at time T 3 . The divider then waits for one cycle of the output clock (step 320), and then implements (step 322) the divider change at time T 4 . 
     The time at which divider DIV --  Z implements the divider change is shown in FIG. 6 as occurring at time T 4 , which is the time corresponding to maximum synch jitter (one cycle of the output clock). For a minimum synch jitter, the time at which DIV --  Z implements a divider change will be one output clock period sooner or time T 3 . In the timing diagram of FIG. 6, when there is maximum synch jitter, dividers DIV --  X and DIV --  Y are shown as implementing a divider value change at the same time. As understood by those skilled in the art, because of delays in the phase locked loop circuitry, dividers DIV --  X and DIV --  Y may not implement a divider change at the exact same time as shown in FIG. 6, however, the difference in time when the dividers change value should always be less than one output clock cycle. Therefore, in the embodiment of the invention discussed above, the uncertainty period for the output clock signal is reduced from one period of the input clock signal to one period of the output clock signal. 
     In the embodiment of the invention discussed above, divider DIV --  Z implements a delay of three periods of the output clock signal after receipt of control signal DIVXLAST --  CYCLE before asserting control signal DIVZDLYLAST --  CYCLE. The length of this delay (three output clock periods) is selected based on the value of divider DIV --  Y, which, in the illustrative embodiment above, has a value of 5. The delay is selected such that for the minimum synch jitter, the difference in time when dividers DIV --  X and DIV --  Z implement the divider change is approximately one output clock cycle, and for the maximum synch jitter, dividers DIV --  X and DIV --  Z implement a divider change at approximately the same time. As understood by those skilled in the art, the delay after receipt of control signal DIVXLAST --  CYCLE before asserting control signal DIVZDLYLAST --  CYCLE could be adjusted to other values based on different timing considerations in other phase locked loops. In addition, the value of the delay may be variable and be adjusted based on measured delays in a phase locked loop to further reduce the difference in time when dividers DIV --  X and DIV --  Z implement a divider value change. 
     Dividers DIV --  X and DIV --  Z may be designed using known digital components such as counters, flip flops and multiplexers to implement the functionality described above. It is preferable to design the dividers such that a change in divider value for a divider occurs only while the output clock signal of the divider is in a LOW state (i.e., zero voltage) to prevent any glitches in the clock signal output from the divider. 
     In the illustrative embodiment of the present invention discussed above, the frequency of the VCO clock signal is greater than the frequency of the input reference signal, and therefore, the clocking of DIV --  X occurs with a longer time period between clock edges than the clocking of DIV --  Z. Accordingly, in the embodiment described above, the time at which a divider value change is implemented in divider DIV --  Z is coordinated to the time at which a divider value change is implemented in divider DIV --  X, since DIV --  Z has a smaller time interval within which it can process information, leading to a smaller potential error in implementing a divider value change. In other embodiments of the present invention, in which the frequency of the VCO clock signal is less than the frequency of the reference input signal, the time at which a divider value change is implemented in divider DIV --  X is coordinated to the time at which a divider value change is implemented in divider DIV --  Z, in a manner similar to that discussed above. 
     In embodiments of the present invention discussed above, phase locked loop circuits having voltage controlled oscillators have been described. As understood by those skilled in the art, phase locked loop circuits may be implemented using current controlled oscillators in place of the voltage controlled oscillators. Embodiments of the present invention include phase locked loops utilizing current controlled oscillators. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements are intended to be within the scope and spirit of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention&#39;s limit is defined only in the following claims and the equivalents thereto.