Abstract:
A multi-port static random access memory for reducing an occupation area of a layout memory cells on a substrate having the improvements from a first plurality of metal electrode layers on a first plurality of active regions included in one unit cell and in other unit cell neighbored to the corresponding one unit cell of the first plurality of metal electrode layers being commonly connected to the power supply source, comprises: a second plurality of the metal electrode layers on second plurality of the active regions and to be independently and separately connected to the power supply source, by every one unit cell in cell array.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor device, and in particular to a multi-port static random access memory (hereinafter, referred to as “SRAM”) having a high operation speed. Further, the present invention relates to SRAM in which an occupation area of memory cells laid out on a substrate can be reduced by the formation of an electrical connection layer only within first unit cell in arrangement of memory cell array, for providing a common power supply source to the arrangement of memory cell array. 
   2. Description of the Related Art 
   In a conventional SRAM, every first unit cell has a flip-flop circuit including a pair of access transistors, a pair of drive transistors, and a pair of load transistors. Compared to first unit cell having a resistor as a load device in the conventional SRAM first unit cell having a bulk-type PMOS transistor as a load transistor has a lower stand-by current and is good in view of memory cell stability. Moreover, it has widely been used as an embedded memory cell in a conventional SRAM since first unit cell having a resistor as a load device and first unit cell having a bulk-type PMOS transistor as a load transistor had the same steps of a production process. Therefore, a multi-port SRAM has been developed for the purpose of increasing the operation speed of its data input/output and of having a wide system application from such a conventional SRAM. In such a multi-port SRAM, increasing the number of transistors in first unit cell is bad in view of an integration density. Problems such as an integration density, a process margin, and a reliability of an operation speed, however, now do not matter owing to the development of a production process art. A wide system application can be enough to load on people&#39;s attentions. 
     FIG. 1  is a circuit configuration diagram of first embodiment according to a conventional two-port SRAM. 
   In  FIG. 1 , a load transistor for common use, a drive transistor for carrying out a write operation, and an access transistor for carrying-out a read operation are shown in first unit cell. There are a pair of read bit line RB and /RBB and a pair of write bit line WB and /WBB in a vertical direction. There are a power supply voltage VCC and a write word line WWL in the upper part of first unit cell, and a power supply ground VSS and a read word line RWL in the lower part of first unit cell. 
   As be shown in  FIG. 1 , a pair of write access transistors WTA 1  and WTA 2 , and a pair of read access transistors RTA 1  and RTA 2 , a pair of load transistors TL 1  and TL 2 , a pair of write drive transistors WTD 1  and WTD 2 , and a pair of read drive transistors RTD 1 , and RTD 2  consist of first unit cell. All the above described transistors have a set of first and second electrodes and gate electrode. Gate electrodes of the write access transistors WTA 1  and WTA 2  in first unit cell are respectively and electrically connected to a write word line WWL. Each of first electrodes of the write access transistors WTA 1  and WTA 2  is electrically coupled to the corresponding bit line of the pair of write bit line WB and /WBB. Also, gate electrodes of the read access transistors RTA 1  and RTA 2  are respectively and electrically connected to the read word line RWL. Each of first electrodes of the read access transistors RTA 1  and RTA 2  is electrically coupled to the corresponding read bit line of the pair of read bit lines RB and /RBB. Each of first electrodes of the load transistors TL 1  and TL 2  is respectively connected to power supply voltage VCC. Each of gate electrodes of the load transistors TL 1  and TL 2  is respectively connected to a first pair of common nodes CN 1  and CN 2 . First common node CN 1  is electrically linked to second common node CN 2  in the first pair of common nodes CN 1  and CN 2 . First write drive transistor WTD 1  at the pair of write drive transistors WTD 1  and WTD 2  and first read drive transistor RTD 1  at the pair of read drive transistors RTD 1  and RTD 2  are in series connected to first load transistor TL 1  at the pair of load transistors TL 1  and TL 2 . Each of gate electrodes of first write drive transistor WTD 1  and first read drive transistor RTD 1  is respectively connected to second common node CN 2  of the first pair of the common nodes CN 1  and CN 2 . A serial connection of second write drive transistor WTD 2  and second read drive transistor RTD 2  is linked to second load transistor TL 2 . And each of gate electrodes of second write drive transistor WTD 2  and second read drive transistor RTD 2  is commonly connected to the first pair of common nodes CN 1  and CN 2 . Second electrodes of first load transistor TL 1  and first write access transistor WTA 1  and first electrode of first write drive transistor WTD 1  are electrically linked to each second through first common node CN 1 . 
   Further, second electrodes of second load transistor TL 2  and second write access transistor WTA 2  and first electrode of second write drive transistor WTD 2  are mutually connected to second common node CNB, too. Second electrode of first write drive transistor WTD 1  and first electrode of first read drive transistor RTD 1  are respectively connected to the power supply ground VSS. Each of second electrodes of the pair of read access transistors RTA 1  and RTA 2  which are PMOS transistors, is respectively connected to the corresponding electrode of the pair of read drive transistors RTD 1  and RTD 2 . And write access transistors WTA 1  and WTA 2 , read access transistors RTA 1  and RTA 2 , write drive transistors WTD 1  and WTD 2 , read drive transistors RTD 1  and RTD 2  are NMOS transistors. First electrode of first load transistor TL 1  is electrically connected to power supply voltage VCC, together with second load transistor TL 2  included in the second unit cell neighbored to the corresponding first unit cell. Also, an electrical common connection of first electrode of second load transistor TL 2  and first load transistor included in second unit cell neighbored to the corresponding first unit cell is made via power supply voltage VCC. First write drive transistor WTD 1  and first read drive transistor RTD 1  transistor included in first unit cell are electrically linked to power supply ground VSS, together with second write drive transistor and second read drive transistor neighbored to the corresponding first unit cell. Second write drive transistor WTD 2  and second read drive transistor RTD 2  are electrically coupled to power supply ground VSS, together with write drive transistor and read drive transistor included in second unit cell neighbored to the corresponding first unit cell. 
     FIG. 2   a  to  FIG. 2   i  are patterned layout configuration diagrams for explaining process steps of first embodiment of a two-port SRAM according to a prior art invention. 
   In  FIG. 2   a , an N-type well region  22  is formed on first part of a cell formation region  21  in order to define a PMOS transistor which is used as a load transistor, wherein the cell formation region  21  is not a fixed region, rather than can be varied. Second region except the N-type well region  22  in the cell formation region  21  is a P type well region. By a formation of a device isolation layer (not shown) in a field region  23  of the cell formation region  21  are made first to seventh active regions  24   a  to  24   g  as shown in  FIG. 2   b . In  FIG. 2   c , first to fourth electrode patterned layers  25   a  to  25   d  are passed through over at least any first portion of the first to seventh active regions  24   a  to  24   g . By exposing the first to seventh active regions  24   a  to  24   g  using the first to fourth electrode patterned layers  25   a  to  25   d  impurity regions (not shown) are formed within the substrate surfaces of their regions  24   a  to  24   g . A selective exposure of the impurity regions or the first to seventh active regions  24   a  to  24   g  makes a formation of a plurality of contact regions  26  which are selectively etched after repeatedly carrying out a formation of an insulation layer between first layer and a corresponding second layer over contact regions  26  in  FIG. 2   d.    
   As shown in  FIG. 3   a , an N-type well region  22  is formed in order to function as a pair of first and second load transistors TL 1  and TL 2 . A formation of first and second active regions  24   a  and  24   b  is made by a separation of the N-type well region  22  to horizontal direction. In some region except N type well region  22  in the cell formation region  21  which is a P-type well region, third and fourth active regions  24   c  and  24   d  which face each second are formed by meeting at least first extension portion to a perpendicular direction from an intersection between a long axis of a horizontal direction and a long axis of a vertical direction. Also, fifth active region  24   e  is formed on a separation region of first and second active regions  24   a  and  24   b . Sixth and seventh active regions  24   f  and  24   g  are respectively formed on left and right lower portions of third and fourth active regions  24   c  and  24   d . A first metal electrode layer  25   a  is formed in order to be utilized as gate electrodes of first load transistor TL 1 , first write drive transistor WTD 1 , and first read drive transistor RTD 1 . First metal electrode layer  25   a  has a configuration in which a central portion of first active region  24   a  is passed on in a vertical direction and at least two portions of third active regions  24   c  are passed on. Second metal electrode layer  25   a  is formed so that a central portion of second active regions  24   d  are passed on. As gate electrodes of second load transistor TL 2 , second write drive transistor WTD 2 , and second read drive transistor RTD 2  functions first metal electrode layer  25   a . Third metal electrode layer  25   c  is formed in order to be utilized as gate electrodes of first and second write access transistors WTA 1  and WTA 2 . Third metal electrode layer  25   c  has a configuration in which third and fourth active regions  24   c  and  24   d  are respectively passed on to vertical direction and their vertical extension portions are met at a predetermined position with each second so that a horizontal extension portion is formed in a horizontal direction. Fourth metal electrode layer  25   d  which is utilized as gate electrodes of first and second read access transistor RTA 1  and RTA 2 , is formed so that the lower portions of third and fourth active regions  24   c  and  24   d  are passed on at the same time. Further, a plurality of contact regions  26  are formed on first to seventh active regions  24   a  to  24   g  of which any portion are not passed on by first to fourth first to fourth metal electrode layer  25   a  to  25   d  or on first to fourth metal electrode layer  25   a  to  25   d . Fifth active region  24   e  is formed in order to be defined as well bias of N type well region  22 . After carrying out a process step for the purpose of obtaining the above described patterned configuration, a process step for forming a first group of metal electrical wires including metal electrical wire layers  27   a  to  27   m  is performed as shown in  FIG. 2   e.    
   In  FIG. 2   e , first to fifth metal electrical wire layers  27   a  to  27   e  are formed in order to be utilized as a power supply voltage VCC, a write word line WWL, a read word line RWL, etc., and sixth to thirteenth metal electrical wire layers  27   f  to  27   e  are formed in order to be utilized as an interior electrical wire. A plurality of via holes  28  are formed, as shown in  FIG. 2   f , on first to thirteenth metal electrical wire layers  27   a  to  27   e . In  FIG. 3   b , first metal electrical wire layer  27   a  is electrically contacted with first electrodes of first and second load transistors TL 1  and TL 2 . A electrical connection of gate electrodes of first load transistor TL 1 , first write drive transistor WTD 1 , and read drive transistor RTD 1 , and first common node CN 1  is made by second metal electrical wire layer  27   b . Third metal electrical wire layer  27   c  causes second common node CN 2  to make an electrical connection of gate electrodes of second load transistor TL 2 , second write drive transistor WTD 2 , and second read drive transistor RTD 2 . Fourth metal electrical wire layer  27   d  which is a horizontal extension, is formed in order to electrically contact with gate electrodes of first and second write access transistor WTA 1  and WTA 2 . In order to electrically contact with gate electrodes of first and second read access transistors RTA 1  and RTA 2 , fifth metal electrical wire layer  27   e  is formed. Sixth and seventh metal electrical wire layer  27   f  and  27   g  are formed in order to electrically contact with first electrodes of first and second write access transistors WTA 1  and WTA 2 . Eighth and ninth metal electrical wire layers  27   h  and  27   i  are formed in order to be electrically contacted with first electrodes of first and second read access transistors RTA 1  and RTA 2 . With third common node CN 3  of first write drive transistor WTD 1  and first read drive transistor RTD 1  is electrically contacted tenth metal electrical wire layer  27   j . Eleventh metal electrical wire layer  27   k  is formed in order to electrically contact with fourth common node CN 4  of second write drive transistor WTD 2  and second read drive transistor RTD 2 . Twelfth and thirteenth metal electrical wire layers  27   l  and  27   m  are formed in order to contact with power supply voltage VCC. First plurality of via holes are respectively formed on sixth to thirteenth metal electrical wire layer  27   f  to  27   m . After carrying out process step for the purpose of obtaining the patterned configuration as shown in  FIG. 2   e , process step for forming a second group of metal electrical wires including metal electrical wire layers  29   a  to  29   f  is performed as shown in  FIG. 2   g.    
   In  FIG. 2   g , first metal electrical wire layer  29   a  and second metal electrical wire layer  29   b  are formed so that these metal electrical wire layers  29   a  and  29   b  may pass on edge parts of both left and right portions of a cell formation region  21  to a vertical direction. First metal electrical wire layer  29   a  and second metal electrical wire layer  29   b  function as power supply ground VSS. Third and fourth metal electrical wire layers  29   c  and  29   d  are formed in order to function as a pair of read bit line RB and /RBB. Also, third and fourth metal electrical wire layers  29   e  and  29   f  are separated from each second at a predetermined distance between first and second metal electrical wire layers  29   a  and  29   b  so that these metal electrical wire layers  29   c  and  29   d  may face. Fifth and sixth metal electrical wire layers  29   e  and  29   f  are formed, for the purpose of functioning as a pair of write bit lines WB and /WBB, so that third and fourth metal electrical wire layers  29   c  and  29   d  are separated from each second at a predetermined distance between third and fourth metal electrical wire layers  29   c  and  29   d  with a shape of an inverse face of these metal electrical wire layers  29   e  and  29   f  On any end of first and second metal electrical wire layers are second plurality of via holes  30 , for the purpose of contacting with power supply ground VSS as known in  FIG. 2   f . Further, a third group of metal electrical wires including metal electrical wire layers  31   a  to  31   c  are formed in a horizontal direction as known in  FIG. 2   g.    
   In  FIG. 3   c , tenth electrical wire layer  27   j  and twelfth electrical wire layer  27   l  of the first metal electrical wire group are electrically coupled through first via holes to first electrical wire layer  29   a  of the second metal electrical wire group. Eleventh electrical wire layer  27   k  and thirteenth electrical wire layer  27   m  of the first metal electrical wire group are electrically contacted through first via holes with second electrical wire layer  29   b  of the second metal electrical wire group. Eighth electrical wire layer  27   h  of the first metal electrical wire group are electrically contacted through first via holes with third electrical wire layer  29   c  of the second metal electrical wire group. Ninth electrical wire layer  27   i  of the first metal electrical wire group are electrically contacted through first via holes with fourth electrical wire layer  29   d  of the second metal electrical wire group. Sixth electrical wire layer  27   f  of the first metal electrical wire group are electrically contacted through first via holes with fifth electrical wire layer  29   e  of the second metal electrical wire group. Seventh metal electrical wire layer  27   g  of the first metal electrical wire group are electrically contacted through first via holes with sixth electrical wire layer  29   f  of the second metal electrical wire group. All first to sixth metal electrical wire layers  29   a  to  29   f  have a vertical extension. 
   First and second electrical wire layers  29   a  and  29   b  of the second metal electrical wire group are electrically contacted through first via holes with first electrical wire layer  31   a  of the third metal electrical wire group. First metal electrical wire layer  31   a  has a horizontal extension. As a write global word line GWL_W second metal electrical wire layer  31   b  of the third metal electrical wire group is utilized. Third metal electrical wire layer  31   c  of the third metal electrical wire group is utilized as a read global word line GWL_R. Second metal electrical wire layer  31   b  and third metal electrical wire layer  31   c  of the third metal electrical wire group are separated from each second at a predetermined horizontal distance. Configurations shown in  FIG. 3   a  to  FIG. 3   c  are an original patterned configuration in which all layers between first layer and second successive layer are overlapped. However, it is difficult to be distinct from a boundary of various regions in case of the show of the overlapped configuration within  FIG. 3   a  to  FIG. 3   c . Therefore, the overlapped configuration is not shown in  FIG. 3   a  to  FIG. 3   c.    
     FIG. 4   a  to  FIG. 4   c  are patterned layout configuration diagrams for explaining process steps of other embodiment of a two-port SRAM according to a prior art invention. In other embodiment of the prior art two-port SRAM, a long axis of active regions for forming first and second load transistors TL 1  and TL 2  is a vertical direction. 
   In  FIG. 4   a , an N type well region  42  is formed on first part of a cell formation region  41  in order to define first and second load transistors TL 1  and TL 2 . First and second active regions  44   a  and  44   b  is formed so that these active regions  44   a  and  44   b  are separated from each second within cell formation region  41 . A vertical direction of these active regions  44   a  and  44   b  is a long axis. In second region except the N-type well region  42  in the cell formation region  41  which is a P-type well region, third and fourth active regions  44   c  and  44   d  which face each second are formed by meeting at least first extension portion to a perpendicular direction from an intersection between a long axis of a horizontal direction and a long axis of a vertical direction. Also, fifth active region  44   e  is formed on a separation region of first and second active regions  44   a  and  44   b.    
   Sixth and seventh active regions  44   f  and  44   g  are respectively formed on left and right lower portions of third and fourth active regions  44   c  and  44   d . A first metal electrode layer  45   a  is formed in order to be utilized as gate electrodes of first load transistor TL 1 , first write drive transistor /WTD 1 , and first read drive transistor RTD 1 . First metal electrode layer  45   a  has a configuration in which a central portion of first active region  44   a  is passed on in a vertical direction and at least two portions of third active regions  44   c  are passed on. Second metal electrode layer  45   b  is formed so that a central portion of second active region  44   b  is passed on in a horizontal direction and at least two portions of fourth active regions  44   d  are passed on. As gate electrodes of second load transistor TL 2 , second write drive transistor WTD 2 , and second read drive transistor RTD 2  functions second metal electrode layer  45   b . Third metal electrode layer  45   c  is formed in order to be utilized as gate electrodes of first and second write access transistors WTA 1  and WTA 2 . Fifth metal electrode layer  45   d  is formed in order to be utilized as gate electrodes of first and second read access transistors RTA 1  and RTA 2 . A plurality of contact regions  46  are formed on first to seventh active regions  44   a  to  44   g  of which any portion are not passed on by first to fourth metal electrode layers  45   a  to  45   d  or on first to fourth metal electrode layers  45   a  to  45   d . Fifth active regions  44   e  is formed in order to define a bias of the N-type well region  42 . 
   In  FIG. 4   b , first metal electrical wire layer  47   a  is electrically contacted with first electrodes of first and second load transistor TL 1  and TL 2 . A electrical connection of gate electrodes of first load transistor TL 1 , first write drive transistor WTD 1 , and read drive transistor RTD 1  and first common node CN 1  are made by second metal electrical wire layer  47   b . Third metal electrical wire layer  47   c  causes second common node CN 2  to make an electrical connection of gate electrodes of second load transistor TL 2 , second write drive transistor WTD 2 , and second read drive transistor RTD 2 . Fourth metal electrical wire layer  47   d  which is a horizontal extension, is formed in order to electrically contact with gate electrodes of first and second write access transistor WTA 1  and WTA 2 . In order to electrically contact with gate electrodes of first and second read access transistors RTA 1  and RTA 2 , fifth metal electrical wire layer  47   e  is formed. Sixth and seventh metal electrical wire layer  47   f  and  47   g  are formed in order to electrically contact with first electrodes of first and second write access transistors WTA 1  and WTA 2 . Eighth and ninth metal electrical wire layers  47   h  and  47   i  are formed in order to electrically contact with first electrodes of first and second read access transistors RTA 1  and RTA 2 . With third common node CN 3  of first write drive transistor WTD 1  and first read drive transistor RTD 1  is electrically contacted tenth metal electrical wire layer  47   j . Eleventh metal electrical wire layer  47   k  is formed in order to electrically contact with fourth common node CN 4  of second write drive transistor WTD 2  and second read drive transistor RTD 2 . Twelfth and thirteenth metal electrical wire layers  47   l  and  47   m  are formed in order to contact with power supply ground VSS. First plurality of via holes are respectively formed on sixth to thirteenth metal electrical wire layers  47   f  to  47   m . First metal electrical wire layer of first metal electrical wire group has a first and second active regions  44   a  and  44   b  of which a long axis is extended to a vertical direction. Source and drain electrodes are positioned at the same layer as fifth active region  44   e , thereby having a straight and vertical extension. 
   In  FIG. 4   c , first metal electrical wire layer  49   a  of second metal electrical wire group is formed so that its electrical wire layers  49   a  is contacted through first via holes with tenth and twelfth metal electrical wire layers  47   j  and  47   l  of first metal electrical wire group to a vertical direction. Second metal electrical wire layer  49   b  of second metal electrical wire group is formed so that its electrical wire layers  49   b  is contacted through first via holes with eleventh and thirteenth metal electrical wire layers  47   k  and  47   m  of first metal electrical wire group to a vertical direction. Third metal electrical wire layer  49   c  of second metal electrical wire group is formed so that its electrical wire layers  49   c  is contacted through first via holes with eighth metal electrical wire layer  47   h  of first metal electrical wire group to a vertical direction. Fourth metal electrical wire layer  49   d  of second metal electrical wire group is formed so that its electrical wire layers  49   d  is contacted through first via holes with ninth metal electrical wire layer  47   i  of first metal electrical wire group to a vertical direction. Fifth metal electrical wire layer  49   e  of second metal electrical wire group is formed so that its electrical wire layers  49   e  is contacted through first via holes with sixth metal electrical wire layer  47   f  of first metal electrical wire group to a vertical direction. Sixth metal electrical wire layer  49   f  of second metal electrical wire group is formed so that its electrical wire layers  49   f  is contacted through first via holes with seventh metal electrical wire layer  47   g  of first metal electrical wire group to a vertical direction. First metal electrical wire layer  51   a  of third metal electrical wire group is formed so that its electrical wire layers  51   a  is contacted through second via holes with first and second metal electrical wire layers  49   a  and  49   b  of second metal electrical wire group to a horizontal direction. As a write global word line GWL_W second metal electrical wire layer  51   b  of the third metal electrical wire group is utilized. Third metal electrical wire layer  51   c  of the third metal electrical wire group is utilized as a read global word line GWL_R. 
   In the above-described SRAM, each electrode at the load transistors included in first unit cell and in second unit cell neighbored to the corresponding first unit cell is mutually connected to power supply source line, thereby being happened at the same time at in-operation of all unit cells that are linked to power supply line VCCL. Also, common electrodes of write drive transistor and read drive transistor in every unit cell are electrically connected to power supply ground VSS, such that a problem is happened at the same time at all unit cells that are linked to power supply ground VSS. 
   Further, the conventional SRAM cell had the second problem that occupation region of a load transistor for obtaining a loading effect is narrow in its width because the width of the load transistor is extended to a vertical direction, resulting in degrading its trust and decreasing its operation speed. 
   SUMMARY OF THE INVENTION 
   Accordingly, an object of the present invention is to provide a multi-port SRAM which can reduce an occupation area of first unit cell on a substrate. 
   Other object of the present invention is to provide a multi-port SRAM which increase an operation speed. 
   To achieve the above objects, a multi-port SRAM according to the present invention in 2-port static random access memory comprising a first plurality of active regions which are separated from each second within a cell formation region, a first plurality of metal electrode layers which are respectively passed on the first plurality of active regions, and a power supply source which is electrically contacted with first plurality of the metal electrode layers, wherein the metal electrode layers included in first unit cell and in second unit cell neighbored to the corresponding first unit cell of the first plurality of metal electrode layers are commonly connected to the power supply source, having the improvements comprise: a second plurality of active regions formed within the cell formation region, and a second plurality of metal electrode layers to be passed on second plurality of the active regions and to be independently and separately connected to the power supply source, wherein the independence and separation of the connection to the power supply source is between the metal electrode layers included in first unit cell in second plurality of the metal electrode layers and the metal electrode layers included in the second unit cell neighbored to the corresponding first unit cell in second plurality of the metal electrode layers. The upper portion of second plurality of the active regions are respectively and commonly contacted with a write word line and the lower portion of second plurality of the active regions are respectively and commonly contacted with a read word line, only in the first unit cell regardless of second unit cell neighbored to the corresponding first unit cell. 
   Further, a multi-port SRAM according to the present invention having a plurality of unit cells each includes: a first pair of first and second load transistors having their gate electrode electrodes respectively formed by first and second metal electrode layers on first and second active regions, their first electrodes for being electrically contacted with a power supply voltage, and their second electrodes for being electrically connected to a first pair of first and second common nodes only in first unit cell, regardless of second unit cell neighbored to the corresponding first unit cell; a first pair of first and second write drive transistors having their gate electrodes and first electrodes for being electrically and respectively connected to the corresponding first of first pair of first and second common nodes; a first pair of first and second read drive transistors having their first electrodes for being electrically and respectively connected to the corresponding first of a second pair of third and fourth common nodes, and their gate electrodes for being electrically and respectively connected to the corresponding first of first pair of first and second common nodes; a first pair of first and second write access transistors having their first electrodes for being electrically and respectively connected to the corresponding first of first pair of common nodes, their gate electrodes for being electrically and respectively connected to the corresponding first of second electrodes of the pair of first and second load transistors, and their second electrodes for being electrically and respectively connected to the corresponding first of a pair of write bit lines; a first pair of first and second read access transistors having their gate electrodes for being electrically and respectively connected to the corresponding first of a pair of read word lines, their first electrodes for being electrically and respectively connected to the corresponding first of the pair of first and second read drive transistors, and their second electrodes for being electrically and respectively connected to the corresponding first of a pair of read bit lines; a plurality of active regions formed within the cell formation region; a plurality of metal electrode layers to be passed on the active regions and to be independently and separately connected to the power supply source; a plurality of metal electrical wire groups having: first metal electrical wire group consisting of first metal electrical wire layer for being electrically contacted with the contact regions of said power supply voltage and with first electrodes of first and second load transistors; second and third metal electrical wire layers for being respectively coupled to the corresponding contact region of the write word lines; fourth metal electrical wire layer for being electrically connected to first to third contact regions for first common node; sixth and seventh metal electrical wire layers for being electrically connected to the contact regions of the pair of write bit lines; eighth and ninth metal electrical wire layers for being electrically connected to the corresponding contact region of the read word lines; tenth metal electrical wire layer for being electrically connected to the contact regions of the power supply ground and is extended to the upper side of third active region; and eleventh and twelfth metal electrical wire layers for being electrically connected to the contact regions of the pair of the read bit lines, a second metal electrical wire group consisting of first metal electrical wire layer for being electrically contacted with first metal electrical wire layer of first metal electrical wire group and for being utilized as said power supply voltage; second metal electrical wire layer for being electrically contacted with second and third metal electrical wire layers of first metal electrical wire group; third to fifth metal electrical wire layers for being electrically contacted with second and third metal electrical wire layers of first metal electrical wire group; third to fifth metal electrical wire layers for being electrically contacted with sixth, seventh, and tenth metal electrical wire layers of first metal electrical wire group; sixth metal electrical wire layer for being electrically contacted with eighth and ninth metal electrical wire layers of first metal electrical wire group and for functioning as the corresponding first of the read word lines; and seventh and eighth metal electrical wire layers for being separated from each second and for being electrically contacted with eleventh and twelfth metal electrical wire layers of first metal electrical wire group, and a third metal electrical wire group consisting of first and second metal electrical wire layers for being utilized as the pair of the write bit lines and for being electrically contacted with third and fourth metal electrical wire layers of second metal electrical wire group via a second plurality of via holes; third and fourth metal electrical wire layers for being utilized as the pair of read bit lines and for being electrically contacted with seventh and eighth metal electrical wire layers of second metal electrical wire group; fifth metal electrical wire layers for functioning as the power supply ground and for being electrically contacted with fifth metal electrical wire layer of second metal electrical wire group. 
   It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a circuit configuration diagram of one embodiment according to a conventional two-port SRAM. 
       FIG. 2   a  to  FIG. 2   i  are patterned layout configuration diagrams for explaining process steps of one embodiment of a two-port SRAM according to a prior art invention. 
       FIG. 3   a  to  3   c  are patterned layout configuration diagrams for explaining process steps of one embodiment of a two-port SRAM according to a prior art invention, after forming a metal electrical wire. 
       FIG. 4   a  to  FIG. 4   c  are patterned layout configuration diagrams for explaining process steps of second embodiment of a two-port SRAM according to a prior art invention. 
       FIG. 5  is a circuit diagram for explaining process steps of first embodiment of a multi-port SRAM according to the present invention. 
       FIG. 6   a  to  FIG. 6   i  are layout schematic diagrams for explaining process steps of first embodiment of a multi-port SRAM according to the present invention. 
       FIG. 7   a  to  FIG. 7   c  are layout schematic diagrams for explaining process steps of first embodiment of a multi-port SRAM according to the present invention after forming a metal electrical wire. 
       FIG. 8   a  to  FIG. 8   c  are layout schematic diagrams for explaining process steps of second embodiment of a multi-port SRAM according to the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Best preferred embodiments of the present invention will now be described with reference to the accompanying drawings. In the accompanying drawings, the same parts as those of the prior art SRAM denote the same symbols as those of the prior art SRAM. 
     FIG. 5  is a circuit configuration diagram of one embodiment of a multi-port SRAM according to the present invention. 
   In  FIG. 5 , symbol RB denotes a read bit line, symbol /RBB an inverted read bit line, symbol WB a write bit line, symbol /WBB an inverted write bit line, symbol WWL a write word line, symbol RWL a read word line, symbol WTA a write access transistor, symbol RTA a read access transistor, symbol CN a common node, symbol TL load transistor, symbol WTD a write drive transistor, symbol RTD a read drive transistor, symbol VCC a power supply voltage and symbol VSS denotes a power supply ground. 
   In  FIG. 5 , a read bit line RB, an inverted read bit line /RBB, a write bit line WB, and an inverted write bit line /WBB included in first unit cell are arranged in a vertical direction. And in the upper part of first unit cell, a power supply voltage VCC and a write word line WWL are arranged in a horizontal direction. In the lower part of first unit cell, power supply ground VSS and a read word line RWL are arranged in a horizontal direction. 
   Gate electrodes of write access transistors WTA 1  and WTA 2  included in second unit cell neighbored to the corresponding first unit cell are electrically connected to a write word line WWL, and first electrodes of write access transistors WTA 1  and WTA 2  are electrically connected to a pair of write bit lines WB and /WBB. Gate electrodes of read access transistors RTA 1  and RTA 2  are commonly connected to a read word line RWL, and first electrodes of read access transistors RTA 1  and RTA 2  are connected to a pair of read bit lines RB and /RBB. 
   Gate electrodes of first and second load transistors TL 1  and TL 2  are electrically connected to a first pair of common nodes CN 1  and CN 2 , and first electrodes of first and second load transistors TL 1  and TL 2  are electrically connected to a power supply voltage VCC, independently from second unit cell neighbored to the corresponding first unit cell. Gate electrodes of first write access transistor WTD 1  and first read access transistor RTD 1  are electrically connected to second common node CN 2  and in series to first load transistor TL 1 . Gate electrodes of second write access transistor WTD 2  and second read access transistor RTD 2  are electrically connected to first common node CN 1  and in series to second load transistor TL 2 . 
   In  FIG. 5 , second electrodes of first load transistor TL 1  and first write access transistor WTA 1 , and first electrode of first write drive transistor WTD 1  are electrically connected to first common node CN 1 . And second electrodes of second load transistor TL 2  and second write access transistor WTA 2 , and first electrode of second write drive transistor WTD 2  are electrically connected to second common node CN 2 . Also, second electrodes of first and second write drive transistors WTD 1  and WTD 2  and first electrodes of first and second read drive transistors RTD 1  and RTD 2  are electrically connected to a power supply ground VSS, independently from second unit cell neighbored to the corresponding first unit cell. Further, the second electrodes of first and second read access transistors RTA 1  and RTA 2  are mutually connected to the second electrodes of first and second read drive transistors RTD 1  and RTD 2 . Wherein first and second load transistors TL 1  and TL 2  are PMOS transistors, and first second write access transistors WTA 1  and WTA 2 , first and second read access transistors RTA 1  and RTA 2 , first and second write drive transistors WTD 1  and WTD 2 , and first and second read drive transistors RTD 1  and RTD 2  are respectively a NMOS transistor. 
   Read and write operations of a multi-port SRAM according to the present invention will be in detail described now. 
   Supposing that a level of data stored in a unit cell is high, level of an electrical signal at first common node CN 1  is high, and therefore a state of second load transistor TL 2  is a turn-off. At this time, states of second write drive transistor WTD 2  and second read drive transistor RTD 2  are respectively a turn-on. Also, level of an electrical signal at first common node CN 2  is low and therefore a state of first load transistor TL 1  is a turn-on and states of first write drive transistor WTD 1  and first read drive transistor RTD 1  are respectively a turn-off. 
   At this situation, when a level of an electrical signal “high” is written into a unit cell a level of an electrical signal at a write word line WWL is high and a level of an electrical signal at a read word line RWL is low, and therefore first and second write access transistors WTA 1  and WTA 2  are turned on and first and second read access transistors RTA 1  and RTA 2  are turned off. Successively, a level of an electrical signal at a write bit line WB is low and a level of an electrical signal at an inverted write bit line /WBB is high. At this time, a level of an electrical signal at first common node CN 1  is low via first write access transistor WTA 1  because a current driving function of first load transistor TL 1  is worse than that of first write access transistor WTA 1 , and therefore second load transistor TL 2  is turned on and second read drive transistor RTD 2  is turned off. Resultantly, a level of an electrical signal at second common node CN 2  is high, first load transistor TL 1  is turned off, and first write drive transistor WTD 1  and first read drive transistor RTD 1  are continue to be turned on. And level of data to be stored in a unit cell is “0”. A completion of a write operations of a multi-port SRAM according to the present invention is made. In case of a read operations of a multi-port SRAM according to the present invention, if a unit cell is selected in order to read-out a stored data “0” from a selected unit cell of a cell array a level of a read word line RWL is high and a level of a write word line WWL is low. Therefore, first and second read access transistors RTA 1  and RTA 2  are turned on and first and second write access transistors WTA 1  and WTA 2  are turned off A level of an electrical signal at first common node CN 1  is low and a level of an electrical signal at second common node CN 2  is high because a level of data stored in a cell is “0”. Also, second load transistor TL 2  is turned on and second write drive transistor WTD 2  and second read drive transistor RTD 2  are continue to be turned off. And first write drive transistor WTD 1  and first read drive transistor RTD 1  are continue to be turned on. Trough first read access transistor RTA 1  and first read drive transistor RTD 1  a read bit line RB is low. By the turned-off state of second read drive transistor RTD 2 , a level of an inverted read bit line /RBB is high. The stored data “0” from the selected unit cell of a cell array is red-out by sensing a difference of voltages on a pair of read bit lines RB and /RBB. 
     FIG. 6   a  to  FIG. 6   i  are schematic layout diagrams for explaining process steps of one embodiment of a multi-port SRAM according to the present invention. 
   In  FIG. 6   a , an N-type well region  62  is formed within first region of a cell formation region  61  in order to function as a pair of first and second load transistors TL 1  and TL 2 . Some region except the N-type well region  62  within the cell formation region  61  indicate a P-type well region. 
   As known from  FIG. 6   b , a formation of first to thirteen active regions  64   a  to  64   m  is made by a separation of second region (not shown) from a field region  63  in the cell formation region  61 . Of first to thirteen active regions  64   a  to  64   m , first, second and fourth active regions  64   a ,  64   b , and  64   d  are independently separated from each second and second regions except the above active regions  64   c ,  64   e ,  64   f ,  64   g ,  64   h ,  64   i ,  64   j ,  64   k ,  64   l , and  64   m  are dependently integrated from each second. First metal electrode layer  65   a  has a configuration in which its two portions are perpendicular to each second and at least first portion of first, third, and sixth active regions  64   a ,  64   c , and  64   f  are passed on. Second metal electrode layer  65   b  is formed so that it may have a symmetrically mutual face configuration with first metal electrode layer  65   a  and at least first portion of second, third, seventh active regions  64   b ,  64   c , and  64   g  may be passed on. Third metal electrode layer  65   c  is formed so that any portion of third active region  64   c  is passed on. Fourth metal electrode layer  65   d  is formed so that any portion of third active region  64   c  may be passed on. Fifth metal electrode layer  65   e  is formed so that any portion of tenth active region  64   j  may be passed on. Sixth metal electrode layer  65   f  is formed so that it may have a symmetrically mutual face configuration with fifth metal electrode layer  65   e  and at least any portion of eleventh active regions  64   k  may be passed on. 
   Using the metal electrode layers, the impurities regions (not shown) are formed within the surface of exposed active regions. 
   In  FIG. 6   d , for the purpose of selectively exposing the impurities regions or the metal electrode layers, a plurality of contact regions  66  are formed. Over the plurality of contact regions  66  is formed an interleave layer insulation which is selectively etched. 
   At this situation on the completion of formation of the contact regions, entire layout configuration will be described below. 
   As shown in  FIG. 7   a , an N-type well region  62  is formed within some of a cell formation region  61  in order to function as a pair of first and second load transistors TL 1  and TL 2 . First and second active regions  64   a  and  64   b  have their long axes which are perpendicular to a vertical direction in the cell formation region  61  and are separated from each second at an opposition. On the central portion of P type well region which is second region except the N type well region  62  within the cell formation region  61  are third active region  64   c  which has its long axis in a horizontal direction. Also, fourth active region  64   d  is a separation region between first and second active regions  64   a  and  64   b . Fifth active region  64   e  is formed to be extended from the central lower portion of third active region  64   c  to a vertical direction. At the lower portion of fifth active region  64   e , sixth and eighth active regions  64   f  and  64   h  are respectively extended to its left side in a horizontal direction and seventh and ninth active regions  64   g  and  64   i  are respectively extended to its right side in a horizontal direction. Tenth and twelfth active regions  64   j  and  64   l  and eleventh and thirteen active regions  64   m  and  64   k  have a symmetrically face configuration at an opposition. These active regions  64   j  and  64   l  are respectively extended to their lower portions to be vertical against eighth active region  64   h . These active regions  64   m  and  64   k  are respectively extended to their lower portions to be vertical against seventh active region  64   g . As gate electrodes of first load transistor TL 1 , first write drive transistor WTD 1 , and first read drive transistor RTD 1  is utilized first metal electrode layer  65   a  which includes a first part to pass on the central of first active region  64   a  in a horizontal direction and a second part to pass on the first part in vertical direction. Second metal electrode layer  65   b  has a face configuration against first metal electrode layer  65   a . As gate electrodes of second load transistor TL 2 , second write drive transistor WTD 2 , and second read drive transistor RTD 2  is utilized second metal electrode layer  65   b  which passes on the central of second active region  64   b  in a horizontal direction and cross-passes on third and sixth active regions  64   c  and  64   f  in vertical direction. Third and fourth metal electrode layers  65   c  and  65   d  are utilized as gate electrodes of first and second write access transistors WTA 1  and WTA 2  which cross-passes third active access transistor  64   c  through their both sides on basis of first and second metal electrode layers  65   a  and  65   b . Fifth and sixth metal electrode layers  65   e  and  65   f  are utilized as gate electrode electrodes of first and second access transistors RTA 1  and RTA 2  which have a configuration in which tenth and eleventh active regions  64   j  and  64   k  are cross-passed in a horizontal direction. First to third contact regions CT 11 , CT 12 , and CT 13  for first common node CN 1  are respectively formed on third active region  64   c  of first electrodes of third metal electrode layer  65   c , the upper portion of second metal electrode layer  65   b , first active region  64   a  of second electrode of first metal electrode layer  65   a , and the contact region of a power supply voltage VCC formed on first and second active regions  64   a  and  64   b  and fourth active region  64   d  of first and second metal electrode layers  65   a  and  65   b . First to third contact regions CT 21 , CT 22 , and CT 23  for second common node CN 2  are respectively formed on third active region  64   c  of first electrodes of fourth metal electrode layers  65   d , the upper portion of first metal electrode layer  65   a , and second active region  64   b  of second electrode of second metal electrode layer  65   b . Contact regions of a pair of write bit lines WB and /WBB are respectively formed on third active region  64   c  of second electrodes of third and fourth metal electrode layers  65   c  and  65   d.    
   Contact regions of a write word line WLL are respectively positioned at the edge of the cell formation region  61  and are respectively formed on the end portion of third and fourth metal electrode layers  65   c  and  65   d . Contact regions of a power supply ground VSS are formed on fifth active region  64   e . Contact regions of a read word line RWL are respectively positioned at the edge of the cell formation region  61  and are respectively formed on the end portion of fifth and sixth metal electrode layers  65   e  and  65   f  Contact regions of a pair of read bit lines RB and /RBB are respectively formed on twelfth and thirteen active regions  64   l  and  64   m  of first electrodes of fifth and sixth metal electrode layers  65   e  and  65   f  Fourth active region  64   d  is a region for mediating a well bias of the N-type well region. On the completion of the process step of the above described layout configuration as shown in  FIG. 7   a , first metal electrical wire layer  67   a  of first metal electrical wire group for functioning as a power supply voltage VCC and second to twelfth metal electrical wire layers  67   b  to  67   l  of first metal electrical wire group are formed as shown in  FIG. 6   e.    
   In  FIG. 6   f , a plurality of via holes are formed on the active regions and the metal electrical wire layers of first metal electrical wire group. 
   In  FIG. 7   b , first metal electrical wire layer  67   a  of first metal electrical wire group is electrically contacted with contact regions of a power supply voltage VCC of fourth active region  64   d  and first electrodes of first and second load transistors TL 1  and TL 2 . Second and third metal electrical wire layer  67   b  and  67   c  of first metal electrical wire group are respectively coupled to a contact region of a write word line WWL. Fourth metal electrical wire layer  67   d  of first metal electrical wire group is electrically connected to first to third contact regions CT 11 , CT 12 , and CT 13  for first common node CN 1 . Sixth and seventh metal electrical wire layers  67   f  and  67   g  of first metal electrical wire group are electrically connected to contact regions of a pair of write bit lines WB and /WBB. Eighth and ninth metal electrical wire layers  67   h  and  67   j  of first metal electrical wire group are electrically connected to contact region of a read word line RWL. Tenth metal electrical wire layer  67   j  of first metal electrical wire group is electrically connected to contact regions of a power supply ground VSS and is extended to the upper side of third active region  64   c . Eleventh and twelfth metal electrical wire layers  67   k  and  67   l  of first metal electrical wire group are electrically connected to contact regions of a pair of read bit lines RB and /RBB. A first plurality of via holes  68  are formed on first to twelfth metal electrical wire layers  67   a  to  67   l  of first metal electrical wire group. After carrying out the process step of the above described layout configuration as shown in  FIG. 7   a , first to eighth metal electrical wire layers  69   a  to  69   h  of second metal electrical wire group for functioning as a power supply voltage VCC, a write word line WWL, and a read word line RWL are formed as shown in  FIG. 6   g . A second plurality of via holes  70  are formed on third to eighth metal electrical wire layers  69   c  to  69   h . Successively, first to sixth metal electrical wire layers  71   a  to  71   e  are formed in a vertical direction as shown in  FIG. 6   i.    
   In  FIG. 7   c , first metal electrical wire layer  69   a  of second metal electrical wire group is electrically contacted with first metal electrical wire layer  67   a  of first metal electrical wire group and is utilized as a power supply voltage VCC. Second metal electrical wire layer  69   b  of second metal electrical wire group is electrically contacted with second and third metal electrical wire layers  67   b  and  67   c  of first metal electrical wire group. Third to fifth metal electrical wire layer  69   c  to  69   e  of second metal electrical wire group are electrically contacted with sixth, seventh, and tenth metal electrical wire layers  67   f ,  67   g , and  67   j  of first metal electrical wire group. Sixth metal electrical wire layer  69   f  of second metal electrical wire group is electrically contacted with eighth and ninth metal electrical wire layers  67   h  and  67   i  of first metal electrical wire group for functioning as a read word line RWL. Seventh and eighth  69   g  and  69   h  are separated from each second and are electrically contacted with eleventh and twelfth. A second plurality of via holes  70  are formed on third, fourth, fifth, seventh, and eighth metal electrical wire layers  69   c ,  69   d ,  69   e ,  69   g , and  69   h.    
   First and second metal electrical wire layers  71   a  and  71   b  of third metal electrical wire group for being utilized as a pair of write bit lines WB and /WBB are electrically contacted with third and fourth metal electrical wire layers  69   c  and  69   d  of second metal electrical wire group via the second plurality of via holes. Third and fourth metal electrical wire layers  71   c  and  71   d  of third metal electrical wire group for being utilized as a pair of read bit lines RB and /RBB are electrically contacted with seventh and eighth metal electrical wire layers  69   g  and  69   h  of second metal electrical wire group. Fifth metal electrical wire layers  71   e  of third metal electrical wire group for functioning as a power supply ground VSS is electrically contacted with fifth metal electrical wire layer  69   e  of second metal electrical wire group. Configurations shown in  FIG. 7   a  to  FIG. 7   c  are an original patterned configuration in which all layers between first layer and second successive layer are overlapped. However, it is difficult to distinct from a boundary of various regions in case of the show of the overlapped configuration within  FIG. 7   a  to  FIG. 7   c . Therefore, the overlapped configuration is not shown in  FIG. 7   a  to  FIG. 7   c.    
     FIG. 8   a  to  FIG. 8   c  are schematic layout diagrams for explaining process steps of second embodiment of a multi-port SRAM according to the present invention. 
   In second embodiment of a multi-port SRAM according to the present invention, long axes of the active regions for functioning as first and second load transistors TL 1  and TL 2  are a horizontal direction. Also, only a vertical direction is a direction at which first and second metal electrical wire layers  85   a  and  85   b  pass on the active regions. In first embodiment of a multi-port SRAM according to the present invention, however, any portions of which the metal electrical wire layers pass on the active regions are formed in a vertical direction and a perpendicular direction to a horizontal direction. Only a vertical direction at which the metal electrical wire layers pass on the active regions is embodied in second embodiment of a multi-port SRAM according to the present invention. 
   As known in  FIG. 8   a , an N-type well region  82  is formed within some of a cell formation region  81  in order to define regions of a pair of first and second load transistors TL 1  and TL 2 . First and second active regions  84   a  and  84   b  have their long axes which are parallel with a horizontal direction in the cell formation region  81  and are separated from each second at an opposition. On the central portion of P-type well region which is second region except the N type well region  82  within the cell formation region  81  are third active region  84   c  which has its long axis in a horizontal direction. Also, fourth active region  84   d  is a separation region between first and second active regions  84   a  and  84   b . Fifth active region  84   e  is formed to be extended from the central lower portion of third active region  84   c  to a vertical direction. At the lower portion of fifth active region  84   e , sixth and eighth active regions  84   f  and  84   h  are respectively extended to its left side in a horizontal direction and seventh and ninth active regions  84   g  and  84   i  are respectively extended to its right side in a horizontal direction. Tenth and twelfth active regions  84   j  and  84   l  and eleventh and thirteen active regions  84   m  and  84   k  have a symmetrically face configuration at an opposition. These active regions  84   j  and  84   l  are respectively extended to their lower portions to be vertical against eighth active region  84   h . These active regions  84   m  and  84   k  are respectively extended to their lower portions to be vertical against seventh active region  84   g . As gate electrodes of first load transistor TL 1 , first write drive transistor WTD 1 , and first read drive transistor RTD 1  is utilized first metal electrode layer  85   a  which includes a first part to pass on the central of first active region  84   a  in a horizontal direction, a second part to be extended to the first part in a horizontal direction, and a third part to be passed on perpendicularly to the second part in a vertical direction. Second metal electrode layer  85   b  has a face configuration against first metal electrode layer  85   a . As gate electrodes of second load transistor TL 2 , second write drive transistor WTD 2 , and second read drive transistor RTD 2  is utilized second metal electrode layer  85   b  which passes on the central of second active region  84   b  in a horizontal direction and cross-passes on third and sixth active regions  84   c  and  84   f  in a vertical direction. Third and fourth metal electrode layers  85   c  and  85   d  are utilized as gate electrodes of first and second write access transistors WTA 1  and WTA 2  which cross-passes third active access transistor  84   c  through their both sides on basis of first and second metal electrode layers  85   a  and  85   b . Fifth and sixth metal electrode layers  85   e  and  85   f  are utilized as gate electrodes of first and second access transistors RTA 1  and RTA 2  and have a configuration in which tenth and eleventh active regions  84   j  and  84   k  are cross-passed in a horizontal direction. 
   First to third contact regions CT 11 , CT 12 , and CT 13  for first common node CN 1  are respectively formed on third active region  84   c  of first electrodes of third metal electrode layer  85   c , the upper portion of second metal electrode layer  85   b , first active region  84   a  of second electrode of first metal electrode layer  85   a , and the contact region of a power supply voltage VCC formed on first and second active regions  84   a  and  84   b  and fourth active region  84   d  of first and second metal electrode layers  85   a  and  85   b . First to third contact regions CT 21 , CT 22 , and CT 23  for second common node CN 2  are respectively formed on third active region  84   c  of first electrodes of fourth metal electrode layers  85   d , the upper portion of first metal electrode layer  85   a , and second active region  84   b  of second electrode of second metal electrode layer  85   b . Contact regions of a pair of write bit lines WB and /WBB are respectively formed on third active region  84   c  of second electrodes of third and fourth metal electrode layers  85   c  and  85   d . Contact regions of a write word line WLL are respectively positioned at the edge of the cell formation region  61  and are respectively formed on the end portion of third and fourth metal electrode layers  85   c  and  85   d . Contact regions of a power supply ground VSS are formed on fifth active region  84   e . Contact regions of a read word line RWL are respectively positioned at the edge of the cell formation region  81  and are respectively formed on the end portion of fifth and sixth metal electrode layers  85   e  and  85   f  Contact regions of a pair of read bit lines RB and /RBB are respectively formed on twelfth and thirteen active regions  84   l  and  84   m  of first electrodes of fifth and sixth metal electrode layers  85   e  and  85   f . Fourth active region  84   d  is a region for mediating a well bias of the N-type well region. 
   Entire layout configuration of first metal electrical wire group is similar like those shown in  FIG. 7   b , but metal electrical wire laid out configuration for being electrically provided with a power supply voltage VCC are very different. This difference appears on that the metal electrode layers of first and second load transistors TL 1  and second formed on first and second active regions  84   a  and  84   b  are not positioned at the same horizontal direction as fourth active region  84   d  by the variation of a long axis of first and second active regions  84   a  and  84   b . Therefore, the metal electrical wire laid out configuration has a vertical part to be perpendicular to the edge of the cell formation region  81 . 
   In  FIG. 8   b , first metal electrical wire layer  87   a  of first metal electrical wire group is electrically contacted with contact regions of a power supply voltage VCC of fourth active region  84   d  and first electrodes of first and second load transistors TL 1  and TL 2 . Second and third metal electrical wire layers  87   b  and  87   c  of first metal electrical wire group are respectively coupled to a contact region of a write word line WWL. Fourth metal electrical wire layer  87   d  of first metal electrical wire group is electrically connected to first to third contact regions CT 11 , CT 12 , and CT 13  for first common node CN 1 . Sixth and seventh metal electrical wire layers  87   f  and  87   g  of first metal electrical wire group are electrically connected to contact regions of a pair of write bit lines WB and /WBB. Eighth and ninth metal electrical wire layers  87   h  and  87   j  of first metal electrical wire group are electrically connected to contact region of a read word line RWL. Tenth metal electrical wire layer  87   j  of first metal electrical wire group is electrically connected to contact regions of a power supply ground VSS and is extended to the upper side of third active region  84   c . Eleventh and twelfth metal electrical wire layers  87   k  and  87   l  of first metal electrical wire group are electrically connected to contact regions of a pair of read bit lines RB and /RBB. A first plurality of via holes  88  are formed on first to twelfth metal electrical wire layers  87   a  to  87   l  of first metal electrical wire group. 
   In  FIG. 8   c , first metal electrical wire layer  89   a  of second metal electrical wire group is electrically contacted with first metal electrical wire layer  87   a  of first metal electrical wire group and is utilized as a power supply voltage VCC. Second metal electrical wire layer  89   b  of second metal electrical wire group is electrically contacted with second and third metal electrical wire layers  87   b  and  87   c  of first metal electrical wire group. Third to fifth metal electrical wire layer  89   c  to  89   e  of second metal electrical wire group are electrically contacted with sixth, seventh, and tenth metal electrical wire layers  87   f ,  87   g , and  87   j  of first metal electrical wire group. Sixth metal electrical wire layer  89   f  of second metal electrical wire group is electrically contacted with eighth and ninth metal electrical wire layers  87   h  and  87   i  of first metal electrical wire group for functioning as a read word line RWL. Seventh and eighth  89   g  and  89   h  are separated from each second and are electrically contacted with eleventh and twelfth metal electrical wire layers  87   h  and  87   i  of first metal electrical wire group. A second plurality of via holes  90  are formed on third, fourth, fifth, seventh, and eighth metal electrical wire layers  89   c ,  89   d ,  89   e ,  89   g , and  89   h.    
   First and second metal electrical wire layers  91   a  and  91   b  of third metal electrical wire group for being utilized as a pair of write bit lines WB and /WBB are electrically contacted with third and fourth metal electrical wire layers  89   c  and  89   d  of second metal electrical wire group via the second plurality of via holes. Third and fourth metal electrical wire layers  91   c  and  91   d  of third metal electrical wire group for being utilized as a pair of read bit lines RB and /RBB are electrically contacted with seventh and eighth metal electrical wire layers  89   g  and  89   h  of second metal electrical wire group. Fifth metal electrical wire layers  91   e  of third metal electrical wire group for functioning as a power supply ground VSS is electrically contacted with fifth metal electrical wire layer  89   e  of second metal electrical wire group. 
   In embodiments of a multi-port SRAM according to the present invention, a number of contact regions to be positioned at the same horizontal direction are limited to for example 6, rather than 4 or 5. Moreover, it is to obtain a necessary margin of a layout configuration on a cell array by the above limitation, or by making contact regions of a power supply ground VSS to be positioned at the lower of drive transistor within a cell formation region. Further, contact regions of a power supply voltage VCC and a power supply ground VSS included in first unit cell and in second unit cell neighbored to the corresponding first unit cell are independently formed by a unit cell of a cell array, thereby being happened only at in-operation of first unit cell, regardless of second unit cell neighbored to the corresponding first unit cell in case of the electrical disconnection of contact regions of the power supply source VCC and VSS to metal electrode layers within the corresponding first unit cell. 
   According to a multi-port SRAM of the present invention, obtainment of a necessary margin of a layout configuration on a cell array is to be able to reduce an occupation area of a memory cell on a substrate. A width of occupation region of load transistors is extended to a vertical direction, resulting in degrading its trust and decreasing its operation speed.