Abstract:
Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates in general to semiconductor fabrication techniques and more particularly to a method for minimizing defects in a semiconductor substrate due to ion implantation. 
       BACKGROUND 
       [0002]    In conventional semiconductor manufacturing processes, ion implantation into a substrate is typically performed through a thermal oxide layer. During ion implantation, oxygen atoms are likely to be driven into the silicon lattice of the substrate. This phenomenon, known in the industry as oxygen “knock on”, is responsible for current leakage into the substrate that may degrade operation. Thus, knock-on oxide provides a source for crystalline defects. To offset the effects of knock-on oxide, adequate thermal annealing with its inherent diffusion of impurities is typically performed to contain the defects within the dopant profile. 
         [0003]    Ion implantation also introduces substrate crystal damage, in which lattice atoms are knocked out of lattice sites, while at the same time a certain number of the newly-introduced atoms will likewise come to rest in positions outside the lattice positions. Such out-of-position phenomena are termed defects. A vacant lattice site is termed a vacancy defect, while an atom located at a non-lattice site is referred to as an interstitial defect. Another defect is the creation of amorphous silicon which must be annealed to return it to its crystalline state. The restorative method generally employed in the art consists of annealing the substrate, where heat is applied to the lattice to mildly energize the atoms, allowing them to work themselves back into the lattice structure and restoring the ion-implanted substrate to its pre-implant condition. 
       SUMMARY 
       [0004]    From the foregoing, it may be appreciated by those skilled in the art that a need has arisen to reduce defects introduced into a semiconductor substrate caused by ion implantation that would effect the operation of a device formed therein. In accordance with the present disclosure, there is provided a method for minimizing defects in a semiconductor substrate due to ion implantation that substantially eliminates or greatly reduces problems and limitations associated with conventional semiconductor fabrication processes. 
         [0005]    According to the present disclosure, a method for minimizing defects in a semiconductor substrate due to ion implantation is presented that includes providing a semiconductor substrate and forming an implant region in the semiconductor substrate. The semiconductor substrate is subjected to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions. The first anneal is at a lower temperature and longer duration than the second anneal. 
         [0006]    The present disclosure provides various technical advantages over devices made by conventional semiconductor fabrication processes. For example, one technical advantage is in the recrystallization of the semiconductor substrate after ion implantation. Another technical advantage is to suppress diffusion of implanted ions in the semiconductor substrate. Some of these technical advantages are shown and described in the following description. Embodiments described herein may enjoy some, all, or none of these advantages. Other technical advantages may be readily apparent to one skilled in the art from the following figures, description, and claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    For a more complete understanding of the present disclosure and the advantages thereof, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts in which: 
           [0008]      FIG. 1  illustrates a manufacturing process showing steps performed on a semiconductor substrate prior to and after ion implantation; 
           [0009]      FIGS. 2A-2E  illustrate the changes in the device structure as a result of each step of the process of  FIG. 1 ; 
           [0010]      FIGS. 3A and 3B  illustrate graphs of the oxygen concentration in a substrate after ion implantation comparing the process of  FIG. 1  to conventional processing and variations in the process; 
           [0011]      FIG. 4  illustrates an annealing process to minimize defects in a substrate due to ion implantation; 
           [0012]      FIG. 5  illustrates a graph showing different temperature and time parameters for the annealing processes; 
           [0013]      FIGS. 6A and 6B  illustrate graphs showing a concentration of boron and carbon atoms respectively resulting from the annealing process. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]      FIG. 1  illustrates manufacturing process  10  in creating a circuit element. Manufacturing process  10  shows steps performed on a semiconductor substrate prior to and after ion implantation.  FIG. 2A-2E  illustrate the changes in the device structure as a result of each step of process  10 . Process  10  may be part of a 90 nm or less CMOS technology using approximately 300 mm wafers. 
         [0015]    Process  10  begins in block  12  by manufacturing or providing a semiconductor substrate  100 . A mask alignment mark may be formed in substrate  100 . During conventional processing steps, a thermal oxide layer is typically formed on the surface of the substrate for protection. Ion implantation is then performed through this thermal oxide layer, resulting in the knock-on oxide phenomenon. For the present application, a native oxide layer  102  is formed on the surface instead of the thermal oxide layer of conventional processes. Native oxide layer  102  is formed on substrate  100  in block  14  by dipping substrate  100  in a chemical wet bath. 
         [0016]    The chemical wet bath may include hydrogen peroxide H 2 O 2  or nitric acid HNO 3 . Solutions with two or more compounds may also be used for the chemical wet bath, such as HCl/H 2 O 2 /H 2 O. An example concentration for the solution may be 1 part HCl, two parts H 2 O 2 , and 110 parts H 2 O. The substrate  100  may be dipped in the chemical wet bath for a period sufficient to grow at least a monolayer of native oxide on substrate  100 . The time and temperature parameters to perform such growth may be 5 to 20 minutes at a temperature of 25° C. to 70° C. The time and temperature parameters for the chemical wet bath may be adjusted as desired. Prior to the chemical wet bath, substrate  100  may be subjected to hydrofluoric acid HF cleaning and then rinsed. 
         [0017]    The result of the chemical wet bath is the growth of a thin layer  102  of native oxide. This native oxide layer  102  may have a thickness of approximately 1 nm and provides protection to the surface of substrate  100 . Native oxide provides better properties than thermal oxide to reduce the effects of knock-on oxide occurring as a result of ion implantation. 
         [0018]    After the chemical wet bath dip, process  10  continues at block  16  where ion implantation is performed through native oxide layer  102  to create one or more implant regions  104  in substrate  100 . Substrate  100  may be subject to the HF clean and rinse and the chemical wet bath dip prior to the separate formation of each implant region  104 . 
         [0019]    In order to further reduce the effect of knock-on oxide, process  10  continues at block  18  with an anisotropic silicon etch to remove an amount of the surface of substrate  100 . The majority of the oxygen atoms driven into the silicon lattice of the substrate by ion implantation are near the surface of substrate  100 . Etching a small portion of the surface of substrate  100  will eliminate those oxygen atoms and improve operation of the end device. 
         [0020]    The silicon etching may be performed in a chemical wet bath. The solution used in this chemical wet bath may include tetramethylammonium hydroxide TMAH. An example etching process may include a solution of 5% to 25% by weight TMAH in water at a temperature between 70° C. and 90°. Other parameters and other solutions may be used in the etching process as desired to achieve a similar result. For example, a potassium hydroxide KOH solution or an ammonium hydroxide NH 4 OH solution may be used instead of TMAH. The silicon etch need only take away about 1 to 5 nm of the surface of substrate  100  as further etching produces insignificant additional benefits in reducing the knock-on phenomenon. An HF clean may be performed prior and/or subsequent to silicon etching to remove any native oxide remaining on the surface of substrate  100 . 
         [0021]    After silicon etching, process  10  may proceed at block  20  with convention processing steps. These steps may include the formation of an epitaxial layer  106  to establish a channel region for a transistor device and defining the source, drain, and gate regions and contacts of the transistor device. Final annealing and secondary ion mass spectrometry may then performed as desired. 
         [0022]      FIGS. 3A and 3B  illustrate graphs  300  and  302  of the oxygen concentration in substrate  100  after ion implantation comparing process  10  to conventional processing and variations in process  10 .  FIG. 3A  shows the oxygen concentration graph  300  in substrate  100  for an implant of Germanium at 50 keV and 5e15/cm 2  concentration, a p-type dopant typical for a NMOS device.  FIG. 3B  shows the oxygen concentration graph  302  in substrate  100  for an implant of Arsenic at 6 keV and 2e13/cm 2  concentration, a n-type dopant typical for a PMOS device. In both graphs, lines  304  show the oxygen concentration of substrate  100  for a conventional processing of ion implantation through a thermal oxide layer used as protection on substrate  100 . Lines  306  show the oxygen concentration of substrate  100  for process  10  for ion implantation through native oxide layer  102  used as protection on substrate  100  without the subsequent silicon etch. Lines  308  show the oxygen concentration of substrate  100  for process  10  for ion implantation through native oxide layer  102  used as protection on substrate  100  with the subsequent silicon etch. As illustrated in graphs  300  and  302 , oxygen concentration in substrate  100  can be reduced by using native oxide layer  102  for protection in place of a conventional thermal oxide layer. Further reduction in oxygen concentration can be achieved by performing a post ion implantation silicon etch. 
         [0023]      FIG. 4  illustrates a process  400  to minimize defects in substrate  100  due to ion implantation. Process  40  may be performed in block  16  of process  10 . Process  40  begins at block  42  with ion implantation. After ion implantation, process  40  continues at block  44  with a low temperature anneal. Low temperature anneal is performed to offset the damage to the substrate caused by ion implantation. Low temperature anneal is performed to recrystallize substrate  100  and eliminate amorphous silicon created during ion implantation. 
         [0024]      FIG. 5  illustrates a graph  500  showing different annealing processes for an implant of Germanium at 50 keV and 5e15/cm 2  concentration. The parameters involved with the low temperature anneal include temperature, time, and ambient environment. The ambient environment may be nitrogen or oxygen. There is a trade-off between temperature and time where a higher temperature results in a lesser amount of annealing time. As shown in graph  500 , line  502  represents an anneal process at a temperature of 575° C. that takes about 600 seconds to eliminate a thickness of amorphous silicon created during ion implantation. Line  504  shows that raising the temperature to 600° C. can reduce the anneal time to 150 seconds. Line  506  shows that raising the temperature further to 625° C. reduces the anneal time to less than 150 seconds. Line  508  shows that raising the temperature further to 650° C. reduces the anneal time to much less than 150 seconds. 
         [0025]    Returning to  FIG. 4 , after the low temperature anneal is performed, process  40  continues at block  44  where substrate  100  is subject to a high temperature anneal. High temperature anneal is performed to set implanted impurities at substitution effectively and suppress diffusion of dopant impurities implanted during ion implantation. For example, a p-type dopant for a NMOS device may include germanium, boron, and carbon. The high temperature anneal suppresses the diffusion of boron and carbon in order control the characteristics of implant region  104 . An example of a high temperature anneal would be at approximately 1000° C. for a period of 5 seconds or less. 
         [0026]      FIGS. 6A and 6B  illustrate graphs  600  and  602  showing the concentration of boron and carbon atoms respectively. Graph  600  shows a line  604  representing the concentration of boron atoms after applying a full thermal budget (including shallow trench isolation, gate oxidation, and source/drain formation) with a low temperature anneal only. Graph  600  shows a line  606  representing the concentration of boron atoms after applying a full thermal budget (including shallow trench isolation, gate oxidation, and source/drain formation) with a high temperature anneal. As shown in Graph  600 , line  606  associated with the high temperature anneal has a less diffused profile than line  604  without the high temperature anneal. Graph  602  shows a line  608  representing the concentration of carbon atoms after applying a full thermal budget (including shallow trench isolation, gate oxidation, and source/drain formation) with a low temperature anneal only. Graph  602  shows a line  610  representing the concentration of carbon atoms after applying a full thermal budget (including shallow trench isolation, gate oxidation, and source/drain formation) with a high temperature anneal. As shown in Graph  602 , line  610  associated with the high temperature anneal has a less diffused profile than line  608  without the high temperature anneal. Similar suppression of other materials can be achieved with the high temperature anneal. 
         [0027]    Although the present disclosure has been described in detail with reference to a particular embodiment, it should be understood that various other changes, substitutions, and alterations may be made hereto without departing from the spirit and scope of the appended claims. For example, although the present disclosure includes a description with reference to a specific ordering of processes, other process sequencing may be followed to achieve the end result discussed herein. 
         [0028]    Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the spirit and scope of the appended claims. Moreover, the present disclosure is not intended to be limited in any way by any statement in the specification that is not otherwise reflected in the appended claims.