Abstract:
A mechanism is provided for verifying a register-transfer level design of an execution unit a set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis,

Description:
BACKGROUND 
       [0001]    The present invention relates in general to the field of simulating and verifying the logical correctness of a digital circuit design on a register-transfer level and in particular to verifying a register-transfer level, design of an execution unit. 
         [0002]    Modern execution units have a complex structure and implement a very large instruction set. For example, floating-point units (FPUs) of IBM system z9 and z10 implement more then 330 instructions with 21 different instruction formats and over ten different precisions. To ensure maximum reliability of such execution units, verification has to cover as much of the relevant state space as possible. 
         [0003]    Typically, simulation is used to verify sequences of instructions executed in a model simulation environment. To make full use of the limited time available, realistic and interesting test cases as well as high simulation performance are essential. However, current simulation methods lack at least one of these characteristics. 
         [0004]    Generally, there are the following existing approaches so the simulation of an execution unit. A first approach is test case generation using random number generators. A simple program generates input vectors that are then simulated in a simulation environment with a software-based model simulator. However this creates no realistic test scenarios, uses no knowledge about data formats, architecture, etc and only low simulation performance can be achieved. 
         [0005]    A second approach is test case generation using architecture test case generators. A sophisticated program implemented in a high-level programming language such as C/C++ generates test cases that take into account all necessary aspects of the underlying processor architecture. The resulting test cases are then simulated in a simulation environment, with a software-based model simulator. However the test case generation is slow and also only low simulation performance can be achieved. 
         [0006]    In the Patent Application Publication US 2009/0070717 A1 “Method and system for generation coverage data for a switch frequency of HDL or VHDL signals” by Deutschle et al a method and system for generating coverage data for a switch frequency of HDL or VHDL signals is disclosed. The disclosed method and system for generating coverage data for a switch frequency of HDL or VHDL signals are using a filtering algorithm or filtering rules for signals occurring in the HDL or VHDL hardware description model that is present at the register-transfer level. The method for generating coverage data for a switch frequency of hardware description language (HDL) signals, comprises the steps of providing a HDL hardware description model, within a register transfer level, providing a filtering algorithm for signals occurring in the HDL hardware description model, extracting signals from the HDL hardware description model, according to the filtering algorithm in order to get relevant signals, performing a simulation process on a compiled representation of the HDL hardware description model, performing a checking routine for the relevant signals in every cycle and storing the relevant signals in a data base. 
         [0007]    Usually, the drivers, monitors, and checkers of the simulation environments are also written in high-level programming languages and thus are separate from the simulation model. This degrades simulation performance even further. 
         [0008]    Using so-called hardware accelerators (e.g., AWAN machines) instead of software-based model simulators would improve the simulation performance drastically. However, this approach does not work well with the existing software-based test case generators and separate drives, monitors, and checkers. The simulation process would he slowed down and any potential performance benefit would be negated. 
       BRIEF SUMMARY 
       [0009]    In one illustrative embodiment, a method, in a data processing system, is provided for verifying a register-transfer level design of an execution unit. The illustrative embodiment generates a set of instruction records associated with a test case The illustrative embodiment stores the set of instruction records in a buffer. For each instruction record in the set of instruction records associated with the test case, the illustrative embodiment: retrieves the instruction record from the buffer; sends the instruction record to both a reference model, and an execution unit in the data processing system, wherein the reference model is reference for a register-transfer level design and wherein the execution unit is a new register-transfer level design to be verified; executes separately, by the reference model and the execution unit, the instruction record; sends separately, by the reference model and the execution unit, results of the execution of the instruction record to a result checker in the data processing system; compares the results of the execution of the instruction record from both the reference model and the execution unit; responsive to a mismatch in the results, indicates a failure of the test case to the test case generator; stops the verification of the test case; and outputs all data associated with the test case from the buffer for analysis. 
         [0010]    In other illustrative embodiments, a computer program. product comprising a computer useable or readable medium having a computer readable program is provided. The computer readable program, when executed on a computing device, causes the computing device to perform various ones, and combinations of, the operations outlined above with regard to the method illustrative embodiment. 
         [0011]    In yet another illustrative embodiment, a data processing system is provided. The data processing system may comprise one or more processors and a memory coupled to the one or more processors. The memory may comprise instructions which, when executed by the one or more processors, cause the one or more processors to perform various ones, and combinations of, the operations outlined above with regard to the method illustrative embodiment. 
         [0012]    These and other features and advantages of the present invention will be described in, or will become apparent to those of ordinary skill in the art in view of, the following detailed description of the example embodiments of the present invention. 
     
    
     
       BRIEF DESCRIPTION OFT HE SEVERAL VIEWS OF THE DRAWINGS 
         [0013]    A preferred embodiment of the invention, as described in detail below, is shown in the drawings, in which 
           [0014]      FIG. 1  is a schematic block diagram of a simulation environment to verify a register-transfer level design of an execution unit in accordance with an illustrative embodiment; 
           [0015]      FIG. 2  is a schematic block diagram of a test case generator for the simulation environment to verify a register-transfer level design of an execution unit of  FIG. 1  in accordance with an illustrative embodiment; 
           [0016]      FIG. 3  is a more detailed block diagram of the test case generator of  FIG. 2  in accordance with an illustrative embodiment; 
           [0017]      FIG. 4  is a more detailed block diagram showing a part of the test case generator of  FIG. 3  to explain how instructions for the test case generator are generated in accordance with an illustrative embodiment; 
           [0018]      FIG. 5  is a more detailed block diagram of a data generator for the test case generator of  FIG. 3  in accordance with an illustrative embodiment; and 
           [0019]      FIG. 6  is a schematic flow chart of a method to verify a register-transfer level design of an execution unit, in accordance with an illustrative embodiment, 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    It will be readily understood that the components of the present invention, as generally described and illustrated in the Figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the apparatus, system, and method of the present invention, as presented in the Figures, is not intended to limit the scope of the invention, as claimed, but merely representative of selected embodiments of the invention. 
         [0021]    Reference throughout this specification to “a select embodiment,” “one embodiment,” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “a select embodiment,” “in one embodiment,” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. 
         [0022]    The illustrated embodiment of the invention will be best understood by reference to the drawings, wherein like part are designated by like numerals throughout. The following description is intended only by way of example, and simply illustrates certain select embodiments of devices, systems, and processes that are consistent with the invention as claimed herein. 
         [0023]      FIG. 1  shows a simulation environment  1  to verify a register-transfer level design of an execution unit  40 , in accordance with an illustrative embodiment. 
         [0024]    Referring to  FIG. 1  the simulation environment  1  to verify the register-transfer level design of the execution unit  40  comprises a test case generator  10 , a driver  20 , and a reference model  30  for the execution unit  40 , and a result checker  50 . 
         [0025]    According to the invention the test case generator  10 , the driver  20 , the reference model  30  for the execution unit  40  and the result checker  50  are written in a hardware description language, and compiled directly in a simulation model of the simulation environment  1 . The driver  20  uses test case data produced by the test case generator  10  to feed the execution unit  40 , like a floating-point unit (FPU), fixed-point unit (FixPU) or any other data manipulating unit, and the reference model  30 . When results are available from both the execution unit.  40  and the reference model  30 , the result checker  50  compares both results and flags an error if there is a difference. 
         [0026]    Like the execution unit  40 , the test case generator  10 , the driver  20 , the reference model  30 , and the result checker  50  are implemented in a synthesizable hardware description language such as Very High Speed Integrated Circuits Hardware Description Language (VHDL) and are inserted into the design, i.e., the sources from which the simulation model  1  is compiled, as VHDL modules. Embodiments of the inventive simulation environment  1  are not limited to running on hardware accelerators such as the ANAN machines. They can also be executed using software-based model simulators, e.g., the IBM MESA simulator and, with minor changes, field-programmable gate array (FPGA) chips. 
         [0027]      FIG. 2  shows the test case generator  10  for the simulation environment  1  in greater detail in accordance with an illustrative embodiment;  FIG. 3  is a more detailed block diagram of the test case generator  10  of  FIG. 2  in accordance with an illustrative embodiment;  FIG. 4  is a more detailed block diagram showing a part of the test case generator  10  of  FIG. 3  to explain how instructions for the test case generator  10  are generated in accordance with an illustrative embodiment; and  FIG. 5  is a more detailed block diagram of a data generator  130  for the test case generator  10  of  FIG. 3  in accordance with an illustrative embodiment. 
         [0028]    Referring to  FIGS. 2 to 5  the test case generator  10  comprises an instruction generator  110 , a data generator  130 , a generation control block  120 , a buffer  140  and an issue control block  150  such that instructions and data generated by the test case generator  10  can be used as input for the reference model  30  of the execution unit  40  and the design of the execution unit  40 . 
         [0029]    The generation of instruction records, which form the instruction stream that is simulated, is decoupled from their issue to the driver  20 , from where they are issued to the execution unit  40  and the reference model  30 . Thus, the generation of instruction records and the storing of these instruction records into the buffer  140  run in parallel to the actual execution of the corresponding instructions in the execution unit  40  and the reference model  30 . 
         [0030]    The test case generator  10  has a simple interface to the user, i.e., a verification engineer, and the driver  20 . The user provides a list  112  of valid instructions and can set certain parameters to configure the test case generation. The driver  20  requests the next instruction record via “get next” instruction, for example. Furthermore, it can request older instruction records in order to support so-called stalls, rejects, kills, and flushes, which require certain instructions of the instruction stream to be re-issued. 
         [0031]    In each simulation cycle, the instruction generator  110  randomly selects an instruction based on a so-called valid instruction list  112  that contains all valid instructions along with their probabilities. Referring to  FIG. 4  the valid instruction list  112  is initialized by so-called sticks  70  which are provided by the user and loaded into the simulation model  1  at runtime. These sticks  70  can be generated from table  60  with instructions and their probabilities, e.g., a. text file or a spreadsheet, in an automated fashion, e.g., by a small script. 
         [0032]    The valid instruction list  112  can be changed without recompiling the simulation model  1 , which usually is a very time-consuming step. By modifying the valid instruction list  112 , the user is able to easily target specific scenarios. 
         [0033]    The instruction generator  110  contains knowledge about memory/general-purpose-register (GPR) input operands an instruction requires. After randomly selecting a valid instruction, the instruction generator  110  sends the corresponding data format information to the data generator  130 . The instruction generator  110  sends the instruction&#39;s so-called operation code (opcode) to the generation control block  120 . 
         [0034]    When a new test case begins, the instruction generator  110  automatically produces one load instruction for each register in the execution unit  40 , e.g., for the floating-point registers in a floating point unit. This initializes both the execution unit  40  and the reference model  30  to the same state and provides an easy way to store the initial register values in the buffer  140 . 
         [0035]    Referring to  FIG. 5 , the data generator  130  comprises a format interpreter  131 , a generator  132 , a register address generator  136  and a multiplexer  137 . The data generator  130  is producing up to two memory/GPR input operands in the data format(s) required by the instruction that was generated by the instruction generator  110 . Furthermore, the data generator  130  selects the floating-point-register (FPR) addresses created by the register address generator  136 , and further instruction-specific fields defined by the processor architecture, if any. 
         [0036]    A data format comprises an instruction format, a precision, and a number domain. The instruction formats are defined in the processor architecture and specify the number of operands, usually between zero and three, the order of these operands, and their location, e.g. memory, FPR, GPR, etc. The precision defines the length of an operand, e.g., short with 32 bits, long with 64 bits, and extended with 128 bits, by controlling the multiplexer  137 . The number domain specifies how the operand data is encoded, e.g., binary fixed-point, binary-coded decimal (BCD), binary floating-point (BFP), hexadecimal floating-point (RFP), decimal floating-point (DFP). But not all combinations of instruction format, precision, and number domain. are valid. 
         [0037]    The user can control the data generator  130  through a set of probabilities, e.g., the probability of generating a zero, a positive number, an infinity, etc.; the probability of reusing register addresses; the probability of instruction-specific rounding modes. The probabilities are set via sticks  70  that are loaded into the simulation model  1  at runtime. 
         [0038]    The generation control block  120  combines the instruction&#39;s operation code generated by the instruction generator  110  and the information provided by the data generator  130  into an instruction record. The instruction record is a set of all processor-architecture-level information associated with an instruction. The instruction record contains all information the driver needs to drive the execution unit  40  and the reference model  30 . 
         [0039]    For example, the instruction record comprises an operation code providing the instruction&#39;s operation code as defined by the processor architecture, memory/GPR operands providing memory/GPR operands for the instruction, register address providing addresses of the registers used by the instruction, further fields providing further instruction-specific input data as defined by the processor architecture, if required, and control registers providing settings of control register that are relevant for the instruction, e.g., IEEE exception enable bits and rounding modes, if required. 
         [0040]    The generation control block  120  contains a counter that counts how many instructions records have been stored into the buffer  140 . Each cycle, until the pre-defined number of instructions per test case is reached, the generation control block  120  stores a new instruction record into the buffer  140  and increments the counter. Once all instructions of the current test case have been generated, i.e., the counter equals the pre-defined number of instructions per test case, the generation control block  120  does not store further instruction records and waits until the next test case begins. When a new test case begins, the counter is reset to zero. 
         [0041]    The buffer  140  stores the generated instruction records. Each of the instruction records can be written by the generation control block  120  and read by the issue control block  150  at the same time. The number of entries in the buffer  140  is the product of the pre-defined number of instructions per test case and a pre-defined number of test cases. This allows the buffer  140  to store not only the current test case but also a certain number of test cases generated and simulated before the current one. This is essential when investigating fails that are caused by instructions or events in previous test cases. 
         [0042]    The issue control block  150  is the interface of the test case generator  10  to the driver  20 . The issue control block  150  contains a counter that gives the index of the next instruction record to be given to the driver  20 . When the driver  20  signals “get next”, the issue control block  150  sends the next instruction record plus its index and a “last” flag, and increments the counter. When the driver  20  needs to re-issue previous instructions, e.g., due to a kill or a flush, the driver  20  signals “resume” along with the index of the required instruction record. The issue control block  150  sets its counter to this index and returns the corresponding instruction record plus index and “last” flag. When the last instruction has successfully completed its execution in both execution unit  40  and reference model  30 , the driver  20  signals “finish”, the issue control block  150  resets its counter to zero, and the test case generator  10  begins generating the next test case. 
         [0043]    If the result checker  50  sees a mismatch between the results of execution unit  40  and reference model  30 , or an error occurs in the execution unit  40 , the driver  20  will signal “fail”. This causes the test case generator  10  to raise a certain internal, fail signal and stop modifying the buffer  140  for a pre-defined number of cycles. A small, external fail collect program, which is triggered in an interval that matches the pre-defined number of cycles, monitors the internal fail signal. If the signal is active, the test case generator  10  reads out all data in the buffer  140 , i.e., the current test case and a certain number of previous test cases, and writes this data into a file. After waiting the pre-defined number of cycles, the test case generator  10  lowers its internal fail signal and begins generating the next test case. 
         [0044]    Since the external fail collect program is only called in a certain interval, the performance impact is minimal. The data contained in the file written by the fail collect program allows the user to reproduce and analyze failing test cases in another, software-based simulation environment, which could reuse parts of the simulation environment  1  described herein. 
         [0045]      FIG. 6  is a schematic flow chart of a method to verify a register-transfer level design of an execution unit, in accordance with an illustrative embodiment. 
         [0046]    Referring to  FIG. 6  the flowchart depicts how the simulation environment  1  to verify a register-transfer level design of an execution unit  40  will be used. According to step S 10  the test case generator  10 , the driver  20 , the reference model  30  for the execution unit  40  and the result checker  50  are written in a hardware description language. In Step  320  the test. case generator  10 , the driver  20 , the reference model  30  for the execution unit  40  and the result checker  50  are compiled directly in a simulation model of the simulation environment  1 . In step S 30  an output of the driver  20  is used as input for the reference model  30  of the execution unit  40  and the design of the execution unit  40 . In step S 40  an output of the reference model  30  of the execution unit.  40  and an output of the design of the execution unit  40  are used as input of the result checker  50  comparing the outputs of the design of the execution unit  40  and the reference model  30  of the execution unit  40  for equality. In step S 50  a mismatch is reported and collected through an external program. 
         [0047]    Furthermore, embodiments of the present invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer-readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection. with the instruction execution system, apparatus, or device. 
         [0048]    The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system. (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include compact disk—read only memory (CD-ROM), compact disk—read/write (CD-R/W), and DVD. A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. 
         [0049]    Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards, are just a few of the currently available types of network adapters. 
         [0050]    Embodiments of the present invention achieve advantageously a very high simulation performance and thus high coverage of state space. The test case generator is able to produce realistic test scenarios that can be controlled by user-defined settings. These user-defined settings can be modified at runtime. Test case generator, driver, reference model, and result checker are separated blocks, which allows easy reuse. Failing test cases can be reproduced in other, software-based simulation environments.