Abstract:
This invention provides layout schemes for ball/pad regions on a printed circuit board for a small regular ball/pad region grid that provides additional space between ball/pad regions for increased wiring capability. The layout scheme is consistent with printed circuit board manufacturing requirements and minimum wiring channel requirements demanded by high density integrated circuit chips.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    (1) Field of the Invention 
         [0002]    This invention relates to a compressed ball/pad region layout grid or matrix for printed circuit boards which will carry integrated circuits and possibly other circuit components. The layout allows spacing for conductors and accommodates high density spacing for integrated circuit pads. 
         [0003]    (2) Description of the Related Art 
         [0004]    U.S. Pat. No. 7,652,379 B2 to Poddar describes a bond pad stack having two conductor layers below a third conductor layer. The third conductor layer has a width that is greater than the width of each of the two conductor layers below the third layer. 
         [0005]    U.S. Pat. No. 7,495,296 B2 to Maeda et al. describes a layout of a multi-channel semiconductor integrated circuit having ternary circuits in order to increase the degree of integration. 
         [0006]    U.S. Pat. No. 6,168,854 B1 to Gibbs describes a method of manufacturing printed circuit boards having high density conductive patterns comprising at least one pad suitable for forming a solder connection with at least one surface mounted component. A process is also described which applies a resist to a conductive pattern, etching the conducting pattern, and using the resist to form a conducting coating on the conducting pattern. 
         [0007]    U.S. Pat. No. 6,057,601 to Lau et al. describes a semiconductor ball grid array package for integrated circuits which have input and output counts higher than 250. The package includes a supporting heat spreader layer having a plurality of saw teeth to penetrate an adhesive layer covering a plurality of ground planes. These ground planes are formed on a backside of a substrate supporting a semiconductor device such that the heat spreader can function as a ground terminal for the semiconductor device. 
         [0008]    U.S. Pat. No. 5,818,114 to Pendse et al. describes a radially staggered bonding pad arrangement around the center of a semiconductor die. The bonding pad arrangement allows for increased lead frame density used for wire bonding conductors between the semiconductor circuit pads and the staggered bonding pad arrangement. 
         [0009]    U.S. Pat. No. 5,567,655 to Rostoker et al. describes a bond pad layout on semiconductor circuit chips which reduces thermally induced mechanical stresses. The bond pads are equidistant from the centerline of the chip. Bond pads on either side of the centerline are staggered. 
       SUMMARY OF THE INVENTION 
       [0010]    Today&#39;s standard IC (integrated circuit) package ball/pad region layout is defined by a regular pitch in the x and y direction, as shown in  FIG. 1 .  FIG. 1  shows a top view of a standard integrated circuit board  10  having a number of ball/pad regions  11 . The pitch  12  is the same in the x and y directions and is determined by the number of required ball/pad regions and the target package size. Typically manufacturing rules require a minimum pitch for a given manufacturing technology. As the density of circuits in integrated circuit chips increases and the size of the chips decreases more wiring channels are required. Smaller pitch is a serious limitation to the availability of sufficient wiring channels. 
         [0011]    ICs with a single outside row and/or column of balls/pads may be routed on a PCB (printed circuit board) using a single outer layer of metal. To route ICs with a higher number of rows/columns the PCBs typically have to use multiple layers of metal. Inner rows/columns are then routed on the outside layer only towards a close placed via, which then allows a further signal routing inside a deeper PCB layer. Vias are drilled holes with a layer of copper at the circumference. Standard vias are mechanically drilled and have a typical minimum hole diameter of 200-300 um. Because of mechanical tolerances the connected landing pads of standard vias are typically ≧550 um. 
         [0012]    Following the trend for miniaturization and reduced PCB space the ball/pad pitch of ICs with a higher level of integration has been reduced from 0.8 mm and 0.65 mm towards 0.5 mm and 0.4 mm with plans to go even towards 0.3 mm. This has created some challenges for the signal routing on the PCB. But from 0.5 mm pitch standard vias can no longer be placed between balls/pads. For about 0.4 mm or smaller ball/pad pitch it is no longer possible to route signals between regular spaced balls/pad regions. 
         [0013]    It is a principal objective of this invention to provide a ball/pad layout scheme that meets manufacturing requirements for a small regular ball/pad region grid and provides additional space between ball/pad regions for increased wiring capability. 
         [0014]    This objective is achieved by using a different x and y ball/pad pitches in local areas of the integrated circuit package. A staggered ball/pad region pitch arrangement is used to achieve a reduced pitch in one direction while maintaining a minimum ball to ball (pad to pad) distance. A ball/pad region pitch of about 0.5 mm can be used in the x direction and a pitch of about 0.32 mm in the y direction with alternating rows locating balls/pads at the gaps of adjacent rows. This provides a spacing of about 0.4 mm between nearest balls/pads in adjacent rows. A different ball/pad region pitch can be used in other regions of the integrated circuit package. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  shows a top view of a printed circuit board having a standard x-y grid of ball/pad regions. 
           [0016]      FIG. 2  shows a top view of a printed circuit board of this invention showing four rows of an x-y ball/pad region grid using a first pitch in the x direction, the top row and bottom row having a one half first pitch off-set in the x direction, a second pitch in the y direction between the top row and the adjacent row and the bottom row and the adjacent row, and a third pitch between the two middle rows. 
           [0017]      FIG. 3  shows a top view of a printed circuit board of this invention showing four rows of an x-y ball/pad region grid having a different pitch in the x and y directions with every second row having a one half pitch offset in the x direction. 
           [0018]      FIG. 4  shows a top view of a printed circuit board of this invention showing a ball/pad region grid of the type shown in  FIG. 3  at the four edges of the printed circuit board with larger spacing between the ball/pad regions in the center of the board. 
           [0019]      FIG. 5  shows a top view of the printed circuit board shown in  FIG. 4  showing placement of standard vias in the board. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0020]    Refer now to  FIG. 2  for a description of a preferred embodiment of the ball/pad region layout of this invention.  FIG. 2  shows a top view of a printed circuit board of this invention showing four rows of an x-y grid for locating the ball/pad regions  22 . The ball/pad regions  22  have a pitch of a first distance  16  in the x direction for all four rows and the top row and bottom row have an off-set  14  of one half of the first distance  16  in the x direction. The distance in the y direction between the centerline  21  of the ball/pad regions  22  in the top row and the centerline  19  of the ball/pad regions  22  in the next row and between the centerline  25  of the ball pad regions  22  bottom row and the centerline  23  of the ball/pad regions in the next to last row is a pitch of a second distance  20 . The distance between the centerlines  19  and  23  of the ball/pad regions in the two middle rows is a pitch of a third distance  18 . The distance between the ball/pad regions in the first row and the nearest neighbor ball/pad regions in the second row and between the ball/pad regions in the last row and the nearest neighbor ball/pad regions in the next to last row is a pitch of a fourth distance  17  In this example the first distance  16  is about 0.5 mm, the second distance  20  is about 0.32 mm, and the third distance  18  is about 0.4 mm. This provides a fourth distance  17  of about 0.4 mm which in this example is about the same as the third distance. Of course, different values for the first, second, and third distances could be used which would result in a different fourth distance. The location of the left most ball/pad regions are on a reference line  15 . 
         [0021]    Refer now to  FIG. 3  for another preferred embodiment of the ball/pad region layout of this invention.  FIG. 3  shows a top view of a printed circuit board of this invention showing four rows of an x-y grid for locating the ball/pad regions  22 . The ball/pad regions  22  have a first pitch in the x direction of a first distance  24  for all four rows. The second row and bottom row have an off-set in the x direction of a second distance  33 , which is one half of the first distance  24 . The pitch of the centerlines of the ball/pad regions in the y direction have a second pitch of a second distance  30 . This results in a separation between nearest neighbor ball/pad regions of a third distance  28 . As an example a first distance  24  of about 0.5 mm and a second distance  30  of about 0.32 mm results in a third distance  28  of about 0.41 mm. The location of the left most ball/pad regions are on a reference line  31 . 
         [0022]    Those skilled in the art will readily recognize that different values for the first distance  24  and second distance  30  can be used, which will provide a different third distance  28  for separation between nearest neighbor ball/pad regions. For example a first distance  24  of 0.58 mm and a second distance  30  of 0.29 mm results in a third distance  28  of about 0.41 mm. 
         [0023]      FIG. 4  shows another embodiment of the ball/pad region layout of this invention.  FIG. 4  shows a top view of a printed circuit board  37  having a ball/pad region layout as described in a previous paragraph and shown in  FIG. 3  around the four edges of the printed circuit board. In the regions around the four edges of the printed circuit board like reference numbers identify like features of the invention as described above and shown in  FIG. 3 .  FIG. 4  also shows ball/pad regions  35  on a more widely spaced grid at the center portion of the printed circuit board.  FIG. 5  shows the printed circuit board of  FIG. 4  also showing the placement of standard vias  35 . 
         [0024]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.