Abstract:
An integrated circuit (IC) with an oscillator and electrostatic discharge (ESD) protection in which the parasitic capacitance of the ESD protection circuitry is disassociated from the oscillator circuitry to minimize loading of the tank circuit thereby minimizing degradation of the tank circuit quality factor (Q).

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an integrated circuit (IC) with an oscillator, and in particular, to such a circuit which also includes electrostatic discharge (ESD) protection. 
   2. Description of the Related Art 
   Referring to  FIG. 1 , high frequency oscillators play a critical role in many circuits, particularly wireless communication circuits. With the increased use and complexities of wireless communication devices, such circuits have become increasingly sophisticated. Among others, one characteristic which is often critical is low phase noise performance. This requires the oscillator to have a resonant, or “tank”, circuit with a high quality factor Q. 
   Referring to  FIG. 1 , one conventional implementation of an oscillator  10  within an IC includes an amplifier circuit with cross-coupled complementary metal oxide semiconductor field effect transistors (C-MOSFETs), such as P-type transistors P 1  and P 2  and N-type transistors N 1  and N 2 , interconnected substantially as shown, and biased between upper (e.g., positive) VDD and lower (e.g., negative) VSS/GND power supply voltage terminals via a resistor R 1 . The output voltage Vout is a differential voltage which appears between signal electrodes  12   a  and  12   b . The tank circuit is formed using shunt capacitors C 1  and C 2  and inductors L 1  and L 2  connected to signal electrodes  12   a  and  12   b  as shown. As is well known in the art, the capacitors C 1 , C 2  can be variable, e.g., varactors, so that this oscillator circuit  10  can be operated as a voltage control oscillator (VCO). The inductors are connected together via a shared electrode B 3  (discussed in more detail below). 
   As is well known in the art, modern ICs virtually always include on-chip ESD protection, and this circuit  10  is no different. To prevent an external ESD event from damaging the oscillator circuitry, ESD protection circuitry in the form of shunt diodes D 1   a , D 1   b , D 2   a  and D 2   b  are connected between the output signal electrodes  12   a ,  12   b  (which can also be electrically connected to on-chip bonding pads B 1 , B 2 ) and the power supply rails VDD, VSS/GND as shown. (The operating principles of such ESD protection circuitry are well known in the art. Further, it will be appreciated by one of ordinary skill in the art that other forms of ESD protection circuitry can be used as well, with such other forms of ESD circuitry also being connected in a shunt arrangement at the output signal electrodes  12   a ,  12   b .) 
   Referring to  FIG. 2  in conjunction with  FIG. 1 , the inductors L 1 , L 2  are typically implemented using bond wires  14   a ,  14   b , with the shared electrode B 3  being a bonding pad resident on a package leadframe  22  upon which the die  20  containing the IC is placed. At the high frequencies for which such integrated oscillator circuits are used, such bond wires  14   a ,  14   b  provide the inductance necessary for the tank circuit. As is well known in the art, the die  20  will include a number of other bonding pads  24 , which are electrically connected to package leadframe bonding pads  26  via bond wires  28 . 
   A problem with this conventional approach, however, is the loading presented to the signal electrodes  12   a ,  12   b  by the shunt ESD circuitry. Such loading is generally in the form of the shunt capacitance which is inherent to the ESD protection circuitry. This shunt capacitance generally has a low quality factor Q, and thereby causes the overall quality factor Q of the tank circuit to be significantly degraded, resulting, in turn, in increased phase noise in the output signal Vout of the oscillator circuit. Further, such additional capacitance of the ESD circuitry adds to the fixed capacitance of the tank circuit, thereby limiting the maximum oscillation frequency and decreasing the effective tuning range, e.g., when using varactors for the tank circuit capacitors C 1 , C 2 . 
   SUMMARY OF THE INVENTION 
   In accordance with the presently claimed invention, an integrated circuit (IC) with an oscillator and electrostatic discharge (ESD) protection is provided in which the parasitic capacitance of the ESD protection circuitry is disassociated from the oscillator circuitry to minimize loading of the tank circuit thereby minimizing degradation of the tank circuit quality factor (Q). 
   In accordance with one embodiment of the presently claimed invention, an integrated circuit (IC) with an oscillator and electrostatic discharge (ESD) protection includes power supply electrodes, shared electrodes, amplifier circuitry, inductances, capacitances, ESD protection circuitry and a DC connection. The amplifier circuitry is coupled between first and second power supply electrodes and includes first and second signal electrodes. First and second inductances are coupled between a first shared electrode and the first and second signal electrodes, respectively. First and second capacitances are coupled between at least one of the first and second power supply electrodes and the first and second signal electrodes, respectively. The ESD protection circuitry is coupled between a second shared electrode and at least one of the first and second power supply electrodes. The DC connection is between the first and second shared electrodes. 
   In accordance with another embodiment of the presently claimed invention, an integrated circuit (IC) with an oscillator and electrostatic discharge (ESD) protection includes power supply electrodes, shared electrodes, amplifier circuitry, bond wires, capacitances and ESD protection circuitry. The amplifier circuitry is coupled between first and second power supply electrodes and includes first and second signal electrodes. First and second bond wires are coupled between a first shared electrode and the first and second signal electrodes, respectively. First and second capacitances are coupled between at least one of the first and second power supply electrodes and the first and second signal electrodes, respectively. The ESD protection circuitry is coupled between a second shared electrode and at least one of the first and second power supply electrodes. A third bond wire is coupled between the first and second shared electrodes. 
   In accordance with still another embodiment of the presently claimed invention, an integrated circuit (IC) with an oscillator and electrostatic discharge (ESD) protection includes power supply electrodes, shared electrodes, oscillator circuitry, ESD protection circuitry and a DC connection. The oscillator circuitry is coupled between first and second power supply electrodes and includes tank circuitry and first and second signal electrodes. The tank circuitry includes inductance circuitry coupled between a first shared electrode and the first and second signal electrodes, and capacitance circuitry coupled between at least one of the first and second power supply electrodes and the first and second signal electrodes. The ESD protection circuitry is coupled between a second shared electrode and at least one of the first and second power supply electrodes. The DC connection is between the first and second shared electrodes. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a conventional integrated oscillator circuit with ESD protection. 
       FIG. 2  is a simplified view of an integrated circuit package having a package leadframe inductor circuit bonding pad connected in a conventional manner. 
       FIG. 3  is a schematic diagram of an integrated oscillator circuit with ESD protection in accordance with one embodiment of the presently claimed invention. 
       FIG. 4  is a simplified view of an integrated circuit package having a package leadframe inductor circuit bonding pad connected in accordance with one embodiment of the presently claimed invention. 
   

   DETAILED DESCRIPTION 
   The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
   Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
   Referring to  FIG. 3 , an IC with an oscillator and ESD protection  100  in accordance with one embodiment of the presently claimed invention includes the amplifier circuit components P 1 , P 2 , N 1 , N 2  and tank circuit components L 1 , L 2 , C 1 , C 2  interconnected as in the circuit of  FIG. 1 . However, in accordance with the presently claimed invention, the ESD protection circuitry is no longer connected directly at the signal electrodes,  12   a ,  12   b . Instead, the ESD protection circuitry (which can now be implemented in a simpler form, e.g., two shunt diodes D 1 , D 2 , connected between a single IC bonding pad B 4  and the power supply rails VDD, ground) is connected to the package leadframe bonding pad B 3  shared by the inductors L 1 , L 2  via another inductance L 3 , e.g., another bond wire  14   c.    
   Provided the bond wires  14   a ,  14   b  forming the tank inductances L 1 , L 2  are substantially matched in length, the package leadframe bonding pad B 3  will be at a signal ground potential due to the balanced nature of this differential oscillator circuitry  100 . As a result, the capacitance of the shunt ESD protection circuit devices D 1 , D 2  will also be at signal ground potential, and thereby not need to be charged or discharged along with the voltage oscillations of the tank circuit, and therefore will not draw any signal current from the tank circuit. Accordingly, since no signal current will flow through the lossy elements of the ESD protection circuit, there is no signal power loss. Consequently, the quality factor Q of the tank circuitry is not degraded by the ESD protection circuit devices. Even with some mismatch in the lengths of the bond wires  14   a ,  14   b  forming the tank circuit inductances L 1 , L 2 , any signal voltage variation at the package leadframe bonding pad B 3  will still be significantly less than the signal voltage appearing at the signal electrodes  12   a ,  12   b.    
   Referring to  FIG. 4 , as noted above, the on-chip ESD protection circuitry is connected to the IC bonding pad B 4  which, in turn, is connected to the package leadframe bonding pad B 3  via a DC connection in the form of another bond wire  14   c . (The other bonding pads and bond wires as depicted in the diagram of  FIG. 2  have been omitted for purposes of clarity.) 
   Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.