Abstract:
An integrated circuit having multiple power/ground connections to a single external terminal and method for manufacturing an integrated circuit provides an integrated circuit having a reduced number of external power/ground terminals. The multiple connections may be made by conductive circuit paths on one side of the substrate and a terminal pad on the same side of the substrate, with the conductive circuit paths leading from die terminals terminating at the terminal pad, or a via may be formed either directly above the terminal pad or contacting its circumference to provide a connection through from the opposite side of the substrate. Multiple vias may be formed above the terminal pad and within its circumference to provide connection of multiple die terminals to the terminal pad.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor packaging, and more specifically, to a substrate having multiple connections to external terminals for providing electrical inter-connection between multiple power connections of one or more integrated circuit dies to a single external terminal. 
     BACKGROUND OF THE INVENTION 
     Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including “flip-chip”, ball grid array and land grid array among other mounting configurations. 
     High-density interconnect schemes such as high-density ball grid arrays (BGAs) or land grid arrays (LGAs) typically have multiple power and ground balls or lands in the array in order to provide a low impedance connection from the die(s) to the external power supply connections. Multiple terminals are also used to provide improved heat transfer from the semiconductor die(s) to the mounting carrier (e.g., printed circuit board or socket). In one terminal arrangement of these packages, the entire center section of the array is dedicated to power and ground connections. 
     The thermal and electrical impedances of the terminal (e.g., solder ball or land) do not necessitate the multi-terminal connection arrangement. Rather, it is the impedance of the wire-bonding structure (if used) and the impedance of the circuit traces on the substrate that necessitate the use of multiple terminals. 
     Therefore, it would be desirable to provide a method and integrated circuit package having a reduced number of power and ground terminals, while maintaining a low electrical impedance and a low thermal impedance connection from the integrated circuit die(s) to ground and power supply terminals. It would similarly be desirable to provide a method and integrated circuit package providing a higher-density interconnect by reducing the number of required power and ground connections. 
     SUMMARY OF THE INVENTION 
     A substrate having multiple power supply and/or ground connections between one or more die terminals to a single external pad provides a lower pin count or higher-density interconnect integrated circuit package. The integrated circuit includes at least one integrated circuit die, a substrate for mounting and electrically interconnecting the integrated circuit die(s) and a cover for covering the integrated circuit die(s). 
     The substrate includes multiple terminal pads for connection to external terminals of the integrated circuit and multiple bond pads for connection to terminals of integrated circuit die(s) where at least two power and/or ground connections from among bond pads are connected to a single terminal pad. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a pictorial diagram depicting features of an integrated circuit in accordance with an embodiment of the invention; 
     FIG. 1B is a pictorial diagram depicting features of an integrated circuit in accordance with another embodiment of the invention; 
     FIG. 1C is a pictorial diagram depicting various pad structures in accordance with embodiments of the invention; 
     FIG. 2A is a pictorial diagram depicting features of an integrated circuit in accordance another embodiment of the invention; 
     FIG. 2B is a pictorial diagram depicting features of a substrate circuit in accordance another embodiment of the invention; and 
     FIG. 2C is a pictorial diagram depicting features of an integrated circuit in accordance with another embodiment of the invention. 
    
    
     The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout. 
     DETAILED DESCRIPTION 
     Referring now to the figures and in particular to FIG. 1A, an integrated circuit  10 A, in accordance with an embodiment of the present invention is depicted. Integrated circuit  10 A is a ball-grid array (BGA) package for a standard integrated circuit die  12 A. Integrated circuit die  12 A is bonded to the top side of a substrate  13 A on which a plurality of circuit paths  20 A are fabricated via etching, plating or sputtering. Circuit paths  20 A may be formed above the top surface of substrate  13 A or may be embedded beneath the surface by laser ablating channels, embossing the substrate or other means. Circuit paths  20 A terminate in bond pads on which wires  15  are bonded, connecting integrated circuit terminals to circuit paths  20 A. A cover  14  is applied over integrated circuit die  12 A and attached to substrate  13 A to protect the assembly from environmental conditions and handling damage. A plurality of solder balls  16 A are attached to pads  19 A for connecting integrated circuit die  12 A to external circuits. 
     The present invention concerns connection of circuit traces  20 A (and also any power and ground planes within a substrate) to pads  19 A. Traditionally, only one connection is typically made between a bond pad and an integrated circuit terminal or ground plane, due to the design rules for circuit path widths and spacing. Also, vias are typically large, requiring a hole that is of significant size with respect to the pads, making only one via typically available per pad. The present invention reduces the size of conductive paths and vias through laser drilling vias and more precisely controlling an etching or plating process, or by embedding the conductive paths beneath the surface of the substrate. The present invention provides multiple connections to the pads, permitting reduction of the number of terminals used for connection of power and/or ground (which in this specification and appended claims should be understood to be contemplated by the term “power connections”). 
     Thus in FIG. 1A, connection of a via  18 A from pad  19 A and to two conductive paths  20 A, multiple power contacts on integrated circuit die  12 A may be coupled to a single power pad  18 A and to solder ball  16 A. Electrical performance is not compromised significantly, as the impedance of wires  15  and the bonded ends, as well as die impedance is typically higher than the impedance of the connection between bond pads  22 A and solder ball  16 A. Also, thermal performance is improved, as the temperature differential between bond pads  22 A is controlled within integrated circuit  10 A, rather than being subject to external conditions (i.e., thermal differences between solder balls). Similarly to the electrical performance, the thermal impedance between bond pads  22 A and solder ball  16 A is typically much lower than the thermal impedance between die  12 A connections and bond pads  22 A. 
     FIG. 1B shows an integrated circuit  10 B that includes a flip-chip semiconductor die  12 B. Rather than bond pads, lands  22 B for the attachment of solder balls or posts  17  from semiconductor die  12 B to s substrate  13 B are included. Other than the differences in die attach methodology, integrated circuit  10 B is an example of a land grid array (LGA) including solder or other metal lands  16 B for the connection of semiconductor die  12 B to external circuits. While the figures illustrate a wire-bonded die in a BGA package and a flip-chip die in an LGA package, any combination of the above as well as other integrated circuits having packages and die connects may be fabricated using techniques and structures in accordance with embodiments of the present invention. 
     FIG. 1C is a pictorial diagram depicting various multiple pad connections in accordance with embodiments of the present invention. Pad  19 C is connected to a single via  18 C that branches to multiple conductive paths  20 C that carry power connections from multiple connection points of an integrated circuit die, power planes of a substrate or other terminal pads. Pad  19 D is connected to multiple vertical vias  18 D that lie within a cylinder having an axial cross section defined by the circumference of pad  19 D. Circuit paths  20 D individually extend from vias  18 D to connect to other power connections within the integrated circuit (generally connections to power or ground terminals on one or more semiconductor dies). 
     Pad  19 E includes a via  18 E contacting the periphery of pad and circuit paths  20 E extending from via  18 E and pad  20 E. It is notable that via  1 BE is much smaller than a typical integrated circuit substrate via, as clearances to the next pads in the grid array must be maintained. Pad  19 F is an example of an embodiment of the present invention without vias. Multiple connections  20 F extend to integrated circuit die power or ground terminals, providing a connection from the power terminals to a single solder ball or land. 
     Referring now to FIG. 2A, an integrated circuit  10 C in accordance with another embodiment of the present invention is depicted. Integrated circuit  10 C is a ball-grid array (BGA) package for integrated circuit die  12 A. Integrated circuit die  12 A is bonded to the top side of a substrate  13 C on which a plurality of circuit paths  20 D are fabricated via etching, plating or sputtering. Circuit paths  20 D may be formed above the top surface of substrate  13 A or may be embedded beneath the surface by laser ablating channels, embossing the substrate or other means. Circuit paths  20 D terminate in bond pads  22 C on which wires  15  are bonded, connecting integrated circuit terminals to circuit paths  20 D. A cover  14  is applied over integrated circuit die  12 A and attached to substrate  13 C to protect the assembly from environmental conditions and handling damage. A plurality of solder balls  16 A are attached to pads  19 D for connecting integrated circuit die  12 A to external circuits. Pad  19 D is connected to multiple vertical vias  18 D that lie within a cylinder having an axial cross section defined by the circumference of pad  19 D. Circuit paths  20 D individually extend from vias  18 D to connect to other power connections within the integrated circuit (generally connections to power or ground terminals on one or more semiconductor dies). 
     Referring now to FIG. 2B, a bottom view of a substrate  13 D in accordance with another embodiment of the present invention is depicted. Substrate  13 D a ball-grid array (BGA) substrate for mounting an integrated circuit die. Pad  19 F includes multiple conductive path  20 F connections which may be fabricated via etching, plating or sputtering. Circuit paths  20 F may be formed above the surfaces of substrate  13 D or may be embedded beneath the surfaces by laser ablating channels, embossing the substrate or other means. Circuit paths  20 F include connections from pad  19 C to a power plane  24 B through a via  18 F and connections to the top side of substrate  13 D through a through via  18 G providing power connections to integrated circuit terminals. 
     Referring now to FIG. 2C, an integrated circuit  10 E in accordance with another embodiment of the invention is depicted. Integrated circuit  10 E is a ball-grid array (BGA) package for integrated circuit die  12 A. Integrated circuit die  12 A is bonded to the top side of a substrate  13 E on which a plurality of circuit paths  20 G are fabricated via etching, plating or sputtering. Another circuit path  20 H connects pad  19 G to a power plane  24 C through a via  18 G. Another via  18 F provided above pad  19 G connects pad  19 G to circuit path  20 G. Circuit path  20 G an circuit path  20 H thus provide multiple connections from pad  19 G to a power plane  24 C and semiconductor die  12 A connections. A cover  14  is attached to substrate and covers semiconductor die  12 A from external environment and handling damage. 
     The above description of embodiments of the invention is intended to be illustrative and not limiting. Other embodiments will be obvious to those skilled in the art in disclosure and fall within the scope of the present invendtion.