Abstract:
A dual-output triple-Vdd charge pump as two pumped outputs that are both pumped to three times the power-supply voltage, 3×Vdd. This pumped output voltage is reduced by two p-channel inner diode drops, to 3×Vdd−2×|Vtp|. A pair of cross-coupled n-channel transistors alternately charge two inner nodes from the power supply. Inner pumping capacitors drive inner nodes between Vdd and 2×Vdd, and the cross-coupling of the gates turns off one of the cross-coupled n-channel transistors when its inner node is being driven high. A p-channel inner diode transistor connects an inner node to an outer node, causing a |Vtp| drop. The outer node is also pumped by an outer pumping capacitor that drives the outer node between 2×Vdd−|Vtp| and 3×Vdd−|Vtp|. A p-channel outer diode transistor conducts from the outer node to the pumped output node, causing another |Vtp| voltage drop. The pumped output voltage is maintained at 3×Vdd−2×|Vtp| by an output capacitor.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates to transistor circuits, and more particularly to charge pumps. 
       BACKGROUND OF THE INVENTION 
       [0002]    Charge pumps are widely used in a variety of semiconductor chips. Charge pumps are used to boost voltages of word or row lines in memory chips, allowing for a greater drive voltage and faster sensing speeds. Charge pumps are used to generate negative voltages below ground for substrate biasing. Charge pumps are also used to boost gate voltages of large bus-switch transistors, allowing a smaller transistor size to be used to drive a large load. 
         [0003]    As power-supply voltages are reduced as device sizes shrink, the lower voltage drive on transistors reduces performance. Boosting voltages is one way to compensate for this device-shrink problem. Sometimes a single charge pump stage is insufficient to reach a desired boosted voltage. Several cascaded stages of charge pumps may then be used. Boosted voltages that are several multiples above the power supply voltage (Vdd or Vcc) may be desired. 
         [0004]      FIG. 1  shows a prior-art charge pump that pumps to 4 times Vdd. A clock CLK is buffered by inverters  20 ,  22 , driving CK 2 , CK 1  between ground and Vdd. The left plates of pumping capacitors  12 ,  14 ,  16  are driven between ground and Vdd. When CK 1  is low, diode  24  charges the other plate of pumping capacitor  12  to Vdd. As CK 1  rises, diode  24  shuts off, allowing capacitive coupling through pumping capacitor  12  to raise the voltage between diodes  24 ,  26 . When CK 1  reaches Vdd, this voltage on the right plate of pumping capacitor  12  reaches a theoretical maximum of 2×Vdd. 
         [0005]    A similar pumping action by CK 2  on pumping capacitor  14  causes the right plate of pumping capacitor  14  to pump between 2×Vdd and 3×Vdd. When CK 1  is Vdd and CK 2  is ground, diode  26  conducts, conducting the 2×Vdd from pumping capacitor  12  to pumping capacitor  14 . Then as CK 2  rises from ground to Vdd, this voltage on the right plate of pumping capacitor  14  swings from 2×Vdd to 3×Vdd. 
         [0006]    A similar pumping action by CK 1  on pumping capacitor  16  causes the right plate of pumping capacitor  16  to pump between 3×Vdd and 4×Vdd. When CK 2  is Vdd and CK 1  is ground, diode  28  conducts, conducting the 3×Vdd from pumping capacitor  14  to pumping capacitor  16 . Then as CK 1  rises from ground to Vdd, this voltage on the right plate of pumping capacitor  16  swings from 3×Vdd to 4×Vdd. 
         [0007]    Output diode  30  allows load capacitor  18  to be charged when the right plate of pumping capacitor  16  is above the output pumped voltage Vp. Vp is charged up to 4×Vdd. 
         [0008]    Real-world effects reduce the pumped voltage Vp. For example, capacitor coupling ratios reduce the pumped voltage at each stage in the charge pump. The voltage on the right plate of pumping capacitor  12  is reduced by the ratio of the capacitance of pumping capacitor  12  to the sum or parasitic capacitances on the node connected to the right plate of pumping capacitor  12 , which includes diodes  24 ,  26  and any wiring capacitances. The voltages on the right plates of pumping capacitors  14 ,  16  are similarly reduced by coupling ratios at each node. Finally, load capacitor  18  may be so large that the pumping current through diode  30  is unable to fully pump up Vp. Current may also leak out from Vp, such as from transistors into bulk or substrate nodes. The final pumped voltage Vp is usually much less than the theoretical maximum of 4×Vdd. 
         [0009]    Sense circuit  10  can receive pumped voltage Vp and compare it to a target voltage, and then shut off oscillator  15  when Vp is above the target voltage. Clock CLK is generated by oscillator  15 ; thus charge pumping is disabled by sense circuit  10 . 
         [0010]      FIG. 2  shows a prior art multi-stage charge pump implemented with n-channel transistors. Diodes  24 ,  26 ,  28 ,  30  of  FIG. 1  are implemented as n-channel transistors  32 ,  34 ,  36 ,  38  in  FIG. 2 . Each transistor has its gate and drain connected together, allowing current to flow as long as the source voltage is one threshold voltage (Vt) below the drain/gate voltage. However, this threshold voltage Vt is larger than the nominal Vtn since the source is above ground due to the body effect. Each of transistors  32 ,  34 ,  36 ,  38  can have a drop of about  1  volt, so pumped voltage Vp is reduced by about 4 volts, to 4×Vdd−4×Vt. 
         [0011]    While useful, such multi-stage charge pumps suffer from diode voltage drops using n-channel transistors for the diodes. The transistor thresholds are also increased due to the body effect. Capacitor coupling ratios are difficult to maintain unless huge pumping capacitors are used relative to parasitic capacitances. This increases area and expense. 
         [0012]    What is desired is a charge pump circuit that uses p-channel transistors rather than n-channel transistors for at least some of the diodes. A charge pump that can pumps to several multiples of Vdd is desired. A charge pump that can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process and integrated with other circuits on a semiconductor chip is desirable. A charge pump with multiple outputs is also desired. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  shows a prior-art charge pump that pumps to 4 times Vdd. 
           [0014]      FIG. 2  shows a prior art multi-stage charge pump implemented with n-channel transistors. 
           [0015]      FIG. 3  is a schematic diagram of a dual-output triple-Vdd charge pump. 
           [0016]      FIG. 4  is a functional diagram of the dual-output triple-Vdd charge pump. 
           [0017]      FIG. 5  is a timing diagram of operation of the dual-output triple-Vdd charge pump of  FIG. 3 . 
           [0018]      FIG. 6  is a graph of the transient response of the dual-output triple-Vdd charge pump of  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    The present invention relates to an improvement in charge pump circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. 
         [0020]      FIG. 3  is a schematic diagram of a dual-output triple-Vdd charge pump. A clock CLK drives inverters  70 ,  72  which drive CK 2 , CK 1  between Vdd and ground. CLK may be disabled by a sense circuit and oscillator as shown in  FIG. 1  by comparing either pumped output voltage VP 1  or VP 2  to a target voltage. The target voltage may be generated by a band-gap voltage generator or other reference circuit, or may be an external input. 
         [0021]    CK 1  and CK 2  pump on pumping capacitors  64 ,  62 , respectively, swinging their bottom plates between ground and Vdd. The top plates of pumping capacitors  64 ,  62  are nodes V 1 , V 2 , respectively, which receive power-supply current through cross-coupled n-channel transistors  52 ,  50 , respectively. The gate of cross-coupled n-channel transistor  50  is node V 1  while its source is node V 2 . The gate of cross-coupled n-channel transistor  52  is node V 2  while its source is node V 1 . The drains of cross-coupled n-channel transistors  50 ,  52  is power supply Vdd while their bulk or substrate nodes are grounded. 
         [0022]    Nodes V 1 , V 2  are pumped to 2×Vdd by pumping capacitors  62 ,  64 . Since the gates of cross-coupled n-channel transistors  52 ,  50  are at the higher pumped voltages V 1 , V 2 , these transistors do not have the threshold voltage Vt drop. Cross-coupled n-channel transistors  52 ,  50  toggle on and off during pumping due to the cross-coupled gate connection to prevent back-flow to Vdd from nodes V 1 , V 2 . 
         [0023]    P-channel inner diode transistor  44  has its gate and bulk nodes connected to node V 3 , allowing current to flow from its source node V 1  when V 1  is more than |Vtp| above its drain, node V 3 . Otherwise back-current flow is blocked by p-channel inner diode transistor  44 . Outer pumping capacitor  66  pumps node V 3  higher by an additional Vdd swing. 
         [0024]    When CK 2  is low, cross-coupled n-channel transistor  52  is off and p-channel inner diode transistor  44  turns on to drive current to node V 3  at 2×Vdd−Vtp. When CK 2  goes high, cross-coupled n-channel transistor  52  is on and p-channel inner diode transistor  44  turns off, allowing outer pumping capacitor  66  to pump node V 3  to 3×Vdd−Vtp. 
         [0025]    P-channel outer diode transistor  46  has its gate and bulk nodes connected to first pumped output node VP 1 , allowing current to flow from its source node V 3  to charge first load capacitor  56  when V 3  is more than |Vtp| above its drain, node VP 1 . Otherwise back-current flow is blocked by p-channel outer diode transistor  46 . There is a voltage drop of |Vtp| through each of p-channel inner diode transistor  44  and p-channel outer diode transistor  46 , so the voltage of first output pumped voltage VP 1  is limited to 3×Vdd−2×|Vtp|. 
         [0026]    A second output pumped voltage VP 2  on load capacitor  54  is also generated from node V 2 . P-channel inner diode transistor  42 , p-channel outer diode transistor  40 , and outer pumping capacitor  60  operate in a similar manner as described for transistors  44 ,  46  and capacitor  66 , using CK 1  rather than CK 2 . The voltage of second output pumped voltage VP 2  is also limited to 3×Vdd−2×|Vtp|. 
         [0027]      FIG. 4  is a functional diagram of the dual-output triple-Vdd charge pump. P-channel inner diode transistors  42 ,  44 , and p-channel outer diode transistors  40 ,  46  are replaced with diodes  82 ,  84  and  80 ,  86 , respectively. These diodes prevent back-current flow. The actual p-channel transistors have a |Vtp| voltage drop compared with an idealized diode, which reduces the output pumped voltages. 
         [0028]    When CK 1  goes high and CK 2  goes low, inner pumping capacitor  64  drives node V 1  higher while inner pumping capacitor  62  drives node V 2  lower. The higher V 1  applied to the gate turns on cross-coupled n-channel transistor  50  while the lower V 2  turns off cross-coupled n-channel transistor  52 . Node V 1  is isolated from power supply Vdd by cross-coupled n-channel transistor  52 , allowing inner pumping capacitor  64  to further raise the voltage of V 1 . The higher voltage V 1  turns on diode  84 , allowing current to flow from node V 1  to node V 3 , raising the voltage of node V 3 . At the same time, the lower CK 2  applied to outer pumping capacitor  66  fully charges outer pumping capacitor  66  through diode  84 . 
         [0029]    Diode  82  is off since node V 4  is higher than node V 2  as V 2  goes lower with CK 2  going lower. However, current from Vdd passes into node V 2  to charge the top plate of inner pumping capacitor  62  through cross-coupled n-channel transistor  50  which is turned on. 
         [0030]    When CK 2  goes high and CK 1  goes low, inner pumping capacitor  62  drives node V 2  higher while inner pumping capacitor  64  drives node V 1  lower. The higher V 2  applied to the gate turns on cross-coupled n-channel transistor  52  while the lower V 1  turns off cross-coupled n-channel transistor  50 . Node V 2  is isolated from power supply Vdd by cross-coupled n-channel transistor  50 , allowing inner pumping capacitor  62  to further raise the voltage of V 2 . The higher voltage V 2  turns on diode  82 , allowing current to flow from node V 2  to node V 4 , raising the voltage of node V 4 . At the same time, the lower CK 1  applied to outer pumping capacitor  60  fully charges outer pumping capacitor  60  through diode  82 . 
         [0031]    Diode  84  is off since node V 3  is higher than node V 1  as V 1  goes lower with CK 1  going lower. However, current from Vdd passes into node V 1  to charge the top plate of inner pumping capacitor  64  through cross-coupled n-channel transistor  52  which is turned on. 
         [0032]    When V 3  is higher than VP 1 , output diode  86  turns on to charge first load capacitor  56 , which maintains first output pumped voltage VP 1 . Likewise, When V 4  is higher than VP 2 , output diode  80  turns on to charge second load capacitor  54 , which maintains second output pumped voltage VP 2 . 
         [0033]      FIG. 5  is a timing diagram of operation of the dual-output triple-Vdd charge pump of  FIG. 3 . In this example the power-supply voltage Vdd is 3 volts. When CLK pulses high, CK 2  pulses low to ground and CK 1  pulses high to 3 volts. When CLK pulses low, CK 1  pulses low to ground and CK 2  pulses high to 3 volts. 
         [0034]    Inner node V 1  is charged to 3 volts during the down stroke of CK 1  when cross-coupled n-channel transistor  52  is on, and is pumped by inner pumping capacitor  64  to 6 volts (2×Vdd) by the up stroke of CK 1  when cross-coupled n-channel transistor  52  is turned off by the down stroke of CK 2 . 
         [0035]    When V 1  is high, p-channel inner diode transistor  44  turns on, driving outer node V 3  to 2×Vdd−|Vtp| or about 5.4 volts. Then as CK 2  rises, p-channel inner diode transistor  44  turns off and outer pumping capacitor  66  drives outer node V 3  up by an additional swing of Vdd, to 3×Vdd−|Vtp| or about 8.4 volts when Vtp is about 0.6 volt. 
         [0036]    First output pumped node VP 1  is charged to one p-channel inner diode threshold less than the maximum of outer node V 3 , or to 3×Vdd−2×|Vtp| or about 7.8 volts. 
         [0037]      FIG. 6  is a graph of the transient response of the dual-output triple-Vdd charge pump of  FIG. 3 . When the oscillator turns on to pulse CLK, the first output pumped node VP 1  is gradually charged until it reaches its maximum of about 7.8 volts. This value is reached within about 1 millisecond. 
       Alternate Embodiments  
       [0038]    Several other embodiments are contemplated by the inventor. For example. Load capacitors may represent parasitic capacitances on an output node, such as an n-channel gate to drain/source and substrate capacitances of downstream transistors and wiring capacitances. An actual load capacitor may not be present. Careful design and layout should be used to control capacitive coupling ratios and the efficiency of the actual circuit. Wiring lengths can be kept to a minimum and the sizes of pumping capacitors kept larger than parasitic capacitances. The charging capacitor may be replaced by an n-channel gate to drain/source parasitic capacitor or a p-channel gate to drain/source and body parasitic capacitor. 
         [0039]    The charge pump may be disabled to save power, such as during power-down modes, or when a sense circuit determines that a target output voltage has been reached. Various filters may be added to smooth responses. |Vtp| is the absolute value of the p-channel inner diode threshold voltage, which can vary with process and other conditions. Sometimes the threshold may be referred to without mention of the absolute value which is understood. The bulk or body bias voltage may also change this threshold voltage. Capacitors could include several capacitors in parallel rather than be a single capacitor. Likewise, transistors may have several legs or segments connected together. 
         [0040]    The charge pump can be connected to Vdd or to any fixed voltage which is generated by an internal voltage regulator circuit. Transistor device sizes can be adjusted. Buffers and inversions can be added or removed. Additional levels of boosting could be added to boost to four, five, or more times Vcc. The VP 1  and/or VP 2  voltage can be adjusted to match the target boost voltage, or VP 1  or VP 2  can be some other elevated voltage that does not exactly match the boost voltage. Some conduction through keeper transistors could then occur. The boosted output voltages VP 1  and VP 2  could be different voltages. The clocks could be exact inverses or could have delays. Clocks may be buffered, inverted, or divided into segments in a variety of ways and yet be the same clock. 
         [0041]    The terms source and drain are interchangeable. The relative voltages on source/drain nodes determine which is considered to be the source and which is considered to be the drain at any instant in time. As voltages change, a particular node may go from acting as a source to acting as a drain. 
         [0042]    The background of the invention section may contain background information about the problem or environment of the invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant. 
         [0043]    Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machine, computer, or other device and are not intended to be performed solely by humans without such machine assistance. Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result. 
         [0044]    Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC Sect. 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claim elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word “means” are not intended to fall under 35 USC Sect. 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line. 
         [0045]    The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.