Abstract:
In a frequency synthesizer, a voltage controlled oscillator has a terminal and oscillates a signal whose frequency corresponds to a control signal applied to the terminal. A first frequency divider divides the frequency of the signal outputted from the voltage controlled oscillator so as to output a first frequency-divided signal. The first frequency-divided signal has a divided frequency. A comparator compares a phase of the first frequency-divided signal with that of a reference signal so as to output a difference signal representing a difference between the phase of the first frequency-divided signal and that of the reference signal. A loop filter smoothes the difference signal outputted from the comparator so as to output the smoothed signal as the control signal to the terminal of the voltage controlled oscillator. A frequency division unit divides the frequency of the signal outputted from the voltage control oscillator so as to output a second frequency-divided signal. The second frequency-divided signal has a divided frequency. A mixer unit mixes the second frequency-divided signal outputted from the frequency division unit and the signal outputted from the voltage control oscillator so as to output a mixed signal.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a frequency synthesizer used to a mobile radio device and a method of generating a frequency-divided signal, which are capable of stably obtaining an excellent C/N characteristic (ratio) over a wide frequency band.  
           [0003]    2. Description of the Related Art  
           [0004]    In cases of a mobile radio device such as a cellular phone, a frequency synthesizer is used for generating an arbitrary local oscillating frequency from a reference signal. Recently, it is desired to realize a cellular phone itself capable of dealing with a plurality of mobile communication systems, such as GSM (Grobal System for Mobile Communication), IMT (International Mobile Communications) 2000 and the like, whose frequency bands are different from each other. To make the cellular phone deal with the plurality of mobile communication systems, the frequency synthesizer must be operated over a wide frequency range.  
           [0005]    The frequency synthesizer used to these cellular phones, as shown in FIG. 1, comprises a voltage controlled oscillator  1  for setting a signal into oscillation, signal whose frequency corresponds to a voltage (Vt) applied to its frequency control voltage terminal, thereby permitting a frequency band of the oscillating signal (output signal) to be changed according to the frequency band control signal. The voltage controlled oscillator  1  is referred to as “VCO”, hereinafter.  
           [0006]    The frequency synthesizer also comprises an adjustable frequency divider  2  for dividing a frequency of the output signal from the VCO  1 , whose frequency is referred to as “fvco” hereinafter, and a phase comparator  3  for comparing a phase of the output signal (frequency-divided signal) from the frequency divider  2 , whose frequency is referred to as “fdiv” hereinafter, with that of a reference signal, whose frequency is referred to as “fref” hereinafter, thereby outputting a signal representing a difference between the phase of the output signal (fdiv) and that of the reference signal (fref). The frequency synthesizer comprises a loop filter  4  for smoothing the signal outputted from the phase comparator  3 .  
           [0007]    [0007]FIG. 2 is a circuit diagram indicating a principle upon which the VCO  1  operates. The VCO  1  comprises a capacitor C 0 , a negative resistor −R and an inductor L, which are connected in parallel with each other.  
           [0008]    The VCO  1  also comprises a capacitor C 1  and a variable capacitor Cv, which are connected in series with each other. The in-series portion of capacitor C 1  and the variable capacitor Cv is connected with the capacitor C 0  in parallel. The VCO  1  further comprises a capacitor C 2  and a switch SW which are connected in series with each other. The in-series portion of the capacitor C 2  and the switch SW is connected with the capacitance C 0  in parallel.  
           [0009]    Next, the operations of the circuit diagram in FIG. 2 are explained.  
           [0010]    The in-parallel portion of the negative resistor −R, the capacitance C 0  and the inductor L is taken as a parallel circuit with an active element, such as a transistor or the like, and the active element is subjected to source voltage to generate power. The negative resistor −R is different from a usual resistor because the negative resistor −R generates power. An oscillating frequency of the VCO  1 , that is, the frequency fcvo of the output signal from the VCO  1  is expressed as the equation (1) in cases where the switch SW is OFF or expressed as the equation (2) in cases where the switch SW is ON: 
             fvco|   SW=OFF =1/[2π{square root}{square root over ( )}{ L (C 0 +C 1 ·Cv/(C 1 +Cv))}]  (1) 
           fvco| SW=ON =1/[2π{square root}{square root over ( )}{ L (C 0 +C 2 +C 1 ·Cv/(C 1 +Cv))}]  (2) 
           [0011]    This shows that the VCO  1  permits the oscillating frequency band to vary with the ON/OFF of the switch SW.  
           [0012]    When the VCO is applied to the frequency synthesizer, shown in FIG. 2, the control voltage is applied to the variable capacitor Cv, causing the capacitance of the variable capacitor Cv to vary, thereby making vary the oscillating frequency fvco.  
           [0013]    In this frequency synthesizer shown in FIG. 1, varying the division frequency ratio of the variable frequency divider  2  causes the frequency fdiv of the output signal from the frequency divider  2  to be varied so that the phase comparator  3  outputs a phase difference signal between the output signal (fdiv) and the reference signal (fref).  
           [0014]    The outputted phase difference signal is sent through the loop filter  4  to the VCO  1 , causing the voltage Vt of the frequency control voltage terminal to be varied, thus varying the output signal (fvco).  
           [0015]    That is, the frequency synthesizer is configured as negative feedback loop so that, when finally the phase of the reference signal (fref and that of the output signal (fdiv) coincide with each other, the phase of the output signal (fdiv) is locked to that of the reference signal (fref), whereby the frequency of the output signal (fvco) from the VCO  1  keeps to be stable.  
           [0016]    Adjusting the frequency band control signal so as to set it in oscillation in a desired frequency band, and adjusting the dividing ratio of the variable frequency divider  2  permit the phase of the output signal (fvco) to be locked in the desired frequency band.  
           [0017]    In the frequency synthesizer with the above function for switching the frequency band, however, dividing the capacitance in the VCO causes the frequency band to be adjusted so that the control sensitivity of the VCO, which represents a variation width of the oscillating frequency per 1 V of the control voltage, whose unit is [Hz/V], is simultaneously varied, whereby the C/N characteristic of the frequency synthesizer must be varied according to the selected (switched) frequency band.  
           [0018]    Switching only the capacitance of the variable capacitor in VCO is insufficient to switch widely the frequency band so that it is necessary to switch the inductance of the inductor in VCO, making increase the circuit size of the VCO.  
           [0019]    When the frequency band is forced to be switched by only switching the capacitance in the VCO, the balance of the inductance and the capacitance is deteriorated to weak the oscillating power, thereby decreasing the output level of the VCO and, in some cases, causing the oscillating of the VCO to be stopped.  
           [0020]    Adding a switch or the like into the resonant circuit causes the ON resistance and the parasitic capacitance of the added switch to decrease the quality factor Q of the oscillator, thereby deteriorating the C/N of the VCO itself.  
           [0021]    In addition, in cases of using the above frequency synthesizer in a mobile radio device, the frequency band used in the frequency synthesizer makes change the communication quality of the mobile radio device.  
         SUMMARY OF THE INVENTION  
         [0022]    The present invention is directed to overcome the foregoing disadvantages. Accordingly, it is an object of the present invention to provide a frequency synthesizer and a method of generating a frequency-divided signal, which are capable of switching its frequency band without greatly changing the C/N characteristic thereof.  
           [0023]    According to one aspect of the present invention, there is provided a frequency synthesizer comprising: a voltage controlled oscillator having a terminal for oscillating a signal whose frequency corresponds to a control signal applied to the terminal; a first frequency divider for dividing the frequency of the signal outputted from the voltage controlled oscillator so as to output a first frequency-divided signal, said first frequency-divided signal having a divided frequency; a comparator for comparing a phase of the first frequency-divided signal with that of a reference signal so as to output a difference signal representing a difference between the phase of the first frequency-divided signal and that of the reference signal; a loop filter for smoothing the difference signal outputted from the comparator so as to output the smoothed signal as the control signal to the terminal of the voltage controlled oscillator; a frequency division unit for dividing the frequency of the signal outputted from the voltage control oscillator so as to output a second frequency-divided signal, said second frequency-divided signal having a divided frequency; and a mixer unit for mixing the second frequency-divided signal outputted from the frequency division unit and the signal outputted from the voltage control oscillator so as to output a mixed signal.  
           [0024]    According to another aspect of the present invention, there is provided a method of generating a frequency divided signal, comprising the steps of: oscillating by a voltage controlled oscillator a signal whose frequency corresponds to a control signal, said voltage controlled oscillator having a terminal, said control signal being applied to the terminal; dividing by a first frequency divider the frequency of the signal outputted from the voltage controlled oscillator so as to output a divided signal, said divided signal having a divided frequency; comparing by a comparator a phase of the divided signal with that of a reference signal so as to output a difference signal representing a difference between the phase of the divided signal and that of the reference signal; smoothing the difference signal outputted from the comparator so as to supply the smoothed signal as the control signal to the terminal of the voltage controlled oscillator; and mixing by a mixer unit a frequency-divided signal and the signal outputted from the voltage control oscillator so as to output a mixed signal, said frequency-divided signal being obtained by dividing the frequency of the signal outputted from the voltage controlled oscillator.  
           [0025]    According to one and another aspects of the present invention, only controlling the frequency division ratio of the frequency division unit and the operating mode (upconvert mode or downconvert mode) of the mixer unit permits the frequency band to be switched, thereby setting the frequency division ratio and the operating mode in no relation to a PLL (Phase Locked Loop). This causes, even if the frequency band is switched, the characteristic of the loop to be invariable, thereby making the control sensitivity of the voltage controlled oscillator and the C/N characteristic thereof invariable, too. In addition, the oscillating power of the voltage controlled oscillator is prevented from decreasing and the oscillating operation thereof is prevented from stopping. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]    Other objects and aspects of the present invention will become apparent from the following description of an embodiment with reference to the accompanying drawings in which:  
         [0027]    [0027]FIG. 1 is a block diagram schematically showing a configuration of a conventional frequency synthesizer;  
         [0028]    [0028]FIG. 2 is a circuit diagram indicating a principal upon which a VCO shown in FIG. 1;  
         [0029]    [0029]FIG. 3 is a block diagram schematically showing a configuration of a frequency synthesizer according to a first embodiment of the present invention;  
         [0030]    [0030]FIG. 4 is a circuit diagram indicating a principal upon which a VCO shown in FIG. 3 operates according to the first embodiment of the present invention;  
         [0031]    [0031]FIG. 5 is a circuit diagram showing a configuration of a mixer unit shown in FIG. 3 according to the first embodiment of the present invention; and  
         [0032]    [0032]FIG. 6 is a block diagram schematically showing a configuration of a frequency synthesizer according to a first embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF EMBODIMENTS  
       [0033]    Embodiments of the present invention will be described hereinafter with reference to the accompanying drawings.  
         [0034]    Incidentally, elements which are the same as those shown in FIG. 1 are assigned to the same characteristic numerals of the elements shown in FIG. 1, thereby omitting the detailed description.  
         [0035]    (First Embodiment)  
         [0036]    A frequency synthesizer F 1  according to a first embodiment of the present invention, as shown in FIG. 3, comprises a VCO  1 A, a frequency divider  2 , a phase comparator  3  and a loop filter  4 , which are similar to the structure shown in FIG. 1.  
         [0037]    In addition, the frequency synthesizer F 1  comprises a frequency divider  5  for dividing an output signal from the VCO  1  on the basis of the frequency division ratio previously set according to the control signal, and a mixer unit  6  for mixing an output signal from the frequency divider  2  and the output signal from the VCO  1 A, which are the differential point as compared with the conventional frequency synthesizer shown in FIG. 1.  
         [0038]    Another different point between the frequency synthesizer F 1  of the present invention and a conventional frequency synthesizer is that the VCO  1 A comprises no frequency switching function.  
         [0039]    That is, FIG. 4 is a circuit diagram indicating a principle upon which the VCO  1 A operates.  
         [0040]    Different point between the VCO  1 A of the first embodiment and the VCO  1  shown in FIG. 2 is that the switch SW and the variable capacitor C 2  corresponding to the frequency switching function are not provided for the VCO  1 A. Remained points of the VCO  1 A except for the different point are the same as the VCO  1 .  
         [0041]    Therefore, the frequency fcvo of the output signal from the VCO  1  is expressed as the equation (3): 
           fvco= 1/[2π{square root}{square root over ( )}{ L (C 0 +C 1 ×Cv/(C 1 +Cv)}]  (3) 
         [0042]    In this first embodiment, in order to simplify the explanation, the frequency divider  5  can switch the frequency division ratio into 1/m1 or 1/m2 so that the frequency divider  5  multiplies the frequency fvco of the output signal by the frequency division ratio, whereby to output the frequency-divided signal whose frequency is taken as fvco/m (m is m1 or m2). The mixer unit  6  is an image reject mixer unit capable of being switchably served as upconvert mixer and as a downconvert mixer according to the phase control signal.  
         [0043]    Next, the operations of the frequency divider shown in FIG. 3 are explained.  
         [0044]    The VCO  1 A turns into the phase lock state through the process which is described as the operations of the conventional frequency synthesizer shown in the Prior Art.  
         [0045]    When the mixer unit  6  is used as the upconvert mixer, in a case where the frequency division rate is set to m1 or m2, the frequency of the output signal from the mixer unit  6  is represented as fvco+fvco/m1 or fvco+fvco/m2 so that switching the frequency division ratio of the frequency divider  5  permits the frequency band of the output signal from the mixer unit  6  to be varied within the range between the fvco/m1 and the fvco/m2.  
         [0046]    When the mixer unit  6  is used as the downconvert mixer, in a case where the frequency division rate is set to m1 or m2, the frequency of the output signal from the mixer unit  6  is represented as fvco−fvco/m1 or fvco−fvco/m2 so that switching the frequency division ratio of the frequency divider  5  permits the frequency band of the output signal from the mixer unit  6  to be varied within the range between fvco/m2 and fvco/m1 to be varied.  
         [0047]    With secured frequency division ratio, that is, secured m1, it is possible to switch the mixer into the upconvert mixer and the downconvert mixer so as to switch the frequency band of the output signal from the mixer unit  6 . At this time, the frequency of the output signal from the mixer unit  6  turns into a frequency of (fvco+fvco/m1) or (fvco−fvco/m1), thereby making it possible to vary the frequency band corresponding to two times the frequency of fvco/m1.  
         [0048]    It is usually known that dividing a frequency of a signal causes its C/N characteristic to be increased. In the frequency synthesizer F 1  of the first embodiment according to the present invention, because of mixing the frequency-divided signal outputted from the mixer unit  6  and the output signal therefrom, the C/N characteristic of the output signal of the mixer unit  6  is determined by the C/N characteristic of the output signal from the VCO  1 A so that, even when varying the frequency band, the C/N of the output signal from the mixer unit  6  is not greatly changed.  
         [0049]    Next, the structure of the mixer unit  6  is explained in detail in reference to FIG. 5. The mixer unit  6  comprises a first 90 degree phase shifter  61  for dividing the output signal fvco from the VCO  1 A into signals S 1   a  (cos α) and S 1   b  (sin α). Between the phase (cos α) of the signal S 1   a  (cos α) and that (sin α) of the signal S 1   b  (sin α), 90 degree phase shift occurs.  
         [0050]    The mixer unit  6  comprises a second 90 degree phase shifter  62  for dividing the output signal from the frequency divider  5  into signals S 2   a  (cos β) and S 2   b  (sin β). Between the phase (cos β) of the signal S 2   a  (cos β) and that (sin β) of the signal S 2   b   1  (sin β), 90 degree phase shift occurs.  
         [0051]    The mixer unit  6  also comprises a first mixer  63  for mixing the signal S 1   a  (cos α) outputted as one side from the first shifter  61  and the signal S 2   a  (cos β) outputted as one side from the second shifter  62 , and a second mixer  64  for mixing the signal S 1   b  (sin α) outputted as other side from the first shifter  61  and the signal S 2   b   1  (sin β) outputted as other side from the second shifter  62 . The mixer unit  6  further comprises an adder  65  for adding the output signals from the first and second mixers  63  and  64 .  
         [0052]    The phase control signal is inputted in the second 90 degree shifter  62  so that the 90 degree shifter  62  can output a signal S 2   b   2  (−sin β) whose phase (−sin β) is reversed from the phase (sin α) of the signal S 2   b   1  (sin β).  
         [0053]    That is, in this embodiment, the phase shifter  62  can switchably output the signal S 2   b   1  (sin β) or the signal S 2   b   2  (−sin β) according to the content of the phase control signal.  
         [0054]    When integrating the phase shifter in IC (Integrated Circuit), the phase shifter is usually configured as a differential circuit so that only switching positive phase signal and negative phase signal simply permits the phase to be reversed.  
         [0055]    Next, the operations of the mixer unit  6  is explained by using calculation equations.  
         [0056]    The first mixer  63  mixes the output signal S 1   a  (cos α) outputted from the first shifter  61  and the signal S 2   a  (cos β) outputted from the second shifter  62  so as to output a signal S 10  represented as the equation (4). 
           S 10=cos α cos β=½{cos (α+β)+cos (α−β)}  (4) 
         [0057]    When the content of the phase control signal inputted in the phase shifter  62  represents that the signal S 2   b   1  (sin β) is selected, the second mixer  64  mixes the output signal S 1   b  (sin α) outputted from the first shifter  61  and the signal S 2   b   1  (sin β) outputted from the second shifter  62  so as to output a signal S 11  represented as the equation (5). 
           S 11=sin α sin β=½{cos (α+β)+cos(α−β)}  (5) 
         [0058]    The equations (4) and (5) clearly shows that the output signal S 12  from the adder  65 , which is the same as the output signal from the mixer unit  6 , is represented as the equation (6). 
           S 12=cos (α+β)  (6) 
         [0059]    This equation (6) clearly shows that the image band of cos (α−β) is rejected so that the mixer unit  6  operates as the upconvert mixer, thereby outputting the signal whose frequency is fvco+fvco/m.  
         [0060]    On the other hand, when the content of the phase control signal inputted in the phase shifter  62  represents that the signal S 2   b   2  (−sin β) is selected, the second mixer  64  mixes the output signal S 1   b  (sin α) outputted from the first shifter  61  and the signal S 2   b   2  (−sin β) outputted from the second shifter  62  so as to output a signal S 12  represented as the equation (7). 
           S 12=−sin α sin β=−½{cos (α+β)−cos (α−β)}  (7) 
         [0061]    The equations (4) and (7) clearly shows that the output signal S 12  from the adder  65 , which is the same as the output signal from the mixer unit  6 , is represented as the equation (8). 
           S 12=cos (α−β)  (8) 
         [0062]    This equation (8) clearly shows that the image band of cos (α+β) is rejected so that the mixer unit  6  operates as the downconvert mixer, thereby outputting the signal whose frequency is fvco−fvco/m.  
         [0063]    As described above, in the frequency synthesizer F 1 , only controlling the frequency division ratio of the frequency divider  5  and the operating mode (upconvert mode or downconvert mode) of the mixer unit  6  permits the frequency band to be switched, thereby setting the frequency division ratio and the operating mode in no relation to a PLL (Phase Locked Loop) corresponding to the structure shown in FIG. 3. This causes, even if the frequency band is switched, the characteristic of the loop to be invariable, thereby making the control sensitivity of the VCO  1 A and the C/N characteristic thereof invariable, too.  
         [0064]    The VCO  1 A has no frequency switching function and no elements required therefor so that it is possible to improve the quality factor Q of the VCO  1 A, permitting the C/N characteristic of the VCO  1 A itself to be improved. In addition, the oscillating power of the VCO  1 A is prevented from decreasing and the oscillating operation thereof is prevented from stopping.  
         [0065]    Because the frequency of the output signal from the mixer unit  6  is remarkably varied, the image reject mixer unit is used as the mixer unit  6  so that no variable band filter is required for preventing the image band on an output side of the mixer unit  6 .  
         [0066]    It is possible to switchably use the mixer unit  6  as the upconvert mixer and the downconvert mixer, permitting the frequency band of the frequency synthesizer F 1  to be widely adjusted.  
         [0067]    Incidentally, in the above description, the frequency divider can switch the frequency division ratio into either one of two values, whereas according to the similar consideration, it is possible to switch the frequency division ratio into one of numbers of values. In this case, it is possible to improve the freedom of setting the switching width of the frequency band.  
         [0068]    In cases where the frequency divider  5  has function for switching its frequency division ratio, no switching function between the upconvert and downconvert may be provided for the frequency synthesizer F 1 , making compact the circuit size thereof.  
         [0069]    The variable frequency divider  2  may be configured to temporally vary its frequency division ratio, like as a fractional-N system usually known, so as to obtain the same effects. In this case, it is possible to set the frequency steps obtained from the output signal from the VCO  1 A so that each step width is shorter than that of the reference signal (fref), increasing the freedom of setting the frequency division ratio of the frequency divider  5 .  
         [0070]    In addition, installing the frequency synthesizer F 1  according to the first embodiment into a mobile radio device permits the communication quality to be stable in no relation to the frequency band to be used.  
         [0071]    (Second embodiment)  
         [0072]    First embodiment)  
         [0073]    A frequency synthesizer F 2  according to a second embodiment of the present invention, as shown in FIG. 6, comprises a frequency divider  2 A having a pre-scalar  21  and a frequency division unit  22  whose output terminal is connected with the mixer unit  6 .  
         [0074]    The pre-scalar  21  previously divides the frequency fvco of the output signal from the VCO  1 A by the frequency division ratio of m (m1 or m2) so at to output the output signal whose frequency is represented as fvco/m to the frequency division unit  22  and the mixer unit  6 .  
         [0075]    The frequency division unit  22  divides the frequency fvco/m of the output signal from the pre-scalar  21  by the frequency division ratio which is (1/m) times the frequency division ratio of the frequency divider  2  shown in FIG. 3.  
         [0076]    The configuration of the frequency divider  2 A is the differential point as compared with the frequency synthesizer F 1  shown in FIG. 3, so that elements which are the same as those shown in FIGS. 1 and 3 are assigned to the same characteristic numerals of the elements shown in FIGS. 1 and 3, thereby omitting the detailed description.  
         [0077]    In this structure of the second embodiment, no frequency divider  5  is required.  
         [0078]    Operations of the frequency synthesizer F 2  are explained.  
         [0079]    In this second embodiment, the frequency fvco of the output signal from the VCO  1 A is inputted in the pre-scalar  21  so as to be divided into the frequency fvco/m so that the output signal whose frequency is fvco/m is outputted to the mixer unit  6 , like the first embodiment, and the frequency division unit  22 .  
         [0080]    The frequency fvco/m of the output signal from the pre-scalar  21  is divided by the frequency division unit  22  on the basis of the frequency division ratio which is (1/m) times the frequency division ratio of the frequency divider  2  so that the frequency of the output signal from the frequency divider  2 A (frequency division unit  22 ) is set to the fdiv which is the same as that of the output signal from the frequency divider  2 .  
         [0081]    Furthermore, because the mixer unit  6  executes the same operations as the first embodiment, it is possible to obtain the above effects described above without using the frequency divider  5 .  
         [0082]    A mobile radio device such as cellular phone or the like has an oscillating frequency which is the range of hundreds MHz to several GHz so that the power consumption of each frequency divider for dividing the frequency is made large. When the frequency synthesizer F 2  according to the second embodiment is installed into a mobile radio device, it is possible to decrease a number of frequency dividers for dividing the oscillating frequency of the VCO, making it possible to decrease the power consumption in the mobile radio device.  
         [0083]    While there has been described what is at present considered to be the preferred embodiment and modifications of the present invention, it will be understood that various modifications which are not described yet may be made therein, and it is intended to cover in the appended claims all such modifications as fall within the true spirit and scope of the invention.