Abstract:
A fully digital glitch-free clock multiplexer includes a monitoring circuit that automatically switches to a newly selected clock, after a defined time period, from a currently selected clock, when the currently selected clock is absent. A maximum time limit is calculated based on a min and max clock frequency ratio. The monitoring circuit operates only when the clock is being switched. This provides flexibility to software to switch the clock any time whether or not the current clock is present, and prevents the system from hanging in the absence of the clock.

Description:
BACKGROUND 
     The present invention relates generally to integrated circuits, and more particularly, to a clock multiplexer for generating a glitch-free clock signal. 
     Integrated circuits (ICs) such as a system on a chip (SoC) and application specific integrated circuits (ASICs) generally include two or more clock generators so that a malfunction or failure in one clock generator does not disable the system. Further, systems such as audio processors require inputs at different clock frequencies for tuning an audio frequency. Hence, such systems include several clock generators and a clock switching system. The clock generators provide clock signals at different frequencies and the clock switching system switches between the clock signals. The clock switching system includes a multiplexer to select and output one of the clock signals based on a select signal. 
     If a glitch occurs during a clock signal switching operation, data values within the IC may be corrupted. A known technique to avoid such glitches is to include a delay circuit in the clock switching system. During the switching operation, the delay circuit delays the clock output signal to prevent glitches from effecting the clock output signal. However, the delay prevents the clock switching system from switching from the currently selected clock signal to another clock signal before the currently selected clock signal goes inactive (i.e., when the currently selected clock signal is absent or is malfunctioning). 
     A known technique to overcome the above-mentioned problem is to include a monitoring circuit to detect the absence of the currently selected clock signal so that a controller or processor can change the select signal so that the multiplexer selects and outputs another clock signal. However, the addition of the monitoring circuit increases circuit area. Further, if the monitoring circuit malfunctions or fails, then there will be a failure in the clock switching system. 
     Another known technique includes resetting the clock generator when the currently selected clock signal is inactive. However, this technique is applicable only for a system that has two or more clock generators. 
     It would be advantageous to have a clock switching system that provides switching between multiple clock signals and avoids glitches. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements. 
         FIG. 1  is a schematic block diagram of a clock switching system that includes first and second switchover control circuits and a first timeout control circuit in accordance with an embodiment of the present invention; 
         FIG. 2  is a schematic block diagram of the first switchover control circuit of  FIG. 1  in accordance with an embodiment of the present invention; 
         FIGS. 3A and 3B  are schematic block diagrams of a reset synchronizer of the first switchover control circuit of  FIG. 2  and a synchronizer of the first switchover control circuit of  FIG. 2 , respectively, in accordance with an embodiment of the present invention; 
         FIGS. 4A and 4B  are schematic block diagrams of a positive edge detector of the first switchover control circuit of  FIG. 2  and a negative edge detector of the first switchover control circuit of  FIG. 2 , respectively, in accordance with an embodiment of the present invention; 
         FIG. 5  is a schematic block diagram of the first timeout control circuit of  FIG. 1  in accordance with an embodiment of the present invention; 
         FIGS. 6A and 6B  are a timing diagram illustrating a switching operation of the clock switching system of  FIG. 1  when a currently selected clock signal is active in accordance with an embodiment of the present invention; 
         FIGS. 7A and 7B  are a timing diagram illustrating a switching operation of the clock switching system of  FIG. 1  when a currently selected clock signal is inactive in accordance with an embodiment of the present invention; 
         FIG. 8  is a schematic block diagram of another clock switching system that includes third, fourth, and fifth switchover control circuits and a second timeout control circuit in accordance with another embodiment of the present invention; 
         FIG. 9  is a schematic block diagram of the third switchover control circuit of  FIG. 8  in accordance with another embodiment of the present invention; 
         FIG. 10  is a schematic block diagram of the second timeout control circuit of  FIG. 8  in accordance with another embodiment of the present invention; 
         FIGS. 11A and 11B  are a timing diagram illustrating a switching operation of the clock switching system of  FIG. 8  when a currently selected clock signal is active in accordance with another embodiment of the present invention; and 
         FIGS. 12A, 12B, and 12C  are a timing diagram illustrating a switching operation of the clock switching system of  FIG. 8  when a currently selected clock signal is inactive in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present invention, and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention. As used herein, the term multiplexer has been abbreviated as a mux. 
     In an embodiment of the present invention, a clock switching system is provided. The clock switching system comprises a decoder, first and second switchover control circuits, first and second muxes, a timeout control circuit, and a first combinational logic circuit. The decoder receives a select signal and generates first and second select signals. The first switchover control circuit receives a timer reset signal, a first clock signal, a second enable signal, and the first select signal, and generates a first enable signal, a first start timer signal, and a first stop timer signal. The second switchover control circuit receives the timer reset signal, a second clock signal, the second select signal, and the first enable signal, and generates the second enable signal, a second start timer signal, and a second stop timer signal. The first mux receives the first and second start timer signals and outputs a start timer output signal based on the select signal. The second mux receives the first and second stop timer signals and outputs a stop timer output signal based on the select signal. The timeout control circuit receives at least one of the first and second clock signals, the start timer signal, and the stop timer signal. The timeout control circuit performs a counting operation for generating a count value based on the start timer output signal, compares the count value with a predetermined timer value, generates the timer reset signal for resetting at least one of the first and second switchover control circuits when the count value is equal to the predetermined timer value, and terminates the counting operation based on at least one of the stop timer output signal and the timer reset signal. The first combinational logic circuit receives the first and second clock signals and the first and second enable signals and outputs at least one of the first and second clock signals as a clock output signal based on the first and second enable signals. 
     In another embodiment of the present invention, a clock switching system is provided. The clock switching system comprises a decoder, first, second, and third switchover control circuits, first and second muxes, a timeout control circuit, and a first combinational logic circuit. The decoder receives first and second bit signals and generates first, second, and third select signals. The first switchover control circuit receives a timer reset signal, a first clock signal, a second enable signal, and a third enable signal and generates a first enable signal, a first start timer signal, and a first stop timer signal. The second switchover control circuit receives the timer reset signal, a second clock signal, the second select signal, the first enable signal, and the third enable signal and generates the second enable signal, a second start timer signal, and a second stop timer signal. The third switchover control circuit receives the timer reset signal, a third clock signal, the third select signal, the first enable signal, and the second enable signal and generates the third enable signal, a third start timer signal, and a third stop timer signal. The first mux receives the first, second, and third start timer signals and the first and second bit signals, and outputs a start timer output signal based on the first and second bit signals. The second mux receives the first, second, and third stop timer signals and the first and second bit signals, and outputs a stop timer output signal based on the first and second bit signals. The timeout control circuit receives at least one of the first, second, and third clock signals, the start timer output signal, and the stop timer output signal. The timeout control circuit performs a counting operation for generating a count value based on the start timer signal, compares the count value with a predetermined timer value, generates the timer reset signal for resetting at least one of the first, second, and third switchover control circuits when the count value is equal to the predetermined timer value, and terminates the counting operation based on at least one of the stop timer signal and the timer reset signal. The first combinational logic circuit receives the first, second, and third clock signals and the first, second, and third enable signals, and outputs at least one of the first, second, and third clock signals as a clock output signal based on the third, first, and second enable signals. 
     Various embodiments of the present invention provide a clock switching system. The clock switching system receives multiple clock signals including first and second clock signals and switches from the first clock signal to the second clock signal. The clock switching system comprises multiple switchover control circuits, first and second muxes, a timeout control circuit, and a combinational logic circuit. The switchover control circuits generate corresponding enable signals, corresponding start timer signals, and corresponding stop timer signals. The first mux is connected to the switchover control circuits for receiving corresponding start timer signals and outputting a start timer output signal based on a select signal. The second mux is connected to the switchover control circuits for receiving corresponding stop timer signals and outputting a stop timer output signal based on the select signal. The timeout control circuit receives the clock signals, the start timer output signal and the stop timer output signal. The timeout control circuit performs a counting operation for generating a count value based on the start timer output signal, compares the count value with a predetermined timer value, generates a timer reset signal for resetting at least one switchover control circuit when the count value is equal to the predetermined timer value and terminates the counting operation based on at least one of the timer reset signal and the stop timer output signal. The combinational logic circuit receives the clock signals and the enable signals, and outputs the second clock signal. 
     The clock switching system does not require any dedicated circuit for monitoring a current state of a currently selected clock signal, thereby reducing the circuit area require for the clock mux. Further, the clock switching system provides switching from the first clock signal to the second clock signal even when the first clock signal is inactive, i.e., when the first clock signal is absent or malfunctioning. 
     Referring now to  FIG. 1 , a schematic block diagram of a first clock switching system  100  in accordance with an embodiment of the present invention is shown. The first clock switching system  100  includes a first decoder  102 , first and second switchover control circuits  104   a  and  104   b , first and second muxes  106   a  and  106   b , a first timeout control circuit  108 , and a first combinational logic circuit  110 . The first timeout control circuit  108  includes a third mux  112 , a first enable control circuit  114 , a first counter  116 , a first comparator  118 , and a first NOT gate  119 . 
     The first decoder  102  has an input terminal for receiving a select signal (V SEL ). The select signal may be generated by a processor or a controller. The first decoder  102  has first and second output terminals for generating first and second select signals (V SEL1  and V SEL2 ), respectively. In one embodiment, when the select signal is at low (i.e., logic low state), the first decoder  102  generates the first select signal at its first output terminal and when the select signal is high, the first decoder  102  generates the second select signal at its second output terminal. 
     The first switchover control circuit  104   a  is connected to the first output terminal of the first decoder  102  and receives the first select signal. The first switchover control circuit  104   a  further receives a first clock signal (V CLK1 ), a tied high signal (V HIGH1 ), a first timer reset signal (V TIMER   _   RST1 ), and a first enable signal (V EN1 ). The first switchover control circuit  104   a  generates a first start timer signal (V START1 ), a second enable signal (V EN2 ), and a first stop timer signal (V STOP1 ). The first switchover control circuit  104   a  will be explained in detail in conjunction with  FIG. 2  below. 
     The second switchover control circuit  104   b  is connected to the second output terminal of the first decoder  102  and the first switchover control circuit  104   a  for receiving the second select signal and the second enable signal, respectively. The second switchover control circuit  104   b  further receives a second clock signal (V CLK2 ), a second logic high signal (V HIGH2 ), and the first timer reset signal. The second switchover control circuit  104   b  generates a second start timer signal (V START2 ), the first enable signal, and a second stop timer signal (V STOP2 ). In the presently preferred embodiment, the second switchover control circuit  104   b  has the same design as the first switchover control circuit  104   a.    
     It will be understood by those of skill in the art that the first and second clock signals may be generated by oscillator circuits or other clock generator circuits. 
     The first mux  106   a  has first and second input terminals connected to the first and second switchover control circuits  104   a  and  104   b  for receiving the first and second start timer signals, respectively, and a select terminal for receiving the select signal. Based on the value of the select signal, the first mux  106   a  selects and outputs one of the first and second start timer signals as a first start timer output signal (V START   _   OUT1 ) at its output terminal. For example, when the select signal is low, the first mux  106   a  outputs the first start timer signal as the first start timer output signal, and when the select signal is high, the first mux  106   a  outputs the second start timer signal as the first start timer output signal. 
     The second mux  106   b  has first and second input terminals connected to the first and second switchover control circuits  104   a  and  104   b  for receiving the first and second stop timer signals, respectively, and a select terminal for receiving the select signal. Based on the value of the select signal, the second mux  106   b  selects and outputs one of the first and second stop timer signals as a first stop timer output signal (V STOP   _   OUT1 ) at its output terminal. For example, when the select signal is low, the second mux  106   b  outputs the first stop timer signal as the first stop timer output signal, and when the select signal is high, the second mux  106   b  outputs the second stop timer signal as the first stop timer output signal. 
     The third mux  112  has a first input terminal for receiving the first clock signal, a second input terminal for receiving the second clock signal, and a select terminal for receiving the select signal. Based on the value of the select signal, the third mux  112  selects and outputs one of the first and second clock signals as a first intermediate clock signal (V INT   _   CLK1 ) at its output terminal. For example, when the select signal is at low, the third mux  112  outputs the first clock signal as the first intermediate clock signal, and when the select signal is high the third mux  112  outputs the second clock signal as the first intermediate clock signal. 
     The first enable control circuit  114  is connected to the first, second, and third muxes  106   a ,  106   b , and  112  for receiving the first start timer output signal, the first stop timer output signal, and the first intermediate clock signal. The first enable control circuit  114  further receives the first timer reset signal. The first enable control circuit  114  generates a first counter enable signal (V CNT   _   EN1 ) and a first counter reset signal (V CNT   _   RST1 ) based on at least one of the first start timer output signal, the first timer reset signal, and the first stop timer output signal. 
     The first counter  116  is connected to the third mux  112  for receiving the first intermediate clock signal. The first counter  116  also is connected to the first enable control circuit  114  for receiving the first counter enable signal and the first counter reset signal. The first counter  116  performs a counting operation based on the first counter enable signal and generates a first count value (V CNT   _   VAL1 ). The first counter  116  stops counting based on the first counter enable signal and the first counter reset signal. The first counter  116  is reset based on the first counter reset signal. 
     The first comparator  118  is connected to the first counter  116  for receiving the first count value. The first comparator  118  compares the first count value with a first predetermined timer value and generates a first comparison signal (V COMP1 ) when the first count value is equal to the first predetermined timer value. 
     The first NOT gate  119  is connected to the first comparator  118  and receives the first comparison signal, and generates the first timer reset signal at its output terminal. The first timeout control circuit  108  activates the first timer reset signal to reset one of the first and second switchover control circuits  104   a  and  104   b  when the first count value is equal to the first predetermined timer value. 
     In one embodiment, the first predetermined timer value is calculated using expression (1):
 
 V   PRE   _   TIMER1 =((frequency of a clock signal with a highest frequency)/(frequency of a clock signal with a lowest frequency))*( K   1 )+1  (1)
 
where, V PRE   _   TIMER1 =the first predetermined timer value; and K 1 =maximum number of clock cycles of the clock signal with the lowest frequency required for switching from the clock signal with the lowest frequency to the clock signal with the highest frequency=maximum number of clock cycles of the clock signal with the lowest frequency required for switching from the clock signal with the highest frequency to the clock signal with the lowest frequency=1.5.
 
     In one embodiment, the clock signal with the lowest frequency is the second clock signal and the clock signal with the highest frequency is the first clock signal. 
     The first predetermined timer value is rounded to the next integer value when it is not an integer value. For example, if the frequency of the clock signal with the highest frequency is 500 MHz and the frequency of the clock signal with the lowest frequency is 35 MHz, then the V PRE   _   TIMER1 =(((500/35)*(1.5))+1)=22.48, so the first predetermined timer value is rounded to 23. 
     The first timeout control circuit  108  receives the first start timer output signal and the first stop timer output signal. The first timeout control circuit  108  further receives the first and second clock signals. The first timeout control circuit  108  performs the counting operation to generate the first count value based on the first start timer output signal, compares the first count value with the first predetermined timer value, and generates the first timer reset signal to reset one of the first and second switchover control circuits  104   a  and  104   b  when the first count value is equal to the first predetermined timer value. The first timeout control circuit  108  terminates the counting operation based on at least one of the first stop timer output signal and the first comparison signal, i.e., an inverted first timer reset signal. 
     The first combinational logic circuit  110  is connected to the first and second switchover control circuits  104   a  and  104   b  for receiving the second enable signal and the first enable signal, respectively. The first combinational logic circuit  110  further receives the first and second clock signals and outputs at least one of the first and second clock signals as a first clock output signal (V CLK   _   OUT1 ) based on the second and first enable signals. 
     In one embodiment, the first combinational logic circuit  110  includes first and second logic gates  120   a  and  120   b . The first and second logic gates  120   a  and  120   b  are AND gates or their functional equivalents. The first combinational logic circuit  110  further includes a third logic gate  122 , which may be an OR gate or its logical equivalent. The first logic gate  120   a  has a first input terminal for receiving the first clock signal and a second input terminal connected to the first switchover control circuit  104   a  for receiving the second enable signal. The first logic gate  120   a  has an output terminal for generating a first intermediate signal (V INT1 ). The second logic gate  120   b  has a first input terminal for receiving the second clock signal and a second input terminal connected to the second switchover control circuit  104   b  for receiving the first enable signal. The second logic gate  120   b  has an output terminal for generating a second intermediate signal (V INT2 ). The third logic gate  122  has a first input terminal connected to the output terminal of the first logic gate  120   a  for receiving the first intermediate signal and a second input terminal connected to the output terminal of the second logic gate  120   b  for receiving the second intermediate signal. The third logic gate  122  has an output terminal for generating the first clock output signal. 
     Referring now to  FIG. 2 , a schematic block diagram of the first switchover control circuit  104   a  in accordance with an embodiment of the present invention is shown. The first switchover control circuit  104   a  includes a first reset synchronizer circuit  202 , first and second synchronizers  204   a  and  204   b , a first positive edge detector  206 , a first negative edge detector  208 , and a second combinational logic circuit  210 . 
     The first reset synchronizer circuit  202  receives the first clock signal and the tied high signal and is connected to the first output terminal of the first decoder  102  and the output terminal of the first NOT gate  119  for receiving the first select signal and the first timer reset signal, respectively. The first reset synchronizer circuit  202  generates a first reset synchronizer signal (V RST1 ). The first reset synchronizer circuit  202  includes a fourth logic gate  212  and a first reset synchronizer  214 . 
     The fourth logic gate  212  has a first input terminal connected to the first output terminal of the first decoder  102  for receiving the first select signal and a second input terminal connected to the output terminal of the first NOT gate  119  for receiving the first timer reset signal. The fourth logic gate  212  has an output terminal for generating a first intermediate reset signal (V INT   _   RST1 ). In one embodiment, the fourth logic gate  212  is an OR gate or its functional equivalent. 
     The first reset synchronizer  214  receives the first clock signal and the tied high signal. The first reset synchronizer  214  is connected to the output terminal of the fourth logic gate  212  for receiving the first intermediate reset signal and generates the first reset synchronizer signal. The first reset synchronizer  214  will be explained in detail in conjunction with  FIG. 3A . 
     The first synchronizer  204   a  receives the first clock signal and is connected to the first output terminal of the first decoder  102  and the first reset synchronizer  214  for receiving the first select signal and the first reset synchronizer signal, respectively. The first synchronizer  204   a  generates a first synchronizer signal (V SYNC1 ). The first synchronizer  204   a  will be explained in detail in conjunction with  FIG. 3B . 
     The second synchronizer  204   b  receives the first clock signal and is connected to the second switchover control circuit  104   b  and the first reset synchronizer  214  for receiving the first enable signal and the first reset synchronizer signal, respectively. The second synchronizer  204   b  generates a second synchronizer signal (V SYNC2 ). The second synchronizer  204   b  is structurally and functionally similar to the first synchronizer  204   a.    
     The first positive edge detector  206  receives the first clock signal and is connected to the first reset synchronizer  214  and the first synchronizer  204   a  for receiving the first reset synchronizer signal and the first synchronizer signal, respectively. The first positive edge detector  206  generates a first detector output signal (V DET1 ). The first positive edge detector  206  will be explained in detail in conjunction with  FIG. 4A . 
     The first negative edge detector  208  receives the first clock signal and is connected to the first reset synchronizer  214  and the second synchronizer  204   b  for receiving the first reset synchronizer signal and the second synchronizer signal, respectively. The first negative edge detector  208  generates a second detector output signal (V DET2 ). The first negative edge detector  208  will be explained in detail in conjunction with  FIG. 4B . 
     The second combinational logic circuit  210  is connected to the first and second synchronizers  204   a  and  204   b  for receiving the first and second synchronizer signals, respectively, connected to the first positive edge detector  206  and the first negative edge detector  208  for receiving the first and second detector output signals, respectively, and connected to the first output terminal of the first decoder  102  for receiving the first select signal. The second combinational logic circuit  210  generates the second enable signal based on the first and second synchronizer signals, generates the first start timer signal based on the first select signal and the first detector output signal, and generates the first stop timer signal based on the first select signal and the second detector output signal. 
     In one embodiment, the second combinational logic circuit  210  includes a fifth logic gate  216 , which may be a NOT gate. The second combinational logic circuit  210  further includes sixth through eighth logic gates  218   a - 218   c . The sixth through eighth logic gates  218   a - 218   c  are AND gates or functional equivalents. The fifth logic gate  216  has an input terminal connected to the second synchronizer  204   b  for receiving the second synchronizer signal. The fifth logic gate  216  generates an inverted version of the second synchronizer signal (V INV   _   SYNC2 ) (hereinafter referred to as an “inverted second synchronizer signal”) at its output terminal. The sixth logic gate  218   a  has a first input terminal connected to the first synchronizer  204   a  for receiving the first synchronizer signal and a second input terminal connected to the output terminal of the fifth logic gate  216  for receiving the inverted second synchronizer signal. The sixth logic gate  218   a  has an output terminal that provides the second enable signal. The seventh logic gate  218   b  has a first input terminal connected to the first output terminal of the first decoder  102  for receiving the first select signal and a second input terminal connected to the first positive edge detector  206  for receiving the first detector output signal. The seventh logic gate  218   b  has an output terminal for provides the first start timer signal. The eighth logic gate  218   c  has a first input terminal connected to the first output terminal of the first decoder  102  for receiving the first select signal and a second input terminal connected to the first negative edge detector  208  for receiving the second detector output signal. The eighth logic gate  218   c  has an output terminal for providing the first stop timer signal. 
     As noted above, the second switchover control circuit  104   b  preferably has the same design as the first switchover control circuit  104   a  so a detailed description is not necessary for one of skill in the art to understand the invention. 
     Referring now to  FIG. 3A , a schematic block diagram of the first reset synchronizer  214  in accordance with an embodiment of the present invention is shown. The first reset synchronizer  214  includes first and second flip-flops  402   a  and  402   b . The first flip-flop  402   a  has an input terminal for receiving the tied high signal, a clock terminal for receiving an inverted version of the first clock signal, a reset terminal connected to the output terminal of the fourth logic gate  212  for receiving the first intermediate reset signal, and an output terminal for generating a first flip-flop output signal (V FF1 ). The second flip-flop  402   b  has an input terminal connected to the output terminal of the first flip-flop  402   a  for receiving the first flip-flop output signal, a clock terminal for receiving the first clock signal, a reset terminal connected to the output terminal of the fourth logic gate  212  for receiving the first intermediate reset signal, and an output terminal for generating the first reset synchronizer signal. It will be understood by those of skill in the art that the first reset synchronizer  214  can be implemented in several ways and will lie under the scope of the invention. 
     Referring now to  FIG. 3B , a schematic block diagram of the first synchronizer  204   a  in accordance with an embodiment of the present invention is shown. The first synchronizer  204   a  includes third and fourth flip-flops  402   c  and  402   d . The third flip-flop  402   c  has an input terminal connected to the first output terminal of the first decoder  102  for receiving the first select signal, a clock terminal for receiving the first clock signal, a reset terminal connected to the output terminal of the second flip-flop  402   b  for receiving the first reset synchronizer signal, and an output terminal for generating a second flip-flop output signal (V FF2 ). The fourth flip-flop  402   d  has an input terminal connected to the output terminal of the third flip-flop  402   c  for receiving the second flip-flop output signal, a clock terminal for receiving an inverted version of the first clock signal, a reset terminal connected to the output terminal of the second flip-flop  402   b  for receiving the first reset synchronizer signal, and an output terminal for generating the first synchronizer signal. It will be understood by those of skill in the art that the first synchronizer  204   a  can be implemented in several ways and will lie under the scope of the invention. 
     Referring now to  FIG. 4A , a schematic block diagram of the first positive edge detector  206  in accordance with an embodiment of the present invention is shown. The first positive edge detector  206  includes a fifth flip-flop  502   a , a fourteenth logic gate  504   a , and a fifteenth logic gate  506   a . The fifth flip-flop  502   a  has an input terminal connected to the first synchronizer  204   a  for receiving the first synchronizer signal, a clock terminal for receiving the first clock signal, a reset terminal connected to the output terminal of the second flip-flop  402   b  for receiving the first reset synchronizer signal, and an output terminal for generating a third flip-flop output signal (V FF3 ). The fourteenth logic gate  504   a  has an input terminal connected to the output terminal of the fifth flip-flop  502   a  for receiving the third flip-flop output signal. The fourteenth logic gate  504   a  generates an inverted version of the third flip-flop output signal (V INV   _   FF3 ) (hereinafter referred to as an “inverted third flip-flop output signal”) at its output terminal. In one embodiment, the fourteenth logic gate  504   a  is a NOT gate. The fifteenth logic gate  506   a  has a first input terminal connected to the output terminal of the fourth flip-flop  402   d  for receiving the first synchronizer signal and a second input terminal connected to the output terminal of the fourteenth logic gate  504   a  for receiving the inverted third flip-flop output signal. The fifteenth logic gate  506   a  has an output terminal for generating the first detector output signal. In one embodiment, the fifteenth logic gate  506   a  is an AND gate or its functional equivalent. It will be understood by those of skill in the art that the first positive edge detector  206  can be implemented in several ways and will lie under the scope of the invention. 
     Referring now to  FIG. 4B , a schematic block diagram of the first negative edge detector  208  in accordance with an embodiment of the present invention is shown. The first negative edge detector  208  includes a sixth flip-flop  502   b , a sixteenth logic gate  504   b , and a seventeenth logic gate  506   b . The sixth flip-flop  502   b  has an input terminal connected to the second synchronizer  204   b  for receiving the second synchronizer signal, a clock terminal for receiving the first clock signal, a reset terminal connected to the output terminal of the second flip-flop  402   b  for receiving the first reset synchronizer signal, and an output terminal for generating a fourth flip-flop output signal (V FF4 ). The seventeenth logic gate  506   b  has a first input terminal connected to the output terminal of the sixteenth logic gate  504   b  for receiving the inverted second synchronizer signal and a second input terminal connected to the output terminal of the sixth flip-flop  502   b  for receiving the fourth flip-flop output signal. The seventeenth logic gate  506   b  has an output terminal for generating the second detector output signal. In one embodiment, the seventeenth logic gate  506   b  is an AND gate. It will be understood by those of skill in the art that the first negative edge detector  208  can be implemented in several ways and will lie under the scope of the invention. 
     Referring now to  FIG. 5 , a schematic block diagram of the first timeout control circuit  108  in accordance with an embodiment of the present invention is shown. The first timeout control circuit  108  includes the third mux  112 , the first enable control circuit  114 , the first counter  116 , the first comparator  118 , and the first NOT gate  119 . The first enable control circuit  114  includes a seventh flip-flop  602 , fourth and fifth muxes  604   a  and  604   b , and an eighteenth logic gate  606 . In one embodiment, the eighteenth logic gate  606  is an AND gate or its functional equivalent. The first enable control circuit  114  further includes nineteenth and twentieth logic gates  608   a  and  608   b . In one embodiment, the nineteenth and twentieth logic gates  608   a  and  608   b  are OR gates or their functional equivalents. 
     The fourth mux  604   a  has a first input terminal for receiving a first mux output signal (V MUX1 ), a second input terminal for receiving a third logic high signal (V HIGH3 ), and a select terminal connected to the output terminal of the first mux  106   a  for receiving the first start timer output signal. Based on a value of the first start timer output signal, the fourth mux  604   a  outputs one of the first mux output signal and the third logic high signal as a second mux output signal (V MUX2 ) at its output terminal. For example, when the first start timer output signal is low, the fourth mux  604   a  outputs the first mux output signal as the second mux output signal, and when the first start timer output signal is high, the fourth mux  604   a  outputs the third logic high signal as the second mux output signal. 
     The seventh flip-flop  602  has an input terminal connected to the output terminal of the fourth mux  604   a  for receiving the second mux output signal, a clock terminal connected to the output terminal of the third mux  112  for receiving the first intermediate clock signal, and an output terminal for generating the first counter enable signal. 
     The fifth mux  604   b  has a first input terminal connected to the output terminal of the seventh flip-flop  602  for receiving the first counter enable signal, a second input terminal for receiving a first logic low signal (V LOW1 ), and a select terminal for receiving a third intermediate signal (V INT3 ). Based on the third intermediate signal, the fifth mux  604   b  selects and outputs one of the first counter enable signal and the first logic low signal as the first mux output signal at its output terminal. For example, when the third intermediate signal is low, the fifth mux  604   b  outputs the first counter enable signal as the first mux output signal, and when the third intermediate signal is high, the fifth mux  604   b  outputs the first logic low signal as the first mux output signal. 
     The eighteenth logic gate  606  has a first input terminal for receiving the third intermediate signal and a second input terminal connected to the output terminal of the seventh flip-flop  602  for receiving the first counter enable signal. The eighteenth logic gate  606  has an output terminal for generating a fourth intermediate signal (V INT4 ). 
     The nineteenth logic gate  608   a  has a first input terminal connected to the output terminal of the second mux  106   b  for receiving the first stop timer output signal and a second input terminal connected to the first comparator  118  for receiving the first comparison signal. The nineteenth logic gate  608   a  has an output terminal for generating the third intermediate signal. 
     The twentieth logic gate  608   b  has a first input terminal connected to the output terminal of the eighteenth logic gate  606  for receiving the fourth intermediate signal and a second input terminal connected to the output terminal of the first mux  106   a  for receiving the first start timer output signal. The twentieth logic gate  608   b  has an output terminal for generating the first counter reset signal. 
     Referring now to  FIGS. 6A and 6B , a timing diagram illustrating a switching operation of the first clock switching system  100  when a currently selected clock signal is active in accordance with an embodiment of the present invention is shown. In an example, a frequency of the first clock signal is 40 megahertz (MHz), a frequency of the second clock signal is 20 MHz, and the first predetermined timer value is 4. 
     From time T 0 -T 2 , the select signal is high and hence, the second select signal is high and the first select signal is low. The first enable signal is high and the second enable signal is low. Thus, the third logic gate  122  outputs the second clock signal as the first clock output signal since the currently selected clock signal is the second clock signal. 
     From time T 2 -T 4 , the select signal transitions from high to low. The first decoder  102  generates a high first select signal and low second select signal. Thus, the first synchronizer  204   a  receives the high first select signal and the third synchronizer  304   a  receives the low second select signal. 
     From time T 4 -T 5 , the first synchronizer  204   a  generates a high first synchronizer signal. The first positive edge detector  206  generates a high first detector output signal. The seventh logic gate  218   b  receives the high first select signal and the high first detector output signal. Thus, the seventh logic gate  218   b  generates a high first start timer signal. Since the first mux  106   a  receives a low select signal, the first mux  106   a  outputs the first start timer output signal, which is high. 
     From time T 5 -T 7 , the first positive edge detector  206  generates the first detector output signal at logic low state. The seventh logic gate  218   b  generates the first start timer signal at logic low state. Thus, the first mux  106   a  outputs the first start timer output signal at logic low state. The first enable control circuit  114  generates the first counter enable signal at logic high state. 
     From time period T 7 -T 10 , the first counter  116  receives the first counter enable signal at logic high state and performs the counting operation. The third synchronizer  304   a  generates the third synchronizer signal at logic low state. The eleventh logic gate  318   a  receives the third synchronizer signal at logic low state and generates the first enable signal at logic low state. Since the first count value is less than the first predetermined timer value, the first comparator  118  generates the first comparison signal at logic low state. Thus, the first NOT gate  119  generates the first timer reset signal at logic high state. Since the first enable signal is at logic low state, the third logic gate  122  does not output the second clock signal as the first clock output signal. 
     From time T 10 -T 11 , the second synchronizer  204   b  generates the second synchronizer signal at logic low state. The fifth logic gate  216  receives the second synchronizer signal at logic low state and generates the inverted second synchronizer signal at logic high state. The sixth logic gate  218   a  receives a high first synchronizer signal and a high inverted second synchronizer signal, so generates a high second enable signal. The first negative edge detector  208  generates a high second detector output signal. The eighth logic gate  218   c  receives the first select signal at logic high state and the high second detector output signal, so generates a high first stop timer signal. Since the select signal is low, the second mux  106   b  outputs the first stop timer output signal at logic high state. The first enable control circuit  114  generates the first counter reset signal at logic high state. The third logic gate  122  outputs the first clock signal as the first clock output signal. 
     From time T 11 -T 19 , the first negative edge detector  208  generates the second detector output signal at logic low state. Thus, the eighth logic gate  218   c  receives the second detector output signal at logic low state and generates the first stop timer signal at logic low state. The second mux  106   b  outputs the first stop timer output signal at logic low state. The first enable control circuit  114  receives the first stop timer output signal at logic low state and generates the first counter enable signal at logic low state. The first enable control circuit  114  generates the first counter reset signal at logic low state. The first counter  116  terminates the counting operation and resets. Thus, the first comparator  118  generates the first comparison signal at logic low state. The first NOT gate  119  generates the first timer reset signal at logic high state. Since the second enable signal is high, the third logic gate  122  continues to output the first clock output signal. 
     Since the first enable signal transitions from high to low at time T 7  and the second enable signal transitions from low to high at time T 10 , the first and second enable signals are non-overlapping. Hence, the third logic gate  122  does not output either of the second and first clock signals as the first clock output signal during time T 7  to T 10 , so a glitch-free switching between the second and first clock signals is provided. Further, as the second clock signal is active during the switching operation, the first timeout control circuit  108  does not enable the first timer reset signal during the switching operation and hence, generates the first timer reset signal at logic high state. 
     Referring now to  FIGS. 7A and 7B , a timing diagram illustrating a switching operation of the first clock switching system  100  when a currently selected clock signal is inactive in accordance with an embodiment of the present invention is shown. 
     From time T 0 -T 3 , the select signal is high, hence the second select signal is high and the first select signal is low. The first enable signal is high and the second enable signal is low. The third logic gate  122  outputs the second clock signal as the first clock output signal. Thus, the currently selected clock signal is the second clock signal. 
     After time T 3 , the second clock signal is inactive. From time T 3 -T 6 , the select signal transitions from high to low. The first decoder  102  generates the first select signal at logic high state and the second select signal at logic low state. Thus, the first synchronizer  204   a  receives the first select signal at logic high state and the third synchronizer  304   a  receives the second select signal at logic low state. 
     From time T 6 -T 7 , the first synchronizer  204   a  generates the first synchronizer signal at logic high state. The first positive edge detector  206  generates the first detector output signal at logic high state. The seventh logic gate  218   b  receives the first select signal at logic high state and the first detector output signal at logic high state and generates the first start timer signal at logic high state. Thus, the first mux  106   a  outputs the first start timer output signal at logic high state. 
     From time T 7 -T 9 , the first enable control circuit  114  generates the first counter enable signal at logic high state. 
     From time T 9 -T 15 , the first counter  116  receives the first counter enable signal at logic high state and performs the counting operation. The first counter  116  generates the first count value. Since the first count value is less than the first predetermined timer value, the first comparator  118  generates the first comparison signal at logic low state. 
     From time T 15 -T 17 , the first count value is 4. Since the first count value is equal to the first predetermined timer value, the first comparator  118  generates the first comparison signal at logic high state. Thus, the first NOT gate  119  generates the first timer reset signal at logic low state. The first enable control circuit  114  generates the first counter reset signal at logic high state. 
     The ninth logic gate  312  receives the second select signal at logic low state and the first timer reset signal at logic low state, so generates the second intermediate reset signal at logic low state. The second reset synchronizer  314  receives the second intermediate reset signal at logic low state and generates the second reset synchronizer signal at logic low state, which resets the third and fourth synchronizers  304   a  and  304   b  and the second positive and negative edge detectors  306  and  308 . Thus, the third synchronizer  304   a  generates the third synchronizer signal at logic low state. The eleventh logic gate  318   a  receives the third synchronizer signal at logic low state and generates the first enable signal at logic low state. Thus, the second switchover control circuit  104   b  is reset. 
     The fourth logic gate  212  receives the first select signal at logic high state and the first timer reset signal at logic low state, so it generates the first intermediate reset signal at logic high state. The first reset synchronizer  214  receives the first intermediate reset signal at logic high state and hence generates the first reset synchronizer signal at logic high state. Thus, the first switchover control circuit  104   a  does not reset. 
     From time T 17 -T 18 , the first enable control circuit  114  generates the first counter enable signal at logic low state. The first enable control circuit  114  generates the first counter reset signal at logic low state. The first counter  116  stops the counting operation and is reset. 
     From time T 18 -T 19 , the second synchronizer  204   b  generates the second synchronizer signal at logic low state. The fifth logic gate  216  receives the second synchronizer signal at logic low state and generates the inverted second synchronizer signal at logic high state. The sixth logic gate  218   a  receives the first synchronizer signal at logic high state and the inverted second synchronizer signal at logic high state and so it generates the second enable signal at logic high state. The first negative edge detector  208  generates the second detector output signal at logic high state and the eighth logic gate  218   c  generates the first stop timer signal at logic high state. Thus, the second mux  106   b  outputs the first stop timer output signal at logic high state. The third logic gate  122  generates the first clock signal as the first clock output signal since the second enable signal is at logic high state. 
     From time T 19 -T 31 , the first negative edge detector  208  generates the second detector output signal at logic low state and the eighth logic gate  218   c  generates the first stop timer signal at logic low state. Thus, the second mux  106   b  outputs the first stop timer output signal at logic low state. The third logic gate  122  continues to output the first clock signal as the first clock output signal. 
     Since the first enable signal transitions from high to low at time T 15  and the second enable signal transitions from low to high at time T 18 , the first and second enable signals are non-overlapping. Hence, the third logic gate  122  does not output either of the second and first clock signals as the first clock output signal during time period T 15  to T 18 , so glitch-free switching between the second and first clock signals is provided. 
     The first clock switching system  100  switches from the second clock signal to the first clock signal even when the second clock signal is inactive. Further, as the second clock signal is inactive during the switching operation, the first timeout control circuit  108  enables the first timer reset signal during the switching operation and hence generates the first timer reset signal at logic low state for resetting the second switchover control circuit  104   b.    
     It will be apparent to those of skill in the art that when the first clock switching system  100  provides switching from a first clock signal to a second clock signal and the first clock signal is inactive, all switchover control circuits except the switchover control circuit performing functions using the second clock signal are reset. 
     Thus, the first clock switching system  100  can be used for providing the second clock output signal at various clock frequencies, i.e., the first clock switching system  100  can provide switching between multiple clock signals. 
     Referring to  FIG. 8 , a schematic block diagram of a second clock switching system  900  in accordance with another embodiment of the present invention is shown. The second clock switching system  900  includes a second decoder  902 , third through fifth switchover control circuits  904   a - 904   c , sixth and seventh muxes  906   a  and  906   b , a second timeout control circuit  908 , and a fourth combinational logic circuit  910 . The second timeout control circuit  908  includes an eighth mux  912 , a second enable control circuit  914 , a second counter  916 , a second comparator  918 , and a second NOT gate  919 . 
     The second decoder  902  has first and second input terminals for receiving first and second bit signals (V BIT1  and V BIT2 , respectively. The first and second bit signals may be generated by a processor or controller circuit. The first bit signal represents a most significant bit (MSB) signal and the second bit signal represents a least significant bit (LSB) signal. The second decoder  902  has first, second, and third output terminals for generating third, fourth, and fifth select signals (V SEL3 , V SEL4 , and V SEL5 ), respectively. Based on the value of the first and second bit signals, the second decoder  902  generates the third select signal, the fourth select signal, and the fifth select signal. When the first and second bit signals are low (i.e., “00”), the second decoder  902  generates the third select signal at its first output terminal. When the first bit signal is low and the second bit signal is high (i.e., “01”), the second decoder  902  generates the fourth select signal at its second output terminal. When the first bit signal is high and the second bit signal is low (i.e., “10”), the second decoder  902  generates the fifth select signal at its third output terminal. 
     The third switchover control circuit  904   a  is connected to the first output terminal of the second decoder  902  for receiving the third select signal. The third switchover control circuit  904   a  further receives a third clock signal (V CLK3 ), a fourth logic high signal (V HIGH4 ), a second timer reset signal (V TIMER   _   RST2 ), and third and fourth enable signals (V EN3  and V EN4 ). The third switchover control circuit  904   a  generates a third start timer signal (V START3 ), a fifth enable signal (V EN5 ), and a third stop timer signal (V STOP3 ). The third switchover control circuit  904   a  is described in detail in conjunction with  FIG. 9 . 
     The fourth switchover control circuit  904   b  is connected to the second output terminal of the second decoder  902  and the third switchover control circuit  904   a  for receiving the fourth select signal and the fifth enable signal, respectively. The fourth switchover control circuit  904   b  further receives a fourth clock signal (V CLK4 ), the fourth enable signal, a fifth logic high signal (V HIGH5 ), and the second timer reset signal. The fourth switchover control circuit  904   b  generates a fourth start timer signal (V START4 ), the third enable signal, and a fourth stop timer signal (V STOP4 ). The fourth switchover control circuit  904   b  preferably has the same circuit design as the third switchover control circuit  904   a  shown in  FIG. 9 . 
     The fifth switchover control circuit  904   c  receives a fifth clock signal (V CLK5 ), a sixth logic high signal (V HIGH6 ), and the second timer reset signal. The fifth switchover control circuit  904   c  is connected to the third output terminal of the second decoder  902  for receiving the fifth select signal. The fifth switchover control circuit  904   c  is further connected to the third and fourth switchover control circuits  904   a  and  904   b  for receiving the fifth enable signal and the third enable signal, respectively. The fifth switchover control circuit  904   c  generates a fifth start timer signal (V START5 ) r the fourth enable signal, and a fifth stop timer signal (V STOP5 ). The fifth switchover control circuit  904   c  preferably has the same circuit design as the third switchover control circuit  904   a  shown in  FIG. 9 . 
     It will be understood by those of skill in the art that the third, fourth, and fifth clock signals may be generated by oscillator circuits or other clock generator circuits. 
     The sixth mux  906   a  has first, second, and third input terminals connected to the third, fourth, and fifth switchover control circuits  904   a ,  904   b , and  904   c  for receiving the third, fourth, and fifth start timer signals, respectively, and first and second select terminals for receiving the first and second bit signals, respectively. Based on the first and second bit signals, the sixth mux  906   a  selects and outputs at least one of the third, fourth, and fifth start timer signals as a second start timer output signal (V START   _   OUT2 ) at an output terminal thereof. When the first and second bit signals are both low, the sixth mux  906   a  selects and outputs the third start timer signal as the second start timer output signal. When the first bit signal is low and the second bit signal is high, the sixth mux  906   a  selects and outputs the fourth start timer signal as the second start timer output signal. When the first bit signal is high and the second bit signal is low, the sixth mux  906   a  selects and outputs the fifth start timer signal as the second start timer output signal. 
     The seventh mux  906   b  has first, second, and third input terminals connected to the third, fourth, and fifth switchover control circuits  904   a ,  904   b , and  904   c  for receiving the third, fourth, and fifth stop timer signals, respectively, and first and second select terminals for receiving the first and second bit signals, respectively. Based on the first and second bit signals, the seventh mux  906   b  selects and outputs one of the third, fourth, and fifth stop timer signals as a second stop timer output signal (V STOP   _   OUT2 ) at its output terminal. When the first and second bit signals are both low, the seventh mux  906   b  selects and outputs the third stop timer signal as the second stop timer output signal. When the first bit signal is low and the second bit signal is high, the seventh mux  906   b  selects and outputs the fourth stop timer signal as the second stop timer output signal. When the first bit signal is at high and the second bit low state, the seventh mux  906   b  selects and outputs the fifth stop timer signal as the second stop timer output signal. 
     The eighth mux  912  has a first input terminal for receiving the third clock signal, a second input terminal for receiving the fourth clock signal, a third input terminal for receiving the fifth clock signal, and first and second select terminals for receiving the first and second bit signals, respectively. Based on the first and second bit signals, the eighth mux  912  selects and outputs one of the third, fourth, and fifth clock signals as a second intermediate clock signal (V INT   _   CLK2 ) at its output terminal. When the first and second bit signals are both low, the eighth mux  912  selects and outputs the third clock signal as the second intermediate clock signal. When the first bit signal is low and the second bit signal is high, the eighth mux  912  selects and outputs the fourth clock signal as the second intermediate clock signal. When the first bit signal is high and the second bit signal is low, the eighth mux  912  selects and outputs the fifth clock signal as the second intermediate clock signal. 
     The second enable control circuit  914  is connected to the sixth, seventh, and eighth muxes  906   a ,  906   b , and  912  for receiving the second start timer output signal, the second stop timer output signal, and the second intermediate clock signal, respectively. The second enable control circuit  914  further receives the second timer reset signal. The second enable control circuit  914  generates a second counter enable signal (V CNT   _   EN2 ) and a second counter reset signal (V CNT   _   RST2 ) based on at least one of the second start timer output signal, the second timer reset signal, and the second stop timer output signal. 
     The second counter  916  is connected to the output terminal of the eighth mux  912  for receiving the second intermediate clock signal. The second counter  916  is connected to the second enable control circuit  914  for receiving the second counter enable signal and the second counter reset signal. The second counter  916  performs a counting operation based on the second counter enable signal for generating a second count value (V CNT   _   VAL2 ) and terminates the counting operation based on at least one of the second counter enable signal and the second counter reset signal. The second counter  916  is reset based on the second counter reset signal. 
     The second comparator  918  is connected to the second counter  916  for receiving the second count value. The second comparator  918  compares the second count value with a second predetermined timer value and generates a second comparison signal (V COMP2 ) at logic high state when the second count value is equal to the second predetermined timer value. 
     The second NOT gate  919  is connected to the second comparator  918  and receives the second comparison signal and generates the second timer reset signal. The second timeout control circuit  908  enables the second timer reset signal for resetting at least one of the third, fourth, and fifth switchover control circuits  904   a ,  904   b , and  904   c  when the second count value is equal to the second predetermined timer value. In one embodiment, the second comparator  918  generates a high active second comparison signal that enables the second timer reset signal. 
     In one embodiment, the second predetermined timer value is calculated using expression (2) given below:
 
 V   PRE   _   TIMER2 =(((frequency of a clock signal with a highest frequency)/(frequency of a clock signal with a lowest frequency))*( K   2 ))+1  (2)
 
where, V PRE   _   TIMER2 =the second predetermined timer value; and K 2 =maximum number of clock cycles of the clock signal with the lowest frequency required for switching from the clock signal with the lowest frequency to the clock signal with the highest frequency=maximum number of clock cycles of the clock signal with the lowest frequency required for switching from the clock signal with the highest frequency to the clock signal with the lowest frequency=1.5.
 
     In this embodiment, the clock signal with the lowest frequency is the fifth clock signal and the clock signal with the highest frequency is the third clock signal. 
     The second predetermined timer value is rounded to the next integer value when the second predetermined timer value is not an integer value. For example, if the frequency of the clock signal with the highest frequency is 600 MHz and the frequency of the clock signal with the lowest frequency is 35 MHz, then the V PRE   _   TIMER2 =(((600/35)*(1.5))+1)=26.71. Thus, the second predetermined timer value is rounded to 27. 
     The second timeout control circuit  908  receives the second start timer output signal and the second stop timer output signal. The second timeout control circuit  908  further receives the third, fourth, and fifth clock signals. The second timeout control circuit  908  performs the counting operation for generating the second count value based on the second start timer output signal, compares the second count value with the second predetermined timer value, and generates the second timer reset signal for resetting at least one of the third, fourth, and fifth switchover control circuits  904   a ,  904   b , and  904   c  when the second count value is equal to the second predetermined timer value. The second timeout control circuit  908  terminates the counting operation based on at least one of the second stop timer output signal and the second comparison signal, i.e., an inverted second timer reset signal. 
     The fourth combinational logic circuit  910  is connected to the third, fourth, and fifth switchover control circuits  904   a ,  904   b , and  904   c  for receiving the fifth enable signal, the third enable signal, and the fourth enable signal, respectively. The fourth combinational logic circuit  910  further receives the third, fourth, and fifth clock signals and outputs at least one of the third, fourth, and fifth clock signals as a second clock output signal (V CLK   _   OUT2 ) based on the fifth enable signal, the third enable signal, and the fourth enable signal. 
     In one embodiment, the fourth combinational logic circuit  910  includes twenty-first through twenty-third logic gates  920   a - 920   c . The twenty-first through twenty-third logic gates  920   a - 920   c  are AND gates. The fourth combinational logic circuit  910  further includes a twenty-fourth logic gate  922 . The twenty-fourth logic gate  922  is an OR gate. The twenty-first logic gate  920   a  has a first input terminal for receiving the third clock signal and a second input terminal connected to the third switchover control circuit  904   a  for receiving the fifth enable signal. The twenty-first logic gate  920   a  has an output terminal for generating a fifth intermediate signal (V INT5 ). The twenty-second logic gate  920   b  has a first input terminal for receiving the fourth clock signal and a second input terminal connected to the fourth switchover control circuit  904   b  for receiving the third enable signal. The twenty-second logic gate  920   b  has an output terminal for generating a sixth intermediate signal (V INT6 ). The twenty-third logic gate  920   c  has a first input terminal for receiving the fifth clock signal and a second input terminal connected to the fifth switchover control circuit  904   c  for receiving the fourth enable signal. The twenty-third logic gate  920   c  generates a seventh intermediate signal (V INT7 ) at its output terminal. 
     The twenty-fourth logic gate  922 , which in a preferred embodiment is an OR gate or its functional equivalent, has a first input terminal connected to the output terminal of the twenty-first logic gate  920   a  for receiving the fifth intermediate signal, a second input terminal connected to the output terminal of the twenty-second logic gate  920   b  for receiving the sixth intermediate signal, and a third input terminal connected to the output terminal of the twenty-third logic gate  920   c  for receiving the seventh intermediate signal. The twenty-fourth logic gate  922  generates the second clock output signal at its output terminal. 
     Referring now to  FIG. 9 , a schematic block diagram of the third switchover control circuit  904   a  in accordance with an embodiment of the present invention is shown. The third switchover control circuit  904   a  includes a twenty-fifth logic gate  1002 , a third reset synchronizer circuit  1004 , fifth and sixth synchronizers  1006   a  and  1006   b , a third positive edge detector  1008 , a third negative edge detector  1010 , and a fifth combinational logic circuit  1012 . 
     The twenty-fifth logic gate  1002  has a first input terminal connected to the fourth switchover control circuit  904   b  for receiving the third enable signal and a second input terminal connected to the fifth switchover control circuit  904   c  for receiving the fourth enable signal. The twenty-fifth logic gate  1002  has an output terminal for generating a first intermediate enable signal (V EN   _   INT1 ). In one embodiment, the twenty-fifth logic gate  1002  is an OR gate or its functional equivalent. 
     The third reset synchronizer circuit  1004  receives the third clock signal and the fourth logic high signal and is connected to the first output terminal of the second decoder  902  and the output terminal of the second NOT gate  919  for receiving the third select signal and the second timer reset signal, respectively. The third reset synchronizer circuit  1004  generates a third reset synchronizer signal (V RST3 ). The third reset synchronizer circuit  1004  includes a twenty-sixth logic gate  1014  and a third reset synchronizer  1016 . 
     The twenty-sixth logic gate  1014  has a first input terminal connected to the first output terminal of the second decoder  902  for receiving the third select signal and a second input terminal connected to the output terminal of the second NOT gate  919  for receiving the second timer reset signal. The twenty-sixth logic gate  1014  has an output terminal for generating a third intermediate reset signal (V INT   _   RST3 ). In one embodiment, the twenty-sixth logic gate  1014  is an OR gate or its functional equivalent. 
     The third reset synchronizer  1016  receives the third clock signal and the fourth logic high signal and is connected to the output terminal of the twenty-sixth logic gate  1014  for receiving the third intermediate reset signal. The third reset synchronizer  1016  generates the third reset synchronizer signal. The third reset synchronizer  1016  is structurally and functionally similar to the first reset synchronizer  214  of  FIG. 3A . 
     The fifth synchronizer  1006   a  receives the third clock signal and is connected to the first output terminal of the second decoder  902  and the third reset synchronizer  1016  for receiving the third select signal and the third reset synchronizer signal, respectively. The fifth synchronizer  1006   a  generates a fifth synchronizer signal (V SYNC5 ). The fifth synchronizer  1006   a  is structurally and functionally similar to the first synchronizer  204   a  of  FIG. 3B . 
     The sixth synchronizer  1006   b  receives the third clock signal and is connected to the output terminal of the twenty-fifth logic gate  1002  and the third reset synchronizer  1016  for receiving the first intermediate enable signal and the third reset synchronizer signal, respectively. The sixth synchronizer  1006   b  generates a sixth synchronizer signal (V SYNC6 ). The sixth synchronizer  1006   b  is structurally and functionally similar to the first synchronizer  204   a  of  FIG. 3B . 
     The third positive edge detector  1008  receives the third clock signal and is connected to the third reset synchronizer  1016  and the fifth synchronizer  1006   a  for receiving the third reset synchronizer signal and the fifth synchronizer signal, respectively. The third positive edge detector  1008  generates a fifth detector output signal (V DET5 ). The third positive edge detector  1008  is structurally and functionally similar to the first positive edge detector  206  of  FIG. 4A . 
     The third negative edge detector  1010  receives the third clock signal and is connected to the third reset synchronizer  1016  and the sixth synchronizer  1006   b  for receiving the third reset synchronizer signal and the sixth synchronizer signal, respectively. The third negative edge detector  1010  generates a sixth detector output signal (V DET6 ). The third negative edge detector  1010  is structurally and functionally similar to the first negative edge detector  208  of  FIG. 4B . 
     The fifth combinational logic circuit  1012  is connected to the fifth and sixth synchronizers  1006   a  and  1006   b  for receiving the fifth and sixth synchronizer signals, respectively, connected to the third positive edge detector  1008  and the third negative edge detector  1010  for receiving the fifth and sixth detector output signals, respectively, and connected to the first output terminal of the second decoder  902  for receiving the third select signal. The fifth combinational logic circuit  1012  generates the fifth enable signal based on the fifth and sixth synchronizer signals, generates the third start timer signal based on the third select signal and the fifth detector output signal, and generates the third stop timer signal based on the third select signal and the sixth detector output signal. 
     In one embodiment, the fifth combinational logic circuit  1012  includes a twenty-seventh logic gate  1018 . The twenty-seventh logic gate  1018  is a NOT gate. The fifth combinational logic circuit  1012  further includes twenty-eighth through thirtieth logic gates  1020   a - 1020   c . The twenty-eighth through thirtieth logic gates  1020   a - 1020   c  are AND gates. The twenty-seventh logic gate  1018  has an input terminal connected to the sixth synchronizer  1006   b  for receiving the sixth synchronizer signal and an output terminal for generating an inverted version of the sixth synchronizer signal (V INV   _   SYNC6 ) (hereinafter referred to as an “inverted sixth synchronizer signal”). The twenty-eighth logic gate  1020   a  has a first input terminal connected to the fifth synchronizer  1006   a  for receiving the fifth synchronizer signal and a second input terminal connected to the output terminal of the twenty-seventh logic gate  1018  for receiving the inverted sixth synchronizer signal. The twenty-eighth logic gate  1020   a  has an output terminal for generating the fifth enable signal. The twenty-ninth logic gate  1020   b  has a first input terminal connected to the first output terminal of the second decoder  902  for receiving the third select signal and a second input terminal connected to the third positive edge detector  1008  for receiving the fifth detector output signal. The twenty-ninth logic gate  1020   b  has an output terminal for generating the third start timer signal. The thirtieth logic gate  1020   c  has a first input terminal connected to the first output terminal of the second decoder  902  for receiving the third select signal and a second input terminal connected to the third negative edge detector  1010  for receiving the sixth detector output signal. The thirtieth logic gate  1020   c  has an output terminal for generating the third stop timer signal. 
     As previously discussed, the fourth and fifth switchover control circuits  904   b  and  904   c  preferably comprise the same design as the third switchover control circuit  904   a  shown in  FIG. 9 . 
     Referring now to  FIG. 10 , a schematic block diagram of the second timeout control circuit  908  in accordance with an embodiment of the present invention is shown. The second timeout control circuit  908  includes the eighth mux  912 , the second enable control circuit  914 , the second counter  916 , the second comparator  918 , and the second NOT gate  919 . The second enable control circuit  914  includes an eighth flip-flop  1302 , ninth and tenth muxes  1304   a  and  1304   b , and a forty-third logic gate  1306 . In one embodiment, the forty-third logic gate  1306  is an AND gate or its functional equivalent. The second enable control circuit  914  further includes forty-fourth and forty-fifth logic gates  1308   a  and  1308   b , which in the embodiment shown comprise OR gates. 
     The ninth mux  1304   a  has a first input terminal for receiving a third mux output signal (V MUX3 ), a second input terminal for receiving a seventh logic high signal (V HIGH7 ), and a select terminal connected to the output terminal of the sixth mux  906   a  for receiving the second start timer output signal. Based on the second start timer output signal, the ninth mux  1304   a  selects and outputs one of the third mux output signal and the seventh logic high signal as a fourth mux output signal (V MUX4 ) at its output terminal. When the second start timer output signal is low, the ninth mux  1304   a  selects and outputs the third mux output signal as the fourth mux output signal, and when the second start timer output signal is high, the ninth mux  1304   a  selects and outputs the seventh logic high signal as the fourth mux output signal. 
     The eighth flip-flop  1302  has an input terminal connected to the output terminal of the ninth mux  1304   a  for receiving the fourth mux output signal and a clock terminal connected to the output terminal of the eighth mux  912  for receiving the second intermediate clock signal. The eighth flip-flop  1302  has an output terminal for providing the second counter enable signal. 
     The tenth mux  1304   b  has a first input terminal connected to the output terminal of the eighth flip-flop  1302  for receiving the second counter enable signal, a second input terminal for receiving a tied low signal (V LOW2 ), and a select terminal for receiving an eighth intermediate signal (V INT8 ). The tenth mux  1304   b  has an output terminal for outputting the third mux output signal. Based on the eighth intermediate signal, the tenth mux  1304   b  selects and outputs one of the second counter enable signal and the tied low signal as the third mux output signal at its output terminal. When the eighth intermediate signal is low, the tenth mux  1304   b  selects and outputs the second counter enable signal as the third mux output signal, and when the eighth intermediate signal is high, the tenth mux  1304   b  selects and outputs the tied low signal as the third mux output signal. 
     The forty-third logic gate  1306  has a first input terminal for receiving the eighth intermediate signal and a second input terminal connected to the output terminal of the eighth flip-flop  1302  for receiving the second counter enable signal. The forty-third logic gate  1306  has an output terminal for generating a ninth intermediate signal (V INT9 ). 
     The forty-fourth logic gate  1308   a  has a first input terminal connected to the output terminal of the seventh mux  906   b  for receiving the second stop timer output signal and a second input terminal connected to the second comparator  918  for receiving the second comparison signal. The forty-fourth logic gate  1308   a  has an output terminal for generating the eighth intermediate signal. 
     The forty-fifth logic gate  1308   b  has a first input terminal connected to the output of the forty-third logic gate  1306  for receiving the ninth intermediate signal and a second input terminal connected to the output of the sixth mux  906   a  for receiving the second start timer output signal, and generates the second counter reset signal at its output terminal. 
     Referring now to  FIGS. 11A and 11B , a timing diagram illustrating a switching operation of the second clock switching system  900  when a currently selected clock signal is active is shown. In this example, a frequency of the third clock signal is 40 MHz, a frequency of the fifth clock signal is 10 MHz, and the second predetermined timer value is 7. 
     From time T 0 -T 6 , the first bit signal high and the second bit signal low so the third and fourth select signals are both low and the fifth select signal is high. The fourth enable signal is at logic high state and the third and fifth enable signals are at logic low state. Thus, the twenty-fourth logic gate  922  outputs the fifth clock signal as the second clock output signal since the currently selected clock signal is the fifth clock signal. 
     From time T 6 -T 11 , the first bit signal transitions from high to low and the second bit signal transitions from low to high. The second decoder  902  generates the fourth select signal at logic high state and the fifth select signal at logic low state. The seventh synchronizer  1106   a  receives the high fourth select signal and the ninth synchronizer  1206   a  receives the low fifth select signal. 
     From time T 11 -T 13 , the seventh synchronizer  1106   a  generates the seventh synchronizer signal at logic high state. The fourth positive edge detector  1108  receives the high seventh synchronizer signal and generates a low seventh detector output signal. The thirty-fifth logic gate  1120   b  receives the high fourth select signal and the high seventh detector output signal and generates a high fourth start timer signal. Since the sixth mux  906   a  receives the first and second bit signals at “01”, respectively, the sixth mux  906   a  outputs a high second start timer output signal. 
     From time T 13 -T 17 , the ninth synchronizer  1206   a  generates a low ninth synchronizer signal. The fortieth logic gate  1220   a  receives the low ninth synchronizer signal and generates the fourth enable signal at logic low state. The fourth positive edge detector  1108  generates the seventh detector output signal at logic low state. The thirty-fifth logic gate  1120   b  generates a low fourth start timer signal. The sixth mux  906   a  outputs the second start timer output signal at logic low state. The second enable control circuit  914  generates the second counter enable signal at logic high state. Since the fourth enable signal is low, the twenty-fourth logic gate  922  does not output the fifth clock signal as the second clock output signal. 
     From time period T 17 -T 19 , the second counter  916  receives a high second counter enable signal and starts the counting operation. 
     From time T 19 -T 21 , the eighth synchronizer  1106   b  generates a low eighth synchronizer signal. The thirty-third logic gate  1118  receives the low eighth synchronizer signal and generates the inverted eighth synchronizer signal at logic high state. The thirty-fourth logic gate  1120   a  receives the high seventh synchronizer signal and the low inverted eighth synchronizer signal and generates the third enable signal at logic high state. 
     The fourth negative edge detector  1110  generates the eighth detector output signal at logic high state. The thirty-sixth logic gate  1120   c  receives the fourth select signal at logic high state and the eighth detector output signal at logic high state, and generates the fourth stop timer signal at logic high state. Since the seventh mux  906   b  receives the first and second bit signals of “01”, the seventh mux  906   b  outputs the second stop timer output signal at logic high state. The second enable control circuit  914  generates the second counter reset signal at logic high state. 
     From time T 21 -T 29 , the fourth negative edge detector  1110  generates the eighth detector output signal at logic low state. The thirty-sixth logic gate  1120   c  generates the fourth stop timer signal at logic low state. The seventh mux  906   b  outputs the second stop timer output signal at logic low state and the second enable control circuit  914  generates the second counter enable signal at logic low state. The second enable control circuit  914  receives the second stop timer output signal at logic low state and generates the second counter enable signal at logic low state. Since the second count value is less than the second predetermined timer value (which in this example is 7), the second comparator  918  generates a low second comparison signal. Thus, the second NOT gate  919  generates the second timer reset signal at logic high state. The second enable control circuit  914  generates the second counter reset signal at logic low state. The second counter  916  terminates the counting operation and is reset. The twenty-fourth logic gate  922  generates the fourth clock signal as the second clock output signal. 
     Since the fourth enable signal transitions from high to low at time T 13  and the third enable signal transitions from low to high at time T 19 , the fourth and third enable signals are non-overlapping. Hence, the twenty-fourth logic gate  922  does not output either of the fourth or fifth clock signals as the first clock output signal during time T 13  to T 19 , so glitch-free switching between the fifth and fourth clock signals is provided. Further, as the fifth clock signal is active during the switching operation, the second timeout control circuit  908  does not enable the second timer reset signal during the switching operation and hence, generates the second timer reset signal at logic high state. 
     Referring now to  FIGS. 12A-12C , a timing diagram illustrating a switching operation of the second clock switching system  900  when a currently selected clock signal is inactive is shown. 
     From time period T 0 -T 5 , the first and second bit signals are at “10”. Hence, the fifth select signal is high and the third and fourth select signals are low. The fourth enable signal is at high and the third and fifth enable signals are low. Thus, the twenty-fourth logic gate  922  outputs the fifth clock signal as the second clock output signal, so the currently selected clock signal is the fifth clock signal. 
     After time T 5 , the fifth clock signal is inactive so the twenty-fourth logic gate  922  does not output the fifth clock signal as the second clock output signal. 
     From time T 6 -T 11 , the first bit signal transitions from high to low and the second bit signal transitions from low to high. Thus, the second decoder  902  generates a high fourth select signal and a low fifth select signal. 
     From time period T 11 -T 13 , the seventh synchronizer  1106   a  generates a high seventh synchronizer signal. The fourth positive edge detector  1108  receives the high seventh synchronizer signal and generates a high seventh detector output signal. The thirty-fifth logic gate  1120   b  receives the fourth select signal at logic high state and the seventh detector output signal at logic high state, and generates the fourth start timer signal at logic high state. The sixth mux  906   a  receives the high fourth start timer signal and outputs the second start timer output signal at logic high state. 
     From time T 13 -T 17 , the fourth positive edge detector  1108  generates the seventh detector output signal at logic low state. The thirty-fifth logic gate  1120   b  generates the fourth start timer signal at logic low state. The sixth mux  906   a  outputs the second start timer output signal at logic low state. The second enable control circuit  914  generates the second counter enable signal at logic high state. The second counter  916  receives the second counter enable signal at logic high state. 
     From time T 17 -T 41 , the second counter  916  counts the second count value. Since the second count value is less than the second predetermined timer value, the second comparator  918  generates a low second comparison signal, and the second NOT gate  919  generates a high second timer reset signal. 
     From time period T 41 -T 45 , the second count value is 7. Since the second count value is equal to the second predetermined timer value, the second comparator  918  generates a high second comparison signal so the second NOT gate  919  generates a low second timer reset signal. The second enable control circuit  914  receives the high second comparison signal and generates a high second counter reset signal. 
     The twenty-sixth logic gate  1014  receives the third select signal at logic low state and the second timer reset signal at logic low state and generates the third intermediate reset signal at logic low state. The third reset synchronizer  1016  receives the third intermediate reset signal at logic low state and generates the third reset synchronizer signal at logic low state, which resets the fifth and sixth synchronizers  1006   a  and  1006   b  and the third positive and negative edge detectors  1008  and  1010 . Thus, the third switchover control circuit  904   a  is reset. 
     The thirty-eighth logic gate  1214  receives the fifth select signal at logic low state and the second timer reset signal at logic low state, and generates the fifth intermediate reset signal at logic low state. The fifth reset synchronizer  1216  receives the low fifth intermediate reset signal and generates the fifth reset synchronizer signal at logic low state, which resets the ninth and tenth synchronizers  1206   a  and  1206   b  and the fifth positive and negative edge detectors  1208  and  1210 . Thus, the ninth synchronizer  1206   a  generates the ninth synchronizer signal at logic low state. The fortieth logic gate  1220   a  receives the ninth synchronizer signal at logic low state and generates the fourth enable signal at logic low state, which resets the fifth switchover control circuit  904   c.    
     The thirty-second logic gate  1114  receives the fourth select signal at logic high state and the second timer reset signal at logic low state, and generates the fourth intermediate reset signal at logic high state. The fourth reset synchronizer  1116  receives the high fourth intermediate reset signal, so the fourth reset synchronizer  1116  generates the fourth reset synchronizer signal at logic high state. Hence, the fourth switchover control circuit  904   b  does not reset. 
     From time T 45 -T 47 , the second comparator  918  generates the second comparison signal at logic low state. The second NOT gate  919  generates the second timer reset signal at logic high state. The second enable control circuit  914  generates the second counter enable signal at logic low state. The second enable control circuit  914  generates the second counter reset signal at logic low state, so the second counter  916  stops counting and is reset. The twenty-sixth logic gate  1014  receives the second timer reset signal at logic high state and generates the third intermediate reset signal at logic high state. The third reset synchronizer  1016  receives the third intermediate reset signal at logic high state. 
     From time T 47 -T 49 , the third reset synchronizer  1016  generates the third reset synchronizer signal at logic high state. The third switchover control circuit  904   a  comes out of reset. The eighth synchronizer  1106   b  generates the eighth synchronizer signal at logic low state. The thirty-third logic gate  1118  receives the low eighth synchronizer signal and generates the inverted eighth synchronizer signal at logic high state. The thirty-fourth logic gate  1120   a  receives the seventh synchronizer signal at logic high state and the inverted eighth synchronizer signal at logic high state, and generates the third enable signal at logic high state. The fourth negative edge detector  1110  generates the eighth detector output signal at logic high state and the thirty-sixth logic gate  1120   c  generates the fourth stop timer signal at logic high state. Thus, the seventh mux  906   b  outputs the second stop timer output signal at logic high state. 
     From time T 49 -T 53 , the fourth negative edge detector  1110  generates a low eighth detector output signal so the thirty-sixth logic gate  1120   c  generates a low fourth stop timer signal. The seventh mux  906   b  outputs the second stop timer output signal at logic low state. The twenty-fourth logic gate  922  generates the fourth clock signal as the second clock output signal. 
     Since the fourth enable signal transitions from high to low at time T 41  and the third enable signal transitions from low to high at time T 47  the fourth and third enable signals are non-overlapping. Hence, the twenty-fourth logic gate  922  does not output either of the fifth and fourth clock signals as the second clock output signal from time T 41 -T 47 , so glitch-free switching between the fifth and fourth clock signals is provided. 
     The second clock switching system  900  switches from the fifth clock signal to the fourth clock signal even when the fifth clock signal is inactive. Further, as the fifth clock signal is inactive during the switching operation, the second timeout control circuit  908  enables the second timer reset signal during the switching operation and hence, generates a low second timer reset signal for resetting the third and fifth switchover control circuits  904   a  and  904   c.    
     It will be apparent to those of skill in the art that when the second clock switching system  900  provides switching from the fifth clock signal to the fourth clock signal and the fifth clock signal is inactive, all switchover control circuits except the switchover control circuit that is performing functions using the fourth clock signal are reset. Thus, the second clock switching system  900  can be utilized for providing the second clock output signal at various clock frequencies, i.e., the second clock switching system  900  can provide switching between multiple clock signals. 
     It will be understood by those of skill in the art that the present invention can be extended to switching between more than three clock signals. 
     It will be understood by those of skill in the art that the same logical function may be performed by different arrangements of logic gates, or that logic circuits operate using either positive or negative logic signals. Therefore, variations in the arrangement of some of the logic gates described above should not be considered to depart from the scope of the present invention. No element, act, or instruction used in the present application should be construed as critical or essential to the invention unless explicitly described as such. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. 
     While various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present invention, as described in the claims.