Abstract:
A level shifter ESD protection circuit with power-on-sequence consideration used for receiving a first signal and outputting a second signal is provided. The level shifter circuit includes an inverter, a first switch, a second switch, a voltage level shifting circuit, a first ESD clamp and a second ESD clamp circuits. When the first power supply has been powered on and the second power supply is off, the first and second switches will remain off resulting from the power-off of the second power supply. Therefore, the second power source would not be affected by the first power supply because of passing through the ESD protection circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the priority benefit of Taiwan application serial no. 94124040, filed on Jul. 15, 2005. All disclosure of the Taiwan application is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of Invention  
         [0003]     The present invention relates to an electrostatic discharge (ESD) protection circuit. More specifically, the present invention relates to a level shifter ESD protection circuit with power-on-sequence consideration.  
         [0004]     2. Description of Related Art  
         [0005]     In mixed-voltage IC, as shown in  FIG. 1A , different internal circuits are supplied with power by the system voltage with different voltage levels, respectively.  FIG. 1A  is a block diagram of a portion of the circuit of a general mixed-voltage IC. In  FIG. 1A , the operation power of the internal circuit  110  is provided by system voltage VDD 1  (for example, 3.3 volts) and ground voltage VSS 1  (for example, 0 volt). In addition, the operation power of the internal circuit  130  is provided by system voltage VDD 2  (for example, 12 volts) and ground voltage VSS 2  (for example, 0 volt). Since the input/output logic levels of the internal circuit  110  and the internal circuit  130  are different, a level shifter is needed to serve as the interface circuit of the internal circuit  110  and the internal circuit  130 . For example, the level shifter  120  receives the output signal  111  (for example, 0˜3.3 volts) output by the internal circuit  110 , transforms the same into a corresponding signal  131  (for example, 0˜12 volts) and outputs the same to the internal circuit  130 .  
         [0006]     When electrostatic discharge (ESD) happens at the connecting end of the mixed-voltage IC, the instantaneous ESD current would flows along the low impedance path in IC in a large volume. The large volume ESD current would generate high temperature and damage any components in the path of the current.  FIG. 1B  is a schematic diagram of the level shifter  120  and the ESD path in  FIG. 1A . For example, as shown in  FIG. 1B , when ESD event happens at the connecting end of the ground voltage VSS 2 , if the system voltage VDD 1  is grounded, then the ESD current passes through the gate capacitor of the transistor  121  from the ground voltage line VSS 2 , flows to the system voltage line VDD 1  (the dotted line ESD 1  of the current path shown in the figure). Or, if the system voltage VSS 1  is grounded, then the ESD current passes through the gate capacitor of the transistor  121  from the ground voltage line VSS 2  and travels to the ground voltage line VSS 1  (the dotted line ESD 2  of the current path shown in the figure). As a result, the transistor  121  may be damaged (in the same principle, the transistor  122  may also be damaged).  
         [0007]     The main cause of the damage of the above components is because there is no connection between the ground voltage line VSS 1  and the ground voltage line VSS 2 . Therefore, the electrostatic discharge current ESD is not able to be conducted to the ground voltage line VSS 2  via the ground voltage line VSS 1 , but only through the silicon substrate. If the substrate impedance is not small enough, the electrostatic discharge current ESD may damage the transistor  121 . Since the ESD is instantaneous, therefore in the case of electrostatic discharge, the impedance of gate capacitor is less than the impedance of normal operation.  
         [0008]      FIG. 1C  is a schematic diagram of another level shifter  120  and ESD path in  FIG. 1A . As shown in  FIG. 1C , the gravity of regular ESD occurred in the system voltage line VDD 2  is severer than the regular ESD occurred in the ground voltage line VSS 2 . That is because the ground voltage line VSS 2  still has the substrate as the connection path connecting the ground voltage line VSS 1 , yet there is no discharging path in N well to help balance charge. Therefore, for example, when ESD event happens at the connecting end of the system voltage line VDD 2 , if system voltage VDD 1  is grounded, then the electrostatic discharge current ESD travels through the gate capacitor of the transistor  123  from the system voltage line VDD 2  and arrives at the system voltage line VDD 1  (the dotted line ESD 1  of the current path shown in  FIG. 1C ). Or, if the ground voltage line VSS 1  is grounded, then the electrostatic discharge current ESD travels through the gate capacitor of the transistor  123  from the system voltage line VDD 2  and arrives at the ground voltage line VSS 1  (the dotted line ESD 2  of the current path shown in  FIG. 1C ). As a result, the transistor  123  may be damaged (same principle, the transistor  124  may also be burned).  
         [0009]     An ESD protection circuit (such as Taiwan Patent No. I234266) may be disposed in the level shifter  120  by those who are skilled in the art to avoid the level shifter  120  from damaged by ESD current. However, system voltage line VDD 1  and system voltage line VDD 2  are usually not powered on at the same time. For example, the mixed-voltage IC cuts off the power supply of the system voltage line VDD 2  when entering power saving mode, while the power supply of the system voltage line VDD 1  is maintained. If the power-on-sequence is taken into consideration, because of the disposition of the ESD protection circuit, the first powered-on power supply may affect the power which is not yet powered on and the related circuits thereof. For example,  FIG. 1D  schematically describes that, through the disposed ESD protection circuit, the power supply which has not been powered on and the related circuits are affected by the power supply which has been powered on earlier.  
         [0010]     With reference to  FIG. 1D , when the power supply of the system voltage line VDD 1  is activated first before the power supply of the system voltage line VDD 2 , the system voltage line VDD 1  supplies power to the system voltage line VDD 2  via the transistor  125  and the ESD clamp circuit  126  (and/or the ESD clamp circuit  127 ). Therefore, the internal circuit  130  which should be turned off may be turned on because of the power supplied by the system voltage line VDD 1 . In addition, since the operating voltage of the internal circuit  130  is different from the voltage of the internal circuit  110 , when the system voltage line VDD 1  supplies power to the system voltage line VDD 2  via the ESD clamp circuit, error of the internal circuit  130  will occur, and even the internal circuit  130  may be damaged.  
       SUMMARY OF THE INVENTION  
       [0011]     The object of the present invention is to provide a level shifter ESD protection circuit with the power-on-sequence consideration to avoid the possible damage to the level shifter when the ESD current flows to another power supply connecting point from the connecting point of one power supply group of a plurality of power supply groups. In addition, the problem that the power which has not been started yet is affected by the power which has been started earlier passing through ESD clamp circuit due to different power-on-sequence can be avoided.  
         [0012]     Another object of the present invention is to provide a level shifter ESD protection circuit with another power-on-sequence consideration; another ESD path is used to protect the level shifter from being damaged, and the problem that the power supply which is not yet started being affected by the power which has started earlier via the ESD clamp circuit can be avoided.  
         [0013]     Another object of the present invention is to provide another level shifter ESD protection circuit with the power-on-sequence consideration; another ESD path is further used to connect different power supply groups so as to avoid the level shifter being damaged by the ESD current, and to avoid the power supply which is not yet started being affected by the power supply which has been started earlier via the ESD clamp circuit.  
         [0014]     Base on the above and other objects, the present invention provides a level shifter ESD protection circuit with consideration of power-on-sequence to receive a first signal and to output a second signal with a corresponding level according to the level of the first signal. Wherein, the first signal operates between the first system voltage and the first ground voltage, and the second signal operates between the second system voltage and the second ground voltage. The level shifter ESD protection circuit includes an inverter, a first switch, a second switch, a voltage level shifting circuit, a first ESD clamp circuit and a second ESD clamp circuit. The inverter receives the first signal and outputs the first inverted signal, wherein the first inverted signal is the inverse of the first signal, and the first inverted signal operates between the first system voltage and the first ground voltage. The first end of the first switch is connected to the output end of the inverter and receives the first inverted signal. The first end of the second switch receives the first signal. The first switch and the second switch respectively determine the connection status of their first end and second end according to the level of the second system voltage. The first input end of the voltage level shifting circuit is connected to the second end of the first switch, and the second input end of the voltage level shifting circuit is connected to the second end of the second switch; the output end of the voltage level shifting circuit outputs the second signal. The first connecting ends of the first and the second ESD clamp circuits are both connected to the second system voltage, and the second connecting ends of the first and the second ESD clamp circuits are respectively connected to the first input end and the second input end of the voltage level shifting circuit.  
         [0015]     From another point of view, the present invention provides a level shifter ESD protection circuit with the consideration of power-on-sequence. This level shifter ESD protection circuit includes the inverter, the first switch, the second switch, the voltage level shifting circuit, the first ESD clamp circuit and the second ESD clamp circuit. The inverter receives the first signal and outputs the first inverted signal. The first end of the first switch is connected to the output end of the inverter to receive the first inverted signal. The first end of the second switch receives the first signal. The first switch and the second switch respectively determine the connection status of their first end and second end according to the level of the second system voltage. The first input end and the second input end of the voltage level shifting circuit are respectively connected to the second end of the first switch and the second switch, and the output end of the voltage level shifting circuit outputs the second signal. The first connecting ends of the first and the second ESD clamp circuits are respectively connected to the first and the second input end of the voltage level shifting circuit, and the second connecting ends of the first and the second ESD clamp circuits are both connected to the second ground voltage.  
         [0016]     The present invention further provides another level shifter ESD protection circuit with the power-on-sequence consideration, which includes the inverter, the first switch, the second switch, the voltage level shifting circuit and the ESD clamp circuit. The inverter receives the first signal and outputs the first inverted signal. The first end of the first switch is connected to the output end of the inverter to receive the first inverted signal. The first end of the second switch receives the first signal. The first switch and the second switch respectively determine the connection status of their first end and second end of the first switch and the second switch according to the level of the second system voltage. The first input end and the second input end of the voltage level shifting circuit are respectively connected to the second end of the first switch and the second switch, and the output end of the voltage level shifting circuit outputs the second signal. The first connecting end of the ESD clamp circuit is connected to the second system voltage, and the second connecting end of the ESD clamp circuit is connected to the first ground voltage.  
         [0017]     Since the present invention utilizes the ESD clamp circuit, therefore the current path can be provided to conduct the instantaneous large volume ESD current between different power supply groups, and thus the damage to the internal circuit (especially the level shifter) in IC can be avoided. In addition, the switch-on/switch-off is controlled by the power-on/power-off, therefore, the problem that the power not yet started is affected by the power which has started earlier passing through the ESD clamp circuit due to different power-on-sequence can be avoided.  
         [0018]     In order to the make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]      FIG. 1A  is a block diagram of a portion of the circuit of a general mixed-voltage IC.  
         [0020]      FIG. 1B  is a schematic diagram of the level shifter and the ESD path in  FIG. 1A .  
         [0021]      FIG. 1C  is a schematic diagram of another level shifter and ESD path in  FIG. 1A .  
         [0022]      FIG. 1D  schematically describes how the earlier powered-on power affects the power which has not been powered-on because of the disposition of the ESD protection circuit.  
         [0023]      FIG. 2A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to an embodiment of the present invention.  
         [0024]      FIG. 2B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to the embodiment of the present invention.  
         [0025]      FIG. 3A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention.  
         [0026]      FIG. 3B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to another embodiment of the present invention.  
         [0027]      FIG. 4A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention.  
         [0028]      FIG. 4B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to another embodiment of the present invention.  
         [0029]      FIG. 5A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention.  
         [0030]      FIG. 5B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to the embodiment of the present invention.  
         [0031]      FIG. 6A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention.  
         [0032]      FIG. 6B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to another embodiment of the present invention.  
         [0033]      FIG. 7A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention.  
         [0034]      FIG. 7B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to another embodiment of the present invention.  
     
    
     DESCRIPTION OF EMBODIMENTS  
       [0035]      FIG. 2A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to an embodiment of the present invention. With reference to  FIG. 2A , the level shifter  220  receives the first signal  211  outputting from the internal circuit  210  in IC and outputs the second signal  231  (received by the internal circuit  230  in IC) with corresponding level according to the level of the first signal  211 . Wherein, the first signal  211  operates between the first system voltage VDD 1  (herein, for example, 3.3 volts) and the first ground voltage VSS 1  (herein, for example, 0 volt). And the second signal  231  operates between the second system voltage VDD 2  (herein, for example, 12 volts) and the second ground voltage VSS 2  (herein, for example, 0 volt).  
         [0036]     In the present embodiment, the level shifter  220  includes the inverter  240 , the voltage level shifting circuit  250 , the first ESD clamp circuit  260 , the second ESD clamp circuit  270 , the first switch  280  and the second switch  290 . The inverter  240  receives the first signal  211  and outputs the first inverted signal  241 . Wherein, the first inverted signal  241  is the inverse of the first signal  211 ; the first inverted signal  241  operates between the first system voltage VDD 1  and the first ground voltage VSS 1 .  
         [0037]     Here, the inverter  240 , for example, includes a P transistor  242  and an N transistor  244 . The source of the transistor  242  is connected to the first system voltage VDD 1 ; the gate of the transistor  242  receives the first signal  211 ; and the drain of the transistor  242  outputs the first inverted signal  241 . The gate of the transistor  244  receives the first signal  211 ; the drain of the transistor  244  is connected to the drain of the transistor  242 ; and the source of the transistor  244  is connected to the first ground voltage VSS 1 .  
         [0038]     The first end of the first switch  280  is connected to the output end of the inverter  240  and receives the first inverted signal  241 . The first end of the second switch  290  receives the first signal  211 . The first switch  280  and the second switch  290  respectively determine the connection status between the first end and second end according to the level of the second system voltage VDD 2 . In other words, when the second system voltage VDD 2  is powered on, both the first switch  280  and the second switch  290  are switched on; on the contrary, when the second system voltage VDD 2  is off, both the first switch  280  and the second switch  290  are switched off.  
         [0039]     In the present embodiment, the first switch  280  includes an N transistor  281 . The gate of the transistor  281  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the first switch  280 . The second switch  290  includes an N transistor  291 . The gate of the transistor  291  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the second switch  290 .  
         [0040]     The first input end of the voltage level shifting circuit  250  is connected to the second end of the first switch  280 , the second input end of the voltage level shifting circuit  250  is connected to the second end of the second switch  290 , and the output end of the voltage level shifting circuit  250  outputs the second signal  231 . The voltage level shifting circuit  250 , for example, includes the P transistors T 1 , T 2 , T 4 , T 5  and the N transistors T 3  and T 6 . The first source/drain (hereinafter “the source”) of the first transistor T 1  is connected to the second system voltage VDD 2 . The gate of the second transistor T 2  is the first input end of the voltage level shifting circuit  250 . The first source/drain (hereinafter “the source”) of the transistor T 2  is connected to the second source/drain (hereinafter “the drain”) of the transistor T 1 . The gate of the third transistor T 3  is connected to the gate of the transistor T 2 . The first source/drain (hereinafter “the drain”) of the transistor T 3  is connected to the second source/drain (hereinafter “the drain”) of the transistor T 2 . The second source/drain (hereinafter “the source”) is connected to the second ground voltage VSS 2 . The first source/drain (hereinafter “the source”) of the fourth transistor T 4  is connected to the second system voltage VDD 2 , the gate of the transistor T 4  is connected to the drain of the transistor T 2 . The gate of the fifth transistor T 5  is the second input end of the voltage level shifting circuit  250 . The first source/drain (hereinafter “the source”) of the transistor T 5  is connected to the second source/drain (hereinafter “the drain”) of the transistor T 4 , while the second source/drain (hereinafter “the drain”) of the transistor T 5  is connected to the gate of the transistor T 1 . The gate of the transistor T 6  is connected to the gate of the transistor T 5 . The first source/drain (hereinafter “the drain”) of the transistor T 6  is connected to the drain of the transistor T 5 . The second source/drain (hereinafter “the source”) of the transistor T 6  is connected to the second ground voltage VSS 2 . Wherein, the drain signal of the transistor T 6  is the second signal  231 .  
         [0041]     The second connecting end of the first ESD clamp circuit  260  is connected to the first input end of the voltage level shifting circuit  250 , while the first connecting end of the first ESD clamp circuit  260  is connected to the second system voltage VDD 2 . The second connecting end of the second ESD clamp circuit  270  is connected to the second input end of the voltage level shifting circuit  250 , while the first connecting end of the second ESD clamp circuit  270  is connected to the second system voltage VDD 2 .  
         [0042]     In the present embodiment, the first ESD clamp circuit  260 , for example, includes a P transistor. Wherein, the drain of the P transistor is connected to the first input end of the voltage level shifting circuit  250 , while the gate, the source and the bulk of the P transistor are all connected to the second system voltage VDD 2 . Or, as known by those who are skilled in the art, the first ESD clamp circuit  260  can also be implemented using diode or other method, and its result is also within the scope of the present invention.  FIG. 2B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to the embodiment of the present invention. With reference to  FIG. 2B , if the first ESD clamp circuit  260  is implemented with diode, the anode of the diode is connected to the first input end of the voltage level shifting circuit  250 , while the cathode of the diode is connected to the second system voltage VDD 2 . In the present embodiment, since the implementation of the second ESD clamp circuit  270  is similar to that of the first ESD clamp circuit  260 , therefore the details are omitted.  
         [0043]     Therefore, when the ESD event happens at the connecting end of the second system voltage line VDD 2 , if the system voltage VDD 1  is grounded, the ESD current will flow to the system voltage line VDD 1  from the system voltage line VDD 2  via the first ESD clamp circuit  260  and the transistor  242 . Or, if the ground voltage line VSS 1  is grounded, the ESD current will flow to the ground voltage line VSS 1  from the system voltage line VDD 2  via the first ESD clamp circuit  260  and the transistor  244 . Therefore, the damage to the level shifter  220  can be avoided. Moreover, the on/off of the control switches  280  and  290  are controlled based on the power-on/power-off of the second system voltage VDD 2 , therefore, the phenomenon that the second system voltage VDD 2  which has not been powered on is affected by the first system voltage VDD 1  which has been powered on earlier and passes through the ESD clamp circuit can be avoided.  
         [0044]     An embodiment is provided to clearly describe the present invention.  FIG. 3A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 3A , the level shifter  350  receives the first signal  311  output by the internal circuit  310  in IC and outputs the second signal  331  (received by the internal circuit  330  in IC) with the corresponding level according to the level of the first signal  311 . Wherein, the first signal  311  operates between the first system voltage VDD 1  (for example, 3.3 volts) and the first ground voltage VSS 1  (for example, 0 volt). And the second signal  331  operates between the second system voltage VDD 2  (for example, 12 volts) and the second ground voltage VSS 2  (for example, 0 volt). The level shifter  320  includes an inverter  340 , a voltage level shifting circuit  350 , a first ESD clamp circuit  360 , a second ESD clamp circuit  370 , a first switch  380  and a second switch  390 .  
         [0045]     The inverter  340  receives the first signal  311  and outputs a first inverted signal  341 . Wherein, the first inverted signal  341  is the inverse of the first signal  311 , and the first inverted signal  341  operates between the first system voltage VDD 1  and the first ground voltage VSS 1 . In the present embodiment, the inverter  340 , for example, includes a P transistor  342  and an N transistor  344 . The source of the transistor  342  is connected to the first system voltage line VDD 1 , the gate of the transistor  342  receives the first signal  311 , and the drain of the transistor  342  outputs the first inverted signal  341 . The gate of the transistor  344  receives the first signal  311 , the drain of the transistor  344  is connected to the drain of the transistor  342 , and the source of the transistor  344  is connected to the first ground voltage VSS 1 .  
         [0046]     The first end of the first switch  380  is connected to the output end of the inverter  340  and receives the first inverted signal  341 . The first end of the second switch  390  receives the first signal  311 . The first switch  380  and the second switch  390  respectively determine the connection status between the first end and second end according to the level of the second system voltage VDD 2 . In other words, when the second system voltage VDD 2  is powered on, both the first switch  380  and the second switch  390  are conducted; and contrariwise, when the second system voltage VDD 2  is powered off, both the first switch  380  and the second switch  390  are cut off.  
         [0047]     In the present invention, the first switch  380  includes an N transistor  381 . The gate of the transistor  381  is connected to the second system voltage VDD 2 , the first connecting end and the second connecting end of the transistor  381  are respectively the first end and the second end of the first switch  380 . The second switch  390  includes an N transistor  391 . The gate of the transistor  391  is connected to the second system voltage VDD 2 , the first connecting end and the second connecting end of the transistor  391  are respectively the first end and the second end of the second switch  390 .  
         [0048]     The first input end of the voltage level shifting circuit  350  is connected to the second end of the first switch  380 , the second input end of the voltage level shifting circuit  350  is connected to the second end of the second switch  390 , and the output end of the voltage level shifting circuit  350  outputs the second signal  331 . The second connecting end of the first ESD clamp circuit  360  is connected to the second ground voltage VSS 2 , the first connecting end of the first ESD clamp circuit  360  is connected to the first input end of the voltage level shifting circuit  350 . The second connecting end of the second ESD clamp circuit  370  is connected to the second ground voltage VSS 2 , the first connecting end of the second ESD clamp circuit  370  is connected to the first input end of the voltage level shifting circuit  350 .  
         [0049]     In the present embodiment, the voltage level shifting circuit  350 , for example, includes the P transistors T 1 , T 3  and N transistors T 2  and T 4 . The first source/drain (hereinafter “the source”) of the first transistor T 1  is connected to the second system voltage VDD 2 . The gate of the second transistor T 2  is the first input end of the voltage level shifting circuit  350 . The first source/drain (hereinafter “the drain”) of the second transistor T 2  is connected to the second source/drain (hereinafter “the drain”) of the first transistor T 1 . The second source/drain (hereinafter “the source”) of the transistor T 2  is connected to the second ground voltage VSS 2 . The first source/drain (hereinafter “the source”) of the third transistor T 3  is connected to the second system voltage VDD 2 , and the second source/drain (hereinafter “the drain”) of the transistor T 3  is connected to the gate of the transistor T 1 , and the gate of the transistor T 3  is connected to the drain of the transistor T 1 . The gate of the transistor T 4  is the second input end of the voltage level shifting circuit  350 . The first source/drain (hereinafter “the drain”) of the transistor T 4  is connected to the drain of the transistor T 3 , and the second source/drain (hereinafter “the source”) of the transistor T 4  is connected to the second ground voltage VSS 2 . Wherein, the drain signal of the transistor T 4  is the second signal  331 .  
         [0050]     In the present embodiment, the first ESD clamp circuit  360 . for example, includes an N transistor. Wherein, the drain of the N transistor is connected to the first input end of the voltage level shifting circuit  350 , and the gate, the source and the bulk of the N transistor are all connected to the second ground voltage VSS 2 . Or, as known by those who are skilled in the art, the first ESD clamp circuit  360  can also be implemented using diode or other method, and its result is also within the scope of the present invention.  FIG. 3B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 3B , if the first ESD clamp circuit  360  is implemented with diode, the cathode of the diode is connected to the first input end of the voltage level shifting circuit  350 , while the anode of the diode is connected to the second ground voltage VSS 2 . In the present embodiment, since the implementation of the second ESD clamp circuit  370  is similar to that of the first ESD clamp circuit  360 , the details are omitted.  
         [0051]     Therefore, when the ESD event happens at the connecting end of the ground voltage VSS 2 , if the system voltage VDD 1  is grounded, the ESD current will flow to the system voltage line VDD 1  from the ground voltage line VSS 2  via the first ESD clamp circuit  360  and the transistor  342 . Or, if the ground line VSS 1  is grounded, the ESD current will flow to the ground voltage line VSS 1  from the ground voltage line VSS 2  via the first ESD clamp circuit  360  and the transistor  244 . Moreover, the on/off of the control switches  380  and  390  are controlled based on the power-on/power-off of the second system voltage VDD 2 ; therefore, the problem that the second system voltage VDD 2  which has not been power-on is affected by the first system voltage VDD 1  which has been power-on earlier and passes through the ESD clamp circuit can be avoided.  
         [0052]     To more clearly and specifically illustrate the present invention, another embodiment is further provided herein.  FIG. 4A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 4A , the level shifter circuit  420  receives the first signal  411  output by the internal circuit  410  in IC and outputs the second signal  431  (received by the internal circuit  430  in IC) with the corresponding level according to the level of the first signal  411 . Wherein the first signal  411  operates between the first system voltage VDD 1  (for example, 3.3 volts) and the first ground voltage VSS 1  (for example, 0 volt). And the second signal  431  operates between the second system voltage VDD 2  (for example, 12 volts) and the second ground voltage VSS 2  (for example, 0 volt).  
         [0053]     In the present embodiment, the level shifter circuit  420 , for example, includes an inverter  440 , a voltage level shifting circuit  450 , an ESD clamp circuit  460 , a first switch  480  and a second switch  490 . The inverter  440  receives the first signal  411  and outputs the first inverted signal  441 . Wherein, the first inverted signal  441  is the inverse of the first signal  411 , and the first inverted signal  441  operates between the first system voltage VDD 1  and the first ground voltage VSS 1 .  
         [0054]     The first end of the first switch  480  is connected to the output end of the inverter  440  and receives the first inverted signal  441 . The first end of the second switch  490  receives the first signal  411 . The first switch  480  and the second switch  490  respectively determine the connection status between the first end and second end according to the level of the second system voltage VDD 2 . In other words, when the second system voltage VDD 2  is powered on, both the first switch  480  and the second switch  490  are conducted; and contrariwise, when the second system voltage VDD 2  is powered off, both the first switch  480  and the second switch  490  are switched off.  
         [0055]     In the present embodiment, the first switch  480  includes an N transistor  481 . The gate of the transistor  481  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the first switch  480 . The second switch  490  includes an N transistor  491 . The gate of the transistor  491  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the second switch  490 .  
         [0056]     Herein, since the voltage level shifting circuit  450  and the inverter  440 , for example, are the same as the voltage level shifting circuit  250  and the inverter  240  in  FIG. 2A  in the previous embodiment, therefore the description is omitted.  
         [0057]     The first connecting end of the first ESD clamp circuit  460  is connected to the second system voltage VDD 2 , the second connecting end of the first ESD clamp circuit  460  is connected to the first ground voltage VSS 2 . In the present embodiment, the ESD clamp circuit  460 , for example, includes a transistor. Wherein, the collector of the transistor is connected to the second system voltage VDD 2 ; the base and the emitter of the transistor are connected to the first ground voltage VSS 1 . Or, as known by those who are skilled in the art, the ESD clamp circuit  460  can also be implemented using diode or other method, and the result thereof is also within the scope of the present invention.  FIG. 4B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 4B , if the ESD clamp circuit  460  is implemented with diode, the anode of the diode is connected to the first ground voltage VSS 1 , while the cathode of the diode is connected to the second system voltage VDD 2 .  
         [0058]     Therefore, when the ESD event happens at the connecting end of the system voltage line VDD 2 , if the ground voltage line VSS 1  is grounded, the ESD current will flow to the ground voltage line VSS 1  from the system voltage VDD 2  via the ESD clamp circuit  460 . Therefore, the damage to the level shifter circuit  420  can be avoided. Moreover, the on/off of the control switches  480  and  490  is controlled based on the power-on/power-off of the second system voltage VDD 2 ; thus, the phenomenon that the second system voltage VDD 2  which is not power-on is affected by the first system voltage VDD 1  which has been power-on earlier can be avoided.  
         [0059]      FIG. 5A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 4B , the level shifter circuit  520  receives the first signal outputting from the internal circuit  510  in IC and outputs the second signal  531  (received by the internal circuit  530  in IC) with the corresponding level according to the level of the first signal  511 . Wherein, the first signal  511  operates between the first system voltage VDD 1  (for example, 12 volts) and the first ground voltage VSS 1  (for example, 0 volt), and the second signal  531  operates between the second system voltage VDD 2  (for example, 3.3 volts) and the second ground voltage VSS 2  (for example, 0 volt).  
         [0060]     In the present embodiment, the level shifter  520  includes the inverter  540 , the voltage level shifting circuit  550 , the ESD clamp circuit  560 , the ESD clamp circuit  570 , the first switch  580  and the second switch  590 . The inverter  540  receives the first signal  511  and outputs the first inverted signal  541 . Wherein, the first inverted signal  541  is the inverse of the first signal  511 , and the first inverted signal  541  operates between the first system voltage VDD 1  and the first ground voltage VSS 1 .  
         [0061]     The first end of the first switch  580  is connected to the output end of the inverter  540  and receives the first inverted signal  541 . The first end of the second switch  590  receives the first signal  511 . The first switch  580  and the second switch  590  respectively determine the connection status between the first end and second end according to the level of the second system voltage VDD 2 . In other words, when the second system voltage VDD 2  is powered on, both the first switch  580  and the second switch  590  are switched on; on the contrary, when the second system voltage VDD 2  is powered off, both the first switch  280  and the second switch  290  are switched off.  
         [0062]     In the present embodiment, the first switch  580  includes an N transistor  581 . The gate of the transistor  581  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the first switch  580 . The second switch  590  includes an N transistor  591 . The gate of the transistor  591  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the second switch  590 .  
         [0063]     In the present embodiment, the voltage level shifting circuit  550 , for example, includes the P transistors T 1 , T 3 , and N transistors T 2  and T 4 . The first source/drain (hereinafter “the source”) of the transistor T 1  is connected to the second system voltage VDD 2 , the gate of the transistor T 1  is the first input end of the voltage level shifting circuit  550 . The first source/drain (hereinafter “the drain”) of the transistor T 2  is connected to the second source/drain (hereinafter “the drain”) of the transistor T 1 . The second source/drain (hereinafter “the source”) of the transistor T 2  is connected to the second ground voltage VSS 2 . The first source/drain (hereinafter “the source”) of the transistor T 3  is connected to the second system voltage VDD 2 , and the second source/drain (hereinafter “the drain”) of the transistor T 3  is connected to the gate of the transistor T 2 , and the gate of the transistor T 3  is the second input end of the voltage level shifting circuit  550 . The gate of the transistor T 4  is connected to the drain of the transistor T 1 , and the first source/drain (hereinafter “the drain”) of the transistor T 4  is connected to the drain of the transistor T 3 , and the second source/drain (hereinafter “the source”) of the transistor T 4  is connected to the second ground voltage VSS 2 . Wherein, the signal of the drain of the transistor T 4  is the second signal  531 .  
         [0064]     The first connecting end of the ESD clamp circuit  560  is connected to the second system voltage VDD 2 , while the second connecting end of the ESD clamp circuit  560  is connected to the gate of the transistor T 1 . In the present embodiment, the ESD clamp circuit  560 , for example, includes a P transistor. Wherein, the drain of the P transistor is connected to the first input end (the gate of the transistor T 1 ) of the voltage level shifting circuit  550 , and the gate, the source and the bulk of the P transistor are all connected to the second system voltage VDD 2 . Or, as known by those who are skilled in the art, the ESD clamp circuit  560  can also be implemented using diode or other method, and the result thereof is also within the scope of the present invention.  FIG. 5B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to the embodiment of the present invention. With reference to  FIG. 5B , if the ESD clamp circuit  560  is implemented with diode, the anode of the diode is connected to the first input end of the voltage level shifting circuit  550 , while the cathode of the diode is connected to the second system voltage VDD 2 .  
         [0065]     In the present embodiment, since the implementation of the second ESD clamp circuit  570  is similar to that of the first ESD clamp circuit  560 , therefore it will not be described again.  
         [0066]      FIG. 6A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 6A , the level shifter circuit  620  receives the first signal  611  output by the internal circuit  610  in IC and outputs the second signal  631  (received by the internal circuit  630  in IC) with the corresponding level according to the level of the first signal  611 . Wherein, the first signal  611  operates between the first system voltage VDD 1  (for example, 12 volts) and the first ground voltage VSS 1  (for example, 0 volt). And the second signal  631  operates between the second system voltage VDD 2  (for example, 3.3 volts) and the second ground voltage VSS 2  (for example, 0 volt).  
         [0067]     In the present embodiment, the level shifter  620  includes the inverter  640 , the voltage level shifting circuit  650 , the ESD clamp circuit  660 , the ESD clamp circuit  670 , the first switch  680  and the second switch  690 . The inverter  640  receives the first signal  611  and outputs the first inverted signal  641 . Wherein, the first inverted signal  641  is the inverse of the first signal  611 , and the first inverted signal  641  operates between the first system voltage VDD 1  and the first ground voltage VSS 1 . Herein, the inverter  640 , for example, is respectively the same as the inverters of the previous embodiments, so it is not described.  
         [0068]     The first end of first switch  680  is connected to the output end of the inverter  640  and receives the first inverted signal  641 . The first end of the second switch  690  receives the first signal  611 . The first switch  680  and the second switch  690  respectively determine the connection status between the first end and second end according to the level of the second system voltage VDD 2 . In other words, when the second system voltage VDD 2  is powered on, both the first switch  680  and the second switch  690  both switched on; on the contrary, when the second system voltage VDD 2  is powered off, both the first switch  680  and the second switch  690  are switched off.  
         [0069]     In the present embodiment, the first switch  680  includes an N transistor  681 . The gate of the transistor  681  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the first switch  680 . The second switch  690  includes an N transistor  691 . The gate of the transistor  691  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the second switch  690 .  
         [0070]     In the present embodiment, the voltage level shifting circuit  650 , for example, includes the P transistors T 1 , T 4  and the N transistors T 2 , T 3 , T 5 , T 6 . The gate of the transistor T 1  is the first input end of the voltage level shifting circuit  650 . The first source/drain (hereinafter “the source”) of the first transistor T 1  is connected to the second system voltage VDD 2 . The gate of the second transistor T 2  is connected to the gate of the transistor T 1 . The first source/drain (hereinafter “the drain”) of the transistor T 2  is connected to the second source/drain (hereinafter “the drain”) of the transistor T 1 . The first source/drain (hereinafter “the drain”) of the transistor T 3  is connected to the second source/drain (hereinafter “the source”) of the transistor T 2 . The second source/drain (hereinafter “the source”) is connected to the second ground voltage VSS 2 . The first source/drain (hereinafter “the source”) of the transistor T 4  is connected to the second system voltage VDD 2 , the second source/drain (hereinafter “the drain”) of the transistor T 4  is connected to the gate of the transistor T 3 . The gate of the transistor T 4  is the second input end of the voltage level shifting circuit  650 . The gate of the transistor T 5  is connected to the gate of the transistor T 4 . The first source/drain (hereinafter “the drain”) of the transistor T 5  is connected to the drain of the transistor T 4 . The gate of the transistor T 6  is connected to the drain of the transistor T 1 . The first source/drain (hereinafter “the drain”) of the transistor T 6  is connected to the source of the transistor T 5 . The second source/drain (hereinafter “the source”) of the transistor T 6  is connected to the second ground voltage VSS 2 . Wherein, the drain signal of the transistor T 5  is the second signal  631 .  
         [0071]     The first connecting end of the first ESD clamp circuit  660  is connected to the second system voltage VDD 2 , the second connecting end of the first ESD clamp circuit  660  is connected to the gates of the transistors T 1  and T 2  simultaneously. In the present embodiment, the ESD clamp circuit  660 , for example, includes a P transistor. Wherein, the drain of the P transistor is connected to the first input end (the gates of the transistors T 1  and T 2 ) of the voltage level shifting circuit  650 . The gate, the source and the bulk of the P transistor are all connected to the second system voltage VDD 2 . Or, as known by those who are skilled in the art, the ESD clamp circuit  660  can also be implemented using diode or other method, and the result thereof is also within the scope of the present invention.  FIG. 6B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 6B , if the ESD clamp circuit  660  is implemented with diode, then the anode of the diode is connected to the first input end of the voltage level shifting circuit  650 , while the cathode of the diode is connected to the second system voltage VDD 2 .  
         [0072]     In the present embodiment, the embodiment of the second ESD clamp circuit  670  is the same with that of the first ESD clamp circuit  660 , therefore here the description is not repeated.  
         [0073]      FIG. 7A  schematically illustrates a circuit diagram of a level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 7A , the level shifter  720  receives the first signal  711  outputting from the internal circuit  710  in IC and outputs the second signal  731  (received by the internal circuit  730  in IC) with the corresponding level according to the level of first signal  711 . Wherein, the first signal  711  operates between the first system voltage VDD 1  (for example, 12 volts) and the first ground voltage VSS 1  (for example, 0 volt). And the second signal  731  operates between the second system voltage VDD 2  (for example, 3.3 volts) and the second ground voltage VSS 2  (for example, 0 volt).  
         [0074]     In the present embodiment, the level shifter  720 , for example, includes the inverter  740 , the voltage level shifting circuit  750 , the ESD clamp circuit  760 , the ESD clamp circuit  770 , the first switch  780  and the second switch  790 . The inverter  740  receives the first signal  711  and outputs the first inverted signal  741 . Wherein, the first inverted signal  741  is the inverse of the first signal  711 , and the first inverted signal  741  operates between the first system voltage VDD 1  and the first ground voltage VSS 1 . Here, since the inverter  740  and the voltage level shifting circuit  750  are respectively the same as the inverter  640  and the voltage level shifting circuit  650  previously described, therefore it is not described.  
         [0075]     The first end of the first switch  780  is connected to the output end of the inverter  740  and receives the first inverted signal  741 . The first end of the second switch  790  receives the first signal  711 . The first switch  780  and the second switch  790  respectively determine the connection status between the first end and second end according to the level of the second system voltage VDD 2 . In other words, when the second system voltage VDD 2  is powered on, both the first switch  780  and the second switch  790  are switched on; on the contrary, when the second system voltage VDD 2  is off, both the first switch  780  and the second switch  790  are switched off.  
         [0076]     In the present embodiment, the first switch  780  includes an N transistor  781 . The gate of the transistor  781  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the first switch  780 . The second switch  790  includes an N transistor  791 . The gate of the transistor  791  is connected to the second system voltage VDD 2 , and its first connecting end and its second connecting end respectively are the first end and the second end of the second switch  790 .  
         [0077]     The first connecting end of the ESD clamp circuit  760  is connected to the gates of the transistors T 1  and T 2  simultaneously, and the second connecting end of the ESD clamp circuit  760  is connected to the second ground voltage VSS 2 . In the present embodiment, the ESD clamp circuit  760 , for example, includes an N transistor. Wherein, the drain of the N transistor is connected to the first input end of the voltage level shifting circuit  750 ; and the gate, the source and the bulk of the N transistor are all connected to the second ground voltage VSS 2 . Or, as known by those who are skilled in the art, the ESD clamp circuit  760  can also be implemented using diode or other method, and the result thereof is also within the scope of the present invention.  FIG. 7B  schematically illustrates a circuit diagram of another level shifter ESD protection circuit according to another embodiment of the present invention. With reference to  FIG. 7B , if the first ESD clamp circuit  760  is implemented with diode, the cathode of the diode is connected to the first input end of the voltage level shifting circuit  750 , while the anode of the diode is connected to the second ground voltage VSS 2 .  
         [0078]     In the present embodiment, since the implementation of the second ESD clamp circuit  770  is similar to that of the first ESD clamp circuit  760 , therefore it is not described again.  
         [0079]     Particularly note that, in the present embodiment, the voltage level shifting circuit  450  in  FIG. 4A  and  FIG. 4B  can be substituted by any voltage level shifting circuits; for example the voltage level shifting circuit  250  in  FIG. 2A , the voltage level shifting circuit  550  in  FIG. 5A , the voltage level shifting circuit  650  in  FIG. 6A  and other voltage level shifting circuits, etc. The results thereof are also within the scope of the present invention.  
         [0080]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.