Abstract:
An adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage, the predistorter including: a predistortion gain block adapted to apply a complex gain to a complex input signal; a first table implemented in a first memory and comprising a 2-dimensional array of cells storing complex gain values, the first table adapted to output the complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and a second table implemented in a second memory and including a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output signal of said power amplifier.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority benefit of French patent application Ser. No. 09/55501, filed on Aug. 5, 2009, entitled “Digital Predistorter For Variable Supply Applications,” which is hereby incorporated by reference to the maximum extent allowable by law. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to a digital predistorter, and to an amplification circuit arrangement comprising a digital predistorter for providing adaptive predistortion at the input of a variable supply power amplifier. 
       BACKGROUND TO THE INVENTION 
       [0003]    Variable supply power amplifiers use envelope tracking to vary the supply voltage based on the amplitude of the input signal, and thereby reduce power consumption. Such amplifiers are, for example, used to amplify an RF signal prior to transmission over a transmission channel. 
         [0004]      FIG. 1  is a graph showing a variable supply voltage V S  and the amplitude AM OUT  of the corresponding RF (radiofrequency) signal at the output of a power amplifier supplied by the variable supply voltage V S . 
         [0005]    The dashed lines in  FIG. 1  illustrate the ideal output signal waveform, and demonstrate the problem of clipping at the signal peaks of the output signal. This problem occurs when the amplitude of the output signal becomes close to the level of the variable supply voltage V S , and the power amplifier thus becomes saturated, distorting the output signal. This distortion is undesirable in many applications such as in wireless communications, where it increases the bandwidth occupied by the transmitted signal. 
         [0006]    It has been proposed to provide an adaptive predistorter that adjusts, in advance, the gain and phase of portions of the input signal before it is amplified by the power amplifier. 
         [0007]    However, a difficulty with such adaptive predistorters is that the gain to be applied depends on several variables, for example on both the level of the input signal and the level of the variable supply voltage. Existing solutions tend to be either complex to implement, or demanding on memory resources and slow to calibrate. 
       SUMMARY OF THE INVENTION 
       [0008]    Embodiments of the present invention aim to at least partially address one or more problems in the prior art. 
         [0009]    According to one aspect of the present invention, there is provided an adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage (V), the predistorter comprising: a predistortion gain block adapted to apply a complex gain to a complex input signal; a first table implemented in a first memory and comprising a 2-dimensional array of cells storing complex gain values, the first table adapted to output said complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and a second table implemented in a second memory and comprising a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output signal of said power amplifier. 
         [0010]    According to one embodiment, the complex gain values in said first table are in Cartesian format, and wherein said gain update values in said second table are complex values also in Cartesian format. 
         [0011]    According to another embodiment, the predistorter further comprises a table update block adapted to generate updated complex gain values based on said complex gain values of the first table and the gain update values of the second table. 
         [0012]    According to another embodiment, the table update block is adapted to update the complex gain values based on the following calculation for each address in the first table: G′ x,y =G x,y ·G 2x,y  where G′ x,y  is the new complex gain value corresponding to address x,y of the first table, G x,y  is the previous complex gain value at address x,y of the first table and G 2x,y  is the gain update value at address x,y of the second table. 
         [0013]    According to another embodiment, the predistorter further comprises a feedback control block adapted to generate said gain update values based on the complex input signal, the output signal of said power amplifier and a previous gain update value stored in said second table. 
         [0014]    According to another embodiment, a first order IIR (infinite impulse response) filtering function is applied when generating said gain update values, based on the following calculation: G 2 ′ x,y =G 2x,y +(G 2x,y −m)α wherein G 2 ′ x,y  is a new gain update value to be stored at address x,y in the second table, G 2x,y  is the previous gain update value at address x,y in the second table, m is a gain ratio equal to the complex input signal divided by the output signal of the power amplifier, and α is a constant. 
         [0015]    According to another embodiment, the first and second tables are each addressed by a column address based on the variable supply voltage and a row address, wherein the row address of the first table is based on the amplitude of the complex input signal and the row address of the second table is based on the amplitude of the output signal of the power amplifier. 
         [0016]    According to another embodiment, the row address input to the first table is equal to: (AM IN [n]/V S [n]), and the row address input to the second table is equal to: (AM OUT  [n]/V S [n]), 
         [0000]    wherein AM IN [n] is the amplitude of the complex input signal and AM OUT [n] is the amplitude of the complex output signal of the power amplifier converted into digital format and V S [n] is the variable supply voltage converted into digital format. 
         [0017]    According to another embodiment, the row address input to the first table is equal to: (AM IN [n]/V S [n]) 2 , and the row address input to the second table is equal to: (AM OUT [n]/V S [n]) 2 , wherein AM IN [n] is the amplitude of the complex input signal and AM OUT [n] is the amplitude of the complex output signal of the power amplifier converted into digital format and V S [n] is the variable supply voltage converted into digital format. 
         [0018]    According to another embodiment, the roles of the first and second tables are exchanged periodically. 
         [0019]    According to another aspect of the present invention, there is provided an amplification circuit arrangement comprising: the above predistorter for applying a predistortion gain to an input signal; a first RF converter for converting the predistorted input signal to an analog signal at a transmission frequency; and a power amplifier for amplifying the analog signal, the power amplifier being powered by a variable supply voltage. 
         [0020]    According to yet a further aspect of the present invention, there is provided an electronic device comprising: modulation circuitry for generating the complex input signal; and the above amplification circuit arrangement. 
         [0021]    According to yet a further aspect of the present invention, there is provided a method of applying a predistortion gain to a complex input signal to be amplified by a power amplifier having a variable supply voltage, comprising: applying to the complex input signal, by a predistortion gain block, complex gain values extracted from a first table comprising a 2-dimensional array of cells storing complex gain values, said complex gain values being extracted based on an amplitude of the complex input signal, and a value of the variable supply voltage of the power amplifier; and accumulating in a 2-dimensional array of a second table gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output signal of said power amplifier. 
         [0022]    According to one embodiment, the method further comprises periodically switching the roles of said first and second tables such that said first table is used for accumulating a 2-dimensional array of gain update values generated based on an output signal of said power amplifier, and the second table is used for providing said complex gain values. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    The foregoing and other purposes, features, aspects and advantages of the invention will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which: 
           [0024]      FIG. 1  (described above) shows a graph of the amplitude of an output signal from a power amplifier and a corresponding variable supply voltage according to one example; 
           [0025]      FIG. 2  illustrates an amplification circuit according to an embodiment of the present invention; 
           [0026]      FIG. 3  illustrates the amplification circuit of  FIG. 2  in more detail; 
           [0027]      FIG. 4  illustrates the amplification circuit of  FIG. 2  in yet more detail; 
           [0028]      FIG. 5  illustrates an alternative arrangement of look-up tables of the amplification circuit of  FIG. 3 ; and 
           [0029]      FIG. 6  illustrates an electronic device according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]      FIG. 2  illustrates an amplification circuit  200  comprising a digital predistorter (DPD)  202  and a power amplifier (PA)  204 . The power amplifier  204  is powered by a variable supply voltage V S , which is varied (by circuitry not shown in  FIG. 2 ) using envelope tracking based on the level of an input modulation signal IQ IN . The predistorter  202  receives, on an input line  206 , the input modulation signal IQ IN , prior to frequency translation and, on an input line  208 , the variable supply voltage V S.    
         [0031]    Predistorter  202  determines, using a 2D look-up table T 1  of complex gains in Cartesian format (i+jq), and based on the amplitude of the input signal IQ IN  and the level of the variable supply voltage V S , the complex predistortion gain to be applied to the input signal. This gain is applied to the input signal IQ IN  to generate a predistorted signal IQ PD , which is provided to the input of an RF UP block  209 . RF UP block  209  up converts the signal IQ PD  to an RF signal RF PD  at a desired transmission frequency, which is provided to the input of the power amplifier  204 . The power amplifier  204  amplifies this signal to generate an RF output signal RF OUT  on an output line  210  for transmission over a transmission channel (not shown in  FIG. 2 ). 
         [0032]    The output signal RF OUT  is also provided to an RF DOWN block  212 , which down converts the RF signal to a baseband signal IQ OUT , which is provided on a feedback line  214  to the predistorter  202 . 
         [0033]    A table T 1  is used to provide predistortion gain values, and a table T 2  is used to store gain update values determined using the output signal IQ OUT  from the RF DOWN block  212 . Periodically, the gain update values accumulated in table T 2  are used to update the gain values in table T 1 . The tables T 1  and T 2  are, for example, implemented in respective memory arrays having the same dimensions as each other. 
         [0034]      FIG. 3  illustrates the amplification circuit  200  in more detail according to one embodiment. In addition to the look-up tables T 1  and T 2 , the digital predistorter  202  comprises a predistortion gain block (PDG)  302 , a feedback control block (FCB)  304 , and a table update block (TUB)  306 . 
         [0035]    The predistortion gain block  302  applies, to digital input modulation signal values IQ IN [n] received on input line  206 , complex gain values G retrieved from look-up table T 1 . The gain values G from table T 1  are selected according to an amplitude value AM IN [n] of the input signal and the level V S [n] of the variable supply voltage. 
         [0036]    Table T 1  comprises a 2D memory array, wherein each column for example corresponds to a different supply voltage value and each row corresponds to a different input signal amplitude value. The memory array comprises, for each combination of the supply voltage and input signal amplitude values, a corresponding complex gain value G in Cartesian format. In one example, the array comprises 8 columns corresponding to 8 different supply voltage values, and 16 rows corresponding to 16 different input signal amplitude values, although in alternative embodiments there could be between 2 and several hundred columns and between 2 and several hundred rows. Obviously, the columns and rows could be switched such that the columns correspond to input signal amplitude values and the rows to the supply voltage values. 
         [0037]    The table T 1  is addressed by digital words x 1 [n], y 1 [n], which are functions of the supply voltage values V S [n], for example provided by a supply voltage controller (not shown in  FIG. 3 ), and the digital input signal amplitude samples AM IN [n], based on the amplitude of the input signal values. In one example, x 1 [n]=V S [n] and y 1 [n]=AM IN [n]=|IQ IN [n]|, where |IQ IN [n]| is the modulus of the complex value of the input signal IQ IN [n]. Alternatively, as will be explained below, other functions may be applied to the amplitude of the input signal to generate the signal y 1 [n]. 
         [0038]    Each of the digital values x 1 [n] and y 1 [n], for example, comprises a number of bits corresponding to the number of corresponding columns and rows in the table T 1  respectively. Assuming there are 8 columns corresponding to supply voltage levels, the values x 1 [n], and for example also the values V S [n], are 3 bits, and assuming there are 16 rows corresponding to the input amplitude, the values y 1 [n], and for example also the values AM IN [n], are 4 bits. This leads to a simple mapping between the address of the table T 1  and the variables AM IN [n] and V S [n]. 
         [0039]    The table T 2  is the same as table T 1 , except that in this example, rather than the address values of the second table being based on the input signal amplitude values AM IN [n] and the supply voltage values V S [n], they are based on output signal amplitude values AM OUT [n] sampled from the output signal RF OUT , and the supply voltage values V S [n]. Thus the gain update values in table T 2  correspond to the reciprocals of the power amplifier gain. During generation of the gain update values in table T 2 , temporary values “G 2 ” are stored in the table. These values are modified iteratively, before being used to update the gain values G in table T 1 . 
         [0040]    Rather than being directly equal to the amplitudes of the input and output signals AM IN [n] and AM OUT [n], the values X 1 [n], y 1 [n] used to address table T 1  and the values x 2 [n], y 2 [n] used to address table T 2  could be determined based on more complex function of these signals, taking into account the properties of these signals and of the power amplifier. For example, for an envelope tracking power amplifier with a signal modulated by QPSK, addressing could be based on the drive signal to supply ratio, equal to the amplitude of the input and output signals divided by the supply voltage. In other words, the tables could be addressed by {V S [n],backoff[n]}, where, in the case of table T 1 : 
         [0000]        y   1   [n ]=backoff IN   [n]=AM   IN   [n]/V   S   [n] , and in the case of table  T 2: 
         [0000]        y   2   [n ]=backoff OUT   [n]=AM   OUT   [n]/V   S   [n].    
         [0041]    In this example, the division by V S [n] is relatively simple, as V S [n] varies slowly and has few possible values. Other functions are possible, such as: 
         [0000]        y   1   [n]=AM   IN   [n]   2   /V   S   [n]   2 , and 
         [0000]    
       
      
       y 
       2 
       [n]=AM 
       OUT 
       [n] 
       2 
       /V 
       S 
       [n] 
       2  
      
     
         [0042]    Advantageously, by selecting an appropriate function based on the characteristics of the signals, the samples will not be concentrated within a small region of the table, but be relatively evenly dispersed throughout the table, meaning that a small table can provide high precision. Interpolation of the input ranges could also be performed to increase linearity even more. It will be apparent to those skilled in the art that there is a trade-off between complexity of the function applied to the input variables, and the size of the table. 
         [0043]    The feedback control block  304  receives the digital input values IQ IN [n] and the digital output values IQ OUT [n], and based on these values, calculates corresponding gain update values G 2  in table T 2 . In particular, on each cycle, block  304  generates an output amplitude value AM OUT [n] based on the digital output value IQ OUT [n], and provides this value to table T 2 . Table T 2  also receives the current supply voltage value V S [n], and outputs the gain update value G 2  from the corresponding address to block  304 . Block  304  then generates the new value G 2 ′ based on the values of IQ IN [n], IQ OUT [n] and G 2 , and writes this value to the same address in table T 2 . 
         [0044]    The table update block  306  periodically updates the gain values G in table T 1  based on the gain update values in table T 2 . For this, each previous gain value G from table T 1  and corresponding gain update value G 2  from table T 2  are provided in turn to block  306 , which generates a new gain value G′ to replace the existing value G in table T 1 . 
         [0045]    In some embodiments, the updating of table T 1  can be performed in parallel to the continuing functioning of the predistortion gain block  302 . Alternatively, table T 1  can be updated periodically at times when there is no input signal, such as between two transmission time slots, or during a synchronization phase. 
         [0046]      FIG. 4  illustrates an example of the structure of the amplification circuit  200  in yet more detail. 
         [0047]    The predistortion gain block  302  comprises a multiplier  402 , which multiplies the complex digital input signal IQ IN [n] by a corresponding complex gain value G provided by table T 1  to provide the complex digital predistorted signal IQ PD [n]. This signal is provided to the RF UP block  209 , which comprises a DAC (digital to analog converter)  403 , which converts the digital signal IQ PD [n] to an analog signal, and a mixer  404 , which frequency shifts the analog signal to provide the signal RF PD  at the desired transmission frequency. 
         [0048]    The input and output signals IQ IN  and IQ OUT  are complex values represented in the Cartesian form “i+jq”. The predistortion gain block  302  and feedback control block  304  comprise respective amplitude extraction blocks  405 ,  406 . Block  405  determines the amplitude |AM IN [n]| as √{square root over ((i IN   2 +q IN   2 ))}, where i IN  and q IN  are the real and imaginary parts respectively of IQ IN [n], and block  406  determines the amplitude |AM OUT [n]| as √{square root over ((i OUT   2 +q OUT   2 ))}, where i OUT  and q OUT  are the real and imaginary parts respectively of IQ OUT [n]. In the case that the tables T 1  and T 2  are addressed directly by the amplitudes AM IN [n] and AM OUT [n], these amplitudes are output as the signals y 1 [n] and y 2 [n] to tables T 1  and T 2  respectively. Alternatively, in the case that an alternative function of the amplitudes is used as described above, the amplitude extraction blocks  405  and  406  for example also apply this function. 
         [0049]    The variable supply voltage values V S [n] provided to tables T 1  and T 2  are for example generated by sampling the supply voltage V S  by an ADC  407 . Alternatively, as mentioned above, they could be provided directly by a supply control block (not shown in  FIG. 4 ). 
         [0050]    The RF DOWN block  212  comprises a mixer  410 , which receives the output signal RF OUT  of the power amplifier  204  on line  210  and down converts this signal from the radio frequency to the baseband, and an ADC  412 , which samples the baseband RF signal to provide the digital values IQ OUT [n]. The input signal IQ IN [n] is also provided to the FCB  304 . The signals IQ IN [n] and IQ OUT [n] for example comprise samples of 10 bits at a rate of 30 MHz for each of the real and imaginary components. Alternatively, the input signal may be provided to the FCB in analog form, and sampled by a further ADC (not shown in  FIG. 4 ) to provide the digital signal. Furthermore, either or both of the signals IQ IN [n] and IQ OUT [n] may be sampled by further sampling circuitry to adapt the sampling rate to the rate used by the FCB  304 . 
         [0051]    The FCB  304  comprises a division unit  416 , which divides the input signal IQ IN [n] by the output signal IQ OUT [n] to generate a complex gain ratio m, which is a gain correction inverted with respect to the gain applied by both the amplification circuits  302  and  204 . The FCB  304  also comprises an iterative update module  420 , which updates values in table T 2 . In particular, module  420  receives the complex gain ratios m from the division unit  416 , for example in 10 bits, as well as a current value G 2  from table T 2 , addressed based on the current address inputs V S [n] and AM OUT [n]. While other types of filters could be implemented, in the present example the module  420  implements a first order IIR (infinite impulse response) filter to generate each new value G 2 ′ to replace the old value G 2 , for example using the following calculation: 
         [0000]        G   2 ′ x,y   =G   2x,y +( G   2x,y   −m )α
 
         [0000]    where x corresponds to the column address, determined based on the supply voltage value V S [n], y corresponds to the row address determined based on the output signal amplitude value AM OUT [n], and α is a value chosen based on the desired filtering of the gain measurement and the rate of convergence of the algorithm. The value α is for example a constant value equal to between 1/32 and ½, and is for example a power of 2 allowing simplified implementation. Assuming a value of α of 1/X, every cell of the table T 2  is for example updated around 2X times in order to obtain an optimal value of G 2 , with around 10% precision. In practise, some cells of the tables will be updated more often than others, and these cells will converge more rapidly to precise estimations of the gain corrections, while cells that are updated more rarely may have a reduced precision, but will equally have lower impact on the global precision of the correction circuitry. 
         [0052]    Alternatively, the value of α could be variable, for example, being selected at the start of each learning phase during which the gain update values are accumulated, based on the desired time period before the next gain update. This may, for example, depend on the type of signal being processed. 
         [0053]    At the start of each new learning phase, the gain update values G 2x,y  throughout the table T 2  that have already been applied are for example re-initialized to a neutral gain of 1. 
         [0054]    The table update circuitry  306  comprises a multiplier  418 , which receives the values at the same address from each of the tables T 1  and T 2  in turn, and multiplies these values together in order to provide an updated complex gain value G′, which is stored in table T 1 . In other words, the update is based on the following calculation: 
         [0000]    
       
      
       G′ 
       x,y 
       =G 
       x,y 
       ·G 
       2x,y  
      
     
         [0000]    where x and y are the column and row addresses respectively, G′ x,y  is a new value to be stored at address x,y of table T 1 , G x,y  is the previous value stored at address x,y of table T 1 , and G 2x,y  is the gain update value stored at address x,y of table T 2 . 
         [0055]    In the embodiment of  FIG. 4 , table T 1  is dedicated to being used as the look-up table for providing the complex gain values G, while table T 2  is used for accumulating the complex gain update values G 2  used to periodically update the complex gain values of table T 1 . In alternative embodiments, the roles of the tables T 1  and T 2  may switched periodically, making the table updating process even more seamless, as will now be described in relation to  FIG. 5 . 
         [0056]      FIG. 5  illustrates the connections to the tables T 1  and T 2  and multiplier  402  according to an embodiment in which multiplexers are used to periodically switch the roles of the tables. 
         [0057]    Multiplier  402  receives the complex gain value G from the output of a multiplexer  502 , which comprises two inputs coupled to outputs of the tables T 1  and T 2  respectively. These outputs of tables T 1  and T 2  are also coupled to respective inputs of a multiplexer  503 , which has its output coupled to the iterative update module  420  of  FIG. 4  and provides the previous gain values G 2 . 
         [0058]    Each of the tables T 1  and T 2  has an input coupled to respective outputs of a multiplexer  504 , which has an input coupled to receive updated gain values G 2 ′ from the output of the iterative update module  420 . Two multiplexers  506  and  508  each comprises one input coupled to receive the digital amplitude values AM IN [n], and another input coupled to receive the digital amplitude values AM OUT [n]. The output of multiplexer  506  is coupled as an address input to table T 1 , while the output of multiplexer  508  is coupled as an address input to table T 2 . As previously, the digital variable supply voltage value V S [n] is coupled to a further address input of each of tables T 1  and T 2 . A multiplexer  510  has an input coupled to the output of multiplier  418 , and has two outputs, one of which is coupled to a data input of each of the tables T 1  and T 2 . 
         [0059]    The multiplexers  502  and  506  are controlled by a digital timing signal θ, while the multiplexers  503 ,  504 ,  508  and  510  are controlled by a digital timing signal φ. The timing signal θ is for example the inverse of the timing signal φ, such that when the timing signal θ is high, the timing signal φ is low, and vice versa. 
         [0060]    Each of the tables T 1  and T 2  is, for example, a dual port memory, such as a dual port RAM (DPRAM), allowing two of its cells to be accessed in a same read or write cycle. Thus secondary address inputs  512  and  514  are, for example, provided in tables T 1  and T 2  respectively, allowing secondary addresses a,b from the tables to be read and provided to the multiplier  418 . As an alternative, the tables T 1  and T 2  could be operated at twice the data rate of the signal samples, for example at 60 MHz if the signal samples are at a rate of 30 MHz, such that two accesses may occur, in which case no secondary address inputs  512 ,  514  need be provided. 
         [0061]    In operation, assuming that signal θ is initially at logic level “0”, and signal φ at logic level “1”, table T 1  is initially used to provide complex gain values G to multiplier  402 , and table T 2  is used to accumulate gain update values G 2 . When the complex gain update values G 2  in table T 2  are to be used to update the complex gain values G in table T 1 , the secondary address inputs  512  and  514  are for example used to output the old complex gain values G from table T 1  and corresponding gain update values G 2  from table T 2 . The results are stored in the corresponding locations in table T 2 . Alternatively, in that case that the secondary address inputs  512  and  514  are not provided and the tables are sampled at twice the rate of the signal samples, the normal address inputs of tables T 1  and T 2  are, for example, used on every other cycle to address the values G x,y  and G 2x,y  to be used for the update. 
         [0062]    Once all of the G 2  values in table T 2  have been replaced by the updated gain values G′, the roles of the tables can be switched. Thus signal θ is switched to logic level “1”, and signal φ is switched to logic level “0”, such that table T 2  is used to provide complex gain values G to multiplier  402 , and table T 1  is used to accumulate gain update values. The above operation then repeats, until the roles of the tables are ready to be switched again. 
         [0063]      FIG. 6  illustrates an electronic device  600 , which is, for example, a mobile telephone, set top box, ADSL router, network adapter or other electronic device having a power amplifier with predistortion. For example, such a device could be used in UMTS (Universal Mobile Telecommunications System), GSM (Global System for Mobile communications), or Bluetooth application. 
         [0064]    Device  600  comprises a signal modulator  602 , which generates a baseband signal for radio transmission based on information from a data source that is to be transmitted, which, for example, comprises digital data, sound or sensor information. The signal provided by the signal modulator  602  is in Cartesian format, having a real component I IN  and imaginary component Q IN . This signal is provided to a power amplifier  604 , which, for example, comprises the circuitry of any of  FIGS. 2 to 5 . The power amplifier  604  applies predistortion, RF up-conversion and power amplification to the input signal to provide an output RF signal RF OUT  The output RF signal is coupled to amplification circuit  606 , which for example comprises filtering and impedance matching networks. The signal is then transmitted over a transmission channel, for example, via an output antenna  608 , although in alternative embodiments the transmission channel could be a wired channel. 
         [0065]    The power amplifier  604  has its power supply voltage V S  modulated by a supply modulator  610 , based on the digital supply signal V S  [n] provided by the signal modulator  602 . In some embodiments, this signal may also be provided directly to the power amplifier  604 , to provide the digital values V S  [n] of the supply voltage. 
         [0066]    An advantage of the embodiments of the predistorter described herein is that, by using two tables, one for providing complex gains for predistortion, and the other for accumulating gain update values, the predistorter has low complexity and low memory requirements. 
         [0067]    Furthermore, by providing tables containing complex gains in Cartesian format, these gains may be applied to the input modulation signal Q IN  by a simple multiplication operation. 
         [0068]    Furthermore, by preparing the gain update values through accumulation of gain measurements in a separate table to the one used for providing the gain values used by the predistorter, measurement errors are filtered during the update procedure in a simple fashion. Complex operations occur only in reduced number at the end of the learning phase, and as they do not need to be performed in real time, they can be handled by a general purpose DSP (digital signal processor). 
         [0069]    Furthermore, as described herein, one table is addressed based on the amplitude AM IN [n] of the input signal, while the other table is address based on the amplitude AM OUT [n] of the output signal, and the gain update values are calculated based on IQ IN [n]/IQ OUT [n], which is the reciprocal of the gain applied to the input signal by the amplification circuit. Alternatively, the table update values could be calculated based on IQ OUT [n]/IQ IN [n]. Furthermore, in some embodiments, the tables are addressed based on the supply to drive ratio, or the supply to drive ratio squared, and this allows the table sizes to be further reduced and/or accuracy to be improved. 
         [0070]    A further advantage of embodiments of the present invention is that the tables may be arranged such that their roles switch periodically, thereby facilitating the updating of the predistortion values, without disrupting the processing of the input signal. 
         [0071]    While a number of particular embodiments of the present invention have been described in detail, it will be apparent to those skilled in the art that there are many modifications that may be applied. 
         [0072]    In particular, it will be apparent to those skilled in the art that there are implementation variations. For example, different algorithms could be used for calculating the gain update values and the complex gain values. Furthermore, parameters such as the number of bits of each input signal are given by way of example only, other values being possible. 
         [0073]    Furthermore, as will be apparent to those skilled in the art, the terms “column” and “row” could be applied to either dimension of a memory array, and the tables could be implemented in two or more memory devices. 
         [0074]    It will also be apparent to those skilled in the art that further pairs of tables T 1 , T 2  could be provided, allowing different operation based on difference conditions of the input signal. For example, one pair of tables could apply to a first frequency range of the transmitted signal, and a second pair of tables could apply to a second frequency range of the transmitted signal, and the appropriate pair of tables could be selected by detecting the frequency range of the transmitted signal.