Abstract:
This invention provides a compiler, circuits and a method for generating a flash memory for integrated circuits. This invention provides a flash memory compiler which can generate flexible configurations which are a function of the flash memory array bit count. In addition, this flash compiler of this invention has the ability to optimize the resultant flash memories so as to produce the correct amount of flash array current driving capability and minimal wasting of power dissipation as a function of the flash memory array size.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to a compiler, circuits and a method for generating a flash memory for integrated circuits. 
   More particularly this invention relates to providing a flash memory compiler which can generate flexible configurations which are a function of the flash memory array bit count. In addition, this invention relates to the ability of a flash compiler to optimize the resultant flash memories so as to produce the correct amount of flash array current driving capability and minimal wasting of power dissipation. 
   2. Description of Related Art 
     FIG. 1  shows a prior art charge pumping circuit. There are thirteen stages of an identical charge pumping circuit macro  120 . Each stage  120  has an input  110  and an output  125 . The output  125  of one stage  120  feeds the input of the next stage  130 . The logical input to the first stage is the Enable signal  110 . This signal starts the charge pumping process. The output of the thirteenth and final stage  140  is the High Voltage signal, HV  150 . The significant feature of the charge pumping circuit of  FIG. 1  is that each stage contains the same pumping circuit with identical capacitance independent of flash array bit count or IO count. 
   U.S. Pat. No. 5,568,424 (Cernea, et al.) “Programmable Power Generation Circuit for Flash EEPROM Memory Systems” describes a voltage and power circuit to drive a variety of flash memory systems. These flash memories include those on the same chip and those off-chip. 
   U.S. Pat. No. 5,693,570 (Cernea, et al.) “Process for Manufacturing a Programmable Power Generation Circuit for Flash EEPROM Memory Systems” describes a process for making a variety of voltage and power generating circuits for various sizes and types of flash memories. 
   U.S. Pat. No. 5,693,570 (Cernea et al.) “Programmable Power Generation Circuit for Flash EEPROM Memory Systems” discloses a circuit for on-chip generation of voltage and power for flash memories. 
   BRIEF SUMMARY OF THE INVENTION 
   It is the objective of this invention to provide a compiler, circuits and a method for generating a flash memory for integrated circuits. 
   It is further an object of this invention to provide a flash memory compiler which can generate flexible configurations which are a function of the flash memory array bit count. 
   It is further an object of this invention to provide the ability of a flash compiler to optimize the resultant flash memories so as to produce the correct amount of flash array current driving capability and minimal wasting of power dissipation. 
   The objects of this invention are achieved by a flash compiler with flexible configurations. This compiler produces a floor plan with three portions, top, middle, and bottom. The flash compiler&#39;s top portion contains array related leafcell layout which could be increased in both x &amp; y directions, source line drivers, and X-decode circuits. The flash compiler&#39;s middle portion contains X-precoder circuits, sense amplifier, IO MUX, and data in/data out buffer circuits which are increased in the x-direction. The flash compiler&#39;s bottom portion is 1 leafcell, containing HV block, reference block which contains reference voltages and currents, and test mode circuits. The flash compiler&#39;s bottom portion is designed with different number of columns to match the width of said top and said middle portion. The flash compiler&#39;s HV block in the bottom portion is made up of charge pump circuitry. 
   The charge pump circuitry is made up of N serially-connected stages of a basic charge pump circuit macro where N is typically 13 to produce voltages around 13 volts which is required to program and erase flash memories. The primary logic input to the first stage of the serial string of 13 stages is connected to an Enable signal. The primary logical output of the 13th and last stage is a HV or high voltage signal. The charge pump circuit macro is a pumping circuit which has a total internal circuit capacitance proportional to the number of IO in the flash array. The charge pump circuit macro contains two clock inputs. The charge pump circuit macros  1  through  13  contain two clock outputs which feed said two clock inputs of the subsequent charge pump stage. The logic outputs from one stage feed the logic inputs of the next stage. 
   The clock input  1  feeds two serially connected inverters. The clock input  2  feeds two serially connected inverters. The output of the two serially connected inverters is the charge pump circuit macro clock output  1 . The output of the two serially connected inverters is the charge pump circuit macro clock output  2 . Clock output  1  is connected to a capacitor C 1 . Clock output  2  is connected to a capacitor C 2 . Capacitor C 1  has its second side connected to the drain of an n-channel metal oxide semiconductor field effect transistor, NMOS, FET  1 , and connected to the gate of another NMOS FET  2 . Capacitor C 2  has its second side connected to the drain of said NMOS FET  2  and connected to the gate of NMOS FET  1 . The sources of the NMOS FETs  1  and  2  are connected in common, to a charge pump circuit primary macro logic input. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a prior art string of charge pumping circuits. 
       FIG. 2  shows a string of charge pumping circuits of this invention. 
       FIG. 3  shows the circuit detail of a single stage from the charging pumping string of circuits prior art string of charge pumping circuits. 
       FIG. 4  illustrates a high level diagram of the floor plan of the flash memory circuit produced by the compiler of this invention. 
       FIG. 5   a  gives a plot of current driving capability versus bit count for the prior art traditional design. 
       FIG. 5   b  gives a plot of current driving capability versus bit count for the circuit of this invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2  shows the charge pumping circuit which is the main embodiment of this invention. There are N stages of an identical charge pumping circuit macro  120 , where N is typically 13 to allow the output voltage, HV to attain a value of around 13 volts which is required for programming and erasing flash memories. Each stage  220  has an input  210  and an output  225 . The output  225  of one stage  220  feeds the input of the next stage  230 . The logical input to the first stage is the Enable signal  210 . This signal starts the charge pumping process. The output of the thirteenth or Nth-final stage  240  is the High Voltage signal, HV  250 . The significant feature of the charge pumping circuit of  FIG. 2  is that each stage  1 – 13  e.g.  220 ,  230 ,  240  contains the same pumping circuit whose capacitances (total capacitances of internal capacitors in the charge pumping circuit) are proportional to the IO count or bit count of the flash memory. 
     FIG. 3  shows one of the above charge pumping circuit stages. This circuit Stage is a main embodiment of this invention. This circuit stage has two clock signals, CK_ 1  ( 310 ) and CK_ 2  ( 320 ) which come from the previous stage. These two clock signals  310 ,  320  form a four-phase clocking system to operate the N-stage series of charge pumping circuits. 
   In addition, the circuit of  FIG. 3  has a logical input, IN,  335  which also comes from the previous stage. The Enable primary input signal is the logical input  335  for the first stage charge pumping circuit. 
   The CK_ 1  clock signal  310  goes into the first of two inverters  340 . The output  345  of the first inverter  340  goes into the second inverter  350 . The output of the second inverter  355  goes to the corresponding CK_ 1  of the next stage. This second inverter output  355  also goes to one side of a capacitor C 1  ( 360 ). The other side of capacitor C 1  ( 360 ) goes to the drain of an N-channel metal oxide semiconductor field effect transistor, NMOS FET  315 . It also goes to the gate of a second NMOS FET  325 . 
   The CK_ 2  clock signal  320  goes into the first of two inverters  370 . The output  375  of the first inverter  370  goes into the second inverter  380 . The output of the second inverter  385  goes to the corresponding CK_ 2  of the next stage. This second inverter output  385  also goes to one side of a capacitor C 2  ( 390 ). The other side of capacitor C 2  ( 390 ) goes to the drain of an N-channel metal oxide semiconductor field effect transistor, NMOS FET  325 . It also goes to the gate of a second NMOS FET  315 . 
   The sources of both NMOS FETs  315  and  325  are tied in common and are attached to the logical input signal  335 . Node  330  as shown in  FIG. 3  is the logical output signal of the charge pumping stage. It feeds the corresponding logical input of the next stage. 
   The current produced by a single charge pump circuit stage of  FIG. 3  can be calculated as follows.
 
 I=C ( dV/dt )
 
 I=C ( V/t )
 
where C is the capacitance C 1  ( 360 ) or C 2  ( 390 ) in  FIG. 3 , V is the voltage change across C and t is the time duration of the voltage change above. Also, the frequency, f, of the four-phase clocking system can be calculated as follows.
 
 I=C ( V/t )
 
 I=CVf  
 
 F=I /( CV )
 
     FIG. 4  shows the overall high-level block diagram of the flash memory produced by the compiler of this invention. The bit line precharge circuit is shown  440 . Next, the top portion  410  of the flash circuit contains the XDEC, x-decode circuit  450 , the main flash memory array  460  and the SHVDR source line drivers  470 . The middle portion  420  of the flash circuit contains the XPDEC, X-precoder circuit  480 , the sense amplifier, SA, the IO multiplexor, IOMUX, the array bus  490 , and data in/data out buffer circuits. 
   The bottom portion  430  contains the reference block (voltage and current references) and test mode circuitry  475 . It also contains the High Voltage block  485  which contains the charge pumping stages previously illustrated in  FIGS. 2 and 3  and described above. 
     FIG. 5   a  shows a plot of charge pump current output or driving capability  510  as a function of flash memory bit count (IO number)  520 . Graph  530  shows a constant current  510  being delivered independent of the flash memory bit count or IO number  520 . Graph  530  represents the typical case for 8 or 16 IO in the flash array. Similarly, graph  540  shows a charge pump current flow which was designed for higher current or more drive capability. Graph  540  represents the typical case for 32 IO in the flash array. Again, graph  540  is independent of bit count  520 . 
     FIG. 5   b  shows the charge pump performance graph of this invention  570 . It also is a plot of charge pump driving capability  550  versus bit count or IO number  560 . It illustrates the main advantage of this invention over the prior art. The current output or charge pump driving capability  550  varies directly  570  as the bit count or IO count  560 . This design is more efficient in the use of power and power dissipation. 
   The advantage of this invention is the flexible design of the basic charge pump circuit. This circuit&#39;s capacitance values are chosen to match closely the current drive requirements, which are dictated by the number of bits in the flash memory array. Referring to  FIG. 3 , the total internal circuit capacitance. i.e., the total capacitance of capacitor C 1  ( 360 ) and capacitor C 2  ( 390 ) of the basic charge pump circuit shown in  FIG. 3 , is dictated by and proportional to, the total number of bits in the flash memory array, thereby providing a flexible design. Since the charge pump circuitry&#39;s drive capability is designed to be directly proportional to the number of bits or IO cells in the array, the compiler of this invention produces an efficient flash memory circuit with lowest power and maximum performance. 
   While this invention has been particularly shown and described with Reference to the preferred embodiments thereof, it will be understood by those Skilled in the art that various changes in form and details may be made without Departing from the spirit and scope of this invention.