Abstract:
A nonvolatile semiconductor memory device comprises a memory cell array of plural memory cells arranged in matrix. Each memory cell includes a first gate insulator layer formed on a semiconductor substrate, a floating gate formed on the semiconductor substrate with the first gate insulator layer interposed therebetween, a second gate insulator layer formed on the floating gate, and a control gate formed on the floating gate with the second gate insulator layer interposed therebetween. The first gate insulator layer is a first cavity layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-300776, filed on Nov. 20, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    An electrically erasable programmable flash memory is known as a nonvolatile semiconductor memory. The flash memory comprises memory cells each usually including a MOS transistor of the stacked gate structure, which includes a floating gate serving as a charge storage layer and a control gate stacked thereon. A tunnel oxide is formed between the floating gate and the semiconductor substrate. 
         [0003]    In the flash memory using such the memory cells, at the time of data write, the semiconductor substrate is grounded and a write voltage is applied to the control gate. As a result, a tunnel current flows via the tunnel oxide between the semiconductor substrate and the floating gate to store electrons in the floating gate. Thus, the memory cell is brought into a written state with a higher threshold. On the other hand, at the time of data erase, the control gate is grounded and the voltage on the silicon substrate is elevated up to an erase voltage. Thus, electrons in the floating gate are drawn therefrom to the semiconductor substrate. As a result, the memory cell is brought into an erased state with a lower threshold. 
         [0004]    In the flash memory of the above-described memory cell structure, however, the tunnel oxide accumulates charge traps at every data rewrite and limits the number of rewrite operations to around 10 5  as a problem. (“Simulation for Degradation of Flash Memory due to Charge Traps in the Tunnel Oxide”, Yokozawa et. al, Technical Report of the Institute of Electronics, Information and Communication Engineers, vol. 96, No. 63(19960523), pp. 17-24). 
       SUMMARY OF THE INVENTION 
       [0005]    In an aspect the present invention provides a nonvolatile semiconductor memory device, comprising a memory cell array of plural memory cells arranged in matrix, each memory cell including a first gate insulator layer formed on a semiconductor substrate, a floating gate formed on the semiconductor substrate with the first gate insulator layer interposed therebetween, a second gate insulator layer formed on the floating gate, and a control gate formed on the floating gate with the second gate insulator layer interposed therebetween, wherein the first gate insulator layer is a first cavity layer. 
         [0006]    In another aspect the present invention provides a method of manufacturing nonvolatile semiconductor memory devices, comprising: forming a first gate insulator layer on a semiconductor substrate; forming a first gate layer turned into a floating gate on the first gate insulator layer; selectively removing the first gate layer and the first gate insulator layer to form a plurality of first isolation trenches extending in parallel with a first direction in the surface layer of the semiconductor substrate; forming a first support film to couple the side of the first isolation trench with the side of the first gate layer facing the first isolation trench, the first support film having a resistance to a first etchant; forming a second gate insulator layer on the first gate layer; forming a second gate layer turned into a control gate on the second gate insulator layer; forming a plurality of second isolation trenches extending in parallel with a second direction crossing the first direction, the second isolation trenches reaching from the second gate layer to the surface of the semiconductor substrate; and forming a first cavity layer between the semiconductor substrate and the first gate layer using the first etchant to remove the first gate insulator layer while leaving the first support film. 
         [0007]    In yet another aspect the present invention provides a method of manufacturing nonvolatile semiconductor memory devices, comprising: forming a first gate insulator layer on a semiconductor substrate; forming a first gate layer turned into a floating gate on the first gate insulator layer; selectively removing the first gate layer and the first gate insulator layer to form a plurality of first isolation trenches extending in parallel with a first direction in the surface layer of the semiconductor substrate; forming a first support film to couple the side of the first isolation trench with the side of the first gate layer facing the first isolation trench, the first support film having a resistance to a first etchant; forming a second gate insulator layer on the first gate layer; forming a second gate layer turned into a control gate on the second gate insulator layer; forming a plurality of second isolation trenches extending in parallel with a second direction crossing the first direction, the second isolation trenches reaching from the second gate layer to the surface of the semiconductor substrate; forming a second support film to couple the side of the first gate layer with the side of the second gate layer, the sides forming the second isolation trench, the second support film having a resistance to the first etchant; and forming the first cavity layer between the semiconductor substrate and the first gate layer and forming the second cavity layer between the first gate layer and the second gate layer using the first etchant to remove the first and second gate insulator layers while leaving the first and second support films. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a plan view of a cell region in a NAND-type EEPROM according to a first embodiment. 
           [0009]      FIGS. 2A and 2B  are cross-sectional views taken along I-I′ line and II-II′ line in  FIG. 1 . 
           [0010]      FIGS. 3A-12B  are cross-sectional views showing the NAND-type EEPROM in order of process step. 
           [0011]      FIG. 13  is a perspective view showing the NAND-type EEPROM in order of process step. 
           [0012]      FIGS. 14A-21B  are cross-sectional views showing a NAND-type EEPROM according to a second embodiment in order of process step. 
           [0013]      FIG. 22  is a perspective view showing the NAND-type EEPROM in order of process step. 
           [0014]      FIGS. 23A and 23B  are cross-sectional views showing the NAND-type EEPROM in order of process step. 
           [0015]      FIG. 24  is a cross-sectional view showing a NAND-type EEPROM according to a third embodiment. 
           [0016]      FIGS. 25A and 25B  are cross-sectional views showing a NAND-type EEPROM according to a fourth embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0017]    The embodiments of the invention will now be described with reference to the drawings. 
       Structure in First Embodiment 
       [0018]      FIG. 1  is a plan view of a cell region in a NAND-type EEPROM (nonvolatile semiconductor memory device) according to a first embodiment of the present invention. 
         [0019]    The cell region includes a plurality of bit lines BL formed therein, which extend in the longitudinal direction in the figure. A layer below these bit lines BL includes selection gates SGD, SGS and a common source line CELSRC formed therein, which extend in the lateral direction perpendicular to the bit line BL. It also includes a plurality of word lines WL, which are sandwiched between the selection gates SGD, SGS and extend in parallel with the selection gates SGD, SGS. 
         [0020]    Memory cells MC are formed below intersections of the word lines WL and the bit lines BL. Selection gate transistors SG 1 , SG 2  are formed below intersections of the selection gates SGD, SGS and the bit lines BL. 
         [0021]      FIG. 2A  is a cross-sectional view in a first direction or a row direction taken along the bit line BL (cross-sectional view taken I-I′ line in  FIG. 1 ) in the NAND-type EEPROM according to the present embodiment.  FIG. 2B  is a cross-sectional view in a second direction or a column direction taken along the word line WL (cross-sectional view taken II-II′ line in  FIG. 1 ). 
         [0022]    As shown in  FIGS. 2A ,  2 B, there is provided a p-type silicon substrate  10 , for example, on which a first gate insulator layer or a first cavity layer  11 , a floating gate  12  composed of polysilicon, a second gate insulator layer or an intergate insulator  13 , and a control gate  14  composed of polysilicon are stacked in this turn to configure a memory cell MC together with the silicon substrate  10 . The first cavity layer  11  may be kept in a vacuum or filled with a gas. In the case of filling a gas, an inert gas such as an N 2  gas and an Ar gas may be filled. 
         [0023]    The floating gates  12  are separated from each other on a memory cell MC basis. The control gates  14  are formed continuously in a direction orthogonal to the bit line BL as the word lines WL or the selection gates SGD, SGS common to the memory cells MC arrayed in the direction orthogonal to the bit line BL or the selection gate transistors SG 1 , SG 2 . Although not shown, as for the selection gate transistors SG 1 , SG 2 , the floating gate  12  and the control gates  14  are short-circuited to configure a normal transistor. 
         [0024]    In regions between the bit lines BL in the upper layer of the silicon substrate  10 , isolation trenches  16  extending in the row direction are formed self-aligned with the floating gates  12 , thereby defining stripe-shaped device regions  18 , which are separated from each other in the column direction. In the isolation trenches  16 , a first support film  17  composed of an insulator is formed to couple the upper portion of the side of the isolation trench  16  with the side of the floating gate  12  to keep the first cavity layer  11  with a certain thickness. 
         [0025]    In portions of the upper layer of the device region  18  opposing the floating gate  12  via the first cavity layer  11 , channel regions of the memory cells MC are formed. In addition, between these channel regions, n-type impurity-diffused regions  19  serving as a drain and a source shared by adjoining memory cells MC are formed. 
         [0026]    The first cavity layer  11 , the floating gate  12 , the intergate insulator  13  and the control gate  14  configure stacked bodies of electrodes. The stacked bodies and the upper surface of the silicon substrate  10  between the stacked bodies are covered with a thin silicon nitride film (not shown), if required, on which an interlayer insulator  15  such as TEOS (tetraethoxysilane) is formed. The interlayer insulator  15  is buried between the stacked bodies. On the interlayer insulator  15 , the bit lines BL are formed selectively. 
         [0027]    The NAND-type EEPROM thus configured has the following effect. Namely, the above-described memory cell of the stacked gate structure may have a capacity C 1  between the channel and the floating gate and a capacity C 2  between the floating gate and the control gate. In this case, the control gate voltage VCG and the floating gate voltage VFG at the time of data write have a relation of VFG=γYVCG as known where γ denotes a coupling ratio, which is represented by γ=C 2 /(C 1 +C 2 ). 
         [0028]    With the floating gate voltage VFG ensured sufficient, lowering the control gate voltage VCG requires as large an increase in the coupling ratio as possible, The tunnel oxide of the prior art structure has a relative permittivity of about 4, which can not reduce C 1  sufficiently. As a result, the coupling ratio γ can not be increased sufficiently and eventually the control gate voltage VCG can not be lowered sufficiently. 
         [0029]    Therefore, the flash memory of prior art requires high voltages for write and erase, a longer time for write and erase, larger power consumption, and larger areas of the row decoder and boosters as a problem. 
         [0030]    With this regard, in the nonvolatile semiconductor device using the memory cells of the present embodiment including the first cavity layer  11  formed in place of the tunnel oxide, the first cavity layer  11  has a relative permittivity of about 1. Accordingly, the capacity C 1  between the floating gate and the channel can be reduced to about ¼ that of the prior art with a relative permittivity of about 4. Thus, the coupling ratio γ can be increased sufficiently and the control gate voltage VCG can be lowered accordingly. This is effective to lower the control gate voltages at the time of data write and erase and reduce the circuit areas of the booster, the row decoder and so forth. 
         [0031]    In this embodiment, the first gate insulator layer immediately beneath the floating gate  12  is the cavity layer  11  and accordingly no charge trap is accumulated immediately beneath the floating gate  12 . Therefore, the number of rewrite operations cannot be lowered by the reduction in FN tunnel current due to charge traps and thus the number of rewrite operations above 10 5  can be realized. 
         [0032]    In the present embodiment, the first cavity layer  11  has no conduction band and accordingly has a larger barrier height than the tunnel oxide. Therefore, the transmittance of the FN tunnel current may lower and elongate the write and erase time possibly. In this case, however, no charge trap stays in the first gate insulator if it is the first cavity layer  11  and accordingly the thickness of the first gate insulator can be thinned correspondingly (for example, to 80 Å or thinner). As a result, the write and erase time can be reduced. 
       Manufacturing Method in First Embodiment 
       [0033]    Referring next to  FIGS. 3-13 , a method of manufacturing the above-described NAND-type EEPROM according to the first embodiment is described. 
         [0034]    First, as shown in  FIG. 3A  (I-I′ section) and  FIG. 3B  (II-II′ section), a silicon oxide  21  or the first gate insulator layer is formed on the silicon substrate  10  in the memory cell region. A first polysilicon film  12 A turned into the floating gate  12  is formed as the first gate layer on the silicon oxide  21 . Then, a resist film (not shown) is formed on the first polysilicon film  12 A. The resist film is then patterned to selectively remove the first polysilicon film  12 A, the silicon oxide  21  and the upper layer of the silicon substrate  10  by anisotropic etching as shown in  FIG. 4  (II-II′ section), thereby forming the first isolation trenches  16  extending in the first direction or the row direction. 
         [0035]    Subsequently, the resist film is removed and a TEOS film is formed over the entire surface. A process of CMP (Chemical Mechanical Polishing) is applied to planarize the surface of the TEOS film. Further, a wet etching with DHF (Dilute Hydrofluoric acid) or RIE (Reactive Ion Etching) is used to etch back the surface of the TEOS film to form a first insulating film  22  inside the first isolation trenches  16  as shown in  FIG. 5  (II-II′ section). The first insulating film  22  is formed such that the upper surface thereof locates lower than the upper surface of the silicon substrate  10 . 
         [0036]    Next, a second insulating film  23  composed of SiN or Al 2 O 3  is formed over the entire surface and buried in the trenches on the first insulating film  22  as shown in  FIGS. 6A and 6B . The second insulating film  23  may be composed of other material if it has a resistance to a later-described first etchant or hydrofluoric gas (HF-vapor) for removing the silicon oxide  21 . 
         [0037]    Subsequently, a RIE (Reactive Ion Etching) process with a second etchant different from the first etchant is used to partly remove the second insulating film  23  to form the first support film  17  (first wing) as shown in  FIGS. 7A and 7B . The first support film  17  couples the side of the first isolation trench  16  with the side of the polysilicon film  12 A. 
         [0038]    Thereafter, a SiO 2  film is formed over the entire surface to form a third insulating film  24  integrated with the first insulating film  22  as shown in  FIGS. 5A and 5B . The surface thereof is then planarized by CMP or the like and, on the upper surface thereof, a second gate insulator layer  13 A having HF-resistance, such as an ONO (SiO 2 —SiN—SiO 2 ) film, to be turned into the intergate insulator  13 , is formed as shown in  FIGS. 9A and 9B . 
         [0039]    Subsequently, on the second gate insulator layer  13 A, a second polysilicon film  14 A is formed as the second gate layer to be turned into the control gate  14  as shown in  FIGS. 10A and 10B . 
         [0040]    Thereafter, a resist film (not shown) is formed and then patterned, followed by an isotropic etching to selectively remove the second polysilicon film  14 A, the second gate insulator layer  13 A, the first polysilicon film  12 A and the silicon oxide  21  to form second isolation trenches  25 . The second isolation trenches extend in a second direction or column direction as shown in  FIGS. 11A and 11B , thereby patterning the multi-layered film to form a stacked gate composed of the floating gate  12 , the intergate insulator  13  and the control gate  14 . In addition, using a mask of the stacked gate, impurity ions are implanted to form the impurity-diffused regions  19 . 
         [0041]    Next, a hydrofluoric gas (HF-vapor) or hydrofluoric acid is used to remove the silicon oxide  21  and the third insulating film  24  to form the first cavity layer  11  between the channel portion in the silicon substrate  10  and the floating gate  12  as shown in  FIGS. 12A and 12B . 
         [0042]    Finally, the interlayer insulator  15  composed of SiO 2  is formed over the entire surface and then the bit lines BL are formed thereon to complete the structure shown in  FIGS. 2A and 2B . 
         [0043]      FIG. 13  is a perspective view showing the NAND-type EEPROM according to the present embodiment immediately after the first cavity layer  11  is formed. As obvious from this figure, the silicon oxide  21  is removed from between the silicon substrate  10  and the floating gate  12  to form the first cavity layer  11 . In this case, the first support film  17  couples the silicon substrate  10  with the floating gate  12  and accordingly makes the first cavity layer  11  with a certain thickness while preventing the floating gate  12  from dropping. 
         [0044]    The first support film  17  is formed locally only on the side of the first isolation trench  16 . Accordingly, in the step of removing the silicon oxide  21 , the third insulating film  24  buried in the first isolation trench  16  is also removed together. Such the removal of the third insulating film  24  buried in the first isolation trench  16  makes it possible to reduce capacitive coupling between floating gates  12  adjoining via the first isolation trench  16 . 
       Second Embodiment 
       [0045]      FIGS. 14-22  show process steps of manufacturing a NAND-type EEPROM according to a second embodiment of the present invention. 
         [0046]    It is assumed in the preceding embodiment that the intergate insulator  13  has HF-resistance. If an ONO (oxide-nitride-oxide) film or the like having an insufficient etching ratio to SiO 2  is used as the intergate insulator  13 , it may be formed as follows. 
         [0047]    The steps including and before the step of forming a third insulating film  26  integrated with the first isolation trench  16  are similar to those including and before the step of forming the third insulating film  24  in the first embodiment and therefore omitted from the following detailed description. 
         [0048]    As shown in  FIGS. 14A and 14B , after formation of the third insulating film  26  integrated with the first isolation trench  16 , the upper surface of the third insulating film  26  is planarized by CMP and then slightly etched back using a wet etching or RIE with DHF. Thereafter, a first cover film  27  composed of SiN having HF-resistance is formed over the entire surface and then planarized by CMP to expose the first polysilicon film  12 A and leave the first cover film  27  only on the upper surface of the third insulating film  26 . If the capacitive coupling between adjoining floating gates presents no problem, then the first cover film  27  may be left over the entire surface. 
         [0049]    Next, a second gate insulator layer  13 A of SiO 2  or the like turned into the intergate insulator  13  is formed on the upper surfaces of the first polysilicon film  12 A and the first cover film  27  as shown in  FIGS. 15A and 15B . 
         [0050]    Subsequently, a second polysilicon film  14 A turned into the control gate  14  is formed on the first cover film  13 A as shown in  FIGS. 16A and 16B . 
         [0051]    Thereafter, a resist film (not shown) is formed and then patterned, followed by anisotropic etching to selectively remove the second polysilicon film  14 A, the second gate insulator layer  13 A, the first polysilicon film  12 A and the silicon oxide  21  to form second isolation trenches  25 . The second isolation trenches  25  extend in the column direction as shown in  FIGS. 17A and 17B , thereby patterning the multi-layered film to form a stacked gate composed of the floating gate  12 , the intergate insulator  13  and the control gate  14 . In addition, using a mask of the stacked gate, impurity ions are implanted to form the impurity-diffused regions  19 . 
         [0052]    Subsequently, a TEOS film is formed over the entire surface as shown in  FIGS. 18A and 18B . The surface of the TEOS film is then planarized by CMP. Further, the surface of the TEOS film is etched back using a wet etching or RIE with DHF to form a fourth insulating film  28  inside the second isolation trenches  25 . The fourth insulating film  28  is formed such that the upper surface thereof locates lower than the upper surface of the floating gate  12 . 
         [0053]    Next, a fifth insulating film  29  composed of SiN or Al 2 O 3  is formed over the entire surface and buried in the trenches on the fourth insulating film  28  as shown in  FIGS. 19A and 19B . The fifth insulating film  29  may be composed of other material if it has HF-resistance. 
         [0054]    Subsequently, a RIE process or the like is used to partly remove the fifth insulating film  29  to form a second cover film  31  (second wing) as shown in  FIGS. 20A and 20B . The second cover film is arranged to couple the sides of the floating gate  12  opposing along the gate length with the sides of the control gate  14  opposing along the gate length and is formed along both the sides to cover the side of the intergate insulator  13 . 
         [0055]    Thereafter, a hydrofluoric gas (HF-vapor) or hydrofluoric acid is used to remove the fourth insulating film  28 , the silicon oxide  21  and the third insulating film  26  to form the first cavity layer  11  between the channel portion in the silicon substrate  10  and the floating gate  12  as shown in  FIGS. 21A and 21B . 
         [0056]      FIG. 22  is a perspective view showing the NAND-type EEPROM according to the present embodiment immediately after the first cavity layer  11  is formed. As obvious from this figure, coupling the silicon substrate  10  with the floating gate  12  by the first support film  17  makes it possible to prevent the floating gate  12  from dropping, like in the preceding embodiment. In the present embodiment, the side of the intergate insulator  13  is covered with the second cover film  13  and the lower surface of the intergate insulator  13  is covered with the first cover film  27 . Accordingly, the intergate insulator  13  can be protected from HF on removal of the silicon oxide  21 . 
         [0057]    After the above step, an interlayer insulator  32  composed of SiO 2  may be formed over the entire surface to form a space along the channel length of the floating gate  12  as shown in  FIGS. 23A and 23B . 
       Third Embodiment 
       [0058]      FIG. 24  is a cross-sectional view showing a NAND-type EEPROM according to a third embodiment of the present invention taken along I-I′ line. 
         [0059]    In the preceding embodiments, the interlayer insulator  32  has floated bottoms. In the third embodiment, though, an interlayer insulator  33  has bottoms extending in pillar shapes and reaching the silicon substrate  10 . With the use of such the structure, the stacked gate structure can be supported surely on the pillars of the interlayer insulator  33 . 
       Fourth Embodiment 
       [0060]      FIGS. 25A and 25B  are cross-sectional views showing a NAND-type EEPROM according to a fourth embodiment of the present invention. 
         [0061]    In the present embodiment, the first cavity layer  11  formed between the floating gate  12  and the silicon substrate  10  and a second cavity layer  34  is formed between the floating gate  12  and the control gate  14 . 
         [0062]    This structure can be produced through the similar steps to those in the second embodiment without forming the first cover film  27  of  FIG. 14B . In this case, the second cover film  31  serves as a second support film capable of retaining the gap between the floating gate  12  and the control gate  14 . 
       Other Embodiments 
       [0063]    In the above embodiments, the NAND-type EEPROM is exemplified to describe the present invention. The present invention may also be applied to a NOR-type EEPROM, a 3-Tr flash memory and a NANO flash memory.