Abstract:
A low voltage differential swing (LVDS) signal driver having substantially constant output differential voltage (Vod) and substantially constant output offset voltage (Vos) irrespective of variations in circuit fabrication processes, power supply voltages and operating temperatures (PVT), as well as circuit load conditions. A driver replica circuit which replicates a portion of the actual LVDS driver circuit conducts a driver replica operating current that is a scaled replica of the LVDS driver operating current. Operating voltages within the LVDS driver and driver replica circuits are monitored and controlled by bias voltages provided by the driver replica circuit. The desired scaling factor for the operating currents is ensured by appropriate scaling of the sizes of the circuit devices within the LVDS driver and driver replica circuits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to high speed digital integrated circuits, and in particular, to low voltage differential swing (LVDS) signal drivers for uses in and with high speed digital integrated circuits. 
     2. Description of the Related Art 
     With the tremendous growth of the Internet, data transfers, in terms of both volume and speed, are increasing dramatically in all areas of communications. For example, data streams for digitized video signals, high definition television (HDTV) and color graphics data require increasing amounts of bandwidth. As a result, increasingly higher speed interconnects between integrated circuits (chips), functional boards and systems become increasingly critical. While virtually all such data is digital in form, it is a high speed analog circuit technique that has become increasingly prevalent in meeting such data transfer needs. This circuitry, i.e., LVDS, provides for multigigabit data transfers on copper interconnects and high speed transmission lines, including fiber optic applications. These LVDS circuits have proven speed, low power, noise control and cost advantages important in point-to-point applications for telecommunications, data communications and video displays. 
     However, while LVDS circuits continue to provide significant advantages in applications requiring high data transfer rates, such circuits are not immune from three major parameters that influence the operation of virtually any circuit or system: circuit fabrication (or manufacture) process variations (“P”); power supply voltage variations (“V”); and operating temperature variations (“T”); often referred to collectively as PVT. 
     With respect to fabrication process variations, it is well known that notwithstanding the stringent quality control measures typically used to fabricate integrated circuits, fabrication processes nonetheless suffer some variations among the various processing parameters. 
     With respect to power supply variations, it is well known that notwithstanding the use of various filters or shielding techniques, noise and especially low frequency noise can be present or induced in the power supply line (e.g., switching noise, electromagnetic interference, etc.). Power supply noise can cause jitter on the rising and falling edges of the signal being processed, as well as frequency skew within the output signal. 
     With respect to operating temperature variations, such variations will virtually never be avoidable, as operating temperatures can vary due to a number of causes, including variations in data transfer rates, ambient temperature, variations in power supply voltage, among others. As operating temperatures vary, so can the amplitude, phase and frequency of some of the signals being processed. 
     Further, conventional LVDS circuits are sensitive to circuit load conditions. Variations in the load impedance will induce variations in the output differential voltage or output offset voltage or both. 
     SUMMARY OF THE INVENTION 
     A low voltage differential swing (LVDS) signal driver having a substantially constant output differential voltage (Vod) and a substantially constant output offset voltage (Vos) irrespective of variations in circuit fabrication processes, power supply voltages and operating temperatures (PVT), as well as circuit load conditions. A driver replica circuit which replicates a portion of the actual LVDS driver circuit conducts a driver replica operating current that is a scaled replica of the LVDS driver operating current. Operating voltages within the LVDS driver and driver replica circuits are monitored and controlled by bias voltages provided by the driver replica circuit. The desired scaling factor for the operating currents is ensured by appropriate scaling of the sizes of the circuit devices within the LVDS driver and driver replica circuits. 
     In accordance with one embodiment of the presently claimed invention, a low voltage differential swing (LVDS) signal driver includes differential signal driver circuitry and signal replication circuitry. The differential signal driver circuitry receives upper and lower biasing signals and in response thereto conducts a driver operating current, provides a driver monitor signal and receives and converts a differential input signal to a LVDS signal. The signal replication circuitry, coupled to the differential signal driver circuitry, receives upper and lower reference signals and the driver monitor signal and in response thereto provides the upper and lower biasing signals and conducts a replica operating current which is maintained as a predetermined replica of the driver operating current. 
     In accordance with another embodiment of the presently claimed invention, a low voltage differential swing (LVDS) signal driver includes differential signal driver means and signal replicator means. The differential signal driver means is for receiving upper and lower biasing signals and in response thereto conducting a driver operating current, providing a driver monitor signal and converting a differential input signal to a LVDS signal. The signal replicator means is for receiving upper and lower reference signals and the driver monitor signal and in response thereto providing the upper and lower biasing signals and conducting a replica operating current which is maintained as a predetermined replica of the driver operating current. 
     In accordance with still another embodiment of the presently claimed invention, a method for generating a low voltage differential swing (LVDS) signal driver includes: receiving upper and lower biasing signals and in response thereto conducting a driver operating current, providing a driver monitor signal and converting a differential input signal to a LVDS signal; receiving upper and lower reference signals and the driver monitor signal and in response thereto providing the upper and lower biasing signals and conducting a replica operating current; and maintaining the replica operating current as a predetermined replica of the driver operating current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of a LVDS signal driver in accordance with one embodiment of the presently claimed invention. 
     FIG. 2 is an electrical schematic diagram of an example embodiment of the circuit of FIG.  1 . 
     FIGS. 3A-3D together are a more detailed electrical schematic diagram of a specific embodiment of the circuit of FIG. 1 in accordance with the circuit topology of FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
     Referring to FIG. 1, an LVDS signal driver circuit  10  (preferably in integrated circuit form) in accordance with one embodiment of the presently claimed invention includes a differential signal driver circuit  12  and a replica bias circuit  14  which, as discussed in more detail below, provides and replicates a number of bias signals. 
     In accordance with well known LVDS circuit principles, the driver circuit  12  receives a differential input signal Vin having a primary (“positive”) differential signal phase Vinp and an inverse (“negative”) differential signal phase Vinn. As is well known, the driver circuit  12  converts this signal Vin to a LVDS output signal Vout having a peak-to-peak differential signal amplitude Vod (e.g., approximately 350 millivolts) and an offset voltage Vos (e.g., 1.2 volts). This output signal Vout drives a load resistance Rload located at the receiver circuitry (not shown) external to this circuitry  10 . (As is well known in the art, the differential input signal Vin need not necessarily be a dual differential signal, but can also be a single differential input signal, as discussed in more detail below.) 
     In accordance with the presently claimed invention, this driver circuitry  12  provides a driver monitor signal Vmondrv and receives two bias signals Vbiasup, Vbiaslw. As discussed in more detail below, this monitor signal Vmondrv is monitored and controlled by way of the incoming bias signals Vbiasup, Vbiaslw with the result being that the driver circuitry  12  has significantly reduced PVT sensitivity. 
     As discussed in more detail below, the replica bias circuitry  14  generates an upper monitor signal Vmonup and a lower monitor signal Vmonlw, as well as a replica monitor signal Vmonrep. The upper Vmonup and lower Vmonlw signals are compared against corresponding externally generated upper Vrefup and lower Vreflw reference signals, with the resulting difference signals Vbiasup and Vbiaslw, respectively, provided as upper and lower biasing signals to the driver circuitry  12 . The replica monitor signal Vmonrep is similarly compared to the driver monitor signal Vmondrv, with the resulting difference signal Vbiasin used to bias the replica bias circuitry  14 . 
     Referring to FIG. 2, one example embodiment  10   a  of the circuit  10  of FIG. 1 can be implemented as shown. The LVDS driver circuitry  12   a  includes P-type metal oxide semiconductor field effect transistors (P-MOSFETs) M 0 , M 3  and M 9 , and N-MOSFETs M 1 , M 2  and M 1 , all interconnected substantially as shown. Transistors M 0 , M 1 , M 2  and M 3  form the output signal “switchbox” with differential pair transistors MO and M 3  receiving the primary differential phase Vinp and differential pair transistors M 1  and M 2  receiving the inverse differential phase Vinn of the input signal Vin. (It should be understood that while this output switchbox has been implemented in a complementary arrangement of P-and N-MOSFETs, a similar switchbox can be implemented using all P-MOSFETs or all N-MOSFETs as desired.). The interconnected drain terminals of transistors of M 0  and M 1  and transistors M 2  and M 3  provide the differential output signal Vout. In accordance with well known LVDS principles, when transistors M 1  and M 3  are turned on, transistors M 0  and M 2  are turned off, while conversely, when transistors M 0  and M 2  are turned on, transistors M 1  and M 3  are turned off. Accordingly, the output current lout is steered through the external load resistor Rload (not shown) to produce the output voltage Vout. (As noted above, the differential input signal Vin need not necessarily be a dual differential signal, but can also be a single differential input signal, in which case for this complementary arrangement of P- and N-MOSFETs, the gate terminals of transistors M 3  and M 2  would be driven together while the gate terminals of transistors M 0  and M 1  would be driven together.) 
     Transistors M 9  and M 10  serve as a current source and a current sink, respectively, for the output current lout flowing between the positive power supply terminal VDD and the negative power supply terminal VSS (or ground GND). As discussed in more detail below, transistor M 9  is biased by an upper biasing voltage Vbiasup and transistor M 10  is biased by a lower biasing voltage Vbiaslw which maintain the output current lout in such a manner as to establish and maintain the driver monitor voltage Vmondrv at the interconnect between the current source transistor M 9  and output switchbox transistors M 0  and M 3 . 
     The replica bias circuitry  14   a  includes P-MOSFETs M 4 , M 5  and M 6 , and N-MOSFETs M 7  and M 8  interconnected in a telescopic, or totem pole, manner substantially as shown. Transistor M 6  serves as a current source controlled by the upper biasing voltage Vbiasup. Similarly, transistor M 8  serves as a current sink controlled by the lower biasing voltage Vbiaslw. Transistors M 5  and M 7 , with their respective gate terminals biased at power supply rails VSS and VDD, respectively, are biased in their fully on states and provide isolation between the current source M 6  and sink M 8  transistors and transistor M 4 . Transistor M 4  is operated to emulate the load resistor Rload by providing within the replica bias circuitry  14   a  a replica resistance corresponding to the load resistor Rload. 
     A replica current Irep flows through transistors M 6 , M 5 , M 4 , M 7  and M 8 . As per Ohm&#39;s Law, the voltage Vrep across transistor M 4  must equal the product of the current Irep through transistor M 4  and the resistance RM 4  of transistor M 4 , or Vrep=Irep*RM 4 . 
     Similarly, the output current lout in the driver circuitry  12   a  flows through the load resistor Rload (not shown). Also as per Ohm&#39;s Law, the voltage Vout across the Rload must equal the product of the current lout through the load Rload and the resistance Rload, or Vout=Iout*Rload. 
     The gate terminal of transistor M 4  is controlled, or modulated, by the intermediate biasing voltage Vbiasin generated by signal comparison circuit OP 3 . This biasing voltage Vbiasin controls, or modulates, the resistance RM 4  of transistor M 4 . In turn, this controls, or modulates the replica current Irep through the replica circuitry  14   a . Further in turn, this controls, or modulates, the replica monitor voltage Vmonrep which is compared by circuit OP 3  against the driver monitor voltage Vmondrv. (It should be understood that, as an alternative, the driver monitor voltage Vmondrv could also be that appearing at the interconnect between the current sink transistor M 10  and output switch box transistors M 1  and M 2 . In a corresponding manner, the replica monitor voltage Vmonrep would then be that appearing at the interconnect of transistors M 7  and M 8 . As discussed above, signal comparison amplifier OP 3  could monitor these voltages and provide the intermediate biasing voltage Vbiasin in an equally effective manner.) 
     Based upon this comparison of these input signals Vmondrv, Vmonrep, circuit OP 3  will adjust the intermediate biasing voltage Vbiasin as necessary to cause these input signals Vmondrv, Vmonrep to become and remain equal. As a result, the drain-to-source voltages Vds, as well as the gate-to-source voltages Vgs (due to the common gate biasing voltage Vbiasup), of current source transistors M 6  and M 9  equal. Accordingly, the currents Irep and lout sourced by these transistors M 6  and M 9 , respectively, are maintained at respective values that are determined by the relative sizes (e.g., channel widths) of these transistors M 6 , M 9 . For example, if transistors M 6  and M 9  were of equal size, then these currents Irep, lout would be equal, or Irep=lout. However, if transistor M 9  is larger than transistor M 6  by a factor of  20  (in accordance with a preferred embodiment of this circuit  10   a ) then the ratio of the output current lout to the replica current Irep would be Iout:Irep=20:1. 
     It should be understood that virtually any scaling factor can be selected, depending upon the desired replica Irep and output Iout currents. Depending upon the desired scaling factor, such scaling factor will be common with respect to the ratios of the sizes of the various transistors as follows: transistors M 6  and M 9 ; transistors M 5 , M 0  and M 3 ; transistors M 7 , M 1  and M 2 ; and transistors M 8  and M 10 . 
     In accordance with this scaling factor, since the transistor stack of the driver circuitry  12   a  and the transistor stack of the replica biasing circuitry  14   a  are equal in terms of device counts between the power supply rails VDD, VSS, the respective voltages dropped across the corresponding devices will be equal. For example, the drain-to-source voltages across transistors M 6  and M 9  will be equal, as will the drain-to-source voltages across transistors M 8  and M 10 , transistors M 5 , M 0  and M 3 , and transistors M 7 , M 1  and M 2 . Lastly, the replica voltage Vrep across transistor M 4 , as noted above, will be equal to the output voltage Vout. This replica voltage Vrep can be changed by proper selection of the upper Vrefup and lower Vreflw reference voltages. 
     Signal comparison circuitry OP 1  receives and compares the upper monitor signal Vmonup and the upper reference voltage Vrefup to provide the upper biasing voltage Vbiasup for transistors M 6  and M 9 . Similarly, signal comparison circuit OP 2  receives and compares the lower monitor signal Vmonlw and lower reference voltage Vreflw to provide the lower biasing voltage Vbiaslw to transistors M 8  and M 10 . In accordance with well known voltage comparator circuit principles, if the upper Vmonup or lower Vmonlw monitor signal voltages increase, e.g., due to an increase in the replica current Irep, then the upper Vbiasup and lower Vbiaslw signal voltages, respectively, also increase. Conversely, if these monitor signal voltages Vmonup, Vmonlw decrease, then the corresponding biasing voltages Vbiasup, Vbiaslw also decrease. As a result, the output lout and replica Irep currents are maintained at the values necessary to, in turn, maintain the output signal voltage Vout at the value established by the controlling of transistor M 4 . 
     Referring to FIGS. 3A and 3B, a more detailed example embodiment  10   b  of the circuit  10   a  of FIG. 2 can be implemented as shown. The LVDS driver circuitry  12   b  includes P-MOSFETs M 206 , M 205 , M 259 , M 263 , M 208 , M 207  and M 35 , and N-MOSFETs, M 186 , M 185 , M 2 , M 1 , M 188 , M 187  and M 30 , all interconnected substantially as shown. Transistors M 206 , M 205 , M 259 , M 263 , M 208 , M 207 , M 186 , M 185 , M 2 , M 1 , M 188  and M 187  form the output signal switchbox with differential pair transistors M 206 , M 205 , M 259 , M 263 , M 208  and M 207  receiving the primary differential phase Vinp and differential pair transistors M 186 , M 185 , M 2 , M 1 , M 188  and M 187  receiving the inverse differential phase Vinn of the input signal Vin. The interconnected drain terminals of these transistors provide the differential output signal Vout. Transistors M 35  and M 30  serve as the current source and current sink, respectively, for the output current Iout. 
     The replica bias circuitry  14   b  includes P-MOSFETs M 165 , M 166  and M 170 , N-MOSFETs M 156  and M 155 , and resistor R 74 , all interconnected substantially as shown. Resistor R 74  is connected across transistor M 170  for the purpose of increasing the resolution of the variable resistance formed by the parallel combination of resistor R 74  and the drain-to-source, or channel, resistance of transistor M 170 . Signal comparison circuit OP 3 , contained within circuit block  20 , receives and compares the driver monitor voltage Vmondrv and replica monitor voltage Vmonrep and provides the intermediate biasing voltage Vbiasin to the gate terminal of transistor M 170 . 
     Signal comparison circuitry OP 1  receives and compares the upper monitor signal Vmonup and the upper reference voltage Vrefup to provide the upper biasing voltage Vbiasup for transistors M 165  and M 35 . Similarly, signal comparison circuit OP 2  receives and compares the lower monitor signal Vmonlw and lower reference voltage Vreflw to provide the lower biasing voltage Vbiaslw to transistors M 155  and M 30 . In accordance with well known voltage comparator circuit principles, if the upper Vmonup or lower Vmonlw monitor signal voltages increase, e.g., due to an increase in the replica current Irep, then the upper Vbiasup and lower Vbiaslw signal voltages, respectively, also increase. Conversely, if these monitor signal voltages Vmonup, Vmonlw decrease, then the corresponding biasing voltages Vbiasup, Vbiaslw also decrease. As a result, the output lout and replica Irep currents are maintained at the values necessary to, in turn, maintain the output signal voltage Vout at the value established by the controlling of transistor M 170 . 
     Additional circuitry  22 , including P-MOSFETs M 233 , M 234 , M 209  and M 228 , N-MOSFETs M 189 , M 192 , M 199  and M 198 , resistor R 64 , and circuit blocks  24   a  and  24   b , which is not part of the presently claimed invention, provides a power down function such that when output signal terminals OUT and OUTB are connected to a signal bus but are not driving such signal bus and, therefore, are placed in a high impedance mode, any other signal voltage appearing on the bus will not cause any of the parasitic diodes within the output P-MOSFETs to turn on due to the presence of such signal bus voltages. 
     Other circuitry  26  can also be provided as a pre-driver stage to ensure that, for each phase of the input signal Vin, all of the output current passes to the load with none remaining to be dissipated within the switchbox, thereby ensuring maximum efficiency in terms of transfer of output current to the load. (For example in the circuit of FIG. 2, when transistors M 1  and M 3  are turned on, transistors M 0  and M 2  are turned off completely, and conversely, when transistors M 0  and M 2  are turned on, transistors M 1  and M 3  are turned off completely.) Additionally, a resistor string  28  can be included to provide any necessary reference voltages. 
     A simulation of the circuitry  10   b  as implemented in FIGS. 3A and 3B demonstrated an output voltage Vout having variations in its differential output voltage amplitude Vod and offset voltage Vos of 15 millivolts and 17 millivolts, respectively, across PVT and load resistance variations. 
     Based upon the foregoing discussion, it can be seen that LVDS signal driver circuitry in accordance with the presently claimed invention advantageously minimizes sensitivity to variations in circuit fabrication processes, power supply voltage and operating temperature. For example, by monitoring and maintaining a constant voltage across the output signal switchbox and maintaining equal biasing voltages across corresponding circuit components within the driver and replica bias circuits while also emulating the load, the differential output Vod and offset Vos voltages will be dependent virtually only on the reference voltages Vrefup, Vreflw. In turn, such reference voltages Vrefup, Vreflw can be generated using PVT-insensitive voltage sources such as bandgap voltage sources, which demonstrate high immunity from PVT variations and are well known in the art. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.