Abstract:
It is the aim of the exemplary disclosure to create a simple system with as great a variability as possible wherein a pulse generator for each ultrasonic transducer element comprises a digital frequency control member for controlling the pulses to be fed to the transducer element and at which at least the pulse frequency (f s ) can be selected by means of an input digital value (FW).

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to ultrasonic transmitter circuitry for operating ultrasonic transducers, which circuitry includes a pulse generator for supplying electrical excitation pulses. 
     Ultrasonic excitation transmitter circuitry of this type should, with respect to the operation of ultrasonic transducers, be designed as versatilely as possible. The circuitry should preferably be applicable not only in a great variety of types of transducer systems, such as, for example, sound heads, with only one or a small number of transducer elements, or whole transducer meshes (so-called arrays); but further in one and the same type of the applied transducer system, quick transfer is desirable to various operational conditions, such as, for example a different transmitting frequency, duration and/or number of the pulses to be emitted during the excitation phase. Especially in phased arrays there is also the desire to be able to make particularly simple adjustment of the delay times, and yet still retain a high degree of accuracy. Conventional devices of all types permit changes in methods of operation in all (as a whole) only by fine tuning individual circuit members by direct intervention in the circuit, or by multiple preparation of individual circuit members or even whole transmitting systems. 
     SUMMARY OF THE INVENTION 
     The aim of the invention is to produce a simpler system with greater versatility for ultrasonic transmitters of the type named above. 
     The aim is achieved according to the invention, in that the pulse generator comprises a digital frequency controlling member, for controlling the pulse rate of the pulses to be supplied to the transducer, in which at least the pulse frequency can be adjusted by means of an input digital value. 
     The invention permits a simple software-type changeover of the ultrasonic transmitter frequency when necessary; intervention in the &#34;hard-wired&#34; circuitry is not necessary. The ultrasonic excitation transmitter according to the invention therefore presents optimal adaptability in various transducer systems with various frequency requirements. Particularly in the case of fixed arrays, precisely defined delay times are given regarding the delayed onward activation of transducer elements excited one after the other chronologically. The transmitting system is thus optimally designed also in this sense. 
     In an advantageous embodiment of the invention, corresponding digital control members can be provided for other parameters of the excitation pulses. Thus, in addition to the frequency control member, a second digital control member, amongst others, can also be present, in which the number of pulses to be fed to a transducer within an excitation phase, and therefore also the total duration of an excitation pulse, can be adjusted by means of an input digital value. If necessary, a third digital control member can also be included, in which the pulse-duty factor can be preselected on the basis of an input digital value. 
     Further advantages and details of the invention will be apparent from the description, below, of an exemplary embodiment illustrated on the accompanying drawing sheet, and from the features of the subclaims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 and 2 illustrate the invention by means of basic circuit diagram; and 
     FIG. 3 shows an impulse diagram of significant voltage pulse sequences, for illustrating the operation of the circuitry of FIGS. 1 and 2. 
    
    
     DETAILED DESCRIPTION 
     In FIG. 1, a programmable reverse (count-down) counter is designated by reference numeral 1, which includes two onward control inputs 2 and 3 and a programming input 4 for input of the desired frequency of the excitation impulses in the form of a digital value FW. At a signal output 5, each time the reverse counter passes through zero, an overflow impulse is emitted, whose pulse rate is a function of the digital input frequency value FW. The component 6 represents a pulse-length multiplexer. At input 7 of component 6, the number of pulses to be allocated altogether to a transmitting pulse is controlled, again in the form of a digital input value (address LW). The number of pulses as digitally selected at LW then determines the total length of the excitation impulse. In the shown interconnection, electronic gates 8 and 9, divider flip-flops 10 and 11, and a starting stage consisting of starting impulse transmitter 12, AND-gate 13 and synchronizing flip-flop 14, are associated with both components 1 and 6. Synchronization proceeds via the pulse rate PT of a central pulse rate generator 15. The pulse sequences S1(t) and S2(t) resulting at the outputs Q of the divider flip-flops 10 and 11 are phase-shifted relative to each other preferably by a pulse duration τ. They then have e.g. the waveforms shown in the diagram of FIG. 3 with the pulse duty factor of 1.1. Thus in FIG. 3, waveforms S1(t) and S2(t) each have equal &#34;on&#34; and &#34;off&#34; intervals, each such interval having a time duration τ, equal to one-half the total period T of each waveform, and the waveforms being offset in phase by T/2. These pulses are finally supplied to a push-pull output stage according to FIG. 2. The push-pull output stage comprises on the input side a driving circuit 17, which is followed on the output side by two transistors 28, 29 in push-pull arrangement, preferably V MOS field effect transistors, via two circuits formed by toroidal core broad-band transformers 18 and 19, diodes 20 and 21, ohmic resistors 22 to 26 and a capacitance 27. On account of the push-pull control of these transistors 28 and 29, a square-wave voltage S(t), FIG. 3, results with an amplitude alternating between +U B  and -U B . This square-wave voltage S is then finally supplied to an ultrasonic transducer 33 via an output network formed by an ohmic resistor 30 and oppositely poled diodes 31 and 32. 
     As already mentioned above, in the case of the ultrasonic transducer 33, a single transducer element may be involved, which emits and receives impulses (e.g. for A-scan-operation). In the illustrated embodiment, however, the transducer 33 is to be, in particular, a single transducer element of a whole transducer mesh (array) for B-scan e.g. that of a phased array. Depending upon the total number of all transducer elements of the array arranged next to each other or even one on top of the other in lines in matrix form, a corresponding number of transmitting stages is then necessary according to the form described here. In the case of application in a phased array, the variable delay times are determined in the simplest way, in that simply the times of applying starting impulses to the starting impulse transmitter 12 of each transmitter stage are selected so as to follow at variable intervals. Thus the delay times are as simple as possible and can be exactly reproduced at any time. In respect of the pulse waveforms of the diagram in FIG. 3, the pulse duration τ amounts preferably to half the wavelength (λ/2) of the useful excitation oscillation S(t), FIG. 3, for a transducer element. With the selected pulse duty factor of 1:1, the symmetrical square-wave pulse waveform S(t) according to FIG. 3 then corresponds exactly to the fundamental wave of the transducer as regards frequency, after sine-shaped obliteration at the respective transducer element. The transducer is thus stimulated at its useful resonant frequency; the harmonic content scarcely has any further effect. The excitation transmitter according to the invention thus brings about a relatively narrow-band excitation of the transducer element. As a consequence, the selected pulse-duty factor of 1:1 with λ/2 as pulse duration creates a transmitting system with particularly high efficiency. Naturally, other pulse-duty factors are also possible e.g. by variation of FW during the set-up of a transmitting pulse sequence; however, they generally lead to a widening of the frequency range. 
     The method of function of the invention according to the exemplary embodiment shown in FIGS. 1 to 3 can be summarized as follows: 
     Before the device is set into operation, the desired frequency is input as a digital value FW at the input 4 of the programmable countdown counter 1. Correspondingly, an address word LW for the pulse number and therefore the total length of an excitation impulse is supplied to the multiplexer 6. To initiate a transmitting process, a starting impulse ST is then set by means of a starting impulse transmitter 12, which is coupled to the input D of flip-flop 14 via the AND circuit 13. The pulse sequence PT of the central clock pulse generator 15 is connected at the same time to the CK-input. With the occurrence of the first pulse PT of this central pulse generator, and the previous transmission of the starting inpulse, a synchronized starting impulse is transmitted to the control input 2 (LOAD) of the countdown counter 1 at the output Q of the flip-flop 14. Thereupon, the count-down counter 1 programs itself with the frequency word FW (e.g. in binary digital format) connected to the input 4 thereof. Once programming is concluded, then the reverse counting of the countdown counter also begins at the clock pulse rate of the impulses PT of the central clock pulse generator 15, which are supplied to the control input 3 (CK) of the countdown counter 1 via the open gate 9. The countdown counter 1 finally passes through the zero position after counting the programmed-in number of FW clock pulses, whereupon an overflow-impulse is produced at the output 5 (RCO). This overflow impulse is transmitted to the input D of the flip-flop 14 via the AND-gate 13. Corresponding to the previous starting impulse ST, this new pulse is synchronized with the next pulse PT of the clock pulse generator 15 and is supplied as an additional LOAD-impulse to the control input 2 of the countdown counter 1. The countdown counter 1 thus reprograms itself again with the value FW and the process of counting down to zero is repeated with a renewed feedback of an overflow impulse, as already described above. 
     This continues until a blocking impulse is supplied by the multiplexer 6 to the gate 9. The time of the occurrence of such a blocking impulse is determined by the last occurrence of a pulse of the number of individual pulses of the excitation impulses, preselected by means of the address word LW. If for example, the number of pulses, as shown in FIG. 3, is preselected as LW equal to 3, then the gate 9 is closed by the multiplexer 6 after the occurrence of the third impulse. No further clock pulses PT of the clock pulse generator 15 can then reach the control input 3 of the counter, whereupon the reverse counting process is stopped. Renewed initiation is brought about again only by a new starting impulse ST at the output of the starting impulse transmitter 12. In addition the multiplexer 6 also controls a second electronic gate 8 for the LOAD-impulses of the synchronizing flip-flop 14 of the input starting stage, in dependence on the selected pulse number LW and on the position of the divider flip-flops 10 and 11 on the output side. The gate 8 is opened by the multiplexer 6 at the moment when, from the input CLR, divider flip-flops 10 and 11 are set at zero at the outputs Q at the same time as the setting of a starting impulse. The gate 8 then continues to be open for LOAD-signals until a closing impulse is also supplied to the gate 8 by the multiplexer 6 at the end of the last pulse of the input pulse number. While the divider flip-flop 10 is now immediately blocked for LOAD-impulses, the divider flip-flop 11 receives yet another final LOAD-impulse via the direct connection to the input CK. Thus the phase-shifted pulse sequences S1 and S2 according to FIG. 3, limited to three pulses, appear at the outputs Q in the case of e.g. the preselected number LW=3. These pulse sequences are then finally converted into the square wave signal S(t) at the push-pull stage according to FIG. 2 in the way already described above. 
     According to the invention, the value FW for the frequency is a digital value. However, from this digital value FW, the transmitting pulse frequency is then formed at the outputs of the divider flip-flops 10 and 11, in connection with the central clock pulse rate PT as follows: ##EQU1## If, for example, the central clock pulse rate is selected as PT=20 MHz, and for FW, the digital value for the number 4 is stored, then the transmitting frequency is set to f s  =2 MHz according to the above equation. Different transmitting frequencies f s  result accordingly for different values of FW. 
     In the exemplary embodiment of FIGS. 1 to 3, the starting impulse transmitter 12 can supply its starting impulse ST directly and immediately (undelayed) in the desired transmission clock pulse rate of transmitting impulses. Normal, undelayed transmitting operation then results, for example, for a single transducer or transducer array. Delay must be carried out insofar as focussing is to be effected; for example, in the case of a phased array. To this end, as already mentioned, the starting impulses for the individual transducer elements of the array are to be prescribed in chronological sequence, variably according to a specific time profile. In the latter case, in particular, the starting impulse transmitter 12 is then preferably a program transmitter for such a time profile, it thus has an input SIT for the actual transmitting impulse timing and forms internally, corresponding to the stored delay program, the variable delay times for the time-displaced transmission of starting impulses ST after the occurrence of associated transmitting clock impulses SIT. The clock pulse SIT can be derived selectively from a separate impulse transmitter or also from the central clock pulse generator 15 mentioned already. Corresponding to the impulse progression of FIG. 3, the square wave impulses of the transmitting pulse voltage S(t) have the same amplitudes. In modification of the exemplary embodiment, however, an amplitude variation can be undertaken in the simplest way according to a preselectable profile in that the operational voltage ±UB of the push-pull output stage is designed variably. Through the selection of a suitable amplitude variation, minor lobe effects in particular can be considerably suppressed. The example of operation permits, in practice, frequency changes in the range of 100 kHz to 10 MHz in the case of a supply voltage of between ±50 V. It can therefore be optimally applied to all transducer systems used presently. 
     It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts and teachings of the present invention. 
     SUPPLEMENTARY DISCUSSION 
     By way of example, it will be apparent to those skilled in the art that pulse length multiplexer 6 may be comprised of a binary counter chain and a comparator which may unlatch gates 8 and 9 at count values corresponding to an input binary digital value LW. Thus if counter 1 counts down to zero in response to five pulses PT, then waveform S, FIG. 3, may have a total duration (measured from the ordinate axis) corresponding to thirty-five pulses PT. Thus with input LW of multiplexer 6 set at a binary value corresponding to thirty-five, gates 8 and 9 could be unlatched and rendered non-transmissive after a count is reached in component 6 of thirty-five pulses PT. If desired, gate 8 could be unlatched at a separate digital input value, e.g. LW&#39; of thirty which could be set in conjunction with a second comparator stage associated with the same counter of component 6. 
     Similarly, it will be apparent that each of the waveforms S1 and S2 may have an &#34;on&#34; time of τ A  clock pulses different from its &#34;off&#34; time of τ B  clock pulses by alternately introducing into counter 1, respective count values (τ A  -1) and (τ B  -1) for alternate countdown to zero (in place of a single input count value FW).