Abstract:
A metal capacitor formed as part of metal dual damascene process in the BEOL, of a wafer. A lower plate ( 27 ) of the capacitor is sandwiched between an insulating layer ( 25 ) and a dielectric layer ( 29 ). The insulating layer on an opposite side abuts a layer of metalization ( 23, 24 ) and the dielectric layer separates the lower plate of the capacitor from an upper plate ( 59 ) of the capacitor. A portion ( 27 A) of the lower plate projects into a via ( 37 ) adjacent to it that is filled with copper ( 63 ). The via projects up to a common surface with the upper plate but is electrically isolated form the upper plate. The via also extends down to the layer of metalization.

Description:
FIELD OF INVENTION 
     The present invention relates to fabrication of a capacitor in the layers of metalization on a semiconductor wafer and, more specifically, to a metal capacitor made as part of a copper dual damascene process during fabrication of the layers of metalization on a semiconductor wafer. 
     BACKGROUND OF THE INVENTION 
     As front end of the line (FEOL) components of a chip have become progressively smaller, more numerous, more complex and faster, the number of back end of the line (BEOL) layers has increased. Because of the size and density of the FEOL devices, the width, and hence the cross sectional areas, of the interconnect lines in the BEOL layers has been reduced. However, reducing such cross sectional area raises the resistance of the aluminum interconnect lines heretofore used. Thus, recently there has been a movement to using copper in the BEOL structures because of its lower resistance qualities. Use of copper has required the adoption of a whole new fabrication technology based on copper dual damascene manufacturing techniques. 
     In the past decoupling capacitors for semiconductor chips have been placed in the packaging. However, given the high frequency at which semiconductor chips now operate, the long conduction paths for decoupling capacitors when placed in the packaging is often not acceptable. The migration from an aluminum reactive ion etch process for interconnections on BEOL layers of a semiconductor chip to copper dual damascene interconnection, along with the need to reduce conduction path length for decoupling capacitors, provides a need for new chip level integrated decoupling capacitor structures and methods of fabricating them. 
     SUMMARY OF THE INVENTION 
     It is an objective of the present invention to provide a method and device for fabricating a metal capacitor within the layers of metal on a semiconductor chip. 
     It is another objective of the present invention to provide a method of fabricating a metal capacitor on a chip as part of a copper dual damascene manufacturing process. 
     It is yet another objective to provide a method of fabricating a precision metal capacitor on a semiconductor chip as part of a copper dual damascene manufacturing process. 
     These and other objectives are meet by providing a method of forming a metal capacitor on a wafer having devices fabricated up through at least one level of metal. The method comprises the steps of depositing an insulating layer, forming a first metal plate on the insulating layer and then providing a dielectric material on top of the first metal plate. Next, a via is formed extending through the dielectric material and contacting the first metal plate. Finally, metal is deposited in the via and on top of the first insulating material so as to form a second metal plate. 
     In another aspect of the present invention it provides a capacitor fabricated within metalization layers of a semiconductor wafer. The capacitor includes an insulating layer and a first plate, made from an electrically conductive material, positioned on a first side of the insulating layer. The first plate has a shoulder. In addition, the capacitor has a dielectric material covering the first plate except for the shoulder and a via that projects down past the dielectric material and includes the shoulder of the first plate. A metal stud is positioned in the via which so as to contact the shoulder. A second plate is positioned adjacent the dielectric material so that the dielectric material is positioned between the first plate and the second plate. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A-1F are cross-sectional schematic representations of the steps of one method of fabricating a metal capacitor in a layer of metalization on a semiconductor wafer as part a dual damascene manufacturing process; 
     FIG. 1G depicts an additional step which when included in the method of fabrication depicted in FIGS. 1A-1F provides a second useful alternative method; 
     FIGS. 2A and 2B are cross-sectional schematic representations of the initial steps of another method of fabricating a metal capacitor that is a variation of the method shown in FIGS. 1A-1F; 
     FIGS. 3A and 3B are cross-sectional schematic representations of the initial steps of yet another method of fabricating a metal capacitor that is a variation of the method shown in FIGS. 1A-1F; 
     FIGS. 4A and 4B are cross-sectional schematic representations of the initial steps of still another method of fabricating a metal capacitor that is a variation of the method shown in FIGS. 1A-1F; and 
     FIGS. 5A-5I are representative of yet another method of fabricating a metal capacitor in a layer of metalization on a semiconductor wafer as part a dual damascene manufacturing process. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is a buried metal capacitor made in the layers of metalization during a BEOL dual damascene fabrication process. 
     FIGS. 1A-1F show one method of fabricating the capacitor of the present invention. The capacitor is fabricated in a metal layer on a semiconductor chip  19 , a portion of such chip being depicted in FIG.  1 A. Typically, chip  19  has devices fabricated up through at least a first metal layer  21 . Metal layer  21  has an insulating layer  22  in which metal interconnects  23  and  24  are embedded and passivated. A first insulating layer  25 , e.g., SiO 2 , fluorinated SiO 2 (FSG), polyarelene ethers (PAE), aerogels, hydrogen silsesquoixane (HSQ), methyl silsesquoixane (MSQ) or similar material is formed on first metal layer  21 . Preferably, first insulating layer  25  is made from a low K (e.g., preferably less than 3.0) dielectric constant insulator. A metal plate  27 , which will serve as the buried metal plate of a capacitor, is formed using conventional deposition and etching steps. Plate  27  can be tungsten, or similar refractory metal, which is compatible with adjacent materials and has good conductivity. In addition, plate  27  should be made from a material that during the various fabrication steps, will not experience grain growth or movement that would disrupt the capacitor insulator on top of it. A dielectric layer  29  is deposited on first metal layer  21  and plate  27 . In this embodiment of the invention, dielectric layer  29  will, as explained below, serve as an etch stop and as the capacitor dielectric. Dielectric layer  29  is made from silicon nitride (SiN x  H y ), silicon carbide (SiC x  H y ), silicon dioxide (SiO 2 ) or other similar materials. Preferably dielectric layer  29  is a high relative K (e.g., greater. than 5) dielectric constant insulator. 
     Referring to FIG. 1B, in the next step vias  35  and  37  are formed to provide contact to first metal layer  21  directly above interconnects  23  and  24 , respectively. Vias  35  and  37  are formed by depositing a photoresist, photo-patterning with a mask to prepare for the formation of vias  35  and  37 , forming vias  35  and  37  by etching and then removing the photoresist. Since the technique of depositing a photoresist, photo patterning with a mask, etching and removing the photoresist is well known, a complete description and illustration of the entire process for forming a via or trench will not be given each time the process is discussed. As described in more detail below, via  37  is formed for the purpose of receiving a metal (e.g., tungsten or copper) stud connecting the underlying metal interconnect  24  and the buried metal plate  27 . In this regard, via  37  is formed so that a portion  29 A of dielectric layer  29  is removed above lower plate  27  so as to expose shoulder  27 A. Via  35  receives a typical vertical interconnect or stud between metal layer  21  and upper metal layers. 
     Referring to FIG. 1C, next a second insulating layer  39 , of the same or a different material as first insulating layer  25 , is deposited on dielectric layer  29  and in vias  35  and  37 . Layer  39  should also preferably be a low relative K material (e.g., a K less than 3.0). 
     Referring to FIG. 1D, next trenches  41 ,  42  and  43  are formed in insulating layer  39  by appropriate photo patterning. In the same step vias  35  and  37  are extended down through insulating layer  25  to metal interconnects  23  and  24 , respectively. Dielectric layer  29  at portion  29 A acts as an etch stop halting the etching of the trench  41 . Since vias  35  and  37  were formed in dielectric layer  29  in the prior etching step illustrated in FIG. 1B, etching continues in both vias  35  an  37  down to metal interconnects  23  and  24 . Trenches  42  and  43  may be wider than vias  35  and  37 , and are usually not perfectly aligned with the vias as shown in FIG.  1 D. 
     The etching step illustrated in FIG. 1D must be highly selective such that it does not degrade portion  29 A, which will serve as the capacitor dielectric. The attributes of the etching process used to form trenches  41 ,  42  and  43  and extend vias  35  and  37  to metal layer  21  are such that it effectively etches the insulators  39  and  25  but does not have much of an etch effect on tungsten plate  27  or dielectric layer  29 . In this regard, when dielectric layer  29  is made of silicon nitride or a similar material, suitable etching for the step illustrated in FIG. 1D may be accomplished using conventional perfluorocarbon (PFC) or hydrofluorocarbon (HFC)etches. 
     As depicted in FIG. 1E, the next step is depositing barrier layer  51  on top of insulating layer  39 , in vias  35  and  37  and in trenches  41 ,  42  and  43 . In the preferred embodiment, barrier layer  51  may be made of one or more of Ta, TaN, WN, TiN, TaSiN, TiSiN and a sputtered copper seed layer. In general, any combination of refractory metals, refractory metal silicides and/or refractory metal nitrides could be used for barrier layer  51 . Barrier layer  51  encapsulates the structure formed up to this point so that it is isolated from the copper which will be electroplated in the last step. The thin seed layer of copper is designed to create a surface upon which the copper will nucleate. In some cases, it may not be necessary to include the seed layer in barrier layer  51 . Copper layer  53  is then electroplated onto barrier layer  51 . 
     In the final step of fabrication of the capacitor structure, illustrated in FIG. 1F, copper layer  53  is removed down to surface  55  by a planarizing step, which in the preferred embodiment is a conventional chemical-mechical polish (CMP). step. The planarization step removes the excess copper down to level  55  of insulating layer  39 . This effectively isolates upper plate  59  in trench  41  from copper studs  61  and  63 . Upper plate  59  forms the top plate of the capacitive structure. While it is perferred that layer  53  be made from copper, the present invention is not so limited. Thus, aluminum, aluminum/copper alloys, and other metals may be used for layer  53 . When layer  53  is not made from copper, it is not typically necessary to provide. a sputtered seed layer as part of barrier layer  51 . 
     Thus, the completed basic capacitive structure appears in FIG. 1F, and includes bottom plate  27 , top plate  59  and dielectric layer  29 A positioned between them. Insulating layer  25  and dielectric layer  29 A almost completely surround bottom plate  27 , isolating it from any electrical contact with plate  59 . Shoulder  27 A is the only portion of plate  27  exposed as it projects into via  37 . Shoulder and edge  27 A make electrical contact with stud  63  in via  37 . Layer  51 A is that portion of barrier layer  51  deposited prior to electroplating copper layer  53 , and is itself a conducting layer. Thus, the capacitive structure depicted in FIG. 1F is ready for interconnection to the rest of the circuitry on the wafer. Surface  66  of plate  59  provides the contact for the upper plate  59  and stud  63  in via  37  provides the contact for lower plate  27 . 
     Inclusion of an additional step in the previously described fabrication process provides a useful variation in the method of making the capacitive structure described above. This second embodiment of the invention is achieved by adding a second mask and etch step to pattern capacitor dielectric  29  prior to forming second insulating layer  39 . Referring to FIG. 1B, the second mask and etch step removes portions  29 B and  29 C of dielectric layer  29 . FIG. 1G depicts the wafer after this mask and etch step but before second insulating layer  39  is applied. Since capacitor dielectric  29  is preferably a high dielectric constant material, this variation reduces line to line capacitance between interconnects. 
     An alternative to the via first integration scheme depicted in FIGS. 1A-1F is illustrated in FIGS. 2A and 2B. In this embodiment, after lower plate  27  is fabricated and dielectric layer  29  and insulating layer  39  are deposited, photoresist layer  80  is provided on the insulating layer  39 . Then, photoresist layer  80  is photo-patterned to form vias  35  and  37 , as illustrated in FIG.  2 A. 
     Referring to FIG. 2B, vias  35  and  37  are then etched down through insulating layer  39 , dielectric layer  29 , and first insulating layer  25  to interconnects  23  and  24 , respectively, as described above relative to FIG.  1 D. Thus, vias  35  and  37  are formed all the way to interconnects  23  and  24  with a single mask. Next, another photoresist layer (not shown) is applied and photo-patterned to form trenches  41 ,  42  and  43 , thereby creating the same structure as shown in FIG.  1 d. Thereafter, chip  19  is completed following the process steps described above and illustrated in FIGS. 1E and 1F. 
     While the capacitor structures formed in accordance with the processes illustrated in FIGS. 1A-1F and  2 A and  2 B function quite effectively and are readily manufacturable, the possibility exists for more capacitance and cross-talk between metal lines in semiconductor chip  19  than may be desirable. This occurs due to the relatively high dielectric constant of dielectric layer  29  and its position between metal lines in semiconductor chip  19 . The embodiment of the present invention illustrated in FIGS. 3A and 3B is designed to overcome this potential disadvantage. 
     In this embodiment, a metal layer (not shown) that forms lower plate  27  and dielectric layer  29  are deposited. Then a layer of photoresist (not shown) is applied, patterned using a single mask and etched so as to form a metal/dielectric stack as illustrated in FIG.  3 A. After stripping the photoresist, insulating layer  39  is deposited. Then photoresist layer  80  is deposited on insulating layer  39  and is patterned to form vias  35  and  37 , as illustrated in FIG.  3 A. Vias  35  and  37  are then etched down to interconnects  23  and  24 , as described above with respect to FIG.  2 B. Trenches  41 ,  42  and  43  are then formed in insulating layer  39 , as shown in FIG.  3 B and described above relative to FIG.  2 B. Finally, semiconductor chip  19  is completed as described above and illustrated in FIGS. 1E and 1F. 
     Still another variation of the method illustrated in FIGS. 1A-1F is shown in FIGS. 4A and 4B. This method is similar to the one shown in FIGS. 3A and 3B in that lower plate  27  and dielectric layer  29  are patterned with a single mask. As such, there is no high K dielectric between wiring lines. However, this embodiment differs from the embodiment shown in FIGS. 3A and 3B in that a low K dielectric etch stop layer  82  is deposited on first insulating layer  25  and lower plate  27 /dielectric layer  29  stack. Suitable materials for etch stop layer  82  include SiC X  H y  and SiO X , which are typically deposited to a thickness of about 20-50 nm. Thereafter insulating layer  39  is deposited on etch stop layer  82 , and is patterned to form vias  35  and  37  and trenches  41 ,  42  and  43  as described above. Formation of trenches  41 ,  42  and  43  includes removal of etch stop layer  82  within the trench, as shown in FIG.  4 B. Then following the process steps described above with regard to FIGS. 1A-1F, fabrication of chip  19  is completed. 
     An advantage of providing etch stop layer  82  is that the depth of metal wire structures (not shown) formed in insulating layer  39  in subsequent process steps can be precisely controlled. This occurs by stopping formation of trenches in insulating layer  39  in which the wire structures will be formed on etch stop layer  82 . Control of trench depth, and hence wire structure thickness, avoids or significantly reduces capacitive coupling between wiring that might arise from wire structures of varying thickness. 
     FIGS. 5A-5I depict yet another embodiment of the present method for fabricating essentially the same capacitive structure as appears in FIG.  1 F. FIG. 5A provides a cross-sectional view of a small portion of a semiconductor chip  172  having devices fabricated up through at least a first metal layer  174 . Typically, layer  174  has an insulating layer  175  in which metal interconnects  176  and  178  are formed. The first step is depositing an insulating layer  180  and then patterning a metal plate  182 , generally of tungsten or other materials suitable for plate  27  as discussed above. The materials used for insulating layer  25  may be used for insulating layer  180 . Next a second insulating layer  184  of the same or different material as insulating layer  180  is deposited onto chip  172 . Finally, a photoresist layer  186  is applied. 
     Referring to FIG. 5B, photo patterning is conducted to create capacitor trench  188  and metal line trench  190  in insulating layer  184 . Then, photoresist layer  186  is removed. 
     Next, a thin layer  192  of a high dielectric constant material (FIG. 5C) is deposited on insulating layer  184  and exposed portions of metal plate  182 . Materials of the type used for layer  29  may be used for layer  192 . 
     As illustrated in FIG. 5D, a second photoresist layer  194  is deposited. Photoresist layer  194  is then patterned to create vias  196  and  198 , which stop on dielectric layer  192 . Next, as shown in FIG. 5E, vias  196  and  198  are extended through the high K dielectric layer  192  and insulating layer  180  so that the vias stop on interconnects  176  and  178 . Via  196  is sized so as to expose shoulder  182 A of metal plate  182 . Then photoresist layer  194  is removed to arrive at the structure depicted in FIG.  5 F. 
     Next, barrier layer  200  (FIG. 5G) is deposited onto dielectric layer  192  and on the surfaces defining vias  196  and  198 . Barrier layer  200  is made from the same materials as barrier layer  51 , as discussed above, e.g., a thin layer of TaN, and a thin sputtered copper seed layer. In the next step, copper layer  202  is electroplated in a thick layer on barrier layer  200  (FIG.  5 H). As noted above, layer  202  may be made from a material other than copper, in which case barrier layer  200  typically will not include a sputtered copper seed layer. 
     As depicted in FIG. 5I chip  172  is then planarized using a chemical-mechanical polish or similar method to remove the excess metal from the surface of chip  172 , and to remove upper, horizontally extending portions of barrier layer  200  and dielectric layer so as to stop at surface  203 . This process leaves the finished capacitor with its lower plate  182 , dielectric layer  192 A and upper plate  204 . Shoulder  182 A of the lower capacitor plate  182  makes an electrical contact with stud  206 , i.e., the metal in via  196 . Thus, the capacitor is ready for connection with the rest of the circuitry of chip  172 . Contact with upper plate  204  is made on the top surface  204 A of the plate, and contact with the lower plate  182  is made at the top surface  206 A of stud  206  in via  196 . 
     The present invention is ideally adapated for use in a copper dual damascene fabrication process. However, all damascene metal structures described above, e.g., interconnects  23  or metal layer  53 , may be made from any suitable metal, not just copper. When copper is not used, it may be desirable to modify the composition of the underlying barrier layers, e.g., barrier layer  51 , including omitting the copper seed layer. 
     While the present invention has been described in connection with a preferred embodiment, it will be understood that it is not so limited. On the contrary, it is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined in the appended claims.