Abstract:
An apparatus includes a current-to-voltage converter configured to convert first and second currents into first and second input voltages and provide the first and second input voltages to first and second nodes, respectively, and a current difference determination circuit configured to determine a difference between the first and second currents based on a difference between the first and second input voltages. A method includes converting first and second currents into first and second input voltages to output the first and second input voltages to first and second nodes, respectively, and determining a difference between the first and second currents based on a difference between the first and second input voltages.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This present disclosure claims the benefit of U.S. Provisional Application No. 61/931,451 filed on Jan. 24, 2014, which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     A current comparator converts currents to voltages using load resistors in order to measure a difference between the currents flowing through the load resistors. When the resistance values of the load resistors are substantially the same, a difference between the converted voltages across the load resistors would be proportional to a difference between the currents flowing through the load resistors. As a result, by measuring the difference between the converted voltages, the difference between the currents can be accurately measured. 
     However, if a resistor mismatch (i.e., a difference between the resistance values of the load resistors) results from process variations in a fabrication process, a difference between the resistance values may dominate over the difference between the currents in determining the voltages across the load resistors. For example, if the resistance value of a first resistor is sufficiently greater than that of a second resistor, a first voltage across the first resistor may be higher than a second voltage across the second resistor, although a first current flowing through the first resistor is in fact lower than a second current flowing through the second resistor. In this case, the difference between the first and second currents may not be accurately measured by measuring the difference between the first and second voltages. 
     A conventional approach to address the above issues related to the resistor mismatch includes increasing a size of load resistors. For example, assuming substantially the same process variations in a fabrication process, if a first pair of matched resistors has a length and a width greater than a length and a width of a second pair of matched resistors, respectively, the first pair of matched resistors would have a smaller resistor mismatch than the second pair of matched resistors. However, this approach consumes a greater area for the matched resistors, and also may result in increased power consumption. 
     SUMMARY 
     In an embodiment, an apparatus includes a current-to-voltage converter configured to convert first and second currents into first and second input voltages and provide the first and second input voltages to first and second nodes, respectively, and a current difference determination circuit configured to determine a difference between the first and second currents based on a difference between the first and second input voltages. 
     In an embodiment, the apparatus further includes a preamplifier including first and second input terminals coupled to the first and second nodes, respectively, and configured to output first and second amplified voltage signals, and first and second current sources. The current-to-voltage converter includes first and second resistors coupled to a power supply voltage. The current difference determination circuit includes a first pair of switching devices configured to couple the first resistor to the first current source in response to a first version of a switching signal and couple the first resistor to the second current source in response to a second version of the switching signal. The current difference determination circuit also includes a second pair of switching devices configured to couple the second resistor to the second current source in response to the first version of the switching signal and couple the second resistor to the first current source in response to the second version of the switching signal. 
     In an embodiment, the first pair of switching devices includes first and second switching devices and the first and second switching devices are coupled to the first resistor at a third node. The second pair of switching devices includes third and fourth switching devices and the third and fourth switching devices are coupled to the second resistor at a fourth node. 
     In an embodiment, the first and fourth switching devices are turned on and the second and third switching devices are turned off when the switching signal has a first value. The first and fourth switching devices are turned off and the second and third switching devices are turned on when the switching signal has a second value. 
     In an embodiment, the switching signal is a first switching signal and the current-to-voltage converter further includes a first capacitive element coupled to the first and third nodes and a second capacitive element coupled to the second and fourth nodes. The current difference determination circuit further includes a fifth switching element configured to couple the first node to a common mode voltage supply in response to a second switching signal and a sixth switching element configured to couple the second node to the common mode voltage supply in response to the second switching signal. 
     In an embodiment, the fifth and sixth switching devices are turned on when the second switching signal has a first value and turned off when the second switching signal has a second value. 
     In an embodiment, the second switching signal has substantially the same period and phase as the first switching signal. 
     In an embodiment, the apparatus further includes a storage element configured to store the first and second amplified voltage signals and output the stored first and second voltage signals in response to a clock signal. 
     In an embodiment, the storage element includes first and second sample and hold circuits, the first and second sample and hold circuits configured to store the first and second amplified voltage signals, respectively. 
     In an embodiment, the difference between the first and second currents has a linear relationship to the difference between the first and second input voltages. 
     In an embodiment, a method includes converting first and second currents into first and second input voltages to output the first and second input voltages to first and second nodes, respectively, and determining a difference between a difference between the first and second currents based on a difference between the first and second input voltages. 
     In an embodiment, the method further includes amplifying the first and second input voltages to output first and second amplified voltage signals. A first end of a first resistor and a first end of a second resistor are coupled to a power supply voltage. Determining the difference between the first and second currents includes coupling a second end of the first resistor to a first current source and coupling a second end of the second resistor to a second current source in response to a switching signal during a first time interval, and coupling the second end of the first resistor to the second current source and coupling the second end of the second resistor to the first current source in response to the switching signal during a second time interval. 
     In an embodiment, a first switching device couples the first resistor to the first current source and a second switching device couples the first resistor to the second current source, and a third switching device couples the second resistor to the first current source and a fourth switching device couples the second resistor to the second current source. 
     In an embodiment, the first and fourth switching devices are turned on and the second and third switching devices are turned off when the switching signal has a first value. The first and fourth switching devices are turned off and the second and third switching devices are turned on when the switching signal has a second value. 
     In an embodiment, converting the first and second currents includes applying a first differential voltage at the second end of the first resistor to a first end of a first capacitive element and applying a second differential voltage at the second end of the second resistor to a first end of a second capacitive element. Determining the difference between the first and second currents further includes coupling a second end of the first capacitive element and a second end of the second capacitive element to a common mode voltage supply in response to a second switching signal during the first time interval and decoupling the second end of the first capacitive element and the second end of the second capacitive element from the common mode voltage supply in response to the second switching signal during the second time interval. 
     In an embodiment, the second end of the first capacitive element and the second end of the second capacitive element are coupled to and decoupled from the common mode voltage supply when the second switching signal has a first value and a second value, respectively. 
     In an embodiment, the second switching signal has substantially the same period and phase as the first switching signal. 
     In an embodiment, the method further includes storing the first and second amplified voltage signals and outputting the stored first and second voltage signals in response to a clock signal. 
     In an embodiment, the first amplified voltage signal is stored in a first sample and hold circuit and the second amplified voltage signal is stored in a second sample and hold circuit. 
     In an embodiment, the difference between the first and second currents has a linear relationship to the difference between the first and second input voltages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a current control system including a current comparator and a current controller. 
         FIG. 2A  is a circuit diagram for a current comparator included in the system of  FIG. 1  according to an embodiment.  FIG. 2B  illustrates waveforms related to an operation of the circuit shown in  FIG. 2A  according to an embodiment. 
         FIG. 3  illustrates an operation of the current-to-voltage converter shown in  FIG. 2A  according to an embodiment. 
         FIG. 4  is a flowchart illustrating a process for measuring a current difference according to an embodiment. 
         FIG. 5  illustrates a process of converting first and second currents into first and second input voltages according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a current control system  100  including a current generator  110 , a current comparator  1 - 200 , and a current controller  150 . In an embodiment, the current control system  100  is used in a communication device including a zero-intermediate frequency transmitter. 
     The current comparator  1 - 200  receives a plurality of currents  120  from the current generator  110 , converts the currents  120  into a plurality of voltages, and compares the converted voltages to output a comparison signal  130 . In an embodiment, the comparison signal  130  indicates differences between one or more selected pairs of the received currents  120 . 
     The current controller  150  receives the comparison signal  130  and outputs a control signal  140  to the current generator  110  based on the comparison signal  130 . In an embodiment, the comparison signal  130  is used to generate a plurality of bias currents having substantially the same magnitude. 
     The current generator  110  receives the control signal  140  and adjusts one or more values of the plurality of currents  120  based on the control signal  140 . In an embodiment, the current generator  110  includes a plurality of current sources. 
       FIG. 2A  is a circuit diagram for a current comparator  2 - 200  included in the current control system  100  of  FIG. 1  according to an embodiment. The current comparator  2 - 220  includes a current-to-voltage converter  201 , a current difference determination circuit  202 , a preamplifier  250 , and a latch  260 . 
     The current-to-voltage converter  201  converts first and second currents I 1  and I 2  into first and second input voltages V p  and V n  at nodes P and N, respectively, which are coupled to input terminals of the preamplifier  250 . The current-to-voltage converter  201  includes first and second resistors  205  and  210 , switching devices  265  and  270 , first and second current sources  275  and  280 , and first and second capacitive elements  235  and  240 . 
     The current difference determination circuit  202  includes switching devices  215 ,  220 ,  225 , and  230  to determine a current difference between the first and second currents I 1  and I 2  based on a difference between the first and second input voltages V p  and V n , as will be described below in more detail. In an embodiment, the switching devices  265  and  270  may be considered to be part of the current difference determination circuit  202  although they are explained as being part of the current-to-voltage converter  201  above. 
     The first resistor  205  is coupled to a power supply voltage V DD  and a first node N 1 . The first node N 1  is coupled to first and second switching devices  215  and  225 . The first switching device  215  couples and decouples the first resistor  205  and a first current source  275  in response to a first switching signal SW 1 . The second switching device  225  couples and decouples the first resistor  205  and a second current source  280  in response to an inverted first switching signal  SW 1   . The inverted first switching signal  SW 1    is also referred to herein as a second version of the first switching signal SW 1 . 
     The second resistor  210  is coupled to the power supply voltage V DD  and a second node N 2 . The second node N 2  is coupled to third and fourth switching devices  220  and  230 . The third switching device  220  couples and decouples the second resistor  210  and the first current source  275  in response to the inverted first switching signal  SW 1   . The fourth switching device  230  couples and decouples the second resistor  210  and the second current source  280  in response to the first switching signal SW 1 . 
     A first end of the first capacitive element  235  is coupled to the first node N 1  and a second end of the first capacitive element  235  is coupled to the third node P. In an embodiment, capacitance value of the first capacitive element  235  is sufficiently large (e.g., about 10 times of capacitance value of an input capacitance of the preamplifier  250 ) to reduce gain loss of the preamplifier  250 . In an embodiment, the capacitance value of the first capacitive element  235  is sufficiently small to render a voltage settling time at the first node N 1  is shorter than a half of the period of a clock signal (e.g., a clock signal CLK 1  to a storage element  260 ). The third node P is coupled to a first input terminal of the preamplifier  250 . The fifth switching device  265  couples and decouples the third node P and a common mode voltage supply V CM  in response to a second switching signal SW 2 . In an embodiment, the second switching signal SW 2  has substantially the same period and phase as the first switching signal SW 1 . 
     A first end of the second capacitive element  240  is coupled to the second node N 2  and a second end of the second capacitive element  240  is coupled to the fourth node N. The fourth node N is coupled to a second input terminal of the preamplifier  250 . The sixth switching device  270  couples and decouples the fourth node N and the common mode voltage supply V CM  in response to the second switching signal SW 2 . 
     Operation of the current-to-voltage converter  201  is described below in more detail with reference to  FIGS. 2B and 3 . 
     Referring to  FIG. 2B , during a first time interval φ 1 , the first switching signal SW 1  has a first value (e.g., a logic high value), and thus the inverted first switching signal  SW 1    has a second value (e.g., a logic low value). The first switching device  215  is turned on to couple the first resistor  205  to the first current source  275  while the second switching device  225  is turned off. As a result, the first current I 1  flows through the first resistor  205  and a level of the voltage V N1  at the first node N 1  is represented by Equation 1:
 
 V   N1   =V   DD   −I   1   *R   1   Equation 1.
 
In Equation 1, V DD  is the level of the power supply voltage V DD  and R 1  is a first resistance value of the first resistor  205 .
 
     During the first time interval φ 1 , the second switching signal SW 2  also has the first value (e.g., a logic high value), and thus the fifth switching device  265  is turned on to couple the second end of the first capacitive element  235  to the common mode voltage supply V CM . As a result, a voltage V C1  across the first capacitive element  235  is represented by Equation 2:
 
 V   C1   =V   N1   −V   CM   =V   DD   −I   1   *R   1   −V   CM   Equation 2.
 
     During the first time interval φ 1 , since the first switching signal SW 1  has the first value (e.g., a logic high value) and the inverted first switching signal  SW 1    has the second value (e.g., a logic low value), the fourth switching device  230  is turned on to couple the second resistor  210  to the second current source  280  while the third switching device  220  is turned off. As a result, the second current I 2  flows through the second resistor  210  and a level of the voltage V N2  at the second node N 2  is represented by Equation 3:
 
 V   N2   =V   DD   −I   2   *R   2   Equation 3.
 
In Equation 3, R 2  is a second resistance value of the second resistor  210 .
 
     During the first time interval φ 1 , the second switching signal SW 2  also has the first value (e.g., a logic high value) during the first time interval φ 1 , the sixth switching device  270  is turned on to couple the second end of the second capacitive element  240  to the common mode voltage supply V CM . Thus, a voltage V C2  across the second capacitive element  240  is represented by Equation 4:
 
 V   C2   =V   N2   −V   CM   =V   DD   −I   2   *R   2   −V   CM   Equation 4.
 
     During a second time interval φ 2 , the first switching signal SW 1  has a second value (e.g., a logic low value), and thus the inverted first switching signal  SW 1    has the first value (e.g., a logic high value). As a result, the second switching device  225  is turned on to couple the first resistor  205  to the second current source  280  while the first switching device  215  is turned off. As a result, the second current I 2  flows through the first resistor  205  and a level of the voltage V N1  at the first node N 1  is represented by Equation 5:
 
 V   N1   =V   DD   −I   2   *R   1   Equation 5.
 
     Since the second switching signal SW 2  also has the second value (e.g., a logic low value) during the second time interval φ 2 , the fifth switching device  265  is turned off to decouple the second end of the first capacitive element  235  and the common mode voltage supply V CM . The voltage V C1  across the first capacitive element  235  is represented by Equation 6:
 
 V   C1   =V   N1   −V   P   =V   DD   −I   2   *R   1   −V   P   Equation 6.
 
In Equation 6, V P  is a level of a first input voltage at the third node P coupled to the second end of the first capacitive element  235 .
 
     Since the charges stored in the first capacitive element  235  remains substantially the same, the voltage V C1  across the first capacitive element  235  as represented in Equation 6 has substantially the same level as that during the first time interval φ 1  as represented by Equation 2. Thus, equating Equations 2 and 6, the level of the first input voltage V P  at the third node P is obtained as Equation 7.
 
 V   P   =I   1   *R   1   +V   CM   −I   2   *R   1   Equation 7.
 
     During the second time interval φ 2 , the third switching device  220  is turned on to couple the second resistor  210  to the first current source  275  while the fourth switching device  230  is turned off. As a result, the first current I 1  flows through the second resistor  210  and a level of the voltage V N2  at the second node N 2  is represented by Equation 8:
 
 V   N2   =V   DD   −I   1   *R   2   Equation 8.
 
     Since the second switching signal SW 2  also has the second value (e.g., a logic low value) during the second time interval φ 2 , the sixth switching device  270  is turned off to decouple the second end of the second capacitive element  240  and the common mode voltage supply V CM . Thus, the voltage V C2  across the second capacitive element  240  is represented by Equation 9:
 
 V   C2   =V   N2   −V   N   =V   DD   −I   1   *R   2   −V   N   Equation 9.
 
In Equation 9, V N  is a level of a second input voltage at the fourth node N coupled to the second end of the second capacitive element  240 .
 
     Since the charges stored in the second capacitive element  240  remains substantially the same, the voltage V C2  across the second capacitive element  240  as represented in Equation 9 has substantially the same level as that during the first time interval φ 1  as represented by Equation 4. Thus, equating Equations 4 and 9, the level of the second input voltage V N  at the fourth node N is obtained as Equation 10:
 
 V   N   =I   2   *R   2   +V   CM   −I   1   *R   2   Equation 10.
 
     Using Equations 7 and 10, a difference between the first and second input voltages V P  and V N  is represented by Equation 11:
 
 V   P   −V   N =( I   1   *R   1   +V   CM   −I   2   *R   1 )−( I   2   *R   2   +V   CM   −I   1   *R   2 )=( I   1   −I   2 )*( R   1   +R   2 )  Equation 11.
 
According to Equation 11, the difference between the first and second input voltages V P  and V N  bears a linear relationship to a difference between the first and second currents I 1  and I 2 , regardless of the first and second resistance values R 1  and R 2  of the first and second resistors  205  and  210 . Such a linear relationship is maintained when the resistance value R 1  of the first resistor  205  is different from the resistance value R 2  of the second resistor  210 , that is, when a resistor mismatch occurs.
 
       FIG. 3  shows a difference (i.e., V P −V N ) between the first and second input voltages V P  and V N  as a function of a difference (i.e., I 2 −I 1 ) between the first and second currents I 1  and I 2 . A dashed line  310 , a solid line  320 , and a dash-dot line  330  indicate differences between the first and second input voltages V P  and V N  when a difference between the first and second resistance values R 1  and R 2  correspond to +110Ω, 10Ω, and −110Ω, respectively. 
     As shown in  FIG. 3 , the differences between the first and second input voltages V P  and V N  each maintain a linear relationship with the difference between the first and second currents I 1  and I 2 , regardless of a corresponding difference between the first and second resistance values R 1  and R 2 . As long as a linear relationship between a difference between the first and second input voltages V P  and V N  and a difference between the first and second currents I 1  and I 2  is maintained, the difference between the first and second currents I 1  and I 2  is unaffected by the resistor mismatch between the first and second resistors  205  and  210 , and thus can be measured accurately. 
     Referring back to  FIG. 2A , the first and second input terminals of the preamplifier  250  receives the first and second input voltages V P  and V N , respectively. The preamplifier  250  amplifies the received input voltages V P  and V N  to output first and second amplified voltage signals  261  and  262  to a storage element  260 . 
     The storage element  260  stores values of the first and second amplified voltage signals  261  and  262  to output stored first and second voltage signals  263  and  264  in response to a clock signal CLK 1 . In an embodiment, the storage element  260  includes a pair of sample and hold circuits, each of which samples the first and second amplified voltage signals  263  and  264  at a time (e.g., a fourth time t 4  of  FIG. 2B ) prior to a time corresponding to rising edges of the first and second switching signals SW 1  and SW 2  and outputs the sampled voltage signals  263  and  264  during the third time interval φ 3  of  FIG. 2B . 
       FIG. 4  is a flowchart illustrating a process  400  for measuring a current difference according to an embodiment. The process may be performed by a device such as the current comparator  2 - 200  of  FIG. 2 . Although the flowchart shows the process being carried out in a particular order, embodiments are not limited thereto. 
     At S 4 - 410 , first and second currents are converted into first and second input voltages to output the first and second input voltages. In an embodiment, first and second current sources generate the first and second currents, respectively. 
     At S 450 , the first and second input voltages are amplified to output first and second amplified voltage signals. In an embodiment, when the first and second input voltages are sufficiently high that amplification of the first and second input voltages is not desirable, the step S 450  may be omitted. 
     At S 470 , the first and second amplified voltage signals are stored in a storage element. In an embodiment, the storage element includes a pair of sample and hold circuits. The difference between the first and second amplified voltage signals may bear a linear relationship to a difference between the first and second currents. Thus, once such a linear relationship is obtained using various processes including a process based on calibration, the difference between the first and second currents can be determined based on the difference between the first and second amplified voltage signals. 
       FIG. 5  illustrates a process  5 - 410  of converting first and second currents into first and second input voltages according to an embodiment. 
     At S 510 , during a first time interval, a second end of a first resistor is coupled to a first current source and a second end of a second resistor is coupled to a second current source in response to a first switching signal. As a result, a first differential voltage at the second end of the first resistor is applied to a first end of a first capacitive element and a second differential voltage at the second end of the second resistor is applied to a first end of a second capacitive element. 
     At S 530 , during the first time interval, a second end of the first capacitive element and a second end of the second capacitive element are coupled to a common mode voltage supply in response to a second switching signal. In an embodiment, voltages across the first capacitive element and the second capacitive element are represented as shown in Equations 2 and 4, respectively. 
     At S 550 , during a second time interval, the second end of the first resistor is coupled to the second current source and the second end of the second resistor is coupled to the first current source in response to the first switching signal. As a result, the first differential voltage and the second differential voltage during the second time interval have different levels from those during the first time interval, respectively. 
     At S 570 , during the second time interval, the second end of the first capacitive element and the second end of the second capacitive element are decoupled from the common mode voltage supply in response to the second switching signal. In an embodiment, voltages across the first capacitive element and the second capacitive element are represented as shown in Equations 6 and 9, respectively. 
     According to an embodiment, the voltages across the first capacitive element and the second capacitive element during the first time interval remains substantially the same as those during the second time interval. As a result, a difference between first and second input voltages, which are input to a preamplifier, bears a linear relationship to a difference between the first and second currents, regardless of the resistance values and of the first and second resistors. 
     Aspects of the present disclosure have been described in conjunction with the specific embodiments thereof that are proposed as examples. Numerous alternatives, modifications, and variations to the embodiments as set forth herein may be made without departing from the scope of the claims set forth below. Accordingly, embodiments as set forth herein are intended to be illustrative and not limiting.