Abstract:
On-chip jitter testing includes providing a clock signal to a circuit under test and delaying outputs from the circuit under test by predetermined delay values. For each delay value, a corresponding output from the circuit under test is compared with a reference signal derived from the clock signal to produce a bit error rate count for each delay value. A jitter value in the output of the circuit under test is determined based on the bit error rate counts.

Description:
BACKGROUND  
         [0001]    This disclosure relates to on-chip testing for jitter in integrated circuit (“IC”) components.  
           [0002]    Jitter is the deviation of a timing event of a signal from its ideal position. Data errors result when this deviation extends past the sampling point at the receiver. A built-in self-test (“BIST”) structure is sometimes included as part of an integrated circuit to test for jitter in components of the integrated circuit. Such an on-chip testing structure allows for internal testing of integrated circuit components instead of more time-consuming external tests.  
           [0003]    Some BIST structures for jitter are based on statistical analysis of time measurement testing. These tests calculate the jitter using standard deviation computations with embedded time to digital converters (“TDC”). High accuracy using these converters may be difficult to achieve because TDCs can be sensitive to crosstalk, substrate and power supply noise. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]    [0004]FIG. 1 is an illustration of a bit cell.  
         [0005]    [0005]FIG. 2 is an illustration of a look-up table.  
         [0006]    [0006]FIG. 3 is an illustration of a BIST structure for testing jitter.  
         [0007]    [0007]FIG. 4 is an illustration of a BIST structure for testing jitter in a phase locked loop.  
         [0008]    [0008]FIG. 5 is a graph illustrating a Bit-Error-Rate. 
     
    
     DETAILED DESCRIPTION  
       [0009]    [0009]FIG. 1 is an illustration of a bit cell  3  from an IC component&#39;s output. Jitter is the deviation of a timing event of the output from its ideal position  4 . Data errors result when this deviation extends past the sampling point  6  at which the signal is read. If there are several short bits in a row the sample point will eventually occur on an edge  2 , resulting in bit errors.  
         [0010]    There are different types of jitter. Total jitter is the convolution of all independent jitter processes; deterministic, or systematic, jitter and random, or non-systematic, jitter. Deterministic jitter is due to non-Gaussian processes and has a bounded amplitude and a specific cause. Deterministic jitter may include jitter resulting from duty cycle distortion, data dependent jitter (e.g., inter-symbol interference-ISI), sinusoidal jitter, and un-correlated (to the data) bounded jitter. Deterministic jitter is measured as a peak-to-peak value and sums linearly.  
         [0011]    Random jitter is characterized by a Gaussian distribution and is assumed to be unbounded. It is often measured in root-mean-square value, which equals the standard deviation (σ) in a Gaussian process.  
         [0012]    Because random jitter can be modeled as a Gaussian distribution it can be used to predict peak-to-peak jitter as a function of a bit error rate (“BER”).  
         [0013]    [0013]FIG. 2 shows exemplary total jitter values  10  that correspond to various bit error rates  12 . Conversely, the BER values  12  can be used as a measurement of total jitter  10 .  
         [0014]    [0014]FIG. 3 shows a BER based built-in self-test (“BIST”) structure  14  for jitter. A clock signal  16  may be generated and provided as an input the circuit under test (“CUT”)  18 . The output of the CUT  18  is subject to a delay line  20  that has predetermined delay values. For each delay value, additional circuitry  24  compares the delayed output of the CUT  18  with a reference signal  22  derived from the clock signal  16 . Based on this comparison, the recovery and bit error rate circuitry  24  produces a BER count that can be used to determine jitter values.  
         [0015]    The delay line  20  is used to simulate jitter contribution in a system cascade in which the CUT  18  is inserted. Delaying the clock signal  16  under test edge so it becomes closer to the reference edge makes more jitter values appear as bit errors. For example, if the delay line  20  is adjusted so that the difference between the delayed CUT output and reference signal  22  equals a specified intrinsic jitter RMS value, the number of bit errors obtained can be interpreted as the BER that the circuit would yield in a cascade that contributes jitter near the specified value.  
         [0016]    [0016]FIG. 4 illustrates a BER-based BIST structure  26  for jitter in a phase-locked loop (“PLL”) circuit  28 . A clock signal  30  is provided to the phase-locked loop circuit  28  which, in this example, is the integrated circuit component under test. The output of the phase-locked loop circuit  28  is subject to a delay line  32 . The delay line&#39;s voltage may be varied increasingly from zero and its output is fed to recovery and bit error rate circuitry  34 . A reference signal derived from the clock signal  30  also is provided to the other circuitry  34 . The other circuitry  34  compares the two inputs and records errors due to jitter. A clock delay line  38  with a fixed delay value can be introduced between the clock signal  30  and the circuitry  34  to make the delay between the clock edges large enough to be measured.  
         [0017]    The different delay values of the delay line  32  may be characterized prior to any measurements using a ring oscillator circuit into which the delay line is inserted. For every step of the delay line&#39;s value variations, bit errors are counted by the recovery and BER circuitry  34  during a fixed interval of time. These counts can be used to create a graph representing the number of errors as a function of the delay between the two clocks.  
         [0018]    [0018]FIG. 5 shows an exemplary graph  42  representing a BER. In this example the graph  42  has a ‘bathtub’ pattern. A The graph  42  can also be viewed as a cumulative distribution function (“CDF”), which is a function of the probability density function (“PDF”) that corresponds to a histogram obtained using time interval measurements in testing for jitter.  
         [0019]    If the jitter has a normal distribution, the standard deviation of the time interval to be measured can be computed as a difference between the times that correspond to 84% and 64% of the final CDF value. To interpret the results, a lookup table such as the one shown in FIG. 2 can be used to generate a BER curve for each delay value.  
         [0020]    Various features of the system may be implemented in hardware, software or a combination of hardware and software. For example, some aspects of this disclosure can be implemented in computer programs executing on programmable computers. Each program can be implemented in a high level procedural or object-oriented programming language to communicate with a computer system. Furthermore, each such computer program can be stored on a storage medium, such as read only memory (“ROM”) readable by a general or special purpose programmable computer, for configuring and operating the computer when the storage medium is read by the computer to perform the functions described above.  
         [0021]    Other implementations are within the scope of the following claims.