Abstract:
An isolated switching regulator has a closed-loop soft-start feature that allows tighter regulation of the output voltage and eliminates or reduces overshoot. It also has an optional reset feature which will resoft-start the regulator during recovery from a fault on the output voltage.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. application Ser. No. 60/980,691 filed on Oct. 17, 2007, which is incorporated herein in its entirety by reference. 
    
    
     FIELD OF THE INVENTION 
     This application relates to isolated switching regulators and more specifically to a soft-start circuit for such regulators. 
     BACKGROUND OF THE INVENTION 
     Isolated switching regulators are commonly used in consumer devices with high input voltages to convert them to lower voltages required by subsystems and safely separate users from hazardous high voltages. The isolation is usually provided by using transformer in power stage and opto-coupler in feedback path as shown in  FIG. 1  for an example of an isolated flyback topology. The circuit is therefore divided to primary and secondary sides. While primary side contains gate drive, PWM comparator, and over current protection circuits, secondary-side circuit contains error amplifier and reference voltage. However, because of isolation required, secondary and primary side cannot be integrated in a single integrated circuit (IC). 
     Traditionally, a discrete solution such as an adjustable shunt regulator circuit (TL431 family) is used to function as the secondary-side controller (i.e., a bandgap and an error amplifier).  FIG. 2  shows how a shunt regulator circuit is typically used as the secondary side controller in an isolated converter such as an isolated flyback. In this circuit, resistors R 1  and R 2  and capacitor C c  are loop compensation elements and resistor R 3  is used to set the output voltage (i.e., V out =(1+R 1 /R 3 )V BG , where V BG  is 1.24V bandgap voltage). The primary side usually is implemented as a current-mode PWM converter, and its basic block diagram is shown in  FIG. 2 . To simplify the compensation and increase its robustness, in addition to current- and voltage-loops, a feed-forward path is added through opto-coupler input diode anode. More detailed information on compensation and secondary-side control with shunt regulator circuit devices is shown in  FIG. 3 . Although illustrated as a flyback converter, these shunt regulator circuits can be used for other isolated topologies such as a forward converters. 
     Discrete solutions such as shown, however, can not provide closed loop soft start to tightly control output voltage V out  during startup sequence. Available solutions with shunt regulators usually use open loop soft-start schemes that control some other voltage or current during the startup such as clamping the V opto  cathode voltage (V opto ) at startup or limiting the transformer current at primary IC. However, since these techniques control V out  indirectly (e.g., open loop), V out  may experience overshoot during startup (i.e., non monolithic startup). The problem worsens for lower V out  values. The cathode voltage of shunt regulator (V opto  in  FIG. 2 ) needs minimum of 1.24V for operation, assuming 1V drop for opto coupler diode, and 0.75V on bias resistor R opto1 , TL431 starts taking over the loop control only when V out  has reached about 3V. This can cause soft-start problems if V out  final value is set at 3.3V. 
     It is also known to use an open-loop soft-start circuit using discrete components, as shown in  FIG. 4 . This circuit utilizes resistor R 13 , capacitor C 18  and diode D 9  to implement the open-loop soft-start circuit. Note that this circuit does not compare the output voltage with a reference during start up, so that closed-loop control is not possible. 
     SUMMARY OF THE INVENTION 
     It is a general object of the invention to provide an improved soft-start circuit for an isolated switching regulator. 
     This and other objects and features are attained in accordance with an aspect of the invention by an isolated switching regulator comprising an input side of a first isolating device, the input side circuit generating a switched voltage across the first isolation device. An output side circuit coupled to an output side of the isolating device, the output side circuit generating control signals to control the input side circuit to generate a regulated output voltage. A second isolating device coupled between the output side circuit and the input side circuit for conveying the control signals generated by the output side circuit to the input side circuit, wherein the output side circuit comprises a closed-loop soft-start circuit. 
     Another aspect of the invention includes a closed-loop soft-start circuit in an isolated switching regulator comprising a primary side circuit coupled via a first isolating device to a secondary side circuit, the secondary side circuit transmitting control signals to the primary side circuit via a second isolating device. A closed-loop soft-start circuit generating control signals during startup of the isolated switching regulator once an output voltage reached substantially 2V T +VdSSAT of the transistors comprising the soft-start circuit where V T  is the threshold voltage and Vdd sat is the drain to source voltage to place an MOS device in saturation and a second isolating device to transmit the control signals to the primary side circuit for controlling the output voltage. 
     A further aspect comprises an isolated switching regulator comprising a primary winding of a transformer and generating a switched voltage across the transformer primary winding for generating a regulated voltage at an output of the switching regulator. A secondary side circuit coupled to a secondary winding of the transformer for generating control signals to control the primary side circuit to generate the regulated voltage at the output of the switching regulator. An opto-coupler coupled to a control input of the primary side circuit and a control output of the secondary side circuit for transmitting the control signals from the secondary side circuit to the primary side circuit. A closed-loop soft-start circuit able to start closed-loop control of the primary side circuit to regulate the output voltage when the output voltage reaches substantially 2V T +Vd ssat of the transistors of the soft-start circuit, where V T  equals the threshold voltage and VdSSAT equals the drain to source voltage to place an MOS device in saturation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an isolated switching regulator; 
         FIG. 2  is a block diagram of a prior art isolated regulator having an open-loop soft-start circuit; 
         FIG. 3  is a schematic diagram of the circuit shown in the block diagram of  FIG. 2 ; 
         FIG. 4  shows an open-loop soft-start circuit; 
         FIG. 5  is a schematic diagram of an isolated switching regulator according to the present invention; 
         FIG. 6  is a more detailed schematic of the circuit generating the secondary side soft-start ramp; 
         FIG. 7  is a schematic diagram of the error amplifier circuit; 
         FIG. 8  shows the secondary side circuit integrated within a power management integrated circuit; 
         FIG. 9  shows a circuit implementation of a dual reference; 
         FIG. 10  shows the output and soft-start pin voltages; and 
         FIG. 11  shows a stable plateau region. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Our solution proposes a closed loop soft-start scheme to tightly control the output voltage at startup. The circuit consists of an error amplifier Amp 1 , pull down transistor M out , a low-voltage bandgap circuit, and a minimum detection circuit choosing between the lower of soft-start ramp and bandgap reference ( FIGS. 5 and 6 ). Since supply voltage for BG and error amplifier (V supply ) and pull down transistor output (V opto ) are separate in proposed topology and V opto  can be driven close to zero, the circuit can start regulating for V out  as low as 1.8V (worst case) or as low as 1.5V (typical). 
     The soft-start procedure is as follows. Before V in  is applied to primary IC, V out  is at zero. When V in  is applied to primary, primary FB node is high through a pull down resistor, since there is no control yet from secondary side. Therefore, primary side IC starts switching transistor M 1  with high duty cycle. Usually, a current limit function is placed in primary IC to limit the current at startup. Output voltage V out  starts to rise with almost no control from secondary side until the voltage is raised enough for secondary side to regulate (about 1.8V). At this point, error amplifier Amp 1  tries to regulate FB SS  node to minimum of bandgap voltage V REF  and soft-start ramp V SS . In early phase of startup, V SS  is lower than V REF  and secondary side regulates the output voltage to V SS . Since V SS  starts from zero, V opto  is pulled down to ground and FB node is pulled low. However, the loop usually is designed such that FB node at the input of primary circuit does not reach zero even when opto input is pulled to the ground, and circuit finds a stable point through its current feedback loop where V out  sits at a voltage V plateau , which is a function of loop components specifically R opto2  This is described below in connection with  FIG. 11 . Output voltage V out  sits at V plateau  until V SS  rises above V plateau (R 3 /(R 3 +R 1 )). At this point, V out  starts to rise again since FB SS  is following rising V SS . Once V SS  goes above V REF , FB SS  is regulated to V BG . V SS  rises and finally is clamped to about 2.2V. 
       FIG. 6  shows more of implementation details of the secondary side soft-start ramp. A low-voltage current source generated in low-voltage bandgap unit charges the capacitor C SS  once V supply (V out ) rises enough for circuit to operate. The capacitor is discharged through internal leakage resistor R leak  when power supply is disconnected. To start V SS  at a non-zero voltage, resistors R SSint and  R SSext  are added. The shape and timing of soft-start ramp and consequently V out  startup can be adjusted by selection of C SS  and R SSext . 
       FIG. 7  shows circuit implementation of error amplifier, minimum function, and output pull down transistor. The minimum function is embedded in input stage of the error amplifier by paralleling transistors M 2  and M SS . The transistor that has the lowest voltage at its gate forms the input stage with transistor M 1 . Therefore, on system, FB SS  node is regulated to the lower of V REF  and V SS . The amplifier is a symmetrical OTA with a common source output stage consisting of transistor M out  and external resistor R opto1 . 
     As another advantage, the proposed secondary side amplifier can be integrated inside the power management IC that usually follow primary regulator in the system ( FIG. 8 ). In these applications, the high voltage of source is first stepped down safely through an isolated regulator and then this intermediate voltage is converted to voltage rails required in the system. 
     Integration of secondary side controller in power management IC enables implementation of other features. For example, reference voltage can be switched to a more accurate reference, once V out  is raised enough. Usually, low voltage bandgap are less accurate and has lower power supply rejection ratio. Therefore, the idea is to soft start the system with a low voltage but low accuracy bandgap and then switch to a higher performance reference, which requires more headroom ( FIG. 9 ). 
     Restarting the soft-start is another feature that can be implemented on proposed secondary side circuit once it is integrated in the system. When V out  has reached its final value after startup, faults such as overload or shorts at the output can bring down the output voltage. Although circuit restarts after the fault is removed, soft start may not reinitiate since there may not be enough time for R leak  to discharge soft-start capacitor. Transistor M RST  is added to discharge the capacitor C SS  and re soft-start the converter when RE_SOFT_START signal is toggled high. RE_SOFT_START signal can be generated by supervisory circuits that monitor V out  such as under voltage level. 
       FIG. 10  shows the measurement results for an isolated flyback circuit controlled by the proposed secondary side amplifier and soft-start. Channel  3  shows soft start pin (V SSext ) and Channel  2  shows the output voltage waveform. Upon power up, V ssext  ramps from zero until it is clamped at about 2V. As explained before, V out  is first ramped up by a rate controlled by current limit of primary side until it exceeds headroom requirements of secondary side circuits. At this point, secondary side takes over. Because of loop setup and since it takes time for soft start ramp to reach initial V out  value, V out  sits on constant voltage of V plateau  until V ss  catches up (Time period of which V out  stays at V plateau  can be adjusted and totally eliminated through selection of R SS ). At this point, V out  follows soft start ramp, and the slope is a function of C ss  value and soft-start charging current. When V ss  exceeds bandgap voltage V ref , secondary side regulates FB SS  to V ref  or equivalently V out  to (1+R 1 /R 3 )V REF . The jump in V out  toward the end of the waveforms is when V REF  is switched to more accurate bandgap. 
     For most of available isolated regulator loops, even when the opto coupler input-side cathode is grounded, the output voltage regulates to a stable point V plateau  ( FIG. 10 ) determined by loop components. This phenomenon further explained for a simplified isolated loop shown in  FIG. 11 . The loop tries to make the signals at the input of primary side PWM comparator equal. Therefore,
 
R sense I Lmax =V FB ,  (1)
 
     where R sense  is the current-sensing gain and I Lmax  is the transformer primary side current peak. The loop is usually designed in a way that even when the opto coupler diode cathode is grounded, the V FB  node is not at zero, but is pulled down to 
                 V   DD     -       (       V   out     -     V   diode       )     ⁢       R     opto   ⁢           ⁢   2         R     opto   ⁢           ⁢   1             ,         
where V diode  is the opto coupler input diode voltage, V DD  is the reference voltage from primary IC (usually 5V), and opto coupler gain is assumed to be one. Therefore, V out  finds a stable point to satisfy the following condition
 
     
       
         
           
             
               
                 
                   
                     
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     Since for a converter working in continuous-time PWM operation, I Lmax  can be specified as a function of input voltage, output voltage, and the load or equivalently I Lmax =f( Vout ). Therefore, V out  regulates to a stable point determined by loop components such as current-sensing gain, VDD voltage, and opto coupler resistor ratio (i.e., V out     —     Plateau =f(R opto2 /R opto1 , R sense , V DD )). Other loop parameters affect the plateau voltage only as second-order effects. For TI isolated flyback boards, R opto2 /R opto1 =2, V DD =5V, and V out     —     Plateau =2.4V. 
     Advantages of the present invention include a closed loop soft-start for isolated regulators thereby providing closer control over the output voltage and lower headroom requirement for secondary side amplifier compared to prior art shunt regulators, seamless transition from soft-start to normal operation (i.e., implementation of minimum function using transistors M 2  and M SS  in  FIG. 7 ). It also provides control over duration of V plateau  region. Adding resistor R SS  in series with soft-start capacitor causes soft start ramp to start higher than zero and therefore soft-start ramp reaching plateau voltage sooner. Adding enough R ss  can totally eliminate plateau region and result in monolithic startup. The addition of re soft-start feature (RE_SOFT_START) and switching from a crude but low-voltage bandgap to accurate, high performance bandgap when V out  has raised close to its final value. 
     Although the present invention has been described with reference to a specific embodiment, it is not limited to this embodiment and no doubt alternatives will occur to the skilled person that lie within the scope of the invention as claimed.