Abstract:
A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This is a continuation application of an application Ser. No. 11/776,562, filed Jul. 12, 2007, now pending, which is a divisional application of U.S. Pat. No. 7,485,517 filed Apr. 7, 2006. The entirety of the above-mentioned patent application and patent are hereby incorporated by reference herein and made a part of this specification. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to an integrated circuit component and a method for fabricating the same, and more particularly, to a semiconductor device and a method for fabricating the same. 
       BACKGROUND OF THE INVENTION 
       [0003]    In the development of the integrated circuit components, high speed and low power electricity consumption are achieved by reducing the size of the component. However, the technique of reducing the component size is limited by the fabrication technique and high cost, thus a new technique of reducing the component size is desired to improve the device driving current. Accordingly, a method of using the stress control had been proposed to overcome the limitation of reducing the component size. 
         [0004]    In a conventional method of using the stress control for improving the device performance, a high tensile or high compression silicon nitride layer used as a contact etching stop layer (CESL) is selectively formed on the substrate according to the N-channel or P-channel to improve the device driving current. 
         [0005]    However, the method of improving the device performance by using the stress layer still leaves some problems. In general, a compressive stress layer is formed on the P-channel device to improve the current gain and efficiency of the device. However, for some P-channel device, the device reliability is degraded. For example, if a compressive stress layer is formed on the input/output (I/O) P-channel MOS transistor (metallic oxide semiconductor field effect transistor), a threshold voltage (Vt) shift effect occurs, which would slow the negative bias temperature instability (NBTI), and further reduce the current gain and affect the device performance. 
       SUMMARY OF THE INVENTION 
       [0006]    Therefore, it is an object of the present invention to provide a semiconductor device which can avoid the negative bias temperature instability (NBTI) degradation, such as to reduce the current gain and affects the device performance. 
         [0007]    It is another object of the present invention to provide a semiconductor device that can avoid the negative bias temperature instability (NBTI) degradation, such that the device performance is improved. 
         [0008]    The present invention provides a semiconductor device, which comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress lay and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/o MOS transistor and without not only the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor. 
         [0009]    In accordance with a preferred embodiment of the present invention, if the first-type MOS transistor is an N-channel MOS (NMOS) transistor and the I/O second-type MOS transistor and the core second-type MOS transistor are P-channel MOS (PMOS) transistors, the first stress layer is a tensile stress layer and the second stress layer is a compressive stress layer. 
         [0010]    In accordance with a preferred embodiment of the present invention, if the first-type MOS transistor is a P-channel MOS (PMOS) transistor and the I/O second-type MOS transistor and the core second-type MOS transistor are N-channel MOS (NMOS) transistors, the first stress layer is a compressive stress layer and the second stress layer is a tensile stress layer. 
         [0011]    In accordance with a preferred embodiment of the present invention, the first stress layer is made of a material comprising silicon nitride. 
         [0012]    In accordance with a preferred embodiment of the present invention, the second stress layer is made of a material comprising silicon nitride. 
         [0013]    The present invention further provides a semiconductor device. The semiconductor device comprises a substrate, a first stress and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) MOS transistor of second-type, and a core MOS transistor of second-type formed thereon. Wherein the first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is disposed on at least the first-type MOS transistor but not the core MOS transistor. The second stress layer is different from the first stress layer and is disposed on the core MOS transistor but not the first-type MOS transistor, and is further disposed on the I/O MOS transistor if the I/O MOS transistor overlaid by the first stress layer. Wherein one of the first stress layer and the second stress layer is a tensile layer and the other one of the first stress layer and the second stress layer is a compressive layer. 
         [0014]    The present invention further provides a semiconductor device, which comprises a substrate, a first stress layer and a second stress layer. The substrate has a first-type MOS transistor, an input/output (I/O) MOS transistor of second-type, and a core MOS transistor of second-type formed thereon. The first stress layer is disposed on the first-type MOS transistor and the I/O MOS transistor. The second stress layer is different from the first stress layer, and is disposed on the core MOS transistor. The first stress layer disposed on the I/O MOS transistor comprises a plurality of broken Si—H links and H+ are moving out of the first stress layer, upon the application of a negative bias on the substrate. 
         [0015]    In accordance with a preferred embodiment of the present invention, each of the first stress layer and the second stress layer is one of a tensile stress layer and a compressive stress layer determined by conductivity types of the first-type and the second-type. 
         [0016]    According to the present invention, a tensile stress layer, a tensile stress layer and a compressive stress layer, or nothing, is formed on the I/O second-type MOS transistor. When the negative bias is applied on the substrate, H+ is not accumulated in the gate dielectric layer, thus the threshold voltage (Vt) shift effect does not occur. In other words, the negative bias temperature instability (NBTI) degradation in the conventional technique is effectively avoided. On the other hand, the method of the present invention does not increase the quantity of the photomasks used in the fabricating process, thus the present invention does not increase any additional fabricating cost. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
           [0018]      FIG. 1A-1D  are cross-sectional views illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. 
           [0019]      FIG. 2  is a cross-sectional view illustrating a method for fabricating a semiconductor device according to another embodiment of the present invention. 
           [0020]      FIG. 3A-3B  are the cross-sectional views illustrating a method for fabricating a semiconductor device according to yet another embodiment of the present invention. 
           [0021]      FIG. 4  is a diagram illustrating the relationship of the stress time and the threshold voltage shift amount of the semiconductor device in the present invention and in the conventional technique. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0022]    The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
         [0023]      FIG. 1A-1D  are cross-sectional views illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. 
         [0024]    First, referring to  FIG. 1A , a substrate  100  is provided. A first-type MOS transistor  102 , an input/output (I/O) second-type MOS transistor  104 , and a core second-type MOS transistor  106  are formed on the substrate  100 . In addition, the first-type MOS transistor  102 , the I/O second-type MOS transistor  104 , and the core second-type MOS transistor  106  are separated from each other by an isolation structure  108 . Here, the isolation structure  108  may be a shallow trench isolation (STI) structure. 
         [0025]    The I/O second-type MOS transistor  104  is an input/output (I/O) MOS transistor, and the core second-type MOS transistor is a core MOS transistor. Wherein, the first-type MOS transistor  102  may be an N-channel MOS (NMOS) transistor, and the I/O second-type MOS transistor  104  and the core second-type MOS transistor  106  may be P-channel MOS (PMOS) transistors. The first-type MOS transistor  102  comprises a gate dielectric layer  102   a,  a polysilicon layer  102   b,  a source/drain region  102   c,  and a spacer  102   d.  The I/O second-type MOS transistor  104  comprises a gate dielectric layer  104   a,  a polysilicon layer  104   b,  a source/drain region  104   c,  and a spacer  104   d.  The core second-type MOS transistor  106  comprises a gate dielectric layer  106   a,  a polysilicon layer  106   b,  a source/drain region  106   c,  and a spacer  106   d.    
         [0026]    In an embodiment, a metal silicide layer (not shown) is formed on the polysilicon layers  102   b,    104   b,    106   b  and the source/drain regions  102   c,    104   c,    106   c  to reduce the resistance, and the metal silicide layer is made of NiSi, WSi or CoSi. In another embodiment, a silicon oxide spacer (not shown) is formed on the sidewalls of the polysilicon layers  102   b,    104   b,    106   b  based on the fabrication requirement. 
         [0027]    The material and forming method of the first-type MOS transistor  102 , the I/O second-type MOS transistor  104 , and the core second-type MOS transistor  106  are known to one of the ordinary skills in the art, thus its detail is omitted herein. 
         [0028]    Then, referring to  FIG. 1B , a first stress layer  110  is formed on the substrate  100  to overlay the substrate  100 , the first-type MOS transistor  102 , the I/O second-type MOS transistor  104 , and the core second-type MOS transistor  106 . Here, the first stress layer  110  is a tensile stress layer that is made of a material such as silicon nitride or other appropriate dielectric layer and formed by a plasma-enhanced chemical vapor deposition (PECVD) method or other appropriate method. 
         [0029]    Then, referring to  FIG. 1C , the first stress layer  110  on the core second-type MOS transistor  106  is removed to form a first stress layer  110 ′. The method for removing the first stress layer  110  on the core second-type MOS transistor  106  comprises: forming a patterned photomask layer (not shown) on the first stress layer  110  to expose the first stress layer  110  on the core second-type MOS transistor  106 ; and performing an etching process to remove the first stress layer  110  that is not overlaid by the patterned photomask layer to form the first stress layer  110 ′. 
         [0030]    Then, referring to  FIG. 1D , a second stress layer  112  is formed on the core second-type MOS transistor  106 . Here, the second stress layer  112  is a compressive stress layer that is made of a material such as silicon nitride or other appropriate dielectric layer. The method for forming the second stress layer  112  comprises: forming a stress material layer (not shown) on the first stress layer  110 ′ and the core second-type MOS transistor  106  by using a plasma-enhanced chemical vapor deposition (PECVD) method or other appropriate method; forming a patterned photomask layer (not shown) on the stress material layer to expose the first stress layer  110 ′ on the first-type MOS transistor  102  and the I/O second-type MOS transistor  104 ; and using the patterned photomask as a mask to perform an etching process in order to remove the stress material layer on the first stress layer  110 ′, such that the second stress layer  112  is formed. 
         [0031]    In summary, in the present invention, a tensile stress layer is formed on the I/O second-type MOS transistor (i.e. the I/O MOS transistor). Thus, when the negative bias is applied on the substrate, the Si—H link in the stress layer is broken, and H+ is moving out of the tensile stress layer and not accumulated in the gate dielectric layer, thus the threshold voltage (Vt) shift effect does not occur. In other words, the negative bias temperature instability (NBTI) degradation does not occur anymore. 
         [0032]    In addition to the embodiments mentioned above, the present invention may be implemented in different ways.  FIG. 2  is a cross-sectional view illustrating a method for fabricating a semiconductor device according to another embodiment of the present invention. The method described in  FIG. 2  is performed subsequent to the embodiment in  FIG. 1C . The same reference numbers are used in  FIG. 1A ,  1 B and  2 , and its detail is omitted herein. 
         [0033]    Referring to  FIG. 2 , after the first stress layer  110 ′ is formed, a second stress layer  112 ′ is formed on the I/O second-type MOS transistor  104  and the core second-type MOS transistor  106 . Here, the second stress layer  112 ′ is a compressive stress layer that is made of a material such as silicon nitride or other appropriate dielectric layer. The method for forming the second stress layer  112 ′ comprises: forming a stress material layer (not shown) on the first stress layer  110 ′ and the core second-type MOS transistor  106  by using a plasma-enhanced chemical vapor deposition (PECVD) method or other appropriate method; forming a patterned photomask layer (not shown) on the stress material layer to expose the first stress layer  110 ′ on the first-type MOS transistor  102 ; and using the patterned photomask as a mask to perform an etching process in order to remove part of the stress material layer, such that the second stress layer  112 ′ is formed. 
         [0034]      FIG. 3A-3B  are cross-sectional views illustrating a method for fabricating a semiconductor device according to yet another embodiment of the present invention. The method described in  FIG. 3A  is performed subsequent to the embodiment in  FIG. 1B . The same reference numbers are used in  FIG. 3A ,  3 B,  1 A and  1 B, and its detail is omitted herein. 
         [0035]    Referring to  FIG. 3A , after the first stress layer  110  is formed, the first stress layer  110  on the core second-type MOS transistor  106  and the I/O second-type MOS transistor  104  is removed to form a first stress layer  110 ″. The method for removing the first stress layer  110  on the core second-type MOS transistor  106  and the I/O second-type MOS transistor  104  comprises: forming a patterned photomask layer (not shown) on the first stress layer  110  to expose the first stress layer  110  on the core second-type MOS transistor  106  and the I/O second-type MOS transistor  104 ; and performing an etching process to remove the first stress layer  110  that is not overlaid by the patterned photomask layer to form the first stress layer  110 ″. 
         [0036]    Then, referring to  FIG. 3B , a second stress layer  112 ″ is formed on the I/O second-type MOS transistor  104  and the core second-type MOS transistor  106 . Here, the second stress layer  112 ″ is a compressive stress layer that is made of a material such as silicon nitride or other appropriate dielectric layer. The method for forming the second stress layer  112 ″ comprises: forming a stress material layer (not shown) on the first stress layer  110 ″, the I/O second-type MOS transistor  104 , and the core second-type MOS transistor  106  by using a plasma-enhanced chemical vapor deposition (PECVD) method or other appropriate method; forming a patterned photomask layer (not shown) on the stress material layer to expose the first stress layer  110 ″ and the I/O second-type MOS transistor  104 ; and using the patterned photomask as a mask to perform an etching process in order to remove part of the stress material layer, such that the second stress layer  112 ″ is formed. 
         [0037]    Similarly, in the present invention, a tensile stress layer and a compressive stress layer, or nothing, is formed on the I/O second-type MOS transistor (i.e. the I/O MOS transistor). When the negative bias is applied on the substrate, H+ is not accumulated in the gate dielectric layer, thus the threshold voltage (Vt) shift effect does not occur. In other words, the negative bias temperature instability (NBTI) degradation in the conventional technique is effectively avoided. 
         [0038]    In the embodiments mentioned above, the first-type MOS transistor  102  is an N-channel MOS (NMOS) transistor, the I/O second-type MOS transistor  104  and the core second-type MOS transistor  106  are P-channel MOS (PMOS) transistors, the first stress layers  110 ,  110 ′,  110 ″ are tensile stress layers, and the second stress layers  112 ,  112 ′,  112 ″ are compressive stress layers. However, the transistors and the stress layers mentioned above only serve for describing the present invention and should not be limited thereto. In another embodiment, the first-type MOS transistor  102  is a P-channel MOS (PMOS) transistor, the I/O second-type MOS transistor  104  and the core second-type MOS transistor  106  are N-channel MOS (NMOS) transistors, the first stress layers  110 ,  110 ′,  110 ″ are compressive stress layers, and the second stress layers  112 ,  112 ′,  112 ″ are tensile stress layers. 
         [0039]    A semiconductor device obtained by the method for fabricating the semiconductor device provided by the present invention is described in detail hereinafter. 
         [0040]    Referring to  FIG. 1D , the semiconductor device of the present invention comprises a substrate  100 , a first stress layer  110 ′, and a second stress layer  112 . Wherein, a first-type MOS transistor  102 , an I/O second-type MOS transistor  104 , and a core second-type MOS transistor  106  are formed on the substrate. The first stress layer  110 ′ is disposed on the first-type MOS transistor  102  and the I/O second-type MOS transistor  104 , and the first stress layer  110 ′ is made of a material such as silicon nitride or other appropriate dielectric layer. The second stress layer  112  is disposed on the core second-type MOS transistor  106 , and the second stress layer  112  is made of a material such as silicon nitride or other appropriate dielectric layer. 
         [0041]    In addition, referring to  FIG. 2 , the semiconductor device of the present invention comprises a substrate  100 , a first stress layer  110 ′, and a second stress layer  112 ′. Wherein, a first-type MOS transistor  102 , an I/O second-type MOS transistor  104 , and a core second-type MOS transistor  106  are formed on the substrate. The first stress layer  110 ′ is disposed on the first-type MOS transistor  102  and the I/O second-type MOS transistor  104 , and the first stress layer  110 ′ is made of a material such as silicon nitride or other appropriate dielectric layer. The second stress layer  112 ′ is disposed on the core second-type MOS transistor  106  and the I/O second-type MOS transistor  104  that overlays the first stress layer  110 ′, and it is made of a material such as silicon nitride or other appropriate dielectric layer. 
         [0042]    Moreover, referring to  FIG. 3B , the semiconductor device of the present invention comprises a substrate  100 , a first stress layer  110 ″, and a second stress layer  112 ″. Wherein, a first-type MOS transistor  102 , an I/O second-type MOS transistor  104 , and a core second-type MOS transistor  106  are formed on the substrate. The first stress layer  110 ″ is disposed on the first-type MOS transistor  102  and made of a material such as silicon nitride or other appropriate dielectric layer. The second stress layer  112 ″ is disposed on the core second-type MOS transistor  106  and made of a material such as silicon nitride or other appropriate dielectric layer. 
         [0043]    Please refer to  FIG. 4  for verifying the effect of the present invention.  FIG. 4  is a diagram illustrating the relationship of the stress time and the threshold voltage shift amount of the semiconductor device in the present invention and in the conventional technique. 
         [0044]    Referring to  FIG. 4 , the objects to be tested in the diagram are: 
         [0045]    a semiconductor device on which a compressive stress layer is formed on an I/O second-type MOS transistor (represented by symbol □); a semiconductor device on which a low stress layer is formed on an I/O second-type MOS transistor (represented by symbol ♦); and a semiconductor device on which a tensile stress layer is formed on an I/O second-type MOS transistor (represented by symbol Δ). Under the constant voltage condition, the test is performed on the objects to obtain the threshold voltage shift amount (ΔVt) in response to the variance of the stress time. It is known from the relationship between the stress time and the threshold voltage shift amount, when the stress time gradually increases, the threshold voltage shift amount of the semiconductor device on which the low stress layer or the tensile stress layer is formed on the I/O second-type MOS transistor is less than that of the semiconductor device on which the compressive stress layer is formed on the I/O second-type MOS transistor. As a result, the semiconductor device of the present invention does not have the negative bias temperature instability (NBTI) degradation. 
         [0046]    In summary, with the semiconductor device and the fabricating method thereof provided by the present invention, when the negative bias is applied on the substrate, H+ is not accumulated in the gate dielectric layer, thus the threshold voltage (Vt) shift effect does not occur. In other words, the negative bias temperature instability (NBTI) degradation in the conventional technique is effectively avoided. On the other hand, compared with the conventional technique, the method of the present invention does not increase the quantity of the photomasks used in the fabricating process, thus the present invention does not increase any additional fabricating cost. 
         [0047]    While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.