Abstract:
The present invention provides a level-shift circuit that can suppress the malfunction caused by the noise due to the ON/OFF of a level-shift transistor and the dV/dt noise due to external noise. The present invention provides a level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side, comprising: a first serial circuit a first resistance including serially-connected to a first switching element; a second serial circuit including a second resistance serially-connected to a second switching element; a latch malfunction protection circuit for which the respective output terminals of the first and second serial circuits are connected to an input terminal; a latch circuit for receiving a signal outputted from the latch malfunction protection circuit; and a capacitor connected between drain terminals of the first resistance and the first switching element and between drain terminals of the second resistance and the second switching element.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a level-shift circuit to prevent the malfunction due to dV/dt noise. 
       BACKGROUND ART 
       [0002]    The control for an industrial motor or a server power source for example is performed by driving half-bridge connection semiconductor devices. As an IC for driving these semiconductor devices, there is an HVIC (High Voltage IC). The use of the HVIC allows both of an upper level-side semiconductor device and a lower level-side semiconductor device of a half-bridge circuit driven by a high potential power source to be driven by one IC. The HVIC receives a control signal of a microcomputer for example to output a signal for driving the semiconductor device. The HVIC includes therein a level-shift circuit in order to drive the upper level-side semiconductor device in particular by a low potential signal. 
         [0003]    The HVIC includes therein a level up shift circuit for transmitting a signal from the low side to the high side and a level down shift circuit for transmitting a signal from the high side to the low side. Generally, a level up shift circuit uses an N channel-type semiconductor switching element and a level down shift circuit uses a P channel-type semiconductor switching element. When a half-bridge circuit is switched, a reference potential of a high side region changes from a low potential to a high potential or from a high potential to a low potential. 
         [0004]      FIG. 1  illustrates a circuit configuration using a conventional level-shift circuit disclosed in Patent Literature 1.  FIG. 1  illustrates a circuit including an output circuit  10  including a high potential-side switching element  11  and a low potential-side switching element  12 , a high potential-side driving circuit  20 , and a low potential-side driving circuit  30 . The high potential-side driving circuit  20  is connected to a gate terminal of the high potential-side switching element  11  of the output circuit  10 . The low potential-side driving circuit  30  is connected to the gate terminal of the low potential-side switching element  12  of the output circuit  10 . 
         [0005]    The output circuit  10  is composed of the high potential-side switching element  11  and the low potential-side switching element  12  that are serially connected. A high voltage power source  13  supplies electric power to a load  14  via the high potential-side switching element  11 . The load  14  is a load that receives the supply of a voltage (electric power) from the half-bridge circuit. The load  14  is connected between the connecting point Vs of the high potential-side switching element  11  and the low potential-side switching element  12  (the potential of the connecting point Vs is also represented by the connecting point Vs) and a grounding potential. 
         [0006]    The high potential-side switching element  11  and the low potential-side switching element  12  are turned ON/OFF in a complementary manner so that one is ON and the other is OFF except for a dead time during which the former and the latter are both OFF. When the low potential-side switching element  12  is ON, the potential of the connecting point Vs is a grounding potential and, when the high potential-side switching element  11  is ON, the potential of the connecting point Vs is the output voltage of the power source  13 . 
         [0007]    The high potential-side driving circuit  20  includes a latch malfunction protection circuit  21 , a latch circuit  22 , a high side driver  23 , a power source  24 , resistances R 1  and R 2 , level-shift transistors  25  and  26 , and diodes D 1  and D 2 . The latch malfunction protection circuit  21 , the latch circuit  22 , the high side driver  23 , and the low potential-side power source terminal of the power source  24  are connected to the connecting point Vs. 
         [0008]    The input of the gate of the level-shift transistor  25  is a set signal that is an input signal to the level-shift circuit of the high potential-side driving circuit  20 . The input of the gate of a level-shift transistor  26  is a reset signal that is an input signal to the level-shift circuit of the high potential-side driving circuit  20 . The set signal is a signal that instructs the timing at which the ON period of the high potential-side switching element  11  is started (or the OFF period is ended). The reset signal is a signal that instructs the timing at which the OFF period of the low potential-side switching element  12  is started (or the ON period is ended). The set signal and the reset signal are pulse input signals that are not turned ON simultaneously. The level-shift transistors  25  and  26  can use an N channel-type semiconductor switching element. 
         [0009]    The input of latch malfunction protection circuit  21  is level-shift output signals setdrn (hereinafter referred to as a setdrn signal) and resdrn (hereinafter referred to as a resdrn signal). When there is a change in the potential of the connecting point Vs, an error signal is caused that is called a dv/dt noise due to the parasitic capacitances Cds 1  and Cds 2  for example between the source and drain of the level-shift transistors  25  and  26 . Then, the setdrn signal and the resdrn signal both have an H level or an L level, undesirably causing the set instruction and the reset instruction to the latch circuit  22  to be valid. In this case, the latch malfunction protection circuit  21  is a circuit to prevent the setdrn signal and the resdrn signal from being directly transmitted to the latch circuit  22  by causing the output to have a high impedance for example. The latch malfunction protection circuit  21  is a circuit that functions, when there is no dv/dt noise, to allow the setdrn signal and the resdrn signal to be directly passed and output and, when there is a dv/dt noise, to output a signal processed based on the setdrn signal and the resdrn signal (by setting one output signal to allow the signal to have an H level when the setdrn signal and the resdrn signal are the ones to set the latch circuit  22  or to allow the output to have a high impedance when the setdrn signal and the resdrn signal are the ones to reset the latch circuit  22  for example) or to block the passage of the setdrn signal and the resdrn signal. 
         [0010]    The input of the latch circuit  22  is an input signal from the latch malfunction protection circuit  21  and stores therein a value set or reset depending on whether the input signal is L or H to output the value. When the input has a high impedance, the latch circuit  22  retains and outputs a value stored immediately before when the input had the high impedance. 
         [0011]    The output terminal of the high side driver  23  is connected to the gate terminal of the high potential-side switching element  11 . The output terminal of the high side driver  23  outputs a signal HO depending on the output of the latch circuit  22  to control the ON/OFF of the high potential-side switching element  11 . 
         [0012]    The diodes D 1  and D 2  have anodes connected to the connecting point Vs. The cathode of the diode D 1  is connected to the connecting point Vsetb. The cathode of the diode D 2  is connected to the connecting point Vrstb. The diodes D 1  and D 2  function to clamp the voltages Vsetb and Vrstb so that the voltages Vsetb and Vrstb are prevented from being equal to or lower than the potential Vs and to protect the latch malfunction protection circuit  21  so that the latch malfunction protection circuit  21  does not receive an overvoltage. 
         [0013]    The low potential-side driving circuit  30  includes a low side driver  31  that controls the ON/OFF of the low potential-side switching element  12  and a power source  32  that supplies a power source to the low side driver  31 . The low side driver  31  amplifies the signal S that instructs the ON/OFF of the low potential-side switching element  12  to output the signal S to the gate terminal of the low potential-side switching element  12 . As a result, the low potential-side driving circuit  30  turns ON the low potential-side switching element  12  when the signal S inputted to the low side driver  31  has a H (High) level and turns OFF the low potential-side switching element  12  when the signal S has an L (Low) level. 
         [0014]      FIG. 2  illustrates a conventional level-shift circuit disclosed in Patent Literature 2. The level-shift circuit shown in  FIG. 2  is different from the level-shift circuit shown in  FIG. 1  mainly in a malfunction prevention circuit and a latch circuit provided at the high side. 
       CITATION LIST 
     Patent Literature 
       [0015]    PTL 1: Japanese Patent No. 3429937 
         [0016]    PTL 2: Japanese Patent Laid-Open No. 2011-044770 
       SUMMARY OF INVENTION 
     Technical Problem 
       [0017]    In accordance with a switching operation of a half-bridge circuit, a level-shift circuit has a phenomenon of so-called dV/dt noise caused when the potential Vs of the connecting point Vs as a reference potential of the high side circuit rapidly changes from a low potential to a high potential or from a high potential to a low potential to thereby cause a change of a part (or the entirety) of the high side circuit to the reference voltage Vs. The level-shift circuit had a possibility where the influence of this dV/dt noise may cause the output of the high side circuit to have a malfunction (logic inversion). Factors causing the tendency of a malfunction due to the generated dV/dt noise include a variation of elements of device constituting the circuit in particular. Specifically, the existence of the element variation causes a different kind of an output of the dV/dt noise in the setdrn signal and the resdrn signal. Thus, when the latch malfunction protection circuit  21  includes therein dV/dt noise, there is no more assumption that the setdrn signal and the resdrn signal both have an H level or an L level. When the setdrn signal and the resdrn signal due to the dV/dt noise occur at timings different by a certain high amount, then such a malfunction occurs that undesirably determines the status of the latch circuit  22  depending on a subsequently-outputted false output signal. The malfunction due to the dV/dt noise leads to the breakage due to the short-circuiting of the half-bridge circuit, thus requiring the malfunction resistance against the dV/dt noise. In the case of the circuits shown in  FIG. 1  and  FIG. 2 , the latch malfunction protection circuit  21  performing a filter operation was provided at the former stage of the latch circuit  22  in order to prevent the malfunction due to the dV/dt noise as described above. 
         [0018]    The dV/dt noise is caused not only by the noise due to the ON/OFF of the level-shift transistor  25  and  26  but also by the external noise from lightning surge or noise of other devices. In the case of the conventional level-shift circuits shown in  FIG. 1  and  FIG. 2 , when the dV/dt noise is caused only by the ON/OFF, the influence by the noise to be caused due to the ON/OFF could be predicted at a certain level, thus preventing a malfunction by adjusting the threshold value of the latch mal function protection circuit  21 . However, when the dV/dt noise is caused not only by the noise due to the ON/OFF but also by external noise, a malfunction could not be predicted because the influence by the external noise could not be predicted. Furthermore, in the case of the circuits shown in  FIG. 1  and  FIG. 2 , a disadvantage of an increased circuit area was caused by an attempt to improve the function of the latch malfunction protection circuit  21  so as to be further able to cope with external noise. 
         [0019]    The present invention has been made in view of the above. It is an objective of the present invention to provide a level-shift circuit to prevent the noise due to the ON/OFF of a level-shift transistor and a malfunction (logic inversion) due to dV/dt noise caused by external noise. 
       Solution to Problem 
       [0020]    In order to solve the above-described problem, one embodiment of the level-shift circuit of the present invention provides a level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side different from the primary side potential system, comprising: a first serial circuit including a first resistance serially-connected to a first switching element, wherein the input of the first switching element is a first input signal for turning ON or OFF the first switching element, and a connecting point of the first resistance and the first switching element acts as an output terminal, a second serial circuit including a second resistance serially-connected to a second switching element, wherein the input of the second switching element a second input signal for controlling the ON/OFF of the second switching element, a connecting point of the second resistance and the second switching element acts as an output terminal, and the first input signal and the second input signal are not simultaneously turned ON, a latch circuit for changing a status depending on the output of the output terminal of the first serial circuit and the output of the output terminal of the second serial circuit, and a first capacitor connected between the output terminal of the first serial circuit and the output terminal of the second serial circuit. 
       Advantageous Effects of Invention 
       [0021]    The level-shift circuit according to the present invention can suppress the malfunction caused by the noise due to the ON/OFF of the level-shift transistor and the dV/dt noise due to external noise. 
         [0022]    Furthermore, according to the present invention, the capacitor provided between two serial circuits eliminates the need to improve the function of a latch malfunction protection circuit. Thus, the latch malfunction protection circuit area can be designed to have a small size, thus providing an entirely-compact circuit apparatus. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0023]      FIG. 1  illustrates a conventional level-shift circuit disclosed in Patent Literature 1; 
           [0024]      FIG. 2  illustrates a conventional level-shift circuit disclosed in Patent Literature 2; 
           [0025]      FIG. 3  illustrates a level up shift circuit according to Example 1 of the present invention; 
           [0026]      FIG. 4A  is a time chart illustrating the operation waveforms of the level-shift circuit; 
           [0027]      FIG. 4B  is a time chart illustrating the operation waveforms of the level-shift circuit; 
           [0028]      FIG. 5  illustrates the level down shift circuit according to Example 2 of the present invention; 
           [0029]      FIG. 6  illustrates the level up shift circuit according to Example 3 of the present invention; 
           [0030]      FIG. 7  illustrates the relation between a capacitor frequency characteristic and a dV/dt noise frequency; and 
           [0031]      FIG. 8  illustrates the relation between the frequency characteristic and the dV/dt noise frequency when a plurality of different capacitors are added. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
     Example 1 
       [0032]      FIG. 3  illustrates a configuration example of the level up shift circuit according to Example 1 of the present invention. In the level up shift circuit shown in  FIG. 3 , a capacitor C 1  is provided between a first serial circuit composed of a resistance R 1  and a first the level-shift transistor  25 , and a second serial circuit composed of resistance R 2  and a second the level-shift transistor  26 . Specifically, the capacitor C 1  is connected between the connecting point between the resistance R 1  and the drain terminal of the first the level-shift transistor  25  (the first serial circuit output terminal), and the connecting point between the resistance R 2  and the drain terminal of the second the level-shift transistor  26  (the second serial circuit output terminal). The circuit illustrated in  FIG. 3  is different from the circuit shown in  FIG. 1  in having the capacitor C 1 . Thus, configurations similar to those of the circuit shown in  FIG. 1  will not be further described. 
         [0033]    As described above, it has been known that the malfunction of the level-shift circuit is caused by an operation difference of two serial circuits to a change of the potential Vs. As an example, a case will be considered where the malfunction due to the dV/dt noise occurs in the status where there is an element variation (e.g., the variation of the parasitic capacitances Cds 1  and Cds 2  of the level-shift transistors  25  and  26 ). When the variation of the output point Vs of the half-bridge circuit (=high side reference potential) due to the switching operation is transmitted to the first and second serial circuits via the diodes D 1  and D 2  to cause the setdrn signal and the resdrn signal to include therein the dV/dt noise, then the parasitic capacitances Cds 1  and Cds 2  have an influence on the waveform of the generated dV/dt noise. Thus, the difference between the parasitic capacitances Cds 1  and Cds 2  causes a difference in the phase or amplitude of the two setdrn and resdrn signals, thus causing the malfunction due to this difference. 
         [0034]    In the present invention, for the purpose of reducing a difference in the phase or amplitude of the two setdrn and resdrn signals, the capacitor C 1  is coupled between two serial circuits. As a result, when there is a potential variation between the setdrn signal and the resdrn signal due to the vibration of the setdrn signal and the resdrn signal (e.g., ringing), the capacitor C 1  causes the two setdrn signal and resdrn signals to be coupled so as to reduce the impedance therebetween. Thus, the potential error between the setdrn signal and the resdrn signal can be reduced. This can consequently prevent the malfunction caused by the noise due to the ON/OFF of the level-shift transistor and the dV/dt noise due to external noise. Since the first and second serial circuits do not have therebetween a DC coupling, there is no operational problem. 
         [0035]      FIG. 4A  illustrates a time chart of the operation waveform of a level-shift circuit according to a conventional configuration as shown in  FIG. 1  in which no capacitor is provided between serial circuits.  FIG. 4B  illustrates a time chart of the operation waveform of the level-shift circuit according to Example 1 of the present invention. As shown in the graph of the reference GND (Vs) of  FIGS. 4A  and B, when noise due to the ON/OFF of the level-shift transistor or external noise is caused, then, in a conventional level-shift circuit having no capacitive coupling, a significant variation a 1  is caused in the difference between the setdrn signal and the resdrn signal as shown in  FIG. 4A , causing a malfunction a 2  where the signal HO changes from the L level to the H level. On the other hand, the level-shift circuit according to the present invention having capacitive coupling suppresses the variation b 1  in the difference between the setdrn signal and the resdrn signal as shown in  FIG. 4B . Thus, the level-shift circuit according to the present invention maintains the signal HO at the L level, thus suppressing the malfunction b 2 . 
         [0036]    As described above, the present invention can prevent the malfunction caused by the noise due to the ON/OFF of the level-shift transistor and the dV/dt noise due to the external noise. Furthermore, according to the present invention, the provision of the capacitor C 1  eliminates the need to improve the function of the latch malfunction protection circuit. This consequently provides a latch malfunction protection circuit area having a smaller design, thus providing an entirely-compact circuit apparatus. 
       Example 2 
       [0037]      FIG. 5  illustrates the configuration of the level down shift circuit according to Example 2 of the present invention.  FIG. 5  illustrates the level down shift circuit including the capacitor C 1  provided over a high side circuit  200  and a low side circuit  300 . 
         [0038]    The high side circuit  200  includes a detection unit  201 , a pulse generation unit  202 , and level-shift transistors  203  and  204 . The low side circuit  300  includes a latch malfunction protection circuit  301 , a latch circuit  302 , an alarm output circuit  303 , resistances R 1  and R 2 , and diodes D 1  and D 2 . A P channel-type semiconductor switching element can be used for the level-shift transistors  203  and  204 . 
         [0039]    In the high side circuit  200  of the level down shift circuit shown in  FIG. 5 , the detection unit  201  detects the excess current, voltage decrease, and overheating of a high potential-side switching element to output a detection signal. In response to the signal outputted from the detection unit  201 , the pulse generation unit  202  generates a pulse and outputs the set signal and reset signal to the level-shift transistors  203  and  204 , respectively. 
         [0040]    In the low side circuit  300  of the level down shift circuit shown in  FIG. 5 , the latch malfunction protection circuit  301  inputs the setdrn signal and the resdrn signal and filters out the setdrn signal and the resdrn signal equal to or lower than a predetermined threshold value to output a signal to the latch circuit  302 . The alarm output circuit  303  outputs an alarm signal depending on the output of the latch circuit  302 . 
         [0041]    By the level down shift circuit, the excess current detection, the voltage decrease detection, and the overheating detection results for example of the high potential-side switching element driven by the high side output (HO) can be transmitted to the low side. 
         [0042]    As shown in  FIG. 5 , the capacitor C 1  can be provided between a serial circuit consisting of the level-shift transistor  203  and the resistance R 1 , and a serial circuit consisting of the level-shift transistor  204  and resistance R 2  to thereby prevent, the malfunction caused by the noise due to the ON/OFF of the level-shift transistor and the dV/dt noise due to the external noise same as in the level up shift circuit according to Example 1 of the present invention. Furthermore, the entire circuit apparatus can have a compact size. 
       Example 3 
       [0043]      FIG. 6  illustrates a configuration example of the level up shift circuit according to Example 3 of the present invention. As shown in  FIG. 6 , the level up shift circuit according to Example 3 is configured so that two serial circuits have therebetween the capacitor C 1  and the capacitor C 2  having a frequency characteristic different from that of the capacitor C 1 . 
         [0044]    As described above, by using a plurality of capacitors having different frequency characteristics, when compared with a case where only one capacitor C 1  is added as in Example 1, the frequency region for reducing the impedance can be increased, thus improving the effect of suppressing the malfunction. 
         [0045]      FIG. 7  illustrates the relation between the capacitor frequency characteristic and the dV/dt noise frequency region. Here, the region X 2  is a constant region. Generally, a capacitive used for the capacitive coupling in a level-shift circuit preferably has a capacity value at which the impedance is decreased at a frequency region causing dV/dt noise (dV/dt noise frequency region X 1 ). 
         [0046]      FIG. 8  illustrates the relation between the frequency characteristic and the dV/dt noise frequency region when a plurality of different capacitors are added.  FIG. 8  illustrates the relation between the frequency characteristic and the dV/dt noise frequency region when capacitors C 5  or C 10  respectively having different frequency characteristics is used alone and when the combined capacity of the capacitors C 5  and C 10  is used. 
         [0047]    As shown in  FIG. 8 , when the capacitors C 5  or C 10  respectively have different frequency characteristics is used alone, an increase of the frequency causes a change of the impedance, at the capacitor self-resonance frequency as a boundary, from the decrease tendency (capacitor characteristic) to the increase tendency (inductance characteristic). Thus, the dV/dt noise frequency region X 1  cannot be covered by the range within which the impedance decreases, thus causing a case where the dV/dt noise cannot be handled sufficiently. 
         [0048]    When the combined capacity of the capacitors C 5  and C 10  is used on the other hand, the impedance can be decreased between two self-resonance frequencies. Thus, the range within which the impedance decreases in the dV/dt noise frequency region X 3  can be more widely secured when compared with a case where only one capacitor is used, thus more widely handling the dV/dt noise. 
         [0049]    In Example 3, a configuration was shown in which two serial circuits had therebetween the two capacitors C 1  and C 2 . However, two or more capacitors can be provided between two level-shift circuits. In Example 3, a configuration was shown in which two serial circuits had therebetween the two capacitors C 1  and C 2  in the level up shift circuit. However, this configuration also can be applied to a level down shift circuit. 
       REFERENCE SIGNS LIST 
       [0000]    
       
           10  Output circuit 
           11  High potential-side switching element 
           12  Low potential-side switching element 
           13 ,  24 , and  32  Power source 
           14  Load 
           20  High potential-side driving circuit 
           21  and  301  Latch malfunction protection circuit 
           22  and  302  Latch circuit 
           23  High side driver 
           25 ,  26 ,  203 , and  204  Level-shift transistor 
           30  Low potential-side driving circuit 
           31  Low side driver 
         R 1  and R 2  Resistance 
         D 1  and D 2  Diode 
         C 1  and C 2  Capacitor 
           200  High side circuit 
           201  Detection unit 
           202  Pulse generation unit 
           300  Low side circuit 
           303  Alarm output circuit