Abstract:
An embodiment of a power supply includes an output node, inductively coupled phase paths, and a sensor circuit. The output node is configured to provide a regulated output signal, and the inductively coupled phase paths are each configured to provide a respective phase current to the output node. And the sensor circuit is configured to generate a sense signal that represents the phase current flowing through one of the phase paths. For example, because the phase paths are inductively coupled to one another, the sensor circuit takes into account the portions of the phase currents induced by the inductive couplings to generate a sense signal that more accurately represents the phase current through a single phase path as compared to conventional sensor circuits.

Description:
CLAIM OF PRIORITY 
       [0001]    The present application is a Continuation of copending U.S. patent application Ser. No. 12/189,112, filed 8 Aug. 2008; which application claims priority to U.S. Provisional Application Ser. Nos. 60/964,792 filed on Aug. 14, 2007, now expired, and U.S. Provisional Application Ser. Nos. 61/072,287 filed on Mar. 27, 2008, now expired; all of the foregoing applications are incorporated herein by reference in their entireties. 
     
    
     SUMMARY 
       [0002]    An embodiment of a power supply includes an output node, inductively coupled phase paths, and a sensor circuit. The output node is configured to provide a regulated output signal, and the inductively coupled phase paths are each configured to provide a respective phase current to the output node. And the sensor circuit is configured to generate a sense signal that represents the phase current flowing through one of the phase paths. 
         [0003]    For example, because the phase paths are inductively coupled to one another, the sensor circuit takes into account the portions of the phase currents induced by the inductive couplings to generate a sense signal that more accurately represents the phase current through a single phase path as compared to conventional sensor circuits. The sense signal may be fed back to a power-supply controller, which regulates the output signal (e.g., an output voltage) at least partly in response to the fed-back sense signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a schematic diagram of an embodiment of a coupled-inductor multiphase power supply that includes sense circuits for sensing the phase currents. 
           [0005]      FIG. 2  is a schematic diagram of a portion of the power supply of  FIG. 1  including the phase-path windings, and an embodiment of the sensor circuits of  FIG. 1 . 
           [0006]      FIG. 3  is a schematic diagram of a two-phase version of the power-supply portion of  FIG. 2 . 
           [0007]      FIGS. 4A and 4C  are timing diagrams of sense signals that are generated by the sensor circuits of  FIG. 3 . 
           [0008]      FIGS. 4B and 4D  are timing diagrams of the phase currents flowing through the windings of  FIG. 3 . 
           [0009]      FIG. 5  is a schematic diagram of a portion of a two phase version of the powers supply of  FIG. 1  including the phase-path windings and another embodiment of the sensor circuits of  FIG. 1 . 
           [0010]      FIG. 6  is a block diagram of an embodiment of a computer system having a power supply that includes sensor circuits that are the same as or similar to one or more of the embodiments discussed above in conjunction with  FIGS. 2-3  and  5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]      FIG. 1  is a schematic diagram of an embodiment of a coupled-inductor (CI) multiphase power supply  10 , here a CI buck converter, which provides a regulated output voltage V out  at a supply output node  11 , and which includes phase paths (alternatively “phases”)  12   1 - 12   n  and current sensors  14   1 - 14   n  for respectively sensing the currents i 1 -i n  through the phases. As discussed below in conjunction with  FIGS. 2-5 , the current sensors  14   1 - 14   n  may each be coupled to respective multiple phase paths  12   1 - 12   n  at nodes or locations other than the supply output node  11 . For example, assume that some or all of the phases  12   1 - 12   n  are magnetically coupled to one another. Coupling a current sensor  14  not only to a first phase  12  for which the sensor measures the phase current, but also to one or more second phases  12  to which the first phase is magnetically coupled, may allow the sensor to sense the current through the first phase more accurately than some conventional current sensors can. 
         [0012]    The current sensors  14   1 - 14   n  respectively generate sense signals I FB1 -I FBn , which respectively represent the phase currents i 1 -i n . For example, each of the signals I FB1 -I FBn  may be a respective voltage that has substantially the same signal phase as the corresponding phase current i and that has an amplitude that is substantially proportional to the amplitude of the corresponding phase current. 
         [0013]    In addition to the current sensors  14   1 - 14   n , the converter  10  includes a coupled-inductor assembly  16  having windings  18   1 - 18   n , which are wound about a common core (not shown in  FIG. 1 ) and which are magnetically coupled to one another via the core, a power-supply controller  20 , high-side drive transistors  22   1 - 22   n , low-side drive transistors  24   1 - 24   n , a filter capacitor  26 , and an optional filter inductor  28 . A winding  18  and the high-side and low-side transistors  22  and  24  coupled to the winding at a phase intermediate node INT compose a respective phase  12 . For example, the winding  18   1  and the transistors  22   1  and  24   1  compose the phase  12   1 . 
         [0014]    The controller  20  may be any type of controller suitable for use in a multiphase CI power supply, is supplied by voltages VDD controller  and VSS controller , and receives the regulated output voltage V out , a reference voltage V ref , and the sense signals I FB1 -I FBn , which are fed back to the controller from the current sensors  14   1 - 14   n , respectively. The controller  20  may use V ref  and the fed back V ont  and I FB1 -I FBn  to conventionally regulate V out  to a desired value. 
         [0015]    The high-side transistors  22   1 - 22   n , which are each switched “on” and “off” by the controller  20 , are power NMOS transistors that are respectively coupled between input voltages VIN 1 -VIN n  and the nodes INT 1 -INT n . Alternatively, the transistors  22   1 - 22   n  may be other than power NMOS transistors, and may be coupled to a common input voltage. Moreover, the transistors  22   1 - 22   n  may be integrated on the same die as the controller  20 , may be integrated on a same die that is separate from the die on which the controller is integrated, or may be discrete components. 
         [0016]    Similarly, the low-side transistors  24   1 - 24   n , which are each switched on and off by the controller  20 , are power NMOS transistors that are respectively coupled between low-side voltages VL 1 -VL n  and the nodes INT 1 -INT n  of the phase windings  18   1 - 18   n . Alternatively, the transistors  24   1 - 24   n  may be other than power NMOS transistors, and may be coupled to a common low-side voltage such as ground. Moreover, the transistors  24   1 - 24   n  may be integrated on the same die as the controller  20 , may be integrated on a same die that is separate from the die on which the controller is integrated, may be integrated on a same die as the high-side transistors  22   1 - 22   n , may be integrated on respective dies with the corresponding high-side transistors  22   1 - 22   n  (e.g., transistors  22   1  and  24   1  on a first die, transistors  22   2  and  24   2  on a second die, and so on), or may be discrete components. 
         [0017]    The filter capacitor  26  is coupled between the regulated output voltage V out  and a voltage VSS cap , and works in concert with the windings  18   1 - 18   n  and an optional filter inductor  28  (if present) to maintain the amplitude of the steady-state ripple-voltage component of V out  within a desired range which may be on the order of hundreds of microvolts (μV) to tens of millivolts (mV). Although only one filter capacitor  26  is shown, the converter  10  may include multiple filter capacitors coupled in electrical parallel. Furthermore, VSS cap  may be equal to VSS controller  and to VL 1 -VL n ; for example, all of these voltages may equal ground. 
         [0018]    As further discussed below, the filter inductor  28  may be omitted if the leakage inductances L lk1 -L lkn  (discussed below) of the windings  18   1 - 18   n  are sufficient to perform the desired inductive filtering function. In some applications, the filter inductor  28  may be omitted to reduce the size and component count of the converter  10 . 
         [0019]    Each of the windings  18   1 - 18   n  of the coupled-inductor assembly  16  may be modeled as a self inductance L and a resistance DCR. For purposes of discussion, only the model components of the winding  18   1  are discussed, it being understood that the model components of the other windings  18   2 - 18   n  are similar, except for possibly their values. 
         [0020]    The self inductance L 1  of the winding  18   1  may be modeled as two zero-resistance inductances: a magnetic-coupling inductance L c1 , and a leakage inductance L lk1 . When a phase current i 1  flows through the winding  18   1 , the current generates a magnetic flux. The value of the coupling inductance L C1  is proportional to the amount of this flux that is coupled to other windings  18   2 - 18   n , and the value of the leakage inductance L lk1  is proportional to the amount of the remaining flux, which is not coupled to the other windings  18   2 - 18   n . In one embodiment, L C1 =L C2 = . . . =L Cn , and L lk1 =L lk2 = . . . =L lkn , although inequality among the coupling inductances L C , the leakage inductances L lk , or both L C  and L lk , is contemplated. Furthermore, in an embodiment, the respective magnetic-coupling coefficients between pairs of coupling inductances L C  are equal (i.e., a current through L C1  magnetically induces respective equal currents in L C2 , . . . L Cn ), although unequal coupling coefficients are contemplated. 
         [0021]    The resistance DCR 1  is the resistance of the winding  18   1  when a constant voltage V 1  is applied across the winding and causes a constant current I 1  to flow through the winding. That is, DCR 1 =V 1 /I 1 . 
         [0022]    The power supply  10  may provide the regulated voltage V out  to a load  30 , such as a microprocessor. 
         [0023]    Still referring to  FIG. 1 , alternate embodiments of the power supply  10  are contemplated. Some or all of the phases  12   1 - 12   n  may be magnetically uncoupled from one another. For example, phases  12   1  and  12   2  may be formed on a first core and thus may be magnetically coupled, and phases  12   3  and  12   4  may be formed on a second core separate from the first core, and thus may be magnetically coupled to one another but magnetically uncoupled form the phases  12   1  and  12   2 . Or, a phase  12  may be magnetically uncoupled from all other phases  12 . Furthermore, although described as a multiphase buck converter, the power supply  10  may be any other type of multiphase power supply. 
         [0024]      FIG. 2  is a schematic diagram of a portion of the power supply  10  of  FIG. 1  including the windings  18   1 - 18   n  and an embodiment of the current sensors  14   1 - 14   n . For purposes of discussion, it is assumed that all of the windings  18   1  and  18   n  are magnetically coupled to one another, and that the filter inductor  28  is omitted from the supply  10 . For brevity, only the sensor  14   1  is discussed, it being understood that the other sensors  14  are similar except for possibly the values of the components that compose the other sensors. 
         [0025]    The sensor  14   1  includes a capacitor C 1  across which the sense signal I FB1  (here a voltage signal) is generated, an optional scaling resistor RC 1  coupled across C 1 , and resistors R 11 -R n1 , which are respectively coupled between the nodes INT 1 -INT n  and C 1 . 
         [0026]    The resistor R 11  couples to C 1  a signal (a current in this embodiment) that represents the portion of the phase current i 1  that the switching transistors  22   1  and  24   1  ( FIG. 1 ) cause to flow through the winding  18   1 . 
         [0027]    And the resistors R 21 -R n1  each couple to C 1  a respective signal (a current in this embodiment) that represents the respective portion of I 1  that a respective phase current i 2 -i n  magnetically induces in the winding  18   1 . That is, the resistor R 21  couples to C 1  a current that is proportional to the portion of i 1  that the phase current i 2  magnetically induces in the winding  18   1 . Similarly, the resistor R 31  couples to C 1  a current that is proportional to the portion of i 1  that the phase current i 3  magnetically induces in the winding  18   1 , and so on. 
         [0028]    C 1  generates from the sum of the signals from R 11 -R n1  the sense voltage I FB1 , which has the same phase as i 1  and which has an amplitude that is proportional to the amplitude of i 1 . 
         [0029]    Therefore, a power-supply controller, such as the controller  20  of  FIG. 1 , may obtain from I FB1  an accurate representation of the instantaneous phase and amplitude of the phase current 
         [0030]    In a similar manner, the capacitors C 2 -C n  respectively generate the sense voltages I FB2 -I FBn , from which a power-supply controller, such as the controller  20  of  FIG. 1 , may obtain accurate representations of the instantaneous phases and amplitudes of the phase currents i 2 -i n . 
         [0031]      FIG. 3  is a schematic diagram of a two-phase (n=2) version of the power-supply portion of  FIG. 2 . 
         [0032]    Referring to  FIG. 3 , an embodiment of a technique for calculating values for R 11 , R 12 , R 21 , R 22 , C 1 , and RC 1  (if present) is presented. To simplify the presentation, it is assumed that R 11 =R 22 =R 1 , R 21 =R 12 =R 2 , L C1 =L c2 =L C , L Llk1 =L lk2 =L lk , DCR 1 =DCR 2 =DCR, and RC 1 =RC 2 =∞ (i.e., RC 1  and RC 2  are omitted) in equations (1)-(16) below. It is, however, understood that the disclosed embodiment may be extrapolated to a more general embodiment of  FIGS. 2-3  for R 11 ≠R 22 , R 21 ≠R 12 , L C1 ≠L C2 , L lk1 ≠L lk2 , DCR 1 ≠DCR 2 , RC 1 ≠RC 2 ≠∞, and n&gt;2. 
         [0033]    Still referring to  FIG. 3 , the following equations are derived from the general relationship between the currents through and the voltages across reverse-coupled inductors—the windings  18   1  and  18   2  are reversed coupled when a positive current flowing through the winding  18   1  into the node  11  induces a positive current in the winding  18   2  also flowing into the node  11 . 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     1 
                   
                   = 
                   
                     
                       s 
                       · 
                       
                         ( 
                         
                           
                             L 
                             lk 
                           
                           + 
                           
                             L 
                             C 
                           
                         
                         ) 
                       
                       · 
                       
                         i 
                         1 
                       
                     
                     - 
                     
                       s 
                       · 
                       
                         L 
                         C 
                       
                       · 
                       
                         i 
                         2 
                       
                     
                     + 
                     
                       DCR 
                       · 
                       
                         i 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     2 
                   
                   = 
                   
                     
                       s 
                       · 
                       
                         ( 
                         
                           
                             L 
                             lk 
                           
                           + 
                           
                             L 
                             C 
                           
                         
                         ) 
                       
                       · 
                       
                         i 
                         2 
                       
                     
                     - 
                     
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                       · 
                       
                         L 
                         C 
                       
                       · 
                       
                         i 
                         1 
                       
                     
                     + 
                     
                       
                         DCR 
                         · 
                         
                           i 
                           2 
                         
                       
                        
                       
                           
                       
                        
                       and 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   
                     i 
                     2 
                   
                   = 
                   
                     
                       
                         V 
                         2 
                       
                       + 
                       
                         s 
                         · 
                         
                           L 
                           C 
                         
                         · 
                         
                           i 
                           1 
                         
                       
                     
                     
                       
                         s 
                         · 
                         
                           ( 
                           
                             
                               L 
                               lk 
                             
                             + 
                             
                               L 
                               C 
                             
                           
                           ) 
                         
                       
                       + 
                       DCR 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where V 1  and V 2  are the voltages at nodes INT 1  and INT 2 , respectively. 
         [0034]    From equations (1)-(3), one may derive the following equation for 
         [0000]    
       
         
           
             
               
                 
                   
                     i 
                     1 
                   
                   = 
                   
                     
                       
                         
                           V 
                           1 
                         
                         · 
                         
                           [ 
                           
                             
                               s 
                               · 
                               
                                 ( 
                                 
                                   
                                     L 
                                     lk 
                                   
                                   + 
                                   
                                     L 
                                     C 
                                   
                                 
                                 ) 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                       
                       + 
                       
                         s 
                         · 
                         
                           L 
                           C 
                         
                         · 
                         
                           V 
                           2 
                         
                       
                     
                     
                       
                         
                           [ 
                           
                             
                               s 
                                
                               
                                 ( 
                                 
                                   
                                     L 
                                     lk 
                                   
                                   + 
                                   
                                     L 
                                     C 
                                   
                                 
                                 ) 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                         2 
                       
                       - 
                       
                         
                           [ 
                           
                             s 
                             · 
                             
                               L 
                               C 
                             
                           
                           ] 
                         
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0035]    Furthermore, where R 11 =R 1  and R 21 =R 2  are the resistors coupled to the capacitor C 1 , one may derive the following equation for the voltage I FB1  across C 1 : 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     
                       FB 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         
                           
                             R 
                             1 
                           
                           
                             1 
                             + 
                             
                               s 
                               · 
                               
                                 R 
                                 1 
                               
                               · 
                               
                                 C 
                                 1 
                               
                             
                           
                         
                         
                           
                             
                               R 
                               1 
                             
                             
                               1 
                               + 
                               
                                 s 
                                 · 
                                 
                                   R 
                                   1 
                                 
                                 · 
                                 
                                   C 
                                   1 
                                 
                               
                             
                           
                           + 
                           
                             R 
                             
                               2 
                                
                               
                                   
                               
                             
                           
                         
                       
                       · 
                       
                         V 
                         1 
                       
                     
                     + 
                     
                       
                         
                           
                             R 
                             2 
                           
                           
                             1 
                             + 
                             
                               s 
                               · 
                               
                                 R 
                                 2 
                               
                               · 
                               
                                 C 
                                 1 
                               
                             
                           
                         
                         
                           
                             
                               R 
                               2 
                             
                             
                               1 
                               + 
                               
                                 s 
                                 · 
                                 
                                   R 
                                   2 
                                 
                                 · 
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                           + 
                           
                             R 
                             1 
                           
                         
                       
                       · 
                       
                         V 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0036]    Because the voltage VDCR 1  across DCR 1  equals i 1  DCR 1 , VDCR 1  has the same phase as i 1 , and has an amplitude that is proportional (by a factor DCR 1 ) to the amplitude of as discussed above in conjunction with  FIG. 1 , these attributes are suitable for I FB1 . 
         [0037]    Unfortunately, DCR 1  is a modeled component, and one does not have physical access to the voltage VDCR 1  across it. 
         [0038]    But, one can set I FB1 =VDCR 1 =i 1 ·DCR 1  according to the following equation, which is derived from equations (4) and (5): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           R 
                           1 
                         
                         · 
                         
                           V 
                           1 
                         
                       
                       + 
                       
                         
                           R 
                           2 
                         
                         · 
                         
                           V 
                           
                             2 
                              
                             
                                 
                             
                           
                         
                       
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         R 
                         2 
                       
                       + 
                       
                         s 
                         · 
                         
                           R 
                           1 
                         
                         · 
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           1 
                         
                       
                     
                   
                   = 
                   
                     
                       
                         
                           
                             V 
                             1 
                           
                           · 
                           
                             [ 
                             
                               
                                 s 
                                 · 
                                 
                                   ( 
                                   
                                     
                                       L 
                                       lk 
                                     
                                     + 
                                     
                                       L 
                                       C 
                                     
                                   
                                   ) 
                                 
                               
                               + 
                               DCR 
                             
                             ] 
                           
                         
                         + 
                         
                           s 
                           · 
                           
                             L 
                             C 
                           
                           · 
                           
                             V 
                             2 
                           
                         
                       
                       
                         
                           [ 
                           
                             
                               s 
                                
                               
                                 ( 
                                 
                                   
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                                     lk 
                                   
                                   + 
                                   
                                     L 
                                     C 
                                   
                                 
                                 ) 
                               
                             
                             + 
                             
                               s 
                               · 
                               
                                 L 
                                 C 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                         · 
                         
                           [ 
                           
                             
                               s 
                               · 
                               
                                 L 
                                 lk 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                       
                     
                     · 
                     DCR 
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0039]    From equation (6), one can derive the following two equations: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         R 
                         1 
                       
                       · 
                       
                         V 
                         1 
                       
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         R 
                         2 
                       
                       + 
                       
                         s 
                         · 
                         
                           R 
                           1 
                         
                         · 
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           1 
                         
                       
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           1 
                         
                         · 
                         
                           [ 
                           
                             
                               s 
                               · 
                               
                                 ( 
                                 
                                   
                                     L 
                                     lk 
                                   
                                   + 
                                   
                                     L 
                                     C 
                                   
                                 
                                 ) 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                       
                       
                         
                           [ 
                           
                             
                               s 
                                
                               
                                 ( 
                                 
                                   
                                     L 
                                     lk 
                                   
                                   + 
                                   
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                                     C 
                                   
                                 
                                 ) 
                               
                             
                             + 
                             
                               s 
                               · 
                               
                                 L 
                                 C 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                         · 
                         
                           [ 
                           
                             
                               s 
                               · 
                               
                                 L 
                                 lk 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                       
                     
                     · 
                     DCR 
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         R 
                         2 
                       
                       · 
                       
                         V 
                         2 
                       
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         R 
                         2 
                       
                       + 
                       
                         s 
                         · 
                         
                           R 
                           1 
                         
                         · 
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           1 
                         
                       
                     
                   
                   = 
                   
                     
                       
                         s 
                         · 
                         
                           L 
                           C 
                         
                         · 
                         
                           V 
                           2 
                         
                       
                       
                         
                           [ 
                           
                             
                               s 
                                
                               
                                 ( 
                                 
                                   
                                     L 
                                     lk 
                                   
                                   + 
                                   
                                     L 
                                     C 
                                   
                                 
                                 ) 
                               
                             
                             + 
                             
                               s 
                               · 
                               
                                 L 
                                 C 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                         · 
                         
                           [ 
                           
                             
                               s 
                               · 
                               
                                 L 
                                 lk 
                               
                             
                             + 
                             DCR 
                           
                           ] 
                         
                       
                     
                     · 
                     DCR 
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0040]    Referring to  FIG. 1 , if one assumes that the controller  20  switches the transistors  22  and  24  at a relatively high frequency, e.g., 100 KHz or higher (this assumption applies in many applications of multiphase power supplies), then one may assume that s(L lk +L C ) and sL lk  are much greater than DCR. Applying these assumptions, equations (7) and (8) respectively reduce to the following equations: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         R 
                         1 
                       
                       · 
                       
                         ( 
                         
                           1 
                           + 
                           
                             s 
                             · 
                             
                               
                                 L 
                                 lk 
                               
                               DCR 
                             
                           
                         
                         ) 
                       
                     
                     
                       
                         ( 
                         
                           
                             R 
                             1 
                           
                           + 
                           
                             R 
                             2 
                           
                         
                         ) 
                       
                       · 
                       
                         ( 
                         
                           1 
                           + 
                           
                             s 
                             · 
                             
                               
                                 
                                   R 
                                   1 
                                 
                                 · 
                                 
                                   R 
                                   2 
                                 
                               
                               
                                 
                                   R 
                                   1 
                                 
                                 + 
                                 
                                   R 
                                   2 
                                 
                               
                             
                             · 
                             C 
                           
                         
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         L 
                         C 
                       
                     
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         2 
                          
                         
                           L 
                           C 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         R 
                         2 
                       
                       · 
                       
                         ( 
                         
                           1 
                           + 
                           
                             s 
                             · 
                             
                               
                                 L 
                                 lk 
                               
                               DCR 
                             
                           
                         
                         ) 
                       
                     
                     
                       
                         ( 
                         
                           
                             R 
                             1 
                           
                           + 
                           
                             R 
                             2 
                           
                         
                         ) 
                       
                       · 
                       
                         ( 
                         
                           1 
                           + 
                           
                             s 
                             · 
                             
                               
                                 
                                   R 
                                   1 
                                 
                                 · 
                                 
                                   R 
                                   2 
                                 
                               
                               
                                 
                                   R 
                                   1 
                                 
                                 + 
                                 
                                   R 
                                   2 
                                 
                               
                             
                             · 
                             C 
                           
                         
                         ) 
                       
                     
                   
                   = 
                   
                     
                       L 
                       C 
                     
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         2 
                          
                         
                           L 
                           
                             C 
                              
                             
                                 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0041]    From equations (9) and (10), one may derive the following design equations for the sensor circuit  14   1  of  FIG. 3 : 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       R 
                       1 
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         R 
                         2 
                       
                     
                   
                   = 
                   
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         L 
                         C 
                       
                     
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         2 
                          
                         
                           L 
                           C 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       R 
                       2 
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         R 
                         2 
                       
                     
                   
                   = 
                   
                     
                       L 
                       C 
                     
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         2 
                          
                         
                           L 
                           C 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       L 
                       lk 
                     
                     DCR 
                   
                   = 
                   
                     
                       
                         
                           R 
                           1 
                         
                         · 
                         
                           R 
                           2 
                         
                       
                       
                         
                           R 
                           1 
                         
                         + 
                         
                           R 
                           2 
                         
                       
                     
                     · 
                     
                       C 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
         [0042]    Therefore, by selecting the components R 11 =R 1 , R 21 =R 2 , and C 1 (L C1 =L C , L lk1 =L lk , and DCR 1 =DCR are assumed to be known quantities for purposes of this disclosure) of the sensor circuit  14   1  such that they satisfy the design equations (11)-(13), the results are that I FB1 ≈i 1 ·DCR 1 , and therefore, that I FB1  has approximately the same phase as i 1 , and has an amplitude that is approximately proportional to (i.e., that has approximately the same amplitude profile as) the amplitude of i 1 . Furthermore, because at least in some applications the design equation (12) may be redundant, one may design the sensor circuit  14   1  by selection component values that satisfy only the equations (11) and (13). 
         [0043]      FIGS. 4A-4D  are respective timing diagrams of I FB1 , i 1 , I FB2 , and i 2  of  FIG. 3  for a two phase embodiment of the power-supply  10  of  FIG. 1  for the following component values, which satisfy the design equations (11)-(13): L lki =L lk2 =200 nanohenries (nH), L C1 =L C2 =500 nH, DOR 1 =DCR 2 =2 milliohms (mΩ), C 1 =C 2 =0.01 microfarads (μF), R 11 =R 22 =17 kiloohms (KΩ), and R 12 =R 21 =24 KΩ. Although I FB1  and I FB2  are voltages, the timing diagrams of  FIGS. 4A and 4C  are in units of Amperes (current) because I FB1  and I FB2  respectively represent the phase currents i 1  and i 2 . For purposes of plotting only, I FB1  and I FB2  have been normalized by setting DCR 1 =DCR 2 =1 such that I FB1  has the same amplitude profile and phase as i 1 , and I FB2  has the same amplitude profile and phase as i 2 . Of course the power-supply controller  20  ( FIG. 1 ) may adjust the amplitude of the I FB1  and I FB2  within the controller by a scale factor other than unity. 
         [0044]    Referring again to  FIGS. 1-4D , alternate embodiments of the disclosed technique for designing the sensor circuits  14   1 - 14   n  are contemplated. For example, equations (1)-(13) may be extrapolated for the design of the power supply  10  having more than n=2 magnetically coupled phases  12   1  and  12   2  (i.e., for n&gt;2). But the equations (1)-(13) may also be suitable for an embodiment of the power supply  10  having only pairs of magnetically coupled phases  12 , e.g., phase  12   1  coupled to phase  12   2  only, phase  12   3  coupled to phase  12   4  only, and so on. Furthermore, one may modify the equations (1)-(13) to cover an embodiment of the power supply  10  where one or more components of the sensor circuit  14  and winding  18  of one phase  12  have different values than the corresponding one or more components of the sensor circuit  14  and winding  8  of another phase  12 . Moreover, one may modify equations (9)-(13) so that they are not simplified based on the assumption that the controller  20  switches the phases  12  at a relatively high frequency. In addition, although the sensor circuits  14  are described as being useful to sense the currents through magnetically coupled phases  12 , one may use the sensor circuits  14  or similar sensor circuits to sense the currents through magnetically uncoupled phases. Furthermore, the disclosed technique, or a modified version thereof, may be suitable for designing the sensor circuits of a multiphase power supply other than a buck converter. Moreover, although an embodiment of a technique for designing the sensor circuit  14 , is disclosed the same or a similar embodiment may be used to design the sensor circuit  14   2 . In addition, although the sensor circuits  14   1 - 14   n  are disclosed as each being coupled to the intermediate nodes INT 1 -INT 2 , the sensor circuits may be coupled to other non-output nodes of phases  12   1 - 12   n . The output node of a phase  12  is the node where all of the phases are coupled together, for example the node  11  in  FIG. 2  where the filter inductor  28  is omitted. 
         [0045]    Referring again to  FIG. 3 , one may wish to include the optional resistor RC 1  in the sensor circuit  14   1  to scale the voltage I FB1  such that K 1 ·I FB1 =i 1 ·DCR 1 , and thus I FB1 =(i 1 ·DCR 1 )/K 1 , where K 1 ≦1 (K 1 =1 when RC 1  is omitted). When RC 1  is present and n=n, then the design equations (11) and (13) may be respectively modified into the following equations, assuming that the values of L c , L lk , and DCR are the same for each winding  18   1 - 18   n  (because the design equation (12) may redundant as discussed above, the equation into which one may modify equation (12) when RC 1  is present is omitted for brevity): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       R 
                       11 
                     
                     
                       
                         
                           R 
                           11 
                         
                         + 
                         
                           R 
                           21 
                         
                         + 
                         … 
                         + 
                         
                           R 
                           
                             n 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                       
                        
                       
                           
                       
                     
                   
                   = 
                   
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         L 
                         C 
                       
                     
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         nL 
                         C 
                       
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       L 
                       lk 
                     
                     DCR 
                   
                   = 
                   
                     
                       
                         
                           R 
                           11 
                         
                         · 
                         
                           R 
                           21 
                         
                         · 
                         … 
                         · 
                         
                           R 
                           
                             n 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         · 
                         
                           RC 
                           1 
                         
                       
                       
                         
                           R 
                           11 
                         
                         + 
                         
                           R 
                           21 
                         
                         + 
                         … 
                         + 
                         
                           R 
                           
                             
                               n 
                                
                               
                                   
                               
                                
                               1 
                             
                              
                             
                                 
                             
                           
                         
                       
                     
                     · 
                     
                       C 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
         [0046]    And K 1  is given by the following equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     K 
                     1 
                   
                   = 
                   
                     
                       
                         ( 
                         
                           
                             R 
                             11 
                           
                           + 
                           
                             R 
                             21 
                           
                           + 
                           … 
                           + 
                           
                             R 
                             
                               n 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                         
                         ) 
                       
                       · 
                       
                         RC 
                         1 
                       
                     
                     
                       
                         
                           ( 
                           
                             
                               R 
                               11 
                             
                             + 
                             
                               R 
                               21 
                             
                             + 
                             … 
                             + 
                             
                               R 
                               
                                 n 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           ) 
                         
                         · 
                         
                           RC 
                           1 
                         
                       
                       + 
                       
                         
                           R 
                           11 
                         
                         · 
                         
                           R 
                           21 
                         
                         · 
                         
                           … 
                           . 
                         
                         · 
                         
                           R 
                           
                             n 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   16 
                   ) 
                 
               
             
           
         
       
     
         [0047]    The modified design equations for the components of the sensor circuits  14   2 - 14   n  and the equations for the scale factors K 2 -K n  may be respectively similar to equations (14)-(16). Furthermore, equations (14)-(16) may be modified where L c , L lk , and DCR are not the same for each winding  18   1 - 18   n . 
         [0048]      FIG. 5  is schematic diagram of a portion of a two-phase (n=2) version of the power supply  10  of  FIG. 1  including the windings  18   1  and  18   2  (which we magnetically coupled) and another embodiment of the sensor circuits  14   1  and  14   2 . For purposes of discussion, it is assumed that the filter inductor  28  is omitted from the power supply  10 . For brevity, only the sensor circuit  14   1  is discussed, it being understood that the other sensor circuit  14   2  is similar except for possibly the values of the components that compose the sensor circuit  14   2 . 
         [0049]    The sensor  14   1  includes a capacitor C 1  across which the sense signal I FB1  (here a voltage signal) is generated, an optional scaling resistor RC 1  across the capacitor C 1 , a resistor R 1  coupled to the capacitor C 1 , and a resistor R 11 , which is coupled between the phase intermediate node INT 1  and the resistor R 1 . The resistors R 11  and R 1  couple to C 1  a signal (a current in this embodiment) that represents the portion of the phase current i 1  that the switching transistors  22   1  and  24   1  ( FIG. 1 ) cause to flow through the winding  18   1 . 
         [0050]    Similarly, the sensor circuit  14   2  includes a capacitor C 2  across which the sense signal I FB2  (here a voltage signal) is generated, an optional scaling resistor RC 2  across the capacitor C 2 , a resistor R 2  coupled to the capacitor C 2 , and a resistor R 22 , which is coupled between the phase intermediate node INT 2  and the resistor R 2 . The resistors R 22  and R 2  couple to C 2  a signal (a current in this embodiment) that represents the portion of the phase current i 2  that the switching transistors  22   2  and  24   2  ( FIG. 1 ) cause to flow through the winding  18   2 . 
         [0051]    The sensor circuits  14   1  and  14   2  also “share” a resistor R 12 , which is coupled between the resistors R 1  and R 2  and also between the resistors R 11  and R 22 . The resistors R 22 , R 12 , and R 1  couple to C 1  a signal (a current in this embodiment) that represents the portion of the phase current i 1  that the phase current i 2  magnetically induces in the winding  18   1 . That is, the resistors R 22 , R 12 , and R 1  couple to C 1  a current that is proportional to the portion of i 1  that i 2  magnetically induces in the winding  18   1 . Similarly, the resistors R 11 , R 12 , and R 2  couple to C 2  a signal (a current in this embodiment) that represents the portion of the phase current i 2  that the phase current i 1  magnetically induces in the winding  18   2 . 
         [0052]    One may extrapolate the sensor circuit  14   1  for use in the power supply  10  ( FIG. 1 ) where n&gt;2 by including in the sensor circuit a respective resistive network between the node INT I  and all the other nodes INT 2 -INT n , where each resistive network may be similar to the network of resistors R 11 , R 12 , and R 22 , except possibly for the values of these resistors. The resistor R 1  would be coupled to the respective nodes of these resistive networks corresponding the node between R 11  and R 22  in  FIG. 5 . And the resistors corresponding to the resistor R 2  in  FIG. 5  would be respectively coupled to the nodes corresponding to the node between R 12  and R 22  in  FIG. 5 . 
         [0053]    One may extrapolate the sensor circuit  14   2  for use in the power supply  10  ( FIG. 1 ) where n&gt;2 in a similar manner, and the sensor circuits  14   3 - 14   n  may each be similar to the sensor circuits  14   1  and  14   2 , except possibly for the values of the resistors. 
         [0054]    Still referring to  FIG. 5 , in an embodiment one may derive design equations for the sensor circuit  14   1  in a manner similar to that presented above in conjunction with  FIG. 3 . Assuming an embodiment of the sensor circuit  14   1  where L c1 =L c2 =L c , L lk1 =L lk2 =L lk , DCR 1 =DCR 2 =DCR, R 11 =R 22 =R A , and R 12 =R B , the design equations for such an embodiment are as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       R 
                       A 
                     
                     
                       
                         R 
                         A 
                       
                       + 
                       
                         R 
                         B 
                       
                     
                   
                   = 
                   
                     
                       L 
                       C 
                     
                     
                       
                         L 
                         lk 
                       
                       + 
                       
                         2 
                          
                         
                           L 
                           C 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       L 
                       lk 
                     
                     DCR 
                   
                   = 
                   
                     
                       R 
                       1 
                     
                     · 
                     C 
                   
                 
               
               
                 
                   ( 
                   18 
                   ) 
                 
               
             
             
               
                 
                   
                     K 
                     1 
                   
                   = 
                   
                     
                       RC 
                       1 
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         RC 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   19 
                   ) 
                 
               
             
           
         
       
     
         [0055]    Referring again to  FIGS. 1 and 5 , alternate embodiments of the disclosed technique for designing the sensor circuits  14   1 - 14   n  of  FIG. 5  are contemplated. For example, equations (17)-(19) may be modified for the design of the power supply  10  having more than n=2 magnetically coupled phases  12   1  and  12   2  (i.e., for n&gt;2). But the equations (17)-(19) may also be suitable for an embodiment of the power supply  10  having only pairs of magnetically coupled phases  12 , e.g., phase  12   1  coupled to phase  12   2  only, phase  12   3  coupled to phase  12   4  only, and so on. Furthermore, one may modify the equations (17)-(19) to cover an embodiment of the power supply  10  where one or more components of the sensor circuit  14  and winding  18  of one phase  12  have different values than the corresponding one or more components of the sensor circuit  14  and winding  18  of another phase  12 . Moreover, one may modify equations (17)-(19) so that they are not simplified based on the assumption that the controller  20  switches the phases  12  at a relatively high frequency. In addition, although the sensor circuits  14  of  FIG. 5  are described as being useful to sense the currents through magnetically coupled phases  12 , one may use the sensor circuits  14  or similar sensor circuits to sense the currents through magnetically uncoupled phases. Furthermore, the disclosed technique, or a modified version thereof, may be suitable for designing the sensor circuits of a multiphase power supply other than a buck converter. Moreover, although an embodiment of a technique for designing the sensor circuit  14 , is disclosed, the same or a similar embodiment may be used to design the sensor circuit  14   2 . In addition, although the sensor circuits  1404   2  are disclosed as each being coupled to the intermediate nodes INT 1 -INT 2 , the sensor circuits  14   1 - 14   2  (and  14   3 - 14   n  of present) may be coupled to other non-output nodes of the phases  12   1 - 12   2  (and  12   3 - 12   n  of present). 
         [0056]      FIG. 6  is a block diagram of an embodiment of a system  40  (here a computer system), which may incorporate a multiphase power supply  42  (such as the multiphase power supply  10  of  FIG. 1 ) that includes one or more phase-current sensor circuits that are the same as or that are similar to embodiments of one or more of the current sensor circuits  14  of  FIGS. 2 ,  3 , and  5 . 
         [0057]    The system  40  includes computer circuitry  44  for performing computer functions, such as executing software to perform desired calculations and tasks. The circuitry  44  typically includes a controller, processor, or one or more other integrated circuits (ICs)  46 , and the power supply  42 , which provides power to the IC(s)  46 —these IC(s) compose(s) the load of the power supply. The power supply  42 , or a portion thereof, may be disposed on the same IC die as one or more of the ICs  46 , or may be disposed on a different IC die. 
         [0058]    One or more input devices  48 , such as a keyboard or a mouse, are coupled to the computer circuitry  44  and allow an operator (not shown) to manually input data thereto. 
         [0059]    One or more output devices  100  are coupled to the computer circuitry  44  to provide to the operator data generated by the computer circuitry. Examples of such output devices  50  include a printer and a video display unit. 
         [0060]    One or more data-storage devices  52  are coupled to the computer circuitry  44  to store data on or retrieve data from external storage media (not shown). Examples of the storage devices  52  and the corresponding storage media include drives that accept hard and floppy disks, tape cassettes, compact disk read-only memories (CD-ROMs), and digital-versatile disks (DVDs). 
         [0061]    From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of this disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.