Abstract:
The present invention comprises a first means to select all repair fuse cells, using a test mode, and to sense each repair fuse cell state depending on the applied read-out voltage; a logical means to generate decision signals to decide the overerasing state of said repair fuse cells by logically combining sensed signals from said each repair fuse cell; and a second means to read output signals of said logical means.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a circuit to check overerasing of repair fuse cells, and more particularly to a method and a circuit to check overerasing of repair fuse cell for checking the overerasing state of fuse cells by sensing the current flowing in the fuse cells at the state to apply 0V to gates of all fuse cell and a uniform voltage to the drain, entering the sensing output to the logical gate and reading the output of the logical gate through an input/output pad. 
     2. Description of the Prior Art 
     Programming repair fuse cells allows repairing defective cells. Then the initial fuse cells should have been erased, and the threshold voltage of the cells should also be adjusted low with enough margins. Where the initial fuse cells were programmed, the normal cells will be repaired since the fuse cells were programmed although the normal cells did not need repairing. Thus undesirable repair occurs so that redundant cells for repairing are reduced. 
     On the other hand, the threshold voltage of the initial fuse cells should be low enough to remove the problem to cause inferiority by access to the redundant cells for repairing to act differently from the main array cells by programming by charge gain of fuse cells that may be generated during testing under some adverse conditions. Accordingly, at the early stage of testing, the fuse cells for repairing should be erased. and the threshold voltage should also be adjusted low. For the process, a circuit to check whether fuse cells are erased and, at the same time, to adjust the threshold voltage of the cells to be low enough is needed. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a circuit to check overerasing of repair fuse cells which can check whether the repair fuse cells are erased, and can adjust the threshold voltage of cells to be low enough at the same time. 
     The present invention to achieve the above objects comprises: a first means to select all repair fuse cells using a test mode and to sense the repair fuse cell state respectively in accordance with the applied read-out voltage; a logical means to generate decision signals to decide the overerasing state of said repair fuse cells by logically combining the sensed signals from each repair fuse cells; and a second means to read output signals of said logical means. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above object, and other features and advantages of the present invention will become more apparent by describing the preferred embodiment thereof with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram to show the relation of a fuse cell block and the peripheral circuits to apply the present invention; 
     FIG. 2 is a detailed circuit diagram of a power-up reset circuit and a repair data sensing delay circuit in FIG. 1; 
     FIG. 3 is waveforms for explaining FIG. 2; 
     FIG. 4 is a detailed circuit diagram of a reference voltage generator in FIG. 1; 
     FIG. 5 is a detailed circuit diagram of a fuse cell gate bias control signal generator in FIG. 1; 
     FIG. 6 is a detailed circuit diagram of the fuse cell drain bias control signal generator in FIG. 1; 
     FIG. 7 is a circuit diagram to describe signal combination for generating fuse cell reset signals; 
     FIG. 8 is a circuit diagram of the fuse cell gate bias control decoder in FIG. 1; and 
     FIG. 9 is a detailed circuit diagram of a circuit to check overerasing of repair fuse cells in accordance with the present invention. 
     Similar reference characters refer to similar parts in the several views of the drawings. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the preferred embodiments of the present invention, and examples of which are illustrated in the accompanying drawings. 
     FIG. 1 is a block diagram to show the relation of a fuse cell block and peripheral circuits to apply the present invention. 
     A power-up reset circuit  1  generates a reset signal RST an inverted reset signal RSTb at any moment after supplying the supply voltage V CC  and they are entered to the repair data sending delay circuit  2  and the fuse cell blocks  7 A to  7 N. The circuit to check overerasing of repair fuse cells in accordance with the present invention is located in the fuse cell blocks  7 A to  7 N. 
     The repair data sensing delay circuit  2  outputs the reference fuse cell signal REFCAMb by entering the reset signal FST and the inverted reset signal RSTb from the power-up resent circuit  1 , the reference voltage VREF from the reference voltage generator  3 , and the fuse cell gate signal CGATE from the fuse cell gate bias control decoder  6 . 
     The reference voltage generator  3  generates the reference voltage VREF according to the reference fuse cell signal REFCAMb from the repair data sensing delay circuit  2  and the reference voltage VREF is inputted to the fuse cell blocks  7 A to  7 N. 
     The fuse cell gate bias control signal generator  4  generates the fuse cell reset signal XRST which is apply to the fuse cell gate bias control decoder  6  according to the first power VPPIN to apply the read-out voltage and the program voltage and the cell program enable signal TPGMCEN. 
     The fuse cell drain bias control signal generator  5  generates the fuse cell select signal TCSEL according to the second power VPPIY to apply the read-out voltage and the program voltage, and the cell program enable signal TPGMCEN, and allows the signal TCSEL entered to the fuse cell blocks  7 A to  7 N. 
     The fuse cell gate bias control decoder  6  generates the fuse cell gate signal CGATE according to the third power VPPX to apply the program voltage and read-out voltage, the fourth power VEEX to supply decoder signals XPREA and erasing voltage, and fuse cell reset signals XRST, and then outputs the signal(GATE) to the repair data sensing delay circuit  2  and the fuse cell blocks  7 A to  7 N. The decoder signal XPREA, the program and the read-out bias enable signal, is that the cell erasing enable signal TERACEN, the fuse cell verify signal TCAMVERIFYr and the reference fuse cell signal REFCAMb are logically combined by the NOR gate. 
     The fuse cell blocks  7 A to  7 N include the circuit to check overerasing of repair fuse cells in accordance with the present invention, and display the result after verifying the cell status according to multiple signals as described above. 
     FIG. 2 is a detailed circuit diagram of a power-up reset circuit and a repair data sensing delay circuit in FIG.  1 . 
     A first NMOS transistor N 1  of the repair data sensing delay circuit  2  is connected between a latch circuit  11  and a second NMOS transistor N 2 , and operates by the inverted reset signal RSTb outputted from the power-up reset circuit  1 . A first PMOS transistor P 1  is connected between a power terminal and the latch circuit  11 , and operates by the inverted reset signal RSTb. The second NMOS transistor N 2  is connected between the first NMOS transistor N 1  and the fuse cell M 1 , and operates by the reference voltage VREF generated from the reference voltage generator  3 . The fuse cell M 1  is connected to a second NMOS transistor(N 2 ); the fuse cell gate signal CGATE is entered to the gate electrode of the fuse cell M 1 ; and the fifth power VSSC is supplied to a drain electrode of the fuse cell. The latch circuit connected between the first PMOS transistor P 1  and the first NMOS transistor N 1  comprises third and fourth inverters I 3  and I 4 , and latches input data. A third NMOS transistor N 3  connected between the latch circuit  11  and the ground terminal V SS  operates by the reset signal RST from the power-up reset circuit  1 . The data latched to the latch circuit  11  are entered to the reference voltage generator  3  after being delayed by the 2 stage RC delay circuit composed by a fifth inverter I 5  and a first capacitor C 1 , a sixth inverter I 6  and a second capacitor C 2 . That is the delay circuit outputs a reference cell signal REFCAMb. 
     A method to drive a repair data sensing delay circuit constituted as described above is described in the following with reference to waveforms in FIG.  3 . 
     At the time of power-up as shown in T 1  of FIG. 3, a reset signal RST is generated from the power-up reset circuit  1  at any time after applying supply voltage V CC . The reset signal RST is inverted to the low state RSTb by the second inverter I 2  and applied to the gate of the first NMOS transistor N 1  and the first PMOS transistor P 1 . Thus, the first NMOS transistor N 1  is turned off, but the first PMOS transistor P 1  is turned on. Then, since the fuse cell M 1  keeps the initial erasing state, supply voltage V CC  is applied via the first PMOS transistor P 1  and a first node Q 1  keeps the high state. Since the potential of the first node Q 1  is inverted to the low state via the third inverter I 3  of the latch circuit  11 , the second node Q 2  becomes the low state. However, a third NMOS transistor N 3  is turned on by the high reset signal RST, and thus the potential of the second node Q 2  keeps the low state. The low potential of the second node Q 2  is delayed for a specified time by the 2(two) state RC delay circuit of the fifth inverter I 5  and the first capacitor C 1 , the sixth inverter I 6  and the second capacitor C 2 , and then outputted at the low state. This signal is entered to the reference voltage generator  3  as a reference fuse cell signal REFCAMb. The reference voltage generator  3  generates the reference voltage VREF and allows the voltage entered to the second NMOS transistor N 2 . Also, the potential of the fuse cell gate signal CGATE inputted to a gate of the fuse cell M 1  rises by the applied supply voltage V CC . 
     As shown in T 2  of FIG. 2, the reset signal RSTb inverted of the second inverter I 2  continuously rises where supply voltage V CC  is continuously applied and the reset signal RST becomes the low state by stopping reset operation in the power-up reset circuit  1 . The inverted reset signal RSTb turns on the first NMOS transistor N 1  and turns off the first PMOS transistor P 1 . Thus, potential of the first node Q 1  is inverted to a low state from high state and delayed for a specified time through the RC delay circuit. The output of the RC delay circuit becomes a high state. This signal is entered to the reference voltage generator  3  as a reference fuse cell signal REFCAMb; removes the continuously rising reference voltage VREF; allows the reference voltage VREF to be entered to the gate of the second NMOS transistor N 2 ; and then turns off the second NMOS transistor N 2 . Also, the potential of the fuse cell M 1  gate signal CGATE entered the gate of the fuse cell M 1  continuously rises with the applied supply voltage V CC , but the signal CGATE gets to the low state after receiving the reference fuse cell signal REFCAMb, and stops sensing. 
     T 3  and T 4  in FIG. 3 show the interval to finish all repair cell sensing, and thus sensing is performed at the early state of power-up as the advantage of the present invention. 
     FIG. 4, as a detailed circuit diagram of the reference voltage generator in FIG. 1, is constituted as described below. 
     A first inverter I 11  inverts the reference fuse cell signal REFCAMb from the repair data sensing delay circuit  2 . The NOR gate NOR 1  logically combines output signals of the first inverter I 11  and the fuse cell verify signal TCAMVERIFYr. The first PMOS transistor P 11  is connected between the power terminal and the second PMOS transistor P 2 , and operates by the output signal of the NOR gate NOR. The second PMOS transistor P 12  is connected between the first PMOS transistor P 11  and the output node Q 11 , and operates by the potential of the output node Q 11 . The first NMOS transistor N 11  is connected between the output node Q 11  and the second NMOS transistor N 12 , and operates by the potential of the output node Q 11 . The second NMOS transistor N 12  is connected between the first NMOS transistor N 11  and the ground terminal V SS , and operates by the potential flowing through the first NMOS transistor N 11 . The third NMOS transistor N 13  is connected between the output node Q 11  and the ground terminal V SS , and operates to output signals of the NOR gate NOR 1 . 
     A method to drive the reference voltage generator constituted as above is described below. 
     The reference fuse cell signal REFCAMb having a low state from the repair data sensing delay circuit  2  is inverted by a first inverter I 11  at a high state and applied to the NOR gate NOR 1 . The fuse cell verify signal TCAMVERIFYr having a low state is entered to the other input terminal of the NOR gate NOR 1  and the signal having a low state is outputted at an output terminal of the NOR gate NOR 1 . The signal having a low state turns on the first PMOS transistor P 11  and turns off the third NMOS transistor N 13 . Thus, the first PMOS transistor P 11 , the second PMOS transistor P 12 , the first NMOS transistor N 11  and the second NMOS transistor N 12  are turned on and an uniform voltage VREF is generated. 
     The reference fuse cell signal REFCAMb having a high state from the repair data sensing delay circuit  2  is inverted by the first inverter I 11  at a low state and then applied to the NOR gate NOR 1 . The fuse cell verify signal TCAMBERIFYr having a low state is entered to the other input terminal of the NOR gate NOR 1  and the output of the NOR gate NOR 1  becomes a high state. The signal having the high state turns off the first PMOS transistor P 11  and turns on the third NMOS transistor N 13 . Then the potential of the output node Q 11  keeps the ground voltage and the voltage is outputted as reference voltage VREF. 
     In starting a fuse cell testing, namely when the fuse cell verify signal TCAMVERIFYr is applied at the high state, the operation is described in the following. The reference fuse cell signal REFCAMb having a low state from the repair data sensing delay circuit  2  is inverted by the first inverter I 11  at a high state applied to the NOR gate NOR 1 . The fuse cell verify signal TCAMVERIFYr having a high state is entered to the other input terminal of the NOR gate NOR 1  and the output of the NOR gate NOR 1  becomes a low state. The signal having low state turns on the first PMOS transistor P 11  and turns off the third NMOS transistor N 13 . Thus supply voltage V CC  is applied via the first PMOS transistor P 11 . Accordingly, the voltage to divide the rising supply voltage by the size ratio of a pull-up PMOS transistor and a pull-down NMOS transistor is outputted as the reference voltage V ref . 
     The reference fuse cell signal REFCAMb having a high state from the repair data sensing delay circuit  2  is inverted by the first inverted I 11  at a low state and applied to the NOR gate NOR 1 . The fuse cell verify signal TCAMVERIFYr having high state is entered to the other input terminal of the NOR gate NOR 1  and the output of the NOR gate NOR 1  becomes low state. The signal having a low state turns on the first PMOS transistor P 11  and turns off the third NMOS transistor N 13 . Thus supply voltage V CC  is applied via the turned-on first PMOS transistor P 11 . 
     As described above, in starting the fuse cell testing, that is, where a fuse cell verify signal TCAMVERIFYr is applied at the high state, the reference voltage VREF of uniform potential is outputted without regard to the reference fuse cell signal REFCAMb from the repair data sensing delay circuit  2 . On the other hand, where fuse cell testing is not performed, the reference voltage VREF of uniform potential is generated by only when the reference fuse cell signal REFCAMb having the low state is applied at the low state. 
     FIG. 5, as a detailed circuit diagram of a fuse cell gate bias control signal generator, is constituted as described below. 
     The first PMOS transistor P 21  is connected between the first power VPPIN to apply the read-out and program voltage, and the first node Q 21 , and operates by the potential of the second node Q 21 . The second PMOS transistor P 22  is connected between the first power VPPIN and the second node Q 22 , and operates by the potential of the first node Q 21 . The third NMOS transistor N 3  connected between the first node Q 21  and the first NMOS transistor N 21 , and the fourth transistor N 24  connected between the second node Q 22  and the second NMOS transistor N 22  always keep the turned-on state since supply voltage V CC  is applied to the gate terminal of the NMOS transistor N 23  and N 24 . The first NMOS transistor N 21  is connected between the third NMOS transistor N 23  and the ground terminal V SS , and operates by the cell program enable signal TPGMCEN. The second NMOS transistor N 22  is connected between the fourth NMOS transistor N 24  and the ground terminal V SS , and operates by the cell program enable signal TPGMCEN inverted and delayed via the first, second and third inverters I 21 , I 22  and I 23 . The reset signals XRSTs, are entered to the fuse cell gate bias control decoder  6 . 
     A method to drive fuse cell gate bias control signal generator is constituted above is described below. 
     Supply voltage V CC  is applied to each gate terminal of the third and fourth NMOS transistors N 23  and N 24  so that they are always keep the turned-on state. At this state, if the cell program enable signal TPGMCEN is applied at the high state via the first and second inverters I 21  and I 22  to program cell the first NMOS transistor N 21  is turned and the second NMOS transistor N 22  is turned off by the low signal inverted by the third inverter I 23 . Thus, as the first node Q 21  keeps the low potential and the second PMOS transistor P 22  is turned on, the second node Q 22  keeps the high state by the supplied first power VPPIN. By the potential of the second node Q 22  keeping the high state, the first PMOS transistor P 21  is turned off, and the potential of the second node Q 22  keeping the high state is outputted to the fuse cell bias control decoder  6  as a cell reset signal XRST. However, since the cell reset signal XRST is applied as the potential of pumping voltage VPPI for cell programming, the first power VPPIN should supply pumping voltage VPPI in programming. 
     Supply voltage V CC  is applied to each gate terminal of the third and fourth NMOS transistors N 23  and N 24  so that they are always keep the turned-on state. At this state, if the cell program enable signal TPGMCEN is applied at the low state via the first and second inverters I 21  and I 22  to read or erase cells, the first NMOS transistor N 21  and the second NMOS transistor N 22  is turned on by the high signal inverted by the third inverter I 23 . Thus, as the second node Q 22  keeps the low potential and the first PMOS transistor P 21  is turned on, the first node Q 21  keeps the high state by the supplied first power VPPIN. By the potential of the first node Q 21  keeping high, the second PMOS transistor P 22  is turned off, and the potential of the second node Q 22  keeping low is outputted to the fuse cell bias control decoder  6  as a cell reset signal XRST. 
     FIG. 6, as a detailed diagram of a cell drain bias control signal generator, is constituted as described below. 
     The first PMOS transistor P 31  is connected between the second power VPPY to apply the read-out and program voltage, and the first node Q 31 , and operates by the potential of the second node Q 32 . The second PMOS transistor P 32  is connected between the second power VPPY and the second node Q 32 , and operates by the potential of the first node Q 31 . The third NMOS transistor N 33  connected between the first node Q 31  and the first NMOS transistor N 31 , and the fourth transistor N 34  connected between the second node Q 32  and the second NMOS transistor N 32  always keep the turned-on state since supply voltage V CC  is applied to the gate terminal. 
     The first NMOS transistor N 31  is connected between the third NMOS transistor N 33  and the ground terminal V SS , and operates by the cell program enable signal TPGMCEN by the first and second inverters I 31  and I 32 . The second NMOS transistor N 32  is connected between the fourth NMOS transistor N 34  and the ground terminal V SS , and operates by the cell program enable signal TPGMCEN delayed and inverted via the first, second and third inverters I 31 , I 32  and I 33 . The signals outputted by the above process, as fuse cell select signals TCSEL, are entered to the circuit to check overerasing of repair fuse cells, in accordance with the present invention, in the fuse cell blocks  7 A to  7 N. 
     A method to drive a fuse cell drain bias control signal generator constituted as above may be described below. 
     First, since supply voltage V CC  is applied to each gate terminal of the third and fourth NMOS transistors N 33  and N 34  so that they are always keep the turned-on state. At this state, if the cell program enable signal TPGMCEN is applied at the high state via the first and second inverters I 31  and I 32  to program cells, the first NMOS transistor N 31  is turned off and the second NMOS transistor N 32  is turned on a low signal inverted by the third inverter I 33 . Thus, as the first node Q 31  keeps low potential and the second PMOS transistor P 32  is turned on, the second node Q 32  keeps the high state by the supplied third power VPPY. By the potential of the second node Q 32  keeping high, the first PMOS transistor P 31  is turned off, and the potential of the second node Q 32  keeping high is entered to the circuit to check overerasing of repair fuse cells as a fuse cell select signal TCSEL. 
     Supply voltage V CC  is applied to each gate terminal of the third and fourth NMOS transistors N 33  and N 34  so that they are always keep the turned-on state. At this state, if the cell program enable signal TPGMCEN is applied at the low state via the first and second inverters I 31  and I 32  to read or erase cells, the first NMOS transistor N 31  is turned off and the second NMOS transistor N 32  is turned on the high signal inverted by the third inverter I 33 . Thus, as the second node Q 32  keeps low potential and the first PMOS transistor P 31  is turned on, the first node Q 21  keeps high state by the supplied first power VPPY. By the potential of the first node Q 31  keeping high state, the second PMOS transistor P 32  is turned off, and the potential of the second node Q 32  keeping low state is entered to the circuit to check overerasing of repair fuse cells as a fuse cells elect signal TCSEL. 
     FIG. 7 shows logically to combine the cell erase enable signal TERACEN, the fuse cell verify signal TCAMVERIFYr and the reference fuse cell signal REFCAMb in the NOR gate NOR 3 , to generate the fuse cell reset signal XRST. 
     FIG. 8, as a detailed circuit diagram of a fuse cell gate bias control decoder, is constituted as described below. 
     The first PMOS transistor P 41  is connected between the third power VPPX and the first node Q 41 , and operates by the fuse cell reset signal XRST. The second PMOS transistor P 42  is connected between the third power VPPX and the first node Q 41 , and operates by the potential of the output terminal CGATE. The third PMOS transistor P 43  is connected between the third power VPPX and the output terminal CGATE, and operates by the potential of the first node Q 41 . The first NMOS transistor N 41  is connected between the first node Q 41  and the ground terminal V SS , and operates by the decoder signal XPREA. The second NMOS transistor N 42 , that is, the triple well NMOS transistor, is connected between the fourth power VEEX and the output terminal CGATE, and operates by the supply voltage V CC  and the fourth power VEEX. The signal outputted to the output terminal is a fuse cell gate signal CGATE. 
     Driving bias condition of a fuse cell gate bias control decoder constituted as described above are shown in the [Table 1]. A method to drive the decoder, using the conditions, is described in the following. 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                                 Program 
                 Erase 
                 Read 
                 Fuse Cell Verify 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 VPPX 
                 VPPI 
                 2 V 
                 Vcc 
                 Vcc 
               
               
                 XRST 
                 VPPI 
                 0 V 
                 0 V 
                 0 V 
               
               
                 VNWELL 
                 Vcc 
                 Vcc 
                 Vcc 
                 Vcc 
               
               
                 XPREA 
                 Vcc 
                 0 V 
                 Vcc or 0 V 
                 0 V 
               
               
                 VEEX 
                 0 V 
                 −9 V 
                 0 V 
                 0 V 
               
               
                 CGATE 
                 VPPI 
                 −9 V 
                 Vcc 
                 0 V 
               
               
                   
               
             
          
         
       
     
     First, for the program mode operation, the third power VPPX keeps the positive pumping voltage VPPI level since the positive pump performs pumping. The fuse cell reset signal XRST rises to the positive pumping voltage VPPI level since the positive pump performs pumping from the 0V level. The fourth power VEEX keeps 0V, that is, the ground voltage V SS . The decoder signal XPREA and the N-well voltage VNWELL keeps supply voltage V CC  level, and thus the fuse cell gate signal CGATE keeps the pumping voltage VPPI level. 
     The first PMOS transistor P 41  is turned off by the pumping voltage VPPI supplied from the fuse cell reset signal XRST. Since the decoder signal XPREA at the high state turns on the first NMOS transistor and thus a path is formed to the ground terminal, the first node Q 41  gets to the low state. Respectively using the potential of the first node Q 41  as input, the third PMOS transistor P 43  is turned on and the second NMOS transistor N 42  which is a triple well NMOS transistor is turned off. Therefore, pumping voltage VPPI is supplied to the output terminal, and the second PMOS transistor P 42  is turned off by the supplied voltage, 
     For the erase mode operation, the third power VPPX keeps 2V, the fuse cell reset signal XRST 0V, and the fourth power VEEX −9V. Since the decoder signal XPREA keeps 0V and the N-well voltage VNWELL does supply voltage V CC , the fuse cell gate signal CGATE is kept at −9V. 
     As the decoder signal XPREA of 0V turns off the first NMOS transistor N 41  and the fuse cell reset signal XRST of 0V turns on the first PMOS transistor P 41 , the first node Q 41  keeps high since 2V is supplied by the third power VPPX. The second NMOS transistor N 42  is turned on the third PMOS transistor P 41  is turned off by the potential of the first node Q 41  at the high state, and thus the output terminal keeps the potential of −9V supplied by the fourth power VEEX. The second PMOS transistor P 42  is turned on by the potential of the output terminal keeping −9V, and thus the first node Q 41  continuously keeps high. 
     For the read-out mode, the third power VPPX keeps the voltage of supply voltage V CC , the fuse cell reset signal XRST 0V, and the fourth power VEEX 0V. Since the decoder signal XPREA keeps supply voltage V CC  or 0V, and the N-well voltage VNWELL the supply voltage V CC  level, thus the fuse cell gate signal CGATE keeps supply voltage V CC . 
     The first node Q 41  keeps low since the first NMOS transistor N 41  is turned on with the supply voltage V CC  supplied by the decoder signal XPREA, and the first PMOS transistor P 41  is turned on by the fuse cell reset signal XRST of 0V. The second NMOS transistor N 42  is turned off and the third PMOS transistor P 43  is turned on by the low potential of the first node Q 41 , and thus the output terminal keeps the potential of supply voltage V CC  supplied by the third power VPPX. As the second PMOS transistor P 42  is turned off by the potential of the output terminal keeping supply voltage V CC , the first node Q 41  continuously keeps low. 
     For fuse cell verify mode, the third power VPPX keeps supply voltage V CC , the fuse cell reset signal XRST 0V, the fourth power VEEX 0V. Since the decoder signal XPREA keeps 0V and the N-well voltage VNWELL the supply voltage V CC  level, thus 0V is kept for the fuse cell gate signal CGATE. 
     Since the first NMOS transistor N 41  is turned off by the decoder signal XPREA of 0V and the first PMOS transistor P 41  is turned on by the fuse cell reset signal XRST of 0V, the first node Q 41  keeps high as the third power VPPX applies supply voltage V CC . The second NMOS transistor N 42  is turned on and the third PMOS transistor P 43  is turned off by the high potential of the first node Q 41 , and thus the output terminal keeps 0V by the fourth power VEEX. As the second PMOS transistor P 42  is turned on by the potential of the output terminal keeping 0V, the first node Q 41  continuously keeps high. 
     FIG. 9, as a circuit diagram of a circuit to check overerasing of repair fuse cells, is constituted as described in the following. 
     The first NMOS transistor N 51  operates by the fuse cell select signal TCSEL generated in a fuse cell drain bias control signal generator  5 , and provides address signals ADDRs to the drain terminal of the fuse cell M 2 . The second NMOS transistor N 52  is connected between a latch circuit  21  and the third NMOS transistor N 53 , and operates by the inverse reset signal RSTb generated from the power-up reset circuit  1 . The third NMOS transistor N 53  is connected between the second NMOS transistor N 52  and the fuse cell M 2 . Therefore, the fuse cell gate signal CGATE is entered to a gate terminal and the fifth power VSSC is applied to a source terminal. The first PMOS transistor P 51  is connected between a power terminal and a latch circuit  21 , and operates by the inverse reset signal RSTb. The latch circuit  21  comprises the first and second inverters I 51  and I 52 ; is connected between the first PMOS transistor P 51  and the second NMOS transistor N 52 ; and performs data latching. The fourth NMOS transistor N 54  is connected between the output terminal of the first inverter I 51  and the ground terminal VSS, and operates by the reset signal RST. The output signal of the latch circuit  21 , after being inverted by the third inverter I 53 , is entered to the first and second transmission gates T 1  and T 2 . The fuse cell verify signal TCAMVERIFYr is entered to the PMOS gate of the first transmission gate T 1  and to the NMOS gate of the second transmission gate T 2 . The fuse cell verify signal TCAMVERIFYr inverted by the fourth inverter I 54  is entered to the NMOS gate of the first transmission gate T 1  and to the PMOS gate of the second transmission gate T 2 . The output of the first transmission gate T 1  is entered to the main memory cell as a fuse cell state signal CAMINFO, and notifies the fuse cell state. The output of the second transmission gate T 2  is entered to the NOR gate NOR 2  with the fail address signal CAM 1  to CAMN, and then logically combined. The output signal of the NOR gate NOR 2  is entered to the input/output pad  31  with the fuse cell verify signal TCAMVERIFYr, and notifies the overerasing state with the fuse cell state verify signal CAMVERINFO. 
     A method driving a circuit to check overerasing of repair fuse cells, constituted in accordance with the present invention, is described in the following. 
     For read-out operation the fuse cell M 2 , cell information is sensed by turning on the third NMOS transistor N 53  and the fuse cell M 2 , using the reference voltage (VREF) supplied for a specified time from the repair data sensing delay circuit, and the potential of the fuse cell gate signal CGATE. The inverted reset signal RSTb rises according to supply voltage V CC . Since the fuse cell verify signal TCAMVERIFYr keeps low, the fuse cell information is transmitted to the main cell. Namely, fuse cells are readed for a specified time T 2  in power-up. 
     Fuse cell M 2  programming is performed according to the cell program enable signal TPGMCEN. The fuse cell gate signal CGATE keeps the potential of pumping voltage VPP 1  since high voltage is applied through the first power VPPIN and the second power VPPIY at the same time with generating the cell program enable signal TPGMCEN. Also, the fuse cell select signal TCSEL keeps the potential of pumping voltage VPPI, the fifth power VSSC 0V, the inverted reset signal RSTb the high state V CC , and 0V is applied as the reference voltage VREF. Thus, an address ADDR for repairing is entered as it is and then supplies voltage Vss is entered to the drain terminal of the fuse cell M 2 . Thus, programming is performed by hot carrier injection. 
     The fuse cell M 2  is erased by the cell erase enable signal TERACEN. The fuse cell gate signal CGATE keeps the potential of −10V with the cell erase enable signal TERACEN, and is applied to a gate of the cell M 2 . To the source terminal, 4V is applied by the fifth power VSSC. Also, 0V for the fuse cell select signal TCSEL and the reference voltage VREF is applied and allows the drain terminal of the fuse cell M 2  to be floating. Accordingly, erasing is performed to the source terminal over FN tunneling. 
     A method to check overerasing in accordance with the present invention is described in the following. Checking overerasing is performed by the generated fuse cell verify signal TCAMVERIFYr. Then, the inverse reset signal RSTb is applied at the high state V CC , and the reference voltage at the high state 2˜3V. 
     Since the first NMOS transistor N 51  is turned off by the fuse cell select signal TCSEL having the low state, the address signal ADDR can not be applied to the drain electrode of the fuse cell M 2 . The second NMOS transistor N 52  is turned on by the high inverse reset signal RSTb, and the third NMOS transistor N 53  by the high reference voltage VREF. Thus, to the drain terminal of the fuse cell M 2 , the voltage reducing, from supply voltage VCC, as much as the gate-source voltage VGS of the second NMOS transistor N 52  and the threshold voltage of the second NMOS transistor N 52  is applied. Then, 0V is applied to the gate terminal of the fuse cell M 2 . However, if the fuse cell M 2  is overerased, current will flow continuously although 0V is applied to the gate electrode of the fuse cell M 2 . Accordingly, the potential of the first node Q 51  keeps low. The potential of the first node Q 51  keeping low is inverted via the first inverter I 51  and the second node Q 52  gets to the high state. The signal at the high state is inverted to the low state via the third inverter I 53 , and then applied to the first and second transmission gates T 1  and T 2 . As the fuse cell verify signal TCAMVERIFYr is applied at the high state, however, the second transmission gate T 2  is turned on and the potential at the low state is applied to the NOR gate NOR 2  by the turned-on gate. To the NOR gate NOR 2 , each cell state outputted from the above process is entered. Namely, multiple fail address signals CAM 1  to CAMN are applied to the NOR gate NOR 2 . If any one of the signals is applied at the high state, thus output gets to the low state. As the result it is decided that overerasing does not occur. If all fuse cells are overerased, the output of the NOR gate NOR  2  is entered to the input/output pad  31  at the high state. Then the input/output pad  31  decides overerasing of all fuse cells and outputs the results as the fuse cell state verify signal CAMVERINF 0 . 
     As described above in accordance with the present invention, since fuse cell erasing for repair may be verified at early stage of testing and early measures are taken for defects that may be detected after testing by several steps, it is possible considerably to reduce production cost. 
     While the present invention has been described and illustrated herein with reference to the certain preferred embodiment thereof, those skilled in the art will recognize the many modifications and enhancements in form and details which can be made therein without departing from the true spirit and scope of the invention.