Abstract:
The invention is a new method for operating a flash EEPROM memory device and in particular for programming and erasing the device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the first semiconductor region, a well terminal inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer, and a control terminal electrically isolated from the charge storing layer by a inter layer dielectric. The method comprises the steps of: applying a first voltage bias of first polarity to the well terminal; allowing a first time period to elapse; applying a second voltage bias of second polarity opposite to the first polarity to the control terminal; resetting the first voltage bias to zero; allowing a second time period to elapse; and resetting the second voltage bias to zero.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    (a) Field of the Invention 
         [0002]    This invention relates to the operation of a non volatile flash memory device and in particular to programming and erasing the device by manipulating the stored charge within. 
         [0003]    (b) Description of the Related Art 
         [0004]    A flash EEPROM device is a semiconductor device having non volatile memory properties which can be electrically programmed and erased. The non volatile memory properties enable the device to retain stored information once the power is turned off. The information is in the form of electrons stored within the floating gate. Devices of this type are described in U.S. Pat. Nos. 4,698,787 [1] and 5,077,691, [2] all of which are incorporated herein by reference. Other similar devices of this type are also described in U.S. Pat. Nos. 5,243,559, [3] 5,361,235, [4] 5,457,652, [5] 5,790,460 [6] and 5,572,464, [7] all of which are incorporated herein by reference. 
         [0005]    Flash EEPROM devices are electrically erasable, programmable, read-only memory devices, which are electrically programmed and erased using on chip high and negative voltage generation circuitry. Data is stored in a binary format in the device in a manner that the device is set to a programmed state and reset to an erased state. Programming the device is accomplished by storing electrons in a floating gate or charge storing layer usually by means of tunneling or hot carrier injection. Erasing the device is done by removing the charge usually by means of tunneling. 
         [0006]    In the prior art there are several programming and erase techniques for a flash memory mostly based on the physical phenomena of charge tunneling through a potential barrier. Implementation of tunneling erase techniques requires the usage of large electrical field across the dielectric between the floating gate and the well. These high electrical fields are known to generate reliability issues that degrade the quality of the dielectric which would eventually cause device failure. As devices advance further into sub micron dimensions, the intensity of the electric fields grow higher to become a dominating factor limiting the device scale down process. 
         [0007]    Conventional flash device erase is achieved by application of a large negative voltage to the control gate and simultaneous application of a moderate positive voltage to the source region. This technique is usually referred to as Negative Gate Source Erase (NGSE). A variation to this method uses both source and drain regions in the erase process at the same time with the exact same bias operation methodology.  FIG. 1  shows a prior art flash device using Fowler-Nordheim tunneling for NGSE. The device  9  is fabricated on a P-type substrate  10  which is maintained at ground potential, while a large negative potential Vg of about −11V is applied to the control gate  11  and simultaneously a positive potential Vs of about 5V is applied to the source region  12 , fabricated from an n+ type semiconductor inside an n− region  15 . The drain region  8  is kept floating throughout the process. The electrical field formed across the dielectric layer  19  between the floating gate and the substrate would yield a tunneling current draining the electrons stored in the floating gate. 
         [0008]    This erase scheme suffers from a reliability issue caused by “hot hole” injection from the substrate  10  into the tunneling dielectric  19  [I-III]. Since the source region  16  is reversed biased during the erase operation, a band to band tunneling current is present at the surface  17 . This tunneling current produces energetic holes that are attracted by the floating gate to source electric field and have a probability for tunneling into the floating gate. This probability is directly related to the magnitude of this electric field. Thus, the “hot hole” current has a strong dependency on the electric field and imposes yet another limit on device sizing as well as on operation voltage levels. The stronger the electric field the larger the tunneling current and vice versa. These “hot hole” cause damage to the semiconductor insulator interface  17  and the dielectric layer  19  by generating interface states and inter dielectric traps. Given enough time, these traps would line up to cause a breakdown of the insulator layer and rend the device useless, a phenomena known as Time Dependent Dielectric Breakdown (TDDB). TDDB theory presents an exponential dependency of the breakdown probability and time to failure of the device on the electrical field strength and stress duration. Attempting to prolong the time to failure by lowering the electric field would result in exponentially longer erase times since the Fowler-Nordheim tunneling current density has an inverse exponential dependency as well and would decrease with lower electric fields. Furthermore, by using NGSE the hot hole tunneling current is localized beneath the source and floating gate overlapping area and the likelihood of the dielectric traps to line up and form a breakthrough path is high. 
         [0009]    Referring to  FIG. 2 , another prior art erase technique is presented using a p-type well structure  24 . The p-well  24  is contacted using a p+ region  29  and formed in a deep n-type well  25 . The n-well  25 , which may be contacted using an n+ region  36 , is formed within a p-type substrate  23 . This erase technique uses a large negative bias potential Vg applied to the control gate  21  of about −11V while simultaneously applying a positive bias potential Vb of about 5V to the p-well  24  via the well terminal  29 . The charge storing layer  28 , also referred to as floating gate, lies beneath the control gate  21  with a dielectric  34  forming an intermediate insulating layer. Usually the p-type substrate  23  is grounded and the n-well  25  is kept floating during the erase operation. The source region  30  and the drain region  31  are either kept floating [3] or at the same potential as the p-well  24  [6], causing the electrons stored in the floating gate  28  to tunnel vertically  37  through the tunneling oxide  33  and into the channel region  22 .This prior art erase technique is commonly referred to as Negative Gate Channel Erase (NGCE). 
         [0010]    The NGCE technique suffers from a different reliability problem. Since the charge is erased into the channel region  22 , by using high electric fields a high energy, a tunneling electron could impact ionize the semiconductor interface to generate an electron hole pair. This energetic hole, as in the previously presented NGSE method, would be attracted by the same high electric field and tunnel back through the dielectric layer  34  into the floating gate  28 . This “hot hole” tunneling current would have the same affect on the dielectric quality and cause degradation over time. However, since in this case, the surface states and inter-dielectric traps are distributed along the entire channel length, most of the performance penalty would be manifested in device read current degradation and reduced programming performance. The impact on programming efficiencies results from the fact that these traps interfere with the hot carrier injection process. 
         [0011]    Another prior art variation for NGCE technique [6] utilized the same biasing potential application for the p-type well  24  and the source region  30 . This technique attempts to minimize the reliability problems induced by hot hole injection by applying the same potential bias to the source and the well, thus minimizing the band to band tunneling the would otherwise occur at the source dielectric interface  26 . This prior art technique, however, does not eliminate the need for using high electric field across the dielectric during erase and the resulting TDDB and performance degradation issues. 
         [0012]      FIG. 3  shows the biasing voltage waveform time dependence used to operate the flash device during erase in the prior art. All prior art techniques use an operation methodology that dictates a simultaneous application of the bias pulses for the control gate and the well either with or without the source and drain regions (the latter are either operated in the same manner as the well or kept floating). Since tunneling is the main mechanism used in erasing the device it is necessary to generate a strong electrical field over the dielectric during erase. As a result, the potential difference between the control gate and the well should be the highest obtainable. The well bias waveform has a finite rise and fall times and a positive polarity while the control gate bias waveform simultaneously assumes a negative polarity. The effective erase time for tunneling to occur is the actual overlap time of these two waveforms when the electric field is maximized. All prior art techniques attempt to maximize the overlap time between these waveforms in order to get the maximal electrical field during the erase sequence making them highly vulnerable to the above mentioned reliability issues. Another drawback of this prior art operation methodology is that the biasing scheme would also yield an electric field across the control gate to floating gate dielectric that would induce charge tunneling from the former to the latter. This tunneling current would interfere with the erase process by adding charge to the floating gate. 
         [0013]    In the prior art there are several programming techniques for a flash memory based on the physical phenomena of charge tunneling through a potential barrier. Implementation of these Fowler-Nordheim tunneling based programming techniques requires the usage of large electrical field across the dielectric as for the erase case. Tunneling based programming is achieved simply by reversing the polarity of the applied bias to the control gate and source and well terminals, thus reversing the direction of the tunneling current. In particular by application of a large positive voltage to the control gate and simultaneous application of a moderate negative voltage to the well region. A variation to this method uses both source and drain regions along with the well region in the programming process at the same time with the exact same bias operation methodology. The merits of having a large electric field across the dielectric layer are inherent to the tunneling based programming scheme as for the tunneling based erase scheme. 
         [0014]    Referring to  FIG. 2 , a prior art program technique is presented using a p-type well structure  24 . The p-well  24  is contacted using a p+ region  29  and formed in a deep n-type well  25 . The n-well  25 , which may be contacted using an n+ region  36 , is formed within a p-type substrate  23 . This program technique uses a large positive bias potential Vg applied to the control gate  21  of about 10V [7] while simultaneously applying a positive bias potential Vb of about 10V to the p-well  24  via the well terminal  29 . The source region  30  is grounded while the drain region  31  is kept floating or at the same potential as the source, causing the electrons from the source and drain to tunnel vertically  38  through the tunneling oxide  33  and into the floating gate  28 . 
         [0015]    When inter dielectric charge traps are present under the floating gate (as shown in  FIG. 4  as  41   b ), the tunneling current from the floating gate to the well has two major components: the direct tunneling component (marked  37   b  as in  FIG. 4 ) and the indirect tunneling component. The direct component is that of charge having sufficient energy to overcome the potential barrier and tunnel to the well, also commonly referred to as Fowler-Nordheim tunneling or “Field Emission”. The indirect component or trap assisted tunneling comprises of two stages. The first stage being the tunneling of charge from the floating gate to the trap (marked  38   b  in  FIG. 4 ) and the second being tunneling of the same charge from the trap to the well (marked  39   b  in  FIG. 4 ). 
         [0016]    Application of high electric fields across the dielectric layer over time results in bond breaking in the dielectric molecular structures which serves as a charge trap. This trap, depending on its nature, can either capture a negative charge (i.e. electron) or a positive charge (i.e. hole). Given enough time these traps would align to form a conducting path from the floating gate to the source or substrate region. Once this occurs the device is considered to be broken down. The bond breaking process has a complex dependency on the applied electrical field stress time. In case the electric field is applied for a short period of time, some of the resulting traps are reversible in nature in a sense that the trapped charge will be released and the molecular bond will recover and remain intact after the removal of the stress. If the stress is applied for longer time periods, the broken bond is unrecoverable and a permanent trap is formed. Well known phenomena such as “Stress Induced Leakage Current” (SILC) [VI] and “Negative Bias Temperature Instability” (NBTI) [VII] may be explained by the reversible nature of these traps. 
         [0017]    Dielectric film properties are modified as a result of trap generation as well, which in turn affects device performance. In the case of a silicon dioxide dielectric, “Anode Hydrogen Release” (AHI) [VIII] is a known phenomenon that results from electrical stress induced bond breaking and release of Hydrogen atoms. The Hydrogen is incorporated into the dielectric thin film during the manufacturing process in order to neutralize surface traps commonly referred to as “surface states”. Once the Hydrogen atoms are released from the surface, they migrate by means of diffusion through the dielectric layer and render its electrical properties as well as affecting the device&#39;s switching properties. 
         [0018]    Dielectric trap generation of silicon (Si) based devices having silicon dioxide (SiO2) as a dielectric film has been widely investigated over the past decade. Trap generation as a result of the applied electric stress is commonly classified into two major categories [VIIII]. The first kind, referred to as surface traps ‘Nit’, caused by silicon-hydrogen bond breaking at the Si—SiO2 interface, resulting in hydrogen diffusion into the bulk oxide and having a partially recoverable nature. The second kind, referred to as oxide traps ‘Not’ (either at the bulk oxide or the interface), is the result of silicon:oxygen bond breaking and having a non recoverable nature. The non recoverable traps are caused by hot holes, created by Fowler-Nordheim stress during erase operation or impact ionization in the bulk Si during channel hot electron program operation, and injected into the dielectric layer. Minimizing the mechanisms of hot hole generation during device operation is a key factor in maximizing device reliability and lifetime. 
         [0019]    High electric fields present between the control gate and the well are known to result in an unwanted leakage current between the floating gate and the control gate. This tunneling based leakage has an exponential dependence on the electric field and interferes both with program and erase of the device. Referring to  FIG. 2 , the charge tunneling between the control gate  21  and the floating gate  28  will always be in an opposite direction to the program or erase tunneling current and reduce the operation efficiency while increasing the overall power dissipation. 
         [0020]    The background and associate prior art erase procedures are described in the following publications: [I] Witters, et al., “Degradation of Tunnel Oxide Floating Gate EPROM Devices and Correlation With High-Field-Current-Induced Degradation of Thin Gate Oxides”, IEEE Transactions On Electron Devices, Vol. 36, No. 9, September 1989, p. 1663. [II] Chun, et al., “Lateral Distribution of Erase Induced Hole Trapping and Interface Traps in Flash EPROM NMOSFET Devices”, IEEE Semiconductor Interface Specialists Conference, 1996. [III] A. Yokozawa, et al., “Investigation for Degradation of the Retention Characteristics due to Oxide Traps Induced by Hole Injection”, NVMSW proc. 1998 pp. 83-85. [IV] S. G. Dmitriev, Y. V. Markin, “Macroscopic Ion Traps at the Silicon Oxide Interface”, Semiconductor, Vol. 32, pp. 625-628, June 1988. [V] Vertoprakhov et al., “The effect of mobile charge in silicon dioxide on the surface states density of mos structure”, Russian Physical Journal, Vol. 19, pp. 378-379. [VI] Hu et al., “Stress induced current in thin silicon dioxide films”, IEDM &#39;92. [VII] Kimizuka et al.“NBTI enhancement by nitrogen incorporation into ultrathin gate oxide”, symposium on VLSI 2000. [VIII] DiMaria et al., “Hydrogen Electrochemistry and Stress-Induced Leakage Current in Silica,” PRL. 83, (1999). [VIIII] Mahapatra et al., “On the Generation and Recovery of Interface Traps in MOSFETs Subjected to NBTI, FN and HCI stress”, IEEE Trans. On Elect. Devices, July 2006. 
       BRIEF SUMMARY OF THE INVENTION 
       [0021]    As a means to avoid the problems described in prior art techniques, a novel operation method for flash devices is presented. One object of an embodiment of the invention is to provide a method of programming and erasing a flash electrically erasable, programmable, read-only memory device, which allows both the usage of lower levels of biasing voltages and of shorter biasing pulse durations thus inherently having a lower vulnerability to the electrical field stress induced reliability issues and higher operation efficiency. 
         [0022]    A flash memory device having a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well terminal formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control terminal electrically isolated from the charge storing layer by a inter layer dielectric and constructed in a manner to have an electric coupling to the charge storing layer. 
         [0023]    The erase method in the present invention comprising of the following steps: 
         [0024]    (1) Application of a first voltage bias of one polarity, being of opposite polarity to the stored charge, to the well terminal and the second semiconductor region with the source and drain regions either kept floating or at the same voltage bias. 
         [0025]    (2) After a time interval, resetting the first bias to zero and application of a second voltage bias, having an opposite polarity to the first voltage bias, to the control gate. 
         [0000]    Thereby removing charge stored in the floating gate by means of tunneling through the dielectric layer and into the well and source and drain regions. 
         [0026]    The program method in the present invention comprising of the following steps: 
         [0027]    (1) Application of a first voltage bias of one polarity, being of opposite polarity to the stored charge, to the control gate. 
         [0028]    (2) After a time interval, resetting the first bias to zero and application of a second voltage bias, having an opposite polarity to the first voltage bias, to the well terminal and the second semiconductor region with the source and drain regions either kept floating or at the same voltage bias. 
         [0000]    Thereby storing charge from the well and source and drain regions into the floating gate by means of tunneling through the dielectric layer. 
         [0029]    The program and erase methods of the present invention introduces an innovative approach for the device operation by utilizing both existing and stress induced newly created traps. These traps assist in the operation of the device by serving as an intermediate point for the tunneling process (stepping stones). By applying the first positive voltage to the well during the first stage, these traps would be forced to deplete from any stored charge within (erase) or filled with charge (program), while during the second stage, where the first bias is reset and the second voltage inversely biased, charge is removed (erase) or added (program) from the floating gate by direct and indirect, trap assisted, tunneling currents. This indirect tunneling component enables the usage of shorter bias pulses since it increases the indirect tunneling current component. The formation of newly created traps in the dielectric during this operation is mostly of reversible nature due to the shorter period and lower magnitude of the electric field compared with the prior art. After the stress is removed the dielectric film will not suffer as much damage compared with prior art operation techniques. This methodology results in superior device reliability and lifetime especially in the sub micron regime. 
         [0030]    Flash device operation is performed to a specific threshold voltage which only depends on the amount of charge added or removed from the floating gate. Thus, the present invention would yield higher tunneling currents without having the inevitable merits of strong electric fields exposure that usually accompany prior art methods. The present invention utilizes an electric field that is about half in magnitude then the one used in all prior art techniques and that has a shorter duration which gives higher immunity to the prior art reliability issues, which in turn have an exponential dependency on both the electric field&#39;s magnitude and duration. 
         [0031]    In addition, the present invention has an inherent reduced likelihood for hot holes generation during device operation, which when injected into the dielectric layer lead to the creation of permanent traps and ultimately device breakdown. 
         [0032]    Furthermore, reduction of the applied electric field between the control gate and the well would reduce the magnitude of the unwanted floating gate to control gate tunneling current for both program and erase and result in increased operation efficiency and lower power dissipation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0033]      FIG. 1  is a cross sectional view of a flash EEPROM device in the prior art operated with the NGSE method. 
           [0034]      FIG. 2  is a cross sectional view of a flash EEPROM device in the prior art operated with the NGCE method. 
           [0035]      FIG. 3  depicts bias voltage waveform timing alignment used in all erase methods of prior art. 
           [0036]      FIG. 4  is the same cross sectional view of  FIG. 2  using corresponding reference numerals and showing the effect of erasing using the method presented in the present invention. 
           [0037]      FIG. 5  depicts bias voltage waveform timing alignment used in all program methods of prior art. 
           [0038]      FIG. 6  is the same cross sectional view of  FIG. 2  using corresponding reference numerals and showing the effect of programming using the method presented in the present invention. 
           [0039]      FIG. 7  depicts bias voltage waveform timing alignment used in the erase process in one configuration of the present invention. 
           [0040]      FIG. 8  depicts bias voltage waveform timing alignment used in the erase process in a second configuration of the present invention. 
           [0041]      FIG. 9  depicts bias voltage waveform timing alignment used in the erase process in a third configuration of the present invention. 
           [0042]      FIG. 10  depicts bias voltage waveform timing alignment used in the program process in one configuration of the present invention. 
           [0043]      FIG. 11  depicts bias voltage waveform timing alignment used in the program process in a second configuration of the present invention. 
           [0044]      FIG. 12  depicts bias voltage waveform timing alignment used in the program process in a third configuration of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0045]    The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. 
         [0046]      FIG. 4  shows an embodiment of the present invention using an n-type flash EEPROM. The EEPROM device  20   b  is formed in a p-type triple well  24   b,  formed within an n-type deep well  25   b,  formed in a p-type substrate  23   b.  The device has a control gate  21   b  that is formed above a floating gate  28   b  with an inter layer electrically isolating dielectric  34   b.  The floating gate  28   b  is isolated from the channel area  22   b  by a dielectric layer  35   b  as well. The floating gate  28   b  is used as a charge storing layer, and may be made of a localized charge trapping material such as nitride, a non localized charge storing material such as poly silicon, an electric charge conducting material, or an isolating material. The drain  31   b  is formed from an n-type semiconductor as is the source  30   b.  The triple well is contacted using highly doped p-type region  29   b  and the deep n-well is contacted using highly doped n-type region  36   b.    
       (a) Erase Operation 
       [0047]    In an embodiment of the present invention, erasing the flash device is accomplished by biasing the well and gate terminals as described in  FIG. 7  or  FIG. 8  in two stages. Referring to  FIG. 7 , the biasing voltage waveform time dependence used to operate the flash device during erase in a first manner of the current invention is depicted. The well biasing voltage is of a positive polarity and the gate biasing is of negative polarity. The well bias is triggered first and after a certain settling time period has elapsed the gate negative bias is triggered. The overlap time between the two pulses, which may or may not equal zero, is depicted as well. Referring to  FIG. 8 , the biasing voltage waveform time dependence used to operate the flash device during erase in a second manner of the current invention is depicted. The well biasing voltage is of a positive polarity and the gate biasing is of negative polarity. The well bias is triggered first and after a certain settling time period has elapsed it is reset back to zero. After another delay time period has elapsed, which may or may not equal zero, the gate negative bias is triggered. The delay time between the two pulses is depicted as well. Referring to  FIG. 9 , the biasing voltage waveform time dependence used to operate the flash device during erase in a third manner of the current invention is depicted. The control gate biasing is operated entirely during the well voltage biasing ramp down. 
         [0048]    In conclusion, the erase technique according to an embodiment of the present invention is accomplished by biasing the well and gate terminals in two stages. In the first stage a positive voltage is used to bias the triple well and in the second stage a negative voltage is used to bias the control gate. The two bias pulses may have an overlap time as indicated in  FIG. 7  or a delay time as indicated in  FIG. 8 . Obviously, in an embodiment, a positive voltage may be used to simultaneously bias the triple well and source region in the first stage, and in another embodiment, a positive voltage may be used to simultaneously bias the triple well and the source and drain regions in the first stage. 
         [0049]    Referring to  FIG. 4 , during the first erase stage, a positive voltage bias is applied to the triple p-type well  22   b  via the well terminal  29   b.  The deep n-type well  25   b  is kept floating while the p-type substrate  23   b  is generally grounded. The source  30   b  and drain  31   b  regions may be kept floating or biased using the same waveform as the triple well  22   b.  Once a certain time period has elapsed, the second stage is initiated during which a negative bias is applied to the control gate  21   b  and the well bias is reset back to zero. The erase sequence is finished when the control gate bias is reset back to zero. 
         [0050]    The well positive bias during the first stage would generate an electric field originating from the well surface to the floating gate  28   b  across the dielectric layer  35   b  and forcing the “surface state traps” (marked  32  in  FIG. 2 ) and “inter dielectric traps” (marked  41   b  in  FIG. 4 ) to release any stored charge within into the well. The direct consequence is that the inter dielectric traps are setup to a tunneling assisting mode in which their probability to attract free charge from the floating gate increases. The time period needed for the traps to enter this state depends on their charge retention lifetime. Once the second stage is initiated, the control gate  21   b  is biased with a negative voltage which would generate an electric field across the floating gate  28   b  to inter layer electrically isolating dielectric  34   b  in an opposite direction from the one generated during the first stage. This field would trigger both a direct and indirect tunneling currents from the floating gate  28   b  to the well thus erasing the device. A direct result of this operation methodology is that the electric fields formed over the dielectric interface is about half in magnitude of the ones used in all prior art techniques and shorter in duration as well. Both features mean higher immunity to the described reliability issues of the prior art, the latter having an exponential dependence on both the electric field&#39;s magnitude and duration. Using weaker electrical fields would considerably lower the tunneling from control gate  21   b  to floating gate  28   b,  a known factor to interfere with the erase process, and result in increased programming efficiency and lower power dissipation. 
         [0051]    Erasing the device to a predetermined threshold level depends only on the quantity of electrons removed from the floating gate  28   b.  The present invention describes not only a more efficient method for removing this charge, thus exposing the device to shorter time periods of electrical field stress, but also allows the usage of weaker fields during erase since biasing is done in two consecutive stages. All prior art erasing techniques dictate the usage of simultaneous biasing schemes. These methodologies require stronger fields and longer erase times making them highly vulnerable to electrical stress induced reliability issues, in turn having an exponential dependence on both field strength and duration. 
       (b) Program Operation 
       [0052]    In an embodiment of the present invention, programming the flash device is accomplished by biasing the well and gate terminals as described in  FIG. 10  or  FIG. 11  in two stages. Referring to  FIG. 10 , the biasing voltage waveform time dependence used to operate the flash device during program in a first manner of the current invention is depicted. The control gate biasing voltage is of a positive polarity and the well biasing is of negative polarity. The control gate bias is triggered first and after a certain settling time period has elapsed the well negative bias is triggered. The overlap time between the two pulses, which may or may not equal zero, is depicted as well. Referring to  FIG. 11 , the biasing voltage waveform time dependence used to operate the flash device during program in a second manner of the current invention is depicted. The control gate biasing voltage is of a positive polarity and the well biasing is of negative polarity. The control gate bias is triggered first and after a certain settling time period has elapsed it is reset back to zero. After another delay time period has elapsed, which may or may not equal zero, the well negative bias is triggered. The delay time between the two pulses is depicted as well. Referring to  FIG. 12 , the biasing voltage waveform time dependence used to operate the flash device during program in a third manner of the current invention is depicted. The well biasing is operated entirely during the control gate voltage biasing ramp down. 
         [0053]    In conclusion, the program technique according to an embodiment of the present invention is accomplished by biasing the well and gate terminals in two stages. In the first stage a positive voltage is used to bias the control gate and in the second stage a negative voltage is used to bias the triple well. The two bias pulses may have an overlap time as indicated in  FIG. 10  or a delay time as indicated in  FIG. 11 . Obviously, in an embodiment, a negative voltage may be used to simultaneously bias the triple well and source region in the second stage, and in another embodiment, a negative voltage may be used to simultaneously bias the triple well and the source and drain regions in the second stage. 
         [0054]    Referring to  FIG. 6 , during the first program stage a positive bias is applied to the control gate  21   c.  Once a certain time period has elapsed, the second stage is initiated during which a negative voltage bias is applied to the triple p-type well  22   c  via the well terminal  29   c.  The deep n-type well  25   c  is kept floating while the p-type substrate  23   c  is generally grounded. The source  30   c  and drain  31   c  regions may be kept floating or biased using the same waveform as the triple well  22   c  and the control gate bias is reset back to zero. The program sequence is finished when the triple well bias is reset back to zero. 
         [0055]    The control gate positive  21   c  bias during the first stage would generate an electric field originating from the floating gate  28   c  to the well surface across the dielectric layer  35   c  and forcing the “surface state traps” (marked  32  in  FIG. 2 ) and “inter dielectric traps” (marked  41   c  in  FIG. 6 ) to release any stored charge within into the floating gate. The direct consequence is that the inter dielectric traps are setup to a tunneling assisting mode in which their probability to attract free charge from the floating gate increases. The time period needed for the traps to enter this state depends on their charge retention lifetime. Once the second stage is initiated, the triple p-type well  22   c  is biased with a negative voltage which would generate an electric field across the floating gate  28   c  to inter layer electrically isolating dielectric  34   c  in an opposite direction from the one generated during the first stage. This field would trigger both a direct and indirect tunneling currents from the well to the floating gate  28   c  thus programming the device. A direct result of this operation methodology is that the electric fields formed over the dielectric interface is about half in magnitude of the ones used in all prior art techniques and shorter in duration as well. Both features mean higher immunity to the described reliability issues of the prior art, the latter having an exponential dependence on both the electric field&#39;s magnitude and duration. Using weaker electrical fields would considerably lower the tunneling from control gate  21   c  to floating gate  28   c,  a known factor to interfere with the program process, and result in increased programming efficiency and lower power dissipation. 
         [0056]    Programming the device to a predetermined threshold level depends only on the quantity of electrons added to the floating gate  28   c.  The present invention describes not only a more efficient method for storing this charge, thus exposing the device to shorter time periods of electrical field stress, but also allows the usage of weaker fields during program since biasing is done in two consecutive stages. All prior art programming techniques dictate the usage of simultaneous biasing schemes. These methodologies require stronger fields and longer program times making them highly vulnerable to electrical stress induced reliability issues, in turn having an exponential dependence on both field strength and duration. 
         [0000]    (c) 
         [0057]    It is clear to those skilled in the art that the erase and program operations could be accomplished using the methods described above also by interchanging the order and waveforms of the applied bias voltages while keeping their polarity. The erase operation could be done by first biasing the control gate in the first stage, having the waveform and timing previously affiliated with the well terminal, before biasing the well terminal in the second stage, having the waveform and timing previously affiliated with the control gate. In the same manner, the program operation could be done by first biasing the well terminal in the first stage, having the waveform and timing previously affiliated with the control gate, before biasing the control gate in the second stage, having the waveform and timing previously affiliated with the well terminal. 
         [0058]    The above description is shown for an embodiment of the present invention using an n-type flash EEPROM for illustrative purposes. It is clear that the above operational description is valid for any kind of EEPROM device by using the same waveforms or reversing their polarity depending on the polarity of charge being manipulated and the type of semiconductor being used to implement the device. Based on the above, those skilled in the art would realize that the embodiments of the present invention described herein are illustrative only and are not in any way limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of this description. 
         [0059]    The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention”, “the present invention” or the like is not necessary limited the claim scope to a specific embodiment, and the reference to particularly preferred exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.