Abstract:
A variable range marker device for use with a PPI radar with digitized video displayed in non-real time. The position of the range marker is initially operator determined by rotation of a knob mechanically linked to an optically encoded disc. Optical sensors produce a digital output indicative of the disc rotation angle and range mark position as a distance from the center of the radar display screen. A counter is preset with the digital ouput at the start of each sweep and decremented once each range cell until a count of zero is reached at which time an unblanking pulse is produced. A numeric display of range is produced by dividing the number of range cells to the range mark by the range setting, scaling according to chosen units of measure, and displaying the result with a LED display, the computations being performed by a processor controlled by a permanently programmed memory. The range mark stays on target as the range scale is changed. The amount of movement of the range mark for a given amount of control rotation is independent of range scale.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to a radar system having an operator-positionable variable range mark. Such a range mark is used by an operator to determine the distance from the radar zero position to the selected target upon which the range mark is positioned. More particularly, the invention relates to such a radar system which additionally employs digital processing of received radar signals. 
     2. Description of the Prior Art 
     Previous radar systems which employed a variable range ring operated primarily using analog signal processing in the PPI mode. Received radar signals were displayed at substantially the same rate at which they were received. Such systems worked reasonably well at longer ranges in which the writing rate upon the cathode ray tube screen of the display device of the radar system was sufficiently slow to produce an acceptably high brightness level. Also, for the time periods ordinarily involved in the longer ranges, the range to a target could be determined with a generally sufficient amount of precision. However, for short ranges, the writing rate of the cathode ray tube beam became unacceptably high so that the brightness level was reduced down to unacceptably low levels. Moreover, it became more and more difficult to accurately measure the distance to a target as the range decreased because of the short time periods involved. 
     In systems employing analog signal processing, the range-mark signal was generated as the output of a timer. The position of the range mark upon the screen of the CRT was determined by the timing constant of an R-C circuit coupled to the timer used to set the time between activation of the timer and pulse output. Most frequently, a potentiometer, used for the resistance, was the operator control used to move the range mark. With this system, a given angle of rotation of the potentiometer moved the range mark on the screen by varying amounts depending on the range scale setting. On the shorter ranges, the range mark moved a relatively large amount for a small potentiometer rotation, while the same rotation would be hardly perceptible on the longest ranges. 
     In still other systems of the prior art, a storage tube was employed to yield a system having a substantially constant brightness independent of the range scale selected. For these systems and other similar systems, the range mark signal was added to the video signal at the output of the storage tube. When the range scale was changed, the range mark would stay at a constant position from the center of the screen and not move on the screen so as to stay on a target selected on another range. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a radar system in which the amount of movement of a range mark position in regards to the amount of movement of an appropriate operator control is constant over all radar range scales. 
     Also, it is an object of the invention to provide a radar system in which a range mark will stay on a preselected target as the range scale is changed. 
     It is further an object of the present invention to provide a PPI radar system having a variable range mark including a digital read out of the range mark position, the resolution of the range mark position being highly accurate for both long and short ranges. 
     Also, it is an object of the present invention to provide such a radar system particularly adapted for use with digital processing of the received radar signals. 
     Moreover, it is still a further object of the invention to provide such a radar system adapted for use with a digital radar signal processor in which the received signals are stored at a first rate then subsequently read out at a second slower rate which may be constant over plural range settings. 
     These, as well as other objects of the invention, may be met by providing the combination of a PPI radar system including display means and means for digitizing radar return signals and means for producing a range mark upon the display means, the position of which is operator variable. Means for digitally displaying the position of the range mark in predetermined units is also provided. The radar system preferably has a plurality of operator selectable range scales wherein the position of the range mark remains at the range at which it was set among at least some of the operator selectable range scales. An operator actuable control including a resolver such as a magnetic or optical resolver is provided for determining the position of the range mark. Preferably, the control is continuously rotatable. 
     The range mark signal producing means preferably includes means for producing a digital count in response to a count of pulses produced by the operator actuable range mark position control. The digital count producing means is preset at the start of each radar pulse period with a digital number corresponding to the position of the variable position range mark as determined by positioning the number stored in a register representing an accumulated count of pulses produced by the resolver. The position of the number is determined in accordance with a selected radar range scale setting such that the least significant bit of the count corresponds to one range cell or sample period at the selected radar range scale setting. The count proceeds during the display period at the rate of one count per range cell. 
     The invention may also be practiced by apparatus for producing a variable range mark signal and for providing a digital indication of the range mark position for a PPI radar indicator comprising the combination of means for storing a digital number representing the position of the range mark upon the display face of the indicator, means for producing a digital count, means for presetting the digital count producing means in response to the digital number, means for producing the range mark signal in response to one or more count outputs from the count producing means, and a programmed arithmetic processor for producing the digital indication of the range mark position, the processor operating upon the digital number and a range scale setting or indication. The digital number stored in the storing means is positioned such that the least significant bit coupled to the counter corresponds to one range cell at the selected radar range scale setting. The range mark will stay on a selected target as the range scale is changed. That is, the distance represented by the range ring from radar zero or center on the display screen is independent of the radar range setting. Moreover, a given amount of rotational or positional change of a control for varying the position of the range mark produces a constant amount of movement on the display screen independent of the range scale selected. The processor comprises, in preferred embodiments, a permanently programmed memory for storing processing instructions, program counter means for addressing the memory, means for decoding the instructions on the outputs of the memory, means for performing additions and/or subtractions in response to the decoding means, and means for storing outputs from the adder means. The memory comprises either a permanently programmed memory such as a PROM, ROM, or other type semiconductor read-only memory. The combination may further include first counting means coupled to the decoding means for determining the position of a decimal point of the number stored in the storing means and second counting means coupled to the decoding means for determining the number of leading zeros in numbers stored in the storing means. Means may also be provided for producing a visual indication of the range mark position. The visual indicating means preferably comprises a light-emitting diode display. Again, means may be provided for producing the digital number representing the position of the range mark. The digital number producing means may include means for producing at least two digital pulsed signals in response to operator rotation of a control shaft, the relative phase of the signals being dependent upon the direction of rotation of the shaft. The digital pulsed signal producing means may include a cylindrically shaped housing having a plurality of apertures therein, light producing means positioned on one side of the housing, and light detecting means positioned on the other side of the housing. Means is also provided for adding to or subtracting from the number representing the position of the range mark in accordance with the digital pulsed signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a basic block diagram of a radar system of the invention; 
     FIG. 2 is a detailed block diagram of a radar system of the invention; 
     FIG. 3 is a block diagram of the variable range mark circuit of the radar system shown in FIG. 2; 
     FIGS. 4A-4C are a schematic diagram of a preferred implementation of the variable range mark circuit of FIG. 3; 
     FIG. 5 is a partially cut-away view of a resolver as used in the invention; 
     FIG. 6 is a cross-sectional view of the device of FIG. 5 additionally showing the operating circuitry; and 
     FIG. 7 is a table showing the instructions set and corresponding codes used with an embodiment of the control processor of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring first to FIG. 1, there is shown a basic block diagram of a PPI radar system 100 constructed in accordance with the teachings of the present invention. The radar system is constructed from three basic units: indicator unit 140, MTR (modulator-transmitter-receiver) unit 102, and antenna unit 101. Indicator unit 140, which provides the display of radar information and contains the operating controls of the system, is ordinarily mounted upon the bridge of the ship for easy access and convenience for use in navigation. Antenna unit 101 is in practice mounted as high as possible with an unobstructed path for the antenna beam to maximize the range of the unit. MTR unit 102 is located in weather-tight position as close as is practical to antenna unit 101 to minimize losses in the high-power transmit pulses coupled to antenna unit 101 and the low-level receive signals coupled from antenna unit 101 to MTR unit 102. 
     Both indicator unit 140 and MTR unit 102 contain separate power modules 174 and 122 respectively. Both take the ship&#39;s power which may be 110 volts AC 60 cycles or any other normally provided primary input power source and convert it to DC voltages suitable for operating the various electronic circuits and electromechanical devices located within the two units. Additionally, MTR power module 122 supplies operating power to antenna 101 to the motor contained therein for rotation of the antenna. By providing separate power modules in each of the two remotely located major operating units, losses which occurred in previous units in the cabling between units is avoided. Moreover, with the system of the present invention, ON/OFF control of MTR power module 122 is accomplished from indicator unit 140 using only low signal level control voltages. Full control is therefore maintained at the indicator unit without large amounts of power dissipation and loss in long runs of cabling between units. 
     Each radar pulse cycle is initiated at indicator unit 140 by the production of an MTR TRIGGER pulse which is coupled to MTR unit 102. Upon receipt of this pulse, MTR unit 102 produces a high-power transmit pulse. The transmit pulse is coupled to antenna unit 101 which radiates the signal outward in a narrow beam. Echo return signals from targets are received at antenna unit 101 and relayed to the receiver portion of MTR unit 102. The receiver portion of MTR unit 102 amplifies and detects the received echo signals and produces a video signal to indicator unit 140. The commencement of the video signal is marked by an acknowledge pulse generated within MTR unit 102. Indicator unit 140 produces a visual display of the signals reflected back from targets in the path of the radar beam in accordance with the video signal. The azimuthal position of the radar antenna is relayed from antenna unit 101 directly to indicator unit 140 to indicate the angle upon the display screen the returned radar signals are to be displayed. 
     Referring next to FIG. 2, there is shown a detailed block diagram of radar system 100 as shown in FIG. 1. Antenna unit 101 contains a rotatable antenna 104 capable of radiating and receiving signals within the frequency range of the radar pulses. Antenna 104 is rotatably connected to a set of gears 108 through a section of waveguide 105. Motor 106 is mechanically linked to antenna 104 through gears 108 and causes antenna 104 to rotate at a substantially constant and predetermined rate. Antenna resolver 112 is also linked through its input rotary shaft to gears 108 and antenna 104. Its input shaft is rotated preferably at the same rate as antenna 104. 
     Signals going to and coming from antenna 104 are coupled through rotary joint 110 within antenna unit 101 through waveguide section 115 to duplexer 114. Receive signals are passed through duplexer 114 to passive limiter 116 to the input of receiver 120. Duplexer 114 isolates the transmit pulses produced by transmitter-modulator 118 from receiver 120 and couples the receive signals directly from waveguide 115 to the input of receiver 120 without substantial loss. Passive limiter 116 provides an absolute amplitude limit upon input signals to protect the input circuitry of receiver 120 from being overloaded from signals picked up from nearby radar transmitters. 
     Transmitter-modulator 118 produces radar pulses in response to an input trigger signal from timing generator 144 within indicator unit 140. The PRF (pulse repetition frequency) of the transmitted radar pulses is entirely determined by the repetition rate of the MTR trigger signal produced by timing generator 144. In previous radar systems in which the PRF was a function of the radar range setting, a plurality of signals indicative of the various possible range settings was coupled to the transmitter-modulator. A decoding circuit then determined the appropriate PRF for the range chosen. With the present system however, only a single trigger signal need be provided. 
     The width of pulses transmitted may also be a function of the radar range scale setting. It may, for example, be desirable to use a narrower pulse on shorter range scales in order to obtain a greater definition than would be possible using the longer pulses necessary to achieve an acceptable signal-to-noise ratio on the longer ranges. However, it has been found not necessary to provide a different pulse width for every possible range setting value. For example, in the preferred system embodiment of the invention there are 10 different range settings between 0.25 and 64 nautical miles. It has been found that only three different pulse widths of approximately 60, 500, and 1000 nanoseconds are practically required. Only a two bit digital signal then need be coupled between timing generator 144 and transmitter-modulator 118 to select among the three pulse widths. As there are many fewer pulse widths required than are range scales values selectable, many fewer lines or signals need be passed between timing generator 144 and transmitter-modulator 118 than were needed in previous systems. 
     In previous systems a trigger pulse was generated within the MTR unit which was coupled to both the modulator and display circuitry. Because of certain characteristics of the most commonly employed modulators, the delay time between application of a trigger pulse and generation of the actual transmitted pulse may vary. This is especially true between ranges. Because of this unpredictable delay difference targets in previously known radar systems would sometimes be displayed having an inaccurate jagged edge caused by the sweep starting either too early or too late. With the systems constructed in accordance with the present invention, this problem has been eliminated. 
     Transmitter-modulator 118 produces an MTR ACKNOWLEDGE pulse at the commencement of each transmit pulse. This MTR ACKNOWLEDGE pulse coupled to timing generator 144 marks the beginning of the start of the radar sweep for each of the video signal processing circuits within indicator unit 140. Because the MTR ACKNOWLEDGE pulse is precisely aligned with the commencement of each radar pulse registration between adjacent sweep lines upon the displace screen is maintained to a high precision. Thus, the actual shapes of targets are accurately presented with no jagged edges caused by imprecise synchronization of the start of the display sweep with the actual transmitted pulse. 
     Transmitter-modulator 118 also produces a sensitivity time control (STC) signal to control the gain within receiver 120. As is well-known in the art, the STC signal is used to vary the gain of receiver 120 during each radar pulse. For signals received from targets nearby the gain is reduced. In this manner the amplifying circuitry within receiver 120 is prevented from being overloaded by the strong signals from nearby targets and locally caused interference and a display having a substantially constant brilliance is produced. 
     The analog video signal produced at the output of receiver 120 is converted to a serial stream of digital data by analog/digital converter 148 within indicator unit 140. The rate at which samples are taken of the analog video signal for digitization and the length of the time period from the start of the radar pulse during which the analog video signal is digitized is dependent upon the radar range scale setting. For the shorter ranges, a higher sampling rate and shorter time period are used. 
     The digitized video signal is read into digital video data storage memory 150 under control of clock pulses from timing generator 144. Digital video data storage memory 150 stores the digitized video signal from an entire radar pulse time period. The range to which the signal is stored is of course dependent of the range scale setting. The digital video signal is read out of digital video data storage memory 150 for dislay upon cathode-ray tube 172 in a second time period also determined by the rate of clock pulses coming from timing generator 144. The second time period may be greater than or less than or the same as the first time period during which the video signal was read into digital video data storage memory 150. Read out occurs preferably immediately following the first time period and before commencement of the next succeeding radar time period. In preferred embodiments, the second time period is substantially constant and independent of the first time period. In this manner, with the constant readout time period the writing or deflection rate of the beam of cathode-ray tube 172 is also constant so that the display produced is of constant intensity independent of the radar range scale setting. For short ranges, the second time period during which the digital signals are read out from digital video data storage memory 150 and displayed is substantially greater than the time period during which the signals were read in. Because of the increase in time period, the writing rate of the beam of the cathode ray tube 172 is decreased over that which would be required should the video signal be displayed at the same rate at which it is received. Hence, the brightness of the display upon short ranges is greatly increased over that of previously known systems. The preferred manner of video signal digitization, storage, and read out is described in U.S. patent application Ser. No. 755,320 filed Dec. 29, 1976 which is a continuation of application Ser. No. 612,882 filed Sept. 12, 1975 now abandoned, which is a continuation of application Ser. No. 413,130 filed Nov. 5, 1973, now abandoned and assigned to the present assignee, the specification of which is herein incorporated by reference. 
     Interference rejection circuit 152 is provided to nullify the interference effects caused by nearby radar transmitters operating within the same frequency band. This type of interference, caused by reception of the transmitted pulses from the nearby radar, appears as plural spiral arms radiating outward from the center of the radar presentation. Interference rejection circuit 152 operates to substantially cancel this type of interference from the radar presentation without substantially effecting the presentation of desired targets. A switch is located upon control panel 146 which permits the operator to turn interference rejection circuit 152 ON and OFF as desired. The details of the construction of interference rejection circuit 152 are contained in U.S. Pat. No. 4,068,233 issued Jan. 10, 1978, the specification of which is herein incorporated by reference. The final video output signal produced at the output of interference rejection circuit 152 is coupled to the video amplifier 166 via video signal summer 160. 
     Also provided is variable range marker circuit 154. Variable range marker circuit 154 produces an output video signal in the form of a short pulse to display a circular range ring mark at a distance from the center of the radar display determined by the setting of range marker adjustment 156. Range marker adjustment 156 may physically be a part of control panel 146. A display device 158 provides a digital read out to the operator of the distance from the radar antenna to the target upon which the variable range mark is positioned. The output variable range mark video signal from variable range mark circuit 154 is coupled to video amplifier 166 through video signal summer 160. 
     Timing generator 144 furnishes clock and other timing signals used for the various circuits within indicator unit 140. An internal oscillator within timing generator 144 produces the clock pulses at predetermined periods. The heading flash from antenna resolver 112 which is produced each time the antenna beam passes the forward direction of the ship is reclocked by the clock pulses produced by the oscillator within timing generator 144 and coupled as a video pulse through video signal summer 160 to video amplifier 166 to produce a mark on the screen to indicate to the operator when the antenna beam so passes the bow of the ship. Timing generator 144 also produces the MTR TRIGGER signal as a pulse at predetermined fixed intervals depending upon the radar range scale setting as relayed from control panel 146. The MTR ACKNOWLEDGE signal from transmitter-modulator 118 is used by timing generator 144 to produce a SWEEP GATE signal which is a logic signal which assumes the high or active state in the time period during which video signals are being received. The SWEEP GATE signal is set in the active state as soon as the MTR ACKNOWLEDGE signal is received and set to the low or inactive state at the end of the time period depending upon the range setting selected. 
     Upon control panel 146 are mounted the various operator actuable controls for adjusting and determining the operation of the various circuits within the radar system. A range control is provided that determines the maximum range at which targets are to be displayed. This distance corresponds to the distance at the edge of the cathode ray tube screen. ON/OFF switches are provided for operating MTR power module 122, motor 106 of antenna 101 via MTR power module 122, interference rejection circuit 152, variable range marker circuit 154, and indicator power module 174. A switch is provided to select between head up (the direction in which the ship is pointing) or north up at the top of the display presentation. 
     For generating displays in which north rather than the current ship&#39;s heading is represented at the top of the display screen, north stabilization circuit 142 modifies the signals received from antenna resolver 112 before coupling them to display position resolver 162. Otherwise, for displays in which the ship&#39;s heading is displayed at the top of the screen, the signals from antenna resolver 112 are coupled directly to display position resolver 162. Display position resolver 162 takes the output signals from either antenna resolver 112 or north stabilization circuit 142 in the form of modulated sine and cosine waveforms and produces therefrom DC voltages for each radar sweep representing X and Y sweep increments. Sweep waveform generator 164 produces X and Y ramp waveforms, the maximum amplitudes of which are determined by the DC voltages from display position resolver 162. Generation of the two ramp waveforms commences at the time marked by the beginning of the DELAYED SWEEP GATE signal from interference rejection circuit 152 which in turn was produced by delaying the SWEEP GATE signal from timing generator 144 by one or more clock periods to permit interference rejection circuit 152 to perform its operation. The X and Y ramp waveforms are each coupled to X and Y deflection amplifiers 168 where they are amplified and coupled to X and Y deflection coils 170 for deflecting the beam of cathode ray tube 172 in the manner well-known in the art. The output of video amplifier 166 is coupled to cathode 176 of cathode ray tube 172 for modulating the beam intensity thereof. 
     The high voltage applied to the accelerating anode of cathode-ray tube 172 and all other operating voltages for the various circuits within indicator unit 140 including the voltages for biasing and operating all the logic circuits contained therein are provided by indicator power module 174. Indicator power module 174 is, as is MTR power module 122, preferably a switching power supply capable of producing at its output a plurality of voltages having the required current furnishing capabilities. The switching frequency of indicator power module 174 and that of MTR power module 122 are selected intermediate the PRF rate as determined by timing generator 144 in accordance with the range setting and the rate of digitization of the analog video signal by analog/digital converter 148. By operating the power modules at a switching rate intermediate the PRF and digitization rates, interference effects are eliminated. 
     Referring next to the block diagram of FIG. 3, the schematic diagram of FIGS. 4a-4c, and the electro-mechanical drawings of FIGS. 5 and 6, the operation of variable range marker (VRM) circuit 154 will be described. Variable range marker circuit 154 provides a variable range mark video signal one range cell wide at a range position which is selected by VRM range adjust control 156. The corresponding value of the range distance in one of, in the example of the preferred embodiment, three alternative selectable dimensions (nautical miles, meters, and yards) may be read on a three or six digit LED display 158 in preferred embodiments which may be located near the top of the face of the screen of CRT 172 upon control panel 146. The three digit display is used for miles while the six digit display is used for yards or meters. 
     The VRM range mark position is determined by the value stored in 16 bit range register 304 (registers 402 and 404). Fifteen of these sixteen bits provide nine bits of resolution (512 range cells) for each of 7 contiguous binary range scale factors in the preferred embodiment. The sixteenth bit provides a &#34;VRM-OFF&#34; indication. Registers 402 and 404 are parallel entry registers with serial shift capabilities. 
     For the majority of the operational time of this circuit, the contents of range register 304 are in a circularly shifted condition with the last bit position of the shift register coupled to the first bit serial input through exclusive OR gate 444 within range update circuit 302. The bit corresponding to one range cell of the selected range scale is located at the LSB end of the register. 
     The nine bits at the LSB end of range register 304 are used to control VRM pulse counter 310 (binary counters 431-433). Between sweep gate signals, VRM pulse counter 310 is preset by an inverted SWEEP GATE signal from inverter 416 to the complement of the count values represented by these bits. During the active state of the SWEEP GATE signal, VRM pulse counter 310 is incremented by one bit count for each range cell as displayed upon CRT 172 as indicated by each READ CLOCK pulse which gates a 2.02 MHz clock pulse through range cell clock select circuit 308 (gates 414 and 415 and inverter 421). When VRM pulse counter 310 reaches a count value of 511, a VRM video pulse is produced. Amplification is provided by gate 448. Upon the next READ CLOCK pulse, the VRM pulse counter 310 advances to a count of 512 at which it remains until the end of the active state of the SWEEP GATE signal for that radar pulse. 
     If the range value contained in range register 304 is greater than 511 range cells of the selected range scale, an overflow condition will be indicated by the activation of the tenth significant bit position of range register 304. When VRM pulse counter 310 is preset to an overflow condition, as may happen when the system is first activated or if the range mark is positioned off scale, VRM pulse counter 310 will remain in the state to which it was preset for the duration of the SWEEP GATE signal and no VRM video pulse will be produced. 
     The value initially stored in range register 304 to set the position of the range mark is changed by means of two VRM control signals LEAD and LAG. These two signals are generated by optical resolver apparatus 201 shown in the views of FIGS. 5 and 6. Alternatively, other types of resolvers such as a magnetic resolver may be used. Cylindrically shaped resolver housing 203 is coupled through shaft 202 to operator rotatable knob 208 upon control panel housing 206. Along the periphery of resolver housing 203 are located a number of longitudinal slots 204 cut through housing 203 at predetermined intervals. There are preferably more of such slots than are shown in FIG. 5, the number being reduced for clarity of illustration. 
     Current furnished light-emitting diodes 214 and 216 through resistors 220 and 218 causes light-emitting diodes 214 and 216 to continuously emit light outwards towards D&#39;arlington-pair phototransistors 210 and 212. Light-emitting diodes 214 and 216 are positioned within housing 203 so that when light is allowed to pass from one of the light-emitting diodes through a slot 204 to one of the D&#39;arlington phototransistors, light from the other one of the light-emitting diodes is partially blocked. The LEAD and LAG signals are produced upon the collectors of the respective phototransistors. Twice an odd number of slots are provided. The phototransistors are positioned such that the LEAD and LAG signals are in quadrature with one another with respect to shaft position. 
     In the preferred embodiment, each one-hundredth of a revolution of control shaft 202 produces an alternate high or low change in level of one of the signals. When the shaft is rotated clockwise, the LEAD signal waveform will be phased in advance of that of the LAG signal while, when shaft 202 is rotated counterclockwise, the LEAD signal waveform will be phased in retard of the LAG signal. 
     As stated above, the value stored in range register 304 is positioned with the bit corresponding to one range cell of the particular range selected at the LSB position of the register which in turn is coupled to the LSB position of VRM pulse counter 310 which is operated at one count per range cell during display time. When the range scale is changed, the binary number stored in range register 304 is shifted to align the appropriate bit in the LSB position. Because of this action, the range mark displayed will stay on a selected target as the range scale is changed and the target changes its relative position on the screen of the display tube. Moreover, also because of the shifting operation, a given amount of rotation of control shaft 202 produces the same distance of movement of the range mark upon the face of the display tube regardless of the range scale selected. Eliminated is the problem of a small rotation producing a large movement on short ranges and very little movement on long ranges. 
     Range update circuit 302 functions to interpret the relative occurrence of transitions in the LEAD or LAG signals and, as a result, to increase or decrease the value stored in range register 304. A detection is made by range update circuit 302 (flip/flops 406 and 408, multiple input register 438, exclusive-OR gates 439-442 and 444, NAND gates 443, 447, and 446, and inverter 445). The relative occurrence of transitions in the LEAD and LAG signals are used to increase or decrease the value stored in range register 304. When shaft 202 of the optical encoder is rotated in one direction or another, an add or subtract indication is interpreted by the circuit from the signals for each incremental change of shaft position. When the shaft is reversed, the first incremental change is ignored so that the shaft must always rotate by at least one increment of position in either direction to change the value set in range register 304. 
     A dimension calculation process is initiated at the beginning of every seventh sweep gate signal for a six digit LED display system and for every fourth sweep gate signal for systems using a three digit LED display. The value change indication and direction of change is stored in register 438 between dimension calculation processes. During each dimension calculation process, the contents of range register 304 is shifted through range update circuit 302 and returned to range register 304. A serial addition or subtraction is performed by exclusive-OR gate 444 within range update circuit 302. The resultant value, which is again stored in range register 304, will be either increased or decreased by a value corresponding to one range cell for the selected range scale or remain unchanged if no change indication has occurred since the last dimension calculation process. Recognition of new change indications is inhibited during each dimension calculation process. 
     Near the conclusion of the dimension calculation process, the contents of range register 304 is positioned with the least significant bit of the 16 bit value stored therein at the next to the LSB end of the register. At this time, the range scale lines (1.5 mile-64 miles and REAL TIME) are sampled simultaneously with the upper 5 bit positions and MSB input of range register 304 by AND&#39;ing the signals together with gates 417-420, 422 and 423 to determine the ranges which would have an overflow condition. The AND&#39;ed signals are encoded to 8-line to 3-bit encoder 424 with the encoded result stored in register 425. If it is determined that none of the scales above the one selected have an overflow condition, the selected scale is used. If any of the scales above the one selected have an overflow condition, the highest of these scales is comparable to a &#34;VRM OFF&#34; indication and will result in the disabling of the digital LED display. The scale selection decision registered as the encoded number within register 425 is used by scale control circuit 306 (gates 417-420, 422, 423, and 430; inverter 426; encoder 424; and register 425) to control the shifting of range registor 304 until the bit which corresponds to a value of 1 range cell upon the selected range scale is positioned at the LSB end of range register 304. 
     Each dimension calculation process is essentially a conversion of the binary values stored in range register 304 to the appropriately scaled decimal value which is to be displayed by digital LED display 158. The conversion is performed by program control processor 315 at a rate determined by an externally supplied 2.02 MHz clock signal. 
     Program control processor 315 includes program counter 326 (counter 466 and 467), instruction memory 324 (read-only memory 471), instruction decoder 322 (decoder 469; gates 472-475, 477, 478, and 481; and inverters 468, 472, 476, 479, and 480), adders 320 (adders 484 and 485; multiplexer 483; gate 320; inverter 450; and flip-flop 455), and accumulator registers 316 (registers 434-437 for which clock signals are provided by gates 429, 456, and 458-460; inverter 457; and flip-flops 452 and 453). In the preferred embodiment, three separate programs are provided depending upon the type of final display desired. Three examples are shown in the tables of Appendix I. In the examples, program number 1 is for conversion to yards, program number 2 for conversion to miles, and program number 3 for conversion to meters. However, other programs may be provided as desired. The program selected is determined by the start count jammed into the parallel inputs of program counter 326 (binary counters 466 and 467). This is done by connecting the program select lines labeled A-C to the numbered terminals of the program select inputs as shown in the table at the lower left of FIG. 4a. The three programs include a total of 155 4-bit word instructions which are permanently stored in instruction memory 324 which may be a read-only or programmable read-only memory. FIG. 7 is a table specifying for each of the 16 possible binary bit output combinations from instruction memory 324 what operations are to be performed corresponding to each instruction. Each instruction within each of the three programs is accessed from instruction memory 324 by program counter 326. Implementation of the instructions is executed by instruction decoder 322. 
     The decimal value to be displayed by digital LED display 158 is generated serially with a word-by-word summation and accumulated in the 8-word by 4-bit accumulator 316 (registers 434-437). Each eighth instruction (shift range register instruction) shifts the next bit of the binary value towards the LSB end of range register 304. If the bit indicates a value of one, each of the following instructions in the series will add the appropriate value to the associated word as it is shifted from accumulator 316 through adder 320 and stored back into accumulator 316 upon the next clock pulse. As each decimal carry is generated, it is stored then added to the next higher significant word. If a bit at the LSB end of range register 304 indicates a value of 0, the words passing through the adder have 0 added to them and remain unchanged. 
     The output of adder 320 is continuously monitored by instruction decoder 322. A count of the last consecutive values of zero is maintained by leading zero counter 318 (counter 482; flip-flop 454; and inventor 449). The last &#34;shift range register&#34; instruction of the sequence will shift the &#34;VRM-OFF&#34; bit to the LSB end of range register 304. This bit normally indicates the presence of a zero. 
     The next group of instructions, the &#34;set significant digits&#34; instructions, holds the contents of accumulator 316 stationary while increasing the count value in leading zero counter 318 by the number of significant digits of accuracy to be displayed. The zero counter value is limited to 7. 
     The next group of instructions, the &#34;round off&#34; instructions serve to round off the value in accumulator 316 to plus or minus one-half increment of the least of the selected significant digits. As each word passes from adder 320 back to accumulator 316, it is replaced by a value of zero and the count in leading zero counter 318 decreases until it is equal to 7. At this point, a value of 5 is added to the word on the input of adders 320. The resultant presence or absence of a carry is stored while the word returned to accumulator 316 is replaced by a value of zero. 
     During the remaining &#34;round off&#34; instructions leading zero counter 318 will carry a count of 8, the carry (if present) will be allowed to propagate, and the resultant summation will be returned to accumulator 316. If the displayed value could contain significant digits to the right of the decimal point, the next eight instructions will be &#34;add zero&#34; instructions. They allow the contents of accumulator 316 to be cycled through adder 320 unchanged to update the count value in leading zero counter 318. 
     These instructions are followed by the &#34;set significant digits&#34; instructions which essentially halt the accumulator contents while increasing the leading zero count by the number of significant digits of accuracy to be displayed. The latter instructions will each also preset decimal point counter 314 (counter 487 and gate 488) to a count state which places the decimal point to the left of the least significant digit in accumulator 316. 
     The next set of instructions, the &#34;decimal right justify&#34; instructions, function to drop off the nonsignificant digits to the right of the eventual decimal point position. With each shift of the contents of accumulator 316, the contents in both leading zero counter 318 and decimal point counter 314 are increased by a value of one until the count and leading zero counter 318 is equal to 7. The position of the contents of accumulator 316 and the count of leading zero counter 318 and decimal point counter 314 will then remain unchanged for the remainder of the &#34;decimal right justify&#34; instructions. 
     The following three sets of instructions cause the contents of accumulator 316 to be cycled through adder 320 unchanged by adding 0&#39;s to update the count value in leading zero counter 318. The &#34;set significant decimal&#34; instruction, the first of these three sets, decimal point counter 314 is inhibited from advancing. The effect of this operation is to shift the decimal point to the left with respect to the digits until it is properly positioned. The second of the sets are &#34;add zero&#34; instructions. The third set is a single &#34;start digital display&#34; instructions which also acts as an &#34;add zero&#34; instruction. This instruction presets program counter 326 to the values determined by its preset inputs and also initiates operation of scale control circuit 306. 
     If the circuit is programmed to always display all significant digits to the left of the decimal point as is the case for yards and meters, another sequence of instructions is used after the last &#34;round off&#34; instruction. First, a &#34;set significant digits&#34; instruction is used to preset decimal point counter 314 to a count state which places the decimal point to the left of the least significant digit in accumulator 316. However, this digit is never displayed. Then, a set of seven &#34;add zero&#34; instructions will occur to update the count value in leading zero counter 318. The final instruction is again the &#34;start digital display&#34; instruction. Once initiated by the &#34;start digital display&#34; instruction the scale control circuit 306 will control the remaining operations of the variable range marker circuits. 
     As described earlier, the first operation of scale control circuit 306 is to sample the range control lines and associated bit positions of range register 304. This is done by the &#34;start digital display&#34; instructions to determine the scale to be selected. The scale selection decision is then stored in register 425 which also functions as a counting register. If the &#34;VRM OFF&#34; bit of range register 304 is in the logical 1 state, accumulator 316 is cleared, leading zero counter 318 is set to a count of 8, decimal point counter 314 is set to place the decimal to the left of the least significant digit in accumulator 316, and also 16 bits of range register 304 are set to the one state. If the &#34;VRM OFF&#34; bit of range register 304 is in the zero state, the contents of accumulator 316, leading zero counter 318, decimal point counter 314, and range register 304 are unaffected. The program counter will continue to be advanced. During this time the position of the contents in accumulator 316 and the counts of leading zero counter 318 and decimal point counter 314 will be inhibited from changing. The position of the contents in range register 304 are changed by each &#34;shift range register&#34; instruction. Each of these instructions is accompanied by addressing counting register 425 within scale control circuit 306. 
     When the bit which corresponds to a value of one range cell of the selected range scale is positioned at the LSB end of range register 304 as indicated by counting register 425 of scale control circuit 306, program counter 326 is inhibited from further advancement and the segment anode driving of LED display 158 is enabled. At this point, the dimension calculation process has been finished and the display output process is begun. While the dimension calculation process was performed using the 2.02 MHz clock, the display output process is operated at the SWEEP GATE signal rate. 
     At the beginning of each succeeding SWEET GATE signal, the contents of accumulator 316 are shifted and the counts of leading zero counter 318 and decimal point counter 314 are advanced. Zero values are entered at the input stage of accumulator 316. As each digit reaches the output end of accumulator 316 a corresponding seven segment code is produced by anode driving circuit 312 (decoder 462 and resistors 464, 465 and 499) which is decoded by seven segment decoder 462 for driving display lines A-G as would be used in a 6 digit display. At the same time, the common cathode line is selected (display lines 1-6 as selected by decoder 461 within scale control circuit 306). If either leading zero counter 318 indicates a count of less than 8 or decimal point counter 314 indicates that the decimal point is yet to be displayed, the selected cathode line will be activated and the digital display thus eliminated. The decimal point anode (DP) is activated by decimal point counter 314 when the appropriate cathode line is selected and activated. Once leading zero counter 318 reaches a count a 8, digits to the left of the decimal point will be blanked by not activating the selected cathode line. Thus a display is produced with a non-zero digit in the left-most display position with the decimal point appropriately positioned. A three digit display may be produced by using only cathode lines 1-3. In that case, the last three cathode lines are selected at the 2.02 MHz rate resulting in a higher duty cycle for each of the remaining three active digits. The anode driving circuit is disabled when the last three cathode lines are selected. 
     The next dimension calculation process begins at the end of the selection period of the sixth cathode line. The dimension calculation program is continued from instruction memory 324 at which program counter 326 is previously halted at the 2.02 MHz rate. Selection between 3 and 6 digit displays is also made internally by connecting the upper input of NOR gate 460 marked E1 to the terminal marked E3 in the case of a six digit display and to the terminal marked E2 in the case of a three digit display. 
     The brightness of the LED display digits is set by adjusting the base drive to transistor 495 by variable resistor 501. The base drive to transistor 495 in turn controls the maximum voltage upon the emitter of transistor 490 and hence the available current through resistors 465 to the LED display device anodes. 
     This concludes the description of preferred embodiments of the invention. Although preferred embodiments have been described, it is believed that numerous modifications and alterations thereto would be apparent to one having ordinary skill in the art without departing from the spirit and scope of the invention. 
     
         ______________________________________APPENDIX INautical MilesAddress   0.sub.4 0.sub.3 0.sub.2 0.sub.1                 Address    0.sub.4 0.sub.3 0.sub.2 0.sub.1______________________________________652       0000        705        1000653       1011        706        0110654       1000        707        0110655       0110        710        0110656       0110        711        0110657       0110        712        0000660       0110        713        0110661       0110        714        0110662       0000        715        1010663       0110        716        0110664       1011        717        0110665       0110        720        0110666       0110        721        0110667       0110        722        0000670       0110        723        0110671       0110        724        0110672       0000        725        0110673       0110        726        0110674       0110        727        0110675       0111        730        0110676       0110        731        0110677       0110        732        0000700       0110        733        0110701       0110        734        0110702       0000        735        1100703       0110        736        0111704       0110        737        0110740       0110        774        0110741       0110        775        1100742       0000        776        1011743       0110        777        1000744       0110        000        0110745       1000        001        0110746       1001        002        0000747       0110        003        0110750       0110        004        0110751       0110        005        1000752       0000        006        0111753       0110        007        1011754       0110        010        0110755       1010        011        0110756       1100        012        0000757       0110        013        0110760       0110        014        0110761       0110        015        1010762       0000        016        1000763       0110        017        0110764       0110        020        0111765       1110        021        0110766       1000        022        0000767       0111        023        0110770       0110        024        0110771       0110        025        1110772       0000        026        1010773       0110        027        0110030       1000        056        0110031       0110        057        0110032       0000        060        0110033       0110        061        0110034       0110        062        0110035       1100        063        0110036       1111        064        0110037       0110        065        0110040       1010        066        0001041       0110        067        0001042       0000        070        0001043       0001        071        0010044       0001        072        0010045       0001        073        0010046       0011        074        0100047       0011        075        0100050       0011        076        0100051       0011        077        0110052       0011        100        0110053       0011        101        0110054       0011        102        0110055       0011        103        0101______________________________________ 
    
     
         ______________________________________MetersAddress   0.sub.4 0.sub.3 0.sub.2 0.sub.1                 Address    0.sub.4 0.sub.3 0.sub.2 0.sub.1______________________________________125       0000        161        0110126       0111        162        1101127       1111        163        1001130       1000        164        0110131       1100        165        0000132       1010        166        1010133       0110        167        1100134       0110        170        1100135       0000        171        0110136       1001        172        1010137       1110        173        1101140       1011        174        0110141       1000        175        0000142       1111        176        1110143       0110        177        1000144       0110        200        1001145       0000        201        0111146       1100        202        1110147       1100        203        1010150       0111        204        0111151       1011        205        0000152       1110        206        1100153       0111        207        1011154       0110        210        1100155       0000        211        1000156       1000        212        1100157       1001        213        1111160       1001        214        1000215       0000        251        1000216       1000        252        0110217       0111        253        1010220       1001        254        1101221       1011        255        1010222       1000        256        0000223       1111        257        0110224       1011        260        0110225       0110        261        1011226       0000        262        0110227       1000        263        1110230       1100        264        1010231       0110        265        1111232       1011        266        0110233       1110        267        0000234       0111        270        0110235       0111        271        0110236       0000        272        0111237       1011        273        1100240       1000        274        1111241       0111        275        1110242       0110        276        0111243       1101        277        0000244       1001        300        0110245       1000        301        0110246       0000        302        1000247       0110        303        1000250       1011        304        1111305       1101        334        0110306       1001        335        0110307       0000        336        0110310       0110        337        0110311       0110        340        0110312       1010        341        0110313       1010        342        0110314       1110        343        0110315       1011        344        0001316       1101        345        0001317       0110        346        0001320       0000        347        0010321       0001        350        0010322       0001        351        0010323       0001        352        0100324       0011        353        0100325       0011        354        0100326       0011        355        0110327       0011        356        0110330       0011        357        0110331       0011        360        0110332       0011        361        0101333       0011______________________________________ 
    
     
         ______________________________________YardsAddress   0.sub.4 0.sub.3 0.sub.2 0.sub.1                 Address    0.sub.4 0.sub.3 0.sub.2 0.sub.1______________________________________400       0000        434        1010401       1100        435        0110402       0110        436        0110403       1011        437        0110404       0110        440        0110405       0110        441        0000406       0110        442        0110407       0110        443        0111410       0000        444        1110411       1000        445        0110412       0111        446        0110413       0110        447        0110414       0111        450        0110415       0110        451        0000416       0110        452        0110417       0110        453        1000420       0000        454        1100421       1011        455        0111422       1000        456        0110423       0110        457        0110424       1000        460        0110425       0110        461        0000426       0110        462        0110427       0110        463        1010430       0110        464        1000431       0000        465        1001432       1011        466        0110433       0110        467        0110470       0110        524        1110471       0000        525        0111472       0110        526        1011473       1110        527        0110474       1010        530        0110475       1100        531        0000476       0110        532        0110477       0110        533        1110500       0110        534        1100501       0000        535        1001502       0110        536        0110503       1100        537        0111504       1111        540        0110505       1000        541        0000506       0111        542        0110507       0110        543        1100510       0110        544        1001511       0000        545        1101512       0110        546        0110513       1000        547        1000514       1111        550        0110515       1011        551        0000516       1000        552        0110517       0110        553        1000520       0110        554        1101521       0000        555        1010522       0110        556        0111523       1010        557        1010560       0110        577        0011561       0000        600        0011562       0110        601        0011563       1010        602        0011564       1010        603        0011565       1111        604        0011566       1000        605        0001567       1110        606        0110570       0110        607        0110571       0000        610        0110572       0001        611        0110573       0001        612        0110574       0001        613        0110575       0011        614        0110576       0011        615        0101______________________________________ 
    
     
         ______________________________________APPENDIX IIPARTS LISTREFERENCE NO.           TYPE______________________________________Resistors410                     1000Ω412,413                 4700Ω427                      150Ω428                      300Ω464                      200Ω465, 492                 390Ω491                     2200Ω494                      750Ω496                     1200Ω499                     1500Ω501                     1000Ω, 1 wattTransistors490                     2N2907A495                     2N2219Capacitors411                     0.05 μfd.493, 498                15 μfd.Integrated Circuits402, 404, 434-437       SN74164406, 408, 452-455       SN74174414, 430, 460, 488      SN7402415, 429, 439, 440-442, 444, 448                   SN7486416, 421, 426, 445, 450, 457, 468, 470,                   SN7404476, 479, 480417-420                 SN7408422, 423                SN74H11424                     SN74148425, 431-433, 466, 467, 482, 487                   SN74163438                     SN74298446, 447, 451, 456, 459, 474, 477, 478                   SN7400458, 472, 473, 475, 481, 486                   SN7410461                     SN74145462                     SN7448469                     SN74S138471                     MMI6306______________________________________ Note: All resistors are 1/4 watt 5% unless otherwise specified; SN designation integrated circuits are Texas Instruments, Inc. types; MMI designation integrated circuit is Monolithic Memories Incorporated type.