Abstract:
A charge transfer amplifier includes a first stage charge transfer amplifier coupled to a positive capacitive feedback mechanism. The positive capacitive feedback mechanism is attached to the output terminal of a first stage charge transfer amplifier. This reduces the capacitance viewed at the output terminal of the first stage charge transfer capacitor thus increasing the overall gain of the charge transfer amplifier. The positive capacitive feedback mechanism includes a second stage amplifier having an output terminal capacitively coupled back to the output terminal of the first stage charge transfer amplifier. The coupling of the positive capacitive feedback mechanism to the charge transfer amplifier allows for enhanced amplifier gain while still retaining the beneficial characteristics of charge transfer amplifiers generally.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation-in-part of U.S. patent application Ser. No. 09/451,562, filed Nov. 30, 1999, which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. The Field of the Invention 
     The present invention relates to systems and methods for amplifying electrical signals. More specifically, the present invention relates to systems and methods for enhancing charge transfer amplifier gain. 
     2. The Prior State of the Art 
     There are many circuits and methods conventionally available for amplifying an electrical signal. One type of amplifier is called a charge transfer amplifier. Charge transfer amplifiers operate on the principle of capacitive charge sharing. Voltage amplification is achieved by transferring a specific amount of charge between appropriately sized capacitors through an active device. 
     FIG. 1 illustrates a charge transfer amplifier  100  that utilizes an nMOS transistor N 1  to transfer charge between capacitors CT and CO. The operation of the nMOS charge transfer amplifier  100  will now be described in order to illustrate the basic principle of charge transfer amplification. 
     The nMOS charge transfer amplifier  100  operates in a cycle of three phases including a reset phase, a precharge phase, and an amplify phase. FIG. 2 is a signal timing diagram for two input signals S 1  and S 2  with respect to the cycle phase that the nMOS charge transfer amplifier  100  is operating in whether that phase be (a) the reset phase, (b) the precharge phase or (c) the amplify phase. The two input signals S 1  and S 2  control corresponding switches S 1  and S 2  of FIG.  1 . Switch !S 1  corresponds to the inverse phase of the input signal S 1 . 
     The cycle begins with the (a) reset phase in which both input signals signal S 1  and S 2  are high indicating that switches S 1  and S 2  are closed and that switch !S 1  is open. Since the switch S 1  is closed, the upper terminal of capacitor CT (i.e., node A) is discharged through the switch S 1  to voltage Vss. Since the switch S 2  is closed, the upper terminal of capacitor CO (i.e., node B is charged to a voltage V PR . The open switch !S 1  prevents static current from flowing through the nMOS transistor N 1 . 
     After the reset phase is the (b) precharge phase in which the signal S 1  is low indicating that switch S 1  is open and the switch !S 1  is closed, and in which the signal S 2  is high indicating that the switch S 2  remains closed. Thus, the upper terminal of the capacitor CO (i.e., node B) remains charged at the precharge voltage V PR . This precharge voltage V PR  is high enough that current flows from node B to the capacitor CT (and node A) through the nMOS transistor N 1  and the switch !S 1 . For example, if the precharge voltage V PR  is at least equal to the input voltage V IN  at the gate of the nMOS transistor N 1 , then the discharge continues until the voltage at the capacitor CT increases to be equal to the input voltage V IN  minus the threshold voltage (hereinafter “V TN ”) of the nMOS transistor N 1 . At that point, the nMOS transistor N 1  enters the cutoff region and current flow to the capacitor C T  substantially ceases. Thus, at the end of the precharge phase, the capacitor CO ideally has a voltage of V PR  while the capacitor CT has a voltage of V IN  -V TN . 
     After the precharge phase is the (c) amplify phase in which both signals S 1  and S 2  are low indicating that both switches S 1  and S 2  are open. During the amplify phase, an incrementally positive input voltage change ΔV IN  at the gate of the nMOS transistor N 1  will cause the nMOS transistor N 1  to turn on thereby allowing current to flow through the nMOS transistor N 1  until the nMOS transistor is again cutoff. For small incrementally positive voltage changes ΔV IN , the nMOS transistor N 1  will cutoff when the voltage on the upper terminal of the capacitor CT (i.e., node A) increases by the incrementally positive voltage change ΔV IN . The amount of charge transferred to the capacitor CT in order to produce this effect is equal to the incrementally positive voltage change ΔV IN  times the capacitance C T  of the capacitor CT. 
     Since the charge ΔV IN ×C T  transferred to the capacitor CT came from node B through transistor N 1 , the charge ΔV IN ×C T  was drawn from the capacitor CO. Thus, the voltage at the capacitor CO and the output voltage V OUT  will change by ΔV IN ×(C T /C 0 ). If the capacitance C T  is greater than the capacitance C 0 , amplification occurs. 
     One advantage of the nMOS charge transfer amplifier  100  is that the voltage gain and power consumption maybe controlled by setting the capacitance of the capacitors CO and CT as well as by setting the capacitance ratio C T /C 0 . Another advantage of charge transfer amplifiers in general is that the circuit performance is generally unaffected by the absolute values of the supply voltage Vss and Vdd as long as these voltages permit proper biasing during the reset and precharge phases. In other words, charge transfer amplifiers have high supply voltage scalability in that no changes are needed for a charge transfer amplifier to operate using a wide range of supply voltages Vss and Vdd. 
     Although the nMOS charge transfer amplifier  100  has these advantages, amplification only occurs in the nMOS charge transfer amplifier  100  if the input gate voltage change ΔV IN  is positive. A negative gate voltage change ΔV IN  would only cause the nMOS transistor N 1  to enter deeper into the cutoff region. Thus, charge transfer between node A and node B would be stifled thereby preventing amplification. 
     FIG. 3 shows a conventional CMOS charge transfer amplifier  300  that amplifies using positive input voltage changes ΔV IN  as well as negative input voltage changes ΔV IN . The CMOS charge transfer amplifier  300  includes the nMOS charge transfer amplifier  100  described above. For clarity, the nMOS charge transfer amplifier  100  is shown in FIG. 3 as being enclosed by a dotted box. 
     The CMOS charge transfer amplifier  300  also includes a partially overlapping pMOS charge transfer amplifier  301  which is shown in FIG. 3 enclosed by a dashed box for clarity. The pMOS charge transfer amplifier  301  shares the voltage input line  302 , the voltage output line  303  and the precharge line  304  with the nMOS charge transfer amplifier  100 . The pMOS charge transfer amplifier  301  is structured similar to the nMOS charge transfer amplifier  100  except that the pMOS charge transfer amplifier  301  uses a pMOS transistor P 1  instead of an nMOS transistor N 1  for transferring charge between capacitors. Also, node A′ of the pMOS charge transfer amplifier  301  is reset to a high voltage Vdd instead of the low voltage Vss and is capacitively coupled to the high voltage Vdd instead of the low voltage Vss. 
     The general operation of the pMOS charge transfer amplifier  301  for negative input voltage changes ΔV IN  is similar to the operation of the nMOS charge transfer amplifier  100  for positive voltage changes ΔV IN  Thus, the input signals S 1  and S 2  of FIG. 2 are used in the operation of the CMOS charge transfer amplifier  300 . Due to the complementary nature of the nMOS charge transfer amplifier  100  and the pMOS charge transfer amplifier  301 , the CMOS charge transfer amplifier  300  amplifies for both positive and negative input voltage changes ΔV IN . 
     The CMOS charge transfer amplifier  300  is advantageous in that it consumes no static current, capitalizes on parasitic capacitors, is memory less, operates over a wide voltage supply range, produces little noise, is insensitive to threshold voltage fluctuations, and comprises relatively few devices. However, it would represent an advancement in the art to create a system and method in which the gain of the charge transfer amplifier is enhanced without giving up any of the advantages inherent in the charge transfer amplifier. 
     SUMMARY AND OBJECTS OF THE INVENTION 
     The foregoing problems in the prior state of the art have been successfully overcome by the present invention, which is directed to an enhanced gain amplifier for use with charge transfer amplifiers. A positive capacitive feedback mechanism is attached from the output terminal to an intermediate terminal of the charge transfer amplifier. This reduces the capacitance viewed at the intermediate terminal of the charge transfer amplifier thus increasing the overall gain of the charge transfer amplifier. The positive capacitive feedback mechanism includes a second stage amplifier having an output terminal capacitively coupled back to the output terminal of the first stage charge transfer amplifier. The coupling of the positive capacitive feedback mechanism to the charge transfer amplifier allows for enhanced amplifier gain while still retaining the beneficial characteristics of the charge transfer amplifier. 
     In one embodiment, the first stage charge transfer amplifier is a differential mode charge transfer amplifier. The second stage amplifier may also be a differential mode charge transfer amplifier with no input coupling portion required. The positive capacitive feedback occurs by capacitively coupling one output terminal of the second stage differential mode charge transfer amplifier to an output terminal of the first stage differential mode charge transfer amplifier. Similarly, the other output terminal of the second stage differential mode charge transfer amplifier is capacitively coupled to the other output terminal of the first stage differential mode charge transfer amplifier. This positive capacitive feedback mechanism increases the gain of the first differential mode charge transfer amplifier. This additional gain is fed to the second stage differential mode charge transfer amplifier thereby improving the gain of the entire cascaded differential mode charge transfer amplifiers. In one embodiment, the feedback capacitors are structured similar to transistors within the second stage differential mode charge transfer amplifiers to improve the performance of the cascaded differential mode charge transfer amplifiers over a wide range of temperatures, bias conditions and threshold voltages. 
     Additional advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or maybe learned by the practice of the invention as set forth hereinafter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order that the manner in which the above-recited and other advantages of the invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which: 
     FIG. 1 is a circuit diagram of a conventional nMOS charge transfer amplifier; 
     FIG. 2 is a timing diagram of several waveforms used to operate switches S 1  and S 2  in order to properly operate the nMOS charge transfer amplifier of FIG. 1, and the CMOS charge transfer amplifier of FIG. 3; 
     FIG. 3 is a circuit diagram of a conventional CMOS charge transfer amplifier which can amplify positive and negative changes in the input voltage; 
     FIG. 4 is a broad schematic diagram of an enhanced gain amplifier that uses positive capacitive feedback in accordance with the present invention; 
     FIG. 5 illustrates in detail an embodiment of the enhanced gain amplifier of FIG. 4 in which the charge transfer amplifier is a conventional CMOS charge transfer amplifier; 
     FIG. 6 illustrates a differential mode charge transfer amplifier; 
     FIG. 7 illustrate in detail an embodiment of the enhanced gain amplifier of FIG. 4 in which the charge transfer amplifier is a different mode charge transfer amplifier and in which the second stage amplifier is a differential mode charge transfer amplifier; 
     FIG. 8 illustrates simulated output of the circuit of FIG. 7 for a sampling rate of 10,000 samples per second for feedback capacitances of 0, 10 and 20 femtoFarads; 
     FIG. 9 illustrates simulated output of the circuit of FIG. 7 for a sample rate of 200,000 samples per second for feedback capacitances of 0, 10 and 20 femtoFarads; 
     FIG. 10A illustrates in more detail the structure of a feedback capacitor CF 1  of FIG. 7; and 
     FIG. 10B illustrates in more detail the structure of a feedback capacitor CF 2  of FIG.  7 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention is described below by using diagrams to illustrate either the structure or processing of embodiments used to implement the circuits and methods of the present invention. Using the diagrams in this manner to present the invention should not be construed as limiting of the scope of the invention. Specific embodiments are described below in order to facilitate an understanding of the general principles of the present invention. However, the principles of the present invention are not intended to be limited to these embodiments. Various modifications and variations will be apparent to one skilled in the art after having reviewed this disclosure. 
     FIG. 4 illustrates an overall schematic diagram of an enhanced gain charge transfer amplifier  400  in accordance with the present invention. The enhanced gain amplifier includes a charge transfer amplifier  410  represented schematically by a box in FIG.  4 . The charge transfer amplifier  410  includes at least one input terminal  411  and at least one output terminal  412 . A capacitive loading means  420  is coupled to the output terminal  412  of the charge transfer amplifier  410 . Additional, a positive feedback means  430  is also coupled to the capacitive loading means  420  so as to reduce the capacitance of the capacitive loading means  420 . 
     Components of a positive feedback means  430  that accomplish this reduction in the capacitance of the capacitive loading means include an amplifier  440  having an input terminal  441  coupled to the output terminal  412  of the charge transfer amplifier  410 . The positive feedback means  430  also includes a positive feedback capacitor  450  having one terminal  451  connected to the output terminal  442  of the amplifier  430  and a second terminal  452  connected to the output terminal  412  of the charge transfer amplifier  410  and to the capacitive loading means  420 . FIG. 5 illustrates an enhanced gain amplifier  500  that corresponding to FIG. 4 in which the charge transfer amplifier  410  is a conventional CMOS charge transfer amplifier of the variety described with respect to FIG.  3  and in which the capacitive loading means  420  includes the output capacitor CO of the charge transfer amplifier having one terminal coupled to a fixed voltage and another terminal coupled to the output terminal  412  of the charge transfer amplifier  410 . 
     As described above with respect to the conventional CMOS charge transfer amplifier of FIG. 3, without the positive feedback means  430 , a voltage change of ΔV IN  at the input terminal  411  of the charge transfer amplifier  410  will result in an amplified voltage change of ΔV IN ×(CT/CO), where “CT” is the capacitance of the capacitor CT L  for positive input voltage changes ΔV IN , where “CT” is the capacitance of the capacitor CT U  for negative input voltage change ΔV IN , and where CO is the capacitance of the capacitor CO. The lower the output capacitance CO, the greater the gain of the charge transfer amplifier  410 . 
     The positive feedback means  430  has the effect of reducing the apparent output capacitance at the output terminal  412  of the charge transfer amplifier  410 . Thus, the gain of the charge transfer amplifier is increased as compared to not having the positive feedback means  430 . 
     The charge transfer amplifier  410  may also be a differential mode charge transfer amplifier of the kind described in co-pending U.S. patent application Ser. No. 09/1451,562, filed Nov. 30, 1999, which is incorporated herein by reference in its entirety. FIG. 6 illustrates a differential mode charge transfer amplifier  600 . In summary, the differential mode charge transfer amplifier uses the signal waveforms of FIG. 2 to perform differential mode amplification in which an input differential voltage (V IN -V REF ) is used to produce an amplifier differential voltage between the two output terminals (i.e., node P and node Q). The detailed operation and other advantages of the differential mode charge transfer amplifier are described in U.S. patent application Ser. No. 09/451,562, previously incorporated by reference. 
     FIG. 7 illustrates an enhanced gain amplifier  700  in which the charge transfer amplifier  410  is a differential mode charge transfer amplifier. Note, however, that although the differential mode charge transfer amplifier may include a capacitive loading means  420  in the form of an actual capacitor coupling each of the output terminals to a fixed voltage, these capacitors are lacking in the charge transfer amplifier  410 . For example, referring to the differential mode charge transfer amplifier illustrated in FIG. 6, a capacitor CO 1  couples one output terminal (node P) to a fixed voltage while a capacitor CO 2  couples the other output terminal (node Q) to a fixed voltage. The capacitive load means  420  may include these capacitors CO 1  and CO 2  configured as shown in FIG.  6 . However, the capacitive loading means  420  in FIG. 7 is the inherent gate capacitance at the transistors MP 3  and MN 3  for the first output terminal (node P) and the inherent gate capacitance at the transistors MP 4  and MN 4  for the second output terminal (node Q). By eliminating the capacitors CO 1  and CO 2 , the overall amplifier size may be reduced. 
     The positive feedback means  430  of the enhanced gain amplifier includes a second stage differential mode charge transfer amplifier. The second stage differential mode charge transfer amplifier is modified as compared to the differential mode charge transfer amplifier shown in FIG. 6 in that the input coupling portion  403  is removed. The input coupling  403  is important to the operation of the differential mode charge transfer amplifier  600  shown in FIG. 6 as it ensures good common mode range and accurate differential mode signal coupling. However, in the enhanced gain amplifier  700  of FIG. 7, the input terminals of the second stage differential mode charge transfer amplifier are precharged to the same voltage as the output terminals of the first stage differential mode charge transfer amplification. Thus, input coupling is not needed in the second stage in order to ensure good common mode range and accurate differential mode signal coupling. The removal of the input coupling portion from the second stage amplifier reduces the size of the enhanced gain amplifier  700  as compared to including the input coupling. However, the second stage differential mode charge transfer amplifier may include the input coupling as desired. If included, the input terminals of the second stage differential mode charge transfer amplifier, may or may not, be precharged to the same voltage as the output terminals of the first stage differential mode charge transfer amplifier. 
     The positive feedback means  430  includes a positive feedback capacitor CF 1  capacitively coupling an output terminal of the second stage differential mode charge transfer amplifier to a first output terminal of the first stage differential mode charge transfer amplifier thereby reducing the apparent capacitance at the first output terminal of the first stage differential mode charge transfer amplifier. In addition, another positive feedback capacitor CF 2  capacitively couples the other output terminal of the second stage differential mode charge transfer amplifier to the second output terminal of the first stage differential mode charge transfer amplifier thereby reducing the apparent capacitance at the second output terminal of the first stage differential mode charge transfer amplifier. 
     The reduction in capacitance at the output terminals of the first stage differential mode charge transfer amplifier increases the gain of the first stage differential mode charge transfer amplifier. This increase gain is again magnified with the second stage differential mode charge transfer amplifier to produce an even larger gain at the output nodes of the second stage differential mode charge transfer amplifier thereby producing a differential output voltage of VO 1 -V 02 . 
     In operation, at a given sampling rate, the feedback capacitors CF 1  and CF 2  will cause the first stage differential mode charge transfer amplifier to exhibit a reduced gain due to the increased load capacitance at nodes P and Q. However, as the enhanced gain amplifier  700  proceeds further into the amplify phase of the cycle, the positive feedback capacitors CF 1  and CF 2  will couple some of the output signal back to nodes P and Q thereby increasing the gain of the first stage differential mode charge transfer amplifier. The overall gain of the enhanced gain amplifier  700  will increase to more than that obtainable by simply cascading the first and second stage differential mode charge transfer amplifiers without positive capacitive feedback. 
     FIG. 8 shows simulation results where the sample rate is 10,000 samples per second. The enhanced gain amplifier  700  is stimulated with a 10 milliVolt differential. The amplifier response in millivolts during the Amplify phase thus represents the gain of the enhanced gain amplifier  700 . Simulation results are given for a feedback capacitance of 0 femtoFarads (fF), 10 fF and 20 fF. The results at 0 fF would represent no positive feedback capacitance. As apparent from FIG. 8, the gain is increased as the feedback capacitance increases. FIG. 9 shows simulation results where the sample rate is 200,000 samples per second. Increase amplifier gain is demonstrated at this sampling rate as well. 
     As demonstrated in FIGS. 8 and 9, for smaller feedback capacitances, the overall gain increases the larger the feedback capacitance. However, if feedback capacitances are too large, the gain of the second stage amplifier tends to degrade towards zero thereby reducing the overall gain of the enhanced gain amplifier. Thus, the feedback capacitances should not be so large as to significantly degrade the gain in the overall system. 
     In one embodiment of the invention, the feedback capacitor CF 1  is structured similar to the transistors MN 4  and MP 4  while the feedback capacitor CF 2  is structure similar to the transistors MN 3  and MP 3 . The similarity in structure allows for the gate capacitance across MN 3  and MP 3  (and MN 4  and MP 4 ) to change proportionally with the capacitance of the corresponding feedback capacitor CF 2  (and CF 1 ) with large variation in temperature, bias conditions and threshold voltages. 
     FIG. 10A illustrates in detail the preferred structure of the feedback capacitor CF 1 . The feedback capacitor exists between node Q and node VO 1 . The feedback capacitor CF 1  includes a non-operational nMOS transistor which is structured similar to transistor MN 4 , and a non-operational pMOS transistor which is structure similar to transistor MP 4 . The gates of each of the nMOS and pMOS transistors are coupled to node Q forming one terminal of the capacitor CF 1  just as the gates of the transistors MP 4  and MN 4  form one terminal of an inherent gate capacitor coupled to the node Q. The body regions of the nMOS and pMOS transistors are coupled to the output terminal VO 1  forming the other terminal of the feedback capacitor CF 1 . The dimensions of the nMOS and pMOS transistors in the feedback capacitor CF 1  are preferably in proportion to the dimensions of the transistors MN 4  and MP 4  in the second stage differential mode charge transfer amplifier. Due to this similar parallel structure, the capacitive behavior of the feedback capacitor CF 1  will change proportionally with the capacitive behavior of the inherent capacitor formed by transistors MN 4  and MP 4 . Therefore, the performance of the enhanced mode amplifier  700  will be consistent across a wide range of temperatures, bias conditions, and threshold voltages. FIG. 10B shows a preferred structure of the second feedback capacitor CF 2  which is similar to the structure of FIG. 10A except that the nMOS transistor is similar in structure to the transistor MN 3  while the pMOS transistor is similar in structure to the transistor MP 3 . 
     The present invention maybe embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.