Abstract:
The present invention provides a method of connecting an integrated circuit to a substrate and a corresponding circuit arrangement. Connecting occurs by performing the steps of: providing a main area (HF 1 ) of the integrated circuit ( 1 ), which has an electrical contacting region ( 2 ), with a mechanical supporting structure ( 3   a   , 3   b   ; 33   a   , 33   b   , 33   c   ; 43   a   , 43   b   , 43   c ); providing a solderable surface region ( 5   a   , 5   b   ; 35   a   , 35   b   , 35   c   ; 60   a   , 60   b   , 60   c ) of the mechanical supporting structure ( 3   a   , 3   b   ; 33   a   , 33   b   , 33   c   ; 43   a   , 43   b   , 43   c ); providing a solderable terminal region ( 10; 5, 30; 40, 50 ), which is electrically connected to the electrical contacting region ( 2 ), on the main area (HF 1 ) of the integrated circuit ( 1 ); providing a main area (HF 2 ) of the substrate ( 20 ) with a first soldering region ( 22′, 23′; 22′, 23′, 22″, 23″ ), which can be aligned with the solderable surface regions ( 5   a   , 5   b   ; 35   a   , 35   b   , 35   c   ; 60   a   , 60   b   , 60   c ), and with a second soldering region ( 22, 23 ), which can be aligned with the solderable terminal region ( 10; 5, 30; 40, 50 ); and simultaneous soldering of the surface regions ( 5   a   , 5   b   ; 35   a   , 35   b   , 35   c   ; 60   a   , 60   b   , 60   c ) to the first soldering region ( 22′, 23′; 22′, 23′, 22″, 23″ ) and of the terminal region ( 10; 5, 30; 40, 50 ) to the second soldering region ( 22, 23 ).

Description:
FIELD OF INVENTION 
   The present invention relates to a method of connecting an integrated circuit to a substrate and to a corresponding circuit arrangement. 
   RELATED APPLICATION 
   Pursuant to 35 USC § 119 this application claims the benefit of German Patent Application No. 102 27 342.1, filed Jun. 19, 2002. 
   BACKGROUND 
   Although it can in principle be applied to any desired integrated circuits, the present invention and the problems on which is based are explained with reference to chips with integrated circuits using silicon technology. 
   Customary solutions for connecting an integrated circuit to a substrate are the use of solder balls of ball-grid arrays for the mechanical connection and the additional use of an underfilling, in order to increase the stability. The underfilling usually consists of an epoxy resin which is filled into the gap between the chip and the substrate. The underfilling serves for increasing the adhesion of the chip on the substrate and for increasing the stability in the x, y and z directions. A further function of the underfilling is to reduce the stresses which occur during temperature changes, and are caused by the thermal mismatch of the chip material and the substrate material. 
   However, it has been found to be disadvantageous with the customary solutions that the connection by the solder balls between the chip and the substrate has inadequate mechanical stability. Therefore, an underfilling is additionally used to increase the mechanical stability of the system. The introduction of the underfilling material is usually carried out at module level, to be precise after the reflow soldering of the components. 
   This underfilling process has the following disadvantages. 
   It is a serial process, in which a drop of the underfilling material has to be placed onto the edges of each individual soldered chip. It is not possible to make the process a parallel process. Moreover, the process is a slow process, since the application of each individual drop of underfilling material requires considerable time. The process cannot be reproduced very well, since bubbles and voids often remain between the chip and the substrate. Furthermore, it does not make it possible to produce delimited adhesion regions and regions which are free from underfilling material. Finally, the process is not suitable for repairing mounted circuit arrangements. 
   As a result of the disadvantages mentioned above, the process costs are high and the process is complex. 
   SUMMARY 
   One object of the present invention is to provide a more simple and less costly method of connecting an integrated circuit to a substrate and a corresponding circuit arrangement. 
   The idea on which the present invention is based is that a main area of the integrated circuit is provided with a mechanical supporting region, which has a solderable surface region, and also with a solderable electrical terminal region. The main area of the substrate is provided with a first soldering region, which can be aligned with the solderable surface region, and with a second soldering region, which can be aligned with the solderable terminal region. Then a simultaneous soldering of the surface region to the first soldering region and of the terminal region to the second soldering region is performed. 
   One advantage of the method according to the invention and of the corresponding circuit arrangement is the high mechanical stability in the x, y and z directions of the mounted circuits without the necessity for customary underfilling. The method according to the invention can be carried out at wafer level. Consequently, thousands of chips can be processed in parallel in one step. This drastically increases the cost efficiency and the speed. 
   The process according to the invention makes it possible to carry out the soldering connection simultaneously with the connection which increases the mechanical stability. Therefore, no additional process steps mare necessary during module processing. Furthermore, the process according to the invention can be carried out on any customary packaging line and, moreover, makes it possible for defectively mounted chips to be repaired in a simple manner. 
   According to a preferred development, the mechanical supporting structure has a plurality of discrete supports. 
   According to a further preferred development, the mechanical supporting structure has a continuous supporting ring. 
   According to a further preferred development, the surface region is metallized in a separate step. 
   According to a further preferred development, the metallizing is carried out simultaneously with the provision of a wiring metallization. 
   According to a further preferred development, the metallizing is carried out by an at least partly conductive adhesive being applied to the mechanical supporting structure. 
   According to a further preferred development, the metallizing is carried out by a mechanical supporting structure consisting of a non-cured polymer being scattered with metal powder in the surface region and the polymer subsequently being cured. 
   According to a further preferred development, the terminal region has solder balls which are applied to a wiring metallization. 
   According to a further preferred development, the terminal region has elastic elevations, to which a wiring metallization is applied. 
   According to a further preferred development, the mechanical supporting structure consists of a preferably non-conductive polymer. 
   According to a further preferred development, the first soldering region and/or second soldering region have metallic contact areas, which are covered with solder paste. 
   According to a further preferred development, the steps before the soldering are carried out at wafer level, separation into individual chips then taking place and the soldering finally being carried out at chip level. 
   Exemplary embodiments of the invention are explained in more detail in the description which follows and are represented in the drawings, in which: 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1   a-e  show schematic representations of a method of connecting an integrated circuit to a substrate according to a first embodiment of the present invention; 
       FIGS. 2   a-d  show schematic representations of a method of connecting an integrated circuit to a substrate according to a second embodiment of the present invention; and 
       FIGS. 3   a-e  show schematic representations of a method of connecting an integrated circuit to a substrate according to a third embodiment of the present invention. 
   

   IN THE FIGURES, THE SAME REFERENCES DESIGNATE THE SAME OR FUNCTIONALLY THE SAME COMPONENTS. 
   DETAILED DESCRIPTION 
   Although only one chip is respectively illustrated in the case of the examples which follow, it should be expressly mentioned that the application of the mechanical supporting structure and the soldering can preferably also be carried out at a higher level, for example wafer level. 
     FIGS. 1   a-e  are schematic representations of a method of connecting an integrated circuit to a substrate according to a first embodiment of the present invention. 
   In  FIG. 1   a , reference  1  designates a chip with an integrated circuit, which is not illustrated in any more detail and has a main area HF 1 , on which an electrical contacting region  2  is provided for the external contacting of the integrated circuit. 
   In a first step of the method according to the first embodiment, a mechanical supporting structure  3   a ,  3   b  in the form of individual raised supporting regions  3   a ,  3   b , provided at the chip periphery, is applied to the first main area HF 1  of the chip  1 . Although in the case of the present invention the mechanical supporting structure comprises individual discrete supports, it goes without saying that it is also possible to provide a supporting structure which is, for example, closed in an annular form or partly closed. 
   In the case of this embodiment, the mechanical supporting structure  3   a ,  3   b  consists of a hard, unelastic epoxy resin, but could under certain circumstances also comprise an elastic epoxy resin. The application of the mechanical supporting structure  3   a ,  3   b  is performed by a customary method, such as for example a printing method or a dispersing method. 
   With reference to  FIG. 1   b , in a subsequent process step, a wiring metallization  5 , which is electrically connected to the electrical contacting region  2 , is provided on the first main area HF 1  of the chip  1 . In particular, in the portions  5   a ,  5   b  the wiring metallization extends also onto the upper side of the mechanical supporting structure  3   a ,  3   b . In this connection, it should already be mentioned now that the surface of the mechanical supporting structure  3   a ,  3   b  must be solderable for the later step of mounting the chip  1  onto the substrate. As will be shown later, it is also possible to apply the metallization of the upper side of the mechanical supporting structure  3   a ,  3   b  in a separate process step, but application together with the wiring metallization  5  is easiest. 
   In the following example, the application of the wiring metallization is performed according to a standard method, such as for example a sputtering method or a plating method, in that titanium and/or copper or nickel and/or gold is deposited, with either a mask being provided in advance or an etching mask and subsequent etching being provided in a later step. 
   With reference to  FIG. 1   c , solder balls  10 , by means of which the electrical connection of the integrated circuit to the substrate is later to be accomplished, are then applied to predetermined regions of the wiring metallization  5  in a known way, for example by solder beam printing [sic]. 
   At the latest after this process step, if the previous process steps were carried out at wafer level, the wafer is divided up into individual chips. 
   According to  FIG. 1   d , a substrate  20  is then provided, with a main area HF 2 , on which the terminal regions  22 ,  22 ′ are provided and solder paste  23 ,  23 ′ is provided on top. In this case, the terminal regions  22  serve for the electrical connection to the solder balls  10 , whereas the terminal regions  22 ′ serve merely for the mechanical connection of the mechanical supporting structure  3   a ,  3   b . In the process step which then follows, the chip  1  is then aligned with respect to the substrate  20  and placed on it in such a way that the solder balls  10  contact the terminal regions  22  with the solder paste  23  and the surface metallization  5   a ,  5   b  of the mechanical supporting structure  3   a ,  3   b  contacts the terminal regions  22 ′ with the solder paste  23 ′ located on it. In a process step which then follows, the structure formed in this way, made up of the substrate  20  and the chip  1  placed on it, is put into a soldering furnace and securely soldered by reflow soldering. 
   As represented in  FIG. 1   e , provided in the securely soldered structure along with the soldered connections by means of the solder balls  10  are mechanical stabilizing regions  50   a ,  50   b , in which the chip  1  is securely connected to the terminal regions  22 ′ of the substrate by means of the mechanical supporting structure  3   a ,  3   b , the surface metallization regions  5   a ,  5   b , the solder paste  23 ′ [sic]. These additional mechanical supporting regions  50   a ,  50   b  lead to a reduced sensitivity with respect to shearing stresses in the x and y directions (that is in the plane of the main areas) and with respect to tensile and compressive forces in the z direction (that is perpendicular to the main areas HF 1 , HF 2 ). 
     FIGS. 2   a-d  are schematic representations of a method of connecting an integrated circuit to a substrate according to a second embodiment of the present invention. 
   In the case of the second embodiment, according to  FIG. 2   a , firstly an arrangement of elastic elevations  30  is provided on the main area HF 1  of the chip  1  and the wiring metallization  5  is brought onto these elevations according to the method described in connection with the first exemplary embodiment. The elastic elevations  30  expediently consist of a polymer with the desired elasticity. 
   In a process step which then follows and is illustrated in  FIG. 2   b , a mechanical supporting structure  33   a ,  33   b ,  33   c  in the form of discrete supports is then provided on the main area HF 1  of the chip  1 . As in the case of the first exemplary embodiment, these supporting regions consist of a polymer of suitable hardness or elasticity, which is applied to the main area HF 1 , for example by means of a printing technique. As a difference from the first embodiment, in the case of this second embodiment a central mechanical supporting region  33   b  is also provided in addition to the peripheral supporting regions  33   a ,  33   c . An anisotropically conducting (partly conducting) solderable adhesive  35   a ,  35   b ,  35   c  is then applied to the mechanical supporting structure  33   a ,  33   b ,  33   c  by an application method known per se. 
   With further reference to  FIG. 2   c , the provision of the substrate  20  is performed, on the main area HF 1  of which the terminal regions  22  with the solder paste  23  are provided for the electrical connection to the wiring metallization and the terminal regions  22 ′,  22 ″ with the solder paste  23 ′,  23 ″ are provided for the mechanical connection to the supporting structure  33   a ,  33   b ,  33   c  by means of the solderable surface regions  35   a ,  35   b ,  35   c.    
   With reference to  FIG. 2   d , as in the case of the first exemplary embodiment, the chip  1  is then aligned with respect to the substrate  20  and correspondingly placed on it, so that the respective soldering regions lie one on top of the other. As already described above, the reflow soldering is finally performed to create a solid connection between the chip  1  and the substrate  20 . 
     FIGS. 3   a-e  are schematic representations of a method of connecting an integrated circuit to a substrate according to a third embodiment of the present invention. 
   In the case of the third embodiment, according to  FIG. 3   a , firstly an isotropically conducting adhesive  40  is applied in the form of elevations  40  to the main area HF 1  of the chip  1 . This takes place, for example, by means of a customary printing method. 
   According to  FIG. 3   b , the depositing and structuring of the wiring metallization  5  is then performed in such a way that cap-shaped surface regions of the elevations  40  are covered by it. 
   In a process step which then follows, according to  FIG. 3   c , mechanical supporting regions  43   a ,  43   b ,  43   c  which consist of a non-conducting adhesive are then provided, as in the case of the second embodiment, in the periphery and the center of the chip  1 , and are left in the non-cured state. 
   According to  FIG. 3   d , the chip  1  or the wafer with the chips  3  is then immersed in a metal powder (for example copper, silver, nickel, lead/tin, . . . ), so that metal powder particles  60   a ,  60   b ,  60   c  remain adhering on the surface of the mechanical supporting structure  43   a ,  43   b ,  43   c  and consequently form solderable regions on the surface of the mechanical supporting structure  43   a ,  43   b ,  43   c.    
   In the process step which then follows, curing of the adhesive of which the mechanical supporting structure  43   a ,  43   b ,  43   c  consists is then performed, so that the metal particle regions  60   a ,  60   b ,  60   c  are fixed. 
   In the process step which then follows and is illustrated in  FIG. 3   e , the aligning of the chip  1  and the correspondingly prepared substrate  20  is then in turn performed, as in the case of the second embodiment explained above, and the reflow soldering is performed, in order to provide a solid connection between the chip  1  and the substrate  20  by means of the soldering regions. 
   Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted to these, but instead can be modified in various ways. 
   The present invention can consequently be applied in particular also to wafer level packages (WLP) or ball-grid-array packages (BGA) or else to hybrids, wafers or other integrated circuits. 
   
     
       
             
           
             
             
           
         
             
                 
             
             
               List of references 
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               1 
               chip 
             
             
               HF1 
               main area 
             
             
               2 
               contacting region 
             
             
               3a, 3b; 33a, 33b, 33c; 
               mechanical supporting structure 
             
             
               43a, 43b, 43c 
             
             
               5a, 5b 
               surface metallization 
             
             
               20 
               substrate 
             
             
               HF2 
               main area 
             
             
               50a, 50b 
               mechanical supporting regions 
             
             
               22, 22′, 22″ 
               terminal regions of 20 
             
             
               23, 23′, 23″ 
               solder paste 
             
             
               10 
               solder balls 
             
             
               30 
               elastic elevations 
             
             
               5 
               wiring metallization 
             
             
               35a, 35b, 35c 
               surface metallization 
             
             
               40 
               isotropically conducting adhesive 
             
             
               50 
               cap region of 5 on 40 
             
             
               60a, 60b, 60c 
               metal powder particles