Abstract:
The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a flash non-volatile memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage and optimize performance. 
       BACKGROUND OF THE INVENTION 
       [0002]    A prior art non-volatile memory cell  110  is shown in  FIG. 1 . The memory cell  110  comprises a semiconductor substrate  112  of a first conductivity type, such as P type. The substrate  112  has a surface on which there is formed a first region  114  (also known as the source line SL) of a second conductivity type, such as N type. A second region  116  (also known as the drain line) also of N type is formed on the surface of the substrate  112 . Between the first region  114  and the second region  116  is a channel region  118 . A bit line BL  120  is connected to the second region  116 . A word line WL  122  is positioned above a first portion of the channel region  118  and is insulated therefrom. The word line  122  has little or no overlap with the second region  116 . A floating gate FG  124  is over another portion of the channel region  118 . The floating gate  124  is insulated therefrom, and is adjacent to the word line  122 . The floating gate  124  is also adjacent to the first region  114 . The floating gate  124  may overlap the first region  114  to provide coupling from the region  114  into the floating gate  124 . A coupling gate CG (also known as control gate)  126  is over the floating gate  124  and is insulated therefrom. An erase gate EG  128  is over the first region  114  and is adjacent to the floating gate  124  and the coupling gate  126  and is insulated therefrom. The top corner of the floating gate  124  may point toward the inside corner of the T-shaped erase gate  128  to enhance erase efficiency. The erase gate  128  is also insulated from the first region  114 . The cell  110  is more particularly described in U.S. Pat. No. 7,868,175 whose disclosure is incorporated herein by reference in its entirety. 
         [0003]    One exemplary operation for erase and program of prior art non-volatile memory cell  110  is as follows. The cell  110  is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate  128  with other terminals equal to zero volt. Electrons tunnel from the floating gate  124  into the erase gate  128  causing the floating gate  124  to be positively charged, turning on the cell  110  in a read condition. The resulting cell erased state is known as ‘1’ state. The cell  110  is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate  126 , a high voltage on the source line  114 , a medium voltage on the erase gate  128 , and a programming current on the bit line  120 . A portion of electrons flowing across the gap between the word line  122  and the floating gate  124  acquire enough energy to inject into the floating gate  124  causing the floating gate  124  to be negatively charged, turning off the cell  110  in read condition. The resulting cell programmed state is known as ‘0’ state. 
         [0004]    Exemplary voltages that can be used for the read, program, and erase operations in memory cell  110  is shown below in Table 1: 
         [0000]    
       
         
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG- 
                   
                   
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 unsel 
               
               
                 Oper- 
                   
                   
                   
                   
                   
                 same 
                 CG- 
                   
                 EG- 
               
               
                 ation 
                 WL 
                 WL-unsel 
                 BL 
                 BL-unsel 
                 CG 
                 sector 
                 unsel 
                 EG 
                 unsel 
                 SL 
                 SL-unsel 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Read 
                 1.0-2 V        
                 0 V 
                 0.6-2 V        
                 0 
                 V/FLT 
                 0-2.6 V 
                 0-2.6 V 
                 0-2.6 V 
                 0-2.6 V 
                 0-2.6 V 
                 0 V 
                 0 
                 V/FLT 
               
               
                 Erase 
                 0 V 
                 0 V 
                 0 V 
                 0 
                 V 
                       0 V 
                 0-2.6 V 
                 0-2.6 V 
                 11.5-12 V  
                 0-2.6 V 
                 0 V 
                 0 
                 V 
               
             
          
           
               
                 Pro- 
                 1 V 
                 0 V 
                  1 uA 
                 Vinh 
                 10-11 V  
                     0-5 V 
                 0-2.6 V 
                 4.5-8 V 
                 0-2.6 V 
                 4.5-5 V        
                 0-1 
                 V/FLT 
               
               
                 gram 
               
               
                   
               
               
                 Note: 
               
               
                 “FLT” means floating 
               
             
          
         
       
     
         [0005]    For programming operation, the EG voltage can be applied much higher, e.g. 8V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 6V, to reduce unwanted erase effect of the adjacent memory cells sharing the same EG gate of the selected memory cells. 
         [0006]    Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell  310  is shown below in Table 2: 
         [0000]    
       
         
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG- 
                   
                   
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 unsel 
               
               
                 Oper- 
                   
                   
                   
                   
                   
                 same 
                 CG- 
                   
                 EG- 
               
               
                 ation 
                 WL 
                 WL-unsel 
                 BL 
                 BL-unsel 
                 CG 
                 sector 
                 unsel 
                 EG 
                 unsel 
                 SL 
                 SL-unsel 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Read 
                 1.0-2 V        
                 −0.5 V/ 
                 0.6-2 V        
                 0 
                 V/FLT 
                 0-2.6 V 
                 0-2.6 V 
                 0-2.6 V 
                 0-2.6 V 
                 0-2.6 V 
                 0 V 
                 0 
                 V/FLT 
               
               
                   
                   
                 0 V 
               
               
                 Erase 
                 0 V 
                 0 V 
                 0 V 
                 0 
                 V 
                       0 V 
                 0 V-2.6 V  
                 0-2.6 V 
                 11.5-12 V  
                 0-2.6 V 
                 0 V 
                 0 
                 V 
               
             
          
           
               
                 Pro- 
                 1 V 
                 −0.5 V/ 
                  1 uA 
                 Vinh 
                 10-11 V  
                 0-2.6 V 
                 0-2.6 V 
                 4.5-5 V 
                 0-2.6 V 
                 4.5-5 V        
                 0-1 
                 V/FLT 
               
               
                 gram 
                   
                 0 V 
               
               
                   
               
             
          
         
       
     
         [0007]    Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell  310  is shown below in Table 3: 
         [0000]    
       
         
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG- 
                   
                   
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 unsel 
               
               
                 Oper- 
                   
                   
                   
                   
                   
                 same 
                 CG- 
                   
                 EG- 
               
               
                 ation 
                 WL 
                 WL-unsel 
                 BL 
                 BL-unsel 
                 CG 
                 sector 
                 unsel 
                 EG 
                 unsel 
                 SL 
                 SL-unsel 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Read 
                 1.0-2 V        
                 −0.5 V/0 V 
                 0.6-2 V        
                 0 
                 V/FLT 
                 0-2.6 V 
                 0-2.6 V 
                 0-2.6 V 
                 0-2.6 V     
                 0-2.6 V 
                 0 V 
                 0 
                 V/FLT 
               
               
                 Erase 
                 0 V 
                 −0.5 V/0 V 
                 0 V 
                 0 
                 V 
                 −(5-9) V  
                 0-2.6 V 
                 0-2.6 V 
                 9-8 V 
                 0-2.6 V 
                 0 V 
                 0 
                 V 
               
             
          
           
               
                 Pro- 
                 1 V 
                 −0.5 V/0 V 
                  1 uA 
                 Vinh 
                     8-9 V 
                     0-5 V 
                 0-2.6 V 
                 8-9 V 
                 0-2.6 V 
                 4.5-5 V        
                 0-1 
                 V-FLT 
               
               
                 gram 
               
               
                   
               
             
          
         
       
     
         [0008]    For programming operation, the EG voltage is applied much higher, e.g. 8-9V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 5V, to reduce unwanted erase effects of the adjacent memory cells sharing the same EG gate of the selected memory cells. 
         [0009]    Also known in the prior art are fully depleted silicon-on-insulator (“FDSOI”) transistor designs as shown in  FIGS. 2-4 . The FDSOI advantages includes a back gate (with buried oxide as a gate oxide) to modulate the threshold voltage (forward body bias or reverse body bias), an ultrathin un-doped channel that gives higher mobility and no random doping fluctuation. It has a ground plane on the back gate to adjust implant to adjust the threshold voltage. It also has a channel that is fully depleted to give better electrostatic control, lower drain-induced-barrier-lowering DIBL and short channel effect. It has minimum source and drain junction. Metal gate and channel length are also used to adjust threshold voltage. 
         [0010]      FIG. 2  depicts FDSOI CMOS circuit cross section  210 . FDSOI CMOS circuit  210  comprises silicon substrate  211 , silicon insulators  216 , FDSOI NMOS transistor  230 , and FDSOI PMOS transistor  240 . 
         [0011]    FDSOI NMOS transistor  230  comprises gate  218 , and source and drain  217 . FDSOI NMOS transistor  230  further comprises p-well  212 , buried oxide layer  213  (which is an insulator), and channel  215 . Channel  215  is an undoped, fully depleted channel. During operation, buried oxide layer  213  minimizes any leakage out of channel  214 . FDSOI NMOS transistor  230  further comprises p-well back gate terminal  219 , which can be used to add a bias to p-well  212  such as to adjust the threshold voltage Vt of the NMOS  230 . 
         [0012]    FDSOI PMOS transistor  240  comprises gate  228 , and source and drain  227 . FDSOI PMOS transistor  240  further comprises n-well  222 , buried oxide layer  223  (which is an insulator), and channel  225 . Channel  225  is an undoped, fully depleted channel. During operation, buried oxide layer  223  minimizes any leakage out of channel  225 . FDSOI PMOS transistor  240  further comprises n-well back gate terminal  229 , which can be used to add a bias to n-well  222  such as to adjust the threshold voltage Vt of the PMOS  240 . 
         [0013]      FIG. 3  depicts FDSOI CMOS circuit cross section  310 . FDSOI CMOS  310  circuit comprises silicon substrate  311 , silicon insulators  316 , FDSOI NMOS transistor  330 , and FDSOI PMOS transistor  340 . 
         [0014]    FDSOI NMOS transistor  330  comprises gate  318 , and source and drain  317 . FDSOI NMOS transistor  330  further comprises n-well  312 , buried oxide layer  313  (which is an insulator), and channel  315 . Channel  315  is an undoped, fully depleted channel. During operation, buried oxide layer  313  minimizes any leakage out of channel  315 . FDSOI NMOS transistor  330  further comprises n-well back gate terminal  319 , which can be used to add a bias to n-well  312  such as to adjust the threshold voltage Vt of the NMOS  330 . 
         [0015]    FDSOI PMOS transistor  340  comprises gate  328 , and source and drain  327 . FDSOI PMOS transistor  340  further comprises p-well  312 , buried oxide layer  323  (which is an insulator), and channel  325 . Channel  325  is an undoped, fully depleted channel. During operation, buried oxide layer  323  minimizes any leakage out of channel  325 . FDSOI PMOS transistor  340  further comprises p-well back gate terminal  329 , which can be used to add a bias to p-well  322  such as to adjust the threshold voltage Vt of the PMOS  340 . 
         [0016]      FIG. 4  depicts FDSOI and bulk CMOS hybrid MOS circuit cross section  410 . Bulk CMOS refers to standard PMOS and NMOS transistor on bulk silicon. Hybrid MOS circuit  410  comprises silicon substrate  411 , silicon insulators  416 , FDSOI NMOS transistor  430  and NMOS transistor  440 . NMOS transistor  440  is a traditional NMOS transistor and not an FDSOI NMOS transistor. 
         [0017]    FDSOI NMOS transistor  430  comprises gate  418 , and source and drain  417 . FDSOI NMOS transistor  430  further comprises p-well  412 , buried oxide layer  413  (which is an insulator), and channel  415 . Channel  415  is an undoped, fully depleted channel. During operation, buried oxide layer  413  minimizes any leakage out of channel  415 . FDSOI NMOS transistor  430  further comprises p-well back gate terminal  419 , which can be used to add a bias to p-well  412  such as to adjust the threshold voltage Vt of the NMOS  430 . 
         [0018]    NMOS transistor  440  comprises gate  428 , and source and drain  427 . NMOS transistor  440  further comprises p-well bulk  422  and doped channel  423 . NMOS transistor  440  further comprises p-well bulk terminal  429 , which can be used to add a bias to p-well bulk  422 . 
         [0019]    To date, fully depleted silicon-on-insulator transistor designs have not been used in flash memory systems. What is needed is a flash memory system that utilizes fully depleted silicon-on-insulator transistor designs. What is further needed is a partitioned flash memory chip that comprises a bulk region and an FDSOI region to maximize area and minimize leakage. 
       SUMMARY OF THE INVENTION 
       [0020]    In the embodiments described below, flash memory devices utilize a partition comprising bulk transistors and a partition comprises FDSOI transistors. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  is a cross-sectional view of a non-volatile memory cell of the prior art. 
           [0022]      FIG. 2  is a cross-sectional view of a FDSOI CMOS circuit of the prior art. 
           [0023]      FIG. 3  is a cross-sectional view of a FDSOI CMOS circuit of the prior art. 
           [0024]      FIG. 4  is a cross-sectional view of a FDSOI CMOS circuit of the prior art. 
           [0025]      FIG. 5  depict various types of FDSOI NMOS and PMOS transistors used in the embodiments. 
           [0026]      FIG. 6  depicts a die used in the embodiments. 
           [0027]      FIG. 7  depicts basic components of an array used in the embodiments. 
           [0028]      FIG. 8  depicts a decoder to generate different voltages for use by the embodiments. 
           [0029]      FIG. 9  depicts an embodiment of a row decoder. 
           [0030]      FIG. 10  depicts another embodiment of a row decoder. 
           [0031]      FIG. 11  depicts another embodiment of a row decoder. 
           [0032]      FIG. 12  depicts another embodiment of a row decoder. 
           [0033]      FIG. 13  depicts an embodiment of an erase gate decoder. 
           [0034]      FIG. 14  depicts an embodiment of a source line decoder. 
           [0035]      FIG. 15  depicts an embodiment of a high voltage logic selector circuit. 
           [0036]      FIG. 16  depicts an embodiment of a coupling gate decoder. 
           [0037]      FIG. 17  depicts an embodiment of a low logic voltage circuit. 
           [0038]      FIG. 18  depicts a sensing system which can be used for the embodiments. 
           [0039]      FIG. 19  depicts an embodiment of a sensing amplifier. 
           [0040]      FIG. 20  depicts another embodiment of a sensing amplifier. 
           [0041]      FIG. 21  depicts another embodiment of a sensing amplifier. 
           [0042]      FIG. 22  depicts another embodiment of a sensing amplifier. 
           [0043]      FIG. 23  depicts an embodiment of a column decoder. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0044]      FIG. 5  depicts eight FDSOI transistor types that are used in the embodiments described herein. 
         [0045]    Standard fixed bias FDSOI MOS transistors includes PMOS transistor  510  and NMOS transistor  550 . FDSOI PMOS transistor  510  comprises an n-well that is biased to Vdd power supply and optionally to ground, in this case transistor channel length is modified to have similar threshold voltage level. FDSOI NMOS transistor  550  comprises a p-well that is biased to ground. The PMOS  510  and NMOS  550  are regular threshold voltage devices. 
         [0046]    Flipped well fixed bias FDSOI MOS transistors includes PMOS transistor  520  and NMOS transistor  560 . FDSOI PMOS transistor  520  comprises a p-well that is biased to ground. FDSOI NMOS transistor  560  comprises an n-well that is biased to ground. The PMOS  520  and NMOS  560  are low threshold voltage devices, i.e., its threshold voltage is lower than that of the PMOS  510  and NMOS  550 . 
         [0047]    Standard dynamic bias FDSOI MOS transistors includes PMOS transistor  530  and NMOS transistor  570 . FDSOI PMOS transistor  530  comprises an n-well that is biased to a dynamic voltage source Vb_PRW. FDSOI NMOS transistor  570  comprises a p-well that is biased to a dynamic voltage source Vb_NRW. The dynamic voltage source is used to forward body (well) bias FBB or reverse body bias RBB to optimize performance. For the PMOS  530  dynamic voltage source Vb_PRW varies to positive voltage (e.g., up to 3V) for RBB and varies to negative voltage (e.g., up to −0.5V) for FBB. For the NMOS  570  dynamic voltage source Vb_NRW varies to positive voltage (e.g., 0V to 3V) for FBB and varies to negative voltage (e.g., 0V to −3V) for RBB. A deep nwell is needed to isolate the pwell from p substrate to allow pwell to be biased at a high level, e.g. 3V or −3V. 
         [0048]    Flipped well dynamic bias FDSOI MOS transistors includes PMOS transistor  540  and NMOS transistor  580 . FDSOI PMOS transistor  540  comprises a p-well that is biased to a dynamic voltage source Vb_PLW. FDSOI NMOS transistor  580  comprises an n-well that is biased to a dynamic voltage source Vb_NLW. For the PMOS  540  dynamic voltage source Vb_PLW varies to positive voltage (e.g., 0V to 3V) for RBB and varies to negative voltage (e.g., 0V to −3V) for FBB. For the NMOS  580  dynamic voltage source Vb_NLW varies to positive voltage (e.g., 0V to 3V) for FBB and varies to negative voltage (e.g., 0V to −0.5V) for RBB. A deep nwell is needed to isolate the pwell from p substrate to allow pwell to be biased at a high level, e.g. 3V or −3V. 
         [0049]    In the embodiments that follow, one or more the eight types of FDSOI transistors shown in  FIG. 5  are used in a flash memory system. 
         [0050]      FIG. 6  depicts an embodiment of an architecture for a flash memory system comprising die  600 . Die  600  comprises: flash memory arrays  601  comprising rows and columns of memory cells of the type described previously as memory cell  110  in  FIG. 1 ; row decoder circuits  602  used to access the rows in flash memory arrays  601  to be read from or written to; column decoder circuits  603  used to access bytes in flash memory arrays  601  to be read from or written to; sensing circuits  604  used to read data from flash memory arrays  601 ; high voltage (HV) decoder  620  consisting of HV decoding block  610  and HV passing blocks  609  and  611  for delivering voltages and biases needed for non-volatile operation for the flash memory arrays  601 ; control logic  605  for providing various control functions, such as redundancy and built-in self-testing; analog circuit  606 ; bulk bias control  607  for controlling the voltage of the bulk (well) regions of transistors; high voltage charge pump circuit  608  used to provide increased voltages for program and erase operations for flash memory arrays  601 . The chip partition for the blocks for FDSOI vs. Bulk CMOS region to achieve optimal performance is as following.
       Row decoder  602 : Standard Vt, Flipped Well Vt, Dynamic Vt FDSOI   Column decoder  603 : Standard Vt, Flipped Well Vt, Dynamic Vt FDSOI   Sensing circuits  604 : Standard Vt, Flipped Well Vt, Dynamic Vt FDSOI   Control logic  605 : Standard Vt, Flipped Well Vt FDSOI   Analog circuit  606 : Standard Vt, Flipped Well Vt, Dynamic Vt FDSOI   Bulk bias control circuit  607 : Standard Vt, Flipped Well Vt, Dynamic Vt FDSOI   HV chargepump circuit  608 : Bulk CMOS and FDSOI hybrid, FDSOI region includes Standard Vt, Flipped Well Vt, Dynamic Vt FDSOIHV decoder circuit  620 : Bulk CMOS and FDSOI hybrid, FDSOI region includes Standard Vt, Flipped Well Vt, Dynamic Vt FDSOI       
 
         [0058]    An embodiment of array  601  is shown in  FIG. 7 . Array  601  comprises a first plurality of subarrays  701  and a second plurality of subarrays  702 . Here, the first plurality of subarrays  701  has a bias voltage applied to its p-well and n-well areas (to achieve higher performance), and the second plurality of subarrays  702  does not have a bias voltage applied to its p-well and n-well areas (to achieve less leakage). Array  601  further comprises row decoder  703 , high voltage subarray source  704 , and high voltage decoder  705 . 
         [0059]      FIG. 8  depicts decoder  800  for generating bias control voltages P 1 _PW, P 2 _PW, N 1 _NW, and N 2 _NW, which are used in the embodiments that follow. Decoder  800  comprises NAND gate  801 , inverter  802 , and programmable voltage sources  803 ,  804 ,  805 , and  806 , as shown. 
         [0060]      FIG. 9  depicts row decoder  900 . Row decoder  900  comprises NAND gate  951 , inverter  952 , as well as PMOS transistors  953 ,  954 ,  956 ,  958 ,  959 , and  961  and NMOS transistors  955 ,  957 ,  960 , and  962  as shown. The NAND gate  951  and inverter  952  serves as row address decoder to decoding address signal XPA-D for row address decoding. The PMOS  956  and NMOS  957  serves as row driver with strong strength to drive pre-determined signal ZVDD into wordlines WLO-7 of memory cell. The PMOS  954 , PMOS  953 , and NMOS  955  serves dual functions, as a row pre-driver and decoding address signals XPZBO-7. 
         [0061]    NAND gate  951  comprises transistors of type FDSOI PMOS  520  with the p-well biased to P 2 _PW and transistors of type FDSOI NMOS  560  with the n-well biased to N 2 _NW. 
         [0062]    Inverter  952  comprises transistors of type FDSOI PMOS  520  with the p-well biased to P 1 _PW and transistors of type FDSOI NMOS  560  with the n-well biased to N 1 _NW. 
         [0063]    PMOS transistors  953 ,  954 ,  958 , and  959  are transistors of type FDSOI PMOS  520  with the p-well biased to P 2 _PW. PMOS transistors  956  and  961  are transistors of type FDSOI PMOS  520  with the p-well biased to P 1 _PW. 
         [0064]    NMOS transistors  955  and  960  are transistors of type FDSOI NMOS  560  with the n-well biased to N 2 _NW. NMOS transistors  957  and  962  are transistors of type FDSOI NMOS  560  with the n-well biased to N 1 _NW. The well bias levels for P 1 _PW/P 2 _PW/N 1 _NW/N 2 _NW are such that using forward bias FBB for speed performance and reverse bias RBB to reduce leakage. 
         [0065]      FIG. 10  depicts row decoder  1000 . Row decoder  1000  is structurally identical to row decoder  900 , except that all of the transistors are of type FDSOI PMOS  520 , with the p-well biased to P 1 _PW. The well bias levels for P 1 _PW is such that using forward bias FBB for speed performance and reverse bias RBB to reduce leakage 
         [0066]      FIG. 11  depicts row decoder  1100 . Row decoder  1100  is structurally identical to row decoder  900 , except that all of the transistors are of type FDSOI NMOS  560 , with the n-well biased to P 1 _NW. The well bias levels for P 1 _NW is such that using forward bias FBB for speed performance and reverse bias RBB to reduce leakage 
         [0067]      FIG. 12  depicts row decoder  1200 . Row decoder  1200  is structurally identical to row decoder  900 , except that: NAND gate  951  comprises transistors of type FDSOI NMOS  550  with the p-well biased to P 2 _PW; inverter  952  comprises transistors of type FDSOI NMOS  560  with the n-well biased to P 1 _NW; PMOS transistors  953 ,  956 ,  958 , and  961  are transistors of type FDSOI PMOS  510  with the p-well biased to P 1 _NW; PMOS transistors  954  and  959  are transistors of type FDSOI PMOS  520  with the p-well biased to P 2 _PW; NMOS transistors  955  and  960  are transistors of type FDSOI NMOS  510 , with the n-well biased to P 2 _PW; and NMOS transistors  957  and  962  are transistors of type FDSOI NMOS  560  of with the n-well biased to P 1 _NW. The well bias levels for P 2 _PW/P 1 _NW are such that using forward bias FBB for speed performance and reverse bias RBB to reduce leakage 
         [0068]      FIG. 13  depicts erase gate decoder  1300 . No FDSOI transistors are used in erase gate decoder  1300  in this example but of bulk CMOS types. HV PMOS  1301  to control current from HV supply VEGSUP, HV PMOS  1302  is used as address decoding. HV NMOS  1303  is used as pull down device to pull EG  1305  to a low level or as a passing transistor to pass bias level EG_LOW_BIAS  1304  into the EG terminal. 
         [0069]      FIG. 14  depicts source line decoder  1400 . No FDSOI transistors are used in source line decoder  1400  in this example but of bulk CMOS types. NMOS  1401  is used to pass SL supply VSLSUP, NMOS  1402  is used to measure (monitor) voltage on SL  1405 , NMOS  1403  is used to pass a low bias level SLRD_LOW_BIAS in read or standby, NMOS  1404  is used to pass a low bias level SLP_LOW_BIAS in program. 
         [0070]      FIG. 15  depicts high voltage circuit selector  1500  that once it is enabled will output positive high voltage level on ENHV and/or negative high voltage level on ENHVNEG. No FDSOI transistors are used in high voltage logic selector  1500  in this example. 
         [0071]      FIG. 16  depicts coupling gate decoder  1600 . No FDSOI transistors are used in coupling gate decoder  1600   1400  in this example but of bulk CMOS types. HV PMOS  1401  is used to pass CG supply, HV PMOS  1402  is as address decoding, PMOS  1403  is used to control current from CG read supply VCGRSUP, HV PMOS  1404  is used to pass CG read supply. PMOS  1405  is used to isolate negative voltage level. NMOS  1407  is used as address decoding, NMOS  1408  and  1409  are used as for negative voltage isolation, NMOS  1410  is used to pass a bias level CG_LOW_BIAS into CG  1406 . NMOS  1411  is used to pass negative voltage supply VHVNEG, NMOS  1412  is used as negative cascoding. 
         [0072]      FIG. 17  depicts low voltage sector enabling latch logic  1700 . Low voltage logic  1700  comprises latched inverters  1701  and  1702  and NMOS transistors  1703  (wordline enabling),  1704  (sector enabling), and  1705  (used for resetting the latched  1701 / 1702 ), all of which are constructed from transistors of type that utilize a p-well. Alternatively inverter  1701  can be constructed from transistors that utilize n-well. 
         [0073]      FIG. 18  depicts sensing system  1800 , similar to blocks  601 / 602 / 603 / 604  of die  600  of  FIG. 6 . Sensing system  1800  comprises sensing amplifiers  1801 ,  1802 ,  1803 , and  1804 . Embodiments of sensing amplifiers  1801 ,  1802 ,  1803 , and  1804  are shown in  FIGS. 19-22 . A reference sector  1810  is used to generate reference bias from reference memory cell for the sensing. The two inputs of a sense amplifier couples to two bitlines of two array planes, for example the sense amplifier  1801  couples to top array plane  1820  and bottom array plane  1821 . One of array plane provides a selected bitline (hence a selected memory cell through one wordline enabled) and the other array plane provides an un-selected bitline (all wordlines are disabled for this array plane) for sensing for symmetrical bitline sensing. 
         [0074]      FIG. 19  depicts sensing amplifier  1900 . Sensing amplifier  1900  comprises PMOS transistors  1901 ,  1906 ,  1907 , and  1903  (of type FDSOI PMOS  520 , with p-well coupled to ground), PMOS transistors  1905 ,  1908 ,  1909 , and  1912  (of type FDSOI PMOS  510  with n-well coupled to V bias ), NMOS transistors  1902 ,  1904 ,  1910 ,  1911 ,  1913 , and  1914  (of type FDSOI NMOS  560 , with n-well coupled to ground), and NMOS transistor  1915  (of type FDSOI NMOS  550 , with p-well coupled to ground). The PMOS  1901  and NMOS  1902  (and PMOS  1903  and NMOS  1904 ) is first (read-out) stage of the sensing amplifier. The PMOS  1901  is mirrored from a reference current Tref (such as from a reference cell in the reference sector  1810  in sensing system  1800  or a resistor). The NMOS  1902  couples to a cell current Icell through the bitline of the selected memory cell. The drain of the NMOS  1902  is sensing out node  1999  which is equal to difference between Tref and Icell times output impedance at node  1999 , i.e., Vsensed=Ro*(Icell−Tref). The drain of the NMOS  1904  is a reference node  1998 . The PMOS  1903  is in a disabled state with a Ileakpmos (duplicating the off state leakage of the PMOS  1901 ), The NMOS  1904  couples to cell current leakage Icellleak through an unselected bitline (selected bitline with all wordlines disabled) of the memory cell. The drain of the NMOS  1904  is sensing out node  1999  which is equal to difference between Ileakpmos and Icellleak times output impedance at node  1998 , i.e., Vrefsen=Ro*(Icellleak−Ileakpmos). The sensing node  1999  and reference node  1998  are precharged at start of sensing to reference voltage level  1920  and  1921  respectively. The transistors  1905 - 1915  is second (comparison) stage of the sensing amplifier. It is a dynamic latched differential amplifier with transistor NMOS  1913  and  1914  as input pair with the sensing out node  1999  and the reference node  1998  as inputs. The transistors  1906 ,  1907 ,  1910 , and  1911  are latched inverters with outputs ON and OP as full voltage level (Vdd/gnd) sensing outputs after sensing the difference between the sensing out node  1999  and the reference node  1998 . The PMOS transistors  1905 ,  1908 ,  1909 ,  1912  are for precharging the nodes of the latched inverters to high supply level. The NMOS  1913  and  1914  are footed input pairs (meaning connecting in series to NMOS transistors of the latched inverters). The NMOS  1915  is enabling bias transistor for the input pairs. 
         [0075]      FIG. 20  depicts sensing amplifier  2000 . Sensing amplifier  2000  is structurally identical to sensing amplifier  1900 , except that the n-well of NMOS transistor  1913  is coupled to a variable voltage source, NL 5 _NWB, and the n-well of NMOS transistor  1914  is coupled to a variable voltage source, NL 5 _NWB. The variable voltage source is used to dynamically bias the well to optimize speed in active (forward body bias) and reduce leakage in standby (reverse body bias). It could also be used to nullify the threshold voltage offset of the sense amplifier. 
         [0076]      FIG. 21  depicts sensing amplifier  2100 . Sensing amplifier  2100  is structurally identical to sensing amplifier  1900 , except that the p-well of PMOS transistor  1901 ,  1903 ,  1906 , and  1907  are coupled to a variable voltage source, PL 1 _PW, and the n-well of NMOS transistor  1902 ,  1904 ,  1910 ,  1911 ,  1913 , and  1914  are coupled to a variable voltage source, NL 1 _NW. The variable voltage source is used to optimize speed in active (forward bias the well) and reduce leakage in standby (reverse bias the well) 
         [0077]      FIG. 22  depicts sensing amplifier  2200  with FDSOI and bulk CMOS hybrid region partition. Sensing amplifier  2200  is structurally identical to sensing amplifier  1900 , except that the p-well of PMOS transistor  1906  and  1907  are coupled to a variable voltage source, PL 1 _PW, and the n-well of NMOS transistor  1910  and  1912  are coupled to a variable voltage source, NL 1 _NW and PMOS transistor  2201  and  2202  and NMOS transistors  2202  and  2204  are bulk CMOS transistors. The PMOS  2201  and NMOS  2202  and PMOS  2203  and NMOS  2204  are bulk cmos read-out stage of the amplifier. This read-out stage couples to a high supply level (due to bulk cmos transistor), for example 1.8 v, instead of a logic supply level, for example Vdd1.2 v for wide sensing range. 
         [0078]      FIG. 23  depicts column decoder  2300 . Column decoder  2300  comprises NMOS transistors  2301 ,  2303 ,  2305 ,  2307 , and  2309  (of type FDSOI NMOS  560 , with n-well coupled to N 1 _NW) to enhance speed for column selection and NMOS transistors  2302 ,  2304 ,  2306 ,  2308 , and  2310  (of type FDSOI NMOS  550 , with p-well coupled to N 1 _PW) to reduce leakage for column de-selection.