Abstract:
A three photomask image transfer method. The method includes using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers spaced apart; removing the set of mandrels; using a second photomask, removing regions of the sidewall spacers forming trimmed sidewall spacers and defining a pattern of first features; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of integrated circuits; more specifically, it relates to a method for forming integrated circuit structures and particularly damascene wire structures. 
     BACKGROUND 
     As integrated circuit feature size has decreased a method of sidewall image transfer (SIT) patterning has been employed for advanced integrated circuit manufacture. However, when used to fabricate the electrical interconnects of the wiring levels, wires formed at one wiring level using SIT cannot be connected to wires formed by non-SIT patterning on the same level and another wiring level must be used to do so. This adds integrated circuit design restrictions which complicates, or in some cases excludes, certain circuit features from the integrated circuit design. Accordingly, there exists a need in the art to eliminate the deficiencies and limitations described hereinabove. 
     SUMMARY 
     A first aspect of the present invention is a method, comprising: using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers spaced apart; removing the set of mandrels; using a second photomask, removing regions of the sidewall spacers forming trimmed sidewall spacers and defining a pattern of first features; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer. 
     A second aspect of the present invention is a method comprising: using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacer loops on sidewalls of the mandrels; removing the set of mandrels; using a second photomask, trimming the sidewall spacer loops to form trimmed sidewall spacers; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer. 
     These and other aspects of the invention are described below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
         FIGS. 1 through 13  illustrate a method of forming a transfer pattern having SIT and non-SIT features interconnected according to embodiments of the present invention; 
         FIGS. 14 and 15  illustrate fabrication of damascene wires in a dielectric layer using the pattern of  FIG. 13  according to embodiments of the present invention; and 
         FIGS. 16 and 17  are top views of exemplary damascene wire structures that may be fabricated according to embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments of the present invention describe a three photomask process wherein all three masks are used on the same fabrication level (e.g., a wiring level of an integrated circuit which comprises damascene wires embedded in an interlevel dielectric (ILD) layer). The first photomask is used to define structures defined by mandrels and the spaces between mandrels before mandrel removal. The second photomask is used to trim the sidewall spacers after mandrel removal. The third photomask is used to interconnect the features defined by the first photomask. SIT patterning is defined as using sidewall spacers formed on the sidewalls of a mandrel to define the shape of a feature (e.g., an insulator between damascene wire). Non-SIT patterning is defined as using a structure (e.g., the mandrel itself) or spaces between sidewall spacers before mandrel removal to define the shape of a feature (e.g., a damascene wire). Thus, mandrel defined features and features defined by the space between sidewall spacers before mandrel removal are non-SIT features. The term “shape” refers to the outline of the feature in top view. Thus, some the shape of features will be defined by the sidewall spacers on the sidewalls of mandrels and some features will be defined by the mandrels themselves. 
       FIGS. 1 through 13  illustrate a method of forming a transfer pattern having SIT and non-SIT features interconnected according to embodiments of the present invention.  FIG. 1A  is a top view and  FIG. 1B  is a cross-section view through line  1 B- 1 B of  FIG. 1A . In  FIGS. 1A and 1B , formed on a semiconductor substrate  100  (which may be a bulk silicon substrate or a silicon on insulator (SOI) substrate and contain field effect transistors) is a dielectric layer  105 . Formed on a top surface of dielectric layer  105  is a first hardmask layer  110  and formed on a top surface of first hardmask layer  110  is a second hardmask layer  115 . Formed on a top surface of second hardmask layer  115  is a mandrel layer  120 . Formed on a top surface of mandrel layer  120  are a first patterned photomask layer  125  which includes a wide photoresist line  126  and a plurality of narrow photoresist lines  128  all having their respective longitudinal axes parallel. Narrow photoresist lines  128  are W1 wide and spaced apart a distance S1. Wide photoresist line  126  is W2 wide and spaced a distance S2 from the adjacent narrow photoresist line  128 . 
     In one example, S1 is between about 54 nm and about 90 nm. In one example, S2 is between about 54 nm and about 300 nm. In one example, S1=S2. In one example, W1 is between about 18 nm and about 60 nm. In one example, W2 is between about 54 nm and about 300 nm. 
     In one example, dielectric layer  105  is a low K (dielectric constant) material, examples of which include but are not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), SiLK™ (polyphenylene oligomer) manufactured by Dow Chemical, Midland, Tex., Black Diamond™ (methyl doped silica or SiO x (CH 3 ) y  or SiC x O y H y  or SiOCH) manufactured by Applied Materials, Santa Clara, Calif., organosilicate glass (SiCOH), and porous SiCOH. In one example, dielectric layer  105  is between about 300 nm and about 2,000 nm thick. A low K dielectric material has a relative permittivity of about 2.4 or less. In one example, dielectric layer  105  comprises materials independently selected from the group consisting of porous or nonporous silicon dioxide (SiO 2 ), fluorinated SiO 2  (FSG). In one example, first hardmask  110  comprises tetraethylorthosilicate (TEOS). In one example, second hardmask layer  115  comprises titanium nitride (TiN). 
     Patterned photoresist layer  125  is formed by a photolithographic process. A photolithographic process is one in which a photoresist layer is applied to a surface of a substrate, the photoresist layer exposed to actinic radiation through a patterned photomask and the exposed photoresist layer developed to form a patterned photoresist layer. When the photoresist layer comprises positive photoresist, the developer dissolves the regions of the photoresist exposed to the actinic radiation and does not dissolve the regions where the patterned photomask blocked (or greatly attenuated the intensity of the radiation) from impinging on the photoresist layer. When the photoresist layer comprises negative photoresist, the developer does not dissolve the regions of the photoresist exposed to the actinic radiation and does dissolve the regions where the patterned photomask blocked (or greatly attenuated the intensity of the radiation) from impinging on the photoresist layer. 
       FIG. 2A  is a top view and  FIG. 2B  is a cross-section view through line  2 B- 2 B of  FIG. 2A . In  FIGS. 2A and 2B , hardmask layer  120  (see  FIG. 1B ) has been etched and patterned photoresist layer  125  removed (see  FIG. 1B ) to form an array of narrow mandrels  120 A and a wide mandrel  120 B. Narrow mandrels  120 A are about W1 wide and spaced apart about distance S1. Wide mandrel  120 B is about W2 wide and spaced about distance S2 from the adjacent narrow mandrel  120 A. 
       FIG. 3A  is a top view and  FIG. 3B  is a cross-section view through line  3 B- 3 B of  FIG. 3A . In  FIGS. 3A and 3B , a conformal layer  130  is formed on the top surfaces and sidewalls of mandrels  120 A and  120 B and the regions of the top surface of second hardmask  115  between the mandrels. In one example, conformal layer  130  comprises silicon nitride. In one example, conformal layer  130  is between about 18 nm and about 60 nm thick. 
       FIG. 4A  is a top view and  FIG. 4B  is a cross-section view through line  4 B- 4 B of  FIG. 4A . In  FIGS. 4A and 4B , an anisotropic etch such as a directional reactive ion etch (RIE) that is selective to the material of conformal layer  130  (see  FIG. 3B ) is performed to form loops of sidewall spacers  130 A on the sidewalls of mandrels  120 A and  120 B. Note the spaces “S” between opposite facing sidewall spacers  120 A on adjacent mandrels  120 A. The width W3 of sidewall spacers  130 A is about the same as the thickness of conformal layer  130  (see  FIG. 3B ). Sidewall spacers  130 A on adjacent mandrels are spaced a distance S3 apart. In one example, S3=W1=W3. In one example, S3 is between about 18 nm and about 60 nm. 
       FIG. 5A  is a top view and  FIG. 5B  is a cross-section view through line  5 B- 5 B of  FIG. 5A . In  FIGS. 5A and 5B , mandrels  120 A and  120 B (see  FIG. 4B ) are removed. Note the spaces between adjacent sidewall spaces  130 A marked “M” were where the mandrels were before mandrel removal. The spaces marked “S” were discussed supra with respect to  FIG. 4B . Features that will be subsequently fabricated in dielectric layer  105  by transferring the pattern of “S” spaces are non-mandrel defined features. Features that will be subsequently transferred into dielectric layer using portions of the pattern of spaces “M” mandrel defined features. The pattern of sidewall spacers after trimming in  FIGS. 9A ,  9 B and  9   c ) will be SIT features. Thus, both mandrel and non-mandrel features will have been defined by the first photomask of the three photomask process. Note the “S” and “M” spaces alternate. At this point, sidewall spacers  130 A are loops with a void in the middle of the loop. 
       FIG. 6A  is a top view,  FIG. 6B  is a cross-section view through line  6 B- 6 B of  FIG. 6A  and  FIG. 6C  is a cross-section view through line  6 C- 6 C of  FIG. 6A . In  FIGS. 6A ,  6 B and  6 C, an organic planarization layer (OPL)  135  is formed on top surfaces and sidewalls of sidewall spacers  130 A on the top surface of second hardmask layer  115  between the sidewall spacers. In one example, OPL  135  is an organic polymer that is not soluble in the developer used to develop the photoresist layer. An OPL forms a planar surface over an otherwise non-planar surface. An antireflective coating (ARC)  140  is formed on the top surface of OPL  135  and a second patterned photoresist layer  145  is formed on the top surface of ARC  140 . Patterned photoresist layer  145  is used to “trim” the loops of sidewall spacers  130 A into strips. ARC  140  was patterned during development of the photoresist. In one example, ARC  140  is a silicon containing ARC (SiARC). Referring to  FIG. 6A , there are four regions  146 ,  147 ,  148  and  149  of patterned photoresist layer  145  that extend further over a portion of sidewall spacers  130 A than other regions of patterned photoresist layer  145 . Regions  146 ,  147 ,  148  and  149  have a width W4. Regions  146  and  147  extend over opposite sides of a loop of one sidewall spacer  130 A. Regions  148  and  149  extend over adjacent sidewall spacer of two different sidewall spacer loops. W4 should be greater than W1+2×W3 for regions  146  and  147  and greater than S3+2×W3 for regions  148  and  149 . 
       FIG. 7A  is a top view,  FIG. 7B  is a cross-section view through line  7 B- 7 B of  FIG. 7A  and  FIG. 7C  is a cross-section view through line  7 C- 7 C of  FIG. 7A . In  FIGS. 7A ,  7 B and  7 C, OPL  135  is partially removed (e.g., by RIE) where not protected by patterned photoresist layer  145  (see  FIG. 6A ) to expose those sidewall spacers  130 A that were not under patterned photoresist layer  145 . No region of OPL is completely removed at this point. However, the entire second patterned photoresist layer is removed during the OPL partial removal process so ARC  140  is exposed. 
       FIG. 8A  is a top view,  FIG. 8B  is a cross-section view through line  8 B- 8 B of  FIG. 8A  and  FIG. 8C  is a cross-section view through line  8 C- 8 C of  FIG. 8A . In  FIGS. 8   a ,  8 B and  8 C, those regions of sidewall spacers  130 A not protected by OPL layer  135  are removed leaving OPL islands  135 A in those regions. ARC  140  (see  FIG. 7A ) is also removed. 
       FIG. 9A  is a top view,  FIG. 9B  is a cross-section view through line  9 B- 9 B of  FIG. 9A  and  FIG. 9C  is a cross-section view through line  9 C- 9 C of  FIG. 9A . In  FIGS. 9A ,  9 B and  9 C, the remaining OPL  135  and  135 A (see  FIG. 8A ) is removed to leave trimmed sidewall spacers  130 B. Not a first pair  150  and a second pair  155  of sidewall spacers  130 B extend past the other sidewall spacers  130 B. 
       FIG. 10A  is a top view,  FIG. 10B  is a cross-section view through line  10 B- 10 B of  FIG. 10A  and  FIG. 10C  is a cross-section view through line  10 C- 10 C of  FIG. 10A . In  FIG. 10 , an OPL layer  160  is formed on top sidewalls and top surfaces of sidewall spacers  130 B and the top surface of second hardmask layer  115  between sidewall spacers  130 B. An antireflective coating (ARC)  165  is formed on the top surface of OPL  160  and a third patterned photoresist layer  170  is formed on the top surface of ARC  165 . Patterned photoresist layer  145  is used to connect features formed the loops of sidewall spacers  130 A into strips. ARC  165  was patterned during development of the photoresist. In one example, ARC  165  is a SiARC. Openings  170 A,  170 B,  170 C and  170 D in patterned photoresist layer  170  have a width W5. W5 is selected be greater than the space between adjacent sidewall spacers  130 B, but less than the space between adjacent sidewall spacers plus twice the width of the sidewall spacers. 
       FIG. 11A  is a top view,  FIG. 11B  is a cross-section view through line  11 B- 11 B of  FIG. 11A  and  FIG. 11C  is a cross-section view through line  11 C- 11 C of  FIG. 11A . In  FIGS. 11A ,  11 B and  11 C, OPL  160  is removed where not protected by patterned photoresist layer  170  (see  FIGS. 10B and 10C ) to expose those portions of sidewall spacers  130 B that were not under photoresist layer  170 . Photoresist layer  170  is also removed during the OPL removal process to expose ARC  165 . Since the pattern of patterned photoresist layer  170  has been transferred into OPL  160 , OPL  160  is a pattern transfer layer as well as a planarization layer. 
       FIG. 12A  is a top view,  FIG. 12B  is a cross-section view through line  12 B- 12 B of  FIG. 12A  and  FIG. 12C  is a cross-section view through line  12 C- 12 C of  FIG. 12A . In  FIGS. 12A ,  12 B and  12 C, second hardmask layer  115  is removed (e.g., by RIE) where not protected by sidewall spacers  130 B or by OPL  160 . Any remaining ARC  165  (see  FIGS. 11B and 11C ) is also removed by the second hardmask etch process. 
       FIG. 13A  is a top view,  FIG. 13B  is a cross-section view through line  13 B- 13 B of  FIG. 13A  and  FIG. 13C  is a cross-section view through line  13 C- 13 C of  FIG. 13A . In  FIGS. 13A ,  13 B and  13 C, all remaining OPL  160  is removed (e.g., by RIE). 
       FIGS. 14 and 15  illustrate fabrication of damascene wires in a dielectric layer using the pattern of  FIG. 13  according to embodiments of the present invention.  FIG. 14A  is a top view,  FIG. 14B  is a cross-section view through line  14 B- 14 B of  FIG. 14A  and  FIG. 14C  is a cross-section view through line  14 C- 14 C of  FIG. 14A . In  FIGS. 14A ,  14 B and  14 C, trenches  175  are etched completely through first hardmask layer  110  and into dielectric layer  105 , where the first hardmask layer is not protected by sidewall spacers  130 B or second hardmask layer.  FIG. 15A  is a top view,  FIG. 15B  is a cross-section view through line  15 B- 15 B of  FIG. 15A  and  FIG. 15C  is a cross-section view through line  15 C- 15 C of  FIG. 15A . In  FIGS. 15A ,  15 B and  15 C, trenches  175  of  FIGS. 14B and 14C  are filled with metal to form a wire  180 , narrow wires  190 A,  190 B,  190 C,  190 D,  19 E,  190 F,  190 G and  190 H of width W8, and a wider wire  195  of width W7 with W7 greater than W8. In the example of  FIGS. 14A ,  14 B and  14 C, the trenches do not extend completely through dielectric layer  105  so wires  180 , 190 A,  190 B,  190 C,  190 D,  19 E,  190 F,  190 G and  190 H and  195  are dual damascene wires, with only the wire portion being illustrated. The step of forming the via portions of dual damascene wires is not illustrated. The openings for the vias would be formed before trenches  175  are formed or after trenches  175  are formed but before filling with metal. See discussion infra. If trenches  175  had extended through dielectric layer  175 , then wires  180 , 190 A,  190 B,  190 C,  190 D,  19 E,  190 F,  190 G and  190 H and  19  would be single-damascene wires. 
     A damascene process is one in which wire trenches or via openings are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited in the trenches and on a top surface of the dielectric. A chemical-mechanical-polish (CMP) process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the dielectric layer to form damascene wires (or damascene vias). When only a trench and a wire (or only a via opening and a via) is formed the process is called single-damascene. 
     There are two processes for forming dual damascene wires. A via first dual-damascene process is one in which via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. A trench first dual-damascene process is one in which trenches are formed part way through the thickness of a dielectric layer followed by formation of vias inside the trenches the rest of the way through the dielectric layer in any given cross-sectional view. All via openings are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is deposited on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planar with the surface the dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias. 
     Returning to  FIGS. 15A ,  15 B and  15 C, wire network  180  includes a first wire  185 A, a second wire  185 B, a third wire  185 C, a fourth wire  185 D and a fifth wire  185 E. Opposite ends of wire  185 A are connected to wires  185 B and  185 C. Opposite ends of wire  185 D are connected to wires  185 B and  185 E. The shapes of wires  180 , 190 A,  190 B,  190 C,  190 D,  19 E,  190 F,  190 G and  190 H and  195  were not defined by sidewall spacers. The shapes of wires  180 , 190 A,  190 B,  190 C,  190 D,  19 E,  190 F,  190 G and  190 H and  195  were defined by the first photomask. The shapes of wire  190 A, wire  185 A, wire  190 D, wire  190 F, wire  190 G and wire  195  were defined by mandrels. The shapes of wire  190 B,  190 C,  190 E, wire  185 D and wire  190 H were defined by the space between sidewall spacers before the mandrels were removed. The shapes of wires  185 B,  185 E and  185 E were defined by third patterned photoresist layer  170  of  FIG. 10A . The shape of the dielectric between wires was defined by sidewall spacers after trimming. The shapes of the dielectric between wires are SIT shapes, the wires are not SIT shapes. 
     Note, that wires defined by mandrels and wires defined by the space between sidewall spacers before mandrel removal alternate. While the number of wires between wires  185 A and  185 D is an even number, with wire  185 A defined by a mandrel and wire  185 D defined by the space between spacers before mandrel removal, the method can produce a odd number of wires between the connected wire portions, with the connected wires both being defined by a mandrel or both being defined by the space between sidewall spacers before mandrel removal. 
       FIGS. 16 and 17  are top views of exemplary damascene wire structures that may be fabricated according to embodiments of the present invention.  FIG. 16  includes wires  200 A,  200 B,  200 C,  200 D,  200 E,  200 F,  200 G,  200 H,  200 I,  200 J,  200 K,  205 A,  205 B and  205 C. Wire  205 A connects narrow wires  200 D and  200 H with a wider wire  200 A. There are two narrow wires (wires  200 B and  200 C) between wire  200 A and  200 D and three (an odd number) of narrow wires (wires  200 E,  200 F and  200 G) between narrow wires  200 D and  200 H.  FIG. 16  includes wires  210 A,  210 B,  210 C,  210 D,  210 E,  210 F,  210 G,  210 H,  2101 ,  210 J,  210 K,  215 A,  215 B and  215 C. In  FIG. 17 , wire  215 A connects wire  210 C (a narrow wire), wire  210 F (a wide wire) and wire  210 H (a narrow wire). Wires  210 D,  210 E and  210 G (narrow wires) and wire  210 F (a wide wire) are between wires  210 C and  210 H. (narrow wires). 
     Thus, the embodiments of the present invention provide a method of fabricating damascene wiring levels wherein wires formed by SIT process and wires formed by non-SIT processes on the same level can be interconnected on that same level. However, the method is not limited to forming damascene wires but may be used to fabricate other structures of integrated circuits. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.