Abstract:
A method and apparatus performs memory read and write operations according to a standard flash memory interface using more cost-effective DRAM devices while maintaining the non-volatile characteristics of a flash memory device using a standby power source. Also, the present invention provides a method that replaces defective memory cell locations with functional memory cell locations.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to flash memory devices, dynamic random-access memory (DRAM) devices, and memory modules.  
           [0002]    Flash memory devices are non-volatile as they retain the memory contents in the absence of a power supply. As such, they are often used in add-on cards or modules for portable electronic systems such as digital cameras, audio players, personal digital assistants (PDA), and notebook computers.  
           [0003]    However, due to the process complexity, the cost of a flash memory device is significantly higher than a dynamic random-access memory (DRAM) device of the same storage capacity.  
           [0004]    In fact, the cost of a small number of flash memory add-on cards may exceed the cost of the portable electronic system itself.  
           [0005]    This cost factor limits the number of add-on cards one may afford to have in association with a portable electronic system. This factor also limits the market popularity and the installation base for the particular portable electronic system.  
           [0006]    Users are constantly seeking for a low-cost solution to the portability, flexibility, extendibility, and affordability of a portable system.  
         BRIEF SUMMARY OF THE INVENTION  
         [0007]    This invention proposes a method and apparatus to build flash memory units with low-cost dynamic random-access memory devices.  
           [0008]    This invention provides a method that maintains the same flash memory device interface to the remaining part of the electronic subsystem or system.  
           [0009]    The present invention provides a method to directly replace existing flash memory devices with DRAM-based devices in existing portable electronic systems or add-on modules.  
           [0010]    The present invention further provides a method that can be implemented with the least efforts and in the least amount of time. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a diagram of a prior art flash memory add-on module.  
         [0012]    [0012]FIG. 2 shows a preferred embodiment of the present invention for a DRAM-based flash memory add-on module.  
         [0013]    [0013]FIG. 3 shows another preferred embodiment of the present invention for a DRAM-based flash memory add-on module.  
         [0014]    [0014]FIG. 4 shows a preferred embodiment of the present invention for a DRAM-based flash memory controller unit.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]    The present invention will be illustrated with some preferred embodiments.  
         [0016]    [0016]FIG. 1 is a diagram of a prior art flash memory add-on module. The flash memory add-on module  101  contains one or more flash memory devices  102  and an optional flash memory module controller unit  103 .  
         [0017]    The flash memory add-on module  101  interfaces with the external system through the memory module interface  104 . The memory module interface  104  contains explicit or implicit memory address, memory control, and memory data signals. These signals may be space-multiplexed, time-multiplexed, or formatted according to certain protocol specification.  
         [0018]    The optional flash memory module controller unit  103  transforms the memory module signals from the memory module interface  104  into flash memory signals on the flash memory address lines  105 , flash memory control lines  106 , and flash memory data lines  107 .  
         [0019]    The optional flash memory module controller unit  103  also receives flash memory signals from the flash memory data lines  107  and transforms the flash memory signals into memory module signals on the memory module interface  104 .  
         [0020]    [0020]FIG. 2 shows a preferred embodiment of the present invention for a DRAM-based flash memory add-on module. The DRAM-based flash memory add-on module  201  consists of one or more DRAM devices  202 , an optional flash memory module controller unit  203 , and a DRAM-based flash memory controller unit  204 .  
         [0021]    The flash memory add-on module  201  interfaces with the external system through the memory module interface  205 . The memory module interface  205  contains explicit or implicit memory address, memory control, and memory data signals. These signals may be space-multiplexed, time-multiplexed, or formatted according to certain protocol specification.  
         [0022]    The optional flash memory module controller unit  203  transforms the memory module signals from the memory module interface  205  into flash memory signals on the flash memory address lines  206 , flash memory control lines  207 , and flash memory data lines  208 .  
         [0023]    The optional flash memory module controller unit  203  also receives flash memory signals from the flash memory data lines  208  and transforms the flash memory signals into memory module signals on the memory module interface  205 .  
         [0024]    The DRAM-based flash memory controller  204  receives flash memory signals on the flash memory address lines  206 , flash memory control lines  207 , and flash memory data lines  208 . The controller transforms these flash memory signals into DRAM signals on the DRAM address lines  209 , DRAM control lines  210 , and DRAM data lines  211 .  
         [0025]    The DRAM-based flash memory controller  204  receives DRAM signals from the DRAM data lines  211  and transforms the DRAM signals into flash memory signals on the flash memory data lines  208 .  
         [0026]    For certain applications, a DRAM-based flash memory controller  204  may be integrated with a flash memory module controller unit  203  to form a DRAM-based flash memory module controller unit  212 .  
         [0027]    [0027]FIG. 3 shows another preferred embodiment of the present invention for a DRAM-based flash memory add-on module. In this preferred embodiment, there is a dedicated DRAM-based flash memory controller for each DRAM device.  
         [0028]    The DRAM-based flash memory add-on module  301  consists of one or more DRAM devices  302 , an optional flash memory module controller unit  303 , and one or more DRAM-based flash memory controller units  304 .  
         [0029]    The flash memory add-on module  301  interfaces with the external system through the memory module interface  305 . The memory module interface  305  contains explicit or implicit memory address, memory control, and memory data signals. These signals may be space-multiplexed, time-multiplexed, or formatted according to certain protocol specification.  
         [0030]    The optional flash memory module controller unit  303  transforms the memory module signals from the memory module interface  305  into flash memory signals on the flash memory address lines  306 , flash memory control lines  307 , and flash memory data lines  308 .  
         [0031]    The optional flash memory module controller unit  303  also receives flash memory signals from the flash memory data lines  308  and transforms the flash memory signals into memory module signals on the memory module interface  305 .  
         [0032]    The DRAM-based flash memory controller  304  receives flash memory signals on the flash memory address lines  306 , flash memory control lines  307 , and flash memory data lines  308 . The controller transforms these flash memory signals into DRAM signals on the DRAM address lines  309 , DRAM control lines  310 , and DRAM data lines  311 .  
         [0033]    The DRAM-based flash memory controller  304  receives DRAM signals from the DRAM data lines  311  and transforms the DRAM signals into flash memory signals on the flash memory data lines  308 .  
         [0034]    [0034]FIG. 4 shows a preferred embodiment of the present invention for a DRAM-based flash memory controller unit.  
         [0035]    The DRAM-based flash memory controller unit  401  consists of a memory address interface unit  402 , a memory control unit  403 , an optional memory data interface unit  404 , an optional clock-timing unit  405 , and an optional power supply unit  406 .  
         [0036]    The memory control unit  403  receives flash memory signals from the flash memory control lines  408 . it may also receive flash memory signals from flash memory address lines  407  and flash memory data lines  409 . The memory control unit generates DRAM control signals on the DRAM control lines  410 .  
         [0037]    The memory control unit also generates DRAM address control signals on the DRAM address control lines  411 . It may also generate DRAM data control signals on the DRAM data control lines  412 .  
         [0038]    When attached to an external system, the memory control unit  403  transforms flash memory read and write access control signals into DRAM read and write access control signals. It also generates DRAM refresh control signals at the appropriate time.  
         [0039]    When detached from an external system, the DRAM-based flash memory controller unit  401  operates in a standby mode. The memory control unit  403  only generates memory refresh control signals to the DRAM devices to maintain the DRAM memory contents.  
         [0040]    The memory address interface unit  402  receives flash memory address signals from the flash memory address lines  407  and DRAM address control signals from DRAM address control lines  411 .  
         [0041]    For memory read and write operations, the memory address interface unit  402  multiplexes the flash memory address into DRAM row and column address signals on the DRAM address lines  413 .  
         [0042]    Upon control signals from the memory control unit  403 , the memory address interface unit  402  may also generate signals on the DRAM memory address lines to control the DRAM operational modes.  
         [0043]    The optional memory data interface unit  402  receives DRAM data control signals from DRAM data control lines  412 . The memory data interface unit  404  controls the memory data input and output between the flash memory data lines  409  and DRAM data lines  415 .  
         [0044]    The optional clock-timing unit  405  generates clock-timing signals  416  to the memory control unit  403 . The clock-timing unit  405  also sends DRAM clock-timing signals  417  to the DRAM devices.  
         [0045]    When attached to an external system, the clock-timing unit  405  may receive external clock-timing signals  418  to use as a timing base.  
         [0046]    The optional power supply unit  406  generates power for the logic units in the flash memory controller unit  401 . The power supply unit  406  also sends power  419  to the DRAM devices.  
         [0047]    When attached to an external system, the power supply unit  406  may receive external power  420  from the external system in order to preserve power for standby use only.  
         [0048]    The memory control unit  403  may also contain control logic to detect certain memory address locations that contain defective memory cells. The control unit may send signals to the memory address interface unit  402  to re-map the memory address to specified DRAM address locations that contain functional memory cells.  
         [0049]    The address re-mapping information may be hard-wired in the control logic or stored in internal or external memory cells.