Abstract:
A bandgap reference circuit incorporates first, second, and third current sources, an operational amplifier coupled to the second and the third current sources, a voltage divider, a first resistor, and first, second, and third bipolar transistors. The second bipolar transistor has a base configured to receive a bias voltage from the voltage divider. The third bipolar transistor has a base and a collector electrically connected to the ground voltage. The first resistor is coupled between the third current source and the third bipolar transistor.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to reference circuits, and more specifically to a bandgap reference circuit. 
         [0003]    2. Description of the Related Art 
         [0004]    A bandgap reference circuit is used to generate a precise and a stable output voltage. The generated voltage is independent of process, voltage, and temperature. The bandgap reference circuit is widely used in various analogue and digital circuits that require a precise voltage for operation. 
         [0005]      FIG. 1  illustrates one commonly used bandgap reference circuit  100 . Referring to  FIG. 1 , the bandgap reference circuit  100  includes PMOS transistors M 1 , M 2 , and M 3 , an operational amplifier OP, resistors R 1  and R 2 , and bipolar transistors Q 1 , Q 2 , and Q 3 . If the base current is neglected, the output voltage VOUT of the bandgap reference circuit  100  can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   VOUT 
                   = 
                   
                     
                       VEB 
                        
                       
                           
                       
                        
                       3 
                     
                     + 
                     
                       VT 
                       × 
                       ln 
                        
                       
                           
                       
                        
                       N 
                       × 
                       
                         ( 
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             2 
                           
                           
                             R 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0006]    Where VEB 3  is the emitter-base voltage of the bipolar transistor Q 3 , VT is the thermal voltage at room temperature, and N is the ratio of the emitter areas of the bipolar transistor Q 2  to the emitter areas of the bipolar transistor Q 1 . 
         [0007]    As can be seen from the equation (1), by adjusting the ratio of resistors R 2 /R 1 , the conventional bandgap reference circuit  100  can provide a stable reference voltage VOUT having a zero temperature coefficient. The voltage level of the voltage VOUT is at around 1.25V, which is approximately equal to the silicon energy gap measured in electron volts, i.e., the silicon bandgap voltage. 
         [0008]    Referring to  FIG. 1 , the minimal voltage level of the supply voltage VDD required by the normal operation of the bandgap reference circuit  100  is: 
         [0000]    
       
         
           
             
               
                 
                   VDD 
                   = 
                   
                     
                        
                       VDS 
                        
                     
                     + 
                     
                       VEB 
                        
                       
                           
                       
                        
                       3 
                     
                     + 
                     
                       VT 
                       × 
                       ln 
                        
                       
                           
                       
                        
                       N 
                       × 
                       
                         ( 
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             1 
                           
                           
                             R 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0009]    Where |VDS| is the drain-source voltage of the PMOS transistor M 3 . 
         [0010]    From equation (2) it can be seen that since the voltage level of VEB 3  is around 0.7V, the voltage level of the supply voltage VDD may be larger than 1.8V to maintain the stable reference voltage VOUT. 
       SUMMARY OF THE INVENTION 
       [0011]    An aspect of the present invention is to provide a bandgap reference circuit. 
         [0012]    According to one embodiment of the present invention, the bandgap reference circuit comprises first, second, and third current sources, an operational amplifier, first, second, and third bipolar transistors, a voltage divider, and a first resistor. The operational amplifier is electrically connected to the first, second, and third current sources. The first bipolar transistor has an emitter electrically connected to the first current source, a base and a collector coupled to a ground voltage. The voltage divider is electrically connected between the emitter of the first bipolar transistor, wherein the voltage divider provides a bias voltage proportional to a base-emitter voltage of the first bipolar transistor. The second bipolar transistor has a base configured to receive the bias voltage, an emitter electrically connected to the second current source, and a collector electrically connected to the ground voltage. The third bipolar transistor has a base and a collector electrically connected to the ground voltage. The first resistor is electrically connected between the third current source and an emitter of the third bipolar transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The invention will be described according to the appended drawings in which: 
           [0014]      FIG. 1  illustrates one commonly used bandgap reference circuit; and 
           [0015]      FIG. 2  shows a schematic diagram of a bandgap reference circuit according to one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]      FIG. 2  shows a schematic diagram of a bandgap reference circuit  200  according to one embodiment of the present invention. Referring to  FIG. 2 , the bandgap reference circuit  200  comprises a current source unit  22 , a voltage divider  24 , an operational amplifier OP, two resistors R 1  and R 2 , and three bipolar transistors Q 1 , Q 2 , and Q 3 . 
         [0017]    The current source unit  22  provides four stable currents I 1 , I 2 , I 3 , and I 4 . In this embodiment, the current source unit  22  is a current mirror formed by four PMOS transistors M 1 , M 2 , M 3 , and M 4 . Referring to  FIG. 2 , each of the PMOS transistors M 1 , M 2 , M 3 , and M 4  has a source electrically connected to a supply voltage VDD and has a gate electrically connected to an output terminal of the operational amplifier OP. Since the gates of the PMOS transistors M 1 , M 2 , M 3 , and M 4  are connected to each other and the sources of the PMOS transistors M 1 , M 2 , M 3 , and M 4  are connected to the common supply voltage VDD, the currents I 1 , I 2 , I 3 , and I 4  through the PMOS transistors M 1 , M 2 , M 3 , and M 4 , respectively, are proportional to the W/L ratio of the transistors. 
         [0018]    Referring to  FIG. 2 , the bipolar transistor Q 1  has an emitter coupled to the drain of the PMOS transistor M 1  and the voltage divider  24 , and has a base and a collector both coupled to a ground voltage. The bipolar transistor Q 2  has an emitter coupled to the drain of the PMOS transistor M 2 , a base coupled to a voltage VA from the voltage divider  24 , and a collector coupled to the ground voltage. The bipolar transistor Q 3  has a base and a collector both coupled to the ground voltage. The resistor R 1  is couple between the drain of the PMOS transistor M 3  and an emitter of the bipolar transistor Q 3 . 
         [0019]    Referring to  FIG. 2 , the operational amplifier OP has a positive input terminal coupled to the drain of the PMOS transistor M 3 , a negative input terminal coupled to the drain of the PMOS transistor M 2 , and the output terminal coupled to the gates of the PMOS transistors M 1 , M 2 , M 3 , and M 4 . The amplifier OP and the PMOS transistors M 2  and M 3  constitute a negative feedback loop which forces the voltages VD 1  and VD 3  to be substantially equal. Thus, the voltages VD 1  and VD 3  can be expressed as: 
         [0000]        VD 1= VD 3= VA+VEB 2= VEB 3+ I 3× R 1   (3)
 
         [0020]    VEB 2  is the emitter-base voltage of the bipolar transistor Q 2 , and VEB 3  is the emitter-base voltage of the bipolar transistor Q 3 . 
         [0021]    Referring to FIG,  2 , the voltage divider  24  is coupled to the emitter of the bipolar transistor Q 1 . In this embodiment, the voltage divider  24  is formed by two series connected resistors R 3  and R 4 . Therefore, the voltage divider  24  provides the voltage VA proportional to a base-emitter voltage of the bipolar transistor Q 1 . Thus, the voltage VA can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   VA 
                   = 
                   
                     VEB 
                      
                     
                         
                     
                      
                     1 
                     × 
                     
                       
                         R 
                          
                         
                             
                         
                          
                         4 
                       
                       
                         
                           R 
                            
                           
                               
                           
                            
                           3 
                         
                         + 
                         
                           R 
                            
                           
                               
                           
                            
                           4 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0022]    Where VEB 1  is the emitter-base voltage of the bipolar transistor Q 1 . 
         [0023]    Accordingly, equation (3) can rearranged into the following equation (5) by using equation (4): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           I 
                            
                           
                               
                           
                            
                           3 
                           × 
                           R 
                            
                           
                               
                           
                            
                           1 
                         
                         = 
                           
                          
                         
                           VA 
                           + 
                           
                             VEB 
                              
                             
                                 
                             
                              
                             2 
                           
                           - 
                           
                             VEB 
                              
                             
                                 
                             
                              
                             3 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             VEB 
                              
                             
                                 
                             
                              
                             1 
                             × 
                             
                               ( 
                               
                                 
                                   R 
                                    
                                   
                                       
                                   
                                    
                                   4 
                                 
                                 
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     3 
                                   
                                   + 
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     4 
                                   
                                 
                               
                               ) 
                             
                           
                           + 
                           
                             VT 
                             × 
                             ln 
                              
                             
                                 
                             
                              
                             N 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0024]    VT is the thermal voltage at room temperature, and N is the ratio of the emitter areas of the bipolar transistor Q 3  to the emitter areas of the bipolar transistor Q 2 . In this embodiment, the currents flowing through the bipolar transistors Q 2  and Q 3  are substantially equivalent. 
         [0025]    Thus, the current I 3  through the resistor R 1  can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                      
                     
                         
                     
                      
                     3 
                   
                   = 
                   
                     
                       1 
                       
                         R 
                          
                         
                             
                         
                          
                         1 
                       
                     
                     × 
                     
                       ( 
                       
                         ( 
                         
                           
                             VEB 
                              
                             
                                 
                             
                              
                             1 
                             × 
                             
                               ( 
                               
                                 
                                   R 
                                    
                                   
                                       
                                   
                                    
                                   4 
                                 
                                 
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     3 
                                   
                                   + 
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     4 
                                   
                                 
                               
                               ) 
                             
                           
                           + 
                           
                             VT 
                             × 
                             ln 
                              
                             
                                 
                             
                              
                             N 
                           
                         
                         ) 
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0026]    Since the emitter-base voltage of the transistor Q 1  has a negative temperature coefficient of −2 mV/° C. and the thermal voltage VT has a positive temperature coefficient of 0.085 mV/° C., the temperature coefficient of the current I 3  can be adjusted to be positive, negative, or substantially zero. The positive temperature coefficient of the current I 3  is obtained by increasing the values of N. The negative temperature coefficient of the current I 3  is obtained by increasing the ratio of the voltage divider  24 . The temperature coefficient of the current I 3  can be adjusted to be substantially zero by varying the values of N and the ratio of the voltage divider  24 . 
         [0027]    In order to provide a stable reference voltage having a low (e.g., substantially zero) temperature coefficient, the bandgap reference circuit  200  comprises the resistor R 2  connected between the drain of the PMOS transistor M 4  and the ground voltage as shown in  FIG. 2 . With such a circuit configuration, the reference voltage VREF can be expressed as: 
         [0000]        VREF=I 4× R 2   (7)
 
         [0028]    In this embodiment, currents flowing through transistors Q 1 , Q 2  and Q 3  are the same. In addition, a size ratio of the PMOS transistors M 1 , M 2 , M 3 , and M 4  in the current source unit  22  is set to 2:1:1:1. Therefore, the current I 2 , I 3 , and I 4  are substantially the same and the current I 1  has twice the magnitude of the current I 2 . Since the currents I 3  and I 4  have the same value, equation (7) can be rearranged into the following equation (8) by using equation (6): 
         [0000]    
       
         
           
             
               
                 
                   VREF 
                   = 
                   
                     
                       ( 
                       
                         
                           R 
                            
                           
                               
                           
                            
                           2 
                         
                         
                           R 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       ) 
                     
                     × 
                     
                       ( 
                       
                         ( 
                         
                           
                             VEB 
                              
                             
                                 
                             
                              
                             1 
                             × 
                             
                               ( 
                               
                                 
                                   R 
                                    
                                   
                                       
                                   
                                    
                                   4 
                                 
                                 
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     3 
                                   
                                   + 
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     4 
                                   
                                 
                               
                               ) 
                             
                           
                           + 
                           
                             VT 
                             × 
                             ln 
                              
                             
                                 
                             
                              
                             N 
                           
                         
                         ) 
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0029]    Hence, the positive temperature coefficient of the voltage VREF is obtained by increasing the values of N. The negative temperature coefficient of the voltage VREF is obtained by increasing the ratio of the voltage divider  24 . If the value of N, the ratio of the voltage divider  24 , and the ratio of the resistance value of resistor R 2  to R 1  are selected appropriately, the output voltage VREF of the bandgap reference circuit  200  will have a zero temperature coefficient and low sensitivity to temperature. 
         [0030]    In addition, compared with the prior art, the bandgap reference circuit  200  of  FIG. 2  can be operable at a lower supply voltage level. Recalling equation (1): 
         [0000]    
       
         
           
             
               
                 
                   VOUT 
                   = 
                   
                     
                       VEB 
                        
                       
                           
                       
                        
                       3 
                     
                     + 
                     
                       VT 
                       × 
                       ln 
                        
                       
                           
                       
                        
                       N 
                       × 
                       
                         
                           R 
                            
                           
                               
                           
                            
                           1 
                         
                         
                           R 
                            
                           
                               
                           
                            
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0031]    From equation (1) it can be seen that the output voltage of the conventional bandgap reference circuit is limited to 1.25V in order to obtain a zero temperature coefficient. However, from equation (8) it can be seen that the output voltage VREF of the bandgap reference circuit of the invention can be reduced since the resistor R 2  is directly connected to the ground voltage, rather than the bipolar transistor. With such circuit configuration, the bandgap reference circuit of the invention can provide an output voltage VREF in a wide voltage range from 0V to 0.64V depending on the value of the resistor R 2 . Therefore, the bandgap reference circuit  200  can be operated at the lower supply voltage level, e.g., on the order of 1V. 
         [0032]    The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the invention as recited in the following claims.