Abstract:
A method for detecting defects between parallel rows of conductors (ROW) in an integrated-circuit array (ARR) includes (a) connecting all alternate rows (ROW) of conductors of the array (ARR) to a first voltage (V DD ) and connecting the other alternate rows (ROW) of conductors of the array (ARR) to a second voltage (V REF ) different from the first voltage, while measuring the current drawn; (b) if the current does not exceed a first limit, ending the process; (c) if the current exceeds the first limit, separately repeating step (a) on first and second halves of the array rather than all of the array, with all of the rows (ROW) of conductors of the half of the array (ARR) not under test connected to the second voltage (V REF ); (d) if the current exceeds a second limit for a half of the array (ARR) in step (c), repeating step (a) on each quarter of the array (ARR) in that half with all of the rows (ROW) of the array (ARR) not under test connected to the second voltage V REF  ; and (e) if the current exceeds a third limit for an array (ARR) quarter in step (d), continuing analogous steps for array (ARR) fractions divisible by two and for predetermined current limits until sufficient information concerning the defects is determined.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to integrated circuits and, in particular, to a method for detecting defects that allow undesired current flow between conductive elements of integrated-circuit arrays, including memories for storing digital data. 
     Memory arrays are typically a matrix of memory-cell transistors physically arranged in adjacent, parallel rows and in adjacent, parallel columns. Parallel conductive wordlines and parallel conductive bitlines, each separated by an insulator, provide electrical connection to the memory cells for reading and writing in the case of random-access memories; or for programming, reading and/or erasing in the case of nonvolatile memories such as EPROMs (Electrically Programmable Read-Only-Memories) and Flash EPROMs (Flash Electrically-erasable, Programmable Read-Only-Memories). One defect arising during manufacture is a short circuit (short) between adjacent wordlines or between adjacent bitlines. A wordline short may result, for example, from an etching process that leaves a filament of conducting material between wordlines formed from a single layer of that conducting material, which may be aluminum or doped polycrystalline silicon. A bitline short may result, for example, from any step in the process that leaves conducting material between bitlines, which may also be formed from an etched layer of aluminum or doped polycrystalline silicon. Other defects may short wordlines to bitlines, or may short either of these to the semiconductor substrate. 
     It is necessary to test memory arrays during manufacture to detect the presence or absence of these defects. Some shorts may have a sufficiently low resistance that none of the cells in the connected row or column are functional. Other shorts may have a sufficiently high resistance that the cells in the connected row or column are programmable (or writable) and readable, but those high-resistance shorts may result in poor reliability of, or in short life of, the memory array. 
     The memory cells of nonvolatile arrays, for example, are generally checked prior to packaging by applying programming voltages that tend to charge the floating gates of all of the memory cells. Charging a floating gate with electrons usually means storing a &#34;zero&#34; bit, sometimes meaning a &#34;one&#34; bit. The data stored in the cells are then read in a form that maps the pattern of any cells that do not indicate storage of a &#34;zero&#34; bit as a result of the programming operation. For example, certain patterns of cells that fail to program indicate the presence of low-resistance shorts between wordlines and/or bitlines. If a relatively small number of rows and/or columns of cells have defects, then those defective rows and/or columns are replaced with redundant rows and/or columns by using lasers, or electrical means such as nonvolatile memory cells, to activate fuses that reroute circuitry. While nonvolatile arrays are discussed here by way of example, similar tests are performed on random access and other memory types. 
     After correction to replace defective memory cells, it is often desirable to test such very-large-scale-integrated circuits for more subtle defects, such as defects that may pose long-term reliability problems. Such subtle defects include high-resistance, low-current paths. One method for testing for more subtle defects is known as I DDQ  testing. As described herein, I DDQ  testing looks for high-resistance defects by placing an electric field or potential difference across elements such as wordlines and/or bitlines that are separated by insulators. The current consumed is measured under those electric-field conditions. For example, I DDQ  testing of memory arrays includes connecting alternate wordlines (or bitlines) to the power supply and connecting the remaining wordlines (or bitlines) to ground. Current consumption above a pre-set limit indicates the presence of at least one high-resistance short or other subtle defect that may cause marginal performance or that may later cause a reliability problem. 
     There is a problem caused when performing an I DDQ  test after known low-resistance shorts have been repaired by replacement with redundant rows or columns of cells. That problem is related to the fact that the low-resistance shorts remain in the array even after the redundancy replacement. If a low-resistance defect exists and if that low-resistance defect has been repaired by replacing the affected cells with redundant cells, the only known way to &#34;map out&#34; the low-resistance defect during I DDQ  testing is to test row-by-row or column-by-column, which is prohibitively slow because of the time required to charge the capacitance before measurement of current. On the other hand, if prior-art parallel methods are used to speed up the testing, the high current drawn by the &#34;repaired&#34; defect masks any additional undetected subtle defects, rendering those subtle defects undetectable. 
     In general, I DDQ  testing is not used to find low-resistance shorts because I DDQ  testing, when performed row-by-row, is much slower than using programmed-cell pattern testing described above. 
     A prior-art method for detecting wordline shorts is described in U.S. patent application Ser. No. 08/149,244 filed Oct. 26, 1993, pending, entitled CIRCUIT AND METHOD FOR DETECTING WORDLINE SHORTS IN INTEGRATED CIRCUIT MEMORIES, assigned to Texas Instruments Incorporated. That patent describes detection of the presence or absence of shorts between wordlines with a single measurement for the entire array. The special test circuit and method connect alternate wordlines to reference potential (V REF  or ground) and connect the other alternate wordlines to a common bias-voltage terminal. With the even and odd numbered wordlines biased in this manner, any low-resistance path between wordlines is detected by measuring the current/voltage characteristic at the common terminal. The described procedure provides parallel detection in one reading of a short between any two adjacent wordlines. However, the patent does not disclose a way of determining where that short is located, and does not provide a way of working around the short, if the short has been repaired (two rows of cells replaced). 
     A prior-art bitline short-detection circuit and method is described in U.S. Pat. No. 5,392,246 issued Feb. 21, 1995 entitled CIRCUIT AND METHOD FOR DETECTING COLUMN-LINE SHORTS IN INTEGRATED-CIRCUIT MEMORIES, also assigned to Texas Instruments Incorporated. The short-detection circuit described in that patent includes a special test circuit that, for example, turns off all wordlines; includes a N-channel transistor for each bitline; includes a decoder that uses only the least significant column address for input; and includes a sensor to detect current between shorted conductors. However, that patent does not disclose a way of determining where a short is located, and does not describe a way of working around defects that have been repaired (columns of cells replaced). An advantage of the detection circuit described in that patent is the requirement for a very small number of transistors. The reason is that the detection circuit described in that patent uses only the least significant address as the input for the column decoder. 
     There is a need for a simple method for conducting I DDQ  testing to detect high resistance paths between adjacent, parallel conductors, and to detect other defects, after the row and/or column locations of low-resistance shorts have been determined and after the affected rows and/or columns or such memory cells have been replaced with redundant rows and/or columns of memory cells. After I DDQ  testing, the memory array may be discarded, classified according to quality, or the rows/columns of those cells adversely affected by marginal short circuits may be replaced with other rows/columns of redundant cells. There is also a need for a simple method for testing to detect the number of, and location of, high-resistance shorts and/or low-resistance shorts between adjacent, parallel conductors in integrated circuit memories. 
     SUMMARY OF THE INVENTION 
     This invention is applicable to any type of integrated circuit having rows and columns of conductive elements susceptible to both low-resistance and high-resistance current paths. 
     In a first aspect, this invention includes circuitry that independently disables multiple addresses to the decoding circuitry of a memory array. The circuit for disabling various addresses includes circuitry that, in response to signals indicating that certain addresses shall be &#34;don&#39;t care&#34; rather than &#34;care&#34;, forces the output of appropriate address input and buffering circuitry to a logical &#34;don&#39;t care&#34; condition; and 
     In a second aspect, this invention allows I DDQ  testing of &#34;repaired&#34; memory arrays for the purpose of producing higher-quality memory arrays having improved reliability. That is, this invention permits &#34;working around&#34; known defects in a &#34;repaired&#34; memory array when performing I DDQ  testing. 
     In a third aspect, this invention further detects the existence of, and/or determines the location of, low-resistance current paths and/or high-resistance current paths. 
     During the testing procedure of this invention, the first (circuitry) aspect of this invention selects individual addresses as either &#34;cares&#34; or &#34;don&#39;t cares&#34;. The selected &#34;don&#39;t care&#34; addresses are chosen in a specific manner. The &#34;care&#34; addresses are sequenced in a particular manner that partitions the testing in a way that avoids drawing current through a known defect, thereby detecting only current that is drawn by previously undetected defects. 
     The second aspect, or method for detecting the existence of defects in the presence of other known defects, includes: 
     (a) connecting at least one maximum number of alternate rows of conductors of the array to a first voltage and connecting the maximum number of other alternate rows of conductors of the array to a second voltage different from the first voltage, the maximum numbers being the largest number of rows addressable without addressing one of the known defects; and; 
     (b) repeating step (a) for any equal maximum number of alternate rows of conductors and for the next smaller maximum numbers of alternate rows of conductors and alternate conductors until all of rows of the array except those with defects have been tested. 
     The third aspect, or method for detecting existence and location of defects, includes: 
     (a) connecting all alternate rows of conductors of the array to a first voltage and connecting the other alternate rows of conductors of the array to a second voltage different from the first voltage, while measuring current between the first voltage and second voltage; 
     (b) if the current does not exceed a first limit, ending the process; 
     (c) if the current exceeds the first limit, separately repeating step (a) on first and second halves of the array rather than all of the array, with all of the rows of conductors of the half of the array not under test connected to the second voltage; 
     (d) if the current exceeds a second limit for a half of the array in step (c), repeating step (a) on each quarter of the array in that half with all of the rows of the array not under test connected to the second voltage; and 
     (e) if the current exceeds a third limit for an array quarter in step (d), continuing analogous steps for array fractions divisible by two and for predetermined current limits until sufficient information concerning the defects is determined. 
     In the second and third aspects of this invention, the alternate-row tests may be conducted on large parts of the array in non-adjacent segments, or partitions, such as the upper one-half of each of the upper and lower halves. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is an electrical schematic diagram of an example prior-art row decoder; 
     FIG. 2 is an electrical schematic diagram of the prior-art row decoder of FIG. 1 modified for use with the method of this invention; 
     FIGS. 3(A) and 3(B) illustrate voltages on wordlines of an array with a particular set of addresses applied to the decoder of FIG. 2; and 
     FIGS. 4(A)-4(D) illustrate voltages on wordlines of an array with particular addresses applied to the decoder of FIG. 2 to perform I DDQ  testing on an array with known high-resistance current paths or to determine the type and location of unknown current paths. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The word &#34;row&#34; is hereby defined to include &#34;column&#34; in this detailed description and in the claims following this description. Similarly, any description relating to &#34;wordlines&#34; is understood to relate equally to &#34;bitlines&#34; or &#34;column-lines&#34;. 
     Throughout this document, logic &#34;high&#34; is used to represent a &#34;true&#34; logic signal and logic &#34;low&#34; is used to represent a &#34;false&#34; logic signal. 
     Furthermore, the word &#34;short&#34; is defined to include any defect which may be detected by measuring (undesired) current flow, whether to an adjacent conductor, the semiconductor substrate, or other feature of the circuit. 
     Also, a &#34;care&#34; address is defined to be an address which performs its normal function in subsequent decoding circuitry. A &#34;don&#39;t care&#34; address is defined to be one which has been placed in a state such that subsequent decoding will not be disabled by that address; that is, subsequent decoding operations which match all other relevant addresses will match regardless of the input state of the &#34;don&#39;t care&#34; address. 
     A. First Aspect--Circuitry 
     The first aspect of the invention includes modification of address input or buffering circuitry in order to allow addresses relevant to a particular decoding operation to be placed selectively and independently into a &#34;don&#39;t care&#34; condition in response to control signals. 
     Referring to FIG. 1, a prior-art row decoder RD for a memory array (not shown in FIG. 1) having 2 N  rows, or wordlines WL, selected using input addresses A 0 , A 1 , . . . , A N-1  is illustrated. The row decoder RD is, for example, implemented as NAND gates 10 having outputs coupled to each wordline WL0, WL1, WL2, WL3, . . . , WL2 N  -1. The inputs of NAND gates 10 are coupled as shown through bus BUS to input addresses A 0 , A 1 , . . . , A N-1  and to the complements A 0-- , A 1-- , . . . , A N-1--  of those input addresses A 0 , A 1 , . . . , A N-1 . Each NAND gate 10, when connected in series with an inverter INV, becomes an AND gate. 
     Referring now to FIG. 2, the prior-art decoding circuit RD of FIG. 1 is modified to accomplish the method of this invention. The decoding circuit RD of FIG. 2 is used to detect defects in an integrated-circuit array. As in the circuit of FIG. 1, the decoding of FIG. 2 is coupled to row conductors WL0, WL1, WL2, WL3, . . . , WL2 N  -1 of the array. Also as in the circuit of FIG. 1, the decoding circuit of FIG. 2 is capable of furnishing one of either a high state or a low state at each row conductor WL0, WL1, WL2, WL3, . . . , WL2 N  -1 of the array. The decoding circuit of FIG. 2 includes a plurality of binary address inputs A 0 , A 1 , . . . , A N-1 . Each binary address input comprising a combination of A 0 , A 1 , . . . , A N-1  corresponds to a row conductor WL0, WL1, WL2, WL3, . . . , WL2 N  -1, respectively, of the array. The decoding circuit of FIG. 2 also includes a control signal DC 0-- , DC 1-- , . . . , DC N-1--  corresponding to each binary address input A 0 , A 1 , . . . , A N-1 , respectively. Each binary address input A 0 , A 1 , . . . , A N-1  and each corresponding control signal DC 0-- , DC 1-- , . . . , DC N-1--  is coupled to a logic circuit that forces the row conductor WL0, WL1, WL2, WL3, . . . , WL2 N  -1 corresponding to the particular binary address A 0 , A 1 , . . . , A N-1  to one of a high state or a low state regardless of the corresponding binary address input A 0 , A 1 , . . . . , A N-1 . In the example circuit of FIG. 2, the logic circuit comprises pairs of first and second NAND gates 11, an input of the first NAND circuit 11 coupled to a binary address input, an input of the second NAND gate 11 coupled to the inverse of that binary address input, an input of each of the first and second NAND gate coupled to the corresponding control signal, the outputs of the first and second NAND circuits coupled through bus BUS and an AND circuit 10, INV to the corresponding row conductor WL0, WL1, WL2, WL3, . . . , WL2 N  -1. The control signals DC 0-- , DC 1-- , . . . , DC N-1--  may, for example, be coupled to the logic circuitry from a source external to the integrated-circuit array. In the decoder circuit RD of FIG. 2, a particular input address A, becomes a &#34;don&#39;t care&#34; by forcing both the true address A, and the complement addresses A J--  &#34;high&#34;. 
     In the prior art described in the preceding Background section, one &#34;don&#39;t care&#34; control signal DC J--  is common to all input addresses A J  except the lowest-order row input address A 0 . This results in the alternate-wordlines-high behavior previously described. 
     In FIG. 2, each input address A J  is individually capable of being made a &#34;don&#39;t care&#34;. This may be accomplished by defining &#34;don&#39;t care&#34; signals DC 0-- , . . . , DC N-1--  as a bus and, for example, deriving them from a source such as a bank of latches, or from a bank of high-voltage sensors attached to each input address A J  pin, respectively. 
     In the example of FIGS. 3(A) and 3(B), input addresses A 1 , . . . , A N-2  to array ARR are made &#34;don&#39;t care&#34; by low signals DC 1-- , . . . , DC N-2   -- , respectively, and only input addresses A 0  and A N-1  are made &#34;cares&#34; by high signals DC 0--  and DC N-1-- , respectively. This results in alternate wordlines high behavior, but only in the half of the array selected by address A N-1 . As discussed below in relation to the second aspect of the invention, if the array is known to have low-resistance short(s) in one half only and the test is for high-resistance shorts only, this step in the I DDQ  test for that half the array may be skipped. The I DDQ  test for the remaining part of that half is performed during later steps. 
     Referring to FIGS. 4(A)-(D), representative wordlines ROW in array ARR are illustrated with A N-2 , A N-1  and A 0  made &#34;cares&#34; by high signals DC N-2-- , DC N-1--  and DC 0-- , respectively. Addresses A 1 , . . . , A N-3  are made &#34;don&#39;t cares&#34; by low signals DC 1-- , . . . , DC N-3-- , respectively. This results in alternate rows high in the quadrant selected by addresses A N-2  and A N-1 , and all rows low in the remaining three quadrants. As discussed below in relation to the second aspect of this invention, any quadrants not containing the short(s) found in the bias configuration of FIGS. 3(A) and 3(B) are tested for I DDQ . Of course, if either half of the array ARR was found to be free of shorts during the first step, it is not necessary to test those quadrants again. However, those quadrants may be included for convenience without jeopardizing subsequent tests by making A N-1  a &#34;don&#39;t care&#34; signal. It is, of course, understood that the bias arrangement of FIGS. 4(A)-(D) does not apply if quadrants are tested again by making, for example, A N-1  a &#34;don&#39;t care&#34; signal. 
     B. Second Aspect--I DDQ  Testing 
     Note that generally the number of low-resistance shorts is small because of the limited number of redundant cells. Therefore, in the test relating to FIGS. 3(A) and 3(B), the time-consuming I DDQ  test is performed over a large part of the array even though shorted cells have been replaced by redundant cells. 
     Because a non-defective CMOS memory array draws very little current, the current drawn from the power supply during the test of this invention is a measure of current leakage. The method of this invention requires that criteria in the form of one or more test current limits be established. If the test is used to find high-resistance shorts, the current limits are relatively low. The current limits may vary depending on the number of wordlines energized, using a higher current limit where conductors are alternately-charged over the entire array, using lower current limits where fractions of the array have conductors at the same voltage. The current may be measured with no wordlines energized to determine actual junction leakage current, which may be added to the leakage current limits used herein. If the test is used to locate defective diffusions, the current limits may have a value determined by excessive current drawn by those defective diffusions. 
     The second aspect of the invention includes using the address input and buffering circuitry of the first aspect to test an array with known defects for additional high-resistance (low-current-consuming-) defects by avoiding current flow through the known defects. (If there are no known defects replaced by redundant elements, then the prior-art testing using alternate wordline or bitlines is sufficient.) Typically, known defects have been replaced by redundant elements. If prior-art parallel methods are used to test an array with replaced defects, the high current drawn by the &#34;repaired&#34; defect masks any additional high-resistance, or subtle defects, rendering those subtle defects undetectable. On the other hand, if I DDQ  testing is performed row-by-row or column-by-column to &#34;map out&#34; the repaired defect, the test time is prohibitively long because of the time required to charge the capacitance before measurement of current. 
     The method for detecting the existence of defects in the presence of other known defects includes: 
     (a) connecting at least one maximum number of alternate rows of conductors of the array to a first voltage and connecting the maximum number of other alternate rows of conductors of the array to a second voltage different from the first voltage, the maximum numbers being the largest number of rows addressable without addressing one of the known defects; and 
     (b) repeating step (a) for any equal maximum number of alternate rows of conductors and for the next smaller maximum numbers of alternate rows of conductors and alternate conductors until all of the rows of the array except those with defects have been tested. (This step may include additional groups of the smaller maximum numbers of alternate rows that may have already been tested.) 
     The maximum number of alternate rows of conductors is defined by the connections of the address signals A 0 , A 1 , . . . , A N-1  to wordlines WL0, WL1, WL2, WL3, . . . , WL2 N  -1. 
     For example, if an array has a single known defect and has N addresses numbered A 0  to A N-1 , 2 N  rows, an I DDQ  test may be performed using the following steps: 
     (1) Select A N-1  and A 0  to be &#34;care&#34; addresses, and the remainder of the addresses to be &#34;don&#39;t care&#34;. 
     (a) If the known defect is in the array half addressed by A N-1  =1, then set A N-1  =0 and test I DDQ  with either A 0  =0 or A 0  =1 or both, as desired. 
     (b) If the known defect is in the array half addressed by A N-1  =0, then set A N-1  =1 and test I DDQ  with either A 0  =0 or A 0  =1 or both, as desired. 
     (c) If the known defect is on the boundary between array halves that are divided by A N-1 , then first set A N-1  =A 0  =0 and test for I DDQ , followed by a similar I DDQ  test with A N-1  =A 0  =1. 
     (2) For each address from A N-2  to A 1  in turn, select one address in addition to A 0  to be a &#34;care&#34;, and the remaining addresses to be &#34;don&#39;t cares&#34;. Repeat step (1) substituting the selected address for A N-1 . Note that &#34;array half addressed by A N-1  &#34; will become &#34;an array quadrant addressed by A N-1  and A N-2 , (or two quadrants addressed by A N-2 , if the test includes previously tested quadrants)&#34;, &#34;an array octant addressed by A N-1 , A N-2  and A N-3  (or four array octants addressed by A N-3 , if the test includes octants that have been previously tested)&#34;, etc. 
     If an array has two known defects and has N addresses numbered A 0  to A N-1 , 2 N  rows, an I DDQ  test may be performed using the following steps: 
     (1) From the addresses A n-1  through A 1 , select an address that distinguishes between the two known defects. That is, select an address A K  such that A K  =0 to address one of the defects and A K  =1 to address the other defect. 
     (2) Select A K  to be a &#34;care&#34; address. If A K  is not A N-1 , then also select A N-1  and A 0  to be &#34;care&#34; addresses, and the remainder of the addresses to be &#34;don&#39;t care&#34;. If A K  is A N-1  , then begin with A N-2  and A 0  as the &#34;care&#34; addresses in addition to A K . 
     (a) Select A K  =0 and perform the following steps: 
     (i) If the known defect addressed by A K  =0 is in the array half addressed by A N-1  =1, then set A N-1  =0 and test I DDQ  with either A 0  =0 or A 0  =1 or both, as desired. 
     (ii) If the known defect addressed by A K  =0 is in the array half addressed by A N-1  =0, then set A N-1  =1 and test I DDQ  with either A 0  =0 or A 0  =1 or both, as desired. 
     (iii) If the known defect addressed by A K  =0 is on the boundary between array halves that are divided by A N-1 , then first set A N-1  =A 0  =0 and test for I DDQ  followed by a similar I DDQ  test with A N-1  =A 0  =1. 
     (b) Select A K  =1 and perform the following steps: 
     (i) If the known defect addressed by A K  =1 is in the array half addressed by A N-1  =1, then set A N-1  =0 and test I DDQ  with either A 0  =0 or A 0  =1 or both, as desired. 
     (ii) If the known defect addressed by A K  =1 is in the array half addressed by A N-1  =0, then set A N-1  =1 and test I DDQ  with either A 0  =0 or A 0  =1 or both, as desired. 
     (iii) If the known defect addressed by A K  =1 is on the boundary between array halves that are divided by A N-1 , then first set A N-1  =A 0  =0 and test for I DDQ , followed by a similar I DDQ  test with A N-1  =A 0  =1. 
     (3) For each address from A N-2  to A 1  in turn except A K , select one address in addition to A 0  and A K  to be a &#34;care&#34;, and the remaining addresses to be &#34;don&#39;t cares&#34;. Repeat step 
     (2) substituting the selected address for A N-1 . 
     Again, the maximum number of alternate rows of conductors is defined by the connections of the address signals A 0 , A 1 , . . . , A N-1  to wordlines WL0, WL1, WL2, WL3, . . . , WL2 N  -1. 
     If an array has two known defects and has N addresses numbered A 0  to A N-1 , 2 N  rows, an I DDQ  test may, alternatively, be performed using the following steps: 
     (1) Select A N-1  and A 0  to be care addresses. If neither known defect is in the half of the array in which A N-1  =0, and there also is no known defect at the boundary between the two half-arrays, then test that half of the array, with A N-1  =0 and A 0  =1. If there is a known defect at the boundary, then instead use A N-1  =A 0  =0. 
     (2) If neither known defect is in the half with A N-1  =1, and there also is no known defect at the boundary between the two half-arrays, then test that half, with A N-1  =1 and A 0  =0. If there is a known defect at the boundary, then instead use A N-1  =A 0  =1. 
     (3) If, there is one known short for one state of A N-1  and the other bridges the boundary between the two half arrays selected by A N-1 , then there is one state of A N-1  for which there is one known defect. The other half has no known defect and has already been tested. To test the half that has not yet been tested, and has one known short, take A N-1  to the state that selects that half array. Also, set A 0  =A N-1 . Now, test this half-array exactly as for the case of one known short, since this half-array is, in fact, equivalent to a full array with one known short. That is, start with A N-2  and A 0  (in addition to A N-1 ) as cares. Then use A N-3  and A 0  (plus, of course, A N-1 ) , and after that A n-4  and A 0  (plus A N-1 ), etc. 
     (4) If, however, there is one known defect for each state of A N-1 , then: 
     (a) With A N-1  =0, test this half of the array exactly as is done for the case of one known short, using addresses A N-2  through A 0 . That is, start with A N-2  and A 0  (in addition to A N-1 , which is being held low) as cares, and then use A N-3  and A 0 , and then A N-4  and A 0 , etc. 
     (b) Repeat the above, but now with A N-1  =1. 
     (5) If there is one state of A N-1  that contains both known defects, then ignore A N-1  completely, and decrement N, so that what was A N-2  now is called A N-1 . Now, go to Step (1). 
     Again, the maximum number of alternate rows of conductors is defined by the connections of the address signals A 0 , A 1 , . . . , A N-1  to wordlines WL0, WL1, WL2, WL3, . . . , WL2 N  -1. 
     If an array has M known defects and has N addresses numbered A 0  to A N-1 , 2 N  rows, an I DDQ  test may be performed by extending the above procedure to allow for M &#34;care&#34; addresses in addition to A 0 . M-1 of the &#34;care&#34; addresses are used to distinguish between the multiple defects, and A 0  and the remaining &#34;care&#34; address are employed in the method of the case with only one known defect to test the array. In certain special cases fewer than M-1 &#34;care&#34; addresses may distinguish between M defects; however, in the general case M-1 &#34;care&#34; addresses are required. 
     C. Third Aspect--Detecting Type and Location of Defects 
     Again, because a non-defective CMOS memory array draws very little current, the current drawn from the power supply during the test of this invention is a measure of current leakage. The method of this invention requires that criteria in the form of one or more test current limits be established. If the test is used to find high-resistance shorts, the current limits are relatively low. If the test is used to find low-resistance shorts, the current limits are relatively high. In either case, the current limits may vary depending on the number of wordlines energized, using a higher current limit where conductors are alternately-charged over the entire array, using lower current limits where fractions of the array have conductors at the same voltage. The current may be measured with no wordlines energized to determine actual junction leakage current, which may be added to the leakage current limits used herein. 
     In the third aspect of the invention, the address input and buffering circuitry referred to in the above discussion of the first aspect above is used to determine the number and location of defects within an array with N address inputs numbered A 0  to A N-1  and 2 N  rows, provided the number of defects does not exceed N-2, by performing the following steps: 
     (1) Select A 0  as a &#34;care&#34; address, select the remaining addresses as &#34;don&#39;t care&#34;, and measure the current. 
     (a) If the current does not exceed a predetermined limit, there are no defects in the array and testing ceases. 
     (b) If the current exceeds a predetermined limit, there is at least one defect in the array. 
     (2) Select A N-1  and A 0  to be &#34;care&#34; addresses, and the remainder of the addresses to be &#34;don&#39;t care&#34;. 
     (a) Select A N-1  =A 0  =0 and measure the current. If the current exceeds a predetermined limit, there is at least one defect in the array half addressed by A N-1  =0. 
     (b) Select A N-1  =A 0  =1 and measure the current. If the current exceeds a predetermined limit, there is at least one defect in the array half addressed by A N-1  =1. 
     (c) If the current in neither (a) nor (b) exceeds the predetermined current limit, then select the remaining two logical combinations of A N-1  and A 0  and measure the current for each. One of these two combinations should exceed the current limit indicating either a defect in the exact center between the halves addressed by A N-1  =0 and A N-1  =1 or a rectifying-type defect in one half of the array. If the testing procedure is concerned with rectifying-type shorts between wordlines, then adjacent wordlines must be energized in opposite directions. One procedure for testing for rectifying-type shorts is to apply voltages as follows. For example, if A N-1  is a care address, choose A 0  =A N-1 . Otherwise, choose A 0  to be the opposite state as the most-significant care-address. In fact, in some cases where there are two or more care addresses (plus A 0 ), the state of A 0  would not matter, because the boundary between the upper and lower half arrays is far from any biased wordlines. 
     (d) If only one of (a) and (b) draws excessive current, then all potential defects must have the same state of A N-1  in their address; note this state and allow A N-1  to be either this state or &#34;don&#39;t care&#34; for the remainder of the testing. 
     (e) If both (a) and (b) drew excessive current, then there are at least two defects and they are in separate halves of the array as divided by A N-1 . It is then necessary for A N-1  to remain a &#34;care&#34; address for the remainder of the testing. Perform the following steps twice, one time for A N-1  =0 and one time for A N-1  =1. 
     (3) For each address from A N-2  to A 1  in turn, select one address to be a &#34;care&#34; in addition to A 0  and possibly higher order addresses determined in the previous step(s) as mandatory &#34;cares&#34;. Select the remaining addresses to be &#34;don&#39;t cares&#34;. Repeat step (2) substituting the selected address for A N-1 . As each address from A N-2  to A 1  is considered in turn note each address state that addresses a defect, as well as addresses that become mandatory &#34;cares&#34; in succeeding steps. 
     When all addresses have been used, information is sufficient to locate all defects. 
     As stated previously, the concepts are described in relation to wordlines or rows, but are equally applicable to columns, provided a type of power-supply-derived bias (high) is applied to alternating columns. It is also possible to apply these concepts to other logic circuits having sufficiently regular arrays, provided that the logic circuits are decoded in a suitable way and that the logic circuits make use of selective disablement or redundant circuit substitution. 
     While the invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is, therefore, contemplated that the appended claims will cover any such modifications or embodiments that fall within the true scope of the invention.