Abstract:
A clock recovery circuit includes a sampling phase detector and frequency detector. The sample values generated in the phase detection portion of the clock recovery circuit and applied as inputs to the frequency detector to allow for frequency “cycle slips” to be detected and corrected without requiring the use of a separate circuit.

Description:
TECHNICAL FIELD 
     The present invention relates to a clock recovery circuit and, more particularly, to clock recovery circuit comprising a self-aligned proportional phase detector (SAPPD) including an integral frequency detection. 
     BACKGROUND OF THE INVENTION 
     Clock recovery circuits are employed within optical and RF receivers to establish synchronization between a locally generated clock and the timing of a bit stream within a received data signal. The local clock, once synchronized to the incoming data signal, is used to control regeneration of the data. In most cases, a phase-locked loop (PLL) circuit is used to provide clock recovery. 
     A phase locked loop (PLL) is a system that uses feedback to maintain an output signal in a specific phase relationship with a reference signal. PLLs are used in many areas of electronics to control the frequency and/or phase of a signal. These applications include frequency synthesizers, analog and digital modulators and demodulators, and clock recovery circuits. 
     A typical prior art PLL includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector produces an output voltage that is proportional to the phase difference between an input signal and the output of the VCO. The loop filter integrates the output of the phase detector and creates a VCO control signal. The VCO produces an ac output signal having a frequency that is proportional to the VCO control voltage. 
     With conventional phase locked loops, difficulties are presented when attempting to phase lock to high frequency input signals. For example, the synchronous optical network (SONET) standard specifies that a 622 MHz PLL should have a loop bandwidth of between 250-500 kHz. Unfortunately, a standard PLL can only “pull-in” an input signal that is within about a loop bandwidth of the nominal frequency. In the above example, this means that a SONET standard PLL has a “pull in” range of about ±0.04% to about ±0.08%. Techniques for extending the frequency lock range of a PLL circuit based on sampled phase detectors utilize a square wave as an auxiliary input to initially tune the VCO, while using an additional phase and frequency detector (PFD) to compare the frequency of the auxiliary input to the VCO output. Once the VCO is tuned to the desired frequency in this manner, the additional PFD is switched out of the PLL feedback loop and the sampled phase detector is utilized to phase lock onto the incoming data. However, relying on the presence of an external reference signal (such as a square wave) to extend the frequency lock range may not be practical in many receiver applications where the only received signal is the incoming random data. 
     A problem exists, however, for a PLL circuit that utilizes a sampled phase detector. Specifically, for large frequency errors, conventional sampled phase detectors are equally likely to generate a positive or negative phase correction signal, regardless of the actual polarity of the frequency error, since the likelihood of sampling before and after a data edge (due to the frequency error) is fifty percent (50%). Thus, it is necessary to ensure that large frequency errors do not occur by extending the frequency lock range of a PLL circuit. 
     Thus, a need remains in the art for any arrangement for providing the desired frequency detection within a clock recovery circuit utilizing a sampled phase detector without the need for a separate frequency detection circuit. 
     SUMMARY OF THE INVENTION 
     The need remaining in the prior art is addressed by the present invention, which relates to a clock recovery circuit and, more particularly, to a clock recovery circuit comprising a self-aligned proportional phase detector (SAPPD) including an integral frequency detection. 
     In accordance with the present invention, the data sample outputs generated by the SAPPD are used as inputs to a frequency detection circuit. The clock signals are used to form a pair of quadrature clock signals at a subclock frequency of f 1 -f 2 , thus defining four quadrants in a cycle of the subclock frequency. A “cycle slip” is then determined based on the data samples, and the frequency adjusted on an UP/DOWN basis, depending upon in the quadrant in which the cycle slip occurs. 
     Other and further aspects and features of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Referring now to the drawings, 
     FIG. 1 a prior art clock recovery circuit including a sampling phase detector; 
     FIG. 2 contains an illustrative eye pattern for the data input signal associated with the recovery circuit of FIG. 1; 
     FIG. 3 is a plot of the mean phase detector output PD(t) as a function of data phase φ; 
     FIG. 4 illustrates an alternative sawtooth phase detector output; 
     FIG. 5 illustrates an exemplary clock recovery circuit including a phase detector providing various output signals that may be used to provide frequency detection in accordance with the present invention; 
     FIG. 6 is a timing diagram of the relation between “early” and “late” data signals and clock signals that may be used to derive frequency “slip” detection in accordance with the present invention; 
     FIG. 7 illustrates an exemplary transition locator circuit of the frequency detection arrangement of the present invention; 
     FIG. 8 contains a timing diagram of the various signals generated in the transition locator circuit of FIG. 7; 
     FIG. 9 contains a diagram illustrating the principle frequency cycle slip in accordance with the present invention; 
     FIG. 10 illustrates an exemplary frequency cycle slip detector formed in accordance with the present invention; and 
     FIG. 11 is a block diagram of a clock recovery circuit providing both phase detection and frequency detection in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     In order to fully understand and appreciate the frequency detection capability of the present invention, it is useful to review the workings of a prior art clock recovery circuit based on a sampling phase detector, as well as a self-aligned proportional phase detector. 
     Referring to FIG. 1, a prior art clock recovery circuit  10  includes a sampling phase detector  12  responsive to an input data signal (“DATA IN ”), a loop filter  14  and a voltage-controlled oscillator (VCO)  16  that provides a recovered clock output based on DATA IN . Clock recovery circuit  10  functions to synchronize the VCO clock output with the symbol-to-symbol timing of DATA IN . Phase detector  12  is comprised of four sampling circuits (e.g., D-type flip-flops) D 1 -D 4 , a pair of exclusive OR gates XOR 1 ,XOR 2  and a subtractor  18  which is used to subtract the output of XOR 1  from the output of XOR 2 . Phase detector  12  is known in the art as the “Alexander” phase detector and is widely used in conventional high-speed clock recovery circuits, and is fully described in an article entitled “Clock Recovery from Random Binary Signals” by J. D. H. Alexander, appearing in  Electronics Letters , Vol. 21, pp. 541-2, 1975. 
     In operation, a data signal to be regenerated (DATA IN ) is received at the D inputs of sampling circuits D 1  and D 3 . The data signal is typically a bit stream of non-return-to-zero (NRZ) data. Sampling circuits D 1 -D 4  may each be embodied as a simple clocked D-type flip-flop, preferably including an internal comparator at the D input of the flip-flop. The comparator is used to compare the amplitude of the input signal at the clocked sampling instant to a decision threshold to determine if the sample is closer to a logic “0” or a logic “1”. The logic level at the input of sampling circuits D 1  and D 3  is transferred to the Q output and held there until the next clock cycle transition (positive transition for circuits D 1 , D 2  and D 4 , a negative transition for D 3 ) appears at the clock input port. Without the internal comparator in the D 1  and D 3  circuits, a typical clocked D flip-flop would provide an indeterminate output for data signal levels at the zero-crossings between bits. 
     FIG. 2 shows an illustrative eye pattern for the input data signal in relation to an aligned VCO clock output. Sampling points A and C on the eye pattern represent the midpoints of two consecutive bits of the data signal. Data samples will be taken at these points if the clock is precisely aligned with the data timing. Sample point B is at the crossover point (zero crossing) between successive bits if the clock is perfectly aligned. Therefore, if there is no data transition between consecutive sampling points A and C (i.e., if the A and C samples are at the same logic level), then the B sample is at the same logic level as the A and C samples. If there is a data transition and the clock is slightly early, the B sample is taken prior to the crossover time and will thus equal the logic level of the A sample. Conversely, if the clock is slightly late during a data transition, the B sample will equal the logic level of the C sample. 
     Referring still to FIGS. 1 and 2, sampling circuits D 1 , D 2  and D 4  are clocked together by the clock output of VCO  16  and sample the D input at the leading edge of the clock pulse. Sampling circuit D 3  samples the D input at the trailing edge of the clock. Since the output Q 1  of sampling circuit D 1  is applied as the D input to sampling circuit D 2 , and the output Q 3  of D 3  sampling circuit D 4 , sampling circuit D 1  stores the most recent bit (i.e., bit C); sampling circuit D 2  stores the previous bit (i.e., bit A); and D 4  stores the crossing point sample (i.e., bit B). That is, the local level of the zero crossing sample B appears at output Q 4  of circuit D 4  at the same time that logic levels of samples A and C appear on outputs Q 2  and Q 1 , respectively. 
     By comparing the value of Q 4  with the values of Q 1  and Q 2 , it can be determined whether the clock is “early” or “late” as follows: 
     
       
         If A=B≠C, then clock is “early” (E) 
       
     
     
       
         If A≠B=C, then clock is “late” (L) 
       
     
     
       
         If A=B=C., or A=C≠B, then no decision is possible. 
       
     
     These four conditions are detected by applying the B and C samples to exclusive OR gates XOR 1  applying the A and B samples to gate XOR 2 , and then subtracting the output of XOR 1  from XOR 2  using analog subtractor  18 . The following truth table depicts the detection conditions: 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
               
               
                   
                   
                   
                 A ⊕ B 
                 B ⊕ C 
                   
                 A ⊕ B − B ⊕ C 
               
               
                 A 
                 B 
                 C 
                 XOR2 
                 XOR1 
                 Decision 
                 PD(t) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 0 
                 0 
                 0 
                 0 
                 0 
                 X 
                 0 
               
               
                 0 
                 0 
                 1 
                 0 
                 1 
                 Early 
                 −1 
               
               
                 0 
                 1 
                 0 
                 1 
                 1 
                 X 
                 0 
               
               
                 0 
                 1 
                 1 
                 1 
                 0 
                 Late 
                 1 
               
               
                 1 
                 0 
                 0 
                 1 
                 0 
                 Late 
                 1 
               
               
                 1 
                 0 
                 1 
                 1 
                 1 
                 X 
                 0 
               
               
                 1 
                 1 
                 0 
                 0 
                 1 
                 Early 
                 −1 
               
               
                 1 
                 1 
                 1 
                 0 
                 0 
                 X 
                 0 
               
               
                   
               
             
          
         
       
     
     In the truth table, the quantity A⊕B represents the output of XOR 2 , B⊕C represents the output of XOR 1  and A⊕B-B⊕C represents the phase detector output, denoted PD(t). As shown by this truth table, if the clock is late, PD(t) will vary between zero volts and the logic high value (e.g., +5V), depending on whether or not a data transition has occurred. If the clock is early, PD(t) will vary between zero volts and the negative value of the logic high voltage (e.g., −5V). Whether the clock is early or late, the average value of PD(t) over a relatively short time interval will depend on the data transition density, i.e., the number of transitions between logic 1&#39;s and logic 0&#39;s within a certain time interval. More specifically, if the function A(t) describes the average data transition density, the mean phase detector output PD(t) can be expressed as: 
     
       
         PD(t)=A(t)sign(φ). 
       
     
     where “sign” denotes the signum function and φ is the data phase, i.e., the phase difference between the symbol timing of the data signal and the VCO clock signal. 
     Referring to FIG. 3, the mean phase detector output PD(t) is plotted as a function of data phase φ. A late clock corresponds to the data phase in the range of 0 to π, 2π to 3π, etc. In this case, PD(t) equals the positive voltage +A(t), which is applied to VCO  16  through loop filter  14  to speed up the VCO output clock frequency towards clock alignment with the input data signal. When the clock is early (i.e., data phase in the range of −π to 0, π to 2π, etc.) PD(t) falls to −A(t). This negative voltage operates to slow the VCO clock frequency towards clock alignment. In this manner, the clock becomes self-aligned with the data signal. 
     While the “Alexander” phase detector has desirable self-aligning properties, it exhibits several drawbacks. First, the mean phase detector output over a given time interval PD(t) is not proportional to the magnitude of the data phase. Rather, the output is a discrete function (i.e., the signum function), as seen in FIG.  3 . That is, the function PD(t) will take on only one of two values regardless of the amount of clock misalignment (for a given data transition density). This property is unlike that of a linear analog phase detector such as the sawtooth phase detector. As shown in FIG. 4, the output of a sawtooth phase detector is proportional the phase error of the clock. By contrast, the Alexander phase shifter lacks such a proportional output and thus the dynamic properties (e.g., jitter transfer, jitter tolerance) are highly dependent on the jitter distribution of the data edges, in terms of amplitude as well as frequency. 
     Since the Alexander phase detector detects phase information only at the zero crossings, the result is a discrete output with limited phase error information. In contrast, it has been found that by deriving phase information at additional times besides the zero crossing, a phase detector output that is substantially proportional to the local clock phase can be produced with the attendant advantages - superior phase jitter performance as well as frequency detection capability. 
     A clock recovery circuit  20  that is also capable of providing frequency detection in accordance with the present invention is illustrated in FIG.  5 . Clock recovery circuit  20  utilizes a modified phase detector  22 , utilizing both a recovered clock signal CK 1  and a second clock signal CK 2 , where second clock CK 2  is used to generate intermediate samples (i.e., B) at times other than the zero-crossings. Similar to the arrangement discussed above, flip-flops D 1  and D 2  are controlled by first clock CK 1  and used to generate data samples A and C. Flip-flop D 3  is clocked by the second clock signal CK 2  and is used to “over sample” DATA IN  at instances other than the zero-crossing. Output Q 3  from D 3  is then applied as an input to flip-flop D 4 , which re-times this “roving” sample with clock CK 1 , as shown. Similar to the Alexander phase detector, gates XOR 1  and XOR 2  are used to determine if clock CK 1  is “early” or “late”. based on the values of A, B and C. In contrast to the Alexander phase detector, second clock CK 2  may be derived from CK 1  by modulating the phase of the latter with a periodic signal, rather than using a “binary” decision. The resulting phase detector output PD(t) is therefore a proportional function of phase, as opposed to a signum function. 
     The frequency detection potential of this arrangement, in accordance with the teachings of the present invention, is illustrated in the timing diagram of FIG.  6 . As shown, the signal that modulates CK 2  is assumed to be a sawtooth function, ramping from a phase of −π to +π. It is to be noted that the phase of CK 2  with respect to CK 1  is monotonically decreasing at a constant rate. In effect, CK 2  has a constant frequency offset with respect to CK 1 . Although it is not essential for the operation of the frequency detector of the present invention, clock CK 2  is most likely easier to implement as a separately-generated clock of a frequency f 2  than as a phase-modulated version of CK 1  operating at a frequency of f 1 . Also, whether f 1 &gt;f 2  or f 2 &gt;f 1  is not essential. For the purposes of the present discussion, it will be assumed that f 1 &gt;f 2 . 
     The eye diagram of FIG. 6 shows the data samples, using the time base of CK 1  as a reference. The eye is moving left or right, depending on the data rate f B  being either greater (i.e., clock “slow”) or less than (i.e., clock “fast”) the frequency f 1  of CK 1 . As shown, sample B is moving right at a rate of f 1 -f 2 . The phase difference φ 12  (t) between CK 1  and CK 2  is shown on the vertical time scale (denoted time′). As long as data sample B is between A and the data transition (denoted as “DT” in FIG.  6 ), XOR 1  will put out “down” transition pulses A(t), indicating that the clock is early, and the output of XOR 2  will stay at zero. When sample B is between the data transition and sample C, the output of XOR 1  stays zero and XOR 2  outputs “up” transition pulses A(t), indicating that the clock is “late”. Therefore, as the data transitions moves left (i.e., clock is “slow”), the number of “down” pulses from XOR 1  will diminish and the number of “up” pulses from XOR 2  will increase linearly with the relative phase of the data transition. Thus, in accordance with the present invention, this arrangement forms a sawtooth phase detector curve with a full 2π range. 
     FIG. 7 illustrates a transition locator circuit  30  of the present invention that is capable of determining the position of sample B with respect to the data transition, as required to perform the frequency detection function of the present invention. CK 1  is used as the clocking input to a pair of flip-flips  32  and  34 , with CK 2  applied as the data input to flip-flop  32  and the quadrature of CK 2  (denoted CK 2 Q) applied as the data input to flip-flop  34 . The output of flip-flop  32  (and its inverse) are both applied as inputs to a first XOR gate  36  and provide a first quadrature subclock S 12  that generates two pulses during the clocking system. Similarly, the output of flip-flop  34  (and its inverse) are applied as inputs to a second XOR gate  38  to generate a remaining pair of subclock pulses S  12 Q that are in quadrature to the pulses from first XOR gate  36 . Combining these pulses in a NAND gate  40  yields a train of four subclock pulses, denoted S 12 T, related to the original clock CK 1 . In accordance with the present invention, pulses S 12 T are used at the beginning of each quadrant, to clear out previous “early” and “late” values and help in determining the “cycle” slip between quadrants. In particular, subclock S 12 T is provided as the clock input to a flip-flop  42 . A first input to flip-flop  42  is held at the logic “1” level, and the remaining input is (an inverted version of) the output of XOR 2  of clock recovery circuit  20 . As discussed above, the output of XOR 2  is the combination of data samples B and C, and when this output has the logic “1” value, indicates that the data is “early” with respect to the clock. In transition circuit  30 , therefore, when there is a “1” present at this input, it will be passed to the output of flip-flop  42  at the beginning of the next subclock quadrant pulse (i.e., at the next pulse of S 12 T). This pulse is inverted so that a falling edge is generated and passed through to the output. The falling edge output from flip-flop  42  is then applied as an input to a following flip-flop  44 , also clocked by subclock S 12 T. As shown, the remaining input to flip-flop  44  is the output of XOR 1  which indicates the presence of a “late” sample with respect to the clock. A pair of inverters  46 ,  48  are included in this signal path to insure that this pulse arrives at flip-flop  44  after the falling edge output from flip-flop  42  has been generated. The output of second flip-flop  44 , denoted as pulse X, which starts with the first late pulse to arrive at the beginning of a quadrant (as defined by subclock S 12 T) and ends at the start of the next quadrant, when both flip-flops  42 , 44  are cleared. Therefore, both the “early” and “late” pulses are always associated with the same quadrant. 
     FIG. 8 is a timing diagram illustrating the various pulses S 12 , S 12 Q, E, L and X as formed in transition detection circuit  30  of FIG.  7 . Defining four quadrants in the clock cycle as Q 1 -Q 4 , S 12 T is shown as supplying a short pulse at the beginning of each quadrant. In the particular example as illustrated in FIG. 8, a “first” late transition occurs in quadrant Q 3 , which initiates pulse X, where X will then a positive value for the duration of this third quadrant. In accordance with the present invention, a cycle slip is defined as occurring when a data transition moves between two adjacent quadrants. FIG. 9 is a simple diagram of “cycle slip” that may be understood with reference to FIG.  8 . In particular, each quadrant of the clock cycle will be associated with a unique pair of subclock signals. For this particular arrangement, quadrant Q 1  is associated with subclock values S 12 =1, S 12 Q=0. Similarly quadrant Q 2  is associated with S 12 =1, S 12 Q=1; quadrant Q 3  is associated with S 12 =0, S 12 Q=1; and quadrant Q 4  is associated with S 12 =0, S 12 Q=0. The combinational logic described below in association with FIG. 10 can then be used to generate an “up” pulse (indicating a positive cycle slip) when a transition from Q 3  to Q 2  occurs and generate a “down” pulse (indicating a negative cycle slip) when a transition from Q 4  to Q 1  occurs, where the “up” and “down” pulses are used as error correction signals for the clock recovery circuit. 
     A cycle slip detector  50 , as shown in FIG. 10, uses the timing of the X pulses with respect to subclock S 12 T to determine the position of the data transition with respect to clock CK 1 . Defined as a rotational frequency detector, pulse stream X is supplied as the clocking input to a set of flip-flops  52 ,  54 ,  56  and  58 . Subclock S 12 Q is applied as the D input to first flip-flop  52 , and forms the first quadrant output Q 1 . This output then passes through second flip-flop  54  to form the third quadrant output Q 3  (as controlled by the clocking rate of pulse stream X). Subclock S 12  is similarly applied as the D input to flip-flop  56  to form second quadrant output Q 2 , where the fourth quadrant output Q 4 , follows as the output of flip-flop  58 . Inverted values of Q 1 , Q 2 , and Q 3  are combined with Q 4  in a first gate  60  and used to indicate a “positive” cycle and the need to increase the frequency, as described above. A second gate  62 , responsive to inverted values of Q 1 , Q 3 , Q 4  and the value of Q 2  is used to generate a “down” frequency slip signal. 
     FIG. 11 illustrates an exemplary self-aligned clock recovery circuit  70  of the present invention, showing in block diagram form the various components described in detail above, namely, phase detector  22 , transition detector  30  and cycle slip detector  50 . As shown, the final frequency slip pulses “up” and “down” from cycle slip detector  50  are fed back to an adder  72  to be combined with the output from phase detector  22  as shown. Thus, the arrangement as shown in FIG. 11 is capable of providing frequency detection within a phase detector circuit arrangement. 
     While the present invention has been described above with reference to specific embodiments thereof, it is understood that one skilled in the art may make many modifications to the disclosed embodiments without departing from the spirit and scope of the invention. For example, while the illustrative embodiment is designed to receive an input data signal comprise of a bit stream (binary data), it may be modified to enable synchronization with an input data signal having a non-binary symbol stream. As another example, the various logic circuits within the phase detector, transition detector and cycle slip detector may be formed of alternative combinations of logic gates, as long as the proper combinational logic is provided. Accordingly, these and other modifications are intended to be included within the spirit and scope of the present invention as defined by the claims appended hereto.