Abstract:
With a housing for accommodating a planar power transistor, a chip of the power transistor is arranged hermetically sealed inside the housing, and metallized areas on the chip lead out of the housing by way of electric terminals. At least in some areas, the housing is formed by at least one of the electric power terminals.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a housing for accommodating a planar power transistor having the features characterized in planar power transistor. 
     BACKGROUND INFORMATION 
     It is conventional for power transistors to be arranged hermetically sealed in housings. Planar power transistors have a chip where the functionally doped zones can be contacted by metallized areas. The metallized areas are connected to electric terminals that lead out of the housing for linking the power transistor to a circuit arrangement. Power transistors have three terminals that function as a gate electrode and for connecting to a positive voltage potential and a negative voltage potential. 
     German Published Patent Application No. 43 27 309 describes that a power. transistor can be arranged in a power transistor package, with the power transistor being arranged in a cast plastic housing, which is electrically insulated. One disadvantage here is that there must be optimum dissipation of the heat generated due to power loss in the power transistor through the plastic housing and/or the relatively small electric terminals. Thus, there are considerable limits to the dissipation of the power loss heat. 
     SUMMARY OF THE INVENTION 
     The housing according to the present invention, offers the advantage that it permits optimum dissipation of power loss heat generated by a chip in the power transistor. Due to the fact that the housing is formed at least in some areas by at least one of the electric terminals, it is advantageously possible to provide large-area contact over which heat can be dissipated. In addition, the at least one of the electric terminals forming part of the housing may be used to advantage at the same time for assembly of the entire power transistor. Thus, a mechanical and electrically conducting connection of the power transistor to a component carrying a positive and/or negative voltage potential is possible by way of this electric terminal. In particular, it is advatageous if press-fit assembly of the power transistor in a component is possible by way of the electric terminal of the power transistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The FIGURE schematically shows a sectional view through a power transistor arranged in a housing according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     The FIGURE shows a schematic sectional diagram of a power transistor  12  arranged in a housing  10 . Power transistor  12  has a planar chip  14 , which is structured in a manner not considered in further detail here. Chip  14  has a back-side metallized area  16 , a first front-side metallized area  18  and a second front-side metallized area  20 . Metallized areas  16 ,  18  and  20  provide the electric connection of the areas structured in chip  14 , i.e., for example, the collector, the emitter and the base or the drain, the source and the gate. 
     Metallized areas  16  and  18  are connected to the power terminals, i.e., a positive voltage potential and/or a negative voltage potential. Metallized area  20  is for the gate electrode, i.e., the base or the gate. 
     Back-side metallized area  16  is applied to a base  24  with a soft solder  22 . Base  24  is made of an electrically conducting material and forms an electric terminal  26  for metallized area  16  of chip  14 . 
     Metallized area  18  is connected to a head carrier  30  by a soft solder  28 . Head carrier  30  is also made of an electrically conducting material and forms an electric terminal  32  for metallized area  18  of chip  14 . 
     Finally, metallized area  20  is connected by a soft solder  34  to a ring element  36  that has a terminal lug  38  projecting away radially to an imaginary vertical line passing through housing  10 . Ring element  36  and terminal lug  38  are made of an electrically conductive material and form an electric terminal  40  for metallized area  20  of chip  14 . 
     On its outer circumference, base  24  forms a ring groove  42  to lead through a sleeve  44 . Sleeve  44  is, for example, glued, soldered or otherwise suitably secured in ring groove  42 . Sleeve  44  may be made of an electrically conductive material or an electrically insulating material, depending on the interconnection of power transistor  12  in a circuit arrangement. The arrangement of sleeve  44  forms an interior space  46  in which chip  14  having metallized areas  16 ,  18  and  20  is arranged. A gap between metallized areas  18  and  20  is filled with an insulating enamel  48 . Remaining interior space  46  is filled with a casting compound  50  that hermetically seals chip  14 . 
     Head carrier  30  and ring element  36  together with its terminal lug  38  project out (upward in the view shown here) of housing  10  composed of base  24 , sleeve  44  and casting compound  50 . Thus, head carrier  30  and terminal lug  38  can be contacted as electric terminals  32  and  40 . Base  24  more or less forms the bottom of housing  10  and can also be contacted as electric terminal  26 . Head carrier  30  forms a cover of housing  10 . 
     Base  24  forms the entire bottom of housing  10 , so that a relatively large area is available for electric terminal  26 . Head carrier  30  forms a shield  52 , so a large contact area is also available for electric terminal  32 . Electric contacting of electric terminals  26  and  32  may be accomplished, for example, by connecting to a component, e.g., a metal plate, having the required voltage potential. Contacting may be accomplished by a solder joint, for example. In addition to a high current carrying capacity of electric terminals  26  and  32 , optimum thermal contacting of chip  14  is guaranteed by the large-area contact of electric terminals  26  and  32  on the respective plates responsible for the power supply. Optimum dissipation of the power loss heat of chip  14  is achieved through relatively voluminous base  24  and/or head carrier  30 . Furthermore, a relatively large mass is provided due to the relatively voluminous design of base  24  and head carrier  30 , providing dynamic thermal protection of chip  14  from external heat sources in addition to good dissipation of the power loss heat. Dissipation of the power loss heat and protection from external thermal energy are provided on both sides of chip  14 , thus especially optimum protection is achieved. 
     Due to the fact that chip  14  is practically encapsulated by base  24  and head carrier  30 , power transistor  12  is also suitable for very rugged operation, such as that in circuit arrangements in motor vehicles, for example. 
     Except for radially projecting terminal lug  38 , all parts of power transistor  12  are designed with rotational symmetry, so that mass production is readily possible, because there need not be any special alignment of chip  14  to base  24  and head carrier  30  or ring element  36  and sleeve  44 . 
     According to an embodiment not shown here, base  24  and/or head carrier  30 , in particular its shield  52 , may be enlarged radially beyond terminal lug  38 . Thus, in addition to the possibility of an even more optimized thermal and electric connection of chip  14 , entire power transistor  12  together with its housing  10  may be designed for a press-fit assembly in a matching recess in a metal component. This permits use even under extreme temperature and current loads.