Abstract:
A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of &#34;1&#34; or a low value of &#34;0&#34;. At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.

Description:
BACKGROUND OF THE INVENTION 
     This application is related in subject matter to two other applications, Ser. Nos. 08/570,446 patented and 08/570,447 both filed on the same day as this application. 
     The present invention is generally directed to error correction, decoding and encoding systems found in digital devices. The present invention incorporates by reference the invention disclosed in U.S. Ser. No. 08/538,691 filed Oct. 3, 1995 entitled &#34;error detection and correction code for four-bit-per-chip memory system&#34;, directed to multibit-per chip computer memory systems in which error correction and detection apparatus are provided to acheive correction of all single symbol errors and the detection of all single symbol errors occurring with a single bit error in a second symbol. More particularly, the present invention is directed to a memory assignment scheme, which assigns error correction code words to selected array modules, and incorporates parity address bits in this assignment scheme in order to provide an error correction and detection method and apparatus capable of detecting a variety of errors, including the detection of data fetched from an erroneous address. 
     In a computer system having b bits of memory available per chip, the failure of each chip can cause one to b erroneous bits in the output data depending upon the failure mode and the data originally stored. A b bit symbol error pattern is used to indicate one of all of the possible 2 b  -1 error patterns in the b bits for each computer chip. Normal error correction and detection systems employed in such situations would involve the use of a single error correction (SEC) and double error detection (DED) code. The SEC-DED code, however, is neither effective in correcting symbol errors generated from single chip failures, nor is effective in detecting symbol errors generated from double chip failures. On the other hand, a single symbol error correction and double symbol error detection code, a so-called SSC-DSD code, would provide an effective error correction and detection method to acheive high reliability in a b bit per chip memory. However, SSC-DSD codes require more check bits and more memory chips than are actually necessary for the problem. In particular, for a 64-bit data bus, the required SSC-DSD code would require four redundant memory chips for every 16 data chips to implement a (78,66) SSC-DSD code. Such codes would be 78 bits in length with 64 information bits and 14 check bits. Thus a memory system implementing this code would require 20 chips based upon the above memory organization. 
     Recognizing the stringent requirements of the SSC-DSD memory system, the present inventors devised a new coding scheme as described in detail in U.S. Ser. No. 08/538,691, in which the number of redundant chips are decreased from 4 to 3 chips for a (76,64) code for each set of 16 chips. This code is then used to correct all single symbol errors and detect all single symbol errors plus a single bit error in a second symbol. In certain instances, however, although the data in storage is error free, an error condition can occur if data is fetched from the wrong address in memory. However, the invention introduced in U.S. Ser. No. 08/538,691 never addressed the issue of detection of data fetched from an erroneous address. 
     The present invention utilizes the coding scheme suggested in U.S. Ser. No. 08/538,691, but improves upon the code by generating address parity bits from system address bits and later including these in the generation of ECC word. Accordingly, a more efficient and more reliable improved computer memory system is provided through the use of the present invention. All of these are desirable results. 
     SUMMARY OF THE INVENTION 
     In accordance with one embodiment of the present invention, digital signal encoding and decoding is accomplished by an apparatus and method through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length. First a multiplicity, k, of multisegment syndrome vectors in which each segment in each of said k syndrome vector is b bits long is generated. 
     Information is then retrieved from memory pertaining to assignment of different data blocks to a plurality of modules in the computer system. A multiplicity of module error indicators are then generated from the syndrome vectors. Each module error indicator is associated with at least one of the plurality of modules. In case of an error, the associated module error indicator is set to a value of one. After error is detected, the same is reported and efforts for correcting the error is taken when the error is determined to be of a kind that is correctable, such as a CE (Correctable Error.) When the error detected is a UE or an uncorrectable error, no further correction efforts are undertaken, but the is reported as such to the user. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which: 
     FIG. 1 is an overall block diagram illustrating a memory system in which a memory word is stored on k separate chips each providing b bits to a computer memory system register; 
     FIG. 2 is a functional block diagram illustrating the 15 possible error patterns for the case in which there are four bits per chip; 
     FIGS. 3A and 3B are functional block diagrams illustrating the limits of error detectability for the circuits of the present invention; 
     FIG. 4 is a general ECC (Error Correction Code) flow diagram, illustrating various staging registers and line buffers involved in the store and fetch operations for the present invention; 
     FIG. 5 is an illustration of the processing of bits during a data store operation; 
     FIG. 6 is a further illustration of the operation of a data store command according to the concepts presented by the present invention; 
     FIG. 7 is an illustration of the processing of bits during a data fetch operation; 
     FIG. 8 is a further illustration of the operation of a data fetch command according to the concepts presented by the present invention; 
     FIG. 9 illustrates the arrangement of data in memory modules on the SIMM array(s). 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention described below is particularly shown with respect to a particular example, namely the construction of a (76,64) code for a four-bit per chip computer memory system. However, the ideas presented herein are extensible to the general b bit per chip situation. In particular, it is noted that the number of rows of b by b submatrices in the parity check matrix is determined by the error correction capabilities that are desired. In the particular instance of the codes constructed in accordance with the present invention, three rows of by b submatrices are sufficient to provide the desired correction and detection capabilities. Likewise in general, codes constructed in accordance with the present invention will have k symbols. Each symbol will be represented by b bits. Since three of the symbols are employed for redundancy, there are thus k-3 information symbols and 3 symbols which comprise check bits. 
     With respect to the present invention for a (76,64) code, the parity check matrix for this code including an embodiment utilizing two address parity bits is given below: 
     
                                           TABLE I__________________________________________________________________________                                               SYMBOL                                                    ADDRESS                                               ID   PARITYDATA                                       ECC      (CHIP)                                                    BITS1  2 3  4 5  6 7  8 9  10                    11 12 13 14 15 16 17 18 19 ID   20__________________________________________________________________________1000 10001000 1000     1000 1000          1000 1000               1001 1101                    1111                       0011                          1100                             1100                                1110                                   0110                                      1000                                         0000                                            0000                                               --   010100 01000100 0100     0100 0100          0100 0100               0111 1011                    1010                       0010                          1000                             1000                                1001                                   1101                                      0100                                         0000                                            0000                                               --   110010 00100010 0010     0010 0010          0010 0010               0111 0110                    1100                       1111                          0011                             0011                                1001                                   1011                                      0010                                         0000                                            0000                                               --   100001 00010001 0001     0001 0001          0001 0001               1110 1101                    1000                       1010                          0010                             0010                                0111                                   0110                                      0001                                         0000                                            0000                                               --   110110 10000010 1011     1010 1101          0101 1110               1000 0001                    1000                       0111                          1000                             1110                                1000                                   0100                                      0000                                         1000                                            0000                                               --   101101 01000001 0110     0101 1011          1111 1001               0100 0011                    0100                       1110                          0100                             1001                                0100                                   1100                                      0000                                         0100                                            0000                                               --   011011 00101010 1101     1000 0110          0100 1001               0010 0101                    0010                       1110                          0010                             1001                                0010                                   0001                                      0000                                         0010                                            0000                                               --   000110 00010101 1011     0100 1101          1100 0111               0001 1111                    0001                       1001                          0001                             0111                                0001                                   0011                                      0000                                         0001                                            0000                                               --   001000 11100111 1010     1001 0010          0110 0001               0101 1000                    1011                       1000                          0110                             1000                                0100                                   1000                                      0000                                         0000                                            1000                                               --   000100 10011110 0101     0111 0001          1101 0011               1111 0100                    0110                       0100                          1101                             0100                                1100                                   0100                                      0000                                         0000                                            0100                                               --   000010 10011110 1000     0111 1010          1011 0101               0100 0010                    1101                       0010                          1011                             0010                                0001                                   0010                                      0000                                         0000                                            0010                                               --   010001 01111001 0100     1110 0101          0110 1111               1100 0001                    1011                       0001                          0110                             0001                                0011                                   0001                                      0000                                         0000                                            0001                                               --   10__________________________________________________________________________ 
    
     DATA STORE OPERATION 
     During a store operation, in accordance with the embodiment represented by the parity check matrix shown in Table I, each of the 12 ECC check bits is generated. The 12 ECC check bits are generated in two stages. During the first stage, a partial ECC check bit is generated by exclusive OR circuits which take a subset of 64 data bits as indicated by the 1&#39;s in each row of the parity check matrix in Table I. For example, the first partial check bit is generated by exclusive-ORing data found at positions: 1, 5, 9, 13, 17, 21, 25, 29, 33, 36, 37, 38, 40, 41, 42, 43, 44, 47, 48, 49, 50, 53, 54, 57, 58, 59, 62 and 63. 
     These address parity bits are generated from selective combination of data from system address bits as discussed later in detail. During the second stage the partial check bits are combined with the address parity bits and data bits to generate the final 12 ECC check bits. 
     The set of 64 data bits together with the 12 check bits form an ECC word. Therefore, it seems that in the embodiment presented in Table I, when the two address parity bits are included, the ECC word is really a (78,66) code word. However, since the parity address bits have been used in the generation of the final 12 ECC check bits, it is unnecessary for them to be stored as part of the ECC word. Therefore, the code is still a (76,64) code since only 76 bits per code word are stored into the memory array or a SIMM (Single-Inline-Memory-Module) as shown in FIG. 9. The address parity bits are regenerated during the fetch operation from the incoming system address bits. 
     The ECC word is divided into 19 groups of 4 bit symbols. In storing data, the ECC word is stored in 19 different chips. That is each symbol is stored on a different chip. This situation is illustrated in FIG. 1 wherein memory system 10 is shown to be organized using m chips with b bits being delivered from each chip at a time. Thus, the ECC word in register 25 is mb bits long. For the example illustrated herein, m=19 and b=4. 
     When an array chip, say chip i, fails the data stored in that chip may or may not be in error depending on the data stored. If the data is in error, the number of errors may be one or more than one. FIG. 2 illustrates all of the possible error patterns 2 b  -1=15 for a failed chip i. FIGS. 3A and 3B illustrate the limits of error detectability in the present invention. FIG. 3A particularly shows the situation in which chip i produces from one to four errors while only a single error occurs in chip j. Reference numeral 20 in FIGS. 1 through 3 refer to the individual memory chips. FIG. 3B shows the situation in which chip i produces from one to four errors while only a single error occurs in address parity bits. 
     At the outset of a store operation data bits are stored in a plurality of storage buffers. In the example illustrated in Table II, given below, the 64 data bits are first stored in two storage buffers named STBUF --  H --  D(0 . . . 31) and STBUF --  L --  D(0 . . . 31), respectively. There are 32 bits of data in each storage buffer and these bits are renamed as SEC --  O --  H(0 . . . 31) and SEC --  O --  L(0 . . . 31) when wired into the memory modules, namely the modules of a SIMM. 
     
                                           TABLE II__________________________________________________________________________STBUF.sub.-- H.sub.-- D(0..31)          11            1111     1111                        2222     2222                                    22330123 4567     8901            2345     6789                        0123     4567                                    8901__________________________________________________________________________1000 1000     1000            1000     1000                        1000     1000                                    10000100 0100     0100            0100     0100                        0100     0100                                    01000010 0010     0010            0010     0010                        0010     0010                                    00100001 0001     0001            0001     0001                        0001     0001                                    00010110 1000     0010            1011     1010                        1101     0101                                    11101101 0100     0001            0110     0101                        1011     1111                                    10011011 0010     1010            1101     1000                        0110     0100                                    10010110 0001     0101            1011     0100                        1101     1100                                    01111000 1110     0111            1010     1001                        0010     0110                                    00010100 1001     1110            0101     0111                        0001     1101                                    00110010 1001     1110            1000     0111                        1010     1011                                    01010001 0111     1001            0100     1110                        0101     0110                                    1111__________________________________________________________________________STBUF.sub.-- L.sub.-- D(0..31)                   SEC.sub.-- O.sub.-- C(0..11)  11    1111       1111          2222             2222                2233      11 STORE.sub.-- ADDRP.sub.-- D(0..1)__________________________________________________________________________0123   4567 8901    2345       6789          0123             4567                8901                   0123                      4567                          8901                             011001   1101 1111    0011       1100          1100             1110                0110                   1000                      0000                          0000                             010111   1011 1010    0010       1000          1000             1001                1101                   0100                      0000                          0000                             110111   0110 1100    1111       0011          0011             1001                1011                   0010                      0000                          0000                             101110   1101 1000    1010       0010          0010             0111                0110                   0001                      0000                          0000                             111000   0001 1000    0111       1000          1110             1000                0100                   0000                      1000                          0000                             100100   0011 0100    1110       0100          1001             0100                1100                   0000                      0100                          0000                             010010   0101 0010    1110       0010          1001             0010                0001                   0000                      0010                          0000                             000001   1111 0001    1001       0001          0111             0001                0011                   0000                      0001                          0000                             000101   1000 1011    1000       0110          1000             0100                1000                   0000                      0000                          1000                             001111   0100 0110    0100       1101          0100             1100                0100                   0000                      0000                          0100                             000100   0010 1101    0010       1011          0010             0001                0010                   0000                      0000                          0010                             011100   0001 1011    0001       0110          0001             0011                0001                   0000                      0000                          0001                             10__________________________________________________________________________ 
    
     The address parity bits are located in address buffers indicated as STORE --  ADDRP --  D(0 . . . 1) in Table II above. The address parity bits are generated from selective combination of data from system address bits as shown in the example provided below in Table III. 
     
                                           TABLE III__________________________________________________________________________ ##STR1## ##STR2## ##STR3## ##STR4## ##STR5## ##STR6## ##STR7## ##STR8## ##STR9## ##STR10## ##STR11##__________________________________________________________________________ CD means memory card selection bit C0-C11 means Column Address 0-11 R0-R11 means Row Address 0-11 EO means even/odd lines (on STC interleaving) RE means RAS A/B decode 
    
     STORE --  ADDRP --  D(0) is generated from the parity of system address bits 1, 2, 5-14, 26, 27 and 30. Similarily, STORE --  ADDRP --  D(1) is the parity of system address bits 0, 3, 4, 5-25, and 31. As illustrated in table III, the mapping of system address bits to memory module depends on the size of the modules. 
     The final ECC check bits are then generated by combining the contents of the STORE --  ADDRP with the data stored in the storage buffers STBUF and the data obtained from the partial check bits generated from the Exclusive-Or circuitry. In short, during the first stage, the partial check bits SY0(0 . . . 11) are generated from the high word data word STBUF --  H --  D(0 . . . 31) and SY1(0 . . . 11) are generated from the low data word STBUF --  L --  D(0 . . . 31). Then SY0 and SY1 and address parity bits are combined to produce the final check bits. The final 12 ECC check bits are stored in SEC --  O --  C(0 . . . 11) buffer. The following equation illustrates in detail the generation of the 12 ECC check bits and their final storage in the SEC --  O --  C(0 . . . 11) buffer. 
     The notation OPA(X||Y||Z) is used to describe a logic function that implements the odd parity of bits X,Y and Z. The generation of check bits is divided in two stages as mentioned earlier. ##STR12## 
     FIG. 4 is an illustration of the general ECC flow diagram. Logic steps 1 through 4, 100 through 400, are the various staging registers and line buffers used in the data store and data fetch operations. Logic steps 1 and 2, 100 and 200, involve different operations that finally allow the generation of ECC store operation 220 into the computer memory DRAM array 500. This information is later fetched from the DRAM array 500 to regenerate and decode the bits during the fetch operation, 300 through 400. 
     During the store operation, the ECC check bits 57 are generated from the 64 data bits 50 and the system address bits 52 as shown FIG. 5. The entire ECC word 58 is then stored into a memory array 500 to be used later during a fetch operation. FIG. 6 shows the storage of data in storage arrays 61, 62 and 63 before the generation of check bits 66,67 and 68. 
     Table I above is an embodiment of the present invention utilizing two address parity bits. Other embodiments are conceivable, however, in accordance to the concepts of the present invention where the number of address parity bits, can either be reduced to one or increased to more than two. Table IV given below provides another embodiment of the present invention where eight address parity bits are generated and used. 
     
                                           TABLE IV__________________________________________________________________________                                               SYMBOL                                                    ADDRESS                                               ID   PARITYDATA                                       ECC      (CHIP)                                                    BITS1  2 3  4 5  6 7  8 9  10                    11 12 13 14 15 16 17 18 19 ID   20 21__________________________________________________________________________1000 10001000 1000     1000 1000          1000 1000               1001 1101                    1111                       0011                          1100                             1100                                1110                                   0110                                      1000                                         0000                                            0000                                               --   0111                                                       11010100 01000100 0100     0100 0100          0100 0100               0111 1011                    1010                       0010                          1000                             1000                                1001                                   1101                                      0100                                         0000                                            0000                                               --   1111                                                       00100010 00100010 0010     0010 0010          0010 0010               0111 0110                    1100                       1111                          0011                             0011                                1001                                   1011                                      0010                                         0000                                            0000                                               --   1011                                                       01110001 00010001 0001     0001 0001          0001 0001               1110 1101                    1000                       1010                          0010                             0010                                0111                                   0110                                      0001                                         0000                                            0000                                               --   1100                                                       11010110 10000010 1011     1010 1101          0101 1110               1000 0001                    1000                       0111                          1000                             1110                                1000                                   0100                                      0000                                         1000                                            0000                                               --   1000                                                       00111101 01000001 0110     0101 1011          1111 1001               0100 0011                    0100                       1110                          0100                             1001                                0100                                   1100                                      0000                                         0100                                            0000                                               --   0110                                                       01111011 00101010 1101     1000 0110          0100 1001               0010 0101                    0010                       1110                          0010                             1001                                0010                                   0001                                      0000                                         0010                                            0000                                               --   0001                                                       00100110 00010101 1011     0100 1101          1100 0111               0001 1111                    0001                       1001                          0001                             0111                                0001                                   0011                                      0000                                         0001                                            0000                                               --   0000                                                       11101000 11100111 1010     1001 0010          0110 0001               0101 1000                    1011                       1000                          0110                             1000                                0100                                   1000                                      0000                                         0000                                            1000                                               --   0000                                                       11000100 10011110 0101     0111 0001          1101 0011               1111 0100                    0110                       0100                          1101                             0100                                1100                                   0100                                      0000                                         0000                                            0100                                               --   0001                                                       10100010 10011110 1000     0111 1010          1011 0101               0100 0010                    1101                       0010                          1011                             0010                                0001                                   0010                                      0000                                         0000                                            0010                                               --   0110                                                       10000001 01111001 0100     1110 0101          0110 1111               1100 0001                    1011                       0001                          0110                             0001                                0011                                   0001                                      0000                                         0000                                            0001                                               --   1011                                                       1001__________________________________________________________________________ 
    
     DATA FETCH OPERATION 
     During a Fetch operation, the reverse of the store process implemented during the store operation is used as shown in FIGS. 7 and 8. Data 70, 72 and 55, including the ECC word, is first fetched from memory 500, as shown in FIG. 7. FIG. 9 illustrates the circuits used during an ECC fetch operation. Data fetched from the DRAM array chips are named MDRMUX --  H(0 . . . 31) 92 for modules 1 to 8, MDRMUX --  L(0 . . . 31) 94 for modules 9 to 16 and MDRMUX --  C(0 . . . 11) 96 for modules 17 to 19. 
     When data is fetched from storage, a set of partial syndrome bits SYH(0 . . . 11) and SYL(0 . . . 11) is generated from the fetched data word from the DRAM array chips or the MDRMUX as illustrated in detail by the following equation: 
     
         __________________________________________________________________________/******** FETCH ECC ****************************************************************//*************************************************************************************/                                 /*&gt;CHECKBIT REGENERATION             &lt;*//*************************************************************************************/SYH(0):= OPA   (MDRMUX.sub.-- H(0)             ||MDRMUX.sub.-- H(4)                       ||MDRMUX.sub.-- H(8)                                 ||MDRMUX.sub.--                                 H(12)|   |MDRMUX.sub.-- H(16)             ||MDRMUX.sub.-- H(20)                       ||MDRMUX.sub.-- H(24)                                 ||MDRMUX.sub.--                                 H(28));SYL(0):= OPA   (MDRMUX.sub.-- L(0)             ||MDRMUX.sub.-- L(3)                       ||MDRMUX.sub.-- L(4)                                 ||MDRMUX.sub.--                                 L(5)|   |MDRMUX.sub.-- L(7)             ||MDRMUX.sub.-- L(8)                       ||MDRMUX.sub.-- L(9)                                 ||MDRMUX.sub.--                                 L(10)|   |MDRMUX.sub.-- L(11)             ||MDRMUX.sub.-- L(14)                       ||MDRMUX.sub.-- L(15)                                 ||MDRMUX.sub.--                                 L(16)|   |MDRMUX.sub.-- L(17)             ||MDRMUX.sub.-- L(20)                       ||MDRMUX.sub.-- L(21)                                 ||MDRMUX.sub.--                                 L(24)|   |MDRMUX.sub.-- L(25)             ||MDRMUX.sub.-- L(26)                       ||MDRMUX.sub.-- L(29)                                 ||MDRMUX.sub.--                                 L(30));SYH(1):= OPA   (MDRMUX.sub.-- H(1)             ||MDRMUX.sub.-- H(5)                       ||MDRMUX.sub.-- H(9)                                 ||MDRMUX.sub.--                                 H(13)|   |MDRMUX.sub.-- H(17)             ||MDRMUX.sub.-- H(21)                       ||MDRMUX.sub.-- H(25)                                 ||MDRMUX.sub.--                                 H(29));SYL(1):= OPA   (MDRMUX.sub.-- L(1)             ||MDRMUX.sub.-- L(2)                       ||MDRMUX.sub.-- L(3)                                 ||MDRMUX.sub.--                                 L(4)|   |MDRMUX.sub.-- L(6)             ||MDRMUX.sub.-- L(7)                       ||MDRMUX.sub.-- L(8)                                 ||MDRMUX.sub.--                                 L(10)|   |MDRMUX.sub.-- L(14)             ||MDRMUX.sub.-- L(16)                       ||MDRMUX.sub.-- L(20)                                 ||MDRMUX.sub.--                                 L(24)|   |MDRMUX.sub.-- L(27)             ||MDRMUX.sub.-- L(28)                       ||MDRMUX.sub.-- L(29)                                 ||MDRMUX.sub.--                                 L(31));SYH(2):= OPA   (MDRMUX.sub.-- H(2)             ||MDRMUX.sub.-- H(6)                       ||MDRMUX.sub.-- H(10)                                 ||MDRMUX.sub.--                                 H(14)|   |MDRMUX.sub.-- H(18)             ||MDRMUX.sub.-- H(22)                       ||MDRMUX.sub.-- H(26)                                 ||MDRMUX.sub.--                                 H(30));SYL(2):= OPA   (MDRMUX.sub.-- L(1)             ||MDRMUX.sub.-- L(2)                       ||MDRMUX.sub.-- L(3)                                 ||MDRMUX.sub.--                                 L(5)|   |MDRMUX.sub.-- L(6)             ||MDRMUX.sub.-- L(8)                       ||MDRMUX.sub.-- L(9)                                 ||MDRMUX.sub.--                                 L(12)|   |MDRMUX.sub.-- L(13)             ||MDRMUX.sub.-- L(14)                       ||MDRMUX.sub.-- L(15)                                 ||MDRMUX.sub.--                                 L(18)|   |MDRMUX.sub.-- L(19)             ||MDRMUX.sub.-- L(22)                       ||MDRMUX.sub.-- L(23)                                 ||MDRMUX.sub.--                                 L(24)|   |MDRMUX.sub.-- L(27)             ||MDRMUX.sub.-- L(28)                       ||MDRMUX.sub.-- L(30)                                 ||MDRMUX.sub.--                                 L(31));SYH(3):= OPA   (MDRMUX.sub.-- H(3)             ||MDRMUX.sub.-- H(7)                       ||MDRMUX.sub.-- H(11)                                 ||MDRMUX.sub.--                                 H(15)|   |MDRMUX.sub.-- H(19)             ||MDRMUX.sub.-- H(23)                       ||MDRMUX.sub.-- H(27)                                 ||MDRMUX.sub.--                                 H(31));SYL(3):= OPA   (MDRMUX.sub.-- L(0)             ||MDRMUX.sub.-- L(1)                       ||MDRMUX.sub.-- L(2)                                 ||MDRMUX.sub.--                                 L(4)|   |MDRMUX.sub.-- L(5)             ||MDRMUX.sub.-- L(7)                       ||MDRMUX.sub.-- L(8)                                 ||MDRMUX.sub.--                                 L(12)|   |MDRMUX.sub.-- L(14)             ||MDRMUX.sub.-- L(18)                       ||MDRMUX.sub.-- L(22)                                 ||MDRMUX.sub.--                                 L(25)|   |MDRMUX.sub.-- L(26)             ||MDRMUX.sub.-- L(27)                       ||MDRMUX.sub.-- L(29)                                 ||MDRMUX.sub.--                                 L(30));SYH(4):= OPA   (MDRMUX.sub.-- H(1)             ||MDRMUX.sub.-- H(2)                       ||MDRMUX.sub.-- H(4)                                 ||MDRMUX.sub.--                                 H(10)|   |MDRMUX.sub.-- H(12)             ||MDRMUX.sub.-- H(14)                       ||MDRMUX.sub.-- H(15)                                 ||MDRMUX.sub.--                                 H(16)|   |MDRMUX.sub.-- H(18)             ||MDRMUX.sub.-- H(20)                       ||MDRMUX.sub.-- H(21)                                 ||MDRMUX.sub.--                                 H(23)|   |MDRMUX.sub.-- H(25)             ||MDRMUX.sub.-- H(27)                       ||MDRMUX.sub.-- H(28)                                 ||MDRMUX.sub.--                                 H(29)|   |MDRMUX.sub.-- H(30));SYL(4):= OPA   (MDRMUX.sub.-- L(0)             ||MDRMUX.sub.-- L(7)                       ||MDRMUX.sub.-- L(8)                                 ||MDRMUX.sub.--                                 L(13)|   |MDRMUX.sub.-- L(14)             ||MDRMUX.sub.-- L(15)                       ||MDRMUX.sub.-- L(16)                                 ||MDRMUX.sub.--                                 L(20)|   |MDRMUX.sub.-- L(21)             ||MDRMUX.sub.-- L(22)                       ||MDRMUX.sub.-- L(24)                                 ||MDRMUX.sub.--                                 L(29));SYH(5):= OPA   (MDRMUX.sub.-- H(0)             ||MDRMUX.sub.-- H(1)                       ||MDRMUX.sub.-- H(3)                                 ||MDRMUX.sub.--                                 H(5)|   |MDRMUX.sub.-- H(11)             ||MDRMUX.sub.-- H(13)                       ||MDRMUX.sub.-- H(14)                                 ||MDRMUX.sub.--                                 H(17)|   |MDRMUX.sub.-- H(19)             ||MDRMUX.sub.-- H(20)                       ||MDRMUX.sub.-- H(22)                                 ||MDRMUX.sub.--                                 H(23)|   |MDRMUX.sub.-- H(24)             ||MDRMUX.sub.-- H(25)                       ||MDRMUX.sub.-- H(26)                                 ||MDRMUX.sub.--                                 H(27)|   |MDRMUX.sub.-- H(28)             ||MDRMUX.sub.-- H(31));SYL(5):= OPA   (MDRMUX.sub.-- L(1)             ||MDRMUX.sub.-- L(6)                       ||MDRMUX.sub.-- L(7)                                 ||MDRMUX.sub.--                                 L(9)|   |MDRMUX.sub.-- L(12)             ||MDRMUX.sub.-- L(13)                       ||MDRMUX.sub.-- L(14)                                 ||MDRMUX.sub.--                                 L(17)|   |MDRMUX.sub.-- L(20)             ||MDRMUX.sub.-- L(23)                       ||MDRMUX.sub.-- L(25)                                 ||MDRMUX.sub.--                                 L(28)|   |MDRMUX.sub.-- L(29));SYH(6):= OPA   (MDRMUX.sub.-- H(0)             ||MDRMUX.sub.-- H(2)                       ||MDRMUX.sub.-- H(3)                                 ||MDRMUX.sub.--                                 H(6)|   |MDRMUX.sub.-- H(8)             ||MDRMUX.sub.-- H(10)                       ||MDRMUX.sub.-- H(12)                                 ||MDRMUX.sub.--                                 H(13)|   |MDRMUX.sub.-- H(15)             ||MDRMUX.sub.-- H(16)                       ||MDRMUX.sub.-- H(21)                                 ||MDRMUX.sub.--                                 H(22)|   |MDRMUX.sub.-- H(25)             ||MDRMUX.sub.-- H(28)                       ||MDRMUX.sub.-- H(31));SYL(6):= OPA   (MDRMUX.sub.-- L(2)             ||MDRMUX.sub.-- L(5)                       ||MDRMUX.sub.-- L(7)                                 ||MDRMUX.sub.--                                 L(10|   |MDRMUX.sub.-- L(12)             ||MDRMUX.sub.-- L(13)                       ||MDRMUX.sub.-- L(14)                                 ||MDRMUX.sub.--                                 L(18)|   |MDRMUX.sub.-- L(20)             ||MDRMUX.sub.-- L(23)                       ||MDRMUX.sub.-- L(26)                                 ||MDRMUX.sub.--                                 L(31));SYH(7):= OPA   (MDRMUX.sub.-- H(1)             ||MDRMUX.sub.-- H(2)                       ||MDRMUX.sub.-- H(7)                                 ||MDRMUX.sub.--                                 H(9)|   |MDRMUX.sub.-- H(11)             ||MDRMUX.sub.-- H(12)                       ||MDRMUX.sub.-- H(14)                                 ||MDRMUX.sub.--                                 H(15)|   |MDRMUX.sub.-- H(17)             ||MDRMUX.sub.-- H(20)                       ||MDRMUX.sub.-- H(21)                                 ||MDRMUX.sub.--                                 H(23)|   |MDRMUX.sub.-- H(24)             ||MDRMUX.sub.-- H(25)                       ||MDRMUX.sub.-- H(29)                                 ||MDRMUX.sub.--                                 H(30)|   |MDRMUX.sub.-- H(31));SYL(7):= OPA   (MDRMUX.sub.-- L(3)             ||MDRMUX.sub.-- L(4)                       ||MDRMUX.sub.-- L(5)                                 ||MDRMUX.sub.--                                 L(6)|   |MDRMUX.sub.-- L(7)             ||MDRMUX.sub.-- L(11)                       ||MDRMUX.sub.-- L(12)                                 ||MDRMUX.sub.--                                 L(15)|   |MDRMUX.sub.-- L(19)             ||MDRMUX.sub.-- L(21)                       ||MDRMUX.sub.-- L(22)                                 ||MDRMUX.sub.--                                 L(23)|   |MDRMUX.sub.-- L(27)             ||MDRMUX.sub.-- L(30)                       ||MDRMUX.sub.-- L(31));SYH(8):= OPA   (MDRMUX.sub.-- H(0)             ||MDRMUX.sub.-- H(4)                       ||MDRMUX.sub.-- H(5)                                 ||MDRMUX.sub.--                                 H(6)|   |MDRMUX.sub.-- H(9)             ||MDRMUX.sub.-- H(10)                       ||MDRMUX.sub.-- H(11)                                 ||MDRMUX.sub.--                                 H(12)|   |MDRMUX.sub.-- H(14)             ||MDRMUX.sub.-- H(16)                       ||MDRMUX.sub.-- H(19)                                 ||MDRMUX.sub.--                                 H(22)|   |MDRMUX.sub.-- H(25)             ||MDRMUX.sub.-- H(26)                       ||MDRMUX.sub.-- H(31));SYL(8):= OPA   (MDRMUX.sub.-- L(1)             ||MDRMUX.sub.-- L(3)                       ||MDRMUX.sub.-- L(4)                                 ||MDRMUX.sub.--                                 L(8)|   |MDRMUX.sub.-- L(10)             ||MDRMUX.sub.-- L(11)                       ||MDRMUX.sub.-- L(12)                                 ||MDRMUX.sub.--                                 L(17)|   |MDRMUX.sub.-- L(18)             ||MDRMUX.sub.-- L(20)                       ||MDRMUX.sub.-- L(25)                                 ||MDRMUX.sub.--                                 L(28));SYH(9):= OPA   (MDRMUX.sub.-- H(1)             ||MDRMUX.sub.-- H(4)                       ||MDRMUX.sub.-- H(7)                                 ||MDRMUX.sub.--                                 H(8)|   |MDRMUX.sub.-- H(9)             ||MDRMUX.sub.-- H(10)                       ||MDRMUX.sub.-- H(13)                                 ||MDRMUX.sub.--                                 H(15)|   |MDRMUX.sub.-- H(17)             ||MDRMUX.sub.-- H(18)                       ||MDRMUX.sub.-- H(19)                                 ||MDRMUX.sub.--                                 H(23)|   |MDRMUX.sub.-- H(24)             ||MDRMUX.sub.-- H(25)                       ||MDRMUX.sub.-- H(27)                                 ||MDRMUX.sub.--                                 H(30)|   |MDRMUX.sub.-- H(31));SYL(9):= OPA   (MDRMUX.sub.-- L(0)             ||MDRMUX.sub.-- L(1)                       ||MDRMUX.sub.-- L(2)                                 ||MDRMUX.sub.--                                 L(3)|   |MDRMUX.sub.-- L(5)             ||MDRMUX.sub.-- L(9)                       ||MDRMUX.sub.-- L(10)                                 ||MDRMUX.sub.--                                 L(13)|   |MDRMUX.sub.-- L(16)             ||MDRMUX.sub.-- L(17)                       ||MDRMUX.sub.-- L(19)                                 ||MDRMUX.sub.--                                 L(21)|   |MDRMUX.sub.-- L(24)             ||MDRMUX.sub.-- L(25)                       ||MDRMUX.sub.-- L(29));SYH(10):=OPA   (MDRMUX.sub.-- H(2)             ||MDRMUX.sub.-- H(4)                       ||MDRMUX.sub.-- H(7)                                 ||MDRMUX.sub.--                                 H(8)|   |MDRMUX.sub.-- H(9)             ||MDRMUX.sub.-- H(10)                       ||MDRMUX.sub.-- H(12)                                 ||MDRMUX.sub.--                                 H(17)|   |MDRMUX.sub.-- H(18)             ||MDRMUX.sub.-- H(19)                       ||MDRMUX.sub.-- H(20)                                 ||MDRMUX.sub.--                                 H(22)|   |MDRMUX.sub.-- H(24)             ||MDRMUX.sub.-- H(26)                       ||MDRMUX.sub.-- H(27)                                 ||MDRMUX.sub.--                                 H(29)|   |MDRMUX.sub.-- H(31));SYL(10):=OPA   (MDRMUX.sub.-- L(1)             ||MDRMUX.sub.-- L(6)                       ||MDRMUX.sub.-- L(8)                                 ||MDRMUX.sub.--                                 L(9)|   |MDRMUX.sub.-- L(11)             ||MDRMUX.sub.-- L(14)                       ||MDRMUX.sub.-- L(16)                                 ||MDRMUX.sub.--                                 L(18)|   |MDRMUX.sub.-- L(19)             ||MDRMUX.sub.-- L(22)                       ||MDRMUX.sub.-- L(27)                                 ||MDRMUX.sub.--                                 L(30));SYH(11):=OPA   (MDRMUX.sub.-- H(3)             ||MDRMUX.sub.-- H(5)                       ||MDRMUX.sub.-- H(6)                                 ||MDRMUX.sub.--                                 H(7)|   |MDRMUX.sub.-- H(8)             ||MDRMUX.sub.-- H(11)                       ||MDRMUX.sub.-- H(13)                                 ||MDRMUX.sub.--                                 H(16)|   |MDRMUX.sub.-- H(17)             ||MDRMUX.sub.-- H(18)                       ||MDRMUX.sub.-- H(21)                                 ||MDRMUX.sub.--                                 H(23)|   |MDRMUX.sub.-- H(25)             ||MDRMUX.sub.-- H(26)                       ||MDRMUX.sub.-- H(28)                                 ||MDRMUX.sub.--                                 H(29)|   |MDRMUX.sub.-- H(30)             ||MDRMUX.sub.-- H(31));SYL(11):=OPA   (MDRMUX.sub.-- L(0)             ||MDRMUX.sub.-- L(1)                       ||MDRMUX.sub.-- L(7)                                 ||MDRMUX.sub.--                                 L(8)|   |MDRMUX.sub.-- L(10)             ||MDRMUX.sub.-- L(11)                       ||MDRMUX.sub.-- L(15)                                 ||MDRMUX.sub.--                                 L(17)|   |MDRMUX.sub.-- L(18)             ||MDRMUX.sub.-- L(23)                       ||MDRMUX.sub.-- L(26)                                 ||MDRMUX.sub.--                                 L(27)|   |MDRMUX.sub.-- L(31));__________________________________________________________________________ 
    
     The same circuits that are used in generating the partial check bits during the store operations are utilized again to regenerate the partial syndrome bits. So for example, partial syndrome bit i is the Exclusive-OR of the fetched data word at positions specified by 1&#39;s in the ith row of the parity check matrix. That is to say that the partial syndrome bits are generated by supplying specified signals to a set of exclusive --  OR gates. 
     The syndrome bits SY(0 . . . 11) are then generated from the combination of the fetched data from check bits MDRMUX --  C(0 . . . 11) and the address parity bits from Fetch --  ADDRP(0. . . m) which are regenerated from the incoming system address bits. 
     
         __________________________________________________________________________/******************************* Syndrome Generation *******************************/SY(0)   :=MDRMUX.sub.-- C(0)    XOR SYH(0)           XOR SYL(0)  XOR FETCH.sub.-- ADDRP(1);SY(1)   :=MDRMUX.sub.-- C(1)    XOR SYH(1)           XOR SYL(1)           XOR FETCH.sub.-- ADDRP(0)                       XOR FETCH_ADDRP(1);SY(2)   :=                              ;MDRMUX.sub.-- C(2)    XOR SYH(2)           XOR SYL(2) XOR FETCH_ADDRP(0)SY(3)   :=MDRMUX.sub.-- C(3)    XOR SYH(3)           XOR SYL(3)           XOR FETCH ADDRP(0)                       XOR FETCH_ADDRP(1);SY(4)   :=                              ;MDRMUX.sub.-- C(4)    XOR SYH(4)           XOR SYL(4) XOR FETCH_ADDRP(0)SY(5)   :=MDRMUX.sub.-- C(5)    XOR SYH(5)           XOR SYL(5)  XOR FETCH ADDRP(1);SY(6)   :=MDRMUX.sub.-- C(6)    XOR SYH(6)           XOR SYL(6)              ;SY(7)   :=MDRMUX.sub.-- C(7)    XOR SYH(7)           XOR SYL(7)              ;SY(8)   :=MDRMUX.sub.-- C(8)    XOR SYH(8)           XOR SYL(8)              ;SY(9)   :=MDRMUX.sub.-- C(9)    XOR SYH(9)           XOR SYL(9)              ;SY(10)   :=MDRMUX.sub.-- C(10)    XOR SYH(10)           XOR SYL(10) XOR FETCH_ADDRP(1);SY(11)   :=MDRMUX.sub.-- C(11)    XOR SYH(11)           XOR SYL(11) XOR FETCH_ADDRP(0)                                   ;__________________________________________________________________________ 
    
     The partial syndrome bits SY(0 . . . 11) 72 are then decoded 74 to identify any possible errors as illustrated in FIG. 7. Module error indicators are then generated according to the formula given below during the decoding process to detect and indicate errors. 
     
         __________________________________________________________________________ ##STR13##MOD.sub.-- 00 :=  (    SY( 1) XOR SY( 2)    XOR  SY( 4) )&amp;      ( SY( 0)       XOR SY( 1)    XOR SY( 3)                            XOR  SY( 5) )&amp;      ( SY( 0)    XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 6) )&amp;      (    SY( 1) XOR SY( 2)    XOR  SY( 7) )&amp;      ( SY( 0)                  XOR  SY( 8) )&amp;      (    SY( 1)               XOR  SY( 9) )&amp;      (           SY( 2)        XOR  SY(10) )&amp;      (                  SY( 3) XOR  SY(11) );MOD.sub.-- 01 :=  ( SY( 0)                  XOR  SY( 4) )&amp;      (    SY( 1)               XOR  SY( 5) )&amp;      (           SY( 2)        XOR  SY( 6) )&amp;      (                  SY( 3) XOR  SY( 7) )&amp;      ( SY( 0)       XOR SY( 1)              XOR SY( 2)    XOR  SY( 8) )&amp;      ( SY( 0)           XOR SY( 3)                            XOR  SY( 9) )&amp;      ( SY( 0)           XOR SY( 3)                            XOR  SY(10) )&amp;      (    SY( 1) XOR SY( 2)                     XOR SY( 3)                            XOR  SY(11) );MOD.sub.-- 02 :=  (           SY( 2)        XOR  SY( 4) )&amp;      (                  SY( 3) XOR  SY( 5) )&amp;      ( SY( 0)    XOR SY( 2)    XOR  SY( 6) )&amp;      (    SY( 1)        XOR SY( 3)                            XOR  SY( 7) )&amp;      (    SY( 1) XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 8) )&amp;      ( SY( 0)       XOR SY( 1)              XOR SY( 2)    XOR  SY( 9) )&amp;      ( SY( 0)       XOR SY( 1)              XOR SY( 2)    XOR  SY(10) )&amp;      ( SY( 0)           XOR SY( 3)                            XOR  SY(11) );MOD.sub.-- 03 :=  ( SY( 0)    XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 4) )&amp;      (    SY( 1) XOR SY( 2)    XOR  SY( 5) )&amp;      ( SY( 0)       XOR SY( 1)    XOR SY( 3)                            XOR  SY( 6) )&amp;      ( SY( 0)    XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 7) )&amp;      ( SY( 0)    XOR SY( 2)    XOR  SY( 8) )&amp;      (    SY( 1)        XOR SY( 3)                            XOR  SY( 9) )&amp;      ( SY( 0)                  XOR  SY(10) )&amp;      (    SY( 1)               XOR  SY(11) );MOD.sub.-- 04 :=  ( SY( 0)    XOR SY( 2)    XOR  SY( 4) )&amp;      (    SY( 1)        XOR SY( 3)                            XOR  SY( 5) )&amp;      ( SY( 0)                  XOR  SY( 6) )&amp;      (    SY( 1)               XOR  SY( 7) )&amp;      ( SY( 0)           XOR SY( 3)                            XOR  SY( 8) )&amp;      (    SY( 1) XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 9) )&amp;      (    SY( 1) XOR SY( 2)                     XOR SY( 3)                            XOR  SY(10) )&amp;      ( SY( 0)       XOR SY( 1)              XOR SY( 2)    XOR  SY(11) );MOD.sub.-- 05 :=  ( SY( 0)       XOR SY( 1)    XOR SY( 3)                            XOR  SY( 4) )&amp;      ( SY( 0)    XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 5) )&amp;      (    SY( 1) XOR SY( 2)    XOR  SY( 6) )&amp;      ( SY( 0)       XOR SY( 1)    XOR SY( 3)                            XOR  SY( 7) )&amp;      (           SY( 2)        XOR  SY( 8) )&amp;      (                  SY( 3) XOR  SY( 9) )&amp;      ( SY( 0)    XOR SY( 2)    XOR  SY(10) )&amp;      (    SY( 1)        XOR SY( 3)                            XOR  SY(11) );MOD.sub.-- 06 :=  (    SY( 1) XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 4) )&amp;      ( SY( 0)       XOR SY( 1)              XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 5) )&amp;      (    SY( 1)               XOR  SY( 6) )&amp;      ( SY( 0)       XOR SY( 1)           XOR  SY( 7) )&amp;      (    SY( 1) XOR SY( 2)    XOR  SY( 8) )&amp;      ( SY( 0)       XOR SY( 1)    XOR SY( 3)                            XOR  SY( 9) )&amp;      ( SY( 0)    XOR SY( 2)                     XOR SY( 3)                            XOR  SY(10) )&amp;      (    SY( 1) XOR SY( 2)    XOR  SY(11) );MOD.sub.-- 07 :=  ( SY( 0)       XOR SY( 1)              XOR SY( 2)    XOR  SY( 4) )&amp;      ( SY( 0)           XOR SY( 3)                            XOR  SY( 5) )&amp;      ( SY( 0)           XOR SY( 3)                            XOR  SY( 6) )&amp;      (    SY( 1) XOR SY( 2)                     XOR SY( 3)                            XOR  SY( 7) )&amp;      (                  SY( 3) XOR  SY( 8) )&amp;      (           SY( 2) XOR SY( 3)                            XOR  SY( 9) )&amp;      (    SY( 1)        XOR SY( 3)                            XOR  SY(10) )&amp;      ( SY( 0)       XOR SY( 1)              XOR SY( 2)                     XOR SY( 3)                            XOR  SY(11) );MOD.sub.-- 08 :=  ( SY( 4)           XOR SY( 7)                            XOR  SY( 0) )&amp;      (    SY( 5) XOR SY( 6)                     XOR SY( 7)                            XOR  SY( 1) )&amp;      (    SY( 5) XOR SY( 6)                     XOR SY( 7)                            XOR  SY( 2) )&amp;      ( SY( 4)       XOR SY( 5)              XOR SY( 6)    XOR  SY( 3) )&amp;      (    SY( 5)        XOR SY( 7)                            XOR  SY( 8) )&amp;      ( SY( 4)       XOR SY( 5)              XOR SY( 6)                     XOR SY( 7)                            XOR  SY( 9) )&amp;      (    SY( 5)               XOR  SY(10) )&amp;      ( SY( 4)       XOR SY( 5)           XOR  SY(11) );MOD.sub.-- 09 :=  ( SY( 8)       XOR SY( 9)    XOR SY(11)                            XOR  SY( 0) )&amp;      ( SY( 8)    XOR SY(10)                     XOR SY(11)                            XOR  SY( 1) )&amp;      (    SY( 9) XOR SY(10)    XOR  SY( 2) )&amp;      ( SY( 8)       XOR SY( 9)    XOR SY(11)                            XOR  SY( 3) )&amp;      (                  SY(11) XOR  SY( 4) )&amp;      (           SY(10) XOR SY(11)                            XOR  SY( 5) )&amp;      (    SY( 9)        XOR SY(11)                            XOR  SY( 6) )&amp;      ( SY( 8)       XOR SY( 9)              XOR SY(10)                     XOR SY(11)                            XOR  SY( 7) );MOD.sub.-- 10 :=  ( SY( 4)       XOR SY( 5)              XOR SY( 6)                     XOR SY( 7)                            XOR  SY( 0) )&amp;      ( SY( 4)    XOR SY( 6)    XOR  SY( 1) )&amp;      ( SY( 4)       XOR SY( 5)           XOR  SY( 2) )&amp;      ( SY( 4)                  XOR  SY( 3) )&amp;      ( SY( 4)    XOR SY( 6)                     XOR SY( 7)                            XOR  SY( 8) )&amp;      (    SY( 5) XOR SY( 6)    XOR  SY( 9) )&amp;      ( SY( 4)       XOR SY( 5)    XOR SY( 7)                            XOR  SY(10) )&amp;      ( SY( 4)    XOR SY( 6)                     XOR SY( 7)                            XOR  SY(11) );MOD.sub.-- 11 :=  (           SY(10) XOR SY(11)                            XOR  SY( 0) )&amp;      (           SY(10)        XOR  SY( 1) )&amp;      ( SY( 8)       XOR SY( 9)              XOR SY(10)                     XOR SY(11)                            XOR  SY( 2) )&amp;      ( SY( 8)    XOR SY(10)    XOR  SY( 3) )&amp;      (    SY( 9) XOR SY(10)                     XOR SY(11)                            XOR  SY( 4) )&amp;      ( SY( 8)       XOR SY( 9)              XOR SY(10)    XOR  SY( 5) )&amp;      ( SY( 8)       XOR SY( 9)              XOR SY(10)    XOR  SY( 6) )&amp;      ( SY( 8)                  XOR  SY( 7) );MOD.sub.-- 12 :=  ( SY( 4)       XOR SY( 5)           XOR  SY( 0) )&amp;      ( SY( 4)                  XOR  SY( 1) )&amp;      (           SY( 6) XOR SY( 7)                            XOR  SY( 2) )&amp;      (           SY( 6)        XOR  SY( 3) )&amp;      (    SY( 5) XOR SY( 6)    XOR  SY( 8) )&amp;      ( SY( 4)       XOR SY( 5)    XOR SY( 7)                            XOR  SY( 9) )&amp;      ( SY( 4)    XOR SY( 6)                     XOR SY( 7)                            XOR  SY(10) )&amp;      (    SY( 5) XOR SY( 6)    XOR  SY(11) );MOD.sub.-- 13 :=  ( SY( 8)       XOR SY( 9)           XOR  SY( 0) )&amp;      ( SY( 8)                  XOR  SY( 1) )&amp;      (           SY(10) XOR SY(11)                            XOR  SY( 2) )&amp;      (           SY(10)        XOR  SY( 3) )&amp;      ( SY( 8)       XOR SY( 9)              XOR SY(10)    XOR  SY( 4) )&amp;      ( SY( 8)           XOR SY(11)                            XOR  SY( 5) )&amp;      ( SY( 8)           XOR SY(11)                            XOR  SY( 6) )&amp;      (    SY( 9) XOR SY(10)                     XOR SY(11)                            XOR  SY( 7) );MOD.sub.-- 14 :=  ( SY( 4)       XOR SY( 5)              XOR SY( 6)    XOR  SY( 0) )&amp;      ( SY( 4)           XOR SY( 7)                            XOR  SY( 1) )&amp;      ( SY( 4)           XOR SY( 7)                            XOR  SY( 2) )&amp;      (    SY( 5) XOR SY( 6)                     XOR SY( 7)                            XOR  SY( 3) )&amp;      (    SY( 5)               XOR  SY( 8) )&amp;      ( SY( 4)       XOR SY( 5)           XOR  SY( 9) )&amp;      (                  SY( 7) XOR  SY(10) )&amp;      (           SY( 6) XOR SY( 7)                            XOR  SY(11) );MOD.sub.-- 15 :=  (    SY( 9) XOR SY(10)    XOR  SY( 0) )&amp;      ( SY( 8)       XOR SY( 9)    XOR SY(11)                            XOR  SY( 1) )&amp;      ( SY( 8)    XOR SY(10)                     XOR SY(11)                            XOR  SY( 2) )&amp;      (    SY( 9) XOR SY(10)    XOR  SY( 3) )&amp;      (    SY( 9)               XOR  SY( 4) )&amp;      ( SY( 8)       XOR SY( 9)           XOR  SY( 5) )&amp;      (                  SY(11) XOR  SY( 6) )&amp;      (           SY(10) XOR SY(11)                            XOR  SY( 7) );MOD.sub.-- 16 :=  (                          SY( 4) )&amp;      (                          SY( 5) )&amp;      (                          SY( 6) )&amp;      (                          SY( 7) )&amp;      (                          SY( 8) )&amp;      (                          SY( 9) )&amp;      (                          SY(10) )&amp;      (                          SY(11) );MOD.sub.-- 17 :=  (                          SY( 0) )&amp;      (                          SY( 1) )&amp;      (                          SY( 2) )&amp;      (                          SY( 3) )&amp;      (                          SY( 8) )&amp;      (                          SY( 9) )&amp;      (                          SY(10) )&amp;      (                          SY(11) );MOD.sub.-- 18 :=  (                          SY( 0) )&amp;      (                          SY( 1) )&amp;      (                          SY( 2) )&amp;      (                          SY( 3) )&amp;      (                          SY( 4) )&amp;      (                          SY( 5) )&amp;      (                          SY( 6) )&amp;      (                          SY( 7) );__________________________________________________________________________ 
    
     FIG. 8 illustrates a set of module errors indicators MOD --  00, MOD --  01, . . . MOD --  18 74. Any error will cause the setting of one of the MOD&#39;s. For example an error in module 0 will cause MOD --  00 to be set to 1. During the decoding operations, bit error indicators are also generated from circuit lines which are later used to invert the fetched data bits to correct certain errors. Invert lines 81 INV --  H(0 . . . 31) 84, INV --  L(0 . . . 31), and INV --  C(0 . . . 11) are used in conjunction with bit errors so that when a bit error indicator is on, the corresponding data bit is corrected by inversion of the data. Bit error indicators 82 are generated from the following equations. 
     
         ______________________________________/********************** Invert Enabling ***********************/______________________________________INV.sub.-- H(0..3)        :=      MOD.sub.-- 00                          GATE SY(0..3);INV.sub.-- H(4..7)        :=      MOD.sub.-- 01                          GATE SY(0..3);INV.sub.-- H(8..11)        :=      MOD.sub.-- 02                          GATE SY(0..3);INV.sub.-- H(12..15)        :=      MOD.sub.-- 03                          GATE SY(0..3);INV.sub.-- H(16..19)        :=      MOD.sub.-- 04                          GATE SY(0..3);INV.sub.-- H(20..23)        :=      MOD.sub.-- 05                          GATE SY(0..3);INV.sub.-- H(24..27)        :=      MOD.sub.-- 06                          GATE SY(0..3);INV.sub.-- H(28..31)        :=      MOD.sub.-- 07                          GATE SY(0..3);INV.sub.-- L(0..3)        :=      MOD.sub.-- 08                          GATE SY(4..7);INV.sub.-- L(4..7)        :=      MOD.sub.-- 09                          GATE SY(8..11);INV.sub.-- L(8..11)        :=      MOD.sub.-- 10                          GATE SY(4..7);INV.sub.-- L(12..15)        :=      MOD.sub.-- 11                          GATE SY(8..11);INV.sub.-- L(16..19)        :=      MOD.sub.-- 12                          GATE SY(4..7);INV.sub.-- L(20..23)        :=      MOD.sub.-- 13                          GATE SY(8..11);INV.sub.-- L(24..27)        :=      MOD.sub.-- 14                          GATE SY(4..7);INV.sub.-- L(28..31)        :=      MOD.sub.-- 15                          GATE SY(8..11);INV.sub.-- C(0..3)        :=      MOD.sub.-- 16                          GATE SY(0..3);INV.sub.-- C(4..7)        :=      MOD.sub.-- 17                          GATE SY(4..7);INV.sub.-- C(8..11)        :=      MOD.sub.-- 18                          GATE SY(8..11);______________________________________ 
    
     In this manner, the status of the module error and the syndromes are to enable a plurality of invert lines and generate other signals pertaining to types of errors 78 including a UE (Uncorrectable error) signal 79 or a CE (Correctable Error) signal 77. 
     
         __________________________________________________________________________/**************************** Error Indication *****************************/ECC.sub.-- ANYE :=   SY(0)       |         SY(1)             |               SY(2)                   |                     SY(3)   SY(4)       |         SY(5)             |               SY(6)                   |                     SY(7)   SY(8)       |         SY(9)             |               SY(10)                   |                     SY(11)                         ;ECC.sub.-- CE   := (      MOD.sub.-- 00 |            MOD.sub.-- 01 |                  MOD.sub.-- 02 |                        MOD.sub.-- 03 |      MOD.sub.-- 04 |            MOD.sub.-- 05 |                  MOD.sub.-- 06 |                        MOD.sub.-- 07 |      MOD.sub.-- 08 |            MOD.sub.-- 09 |                  MOD.sub.-- 10 |                        MOD.sub.-- 11 |      MOD.sub.-- 12 |            MOD.sub.-- 13 |                  MOD.sub.-- 14 |                        MOD.sub.-- 15 |      MOD.sub.-- 16 |            MOD.sub.-- 17 |                  MOD.sub.-- 18 |                            );ECC.sub.-- UCE   := ECC.sub.-- ANYE &amp;  ECC.sub.-- CE;/********************************************************************//*&gt;INVERT  AND FETCH.sub.-- ECC.sub.-- OUTPUT     &lt;*//***********************************************************************/STEP3.sub.-- IN.sub.-- H(0..31) := MDRMUX.sub.-- OUT.sub.-- H(0..31) XORINV.sub.-- H(0..31);STEP3.sub.-- IN.sub.-- L(0..31) := MDRMUX.sub.-- OUT.sub.-- L(0..31) XORINV.sub.-- L(0..31);STEP3.sub.-- IN.sub.-- C(0..11) := MDRMUX.sub.-- OUT.sub.-- C(0..11) XORINV.sub.-- C(0..11);__________________________________________________________________________ 
    
     FIG. 9 illustrates the arrangement of data in the memory modules on the SIMMs. There are 19 memory modules in a SIMM; a number of SIMMs can therefore be configured in this way into the memory. As illustrated, the data bits and check bits are divided into 4 bit symbols to store in 19 memory modules. SEC --  O --  H(0 . . . 31) are stored in modules 1 to 8, SEC --  O --  L(0 . . . 31) are stored in modules 9 to 16, and SEC --  O --  C(0 . . . 11) are stored in modules 17 to 19. The mapping of system address bits to memory modules depends on the module size as shown in Table IV and FIG. 9. 
     While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.