Abstract:
A memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device is disclosed. In one embodiment, the memory device includes at least one evaluation circuit for amplifying a signal resulting from the reading of a memory cell, and a device for precharging an output of the evaluation circuit to a predetermined voltage level.

Description:
BACKGROUND  
       [0001]    The invention relates to a memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device. 
         [0002]    In the case of conventional memory devices, including conventional semiconductor memory devices, one differentiates between so-called functional memory devices (e.g. PLAs, PALs, etc.), and so-called table memory devices, e.g. ROM devices (ROM=Read Only Memory)—including PROMs, EPROMs, EEPROMs, flash memories, etc.—, and RAM devices (RAM=Random Access Memory), e.g. DRAMs and SRAMs. 
         [0003]    A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address again later. 
         [0004]    Since as many memory cells as possible are to be accommodated in a RAM device, one has been trying to realize them as simple as possible. 
         [0005]    In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g. of few, for instance 6, transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element (e.g. a trench capacitor) with the capacitance of which one bit can be stored as charge. 
         [0006]    This charge, however, remains for a short time only. Therefore, a so-called “refresh” must be performed regularly, e.g., approximately every 64 ms. 
         [0007]    In contrast to that, no “refresh” has to be performed in the case of SRAMs, i.e., the data stored in the memory cells remains stored as long as an appropriate supply voltage is fed to a respective SRAM. 
         [0008]    In the case of non-volatile memory devices (NVMs), e.g. EPROMs, EEPROMs, flash memories, OTPs, etc., however, the stored data remains stored even when the supply voltage is switched off. 
         [0009]    The memory cells provided in the above-mentioned memory devices are each adapted to be connected to corresponding bit lines so as to transmit a data value to be read out from a memory cell or a data value to be written into a memory cell. 
         [0010]    On reading out a memory cell, an access transistor connected with a memory cell is first of all connected through by the activation or selection, respectively, of a word line, and the charge state stored in the memory cell is applied to the bit line. Later, the weak signal coming from the memory cell is amplified by a sense amplifier/evaluated by an evaluator circuit, respectively. 
         [0011]    In the sense amplifier/evaluator circuit, the read current (Icell) resulting from the reading of a memory cell e.g. may be compared with a reference current (Iref), e.g. by use of respective current mirror devices. 
         [0012]    The current mirror devices, e.g., might be connected to a supply voltage (Usupply), and to ground (VSS, e.g., 0V). 
         [0013]    Further, the output of the current mirror devices might be connected to respective inverters. 
         [0014]    If the read current (Icell) is bigger than the reference current (Iref), a voltage (Uver) at the output of the current mirror devices, i.e., the input of the inverters, is driven to the value of the above supply voltage (Usupply). Hence, e.g., a “logic 1” is output at the output of the inverters. 
         [0015]    If, however, the read current (Icell) is smaller than the reference current (Iref), the voltage (Uver) at the output of the current mirror devices, i.e., the input of the inverters, is driven to ground, e.g., 0V. Hence, e.g., a “logic 0” is output at the output of the inverters. 
         [0016]    Prior to the reading out of the memory cell, the corresponding bit line is precharged to a predetermined voltage (Uref), e.g. by a so-called precharge circuit that is connected with the corresponding bit line. 
         [0017]    This—due to the parasitic capacitances of the bit line—takes a certain time t 1  (“bit line charge time”). 
         [0018]    During the bit line charge time t 1 , the voltage (Uver) at the output of the current mirror devices—as becomes clear from the explanations above—either has the value of the supply voltage (Usupply), or has a value of 0V (ground). 
         [0019]    When reading out the memory cell, the voltage (Uver) at the output of the current mirror devices—as also becomes clear from the explanations above, and depending on the result of the above comparison between the read current (Icell) and the reference current (Iref)—might change e.g. from the value of the supply voltage (Usupply) to ground, e.g., 0V, or vice versa, i.e., from ground, to the value of the supply voltage (Usupply). 
         [0020]    The state of the inverters e.g. might change when the voltage (Uver) at the output of the current mirror devices reaches 0.5*Usupply. Alternatively, for safety reasons; measures might be taken that ensure that the state of the inverters does not change before the voltage (Uver) at the output of the current mirror devices reaches 0.25*Usupply or 0.75*Usupply, respectively. 
         [0021]    To charge the input of the inverters to 0.25*Usupply or 0.75*Usupply, respectively—due to respective parasitic capacitances—again takes a certain time t 2  (“evaluation time”). 
         [0022]    Further, the above inverters lead to a respective additional delay τ gate delay  of the output signal (“gate delay time”). 
         [0023]    Hence, in total, the reading out of a memory cell might take a considerably long amount of time t 1 +t 2 +τ gate delay . 
         [0024]    For these or other reasons, there is a need for the present invention. 
       SUMMARY  
       [0025]    One embodiment provides a memory device having at least one evaluation circuit for amplifying a signal resulting from the reading of a memory cell, and a device for precharging an output of the evaluation circuit to a predetermined voltage level. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0026]    The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. 
           [0027]      FIG. 1  illustrates a schematic representation of a section of a conventional memory device. 
           [0028]      FIG. 2  is a signal diagram illustrating the time course of a plurality of voltages occurring during the reading out of a memory cell in the memory device illustrated in  FIG. 1 . 
           [0029]      FIG. 3  illustrates a schematic representation of a section of a memory device in accordance with an embodiment of the invention. 
           [0030]      FIG. 4  illustrates a signal diagram illustrating the time course of a plurality of voltages occurring during the reading out of a memory cell in the memory device illustrated in  FIG. 2 . 
           [0031]      FIG. 5  illustrates a more detailed view of an embodiment of the section of the memory device illustrated in  FIG. 3 , and a respective bit line precharge circuit. 
       
    
    
     DETAILED DESCRIPTION  
       [0032]    In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or other changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
         [0033]      FIG. 1  illustrates a schematic representation of a section of a memory device  1 , including elements used during the reading out of a memory cell of the memory device. 
         [0034]    The memory device may for instance be a RAM device (RAM=Random Access Memory), e.g., a DRAM or SRAM, or a non-volatile memory device, e.g., a PROM, EPROM, EEPROM, flash memory, or OTP, etc. 
         [0035]    As is illustrated in  FIG. 1 , the memory device  1  including a sense amplifier/evaluator circuit with two current mirror devices  2   a,    2   b.    
         [0036]    The current mirror device  2   a  includes two transistors (two PMOS field-effect transistors  3   a,    3   b ). 
         [0037]    Correspondingly similar, the current mirror device  2   b  includes two transistors (here: two NMOS field-effect transistors  8   a,    8   b ). 
         [0038]    The source of the PMOS field-effect transistor  3   a  is connected via a line  4  to a supply voltage (Usupply), and via a line  5  to the source of the PMOS field-effect transistor  3   b.    
         [0039]    The drain of the PMOS field-effect transistor  3   b  is connected via lines  6 ,  7  to the drain of the NMOS field-effect transistor  8   b,  and via a line  9 , which is used as an output of the current mirror devices  2   a,    2   b,  to an input of an inverter  9   a.    
         [0040]    The output of the inverter  9   a  is connected to an input of a further inverter  9   b,  the output of which is connected to an output line  17 . 
         [0041]    The source of the NMOS field-effect transistor  8   b  is connected via a line  10  to ground (VSS, e.g., 0V), and to the source of the NMOS field-effect transistor  8   a.    
         [0042]    Further, the gate of the NMOS field-effect transistor  8   b  is connected via a line  11  to the gate of the NMOS field-effect transistor  8   a,  and via a line  12  to the drain of the NMOS field-effect transistor  8   a,  and to a line  13 , to which as will be explained below a reference current (Iref) might be applied. 
         [0043]    Correspondingly similar, the gate of the PMOS field-effect transistor  3   b  is connected via a line  14  to the gate of the PMOS field-effect transistor  3   a,  and via a line  15  to the drain of the PMOS field-effect transistor  3   a,  and to a line  16 , which is connected or is connectable to a bit line, and to which as will be explained below—when reading out a respective memory cell—a read current (Icell) might be applied. 
         [0044]    The memory device  1  may includes one or several memory cell arrays, each including a plurality of memory cells arranged in respective parallel rows and columns. 
         [0045]    The memory cells provided in the above-mentioned memory cell arrays are each adapted to be connected to corresponding bit lines so as to transmit a data value to be read out from a memory cell or a data value to be written into a memory cell. 
         [0046]    On reading out a memory cell, an access transistor connected with a memory cell is first of all connected through by the activation or selection, respectively, of a word line, and the charge state stored in the memory cell is applied to the bit line. Later, the weak signal coming from the bit line is amplified by the above evaluator circuit with the two current mirror devices  2   a,    2   b.    
         [0047]    For this purpose, in the evaluator circuit with the two current mirror devices  2   a,    2   b,  the read current (Icell) present on the line  16  connected/connectable with the bit line, resulting from the reading of a memory cell (and fed to the first current mirror device  2   a,  see explanations above, and  FIG. 1 ) is compared with the reference current (Iref) present on the line  13  (fed to the second current mirror device  2   b,  see explanations above, and  FIG. 1 ). 
         [0048]    If the read current (Icell) is bigger than the reference current (Iref), a voltage (Uver) at the output  9  of the current mirror devices  2   a,    2   b,  i.e., the input of the inverter  9   a,  is driven to the value of the above supply voltage (Usupply). Hence, e.g., a “logic 1” is output at the output line  17  connected with the output of the inverters  9   a,    9   b  (or—alternatively—a “logic 0”). 
         [0049]    If, however, the read current (Icell) is smaller than the reference current (Iref), the voltage (Uver) at the output  9  of the current mirror devices  2   a,    2   b,  i.e., the input of the inverter  9   a,  is driven to ground, e.g., 0V. Hence, e.g., a “logic 0” is output at the output line  17  connected with the output of the inverters  9   a,    9   b  (or—alternatively—a “logic 1”). 
         [0050]    Prior to the reading out of the memory cell, and as is illustrated in  FIG. 2 , the voltage (Ubl) present on the corresponding bit line is precharged to a predetermined voltage (Uref), e.g. by a so-called precharge circuit that is connected with the corresponding bit line. This—due to the parasitic capacitances of the bit line, and as is illustrated in FIG.  2 —takes a certain time t 1  (“bit line charge time”). During the bit line charge time t 1 , the voltage (Uver) at the output  9  of the current mirror devices  2   a,    2   b —as becomes clear from the explanations above—either has the value of the supply voltage (Usupply), or has a value of 0V. 
         [0051]    When reading out the memory cell, the voltage (Uver) at the output  9  of the current mirror devices  2   a,    2   b —as also becomes clear from the explanations above, and depending on the result of the above comparison between the read current (Icell) and the reference current (Iref)—might change e.g. from the value of the supply voltage (Usupply) to ground, e.g., 0V, or vice versa, i.e., from ground, to the value of the supply voltage (Usupply). 
         [0052]    The state of the inverters  9   a,    9   b  connected with the output  9  of the current mirror devices  2   a,    2   b  e.g. might change when the voltage (Uver) at the output  9  of the current mirror devices  2   a,    2   b  reaches 0.5*Usupply. Alternatively, for safety reasons, measures might be taken that ensure that the state of the inverters  9   a,    9   b  does not change before the voltage (Uver) at the output  9  of the current mirror devices  2   a,    2   b  reaches 0.25*Usupply or 0.75*Usupply, respectively (see  FIG. 2 ). For this purpose, e.g. a Schmitt-Trigger might be used (instead of or in addition to the inverters  9   a,    9   b ). Additionally or alternatively, for example, a Flip-Flop may be used connected with the output line  17 , which is evaluated after a predetermined “safety time”, only. 
         [0053]    To charge the input of the inverters  9   a,    9   a /Schmitt Trigger to 0.25*Usupply or 0.75*Usupply, respectively—due to respective parasitic capacitances  20  e.g. of the lines  6 ,  7 ,  9 , the transistors  3   b,    8   b,  the inverter  9   a,  etc.—again takes a certain time t 2  (“evaluation time”) (in the present case, approximately 1.4 RC). Further,—as also illustrated in FIG.  2 —the above inverters  9   a,    9   b  lead to a respective additional delay τ gate delay  (“gate delay time”) of the output signal, i.e., a voltage U DO  output at the output line  17 . Hence, in total, the reading out of a memory cell might take a considerably long amount of time t 1 +t 2 +τ gate delay . 
         [0054]      FIG. 3  illustrates a schematic representation of a section of a memory device  101  in accordance with an embodiment of the invention, including elements used during the reading out of a memory cell of the memory device. 
         [0055]    The memory device may for instance be a RAM device (RAM=Random Access Memory), e.g., a DRAM or SRAM, or a non-volatile memory device, e.g. a PROM, EPROM, EEPROM, flash memory, or OTP, etc. 
         [0056]    As is illustrated in  FIG. 3 , the memory device  101  including a sense amplifier/evaluator circuit with two current mirror devices  102   a,    102   b  (and a plurality of additional sense amplifiers/evaluator circuits, constructed identically or similarly as the evaluator circuit illustrated in  FIG. 3 ). 
         [0057]    The current mirror device  102   a  includes two transistors (here: two PMOS field-effect transistors  103   a,    103   b ). 
         [0058]    Correspondingly similar, the current mirror device  102   b  includes two transistors (here: two NMOS field-effect transistors  108   a,    108   b ). 
         [0059]    In one embodiment, instead of the PMOS field-effect transistors  103   a,    103   b,  respective NMOS field-effect transistors could be used, and—correspondingly—instead of the NMOS field-effect transistors  108   a,    108   b,  respective PMOS field-effect transistors, etc. (e.g., in the case of a negative supply voltage Usupply (see below)). 
         [0060]    The source of the PMOS field-effect transistor  103   a  is connected via a line  104  to a supply voltage (Usupply), and via a line  105  to the source of the PMOS field-effect transistor  103   b.    
         [0061]    The drain of the PMOS field-effect transistor  103   b  is connected via lines  106 ,  107  to the drain of the NMOS field-effect transistor  108   b,  and via a line  109 , which is used as an output of the current mirror devices  102   a,    102   b,  to an input of an inverter  109   a.    
         [0062]    Further, as will be explained in greater detail below, the drain of the PMOS field-effect transistor  103   b  (and hence, the lines  106 ,  107 ,  109 , and the drain of the NMOS field-effect transistor  108   b,  as well as the input of the inverter  109   a ) in addition via a line  203  is connected to a switching device  201 . 
         [0063]    As a switching device  201 , e.g., a transistor may be used (here: a PMOS field-effect transistor (alternatively, e.g., a NMOS field-effect transistor)), or e.g. a transmission gate, etc. 
         [0064]    In one embodiment, the above line  203 , i.e., the lines  106 ,  107 ,  109 , the transistors  103   b,    108   b,  and the inverter  109   a  may be connected to the source-drain path of the transistor  201  (here: the source of the PMOS field-effect transistor (or alternatively, the drain of a respective NMOS field-effect transistor)). 
         [0065]    A control input of the switching device  201  (here: the gate of the PMOS field-effect transistor  201 ) is connected via a control line  204  to a control device  202  (here: an evaluator circuit output precharge control device  202 ). 
         [0066]    As is further illustrated in  FIG. 3 , the switching device  201  via a line  206  in addition is connected to a voltage supply  205 , providing a constant voltage of Uschalt. 
         [0067]    The above line  206 , i.e., the voltage supply  205  may be connected to the source-drain path of the transistor  201  (here: the drain of the PMOS field-effect transistor (or alternatively, the source of a respective NMOS field-effect transistor)). 
         [0068]    The voltage Uschalt provided by the voltage supply  205  may e.g. be approximately 0.5*Usupply, i.e., approximately half the supply voltage Usupply to which the first current mirror device  102   a  is connected (and/or e.g. half of the sum of the supply voltage Usupply and the ground voltage VSS (see below)). 
         [0069]    As will be described in further detail below, when the control device  202  brings the control line  204  in a first state (e.g., “logic 0” (or—alternatively—“logic 1”)), the switching device  201 /transistor  201  is activated/switched on, such that the voltage supply  205 —and hence, the voltage Uschalt—is electrically conductively coupled to the line  203 . 
         [0070]    Further, as also will be described in further detail below, when the control device  202  brings the control line  204  in a second state, different from the first state (e.g., “logic 1” (or—alternatively—“logic 0”)), the switching device  201 /transistor  201  is deactivated/switched off, such that the voltage supply  205 —and hence, the voltage Uschalt—is decoupled from the line  203  (i.e., no conductive connection is provided between the voltage supply  205 , and the line  203 ). 
         [0071]    As is further illustrated in  FIG. 3 , the output of the inverter  109   a  is connected to an input of a further inverter  109   b,  the output of which is connected to an output line  117 . 
         [0072]    Alternatively, more or less than two inverters may be provided, e.g., one single inverter (or no inverters at all). 
         [0073]    The source of the NMOS field-effect transistor  108   b  is connected via a line  110  to ground (i.e., to the above ground voltage VSS, e.g., 0V), and to the source of the NMOS field-effect transistor  108   a.    
         [0074]    Further, the gate of the NMOS field-effect transistor  108   b  is connected via a line  111  to the gate of the NMOS field-effect transistor  108   a,  and via a line  112  to the drain of the NMOS field-effect transistor  108   a,  and to a line  113 , to which as will be explained below a reference current (Iref) might be applied. 
         [0075]    Correspondingly similar, the gate of the PMOS field-effect transistor  103   b  is connected via a line  114  to the gate of the PMOS field-effect transistor  103   a,  and via a line  115  to the drain of the PMOS field-effect transistor  103   a,  and to a line  116 , which is connected or is connectable to a bit line, and to which as will be explained below—when reading out a respective memory cell—a read current (Icell) might be applied. 
         [0076]    The memory device  101  may include one or several memory cell arrays, each including a plurality of memory cells arranged in respective parallel rows and columns. 
         [0077]    The memory cells provided in the above-mentioned memory cell arrays are each adapted to be connected to corresponding bit lines so as to transmit a data value to be read out from a memory cell or a data value to written into a memory cell. 
         [0078]    On reading out a memory cell, an access transistor connected with the memory cell is first of all connected through by the activation or selection, respectively, of a word line, and the charge state stored in the memory cell is applied to the bit line. Later, the weak signal coming from the bit line is amplified by the above evaluator circuit with the two current mirror devices  102   a,    102   b.    
         [0079]    For this purpose, in the evaluator circuit with the two current mirror devices  102   a,    102   b,  the read current (Icell) present on the line  116  connected/connectable with the bit line, resulting from the reading of a memory cell (and fed to the first current mirror device  102   a,  see explanations above, and  FIG. 3 ) is compared with the reference current (Iref) present on the line  113  (fed to the second current mirror device  102   b,  see explanations above, and  FIG. 3 ). 
         [0080]    If the read current (Icell) is bigger than the reference current (Iref), a voltage (Uver) at the output  109  of the current mirror devices  102   a,    102   b,  i.e., the input of the inverter  109   a,  is driven to the value of the above supply voltage (Usupply). Hence, e.g., a “logic 1” is output at the output line  117  connected with the output of the inverters  109   a,    109   b  (or—alternatively—a “logic 0”). 
         [0081]    If, however, the read current (Icell) is smaller than the reference current (Iref), the voltage (Uver) at the output  109  of the current mirror devices  102   a,    102   b,  i.e., the input of the inverter  109   a,  is driven to ground, e.g., 0V. Hence, e.g., a “logic 0” is output at the output line  117  connected with the output of the inverters  109   a,    109   b  (or—alternatively—a “logic 1”). 
         [0082]    Prior to the reading out of the memory cell, e.g., starting at a time t 0  illustrated in  FIG. 4 , the voltage (Ubl) present on the corresponding bit line is precharged to a predetermined voltage (Uref), e.g. by a respective precharge circuit that is connected with the corresponding bit line. This—due to the parasitic capacitances of the bit line, and as is illustrated in FIG.  4 —takes a certain time t 1  (“bit line charge time”). 
         [0083]    Starting, e.g., in parallel to the above precharging of the bit line to the above predetermined voltage (Uref) (e.g., also e.g. starting at the above time t 0 )—and hence, as illustrated in  FIG. 4 , also prior to reading out the memory cell, and while the above bit line is charged—the control device  202  brings the control line  204  from the above second to the above first state (e.g., “logic 0” (or—alternatively—“logic 1”), such that the switching device  201 /transistor  201  is activated/switched on, and the voltage supply  205 —and therefore, the voltage Uschalt—is electrically conductively coupled to the line  203 . 
         [0084]    Hence, as is illustrated in  FIG. 4 , the voltage (Uver) at the output  109  of the current mirror devices  102   a,    102   b —which as becomes clear from the explanations above at the above time t 0  either has the value of the supply voltage (Usupply), or a value of 0V (ground)—is charged to the above voltage Uschalt provided by the voltage supply  205 , i.e., approximately 0.5*Usupply (“output precharge voltage”). 
         [0085]    As is illustrated in  FIG. 4 , the voltage (Uver) at the output  109  of the current mirror devices  102   a,    102   b  reaches the above value 0.5*Usupply (output precharge voltage) at a time time t 0,1 , i.e., before the bit line is precharged to the above predetermined bit line precharge voltage (Uref), and hence, before the time t 1  (“bit line charge time”). 
         [0086]    As is further illustrated in  FIG. 4 , and as will be described in further detail below, e.g., when the voltage at the bit line reaches a certain, further predetermined value (Upre), and/or e.g. starting at a time t 0,2 —after the time t 0,1  at which the output  109  of the current mirror devices  102   a,    102   b  reaches the above value 0.5*Usupply (output precharge voltage), and before or short before or when the bit line is precharged to the above predetermined bit line precharge voltage (Uref), i.e., before or short before or after the time t 1  (“bit line charge time”), the control device  202  brings the control line  204  from the above first state back to the above second state (e.g., “logic 1” (or—alternatively—“logic 0”)). Hence, the switching device  201 /transistor  201  is deactivated/switched off, and the voltage supply  205 —and therefore, the voltage Uschalt—is decoupled from the line  203 . 
         [0087]    The above further, predetermined value Upre e.g. might be chosen such that it is e.g. just a little bit smaller, than the value of the bit line precharge voltage Uref. For instance, Upre might be chosen such that it is between 0.8*Uref and 0.99*Uref, or for instance, between 0.9*Uref and 0.95*Uref, etc., etc. 
         [0088]    When the bit line was precharged to the above predetermined bit line precharge voltage (Uref), i.e., at the above time t 1  (“bit line charge time”)—or even before, e.g., at the above time t 0,2 , or between the above times t 0,2  and t 1 , etc.—the evaluation/reading out of the memory cell is started. 
         [0089]    Hence, the voltage (Uver) at the output  109  of the current mirror devices  102   a,    102   b —corresponding to the explanations above, and depending on the result of the above comparison between the read current (Icell) and the reference current (Iref)—then changes from the above value 0.5*Usupply (output precharge voltage) (reached at the above time t 0,2  already) to ground, e.g., 0V, or to the value of the supply voltage (Usupply). 
         [0090]    Correspondingly similar as was explained above in connection with  FIG. 1 , the state of the inverters  109   a,    109   b  connected with the output  109  of the current mirror devices  102   a,    102   b  e.g. might change when the voltage (Uver) at the output  109  of the current mirror devices  102   a,    102   b  reaches 0.5*Usupply. Alternatively, for safety reasons, measures might be taken that ensure that the state of the inverters  109   a,    109   b  does not change before the voltage (Uver) at the output  109  of the current mirror devices  102   a,    102   b  reaches 0.25*Usupply or 0.75*Usupply, respectively (see  FIG. 4 ). For this purpose, e.g. a Schmitt-Trigger might be used (instead of or in addition to the inverters  109   a,    109   b ). Additionally or alternatively, for example, a Flip-Flop may be used connected with the output line  117 , which is evaluated after a predetermined “safety time”, only. 
         [0091]    In one embodiment of the memory device  101  illustrated in  FIG. 3 , the time t 3 —illustrated in FIG.  4 —that is necessary to charge the input of the inverters  109   a,    109   b  to 0.25*Usupply or 0.75*Usupply, respectively is smaller, than the above “evaluation time” t 2 —illustrated in FIG.  2 —in the memory device  1  illustrated in  FIG. 1  (even though respective parasitic capacitances  120  e.g. of the lines  106 ,  107 ,  109 , the transistors  103   b,    108   b,  and the inverter  109   a  of the memory device  101  of  FIG. 3  might be correspondingly similar as the respective parasitic capacitances  20  caused, e.g., by the lines  6 ,  7 ,  9 , the transistors  3   b,    8   b,  and the inverter  9   a  of the memory device  1  illustrated in  FIG. 1 ). 
         [0092]    The reason is that due to the above precharge of the output  109  of the current mirror devices  102   a,    102   b  to the above value 0.5*Usupply (output precharge voltage) the output  109  of the current mirror devices  102   a,    102   b  in the memory device  101  illustrated in  FIG. 3  needs only to change from the above value 0.5*Usupply (output precharge voltage) to 0.25*Usupply or 0.75*Usupply, respectively (and not from 0V to 0.75*Usupply, or Usupply to 0.25*Usupply, respectively, as is the case in the memory device  1  illustrated in  FIG. 1 ). 
         [0093]    Hence, as illustrated in  FIG. 4 , in the memory device  101  illustrated in  FIG. 3 , the above time t 3  that is necessary to charge the input of the inverters  109   a,    109   a  from 0.5*Usupply to 0.25*Usupply or 0.75*Usupply may e.g. only be approximately 0.75 RC (while in the memory device  1  illustrated in  FIG. 1 , as mentioned above, the “evaluation time” t 2  e.g. may be approximately 1.4 RC). 
         [0094]    In the memory device  101  illustrated in  FIG. 3 , correspondingly similar as is the case in the memory device  1  illustrated in  FIG. 1 , the above inverters  109   a,    109   b  lead to a respective additional delay τ gate delay  (“gate delay time”) of the output signal, i.e., a voltage U DO  output at the output line  117  of the memory device  101  (see  FIG. 4 ). However, as the time t 3  that is necessary to charge the input of the inverters  109   a,    109   a  from 0.5*Usupply to 0.25*Usupply or 0.75*Usupply as explained above in the memory device illustrated in  FIG. 3  is considerably smaller, than the “evaluation time” t 2  in the memory device  1  illustrated in  FIG. 1 , and as also from a respective comparison of the  FIGS. 2 and 4 , the reading out of a memory cell in the memory device  101  is considerably faster, than in the memory device  1  (and e.g. might only take the amount of time t 1 +t 3 +τ gate delay  (or less), versus t 1 +t 2 +τ gate delay  as is the case in the memory device  1 ). 
         [0095]      FIG. 5  illustrates a more detailed view of an embodiment of the section of the memory device  101  illustrated in  FIG. 3 , and a respective bit line precharge circuit  1005 , coupled to the line  116  of the memory device  101 , and connected or connectable with the corresponding bit line. 
         [0096]    In one embodiment illustrated in  FIG. 5 , the bit line precharge circuit  1005 —mentioned with respect to  FIG. 3 , already, and used to charge the voltage (Ubl) present on the corresponding bit line to the above predetermined voltage (Uref) during the above bit line charge time ti—comprises an operational amplifier  1002 , and a transistor  1003 , e.g. a respective NMOS field-effect transistor (or, alternatively, a PMOS field-effect transistor, etc.). 
         [0097]    The drain-source path of the transistor  1003  (in particular, the drain of the NMOS field-effect transistor) is connected to the above line  116 , i.e., the drain and gate of the PMOS field-effect transistor  103   a,  and the gate of the PMOS field-effect transistor  103   b.    
         [0098]    Further, a gate of the NMOS field-effect transistor  1003  is connected to the output of the operational amplifier  1002 . 
         [0099]    A first input of the operational amplifier  1002  (e.g., a minus-input thereof) is connected to a line  1002   a,  to which a constant voltage with the value of the above predetermined voltage Uref might be applied. 
         [0100]    As is further illustrated in  FIG. 5 , the respective bit line is connected or connectable to a line  1006 , which is connected via a line  1002   b  to a second input of the operational amplifier  1002  (e.g., a plus-input thereof), via a line  1007  to the source-drain path of the transistor  1003  (to the source of the respective NMOS field-effect transistor  1003 ), and—as will be described in further detail below—via a line  1004   a  to a first input of an additional operational amplifier  1004  (e.g., a minus-input thereof). 
         [0101]    By the operational amplifier  1002 , and the transistor  1003 ,—correspondingly similar as in conventional memory devices—the value of the voltage present on the line  1006 —and hence, the bit line, i.e., the above bit line voltage Ubl (after connection of the bit line with the line  1006 , e.g. by use of a further transistor (not illustrated))—is regulated/precharged to the above value Uref (bit line charge time t 1 , see  FIG. 4 ). 
         [0102]    In the specific embodiment illustrated in  FIG. 5 , the above additional operational amplifier  1004  functions as “switching control device  202 ” (illustrated in  FIG. 3 ). 
         [0103]    As is illustrated in  FIG. 5 , a second input of the additional operational amplifier  1004  (e.g., a plus-input thereof) is connected to a line  1004   b,  to which a constant voltage with the value of the above further, predetermined voltage Upre might be applied. 
         [0104]    The output of the additional operational amplifier  1004  is connected via a line  1008  with the control line  204  (i.e., the gate of the transistor  201 ), and—as will be described below—via the line  1008 , and a line  1009  to a control input of the inverter  109   a.    
         [0105]    In the additional operational amplifier  1004 , the voltage present on the lines  1006 ,  1004   a —and hence, the bit line, i.e., the bit line voltage Ubl (after connection of the bit line with the line  1006 , see above)—is compared with the further, predetermined voltage Upre present on line  1004   b.    
         [0106]    As is illustrated in  FIG. 4 , at the beginning of the above bit line charge time t 1 , the value of the bit line voltage Ubl is still smaller, than the value of the further, predetermined voltage Upre present on line  1004   b.    
         [0107]    Therefore, the output of the additional operational amplifier  1004 —and therefore, also the lines  1008 ,  1009 ,  204 —are in the above first state (e.g., “logic 0” (or—alternatively—“logic 1”)). 
         [0108]    Due to the above first state (e.g., “logic 0” (or—alternatively—“logic 1”)) of the line  204 , the switching device  201 /transistor  201  is activated/switched on, and the voltage supply  205 —and therefore, the voltage Uschalt—is electrically conductively coupled to the line  203 . 
         [0109]    Further, due to the above first state (e.g., “logic 0” (or—alternatively—“logic 1”)) of the line  1009 , the inverter  109   a  is deactivated/switched off, such that the inverter  109   a  does not evaluate the signal present on its input  109 . 
         [0110]    As is further illustrated in  FIG. 4 , during the above bit line charge time t 1 , the bit line voltage Ubl continues to grow. At the end of the above bit line charge time t 1  (here: at the above time t 0,2 ), the value of the bit line voltage Ubl gets bigger, than the value of the further, predetermined voltage Upre present on line  1004   b.    
         [0111]    Therefore, the output of the additional operational amplifier  1004 —and therefore, also the lines  1008 ,  1009 ,  204 —changes from the above first state to the above second state (e.g., “logic 1” (or—alternatively—“logic 0”)). 
         [0112]    Due to the above second state (e.g., “logic 1” (or—alternatively—“logic 0”)) of the line  204 , the switching device  201 /transistor  201  is deactivated/switched off, and the voltage supply  205 —and therefore, the voltage Uschalt—is decoupled from the line  203 . 
         [0113]    Further, due to the above second state (e.g., “logic 1” (or—alternatively—“logic 0”)) of the line  1009 , the inverter  109   a  is activated/switched on, such that the inverter  109   a  as explained above starts to evaluate the signal present on its input  109 . 
         [0114]    In an additional alternative embodiment, the lines  1008 ,  1009 ,  204  (i.e., the switching device  201 , and the inverter  109   a ) are not controlled by an operational amplifier  1004  as illustrated in FIG.  5 /a signal generated by such operational amplifier  1004 , but by a clock generator/a clock signal, e.g. by a clock signal which is in a predefined time relationship with regard to a clock signal used for evaluating the voltage U DO  output at the output line  117 . 
         [0115]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments illustrated and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.