Abstract:
An apparatus comprising a Darlington transistor pair and a bias circuit. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The bias circuit may be coupled between an output transistor of said Darlington transistor pair and the input node. The bias circuit generally comprises (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of the bias transistor and base of the output transistor.

Description:
[0001]     This is a continuation of U.S. Ser. No. 10/623,070, filed Jul. 18, 2003. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to amplifiers generally and, more particularly to a method and/or architecture for implementing a self-biased Darlington amplifier.  
       BACKGROUND OF THE INVENTION  
       [0003]     Conventional Darlington Amplifiers are often employed in a 3 terminal package (i.e., a SOT-89 package) or other 3 terminal style transistor package. Such amplifier packages are attractive because they typically have a small outline, a low cost, and a user-friendly implementation. Conventional 3-terminal transistor style packages typically allow one RF input, one RF output, and one reference ground terminal. The limited number of terminals imposes a constraint for bias solutions in Darlington amplifiers.  
         [0004]     Referring to  FIG. 1 , a circuit  10  illustrating a conventional Darlington gain block biasing scheme is shown. In the circuit  10 , an off-chip bias set Resistor RDC is used to set a nominal bias current Icc presented through a gain block  12 . The gain block  12  presents a signal OUT in response to a signal IN and the current Icc. Typically, the more voltage drop across the resistor RDC, the better the stability of the bias current Icc over temperature and supply variations.  
         [0005]     The DC bias set resistor RDC sets the total current bias of the circuit  10 . However, the DC bias set resistor RDC also creates a voltage drop, reducing the output voltage and RF headroom provided to the Darlington output stage.  
         [0006]     The external DC bias set resistor RDC has one or more of the following disadvantages (a) a limited output voltage swing and power output, (b) a limited DC bias ramp up with input power (inhibiting class B operation), and/or (c) the need for a user to provide the external DC bias set resistor to set the bias of the amplifier.  
         [0007]     Referring to  FIG. 2 , a more detailed diagram of the circuit  10  is shown. The larger the voltage drop across the resistor RDC, the lower the voltage applied to the collectors of the transistors Q 1  and Q 2  and the lower the value of the signal OUT. The reduced voltage swing of the signal OUT affects saturated output power, 1 dB compression, and output IP3 (third order intercept point).  
         [0008]     Moreover, for class AB, B, and C operation (e.g., where the current Icc increases with input power), the resistor RDC will drop even more voltage, reducing the maximum output power capability. Conventional bias schemes therefore need the user to optimize the value of the resistors RDC in order to meet specific design criteria. Conventional setting the bias involves a trade-off between DC stability and radio frequency (RF) performance.  
         [0009]     Referring to  FIG. 3 , a diagram illustrating the simulated current-voltage characteristics of a conventional Darlington bias circuit  10  is shown. A bias variation of 20 mA at 5V over a −25° C. to 25° C. temperature change is shown.  
         [0010]     Referring to  FIG. 4 , a diagram illustrating a measured current-voltage characteristics of conventional bias of the circuit of  FIG. 2  is shown. A bias variation of ˜8-9 mA at 5V over a 0 to 85° C. temperature change is shown. The instantaneous slope of the I-V curve at 5V illustrates bias sensitivity to the supply voltage.  
         [0011]     Referring to  FIG. 5 , a diagram illustrating measured S-parameters over temperature comparison of the convention approach is shown. The gain changes by less than 0.5 dB over an 85 C temperature (i.e., acceptable temperature gain variation).  
         [0012]     It would be desirable to have a fully self-biased amplifier that does not need an external bias set resistor RDC where the amplifier maintains or improves (i) output voltage headroom and RF swing, (ii) tolerance to supply and temperature variations, (iii) enables class AB, B, C dynamic bias operation, and/or (iv) may be implemented in a 3-terminal package (e.g., 5512) traditionally having one RF input, one RF output, and one ground.  
         [0013]     It would also be desirable to implement a self-bias solution for a Darlington amplifier that may (i) be implemented in a 3-terminal transistor style package such as the SOT-89, (ii) eliminate the need for an external DC bias resistor, and/or (iii) allow high output voltage headroom and output power.  
         [0014]     It would also be desirable to implement a self-bias solution that (i) has a lower sensitivity to temperature and supply voltage variation, and/or (ii) may be monolithically integrated with the Darlington amplifier to reduce size, cost, and/or complexity of integration.  
       SUMMARY OF THE INVENTION  
       [0015]     The present invention concerns an apparatus comprising a Darlington transistor pair and a bias circuit. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The bias circuit may be coupled between an output transistor of said Darlington transistor pair and the input node. The bias circuit generally comprises (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of the bias transistor and base of the output transistor.  
         [0016]     The objects, features and advantages of the present invention include providing self-biased Darlington amplifier that may (i) increase the voltage supplied to an output device, (ii) improve output power efficiency and linearity, (iii) reduce the temperature sensitivity (e.g., by a factor of 2 over conventional approaches), (iv) reduce the supply voltage sensitivity (e.g., by a factor of 2 over conventional approaches), (v) enable dynamic bias operation (e.g., class AB or B), (vi) be monolithically integrated to reduce size and/or cost, and/or (vii) be applied to 3.3V SiGe HBT and Si BJT Darlington gain blocks.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:  
         [0018]      FIG. 1  is a diagram of a conventional amplifier;  
         [0019]      FIG. 2  is a diagram illustrating a conventional Darlington amplifier and bias arrangement;  
         [0020]      FIG. 3  is a simulated current-voltage characteristic of the conventional bias arrangement of  FIG. 2 ;  
         [0021]      FIG. 4  is a diagram illustrating a measured current-voltage characteristic of the conventional bias arrangement of  FIG. 2 ;  
         [0022]      FIG. 5  is a diagram illustrating measured S-parameters over temperature comparison of the convention approach of  FIG. 2 ;  
         [0023]      FIG. 6  is a diagram illustrating a preferred embodiment of the present invention;  
         [0024]      FIG. 7  is a more detailed diagram of the present invention;  
         [0025]      FIG. 8  is a diagram illustrating simulated current-voltage characteristics of the present invention;  
         [0026]      FIG. 9  is a diagram illustrating a self-bias circuit applied to a thermally distributed Darlington amplifier;  
         [0027]      FIG. 10  illustrates a low noise embodiment of the invention that may provide an improvement in the noise performance of the embodiment of the invention illustrated in  FIGS. 6 and 7 ;  
         [0028]      FIG. 11  illustrates a noise improvement of the circuit of  FIG. 9  compared with the circuits of  FIGS. 6 and 7 ;  
         [0029]      FIG. 12  is a diagram illustrating a measured current-voltage characteristic of the self-bias approach of the present invention;  
         [0030]      FIG. 13  is a diagram illustrating measured S-parameter of the self-bias of the present invention; and  
         [0031]      FIG. 14  is a diagram illustrating measured output power, gain, and bias current of the present invention illustrating class AB operation. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]     The present invention may implement a self-bias Darlington Gain Block that may (i) eliminate a bias resistor (e.g., RDC), (ii) increase output voltage headroom, (iii) improve stability over temperature and supply voltage (e.g., Vcc) variations, and/or (iv) enable class AB biasing. In one example, the present invention may be implemented in a SOT-89 package. However, other packages, such as other 3-pin packages, may be implemented to meet the design criteria of a particular implementation.  
         [0033]     Referring to  FIG. 6 , a diagram of a circuit  100  illustrating a preferred embodiment of the present invention is shown. The circuit  100  generally comprises a Darlington gain block  102 , a capacitor (e.g., C_BYPASS) and an inductor  104 . The inductor  104  may provide a radio frequency (RF) choke. The Darlington gain block  102  generally presents a signal (e.g., OUT) in response to a signal (e.g., IN) and a current presented through the inductor  104 . The circuit  100  is implemented without the resistance RDC shown in  FIG. 1  of the background section.  
         [0034]     Referring to  FIG. 7 , a more detailed diagram of the circuit  100  is shown. The circuit  100  illustrates a basic embodiment of the Self-biased Darlington amplifier in accordance with the present invention. A main amplifier may be implemented with a transistor Q 1  and a transistor Q 2 . A bias section (or circuit)  102  is generally connected between the emitter and base of the transistor Q 1 . The bias section  102  may be implemented as a self-bias feedback circuit. The circuit  100  also comprises parallel feedback resistor RFB, a series feedback resistor REE 2 , and bias resistor REE 1 . The bias resistor REE 1  may be used to bias the transistor Q 1 . The self-bias feedback circuit  102  may be used to stabilize the bias of the circuit  100  without relying on an external resistor (as in the conventional approach described in  FIG. 2 ).  
         [0035]     The self-bias feedback circuit  102  generally comprises a resistor (e.g., R_BLOCK), a transistor (e.g., Q_BIAS), a resistor (e.g., R_ISO), a resistor (e.g., REE_BIAS) and a capacitor (e.g., C_BYP 2 ). The resistor R_BLOCK may be implemented as an RF blocking resistor. The transistor Q_BIAS may be implemented as a biasing transistor. The resistor R_ISO may be implemented as an RF isolation. The emitter biasing resistor REE_BIAS may be coupled between the emitter of the transistor Q_BIAS and ground. The capacitor C_BYP 1  may be implemented as an AC bypass. The transistor Q_BIAS generally operates as a pseudo mirror bias transistor of the transistor Q 2 . The self-bias circuit  102  generally works in conjunction with the parallel feedback resistor RFB to set up a reference current (e.g., IBB). The current IBB is approximately mirrored to the output transistor Q 2 . The relationship between IBB and ICC 2  is only approximate, but generally mirror each other in current over temperature, supply voltage, and input drive level variations. The ratio of the areas of the transistor Q_BIAS and the transistor Q 2 , and the emitter resistors REE_BIAS and REE 2 , are generally scaled in proportion to the bias currents IBB and ICC 2 , respectively. For example, if the current IBB is 1 mA and the current ICC 2  is 100 mA, then the area of the transistor Q_BIAS may be implemented as 1/100 th  of the area of the transistor Q 2 . The resistor REE_BIAS will generally be 100 time the value of the resistor REE 2 , approximately. However, other ratios may be implemented to meet the design criteria of a particular implementation.  
         [0036]     The values of the resistor R_BLOCK and the resistor R_ISO are generally chosen for optimum RF performance versus DC bias sensitivity. For ideal RF performance, the resistor R_ISO should typically be greater than 10 Ω but less than 1,000 Ω. The value of the resistor R_BLOCK should typically be greater than 100 Ω but less than 10,000 Ω. DC stability may be forfeited in favor of RF performance (or vice versa) to obtain combinations outside of these ranges.  
         [0037]     The bypass capacitor C_BYP 1  and the blocking resistor R_BLOCK set the lower frequency limit of operation. The lower frequency may be extended by increasing either or both values of the capacitor C_BYP 1  and the resistor R_BLOCK. However, increasing the value of the resistance of the resistor R_BLOCK will generally degrade the bias mirroring relationship between the transistor Q_BIAS and the transistor Q 2 . In a sense, the self-biased amplifier  100  resembles a type of DC current mirror, except that the circuit  100  provides well defined RF input and output terminals. The DC mirror operation is less than ideal due to the RF blocking resistor.  
         [0038]     Referring to  FIG. 8 , a diagram illustrating the simulated current-voltage characteristics of the self-bias circuit of the present invention is shown. A 10 mA variation for the present invention is illustrated. The temperature sensitivity of the new self-bias circuit has been improved by a factor of 2 over the conventional bias approach of  FIG. 2 . The bias sensitivity of the present invention is generally a factor of 2 better than the conventional case.  
         [0039]     Referring to  FIG. 9 , a circuit  100  illustrates an embodiment of the invention is shown illustrating the self-bias circuit  102  applied to a thermally distributed Darlington amplifier. The distributed Darlington is a practical employment to improve the thermal and reliability performance of the chip by spatially distributing the hot component of the chip layout design. An example of a thermally distributed Darlington amplifier may be found in co-pending application Ser. No. 09/888,865, which is hereby incorporated by reference in its entirety.  
         [0040]     A plurality of RF blocking resistors (e.g., RDC_B, RDC_A, . . . ) which the couple DC bias from a plurality of Darlington input transistors (e.g., Q 1 A, Q 1 B, . . . ) to a single bias transistor Q_BIAS, which sets up the reference current for all the Darlington output transistors (e.g., Q 2 A, Q 2 B, . . . ).  
         [0041]     Referring to  FIG. 10 , a circuit  100 ″ is shown illustrating an example of a low noise embodiment of the invention. The circuit  100 ″ may improve the noise performance. An additional RF choke inductor (e.g., L 1 ) and bypass capacitor (e.g., C_BYP 2 ) may provide a low pass filter to filter out the high frequency noise contributions of the bias transistor Q_BIAS. The resistor R_ISO may also preserve the gain and return-loss performance at lower frequencies. The low frequency noise operation is generally determined by both the capacitor C_BYP 2  and the inductor L 1 . The higher the values, the lower the low-noise frequency of operation. Typically, the various components of the circuit  100 ″ may be integrated monolithically on a single chip. An external bypass capacitor (not shown) in parallel with the capacitor C_BYP 2  may be used to extend this lower frequency band edge.  
         [0042]     Referring to  FIG. 11 , a diagram illustrating the noise improvement gained by employing the additional filter components is shown. The curve  302  (e.g., No Choke(L 1 =0)) represents the noise figure performance obtained from the circuit  100  where the self-bias circuit is directly coupled to the input. The curve  306  (e.g., Ideal Choke Inductor (L 1 =Infinity)) represents the noise figure performance obtained from employing an ideal choke L 1 , with the circuit  100 ″. The curve  304  (e.g., “Finite Choke (L 1 =8 nH) and R_ISO=100 ohms) represents the noise figure performance obtained with a practical monolithic choke of 8 nH and isolation resistor of 100 ohms. The outer curves represent the achievable improvement in noise which can be gained by integrating an LRC filter with the self-bias circuit.  
         [0043]     Referring to  FIG. 12 , a diagram illustrating a measured current-voltage characteristic of self-bias of the present invention is shown. The bias sensitivity illustrates an improvement by a factor of two over the conventional case ( FIG. 3 ).  
         [0044]     Referring to  FIG. 13 , a diagram illustrating measured S-parameter of the self-bias of the present invention is shown. The gain and return loss sensitivity over temperature illustrates acceptable operation.  
         [0045]     The gain and return loss sensitivity over temperature is similar for both cases indicating that the new self-bias approach is as well behaved as the conventional approach. Gain for both cases changes by less than 0.5 dB over an 85 C temperature change indicating good temperature gain insensitivity.  
         [0046]     Referring to  FIG. 14 , an example of the Measured Pout, ICC, and Gain versus input power Pin, @2 Ghz and T=25 C is shown.  FIG. 14  illustrates that good output power and gain compression characteristics (e.g., greater than 18 dBm) can be obtained using the new self-biased Darlington approach. Moreover, this plot illustrates that the new self-bias can allow class AB or B dynamic bias operation as evident by the increase in the amplifier bias current ICC as input power PIN is increased. This is a fundamental limitation observed in the conventional Darlington bias when using an external set resistor which tends reduce DC output voltage headroom as input power, PIN (and ICC) is increased.  
         [0047]     The transistors described herein may be implemented as bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), double heterojunction bipolar transistors (DHBT) or pseudomorphic high electron mobility transistors (PHEMT). However, other transistors with similar characteristics may be implemented to meet the design criteria of a particular implementation. In particular, the various, transistors of the present invention may be implemented using a variety of process technologies. For example, any or all semiconductors, including compound semiconductors, III-V semiconductors, Silicon Germanium (SiGe), Indium Gallium Phosphorous (InGaP), Indium Phosphide (InP), or Gallium Arsenide (GaAs) may be used. However, other process technologies may be implemented to meet the design criteria of a particular implementation.  
         [0048]     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.