Abstract:
A bus driver circuit (FIG.  2 ) is disclosed. The circuit includes a signal lead of a bus ( 200 ) and a reference terminal (Vss). A first transistor (MN 0 ) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN 1 ) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP 0 ) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP 1 ) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).

Description:
BACKGROUND OF THE INVENTION 
     Embodiments of the present invention relate to a transition rate controlled bus driver circuit having reduced load capacitance sensitivity. 
     In wired digital communication systems with variable connection lengths and bus termination impedances there are challenging design limitations related to rise and fall time, power dissipation, and low and high output voltage levels. These limitations are further complicated by signal overshoot and inductive ringing which can cause interference between adjacent bus leads and communication errors. Frequently there must be a balance between bus circuit drive strength to control signal rise and fall times as well as to establish reliable logic levels after signal transitions. Some implementations may simply employ large n-channel and p-channel drive transistors with passive filter circuits, but these implementations are only effective for a limited range of bus loading. Other implementations may employ active current sources to achieve a controlled transition rate of a bus signal. However, these may be limited by power constraints. 
     Referring to  FIG. 1 , there is a simplified circuit diagram of a bus pull down circuit of the prior art. The circuit includes bus  100  and n-channel pull down transistor M PD    104 . Feedback capacitor C PD    102  is coupled between the gate and drain of transistor M PD . In operation, the gate of M PD  is driven high by current source  106  to pull bus lead  100  low while current source  108  is off. Alternatively, the gate of M PD  is driven low by current source  108  when bus lead  100  is to remain high while current source  106  is off. Although this circuit provides a controlled pull down rate of bus lead  100 , switching time is limited by current source  106  and threshold voltage and process variation of transistor M PD    104 . 
     While preceding approaches have provided improvements in bus switching and power consumption, the present inventors recognize that still further improvements are possible. Accordingly, the preferred embodiments described below are directed toward improving upon the prior art. 
     BRIEF SUMMARY OF THE INVENTION 
     In a preferred embodiment of the present invention, a bus drive circuit is disclosed. The circuit includes a signal lead of a bus and a reference terminal. A first transistor has a first control terminal and has a first current path coupled to the reference terminal. A second transistor has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor is arranged to provide a first current through the first current path when the signal lead is in a first logic state. A fourth transistor is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         FIG. 1  is a circuit diagram of a bus pull down circuit of the prior art; 
         FIG. 2  is a circuit diagram of bus driver circuit of the present invention; 
         FIG. 3A  is a circuit diagram showing operation of the present invention when a bus lead is driven to a high logic level; 
         FIG. 3B  is a circuit diagram showing operation of the present invention when the bus lead is driven to a low logic level; 
         FIG. 4  is a timing diagram showing operation of the bus driver circuit of the present invention; 
         FIG. 5A  is a circuit diagram showing operation of an alternative embodiment of the present invention when the bus lead is driven to a high logic level; and 
         FIG. 5B  is a circuit diagram showing operation of the alternative embodiment of the present invention when the bus lead is driven to a low logic level. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The preferred embodiments of the present invention provide significant advantages over bus driver circuits of the prior art as will become evident from the following detailed description. 
     Referring to  FIG. 2 , there is a bus driver circuit of the present invention which may be used for driving bus leads or other loads having a wide range of capacitance and inductance. Here and in the following discussion bus  200  is shown as a single signal lead for the purpose of explanation. However, one of ordinary skill in the art will understand that many bus drive circuits and signal leads may be required on an integrated circuit to drive internal or external address, data, and control bus signals. The bus driver circuit of  FIG. 2  is preferably operated by a processor  210  which produces control, address, and data signals. Control signals from processor  210  determine whether the bus driver circuit is to drive signals on bus  200  or whether another device may have control of the bus. Address and data signals determine the logic state of individual bus leads. Address and data signals transmitted on the bus driver circuit are received by remote bus receiver circuit  206 , which may be a Schmidt trigger or buffer circuit enabled by receive signal RXE_H or other suitable receive circuit. 
     Transistor sizes of  FIG. 2  are shown by way of example in the format X(W/L), where W is the width of a single transistor, L is the length of the transistor, and X is the number of parallel repetitions of the single transistor. Here and in the following discussion, the same reference names and numerals are used to indicate substantially the same circuit elements in the various drawing figures. In the example of  FIG. 2 , transistor names beginning with MP are p-channel metal oxide semiconductor (MOS) transistors. Transistors beginning with MN are n-channel MOS transistors. However, one of ordinary skill in the art having access to the instant specification will understand that bipolar transistors may be used rather than MOS transistors. Finally, short horizontal lines at the source of p-channel transistors represent a positive supply voltage terminal (Vdd). Correspondingly, triangles at the source of n-channel transistors represent a reference voltage such as Vss or ground. 
     The bus driver circuit of  FIG. 2  includes a p-channel current mirror circuit formed by transistors MP 0 , MP 1 , MP 3 , and MP 4 . These transistors are typically operated in saturation with a same gate to source voltage so that their drain currents are relatively constant and proportional to their respective widths. The common gate of the p-channel current mirror circuit is connected to the common drain terminal of transistors MP 7  and MN 8 . Transistors MP 7  and MN 8  have a common gate terminal that is coupled to receive enable signal TXE_H. When enable signal TXE_H is low, MP 7  is on and MN 8  is off. In this state, the common gate terminal of the p-channel current mirror circuit is coupled to Vdd, and the p-channel transistors of the current mirror circuit are off. Alternatively, when enable signal TXE_H is high, MP 7  is off and MN 8  is on. In this state, the common gate terminal of the p-channel current mirror circuit is coupled to Vss through current source  204 . Current source  204  provides a small current of approximately 32 μA to achieve a bias voltage of the common gate terminal so that the p-channel transistors of the current mirror circuit operate in saturation. 
     The bus driver circuit of  FIG. 2  also includes an n-channel current mirror circuit formed by transistors MN 0  and MN 1 . These transistors are also operated in saturation with a same gate to source voltage so that their drain currents are relatively constant and proportional to their respective widths. The common gate of the n-channel current mirror circuit is connected to the drain terminal of transistor MN 6 . Transistor MN 6  is coupled to receive enable signal TXE_L. When enable signal TXE_L is high and MN 1  is on. In this state, the common gate terminal of the n-channel current mirror circuit is coupled to Vss, and the n-channel transistors of the current mirror circuit are off. Alternatively, when enable signal TXE_L is low, MN 8  is off. In this state, the common gate terminal of the n-channel current mirror circuit is coupled to the drain of MP 0 , which provides a small current to achieve a bias voltage of the common gate terminal so that the n-channel transistors of the current mirror circuit operate in saturation. 
     When the bus driver circuit is enabled, data signal TX_H is applied to the gates of MP 2  and MN 3 . When TX_H is high, MP 2  is off and MN 3  is on. In this state, the gate and drain of MN 0  are connected to the drain of MP 0  in a diode configuration. Thus, the gate on the n-channel current mirror is held at approximately an n-channel transistor threshold voltage (V TN ) above Vss. Alternatively, when TX_H goes low to pull bus lead  200  low, MP 2  is on and MN 3  is off. In this state, the gate of MN 0  is connected to the drain of MP 0  and MP 1 , and the drain of MN 0  is open. The common gate terminal of the n-channel current mirror is coupled to bus lead  200  by capacitor C PD . Data signal TX_L is also applied to the gate of MN 2 . When TX_L is low, MN 2  is off and the drain of MN 1  is open. When TX_L goes high MN 2  turns on to couple bus lead  200  to the drain of MN 1 . The series connection of MN 1  and MN 2  is designed to sink more current than MP 4  can source. Bus lead  200 , therefore, is pulled low through MN 1  and MN 2  when TX_L goes high. 
     Turning now to  FIG. 3A , operation of the bus driver circuit of  FIG. 2  will be explained when bus lead  200  is driven high to a first logic state. The same reference names and numerals are used in  FIG. 3A  for the same circuit elements of  FIG. 2  as previously discussed. Data signals TX_H and TX_L are high and low, respectively, when bus lead  200  is driven high. In this state, MP 2  is off and MN 3  is on. MN 0  is configured as an MOS diode with gate and drain connected to lead  202 . MP 0  provides a small current of approximately 2 μA to keep the common gate of MN 0  and MN 1  at approximately an n-channel threshold voltage V TN  above Vss. MN 2  is off so no current flows through MN 1 . MP 4  is on and holds bus lead  200  at Vdd. This configuration is highly advantageous for several reasons. First, the circuit conducts only 2 μA through MP 0  in steady state operation when bus lead  200  remains high. Second, MP 4  holds bus lead  200  high without any steady state power dissipation. Third, the gate of MN 1  is held at approximately V TN , so any increase in gate voltage immediately begins a high to low transition of bus lead  200  without the time required for the control gate to reach V TN . 
     Referring next to  FIG. 3B , operation of the bus driver circuit of  FIG. 2  will be explained with reference to the timing diagram of  FIG. 4  when bus lead  200  is driven low to a second logic state. At time t 1 , data signals TX_L and TX_H go high and low, respectively. The high level of TX_L turns on MN 2 , thereby connecting pull down transistor MN 1  to bus lead  200 . The low level of TX_H turns off MN 3  and turns on MP 2 . In this state, the drain of MN 0  is open and MN 0 , therefore, conducts no current. MP 2  is on and the sum of current through MP 0  (2 μA) and MP 1  (28 μA) or I PD  (30 μA) is applied to lead  202 . This produces a slight increase in MN 1  gate voltage to an equilibrium value. MN 1  immediately begins to conduct current from MP 4  and discharge bus lead  200 . From time t 1  to time t 2  bus lead  200  discharges at a rate of −I PD /C PD . The transition rate of bus lead  200 , therefore, is controlled by I PD  and C PD  and is substantially linear. This is because MN 1  operates in saturation and the gate of MN 1  remains at an equilibrium voltage, so the current I PD  through C PD  is equal to C PD ·dV200/(t 2 −t 1 ). Thus, −I PD /C PD  is equal to dV200/(t 2 −t 1 ). At time t 2 , bus lead  200  achieves an output low value and is received by bus receiver  206 . Subsequently, V 202  increases linearly from time t 2  to time t 3  as current I PD  charges C PD . As the gate voltage of MN 1  reaches Vdd, bus lead  200  reaches a minimum output low value (V OL ). From time t 3  to time t 4  MN 1  operates in the linear region to hold bus lead  200  at V OL . At time t 4 , data signals TX_L and TX_H go low and high, respectively. The low level of TX_L turns off MN 2  and current through MP 4  charges bus lead  200  linearly to Vdd at time t 5 . The high level of TX_H turns MN 3  on and MP 2  off. MN 0  is once again configured as an MOS diode and operates in saturation to discharge lead  202  linearly to V TN  at time t 5 . 
     Several advantages of the present invention are apparent from the foregoing discussion. First, the control gate of pull down transistor MN 1  begins at V TN . Thus, the high to low transition of bus lead  200  begins immediately with the transition of data signals TX_L and TX_H. Second, all transitions of bus lead  200  are linear and are driven by a relatively constant current from either the p-channel current mirror (MP 4 ) or the n-channel current mirror (MN 1 ). This greatly reduces inductive ringing and overshoot during bus transitions, because the ringing is equal to a product of bus inductance and a rate of change of current with time (L BUS ·di/dt). Since transition current is approximately constant, ringing and overshoot are small. Third, the transition rate of bus lead  200  is controlled by the selection of MP 0  and MP 1  (I PD ) and C PD  and is, therefore, substantially independent of load capacitance for a wide range of values. Finally, the bus drive circuit dissipates virtually no steady state power. Moreover, power dissipation during signal transitions only occurs for a brief time until remote bus receiver  206  receives the data on bus lead  200 . 
     Referring next to  FIGS. 5A and 5B , there is an alternative embodiment of the present invention, wherein p-channel transistor MP 4  is divided into two p-channel transistors or current sources  500  and  502 . P-channel transistor  504  is added in series with transistor  500  and controlled by data signal TX_L. As previously described, when bus lead  200  remains high data signal TX_L remains low. The low level of TX_L turns off MN 2  and turns on p-channel transistor  504 . Thus, p-channel transistors  500  and  502  provide current to drive bus lead  200  from a second logic state (low) to a first logic state (high). This is equivalent to the previously described embodiment of  FIG. 3A . A low to high transition of data signal TX_L ( FIG. 5B ) subsequently turns on MN 2  and turns off p-channel transistor  504 . In this state, pull down transistor MN 1  must only sink current from p-channel transistor  502  and discharge bus lead  200 . Thus, power dissipation is further reduced during high to low signal transitions of bus lead  200 . 
     Still further, while numerous examples have thus been provided, one skilled in the art should recognize that various modifications, substitutions, or alterations may be made to the described embodiments while still falling within the inventive scope as defined by the following claims. For example, in the circuit of  FIG. 3A  the control gate of n-channel transistor MN 1  is biased at approximately a threshold voltage V TN  above Vss. In an alternative embodiment of the present invention, the control gate of n-channel transistor MN 1  may be biased slightly below the threshold voltage V TN  by making the channel length of n-channel transistor MN 0  less than the channel length of MN 1 . The short channel effect of MN 0  provides a bias voltage slightly less than V TN  so that n-channel transistor MN 1  remains off while control signal TX_H is high. In this embodiment, n-channel transistor MN 2  and control signal TX_L may be eliminated, and the drain of n-channel transistor MN 1  may be directly connected to the drain of p-channel transistor MP 4 . Moreover, although individual transistors are used as switching devices, one of ordinary skill in the art will understand that transmission gates or other suitable switching devices may also be used. Other combinations will be readily apparent to one of ordinary skill in the art having access to the instant specification.