Abstract:
A frequency multiplier including some embodiments, the frequency multiplier includes: a first transistor and a second transistor, wherein a first terminal of the first transistor is connected to a third terminal of the second transistor through a first capacitor, and a first terminal of the second transistor is connected to a third terminal of the first transistor through a second capacitor. The frequency multiplier also includes a balun, wherein the third terminal of the first transistor is connected to a terminal of the balun, and the third terminal of the second transistor is connected to a different terminal of the balun.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates generally to frequency multipliers. 
       BACKGROUND 
       [0002]    Frequency multipliers are often used in microwave/millimeter-wave signal sources. A frequency multiplier can up-convert a relatively low frequency signal into a high frequency signal. Drawbacks exist with conventional frequency multipliers. For example, some conventional frequency multipliers have a low conversion gain and a limited operating frequency, while others consume large amounts of power and require a relatively high supply voltage. What is desired is a frequency multiplier that overcomes at least some of these disadvantages. 
       SUMMARY 
       [0003]    In one aspect, the present invention provides a frequency multiplier that overcomes at least some of the above mentioned disadvantages. In some embodiments, the frequency multiplier includes: a first transistor having a first terminal, a second terminal and a third terminal; and a second transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the first transistor is connected to the third terminal of the second transistor through one or more circuit elements, said one or more circuit elements including a first capacitor, and the first terminal of the second transistor is connected to the third terminal of the first transistor through one or more circuit elements, said one or more circuit elements including a second capacitor. 
         [0004]    In some embodiments, the frequency multiplier also includes a balun, wherein the third terminal of the first transistor is connected to a first terminal of the balun, and the third terminal of the second transistor is connected to a second terminal of the balun. 
         [0005]    The second terminal of the first transistor may be connected to an output node and the second terminal of the second transistor may also be connected to the output node. The transistor may be implemented using bipolar junction transistors or other transistors. 
         [0006]    Accordingly, in some embodiments, the first terminal of the first transistor is the base of the first transistor, the first terminal of the second transistor is the base of the second transistor, the second terminal of the first transistor is the collector of the first transistor, the second terminal of the second transistor is the collector of the second transistor, the third terminal of the first transistor is the emitter of the first transistor, and the third terminal of the second transistor is the emitter of the second transistor. 
         [0007]    In some embodiments, the frequency multiplier also includes a third capacitor, wherein the third terminal of the first transistor is connected to the third terminal of the second transistor through the third capacitor. In some embodiments, the first terminal of the first transistor and the first terminal of the second transistor are biased at a turn-on voltage. 
         [0008]    In another aspect, the present invention provides a frequency multiplier method for use in a frequency multiplier circuit comprising a first transistor having a first terminal, a second terminal and a third terminal and a second transistor having a first terminal, a second terminal and a third terminal. In some embodiments, the method includes: merging the frequency multiplier circuit with a balun; and simultaneously applying at each transistors&#39; first and third terminals anti-phase RF signals. 
         [0009]    In some embodiments, each transistor is a bipolar junction transistor (BJT), and the first terminal of the first transistor is the base of the first transistor, the first terminal of the second transistor is the base of the second transistor, the second terminal of the first transistor is the collector of the first transistor, the second terminal of the second transistor is the collector of the second transistor, the third terminal of the first transistor is the emitter of the first transistor, and the third terminal of the second transistor is the emitter of the second transistor. In some embodiments, the first terminal of the first transistor and the first terminal of the second transistor are biased at a turn-on voltage. 
         [0010]    In some embodiments, the method also includes capacitively coupling the first transistor with the second transistor to form a capacitive coupled transistor pair. In some embodiments, the step of capacitively coupling the first transistor with the second transistor comprises: connecting the first terminal of the first transistor to the third terminal of the second transistor through one or more circuit elements, said one or more circuit elements including a first capacitor; and connecting the first terminal of the second transistor to the third terminal of the first transistor through one or more circuit elements, said one or more circuit elements including a second capacitor. 
         [0011]    In some embodiments, the method includes: capacitively coupling the first transistor with the second transistor to form a capacitive coupled transistor pair; and simultaneously applying at each said transistors first and third terminals anti-phase RF signals. 
         [0012]    The above and other aspects and embodiments of the present invention are described below with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various embodiments of the present invention. In the drawings, like reference numbers indicate identical or functionally similar elements. 
           [0014]      FIG. 1  is circuit diagram illustrating a frequency multiplier according to some embodiments of the invention. 
           [0015]      FIG. 2  is circuit diagram illustrating a frequency multiplier according to other embodiments of the invention. 
           [0016]      FIG. 3  is circuit diagram illustrating a frequency multiplier according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    In a frequency multiplier according to some embodiments of the invention, the frequency multiplier includes two bipolar junction transistors and anti-phase RF signals are applied simultaneously at each transistor&#39;s base and emitter. Thus, the RF signal swing across the transistors&#39; base-emitter is larger than that in the conventional frequency multipliers. Consequently, a high conversion gain is possible. Furthermore, in some embodiments, the frequency multiplier is merged with a passive balun. Thus, the whole circuit can be compact. 
         [0018]    Referring now to  FIG. 1 ,  FIG. 1  is circuit diagram illustrating a frequency multiplier  100  according to some embodiments of the invention. As illustrated in  FIG. 1 , frequency multiplier  100  may be used to multiply the frequency of a signal produced by a signal generator  110  (e.g., a voltage controlled oscillator (VCO)) or other signal generator). 
         [0019]    As shown in  FIG. 1 , frequency multiplier  100  includes a capacitive cross-coupled transistor pair (Q 1  and Q 2 ) and a passive balun  106  for providing differential signals for the transistor pair. For example, the base of transistor Q 1  is connected to the emitter of transistor Q 2  via capacitor  104 , and, likewise, the base of transistor Q 2  is connected to the emitter of transistor Q 1  via capacitor  102 . While transistor Q 1  and Q 2  are illustrated as being biplor junction transistors, this was done solely for the sake of illustration. Thus, the invention is not limited to any particular type of transistor. 
         [0020]    As further illustrated in  FIG. 1 , the collectors of Q 1  and Q 2  are connected to an output node  108  where a high frequency RF signal is taken out, and Q 1 &#39;s emitter and Q 2 &#39;s base are connected with the balun&#39;s balanced output. Therefore, the anti-phase RF signal via the balun is added at both base and emitter of each transistor Q 1  and Q 2 . 
         [0021]    In contrast, in conventional frequency multipliers, the differential RF signal is added at the base of two transistors, but their emitters are connected to an ac virtual ground. Therefore, its RF signal&#39;s swing across base and emitter is less that of frequency multiplier  100 . Thus, frequency multiplier  100  is superior to the prior multipliers in terms of conversion gain. 
         [0022]    In addition, the impedance of the second coil of balun  106  acts as emitter degeneration, which provides a negative feedback for the transistors. It enables the conversion gain to be insensitive to the input RF power. In other words, the conversion gain can be kept constant within a certain range of RF input power. 
         [0023]    To improve conversion gain, the base of each transistor is biased at turn-on voltage. For example, as shown in  FIG. 1 , the base of Q 1  is connected to voltage source Vb through a resistor and the base of Q 2  is also connected to voltage source Vb through a resistor. Accordingly, transistor Q 1  and Q 2  are turned-on only within half-period alternatively. This results in a high efficiency which is defined as the ratio of output RF power to dc power consumption. 
         [0024]    Passive balun  106  provides differential RF signals for the capacitive coupled transistor pair. At the output point, the odd-order harmonics are added in anti-phase, while, the even-order harmonics are in-phase. Thus, the even harmonics, especially the second harmonic, are dominated, and the odd harmonics are suppressed. The suppression of the odd harmonics, especially the fundamental component, is determined by the performance of the balun, symmetry of layout, etc. However, the cross-coupled transistor pair has a function of actively compensating for certain unbalance existing at the output of the passive balun, i.e., improves the fundamental signal&#39;s balance at two transistor&#39;s collectors, therefore, it helps to achieve better fundamental suppression. 
         [0025]    Frequency multiplier  100  has a wide frequency bandwidth which is determined by the passive balun and the capacitors  102  and  104 , the capacitance of which may be equal. 
         [0026]    Referring now to  FIG. 2 ,  FIG. 2  illustrates a frequency multiplier  200  according to some embodiments of the invention. Multiplier  200  is identical to multiplier  100 , with the exception that a capacitor Cp has been added. By adding a parallel capacitor Cp across the passive balun, as shown in  FIG. 2 , the gain of multiplier becomes very flat. 
         [0027]    In summary, advantages that may be realized by utilizing the multipliers described herein are: (1) a high conversion gain; (2) constant gain within certain range of RF input power; (3) broad RF bandwidth; (4) high frequency purity; (5) compact circuit; (6) low dc power consumptions, and (7) low dc supply voltage. 
         [0028]    While the figures illustrate the use of BJTs for the transistors, multipliers  100  and  200  can be implemented in any semiconductor technology (e.g., CMOS, bipolar, Silicon, GaAs, etc). Multipliers  100  and  200  can be also implemented in discrete circuits. 
         [0029]    For example, referring to  FIG. 3 ,  FIG. 3  illustrates a multiplier  300 . Multiplier  300  is identical to multiplier  200  with the exception that the BJTs are replaced with MOSFETS. As shown in  FIG. 3 , frequency multiplier  300  includes passive balun  106  and a capacitive cross-coupled transistor pair (Q 1  and Q 2 ). For example, the gate of transistor Q 1  is connected to the source of transistor Q 2  via capacitor  104 , and, likewise, the gate of transistor Q 2  is connected to the source of transistor Q 1  via capacitor  102 . As further illustrated in  FIG. 1 , the drains of Q 1  and Q 2  are connected to output node  108  where a high frequency RF signal is taken out, and Q 1 &#39;s source and Q 2 &#39;s gate are connected with the balun&#39;s balanced output. 
         [0030]    The multipliers described above can be used in any system requiring a relatively high frequency signal. For example, the multipliers can be used in high frequency radar system, high frequency transceivers, etc. 
         [0031]    While various embodiments/variations of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments. Further, unless stated, none of the above embodiments are mutually exclusive. Thus, the present invention may include any combinations and/or integrations of the features of the various embodiments.