Abstract:
An organic light emitting display, suitable for a high quality and high resolution display device, rapidly charges a data voltage using a voltage programming technique, after compensating for a deviations in the threshold voltage and mobility of a driving transistor using a current programming technique. The organic light emitting display includes: a data line supplying a data signal; a scan line supplying a scan signal; a first switching element, electrically coupling its control electrode to the scan line, transferring the data signal supplied from the data line; a driving transistor, electrically coupling its control electrode to the first switching element, controlling a driving current of a first voltage line; a first capacitive element electrically coupled between the first switching element and the control electrode of the driving transistor; an Organic Light Emitting Diode (OLED), electrically coupled between the driving transistor and a second power voltage line, displaying an image by a current supplied from the driving transistor; and a fourth switching element compensating for deviations of characteristics of the driving transistor by supplying a current of the first current line to the driving transistor.

Description:
CLAIM FOR PRIORITY 
     This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C.§119 from an application for ORGANIC LIGHT EMITTING DISPLAY earlier filed in the Korean Intellectual Property Office on 21 Dec. 2006 and there duly assigned Serial No. 10-2006-0131961. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an organic light emitting display, and more particularly, the present invention relates to an organic light emitting display suitable for a high quality and high resolution display device, by rapidly charging a data voltage using a voltage programming technique, after compensating for deviations, such as a threshold voltage and a mobility of a driving transistor, using a current programming technique. 
     2. Description of the Related Art 
     Generally, a conventional organic light emitting display electrically excites a phosphor or a phosphorescent organic compound and emits light, which displays an image by driving N×M organic emitting cells. The organic light emitting cell of  FIG. 1  includes an anode of Indium Tin Oxide (ITO), an organic thin film and a cathode (metal). The organic thin film is a multilayer structure including an EMitting Layer (EML), an Electron Transport Layer (ETL) and a Hole Transport Layer (HTL), and may further include an extra Electron Injection Layer (EIL) and Hole Injection Layer (HIL). 
     Techniques for driving the organic light emitting cell include a simple matrix technique and an active matrix technique using a Thin Film Transistor (TFT) or a MOSFET. The simple matrix technique drives a light emitting cell by forming an anode to intersect with a cathode and selecting a line. The active matrix technique connects the TFT and a capacitor to respective Indium Tin Oxide (ITO) pixel electrodes to maintain a voltage by the capacity of a capacitor. The active matrix technique is divided into a voltage programming technique and a current programming technique according to the form of a signal supplied to the capacitor for maintaining the voltage. 
     Organic light emitting displays using voltage and current programming techniques are respectively explained below with reference to  FIGS. 2 and 3 . 
       FIG. 2  is a pixel circuit of a voltage programming technique for driving an Organic Light Emitting Diode (OLED) and representatively illustrates one of N×M pixel circuits. 
     Referring to  FIG. 2 , a driving transistor (M 1 ) is coupled to the OLED so as to supply a light-emitting current. The amount of current of the driving transistor (M 1 ) is controlled by a data voltage supplied through a first switching element (S 1 ). A first capacitive element (C 1 ) for maintaining the supplied voltage for a fixed period of time is coupled between a gate and a source of the driving transistor (M 1 ). A first electrode of the first switching element (S 1 ) is coupled to a data line (Data[m]), and a control electrode thereof is coupled to a scan line (Scan [n]). 
     When the first switching element (S 1 ) is turned on by a scan signal supplied to the control electrode of the first switching element (S 1 ), a data voltage is supplied from the data line (Data[m]) to the control electrode of the driving transistor (M 1 ). As a result thereof, a current (I OLED ) corresponding to a voltage (V GS ) charged between the gate and the source of the driving transistor (M 1 ) by the first capacitive element (C 1 ) flows to the drain of the driving transistor (M 1 ) and the OLED emits light according to the current (I OLED ). 
     The current flowing to the OLED is obtained by Equation 1. 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           I 
                           OLED 
                         
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   V 
                                   GS 
                                 
                                 - 
                                 
                                   V 
                                   TH 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   V 
                                   SG 
                                 
                                 - 
                                 
                                    
                                   
                                     V 
                                     TH 
                                   
                                    
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   V 
                                   DD 
                                 
                                 - 
                                 
                                   V 
                                   DATA 
                                 
                                 - 
                                 
                                    
                                   
                                     V 
                                     TH 
                                   
                                    
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
             
           
         
       
     
     In Equation I, I OLED  is a current flowing to the OLED, V GS  is a voltage between the gate and the source of the driving transistor (M 1 ), and a V TH  is a threshold voltage of the driving transistor (M 1 ), a V DATA  is a data voltage, and β is a constant. 
     As shown in Equation 1, according to the pixel circuit shown in  FIG. 2 , the current corresponding to the supplied data voltage is supplied to the OLED, and the OLED emits light corresponding to the supplied current. 
     In the pixel circuit of the voltage programming technique discussed above, the luminance is non-uniform due to deviations in mobility and threshold voltage of a TFT caused by non-uniformities in the manufacturing process. 
     On the contrary, the pixel circuit of the current programming technique may obtain a uniform display characteristic, even though the driving transistor in the respective pixels has a non-uniform voltage-current characteristic, if a current source supplying a current to the pixel circuit is uniform on all of the data lines. 
       FIG. 3  is a pixel circuit of a current programming technique for driving the OLED, and representatively illustrates one of N×M pixel circuits. 
     Referring to  FIG. 3 , the driving transistor (M 1 ) is coupled to the OLED so as to supply a light-emitting current, and the amount of current of the driving transistor (M 1 ) is controlled by a data current supplied through the first switching element (S 1 ). 
     When the first and second switching elements (S 1  and S 2 ) are turned on due to a selection signal outputted from the scan line (Scan [n]), the driving transistor (M 1 ) is connected in a diode configuration, a voltage corresponding to a data current (I DATA ) from the data line (Data [m]) is stored in the first capacitive element (C 1 ), the current (I OLED ) corresponding to the voltage stored in the first capacitive element (C 1 ) flows to the drain of the driving transistor (M 1 ), and the OLED emits light corresponding to the current (I OLED ). The current flowing to the OLED is obtained by Equation 2. 
     
       
         
           
             
               
                 
                   
                     I 
                     OLED 
                   
                   = 
                   
                     
                       
                         β 
                         2 
                       
                       ⁢ 
                       
                         
                           ( 
                           
                             
                               V 
                               GS 
                             
                             - 
                             
                               V 
                               TH 
                             
                           
                           ) 
                         
                         2 
                       
                     
                     = 
                     
                       I 
                       DATA 
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
             
           
         
       
     
     In Equation 2, I OLED  is a current flowing to the OLED, V GS  is a voltage between the gate and the source of the driving transistor (M 1 ), V TH  is a threshold voltage of the driving transistor (M 1 ), I DATA  is a data current, and β is a constant. 
     As shown in Equation 2, in accordance with the current programming pixel circuit discussed above, the current (I OLED ) flowing to the OLED is the same as the data current (I DATA ), so that a programming current source may obtain a uniform characteristic on all of the panels. However, the current (I OLED ) flowing to the OLED is a minute current, and the pixel circuit is controlled by the minute current (I DATA ), so that it has a problem in that it takes a considerable amount of time to charge the data line. For example, if a load capacitance of the data line is 30 pF, several milliseconds are needed to charge a load of the data line with a data current of several tens to several hundreds of nA. Therefore, there is a problem in that there is not sufficient time to charge the load of the data line, considering a line time of several tens of μs. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide an organic light emitting display that can be suitable for a high quality and high resolution display by rapidly charging a data voltage using a voltage programming technique, after compensating for deviations, such as the threshold and mobility of the driving transistors, using a current programming technique. 
     According to an aspect of the present invention, an organic light emitting display is provided including: a data line supplying a data signal; a scan line supplying a scan signal; a first switching element, electrically coupling its control electrode to the scan line, transmitting a data signal supplied from the data line; a driving transistor, electrically coupling its control electrode to the first switching element, controlling a driving current of a first power voltage line; a first capacitive element electrically coupled between the first switching element and the control electrode of the driving transistor; an Organic Light Emitting Diode (OLED), electrically coupled between the driving transistor and a second power voltage line, displaying an image by a current supplied from the driving transistor; and a fourth switching element supplying a current of a first current line to the driving transistor and compensating for deviations in characteristics of the driving transistor. 
     A first electrode of the fourth switching element may be electrically coupled to the first current line, and a second electrode thereof may be electrically coupled between the driving transistor and the OLED. 
     The organic light emitting display may be operated by supplying a current from a first current source by turning on the fourth switching element and compensating for the deviations in characteristics of the driving transistor, and then programming a data voltage to the first capacitive element by turning the first switching element. 
     The organic light emitting display may further include a third switching element supplying a voltage of the first power voltage line to the first capacitive element, a second switching element coupled to the driving transistor connected in a diode configuration, and a fifth switching element transmitting the current supplied from the driving transistor to the OLED. 
     A first electrode of the third switching element may be electrically coupled to the first power voltage line, and a second electrode thereof may be electrically coupled between the first switching element and the first capacitive element. A first electrode of the second switching element may electrically coupled between the control electrode of the driving transistor and the first capacitive element, and a second electrode thereof may be electrically coupled between the driving transistor and the fourth switching element. A first electrode of the fifth switching element may be electrically coupled between the driving transistor and the fourth switching element, and a second electrode may be electrically coupled to the OLED. 
     Control electrodes of the second to the fourth switching elements may be coupled to a direct scan line, and a control electrode of the fifth switching element may be coupled to a light emitting control line. 
     The first to the fifth switching elements and the driving transistor may each be P-channel transistors. 
     For a compensation period in an image display period of one frame, if the second to the fourth switching elements are turned on, and the first and fifth switching elements are turned off, the current from the first current line is supplied to the driving transistor, so that deviations in characteristics of the driving transistor may be compensated for. 
     For a programming period in the image display period of one frame, if the first switching element is turned on, the second to the fifth switching elements are turned off, a data voltage from the data line may be supplied to a first electrode of the first capacitive element. 
     For a light emitting period in the image display period of one frame, if the fifth switching element is turned on, and the first to the fourth switching elements are turned off, the voltage stored in the first capacitive element is supplied to the organic light emitting diode so as to emit light. 
     The organic light emitting display may further include a second capacitive element whose a first electrode is electrically coupled between the first power voltage line and the first electrode of the third switching element, and a second electrode is electrically coupled between the first capacitive element and the control electrode of the driving transistor. 
     Control electrodes of the second to the fourth switching elements are coupled to a direct scan line, and a control electrode of the fifth switching element may be coupled to a light emitting control line. 
     The organic light emitting display may further include a second capacitive element whose a first electrode is electrically coupled between the first power voltage line and the first electrode of the third switching element, and a second electrode is electrically coupled between the first capacitive element and the second electrode of the third switching element. 
     The organic light emitting display compensates for deviations in characteristics of the driving transistor by programming a data voltage and causing a fixed volume of current to flow to the driving transistor prior to driving. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the present invention and many of the attendant advantages thereof, will be readily apparent as the present invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein: 
         FIG. 1  is a conceptual diagram of an organic light emitting diode; 
         FIG. 2  is a pixel circuit diagram of a voltage programming technique; 
         FIG. 3  is a pixel circuit diagram of a current programming technique; 
         FIG. 4  is a schematic diagram of an organic light emitting display according to an embodiment of the present invention; 
         FIG. 5  is a circuit diagram of a pixel circuit of an organic light emitting display according to one exemplary embodiment of the present invention; 
         FIG. 6  is a timing diagram of the pixel circuit of  FIG. 5 ; 
         FIG. 7  is a circuit diagram of a pixel circuit of an organic light emitting display according to another exemplary embodiment of the present invention; 
         FIG. 8  is a timing diagram of the pixel circuit of  FIG. 7 ; 
         FIG. 9  is a circuit diagram of a pixel circuit of an organic light emitting display according to still another exemplary embodiment of the present invention; and 
         FIG. 10  is a timing diagram of the pixel circuit of  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, exemplary embodiments of the present invention are described in detail with reference to the accompanying drawing. The aspects and features of the present invention and methods for achieving the aspects and features will be apparent by referring to the embodiments to be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed hereinafter, but can be implemented in diverse forms. The matters defined in the description, such as the detailed construction and elements, are merely specific details provided to assist those of ordinary skill in the art in a comprehensive understanding of the present invention, and the present invention is only defined within the scope of the appended claims. In the entire description of the present invention, the same drawing reference numerals are used for the same elements across various figures. 
       FIG. 4  is a block diagram of an organic light emitting display according to an embodiment of the present invention. 
     Referring to  FIG. 4 , a flat panel display  100  includes a scan driver  110 , a data driver  120 , a light emitting control driver  130 , an organic light emitting display panel (hereinafter, referred to as the “panel”)  140 , a first voltage power supply  150 , a second voltage power supply  160  and a first current supply  170 . 
     The scan driver  110  sequentially supplies a scan signal to the panel  140  through a plurality of scan lines (Scan[ 1 ], Scan[ 2 ], . . . , and Scan[n]). 
     The data driver  120  supplies a data signal to the panel  140  through a plurality of data lines (Data[ 1 ], Data[ 2 ], . . . , and Data[m]). 
     The light emitting control driver  130  sequentially supplies a light emitting control signal to the panel  140  through a plurality of light emitting control lines (Em[ 1 ], Em[ 2 ], . . . , and Em[n]). 
     The panel  140  includes the plurality of scan lines (Scan[ 1 ], Scan[ 2 ], . . . , and Scan[n]) and the plurality of light emitting control lines (Em[ 1 ], Em[ 2 ], . . . , and Em[n] that are arranged in a column direction, the plurality of data lines (Data[ 1 ], Data[ 2 ], . . . , and Data[m]) arranged in a row direction, and a pixel circuit  141  defined by the plurality of scan lines (Scan[ 1 ], Scan[ 2 ], . . . , and Scan[n]), the plurality of data lines (Data[ 1 ], Data[ 2 ], . . . , and Data[m]) and the plurality of light emitting control lines (Em[ 1 ], Em[ 2 ], . . . , and Em[n]). 
     The pixel circuit is formed in a pixel region defined by two adjacent scan lines (or light emitting control lines) and two adjacent data lines. As described above, the scan signal is supplied by the scan driver  1   10  to the plurality of scan lines (Scan[  1 ], Scan[ 2 ], . . . , and Scan[n]), a data signal is supplied by the data driver  120  to the plurality of data lines (Data[ 1 ], Data[ 2 ], . . . , and Data[m]), and the light emitting control signal is supplied by the light emitting control driver  130  to the plurality of light emitting control lines (Em[ 1 ], Em[ 2 ], . . . , and Em[n]). 
     The first and second voltage power supplies  150  and  160  supply first and second power supply voltages to respective pixel circuits  141  on the panel  140 , and the first current supplier  170  supplies a first current to respective pixel circuits  141  on the panel  140 . 
       FIG. 5  is a circuit diagram of a pixel circuit of an organic light emitting display according to one exemplary embodiment of the present invention. The following pixel circuits denote one pixel circuit of the flat panel display  100  of  FIG. 4 . 
     Referring to  FIG. 5 , the pixel circuit of the organic light emitting display includes a scan line (Scan[n]), a direct scan line (Scan[n- 1 ]), a data line (Data[m]), a light emitting control line (Em[n]), a first power supply voltage line (V DD ), a second power supply voltage line (VSS), a first current line (I sink ), a driving transistor (M 1 ), a first switching element (S 1 ), a second switching element (S 2 ), a third switching element (S 3 ), a fourth switching element (S 4 ), a fifth switching element (S 5 ), a first capacitive element (C 1 ) and an Organic Light Emitting Diode (OLED). 
     The scan line (Scan[n]) supplies a scan signal for selecting an OLED to be driven to a control electrode of the first switching element (S 1 ). The scan line (Scan[n]) is electrically coupled to the scan driver  110  (see  FIG. 4 ) for generating a scan signal. 
     The direct scan line (Scan[n- 1 ]) is indicated as Scan[n- 1 ] since a previously selected (n- 1 )th scan line is commonly coupled and used. The direct scan line (Scan[n- 1 ]) controls the operation of the second to fourth switching elements S 2 , S 3  and S 4 . 
     The data line (Data[m]) supplies a data signal (voltage) in proportion to a light emitting luminance to a first electrode (A) of the first capacitive element (C 1 ). The data line (Data[m]) is electrically coupled to the data driver  120  (referring to  FIG. 4 ) for generating a data signal. 
     The light emitting control line (Em[n]) is electrically coupled to a control electrode of the fifth switching element (S 5 ), to control a light emitting time of the OLED. The light emitting control line (Em[n]) is electrically coupled to the light emitting control driver  130  (referring to  FIG. 4 ) for generating a light emitting control signal. 
     The first power supply voltage line (V DD ) enables the first power supply voltage to be supplied to the OLED. The first power supply voltage line (V DD ) is coupled to the first voltage power supply  150  (see  FIG. 4 ) for supplying the first power supply voltage. 
     The second power supply voltage line (VSS) enables a second power supply voltage to be supplied to the OLED. The second power supply voltage line (VSS) is coupled to the second voltage power supply  160  (see  FIG. 4 ) for supplying the second power supply voltage. The first power supply voltage may be at a higher voltage level than the second power supply voltage. 
     The first current line (I sink ) enables a first current to be supplied to the driving transistor (M 1 ). When the fourth switching element (S 4 ) is turned on, a current is supplied to the driving transistor (M 1 ), so that deviations in mobility and threshold of the driving transistors (M 1 ) of respective pixel circuits  141  (see  FIG. 4 ) are compensated for, in the same fashion as the current programming technique of  FIG. 3 . The first current line (I sink ) is coupled to the first current supply  170  (see  FIG. 4 ) for supplying a first current. 
     The driving transistor (M 1 ) includes a first electrode electrically coupled to the first power supply voltage line (V DD ), a second electrode electrically coupled to a first electrode of the fifth switching element (S 5 ) and a second electrode of the fourth switching element (S 4 ), and a control electrode electrically coupled to a second electrode of the first switching element (S 1 ). The driving transistor (M 1 ) (assumed to be a P-channel transistor) is turned on if a data signal at a low level (or a negative voltage) is supplied through the control electrode, and supplies a fixed voltage from the first power supply voltage line (V DD ) to the OLED. A first capacitive element (C 1 ) is charged by supplying a data signal of a high level (or a positive voltage) to a first electrode (A) thereof. As a result thereof, even though the first switching element (S 1 ) is turned off, the data signal at a high level (or a positive voltage) is continuously supplied to the control electrode of the driving transistor (M 1 ) by the voltage charged in the first capacitive element (C 1 ) for a fixed time. 
     The driving transistor (M 1 ) may be an amorphous silicon TFT, a polysilicon TFT, an organic TFT, a nano thin film semiconductor transistor or equivalents thereof. However, the present invention is not limited thereto. 
     If the driving transistor (M 1 ) is the polysilicon TFT, it may be formed by laser crystallization, metal induced crystallization, high voltage crystallization or equivalents thereof However, the present invention is not limited thereto. 
     Laser crystallization is a method of crystallizing an amorphous silicon with an excimer laser, for example. Metal induced crystallization is a method including positioning a metal, for example, adjacent to an amorphous silicon and starting crystallization from the metal by applying a predetermined temperature. Furthermore, high voltage crystallization is a method of crystallizing amorphous silicon, for example, by applying a predetermined voltage to the amorphous silicon. 
     If the driving transistor (M 1 ) is manufactured by the metal induced crystallization, the driving transistor (M 1 ) further includes a metal selected from a group consisting of nickel (Ni), cadmium (Cd), cobalt (Co), Titanium (Ti), palladium (Pd), tungsten (W) or equivalents thereof. 
     The first switching element (S 1 ) includes a first electrode (a drain electrode or a source electrode) electrically coupled to the data line (Data[m]), a second electrode (a source electrode or a drain electrode) electrically coupled to a control electrode (a gate electrode) of the driving transistor (M 1 ), and a control electrode electrically coupled to the scan line (Scan[n]). When the first switching element (S 1 ) is turned on, a data signal is supplied to the first electrode (A) of the first capacitive element (C 1 ). 
     The second switching element (S 2 ) includes a first electrode electrically coupled to the control electrode of the driving transistor (M 1 ), and a second electrode electrically coupled between the second electrode of the driving transistor (M 1 ) and the first electrode of the fifth switching element (S 5 ). When a scan signal of a low level is supplied to the control electrode through the direct scan line (Scan[n- 1 ]), the fifth switching element (S 5 ) is turned on and is connected in a diode configuration. 
     The third switching element (S 3 ) includes a first electrode electrically coupled to the first power supply voltage line (V DD ), and a second electrode electrically coupled to the first electrode (A) of the first capacitive element (C 1 ). When a scan signal at a low level is supplied to a control electrode through the direct scan line (Scan[n- 1 ]), the third switching element (S 3 ) is turned on, thereby supplying the first power supply voltage (V DD ) to a node A of the first capacitive element (C 1 ). 
     The fourth switching element (S 4 ) includes a first electrode (a source electrode or a drain electrode) electrically coupled to the first current line (I sink ), and a second electrode (a drain electrode or a source electrode) electrically coupled between the second electrode of the driving transistor (M 1 ) and the second switching element (S 2 ). When a scan signal of a low level is supplied to the control electrode through the direct scan line (Scan [n- 1 ]), the fourth switching element (S 4 ) is turned on, thereby supplying a first current of the first current line (I sink ) to the driving transistor (M 1 ). 
     The fifth switching element (S 5 ) includes a first electrode electrically coupled to the second electrode of the driving transistor (M 1 ), and a second electrode electrically coupled to an anode of the OLED. When a scan signal at a low level is supplied to the control electrode through the light emitting control line (Em[n]), the fifth switching element (S 5 ) is turned on, thereby causing a current to flow from the driving transistor (M 1 ) to the OLED. 
     The first capacitive element (C 1 ) includes a first electrode (A) electrically coupled between the second electrode of the first switching element (S 1 ) and the third switching element (S 3 ), and a second electrode (B) electrically coupled between the control electrode of the driving transistor (M 1 ) and the first electrode of the second switching element (S 2 ). 
     The OLED includes an anode electrically coupled to the second electrode of the fifth switching element (S 5 ), and a cathode electrically coupled to a second power supply voltage line (VSS). The OLED emits light at a predetermined luminance by the current controlled through the driving transistor (M 1 ). 
     The OLED is equipped with a light emitting layer (hereinafter, referred to as “EML”, see  FIG. 1 ), and the EML is a material selected from phosphor materials, phosphorescent materials, mixtures thereof or equivalents thereof. However, the present invention is not limited thereto. 
     Furthermore, the EML may be a material selected from red light emitting materials, green light emitting materials, blue light emitting materials, mixtures thereof or equivalents thereof. However, the present invention is not limited thereto. 
       FIG. 6  is a timing diagram of the organic light emitting display of  FIG. 5 . The operation of the pixel circuit of the organic light emitting display is as follows. 
     Referring to  FIG. 6 , the timing diagram of the organic light emitting display includes a current programming period (T 1 ), a delay period  1  (T 2 ), a programming period (T 3 ), a delay period  2  (T 4 ) and a light emitting period (T 5 ). 
     For the current programming period (T 1 ), a scan signal of a low level is supplied to the direct scan line (Scan[n- 1 ]), so that the second to the fourth switching elements S 2 , S 3  and S 4  are turned on. The second switching element (S 2 ) is turned on, so as to connect the driving transistor in a diode configuration. The third switching element (S 3 ) is turned on, so as to supply a first power supply voltage of the first power supply voltage line to the A node. The fourth switching element (S 4 ) is turned on, so as to cause the first current to flow to the driving transistor (M 1 ). The first current (I sink ) is obtained by Equation 3. 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           I 
                           
                             sin 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             k 
                           
                         
                         = 
                           
                         ⁢ 
                         
                           
                             
                               β 
                               2 
                             
                             ⁢ 
                             
                               
                                 ( 
                                 
                                   
                                     V 
                                     GS 
                                   
                                   - 
                                   
                                     V 
                                     TH 
                                   
                                 
                                 ) 
                               
                               2 
                             
                           
                           = 
                           
                             I 
                             OLED 
                           
                         
                       
                     
                   
                   
                     
                       
                         
                           V 
                           GS 
                         
                         = 
                           
                         ⁢ 
                         
                           
                             
                               
                                 2 
                                 ⁢ 
                                 
                                   I 
                                   
                                     sin 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     k 
                                   
                                 
                               
                               β 
                             
                           
                           + 
                           
                             V 
                             TH 
                           
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   3 
                 
               
             
           
         
       
     
     In Equation 3, V GS  is a voltage between the gate and the source of the driving transistor, V TH  is a threshold voltage of the driving transistor and β is a constant. A voltage value (V GS ) stored between the gate and the source of the driving transistor (M 1 ), i.e., between A and B nodes, may be estimated by the first current (I sink ). Furthermore, a current flowing into the drain of the driving transistor, i.e., a current flowing into the OLED is controlled by the first current, so that a desired luminance may be obtained, regardless of deviations in the mobility and threshold of respective driving transistors. 
     For the delay period  1  (T 2 ), a scan signal of the scan line (Scan[n]) is maintained at a high level, a data voltage (V DATA ) of the data line (Data[m]) is changed into a data voltage (V DATA ) corresponding to a pixel circuit coupled to the scan line (Scan[n]). If there is no delay period  1  (T 2 ), when a scan signal of the scan line (Scan[n]) arrives at a low level prior to the supplying of a present data voltage (V DATA ), a direct data voltage supplied to the data line (Data [m]) is supplied to the driving transistor (M 1 ) through the first switching element (S 1 ). 
     For the programming period (T 3 ), a scan signal at a low level is supplied to the scan line (Scan[n]), so that the first switching element(S 1 ) is turned on, so as to supply a data signal to the A node. A voltage variation of the voltages (T 1 →T 3 ) of the A node is obtained by Equation 4.
 
Δ V   A   =V   DATA   −V   DD   Equation 4:
 
     In other words, a voltage of the A node is a difference between the voltage (V DATA ) for the programming period (T 3 ) and the voltage (V DD ) for the current programming period (T 1 ). 
     For the delay period  2  (T 4 ), a scan signal of the scan line (Scan[n]) becomes a high level for a fixed time before a light emitting control signal of the light emitting control line (Em[n]) becomes a low level. This is for preventing a delay phenomenon that may occur due to the delay of respective elements in the operation of the pixel circuit. 
     For the light emitting period (T 5 ), a scan signal at a low level is supplied to the light emitting control line (Em[n]) and then the fifth switching element (S 5 ) is turned on, so that the voltage charged in the first capacitive element, i.e., a current (I OLED ) corresponding to the gate-source voltage (V GS ) of the driving transistor (M 1 ) is supplied to the OLED so as to emit light. The current (I OLED ) is obtained by Equation 5. 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           I 
                           OLED 
                         
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   V 
                                   GS 
                                 
                                 - 
                                 
                                   Δ 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     V 
                                     A 
                                   
                                 
                                 - 
                                 
                                   V 
                                   TH 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   
                                     
                                       
                                         2 
                                         ⁢ 
                                         
                                           I 
                                           
                                             sin 
                                             ⁢ 
                                             
                                                 
                                             
                                             ⁢ 
                                             k 
                                           
                                         
                                       
                                       β 
                                     
                                   
                                   ⁢ 
                                   
                                     V 
                                     TH 
                                   
                                 
                                 - 
                                 
                                   ( 
                                   
                                     
                                       V 
                                       DATA 
                                     
                                     - 
                                     
                                       V 
                                       DD 
                                     
                                   
                                   ) 
                                 
                                 - 
                                 
                                   V 
                                   TH 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   
                                     
                                       2 
                                       ⁢ 
                                       
                                         I 
                                         
                                           sin 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           k 
                                         
                                       
                                     
                                     β 
                                   
                                 
                                 - 
                                 
                                   V 
                                   DATA 
                                 
                                 + 
                                 
                                   V 
                                   DD 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   5 
                 
               
             
           
         
       
     
     In Equation 5, V GS  is a voltage between the gate and the source of the driving transistor, ΔV A  is the variation of voltages of A node, V DATA  is a data voltage, V DD  is a first power supply voltage and V TH  is a threshold voltage of the driving transistor. Referring to Equation 5, the current (I OLED ) is controlled by the first power supply voltage (V DD ), the data voltage (V DATA ) and the first current (I sink ). 
     As described above, the driving circuit is a voltage programming technique for compensating for deviations in the mobility and threshold of the driving transistors for the current programming period (T 1 ), programming and driving a data voltage for the programming period (T 3 ). In other words, the deviations in the mobility and threshold of the transistors, i.e., a disadvantage occurring in the voltage programming technique, may be compensated for by first programming the current to the pixel circuit. Furthermore, the pixel circuit is a voltage programming technique programming the data voltage after programming the current to the pixel circuit, thereby reducing the time needed to charge the voltage in the capacitive element generated from the pixel circuit of the current programming technique. In other words, the disadvantages of the voltage programming technique and the current programming technique are obviated. 
       FIG. 7  is a circuit diagram of a pixel circuit of an organic light emitting display according to another exemplary embodiment of the present invention. The following pixel circuit corresponds to one pixel circuit of the flat panel display  100  of  FIG. 4 . 
     Referring to  FIG. 7 , the pixel circuit of the organic light emitting display has the same configuration as that of  FIG. 5 , except for the second capacitive element (C 2 ). The second capacitive element (C 2 ) includes the first electrode electrically coupled between the first power supply voltage line (V DD ) and the driving transistor (M 1 ), and the second electrode electrically coupled to the control electrode of the driving transistor (M 1 ). 
       FIG. 8  is a timing diagram of the pixel circuit of the organic light emitting display of  FIG. 7 . The timing diagram of  FIG. 8  is nearly the same as the timing diagram of  FIG. 6 . 
     Referring to  FIG. 8 , the driving timing diagram of the pixel circuit of the organic light emitting display includes a current programming period (T 1 ), a delay period  1  (T 2 ), a programming period (T 3 ), a delay period  2  (T 4 ) and a light emitting period (T 5 ). 
     For the current programming period (T 1 ), a scan signal of a low level is supplied to the direct scan line (Scan[n- 1 ]), so that the second to the fourth switching elements S 2 , S 3  and S 4  are turned on. The second switching element (S 2 ) is turned on so that the driving transistor is connected in a diode configuration. The third switching element (S 3 ) is turned on, so as to supply the first power supply voltage of the first power supply voltage line to the first electrode (A) of the first capacitive element (C 1 ) and the first electrode (A) of the second capacitive element (C 2 ). The fourth switching element (S 4 ) is turned on, so as to cause the first current to flow to the driving transistor (M 1 ). The first current (I sink ) is obtained by Equation 6. 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           
                             I 
                             
                               sin 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               k 
                             
                           
                           = 
                             
                           ⁢ 
                           
                             
                               
                                 β 
                                 2 
                               
                               ⁢ 
                               
                                 
                                   ( 
                                   
                                     
                                       V 
                                       GS 
                                     
                                     - 
                                     
                                       V 
                                       TH 
                                     
                                   
                                   ) 
                                 
                                 2 
                               
                             
                             = 
                             
                               I 
                               OLED 
                             
                           
                         
                       
                     
                     
                       
                         
                           
                             V 
                             GS 
                           
                           = 
                             
                           ⁢ 
                           
                             
                               
                                 
                                   2 
                                   ⁢ 
                                   
                                     I 
                                     
                                       sin 
                                       ⁢ 
                                       
                                           
                                       
                                       ⁢ 
                                       k 
                                     
                                   
                                 
                                 β 
                               
                             
                             + 
                             
                               V 
                               TH 
                             
                           
                         
                       
                     
                   
                   ⁢ 
                   
                       
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   6 
                 
               
             
           
         
       
     
     In Equation 6, V GS  is a voltage between the gate and the source of the driving transistor, V TH  is a threshold voltage of the driving transistor, and β is a constant. A voltage value (V GS ) stored between the gate and the source of the driving transistor (M 1 ) is defined by the first current (I sink ). Furthermore, a current flowing to the drain of the driving transistor (M 1 ), i.e., a current flowing to the organic light emitting diode is controlled by the first current, so that the desired luminance may be obtained regardless of deviations in the mobility and threshold of respective transistors. 
     For the delay period  1  (T 2 ), the scan signal of the scan line (Scan[n]) is maintained at a high level, a data voltage (V DATA ) of the data line (Data[m]) is changed into a data voltage (V DATA ) corresponding to the pixel circuit coupled to the scan line (Scan[n]). If there is no delay period  1  (T 2 ), when a scan signal of the scan line (Scan[n]) reaches a low level prior to the supplying of a present data voltage (V DATA ), a direct data voltage supplied to the data line (Data[m]) is supplied to the driving transistor (M 1 ) through the first switching element (S 1 ). 
     For the programming period (T 3 ), a scan signal of a low level of the scan line (Scan[n]) is supplied, the first switching element (S 1 ) is turned on, so that a data signal is supplied to A node. A voltage variation of the A node is obtained by Equation 7.
 
Δ V   A   =V   DATA   −V   DD   Equation 7:
 
     In other words, the voltage of the A node is a difference between the voltage (V DATA ) for the programming period (T 3 ) and the voltage (V DD ) for the current programming period (T 1 ). 
     For the delay period  2  (T 4 ), a scan signal of the scan line (Scan[n]) reaches a high level for a fixed time before a scan signal of the light emitting control line (Em[n]) reaches at a low level. This is for preventing a delay phenomenon occurring due to the delay of respective elements in the operation of the pixel circuit. 
     For the light emitting period (T 5 ), a scan signal at a low level is supplied to the light emitting control line (Em[n]) and the fifth switching element (S 5 ) is turned on, so that a voltage charged in the first capacitive element (C 1 ) and the second capacitive element (C 2 ), i.e., a current corresponding to the gate-source voltage (V GS ) of the driving transistor (M 1 ) is supplied to the OLED so as to emit light. The current (I OLED ) is obtained by Equation 8. 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           I 
                           OLED 
                         
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 VGS 
                                 - 
                                 
                                   Δ 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     V 
                                     G 
                                   
                                 
                                 - 
                                 
                                   V 
                                   TH 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   
                                     
                                       2 
                                       ⁢ 
                                       
                                         I 
                                         
                                           sin 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           k 
                                         
                                       
                                     
                                     β 
                                   
                                 
                                 + 
                                 
                                   V 
                                   TH 
                                 
                                 - 
                                 
                                   
                                     
                                       C 
                                       1 
                                     
                                     
                                       
                                         C 
                                         1 
                                       
                                       + 
                                       
                                         C 
                                         2 
                                       
                                     
                                   
                                   ⁢ 
                                   
                                     ( 
                                     
                                       
                                         V 
                                         DATA 
                                       
                                       - 
                                       
                                         V 
                                         DD 
                                       
                                     
                                     ) 
                                   
                                 
                                 - 
                                 
                                   V 
                                   TH 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   
                                     
                                       2 
                                       ⁢ 
                                       
                                         I 
                                         
                                           sin 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           k 
                                         
                                       
                                     
                                     β 
                                   
                                 
                                 - 
                                 
                                   
                                     
                                       C 
                                       1 
                                     
                                     
                                       
                                         C 
                                         1 
                                       
                                       + 
                                       
                                         C 
                                         2 
                                       
                                     
                                   
                                   ⁢ 
                                   
                                     ( 
                                     
                                       
                                         V 
                                         DATA 
                                       
                                       - 
                                       
                                         V 
                                         DD 
                                       
                                     
                                     ) 
                                   
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   6 
                 
               
             
           
         
       
     
     In Equation 8, Δ V G  is a gate voltage variation of the driving transistor (M 1 ) according to the voltage variation (V DATA −V DD ) of the A node, V DATA  is a data voltage, V DD  is a first power supply voltage, and V TH  is a threshold voltage of the driving transistor (M 1 ). Referring to Equation 5, the current (I OLED ) is controlled by the first power supply voltage (V DD ), the data voltage (V DATA ) and the first current (I sink ). 
     As described above, a driving circuit of a voltage programming technique compensates for deviations in the mobility and threshold of the driving transistors for the current programming period (T 1 ), and programming and driving a data voltage for the programming period (T 3 ). In other words, the driving circuit can compensate for the deviations in the mobility and threshold of the transistors that may occur from the voltage programming technique by first programming the current to the pixel circuit. Furthermore, the pixel circuit of a voltage programming technique programs a data voltage after programming the current to the pixel circuit, thereby reducing the time needed to charge the voltage in the capacitive element generated by the pixel circuit of the current programming technique. In other words, the disadvantages of the voltage programming technique and the current programming technique are obviated. 
       FIG. 9  is a circuit diagram of a pixel circuit of an organic light emitting display according to still another exemplary embodiment of the present invention. The following pixel circuit corresponds to one pixel circuit of the flat panel display  100  of  FIG. 4 . 
     Referring to  FIG. 9 , the pixel circuit of the organic light emitting display has the same configuration as  FIG. 5 , except for the second capacitive element (C 2 ). The second capacitive element (C 2 ) includes the first electrode electrically coupled between the first power supply voltage line (V DD ) and the driving transistor (M 1 ), and a second electrode electrically coupled between the first electrode of the first capacitive element (C 1 ) and the second electrode of the third switching element (S 3 ). 
       FIG. 10  is timing diagram of a pixel circuit of the organic light emitting display of FIG.  9 . The timing diagram of  FIG. 10  is nearly the same as that of  FIG. 6 . 
     For the current programming period (T 1 ), a scan signal of a low level is supplied to the direct scan line (Scan[n- 1 ]), so that the second to the fourth switching elements (S 2 , S 3  and S 4 ) are turned on. The second switching element (S 2 ) is turned on so that the driving transistor (M 1 ) is connected in a diode configuration. The third switching element (S 3 ) is turned on, so as to supply a first power supply voltage of the first power supply voltage line to the A node. The fourth switching element (S 4 ) is turned on, so as to cause the first current to flow to the driving transistor (M 1 ). The first current (I sink ) is obtained by Equation 9. 
     
       
         
           
             
               
                 
                   
                     
                       I 
                       
                         sin 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         k 
                       
                     
                     = 
                     
                       
                         
                           β 
                           2 
                         
                         ⁢ 
                         
                           
                             ( 
                             
                               
                                 V 
                                 GS 
                               
                               - 
                               
                                 V 
                                 TH 
                               
                             
                             ) 
                           
                           2 
                         
                       
                       = 
                       IOLED 
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       V 
                       GS 
                     
                     = 
                     
                       
                         
                           
                             2 
                             ⁢ 
                             
                               I 
                               
                                 sin 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 k 
                               
                             
                           
                           β 
                         
                       
                       + 
                       
                         V 
                         TH 
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   9 
                 
               
             
           
         
       
     
     In Equation 9, V GS  is a voltage between the gate and the source of the driving transistor (M 1 ), V TH  is a threshold of the driving transistor, and β is a constant. A voltage value (V GS ) to be stored in the gate and the source of the driving transistor (M 1 ) may be estimated by the first current (I sink ). Furthermore, a current flowing to the driving transistor (M 1 ), i.e., a current flowing to the organic light emitting display is controlled by the first current, so that the desired luminance maybe obtained regardless of deviations in the mobility and threshold of respective transistors. 
     For the delay period  1  (T 2 ) a scan signal of the scan line (Scan[n]) is maintained at a high level, and a data voltage (V DATA ) of the data line (Data[m]) is changed into a data voltage (V DATA ) corresponding to the pixel circuit coupled to the scan line (Scan[n]). If there is no delay period  1  (T 2 ), a scan signal of the scan line (Scan[n]) reaches a low level prior to the supplying of a present data voltage (V DATA ), and a direct data voltage supplied to the data line (Data[m]) is supplied to the driving transistor (M 1 ) through the first switching element (S 1 ). 
     For the programming period (T 3 ), a scan signal at a low level of the scan line (Scan[n]) is supplied and the first switching element (S 1 ) is turned on, so that a data signal is supplied to the A node. A voltage variation (T 1 →T 3 ) of the A node is obtained by Equation 10.
 
Δ V   A   =V   DATA   −V   DD   Equation 10:
 
     In other words, a voltage of the A node is a difference between the voltage (V DATA ) for the programming period (T 3 ) and the voltage (V DD ) for the current programming period (T 1 ). 
     For the delay period  2  (T 4 ), a scan signal of the scan line (Scan[n]) reaches a high level for a fixed time before a scan signal of the light emitting control line (Em[n]) reaches at a low level. This is for preventing a delay phenomenon that can occur due to the delay of respective elements in the operation of the pixel circuit. 
     For the light emitting period (T 5 ), a scan signal of a low level is supplied to the light emitting control line (Em[n]), the fifth switching element (S 5 ) is turned on, so that a voltage charged in the first and the second capacitive elements (C 1  and C 2 ), i.e., a current (I OLED ) corresponding to the gate-source (V GS ) of the driving transistor (M 1 ) is supplied to the OLED so as to emit light. The current (I OLED ) is obtained by Equation 11. 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           I 
                           OLED 
                         
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   V 
                                   GS 
                                 
                                 - 
                                 
                                   Δ 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     V 
                                     G 
                                   
                                 
                                 - 
                                 
                                   V 
                                   TH 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   
                                     
                                       2 
                                       ⁢ 
                                       
                                         I 
                                         
                                           sin 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           k 
                                         
                                       
                                     
                                     β 
                                   
                                 
                                 + 
                                 
                                   V 
                                   TH 
                                 
                                 - 
                                 
                                   ( 
                                   
                                     
                                       V 
                                       DATA 
                                     
                                     - 
                                     
                                       V 
                                       DD 
                                     
                                   
                                   ) 
                                 
                                 - 
                                 
                                   V 
                                   TH 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             β 
                             2 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   
                                     
                                       2 
                                       ⁢ 
                                       
                                         I 
                                         
                                           sin 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           k 
                                         
                                       
                                     
                                     β 
                                   
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     
                                       V 
                                       DATA 
                                     
                                     - 
                                     
                                       V 
                                       DD 
                                     
                                   
                                   ) 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   11 
                 
               
             
           
         
       
     
     In Equation 11, Δ V G  is a gate voltage variation of the driving transistor (M 1 ) according to the voltage variation (V DATA −V DD ) of the A node, V DATA  is a data voltage, V DD  is the first power supply voltage, and V TH  is a threshold voltage of the driving transistor. As shown in Equation 5, the current (I OLED ) is controlled, by the first power supply voltage (V DD ), the data voltage (V DATA ) and the first current (I sink ). 
     As shown above, the driving circuit is a voltage programming technique driven by compensating for the deviations in the mobility and threshold of the driving transistor (M 1 ) for the current programming period (T 1 ) and programming the data voltage for the programming period (T 3 ). In other words, the driving circuit can compensate for the deviations in the mobility and threshold of the transistors that occur from the voltage programming technique by first programming the current to the pixel circuit. Furthermore, the pixel circuit of the voltage programming technique programs the data voltage after programming the current to the pixel circuit, thereby reducing the time needed to charge a voltage in the capacitive element from the pixel circuit of the current programming technique. In other words, the disadvantages of the voltage programming technique and the current programming technique are obviated. 
     As described above, the organic light emitting display according to the present invention produces the following effect. 
     First, the organic light emitting display rapidly charges the data voltage using the voltage programming technique, after compensating for a deviations in the mobility and threshold of the driving transistor using the current programming technique, thereby resulting in a high quality and high resolution display device. 
     It should be understood by those of ordinary skill in the art that various replacements, modifications and changes in the form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. Therefore, it is to be appreciated that the above described embodiments are for purposes of illustration only and are not to be construed as being limitations of the present invention.