Abstract:
A stepper is combined with hardware that deposits a layer of material in the course of forming an integrated circuit, thus performing the deposition, patterning and cleaning without exposing the wafer to a transfer between tools and combining the function of three tools in a composite tool. The pattern-defining material is removed by the application of UV light through the mask of the stepper, thereby eliminating the bake and development steps of the prior art method. Similarly, a flood exposure of UV eliminates the cleaning steps of the prior art method.

Description:
TECHNICAL FIELD  
       [0001]     The field of the invention is that of fabricating integrated circuits (and micromachining), in particular depositing a patterned layer of material in the course of the formation of a structure.  
       BACKGROUND OF THE INVENTION  
       [0002]     The standard method of forming an integrated circuit consists basically of defining a pattern lithographically in a photosensitive material and then removing or depositing a layer of the integrated circuit according to the pattern.  
         [0003]     The lithography is performed in a composite tool that combines the steps of applying the photoresist, baking it, and developing it in a first unit and the step of exposing the resist to photons in a second unit. The two units are combined in a common envelope, referred to as a combined tool, so that transfer between the units does not expose the wafer to the ambient atmosphere in the clean room of the fab.  
         [0004]     The process requires a deposition tool, typically using a type of chemical vapor deposition to deposit the unpatterned layer material and an ashing tool to remove residues of the photoresist, for a total of three tools.  
         [0005]     A clean room has a highly controlled ambient atmosphere that is nevertheless more contaminated with foreign matter than the atmosphere within the composite lithography tool.  
         [0006]     A simplified list of the steps on the material deposition and pattern process is set forth in Table I.  
                       TABLE I                                       Blanket material deposition           Resist coat           Softbake Resist           Wafer transfer to Stepper           Pattern Exposure           Wafer transfer from stepper           Hardbake Resist           Develop Resist           Etch Removal of Deposited Material           Wafer Transfer to Ashing Tool           Ash Resist           Post Removal Clean                      
 
         [0007]     In many integrated circuits using advanced technology, this sequence may be repeated up to 20 times. Integrated circuits using embedded DRAM modules require even more steps.  
         [0008]     The manufacture of integrated circuits is a highly competitive field and manufacturers are constantly seeking to reduce costs.  
         [0009]     The art could benefit from a process for forming a patterned layer that requires fewer steps and/or fewer tools than the current process.  
       SUMMARY OF THE INVENTION  
       [0010]     The invention relates to a combined apparatus for forming a patterned layer of a structure material on a workpiece, incorporating within a common enclosure a deposition module for depositing and removing material and an exposure module for defining a pattern in a photosensitive pattern material.  
         [0011]     A feature of the invention is that the material removal step in the patterning of a layer of pattern material is performed in the same chamber as the exposure of the material.  
         [0012]     Another feature of the invention is that the patterning process is effected by exposure to particles (photons or electrons), which remove the pattern-defining material as a vapor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  shows in partially schematic, partially pictorial fashion, a simplified diagram of an apparatus for practicing the invention.  
         [0014]      FIGS. 2-7  show in cross section steps in forming two layers of a structure.  
         [0015]      FIG. 8  shows a block diagram of the apparatus. 
     
    
     DETAILED DESCRIPTION  
       [0016]      FIG. 1  shows a simplified diagram of an apparatus  100  for practicing the invention, in which the right side of the Figure, denoted with numeral  110  is an exposure module that performs the functions of a stepper, generating a beam of ultraviolet photons in source  20  that passes through mask  30 , which carries the pattern to be imposed on the workpiece  10 , illustratively a semiconductor wafer that will contain a set of integrated circuits (ICs). Workpiece  10  is carried by pedestal  50  that is moved as indicated by arrow  105  in a conventional fashion to place a particular IC under the patterned beam.  
         [0017]     On the left side of the Figure, deposition module  120  has a set of input gas lines. Line  42  carries the Self-Assembled siloxane-based organic Material (SAM) that adsorbs on the surface of the wafer to form an unpatterned film. Alternatively, line  44  may carry a similar deposition inhibitor material that has the property that it vaporizes upon exposure to electrons or photons. Line  44  carries a purge gas, such as argon or nitrogen. Line(s)  46  carry the precursor(s) of the structure material that will be deposited in apertures to be formed in the SAM by the UV. Line  48  carries an oxidizer which is used in the deposition process.  
         [0018]     Dashed line  102  denotes schematically an optional separation between chambers that perform the functions of deposition and particle exposure.  
         [0019]     In operation, as shown in  FIG. 2 , a wafer is introduced to the deposition module and receives a film of SAM  15 , referred to generally as a pattern material, that adsorbs evenly across the wafer surface. The film  15  is patterned by exposure to UV radiation  32  from source  20 , patterned by mask  30 . The effect of this exposure is to remove the SAM that is exposed to the UV. The exposed material becomes volatile and exits along line  41 , leaving a patterned layer containing a set of apertures  12  that are to be filled with a structure material that will be part of the IC, at least temporarily, e.g. the structure material may be a conductor in the back end of the integrated circuit.  
         [0020]     Illustratively, the filling mechanism is Atomic Layer Deposition (ALD), the apparatus for which is represented schematically by block  130  in Deposition Module  120 . A criterion for selecting the deposition method and deposited material is that it selectively fills the exposed apertures  12  without adhering to the SAM. SAM  15  has the property that it is hydrophobic, and the material deposited by the ALD process is required to have the property that it does not adhere to hydrophobic materials. This is a general rule with ALD and thus there are few restrictions in materials to be deposited. Consequently, the ALD deposition is selective and the problem of removing unwanted material from the unpatterned portion of the SAM does not arise. Alternatively, Chemical Vapor Deposition (CVD) may be used, if it is preferred in a particular application.  
         [0021]     When the apertures  12  have been filled with a first material  210 , as shown in  FIG. 3 , the remaining SAM material can be removed by a flood exposure of UV. Alternatively, in the example illustrated in  FIG. 4 , a second layer of SAM  17  is deposited and patterned by a second mask to cover the first deposited material  210 . The step of  FIG. 4  may be used in the case where more than one material is desired on the same level. However, this step may be performed before any later step and any number or repeats may be performed.  
         [0022]      FIG. 5  shows the result of a second patterning of SAM layer 15  with UV  32  patterned by mask  31  to open apertures  14  in the first layer of SAM  15 .  
         [0023]     A second layer of structure material  212  is deposited by ALD as shown in  FIG. 6 , illustratively with a different thickness from layer  210 . The structures formed from layer  210  on the left side of the figure, being protected by SAM  17  are unchanged, while the stub of material  210  on the right side is covered by a layer of material  212 .  
         [0024]      FIG. 7  shows the final structure after a clean up flood exposure of UV  32 , with separate blocks of material  210  and  212  on the left and a composite structure of both materials on the right. Optionally, a layer of dielectric may be deposited by CVD and planarized by chemical-mechanical polishing. The dielectric may be deposited in the invented combined tool using conventional precursors or in a specialized CVD tool and the planarization may be performed in a conventional CMP tool. This option may be used if more than one layer is to be formed and if a planar surface is desired for the next layer.  
         [0025]      FIG. 8  shows a flow chart of the process illustrated in  FIGS. 2 through 7 . The wafer is inserted in the tool in step  305 , either a separate deposition chamber as illustrated in  FIGS. 1 and 9  or a combined chamber that contains apparatus for performing both functions of deposition and exposure.  
         [0026]     A first layer of SAM is deposited in step  310 .  
         [0027]     The SAM is exposed by UV through a mask in step  320 .  
         [0028]     A first layer of ALD material is put down in step  330 .  
         [0029]     Optionally, as shown by line  350 , a second layer of SAM can be put down at this time without removing the first layer, returning to step  310 .  
         [0030]     As an alternative, the first layer can be removed by a flood exposure of UV in step  340  and the path denoted by line  350 ′ can be taken.  
         [0031]     The process of depositing a patterned layer according to the invention is summarized in TABLE II.  
                       TABLE II                                       Deposition of (siloxane-based) deposition inhibitor blanket coat           Pattern definition and removal of inhibitor by UV light           Selective deposition in open areas           Flood UV exposure to remove inhibitor                      
 
         [0032]     Those skilled in the art will appreciate that the prior art process of TABLE I requires nine steps and three tools (stepper, deposition, and ashing), while the process according to the invention requires only four steps in a single tool.  
         [0033]     An alternative representation of the tool is shown in  FIG. 9 , highlighting the physical relationship between the deposition module and the exposure module. Block  100  in  FIG. 9  represents the overall tool structure of the tool, which may include all components located in close proximity or may include physically separate chambers that have different atmospheres. Incorporating all components in a single enclosure would save cost.  
         [0034]     In a particular example, the optics of the stepper must be extremely precise and even a thin coating of material from the SAM or the structure material  210  may alter the focus of the UV beam. It may, therefore, be advisable to reduce this possibility by isolating the deposition environment from the patterning environment using separate chambers for each function.  
         [0035]     Referring again to  FIG. 9 , block  102 , labeled material handler, represents the conventional robotic handler that receives the wafer from the transfer module circulating in the fab and transfers it between the deposition module  120  (also referred to as the means for depositing a structure material) and the exposure module  110  as required by the process being carried out.  
         [0036]     The patterning of the pattern material (the SAM, which embodies the pattern) may be carried out by an electron beam (direct-write or projection lithography) in which case the pattern unit may be a deflection unit for controllably deflecting the beam.  
         [0037]     Wafer  10  has been referred to as a workpiece because the apparatus can be applied to micromachining of many types and is not confined to integrated circuits.  
         [0038]     While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.