Abstract:
A semiconductor device includes an upper conductive strip group and a lower conductive strip group crossing under the upper conductive strip group. Adjacent first and second conductive strips of the upper conductive strip group are adapted to receive a first voltage, a third conductive strip of the lower conductive strip group is adapted to receive a second voltage. A capacitor is provided at a first intersection between the first and third conductive strips and at a second intersection between the second and third conductive strip, and the capacitor extends from the first intersection to the second intersection.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device including so-called decoupling capacitors connected between power supply conductive strips and ground conductive strips for stabilizing a power supply voltage supplied to the power supply conductive strips and a ground voltage supplied to the ground conductive strips. 
         [0003]    2. Description of the Related Art 
         [0004]    In a semiconductor device, so-called decoupling capacitors are connected between power supply conductive strips and ground conductive strips, in order to stabilize a power supply voltage supplied to the power supply conductive strips and a ground voltage supplied to the ground conductive strips (see: WO00/67324 and U.S. Pat. No. 6,600,209B1). Also, a metal-insulator-metal (MIM) capacitor is disclosed in “A High Reliability Metal Insulator Metal Capacitor for 0.18 μm Copper Technology”, M. Armacost, A. Augustin, P. Felsner, Y. Feng, G. Friese, J. Heidenreich, G. Hueckel, O. Prigge, K. Stein (2000 IEEE). 
         [0005]    A prior art semiconductor device is constructed by a plurality of lower conductive strips formed on a semiconductor substrate and extending in parallel to each other in a first direction and a plurality of upper conductive strips formed over the lower conductive strips and extending in parallel to each other in a second direction perpendicular to the first direction. The odd-numbered lower conductive strips receive a power supply voltage and the even-numbered lower conductive strips receive a ground voltage. Similarly, the odd-numbered upper conductive strips receive the power supply voltage and the even-numbered upper conductive strips receive the ground voltage. A plurality of unit capacitors are formed at intersections between the odd-numbered lower conductive strips and the even-numbered upper conductive strips and at intersections between the even-numbered lower conductive strips and the odd-numbered upper conductive strips (see; WO00/67324 and U.S. Pat. No. 6,300,209B1). 
       SUMMARY OF THE INVENTION 
       [0006]    In the above-described prior art semiconductor device, however, since each of the unit capacitors is provided only at the intersections between the lower conductive strips and the upper conductive strips, the capacitance of each of the unit capacitors is so small that the total capacitance of the unit capacitors is small. As a result, the unit capacitors would not sufficiently serve as a decoupling capacitor whose capacitance is required to be large. 
         [0007]    According to the present invention, a semiconductor device includes an upper conductive strip group and a lower conductive strip group crossing under the upper conductive strip group. Adjacent first and second conductive strips of the upper conductive strip group are adapted to receive a first voltage, and a third conductive strip of the lower conductive strip group is adapted to receive a second voltage. A capacitor is provided at a first intersection between the first and third conductive strips and at a second intersection between the second and third conductive strip, and the capacitor extends from the first intersection to the second intersection. 
         [0008]    Also, a semiconductor device includes an upper conductive strip group and a lower conductive strip group crossing under the upper conductive strip group. First and second conductive strips of the upper conductive strip group are adapted to receive a first voltage and a second voltage, respectively, and a third conductive strip of the lower conductive strip group is adapted to receive the second voltage. A capacitor includes a lower electrode layer, an upper electrode layer and a dielectric layer sandwiched by the lower electrode layer and the upper electrode layer. The upper electrode layer is connected to the conductive strip and the lower electrode layer is connected to the second conductive strip. The second conductive strip is connected to the third conductive strip. 
         [0009]    On the other hand, a semiconductor device includes a lower conductive strip group and an upper conductive strip group crossing over the lower conductive strip group. Adjacent first and second conductive strips of the lower conductive strip group are adapted to receive a first voltage, and a third conductive strip of the upper conductive strip group is adapted to receive a second voltage. A capacitor is provided at a first intersection between the first and third conductive strips and at a second intersection between the second and third conductive strip, and the capacitor extends from the first intersection to the second intersection. 
         [0010]    Also, a semiconductor device includes a lower conductive strip group and an upper conductive, strip group crossing over the upper conductive strip group. First and second conductive strips of the lower conductive strip group are adapted to receive a first voltage and a second voltage, respectively, and a third conductive strip of the upper conductive strip group is adapted to receive said second voltage. A capacitor includes a lower electrode layer, an upper electrode layer and a dielectric layer sandwiched by the lower electrode layer and the upper electrode layer. The lower electrode layer is connected to the conductive strip, the upper electrode layer is connected to the second conductive strip, and the second conductive strip is connected to the third conductive strip. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present invention will be more clearly understood from the description set forth below, with reference to the accompanying drawings, wherein: 
           [0012]      FIG. 1  is a plan view illustrating a first embodiment of the semiconductor device according to the present invention; 
           [0013]      FIG. 2A  is a first partial enlargement of the semiconductor device of  FIG. 1 ; 
           [0014]      FIG. 2B  is a cross-sectional view taken along the line II-II of  FIG. 2A ; 
           [0015]      FIG. 3A  is a second partial enlargement of the semiconductor device of  FIG. 1 ; 
           [0016]      FIG. 3B  is a cross-sectional view taken along the line III-III of  FIG. 3A ; 
           [0017]      FIG. 4  is a plan view illustrating a second embodiment of the semiconductor device according to the present invention; 
           [0018]      FIG. 5A  is a first partial enlargement of the semiconductor device of  FIG. 4 ; 
           [0019]      FIG. 6B  is a cross-sectional view taken along the line V-V of  FIG. 5A ; 
           [0020]      FIG. 6A  is a second partial enlargement of the semiconductor device of  FIG. 4 ; and 
           [0021]      FIG. 6B  is a cross-sectional view taken along the line VI-VI of  FIG. 6A . 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0022]    In  FIG. 1 , which illustrates a first embodiment of the semiconductor device according to the present invention, a plurality of lower conductive strips L 1 , L 2 , L 3 , L 4 , L 5 , L 6 , . . . extend in parallel to each other in an X direction, and upper conductive strips U 1 , U 2 , U 3 , U 4 , U 5 , U 6 , . . . extend in parallel to each other in a Y direction perpendicular to the X direction. 
         [0023]    Every three lower conductive strips L 1 , L 2 , L 3 , L 4 , L 5 , L 6 ; . . . alternately receive a power supply voltage V DD  and a ground voltage GND. That is, the lower conductive strips L 1 , L 2 , L 3 ; L 7 , L 8 , L 9 ; . . . receive the power supply voltage V DD , and the lower conductive strips L 4 , L 5 , L 6 ; L 10 , L 11 , L 12  . . . receive the ground voltage GND. Similarly, every three upper conductive strips U 1 , U 2 , U 3 ; U 4 , U 5 , U 6 ; . . . alternately receive the power supply voltage V DD  and the ground voltage GND. That is, the upper conductive strips U 1 , U 2 , U 3 ; U 7 , U 8 , U 8 ; . . . receive the power supply voltage V DD , and the upper conductive strips U 4 , U 5 , U 6 ; U 10 , U 11 , U 12  . . . receive the ground voltage GND. 
         [0024]    Also, a plurality of capacitors each formed by one lower electrode layer LE and one upper electrode layer UE are staggered at every three lower conductive strips L 1 , L 2 , L 3 , . . . , and at every three upper conductive strips U 1 , U 2 , U 3 , . . . . In this case, all the capacitors have the same structure. Additionally, the spacing of the capacitors along the X direction is one upper conductive strip, while the spacing of the capacitors along the Y direction is minimum which would sufficiently prevent them from being short-circuited with each other. In more detail, one capacitor is provided between the three consecutive lower conductive strips receiving one of the power supply voltage V DD  and the ground voltage GND and the three consecutive upper conductive strips receiving the other of the power supply voltage V DD  and the ground voltage GND including their immediately adjacent upper conductive strips. Thus, the areas of the lower electrode layer LE and the upper electrode layer UE can be increased as compared with those of the three lower conductive strips and the three upper conductive strips. As a result, the capacitance of the capacitors can be increased, so that the voltages at the lower conductive strips and the upper conductive strips can be stabilized. 
         [0025]    Particularly, since the lower electrode layer LE and the upper electrode layer UE extend a spacing between the lower conductive strips L 1 , L 2 , L 3 , . . . and a spacing between the upper conductive strips U 1 , U 2 , U 3 , . . . , the capacitance of the capacitors can be remarkably increased as compared with the prior art where capacitors are formed only at intersections between the lower conductive strips and the upper conductive strips. 
         [0026]    Note that via structures V 1  each formed by 3×3 vias are provided for connecting respective ones of the lower conductive strips to respective ones of the upper conductive strips, with the respective lower conductive strips and the respective upper conductive strips receiving the same voltage, thus further stabilizing the power supply voltage V DD  and the ground voltage GND. 
         [0027]    The capacitor of  FIG. 1  which is formed between the lower conductive strips L 4 , L 5  and L 6  and the upper conductive strips U 7 , U 8  and U 9  including their immediately adjacent upper conductive strips U 6  and U 10  is explained next with reference to  FIG. 2A  and  FIG. 2B  which is a cross-sectional view taken along the line II-II of  FIG. 2A . 
         [0028]    As illustrated in  FIG. 2A , the lower electrode layer LE opposes the three lower conductive strips L 4 , L 5  and L 6  and the five upper conductive strips U 6 , U 7 , U 8 , U 9  and U 10 . On the other hand, the upper electrode layer UE opposes the three lower conductive strips L 4 , L 5  and L 6  and the three upper conductive strips U 7 , U 8  and U 9 . That is, the lower electrode layer LE is outwardly protruded from the upper electrode layer UE along the X direction. This also would increase the capacitance of the capacitor. 
         [0029]    The lower conductive strips L 4 , L 5  and L 6  (=GND) are connected to the upper conductive strips U 6  and U 10  (=GND) with interstitial via structures V 2  each formed by three vias. 
         [0030]    The lower electrode layer LE (=GND) is connected to the upper conductive strips U 6  and U 10  (=GND) with interstitial via structures V 3  each formed by three vias. 
         [0031]    The upper electrode layer UE (=V DD ) is connected to the upper conductive strips U 7 , U 8  and U 9  (−V DD ) with interstitial via structures V 4  each formed by 3×3 vias. 
         [0032]    Also, as illustrated in  FIG. 2B , a semiconductor substrate (not shown) where semiconductor transistor circuits and the like are formed is provided. Also, an insulating layer (not shown) is formed on the semiconductor substrate. Then, the lower conductive layer such as L 5 , an insulating interlayer  21 , the lower electrode layer LE, a dielectric layer  22 , the upper electrode layer UE and an insulating interlayer  23  are formed in this order. 
         [0033]    Further, the via structures V 2 , V 3  and V 4  are formed within the insulating interlayer  21 , the dielectric layer  22  and the insulating interlayer  23  simultaneous with the formation of the via structures V 1  of  FIG. 1 . In this case, the via structures V 2  are connected to the lower conductive strip L 5 , the via structures V 3  are connected to the lower electrode layer LE, and the via structures V 4  are connected to the upper electrode layer UE. 
         [0034]    Note that via structures (not shown) are formed, so that the lower conductive strips and the upper conductive strips are connected to the semiconductor substrate. As a result, the semiconductor substrate is subjected to the power supply voltage V DD  and the ground voltage GND. All the via structures V 1 , V 2 , V 3  and V 4  can be formed at once to decrease the manufacturing steps. 
         [0035]    Additionally, the upper conductive strips U 6 , U 7 , U 8 , U 9  and U 10  are formed on the insulating interlayer  23 . In this case, the upper conductive strips U 6  and U 10  are connected by the via structures V 2  and V 3  to the lower conductive layer L 5  and the lower electrode layer LE. Also, the upper conductive strips U 7 , U 8  and U 9  are connected by the via structure V 4  to the upper electrode layer UE. 
         [0036]    The insulating interlayer  23  is thicker than the insulating interlayer  21 . For example, the insulating interlayers  21  and  23  are about 20 nm thick and about 500 nm thick, respectively. In this case, the thickness of the capacitor formed by the lower electrode layer LE, the upper electrode layer UE, the dielectric layer  22  sandwiched the lower electrode layer LE and the upper electrode layer UE is about 400 nm thick. As a result, the power supply voltage V DD  at the upper conductive strips U 7 , U 8  and U 9  in stabilized directly by the capacitor, and the ground voltage GND is stabilized indirectly by the capacitor. 
         [0037]    Additionally, the insulating interlayer  21  and  23  are so thick that a leakage current flowing from the upper conductive strips to the lower conductive strips can be suppressed. 
         [0038]    Further, the lower electrode layer LE and the upper electrode layer UE of the capacitor are separated from the lower conductive strip L 5  and the upper conductive strips U 5 , U 7 , U 8 , U 9  and U 10 , so that the lower electrode layer LE can be in proximity to the upper electrode layer UE. As a result, the capacitance of the capacitor can be increased, which would further stabilize the power supply voltage V DD  and the ground voltage GND. 
         [0039]    Additionally, since the upper conductive strips U 7 , U 8  and U 9  receives the same voltage, i.e., the power supply voltage V DD , so that there is no leakage current issue therebetween, the upper conductive strips U 7 , U 8  and U 9  can be as close as possible. As a result, a chemical mechanical polishing (CMP) process can easily be performed upon the insulating interlayer  23 . 
         [0040]    Thus, in  FIGS. 2A and 2B , the two adjacent upper conductive strips such as U 7  and U 8  receive the power supply voltage V DD , and the lower conductive strip L 5  receives the ground voltage GND. The capacitor is provided at a first intersection between the upper conductive strip U 7  and the lower conductive strip L 6  and at a second intersection between the upper conductive strip U 8  and the lower conductive strip L 6 . The capacitor extend from the first intersection to the second intersection. 
         [0041]    Also, in  FIGS. 2A and 2B , the upper electrode UE (=V DD ) is connected to the upper conductive strips U 7  and U 8  (=V DD ), while the lower electrode UE (=GND) is connected via the upper conductive strip U 6  (=GND) to the lower conductive strip L 5  (=GND). 
         [0042]    The capacitor of  FIG. 1  which is formed between the lower conductive strips L 7 , L 8  and L 9  and the upper conductive strips U 4 , U 5  and U 6  including their immediately adjacent upper conductive strips U 3  and U 7  is explained next with reference to  FIG. 3A  and  FIG. 3B  which is a cross-sectional view taken along the line III-III of  FIG. 3A . 
         [0043]    As illustrated in  FIG. 3A , the lower electrode layer LE opposes the three lower conductive strips L 7 , L 8  and L 9  and the five upper conductive strips U 3 , U 4 , U 5 , U 6  and U 7 . On the other hand, the upper electrode layer UE opposes the three lower conductive strips L 7 , L 8  and L 9  and the three upper conductive strips U 4 , U 5  and U 6 . That is, the lower electrode layer LE is also outwardly protruded from the upper electrode layer UE along the X direction. This also would increase the capacitance of the capacitor. 
         [0044]    The lower conductive strips L 7 , L 8  and L 9  (=V DD ) are connected to the upper conductive strips U 3  and U 7  (=V DD ) with interstitial via structures V 2  each formed by three vias. 
         [0045]    The lower electrode layer LE (=V DD ) is connected to the upper conductive strips U 3  and U 7  (=V DD ) with interstitial via structures V 3  each formed by three vias. 
         [0046]    The upper electrode layer UE (=GND) is connected to the upper conductive strips U 4 , U 5  and U 6  (=GND) with interstitial via structures V 4  each formed by 3×3 vias. 
         [0047]    Also, as illustrated in  FIG. 3B , in the same way as in  FIG. 2B , the lower conductive layer such as L 8 , an insulating interlayer  21 , the lower electrode layer LE, a dielectric layer  22 , the upper electrode layer UE and an insulating interlayer  23  are formed in this order. Further, the via structures V 2 , V 3  and V 4  are formed within the insulating interlayer  21 , the dielectric layer  22  and the insulating interlayer  23  simultaneous with the formation of the via structures V 1  of  FIG. 1 . 
         [0048]    Thus, in  FIGS. 3A and 3B , the two adjacent upper conductive strips such as U 4  and U 5  receive the ground voltage GND, and the lower conductive strip L 8  receives the power supply voltage V DD . The capacitor is provided at a first intersection between the upper conductive strip U 4  and the lower conductive strip L 8  and at a second intersection between the upper conductive strip U 5  and the lower conductive strip L 8 . The capacitor extends from the first intersection to the second intersection. 
         [0049]    Also, in  FIGS. 3A and 3B , the upper electrode UE (=GND) is connected to the upper conductive strips U 4  and U 6  (&#39;GND), while the lower electrode UE (=V DD ) is connected via the upper conductive strip U 3  (=V DD ) to the lower conductive strip L 5  (=V DD ). 
         [0050]    A method for manufacturing the semiconductor device of  FIG. 1  is briefly explained below. 
         [0051]    First, in accordance with a metal depositing process and a photolithography and etching process, lower conductive strips L 1 , L 2 , L 3 , . . . are formed on an insulating layer which is formed on a semiconductor substrate where semiconductor transistor circuits are already formed. 
         [0052]    Next, an about 20 nm thick insulating interlayer  21  is formed by a chemical vapor deposition (CVD) process. Then, a metal layer made of Ti, TiN, Ta or TaN is deposited and is patterned by a photolithography and etching process to complete the lower electrode layer LE. 
         [0053]    Next, a dielectric layer  22  is formed by a CVD process. Then, a metal layer made of Ti, TiN, Ta or TaN is deposited and is patterned by a photolithography and etching process to complete the upper electrode layer UE. 
         [0054]    Next, an about 500 nm thick insulating interlayer  23  is deposited by a CVD process. Then, a CMP process is performed upon the insulating interlayer  23  to flatten it. 
         [0055]    Finally, via holes for via structures V 1 , V 2 , V 3  and V 4  and grooves for upper conductive strips U 1 , U 2 , . . . are formed by a dual damascene process. Then, metal is deposited and is buried in the via holes and grooves by a CMP process to complete the via structures V 1 , V 2 , V 3  and V 4  and the upper conductive strips U 1 , U 2 , . . . , which would avoid disconnection of the via structures V 1 , V 2 , V 3  and V 4  and the upper conductive strips U 1 , U 2 , . . . . 
         [0056]    In  FIG. 4 , which illustrates a second embodiment of the semiconductor device according to the present invention, a plurality of upper conductive strips U 1 , U 2 , U 3 , U 4 , U 5 , U 6 , . . . extend in parallel to each other in the X direction, and lower conductive strips L 1 , L 2 , L 3 , L 4 , L 5 , L 6 , . . . extend in parallel to each other in the Y direction. 
         [0057]    Even in this case, every three lower conductive strips L 1 , L 2 , L 3 ; L 4 , L 5 , L 6 ; . . . alternately receive the power supply voltage V DD  and the ground voltage GND, and every three upper conductive strips U 1 , U 2 , U 3 ; U 4 , U 5 , U 6 ; . . . alternately receive the power Supply voltage V DD  and the ground voltage GND. 
         [0058]    Also, a plurality of capacitors each formed by one lower electrode layer LE and one upper electrode layer UE are staggered at every three lower conductive strips L 1 , L 2 , L 3 , . . . , and at every three upper conductive strips U 1 , U 2 , U 3 , . . . . In this case, all the capacitors have the same structure. Additionally, the spacing of the capacitors along the X direction is one lower conductive strip, while the spacing of the capacitors along the Y direction is minimum which would sufficiently prevent them from short-circuiting each other. In more detail, one capacitor is provided between the three consecutive upper conductive strips receiving one of the power supply voltage V DD  and the ground voltage GND and the three consecutive lower conductive strips receiving the other of the power supply voltage V DD  and the ground voltage GND including their immediately adjacent lower conductive strips. Thus, the areas of the lower electrode layer LE and the upper electrode layer UE can be increased as compared with those of the three lower conductive strips and the three upper conductive strips. As a result, the capacitance of the capacitors can be increased, so that the voltages at the lower conductive strips and the upper conductive strips can be stabilized. 
         [0059]    Particularly, since the lower electrode layer LE and the upper electrode layer UE extend a spacing between the lower conductive strips L 1 , L 2 , L 3 , . . . and a spacing between the upper conductive strips U 1 , U 2 , U 3 , . . . , the capacitance of the capacitors can be remarkably increased as compared with the prior art where capacitors are formed only at intersections between the lower conductive strips and the upper conductive strips. 
         [0060]    Note that via structures V 1 ′ each formed by 3×3 vias are provided for connecting respective ones of the lower conductive strips to respective ones of the upper conductive strips, with the respective lower conductive strips and the respective upper conductive strips receiving the same voltage, thus further stabilizing the power supply voltage V DD  and the ground voltage GND. 
         [0061]    The capacitor of  FIG. 4  which is formed between the upper conductive strips U 4 , U 5  and U 6  and the lower conductive strips L 7 , L 8  and L 9  including their immediately adjacent lower conductive strips L 6  and L 10  is explained next with reference to  FIG. 5A  and  FIG. 5B  which is a cross-sectional view taken along the line V-V of  FIG. 5A . 
         [0062]    As illustrated in  FIG. 5A , the upper electrode layer UE opposes the three upper conductive strips U 4 , U 5  and U 6  and the five lower conductive strips L 6 , L 7 , L 8 , L 9  and L 10 . On the other hand, the lower electrode layer LE opposes the three upper conductive strips U 4 , U 5  and U 6  and the three lower conductive strips L 7 , L 8  and L 9 . That is, the upper electrode layer UE is outwardly protruded from the lower electrode layer LE along the X direction. This also would increase the capacitance of the capacitor. 
         [0063]    The lower electrode layer LE (=V DD ) is connected to the lower conductive strips L 7 , L 8  and L 9  (=V DD ) with interstitial via structures V 2 ′ each formed by 3×3 vias. 
         [0064]    The upper electrode layer UE (=GND) is connected to the lower conductive strips L 6  and L 10  (=GND) with interstitial via structures V 3 ′ each formed by three vias. 
         [0065]    The upper conductive strips U 4 , U 5  and U 6  (=GND) are connected to the lower conductive strips L 6  and L 10  (=GND) with interstitial via structures V 4 ′ each formed by three vias. 
         [0066]    Also, as illustrated in  FIG. 5B , a semiconductor substrate (not shown) where semiconductor transistor circuits and the like are formed is provided. Also, an insulating layer (not shown) is formed on the semiconductor substrate. Then, the lower conductive layers L 6 , L 7 , L 8 , L 9  and L 10 , an insulating interlayer  31 , the lower electrode layer LE, a dielectric layer  32 , the upper electrode layer UE, an insulating interlayer  33  and the upper conductive strip such as U 6  are formed in this order. 
         [0067]    Further, the via structures V 2 ′, V 3 ′ and V 4 ′ are formed within the insulating interlayer  31 , the dielectric layer  32  and the insulating interlayer  33  with the formation of the via structures V 1 ′ of  FIG. 4 . In this case, the via structures V 2 ′ are connected between the lower electrode layer LE and the lower conductive strips L 7 , L 8  and L 9 , the via structures V 3 ′ are connected between the upper electrode layer UE and the lower conductive strips L 6  and L 10 , and the via structures V 4 ′ are connected between the upper electrode layer UE and the lower conductive strips L 6  and L 10 . 
         [0068]    Note that via structures (not shown) are formed, so that the lower conductive strips and the upper conductive strips are connected to the semiconductor substrate. As a result, the semiconductor substrate is subjected to the power supply voltage V DD  and the ground voltage GND. Also, the via structures V 1 ′, V 2 ′, V 3 ′ and V 4 ′ are separately formed which would Increase the manufacturing steps. 
         [0069]    The insulating interlayer  31  is thicker than the insulating interlayer  33 . For example, the insulating interlayer  31  and  33  are about 500 nm thick and about 20 nm thick, respectively. In this case, the thickness of the capacitor formed by the lower electrode layer LE, the upper electrode layer UE, the dielectric layer  32  sandwiched by the lower electrode layer LE and the upper electrode layer UE is about 400 nm thick. As a result, the power supply voltage V DD  at the lower conductive strips L 7 , L 8  and L 9  is stabilized directly by the capacitor, and the ground voltage GND is stabilized indirectly by the capacitor. 
         [0070]    Additionally, the insulating interlayer  31  and  33  are so thick that a leakage current flowing from the lower conductive strips to the upper conductive strips can be suppressed. 
         [0071]    Further, the lower electrode layer LE and the upper electrode layer UE of the capacitor are separated from the upper conductive strip U 5  and the lower conductive strips L 6 , L 7 , L 8 , L 9  and L 10 , so that the lower electrode layer LE can be in proximity to the upper electrode layer UE. As a result, the capacitance of the capacitor can be increased, which would further stabilize the power supply voltage V DD  find the ground voltage GND. 
         [0072]    Additionally, since the upper conductive strips U 4 , U 5  and U 6  receives the same voltage, i.e., the ground voltage GND, so that there is no leakage current issue therebetween, the upper conductive strips U 4 , U 5  and U 6  can be as close as possible. As a result, a chemical mechanical polishing (CMP) process can easily be performed upon the insulating interlayer  33 . 
         [0073]    Thus, in  FIGS. 5A and 5B , the two adjacent lower conductive strips such as L 7  and L 8  receive the power supply voltage V DD , and the upper conductive strip U 5  receives the ground voltage GND. The capacitor is provided at a first intersection between the lower conductive strip L 7  and the upper conductive strip U 5  and at a second intersection between the lower conductive strip L 5  and the upper conductive strip U 5 . The capacitor extends from the first intersection to the second intersection. 
         [0074]    Also, in  FIGS. 5A and 5B , the lower electrode LE (=V DD ) is connected to the lower conductive strips L 7  and L 8  (=V DD ), while the upper electrode UE (=GND) is connected via the lower conductive strip L 6  (=GND) to the upper conductive strip U 5  (=GND). 
         [0075]    The capacitor of  FIG. 4  which is formed between the upper conductive strips U 7 , U 8  and U 9  and the lower conductive strips L 4 , L 5  and L 6  including their immediately adjacent lower conductive strips L 3  and L 7  is explained next with reference to  FIG. 6A  and  FIG. 6B  which is a cross-sectional view taken along the line VI-VI of  FIG. 6A . 
         [0076]    As illustrated in  FIG. 6A , the upper electrode layer UE opposes the three upper conductive strips U 7 , U 8  and U 9  and the five lower conductive strips L 3 , L 4 , L 5 , L 6  and L 7 . On the other hand, the lower electrode layer LE opposes the three upper conductive strips U 7 , U 8 , and U 9  and the three lower conductive strips L 4 , L 5  and L 6 . That is, the upper electrode layer UE is also outwardly protruded from the lower electrode layer LE along the X direction. This also would increase the capacitance of the capacitor. 
         [0077]    The lower electrode layer LE (=GND) is connected to the lower conductive strips L 4 , L 5  and L 6  (=GND) with interstitial via structures V 2 ′ each formed by 3×3 vias. 
         [0078]    The upper electrode layer UE (=V DD ) is connected to the lower conductive strips L 3  and L 7  (=V DD ) with interstitial via structures V 3 ′ each formed by three vias. 
         [0079]    The upper conductive strips U 7 , U 8  and U 9  (=V DD ) are connected to the lower conductive strips L 3  and L 7  (=V DD ) with interstitial via structures V 4 ′ each formed by three vias. 
         [0080]    Also, as illustrated in  FIG. 6B , in the same way as in  FIG. 5B , the lower conductive layers L 6 , L 7 , L 8 , L 9  and L 10 , an insulating interlayer  31 , the lower electrode layer LE, a dielectric layer  32 , the upper electrode layer UE, an insulating interlayer  33  and the upper conductive strip such as U 5  are formed in this order. Further, the via structures V 2 ′, V 3 ′ and V 4 ′ are formed within the insulating interlayer  31 , the dielectric layer  32  and the insulating interlayer  33  with the formation of the via structures V 1 ′ of  FIG. 4 . 
         [0081]    Thus, in  FIGS. 6A and 6B , the two adjacent lower conductive strips such as L 4  and L 5  receive the ground voltage GND, and the upper conductive strip U 8  receives the power supply voltage V DD . The capacitor is provided at a first intersection between the lower conductive strip L 4  and the upper conductive strip U 8  and at a second intersection between the lower conductive strip L 5  and the upper conductive strip U 8 . The capacitor extends from the first intersection to the second intersection. 
         [0082]    Also, in  FIGS. 6A and 6B , the lower electrode LE (=GND) is connected to the lower conductive strips L 4  and L 5  (=GND), while the upper electrode UE (=V DD ) is connected via the lower conductive strip L 3  (=V DD ) to the upper conductive strip U 8  (=V DD ). 
         [0083]    A method for manufacturing the semiconductor device of  FIG. 4  is briefly explained below. 
         [0084]    First, in accordance with a metal depositing process and a photolithography and etching process, lower conductive strips L 1 , L 2 , L 3 , . . . are formed on an insulating layer which is formed on a semiconductor substrate where semiconductor transistor circuits are already formed. 
         [0085]    Next, an about 500 nm thick insulating interlayer  31  is formed by a chemical vapor deposition (CVD) process. Then, via holes for via structures V 2 ′ are formed, and metal is buried in the via holes by a CMP process to complete the via structures V 2 ′. Then, a metal layer made of Ti, TiN, Ta or TaN is deposited and is patterned by a photolithography and etching process, so that the lower electrode layer LE is connected to the via structures V 2 ′. 
         [0086]    Next, a dielectric layer  32  is formed by a CVD process. Then, via holes for via structures V 3 ′ are formed, and metal is buried in the via holes by a CMP process to complete the via structures V 3 ′. Then, a metal layer made of Ti, TiN, Ta or TaN is deposited and is patterned by a photolithography and etching process, so that the upper electrode layer UE is connected to the via structures V 3 ′. 
         [0087]    Next, an about 20 nm thick insulating interlayer  33  is deposited by a CVD process. Then, via holes for via structures V 4 ′ are formed, and metal is buried in the via boles by a CMP process to complete the via structures V 4 ′. 
         [0088]    Finally, grooves for upper conductive strips U 1 , U 2 , . . . are formed by a dual damascene process. Then, metal is deposited and is buried in the grooves by a CMP process to complete the upper conductive strips U 1 , U 2 , . . . , which would avoid disconnection of the upper conductive strips U 1 , U 2 , . . . . 
         [0089]    In the above-described embodiments, every three lower conductive strips alternately receive the power supply voltage V DD  and the ground voltage GND; however, every two lower conductive strips or every four lower conductive strips or more can alternately receive the power supply voltage V DD  and the ground voltage GND. Similarly, every three upper conductive strips alternately receive the power supply voltage V DD  and the ground voltage GND; however, every two upper conductive strips or every four upper conductive strips or more can alternately receive the power supply voltage V DD  and the ground voltage GND.