Abstract:
An improved charge pump used in a phase-locked loop includes transient current correction capability by adding a canceling capacitance for each parasitic capacitance associated with a switching device in a charge pump. For each transient current component flowing through the parasitic capacitance, a canceling capacitance is implemented to create a canceling transient current component in the opposite direction such that it cancels out the transient current component. Preferably, an additional switching device is added to implement such a canceling capacitance for each parasitic capacitance.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates generally to a phase-locked loop (PLL) and, more particularly, to an improved charge pump with transient current correction.  
           [0003]    2. Description of the Related Art  
           [0004]    High-performance, low-jitter phase-locked loops (PLLs) require accurate sensing and correction of the phase and frequency error between a reference clock signal and a feedback clock signal. Typically, a PLL includes a phase-frequency detector (PFD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and optionally a frequency divider. The PFD senses the aforementioned phase and frequency error and generates timing signals, which are used to generate currents in the charge pump. These currents are then integrated by a loop filter to create a control voltage, which is input to the VCO. This voltage controls the frequency of the VCO. Ideally, a plot of this control voltage as a function of a phase error should produce a linear response over the cycle and should pass through the origin of the plot. For conventional charge pumps currently used in PLLS, however, this is not the case.  
           [0005]    Conventional charge pumps have current source and sink along with switching devices used to control current flows through the current source and sink. The output signals of a PFD switch these switching devices. Typically, when the feedback clock signal leads the reference clock signal, the current sink is coupled to the loop filter so that the control voltage is decreased. When the reference clock signal leads the feedback clock signal, the current source is coupled to the loop filter so that the control voltage is increased. When the PLL is locked, nether the current source nor the current sink is coupled to the loop filter so that the control voltage does not change.  
           [0006]    The switching devices are coupled to the current source and sink in series. The devices may be positioned either at the top and bottom of the current source and sink or between the stack of the current source and sink. In such structures, the switching devices force the current in the current sources or sinks to be shut off, resulting in large biasing differences between conducting and non-conducting states. The current source and sink are typically implemented with current mirrors. The current mirrors generally comprise a plurality of transistors such as metal-oxide-silicon field effect transistors (MOSFETs). These three-terminal transistors have parasitic capacitances between a gate and the other two terminals (drain and source terminals in case of MOSFETs). These parasitic capacitances contribute additional transient currents, which distort the linearity of the control voltage as a function of a phase error when the phase error is small. For small phase errors, the initial transient current dominates the charge pump&#39;s response. In the aforementioned plot of the control voltage as a function of a phase error, therefore, a conventional charge pump would generate a higher slope region at or near the origin where the transient currents flow and a discontinuity in the response after the transient currents have died out. There is also another discontinuity at the origin of the transfer function because the transient currents are different for charge and discharge operations. These transient currents are not well controlled since they are due to the design and process of the switching devices.  
           [0007]    Therefore, there is a need for an improved charge pump that eliminates these transient currents associated with the switching devices used in the charge pump.  
         SUMMARY OF THE INVENTION  
         [0008]    The present invention provides a charge pump with transient current correction. The charge pump is coupled to a loop filter to charge and discharge the loop filter in a phase-locked loop.  
           [0009]    At least a switching device is included in the charge pump for receiving a control signal. The switching device has at least a parasitic capacitance such that a transient current component is created across the parasitic capacitance while the control signal is in a transient state. At least a canceling capacitance is also included in the charge pump and is coupled to the parasitic capacitance for receiving an inverted signal of the control signal such that a canceling transient current component is created across the canceling capacitance while the control signal in a transient state. This canceling transient current component effectively cancels out the transient current component. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:  
         [0011]    [0011]FIG. 1 is a block diagram of a phase-locked loop;  
         [0012]    [0012]FIG. 2 is a plot diagram of a two-dimensional Cartesian coordinate system depicting a plot of a control voltage of a loop filter as a function of a phase error detected by a phase-frequency detector in a phase-locked loop;  
         [0013]    [0013]FIG. 3 is a schematic diagram depicting a prior-art charge pump circuit; and  
         [0014]    [0014]FIG. 4 is a schematic diagram depicting an improved charge pump circuit with transient current correction.  
     
    
     DETAILED DESCRIPTION  
       [0015]    In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail.  
         [0016]    Referring to FIG. 1 of the drawings, the reference numeral  100  generally designates a block diagram incorporating a phase-locked loop (PLL)  102 . The PLL  102  is coupled to a reference clock generator  104  to receive a reference clock signal  106  having frequency F_REF and is configured to generate a PLL output signal  108  having frequency F_CLK. Generally, the PLL  102  uses a feedback loop  110  to lock a feedback signal  112  to the reference clock signal  106 .  
         [0017]    Specifically, the feedback loop  110  includes a phase-frequency detector  114 , a charge pump  116 , a loop filter  118 , a voltage-controlled oscillator (VCO)  120 , and optionally a frequency divider  122 .  
         [0018]    In the PLL  102 , the phase-frequency detector  114  compares the reference clock signal  106  and the feedback signal  112  and generates an error signal  124 , which is proportional to the magnitude of the phase/frequency difference between the reference clock signal  106  and the feedback signal  112 . The error signal  124  is fed to the charge pump  116 . Typically, the error signal  124  has three states: UP, DN, and OFF. UP is asserted when the reference clock signal  106  lags behind the feedback signal  112 , whereas DN is asserted when the reference clock signal  112  leads the feedback signal  112 . When the PLL  102  is locked, neither UP nor DN is asserted, which is an OFF state. The charge pump  116  controls the magnitude of charge stored in the loop filter  118  using current, thereby converting the error signal  124  into a control voltage input V c    126 , which is recognizable by the VCO  120 . For example, the loop filter  118  contains a series RC combination. The series RC combination produces a second order system. However, other types of loop filters may be used instead. The VCO  120  generates the PLL output signal  108 . Typically, the frequency F_CLK of the PLL output signal  108  is proportional to the control voltage input  126 .  
         [0019]    Optionally, the frequency divider  122  further divides down the frequency F_CLK of the PLL output signal  108  before the PLL output signal  108  is fed back to the phase-frequency detector  122 . Provided that the frequency divider  122  is used in the PLL  102 , the frequency of the PLL output signal  108  is higher than that of the feedback signal  112  by a factor of the frequency divider  122 . For example, if the frequency divider  122  with a factor of N is used, the frequency of the PLL output signal  108  is approximately N times that of the feedback signal  112 . Therefore, F_CLK=N*F_REF, wherein N is a positive integer. This is because the PLL  102  locks the frequency of the feedback signal  112  to the frequency F_REF of the reference clock signal  106  in the feedback loop  110 .  
         [0020]    Now referring to FIG. 2, a plot diagram  200  of a two-dimensional Cartesian coordinate system is shown to depict a plot of a control voltage of a loop filter as a function of a phase error detected by a phase-frequency detector in a phase-locked loop. The plot diagram  200  has the phase error and the control voltage as an x (horizontal) axis  202  and y (vertical) axis  204 , respectively. Ideally, the plot diagram  200  should produce a linear response as shown in a dashed line  206  and should pass through the origin  208 . As shown in a solid line  210 , a conventional charge pump would generate a higher slope region  212  at or near the origin  208 , where the transient currents flow, and discontinuities around points A and B in the response after the transient currents have died out. There is also another discontinuity at the origin of the transfer function because the transient currents are different for charge and discharge operations. In the plot diagram  200 , it is assumed for simplicity that the transient currents exist, wherein the phase error is within the region  212 , and do not exist at all, wherein the phase error is outside the region  212 .  
         [0021]    In FIG. 3, a schematic diagram of a prior-art charge pump circuit  300  is shown. The prior-art charge pump circuit  300  comprises a source current mirror  302 , a sink current mirror  304 , and switching devices Q 1  and Q 5 . Switching device Q 1  is coupled between the source current mirror  302  and a capacitor C. Similarly, switching device Q 5  is coupled between the sink current mirror  304  and the capacitor C. Switching device Q 1  has parasitic capacitances C 1   s  and C 1   d . Similarly, switching device Q 5  has parasitic capacitances C 5   s  and C 5   d . Note that switching devices Q 1  and Q 5  are controlled by UPB and DN, respectively. UPB is an inverted signal of UP signal. As mentioned above in reference to FIG. 1, UP and DN signals are generated by the phase-frequency detector  114 .  
         [0022]    Preferably, the source current mirror  302  comprises a reference current source  306  coupled to biasing device Qa, which is coupled to biasing device Qb. The reference current source  306  is configured for flow reference current Iref. Note that biasing device Qa has its two terminals (e.g., gate and drain terminals in case that switching device Qa is a p-channel MOSFET) coupled together at node A. Since the control terminal of the biasing device Qb is also coupled to node A, the potential of the control terminals of biasing devices Qa and Qb are equal. This along with other bias conditions allows switching device Qb to flow reference current Iref through switching device Qb when switching device Q 1  is turned on.  
         [0023]    Similarly, the sink current mirror  304  comprises a reference current source  308  coupled to biasing device Qd, which is coupled to biasing device Qe. The reference current source  308  is configured for flow reference current Iref. Note that biasing device Qd has its two terminals (e.g., gate and drain terminals in case that switching device Qd is a n-channel MOSFET) coupled together at node B. Since the control terminal of the biasing device Qe is also coupled to node B, the potential of the control terminals of biasing devices Qd and Qe are equal. This along with other bias conditions allows switching device Qe to flow reference current Iref through switching device Qe when switching device Q 5  is turned on.  
         [0024]    Node X will rise to the level of Vdd when UPB is high (i.e., UP is not asserted). When UPB is low (i.e., UP is asserted), the initial current in device Q 1  is usually much larger than the desired current Iref supplied through Qb, because the voltage drop (Vsg) between node X and the control terminal of Q 1  approximately equals Vdd. Parasitic capacitances C 1   s , C 1   d , C 5   s , and C 5   d  contribute additional transient currents to currents I 1  an Ic. Similarly, assertions on DN create current transients by the same mechanisms as UPB, but of different magnitude due to difference in device characteristics and parasitics between switching devices Q 1  and Q 5 . Preferably, devices Qa, Qb, and Q 1  are PMOS transistors, whereas devices Qd, Qe, and Q 5  are NMOS transistors.  
         [0025]    [0025]FIG. 4 is a schematic diagram depicting an improved charge pump circuit  400  with transient current correction. The improved charge pump circuit  400  includes the prior-art charge pump circuit  300  and a transient current correction circuit  402  interconnected to the prior-art charge pump circuit  300 .  
         [0026]    The transient current correction circuit  402  comprises devices Qc, Qf, Q 2 , Q 3 , Q 4 , Q 6 , Q 7 , and Q 8 . Devices Qb and Qc are identical and are matched to Qa. Similarly, devices Qe and Qf are identical and are matched to Qd. Signals UP and UPB are complementary as are signals DN/DNB. These complementary signal pairs are matched such that they switch simultaneously but UPB and DN are never asserted simultaneously. As UPB transitions from low to high (or high to low) and UP switches simultaneously from high to low (low to high), parasitic transient currents IC 1   s , IC 1   d , and IC 4   s  will flow. If devices Q 1 , Q 2 , and Q 4  are identical in size (e.g., W and L), type, and orientation, etc. and are in close proximity, then IC 1   s =−IC 4   s , and IC 1   d =IC 2   d , effectively canceling each other since UP and UPB switch in opposite directions simultaneously. Devices Q 4 , Q 8 , and Qf form a complementary current path to the path formed by Q 1 , Q 5 , and Qe. Since current Iref produced by current source Qb will flow regardless of the state of UP/UPB, node X will remain constant, removing the greatest source of unwanted transient current from I 1 .  
         [0027]    Similarly, if devices Q 5 , Q 6 , and Q 7  are identical in size (e.g., W and L), type, and orientation, etc. and are in close proximity, then IC 5   d =−IC 6   d , and IC 5   s =−IC 7   s , effectively canceling each other since DN and DNB switch in opposite directions simultaneously. Devices Q 3  and Q 8  allow more even match between the complementary paths and the main current paths, which charge and discharge capacitor C, and are identical to Q 1  and Q 5 , respectively.  
         [0028]    Preferably, devices Qa, Qb, Qc, Q 1 , Q 2 , Q 3 , and Q 4  are PMOS transistors, whereas devices Q 5 , Q 6 , Q 7 , Q 8 , Qd, Qe, and Qf are NMOS transistors. However, different types of transistors may be used instead without departing from the true spirit of the present invention.  
         [0029]    It will be understood from the foregoing description that various modifications and changes may be made in the preferred embodiment of the present invention without departing from its true spirit. This description is intended for purposes of illustration only and should not be construed in a limiting sense. The scope of this invention should be limited only by the language of the following claims.