Abstract:
A system for minimizing power consumption of a multiprocessor data storage system is disclosed. The system utilizes processors that are capable of operating at a number of different reduced power modes, such that the processors operate at full power during peak workloads, but can be powered down during low workload times. When the onset of peak loads are detected through monitoring I/Os per second (“IOPS”) and/or response times of the system, the processors are brought out of power-down mode to handle the increased IOPS during the peak loads. In this manner, the majority of the processors only operate at full power when the system experiences peak loads. During normal and low load times, the processors are either operated at reduced power or are powered down. This results in a significant reduction in power consumption of the system.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to a method and system for minimizing power consumption in a multiprocessor data storage system and, more particularly, to a method and system for monitoring a performance indicator of the data storage system and powering up/down processors to process inputs and outputs of the system based on the performance of the system. 
     BACKGROUND OF THE INVENTION 
     As is known in the art, large host computers and servers (collectively referred to herein as “host computer/servers”) require large capacity data storage systems. These large computer/servers generally include data processors, which perform many operations on data introduced to the host computer/server through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system. 
     One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the host computer/server are coupled together through an interface. The interface includes “front end” or host computer/server controllers (or directors) and “back-end” or disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the host computer/server. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the host computer/server merely thinks it is operating with its own local disk drive. One such system is described in U.S. Pat. No. 7,124,245, (“the &#39;245 patent”) entitled “Data Storage System Having Cache Memory Manager with Packet Switching Network”, inventors Walton et al., issued Oct. 17, 2006, and assigned to the same assignee as the present invention, which patent is incorporated herein by reference in its entirety. 
     In such a system, each microprocessor  329  in each of the front end directors  350  is always at full power, in one example at 80 W, in order to enable the system to provide desired storage response times to satisfy unplanned peak workloads. The processor architecture is designed to enable the system to be able to handle peak loads at all times so that response times consistently meet application requirements. However, during low workload times, the processors remain operating at full power, resulting in unnecessary power consumption. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a method and system for minimizing power consumption of a multiprocessor data storage system. The invention utilizes processors that are capable of operating at a number of different reduced power modes, such that the processors operate at full power during peak workloads, but can be powered down during low workload times. The system includes one processor that is preferably a low-power processor, although a high-power processor may be utilized, that is always in operation to service inputs and outputs (“I/Os”) through the directors, while other high power processors remain in a power-down mode. When the onset of peak loads are detected through monitoring I/Os per second (“IOPS”) and/or response times of the system, the high power processors are brought out of power-down mode to handle the increased IOPS during the peak loads. In this manner, the majority of the high-power processors only operate at full power when the system experiences peak loads. During normal and low load times, the processors are either operated at reduced power or are powered down. This results in a significant reduction in power consumption of the system. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features of the invention will become more readily apparent from the following detailed description when read together with the accompanying drawings, in which: 
         FIG. 1  is a schematic block diagram showing the system for minimizing power consumption of a multiprocessor data storage system in accordance with the present invention; 
         FIG. 2  is a schematic block diagram showing another embodiment of the system for minimizing power consumption of a multiprocessor data storage system in accordance with the present invention; 
         FIG. 3  is a schematic block diagram showing yet another embodiment of the system for minimizing power consumption of a multiprocessor data storage system in accordance with the present invention; 
         FIG. 4  is a flow diagram showing the steps involved in the method of minimizing power consumption of a multiprocessor data storage system in accordance with the present invention; and 
         FIG. 5  is a graph showing how changes in the amount of I/Os cause the system to switch the processors between operating power modes in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a schematic block diagram of an embodiment of a system  10  for minimizing power consumption of a multiprocessor data storage system. The system  10  includes a host  12  and a bank of disk drives  14 . As described in the &#39;245 patent, host  12  sends commands and data to and receives data from disk drives  14 . System  10  further includes an interface  18 , which corresponds to the network section and backend directors described in the &#39;245 patent. Front end directors  16   0 ,  16   1 , and  16   2  includes processors P 0 , P 1 , and P 2 , respectively, and operate to process data transfers between the host  12  and the disk drives  14 , as described in the &#39;245 patent. System  10  further includes a controller  20 , which operates to transfer data transfers between the host  12  and the front end directors  16   0 ,  16   1 , and  16   2 . 
     In operation, data transfers, or I/Os are transferred between the host  12  and the disk drives  14  through controller  20 . Controller  20  monitors the IOPS and determines at what power level the processors P 0 , P 1 , and P 2  need to operate to handle the current workload of the system  10 . In system  10 , processor P 0  is always at full power to process I/Os. Processor P 0  may be a low-power processor, for further reducing power consumption when the load on the system is low. Alternatively, processor P 0  may be a high-power, 80 W processor. Processors P 1  and P 2  are processor that are capable of operating at different power level modes. An example of one such processor is the 5100 Series of the Intel Xeon processor available from Intel Corporation of Santa Clara, Calif. Such processors are capable of operating at one of four different power levels: full power (C 1  mode—80 W), powered-down (C 4  mode—1.8 W), and modes C 3  and C 2 , which are between modes C 4  and C 1 . For example, mode C 3  could be 25 W and C 2  mode could be 50 W. As is known in the art, the higher the operating voltage level, the higher the frequency at which the processor operates to process I/O. Levels C 2  and C 3  may be chosen to provide a balance of power consumption and processing ability of the processors. 
     As stated above, while processor P 0  is processing I/Os, controller  20  monitors trends in the IOPS. When IOPS are at a low level, relative to the processing capacity of processor P 0 , only processor P 0  operates at full power. When the IOPS increase such that processor P 0  is operating at, for example 80% of its capacity, controller  20  instructs processor P 1  to switch from C 4  mode to C 3  mode, in anticipation of the capacity of processor P 0  reaching its maximum. Once processor P 1  is powered up to mode C 3 , controller  20  begins directing I/Os to processor P 1  for processing. As the IOPS increase, controller  20  will increase the number of I/Os to processor P 1  for processing. Controller  20  can instruct processor P 1  to power up to mode C 2  and then C 1  based on the IOPS or, alternatively, as the demand on processor P 1  increases, processor P 1  can switch itself to higher power modes to handle the increase. Likewise, when the IOPS begin to decrease, controller  20  can instruct processor P 1  to power down to lower power modes or, processor P 1  can incrementally reduce its own power when detecting the decreased load. In this manner, processor P 1  is only powered up when necessary to handle the load on the system and, even when it is powered up, it is only powered at a level that is necessary for handling the level of IOPS and for maintaining the optimal response times of the system. 
     An alternative embodiment is shown at  50  in  FIG. 2 . Similar to system  10  of  FIG. 1 , system  50  includes a host  12  and a bank of disk drives  14 . As described in the &#39;245 patent, host  12  sends commands and data to and receives data from disk drives  14 . System  10  further includes an interface  18 , which corresponds to the network section and backend directors described in the &#39;245 patent. 
     Front end directors  56   0 ,  56   1 , and  56   2  include processors P 0 , P 1 , and P 2 , respectively, and operate to process data transfers between the host  12  and the disk drives  14 , as described in the &#39;245 patent. However, in this embodiment, processor P 0  performs the operation of controller  20  of system  10 . Accordingly, processor P 0  monitors the IOPS and determines at what power level the processors P 0 , P 1 , and P 2  need to operate to handle the current workload of the system  10 . Similar to system  10 , in system  50 , processor P 0  is always at full power to process I/Os. Processor P 0  may be a low-power processor, for further reducing power consumption when the load on the system is low. Alternatively, processor P 0  may be a high-power, 80 W processor. 
     In operation, while processor P 0  is processing I/Os, it also monitors trends in the IOPS. When IOPS are at a low level, relative to the processing capacity of processor P 0 , only processor P 0  operates at full power. When the IOPS increase such that processor P 0  is operating at, for example 80% of its capacity, it instructs processor P 1  to switch from C 4  mode to C 3  mode, in anticipation of the capacity of processor P 0  reaching its maximum. Once processor P 1  is powered up to mode C 3 , host  12  detects that processor P 1  is powered up and begins directing I/Os to processor P 1  for processing. As the IOPS increase, processor P 0  instructs processor P 1  to power up to mode C 2  and then C 1  based on the IOPS or, alternatively, as the demand on processor P 1  increases, processor P 1  can switch itself to higher power modes to handle the increase. Likewise, when the IOPS begin to decrease, processor P 0  can instruct processor P 1  to power down to lower power modes or, Processor P 1  can incrementally reduce its own power when detecting the decreased load. In this manner, processor P 1  is only powered up when necessary to handle the load on the system and, even when it is powered up, it is only powered at a level that is necessary for handling the level of IOPS and for maintaining the optimal response times of the system. 
     Another alternative embodiment is shown at  60  in  FIG. 3 . Similar to system  50  of  FIG. 2 , system  60  includes a host  12  and a bank of disk drives  14 . As described in the &#39;245 patent, host  12  sends commands and data to and receives data from disk drives  14 . System  60  further includes an interface  18 , which corresponds to the network section and backend directors described in the &#39;245 patent. 
     In  FIG. 3 , processors P 0 , P 1  and P 2  are all disposed on a single front end director  60  and I/Os are input to the director  62  through a common I/O port from the host  12  and a common I/O port from the interface  18 . The operation of system  60  is essentially the same as the operation of system  50 , in that processor P 0  monitors the IOPS and determines at what power level the processors P 0 , P 1 , and P 2  need to operate to handle the current workload of the system  60 . Similar to system  50 , in system  60 , processor P 0  is always at full power to process I/Os. Processor P 0  may be a low-power processor, for further reducing power consumption when the load on the system is low. Alternatively, processor P 0  may be a high-power, 80 W processor. 
     In operation, while processor P 0  is processing I/Os, it also monitors trends in the IOPS. When IOPS are at a low level, relative to the processing capacity of processor P 0 , only processor P 0  operates at full power. When the IOPS increase such that processor P 0  is operating at, for example 80% of its capacity, it instructs processor P 1  to switch from C 4  mode to C 3  mode, in anticipation of the capacity of processor P 0  reaching its maximum. Once processor P 1  is powered up to mode C 3 , host  12  detects that processor P 1  is powered up and begins directing I/Os to processor P 1  for processing. As the IOPS increase, processor P 0  instructs processor P 1  to power up to mode C 2  and then C 1  based on the IOPS or, alternatively, as the demand on processor P 1  increases, processor P 1  can switch itself to higher power modes to handle the increase. Likewise, when the IOPS begin to decrease, processor P 0  can instruct processor P 1  to power down to lower power modes or, Processor P 1  can incrementally reduce its own power when detecting the decreased load. In this manner, processor P 1  is only powered up when necessary to handle the load on the system and, even when it is powered up, it is only powered at a level that is necessary for handling the level of IOPS and for maintaining the optimal response times of the system. 
       FIG. 4  is a flow diagram  100  showing the steps involved in the method of minimizing power consumption in a multiprocessor data storage system. In Step  102 , when the system is booted up, processor P 0  begins processing I/Os, while processor P 1  is in mode C 4 . During this time, and throughout the operation of the system, a performance indicator, PI, such as IOPS, for example, is monitored, Step  104 . It will be understood that other performance indicators, such as response time or operating bandwidth of the system may be monitored during the operation of the system. The monitoring of Step  104  may be performed by controller  20  in the case of system  10 , or by processor P 0 , in the case of system  50 . If PI is determined to be below a first predetermined value PV 1 , Step  106 , meaning that processor P 0  is capable of handling the rate of IOPS, the system returns to Step  102  and processor P 0  continues to process I/Os. 
     If, in Step  106 , the performance indicator is determined to be greater than PV 1 , processor P 1  is powered up to mode C 3 , Step  108 . In system  10 , controller  20  instructs processor P 1  to power up to mode C 3  and in system  50 , processor P 0  provides the instruction. 
     I/Os are then processed with processor P 0  and processor P 1  in C 3  mode, Step  110 . The performance indicator continues to be monitored, Step  112  and if it is below a predetermined value 2, PV 2 , Step  114 , and if PI is greater than PV 1 , the system continues to process I/Os with processor P 0  and processor P 1  in C 3  mode, Step  110 . If PI is determined to be less than PV 1 , Step  116 , processor P 1  is powered down to mode C 4 , Step  118 , and the system returns to Step  102  and processor P 0  continues to process I/Os. As discussed above, the instruction to power down processor P 1  can come from controller  20  in system  10  and from processor P 0  in system  50 . Alternatively, processor P 1  can incrementally reduce its own power when detecting the decreased load. 
     If, in Step  114 , it is determined that PI is greater than PV 2 , processor P 1  is powered to mode C 2 , Step  120 . Again, in system  10 , controller  20  instructs processor P 1  to power up to mode C 2  and in system  50 , processor P 0  provides the instruction. Alternatively, as the demand on processor P 1  increases, processor P 1  can switch itself to higher power modes to handle the increase. I/Os are then processed with processor P 0  and processor P 1  in C 2  mode, Step  122 . The performance indicator PI continues to be monitored, Step  124 , to determine if it is below a predetermined value 3, PV 3 , Step  126 . If it is, the system returns to Step  114  to determine if processor P 1  will continue to process I/Os in C 2  mode. If PI is determined to be greater than PV 3  in Step  126 , processor P 1  is powered up to mode C 1 , Step  128 . I/Os are then processed with processor P 0  and processor P 1  in C 1  mode, Step  130 . The performance indicator PI continues to be monitored, Step  132 , to determine if it is below a predetermined value 3, PV 3 , Step  126 . If it is, the system returns to Step  114  to determine if processor P 1  will continue to process I/Os in C 2  mode. This process continues during the operation of the respective systems  10  and  50 . Although not specifically shown, processor P 2  may be powered up in a similar fashion as processor P 1 , when processor P 1  is operating in the C 1  mode and the IOPS, for example, continue to increase beyond the capacity of P 0  and P 1  operating at C 1 . 
       FIG. 5  is a graph showing how changes in the amount of I/Os cause the system to switch the processors between operating power modes. The graphs shows the number of I/Os processed by the system over time (IOPS). During period A, between times t 1  and t 2 , when IOPS are relatively low, the system operates with processor P 0  and processor P 1  in C 4  mode. During period B, between times t 2  and t 3 , when the IOPS increase beyond, for example, 80% of the capacity of processor P 0 , processor P 1  is powered up to mode C 3  and the system operates with processor P 0  and processor P 1  in C 3  mode. After time t 3 , during period C, when the IOPS have increased further, processor P 1  is powered up to mode C 2  and the system operates with processor P 0  and processor P 1  in C 2  mode. 
     After time t 4 , the IOPS begin to decrease. Therefore, during period D, processor P 1  is powered down to mode C 3  and the system operates with processor P 0  and processor P 1  in C 3  mode. During period E, the system operates with processor P 0  and processor P 1  in C 4  mode. Between times t 6  and t 8 , as the IOPS increase, processor P 1  is powered up first to mode C 3  and then to mode C 2 . During period H, after the IOPS have increased further, processor P 1  is powered up to mode C 1  and the system operates with processor P 0  and processor P 1  in C 1  mode. 
     Accordingly, the system enables a data storage system to minimize its power consumption by only powering up processors to a level that is necessary for processing the loads that the system is experiencing. 
     The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For example, although the invention has been described in connection with a data storage system, it will be understood that the invention may be utilized in any multiprocessor system that processes I/Os. The present embodiments are therefore to be considered in respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of the equivalency of the claims are therefore intended to be embraced therein.