Abstract:
Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes complementary data-input transistors to expedite the data combiner&#39;s response to changes in input data.

Description:
BACKGROUND 
     Modern digital systems represent digital data either in series (i.e., as a series of bits) or in parallel (i.e., as a transmitting one or more bytes simultaneously using multiple data lines). While it is generally easier to store and manipulate data in parallel, it is often beneficial to transmit data in series. Many systems therefore employ parallel-to-serial converters. 
     FIG. 1 (prior art) depicts a parallel-to-serial converter  100  that serializes ten-bit words presented in parallel on data lines D&lt;9:0&gt;. Converter  100  includes a parallel shifter  105 , which in turn includes a pair of five-bit shift registers  110  and  115 . Each shift register  110  and  115  connects to one of a pair of complementary clocks C EV  and C OD . Designations C EV  and C OD  stand for “clock even” and “clock odd,” respectively, because even data bits are presented on an output terminal D OUT  when C EV  is high and odd data bits are presented on output terminal D OUT  when C OD  is high. 
     Every fifth rising edge of clock C EV , register  110  stores the even-numbered data bits D&lt;8,6,4,2,0&gt; presented on bus D&lt;9:0&gt; and register  115  stores the odd-numbered data bits D&lt;9,7,5,3,1&gt; presented on the same bus. Each of registers  110  and  115  then present their respective data one bit at a time, so that both odd and even data bits are presented alternately to a data combiner  120 . Data combiner  120  alternately gates the odd and even data bits presented on respective data terminals D OD  and D EV  to produce a serialized version of the data produced by shifter  105 . 
     If manufactured using commonly available CMOS processes, converter  100  can perform with clock frequencies as high as about 2 GHz. Unfortunately, modern high-speed digital communication systems transmit serial data in the 10 Gb/s range. The frequency response of converter  100  is insufficient to meet the needs of some modern systems. More exotic processes, such as those employing silicon germanium or gallium arsenide, provide improved high-frequency response; unfortunately, this improvement comes at considerable expense. 
     SUMMARY 
     The present invention is directed top parallel-to-serial converters capable of operating at speed sufficient to meet the needs of modern communication systems without consuming excessive power or requiring complex and expensive fabrication technologies. Converters in accordance with the invention include data combiners employing current sources and differential current-steering circuits. The current-steering circuits respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment of the invention includes complementary data-input transistors to expedite the data combiner&#39;s response to changes in input data. 
     This summary does not define the scope of the invention, which is instead defined by the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     FIG. 1 (prior art) depicts a parallel-to-serial converter  100  that serializes ten-bit words presented in parallel on data lines D&lt;9:0 &gt;. 
     FIG. 2A depicts a data combiner  200  in accordance with one embodiment of the invention. 
     FIG. 2B is a timing diagram  250  depicting the operation of current-steering circuit  205  of FIG.  2 A. 
     FIG. 3 depicts a parallel-to-serial converter  300  in accordance with another embodiment of the invention. 
     FIG. 4A details an embodiment of data combiner  315 . 
     FIG. 4B is a waveform diagram  430  depicting the operation of current-steering circuit  400  of FIG.  4 A. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2A depicts a data combiner  200  in accordance with one embodiment of the invention. Data combiner  200  serializes two-bit data bytes at a rate far greater than can be achieved using data combiner  120  of FIG.  1 . Data combiner  200  includes a pair of current-steering circuits  205  and  210 , each of which receives a pair of complementary clock signals C OD  and C EV . Steering circuit  205  steers current from a current source  215  to an output terminal OUTb and from output terminal OUTb to ground in response to even and odd data signals D EV  and D OD . The steered current represents a serialized version of data signals D EV  and D OD ; similarly, steering circuit  210  receives the complements Db EV  and Db OD  of respective even and odd data signals D EV  and D OD  to produce a serialized version of these data signals on an output terminal OUT. The serialized data signals on lines OUT and OUTb are complementary; signal designations terminating in a lower-case “b” identify active-low signals. 
     Steering circuit  205  includes a pair of differential NMOS input transistors  220  and  225  having their respective control terminals (gates) tied to data terminals D EV  and D OD . Steering circuit  205  also includes a pair of differential NMOS input transistors  230  and  235  having their respective control terminals tied to respective complementary clock terminals C EV  and C OD . Finally, circuit  205  includes a pair of PMOS transistors  240  and  245  having their respective control terminals connected to respective data terminals D EV  and D OD . Complementary transistors  220  and  240  form an inverter that connects between input terminal D EV  and output terminal OUTb via transistor  230 . Steering circuits  205  and  210  are identical, so a detailed discussion of steering circuit  210  is omitted for brevity. 
     FIG. 2B is a timing diagram  250  depicting the operation of current-steering circuit  205  of FIG.  2 A. Diagram  250  assumes two arbitrary even and odd data streams, received in parallel, to be serialized by data combiner  200 . Each signal is identified using the node designation for the corresponding terminal. Whether a given designation refers to a node or a signal will be clear from the context. 
     Beginning at time T 0 , the odd and even data signals D EV , and D OD  are both logic zeroes. Transistors  220  and  225  are therefore biased off and transistors  240  and  245  biased on, so that terminals X 1  and X 2  both approach power-supply voltage VDD. Clocks C EV  and C OD  are high and low, respectively (clock Cis the complement of C EV ); consequently, transistor  230  is on and transistor  235  is off. Transistor  220  is off, so current-steering circuit  200  steers the current from current source  215  out through terminal OUTb. Since signal OUTb is active low, terminal OUTb expresses a positive (outgoing) current at time T 0  to express a logic zero. The logic zero “even” data on terminal D EV  is therefore expressed on output terminal OUTb between times T 0  and T 1 . 
     At time T 1 , the odd and even data signals D EV  and D OD  are still both logic zero, but clock signals C EV  and C OD  reverse. Transistor  235  is therefore biased on and the odd data signal D OD  selected to determine the logic level on output terminal OUTb. In this case, the output signal OUTb does not change; however, during this period the “odd” data on terminal D OD  is responsible for the logic zero expressed on output terminal OUTb. 
     Even data signal D EV  transitions to a logic one some time between T 1  and T 2 . Transistor  220  responds, pulling terminal X 1  toward ground potential. Then, at time T 2 , clock signal C EV  turns on transistor  230  so transistors  230  and  220  steer the current from source  215  to ground and away from output terminal OUTb. Data combiner  200  thus expresses a logic one output signal (recall that OUTb is active low, so a logic one is expressed using a “negative” current on that terminal). 
     Skipping ahead, the odd data signal D OD  changes from a logic one to a logic zero between times T 4  and T 5 . In the absence of transistor  245 , terminal X 2  would not respond to the change on terminal D OD  until transistor  235  turns on again at time T 5 . Current from current source  215  would then be steered to terminal X 2 , delaying the state change on output terminal OUTb until after time T 5 . Such a delay would undesirably slow the operation of data combiner  200 . The inclusion of transistor  245  expedites the transition on terminal X 2  by connecting terminal X 2  to VDD as soon the data DOD transitions, thus pre-charging terminal x 2  a time t before time T 5 . When transistor  235  turns on, current source  215  does not waste valuable time charging node X 2 , so output terminal OUTb transitions more rapidly. Transistor  240  provides the same advantage as transistor  245  for data on terminal D EV . 
     Output signals OUT and OUTb are depicted as voltage fluctuations for clarity; however, the logic levels between output terminals OUT and OUTb are primarily expressed using differential currents. The preferred embodiments of the invention use current steering and differential signaling to improve noise immunity and to reduce the voltage swing required to express logic levels. These improvements deliver devices capable of higher data transmission speeds, greater bandwidth, and lower power consumption. 
     Current-steering circuit  210  functions identically to circuit  205  using complementary data signals. The resulting output signal on terminal OUT is therefore complementary to the signal on terminal OUTb. 
     FIG. 3 depicts a parallel-to-serial converter  300  in accordance with another embodiment of the invention. Converter  200  of FIG. 2 serializes two-bit data; converter  300  of FIG. 3 illustrates how the invention can be extended to serialize data represented using more than 2 bits. 
     Converter  300  includes a conventional 8phase-locked loop (PLL)  305  that produces, from a clock signal CLK, eight phase-delayed clocks signals C&lt;7:0&gt;. In one embodiment, the phase difference between clock signals C&lt;7:0&gt; is about 100 picoseconds. Converter  300  also includes a conventional shifter  310  that uses eight shift registers (not shown) and the eight phase-delayed clocks signals C&lt;7:0&gt; to convert each of a series of 64-bit data words on a bus D&lt;63:0&gt; into a series of eight eight-bit data words on a bus D&lt;7:0&gt;. Finally, converter  300  includes a data combiner  315  adapted in accordance with the invention to serialize the eight-bit data on lines D&lt;7:0&gt; using the clock signals on lines C&lt;7:0&gt;. Combiner  315  presents the serialized data as a pair of differential output signals TX and TXb on like-named output terminals. Terminal TX_VCM is the common-mode voltage terminal between the TX and TXb output terminals, and is produced, for example, between a pair of 50-ohm resistors. The common-mode voltage on terminal TX_VCM can be used in a conventional feedback configuration to set the common mode. 
     Converter  300  illustrates an example that serializes eight-bit data, but the invention can be extended to more or fewer bits. 
     FIG. 4A details an embodiment of data combiner  315 . Data combiner  315  includes a pair of complementary current-steering circuits  400  and  405  that provide respective complementary serialized signals TX and TXb. Circuits  400  and  405  are identical except that they receive complementary data signals to produce their respective complementary output signals. A detailed description of combiner  405  is therefore omitted for brevity. 
     Current-steering circuit  400  includes PMOS switch network  410  connected between a first current source  415  and output terminal TX and an NMOS switch network  420  connected between a second current source  425  and output terminal TX. Current steering circuit  400  expresses logic ones by directing current from current source  415  through switch network  410  to output terminal TX, and expresses logic zeroes by sinking current from terminal TX through switch network  420  and current source  425 . 
     FIG. 4B is a waveform diagram  430  depicting the operation of current-steering circuit  400  of FIG.  4 A. Diagram  430  shows clock signal CLK, the eight phase-shifted signals C&lt;7:0&gt;, and a graphical representation of output signal TX. Complementary clock signals Cb&lt;7:0&gt; and complementary output signal TXb are omitted from FIG.  4 A. 
     From time T 0  to time T 1 , clock signals C 0  and C 5  are both high and their complementary counterparts Cb 0  and Cb 5  are low. The relative phases of clocks C&lt;7:0&gt; (and their complements) are such that in switch network  410  only the four transistors in the far-right column connected to clock terminals C 0 , C 5 , Cb 0 , and Cb 5  are biased on. The two transistors in the same far-right column with their control terminals connected to data terminal Db 0  therefore determine the logic level expressed on output terminal TX: if complementary data signal Db 0  is a logic zero, the PMOS transistor with its gate connected to terminal Db 0  turns on to complete the path for current between current source  415  and output terminal TX; if data signal Db 0  is a logic one, the NMOS transistor with its gate connected to terminal Db 0  turns on to complete the path for current between output terminal TX and current source  425 . Thus, of the eight data signals Db&lt;7:0&gt; presented to steering circuit  400 , the output signal TX is determined solely by the level on data terminal Db 0  from time T 0  to T 1 . This aspect of circuit  400  is depicted in diagram  430  as the “Db 0 ” associated with signal TX, which is to say that output TX reflects that data bit at Db 0  from time T 0  to time T 1 . 
     Clock signals C&lt;7:0&gt; combine to form eight unique combinations of clock signals, one combination for each presentation of data D&lt;7:0&gt;. Steering circuit decodes each of the combinations of clock signals to present the eight data bits in series on output terminal TX before a subsequent sequence of eight bits is presented on data terminals D&lt;7:0&gt;. 
     The second steering circuit  405  is identical to steering circuit  400 , except that steering circuit  405  receives data signals D&lt;7:0&gt;, the complement of the data signals Db&lt;7:0&gt; presented to steering circuit  400 . Thus configured, steering circuit  405  produces an output signal TXb that is the complement of output signal TX. Thus, when steering circuit  400  provides current from current source  415  to output terminal TX, steering circuit  405  will simultaneously sink current from output terminal TXb through a current source in steering circuit  405  identical to current source  425 ; similarly, when steering circuit  400  sinks current from output terminal TX via current source  425 , steering circuit  405  will simultaneously provide current to output terminal TXb via a current source in steering circuit  405  identical to current source  415 . 
     While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example, while the above-embodiments serialize two- and eight-bit data presented in parallel, the present invention can be extended to serialize parallel data represented using different numbers of bits. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance, the method of interconnection establishes some desired electrical communication between two or more circuit nodes, or terminals. Such communication may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description.