Abstract:
An exemplary method and apparatus are provided for a remapping of Optical Data Units of fixed size into lower order Optical Data Units of flexible size. More particularly, a transport signal which has a frame structure referred to as Optical Transport Units may be transmitted through an Optical Transport Network domain. Each Optical Transport Unit contains at least one Optical Data Unit of fixed size with an overhead section and a payload section. An edge network node of the Optical Transport Network domain receives the transport signal and remaps the at least one Optical Data Unit of fixed size into a domain-internal lower order Optical Data Unit of flexible size. Within the Optical Transport Network domain, the remapped domain-internal lower order Optical Data Unit of flexible size is transmitted as payload of a domain-internal higher order Optical Data Unit of fixed size.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of telecommunications and more particularly to a method and related apparatus for transmitting optical signals in an Optical Transport Network. 
       BACKGROUND OF THE INVENTION 
       [0002]    The ITU has defined in ITU-T G.709 the signals format and interfaces of the Optical Transport Network (OTN). The basic frame structure is an Optical Transport Module of size k (OTUk), where k can be 1, 2, 2e, 3, 3e2, or 4. It contains framing and section overhead plus a bit-synchronously mapped transport entity termed Optical Data Unit of size k (ODUk). An ODUk contains a payload area plus ODUk overhead. An Optical Payload Unit (OPUk) is mapped into the payload area and carries a client signal or other lower order ODUs being time-division multiplexed. OTUk signals are asynchronous within certain specified limits of typically ±20 ppm. 
         [0003]    In an Optical Transport Network, connections are switched on ODU level. The ODU is thus the switchable transport entity that travels along a network path. There exists a variety of different client signals mappings and different combinations of lower order ODUj are possible, where k can be any of 0, 1, 2, 2e, 3, or flex. An ODUflex for instance has a rate, which is a multiple of −1.24 Gbit/s. 
         [0004]    To create an OTU frame, a client signal rate is first adapted at the OPU layer and the client signal rate adjusted to the OPU rate. The OPU overhead contains information to support the adaptation of the client signal. The adapted OPU is then mapped into the ODU. The ODU overhead contains overhead bytes that allow end-to-end supervision and tandem connection monitoring. Finally, the ODU is mapped into an OTU, which provides framing as well as section monitoring and forward error correction (FEC). 
       SUMMARY OF THE INVENTION 
       [0005]    The multiplexing structure of the OTN according to ITU-T G.709 was defined over a long time. Due to addition of new client types, such as GbE and 10 GbE, the multiplexing structure became more and more complex over time. In addition, some more mappings and interface types were defined in a non-normative way, which are contained in ITU-T G.sup43. The resulting multiplexing structure is complex and thus complex to implement and manage in a network element. 
         [0006]    According to the present embodiments, a simplification through remapping of ODUs into ODUflex is described below. 
         [0007]    In particular, a transport signal which has a frame structure referred to as Optical Transport Units will be transmitted through an Optical Transport Network domain. Each Optical Transport Unit contains at least one Optical Data Unit of fixed size with an overhead section and a payload section. A edge network node of the Optical Transport Network domain receives the transport signal and remaps the at least one Optical Data Unit of fixed size into a domain-internal lower order Optical Data Unit of flexible size, which size is configurable in granularity of predefined tributary slots of a higher order Optical Data Unit of fixed size. Within the Optical Transport Network domain, the remapped domain-internal lower order Optical Data Unit of flexible size is transmitted as payload of a domain-internal higher order Optical Data Unit of fixed size. 
         [0008]    At the far end edge network node where the domain-internal lower order Optical Data Unit of flexible size is received as payload of a domain-internal higher order Optical Data Unit of fixed size, the domain-internal lower order Optical Data Unit of flexible size is de-mapped back into a recovered Optical Data Unit of fixed size. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    Preferred embodiments of the present invention will now be described with reference to the accompanying drawings in which 
           [0010]      FIG. 1  shows the multiplexing structure according to G.709; 
           [0011]      FIG. 2  shows a multiplexing structure with ODUk remapping using ODUflex as unitary lower order ODU; 
           [0012]      FIG. 3  shows a network with simplified ODUflex switching and ODUk remapping at boarder nodes; 
           [0013]      FIG. 4  shows a diagram representing the functional model of ODUk/ODUflex remapping; and 
           [0014]      FIG. 5  an interface for ODUk/ODUflex remapping. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]      FIG. 1  shows an overview of the multiplexing structure currently used in G.709 networks. Different mappings are defined for different client signals  11  into different type of lower order ODUk  12 , which can then be multiplexed into different size higher order ODUk  13  and then synchronously mapped into corresponding OTUk frames  14 . This multiplexing structure will even be complicated by the future introduction of a next higher ODUk rate of approximately 400 Gb that will then be termed ODUs. 
         [0016]    To simplify this multiplexing hierarchy, the inventor proposes to map all kind of client signals into lower order ODUflex and remap existing ODUk into order ODUflex. 
         [0017]    The resulting multiplexing hierarchy is shown schematically in  FIG. 2 . All client signals  21 , independent of their type and origin will be mapped into ODUflex  22 . Existing ODUk  25  will be re-mapped into ODUflex  22 . ODUflex  22  will then be multiplexed and mapped into a higher order ODUk  23  corresponding to the line rate and transported in a corresponding OTUk frame  24 . 
         [0018]    A network with simplified ODUk switching is shown schematically in  FIG. 3 . Within OTN domain  30 , there are different network nodes  31 - 34 . Nodes  31  and  34  represent boarder nodes, which can receive and transmit any kind of ODUk signals at interfaces  311 ,  342 . Within OTN domain  30 , all network nodes  31 - 34  transmit only signals carrying lower order (LO) ODUflex. 
         [0019]    For instance, network node  31  receives an ODUk signal where k can be any valid value. An internal switch function  313  is provided, which connects the received ODUk to interface  312 . Interface  312  contains an ODU remapping function to remap the ODU into LO ODUflex, adapt it to an appropriate higher order (HO) ODUk and map the latter to a corresponding OTUk for transport with OTN domain  30 . It should be noted, that the remapping function could in principle also be located in interface  312 . Received client signals other than ODUk are mapped into ODUflex as shown in  FIG. 2 . 
         [0020]    Node  32  contains interfaces  321 ,  322  and internal switch function  323  interconnecting interfaces  321 ,  322 . Similarly, node  33  contains interfaces  331 ,  332  and an internal switch function  333  interconnecting interfaces  331 ,  332 . Interfaces  321 ,  322  and  331 ,  332  receive and transmit only signals carrying LO ODUflex. Node  34  receives and transmits at interface  341  signals carrying ODUflex and at interface  342  signals capable of carrying any kind of ODUk signals. Switch function  343  interconnects interfaces  341 ,  342 . Interface  341  contains a remapping function for converting received LO ODUflex into ODUk as pre-configured at interface  342   
         [0021]    The signal between nodes  31  and  32  has a rate of 10 G corresponding to OTU 2 , the signal between nodes  32  and  33  has a rate of 100 G corresponding to OTU 4 , and the signal between nodes  33  and  34  has a rate of 40 G corresponding to OTU 3 . Therefore, at node  31 , the re-mapped LO ODUflex is mapped into HO ODU 2 , in node  32 , ODUflex received at interface  321  is mapped into HO ODU 4 , and at node  33 , received ODUflex is mapped into HO ODU 3 . 
         [0022]      FIG. 4  shows the functional model of the ODUk/ODUflex remapping function implemented into boarder nodes  31 ,  34 , respectively. Towards an external network domain, a usual OTN line cards  41  is provided, which has a OTUk termination function  411  and an OTUk/ODUk adaptation function. An interconnection function  42 , such as an ODU switch matrix, interconnects the various line card  41 ,  43  of the network node. 
         [0023]    An OTN line card  43  is provided towards an internal network domain. Similar to line card  41 , line card  43  contains a OTU termination function  431  and a OTUk/ODUj adaptation function  432 . Additionally, line card  43  contains a ODUk termination function  436  for ODUk received from connection function  42  and an ODU termination function  435  for LO ODUflex. ODU termination functions  436  and  435  are interconnected. Since ODUflex cannot be mapped directly into OTUk, higher order ODUk termination function  433  and ODUk/ODUj adaptation function  434  are provided between ODU termination function  435  and  432 . 
         [0024]    It should be noted that  FIG. 4  shows the case with only a single incoming HO ODUk being mapped to one single internal LO ODUflex. However, all combinations with external HO or LO ODUk and internal one single or several LO ODUflex are covered by the invention as well and could be implemented by those skilled in the art using the mapping principles and procedures known from G.709. In all these cases, the re-mapping part above ODU connection function  42  remains unchanged. 
         [0025]    It should be understood that the connection between  435  and  434  does not necessarily go physically through connection function  42  even if this is the case in the functional view of  FIG. 4 . The actual physical implementation is implementation specific. 
         [0026]    ODUflex uses 1.25 Gbit/s tributary time slots of a higher order ODUk (k&gt;1) to create a variable size container and can either transport a constant bitrate (CBR) client signal using Bit-synchronous Mapping Procedure (BMP), or can carry packet data flows encapsulated with Generic Framing Procedure (GFP). 
         [0027]    ODUflex are in any case multiplexed into a higher, fixed rate ODUk for transport in the OTN. As with all cases of ODUj to ODUk multiplexing, the lower rate ODUj occupies some number of Tributary Slots of the higher rate ODUk. For ODUflex multiplexing, the Tributary Slot granularity is roughly 1.25 Gbit/s. Since ODUflex are effectively asynchronous to the ODUk into which they are multiplexed, a mapping mechanism termed Generic Mapping Procedure (GMP) is employed. 
         [0028]    GMP is a mechanism used to accommodate the nominal bit-rate difference between a client and server layer, and the clock variations that may occur between client and server layer signals. No distinction is made between fixed and variable stuff locations. The server frame (or multi-frame) is divided into a certain number of GMP words, where each word may contain either data or stuff. Words containing data are distributed as evenly as possible, quantized to word size, across the server frame using a sigma/delta distribution algorithm. 
         [0029]    Proper operation depends only on mapper and demapper knowing the number of data words which are filled into each frame (or multi-frame). Larger GMP word sizes are used for higher bit-rate clients to avoid the need for large barrel shifters. Additional timing information may be transmitted from the mapper to the demapper to meet the timing requirements of the client if necessary. This allows the demapper to know how many client bytes (or bits) are to be emitted by the demapper during each server frame period. 
         [0030]    The formula governing the Sigma/Delta algorithm is as follows: 
         [0031]    Content of each Payload position is
       data, if (Payload position×data byte count) mod (P server )&lt;data word count and   stuff, if (Payload position×data byte count) mod (P server )≧data word count,
 
where P server  is the total number of word positions in the server frame payload.
       
 
         [0034]    P server  is always known and fixed. Similarly, the payload position being evaluated is also inherently known. The final variable, the data word count, changes from frame to frame to match the rate of the client being mapped. For each frame, the appropriate count is determined by the mapper and signaled in the OPUk overhead to the demapper using the JC 1 / 2 / 3  bytes. 
         [0035]    The count being signaled is 14 bits, to support the 15232 payload bytes in an OPUk frame, and spans both JC 1  and JC 2 . To ensure robustness at the receiver in the presence of bit errors, JC 3  contains a CRC-8 which allows error detection and certain amount of error correction. There is also an encoding for count increments or decrements and a state machine at the receiver is used to manage the values received and protect against bit errors. The demapper requires the count before the first payload position occurs, so it has to be determined and signaled in the previous frame. 
         [0036]    While, as explained, ODUflex is always mapped into HO ODUk using GMP, G.709 defines that some other LO ODUj use the asynchronous mapping procedure (AMP) for mapping into HO ODUk. The PSI field in the OPUk OH contains a payload type (PT) value, which defines the tributary slot size for multiplexing of LO ODUj into HO ODUk. Table 7-10 below, taken from G.709, defines the applicable mapping procedure and payload type values. 
         [0000]    
       
         
               
             
               
               
               
             
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 7-10 
               
             
             
               
                   
               
               
                 Overview of ODUj into OPUk mapping types 
               
             
          
           
               
                   
                 2.5 G tributary slots 
                 1.25 G tributary slots 
               
             
          
           
               
                   
                 OPU2 
                 OPU3 
                 OPU1 
                 OPU2 
                 OPU3 
                 OPU4 
               
               
                   
               
             
          
           
               
                 ODU0 
                 — 
                 — 
                 AMP 
                 GMP 
                 GMP 
                 GMP 
               
               
                   
                   
                   
                 (PT =  
                 (PT =  
                 (PT =  
                 (PT =  
               
               
                   
                   
                   
                 20) 
                 21) 
                 21) 
                 21) 
               
               
                 ODU1 
                 AMP 
                 AMP 
                 — 
                 AMP 
                 AMP 
                 GMP 
               
               
                   
                 (PT = 20) 
                 (PT = 20) 
                   
                 (PT =  
                 (PT =  
                 (PT =  
               
               
                   
                   
                   
                   
                 21) 
                 21) 
                 21) 
               
               
                 ODU2 
                 — 
                 AMP 
                 — 
                 — 
                 AMP 
                 GMP 
               
               
                   
                   
                 (PT = 20) 
                   
                   
                 (PT =  
                 (PT =  
               
               
                   
                   
                   
                   
                   
                 21) 
                 21) 
               
               
                 ODU2e 
                 — 
                 — 
                 — 
                 — 
                 GMP 
                 GMP 
               
               
                   
                   
                   
                   
                   
                 (PT =  
                 (PT =  
               
               
                   
                   
                   
                   
                   
                 21) 
                 21) 
               
               
                 ODU3 
                 — 
                 — 
                 — 
                 — 
                 — 
                 GMP 
               
               
                   
                   
                   
                   
                   
                   
                 (PT =  
               
               
                   
                   
                   
                   
                   
                   
                 21) 
               
               
                 ODUflex 
                 — 
                 — 
                 — 
                 GMP 
                 GMP 
                 GMP 
               
               
                   
                   
                   
                   
                 (PT =  
                 (PT =  
                 (PT =  
               
               
                   
                   
                   
                   
                 21) 
                 21) 
                 21) 
               
               
                   
               
             
          
         
       
     
         [0037]    Thus, re-mapping of ODUk into LO ODUflex may require a change of the payload type value and a change of the applicable mapping procedure, i.e. from AMP to GMP. 
         [0038]      FIG. 5  shows a block diagram of the re-mapping function implemented within a boarder network node  31 ,  34 , in  FIG. 3 . 
         [0039]    A optical interface  51 , for example a coherent optical receiver, receives an optical line signal and converts it into an electrical data signal, which is fed to a framer  52 . Framer  52  scans the data signal for a frame alignment signal (FAS) and, when locked to a FAS, terminates the section overhead. 
         [0040]    The output of framer  52  is fed to a selector  55  and to a processor  53 , which converts the mapping procedure from AMP to GMP if required. The output of processor  53  is fed to selector  55  and to a processor function  54 , which changes the payload type from type 20 to type 21, if required. The output of selector  55  is connected to a remapper  56 . A clock signal  63  derived at framer  52  is used to drive processors  53 ,  54  and remapper  56 . 
         [0041]    Remapper  56  contains a demultiplexer  57 , which extracts the OPUk payload bytes and ODUk overhead bytes from the received input and transfers it 1:1 to a multiplexer  58 , which re-maps the payload and overhead into a LO ODUflex and multiplexes the latter into a HO ODUk. No recalculation of BIP-8 parity blocks from the received signal is required. 
         [0042]    The clock of the LO ODUflex is determined by the clock of the ODUk that is being remapped to the LO ODUflex to allow timing transparency. Conversely, at the far end edge node, where the ODUflex is “demapped” into the original ODUk format, the recovered ODUk clock is determined by the LO ODUflex, thus allowing full end-to-end timing transparency. 
         [0043]    The output of multiplexer  58  is fed to an OTU framer  60 , which adds framing and section overhead and forwards the signal to a transmit-side optical interface  61 . At optical interface  61 , the signal is modulated onto an optical carrier for transmission over an optical fiber section. 
         [0044]    It should be understood that for the sake of simplicity, only one direction, with remapping ODUk into LO ODUflex, i.e. domain external interface towards domain internal interface, is shown. However, the opposite direction works symmetrical, with LO ODUflex clock driving the demapping process. It should be understood, however, that since the re-mapped ODUflex is a valid G.709 signal, demapping back into the original ODUk format is not necessary, depending on the application. 
         [0045]    Selector  55  selects from the three processing paths, i.e. (1) no AMP-GMP remapping and no PT remapping, (2) AMP-GMP remapping and no PT remapping, (3) both AMP-GMP and PT remapping, depending on the type of input ODUk and its payload type value according to table 7-10 of ITU-T G.709 shown above. 
         [0046]    In a further improvement, an OPUk OH byte is used to indicate that the signal has been remapped. It should be understood that in principle as a matter of definition, any available overhead bit can be used to indicate that the ODUflex has been remapped from another ODUk. However, it is preferable to re-use the existing payload structure identifier (PSI) for this additional purpose. 
         [0047]    In particular, the bit  1  (MSB) of PSI[0] is inverted for valid payload type code points (0x01 to 0x21) to indicate that the LO ODUflex transports a remapped ODUk. The inversion is performed when mapping ODUk into LO ODUflex and when mapping LO ODUflex back into ODUk. For other PSI[0] values than 0x01 to 0x21 resp. 0x81 to 0xa1 there is no inversion, in this case PSI[0] is mapped unchanged. In case the optional modification is not performed, PSI[0] is mapped unchanged, consequently there is no indication in the LO ODUflex that indicates the transport of an ODUk in the LO ODUflex. 
         [0048]    It is a configuration parameter of the mapping function if the optional PSI[0] inversion is performed or not. Other PSI bytes than PSI[0] are mapped unchanged. 
         [0049]    Accordingly, an inverter  59  is located between demultiplexer  57  and multiplexer  58 , which inverts the extracted PSI[0] bit. A control signal  62  activates or deactivates the PSI[0] bit inversion. 
         [0050]    The description and drawings merely illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof. 
         [0051]    The functions of the various elements shown in the figures, including any functional blocks labeled or described as “processors”, may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included. Similarly, the selector shown in  FIG. 5  is conceptual only. Its function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.