Abstract:
A controller apparatus for utilizing downgrade memory and method for operating the same are proposed. The controller apparatus uses address assignment to access the downgrade memory, which is classified by accessible address after testing. The controller apparatus is applicable to various applications, including memory interface controller for the accessing of a sub system. The controller apparatus can be integrated into the sub system within single chip. The controller apparatus further comprises at least one recording unit to record the initialization format and address mapping relation of a specific downgrade memory. Therefore, controller apparatus can be adapted to access various kinds of downgrade memory designated by the recording unit.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a memory controller and an operating method for the same, especially to a memory controller for using a downgrade memory with initialization step and an operating method for the same  
         [0003]     2. Description of Prior Art  
         [0004]      FIG. 1  shows a block diagram of a conventional DDR SDRAM, which exemplifies a prevailing DRAM structure since the commencement of SDRAM. The shown memory is divided into a plurality of banks selected by bank address. The memory cells in each bank are accessed through a plurality of column addresses and a plurality of row addresses. As also shown in this figure, the column addresses and the row addresses are generally accessed in multiplexing way as the capacity size of DRAM memory increases. Taking a 256M (32M*8) memory as example, all the address pins A 0 -A 12  in address bus shown on left-top side of  FIG. 1  are allocated to row address, while part of the address bus (for example, A 0 -A 9 ) are allocated to column address in multiplexing fashion to save pin count. As also shown in  FIG. 1 , the bus of the memory also comprises bank address BA 0 , BA 1  to select memory bank, control signal pins /CAS, /RAS, /WE, and /CS (where slash “/” indicated inverted active signal) and data signal pins DQ 0 -DQ 7 . The address pins A 0 -A 12  and BA 0 , BA 1  can also be used for setting mode registers besides addressing.  
         [0005]      FIG. 2  shows an allocation table for row address, column address and bank address of a standard SDRAM memory. Taking also the 256M (32M*8) memory as example, the address pin setting for row address, column address and bank address is (2, 13, 10). As can be seen from  FIG. 2 , the pin counts of the SDRAM memory has specific regulation for correctly accessing the SDRAM memory through a memory controller.  
         [0006]     As the progress of semiconductor technology, the capacity of DRAM memory is also rapidly increased. The current operation system also has capability to access memory larger than 4G bytes and the capacity of the commercially available memory is generally larger than 128 M bytes. Semiconductor memories are generally subjected to a test step after manufacture. If the defect of the memory is not serious after examination by the test step, the error can be corrected by redundant memory cells before package of the memory. However, if the defect of the memory is serious, the error cannot be corrected by redundant memory cells. The defected memory will be dropped or used as downgrade memory. In the downgrade memory, only accessible portion in the memory is used and the storage capacity is generally smaller than the normal capacity.  
         [0007]     The applications of the conventional downgrade memory have following three ways, or the combination thereof.  
         [0008]     As shown in  FIG. 3A , in the first conventional way to use downgrade memory, an external redundant memory  76  is used to correct the error of the downgrade memory  70 . An external non-volatile memory unit  72  is used to record the defect location and used for the reference of the external redundant memory  76 . The external non-volatile memory unit  72  can be realized by, for example, EEPROM or Flash memory and the external redundant memory  76  can be realized by, for example, SRAM or DRAM memory. The external redundant memory  76  can be integrated into ASIC or independently arranged. A comparison/control unit  74  compares an accessing address with defect location and the comparison result is used to control a data bus multiplexer  78  to determine whether the output will be generated by the external redundant memory  76 . An alternative way is to use the comparison/control unit  74  to control the DM/DQM signal of memory  70  to control the output from the memory  70  and the external redundant memory  76 . The first conventional way has a disadvantage of higher cost caused by the high speed and complicated comparison/control unit  74 . The comparison/control unit  74  may need to integrate with the external redundant memory  76  to the same ASIC. However, the use of data bus multiplexer  78  to intercept data bus or the use of DM/DQM signal of memory  70  will cause bus contention problem. The accessing speed of the downgrade memory is limited. Moreover, the use of non-volatile memory unit  72  to record the defect location and the complexity in the comparison/control unit  74  will limit the application of the first conventional way to downgrade memory with less defect.  
         [0009]     The second conventional method involves data line division, where the defected areas are precluded in terms of data line DQ. With reference to  FIG. 3B , where two 32M*8 SDRAMs are tested and sorted and are used with 32M*1 bit DQ line. For example, if one 32M*8 SDRAM has available area of 32M*2(DQ0−DQ1) and another 32M*8 SDRAM has available area of 32M*6(DQ2−DQ7), the available 2+6=8 DQ lines can be drawn from the two SDRAMs such that a 32M*8 SDRAM is simulated. This method has the advantage of low cost. However, the utilization rate thereof is limited, because the division based on the 32M*1 bit DQ is not compatible with global area layout inside the memory. For example, when all 8 bits for one address are malfunctioned, this defected memory cannot be used as downgrade memory by this method even though this defect is minor.  
         [0010]     The third conventional method uses address line division to preclude the defected area in terms of address line. Taking a 32M*8 DRAM as example (as shown in  FIG. 2 , the pin setting is Bank*Row*Column=2*13*10), the defected area for this DRAM is corresponding to the portion with Row address A 12  being High after test. In other word, the defected area will never be accessed if the Row address A 12  is kept pulling High. In this situation, as shown in  FIG. 3C , the defected area can be precluded by always pulling low the physical address line A 12 . With reference also to  FIG. 2 , the memory downgraded in this way can be used as a standard 16M*8 DRAM. This downgrade method has the advantage of versatile variation because the address line has large amount. The variation can also be applied to pull High/Low, address inversion etc. The downgrade method can be performed for one fold downgrade or two fold downgrade (32M*8 down to 8M*8) or more folds. However, the downgrade method has the disadvantage of involving ASIC for address conversion. If the address line to be processed is not an exclusive address line, namely, the address line is multiplexed for row address and column address; ASIC is needed for address conversion. Moreover, the downgraded memory may not be a standard DRAM after address line division. For example, a 16M*8 DRAM (Bank*Row*Column=2*12*10) is downgraded by pulling low the A 11  address line, however, this downgraded memory is not a standard DRAM as can be reference to  FIG. 2 . Therefore, an ASIC is needed to convert the signal of the downgraded memory to simulate an 8M*8 DRAM with pin assignment Bank*Row*Column=2*12*9. Moreover, for advanced DRAM memory such as SDRAM and its successors, the address lines there are also used for initialization commands such as MRS, EMRS commands. Therefore, additional ASIC is needed for signal conversion, which can be referred to Taiwan Patent No. 198183. This patent is also filed by the same applicant as the present invention.  
         [0011]     However, the above-mentioned related art has the disadvantages of high cost and signal delay to hinder high-speed application. Moreover, various ASICs are needed for different address conversion schemes, this is inflexible. Moreover, the above-mentioned related art downgrade method is limited to certain conversion, for example, column address reduction instead of column address augmentation.  
       SUMMARY OF THE INVENTION  
       [0012]     It is the object of the present invention to provide a memory controller for downgrade memory to overcome above-mentioned problem. The utilization rate can be increased and with extremely low delay and low cost.  
         [0013]     According to a preferred embodiment of the present invention, the memory controller is provided between a downgrade memory and a memory requester. Herein several items are defined to better understand the following. The term “non-defect area” is referred to a cell group without any defect. The term “defect area”, is referred to a cell group which at least covers all defect cells. The memory controller sends initialization signals to the downgrade memory according to pin setting of the downgrade memory. The memory controller helps the memory requester to access at least a subset of the non-defect area of the downgrade memory according to memory space requested by the memory requester.  
         [0014]     Preferably, the memory controller according to a preferred embodiment of the present invention sends predetermined signals to downgrade logical addresses of the downgrade memory according to a downgrade type setting. The predetermined signals can be directly pulling high/low according to the downgrade type setting or some specific signals or the logic combination thereof.  
         [0015]     Preferably, the memory controller according to a preferred embodiment of the present invention comprises a recording unit to record the information of available logical address, correct initialization command and downgraded status. The recording unit can be implemented by jumper, connection status of resistor or EEPROM.  
         [0016]     The memory controller according to the present invention can be easily applied to most current commercially available memory. The downgrade addresses can be bank addresses, row address and column addresses precluded with burst length range. The memory controller according to the present invention can be easily applied to full page burst memory (for example, frame buffer memory) as long as the page size of the downgrade memory is larger than the requested page size. 
     
    
     BRIEF DESCRIPTION OF DRAWING  
       [0017]     The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which:  
         [0018]      FIG. 1  shows a block diagram of a conventional DDR SDRAM.  
         [0019]      FIG. 2  shows an allocation table for row address, column address and bank address of a standard SDRAM memory.  
         [0020]      FIG. 3A  shows the first conventional way to use downgrade memory.  
         [0021]      FIG. 3B  shows the second conventional way to use downgrade memory.  
         [0022]      FIG. 3C  shows the third conventional way to use downgrade memory.  
         [0023]      FIG. 4A  shows a schematic diagram of a first preferred embodiment of the present invention.  
         [0024]      FIG. 4B  shows a schematic diagram of a second preferred embodiment of the present invention.  
         [0025]      FIG. 4C  shows a schematic diagram of a third preferred embodiment of the present invention.  
         [0026]      FIG. 4D  shows a schematic diagram of a fourth preferred embodiment of the present invention.  
         [0027]      FIG. 4E  shows a schematic diagram of a fifth preferred embodiment of the present invention.  
         [0028]      FIG. 5  demonstrates the working principle of the first preferred embodiment of the present invention.  
         [0029]      FIG. 6  shows a flowchart according to a preferred embodiment of the present invention.  
         [0030]      FIG. 7A  shows a mapping relationship with reference to the control input pins.  
         [0031]      FIG. 7B  shows another mapping relationship with reference to the control input pins.  
         [0032]      FIG. 8  is a schematic diagram showing the concept of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0033]     In any application system using memory, a memory controller is employed to facilitate one or more sub-system to access the memory. The sub-system is referred to as Memory Requester hereinafter for clarity. The portion of the memory controller, which faces the memory, is referred to as Front-End. The portion of the memory controller, which faces the memory requester, is referred to as Back-End hereinafter for clarity. The memory controller has versatile functions such as memory refresh, switch and trace of memory page, initialization control of memory and mapping relationship between front-end and back-end.  
         [0034]     In the prior art downgrade memory, one or more downgrade memory is used to simulate a standard memory for the accessing of memory controller. In the present invention, the memory controller has a built-in initialization control and provides mapping relationship between front-end and back-end for downgrade memory.  
         [0035]      FIG. 4A  shows a schematic diagram of a first preferred embodiment of the present invention. The present invention can be applied to any electronic system  10  needing to access memory. As shown in this figure, the electronic system  10  comprises one or more sub-systems  100  and the sub-systems  100  accesses a downgrade memory  20  through the help of a memory controller  120 .  
         [0036]      FIG. 5  demonstrates the working principle of the first preferred embodiment of the present invention, where the sub-systems  100  needs memory with 2 m  addressable space, namely, m logical address lines. A memory  20  with 2 n  addressable space (namely the memory  20  has n logical addresses including bank address, row address and column address), the available capacity after address line division needs to exceed 2 m  bits.  
         [0037]     In this example, q logical addresses (q≧0) in the Y physical lines are the logical address for downgrade division (hereinafter, the q logical addresses are referred to as first downgrade logical addresses) and the downgrade command and initialization commands for those q logical address do not need logic gate, namely, the physical address lines corresponding to the q logical address can be directly connected to ground level or high level. Moreover, the X physical lines for the remaining (n−q)=p logical address lines are linked to the memory controller  120 , where the p logical addresses are referred to as linked logical addresses. In the p logical addresses, there are r logical addresses (r&gt;0) and (p−r)≧m, where the r logical addresses are referred to as second downgrade logical addresses. When the memory controller  120  sends initialization commands for the memory  20 , the memory controller  120  sends correct signal satisfied with standard through the X physical lines according to initialization needs and a pin setting of the downgrade memory. In memory accessing stage, the memory controller  120  helps to access m requested logical addresses, while the memory controller  120  sends suitable signal for the r second downgrade logical addresses according to the downgrade type setting. For the (p−r−m) unused logical addresses, the memory controller  120  sends predetermined signal for those logical addresses. The (p−r−m) unused logical addresses can also be treated as downgrade logical addresses for simplification.  
         [0038]     The downgrade type setting imposes limitation on applicable signals for certain logical addresses to prevent from using the defect area in the downgrade memory. When the first and the second downgrade logical addresses of the downgrade memory are applied with signals complied with the downgrade type setting in data-accessing stage, the defect area can be prevented from accessing. In above-mentioned preferred embodiment, the first downgrade logical addresses (the q logical addresses) are not processed through the memory controller  120 . The second downgrade logical addresses (the r logical addresses) are processed through the memory controller  120 . The memory cells corresponding to the (p−r−m) unused logical addresses are beyond the requirement of the memory requester. Therefore, the (p−r−m) unused logical addresses can be treated as the second downgrade logical addresses for simplification.  
         [0039]      FIG. 6  shows a flowchart according to a preferred embodiment of the present invention.  
         [0040]     Step S 600 : Determining the logical addresses number m required by the electronic system and the linked logical addresses p.  
         [0041]     Step S 610 : Determining the second downgrade logical addresses r among the p linked logical addresses.  
         [0042]     Step S 620 : Sending initialization signal through the X linked physical lines.  
         [0043]     Step S 630 : Accessing  2   m  addressable space in the memory according to the logical addresses number m required by the sub-system.  
         [0044]     Step S 640 : Sending suitable signal to the r second downgrade logical addresses.  
         [0045]     Step S 650 : Sending predetermined signal, such as signals of fixed level, to the (p−r−m) unused logical addresses.  
         [0046]      FIG. 4B  shows the block diagram according to another preferred embodiment of the present invention, where the sub system  100  is exemplified with a micro controller  100 . A recording unit  140  is incorporated to help the memory controller  120  to send correct initialization command and signal conversion according to downgrade type setting of the memory  20 .  
         [0047]     The recording unit  140  can be any medium with recording function such as jumper, connection status of resistors, EEPROM, record or firmware in micro-controller. The recording unit  140  can be used to indicated the supportable types of downgrade memory for the memory controller  120 . For example, the supportable types of downgrade memory can be 4M*16 or 8M*16 memory.  
         [0048]     In the second preferred embodiment of the present invention, there is only one memory requester  100  in back-end of the memory controller  120  and the required memory capacity is 8M*16. The memory controller  120  is connected to the memory requester  100  through address lines SA 0 , SA 1  . . . SA 22 . The memory  20  connected to the front end of the memory controller  120  is an 8M*16 downgrade memory, which is downgraded from a 16M*16 SDRAM. The memory  20  has following six address division ways, where we use BA for representing bank address, RA for representing row address and CA for representing column address. The first division way is CA 7 =L to indicate a required portion in the non-defect area; the second division way is CA 7 =H to indicate a required portion in the non-defect area; the third way is RA 7 =L to indicate a required portion in the non-defect area; the fourth way is RA 7 =H to indicate a required portion in the non-defect area; the fifth way is CA 7 =RA 7  to indicate a required portion in the non-defect area and the sixth way is CA 7 =/RA 7  to indicate a required portion in the non-defect area, where slash “/” means inverted phase. The physical address lines A 0  . . . A 12 ,BA 0 ,BA 1  of the memory  20  are connected to the pins MA 0  . . . MA 14  of the memory controller  120 . In this preferred embodiment, the recording unit  140  is realized by connecting three jumpers JP 0 -JP 2  to three control input pins S 2 , S 1  and S 0  of the memory controller  120 . The skilled in the art would know that the no prior art technology can simulate the downgrade memory with above-mentioned six address division ways into standard 8M*16, even though the downgrade memory with above-mentioned six address division ways has the memory capacity of 8M*16.  
         [0049]     The memory controller  120  has following operations according to the present invention. Provided the memory controller  120  sets the CAS Latency=3, Wrap Type being linear Mode, Burst Length=4, then the memory controller  120  sends 0,0,0,0,0,0,0,0,0,1,1,0,0,1,0 for pins MA 14  . . . MA 0  in MRS command during initialization stage of the memory. Namely, the signals sent to MA 1 ,MA 4 ,MA 5  pins are high, and the remaining signals are low, this step can also be referred to the description of S 620 .  
         [0050]     In data accessing stage, the memory controller  120  establishes a mapping relationship between the logical address BA 0 ,BA 1 ,RA 0  . . . RA 12 ,CA 0  . . . CA 8  at front end and the address lines SA 0 ,SA 1  . . . SA 22  at back end according to the input status of the control input pins S 2 , S 1 , S 0  and with reference to the relationship in  FIG. 7A . As can be seen from this figure, the memory controller  120  establishes a mapping relationship for supporting downgrade memory characterized by CA 7 =L when the S 2 ,S 1 ,S 0  are L,L,L. the memory controller  120  establishes a mapping relationship for supporting downgrade memory characterized by CA 7 =H when the S 2 ,S 1 ,S 0  are L,L,H. The operation for above mapping relationship can also be referred to the description for step S 630 .  
         [0051]      FIG. 4C  shows the third preferred embodiment of the present invention, where an additional pin S 3  is added to the recording unit  140  for supporting other address division types. When the signal at pin S 3  is low, the memory controller  120  can support above-mentioned six address division types. When the signal at pin S 3  is high, the memory controller  120  can also support six new address division types. As shown in  FIG. 7B , when S 3 , S 2 , S 1 , S 0  are H,L,L,L, the CA 5 =L address division type can be supported. When S 3 , S 2 , S 1 , S 0  are H,L,L,H, the CAS=H address division type can be supported. When S 3 , S 2 , S 1 , S 0  are H,L,H,L, the RA 5 =L address division type can be supported. When S 3 , S 2 , S 1 , S 0  are H,L,H,H, the RA 5 =H address division type can be supported. When S 3 , S 2 , S 1 , S 0  are H,H,L,L, the CA 5 =RA 5  address division type can be supported. When S 3 , S 2 , S 1 , S 0  are H,H,L,H, the CA 5 =/RA 5  address division type can be supported.  
         [0052]     As can be seen from above description, the memory controller  120  according to the present invention can support memory of almost any address division type as long as sufficient column address amount is reserved for page size and the column address for burst length is precluded according to the requirement of the requester. Moreover, the prior art downgrade method by address division needs different circuits for different division ways, while the memory controller  120  according to the present invention needs only change mapping relationship of address lines according to the setting of recording unit  140 . Therefore, the design complexity is greatly reduced.  
         [0053]     As can be seen from the second and the third preferred embodiment, the present invention can be applied to various address division schemes. For those applications with high efficiency and high speed request, the following fourth and the fifth embodiments shows simplifying scheme for increasing the utilization rate of downgrade memory without increasing internal delay.  
         [0054]      FIG. 4D  shows the fourth embodiment of the present invention. The memory controller  120  has similar back end as that in the second preferred embodiment However, for the connection between the memory  20  and the memory controller  120 , the A 6  pin can be selectively connected to MA 7  pin and the A 7  pin can be selectively connected to the MA 6  pin through the connection of external resistor or jumper. Therefore, the address division ways can be expanded to CA 6 =L, CA 6 =H, RA 6 =L, RA 6 =H, CA 6 =RA 6  and CA 6 =/RA 6  without increasing complexity of memory controller  120 .  
         [0055]      FIG. 4E  shows the fifth embodiment of the present invention. The fifth embodiment also supports similar downgrade memory with the third embodiment but in different way. In comparison with the third embodiment, the fifth embodiment is added with an identification input pin S 3  and the A 5  and A 7  pins of the memory  20  are connected to the memory controller  120  through the connection of external resistor or jumper. For MRS signal of initialization, when the pins A 5  and A 7  are connected to the pins MA 5  and MA 7 , the S 3  pin is set to be low such that the signals for the pins MA 14  . . . MA 0  are the same as the third embodiment to ensure the memory  20  has received the correct MRS commands. When the signals of the pins A 5  and A 7  are switched, the signal at the S 3  pin is set to be high such that the signals for the pins MA 14  . . . MA 0  are 0,0,0,0,0,0,0,1,0,0,1,0,0,1,0. Therefore, the memory  20  has received the correct MRS commands. The mapping relationship for the front end and back end of the memory controller  120  is independent of the signal at the S 3  pin and is the same as that shown in  FIG. 7A . Therefore the circuit complexity is transferred to the output logic circuits for initialization. Those output logic circuits for initialization can be set with arbitrary wait state and the overall system accessing is not influenced.  
         [0056]     The fifth embodiment of the present invention can be further simplified for system with micro controller. The initialization control can be performed by firmware of the micro controller. Therefore, the input state of the S 3  pin can be read by the micro controller and the various MRS signals are provided by firmware to not increase hardware complexity.  
         [0057]     The above-mentioned embodiments are exemplified with the mapping relationship between logic address signals of front end and back end in the memory controller  120 . However the mapping relationship between logic address signals of front end and back end is just a subset of a generic mapping relationship between front end and back end of the memory controller  120 . The concept of the present invention can be easily applied to downgrade memory with non-2′ power capacity.  
         [0058]     The sixth embodiment of the present invention can be used for a downgrade memory with non-2′ power capacity. Provided that there are three memory requesters and each of the memory requesters needs an individual 1M*16 memory capability, the total memory capability needed is 3M*16. In this preferred embodiment, the memory controller  120  comprises two control input pins S 1  and S 0  to identify and support for 3M*16 downgrade memory, which is downgraded from 8M*16 memory. The memory controller  120  according to the sixth embodiment of the present invention can support following downgrade type. When the signals of the pins S 1 ,S 0  are L,L, the memory controller  120  can support a 3M*16 downgrade memory having a required portion in the non-defect area with the pin setting CA 8 =H AND NOT(RA 8 =L AND CA 7 =L). When the signals of the pins S 1 ,S 0  are L,H, the memory controller  120  can support a 3M*16 downgrade memory having a required portion in the non-defect area with the pin setting CA 8 =H AND NOT(RA 8 =L AND CA 7 =H). When the signals of the pins S 1 ,S 0  are H, L the memory controller  120  can support a 3M*16 downgrade memory having a required portion in the non-defect area with the pin setting CA 8 =H AND NOT(RA 8 =H AND CA 7 =H). Hereinafter the three memory requesters are referred to as RQ 0 , RQ 1 , and RQ 2 . The respective 1M*16 for the memory requesters RQ 0 , RQ 1 , and RQ 2  form a virtual space of 3M*16. If the three highest addresses in the memory site are selected as CA 8 , RA 8 , and CA 7 , the memory space is divided into eight 1M*16 addressable sub-spaces by the logical addresses CA 8 , RA 8 , and CA 7 . The memory needed by the memory requesters RQ 0 , RQ 1 , and RQ 2  belong to three memory sub-spaces in the memory space addressable by the logical addresses CA 8 , RA 8 , and CA 7 . Therefore, the memory controller  120  can serve memory request for the memory requesters RQ 0 , RQ 1 , and RQ 2  as long as the memory controller  120  can establish mapping relationship between three 1M*16 memory locations at memory requester end with three 1M*16 memory sub-spaces at front end of the memory.  
         [0059]     In the sixth embodiment of the present invention, the memory controller  120  can one by one map the logical addresses SA 19 ,SA 18  . . . SA 0  of the 1M*16 memory location to the logical addresses BA 1 ,BA 0 ,RA 11  . . . RA 9 ,RA 7 ,RA 6  . . . RA 0 , CA 6 ,CA 5  . . . CA 0  of the front end of the memory. When the signals at pins S 1 ,S 0  are L,L and the memory requester RQ 0  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,H,H; when memory requester RQ 1  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,L,H; when memory requester RQ 2  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,H,L. When the signals at pins S 1 ,S 0  are L,H and the memory requester RQ 0  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,L,L; when memory requester RQ 1  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,H,H; when memory requester RQ 2  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,H,L. When the signals at pins S 1 ,S 0  are H,L and the memory requester RQ 0  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,L,L; when memory requester RQ 1  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,L,H; when memory requester RQ 2  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,H,H. When the signals at pins S 1 ,S 0  are H,H and the memory requester RQ 0  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,L,L; when memory requester RQ 1  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,L,H; when memory requester RQ 2  demands for memory accessing, the signals at the logical addresses CA 8 ,RA 8 ,CA 7  are set to be H,H,L.  
         [0060]      FIG. 8  is a schematic diagram showing the concept of the present invention. The downgrade memory is connected to the memory controller  120  through X physical lines and the X physical lines provide p linked logical addresses, which are larger than m logical addresses requested by system. Therefore, the X physical lines exceed what the system requires and the X physical lines provide memory accessing for downgrade memory of different defect types. By setting the memory controller  120  to access partial physical lines among the X physical lines, the memory controller  120  has flexibility to access different portions in the non-defect area in the downgrade memory of different defect types. On the contrary, the conventional memory controller for downgrade memory is generally connected to the downgrade memory with physical lines having number exactly meeting system requirement. Therefore, the conventional memory controller for downgrade memory can only be used for limited types of downgrade memory. The memory controller  120  according to the present invention has ability to connect to more physical lines and can access downgrade memory of versatile defect types through the help of the recording unit  140 . The memory controller  120  according to the present invention can be used for accessing downgrade memory of versatile defect type to reduce cost.  
         [0061]     Moreover, to demonstrate the versatile usage of the memory controller  120  according to the present invention, the application of m requested logical addresses are used to address 2 m  memory units. The actual need might not be 2 m  memory units and depends on designer choice. The manually assigned memory space for the back end of the memory controller can be generally expressed by a virtual space. When there is only one micro controller, the virtual space is the memory space for the micro controller. When there are different memory requesters at the back end of the memory controller, the memory space required by respective memory requester may be or may not be overlapped and can be manually assigned. The virtual addresses in the virtual space can be indicated by VA( 0 ), VA( 1 ) . . . VA(m− 1 ) and can be linked to the m logical addresses one by one through the memory controller  120 . For example, if the memory controller  120  according to the present invention is applied to DTV, the virtual addresses in the virtual space are the virtual addresses for the micro processor and the DS P processor, respectively. The memory resource requested by the micro processor and the DS P processor can be provided by accessing a downgrade memory through the memory controller  120  according to the present invention. When the memory resource requested is a non-2&#39;s power memory unit, a mapping relationship is established between the virtual space and the addressable memory locations in the memory. Therefore, the usage of memory controller  120  according to the present invention is not limited to what can be achieved by address line division, and can be extended addressable space mapping between back end and front end. The above mentioned 2&#39;s power memory unit is also a subset for the addressable space mapping.  
         [0062]     Accordingly the memory controller  120  according to the present invention has following advantages:  
         [0063]     1. Low cost: The current electronic system has a trend of highly integration such that the memory controllers are almost integrated into other chip. Taking PC as an example, the memory controller for main memory is integrated into North Bridge. In VGA card with AGP interface, the memory controller is integrated into single chip with GPU and AGP controller. The slight elaboration on the memory controller will not increase the cost for chip. However, the overall cost can be reduced because the memory controller  120  according to the present invention has flexibility to access other kinds of downgrade memories.  
         [0064]     2. Applicability for high speed environment: The memory controller according to the present invention involves small gate delay between the memory requester and the memory, while the prior art memory controller involves external  10  delay for ASIC.  
         [0065]     3. Great utilization rate for memory: The downgraded memory used by the memory controller according to the present invention  
         [0066]     Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.