Abstract:
A method of manufacturing a semiconductor structure for a substrate having electronic elements formed thereon is described. The method includes steps of forming a dielectric layer over the substrate and forming a trench in the dielectric layer. It should be noticed that a border shape of the trench is a non-straight shape. Finally, the trench is filled with a conductive material to form an interconnect structure.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This is a divisional application of patent application Ser. No. 10/907,890, filed on Apr. 20, 2005. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of Invention  
         [0003]     The present invention relates a method of manufacturing a semiconductor structure. More particularly, the present invention relates to a method of manufacturing an interconnect structure.  
         [0004]     2. Description of Related Art  
         [0005]     In the process of manufacturing an integrated circuit, interconnects are used to connect electronic elements to each other. As the increase of the integration of the integrated circuit, in order to accommodate to the increased requirement of interconnects due to decreasing the size of the electronic elements, it is common to use more than two conductive layers to construct the interconnects for connecting electronic elements to each other. In order to prevent the conductive layers from forming a short circuit by directly connecting to each other, the conductive layers are isolated from each other by using an inter-metal dielectric between the conductive layers. Further, the plugs are used to connect the successive conductive layers.  
         [0006]     Conventionally, the borders of the interconnects for connecting the electronic elements in touch with the inter-metal dielectric are straight. However, this kind of layout would leads to hardly releasing the stress of the interconnects and poor adhesion between the interconnects and the inter-metal dielectrics.  
       SUMMARY OF THE INVENTION  
       [0007]     Accordingly, at least one objective of the present invention is to provide a semiconductor structure having a non-straight-border-shape interconnect structure. Because of the non-straight-border-shape interconnect structure, the stress of the interconnect structure can be well distributed through the irregular borders. Hence, the delamination phenomenon can be alleviated and the defects due to delamination can be reduced. Further, since the border of the interconnect structure is irregular, the adhesion between two different type material, such as the conductive material and the dielectric material, can be increased and the reliability of the semiconductor structure is increased as well.  
         [0008]     At least another objective of the present invention is to provide a method of manufacturing a semiconductor structure capable of well distributing the stress of the conductive material to the non-straight border of the interconnect structure. Besides, because of the non-straight border of the interconnect structure, the adhesion between the conductive material and the dielectric material is increased and the reliability of the semiconductor structure is also increased.  
         [0009]     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor structure for a substrate having electronic elements formed thereon. The semiconductor structure comprises a dielectric layer and a conductive stuffing material. The dielectric layer is located over the substrate. It should be noticed that the dielectric layer has a plurality of trenched and a border shape of each trench is a non-straight shape. The conductive stuffing material fills the trenches to form an interconnect structure.  
         [0010]     In the present invention, the conductive stuffing material can be metal copper. Besides, the non-straight shape can be a zigzag shape, a wavy shape or an irregular shape comprising a plurality of protruding-recession pairs.  
         [0011]     The present invention also provides a semiconductor structure for a substrate having electronic elements formed thereon. The semiconductor structure comprises a dielectric layer and an interconnect structure. The dielectric layer is located over the substrate. The interconnect structure is located in the dielectric layer and the interconnect structure is composed of a plurality of wire sections and a border shape of each wire section is a non-straight shape.  
         [0012]     In the present invention, the interconnect structure is formed from metal copper. Further, the non-straight shape can be a zigzag shape, a wavy shape or an irregular shape comprising a plurality of protruding-recession pairs.  
         [0013]     The present invention further provides a method of manufacturing a semiconductor structure for a substrate having electronic elements formed thereon. The method comprises steps of forming a dielectric layer over the substrate and forming a trench in the dielectric layer. It should be noticed that a border shape of the trench is a non-straight shape. Finally, the trench is filled with a conductive material to form an interconnect structure.  
         [0014]     In the present invention, the step of forming the trench further comprises steps of forming a photoresist layer with a thickness on the dielectric layer, patterning the photoresist layer by using a photomask having a designed pattern, patterning the dielectric layer by using the patterned photoresist layer as a mask and removing the patterned photoreisist layer. More specifically, the thickness of the photoresist layer is less than that of the dielectric layer. Alternatively, a border shape of the designed pattern on the photomask is a non-straight shape. Further, the conductive material can be metal copper.  
         [0015]     Since the border of the interconnect structure is non-straight, the stress of the interconnect structure can be well distributed through the irregular borders. Therefore, the delamination phenomenon can be alleviated and the defects due to delamination can be reduced. Further, because the border of the interconnect structure is irregular, the adhesion between the conductive material and the dielectric material can be increased and the reliability of the semiconductor structure is increased as well.  
         [0016]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0018]      FIG. 1A  through  FIG. 1C  are three-dimensional views showing a method of manufacturing a semiconductor structure according to one of the preferred embodiments of the invention.  
         [0019]      FIG. 2  is a top view of  FIG. 1C  showing an interconnect structure having a non-straight border.  
         [0020]      FIG. 3A  through  FIG. 3C  are three-dimensional views showing a method of manufacturing a semiconductor structure according to one of the preferred embodiments of the invention.  
         [0021]      FIG. 4  is a top view of  FIG. 1C  showing an interconnect structure having a non-straight border. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]     In the invention, a novel semiconductor structure and a novel approach for manufacturing the semiconductor structure are proposed. The semiconductor structure according to the invention possesses an interconnect structure having non-straight border. Because of the non-straight border, the stress of the interconnects can be well distributed and the adhesion between the interconnects and the inter-metal dielectric can be improved.  
         [0023]      FIG. 1A  through  FIG. 1C  are three-dimensional views showing a method of manufacturing a semiconductor structure according to one of the preferred embodiments of the invention. As shown in  FIG. 1A , a substrate  100  is provided, wherein the substrate  100  has at least one electronic element formed therein. Thereafter, a dielectric layer  102  is formed over the substrate  100 . The dielectric layer  102  can be, for example, formed from silicon oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon nitride or silicon oxy-nitride by atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Then, a photoresist layer  104  is formed on the dielectric layer  102 . Notably, the thickness of the photoresist layer  104  is less than that of the dielectric layer  102 . More specifically, the thickness of the photoresis layer  104  is much less than the requirement of the design rule.  
         [0024]     As shown in  FIG. 1B , a photolithography process is performed to pattern the photoresist layer  104  and the photoresist layer  104  is transformed into a photoresist layer  104   a  having a trench pattern (not shown). Thereafter, an etching process is performed to pattern the dielectric layer  102  by using the photoresist layer  104   a  as a mask so that the dielectric layer  102  is transformed into a dielectric layer  102   a  having a trench  106 . Since the thickness of the photoresist layer  104   a  is much less than the required thickness for being as an etching mask in the etching process, the sidewall of the photoresist layer  104   a  is consumed by the etchant and becomes slant during the etching process. Therefore, the edge of the photoresist layer  104   a  is no longer straight but becomes non-straight. As a result, by using the photoresist layer  104   a  with a non-straight border  104   b  as an etching mask, the trench  106  formed in the dielectric layer  102   a  also possesses a non-straight border  102   b.    
         [0025]     As shown in  FIG. 1C  together with  FIG. 2 , the top view of  FIG. 1C , the photoresist layer  104   a  is removed. Then, the trench  106  (shown in  FIG. 1B ) is filled with a conductive material to form an interconnect structure  108 . The interconnect structure  108  can be, for example, formed from metal copper. Because the border of the trench  102   b  is non-straight, the interconnect structure  108  formed in the trench  106  also possesses a non-straight border  108   a.    
         [0026]      FIG. 3A  through  FIG. 3C  are three-dimensional views showing another method of manufacturing a semiconductor structure according to one of the preferred embodiments of the invention. As shown in  FIG. 3A , a substrate  200  is provided, wherein the substrate  200  has at least one electronic element formed therein. Thereafter, a dielectric layer  202  is formed over the substrate  200 . The dielectric layer  202  can be, for example, formed from silicon oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon nitride or silicon oxy-nitride by atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Then, a photoresist layer  204  is formed on the dielectric layer  202 .  
         [0027]     As shown in  FIG. 3B , a photolithography process is performed to pattern the photoresist layer  204  by using a photomask (not shown) and the photoresist layer  204  is transformed into a photoresist layer  204   a  having a trench pattern (not shown). Notably, the photomask has a designed pattern, and the border shape of the designed pattern on the photomask is a non-straight shape. The non-straight shape can be, for example, a zigzag shape, a wavy shape or an irregular shape comprising a plurality of protruding-recession pairs. After the photolithography process, the designed pattern on the photomask is transferred onto the photoresist layer  204  and the border of the trench pattern in the photoresist layer  204   a  is also non-straight. Thereafter, an etching process is performed to pattern the dielectric layer  202  by using the photoresist layer  204   a  as a mask so that the dielectric layer  202  is transformed into a dielectric layer  202   a  having a trench  206 . Since the sidewall of the photoresist layer  204   a  is non-straight, the border  202   b  of the trench  206  formed in the dielectric layer  202   a  is also non-straight. The edge of the trench  206  formed in the dielectric layer  202   a  can be, for example, a zigzag shape, a wavy shape or an irregular shape comprising a plurality of protruding-recession pairs.  
         [0028]     As shown in  FIG. 3C  together with  FIG. 3 , the top view of  FIG. 1C , the photoresist layer  204   a  is removed. Then, the trench  206  (shown in  FIG. 3B ) is filled with a conductive material to form an interconnect structure  208 . The interconnect structure  208  can be, for example, formed from metal copper. Because the border of the trench  202   b  is non-straight, the interconnect structure  208  formed in the trench  206  also possesses a non-straight border  208   a.    
         [0029]     In the both preferred embodiment of the present invention, a single interconnect/conductive wire formed in a single trench is used to represent the interconnect structure in the dielectric layer. However, in the application of the present invention, the interconnect structure is composed of several wire sections formed in trenches in the dielectric layer and the border shape of each wire section is non-straight shape.  
         [0030]     In the present invention, because of the non-straight-border-shape interconnect structure, the stress of the interconnect structure can be well distributed through the irregular borders. Hence, the delamination phenomenon can be alleviated and the defects due to delamination can be reduced. Further, since the border of the interconnect structure is irregular, the adhesion between two different type material, such as the conductive material and the dielectric material, can be increased and the reliability of the semiconductor structure is increased as well.  
         [0031]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.