Abstract:
A semiconductor circuit apparatus having a commonly shared control unit that coordinates reading and writing timed activities in two ranked subcircuits is presented. The semiconductor circuit includes: first and second ranks; and a rank control block shared by the first and second ranks and configured to provide a column-related command and an address to one of the first and second ranks in response to a chip select signal for selecting the first or second rank.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2009-0130726, filed on Dec. 24, 2009, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a semiconductor circuit apparatus, and more particularly, to a semiconductor circuit apparatus which controls ranks. 
         [0004]    2. Related Art 
         [0005]    In general, a rank in a semiconductor circuit apparatus refers to a unit memory chip which is controlled by one chip select signal and has an independent function. Depending on the configuration of the semiconductor circuit apparatus, one or more ranks may be provided. Here, a signal for activating ranks may be a chip select signal CS or chip enable signal CE. Each of the ranks is installed in such a manner that a unit memory chip having a plurality of semiconductor memory cells integrated therein is attached on a printed circuit board (PCB) and connected to a panel or the like through a plurality of contact terminals. 
         [0006]    Meanwhile, according to an inter-rank timing regulation, that is, a timing spec defined to satisfy a read or write mode between different ranks, tWTR is 1tCK. In this case, the respective ranks include an individual column command control unit and an individual address control unit such that when address information is provided to the corresponding rank, information of the rank does not collided with that of another rank. 
         [0007]    In the write mode, the address control unit should apply a write latency to provide address information to the rank. In this case, such a write latency delays the address through a plurality of shift registers. Therefore, when the address control unit is provided for each rank, it may degrade area efficiency of the semiconductor circuit apparatus. 
       SUMMARY 
       [0008]    A semiconductor circuit apparatus which controls a plurality of ranks is described herein. 
         [0009]    In one embodiment of the present invention, a semiconductor circuit apparatus includes: first and second ranks; and a rank control block shared by the first and second ranks and configured to provide a column-related command and an address to one of the first and second ranks in response to a chip select signal for selecting the first or second rank. 
         [0010]    In another embodiment of the present invention, a semiconductor circuit apparatus includes: first and second ranks; a command control unit configured to provide a column-related activation signal for each rank and read and write information signals of the corresponding rank in response to an chip signal for selecting the first or second rank; and an address control unit configured to latch the address in response to read and write combined information signals irrelevant to rank information. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0012]      FIG. 1  is a block diagram of a semiconductor circuit apparatus according to one embodiment; 
           [0013]      FIG. 2  is a block diagram of a rank control unit of  FIG. 1 ; 
           [0014]      FIG. 3  is a block diagram of a command control block of  FIG. 2 ; 
           [0015]      FIG. 4  is a block diagram of an address control block of  FIG. 2 ; 
           [0016]      FIG. 5  is a circuit diagram of a first address latch of  FIG. 4 ; 
           [0017]      FIG. 6  is a circuit diagram of a second address latch of  FIG. 4 ; 
           [0018]      FIG. 7  is a circuit diagram of a shift register of  FIG. 4 ; 
           [0019]      FIG. 8  is a circuit diagram of a first address supply unit of  FIG. 4 ; and 
           [0020]      FIG. 9  is a voltage waveform diagram showing the operation of the semiconductor circuit apparatus of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Hereinafter, a semiconductor circuit apparatus according to the present invention will be described below with reference to the accompanying drawings through preferred embodiments. 
         [0022]      FIG. 1  is a block diagram of a semiconductor circuit apparatus  10  according to one embodiment. 
         [0023]    Referring to  FIG. 1 , the semiconductor circuit apparatus  10  according to the embodiment includes a first rank  100 , a second rank  200 , and a rank control unit  300 . 
         [0024]    The first rank  100  is a memory area which is activated by a first chip select signal CS 0 . The second rank  200  is a memory area which is activated by a second chip select signal CS 1 . The first and second rank  100  and  200  may be referred to as first and second chips, respectively. In the semiconductor circuit apparatus configured in such a dual rank mode for supporting two ranks, the first and second ranks  100  and  200  may be independently driven by the respective individual first or second chip select signals CS 0  and CS 1 . 
         [0025]    The rank control unit  300  latches column-related commands WT and RD and an address ADD and provides the latched column-related commands and address to the corresponding ranks  100  and  200  in accordance with the activated chip select signals CS 0  and CS 1 . 
         [0026]    The rank control unit  300  receives the column-related commands WT and RD, the first and second chip select signals CS 0  and CS 1 , the address ADD, a clock signal CLK, and a write latency WL, and a burst length BL, and provides a first rank column command signal WT/RD_CS 0  and a first rank address signal ADD_CS 0  to the first rank  100  or a second rank column command signal WT/RD_CS 1  and a second rank address signal ADD_CS 1  to the second rank  200 . 
         [0027]    That is, the rank control unit  300  according to this embodiment is a shared circuit unit configured to control the column-related commands WT and RD and the address of the respective ranks  100  and  200 . More specifically, the rank control unit  300  receives the column-related commands WT and RD, and selectively provides the column-related commands WT and RD to the corresponding ranks  100  and  200  in accordance with the activated chip select signals CS 0  and CS 1 . Furthermore, the rank control unit  300  according to this embodiment may selectively provide an address signal (not shown) to the corresponding ranks  100  and  200 , the address signal being delayed by applying a necessary latency while latching the address ADD. This is different from the conventional semiconductor circuit apparatus including the address control unit and the column command control unit which are provided for each rank. The ranks are controlled by the shared rank control unit  300  in the semiconductor circuit apparatus  10  according to the embodiment. Therefore, it is possible to control the independent drive of each rank and improve the area efficiency of the semiconductor circuit apparatus. 
         [0028]      FIG. 2  is a block diagram of the rank control unit  300  of  FIG. 1 .  FIG. 3  is a block diagram of a command control block  305  of FIG.  2 . 
         [0029]    Referring to  FIGS. 2 and 3 , the rank control unit  300  includes a command control block  305  and an address control block  360 . 
         [0030]    The command control block  305  is configured to provide read and write signals for the corresponding rank and read and write signals without discrimination between the ranks, in response to the first and second chip select signals CS 0  and CS 1 , the column-related commands WT and RD, the write latency WL, and the burst length BL. More specifically, when the column-related commands WT and RD are inputted, the command control block  305  provides a first write information signal wt_cs 0 _L, a first read information signal rd_cs 0 _L, a second write information signal wt_cs 1 _L, a second read information signal rd_cs 1 _L, a write combined information signal WT_CS 01 , and a read combined information signal RD_CS 01 , in response to the corresponding chip select signals CS 0  and CS 1 . 
         [0031]    The command control block  305  includes a command reception unit  325  and a column command control unit  355 . 
         [0032]    The command reception unit  325  is configured to receive the column-related commands WT and RD and the first and second chip select signals CS 0  and CS 1  and configured to provide a first rank write signal wt_cs 0 , a first rank read signal rd_cs 0 , a second rank write signal wt_cs 1 , and a second rank read signal rd_cs 1 . 
         [0033]    The command reception unit  325  includes a first command control section  310  and a second command control section  320 . 
         [0034]    The first command control section  310  provides the first rank write signal wt_cs 0  and the first rank read signal rd_cs 0  in response to the column-related commands WT and RD and the first chip select signal CS 0 . Then, when the first chip select signal CS 0  and the write command WT of the column-related commands WT and RD are activated, the first command control section  310  provides the activated first rank write signal wt_cs 0 . Furthermore, when the first chip select signal CS 0  and the read command RD are activated, the first command control section  310  provides the first rank read signal rd_cs 0 . 
         [0035]    The second command control section  320  provides the second rank write signal wt_cs 1  and the second rank read signal rd_cs 1  in response to the column-related commands WT and RD and the second chip select signal CS 1 . Similar to the first command control section  310 , when the second chip select signal CS 1  and the write command WT of the column-related commands WT and RD are activated, the second command control section  320  provides the activated second rank write signal wt_cs 1 . Furthermore, when the second chip select signal CS 1  and the read command RD are activated, the second command control section  320  provides the second rank read signal rd_cs 1 . 
         [0036]    That is, the column-related commands WT and RD are provided to both of the first and second command control sections  310  and  320 . At this time, the column-related signals activated by the corresponding command control section may be provided in response to the respective activated chip select signals CS 0  and CS 1 . 
         [0037]    The column command control unit  355  receives the first rank write signal wt_cs 0 , the first rank read signal rd_cs 0 , the second rank write signal wt_cs 1 , the second rank read signal rd_cs 1 , the burst length BL, and the write latency WL, and provides a first column-related activation signal WT/RD_CS 0 , a second column-related activation signal WT/RD_CS 1 , a write combined information signal WT_CS 01 , a read combined information signal RD_CS 01 , a first write information signal wt_cs 0 _L, a first read information signal rd_cs 0 _L, a second write information signal wt_cs 1 _L, and a second read information signal rd_cs 1 _L. That is, the column command control unit  355  receives the activated column-related signal, determines whether the received column-related signal is a column-related signal for the first rank or the second rank, and provides the column-related activation signal to the corresponding rank. Furthermore, the column command control unit  355  combines the respective column commands to provide the write combined information signal WT_CS 01  and the read combined information signal RD_CS 01  to the address control block  360 . The write combined information signal WT_CS 01  and the read combined information signal RD_CS 01  inform whether the combined information is write information or read information irrelevant to the ranks. 
         [0038]    The column command control unit  355  includes a first column control section  330 , a second column control section  340 , and a command combination section  350 . 
         [0039]    The first column control section  330  receives the first rank write signal wt_cs 0  and the first rank read signal rd_cs 0 , and provides the first column-related activation signal WT/RD_CS 0  to the first rank  100 . The first column-related activation signal WT/RD_CS 0  is a main signal which is used to activate column-related signals. Accordingly, the first rank  100  activates the column-related signals in response to the first column-related activation signal WT/RD_CS 0 . Furthermore, the first column control section  330  receives the first rank write signal wt_cs 0 , and provides the first write information signal wt_cs 0 _L to the address control block  360  in the write mode, the first write information signal wt_cs 0 _L being delayed by the write latency WT and the burst length BL. That is, the first write information signal wt_cs 0 _L is a signal which is used to control latching an address related to a timing at which a write control operation is to be substantially performed in an internal circuit, in response to a write command provided from outside. Therefore, the first write information signal wt_cs 0 _L is a signal which has timing information for fetching an address signal required when the write operation of the internal circuit is performed, after data is inputted by the burst length BL after a predetermined write latency WL in response to the external write command. Meanwhile, since a latency is not required in the read mode, the first column control section  330  provides the first rank read signal rd_cs 0  as the first read information signal rd_cs 0 _L without delay. 
         [0040]    Similar to the first column control section  330 , the second column control section  340  receives the second rank write signal wt_cs 1  and the second rank read signal rd_cs 1 , and provides a second column-related activation signal WT/RD_CS 1  to the second rank  200 . The second column-related activation signal WT/RD_CS 1  is a main signal which is used to activate the column-related signals. Accordingly, the second column control section  340  receives the second rank write signal wt_cs 1 , and provides a second write information signal wt_cs 1 _L to the address control block  360  in the write mode, the second write information signal wt_cs 1 _L being delayed by the write latency WL and the burst length BL. In the read mode, however, the second column control section  340  provides the second rank read signal rd_cs 1  as the second read information signal rd_cs 1 _L without delay. 
         [0041]    The command combination unit  350  is configured to combine the respective column-related commands and provide the write combined information signal WT_CS 01  and the read combined information signal RD_CS 01  to the address control block  360 . The write combined information signal WT_CS 01  and the read combined information signal RD_CS 01  inform whether the combined information is write information or read information which is irrelevant to the ranks. 
         [0042]    The address control block  360  receives the clock signal CLK, the write latency WL, the address ADD, the write combined information signal WT_CS 01 , the read combined information signal RD_CS 01 , and the read and write information signals relevant to the respective ranks, and provides a first rank address ADD_CS 0  and a second rank address ADD_CS 1 . 
         [0043]    The address control block  360  latches the address ADD provided from outside in response to the write combined information signal WT_CS 01  and the read combined information signal RD_CS 01 , respectively. In the write mode, the address control block  360  applies the write latency to the address ADD and provides the address ADD to the corresponding rank in response to the activated information signal relevant to the rank. In the read mode, the address control block  360  provides the address ADD to the corresponding rank in response to the activated information signal relevant to the rank, without applying the latency. 
         [0044]    According to the embodiment, the command control unit and the address command unit are not provided for each of the ranks, but rather one rank control unit is shared by the plurality of ranks. Therefore, it is possible to improve the area efficiency. 
         [0045]      FIG. 4  is a block diagram of the address control block  360  of  FIG. 2 . 
         [0046]    Referring to  FIG. 4 , the address control block  360  includes an address separation unit  361 , a first address supply unit  367 , and a second address supply unit  368 . 
         [0047]    The address separation unit  361  includes a first address latch  362 , a second address latch  364 , and a shift resistor  366 . 
         [0048]    The first address latch  362  receives the read combined information signal RD_CS 01  and the address ADD to provide a read address lat_rd. That is, the first address latch  362  is an address latch for a read operation. Since a typical address latch is used as the first address latch  362 , the detailed description thereof will be omitted. 
         [0049]    The second address latch  364  receives the write combined information signal WT_CS 01  and the address ADD to provide a write address lat_wt. That is, the second address latch  364  is an address latch for a write operation. 
         [0050]    The shift register  366  receives the write latency WL, the clock signal CLK, and the write address lat_wt, and subsequently provides a delayed write address wl_wt. As described above, such a write operation is a synchronous command requiring a clock-based time regulation. In other words, the write operation of the semiconductor circuit apparatus starts in response to a write column-related signal which is generated while satisfying a predetermined time regulation required for an actual write operation. Then, the shift register  366  applies the write latency WL to delay the write address lat_wt. That is, the shift register  366  synchronizes the write address lat_wt with the clock CLK to delay the write address lat_wt by the corresponding write latency WL, and to provide the delayed write address wl_wt suitable for a timing required for the write operation. In particular, the shift register  366  according to the embodiment applies the latency and provides the commonly-delayed write address in the write mode, regardless of the ranks. Therefore, it is possible to improve the area efficiency. This will be described below in detail with reference to drawings. 
         [0051]    The first address supply unit  367  receives a first write address control signal wt_cs 0 _L, a first read address control signal rd_cs 0 _L, the read address lat_rd, and the delayed write address wl_wt, and provides the first rank address ADD_CS 0  to the first rank  100 . 
         [0052]    The second address supply unit  368  receives a second write address control signal wt_cs 1 _L, a second read address control signal rd_cs 1 _L, the read address lat_rd, and the delayed write address wl_wt, and provides the second rank address ADD_CS 1  to the second rank  200 . 
         [0053]    When providing the latched address to the corresponding ranks, the first and second address supply units  367  and  368  provide the latched address information through different signal paths (ranks) such that the address information of one rank does not collide with that of the other rank. 
         [0054]      FIG. 5  is a circuit diagram of the first address latch  362  of  FIG. 4 . Referring to  FIG. 5 , the first address latch  362  includes a first transmission section TR 1  and a first latch section L 1 . The first transmission section TR 1  receives the address ADD in response to the read combined information signal RD_CS 01 . 
         [0055]    The first latch section L 1  latches the signal received from the first transmission section TR 1 , and includes third and fourth inverters IV 3  and IV 4 . 
         [0056]    The operation of the first address latch  362  will be described as follows. The first address latch  362  latches the address ADD in response to the read combined information signal RD_CS 01 . The read combined information RD_CS 01  includes both of a first rank read command and a second rank read command. Then, when the read command for the first or second rank is provided, the first address latch  362  may latch the address ADD to provide the read address lat_rd. At this time, a separate latency for the read operation is not required. 
         [0057]      FIG. 6  is a circuit diagram of the second address latch  364  of  FIG. 4 . Referring to  FIG. 6 , the second address latch  364  includes a second transmission section TR 2  and a second latch section L 2 . 
         [0058]    The second transmission section TR 2  receives the address ADD in response to the write combined information signal WT_CS 01 . 
         [0059]    The second latch section L 2  latches the signal received from the second transmission section TR 2 , and includes seventh and eighth inverters IV 7  and IV 8 . 
         [0060]    The operation principle of the second address latch  364  is similar to that of the first address latch  364 . Therefore, the descriptions thereof will be omitted to avoid the duplication. However, when the write command for the first or second rank is provided, the second address latch  364  may latch the address ADD to provide the write address lat_wt. 
         [0061]      FIG. 7  is a circuit diagram of the shift register  366  of  FIG. 4 . Referring to  FIG. 7 , the shift register  366  includes a plurality of transmission sections T 1 , T 2 , T 3  and t 4 . Each of the transmission sections T 1 , T 2 , T 3  and T 4  includes a transmission gate TG and a latch L. 
         [0062]    The first transmission section T 1  receives the write address lat_wt in synchronization with a rising edge of the clock signal CLK, and transmits the received write address lat_wt. The transmission gate TG is turned on in response to a high level of the clock signal CLK. The latch L latches the signal transmitted from the transmission gate TG. 
         [0063]    The second transmission section T 2  receives the signal from the first transmission section T 1  in synchronization with a falling edge of the clock signal CLK, and transmits the received signal. The transmission gate TG is turned on in response to a low level of the clock signal CLK. The latch L latches the signal transmitted from the transmission gate TG. 
         [0064]    As such, the respective transmission sections T 1 , T 2 , T 3  and T 4  are alternately turned on in response to the clock signal CLK. Then, when the first and third transmission sections T 1  and T 3  or the second and fourth transmission sections T 2  and T 4  are turned on to transmit a signal, each pair of a turned-on transmission section and a turned-off transmission section has a delay time corresponding to one clock period. 
         [0065]    Meanwhile, the shift register  366  further includes pass gates PASS and inverters INV 1 , INV 2 , INV 3 , . . . . The pass gate PASS receives the write latency WL&lt; 1 : 4 &gt; through the inverters INV 2 , INV 3 , . . . . 
         [0066]    The shift register  366  receives the write address lat_wt, delays the write address lat_wt by the write latency WL&lt; 1 : 4 &gt;, and provides the delayed write address wl_wt. Accordingly, it is possible to provide the delayed write address wl_wt to which the necessary write latency is applied, in the write mode. 
         [0067]    The operation of the shift register  366  may be described more specifically as follows. When the write latency WL&lt; 1 : 4 &gt; is 1, the first write latency WL&lt; 1 &gt; is activated to a high level. Therefore, the pass gate PASS receiving the activated first write latency WL&lt; 1 &gt; is turned on to provide an output signal of the second transmission section T 2  as the delayed write address wl_wt. That is, when a signal passes through the first and second transmission sections T 1  and T 2  or the third and fourth transmission sections T 3  and T 4 , the delay time corresponding to one clock period is provided. Therefore, when the write latency is 1, an address signal delayed by one clock period may be provided. 
         [0068]      FIG. 8  is a circuit diagram of the first address supply unit  367  of  FIG. 4 . 
         [0069]    Referring to  FIG. 8 , the first address supply unit  367  includes a first transmission section TR 10 , a second transmission section TR 11 , and a latch section LAT. 
         [0070]    The first transmission section TR 10  provides the read address lat_rd in response to the activated first read information signal rd_cs 0 _L. 
         [0071]    The second transmission section TR 11  provides the delayed write address wl_wt in response to the activated first write information signal wt_cs 0 _L. As described above, the delayed write address wl_wt is a signal to which the write latency WL is applied, and the first write information signal wt_cs 0 _L is a signal to which the write latency WL and the burst length BL are applied. 
         [0072]    The latch section LAT includes third and fourth inverters  13  and  14 . The latch section LAT receives the signal from the first and second transmission sections TR 10  and TR 11 , and latches the received signal to provide as the first rank address ADD_CS 0 . 
         [0073]    More specifically, the first address supply unit  367  provides the corresponding address as the first rank address ADD_CS 0  in response to the read information and write information on the first rank. That is, the first address supply unit  367  provides the read address lat_rd as the first rank read ADD_CS 0  in response to the activated first rank read address information signal rd_cs 0 _L. Similarly, when the first write information signal wt_cs 0 _L is activated, the first address supply unit  367  provides the write address lat_wt as the first rank address ADD_CS 0 . 
         [0074]    The configuration and operation principle of the second address supply unit  368  are similar to those of the first address supply unit  367 . Therefore, the descriptions thereof will be omitted. 
         [0075]    According to the embodiment, when an address is provided to a corresponding rank while the address is latched by the combined read information or write information, the address is transmitted in response to the read information or write information of each rank. Accordingly, individual control units are not provided for each rank, but rather only one control unit is shared by all of the ranks, which makes it possible to realize improves in the area efficiency. A read or write command has a separated signal path such that different ranks can be selected. An address is latched regardless of the rank information and then controlled by read and write signals having rank information at a timing at which the read or write operation of the corresponding rank is performed. Therefore, the address can be provided only to the corresponding rank. 
         [0076]      FIG. 9  is a voltage waveform diagram showing the operation of the semiconductor circuit apparatus of  FIG. 1  according to the embodiment. 
         [0077]    Referring to  FIGS. 1 to 9 , the operation of the semiconductor circuit apparatus according to the embodiment will be described. 
         [0078]    At a time interval t 0 -t 1 , a command WT_R 0  for performing the write mode of the first rank  100  is inputted. 
         [0079]    In response to the command WT_R 0 , the write combined information signal WT_CS 01  is activated. At this time, the pulse width of the write combined information signal WT_CS 01  is ½ tCK. The address ADD is latched in response to the write combined information signal WT_CS 01  to provide the write address lat_wt. 
         [0080]    At a time interval t 1 -t 2 , a command RD_R 1  for performing the read mode of the second rank  200  is inputted. 
         [0081]    An inter-rank operation spec regulation is 1 tCK. Therefore, although the read command RD_R 1  of the second rank  200  is inputted in one clock period after the write command WT_R 0  of the first rank  100  is inputted, the operation can be performed. 
         [0082]    In response to the read command, the read combined information signal RD_CS 01  is activated. The address ADD is latched in response to the read combined information signal RD_CS 01  to provide the read address lat_rd. Furthermore, since the latency is not necessary in the read mode, the read address lat_rd may be provided as the second rank address ADD_CS 1  without delay. 
         [0083]    Meanwhile, data is delayed by the write latency WL in response to the write command WT_R 0  of the first rank  100 , and then inputted from time t 2 . 
         [0084]    At a time interval t 3 -t 4 , a command RD_R 1  for performing the read mode of the second rank  200  is inputted. Since a column command input time in the same rank is defined as 2 tCK, the command input is suitable. Accordingly, the read combined information signal RD_CS 01  is activated. In response to the read combined information signal RD_CS 01 , a newly-received address ADD is latched as the read address lat_rd. In response to the second rank read address signal rd_cs 1 _L to which latency does not need to be applied, the latched read address lat_rd is provided as the second rank address ADD_CS 1 . 
         [0085]    At a time interval t 4 -t 5 , the first write information signal wt_cs 0 _L is delayed by the write latency WL and the burst length BL in response to the first rank write command WT_R 0 , and then activated. As described above, the first write information signal wt_cs 0 _L is activated after a predetermined time is delayed, so that the internal circuit operation of the first rank  100  is substantially performed at a timing at which the input of data is terminated in response to the write command. 
         [0086]    Therefore, the latched write address lat_wt is provided as the first rank address signal ADD_CS 0  in response to the activated first write information signal wt_cs 0 _L. 
         [0087]    After time t 5 , the data is outputted after a predetermined CAS latency of the first read operation. Here, the CAS latency may be set to 4. 
         [0088]    Signals capable of strobing the addresses of the respective ranks may be referred to as a first strobe signal rd/wt_strobe_cs 0  and a second strobe signal rd/wt_strobe_cs 1 . The strobe signals may be activated in response to the first write address information signal wt_cs 0 _L and the second read address information signal rd_cs 1 _L, respectively. Therefore, it can be seen that an address signal fetched by the second strobe signal rd/wt_strobe_cs 1  of the second read operation of the second rank does not collide with an address signal fetched by the first strobe signal rd/wt_strobe_cs 0  of the write operation of the first rank (refer to a dotted circle of  FIG. 9 ). In other words, although the rank control unit  300  is shared, it is possible to satisfy the inter-rank column operation spec regulation (1tCK). 
         [0089]    According to the embodiment, the control unit shared by the plurality of ranks is provided, and a suitable latency is applied to selectively provide an address signal to the corresponding rank at a timing at which the internal circuit operation is substantially required in a state in which an address is latched at the same time when a column command is inputted. Therefore, while the inter-rank spec regulation is satisfied, the area efficiency can be improved. 
         [0090]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor circuit apparatus described herein should not be limited based on the described embodiments. Rather, the semiconductor circuit apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.