Abstract:
An exponential function generator embodied by a CMOS process and a variable gain amplifier (VGA) employing the same. Since it is difficult for CMOS devices to attain an exponential function by themselves, the exponential function generator employs a scheme of generating two voltage signals varying with different slopes for a control voltage and summing up the two voltage signals so as to obtain an approximated exponential function. Further, the VGA is designed capable of being implemented by the CMOS process and performs only fixed gain amplification at an input stage by considering the deterioration of features of CMOS devices, linearly changes the gain by providing an exponential control current to a variable gain cell performing the practical gain variation for its bias control, and constructs a load by using FETs operating in an ohmic region to perform a stabilized operation regardless of variations in external factors.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor circuit technology and, more particularly, to an exponential function generator and a variable gain amplifier (VGA) employing the same.  
         DESCRIPTION OF RELATED ART  
         [0002]    In a wireless communication system, a receiver may receive a signal that experiences wide variations in signal power. In receivers such as are used in a wideband digital code division multiple access (CDMA) mobile station, it is necessary to control the power of the demodulated signal for proper signal processing. Moreover, in transmitters such as are used in a CDMA mobile station, it is indispensable to control the transmit power in order to avoid excessive interference to other mobile stations. These same power control considerations apply to narrowband analog frequency modulation (FM) wireless communication system transmitters and receivers.  
           [0003]    Dual-mode CDMA/FM wireless communications systems should provide power control of transmitted and received signals of both digital CDMA and analog FM modulation. In these dual-mode mobile stations, the control process is complicated by the differing dynamic ranges and industry regulation standards associated with the CDMA and FM signals. Therefore, the provision of separate automatic gain control (AGC) circuitry for both the CDMA and the FM signals increases the complexity and expense of such dual-mode mobile stations. Accordingly, it is desired to provide AGC circuitry capable of operating upon both the CDMA and FM signals.  
           [0004]    A variable gain amplifier (VGA), which is one of the AGC circuits, provides a gain in proportion to a control voltage. The VGA provides an exponential voltage gain as a function of linear increases in the applied control voltage thereby providing an approximately linear power gain in decibels (dB) in direct proportion to linear increases in the applied control voltage. The VGA can be used in many applications including receivers and transmitters.  
           [0005]    Referring to FIG. 1, there is shown a block diagram of a conventional variable gain amplifier (VGA)  100  included in a receiver of a dual-mode CDMA/FM mobile station, which is found in U.S. Pat. No. 5,880,631, entitled “HIGH DYNAMIC RANGE VARIABLE GAIN AMPLIFIER” issued Mar. 9, 1999, and briefly summarized herein as representative of the prior art.  
           [0006]    As shown in FIG. 1, the VGA  100  comprises an input stage  120  and two cascaded current amplifiers  160 A and  160 B. The current amplifiers  160 A and  160 B are successively cascaded to increase the dynamic range of the VGA  100  and the number of current amplifiers can be adjusted, as necessity requires.  
           [0007]    The input stage  120  includes a separate FM input stage  121  and CDMA input stage  122  with respective input ports  171  and  170 . The FM input stage  121  and the CDMA input stage  122  are alternately connected to the current amplifier  160 A through switches  123 , which are controlled by a CDMA/FM mode select signal.  
           [0008]    The VGA  100  also employs bias ports  110 ,  130 ,  150 A and  150 B for control voltages to be applied to the VGA  100 . The gain of each stage is controlled by control voltages, which, for example, may be generated by receiver detection circuitry that determines the signal strength. Each stage is comprised of a variety of components, including an active device such as a transistor.  
           [0009]    Since it operates with a low supply voltage, about 3.6 V, the input stage  120  converts an input voltage signal to a current signal to prevent the VGA active devices from operating in their non-linear region, and distorting the input signal.  
           [0010]    Meanwhile, FIG. 1 provides the bias port  130  coupled to a transconductance bias control circuit  140 , which will be described later.  
           [0011]    Referring to FIG. 2, there is shown a diagram of the CDMA input stage  122  of FIG. 1, which includes a Gilbert cell attenuator  226  and a variable transconductance amplifier  227  and serves four functions.  
           [0012]    First, the variable transconductance amplifier  227  converts the input voltage signal to a current signal. Second, the combination of the variable transconductance amplifier  227  and the Gilbert cell attenuator  226  permits variable amplification of the signal, which may be varied exponentially by linearly adjusting control voltages at the bias port  110 . Third, increased emitter degeneration in the variable transconductance amplifier  227  reduces the intermodulation distortion (IMD) of the VGA  100  when the input voltage signal is large and the IMD would be most prominent. That is, as the emitter degeneration in the variable transconductance amplifier  227  is increased, the transconductance, and thus the IMD, of the CDMA input stage  122  is decreased. Fourth, decreased emitter degeneration in the variable transconductance amplifier  227  improves the noise feature of the VGA  100  when the input voltage signal is small and noise performance is the most critical. Namely, as the emitter degeneration in the variable transconductance amplifier  227  is decreased, the transconductance of the CDMA input stage  122  is increased, improving the noise feature of the receiver.  
           [0013]    The variable transconductance amplifier  227  is comprised of two bipolar junction transistors (BJTs)  235  and  236 , two current sources  238  and  239 , and a field effect transistor (FET)  237 . The current sources  238  and  239  are serially connected to the emitters of the BJTs  235  and  236 , respectively. The source connection  228  and drain connection  229  of the FET  237  are respectively connected to the emitters of the BJTs  235  and  236 . The balanced signal at the VGA input port  170  is applied to the bases of the BJTs  235  and  236 . The balanced current output of the variable transconductance amplifier  227  flows from the collectors of the BJTs  235  and  236 .  
           [0014]    The transconductance of the variable transconductance amplifier  227  may be adjusted by varying the emitter degeneration of the BJTs  235  and  236 . As a result, the gain of the VGA  100  may be varied. The emitter degeneration of the BJTs  235  and  236  is created by varying the channel resistance of the FET  237 . The FET  237  is operated like a variable resistor in its ohmic region and provides variable emitter degeneration for both of the BJTs  235  and  236 . The drain-source bias voltage of the FET  237  must therefore be less than the knee voltage of the FET  237 . The channel resistance may be varied by adjusting the bias across the gate-source junction of the FET  237  by varying the voltage applied at a bias port  124 . The transconductance of the variable transconductance amplifier  227  can be increased by decreasing the channel resistance of the FET  237 .  
           [0015]    The differential output currents of the variable transconductance amplifier  227  are coupled to the Gilbert cell attenuator  226 . The Gilbert cell attenuator  226  varies the current amplitude of a signal applied to its inputs. The Gilbert cell attenuator  226  contains a first pair of BJTs  231  and  234 , and a second pair of BJTs  232  and  233 . The attenuation level of the Gilbert cell attenuator  226  is established by a control voltage applied at the bias port  110 .  
           [0016]    The Gilbert cell attenuator  226  attenuates the output current of the variable transconductance amplifier  227  when the first pair of BJTs  231  and  234  are biased by the control voltage applied to the bias port  110  so that a component of the variable transconductance amplifier&#39;s output current flows through the first pair of BJTs  231  and  234  rather than through the second pair of BJTs  232  and  233 . Hence the balanced currents at an output port  190  of the Gilbert cell attenuator  226  are diminished.  
           [0017]    The configuration of the FM input stage  121  is similar to that of the CDMA input stage  122  described in FIG. 2 except that the FET  237  is replaced by a fixed resistance. As previously mentioned, the fixed resistance of the FM input stage  121  provides a fixed transconductance because industry standards, such as IS-95, allow compression of the input signal at a much lower input level than that of the CDMA input signal.  
           [0018]    Referring to FIG. 3, there is provided a diagram of the transconductance bias control circuit  140  of FIG. 1.  
           [0019]    As shown in FIG. 3, the transconductance bias control circuit  140  includes an exponential function generator  360 , a first and a second operational amplifier circuit  353  and  354 , a low pass filter  352  and a current source  341 .  
           [0020]    The exponential function generator  360  converts the control voltage applied at the bias port  130  to two output currents flowing from an output node  358  of the exponential function generator  360  to the first operational amplifier circuit  353 . The ratio of the amplitudes of these currents is exponentially proportional to the control voltage.  
           [0021]    Referring to FIG. 4, there is illustrated a diagram of the exponential function generator  360 , which comprises a differential amplifier  465  provided with the control voltage at the bias port  130  and a pair of FET current mirrors  474  driven by outputs of the differential amplifier  465 . The differential amplifier  465  includes a parallel pair of BJTs  461  and  462  whose bases are connected to the bias port  130  and a current source  472  connected to the pair of BJTs  461  and  462 . The pair of FET current mirrors  474  includes four FETs  464 ,  466 ,  468  and  470 . Due to an exponential input voltage-output current relationship of the BJTs  461  and  462 , the ratio of their collector currents is proportional to the differential base voltage between the BJTs  461  and  462 , which is determined by the control voltage signal. Thus, the linear differential voltage change across the bias port  130  is translated to an exponentially related current at the output node  358 . The current mirrors  474  simply take the exponentially related current generated by the pair of BJTs  461  and  462  and provide it for use throughout the differential amplifier  465 .  
           [0022]    Referring back to FIG. 3, the first and the second operational amplifier circuits  353  and  354  act in cooperation with the exponential function generator  360  to control the channel resistance of the FET  237  of FIG. 2. The first operational amplifier circuit  353  employs a master FET  344 , which is preferably identical to the FET  237 , a reference resistor  346  and a differential operational amplifier  348 . The output currents from the exponential function generator  360  are coupled to the master FET  344  and the reference resistor  346 . The differential operational amplifier  348  forces the voltage across the drain and source terminals of the master FET  344  and the terminals of the reference resistor  346  to be equal by varying the bias voltage applied to the gate of the master FET  344 . The bias voltages applied to the gates of the FET  237  and the master FET  344  are generally equal. However, the gate bias voltage applied to the FET  237  through the bias port  124  is low pass filtered to prevent thermal noise from the transconductance bias control circuit  140  from being injected onto the FET  237 . The low pass filtering is accomplished by a low pass filter  352  formed by series resistor  350  and shunt capacitor  351 .  
           [0023]    The second operational amplifier  354  includes a non-inverting, unity gain operational amplifier  349  and resistors  345  and  347 , that sense the drain-source voltage across the FET  237  via the source connection  228  and the drain connection  229 . The second operational amplifier circuit  354  forces the master FET  344  and the FET  237  to have the same source voltage.  
           [0024]    The exponential function generator  360  and the current source  341  connected around the master FET  344  and the reference resistor  346  are designed so that the voltage drop across the reference resistor  346 , and hence across the drain-source of the master FET  344 , is less than the FET&#39;s knee voltage. As a result, the operation of the first and the second operational amplifier circuits  353  and  354  force the FET  237  and the master FET  344  to operate at similar quiescent points in their ohmic regions. Therefore, the channel resistances of both of the FET  237  and the master FET  344  are generally identical and vary exponentially with a linearly adjusted control voltage applied to the bias port  130 .  
           [0025]    Referring to FIG. 5, there is illustrated a diagram of the current amplifiers  160 A and  160 B of FIG. 1. The input of the current amplifier  160  as shown in FIG. 5 may be coupled to the output of the input stage  120  or the output of another current amplifier. The current amplifier  160  comprises a Darlington differential amplifier  510 , a cascode differential amplifier  520  and a tail current generator  570 . The current amplifier  160  is biased by power supplies and current sources  596  and  598 .  
           [0026]    The Darlington differential amplifier  510  includes BJTs  580 ,  586 ,  588  and  594  and resistors  582 ,  584 ,  590  and  592  in the topology shown in FIG. 5 such that the Darlington differential amplifier  510  has a resistive shunt-series feedback to provide an enhanced current gain and process variation insensitivity.  
           [0027]    The cascode differential amplifier  520  includes BJTs  500 ,  502 ,  504  and  506  in the topology of a differential current mirror, which allows the gain of the current amplifier  160  to be varied by varying tail currents. The cascode differential amplifier  520  provides a translinear loop, which provides variable current amplification according to the ratio of the tail currents generated by the tail current generator  570 .  
           [0028]    The gain of the current amplifier  160  is controlled by the tail current generator  570 . The tail current generator  570 , through a differential port, is connected to both of the Darlington differential amplifier  510  and the cascode differential amplifier  520 . The current amplification of the current amplifier  160  may be varied exponentially by using the control current generated by the exponential function generator  360  of FIG. 4 and applied to the control ports  150 . For reference, the tail current generator  570  includes an exponential function generator and a pair of bipolar current mirrors. Each of the bipolar current mirrors includes a plurality of resistors and a multiplicity of BJTs.  
           [0029]    As described above, since the conventional VGA includes BJTs in each component thereof, it is formed by a BiCMOS manufacturing process. In particular, the exponential function generator having exponentially varying gain can readily convert the control voltage to an exponential current by using features of the BJT device itself. Therefore, the reason why the BiCMOS manufacturing process is used instead of a CMOS manufacturing process, even though the CMOS process can achieve low cost of production and high integration, is that it is difficult to implement an appropriate exponential function although a device of a large size is used since the transconductance of a CMOS device is very small and, thus, BJT&#39;s are inevitably used. Further, it is difficult to attain BJT features of acting amplification through the use of the CMOS manufacturing process.  
           [0030]    Meanwhile, the exponential function generator is widely applied to other analog systems in addition to the before-mentioned VGA and, therefore, it is required to form the exponential function generator by using the CMOS manufacturing process.  
         SUMMARY OF THE INVENTION  
         [0031]    It is, therefore, a primary object of the present invention to provide an exponential function generator capable of attaining an appropriate exponential function through the use of a CMOS manufacturing process.  
           [0032]    Another object of the present invention is to provide a variable gain amplifier employing the exponential function generator, which can be implemented by a CMOS manufacturing process.  
           [0033]    In accordance with one aspect of the present invention, there is provided an exponential function generator comprising a first and a second curve generator for producing signals varying with different slopes by sampling an inputted control voltage; and an adder for summing up the signals outputted from the first and the second curve generators to thereby output a voltage signal having an approximated exponential function value.  
           [0034]    In accordance with another aspect of the present invention, there is provided a variable gain amplifier embodied by a CMOS process, comprising an input stage for amplifying differential input signals to thereby output voltage signals having a limited fixed gain value; an exponential function generator including a first and a second curve generator which produce signals varying with different slopes by sampling an inputted control voltage, and summing up the signals outputted from the first and the second curve generators to thereby output a signal having an approximated exponential function value; a control current generator for producing an exponential control current in response to the output signal of the exponential function generator; and a variable voltage amplifier for performing variable gain amplification of the voltage signal outputted from the input stage in response to the exponential control current.  
           [0035]    In accordance with the present invention, the exponential function generator is implemented by using a CMOS manufacturing process. Since it is difficult for CMOS devices to attain an exponential function by themselves, the present invention employs a scheme of generating two voltage signals varying with different slopes for a control voltage and summing up the two voltage signals so as to obtain an approximated exponential function. Meanwhile, in accordance with the present invention, the VGA including the inventive exponential function generator is designed capable of being implemented by employing the CMOS manufacturing process. That is, the present invention performs only fixed gain amplification at an input stage by considering the deterioration of features of CMOS devices, linearly changes the gain by providing an exponential control current to a variable gain cell, e.g., a differential voltage amplifier, performing the practical gain variation for the bias control of the variable gain cell, and constructs a load by using FETs operating in an ohmic region to perform a stabilized operation regardless of variations in external factors such as temperature, manufacturing processes and so on. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0036]    The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0037]    [0037]FIG. 1 shows a block diagram of a conventional variable gain amplifier included in a receiver of a dual-mode CDMA/FM mobile station;  
         [0038]    [0038]FIG. 2 provides a circuit diagram of the CDMA input stage of FIG. 1;  
         [0039]    [0039]FIG. 3 describes a circuit diagram of the transconductance bias control circuit of FIG. 1;  
         [0040]    [0040]FIG. 4 is a circuit diagram of the exponential function generator of FIG. 3;  
         [0041]    [0041]FIG. 5 illustrates a circuit diagram of the current amplifier of FIG. 1;  
         [0042]    [0042]FIG. 6 represents a block diagram of a variable gain amplifier in accordance with the present invention;  
         [0043]    [0043]FIG. 7 depicts a block diagram of the exponential function generator of FIG. 6;  
         [0044]    [0044]FIG. 8 is a circuit diagram of the exponential function generator of FIG. 6;  
         [0045]    [0045]FIG. 9 shows a circuit diagram of the control current generator of FIG. 6; and  
         [0046]    [0046]FIG. 10 describes a diagram of the variable gain cell of FIG. 6. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0047]    Hereinafter, some preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.  
         [0048]    Referring to FIG. 6, there is illustrated a block diagram of a variable gain amplifier (VGA)  700  in accordance with an embodiment of the present invention.  
         [0049]    The VGA  700  comprises an input stage  710 , an exponential function generator  720 , a control current generator  730  and two variable gain cells  740 A and  740 B.  
         [0050]    The input stage  710  includes an FM input stage  712  operating in an FM mode, a CDMA input stage  714  operating in a CDMA mode and switches  716  for alternately connecting the FM input stage  712  and the CDMA input stage  714  to the variable gain cell  740 A under the control of an CDMA/FM mode select signal. Herein, the FM input stage  712  and the CDMA input stage  714  are implemented as differential amplifiers made by a CMOS manufacturing process and perform fixed gain amplification to a degree that will not degrade the noise feature and the distortion feature of an inputted FM/CDMA signal. The fixed gain amplification is performed by considering coarse transconductance of a CMOS device. The differential amplifier made by the CMOS manufacturing process is a well-known circuit and, therefore, detailed explanation of the configuration and operation of the differential amplifier will be omitted.  
         [0051]    The variable gain cells  740 A and  740 B in which a gain is practically varied are constructed by a kind of voltage amplifier whose input and output are voltage signals. The variable gain cells  740 A and  740 B are also embodied by the CMOS manufacturing process and their gains are varied by a semi-exponential control current I ctrl .  
         [0052]    The exponential function generator  720  converts a control voltage V ctrl  to an exponential function and is also implemented by the CMOS manufacturing process.  
         [0053]    The control current generator  730  is provided with an exponential voltage V c  outputted from the exponential function generator  720  to thereby produce the control current I ctrl , and is implemented by the CMOS manufacturing process.  
         [0054]    Referring to FIG. 7, there is depicted a block diagram of the exponential function generator  720  of FIG. 6.  
         [0055]    The exponential function generator  720  includes a first and a second curve generator  810  and  820  and an adder  830  for summing up the output voltages from the curve generators  810  and  820 . The first and the second curve generators  810  and  820  produce voltage signals varying with different slopes for the control voltage V ctrl , and the adder  830  employs a scheme of summing up the voltage signals outputted from the first and the second curve generators  810  and  820  to thereby produce an approximated exponential function, considering CMOS features.  
         [0056]    Referring to FIG. 8, there is shown a circuit diagram of the exponential function generator  720  of FIG. 6.  
         [0057]    The first curve generator  810  includes a level shifter  812  for changing the level of the control voltage V ctrl , a V-I converter  814  for converting an output voltage from the level shifter  812  to a current, and a current mirror  816 .  
         [0058]    The level shifter  812  contains a resistor R 1  connected between the control voltage V ctrl  and an output node V N1  and a resistor R 2  connected between a reference voltage V ref  and the output node V N1 .  
         [0059]    The current mirror  816  includes two current sources  818  and  819  connected in parallel to a supply voltage V dd .  
         [0060]    The V-I converter  814  has an operational amplifier  817  receiving the output voltage V N1  of the level shifter  812  as its positive input, an FET M 1  whose gate is supplied with an output of the operational amplifier  817 , and a resistor R 3  connected between a drain of the FET M 1  and a ground voltage node. The drain of the FET M 1  is also attached to a negative input node of the operational amplifier  817  and a source of the FET M 1  is connected to the current source  818 .  
         [0061]    In the meantime, the second curve generator  820  has a symmetric configuration with that of the first curve generator  810  except it employs a parasitic PNP BJT Q 1 . Since the parasitic PNP BJT Q 1  does not perform the amplification and, thus, does not require superior features, it can be easily embodied by the CMOS manufacturing process.  
         [0062]    The adder  830  adds an output of the current source  819  to an output of a corresponding current source of the second curve generator  820  to thereby output the exponential voltage V c  and employs an output resistor R connected between the exponential voltage V c  node and the ground voltage node.  
         [0063]    As illustrated above, in the exponential function generator  720 , a current I 1  flowing through the resistor R 3  of the first curve generator  810  can be represented as V N1 /R 3 . On the other hand, a current  12  flowing through a resistor R 6  of the second curve generator  820  becomes a non-linear function for the control signal V ctrl  by the parasitic PNP BJT Q 1  connected between the resistor R 6  and the ground voltage node. The parasitic PNP BJT Q 1  does not operate until the level shifter output voltage V N2  of the second curve generator  820  is over a threshold voltage. The parasitic PNP BJT Q 1  has a very small turn-on resistance because of its diode feature. Therefore, the current I 2  is approximated to V N2 /R 6 .  
         [0064]    Meanwhile, the output voltage V c  of the exponential function generator  720  can be represented as (I 1 +I 2 )×R, which has an independent semi-exponential value of external factors such as temperature, manufacturing processes and so on by sampling the control voltage V ctrl  to respective different values according to a resistance ratio of the first and the second curve generators  810  and  820 .  
         [0065]    In FIG. 9, there is shown a circuit diagram of the control current generator  730  of FIG. 6, which is implemented by the CMOS manufacturing process.  
         [0066]    The control current generator  730  includes a FET M 3  whose gate is provided with the exponential voltage V c  outputted from the exponential function generator  720  and two FETs M 100  and M 101  constructing a current mirror. A current flowing through the FET M 100  varies depending on the exponential voltage V c  coupled to the FET M 3  and a current mirrored to the FET M 101  is varied and outputted as a control current I ctrl ′.  
         [0067]    Referring to FIG. 10, there is described a circuit diagram of the variable gain cells  740 A and  740 B of FIG. 6, which are also constructed by the CMOS manufacturing process.  
         [0068]    The variable gain cell  740  has a differential amplifier structure including a bias control unit  742 , a voltage input unit  744  and a load unit  746 . The bias control unit  742  uses the control current I ctrl  outputted from the control current generator  730  as a current source and the voltage input unit  744  includes two FETs M 4  and M 5  whose gates are provided with differential input voltages IN+ and IN−, respectively. The load unit  746  contains an effective load part  748 , a common mode feedback (CMFB) circuit  749  and two FETs M 6  and M 7  whose gates are supplied with an output of the CMFB circuit  749 . The effective load part  748  is composed of two resistors R 7  and R 8  connected between drains of the FETs M 6  and M 7 , and two FETs M 8  and M 9 . A node between the two resistors R 7  and R 8  is connected to an input node of the CMFB circuit  749  and a node between the FETs M 8  and M 9  is attached to a second constant voltage V CM2 . Further, gates of the FETs M 8  and M 9  are commonly connected to the supply voltage V dd . In this drawing, OUT+ and OUT− represent differential output voltages.  
         [0069]    For reference, the CMFB circuit  749  uses a first and the second constant voltage V CM1  and V CM2  for the bias; receives a voltage at the node between the two resistors R 7  and R 8  of the effective load part  748 , wherein, practically, the resistors R 7  and R 8  have the same resistance; compares the received voltage with the first constant voltage V CM1 ; and controls the operation of the FETs M 6  and M 7  connected to its output node according to the comparison result to thereby allow the node between the resistors R 7  and R 8  whose voltage is represented as [(Vout+)+(Vout−)]/2 to maintain the first constant voltage V CM1 . That is, according to the operation of the CMFB circuit  749 , the node between two resistors R 7  and R 8  maintains its state like an AC ground state.  
         [0070]    In the variable gain cell  740  configured as described above, if the FETs M 4  and M 5  of the voltage input unit  744  are allowed to operate in their saturation regions, a voltage gain of the variable gain cell  740  can be represented as the product of a transconductance value gm of the FETs M 4  and M 5  and an effective resistance R eff  of the effective load part  748 . The voltage gain Av of the variable gain cell  740  is described in an equation, EQ. 1.  
                   Av   =       gm   M4     ·     R   eff                   =           I   ctrl     ·     μ   n                Cox        (     W   /   L     )       M4     ·     R   eff                                         EQ   .              1                               
 
         [0071]    Herein, gm M4  represents the transconductance of the FET M 4 ; μ n  depicts mobility of an NMOS transistor; Cox is capacitance of a gate oxide film of the FET M 4 ; and (W/L) M4  means a ratio of a channel width W to a channel length L of the FET M 4 .  
         [0072]    Meanwhile, the effective resistance R eff  is shown in an equation, EQ. 2.  
                     R   eff     =         R     0   ,   M6       //   R7     //     R     ds   ,   M8                     =       R     ds   ,   M8   ,       (         R     ds   ,   M8            〈     〈     R7        〈     〈     R     0   ,   M6                   )                   =     1       μ   n            Cox        (     W   /   L     )       M8          (       V   dd     -     V   CM2     -     V   TN       )                       EQ   .              2                               
 
         [0073]    In EQ. 2, R 0,M6  means an output resistance of the FET M 6 ; R ds,M8  is a drain-source resistance of the FET M 8 ; and V TN  represents a threshold voltage of an NMOS transistor. Therefore, the equation EQ. 1 can be modified to an equation, EQ. 3.  
             Av   =             I   ctrl     ·     μ   n              Cox        (     W   /   L     )       M4             μ   n            Cox        (     W   /   L     )       M8          (       V   dd     -     V   CM2     -     V   TN                     EQ   .              3                               
 
         [0074]    At this time, since the transconductance value gm is described in a square root, the voltage gain Av of the variable gain cell  740  cannot have linearity. Accordingly, the control current I ctrl  is produced by processing the exponential voltage V c  generated from the exponential function generator  720  at the control current generator  730  in order to linearize the voltage gain Av. Namely, if the FET M 3  of the control current generator  730  is designed to operate in a saturation region for a sufficiently wide input voltage range, a square law current of the FET M 3  is generated and the output current I ctrl ′ of the control current generator  730  can be described as shown in an equation, EQ. 4, since the input of control current generator  730  is the exponential voltage V c .  
               I   ctrl   ′     =       1   2          μ   n            Cox        (     W   /   L     )       M3            (       V   c     -     V   TN       )     2               EQ   .              4                               
 
         [0075]    In the meantime, when using the current I ctrl ′ as the bias control current I ctrl  of the variable gain cell  740  through the use of a current mirror, the voltage gain Av of the variable gain cell  740  is rearranged as described in an equation, EQ. 5.  
                   Av   =           μ   n          Cox        (       V   c     -     V   TN       )             μ   n          Cox        (       V   dd     -     V   CM2     -     V   IN       )           ·         1   2     ·           (     W   /   L     )     M3            (     W   /   L     )     M4             (     W   /   L     )     M8            (     W   /   L     )     M8                           =           1   2     ·           (     W   /   L     )     M3            (     W   /   L     )     M4             (     W   /   L     )     M8            (     W   /   L     )     M8             ·       (       V   c     -     V   TN       )       (       V   dd     -     V   CM2     -     V   TN       )                       EQ   .              5                               
 
         [0076]    Herein, the FET M 8  should operate in its ohmic region so as to maintain its stabilized operation regardless of variations in the external factors such as manufacturing processes, temperature and so on, and the drain-source voltage of the FET M 8  should be minimized to obtain superior linearity. Since the voltage difference of the first and the second constant voltages V CM1  and V CM2 , which are used in constructing the CMFB circuit  749 , becomes the drain-source voltage of the FET M 8 , it is possible to adjust the linearity.  
         [0077]    If the FETs M 4  and M 5  are allowed to operate in their saturation regions, their noise features are also improved and the voltage gain of the variable gain cell  740  shows an independent value of the external factors such as the temperature and the manufacturing process. Meanwhile, it is not necessarily required that the gate voltage of the FET M 8  be the supply voltage V dd  and its value is determined to allow the FET M 8  to operate in the ohmic region.  
         [0078]    In accordance with the above embodiment, there is exemplified the exponential function generator applied to the VGA. However, the present invention is applicable to the case in which the exponential function generator is used in other analog systems.  
         [0079]    In accordance with the present invention, since the exponential function generator is implemented by the CMOS manufacturing process, it is possible to reduce the cost of production and increase the integration. Further, although the inventive exponential function generator and the VGA using the same are made through the use of the CMOS manufacturing process, they are independent of variations in the external factors such as the temperature and the manufacturing process, and their productivity becomes superior. Moreover, since the inventive VGA uses the control current I ctrl  as the bias current source of the variable gain cell, there is obtained an advantage of reducing the current consumption by using the current variation according to the gain.  
         [0080]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.