Abstract:
A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed.

Description:
FIELD OF INVENTION 
       [0001]    This application is related to collection of memory traffic traces using a trace buffer mechanism. 
       BACKGROUND 
       [0002]    Modern processors, such as, for example, central processing unit (CPU) chips, often contain multiple processing cores, multiple levels of cache hierarchy and complex interfaces between many different blocks of logic. Attempting to debug failures in this environment may be very difficult and time consuming. Often scan dumps, which provide an instantaneous view of the state of the processor, may provide some insight as to the cause of a failure when one is detected. However, many times, the events that cause the failure actually occur much earlier than (prior to) the point at which the failure is detected and the state is captured. As a result, the processor state captured via scan at the time of detection contains little or no useful information regarding the cause of the failure. 
         [0003]    An additional tool to help debug failures is a trace capture buffer (TCB) that keeps track of the sequence of memory references that the processor makes. The TCB may record a limited sequence of transactions arriving at the memory system. This buffer may either be written in a loop where older transactions are replaced by new ones when the buffer is full, or the processor may be paused and the buffer written to DRAM memory to extend its storage capability. 
         [0004]    Even with the TCB, there are limits to the debug information that may be captured. For example, cache memory (e.g., the L3 cache), which is located between the processing cores and the memory system, may complete some core requests autonomously without generating any transactions to the memory system. As a result, these operations, which may be important for debugging a particular failure, do not reach the TCB and are unobservable. 
       SUMMARY OF EMBODIMENTS 
       [0005]    A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in the TCB for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. 
         [0006]    In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a trace capture buffer (TCB), providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0007]    A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings wherein: 
           [0008]      FIG. 1  shows an example of a multi-core processor configured to implement an embodiment the invention; 
           [0009]      FIG. 2  shows an example of the L3 cache of the processor in  FIG. 1 ; and 
           [0010]      FIG. 3  shows an example trace controller of the L3 cache of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0011]    While the examples herein describe specific types of caches (for example, an L3 cache) and devices associated with caches (L3 controller, etc.), embodiments of this invention applies to any type of cache and devices associated with caches, wherein there may be multiple caches operating at multiple levels for multiple purposes. The term “memory” as used herein, refers to any type of storage including but not limited to dynamic random access memory, flash memory, disk, or the like. 
         [0012]    A mechanism to provide visibility to transactions (e.g., read requests, write requests, and the like) on the core to a cache interface (e.g., an L3 cache interface) in the TCB for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described below. 
         [0013]      FIG. 1  shows an example of a processor  100  which, in the exemplary embodiment is a multi-core processor ( 100 ) configured to implement an embodiment of the invention. The processor ( 100 ) comprises multiple cores ( 110   a - 110   n ), wherein the cores  110   a - 110   n  are coupled to a cache (for example, an L3 cache ( 120 )). The L3 cache ( 120 ) is connected to a memory system ( 130 ) that includes TCB ( 140 ). 
         [0014]    One or more requests (described more fully below) from the multiple cores ( 110   a - 100   n ) are presented to the L3 controller ( 125 ) which tries to complete them via the L3 cache ( 120 ). Read or write operations look up the L3 tags and if the address is found in an appropriate state for the memory access, the L3 cache provides the data back to the requesting core and the transaction is completed. 
         [0015]    Similarly for victim (wherein a victim is an element that is removed from one cache to be written into a lower level cache), the L3 cache stores the address in the tag array and stores the associated data in the data array. If the set of data determined by the particular tag index into main memory contains no invalid locations, an L3 victim may be generated and forwarded to the memory system ( 130 ). This invention is concerned with propagating these read hits to a cache, and victim writes into the cache, to a memory system where they may be traced (that is, the cache is bypassed). 
         [0016]      FIG. 2  shows an example of the cache (e.g., L3 cache ( 120 )) of the processor ( 100 ) in  FIG. 1 . The L3 cache ( 120 ) includes a controller (for example, L3 controller ( 125 )). The L3 controller ( 210 ) is coupled to a trace controller ( 225 ) and a request queue ( 230 ). The trace controller ( 225 ) is also coupled to the request queue  230 . 
         [0017]    Memory access requests come into the L3 controller ( 210 ) where the trace controller ( 225 ) examines each request to determine if (1) the request matches any of the trigger conditions (e.g., conditions that will trigger tracing). One common example of a trigger is to collect all coherent memory accesses, including reads, writes, clean victims and dirty victims to enable bypassing, and if bypassing is already enabled, either due to triggering by an earlier request or because the TCB enable is active (a TCB indicator or bit is set) and the trace controller ( 225 ) is configured to use it as a trigger, the request is matched against the trace controller filters. The behavior of the trace collection mechanism is very similar to an on-chip logic analyzer which can be programmed to capture events on a bus which meet a set of predefined rules to determine if the request should be bypassed. Once tracing has been triggered and if the request matches the trace controller filter, the request is marked with a “trace enable” bit (or indicator) when it is loaded into the request queue ( 230 ). The L3 controller ( 125 ) normally services each transaction in the request queue by looking up its address in the L3 array and responding with data (data corresponding to the request, i.e., data that satisfies the request) if the state is appropriate. 
         [0018]    For read accesses, an appropriate state includes any of: modified, owned, exclusive or shared. For write accesses, appropriate states include modified or exclusive. If the state is owned or shared, the data may be returned to the cache but an ownership request must be sent to the memory controller before the processor may complete the access. A write access to a cache also returns data. A write is performed as a read-first then modify operation. 
         [0019]    If the L3 controller ( 125 ) needs to victimize a line to make room for the new victim, the L3 cache victim is sent to the memory system ( 130 ). However, if either a read or allocate transaction has been queued with its trace enable bit (or indicator) set, the controller (e.g., L3 controller) accesses the L3 array as usual, and also forwards the request to the memory system ( 130 ) in the same manner it would have, had the request been a read that missed, that is, where the data was not in the cache (for example, the L3 cache ( 120 )) or a write that was marked as non-cacheable. This allows the request tagged with the trace enable bit to be captured in the TCB ( 140 ) in the memory system ( 130 ). 
         [0020]    The trace controller ( 225 ) is shown in more detail in  FIG. 3 . The trace controller ( 225 ) comprises the control register ( 310 ) which controls the operation of the trace controller ( 225 ) including selecting triggers and enabling the filter. The address target register ( 330 ) along with the request mask ( 320 ) are used to provide a filter for incoming requests. Requests which match the specified address(es) and type(s) will generate either triggers and/or cause the trace enable bit or indicator to be set according to the control register ( 310 ) configuration. 
         [0021]    There may be a plurality of different types of transactions that the cache autonomously completes which prevents them from reaching the trace buffer. In one embodiment, there are two transaction types. The first type includes read operations that hit in the L3 cache where the cache provides the data to the core to complete the operations without the participation of the memory system (bypassing the memory system). The second is a victim line from the core&#39;s L2 cache which is written into the L3 cache and again completes the operation without forwarding the transaction to the memory system. Embodiments of this invention make these two types of transactions visible to the TCB by bypassing the L3, thereby treating them as though the read operations were misses (e.g., not cached) and the core victims were non-cacheable. 
         [0022]    In the case of reads, the memory system may probe the system caches as necessary and extract the line from the L3 and return the data to the requesting core. This more circuitous route for the request allows it to be captured in the TCB as it is sent to the memory system, while allowing the processor to maintain coherency, albeit with a longer latency. Similarly, enabling victims to bypass the memory system allows them to be captured in the trace buffer as well. The memory system generates whatever probes of the caches are necessary to maintain coherency and writes the data to dynamic random access memory (DRAM) or similar memory device. In other words, bypassing the cache is transparent at the application level (or from the perspective of the application). 
         [0023]    In this way, processor requests may be made visible to the TCB in a software transparent manner possibly at the expense of some performance degradation. In order to avoid filling up the available trace storage or significantly impacting performance, the bypassing of requests may be accomplished selectively according to the type of read block (e.g., a normal data read RdBlk) or line fill (a processor reading a line into its own internal cache, wherein a line is the unit of data that a cache operates on), shared line fill (RdBlkS, line fill with intent to modify (RdBlkM) or L2 dirty victim block (VicBlk) or clean victim block (WrVicBlkCl) which are indicated by a request mask register. In addition, an enable from the trace buffer itself may be used to enable the selected set of requests to be bypassed. A local trigger may also be used to enable bypassing of a preprogrammed set of request types when a specific type of request is observed relative to a particular address (via a compare with the address target register). Similarly, the trace buffer already includes a rich set of filters. These filters enable trace buffer activity to be captured and the trace buffer being enabled for capture may be used as an enable to cause the L3 to bypass the selected set of requests. 
         [0024]    For example, the TCB receives a large number of events such as a request (e.g., a transaction) of a specific type traversing the crossbar or a probe receiving a particular transaction response from the system and it may be programmed to begin capturing trace information based on many different combinations of these events. The TCB may be programmed to begin capturing when an event or sequence of events is observed that might be relevant to the bug or condition under investigation. In this case, a signal from the TCB indicating that it has been triggered (the trace controller simply reacts to the received signal) may be used by the L3 trace controller to cause it to begin bypassing requests so that they may be captured in the TCB to aid in the debug. In other cases, it may be desirable for the L3 trace controller to autonomously begin trace bypass based on matches with incoming request types or addresses which may not otherwise be forwarded to the TCB allowing it to be triggered. 
         [0025]    Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements. The methods or flow charts provided herein may be implemented in a computer program, software, or firmware incorporated in a computer-readable storage medium for execution by a general purpose computer or a processor. Examples of computer-readable storage mediums include a read only memory (ROM), a random access memory (RAM), a register, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks, and digital versatile disks (DVDs). 
         [0026]    Embodiments of the invention may be represented as instructions and data stored on a computer readable memory. For example, aspects of the invention may be included in a hardware description language (HDL) code stored on such computer readable media. Such instructions, when processed may generate other intermediary data (e.g., netlists, GDS data, or the like) that can be used to create mask works that are adapted to configure a manufacturing process (e.g., a semiconductor fabrication facility). Once configured, such a manufacturing process is thereby adapted to manufacture processors or other semiconductor devices that embody aspects of the present invention. 
         [0027]    Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, application specific integrated circuits (ASICs), graphics processing units (GPUs), field programmable gate arrays (FPGAs) circuits, any other type of integrated circuit (IC), and/or a state machine.