Abstract:
In a multicasts wireless telecommunication system providing an aggregation of one or more independent data components as a flow, wherein the OIS is located at the latch point of the beginning of the superframe, and the OIS programming is latched at the superframe boundary, the improvement of deriving signal parameter information from Signaling Parameter Channel (SPC) symbols transmitted in a Forward Link only (FLO) network by deriving a time domain channel estimate by assuming each of the combinations for the signal parameter field in the scrambler seed and picking the signal parameter combination that yields the most energy in the time domain above a threshold value.

Description:
CLAIM OF PRIORITY UNDER 35 USC §119 
       [0001]    The present application for a patent claims priority to provisional application No. 61/040,502 entitled “SYSTEMS AND METHODS FOR PROCESSING A SIGNALING PARAMETERS CHANNEL” filed Mar. 28, 2008, and assigned to the assignee hereof and hereby expressly incorporated by reference herein. 
     
    
     BACKGROUND 
       [0002]    1. Field 
         [0003]    The present disclosed embodiments relates generally to processing wave forms in a wireless telecommunication system at the Forward Link Only (FLO) receiver, and more specifically to signaling parameters channel (SPC) and its associated processing at the FLO receiver, wherein SPC is a new channel added to the FLO superframe as a revision of the FLO air interface specification to convey physical layer parameters that cannot be transmitted through the Overhead Information Symbol (OIS). 
         [0004]    2. Background 
         [0005]    The Forward Link Only (FLO) system multicasts several services. A service is an aggregation of one or more independent data components. Each independent data component of a service is called a flow. For example, a flow can be the video component, audio component, text or signaling component of a service. 
         [0006]    The transmitted signal in the Forward Link Only system is organized into superframes, wherein each superframe has the duration of about one second.  FIG. 1  shows the general relationship (not to scale) between the various physical layer channels in a superframe, such as the OIS and the data channels. 
         [0007]    Forward Link Only services are carried over one or more logical channels, and these logical channels are called Multicast Logical Channels or MLCs. It is the smallest addressable element in the FLO Network transmission system. 
         [0008]    The definition of the FLO Air interface is that the FLO physical layer consists of the FLO physical layer channels. The OIS and Data are two of them. OIS stands for overhead information symbol channel. OIS channel carries the important system information sent out by the network. 
         [0009]    Min monitor cycle is used as a period for the device to get the OIS. When the MediaFLO device is in the idle mode, most of the time FLO modem goes to the low power mode or sleep mode. It wakes up periodically at the Min monitor cycle to decode the OIS. 
         [0010]    However, there are physical layer parameters in the FLO superframe that cannot be transmitted through the OIS. 
         [0011]    There is therefore a need in the wireless telecommunications systems devices employing the Forward Link Only (FLO) system multicast services to convey physical layer parameters that cannot be transmitted through the OIS. 
       SUMMARY 
       [0012]    Embodiments disclosed herein address the above stated needs to convey physical layer parameters by employing Signal Parameters Channel in associated processing at the FLO receiver, so that the SPC when added to the FLO superframe enables physical layer parameters that cannot be transmitted through the OIS to now be conveyed. 
         [0013]    In one aspect of the SPC addition to the FLO superframe, the SPC carries information that would be required to decode the OIS itself. 
         [0014]    In another aspect, since one important characteristic of SPC is that the SPC wave form is independent of the physical layer parameters such as slot to interlace map, the Fast Fourier Transform (FFT) and cyclic prefix, this allows the receiver to be able to decode the information carried by the SPC under any network deployment conditions using default factory settings. The information obtained from the SPC can then be used to decode the OIS, which in turn will allow for other parameters to be configured via the network. 
         [0015]    In yet another aspect, the SPC symbols have been designed such that the receiver processing is along the lines of Wide Area Differentiator/Local Area Differentiator (WID/LID) determination in the WIC/LIC symbols allow reuse of hardware in the receiver. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0016]      FIG. 1  depicts the location and relationship of the OIS channel and data channel in the FLO (Forward Link Only) superframe structure. 
           [0017]      FIG. 2  shows the superframe structure for FLO with PPC symbols and SPC symbols which are always of duration 4625 chips. 
           [0018]      FIG. 3  shows a SPC symbol structure. 
           [0019]      FIG. 4  shows a block diagram for SPC processing at the receiver. 
           [0020]      FIG. 5  is a diagram of a hardware circuit to implement the descrambling operation. 
           [0021]      FIG. 6  is a block diagram for the threshold operation. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Signalling parameters Channel (SPC) and its associated processing at the FLO receiver is a new channel that is added to FLO superframe in revision of the FLO Air Interface Specification. In particular, SPC is added to the FLO superframe to convey physical layer parameters that cannot be transmitted through the OIS. For example, SPC carriers information that would be required to decode the OIS itself. The information that is carried by the SPC includes FFT mode information (1 k, 2 k, 4 k, 8 k), the cyclic prefix length used ( 1/16. ⅛, ¼ or ⅜) and the slot to interface map used ((2,6) pattern, (0,3,6) pattern). 
         [0023]    Each SPC symbol can convey 8 bits of information. Therefore, 16 bits of information can be conveyed using the two SPC symbols. 16 bits of information allows for additional room to convey any other information that may be required in the future. 
         [0024]    One important characteristic of SPC is that the SPC waveform is independent of the physical layer parameters such as slot to interface map, FFT mode and cyclic prefix. This allows the receiver to be able to decode the information carried by SPC under any network deployment conditions using default factory settings. The information obtained from the SPC can then be used to decode OIS, which will in turn allow for other parameters to be configured via network. SPC symbols have been designed such that the receiver processing is along the lines of WID/LID determination in WIC/LIC symbols or the (Positioning Parameters Channel) PPC symbol to simplify the receiver architecture. 
         [0025]    With regard to the numerology of the innovation, SPC symbols occur at the end of FLO superframe. SPC symbols are always two in number, and this fixed numerology follows across all modes of transmission. The superframe structure for FLO with PPC symbols and SPC symbols is shown in  FIG. 1  SPC symbols are always of duration 4625 chips and have identical structure across FFT modes, cyclic prefix lengths and pilot patterns. It should be noted that SPC symbol structure is based on 4K mode interlaces and does not depend on the FFT mode used for the rest of the superframe. 
         [0026]    See  FIG. 1  which shows the location and relationship of the OIS channel and data channel in the forward link only (FLO) air interface by way of the super frame structure, wherein rapid channel acquisition is achieved through an optimized pilot and interleaver structure design. The interleaving schemes incorporated in the FLO air interface simultaneously assure time diversity. Here, the pilot structure and interleaver design optimizes channel utilization without perturbing the user with long acquisition times. The FLO transmitted signal is organized into super frames, wherein each super frame is comprised of four frames of data, including the TDM pilots, the overhead information symbols (OIS) and frames containing wide-area and local-area data. In general, each super frame consists of 200 OFDM symbols per MHz of allocated bandwidth (1200 symbols of 6 MHz), and each symbol contains 7 interlaces of active subcarriers. Each interlace is uniformly distributed in frequency, so that it achieves the full frequency diversity within the available bandwidth. These interlaces are assigned to logical channels that vary in terms of duration and number of actual interfaces used to provide flexibility in the time diversity achieved by any given data source. Lower data rate channels can be assigned fewer interlaces to provide time diversity, while higher data rate channels utilize more interlaces to minimize the signal on-time and reduce power consumption. The acquisition time for both low and high data rate channels is approximately the same. Both frequency and time diversity can be maintained without compromising acquisition time. 
         [0027]    SPC symbols are recovered using the demodulation technique that is employed in direct sequence spread spectrum systems. In particular, useful information from the received signal can be obtained only when the scrambling sequence at the receiver is matched to the scrambling sequence used at the transmitter. If the scrambling sequence is mismatched, then the received signal would appear as noise to the receiver. However, if the scrambling sequence used at the receiver matches with the transmitted sequence, then the receiver would be able to extract information from the received signal. In particular, SPC symbol transmits pilots in the frequency domain on interlaces 0 and 4 with the only uknown at the receiver being the four bits used in the scrambler seed for each of the interlaces. The algorithm used for SPC decoding computes the channel estimate in time domain using the pilots from each of the interlaces and also a particular combination of the four unknown bits in the scrambler seed. When the receiver scrambler seed is not matched to the transmitter, the time domain channel estimate appears noisy with no significant energy taps. However, when the receiver scrambler seed matches with that of the transmitter, the time domain channel estimate will exhibit energy concentrated in few taps. In order to identify the concentration of the energy in few taps, an energy threshold is set and the energy above the threshold is collected. The four bits in the WID field of the scrambler seed index corresponding to the maximum energy above the threshold are declared as the Information bits contained in that particular SPC symbol interlace. 
         [0028]    Reference is now made to  FIG. 2 , which shows the superframe structure for the FLO with the SPC and PPC symbols for the 2K mode. As can be seen from  FIG. 2 , the SPC symbols are at the end of the FLO superframe. The SPC symbols are always two in number, and follow fixed numerology across all modes of transmission. The SPC symbols are always of duration 4625 chips. The break up of the SPC symbols is independent on the FFT mode. In this connection, it should be noted that the SPC symbols structure is based on 4K mode interlaces and does not depend on the FFT mode used for the rest of the superframe. 
         [0029]    The superframe structure for the 1K, 2K, 4K and 8K FFT modes for the FLO waveform with SPC and PPC symbols are shown in  FIG. 2 , and are as follows: 
         [0030]    FFT window=4096 chips 
         [0031]    Cyclic prefix=512 chips 
         [0032]    Window=17 chips 
         [0033]    As can be seen from the SPC symbol structure of  FIG. 3 , there are two 4K mode interlaces active in each SPC symbol. In particular, interlaces 0 and 4 are occupied in the frequency domain. Two active interlaces in the frequency domain lead to a time domain waveform that is periodic with a periodicity of 1024 samples, and four such periods occur within the FFT window. Information in SPC symbols is conveyed through the scrambler seed used for interlaces 0 and 4. Specifically, the WID field in the scrambler seed is used to convey 4 bits of information in each interlace while the LID field is hard-coded to 0000. The scrambler seed referred to here is the 20 bit scrambler seed specified in FLO AIS given by
   d3d2d1d0 c3c2c1c0 b0 a10a9a8a7a6a5a4a3a2a1a0   where   a10a9a8a7a6a5a4a3a2a1a0—correspond to the OFDM symbol index   b0—reserved bit set equal to 1   c3c2c1c0—LID (Local area differentiator)   d3d2d1d0—WID (Wide area differentiator).The receiver should use the following information for descrambling the SPC symbols.   In addition to the scrambler seed, the mask used for scrambling is based on the slot information. The information for each of the interlaces in SPC0 and SPC1 is as follows (see  FIG. 3 ).   Interlace 0:   Symbol index (a10-a0)—hard coded: SPC0=0-, SPC1=1   LID=0000   WID=4 bits of Information to be conveyed   Slot index=0 (identity slot to interlace map used)   Interlace 4:   Symbol index (a10-a0)—hard coded: SPC0=0, SPC1=1   LID=0000   WID=4 bits of Information to be conveyed   Slot index=4 (identity slot to interlace map used)   Symbol index (a10-a0)—hard coded: SPC0=0, SPC1=1   LID=0000   WID=4 bits of Information to be conveyed   Slot index=0 (identity slot to interlace map used)   
 
         [0055]    The block diagram for SPC processing is shown in  FIG. 4 , where the software collects the 16 bits of information obtained from SPC0 and SPC1 and determines the system parameters to be used for decoding the FLO waveform. Based on the decoded information, the software programs the slot to interlace map to be used, the cyclic prefix information and the FFT mode information to be used by the hardware to decode the OIS and data channels in the superframe. 
         [0056]    The steps involved in determining the scrambler information is described in the following sections. While the processing for interlace 4 is almost identical to that of interlace 0, there are a few minor differences which will be highlighted wherever they occur. 
         [0057]    Scrambler Seed Detection. 
         [0058]    The receiver operations involved in scrambler seed detection corresponding to all the fields other than the WID field are known at the receiver. Accordingly, we use scrambler seed detection and WID detection interchangeably. Note that the WID field detection in SPC does not correspond to actual WID used by the transmitter to scramble the superframe information. Also, to distinguish between the four WID fields detected during the processing of the two SPC symbols, we refer to the four fields as SPC0_WID0, SPC0_WID1, SPC1_WID0,SPC1_WID1, where the index after SPC refers to SPC symbol index and the index after WID corresponds to interlace index. SPC processing is initiated in HW by the software by writing 1 to the register FLO_SPC_PROCESS. This enables the processing of both the SPC symbols in the superframe. 
         [0059]    Time Domain Interlace 
         [0060]    SPC symbol processing follows TDM1 detection, WIC/LIC detection and TDM2 processing in the superframe. The TDM1, WIC/LIC and TDM2 are also fixed across various FFT modes, cyclic prefix sizes and slot to interlace maps. Therefore fine timing alignment is available e at the receiver via TDM2 before SPC is processed. However, there is a close to one second delay before SPC symbols can be processed after fine time alignment via TDM2. The long delay could potentially result in timing drifts thus resulting in possible ambiguity in symbol boundary at SPC. Therefore, we use only two periods (2K samples) out of the total of four possible periods (4K samples) in the SPC symbol. Note that depending on the timing ambiguity expected from the circuitry of the chip, one to four periods of the SPC waveform can be used for processing. The start of the window for collecting the 2K samples is programmable by software through the register FLO_SPC_OFFSET. 
         [0061]    During each SPC symbol, the FFT block collects 2K samples starting at sample number FLO_SPC_OFFSET coming out of the AFC. FFT extends the 2K samples periodically to form 4K samples (2 periods of 2K samples). Let x(n), n=0,1..4095 be the 4096 samples after periodic extension where x(n)=x(n+2048), for 0≦n≦2047. FFT block forms 512 time domain interlace samples corresponding to interlace 0 and interlace 4 using x(n), n=0,1..4095. Let the 512 samples corresponding to interlace m be denoted by y m (n), n=0,1,2,..511., where m=0,4. 
         [0062]    512 pt FFT 
         [0063]    The next step in computing WID is to perform a 512 pt FFT on the sequence {y m (n)} corresponding to interlaces 0 and 4. The 512 pt FFT (with normalization as implemented in the hardware) is given by 
         [0000]    
       
         
           
             
               
                 
                   Y 
                   m 
                 
                  
                 
                   ( 
                   k 
                   ) 
                 
               
               = 
               
                 
                   1 
                   64 
                 
                  
                 
                   
                     ∑ 
                     
                       l 
                       = 
                       0 
                     
                     511 
                   
                    
                   
                     
                       
                         y 
                         m 
                       
                        
                       
                         ( 
                         l 
                         ) 
                       
                     
                      
                     
                        
                       
                         
                           
                             - 
                             j2π 
                           
                            
                           
                               
                           
                            
                           lk 
                         
                         512 
                       
                     
                   
                 
               
             
             , 
             
               
                 for 
                  
                 
                     
                 
                  
                 k 
               
               = 
               0 
             
             , 
             1 
             , 
             2 
             , 
             
               … 
                
               
                   
               
                
               511. 
             
           
         
       
     
         [0064]    At the output of the FFT block, the samples corresponding to interlaces 0 and 4 given by {Y m (k)}, k=0,1,2..511 in frequency domain where each frequency domain sample is a complex number, with real and imaginary components each represented by 9 signed bits with a scale factor of 2 6 . 
         [0065]    Descrambling 
         [0066]    After obtaining the frequency domain samples, hypothesis testing is performed using the 16 possible scrambler seeds corresponding to the 4 bits for the WID field in the scrambler seed for each of the two interlaces. Note that the 4 bits corresponding to the LID field are all set to 0000 during the descrambling operation. The scrambler seed and mask parameters for the interlace 0 and interlace 4 are as follows: 
       Interlace 0: 
       [0067]    Symbol index=0000 for SPC0 and 0001 for SPC1 
         [0068]    LID field=0000 
         [0069]    WID field=all combinations from 0000 through 1111 
         [0070]    Slot index=0 (since identity slot to interlace map is used) 
         [0071]    Interlace 4 
         [0072]    Symbol index=0000 for SPC0 and 0001 for SPC1 
         [0073]    LID field=0000 
         [0074]    WID field=all combinations from 0000 through 1111 
         [0075]    Slot index=4 (identity slot to interlace map) 
         [0076]    If the scrambler output corresponding to the k th subcarrier in the interlace 0 corresponding to the i th hypothesis (i goes from 0 through 15) is given by S i (k), then the descrambler output is given by: 
         [0000]        H   i ( k )= Y ( k ) S*   i ( k ) 
         [0000]    Note that S i (k) is obtained by mapping the scrambler output [b 2k  b 2k+1 ] to the QPSK constellation. Multiplication by S* i (k) is accomplished as a clockwise rotation by a multiple of π/2 as shown in Table 1 followed by a clockwise rotation by π/4 (given by 1-j ignoring scaling by 
         [0000]    
       
         
           
             
               
                 1 
                 
                   2 
                 
               
               ) 
             
             . 
           
         
       
     
         [0000]    
       
         
               
               
               
             
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 (b 2k+1  b 2k ) (from scrambler) 
                 Angle of rotation (degrees) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 00 
                 0 
               
               
                   
                 01 
                 90 
               
               
                   
                 11 
                 180 
               
               
                   
                 10 
                 270 
               
               
                   
                   
               
             
          
         
       
     
       Descrambling Operation Based on the Scrambler Output 
       [0077]    The hardware operations for descrambling is the same as that used for descrambling of the pilot symbols in channel estimation, WIC/LIC symbols and PPC acquisition mode operations, and the hardware circuit to implement the descrambling operation is shown in  FIG. 5 . 
         [0078]    Zero Extrapolation 
         [0079]    Note that there are only 500 pilots transmitted in each of the active interlaces for the SPC symbols. A least squares channel estimate based on 500 pilots would involve a matrix inversion operation and is computationally expensive. Therefore, it is computationally advantageous to extend the 500 pilot observations to 512 observations so that the least squares channel estimation operation can be reduced to a 512 point IFFT operation. The extension of 500 pilot observations to 512 observations can be done in one of several ways. One way to extend the observations is to use zero extrapolation where the missing pilot observations are replaced with zeros. The zero extrapolation performed on H i (k) is similar to the zero extrapolation performed during channel estimation. The memory locations are zeroed out are slightly different between interlaces 0 and 4. 
         [0080]    For Interlace 0: set the memory locations between 251 and 261 (11 subcarriers) in the buffer corresponding to H i (k)&#39;s equal to zero to account for the presence of guard subcarriers. In addition, the DC subcarrier at memory location 0 should also be set to zero. 
         [0081]    For Interlace 4: set the memory locations between 250 and 261 (12 subcarriers) in the buffer corresponding to H i (k)&#39;s equal to zero to account for the presence of guard subcarriers. In this case, DC subcarrier is not part of the interlace and hence does not require special attention. 
         [0000]    Another example of extrapolation is a zero order hold where the last pilot observation is extended to fill in the missing pilots. In yet another case, the missing pilot observations may be formed by a filtering process on all the available pilot observations. 
         [0082]    512pt IFFT 
         [0083]    After extrapolation, we obtain 512 values for H i (k). We then perform a 512 pt IFFT operation on the extrapolated values for WID hypothesis i to obtain the corresponding time domain samples. The IFFT operation on the extrapolated values H i (k) is given by (with normalization as in the hardware) 
         [0000]    
       
         
           
             
               
                 
                   h 
                   i 
                 
                  
                 
                   ( 
                   l 
                   ) 
                 
               
               = 
               
                 
                   1 
                   64 
                 
                  
                 
                   
                     ∑ 
                     
                       k 
                       = 
                       0 
                     
                     511 
                   
                    
                   
                     
                       
                         H 
                         i 
                       
                        
                       
                         ( 
                         k 
                         ) 
                       
                     
                      
                     
                        
                       
                         
                           j2π 
                            
                           
                               
                           
                            
                           lk 
                         
                         512 
                       
                     
                   
                 
               
             
             , 
             
               
                 for 
                  
                 
                     
                 
                  
                 l 
               
               = 
               0 
             
             , 
             1 
             , 
             
               2 
                
               … 
                
               
                   
               
                
               511. 
             
           
         
       
     
         [0000]    At the output of the IFFT operation, we obtained a 512 length time domain channel estimate given by {h i (l)} corresponding to the transmitter using the scrambling pattern with the WID given by index i. Each time domain sample is a complex number with the real and imaginary parts represented by 9 bits. The next step is to threshold the channel estimate to remove contribution of noise and measure energy against each hypothesis. 
         [0084]    Thresholding and Energy Measurement 
         [0085]    After obtaining the time domain channel estimate, the energy in each tap is computed and compared to a threshold value. The thresholding and energy measurement procedure is similar to that in WIC/LIC and PPC processing. The threshold value to be used is programmed by software in FLO_SPC_THRESHOLD, which is referred to as β. 
         [0000]    For each hypothesis i, the pseudo code for measuring the corresponding energy E i  is as follows: 
         [0000]    
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 E i  = 0; 
               
               
                   
                 for l = 0..511 
               
               
                   
                   if |h i (l)| 2  ≧ β 
               
               
                   
                     E i  = E i  +|h i (l)| 2 ; 
               
               
                   
                   end; 
               
               
                   
                 end; 
               
               
                   
                   
               
             
          
         
       
     
         [0086]    The block diagram for implementing the thresholding operation and energy accumulation is given in  FIG. 6 . 
         [0000]    The above steps corresponding to descrambling through thresholding and energy measurement are repeated for all of the 16 hypotheses. After collecting energies E i  for i=0,1,..15 corresponding to the 16 hypotheses, we find i for which E i  is maximum. The four bits representing the winning hypothesis which is the value of i corresponding to maximum E i  represent the information contained in that particular interlace of the SPC symbol. The same process is repeated independently on each of the two interlaces and then on each of the SPC symbols in the superframe. 
         [0087]    Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. 
         [0088]    Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. 
         [0089]    The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. 
         [0090]    The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal. 
         [0091]    The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.