Abstract:
A pump circuit forming a boosted power supply (Vpp) generating circuit includes: first and second pumps generating a boosted power supply; and a test circuit controlling levels of stress applied to the first and second pumps in accordance with a signal input from a ring oscillator and a test signal. A semiconductor memory device of the present invention enables application of a desired level of stress to each capacitor of the pump circuit formed for a stress test, and provides enhanced efficiency of the stress test and increased reliability of the semiconductor integrated circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor integrated circuit and, more particularly to a structure of a boosted power supply generating circuit. 
     2. Description of the Background Art 
     Conventionally, for a semiconductor integrated circuit such as a DRAM (Dynamic Random Access Memory), a boosted power supply has been widely used to eliminate the influence of a threshold voltage of a transistor. In the DRAM, a boosted power supply Vpp is primarily used as a word line voltage or the like. 
     FIG. 14 is a block diagram showing a boosted power supply generating circuit  500  (hereinafter referred to as a Vpp generating circuit). 
     Vpp generating circuit  500  includes a detector circuit  100 , a ring oscillator circuit  200 , and a pump circuit  300 . 
     Detector circuit  100  detects any decrease in its voltage below a prescribed level due to current consumption of the semiconductor integrated circuit or the like for generating a signal Φ 1  in generating Vpp. 
     An exemplary ring oscillator circuit  200  is shown in FIG.  15 . 
     Ring oscillator circuit  200  includes an NAND circuit  201 , a delay circuit  206  having inverters  202  to  205  connected in series, and an inverter  207 . 
     Ring oscillator circuit  200  receives signal Φ 1  for repeatedly generating pulse signal Φ 2 . 
     An exemplary pump circuit  300  is shown in FIG.  16 . 
     Pump circuit  300  includes capacitors  301 ,  302 , and  303 , an inverter  304 , and N channel transistors  305 ,  306 ,  307 , and  308 . 
     In pump circuit  300 , capacitor  301  is arranged between nodes N 1  and N 3 . N channel transistor  305  is arranged between an external power supply source Ext. Vcc (hereinafter referred to as Vcc) and node N 3 , having its gate connected to external power supply source Vcc. N channel transistor  306  is arranged between external power supply source Vcc and node N 4 , having its gate connected to node N 3 . N channel transistor  307  is arranged between external power supply source Vcc and node N 5 , having its gate connected to node N 3 . Inverter  304  is arranged between nodes N 1  and N 2 . Capacitor  302  is arranged between nodes N 2  and N 5 . Capacitor  303  is arranged between nodes N 2  and N 4 . N channel transistor  308  is arranged between nodes N 4  and N 6 , having its gate connected to node N 5 . Vpp is supplied to each portion of the circuit from node N 6 . 
     Pump circuit  300  receives output signal Φ 2  from ring oscillator circuit  200  for generating Vpp by a pumping operation of capacitors  301 ,  302 , and  303 . 
     The operation of Vpp generating circuit  500  shown in FIG. 14 will be described with reference to a time chart of FIG.  17 . 
     Detector circuit  100  is set to output signal Φ 1  at “L” if its voltage is at a desired level (at or higher than a detection level) in generating Vpp. 
     Detector circuit  100  detects any decrease in Vpp below a prescribed level due to power consumption of the semiconductor integrated circuit, and outputs signal Φ 1  at “H.” 
     If the decrease in Vpp is detected, output signal Φ 1  at “H” is input from detector circuit  100 , and therefore ring oscillator circuit  200  repeatedly outputs pulse signal Φ 2  at “H” in response to input signal Φ 1  at “H” until Vpp attains to a prescribed level by a pumping operation which will later be described (FIG. 17 shows that one pumping operation restores Vpp). 
     If no decrease in Vpp is detected, output signal Φ 1  at “L” is input from detector circuit  100 , and therefore ring oscillator circuit  200  outputs signal Φ 2  at “L.” 
     At the time, in pump circuit  300 , node N 1  is at “L,” and node N 2  is at “H” because of inverter  304 . 
     Node N 3  is precharged to a level of power supply voltage Vcc−Vth (Vth is a threshold voltage of N channel transistor  305 ), and capacitor  301  is charged. 
     Nodes N 4  and N 5  are at a level of Vcc−2Vth (Vth is a threshold voltage of N channel transistors  306  and  307 ). 
     If detector circuit  100  detects any decrease in Vpp, it outputs signal Φ 1  at “H.” 
     Ring oscillator circuit  200  operates in response to signal Φ 1  at “H,” and outputs signal Φ 2  at “H.” 
     At the time, node N 1  is at “H,” and the pumping operation of capacitor  301  brings node N 3  to a level of 2Vcc−Vth, so that N channel transistors  306  and  307  are fully turned on. 
     Node N 2  attains from “H” to “L” because of inverter  304 . 
     Thus, although the voltage levels at nodes N 4  and N 5  temporarily decrease, they are precharged to the Vcc level when N channel transistors  306  and  307  are turned on. 
     Thus, capacitors  302  and  303  are charged to the Vcc level. 
     Subsequently, when output signal Φ 2  from ring oscillator circuit  200  attains to “L,” node N 2  attains to “H” because of inverter  304 . 
     The pumping operation of capacitors  302  and  303  causes nodes N 4  and N 5  to attain to the 2Vcc level. 
     Then, N channel transistor  308  is turned on and electric charges are supplied to node N 6 . As a result, the voltage level at node N 6  rises. 
     A stress test is performed on a semiconductor integrated circuit to assure reliability, in which a high electric field is applied to an oxide film. In the above described Vpp generating circuit, reliability of capacitors  301 ,  302 , and  303  must also be assured. In a stress test mode, the semiconductor integrated circuit is maintained in a stand-by mode and detector circuit  100  is inactivated by a Test signal shown in FIG.  14 . At the time, output signals Φ 1  and Φ 2 , respectively from detector circuit  100  and ring oscillator circuit  200 , are both at “L.” Thus, in the stress test mode, nodes N 1  and N 2  of the pump circuit  300  are always at “L” and “H,” respectively. Accordingly, capacitors  302  and  303  are subject to weaker stress as compared with capacitor  301 . 
     Having the above described structure, Vpp generating circuit  500  of a conventional semiconductor integrated circuit suffers from a problem that a desired level of stress cannot be applied to each capacitor in the pump circuit in a stress test mode for assuring reliability. 
     SUMMARY OF THE INVENTION 
     The present invention provides a Vpp generating circuit which ensures that a capacitor is reliably tested. 
     A semiconductor integrated circuit of the present invention includes: a plurality of memory cells arranged in a matrix; a memory cell array region having a plurality of word lines arranged corresponding to rows; and a plurality of bit lines arranged corresponding to columns; a pump circuit generating by a plurality of capacitors a boosted voltage supplied to the memory cell array region; and a test circuit controlling a level of stress applied to the plurality of capacitors in the pump circuit. 
     Preferably, the test circuit is controlled by a test signal. 
     Particularly, the test signal controls levels of stress applied to the plurality of capacitors. 
     According to the above described semiconductor integrated circuit, a desired level of stress can be applied to each capacitor in the pump circuit in a stress test mode, so that the semiconductor integrated circuit is provided with enhanced reliability. 
     Particularly, the test circuit controls the levels of stress applied to the plurality of capacitors simultaneously by the test signal. 
     According to the semiconductor integrated circuit of the present invention, desired levels of stress can be simultaneously applied to capacitors of the pump circuit in the stress test, so that the efficiency of the stress test and the reliability of the semiconductor integrated circuit increases. 
     Particularly, the test signal is input from an external signal pin. 
     Particularly, the test signal is input from an external pad. 
     Preferably, there is further provided a test signal generating circuit for internally generating the test signal. 
     Particularly, the test signal generating circuit generates a test signal in response to input from the external signal pin. 
     Particularly, the test signal generating circuit generates the test signal in response to input from the external pad. 
     According to the semiconductor integrated circuit of the present invention, the input test signal is generated from the external pad, external signal pin, or internally from test signal generating circuit. 
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing a pump circuit according to a first embodiment of the present invention. 
     FIG. 2 is a diagram showing a Vpp generating circuit according to the first embodiment of the present invention. 
     FIG. 3 is a table shown in conjunction with an operation of the pump circuit according to the first embodiment of the present invention. 
     FIGS. 4 and 5 are diagrams showing the pump circuit according to the first embodiment of the present invention. 
     FIG. 6 is a diagram showing a pump circuit according to a second embodiment of the present invention. 
     FIG. 7 is a diagram showing a Vpp generating circuit according to the second embodiment of the present invention. 
     FIG. 8 is a table shown in conjunction with an operation of the pump circuit according to the second embodiment of the present invention. 
     FIGS. 9 and 10 are diagrams showing the pump circuit according to the second embodiment of the present invention. 
     FIG. 11 is a block diagram showing a general arrangement of a DRAM of one embodiment of the present invention. 
     FIG. 12 is a circuit block diagram showing an arrangement of a memory mat of FIG.  11 . 
     FIG. 13 is a block diagram showing a general arrangement of a DRAM provided with a test signal generating circuit according to one embodiment of the present invention. 
     FIG. 14 is a block diagram showing a Vpp generating circuit. 
     FIG. 15 is a diagram showing an exemplary ring oscillator circuit. 
     FIG. 16 is a diagram showing an exemplary pump circuit. 
     FIG. 17 is a diagram showing an exemplary operation waveforms of the Vpp generating circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention will be described in detail with reference to the drawings. It is noted that the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated. 
     First Embodiment 
     FIG. 1 shows a pump circuit  310  forming a Vpp generating circuit according to the first embodiment of the present invention. 
     Pump circuit  310  includes a test circuit  400 , a first pump  311 , a second pump  312 , and an inverter  304  arranged between nodes N 1  and N 2 . 
     Test circuit  400  includes: an NOR circuit  401  receiving a test signal TM 1  and an output signal Φ 2  from ring oscillator circuit  200 ; and an NOR circuit  402  receiving an output signal from NOR circuit  401  and a test signal TM 2 . 
     Test circuit  400  controls output signal Φ 2  from ring oscillator circuit  200  in accordance with a test signal. 
     An output from the test circuit (an output from NOR circuit  402 ) is supplied (input) to node N 1 . By inputting a signal from node N 1  and a signal from node N 2  (an inversion of a signal at node N 1 ) respectively to first and second pumps  311  and  312 , the level of stress applied to each pump is controlled. 
     Each of first and second pumps  311  and  312  includes a capacitor. 
     In the present invention, a desired level of stress is applied to each capacitor in a stress test mode by test circuit  400 . Namely, a prescribed voltage difference is applied between polar plates of each capacitor. 
     FIG. 2 shows an arrangement of Vpp generating circuit  510  of the present invention. In FIG. 2, pump circuit  320  is shown as an illustrative example of pump circuit  310 . 
     Vpp generating circuit  510  includes a detector circuit  100 , a ring oscillator circuit  200 , and a pump circuit  320 . 
     Pump circuit  320  includes a test circuit  400 , capacitors  301  to  303 , transistors  305  to  308 , and an inverter  304 . 
     The relationship among capacitors  301  to  303 , transistors  305  to  308 , and inverter  304  is as described above. 
     The operation of pump circuit  320  of the present invention will be described with reference to a table of FIG. 3, which is shown in conjunction with the operation of the pump circuit. 
     In a normal operation, if test signals TM 1  and TM 2  are both at “L,” input signal Φ 2  of test circuit  400  is directly input to node N 1 . 
     In a stress test mode, test signals TM 1  and TM 2  are controlled to have a combination of levels that controls the voltage levels at nodes N 1  and N 2 . 
     Namely, if test signals TM 1  at “H” and TM 2  at “L” are input, nodes N 1  and N 2  respectively attain to “H” and “L,” so that stresses are applied to capacitors  302  and  303  shown in FIG.  2 . 
     If test signals TM 1  at “L” and TM 2  at “H” are input, nodes N 1  and N 2  respectively attain to “L” and “H,” so that a stress is applied to capacitor  301  shown in FIG.  2 . 
     As to a method of inputting test signals TM 1  and TM 2 , if input is performed with respect to a wafer as shown in FIG. 4, these signals are input from an external pad  17 . 
     Alternatively, test signals TM 1  and TM 2  may be internally generated by test signal generating circuit  19  in accordance with an external signal received from external signal pin  18  as shown in FIG.  5 . 
     Second Embodiment 
     FIG. 6 shows a pump circuit  330  forming a Vpp generating circuit according to the second embodiment of the present invention. 
     Pump circuit  330  includes a test circuit  410 , a first pump  311 , and a second pump  312 , and an inverter  304 . Inverter  304  outputs an inverted signal of output signal Φ 2  from ring oscillator circuit  200 . 
     Test circuit  410  includes: an NOR circuit  411  receiving a test signal TM 1  and output signal Φ 2  from ring oscillator circuit  200 ; an NOR circuit  412  receiving an output signal from NOR circuit  411  and test signal TM 2 ; an NOR circuit  413  receiving test signal TM 1  and an output signal from inverter  313 ; and an NOR circuit  414  receiving an output signal from NOR circuit  413  and test signal TM 2 . 
     An output from NOR circuit  412  is supplied to a node N 7  electrically connected to first pump  311 , whereas an output from NOR circuit  414  is supplied to a node N 8  electrically connected to second pump  312 . 
     Test circuit  410  uses a test signal for controlling the voltage levels at nodes N 7  and N 8 , so as to control the level of stress applied to each pump. 
     The present invention provides for simultaneous application of desired levels of stress to capacitors in the stress test mode by test circuit  410 . 
     FIG. 7 is a Vpp generating circuit  520  of the present invention that includes a pump circuit  340  as an illustrative example of pump circuit  330 . 
     Vpp generating circuit  520  includes a detector circuit  100 , a ring oscillator circuit  200 , and a pump circuit  340 . 
     Pump circuit  340  includes a test circuit  410 , capacitors  301  to  303 , transistors  305  to  308 , and an inverter  304 . 
     Capacitors  301  to  303  are connected to transistors  305  to  308  as described above. Inverter  304  is connected to NOR circuit  413  for inputting an inversion of output signal Φ 2  from ring oscillator circuit  200  to test circuit  410 . 
     In pump circuit  340 , capacitor  301  is connected between nodes N 7  and N 3 , capacitor  302  between nodes N 8  and N 5 , and capacitor  303  between nodes N 8  and N 5 . 
     The operation of pump circuit  340  of the present invention will be described with reference to a table of FIG. 8, which is shown in conjunction with the operation of the pump circuit. 
     In a normal operation, if test signals TM 1  and TM 2  are both at “L” as in the first embodiment, input signal Φ 2  and its inversion are directly input to nodes N 7  and N 8 . 
     In a stress test mode, test signals TM 1  and TM 2  are controlled to have a combination of levels that controls the voltage levels at nodes N 7  and N 8 . 
     Namely, if test signal TM 2  at “H” is input, nodes N 7  and N 8  both attain to “L” independent of test signal TM 1 , so that stresses are simultaneously applied to capacitors  301 ,  302 , and  303  shown in FIG.  7 . 
     As to a method of inputting test signals TM 1  and TM 2 , if input is performed with respect to a wafer as shown in FIG. 9 as in the first embodiment, these signals are input from external pad  17 . 
     Alternatively, test signals TM 1  and TM 2  can be internally generated by test signal generating circuit  19  in accordance with an external signal from external signal pin  18  as shown in FIG.  10 . 
     FIG. 11 is a block diagram showing an arrangement of a DRAM according to one embodiment of the present invention. Referring to FIG. 11, the DRAM includes: an internal power supply potential generating circuit  1 ; a clock generating circuit  2 ; a row and column address buffer  3 ; a row decoder  4 ; a column decoder  5 ; a memory mat  6 ; an input buffer  9 ; and an output buffer  10 . Memory mat  6  includes a memory array  7  and a sense amplifier+input/output control circuit  8 . 
     Internal power supply potential generating circuit  1  externally receives a power supply potential VCC and ground potential GND for generating internal power supply potentials VPP, VCCS, and VBL. Clock generating circuit  2  selects a prescribed operation mode in accordance with externally applied signals/RAS and /CAS for generally controlling the DRAM. 
     Row and column address buffer  3  generates row address signals RA 0  to RAi and column address signals CA 0  to CAi in accordance with externally applied address signals A 0  to Ai (note that i is an integer of at least 0). Generated signals RA 0  to RAi and CA 0  to CAi are respectively applied to row decoder  4  and column decoder  5 . 
     Memory array  7  includes a plurality of memory cells arranged in a matrix and each storing 1-bit data. Each memory cell is arranged at a prescribed address determined by column and row addresses. 
     Row decoder  4  designates a row address of memory array  7  in response to row address signals RA 0  to RAi applied from row and column address buffer  3 . Column decoder  5  designates a column address of memory array  7  in response to column address signals CA 0  to CAi applied from row and column address buffer  3 . Sense amplifier+input/output control circuit  8  connects a memory cell at an address designated by row decoder  4  and column decoder  5  to one end of a pair of data input/output lines IOP. The other ends of a pair of data input/output lines IOP are respectively connected to input buffer  9  and output buffer  10 . 
     In a writing mode, input buffer  9  applies externally input data Dj (note that j is a natural number) to the selected memory cell through the pair of data input/output lines IOP in response to an externally applied signal/W. In a reading mode, output buffer  10  externally outputs read data Qj from the selected memory cell in response to an externally input signal/OE. 
     FIG. 12 is a circuit block diagram showing an arrangement of memory mat  6  of the DRAM shown in FIG.  11 . Referring to FIG. 12, memory array  7  includes a plurality of memory cells MC arranged in a matrix, word lines WL arranged corresponding to rows, and a pair of bit lines BL, /BL arranged corresponding to columns. Each memory cell MC is of a well known type that includes an N channel MOS transistor for accessing and a capacitor for data storage. Word line WL transmits an output from row decoder  4  for activating memory cells MC in the selected row. The pair of bit lines BL, /BL is used for inputting/outputting data signals with respect to selected memory cells MC. 
     Sense amplifier+input/output control circuit  8  includes a pair of data input/output lines IO, /IO (IOP), as well as column selection gates  11  arranged corresponding to columns, a sense amplifier  12 , and an equalizer  13 . Column selection gate  11  includes a pair of N channel MOS transistors connected between a pair of bit lines BL, /BL and a pair of data input/output lines IO, /IO. A pair of N channel MOS transistors of each column selection gate  11  has its gate connected to column decoder  5  through column selection line CSL. In column decoder  5 , if column selection line CSL rises to an “H” level of a selection level, the pair of N channel MOS transistors are rendered conductive, and the pair of bit lines BL, /BL and the pair of data input/output lines IO, /IO are connected. 
     Sense amplifier  12  amplifies a small potential difference between the pair of bit lines BL, /BL to an internal power supply voltage VCCS (&lt;VCC) in response to the fact that sense amplifier activation signals SE, /SE have respectively attained to “H” and “L.” Equalizer  13  equalizes potentials of the pair of bit lines BL, /BL to a bit line potential VBL (=VCCS/2) in response to the fact that a bit line equalize signal BLEQ has attained to “H” level of an activation level. 
     Thus, in the DRAM, various internal power supply potentials VPP, VCCS, and VBL are generated in accordance with external power supply potential VCC. 
     FIG. 13 shows test signal generating circuit  19  of the present invention added to the DRAM of FIG.  11 . 
     Test signal generating circuit  19  outputs test signals TM 1  and TM 2  in accordance with an input to external pad  17  or external signal pin  18 . 
     The Vpp generating circuit is provided in internal power supply potential generating circuit  1  of FIG. 11 or FIG.  13 . 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.