Abstract:
The present invention provides an amplitude detector comprising: a first peak holding means for generating a first peak voltage signal for holding a peak voltage of a detected signal; a differential signal generating means for generating a differential signal between the first peak voltage signal and the detected signal; and a second peak holding means for generating an amplitude detect signal holding a peak voltage of the differential signal.

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to an amplitude detector and an equalizer. 
     When a video signal of R (Red), G (Green), and B (Blue) for example is transmitted through a copper monitor cable, the amplitude of the signal is detected by a destination receiver and, based on the detection result, the signal of which amplitude has been attenuated by transmission is amplified to restore the original signal. 
     FIG. 7 shows a constitution of a related-art amplitude detector  1  arranged in a receiver. As shown, the amplitude detector  1  has a capacitor  2 , a full-wave rectifier  3 , and a peak-hold circuit  4 . In the amplitude detector  1 , the DC component of a video signal S 0  transmitted over a monitor cable is removed by the capacitor  2  and the AC component S 2  of the video signal S 0  shown in FIG. 8 is outputted to the full-wave rectifier  3 . In the full-wave rectifier  3 , the AC component S 2  is full-wave rectified into a signal S 3  shown in FIG.  8 . In the peak-hold circuit  4 , the peak voltage of the signal S 3  is detected and an amplitude detect signal S 1  for holding this peak voltage is outputted. 
     FIG. 9 shows a constitution of another related-art amplitude detector  11  arranged in a receiver. 
     As shown, the amplitude detector  11  has a capacitor  2 , a positive peak-hold circuit  13 , a negative peak-hold circuit  14 , and an operational amplifier  15 . In the amplitude detector  11 , the DC component of a video signal S 0  transmitted over a monitor cable is removed by the capacitor  2  and an AC component S 2  of the video signal S 0  shown in FIG. 10 is outputted to the positive peak-hold circuit  13  and the negative peak-hold circuit  14 . In the positive peak-hold circuit  13 , the positive peak voltage of the AC component S 2  is detected and a signal S 13  for holding the detected peak voltage is outputted. In the negative peak-hold circuit  14 , the negative peak voltage of the AC component S 2  is detected and a signal S 14  for holding the detected peak voltage is outputted as shown in FIG.  10 . In the operational amplifier  15 , a differential voltage between the signal S 14  and the signal S 13  is detected and the detected differential voltage is outputted as an amplitude detect signal S 11 . According to the amplitude detector  11 , the peak-to-peak amplitude of the AC component S 2  of the video signal S 0  can be correctly detected theoretically. 
     However, in the amplitude detector  1  shown in FIG.  7 , if the duty ratio of the video signal S 0  is deviated from 0.5, the amplitude detect signal S 1  shown in FIG. 8 does not become a half of the peak-to-peak amplitude of the AC component  2 , causing an error in a measured value. Consequently, the attenuated amplitude of the video signal S 0  cannot be properly amplified for restoring the original signal. 
     Theoretically, the amplitude detector  11  shown in FIG. 9 can correctly detect the peak-to-peak amplitude of the AC component S 2  of the video signal S 0 . Actually, however, the characteristic of the positive peak-hold circuit  13  and the characteristic of the negative peak-hold circuit  14  are not exactly in symmetry, so that an error occurs also in the amplitude detect signal S 11 . 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide an amplitude detector capable of properly detecting an amplitude of a video signal for example. 
     In carrying out the invention and according to one aspect thereof, there is provided an amplitude detector comprising: a first peak holding means for generating a first peak voltage signal for holding a peak voltage of a detected signal; a differential signal generating means for generating a differential signal between the first peak voltage signal and the detected signal; and a second peak holding means for generating an amplitude detect signal holding a peak voltage of the differential signal. 
     In carrying out the invention and according to another aspect thereof, there is an amplitude detector comprising: a first peak holding means for generating a first peak voltage signal for holding a peak voltage of a detected signal; a first differential signal generating means for generating a first differential signal between the first peak voltage signal and the detected signal; a second peak holding means for generating a first amplitude detect signal holding a peak voltage of the first differential signal; a third peak holding means for generating a third peak voltage signal for holding a peak voltage of a reference signal; a second differential signal generating means for generating a second differential signal between the third peak voltage signal and the reference signal; a fourth peak holding means for generating a second amplitude detect signal holding a peak voltage of the second differential signal; and a third differential signal generating means for generating a third amplitude detect signal corresponding to a difference between the first amplitude detect signal and the second amplitude detect signal. 
     In the amplitude detector according to the invention, if the duty ratio of the input signal varies to vary an DC offset, the waveform of the first peak voltage signal follows the peak value of the input signal. Therefore, in the differential signal generating means, obtaining the difference between the first peak voltage signal and the input signal can obtain the differential signal indicative of the potential of the input signal relative to the first peak voltage signal. In the differential signal, the DC offset is canceled. Therefore, the amplitude detect signal having the peak-hold waveform of the differential signal correctly reflects the amplitude of the input signal relative to the output potential of the amplitude detect signal when the amplitude of the input signal is zero. 
     In carrying out the invention and according to still another aspect thereof, there is provided an equalizer comprising: a filter means for extracting a high-frequency component from an input signal to provide a first signal; a first amplifying means for amplifying, based on an amplification factor control signal, the first signal to generate a second signal; a second amplifying means for amplifying the input signal to generate a third signal; a superimposing means for superimposing the second signal and the third signal on each other to generate a fourth signal; and an amplitude detecting means for detecting an amplitude of the fourth signal to generate, based on the detected amplitude, the amplification factor control signal; the amplitude detecting means having a first peak holding means for generating a first peak voltage signal for holding a peak voltage of the fourth signal, a first differential signal generating means for generating a first differential signal between the first peak voltage signal and the fourth signal, a second peak holding means for generating a first amplitude detect signal holding a peak voltage of the first differential signal, a third peak holding means for generating a third peak voltage signal for holding a peak voltage of a reference signal, a second differential signal generating means for generating a second differential signal between the third peak voltage signal and the reference signal, a fourth peak holding means for generating a second amplitude detect signal holding a peak voltage of the second differential signal, and a third differential signal generating means for generating the amplification factor control signal corresponding to a difference between the first amplitude detect signal and the second amplitude detect signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects of the invention will be seen by reference to the description, taken in connection with the accompanying drawing, in which: 
     FIG. 1 is a diagram illustrating a constitution of an amplitude detector practiced as a first preferred embodiment of the invention; 
     FIG.  2 A and FIG. 2B are diagrams illustrating the waveforms of signals in the amplitude detector shown in FIG. 1; 
     FIG. 3 is a diagram illustrating a constitution of an amplitude detector practiced as a second preferred embodiment of the invention; 
     FIG. 4 is a circuit diagram illustrating a particular constitution of the amplitude detector shown in FIG. 3 practiced as a third preferred embodiment of the invention; 
     FIG. 5 is a diagram illustrating a constitution of an equalizer practiced as a fourth preferred embodiment of the invention; 
     FIG. 6 is a diagram for describing a comparator that performs comparison with reference to DC center and amplitude center; 
     FIG. 7 is a diagram illustrating a constitution of a related-art amplitude detector arranged in a receiver; 
     FIG. 8 is a diagram illustrating the waveforms of signals in the amplitude detector shown in FIG. 7; 
     FIG. 9 is a diagram illustrating a constitution of another related-art amplitude detector arranged in a receiver; and 
     FIG. 10 is a diagram illustrating the waveforms of signals in the amplitude detector shown in FIG.  9 . 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     This invention will be described in further detail by way of example with reference to the accompanying drawings. 
     First Preferred Embodiment: 
     FIG. 1 shows the constitution of an amplitude detector  21  practiced as a first preferred embodiment of the invention. As shown, the amplitude detector  21  comprises a capacitor  22 , an amplifier  23 , a peak-hold circuit  24  as a first peak-hold means, an operational amplifier  25  as a differential signal generator, and a peak-hold circuit  26  as a second peak-hold means. 
     In the amplitude detector  21 , a detected signal S 20  is inputted therein from one end of the capacitor  22 , the other end thereof being connected to the input terminal of the amplifier  23 . The output terminal of the amplifier  23  is connected to the “−” terminal of the operational amplifier  25  and the input terminal of the peak-hold circuit  24 . The output terminal of peak-hold circuit  24  is connected to the “+” terminal of the operational amplifier  25 . The output terminal of the operational amplifier  25  is connected to the input terminal of the peak-hold circuit  26 . From the output terminal of the peak-hold circuit  26 , an amplitude detect signal S 21  is outputted. 
     In the amplitude detector  21 , an AC component S 22  of the detected signal S 20  is amplified by the amplifier  23 . The amplified AC component S 22  is inputted in the “−” terminal of the operational amplifier  25  and the input terminal of the peak-hold circuit  24  as a signal S 23  having a waveform shown in FIG.  2 A. Then, from the peak-hold circuit  24 , a peak voltage signal S 24  shown in FIG. 2A having the peak-hold waveform of the signal S 23  is outputted to the “+” terminal of the operational amplifier  25 . Next, from the output terminal of the operational amplifier  25 , a differential signal S 25  having a waveform shown in FIG. 2B corresponding to the differential voltage between the peak voltage signal S 24  and the signal S 23  is outputted to the input terminal of the peak-hold circuit  26 . Then, from the peak-hold circuit  26 , a peak-voltage signal S 21  shown in FIG. 2B having the peak-hold waveform of the differential signal S 25  is outputted. 
     In the amplitude detector  21 , if the duty ratio of the signal S 23  varies to vary an DC offset, the waveform of the peak voltage signal  524  follows the peak value of the signal S 23 . Therefore, in the operational amplifier  25 , obtaining the difference between the peak voltage signal S 24  and the signal S 23  can obtain the differential signal S 25  indicative of the potential of the signal S 23  relative to the peak voltage signal S 24 . In the differential signal  525 , the DC offset is canceled. Therefore, the amplitude detect signal S 21  having the peak-hold waveform of the differential signal S 25  correctly reflects the amplitude of the signal S 23  relative to the output potential (“0” shown in FIGS. 2A and 29) of the amplitude detect signal S 21  when the amplitude of the signal S 23  is zero. 
     Second Preferred Embodiment: 
     In the amplitude detector  21  shown in FIG. 1, there occurs a slight deviations between the peak voltage of the signal S 23  and the peak voltage signal S 24 , and between the peak voltage of the signal S 25  and the amplitude detect signal S 21  because of the asymmetry between the outputs of the amplifier and peak-hold circuit  24  or the response frequency limit of peak-hold circuit  26  for example. These deviations are made obvious when the period of the detected signal S 20  is relatively short, thereby lowering amplitude measuring accuracy. An amplitude detector practiced as the second preferred embodiment of the invention is intended to reduce the effect of the deviation in peak between the signals. 
     FIG. 3 shows a constitution of the amplitude detector  31  practiced as the third preferred embodiment. As shown, the amplitude detector  31  comprises amplitude detecting circuits  33  and  34  and an operational amplifier  27 . In the amplitude detector  31 , a detected signal S 20  is inputted in the amplitude detecting circuit  33 . From the amplitude detecting circuit  33 , an amplitude detect signal S 26   a  is inputted in the “+” terminal of the operational amplifier  27  At the same time, a reference signal S 32  is inputted in the amplitude detecting circuit  34 . From the amplitude detecting circuit  34 , an amplitude detect signal S 26   b  is inputted in the “−” terminal of the operational amplifier  27 . The reference signal S 32  has a frequency approximately the same as the frequency of the detected signal S 20  and an amplitude approximately the same as an amplitude expected of the detected signal S 20 . From the operational amplifier  27 , an amplitude detect signal S 31  equivalent to the differential voltage between the amplitude detect signals S 26   a  and S 26   b  is outputted. 
     The amplitude detecting circuit  33  has generally the same constitution as that of the amplitude detector  21  shown in FIG.  1 . The amplitude detecting circuit  34  has generally the same constitution as that of the amplitude detector  21  shown in FIG. 1 except that the capacitor  22  is not provided. 
     To be more specific, the amplifiers  23   a  and  23   b  shown in FIG. 3 are the same the amplifier  23  shown in FIG.  1 . The peak-hold circuits  24   a  and  24   b  are the same as the peak-hold circuit  24  shown in FIG.  1 . The operational amplifiers  25   a  and  25   b  are the same as the operational amplifier  25  shown in FIG.  1 . The peak-hold circuits  26   a  and  26   b  are the same as the peak-hold circuit  26  shown in FIG.  1 . 
     In the amplitude detector  31 , if the detected signal S 20  is a high-frequency signal, the effect of the deviation in peak between the input and output signals of the peak-hold circuit as described above appears on both the amplitude detect signals S 26   a  and S 26   b  equally. 
     Therefore, differentially amplifying the amplitude detect signals S 26   a  and S 26   b  through the operational amplifier  27  can detect with a high precision the amplitude of the detected signal S 20  with reference to the amplitude of the reference signal S 32 . 
     Third Preferred Embodiment: 
     FIG. 4 shows a specific circuit of the amplitude detector  31  shown in FIG.  3 . As shown, an amplifier  23   a  of the amplitude detector  31  is composed of a npn-channel transistors Q 1  and Q 2 , resistors R 1 , R 2 , and R 3 , and constant current sources I 1  and I 2 . The base of the transistor Q 2  is applied with a constant potential equal to the bias of the transistor Q 1 , for example, Vcc/2, and a differential signal having the same bias as that of the signal of the transistor Q 1  but having the reverse signal polarity. The collectors of the transistors Q 1  and Q 2  are connected to a power supply line  40  through the resistors R 1  and R 2  respectively. The power supply line  40  is held a supply voltage Vcc. The base of the transistor Q 1  is applied with a detected signal S 20  through a capacitor  22 . The collector of the transistor Q 2  is connected to the base of the transistor Q 3 . The emitters of Q 1  and Q 2  are connected across R 3 . The collector of the transistor Q 3  is connected to the power supply line  40  and the emitter of this transistor is connected to ground through a constant current source I 3 . The emitter of the transistor Q 3  is connected to the base of a transistor Q 6 . 
     The peak-hold circuit  24   a  is composed of a transistor Q 4 , a capacitor C 1 , and a constant current source I 4 . The collector of the transistor Q 4  is connected to the power supply line  40 . The base of this transistor is connected to the collector of the transistor Q 3 . The emitter of this transistor is connected to ground through the constant current source I 4 . One end of the capacitor C 1  is connected to the power supply line  40  and the other end to the emitter of the transistor Q 4  and the base of a transistor Q 5 . 
     The operational amplifier  25   a  is composed of transistors Q 5  and Q 6 , resistors R 4  and R 5 , and a constant current source I 5 . The collector of the transistor Q 6  is connected to the power supply line  40 . The emitter of this transistor is connected to the emitter of the transistor Q 5  through the resistor R 4 . The emitter of the transistor Q 6  is connected to ground through the constant current source I 5 . The base of the transistor Q 6  is applied with a signal S 23   a  through the transistor Q 3   31 . The collector of the transistor Q 5  is connected to the power supply line  40  through the resistor R 5 . 
     The peak-hold circuit  26   a  is composed of a transistor Q 7 , a capacitor C 2 , and a constant current source I 6 . The base of the transistor Q 7  is connected to the collector of the transistor Q 5 . The collector of the transistor Q 7  is connected to the power supply line  40 . The base of this transistor is connected to ground through the constant current source I 6 . One end of the capacitor C 2  is connected to the power supply line  40  and the other end to the emitter of the transistor Q 7  and the “+” terminal of the operational amplifier  27 . 
     Referring to FIG. 4, the resistance value of each of the resistors R 1 , R 2 , and R 3  is  1  kΩ. The resistance value of each of the resistors R 4  and R 5  is  2  kΩ. Each of the constant current sources I 1 , I 2 , and I 3  outputs a constant current of  250  μA. Each of the constant current sources I 4  and I 6  outputs a constant current of  4  μA. The constant current source I 5  outputs a constant current of  500  μA. The amplitude detecting circuit  34  has generally the same constitution as that of the amplitude detecting circuit  33  shown in FIG. 3 except that the capacitor  22  is not provided. 
     In the amplitude detecting circuit  33  of the amplitude detector  31  shown in FIG. 4, the DC component of the detected signal S 20  is removed by the capacitor  22  and the AC component S 22  of this signal is applied to the base of the transistor Q 1  to be amplified. The amplified AC component S 22  is then applied to the bases of the transistors Q 3  and Q 4  as a signal S 23   a . The peak potential of the signal S 23   a  is applied to the base of the transistor Q 5  as a peak voltage signal S 24   a  corresponding to the stored charge of the capacitor C 1  of the peak-hold circuit  24   a . The signal S 23   a  is then applied from the emitter of the transistor Q 3  to the base of the transistor Q 6 . 
     Next, the peak voltage signal S 24   a  indicative of the peak potential of the signal S 23   a  and the signal S 23   a  are differentially amplified by the operational amplifier  25   a . A resultant differential signal S 25   a  is applied to the base of the transistor Q 7 . The peak potential of the differential signal S 25   a  is inputted to the “+” terminal of the operational amplifier  27  as an amplitude detect signal S 26   a  corresponding to the stored charge of the capacitor C 2  of the peak-hold circuit  26   a . Namely, if the DC balance of the signal S 23   a  is not kept, the base line fluctuates. Therefore, the absolute value of the peak voltage signal S 24   a  indicative of the peak of the signal S 23   a  does not represent the amplitude of the signal S 23   a . At this moment, the interval between the potential at the bottom of the waveform of the signal S 23   a  and the potential of the peak voltage signal S 24   a  represents the amplitude. Consequently, the peak potential of the differential signal S 25   a  obtained by rolling back the signal S 23   a  relative to the peak voltage signal S 24   a  that represents the amplitude. 
     On the other hand, in the amplitude detecting circuit  34 , the same processing as that executed on the detected signal S 20  in the amplitude detecting circuit  33  is executed on the reference signal S 32 . A resultant amplitude detect signal S 26   b  is outputted to the “−” terminal of the operational amplifier  27 . Then, an amplitude detect signal S 31  equivalent to the differential voltage between the amplitude detect signal  26   a  and the amplitude detect signal S 26   b  is outputted from the operational amplifier  27 . 
     Fourth Preferred Embodiment 
     The following describes an equalizer that incorporates the above-mentioned amplitude detector. FIG. 5 shows a constitution of an equalizer  51  practiced as a fourth preferred embodiment of the invention. As shown, the equalizer  51  comprises an BEA (High Emphasis Amplifier)  70 , a signal detector  57 , the amplitude detector  31  functioning as an AGC (Automatic Gain Control), a QFB (Quantization Feedback Comparator), and an amplifier  62 . The equalizer  51  is installed in a receiver for example. A video signal IN representing R, G, B is inputted in the equalizer  51  through a copper monitor cable. A quantizing feedback signal OUT and a serial data SD are outputted from the equalizer  51  accordingly. 
     The HEA  70  has a three-pole HPF (High Pass Filter)  52 , a linear amplifier  53 , an amplifier  54 , and a superimposing circuit  55 . In the HEA  70 , the high-frequency component of the inputted video signal IN is extracted by the HPF  52 . The extracted high-frequency component is amplified by the amplifier  54  to be inputted in the superimposing circuit  55  as a signal S 54 . At this moment, the amplification factor of the amplifier  54  is determined by the amplitude detect signal S 31  functioning as a amplification factor control signal from the amplitude detector  31 . This automatically controls the gain of the signal S 54 . At the same time, the video signal IN is linear-amplified by the linear amplifier  53  into a signal S 53 , which is inputted to the superimposing circuit  55 . In the superimposing circuit  55 , the signal S 54  and the signal S 53  are superimposed on each other. A resultant superimposed signal S 55  is inputted in the amplitude detecting circuit  33  of the amplitude detector  31  and the QFB  61 . This compensates the high-frequency component lost in cable attenuation. 
     The QFB  61  is a comparator that operates with reference to not DC center but amplitude center. Therefore, the QFB  61  compares the superimposed signal S 55  with a predetermined reference value to generate the quantization feedback signal OUT. The quantization feedback signal OUT is used as a digital signal identified by compensating the signal distorted by copper wire transmission. Namely, if the duty ratio of the superimposed signal S 55  is small, a location at which area S+ of “+” region matches area S− of “−” region in a waveform shown in FIG. 6 becomes the DC center (V=0). In the QFB  61 , amplitude center −V 1 , which is the center potential of waveform amplitude provides a threshold. 
     The amplitude detector  31  is the circuit shown in FIGS. 3 and 4. The superimposed circuit signal S 55  and, through the amplifier  62 , the reference signal S 32  are inputted in the amplitude detector  31  to generate the amplitude detect signal S 31 . This amplitude detect signal S 31  is inputted in the amplifier  54  and the signal detector  57 . 
     The signal detector  57  detects that the output of the amplitude detector  31  is a desired value or higher and generates the signal detect output SD. 
     According to the equalizer  51 , precision amplitude detection is performed in the amplitude detector  31 , so that the quantization feedback signal OUT and the signal detect output SD can be generated with great precision. 
     The present invention is not limited to the above-mentioned embodiments. For example, the amplitude detector  21  shown in FIG. 1 can be implemented by not only the circuit constitution shown in FIG. 3 but also any other circuit constitution having the equivalent capabilities. In addition, the amplitude detector  21  may be incorporated in not only the equalizer  51  shown in FIG. 3 but also an AGC for example. 
     As described, the amplitude detector according to the invention can properly detect the amplitude of a detected signal. According to the equalizer according to the invention, an attenuated input signal can be compensated with great precision. 
     While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.