Abstract:
Provided is an etching-before-packaging horizontal chip three-dimensional system level metal circuit board structure comprising a metal substrate frame; the metal substrate frame is provided with base islands and pins therein; the front faces of the base islands are provided with chips; the front faces of the chips are connected to the front faces of the pins via metal wires; conductive posts are disposed on the front faces or back faces of the pins; the peripheral areas of the base islands, the areas between the base islands and the pins, the areas between the pins, the areas above the base islands and the pins, the areas below the base islands and the pins, and the exteriors of the chips, the metal wires and the conductive posts are all encapsulated with molding compound.

Description:
[0001]    This application claims priority to Chinese Patent Application No. 201310339322.4 titled “ETCHING-FIRST-PACKAGING-SECOND UPSIDE-UPWARD-INSTALLATION THREE-DIMENSIONAL SYSTEM-IN-PACKAGE METAL CIRCUIT WIRING BOARD STRUCTURE AND PROCESS METHOD” and filed with the Chinese State Intellectual Property Office on Aug. 6, 2013, which is incorporated herein by reference in its entirety. 
       FIELD 
       [0002]    The present disclosure relates to an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure and a method therefor, first-etched and later-packaged wiring which relates to the technical field of semiconductor packaging. 
       BACKGROUND 
       [0003]    Conventional techniques for fabricating a metal lead frame include the following methods. 
         [0004]    1) In mechanical punching technology, a metal sheet is punched by a top blade and a bottom blade from top to bottom or from bottom to top longitudinally, so that a die pad for carrying a chip, an inner lead for signal transmission and an outer lead connected to an external PCB (Printed Wiring Board) can be formed in a lead frame in the metal sheet, and afterwards a metallic electroplated coating is coated on specific regions of the inner lead(or) and the die pad, to form a useable lead frame (referring to  FIGS. 76 to 78 ). 
         [0005]    2) In chemical etching technology, exposing, developing, windowing and chemical etching are performed on a metal sheet, so that a die pad for carrying a chip, an inner lead for signal transmission and an outer lead connected to an external PCB can be formed in a lead frame in the metal sheet, and afterwards a metallic electroplated coating is coated on specific regions of the inner lead and(or) the die pad, to form a useable lead frame (referring to  FIG. 79  to  80 ). 
         [0006]    3) Based on method 1) and method 2), another method further includes pasting a high temperature adhesive film with resistance to 260 degrees Celsius on the back of the lead frame which already includes the die pad for carrying a chip, the inner lead for signal transmission, the outer lead connected to an external PCB and the metallic electroplated coating on specific regions of the inner lead and(or) the die pad, to form a lead frame which can be used in a quad no-lead package and a scale plastic package (referring to  FIG. 81 ). 
         [0007]    4) Based on method 1) and method 2), another method further includes prepackaging the lead frame which includes the die pad for carrying a chip, the inner lead for signal transmission, the outer lead connected to an external PCB and metallic electroplated coating on specific regions of the inner lead and the die pad, and filling punched or chemically etched regions in the metal sheet with a thermoset epoxy resin, to form a pre-filled lead frame which can be used in a quad no-lead package and a scale plastic package and a package with copper wire bonding (referring to  FIG. 82 ). 
         [0008]    The disadvantages of the conventional technique are described as follows. 
         [0009]    1) Lead Frame Formed through Mechanical Punching 
         [0010]    a. In mechanical punching, a top blade and a bottom blade punch from top to bottom or from bottom to top to form a vertical section, thus any other function or component cannot be embedded into the lead frame, for example, a system object can not be integrated into the metal lead frame. 
         [0011]    b. in mechanical punching, an edge of a metal sheet is extruded through a top blade and a bottom blade to form a extended metallic region, and length of the extended metallic region formed through extrusion can only be 80% of thickness of the lead frame at most. In a case that the length is larger than 80% of the thickness of the lead frame, the extended metallic region formed through extrusion is prone to problems such as a warpage, a subfissure, a rupture, an irregular shape and a surface hole, and an ultrathin lead frame is more prone to these problems (referring to  FIGS. 85 to 86 ). 
         [0012]    c. In a case that the length of the extended metallic region formed through mechanical punching is smaller than or exactly 80% of the thickness of the lead frame, the extended length is not enough for embedding a related object in the extended metallic region, especially for an ultrathin lead frame (referring to  FIGS. 85 and 86 ). 
         [0013]    2) Lead Frame formed through Chemical Etching 
         [0014]    a. In chemical etching, space for embedding a component can be obtained through partial-etching, and the major disadvantage thereof is the difficulty to control a etching depth and a flatness of an etched plane. 
         [0015]    b. After partially-etched regions for embedding components are formed in a metal sheet, a structural strength of the lead frame becomes very small, which will directly influence operation conditions (such as, pick-and-place, transportation, a high temperature, high pressure and thermal shrinkage) required for embedding an object later. 
         [0016]    c. The lead frame formed through chemical etching can only present a pattern of an outer lead or an inner lead on the top surface and the back of the lead frame, and cannot present a system-in-package metal lead frame with a multilayer three-dimensional metal wiring. 
       SUMMARY 
       [0017]    In order to overcome the disadvantages above, an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure and a method therefor are provided, which can improve the functionality and application performance of a conventional metal lead frame limited by that a component can not be embedded in the metal lead frame. 
         [0018]    A method for manufacturing a first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board is provided. The method includes: 
         [0019]    step 1, providing a metal substrate; 
         [0020]    step 2, pre-plating a surface of the metal substrate with a micro copper layer; 
         [0021]    step 3, applying with a photoresist film, 
         [0022]    wherein a photoresist film which is able to be exposed and developed is pasted on a top surface and a bottom surface of the metal substrate pre-plated with the micro copper layer; 
         [0023]    step 4, removing a part of the photoresist film on the bottom surface of the metal substrate, 
         [0024]    wherein the bottom surface of the metal substrate, which has been pasted with the photoresist film in step 3, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be plated later; 
         [0025]    step 5, plating with a metal wiring layer, 
         [0026]    wherein the region of the bottom surface of the metal substrate from which the part of the photoresist film has been removed in step 4 is plated with the metal wiring layer; 
         [0027]    step 6, applying with a photoresist film, 
         [0028]    wherein the bottom surface of the metal substrate in step 5 is pasted with the photoresist film which can be exposed and developed; 
         [0029]    step 7, removing a part of the photoresist film on the bottom surface of the metal substrate, 
         [0030]    wherein the bottom surface of the metal substrate, which has been pasted with the photoresist film in step 6, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be plated later; 
         [0031]    step 8, plating with a high-conductivity metal wiring layer, 
         [0032]    wherein the region of the bottom surface of the metal substrate from which the part of the photoresist film has been removed in step 7 is plated with the high conductivity metal wiring layer; 
         [0033]    step 9, removing the photoresist film, 
         [0034]    wherein the photoresist film on the surface of the metal substrate is removed; 
         [0035]    step 10, molding with an epoxy resin, 
         [0036]    wherein the molding with the epoxy resin for protection is performed on a surface of the metal wiring layer on the bottom surface of the metal substrate; 
         [0037]    step 11, grinding a surface of the epoxy resin, 
         [0038]    wherein the surface of the epoxy resin is ground after the molding with the epoxy resin has been performed; 
         [0039]    step 12, applying with a photoresist film, 
         [0040]    wherein the top surface and the bottom surface of the metal substrate are applied with the photoresist film which can be exposed and developed after the surface of the epoxy resin has been ground in step 11; 
         [0041]    step 13, removing a part of the photoresist film on the top surface of the metal substrate, 
         [0042]    wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 12, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be etched later; 
         [0043]    step 14, chemical etching, 
         [0044]    wherein the chemical etching is performed in the region of the top surface of the metal substrate in which exposing and developing have been performed in step 13; 
         [0045]    step 15, plating with a metal layer, 
         [0046]    wherein the top surface of the metal substrate on which the chemical etching has been performed in step 14 is plated with the metal layer, so that a die pad and a lead are formed on the metal substrate; 
         [0047]    step 16, applying with a photoresist film, 
         [0048]    wherein the top surface and the bottom surface of the metal substrate are applied with the photoresist film which can be exposed and developed after the plating with the metal layer has been performed in step 15; 
         [0049]    step 17, removing a part of the photoresist film on the top surface of the metal substrate, 
         [0050]    wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 16, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later; 
         [0051]    step 18, plating with a metal pillar, 
         [0052]    wherein the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 17 is plated with the metal pillar; 
         [0053]    step 19, removing the photoresist film, 
         [0054]    wherein the photoresist film on the surface of the metal substrate is removed; 
         [0055]    step 20, coating with an adhesive material, 
         [0056]    wherein a top surface of the die pad is coated with a conductive or non-conductive adhesive material after the die pad has been formed in step 15; 
         [0057]    step 21, bonding dies, 
         [0058]    wherein a chip is bonded in the conductive or non-conductive adhesive material in step 20; 
         [0059]    step 22, bonding a metal wire, 
         [0060]    wherein the metal wire is bonded between a top surface of the chip and a top surface of the lead; 
         [0061]    step 23, encapsulating, 
         [0062]    wherein the molding with a molding material is performed on the top surface of the metal substrate in step 22; 
         [0063]    step 24, grinding a surface of an epoxy resin, 
         [0064]    wherein the surface of the epoxy resin is ground after the molding with the epoxy resin has been performed in step 23; and 
         [0065]    step 25, plating with an anti-oxidizing metal layer or coating with an antioxidant, 
         [0066]    wherein an exposed surface of the metal substrate is plated with the anti-oxidizing metal layer or is coated with the antioxidant after the surface of the epoxy resin has been ground in step 24. 
         [0067]    Step 15 is performed between step 4 and step 5. 
         [0068]    A first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure includes a metal substrate frame, where a die pad and a lead are provided in the metal substrate frame, a chip is provided on a top surface or a bottom surface of the die pad via a conductive or nonconductive material, the top surface of the chip and the top surface of the lead are connected through a metal wire, a conductive pillar is provided on the top surface or the bottom surface of the lead, and a peripheral region of the die pad, a region between the die pad and the lead, a region between the lead and another lead, an upper region of the die pad and the lead, a lower region of the die pad and the lead, and the chip, the metal wire and the conductive pillar are encapsulated, with a molding material being flush with a top of the conductive pillar, and surfaces of the metal substrate frame, the lead and the conductive pillar exposed from the molding material being plated with an anti-oxidizing layer or being coated with an antioxidant. 
         [0069]    A first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure includes a metal substrate frame and a chip, where a lead is provided in the metal substrate frame, the chip is provided on a top surface of the lead or between the lead and another lead via a conductive or nonconductive adhesive material, a top surface of the chip and the top surface of the lead are connected through a metal wire, and a conductive pillar is provided on the top surface or a bottom surface of the lead, a region between the lead and another lead, an upper region of the lead, an lower region of the lead, and a peripheral region of the chip, the metal wire and the conductive pillar are encapsulated, with a molding material being flush with a top of the conductive pillar, and surfaces of the metal substrate frame, the lead and the conductive pillar exposed from the molding material being plated with an anti-oxidizing layer or being coated with an antioxidant (OSP). 
         [0070]    A passive device is connected across the lead and another lead via a conductive adhesive material, the passive device is connected across the top surface of the lead and the top surface of another lead, or across the bottom surface of the lead and the bottom surface of another lead. 
         [0071]    There are a plurality of rings of the conductive pillars. 
         [0072]    A second chip is provided on the top surface of the chip via a conductive or nonconductive adhesive material, and the top surface of the second chip and the lead are connected through a metal wire. 
         [0073]    A second conductive pillar is provided on the top surface or the bottom surface of the lead, a second chip is flipped on the second conductive pillar via a conductive material, and the second conductive pillar and the second chip are provided inside the molding material. 
         [0074]    A second conductive pillar is provided on the top surface or the bottom surface of the lead, a passive device is provided on the second conductive pillar, and the second conductive pillar and the passive device are provided inside the molding material. 
         [0075]    A method for manufacturing a first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board is provided. The method includes: 
         [0076]    step 1, providing a metal substrate; 
         [0077]    step 2, pre-plating a surface of the metal substrate with a micro copper layer; 
         [0078]    step 3, applying with a photoresist film, 
         [0079]    wherein a top surface and a bottom surface of the metal substrate which have been pre-plated with the micro copper layer are respectively applied with the photoresist film which can be exposed and developed; 
         [0080]    step 4, removing a part of the photoresist film on the top surface of the metal substrate, 
         [0081]    wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 3, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later; 
         [0082]    step 5, plating with a first metal wiring layer, 
         [0083]    wherein the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 4 is plated with the first metal wiring layer; 
         [0084]    step 6, applying with a photoresist film, 
         [0085]    wherein the top surface of the metal substrate in step 5 is applied with the photoresist film which can be exposed and developed; 
         [0086]    step 7, removing a part of the photoresist film on the top surface of the metal substrate, 
         [0087]    wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 6, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later; 
         [0088]    step 8, plating with a second metal wiring layer, 
         [0089]    wherein the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 7 is plated with the second metal wiring layer, which serves as a conductive pillar to connect the first metal wiring layer to a third metal wiring layer; 
         [0090]    step 9, removing the photoresist film, 
         [0091]    wherein the photoresist film on the surface of the metal substrate is removed; 
         [0092]    step 10, applying with a non-conductive adhesive film, 
         [0093]    wherein the top surface of the metal substrate is applied with a layer of the non-conductive adhesive film; 
         [0094]    step 11, grinding a surface of the non-conductive adhesive film, 
         [0095]    wherein the surface of the non-conductive adhesive film is ground after the applying the non-conductive adhesive film has been performed; 
         [0096]    step 12, performing metallization pretreatment on the surface of the non-conductive adhesive film, 
         [0097]    wherein the metallization pretreatment is performed on the surface of the non-conductive adhesive film; 
         [0098]    step 13, applying with a photoresist film, 
         [0099]    wherein the top surface and the bottom surface of the metal substrate in step 12 are applied with the photoresist film which can be exposed and developed; 
         [0100]    step 14, removing a part of the photoresist film on the top surface of the metal substrate, 
         [0101]    wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 13, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be etched later; 
         [0102]    step 15, etching; 
         [0103]    wherein the etching is performed in a region from which the part of the photoresist film has been removed in step 14; 
         [0104]    step 16, removing the photoresist film on the top surface of the metal substrate, 
         [0105]    wherein the photoresist film on the top surface of the metal substrate is removed, so as to expose a metallized region to be plated later; 
         [0106]    step 17, plating with a third metal wiring layer, 
         [0107]    wherein the top surface of the metal substrate in step 16 is plated with the third metal wiring layer; 
         [0108]    step 18, applying with a photoresist film, 
         [0109]    wherein the top surface of the metal substrate in step 17 is applied with the photoresist film which can be exposed and developed; 
         [0110]    step 19, removing a part of the photoresist film on the top surface of the metal substrate, 
         [0111]    wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 18, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later; 
         [0112]    step 20, plating with a fourth metal wiring layer, 
         [0113]    wherein the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 19 is plated with the fourth metal wiring layer, which serves as a conductive pillar to connect the third metal wiring layer to a fifth metal wiring layer; 
         [0114]    step 21, removing the photoresist film, 
         [0115]    wherein the photoresist film on the surface of the metal substrate is removed; 
         [0116]    step 22, applying with a non-conductive adhesive film, 
         [0117]    wherein the top surface of the metal substrate is applied with a layer of the non-conductive adhesive film; 
         [0118]    step 23, grinding a surface of the non-conductive adhesive film, 
         [0119]    wherein the surface of the non-conductive adhesive film is ground after the applying the non-conductive adhesive film has been performed; 
         [0120]    step 24, performing metallization pretreatment on the surface of the non-conductive adhesive film, 
         [0121]    wherein the metallization pretreatment is performed on the surface of the non-conductive adhesive film; 
         [0122]    step 25, applying with a photoresist film, 
         [0123]    wherein the top surface and the bottom surface of the metal substrate in step 24 are applied with the photoresist film which can be exposed and developed; 
         [0124]    step 26, removing a part of the photoresist film on the bottom surface of the metal substrate, 
         [0125]    wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 25, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be etched later; 
         [0126]    step 27, etching; 
         [0127]    wherein the etching is performed in a region from which the part of the photoresist film has been removed in step 26; 
         [0128]    step 28, removing the photoresist film on the top surface of the metal substrate, 
         [0129]    wherein the photoresist film on the top surface of the metal substrate is removed; 
         [0130]    step 29, plating with a fifth metal wiring layer, 
         [0131]    wherein the top surface of the metal substrate in step 28 is plated with the fifth metal wiring layer, so that a die pad and a lead are formed on the metal substrate; 
         [0132]    step 30, applying with a photoresist film, 
         [0133]    wherein the top surface of the metal substrate in step 29 is applied with the photoresist film which can be exposed and developed; 
         [0134]    step 31, removing a part of the photoresist film on the bottom surface of the metal substrate, 
         [0135]    wherein the bottom surface of the metal substrate, which has been applied with the photoresist film in step 30, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be etched later; 
         [0136]    step 32, chemical etching; 
         [0137]    wherein the chemical etching is performed in a region on the bottom surface of the metal substrate in which exposing and developing have been performed in step 31, till the metal wiring layer is reached; 
         [0138]    step 33, applying with a photoresist film, 
         [0139]    wherein the bottom surface of the metal substrate on which the chemical etching has been performed in step 32 is applied with the photoresist film which can be exposed and developed; 
         [0140]    step 34, removing a part of the photoresist film on the bottom surface of the metal substrate, 
         [0141]    wherein the bottom surface of the metal substrate, which has been applied with the photoresist film in step 33, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be plated later; 
         [0142]    step 35, plating with a metal pillar, 
         [0143]    wherein the region of the bottom surface of the metal substrate from which the part of the photoresist film has been removed in step 34 is plated with the metal pillar; 
         [0144]    step 36, removing the photoresist film, 
         [0145]    wherein the photoresist film on the surface of the metal substrate is removed; 
         [0146]    step 37, coating with an adhesive material; 
         [0147]    wherein a bottom surface of the die pad is coated with a conductive or non-conductive adhesive material after the photoresist film on the surface of the metal substrate has been removed in step 36; 
         [0148]    step 38, bonding dies, 
         [0149]    wherein a chip is bonded in the conductive or non-conductive adhesive material in step 37; 
         [0150]    step 39, bonding a metal wire, 
         [0151]    wherein the metal wire is bonded between a top surface of the chip and a top surface of the lead; 
         [0152]    step 40, encapsulating, 
         [0153]    wherein the molding with epoxy resin, which is commonly known as a molding material, is performed on the bottom surface of the metal substrate in step 39; 
         [0154]    step 41, grinding a surface of the epoxy resin, 
         [0155]    wherein the surface of the epoxy resin is ground after the molding with the epoxy resin has been performed in step 40; 
         [0156]    step 42, plating with an anti-oxidizing metal layer or coating with an antioxidant, 
         [0157]    wherein an exposed surface of the metal substrate is plated with the anti-oxidizing metal layer or is coated with the antioxidant after the surface of the epoxy resin has been ground in step 41. 
         [0158]    The steps 6 to 17 are repeated for times to form more metal wiring layers. 
         [0159]    Compared with the prior art, the disclosure has the following beneficial effects. 
         [0160]    1) Currently, a metal lead frame is manufactured through mechanical punching or chemical etching, where multiple metal wiring layers can not be formed, and no object can be embedded in an interlayer in a metal lead frame manufactured through mechanical punching, while an object can be embedded in an interlayer in a three-dimensional metal wiring composite-type substrate according to the present disclosure. 
         [0161]    2) A heat conduction object or a heat dissipation object can be embedded as required at a position or in a region in the interlayer in the three-dimensional metal wiring composite-type substrate on a heat conduction or a heat dissipation requirement, to form a system-in-package metal lead frame with a good thermal property (referring to  FIG. 87 ). 
         [0162]    3) An active element or component or a passive component can be embedded as required at a position or in a region in the interlayer in the three-dimensional metal wiring composite-type substrate based on system and function requirements, to form a system-in-package metal lead frame. 
         [0163]    4) it can not be seen from an appearance of a final product of the three-dimensional metal wiring composite-type substrate that an object for system and function requirements is embedded in the interlayer. Especially for a silicon chip, the embedment can not be detected even through X-ray, thereby achieving a privacy and security of the system and function; 
         [0164]    5) Since the final product of the three-dimensional metal wiring composite-type substrate includes various components, an ultrathin package can be formed through cutting the three-dimensional metal wiring composite-type substrate in terms of each unit in a case of no subsequent second packaging. 
         [0165]    6) Second packaging can be performed on the three-dimensional metal wiring composite-type substrate besides embedding of an object, thereby achieving integration of system functions. 
         [0166]    7) Not only an object can be embedded in the three-dimensional metal wiring composite-type substrate, different unit packages or system-in-package can also be stacked on a periphery of a package of the three-dimensional metal wiring composite-type substrate, thereby achieving a dual-system package or a multi-system package. 
         [0167]    8) The three-dimensional metal wiring substrate can be applied to a multichip module (MCM) package (referring to  FIGS. 88 and 89 ), and has lower cost and higher toughness than a conventional MCM substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0168]    The embodiments of the disclosure are described in conjunction with drawings, so that the characteristics, advantages and object of the disclosure can be better understood. 
           [0169]      FIGS. 1 to 25  are diagrams of steps of a method for manufacturing a first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board of the present disclosure; 
           [0170]      FIG. 26  is a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal board structure according to the first embodiment of the disclosure; 
           [0171]      FIG. 27  is a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal board structure according to the second embodiment of the disclosure; 
           [0172]      FIG. 28  is a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal board structure according to the third embodiment of the disclosure; 
           [0173]      FIG. 29  is a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal board structure according to the fourth embodiment of the disclosure; 
           [0174]      FIG. 30  is a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal board structure according to the fifth embodiment of the disclosure; 
           [0175]      FIGS. 31 and 32  are diagrams of an first-etched and later-packaged normal chip three-dimensional system-in-package metal board structure according to the sixth embodiment of the disclosure; 
           [0176]      FIGS. 33 to 74  are flowcharts of processes for manufacturing an first-etched and later-packaged normal chip three-dimensional system-in-package metal board structure according to the seventh embodiment of the disclosure; 
           [0177]      FIG. 75  is a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal board structure according to the seventh embodiment of the disclosure; 
           [0178]      FIG. 76  is a diagram of a punching operation in the method for manufacturing a metal lead frame in the prior art; 
           [0179]      FIG. 77  is a diagram of a metal strip in manufacturing a metal lead frame in the prior art; 
           [0180]      FIG. 78  is a top surface view of a lead frame in manufacturing a metal lead frame in the prior art; 
           [0181]      FIG. 79  is a sectional view of a metal lead frame in processes of exposing, developing, windowing and etching in the prior art; 
           [0182]      FIG. 80  is a top surface view of a lead frame in manufacturing a metal lead frame in the prior art; 
           [0183]      FIG. 81  is a sectional view of a QFN (Quad Flat No-lead) package in manufacturing a metal lead frame in the prior art; 
           [0184]      FIG. 82  is a diagram of a pre-filled lead frame in manufacturing a metal lead frame in the prior art; 
           [0185]      FIG. 83  is a diagram of extruding with a top blade and a bottom blade to form an extended region in manufacturing a metal lead frame in the prior art; 
           [0186]      FIG. 84  is a diagram of a subfissure, a rupture and a warpage generated in extruding with a top blade and a bottom blade to form an extended region in manufacturing a metal lead frame in the prior art; 
           [0187]      FIG. 85  is a diagram of an extended region formed through extruding with a top blade and a bottom blade in manufacturing a metal lead frame in the prior art is smaller than 80% of length of a lead frame; 
           [0188]      FIG. 86  is a diagram of an extended region which is formed through extruding with a top blade and a bottom blade in manufacturing a metal lead frame in the prior art is smaller than 80% of length of a lead frame and is difficult for embedding an object; 
           [0189]      FIG. 87  is a diagram of a case that a heat conduction object or a heat dissipation object is embedded as required at a position or in a region in an interlayer in a three-dimensional metal wiring composite-type substrate on a heat conduction requirement or a heat dissipation requirement; 
           [0190]      FIG. 88  is a diagram of applying with a three-dimensional metal wiring substrate to a multichip module (MCM) package; and 
           [0191]      FIG. 89  is a top view for  FIG. 88 . 
       
    
    
       [0192]    In the drawings,  1  represents a metal substrate frame,  2  represents a die pad,  3  represents a lead,  4  represents a conductive or nonconductive adhesive material,  5  represents a chip,  6  represents a metal wire,  7  represents a conductive pillar,  8  represents a molding material,  9  represents an anti-oxidizing layer or an antioxidant,  10  represents a passive device,  11  represents an electrostatic discharge coil,  12  represents a second chip,  13  represents a second conductive pillar and  14  represents a conductive material. 
       DETAILED DESCRIPTION 
       [0193]    Technical solutions according to embodiments of the disclosure are described in detail hereinafter in conjunction with the drawings. It should be understood that the described embodiments are only a part rather than all of the embodiments according to the present disclosure. Other embodiments obtained by those skilled in the art based on the embodiments in the present disclosure without any creative work fall in the scope of protection of the present disclosure. An first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure and a method therefor are provided as follows. 
       A First Embodiment 
     Single-Layer Wiring, Single Normal Chip and Single Ring of Leads 
       [0194]    Referring to  FIG. 26 , a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure according to the first embodiment of the disclosure is shown. The structure includes a metal substrate frame  1 , where a die pad  2  and a lead  3  are provided in the metal substrate frame  1 , a chip  5  is provided on the top surface of the die pad  2  via a conductive or nonconductive adhesive material  4 , and the top surface of the chip  5  and the top surface of the lead  3  are connected through a metal wire  6 . A conductive pillar  7  is provided on the top surface of the lead  3 . A peripheral region of the die pad  2 , a region between the die pad  2  and the lead  3 , a region between the lead  3  and another lead  3 , a region above the die pad  2  and the lead  3 , a region below the die pad  2  and the lead  3 , and regions outside the chip  5 , the metal wire  6  and the conductive pillar  7  are encapsulated with a molding material  8 . The molding material  8  is flush with a top of the conductive pillar  7 . Surfaces of the metal substrate frame  1 , the die pad  2 , the lead  3  and the conductive pillar  7  exposed out of the molding material  8  are plated with an anti-oxidizing layer or are coated with an antioxidant (OSP)  9 . 
         [0195]    The process method includes steps 1 to 25. 
         [0196]    Step 1 may include providing a metal substrate. 
         [0197]    As illustrated in  FIG. 1 , a metal substrate with an appropriate thickness is provided. The metal substrate is only used as a transitive material for supporting a wiring layer structure in wiring fabrication and subsequent packaging. The metal substrate is mainly made of a metal material, where the metal material may be copper, iron, galvanized material, stainless steel, aluminum, any other conductive metal material or a conductive non-all-metal material. 
         [0198]    Step 2 may include pre-plating a surface of the metal substrate with a micro copper layer. 
         [0199]    As illustrated in  FIG. 2 , the surface of the metal substrate is pre-plated with the micro copper layer. Thickness of the micro copper layer ranges from 2 μm to 10 μm, where the micro copper layer may be thinner or thicker based on a functional requirement, to form a tight integration of the wiring layer and the metal substrate in subsequent wiring fabrication. The pre-plating may be implemented through chemical deposition or electrolytic plating. 
         [0200]    Step 3 may include applying a photoresist film. 
         [0201]    As illustrated in  FIG. 3 , a top surface and a bottom surface of the metal substrate which have been pre-plated with the micro copper layer are respectively applied with the photoresist film which can be exposed and developed. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0202]    Step 4 may include removing a part of the photoresist film on the bottom surface of the metal substrate. 
         [0203]    As illustrated in  FIG. 4 , the bottom surface of the metal substrate, which has been pasted with the photoresist film in step 3, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be plated later. 
         [0204]    Step 5 may include plating with a metal wiring layer. 
         [0205]    As illustrated in  FIG. 5 , wiring the bottom surface of the metal substrate in the region where the photoresist film is removed in step 4 is plated with a metal wiring layer. The metal wiring layer may be made of a material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold (plating thickness usually ranges from 5 μm to 20 μm and may be varied based on different properties), and of course any other conductive metal material may be feasible, without limitation to metal material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold. The plating may be implemented through chemical deposition or electrolytic plating. 
         [0206]    Step 6 may include applying a photoresist film. 
         [0207]    As illustrated in  FIG. 6 , the bottom surface of the metal substrate in step 5 is applied with the photoresist film which can be exposed and developed. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0208]    Step 7 may include removing a part of the photoresist film on the bottom surface of the metal substrate. 
         [0209]    As illustrated in  FIG. 7 , the bottom surface of the metal substrate, which has been pasted with the photoresist film in step 6, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be plated later. 
         [0210]    Step 8 may include plating with a high-conductivity metal wiring layer. 
         [0211]    As illustrated in  FIG. 8 , the bottom surface of the metal substrate in the region where the photoresist film is removed in step 7 is plated with a high-conductivity metal wiring layer. The high-conductivity metal wiring layer may be made of material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold, and of course any other conductive metal material may be feasible, without limitation to metal material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold. The plating may be implemented through chemical deposition or electrolytic plating. 
         [0212]    Step 9 may include removing the photoresist film. 
         [0213]    As illustrated in  FIG. 9 , the photoresist film on the surface of the metal substrate is removed. The photoresist film may be removed through softening with a chemical potion and then flushing with high-pressure water. 
         [0214]    Step 10 may include molding an epoxy resin. 
         [0215]    As illustrated in  FIG. 10 , the molding with the epoxy resin for protection is performed on surfaces of the metal wiring layer and the metal wiring layer with high-conductivity both of which are on the bottom surface of the metal substrate. An epoxy resin with or without a filler may be selected depending on a product property. The encapsulating may be implemented through pouring glue with a mold, spraying with a spray device, pasting a film or brush coating. 
         [0216]    Step 11 may include grinding a surface of the epoxy resin. 
         [0217]    As illustrated in  FIG. 11 , the surface of the epoxy resin is grinded after the molding with the epoxy resin, in order to expose, the metal wiring layer with high-conductivity for fabricating an outer lead, out of a surface of the plastic package, and control thickness of the epoxy resin. 
         [0218]    Step 12 may include applying a photoresist film. 
         [0219]    As illustrated in  FIG. 12 , the top surface and the bottom surface of the metal substrate are applied with the photoresist film which can be exposed and developed after the surface of the epoxy resin has been ground in step 11. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0220]    Step 13 may include removing a part of the photoresist film on the top surface of the metal substrate. 
         [0221]    As illustrated in  FIG. 13 , the top surface of the metal substrate, which has been applied with the photoresist film in step 12, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be etched later. 
         [0222]    Step 14 may include performing chemical etching. 
         [0223]    As illustrated in  FIG. 14 , chemical etching is performed on the top surface of the metal substrate in a region exposed and developed in step 13, and is stopped until a metal wiring layer is reached. A chemical potion for etching may be copper chloride, ferric chloride or any other chemical potion available for chemical etching. 
         [0224]    Step 15 may include plating with a metal layer. 
         [0225]    As illustrated in  FIG. 15 , the top surface of the metal substrate on which the chemical etching has been performed in step 14 is plated with a metal layer, so that a die pad and a lead are formed on the metal substrate. The metal wiring layer may be made of material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold, and of course any other conductive metal material may be feasible, without limitation to metal material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold. The plating may be implemented through chemical deposition or electrolytic plating. 
         [0226]    Step 16 may include applying a photoresist film. 
         [0227]    As illustrated in  FIG. 16 , the top surface and the bottom surface of the metal substrate are applied with the photoresist film which can be exposed and developed after the plating with the metal layer has been performed in step 15. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0228]    Step 17 may include removing a part of the photoresist film on the top surface of the metal substrate. 
         [0229]    As illustrated in  FIG. 17 , the top surface of the metal substrate, which has been applied with the photoresist film in step 16, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later. 
         [0230]    Step 18 may include plating with a metal pillar. 
         [0231]    As illustrated in  FIG. 18 , the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 17 is plated with the metal pillar. The metal pillar may be made of material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold, and of course any other conductive metal material may be feasible, without limitation to metal material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold. The plating may be implemented through chemical deposition or electrolytic plating. 
         [0232]    Step 19 may include removing the photoresist film. 
         [0233]    As illustrated in  FIG. 19 , the photoresist film on the surface of the metal substrate is removed. The photoresist film may be removed through softening with a chemical potion and then flushing with high-pressure water. 
         [0234]    Step 20 may include coating with an adhesive material. 
         [0235]    As illustrated in  FIG. 20 , a top surface of the die pad is coated with a conductive or non-conductive adhesive material after the die pad has been formed in step 15, for the purpose of integration of the die pad and a subsequently embedded chip. 
         [0236]    Step 21 may include bonding dies. 
         [0237]    As illustrated in  FIG. 21 , a chip is bonded in the conductive or nonconductive adhesive material in step 20. 
         [0238]    Step 22 may include bonding a metal wire. 
         [0239]    As illustrated in  FIG. 22 , the metal wire is bonded between a top surface of the chip and a top surface of the lead. The metal wire may be made of gold, silver, copper, aluminum or alloy, and a shape of the metal wire may be a filament or a strip. 
         [0240]    Step 23 may include encapsulating. 
         [0241]    As illustrated in  FIG. 23 , the molding with a molding material is performed on the top surface of the metal substrate in step 22. The molding may be implemented through pouring glue with a mold, spraying with a spray device, or pasting a film. The molding material may be an epoxy resin with or without a filler. 
         [0242]    Step 24 may include grinding a surface of the epoxy resin. 
         [0243]    As illustrated in  FIG. 24 , the surface of the epoxy resin is grinded after the molding with the epoxy resin has been performed in step 23, in order to expose the metal pillar out of the surface of the plastic package, and control thickness of the epoxy resin. 
         [0244]    Step 25 may include plating with an anti-oxidizing metal layer or coating with an antioxidant OSP. 
         [0245]    As illustrated in  FIG. 25 , an exposed surface of the metal substrate is plated with the anti-oxidizing metal layer such as gold, nickel-gold, nickel-palladium-gold or tin, or is coated with the antioxidant (OSP), after the surface of the epoxy resin has been ground in step 24. 
       A Second Embodiment 
     Multiple Rings of Leads, Single Normal Chip, Passive Device and Electrostatic Discharge Coil 
       [0246]    Referring to  FIG. 27 , a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure according to the second embodiment is shown. The second embodiment differs from the first embodiment in that: there are multiple rings of conductive pillars  7 , a passive device  10  is connected across the lead  3  and another lead  3  via a conductive adhesive material, and an electrostatic discharge coil  11  is provided between a die pad  2  and the lead  3 . The top surface of the electrostatic discharge coil  11  and the top surface of the chip  5  are connected through a metal wire  6 , and the passive device  10  may be connected across the top surface of the lead  3  and the top surface of another lead  3 , across the top surface of the lead  3  and the top surface of the electrostatic discharge coil  11 , or across the top surface of the die pad  2  and the top surface of the electrostatic discharge coil  11 . 
       A Third Embodiment 
     Single Ring of Leads, Multiple Tiled Die Pads, and Multiple Normal Chips 
       [0247]    Referring to  FIG. 28 , a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure according to the third embodiment of the disclosure is shown. The third embodiment differs from the first embodiment in that: there are multiple die pads  2 , and a chip  5  is provided on each of the die pads  2  via a conductive or nonconductive adhesive material  4 , and the top surface of the chip  5  and the top surface of another chip  5  are connected through a metal wire  6 . 
       A Fourth Embodiment 
     Single Ring of Leads, Multiple Stacked Normal Chips 
       [0248]    Referring to  FIG. 29 , a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure according to the fourth embodiment of the disclosure is shown. The fourth embodiment differs from the first embodiment in that: a second chip  12  is provided on the top surface of the chip  5  via a conductive or nonconductive adhesive material  4 , and the top surface of the second chip  12  and the top surface of the lead  3  are connected through a metal wire  6 . 
       A Fifth Embodiment 
     Single Ring of Leads, Multiple Stacked Normal and Flipped Chips 
       [0249]    Referring to  FIG. 30 , a diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure according to the fifth embodiment of the disclosure is shown. The fifth embodiment differs from the first embodiment in that: a second conductive pillar  13  is provided on the top surface of the lead  3 , and a second chip  12  is flipped on the second conductive pillar  13  via a conductive material  14 , and the second conductive pillar  13  and the second chip  12  are provided inside the molding material  8 . 
       A Sixth Embodiment 
       [0250]    No Die Pad, and Single Normal Chip 
         [0251]    Referring to  FIGS. 31 and 32 , diagrams of an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure according to the sixth embodiment of the disclosure are shown. The sixth embodiment differs from the first embodiment in that: the metal wiring board structure does not include a die pad  2 , and a chip  5  is provided on the top surface of the metal substrate  1  or between the top surface of the lead  3  and the top surface of another lead  3  via a conductive or nonconductive adhesive material  4 . 
       A Seventh Embodiment 
     Multiple Wiring Layers, Single Normal Chip, and Single Ring of Leads 
       [0252]    Referring to  FIG. 75 , a structural diagram of an first-etched and later-packaged normal chip three-dimensional system-in-package metal wiring board structure according to the seventh embodiment of the disclosure is shown. The seventh embodiment differs from embodiment 1 in that: the die pad  2  or the lead  3  includes multiple metal wiring layers, where two adjacent metal wiring layers are connected through a conductive pillar, a chip is provided on the back of the die pad  2  via a conductive or nonconductive material  4 , and a conductive pillar  7  is provided on the back of the lead  3 . 
         [0253]    A method therefor includes steps 1 to 42. 
         [0254]    Step 1 may include providing a metal substrate. 
         [0255]    As illustrated in  FIG. 33 , a metal substrate with an appropriate thickness is provided. The metal substrate is only used as a transitive material for supporting a wiring layer structure in wiring fabrication and subsequent packaging. The metal substrate is mainly made of a metal material, where the metal material may be copper, iron, galvanized material, stainless steel, aluminum, any other conductive metal material or a conductive non-all-metal material. 
         [0256]    Step 2 may include pre-plating a surface of the metal substrate with a micro copper layer. 
         [0257]    As illustrated in  FIG. 34 , the surface of the metal substrate is pre-plated with the micro copper layer. Thickness of the micro copper layer ranges from 2 μm to 10 μm, where the micro copper layer may be thinner or thicker based on a functional requirement, to form a tight integration of the wiring layer and the metal substrate in subsequent wiring fabrication. The pre-plating may be implemented through chemical deposition or electrolytic plating. 
         [0258]    Step 3 may include applying with a photoresist film. 
         [0259]    As illustrated in  FIG. 35 , a top surface and a bottom surface of the metal substrate which have been pre-plated with the micro copper layer are respectively applied with the photoresist film which can be exposed and developed, to protect subsequent operations of plating metal layers. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0260]    Step 4 may include removing a part of the photoresist film on the top surface of the metal substrate. 
         [0261]    As illustrated in  FIG. 36 , the top surface of the metal substrate, which has been applied with the photoresist film in step 3, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later. 
         [0262]    Step 5 may include plating with a first metal wiring layer. 
         [0263]    As illustrated in  FIG. 37 , the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 4 is plated with the first metal wiring layer. The first metal wiring layer may be made of a material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold (plating thickness usually ranges from 5 μm to 20 μm and may be varied based on different properties), and of course any other conductive metal material may be feasible, without limitation to metal material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold. The plating may be implemented through chemical deposition or electrolytic plating. 
         [0264]    Step 6 may include applying with a photoresist film. 
         [0265]    As illustrated in  FIG. 38 , the top surface of the metal substrate in step 5 is applied with the photoresist film which can be exposed and developed. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0266]    Step 7 may include removing a part of the photoresist film on the top surface of the metal substrate. 
         [0267]    As illustrated in  FIG. 39 , the top surface of the metal substrate, which has been applied with the photoresist film in step 6, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later. 
         [0268]    Step 8 may include plating a second metal wiring layer. 
         [0269]    As illustrated in  FIG. 40 , the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 7 is plated with the second metal wiring layer, which serves as a conductive pillar to connect the first metal wiring layer to a third metal wiring layer. The metal wiring layer may be made of copper, nickel-gold, nickel-palladium-gold, silver, gold, or tin. The plating may be implemented through chemical deposition or electrolytic plating. 
         [0270]    Step 9 may include removing the photoresist film. 
         [0271]    As illustrated in  FIG. 41 , the photoresist film on the surface of the metal substrate is removed, for an operation of pasting a nonconductive film subsequently. The photoresist film may be removed through softening with a chemical potion and then flushing with high-pressure water. 
         [0272]    Step 10 may include applying with a nonconductive film. 
         [0273]    As illustrated in  FIG. 42 , the top surface of the metal substrate is applied with a layer of the non-conductive adhesive film, to insulate the first metal wiring layer from the third metal wiring layer. The applying may be pasted through a conventional rolling device, or be pasted in vacuum environment, to avoid residual air during the process of pasting. The nonconductive film is mainly a thermoset epoxy resin, and the epoxy resin may be a nonconductive film with or without a filler depending on a product property. The epoxy resin may be dyed depending on a product property. 
         [0274]    Step 11 may include grinding a surface of the nonconductive film. 
         [0275]    As illustrated in  FIG. 43 , the surface is grinded after the pasting of the nonconductive film, in order to expose the second metal wiring layer, maintain a flatness of the nonconductive film and the second metal wiring layer, and control thickness of the nonconductive film. 
         [0276]    Step 12 may include performing metallization pretreatment on the surface of the nonconductive film. 
         [0277]    As illustrated in  FIG. 44 , the metallization pretreatment is performed on the surface of the nonconductive film to attach a layer of metalized polymer material, which serves as a catalytic converter to plate a metal material subsequently. Attaching the metalized polymer material may include spraying, plasma oscillating, surface roughening, and drying. 
         [0278]    Step 13 may include applying with a photoresist film. 
         [0279]    As illustrated in  FIG. 45 , the top surface and the bottom surface of the metal substrate in step 12 are applied with the photoresist film which can be exposed and developed, to protect subsequent operation of plating with the third metal wiring layer. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0280]    Step 14 may include removing a part of the photoresist film on the top surface of the metal substrate. 
         [0281]    As illustrated in  FIG. 46 , the top surface of the metal substrate, which has been applied with the photoresist film in step 13, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be etched later. 
         [0282]    Step 15 may include etching. 
         [0283]    As illustrated in  FIG. 47 , the etching is performed in a region from which the part of the photoresist film has been removed in step 14, to completely erode metal regions except metal wirings required to be reserved. The etching may be performed with copper chloride, ferric chloride or any other chemical potion for etching. 
         [0284]    Step 16 may include removing the photoresist film on the top surface of the metal substrate. 
         [0285]    As illustrated in  FIG. 48 , the photoresist film on the top surface of the metal substrate is removed, to expose a pattern in a metal region required to be plated subsequently. 
         [0286]    Step 17 may include plating with a third metal wiring layer. 
         [0287]    As illustrated in  FIG. 49 , the top surface of the metal substrate in step 16 is plated with the third metal wiring layer. The third metal wiring layer may be made of copper, nickel-gold, nickel-palladium-gold, silver, gold or tin. The plating may be implemented through chemical deposition and electrolytic plating or through only chemical deposition to obtain a required thickness. 
         [0288]    Step 18 may include applying with a photoresist film. 
         [0289]    As illustrated in  FIG. 50 , the top surface of the metal substrate in step 17 is applied with the photoresist film which can be exposed and developed, for subsequent fabrication of metal wiring layers. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0290]    Step 19 may include removing a part of the photoresist film on the top surface of the metal substrate. 
         [0291]    As illustrated in  FIG. 51 , the top surface of the metal substrate, which has been applied with the photoresist film in step 18, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later. 
         [0292]    Step 20 may include plating with a fourth metal wiring layer. 
         [0293]    As illustrated in  FIG. 52 , the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 19 is plated with the fourth metal wiring layer, which serves as a conductive pillar to connect the third metal wiring layer to a fifth metal wiring layer. The fourth metal wiring layer may be made of copper, nickel-gold, nickel-palladium-gold, silver, gold or tin. The plating may be implemented through chemical deposition or electrolytic plating. 
         [0294]    Step 21 may include removing the photoresist film. 
         [0295]    As illustrated in  FIG. 53 , the photoresist film on the surface of the metal substrate is removed, for an operation of pasting a nonconductive film subsequently. The photoresist film may be removed through softening with a chemical potion and then flushing with high-pressure water. 
         [0296]    Step 22 may include applying with a nonconductive film. 
         [0297]    As illustrated in  FIG. 54 , the top surface of the metal substrate is applied with a layer of the non-conductive adhesive film, to insulate the third metal wiring layer from the fifth metal wiring layer. The nonconductive film may be pasted through a conventional rolling device, or be pasted in vacuum environment, to avoid residual air during the process of pasting. The nonconductive film is mainly a thermoset epoxy resin, and the epoxy resin may be a nonconductive film with or without a filler depending on a product property. The epoxy resin may be dyed depending on a product property. 
         [0298]    Step 23 may include grinding a surface of the nonconductive film. 
         [0299]    As illustrated in  FIG. 55 , the surface of the non-conductive adhesive film is ground after the applying the non-conductive adhesive film has been performed, in order to expose the fourth metal wiring layer, maintain a flatness of the nonconductive film and the fourth metal wiring layer, and control thickness of the nonconductive film. 
         [0300]    Step 24 may include performing metallization pretreatment on the surface of the nonconductive film. 
         [0301]    As illustrated in  FIG. 56 , the metallization pretreatment is performed on the surface of the nonconductive film to attach a layer of metalized polymer material, which serves as a catalytic converter to plate with a metal material subsequently. Attaching the metalized polymer material may include spraying, plasma oscillating, surface roughening, and drying. 
         [0302]    Step 25 may include applying with a photoresist film. 
         [0303]    As illustrated in  FIG. 57 , the top surface and the bottom surface of the metal substrate in step 24 are applied with the photoresist film which can be exposed and developed, to protect a subsequent operation of plating with the fifth metal wiring layer. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0304]    Step 26 may include removing a part of the photoresist film on the top surface of the metal substrate. 
         [0305]    As illustrated in  FIG. 58 , the top surface of the metal substrate, which has been applied with the photoresist film in step 25, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be etched later. 
         [0306]    Step 27 may include etching. 
         [0307]    As illustrated in  FIG. 59 , the etching is performed in a region from which the part of the photoresist film has been removed in step 26, to completely erode metal regions except metal wirings required to be reserved. The etching may be performed with copper chloride, ferric chloride or any other chemical potion for etching. 
         [0308]    Step 28 may include removing the photoresist film on the top surface of the metal substrate. 
         [0309]    As illustrated in  FIG. 60 , the photoresist film on the top surface of the metal substrate is removed, to expose a pattern in a metal region required to be plated subsequently. 
         [0310]    Step 29 may include plating with a fifth metal wiring layer. 
         [0311]    As illustrated in  FIG. 61 , the top surface of the metal substrate in step 28 is plated with the fifth metal wiring layer, so that a die pad and a lead are formed on the metal substrate. The fifth metal wiring layer may be made of copper, nickel-gold, nickel-palladium-gold, silver, gold or tin. The plating may be implemented through chemical deposition and electrolytic plating or through only entirely chemical deposition to obtain required thickness. 
         [0312]    Step 30 may include applying with a photoresist film. 
         [0313]    As illustrated in  FIG. 62 , the top surface of the metal substrate in step 29 is applied with the photoresist film which can be exposed and developed. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0314]    Step 31 may include removing a part of the photoresist film on the bottom surface of the metal substrate. 
         [0315]    As illustrated in  FIG. 63 , the bottom surface of the metal substrate, which has been applied with the photoresist film in step 30, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be etched later. 
         [0316]    Step 32 may include performing chemical etching. 
         [0317]    As illustrated in  FIG. 64 , the chemical etching is performed in a region on the bottom surface of the metal substrate in which exposing and developing have been performed in step 31, till the metal wiring layer is reached. A chemical potion for etching may be copper chloride, ferric chloride or any other chemical potion available for chemical etching. 
         [0318]    Step 33 may include applying with a photoresist film. 
         [0319]    As illustrated in  FIG. 65 , the bottom surface of the metal substrate on which the chemical etching has been performed in step 32 is applied with the photoresist film which can be exposed and developed. The photoresist film may be a dry photoresist film or a wet photoresist film. 
         [0320]    Step 34 may include removing a part of the photoresist film on the bottom surface of the metal substrate. 
         [0321]    As illustrated in  FIG. 66 , the bottom surface of the metal substrate, which has been applied with the photoresist film in step 33, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be plated later. 
         [0322]    Step 35 may include plating with a metal pillar. 
         [0323]    As illustrated in  FIG. 67 , the region of the bottom surface of the metal substrate from which the part of the photoresist film has been removed in step 34 is plated with the metal pillar. The metal pillar may be made of copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, nickel-palladium-gold and so on, and of course any other conductive metal material may be feasible, without limitation to a metal material such as copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, or nickel-palladium-gold. The plating may be implemented through chemical deposition or electrolytic plating 
         [0324]    Step 36 may include removing the photoresist film. 
         [0325]    As illustrated in  FIG. 68 , the photoresist film on the surface of the metal substrate is removed. The photoresist film may be removed through softening with a chemical potion and then flushing with high-pressure water. 
         [0326]    Step 37 may include coating with an adhesive material. 
         [0327]    As illustrated in  FIG. 69 , a bottom surface of the die pad formed in step 29 is coated with a conductive or non-conductive adhesive material, for integration of the die pad and a chip to be embedded later. 
         [0328]    Step 38 may include bonding dies. 
         [0329]    As illustrated in  FIG. 70 , a chip is bonded in the conductive or non-conductive adhesive material in step 37. 
         [0330]    Step 39 may include bonding a metal wire. 
         [0331]    As illustrated in  FIG. 71 , the metal wire is bonded between a top surface of the chip and a top surface of the lead. The metal wire may be made of gold, silver, copper, aluminum or alloy, and a shape of the metal wire may be a filament or a strip. 
         [0332]    Step 40 may include encapsulating. 
         [0333]    As illustrated in  FIG. 72 , encapsulating is performed on the bottom surface of the metal substrate in step 39 with a molding material. The encapsulating may be implemented through pouring glue with a mold, spraying with a spray device, pasting a film or brushing coating. The molding material may be an epoxy resin with or without a filler. 
         [0334]    Step 41 may include grinding a surface of the epoxy resin. 
         [0335]    As illustrated in  FIG. 73 , the surface of the epoxy resin is grinded after the molding with the epoxy resin has been performed in step 40, in order to expose the metal pillar out of the surface of the encapsulation, and control thickness of the epoxy resin. 
         [0336]    Step 42 may include plating with an anti-oxidizing metal layer or coating with an antioxidant OSP. 
         [0337]    As illustrated in  FIG. 74 , an exposed surface of the metal substrate is plated with the anti-oxidizing metal layer such as gold, nickel-gold, nickel-palladium-gold or tin, or is coated with an antioxidant (OSP) after the surface of the epoxy resin has been ground in step 41.