Abstract:
A bipolar dual-channel charge-coupled device having a first channel at the surface for storing a first bit stream of minority charge carrier packets and a second channel buried in the bulk for storing a second bit stream of majority charge carrier packets. The two bit streams are transferred along their respective surface and buried channels simultaneously and independently of each other, thereby substantially increasing the bit storage density of the chip.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to charge-coupled devices and more particularly to a bipolar dual-channel charge-coupled device for the simultaneous storage of two independent bit streams of charge packets of opposite conductivity types. 
     2. Description of the Prior Art 
     Charge-coupled device (CCD) structures for use in data processing system storage and communication signal processing are well known in the art. Referring to the patents and publications listed below under the heading &#34;References Cited By Applicant&#34;, Boyle and Smith [Refs. 1, 2, 3] originally disclosed the basic charge-coupled concept in the form of a surface channel device. Krambeck [Ref. 4] then disclosed the buried channel structure wherein the charge packets are within the bulk of the semiconductor rather than at the surface. Modifications of the buried channel arrangement were thereafter disclosed by Carnes and Kosonocky [Ref. 5], Erb [Ref. 6], Tasch [Ref. 7], Esser [Ref. 8] and Walden [Ref. 9]. 
     The charge-coupled structure is a serial device and therefore its access time is much slower than a randomly accessed semiconductor device. However, the charge-coupled device has a higher bit density and simpler structure and therefore lower cost than the random access memory device, and therefore may have utility in mass storage applications where cost rather than speed is of primary importance. However, in these low-cost applications the charge-coupled device must compete on a cost basis with presently available techologies such as disk and tape storage, as well as proposed new technologies such as the bubble magnetic memory. 
     Therefore, if the charge-coupled device is to succeed in this competition of technolgies, it is vitally important that the cost per bit of information be reduced by every feasible means. Since for a given chip size and technology the cost of manufacture is approximately constant, one of the most effective ways of reducing the cost is to increase the chip density; that is, the number of bits of information stored per chip unit area. 
     Krambeck [Ref. 4] discloses an arrangement having dual buried channels parallel to and spaced from each other and buried within the semiconductor bulk so as to store two independent bit streams. If feasible, this arrangement would approximately double the bit density. In effect, this proposal appears to be an attempt to fabricate CCD registers on the front as well as the back side of the wafer, and thus obtain two registers in the same area. However, it is believed that the inherent disadvantages of this arrangement render it impractical so that it has not been put into production. 
     The prior art noted above, as well as all other prior integrated circuit devices of which the present inventor is aware, are divided by a rigid dichotomy of bipolar and MOS technologies. That is, the bipolar devices involve the flow of charge carriers of both conductivity types, whereas the MOS (metal-oxide-semiconductor) devices are unipolar and involve the flow of charge carriers of only one conductivity type. More particularly, all charge-coupled devices of the prior art of which the present inventor is aware embody the unipolar MOS technology. 
     SUMMARY OF THE INVENTION 
     The charge-coupled device structure in accordance with the present invention achieves almost double the bit density of the prior art by the heterodoxy of departing from the heretofore rigid separation of bipolar and MOS technologies. That is, the present charge-coupled device is bipolar rather than unipolar in that the current flow comprises the transportation of electrons as well as holes. 
     More particularly, in the preferred embodiment disclosed for purposes of illustration, a single charge-coupled device stores and transfers two separate independent serial bit streams of information. A first bit stream comprising a series of charge carrier packets of one conductivity type (e.g. electrons) flows along a first channel at the surface of the semiconductor. A second bit stream comprising a series of charge carrier packets of the opposite conductivity type (e.g. holes) flows in a second channel buried within the bulk of the semiconductor and spaced from the first bit stream at the surface of the semiconductor. 
     In the present invention each gate electrode forms at alternate clock phases two potential wells each trapping charge packets of the opposite conductivity type. More particularly, at one clock phase a first potential well under the gate electrode traps electrons adjacent the surface of the semiconductor, and then at the next clock phase a second potential well under the same gate electrode traps holes in a buried channel spaced inwardly within the interior bulk of the semiconductor. As a result, each gate electrode alternately forms two different charge storage sites for electrons and holes respectively. 
     Although the resulting bit density is not quite doubled due to the necessity for additional structure and circuitry to accommodate the extra channel, the bit density achieved by the bipolar charge-coupled device of the present invention is substantially increased as compared with unipolar devices of the prior art, and therefore the cost per bit of information is substantially reduced. 
     IN THE DRAWINGS 
     FIG. 1 is a sectional plan view, partially broken away, of a charge-coupled device in accordance with the present invention and showing two adjacent serial shift registers or channels. 
     FIG. 2 is a longitudinal sectional view through the upper channel of FIG. 1 and taken substantially on the line 2--2 in the latter figure. 
     FIG. 3 is a transverse sectional view through both channels shown in FIG. 1 and is taken substantially on the line 3--3 of the latter figure. 
     FIG. 4 is a schematic sectional view of the vertical geometry and showing a majority carrier charge packet stored within the buried potential well beneath a first gate electrode and a minority carrier charge packet stored within the surface potential well beneath a second gate electrode, together with plots of the respective electrostatic potentials provided by the two gate electrodes. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 4, the basic mode of operation of the present invention will first be described. An N-type substrate 9 is shown with a P-type diffusion layer 10 formed adjacent its upper surface. Superimposed over the latter is an insulating layer 11 of silicon dioxide separating the upper surface of the substrate 9 from a series of gate electrodes as indicated schematically at G1 and G2. 
     The P-type layer 10 is reverse-biased in the conventional manner so as to form a depletion region constituting a buried charge channel along which packets of holes may be stored and transferred in the manner well-known in the art. One such buried charge packet is indicated in FIG. 4 by the dashed lines enclosing the three &#34;plus&#34; symbols designating holes. This buried charge packet is shown as stored within a potential well buried within the interior bulk of the P-type layer 10 and located beneath the first electrode G1. 
     Located beneath the second electrode G2 and adjacent to the surface of the P-type layer 10 there is shown an electronic charge packet within a potential well indicated by the dashed lines enclosing three &#34;minus&#34; symbols depicting electrons. 
     The electrostatic potential provided by the φ1 clock voltage applied to gate electrode G1 is shown by a plot beneath that electrode, and similarly, the potential provided by the φ2 clock voltage applied to the gate electrode G2 is shown as a plot beneath the latter electrode. The abscissa of each of these potential plots extends downwardly as shown by the arrow and is marked &#34;DEPTH&#34; so as to indicate the distance from the surface of the substrate. The ordinate of each of these potential plots is shown by the arrow to extend to the right and is the respective electrostatic potential provided by each of the gate electrodes G1 and G2. 
     By properly time-sequenced clock phase voltages applied to the gates such as G1 and G2, the buried charge potential wells along with the charge packets of holes stored therein may be shifted along the buried charge channel from site to site so as to form a continuous serial stream of data bits flowing from left to right as viewed in the drawings, while simultaneously the surface charge potential wells with the electron charge packets stored therein may be transferred serially from site to site along the surface of the P-type layer 10 so as to provide a second serial data bit stream flowing from right to left. This simultaneous flow of two separate and independent data bit streams enables the bit density of the charge-coupled device of the present invention to be almost doubled as compared with equivalent devices of the prior art. The structural details of a preferred embodiment realizing this novel mode of operation are described below. 
     Referring now to FIGS. 1 to 3 inclusive, there is shown a preferred embodiment of the invention for the purpose of illustrating one of the many forms which the invention may take in practice. These figures show a portion of an integrated circuit shift register configuration including two adjacent serial channels each constituting a serial shift register section. However, it will be understood that the invention may be readily embodied in parallel sections such as in a serial-parallel-serial memory configuration. 
     One of the serial shift register sections is shown in the upper portion of FIG. 1 and will be described in detail. The other shift serial register section is an identical mirror image of the first register section and is shown in the lower portion of FIG. 1. The corresponding elements of the two registers have applied thereto the same reference designations with those referring to the second register also having the suffix &#34;a&#34; appended. 
     Both shift registers are formed in the substrate 9 of N-type semiconductor material which has formed therein adjacent its upper surface the diffusion layer 10 of P-type semiconductor material. Extending over the upper surface of the substrate 9 and layer 10 is the usual dielectric insulating film 11 of silicon dioxide. Superimposed upon the latter and arranged in serial contiguous relation are the gate electrodes G1, G2, G3, G4, Gn. 
     At the right-hand end of each shift register is a buried charge output port serving as the drain for the hole charge packets. This port comprises a metal contact 12 having a portion 13 projecting downwardly through the insulating silicon dioxide film 11 and in conductive contact with a diffusion region 14 of P +  -type and embedded within the P-type layer 10. 
     At the opposite left-hand end of each shift register is a buried charge input port which serves as a source for the hole charge packets. This port comprises a metal contact 15 having a portion 16 projecting downwardly through the insulating silicon dioxide film 11 so as to conductively contact a P +  -type region 17 formed within the P-type layer 10. 
     At the right-hand end of each shift register there is a surface charge input port serving as the source for the electronic charge packets. This input port comprises a contact 18 having a portion 19 projecting downwardly through the silicon dioxide film 11 in a manner similar to the construction of contact 12 and portion 13. However, the portion 19 of contact 18 extends to a diffusion region 20 which differs from region 14 in that region 20 is N-type and is formed within the P-type layer 10 adjacent the P +  -type region 14 as shown in FIG. 3. 
     The left-hand end of each shift register is provided with a surface charge output port which serves as a drain for the electronic charge packets. This output port is similar in construction to the surface charge input port and comprises a contact 21 having a portion 22 projecting downwardly through the silicon dioxide film 11 so as to make conductive contact with an N-type region 23 diffused within the P-type layer 10 and adjacent to the P +  -type region 17. 
     Referring to FIG. 3, it will be seen that the silicon dioxide film 11 is provided with downwardly extending recessed portions 28, 29, 30 which serve two important functions. First, these portions prevent the electronic charge at the surface of P-type layer 10 from escaping to the N-type substrate 9 which is biased at the most positive voltage. Second, the recessed portions of the silicon dioxide film 11 serve to isolate the adjacent channels which in the preferred embodiment are disclosed as adjacent serial shift register sections. More specifically, the recessed silicon dioxide extension 29 is shown extending between the channel of the first serial shift register section and the adjacent channel of the second serial shift register section so as to isolate the two adjacent channels from each other. 
     In order to provide a buried channel within P-type layer 10 the latter must be depleted. This is achieved in the conventional manner by the application of a negative bias at 24 to contact 12 of the buried charge output port. 
     The operation of the structure shown in FIGS. 1 to 3 will be apparent from the above description of the invention with respect to FIG. 4 and therefore will be stated here only summarily. A first serial data bit stream enters a serial shift register section at the surface charge input port 18, 19, 20 and flows as a series of electronic charge packets from right to left, as viewed in the drawings, along the surface of P-type layer 10. These electronic charge packets are transferred from site to site as appropriate clock phase voltages are applied in timed sequence to gate electrodes G1, G2, G3, G4, Gn in the conventional manner well-known in the art. The serial stream of surface electronic charge packets is then output from the shift register section at the surface charge output port 21, 22, 23. 
     Simultaneously with the flow of the electronic charge packets along the surface of P-type layer 10, a second data bit serial stream flows in the opposite direction from left to right as viewed in the drawing. This second data bit serial stream is in the form of buried hole charge packets. The stream enters the serial shift register section at buried charged input port 15, 16, 17 and the resulting hole charge packets flow serially from site to site along the buried charge depletion region formed within the bulk interior of P-type layer 10. The serial stream of hole charge packets is then output from the serial shift register section at buried charge output port 12, 13, 14. 
     While the invention has been shown and particularly described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as delineated in the appended claims. 
     References Cited By Applicant 
     1. Boyle, W. S. and Smith, G. E., &#34;Charge Coupled Semiconductor Devices,&#34; Bell Sys. Tech. J. (April 1970) pp. 587-593. 
     2. Boyle, W. S. and Smith, G. E., U.S. Pat. No. 3,858,232; issued Dec. 31, 1974; filed Nov. 9, 1971. 
     3. Smith, G. E., U.S. Pat. No. 3,761,744; issued Sept. 25, 1973; filed Dec. 2, 1971. 
     4. Krambeck, R. H., U.S. Pat. No. 3,739,240; issued June 12, 1973; filed Apr. 6, 1971. 
     5. Carnes, J. E. and Kosonocky, W. F., &#34;Charge-Coupled Devices and Applications,&#34; Solid State Technology, (April 1974) pp. 67-77. 
     6. Erb, D. M., U.S. Pat. No. 3,913,077; issued Oct. 14, 1975; filed Apr. 17, 1974. 
     7. Tasch, A. F., Jr., U.S. Pat. No. 4,024,563; issued May 17, 1977; filed Sept. 2, 1975. 
     8. Esser, L. J. M., U.S. Pat. No. 3,965,481; issued June 22, 1976; filed Nov. 22, 1974. 
     9. Walden, R. H., Krambeck, Strain, R. J., McKenna, J., Schryer, N. L. and Smith, G. E., &#34;The Buried Channel Charge Coupled Device,&#34; Bell Sys. Tech. J. (September 1972) pp. 1635-1640.