Abstract:
A method of fabricating nonvolatile memory devices. The method includes forming a tunnel oxide layer, a stacked oxide layer, a polysilicon layer for a control gate, a buffer oxide layer and a buffer nitride layer in order on the entire surface of a semiconductor substrate, and patterning the substrate vertically to form a control gate and a first device isolation region. The method also includes implanting ions into the first device isolation region to form common source and drain regions, filling the gap of the first device isolation region to form a first device isolation structure, and removing the buffer nitride layer and the buffer oxide layer. The method further includes depositing polysilicon for a word line on the substrate, and patterning the substrate vertically to form the word line and a second device isolation region, forming sidewall spacers on the sidewalls of the control gate and the word line, and forming silicide on the word line.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method of fabricating nonvolatile memory devices and, more particularly, to a method of fabricating nonvolatile memory devices which embody a NOR flash cell with a stacked oxide layer with 4F 2  unit cell area. 
   2. Background of the Related Art 
   In general, there are two categories in semiconductor devices, namely, volatile memory and non-volatile memory. Volatile memory includes dynamic random access memory (hereinafter referred to as “DRAM”) and static DRAM (hereinafter referred to as “SDRAM”). One characteristic of volatile memory is that data is maintained only while electric power is applied. In other words, when power is turned off, the data in the volatile memory disappears. On the other hand, non-volatile memory, mainly ROM (Read Only Memory), can maintain data regardless of the application of electric power. 
   From the point of a view of a fabrication process, non-volatile memory is divided into a floating gate type and a metal insulator semiconductor (hereinafter referred to as “MIS”) type. The MIS type has doubly or triply deposited dielectric layers which comprise at least two kinds of dielectric materials. 
   The floating gate type stores data using potential wells, and is represented by an ETOX (Electrically erasable programmable read only memory Tunnel OXide) used in a flash EEPROM (Electrically Erasable Programmable Read Only Memory). 
   The MIS type performs program operation using traps at a bulk dielectric layer, an interface between dielectric layers, and an interface between a dielectric layer and a semiconductor. Metal/Silicon ONO Semiconductor (hereinafter referred to as “MONOS/SONOS”) structure mainly used for the flash EEPROM is a representative MIS structure. 
   Referring to  FIG. 1 , a device isolation structure  11  is formed on a semiconductor substrate  10 , on which a gate oxide layer  12  is formed. A first polysilicon layer  13  formed on the gate oxide layer  12  is then used as a floating gate. A dielectric layer  15  and a second polysilicon layer  16  are sequentially formed on the floating gate  13 , and the second polysilicon layer  16  is used as a control gate. A flash memory cell is then completed by depositing a metal layer  17  and a nitride layer  18  on the control gate  16 , and by patterning them in cell structure. 
   For the present fabricating processes of NOR flash memories, a self-aligned source (hereinafter referred to as “SAS”) process or a self-aligned shallow trench isolation (hereinafter referred to as “SA-STI”) process is chiefly adopted to minimize the unit cell area of the NOR flash memories. Although the SAS or the SA-STI processes or even both processes are applied, the unit cell area can not be reduced down to the minimum area(4F 2 ) of a NAND flash cell, because a bit contact must be formed. 
   SUMMARY OF THE INVENTION 
   Accordingly, the present invention is directed to a method of fabricating nonvolatile memory devices that substantially obviates one or more problems due to limitations and disadvantages of the related art. 
   The present invention advantageously provides a method of fabricating nonvolatile memory devices which embodies a flash memory with 4F 2  unit cell area without the need for adopting an SAS process or an SA-STI process and has simpler manufacturing processes than those for a NOR flash cell using floating gate devices according to the related art. 
   To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method of fabricating nonvolatile memories includes forming a tunnel oxide layer, a stacked oxide layer, a polysilicon layer for a control gate, a buffer oxide layer and a buffer nitride layer in order on the entire surface of a semiconductor substrate, patterning the substrate vertically to form a control gate and a first device isolation region, implanting ions into the first device isolation region to form common source and drain regions, filling the gap of the first device isolation region to form a first device isolation structure, removing the buffer nitride layer and the buffer oxide layer, depositing polysilicon for a word line on the substrate, and patterning the substrate vertically to form the word line and a second device isolation region, forming sidewall spacers on the sidewalls of the control gate and the word line, and forming silicide on the word line. 
   It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary, but are not restrictive of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings: 
       FIG. 1  is a cross-sectional view illustrating a flash memory cell fabricated in accordance with the related art; 
       FIG. 2  is a cross-sectional view illustrating a nonvolatile memory device in accordance with the present invention; 
       FIGS. 3   a  to  3   d  are a drawings comparing unit cell areas of a NOR flash memory according to the related art and a nonvolatile memory device according to the present invention; 
       FIGS. 4   a  and  4   b  are top views illustrating a cell array layout and a cell array circuit of a nonvolatile memory device according to the present invention respectively; 
       FIGS. 5   a  through  5   c  are cross-sectional views illustrating example processes of fabricating nonvolatile memory devices according to an embodiment of the present invention; 
       FIGS. 6   a  through  6   c  are cross-sectional views illustrating example processes of fabricating nonvolatile memory devices according to an embodiment of the present invention; 
       FIGS. 7   a  through  7   c  are cross-sectional views illustrating example processes of fabricating nonvolatile memory devices according to an embodiment of the present invention; 
       FIGS. 8   a  through  8   c  are cross-sectional views illustrating example processes of fabricating nonvolatile memory devices according to an embodiment of the present invention; and 
       FIGS. 9   a  through  9   c  are cross-sectional views illustrating example processes of fabricating nonvolatile memory devices according to an embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Reference will now be made in detail to exemplary embodiments of the present invention which are illustrated in the accompanying drawings. 
   Referring to  FIG. 2 , a nonvolatile memory device in accordance with the present invention is illustrated. A stacked oxide layer  104  and a polysilicon gate  105  are sequentially formed on a P-type substrate. A source  103  and a drain  102  are formed under respective sides of the gate  105 . The stacked oxide layer  104  comprises a tunnel oxide layer  106 , a storage oxide layer  107  and a block oxide layer  108 . The tunnel oxide layer  106  comprises a single layer or a multi-layer of a first tunnel oxide layer  106 - 1  and a second tunnel oxide layer  106 - 2 . Similarly, the block oxide layer  108  comprises a single layer or a multi-layer of a first block oxide layer  108 - 1  and a second block oxide layer  108 - 2 . 
   If the tunnel oxide layer has a single layer, it may be made of one of SiO 2 , Al 2 O 3  and Y 2 O 3 . If the tunnel oxide layer has a multi-layer, the first tunnel oxide layer may be made of one of Al 2 O 3 , Y 2 O 3 , HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3  and Lu 2 O 3 , and the second tunnel oxide layer may be made of one of SiO 2 , Al 2 O 3  and Y 2 O 3 . 
   The storage oxide layer may be made of one of HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3  and Lu 2 O 3 . 
   If the block oxide layer has a single layer, it may be made of one of SiO 2 , Al 2 O 3  and Y 2 O 3 . If the block oxide layer has a multi-layer, the first block oxide layer may be made of one of SiO 2 , Al 2 O 3  and Y 2 O 3 , and the second block oxide layer may be made of one of Al 2 O 3 , Y 2 O 3 , HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Tm 2 O 3 ,Yb 2 O 3  and Lu 2 O 3 . 
   For the program operation of the device, hot electron injection is carried out. When hot electrons are implanted into the potential well formed in the storage oxide layer, they jump the energy barrier of the tunnel oxide layer and a threshold voltage is increased. For the erase operation of the device, the electrons, which are stored in the potential well of the storage oxide layer, move to the silicon substrate by FN (Fowler-Nordheim) tunneling. Thus, the threshold voltage is decreased. For the read operation of the device, a middle voltage between the threshold voltage of the program state and that of the erase state is applied to the gate. A device state of either the program or the erase is determined by detecting current due to the applied voltage. 
   Referring to  FIG. 3   a , a NOR flash unit cell area with a bit contact is about 10.5F 2  when both an SAS and an SA-STI process are not applied. 
   Referring to  FIG. 3   b , a NOR flash unit cell area with a bit contact is about 9F 2  when only the SAS process is applied. Thus, the cell area can be reduced by about 15% in comparison to the cell area of the cell in  FIG. 3   a , due to the SAS process. 
   Referring to  FIG. 3   c , a NOR flash unit cell area with a bit contact is about 6F 2  when both the SAS and the SA-STI process are applied. Thus, the cell area can be reduced by about 43% and 33% in comparison to the cell area in  FIG. 3   a  and  FIG. 3   b , respectively. 
   Referring to  FIG. 3   d , a NOR flash unit cell with a stacked oxide layer, which doesn&#39;t have a bit contact, has a unit cell area of about 4F 2  in accordance with the present invention. The 4F 2  corresponds to a NAND flash unit cell area using the SA-STI process. Thus, the cell area can be reduced by about 62%, 55%, and 33% as compared to the cell area in  FIG. 3   a ,  FIG. 3   b , and  FIG. 3   c , respectively. 
   Referring to  FIG. 4   a  and  4   b , top views of a cell array layout and a cell array circuit of a nonvolatile memory according to the present invention are illustrated. A floating gate device  301  is shown in  FIG. 4   a . Cross-sectional views along the line A–A′ of  FIG. 4   b  are shown in  FIGS. 5   a ,  6   a ,  7   a ,  8   a , and  9   a . Cross-sectional views along the line B–B′ of  FIG. 4   b  are shown in  FIGS. 5   b ,  6   b ,  7   b ,  8   b , and  9   b . Cross-sectional views along the line C–C′ of  FIG. 4   b  are shown in  FIGS. 5   c ,  6   c ,  7   c ,  8   c , and  9   c.    
   Referring to  FIGS. 5   a ,  5   b , and  5   c , a deep N-type well  502  and a P-type well  503  are each defined in a semiconductor substrate  501  by using ion implantation processes. When the P-type well is defined, ion implantations for adjusting a threshold voltage and/or preventing a punch-through may be simultaneously performed. As a tunnel oxide layer, a storage oxide layer and a block oxide layer are sequentially formed, a stacked oxide layer  504  is completed. Thereafter, a polysilicon layer  505  for a control gate, a buffer oxide layer  506  and a buffer nitride layer  507  are sequentially deposited on the stacked oxide layer  504 . 
   If the tunnel oxide layer has a single layer, it may be made of one of SiO 2 , Al 2 O 3  and Y 2 O 3  with a thickness between about 30 Å and about 150 Å. If the tunnel oxide layer has a multi-layer, the first tunnel oxide layer may be made of one of Al 2 O 3 , Y 2 O 3 , HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3  with a thickness between about 30 Å and about 150 Å, and the second tunnel oxide layer may be made of one of SiO 2 , Al 2 O 3  and Y 2 O 3  with a thickness between about 5 Å and about 50 Å. 
   The storage oxide layer may be made of one of HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3  and Lu 2 O 3  with a thickness between about 40 Å and about 500 Å. 
   If the block oxide layer has a single layer, it may be made of one of SiO 2 , Al 2 O 3  and Y 2 O 3  with a thickness between about 40 Å and about 200 Å. If the block oxide layer has a multi-layer, the first block oxide layer may be made of one of SiO 2 , Al 2 O 3  and Y 2 O 3  with a thickness between about 5 Å and about 50 Å, and the second block oxide layer may be made of one of Al 2 O 3 , Y 2 O 3 , HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3  and Lu 2 O 3  with a thickness between about 40 Å and about 200 Å. 
   Here, as doped polysilicon may be used for the polysilicon layer  505 , or after an undoped polysilicon layer is deposited on the substrate, the undoped polysilicon layer may be doped through an ion implantation process. In an exemplary embodiment, the polysilicon layer  505  for a control gate is deposited with a thickness between about 500 Å and about 3000 Å. The buffer oxide layer is deposited with a thickness between about 100 Å and about 200 Å. The buffer nitride layer is deposited with a thickness between about 100 Å and about 2000 Å. 
   Referring to  FIGS. 6   a ,  6   b , and  6   c , the substrate is etched along the line B-B′ through a photolithography process, so that a device isolation structure  508  is formed. Predetermined ions or dopants are implanted to form common source and drain regions  509  in the region where the device isolation structure is formed. Before this implantation process for the common source and drain regions, an oxide growth process may be carried out for the sidewalls of the control gate and the device isolation structure. 
   Referring to  FIGS. 7   a ,  7   b , and  7   c , an APCVD (Atmospheric Pressure Chemical Vapor Deposition) or an HDP-CVD (High Density Plasma Chemical Vapor Deposition) process is applied to fill the gap between the device isolation structure and the control gate with an oxide layer  510 . An etchback process is performed to smooth the oxide layer  510 , until the oxide layer  510  is recessed to the middle of the buffer nitride layer  507 . A CMP (Chemical Mechanical Polishing) process may be carried out instead of the etchback process for the smoothing of the oxide layer  510 . 
   Referring to  FIGS. 8   a ,  8   b , and  8   c , after the buffer nitride layer and the buffer oxide layer on the control gate are removed by a wet etch, polysilicon  511  is deposited on the entire surface of the substrate. After the substrate is patterned along the word line (the line A-A′), the substrate is etched to form a word line. At the same time, as the control gate and the stacked oxide layer are patterned along the word line, a device isolation structure is formed to isolate each word line. In order to prevent a leakage current caused by a punch-through between the common source and drain regions, the device isolation structure may be etched more deeply than the junction depth of the common source and drain regions. The word line connects all the control gates, and may be utilized as a mask for any additional ion implantation in the later processes. As doped polysilicon may be used for the word line or after an undoped polysilicon layer is deposited on the substrate, the undoped polysilicon layer may be doped through an ion implantation process. In one embodiment, the polysilicon layer for the word line is deposited with a thickness between about 500 Å and about 3000 Å. After the word line is completed, an oxide layer may be deposited on the surface and the sidewalls of the exposed word line, the sidewalls of the control gate and the surface of the exposed device isolation structure. 
   Referring to  FIGS. 9   a ,  9   b , and  9   c,  sidewall spacers  512  are formed on the sidewalls of the control gate and the word line, and a silicide layer  513  is then selectively formed only on the word line by means of a silicide process. Because the insulation layer, which is deposited to form the sidewall spacers on the entire surface of the substrate, also fills the gap between the device isolation structure and the control gate, oxide may be deposited on the substrate as the insulation layer for the sidewall spacers, although nitride may be used. 
   Accordingly, the disclosed methods form a control gate and a device isolation structure at the same time, and use the control gate as a mask to form common source and drain regions in the device isolation region without any additional mask for forming source and drain regions. Thus, although neither an SAS process nor an SA-STI process is applied, a NOR flash cell area is effectively reduced. As this method doesn&#39;t need a bit contact which connects each drain of nonvolatile memory device with a stacked oxide layer to a bit line, a NOR flash cell area can be reduced by the area a NAND flash cell occupies. In addition, because an oxide layer is used as a material for storing electric charges instead of a floating gate, whose formation process is omitted, production cost is reduced. 
   Korean Patent Application Serial Number 10-2003-0101070, filed on Dec. 31, 2003, is hereby incorporated by reference in its entirety. 
   The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.