Abstract:
A conversion circuit for converting a current signal into a first output voltage signal, where the current signal flows through a sensing component, is provided. The conversion circuit includes: a first current eliminating circuit, configured to eliminate a first current in the current signal. The first current eliminating circuit includes: a current sample and hold circuit; and a current driving circuit, coupled between the sensing component and the current sample and hold circuit; a second current eliminating circuit, coupled to the sensing component and configured to eliminate a second current in the current signal; and an integrating circuit, coupled to the sensing component and configured to integrate a third current in the current signal, and output a first input voltage signal between a first integration output terminal and a second integration output terminal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation application of PCT application No. PCT/CN2016/090468 submitted on Jul. 19, 2016, which is based upon and claims priority to Chinese patent application No. 201511016745.8 on Dec. 29, 2015, both of which are incorporated herein for reference in their entireties. 
     
    
     TECHNICAL FIELD 
       [0002]    The present patent application relates to the field of electronic technologies, and in particular, relates to a conversion circuit and a detection circuit which are capable of eliminating a photoelectric current. 
       BACKGROUND 
       [0003]    With the development of science and technology, heartbeat detection function is employed in wearable electronic devices, which makes a light-emitting diode (LED) irradiate towards inner of a human body. The light penetrating through or reflected from the human body is sensed by using a photodiode or a phototransistor, and an optical signal (that is, a photoelectric current) sensed by the photodiode or phototransistor is converted into a voltage signal by using a heartbeat detection circuit. 
         [0004]    An existing heartbeat detection circuit converts the photoelectric current flowing through the photodiode or the phototransistor into a voltage signal by using a transimpedance amplifier (TIA, which is also referred to as a current-to-voltage converter). However, the heartbeat signal has a very small amplitude, and is easy to be impacted by background light from the environment. The transimpedance amplifier is incapable of eliminating a background photoelectric current, and thus accuracy of judgment of the heartbeat signal is affected. Further, the transimpedance amplifier has a high power consumption, and is easy to be impact by noise. Therefore, an improvement to the existing heartbeat detection circuit is desired. 
       SUMMARY 
       [0005]    A first technical problem to be solved by some embodiments of the present invention is to provide a conversion circuit to eliminate the impacts caused by a background photoelectric current. 
         [0006]    An embodiment of the present invention provides a conversion circuit for converting a current signal into a first output voltage signal where the current signal flows through a sensing component. The conversion circuit includes: 
         [0007]    a first current eliminating circuit, configured to eliminate a first current in the current signal, the first current eliminating circuit including: 
         [0008]    a current sample and hold circuit; and 
         [0009]    a current driving circuit, coupled between the sensing component and the current sample and hold circuit; 
         [0010]    a second current eliminating circuit, coupled to the sensing component and configured to eliminate a second current in the current signal; and 
         [0011]    an integrating circuit, coupled to the sensing component and configured to integrating for a third current in the current signal, the integrating circuit having a first integration output terminal and a second integration output terminal, wherein the first integration output terminal and the second integration output terminal are configured to output the first output voltage signal. 
         [0012]    A second technical problem to be solved by some embodiments of the present invention is to provide a detection circuit. The detection circuit includes: 
         [0013]    a photodiode, configured to receive a reflected light and generate a current signal according to the reflected light; and 
         [0014]    a conversion circuit as described above; 
         [0015]    a fully differential amplification circuit, including: 
         [0016]    a first input terminal, coupled to a first integration output terminal of the conversion circuit; 
         [0017]    a second input terminal, coupled to a second integration output terminal of the conversion circuit; 
         [0018]    a first output terminal; and 
         [0019]    a second output terminal. 
         [0020]    In the conversion circuit according to some embodiments of the present invention, a background photoelectric current and a base current in the current signal may be eliminated, and integration may be carried out for a heartbeat current in the current signal by using the integrating circuit, such that the impacts caused by the background photoelectric current and the base current to the heartbeat current are removed, and the detection efficiency is improved. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  is a schematic diagram of a detection circuit according to an embodiment of the present invention; 
           [0022]      FIG. 2  is a schematic diagram of a conversion circuit according to an embodiment of the present invention; 
           [0023]      FIG. 3  is a schematic diagram of one inverting amplifier in  FIG. 2  according to an embodiment of the present invention; 
           [0024]      FIG. 4  is a schematic diagram of another inverting amplifier in  FIG. 2  according to an embodiment of the present invention; 
           [0025]      FIG. 5  is a schematic diagram of a buffer in  FIG. 1  according to an embodiment of the present invention; 
           [0026]      FIG. 6  is a schematic diagram of a fully differential amplification circuit in  FIG. 1  according to an embodiment of the present invention; and 
           [0027]      FIG. 7  is a schematic diagram of an analog-to-digital converter in  FIG. 1  according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention is further described in detail below by reference to some exemplary embodiments and the accompanying drawings. It should be understood that the embodiments described here are only some exemplary ones for illustrating the present invention, and are not intended to limit the present invention. 
         [0029]    Referring to  FIG. 1 ,  FIG. 1  is a schematic diagram of a detection circuit  10  according to an embodiment of the present invention. The detection circuit  10  may be configured to detect a heartbeat of a human body, and the detection circuit  10  includes a driving circuit  102 , a light-emitting diode LED, a photodiode PD, a conversion circuit  100 , a fully differential amplification circuit  104  and an analog-to-digital converter ADC. 
         [0030]    The driving circuit  102  is coupled to the light-emitting diode LED, and configured to generate a base signal SIG to drive the light-emitting diode LED. The light-emitting diode LED generates an incident light λ 1  according to the base signal SIG. The incident light λ 1  irradiates a particular part of the human body, for example, a finger FG, such that the finger FG generates a reflected light λ 2 . The photodiode PD is configured to receive the reflected light λ 2  and generate a current signal I PD  according to the reflected light λ 2 . The conversion circuit  100  is coupled to the photodiode PD, and configured to convert the current signal I PD  into an output voltage V O1  and output an output voltage V O1  to the fully differential amplification circuit  104 . The fully differential amplification circuit  104  amplifies the output voltage V O1  to a voltage V O2  and outputs the voltage V O2  to the analog-to-digital converter ADC. The analog-to-digital converter ADC converts the analog voltage V O2  into a digital signal V O3 , and output the digital signal V O3  to a rear end operation circuit for subsequent operation and processing. 
         [0031]    In an embodiment, the detection circuit  10  may include switches S 1  and S 2  and buffers BF 1  and BF 2 . The switches S 1  and S 3  and the buffers BF 1  and BF 2  are coupled between the conversion circuit  100  and the fully differential amplification circuit  104 . For example, the switch S 1  and the buffer BF 1  are serially connected between a first output terminal of the conversion circuit  100  and a first input terminal of the fully differential amplification circuit  104 ; the switches  2  and the buffer BF 2  are serially connected to a second output terminal of the conversion circuit and a second input terminal of the fully differential amplification circuit  104 . 
         [0032]    It should be noted that the incident light λ 1  generated by the light-emitting diode LED is a modulated light, a heartbeat signal of a human body is modulated on the base signal SIG to generate the reflected light λ 2 , and the photodiode PD generates the current signal I PD  according to the reflected light λ 2 . Therefore, the current signal I PD  includes a background photoelectric current I BG , a base current I SIG  and a heartbeat current I HB  (that is, I PD =I BG +I SIG +I HB ). The background photoelectric current I BG  is a current from background light of the environment and caused by the photodiode PD. The base current I SIG  is a modulated base current relevant to the base signal SIG. The heartbeat current I HB  is a useful signal indicating the heartbeat of the human body. The heartbeat current I HB  is very small relative to the background photoelectric current I BG  and the base current I SM . In this case, the conversion circuit  100  may extract the heartbeat current I HB  from the current signal I PD , that is, differentiating the heartbeat current I HB  from the background photoelectric current I BG  and the base current I SIG . In other words, the conversion circuit  100  may eliminate the background photoelectric current I BG  and the base current I SIG  of the current signal I PD , and carry out integration for the heartbeat current I HB  of the current signal I PD . As such, the output voltage V O1  actually indicates the heartbeat of the human body. 
         [0033]    Specifically, referring to  FIG. 2 ,  FIG. 2  is a schematic diagram of a conversion circuit  100  according to an embodiment of the present invention. The conversion circuit  100  includes a current eliminating circuit  120  (corresponding to a first current eliminating circuit), a current eliminating circuit  122  (corresponding to a second current eliminating circuit), noise suppression capacitors CAN 1  (corresponding to a first noise suppression capacitor) and C AN2  (corresponding to a second noise suppression capacitor) and an integrating circuit  124 . The current eliminating circuit  120 , the current eliminating circuit  122  and the integrating circuit  124  are all coupled to a photodiode PD. The current eliminating circuit  120  is configured to eliminate a background photoelectric current I BG  (corresponding to a first current) of a current signal I PD . The current eliminating circuit  122  is configured to eliminate a base current I SIG  (corresponding to a second current) of the current signal I PD . The integrating circuit  124  is configured to carry out integration for a heartbeat current I HB  (corresponding to a third current) in the current signal I PD , generate an output voltage V O1  (corresponding to a first output voltage), and output the output voltage V O1  to a node between integration output terminals N 1  and N 2  of the integrating circuit  124 . The detection circuit  10  transfers the output voltage V O1  to the fully differential amplification circuit  104  via switches S 1 , S 2  and buffers BF 1 , BF 2 . In addition, the noise suppression capacitors CAN 1  and C AN2  are respectively coupled to the integration output terminals N 1  and N 2 , and configured to reduce a bandwidth of the entire conversion circuit  100 , and thus reduce noise energy between the integration output terminals N 1  and N 2  to achieve the effect of noise suppression. 
         [0034]    In detail, the integrating circuit  124  includes an inverting amplifier INV, integrating capacitors C int1 , C int2 , integrating switches S int1 , S int2 , switches S 3  and S 4 . The inverting amplifier INV has an input terminal and an output terminal. As illustrated in  FIG. 2 , the integrating capacitor C int1  is coupled between the input terminal of the inverting amplifier INV and the integration output terminal N 1 , and the integrating capacitor C int2  is coupled between the input terminal of the inverting amplifier INV and the integration output terminal N 2 . The switch S 3  is coupled between the input terminal of the inverting amplifier INV and the integration output terminal N 1 , and the switch S 4  is coupled between the input terminal of the inverting amplifier INV and the integration output terminal N 2 . The integrating switch S int1  is coupled between the integration output terminal N 1  and the output terminal of the inverting amplifier INV, and the integrating switch S int2  is coupled between the integration output terminal N 2  and the output terminal of the inverting amplifier INV. The integrating switches S int1  and S int2  are respectively controlled by signals Phi and Phi′; the signals Phi and Phi′ are frequency signals that are not overlapped with each other. In this case, during a first duration, the integrating switch S int1  is switched off and the integrating switch S int2  is switched on, the integrating circuit  124  carries out integration for the heartbeat current I HB  of the current signal I PD  by using the integrating capacitor C int1 , and the noise suppression capacitor CAN 1  suppresses the noise of the integrating capacitor C int1 . During a second duration, the integrating circuit S int2  is switched off and the integrating circuit S int1  is switched on, the integrating circuit  134  carries out integration for the heartbeat current I HB  of the current signal I PD  by using the integrating capacitor C int2 , and the noise suppression capacitor C AN2  suppresses the noise of the integrating capacitor C int2 . 
         [0035]    It should be noted that with increasing of the integration duration, the voltage difference (that is, the output voltage V O1 ) between the integration output terminals N 1  and N 2  may be increased. In addition, the noise suppression capacitors C AN1  and C AN2  are respectively coupled to the integration output terminals N 1  and N 2 , and the noise suppression capacitors C AN1  and C AN2  may not generate an excessive step response, whereas power consumption of the inverting amplifier INV can be reduced. Therefore, the detection circuit  10  achieves reduction of power consumption and noise by using the noise suppression capacitors C AN1  and C AN2  coupled to the integration output terminals N 1  and N 2 . 
         [0036]    In addition, the current eliminating circuit  122  may be practiced using an N-type field effect transistor, and the current eliminating circuit  122  may be controlled by the signal Phi′. In other words, the current eliminating circuit  122  may generate, during the second duration, a current to eliminate the base current I SIG  of the current signal I PD . 
         [0037]    The current eliminating circuit  120  includes a current sample and hold circuit  140  and a current driving circuit  142 . The current sample and hold circuit  140  includes a transistor M 7 , a sample and hold capacitor C SH , and a sample and hold switch S SH1 . The transistor M 7  may be a P-type field effect transistor, the sample and hold capacitor C SH  is coupled between a source and a gate of the transistor M 7 , and the sample and hold switch S SH1  is coupled between the gate and a drain of the transistor M 7 . The current driving circuit  142  is coupled between the current sample and hold circuit  140  and the photodiode PD, and the current driving circuit  142  includes transistors M 8 , M 9 , M 10  and a sample and hold switch S SH2 . The transistor M 9  may be a P-type field effect transistor, and the transistors M 8  and M 10  may be N-type field effect transistors. The transistor M 9  is coupled between the source of the transistor M 7  and a gate of the transistor M 8 , a drain of the transistor M 8  is coupled to the drain of the transistor M 7 , and a source of the transistor M 8  and a gate of the transistor M 10  are both coupled to the photodiode PD. One terminal of the sample and hold switch S SH2  is coupled to the gate of the transistor M 8  and a drain of the transistor M 9 , and the other terminal of the sample and hold switch S SH2  is coupled to a drain of the transistor M 10 . When the sample and hold switches S S H 1  and S SH2  are both switched off, the current eliminating circuit  120  rapidly generates a current to eliminate the background photoelectric current I BG  of the current signal I PD . In conclusion, the current eliminating circuit  120  is a rapid current sample and hold circuit, which, in addition to eliminating the background photoelectric current I BG  of the current signal I PD , further rapidly charges an equivalent capacitor inside the photodiode PD, to shorten the initialization time required by the conversion circuit  100 , and hence to reduce power consumption. 
         [0038]    Accordingly, the conversion circuit  100  eliminates the background photoelectric current I BG  of the current signal I PD  by using the current eliminating circuit  120 , eliminates the base current I SIG  of the current signal I PD  by using the current eliminating circuit  122 , and carries out integration for the heartbeat current I HB  of the current signal I PD  by using the integrating circuit  124 , to thereby improve the detection efficiency. Further, the conversion circuit  100  suppresses the noise by using the noise suppression capacitors C AN1  and C AN2  coupled to the integration output terminals N 1  and N 2 , thereby achieving reduction of power consumption and noise. 
         [0039]    It should be noted that the preceding embodiments are used to describe the concepts of some embodiments of the present invention. A person skilled in the art may make different modifications to the present invention without any limitation to the above given embodiments. For example, practice of the inverting amplifier INV in the integrating circuit  124  is not limited to a specific architecture. For example, referring to  FIG. 3 ,  FIG. 3  is a schematic diagram of an inverting amplifier  30 . The inverting amplifier  30  may be used to practice the inverting amplifier INV, and the inverting amplifier  30  includes transistors M 31  and M 32 ; the transistor M 31  is a P-type field effect transistor and the transistor M 32  is an N-type field effect transistor. A gate and a drain of the transistor M 31  are respectively coupled to a gate and a drain of the transistor M 32 , the gates of the transistor  31  and transistor M 32  form an input terminal of the inverting amplifier  30 , and the drains of the transistor M 31  and transistor M 32  form an output terminal of the inverting amplifier  30 . 
         [0040]    In another aspect, referring to  FIG. 4 ,  FIG. 4  is a schematic diagram of another inverting amplifier  40  according to an embodiment of the present invention. The inverting amplifier  40  may be used to practice the inverting amplifier INV, and the inverting amplifier  40  includes transistors M 41  to M 44  and a bias circuit  400 . The bias circuit  400  includes transistors M 45 , M 46  and resistors R 1 , R 2 . The transistors M 41 , M 43  and M 45  are all P-type field effect transistors, and the transistors M 42 , M 44  and M 46  are all N-type field effect transistors. 
         [0041]    As illustrated in  FIG. 4 , a gate of the transistor M 41  is coupled to a gate of the transistor M 42  to form an input terminal of the inverting amplifier  40 , and a drain of the transistor M 43  is coupled to a drain of the transistor M 44  to form an output terminal of the inverting amplifier  40 . A drain of the transistor M 41  is coupled to a source of the transistor M 43 , a drain of the transistor M 42  is coupled to a source of the transistor M 44 , a gate of the transistor M 43  is coupled to a drain of the transistor M 46 , a gate of the transistor M 44  is coupled to a drain of the transistor M 45 , a gate of the transistor M 45  is coupled to a gate of the transistor M 46 ; the resistor R 1  is coupled between the gate of the transistor M 45  and the drain of the transistor M 45 , and the resistor R 2  is coupled between the gate of the transistor M 46  and the drain of the transistor M 46 . 
         [0042]    It should be noted that the transistors M 41 , M 42  and the transistors M 43 , M 44  collaboratively form a cascade structure, which further improves a direct current gain of the inverting amplifier, and thus reduces a coupling degree of signals between the first duration and the second duration, and improves a linearity and signal-to-noise ratio of the integrating circuit  124 . In another aspect, the transistors M 45  and M 46  in the bias circuit  400  are respectively in a mirror relationship with the transistors M 41  and M 42  therein. When voltages of the transistors M 41  to M 44  change, voltage of the bias circuit  400  varies adaptively. In other words, the bias circuit  400  can increase a dynamic range of the inverting amplifier  40 . In addition, the resistors R 1  and R 2  may pull down a gate voltage of the transistor M 43  and pull up a gate voltage of the transistor M 44 , to prevent the transistors M 41  and M 42  from entering a linear region. 
         [0043]    In addition, practice of the buffers BF 1  and BF 2  is not limited to a specific architecture. For example, referring to  FIG. 5 ,  FIG. 5  is a schematic diagram of a buffer  50  according to an embodiment of the present invention. The buffer  50  may be used to practice any one of the buffers BF 1  and BF 2 . The buffer  50  includes switches  501 ,  503 ,  504 , a capacitor  502  and transistors  505 ,  506 . During a third duration, the switches  501  and  503  are switched off and the switch  504  is switched on, and the capacitor  502  samples the output voltage of the integrating circuit  124 ; during a fourth duration, the switch  504  is switched off and the switches  501  and  503  are switched on, and the buffer  50  holds the output voltage of the integrating circuit  124 , and outputs the output voltage to the fully differential amplification circuit  104 . 
         [0044]    In addition, practice of the fully differential amplification circuit  104  is not limited to a specific architecture. For example, referring to  FIG. 6 ,  FIG. 6  is a schematic diagram of a fully differential amplification circuit  60  according to an embodiment of the present invention. The fully differential amplification circuit  60  may be used to practice the fully differential amplification circuit  104 . The fully differential amplification circuit  60  includes a fully differential operational amplifier  610 , capacitors  603 ,  606 ,  607 ,  603 ′,  606 ′ and  607 ′, and switches  601 ,  602 ,  604 ,  605 ,  608 ,  609 ,  601 ′,  602 ′,  604 ′,  605 ′,  608 ′ and  609 ′. The switches  602 ,  605 ,  609 ,  602 ′,  605 ′ and  609 ′ are controlled by the signal Phi, and the switches  601 ,  604 ,  608 ,  601 ′,  604 ′ and  608 ′ are controlled by the signal Phi′. During the second duration, the switches  601 ,  604 ,  608 ,  601 ′,  604 ′ and  608 ′ are switched off and the switches  602 ,  605 ,  609 ,  602 ′,  605 ′ and  609 ′ are switched on, and the capacitors  603  and  603 ′ sample the output voltages of the buffers BF 1  and BF 2 ; and during the first duration, the switches  602 ,  605 ,  609 ,  602 ′,  605 ′ and  609 ′ are switched off and the switches  601 ,  604 ,  608 ,  601 ′,  604 ′ and  608 ′ are switched on, and the fully differential amplification circuit  104  transfers the charges stored in the capacitors  603  and  603 ′ to the capacitors  606  and  606 ′. By controlling the switches using the signals Phi and Phi′, the circuit architecture of the fully differential amplification circuit  60  can fully eliminate impacts caused by an offset voltage, a limited gain and flicker noise, and thus enhances the efficiency of the fully differential amplification circuit. 
         [0045]    In addition, practice of the analog-to-digital converter ADC is not limited to a specific architecture. For example, referring to  FIG. 7 ,  FIG. 7  is a schematic diagram of an analog-to-digital converter  70 . The analog-to-digital converter  70  may be used to practice the analog-to-digital converter ADC. The analog-to-digital converter  70  includes a first correlation array  701 , a second correlation array  702 , a capacitor array  703 , a comparator  704  and a logic module  705 . The first correlation array  701  and the second correlation array  702  both includes switches B 1  to BN, and the first correlation array  701  and the second correlation array  702  are both coupled to the capacitor array  703 . The capacitor array  703  includes capacitors C, 2C to2 N C. The logic module  705  controls conduction of the switches B 1  to BN of the first correlation array  701  and the second correlation array  702  according to an output comparison result of the comparator  704 , and converts an analog voltage V O2  into a digital voltage V O3 . The other operation details of the analog-to-digital converter  70  are well known by a person skilled in the art, which is thus not described herein any further. 
         [0046]    In conclusion, in the conversion circuit according to some embodiments of the present invention, a background photoelectric current and a base current in the current signal may be eliminated, and integration may be carried out for a heartbeat current in the current signal by using the integrating circuit, such that the impacts caused by the background photoelectric current and the base current to the heartbeat current are removed, and the detection efficiency is improved. Further, the conversion circuit further suppresses the noise by a noise suppression capacitor, thereby achieving reduction of power consumption and noise. 
         [0047]    Described above are merely some preferred embodiments of the present invention, but are not intended to limit the present invention. Any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the present invention should fall within the protection scope of the present invention.