Abstract:
A system and method for providing discrete analog voltage levels. The system and method employs a pseudo-random sequence generator for generating random-sequences of binary values, namely zeros and ones, based on a digital input. The pseudo-random sequence serves to modulate a current source whose output is integrated to develop a constant discrete analog voltage output. This method reduces spurious frequency interference on the circuit. The system and method can be employed in a node of a wireless ad-hoc communications network.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a system and method which principally employs pseudo-random binary sequence with known bias to generate discrete analog voltage levels. More particularly, the present invention relates to an apparatus and method for providing respective discrete analog voltage levels by modulating a current source with a pseudo-random binary sequence, the output of which being integrated over time to develop discrete and precise analog voltage levels. 
     2. Description of the Related Art 
     Many times, electronic systems require static analog voltage levels for tuning and control of the various sub-systems. Moreover, it is acceptable for the required analog voltage levels to be chosen from a discrete set of levels. A very popular choice among electronic system designers for developing discrete voltage levels is through the use of analog to digital converters (DAC) where a digital binary word defines the discrete analog voltage level that is developed at the output of the device. 
     Many different techniques are employed to develop discrete analog levels from digital binary words. Among these are successive approximation registers (SARs), flash, and delta-sigma techniques. However, as can be appreciated by one skilled in the art, most of these DAC implementations are extremely sophisticated and complex, making them expensive and large in comparison to the cost and size of the other components in the system. In certain applications, therefore, it is desirable to have a very low complexity DAC to maintain a reasonable system cost. Moreover, it is desirable to have a DAC which is very amenable to integration into low-cost digital integrated circuits (ICs). 
     Accordingly, a need exists for a simple and inexpensive system and method for providing discrete analog voltage levels from within a digital IC employing a minimal complexity technique. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a system and method capable of providing an analog voltage level from a set of discrete levels selected by a digital control word and employing a low complexity technique for this function. 
     Another object of the present invention is to reduce system costs through the use of existing digital logic component resource on a circuit board, namely, application specific ICs (ASIC) or programmable logic devices (PLD), to provide the discrete analog voltage levels via the addition of a minimal number of external analog components. 
     These and other objects are substantially achieved by a system and method for providing discrete analog voltage levels. The system and method employs a digitally programmable pseudo-random sequence generator for generating finite length, repetitive, sequences of binary values, namely zeros and ones, which have varying degrees of bias. The bias of a binary sequence is defined by the formula 
     
       
         Bias=(None−Nzero)/(2*(None+Nzero)) 
       
     
     Where “None” equals the total number of ones in the binary sequence and “Nzero” equals total number of zeros in the binary sequence. 
     From this formula, it is evident that a binary sequence with an equal number of zeros and ones has a bias of zero. Such a sequence is said to be perfectly balanced. If a sequence has more ones than zeros, then it will have a positive bias. In the same manner, sequences with more zeros than ones have a negative bias. Polarity keying a constant valued current source with the pseudo-random, repetitive sequence with know bias, and then integrating the output of the current source through a capacitor, transforms the bias of the binary sequence into an appropriately scaled precise discrete analog voltage. The current source modulation time interval, as well as the integrating capacitor value, shall be chosen so as to minimize undesirable fluctuations in the final output voltage. Specifically, the ratio of the constant current source value to the integrating capacitor in this example is at least one-twentieth the modulation time interval. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, advantages and novel features of the invention will be more readily appreciated from the following detailed description when read in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of two exemplary shift registers for generating pseudo-random binary sequences in accordance with an embodiment of the present invention; and 
     FIG. 2 is a block diagram of a circuit employing the PN sequence generator shown in FIG. 1 to produce discrete analog voltages in accordance with an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram illustrating a PN generator  110  employing two shift registers  102  and  104 , respectively, for generating pseudo-random binary sequences in accordance with an embodiment of the present invention. Feedback taps from the first register  102  are summed in a modulo- 2  adder  106 , and fed back to the shift register input creating a linear feedback shift register (LFSR). The second register  104  is connected in a similar manner to a modulo- 2  adder  108 . The output of both registers is connected to a common modulo- 2  adder  109 , whose output is the output of the PN generator  110 . 
     In a preferred embodiment of the present invention, each of the shift registers  102  and  104  has a length of five. In this example, shift registers  102  and  104  have feedback polynomials [u] o 45 =1+D 2 +D 4 +D 5  and [v] o 71 =1+D 3 +D 4 +D 5 , respectively. However, as can be appreciated by one skilled in the art, each shift register  102  and  104  can have any suitable length and/or other feedback polynomials in order to generate the desired number of PN sequences having the desired length. 
     The PN sequence generator  110  generates random-binary sequences. The reason pseudo-random (PN) sequences are used instead of any stream of zeros and ones is to minimize unwanted discrete spurious frequencies in a circuit. Indeed, pseudo-random sequences substantially guarantee that the signal generated at the output of the binary device is wideband, thus limiting discrete spurious frequency interference. 
     Table 1 below shows a set of 31-chip sequences generated by the PN generator  110  shown in FIG. 1 to be used to achieve an 18-level DAC. The values indicated in the columns “Init [u]” and “Init [v]” represent the hexadecimal seeds that are loaded into the shift registers  102  and  104  to produce the respective binary sequence shown in the “Sequence” column. For example, when the hexadecimal values “A” and “12”, corresponding to binary values “01010” and “10010” are loaded into shift registers  102  and  104 , respectively, the PN generator  110  generates the repetitive 31-chip sequence shown in the corresponding “Sequence” column. The number in the “Bias” column are the results of applying the formula 
     
       
         Bias=(None−Nzero)/(2*(None+Nzero)) 
       
     
     where “None” equals the total number of ones in the binary sequence and “Nzero” equals total number of zeros in the binary sequence. 
     It is noted that the initial shift-register seed for each sequence corresponding to a specific bias was determined by selecting, among all possible sequences, with the same bias, the sequence which has the lowest discrete spurious frequency components. 
     
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Examples of 31-Chip Sequences for an 18-Level DAC 
               
             
          
           
               
                 Bias 
                 Init [u] 
                 Init [v] 
                 Sequence 
               
               
                   
               
               
                 +17/62 
                 A 
                  5 
                 1111101111001001111110101111111 
               
               
                 +15/62 
                 1A 
                 11 
                 1101111101111001001111110101111 
               
               
                 +13/62 
                  7 
                 10 
                 1101101111111001111111110100100 
               
               
                 +11/62 
                 15 
                 1A 
                 1101101011001111000101111110111 
               
               
                  +9/62 
                  2 
                 15 
                 1110011111111101001001001110101 
               
               
                  +7/62 
                 11 
                 1A 
                 1111000101111110111001001010011 
               
               
                  +5/62 
                  7 
                 D 
                 0111100010111111011100100101001 
               
               
                  +3/62 
                  9 
                  1 
                 0010010111011101010011111000110 
               
               
                  +1/62 
                  7 
                  0 
                 1101001000010101110110001111100 
               
               
                  −1/62 
                 1A 
                 17 
                 1011011110101000100111000001100 
               
               
                  −3/62 
                 C 
                 18 
                 0010010001011101011000100011110 
               
               
                  −5/62 
                 1A 
                 1A 
                 0001110100000010001101101011001 
               
               
                  −7/62 
                  9 
                 1B 
                 0111000010001000000110101101100 
               
               
                  −9/62 
                 F 
                 1A 
                 1001001010011000011101000000100 
               
               
                 −11/62 
                 15 
                 D 
                 0010010100110000111010000001000 
               
               
                 −13/62 
                 11 
                 C 
                 1001000001000011011000000101000 
               
               
                 −15/62 
                 14 
                 1D 
                 1000001000011011000000101000000 
               
               
                 −17/62 
                 A 
                 12 
                 0000010000110110000001010000000 
               
               
                   
               
             
          
         
       
     
     FIG. 2 is a block diagram of a DAC circuit  100  implementing the PN generator  110  shown in FIG. 1 in accordance with an embodiment of the present invention. Specifically, the circuit  100  comprises a PN binary sequence generator  110  and an integrator circuit  120 . The PN generator  110  receives control logic digital inputs which select the shift register seeds as discussed above. Additionally, PN generator  110  receives a clock which determines the minimum time interval between transitions of the binary output sequence. This interval is referred to as the modulation time interval. The PN binary sequence modulates current source  121  in such a manner as to produce a positive current pulse of value +I when its modulation input equals a binary one and a negative current pulse of value −I when its modulation input equals a binary zero. The positive and negative current pulses from the current source  121  are integrated by capacitor  122  to develop analog voltage Vout at the output of the integrating circuit  120 . 
     Therefore, in accordance with an embodiment of the present invention, the DAC  100  can be achieved by combining a PN sequence generator  110  with an integrating circuit  120 , and by taking the analog output voltage developed across the integrating capacitor  122 . The circuit  100  is particularly useful for controlling the transmit power in terminals or nodes of wireless ad-hoc communications networks, such as those described in U.S. Pat. No. 5,943,322 to Mayor, and in U.S. patent application Ser. No. 09/897,790 entitled “Ad Hoc Peer-to-Peer Mobile Radio Access System Interfaced to the PSTN and Cellular Networks”, filed on Jun. 29, 2001, in U.S. patent application Ser. No. 09/815,157 entitled “Time Division Protocol for an Ad-Hoc, Peer-to-Peer Radio Network Having Coordinating Channel Access to Shared Parallel Data Channels with Separate Reservation Channel”, filed on Mar. 22, 2001, and in U.S. patent application Ser. No. 09/815,164 entitled “Prioritized-Routing for an Ad-Hoc, Peer-to-Peer, Mobile Radio Access System”, filed on Mar. 22, 2001, the entire content of said patent and each of said patent applications being incorporated herein by reference. 
     As can be appreciated by those skilled in the art, the characteristics of the analog voltage output of the integrating circuit  120  will depend on i.) the modulation time interval; ii.) the uniform quantization step in bias between PN sequences; iii.) the value of the current source  121 ; and iv.) the value of the integrating capacitor  122 . Provided that the ratio of the value of the current source  121  to the value of the integrating capacitor  122  times the uniform quantization step in bias is at least one-tenth (or at least approximately one-tenth) the value of the modulation time interval, the value of the analog voltage output of the integrating circuit  120  is determined by the bias of the selected PN sequence scaled by the value of the current source  121  plus the initial voltage across the integrating capacitor  122 . Typically, this initial voltage is chosen to be zero; hence, the output voltage of the integrating circuit  120  is a function of the PN sequence&#39;s bias and the value of the current source  122 . 
     As demonstrated above, the circuit  100 , after only a minimal number of clocking periods upon initialization, develops a steady analog voltage at the output of the integrating circuit whose value can be adjusted by digitally selecting a PN sequence with the respective bias. In the example described above, the PN generator  110  is used to generate 18 bias values. However, the sizes of the shift registers  102  and  104  can be increased or decreased to increase or decrease the number of bias values or to change the uniform bias quantization step. 
     Although only a few exemplary embodiments of the present invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the following claims.