Abstract:
A transceiver circuit includes driver circuits, receiver circuits, and suspend-mode buffers that are arranged to withstand an over-voltage conditions that would otherwise damage those circuits. An over-voltage sense circuit is arranged to detect the over-voltage condition on a data line in the transceiver. Cascode devices are placed in critical points of the various circuits, while voltages are coupled to other critical points such that none of the transistor devices that are coupled to the data lines are damaged by the over-voltage condition. Selector circuits are arranged to couple the highest detected voltages to various transistor wells to prevent forward biasing parasitic diodes in the transistors. Series switching circuits are arranged to break critical conduction paths during the over-voltage condition. The over-voltage protection scheme is suitable for use in integrated USB transceivers.

Description:
FIELD OF THE INVENTION 
   The present invention generally related to transceiver circuits that include over-voltage and short-circuit protection. More particularly, the present invention is related to USB transceiver circuits that detect an over-voltage condition that may be caused by a short-circuit condition, and controlling the maximum voltages that are exposed to critical transistors in the USB transceiver. 
   BACKGROUND OF THE INVENTION 
   Line drivers are used to transmit data over a communication line to a receiver. The driver operates as a source that provides signals to the communication line, where the signals may be either differential or single-supply referenced. Either a current or voltage output signals may be provided, depending on the overall system requirements. 
   In one example system, the output signal from the line driver is provided as one or more single-supply referenced voltages. Data is transmitted over the communication line by pulling the voltage between one supply level (e.g., VCC) and another (e.g., ground). The receiver detects the voltage levels on the communication line to receive the data transmission. 
   In another example system, the output signal from the line driver is provided as a differential voltage that is provided to the communication line. Data is transmitted over the communication line by changing the polarity of the differential voltage from positive to negative. The receiver detects the polarity of the voltage on the communication line to receive the data transmission. 
   In still another example system, the output signal is a differential current that is driven into a terminating load at the opposite end of the communication line. Data is transmitted over the communication line by changing the polarity of the current from positive to negative. The current that is transmitted over the communication line is converted into a voltage by the terminating load. The receiver detects the changes in the polarity across the terminating load to receive the data transmission. 
   Many modern computing devices utilize transceiver interface circuitry. Two commonly used interfaces are the universal serial bus interface (USB) and the IEEE 1394 serial interface (also referred to as “Firewire”). Digital cameras, personal computers (PCs), personal data assistants (PDAs) are but a few example devices that often include a universal serial bus interface (USB). Digital video cameras, external hard disk drives, and PCs are but a few example devices that often include an IEEE 1394 interface. 
   Each transceiver circuit permits communication between two different devices over a serial communication link. The serial communication link is not a fixed bus, but instead is a configured by a user on demand. For example, a digital camera is a portable device that is not connected to a PC via a USB interface until data transfer is required. A USB cable serves as the communication bus that connects the digital camera to the PC such that the data can be transferred. Most LVDS devices can be “hot plugged”, meaning that the device need not be powered down before connecting the various devices together. 
   SUMMARY OF THE INVENTION 
   A transceiver circuit includes driver circuits, receiver circuits, and suspend-mode buffers that are arranged to withstand an over-voltage conditions that would otherwise damage those circuits. An over-voltage sense circuit is arranged to detect the over-voltage condition on a data line in the transceiver. Cascode devices are placed in critical points of the various circuits, while voltages are coupled to other critical points such that none of the transistor devices that are coupled to the data lines are damaged by the over-voltage condition. Selector circuits are arranged to couple the highest detected voltages to various transistor wells to prevent forward biasing parasitic diodes in the transistors. Series switching circuits are arranged to break critical conduction paths during the over-voltage condition. The over-voltage protection scheme is suitable for use in integrated USB transceivers. 
   A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of an exemplary USB interface; 
       FIG. 2  is a schematic diagram of an exemplary driver circuit in a USB interface; 
       FIG. 3  is a schematic diagram of an exemplary single-ended receiver circuit in a USB interface; 
       FIG. 4  is a schematic diagram of an exemplary differential receiver circuit in a USB interface; 
       FIG. 5  is a schematic diagram of an exemplary suspend-mode buffer circuit in a USB interface; and 
       FIG. 6  is a schematic diagram of an exemplary over-voltage sense circuit, arranged in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediary devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” means at least one current signal, voltage signal or data signal. The meaning of “a”, “an”, and “the” include plural references. The meaning of “in” includes “in” and “on”. 
   Interface System Overview 
     FIG. 1  is a schematic diagram of an exemplary interface system ( 100 ) that is arranged in accordance with the present invention. The interface system ( 100 ) includes two driver circuits ( 200 ), two single-ended receiver circuits ( 300 ), a differential receiver circuit ( 400 ), two suspend-mode buffers ( 500 ), and two over-voltage sense circuits ( 600 ). 
   A pair of data lines (D+, D−) operates as a bi-directional serial communication bus that can be used for transmitting or receiving data. The USB interface system ( 100 ) is transmits a signal to the data lines (D+, D−) in response to signals received from a pair of input lines (INP, INN). The USB interface system ( 100 ) provides data to a differential receiver line (RCV), a positive input line (VPIN), and a negative input line (VMIN) in response to data that is received from the data lines (D+, D−). 
   The first driver circuit ( 200 ) is coupled between input line INP and data line D+, while the second driver circuit ( 200 ) is coupled between input line INN and data line D−. The driver circuits are enabled to transmit signals to the data lines (D+, D−) when enabled by enable lines en — pb and en — mb, respectively. The first and second driver circuits ( 200 ) are configured to provide reference signals Vpnwell and Vnnwell, which are used by the differential receiver circuit ( 400 ). 
   The first single-ended receiver circuit ( 300 ) is coupled between data line D+ and receiver line VPIN, while the second single-ended receiver circuit ( 300 ) is coupled between data line D− and receiver line VMIN. The single-ended receiver circuits utilize another reference signal (VREF). 
   The differential receiver circuit ( 400 ) is configured to provide data to the differential receiver line (RCV) in response to the data lines (D+, D−) when enabled by enable lines en — pb and en — mb. The differential receiver circuit ( 400 ) includes over-voltage protection circuitry that is controlled by enable lines en — pb and en — mb, and is responsive to reference signals Vpnwell and Vnnwell. The differential receiver circuit ( 400 ) and the driver circuits ( 200 ) are not active at the same time. 
   The first suspend-mode buffer ( 500 ) is coupled between data line D+ and receiver line VPIN, while the second suspend-mode buffer ( 500 ) is coupled between data line D- and receiver line VMIN. The first suspend-mode buffer ( 500 ) includes over-voltage protection circuitry that is controlled by enable lines en — p and en — pb, while the second suspend-mode buffer ( 500 ) includes over-voltage protection circuitry that is controlled by enable lines en — m and en — mb. 
   The first over-voltage sense circuit ( 600 ) is coupled to data line D+, while the second over-voltage sense circuit ( 600 ) is coupled to data line D−. The first over-voltage sense circuit ( 600 ) is configured to provide the en — p and en — pb enable lines, while the second over-voltage sense circuit ( 600 ) is configured to provide the en — m and en — mb enable lines. 
   For each of the operating modes described below, the over-voltage sense circuits ( 600 ) must remain active to ensure that all of the electronic circuits are protected from any over-voltage condition on the data lines. 
   In one operating mode (e.g., normal operation), the interface system ( 100 ) receives a differential signal that is applied to INP and INN. The first and second driver circuits ( 200 ) receive the differential signal (INP, INN) and provide a differential current drive to the D+ and D− data lines. The single-ended receiver circuits ( 300 ) provide signals VPIN and VMIN in response to signals that are sensed from the D+ and D− lines. The differential receiver circuit ( 400 ) is configured to provide data to the differential receiver line (RCV) in response to signals that are sensed from the data lines (D+, D−). The suspend mode buffers ( 500 ) are deactivated in the normal operating mode (or placed in tri-state) since the single-ended receiver circuits ( 300 ) are fully activated. The differential receiver circuit ( 400 ) and the driver circuits ( 200 ) are not active at the same time. 
   In another operating mode (e.g., suspended operation), the interface system ( 100 ) is arranged to operate in a low-power condition such that all of the circuit blocks except for the suspend mode buffers ( 500 ) and the over-voltage sense circuits ( 600 ) are deactivated. The suspend-mode buffers ( 500 ) are arranged to sense the signals on the data lines (D+, D−) and provide signals to VPIN and VMIN when signals are detected on the data lines. The other circuit blocks are activated into the normal operating mode after signals are detected on the data lines by the suspend mode buffers ( 500 ). 
   In another operating mode (e.g., over-voltage operation), the over-voltage sense circuits ( 600 ) detect an over-voltage condition on either one of the D+ and D− data lines. The first driver circuit ( 200 ) is disabled when an over-voltage condition is detected on the D+line, while the second driver circuit ( 200 ) is disabled when an over-voltage condition is detected on the D−line. Similarly, the differential receiver ( 400 ) is disabled when an over-voltage condition is detected on the data lines (D+. D−) . The suspend-mode buffers ( 500 ) are also disabled when the over-voltage condition is detected on the data lines (D+, D−) . The receiver circuits are configured to maintain valid DC operating conditions during over-voltage operation such that the receivers do not need to be power cycled or reset before returning to normal operation. The outputs of the receivers are arranged to maintain valid output signals during over-voltage operation. 
   Each electronic circuit that is illustrated in  FIGS. 1–6  is arranged to operate over various transceiver specifications. For example, a USB transceiver must operate with data lines (D+, D−) in the 0–3.6 V nominal operating range, remain undamaged in the 4.4V –5.25V range when shorted to an over-voltage condition, at −1V for worst case AC undershoot, and at 4.6V for worst case AC overshoot. 
   In addition to the transceiver specifications, each of the electronic circuits must also operate within prescribed operating limits. The operating limits for the electronic circuits are specific to the semiconductor process that is employed to manufacture the electronic circuits. In one example semiconductor process, the maximum drain-source voltage (Vds) is 3.6V, the maximum gate-drain voltage (Vgd) is 4.2V, the maximum gate-source voltage is 4.2V, the maximum gate-bulk voltage is 4.2V, maximum voltage across a gated diode is 5.5V, and the maximum voltage across a non-gated junction (Vj) is 6.5V. Each parameter described-above corresponds to an operating limit that must be maintained to protect the electronic circuits from damage. Other operating limits, other than those described above, are considered within the scope of the present invention. 
   Exemplary Driver Circuit 
     FIG. 2  is a schematic diagram of an exemplary driver circuit ( 200 ) that is arranged in accordance with the present invention. The driver circuit ( 200 ) corresponds to a means for driving that is arranged to drive an output signal on a data line in response to an input signal when enabled. Driver circuit  200  includes three logic gates (G 201 –G 203 ), and thirteen transistors (M 201 –M 213 ). 
   Logic gate G 201  is coupled between IN and node N 201 . Logic gate G 202  is coupled between IN and node N 208 . Logic gate G 203  includes a first input that is coupled to node N 208 , a second input that is coupled to ENB, and an output that is coupled to node N 209 . Transistor M 201  includes a drain that is coupled to node N 202 , a gate that is coupled to EN, and a source that is coupled to node N 201 . Transistor M 202  includes a drain that is coupled to node N 202 , a gate that is coupled to ENB, and a source that is coupled to node N 201 . Transistor M 203  includes a drain that is coupled to node N 202 , a gate that is coupled to EN, and a source that is coupled to VDD. Transistor M 204  includes a drain that is coupled to node N 203 , a gate that is coupled to ENB, a source that is coupled to VDD, and a body that is coupled to VNWELL. Transistor M 205  includes a drain that is coupled to node N 204 , a gate that is coupled to node N 202 , a source that is coupled to node N 203 , and a body that is coupled to VNWELL. Transistor M 206  includes a drain that is coupled to node N 204 , a gate that is coupled to node N 202 , and a source that is coupled to node N 205 . Transistor M 207  includes a drain that is coupled to node N 205 , a gate that is coupled to EN, and a source that is coupled to GND. Transistor M 208  includes a drain that is coupled to node N 204 , a gate that is coupled to VDD, and a source and body that are coupled to VNWELL. Transistor M 209  includes a drain that is coupled to OUT, a gate that is coupled to node N 204 , a body that is coupled to VNWELL, and a source that is coupled to VDD. Transistor M 210  includes a drain that is coupled to OUT, a gate that is coupled to VDD, and a source that is coupled to node N 210 . Transistor M 211  includes a drain that is coupled to node N 210 , a gate that is coupled to node N 209 , and a source that is coupled to GND. Transistor M 212  includes a drain and body that are coupled to VNWELL, a gate that is coupled to OUT, and a source that is coupled to VDD. Transistor M 213  includes a drain and body that are coupled to VNWELL, a gate that is coupled to VDD, and a source that is coupled to OUT. 
   Driver circuit  200  receives an input signal from IN, and provides output signals OUT and VNWELL when enabled. Driver circuit  200  is enabled when signal EN corresponds to logic  1 . Signal ENB corresponds to an inverse of signal EN. Transistors M 201 , M 203  and M 207  are responsive to the EN signal, while transistors M 202 , M 204 , and logic gate G 203  are responsive to the ENB signal. The operating modes for the driver circuit ( 200 ) are described below. 
   Driver Circuit: Normal Operating Mode 
   During the normal operating mode, the driver circuit ( 200 ) is enabled by signals EN and ENB. For the exemplary circuit illustrated in  FIG. 2 , signal EN corresponds to logic  1 , and signal ENB corresponds to logic  0  when the normal operating mode is selected. Transistors M 203 , M 208  and M 213  are deactivated and have no effect in this operating mode. 
   Logic gate  201  provides an inverse logic signal at node N 201  in response to the input signal (IN). Transistors M 201  and M 202  are arranged to operate as a transmission gate that transfers the signal from node N 201  to node N 202 . Thus, the signal at node N 202  corresponds to an inverse of the input signal (IN). Transistors M 204  and M 207  are activated such that transistors M 205  and M 206  operate as an inverting logic circuit that provide a signal at node N 204  in response to the signal at node N 202 . Thus, the signal at node N 204  corresponds to the same logic level as the input signal (IN). The signal at node N 209  corresponds to the same logic level as the input signal (IN) such that transistors M 209 –M 211  operate as another inverting logic circuit that provides a signal to OUT in response to the input signal (IN) via nodes N 204  and N 209 . Transistors M 212  and M 213  are arranged to operate as a selector circuit that selects the greater of VDD and OUT and provides the resulting potential to VNWELL. When signal OUT is lower than VDD, transistor M 212  is conducting more strongly than M 213  such that VDD is coupled to VNWELL. When signal OUT is higher than VDD, transistor M 213  is conducting more strongly than transistor M 212  such that OUT is coupled to VNWELL. When signal OUT and VDD are equal, both transistors M 212  and M 213  are conducting equally well such that OUT and VDD are both coupled to VNWELL. 
   Driver Circuit: Over-Voltage Operating Mode 
   During the over-voltage operating mode, the driver circuit ( 200 ) is disabled by signals EN and ENB, and the output signal (OUT) is above the power supply level (VDD). The output signal (OUT) may exceed the power supply level (VDD) as a result of a short-circuit condition between the respective data line (D+ and/or D−) and an external power supply level. For the exemplary circuit illustrated in  FIG. 2 , signal EN corresponds to logic  0 , and signal ENB corresponds to logic  1  when the over-voltage operating mode is selected. Transistors M 201 , M 202 , M 204 , M 207 , M 211 , and M 212  are deactivated in this operating mode. 
   The transmission gate (e.g., transistors M 201 , M 202 ) is disabled such that node N 202  is isolated from node N 201 . Transistor M 203  is arranged to operate as a pull-up circuit that couples VDD to node N 202 . Transistors M 204  and M 207  are deactivated such that the inverting logic circuit (M 205 , M 206 ) is disabled. Transistor M 208  is forward biased such that VNWELL is coupled to node N 204 . Transistor M 210  is arranged to provide a potential at node N 210  that corresponds to VDD−VTH. Transistor M 213  is forward biased such that OUT is coupled to VNWELL. 
   The over-voltage condition occurs on the OUT signal line such that all devices that are coupled to OUT must be protected from the over-voltage condition. For example, each transistor has a maximum drain-source voltage (VDS), a maximum gate-drain voltage (VGD), and a maximum gate-source voltage (VGS). Typical transistor devices have identical maximum values for VGD and VGS. 
   Transistors M 209 –M 213  are arranged to operate within the processing limits such that the driver circuit ( 200 ) withstands the over-voltage condition without damage. VGD for transistor M 209  corresponds to V(OUT)−V(N 204 ). Since VNWELL is coupled to OUT and node N 204 , VGD corresponds to zero for transistor M 209 . VDS for transistor M 209  corresponds to V(OUT)−VDD. The maximum VDS and the maximum VGD of transistor M 211  corresponds to VDD−VTH, where VTH corresponds to the threshold voltage of transistor M 210 . Transistor M 210  has a maximum VDS that corresponds to V(OUT)−(VDD−VTH)), which should be well within process limitations. Also, V(OUT) has a maximum value that is specified by the USB transceiver (e.g. V(OUT)&lt;5.25V for USB 2.0). 
   In one example, VGDMAX=4.2V, VDSMAX=3.6V, VDD=3.6V, V(OUT)&lt;5.25V, and VTH=1V. For this example,
         VGD(M 209 )=0&lt;4.2V,   VDS(M 209 )=V(OUT)−3.6V&lt;3.6V,   VDG(M 210 )=V(OUT)−3.6V&lt;4.2V,   VDS(M 210 )=V(OUT)−2.6V&lt;3.6V,   VDG(M 211 )=2.6V&lt;4.2V, and VDS(M 211 )=2.6V.
 
Exemplary Single-Ended Receiver Circuit
       

     FIG. 3  is a schematic diagram of an exemplary single-ended receiver circuit ( 300 ) that is arranged in accordance with the present invention. The single-ended receiver circuit ( 300 ) corresponds to a means for receiving that is arranged to provide a receiver signal in response to a sense signal from a data line. Single-ended receiver circuit  300  includes a current source (I 301 ), and five transistors (M 301 –M 305 ). 
   Transistor M 301  includes a drain that is coupled to node N 301 , a gate that is coupled to VREF, a source that is coupled to node N 303 , and a body that is coupled to VDD. Transistor M 302  includes a drain that is coupled to node N 302 , a gate that is coupled to node N 304 , a source that is coupled to node N 303 , and a body that is coupled to VDD. Transistor M 303  includes a drain and gate that are coupled to OUT, and a source that is coupled to GND. Transistor M 304  includes a drain and gate that are coupled to node N 302 , and a source that is coupled to GND. Transistor M 305  includes a drain that is coupled to IN, a gate that is coupled to VDD, and a source that is coupled to node N 304 . Current source  1301  is coupled between VDD and node N 303 . 
   Single-Ended Receiver Circuit: Normal Operating Mode 
   Transistor M 305  is biased such that the single-ended receiver ( 300 ) is arranged to provide an output signal at the output terminal (OUT) in response to an input signal at the input terminal (IN). Transistor M 305  is configured to operate as a switching circuit that couples the input signal to node N 304 . Transistors M 301  and M 302  are configured to operate as a differential pair that compares the input signal (via transistor M 305 ) to a reference signal that is provided to VREF. Transistor M 303  and M 304  are configured to operate as diode-type devices that are selectively forward biased by current IT 31  in response to the comparison of the reference signal to the input signal. Thus, the output signal either corresponds to a maximum value of slightly above VTH (the threshold voltage of transistor M 303 ), and a minimum value that is approximately zero. 
   An amplifier stage (not shown) may be employed to detect the output signal from the output terminal (OUT) and generate high and low logic levels. For example, a mirror transistor that is series coupled to a pull-up circuit may be configured to receive the output signal and provide logic levels. Any appropriate circuit arrangement may be employed to convert the output signal levels from the single-ended receiver circuits to appropriate logic levels. 
   Single-Ended Receiver Circuit: Over-Voltage Operating Mode 
   Transistor M 305  is configured to protect the gate of transistor M 302  from an over-voltage condition in the input signal. Transistor M 305  is configured to pass the input signal to the gate of transistor M 302  until the input signal level reaches the threshold voltage associated with transistor M 305 . The voltage associated with node N 304  is clamped to VDD−VTH (the threshold voltage of transistor M 305 ) when the input signal exceeds VDD. 
   Exemplary Differential Receiver Circuit 
     FIG. 4  is a schematic diagram of an exemplary differential receiver circuit ( 400 ) that is arranged in accordance with the present invention. The differential receiver circuit ( 400 ) corresponds to a means for differentially receiving that is arranged to provide a receiver signal in response to a differentially senses signal from the data lines. Differential receiver circuit  400  includes two current sources (I 401 –I 402 ), two logic gates (G 401 –G 402 ), and eighteen transistors (M 401 –M 418 ). 
   Transistor M 401  includes a drain that is coupled to INP, a gate that is coupled to ENB — P, a source that is coupled to INP 4 , and a body that is coupled to VPNWELL. Transistor M 402  includes a drain that is coupled to INP, a gate that is coupled to VDD, and a source that is coupled to INP 4 . Transistor M 403  includes a drain that is coupled to INM, a gate that is coupled to VDD, and a source that is coupled to INM 4 . Transistor M 404  includes a drain that is coupled to INM, a gate that is coupled to ENB — N, a source that is coupled to INM 4 , and a body that is coupled to VNNWELL. Transistor M 405  includes a drain that is coupled to INP 4 , a gate that is coupled to node N 401 , a source that is coupled to VDD, and a body that is coupled to VPNWELL. Transistor M 406  includes a drain that is coupled to INM 4 , a gate that is coupled to node N 402 , a source that is coupled to VDD, and a body that is coupled to VNNWELL. Transistor M 407  includes a drain that is coupled to node N 403 , a gate that is coupled to node N 404 , and a source that is coupled to VDD. Transistor M 408  includes a drain and gate that are coupled to node N 404 , and a source that is coupled to VDD. Transistor M 409  includes a drain that is coupled to node N 404 , a gate that is coupled to INM 4 , and a source that is coupled to node N 405 . Transistor M 410  includes a drain that is coupled to node N 406 , a gate that is coupled to INP 4 , and a source that is coupled to node N 405 . Transistor M 411  includes a drain and gate that are coupled to node N 406 , and a source that is coupled to node VDD. Transistor M 412  includes a drain that is coupled to node N 406 , a gate that is coupled to node  407 , and a source that is coupled to GND. Transistor M 413  includes a drain and gate that are coupled to node N 407 , and a source that is coupled to GND. Transistor M 414  includes a drain that is coupled to node N 407 , a gate that is coupled to INM 4 , and a source that is coupled to node N 408 . Transistor M 415  includes a drain that is coupled to node N 403 , a gate that is coupled to INP 4 , and a source that is coupled to node N 408 . Transistor M 416  includes a drain and gate that are coupled to node N 403 , and a source that is coupled to GND. Transistor M 417  includes a drain that is coupled to OUT, a gate that is coupled to node N 403 , and a source that is coupled to GND. Transistor M 418  includes a drain that is coupled to OUT, a gate that is coupled to node N 406 , and a source that is coupled to VDD. Logic gate G 401  is coupled between ENB — P and node N 401 , while logic gate G 402  is coupled between ENB — N and node N 402 . Logic gates G 401  and G 402  have a high power supply signal that is coupled to VDD, and a low power supply signal that is coupled to VDD/2. Current source I 401  is coupled between node N 405  and GND, while current source  1402  is coupled between VDD and node N 408 . 
   Differential Receiver Circuit: Normal Operating Mode 
   During the normal operating mode, the differential receiver circuit ( 400 ) is enabled by signals ENB — N and ENB — P. For the exemplary circuit illustrated in  FIG. 4 , signal ENB — N and ENB — P corresponds to logic  0  when the normal operating mode is selected. Transistors M 405  and M 406  are deactivated and have no effect in this operating mode. 
   Logic gate G 401  provides an inverse logic signal at node N 401  in response to one input signal (ENB — P), while logic gate G 402  provides an inverse logic signal at node N 402  in response to the other input signal (ENB — N) Transistor pairs M 401 , M 402  and M 403 , M 404  are arranged to operate as switching circuits that pass input signals from INP and INM to INP 4  and INM 4 , respectively. 
   Transistors M 417  and M 418  are arranged as an output stage in the differential receiver circuit ( 400 ). The output stage is configured to provide an output signal to OUT in response to signals from INP and INM, which are provided to two differential pair circuits that cooperate with the output stage to operate over a rail-to-rail common mode input range. 
   The first differential pair circuit includes transistors M 409 , M 410 , and current source I 401 . The first differential pair circuit steers current IT 41  from current source I 401  in response to the difference between signals from INP 4  and INM 4 . Transistors M 408  and M 407  are arranged as a first current mirror circuit that is responsive to current from transistor M 409 , and provides biasing to transistor M 417 . Transistors M 411  and M 418  are arranged as a second current mirror circuit that is responsive to current from transistor M 410 . 
   The second differential pair circuit includes transistors M 414 , M 415 , and current source  1402 . The second differential pair circuit steers current IT 42  from current source  1402  in response to the difference between signals from INP 4  and INM 4 . Transistors M 412  and M 413  are arranged as a third current mirror circuit that is responsive to current from transistor M 414 , and provides biasing to transistor M 411 . Transistors M 416  and M 417  are arranged as a fourth current mirror circuit that is responsive to current from transistor M 415 . 
   Differential Receiver Circuit: Over-Voltage Operating Mode 
   During the over-voltage operating mode, the differential receiver circuit ( 400 ) is protected from high input voltages (e.g., at the INP and INM terminals) when either one of signals ENB — N or ENB — P are active. For the exemplary circuit illustrated in  FIG. 4 , signal ENB — N and/or ENB — P corresponds to logic  1  when the over-voltage operating mode is selected. Transistors M 405  and M 406  are configured to operate as pull-up circuits that couple at least one of INP 4  and INM 4  to VDD in the over-voltage operating mode. 
   In one example over-voltage operating mode, the ENB — P signal corresponds to logic  1  when the input signal at INP exceeds the high power supply voltage (VDD). The logic  1  signal disabled transistor M 401 . Logic gate G 401  provides a logic  0  signal at node N 401 , which activates transistor M 405  such that VDD is coupled to INP 4 . 
   In another example over-voltage operating mode, the ENB — N signal corresponds to logic  1  when the input signal at INM exceeds the high power supply voltage (VDD). The logic  1  signal disabled transistor M 404 . Logic gate G 402  provides a logic  0  signal at node N 402 , which activates transistor M 406  such that VDD is coupled to INM 4 . 
   Transistors M 401 –M 418  are arranged to operate within the processing limits such that the differential receiver circuit ( 400 ) withstands the over-voltage condition on the input signals (INP, INM, which corresponds to D+ and D− as shown in  FIG. 1 ) without damage. The pull-up circuits (e.g., transistors M 405  and M 406 ) ensure that the gate of transistors M 409 , M 410 , M 414 , and M 415  never exceed the high power supply voltage (VDD). 
   The body connections for transistors M 401  and M 404  are coupled to VPNWELL and VNNWELL, respectively. VPNWELL is coupled to the higher of VDD and the respective input signal (INP, D+) from one of the driver circuits ( 200 ), while VNNWELL is coupled to the higher of VDD and the respective input signal (INM, D−) from another one of the driver circuits ( 200 ), as previously described with respect to  FIG. 2 . Since the body terminal for each of transistors M 401  and M 404  is always connected to the highest potential (either VDD or the input signal), the parasitic drain-well diodes in transistors M 401  and M 404  will remain reverse biased. 
   The voltage associated with the logic  1  signal for ENB — P corresponds to the higher of VDD and INP (D+) as will be described later with respect to the over-voltage sense circuit ( 600 ). Similarly, the voltage associated with the logic  1  signal for ENB — N corresponds to the higher of VDD and INM (D−). Transistors M 401  and M 404  have no voltages across their drain-gate terminals during their respective over-voltage conditions. 
   Since logic gate G 401  has a low power supply that corresponds to VDD/2 such that the logic  0  signal at node N 401  also corresponds to VDD/2. Similarly, logic gate G 402  has a low power supply that corresponds to VDD/2 such that the logic  0  signal at node N 402  also corresponds to VDD/2. Transistor M 405  has a maximum gate-body voltage that corresponds to the difference between VDD/2 and VPNWELL. Similarly, transistor M 406  has a maximum gate-body voltage that corresponds to the difference between VDD/2 and VNNWELL. 
   The differential receiver circuit ( 400 ) is arranged to resist glitching in the output signal (OUT) when an AC overshoot causes the ENB signal (or signals) to momentarily change to logic  1 . The pull-up circuits (e.g., transistors M 405 , M 406 ) bypass transistor M 401  and transistor M 404  such that the input signals have no effect on the output signal in the over-voltage operating mode. 
   Exemplary Suspend-Mode Buffer Circuit 
     FIG. 5  is a schematic diagram of an exemplary suspend-mode buffer circuit ( 500 ) that is arranged in accordance with the present invention. The suspend mode buffer circuit ( 500 ) corresponds to a means for buffering that is arranged to provide a buffered sense signal in response to a sense signal from a data line when active. Suspend-mode buffer circuit  500  includes twelve transistors (M 501 –M 512 ). 
   Transistor M 501  includes a drain that is coupled to node N 501 , a gate that is coupled to EN, and a source that is coupled to VDD. Transistor M 502  includes a drain that is coupled to node N 502 , a gate that is coupled to EN, and a source that is coupled to VDD. Transistor M 503  includes a drain that is coupled to IN, a gate that is coupled to VDD, and a source that is coupled to IN 5 . Transistor M 504  includes a drain that is coupled to node N 502 , a gate that is coupled to IN, and a source that is coupled to VDD. Transistor M 505  includes a drain that is coupled to node N 501 , a gate that is coupled to IN, and a source that is coupled to node N 502 . Transistor M 506  includes a drain that is coupled to IN 5 B, a gate that is coupled to ENB, and a source that is coupled to node N 501 . Transistor M 507  includes a drain that is coupled to IN 5 B, a gate that is coupled to IN 5 , and a source that is coupled to node N 503 . Transistor M 508  includes a drain that is coupled to node N 503 , a gate that is coupled to IN 5 , and a source that is coupled to GND. Transistor M 509  includes a drain that is coupled to node N 502 , a gate that is coupled to IN 5 B, and a source that is coupled to VDD. Transistor M 510  includes a drain that is coupled to VDD, a gate that is coupled to IN 5 B, and a source that is coupled to node N 503 . Transistor M 511  includes a drain that is coupled to OUT, a gate that is coupled to IN 5 B, and a source that is coupled to VDD. Transistor M 512  includes a drain that is coupled to OUT, a gate that is coupled to IN 5 B, and a source that is coupled to GND. 
   The suspend mode buffers are normally disabled unless the system is in the suspend mode. For example, the suspend mode buffers are disabled in the normal operating mode, and again during the suspend mode operation. 
   Suspend Mode Buffer: Suspend Mode Operation 
   During the suspend mode, the suspend mode buffer ( 500 ) is enabled by signals ENB — N and ENB — P. For the exemplary circuit illustrated in  FIG. 5 , signal EN corresponds to logic  1  and when the suspend operating mode is selected. Signal ENB corresponds to an inverse of signal EN. Transistors M 501 , M 502  are deactivated in the suspend mode and have no effect on the remaining circuitry in this operating mode. 
   Transistor M 503  is configured to operate as a transmission gate that couples an input signal from IN to IN 5 . Transistors M 504  and M 505  are configured to operate as a cascoded source circuit that is responsive to the input signal from IN, while transistors M 507  and M 508  are arranged to operate as a cascoded sink circuit that is responsive to the input signal from IN 5 . Transistor M 506  is configured to operate as a switching circuit that couples node N 501  to IN 5 B such that the source and sink circuits are coupled together to operate as a cascoded inverter circuit during the suspend mode. Transistors M 511  and M 512  are arranged to operate as an inverter circuit that provides a signal to OUT in response to the signal from IN 5 . 
   Transistors M 509  and M 510  are arranged to provide hysterisis to the cascoded inverter circuit. Transistor M 510  is activated and transistor M 509  is deactivated when the input signal corresponds to logic  0 , such that the cascoded inverter circuit has a first threshold. Transistor M 510  is deactivated and transistor M 509  is activated when the input signal corresponds to logic  1 , such that the cascoded inverter circuit has a second threshold. The first threshold and second threshold are different from one another such that the suspend mode buffers have a hysterisis characteristic that is less susceptible to noise on the data lines. 
   Suspend Mode Buffer: Over-Voltage Operating Mode 
   During the over-voltage operating mode, the suspend mode buffer ( 500 ) is disabled by EN and ENB. For the exemplary circuit illustrated in  FIG. 5 , signal EN corresponds to logic  0  and ENB corresponds to logic  1  when the over-voltage operating mode is selected. Transistors M 501  and M 502  are activated, while transistor M 506  is disabled. 
   Transistor M 503  is arranged to protect transistors M 507  and M 508  from the over-voltage condition on the input signal. The voltage at IN 5  is limited to VDD−VTH, where VTH corresponds to the threshold voltage of transistor M 503 . Thus, the maximum gate-source and gate-drain voltage for transistors M 507  and M 508  corresponds to VDD-VTH, which are within process limits. 
   Transistors M 501  and M 502  are arranged to operate as a protection circuit that protects transistors M 504  and M 505  from the over-voltage condition on the input signal. The voltage at nodes N 501  and N 502  are coupled to VDD. Thus, the maximum gate-source and gate-drain voltages for transistor M 504  and M 505  corresponds to V(IN)−VDD. The drain-source voltages for transistors M 504  and M 505  correspond to zero. 
   Transistor M 506  is disabled such that node N 501  is isolated from IN 5 B, such that the cascoded pull-up network (transistors M 504 , M 505 ) are isolated from the cascoded pull-down network (transistors M 507 , M 508 ). The output of the suspend mode buffer (OUT) is maintained as a high logic signal during the over-voltage condition, maintaining the functionality of the buffer. 
   Exemplary Over-Voltage Sense Circuit 
     FIG. 6  is a schematic diagram of an exemplary over-voltage sense circuit ( 600 ) that is arranged in accordance with the present invention. The over-voltage sense circuit ( 600 ) corresponds to a means for detecting that is arranged to detect an over-voltage condition on a data line. Over-voltage sense circuit  600  includes six transistors (M 601 –M 606 ), two resistors (R 601 , R 602 ), three current sources (I 601 –I 603 ), and four logic gates (G 601 –G 604 ). 
   Transistor M 601  includes a drain and gate that are coupled to node N 601 , and a source that is coupled to VDD. Transistor M 602  includes a drain that is coupled to node N 603 , a gate that is coupled to node N 601 , and a source that is coupled to node N 602 . Transistor M 603  includes a drain and gate that are coupled to node N 604 , and a source that is coupled to node VDD. Transistor M 604  includes a drain that is coupled to node N 604 , a gate that is coupled to node N 603 , and a source that is coupled to node N 605 . Transistor M 605  includes a drain that is coupled to VDD, a gate that is coupled to VDD/2, and a source that is coupled to node N 605 . Transistor M 606  includes a drain that is coupled to node N 606 , a gate that is coupled to node N 604 , and a source that is coupled to VDD. Resistor R 601  is coupled between SNS and node N 602 . Resistor R 602  is coupled between node N 603  and GND. Current source I 601  is coupled between node N 601  and GND. Current source I 602  is coupled between node N 605  and GND. Current source I 603  is coupled between node N 606  and GND. Logic gate G 601  is coupled between node N 606  and node N 607 . Logic gate  0602  is coupled between node N 607  and ENB. Logic gate  0603  is coupled between ENB and EN. Logic gate G 604  is coupled between EN and ENB — H. 
   The over-voltage sense circuit is active in all operating modes. Voltage VX corresponds to the higher of VDD and a respective one of the data lines (D+ or D− from  FIG. 1 ). The voltage for VX corresponds to the VNWELL signal from the driver circuits (either VPNWELL or VNNWELL). Logic gate G 604  includes a cascode circuit arrangement such that the logic gate can withstand higher voltages. For example, logic gate G 604  may comprise an inverter circuit that has stacked P-type devices and stacked N-type devices such that the inverter is a cascoded inverter circuit. The output voltage from logic gate G 604  corresponds to either a ground level or a level corresponding to VX. 
   Current source I 601  and transistor M 601  are arranged to provide a first reference signal (VT) to node N 601 . Transistor M 602  is arranged to cooperate with resistor R 601  and R 602  such that they provide a second reference signal (VR) at node N 603 . One of the data lines (D+ or D−) is coupled to the sense node (SNS) such that transistor M 602  detects when SNS exceeds a trip point. The trip point is determined by resistor R 602 , transistor M 602 , and the first reference signal (VT). Resistor R 601  is arranged to limit the current to transistor M 602 . 
   Transistors M 604  and M 605  are arranged to operate as a differential pair that shares a common connection to current source I 602 . Transistor M 603  activates transistor M 606  when the second reference signal (VR) exceeds VDD/2, indicating that the sense node (SNS) has detected the over-voltage condition. Node N 606  changes from logic  0  to logic  1  when transistor M 606  is activated such that the logic circuits (G 601 –G 604 ) detect the over-voltage condition. Signals ENB and ENB — H correspond to logic  1 , and signal EN corresponds to logic  0  when the over-voltage condition is detected. 
   The above-described examples include discrete components and circuits that are combined together to provide an over-all functionality. One or more of the circuit blocks may be combined together, or separated apart without departing from the spirit of the present invention. Moreover, the over-all circuit topologies may be applied to field effect devices, bipolar junction devices as well as other technologies. 
   The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.