Abstract:
Pulse width modulation of the connection of a load output terminal to a power supply terminal is effected. In response to a first level of the pulse width modulated signal, the load is disconnected from the power supply terminal, steady-state load voltage is preserved on a capacitor connected between a load output terminal and a power supply terminal, and steady-state load current information is held on a capacitor within the feedback loop. In response to a second level of the pulse width modulated signal, the load is reconnected to the power supply terminal, and load voltage and current instantaneously resume at their correct steady-state values.

Description:
TECHNICAL FIELD  
       [0001]     The present disclosure relates to pulse-width-modulation control for a switch-mode power supply voltage regulator, more particularly to improving operation at frequencies above the power supply control loop&#39;s crossover frequency.  
       BACKGROUND  
       [0002]     A conventional switch-mode power supply is illustrated in the block diagram of  FIG. 1 . The voltage applied to load  10  at the V OUT  node is regulated by the power supply circuit. The load is connected in series with a signal responsive switch  12 , the series circuit connected across output capacitor  14 . The capacitor and switch are both directly connected to the ground power supply terminal. The other power supply terminal, V IN , is connected to the V OUT  node through inductance  16  and diode  18 . V SW , the junction of the inductance and diode, is connected through signal responsive switch  20  to ground via current-sense resistor  13 . Signal responsive switches such as  12  and  20  are typically electronic switches having gate activation. Signal responsive switch  12  is operable in response to a pulse width modulated signal PWM. Signal responsive switch  20  is operable in response to a feedback control circuit that comprises error amplifier  22 , capacitor  24 , oscillator  11 , comparator  15 , and latch  28 . A reference voltage V REF  is applied to a first input of the error amplifier  22 . The voltage at the V OUT  node, or a fraction thereof, is applied to the second input of the error amplifier. Capacitor  24  is charged and discharged by the output of the error amplifier.  
         [0003]      FIG. 2  illustrates time waveforms of various circuit parameters during normal operation of the conventional circuit of  FIG. 1 . Waveform (A) represents pulse width modulation signal PWM. Waveform (B) represents a voltage signal applied to the V GATE  of signal responsive switch  20 . Voltage at the V OUT  node is shown in waveform (C). Voltage V ITH  at the output of error amplifier  22  is shown in waveform (D). In operation, at time t 1 , the PWM signal is high and switch  12  is closed so that the load is connected to ground. While in this condition, the switch  20  is switched at a peak current level, sensed as V SENSE =V ITH , that is required to maintain voltage V OUT  at a level equal to V REF . This circuit configuration functions in a well known manner as a current-mode voltage boost regulator, wherein V OUT  is greater than V IN , and the error amplifier output directly controls the peak switching/inductor current. The switching of V GATE  is implemented by the S-R latch  28  in response to the rising edge of oscillator  11 , which sets the latch, raising V GATE  and closing switch  20 . Switch  20  is opened when V SENSE  crosses the level of voltage V ITH  at capacitor  24 , which crossing trips the output of comparator  15 , resetting latch  28 . Switch  20  is again closed at the next rising edge provided by oscillator  11 . When switch  20  is in the closed state and switch  12  is in the closed state, charge on capacitor  14  discharges through the load  10 . When switch  20  is in the open state and switch  12  is in the closed state, charge is applied to capacitor  14  from the power supply via diode  18 . Voltage V OUT  and voltage V ITH  are relatively constant in steady-state operation, as shown by waveforms (C) and (D), respectively.  
         [0004]     At time t 2  the PWM signal goes low to set switch  12  to an open state, causing instantaneous disconnection of the output load from ground. When the load current is interrupted, a V OUT  overvoltage condition occurs as the supply continues to deliver excess output current through the inductance  16  to the output capacitor  14  during the duty cycle switching of switch  20 . The V OUT  overvoltage condition, as shown in waveform (C), continues until the feedback control loop has time to correct for the error. As excess output current is delivered to the output capacitor  14 , V OUT  increases. The increased feedback voltage (V REF - V OUT ), applied to the error amplifier, decreases the charge applied to capacitor  24 , as indicated by current waveform (D), thereby resulting in a decreased peak switching current at which switch  20  opens. The current I L  is shown in waveform (E). The changes of voltages V OUT  and V ITH  decrease toward a steady-state value as correction is made by the circuit for the transient effects of the PWM signal change. The time required to reach a new steady-state value is related to the closed-loop bandwidth and crossover frequency for the control loop.  
         [0005]     At time t 3  the PWM signal again goes high and the load is reconnected to ground through now-closed switch  12 . At that time the periodic signal V GATE  applied to switch  20  had been adjusted to supply the appropriate charge to capacitor  14  with the load disconnected. A V OUT  undervoltage condition occurs upon reconnection of the load as it will discharge capacitor  14  because the peak current supplied by switch  20  at that time, as shown in waveform (E), is not appropriate to the changed condition. The undervoltage condition continues until the feedback control loop can correct and recharge the capacitor. The negative feedback voltage is acted upon by the feedback control loop to adjust the current limit imposed on switch  20  such that the charge applied to capacitor  14  is increased. Voltages V OUT  and V ITH  increase toward their appropriate steady-state values as correction is made by the circuit for the transient effects of the PWM signal change.  
         [0006]     The magnitude and time extents of the overvoltage and undervoltage conditions depend on control loop parameters, load conditions, and PWM switching frequency. Effective PWM control of a load is thus fundamentally limited to frequencies substantially below that at which the control loop can correct perturbations. The need thus exists for a pulse width modulated control arrangement for a switch-mode power supply that is operable at high frequencies.  
       SUMMARY OF THE DISCLOSURE  
       [0007]     The subject matter described herein fulfills the above-described needs of the prior art at least in part by providing a method for effecting pulse width modulation of the connection of a load to a power supply terminal in response to a first level of a pulse width modulated signal, which disconnects the load from the power supply terminal in response to a second level of the pulse width modulated signal, and charges a capacitor connected between the load output terminal and the power supply terminal at a peak current level controlled in response to the voltage at the output terminal via a feedback control loop only when the pulse width modulated signal is at the first level. Charging of the capacitor is inhibited when the pulse width modulated signal is at a second level.  
         [0008]     In accordance with an aspect of the disclosure, a first signal responsive switch is connected in series with the load between a voltage output node and the power supply terminal, the switch operative between an open and closed state in response to a pulse width modulation signal. A second signal responsive switch is connected in series with an impedance and a power supply terminal to draw current from the power supply through the impedance when the second signal responsive switch is in a closed state. A feedback circuit is connected between a load circuit terminal and the second signal responsive switch for controlling the state of the second signal responsive switch. A voltage representative of a load parameter is subtracted from a reference voltage by a error amplifier to obtain an error current applied to a storage capacitor. The storage capacitor voltage is converted to a peak current limit imposed on the second signal responsive switch. The load parameter may be load voltage taken at the load output terminal, or load current derived from a resistance connected in series with the load.  
         [0009]     The feedback circuit is responsive to the pulse width modulation signal so as to be inactive when the first signal responsive switch is in the open state. A third signal responsive switch is connected in series with the error amplifier and also responsive to the pulse width modulation signal so as to be in the same state as the first signal responsive switch. A logic element having a first input terminal connected to the feedback circuit and a second input terminal connected to the pulse width modulated signal, and an output terminal connected to the second signal responsive switch ensure that the second signal responsive switch is in an open state when the other signal responsive switches are in an open state. Peak switch current information proportional to load current state is thus stored by the storage capacitor when the load is disconnected from the power supply terminal.  
         [0010]     Additional advantages will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     Implementations of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.  
         [0012]      FIG. 1  is a block diagram of a conventional switch-mode power supply.  
         [0013]      FIG. 2  is illustrative of time waveforms for the circuit of  FIG. 1 .  
         [0014]      FIG. 3  is a block diagram of a switch-mode power supply in accordance with the present invention.  
         [0015]      FIG. 4  is illustrative of time waveforms for the circuit of  FIG. 3 .  
         [0016]      FIG. 5  is a block diagram of a variation of the switch-mode power supply of  FIG. 3 .  
         [0017]      FIG. 6  is a block diagram of a variation of the switch-mode power supplies of  FIGS. 3 and 5 .  
     
    
     DETAILED DESCRIPTION  
       [0018]     The regulator circuit depicted in  FIG. 3  contains some of the same elements as shown in  FIG. 1  that are identified by the same reference numerals. As in  FIG. 1 , the voltage applied to load  10  at the V OUT  node is regulated by the power supply circuit. The load is connected in series with a signal responsive switch  12 , the series circuit connected across output capacitor  14 . The capacitor and switch are both directly connected to the ground power supply terminal. The other power supply terminal, V IN , is connected to the V OUT  node through inductance  16  and diode  18 . The junction of the inductance and diode, V SW , is connected to ground through the series combination of signal responsive switch  20  and current-sense resistor  13 .  
         [0019]     Signal responsive switch  12  is operable in response to a pulse width modulated signal PWM. Signal responsive switch  20  is operable in response to a feedback control circuit that comprises error amplifier  22 , third signal responsive switch  30 , capacitor  24 , oscillator  11 , comparator  15 , latch  28 , and AND gate  32 . The pulse width modulation signal PWM is coupled to switch  30  and to one input of AND gate  32 . The other input of AND gate  32  is coupled to latch  28  for receipt of the feedback loop switching signal output. The output of AND gate  32 , V GATE , is applied to the gate of the switch  20 . Reference voltage V REF  is applied to a first input of the error amplifier. The voltage at the V OUT  node, or a fraction thereof, is applied to the second input of the error amplifier.  
         [0020]     Operation of the circuit of  FIG. 3  is as follows, with reference to the waveforms of  FIG. 4 . At time t 1 , the PWM signal, shown in waveform (A), is high. The high signal, applied to the gates of switches  12  and  30 , drives these switches to a closed state. The high signal is also received at one input of the AND gate  32 . During this time, switch  12  is closed so that the load is connected to ground. As switch  30  is closed and a high signal is applied to an input of the AND gate  32 , the switch  20  is switched by the feedback loop at a peak current that is required to maintain voltage V OUT  at a level equal to V REF . The output signal V GATE  of AND gate  32  is shown in waveform (B). Voltages V OUT  and V ITH  are relatively constant, as shown by waveforms (C) and (D), respectively.  
         [0021]     At time t 2 , the PWM signal goes low and is effective to drive switches  12  and  30  to an open state and to prevent a high output signal from AND gate  32 . Thus, during the low signal period between t 1  and t 2  switch  20  is maintained in an open state and no periodic switching takes place. As switch  20  and switch  12  remain open, capacitor  14  effectively holds the load voltage value constant. As the switch  30  disconnects the output of the error amplifier from capacitor  24 , the voltage at that capacitor remains unchanged, and thus effectively holds V ITH , the desired steady-state peak current value, constant. The load current information at time t 2  is thus stored until the PWM signal goes high at time t 3 , and there is no need for the charge current to capacitor  24  to build up when switch  12  returns to a closed state. During that time period, voltage V OUT  and current V ITH  remain relatively constant at their earlier levels. No over or under voltage condition exists that will be in need of correction.  
         [0022]     At time t 3  the PWM signal again goes high to again drive switches  12  and  30  to a closed state and AND gate  32  to a mode in which the feedback duty cycle signal will be applied to the V GATE  of switch  20 . As voltages V OUT  and V ITH  are already at their steady-state levels, the circuit functions without the need to correct for transients caused by the change in level of the PWM signal. Voltages V OUT  and V ITH  remain relatively constant at their same levels while periodic switching of switch  20  again takes place.  
         [0023]      FIG. 5  is a block diagram of a variation of the switch-mode power supply of  FIG. 3  and differs therefrom in the following manner. Connected between switch  12  and ground power supply terminal is resistor  34 . When switch  12  is in the closed state the voltage at V S  is a function of the current drawn by the load. That voltage is applied to the one input of the error amplifier to be subtracted from the voltage V REF  applied at the other input terminal. Thus, the circuit of  FIG. 5  provides periodic switching of switch  20  as a function of load current I OUT  In the operation of the circuit of  FIG. 5 , switches  12 ,  20  and  30  are responsive to changes in the level of the PWM signal in the same manner as described with respect to the operation of the  FIG. 3  circuit. The waveforms shown in  FIG. 4  also depict the operation of the  FIG. 5  arrangement. This arrangement can be used to advantage with loads that are non-linear in nature.  
         [0024]      FIG. 6  is a block diagram of a variation of the switch-mode power supplies of  FIG. 3  and  5 . Multiplier  36  has a first input connected to receive the voltage at V S  and a second input to receive the output voltage V OUT . The output V POWER  of the multiplier is applied to the negative input of error amplifier  22 . V POWER  is the scaled product of load voltage and load current and is subtracted from the voltage V REF  applied at the other input terminal of the error amplifier. Thus, the circuit of  FIG. 6  provides periodic switching of switch  20  as a function of V POWER , a voltage proportional to load power. In the operation of the circuit of  FIG. 6 , switches  12 ,  20  and  30  are responsive to changes in the level of the PWM signal in the same manner as described with respect to the operation of the circuits of  FIG. 3  and  FIG. 5 . The waveforms shown in  FIG. 4  also depict the operation of the  FIG. 6  arrangement. The power supply of  FIG. 6  can be used to advantage with nonlinear loads when power is the parameter of interest.  
         [0025]     In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein. For example the concepts expressed herein with respect to the illustrated boost regulator circuits are equally applicable to other well known regulators including buck, buck/boost, flyback, forward, inverting SEPIC and zeta configurations.