Abstract:
A method and system for synchronizing to an incoming Hsync signal, and for generating a phase locked clock signal in response thereto. The Hsync signal and an incoming clock are coupled to a sequence of modules. Each module includes a latch for sampling the incoming clock on a transition of the Hsync signal, whose output is combined (using an XOR gate) with the Hsync signal. Each module includes a time delay for generating a delayed clock signal, incrementally delayed from the previous module in the sequence, so that the clock signal for each module is phase-offset from all other modules. The latch outputs are summed using a resistor network, to produce a triangle-shaped waveform which is phase locked to the Hsync signal and which is frequency locked to the incoming clock. The triangle-shaped waveform is compared with a constant voltage to produce a square wave.

Description:
This application is a continuation of Ser. No. 08/593,325, filed Jan. 31, 1996, U.S. Pat. No. 5,719,511. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to synchronizing and clock generating circuits, and methods for using the same. 
     2. Description of Related Art 
     In computer systems and other digital systems for displaying video signals, it is common to receive an incoming video signal and to synchronize to its timing. The incoming video signal typically includes a horizontal sync (Hsync) signal, a periodic signal having a period of one horizontal line of video, and having a clock edge in phase with a beginning point for each such horizontal line. 
     It is generally desirable to synchronize other higher frequency signals to the Hsync signal, such as a pixel clock (Pclock) signal. The Pclock frequency is typically 2000 times the Hsync frequency. This is often accomplished with a phase locked loop. However, use of a phase locked loop is subject to a substantial drawback. The Hsync signal may not be precise, and its frequency may vary over time, causing other higher frequency signals such as the Pclock signal to have a significant jitter, making it substantially unusable for graphics applications, for example. Because higher frequency signals are a substantial multiple of the Hsync frequency, resulting variation in those signals can be substantial and is undesirable. 
     Accordingly, it would be advantageous to provide a circuit for synchronizing and for generating a clock signal. 
     SUMMARY OF THE INVENTION 
     The invention provides a method and circuit for synchronizing to an incoming Hsync signal or other incoming signal, and for generating a phase locked clock signal or other high frequency signal in response thereto. A set of parallel clock signals are sampled by the Hsync signal, to produce a set of sample clock bits. The sample clock bits are logically combined with the Hsync signal and summed, to produce a summed signal which is phase locked to the Hsync signal and has the same period as the clock signals. In a preferred embodiment, the summed signal is compared with a reference, to produce a square wave output, which may be used as a Pclock or other clock signal. 
     In a preferred embodiment, the Hsync signal and an incoming clock are coupled to a sequence of modules. Each module comprises a latch for sampling the incoming clock on a transition of the Hsync signal, whose output is combined (using an XOR gate) with the Hsync signal. Each module comprises a time delay for generating a delayed clock signal, incrementally delayed from the previous module in the sequence, so that the clock signal for each module is phase-offset from all other modules. The latch outputs are summed using a resistor network, to produce a triangle-shaped waveform which is phase locked to the Hsync signal and which is frequency locked to the incoming clock. The triangle-shaped waveform is compared with a constant voltage to produce a square wave. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a first part of a circuit for synchronizing to an incoming Hsync signal and for generating a phase locked high frequency signal in response thereto. 
     FIG. 2 shows a timing diagram of signals synchronized to an incoming clock. 
     FIG. 3 shows a second part of a circuit for synchronizing to an incoming Hsync signal and for generating a phase locked high frequency signal in response thereto. 
     FIG. 4 shows a timing diagram of signals synchronized to the incoming Hsync signal. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a first part of a circuit for synchronizing to an incoming Hsync signal and for generating a phase locked high frequency signal in response thereto. 
     A circuit  100  comprises a first input node  101  for receiving an incoming signal and a second input node  102  for receiving an incoming clock. 
     In a preferred embodiment, the incoming signal at the node  101  comprises a horizontal sync (Hsync) signal for a video signal, and has a frequency range of from about 31.5 KHz to about 70 KHz, depending on the nature of the video board and the screen resolution. In alternative embodiments, the incoming signal may comprise another signal with a periodic edge transition. 
     In a preferred embodiment, the incoming clock at the node  102  comprises a clock signal at a frequency range of between about 20 MHz to about 80 MHz, corresponding to a clock period of between about 12.5 nanoseconds and about 50 nanoseconds. 
     The circuit  100  comprises an output node  103  for supplying a generated clock. In a preferred embodiment, the generated clock at the node  103  is used as a pixel clock signal (Pclock) by video circuits coupled thereto. 
     The Hsync signal at the first node  101  is coupled to an Hsync line  110 , which is coupled to a plurality of modules  120 . 
     Each module  120  comprises a D flip-flop  121 , having a D input, a clock input, and a Q output. The D flip-flop  121  operates to store a single data bit appearing at its D input when an edge transition occurs at its clock input, and to present that data bit at its Q output at all times. D flip-flops are known in the art of digital circuit design. 
     Each module  120  comprises an XOR gate  122 , having a first input, a second input, and an output. The XOR gate  122  computes the logical “exclusive OR” of its two inputs. XOR gates are known in the art of digital circuit design. 
     Each module  120  comprises a time delay  123 , having an input and an output. The time delay  123  presents the signal appearing at its input, after a time delay, as an identical signal at its output. Time delay elements are known in the art of digital circuit design. 
     The Hsync line  110  is coupled to each module  120  at the clock input of its D flip-flop  121 . 
     The incoming clock at the second node  102  is coupled to a CLOCK line  111 , which is also coupled to the plurality of modules  120 , but is subjected to an incremental time delay at each successive module  120 . 
     The (undelayed) CLOCK line  111  is coupled to a first module  120  at the D input for the D flip-flop  121 , at the first input for the XOR gate  122 , and at the input for the time delay  123 . The output of the time delay  123  for the first module  120  provides a delayed clock, which is the incoming clock delayed by one unit τ (tau) of time delay, on a delayed clock line  112 . 
     The delayed clock line  112  (the incoming clock delayed by τ, labeled CK 1 ), is coupled to the second module  120  in like manner as the CLOCK line  111  is coupled to the first module  120 . Similarly, a second delayed clock line  112  (the incoming clock is delayed by 2τ, labeled CK 2 ), is coupled to the third module  120 , and so on, so that in general the incoming clock, delayed by Nτ, where N is an integer, is coupled using an Nth delayed clock line  112  to the (N+1) st module  120 . 
     Within each module  120 , the Q output of the D flip-flop  121  is coupled to the second input of the XOR gate  122 . The output of the XOR gate  122  is coupled to a node  124 , labeled S 1 , S 2 , and so on, respectively for each module  120 , thus generating one output bit per module  120 . 
     In a preferred embodiment, there are typically eight modules  120 , and each time unit τ typically comprises 3 nanoseconds. However, in alternative embodiments, different values of the time unit τ may be used. 
     FIG. 2 shows a timing diagram of signals synchronized to an incoming clock. 
     The clock signal  200  on the CLOCK line  111  is shown in parallel with the clock signals  200  on the delayed clock lines  112 . Each clock signal  200  is incrementally delayed by one time unit τ for each module  120 . Thus, CK 1  is delayed by τ, CK 2  is delayed by 2τ, and so on, up to CK 7  in a embodiment having eight modules  120 , which is delayed by 7τ. 
     A transition  201  represents a time of transition from logic “1” to logic “0” for an Hsync signal on the Hsync line  110 . Due to the incremental delays, some of the clock signals  200  are logic “0” at the transition  201 , while others of the clock signals  200  are logic “1” at the transition  201 . 
     The Hsync signal on the Hsync line  110  clocks the D flip-flop  121  for each of the modules  120 , causing the D flip-flop  121  to sample the value of its corresponding clock signal  200 , and causing the Q output of each D flip-flop  121  to take on that value. A sampled clock waveform  202  shows the sampled value for each D flip-flop  121  at the transition  201 . 
     In those modules  120  where the sampled value is logic “0”, the output of the XOR gate  122  (and thus the logic value at the node  124 ) will be equal to its corresponding clock signal  200 , while in those modules  120  where the sampled value is logic “1”, the output of the XOR gate  122  will be the inverse of its corresponding clock signal  200 . 
     FIG. 3 shows a second part of a circuit for synchronizing to an incoming Hsync signal and for generating a phase locked high frequency signal in response thereto. 
     Each node  124  (also shown in FIG. 1) is coupled to a resistor  300  in a resistor network  301 . The resistors  300  all have equal resistance value and are all coupled to a summing node  302 , so as to generate a signal at the summing node  302  which is the analog sum of the signals at the nodes  124 . 
     In alternative embodiments, the resistors  300  may have differing values, so as to generate a signal which is a weighted sum. Alternatively, another circuit for summing or another technique for summing may be used. 
     The summing node  302  is coupled to a comparator  303  at a positive input. The comparator  303  comprises a negative input, which is coupled to a reference, preferably a constant 2.5 volts for the CMDS logic family. The comparator  303  also comprises an output, which is coupled to the output node  103  for supplying the generated clock. 
     In alternative embodiments, another reference may be used, such as another reference voltage for another logic family or another reference voltage for the CMDS logic family. 
     FIG. 4 shows a timing diagram of signals synchronized to the incoming Hsync signal. 
     Output signals  400  at the nodes  124  are shown in parallel, each corresponding either to one of the clock signals  200  (CLOCK, CK 1 , CK 2  and CK 7 ) or to one of the clock signals  200  inverted (CK 3  inverted, CK 4  inverted, CK 5  inverted, CK 6  inverted). 
     A transition line  401  for the Hsync signal on the Hsync line  110  is shown corresponding to an edge transition  402  for the Hsync signal. A sum signal  403  is generated at the summing node  302 ; this sum signal  403  is always zero at the transition  401 . 
     As time passes, the output signals  400  change with changes in the clock signals  200 . A sequence of lines  404  is shown corresponding to later times following the edge transition  402  for the Hsync signal. The sum signal  403  is continuously generated at the summing node  302 ; the sum signal  403  rises and falls in a triangle-shaped waveform with changes in the clock signals  200 , with a period equal to the period of the clock signals  200 . 
     A generated clock signal  405  is generated at the output node  103 , in response to the sum signal  403  at the summing node  302 , using the comparator  303 . The generated clock signal  405  is a square wave. 
     Because the generated clock signal  405  is always zero at the edge transition  402  for the Hsync signal, it is synchronized to the incoming signal at the node  101 . Because the generated clock signal  405  is responsive to the sum signal  403 , it has a frequency equal to the incoming clock at the node  102 . 
     In addition to the generated clock signal  405 , a delayed Hsync signal is generated which is synchronized with the generated clock signal  405  and which skips the first new period of the generated clock signal  405 , so as to avoid any transition between generated clock signals  405  for successive Hsync pulses. 
     In a preferred embodiment, the total delay Kτ, where K is the number of modules  120 , must be greater than one-half of the period of the input clock at node  102 , to be able to sample the input clock. 
     The generated clock signal  405  may have a phase shift at each transition  402 , and the amount of this phase shift depends on the value of the unit time delay τ, the number of modules  120 , and on the input clock frequency. For eight modules  120 , the phase shift will be no more than τ in the worst case (when the input clock has a period exactly equal to 2τ). 
     ALTERNATIVE EMBODIMENTS 
     Although preferred embodiments are disclosed herein, many variations are possible which remain within the concept, scope, and spirit of the invention, and these variations would become clear to those skilled in the art after perusal of this application.