Abstract:
Apparatus for calibrating a transmitter of a first integrated circuit, the transmitter being capable of transmitting a signal at N different transmit power levels based on N respective calibration values stored in the first integrated circuit, wherein N&gt;1, the apparatus having corresponding methods, comprise: a power meter to measure a received power level of the signal transmitted at one of the N power levels; and a calibration circuit comprising an adjustment circuit to adjust the calibration value for the power level until the received power level of the signal falls within a predetermined range, and an offset circuit to replace each of the calibration values for the N−1 remaining transmit power levels based on the adjusted calibration value for the transmit power level and a respective predetermined offset from the adjusted calibration value.

Description:
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/862,520, filed on Oct. 23, 2006, the disclosure thereof incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The present invention relates generally to signal transmission. More particularly, the present invention relates to predictive transmitter calibration. 
     In general, transmitters must be calibrated after manufacture to ensure that the transmitted power falls within ranges set by design, industry standards, and the like. For example, a wireless local-area network (WLAN) chip generally includes a register to store a calibration value for each of the multiple power levels at which the chip can transmit, and in each of the multiple frequency bands the chip employs. During calibration, in each channel, and for each power level, a receiver measures the power transmitted by the chip, and adjusts the respective calibration value to bring that power level within a predetermined range. Currently, this process must be repeated several times for each power level, for each frequency band, for each chip. The current calibration scheme is therefore expensive and time-consuming. 
     SUMMARY 
     In general, in one aspect, the invention features an apparatus for calibrating a transmitter of a first integrated circuit, the transmitter being capable of transmitting a signal at N different transmit power levels based on N respective calibration values stored in the first integrated circuit, wherein N&gt;1, the apparatus comprising: a power meter to measure a received power level of the signal transmitted by the first integrated circuit at one of the N transmit power levels; and a calibration circuit comprising an adjustment circuit to adjust the calibration value for the one of the N transmit power levels until the received power level of the signal transmitted by the first integrated circuit at the one of the N transmit power levels falls within a predetermined range, and an offset circuit to replace each of the calibration values for the N−1 remaining transmit power levels based on the adjusted calibration value for the one of the N transmit power levels and a respective predetermined offset from the adjusted calibration value. 
     In some embodiments, the calibration offset values are determined based on power level measurements of a signal transmitted by a transmitter of a second one of the integrated circuits. Some embodiments comprise a power point selector to select the one of the N transmit power levels. In some embodiments, the transmitter of the first integrated circuit is capable of transmitting a signal at N different transmit power levels in each of a plurality of different frequency channels, wherein the apparatus further comprises: a channel selector to select the frequency channels. In some embodiments, the first integrated circuit is compliant with all or part of IEEE standard 802.11, including draft and approved amendments 802.11a, 802.11b, 802.11e, 802.11g, 802.11i, 802.11k, 802.11n, 802.11v, and 802.11w. 
     In general, in one aspect, the invention features a method for calibrating a transmitter of a first integrated circuit, the transmitter being capable of transmitting a signal at N different transmit power levels based on N respective calibration values stored in the first integrated circuit, wherein N&gt;1, the method comprising: measuring a received power level of the signal transmitted by the first integrated circuit at one of the N transmit power levels; and adjusting the calibration value for the one of the N transmit power levels until the received power level of the signal transmitted by the first integrated circuit at the one of the N transmit power levels falls within a predetermined range, and replacing each of the calibration values for the N−1 remaining transmit power levels based on the adjusted calibration value for the one of the N transmit power levels and a respective predetermined offset from the adjusted calibration value. 
     In some embodiments, the calibration offset values are determined based on power level measurements of a signal transmitted by a transmitter of a second one of the integrated circuits. Some embodiments comprise selecting the one of the N transmit power levels. In some embodiments, the transmitter of the first integrated circuit is capable of transmitting a signal at N different transmit power levels in each of a plurality of different frequency channels, wherein the method further comprises: selecting the frequency channels. In some embodiments, the first integrated circuit is compliant with all or part of IEEE standard 802.11, including draft and approved amendments 802.11a, 802.11b, 802.11e, 802.11g, 802.11i, 802.11k, 802.11n, 802.11v, and 802.11w. 
     In general, in one aspect, the invention features an apparatus for calibrating a transmitter of a first integrated circuit, the transmitter being capable of transmitting a signal at N different transmit power levels based on N respective calibration values stored in the first integrated circuit, wherein N&gt;1, the apparatus comprising: power meter means for measuring a received power level of the signal transmitted by the first integrated circuit at one of the N transmit power levels; and means for calibration comprising adjustment means for adjusting the calibration value for the one of the N transmit power levels until the received power level of the signal transmitted by the first integrated circuit at the one of the N transmit power levels falls within a predetermined range, and offset means for replacing each of the calibration values for the N−1 remaining transmit power levels based on the adjusted calibration value for the one of the N transmit power levels and a respective predetermined offset from the adjusted calibration value. 
     In some embodiments, the calibration offset values are determined based on power level measurements of a signal transmitted by a transmitter of a second one of the integrated circuits. Some embodiments comprise power point selector means for selecting the one of the N transmit power levels. In some embodiments, the transmitter of the first integrated circuit is capable of transmitting a signal at N different transmit power levels in each of a plurality of different frequency channels, wherein the apparatus further comprises: channel selector means for selecting the frequency channels. In some embodiments, the first integrated circuit is compliant with all or part of IEEE standard 802.11, including draft and approved amendments 802.11a, 802.11b, 802.11e, 802.11g, 802.11i, 802.11k, 802.11n, 802.11v, and 802.11w. 
     Some embodiments comprise a computer program executable on a processor for calibrating a transmitter of a first integrated circuit, the transmitter being capable of transmitting a signal at N different transmit power levels based on N respective calibration values stored in the first integrated circuit, wherein N&gt;1, the computer program comprising: instructions for measuring a received power level of the signal transmitted by the first integrated circuit at one of the N transmit power levels; and instructions for adjusting the calibration value for the one of the N transmit power levels until the received power level of the signal transmitted by the first integrated circuit at the one of the N transmit power levels falls within a predetermined range, and instructions for replacing each of the calibration values for the N−1 remaining transmit power levels based on the adjusted calibration value for the one of the N transmit power levels and a respective predetermined offset from the adjusted calibration value. 
     In some embodiments, the calibration offset values are determined based on power level measurements of a signal transmitted by a transmitter of a second one of the integrated circuits. Some embodiments comprise instructions for selecting the one of the N transmit power levels. In some embodiments, the transmitter of the first integrated circuit is capable of transmitting a signal at N different transmit power levels in each of a plurality of different frequency channels, wherein the computer program further comprises: instructions for selecting the frequency channels. In some embodiments, the first integrated circuit is compliant with all or part of IEEE standard 802.11, including draft and approved amendments 802.11a, 802.11b, 802.11e, 802.11g, 802.11i, 802.11k, 802.11n, 802.11v, and 802.11w. 
     The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  shows plots of calibration values vs. power levels for a characteristic curve and a calibrated curve. 
         FIG. 2  shows a WLAN chip calibration system comprising a test controller in communication with a device-under-test according to some embodiments of the present invention. 
         FIG. 3  shows a process for the WLAN chip calibration system of  FIG. 2  according to some embodiments of the present invention. 
     
    
    
     The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears. 
     DETAILED DESCRIPTION 
     Embodiments of the present invention provide predictive transmitter calibration techniques that are especially useful with integrated circuit transmitters such as WLAN chips. The inventors have discovered that, for a group of related chips, the relationship between calibration values and transmitted power exhibits a characteristic calibration curve that differs between the chips only in the value of the intercept of the curve with the calibration value axis. Based on this discovery, the inventors have developed a new calibration technique in which, once the characteristic curve has been established for a group of chips, only one power point on the curve need be determined for each chip during calibration. Then the remaining points on the curve can be calculated rather than measured. For example, the calibration value offsets between the power points on the characteristic curve can be determined and used to determine the calibration values for each chip during calibration. Thus multiple power levels for a chip can be calibrated by measuring only one of the power levels. For example, Table 1 shows a table of power levels, calibration values, and offsets characteristic of an example group of chips. 
     
       
         
               
               
               
             
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Power (dBm) 
                 Calibration value 
                 Offset 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 0 
                 0x18 
                 — 
               
               
                 4 
                 0x20 
                 0x20-0x18 = 8 
               
               
                 5 
                 0x22 
                 0x22-0x20 = 2 
               
               
                 10 
                  0x2A 
                 0x2A-0x22 = 8  
               
               
                 11 
                  0x2D 
                 0x2D-0x2A = 3 
               
               
                 14 
                 0x32 
                  0x32-0x2D = 5 
               
               
                 17 
                 0x39 
                 0x39-0x32 = 7 
               
               
                   
               
             
          
         
       
     
     In the example of Table 1, each offset is calculated as the difference in the calibration values between the current power point and the previous power point. Of course, the offsets can be calculated in other ways. For example, all of the offsets could be referenced to the same power point, and the like. The characteristic data of Table 1 can be obtained by calibrating a statistically significant number of the chips in a group by conventional measurement methods, and compiling the calibration values to obtain the calibration value offsets shown in Table 1. 
     Table 2 shows a table of power levels and calibration values calculated for a single chip from the group of chips characterized by Table 1. 
     
       
         
               
               
             
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 Power (dBm) 
                 Calibration value 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 0 
                 0x12 (measured) 
               
               
                 4 
                 0x12 + 8 = 0x1A 
               
               
                 5 
                 0x1A + 2 = 0x1C 
               
               
                 10 
                 0x1C + 8 = 0x24 
               
               
                 11 
                 0x24 + 3 = 0x27 
               
               
                 14 
                 0x27 + 5 = 0x3C 
               
               
                 17 
                 0x3C + 7 = 0x43 
               
               
                   
               
             
          
         
       
     
     Referring to Table 2, only a single power point (0 dBm) has been calibrated by conventional measurement techniques, resulting in a calibration value of 0×12 for that power point. The remaining calibration values in Table 2 have been calculated using the that calibration value and the offsets from Table 1. For example, the calibration value for the second power point (4 dBm) is calculated by adding the offset for that power point from Table 1 (8) to the measured calibration value (0×12) of the previous power point (0 dBm) to yield 0×12+8=0x1A.  FIG. 1  shows plots of calibration values vs. power levels for both the characteristic curve  102  of Table 1 and the calibrated curve  104  for the chip of Table 2. Note that the only significant difference in the curves is the value of the intercept with the calibration value axis. 
       FIG. 2  shows a WLAN chip calibration system  200  comprising a test controller  202  in communication with a device-under-test (DUT)  204  according to some embodiments of the present invention. DUT  204  can be compliant with all or part of IEEE standard 802.11, including draft and approved amendments such as 802.11a, 802.11b, 802.11e, 802.11g, 802.11i, 802.11k, 802.11n, 802.11v, and 802.11w. But while embodiments of the present invention are described with respect to calibrating WLAN chips, they are also applicable to calibrating other sorts of transmitters, and are not limited to integrated circuit transmitters or wireless communications. 
     Although in the described embodiments, the elements of test controller  202  are presented in one arrangement, other embodiments may feature other arrangements, as will be apparent to one skilled in the relevant arts based on the disclosure and teachings provided herein. For example, the elements of test controller  202  can be implemented in hardware, software, or combinations thereof. 
     Referring to  FIG. 2 , DUT  204  includes a chip controller  206  to control DUT  204 , an electrically-erasable programmable read-only memory (EEPROM)  208  to store calibration values, for example as a look-up table, a power amplifier (PA)  210  to amplify a signal according to the calibration values stored in EEPROM  208 , and an RF section  212  to generate an RF signal  214  based on the amplified signal. Test controller  202  includes a power meter  216  to measure power levels of RF signal  214 , and a calibration circuit  218  to modify the calibration values stored in EEPROM  208  of DUT  204 . 
     Calibration circuit  218  includes an adjustment circuit  220 , a memory  222 , and an offset circuit  224 . Adjustment circuit  220  adjusts a calibration value stored in EEPROM  208  of DUT  204  based on power level measurements of RF signal  214 . Memory  222  stores calibration value offsets for a characteristic curve for a group of devices including DUT  204 , for example such as the offsets of Table 1. Offset circuit  224  calculates calibration values based on the calibration value determined by adjustment circuit  220  and the offsets stored in memory  222 . 
     Test controller  202  can also include a power point selector  226  and a channel selector  228 . Power point selector  226  selects the power points for calibration of DUT  204 . Channel selector  228  selects frequency channels for calibration when DUT  204  can transmit in multiple frequency channels. 
       FIG. 3  shows a process  300  for WLAN chip calibration system  200  of  FIG. 2  according to some embodiments of the present invention. Although in the described embodiments, the elements of process  300  are presented in one arrangement, other embodiments may feature other arrangements, as will be apparent to one skilled in the relevant arts based on the disclosure and teachings provided herein. For example, in various embodiments, some or all of the steps of process  300  can be executed in a different order, concurrently, and the like. 
     In calibration process  300 , test controller  202  first calibrates a power point by measurement of RF signal  214 , and then calibrates the remaining power points, without measurement of RF signal  214 , by calculations using the calibrated power point and data describing a characteristic curve for DUT  204 . Referring to  FIG. 3 , in embodiments wherein DUT  204  can transmit on multiple frequency channels, channel selector  228  selects one of the channels for calibration (step  302 ). Power point selector  226  of test controller  202  selects a power point for calibration by measurement (step  304 ). In response, chip controller  206  of DUT  204  causes DUT  204  to transmit RF signal  214  at the selected power point and channel. In the described embodiments, the power point selected for calibration by measurement is 0 dBm, but of course, another power point can be selected instead. In addition, while only one power point is calibrated by measurement in the described embodiments, multiple power points can be calibrated in this way. 
     Power meter  216  of test controller  202  measures the power level of RF signal  214  (step  306 ). Adjustment circuit  220  calibrates the selected power point of DUT  204  by adjusting the calibration value stored in EEPROM  208  of DUT  204  for the power point (step  308 ). Steps  306  and  308  are repeated until the received power level of RF signal  214  transmitted by DUT  204  falls within the predetermined calibration range for the power point (step  310 ). 
     Calibration circuit  218  then calibrates the remaining power points of DUT  204  by calculation, without measurement of RF signal  214 . In particular, offset circuit  224  selects one of the remaining power points (step  312 ), adds the characteristic curve offset for that power point (stored in memory  222 ) to the calibration value of the previous power point (step  314 ), and replaces the calibration value in EEPROM  208  of DUT  204  with the result (step  316 ). For example, offset circuit  224  generates the calibration values shown in Table 2 above. 
     Process  300  then calculates the calibration value for the next power point in the channel in a similar manner (returning to step  312 ). When no power points remain in the selected channel (step  318 ), calibration process  300  is done (step  320 ). 
     Embodiments of the invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps of the invention can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output. The invention can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits). 
     A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.