Abstract:
Audible noise related to power state transitions of an information handling system processing component, such as the central processing unit, is reduced by randomizing the time between power state transitions. Random power state transitions are managed by an operating system module that tracks the transitions and selects random times for subsequent transitions within a predetermined time range. Alternatively, an arbitrating circuit intercepts power state transition commands and arbitrates their communication at random times. Random power state transitions reduces audible noise by spreading the frequency of the noise-causing power transition events over a wider band.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates in general to the field of information handling system audible noise, and more particularly to a system and method for reduction of information handling system audible noise related to power state transitions.  
         [0003]     2. Description of the Related Art  
         [0004]     As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.  
         [0005]     As information handling systems have grown in number, the cumulative power consumed by individual systems has become a growing concern. Industry and environmental groups have worked to decrease power consumption by generating and using a number of power conservation steps, such as automated power downs of systems and displays after periods of nonuse. Power conservation initiatives have naturally focused on information handling system components that consume greater amounts of power and especially on components having operational settings with variable power consumption. For example, a common power conservation technique is to throttle the central processing unit (CPU) to a variety of power saving states. The CPU is typically capable of transitioning dynamically between a fully active state and one or more different “sleep” states in a manner that is generally seamless to the user of the system. Throttling of a CPU between a variety of power saving states is particularly attractive with portable information handling systems when operating on an internal battery power source. When a portable system detects an idle state, throttling of the CPU is accomplished with minimal impact on the user of the system, thus increasing the time of the battery life between recharges.  
         [0006]     One difficulty that arises from the frequent transition between various CPU power states is that each transition tends to generate audible noise due to the peso-electric effect that accompanies changes in power applied to the CPU. The peso-electric effect results when sudden changes to CPU core voltages change the linear dimensions of ceramic capacitors used to decouple power rails. Changes in the linear dimensions of capacitors translates into board vibrations which are sometimes perceived by a user as a high-pitched audible noise. Typically, transitions between CPU power states occur at regular intervals, usually at 1 mS intervals, so that harmonics from these transitions produce a squealing noise that is annoying to users and sometimes perceived by users as a failing system. One way to minimize the audible noise is to replace the ceramic capacitors with POSCAPS that do not experience the peso-electric effect. However, POSCAPS are typically five times as expensive as ceramic capacitors and a typical CPU power regulator uses four to six of these capacitors. Other alternatives to reduce noise include mechanical modifications to the information handling system housing to reduce noise effects and masking entry into power saving states until a fixed timer expires, however, these techniques generally have an inadequate impact on the noise.  
       SUMMARY OF THE INVENTION  
       [0007]     Therefore a need has arisen for a system and method which effectively reduces noise associated with information handling system power state transitions.  
         [0008]     In accordance with the present invention, a system and method are provided which substantially reduce the disadvantages and problems associated with previous methods and systems for reducing noise associated with information handling system power state transitions. Power state transitions of an information handling system processing component are performed at randomized times to reduce audible noise associated with the power state transitions.  
         [0009]     More specifically, an information handling system central processing unit receives power at plural states provided by a power manager, such as software, firmware and hardware components distributed through the operating system and chipset to reduce power applied in accordance with processing demands. The power manager transitions between the plural power states at a regular periodic interval, such as 1 mS resulting in a 1 KHz cycle of audible noise generated by power rails that provide the power at the variable power states. An audible noise reduction module randomizes the power timing of the power state transitions within a predetermined time period, such as 0.8 to 2 mS, so that audible noise is reduced by spreading the audible noise across a wider frequency spectrum. In one embodiment, the audible noise reduction module is a software module associated with the operating system that randomizes power transition requests sent by the operating system. In an alternative embodiment, audible noise reduction module is an arbitration circuit that selectively arbitrates communication of power transition commands from the chipset of the information handling system to achieve increased randomization of the power transition commands.  
         [0010]     The present invention provides a number of important technical advantages. One example of an important technical advantage is that audible noise associated with information handling system power state transitions is reduced with minimal impact on system performance. Audible noise is reduced by expanding the bounds of the timing of the power state transitions, such as a range of 0.8 to 2 mS instead of the typical 1 mS value, to spread the spectrum of noise over a wider frequency band as opposed to the typical 1 KHz frequency. Increasing the bounds of the timing of power state transitions has some minimal impact on battery life, however the impact is minimal, such as a decrease of ten minutes of life for a five hour battery in one embodiment. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.  
         [0012]      FIG. 1  depicts a block diagram of an information handling system having software and hardware audible noise reduction modules;  
         [0013]      FIG. 2  depicts a flow diagram of a process for randomizing an information handling system processing component&#39;s power state transitions; and  
         [0014]      FIG. 3  depicts a circuit diagram of an arbitrator module that selectively communicates power state transition commands. 
     
    
     DETAILED DESCRIPTION  
       [0015]     Randomization of power state transitions of an information handling system processing component reduces audible noise related to the power state transitions by spreading the frequency of the noise over an increased spectrum. For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.  
         [0016]     Referring now to  FIG. 1 , a block diagram depicts an information handling system  10  having a software audible noise reduction module  12  and a hardware audible noise reduction module  14 . Information handling system  10  processes information at a hardware layer  16 , an operating system layer  18  and an application layer  20 . Hardware layer  16  includes plural processing components, such as a central processing unit (CPU)  22  and a chipset  24 . Operating system layer  18  includes an operating system  26  that coordinates the operation of the hardware components to perform tasks for applications running in application layer  20 . A power manager  28  associated with operating system  26  monitors the activity level of central processing unit  22  and, at regular periodic intervals such as every millisecond, power manager  28  adjusts the power state of central processing unit  22 , thus altering the power communicated across power rail  30 . Power manager  28  includes firmware and software instructions running in operating system  26  and on chipset  24  which adjusts the power state of central processing unit  22  in accordance with the processing demands of applications in use on information handling system  10 , with more processing intensive applications consuming greater power and idle use consuming reduced power. The one millisecond (1 mS) power state adjustment interval generates a 1 KHz audible noise from power rail  30  as capacitors associated with power rails  30  adjust to changes in power consumption.  
         [0017]     The audible noise output by power rail  30  is dampened with either the software audible noise reduction module  12  or the hardware audible noise reduction module  14  by expanding the time range over which power state transitions occur, such as a range of 0.8 to 2 mS instead of a regular 1 mS interval. Audible noise is reduced as the spectrum of noise from power rail  30  is spread over a wider frequency band. The software audible noise reduction module  12  operates as module associated with operating system  26  that sets random times for operating system  26  to allow power state transitions by power manager  28 . Referring now to  FIG. 2 , a flow diagram depicts one embodiment of a process for audible noise reduction module  12  to randomize an information handling system&#39;s processing component&#39;s power state transitions. The process begins at step  32  by tracking the time of entry into a power state, such as the value in a timer maintained by audible noise reduction module  12 . At step  34  a random timer value is determined for the next power state transition to occur, such as value within a range of 0.8 to 2 mS from the last power state transition. In one embodiment, the random time value is compared against the last time value to ensure that the power transition times will have adequate time spreads. In an alternative embodiment, experimentation is use to determine time values having greater noise reduction, such as based on the harmonics of the noise within the information handling system. At step  36 , the power state transition is performed at the random timer value and the process returns to step  32  to track the time of entry into the power state.  
         [0018]     Referring now to  FIG. 3 , a circuit diagram depicts an arbitrator module  38  that selectively communicates power state transition commands for audible noise reduction module  14 . A flip flop arbitrator  40  selectively communicates C 4  power saving request inputs  42  from chipset  24 , called CH3_DRRSLPVR, to the power regulator for CPU  22 . Flip flop arbitrator  40  only allows power transition requests to propagate from input  42  to output  44  if the request arrives in an “allowed time window” set by a random allowed time window circuit  46 . The duration of an allowed time window is randomly set by the duty cycle R 26  and C 6  of circuit  46  using the switching node LX of the power regulator as the gating signal since the regulator switching frequency is random with respect to the generation of power transition commands at input  42 . If a power transition request is denied by flip flop arbitrator  40  as having arrived outside of the allowed time, the power transition request may still be communicated by an extended allowed time window circuit  48  if the request is asserted for a long enough time to allow capacitor C 5  to charge through resistor R 23 . This allows for delayed entry into a power saving state to ensure that power savings are still achieved under appropriate circumstances. The duty cycle and therefore probability of allowing a request to occur is set by selecting the R and C values.  
         [0019]     Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.