Abstract:
A guard ring structure having a semiconductor substrate with a circuit region encircled by a first ring and a second ring. At least one of the first and second ring includes: a plurality of separated doping regions formed in various top portions of the semiconductor substrate, providing P-N junction or N-P junction on bottom of the plurality of separated doping regions; and an interconnect element formed over the semiconductor substrate, covering at least portion of the plurality of separated doping regions.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a Continuation of pending U.S. patent application Ser. No. 14/020,367, filed on Sep. 6, 2013, which claims the benefit of U.S. Provisional Application No. 61/698,443 filed Sep. 7, 2012, the entireties of which are incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to integrated circuit (IC) devices, and in particularly, to a guard ring structure for an IC device and a method for forming the same. 
         [0004]    2. Description of the Related Art 
         [0005]    In a semiconductor process, a plurality of dies, each containing integrated circuits (ICs), are fabricated on a semiconductor wafer at one time. Advances in semiconductor processing technologies, such as high-resolution photolithography and anisotropic plasma etching, have dramatically reduced the feature sizes of formed semiconductor devices in the integrated circuit and increased the device packing density. Other process technologies, such as die scribing for separating dies within a wafer and fuse blowing for improving the yield of circuit elements in the ICs, however, induce lateral stresses which spread along boundaries of the die. The lateral stresses may further progress into a core circuitry of the die, thus reducing yield and performance thereof. In addition, oxidation of the ICs in the die induced by environment moisture also reduces yield and performance thereof. 
         [0006]    Therefore, a guard ring structure is needed to be formed around a semiconductor die for the purposes of moisture isolation and structural reinforcement of the ICs therein. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    An exemplary guard ring structure comprises a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively comprises a plurality of separated first doping regions formed in a top portion of the semiconductor substrate, having a second dopant type opposite to the first dopant type; and an interconnect element formed over the semiconductor substrate, covering the first doping regions. 
         [0008]    Another exemplary guard ring structure comprises a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively comprises: a first doping region embedded in a portion of the semiconductor substrate, having a second dopant type opposite to the first dopant type; and an interconnect element formed over the semiconductor substrate, covering the first doping region. 
         [0009]    An exemplary method for forming a guard ring structure comprises: providing a semiconductor substrate having a first doping region formed over a top portion thereof, wherein the semiconductor substrate has a first dopant type and the first doping region has the first dopant type or a second dopant type opposite to the first dopant type; forming a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers comprises a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions and extending along a second direction perpendicular to the first direction; performing an etching process to the first doping region using the patterned photoresist layers as an etching mask, removing the first doping region not covered by the patterned photoresist layers and forming a plurality of patterned first doping regions, wherein each of the patterned first doping regions comprises a plurality of parallel strip portions extending along the first direction and a plurality of bridge portions formed between the parallel strip portions and extending along the second direction perpendicular to the first direction; removing the patterned photoresist layers; forming an isolation region between and adjacent to the patterned first doping regions; and forming a plurality of interconnect elements over the semiconductor substrate, respectively covering one of the patterned first doping regions thereunder. 
         [0010]    Another exemplary method for forming a guard ring structure comprises: providing a semiconductor substrate having a first doping region formed over a top portion thereof, wherein the semiconductor substrate has a first dopant type and the first doping region has the first dopant type or a second dopant type opposite to the first dopant type; forming a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers comprises a plurality of parallel strip portions extending along a first direction and a plurality of arm portions extending from opposite sides of each of the parallel strip portions along a second direction perpendicular to the first direction; performing an etching process to the first doping region using the patterned photoresist layers as an etching mask, removing the first doping region not covered by the patterned photoresist layers and forming a plurality of patterned first doping regions, wherein each of the patterned first doping regions comprises a plurality of parallel strip portions extending along the first direction and a plurality of arm portions formed between the parallel strip portions and extending along the second direction perpendicular to the first direction; removing the patterned photoresist layers; forming an isolation region between and adjacent to the patterned first doping regions; and forming a plurality of interconnect elements over the semiconductor substrate, respectively covering one of the patterned first doping regions thereunder. 
         [0011]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0013]      FIG. 1  is schematic top view of an integrated circuit die according to an embodiment of the invention; 
           [0014]      FIG. 2  is a schematic cross section along line  2 - 2  of integrated circuit die shown in  FIG. 1 , showing a guard ring structure according to an embodiment of the invention; 
           [0015]      FIG. 3  is a schematic cross section showing a guard ring structure according to another embodiment of the invention; 
           [0016]      FIG. 4  is a schematic cross section showing a guard ring structure according to yet another embodiment of the invention; 
           [0017]      FIG. 5  is a schematic cross section showing a guard ring structure according to another embodiment of the invention; 
           [0018]      FIG. 6  is a schematic top view of a guard ring structure according to an embodiment of the invention; 
           [0019]      FIGS. 7-9, and 11-12  are schematic top views showing a method for fabricating a guard ring structure according to an embodiment of the invention. 
           [0020]      FIG. 10  is a perspective view showing a region  400  shown in  FIG. 9 . 
           [0021]      FIG. 13  is a schematic top view of a guard ring structure according to another embodiment of the invention. 
           [0022]      FIGS. 14-16, and 18-19  are schematic top views showing a method for fabricating a guard ring structure according to another embodiment of the invention. 
           [0023]      FIG. 17  is a perspective view showing a region  500  shown in  FIG. 16 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0025]      FIG. 1  is a schematic top view of an exemplary integrated circuit (IC) die  10  having a circuit region  12  encircled by a guard ring structure comprising two rings  14  and  16  for moisture isolation and structural reinforcement of the integrated circuits (ICs, not shown) therein. As shown in  FIG. 1 , the circuit region  12  of the IC die  10  is encircled by the guard ring structure comprising an inner ring  14  relatively close to the circuit region  12  and an outer ring  16  relatively close to an edge of the IC die  10 . 
         [0026]      FIG. 2  is a schematic cross section along line  2 - 2  of the IC die  10  shown in  FIG. 1 , showing the rings  14  and  16  of the guard ring structure. The guard ring structure of the IC die  10  shown in  FIG. 2  is a comparative embodiment for describing an undesired substrate noise coupling issue that may propagate along the guard ring structure found by the inventors, and does not limit the scope of the present application. 
         [0027]    As shown in  FIG. 2 , the rings  14  and  16  are defined in and over different portions of a semiconductor substrate  100 , respectively comprise a well region  102  embedded in the semiconductor substrate  100 , a doping region  106  formed in a portion of the semiconductor substrate  100  overlying the well region  102 , and an interconnect element  200  formed over the doping region  106 . The well region  102  is a doping region blanketly embedded in the semiconductor substrate  100 . In addition, a plurality of isolation regions  104  such as shallow trench isolation (STI) regions is formed over portions of the semiconductor substrate  100  between and adjacent to the doping regions  106  to isolate thereof from each other. 
         [0028]    In one embodiment, the semiconductor substrate  100  can be an intrinsic substrate such as a bulk silicon substrate and is provided with a first dopant type such as p-type. At this time, the well region  102  can be, for example, a doping region of the first dopant type and has a resistivity lower than that of the semiconductor substrate  100 . Also, the doping region  106  can be, for example, a doping region of the first dopant type, having a resistivity lower than that of the well region  102 . 
         [0029]    An interconnect element  200  is substantially located over the doping region  106  and may comprise a plurality of dielectric layers  110  sequentially stacked over the semiconductor substrate  100 , having a plurality of conductive vias  120  and conductive lines  130  alternately formed in one of the dielectric layers  110 . A metallic-silicide region (not shown) may be provided at the interface between the doping region  106  and the interconnect element  200 . In one embodiment, the conductive vias  120  and the conductive lines  130  in the interconnect element  200  may comprise conductive materials such as copper or aluminum, such that the rings  14  and  16  may become a good conductor to couple substrate noise  140  from the electrical devices such as clock digital logic circuits formed in a portion (not shown) of the circuit region  12  (see  FIG. 1 ), and the substrate noise  140  coupled to the rings  14  and  16  may be thus delivered along, for example, the interconnect element  200  of the rings  14  and  16  and may be transmitted to other circuit devices such as analog circuits formed in other portions (not shown) of the circuit region  12  (see  FIG. 1 ), thereby affecting the overall reliability of IC die  10 . 
         [0030]    Therefore,  FIG. 3  is a cross section of exemplary rings  14 ′ and  16 ′ and can be applied to replace the rings  14  and  16  of the guard ring structure of the IC die  10  shown in  FIGS. 1-2  for reducing or eliminating the above described substrate noise coupling issue. For the purpose of simplicity, same reference numbers in  FIG. 3  represent the same elements shown in  FIGS. 1-2 , and only differences between the rings  14 ,  16 ,  14 ′ and  16 ′ are discussed as follows. 
         [0031]    As shown in  FIG. 3 , the rings  14 ′ and  16 ′ are formed over various portions of the semiconductor substrate  100 , respectively, comprising a doping region  103  embedded in a portion of the semiconductor substrate  100 , a plurality of doping regions  106 ′ formed in various portions of the semiconductor substrate  100  overlying the doping region  103 , and an interconnect element  200  formed over the doping regions  106 ′. At this time, the doping region  103  is underlying the interconnect element  200  and is isolated from the adjacent doping region  103  by the well region  102  formed therebetween. In addition, a plurality of isolation regions  104  such as shallow trench isolation (STI) regions is also formed over various portions of the semiconductor substrate  100  and are between and adjacent to the doping regions  106 ′ to isolate the doping regions  106 ′ from each other. Similarly, a metallic-silicide region (not shown) may be provided at the interface between the doping regions  106 ′ and the interconnect element  200 . 
         [0032]    In one embodiment, the semiconductor substrate  100  can be, for example, a bulk silicon substrate and is provided with a first dopant type, for example, p-type. At this time, the well regions  102  can be, for example, a doping region of the first dopant type, having a resistivity lower than that of the semiconductor substrate  100 . The doping regions  103  can be, for example, a doping region of a second dopant type opposite to the first dopant type, such as n-type, having a resistivity lower than that of the semiconductor substrate  100 . The doping regions  106 ′ can be, for example, a doping region of the first dopant type, having a resistivity lower than that of the well region  102 . 
         [0033]    Due to formation of the doping region  103  of the dopant type opposite to that of the semiconductor substrate  100  and the doping regions  106  in each of the rings  14 ′ and  16 ′, a P-N junction diode may be formed at an interface between the semiconductor substrate  100  and the doping regions  103 , and a plurality of N-P junction diodes can be formed at an interface between the doping region  103  and the doping regions  106 ′, such that the substrate noises  140  shown in  FIG. 3  of a predetermined frequency not greater than 1 GHz can be greatly reduced or even rejected by the diodes, and/or the substrate noise  140  of a predetermined frequency greater than 1 GHz can also be suppressed by the diodes, thereby preventing transmission of the substrate noise by the interconnect element  200  therein. 
         [0034]    Moreover,  FIG. 4  is a schematic cross section of other exemplary rings  14 ″ and  16 ″ and can be applied to replace the rings  14  and  16  of the guard ring structure shown in IC die  10  shown in  FIGS. 1-2  for reducing or eliminating the above described substrate noise coupling issues. The rings  14 ″ and  16 ″ are modified from the rings  14 ′ and  16 ′ shown in  FIG. 3 . For the purpose of simplicity, same reference numbers in  FIG. 4  represent the same elements shown in  FIGS. 1-3 , and only differences between the rings  14 ,  16 ,  14 ′,  16 ′,  14 ″, and  16 ″ are discussed as follows. 
         [0035]    As shown in  FIG. 4 , the rings  14 ″ and  16 ″ are formed over various portions of the semiconductor substrate  100 , respectively, comprising a doping region  103  embedded in a portion of the semiconductor substrate  100 , a plurality of doping regions  106 ′ formed in various portions of the semiconductor substrate  100  overlying the doping region  103 , and an interconnect element  200  formed over the doping region  106 . At this time, the doping region  103  is underlying the interconnect element  200  and is isolated from the adjacent doping region  103  by the semiconductor substrate  100 . In this embodiment, the well regions  102  shown in  FIG. 3  are not formed in the semiconductor substrate  100 . Similarly, a metallic-silicide region (not shown) may be provided at the interface between the doping region  106 ′ and the interconnect element  200 . 
         [0036]    Due to formation of the doping regions  103  of the dopant type opposite to that of the semiconductor substrate  100  and the doping regions  106 ′, a P-N junction diode can be formed at an interface between the semiconductor substrate  100  and the doping region  103 , and a plurality of N-P junction diodes can be formed at an interface between the doping region  103  and the doping regions  106 ′, such that the substrate noise  140  shown in  FIG. 4  of a predetermined frequency not greater than 1 GHz can be greatly reduced or even rejected by the diodes, and/or the substrate noise  140  of a predetermined frequency greater than 1 GHz can also be suppressed by the diodes, thereby preventing transmission of the substrate noise by the interconnect element  200  therein. 
         [0037]    Furthermore,  FIG. 5  is a schematic cross section of other exemplary rings  14 ′″ and  16 ′″ and can be applied to replace the rings  14  and  16  of the guard ring structure shown in IC die  10  shown in  FIGS. 1-2  for reducing or eliminating the above described substrate noise coupling issues. The rings  14 ′″ and  16 ′″ are modified from the rings  14 ′ and  16 ′ shown in  FIG. 3 . For the purpose of simplicity, same reference numbers in  FIG. 5  represent the same elements shown in  FIGS. 1-3 , and only differences between the rings  14 ′,  16 ′,  14 ″, and  16 ″ are discussed as follows. 
         [0038]    As shown in  FIG. 5 , the rings  14 ′″ and  16 ′″ are formed over various portions of the semiconductor substrate  100 , respectively, comprising a plurality of doping regions  106 ″ formed in various portions of the semiconductor substrate  100 , and an interconnect element  200  formed over the doping regions  106 ″. At this time, the doping regions  106 ″ are underlying the interconnect structure  200  and are isolated from the adjacent doping region  106 ″ by the isolation regions  104 , and no other doping region or well region are formed underlying the doping regions  106 ″ and the isolation regions  104  of the seal ring structure in the semiconductor substrate  100 . Similarly, a metallic-silicide region (not shown) may be provided at the interface between the doping region  106 ″ and the interconnect element  200 . 
         [0039]    In one embodiment, the doping regions  106 ″ can be, for example, of a second dopant type such as n-type opposite to the first dopant type of the semiconductor substrate  100 , having a resistivity lower than that of the semiconductor substrate  100 . 
         [0040]    Due to formation of the doping regions  106 ″ having the dopant type opposite to that of the semiconductor substrate  100 , a plurality of P-N junction diodes can be formed at an interface between the semiconductor substrate  100  and the doping regions  106 ″, such that the substrate noise  140  shown in  FIG. 5  of a predetermined frequency not greater than 1 GHz can be greatly reduced or even rejected by the diodes, and/or the substrate noise  140  of a predetermined frequency greater than 1 GHz can also be suppressed by the diodes, thereby preventing transmission of the substrate noise by the interconnect element  200  therein. 
         [0041]      FIG. 6  is a schematic top view of the rings  14 ′,  16 ′,  14 ″,  16 ″,  14 ′″, and  16 ′ shown in  FIGS. 3-5 , and for the purpose of simplicity, the interconnect elements  200  are not shown in  FIG. 6 . In  FIG. 6 , the doping regions  106 ′/ 106 ″, respectively, comprise a plurality of parallel strip portions  106   a  extending over the semiconductor substrate  100  along a direction such as a Y direction in  FIG. 6 , and a plurality of bridge portions  106   b  extending between two adjacent strip portions  106   a  along a direction such as an X direction in  FIG. 6 . The strip portions  106   a  of the adjacent doping regions  106 ′/ 106 ″ are mainly isolated from each other by the isolation regions  104  formed adjacent thereto. 
         [0042]      FIGS. 7-9 and 11-12  are schematic top views showing an exemplary method for fabricating a guard ring structure as that shown in  FIGS. 3-5  having the doping regions  106 ′/ 106 ″, and  FIG. 10  is a perspective view showing a region  400  in  FIG. 9 . 
         [0043]    In  FIG. 7 , the semiconductor substrate  100  is provided with blanket doping regions  106 ′/ 106 ″ thereover. The doping regions  106 ′/ 106 ″ can be doped with either a dopant type which is the same as that of the semiconductor substrate  100  as shown in  FIGS. 3-4  or with a dopant type opposite to that of the semiconductor substrate  100  as shown in  FIG. 5 , and may overlie the other well regions (not shown) embedded in the semiconductor substrate  100 . 
         [0044]    Next, in  FIG. 8 , two patterned photoresist layers  300  are formed over various portions of the semiconductor substrate  100 . As shown in  FIG. 8 , each of the patterned photoresist layers  300  comprises a plurality of parallel strip portions  300   a  and a plurality bridge portions  300   b  formed between the strip portions  300   a . The bridge portions  300   b  shown in  FIG. 8  are aligned and respectively connected to two adjacent strip portions  300   a  adjacent thereto. 
         [0045]    Next, as shown in  FIG. 9 , a patterning process (not shown) such as an etching process is performed on the doping regions  106 ′/ 106 ″ exposed by the patterned photoresist layers  300  and using the patterned photoresist layers  300  as a mask layer. Therefore, the portions of the doping regions  106 ′/ 106 ″ exposed by the patterned photoresist layers  300  are removed and the semiconductor substrate  100  is exposed. Due to formations of the bridge portions  300   b  in the patterned photoresist layers  300 , collapsing of the long extending strip portions  300   a  of the patterned photoresist layers  300  formed over the semiconductor substrate  100  during the above patterning process of the doping regions  106 ′/ 106 ″ is prevented and the pattern accuracy of the formed doping regions  106 ′/ 106 ″ are ensured. 
         [0046]      FIG. 10  is a perspective view showing a region  400  shown in  FIG. 9 , and one of the formed doping regions  106 ′/ 106 ″ comprising two strip portions  106   a  and a bridge portion  106   b  connected thereto having the same pattern as that of the strip portions  300   a  and the bridge portion  300   b  of the patterned photoresist layers  300  formed thereabove. 
         [0047]    In  FIG. 11 , the patterned photoresist layers  300  are then removed and a plurality of patterned doping regions  106 ′/ 106 ″ is left over the semiconductor substrate  100 . Next, a dielectric material (not shown) is blanketly formed over the semiconductor substrate  100  and the patterned doping regions  106 ′/ 106 ″, and the portion of the dielectric material over the doping regions  106 ′/ 106 ″ are then removed by a planarization process (not shown), such as a chemical mechanical polishing process. Therefore, the patterned doping regions  106  are isolated by the isolation region  104  made of the dielectric material. As shown in  FIG. 9 , each of the patterned doping regions  106 ′/ 106 ″ may comprise a plurality of parallel strip regions  106   a  and a plurality of bridge portions  106   b  connecting to the strip portions  106   a  as shown in  FIG. 6 . 
         [0048]    Next, conventional interconnect fabrication can be performed to the structure shown in  FIG. 11 , thereby forming the interconnect elements  200  respectively overlying one of the patterned doping regions  106 ′/ 106 ″ and obtaining the guard ring structure having the schematic cross sections as shown in  FIGS. 3-5 . At this time, only the topmost dielectric layer  110  is shown in  FIG. 12 , for simplicity. 
         [0049]      FIG. 13  is another schematic top view of the rings  14 ′,  16 ′,  14 ″,  16 ″,  14 ′″, and  16 ′″ shown in  FIGS. 3-5 , and for the purpose of simplicity, the interconnect elements  200  are not shown in  FIG. 13 . In  FIG. 13 , the doping regions  106 ′/ 106 ″, respectively, comprise a plurality of parallel strip portions  106   a  extending over the semiconductor substrate  100  along a direction such as a Y direction in  FIG. 13 , and a plurality of arm portions  106   c  extending to opposite sides each of the strip portions  106   a  along a direction such as a X direction in  FIG. 13 . The strip portions  106   a  of the adjacent doping regions  106 ′/ 106 ″ are mainly isolated from each other by the isolation regions  104  formed adjacent thereto. 
         [0050]      FIGS. 14-16 and 18-19  are schematic diagrams showing an exemplary method for fabricating a guard ring structure as that shown in  FIGS. 3-5  having the doping regions  106 ′/ 106 ″, and  FIG. 17  is a perspective view showing a region  500  in  FIG. 16 . 
         [0051]    In  FIG. 14 , the semiconductor substrate  100  is provided with blanket doping regions  106 ′/ 106 ″ thereover. The doping regions  106 ′/ 106 ″ can be doped with either a dopant type which is the same as that of the semiconductor substrate  100  as shown in  FIGS. 3-4  or with a dopant type opposite to that of the semiconductor substrate  100  as shown in  FIG. 5 , and may overlie the other well regions (not shown) embedded in the semiconductor substrate  100 . 
         [0052]    Next, in  FIG. 15 , two patterned photoresist layers  300  are formed over various portions of the semiconductor substrate  100 . As shown in  FIG. 15 , each of the patterned photoresist layers  300  comprises a plurality of parallel strip portions  300   a  and a plurality arm portions  300   c  extend from opposite sides of each of the strip portions  300   a . The arm portions  300   c  extended from each of strip portions  300   a  may be not aligned and are isolated from the strip portion  300   a  and arm portions  300   c  adjacent thereto. 
         [0053]    Next, as shown in  FIG. 16 , a patterning process (not shown) such as an etching process is performed on the doping regions  106 ′/ 106 ″ exposed by the patterned photoresist layers  300  and using the patterned photoresist layers  300  as a mask layer. Therefore, the portions of the doping regions  106 ′/ 106 ″ exposed by the patterned photoresist layers  300  are removed and the semiconductor substrate  100  is exposed. Due to formations of the arm portions  300   c  in the patterned photoresist layers  300 , such that collapsing of the long extending strip portions  300   a  formed over the semiconductor substrate  100  during the sequential patterning process of the doping regions  106 ′/ 106 ″ is prevented and the pattern accuracy of the formed doping regions  106 ′/ 106 ″ are ensured. 
         [0054]      FIG. 17  is a schematic perspective view showing a region  500  shown in  FIG. 16 , and one of the formed doping regions  106 ′/ 106 ″ comprises a strip portion  106   a  and two arm portions  106   c  connected thereto having the same pattern as that of the strip portion  300   a  and the arm portions  300   c  of the patterned photoresist layers  300  formed thereabove. 
         [0055]    In  FIG. 18 , the patterned photoresist layers  300  are then removed and a plurality of patterned doping regions  106 ′/ 106 ″ is left over the semiconductor substrate  100 . Next, a dielectric material (not shown) is blanketly formed over the semiconductor substrate  100  and the patterned doping regions  106 ′/ 106 ″, and the portion of the dielectric material over the doping regions  106 ′/ 106 ″ are then removed by a planarization process (not shown), such as a chemical mechanical polishing process. Therefore, the patterned doping regions  106  are isolated by the isolation region  104  made of the dielectric material. As shown in  FIG. 18 , each of the patterned doping regions  106 ′/ 106 ″ may comprise a plurality of parallel strip regions  106   a  and a plurality of arm portions  106   c  extending from opposite side of each of the strip portions  106   a  as shown in  FIG. 13 . 
         [0056]    Next, conventional interconnect fabrication can be performed to the structure shown in  FIG. 18 , thereby forming the interconnect elements  200  respectively overlying one of the patterned doping regions  106 ′/ 106 ″ and obtaining the guard ring structure having the schematic cross sections as shown in  FIGS. 3-5 . At this time, only the topmost dielectric layer  110  is shown in  FIG. 19 , for simplicity. 
         [0057]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.