Abstract:
A method of modifying data of functional latches of a logic unit during scan chain testing thereof to verify a test case failure of a suspected cell comprises: (a) determining a test case failure in the logic unit through scan chain testing thereof; (b) suspending clocked operations of the logic unit; (c) during suspended clocked operations of the logic unit, performing the following steps: (i) reading logic states of the functional latches; and (ii) modifying the logic state of at least one of the functional latches based on the determined test case failure; (d) restarting clocked operations of the logic unit; and (e) reading logic states of the functional latches resulting from the modification to verify the test case failure of a suspected cell.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to scan chain testing of electrical systems, in general, and more particularly, to a method and system of modifying data in functional latches of a logic unit during scan chain testing thereof to verify a test case failure of a suspected cell.  
         [0002]     Today&#39;s electrical systems are generally embedded in very large scale integrated (VLSI) circuits which contain hundreds of thousands if not millions of electrical cells. Usually, these cells are grouped into functional units which may include both combinational logic and sequential logic comprised of clocked memory elements referred to as functional latches. After fabrication, each VLSI circuit is tested to check the functionality of its logic circuits and the interconnections thereof. In order to expedite this process, the VLSI circuits are fabricated with test circuits, which may be in the form of JTAG scan chains, for example. JTAG scan chain circuits are constructed and operated by a test access process (TAP) controller in accordance with the IEEE standard 1149.1.  
         [0003]     Typically, the latches of a functional unit within a VLSI circuit are interfaced to corresponding scan latches in a boundary scan chain as illustrated by way of example in the block diagram schematic of  FIG. 1 . More specifically, scan latches SL 1 , . . . , SLN of a test scan chain are controlled by the TAP controller  10  to test the functional logic unit  12  shown within the dashed lines. Each scan latch SL 1 , . . . , SLN is coupled to a corresponding functional latch FL 1 , . . . , FLN in unit  12  by signal lines S 1 , . . . , SN, respectively. Test bit patterns are supplied by the TAP controller  10  to the scan latches SL 1 , . . . , SLN over a serial bus  14  which is daisy chained among the serial in (SI) and serial out (SO) ports of the latches SL 1 , . . . , SLN. The serial bus  14  begins and ends in the TAP controller  10  so that resultant test data may be read from the scan latches SL 1 , . . . , SLN to the TAP controller  10  thereover.  
         [0004]     In operation, the TAP controller  10  may be operated by standardized JTAG bus signals TCK, TDI, TDO, TRST, and TMS to control the flow of test and resultant bit pattern date over the serial bus  14  through control signals comprising Shift, Update and Write provided to the scan latches SL 1 , . . . , SLN over a parallel bus  16 . The functional logic unit  12  may be synchronized in operation by a master system clock (MCK), for example. Accordingly, the TAP controller  10  may introduce a test bit pattern to and read the resultant bit pattern from the functional latches FL 1 , . . . , FLN of unit  12  through the chain of scan latches SL 1 , . . . , SLN via respective signal lines S 1 , . . . , SN utilizing the clock MCK and control signals of bus  16 . From the resultant bit pattern, the TAP controller  10  in cooperation with a Debug unit  18  may determine a failure in the functionality and/or circuit interconnection of the unit  12 . However, as a result of the functional interdependency of the cells of the unit  12 , it may not be possible to verify the particular cell or cells that have failed without further complex processing.  
         [0005]     Accordingly, from this perspective, it is important and desirable to have a method and system of scan chain testing which may permit verifying the particular cell or cells causing the detected failure in a functional unit of a VLSI circuit. The present invention provides for such a method and system. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIG. 1  is a block diagram schematic of an exemplary system for scan chain testing of a functional logic unit suitable for embodying one aspect of the present invention.  
         [0007]      FIG. 2  is a block diagram schematic of an exemplary scan latch/functional latch combination suitable for use in the embodiment of  FIG. 1 .  
         [0008]      FIGS. 3A and 3B  are, in composite, a circuit schematic of an exemplary scan latch suitable for use in the embodiment of  FIGS. 1 and 2 .  
         [0009]      FIG. 4  is an exemplary flowchart of steps suitable for embodying another aspect of the present invention.  
         [0010]      FIG. 5  is a block diagram schematic of an exemplary interface between a processor and scan chain testing controller suitable for use in the embodiment of  FIG. 1 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]     An exemplary scan latch/functional latch combination circuit suitable for use in the embodiment of  FIG. 1  is shown in the block diagram schematic of  FIG. 2 . Referring to  FIG. 2 , a scan latch  20  which is exemplary of the latches in the scan chain SL 1 , . . . , SLN is coupled to its corresponding functional latch  22  in the functional logic unit  12  by way of two signal lines fb and in 1 . Under functional operation, data is provided to an input port  24  of the functional latch  22  over a signal line designated as “in”. A gate  26  may be provided in the signal line “in” to buffer the data signal. A functional clock FCK, derived from the master clock MCK (see  FIG. 1 ), having a rate of two-hundred megahertz (200 MHz), for example, controls the capturing of data at the port  24  by the latch  22 . In the present embodiment, the clock FCK may be a square wave which may be converted to a short pulsed waveform (PCK) by a circuit  28 . For example, the circuit  28  may produce a very short pulse on the order of seventy picoseconds (70 psec), for example, with each rising edge of the square waveform clock FCK to effect the clock PCK. Accordingly, at each pulse of PCK, data at port  24  is captured by the functional latch  22  and transferred to the output port  30 .  
         [0012]     As noted above, the scan latch  20  is also coupled to the serial bus  14  and to the control signals SHIFT, UPDATE and WRITE of the parallel bus  16 . In a controllable test mode, test data may be shifted into the scan latch  20  via the serial bus  14  using the SHIFT signal of bus  16 . The test data of scan latch  20  may be written to the signal lines fb and in 1  by the TAP controller  10  by pulsing the WRITE signal of bus  16 . The test data written to lines fb and in 1  dominate over the data at the input port  24  of functional latch  22  so that at the next pulse of PCK, the test data instead of the input data at port  24  is captured and transferred to the output  30  of the functional latch  22 . Thereafter, the functional latch  22  will perform its clocked operations within the functional logic unit  12  based on the initial test data received from the scan latch  20 .  
         [0013]     In an observable test mode, the scan latch  20  may observe the clocked or operational logic states of the functional latch  22  in response to the initial test data. In the observable test mode, the logic state of the functional latch  22  is provided to the scan latch  20  over signal lines fb and in 1 . When the TAP controller  10  desires to observe the state of the latch  22 , it pulses the UPDATE signal of bus  16  which causes the latch  20  to sample or capture the data on lines fb and in 1  and transfer the sampled data to the output scan port (SO) thereof. The sampled data may then be shifted to the TAP controller  10  over the serial bus  14  using the SHIFT signal of bus  16 .  
         [0014]      FIGS. 3A and 3B  are, in composite, a circuit schematic of an exemplary scan latch suitable for use in the embodiment of  FIGS. 1 and 2 . The exemplary scan latch circuit is comprised of NMOS and PMOS transistors as well as complementary metal oxide semiconductor (CMOS) transistor pairs. All of the CMOS pairs of the circuit are coupled between the supply buses V DD  and ground GND. Referring to  FIGS. 3A and 3B , the SHIFT signal is coupled through a CMOS pair  40  to produce the signal ns which is coupled through another CMOS pair  42  to produce the signal bshift. Similarly, the scan in (sin) signal is coupled through a CMOS pair  44  to produce the signal nsin which is coupled through another CMOS pair  46  to produce the signal bsin. The signal bsin is coupled through the parallel channels of a pair of NMOS and PMOS transistors,  48  and  50 , respectively, that are coupled source-to-source and drain-to-drain. The NMOS transistor  48  is gated by the signal bshift and the PMOS transistor  50  is gated by the complementary signal ns. The drain side of the transistor pair  48  and  50  effects the signal sd 0  which is coupled through a CMOS pair  52  to produce the signal sd 1  which is coupled through another CMOS pair  54  to produce the signal sd 2 . The signal sd 1  is also coupled to the gates of another CMOS pair  53 , the out put of which being coupled back to the signal sd 0 .  
         [0015]     The signal sd 0  is also coupled to ground GND through a pair of series connected NMOS transistors  56  and  58 , transistor  56  being gated by the signal in 1  and transistor  58  being gated by the signal UPDATE. Likewise, the signal sd 1  is also coupled to GND through a pair of series connected NMOS transistors  60  and  62 , transistor  60  being gated by the signal fb and transistor  62  being gated by the signal UPDATE. Signal sd 2  is coupled through the parallel channels of a pair of NMOS and PMOS transistors,  64  and  66 , respectively, that are coupled source-to-source and drain-to-drain. The NMOS transistor  64  is gated by the signal ns and the PMOS transistor  66  is gated by the complementary signal bshift. The drain side of the transistor pair  64  and  66  effects the signal nsout which is coupled through a CMOS pair  68  to produce the scan out signal sout. In addition, the signal nsout is coupled to V DD  through a PMOS transistor which is gated by signal sout, and is also coupled to GND through a series connected pair of NMOS transistors  72  and  74 , the transistor  72  being gated by the signal sout and the transistor  74  being gated by bshift.  
         [0016]     The foregoing part of the scan latch circuit of  FIGS. 3A and 3B  permits scanning in of a test date pattern. For example, test date presented to the scan input port sin is shifted to the center section as signals sd 0  and sd 1  via transistor pair  48 ,  50  when SHIFT changes state, and then, shifted to the scan output port sout via transistor pair  64 ,  66  when SHIFT changes back to its static state. In this manner, serial test data may be shifted through the scan latches of the chain until all of the scan latches have the proper test data stored as sd 0  and sd 1 . The test data stored in the latches may be written to their corresponding functional latches over signal lines fb and in 1  using the scan latch circuitry which will now be described.  
         [0017]     Referring to  FIGS. 3A and 3B  again, the signal lines fb and in 1  are coupled to GND through respective pairs of NMOS transistors  80 ,  82  and  84 ,  86 . The transistors  84  and  80  are gated by the signals sd 0  and sd 1 , respectively, and the transistors  82  and  86  are both gated by the WRITE signal. Thus, the test data stored in the scan latch  20  as sd 0  and sd 1  may be transferred to the signal lines in 1  and fb coupled to the functional latch  22  when the WRITE signal changes state. Thereafter, the test data over signal lines fb and in 1  may be captured by the functional latch  22  in the next clock cycle.  
         [0018]     In addition, with the WRITE signal in the dormant state, the logic states of signal lines fb and in 1  are controlled by the logic state of the functional latch  22  and may be sampled (observed) by the scan latch  20 . More specifically, when the signal UPDATE is pulsed, the logic states of lines in 1  and fb are transferred to signals sd 0  and sd 1  via transistors pairs  56 ,  58  and  60 ,  62 , respectively. The signals sd 0  and sd 1  control the logic state of sd 2  which is transferred to the scan output port via transistor pair  64 ,  66  and CMOS pair  68 . The sampled or observed resultant data from the functional latch  22  may be shifted serially back to the TAP controller  10  in the same manner as described above for scanning in data to the scan latches. The TAP controller  10  may analyze the response data to determine if a failure or failures have occurred.  
         [0019]     As noted above, while the TAP controller  10  may determine a failure in the logic unit  12  based on the observed resultant data, it is not capable without complex processing to verify the exact cell or cells in which the failure occurs. The present inventive methodology permits a test operator through use of a JTAG processor  100 , which may be a personal computer (PC) or a workstation, for example, to isolate a region in the logic unit  12  and verify the failed cell by exercising the TAP controller  10  using standard JTAG test bus signals comprising TCK, TDI, TDO, TRST, TMS as shown in the block diagram of  FIG. 5 . The TAP controller  10  may be exercised through a sequence of steps as shown in the exemplary flowchart of  FIG. 4 .  
         [0020]     For example, during a test operation of the functional logic unit  12 , the captured logic states of the functional latches of the unit  12  may be read into the TAP controller  10  from the scan latches via serial bus  14  as described supra and transferred therefrom to the JTAG processor  100  over TDO, for example. In the JTAG processor  100 , it may be determined from the sampled logic states of the functional latches if a failure has occurred in the logic unit  12 . If a failure is detected, then an operator may initiate steps via the JTAG processor  100  in accordance with the present invention to verify the failed cell in unit  12 . Referring to the exemplary flowchart of  FIG. 4 , the dashed line  102  separates the method steps between the JTAG processor  100  and the TAP controller  10  for the present embodiment. For example, those steps to left and right of the dashed line  102  may be carried out in the JTAG processor  100  and TAP controller  10 , respectively. The exemplary flowchart of  FIG. 4  will now be described in connection with the embodiment of  FIGS. 1 and 5 .  
         [0021]     When the JTAG processor  100  detects a failed condition during a test operation of logic unit  12 , it will start an analysis in step  104  which may include sending an instruction to the TAP controller  10  over signal line TDI, for example, to interrupt the clocked operation of the logic unit  12  and render it in a suspended state. The content of the instruction may include halting the clock FCK for a predetermined number of clock cycles. In the embodiment of  FIG. 1 , the clock FCK is derived from the clock MCK through a gate  106 , for example. The clock FCK may be halted by disabling gate  106  by a halt clock signal  108  generated by the Debug unit  18 . In the present embodiment, the clock MCK may be monitored by the Debug unit as a measure of time or number of cycles. Referring back to  FIG. 4 , the TAP controller  10  receives the instruction issued by processor  100  in step  110 . It may store the instruction in an instruction register  112  for decoding by a decoder unit  114 . In response to the instruction, the TAP controller  10  may program the Debug unit  18  in step  120  to halt the clock FCK for a predetermined number of MCK clock cycles. An example instruction may be as follows: “Halt FCK 1000 clock cycles after 10 signal transitions”.  
         [0022]     After the clocked operations of the logic unit  12  are suspended by halting the clock FCK, the TAP controller  10  may capture or sample the current logic states of the functional latches into their corresponding scan latches in step  122 . As noted above, this step  122  may be accomplished, in the present embodiment, by pulsing the Update signal of bus  16  (see  FIG. 1 ). Thereafter, in step  124 , the sampled logic states are read or scanned into the TAP controller  10  via the serial bus  14  by pulsing the Shift signal of bus  16  for a number of cycles commensurate with the number of scan latches in the chain. When all of the sampled data is read into the TAP controller  10 , step  124  controls the transfer of the sampled data to the JTAG processor  100  via line TDO, for example.  
         [0023]     Then, the JTAG processor  100  may be used to determine a failed cell from the sampled logic states of the functional latches in step  126 . If a failed cell can be determined, then the method ends; if not, then, in step  128 , the operator may modify the current pattern of the logic states using the processor  100  to assist in verifying a failed cell in logic unit  12 . One or more bits of the read in logic pattern may be changed to correct or amend (introduce) the logic state(s) of a suspected latch(es). Also, in step  128 , the JTAG processor  100  may be controlled to transfer the modified pattern of logic states to the TAP controller  10  via line TDI, for example. In step  130 , the TAP controller  10  receives the modified pattern from the processor  100 , and, in step  132 , shifts the pattern serially to the corresponding scan latches via the serial bus  14 . Also, in step  130 , the TAP controller  10  writes the modified pattern of logic states from the scan latches to the respective signal lines fb and in 1  of their corresponding functional latches to replace the logic states currently in the functional latches.  
         [0024]     Thereafter, the TAP controller  10  may restart the clock FCK in step  134  by removing the halt clock signal  108  from gate  106 , for example. When the clock FCK is restarted, the functional latches will capture the new logic states form lines fb and in 1  to assist in verifying a known or speculative failed cell or cells. Then, the logic unit  12  may perform in a clocked operation through a number of clock cycles as may be determined by the JTAG processor  100  and the steps of the method of  FIG. 4  repeated starting at step  104 . For example, if the processor  100  wants the logic unit  12  to perform through four clock cycles or signal transitions, it may issue an instruction to the controller  10  at step  10  to halt the clock FCK after four signal transitions. In response, the Debug unit  18  may count four clock cycles of the clock MCK and generate the halt clock signal  108 . Thereafter, the method steps may be repeated starting at step  110 .  
         [0025]     In the foregoing described manner, the present embodiment may perform “write-on-the-fly” test data transitions during testing or debug operations to inject verification or correction logic states into one or more desired functional latches to verify one or more known or speculative failed cells of the functional logic unit. Thus, the method works well as a debug tool to allow an operator via the JTAG processor to test a certain failure, if the failure can be limited to a suspected cell of the logic unit, for example, by suspending clocked operations, injecting a corrected logic state into the latch of the cell during suspended clocked operation, and then, restarting clocked operations and determining if the failure disappears or appears as the case may be.  
         [0026]     While the present invention has been presented herein above in connection with one or more embodiments, it is understood that all such embodiments were described merely by way of example with no intention of limiting the invention in any way. Accordingly, the present invention should not be limited by any of the presented embodiments, but rather construed in breadth and broad scope in accordance with the recitation of the claims appended hereto.