Abstract:
The invention encompasses several improved Turbo Codes Decoder method and apparatus to provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP codes. (1) Two pipelined Log-MAP decoders are used for iterative decoding of received data. (2) A Sliding Window of Block N data are used on the input Memory for pipeline operations. (3) The output block N data from the first decoder A are stored in the RAM memory A, and the second decoder B stores output data in the RAM memory B, such that in pipeline mode Decoder A decodes block N data from the RAM memory B while the Decoder B decodes block N data from the RAM memory A at the same clock cycle. (4) Log-MAP decoders are simpler to implement in ASIC and DSP codes with, only Adder circuits, and are low-power consumption. (5) Pipelined Log-MAP decoders architecture provides high speed data throughput, one output per clock cycle.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This is a continuation of patent application Ser. No. 09/681,093 filed Jan. 2, 2001. 
     
    
     
       BACKGROUND OF INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    This invention relates to Wireless Baseband Processor and Forward Error-Correction (FEC) Codes for 3G Wireless Mobile Communications; and more particularly, to a very high speed Turbo Codes Decoder using pipelined Log-MAP decoders architecture for 3G CDMA2000 and 3G WCDMA.  
           [0004]    2. Description of Prior Art  
           [0005]    Turbo Codes is based upon the classic forward error correction concepts that include the use of recursive systematic constituent Encoders (RSC) and Interleaver to reduce E b /N 0  for power-limited wireless applications such as digital 3G Wireless Mobile Communications.  
           [0006]    A Turbo Codes Decoder is an important baseband processor of the digital wireless communication Receiver, which was used to reconstruct the corrupted and noisy received data and to improve BER (10 −6 ) throughput. The FIG. 1. shows an example of a 3G Receiver with a Turbo Codes Decoder  13  which decodes data from the Demodulator  11  and De-mapping  12  modules, and sends decoded data to the MAC layer  14 .  
           [0007]    A most widely used FEC is the Viterbi Algorithm Decoder in both wired and wireless application. The drawback is that it would requires a long waiting for decisions until the whole sequence has been received. A delay of six time the memory of the received data is required for decoding. One of the more effective FEC, with higher complexity, a MAP algorithm used to decode received message has comprised the steps of very computational complex, requiring many multiplications and additions per bit to compute the posteriori probability. The major difficulty with the use of MAP algorithm has been the implementation in semiconductor ASIC devices, the complexity the multiplications and additions which will slow down the decoding process and reducing the throughput data rates. Furthermore, even under the best conditions, each multiplication will be used in the MAP algorithm, that would create a large circuits in the ASIC. The result is costly, and low performance in bit rates throughput.  
           [0008]    Recently introduced by the 3GPP organization a new class of error correction codes using parallel concatenated codes (PCCC) that include the use of the classic recursive systematic constituent Encoders (RSC) and Interleaver as shown in FIG. 3. offers great improvement. An example of the 3GPP Turbo Codes PCCC with 8-states and rate ⅓ is shown in FIG. 3., data enters the two systematic encoders  31   33  separated by an interleaver  32 . An output codeword consists of the source data bit followed by the output bits of the two encoders.  
           [0009]    Other prior work of error correction codes was done by Berrou et al. describing a parallel concatenated codes which is much complex encoding structure which is not suitable for portable wireless device. Another patent U.S. Pat. No. 6,023,783 by Divsalar and Pollara et al. describes a more improved encoding method than Berrou and mathematical concepts of parallel concatenated codes. However, patents by Berrou et al., Divsalar et al., and others only described the concept of parallel concatenated codes using mathematical equations which are good for research in deep space communications and other government projects but are not feasible, economical, and suitable for consumers&#39; portable wireless device. The encoding of data is simple and can be easily implemented with a few xor and flip-flop logic gates. But the decoding the Turbo Codes is much more difficult to implement in ASIC or software. The prior arts describe briefly the implementation of the Turbo Codes Decoder which are mostly for deep space communications and requires much more hardware, powers and costs.  
           [0010]    Another prior art example of a 16-states Superorthogonal Turbo Codes (SOTC) is shown in FIG. 2. It is identical to the previous 3GPP Turbo Codes PCCC except a Walsh Code Generator substitutes for the XOR binary adder. Data enters the two systematic encoders  21   23  separated by an interleaver  22 . An output codeword consists of the two Walsh Codes output of the two encoders.  
           [0011]    All the prior arts of Turbo Codes fail to provide a simpler and suitable method and architecture for a Turbo Codes Decoder as it is required and desired for 3G cellular phones and 3G personal communication devices including high speed data throughput, low power consumption, lower costs, limited bandwidth, and limited power transmitter in noisy environment.  
         SUMMARY OF INVENTION  
         [0012]    The present invention concentrates only on the Turbo Codes Decoder to implement a more efficient, practical and suitable architecture and method to achieve the requirements for 3G cellular phones and 3G personal communication devices including higher speed data throughput, lower power consumptions, lower costs, and suitable for implementation in ASIC or DSP codes. The present invention encompasses improved and simplified Turbo Codes Decoder method and apparatus to deliver higher speed and lower power especially for 3G applications. As shown in FIG. 5., and FIG. 4., our invention Turbo Codes Decoder utilizes two pipelined and serially concatenated SISO Log-MAP Decoders. The two decoders function in a pipelined scheme; while the first decoder is decoding data in the second-decoder-Memory, the second decoder performs decoding data in the first-decoder-Memory, which produces a decoded output every clock cycle in results. As shown in FIG. 6., our invention Turbo Codes Decoder utilizes a Sliding Window of Block N on the input buffer memory to decode per block N data for improvement processing efficiency. Accordingly, several objects and advantages of our Turbo Codes Decoder are:  
           [0013]    To deliver higher speed throughput and lower power consumption  
           [0014]    To utilize SISO Log-MAP decoder for faster decoding and simplified implementation in ASIC and DSP codes with the use of binary adders for computation.  
           [0015]    To perform re-iterative decoding of data back-and-forth between the two Log-MAP decoders in a pipelined scheme until a decision is made. In such pipelined scheme, a decoded output data is produced each clock cycle.  
           [0016]    To utilize a Sliding Window of Block N on the input buffer memory to decode per block N data for improvement pipeline processing efficiency  
           [0017]    To improve higher performance in term of symbol error probability and low BER (10 −6 )for 3G applications such as 3G W-CDMA, and 3G CDMA2000 operating at very high bit-rate up to 100 Mbps in a low power noisy environment.  
           [0018]    To utilize an simplified and improved architecture of SISO Log-MAP decoder including branch-metric (BM) calculations module, recursive state-metric (SM) forward/backward calculations module, Add-Compare-Select (ACS) circuit, Log-MAP posteriori probability calculations module, and output decision module.  
           [0019]    To reduce complexity of multiplier circuits in MAP algorithm by perform the entire MAP algorithm in Log Max approximation with the uses of binary adder circuits which are more suitable for ASIC and DSP codes implementation while still maintain a high level of performance output.  
           [0020]    To design an improve Log-MAP Decoder using high level design language (HDL) such as Verilog, system-C and VHDL which can be synthesized into custom ASIC and FPGA devices.  
           [0021]    To implement an improve Log-MAP Decoder in DSP (digital signal processor) using optimized high level language C, C++, or assembly language.  
           [0022]    Still further objects and advantages will become apparent to one skill in the art from a consideration of the ensuing descriptions and accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0023]    [0023]FIG. 1. is a typical 3G Receiver Functional Block Diagram which use Turbo Codes Decoder for error-correction. (Prior Art).  
         [0024]    [0024]FIG. 2. is an example of an 16-states Superorthogonal Turbo Code (SOTC) Encoder with Walsh code generator. (Prior Art).  
         [0025]    [0025]FIG. 3. is a block diagram of the 8-states 3GPP Parallel Concatenated Convolutional Codes. (Prior Art).  
         [0026]    [0026]FIG. 4. is the Turbo Codes Decoder System Block Diagram showing Log-MAP Decoders, Interleavers, Memory Buffers, and control logics.  
         [0027]    [0027]FIG. 5. is a Turbo Codes Decoder State Diagram.  
         [0028]    [0028]FIG. 6. is the Block N Sliding Window Diagram.  
         [0029]    [0029]FIG. 7. is a block diagram of the SISO Log-MAP Decoder showing Branch Metric module, State Metric module, Log-MAP module, am State and Branch Memory modules.  
         [0030]    [0030]FIG. 8 a.  is the 8-States Trellis Diagram of a SISO Log-MAP Decoder using for the 3GPP 8-state PCCC Turbo codes.  
         [0031]    [0031]FIG. 8 b.  is the 16-States Trellis Diagram of a SISO Log-MAP Decoder using for the superorthogonal Turbo codes (SOTC).  
         [0032]    [0032]FIG. 9. is a block diagram of the BRANCH METRIC COMPUTING module.  
         [0033]    [0033]FIG. 10 a.  is a block diagram of the Log-MAP computing for u=0.  
         [0034]    [0034]FIG. 10 b.  is a block diagram of the Log-MAP computing for u=1.  
         [0035]    [0035]FIG. 11. is a block diagram of the Log-MAP Compare &amp; Select I maximum logic for each state.  
         [0036]    [0036]FIG. 12. is a block diagram of the Soft Decode module.  
         [0037]    [0037]FIG. 13. is a block diagram of the Computation of Forward Recursion of State Metric module (FACS).  
         [0038]    [0038]FIG. 14. is a block diagram of the Computation of Backward Recursion of State Metric module (BACS).  
         [0039]    [0039]FIG. 15. showing State Metric Forward computing of Trellis state transitions.  
         [0040]    [0040]FIG. 16. showing State Metric Backward computing of Trellis state transitions.  
         [0041]    [0041]FIG. 17. is a block diagram of the State Machine operations of Log-MAP Decoder.  
         [0042]    [0042]FIG. 18. is a block diagram of the BM dual-port Memory Module.  
         [0043]    [0043]FIG. 19. is a block diagram of the SM dual-port Memory Module.  
         [0044]    [0044]FIG. 20. is a block diagram of the De-Interleaver dual-port RAM Memory Memory Module for interleaved input R 2 .  
         [0045]    [0045]FIG. 21. is a block diagram of the dual RAM Memory Module for input R 0 ,R 1 .  
         [0046]    [0046]FIG. 24. is a block diagram of the intrinsic feedback Adder of the Turbo Codes Decoder.  
         [0047]    [0047]FIG. 23. is a block diagram of the Iterative decoding feedback control. 
     
    
     DETAILED DESCRIPTION  
       [0048]    Turbo Codes Decoder  
         [0049]    An exhibition of a 3GPP 8-state Parallel Concatenated Convolutional Code (PCCC), with coding rate ⅓, constraint length K=4, using SISO Log-MAP Decoders is provided for simplicity in descriptions of the invention. As shown in FIG. 4, a Turbo Codes Decoder has two concatenated Log-MAP SISO Decoders A  42  and B  44  connected in a feedback loop with dual-port Memory  43  and dual-port Memory  45  in between. An input interleaver Memory  41 , shown in details FIG. 20, has one interleaver  201 , and dual-port RAM memory  202 . Input Memory blocks  48   49 , shown in details FIG. 21, have dual-port RAM memory  202 . A control logic module (CLSM)  47 , consists of various state-machines, which control all the operations of the Turbo Codes Decoder. The hard-decoder module  46  outputs the final decoded data. Signals R 2 , R 1 , R 0  are the received soft decision data from the system receiver. Signal XO 1 , and XO 2  are the output soft decision of the Log-MAP Decoders A  42  and B  44  respectively, which are stored in the buffer Memory  43  and Memory  45  module. Signal Z 2  and Z 1  are the output of the buffer Memory  43  and Memory  45  where the Z 2  is feed into Log-MAP decoder B  44 , and Z 1  is feedback into an Adder  231  then into Log-MAP decoder A  42  for iterative decoding.  
         [0050]    More particularly, the R 0  is the data bit corresponding to the the transmit data bit u, R 1  is the first parity bit corresponding to the output bit of the first RSC encoder, and R 2  is interleaved second parity bit corresponding to the output bit of the second RSC encoder as reference to FIG. 3.  
         [0051]    In accordance with the invention, the R 0  data is added to the feedback Z 1  data then feed into the decoder A, and R 1  is also fed into decoder A for decoding the first stage of decoding output X 01 . The Z 2  and R 2  are fed into decoder B for decoding the second stage of decoding output X 02 .  
         [0052]    In accordance with the invention, as shown in FIG. 6., the Turbo Codes Decoder utilizes a Sliding Window of Block N  61  on the input buffers  62  to decode one block N data at a time, the next block N of data is decoded after the previous block N is done in a circular wrap-around scheme for pipeline operations.  
         [0053]    In accordance with the invention, the Turbo Codes Decoder decodes an 8-state Parallel Concatenated Convolutional Code (PCCC), and also decodes a 16-states Superorthogonal Turbo Codes SOTC with different code rates.  
         [0054]    As shown in FIG. 4. the Turbo Codes Decoder functions effectively as follows:  
         [0055]    Received soft decision data (RXData[2:0]) are stored in three input buffers Memory  48   49   41  to produce R 0 , R 1 , and R 2  output data words. Each output data word R 0 , R 1 , R 2  contains a number of binary bits.  
         [0056]    A Sliding Window of Block N is imposed onto each input memory to produce R 0 , R 1 , and R 2  output data words.  
         [0057]    When a block of N input data is ready, the Turbo Decoder starts the Log-MAP Decoder A to decode the N input data based on the soft-values of R 0 , Z 1  and R 1 , then stores the outputs in the buffer Memory A.  
         [0058]    The Turbo Decoder also starts the Log-MAP Decoder B at the same time to decode the N input data based on the soft-values of R 2  and Z 2 , then store the outputs in the De-Interleaver Memory.  
         [0059]    The Turbo Decoder will do the iterative decoding for L number of times (L=1,2, . . . M). The Log-MAP Decoder A uses the sum of Z 1  and R 1  and R 0  as inputs. The Log-MAP Decoder B uses the data Z 2  and R 2  as inputs.  
         [0060]    When the iterative decoding sequences are done, the Turbo Decoder starts the hard-decision operations to compute and produce soft-decision outputs.  
         [0061]    SISO Log-MAP Decoder  
         [0062]    As shown in FIG. 7., an SISO Log-MAP Decoder 42   44  comprises of a Branch Metric (BM) computation module  71 , a State Metric (SM) computation module  72 , a Log-MAP computation module  73 , a BM Memory module  74 , a SM Memory module  75 , and a Control Logic State Machine module  76 . Soft-values inputs enter the Branch Metric (BM) computation module  71 , where Euclidean distance is calculated for each branch, the output branch metrics are stored in the BM Memory module  74 . The State Metric (SM) computation module  72  reads branch metrics from the BM Memory  74  and compute the state metric for each state, the output state-metrics are stored in the SM Memory module  75 . The Log-MAP computation module  73  reads both branch-metrics and state-metrics from BM memory  74  and SM memory  75  modules to compute the Log Maximum a Posteriori probability and produce soft-decision output. The Control Logic State-machine module  76  provides the overall operations of the decoding process.  
         [0063]    As shown in FIG. 7. and primary example of 3GPP Turbo Codes, the Log-MAP Decoder  42   44  functions effectively as follows:  
         [0064]    The Log-MAP Decoder  42   44  reads each soft-values (SD) data pair input, then computes branch-metric (BM) values for all paths in the Turbo Codes Trellis  80  as shown in FIG. 8 a.  (and Trellis  85  in  8   b .), then stores all BM data into BM Memory  74 . It repeats computing BM values for each input data until all N samples are calculated and stored in BM Memory  74 .  
         [0065]    The Log-MAP Decoder  42   44  reads BM values from BM Memory  74  and SM values from SM Memory  75 , and computes the forward state-metric (SM) for all states in the Trellis  80  as shown in FIG. 8 a.  (and Trellis  85  in  8   b .), then store all forward SM data into SM Memory  75 . It repeats computing forward SM values for each input data until all N samples are calculated and stored in SM Memory  75 .  
         [0066]    The Log-MAP Decoder  42   44  reads BM values from BM Memory  74  and SM values from SM Memory  75 , and computes the backward state-metric (SM) for all states in the Trellis  80  as shown in FIG. 8 a.  (and Trellis  85  in  8   b .), then store all backward SM data into the SM Memory  75 . It repeats computing backward SM values for each input data until all N samples are calculated and stored in SM Memory  75 .  
         [0067]    The Log-MAP Decoder  42   44  then computed Log-MAP posteriori probability for u=0 and u=1 using BM values and SM values from BM Memory  74  and SM Memory  75 . It repeats computing Log-MAP posteriori probability for each input data until all N samples are calculated. The Log-MAP Decoder then decodes data by making soft decision based on the posteriori probability for each stage and produce soft-decision output, until all N inputs are decoded.  
         [0068]    Branch Metric Computation module  
         [0069]    The Branch Metric (BM) computation module  71  computes the Euclidean distance for each branch in the 8-states Trellis  80  as shown in the FIG. 8 a.  based on the following equations:  
         Local Euclidean distances values= SD   0 * G   0 + SD   1 * G   1   
         [0070]    The SD 0  and SD 1  are soft-values input data, G 0  and G 1  are the expected input for each path in the Trellis  80 . G 0  and G 1  are coded as signed antipodal values, meaning that 0 corresponds to +1 and 1 corresponds to −1. Therefore, the local Euclidean distances for each path in the Trellis  80  are computed by the following equations:  
           M   1 = SD   0 + SD   1   
           M   2 =− M   1   
         M 3 =M 2   
         M 4 =M 1   
           M   5 =− SD   0 + SD   1   
           M   6 =− M   5   
         M 7 =M 6   
         M 8 =M 5   
         M 9 =M 6   
         M 10 =M 5   
         M 11 =M 5   
         M 12 =M 6   
         M 13 =M 2   
         M 14 =M 1   
         M 15 =M 1   
         M 16 =M 2   
         [0071]    As shown in FIG. 9., the Branch Metric Computing module comprise of one L-bit Adder  91 , one L-bit Subtracter  92 , and a 2′complemeter  93 . It computes the Euclidean distances for path M 1  and M 5 . Path M 2  is 2′complement of path M 1 . Path M 6  is 2′complement of M 5 . Path M 3  is the same path M 2 , path M 4  is the same as path M 1 , path M 7  is the same as path M 6 , path M 8  is the same as path M 5 , path M 9  is the same as path M 6 , path M 10  is the same as path M 5 , path M 11  is the same as path M 5 , path M 12  is the same as path M 6 , path M 13  is the same as path M 2 , path M 14  is the same as path M 1 , path M 15  is the same as path M 1 , and path M 16  is the same as path M 2 .  
         [0072]    State Metric Computing Module  
         [0073]    The State Metric Computing module  72  calculates the probability A(k) of each state transition in forward recursion and the probability B(k) in backward recursion. FIG. 13. shows the implementation of state-metric in forward recursion with Add-Compare-Select (ACS) logic, and FIG. 14. shows the implementation of state-metric in backward recursion with Add-Compare-Select (ACS) logic. The calculations are performed at each node in the Turbo Codes Trellis  80  (FIG. 8 a .) in both forward and backward recursion. The FIG. 15. shows the forward state transitions in the Turbo Codes Trellis  80  (FIG. 8 a .), and FIG. 16. show the backward state transitions in the Turbo Codes Trellis  80  (FIG. 8 a .). Each node in the Trellis  80  as shown in FIG. 8 a.  has two entering paths: one-path  84  and zero-path  83  from the two nodes in the previous stage.  
         [0074]    The ACS logic comprises of an Adder  132 , an Adder  134 , a Comparator  131 , and a Multiplexer  133 . In the forward recursion, the Adder  132  computes the sum of the branch metric and state metric in the one-path  84  from the state s(k−1) of previous stage (k−1). The Adder  134  computes the sum of the branch metric and state metric in the zero-path  83  from the state (k−1) of previous stage (k−1). The Comparator  131  compares the two sums and the Multiplexer  133  selects the larger sum for the state s (k) of current stage (k). In the backward recursion, the Adder  142  computes the sum of the branch metric and state metric in the one-path  84  from the state s(j+1) of previous stage (J+1). The Adder  144  computes the sum of the branch metric and state metric in the zero-path  83  from the state s(j+1) of previous stage (J+1). The Comparator  141  compares the two sums and the Multiplexer  143  selects the larger sum for the state s(j) of current stage (j).  
         [0075]    The Equations for the ACS are shown below:  
           A ( k )= MAX  [( bm   0 + sm   0 ( k− 1)), ( bm   1 + sm   1 ( k− 1)] 
           B ( j )= MAX  [( bm   0 + sm   0 ( j+ 1)), ( bm   1 + sm   1 ( j+ 1)] 
         [0076]    Time (k−1) is the previous stage of (k) in forward recursion as shown in FIG. 15., and time (j+1) is the previous stage of (j) in backward recursion as shown in FIG. 16.  
         [0077]    Log-MAP Computing Module  
         [0078]    The Log-MAP computing module calculates the posteriori probability for u=0 and u=1, for each path entering each state in the Turbo Codes Trellis  80  corresponding to u=0 and u=1 or referred as zero-path  83  and one-path  84 . The accumulated probabilities are compared and selected the u with larger probability. The soft-decision are made based on the final probability selected for each bit. FIG. 10 a.  shows the implementation for calculating the posteriori probability for u=0. FIG. 10 b.  shows the implementation for calculate the posteriori probability for u=1. FIG. 11. shows the implementation of compare-and-select the u with larger probability. FIG. 12. shows the implementation of the soft-decode compare logic to produce output bits based on the posteriori probability of u=0 and u=1. The equations for calculation the accumulated probabilities for each state and compare-and-select are shown below:  
         sum —   s   00 = sm   0   i+bm   1 + sm   0   j    
         sum —   s   01 = sm   3   i+bm   7 + sm   1   j    
         sum —   s   02 = sm   4   i+bm   9 + sm   2   j    
         sum —   s   03 = sm   7   i+bm   15 + sm   3   j    
         sum —   s   04 = sm   1   i+bm   4 + sm   4   j    
         sum —   s   05 = sm   2   i+bm   6 + sm   5   j    
         sum —   s   06 = sm   5   i+bm   12 + sm   6   j    
         sum —   s   07 = sm   6   i+bm   14 + sm   7   j    
         sum —   s   10 = sm   1   i+bm   3 + sm   0   j    
         sum —   s   11 = sm   2   i+bm   5 + sm   1   j    
         sum —   s   12 = sm   5   i+bm   11 + sm   2   j    
         sum —   s   13 = sm   6   i+bm   13 + sm   3   j    
         sum —   s   14 = sm   0   i+bm   2 + sm   4   j    
         sum —   s   15 = sm   3   i+bm   8 + sm   5   j    
         sum —   s   16 = sm   4   i+bm   10 + sm   6   j    
         sum —   s   17 = sm   7   i+bm   16 + sm   7   j    
           s   00 sum=MAX[sum —   s   00 ,  0 ] 
           s   01 sum=MAX[sum —   s   01 ,  s   00 sum] 
           s   02 sum=MAX[sum —   s   02 ,  s   01 sum] 
           s   03 sum=MAX[sum —   s   03 ,  s   02 sum] 
           s   04 sum=MAX[sum —   s   04 ,  s   03 sum] 
           s   05 sum=MAX[sum —   s   05 ,  s   04 sum] 
           s   06 sum=MAX[sum —   s   06 ,  s   05 sum] 
           s   07 sum=MAX[sum —   s   07 ,  s   06 sum] 
           s   10 sum=MAX[sum —   s   10 ,  0 ] 
           s   11 sum=MAX[sum —   s   11 ,  s   10 sum] 
           s   12 sum=MAX[sum —   s   12 ,  s   11 sum] 
           s   13 sum=MAX[sum —   s   13 ,  s   12 sum] 
           s   14 sum=MAX[sum —   s   14 ,  s   13 sum] 
           s   15 sum=MAX[sum —   s   15 ,  s   14 sum] 
           s   16 sum=MAX[sum —   s   16 ,  s   15 sum] 
           s   17 sum=MAX[sum —   s   17 ,  s   16 sum] 
         [0079]    Control Logics—State Machine (CLSM) Module  
         [0080]    As shown in FIG. 7. the Control Logics module controls the overall operations of the Log-MAP Decoder. The control logic state machine  171 , referred as CLSM, is shown in FIG. 17. The CLSM module  171  (FIG. 17.) operates effectively as the followings. Initially, it stays in IDLE state  172 . When the decoder is enable, the CLSM transitions to CALC-BM state  173 , it then starts the Branch Metric (BM) module operations and monitor for completion. When Branch Metric calculations are done, referred as bm-done the CLSM transitions to CALC-FWD-SM state  174 , it then tarts the State Metric module (SM) in forward recursion operation. When the forward SM state metric calculations are done, referred as fwd-sm, the CLSM transitions to CALC-BWD-SM state  175 , it then starts the State Metric module (SM) in backward recursion operations. When backward SM state metric calculations are done, referred as bwd-sm-done the CLSM transitions to CALC-Log-MAP state  176 , it then starts the Log-MAP computation module to calculate the maximum a posteriori probability to produce soft decode output. When Log-MAP calculations are done, referred as log-map-done, it transitions back to IDLE state  172 .  
         [0081]    BM Memory and SM Memory  
         [0082]    The Branch-Metric Memory  74  and the State-Metric Memory  75  are shown in FIG. 7. as the data storage components for BM module  71  and SM module  72 . The Branch Metric Memory module is a dual-port RAM contains M-bit of N memory locations as shown in FIG. 18. The State Metric Memory module is a dual-port RAM contains K-bit of N memory locations as shown in FIG. 19. Data can be written into one port while reading at the other port.  
         [0083]    Buffer Memory  
         [0084]    As shown in FIG. 4., the buffer Memory A  43  stores data for the first decoder A  42 , and buffer Memory B  45  stores data for the second decoder B  44 . In an iterative pipelined decoding, the decoder A  42  reads data from buffer memory B  45  and writes results data into buffer memory B  43 , the decoder B  44  reads data from buffer memory A  43  and write results into buffer memory B  45 .  
         [0085]    As shown in FIG. 20., the De-Interleaver memory  41  comprises of an De-Interleaver module  201  and a dual-port RAM  202  contains M-bit of N memory locations. The Interleaver is a Turbo code internal interleaver as defined by 3GPP standard ETSI TS 125 222 V3.2.1 (2000-05), or other source. The Interleaver permutes the address input port A for all write operations into dual-port RAM module. Reading data from output port B are done with normal address input.  
         [0086]    As shown in FIG. 21., the buffer memory  43   45  comprises of a dual-port RAM  212  contains M-bit of N memory locations.  
         [0087]    Turbo Codes Decoder Control Logics—State Machine (TDCLSM)  
         [0088]    As shown in FIG. 4. the Turbo Decoder Control Logics module  47 , referred as TDCLSM, controls the overall operations of the Turbo Codes Decoder. Log-MAP A  42  starts the operations of data in Memory B  45 . At the same time, Log-MAP B starts the operations in Memory A  43 . When Log-MAP A  42  and Log-MAP B  44  are done for a block N data, the TDCLSM  47  starts the iterative decoding for L number of times. When the iterative decoding sequences are done, the TDCLSM  47  transitions to HARD-DEC to generate the hard-decode outputs. Then the TDCLSM  47  transitions to start decoding another block of data.  
         [0089]    Iterative Decoding  
         [0090]    Turbo Codes decoder performs iterative decoding L times by feeding back the output Z 1  of the second Log-MAP decoder B into the first Log-MAP decoder A, before making decision for hard-decoding output. As shown in FIG. 23., the Counter  233  count the preset number L times.