Abstract:
In a semiconductor logic circuit, a plurality of gates are provided, each formed of a junction type field effect transistor. The junction type field effect transistor of one of the gates is directly coupled to the junction type field effect transistor of a succeeding gate. An element is provided for clamping an output voltage of the junction type field effect transistor of the one gate, which provides an input voltage for the junction type field effect transistor of the succeeding gate, to below about a forward voltage of a pn junction of the succeeding gate.

Description:
This is a continuation of application Ser. No. 790,945, filed Oct. 24, 1985. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor circuit apparatus formed of a direct coupled FET logic circuit (DCFL) by using a gate having a junction type field effect transistor (J-FET). 
     A DCFL requires only a small number of elements for forming a gate and thus is suitable for providing a large scale logic circuit. 
     FIG. 1 shows an example of a conventional DCFL. In this conventional DCFL, two inverters 11 and 21 are directly coupled. The inverters 11 and 21 consist of J-FETs 12 and 22 using GaAs semiconductors and resistors 13 and 23, respectively. With this arrangement, the OFF-resistance of the J-FET 12 is normally considerably higher than the resistance of the resistor 13 so that the high level of an output voltage of the J-FET 12, i.e., an input voltage to J-FET 22, is substantially the same as the voltage (VDD) of a drive power source (not shown). 
     When a ring oscillator is formed by a DCFL as described above and propagation delay time (τpd) per gate is measured, τpd is gradually increased in accordance with the increase in the voltage VDD as shown by the solid line in FIG. 2. In constrast to this, when Schottky barrier type field effect transistors (MES-FETs) are used in place of the J-FETs 12 and 22, τpd is kept constant even if the voltage VDD is increased, as shown by the dotted line in FIG. 2. 
     This is assumed to be caused by a carrier storage effect of a channel, or a substrate of the J-FET 22 is enhanced as the high level input voltage of the J-FET 22 which becomes higher than a forward voltage (Vf=1.0 V) at a pn junction. 
     Therefore, in a conventional example as mentioned above, when the voltage VDD is set to be, e.g., higher than 1.5 V, τpd as well as power consumption will be increased, resulting in a great disadvantage. 
     For this reason, the voltage VDD must be set in a range of, e.g., 1.0 to 1.4 V, and the setting condition of the voltage VDD becomes critical. In addition, in some J-FETs, the voltage VDD rapidly increases from the vicinity of 1.2 V, depending upon a condition of the substrate. In this case, the setting condition of the voltage VDD becomes more strict. In other words, only a small margin against variation in the voltage VDD is allowable, this resulting in difficult circuit design. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a semiconductor circuit apparatus of a simple circuit design, wherein the propagation delay time is not increased upon variation in voltage of a drive power source, and thus a margin for variation in the voltage of the drive power source is large. 
     In a semiconductor circuit apparatus according to the present invention, an output voltage of a J-FET of a preceding gate which serves as an input voltage to a J-FET of a succeeding gate is limited to below about a forward voltage of a pn junction, so that even if a voltage of a drive power source varies, a carrier storage effect does not conspicuously appear at a J-FET of the succeeding gate. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuit configuration of an example of a conventional semiconductor circuit apparatus; 
     FIG. 2 is a graph showing a propagation delay time of the conventional semiconductor circuit apparatus; and 
     FIGS. 3 and 4 show circuit configurations of semiconductor circuit apparatuses according to first and second embodiments of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Semiconductor circuit apparatuses according to first and second embodiments of the present invention, as applied to two-stage inverters, will be described with reference to FIGS. 3 and 4. 
     FIG. 3 shows the first embodiment of the present invention. The apparatus of the first embodiment can have substantially the same configuration and is connected to a potential V DD  (first voltage potential) as the conventional one shown in FIG. 1 except that gate terminals of J-FETs 12 and 22 in FIG. 3 are connected to a clamping power source (second voltage potential) (not shown) through Schottky barrier diodes (SBD) 14 and 24. 
     Although it varies a little depending upon the types of metal forming the Schottky barrier, a forward bias voltage Vf of the SBDs 14 and 24 is generally about 0.6 V. When a voltage higher than 0.6 V is applied in the forward direction, a current flows in the SBDs 14 and 24. 
     When a voltage (VGG) (second voltage potential) of a clamping power source is set to about 0.4 V, and input voltage to the J-FET 22 is maintained at about 1.0 V as long as the SBD 24 has a sufficient current capacity. In other words, when the voltage VDD is increased and the output voltage of the J-FET 12 almost exceeds 1.0 V, the current flows in the SBD 24 so that the output voltage of the J-FET 12, i.e., the input voltage to the J-FET 22, is controlled to be about 1.0 V. 
     As a result, even if the voltage VDD is increased, the input voltage to the J-FET 22 is controlled to below about Vf of the pn junction. Then, the carrier storage effect does not notably occur at the J-FET 22 and the propagation delay time τpd of the inverter 21 is not increased. 
     In the first embodiment, a gate terminal of the J-FET 12 is also connected to the clamping power source through the SBD 14. Therefore, even when the input voltage to the J-FET 12 almost exceeds 1.0 V, a current flows in the SBD 14 so that the input voltage is controlled to be about 1.0 V. As a result, the carrier storage effect does not notably occur at the J-FET 12, thereby preventing an increase in τpd of the inverter 11. 
     FIG. 1 shows a second embodiment of the present invention. The apparatus of the second embodiment can have substantially the same configuration as the first embodiment shown in FIG. 3, except that in FIG. 4, a clamping power source is not provided and SBDs 14 and 24 are connected between drain terminals and gate terminals of FETs 12 and 22, respectively. The low level of an input voltage to the J-FET 12 is set to 0.2 V, and Vf of the SBDs 14 and 24 is set to 0.7 V. 
     According to the second embodiment, even when the voltage VDD is increased and the output voltage of the J-FET 12 almost exceeds 0.9 V, a current flows in the SBD 14 so that the output voltage of the J-FET 12, i.e. the input voltage to the FET 22, is controlled to be 0.9 V. Then, the carrier storage effect does not notably occur at the J-FET 22 and the propagation delay time τpd of the inverter 21 is not increased. 
     In the second embodiment, the SBD 24 is connected between the drain and gate terminals of the J-FET 22. Therefore, even when the output voltage of the J-FET 22 almost exceeds 0.9 V, a current flows in the SBD 24 to control the output voltage to about 0.9 V. 
     The apparatus according to the second embodiment does not require a clamping power source and thus has a much simpler circuit design. However, the voltage Vf of SBDs 14 and 24 directly determines a logic amplitude, i.e., the difference between the high and low level output voltages. In order to increase the logic amplitude, it is preferable to set the voltage Vf of the SBDs 14 and 24 to be larger than the voltage Vf in the first embodiment, as has been described above. 
     Even if the voltage Vf of the SBDs 14 and 24 is positively increased, the high level output voltage of the J-FET 12 can be controlled to be about the voltage Vf of the pn junction by decreasing the low level input voltage of the J-FET 12 and simultaneously increasing the voltage VDD. Therefore, operation conditions can be determined without increasing τpd. 
     The high level of the output voltage of the J-FET 12, i.e. the input voltage to the J-FET 12, is controlled both in the first and second embodiments. However, a low level of these voltages is determined in accordance with a ratio of a resistance of the resistor 13 to an on resistance of the J-FET 12. Therefore, the low level can be determined independently of the high level. 
     In the first and second embodiments, the SBDs 24 and 14 are used as elements for clamping the output voltage of the J-FET 12 so as to allow high-speed operation of the J-FETs 12 and 22 using GaAs. Therefore, when a high-speed operation is not needed, junction diodes and the like can be used in place of the SBDs 24 and 14. 
     The resistors 13 and 23 as passive elements are used in the first and second embodiments as loads for the inverters 11 and 21. However, FETs or other devices as active elements can be used instead. 
     The first and second embodiments of the present invention are applied to double-stage inverters. However, the present invention can be applied to a gate other than an inverter. 
     As has been mentioned above, according to the semiconductor circuit apparatus of the present invention, the carrier storage effect does not occur significantly at a J-FET of a succeeding gate, even if the voltage of a drive power source varies. Therefore, the propagation delay time is not increased due to a variation in voltage of the drive power source. 
     Since the propagation delay time is not increased by a variation in voltage of the drive power source, a margin for the variation in voltage of the drive power source becomes large, resulting in simple circuit design. 
     Although various minor changes and modifications might be proposed by those skilled in the art, it will be understood that I wish to include within the claims of the patent warranted hereon all such changes and modifications as reasonably come within my contribution to the art.