Abstract:
In order to prevent interference of signals in a plurality of outputs from a current mirror circuit, the current mirror circuit comprises a current mirror input transistor Q 1  through which a constant current flows and a plurality of current mirror output transistors Q 7  and Q 8  which have control ends commonly connected to a control end of the current mirror input transistor Q 1 . The constant current is supplied from the plurality of current mirror output transistors Q 7  and Q 8  to a plurality of operating circuits. Further, at least one of the plurality of current mirror output transistors Q 7  and Q 8  is equipped with a low pass filter for removing a high-frequency component contained in a current output from the at least one of the plurality of current mirror output transistors Q 7  and Q 8.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The disclosure of Japanese Patent Application No. 2006-351118 including specification, claims, drawings and abstract, filed on Dec. 27, 2006 is incorporated herein by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a constant current circuit which includes an input path through which a constant current on an input side of the constant current circuit flows, and an output path through which a constant current on an output side of the constant current circuit corresponding to the constant current on the input side flows. 
         [0004]    2. Description of the Related Art 
         [0005]    Conventionally, a great number of various current mirror circuits have been used in a semiconductor integrated circuit. Here, some of the current mirror circuits often include, with respect to one current mirror input transistor, a plurality of current mirror output transistors which are connected on a common base to the current mirror input transistor. 
         [0006]    Such current mirror circuits are disclosed in Japanese Patent Publications JP 2006-33523, JP H10-97332, JP H07-121256, and other publications. 
         [0007]    When a signal is handled using a circuit having a plurality of outputs as described above, in some instances, problems such as interference or leakage of a signal at high frequencies will arise through a base line of a current mirror circuit. In particular, when a gain of a signal to be handled is high, when a MIX circuit is used, or when a signal to be handled is of high frequency, it is highly likely that the above-described problem of signal leakage will occur. Further, there may be cases where the occurrence of the above-described problem causes generation of unexpected oscillation depending on the amount of leakage or phase conditions. 
       SUMMARY OF THE INVENTION 
       [0008]    The present invention provides a constant current circuit comprising a current mirror input, transistor through which a constant current flows, and a plurality of current mirror output transistors. In the constant current circuit, at least one of the plurality of current mirror output transistors is equipped with a low-pass filter for eliminating a high frequency component contained in a current output from the at least one of the plurality of current mirror output transistors. 
         [0009]    Accordingly, provision of the low-pass filter can prevent the high frequency component in a circuit connected to an output of one current mirror circuit adversely affecting an output of another current mirror circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0010]    Preferred embodiments of the present invention will be described in detail based on the following figures, wherein: 
           [0011]      FIG. 1  shows a basic configuration of a constant current circuit according to an embodiment of the present invention; 
           [0012]      FIG. 2  shows another basic configuration of the constant current circuit; 
           [0013]      FIG. 3  shows still another basic configuration of the constant current circuit; 
           [0014]      FIG. 4  shows still another basic configuration of the constant current circuit; 
           [0015]      FIG. 5  is a diagram in which the circuit of  FIG. 1  is depicted in a simplified form to explain operation of the circuit; 
           [0016]      FIG. 6  depicts a further simplified form of the circuit shown in  FIG. 5 ; 
           [0017]      FIG. 7  depicts a still further simplified form of the circuit shown in  FIG. 6 ; 
           [0018]      FIG. 8  depicts another configuration of the circuit shown in  FIG. 6  in which a low-pass filter is added; 
           [0019]      FIG. 9  depicts a further modified configuration of the circuit shown in  FIG. 6 ; 
           [0020]      FIG. 10  depicts a configuration in which a low-pass filter is added to the circuit shown in  FIG. 9 ; 
           [0021]      FIG. 11A  shows a structure of the low-pass filter; 
           [0022]      FIG. 11B  shows another structure of the low-pass filter; 
           [0023]      FIG. 11C  shows still another structure of the low-pass filter; 
           [0024]      FIG. 11D  shows a further structure of the low-pass filter; 
           [0025]      FIG. 12  shows a configuration according to the embodiment using a parasitic capacitance; 
           [0026]      FIG. 13A  is a diagram showing a configuration according to an embodiment in which the low-pass filter is added to the circuit shown in  FIG. 1 ; 
           [0027]      FIG. 13B  is a diagram showing an improvement effect of adding the low-pass filter to the circuit shown in  FIG. 1 ; 
           [0028]      FIG. 14A  is a diagram showing a configuration according to an embodiment in which the low-pass filter is added to the circuit shown in  FIG. 2 ; 
           [0029]      FIG. 14B  is a diagram showing an improvement effect of adding the low-pass filter to the circuit shown in  FIG. 2 ; 
           [0030]      FIG. 15A  is a diagram showing a configuration according to an embodiment in which the low-pass filter is added to the circuit shown in  FIG. 3 ; 
           [0031]      FIG. 15B  is a diagram showing an improvement effect of adding the low-pass filter to the circuit shown in  FIG. 3 ; 
           [0032]      FIG. 16A  is a diagram showing a configuration according to an embodiment in which the low-pass filter is added to the circuit shown in  FIG. 4 ; 
           [0033]      FIG. 14B  is a diagram showing an improvement effect of adding the low-pass filter to the circuit shown in  FIG. 4 ; 
           [0034]      FIG. 17  is a diagram in which a plurality of output terminals are installed in a current mirror circuit having the configuration shown in  FIG. 1 , and a low-pass filter is provided for each of the output terminals; 
           [0035]      FIG. 18  is a diagram in which a plurality of output terminals are installed in a current mirror circuit having the configuration shown in  FIG. 2 , and a low-pass filter is provided for each of the output terminals; 
           [0036]      FIG. 19  is a diagram in which a plurality of output terminals are installed in a current mirror circuit having the configuration shown in  FIG. 3 , and a low-pass filter is provided for each of the output terminals; and 
           [0037]      FIG. 20  is a diagram in which a plurality of output terminals are installed in a current mirror circuit having the configuration shown in  FIG. 4 , and a low-pass filter is provided for each of the output terminals. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0038]    Referring to the drawings, preferred embodiments of the present invention will be described below. 
         [0039]    A mechanism for causing signal leakage will be explained. Here, a high frequency signal region in which a parasitic capacitance in a transistor is not negligible is considered in the description below. 
         [0040]      FIG. 1  shows a basic configuration of a constant current circuit according to an embodiment of the present invention. In the constant current circuit, a PNP transistor Q 1  has an emitter connected to a positive power supply and a collector connected via a constant current source CC to ground. A base of the transistor Q 1  which is a control end of the transistor Q 1  is connected to the positive power supply through a resistance R 1  and also connected to a collector of a PNP transistor Q 2 . A base of the transistor Q 2  is connected to the collector of the transistor Q 1 , while a collector of the transistor Q 2  is connected to ground. Further, a base line of the transistor Q 1  is connected to PNP transistors Q 7  and Q 8  whose emitters are connected to the positive power supply, and a base current is supplied from the transistor Q 2  to the base line. Thus, the transistors Q 7  and Q 8  constitute a current mirror circuit in conjunction with the transistor Q 1 . 
         [0041]    In addition, an NPN transistor Q 4  has a base to which a signal IN is input, a collector connected to the positive power supply, and an emitter connected to a collector of an NPN transistor Q 3 . An emitter of the transistor Q 3  is connected to ground, while a base of the transistor Q 3  is connected to ground through a resistance R 2  and also connected to both a base of an NPN transistor Q 6  and an emitter of an NPN transistor Q 5 . The transistor Q 6  has an emitter connected to ground and a collector connected to a base of the NPN transistor Q 5 . The transistor Q 5  has a collector connected to the positive power supply and an emitter connected to a common base for the transistors Q 3  and Q 6 . Therefore, the transistor Q 6  and the transistor Q 3  constitute a current mirror. Further, both the collector of the transistor Q 6  and the base of the transistor Q 5  are connected to a collector of the transistor Q 7 . As a result, a constant current corresponding to a current that flows through the transistor Q 1  is fed from the transistor Q 7 , and the constant current flows through both the transistor Q 6  and the transistor Q 3 . Therefore, the constant current flows through the transistor Q 4  as a bias current, which causes the transistor Q 4  to output a current corresponding to the input signal IN from an output terminal OUT 0  disposed on a collector side of the transistor Q 4 . 
         [0042]    On the other hand, a collector of the transistor Q 8  is connected to a collector of an NPN transistor Q 9  whose emitter is connected to ground. A collector of the transistor Q 9  is connected to a base of an NPN transistor Q 10 , and a collector of the transistor Q 10  is connected to the positive power supply while an emitter of the transistor Q 10  is connected to a base of the transistor Q 9 . 
         [0043]    The base of the transistor Q 9  is connected to ground through a resistance R 3  and also connected to a base of an NPN transistor Q 11 . The transistor Q 11  has an emitter connected to ground, and constitutes a current mirror in conjunction with the transistor Q 9 . 
         [0044]    A collector of the transistor Q 11  is connected to an emitter of an NPN transistor Q 12 . A collector of the transistor Q 12  is connected to the positive power supply through a resistance R 4 , and a signal IN 2  is input to a base of the transistor Q 12 . In addition, an output terminal OUT is connected to a collector of the transistor Q 12 . 
         [0045]    The constant current that flows through the transistor Q 1  is sent to the transistor Q 11  and then supplied as the bias current to the transistor Q 12 . Accordingly, a voltage output in accordance with ah input to the transistor Q 12  is obtained at the output terminal OUT. 
         [0046]    In the above-described circuit, the transistor Q 1  forms the current mirror together with the transistors Q 7  and Q 8 , and the transistors Q 7  and Q 8  function as a constant current source. In addition, the transistors Q 7  and Q 8  are circuits for handling different signals. 
         [0047]    Here, in order to find leakage of a high-frequency component that leaks to the output terminal OUT in the above-described circuit, the output terminal OUT 0  is removed from the circuit, and the input to the base of the transistor Q 12  is supplied at a constant voltage. Accordingly, the output terminal OUT 0  is removed from the circuits of from  FIG. 2  onward, and the input to the base of the transistor Q 12  is represented as a direct-current power supply. 
         [0048]    Then, in  FIG. 2 , the transistors Q 2 , Q 5 , and Q 10  disposed between the base and the collector of the transistor Q 1  which is located on an input side of the current mirror are composed of MOS transistors. The transistors Q 2 , Q 5 , and Q 10  function to provide the base current to the transistors that form the current mirror. When the MOS transistors which do not need the base current are used as the transistors Q 2 , Q 5 , and Q 10 , the current mirror can be configured with a high degree of accuracy. 
         [0049]    In  FIG. 3 , the transistors Q 1 , Q 2 , Q 7 , and Q 8  that constitute the current mirror circuit for supplying the constant current from the constant current source CC shown in  FIG. 1  are composed of NPN transistors. Accordingly, the transistors Q 3 , Q 5 , Q 6 , Q 9 , Q 10 , and Q 11  that constitute another current mirror circuit are composed of PNP transistors. Also in this circuit, the current that flows through the constant current source CC is supplied via the transistors Q 7  and Q 8  to the transistors Q 4  and Q 12  as the bias current, and the inputs to the bases of the transistors Q 4  and Q 12  are respectively obtained at output terminals of the transistors Q 4  and Q 12 . 
         [0050]      FIG. 4  shows an example of using the MOS transistors as the transistors Q 2 , Q 5 , and Q 10  in the circuit of  FIG. 3 . 
         [0051]    Here, an instance where an input to the transistor Q 4  has high frequencies is considered. In the circuit of  FIG. 1 , because a CB (collector-base) capacitance in each of the transistors is not negligible with respect to a voltage change at the high frequencies, the signal input to the base of the transistor Q 4  shown in  FIG. 1  is transferred in the following way: the emitter of the transistor Q 4 =&gt;the CB capacitance of the transistor Q 3 =&gt;EB of the transistor Q 5 //the CB capacitance of the transistor Q 6 =&gt;the CB capacitance of the transistor Q 7 =&gt;the CB capacitance of the transistor Q 8 =&gt;the CB capacitance of the transistor Q 9 //EB of the transistor Q 10 =&gt;the CB capacitance of the transistor Q 11 =&gt;the emitter of the transistor Q 12  (where the symbol // represents parallel connection). Thus, the input signal acts on the emitter of the transistor Q 12 , thereby causing the transistor Q 12  to operate. As a result of the operation, the input signal leaks from the collector of the transistor Q 12  to the output terminal. 
         [0052]    For example, when the CB capacitances of the transistors at the high frequencies in the circuit shown in  FIG. 1  are replaced with a power supply for retaining a voltage, the circuit of  FIG. 1  can be simplified as illustrated in  FIG. 5 . Further, when the circuit of  FIG. 5  is developed by removing the transistors Q 3 , Q 5 , Q 6 , Q 9 , Q 10 , and Q 11 , a circuit as shown in  FIG. 6  is obtained. Still further, when the transistors Q 1  and Q 2  are represented simply by diodes and the transistors Q 7  and Q 8  are represented only by direct current power supplies in the circuit of  FIG. 6 , the circuit can be also depicted as shown in  FIG. 7 . 
         [0053]    Finally, the most simplified diagram of the above-described circuit is shown in  FIG. 9 . In the circuit of  FIG. 9 , the direct current power supplies are omitted, and the CB capacitances of the transistors Q 7  and Q 8  are described as capacitances in their original forms. 
         [0054]    As can be seen from  FIG. 9 , it is found that, in the current mirror circuit having a plurality of outputs, signal leakage to the base line of the current mirror transistor due to the CB capacitance of one transistor (for example, the transistor Q 7 ) causes the collector of the output transistor Q 12  (not illustrated in  FIG. 9 ) to undergo a DC change which allows the signal to be leaked to the output. 
         [0055]    With this in view in the present embodiment, a low pass filter is mounted between an output collector and a part that receives a current from the output collector, to thereby eliminate the DC change which results in the signal leakage. More specifically, in this embodiment, a low pass filter LPF is inserted, as illustrated in  FIG. 10 , between an input signal source and the collector of the transistor Q 7  and between the collector of the transistor Q 8  and the output terminal OUT for outputting the signal, to remove, in the low pass filter LPF, the high-frequency component from the signal with a view toward preventing the signal leakage being transferred over the base line of the current mirror circuit. A slightly more detailed illustration of the circuit of  FIG. 10  is shown in  FIG. 8 . 
         [0056]    Here, the low pass filter LPF is preferably configured in a form as depicted in  FIG. 11A ,  11 B,  11 C, or  11 D. 
         [0057]    In  FIG. 11A , a connection point between two resistances connected in series is connected to one end of a capacitance whose the other end is connected to ground. In  FIG. 11B , a lower side (a ground side) of one resistance is connected to one end of the capacitance whose other end is connected to ground. In  FIG. 11C , an upper side (a positive power supply side) of one resistance is connected to one end of the capacitance whose other end is connected to ground. 
         [0058]    On the other hand, in  FIG. 11D , only the resistance is disposed on wiring. In this form of wiring with only the resistance, because each of the transistors in a semiconductor integrated circuit has a parasitic capacitance between a collector and a substrate (a C-SUB capacitance), the low pass filter LPF may be configured by only the resistance as shown in  FIG. 12 . More specifically, in the semiconductor integrated circuit, various types of transistors are formed by implanting impurities into a silicon substrate to thereby form an N well, a P well, an N region, a P region, and others. Accordingly, the parasitic capacitance is generated between a collector (C) region and the substrate (SUB). Then, this parasitic capacitance can be used as a capacitance for the low pass filter LPF. Such usage of the capacitance allows the high-frequency component to escape to a substrate side. For example, because the parasitic capacitance exists on each collector side of the transistors as shown in  FIGS. 11A to 11D , the low pass filter LPF can be formed on a wiring line by disposing the resistance on the wiring line for connecting the collectors of the transistor Q 7  and of the transistor Q 6 , or by disposing the resistance on a wiring line for connecting the collectors of the transistor Q 8  and of the transistor Q 10 . 
         [0059]      FIGS. 13A ,  14 A,  15 A, and  16 A show circuits according to other embodiments. It should be noted that a signal output corresponding to an input to the transistor Q 4  is not illustrated in  FIGS. 13A ,  14 A,  15 A, and  16 A. In each of the circuits, the low pass filter LPF using the series resistances and the capacitance in combination as shown in  FIG. 11A  is mounted on both the wiring line for connecting the collectors of the transistor Q 7  and of the transistor Q 6 , and the wiring line for connecting the collectors of the transistor Q 8  and of the transistor Q 10 . 
         [0060]    On the other hand,  FIGS. 13B ,  14 B,  15 B, and  16 B are diagrams each showing an effect obtained by the provision of the low pass filter LPF as described above. In  FIGS. 13B ,  14 B,  15 B, and  16 B, a curve designated as “NEW CIRCUIT” represents the circuit according to the embodiment. It can be seen from the drawings that signal leakage is suppressed in a wide range of from several megahertzs (MHz) to 1 gigahertz (GHz). 
         [0061]    Specifically,  FIG. 13A  shows the circuit configured by adding the low pass filters LPFs into the circuit shown in  FIG. 1 ,  FIG. 14A  shows the circuit configured by adding the low pass filters LPFs into the circuit shown in  FIG. 2 ,  FIG. 15A  shows the circuit configured by adding the low pass filters LPFs into the circuit shown in  FIG. 3 , and  FIG. 16A  shows the circuit configured by adding the low pass filters LPFs into the circuit shown in  FIG. 4 . 
         [0062]      FIGS. 17 ,  18 ,  19 , and  20  show application examples of the present embodiment. In the application examples, the base line of one current mirror input transistor Q 1  is connected to multiple current mirror output transistors Q 20   s  from which the constant currents are respectively output, and the output constant currents are supplied to respective output terminals. In addition, the low pass filter LPF is disposed on each current path between the current mirror output transistors Q 20   s  and the output terminals, to remove the high-frequency component through the low pass filter LPF on the current path. The current mirror circuit including the low pass filters is integrated into one cell, and the outputs from the current mirror output transistors Q 20   s  is connected to output terminals of the cell to respectively supply the constant current via the output terminals of the cell to operation circuits installed outside the cell. 
         [0063]    As described above, the current mirror circuit having a plurality of the constant current outputs is integrated into one cell, and the low pass filter is mounted on a part from which the constant currents are output, to thereby remove the high-frequency component. In this manner, a high-frequency signal being transferred from one output terminal via the base line of the current mirror circuit to another output terminal can be prevented. 
         [0064]    Therefore, without taking into account the effect of high frequencies transferred via the base line of the current mirror circuit to each of the output terminals (OUT  1 ,  2 ,  3 , . . .  4 , and  5 ) from which the constant current is output, a circuit to be connected to each of the output terminals can be designed. 
         [0065]    It should be noted that all the transistors may be configured using the MOS transistors, which has not explained in the description above. In this case, the PNP type corresponds to a P channel, the NPN type corresponds to an N channel, the collector corresponds to a drain, the emitter corresponds to a source, and the base (the control end) corresponds to the gate (the control end).