Abstract:
A communication device comprises a port via which the communication device is operable to communicate over a communication channel; command hardware operable to output a controlled signal over the communication channel; monitor hardware operable to monitor the controlled signal and output a controlling signal to block propagation of the controlled signal if a fault is identified in the controlled signal; and signal blocking circuitry coupled to a transmission path of the controlled signal and to a transmission path of the controlling signal; wherein, when the controlled signal is to be blocked, the signal blocking circuitry applies the controlling signal to the controlled signal such that a receiver at one end of the transmission path of the controlled signal identifies the controlled signal as a faulty signal; and wherein, when the controlled signal is not being blocked, the controlled signal is unimpeded by the signal blocking circuitry.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to U.S. Provisional Patent Application No. 61/081,302, filed on Jul. 16, 2008 and entitled “SYSTEM AND METHOD OF BLOCKING AN ELECTRICAL SIGNAL TRANSMISSION”, which is referred to herein as the &#39;302 application. 
     
    
     BACKGROUND 
       [0002]    In some electronic systems, it is desirable to block the transmission of a signal or otherwise prevent the propagation of the signal in some situations, such as when a signal is transmitted with an error or fault. To enable the blocking of a signal in some situations, additional circuitry is typically added. The components used in typical circuitry for blocking a signal transmission add to the cost and weight of the system. In addition, each component in the additional circuitry through which a signal passes can degrade the signal or can themselves be a source of errors. 
       SUMMARY 
       [0003]    In one embodiment, a communication device is provided. The communication device comprises a port via which the communication device is operable to communicate over a communication channel; command hardware operable to output a controlled signal over the communication channel; monitor hardware operable to monitor the controlled signal and output a controlling signal to block propagation of the controlled signal if a fault is identified in the controlled signal; and signal blocking circuitry coupled to a transmission path of the controlled signal and to a transmission path of the controlling signal; wherein, when the controlled signal is to be blocked, the signal blocking circuitry applies the controlling signal to the controlled signal such that a receiver at one end of the transmission path of the controlled signal identifies the controlled signal as a faulty signal; and wherein, when the controlled signal is not being blocked, the controlled signal is unimpeded by the signal blocking circuitry. 
     
    
     
       DRAWINGS 
         [0004]    Understanding that the drawings depict only exemplary embodiments and are not therefore to be considered limiting in scope, the exemplary embodiments will be described with additional specificity and detail through the use of the accompanying drawings, in which: 
           [0005]      FIG. 1  is a block diagram of one embodiment of a communication system. 
           [0006]      FIG. 2  is a diagram showing one example of the comparison of data associated with a signal to an expected data in order to detect an error in the signal. 
           [0007]      FIG. 3  is a block diagram of one embodiment of a fault-tolerant device used in the system of  FIG. 1 . 
           [0008]      FIG. 4  is an exemplary chart depicting the effect of one embodiment of signal blocking circuitry on a signal transmission. 
           [0009]      FIG. 5  is a block diagram of another embodiment of a fault-tolerant device. 
           [0010]      FIG. 6  is a block diagram of yet another embodiment of a fault-tolerant device. 
           [0011]      FIG. 7  is a flow chart depicting one embodiment of a method of preventing propagation of a signal. 
           [0012]      FIG. 8  is block diagram of another embodiment of a fault-tolerant device. 
       
    
    
       [0013]    In accordance with common practice, the various described features are not drawn to scale but are drawn to emphasize specific features relevant to the exemplary embodiments. 
       DETAILED DESCRIPTION 
       [0014]    In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific illustrative embodiments. However, it is to be understood that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made. Furthermore, the method presented in the drawing figures and the specification is not to be construed as limiting the order in which the individual acts may be performed. The following detailed description is, therefore, not to be taken in a limiting sense. 
         [0015]      FIG. 1  is a block diagram of one embodiment of a communication system  100 . Communication system  100  includes a fault-tolerant device  101  configured to block transmission of faulty signals, which transmits signals via one or more communication channels  114  to a receiver  128 . As used herein, “blocking” transmission of a signal includes causing the receiver  128  to reject the signal as faulty. It is to be understood that device  101  is provided by way of example and not by way of limitation. For example, other fault-tolerant devices can be used in other embodiments. In addition, receiver  128  can be implemented as a fault-tolerant device having circuitry similar to device  101  with the ability to transmit signals and to block faulty signals. 
         [0016]    In the example shown in  FIG. 1 , device  101  includes a command integrated circuit (IC)  104  and a monitor IC  106 . Circuitry in the command IC  104  is also referred to herein as “command hardware” and the circuitry in the monitor IC  106  is also referred to herein as “monitor hardware.” Exemplary command hardware and monitor hardware are described in more detail below with respect to  FIG. 3 . In addition, although the command hardware and monitor hardware are implemented in separate integrated circuits in the example shown in  FIG. 1 , the command and monitor hardware can be implemented in a single integrated circuit, if requirements permit, in other embodiments. Similarly, in other embodiments, the command hardware and the monitor hardware can be implemented in separate devices, or each can be implemented as circuits comprising several devices. 
         [0017]    Each communication channel  114  is implemented using a suitable communication medium or media (for example, metallic communication media such as twisted pair cables, coaxial cable and optical communication media such as fiber optic cables). Both the command IC  104  and the monitor IC  106  are coupled to the transmit portion  110  and one or both can be coupled to the optional receive portion  112  of the respective communication channel  114 . The communication channel  114  is coupled to the device  101  via port  102 . The command IC  104  transmits signals (also referred to herein as “controlled signals”) over transmit portion  110 . Since the monitor IC  106  is also coupled to the transmit portion  110 , the monitor IC  106  is able to monitor the signals transmitted by the command IC  104  over transmit portion  110 . In particular, the monitor IC  106  determines if a signal transmitted by the command IC  104  matches expected values or expected data for a transmission of data (for example, in the form of a packet or message) that is encoded onto the transmitted signal. 
         [0018]    Both the monitor IC  106  and the command IC  104  are coupled to application layer functionality  134 . Application layer functionality  134  processes data for the desired operation of device  101  and provides the data to monitor IC  106  and the command IC  104  for transmission over communication channel  114 . The command IC  104  encodes and transmits the data. The monitor IC  106  performs similar processing on the data from the application layer functionality  134  as the command IC  104  to determine the expected values or data to be transmitted. If the values computed by the monitor IC  106  do not match the values computed by the command IC  104 , an error has occurred. 
         [0019]    For example, in one implementation of such an embodiment, the monitor IC  106  performs a bit-by-bit comparison of the transmitted signal to an expected or computed value for the respective bit. One example of such a bit-by-bit comparison is shown in  FIG. 2 . In particular, the top line labeled “COM” in  FIG. 2  represents the data included in a signal transmitted by the command IC  104  and the second line labeled “MON” represents the data expected by the monitor IC  106 . The data is compared bit-by-bit in the monitor IC  106  to determine if the signal is faulty. In some embodiments, the monitor IC  106  compares the entire transmission of the signal to the expected data. In other embodiments, the monitor IC  106  only compares a part of the transmission, such as an identification field or some data field or sub-field that is known to be critical for system operation. 
         [0020]    In some fault tolerant systems, the monitor IC  106  needs to block or otherwise notify a receiver  128  that a signal is faulty before the end of the transmission or packet is received by the receiver  128 . This is referred to herein as “killing” the transmission or packet. The amount of time in which to kill the transmission is labeled as the reaction time in  FIG. 2 , where EOP represents the End Of Packet. Notably, although  FIG. 2  is described in relation to packet switched networks, other embodiments can be implemented using other network types. 
         [0021]    In the example shown in  FIG. 2 , a mismatch occurs in the twelfth bit. However, a mismatch can occur at any point in the data. Thus, the reaction time can be a relatively short period of time compared to the length of the transmission. In some embodiments, the signals are high speed signals on the order of 1 Gbps or higher. Hence, the monitor IC  106  has to be able to react sufficiently quickly to kill the transmission before the end of the reaction time. In addition, for non-faulty signals, it is desirable for the monitor IC  106  to reduce or minimize any distortions to the transmitted non-faulty signals. 
         [0022]      FIG.3  is a block diagram of one embodiment of the fault-tolerant device  101  shown in  FIG. 1 . One embodiment of signal blocking circuitry  116  is also shown in  FIG. 3  that enables a sufficiently quick response to kill a transmission and minimizes distortion of non-faulty signals. In  FIG. 3  the receive portion  112  of communication channel  114  and the Application layer Functionality  134  have been omitted to simplify  FIG. 3  for purposes of explanation. In addition, in the embodiment shown in  FIG. 3 , the transmit portion  110  of the communication channel  114  includes two links  111 - 1  and  111 - 2  for differential signaling. However, it is to be understood that a transmit portion  110  having a single communication link  111  for single-ended signaling can be used in other embodiments. In addition, in this embodiment, the transmitted signal is a digital signal transmitted over the communication links  111  using a communication standard from one of the IEEE 802.3 family of standards (commonly referred to as Ethernet). 
         [0023]    In the embodiment shown in  FIG. 3 , signal blocking circuitry  116  includes a diode  118  and a driver  120  for each link  111 . In this embodiment, diodes  118  are implemented as PiN diodes. A PiN diode is a diode having an intrinsic “i region” between a p layer and an n layer of a p-n junction. However, other diodes having a low capacitance, such as Schottky diodes, can be used in other embodiments. For example, a low capacitance diode has a capacitance on the order of &lt;1 picofarad in some high speed applications. In the embodiment shown in  FIG. 3 , one end of each diode  118  is coupled to the respective link  111  and the other end of each diode  118  is coupled to a respective driver  120 . Each driver  120  is coupled to a comparison circuit  126  in the monitor IC  106 . Notably, in this embodiment, diodes  118  are not included in the monitor IC  106 . Placing diodes  118  outside the monitor IC  106  helps reduce distortion of non-faulty signals. In particular, the capacitance of a pin of the IC package is typically larger than the capacitance of the diode  118 , which would increase distortion of non-faulty signals. However, it is to be understood that, in other embodiments, the diodes  118  are included in the monitor IC  106  package. 
         [0024]    In operation, processing circuitry  130  in the command IC  104  provides a signal to the differential transmitter  122  for transmission over links  111  to the receiver  128 . The differential receiver  124  in the monitor IC  106  also receives the differential signal transmitted by the differential transmitter  122  and outputs the signal data to the comparison circuit  126 . The comparison circuit  126  also receives the expected data values calculated by the monitor IC  106  in processing circuitry  130 . The comparison circuit  126  does a bit-by-bit comparison as described above. Under normal conditions when the data match bit-for-bit, the output of driver  120 - 1  is low, which reverse biases diode  118 - 1 . Similarly, since driver  120 - 2  is an inverting driver, the output of driver  120 - 2  is high under normal conditions, which reverse biases diode  118 - 2 . In the reverse biased state, the signals on links  111  and any direct current (DC) bias from the drivers  120  do not pass through the diodes  118 - 1  and  118 - 2 . 
         [0025]    The capacitance of drivers  120 - 1  and  120 - 2  is also small (for example, below 10 nanofarads). Since the drivers  120  and diodes  118  are coupled in series, the total capacitance is equal to the sum of the reciprocal of the individual capacitances. Thus, the total capacitance is smaller than the individual capacitance of either the diodes  118  or drivers  120 . Due to the low total capacitance and the fact that non-faulty signals and DC bias do not pass through the diodes  118 , little distortion of the non-faulty signals occurs in normal conditions. Thus, the controlled signal is unimpeded by the signal blocking circuitry  11   6 . Furthermore, since only a diode and a driver are used in this embodiment, the number of components which have the potential to corrupt the non-faulty signals is reduced. In addition, the cost and weight of the device  101  is also reduced as compared to typical fault tolerant devices due to the relatively smaller number of simpler components used in signal blocking circuitry  116 . 
         [0026]    If the comparison circuit  126  detects a mismatch, the comparison circuit  126  outputs a signal that drives the output of driver  120 - 1  high and the output of driver  120 - 2  low. In particular, drivers  120 - 1  and  120 - 2  are amplifiers that amplify the signal output from the comparison circuit  126  by increasing the current capability of the signal. The signal output by the comparison circuit  126  is also referred to herein as the “kill” signal or “controlling” signal. The amplified kill signal results in switching the bias of diodes  118 - 1  and  118 - 2 . When the bias of diodes  118 - 1  and  118 - 2  switches, the controlled signal transmitted by the differential transmitter  122  is impeded. In particular, the transmitted differential signal passes through the diodes  118 - 1  and  118 - 2  or a DC-bias is applied to the differential signal. Hence, the part of the controlled signal on link  111 - 1  is pulled high by the DC bias and the part of the controlled signal on link  111 - 2  is pulled low by the applied DC bias in this embodiment. The controlled signal is maintained in this separated state for a sufficient length of time to cause the receiver  128  to view the controlled signal as a faulty signal. Each part of the differential signal looks continuously high or continuously low to the receiver  128  for the duration of the Kill pulse. Thus, an alternating current (AC) signal riding on the DC bias no longer crosses the decision threshold of the receiver  128  which causes the receiver  128  to reject the signal. 
         [0027]      FIG. 4  is a diagram depicting an exemplary signal trace of a signal output from the signal blocking circuitry  116  of  FIG. 3 . The separation  401  is the result of switching the bias of diodes  118  to allow the transmitted faulty signal to pass through the diodes or to allow a DC-bias to be applied. In particular, the comparison circuit  126  outputs the kill signal to the drivers  120  for a predetermined amount of time that determines the length of the separation  401 . The predetermined amount of time is chosen so that the receiver interprets the signal as being faulty. For example, in this embodiment, 8b/10b encoding is used. In 8b/10b encoding, the longest that a signal can run without changing state is 5 bits. If a signal does not change state for more than 5 bits, the signal is perceived by the receiver  128  as an illegal symbol and is rejected. At speeds around 1.25 Gbps, 5 bits are equal to about 4 nanoseconds. The comparison circuit  126 , therefore, outputs the kill signal for more than 4 nanoseconds, which switches the bias of diodes  118  for a sufficient length of time. 
         [0028]    For example, in the embodiment shown in  FIG. 3 , monitor IC  106  includes a timer  132  that is set to count 16 bits. The comparison circuit  126 , thus, maintains the diodes  118  in the switched bias state for 16 bits, which results in the separation  401  shown in  FIG. 4  of about 12 nanoseconds. The second separation  403  in  FIG. 4  is the result of the diodes  118  trying to return to the normal or initial state (that is, the reversed bias state in this example) after the comparison circuit  126  ceases outputting the kill signal. As the diodes  118  return to the normal state, each side of the differential is pulled in the opposite direction and the differential signal is separated for approximately 10 nanoseconds, in this embodiment. Hence, signal blocking circuitry  116  results in two separations,  401  and  403 , which each last for approximately twice the amount of time needed to cause the receiver  128  to reject the faulty transmitted signal. 
         [0029]    Although 8b/10b encoding is discussed in this embodiment, it is to be understood that other encoding techniques can be used in other embodiments, such as, but not limited to, 4b/5b and Manchester encoding. In addition, although differential signaling is used in this embodiment, single-ended signaling can be used in other embodiments. In such embodiments, only a single diode  118  and driver  120  are used. 
         [0030]    For example, in one alternative embodiment, Manchester encoding is used for single-ended signaling. Manchester encoding requires the signal to flip state every other bit. Hence, in such an embodiment, comparison circuit  126  can transmit a kill signal for longer than 2 bits to maintain a diode  118  in the switched bias state. In the switched bias state, a DC-bias is applied or the transmitted signal will pass through diode  118  for longer than 2 bits, which prevents the receiver  128  from seeing the transmitted signal switch state for more than 2 bits. Therefore, the receiver  128  will reject the transmitted signal as a faulty signal. 
         [0031]      FIG. 5  is a block diagram of another embodiment of a fault-tolerant device  501  having signal blocking circuitry  516 . Fault-tolerant device  501  operates similar to fault-tolerant device  101  described in  FIGS. 1 and 2 . In the embodiment shown in  FIG. 5 , signal blocking circuitry  516  includes resistors  534 - 1  and  534 - 2 . Resistors  534 - 1  and  534 - 2  adjust the differential signal to make it as weak locally as it is seen by the receiver  128 . In this way, if the transmitter  122  is weak, an error is detected locally by monitor IC  106  whenever a too weak signal is received by the receiver  128 . The resisters  534 - 1  and  534 - 2  also mitigate any drop in impedance that the capacitance of differential receiver  124  may cause to the signals  111 . 
         [0032]      FIG. 6  is a block diagram of another embodiment of a fault-tolerant device  601  having signal blocking circuitry  616 . Fault-tolerant device  601  operates similar to fault-tolerant device  101  described in  FIGS. 1 and 2 . In the embodiment shown in  FIG. 6 , signal blocking circuitry  616  includes two diodes  618  and a driver  120  for each link  111 .  FIG. 6  illustrates that more than one diode  618  can be used to reduce the diodes&#39; total capacitance and reduce the distortion of non-faulty signals. 
         [0033]      FIG. 7  is a flow chart depicting one embodiment of a method  700  of preventing propagation of faulty transmissions. Method  700  can be implemented in a communication device such as device  101  described above. At block  702 , a transmission is initiated. For example, in some embodiments, a signal is encoded with transmission using a run-length limited (RLL) encoding technique such as 8b/10b, 4b/5b, etc., as described above. In addition, in some embodiments, the transmitted signal is a differential signal. At block  704 , it is determined if the transmitted signal contains an error or is otherwise faulty. In particular, an error is detected prior to completing the transmission. For example, in some embodiments, the monitor hardware can monitor the signal and perform a bit-for-bit comparison of the transmitted data with expected values to determine if the transmission contains an error, as described above. If an error is detected, a kill signal is generated at block  706 . The kill signal switches the bias of a diode, such as diode  118 , from a reverse biased state to a forward biased state. Switching the bias to a forward biased state causes a DC-bias to be applied to the transmitted signal through the diode. Since the DC-bias is applied to at least a portion of the transmitted signal such that no bit transition is seen, the receiver will identify the signal and (the transmission) as faulty and reject it as described above. 
         [0034]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiments shown. For example, in the embodiment described above, the signal blocking circuitry  116  is described as including a diode  118  and a driver  120  for each link  111 . However, other embodiments of signal blocking circuitry  116  can be used. One exemplary alternative of the signal blocking circuitry  816  is shown in  FIG. 8 . Signal blocking circuitry  816  is implemented with a directional optical coupler  817 , such as a Wye coupler, instead of the diode  118 . In such an embodiment, the controlled signal and the controlling signal are optical signals. Thus, electrical driver  120  is replaced with optical driver  820 . Outputting the controlling signal to the directional optical coupler  817  has a similar effect as adding the DC bias with the diode  118 . In particular, the directional optical coupler  817  adds the controlling signal to the controlled signal such that the receiver  128  is not able to perceive bit transitions in the controlled signal. Thus, the receiver  128  rejects the controlled signal as being faulty. In addition, the directional optical coupler  817  keeps the controlled signal&#39;s power from leaking out through the controlling signal&#39;s source, like the low capacitance of a reversed bias diode  118 . Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.