Abstract:
Provided is a flash memory, and more particularly, to a method and structure for erasing flash blocks based on back-bias. The method comprises the steps of forming a flash block on a silicon on insulator (SOI) substrate and forming a body-electrode on back side of the silicon on insulator (SOI) substrate.

Description:
[0001]     This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 10-2005-0035142 filed in Korea on Apr. 27, 2005, the entire contents of which are hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a flash memory, and more particularly, to a method for erasing flash blocks based on back-bias, and a structure thereof.  
         [0004]     2. Description of the Background Art  
         [0005]     While Dynamic Random Access Memory (DRAM) or Static RAM (SRAM) lose data when power turned off, flash memory has the advantage of Read Only Memory (ROM) that maintains stored data even when the power is off and the advantage of RAM that can input and output data. Thus, flash memory is called non-volatile memory.  
         [0006]     Since non-volatile memory can be highly integrated just as DRAM and it has an excellent data preservation property, it can be used as an auxiliary memory in a system and it has a wide range of applications, such as data storage including personal electronic communication devices, digital cameras, Moving Picture Experts Group Audio Level 3 (MP3) players, and memory cards which require mobility and portability.  
         [0007]     When the flash device is formed by using a silicon-on-insulator (SOI) substrate, there are advantages such as devices can be easily isolated, the area of each flash device can be reduced, and a short-channel effect caused by reduced channel length of each flash device can be reduced.  
         [0008]     Particularly, SOI technology which makes it possible to manufacture an ultra fine transistor having a double gate, a tri-gate, or a gate array, such as FinFET, is essential for the manufacturing of tera-bit flash memory devices going beyond sub-40 nm level.  
         [0009]     However, since the SOI substrate does not have a silicon substrate connected to a channel, there is a shortcoming that it cannot use conventional Fowler-Nordheim (F-N) tunneling which collectively erases data through block erasion and sector erasion by supplying high-voltage to a well.  
       SUMMARY OF THE INVENTION  
       [0010]     Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the background art.  
         [0011]     It is an object of the present invention to provide a method for manufacturing a flash memory device that has a high reproducibility and performs re-flash through a simple process by using a silicon-on-insulator (SOI) substrate.  
         [0012]     It is another object of the present invention to provide a method for manufacturing a small flash memory device by using an SOI substrate.  
         [0013]     According to an aspect of the present invention, provided is a method of manufacturing a flash memory device. The method comprises forming a flash block on a silicon on insulator (SOI) substrate and forming a body-electrode on back side of the silicon on insulator (SOI) substrate.  
         [0014]     The SOI substrate comprises a silicon substrate and an insulating film, and the doping concentration of the silicon substrate is more than 10 17  cm −3 .  
         [0015]     The SOI substrate comprises a silicon substrate and an insulating film, and the insulating film is thinner than 0.1 μm.  
         [0016]     The method of manufacturing a flash memory device further comprises depositing a passivation oxide layer.  
         [0017]     The flash block is formed as one of a floating-type, a silicon-oxide-nitride-oxide-silicon (SONOS), or a metal-oxide-nitride-oxide-silicon (MONOS).  
         [0018]     According to another aspect of the present invention, provided is a flash memory device. The flash memory device comprises a silicon on insulator (SOI) substrate, a flash block formed on the SOI substrate and a body-contact formed on back side of the SOI substrate.  
         [0019]     The SOI substrate comprises a silicon substrate and an insulating film, and the doping concentration of the silicon substrate is more than 10 17  cm −3 .  
         [0020]     The SOI substrate comprises a silicon substrate and an insulating film, and the insulating film is thinner than 0.1 μm.  
         [0021]     The flash memory device further comprises a passivation oxide layer deposited on the SOI substrate.  
         [0022]     The flash block is formed as one of a floating-type, a silicon-oxide-nitride-oxide-silicon (SONOS), or a metal-oxide-nitride-oxide-silicon (MONOS).  
         [0023]     The flash block comprises a control gate, a gate oxide film, and a floating gate.  
         [0024]     According to another aspect of the present invention, provided is a method of manufacturing a flash memory. The method comprises forming a silicon on insulator (SOI) substrate and a body-contact implantation (B.C.I) mask pattern, forming a body-contact implantation (B.C.I) area by applying an impurity to the SOI substrate using the B.C.I mask pattern, removing the B.C.I mask pattern and performing an annealing, forming a flash block on the SOI substrate and depositing a passivation oxide layer, forming a body-contact (B.C) mask on top of the passivation oxide layer and forming a contact hole by using the B.C mask and forming a body-contact in the contact hole.  
         [0025]     The SOI substrate comprises a silicon substrate and an insulating film, and the insulating film is thinner than 0.1 μm.  
         [0026]     The SOI substrate comprises a silicon substrate and an insulating film, and the doping concentration of the silicon substrate is more than 10 17  cm −3 .  
         [0027]     The flash block is formed as one of a floating type, a silicon-oxide-nitride-oxide-silicon (SONOS), or a metal-oxide-nitride-oxide-silicon (MONOS).  
         [0028]     The flash block comprises a control gate, a gate oxide film, and a floating gate.  
         [0029]     The SOI substrate comprises a silicon substrate and an insulating film, and when the silicon substrate is formed as a P-well, a N+ impurity is injected to the silicon substrate.  
         [0030]     The SOI substrate comprises a silicon substrate and an insulating film, and when the silicon substrate is formed as an N-well, a P+ impurity is injected to the silicon substrate.  
         [0031]     According to another aspect of the present invention, provided is a flash memory device. The flash memory device comprises a silicon on insulator (SOI) substrate comprising a silicon substrate including body-contact implantation (B.C.I) area and an insulating film, a flash block is formed on the SOI substrate, a passivation oxide film is formed on the SOI substrate to protect the flash block and a body-contact formed in a hall which is formed in the inside of both the passivation oxide film and the insulating film.  
         [0032]     The insulating film is thinner than 0.1 μm.  
         [0033]     The doping concentration of the silicon substrate is more than 10 17  cm −3 .  
         [0034]     An N+ impurity is injected to the B.C.I area of the silicon substrate when the silicon substrate is formed as a P-well.  
         [0035]     A P+ impurity is injected to the B.C.I area of the silicon substrate when the silicon substrate is formed as an N-well.  
         [0036]     The flash block is formed as one of a floating type, silicon-oxide-nitride-oxide-silicon (SONOS), or metal-oxide-nitride-oxide-silicon (MONOS).  
         [0037]     The flash block comprises a control gate, a gate oxide film, and a floating gate.  
         [0038]     Details of other embodiments are included in the detailed description and drawings of the present specification. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0039]     The invention will be described in detail with reference to the following drawings in which like numerals refer to like elements.  
         [0040]      FIGS. 1A  to  1 D are cross-sectional views with regard to a process for manufacturing a flash memory according to an embodiment of the present invention;  
         [0041]      FIGS. 2A  to  2 G are cross-sectional views with regard to a process for manufacturing a flash memory according to another embodiment of the present invention; and  
         [0042]      FIGS. 3A  to  3 G are cross-sectional views with regard to a process for manufacturing a flash memory according to still another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0043]     Preferred embodiments of the present invention will be described in a more detailed manner with reference to the drawings.  
         [0044]     The advantages and objects of the present invention and a method achieving the objects will be clearly understood by referring to the following embodiments which are described with reference to the accompanying drawings. However, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims. The present invention is only defined by the scope of claims in the present specification. Herein, the same reference number is given to the same constituent element throughout the specification although it appears in different drawings.  
         [0045]     Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.  
         [0046]      FIGS. 1A  to  1 D are cross-sectional views with regard to a process for manufacturing a flash memory according to an embodiment of the present invention.  
         [0047]     Referring to  FIG. 1A , a silicon substrate  101 , a lower insulating film  102 , and a silicon layer  103  are formed sequentially. This silicon/insulating file/silicon structure is called a silicon-on-insulator (SOI) substrate.  
         [0048]     When the silicon substrate  101  is doped in a high doping concentration or the thickness of the insulating film  102  is low, the back-bias voltage required to erase data stored in a flash block decreases. In an embodiment of the present invention, it is desirable that the doping concentration of the silicon substrate  101  is more than 10 17  cm −3  and the thickness of the lower insulating film  102  is less than 0.1 μm.  
         [0049]     In other words, the higher the doping concentration of the silicon substrate  101 , the more the resistance decreases, and, thus, the required back-bias voltage decreases.  
         [0050]     The back-bias voltage which is applied to the body-contact  106  formed in the lower part of the silicon substrate  101  falls down in the lower insulating film  102  and, then, is applied to the silicon layer  103 . Thus, the thinner the lower the insulating film  102  is, the less back-bias voltage is required to erase data stored in the flash blocks  104 .  
         [0051]     Referring to  FIG. 1B , flash blocks  104  comprising a control gate  104   a , a gate oxide film  104   b , and a floating gate  104   c  are formed. In this embodiment, the flash blocks  104  may be implemented as a floating type. However, the flash blocks  104  have diverse types, such as a silicon-oxide-nitride-oxide-silicon (SONOS), metal oxide nitride oxide silicon (MONOS).  
         [0052]     Referring to  FIG. 1C , a passivation oxide layer  105  is deposited to protect the flash blocks  104 . Next, referring to  FIG. 1D , a body-electrode  106  is formed on the back side of the silicon substrate  101 .  
         [0053]     When the high back-bias voltage is applied to the body-contact  106  formed in the lower surface of the silicon substrate  101  and 0[V] is applied to the control gate  104   a , F-N tunneling current is generated in the gate oxide film  104   b  and electrons flow from the floating gate  104   c  to the silicon substrate  101 . Accordingly, a data stored in the flash blocks  104  is erased.  
         [0054]     In this embodiment, it is desirable that the high back-bias voltage is 10[V]. However, the back-bias voltage can be changed according to a thickness of the lower insulating film  102 , a concentration of the silicon substrate  101 , or a characteristic of the flash block  104 .  
         [0055]      FIGS. 2A  to  2 G are cross-sectional views with regard to a process for manufacturing a flash memory according to another embodiment of the present invention.  
         [0056]     Referring to  FIG. 2A , a silicon substrate  201 , a lower insulating film  202 , a silicon layer  203 , and a body-contact implantation (B.C.I) mask pattern  204  are formed sequentially. The structure comprising the silicon substrate  201 , the lower insulating film  202 , and a silicon layer is called as a silicon on insulator (SOI) substrate.  
         [0057]     The B.C.I mask pattern  204  is formed by using a photoresist process.  
         [0058]     Preferably, the lower insulating film is thinner than 0.1 μm. The thinner the lower insulating film is, the less back-bias voltage to erase flash blocks becomes.  
         [0059]     Subsequently, referring  FIG. 2B , N+ impurity having a high level of energy is injected into a P-well of the silicon substrate  201  for body-contacts by using the B.C.I mask pattern  204 . Consequently, a body-contact implantation (B.C.I) area  205  is formed.  
         [0060]     The high level of energy required for the N+ impurity insertion means a level of energy high enough to inject the impurity into the P-well of the silicon substrate  201  under the lower insulating film. The level of energy is different according to the kind of injected impurity and the thickness of the silicon layer  203  and the lower insulating film  202 .  
         [0061]     The B.C.I regions  205  with the impurity injected thereto are isolated from each other due to step height between the B.C.I mask pattern  204  and the silicon layer  203 .  
         [0062]     Subsequently, referring to the  FIG. 2C , the B.C.I mask pattern  204  is removed and annealing occurs.  
         [0063]     Next, referring to the  FIG. 2D , flash blocks  206  are formed on the lower insulating film  202 . The flash blocks  206  comprise a control gate  206 , a gate oxide film  206   b , and a floating gate  206   c.    
         [0064]     In this embodiment, the flash blocks are implemented as a floating type. However, the flash blocks  206  are formed in diverse forms, such as a SONOS and a MONOS.  
         [0065]     Referring to  FIG. 2E , a passivation oxide layer  207  is deposited to protect the flash block  206 .  
         [0066]     Referring to  FIG. 2F , contact holes  209  are formed by using a body-contact (B.C) mask  208 .  
         [0067]     Subsequently, referring to  FIG. 2G , body-contacts  210  are formed through metal deposition or patterning.  
         [0068]     When a high back-bias voltage is applied to the body-contact  210  of the flash memory  200 , 0[V] is applied to the control gate  206   a , and the back bias voltage is applied to the B.C.I areas  205 , F-N tunneling current is generated in the gate oxide film  206   b  and electrons flow from the floating gate  206   c  to the silicon substrate  201 . Accordingly, data stored in the flash blocks  206  is erased.  
         [0069]      FIGS. 3A  to  3 G are cross-sectional views with regard to a process for manufacturing a flash memory according to still another embodiment of the present invention.  
         [0070]     Referring to  FIG. 3A , a silicon substrate  301 , a lower insulating film  302 , a silicon layer  303 , and a B.C.I. mask pattern  304  are formed sequentially.  
         [0071]     In this embodiment, the silicon substrate  301  is formed as N-well, and the B.C.I. mask pattern  304  is formed by using a photoresist process.  
         [0072]     Preferably, the lower insulating film is thinner than 0.1 μm to decrease the back-bias voltage required to erase data stored in flash blocks  306  (see  FIGS. 3D  to  3 G).  
         [0073]     In other words, the back-bias voltage which is applied to the silicon substrate  301  falls down in the lower insulating film  302  and, then, is applied to the silicon layer  303 . Thus, the thinner the lower the insulating film  302  is, the less the back-bias voltage is required to erase data stored in the flash blocks  306  (see  FIGS. 3D  to  3 G).  
         [0074]     Subsequently, referring to  FIG. 3B , P+ impurity having a high level of energy is injected into an N-well of the silicon substrate  301  for body-contacts by using the B.C.I mask pattern  304 . Consequently, body-contact implantation (B.C.I) areas  305  are formed.  
         [0075]     The high level of energy needed in the P+ impurity insertion means a level of energy high enough to inject the impurity into the N-well of the silicon substrate  301  under the lower insulating film  302 . The level of energy required differs according to the kind of injected impurity and the thickness of the silicon layer  303  and the lower insulating film  302 .  
         [0076]     The B.C.I regions  305  with the impurity injected thereto are isolated from each other due to step height between the B.C.I mask pattern  304  and the silicon layer  303 .  
         [0077]     Subsequently, referring to  FIG. 3C , the B.C.I mask pattern  304  is removed and annealing is carried out.  
         [0078]     Next, referring to  FIG. 3D , flash blocks  306  are formed on the lower insulating film  302 . The flash blocks  306  comprise a control gate  306   a , a gate oxide film  306   b , and a floating gate  306   c.    
         [0079]     In this embodiment, the flash blocks  306  are implemented as a floating type. However, the flash blocks  306  are formed in diverse forms, such as a SONOS and a MONOS.  
         [0080]     Referring to  FIG. 3E , a passivation oxide layer  307  is deposited to protect the flash bocks  306 .  
         [0081]     Referring to  FIG. 3F , contact holes  309  are formed by using a body-contact (B.C.) mask  308 .  
         [0082]     Subsequently, referring to  FIG. 3G , body-contacts  310  are formed through metal deposition or patterning.  
         [0083]     When a high back-bias voltage is applied to the body-contact  310  of the flash memory  300 , 0[V] is applied to the control gate  306   a , and the back bias voltage is applied to the B.C.I areas  305 , F-N tunneling current is generated in the gate oxide film  306   b  and electrons flow from the floating gate  306   c  to the silicon substrate  301 . Accordingly, data stored in the flash blocks  306  is erased.  
         [0084]     According to the present invention described above, a flash memory device that can perform re-flash with a high reproducibility in a simple manner can be manufactured by using the SOI substrate. Also, with the SOI substrate, it is possible to manufacture a small flash memory device.  
         [0085]     The invention being thus described may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.