Abstract:
In a gain-variable amplifier including a dual differential amplifier circuit for amplifying an input voltage to generate an output voltage with a gain in accordance with first and second control voltages, and a control voltage generating circuit, for generating the first and second control voltages in accordance with a gain control voltage, a polarity of a difference between the first and second control voltages is unchanged, when the gain control voltage is within a control range.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a gain-variable amplifier. 
     2. Description of the Related Art 
     A prior art gain-variable amplifier includes a dual differential amplifier circuit for amplifying an input voltage to generate an output voltage with a gain in accordance with first and second control voltages, and a control voltage generating circuit for generating the first and second control voltages in accordance with a gain control voltage, a polarity of a difference between the first and second control voltages is changed, when the gain control voltage is within a control range. This will be explained later in detail. 
     In the prior art gain-variable amplifier, however, since the gain characteristics have an inflection point with respect to the gain control voltage, it is difficult to control the gain by the gain control voltage. Also, the phase of an output voltage is inverted at the inflection point. This substantially reduces a control range of gain by the gain control voltage. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to easily control a gain-variable amplifier by a gain control voltage. 
     Another object is to provide a gain-variable amplifier with no inversion of phase of an output voltage. 
     According to the present invention, in a gain-variable amplifier including a dual differential amplifier circuit for amplifying an input voltage to generate an output voltage with a gain in accordance with first and second control voltages, and a control voltage generating circuit, for generating the first and second control voltages in accordance with a gain control voltage, a polarity of a difference between the first and second control voltages is unchanged, when the gain control voltage is within a control range. Thus, no inflection point is generated in the gain characteristics. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram illustrating a prior art gain-variable amplifier; 
     FIG. 2 is a graph showing the gain characteristics of the gain-variable amplifier of FIG. 1; 
     FIG. 3 is a circuit diagram illustrating a first embodiment of the gain-variable amplifier according to the present invention; 
     FIG. 4 is a graph showing the gain characteristics of the gain-variable amplifier of FIG. 3; 
     FIG. 5 is a circuit diagram illustrating a second embodiment of the gain-variable amplifier according to the present invention; 
     FIG. 6 is a graph showing the gain characteristics of the gain-variable amplifier of FIG. 5; 
     FIG. 7 is a circuit diagram illustrating a third embodiment of the gain-variable amplifier according to the present invention; and 
     FIG. 8 is a circuit diagram illustrating a fourth embodiment of the gain-variable amplifier according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiments, a prior art gain-variable amplifier will be explained with reference to FIGS. 1 and 2. 
     In FIG. 1, a first differential amplifier is formed by two NPN type transistors Q 1  and Q 2  having a common emitter connected via a constant current source IS 1  whose current is I 1  to a ground terminal GND. An AC input voltage V in  is applied between input terminals IN 1  and IN 2 , i.e., between the bases of the transistors Q 1  and Q 2 . 
     The first differential amplifier amplifies the input voltage V in . 
     Also, a second differential amplifier is formed by two NPN type transistors Q 3  and Q 4  having a common emitter connected to the collector of the transistor Q 1 . The collector of the transistor Q 3  is connected to a power supply terminal V CC , while the collector of the transistor Q 4  is connected via an output resistor R 0  to the power supply terminal V CC . 
     Similarly, a third differential amplifier is formed by two NPN type transistors Q 5  and Q 6  having a common emitter connected to the collector of the transistor Q 2 . The collector of the transistor Q 5  is connected to the power supply terminal V CC , while the collector of the transistor Q 6  is connected via the output resistor R 0  to the power supply terminal V CC . 
     The output resistor R 0  provides an output voltage V out  at an output terminal OUT. In this case, a current I 0  flowing through the resistor R 0  is formed by a negative phase current I -   flowing through the transistor Q 4  of the second differential amplifier and the transistor Q 1  of the first differential amplifier and a positive phase current I +   flowing through the transistor Q 6  of the third differential amplifier and the transistor Q 2  of the first differential amplifier. Note that the negative phase current I -   is opposite in phase to the positive phase current I + . 
     Also, the bases of the transistors Q 3  and Q 6  receive a first control voltage V C .spsb.1, while the bases of he transistors Q 4  and Q 5  receive a second control voltage V C .spsb.2. The control voltages V C .spsb.1 and V C .spsb.2 are generated by a control voltage generating circuit GEN. 
     The control voltages generating circuit GEN is constructed by a constant voltage source VS 1  and a voltage divider formed by two resistors R 1  and R 2  between the base of the transistor Q 6  and a gain control terminal C whose voltage is V C . That is, the control voltage V C .spsb.1 is generated by the constant voltage source VS 1 , while the control voltage V C .spsb.2 is generated by the voltage divider (R 1 , R 2 ). In this case, 
     
         V.sub.C.spsb.2 =V.sub.C.spsb.1 +(V.sub.C -V.sub.C.spsb.1)·R.sub.1 /(R.sub.1 +R.sub.2)                                       (1) 
    
     Thus, the higher the voltage V C .spsb.2 (V C ), the larger the negative phase current I - . On the other hand, the lower the voltage V C .spsb.2 (V C ), the larger the positive phase current I + . 
     The operation of the gain-variable amplifier of FIG. 1 is explained next in more detail. 
     If V C  &gt;V C .spsb.1, i.e., V C .spsb.2 &gt;V C .spsb.1, the voltage at the bases of the transistors Q 3  and Q 6  is higher than the voltage at the bases of the transistors Q 4  and Q 5 . Therefore, the negative phase current I -   is greater than the positive phase current I + . In this state, when the gain control voltage V C  is further increased, the current I 0  (=I +  +I - ) is increased. Thus, as shown in FIG. 2, the gain of the gain-variable amplifier of FIG. 1 is increased as the gain control voltage V C  is increased. 
     On the other hand, if V C  &lt;V C .spsb.1, i.e., V C .spsb.2 &lt;V C .spsb.1, the voltage at the bases of the transistors Q 4  and Q 5  is higher than the voltage at the bases of the transistors Q 3  and Q 6 . Therefore, the positive phase current I +   is greater than the negative phase current I - . In this state, when the again control voltage V C  is further decreased, the current I 0  (=I +  +I - ) is increased. Thus, as shown in FIG. 2, the gain of the gain-variable amplifier of FIG. 1 is increased as the gain control voltage V C  is decreased. 
     In addition, if V C  =V C .spsb.1, i.e., V C .spsb.2 =V C .spsb.1, the voltage at the bases of the transistors Q 3  and Q 6  is equal to the voltage at the bases of the transistors Q 4  and Q 5 . Therefore, the negative phase current I -   is equal to the positive phase current I + . In this case, since the negative phase current I -  is opposite in phase to the positive phase current I + , so that the negative phase current I -   offsets the positive phase current I + , the current I 0  includes only a DC component and is minimum. Thus, as shown in FIG. 2, the gain of the gain-variable amplifier of FIG. 1 is minimum. 
     In the gain-variable amplifier of FIG. 1, since the gain characteristics has an inflection point as indicated by A in FIG. 2, it is difficult to control the gain by the gain control voltage V C . Also, the phase of the output voltage V out  is inverted at the inflection point A. Since only a half of the exploitable control range is utilized, the control range is substantially reduced. 
     In FIG. 3, which illustrates a first embodiment of the present invention, a control voltage generating circuit GEN1 is provided instead of the control voltage generating circuit GEN. The control voltage generating circuit GEN1 is constructed by a differential amplifier formed by NPN type transistors Q 11  and Q 12  having a common emitter connected to a constant current source IS 2  whose current is I 2 . The base of the transistor Q 11  is connected to a constant voltage source VS 2  whose voltage is V R , and a voltage divider formed by resistors R 11  and R 12  is connected between the base of the transistor Q 11  and the gain control terminal C. 
     Also, a resistor R 13  is connected between the power supply terminal V CC  and the collector of the transistor Q 11 , and resistors R 14  and R 15  are connected between the power supply terminal V CC  and the collector of the transistor Q 12 . Further, a resistor R 16  is connected between the collectors of the transistors Q 11  and Q 12 . Here, assume that 
     
         R.sub.13 =R.sub.14                                         (2) 
    
     
         R.sub.15 =R.sub.16                                         (3) 
    
     The operation of the gain variable amplifier of FIG. 3 is explained next. 
     If V C  =0V (GND), the voltage at the base of the transistor Q 11  is higher than the voltage at the base of the transistor Q 12 , so that the transistors Q 11  and Q 12  are turned ON and OFF, respectively. As a result, the current I 2  flows through the transistor Q 11 . In this case, 
     
         V.sub.C.spsb.2 =V.sub.C.spsb.1 +(V.sub.CC -V.sub.C.spsb.1)·(R.sub.15 +R.sub.16)/(R.sub.14 +R.sub.15 +R.sub.16)&gt;V.sub.C.spsb.1                                 (4) 
    
     Thus, the negative phase current I -  is greater than the positive phase current I + . 
     Also, if V C  =V R , the voltage at the base of the transistor Q 11  is equal to the voltage at the base of the transistor Q 12 . As a result, a current of I 2  /2 flows through each of the transistors Q 11  and Q 12 . Therefore, if a current flowing from the collector of the transistor Q 11  via the resistor R 16  to the collector of the transistor Q 12  is defined by I 16 , 
     
         V.sub.C.spsb.1 =V.sub.CC -(I.sub.2 /2+I.sub.16)·R.sub.13 (5) 
    
     
         V.sub.C.spsb.2 =V.sub.CC -(I.sub.2 /2-I.sub.16)·R.sub.14 (6) 
    
     Since R 13  =R 14  (see formula (2)), from the formulae (5) and (6), 
     
         V.sub.C.spsb.2 &gt;V.sub.C.spsb.1                             (7) 
    
     Further, if V C  =V CC , the voltage at the base of the transistor Q 11  is lower than the voltage at the base of the transistor Q 12 , so that the transistors Q 11  and Q 12  are turned OFF and ON, respectively. As a result, the current I 2  flows through the transistor Q 12 . Also, in this case, from the formulae (2) and (3), 
     
         R.sub.13 +R.sub.16 =R.sub.14 +R.sub.15                     (8) 
    
     Therefore, a current of I 2  /2 flows through the resistors R 13  and R 16 , and also, a current of I 2  /2 flows through the resistors R 14  and R 15 . Therefore, 
     
         V.sub.C.spsb.1 =V.sub.CC -(I.sub.2 /2)·R.sub.13   (9) 
    
     
         V.sub.C.spsb.2 =V.sub.CC -(I.sub.2 /2)·R.sub.14   (10) 
    
     Since R 13  =R 14  (see formula (2)), from the formulae (9) and (10), 
     
         V.sub.C.spsb.2 =V.sub.C.spsb.1                             (11) 
    
     Therefore, as shown in FIG. 4, the gain of the gain-variable amplifier of FIG. 3 is decreased as the gain control voltage V C  is increased. In this case, since the gain control voltage V C  is from 0V to V CC , the negative phase current I -   is greater than the positive phase current I + . Also, when V C  =V CC , the gain of the gain-variable amplifier of FIG. 3 is minimum as indicated by A in FIG. 4. 
     Thus, in the gain-variable amplifier of FIG. 3, since the gain characteristics have no inflection point, it is easy to control the gain by the gain control voltage V C . Also, the phase of the output voltage V out  is never inverted. Since a full of the exploitable control range can be utilized, the control range of gain by the gain control voltage V C  can be substantially increased. 
     In FIG. 5, which illustrates a second embodiment of the present invention, a control voltage generating circuit GEN2 is provided instead of the control voltage generating circuit GEN1 of FIG. 3. In the control voltage generating circuit GEN2, the resistor R 13  of FIG. 3 is exchanged with the resistors R 14  and R 15  of FIG. 3. In other words, the control voltages V C .spsb.1 and V C .spsb.2 are exchanged with each other. 
     The operation of the gain variable amplifier of FIG. 5 is explained next. 
     If V C  =0V(GND), the voltage at the base of the transistor Q 11  is higher than the voltage at the base of the transistor Q 12 , so that the transistors Q 11  and Q 12  are turned ON and OFF, respectively. As a result, the current I 2  flows through the transistor Q 11 . Also, in this case, from the formula (8), a current of I 2  /2 flows through the resistors R 13  and R 16 , and also, a current of I 2  /2 flows through the resistors R 14  and R 15 . Therefore, 
     
         V.sub.C.spsb.1 =V.sub.CC -(I.sub.2 /2)·R.sub.13   (12) 
    
     
         V.sub.C.spsb.2 =V.sub.CC -(I.sub.2 /2)·R.sub.14   (13) 
    
     Since R 13  =R 14  (see formula (2)), from the formulae (12) and (13), 
     
         V.sub.C.spsb.2 =V.sub.C.spsb.1                             (14) 
    
     Also, if V C  =V R , the voltage at the base of the transistor Q 11  is equal to the voltage at the base of the transistor Q 12 . As a result, a current of I 2  /2 flows through each of the transistors Q 11  and Q12. Therefore, 
     
         V.sub.C.spsb.1 =V.sub.CC -(I.sub.2 /2-I.sub.16)·R.sub.13 (15) 
    
     
         V.sub.C.spsb.2 =V.sub.CC -(I.sub.2 /2+I.sub.16)·R.sub.14 (16) 
    
     Since R 13  =R 14  (see formula (2)), from the formulae (15) and (16), 
     
         V.sub.C.spsb.2 &lt;V.sub.C.spsb.1                             (17) 
    
     Further, if V C  =V CC , the voltage at the base of the transistor Q 11  is lower than the voltage at the base of the transistor Q 12 , so that the transistors Q 11  and Q 12  are turned OFF and ON, respectively. As a result, the current I 2  flows through the transistor Q 12 . In this case, 
     
         V.sub.C.spsb.1 =V.sub.C.spsb.2 +(V.sub.CC -V.sub.C.spsb.2)·(R.sub.15 +R.sub.16)/(R.sub.14 +R.sub.15 +R.sub.16)&gt;V.sub.C.spsb.2                                 (18) 
    
     Thus, the positive phase current I +   is greater than the negative phase current I - . 
     Therefore, as shown in FIG. 6, the gain of the gain-variable amplifier of FIG. 5 is increased as the gain control voltage V C  is increased. In this case, the gain control voltage V C  is from 0V to V CC , the positive phase current I +   is greater than the negative phase current I - . Also, when V C  =0V, the gain of the gain-variable amplifier of FIG. 5 is minimum as indicated by A in FIG. 6. 
     Thus, in the gain-variable amplifier of FIG. 5, since the gain characteristics have no inflection point, it is easy to control the gain by the gain control voltage V C . Also, the phase of the output voltage V out  is never inverted. Since a full of the exploitable control range can be utilized, the control range of gain by the gain control voltage V C  can be substantially increased. 
     In FIG. 7, which illustrates a third embodiment of the present invention, the resistors R 13 , R 14 , R 15  and R 16  of FIG. 3 are replaced by diodes D 1 , D 2 , D 3  and D 4 , respectively. In this case, the values of the resistors R 13 , R 14 , R 15  and R 16  of FIG. 3 are replaced by the saturation currents of the diodes D 1 , D 2 , D 3  and D 4 , respectively. That is, the saturation current of the diode D 1  is equal to that of the diode D 2 , and the saturation current of the diode D 3  is equal to that of the diode D 4 . Thus, the operation of the gain-variable amplifier of FIG. 7 is the same as that of the gain-variable amplifier of FIG. 3. 
     In FIG. 8, which illustrates a fourth embodiment of the present invention, the resistors R 13 , R 14 , R 15  and R 16  of FIG. 5 are replaced by diodes D 1 , D 2 , D 3  and D 4 , respectively. Also, in this case, the values of the resistors R 13 , R 14 , R 15  and R 16  of FIG. 5 are replaced by the saturation currents of the diodes D 1 , D 2 , D 3  and D 4 , respectively. That is, the saturation current of the diode D 1  is equal to that of the diode D 2 , and the saturation current of the diode D 3  is equal to that of the diode D 4 . Thus, the operation of the gain-variable amplifier of FIG. 8 is the same as that of the gain-variable amplifier of FIG. 5. 
     As explained hereinabove, according to the present invention, since the gain characteristics have no inflection point, it is easy to control the gain by the gain control voltage. Also, the phase of the output voltage is never inverted. As a result, a control range of gain by the gain control voltage can be substantially increased.