Abstract:
Therefore, the object of the invention is to utilize the unused channel capacity of the television channel even more optimally for additional signals. Both on the transmitting, as well as the receiving side, the clock pulses for video and audio data to be additionally transmitted are generated from the FBAS useful signal by counting, weighting and decision-making, both signals being separately digitized, buffered, and compressed before being superimposed upon on the useful video signal. Subsequent to the same clock pulse generation, the steps follow in the reverse order on the receiver side. The implementation can be carried out on the transmitter side using additional equipment, on the receiver side by computer software or additional devices installed in the conventional TV set. The application can be carried out for any additional video and sound signals. A preferred special application is a community picture broadcast similar to a slide presentation.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method of transmitting additional data in television frames, as well as to a transmitting device, a receiving device, and a system for carrying out the method. Methods and equipment are known for audio data, for example, from Gassmann/Eckert: &#34;Das COM-System&#34; [The COM System],Funkschau 1970, no. 20, pages 689-692 and no. 21, pages 749-750, and for video data from Langenkamp/Lowy: &#34;Megatext-IC fur Videotext und Grafik&#34; [Megatext IC for video text and graphics], RFE1994, no. 7, pages 18-20. 
     The properties of the FBAS signal (color, video, sweep and synchronization signal) leave open the possibility of superpositioning other information-carrying signals (additional data) without interfering with reception of the television broadcast program. Although most publications are concerned with only one type of additional data, the transmission of several additional test signals and data signals is described, for example, by Rudolf Meusel: Fernsehtechnik [Television Technology], Huttig 1991, on pages 210-227 in chapter 9. The additional data are transmitted at the highest possible transmission rate and with a high transmission reliability. 
     Although radio satellite technology has permitted reception of an ever increasing number of television programs, local program providers offer no possibility of regional services because of the large coverage zones and high cost. However, broad-band communication networks are not suitable for portable equipment and reception sites at great distances. The terrestrial transmitter network infrastructure already contains test lines and video text, mainly in the video-free lines. Additional wireless services have often failed because of the shortage of frequencies and the high cost of television studios. German Published Application DE-OS 25 16 742 discloses a television system with which digitized audio signals are transmitted during the back porch period. To be able to transmit a higher data rate, the respective FBAS signal is modified so that the back porch is lengthened at the expense of the duration of the horizontal synchronizing pulse. The modified FBAS signal and the digitized audio signals are sent to an adder that inserts the digitized audio signal into the lengthened back porch. 
     German Published Application DE-OS 31 03 406 discloses a method of transmitting digitized audio signals in the horizontal blanking interval of a video signal. However, this prior art document does not address the problem of making the color and/or video signal-free intervals of an FBAS signal optimally available for the transmission of additional data. 
     German Published Application DE-OS 37 32 111 discloses a method of adjusting the propagation time of video and audio signals to a reference signal. According to the known method, before the video signal is entered into the memory of a video synchronizer, the audio signal is inserted into the blanking intervals of the video signal. The video and audio signals are processed simultaneously in the memory of the video synchronizer. After triggering the processed signal, the audio signal inserted is separated from the video signal again. This document also does not address the problem of being able to better utilize the color and/or video signal-free intervals of the FBAS signal for transmission of additional data. 
     German Published Application DE-OS 29 01 034 discloses a method and a circuit arrangement for compressing and decompressing analog signals in digital form. The compressed digital signals are, in fact, inserted into the free information intervals of video signals or transmitted instead of television signals. However, this document does not contain any references or suggestions indicating how the color and/or video signal-free intervals of an FBAS signal can be utilized better for the transmission of additional data. 
     The object of present invention is to utilize the unused channel capacity of the television channel even more optimally and thus ensure a high transmission reliability, high transmission rates, high system variability, interference-free reception of the television program, superpositioning of the additional data without technical intervention in the television transmitter modules and the compatibility of existing television equipment for PALplus, NTSC and SECAM. 
     This method with its counting, weighting and decision-making elements is readily suitable for additional implementation in computers which can also be equipped with television receiving cards for multimedia purposes. 
     An advantageous possible refinement of the method facilitates implementation in terms of both hardware on the receiving end and addition on the transmitting end. 
     A suitable device for implementation in terms of hardware is suitable as an addition to the existing transmitters and receivers of the television broadcast network. 
     With the present invention, the information-carrying signals for the additional data transmission are merged using an overlay circuit in such a way that signals can be program-positioned in all color and video signal-free intervals. 
     The additional data transmission system according to present invention has a number of advantages. Due to the selection with counting and weighting, the system can be configured in making a decision about the use of the time segments for the additional data transmission in such a way that there is no interference in reception of the television broadcast. The superpositioning and reception of the information-carrying additional data signals can be accomplished with small, relatively inexpensive additional equipment. The transmission rate can be adapted as needed to the conditions of the real channel by programming. The additional data transmission is implemented with signal levels lower than 20 mV, thus ensuring compatibility with conventional commercial television equipment. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is explained in greater detail below on the basis of one example and with reference to the respective figures, which show: 
     FIG. 1: the additional data adder on the transmitting end, 
     FIG. 2: the additional data receiver on the receiving end, 
     FIG. 3: the signal diagram for superpositioning of the FBAS signal and the additional data signal for the first type of line, 
     FIG. 4: the signal diagram for superpositioning of the FBAS signal and the additional data signal for a second type of line, 
     FIG. 5: the signal diagram for reception of the additional data signal for the first type of line, and 
     FIG. 6: the signal diagram for reception of the additional data signal for a second type of line. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows the data-controlled line-selective split sequence generator 11 that delivers a split sequence signal sp and a split permission signal se (FIGS. 3 and 4), which is converted to a three-level additional data signal of the levels 0, + and - in digital-analog converter 8. 
     The non-band-limited additional data signal contained at the output of digital-analog converter 8 is limited to the video band width by the effect of transmission filter 9 and is superimposed on the FBAS signal of the first line type or another line type in adder 10. The data-controlled line-selective split sequence generator 11 is controlled by the data to be transmitted, which are polled by the data clock stored in signal EPROM 3.2, and by the time control signals for frame pulse BI, line pulse ZI and system clock pulse ST of transmitter synchronization 12. 
     Frame pulse BI occurs at the start of each frame, and pulse ZI occurs at the start of each line. The frame pulse rate and the system clock rate are linked together in a phase-locked manner. Beginning with the frame pulse, lines from 0 to 624 are counted in the line counter. Since a number of lines have a similar structure with regard to the additional data signals to be inserted, the address range of signal EPROM 3.1 is addressed with the line number by the line type EPROM 3.2, and signal EPROM 3.1 generates a signal insertion that fits into the respective line structure. 
     In FIG. 3, the signals for six data symbols have been inserted at the bottom of the synchronization pulse, the signals for three data symbols have been inserted downstream from the color burst, and the signal for one data symbol has been inserted on the front porch. 
     For the type of line shown in FIG. 4, the signals for six data symbols have been inserted at the bottom of the synchronization pulse, the signals for eight data symbols have been inserted on the back porch, and the signal for one data symbol has been inserted on the front porch. Since a number of lines have identical structures, identical signal structures can be stored in signal EPROM 3.1. At the same time, the system clock pulse edges ST are counted over time by the clock pulse counter, e.g., 576 clock pulses per line. With system clock pulse ST and the choice of line type ZT, the signals previously stored in signal EPROM 3.1, namely the split permission se, split signal sp and data clock pulse are read out chronologically, system clock pulse edge by system clock pulse edge, and sent to digital-analog converter 8. 
     The possibility of being able to fit the information-carrying additional data signals exactly into the desired time intervals of the entire frame is based on the high-precision derivation of frame pulse BI, line pulse ZI and system clock pulse ST from the FBAS signal supplied to transmitter synchronization 12. The core of the transmitter synchronization is a synchronous processor, e.g., circuit TDA 9257 which derives a processor clock pulse of 27 MHz, a horizontal signal HS and a vertical signal VS with a jitter of less than 5 ns from the FBAS signal for further processing. These signals are linked together sequentially and by combination in these modules, namely the scaler for system clock pulse 6, frame pulse detector 5 and line pulse detector 7, in such a way as to obtain a system clock pulse ST of 9 MHz, for example, with 576 system clock pulse edges per television line signal, line pulse ZI, which marks each first-of-line edge of system clock pulse ST, and frame pulse signal BI, which marks each first-of-frame flank of the system clock pulse. 
     In addition to the polling of split permission signal se and split signal sp, which is ultimately time-controlled, signals BI, ZI and ST are available for adapting between the output speed of the data source whose data are to be transmitted and the data clock pulse of the data-controlled line-selective split sequence generator with a FIFO circuit, for example. 
     FIG. 2 shows the additional data receiver to be operated on the receiving end, where the processing of the signals in the receiver and the signals for controlling it are shown in FIG. 5 for the first type of line and in FIG. 6 for another type of line. This additional data receiver consists of receiver synchronization 21, line-selective reference split sequence generator 20 and the analog input part which is in turn composed of clamp circuit 13, limiter amplifier/offset correction 14, analog-digital converter 14 and digital correlator 19. The clamping can be activated by the counting of the clock pulse edges in the line by clock pulse counter 1 and read out of the corresponding memory contents from the control and signal EPROM 3.1. After the sum of the FBAS signal and the additional data signal has passed clamp circuit 13, amplification, limiting and offset correction are performed in limiter amplifier 14 in such a way that the converter range of the downstream analog-digital converter is utilized optimally during the presence of the additional data signals without any overloads (FIGS. 5 and 6). 
     This offset correction is controlled with signal offset correction ok which is read out of the control and signal EPROM 3.1. The sequence of samples goes in a certain word width to digital multiplier 16, where the output signal of the limiter amplifier is multiplied by the reference signal in the form of the supplied split permission signal se and split sequence signal sp in digital form. 
     The product is then integrated by digital integrator 17. The result of the integration can be seen in analog representation in FIGS. 5 and 6. The integrator is enabled by integration permission signal ie, which is read out of the control and signal EPROM 3.1, reset by the integrator reset signal ir, and the decision is made by the transfer pulse u. Except for the fact that only one reference split sequence signal with sp and se and the above-mentioned control signals ie, ir, u, ki and ok are needed for the reception process, the line-selective reference split sequence generator 20 corresponds to the data-controlled line-selective split sequence generator 11. 
     In addition to the ultimately regenerated data and the regenerated data clock pulse read out of control and signal EPROM 3.1 (FIGS. 5 and 6), BI, ZI and ST signals are available for adjusting the data output rate of the additional data receiver to the data clock pulse of the downstream data sink with a FIFO circuit, for example. 
     For transmitter synchronization, the frame pulse BI, line pulse ZI and system clock pulse ST are obtained from the FBAS signal by the interaction of synchronous processor 4, the scaler for system clock pulse 6, frame pulse detector 5 and line pulse detector 7, thus permitting accurate positioning of the additional data signal within the total television frame with an accuracy greater than 5 ns. 
     In the data-controlled line-selective split sequence generator 20, the total television frame with a time reference of 111.1 ns, for example, can be addressed completely using the frame pulse BI, line pulse ZI and system clock pulse ST, a line counter 2 and a clock pulse counter 1, so the additional data signals which can be selected at will or programmed by EPROM can be fitted into the television frame structure. If the line type is selected by line counter 2 with the help of a line type EPROM 3.2, the storage size for the signal part of the signal and control EPROM 3.1 can be reduced greatly. 
     For reception synchronization, frame pulse BI, line pulse ZI and system clock pulse ST are generated from the FBAS signal through the interaction of synchronous processor 4, scaler for system clock pulse 6, frame pulse detector 5 and line pulse detector 7, thus permitting a chronologically accurate positioning of the reference signal for the correlation reception within the total television frame with an accuracy greater than 5 ns. 
     The total television frame in the line-selective reference split sequence generator can be addressed completely using the frame pulse BI, line pulse ZI and system clock pulse ST, a line counter 2 and a clock pulse counter 1, so the additional data signals, which can be selected at will and programmed by EPROM, can be received in the television frame structure by digital correlation receiver 19. 
     With the same precision, the control signals, namely clamping pulse ki, offset compensation ok, system clock pulse for AD conversion, split permission signal se, split signal sp, integration permission signal ie, integrator reset signal ir and transfer signal u, which are necessary for the input stages, the AD converter and digital correlation receiver, are generated. 
     Clamping circuit 13, which is ensured by means of an accurate time control by clamp pulse ki, permits further optimal processing of the mixture of FBAS signal and additional data signal. Limiter amplifier/offset compensation 14 amplifies this mixture in the input stages so that the FBAS level is raised to an average of 0 volt during the synchronization pulse, controlled by the offset compensation signal. According to the level of the additional data signals, there is such a gain here that the AD converter input converter range is optimally utilized, including possible noise. Limiting the amplifier protects the AD converter from destruction in these times because chrominance and luminance are transmitted. 
     The additional data is transmitted using biphase signals, so that transmission at a low error rate with additional data signal levels of a few mV is possible in reception by averaging due to integration, even if clamping and offset compensation are not accurate. 
     The programmability of the additional data transmission system permits simple adaptation to SECAM, NTSC, PAL and PALplus. 
     The frame pulse BI, line pulse ZI and system clock pulse ST are available on the transmitting end and also on the receiving end for rate adaptation between source and transmission system or sink and transmission system and for frame and overframe synchronization.