Abstract:
CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs while the second places the switches on the analog bias voltages inherent to a current controlled inverter.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application contains subject matter which is related to the subject matter of the following co-pending applications, each of which is assigned to the same assignee as this application, International Business Machines Corporation of Armonk, N.Y. Each of the below listed applications is hereby incorporated herein by reference in its entirety:  
         [0002]     “Power Supply Insensitive Delay Element”, Dreps et al, U.S. Ser. No. ______. filed concurrently herewith.  
         [0003]     “On-Chip Detection of Power Supply Vulnerabilities”, Sperling et al, U.S. Ser. No. ______ filed concurrently herewith. 
     
    
     TRADEMARKS  
       [0004]     IBM ® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. and other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.  
       BACKGROUND OF THE INVENTION  
       [0005]     1. Field of the Invention  
         [0006]     This invention relates to digital multiplexer circuits and particularly to noise insensitive multiplexer designs.  
         [0007]     2. Description of Background  
         [0008]     Before our invention there were many means by which the multiplexing of signals could occur. U.S. Pat. Nos. 5,598,115; 5,625,303; 5,646,558; 5,773,995 and patent application 2004/0008073 all show circuits in which transistor passgates are used to drive a common node. These designs suffer from high sensitivity to power supply noise perturbations, as the delay from input to output is directly proportional to the power supply value.  
       SUMMARY OF THE INVENTION  
       [0009]     The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a current controlled inverter structure incorporated into the basic multiplexer. The method of switching between the inputs is accomplished by creating high impedance nodes on the unselected paths. Two methods of creating this high impedance are detailed herein.  
         [0010]     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:  
         [0012]      FIG. 1  illustrates one example of two current controlled inverters connected at their output.  
         [0013]      FIG. 2  illustrates one example of creating a high impedance node using passgates on the data inputs.  
         [0014]      FIG. 3  illustrates one example of creating a high impedance node using passgates on the analog bias inputs. 
     
    
       [0015]     The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0016]     Referring now to  FIG. 1  of the drawings, a pair of current controlled inverters connected at their outputs is formed. The transistors  17  and  18  are connected as a simple inverter where nodes  30  and  32  are shorted to the primary data input IN 1 . The transistors  16  and  19  are connected as bias transistors where node  12  is the analog input BIASP and node  14  is the analog input BIASN. A second current controlled inverter formed by transistors  20 ,  21 ,  22  and  23  is connected in the same manner. Nodes  31  and  33  are shorted to the primary data input IN 2 , node  13  is connected to the analog input BIASP and node  15  is connected to the analog input BIASN. The output of the first inverter, denoted by node  24 , is shorted to the output of the second inverter, denoted by node  25 , and encompasses the primary output. Further details of the current controlled inverter and the generation of analog voltages BIASN and BIASP can be found in “Power Supply Insensitive Delay Element”, Dreps et al referenced above.  
         [0017]     The circuit detailed in  FIG. 1  will not multiplex between the two data inputs and will introduce significant distortion on the output. In order to select just one input, a high impedance must be created at the drains of the unselected transistors. To select IN 1  the high impedance must be created on the drains of transistors  21  and  22 . To select IN 2  the high impedance must be created on the drains of transistors  17  and  18 . One method is to short the unselected data input to a power supply, while another method is to short the analog bias voltage inherent to a current controlled inverter to a power supply. Both of these methods may be expanded for any number of inputs signals.  
         [0018]     Referring now to  FIG. 2  of the drawings, the current controlled inverters from  FIG. 1  are connected such that the inputs may be multiplexed to the output. Passgates  40 ,  41 ,  42 , and  43  are connected between their respective data inputs and transistor gate nodes  30 ,  31 ,  32 ,  33 . Switches  44 ,  45 ,  46  and  47  are connected such that they may short their respective transistor gate nodes to whichever voltage that turns off the transistor. For the p-type transistors this is the VDD power supply shown as node  11 . For the n-type transistors this is the ground node. When selecting the IN 1  data input, passgates  40  and  42  will pass the IN 1  input signal to nodes  30  and  32  respectively, while passgates  41  and  43  will block the IN 2  input signal from being passed to nodes  31  and  33  respectively. At the same time, switches  44  and  46  will remain open to allow the IN 1  input signal to propagate through and switches  45  and  47  will short the respective power supplies to nodes  31  and  33 . By shorting node  31  to the power supply  11  and shorting node  33  to ground a high impedance is created at the drains of transistors  21  and  22 . This allows the signal from IN 1  to propagate to the output without distortion. This operation can be reversed to select the IN 2  input signal instead of IN 1 . It may also be expanded to include any number of other data input signals.  
         [0019]     Referring now to  FIG. 3  of the drawings, the current controlled inverters from  FIG. 1  are connected in another manner such that the inputs may be multiplexed to the output. Passgates  50 ,  51 ,  52 , and  53  are connected between their respective analog bias voltage inputs and transistor gate nodes  12 ,  13 ,  14 ,  15 . Switches  54 ,  55 ,  56  and  57  are connected such that they may short their respective transistor gate nodes to whichever voltage that turns off the transistor. For the p-type transistors this is the VDD power supply shown as node  11 . For the n-type transistors this is the ground node. When selecting the IN 1  data input, passgate  50  will pass the BIASP analog input signal to node  12  and passgate  52  will pass the BIASN analog input signal to node  14 . Passgates  41  and  43  will block their respective analog bias input signal from being passed to nodes  13  and  15  respectively. At the same time, switches  54  and  56  will remain open to allow the analog bias input signals to pass through and switches  55  and  57  will short the respective power supplies to nodes  13  and  15 . By shorting node  13  to the power supply  11  and shorting node  15  to ground a high impedance is created at the drains of transistors  20  and  23 . Since transistors  20  and  21  as well as transistors  22  and  23  are in series the high impedance is also seen at the drains of transistors  22  and  23 . This allows the signal from IN 1  to propagate to the output without distortion. This operation can be reversed to select the IN 2  input signal instead of IN 1 . It may also be expanded to include any number of other data input signals.  
         [0020]     Referring now to  FIGS. 2 and 3 , commonality features between the two designs are evident by the use of identical passgates  40 ,  41 ,  42 ,  43  and  50 ,  51 ,  52 ,  53 . Switches  44 ,  45 ,  46 ,  47  and  54 ,  55 ,  56 ,  57  are also common between the two designs. The multiplexing method may therefore be selected by moving the switching design elements.  
         [0021]     The capabilities of the present invention can be implemented in hardware. The circuit provided by the hardware can be provided by a design service of IBM and others to enable creation and use of the circuit provided by the hardware.  
         [0022]     While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.