Abstract:
A method for monitoring the operating condition of an inductive load including applying a control pulse to a control line coupled to the inductive load, generating a verification pulse indicating the operating condition of the inductive load, applying the verification pulse to the control line and sampling the verification pulse to determine the operating condition of the inductive load.

Description:
This application is a continuation of application Ser. No. 07/923,923, filed as PCT/EPas PCT/EP91/0023, Feb. 6, 1991, published as WO91/15777, Oct. 17, 1991, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to monitoring valve control lines for detecting faults and, more particularly, a process for monitoring a valve and its associated control line for detecting faults in either the valve or the control line. 
     2. Description of the Related Art 
     Processes for monitoring inductive loads, such as valves, for faults are known from DE-Al 0 249 448 and the DE-Al 30 07 464. In the latter specification, control and checking are carried out by the same control unit, but there are two separate lines provided for the two functions. 
     In control systems such as anti-locking systems, automatic slip control etc., the solenoid valves are arranged at a distance from the controller, and are connected with it in each case via a control line. 
     SUMMARY OF THE INVENTION 
     The present invention provides a process with which valves and their associated control lines can be monitored without an additional checking line for checking that both are free of faults. This monitoring is carried out via the control line and the control circuit. In order to reduce the number of lines, triggering and error message transmission are transmitted on one line. Fault diagnosis is possible via a defined impulse sequence. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is explained in greater detail on the basis of the design examples and diagrams represented in the following figures: 
     The figures show: 
     FIG. 1 shows representative waveforms of signals associated with controlling a solenoid valve. 
     FIG. 2 shows a schematic block diagram of a first embodiment of the present invention. 
     FIG. 3 shows representative waveforms of signals associated with controlling an inductive solenoid and checking for faults according to the present invention. 
     FIG. 4 shows a schematic block diagram of a second embodiment of the present invention. 
     FIG. 5 shows representative waveforms of signals associated with controlling an inductive solenoid and checking for faults, and fault signals returned from the solenoid. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     For the invention, the cut-off peak, or inductive kickback, occurring when inductive loads are switched is a measure for the correct state of the high-level stage. If, for example, the inductance becomes smaller due to short-circuiting in the load or a short circuit in the coil, the time tx of the cut-off peak occurring after switching off alters. FIG. 1 shows on the one hand a waveform of current J in a switching process, e.g. of a valve, and secondly the corresponding voltage curve U A  with reference to point A in FIG. 2. 
     In FIG. 2, the solenoid valve 1 is triggered via an input terminal 2, an AND-gate 3, a high-level stage 4 including a Zener diode 5 and a battery 6. A computer triggers the valve at appropriate times for control purposes, and on the other hand also monitors the valve for faults via the same control line to be connected at 2. 
     In the case of a fault-free valve, at the end of the drive signal, in accordance with FIG. 1, the cut-off peak, or inductive kickback, represented there occurs with the height U Z  and width tx shown in the drawing. In FIG. 3a, the drive signal output from the computer is shown; FIG. 3b shows the signal appearing at terminal 2; FIG. 3c shows interrogation, or samples of the signal at terminal 2, impulses of the computer. In FIG. 3b, the duration tx of the cut-off peak is shown. With the occurrence of the cut-off peak, a comparator 7 with a predetermined reference voltage operates. With the aid of a time function element 8, with the time constant t (see FIG. 3b) and an AND-gate 9, the output signal of AND-gate 9 causes a signal to be input to an inverter 10 which corresponds to the impulse 11 shown in FIG. 3b. By way of the inverter 10 and a transistor 12, the impulse 11 is created at the terminal 2, the length of t 2  being conditioned by the cut-off peak or its decay below the reference voltage. In the case of a good valve, it is always the same impulse 11 which occurs, and which is thus a sign of a good valve. 
     During time t 1 , the computer scans, through the first of the impulses of FIG. 3c, the low-potential on the control line, and then, through the second impulse, the high-potential occurring through a cut-off peak of the correct width. The low-potential is scanned once again in order to obtain additional information in the case of possibly too wide cut-off peaks due to inductances switched in series, or due to other faults. It is important that the sequence is controlled by the triggering itself, and that no additional interrupt loading occurs, and that only one line is required for triggering and acknowledgement. 
     In FIG. 4, a complete embodiment example is shown, the embodiment example of FIG. 2 being fully integrated. 
     Here the valve 1&#39; is triggered from terminal 2&#39; via an AND-gate 3&#39; and a switching transistor 20. The comparator 7&#39; corresponds to the comparator 7, the elements 9&#39; and 8&#39; correspond to the AND-gate 9 and the time element 8, respectively, and the elements 10&#39; and 12&#39; correspond to the inverter 10 and the transistor 12, respectively. 
     After switching off the drive signal in the case of a good valve a signal corresponding to the impulse 11 of FIG. 3b develops at terminal 2, produced by the output signal of the AND-gate 9&#39; arriving after time t 1  at the inverter 10&#39; and transistor 12&#39; via gates 21, 23 and 34. The AND-gate 21 is conducting, because the element 25 reacting to the falling edge of the drive signal, triggers a time element 26 with the time constant t 3  which is longer than tx. Where valve 1&#39; is good, the verification impulse 11&#39; shown in FIG. 5a occurs at the terminal. 
     FIG. 5 shows in FIG. 5x a drive impulse ending at t 4 , in FIG. 5y the sampling pulses, and in FIG. 5a-5e various acknowledgement signals (recognition signals), or waveforms generated in cases of different valve faults. 
     If a short circuit in coil occurs in valve 1&#39;, then the inductance is reduced and thus also the level of the induced voltage after transistor 20 turns off; thus the time is reduced in which the induced and limited voltage, i.e., the inductive kickback, is greater than the reference voltage of the comparator 7&#39;. If this time is smaller than the time of the time element 8&#39;, then the output of gate 9&#39; remains low. 
     After the end of the time of the time constant element 26, an element 27 sends a pulse to the input of the AND-gate 28. Due to the inverted input of an OR-gate 30, its output is a 1. Thus, the bistable element 29 is set, the `Q` output of which then brings the terminal 2&#39; to a high signal via the OR gate 24, inverter 10&#39; and transistor 12&#39;. The distinctive curve shown in FIG. 5e then results. 
     If a short-circuit occurs in valve 1&#39; during triggering, then the voltage across resistor 31 is greater than the voltage level of a reference voltage of the comparator 32. Thus, a bistable element 33 is tripped, the Q-output of which then blocks the AND-gate 3&#39; and also transistor 20. 
     At the end of triggering, the time element 26 is again triggered which causes the AND-gate 21 to conduct. Via an OR-gate 35 and the elements 8&#39; and 9&#39;, after the end of t 1 , a high signal is created which also brings about a high-signal at terminal 2&#39; via the elements 21, 23, 10&#39; and 12&#39;. The AND-gate 28 is enabled by the tripped bistable element 33, so that with the end of the time constant of the time element 26, it switches and sets the bistable element 29. This means that the terminal remains on a high signal, and the curve of FIG. 5c is thus produced. 
     If a line break, or open, occurs at valve 1&#39;, then the voltage change caused by it is detected by a comparator 37. This immediately brings about a high signal at the terminal 2&#39; via the elements 24, 10&#39; and 12&#39;. This also happens if the line break occurs during triggering (see FIG. 5b). 
     By using of a comparator 38, a temperature rise at transistor 20 can also be detected by using a well-known temperature detection device 39 coupled to comparator 38. The bistable element 33 is set and the triggering prevented by way of the AND-gate 3&#39;. 
     Due to the output signal of the comparator 38 and the output signal existing after the end of triggering, the AND-gate 22 is conducting. Its output signal brings about a high signal at the terminal 2&#39; via the elements 23, 24, 10&#39; and 12&#39;. With its output signal, the AND-gate 34 triggers the time element 8&#39;; after the end of the time constant of the time element 8&#39;, the AND-gate 9&#39; sends a signal to the AND-gate 21, which thus becomes conducting. The exclusive OR-gate 24 is thus blocked and thus a low signal is brought about at the terminal 2&#39;. This lasts until at the end of t 3  of time element 26, the AND-gate 21 is again blocked. Simultaneously, a high signal is again brought about at the terminal 2&#39; via the elements 27-29, 24, 10&#39; and 12&#39;. The curve shown in FIG. 5d results. 
     It can be seen from FIG. 5 that in cases of possible faults at the valve, recognition signals which deviate from the verification signal of FIG. 5a, and which identify the fault which has occurred, are created on the control line which can be sampled and recognised by the pulses of FIG. 3c. 
     The reset switching and the supply have not been described in further detail.