Abstract:
An integrated circuit allows for the correction of distortion at an input of a sampling network. The integrated circuit contains a first bootstrap circuit to drive a sampling network transistor and a second bootstrap circuit to separate the back-gate terminal of the transistor from a voltage input by a resistance inserted in series. The presence of the inserted resistance counteracts the effect of the nonlinear back-gate capacitance on the distortion at the input.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a sampling network. The present invention further relates to an integrated circuit that corrects a distortion at the input of a sampling network. The present invention further relates to a circuit that reduces nonlinearity in a sampling network resulting from a back-gate capacitance of a MOSFET device in the network. 
       BACKGROUND INFORMATION 
       [0002]    Sampling networks may be used for a variety of uses, such as digital filtering, analog-to-digital conversion, digital-to-analog conversion, or sampling inputs with sample and hold (or track and hold) circuits. In a particular sampling network, a plurality of input signals are sampled onto an array of capacitors, sample and hold circuits, or track and hold circuits, depending on the configuration of the network. The stored signal may then be converted or filtered based on the design of the network. 
         [0003]    Sampling networks have a number of drawbacks which do not allow for ideal operation. An example of one such drawback is distortion that is produced from various circuit elements within the network. In a sampling network that uses track and hold circuits, the input switch may be an initial source of distortion for the sampling network. This may occur in the network regardless of whether the circuit is in a track phase (where the tracking capacitors are being charged) or the circuit is in the hold phase (where the charge is held on the capacitors). 
         [0004]    Additionally, all sampling networks, regardless of the configuration, have other sources of distortion. A particular high source of distortion in sampling networks occurs at the voltage sampled at a sampling capacitor. This is generally a result of the presence of a nonlinear resistor used in the sampling network which may be voltage dependent and thus cause distortion at the output of a sampled capacitor. Nonlinear parasitic capacitance may additionally contribute to the distortion at the sampled capacitor. One method to correct this distortion is to use a bootstrap circuit to “bootstrap” the devices in the sampling network. A bootstrap circuit that is connected to an input switch can pull up the current through the input switch and keep the gate-to-source and the back-gate-to-source voltages constant, and effectively eliminate a variation of the resistance of the nonlinear resistor from varying the input voltage. The use of a bootstrap circuit has the additional benefit of causing a reduction in a variation of a switch resistor with the input voltage. 
         [0005]    The use of bootstrap circuits however, may lead to unwanted residual effects. For example, in a bootstrap circuit using MOSFET devices, bootstrapping a back-gate of a MOSFET device would lead to an unwanted junction capacitance at the input of the sampling network. This additional capacitance introduces nonlinearity at the input that may degrade the performance of the sampling network. Thus there remains a need in the art, for an integrated circuit which may improve linearity at the input of a sampling network, without leading to additional distortion. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is a diagram of the integrated circuit with multiple bootstrap circuits coupled to a sampling network. 
           [0007]      FIG. 2  is an equivalent diagram of the integrated circuit coupled with a sampling network. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    The subject invention will now be described in detail for specific preferred embodiments of the invention, it being understood that these embodiments are intended only as illustrative examples and the invention is not to be limited thereto. 
         [0009]    Nonlinearity and distortion in a sampling network may be overcome by an integrated circuit that introduces additional series resistance into a sampling network. Embodiments of the present invention provide a pair of bootstrap circuits which may be coupled to a sampling network (such as an analog to digital converter), and a resistive element which may be connected between the input and a back-gate switch of the sampling network. 
         [0010]      FIG. 1  illustrates an integrated circuit of the present invention. Integrated circuit  100  may contain a sampling network  120  coupled to bootstrap circuit  110 . Sampling network  120  may contain a transistor  130  and a sampling capacitor  140 . Transistor  130  may be any three-terminal transistor such as an nMOS device. The gate of transistor  130  may be coupled to the output of bootstrap circuit  110 . The input of bootstrap circuit  110  may be connected to a voltage input terminal. For ease of illustration, the details of bootstrap circuit  110  are not depicted. 
         [0011]    Transistor  130  may be coupled to the voltage input terminal at the source terminal of the transistor, tying the source to the input. The source terminal of transistor  130  may have a representative source impedance, Z s , which is not shown. As bootstrap circuit  110  is directly connected to the voltage input terminal, the output of the bootstrap circuit  110  will vary with a change to V in , and the gate-to-source voltage of transistor  130  may remain fixed. The drain terminal of transistor  130  may be coupled to capacitor  140 . Capacitor  140  may be connected to a switch  170 , which may connect and disconnect the sampling capacitor to ground. 
         [0012]    The back-gate of transistor  130  may be coupled to bootstrap circuit  150 . Bootstrap circuit  150  may contain two transistors,  152 ,  154 . Transistors  152  and  154  may also be any nMOS devices. The source terminals of transistors  152  and  154  may be coupled together and tied to the back-gate of transistor  130  of the sampling network. The drain terminal of transistor  152  may be coupled to ground, and the drain terminal of transistor  154  may be coupled to resistor  160 , which may be a variable resistor. Resistor  160  may be coupled to the voltage input terminal. In an embodiment, resistor  160  may be between 300 ohms to 1 kilohm. A resistance value that is significantly larger than 1 kilohm may actually degrade the performance of the sampling network and reduce an effectiveness of the bootstrapping of the back-gate by bootstrap circuit  150 . 
         [0013]    During a sampling phase, an input signal (V in ) is applied to the source terminal of transistor  130 . During this phase, the input signal is also applied to an input of bootstrap circuit  110  which may output a bootstrap voltage which may be greater than V in  to the gate terminal of transistor  130 . As the voltage of the gate terminal of may be greater than the voltage at the source terminal, the gate-to-source voltage (“V GS ”) of transistor  130  may be greater than a threshold voltage (“V TH ”), and transistor  130  may turn on. When transistor  130  is on, a channel is open between the drain and the source of the transistor, and the input signal may be applied to capacitor  140 . Switch  170  may close, connecting a bottom plate of capacitor  140  to ground. 
         [0014]    Transistor  134  may also turn on and operate in a linear region when the input signal is applied. Alternately during this phase, transistor  132  may be off. When transistor  134  is on, resistor  160  may be connected to the back-gate of transistor  130 . Resistor  160  may isolate the back-gate from the input signal and from the source terminal of transistor  130 . 
         [0015]    When the capacitor plates of capacitor  140  have a differential voltage equal to V in , switch  170  may open. During this disconnecting phase, the voltage at the drain terminal of transistor  130  may be equal to V in  and the drain-to-source voltage may be zero. Bootstrap circuit  110  may output a lower voltage to transistor  130 , where the gate-source voltage may be less than the threshold voltage. Transistor  130  may turn off, disconnecting capacitor  140  from the input. 
         [0016]    During this disconnecting phase, transistor  134  may turn off, disconnecting the back-gate of transistor  130  from the input signal. Transistor  132  may turn off, connecting the back-gate of transistor  130  to ground. 
         [0017]    The insertion of resistor  160  between the voltage input terminal and bootstrap circuit  150  may decrease the nonlinearity at the voltage input during operation, which is created by the nonlinear capacitance, C P , in the back-gate of transistor  130 . This may be demonstrated by modeling the input voltage in terms of transistor  130  and resistor  160 , which may be represented by equation (i): 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     in 
                   
                   = 
                   
                     
                       
                         V 
                         s 
                       
                        
                       
                         
                           Z 
                           L 
                         
                          
                         
                           ( 
                           
                             1 
                             + 
                             
                               
                                 sC 
                                 p 
                               
                                
                               R 
                             
                           
                           ) 
                         
                       
                     
                     
                       
                         ( 
                         
                           
                             Z 
                             s 
                           
                           + 
                           
                             Z 
                             L 
                           
                         
                         ) 
                       
                        
                       
                         [ 
                         
                           1 
                           + 
                           
                             
                               sC 
                               p 
                             
                              
                             
                               ( 
                               
                                 
                                   ( 
                                   
                                     
                                       
                                         Z 
                                         s 
                                       
                                        
                                       
                                         Z 
                                         L 
                                       
                                     
                                     
                                       
                                         Z 
                                         s 
                                       
                                       + 
                                       
                                         Z 
                                         L 
                                       
                                     
                                   
                                   ) 
                                 
                                 + 
                                 R 
                               
                               ) 
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   i 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Z L  is the impedance of sampling capacitor  160  and switch  170 , Z s  is the source impedance of transistor  130 , V s  is the source voltage of transistor  130 , R is the resistance of resistor  160 , and C p  is the back-gate nonlinear capacitance of transistor  130  scaled by a factor s. 
         [0018]    The relative distortion of the input voltage may further be modeled by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         δ 
                          
                         
                             
                         
                          
                         
                           V 
                           in 
                         
                       
                       
                         V 
                         in 
                       
                     
                     = 
                     
                       
                         
                           - 
                           s 
                         
                          
                         
                             
                         
                          
                         δ 
                          
                         
                             
                         
                          
                         
                           
                             C 
                             p 
                           
                            
                           
                             ( 
                             
                               
                                 
                                   Z 
                                   s 
                                 
                                  
                                 
                                   Z 
                                   L 
                                 
                               
                               
                                 
                                   Z 
                                   s 
                                 
                                 + 
                                 
                                   Z 
                                   L 
                                 
                               
                             
                             ) 
                           
                         
                       
                       
                         
                           ( 
                           
                             1 
                             + 
                             
                               s 
                                
                               
                                   
                               
                                
                               
                                 C 
                                 p 
                               
                                
                               R 
                             
                           
                           ) 
                         
                          
                         
                           [ 
                           
                             1 
                             + 
                             
                               s 
                                
                               
                                   
                               
                                
                               
                                 
                                   C 
                                   p 
                                 
                                  
                                 
                                   ( 
                                   
                                     
                                       ( 
                                       
                                         
                                           
                                             Z 
                                             s 
                                           
                                            
                                           
                                             Z 
                                             L 
                                           
                                         
                                         
                                           
                                             Z 
                                             s 
                                           
                                           + 
                                           
                                             Z 
                                             L 
                                           
                                         
                                       
                                       ) 
                                     
                                     + 
                                     R 
                                   
                                   ) 
                                 
                               
                             
                           
                           ] 
                         
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     where 
                      
                     
                         
                     
                      
                     
                       
                         δ 
                          
                         
                             
                         
                          
                         
                           V 
                           in 
                         
                       
                       
                         V 
                         in 
                       
                     
                   
                 
               
               
                 
                   ( 
                   ii 
                   ) 
                 
               
             
           
         
       
     
         [0000]    is the relative distortion of the input voltage, and δC p  is the distortion of the nonlinear capacitance of the back-gate of transistor  130 . 
         [0019]    As demonstrated by equation (ii), 
         [0000]    
       
         
           
             
               δ 
                
               
                   
               
                
               
                 V 
                 in 
               
             
             
               V 
               in 
             
           
         
       
     
         [0000]    is inversely proportional to R, and therefore the relative distortion of the input voltage may decrease if the resistance of resistor  160  is increased. If resistor  160  is removed, R=0, and the relative distortion of the input voltage may be entirely dependent on the nonlinear back-gate capacitance C P , as shown in equation (iii): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       δ 
                        
                       
                           
                       
                        
                       
                         V 
                         in 
                       
                     
                     
                       V 
                       in 
                     
                   
                   = 
                   
                     
                       
                         - 
                         s 
                       
                        
                       
                           
                       
                        
                       δ 
                        
                       
                           
                       
                        
                       
                         
                           C 
                           p 
                         
                          
                         
                           ( 
                           
                             
                               
                                 Z 
                                 s 
                               
                                
                               
                                 Z 
                                 L 
                               
                             
                             
                               
                                 Z 
                                 s 
                               
                               + 
                               
                                 Z 
                                 L 
                               
                             
                           
                           ) 
                         
                       
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             sC 
                             p 
                           
                            
                           
                             ( 
                             
                               
                                 
                                   Z 
                                   s 
                                 
                                  
                                 
                                   Z 
                                   L 
                                 
                               
                               
                                 
                                   Z 
                                   s 
                                 
                                 + 
                                 
                                   Z 
                                   L 
                                 
                               
                             
                             ) 
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   iii 
                   ) 
                 
               
             
           
         
       
     
         [0020]    Absent resistor  160 , a distortion that is dependent on nonlinear back-gate capacitance C p  may worsen. An input with a high frequency may also adversely affect the distortion at the voltage input terminal of a typical sampling voltage, creating a capacitive high-pass filter, in the absence of resistor  160 . Inserting resistor  160  between the back-gate of transistor  130  and the voltage input terminal may convert the capacitive high-pass filter to a low-pass filter response. If R is increased and thus the distortion is decreased, the corresponding frequency may also decrease. 
         [0021]    Although resistor  160  may reduce distortion due to nonlinearity from the back-gate capacitance in transistor  130 , other sources of distortion at the input may occur. These sources may include a switch resistance variation that occurs between the gate voltage and the back-gate voltage of transistor  130 . These sources may be corrected directly by bootstrap circuit  110  and bootstrap circuit  150 . 
         [0022]    The technique described herein may be used in any other sampling network where any nonlinear capacitance is generated in a signal path from an input voltage.  FIG. 2  illustrates an equivalent diagram of the resistor insertion technique of the present invention embodied in  FIG. 1 . V s  may represent the voltage at the source of a MOSFET device in a sampling network and Z s  may represent the impedance at the source of the MOSFET device. The source impedance may be coupled to the input voltage. Resistor  160  may be coupled to the input voltage and to a nonlinear capacitance C p  of the MOSFET device. C p  may be connected to ground and may be in series with resistor  160 . Resistor  160  and nonlinear capacitance C p  may be connected in parallel with a load impedance Z L , where the load impedance may be the impedance of connected sampling capacitors. 
         [0023]    Several embodiments of the invention are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.