Abstract:
A simplified comparator circuit ( 10 ) having hysteresis and lower power requirements for its implementation. The circuit ( 10 ) includes 2 minimum-sized MOSFETs (MN 4 , MN 5 ) providing feedback from the circuit output to an input device (MN 1 ) body to produce hystereis, requiring very little power. This invention is suitable for applications not requiring a precisely set hysteresis magnitude.

Description:
FIELD OF THE INVENTION 
   The present invention is generally directed to MOSFET differential pair circuits, and more particularly to such circuits having hysteresis. 
   BACKGROUND OF THE INVENTION 
   Comparator circuits often are implemented with hysteresis from output to input to prevent noise on the input from causing multiple switches in output, or chatter. There have been many means devised to accomplish the hysteresis, such as using a resistor network from input to output dissipating power in at least one state. Examples of some are shown in U.S. Pat. No. 4,110,641 to Robert L. Payne entitled “CMOS Voltage Comparator with Internal Hysteresis” and U.S. Pat. No. 4,394,587 to McKenzie et al entitled “CMOS Differential Comparator with Hysteresis”. Such previous solutions have required the addition of several devices creating a more complex design and requiring additional power. 
   SUMMARY OF THE INVENTION 
   The present invention achieves technical advantages as a simplified comparator circuit having hysteresis and lower power requirements for its implementation. The circuit includes 2 minimum-sized MOSFETs providing feedback from the circuit output to an input device&#39;s body to produce hystereis, requiring very little power. This invention is particularly suitable for applications not requiring a precisely set hysteresis magnitude. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic of an improved simplified comparator circuit having hysteresis according to the present invention; and 
       FIG. 2  is a timing diagram of the circuit of  FIG. 1  showing the hysteresis and low static power. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1  is the schematic of a new comparator  10  with hysteresis according to a preferred embodiment of the present invention. Transistors MN 1  and MN 2  form a input differential pair. Transistor MN 3  provides a tail current, and transistors MP 1  and MP 2  provide a mirror of transistor MN 2 &#39;s drain current. 
   At balance, when voltages at inputs VINP and VINM are equal, currents in transistors MN 1  and MP 1  will be equal and the output at transistor MP 0 &#39;s drain will be at an intermediate voltage between VCC and GND. If input VINP is slightly higher than input VINM, then the balance will be disturbed and the output OUT will go high. Any noise at the inputs near this balance point will cause the output OUT to reflect that same noise gained up. 
   In order to remove this noise at the output OUT, it is desirable that once the output OUT goes high the first time, hysteresis modifies the input threshold such that the input differential voltage needs to drop considerably before reaching the new input threshold. This threshold change needs to be outside the range of expected input noise. 
   According to one embodiment of the present invention, the back gates of transistors MN 1  and MN 2  are nominally tied to GND. The back gate of transistor MN 2  is tied directly to GND, while the back gate of transistor MN 1  is tied to GND through intermediate transistor MN 4  providing a pulldown of 10 μA. Transistor MN 4  is selectively enabled by a control signal CTRL, which CTRL signal is a bias line to define the DC currents in MN 0 , MN 3  and MN 4 . Control signal CTRL is at GND potential when the comparator is biased off, and it is about 1V when the comparator is biased on. This pull-down current responsively goes to zero when transistor MN 1 &#39;s back gate is pulled down to GND. This condition exists when the input differential voltage is negative (VINP&lt;VINM), the output OUT is low and transistor MN 5  is off, as shown in  FIG. 2 . 
   Once the input differential voltage exceeds zero (VINP&gt;VINM), the output OUT goes high, transistor MN 5  consequently turns on and pulls transistor MN 1 &#39;s back gate voltage to that of its source. This, in-turn, advantageously causes the threshold of transistor MN 1  to reduce compared to if its back gate was tied directly to GND. This threshold shift is the amount of hysteresis seen at the input VINP/VINM, and notably is a function of the body effect of the NMOS devices MN 1  and MN 2  in a particular semiconductor manufacturing process, and the common-mode voltage at the inputs VINP/VINM at the threshold. In this embodiment of the present invention, there is about a 0.5 volt Hysteresis. 
   Advantageously, the simple MOSFET differential circuit  10  having hysteresis is accomplished with the addition of only two small NMOS devices MN 4  and MN 5 , and the only extra current is 10 μA, which current is most of the time off in applications that this comparator  10  may be used in, such as a delay circuit involving the charging of a capacitor. Thus, the static power dissipation if very low. 
   Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.