Abstract:
A ring-type voltage-controlled oscillator with a good duty cycle for use in a PLL frequency synthesizer. The delay cell circuit used in the ring-type VCO comprises two first inverters, two resistance units, and a differential delay circuit. The inverters receive respective differential input signals and generate respective differential signals to resistance units. The differential delay circuit is coupled to the resistance units, generating differential output signals which are a delayed version of the differential input signals. The resistance units have a resistance value adjusted according to a resistance control voltage for controlling the strength of inverters so as to alter the time delay of the first and second differential output signals.

Description:
BACKGROUND 
   The invention relates to a ring-type voltage oscillator, and more particularly to a ring-type oscillator with improved duty cycle. 
   In recent years, the rapid growth of cellular communications systems has motivated an increasing demand for high performance integrated radio frequency (RF) components, such as frequency synthesizers. Phase-locked loop (PLL) techniques have been widely used in frequency synthesis to meet the stringent requirements of wireless standards. Among the function blocks in a PLL, VCO (Voltage-controlled oscillator) is a crucial circuit for determining the characteristics of a PLL. A desirable VCO offers a broad frequency band, realizes stable oscillation, and has low noise characteristics. 
   Ring-type oscillator is one kind of voltage-controlled oscillators. It is realized by cascading several delay cells to form a closed loop.  FIG. 1  is a block diagram of a conventional ring-type oscillator  10 . Operation of delay cells  12   a ,  12   b  and  12   c  in the ring-type oscillator is similar to an inverter and each delay cell generates a complement output signal with a time delay added to an input signal. The amount of time delay dictates the frequency at which the ring-type oscillator operates. The greater the delay time, the lower the frequency. That is, the frequency of the ring-type oscillator is inversely proportional to the total delay time of the delay cell in the loop. Ring-type oscillators provide advantages such as wide operating-frequency range and no extra processing step in a standard CMOS process, compared to other kind of VCOs, such as a LC-tank VCO. 
   However, VCOs including ring-type oscillators usually show poorer phase-noise performance, such as duty cycle distortion which may result in a poor bit-error rate and an inferior lock-in range of a clock and data recovery circuit. The duty cycle fluctuation of a ring-type oscillator may stem from the mismatch of transistors or extrinsic parameters, for example, device processing temperature, voltage and/or frequency of the frequency synthesizer. To solve this problem, a duty cycle correction circuit is usually added in a frequency synthesizer. However, this increases the power consumption and circuit complexity of the frequency synthesizer. Therefore, it is desirable to have a ring-type oscillator with an improved duty cycle. 
   SUMMARY 
   The present invention is generally directed to a ring-type voltage-controlled oscillator for use in a PLL frequency synthesizer. According to one aspect of the invention, the ring type voltage-controlled oscillator comprises a plurality of delay cell circuits, wherein each delay cell circuit has at least an output coupled to an input of a next sequential delay cell circuit in the ring-type voltage-controlled oscillator. One of the delay cell circuits comprises a first inverter, a second inverter, a first resistance unit, a second resistance unit and a differential delay circuit. The first inverter comprises a first NMOS transistor having a gate receiving a first differential input signal, a drain generating a first differential signal and a source coupled to a second power rail. The second inverter comprises a second NMOS transistor having a gate receiving a second differential input signal and a drain generating a second differential signal and a source coupled to the second power rail. The first resistance unit is coupled to the drain of the first NMOS transistor, and receives the first differential signal. The second resistance unit is coupled to the drain of the second NMOS transistor, and receives the second differential signal. The differential delay circuit is coupled to a first power rail for generating a first differential output signal to a first terminal and the first resistance unit, and a second differential output signal to a second terminal and the second resistance unit. The first and second resistance units have a resistance value adjusted according to a resistance control voltage for controlling the strength of the first and the second NMOS transistor so as to alter the time delay of the first and second differential output signal. 
   According to another aspect of the invention, a delay cell circuit for a ring-type voltage-controlled oscillator is disclosed. The delay cell circuit comprises a first inverter, a second inverter, a first resistance unit, a second resistance unit and a differential delay circuit. The first inverter comprises a first NMOS transistor having a gate receiving a first differential input signal, a drain generating a first differential signal and a source coupled to a second power rail. The second inverter comprises a second NMOS transistor having a gate receiving a second differential input signal and a drain generating a second differential signal and a source coupled to the second power rail. The first resistance unit is coupled to the drain of the first NMOS transistor, and receives the first differential signal. The second resistance unit is coupled to the drain of the second NMOS transistor, and receives the second differential signal. The differential delay circuit is coupled to a first power rail for generating a first differential output signal to a first terminal and the first resistance unit, and a second differential output signal to a second terminal and the second resistance unit. The first and second resistance units have a resistance value adjusted according to a resistance control voltage for controlling the strength of the first and the second NMOS transistor so as to alter the time delay of the first and second differential output signal. 

   
     DESCRIPTION OF THE DRAWINGS 
     The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which: 
       FIG. 1  is a block diagram of a conventional ring-type oscillator. 
       FIG. 2  is a block diagram of a ring-type voltage-controlled oscillator in accordance with an embodiment of the invention. 
       FIG. 3  is a schematic diagram of a delay cell circuit for the ring-type voltage-controlled oscillator of  FIG. 2  in accordance with an embodiment of the invention. 
       FIG. 4  is a block diagram of a ring-type voltage-controlled oscillator in accordance with another embodiment of the invention. 
       FIG. 5  is a schematic diagram of a delay cell circuit for the ring-type voltage-controlled oscillator of  FIG. 4  in accordance with another embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   With reference to  FIG. 2 , a ring-type voltage-controlled oscillator  20  in one embodiment of the present invention is illustrated. The ring-type VCO  20  includes four identical delay cell circuits  22   a ,  22   b ,  22   c  and  22   d , each having two differential input signals V in  and V in−  and two differential output signals V out  and V out− . Differential output signal V out  of delay cell circuit  22   a  is fed to the positive input of delay cell circuit  22   b , and then to the next stage in a similar fashion. Differential output signal V out  of delay cell circuit  22   d , the last stage of the ring-type VCO  20 , is fed back to the negative input of delay cell circuit  22   a . Similarly, differential output signal V out−  of delay cell circuit  22   a  is fed to the negative input of delay cell circuit  22   b  and then to the next stage in the similar fashion. Differential output signal V out−  of delay cell circuit  22   d , the last stage of the ring-type VCO  20 , is fed back to the positive input of delay cell circuit  22   a . As such, the differential output signals V out  and V out−  in the ring-type VCO  20  will switch between HIGH and LOW states. Each delay cell circuit  22   a ,  22   b ,  22   c  and  22   d  causes a 45° phase shift, so the phase shifts relative to V in  of delay cell circuit  22   a  are as follows. Differential output signal V out  of delay cell circuit  22   a  is shifted 45°, signal V out  of delay cell circuit  22   b  is shifted 90°, signal V out  of delay cell circuit  22   c  is shifted 135°, and signal V out  of delay cell circuit  22   d  is shifted 180°, fed back to the delay cell circuit  22   a . Consequently, the differential output signal V out−  of delay cell circuit  22   a  is shifted 225°, signal V out−  of delay cell circuit  22   b  is shifted 270°, signal V out−  of delay cell circuit  22   c  is shifted 315°, and signal V out−  of delay cell circuit  22   d  is shifted 360° (ie. 0°). The outputs of the ring-type VCO  20  thus incorporate two output signals which switch between High and LOW sates. Therefore, controlling the delay time in each delay cell circuit by a control voltage V cont  can obtain an oscillating output clock of VCOs with desired frequency. 
     FIG. 3  shows the schematic diagram of delay cell circuit  300  for the ring-type VCO  20  of  FIG. 2  in accordance with an embodiment of the invention. Recalling that delay cell circuits  22   a ˜ 22   d  of the ring-type VCO  20  in  FIG. 2  are the same, the delay cell circuit  300  corresponds to any of delay cell circuits  22   a ˜ 22   d . Delay cell circuit  300  comprises four inverters  302 ,  304 , 312  and  314 , two resistance units  306  and  308 , and a differential delay circuit  310 . Moreover, delay cell circuit  300  includes two differential input signals V in  and V in−  and two differential output signals V out  and V out−  as delay cell circuits  22   a ˜ 22   d  in  FIG. 2 . 
   Inverters  302 ,  304 ,  312  and  314  each consist of an NMOS transistor (N 1 , N 2 , N 3  and N 4  for inverters  302 ,  304 ,  312  and  314  respectively) connected in series, drain to drain, with a PMOS transistor (P 1 , P 2 , P 3  and P 4  for inverters  302 ,  304 ,  312  and  314  respectively). The sources of transistor P 1 ˜P 4  and N 1 ˜N 4  are connected to a power rail V DD  and to another power rail, preferably ground, respectively. Each transistor in inverter  302  and  312  (N 1 , N 3 , P 1 , P 3 ) has a common gate to receive the differential input signals V in . Similarly, transistors in inverter  304  and  314  (N 2 , N 4 , P 2 , P 4 ) have a common gate to receive the differential input signals V in− . The drain of transistor N 1  is connected to the resistance unit  306 , supplying a differential signal V out2−  while the drain of transistor N 2  is connected to the resistance unit  308 , supplying a differential signal V out2 . The drains of transistors N 3  and N 4  are connected to the differential delay circuit  310 , generating respective differential output signals V out−  and V out . 
   Resistance units  306  and  308  comprise two NMOS transistors, N 5  and N 6  respectively. Transistors N 5  and N 6  have sources coupled to the drains of transistors N 1  and N 2  respectively and gates receiving a resistance control voltage V cont , acting as varying resistors to tune the time delay of the delay cell circuit  300 . The drains of transistors N 5  and N 6  are connected to the differential delay circuit  310  and the drains of transistors N 3  and N 4  respectively. 
   Differential delay circuit  310  comprises two cross-coupled PMOS transistors P 5  and P 6 . Transistor P 5  comprises a gate coupled to the drain of transistor P 6 , receiving a differential output signal V out  and also to the drain of transistor N 6 . Transistor P 6  comprises a gate coupled to the drain of the transistor P 5 , receiving a differential output signal V out−  and also to the drain of transistor N 5 . Both the sources of transistors P 5  and P 6  are coupled to the power rail V DD . Thus differential output signals of delay cell circuit  300 , V out−  is contributed by the differential delay circuit  310 , the inverter  312  and resistance unit  306  and V out  is contributed by the differential delay circuit  310 , the inverter  314  and resistance unit  308 . 
   The operation of the delay cell circuit  300  is described as follows, assuming the current state of input signal V in  is 0V (LOW), and signal V in−  is V DD  (HIGH), thus the differential output signal V out−  is V DD  (HIGH) and signal V out  is 0V (LOW). When the input signal V in  is transited from 0V to V DD , that is, the input signal V in−  is transited V DD  to 0V, signals V in  and V in−  are fed to inverters  312 , 302  and inverters  304 , 314  respectively. The transistor P 3  is turned off and transistor N 3  is turned on, starting discharge of the negative output of delay cell circuit  300 . Since the transistor P 5  was turned on in previous state (i.e. when the input signal V in  was 0V), the transistor N 3  then competes with transistor P 5  to pull the output signal V out −  down when transistor P 5  is pulling it up. The transistor P 5 , however, is turned off when the voltage at gate is charged over a certain voltage by transistor P 4  because transistor P 4  is turned on when signal V in−  is transited to 0V. The transistor N 3  thus discharges the negative output of the delay circuit  300 , trying to pull the signal V out−  to 0V. Meanwhile, the signal V out2−  generated by the inverter  302  is also pulled to 0V by transistor N 1 . The transistor N 5  acts as a voltage-controllable resister, operatively discharging the voltage at the negative output of delay circuit  300 , thereby is generating a tunable current from drain to source in transistor N 5  to help pull the state of signal V out−  to 0V. 
   Conversely, the transistor P 4  is turned on and transistor N 4  is turned off when signal V in−  is transited from V DD  to 0V. Since the transistor P 6  was turned off in previous stage when the input signal V in−  was V DD , the transistor P 4  charges the positive output of the delay circuit  300 , trying to pull the signal V out  up. The transistor P 6  is turned on when the voltage at gate is less than a certain voltage, starting to pull the signal V out  up. Meanwhile, the signal V out2  generated by the inverter  304  is also pulled to V DD  by transistor P 2  through another voltage-controllable resistor, the transistor N 6 . The drain and source of transistor N 6  are thus reversed to draw a current to charge the positive output of the delay cell circuit  300 , helping to pull the signal V out  up to V DD . 
   The control voltage V cont  of resistance units  306  and  308  is controlled to adjust the driving strengths of the inverters  302  and  304  respectively, thereby controlling the impedance of transistors N 5  and N 6  by voltage V cont . When the control voltage V cont  is high, charge or discharge of outputs of inverter  312  and  314  is faster. When voltage V cont  is Low, charge or discharge is slower. With the resistances units  306  and  308  and the inverters  302  and  304 , the transition of the delay cell circuit  300  is thus short and the delay time is controlled. Utilizing such delay cell circuit in a ring-type VCO, the duty cycle of the output clock can be improved and a good duty cycle such as 50% can be obtained. 
     FIG. 4  illustrates another embodiment of the invention wherein four delay cell circuits  44   a ˜ 44   b  form a ring-type VCO  40 . Each delay cell circuit in the ring-type VCO  40  has four differential inputs, where V inP  and V inP−  is a pair of differential input signals while V inN  and V inN−  is another pair. The input signal V inP  is 45° faster than signal V inN  while signal V inP−  is the same to signal V inN− . That is, when the signal V inN  is in Q45 (phase 45°), the signal V inP  is in Q0 (phase 0°). The operation of the ring-type VCO  40  is described, accompanied by  FIG. 5  as follows. 
     FIG. 5  shows a schematic diagram of delay cell circuit  500  of the ring-type VCO  40  in  FIG. 4  in accordance with another embodiment of the invention. The delay cell circuit  500  is similar to delay cell circuit  300  except for the PMOS and NMOS transistors in the inverters receiving different differential input signals. In delay cell circuit  500 , PMOS transistors P 1  and P 3  receive a differential input signal V inP  and NMOS transistors N 1  and N 3  receive a differential input signal V inN . Furthermore, PMOS transistors P 2  and P 4  receive a differential input signal V inP−  and NMOS transistors N 2  and N 4  receive a differential input signal V inN− . Normally, PMOS transistors are slower than NMOS transistor. However, as mentioned, the input signals V inP  and V inP−  in the ring-type VCO  40  which utilizes the delay cell circuit  500  in  FIG. 5  are 45° faster than signals V inN  and V inN− . Thus, the PMOS transistors in delay cell circuit  500  can be triggered earlier and the ring-type VCO can achieve a good duty cycle under most operating frequencies and voltage supplies. 
   While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.