Abstract:
A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to the data processing field, and more particularly, relates to a method, system and computer program product for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system. 
       DESCRIPTION OF THE RELATED ART 
       [0002]    Modern computer systems typically are configured with a large amount of memory in order to provide data and instructions to one or more processors in the computer systems. Main memory of the computer system is typically large, often many GB (gigabytes) and is typically implemented in DRAM. 
         [0003]    Bad memory cells are a common failure mechanism in system DRAM. Redundancy has been used for repair of a memory system of memory modules, such as Dual In-Line Memory Modules (DIMMs). Conventional redundancy arrangements can dramatically increase the overall cost of the memory subsystem. This redundancy is usually in the form of extra DRAM modules or DIMMs, and can often be too much for a majority of failures. 
         [0004]    A need exists for an effective mechanism for implementing repair or redundancy enabling the memory system to recover from single address or small range of address fails. It is desirable that such mechanism is provided without substantially increasing cost or system overhead. 
       SUMMARY OF THE INVENTION 
       [0005]    Principal aspects of the present invention are to provide a method, system and computer program product for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports error correcting code (ECC). Other important aspects of the present invention are to provide such method, system and computer program product substantially without negative effects and that overcome many of the disadvantages of prior art arrangements. 
         [0006]    In brief, a method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system with ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register. 
         [0007]    In accordance with features of the invention, the data register includes an alternative memory array. With the data register is provided in the DRAM, memory buffer or memory controller latencies are preserved, so that use of the AMA is substantially transparent to the system. An additional advantage is that by reducing the system overhead and cost normally associated with current redundancy implementations, the negative impact to the system is minimized. 
         [0008]    In accordance with features of the invention, the data register is used as a replacement of the failing address. In this case, the writes and reads go to or come from the register directly. A second way to use the register is to send all writes to both the DRAM and the data register. In this case, the register is used as a backup instead of replacement. Reads are sent to the DRAM and passes through if no error is detected. Should an error occur, the contents of the register are used, replacing the failing data from the DRAM. 
         [0009]    In accordance with features of the invention, redundant addresses in the DRAM optionally are used. DRAM commonly has predefined redundant addresses in DRAM arrays. The predefined redundant addresses are made available to the system and are invoked as needed and mapped to failing addresses. Another source for spare addresses is to allocate an address range in the normally available address space. The range of addresses is allocated to be used to replace failing addresses. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: 
           [0011]      FIG. 1  is a block diagram representation illustrating an example system for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with the preferred embodiment; 
           [0012]      FIG. 2  is a high level flow chart illustrating exemplary operations of the example system of  FIG. 1  for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with the preferred embodiment; 
           [0013]      FIG. 3  is a high level flow chart illustrating exemplary alternate memory array operations of the example system of  FIG. 1  for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with the preferred embodiment; 
           [0014]      FIG. 4  is a more detailed diagram illustrating example on-memory controller alternate memory array hardware for read operations in the example system of  FIG. 1  for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with the preferred embodiment; 
           [0015]      FIG. 5  is a more detailed diagram illustrating example on-memory controller alternate memory array hardware for write operations in the example system of  FIG. 1  for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with the preferred embodiment; 
           [0016]      FIG. 6  is a more detailed diagram illustrating example read operations and populating the example alternate memory array hardware of  FIGS. 4 and 5  in the example system of  FIG. 1  for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with the preferred embodiment; and 
           [0017]      FIG. 7  is a block diagram illustrating a computer program product in accordance with the preferred embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0018]    In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which illustrate example embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. 
         [0019]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0020]    In accordance with features of the invention, a method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system with ECC. 
         [0021]    In accordance with features of the invention, the method, system and computer program product provide repair or redundancy enabling the memory system to recover from single address or small range of address fails, and without substantially increasing cost or system overhead. 
         [0022]    Having reference now to the drawings, in  FIG. 1 , there is shown an example computer system generally designated by the reference character  100  for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with the preferred embodiment. 
         [0023]    Computer system  100  includes a host computer  102  including a memory controller  104  coupled by at least one or a plurality of memory buffers  106  or memory buffer chip  106  to a system dynamic random access memory (DRAM)  108 , such as a plurality of Dual In-Line Memory Modules (DIMMs) 1-N,  110 . 
         [0024]    Computer system  100  includes an alternate memory array control program  114  of the preferred embodiment. Memory controller  104  is suitably programmed by the alternate memory array control program  114  to execute the flow charts of  FIGS. 2 and 3  of the preferred embodiment. Computer system  100  implements enhanced hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with the preferred embodiments. 
         [0025]    Computer system  100  implements redundancy, greatly improving the ability of the system to recover from single address or small range of address fails. An alternate memory array  402 , as illustrated and described with respect to  FIGS. 2-6 , stores instances of redundancy, for example, and is provided in a selected one of DRAM  108 , memory buffer  106 , or memory controller (MC)  104 . While implementation of the AMA  402  at the MC  104  and buffer  106  does not add to the latency, implementation at the DRAM  108  can increase latency slightly. At the DRAM  108 , extra wiring is provided to relay the ECC data as well as a predefined command or MRS command to signal a switch to a spare DRAM location. 
         [0026]    Computer system  100  is shown in simplified form sufficient for understanding the present invention. The illustrated computer system  100  is not intended to imply architectural or functional limitations. The present invention can be used with various hardware implementations and systems and various other internal hardware devices, for example, multiple main processors. 
         [0027]    Referring to  FIGS. 2 and 3 , there are shown respective flow charts generally designated by the reference characters  200 ,  300  illustrating exemplary operations of the example system  100  for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in accordance with preferred embodiments of the invention. 
         [0028]    In  FIG. 2 , exemplary AMA operations start as indicated at a block  202 . As indicated at a block  204 , an incoming address, data and ECC are received as indicated at a block  204 . An available AMA location is computed as indicated at a block  206 . A new location is identified as indicated at a block  208 . Responsive to an incoming address, data and ECC received at block  204 , checking for a command type is performed as indicated at a decision block  210 . When a read command is identified, checking if an error was detected as indicated at a decision block  212 . When an error was detected, the incoming address is compared with contents of AMA as indicated at a block  214 . Checking whether comparator logic found a matching valid entry in the AMA as indicated at a decision block  216 . When the comparator logic found a matching valid entry in the AMA, the matching entry in the AMA is invalidated and marked as unusable as indicated at a block  218 . A new entry is added to the AMA, and RAS operations are performed as indicated at a block  220 . Operations continue with the next request at block  222 . Operations end as indicated at a block  224 . 
         [0029]    When an error was not detected at decision block  212 , the incoming address is compared with contents of AMA as indicated at a block  226 . Checking whether comparator logic found a matching valid entry in the AMA as indicated at a decision block  228 . When the comparator logic did not find a matching valid entry in the AMA, data and ECC are read from the DRAM as indicated at a block  230 . When the comparator logic found a matching valid entry in the AMA, data and ECC are read from the AMA as indicated at a block  232 . Operations continue with the next request at block  222 . Operations end as indicated at a block  224 . 
         [0030]    When a write command is identified at decision block  210 , the incoming address is compared with contents of the AMA as indicated at a block  234 . Checking whether the comparator logic finds a matching valid entry in the AMA is performed as indicated at a decision block  236 . When the comparator logic found a matching valid entry in the AMA, data and ECC are written the AMA as indicated at a block  238 . When the comparator logic did not find a matching valid entry in the AMA, data and ECC are written to the DRAM as indicated at a block  240 . Operations continue with the next request at block  222 . Operations end as indicated at a block  224 . 
         [0031]    In  FIG. 3 , exemplary operations start with the MC  104  sending a read request as indicated at a block  302 . Checking whether the read request is in the Alternate Memory Array (AMA)  402  is performed as indicated at a decision block  304 . If the read request has a valid address in the AMA  402 , then the data is obtained from the AMA as indicated at a block  306 . Checking whether an error is detected on the read is performed as indicated at a decision block  308 . When an error is detected on the read, and it is determined that the error is correctable and the Correctable Error (CE) does not exceed a preset threshold for CEs at a decision block  310 , then the data is corrected with ECC and the AMA is updated as indicated at a block  311 . When the error is an Uncorrectable error (UE) or a CE that exceeds the preset threshold for CEs, then the AMA locations are marked as unusable or corrupted as indicated at a block  312 . 
         [0032]    Otherwise if the read request is not in the AMA  402 , then the data is obtained from the DRAM  108  as indicated at a block  314 . Checking whether an error is detected on the read is performed as indicated at a decision block  316 . When an error is not detected on the read at decision block  308  and at decision block  316 , then operations continue with the next request as indicated at a block  318 . The operations end as indicated at a block  320 . 
         [0033]    When an error is detected on the read from the DRAM, at decision block  316 , it is determined if the error is correctable as indicated at a decision block  322 . When a correctable error (CE) is identified at decision block  322 , then checking for available spares is performed as indicated at a decision block  324 . If spares are not available, the appropriate Memory Reliability Availability and Serviceability (Memory RAS) operations are performed as indicated at a block  326 . When spares are available, then the corrected data with ECC is written into a new AMA location as indicated at a block  328 . Then after the data and ECC is written at block  328  or after the RAS operations are performed at block  324 , operations continue with the next request at block  318 . 
         [0034]    Referring to  FIG. 4 , a read operation generally designated by the reference character  400  is illustrated with an Alternate Memory Array (AMA)  402  of the preferred embodiment. AMA  402  includes a plurality of addresses 0-N,  408  with a respective valid signal V0-VN, a plurality of comparators 0-N,  410  with a respective match signal M0-MN, and a plurality of data entries DATA 0+ECC-DATA N+ECC,  412 . For example, to provide dedicated support to certain software operations, constraints on AMA  402  may be placed by providing a start and end addresses  408 . The AMA  402  only populates its entries  412  with addresses  408  that are within the given range of the start and end addresses  408 . 
         [0035]    As shown in  FIG. 4 , a read request sent by the memory controller  104  includes an incoming address  414 . The address  414  of read is compared against valid addresses  408  in AMA  402 . The read command is sent unaltered to main memory  108  as indicated at a block  416 . If this address matches any valid address in the AMA, the corresponding particular match signal of match signals M0-MN is set and the data  412  associated with that address is sent to an output bus  418 . The data returned from memory as indicated at a block  420  and the data on the output bus  418  of the AMA  402  are input to a multiplexer  422  to determine which will be sent on the memory data bus. A select line applied to the multiplexer  422  includes an OR  416  of all match signals M0-MN from the AMA  402  where an address has been matched. Delivery of the data back to the processor incurs no extra latency from utilizing the AMA  402 . If a match is found in the AMA  402 , that data would return simultaneously with the data from mainstore  108  to preserve timings. 
         [0036]    Referring to  FIG. 5 , a write operation generally designated by the reference character  500  is illustrated with the AMA  402 . A write request sent by the memory controller  104  includes an incoming address  502 , and incoming data  504 . The address  502  of the write is compared against valid addresses  408  in the AMA  402 . Command and data also are sent unaltered to the main memory  108 . If the incoming address  502  matches any valid address  408  in the AMA  402 , the corresponding match signal M0-MN is set and the input data and ECC are written into the corresponding entry  412  of the AMA  402  via a respective gate  510 . If an AMA address  408  does not match, the AMA  402  does nothing. 
         [0037]    Referring to  FIG. 6 , populating AMA operation generally designated by the reference character  600  is illustrated with the AMA  402 . For example, the populating AMA operation is responsive to a read request sent to main memory  108  that returns data with correctable error to utilize a spare entry in Alternate Memory Array (AMA)  402  with an incoming address  602  and incoming data  604 . A next available entry in the AMA  402  is determined as indicated at a block  606  utilized both valid and match signals of address  408  and comparator  410  from the AMA  402 , as well as an algorithm for optimization. An empty entry is returned, as well as an enable signal (WE) to allow writing to that entry as indicated at a block  608 . If the address triggering the correction was already in the table match signal detected (V#) an invalidate signal will also be returned for that address to prevent further use of that entry as indicated at a block  610 . The data and ECC are then written into the corresponding entry  412  to be used on the next read to this address. 
         [0038]    It should be understood that to lower hardware costs, software algorithms optionally are used to populate the AMA  402  so that searching through the AMA does not require significant hardware. For example, techniques such as linked and doubly linked lists; sort and the like are used to populate the AMA. However, software algorithms may lead to loss of performance. When the AMA is full, an AMA full-bit is sent to the MC  104  indicating all entries  412  are used so the AMA  402  can be bypassed, if needed. Also, the AMA full-bit triggers an automatic clean-up of AMA  402 . For example, in operation of system  100 , with invalidation of data in main memory  108 , those entries are deleted from the AMA  402  as well to free up space, such as with Page Guard software. If empty slots  412  are available in AMA  402 , search through CE history of MC  104  to find addresses that are most likely to take a CE again and populate AMA with good data and ECC. High priority requests from MC are accepted to populate the AMA  402  with addresses that exceeded CE thresholds or are near exceeding CE thresholds. Priority schemes are implemented if all entries  412  of AMA  402  s are used up, and soft errors entries are cleaned up. Data coming back from main memory  108  are compared and after a set number of good data from main memory, the corresponding AMA entry  412  is deleted. 
         [0039]    To maintain high RAS within the AMA  402  scrubbing of all the entries in the AMA must be performed periodically to invalidate and mark an entry unusable if a UE occurs or if a CE exceeds the threshold after fetching data from AMA. During IPL, the AMA  402  should also be initialized by performing read/write patterns and marking out bad locations. Periodically, entries within the AMA must be freed if associated addresses are made unavailable to the system via operations such as page guard. 
         [0040]    Referring now to  FIG. 7 , an article of manufacture or a computer program product  700  of the invention is illustrated. The computer program product  700  is tangibly embodied on a non-transitory computer readable storage medium that includes a recording medium  702 , such as, a floppy disk, a high capacity read only memory in the form of an optically read compact disk or CD-ROM, a tape, or another similar computer program product. Recording medium  702  stores program means  704 ,  706 ,  708 , and  710  on the medium  702  for carrying out the methods for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair of the preferred embodiment in the system  100  of  FIG. 1 . 
         [0041]    A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means  704 ,  706 ,  708 , and  710 , direct the computer system  100  for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair of the preferred embodiment. 
         [0042]    While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.