Abstract:
A method and system for compensating for voltage notches in phase locked loop (PLL) control devices. A bridge firing controller receives signals representative of two of the line to line voltages received by the bridge. The controller includes a PLL synchronizing tool which receives the line to line voltage signals and generates a synchronizing phase error signal for aligning the phases of the two input signals. The controller, for a predetermined period following bridge firing, determines whether a voltage notch has occurred. If so, the controller substitutes model control signals for actual control signals so as to reduce the effect of the notch on the generated phase error signal used for synchronization. If not, the controller continues to use the actual control signals to generate the phase error signal. Once the predetermined period has expired, the controller utilizes the actual control signals to generate the phase error signal.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to devices and systems for controlling and regulating the conversion of power from an AC source to a load, typically a DC motor. More particularly, the present invention relates to devices which control the conduction of controllable rectifier, e.g., thyristor, bridges placed between the source and the motor and, in particular, methods for compensating for inaccuracies caused by voltage notches during bridge commutation. 
     Motor control systems of the type described above typically include at least one rectifier bridge connecting the motor windings to alternating voltage supply lines. For a conventional three phase motor, each AC phase line is generally coupled to the motor by a pair of connected thyristors. That is, in a three phase system, six thyristors are required to transfer power from the source to the load, each for one half of each phase. A thyristor, such as a silicon controlled rectifier (SCR), is generally defined as a switchable diode controlled by a gate element. Each thyristor presents a relatively high blocking impedance to the flow of electrical energy until it is forward biased by a trigger current being applied to its gate element. A digital control circuit typically determines the proper time to trigger the thryistors during each half-cycle of the supply line voltage. Once a thyristor is triggered by the application of a predetermined current to its gate, the forward blocking impedance is lowered, thereby permitting the flow of electrical energy through the thyristor in the manner of a diode. Once conduction has been enabled, the thyristor cannot be turned off until the current flowing therethrough is reduced to near zero (i.e., makes a zero crossing). 
     The amount of power transferred to the motor is controlled by varying the duration of the conduction of the various thyristors. This is done by controlling the firing angle of each thyristor, that is, the point in the AC waveform at which the thyristor is initiated into conduction. The process of switching from thyristor to thyristor is known as commutation. 
     Generally, in a polyphase system, all of the line current is carried by a particular phase or thyristor at a given point in time. However, since the commutation of current from one thyristor cell to the next takes both time and voltage, during commutation, two consecutive cells become shorted for the time it takes to commute the line current from the outgoing cell to the oncoming cell. The duration of this short is related to both the commutation inductance (the inductance of the source supplying the bridge) and the amplitude of the current being commutated. As a result, the typically sinusoidal AC line to line voltage becomes corrupted by periods of zero voltage caused by the cell shorting. These disturbance periods are commonly referred to as voltage notches. Since six thyristors are fired during each cycle, six voltage notches appear in each of the line to line voltage signals every cycle. 
     In order to control the firing of the various thyristors, conventional systems incorporate a firing controller, either analog or digital, to control the firing angle of each thyristor. The line to line voltages described above are generally used by the controller in conjunction with a phase lock loop (PLL) to synchronize the phases of each of the received line to line voltages and to thereby accurately determine the proper thyristor firing angles. The above-described voltage notches in each of the line to line voltage signals introduce deleterious effects to the accuracy and stability of the PLL and the firing controller. 
     U.S. Pat. No. 4,399395 issued to Paul M. Espelage recognizes problems caused by voltage notches and discloses a method for compensating therefor wherein a synchronizing pulse train is generated from a composite waveform developed by summing at least one line to line voltage signals containing the voltage notches and a signal corresponding to at least one delta current derived from the difference of two phase currents and multiplied by a factor representative of the commutation inductance. Unfortunately, this method fails to efficiently and accurately compensate for such effects with a minimum of complexity and increased cost. 
     Accordingly, there is a need in the art of power control systems for a system and method for accurately compensating for the effects of voltage notches without increasing the cost or complexity of the system. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention overcomes the problems noted above, and provides additional advantages, by providing for a method and system for compensating for voltage notches in phase locked loop (PLL) control devices. A bridge firing controller receives signals representative of two of the line to line voltages received by the bridge. The controller includes a PLL synchronizing tool which receives the line to line voltage signals and generates a synchronizing phase error signal for aligning the phases of the two input signals. The controller, for a predetermined period following bridge firing, determines whether a voltage notch has occurred. If so, the controller substitutes model control signals for actual control signals so as to reduce the effect of the notch on the generated phase error signal used for synchronization. If not, the controller continues to use the actual control signals to generate the phase error signal. Once the predetermined period has expired, the controller utilizes the actual control signals to generate the phase error signal. 
     By substituting model signals for actual signals during voltage notches, the effects of the voltage notches are compensated, thereby enabling the use of previously unstable high gain proportional plus integral controllers having decreased susceptibility to phase error losses and providing for more accurate operation of the thyristor bridge. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention can be understood more completely by reading the following Detailed Description of exemplary embodiments, in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a basic block diagram illustrating a thyristor bridge and firing controller system incorporating the method of the present invention; 
     FIG. 2 is a flow chart describing a method for compensating for voltage notches in a phase locked loop; 
     FIG. 3 is an exemplary graph of phase error, V α , V β     —     model , V β , V β     —     model , V ac , and V ac     —     Fbk  signals all against time illustrating uncompensated voltage notches and their effects; 
     FIG. 4 is an exemplary graph similar to FIG. 3 showing phase error, V α , V α     —     model , V β , V β     —     model , V ac , and V ac     —     Fbk  signals all against time wherein the voltage notches in the signals have been compensated in accordance with one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to the Figures and, in particular, to FIG. 1, there is shown a block diagram illustrating one embodiment of a power conversion apparatus incorporating the voltage notch compensation system of the present invention. In particular, forward and reversing thyristor bridges  102  and  104  are connected between an AC source (either a single or a polyphase source) and a load in the manner described above. Bridge firing controller  106  and supervisor controller  108  are electronically connected to the system for controlling the firing of the bridges  102  and  104 . In accordance with one embodiment of the present invention, the bridge firing controller  106  receives signals from the system indicative of the bridge output voltage, the load current, and the line to line input voltages. Further, the bridge firing controller also receives signals indicative of the gate signals applied to each thryistor in bridges  102  and  104 . In the manner set forth in detail below, the bridge firing control utilizes these signals to accurately and quickly enable safe and effective transfer of power from the source to load or, in a reversing mode, from the load to the source. It should be understood that although the above described system has been illustrated to include a thyristor bridge for use in controlling a DC motor, the present invention may also be utilized in the control of cycloconverters feeding AC motors, in SCR bridges used for load commutated inverters, and in other similarly controlled rectifier bridges. 
     Preferably, the bridge firing controller  106  is a digital micro-controller incorporating a two-phase phase locked loop (PLL) and a proportional plus integral (PI) controller for synchronizing the two input line to line voltages received by the bridge. Unfortunately PI controllers suffer from problems which adversely effect their ability to accurately follow phase and frequency changes in the input signals. In particular, if the PI incorporated into the controller is tuned with a low gain, the PI may be unable to react quickly enough to changes in phase and frequency, thus leading to a phase error between the input voltage and the angle γ PLL . These phase errors limit the bandwidth and linearity of the thyristor bridge, and force the outer regulator loops to compensate therefor. Conversely, to overcome the deficiencies of low gain PI controllers, a high gain PI controller may be used to enable quick reaction to changes in phase and frequency. However, as set forth above, high gain PI&#39;s are susceptible to disturbances caused by voltage notches in the line to line voltage signals. Accordingly, the bridge firing controller  108  generates model signals related to the input line to line voltages, wherein during voltage notch conditions, the model signals may be used in place of the actually measured signals, thereby permitting the use of high gain PI controllers and increasing the ability of the controller to accurately and efficiently control the firing of the thyristor bridge. 
     Referring now to FIG. 2, there is shown a flow chart describing one embodiment of a method for compensating for voltage notches in a thyristor bridge firing controller. As is known in the art, a controller for regulating the firing of thyristors in a thyristor bridge necessarily receives phase information relating to the line voltage which the bridge is presently conducting in order to align the firing impulses to the line to line voltage. In accordance with one embodiment of the present invention, the bridge firing controller  108 , in step  200 , receives two of the AC line to line voltage signals V ab  and V ca , phase shifted from the other by 120°. Mathematically, the signals V a , V b , V c , V ab , and V ca  can be expressed using the following expressions: 
     
       
         V a =V Mag *sin(γ line );  
       
     
     
       
         
           
             
               
                 V 
                 h 
               
               = 
               
                 
                   V 
                   Mag 
                 
                 * 
                 
                   sin 
                    
                   
                     ( 
                     
                       
                         γ 
                         line 
                       
                       + 
                       
                         
                           2 
                           * 
                           π 
                         
                         3 
                       
                     
                     ) 
                   
                 
               
             
             ; 
           
         
         
           
             
               
                 V 
                 c 
               
               = 
               
                 
                   V 
                   Mag 
                 
                 * 
                 
                   sin 
                    
                   
                     ( 
                     
                       
                         γ 
                         line 
                       
                       - 
                       
                         
                           2 
                           * 
                           π 
                         
                         3 
                       
                     
                     ) 
                   
                 
               
             
             ; 
           
         
                 
         
             
         
      
     
     
       
           V   ab   =V   Peak =*sin(ω* t );  
       
     
     
       
         
           
             
               
                 V 
                 ca 
               
               = 
               
                 
                   V 
                   Peak 
                 
                 * 
                 
                   sin 
                    
                   
                     ( 
                     
                       
                         ω 
                         * 
                         t 
                       
                       + 
                       
                         
                           2 
                           * 
                           π 
                         
                         3 
                       
                     
                     ) 
                   
                 
               
             
             ; 
           
         
                 
         
             
         
      
     
     where            γ   line     =       ∫   o   t            ω   line                        t           ,                          
     ω line =2*π*linefrequency, ω*t=γ input , and          2   *   π     3                          
     is 120 electrical degrees. 
     In step  202 , the controller inputs the line to line voltage signals (V ab , V ca ) into a two-phase phase locked loop (PLL) synchronizing tool incorporated into the controller. In step  204 , the PLL, through coordinate transformation, converts the input line to line voltage signals into two sine wave signals (V α , V β ) having the same amplitude (V Mag ), but 90° out of phase. The two-phase PLL also generates an angle γ PLL  that corresponds to the input angle γ input , if the PLL is working correctly and is locked to the input voltage. This angle γ PLL  is then used by the controller in the conventional manner to define the time for the cell firing. The above calculations are described mathematically in the following manner: 
     Since V α  and V β  have the same amplitude but are 90° out of phase, they can be re-written as: 
     
       
           V   α   =V   Mag *sin(γ line );  
       
     
     
       
           V   β   =V   Mag *sin(γ line ); and  
       
     
     
       
         
           V 
           Mag 
           ={square root over (V α   2   −V   β   2 +L ))},  
         
       
     
     where V Mag  is the amplitude of the converted line to line voltages, as measured by the controller. 
     In order to increase the accuracy of the phase synchronization during voltage notch disturbances, the PLL, in step  206  also generates a time-corrected model for each of the voltage signals V α  and V β  referred to as V α     —     Model  and V β     —     Model . V α     —     Model  and V β   Model  are based upon the sine-cosine signal of the PLL and the amplitude V Mag , in accordance with the following expressions: 
     
       
           V   α     —     Model   =V   Mag *sin(γ PLL +ω PLL   *Δt ), and  
       
     
     
       
           V   β     —     Model   =V   Mag *cos(γ PLL +ω PLL   *Δt ),  
       
     
     where ω PLL *Δt represents a phase advance of one controller sampling time at the last calculated frequency of the PLL. 
     In step  208 , the controller determines whether a bridge firing has recently been commanded (preferably within the last 5 samplings or approximately 1250 μs, where the controller sampling time is 250 μs). If a bridge firing has not been recently commanded, the controller assumes that no voltage notches are present and continues to step  212 , described below, wherein the PLL selects the measured values of V α  and V β  for phase error calculation. If the controller determines that a bridge firing has recently been commanded, the PLL, in step 210, determines whether a voltage notch disturbance is occurring by determining whether the quantity |(V α −V α     —     Model )| is less than a predetermined percentage of V Mag  (preferably, around 10%). If so, the controller determines that a voltage notch is not occurring and proceeds to step  212 , wherein the PLL uses the measured value of V α  for phase error calculation. However, if, |(V α −V α     —     Model )| is greater than the predetermined percentage of V Mag , the controller proceeds to step  214 , where it selects the model value V α     —     Model  for phase error calculation. 
     A similar procedure is simultaneously followed for V β . If |(V β −V β     —     Model )| is less than a predermined percentage of V Mag  (preferably, around 10%), the controller selects the measured value V β  for phase error calculation. However, if |(V β −V β     —     Model )| is greater than the predetermined valued of V Mag  (preferably, around 10%), the controller selects the model value V β     —     Model  for phase error calculation. 
     In step  216 , the PLL utilizes the set of signals selected in steps  212  or  214  and generates a phase error signal V Error  which is proportional to the sine of the angle difference between the two sets of orthogonal quantities (i.e., γ line −γ PLL ), according to the expression: 
     
       
           V   Error =( V   α *cos(γ PLL )− V   β *sin(γ PLL ))  
       
     
     
       
          = V   Mag *sin(γ line −γ PLL )  
       
     
     wherein all variables are as set forth above. Note that where V α     —     Model  and V β     —     Model  have been selected in step  214 , V α  and V β  are replaced therewith. 
     Preferably, the phase error signal V Error  is regulated to zero using a proportional plus integral (PI) controller. The PI controller, in step  218 , generates a signal corresponding to the frequency of the input line voltage. This signal is then integrated in step  220  to generate the angle γ PLL . This angle γ PLL  is then used in step  222  to generate the two orthogonal sine and cosine signals of the phase angle γ PLL . In this manner, the PLL can follow the phase and frequency changes of the input line provided that the bandwidth of the closed loop is wide enough to follow. 
     By selectively determining the existence of voltage notches caused by cell commutation effects and calculating the phase error signal based upon model voltages during the effect, the inventive controller effectively smooths out the disturbances, thereby increasing the accuracy of the phase error calculation. 
     Referring now to FIGS. 3 and 4, there are shown four channels containing exemplary graphs illustrating each of the signals ph_error, V α , V α     —     model , V β , V β     —     model , V ac , and V ac     —     Fbk  against time for both an uncompensated system wherein voltage notches adversely effect PLL performance (FIG. 3) and a system compensated in accordance with the method set forth above wherein the effects of the voltage notches have been reduced (FIG.  4 ). In particular, the V ac  and V ac     —     Fbk  signals, shown in channel 1 of both FIG.  3  and FIG. 4, represent the analog and sampled line to line voltage signals received by the PLL. The V α  and V α     —     model  signals shown in channel 3 as well as the V β  and V β     —     model  signals shown in channel 3 are generated by the PLL. The ph_error signal also generated by the PLL is shown in channel 4. 
     Referring in particular to channel 1 of FIG. 3, there can be seen voltage notch effects to the line to line voltage signal designated by the numeral  300  caused by brief short circuits during the firing of successive thyristors. Please note that 6 discrete voltage notches  300  appear during each firing cycle. As described above, these voltage notches cause disturbances and inaccuracies  302 ,  304  and  306  in the measurement of V α , V β  and the synchronizing ph_error signals, respectively, each generated by the PLL as shown in channels 2-4 of FIG.  3 . 
     Referring now to FIG. 4, voltage notch effects  400  in the line to line voltage signals V ac  and V ac     —     Fbk  are shown in channel 1 and are similar to those shown in FIG.  3  and described above. However, unlike the signals shown in FIG. 3, the above-described method for compensating for these notches has been applied to the FIG. 4 signals by the PLL thereby resulting in significantly reduced voltage notch effects in each of the V α , V β  and phase_error signals shown in channels 2-4. 
     By compensating for the effects of voltage notches caused by thyristor cell commutation in phase locked loops, the method of the present invention provides for more accurate operation of a thyristor bridge, thereby enabling the use of previously unstable high gain proportional plus integral controllers having decreased susceptibility to phase error losses. 
     While the foregoing description includes many details and specificities, it is to be understood that these have been included for purposes of explanation only, and are not to be interpreted as limitations of the present invention. Many modifications to the embodiments described above can be made without departing from the spirit and scope of the invention, as is intended to be encompassed by the following claims and their legal equivalents.