Abstract:
Modular electronic trunk selectors are known which have a number of incoming trunk modules and a common control module. Incoming trunks are connected to outgoing trunks by the common control module. The invention disclosed is a trunk selector of this type but it includes automatic testing and fault location. Periodic tests are randomly made of incoming trunks to see if correct signals are present on certain leads between the incoming trunk module and the common control module. Checks are also made for continuity and open circuit conditions on the switching paths at appropriate times. Tests are also made when regular calls are being set up. Detection of a fault initiates a &#34;loop-back&#34; in the common control module to see if the fault is in the incoming trunk module or the common control module and an appropriate alarm is activated.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an electronic trunk selector having automatic testing and fault location features. 
     Modular electronic trunk selectors are known which have a number of incoming trunk modules and a common control module. Each incoming trunk module may be provided with a plurality of incoming trunks and these are adapted to be connected to outgoing trunks by the common control module. The number of incoming trunks may be different from the number of outgoing trunks and normally there are more incoming trunks than outgoing trunks. 
     SUMMARY OF THE INVENTION 
     The present invention relates to an electronic trunk selector which includes automatic testing and fault location means and particularly to one of the type mentioned in the immediately preceding paragraph. 
     The electronic trunk selector may be used to increase the limited availability of step-by-step selectors and offer a space saving of about 50% over rotary out trunk units (ROTS) with much improved equipment and transmission performance. 
     Connection of inlet to outlet is by means of electronically controlled reed relays. The fast operating time of the equipment overcomes the problem of interdigital time and the equipment is free from steady state and impulse noise, factors favourable to data transmission. It is arranged for switching T,R,S leads, together with a spare. 
     The incoming trunk modules (ITM&#39;s) provide the switching matrix crosspoints for connecting incoming trunks to outgoing trunks and the call supervisory functions for each Incoming Trunk. Each ITM has logic circuitry for setting up a switching path in conjunction with the Common Control Module (CCM) and for controlling the switching matrix. Typically there are 2 ITM&#39;s per Trunk Selector. 
     The CCM provides the common control circuitry for setting up the switching paths in the Trunk Selector. It operates on instructions from the ITM&#39;s indicating Incoming Trunks requiring connection to Outgoing Trunks. It also provides control and supervisory circuits associated with each outgoing trunk and means for automatic testing and fault locating and the operation of corresponding alarm indications. There is only one CCM for each Trunk Selector. 
     In a typical configuration of trunk selector having twelve incoming trunks, there are two ITM&#39;s which could accommodate up to sixteen incoming trunks. All selectors have full access to eight outgoing trunks. Of course, this is merely exemplary and other configurations could be used. 
     In accordance with a broad aspect of the invention, there is provided an electronic trunk selector for selectively connecting any one of a plurality of incoming trunks to any one of a plurality of outgoing trunks, the incoming trunks being connected to at least one incoming trunk module (ITM) and the outgoing trunks being connected to a common control module (CCM), the CCM having means for sending to the ITM sequential addresses of incoming trunks and the ITM having means for sensing if an incoming trunk is requesting service and for sending to the CCM a signal on a first (RQ) lead to indicate that the incoming trunk is requesting service when that incoming trunk is addressed by the CCM and means for sending signals on a second (OC-DR) lead to the CCM regarding the busy/idle status of an addressed incoming trunk, said CCM having means for periodic random testing of idle incoming trunks whereby it causes the ITM to connect the idle incoming trunk to an idle outgoing trunk pre-selected by the CCM and checks the RQ lead to see if it indicates a request for service and checks the OC-DR lead to see if it indicates a busy status of the incoming trunk. 
     A preferred embodiment of the invention will now be described in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF DRAWING 
     FIGS. 1 and 2 together, with FIG. 1 at the top and FIG. 2 at the bottom, comprise a block diagram of an incoming trunk module in accordance with the invention. 
     FIGS. 3-6, which go together as shown in FIG. 7, comprise a block diagram of part of a common control module according to the invention and FIGS. 8-11, which fit together as shown in FIG. 12, comprise a block diagram of the remainder of the common control module. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The incoming trunk module (ITM) shown in FIGS. 1 and 2 will be discussed first. 
     Seizure and setting up of a switching path results in a seizure request to the common control module (CCM). When a step-by-step (S×S) selector seizes an inlet (INC TRK) of the electronic trunk selector, it grounds the INC TRK &#34;S&#34; lead (top left of FIG. 1). This turns on transistor Q101 via resistor R101, transistor Q101 conducting via collector load resistor R102. The emitter of transistor Q101 is connected to -10 volts, as indicated on the drawing. Resistor R104 ensures that normally (in the idle state) transistor Q101 is held OFF. Diode CR101 prevents reverse breakdown of the base-emitter junction of transistor Q101 with -48 v on the &#34;S&#34; lead, --48 volts being a typical system voltage. Transistor Q101 when &#34;ON&#34; forward biases diode CR102 placing a logic &#34;0&#34; (-10v) on the input to inverter gate ICI. This produces via inverter IC2 a &#34;0&#34; on pin 13 of IC 3 and on the &#34;Master Reset&#34; (MR) of 4-bit latch IC4, removing the reset. Capacitor C102 and resistor R105 act mainly on RELEASE, which will be described subsequently. On seizure capacitor C102 discharges rapidly through diode CR102, introducing only a small delay. 
     A &#34;0&#34; on pin 13 of AND gate IC3 gives a &#34;0&#34; on pin 13 of IC5. Since latch IC4 was previously reset, its output Q3 is at a &#34;0&#34; and a &#34;1&#34; will be produced at the output of NOR gate IC5, giving a &#34;1&#34; to the input of multiplexer IC6 (FIG. 2) corresponding to that particular INC TRK. When the INC TRK counter in the common control module (to be described subsequently) reaches that INC TRK (i.e. binary address on leads IT-1,2,4 correspond to number of INC TRK in that ITM) the multiplexer IC6 routes the &#34;1&#34; from pin 11 of IC5 to its output pin (Z) and thence to the &#34;RQ&#34; lead to the CCM. The &#34;disable&#34; (DIS) input to IC6 from the &#34;DIS&#34; lead is normally &#34;0&#34;-not disabled. 
     Loading of an OG TRK address from the CCM will now be described. 
     When the CCM detects the request on the &#34;RQ&#34; lead, it sends back a &#34;0&#34; on the &#34;EN&#34; lead (lower left, FIG. 2) to that ITM in a manner described later. This produces a &#34;1&#34; via inverter IC7 on pin 5 of IC8 and on pin 5 of IC9. At the same time, the CCM will have stopped the INC TRK counter (to be discussed later) so that the address on the IT-1,2,4 bus leads (see FIG. 2) will cause decoder IC10 to put a &#34;1&#34; on pin 6 of IC8. (fourth bit &#34;D&#34; of decoder IC10 is &#34;0&#34;-&#34;DIS&#34; lead not activated-enabling decoder). This produces a &#34;0&#34; at the output of NAND gate IC8, reverse-biasing diode CR104. Capacitor C106 then charges through resistor R119. When the input of inverter IC12 reaches its switching threshold of about -5v, its output pin 12 goes to a &#34;1&#34; making input D3 of latch IC4 a &#34;1&#34; and producing a &#34;strobe&#34; pulse on the &#34;ST&#34; input of the latch IC4 via differentiator C108, R122. This strobe pulse causes the binary OG TRK address from the CCM on leads OT-1, 2, 4 to be loaded into latch IC 4 inputs D0, D1, D2 together with the &#34;1&#34; on input D3. These logic states appear immediately at the outputs Q0-Q3 of 4-bit latch IC4. The function of the delay circuit formed by CR104, C106, R119 is to slightly delay the leading edge of the &#34;EN&#34; pulse so that the information on the OT-1,2,4 leads has settled after OG TRK selection. It has little effect on the trailing edge since C106 discharges quickly through CR104. Latch bit D3/Q3 serves as a BUSY/IDLE indicator with Q3 being a &#34;1&#34; when the circuit is busy. As soon as Q3 goes to a &#34;1&#34; the &#34;1&#34; on the &#34;RQ&#34; lead to the CCM is removed, since the &#34;1&#34; on pin 12 of NOR gate IC5 forces pin 11 to a &#34;0&#34;. 
     A return of BUSY indication and OG TRK address is returned to the CCM as confirmation. When latch IC4 has been loaded, the binary OG TRK address appears on input pins 3, 6, 1 of 3-state inverting gates IC13. The &#34;0&#34; on the &#34;EN&#34; lead produces a &#34;1&#34; on pin 12 of IC 14 and on the input of inverter IC 15, via inverter IC7 and OR gate IC9. There is a &#34;1&#34; on pin 9 of IC14 from the decoder IC10, a &#34;1&#34; on pin 11 from output Q3 on latch IC4 and a &#34;1&#34; on pin 10 via inverter IC16 (FIG. 2). This causes the output of NAND gate IC14 to go to a &#34;0&#34;, placing a &#34;0&#34; on the &#34;OC-DR&#34; lead via forward biassed diode CR 150 to the CCM as a busy indication and removing the disable from 3-state gates IC13. At the same time, the output of IC15 is a &#34;0&#34;, enabling the gates IC13 and causing an inverted version of the OG TRK address to be returned on the OC - 1,2,4 bus leads. On removal of the &#34;EN&#34; pulse, pin 12 of IC13 returns to a &#34;0&#34; and the address on the OC-1,2,4 bus and &#34;0&#34; on the OC-DR lead are removed. When the 3-state gates IC13 are disabled, the output becomes high - impedance (neither &#34;0&#34; nor &#34;1&#34;) so that other gates may control the bus from other INC TRK Circuits. 
     It should be noted that the circuitry shown in FIGS. 1 and 2 relates only to a single incoming trunk on an ITM. Most of the circuitry would thus be duplicated for the other seven trunks except for some common items such as the decoder IC10 and multiplexer IC6, as will be obvious. 
     Operation of the switching matrix (SW MTX) relay will now be described. 
     The OG TRK address and busy/idle bit from outputs Q0 to Q3 of latch IC4 also appear at the bases of transistors Q106, Q108, Q109 and Q110. Each transistor performs as an inverter and level translator. Transistors Q108 to Q110 present the address to the SW MTX decoder IC18. Transistor Q106 inverts the BUSY indication from Q3 and IC4 to give a &#34;0&#34; to the &#34;D&#34; input of the decoder IC18 which enables the decoder. Each transistor level translator works in the same manner and only Q109 will be discussed here. When Q0 from IC4 is at a &#34;1&#34; (ground), Q109 turns OFF so that input &#34;A&#34; to decoder IC18 is pulled to a &#34;0&#34; (-22v) by resistor R109. When Q0 is at a &#34;0&#34; (-10v), Q109 turns ON. Since approximately the same current flows through R125 and R109 (neglecting small base current), both resistors are chosen to be the same value. Then, approximately 11 volts will be dropped across each resistor, and input &#34;A&#34; to the decoder IC18 will be at a &#34;1&#34; (-11v). If OG TRK #1 has been selected by the CCM, Q1 of IC18 will go to a &#34;1&#34; (-10v) and transistor Q102 will turn ON via resistor R102, operating SW MTX relay K101. Diode CR102 protects transistor Q102 against back emf spikes on release of the circuit. The purpose of the level translators (from GND, -10v to -10v, -22v) is to allow nominal 24v relays to be used as opposed to 12v types which draw an undesirably high amount of current. 
     When the corresponding SW MTX relay operates, it connects the INC TRK T,R,S,SP leads through to the T1, R1, S1, SP1 leads of the OG TRK relay in the CCM (to be described later). 
     Release of the circuit occurs when the ground is removed from the &#34;S&#34; lead. Transistor Q101 turns off, reverse biasing CR102 so that capacitor C102 starts to charge through resistor R105. When the input of ICI reaches the gate threshold of about -5 volts, its output pin goes to a &#34;0&#34;, producing a &#34;1&#34; at the output of IC2. This resets the latch IC4 by the &#34;MR&#34; input, giving &#34;0&#39;s&#34; at all outputs Q0-Q3. Output Q3 (the BUSY/IDLE indicator) going to a &#34;0&#34; gives a &#34;1&#34; at input &#34;D&#34; of decoder IC18, disabling the decoder and so releasing the SW MTX relay that had been operated via transistor Q102, etc. The delay produced by CR102, C102 and R105 (in the order of 100 mS) ensures that the SW MTX relay is released after the OG TRK relay in the CCM, which starts releasing as soon as the &#34;S&#34; lead ground disappears, so that the SW MTX is not required to break away voltage or current, this being known in the art as &#34;dry&#34; switching. 
     Interrogation of the ITM by the CCM while the CCM is scanning for service requests is as follows. 
     When the CCM is scanning (i.e. scanner not stopped during setup of switching path), it places &#34;0&#34; pulses on the &#34;TE&#34; lead during the time it is looking at that ITM. Each time a new address is placed on the IT-1,2,4 leads to look at one of the eight INC TRKS in that ITM, a &#34;0&#34; pulse is placed on the &#34;TE&#34; lead and stays there for the first quarter period of the address duration. This produces a &#34;1&#34; pulse via inverter IC20 (FIG. 2) on one input of IC21 and on pin 6 of IC9. If the decoder IC10 is addressed to the same INC TRK, there will be a &#34;1&#34; on the other input of IC21 producing a &#34;0&#34; pulse via differentiator C104, R117 at pin 12 of AND gate IC3, thus giving a &#34;0&#34; pulse on pin 13 of IC5. If the INC TRK circuit is IDLE, there will be a &#34;0&#34; also on pin 12 of IC5 and a &#34;1&#34; pulse will be presented to the appropriate input of multiplexer IC6. Since the muliplexer IC6 is addressed to the same INC TRK, this &#34;1&#34; pulse is fed back immediately to the CCM on the &#34;RQ&#34; lead as an indication that the circuit is IDLE. If the circuit is BUSY, pin 12 of IC5 will be at a &#34;1&#34; forcing pin 11 to a &#34;0&#34; and inhibiting an &#34;RQ&#34; lead signal. The &#34;1&#34; pulse on pin 6 of IC9 will appear via the OR gate on pin 12 of IC14. Pin 11 of IC14 will be at a &#34;1&#34; from output Q3 of latch IC4, pin 9 will be at a &#34;1&#34; from the decoder IC10 and pin 10 will be at a &#34;1&#34; (circuit not disabled). Therefore the OG TRK address of the connected OG TRK and a &#34;1&#34; on the &#34; OC-DR&#34; lead will be returned to the CCM as a BUSY indication for the duration of the &#34;TE&#34; pulse. The operation of the 3-state gates IC13, etc., is the same as explained above. 
     The duration of the &#34;TE&#34; pulse is very short (about 25 s) so there is no tendency for the pulses at the output of IC21 to operate &#34;A&#34; relay K109 via transistor Q103. 
     Since both the decoder IC10 and multiplexer IC6 are used in producing the interrogation response, both are checked for failure of any input or output, as explained later. 
     The CCM automatically makes a &#34;test&#34; call as will now be explained. 
     When the CCM makes a test call, it stops its INC TRK counter, &#34;freezing&#34; the address on the IT-1,2,4 leads to the address of the INC TRK to be tested, and places a continuous &#34;0&#34; on the &#34;TE&#34; lead to the corresponding ITM. If the INC TRK circuit is idle, the leading edge of the &#34;TE&#34; lead &#34;0&#34; will produce an &#34;RQ&#34; lead response as described previously, but differentiator C104, R117 will ensure that it is still only a pulse that is returned to the CCM although the &#34;TE&#34; lead remains at a &#34;0&#34;. IF the INC TRK circuit is busy, a busy indication will be returned as described previously, but the CCM will then reset the test sequence (to be described), immediately removing the &#34;0&#34; from the &#34;TE&#34; lead. 
     If the INC TRK is idle, the &#34;TE&#34; lead will stay at a &#34;0&#34; giving a &#34;0&#34; at the output of gate IC21 which then operates the &#34;A&#34; relay K109 via PNP transistor Q103 and resistor R113. Resistor R114 ensures that Q103 normally turns OFF properly. Diode CR109 protects transistor Q103 against voltage spikes from the relay K109. 
     When the &#34;A&#34; relay operates, it places grounds on all four INC TRK leads T, R, SP, S. It also breaks the T, R, SP leads back to the S×S selectors, but the ground on the S lead is returned as an indication that the inlet is busy, preventing seizure by the S×S while a test call is in progress. 
     The ground on the &#34;S&#34; lead also turns on transistor Q101 and a switching path is set up in exactly the same way as for a regular call, this action having been explained previously. When the path has been set up and the SW MTX relay K101 has operated, the CCM can test for the grounds on all four leads from the &#34;A&#34; relay, in a manner to be described subsequently. 
     At the end of a test call, the CCM returns the &#34;TE&#34; lead to a &#34;1&#34; causing the &#34;A&#34; relay to release. All grounds are then removed and the ground disappearing from the &#34;S&#34; lead causes the circuit to release as for a regular call. 
     It can be seen that all parts of the circuitry are checked during a test call, since the &#34;A&#34; relay places a ground on the &#34;S&#34; lead as for a regular call, so checking even the &#34;S&#34; lead monitor transistor, Q101. The CCM will diagnose a fault condition if it does not then receive a steady request signal on the &#34;RQ&#34; lead after allowing for sufficient delay for operation of the &#34;A&#34; relay. 
     Disabling of the ITM in a fault locating sequence and activation of an alarm indication will now be described. 
     When the CCM diagnoses a fault condition, it institutes a FAULT LOCATING SEQUENCE, in a manner to be described later, to determine whether the fault is in the CCM or the ITM. 
     The &#34;DIS&#34; lead to both ITM&#39;s is activated by placing a &#34;1&#34; on it. This disables the decoder IC10 (D input) and the multiplexer IC6 (Disable &#34;DIS&#34; input) and IC14 via input pin 10 and inverter IC16. Disabling the multiplexer IC6 prevents a request signal or interrogation response (&#34;1&#34;) from being sent to the CCM on the &#34;RQ&#34; lead. Pin 10 of IC14 going to a &#34;0&#34; forces its output pin 13 to a &#34;1&#34;, disabling 3-state gates IC13 and preventing both OG TRK address and a busy indication from being sent to the CCM on the OC-1, 2, 4, DR leads. Having removed all logic signals from the ITM&#39;s, the CCM can now &#34;loop back&#34; its own signals to the &#34;RQ&#34; and &#34;OC-1. 2, 4, DR&#34; leads to check whether the fault still persists or is cleared. 
     If &#34;looping back&#34; in the CCM clears the fault, then the fault must have been in the addressed ITM. In this case, the CCM operates a latch corresponding to the addressed ITM; this in turn places a &#34;1&#34; on the corresponding &#34;ALM&#34; lead, lighting the &#34;ITM ALM&#34; indicating LED CR111 via resistor R130 (FIG. 2). COMMON CONTROL MODULE (CCM) 
     Seizure and setting of a switching path and interrogation of an ITM is as follows. 
     Prior to receiving a request for service from an ITM, an idle OG TRK will have been preselected in the following manner. Each OG TRK circuit is equipped with an &#34;S&#34; lead monitor transistor Q202 (FIG. 10). When the OG TRK is idle, there will be open or -48V on the &#34;S&#34; lead, keeping Q202 turned off. Resistor R206 ensures proper turn off, diode CR201 prevents reverse breakdown of the base-emitter junction. When the OG TRK is busy, a ground on the &#34;S&#34; lead turns transistor Q202 on by resistor R205. Resistor R202 is a collector load for transistor Q202. Multiplexor IC30 looks at the 8 OG TRK circuits under control of the binary address on the OT1, 2, 4 leads (inverted through gates IC31). The logic state at the addressed input is routed from the Z output to pin 6 of IC32 (FIG. 5) via the &#34;CS&#34; lead. The multiplexer IC30 (FIG. 10) is permanently enabled, both the &#34;DIS&#34; (disable) and &#34;INH&#34; (inhibit) leads connected to a logic &#34;0&#34; (-10v). If the address on the OT-1,2,4 leads corresponds to a BUSY OG TRK, then the &#34;0&#34; from Q202 will be routed to pin 6 of IC32 (FIG. 5). Pin 5 of IC32 is connected to a continuous source of clock pulses (explained below); therefore when the clock is at a &#34;0&#34; the output of IC32, connected to pin 5 of IC33, will go to a &#34;1&#34;. Pin 6 of IC33 is at a &#34;1&#34; when the CCM is not setting up a switching path and a low going clock pulse will be produced from the NAND gate IC33 for the clock input to counter IC34. This will clock the counter IC34 to the next address, causing the multiplexer IC30 (FIG. 10) to look at the next OG TRK, by means of the OT-1, 2, 4 leads. If the next OG TRK is also busy, pin 6 of IC32 (FIG. 5) will remain at a &#34;0&#34; so that the counter will receive another clock pulse which pin 5 of IC32 goes to a &#34; 0&#34; again. This scanning continues until an IDLE OG TRK is found, at which time pin 6 of IC32 goes to a &#34;1&#34; forcing pin 4 of IC32 to a &#34;0&#34; and pin 4 of IC33 to a &#34;1&#34;. This cuts off the clock pulses from counter IC34, stopping the counter and &#34;freezing&#34; the address on the OT1, 2, 4 leads to the idle OG TRK. 
     Incoming trunk scanning and interrogation is as follows. 
     The CCM, while not setting up a switching path, is continuously scanning the &#34;RQ&#34; leads from the ITM&#39;s, looking for a service request. The main system clock is derived from &#34;programmable timer&#34; IC 35 (FIG. 3). This doubles as an oscillator for producing the clock pulses and a timer for determinimg the rate of automatic testing, discussed below. The clock oscillator frequency determining components are C3, R4, and R5 connected to the OUT 1, IN 1 and OUT 2 terminals and the square wave clock appears at OUT 2. From OUT 2, the frequency is halved by flip-flop IC36 connected in a standard J/K configuration as a toggle circuit that changes state every time the clock input (C) goes to a &#34;1&#34;. 
     The output (Q) of IC36 is routed to pin 5 of OG TRK scanner gate IC32 (FIG. 5), and to pin 8 of IC37 (FIG. 3) where it is NANDed with the double frequency from OUT 2 of IC35. The output of IC37 only goes to a &#34;0&#34; when both inputs are at a &#34;1&#34;; the effect of this is to produce a pulse waveform with a period equal to that of the waveform from &#34;Q&#34; of IC36, but with a &#34;0&#34; pulse of the width equal to only a quarter of this period. Normally, pin 5 of IC38 is at a &#34;0&#34; and therefore these pulses appear at the clock input of incoming trunk counter IC47 via IC38 and inverter IC39. This continuously clocks the counter causing the binary address on the IT1,2,4 leads to the ITM&#39;s to be continuously changed so that the decoders and multiplexers in each ITM will successively look at each of the 8 trunks in that ITM in turn. The fourth bit of the counter IC47 is connected to the first address bit of several decoders and a multiplexer IC40. The second address bit is permanently strapped to a &#34;0&#34; so that each multiplexer and decoder looks at only 2 inputs or outputs. The multiplexer IC40 looks at the &#34;RQ&#34; leads from two ITM&#39;s, ITM1 and ITM2, connected to the X1 and X0 inputs respectively. When input &#34;A&#34; of the multiplexer IC40, connected to Q4 of the counter IC47, is at a &#34;1&#34;, the &#34;RQ&#34; lead from ITM 1 is connected to the multiplexer output &#34;Z&#34;; when input &#34;A&#34; is at a &#34;0&#34;, the &#34;RQ&#34; lead from ITM 2 is connected to &#34;Z&#34;. IT can be seen that the CCM in this manner looks at all of the INC TRKS in one ITM, then switches to the other ITM to look at its INC TRKS. Normally (not in TEST SEQUENCE) the &#34;strobe&#34; input (ST) of the multiplexer IC40 is at a &#34;0&#34; meaning that the multiplexer is permanently enabled. When not in a FAULT LOCATING SEQUENCE, 3-state inverting gates IC41 are disabled, having no effect on the &#34;RQ&#34; leads. As the counter is scanning, the pulses on pin 4 of IC38 are also routed to the enable input (E) of decoder IC42 (FIG. 4) via NOR gate IC43 (FIG. 3). This routes &#34;interrogation pulses&#34; to the &#34;TE&#34; lead of the addressed ITM. 
     An enable instruction is sent to the ITM when a service request is received. When the counter IC47 reaches the address of an INC TRK requesting service, the corresponding &#34;RQ&#34; lead will go to a &#34;1&#34; which will be routed from the multiplexer IC 40 output via inverter IC44 to give a &#34;0&#34; at pin 1 of IC45. If the &#34;1&#34; on the &#34;RQ&#34; lead is a true service request--not just an interrogation response--then it will remain there until serviced by the CCM. Therefore, on the next clock half-cycle (Q output of IC36 goes to a &#34;0&#34;) both inputs of OR gate IC45 will be at &#34;0&#34; and pin 3 will go to a &#34;0&#34;, setting &#34;SCA&#34; latch IC46. This cuts off the clock pulses from the counter by placing a &#34;1&#34; on pin 5 of IC38 via OR gate IC49, forcing pin 4 of IC38 to a &#34;0&#34; and the clock input to a &#34;1&#34;. The &#34;1&#34; on the &#34;Q&#34; output of IC46 also triggers the &#34;EN&#34; monostable IC50 (FIG. 5) on the &#34;A&#34; input via differentiator C26, R32. 
     When the &#34;EN&#34; monostable IC50 has been triggered, it produces a high-going pulse on its &#34;Q&#34; output and a low-going pulse on its &#34;Q&#34;output. The duration of each pulse is determined by C28, R35. 
     The &#34;0&#34; pulse from the Q output of EN monostable IC50 enables decoder IC51, resulting in a similar pulse on the &#34;EN&#34; lead of the addressed ITM. The ITM should then load the pre-selected OG TRK address into its latches, return the address on OC1,2,4 as confirmation together with a busy signal on the OC-DR lead, remove the service request on the &#34;RQ&#34; lead and operate the SW MTX relay in the manner previously discussed. The &#34;0&#34; pulse on the &#34;Q&#34; output of EN monostable IC50 also sets the &#34;ENF&#34; latch IC53 (FIG. 6) via OR gate IC54. IC54 provides a small delay on the leading edge of the pulse since both inputs must go to a &#34;0&#34; before the output goes to a &#34;0&#34; and pin 9 is delayed by R7, C6. This delay is to match the same delay in the ITM (discussed previously) because the output of IC54 also connects to the fault locating circuitry discussed below. The ENF latch, when set, places a &#34;0&#34; via inverter IC55 on pin 6 of IC33, (FIG. 5), preventing any further clocking of the OG TRK counter IC 34 until the ENF latch IC53 has been reset (end of call set up). This prevents the counter IC34 from clocking to the next idle OG TRK as soon as the ground from the INC TRK &#34;S&#34; lead is switched to the OG TRK &#34;S&#34; lead (i.e. when the OG TRK relay operates). 
     Operation of the OG TRK relay and cut-through will not be discussed. 
     As soon as the SW MTX relay K101 in the ITM operates (FIG. 1), the ground from the INC TRK &#34;S&#34; lead is switched to the &#34;S&#34; lead of the corresponding OG TRK relay, and thence via the normally closed contacts to the &#34;ST&#34; lead multiple (FIG. 8). This turns on transistor Q301 via resistor R33 and collector load R35. Diode CR10 protects the base-emitter junction against any voltage more negative than -10V, and resistor R34 ensures proper turn-off. When transistor Q301 turns ON it puts a &#34;0&#34; on the input of inverter IC57 (FIG. 11) via resistor R301, giving a &#34;1&#34; on pin 3 of IC58. Since the &#34;ENF&#34; latch IC53 (FIG. 6) has been set, and the TST latch IC60 (FIG. 3) has not been set, there will be &#34;1&#39;s&#34; on pins 4 and 5 of IC58 (FIG. 11) and the output will go to a &#34;0&#34; enabling decoder IC61 (FIG. 10) from its &#34;D&#34; input. Since the decoder is addressed from the OT-1,2,4 leads via inverters IC31, it will place a &#34;1&#34; on the output corresponding to the selected OG TRK. This turns PNP transistor Q901 ON via inverter IC62 and resistor R901, operating the OG TRK relay &#34;OG&#34;. Diode CR901 protects transistor Q901 from back emf spikes from the relay OG; resistor R902 ensures proper turn-off of the transistor. As soon as the relay OG operates, all leads from the SW MTX--T1, R1, SP1, S1--are switched through to the T, R, SP, S leads (see FIG. 10) which connect to the outgoing repeater in the external system. The ground on the S1 lead therefore appears on &#34;S&#34; lead, turning transistor Q202 on and ensuring that the OG trunk will appear busy to succeeding calls. With Q202 on, -10v at the collector of Q202 is connected via the OG TRK relay contact and resistor R903 to the base of transistor Q901, thus providing a holding path for Q901 and the OG TRK relay. The function of C606, R301 (FIG. 11) can now be explained. The OG TRK relay is initially operated by means of the ground on the &#34;ST&#34; lead, via Q301 (FIG. 8) and the decoder IC61 (FIG. 10) etc. However, as soon as the relay begins to operate, the ground will be broken away from the &#34;ST&#34; lead and transferred to the &#34;S&#34; lead; the function of C606 is to delay the removal of the drive signal until the relay has had time to fully operate--at which time it is held via Q202, R903, etc., (FIG. 10). When Q301 turns on, the delay on the operate signal to the decoder is relatively short, being determined by the time constant (R301×C606). However, when Q301 turns off, a much longer delay is introduced, being determined by the time constant [(R35+R301)×C606], where R35 is several times larger then R301. 
     As soon as the holding path to the OG relay has been established, the release of the OG trunk relay is under control of the ground on the &#34;S&#34; lead. On release, the ground disappears from the &#34;S&#34; lead and Q202 turns off, removing the drive to Q901 via R903. The delay in the ITM on release (discussed earlier) ensures that the OG TRK relay releases first, permitting the SW MTX relay to operate and release under so-called &#34;dry&#34; circuit conditions. 
     Release of the CCM for processing other calls will now be discussed. At the same time as the &#34;EN&#34; pulse was sent out, the &#34;TIM&#34; monostable IC65 (FIG. 6) was triggered on its &#34;A&#34; input from the &#34;Q&#34; output of EN monostable IC50 (FIG. 5). The width of the low-going pulse on the &#34;Q&#34; output of TIM monostable IC65 is determined by C34, R41 and is chosen to be greater than the worst case operate time of the OG TRK relays. On the trailing edge of the pulse (i.e. high-going), a &#34;1&#34; pulse is produced by differentiator C37, R44 on the TIM lead. The &#34;TD&#34; monostable IC66 (FIG. 5) will not have been triggered because of not being in a test sequence, so there will be a &#34;1&#34; on pin IC67 (FIG. 6). Therefore, when the &#34;TIM&#34; monostable IC65 times out, i.e. after the OG TRK relay has operated, a &#34;0&#34; pulse will be produced at the output of NAND gate IC67, setting the &#34;GDT&#34; latch IC68. This gives a  &#34;1&#34; to pin 5 of IC70. Since no fault has been encountered, the &#34;FL&#34; latch IC71 (FIG. 4) will not have been set and there will be a &#34;1&#34; on pin 6 of IC70. This produces a &#34;1&#34; on the output of IC72 (FIG. 7) via resistor R31, which triggers the &#34;RST&#34; (reset) monostable IC74 on its &#34;A&#34; input. This produces a low-going pulse (width determined by C29, R36) on its &#34;Q&#34; output, which connects to all latch reset inputs (R). In this way, at the end of the sequence setting-up the switching path, all latches are reset and the CCM proceeds to start looking for the next service request (INC TRK counter IC47 (FIG. 3) re-starts because &#34;SCA&#34; IC46 is reset, allowing clocking again through IC38). 
     Power reset is as follows. 
     When the power is initially turned on in the unit, capacitor C31 (FIG. 6) is discharged. This places a &#34;O&#34; (-10v) on the &#34;B&#34; trigger input of the &#34;RST&#34; monostable IC74, triggering the monostable which resets all latches, etc. It also connects to the &#34;CD&#34; input of the &#34;TD&#34; monostable IC66 (FIG. 5) holding that reset. Capacitor C31 charges through resistor R38, eventually removing the reset trigger. 
     A test call will now be described. 
     Activation of the &#34;TE&#34; lead to the ITM will be discussed first. 
     At pre-determined time intervals a &#34;1&#34; pulse is produced at the DECODE OUT pin 13 of IC35 (FIG. 3). The timing interval is produced internally in IC35 by dividing down the internal oscillator frequency determined by C3, R4 and R5. Selection of the time interval is achieved by strapping inputs A, B, C, D to O&#39;s or l`s. The binary number set up on A, B, C, D determines the number of counter stages included in the divider chain. Resistor R2 and capacitor C1 are the timing components of an internal monostable, determining the width of the output pulse at pin 13 (DECODE OUT). 
     The &#34;1&#34; pulse at pin 13 of IC35 sets the &#34;TST&#34; latch, IC60, via inverter IC75. This in turn sets the &#34;TE&#34; latch IC76 via inverter IC77 and differentiator C30, R37. The &#34;0&#34; at the output of IC77 (i.e. on the &#34;TST&#34; lead) forces pin 10 of NAND gate IC78 to a &#34;1&#34; cutting off the clock pulses to counter IC47 via OR gate IC49 and pin 5 of IC38. This stops the counter IC47 at the INC TRK it happens to be addressing when the timer, IC35, operates (i.e. random selection of tested INC TRK). The &#34;1&#34; from the output of the &#34;TE&#34; latch IC76 places a solid &#34;0&#34; on the enable (E) of decoder IC42, via NOR gate IC43. This sends a solid &#34;0&#34; to the addressed ITM on its &#34;TE&#34; lead, which should cause the ITM to start operating its &#34;A&#34; relay to ground the leads of the incoming trunk, this action having been discussed above. 
     The test sequence is reset if the incoming trunk is busy, as follows. 
     If the incoming trunk is busy, it will send back a &#34;0&#34; on the &#34;OC-CR&#34; bus to the CCM. This places a &#34;0&#34; on pin 13 of IC80 (FIG. 4). Since the &#34;TST&#34; latch has been set, there will also be a &#34;0&#34; on pin 12, giving a &#34;1&#34; on pin 11 of IC80 and on pin 5 of IC81 (FIG. 6). Pins 3 and 4 of IC81 will also be at &#34;1&#39;s&#34; (&#34;FL&#34; latch not set, &#34;ENF&#34; latch not set) so a &#34;0&#34; will be produced at pin 6 of IC81, triggering the &#34;RST&#34; monostable IC74 on its &#34;A&#34; input via NAND gate IC72. This resets the TEST SEQUENCE by resetting both &#34;TST&#34; and &#34;TE&#34; latches by the &#34;0&#34; pulse on their &#34;R&#34; inputs. The &#34;TE&#34; latch is reset via AND gate IC83. 
     It the INC TRK is idle, no signal should be returned on the &#34;OC-DR&#34; bus, but a &#34;1&#34; should be returned on the &#34;RQ&#34; lead. Initially, a short pulse will be returned on the &#34;RQ&#34; lead in response to the leading edge of the &#34;TE&#34; signal. This, however, will be ignored by the CCM, because when the &#34;TST&#34; latch IC60 is set, a &#34;0&#34; is placed on pin 9 of IC84. Initially, pin 8 of IC84 will also be at a &#34;0&#34; because capacitor C8 is discharged (previously pin 5 of IC85 was at a &#34;1&#34;). Therefore, pin 10 of IC84 will initially be at a &#34;1&#34;, disabling multiplexer IC40 by means of its strobe input, ST. As soon as capacitor C8 has charged sufficiently through resistor R8, however, from the &#34;0&#34; on pin 5 of IC85 from the &#34;TE&#34; latch, pin 10 of IC84 will go to a &#34;0&#34;, enabling multiplexer IC40. Resistor R8 and capacitor C8 are chosen so that by the time IC40 is enabled, the &#34;A&#34; relay should have operated (in the ITM), placing a solid &#34;1&#34; on the &#34;RQ&#34; lead. This &#34;1&#34; will set the &#34;SCA&#34; latch IC46 via IC44 and IC45 as soon as the clock goes to a &#34;0&#34; on pin 2 of IC45. When the SCA latch IC46 is set, the EN monostable IC50, (FIG. 5) is triggered, sending an &#34;EN&#34; signal to the addressed ITM, and the &#34;TIM&#34; monostable is triggered, in the same way as described previously. The ITM should start operating the pre-selected SW MTX relay in the same way as for a regular call. 
     An open circuit check will now be described. 
     At the same time that the &#34;EN&#34; monostable is triggered, the &#34;1&#34; pulse from C26, R32 is NANDed with the &#34;1&#34; from the output of the &#34;TST&#34; latch by means of IC87 (FIG. 5), giving a &#34;0&#34; pulse on the &#34;CX&#34; lead to pin 9 of IC90, (FIG. 9). If the output from the &#34;open circuit&#34; comparators IC91 and IC92, connected to pin 8 of IC90, is a &#34;1&#34;, indicating &#34;open circuit&#34; then pin 10 of IC90 will be forced to a &#34;0&#34; producing no pulse to initiate a fault locating sequence. This checks that none of the contacts of the selected SW MTX relay are shorted together. At the same time, the &#34;A&#34; relay in the ITM has operated, placing grounds on all four INC TRK leads T, R, SP, S, but the SW MTX relay has not yet had time to operate since the &#34;EN&#34; signal has only just been sent out. If any contact was shorted, a ground would be seen on one of the leads T1, R1, SP1, or S1 (FIG. 8). 
     Operation of the &#34;open circuit&#34; and &#34;continuity&#34; comparators, FIG. 8, will now be described. 
     Resistors R36 and R38 form a potential divider, producing a potential of approximately -8v at their junction if resistors R29-R32 are open circuit at their other ends, i.e. the TT, RT, SPT, and ST leads. This is the condition when all leads T1, R1, SP1 and S1 are &#34;open circuit&#34;. The values of R49, R50 and R51, forming another potential divider, are chosen such that the potential at the junction of R49 and R50 is slightly higher than -8v, and the potential at the junction of R50 and R51 is slightly lower than -8v. Therefore, when &#34;open-circuit&#34; the output of analogue compatator IC91 by itself would be a &#34;1&#34; since the inverting input (-) is slightly lower than its non-inverting input (+). Similarly, the output of analogue comparator IC92 by itself would also be a &#34;1&#34;, since its non-inverting input (+) is slightly higher than its inverting input (-). Each comparator has an &#34;open collector&#34; output circuit (equivalent to an NPN transistor with no collector load resistor) so that the outputs of the two comparators can be wired together to a common load resistor, R47. Only when both outputs would by themselves be a &#34;1&#34; is a &#34;1&#34; produced when connected together. If any potential (other than -8v) is connected to any of the leads TT, RT, SPT, ST, then the potential at the input of the comparators will no longer be at -8v, and one of them will produce a &#34;0&#34; at the output. Only when all leads are &#34;open circuit&#34; will a &#34;1&#34; be produced. 
     The &#34;continuity&#34; comparators IC93 and IC94 function in exactly the same way, except that potential divider R52, R53, R54 has values chosen so that the &#34;window&#34; provided by R53 is centered around approximately -2v, instead of -8v. Resistors R29, R30, R31 and R32 are equal value resistors chosen so that when all leads TT, RT, SPT, ST are grounded then the parallel resistance of R29-R32 and R36 will also give a potential of -2v at the inputs of the comparators IC93 and IC94. Only when all four leads are grounded (indicating continuity of all leads through the SW MTX relay from the &#34;A&#34; relay grounds) will the output of the &#34;continuity&#34; comparators be a &#34;1&#34;. Any lead which is &#34;open circuit&#34;, or connected to any other potential, will cause the output to go to a &#34;0&#34;. 
     The small &#34;windows&#34; provided by R50 and R53 allow for slight deviations from the theoretical, due to component tolerances, etc. Resistors R39-R42 limit the current into the inputs of the comparators should the inputs go outside of the 10v supply range, but have almost no effect on the voltage comparison because of the normally very high input impedance. 
     The &#34;continuity&#34; check will now be discussed. 
     When the &#34;TIM&#34; monostable IC65 (FIG. 6) times out, it produces a &#34;1&#34; pulse on the &#34;TIM&#34; lead via C37, R44, as described before. However, at this time, the &#34;GDT&#34; latch IC68 is not set, because there is a &#34;0&#34; on pin 3 of IC67 from the &#34;Q&#34; output of the &#34;TD&#34; monostable IC66 (FIG. 5). The &#34;TD&#34; monostable IC66 was triggered via IC95 at the same time as the &#34;EN&#34; was sent out, from the &#34;1&#34; on the &#34;Q&#34; output of the &#34;EN&#34; monostable and the &#34;1&#34; on the output of the &#34;TST&#34; latch IC60 (FIG. 3). The time interval of TD monostable IC66 (FIG. 5) is chosen to be slightly greater than that of the TIM monostable IC65 (FIG. 6). 
     The &#34;1&#34; pulse on the &#34;TIM&#34; lead gives a &#34;0&#34; pulse on pin 11 of IC100 (FIG. 9) via inverter IC101. Since the GDT latch has not operated, there is also a &#34;0&#34; on pin 12 of IC100 and the output will be determined by pin 13. 
     By this time, the SW MTX relay in the ITM should have operated so there should be &#34;continuity&#34; of all four leads and the output of the &#34;continuity&#34; comparators IC93 and IC94 (FIG. 8) should be a &#34;1&#34;. Since there should be a ground on the &#34;ST&#34; lead, Q301 (FIG. 8) turns ON, producing a &#34;1&#34; on pin 9 of IC102 via inverter IC103. Therefore, the output of AND gate IC102, connected to pin 13 of IC100, should be at a &#34;1&#34;, forcing pin 10 of IC100 to a &#34;0&#34; and preventing the initiation of a fault locating sequence. 
     De-activation of the &#34;TE&#34; lead to the ITM is accomplished as follows. 
     After the above described check has been made, the &#34;TD&#34; monostable IC66 (FIG. 5) will time-out, producing a &#34;0&#34; pulse at the junction of C36, R43 from its &#34;Q&#34; output. This re-triggers the &#34;TIM&#34; monostable IC65 (FIG. 6) on its &#34;B&#34; input, and resets the &#34;TE&#34; latch IC76 (FIG. 3) via AND gate IC83. The GDT latch IC68 (FIG. 6) will still not be set because the &#34;TIM&#34; pulse will have disappeared. 
     Resetting the &#34;TE&#34; latch IC76 will remove the &#34;0&#34; on the &#34;TE&#34; lead to the addressed ITM, via decoder IC42 (FIG. 4) and IC43 (FIG. 3). This in turn will cause the ITM to release the &#34;A&#34; relay removing the grounds from all four leads T, R, SP, S. 
     Reset of the test sequence and release of the CCM is as follows. 
     When the &#34;TIM&#34; monostable IC65 (FIG. 6) times out again, the GDT latch IC68 will be set (Q) output of TD monostable IC66, FIG. 5, is now back to a &#34;1&#34;) and the &#34;RST&#34; monostable IC74 will be triggered, resetting all sequencing latches allowing the INC TRK counter IC47 to start scanning again, in the same way as at the end of a regular call set up sequence. The purpose in re-triggering the TIM monostable IC65 and waiting for its time out is to allow time for the &#34;A&#34; relay in the ITM to release before resetting the test sequence and allowing INC TRK scanning, so that the ground on the &#34;S&#34; lead from the &#34;A&#34; relay will not be seen as a regular call service request. 
     Checks and fault location while scanning for service requests will now be described. 
     While the INC TRK counter IC47 is scanning the ITM&#39;s and INC TRKs for service requests, it is interrogating each INC TRK with a &#34;0&#34; pulse on the corresponding &#34;TE&#34; lead. If the INC TRK is idle, a &#34;1&#34; pulse of similar duration should be returned immediately on the corresponding &#34;RQ&#34; lead. If the INC TRK is busy, then a &#34;0&#34; pulse of similar duration should be returned immediately on the &#34;OC-DR&#34; bus. If neither response is obtained, or if a response is obtained on both leads, then there must be a fault, either in the ITM decoder, multiplexer or random logic, or in the circuitry in the CCM which is monitoring for the response. 
     One possibility is no response on either the &#34;RQ&#34; or the &#34;OC-DR&#34; leads. The interrogation pulse subsequently routed to the &#34;TE&#34; lead of the addressed ITM by decoder IC42 (FIG. 4) appears on the enable input of the decoder and pin 5 of IC85. This produces a &#34;1&#34; pulse on pin 9 of IC105 (FIG. 4), and on pin 1 of IC106 (FIG. 3). Since the &#34;TST&#34; latch is reset, there is a &#34;1&#34; on pin 2 of IC106 and therefore a &#34;1&#34; at the output, pin 3, forcing pin 11 of IC107 to a &#34;0&#34;. This gives a &#34;0&#34; pulse to pin 12 of IC108. Pin 13 of IC108 is also at a 0 (&#34;ENF&#34; latch reset). If neither &#34;RQ&#34; nor &#34;OC-DR&#34; response is obtained, then pin 11 of IC108 will also remain at a &#34;0&#34;, from pin 11 of IC109 (pin 12 of IC109 staying at a &#34;1&#34;--no &#34;OC-DR&#34; lead response, plus pin 13 of IC109 at a &#34;1&#34; (no &#34;RQ&#34; lead response via multiplexor IC40 and inverter IC44). This gives a &#34;1&#34; pulse to pin 5 of NOR gate IC110, forcing the output pin 6 to a &#34;0&#34; and setting the &#34;FL&#34; (fault-locating) latch IC71 via inverter IC111 and NOR gate IC112. 
     Functions of the &#34;FL&#34; latch will now be described. 
     Setting the &#34;FL&#34; latch does several things simultaneously. It places a &#34;1&#34; on the &#34;DIS&#34; bus to both ITM&#39;s, causing them to remove all logic signals sent to the CCM, and switching the circuits driving the corresponding leads to a high-impedance state, discussed previously. It stops the INC TRK counter IC47 (FIG. 3) at the address of the faulty INC TRK by cutting off the clock pulses via IC38 (Q output of &#34;FL&#34; latch at &#34;1&#34; gives &#34;0&#34; on pin 8 of IC78 via inverter IC113, forcing pin 10 of IC78 to a &#34;1&#34;, giving a &#34;1&#34; on pin 5 of IC38 via OR gate IC49). It also re-activates the corresponding &#34;TE&#34; lead by a &#34;1&#34; pulse on pin 4 of IC43 via differentiator C32, R40 and NOR gate IC115, FIG. 5. Pin 4 of IC115 goes to a &#34;1&#34; because pin 6 is at a &#34;0&#34;--TST latch reset--and pin 5 is at a &#34; 0&#34;--from &#34;FL&#34; latch via IC113. Still at the same time, it removes the &#34;disable&#34; from 3-state gates IC41 (FIG. 3) via pin 8 of IC113 (FIG. 4). Since the &#34;B&#34; latch IC116 is not yet set, the common enable (pin 12) of gates IC41 is at a &#34;0&#34; and therefore the &#34;0&#34; pulse on the &#34;TE&#34; lead will be &#34;looped back&#34;, as a &#34;1&#34; pulse onto the corresponding &#34;RQ&#34; lead via one of the gates IC41. If the multiplexer IC40 and inverter IC44 are not faulty, then a &#34;0&#34; pulse will be returned on pin 6 of IC117 (FIG. 4) and therefore on pin 4 of IC117 and on pin 5 of IC118. Pin 6 of IC118 will also be at a &#34;0&#34; from the &#34;FL&#34; latch via IC113, so that the pulse at the output will set the &#34;B&#34; latch, IC116. 
     There will now be described the action of the circuitry in case of a fault in the CCM related to the &#34;RQ&#34; lead. 
     If the &#34;B&#34; latch IC116 is not immediately set as a result of the &#34;looped back&#34; &#34;RQ&#34; signal--indicating a fault in the CCM--then the &#34;0&#34; on pin 5 of IC120 together with the 0 on pin 6 (&#34;ENF&#34; latch reset) will produce a &#34;1&#34; on pin 8 of IC121, forcing pin 9 to a &#34;0&#34; and setting the &#34;CAL&#34; (CCM alarm) latch IC122 via IC123 (pin 12 of IC123 at a &#34;0&#34; from &#34;0&#34; on pin 8 of IC113) and IC124. Setting the &#34;CAL&#34; latch IC122 lights &#34;CCM ALM&#34; LED via emitter follower transistor Q401 and resistor R401. 
     If the &#34;RQ&#34; signal looped back is recognized by the CCM, then the &#34;B&#34; latch is set so quickly after the &#34;FL&#34; latch is set that pin 13 of IC123 goes to a &#34;1&#34; almost immediately after pin 12 goes to a &#34;0&#34;. Any very short pulse that might get through IC123 to set the &#34;CAL&#34; latch is removed by a small capacitor C401. 
     When the &#34;B&#34; latch is set, it places a &#34;1&#34; on the common enable, pin 12, of gates IC41, (FIG. 3), forcing all outputs to a &#34;0&#34;. This removes the &#34;looped back&#34; &#34;RQ&#34; signal and places a &#34;looped back&#34; &#34;OC-DR&#34; signal on the &#34;OC-DR&#34; lead via gate IC151 (FIG. 4). 
     The circuitry can recognize a fault in the CCM related to the &#34;OC-DR&#34; lead, as follows. 
     If the CCM does not recognize the looped back &#34;0&#34; on the &#34;OC-DR&#34; lead, then both inputs of IC124 (OC-DR lead and output of &#34;B&#34; latch) will be at a &#34;1&#34; giving a &#34;1&#34; to pin 1 of IC121 which forces the output to a &#34;0&#34; and sets the &#34;CAL&#34; latch and lights the CCM ALM LED as before. 
     An ITM fault may be related to either the &#34;RQ&#34; or &#34;OC-DR&#34; leads. If the CCM does recognize the &#34;looped back&#34; &#34;0&#34; on the &#34;OC-DR&#34; lead, then, since it has already checked the &#34;RQ&#34; response &#34;looped back&#34; and found it to be satisfactory (otherwise the &#34;B&#34; latch would have been set and a CCM ALM would have been activated), therefore the fault must be with the ITM. A &#34;0&#34; on the &#34;OC-DR&#34; lead will place a &#34;1&#34; on pin 12 of IC125 via inverter IC126. Provided the &#34;RQ&#34; lead has returned to a &#34;0&#34; there will also be a &#34;1&#34; on pin 13 of IC125, giving a &#34;1&#34; to pins 2 and 8 of IC130. Pin 1 of IC130 will also be at a &#34;1&#34; since the &#34;ENF&#34; latch is reset, so a &#34;0&#34; will appear on pin 8 of IC131 and thence on pin 10 of IC131. This gives a &#34;0&#34; on both inputs of IC132 (other input at a &#34;0&#34; from IC113) in turn giving a &#34;0&#34; to the &#34;enable&#34; of decoder IC133. Since the decoder IC133 is addressed to the same ITM by means of it &#34;A&#34; input, the &#34;0&#34; will be routed to the latch (part of IC134) corresponding to the faulty ITM. The latch will be set, placing a &#34;1&#34; on the corresponding &#34;ALM&#34; lead, via emitter follower transistor Q402 or Q403, to light the ITM alarm LED in the ITM. 
     Another possible fault is a response on both the &#34;RQ&#34; and &#34;OC-DR&#34; leads. If, when the ITM is interrogated, a response is obtained on both of these leads, then both inputs to IC135 will go to a &#34;0&#34; giving a &#34;1&#34; on pin 8 of IC105. This is ANDed with the &#34;1&#34; pulse on pin 9 (from the &#34;TE&#34; interrogation pulse) to give a &#34;1&#34; to pin 3 of IC110, forcing the output to a &#34;0&#34; and setting the &#34;FL&#34; latch as before. Exactly the same &#34;loop-back&#34; sequence is then initiated. If everything is satisfactory after the ITM is disabled, then the fault is in the ITM and the alarm is activated in an identical manner as before. If both &#34;RQ&#34; and &#34;OC-DR&#34; responses are still obtained simultaneously after setting the &#34;FL&#34; latch IC71 and &#34;looping back&#34;, then the &#34;1&#34; at pin 3 of IC135 will force the output of IC121 to a &#34;0&#34; and set the &#34;CAL&#34; latch and light the &#34;CCM ALM&#34; LED, as before. 
     The CCM is released and the fault locating sequence reset on the occurrence of an alarm. When either a CCM or an ITM alarm is activated, a &#34;0&#34; pulse will appear at one of the inputs of IC136. This gives a &#34;0&#34; pulse to pin 11 of IC72 (FIG. 6), forcing the output to a &#34;1&#34; and triggering the &#34;RST&#34; monostable IC74. This resets all the sequencing latches and allows the counter IC47 to continue scanning the INC TRKS. Checks and fault location are also carried out while setting up a switching path. When the CCM recognizes a service request and starts setting up a switching path by placing a &#34;0&#34; on the &#34;EN&#34; lead of the addressed ITM, several checks are made at the same time, as will now be described. 
     A check is made of the latched OG TRK address returned from the ITM. When the &#34;EN&#34; lead is activated, the ITM loads the OG TRK address into its latches IC4 (FIG. 1) after a very small delay, and returns the latched-in address (inverted) on the OC-1, 2, 4 bus leads, as discussed before. Digital comparator IC140 (FIG. 11) is connected to the inverted OT-1, 2, 4 bus leads (inputs A0, A1, A2) and the OC-1, 2, 4 bus leads (inputs B0, B1, B2). 
     One inversion of the &#34;OT&#34; leads in the CCM, and one inversion of the &#34;OC&#34; leads in the ITM make the comparison a valid one. When the binary word on the &#34;A&#34; inputs of the comparator exactly matches the word on the &#34;B&#34; inputs, then the (A=B) OUT output will go to a &#34;1&#34; (fourth bit A3, B3 is not used and is strapped to ground; other inputs are only used when comparators are cascaded for words larger than four bits and are either strapped to ground or -10v). 
     If the address returned on the &#34;OC&#34; leads does not match, then the output of the comparator will stay at a &#34;0&#34; when the &#34;ED&#34; lead (&#34;EN&#34; with leading edge delayed by a small amount to match the delay in the ITM) goes to a &#34;0&#34;. This produces a &#34;0&#34; pulse at pin 3 of IC141 (FIG. 9) forcing pin 6 of IC142 to a &#34;1&#34; and setting the &#34;FL&#34; latch via the &#34;SF&#34; lead and IC112 (FIG. 4). As soon as the &#34;FL&#34; latch is set, the gates in the ITM are disabled as before, but three state gates IC143 (FIG. 11) are enabled, &#34;looping-back&#34; the OT-1, 2, 4 leads (inverted) onto the OC-1, 2, 4 leads. If the fault still persists--indicating a CCM fault--then the output of the comparator will stay at a &#34;0&#34; and there will now be a &#34;0&#34; on both inputs of IC145 (FIG. 9) since the &#34;LA&#34; lead from the &#34; FL&#34; latch via IC113 (FIG. 4) will now be at a &#34;0&#34;. This gives a &#34;1&#34; at pin 13 of IC146, forcing the output to a &#34;1&#34; and setting the &#34;CAL&#34; latch via the &#34;CAL&#34; lead and IC124 (FIG. 4). This lights the CCM ALM LED as before. If the address &#34;looped-back&#34; matches, implying that the fault is in the ITM, then there will be no &#34;1&#34; at pin 13 of IC146 and the &#34;CAL&#34; latch will not be set. In this case, no alarm will be set until the &#34;GDT&#34; latch is set. Although a fault has been detected, the &#34;TIM&#34; monostable will still have been triggered when the &#34;EN&#34; pulse was sent out, and when the &#34;TIM&#34; monostable times out, the &#34;GDT&#34; latch will be set as before. When the GDT latch IC68 (FIG. 6) is set, a &#34;0&#34; is placed on pin 9 of IC131 (FIG. 4) via inverter IC147 and resistor R402. This gives a &#34; 0&#34; on pin 10 of IC131. Since the &#34;FL&#34; latch is set, both inputs of IC132 are at &#34;0&#34; and the decoder IC133 is enabled, activating the corresponding ITM ALM as described before. If a CCM alarm had been detected, the ITM alarm would not have been actuated in this way, because the CCM alarm would have triggered the &#34;RST&#34; monostable, resetting the sequence before the &#34;TIM&#34; timed out and set the &#34;GDT&#34; latch. Actually, when the &#34;RST&#34; monostable is triggered, it resets the &#34;TIM&#34; monostable immediately via its &#34;CD&#34; input causing a &#34;1&#34; pulse via C37, R44 at pins 4 and 5 of IC67, but this cannot set the &#34;GDT&#34; latch, because the latch is simultaneously being held reset on its &#34;R&#34; input. 
     A check of conditions on the &#34;RQ&#34;, &#34;OC-DR&#34; leads is also made after loading the ITM. When the &#34;EN&#34; lead is activated, the ITM should remove the &#34;1&#34; from its &#34;RQ&#34; lead and place a &#34;0&#34; on the &#34;OC-DR&#34; bus as discussed before. If the CCM continues to see a &#34;1&#34; on the corresponding &#34;RQ&#34; lead, there will be a &#34;0&#34; on pin 13 of IC125 (FIG. 4) via multiplexer IC40 and inverter IC44 (FIG. 3) If the CCM continues to see a &#34;1&#34; on the &#34;OC-DR&#34; bus, there will be a &#34;0&#34; on pin 12 of IC125, via inverter IC126. Either fault condition will produce a &#34;0&#34; on pin 8 of IC150 which, together with the &#34;0&#34; on pin 9 of IC150 from the delayed &#34;EN&#34; signal (&#34;EN&#34; monostable Q output and IC54) will give a &#34;1&#34; to pin 4 of IC110, forcing the output to a &#34;0&#34; and setting the &#34;FL&#34; latch via IC111 and IC112. 
     As soon as the &#34;FL&#34; latch is set, the gates in the ITM will be disabled by means of the &#34;DIS&#34; lead as before. 
     This time, however, since the &#34;O&#34; pulse from the Q output of the &#34;EN&#34; monostable IC50 will not yet have disappeared, there will be a &#34;0&#34; on pin 5 of IC117 and therefore a &#34;0&#34; on pin 5 of IC118. Since the &#34;FL&#34; latch is set, there will also be a &#34;0&#34; on pin 6 of IC118 via IC113. This produces a &#34;0&#34; pulse at the output, immediately setting the &#34;B&#34; latch IC116. This causes &#34;O&#34; on the &#34;OC-DR&#34; lead to be &#34;looped-back&#34; via IC151. If the CCM continues to see a &#34;1&#34; on the &#34;OC-DR&#34; lead, then there will be a &#34;1&#34; on both inputs of IC124 (pin 5 at a &#34;1&#34; from the &#34;B&#34; latch) giving a &#34;1&#34; to pin 1 of IC121, forcing the output to a &#34;0&#34;. Since the &#34;FL&#34; latch is set, there will be &#34;0&#39;s&#34; on both inputs of IC123 and the &#34;CAL&#34; latch will be set via IC124 and the CCM ALM LED lit, as before. If the CCM continues to see a &#34;1&#34; on the &#34;RQ&#34; lead (but there is no fault with the &#34;OC-DR&#34; lead) then there will be a &#34;0&#34; on both inputs of IC135 giving a &#34;1&#34; to pin 2 of IC121--forcing the output to a &#34;O&#34; and activating the CCM alarm as before. 
     If, after the &#34;FL&#34; latch is set, the correct conditions are seen on the &#34;RQ&#34; and &#34;OC-DR&#34; leads, then no CCM alarm will be activated, and, as described before, an ITM alarm will be activated when the &#34;TIM&#34; monostable times out setting the &#34;GDT&#34; latch. 
     Checks and fault location are also made while making a test call. For example, a check for service request is made after activating the &#34;TE&#34; lead. When the CCM has initiated a test call by activating the &#34;TE&#34; lead to the addressed ITM, it waits to allow for the operate time of the ITM &#34;A&#34; relay, as discussed earlier. After this delay, determined by R8, C8, FIG. 3, it looks to see if a service request (&#34;1&#34;) has been returned on the &#34;RQ&#34; lead; if none is present then a fault must exist in the ITM or CCM. 
     After the &#34;TE&#34; latch is set, a &#34;1&#34; is produced at pin 12 of IC107 via IC43 and IC85 after the delay determined by R8, C8. This forces the output of IC107 to a &#34;0&#34; giving a &#34;0&#34; to pin 12 of IC108 (FIG. 4). If no &#34;1&#34; has been returned on the &#34;RQ&#34; lead, then pin 13 of IC108 will also be at a &#34;0&#34;, since the &#34;EN&#34; monostable will not have been triggered, and the &#34;ENF&#34; latch will not have been set. Also, both inputs of IC109 will be at a &#34;1&#34; forcing pin 11 of IC108 to a &#34;0&#34;. The &#34;OC-DR&#34; lead on pin 12 of IC109 must be at a &#34;1&#34;, since otherwise it would indicate a busy INC TRK, and this would have immediately reset the test sequence before time out of R8, C8. Since all three inputs of IC108 are at &#34;0&#34;, a &#34;1&#34;  will be produced at pin 5 of IC110, forcing the output to a &#34;0&#34; and setting the &#34;FL&#34; latch IC71 via IC111 and IC112. Now, with the &#34;FL&#34; latch set, signals are &#34;looped-back&#34; first onto the &#34;RQ&#34; lead and then onto the &#34;OC-DR&#34; lead to determine whether the fault is in the ITM or the CCM in an identical manner to that described previously, except that the &#34;TE&#34; lead is not reactivated from IC115, C32, R40, because pin 6 of IC115 is now at a &#34;1&#34; from the output of the &#34;TST&#34; latch keeping the output at a &#34;0&#34;. It is unnecessary to re-activate the &#34;TE&#34; lead because the &#34;TE&#34; latch IC76 (FIG. 3) is keeping a solid &#34;0&#34; on it via pin 3 of IC43. 
     A check is also made on the OG TRK address and the &#34;RQ&#34; and &#34;OC-DR&#34; leads after loading of the ITM. If the CCM does see a service request on the &#34;RQ&#34; lead, then it will activate the corresponding &#34;EN&#34; lead and make exactly the same checks as discussed before. That is, it will check that the address returned on the OC-1, 2, 4 leads matches the address sent to the ITM on the OT-1, 2, 4 leads and it will check that the service request has been removed and the &#34;OC-DR&#34; lead activated. If any condition is not met, then it will set the &#34;FL&#34; latch IC71 and make the &#34;loop-back&#34; tests and activate the appropriate alarm as described before. The only difference is, that if an ITM fault is diagnosed, the &#34;GDT&#34; latch will not be set and an ITM alarm activated until the &#34;TIM&#34; monostable has timed out a second time, i.e. after the &#34;TD&#34; monostable has timed out. 
     A check is also made on the SW MTX contacts for &#34;open circuit&#34; and &#34;continuity&#34;. When the service request is returned from the ITM, the &#34;1&#34; pulse from C26, R32 that triggers the &#34;EN&#34; monostable IC50 (FIG. 5) also appears on pin 2 of IC87. With the &#34;1&#34; on pin 1 of IC87 from the &#34;TST&#34; latch, a &#34;0&#34; pulse is produced on the &#34;CX&#34; lead to pin 9 of IC90 (FIG. 9). At this time, the output of the &#34;open circuit&#34; comparators IC91 and IC92 appearing on pin 8 of IC90 should be at a &#34;1&#34; indicating &#34;open circuit&#34; of all four leads T1, R1, SP1, S1. If, instead, pin 8 of IC90 is at a &#34;0&#34; then a &#34;1&#34; pulse will be produced at the output, forcing pin 11 of IC155 to a &#34;0&#34; and giving a &#34;1&#34; pulse on the &#34;SF&#34; lead via IC142 to set the &#34; FL&#34; latch via IC112 (FIG. 4). 
     When the &#34;TIM&#34; monostable times out, it produces a &#34;0&#34; pulse on pin 11 of IC100 (FIG. 9) via the &#34;TIM&#34; lead and inverter IC101. The &#34;GDT&#34; latch will not yet have been set, so there will also be a &#34;O&#34; on pin 12 of IC100. 
     At this time, there should be a &#34;1&#34; on pin 13 of IC100 from IC102, indicating &#34;continuity&#34; or grounds on all four leads T1, R1, SP1, S1. If, instead, pin 13 is at a &#34;0&#34; then pin 10 of IC100 will go to a &#34;1&#34; forcing pin 11 of IC155 to a &#34;0&#34; and setting the &#34;FL&#34; &#34;latch&#34;, as before. 
     If either of the above faults are encountered (leads not open circuit or continuous at the appropriate times) then the &#34;FL&#34; latch is set, as described, and a &#34;0&#34; will be placed on the &#34;GX&#34; lead via IC156 and IC157 (pin 2 of IC157 at a &#34;0&#34; from the &#34;FL&#34; latch via IC113, pin 8 at a &#34;0&#34; from the &#34;ENF&#34; latch via IC55 and pin 1 at a &#34;0&#34; from the &#34;GDT&#34; latch IC68 which is not yet set). A &#34;0&#34; on the &#34;GX&#34; lead will turn on PNP transistors Q804-Q807 (FIG. 8) via R21, R23, R25, R27, respectively. This places grounds on all four leads TT, RT, SPT and ST. Resistors R22, R24, R26 and R28 ensure that transistors Q804-Q807 turn off properly. If the CCM still does not recognize a &#34;continuity&#34; condition, the output of IC102 (FIG. 9) will remain at a &#34;0&#34;, giving a &#34;0&#34; on pin 8 of IC160. Since the &#34;GX&#34; lead connected to pin 9 of IC160 is also at a &#34;0&#34;, then a &#34;0&#34; will be produced on pins 12 and 13 of IC161, forcing the output to a &#34;1&#34; and putting a &#34;1&#34; on the &#34;CAL&#34; lead via IC146. This sets the &#34;CAL&#34; latch via IC124 (FIG. 4) lighting the CCM ALM LED as described previously. 
     If the CCM does recognize the &#34;looped-back&#34; &#34;continuity&#34; condition, the CCM ALM will not be activated, since pin 10 of IC102 will be at a &#34;1&#34;. In this case, no alarm will be activated until the &#34;GDT&#34; latch is set when the &#34;TIM&#34; monostable times out a second time. Then, pin 1 of IC157 goes to a &#34;1&#34;, forcing the output to a &#34;0&#34; and removing the &#34;0&#34; from the &#34;GX&#34; lead via IC156. This turns transistors Q804-Q807 (FIG. 8) off, removing the &#34;looped-back&#34; grounds from TT, RT, SPT, ST. Now the CCM should recognize an &#34;open circuit&#34; condition because, by the time the &#34;GDT&#34; latch is set, the &#34;A&#34; relay in the ITM will have released, removing the grounds from the four leads. If the CCM still does not recognize an &#34;open-circuit&#34; condition, then pin 9 of IC165 (FIG. 9) will be at a &#34;0&#34;, giving a &#34;1&#34; to pin 8 of IC166. Pin 9 of IC166 will also be at a &#34;1&#34; from the &#34;GDT&#34; latch via the &#34;GDT&#34; lead. This gives a &#34;0&#34; to one input of IC167, giving a &#34;0&#34; to pin 11 of IC161, since the other input to IC167 is also at a &#34;0&#34; from the &#34;FL&#34; latch via IC113 (FIG. 4) and the &#34;LA&#34; lead. This forces the output of IC161 to a &#34;1&#34;, setting the &#34;CAL&#34; latch and lighting the CCM ALM LED via IC146, &#34;CAL&#34; lead and IC124 (FIG. 4), as before. 
     If the CCM does recognize an &#34;open circuit&#34; condition, then the &#34;CAL&#34; latch will not be set, since pin 9 of IC165 will be at a &#34;1&#34; locking the output of IC166 to a &#34;1&#34;. Now, since the &#34;GDT&#34; latch has been set, indicating the completion of the sequence, and no CCM alarm has been activated (if it had been it would have immediately triggered the &#34;RST&#34; monostable, resetting all latches) then the fault must be in the ITM (i.e. CCM recognizes &#34;continuity&#34; and &#34;open circuit&#34; conditions satisfactorily). In this case, the &#34;1&#34; at the output of the GDT latch IC68 (FIG. 6) will produce a &#34;O&#34; at one input of IC132 via IC131, R402 and IC147. The other input of IC132 is also at a &#34;0&#34; from the &#34;FL&#34; latch via IC113 so decoder IC133 is enabled and an ITM ALM activated as described previously. The purpose of R402 (FIG. 6) in combination with C444 (FIG. 4) is to provide a small delay before setting the ITM alarm. This is necessary to allow sufficient time for a CCM alarm to be activated if, after setting the &#34;FL&#34; latch IC71, the CCM did not recognize an &#34;open-circuit&#34; condition (as described before). If there were no delay, an ITM alarm would be set as soon as the &#34;GDT&#34; latch was set. With the delay, the CCM alarm has time to be set first. Then, as soon as the CCM alarm is set, it triggers the &#34;RST&#34; monostable IC74, resetting the &#34;GDT&#34; latch and so preventing erroneous alarm. The ITM alarm should only be set if there is no CCM alarm triggered. 
     Operating the &#34;alarm reset&#34; button (top of FIG. 4), places a &#34;0&#34; on the reset inputs (R) of alarm latches IC134 and IC122. This resets any CCM or ITM alarm conditions, extinguishing the corresponding alarm LEDs. Normally the reset inputs are held to a &#34;1&#34; by resistor R445. 
     Any suitable commercially available CMOS (Complementary Metal Oxide Semiconductor) integrated circuits may be used for the gates, inverters, latches, etc., but, for convenience, the larger items may be as follows: 
     Ic4--mc14508 cp 
     ic18--mc14028 cp 
     ic13--mc14502 cp 
     ic6--mc14512 cp 
     ic10--mc14028 cp 
     ic35--mc14536 cp 
     ic36--mc14027 cp 
     ic40--mc14539 cp 
     ic46--cd4044 ae 
     ic47--mc14024 cp 
     ic60--cd4044 ae 
     ic76--cd4044 ae 
     ic42--mc14556 cp 
     ic51--mc14556 cp 
     ic116--cd4044 ae 
     ic133--mc14556 cp 
     ic134--cd4044 ae 
     ic122--cd4044 ae 
     ic71--cd4044 ae 
     ic50--mc14528 cp 
     ic34--mc14024 cp 
     ic66--mc14528 cp 
     ic65--mc14528 cp 
     ic53--cd4044 ae 
     ic68--cd4044 ae 
     ic74--mc14528 cp 
     ic91 through IC94--LM339 
     Ic61--mc14028 cp 
     ic30--mc14512 cp 
     ic140--mc14585 cp 
     all part numbers commencing with &#34;MC&#34; are manufactured by MOTOROLA and those commencing with CD are by RCA. LM339 is by NATIONAL SEMICONDUCTORS. 
     For all IC&#39;s, except IC18, V dd  =GND (OV) and V ss  =-10v. For IC18, V dd  =-10v and V ss  =-22v.