Abstract:
This disclosure discusses a programmable frequency synthesizer arrangement having programming feedback capability used to avoid undesirable operation due to random hard and soft faults. The arrangement operates by supplying appropriate programming information, receiving the same, subject to random hard or soft faults, and, in response, directing the operation of a frequency synthesizer (10). The feedback capability is accomplished by generating a feedback signal (35, 36) indicative of the programming information as applied to the frequency synthesizer, generating a reference signal representative of the appropriate programming information, comparing the two signals, and blocking undesirable operation of the frequency synthesizer if the comparison indicates the occurrence of a random hard or soft fault. Further disclosed is a wireless communications transceiver with the programmable frequency synthesizer arrangement.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to frequency synthesizers for wireless communications equipment and more particularly to such devices that include provisions for assuring the frequency synthesizer is generating the desired frequency prior to allowing, for example, the transmission of a radio frequency carrier. 
     Modern day wireless communications equipment often need the capability to routinely, rapidly, and reliably change between any two of, for example, a large number of potential radio frequency carriers with specific system critical parameters. This capability makes it possible to utilize efficient, high capacity, wireless communications technologies such as cellular telephone or trunked radio systems. This type of system, in turn, makes it feasible to satisfy, to a greater extent, the exploding demands of the wireless communications markets with a largely fixed frequency spectrum allocation. 
     The frequency synthesizer has enjoyed widespread usage and provides an economically effective way of generating, and rapidly changing between any two of, a large number of radio frequency carriers with desired parameters. To generate a specific radio frequency carrier, the frequency synthesizer must be programmed with an instruction corresponding to the desired radio frequency carrier. Some time after being programmed, depending on its dynamic characteristics, the frequency synthesizer should &#34;LOCK&#34; to the desired radio frequency carrier. To change the radio frequency carrier, the synthesizer must be reprogrammed, and allowed to &#34;LOCK&#34;, to the new frequency. During this time the frequency synthesizer will be generating undesired, i.e., unauthorized, and often system-detrimental carrier frequencies. In an effort to avoid some problems associated with the above, prior devices simply presume the synthesizer has been correctly programmed and utilize an out-of-lock indication to preclude transmission until the synthesizer is actually locked. 
     This, however, may well present a problem. If the programming accuracy presumption is in fact incorrect but nevertheless the synthesizer locks to a frequency, the equipment may be allowed to transmit on either an unauthorized frequency or, almost certainly, a system-detrimental frequency. This situation could occur in any number of ways, including, a temporary or permanent hard fault in the programming system, or a soft fault such as, controller software errors or other possibly indeterminate, intermittent causes. The net effect of these problems is almost certainly communications failure for the user of the faulty piece of equipment and very likely other users, if the equipment is allowed to transmit on an undesired frequency. Indirectly, burdens may be imposed on all users while the system attempts to compensate for the errant equipments behavior. 
     To eliminate part of these problems, such as a permanent hard fault, known prior devices have used an approach whereby the synthesizer is first programmed to a non-useful frequency, allowed to lock, and then programmed to the desired frequency. By monitoring an out-of-lock detector for an &#34;unlock,&#34; &#34;lock,&#34; &#34;unlock,&#34; and finally &#34;LOCK&#34; sequence of indications, a reasonable implication that the programming system is functioning, at least in part, can be made. This approach, while helpful, does not protect against soft or other indeterminate errors and is completely contrary to the requirement of rapidly changing to the new frequency. 
     Today&#39;s system requirements, routinely changing operating frequencies with flexible parameters, have dramatically increased the amount of information which must be successfully programmed. This only exacerbates an already potentially serious problem. 
     From the above it will be appreciated that a need exists for a frequency synthesizer programming system which provides enhanced assurance that the frequency synthesizer is locked on the desired frequency at all times and under all operating conditions. 
     SUMMARY OF THE INVENTION 
     This invention solves the aforementioned needs by providing a programmable frequency synthesizer arrangement having a programming feedback capability that is adaptable to avoid undesirable operation due to random hard and soft faults. The arrangement includes generating appropriate programming information for controlling the operation of the associated frequency synthesizer, receiving the programming information and, subject to the occurrence of random hard or soft faults, directing the operation of the frequency synthesizer, and then generating a feedback signal indicative of the programming information applied to the frequency synthesizer. A deterrence function generates a reference signal indicative of the appropriate programming information, compares this signal with the feedback signal, and then provides blocking of further undesirable operation of the frequency synthesizer whenever the above comparison indicates the occurrence of a random hard or soft fault. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The invention, itself, however together with further advantages thereof, may best be understood by reference to the accompanying drawings in which: 
     FIG. 1 is a diagram of a programmable frequency synthesizer arrangement in accordance with one embodiment of the present invention. 
     FIG. 2 is a diagram of a transceiver using the programmable frequency synthesizer of FIG. 1 in accordance with another embodiment of the present invention. 
     FIG. 3 is a diagram of a process flow chart in accordance with yet another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a frequency synthesizer arrangement is illustrated generally, which synthesizer includes programming feedback capability in accordance with the present invention. A fully programmable frequency synthesizer (10) consisting of a logic circuit (12), loop filter (13), and voltage controlled oscillator (VCO) (14), interconnected in frequency synthesizer fashion, as depicted, is used to generate an appropriate frequency synthesizer signal (15). This signal is then coupled to an injection control block (16). A processor (20) consisting, for example, of one or more microprocessor systems, performs the remaining interface and controller duties associated with operating the frequency synthesizer (10) as, for example, a source from which transmitter radio frequency carriers are derived. 
     the processor (20), acting as a controller and responding to a programming request such as, for example, &#34;Freq. Ch.&#34; (21) or &#34;PTT&#34; (22), initiates a programming task by generating appropriate programming information suitable for controlling the operation of the frequency synthesizer (10). This programming task includes composing the appropriate programming information and making it available, as, for example, serial data indicated at (25), a clock signal at (26), and a latch pulse at (27), to register (30). Register (30), part of the logic circuit (12), is adapted to receive the appropriate programming information and apply at least part of this information to direct the operation of the frequency synthesizer (10). The above described programming task, including its functions and procedures, may be subject to an occurrence of a random hard and/or soft fault, which fault, in turn, may cause undesirable operation of the frequency synthesizer. 
     To avoid this undesirable occurrence, logic circuit (12) acts to generate a feedback signal that is representative of the programming information as above applied. This feedback signal, is supplied by an &#34;AUX&#34; (31), coming from register (30), as well as that from out-of-lock detector (33), included as part of the logic circuit (12). 
     In response to the feedback signals (35, 36), a deterrence arrangement, embodied in processor (20), compares the feedback signal and a reference signal, derived from the appropriate programming information, and, based on this comparison, functions to block further undesirable operation of the frequency synthesizer (10). More particularly, processor (20) compares the &#34;AUX&#34; signal (35) to an expected value, the reference signal, and, further, confirms the absence of an out-of-lock indication (36). In the event the above comparison implies undesirable operation (occurrence of a fault) or an out-of-lock indication is detected, the processor (20) will operate to block undesirable operation of the frequency synthesizer (10) by, for example, setting an alarm (38), not enabling injection via the connection labelled &#34;Inj. En.&#34; (39) and/or repetitively initiating the programming task. Thus, undesirable operation can be effectively avoided by detecting and correcting for soft (non recurring) faults or detected and disallowed if caused by hard (recurring) faults. 
     An additional embodiment of the present invention, as shown in FIG. 2, represents such a frequency synthesizer arrangement as adapted in a wireless communications system with an associated transmitter and receiver. Elements of FIG. 2 which are identical to FIG. 1 have like reference numerals. FIG. 2 includes frequency synthesizer (10) coupled by injection control block (16) providing a transmit injection signal (44) to transmitter (45) and a receive frequency synthesizer (50), adapted to provide a receive injection signal (46) to receiver (47). Transmitter (45) uses the transmit injection signal (44) to generate a corresponding desired transmit radio frequency carrier which is then coupled to antenna (48). Receiver (47), coupled to antenna (48), uses the receive injection signal (46) to receive a corresponding radio frequency carrier and provide a corresponding desired receiver output (49). 
     Processor (20) provides a programming task and a deterrence arrangement, in a similar manner as described with reference to FIG. 1, for both the transmit frequency synthesizer (10) and the receive frequency synthesizer (50). The receive frequency synthesizer (50) feedback signal (75, 76) is coupled at (74) to processor (20) along with other receiver status signals indicated at (77) via a multiplexer (78). Processor (20), having initiated a receive frequency synthesizer (50) programming task in response to, for example, a &#34;Freq. Ch.&#34; (81), performs, in response to the feedback signal (75, 76), a receiver deterrence function in the manner described previously that may result in setting an &#34;Rx. Alarm&#34; (82) and/or repetitively initiating the programming task. 
     Appreciation of the present invention and its various embodiments can be enhanced by reviewing the simplified process flow diagram of FIG. 3. This process flow diagram is representative of a subroutine executed by processor (20) during the operation of the present invention. As indicated the frequency synthesizer initiates the start of programming at step (100). At step (101), if the transmit frequency synthesizer needs to be programmed, a PTT hold-off signal is set, thereby disabling the transmit injection signal (44) via the connection labelled &#34;Inj. En.&#34; (39) and injection control block (16). Processor (20) may then obtain the desired frequency (DF) at step (102) from, for example, memory and the current appropriate out-of-lock indication (lock status) (LS) (36 or 76). At step (103), if LS=&#34;LOCK&#34; and the last frequency (LF)=DF the left path designated &#34;no&#34; is followed to step (110). 
     If either above equality is not satisfied, processor (20), following the path designated &#34;yes,&#34; may set a desired change frequency state (DFS) at step (104). DFS may be set equal to a value derived from DF, for example, a parity check, a cyclic redundancy code (CRC), bit by bit echo, or as depicted at step (104), a value derived from the last change frequency state (LFS), for example, the inverse of LFS. LFS is representative of the most recent appropriate &#34;AUX&#34; signal (35 or 75). Given an appropriate programming information, including DF and DFS from above, an attempt to program the frequency synthesizer (10 or 50) is made at step (105). This attempt includes processor (20) generating the appropriate programming information, register (30 or 70) receiving at least part of the same and in response thereto directing the operation of the appropriate frequency synthesizer (10 or 50) and, further, generating a feedback signal (specifically &#34;AUX&#34; (31 or 71) supplies a change frequency state (CFS) and the out-of-lock detector (33 or 73) supplies LS) representative of the programming information as above applied for directing the operation of the frequency synthesizer. Processor (20) next assumes a deterrence arrangement whereby the feedback signal, specifically CFS (35 or 75) and LS (36 or 76), is retrieved at step (106) and compared to a generated reference signal indicative of the programming information, specifically DFS and &#34;LOCK&#34;, at step (107). 
     If either equality (DFS=CFS, &#34;LOCK&#34;=LS) fails, processor (20) may set the appropriate alarm (38 or 82) at step (108) and then repeat steps (105, 106, and 107). Thus, processor (20), acting as a deterrence arrangement, is blocking further undesirable operation of the frequency synthesizer whenever the above comparison indicates the occurrence of a random hard or soft fault that has corrupted the appropriate programming information. If the step (107) equalities are satisfied, the path designated &#34;yes&#34; is taken to step (109) where LFS and LF are set equal to DFS and DF respectively. At this point in the process the programmable frequency synthesizer arrangement using programming feedback has determined that the frequency synthesizer programming was properly performed. At step (110) if a transmit frequency synthesizer was being programmed the PTT hold-off signal is cleared and &#34;Inj En. (39)&#34; is now subject to PTT (22) control.