Abstract:
A latch circuit provides an equilibration voltage to a plurality of equilibrate circuits in a memory device. If a row to column short occurs which draws too much current from the latch circuit, the latch circuit will change states and cease supplying a voltage to the equilibrate circuit, thereby limiting current drain on the memory device.

Description:
FIELD OF THE INVENTION 
     The present invention relates to reducing the current drain in a memory device caused by row to column shorts. 
     DISCUSSION OF THE RELATED ART 
     As cell density of memory devices, e.g., DRAM devices, continues to increase, there is a corresponding need to reduce the amount of current drawn by such devices. One source of undesired current draw is row to column shorts. Increasing cell density also increases the number of row to column shorts which may be present in a memory device. If too much current is consumed by row to column shorts, a memory device will not meet strict specifications required for its voltage source, standby current, and self-refresh current. 
     One solution for dealing with row to column shorts is illustrated in FIG.  1 . FIG. 1 illustrates an equilibrate circuit  29  which is typically provided across the complementary digit lines  11  and  13  of a column of a memory device. The equilibrate circuit  29  includes a transistor  23  which is designed to couple the digit lines  11  and  13  together during an equilibrate operation, and a pair of transistors  25  and  27  which provide a voltage from a node A to the respective digit lines  11  and  13 . The voltage at node A is in turn supplied through a transistor  35  which has a source coupled to a voltage potential, which is typically equal to half the supply voltage Vcc, that is Vcc/2. 
     The gate of transistor  35  is coupled to a charge pump output voltage Vccp which causes transistor  35  to continuously supply the voltage Vcc/2 to node A during normal operation of a device. The equilibrate circuit  29  is activated in response to an equilibrate control signal EQ on the equilibrate line  31  to turn on transistors  23 ,  25  and  27 . Equilibration of the digit lines  11  and  13  is performed just prior to a read operation by sense amplifier  37 , which is also coupled to the complementary digit lines  11  and  13 . 
     A word line  15  is also illustrated in FIG. 1, which coupled to a gate of a memory cell access transistor  17  which serves to read out charge stored in a cell capacitor  19 . A short between a row line  15  and column (digit) line  13  is illustrated as a resistance  21  in FIG.  1 . During the equilibration operation word line  15  is grounded. Accordingly, a row to column  21  short will cause a current drain in the path from node A through transistor  27 , digit line  13 , and word line  15  during the equilibration operation. 
     In order to limit current when a row to column short exists, the transistor  35  is provided with a relatively long current limiting N-channel, as depicted in FIGS. 2 and 3. FIG. 2 is a sectional side view showing the source and drain regions of transistor  35  and the long channel L, while FIG. 3 illustrates a top view of the long channel L. In one typical arrangement, the width to length of the channel region of transistor  35  is 2.6/19 as shown in FIG.  3 . 
     While the long N-channel does serve to limit current in case of a row to column short to typically 40 uA as the number of row to column shorts increases in different columns of high density memory devices, this conventional technique begins to draw increasing amounts of current, thus hindering the ability of memory device to meet tight voltage and current specifications. 
     In this regard, it should be noted that while the FIG. 1 circuit shows a long channel transistor  35  connected to a single equilibrate circuit  29 , in actual practice transistor  35  is connected to a plurality of equilibrate circuits  29  in a column of a memory device. 
     As a consequence, as densities of memory devices increase with corresponding increases in row to column shorts, there is a need for an improved circuit for supplying Vcc/2 to the equilibrate circuit  29  which does not consume large amounts of current in the presence of row to column shorts. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the problem with the FIG. 1 circuit by substituting the transistor  35  with a latch circuit which supplies voltage Vcc/2 to one or more equilibrate circuits  29 , as long as the current drawn from the latch circuit is below a predetermined threshold. Once the drawn current exceeds the predetermined threshold, the latch circuit switches to a state where voltage is no longer supplied to the equilibrate circuits. 
     Preferably, the latch circuit is a self-switching circuit, so that as soon as the current drawn from the latch exceeds the predetermined threshold current, the latch self switches to the state where no voltage is supplied to the equilibrate circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other advantages and features of the invention will be more clearly discerned from the following detailed description of the invention which is provided in connection with the accompanying drawings, in which: 
     FIG. 1 illustrates a conventional equilibrate circuit and current limiter therefor; 
     FIG. 2 illustrates a cross-sectional view of a current limiting transistor used in the circuit of FIG. 1; 
     FIG. 3 illustrates a top view of a channel region of the current limiting transistor; 
     FIG. 4 illustrates a latch circuit constructed in accordance with an exemplary embodiment of the invention; 
     FIG. 5 illustrates the relationship of the latch circuit of FIG. 4 to equilibrate circuits provided in a column of a memory device; and 
     FIG. 6 illustrates a processor circuit which employs a memory device using the FIG. 4 circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention replaces the current limiting circuit  33  illustrated in FIG. 1, including transistor  35  which supplies the voltage Vcc/2 to node A, with a new latch circuit  41  illustrated in FIG.  4 . 
     The latch circuit of FIG. 4 is a self-latching circuit in that as long as current drawn from the latch circuit  41  is below a predetermined threshold, voltage is supplied by the latch circuit at node C and through transistor  43  to node A and one or more equilibrate circuits  29 . 
     At the heart of latch circuit  41  is a latch  45  formed by a first pair  47  and  51  of complementary N and P channel MOS transistors, and a second pair  49  and  53  of complementary N and P channel MOS transistors. Each pair of transistors is serially connected, and the two pairs of transistors are connected in parallel across nodes E and F. Nodes C and D define the respective connection point of the complementary transistors  47  and  51  and  49  and  53  and input/output nodes for latch  45 . 
     As illustrated in FIG. 4, the gate of transistor  47  is connected to node D; the gate of transistor  49  is connected to node C; the gate of transistor  51  is connected to node D; and the gate of transistor  53  is connected to node C. This cross-coupling of the transistors forms latch  45 . The output of latch  45  is taken at node C, which supplies a voltage from source Vcc/2 through transistors  55  and  47  to the equilibrate circuits  29  through transistor  43 . 
     Latch circuit  41  also contains a capacitor  57  which is connected between node D and ground. Node F of latch circuit  45  is also connected to ground. 
     A power-up circuit is also provided within latch circuit  41 , and includes a power-up signal line  63  upon which a power-up signal appears during power-up of a memory device. The power-up signal line  63  is connected to the gate of a transistor  59  which is coupled between Vcc/2 and node E, and serves to provide additional current to node E during a power-up operation. 
     Power-up line  63  is also connected to the gate of transistor  61  and serves to force node D to ground. The power-up circuitry, including transistors  59  and  61 , ensures that latch  45  will always latch to a first predetermined state which will supply a voltage from Vcc/2 through transistor  55  and transistor  47  to node C, to thereby provide the equilibrate voltage to each of the equilibrate circuits  29  connected to node A. 
     Capacitor  57  is present for the case where the power-up signal is not working properly and to compensate for all of the capacitance on node A. Further, the device sizes of the latch circuit  41  are skewed to favor transistor  47  being ON. 
     Transistor  55  can be configured as a current limiting transistor like transistor  35  described above in connection with FIG.  1 . The gate of transistor  55  is connected at a voltage supply terminal which supplies a pump voltage Vccp to the gate of transistor  55 . 
     When first powered up, FIG. 4 will assume a first state as noted, wherein a voltage Vcc/2 appears at node C and is applied to node A and to each of the equilibrate circuits  29  connected to node A. This condition will be maintained as long as the current drawn from node C is less than the current drawn at node E by the latch  45  from the terminal supplying the voltage Vcc/2. However, when current drawn from node C begins to equal the current drawn at node E through transistor  55 , then latch  45  will switch to a second state whereby transistor  47 , previously on, is now turned off. As a consequence, node C is pulled to ground through transistor  51 . Latch  45  will remain in this condition and continue to fail to supply any current to the equilibrate circuits  29 . 
     Referring back to FIG. 1 for moment, if a row to column short  21  appears in a memory device employing the FIG. 4 latch circuit, and it causes a current drain at node C in FIG. 4, which exceeds a threshold current, determined by the current drawn at node E through transistor  55 , this will cause the latch circuit  45  to self-switch to its second state causing transistor  47  to turn off, decoupling node E and node C. 
     FIG. 5 illustrates the use of latch circuit  41  to supply voltage to a plurality of equilibrate circuits  29  which are connected in a column of a memory device. It should be noted that this is but one arrangement in which latch  41  may find utility. Latch  41  may also be used to simultaneously provide a voltage to equilibrate circuits in one or more columns of a memory device. Also, when a memory device employs segmented columns, a separate latch  41  may be provided for each of the equilibrate circuits of a column segment. 
     FIG. 6 illustrates a processor system which employs a memory device which contains an equilibrate circuit  29  and associated latch circuit  41  of the invention. As shown in FIG. 6, the processor system, such as a computer system, for example, comprises a central processing unit (CPU)  210 , for example, a microprocessor, that communicates with one or more input/output (I/O) devices  240 ,  250  over a bus  270 . The computer system  200  also includes random access memory (RAM)  260 , a read only memory (ROM)  280  and may include peripheral devices such as a floppy disk drive  220  and a compact disk (CD) ROM drive  230  which also communicates with CPU  210  over the bus  270 . The RAM  260  is preferably constructed as one or more integrated circuits which each include a latch circuit  41  as described above. It may also be desirable to integrate the processor  210  and memory  260  on a single IC chip. 
     Although the invention has been described above in connection with exemplary embodiments, it is apparent that many modifications and substitutions can be made without departing from the spirit or scope of the invention. Accordingly, the invention is not to be considered as limited by the foregoing description, but is only limited by the scope of the appended claims.