Abstract:
The present invention enables the self-diagnosis functionality by embedding a cable modem with the CMTS system with mechanisms to redirect the signals from external connections to the embedded cable modem, thereby enabling the end user to fully test the CMTS using a suite of diagnostic tests. The embedded cable modem integrates the external CM, computer and diagnostic software in the chassis, or alternatively onto the CMTS card in the chassis. The invention enables the end user to fully test the functionality as a stand-alone unit, without relying on any external test equipment or methods. It also enables the end user to diagnose the CMTS from a remote location. Another major advantage of the present invention is that it enables the CMTS/CM function to be verified over the entire physical layer parameter set (frequency, symbol rate, FEC, signal levels, etc.) while not interrupting any of the services that are on the ‘live’ HFC plant.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   The application is related to co-pending application Ser. No. 09/474,039, entitled, “System and Process for Direct, Flexible and Scalable Switching of Data Packets in Broadband Networks”, filed Dec. 28, 1999, and Ser. No. 09/566,540, entitled, “System Having a Meshed Backplane and Process for Transferring Data Therethrough”, filed May 8, 2000, now issued as U.S. Pat. No. 6,611,526 on Aug. 26, 2003 by the present applicants. This application is also related to co-pending application Ser. No. 09/568,270, entitled, “System and Process for Return Channel Spectrum Manager”, filed on even date with the present application. 

   FIELD OF THE INVENTION 
   This invention relates generally to networking data processing systems, and, more particularly to a broadband network environment, for example, one using a SONET backbone and Hybrid Fiber-Coax(ial cable) (“HFC”) to connect users to the backbone. An emerging hardware/software standard for the HFC environment is DOCSIS (Data Over Cable Service Interface Standard) of CableLabs. 
   BACKGROUND OF THE INVENTION 
   In a current configuration of wide-area delivery of data to HFC systems (each connected to 200 households/clients), the head-end server is connected to a SONET ring via a multiplexer drop on the ring (see FIG.  1 ). These multiplexers currently cost some $50,000 in addition to the head-end server, and scaling up of service of a community may require new multiplexers and servers. 
   The failure of a component on the head-end server can take an entire “downstream” (from the head-end to the end-user) sub-network out of communication with the world. Attempts have been made to integrate systems in order to reduce costs and to ease system management. A current integrated data delivery system is shown in FIG.  2 .  FIG. 2  shows a system having a reverse path monitoring system, an ethernet switch, a router, modulators and upconverters, a provisioning system, telephony parts, and a plurality of CMTS&#39;s (cable modem termination systems). This type of system typically has multiple vendors for its multiple systems, has different management systems, a large footprint, high power requirements and high operating costs. 
   A typical network broadband cable network for delivery of voice and data is shown in FIG.  3 . Two OC-12 port interface servers are each connected to one of two backbone routers which are in turn networked to two switches. The switches are networked to CMTS head-end routers. The CMTS head-end routers are connected to a plurality of optical nodes. The switches are also connected to a plurality of telephone trunk gateways which are in turn connected to the public switched telephone network (PSTN). As with the “integrated” system shown in  FIG. 2 , this type of network also typically has multiple vendors for its multiple systems, has different management systems, a large footprint, high power requirements and high operating costs. 
   In order to facilitate an effective integrated solution to have an integrated diagnostic system. Current art CMTS&#39;s do not have the capability of self-diagnosing. It is impossible to perform loop back testing on a CMTS modem because the downstream (transmitter) modulation is different from the upstream (receiver) modulation in a system using the CableLabs DOCSIS cable modem standard. Currently, loop back testing on a CMTS must be done using an external cable modem (CM) box connected to a general purpose computer running specialized diagnostic software. The CM and computer receive incoming packets and send them back to the CMTS. It is difficult to control external equipment, particularly equipment that is remote from the CMTS such as a centralized network management system. Lack of integration with the system means a significant amount of end user interaction and preparation for implementing diagnostic tests. 
   It is desirable to have an integrated solution to reduce the size of the system, its power needs and its costs, as well as to give the data delivery system greater consistency. 
   It is an object of the present invention to provide a system and process for electrical interconnect for broadband delivery of high-quality voice, data, and video services. 
   It is another object of the present invention to provide a system and process for a cable access platform having high network reliability with the ability to reliably support lifeline telephony services and the ability to supply tiered voice and data services. 
   It is another object of the present invention to provide a system and process for a secure, scalable network switch. 
   SUMMARY OF THE INVENTION 
   The problems of providing a self-diagnostic capability for delivery of voice and data in a compact area for an integrated switch are solved by the present invention of an embedded cable modem. 
   The present invention enables the self-diagnosis functionality by embedding a cable modem with the CMTS system with mechanisms to redirect the signals from external connections to the embedded cable modem, thereby enabling the end user to fully test the CMTS using a suite of diagnostic tests. The embedded cable modem integrates the external CM, computer and diagnostic software in the chassis, or alternatively onto the CMTS card in the chassis. The invention enables the end user to fully test the functionality as a stand-alone unit, without relying on any external test equipment or methods. It also enables the end user to diagnose the CMTS from a remote location. Another major advantage of the present invention is that it enables the CMTS/CM function to be verified over the entire physical layer parameter set (frequency, symbol rate, FEC, signal levels, etc.) while not interrupting any of the services that are on the ‘live’ HFC plant. 
   The present invention together with the above and other advantages may best be understood from the following detailed description of the embodiments of the invention illustrated in the drawings, wherein: 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a prior art network on a SONET ring; 
       FIG. 2  shows a prior art data delivery system; 
       FIG. 3  shows a prior art data delivery network; 
       FIG. 4  is a block diagram of a chassis according to principles of the invention; 
       FIG. 5  shows an integrated cable infrastructure having the chassis of  FIG. 4 ; 
       FIG. 6  is a block diagram of the application cards, the backplane and a portion of the interconnections between them in the chassis of  FIG. 4 ; 
       FIG. 7  is a schematic diagram of the backplane interconnections, including the switching mesh; 
       FIG. 8  is a block diagram of two exemplary slots showing differential pair connections between the slots; 
       FIG. 9  is a block diagram of the MCC chip in an application module according to principles of the present invention; 
       FIG. 10  is a diagram of a packet tag; 
       FIG. 11  is a block diagram of a generic switch packet header; 
       FIG. 12  is a flow chart of data transmission through the backplane; 
       FIG. 13  is a block diagram of an incoming ICL packet; 
       FIG. 14  is a block diagram of a header for the ICL packet of  FIG. 13 ; 
       FIG. 15  shows example mapping tables mapping channels to backplane slots according to principles of the present invention; 
       FIG. 16  is a block diagram of a bus arbitration application module connected in the backplane of the present invention; 
       FIG. 17  is a state diagram of bus arbitration in the application module of  FIG. 16 ; 
       FIG. 18  is a block diagram of the chassis of  FIG. 4  showing a subset of RF signal lines in the backplane according to principles of the invention; and, 
       FIG. 19  is a block diagram of a CMTS application module and an embedded cable modem connected through the backplane according to principles of the invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 4  shows a chassis  200  operating according to principles of the present invention. The chassis  200  integrates a plurality of network applications into a single switch system. The invention is a fully-meshed OSI Layer 3/4 IP-switch with high performance packet forwarding, filtering and QoS/CoS (Quality of Service/Class of Service) capabilities using low-level embedded software controlled by a cluster manager in a chassis controller. Higher-level software resides in the cluster manager, including router server functions (RIPv1, RIPv2, OSPF, etc.), network management (SNMP V1/V2), security, DHCP, LDAP, and remote access software (VPNs, PPTP, L2TP, and PPP), and can be readily modified or upgraded. 
   In the present embodiment of the invention, the chassis  200  has fourteen (14) slots for modules. Twelve of those fourteen slots hold application modules  205 , and two slots hold chassis controller modules  210 . Each application module has an on-board DC-DC converter and is “hot-pluggable” into the chassis. The chassis controller modules  210  are for redundant system clock/bus arbitration. Examples of applications that may be integrated in the chassis are a CMTS module  215 , an Ethernet module  220 , a SONET module  225 , and a telephony application  230 . Another application may be an interchassis link (ICL) port  235  through which the chassis may be linked to another chassis. 
     FIG. 5  shows an integrated cable infrastructure  260  having the chassis  200  of FIG.  4 . The chassis  200  is part of a regional hub  262  (also called the “head-end”) for voice and data delivery. The hub  262  includes a video controller application  264 , a video server  266 , Web/cache servers  26 B, and an operation support system (OSS)  270 , a combiner  271  and the chassis  200 . The chassis  200  acts as an IP access switch. The chassis  200  is connected to a SONET ring  272 , outside the hub  262 , having a connection to the Internet  274 , and a connection to the Public Switched Telephone Network (PSTN)  276 . The chassis  200  and the video-controller application  264  are attached to the combiner  271 . The combiner  271  is connected by an HFC link  278  to cable customers and provides IP voice, data, video and fax services. At least 2000 cable customers may be linked to the head-end by the HFC link  278 . The chassis  200  can support a plurality of HFC links and also a plurality of chassises may be networked together (as described below) to support thousands of cable customers. 
   By convention today, there is one wide-band channel for transmission (downloading) to users (which may be desktop computers, facsimile machines or telephone sets) and four much narrower channels for (uploading). This is processed by the HFC cards with duplexing at an O/E node. The local HFC cable system or loop may be a coaxial cable distribution network with a drop to a cable modem. 
     FIG. 6  shows application modules connected to a backplane  420  of the chassis  200  of FIG.  4 . In the present embodiment of the invention, the backplane is implemented as a 24-layer printed wiring board and includes 144 pairs of uni-directional differential-pair connections, each pair directly connecting input and output terminals of each of a maximum of twelve application modules with output and input terminals of each other module and itself. Each application module interfaces with the backplane through a Mesh Communication Chip (MCC)  424  through these terminals. Each application module is also connected to a chassis management bus  432  which provides the modules with a connection to the chassis controllers  428 ,  430 . Each MCC  424  has twelve (12) serial link interfaces that run to the backplane  420 . Eleven of the serial links on each application module are for connecting the application module to every other application module in the chassis. One link is for connecting the module with itself, i.e., a loop-back. The backplane is fully meshed meaning that every application module has a direct link to every other application module in the chassis through the serial links. Only a portion of the connections is shown in  FIG. 6  as an example. The backplane mesh is shown in FIG.  7 . 
   The 12 channels with serial links of the MCC are numbered 0 to 11. This is referred to as the channel ID or CID. The slots on the backplane are also numbered from 0 to 11 (slot ID, or SID). The chassis system does not require, however, that a channel 0 be wired to a slot 0 on the backplane. A serial link may be connected to any slot. The slot IDs are dynamically configured depending on system topology. This provides freedom in backplane wiring layout which might otherwise require layers additional to the twenty-four layers in the present backplane. The application module reads the slot ID of the slot into which it is inserted. The application module sends that slot ID out its serial lines in an idle stream in between data transmissions. The application module also includes the slot ID in each data transmission. 
     FIG. 15  shows examples of mapping tables of channels in cards to backplane slots. Each card stores a portion of the table, that is, the table row concerning the particular card. The table row is stored in the MCC. 
     FIG. 16  shows a management bus arbitration application module connected to the backplane. The backplane contains two separate management buses for failure protection. Each application module in the chassis including the two chassis controllers as well as the twelve applications modules can use both or either management bus. 
   The management bus is used for low-speed data transfer within the chassis and generally consists of control, statistical, configuration information, data from the chassis controller modules to the application modules in the chassis. 
   The implementation of the management bus consists of a four bit data path, a transmit clock, a transmit clock signal, a collision control signal, and a four bit arbitration bus. As seen in  FIG. 16 , the bus controller has a 10/100 MAC device, a receive FIFO, bus transceiver logics, and a programmable logic device (“PLD”). 
   The data path on the management bus is a four-bit (Media Independent Interface) MII standard interface for 10/100 ethernet MACs. The bus mimics the operation of a standard 100 Mbit ethernet bus interface so that the MAC functionality can be exploited. The programmable logic device contains a state machine that performs bus arbitration. 
     FIG. 17  shows the state diagram for the state machine in the programmable logic device for the management bus. The arbitration lines determine which module has control of the bus by using open collector logic. The pull-ups for the arbitration bus reside on the chassis controller modules. Each slot places its slot ID on the arbitration lines to request the bus. During transmission of the preamble of data to be transmitted, if the arbitration is corrupted, the bus controller assumes that another slot had concurrently requested the bus and the state machine within the PLD aborts the transfer operation by forcing a collision signal for both the bus and the local MAC device active. As other modules detect the collision signal on the bus active, the collision line on each local MAC is forced to the collision state, which allows the back-off algorithm within the MAC to determine the next transmission time. If a collision is not detected, the data is latched into the receive FIFO of each module, and the TX_Enable signal is used to quantify data from the bus. The state machine waits four clock cycles during the preamble of the transmit state, and four clock cycles during the collision state to allow the other modules to synchronize to the state of the bus. 
   Backplane Architecture 
     FIG. 7  shows the internal backplane architecture of the current embodiment of the switch of the invention that was shown in exemplary fashion in FIG.  6 . One feature is the full-mesh interconnection between slots shown in the region  505 . Slots are shown by vertical lines in FIG.  7 . This is implemented using 144 pairs of differential pairs embedded in the backplane as shown in FIG.  8 . Each slot thus has a full-duplex serial path to every other slot in the system. There are n(n−1) non-looped-back links in the system, that is, 132 links, doubled for the duplex pair configuration for a total of 264 differential pairs (or further doubled for 528 wires) in the backplane to create the backplane mesh in the present embodiment of the invention. Each differential pair is able to support data throughput of more than 1 gigabit per second. 
   In the implementation of the current invention, the clock signal is embedded in the serial signaling, obviating the need for separate pairs (quads) for clock distribution. Because the data paths are independent, different pairs of cards in the chassis may be switching (ATM) cells and others switching (IP) packets. Also, each slot is capable of transmitting on all 11 of its serial links at once, a feature useful for broadcasting. All the slots transmitting on all their serial lines achieve a peak bandwidth of 132 gigabits per second. Sustained bandwidth depends on system configuration. 
   The mesh provides a fully redundant connection between the application cards in the backplane. One connection can fail without affecting the ability of the cards to communicate. Routing tables are stored in the chassis controllers. If, for example, the connection between application module 1 and application module 2 failed, the routing tables are updated. The routing tables are updated when the application modules report to the chassis controllers that no data is being received on a particular serial link. Data addressed to application module 2 coming in through application module 1 is routed to another application module, for instance application module 3, which would then forward the data to application module 2. 
   The bus-connected backplane region  525  includes three bus systems. The management/control bus  530  is provided for out-of-band communication of signaling, control, and management information. A redundant backup for a management bus failure will be the mesh interconnect fabric  505 . In the current implementation, the management bus provides 32-bit 10-20 MHz transfers, operating as a packet bus. Arbitration is centralized on the system clock module  102  (clock A). Any slot to any slot communication is allowed, with broadcast and multicast also supported. The bus drivers are integrated on the System Bus FPGA/ASIC. 
   A TDM (Time Division Multiplexing) Fabric  535  is also provided for telephony applications. Alternative approaches include the use of a DSO fabric, using 32 TDM highways (sixteen full-duplex, 2048 FDX timeslots, or approximately 3 T3s) using the H.110 standard, or a SONET ATM (Asynchronous Transfer Mode) fabric. 
   Miscellaneous static signals may also be distributed in the bus-connected backplane region  540 . Slot ID, clock failure and management bus arbitration failure may be signaled. 
   A star interconnect region  545  provides independent clock distribution from redundant clocks  102  and  103 . The static signals on backplane bus  540  tell the system modules which system clock and bus arbitration slot is active. Two clock distribution networks are supported: a reference clock from which other clocks are synthesized, and a TDM bus clock, depending on the TDM bus architecture chosen. Both clocks are synchronized to an internal Stratum 3/4 oscillator or an externally provided BITS (Building Integrated Timing Supply). 
     FIG. 8  shows a first connection point on a first MCC on a first module, MCC A  350 , and a second connection point on a second MCC on a second module, MCC B  352 , and connections  354 ,  355 ,  356 ,  357  between them. The connections run through a backplane mesh  360  according to the present invention. There are transmit  362 ,  364  and receive  366 ,  368  channels at each MCC  350 ,  352 , and each channel has a positive and a negative connection. In all, each point on a module has four connections between it and every other point due to the backplane mesh. The differential transmission line impedance and length are controlled to ensure signal integrity and high speed operation. 
     FIG. 9  is a block diagram of the MCC chip. An F-bus interface  805  connects the MCC  300  to the FIFO bus (F-bus). Twelve transmit FIFOs  810  and twelve receive FIFOs  815  are connected to the F-bus interface  805 . Each transmit FIFO has a data compressor (12 data compressors in all,  820 ), and each receive FIFO has a data expander (12 data expanders in all,  825 ). Twelve serializer/deserializers  830  serve the data compressors  820  and data expanders  825 , one compressor and one expander for each A channel in the MCC is defined as a serial link together with its encoding/decoding logic, transmit queue and receive queue. The serial lines running from the channels connect to the backplane mesh. All the channels can transmit data at the same time. A current implementation of the invention uses a Mesh Communication Chip to interconnect up to thirteen F-buses in a full mesh using serial link technology. Each MCC has two F-bus interfaces and twelve serial link interfaces. The MCC transmits and receives packets on the F-buses in programmable size increments from 64 bytes to entire packets. It contains twelve virtual transmit processors (VTPs) which take packets from the F-bus and send them out the serial links, allowing twelve outgoing packets simultaneously. The VTPs read the MCC tag on the front of the packet and dynamically bind themselves to the destination slot(s) indicated in the header. 
   The card/slot-specific processor, card/slot-specific MAC/PHY pair (Ethernet, SONET, HFC, etc.) and an MCC communicate on a bi-directional F-bus (or multiple unidirectional F-busses). The packet transmit path is from the PHY/MAC to the processor, then from the processor to the MCC and out the mesh. The processor does Layer 3 and Layer 4 look-ups in the FIPP to determine the packet&#39;s destination and Quality of Service (QoS), modifies the header as necessary, and prepends the MCC tag to the packet before sending it to the MCC. 
   The packet receive path is from the mesh to the MCC and on to the processor, then from the processor to the MAC/Phy and out the channel. The processor strips off the MCC tag before sending the packet on to the MAC. 
   A first data flow control mechanism in the present invention takes advantage of the duplex pair configuration of the connections in the backplane and connections to the modules. The MCCs have a predetermined fullness threshold for the FIFOs. If a receive FIFO fills to the predetermined threshold, a code is transmitted over the transmit channel of the duplex pair to stop sending data. The codes are designed to direct-couple balance the signals on the transmission lines and to enable the detection of errors. The codes in the present implementation of the invention are 16B/20B codes, however other codes may be used within the scope of the present invention. The MCC sends an I1 or I2 code with the XOFF bit set to turn off the data flow. This message is included in the data stream transmitted on the transmit channel. If the FIFO falls below the predetermined threshold, the MCC clears the stop message by sending an I1 or I2 code with the XOFF bit cleared. The efficient flow control prevents low depth FIFOs from overrunning, thereby allowing small FIFOs in ASICS, for example, 512 bytes, to be used. This reduces microchip costs in the system. 
     FIG. 10  shows a packet tag, also called the MCC tag. The MCC tag is a 32-bit tag used to route a packet through the backplane mesh. The tag is added to the front of the packet by the slot processor before sending it to the MCC. The tag has four fields: a destination mask field, a priority field, a keep field, and a reserved field. The destination mask field is the field holding the mask of slots in the current chassis to which the packet is destined, which may or may not be the final destination in the system. For a transmit packet, the MCC uses the destination mask to determine which transmit queue(s) the packet is destined for. For a receive packet the MCC uses the priority and keep fields to determine which packets to discard in an over-committed slot. The reserved field is unused in the current embodiment of the invention. 
   The MCC has two independent transmit mode selectors, slot-to-channel mapping and virtual transmit mode. In slot-to-channel mapping, the MCC transparently maps SIDs to CIDs and software does not have to keep track of the mapping. In virtual transmit mode, the MCC handles multicast packets semi-transparently. The MCC takes a single F-bus stream and directs it to multiple channels. The transmit ports in the MCC address virtual transmit processors (VTPs) rather than slots. The F-bus interface directs the packet to the selected virtual transmit processor. The VTP saves the Destination Mask field from the MCC tag and forwards the packet data (including the MCC tag) to the set of transmit queues indicated in the Destination Mask. All subsequent 64 byte “chunks” of the packet are sent by the slot processor using the same port ID, and so are directed to the same VTP. The VTP forwards chunks of the packet to the set of transmit queues indicated in the Destination Mask field saved from the MCC tag. When a chunk arrives with the EOP bit set, the VTP clears its destination mask. If the next chunk addressed to that port is not the start of a new packet (i.e., with the SOP bit set), the VTP does not forward the chunk to any queue. 
   The destination mask of the MCC tag enable efficient multicast transmission of packets through “latching.” The destination mask includes code for all designated destination slots. So, if a packet is meant for all twelve slots, only one packet need be sent. The tag is delivered to all destinations encoded in the mask. If only a fraction of the slots are to receive the packet, only those slots are encoded into the destination mask. 
   The MCC maintains a set of “channel busy” bits which it uses to prevent multiple VTPs from sending packets to the same CID simultaneously. This conflict prevention mechanism is not intended to assist the slot processor in management of busy channels, but rather to prevent complete corruption of packets in the event that the slot processor accidentally sends two packets to the same slot simultaneously. When the VTPs get a new packet, they compare the destination CID mask with the channel busy bits. If any channel is busy, it is removed from the destination mask and an error is recorded for that CID. The VTP then sets all the busy bits for all remaining destination channels and transmits the packet. When the VTP sees EOP on the F-bus for the packet, it clears the channel busy bits for its destination CIDs. 
   The F-bus interface performs the I/O functions between the MCC and the remaining portion of the application module. The application module adds a 32-bit packet tag (MCC tag), shown in  FIG. 10 , to each data packet to be routed through the mesh. 
   The data received or transmitted on the F-bus is up to 64 bits wide. In data transmission, the F-bus interface adds 4 status bits to the transmit data to make a 68-bit data segment. The F-bus interface drops the 68-bit data segment into the appropriate transmit FIFO as determined from the packet tag. The data from a transmit FIFO is transferred to the associated data compressor where the 68-bit data segment is reduced to 10-bit segments. The data is then passed to the associated serializer where the data is further reduced to a serial stream. The serial stream is sent out the serial link to the backplane. 
   Data arriving from the backplane comes through a serial link to the associated channel. The serializer for that channel expands the data to a 10-bit data segment and the associated data expander expands the data to a 68-bit data segment which is passed on to the related FIFO and then from the FIFO to the F-bus interface. 
   A Fast IP Processor (FIPP) is provided with 32/64 Mbytes of high-speed synchronous SDRAM, 8 Mbytes of high-speed synchronous SRAM, and boot flash. The FIPP has a 32-bit PCI bus and a 64-bit FIFO bus (F-bus). The FIPP transfers packet data to and from all F-bus-connected devices. It provides IP forwarding in both unicast and multicast mode. Routing tables are received over the management bus from the chassis route server. The FIPP also provides higher layer functions such as filtering, and CoS/QoS. 
   Each line card has a clock subsystem that produces all the clocks necessary for each card. This will lock to the reference clock provided by the System Clock and Management Bus Arbitration Card. 
   Each card has hot-plug, power-on reset circuitry, and Sanity Timer functions. All cards have on-board DC-to-DC converters to go from the −48V rail in the backplane to whatever voltages are required for the application. Some cards (such as the CMTS card) likely will have two separate and isolated supplies to maximize the performance of the analog portions of the card. 
     FIG. 11  shows a generic switch header for the integrated switch. The header is used to route data packets through the system. The final destination may be either intra-chassis or inter-chassis. 
   The header type field indicates the header type used to route the packet through the network having one or more chassis systems. Generally, the header type field is used to decode the header and provide information needed for packet forwarding. Specifically, the header type field may be used to indicate that the Destination Fabric Interface Address has logical ports. The header type field is also used to indicate whether the packet is to be broadcast or unicast. The header type field is used to indicate the relevant fields in the header. 
   The keep field indicates whether a packet can be dropped due to congestion. 
   The fragment field indicates packet fragmentation and whether the packet consists of two frames. 
   The priority field is used to indicate packet priority. 
   The encap type field is a one bit field that indicates whether further layer 2 processing is needed before the packet is forwarded. If the bit is set, L2 is present. If the bit is not set, L2 is not present. 
   The Mcast type field is a one bit field that indicates whether the packet is a broadcast or multicast packet. It may or may not be used depending on the circumstances. 
   The Dest FIA (Fabric Interface Address) type field indicates whether the destination FIA is in short form (i.e., &lt;chassis/slot/port&gt;) or in long form (i.e., &lt;chassis/slot/port/logical port&gt;). This field may or may not be used depending on the circumstances. This field may be combined with the header type field. 
   The Src FIA type field is a one bit field that indicates whether the source FIA is in short form (i.e., &lt;chassis/slot/port&gt;) or in long form (i.e., &lt;chassis/slot/port/logical port&gt;). This field may or may not be used depending on the circumstances. This field may be combined with the header type field. 
   The data type field is an x-bit field used for application to application communication using the switch layer. The field identifies the packet destination. 
   The forwarding info field is an x-bit field that holds the Forwarding Table Revision is a forwarding information next hop field, a switch next hop, that identifies which port the packet is to go out, along with the forward_table_entry key/id. 
   The Dest FIA field is an x-bit field that indicates the final destination of the packet. It contains chassis/slot/port and sometimes logical port information. A chassis of value 0 (zero) indicates the chassis holding the Master Agent. A port value of 0 (zero) indicates the receiver of the packet is an application module. The logical port may be used to indicate which stack/entity in the card is to receive the packet. All edge ports and ICL ports are therefore “1”-based. 
   The Src FIA field is an x-bit field that indicates the source of the packet. It is used by the route server to identify the source of incoming packets. 
     FIG. 12  is a flow chart of the general packet forwarding process. When a packet is received at one of the application modules of the switch, the module examines the BAS header, if one is present, to determine if the packet was addressed for the chassis to which the module is attached. If not, the application module looks up the destination chassis in the routing table and forwards the packet to the correct chassis. If the packet was addressed for the chassis, the application module examines the header to determine whether the packet was addressed to the module (or slot). If not, the application module looks up the destination slot in the mapping table and forwards the packet to the correct application module. If the packet was addressed to the application module, the application module compares the forwarding table ID in the header to the local forwarding table revision. If there is a match, the module uses the pointer in the header to forward the packet on to its next destination. 
   Unicast Traffic Received from an ICL Port 
     FIG. 13  is a diagram of an incoming ICL packet. The packet has a BAS header, an encap field that may be either set or not (L 2  or NULL), an IP field, and a data field for the data. 
     FIG. 14  is a diagram of a header for the packet of FIG.  12 . The header type may be 1 or 2. A header type of 1 indicates an FIA field that is of the format chassis/slot/port both for destination and source. A header type of 2 indicates an FIA field of the format chassis/slot/port/logical port for both destination and source. The keep field is not used. The priority field is not used. The fragment field is not used. The next hop filed is not used. The Encap field is zero or 1. The Mcast field is not used. The DST FIA type may be 0 or 1. The SRC FIA type may be zero or one. The BAS TTL field is not used. The forward info field is used. And the DST and SRC FIA fields are used. 
   Embedded Cable Modem 
   The cable modem termination system comprises an asymmetrical communication system with two major components: a head end component and a client end component. The head end component, known as the cable modem termination system (CMTS) transmits a signal to a cable modem (CM) that is substantially different form the signal it receives from the CM. The CMTS transmits a 5 megabaud, 64/256 QAM, in the 54 to 850 MHz band signal and the CM transmits a 160 kilobaud to 2.56 megabaud, QPSK/16 QAM, in the 5 to 42 MHz band signal. Because the transmit signal is different from the receive signal, it is impossible to perform physical layer loopback for self-diagnostic testing. 
     FIG. 18  shows the chassis  200  of  FIG. 4  with RF signal lines  906  running through the backplane  420  from the CMTS&#39;s  215 ,  900 ,  902 ,  904  to a chassis controller module  908 . In actuality, RF signals lines run from each of the applications slots to each of the chassis controllers  908 ,  910 . The figure is simplified for clarity. 
   Each of the chassis controllers  908 ,  910  has an embedded cable modem system  912 ,  914  capable of receiving a signal from one of the CMTS&#39;s and generating a return signal to the sending CMTS. The embedded cable modem also contains diagnostic functions. 
   The signal lines  906  in backplane carry the radio frequency (RF) signals from the CMTS to the embedded CM and back again. This type of RF signal routing on a backplane requires a high degree of care in the implementation of the backplane to ensure the RF signals are not contaminated by any of the digital signals on the backplane. 
     FIG. 19  shows a CMTS application module  215  connected through the backplane  420  to an embedded cable modem  912 . The CMTS application module  215  has a downstream modulator  920  and four upstream modulators  922 ,  924 ,  926 ,  928 . A packet processing and backplane interface  930  sends and receives data at the backplane  420 . The data is processed at the CMTS MAC layer  932 . The embedded cable modem  908  receives the downstream signal from the CMTS application module  215  at a first 12-position relay  936  (having one position for each application module). The embedded cable modem  912  sends return signals through a second 12-position relay  937  to the CMTS application module  215 . The embedded cable modem  912  also receives CMTS signals at the second 12-position relay  937  for diagnostic purposes. 
   In the cable modem, the downstream RF signal goes through a first variable attenuator  938  and then a first summer  940  before being demodulated at a downstream demodulator  942 . The signal is processed at the cable modem MAC layer  944 . From the MAC layer  944 , the signal may be processed at a CM packet processing and backplane interface  946  and then packets may be transmitted to the backplane  420 . The signal could also be sent through an upstream burst modulator  948  that modulates the return signal. The return signal is then sent through second summer  950 , followed by a second variable attenuator  952  and then through the second 12-position relay  937  where it is returned through an RF signal line to the CMTS application module  215 . 
   From the CM packet processing and backplane interface  946 , the signal can be directed to the system interface  955  where, in the preferred embodiment of the invention, the diagnostic software resides. In a first alternative embodiment of the invention, the diagnostic software may reside in the chassis controller outside the embedded cable modem. In a second alternative embodiment, the diagnostic software may reside on an application module in the chassis, such as the CMTS module. In a third alternative embodiment, the diagnostic software may reside at the central network manager or some other remote, off-chassis location. 
   The embedded cable modem  912  has a calibrated broadband noise source  954  that generates a noise signal that can be added to the downstream signal at the first summer  940  and to the upstream signal at the second summer  950 . The calibrated noise source  954  is used to generate test signals for carrier to noise diagnostics. 
   In operation, outgoing packets flow from the CMTS backplane interface  930 , to the CMTS MAC  932 , to the CMTS downstream modulator  920  where they are modulated onto a carrier in the range of 54 to 850 MHz. The resulting signal is then routed to the external hybrid fiber coax (HFC) where it is sent to the downstream CMs, including the embedded cable modem. Upstream packets are modulated and transmitted from the CMs and the embedded cable modem in the range of 5-42 MHz onto the HFC cabling into one of the upstream ports of the CMTS where the signal is routed into one of the upstream demodulators. The embedded cable modem is able to perofmr diagnostics on both the downstream and upstream signal as well as generate test signals to the CMTS. 
   In alternative embodiments of the invention, the embedded cable modem may reside on each CMTS application module. Alternatively, the embedded cable modem may itself be an application module. 
   It is to be understood that the above-described embodiments are simply illustrative of the principles of the invention. Various and other modifications and changes may be made by those skilled in the art which will embody the principles of the invention and fall within the spirit and scope thereof.