Abstract:
Provided is a voltage regulator including a leakage current sink circuit capable of suppressing an influence of a leakage current of an output transistor at high temperature, and reducing power consumption of the voltage regulator at normal temperature. The voltage regulator includes: a reference voltage circuit configured to output a reference voltage; an output transistor configured to output an output voltage; a voltage divider circuit configured to divide the output voltage to output a feedback voltage; an error amplifier circuit configured to amplify a difference between the reference voltage and the feedback voltage, and output the amplified difference to control a gate of the output transistor; and a leakage current sink circuit connected to an output terminal and configured to be prevented from operating at normal temperature, and suppress an influence of a leakage current from the output transistor only at high temperature.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2013-219530 filed on Oct. 22, 2013, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a voltage regulator including a leakage current sink circuit capable of suppressing a leakage current of an output transistor at high temperature, and reducing power consumption of the voltage regulator at normal temperature. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 6  illustrates a related-art voltage regulator configured to suppress a leakage current of an output transistor. The related-art voltage regulator includes a reference voltage circuit  103 , a differential amplifier circuit  104 , an output transistor  105 , a voltage divider circuit  106 , and a leakage current sink circuit  107 . 
         [0006]    The differential amplifier circuit  104  compares a reference voltage VREF output from the reference voltage circuit  103  and a feedback voltage VFB output from the voltage divider circuit  106 , and controls a gate voltage of the output transistor  105  so that an output voltage VOUT of an output terminal  102  is kept at a predetermined value. 
         [0007]    The output voltage VOUT is independent of a power supply voltage and is constant as expressed by Expression (1). 
         [0000]      VOUT=( RS+RF )/ RS× VREF  (1)
 
         [0000]    where RS represents a resistance value of a resistor  122 , and RF represents a resistance value of a resistor  121 . 
         [0008]    In a state in which no load is connected to the output terminal  102  or a light load is connected thereto, the differential amplifier circuit  104  controls a gate-source voltage of the output transistor  105  so that the output transistor  105  enters a substantially off state, to thereby cause only a current necessary for keeping an output of the voltage divider circuit  106  to flow, or cause a current obtained by adding to the current a current amount for the light load to flow. In this case, a current Ifb that flows through the voltage divider circuit  106  is ideally expressed by Expression (2). 
         [0000]        Ifb =VREF/ RS   (2)
 
         [0000]    The output voltage VOUT is expressed by Expression (3) with use of the current Ifb flowing through the voltage divider circuit  106 . 
         [0000]      VOUT=( RS+RF )× Ifb   (3)
 
         [0000]    However, at high temperature, a leakage current Ileak of the output transistor  105  flows. The leakage current Ileak exponentially increases along with an increase in temperature to be non-negligible. Thus, in a state in which no load is connected to the output terminal  102  or a light load is connected thereto, the leakage current Ileak ultimately flows into the voltage divider circuit  106 . 
         [0009]    Hence, Expression (3) is transformed into Expression (4) at high temperature. 
         [0000]      VOUT=( RS+RF )×( Ifb+I leak)  (4)
 
         [0000]    Therefore, the output voltage VOUT is increased due to an influence of the leakage current Ileak, and the voltage regulator cannot operate normally. To deal with this, the leakage current sink circuit  107  including a depletion type NMOS transistor  111  and an NMOS transistor  112  is used to reduce the influence of the leakage current (for example, see Japanese Patent Application Laid-open No. 2012-226421). 
         [0010]    However, the related-art voltage regulator has a problem in that current flows through the leakage current sink circuit  107  from the output terminal  102  even at normal temperature, and hence the power consumption cannot be reduced. 
       SUMMARY OF THE INVENTION 
       [0011]    The present invention has been made in view of the above-mentioned problem, and provides a voltage regulator including a leakage current sink circuit capable of suppressing an influence of a leakage current of an output transistor at high temperature, and reducing power consumption of the voltage regulator at normal temperature. 
         [0012]    In order to solve the related-art problem, a voltage regulator according to one embodiment of the present invention has the following configuration. 
         [0013]    The voltage regulator includes: a reference voltage circuit configured to output a reference voltage; an output transistor configured to output an output voltage; a voltage divider circuit configured to divide the output voltage to output a feedback voltage; an error amplifier circuit configured to amplify a difference between the reference voltage and the feedback voltage, and output the amplified difference to control a gate of the output transistor; and a leakage current sink circuit connected to an output terminal of the voltage regulator. The leakage current sink circuit includes: temperature detection means; and a transistor configured to cause a leakage current to flow, which is controlled by a signal output from the temperature detection means. The leakage current sink circuit is configured to be prevented from operating at normal temperature, and suppress an influence of the leakage current from the output transistor on the output terminal only at high temperature. 
         [0014]    The voltage regulator including the leakage current sink circuit according to one embodiment of the present invention can be prevented from operating to reduce the power consumption at normal temperature, and can sink the leakage current from the output transistor to suppress the influence of the leakage current at high temperature. Further, the leakage current sink circuit includes as elements thereof the similar transistors, namely, NMOS transistors and depletion type NMOS transistors so that the process fluctuations can be suppressed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a circuit diagram illustrating a voltage regulator according to a first embodiment of the present invention. 
           [0016]      FIG. 2  is a circuit diagram illustrating a voltage regulator according to a second embodiment of the present invention. 
           [0017]      FIG. 3  is a circuit diagram illustrating a voltage regulator according to a third embodiment of the present invention. 
           [0018]      FIG. 4  is a circuit diagram illustrating a voltage regulator according to a fourth embodiment of the present invention. 
           [0019]      FIG. 5  is a circuit diagram illustrating a voltage regulator according to a fifth embodiment of the present invention. 
           [0020]      FIG. 6  is a circuit diagram illustrating a related-art voltage regulator. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0021]    In the following, embodiments of the present invention are described with reference to the drawings. 
       First Embodiment  
       [0022]      FIG. 1  is a circuit diagram illustrating a voltage regulator according to a first embodiment of the present invention. The voltage regulator of the first embodiment includes a reference voltage circuit  103 , a differential amplifier circuit  104 , an output transistor  105 , a voltage divider circuit  106 , a leakage current sink circuit  107 , a ground terminal  100 , a power supply terminal  101 , and an output terminal  102 . The reference voltage circuit  103  includes a depletion type NMOS transistor  131  and an NMOS transistor  132 . The voltage divider circuit  106  includes resistors  121  and  122 . The leakage current sink circuit  107  includes depletion type NMOS transistors  111  and  115 , NMOS transistors  112  and  114 , and an inverter  113 . 
         [0023]    The depletion type NMOS transistor  131  has a gate and a source both connected to a gate and a drain of the NMOS transistor  132  and an inverting input terminal of the differential amplifier circuit  104 , and a drain connected to the power supply terminal  101 . The NMOS transistor  132  has a source connected to the ground terminal  100 . The differential amplifier circuit  104  has an output terminal connected to a gate of the output transistor  105 , and a non-inverting input terminal connected to a node between one terminal of the resistor  121  and one terminal of the resistor  122 . The output transistor  105  has a source connected to the power supply terminal  101 , and a drain connected to the output terminal  102  and the other terminal of the resistor  121 . The other terminal of the resistor  122  is connected to the ground terminal  100 . The depletion type NMOS transistor  111  has a gate connected to the ground terminal  100 , a drain connected to the output terminal  102 , and a source connected to a drain of the NMOS transistor  112  and an input terminal of the inverter  113 . The NMOS transistor  112  has a gate and a source both connected to the ground terminal  100 . The NMOS transistor  114  has a gate connected to an output of the inverter  113 , a drain connected to the output terminal  102 , and a source connected to a drain of the depletion type NMOS transistor  115 . The depletion type NMOS transistor  115  has a gate and a source both connected to the ground terminal  100 . 
         [0024]    Next, the operations of the voltage regulator of the first embodiment are described. 
         [0025]    At normal temperature, the NMOS transistor  112  allows no current to flow between the output terminal  102  and the ground terminal  100 , and the depletion type NMOS transistor  111  starts in a state in which a channel is formed. Thus, High is input to the input terminal of the inverter  113 . Then, the inverter  113  outputs Low to turn off the NMOS transistor  114 . In this way, the leakage current sink circuit  107  causes no consumption current to flow at normal temperature. 
         [0026]    At high temperature, the depletion type NMOS transistor  111  causes a junction leakage current and causes an off leakage current of the NMOS transistor  112  to flow, and hence a voltage of the input terminal of the inverter  113  drops to input Low. Then, the inverter  113  outputs High to turn on the NMOS transistor  114  so that a leakage current from the output transistor  105  is sunk by a current amount that can flow through the depletion type NMOS transistor  115 . In this way, the leakage current of the output transistor  105  can be sunk to suppress the influence of the leakage current only at high temperature. 
         [0027]    Note that, a threshold of the depletion type NMOS transistor and a threshold of the NMOS transistor are determined by implanting the same ions having different concentrations into the transistors by the same device. Thus, even if the thresholds fluctuate due to variation of the device, the directions of the fluctuation are the same, and hence the process fluctuations can be suppressed. 
         [0028]    Note that, the reference voltage circuit  103  may have any configuration without limitation as long as the operations of the present invention are achieved. 
         [0029]    Further, although not illustrated, at least one depletion type NMOS transistor having a gate and a drain connected to each other may be connected in series between the drain of the NMOS transistor  112 . 
         [0030]    Further, a power supply terminal of the inverter  113  may be connected to the power supply terminal  101  or the output terminal  102 . 
         [0031]    As described above, according to the voltage regulator of the first embodiment, the leakage current sink circuit  107  can be prevented from operating to reduce the power consumption at normal temperature, and the leakage current sink circuit  107  can operate to sink the leakage current of the output transistor  105  so that the influence of the leakage current can be suppressed at high temperature. 
         [0032]    Further, the leakage current sink circuit  107  includes as elements thereof the similar transistors, namely, the depletion type NMOS transistors and the NMOS transistors so that the process fluctuations can be suppressed. 
       Second Embodiment  
       [0033]      FIG. 2  is a circuit diagram illustrating a voltage regulator according to a second embodiment of the present invention.  FIG. 2  differs from  FIG. 1  in that the drain of the NMOS transistor  114  is connected to a source of a depletion type NMOS transistor  116 , and the depletion type NMOS transistor  116  has a gate connected to the ground terminal  100 , and a drain connected to the output terminal  102 . Also with this configuration, the voltage regulator can operate as in the first embodiment. 
         [0034]    Note that, although not illustrated, even when the gate and the source of the depletion type NMOS transistor  111  are connected to each other, the voltage regulator can operate similarly. Further, the reference voltage circuit  103  may have any configuration without limitation as long as the operations of the present invention are achieved. 
         [0035]    As described above, according to the voltage regulator of the second embodiment, the leakage current sink circuit  107  can be prevented from operating to reduce the power consumption at normal temperature, and the leakage current sink circuit  107  can operate to sink the leakage current so that the influence of the leakage current can be suppressed at high temperature. Further, the leakage current sink circuit  107  includes as elements thereof the similar transistors, namely, the depletion type NMOS transistors and the NMOS transistors so that the process fluctuations can be suppressed. 
       Third Embodiment  
       [0036]      FIG. 3  is a circuit diagram illustrating a voltage regulator according to a third embodiment of the present invention.  FIG. 3  differs from  FIG. 2  in that a resistor  118  is connected between the source of the depletion type NMOS transistor  116  and the drain of the NMOS transistor  114 , and the gate of the depletion type NMOS transistor  116  is connected to the drain of the NMOS transistor  114 . 
         [0037]    Next, the operations of the voltage regulator of the third embodiment are described. 
         [0038]    At normal temperature, the NMOS transistor  112  allows no current to flow between the output terminal  102  and the ground terminal  100 , and the depletion type NMOS transistor  111  starts in a state in which a channel is formed. Thus, High is input to the input terminal of the inverter  113 . Then, the inverter  113  outputs Low to turn off the NMOS transistor  114 . In this way, the leakage current sink circuit  107  causes no consumption current to flow at normal temperature. 
         [0039]    At high temperature, the depletion type NMOS transistor  111  causes the junction leakage current and causes the off leakage current of the NMOS transistor  112  to flow, and hence the voltage of the input terminal of the inverter  113  drops to input Low. Then, the inverter  113  outputs High to turn on the NMOS transistor  114  so that the leakage current from the output transistor  105  is sunk by a current amount that can flow through the depletion type NMOS transistor  116 . In this way, the leakage current can be sunk to suppress the influence of the leakage current only at high temperature. In addition, by trimming the resistor  118  to adjust a current amount to be sunk, the influence of the leakage current can be more accurately suppressed. 
         [0040]    Note that, instead of the resistor  118 , a depletion type NMOS transistor, which has a gate and a drain connected to each other and operates in a non-saturation region, may be connected in series. 
         [0041]    Further, the reference voltage circuit  103  may have any configuration without limitation as long as the operations of the present invention are achieved. 
         [0042]    As described above, according to the voltage regulator of the third embodiment, the leakage current sink circuit  107  can be prevented from operating to reduce the power consumption at normal temperature, and the leakage current sink circuit  107  can operate to sink the leakage current so that the influence of the leakage current can be suppressed at high temperature. Further, the influence of the leakage current can be more accurately suppressed by trimming the resistor  118 . 
       Fourth Embodiment  
       [0043]      FIG. 4  is a circuit diagram illustrating a voltage regulator according to a fourth embodiment of the present invention.  FIG. 4  differs from  FIG. 1  in that the NMOS transistor  114  is changed to a PMOS transistor  119 , and the inverter  113  is eliminated. A gate of the PMOS transistor  119  is connected to the drain of the NMOS transistor  112 . 
         [0044]    Next, the operations of the voltage regulator of the fourth embodiment are described. 
         [0045]    At normal temperature, the NMOS transistor  112  allows no current to flow between the output terminal  102  and the ground terminal  100 , and the depletion type NMOS transistor  111  starts in a state in which a channel is formed. Thus, High is input to the gate of the PMOS transistor  119  to turn off the PMOS transistor  119 . In this way, the leakage current sink circuit  107  causes no consumption current to flow at normal temperature. 
         [0046]    At high temperature, the depletion type NMOS transistor  111  causes the junction leakage current and causes the off leakage current of the NMOS transistor  112  to flow, and hence a voltage of the gate of the PMOS transistor  119  drops to turn on the PMOS transistor  119 . Then, the leakage current from the output transistor  105  is sunk by a current amount that can flow through the depletion type NMOS transistor  115 . In this way, the leakage current can be sunk to suppress the influence of the leakage current only at high temperature. Because the gate of the PMOS transistor  119  inputs a signal directly from the NMOS transistor  112 , the off leakage current can be increased along with an increase in temperature to increase a gate-source voltage of the PMOS transistor  119  so that a current to be sunk can flow even in the non-saturation state. Hence, even when the leakage current sink circuit  107  is in a lower temperature state, the leakage current can be sunk bit by bit. Further, the number of the elements can be reduced to reduce an area of the leakage current sink circuit  107 . 
         [0047]    Note that, the reference voltage circuit  103  may have any configuration without limitation as long as the operations of the present invention are achieved. 
         [0048]    As described above, according to the voltage regulator of the fourth embodiment, the leakage current sink circuit  107  can be prevented from operating to reduce the power consumption at normal temperature, and the leakage current sink circuit  107  can operate to sink the leakage current so that the influence of the leakage current can be suppressed at high temperature. 
         [0049]      FIG. 5  is a circuit diagram illustrating another example of the voltage regulator according to the present invention.  FIG. 5  differs from  FIG. 1  in that NMOS transistors  201  and  202  and fuses  203  and  204  are added. 
         [0050]    The NMOS transistor  201  has a gate and a source connected to the ground terminal  100 , and a drain connected to one terminal of the fuse  203 . The other terminal of the fuse  203  is connected to the input terminal of the inverter  113 . The NMOS transistor  202  has a gate and a source connected to the ground terminal  100 , and a drain connected to one terminal of the fuse  204 . The other terminal of the fuse  204  is connected to the input terminal of the inverter  113 . Other connections are the same as those of  FIG. 1 . 
         [0051]    In the voltage regulator illustrated in  FIG. 5 , by trimming the fuses  203  and  204 , a leakage current that flows when the leakage current sink circuit  107  and the output transistor  105  have the same temperature can have an optimal value, and a temperature at which the leakage current from the output transistor  105  is sunk can thus be adjusted. 
         [0052]    Note that, the three NMOS transistors  201 ,  202 , and  112  are connected in parallel, but the number of the transistors is not limited to three and four or more transistors may be connected in parallel. Further, even when the configuration illustrated in  FIG. 5  is applied to the circuits illustrated in  FIG. 2  to  FIG. 4 , the same effects can be obtained. 
         [0053]    As described above, according to the voltage regulator of the present invention, the leakage current sink circuit  107  can be prevented from operating to reduce the power consumption at normal temperature, and the leakage current sink circuit  107  can operate to sink the leakage current from the output transistor  105  so that the influence of the leakage current can be suppressed at high temperature.