Abstract:
Circuits and methods are provided for providing high speed operational amplifiers and, in particular, operational amplifiers having frequency compensation circuits that provide improved slew rates with low power dissipation when configured with feedback. Frequency compensation schemes are provided to enable dynamic configuration of frequency compensation circuits implementing miller compensation whereby nodal connections of compensation capacitors are changed during driver setup and driving periods such that compensation capacitors are connected to source voltages to rapidly charge/discharge compensation capacitors using supply source currents during setup period, while providing frequency compensation during the setup and driving periods to maintain circuit stability and prevent oscillation of an output voltage due to the feedback.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority to Korean Patent Application No. 10-2004-0077156, filed on Sep. 24, 2004, which is incorporated herein by reference.  
       TECHNICAL FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to high speed operational amplifiers and, more specifically, to differential amplifiers having frequency compensation circuits that provide improved slew rates with low power dissipation.  
       BACKGROUND  
       [0003]     In general, operational amplifiers are versatile integrated circuits that are commonly implemented in various types of electronic circuits. For instance, operational amplifiers are typically used as output drivers for LCD (liquid crystal display) devices, DACs (digital-to-analog converters), ADCs (analog-to-digital converters), switched capacitor filters, analog filters, etc. In LCD devices, source driver circuits are constructed using operational amplifiers as source line drivers for driving an output signal to transfer an amplified color signal to a TFT LCD panel. The source line drivers operate by differentially amplifying input signals applied to non-inverting and inverting input terminals of a differential input stage of the operational amplifiers.  
         [0004]     With operational amplifiers, the performance and reliability of the electronic circuit depends on the slew rate, or the response speed of an output signal as function of an input signal. Currently, high resolution LCD panel displays such as QVGA (quarter video graphic array) and VGA (video Graphics Array) are continually being developed and optimized to provide increasing resolution. As the resolution increases, the activation period of the input signal to drive the TFT-LCD panel becomes shorter. As a result, it is important that the slew rate of the differential amplifier be minimized.  
         [0005]      FIG. 1  illustrates a conventional operational amplifier ( 100 ) having a two-stage topology that provides rail-to-rail common mode range of operation at the input and output of the operational amplifier. In general, the operational amplifier ( 100 ) comprises a differential input circuit ( 110 ), a folded cascode stage ( 120 ) (gain stage) and a class AB output stage ( 130 ). The differential input circuit ( 110 ) and folded cascode stage ( 120 ) form a folded cascode OTA (operational transconductance amplifier) amplifier which amplifies the difference of two input voltages applied to a non-inverting INP and inverting INN terminals, and generates a current at the output stage ( 130 ). In addition, the operational amplifier ( 100 ) comprises a frequency compensation circuit ( 140 ) that implements a known cascoded Miller frequency compensation scheme to enhance phase margin and reduce oscillation, as is known in the art. The architecture and operation of the operational amplifier ( 100 ) is well-known in the art, and a detailed explanation is not necessary. For illustrative purposes, however, a brief description of constituent components and functions of the operational amplifier ( 100 ) will be provided hereafter.  
         [0006]     The differential input circuit ( 110 ) is designed to provide rail-to-rail operation, wherein an input common mode voltage can vary throughout the range between the positive power supply rail voltage VDD and the negative power supply rail voltage VSS. The differential input circuit ( 110 ) comprises a first differential amplifier comprising PMOS transistors DTR 11  and DTR 12 , a second differential amplifier comprising NMOS transistors DTR 21  and DTR 22 , a first current source ITR 1  and a second current source ITR 2 . The PMOS transistors DTR 11  and DTR 12  (of the first differential amplifier) are a matched transistor pair having a common source configuration with source electrodes commonly connected to a node N 10 . The first current source ITR 1  is connected between the node N 10  and a positive supply rail voltage VDD. The first current source ITR 1  is a PMOS transistor, which sinks a bias current IB 1  of the first differential amplifier so that substantially constant bias current is provided to the PMOS transistors DTR 11  and DTR 12 . A bias control voltage VB 1  input to a gate electrode of the PMOS transistor ITR 1  controls the quantity of the bias current IB 1  provided to the first differential amplifier.  
         [0007]     Likewise, the NMOS transistors DTR 21  and DTR 22  (of the second differential amplifier) are a matched transistor pair having a common source configuration with source electrodes commonly connected to a node N 20 . The second current source ITR 2  is connected between the common node N 20  and a negative supply rail voltage VSS. The second current source ITR 2  is an NMOS transistor, which sinks a bias current IB 2  of the second differential amplifier so that substantially constant bias current is provided to the NMOS transistors DTR 21  and DTR 22 . A bias control voltage VB 6  input to a gate electrode of the transistor ITR 2  controls the quantity of the bias current IB 2  provided to the second differential amplifier. Typically, the bias control voltages VB 1  and VB 6  are controlled such that the bias current IB 1  provided to the first differential amplifier is substantially the same value as the bias current IB 2  provided to the second differential amplifier (i.e., IB 1 =IB 2 ).  
         [0008]     The gate electrodes of the transistors DTR 11  and DTR 21  are commonly connected to a positive (non-inverting) input terminal INP, and the gate electrodes of the transistors DTR 12  and DTR 22  are commonly connected to a negative (inverting) input terminal INN. The drain electrodes of the NMOS transistors DTR 21  and DTR 22  are output terminals connected to nodes N 1  and N 1 ′ in the folded cascode stage ( 120 ). The drain electrodes of the PMOS transistors DTR 11  and DTR 12  are output terminals connected to nodes N 2  and N 2 ′ in the folded cascode stage ( 120 ).  
         [0009]     In general, the folded cascode stage ( 120 ) comprises a summing circuit formed of two current mirrors and a common floating current source that drives the current mirrors. In particular, the folded cascode stage ( 12 ) comprises a first set of control transistors comprising PMOS transistors CTR 1 , CTR 2 , CTR 3  and CTR 4  and a second set of control transistors comprising NMOS transistors CTR 5 , CTR 6 , CTR 7  and CTR 8 . The first set of control transistors CTR 1 ˜CTR 4  form a first current mirror and the second set of control transistors CTR 5 ˜CTR 8  form a second current mirror. Further, bias transistors BTR 1  and BTR 3  form the floating current source which drives the current mirrors. An external bias voltage VB 2  is applied to the gates of CTR 3  and CTR 4 , and an external bias voltage VB 5  is applied to the gates of CTR 5  and CTR 6 . Further, external bias voltages VB 3  and VB 4  are applied to the gates of BTR 1  and BTR 3 , respectively.  
         [0010]     The summing circuit operates to add the output currents of the differential amplifiers in the differential input stage ( 110 ) so as to provide drive currents for the driver output stage ( 130 ). In particular, the first current mirror CTR 1 ˜CTR 4  is loaded by the drain currents of the input pairs DTR 21  and DTR 22  and the second current mirror CTR 5 ˜CTR 8  is loaded by the drain currents of the input pair DTR 11  and DTR 12 . The current mirror circuits operate to mirror the output currents at nodes N 1 ′ and N 2 ′ and add these currents to the currents at nodes N 1  and N 2  to provide drive currents for the output stage ( 130 ).  
         [0011]     The output stage ( 130 ) comprises a class-AB rail-to-rail output stage comprising a pair of common source connected output transistors PUTR and PDTR, which are connected to control nodes NC 1  and NC 2 , respectively. The cascode stage ( 120 ) includes a bias control circuit formed by a complementary pair of transistors BTR 2  and BTR 4  to provide class AB control. The transistors BTR 2  and BTR 4  are connected in parallel between control nodes NC 1  and NC 2  to supply drive currents in parallel to the output transistors PUTR and PDTR, and are biased with bias voltage VB 3  and VB 4 , respectively. The class-AB action is performed by maintaining the voltage between the gates of the output transistors PUTR and PDTR constant (i.e., NC 1 −NC 2 =constant). The floating current source biases the summing circuit as well as the class AB control circuit. The bias control transistors BTR 2  and BTR 4  and similar in structure to the floating current source transistors BTR 1  and BTR 3 , which results in a quiescent current that is independent of the supply voltage.  
         [0012]     The frequency compensation circuit ( 140 ) includes compensation capacitors C 1  and C 2 , which are connected between the output node NOUT and the cascode stage ( 120 ) to provide cascoded Miller compensation, as is known in the art. The first capacitor C 1  is connected between the output node NOUT and node N 1  and the second capacitor C 2  is connected between the output node NOUT and node N 2 . In general, the compensation circuit ( 140 ) operates to provide necessary compensation to maintain the stability when the operational amplifier is configured with feedback and increase the phase margin. However, the addition of the compensation capacitors introduces slewing of the output signal as a result of the time delay for charging and discharging the capacitors when driving the output node NOUT.  
         [0013]     More specifically, in the conventional amplifier of  FIG. 1 , the slew rate of the output signal is predominately determined by the current IS that is available to charge and discharge the compensation capacitors C 1  and C 2 . The slew rate of the output signal is determined as  
         SR   =         ⅆ   Vo       ⅆ   t       =     IS     C   ⁢           ⁢   1           ,       
 
 where Vo is the output voltage, where the available current IS for slewing is the bias current of the differential amplifier (IB 1 =IB 2 ), and where C 1 =C 2  is the capacitance of compensation capacitors. When designing the amplifier ( 100 ), the capacitors C 1  and C 2  are typically first selected using known techniques based on, e.g., amplifier gain, the frequency of operation, the load impedance, desired settling time, etc., to achieve the desired stability. The slew rate will then be determined by the bias current IB 1 =IB 2  of the differential amplifier. For example, in conventional TFT-LCD source driver circuits that implement the differential amplifier of  FIG. 1 , for example, the bias current IB 1 =IB 2  is selected so as to satisfy a maximum driver output setup time, tD, which is required when output voltage Vout swings at a maximum value. 
 
         [0014]      FIG. 4  is an exemplary waveform diagram that illustrates input and output voltages of the operational amplifier ( 100 ) when configured as a single-ended, non-inverting differential amplifier with unity gain (i.e., the output node NOUT is connected to the inverting input INN of the differential amplifiers. Ideally, the output voltage waveform (denoted as PD) should track the input voltage waveform (denoted as INP). However, the rising and falling edges of the output voltage PD have sloped transitions where the slope is determined by the slew rate. In  FIG. 1 , the slewing of the output signal NP is due to the time required for charging/discharging the compensation capacitors C 1 , C 2  when the output voltage at node NOUT changes from Vo 1  to Vo 2 . In such instance, the voltage across the compensation capacitors C 1 , C 2  must be changed by ΔV=Vo 1 −Vo 2 , which requires the capacitors C 1 , C 2  to be charged/discharged by CΔV. The nodes of the compensation capacitors C 1 , C 2  connected to the output node NOUT can be readily charged or discharged by the output currents that flow through PUTR and PDTR. However, the nodes of the compensation capacitors C 1 , C 2  connected to cascode node N 1  and N 2  are charged/discharged by a small current IS, which has a maximum value equal to bias currents IB 1 =IB 2 , which effectively limits the slew rate.  
         [0015]     To improve the slew rate, either the size of the compensation capacitors C 1  and C 2  must be decreased or the bias current of the differential amplifiers must be increased. Reducing the size of compensation capacitors C 1  and C 2 , however, results in decreased stability and oscillation of the output voltage, which is undesirable. Although the bias currents can be increased to improve the slew rate, this is undesirable as increased bias current levels result in increased power dissipation.  
       SUMMARY OF THE INVENTION  
       [0016]     In general, exemplary embodiments of the invention include high speed operational amplifiers having frequency compensation circuits that provide improved slew rates with low power dissipation. More specifically, exemplary embodiments of the invention including frequency compensation circuits implementing miller compensation, which are dynamically configured to change nodal connections of compensation capacitors during driver setup and driving periods to provide improved slew rates, while providing stable operation with low power dissipation.  
         [0017]     In one exemplary embodiment of the invention, an operational amplifier includes a first differential amplifier input stage, a second stage having an output node NOUT, and a frequency compensation circuit connected between the output node NOUT and an output node N 1  of the first differential amplifier input stage. The frequency compensation circuit comprises a first capacitor and a first and second switch. The first switch and the first capacitor are serially connected between a supply voltage rail and the output node NOUT. The second switch is connected to the output node N 1  and to a node between the first switch and the first capacitor.  
         [0018]     A control circuit generates a plurality of switch control signals when an input signal is input to a first input terminal of the differential amplifier input stage. During a first time period (output driver setup period), switch control signals are generated to activate the first switch to connect the first capacitors to the supply voltage rail, and deactivate the second switch. Thereafter, during a second time period (driving period) subsequent to the first time period, switch control signals are generated to deactivate the first switch and to activate the second switch to connect the first capacitors to the output node N 1 .  
         [0019]     In another exemplary embodiment of the invention, an operational amplifier includes a first differential amplifier input stage, a second stage having an output node NOUT, and a frequency compensation circuit connected between the output node NOUT and an output node N 1  of the first differential amplifier input stage. The frequency compensation circuit comprises a first capacitor, a second capacitor, and first, second and third switches. The first switch and the first capacitor are serially connected between a supply voltage rail and the output node NOUT. The second switch is connected to the output node N 1  and to a node between the first switch and the first capacitor. The second capacitor is connected between the output nodes NOUT and N 1 , and the third switch connected between the output node NOUT and an output terminal of the operational amplifier.  
         [0020]     A control circuit generates a plurality of switch control signals when an input signal is input to a first input terminal of the differential amplifier input stage. During a first time period (driver output setup time), switch control signals are generated to activate the first switch to connect the first capacitor to the supply voltage rail, and to deactivate the second and third switches. Thereafter, during a second time period (driving period) subsequent to the first time period, switch control signals are generated to deactivate the first switch and to activate the second and third switches to connect the first and second capacitors in parallel between the output nodes NOUT and N 1  and to connect the output node NOUT to an output pad to drive an output load.  
         [0021]     These and other exemplary embodiments, aspects, objects, features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]      FIG. 1  illustrates a conventional operational amplifier.  
         [0023]      FIG. 2  illustrates an operational amplifier according to an exemplary embodiment of the invention.  
         [0024]      FIG. 3  illustrates an operational amplifier according to another exemplary embodiment of the invention.  
         [0025]      FIG. 4  is an exemplary waveform diagram that illustrates input and output voltages of the operational amplifier of  FIG. 1  when configured as a single-ended, non-inverting differential amplifier with unity gain.  
         [0026]      FIG. 5  is an exemplary waveform diagram that illustrates input and output voltages of the operational amplifier of  FIG. 2  when configured as a single-ended, non-inverting differential amplifier with unity gain, according to an exemplary embodiment of the invention.  
         [0027]      FIG. 6  is a timing diagram that illustrates an exemplary mode of operation of the operational amplifier of  FIG. 2 , according to an exemplary embodiment of the invention.  
         [0028]      FIG. 7  is a timing diagram that illustrates an exemplary mode of operation of the operational amplifier of  FIG. 3 , according to an exemplary embodiment of the invention.  
         [0029]      FIG. 8  illustrates an operational amplifier according to another exemplary embodiment of the invention.  
         [0030]      FIG. 9  illustrates an operational amplifier according to another exemplary embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0031]      FIG. 2  illustrates an operational amplifier ( 200 ) according to an exemplary embodiment of the invention. The operational amplifier ( 200 ) has a framework similar to the operational amplifier ( 100 ) of  FIG. 1 , except that the operational amplifier ( 200 ) comprises a frequency compensation circuit ( 240 ) that is designed to improve the slew rate without increasing static power consumption. In general, the operational amplifier ( 200 ) comprises a first supply voltage (VDD) rail and a second supply voltage (VSS) rail, a differential amplifier input stage ( 110 ) comprising a non-inverting input terminal INP and an inverting signal input terminal INN, a folded cascode stage ( 120 ) connected to an output of the differential amplifier input stage ( 110 ), and a class AB output driver stage ( 130 ) for generating a driving current to drive output node NOUT. The various stages ( 110 ,  120  and  130 ) are similar in architecture and operation to the operational amplifier of  FIG. 1  and, thus, a detailed explanation is not needed.  
         [0032]     The frequency compensation circuit ( 240 ) comprises switches SW 11 , SW 12 , SW 21 , SW 22 , and SW 3  and compensation capacitors C 11 , C 12 , C 21  and C 22 . The compensation circuit ( 240 ) is connected to nodes N 1  and N 2  of the folded cascode stage ( 120 ) and to the output node NOUT. The output node NOUT is connected in feedback to the inverting input terminal (INN) of the differential amplifier input stage ( 110 ). The switch SW 11  and the capacitor C 11  are serially connected between the VDD supply voltage rail and the output node NOUT. The SW 12  and the capacitor C 12  are serially connected between the VSS supply voltage rail and the output node NOUT. The switch SW 21  is connected to node N 1  of the folded cascode stage ( 120 ) and a node N 11  between the switch SW 11  and the capacitor C 11 . The switch SW 22  is connected to node N 2  of the folded cascode stage ( 120 ) and to a node N 22  between the switch SW 12  and the capacitor C 12 . Further, the capacitor C 21  is connected between node N 1  of the folded cascode stage ( 120 ) and the output node NOUT, and the capacitor C 22  is connected between node N 2  of the folded cascode stage ( 120 ) and the output node NOUT. The switch SW 3  is connected between the output node NOUT and an output terminal (or pad) PD of the operational amplifier ( 200 ).  
         [0033]     In the exemplary embodiment of  FIG. 2 , the switches SW 11 , SW 12 , SW 21 , SW 22  and SW 3  are selectively activated and deactivated by respective control signals CTRL 1  and CTRL 2  during certain time periods to change the nodal connections of the various compensation capacitors C 11 , C 12 , C 21  and C 22  in a manner that increases the slew rate while providing stable operation. In essence, the compensation capacitors C 11  and C 21  in compensation circuit ( 240 ) can be viewed, collectively, as the compensation capacitor C 1  in compensation circuit ( 140 ) of  FIG. 1 , when the capacitors C 11  and C 21  are connected in parallel between cascode node N 1  and output node NOUT (where C 1 =C 11 +C 12 ). Similarly, the compensation capacitors C 12  and C 22  can be viewed, collectively, as the compensation capacitor C 2  in compensation circuit ( 140 ) of  FIG. 1 , when the capacitors C 12  and C 22  are connected in parallel between cascode node N 2  and output node NOUT (where C 2 =C 12 +C 22 ). As will be explained below, however, dividing each compensation capacitor C 1  and C 2  (in  FIG. 1 ) into two separate capacitors C 11 /C 21  and C 12 /C 22 , respectively, coupled with dynamic switching control provide a substantial improvement in the slew rate, while maintaining circuit stability and low power dissipation.  
         [0034]     An exemplary mode of operation of the operational amplifier ( 200 ) with the compensation circuit ( 240 ) will now be discussed with reference to the waveform diagrams of  FIGS. 5 and 6 , wherein it is assumed that the operational amplifier ( 200 ) is configured as a unity gain buffer with the output node NOUT connected to the inverting input terminal INN of the differential input stage ( 110 ), and wherein input signals are applied to the non-inverting terminal INP. For illustrative purposes, it is further assumed that a time period P (comprising periods P 1  and P 2 ) represents a row line scan time for a TFT LCD, wherein time period P 1  (t 1 ˜t 0 ) represents a fixed, predetermined source driver setup time, and period P 2  is the period for driving a source line. As noted above, as the LCDs are designed with higher resolution, the activation periods must be decreased (e.g., period P must be decreased). Consequently, it is preferable to limit the maximum, fixed setup time period P 1  that is needed for driving source lines.  
         [0035]     Referring now to  FIGS. 5 and 6 , a differential amplification operation begins at time t 0  where an input signal INP is applied to the non-inverting terminal of the input stage ( 110 ). Further, at time t 0 , control signal CTRL 1  is asserted to activate (close) switches SW 11  and SW 12  and the second control signal CTRL 2  is de-asserted to deactivate (open) switches SW 21 , SW 22  and SW 3 . Thus, at time t 0 , the compensation capacitors C 11  and C 12  are decoupled from cascode nodes N 1  and N 2 , respectively, and connected to the source (VDD) and ground (VSS) voltage rails, respectively. Moreover, the output node NOUT is decoupled from the capacitive load connected to output pad PD.  
         [0036]     At time t 0 , the compensation circuit ( 240 ) is dynamically configured in a state that enables a rapid transition of the output voltage of node NOUT during the period P 1  while providing sufficient compensation to maintain circuit stability and prevent oscillation of the output voltage. In particular, during period P 1 , the small compensation capacitors C 11  and C 12  are rapidly charged/discharged by current supplied from the source and ground voltages VDD and VSS, and the small compensation capacitors C 21  and C 22  are readily charged/discharged by the small bias current supplied by nodes N 1  and N 2 . As a result, as depicted in  FIG. 5 , the output voltage NOUT rapidly transitions to the voltage level of the input voltage INP, thereby providing improved slew rate.  
         [0037]     Moreover, during the settling period P 1 , the compensation capacitors C 21  and C 22 , although small, provide sufficient compensation to maintain stability and prevent oscillation of the output voltage of output node NOUT as a result of feedback. The compensation is realized with smaller capacitors C 21  and C 22  during period P 1  due to the fact that node NOUT is decoupled (via open switch SW 3 ) from the large output capacitive load, and replaced by an effective smaller capacitive load that is realized by small compensation capacitors C 11  and C 12  essentially acting as small load capacitors (which are smaller than the actual load capacitance) during the settling period, but which are proportionate to the values of C 21  and C 22  to provide stability.  
         [0038]     Referring again to  FIGS. 5 and 6 , at time t 1 , upon expiration of the settle period P 1 , the control signal CTRL 1  is de-asserted such that the switches SW 11  and SW 12  are deactivated (opened), and the second control signal CTRL 2  is asserted to activate (close) switches SW 21 , SW 22  and SW 3 . Thus, at time t 1 , the output node NOUT is coupled to the output pad PD (coupled to the load). In addition, the compensation capacitors C 11  and C 12  are decoupled from the supply and ground voltage rails VDD and VSS, respectively, and connected to the cascode nodes N 1  and N 2 , respectively. In this manner, compensation capacitors C 11  and C 21  are connected in parallel between node N 1  and the output node NOUT. Likewise, compensation capacitors C 12  and C 22  are connected in parallel between node N 2  and the output node NOUT.  
         [0039]     At time t 1 , the compensation circuit ( 240 ) is dynamically configured in a state to effectively drive the output load with the settled output voltage during period P 2  while providing sufficient compensation to maintain circuit stability and prevent oscillation of the output voltage. In particular, at time t 1 , when the output voltage of node NOUT is coupled to the output pad PD, the stability of the output voltage is maintained from the compensation provided by parallel connected capacitors C 11 /C 21  and C 12 /C 22  such that the output pad voltage PD does not oscillate upon connection to the output node voltage NOUT due to the feedback. Therefore, during period P 2 , the output load (e.g., source line) can be driven with sufficient compensation capacitance in proportion to the load capacitance to effectively drive the load line.  
         [0040]     In the exemplary embodiment of  FIG. 2 , increased stability is further realized by operating control transistors CTR 2  and CTR 8  in a weak inversion state such that the overdrive voltage (Vgs-Vth) is virtually 0 volts (very small 20-30 mv). By keeping the overdrive voltage of transistors CTR 2  and CTR 8  at virtually 0 v, the voltage of node N 1  is maintained at almost VDD and the voltage of node N 2  is maintained at almost VSS. In such instance, when nodes N 1  and N 11  are connected by upon activation of switch SW 21 , the significantly small voltage differential (about 0V) between such nodes will not cause voltage ripple of the output voltage at the start of driving period P 2 . Likewise, when nodes N 2  and N 22  are connected by upon activation of switch SW 22 , the significantly small voltage differential (about 0V) between such nodes will not cause voltage ripple of the output voltage at the start of period P 2 .  
         [0041]     Thus, as demonstrated above, the frequency compensation circuit ( 240 ) can be dynamically configured during different periods by controlling the switches to change the connections of the compensation capacitors, to thereby achieve increased slew rate while providing sufficient stability. In the exemplary embodiment of  FIG. 2 , the switches can be realized using NMOS or PMOS transistors, for example. The ratio of the capacitors C 21 /C 11  and C 22 /C 12  can be selected to provide a desired slew rate and stability. In one exemplary embodiment, C 11  and C 21  are selected such that the ratio C 21 /C 11 =¼ and C 22 /C 12 =¼. Moreover, the value the compensation capacitors C 11 , C 21 , C 12  and C 22  can be selected such that C 11 +C 21 =C 1  and C 12 +C 22 =C 2 , where the capacitance values of C 1  and C 2  are chosen in a manner the same or similar to the values of compensation capacitors C 1  and C 2  discussed above with reference to  FIG. 1 . The operational amplifier ( 200 ) can achieve an increased slew rate in an amount of (C 11 +C 22 )/C 21  as compared to the conventional circuit of  FIG. 1 .  
         [0042]      FIG. 3  illustrates an operational amplifier ( 300 ) according to an exemplary embodiment of the invention. The operational amplifier ( 300 ) has a framework similar to the operational amplifier ( 100 ) of  FIG. 1 , except that the operational amplifier ( 300 ) comprises a frequency compensation circuit ( 340 ) that is designed to improve the slew rate without increasing static power consumption. In general, the operational amplifier ( 300 ) comprises a first supply voltage (VDD) rail and a second supply voltage (VSS) rail, a differential amplifier input stage ( 110 ) comprising a non-inverting input terminal INP and an inverting signal input terminal INN, a folded cascode stage ( 120 ) connected to an output of the differential amplifier input stage ( 116 ), and a class AB output driver stage ( 130 ) for generating a driving current to drive output node NOUT. The various stages ( 110 ,  120  and  130 ) are similar in architecture and operation to the operational amplifier of  FIG. 1  and, thus, a detailed explanation is not needed.  
         [0043]     The frequency compensation circuit ( 340 ) comprises switches SW 11 , SW 12 , SW 21  and SW 22  and compensation capacitors C 1  and C 2 . The compensation circuit ( 340 ) is connected to nodes N 1  and N 2  of the folded cascode stage ( 120 ) and to the output node NOUT. The output node NOUT is connected in feedback to the inverting input terminal (INN) of the differential amplifier input stage ( 110 ). The switch SW 11  and the capacitor C 1  are serially connected between the VDD supply voltage rail and the output node NOUT. The SW 12  and the capacitor C 2  are serially connected between the VSS supply voltage rail and the output node NOUT. The switch SW 21  is connected to node N 1  of the folded cascode stage ( 120 ) and a node N 11  between the switch SW 11  and the capacitor C 1 . The switch SW 22  is connected to node N 2  of the folded cascode stage ( 120 ) and to a node N 22  between the switch SW 12  and the capacitor C 2 .  
         [0044]     In the exemplary embodiment of  FIG. 3 , the switches SW 11 , SW 12 , SW 21  and SW 22  are selectively activated and deactivated by respective control signals CTRL 1  and CTRL 2  during certain time periods to change the nodal connections of the various compensation capacitors C 1  and C 2  in a manner that increases the slew rate while providing stable operation. An exemplary mode of operation of the operational amplifier ( 300 ) with the compensation circuit ( 340 ) will now be discussed with reference to the waveform diagram of  FIG. 7 , wherein it is assumed that the operational amplifier ( 300 ) is configured as a unity gain buffer with the output node NOUT connected to the inverting input terminal INN of the differential input stage ( 110 ), and wherein input signals are applied to the non-inverting terminal INP. For illustrative purposes, as noted above, it further assumed that a time period P (comprising periods P 1  and P 2 ) represents a row line scan time for a TFT LCD, wherein time period P 1  (t 1 ˜t 0 ) represents a fixed, predetermined source driver setup time, and period P 2  is the period for driving a source line.  
         [0045]     Referring to  FIG. 7 , a differential amplification operation begins at time t 0  where an input signal INP is applied to the non-inverting terminal of the input stage ( 110 ). Further, at time t 0 , control signal CTRL 1  is asserted to activate (close) switches SW 11  and SW 12  and the second control signal CTRL 2  is de-asserted to deactivate (open) switches SW 21  and SW 22 . Thus, at time t 0 , the compensation capacitors C 1  and C 2  are decoupled from cascode nodes N 1  and N 2 , respectively, and connected to the source (VDD) and ground (VSS) voltage rails, respectively.  
         [0046]     At time t 0 , the compensation circuit ( 340 ) is dynamically configured in a state that enables a rapid transition of the output voltage of node NOUT during the period P 1  as the capacitors C 1  and C 2  are rapidly charged/discharged by current supplied from the source and ground voltages VDD and VSS, thereby providing improved slew rate. During the period P 1 , some instability can be realized because of the lack of Miller compensation capacitance connected between the output node NOUT and the cascode nodes N 1  and N 2 .  
         [0047]     As further depicted in  FIG. 7 , at time t 1 , upon expiration of the settle period P 1 , the control signal CTRL 1  is de-asserted such that the switches SW 11  and SW 12  are deactivated (opened), and the second control signal CTRL 2  is asserted to activate (close) switches SW 21  and SW 22 . Thus, at time t 1 , the compensation capacitors C 1  and C 2  are decoupled from the supply and ground voltage rails VDD and VSS, respectively, and connected to the cascode nodes N 1  and N 2 , respectively. Thus, at time t 1 , the compensation circuit ( 340 ) is dynamically configured in a state to effectively drive the output load with the settled output voltage during period P 2  while providing sufficient compensation capacitance to maintain circuit stability and prevent oscillation of the output voltage. Although oscillation may occur during period P 1  due to lack of miller compensation, the values of capacitors C 1  and C 2  can be chosen to rapidly dampen the voltage oscillation upon commencement of period P 2  when the capacitors C 1  and C 2  are connected to nodes N 1  and N 2 .  
         [0048]     In the exemplary embodiment of  FIG. 3 , as with the exemplary embodiment of  FIG. 2  as discussed above, increased stability is further realized by operating control transistors CTR 2  and CTR 8  in a weak inversion state such that the overdrive voltage (Vgs-Vth) is virtually 0 volts (very small 20-30 mv). By keeping the overdrive voltage of transistors CTR 2  and CTR 8  at virtually 0 v, the voltage of node N 1  is maintained at almost VDD and the voltage of node N 2  is maintained at almost VSS. In such instance, when nodes N 1  and N 11  are connected by upon activation of switch SW 21 , the significantly small voltage differential (about 0V) between such nodes will not cause voltage ripple of the output voltage at the start of driving period P 2 . Likewise, when nodes N 2  and N 22  are connected by upon activation of switch SW 22 , the significantly small voltage differential (about 0V) between such nodes will not cause voltage ripple of the output voltage at the start of period P 2 .  
         [0049]     It is to be understood that amplifiers depicted in  FIGS. 2 and 3  are merely examples of amplifier circuits which may implement frequency compensation circuits and methods according to exemplary embodiments of the invention. It is to be appreciated that frequency compensation circuits and methods of the invention can be generally applied to maintain stability in various types of multi-stage amplifiers with feedback. By way of example,  FIGS. 8 and 9  are high-level schematic illustrations of operational amplifiers according to other exemplary embodiments of the invention.  
         [0050]     In particular, referring to  FIG. 8 , an operational amplifier ( 400 ) comprises a two-stage topology with first and second stages S 1  and S 2 , and a frequency compensation circuit ( 440 ) connected between an output node NOUT and an output node (e.g., cascode node) of stage S 1 . The first stage S 1  may comprise a differential input and gain stage (e.g., cascode circuit) having any suitable framework. The second stage may comprise a gain stage (or output stage) with any suitable framework for the desired class of operation (e.g., class AB, Class A, etc.). The output node NOUT is connected to the inverting input terminal of the input stage S 1 . The frequency compensation circuit ( 440 ) comprises compensation capacitors C 11  and C 12  and switches SW 1 , SW 2  and SW 3 , and operates to provide frequency compensation and maintain stability of the output voltage as a result of the feedback. The frequency compensation circuit ( 440 ) is similar in operation and framework to the frequency compensation circuit ( 240 ) of  FIG. 2 , and thus a detailed explanation is not necessary.  
         [0051]     Referring to  FIG. 9 , an operational amplifier ( 500 ) comprises a two-stage topology with first and second stages S 1  and S 2 , and a frequency compensation circuit ( 540 ) connected between an output node NOUT and an output node (e.g., cascode node) of stage S 1 . As with the exemplary embodiment of  FIG. 8 , the first stage S 1  may comprise a differential input and gain stage (e.g., cascode circuit) having any suitable framework, and the second stage S 2  may comprise a gain stage (or output stage) with any suitable framework for the desired class of operation (e.g., class AB, Class A, etc.). The output node NOUT is connected to the inverting input terminal of the input stage S 1 . The frequency compensation circuit ( 540 ) comprises a compensation capacitor C 1  and switches SW 1  and SW 2 , and operates to provide frequency compensation and maintain stability of the output voltage as a result of the feedback. The frequency compensation circuit ( 540 ) is similar in operation and framework to the frequency compensation circuit ( 340 ) of  FIG. 3 , and thus a detailed explanation is not necessary.  
         [0052]     Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.