Abstract:
Disclosed are a sampling circuit and a receiver with which filter characteristics compatible with the reception of wideband signals can be realized with a high degree of freedom in the setting of the filter characteristics. More specifically, a sampling circuit capable of removing adjacent interfering wave signals while keeping in-band deviation small is disclosed. The sampling circuit ( 100 ) is equipped with a discrete-time analog processing circuit group ( 101 ) wherein multiple discrete-time analog processing circuits are connected in parallel, a synthesizer ( 102 ) which synthesizes the output signals from each of the circuit systems and outputs same, and a digital control unit ( 103 ) which outputs control signals. Each of the discrete-time analog processing circuits ( 101 - 1 - 101 - n ) is configured to include multiple rotate capacitor units ( 1014 ) which each includes a main rotate capacitor ( 10144 ) and a sub-rotate capacitor ( 10143 ), and only the main rotate capacitors ( 10144 ) share electric charge with a buffer capacitor ( 1022 ) included in the synthesizer ( 102 ).

Description:
TECHNICAL FIELD  
       [0001]    The present invention relates to a sampling circuit and a receiver, and, more particularly, to a technology to perform received signal processing such as frequency conversion, filter processing and so forth, by means of discrete time analog processing. 
       BACKGROUND ART 
       [0002]    A configuration has been disclosed that performs reception processing by means of direct discrete time sampling of a high-frequency signal with the aim of achieving small size and low power consumption of a receiver and integrating the analog signal processing section and digital signal processing section (see Patent Literature 1 and Non-Patent Literature 1, for example). 
         [0003]      FIG. 1  shows the overall configuration of a sampling circuit disclosed in Patent Literature 1 and Non-Patent literature 1.  FIG. 2  is a timing chart showing control signals inputted to the sampling circuit shown in  FIG. 1 . The sampling circuit shown in  FIG. 1  performs frequency conversion on a received analog RF signal using a multi-tap direct sampling mixer to obtain a discrete time analog signal. To be more specific, electrical charge transfer between capacitors included in the sampling circuit in  FIG. 1  realizes filter characteristics resulting in the product of an FIR (finite impulse response) filer and an IIR (infinite impulse response) filter. Characteristics around the passband are determined based on second-order IIR filter characteristics.  FIG. 3A  and  FIG. 3B  show examples of wideband frequency characteristics and narrowband frequency characteristics nearby the passband in the sampling circuit in  FIG. 1 . 
       CITATION LIST 
     Patent Literature 
       [0000]    
       
         PTL 1 U.S. Patent Application Laid-Open No. 2003/0035499 
       
     
       Non-Patent Literature 
       [0000]    
       
         NPL 1 R. B. Staszewski; et al. “All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS”, IEEE Journal of Solid-State Circuits, VOL. 39, NO. 12, December 2004 (p 2284˜2287, FIG. 12 to FIG. 16) 
       
     
       SUMMARY OF INVENTION  
     Technical Problem 
       [0006]    However, the conventional sampling circuit as shown in  FIG. 1  can obtain only second-order filter characteristics, and therefore has a problem that it is not possible to obtain satisfactory frequency response characteristics when the sampling circuit is attempted to be applied to a wideband radio communication system. To be more specific, when a sampling circuit having the filter characteristics shown in  FIG. 3B  is attempted to be applied to a wideband radio communication system in which signals in a neighboring channel and other interfering waves exist nearby the band to receive signals, it is not possible to fully attenuate interfering waves, and gain variations occur in the band to receive signals. 
         [0007]    In addition, with the configuration shown in  FIG. 1 , there are only three kinds of capacitance values of history capacitor  3 , rotate capacitors  4   a  to  4   h  and buffer capacitor  5 , which are circuit element values contributing to change in frequency response characteristics of filtering in the sampling circuit. Therefore, filter characteristics obtained by changing these circuit element values are limited, so that it is not possible to flexibly design filter characteristics. 
         [0008]    For example, when it is desired to realize frequency response characteristics to secure a greater amount of attenuation for cancelling interfering waves nearby the receiving channel band, it is possible to achieve the frequency response characteristics by increasing the ratio of capacitance values between history capacitor  3  and rotate capacitors  4   a  to  4   h.  However, this causes increase in gain variations in the band to receive signals. By contrast with this, when the amount of gain variations in the band to receive signals is attempted to be reduced, it is not possible to secure the amount of attenuation for interfering waves. 
         [0009]    As described above, the above-described sampling circuit has a problem that it is not possible to both secure attenuation characteristics in the interfering wave area and reduce the amount of gain variations in the band to pass received signals. 
         [0010]    It is therefore an object of the present invention to provide a sampling circuit and a receiver using time analog processing, which are able to realize filter characteristics supporting wideband signal reception and flexibly design filter characteristics. 
       Solution to Problem 
       [0011]    The sampling circuit according to the present invention adopts a configuration to include: a group of a plurality of discrete time analog processing circuits arranged in parallel, each having a sampling switch that samples an inputted signal, a history capacitor connected to the sampling switch and a plurality of rotate capacitor units connected to the history capacitor in parallel; a adding section including: a buffer capacitor that accumulates electrical charge outputted from each of the discrete time analog processing circuits; and a dump switch that controls a connection state between each of the discrete time analog processing circuits and the buffer capacitor; and a digital control unit that outputs a plurality of control signal to control operation of the plurality of rotate capacitor units and operation of the adding section, wherein: each of the plurality of rotate capacitor units has an integration switch, a release switch, and a main rotate capacitor and a sub-rotate capacitor to which the integration switch and the release switch are connected; and at a timing electrical charge accumulated in the history capacitor is inputted to the rotate capacitor unit, the main rotate capacitor and the sub-rotate capacitor are connected to the history capacitor in parallel via the integration switch, and, at a timing electrical charge is outputted from the rotate capacitor unit to the buffer capacitor, only the main rotate capacitor is connected to the release switch. 
         [0012]    The sampling circuit according to the present invention adopts a configuration to include: an electrical charge sampling circuit having a sampling switch that samples an inputted signal and a history capacitor connected to the sampling switch; a group of a plurality of discrete time analog processing circuits arranged in parallel, each having a rotate capacitor unit and a buffer capacitor unit; a adding section that adds outputs from the group of the discrete time analog processing circuits and outputs a result; and a digital control unit that outputs a plurality of control signals to control operation of the group of the discrete time analog processing circuits and operation of the adding section, wherein: the rotate capacitor unit has a first integration switch, a main rotate capacitor and a sub-rotate capacitor connected to the first integration switch in parallel; and the buffer capacitor unit has a second integration switch and a buffer capacitor connected to the second integration switch; at a timing electrical charge accumulated in the history capacitor is inputted to the rotate capacitor unit, the main rotate capacitor and the sub-rotate capacitor are connected to the history capacitor in parallel via the first integration switch; and at a timing electrical charge is outputted from the rotate capacitor unit to the adding section, only the main rotate capacitor is connected to the adding section. 
       Advantageous Effects of Invention 
       [0013]    According to the present invention, a circuit configuration is adopted where a plurality of rotate capacitor units each including a main rotate capacitor and sub-rotate capacitor are used as components of a plurality of discrete time analog processing circuits, where only the main rotate capacitor shares electrical charge with a buffer capacitor in the output side, so that it is possible to increase the kinds of element parameters that can be set in the circuit. Therefore, even if the sampling circuit is applied to a wideband radio communication system, it is possible to effectively attenuate interfering waves and reduce gain variations in the band to pass received signals. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0014]      FIG. 1  is a connection diagram showing an example of the configuration of a conventional sampling circuit; 
           [0015]      FIG. 2  is a timing chart showing control signals used in the conventional sampling circuit; 
           [0016]      FIG. 3  is a characteristic diagram realized by the conventional sampling circuit; 
           [0017]      FIG. 4  is a block diagram showing a configuration of a sampling receiver according to Embodiment 1; 
           [0018]      FIG. 5  is a connection diagram showing the configuration of the sampling circuit according to Embodiment 1; 
           [0019]      FIG. 6  is a connection diagram showing the specific configuration of the sampling circuit according to Embodiment 1; 
           [0020]      FIG. 7  is a timing chart showing control signals used in Embodiment 1; 
           [0021]      FIG. 8  shows a configuration of a variable capacitance capacitor according to Embodiment 1; 
           [0022]      FIG. 9  is a connection diagram showing a configuration of a sampling circuit according to Embodiment 2; 
           [0023]      FIG. 10  is a timing chart showing control signals used in Embodiment 2; 
           [0024]      FIG. 11  is a characteristic diagram showing examples of a third IIR filter characteristic realized in Embodiment 2; 
           [0025]      FIG. 12  is a connection diagram showing a configuration of a sampling circuit according to Embodiment 3; 
           [0026]      FIG. 13  is a connection diagram showing a specific configuration of the sampling circuit according to Embodiment 3; and 
           [0027]      FIG. 14  is a timing chart showing control signals used in Embodiment 3. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0028]    Now, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
       Embodiment 1 
       [0029]      FIG. 4  shows the configuration of a sampling receiver according to the present embodiment. Sampling receiver  10  has antenna  11 , LNA (low noise amplifier)  12 , sampling circuit  13 , local frequency oscillating section  14 , A/D (analog to digital) conversion processing section  15  and digital reception processing section  16 . 
         [0030]    This sampling receiver  10  receives electromagnetic wave  21  transmitted at carrier frequency f RF , and applies discrete-time frequency conversion and filter processing on this received signal to extract a desired signal component. Then, sampling receiver  10  performs digital reception processing by converting the extracted desired signal component to a digital signal, and outputs resultant received data  27 . 
         [0031]    Antenna  11  receives electromagnetic wave  21  transmitted at carrier frequency (f RF ) from a transmitting station (not shown) and converts it to analog RF signal  22 . LNA  12  amplifies analog RF signal  22  and outputs the result. 
         [0032]    Amplified analog RF signal  23  and local frequency signal  24  are inputted to sampling circuit  13 . Sampling circuit performs filter processing by performing discrete-time frequency conversion on analog RF signal  23  using local frequency signal (f LO )  24  to obtain baseband signal  25  resulting in extracting a desired signal component, and outputs baseband signal  25 . 
         [0033]    Local frequency oscillating section  14  generates local frequency signal (f LO )  24  used in sampling processing and frequency conversion processing, and outputs it to sampling circuit  13 . 
         [0034]    A/D conversion processing section  15  quantizes an inputted baseband signal into digital values at a predetermined sampling frequency and outputs digital baseband signal  26  having been converted to a digital signal. 
         [0035]    Digital reception processing section  16  performs predetermined digital reception processing, including demodulation, decoding and so forth, on inputted digital baseband signal  26 , and outputs resultant reception data  27 . 
         [0036]      FIG. 5  shows the configuration of sampling circuit  13  in  FIG. 4 . Sampling circuit  100  in  FIG. 5  is equivalent to sampling circuit  13  in  FIG. 4 . In sampling circuit  100 , a plurality of discrete time analog processing circuits  101 - 1  to  101 - n  that perform discrete time analog processing on input signals are arranged in parallel. By individually setting circuit element values for respective discrete time analog processing circuits  101 - 1  to  101 - n,  it is possible to produce better filter frequency response characteristics than in a conventional sampling circuit having a single discrete time analog processing circuit. 
         [0037]    &lt;Configuration of a Sampling Circuit&gt; 
         [0038]      FIG. 6  shows the specific configuration of sampling circuit  100  in  FIG. 5 . Sampling circuit  100  in  FIG. 6A  has discrete time analog processing circuit group  101  in which n (n sequences of) discrete time analog processing circuits  101 - 1  to  101 - n  are connected in parallel, adder  102  and digital control unit  103 . 
         [0039]    Adder  102  has buffer capacitor  1022 , dump switch  1021  that controls connection and disconnection between buffer capacitor  1022  and the plurality of discrete time analog processing circuits  101 - 1  to  101 - n  connected in parallel, and reset switch  1023  to ground main rotate capacitors  10144   1  to  10144   n  in discrete time analog processing circuits  101 - 1  to  101 - n.    
         [0040]    In addition, digital control unit  103  generates and transmits control signals to discrete time analog processing circuits  101 - 1  to  101 - n,  dump switch  1021  and reset switch  1023 , respectively. 
         [0041]    Next, the configuration of each of discrete time analog processing circuits  101 - 1  to  101 - n  will be explained. Discrete time analog processing circuit  101 - 1  to  101 - n  have the same configuration, so that discrete time analog processing circuit  101 - 1  will be explained here. 
         [0042]    Discrete time analog processing circuit  101 - 1  has TA (transconductance amplifier)  1011  that converts an inputted analog RF signal (voltage signal) to a current signal; sampling switch  1012  connected to TA (transconductance amplifier) 1011 ; history capacitor  1013  connected to sampling switch  1012 ; and a rotate capacitor unit group composed of a plurality of rotate capacitor units  1014  connected to sampling switch  1012  and history capacitor  1013  in parallel. 
         [0043]      FIG. 6B  shows the configuration of rotate capacitor unit  1014 . Rotate capacitor unit  1014  has sub-rotate capacitor  10143  and main rotate capacitor  10144 . Integration switch  10141  and release switch  10145  are connected to sub-rotate capacitor  10143 , and integration switch  10142  and release switch  10146  are connected to main rotate capacitor  10144 . 
         [0044]    Digital control unit  103  generates control signals S 1  to S 2N , SAZ, SBZ, D and R. Control signals S 1  to S 2N  are supplied to integration switches  10141  and  10142  in each rotate capacitor unit  1014 . Control signals SAZ and SBZ are supplied to release switches  10145  and  10146  in each rotate capacitor unit  1014 . In addition, control signal D and control signal R are supplied to dump switch  1021  and reset switch  1023 , respectively. 
         [0045]    Any of control signals S 1  to S 2N  is inputted to terminal CK 1  and control signal SAZ or SBZ is inputted in terminal CK 2  in  FIG. 6B . In  FIG. 6A , each of discrete time analog processing circuits  101 - 1  to  101 - n  has 2×N (N is a natural number equal to or greater than 1) rotate capacitor units  1014 . Control signal SAZ is inputted to terminal CK 2  of each of left half N rotate capacitor units  1014 , among 2×N rotate capacitor units  1014 , and control signal SBZ is inputted to terminal CK 1  of each of right half N rotate capacitor units  1014 . Here, this is merely an example, and the arrangement of rotate capacitor units  1014  to receive control signal SAZ and rotate capacitor units  1014  to receive control signal SBZ is not limited to this. 
         [0046]    Here, in each of discrete time analog processing circuits  101 - 1  to  101 - n,  the capacitance value of history capacitor  1013 , and the capacitance value of sub-rotate capacitor  10143  and the capacitance value of main rotate capacitor  10144  in each rotate capacitor unit  1014  are set based on equations described later. In  FIG. 6 , in order to clearly show these capacitance values, capacitance C H  of history capacitor  1013 , capacitance C Rs  of sub-rotate capacitor  10143  and capacitance C Rm  of main rotate capacitor  10144  are specified by assigning subscript k (k=1 to n). 
         [0047]    Here, as described above, each of discrete time analog processing circuits  101 - 1  to  101 - n  has 2×N (N is a natural number equal to or more than 1) rotate capacitor units  1014 . Each rotate capacitor unit  1014  has one main rotate capacitor  10144  and one sub-rotate capacitor  10143 . One integration switch  10141  and one release switch  10145  are connected to sub-rotate capacitor  10143 . Meanwhile, one integration switch  10142  and one release switch  10146  are connected to main rotate capacitor  10144 . 
         [0048]    Therefore, one discrete time analog processing circuit  101 - k  includes 2×N rotate capacitor units  1014   k , 2×N main rotate capacitors  10144   k , 2×N sub-rotate capacitors  10143   k , 2×N integration switches  10141   k  and  10142   k , and 2×N release switches  10145   k  and  10146   k . 
         [0049]    Here, with the present embodiment, although another configuration is possible where capacitors for feedback control and control signals therefor are used, illustrations and descriptions of capacitors for feedback control are omitted for ease of explanation. 
         [0050]      FIG. 7  is a timing chart showing control signals outputted from digital control unit  103  and local frequency signals supplied to sampling switch  1012 . Control signals S 1  to S 2N  have high level periods shifted from each other, and each high level period is equivalent to M periods of a local frequency signal LO. In addition, control signal SAZ and control signal SBZ alternately come into the high level. Upon receiving these control signals, rotate capacitor unit  1014  performs alternately integration and release of sub-rotate capacitor  10143  and main rotate capacitor  10144 , according to on/off states of integration switches  10141  and  10142  and release switches  10145  and  10146 . 
         [0051]    Here, it is distinctive that, while electrical charge inputted to main rotate capacitor  10144  during integration switch  10142  being turned on, is partly released to buffer capacitor  1022  upon turning release switch  10146  on, electrical charge inputted to sub-rotate capacitor  10143  during integration switch  10141  being tuned on, is grounded and discharged at the timing release switch  10145  is turned on. 
         [0052]    In this way, by using main rotate capacitor  10144  sharing electrical charge with buffer capacitor  1022  and sub-rotate capacitor  10143  not sharing electrical charge with buffer capacitor  1022 , it is possible to switch the capacitance value of rotate capacitor unit  1014  between the time to input electrical charge and the time to output electrical charge. By this configuration, even if discrete time analog processing circuits  101 - 1  to  101 - n  share common TA (transconductance amplifier)  1011 , it is possible to control respective gains. By this means, when a circuit to realize filter characteristics having attenuation poles described later is designed, it is possible to control attenuation pole frequencies by capacitance ratios. 
         [0053]    Here, adder  102  is not necessarily realized with a passive configuration by means of electrical charge sharing using buffer capacitor  1022  shown in  FIG. 6 . For example, it is possible to prepare the same number of buffer capacitors  1022  as the number of parallel discrete time analog processing circuits  101 - 1  to  101 - n,  and output signals from buffer capacitors  1022  by means of an adding circuit using an operational amplifier. 
         [0054]    Here, the present invention does not limit what circuit configuration after buffer capacitor  1022  is. For example, a circuit configuration is possible in which a discrete signal value defined by the amount of electrical charge accumulated in buffer capacitor  1022  is quantized into a digital value while holding the discrete signal value as is (sampling and holding), and then digital signal processing is performed. In addition, for example, another configuration is possible in which a discrete signal value defined by the amount of electrical charge accumulated in buffer capacitor  1022  is converted to a voltage, and then signal processing is performed. 
         [0055]    &lt;Operation of a Sampling Circuit&gt; 
         [0056]    Next, operation of sampling circuit  100  according to the present embodiment will be explained. In each of discrete time analog processing circuits  101 - 1  to  101 - n,  inputted analog RF signal  23  is converted to an analog RF current signal by means of TA (transconductance amplifier)  1011 , and sampled with local frequency signal (f LO )  24  having approximately the same frequency LO as that of the analog RF current signal by means of sampling switch  1012 . Moreover, in each of discrete time analog processing circuits  101 - 1  to  101 - n  in sampling circuit  100 , electrical charge of sampled signals is integrated and shared between history capacitor  1013 , and sub-rotate capacitor  10143  and main rotate capacitor  10144  in rotate capacitor unit  1014  to form a discrete time signal. 
         [0057]    Moreover, in each of discrete time analog processing circuits  101 - 1  to  101 - n,  integration switch  10141  and integration switch  10142  and release switch  10145  and release switch  10146  in rotate capacitor unit  1014  are controlled on and off between history capacitor  1013 , and sub-rotate capacitor  10143  and main rotate capacitor  10144  in rotate capacitor unit  1014 , so that the operation equivalent to the first FIR filter characteristic and the second FIR filter characteristic is performed. 
         [0058]    Here, the first FIR filter characteristic is determined by the time length for a high level period of each of control signals S 1  to S 2N  in each of a plurality of discrete time analog processing circuit  101 - 1  to  101 - n.  That is, the first FIR filter characteristic is determined by the time length for integration by charging and electrical charge sharing between history capacitor  1013 , and sub-rotate capacitor  10143  and main rotate capacitor  10144  in rotate capacitor unit  1014 . With the present embodiment, the time length for integration corresponds to M periods of a local frequency LO, so that it is possible to represent the transfer function of the first FIR filter characteristic realized in each discrete time analog processing circuit by equation 1. 
         [0000]    
       
         
           
             
               
                 
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         [0059]    In addition, the second FIR filter characteristic is determined by the number N of main rotate capacitors  10144  selected by control signal SAZ or SBZ, among 2×N main rotate capacitors  10144  in rotate capacitor unit  1014 , and the value of the above-described M, regardless of the capacitance value of each capacitor used in each of a plurality of discrete time analog processing circuits  101 - 1  to  101 - n.  It is possible to represent the transfer function of the second FIR filter characteristic realized in each discrete time analog processing circuit by equation 2. 
         [0000]    
       
         
           
             
               
                 
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         [0060]    In addition, in each of a plurality of discrete time analog processing circuits  101 - 1  to  101 - n,  electrical charge is shared between history capacitor  1013  and the capacitors connected to history capacitor  1013  by control signals S 1  to S 2N  supplied to integration switches  10141  and  10142 , among sub-rotate capacitors  10143  and main rotate capacitors  10144  in a plurality of rotate capacitor units  1014 . Then, the results of electrical charge sharing accumulated in main rotate capacitors  10144  in each discrete time analog processing circuit are added by electrical charge sharing in subsequent adder  102  to realize the first and second IIR filters. 
         [0061]    This first IIR filter characteristic is obtained by sharing among C Rmk , C Rsk , C Hk  and the electrical charge inputted from TA (transconductance amplifier)  1011  and the electrical charge accumulated in C Hk  resulting from electrical charge sharing one timing before. It is possible to represent this transfer function by equation 3. Here, sub-rotate capacitor  10143  is not connected to buffer capacitor  1022 . By this means, in each of discrete time analog processing circuits  101 - 1  to  101 - n,  numerator coefficients of a transfer function are determined by the ratio of the capacitance of main rotate capacitor  10144  to the capacitance of history capacitor  1013 . In addition, denominator coefficients of a transfer function are determined by the ratio of a total sum of the capacitance of main rotate capacitor  10144  and sub-rotate capacitor  10143  to the capacitance of history capacitor  1013 . 
         [0062]    To be more specific, in equation 3, these proportions are described as C Rmk /C Hk  in the numerator and (C Rmk +C Rsk )/C Hk  in the denominator after Σ. It is possible to individually set these ratios, according to the capacitances of main rotate capacitor  10144  and sub-rotate capacitor  10143 , and it is possible to set coefficients of a transfer function based on capacitance ratios. Capacitance ratios are accurate in manufacture by means of semiconductor process and allow accurate coefficient setting. 
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         [0063]    Here, in equation 3, T s  is the time length for the sampling period of sampling with local signal frequency LO in sampling switch  1012 . In addition, g m  is the transconductance value of TA (transconductance amplifier)  1011  in each of discrete time analog processing circuits  101 - 1  to  101 - n.  In addition, C Hk  is the capacitance value of history capacitor  1013  in k-th (k is a natural number from 1 to n) of discrete time analog processing circuits  101 - k.  In addition, C Rmk  is the capacitance value of one sub-rotate capacitor  10143  in k-th discrete time analog processing circuits  101 - k.  In addition, C Rsk  is the capacitance value of one main rotate capacitor  10144  in k-th of discrete time analog processing circuits  101 - k.    
         [0064]    Moreover, electrical charge is shared between buffer capacitor  1022  and main rotate capacitor  10144  connected to buffer capacitor  1022  by control signal SAZ or SBZ supplied to release switch  10146  in rotate capacitor unit  1014 , among main rotate capacitors  10144  in a plurality of rotate capacitor units  1014 . The second IIR filter characteristic is realized by this electrical charge sharing between main rotate capacitor  10144  and buffer capacitor  1022 . It is possible to represent its transfer function by equation 4. In equation 4, C B  represents the capacitance value of buffer capacitor  1022 . 
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         [0065]    Here, the terms are not distinctly separated in equations 1 to 4, but organized for ease of explanation of a method of designing filter characteristics of a sampling circuit described later. To be accurate, the addition in equation  3  is realized at the same time as the second IIR filter characteristic is realized. 
         [0066]    As described above, total transfer characteristic H(z) of filtering processing obtained in the entire sampling circuit  100  shown in  FIG. 6A  is represented as the characteristic obtained by combining the characteristics of equation 1 to equation 4, and can be substituted for equation 5. 
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                               1 
                             
                           
                         
                       
                       · 
                       
                         1 
                         N 
                       
                       · 
                       
                         
                           1 
                           - 
                           
                             z 
                             
                               
                                 - 
                                 M 
                               
                               × 
                               N 
                             
                           
                         
                         
                           1 
                           - 
                           
                             z 
                             
                               - 
                               M 
                             
                           
                         
                       
                       · 
                       
                         
                           
                             Mg 
                             m 
                           
                            
                           
                             T 
                             S 
                           
                         
                         
                           π 
                            
                           
                             
                               ∑ 
                               
                                 k 
                                 = 
                                 1 
                               
                               n 
                             
                              
                             
                                 
                             
                              
                             
                               C 
                               Rmk 
                             
                           
                         
                       
                     
                      
                     
                         
                     
                      
                     
                       
                         ∑ 
                         
                           k 
                           = 
                           1 
                         
                         n 
                       
                        
                       
                           
                       
                        
                       
                         
                           
                             
                               z 
                               
                                 - 
                                 M 
                               
                             
                              
                             
                               
                                 C 
                                 Rmk 
                               
                               / 
                               
                                 C 
                                 Hk 
                               
                             
                           
                           
                             
                               
                                 ( 
                                 
                                   
                                     C 
                                     Rmk 
                                   
                                   + 
                                   
                                     C 
                                     Rsk 
                                   
                                 
                                 ) 
                               
                               / 
                               
                                 C 
                                 Hk 
                               
                             
                             + 
                             1 
                             - 
                             
                               z 
                               
                                 - 
                                 M 
                               
                             
                           
                         
                         · 
                         
                           
                             
                               ∑ 
                               
                                 k 
                                 = 
                                 1 
                               
                               n 
                             
                              
                             
                               
                                 NC 
                                 Rmk 
                               
                               / 
                               
                                 C 
                                 B 
                               
                             
                           
                           
                             
                               
                                 ∑ 
                                 
                                   k 
                                   = 
                                   1 
                                 
                                 n 
                               
                                
                               
                                   
                               
                                
                               
                                 
                                   NC 
                                   Rmk 
                                 
                                 / 
                                 
                                   C 
                                   B 
                                 
                               
                             
                             + 
                             1 
                             - 
                             
                               z 
                               
                                 - 
                                 MN 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   5 
                   ] 
                 
               
             
           
         
       
     
         [0067]    It is important that, in the transfer function represented by equation 5, if capacitance values C Hk , C Rmk , C Rsk  and C B  of respective capacitors in n discrete time analog processing circuits  101 - 1  to  101 - n  are set at random, it is not possible to obtain desired filter frequency response characteristics. 
         [0068]    In particular, it is possible to understand that the first IIR filter characteristic represented by equation 3 is the sum of first-order IIR filter characteristics. To be short, it is possible to describe as equation 6. In equation 6, constant a k  corresponds to C Rmk /C Hk  in equation 3, and constant b k  corresponds to (C Rmk +C Rsk )/C Hk  in equation 3. Therefore, it is possible to determine constant a k  and constant b k  based on the capacitances of main rotate capacitor  10144  sub-rotate capacitor  10143 , respectively. 
         [0000]    
       
         
           
             
               
                 
                   ( 
                   
                     Equation 
                      
                     
                         
                     
                      
                     6 
                   
                   ) 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     H 
                     
                       IIR 
                        
                       
                           
                       
                        
                       3 
                     
                   
                   = 
                   
                     
                       ∑ 
                       
                         k 
                         = 
                         1 
                       
                       n 
                     
                      
                     
                         
                     
                      
                     
                       
                         a 
                         k 
                       
                       
                         
                             
                         
                          
                         
                           
                             b 
                             k 
                           
                           + 
                           1 
                           - 
                           
                             z 
                             
                               - 
                               M 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   6 
                   ] 
                 
               
             
           
         
       
     
         [0069]    By calculating constants a k  and b k  using DC gains, the positions of attenuation poles and so forth, which are set at random, and comparing H IIR1  in equation 3 and H IIR3  in equation 6, it is possible to calculate the values of g m , C Rmk , C Rsk  and C Hk . A specific method of selecting element values will be described in Embodiment 2. 
         [0070]    Meanwhile, it is significantly difficult to accurately make the difference of transconductance value g m  of TA (transconductance amplifier)  1011  between each circuit. Therefore, in the configuration shown in  FIG. 6A , g m  of TA (transconductance amplifier)  1011  is the same value between each of discrete time analog processing circuits  101 - 1  to  101 - n.  By this means, it is possible to greatly reduce design difficulties as compared to a case in which discrete time analog processing circuits have TAs (transconductance amplifiers)  1011  having different g m  values. In addition, each of discrete time analog processing circuits  101 - 1  to  101 - n  has one TA (transconductance amplifier)  1011 , so that it is possible to produce an effect of increasing gain as compared to a case in which one TA (transconductance amplifier)  1011  is used across entire sampling circuit  100 . 
         [0071]    As described above, according to the present embodiment, a circuit configuration is adopted where a plurality of discrete time analog processing circuits  101 - 1  to  101 - n  are connected in parallel, electrical charge signals obtained in each of discrete time analog processing circuits  101 - 1  to  101 - n  are weighted by the capacitance ratio between main rotate capacitor  10144  and sub-rotate capacitor  10143  and adding the results in buffer capacitor  1022 . By this means, it is possible to increase the order of the IIR filter realized in sampling circuit  100 . 
         [0072]    Moreover, by using main rotate capacitor  10144  and sub-rotate capacitor  10143 , it is possible to perform weighting by the capacitance ratio appropriate for semiconductor process in high-order IIR filter design for sampling circuit  100 . In addition, the kinds and the number of circuit element values that can be set in filter design increase, so that it is possible to dramatically increase the flexibility of filter design. In particular, by adequately setting the number n of discrete time analog processing circuits  101 - 1  to  101 - n  provided in parallel, depending on the filter performance required for a receiver, it is possible to randomly set the number of attenuation poles and the positions in the frequency domain, and therefore it is possible to realize filter characteristics supporting reception of wideband signals. 
         [0073]    Here, in  FIG. 6 , a case has been explained where, in each of n discrete time analog processing circuits  101 - 1  to  101 - n,  capacitance values C Rsk  of sub-rotate capacitors  10143  in rotate capacitor units  1014  are the same value in one discrete time analog processing circuit, and also capacitance values C Rmk  of main rotate capacitors  10144  in rotate capacitor units  1014  are the same value in one discrete time analog processing circuit, but capacitance values C Rsk  and capacitance values C Rmk  are respectively different between different discrete time analog processing circuits. However, the present invention is not necessarily limited to this. 
         [0074]    In addition, in one discrete time analog processing circuit, it is possible to make respective capacitance values of main rotate capacitors  10144  differ and also make respective capacitance values of sub-rotate capacitors  10144  differ between a plurality of rotate capacitor units  1014 . In this case, the transfer function varies, so that it is necessary to change the method of designing filter characteristics of a sampling circuit, according to the present embodiment. In addition, it is reasonable to use one of discrete time analog processing circuits requiring the greatest necessary amplitude gain, as the reference for weighting, without providing sub-rotate capacitor  10143 . 
         [0075]    With the configuration according to the present embodiment, although a case has been explained as an example where local frequency signals LO are generated not only in digital control unit  103  and supplied to sampling switch  1012 , the present invention is not limited to this. Another configuration is possible where local frequency signals LO are generated in digital control unit  103  and supplied to sampling switch  1012 . 
         [0076]    With the configuration according to the present embodiment, although a case has been explained where, after electrical charge sharing, main rotate capacitor  10144  and sub-rotate capacitor  10143  are grounded by reset switch  1023 , electrical charge may be held without grounding. It is possible to improve gain by holding electrical charge without grounding. It is possible to reduce the number of switches and control signals to simplify the circuit configuration. 
         [0077]    In addition, a configuration is possible where the capacitance value of each of main rotate capacitor  10144 , sub-rotate capacitor  10143 , history capacitor can be changed. For example, as shown in  FIG. 8 , by controlling switch W(i)(i=1˜N) on and off to determine the entire capacitance, it is possible to change gains, cutoff frequencies and attenuation pole frequencies with a single circuit configuration. Here, the entire circuit configuration shown in  FIG. 8  is equivalent to one capacitor. 
       Embodiment 2 
       [0078]    With the present embodiment, examples of circuit configurations and realized filter characteristics in discrete time analog processing circuits in parallel shown in Embodiment 1, will be explained, where the number of circuits to be in parallel is 3. In addition, with the present embodiment, appropriate configuration requirements will be presented in this case. 
         [0079]      FIG. 9  shows the configuration of a sampling circuit according to the present embodiment. In sampling circuit  200 , the number of discrete time analog processing circuits  101 - 1  to  101 - n  connected in parallel in sampling circuit  100  shown in  FIG. 6 , is 3. Here, a case is shown as an example where the number (2×N) in each of discrete time analog processing circuits  101 - 1 ,  101 - 2  and  101 - 3  is, for example, 2×N=4 (i.e. N=2). In  FIG. 9 , the same components and actions as in  FIG. 6  are assigned the same reference numerals and descriptions will be omitted. 
         [0080]    Calculated element values often include negative coefficients. In these cases, it is preferable to switch between the positive phase and the negative phase of differential signals inputted to TA (transconductance amplifier)  1011  or buffer capacitor  1022 . 
         [0081]      FIG. 10  is a timing chart showing control signals outputted from digital control unit  103  and local frequency signals supplied to sampling switch  1012  in the present embodiment. Control signals S 1  to S 4  have high level periods shifted from each other, and each high level period is equivalent to M periods of a local frequency signal LO. With the present embodiment, M is set 8, for example. 
         [0082]    Control signals S 1  to S 4  are sent to integration switches  10141  and  10142  in each of discrete time analog processing circuits  101 - 1 ,  101 - 2  and  101 - 3 . Control signal SAZ and control signal SBZ are alternately in the high level and are sent to release switches  10145  and  10146  to allow two rotate capacitor units  1014  to connect with one another. Control signals SAZ and SBZ are sent to release switches  10145  and  10146  in each of discrete time analog processing circuits  101 - 1 ,  101 - 2  and  101 - 3 . Control signal D and control signal R are sent to dump switch  1021  and reset switch  1023 , respectively. 
         [0083]    The filter characteristic realized in the entire sampling circuit  200  configured as described above, is equivalent to equation 5, where n=3. 
         [0084]    In equation 5, part forming the third IIR filter characteristic includes three first-order low pass filters connected in parallel, so that it is possible to describe equation 6 with n=3. 
         [0085]    Here, coefficient values of equation 6 are defined to provide attenuation poles at designated frequencies. Assume that the DC gain is D, b 1 , b 2  and b 3  are any values and ω N  is the angular frequency of the attenuation pole, it is possible to derive a 1 , a 2  and a 3  from the following equation. 
         [0000]    
       
         
           
             
               
                 
                   
                       
                   
                    
                   
                     ( 
                     
                       Equation 
                        
                       
                           
                       
                        
                       7 
                     
                     ) 
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     [ 
                     
                       
                         
                           
                             a 
                             1 
                           
                         
                       
                       
                         
                           
                             a 
                             2 
                           
                         
                       
                       
                         
                           
                             a 
                             3 
                           
                         
                       
                     
                     ] 
                   
                   = 
                   
                     
                       
                         ⌈ 
                         
                           
                             
                               
                                 Re 
                                  
                                 
                                   [ 
                                   
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               2 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               3 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                   
                                   ] 
                                 
                               
                             
                             
                               
                                 Re 
                                  
                                 
                                   [ 
                                   
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               1 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               3 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                   
                                   ] 
                                 
                               
                             
                             
                               
                                 Re 
                                  
                                 
                                   [ 
                                   
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               1 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               2 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                   
                                   ] 
                                 
                               
                             
                           
                           
                             
                               
                                 Im 
                                  
                                 
                                   [ 
                                   
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               2 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                     
                                       
                                         
                                           ( 
                                           
                                             
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                                               3 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                   
                                   ] 
                                 
                               
                             
                             
                               
                                 Im 
                                  
                                 
                                   [ 
                                   
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               1 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               3 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                   
                                   ] 
                                 
                               
                             
                             
                               
                                 Im 
                                  
                                 
                                   [ 
                                   
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               1 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                     
                                       
                                         
                                           ( 
                                           
                                             
                                               b 
                                               2 
                                             
                                             + 
                                             1 
                                             - 
                                             
                                               z 
                                               N 
                                               
                                                 - 
                                                 M 
                                               
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                   
                                   ] 
                                 
                               
                             
                           
                           
                             
                               
                                 1 
                                 / 
                                 
                                   b 
                                   1 
                                 
                               
                             
                             
                               
                                 1 
                                 / 
                                 
                                   b 
                                   2 
                                 
                               
                             
                             
                               
                                 1 
                                 / 
                                 
                                   b 
                                   3 
                                 
                               
                             
                           
                         
                         ⌉ 
                       
                       
                         - 
                         1 
                       
                     
                      
                     
                       [ 
                       
                         
                           
                             0 
                           
                         
                         
                           
                             0 
                           
                         
                         
                           
                             D 
                           
                         
                       
                       ] 
                     
                   
                 
               
               
                 
                   [ 
                   7 
                   ] 
                 
               
             
             
               
                 
                   
                       
                   
                    
                   
                     
                       where 
                        
                       
                           
                       
                        
                       
                         z 
                         n 
                       
                     
                     = 
                     
                       
                         cos 
                          
                         
                             
                         
                          
                         
                           ω 
                           N 
                           t 
                         
                       
                       + 
                       
                         j 
                          
                         
                             
                         
                          
                         sin 
                          
                         
                             
                         
                          
                         
                           ω 
                           N 
                           t 
                         
                       
                     
                   
                 
               
               
                 
                     
                 
               
             
           
         
       
     
         [0086]    By comparing the part forming the third IIR filter characteristic in equation 5, where n=3, with equation 6, it is possible to obtain equation 8, equation 9 and equation 10. Then, it is possible to derive the element value of each circuit element from equation 8, equation 9 and equation 10. 
         [0000]        C   Rm1 /(C Rm1   +C   Rs1 )=−( a   1   b   2 )/( a   2   b   1 ), C   Rm2 /( C   Rm2   +C   Rs2 )=1, C   Rm3 /( C   Rm3   +C   Rs3 )=−( a   3   b   2 )/( a   2   b   3 )   (Equation 8)
 
         [0000]        C   Rm1   +C   Rs1   =b   1   C   H1   ,C   Rm2   +C   Rs2   =b   2   C   H2   ,C   Rm3   +C   Rs3   =b   3   C   H3    (Equation 9)
       where, C H1 , C H2  and C H3  are any values       
 
         [0000]    
       
         
           
             
               
                 
                   ( 
                   
                     Equation 
                      
                     
                         
                     
                      
                     10 
                   
                   ) 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     g 
                     m 
                   
                   = 
                   
                     
                       
                         
                           a 
                           2 
                         
                          
                         
                           ( 
                           
                             
                               a 
                               1 
                             
                             + 
                             
                               a 
                               2 
                             
                             + 
                             
                               a 
                               3 
                             
                           
                           ) 
                         
                       
                       
                         
                           b 
                           2 
                         
                          
                         
                           ( 
                           
                             
                               a 
                               1 
                             
                             + 
                             
                               a 
                               2 
                             
                             + 
                             
                               a 
                               3 
                             
                           
                           ) 
                         
                       
                     
                     · 
                     
                       
                         π 
                          
                         
                           ( 
                           
                             
                               C 
                               
                                 Rm 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             + 
                             
                               C 
                               
                                 Rm 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             + 
                             
                               C 
                               
                                 Rm 
                                  
                                 
                                     
                                 
                                  
                                 3 
                               
                             
                           
                           ) 
                         
                       
                       
                         MT 
                         LO 
                       
                     
                   
                 
               
               
                 
                   [ 
                   10 
                   ] 
                 
               
             
           
         
       
     
         [0088]    For example, by deriving each circuit element value in sampling circuit  200  from equation 8, equation 9 and equation 10, assuming conditions represented in equation 11, it is possible to calculate the value represented by equation 12. 
         [0000]      f LO =1 GHz,b 1 =0.2513,b 2 =0.5027,b 3 =0.7540,M=8,N=1,C H1 =C H2 =C H3 =5 pF,ω N =10 MHz   (Equation 11)
 
         [0000]      g m =49.655 mS,C Rm1 =750.13 fF,C Rs1 =506.50 fF,C Rm2 =2.5133 pF,C Rs2 =0,C Rm3 =2.0174 pF,C Rs3 =1.7525 pF   (Equation 12)
 
         [0089]      FIG. 11  shows the frequency response characteristic of the third IIR filter obtained when sampling circuit  200  with three parallel circuits shown in  FIG. 9  uses the conditions shown in equation 11 and the circuit element values shown in equation 12, where the characteristic is represented by solid lines. Meanwhile, as a comparative example, dotted-lines represent the frequency response characteristic in a case in which a configuration with only one discrete time analog processing circuit is employed to limit the bandwidth to obtain attenuation of 3 dB (decibel) to one. It is possible to see from  FIG. 11  that, by employing a configuration in which three parallel discrete time analog processing circuits are arranged, instead of a configuration with only one discrete time analog processing circuit, it is possible to secure a greater amount of attenuation in the cutoff frequency band without changing the gain in the pass frequency band. Here, the value of buffer capacitor  1022  is 10 pF at the time to calculate the characteristic. During circuit implementation, it is necessary to realize negative coefficients in one discrete time analog processing circuit, so that some measures such as switching between the positive phase and the negative phase and so forth are required. 
         [0090]    As described above, according to the present embodiment, a circuit configuration is adopted where three discrete time analog processing circuits  101 - 1 ,  101 - 2  and  101 - 3  are connected in parallel, and electrical charge signals obtained in respective circuits are added in buffer capacitor  1022 . By this means, it is possible to increase the order of the IIR filter realized in sampling circuit  200 , and therefore, it is possible to realize frequency response characteristics and bandpass characteristics to provide more significant frequency-to-attenuation characteristics. 
         [0091]    Here, with the present embodiment, although a case has been shown where the number of discrete time analog processing circuits  101 - 1  to  101 - n  is 3, the present invention is not limited to this number of circuits in parallel. Based on the subject matters disclosed in the above-described embodiments, it is possible to readily apply the present invention to a case in which the number of circuits in parallel is four or more, or two, naturally. 
       Embodiment 3 
       [0092]    With the present embodiment, a configuration will be shown where it is possible to realize the sum of first-order IIR filter characteristics using a single TA (transconductance amplifier)  1011  across the entire circuit, like Embodiment 1. That is, although with Embodiment 1, each of a plurality of discrete time analog processing circuits  101 - 1  to  101 - n  has one TA (transconductance amplifier)  1011  as shown in  FIG. 6 , one TA (transconductance amplifier)  1011  is shared across the entire sampling circuit according to the present embodiment. 
         [0093]      FIG. 12  shows the configuration of a sampling circuit according to the present embodiment. Sampling circuit  300  in  FIG. 12  is equivalent to sampling circuit  13  in  FIG. 14 . Sampling circuit  300  has electrical charge sampling circuit  301  that converts input voltage signals to current signals and samples them, discrete time analog processing circuit group  302  that has a plurality of discrete time analog processing circuits  302 - 1  to  302 - n  arranged in parallel and performs discrete time analog processing, and adder  303  that adds outputs from discrete time analog processing circuits  302 - 1  to  302 - n  and outputs the result. By individually setting respective circuit element values of discrete time analog processing circuits  302 - 1  to  302 - n,  it is possible to realize better filter frequency response characteristics with a configuration using a single TA (transconductance amplifier) than with a conventional sampling circuit having only one discrete time analog processing circuit. 
         [0094]      FIG. 13A  shows a specific configuration of the sampling circuit shown in  FIG. 12 . Sampling circuit  301  has TA (transconductance amplifier)  3011 , sampling switch  3012  and history capacitor  3013 . 
         [0095]    Each of discrete time analog processing circuits  302 - 1  to  302 - n  has rotate capacitor unit  3021  shown in  FIG. 13B  and buffer capacitor unit  3022  shown in  FIG. 13C . Rotate capacitor unit  3021  has integration switch  30211 , main rotate capacitor  30212  and sub-rotate capacitor  30213 . Buffer capacitor unit  3022  has integration switches  30221  and  30222 , and buffer capacitor  30223 . 
         [0096]    Adder  303  has dump switch  3031 , buffer capacitor  3032 , and reset switches  3033  and  3034 . 
         [0097]    Digital control unit  304  supplies control signals to electrical charge sampling circuit  301 , discrete time analog processing circuits  302 - 1  to  302 - n  and adder  303  to perform frequency conversion, decimation and filtering in sampling circuit  300  in order to produce desired characteristics. 
         [0098]      FIG. 14  is a timing chart showing control signals LO 1  to LO 4  outputted from digital control unit  304 . LO 1  to LO 4  have high level periods shifted from each other, each of which is ¼ of an input signal period. 
         [0099]    Next, operations of sampling circuit  300  will be explained. First, electrical charge sampling circuit  301 , and discrete time analog processing circuits  302 - 1  to  302 - n  sample electrical charge of input analog RF signal  23 . That is, analog RF signal  23 , an inputted voltage signal, is converted to a current signal by TA (transconductance amplifier)  3011 . The current signal is inputted to history capacitor  3013 , main rotate capacitor  30212  and sub-rotate capacitor  30213  via sampling switch  3012  and integration switch  30211  in rotate capacitor unit  3021 , and electrical charge is integrated during the period equal to ¼ of a desired input signal period. History capacitor  3013  holds the electrical charge at the time of last sampling as the initial state of sampling, so that it is possible to produce an IIR filter effect. 
         [0100]    Next, in each of a plurality of discrete time analog processing circuits  302 - 1  to  302 - n  arranged in parallel, rotate capacitor unit  3021  and buffer capacitor unit  3022  share electrical charge. That is, main rotate capacitor  30212   k , sub-rotate capacitor  30213   k , and buffer capacitor  30223   k  share electrical charge by receiving, as input, electrical charge accumulated in main rotate capacitor  30212   k  and sub-rotate capacitor  30213   k , via integration switches  30221   k  and  30222   k . Buffer capacitor  30223   k  holds the electrical charge at the time of last electrical charge sharing, as the initial state of electrical charge supply, so that it is possible to produce an IIR filter effect. 
         [0101]    Next, electrical charge is shared between main rotate capacitor  30212   k  in each of a plurality of discrete time analog processing circuits  302 - 1  to  302 - n  arranged in parallel and buffer capacitor  3032  in adder  303 . That is, main rotate capacitor  30212   k  and buffer capacitor  3032  share electrical charge by receiving, as input, electrical charge accumulated in main rotate capacitors  30212   1 to N , via dump switch  3031 . This electrical charge sharing allows a passive circuit to output the adding result of outputs from discrete time analog processing circuits  302 - 1  to  302 - n.  In addition, buffer capacitor  3032  holds the electrical charge at the time of last electrical charge sharing, as the initial state of electrical charge supply, so that it is possible to produce an IIR filter effect. 
         [0102]    Finally, the potentials of main rotate capacitor  30212   k  and sub-rotate capacitor  30313   k  are reset through reset switches  3033  and  3034  to set the potential allowing sampling switch  3012  to correctly operate. 
         [0103]    By repeating the above-described operation, it is possible to provide a transfer function represented by equation 13. 
         [0000]    
       
         
           
             
               
                 
                   
                       
                   
                    
                   
                     ( 
                     
                       Equation 
                        
                       
                           
                       
                        
                       13 
                     
                     ) 
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     H 
                      
                     
                       ( 
                       z 
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                         ( 
                         
                           
                             
                               
                                 
                                   
                                     
                                       
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                                         ( 
                                         
                                           
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                                          
                                         k 
                                       
                                     
                                   
                                 
                                 
                                   
                                     
                                       ( 
                                       
                                         
                                           C 
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                                     / 
                                     
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                         ) 
                       
                     
                   
                 
               
               
                 
                   [ 
                   13 
                   ] 
                 
               
             
           
         
       
     
         [0104]    Here, g m  represents the g m  value of TA (transconductance amplifier)  3011 . In addition, T s  represents the period of a local (LO) signal. Moreover, C H  is the capacitance value of history capacitor  3013 , C Rmk  is the capacitance value of main rotate capacitor  30212 , C Rsk  is the capacitance value of sub-rotate capacitor  30213 , C Bl  is the capacitance value of buffer capacitor  30223  in buffer capacitor unit  3022  and C B  is the capacitance value of buffer capacitor  3032  in adder  303 . 
         [0105]    Moreover, assume that C Rmk +C Rsk =C R , it is possible to describe equation 14. 
         [0000]    
       
         
           
             
               
                 
                   
                       
                   
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                     ( 
                     
                       Equation 
                        
                       
                           
                       
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                       14 
                     
                     ) 
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
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                   [ 
                   14 
                   ] 
                 
               
             
           
         
       
     
         [0106]    As seen from equation 14, with a configuration using single TA (transconductance amplifier)  3011 , it is possible to realize the sum of first-order filter IIR filter characteristics in which coefficients are determined based on the capacitance ratio between circuit elements. By this means, it is possible to realize a circuit configuration which can be easily designed and has resistance to variations in semiconductor process. 
         [0107]    As described above, according to the present embodiment, a circuit configuration is adopted where a plurality of discrete time analog processing circuits  302 - 1  to  302 - n  are connected in parallel and are connected to electrical charge sampling circuit  301 , and respective electrical charge signals obtained in discrete time analog processing circuits  302 - 1  to  302 - n  are added in buffer capacitor  3032 , and main rotate capacitor  30212  and sub-rotate capacitor  30213  are used in each of discrete time analog processing circuits  302 - 1  to  302 - n,  so that it is possible to realize the sum of first-order IIR filter characteristics in single electrical charge sampling circuit  301  and determine the coefficient values based on capacitance ratios. 
         [0108]    By this means, it is possible to perform weighting according to the capacitance ratio suitable for semiconductor process in a circuit configuration using a single electrical charge sampling circuit. In addition, the kinds and numbers of circuit element values able to be set in filter design, so that it is possible to dramatically improve the flexibility of filter design. In particular, the number of discrete time analog processing circuits arranged in parallel is adequately set depending on the filter performance required for a receiver, so that it is possible to randomly set the number of attenuation poles and the positions in the frequency domain, and therefore realize filter characteristics supporting reception of wideband signals. 
         [0109]    Moreover, with the above-described circuit configuration, it is possible to reduce unnecessary harmonic response by using signals having high level periods shifted from each other, each of which is equal to ¼ of an input signal period, as LO 1  to LO 4 . This is enabled in a case in which a sampling circuit has a single discrete time analog processing circuit. 
         [0110]    The disclosure of Japanese Patent Application No. 2008-308953, filed on Dec. 3, 2008, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. 
       INDUSTRIAL APPLICABILITY  
       [0111]    The direct sampling circuit and receiver according to the present invention is useful for a high-frequency signal processing circuit in the receiving section in a radio communication apparatus and is appropriate for signal frequency conversion and filtering processing. 
       REFERENCE SIGNS LIST 
       [0000]    
       
           10  Sampling receiver 
           12  Low noise amplifier 
           13 ,  100 ,  200 ,  300  Sampling circuit 
           101 ,  302  Discrete time analog processing circuit group 
           101 - 1  to  101 - n,    302 - 1  to  302 - n  Discrete time analog processing circuit 
           1011 ,  3011  TA (transconductance amplifier) 
           1012 ,  3012  Sampling switch 
           1013 ,  3013  History capacitor 
           1014 ,  3021  Rotate capacitor unit 
           10141 ,  10142 ,  30211 ,  30221 ,  30222  Integration switch 
           10143 ,  30213  Sub-rotate capacitor 
           10144 ,  30212  Main rotate capacitor 
           10145 ,  10146  Release switch 
           102 ,  303  Adder 
           1021 ,  3031  Dump switch 
           1022 ,  3022 ,  30223  Buffer capacitor 
           1023 ,  3033  Reset switch 
           103 ,  304  Digital control unit 
           301  Electrical charge sampling circuit 
           3022  Buffer capacitor unit