Abstract:
In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. Correction control circuitry is configured to control gain control circuitry based on the asymmetrical signal to adjust a gain of the amplifier to correct the asymmetric signal. A first adjustment of the gain control circuitry is performed during a first interval and a second adjustment of the gain control circuitry is performed during a second interval to correct the asymmetric signal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present disclosure claims priority to U.S. Provisional App. No. 61/258,148 for “Asymmetry Correction Circuit for Read Channel” filed Nov. 4, 2009, which is incorporated herein by reference in its entirety for all purposes. 
    
    
     BACKGROUND 
     Particular embodiments generally relate to asymmetric correction circuits. 
     Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. 
     In a read channel for a hard disk drive, a signal received from a read head of the disk drive may be asymmetric. For better performance, the symmetry of the asymmetric signal should be corrected. 
       FIG. 1   a  depicts a graph  100  of an asymmetric signal  102  and ideal signal  104 . Ideal signal  104  includes pulses in a period that have absolute peak amplitudes that are equal and asymmetric signal  102  has pulses that have unequal absolute peak amplitudes in the period. The correction of asymmetric signal  102  is performed to correct the asymmetry of asymmetric signal to be similar to the symmetry of ideal signal  104 . 
     One way of correcting asymmetric signal  102  is to generate a square term that increases or decreases the amplitude of asymmetric signal  102 .  FIG. 1   b  depicts a graph showing the correction. A square term  106  is combined with asymmetric signal  102  to produce an output signal  108 . However, an additional path and circuitry is needed to generate the square term. 
     Another way of correcting asymmetric signal  102  is to use extra current sources.  FIG. 2  depicts an example of a circuit for correcting asymmetric signal  102  using signal currents IS 1 , IS 2 , and IS 3 . The output of circuit  200  is across resistors  208   a  and  208   b . Resistors  208   a  and  208   b  are connected between signal currents IS 1  and IS 2 , and voltage is supplied by a common mode voltage source, Vcom. The current is varied to correct asymmetric signal  102 . For example, adding more current through resistors  208   a  and  208   b  increases the output voltage (e.g., the amplitude of asymmetric signal  102 ) while decreasing the current through resistors  208   a  and  208   b  decreases the output voltage. 
     The switching section includes two pair of high speed field effect transistors  210  (including transistors T 1 , T 2 ) and  212  (including transistors T 3 , T 4 ) for switching biasing current to the amplifier section  214 . Each of the transistors T 1 , T 2 , T 3 , T 4  can behave as a switch. These characteristics of the transistors T 1 , T 2 , T 3 , T 4  cause biasing current to flow through only the transistors having a positive gate, and not through the transistors having a negative gate. Therefore, whichever transistors are conducting are passing all the current. The current is not shared by each of the transistors of the switching pair. 
     The amplifier section  214  is a differential amplifier comprising a pair of field effect transistors T 5  and T 6 . The differential amplifier is responsive to the differential input signal, Vip and Vin, producing a differential current, δ i , proportional to the transconductance (or gain gm) of the transistor pair  214  times the differential signal input voltage Vip−Vin. Therefore, a positive differential current δ i  flows through transistor T 5  and correspondingly, a negative differential current, −δ i  flows through transistor T 6  when Vip is positive and Vin is negative. Conversely, when Vip is negative and Vip is positive, −δ i  flows in transistor T 5  and δ i  flows in transistor T 6 . Also, when Vin is positive, transistors T 1  and T 4  are conducting causing a current of 2×δ i  to flow across the biasing resistors  208   a  and  208   b . When Vin is positive, transistors T 2  and T 3  are conducting, also causing a current of 2×δ i , to flow across resistors  208   a  and  208   b . Adding more current through resistors  208   a  and  208   b  increases the output voltage (e.g., the amplitude of asymmetric signal  102 ). 
     Although using current summing may correct the asymmetry of asymmetric signal  102 , the use of current summing needs higher supply voltage due to stacking switches on top of the signal current path, and may cause higher power usage, higher current, and use more area on an integrated circuit (IC) chip. 
     SUMMARY 
     In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. Correction control circuitry is configured to control gain control circuitry based on the asymmetrical signal to adjust a gain of the amplifier to correct the asymmetric signal. A first adjustment of the gain control circuitry is performed during a first interval and a second adjustment of the gain control circuitry is performed during a second interval to correct the asymmetric signal. 
     In one embodiment, the gain control circuitry comprises input resistance circuitry and feedback resistance circuitry. 
     In one embodiment, the correction control circuitry adjusts a ratio of resistance between the input resistance circuitry to the feedback resistance circuitry. 
     In one embodiment, the first adjustment lowers an input resistance of the input resistance circuitry and the second adjustment lowers the feedback resistance of the feedback resistance circuitry. 
     In another embodiment, a system includes the apparatus and further includes a pre-amplifier configured to receive the asymmetrical signal from a read head of a hard disk drive, wherein the pre-amplifier is configured to send the asymmetric signal to the amplifier. 
     In another embodiment, a method includes: receiving an asymmetric signal at an amplifier; adjusting a gain of the amplifier to correct the asymmetric signal to produce a corrected signal, wherein a first adjustment of gain control circuitry is performed during a first half period and a second adjustment of the gain control circuitry is performed during a second half period to correct the asymmetric signal; and outputting the corrected signal. 
     In one embodiment, adjusting the gain comprises adjusting an input resistance and a feedback resistance. 
     The following detailed description and accompanying drawings provide a more detailed understanding of the nature and advantages of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a graph of an asymmetric signal and an ideal signal. 
         FIG. 2  depicts an example of a circuit for correcting the asymmetric signal using current sources. 
         FIG. 3  depicts an example of a system for asymmetric correction according to one embodiment. 
         FIG. 4  shows an example of a graph showing a differential asymmetric signal according to one embodiment. 
         FIG. 5  depicts a more detailed example of a system for correcting asymmetry according to one embodiment. 
         FIG. 6  depicts a simplified flowchart of a method for forming asymmetric correction according to one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Described herein are techniques for asymmetric correction. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
       FIG. 3  depicts an example of a system  300  for asymmetric correction according to one embodiment. System  300  may be used in a read channel to process signals received from a read head of a hard disk drive (HDD). However, system  300  may be used in other applications where correction of an asymmetric signal is required. The asymmetric signal may be received from a pre-amplifier in the read channel. A corrected signal may then be output to an analog processor, such as an analog to digital converter (ADC). 
     The asymmetric signal may be received at a variable gain amplifier (VGA)  302 . In one embodiment, the asymmetric signal may be a differential asymmetric signal. When used in this disclosure, asymmetric signal may refer to a differential version or a single-ended version. 
     Amplifier  302  corrects the asymmetry of the asymmetric signal to output the corrected signal at nodes Vn and Vp. The corrected signal is output by increasing or decreasing the gain of amplifier  302 . 
     To adjust the gain, gain control circuitry  304   a/b  and asymmetric correction control circuitry  306   a/b  are used. Gain control circuitry  304   a  and asymmetric correction control circuitry  306   a  may process a positive asymmetric signal and gain control circuitry  304   b  and asymmetric correction control circuitry  306   b  may process a negative asymmetric signal. 
     Asymmetric correction control circuitry  306  is used to control gain control circuitry  304 . For example, driver circuitry  308  may be used to control switches in asymmetric correction control circuitry  306 . By controlling switches, a resistance ratio of between an input resistance and a feedback resistance may be adjusted in gain control circuitry  304   a . By changing the ratio, the gain of amplifier  302  is adjusted, which corrects the asymmetry of the asymmetric signal. 
       FIG. 4  shows an example of a graph  400  showing a differential asymmetric signal according to one embodiment. A positive asymmetric signal  402   a  and a negative asymmetric signal  402   b  form the differential asymmetric signal. Also, a positive ideal signal  404   a  and a negative ideal signal  404   b  are shown. To correct asymmetric signals  402   a  and  402   b , the gain is boosted in the signal path for asymmetric signals  402   a  and  402   b  in odd half periods, e.g., a first T/ 2 , a third T/ 2 , a fifth T/ 2 , and so on. This increases the amplitude of the asymmetric signal to be closer to the amplitude of ideal signals  404   a  and  404   b , respectively. For example, as shown in the first T/ 2 , the amplitude of asymmetric signal  402   a  is below that of ideal signal  404   a  and increasing the amplitude of asymmetric signal  402   a  corrects the symmetry of asymmetric signal. Also, asymmetric signal  402   b  may have the gain increased in the negative direction. 
     Also, the amplitude of asymmetric signal  402   a  and  402   b  is above the peak amplitude of ideal signal  404   a  in the even half periods. If the signal path gain is reduced for the even half periods, e.g., a second T/ 2 , a fourth T/ 2 , a sixth T/ 2 , and so on, then asymmetric signals  402   a  and  402   b  have their amplitude reduced to be closer to the amplitude of ideal signals  404   a  and  404   b.    
       FIG. 5  depicts a more detailed example of system  300  for correcting asymmetry according to one embodiment. Gain control circuitry  304   a / 304   b  may include input resistance circuitry  504   a / 504   b  and feedback resistance circuitry  502   a / 502   b . Also, asymmetric correction control circuitry  306  may include switches  505   a   1 / 505   b   1  and  505   a   2 / 505   b   2 . System  300  will be described with respect to the positive signal of a differential asymmetric signal; however, a person of skill in the art will recognize how the negative signal may be processed based on the teachings and disclosure described. 
     Driver circuitry  308  includes a driver  506 , which controls switches  505 . Switches  505  may be controlled to adjust the ratio of resistance between input resistance circuitry  504  and feedback resistance circuitry  502 . By adjusting the ratio, the gain of amplifier  302  is adjusted such that correction of asymmetric signal  402  is performed. 
     The magnitude of asymmetry correction may be controlled by how much the gain is changed. For example, an analog-to-digital converter (ADC) may sample asymmetric signal  402  and determine how much gain adjustment is needed to correct asymmetric signal  402 . A peak amplitude at a time for asymmetric signal  402  is compared to a peak amplitude for ideal signal  404  at that time. The amount of correction is then determined Gain control circuitry  304   a  is then adjusted to provide the determined gain. For example, a ratio of resistance for input resistance  504   a  and feedback resistance  502   a  is adjusted to adjust the gain of amplifier  302  to the desired amount. 
     To adjust the gain, different combinations of resistances are used in feedback resistance  502  and input resistance  504 . Switch  505   a   2  is used to couple a resistor R 2   a  to be in parallel to a resistor R 2 . Also, a switch  505   a   1  is used to couple a resistor R 1   a  to be in parallel to a resistor R 1 . By coupling the resistor R 2   a  to resistor R 2 , the feedback resistance is lowered. Also, by coupling a resistor R 1   a  in parallel to a resistor R 1 , the input resistance is lowered. This may be used to change the resistance ratio for input resistance  504   a  and feedback resistance  502   a.    
     One example of controlling switches  505   a   1  and  505   a   2  will now be described. Other ways of controlling switches may also be appreciated. Referring to  FIG. 4 , in the first T/ 2 , the amplitude of asymmetric signal  402   a  is less than the amplitude of ideal signal  404   a . To correct asymmetric signal  402   a , the gain is increased. In one example, switch  505   a   1  is closed and switch  505   a   2  is opened. This causes input resistance  504   a  to be R 1 ∥R 1   a  and feedback resistance  502   a  to be R 2 . The gain is: 
               RFeedback   RInput     =       R   ⁢           ⁢   2       R   ⁢           ⁢   1   ⁢          R   ⁢           ⁢   1   ⁢   a                 
where RFeedback is the resistance of feedback resistance  502   a  and RInput is the resistance of input resistance  504   a . Because input resistance  504   a  is lowered due to the addition of resistor R 1   a  in parallel with resistor R 1 , gain is increased (the gain when both switches  505   a   1  and  505   b   1  open is R 2 /R 1 ). This corrects the asymmetry of asymmetric signal  402   a.  
 
     In the second T/ 2 , the amplitude of asymmetric signal  402   a  is greater than the amplitude of ideal signal  404   a  (in the negative direction). To correct asymmetric signal  402   a , the gain is decreased. In one example, switch  505   a   1  is opened and switch  505   a   2  is closed. 
     This causes feedback resistance  502   a  to be R 2 ∥R 2   a  and input resistance  504   a  to be R 1 . The gain is: 
               RFeedback   RInput     =       R   ⁢           ⁢   2   ⁢          R   ⁢           ⁢   2   ⁢   a           R   ⁢           ⁢   1             
where RFeedback is the resistance of feedback resistance  502   a  and RInput is the resistance of input resistance  504   a . Because feedback resistance  502   a  is lowered due to the addition of resistor R 2   a  in parallel with resistor R 2 , gain is decreased. This corrects the asymmetry of asymmetric signal  402   a.  
 
     The above process repeats itself for each period. For example, the third T/ 2  have switched controlled as described with respect to the first T/ 2  and the fourth T/ 2  have switches controlled as described with respect to the second T/ 2 . 
     Driver  506  may be used as driver circuitry  308 . Driver  506  receives driver input signal outputs a differential signal (D 1  and D 2 ) to drive switches  505 . The polarity of the driver signals may change according to the asymmetric signal polarity. In one embodiment, when the square wave is high, switch  505   a   1  may be closed and switch  505   a   2  may be open. When the square wave is low, switch  505   a   1  may be opened and switch  505   a   2  may be closed. 
     Although the above structure was described, other implementations may be used to change the resistance ratio between output resistance  502   a  and input resistance  504   a . Also, different types of devices for resistors R 1 , R 1   a , R 2 , R 2   a , and switches  505  may be used. For example, metal oxide semiconductor field effect transistors (MOSFETs) may be used. Although two parallel resistors are described for input resistance  504  and feedback resistance  502 , X number of resistors in parallel may be used to provide different granularity of resistances (and thus gain), where X is an integer. For example, X number of switches in input resistance  504  may be opened or closed to achieve a desired input resistance and feedback resistance. 
       FIG. 6  depicts a simplified flowchart of a method for forming asymmetric correction according to one embodiment. At  602 , a difference is determined between asymmetric signal  402  and ideal signal  404 . For example, an ADC may sample asymmetric signal  402  and determine a difference between the sample and ideal signal  404  at a multiple times. 
     At  604 , the difference is analyzed for asymmetric signal  402  to determine the amount of gain needed to correct the asymmetry. 
     At  606 , the gain is adjusted for amplifier  302  based on the difference determined at  602 . For example, the ratio of resistance between input resistance circuitry  604  and feedback resistance circuitry  602  is adjusted. In one example, a driver signal is adjusted based on the amount of gain determined at  604 . For example, depending on the resistance desired, the driver signal is used to control a number of switches. In one example, a number of resistors may be coupled in parallel. Switches are controlled to couple a number of resistors in parallel to achieve the desired resistance. The driver signal may include multiple paths to control the switches. At  608 , switches  505  are controlled based on the driver signal to adjust the gain of amplifier  302 . 
     Accordingly, particular embodiments provide a way to adjust the asymmetry of a signal with a variable gain amplifier  302 . The use of amplifier  302  provides higher bandwidth, lower distortion, and lower power. Also, particular embodiments may operate under a lower supply voltage condition. The lower power, lower distortion, and higher bandwidth may result because the correction is performed in amplifier  302  and external current sources or an external square wave generation circuit do not need to be used. Further, amplifier  302  may already be present in the read channel (it may have been used to amplify the signal but not correct the asymmetry). 
     As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. 
     The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims.