Abstract:
A display system ( 10 ) which includes a CRT feedback current simulating circuit ( 20 ) to simulate the cathode feedback current directly from the from the red, green and blue output biases of the video processor ( 13 ). Furthermore, the display system ( 10 ) applies blanking to the references pulses applied to the CRT output driving stage ( 16 ) so that the reference pulses will not be visible during a vertical underscanned condition. Shifting the generation of the cathode feedback current prior to the application of the blanking prevents any significant distortion, modification or skewing of the cathode feedback current sensed by the AKB sensing circuitry ( 19 ) of the video processor ( 13 ).

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to CRT or the like display systems, and more particularly to a display system having selectable automatic CRT cutoff stabilization or auto kinescope bias (AKB) with CRT feedback current simulation.  
         BACKGROUND OF THE INVENTION  
         [0002]    Automatic cathode ray tube (CRT) cutoff stabilization is conventionally achieved by inserting reference pulses near the video black level during the vertical blanking interval. In a closed loop manner, relative DC biases are varied to achieve equal CRT red, green and blue (RGB) cathode currents. Normally, there reference pulses are in the top overscanned part of the display and are not visible. However, in display modes in which the vertical deflection is underscanned, such as in the case where a 16:9 aspect ratio picture is displayed on a 4:3 display, these reference pulses become visible and distracting.  
           [0003]    Referring now to FIG. 1, a schematic diagram of a conventional display system  1  with auto kinescope bias (AKB) is shown. The display system  1  includes a video processor integrated circuit (IC)  3  which monitors the current feedback on line  2  feed to the current feedback input terminal  5  during reference pulse intervals and adjusts the red (R) output bias  4 R, the green (G) output bias  4 G, and the blue (B) output bias  4 B to maintain equal cathode currents. The display system  1  further includes a CRT output driving stage  6  having a plurality of CRT drive amplifiers  6   a ,  6   b ,  6   c  which are operational amplifiers. Each of the CRT drive amplifiers  6   a ,  6   b ,  6   c  have three outputs on lines  8   1 ,  8   2  and  8   3 . The output on line  8   1  of a respective CRT drive amplifier  6   a ,  6   b ,  6   c  drives a respective red, green and blue CRT&#39;s cathode RC, GC and BC and sink current. The output on line  8   2  of a respective CRT drive amplifier  6   a ,  6   b ,  6   c  supplies the cathode feedback current to the AKB sensing circuitry  9  of the video processor integrated circuit (IC)  3  on line  2 . The output on line  8   3  of a respective CRT drive amplifier  6   a ,  6   b ,  6   c  drives a respective one of the feedback resistors R 7 , R 8 , R 9 .  
           [0004]    The CRT drive amplifiers  6   a ,  6   b ,  6   c  each have a resistor or impedance R 4 , R 5  and R 6 , respectively, coupled to a first input terminal of a respective CRT drive amplifier  6   a ,  6   b ,  6   c . Moreover, feedback resistors R 7 , R 8  and R 9  are coupled to between the resistor or impedance R 4 , R 5  and R 6 , respectively, and the input terminal of its respective CRT drive amplifier  6   a ,  6   b ,  6   c . Furthermore, each of the CRT drive amplifiers  6   a ,  6   b ,  6   c  have a second input terminal which receives reference pulses near the video black level during the vertical blanking interval on line  7 .  
         SUMMARY OF THE INVENTION  
         [0005]    The present invention contemplates a display system which has a means for stabilizing the AKB closed loop in the absence of a CRT supplying the cathode feedback current and which applies blanking to prevent the reference pulses from being visible.  
           [0006]    The present invention further contemplates a display system which has a means for selectively defeating AKB or, in other words, not using AKB and substituting an alternative cathode feedback current source such as during a vertical underscanned condition. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1 illustrates a schematic diagram of a conventional display system.  
         [0008]    [0008]FIG. 2 illustrates a schematic diagram of a display system in accordance of the present invention.  
         [0009]    [0009]FIG. 3 illustrates an alternate embodiment of the schematic diagram of a display system in accordance of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0010]    Referring now to FIG. 2, the display system of the present invention is generally referenced by the numeral  10 . The display system  10  in general eliminates visible reference pulses when the vertical deflection is underscanned by (1) applying blanking (a vertical blanking signal) to prevent reference pulses from being visible; and (2) replacing the conventional cathode feedback current from the outputs of the CRT output driving stage  16  with a simulated cathode feedback current from a CRT feedback current simulation circuit  20  positioned prior to the application of the blanking or the CRT output driving stage  16 . The CRT feedback current simulation circuit  20  provides for the shifting of the cathode feedback current to a position prior the or the CRT output driving stage  6  so that a reference pulse/vertical blanking signal, on line  17 , can be applied to the CRT output driving stage  6  without significantly distorting, modifying or skewing the cathode feedback current. In the exemplary embodiment, the simulated cathode feedback current is simulated directly from the red (R) output bias  14 R, the green (G) output bias  14 G and the blue (B) output bias  14 B of the video processor integrated circuit (IC)  13 .  
         [0011]    The CRT feedback current simulation circuit  20  includes a current mirror  22 , a red transistor Q 1  having its base coupled to the red (R) output bias  14 R, a green transistor Q 2  having its base coupled to the green (G) output bias  14 G and a blue transistor Q 3  having its base coupled to the blue (B) output bias  14 B. The current mirror  22  includes transistors Q 4  and Q 5  having their bases coupled together and to the collector of transistor Q 4 . The emitters of transistors Q 4  and Q 5  are coupled to Vcc. The collectors of the red transistor Q 1 , the green transistor Q 2  and the blue transistor Q 3  are all coupled to the collector and base of transistor Q 4 . The emitters of the red transistor Q 1 , the green transistor Q 2  and the blue transistor Q 3  have coupled thereto a respective emitter resistor or impedance R 1 , R 2 , R 3  which are coupled to ground.  
         [0012]    The CRT feedback current simulation circuit  20  further includes current sinking transistor Q 10  having a collector tied to the collector of transistor Q 5  of the current mirror  22  at node A. At node A, a net current is communicated to the current feedback input terminal  15  of the video processor integrated circuit (IC)  13 . The base of transistor Q 10  is coupled to ground and the emitter has a resistor or impedance R 12  tied to voltage -Vee. As can be appreciated, the collector currents  15  and  110  of transistors Q 5  and Q 10  supply the net current to node A which defines the simulated cathode feedback current of the CRT feedback current simulation circuit  20 . The simulated cathode feedback current is communicated from node A to the current feedback input terminal  15  of the video processor integrated circuit (IC)  13  and is sensed by the AKB sensing circuitry  19 . It should be noted that AKB is also known or functions as CRT cutoff stabilization.  
         [0013]    In operation the collector currents transistors Q 1 , Q 2  and Q 3  produced by the sequential reference levels during vertical retrace, mirrored via transistors Q 4  and Q 5  of current mirror  22 , are each only slightly greater than the current sunk by the current sinking transistor Q 10 . By sinking current through transistor Q 10 , transistors Q 1 , Q 2  and Q 3  remain active at all times with relatively little change in their respective collector currents thereby, providing stable characteristics, especially for the Vbe (the base-emitter voltage, not shown). In other words, the output current from transistor Q 5  of the current mirror  22  is sunk by transistor Q 10 . Collector currents from transistors Q 5  and Q 10  are in the milli-Amp range. However, the current to the current feedback input terminal  15  is in the microAmp range. Thus, when transistor Q 5  is slightly greater than transistor Q 10 , the loop will stabilize which tends to minimize variations at the base-emitter junctions of the transistors Q 1 -Q 3 .  
         [0014]    As can be appreciated, simulating CRT “cut-on” with transistor turn-on would be much less predictable and stable. In the exemplary embodiment, the CRT “cut-on” voltage is approximately a +180.0 Volts from grid. However, as is well known, at a voltage of approximately +179.9 V some current is drawn causing CRT illumination. Reference pulses/vertical blanking signal is applied to the CRT drive amplifiers  16   a ,  16   b ,  16   c , on line  17 , to prevent the reference pulses from being visible on the display  35  and, especially, in display modes where the vertical deflection is underscanned.  
         [0015]    Referring still to the schematic diagram of display system  10  of FIG. 1, the output on line  18   1  of a respective CRT drive amplifier  16   a ,  16   b ,  16   c  drives a respective red, green and blue CRT&#39;s cathode RC, GC and BC and sink current of display  35 . The output on line  18   2  of a respective CRT drive amplifier  16   a ,  16   b ,  16   c  is coupled to ground. The output on line  18   3  of a respective CRT drive amplifier  16   a ,  16   b ,  16   c  drives a respective one of the feedback resistors R 7 , R 8 , R 9 .  
         [0016]    Referring now to FIG. 3, an alternate embodiment of the schematic diagram of a display system in accordance of the present invention is illustrated. The display system  100  includes selective switching circuitry  140  for selectively feeding a cathode feedback current from the CRT output driving stage  116  or a simulated cathode feedback current from the CRT feedback current simulation circuitry  120  to the current feedback input terminal  115  of the video processor integrated circuit (IC)  130 . Since the CRT feedback current simulation circuitry  120  is essentially the same as the CRT feedback current simulation circuitry  20  of FIG. 2, no further discussion will be provided except as related to the selective switching circuitry  140 .  
         [0017]    Referring now to the selective switching circuitry  140 , an AKB “on” or “off” signal is delivered on line  142  through resistor R 23  to the base of transistor Q 12  wherein an AKB “on” signal is substantially equal to 5V and the AKB “off” signal is substantially equal to 0V. The AKB “on” or “off” signal on line  142  is delivered to base transistor Q 11  via resistor R 14 . The AKB “on” or “off” signal on line  142  is also delivered to the base of transistor Q 13  on line  144  and the base of transistor Q 9  on line  146 . The base of transistor Q 11  is coupled to the base of transistor Q 8 . The emitters of transistors Q 11  and Q 12  are tied together at node B which receives the second output from the CRT drive amplifiers  116   a ,  116   b ,  116   c  on line  118   2 . The current on line  118   2  supplies the cathode feedback current to AKB sensing circuitry  119  via the current feedback input terminal  115 . The collector of transistor Q 12  is tied to -Vee.  
         [0018]    Transistors Q 8  and Q 9  have theirs emitters tied to node C which is coupled to the collector of transistor Q 5  of current mirror  122 . The collector of transistor Q 9  is coupled to the collector of transistor Q 10  and to node A. The collector of transistor Q 8  is tied to ground. The base of transistor Q 11  is coupled to the base of transistor Q 8  both of which are tied to Vcc, on line  152 , through resistor R 10  at node D. The emitter of transistor Q 13  is coupled to the emitter of transistor Q 10  at the first terminal of emitter resistor or impedance R 12 . The collector of transistor Q 13  is coupled to Vcc on line  150 . In this embodiment, the base of transistor Q 10  is coupled to resistor R 11  between the base of transistor Q 8  wherein resistor R 11  is in series with and between resistor R 10  and resistor R 13 . Resistor R 13  is coupled to ground.  
         [0019]    In operation, when the AKB “on” signal is present on line  142 , the CRT feedback current simulation circuitry  120  is selectively disabled and the collector of transistor Q 11  operates to deliver the cathode feedback current from CRT drive amplifiers  116   a ,  116   b ,  116   c  on line  1182  on feedback line  148  to the current feedback input terminal  115  of the video processor integrated circuit (IC)  130  and which is sensed by the AKB sensing circuitry  119 .  
         [0020]    On the other hand, when the AKB “off” signal is present on line  142 , the CRT feedback current simulation circuitry  120  is selectively enabled and the net collector currents from the transistor Q 5  via transistor Q 9  and transistor Q 10  at node A deliver a simulated cathode feedback current to the current feedback input terminal  115 .  
         [0021]    Transistor pair Q 11  and Q 12  and transistor pair Q 8  and Q 9  are alternately biased “on” and “off”. Thus, when the AKB “on” signal is present, transistor Q 11  is on, transistor Q 12  is off, transistor Q 8  is on, transistor Q 9  is off and transistor Q 13  turns transistor Q 10  off. Therefore, the only the resultant cathode feedback current at node B is communicated through node A via line  148  and to the current feedback input terminal  115 .  
         [0022]    However, when the AKB “off” signal is present, transistor Q 11  is off, transistor Q 12  is on, transistor Q 8  is off, and transistor Q 9  is on. Therefore, the simulated cathode feedback current at node A is the net collector current from the collectors of transistor Q 5  via transistor Q 9  and transistor Q 10  and is feed to the current feedback input terminal  115 .  
         [0023]    In this embodiment, the CRT feedback current simulation circuitry  120  only needs to be activated during an underscanned mode of operation such as, without limitation, when a 16:9 aspect ratio is displayed in a 4:3 display. Otherwise, during modes other than the underscanned mode, there is no reason to defeat the AKB with an alternate cathode feedback current source. Hence, an external switch (not shown) may be provided on the display  135  to supply the AKB “on”/“off” signal on line  142 .  
         [0024]    Referring still to the schematic diagram of the embodiment of FIG. 3, the output on line  118   1  of a respective CRT drive amplifier  116   a ,  116   b ,  116   c  drives a respective red, green and blue CRT&#39;s cathode RC, GC and BC and sink current of display  135 . The output on line  118   3  of a respective CRT drive amplifier  16   a ,  16   b ,  16   c  drives a respective one of the feedback resistors R 7 , R 8 , R 9 . The CRT drive amplifiers  116   a ,  116   b ,  116   c  each have a resistor or impedance R 4 , R 5  and R 6 , respectively, coupled to a first input terminal of a respective CRT drive amplifier  116   a ,  116   b ,  116   c . Moreover, feedback resistors R 7 , R 8  and R 9  are coupled to between the resistor or impedance R 4 , R 5  and R 6 , respectively, and the input terminal of its respective CRT drive amplifier  116   a ,  116   b ,  116   c . Furthermore, each of the CRT drive amplifiers  116   a ,  116   b ,  116   c  have a second input terminal which receives reference pulses/vertical blanking signal near the video black level during the vertical blanking interval on line  117 . It should be noted that the vertical blanking signal is applied on lines  17  and  117  only in the AKB off mode.  
         [0025]    Numerous modifications to and alternative embodiments of the present invention will be apparent to those skilled in the art in view of the foregoing description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. Details of the structure may be varied substantially without departing from the spirit of the invention and the exclusive use of all modifications which come within the scope of the appended claims is reserved.