Abstract:
A semiconductor integrated circuit has a 3-dimmensional interconnection line structure for high-speed operation. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a 3-dimmensional tournament tree shaped multilayer interconnection lines, wherein a single electric feeding point on a top surface of the MMIC is divided, layer by layer, into plural electrodes on the semiconductor substrate of the MMIC via a plurality of laminated interconnection layers and vertical interconnection layers therebetween shaped like a tournament tree.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor integrated circuit for high-speed operation, and more particularly, to three-dimensional interconnection wiring structure forming the semiconductor integrated circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    Monolithic Microwave Integrated Circuit (MMIC) for comprising high frequency devices such as a High Electron Mobility Transistor (HEMT) or a Hetero-junction Bipolar Transistor (HBT), unlike a conventional silicon integrated circuit, needs high frequency wave guides for its interconnection lines. A microstrip line has been conventionally used for high frequency interconnection lines because it has stable wiring characteristics and low dispersion characteristics which means that frequency dependence of propagation constant is weak. FIG. 1 is a cross-sectional view of a high frequency wave-guide for a 3-dimensional MMIC of prior art, particularly using multilayer microstrip lines. As shown in FIG. 1, the multilayer MMIC of prior art has a grounded plate  3  on a surface insulating layer  2  formed on the surface of a semiconductor substrate, and the grounded plate  3  is coupled with each of interconnection layers  5  formed on the respective insulating layers  4  to form the respective microstrip lines. The multilayer MMIC of prior art has an advantage in high-density integration over a usual MMIC having interconnection lines laid out on a single plane. However, signal propagation time in the high frequency interconnection lines depends significantly upon not only effective length of interconnection layers but also geometrical relationship with each other, particularly between the interconnection layers and the grounded plate. Therefore, it is not easy to feed an identical signal from a single node to plural nodes with identical timing. Nevertheless, there has been no report on multilayer interconnection lines for high frequency signals in consideration for signal timing. Additionally, it is not allowed that any conductive layer is laid out between the grounded plate and a microstrip line coupled therewith, which considerably restricts freedom of circuit layout design for high-density integration.  
         SUMMARY OF THE INVENTION  
         [0005]    Accordingly, it is an object of this invention to provide an MMIC having a 3-dimmensional tournament tree shaped multilayer interconnection lines, whereby a single electric signal on the uppermost interconnection layer can be fed to plural electrodes on the lowest interconnection layer with identical timing.  
           [0006]    It is a further object of this invention to provide a 3-dimmensional MMIC having a smaller chip area with the same design rule and higher speed operation than prior art, in which electric feeding lines are allowed to overlap other interconnection layers.  
           [0007]    In accordance with the stated objects, one aspect of the present invention is a multilayer interconnection structure for a 3-dimmensional MMIC, in which a semiconductor device for high frequency operation comprises a semiconductor substrate having an insulating layer on the surface thereof, a grounded plate formed on the semiconductor substrate connecting to a ground potential, a plurality of laminated interconnection layers formed on the grounded plate, the plurality of laminated interconnection layers being insulated from each other and also the grounded plate by insulating layers therebetween, and a vertical interconnection layer for connecting each immediately opposed upper and lower pair of the plurality of laminated interconnection layers in a through-hole penetrating the corresponding one of the insulating layers therebetween, the vertical interconnection layer being disposed at an electric center point of each of the plurality of laminated interconnection layers on a first surface of the corresponding one of the plurality of laminated interconnection layers, and at each end of the corresponding one of the plurality of laminated interconnection layers on a second surface of the corresponding one of the plurality of laminated interconnection layers opposing to the first surface. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    The present invention will be more apparent from the following description, when taken to conjunction with the accompanying drawings, in which:  
         [0009]    [0009]FIG. 1 is a cross-sectional view of a high frequency wave-guide for a 3-dimensional MMIC of prior art.  
         [0010]    [0010]FIG. 2 is a cross-sectional view of a high frequency wave-guide for a 3-dimensional MMIC for the first embodiment according to the present invention.  
         [0011]    [0011]FIG. 3 is a see-through plan view of a 3-dimensional MMIC for the second embodiment according to the present invention.  
         [0012]    [0012]FIG. 4 is a cross-sectional view of the 3-dimensional MMIC along A-A′ line shown in FIG. 3.  
         [0013]    [0013]FIG. 5 is a cross-sectional view of the 3-dimensional MMIC along B-B′ line shown in FIG. 3. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0014]    Embodiment 1  
         [0015]    [0015]FIG. 2 is a cross-sectional view of a high frequency wave-guide for a 3-dimensional MMIC for the first embodiment according to the present invention.  
         [0016]    Referring to FIG. 2, each of the interconnection layers  5  is formed on the corresponding insulating layer  4  by dividing them thereon, layer by layer, from the upper layer to the lower layer, in which the upper layer is connected to the lower layer via a vertical interconnection layer  6  at an electrical center point of the lower interconnection layer  5  in a tournament tree shape. According to this multilayer structure of the present invention, an electric signal inputted in the uppermost interconnection layer  5  can be fed to each of the active regions  1   a  (four regions in FIG. 2) in the semiconductor substrate in identical timing. If the interconnection layer is laid out on a single plane shaped like a tournament tree written on a sheet of paper in which each branch of the interconnection layer has identical length, it is necessary to form a straight and long vertical interconnection layer from each end point of the interconnection layers on the uppermost surface to the corresponding active region on the deepest surface by penetrating all of the insulating layers therebetween in order to feed a single electric signal to each of the active regions in identical timing. However, since numbers of insulating layers increases based on increasing of device functions in a recent 3-dimmensional MMIC, it takes a lot of etching-time to form long through-holes penetrating many numbers of insulating layers, and further, it is also very difficult to plug metal in the long through-holes uniformly without voids. In contrast, in the present invention, even if the number of the insulating layers increases, each of the through-holes does not increase in depth because the interconnection layers are divided in the depth direction. Needless to say, in the present invention, a long through-hole penetrating many numbers of insulating layers can be formed by connecting short through-holes layer by layer.  
         [0017]    Embodiment 2  
         [0018]    [0018]FIG. 3 is a see-through plan view of a 3-dimensional MMIC for the second embodiment according to the present invention.  
         [0019]    [0019]FIG. 4 is a cross-sectional view of the 3-dimensional MMIC along A-A′ line shown in FIG. 3.  
         [0020]    [0020]FIG. 5 is a cross-sectional view of the 3-dimensional MMIC along B-B′ line shown in FIG. 3.  
         [0021]    In this embodiment, as shown in FIG. 4, an electric signal or power is provided from the first interconnection layer  51  on the uppermost layer to each of active regions of an FET through the second interconnection layer  52  on the lower layer and the third interconnection layer  53  on the further lower layer. The insulating layer is made of resin insulating layer having low dielectric constant such as polyimide or benzocyclobutane (BCB). The surface insulating layer  2  on the semiconductor substrate  1  is made of a stable insulating layer such as silicon nitride. Since length of the interconnection layers is identical with each other by forming each of the through-holes  6  in the corresponding electrical center points of the second and third interconnection layers, it can be possible to provide a signal to each of the active regions  1   a  in the same timing.  
         [0022]    As shown in FIG. 3, the laminated interconnection layers are laid out in perpendicular to each other between the upper layer and the lower layer directly opposing to the upper layer. As shown in FIG. 4, the second interconnection layer  52  connected to the first interconnection layer  51  is connected to the third interconnection layer  53  by the vertical interconnection layer  6  formed at both ends of the second interconnection layer  52 . As shown in FIG. 5, the third interconnection layer  53  is connected to each of the active regions  1   a  at both ends of the third interconnection layer  53 . Additionally, since the grounded plate  3  is exposed to the through-holes, a through-hole insulating layer  6   a  is formed on each inside-wall of the through-holes. Another important advantage of these embodiments other than to feed a signal to each of the active regions in identical timing is that the first, second and third interconnection layers are overlapped to each other only at each point of the through-holes. To form the microstrip lines in a 3-dimmensional MMIC of prior art, it is desirable that each of the horizontal interconnection layers vertically opposes the corresponding grounded plate  3 , and that no other conductors are disposed between them. In comparison with the prior art, it is obvious that the embodiments on the present invention have better signal propagation characteristics because overlapping occurs only at each of the through-holes.  
         [0023]    Although only the foregoing embodiments of the present invention have been disclosed on a typical electric feeding line structure, it will be obvious to those having ordinary skill in the art, that changes and modifications may be made thereto without departing from the spirit and the scope of the invention as hereinafter claimed. For instance, timing signals of the present invention can be favorable to a power field effect transistor (FET). Since the power FET usually has many parallel structures including gate, source and drain electrodes, it is important to provide input or output signals to these parallel electrodes at the same timing for parallel operation. Thus, the parallel operation is facilitated by applying the present invention to these parallel electrodes for gate, source and drain. Although the disclosed embodiments illustrate the interconnection lines divided layer by layer from upper to lower layers, it is also possible that the interconnection lines are divided layer by layer from lower to upper layers in the reverse direction, by which plural electronic potentials can be supplied consolidatedly to a single active region (or an electronic potential can be divided from the single active region to the plural interconnection lines). Needless to say, the present invention can apply to not only the active region of an active device such as the semiconductor device but also passive devices such as a capacitive, inductive or resistive device. Furthermore, those passive devices can be formed by conductors between insulating layers as well as on a semiconductor substrate.