Abstract:
Embodiments relate to a current cell circuit in a digital-analog converter. According to embodiments, a current cell circuit in a digital-analog converter may include a current source connected to a power voltage terminal to generate current having a predetermined magnitude, a first current switch transferring current provided from the current source to a first output terminal, a first current generator detecting output voltage from the first output terminal and generating the amount of reduced current from the detected voltage, and a first current supplier supplying the amount of current generated from the first current generator to the first current switch. According to embodiments, current variations at a constant output voltage may be minimized. This may make it possible to obtain more stable frequency characteristics.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2007-0138896 (filed on Dec. 27, 2007), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    A digital-analog converter (DAC) may convert a digital signal into an analog signal. A DAC may be manufactured using various devices such as a resistor, a capacitor, a current source and the like. A DAC that may be manufactured as described above may have various advantages and disadvantages with respect to conversion speed, resolution, power consumption, and the like according to devices used and structures. 
         [0003]    Among digital-analog converters having various structures, a current driving type digital-analog converter may be a suitable structure for high-speed and high-resolution signal conversion. Many digital-analog converters of high-speed and high-resolution apparatuses may be designed as a current driving type DAC. 
         [0004]    Recent developments of digital signal processing techniques may include a signal processing method to process parts. According to the related art, analog signals in the related art may be processed with digital signals. Processing results may be converted again into analog signals. An amount of processing data in various wire/wireless communication systems to which such a signal processing method may be applied may be increasing. Hence, an amount of data that may require digital signals to be converted into analog signals may be increasing. Accordingly, there may be an increased demand for a digital-analog converter with improved performance, and with high-speed and high-resolution characteristics, compared to the related art. 
         [0005]    In addition, an amount of data processing in various wire/wireless communication systems that may have wide band characteristics and signals that may occupy a wide band may be increasing. Hence, there may be a demand for a digital-analog converter (DAC) having high operation characteristics to process signals occupying a wide band. 
         [0006]    Communication systems and high speed image signal processing systems may be developed and implemented as a system on chip (SOC). Therefore, a utility value of a DAC may become more important as intellectual property (IP). 
         [0007]      FIG. 1  illustrates a current cell circuit in a related art digital-analog converter. Referring to  FIG. 1 , a current cell circuit in a DAC may transfer current provided from current source M 0  according to signals output from a decoder that may receive N-bit digital data and driver into output terminals IOUTN and IOUTP. 
         [0008]    A current cell circuit in a DAC may include first PMOS transistor M 0 , which may have a source connected to power voltage terminal VDD, and which may operate as a current source to generate current having a predetermined magnitude. A current cell circuit may also include second PMOS transistor M 1 , which may have a source connected to a drain of first PMOS transistor M 1  via node VS, and may operate as a current switch to transfer current provided from first PMOS transistor M 1  to first output terminal IOUTN. Third PMOS transistor M 2  may also be provided, and may have a source connected to a drain of first PMOS transistor M 1  via node VS, and may operate as a current switch to transfer current provided from first PMOS transistor M 1  to second output terminal IOUTP. 
         [0009]    A gate of second PMOS transistor M 1  and a gate of third PMOS transistor M 2  may be connected to first switch terminal SW 1  and second switch terminal SW 2 , respectively. If output voltage from first output terminal IOUTN and second output terminal IOUTP is raised, first PMOS transistor M 0 , which may be a current source, may enter a linear area from a saturation area. In this case, a current value flowing in first PMOS transistor M 0  may change when output voltage values from first output terminal IOUTN and second output terminal IOUTP reach a preset voltage value. 
         [0010]    If a current value of first PMOS transistor M 0  changes, unit current may be mismatched, which may cause differences in output voltage values for input codes. Accordingly, an integral non-linearity (INL) value may have a value more than several least significant bit (LSB) values. 
         [0011]    As a digital-analog converter has a wider output range, various systems may be designed more easily. This may increase a demand for a wider IP output range of a digital-analog converter. However, as shown in  FIG. 1 , in a related art current cell circuit, differences in output voltage for input codes may occur. This may reduce an amount of current from a current source. 
       SUMMARY 
       [0012]    Embodiments relate to a digital-analog converter (DAC). Embodiments relate to a current cell circuit in a digital-analog converter and a method of providing current from a current cell circuit in a digital-analog converter. 
         [0013]    Embodiments relate to a current cell circuit in a digital-analog converter that may widen a range of output voltage by converting voltage detected from a current cell circuit into current. This may compensate for an amount of current reduced as output voltage increases, so that current variations may be minimized at a predetermined output voltage. 
         [0014]    According to embodiments, a current cell circuit in a digital-analog converter may include at least one of the following. A current source connected to a power voltage terminal to generate current having a predetermined magnitude. A first current switch transferring current provided from the current source to a first output terminal. A first current generator to detect output voltage from the first output terminal and generate the amount of reduced current from the detected voltage. A first current supplier to supply the amount of current generated from the first current generator to the first current switch. 
     
    
     
       DRAWINGS 
         [0015]      FIG. 1  is a drawing illustrating a current cell circuit in a related art digital-analog converter (DAC). 
           [0016]    Example  FIG. 2  is a circuit view of a current cell circuit in a digital-analog converter according to embodiments. 
           [0017]    Example  FIG. 3  is a graph comparing characteristics of a current cell circuit according to embodiments with characteristics of a related art current cell circuit. 
           [0018]    Example  FIGS. 4 and 5  are graphs showing performance measurement results of a digital-analog converter using a current cell circuit, according to embodiments. 
       
    
    
     DESCRIPTION 
       [0019]    Example  FIG. 2  is a circuit view of a current cell circuit in a digital-analog converter according to embodiments. Referring to example  FIG. 2 , a current cell circuit in a digital-analog converter (DAC) may transfer current provided from current source M 0  in accordance with signals output from driver and a decoder that may receive N-bit digital data to output terminals IOUTN and IOUTP. 
         [0020]    According to embodiments, a current cell circuit in a DAC may also include four PMOS transistors M 4 , M 5 , M 7  and M 8  and two NMOS transistors M 3  and M 6 . A current cell circuit may also include first PMOS transistor M 0 , second PMOS transistor M 1 , and third PMOS transistor M 2 . 
         [0021]    According to embodiments, first PMOS transistor M 0 , which may have a source connected to power voltage terminal VDD, may operate as a current source to generate current having a predetermined magnitude. According to embodiments, second PMOS transistor M 1  may have a source connected to receive current provided from first PMOS transistor M 0  and a drain connected to first output terminal IOUTN. According to embodiments, second PMOS transistor M 1 , whose source may be connected to a drain of first PMOS transistor M 0  through node VS, may operate as a current switch, and may transfer current provided from first PMOS transistor M 0  to first output terminal IOUTN. 
         [0022]    According to embodiments, third PMOS transistor M 2  may have a source connected to receive current provided from first PMOS transistor M 0  and a drain connected to second output terminal IOUTP. According to embodiments, third PMOS transistor M 2 , whose source may be connected to a drain of first PMOS transistor M 0  through node VS, may operate as a current switch, and may transfer a current provided from first PMOS transistor M 0  to second output terminal IOUTP. 
         [0023]    According to embodiments, first NMOS transistor M 3  may have a gate connected to a drain of third PMOS transistor M 2  and second output terminal IOUPT in parallel, and a source connected to ground terminal GND. According to embodiments, first NMOS transistor M 3  may detect output voltage from second output terminal IOUTP and may generate an amount of reduced current from the detected voltage. According to embodiments, first NMOS transistor M 3  may operate as a current generator. 
         [0024]    According to embodiments, fourth PMOS transistor M 4  may have a source connected to power voltage terminal VDD, and a drain and a gate connected to a drain of first NMOS transistor M 3 . Fifth PMOS transistor M 5  may have a source connected to power voltage terminal VDD, a gate connected to a gate of fourth PMOS transistor M 4 , and a drain connected to node VS. 
         [0025]    According to embodiments, fourth PMOS transistor M 4  and fifth PMOS transistor M 5  may supply an amount of current generated from first NMOS transistor M 3  to third PMOS transistor M 2 . According to embodiments, fourth PMOS transistor M 4  and fifth PMOS transistor M 5  may be current generators. 
         [0026]    According to embodiments, second NMOS transistor M 6  may have a gate connected to a drain of second PMOS transistor M 1  and first output terminal IOUPN in parallel, and a source connected to a ground terminal GND. Second NMOS transistor M 6  may detect output voltage from first output terminal IOUTN and may generate an amount of reduced current from a detected voltage. According to embodiments, second NMOS transistor M 6  may operate as a current generator. 
         [0027]    According to embodiments, sixth PMOS transistor M 7  may have a source connected to power voltage terminal VDD, and a drain and a gate connected to a drain of second NMOS transistor M 6 . According to embodiments, seventh PMOS transistor M 8  may have a source connected to power voltage terminal VDD, a gate connected to a gate of sixth PMOS transistor M 7 , and a drain connected to node VS. 
         [0028]    According to embodiments, sixth PMOS transistor M 7  and seventh PMOS transistor M 8  may supply an amount of current generated from second NMOS transistor M 6  to second PMOS transistor M 1 . According to embodiments, sixth PMOS transistor M 7  and seventh PMOS transistor M 8  may be current generators. 
         [0029]    According to embodiments, as output voltage of output terminals IOUTN and IOUTP rise, voltage of node VS may also rise. Owing to such a phenomenon, a voltage difference between a source and drain of first PMOS transistor M 0 , which may be a current source, may decrease. According to embodiments, an amount of unit current generated from first PMOS transistor M 0  may decrease. 
         [0030]    According to embodiments, in a current cell circuit in a digital-analog converter an output voltage from output terminals IOUTN and IOUTP may be detected, respectively, through first NMOS transistor M 3  and second NMOS transistor M 6 . An amount of reduced current from a detected voltage may be generated. An amount of current generated from first NMOS transistor M 3  may be supplied to third PMOS transistor M 2  through fourth PMOS transistor M 4  and fifth PMOS transistor M 5 . An amount of current generated from second NMOS transistor M 6  may be supplied to second PMOS transistor M 1  through sixth PMOS transistor M 7  and seventh PMOS transistor M 8 . 
         [0031]    Example  FIG. 3  is a graph comparing characteristics of a current cell circuit, according to embodiments, with characteristics of a related art current cell circuit. A horizontal axis may represent voltage of an output terminal and a vertical axis may represent current of a third PMOS transistor M 2 . A solid line may represent a related art technique and a dotted line may represent embodiments. 
         [0032]    Referring to example  FIG. 3 , if voltage IOUTP from an output terminal reaches 1.6V, a related art current cell circuit may have large current variations. A current cell according to embodiments may have a substantially constant output current, even though a voltage IOUTP from an output terminal reaches 1.6V. 
         [0033]    Example  FIGS. 4 and 5  are graphs showing performance measurement results of a digital-analog converter using a current cell circuit according to embodiments. In the graphs shown in example  FIGS. 4 and 5 , a horizontal axis may represent an input code and a vertical axis may represent LSB, respectively. In example  FIG. 4 , reference numeral  10  may represent a performance of a related art digital-analog converter, and reference numeral  20  may represent a performance of a digital-analog converter using a current cell circuit according to embodiments. Example  FIG. 5  shows only performance measurement results of a digital-analog converter using a current cell circuit according to embodiments. 
         [0034]    Referring to example  FIG. 4 , integral non-linearity (INL) characteristics of a current cell circuit in a digital-analog converter according to embodiments may be improved more than doubled as compared to a related art current cell circuit. Differential Non-Linearity (DNL) characteristics of a current cell circuit in a digital-analog converter according to embodiments may be substantially the same as compared to a related art current cell circuit, as shown in example  FIG. 5 . 
         [0035]    Table 1 exemplifies simulation results for a current cell circuit in a digital-analog converter according to embodiments. 
         [0000]    
       
         
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
             
             
               
                   
                 INL 
                 +/−1 
                 LSB 
               
               
                   
                 DNL 
                 +/−0.3 
                 LSB 
               
               
                   
                 SNR (at, fin = 2.34M, fs = 100M) 
                 53.02 
                 dB 
               
               
                   
                 SFDR (at, fin = 2.34M, fs = 100M) 
                 53.88 
                 dB 
               
               
                   
                 Output Swing 
                 −1.6~1.6 
                 V 
               
               
                   
                 Resolution 
                 10 
                 bit 
               
               
                   
                 VDD 
                 3.3 
                 V 
               
               
                   
                   
               
             
          
         
       
     
         [0036]    According to embodiments, SFDR may represent a spurious-free dynamic range and SNR may represent a signal to noise ratio. According to embodiments, a current cell circuit in the digital-analog converter may be applied, for example, to a digital-analog converter with a 10 bit 100 Msps and a 0.13 μm spice model is used as an application device. 
         [0037]    Referring to Table 1, through simulation results, a current cell circuit may have power voltage VDD of 3.3V, and may have a wide swing structure with output voltage ranging from approximately −1.6V to 1.6V, INL of +/−1 LSB, and DNL of +/−0.3 LSB. 
         [0038]    Also, if an input frequency fin is 2.3 MHz and a sampling frequency fs is 100 MHz, a spurious-free dynamic range (SFDR) may be approximately 53.88 dB and a signal to noise ratio (SNR) may be approximately 53.07 dB. 
         [0039]    According to embodiments, if a current cell circuit in a digital-analog converter is used, L values (length of first PMOS transistor M 0  in example  FIG. 2 ) of a current source within a current cell may be increased, which may result in better frequency characteristics. 
         [0040]    A current cell circuit in a digital-analog converter according to embodiments may minimize current variations at a constant output voltage. This may provide more stable frequency characteristics. 
         [0041]    It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.