Abstract:
A system and method for processing a wafer includes a charge neutralization system. The wafer processing system includes a wafer measuring device that can measure characteristics of a surface of the semiconductor wafer. One or more wafer processing stations perform a chemical mechanical polish (CMP) process on the wafer surface. A desica cleaning station can clean and dry the semiconductor wafer. The wafer processing system further includes a charge neutralizing device that can alter a surface charge of the wafer surface.

Description:
TECHNICAL FIELD 
     The disclosure relates generally to semiconductor substrates and more particularly to a system and method for cleaning a charging wafer surface. 
     BACKGROUND 
     Chemical Mechanical Polishing (CMP) is wet process used in semiconductor manufacturing processes. CMP is a process that uses an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring. 
     Wafer charging is a well known production yield detractor. Wafer charging can cause a circuit shortage and induce defects. For example, recently it has been found that, for 32 nm Mx levels, an increasing trend of dendrite defects is present. 
     SUMMARY 
     Embodiments of the present disclosure provide a wafer processing system capable of cleaning a surface of a semiconductor wafer. The wafer processing system includes a wafer measuring device that can measure characteristics of a surface of the semiconductor wafer. The wafer processing system also includes at least one wafer processing station configured to clean and/or polish the wafer surface. In addition, the wafer processing system includes a charge neutralizing device that can alter a surface charge of the wafer surface. 
     Embodiments of the present disclosure also provide a Chemical Mechanical Planarization (CMP) system capable of cleaning a surface of a semiconductor wafer. The CMP system includes a wafer measuring device that can measure characteristics of a surface of the semiconductor wafer. The CMP also includes at least one wafer processing station that can perform a CMP process on the wafer surface and a desica cleaning station that can clean and dry the semiconductor wafer. The CMP system further includes a charge neutralizing device that can alter a surface charge of the wafer surface. 
     Now Embodiments of the present disclosure provide a method for cleaning a surface of a semiconductor wafer. The method includes measuring at least one characteristic of a surface of the semiconductor wafer. The method also includes processing the wafer surface and neutralizing a surface charge of the wafer surface. 
     Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of this disclosure and its features, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which: 
         FIGS. 1A through 1P  illustrate surface charges before and after CMP according to this disclosure; 
         FIG. 2  illustrates an integration wafer according to the present disclosure; 
         FIG. 3  illustrates a CMP system according to the present disclosure; 
         FIG. 4  illustrates a pulsed DC ionizing bar according to embodiments of the present disclosure; 
         FIG. 5  illustrates a CMP system including a charge neutralizer according to embodiments of the present disclosure; and 
         FIGS. 6 through 9  illustrate processes for charge neutralization according to embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1 through 9 , discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system. 
       FIGS. 1A through 1P  illustrate surface charges before and after CMP according to this disclosure. Each of  FIGS. 1A through 1P  illustrates surface charging before and after the CMP process for various metal and insulator films. 
     For example,  FIG. 1A  illustrates a Tantalum Nitride (TaN) film surface charge before  100  and after  102  a Platen  2  (P 2 ) CMP. The surface charge varies from 0.07 before CMP to −0.02 after CMP. 
       FIG. 1B  illustrates a TaN film surface charge before  104  and after  106  a Platen  3  (P 3 ) CMP. The surface charge varies from −0.12 before CMP to −0.16 after CMP. 
       FIG. 1C  illustrates a Copper (Cu) Seed film surface charge before  108  and after  110  a P 2  CMP. The surface charge varies from −0.40 before CMP to −0.44 after CMP. 
       FIG. 1D  illustrates a Cu Seed film surface charge before  112  and after  114  the P 3  CMP. The surface charge varies from −0.36 before CMP to −0.44 after CMP. 
       FIG. 1E  illustrates a Cu Plate film surface charge before  116  and after  118  the P 2  CMP. The surface charge varies from −0.32 before CMP to −0.39 after CMP. 
       FIG. 1F  illustrates a Cu Plate film surface charge before  120  and after  122  the P 3  CMP. The surface charge varies from −0.32 before CMP to −0.39 after CMP. 
       FIG. 1G  illustrates an octomethylcyclotetra-cyloxane (OMCATS) (e.g., a lower K insulated material) CAP film surface charge before  124  and after  126  the P 2  CMP. The surface charge varies from 0.74 before CMP to 0.53 after CMP. 
       FIG. 1H  illustrates an OMCATS CAP film surface charge before  128  and after  130  the P 3  CMP. The surface charge varies from 0.70 before CMP to 0.52 after CMP. 
       FIG. 1I  illustrates a Tetraethyl orthosilicate (TEOS) film surface charge before  132  and after  134  the P 2  CMP. The surface charge varies from 0.30 before CMP to 0.26 after CMP. 
       FIG. 1J  illustrates a TEOS film surface charge before  136  and after  138  the P 3  CMP. The surface charge varies from 0.34 before CMP to 0.32 after CMP. 
       FIG. 1K  illustrates a Low Temp Oxidation (LTO) film surface charge before  140  and after  142  the P 2  CMP. The surface charge varies from 0.38 before CMP to 0.58 after CMP. 
       FIG. 1L  illustrates an LTO film surface charge before  144  and after  146  the P 3  CMP. The surface charge varies from 0.74 before CMP to 0.64 after CMP. 
       FIG. 1M  illustrates an OMCATS Inverse Lithography Technology (ILT) film surface charge before  148  and after  150  the P 2  CMP. The surface charge varies from 0.47 before CMP to 0.30 after CMP. 
       FIG. 1N  illustrates an OMCATS ILT film surface charge before  152  and after  154  the P 3  CMP. The surface charge varies from 0.40 before CMP to 0.11 after CMP. 
       FIG. 1-O  illustrates a ULK film surface charge before  156  and after  158  the P 2  CMP. The surface charge varies from 0.26 before CMP to 0.25 after CMP. 
       FIG. 1P  illustrates a ULK film surface charge before  160  and after  162  the P 3  CMP. The surface charge varies from 0.64 before CMP to 0.28 after CMP. 
     As shown in  FIGS. 1A through 1P , the film surfaces exhibit memory effects, especially for the charge peak region where charging is most likely to occur. Ionizing of the surface can effectively smooth the charge peak areas and inhibit charging to occur. 
       FIG. 2  illustrates an integration wafer  200  according to the present disclosure. The integrated wafer  200  includes a P+ region  205  and an N+ region  210 . The wet-chemical surface creates a galvanic cell where copper lines  215  on the P+ region  205  behave as an anode and copper lines  220  on the N+ region  210  behave as a cathode. As a result, a surface charge of Cu ions can be easily formed. Dendrite defects can be generated in critical and reproducible conditions. 
       FIG. 3  illustrates a CMP system  300  according to the present disclosure. The embodiment of the CMP system  300  shown in  FIG. 3  is for illustration only. Other CMP system embodiments could be used without departing from the scope of this disclosure. 
     The CMP system  300  includes three Platens, Platen  1  (P 1 )  305 , Platen  2  (P 2 )  310  and Platen  3  (P 3 )  315 . An inline metrology device  320  measures the surface characteristics of a wafer. Then, the wafer is processed through P 1   305 , P 2   310  and P 3   315 . For example, P 1   305  can be set for bulk (that is, full) Cu polish. P 2   310  can be set as a copper clearing pattern, that is, to clear the copper. P 3   315  can be configured for barrier clear and dielectric stopping. After the CMP processes, the wafer can be dried in a post CMP cleaner  325 , such as a Desica®. The post CMP cleaner  325  can include a megasonic (Meg) cleaner stage  330 , a dual brush clean stage  335  (such as brush  1  and brush  2  clean stages), and a dryer stage  340 . 
       FIG. 4  illustrates a pulsed DC ionizing bar  400  according to embodiments of the present disclosure. The embodiment of the pulsed DC ionizing bar  400  shown in  FIG. 4  is for illustration only. Other embodiments could be used without departing from the scope of this disclosure. 
     The pulsed DC ionizing bar  400  includes a charge core  405 . The pulsed DC ionizing bar  400  also includes a plurality of dedicated positive emitter pins  410  and a plurality of dedicated negative emitter pins  415 . The plurality of dedicated positive emitter pins  410  and plurality of dedicated negative emitter pins  415  can be separated by an insulated separator  420 . The separator  410  is configured to inhibit the flow of ions from the between the positive emitter pins  410  and negative emitter pins  415 . 
     The pulsed DC ionizing bar  400  produces positive and negative ions. The ions are ejected onto the wafer surface  450  when the wafer passes through an ejection way in a charge neutralization zone. The ejection way is the area in the charge neutralization zone wherein the wafer is placed for charge neutralization processing by the pulsed DC ionizing bar  400  (discussed below with respect to  FIG. 5 ). The positive ions are ejected though the plurality of positive emitter pins  410  and the negative ions are ejected through the plurality of negative emitter pins  415 . 
     When the wafer surface  450  is positively charged, the positive ions ejected from the positive emitter pins  410  will not attach to the wafer surface  450  due to electrical repulsion. However, the negative ions ejected from the negative emitter pins  415  will attach to the wafer surface  450  as a result of the electrical attractive force. The attaching of the negative ions to the positively charged wafer surface  450  neutralizes the wafer surface  450 . Any remaining neutralized residuals can be washed away during a normal wet clean procedure. 
     Additionally, when the wafer surface  450  is negatively charged, the negative ions ejected from the positive emitter pins  415  will not attach to the wafer surface  450  due to electrical repulsion. However, the positive ions ejected from the positive emitter pins  410  will attach to the wafer surface  450  as a result of the electrical attractive force. The attaching of the positive ions to the negatively charged wafer surface  450  also neutralizes the wafer surface  450 . Any remaining neutralized residuals can be washed away during a normal wet clean procedure. 
     In some embodiments, the ion ratios from the pulsed DC ionizing bar  400  can be adjusted to vary the charge on the wafer surface charge. For example, the wafer surface charging can be changed to neutral, negative or positive by adjusting the positive to negative ion ratios that are ejected from the pulsed DC ionizing bar  400 . 
       FIG. 5  illustrates a CMP system including a charge neutralizer according to embodiments of the present disclosure. The embodiment of the CMP system  500  shown in  FIG. 5  is for illustration only. Other embodiments of the CMP system  500  could be used without departing from the scope of this disclosure. 
     The CMP system  500  includes three Platens, Platen  1  (P 1 )  505 , Platen  2  (P 2 )  510  and Platen  3  (P 3 )  515 . An inline metrology device  520  measures the surface characteristics of a wafer. The CMP system  500  includes a cleaning/drying stage, such as a Desica cleaner  525 . The Desica cleaner  525  can include a metrosonic (Meg) cleaner stage  530 , a brush clean stage  535  (such as brush  1  and brush  2  clean stages), and a dryer stage  540 . In addition, the CMP system  500  includes a charged neutralizer  545 . The charge neutralizer can be any ionizing source, such as a pulsed DC ionizing bar  400 . The charged neutralizer  545  is disposed in a charge neutralizing zone  550 . 
     The charge neutralizing zone  550  can be disposed within the CMP system  500  in relationship to the platens  505 - 515  and Desica cleaner  525 . For example, the charge neutralizing zone  550  can be disposed between the platens  505 - 515  and Desica cleaner  525  such that charge neutralization can occur prior to or after the CMP process. In some embodiments, the charged neutralizer  545  can be disposed prior to the Meg clean stage  530 . In some embodiments, the charged neutralizer  545  can be disposed prior to the brush clean stage  535 . In some embodiments, the charged neutralizer  545  can be disposed prior to the dryer stage  540 . 
     The wafer is processed through one or more wafer processing stations, such as P 1   505 , P 2   510  and P 3   515 . For example, P 1   505  can be set for bulk (that is, full) Cu polish. P 2   510  can be set as a copper clearing pattern, that is, to clear the copper. P 3   515  can be configured for barrier clear and dielectric stopping. After the CMP processes, the wafer can be dried in a Desica cleaner  525 . After the CMP processing, the wafer undergoes charge neutralization. The wafer is placed in the ejection way of the charged neutralizer  545  prior to or during the cleaning/drying stage. For example, the wafer can be placed in the ejection way of the charge neutralizer prior to being placed in the Meg clean stage  530 , or prior to being placed the brush clean stage  535 , or prior to being placed the dryer stage  540 , or any combination thereof. 
     In additional and alternative embodiments, the charged neutralizer  545  can be disposed such that charge neutralization is performed after measurement by the inline metrology  520 . Then, the wafer is processed through P 1   505 , P 2   510  and P 3   515 . For example, P 1   505  can be set for bulk (that is, full) Cu polish. P 2   510  can be set as a copper clearing pattern, that is, to clear the copper. P 3   515  can be configured for barrier clear and dielectric stopping. After the CMP processes, the wafer can be dried in a Desica cleaner  525  The Desica cleaner  525  can include a metrosonic cleaner stage  530 , a brush clean stage  535  (such as brush  1  and brush  2  clean stages), and a dryer stage  540 . In some embodiments, the wafer undergoes a second charge neutralization after CMP processing. For example, the wafer can be placed in the ejection way of the charged neutralizer  545  prior to being placed in the Meg clean stage  530 . In some embodiments, the wafer can be placed in the ejection way of the charged neutralizer  545  prior to being placed the brush clean stage  535 . In some embodiments, the wafer can be placed in the ejection way of the charged neutralizer  545  prior to being placed the dryer stage  540 . 
       FIGS. 6 through 9  illustrate processes for charge neutralization according to embodiments of the present disclosure. The embodiment of processes  600 ,  700 ,  800  and  900  shown in  FIGS. 6-9  are for illustration only. Other embodiments could be used without departing from the scope of this disclosure. 
     In block  605 , the surface characteristics of a wafer are measured. The surface characteristics can be measured by an inline metrology device. Thereafter, the wafer can undergo CMP processing. For example, in block  610 , a first Platen (P 1 ) can be set for bulk (that is, full) Cu polish. In block  615 , a second Platen (P 2 ) can be set as a copper clearing pattern, that is, to clear the copper. In block  620 , a third Platen (P 3 ) can be configured for barrier clear and dielectric stopping. Thereafter, the wafer undergoes charge neutralization in block  625 . Charge neutralization can be performed by any ionizing source, such as the pulsed DC ionizing bar  400 . The wafer then undergoes a cleaning, such as a metrosonic cleaning, in block  630 . In block  635 , a brush cleaning is applied to a wafer. Thereafter, in block  640 , the wafer undergoes a drying stage. 
     In the example shown in  FIG. 7 , the charge neutralization in block  625  is performed before the CMP process, that is, before the first Platen in block  610 . For example, in block  605 , the surface characteristics of a wafer are measured. The surface characteristics can be measured by an inline metrology device. Then, the wafer is transferred to neutralizing station in which the wafer undergoes charge neutralization in block  625 . Charge neutralization can be performed by any ionizing source, such as the pulsed DC ionizing bar  400 . Thereafter, the wafer is transferred to one or more CMP processing stations. For example, the wafer can undergo CMP processing in block  610 , in which a first Platen (P 1 ) can be set for bulk (that is, full) Cu polish; in block  615 , in which a second Platen (P 2 ) can be set as a copper clearing pattern, that is, to clear the copper; and in block  620 , in which a third Platen (P 3 ) can be configured for barrier clear and dielectric stopping. Thereafter, the wafer undergoes a cleaning, such as a metrosonic cleaning, in block  630 . In block  635 , a brush cleaning is applied to a wafer. Then, in block  640 , the wafer undergoes a drying stage. 
     In the example shown in  FIG. 8 , the charge neutralization in block  625  is performed during the cleaning/drying stage after the metrosonic cleaning in block  630 . For example, in block  605 , the surface characteristics of a wafer are measured. The surface characteristics can be measured by an inline metrology device. Thereafter, the wafer can undergo CMP processing in block  610 , in which a first Platen (P 1 ) can be set for bulk (that is, full) Cu polish; in block  615 , in which a second Platen (P 2 ) can be set as a copper clearing pattern, that is, to clear the copper; and in block  620 , in which a third Platen (P 3 ) can be configured for barrier clear and dielectric stopping. Thereafter, the wafer undergoes a cleaning, such as a metrosonic cleaning, in block  630 . Then, the wafer undergoes charge neutralization in block  625 . Charge neutralization can be performed by any ionizing source, such as the pulsed DC ionizing bar  400 . In block  635 , a brush cleaning is applied to a wafer. Then, in block  640 , the wafer undergoes a drying stage. 
     In the example shown in  FIG. 9 , the charge neutralization in block  625  is performed during the cleaning/drying stage after the brush stage in block  635 . For example, in block  605 , the surface characteristics of a wafer are measured. The surface characteristics can be measured by an inline metrology device. Thereafter, the wafer can undergo CMP processing in block  610 , in which a first Platen (P 1 ) can be set for bulk (that is, full) Cu polish; in block  615 , in which a second Platen (P 2 ) can be set as a copper clearing pattern, that is, to clear the copper; and in block  620 , in which a third Platen (P 3 ) can be configured for barrier clear and dielectric stopping. Thereafter, the wafer undergoes a cleaning, such as a metrosonic cleaning, in block  630 . Then, the wafer undergoes charge neutralization in block  625 . Charge neutralization can be performed by any ionizing source, such as the pulsed DC ionizing bar  400 . In block  635 , a brush cleaning is applied to a wafer. Then, in block  640 , the wafer undergoes a drying stage. 
     Although  FIGS. 6 through 9  illustrate examples of a charge neutralization process, various changes may be made to  FIGS. 6 through 9 . For example, one or more steps could be omitted, modified, or rearranged and additional steps could be added in  FIGS. 6 through 9 . In some embodiments, the charge neutralization in block  625  is performed more than once and can occur at different stages during the process. For example, block  625  can occur prior to block  610  and after block  620 . Also, various modifications could be made to the structures shown in  FIGS. 4 and 5 . Further, while certain components have been described above as being formed from particular materials, each component could be formed from any suitable material(s) and in any suitable manner. In addition, the relative sizes and shapes of the components are for illustration only. 
     Embodiments of the present disclosure can be applied to all wet clean systems. In addition, embodiments of the present disclosure can be applied to all kinds of wafer surfaces that undergo wet cleaning such as metal and insulators. The wafer surfaces can undergo charge neutralization at anytime once the surface experiences charging issues. Further, dendrite defects can be reduced by a post CMP clean using base chemistry as opposed to acid chemistry. Embodiments of the present disclosure improve the production wafer yield through the elimination of the wafer surface charging and can be applied at any wet clean step. Further, embodiments of the present disclosure can enable the changing of the wafer surface charging to neutralization, negative and positive by adjusting the positive to negative ions ratios that are ejected from the ionization source. 
     While this disclosure has described certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of example embodiments does not define or constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure, as defined by the following claims.