Abstract:
According to the present invention, a semiconductor chip is mounted on a zigzag in-line type package (ZIP) partially using a tabless lead frame and bonding pads are arranged on the chip so that the chip can be applied also to other different types of packages. As different types of packages there are a small out-line J-bent type package (SOJ) for which there is used a lead frame with tab and a dual in-line type package (DIP) for which there is used a tabless lead frame. Further, a plurality of bonding pad pairs are provided among the bonding pads on the chip each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to readily facilitate, or make compatible, the semiconductor chip to a variety of or different types of packages.

Description:
BACKGROUND OF THE INVENTION: 
     The present invention relates to a semiconductor device and more particularly, to a technique which effectively allows application of a semiconductor chip (pellet) in different kinds of packages. 
     As a dynamic RAM (Random Access Memory) package, a dual in-line type package (DIP type package) has heretofore been mainly used for RAMs up to a 256 k-bit dynamic RAM. However, with higher integration, a package which permits a high density mounting has been desired. Consequently, also in dynamic RAMs of 1M bits or more, there is an increasing demand for packages other than DIP type packages, such as small out-line type (SOJ type) packages and zig-zag in-line type (ZIP type) packages. 
     SUMMARY OF THE INVENTION: 
     Having studied the above technique, the present inventors became aware of a problem that it was difficult for a single semiconductor chip to be applicable to a variety of packages in semiconductor chips which have an increased size as a result of an increase in capacity of dynamic RAMs. More particularly, as the chip size increases, the spacing between the side end of a package and a tab as a chip mounting portion becomes narrow. Therefore, also where the chip is applied to a different package type, there arises the problem of a narrower spacing being available between the side end of the package and a tab. As a result, the inner leads contained in the resin which forms the package become shorter, otherwise it will become impossible to completely receive the leads in the package. 
     In view of the above problem, the present inventors have developed a technique permitting a single semiconductor chip to be applicable to different types of packages. 
     The following is a brief description of typical contents of the present invention. 
     Bonding pads are disposed on a semiconductor chip so as to be applicable to different kinds of packages such as ZIP type package, SOJ type package and DIP type package. Further, there are used lead frames corresponding respectively to various packages. 
     According to the above improved developments, it is possible for a single semiconductor chip to be applicable or compatable to different kinds of packages by selecting bonding pads and a lead frame according to the kind of a package used. 
     Moreover, it is possible to obtain a semiconductor chip applicable to various kinds of packages by using conventional lead frames without changing the wiring other than the wiring for effecting the connection of the leads with internal circuitry of the chip or bonding pads, this being accomplished without changing the pre-existing arrangement of the bonding pads. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a side view showing an internal structure of a ZIP type package according to Embodiment I of the present invention; 
     FIG. 2 is a side view showing the shape of leads in the ZIP type package of FIG. 1; 
     FIG. 3 is a side view showing the appearance of a ZIP type package of FIG. 1; 
     FIG. 4 is a bottom view of the ZIP type package shown in FIG. 3; 
     FIG. 5 is a sectional view taken along line A--A of FIG. 3; 
     FIG. 6 is a plan view, showing an internal structure of an SOJ type package according to Embodiment II of the present invention; 
     FIG. 7 is a plan view showing an appearance of the SOJ type package of FIG. 6; 
     FIG. 8 is a side view of the SOJ type package shown in FIG. 7; 
     FIG. 9 is a sectional view taken along line B--B of the SOJ type package shown in FIG. 7; 
     FIG. 10 is a plan view showing an internal structure of a DIP type package according to Embodiment III of the present invention; 
     FIG. 11 is a plan view showing leads used in the DIP type package of FIG. 10; 
     FIG. 12 is a plan view showing an appearance of the DIP type package of FIG. 10; 
     FIG. 13 is a side view of the DIP type package shown in FIG. 12; and 
     FIG. 14 is a sectional view taken along line C--C of the DIP type package shown in FIG. 12. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention will be described below specifically with reference to the accompanying drawings. In all the drawings illustrating the embodiments, the portions having the same functions are indicated by the same reference numerals. Therefore, repeated explanations thereof will be omitted. 
     Embodiment I 
     FIG. 1 is a side view showing an internal structure of a ZIP type package according to Embodiment I of the present invention; FIG. 2 is a side view showing the shape of leads used in the ZIP type package of FIG. 1; FIG. 3 is a side view showing an appearance of the ZIP type package of FIG. 1; FIG. 4 is a bottom view of the ZIP type package shown in FIG. 3; and FIG. 5 is a sectional view taken along line A--A of FIG. 3. 
     As shown in FIGS. 1 to 5, in the ZIP type package according to Embodiment I, a semiconductor chip 1 such as, for example, a silicon chip, which constitutes a dynamic RAM of say 4 M bits (e.g. 4 M×1 bit construction) is sealed by resin 2. The size of this ZIP type package is 350 mil for example. The reference marks L 1  to L 20  denote leads. In this embodiment the number of those leads is twenty; that is, the ZIP type package according to Embodiment I is of 20 pins (the number of pins actually used, however, is 18, as will be described later). Of the leads L 1  to L 20 , the leads L 4 , L 11  and L 12  are distributed along the underside of the semiconductor chip 1. Thus, the lower-side area of the chip 1 is used for the wiring of the leads L 4 , L 11  and L 12 . Numeral 3 denotes a support plate for supporting the semiconductor chip 1. The chip 1 is supported in the greater part thereof by the support plate 3, but partially it is supported by the leads L 4 , L 11  and L 12 . That is, the semiconductor chip 1 is supported by both the support plate 3 and the leads L 4 , L 11  and L 12 . Thus, the ZIP type semiconductor device according to Embodiment I has been formed partially using a tabless lead frame. Further, by using the under-side area of the semiconductor chip 1 for the wiring of some leads it is made possible to reduce the package size as compared with the case where leads are disposed around a semiconductor chip using a tab. 
     Where the semiconductor chip 1 is supported by the support plate 3 and the leads L 4 , L 11  and L 12 , the chip 1 is mounted through an electrical insulator, for example, a polyimide-based resin sheet 4 (FIG. 5), whereby it is possible to attain electrical insulation between the support plate 3 and the leads L 4 , L 11 , L 12  and also electrical insulation among the leads L 4 , L 11  and L 12 . 
     As shown in FIG. 1, the semiconductor chip 1 is provided with four memory cell arrays M-ARY, X decoder X-DCR, Y decoder Y-DCR, word line driver W-DRV and peripheral circuitry PC. The memory cell arrays M-ARY are each divided into four partitions each 256k bits. The semiconductor chip 1 is provided with bonding pads P 1  to P 35  at short-side end portions thereof. Of these bonding pads P 1  -P 35 , the bonding pads P 1  -P 3 , P 5 , P 9  -P 13 , P 20  -P 30  and the leads L 1  -P 8 , L 11  -L 20  are bonded through wires W. Thus, the semiconductor chip 1 is provided with bonding pads not actually used which are P 4 , P 6  -P 8 , P 14  -P 19  and P 31  -P 35 . These bonding pads are to be used when an SOJ type package or a DIP type package is used in place of the ZIP type package. The bonding pads P 4 , P 6  -P 8 , P 14  -P 19  and P 31  -P 35  which are not actually used in the ZIP type package are electrically connected to the foregoing leads in the same package; that is, they have the same function as that of the bonding pads P.sub. 1 -P 3 , P 5 , P 9  -P 13  and P 20  -P 30  which are actually being used. Thus, the bonding pads P 1  -P 35  are provided on the semiconductor chip 1 so as to be applicable to packages of different types from the ZIP type package. Consequently, using the same semiconductor chip 1, the present invention is applicable to other packages than the ZIP type package. That is, when there is a demand for using a package other than the ZIP type package, the demand can be met by a mere change to the package to be used without redesigning the semiconductor chip 1. 
     The leads (pins) L 1  -L 20  function as shown in FIG. 1. In the same figure, A0-A10 represent address signals, Vcc represents a supply potential, Vss an earth potential, CAS a column address strobe signal, RAS a row address strobe signal, WE a write enable signal, Dout a data output, and Din a data input. The leads L 9  and L 10  are not actually used, which are indicated by NC. The lead L 15  of Vcc and the bonding pads P 22 , P 23  are bonded together through two wires W, and the lead L 4  of Vss and the bonding pads P 12 , P 13  are bonded through two wires W. This is for reducing the power source impedance. 
     The following is an explanation of a semiconductor device assembling process using the ZIP type package of Embodiment I. 
     In the semiconductor device with the semiconductor chip of 4MDRAM mounted thereon according to Embodiment I, as shown in FIGS. 1-5, the insulating sheet 4 is bonded onto the support plate 3 and the inner lead portions of the leads L 4 , L 11  and L 12 , then the semiconductor chip 1 of 4MDRAM is mounted on the sheet 4. The foregoing lead frame, having such a shape as shown in FIG. 2, is formed by a copper alloy or an iron-nickel alloy. The insulating sheet 4 and the semiconductor chip 1 are mounted through an adhesive (not shown) or by pressure-bonding. 
     Next, the bonding portions of the leads L 1  -L 8 , L 11  -L 20  and the bonding pads P 1  -P 3 , P 5 , P 9  -P 13 , P 20  -P 30  are electrically connected together through bonding wires W which are gold (Au) wires for example. The wire bonding is carried out by a wedge ball bonding method. 
     After the wire bonding is over, a resin-sealed type semiconductor device is completed through a conventional resin sealing step. For example, an epoxy resin is used as the sealing resin. 
     Embodiment II 
     FIG. 6 is a plan view showing an internal structure of an SOJ type package according to Embodiment II of the present invention; FIG. 7 is a plan view showing an appearance of the SOJ type package of FIG. 6; FIG. 8 is a side view of the SOJ type package shown in FIG. 7; and FIG. 9 is a sectional view taken along line B--B of the SOJ type package shown in FIG. 7. 
     In the SOJ type package according to Embodiment II, as shown in FIGS. 6 to 9, a semiconductor chip 1 similar to that used in Embodiment I is sealed by resin 2. The size of this SOJ type package is 350 mil for example. Unlike Embodiment I, leads L 1  -L 20  have been formed using a lead frame with tab. The semiconductor chip 1 is supported by only a tab 5 which is of about the same shape as the chip. The lead frame with tab was used so that the same semiconductor chip as that used in the ZIP type package of Embodiment I could be used also in the SOJ type package. Since the semiconductor chip 1 is supported by only the tab 5, the semiconductor chip 1 is mounted directly on the tab 5 rather than through an electrical insulation sheet such as a polyimide resin sheet 4 as in Embodiment I. As shown in FIG. 9, the semiconductor chip 1 is attached to the tab through an adhesive 4&#39;. 
     In this embodiment II, of the bonding pads P 1  -P 35  provided on the semiconductor chip 1, it is P 1  -P 3 , P 5 , P 12 , P 13 , P 15  -P 23  and P 31  -P 35  that are actually being used. The bonding pads P 1  -P 3 , P 5 , P 12 , P 13 , P 15  -P 23 , P 31  -P 35  and leads L 1  -L 3 , L 5  -L 16 , L 18  -L 20  are bonded through wires W. The leads L 4  and L 17  are not used in this Embodiment II. 
     The semiconductor chip 1 used in this Embodiment II is the same as that used in the ZIP type package of Embodiment I and is formed with the same circuitry as that in Embodiment I. The bonding pads used here are P 1  -P 3 , P 5 , P 12 , P 13 , P 15  -P 22  and P 31  -P 35 . These bonding pads have been preformed on the semiconductor chip for the ZIP type package of Embodiment I, having the same function as that of the bonding pads used in the ZIP type package. The bonding pads of the semiconductor chip being used are those which correspond to the lead frame for the SOJ type package. 
     Thus, according to this Embodiment II, out of the bonding pads P 1  -P 35  provided on the semiconductor chip 1 for the ZIP type package, those prepared in advance for the SOJ type package are used, whereby the SOJ type package incorporating the semiconductor chip 1 can be obtained easily without requiring the redesigning of the chip 1. 
     The following description is now provided with respect to a semiconductor device assembling process using the SOJ type package of Embodiment II. 
     As shown in FIGS. 6 to 9, the semiconductor chip is mounted on the tab 5 through the adhesive 4&#39; which is an electroconductive material such as silver (Ag) paste for example. The foregoing lead frame is formed by a copper alloy or an iron-nickel alloy. 
     Then, the bonding portions of the leads L 1  -L 3 , L 5  -L 16 , L 18  -L 20  and the bonding pads P 1  -P 3 , P 5 , P 12 , P 13 , P 15  -P 23 , P 31  -P 35  on the semiconductor chip are electrically connected through bonding wires W. The bonding is carried out using, for example, gold (Au) wires according to a wedge ball method. 
     After the wire bonding is over, leads are formed through a conventional resin sealing step, whereby a semiconductor device for an SOJ type package is completed. 
     Embodiment III 
     FIG. 10 is a plan view showing an internal structure of a DIP type package according to Embodiment III of the present invention; FIG. 11 is a plan view showing leads used in the DIP type package of FIG. 10; FIG. 12 is a plan view showing an appearance of the DIP type package of FIG. 10; FIG. 13 is a side view of the DIP type package shown in FIG. 12; and FIG. 14 is a sectional view taken along line C--C of the DIP type package shown in FIG. 12. 
     In the DIP type package according to Embodiment III, as shown in FIGS. 10 to 14, a semiconductor chip 1 similar to that of Embodiment I is sealed by resin 2. The size of this DIP type package is 300 mil for example. Leads L 1  to L 18  have been formed using a tabless lead frame in the same manner as in Embodiment I, which lead frame according to the present embodiment is a tabless lead frame for DIP type package. In this Embodiment III, unlike Embodiments I and II, the support plate 3 or the tab 5 is not provided, and the semiconductor chip 1 is supported by the leads L 2  -L 8  and L 11  -L 17  through sheet 4. The whole of the underside area of the chip 1 is used for the wiring of the leads L 1  -L 18 . 
     Of the bonding pads P 1  -P 35  provided on the semiconductor chip 1, it is P 5  -P 13  and P 22  -P 32  that are actually being used. These bonding pads P 5  -P 13 , P 22  -P 32  and the leads L 1  -L 18  are bonded through wires W. 
     In this Embodiment III, in order to attain satisfactory bonding with the leads, it is necessary that the function of the bonding pads P 9 , P 11  and P 24  -P 32  be changed from that in Embodiments I and II. This functional change can be effected by changing the wiring of the final aluminum film used for the connection of the semiconductor chip 1 and the bonding pads into a wiring different from that used in the semiconductor chips for the ZIP and SOJ type packages. That is, only the function of the bonding pads is changed while their positions are kept intact. In comparison between FIGS. 1 and 10, the change in function from the bonding pads for the ZIP type package to the bonding pads for the DIP type package is performed specifically in the following manner: A0: from P 25  to P 27 , A1: from P 24  to P 26 , A2: from P 20  to P 25  A3: from P 21  to P 24 , A4: from P 26  to P 32 , A5: from P 27  to P 31 , A6: from P 28  to P 30 , A8: from P 30  to P 28 , A9: from P 11  to P 9 , A10: from P 1  to P 8 , Dout: from P 9   to P 11 , WE: from P 3  to P 6 , RAS: from P 2  to P 7 . 
     According to this Embodiment III, as can be seen from the above, by using those bonding pads which have been prepared in advance for the DIP type package out of the bonding pads P 1  -P 35 , it is possible to easily obtain a DIP type package incorporating the semiconductor chip 1 through only the change of the aluminum wiring without redesigning the other portions of the chip 1. 
     Moreover, the DIP type package can be obtained without changing the lead frame and without changing the internal circuitry, other than the application of the final aluminum film wiring for connection to the pre-existing the arrangement of the bonding pads. 
     Further, the use of a tabless lead frame permits reduction of the package size. 
     The assembly of the DIP package semiconductor device of Embodiment III is performed in the following manner as shown in FIGS. 10 to 14. The semiconductor chip 1 is mounted on the inner lead portions of the tabless lead frame through an insulating sheet and, using the same steps as in Embodiment I, there is completed the DIP package semiconductor device. In this case, the leads L 1  -L 18  and the bonding pads P 5  -P 13 , P 22  -P 32  are electrically connected through bonding wires W. The function of the bonding pads is changed by changing only the aluminum wiring according to a master slice method in corresponding relation to the tabless lead frame. 
     Although the present invention has been described above in conjunction with specific exemplifying embodiments thereof, it goes without saying that the invention is not limited to those embodiments and that various modifications may be made in the range not departing from the spirit and scope of the invention. 
     For example, the shape of the leads L 1  -L 20  may be changed where required. The 4M-bit dynamic RAM constituted by the semiconductor chip 1 may be of a 4M×1-bit construction. Not only the present invention is applicable to other semiconductor integrated circuit devices than dynamic RAM&#39;s, such as static RAM&#39;s for example, but also it is possible to use other packages than the foregoing SOJ and DIP type packages, as packages of a different type from the ZIP type package. Thus, the same semiconductor chip is applicable to different types of packages.