Abstract:
Located between the frustoconical needle tip and the cylindrical needle shank of a nozzle needle of a fuel injection valve is a frustoconical needle portion, into which is introduced a peripheral groove, by means of which damping is capable of being set, depending on the position of the groove, during the axial movement of the nozzle needle.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to analog-to-digital converters having a first reference potential source for providing first reference potentials, a first input stage having at least two differential amplifiers. Each of the differential amplifiers have a first and second transistor, a first input for feeding in one of the reference potentials, a second input for feeding in a first input signal, and two output terminals. 
     2. Description of the Related Art 
     An analog-to-digital converter (A/D converter) of this type is disclosed for example in Hui Pan et al.: “A3.3V 12b 50Msample/s A/D Converter in 0.6 μm CMOS with over 80 dB SFDR”, paper MP 2.4, Proceedings of the International Solid State Circuit Conference ISSCC 2000. FIG. 1 illustrates an input stage of such an A/D converter according to the prior art. 
     This A/D converter has as reference potential source, a series circuit of resistors R 11 , R 12 , R 13 , R 14 , R 15  which are connected up between a supply potential Vdd and a reference-ground potential GND. In this case, different reference potentials VRP 1 , VRP 2 , VRP 3 , VRP 4  can be tapped off in each case at nodes between two adjacent resistors. These reference potentials VRP 1 , VRP 2 , VRP 3 , VRP 4  are fed to respective first inputs of identically constructed differential amplifiers DV 11 , DV 12 , DV 13 , DV 14 , a first input signal VIP being fed to second inputs of these differential amplifiers DV 11 , . . . , DV 14 . The differential amplifiers DV 11 , . . . , DV 14  each have first and second transistors T 11 , T 12 , the gate terminal of the first transistor T 11  being connected to a first input terminal E 11  of the differential amplifier and the gate terminal of the second transistor T 12  being connected to a second input terminal E 12 . Source terminals of the first and second transistors of the differential amplifier DV 11 , . . . , DV 14  are connected to a common current source I 11 . The drain terminals of the first and second transistors T 11 , T 12  form output terminals A 11 , A 12  of the differential amplifiers DV 11 , . . . , DV 14 , these output terminals A 11 , A 12  being connected to a second supply potential V+ via resistors RL 1 , RL 2 , for example. By means of comparators (not specifically illustrated), the potentials at the two output terminals A 11 , A 12  of a differential amplifier are evaluated, and the first input signal VIP is compared with all the reference potentials VRP 1 , . . . , VRP 4  in this way. 
     The A/D converter known according to the prior art and illustrated in FIG. 1 has a second input stage in addition to the first input stage. This second input stage has a series circuit of resistors R 21 , R 22 , R 23 , R 24 , which are connected up between the supply potential Vdd and the reference-ground potential GND. In this case, reference potentials VRM 1 , VRM 2 , VRM 3 , VRM 4  can be tapped off at nodes between the resistors R 21 , . . . , R 24  and are fed to respective first inputs of differential amplifiers DV 21 , DV 22 , DV 23 , DV 24 . These differential amplifiers DV 21 , . . . , DV 24  are identical to one another and identical to the differential amplifiers DV 11 , . . . , DV 14  of the first input stage. A second input signal VIM, which corresponds to the difference between a constant signal and the input signal VIP, is fed to the second input terminal of the differential amplifiers DV 21 , . . . , DV 24  of the second input stage. A differential amplifier of the first input stage and a differential amplifier of the second input stage in each case form a differential amplifier pair, in which the first output A 11  of a differential amplifier DV 11  of the first input stage is connected to the second output A 22  of a differential amplifier DV 21  of the second input stage and a second output A 12  of a differential amplifier DV 11  of the first input stage is connected to a first output A 21  of a differential amplifier DV 21  of the second input stage. In this case, the common outputs M 1 , P 1  are connected to the second supply potential V+ via resistors RL 1 , RL 2 . The reference potentials VRM 1 , . . . , VRM 4  fed to the differential amplifiers DV 21 , . . . , DV 24  of the second input stage correspond to the difference between the first supply potential Vdd and the supply potential VRP 1 , VRP 2 , VRP 3 , VRP 4  of the associated differential amplifier DV 11 , . . . , DV 14  of the first input stage. This combination of two differential amplifiers to form a differential amplifier pair, complementary input signals VIP, VIM and complementary reference potentials VRP 1 , . . . , VRP 4 , VRM 1 , . . . , VRM 4  in each case being fed to the individual differential amplifiers of a differential amplifier pair, increases the common-mode rejection of such an A/D converter according to the prior art. 
     In order to be able to operate the transistors of the differential amplifiers in the known A/D converter in the saturation region, a minimum gate potential is required for driving them, which results from the sum of the saturation voltage of the current source, the threshold voltage, that is to say the gate-source voltage at which the transistors start to conduct, and an effective gate voltage. When the transistors are realized as n-channel MOS transistors and the current sources are also realized as MOS transistors using silicon technology, typical values are 0.15 V for the saturation voltage of the current source, 0.3 V for the threshold voltage and 0.15 V for the required effective gate voltage, with the result that the gate potential at the transistors must be a minimum of 0.6 V in order to be able to operate the transistors of the differential amplifiers in the saturation region. In other words, the respective smallest reference potential (VRP 1 , VRM 4  in FIG. 1) must be at least 0.6 V. If a supply voltage of 1.2 V is assumed for an entire circuit arrangement in which the A/D converter is realized, and if account is taken of the fact that driver stages for providing the input voltage VIP, VIM usually fall short by at least 0.2 V in attaining the supply voltage of 1.2 V, with the result that the maximum input voltage is only about 1.0 V, then a usable input voltage range remains within which the input signal VIP is permitted to fluctuate by only 0.4 V, which corresponds to one third of the supply voltage. Such a small input voltage range is not sufficient for many applications. 
     SUMMARY OF THE INVENTION 
     It is an aim of the present invention, therefore, to provide an analog-to-digital converter in which the processable voltage range of the input signal is increased compared with previously known analog-to-digital converters. 
     This aim is achieved with an A/D converter wherein first and second transistors of at least one of the differential amplifiers are of a type complementary to the first and second transistors of the other differential amplifiers. 
     Accordingly, the A/D converter according to the invention has a first reference potential source for providing first reference potentials, and a first input stage having at least two differential amplifiers, which each have a first and a second transistor. According to the invention, the first and second transistors of at least one differential amplifier are of a type complementary to the first and second transistors of the other differential amplifiers, in other words the first and second transistors of at least one differential amplifier are designed as p-channel transistors, while the first and second transistors of the other differential amplifiers are designed as n-channel transistors. 
     The advantage of using differential amplifiers having p-channel transistors and differential amplifiers having n-channel transistors in an A/D converter consists in the possibility of also being able to process input signals which lie below the minimum gate potential for n-channel transistors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is explained in more detail below using exemplary embodiments with reference to figures, in which: 
     FIG. 1 shows an A/D converter according to the prior art; 
     FIG. 2 shows an A/D converter according to the invention in accordance with a first embodiment with a first input stage; 
     FIG. 3 shows an A/D converter according to the invention in accordance with a second embodiment with a first and a second input stage; 
     FIG. 4 shows an A/D converter in accordance with a further embodiment, in which output terminals of differential amplifiers of a differential amplifier pair are in each case coupled to one another via a switch for controlling output currents; 
     FIG. 5 shows an exemplary embodiment of a switch for controlling the output currents; 
     FIG. 6 shows an A/D converter according to the invention in accordance with a further embodiment, in which the current sources of the differential amplifiers are driven by a current regulating arrangement; 
     FIG. 7 shows a circuit diagram of part of the current regulating arrangement in accordance with FIG. 6; 
     FIG. 8 shows an A/D converter according to the invention in accordance with a further embodiment, in which the current sources are driven in a manner dependent on the respective reference potentials; 
     FIG. 9 shows an A/D converter in accordance with a further embodiment of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the figures, unless specified otherwise, identical reference symbols designate identical parts with the same meaning. 
     FIG. 2 shows an A/D converter in accordance with a first embodiment of the invention. The A/D converter has a first reference current source comprising a series circuit of resistors R 11 , R 12 , R 13 , R 14 , R 15  between a supply potential Vdd and a reference-ground potential GND and differential amplifiers DP 11 , DP 12 , DN 13 , DN 14  for comparing reference potentials VRP 1 , VRP 2 , VRP 3 , VRP 4  with an input signal VIP. The resistors R 11 , R 12 , R 13 , R 14 , R 15  preferably have the same value, with the result that the reference potentials VRP 1 , VRP 2 , VRP 3 , VRP 4 , which can each be tapped off at nodes between two adjacent resistors, in each case differ by multiples of the smallest reference potential VRP 1 . FIG. 2 shows, by way of example, a 2-bit converter having four differential amplifiers in order to be able to compare the input signal VIP with four different reference potentials VRP 1 , . . . , VRP 4 . The resolution of the A/D converter increases with the number of differential amplifiers, and so an 8-bit converter requires 256 differential amplifiers and a reference potential source which provides a corresponding number of reference potentials. Such a reference potential source can be realized in a simple manner by connecting a correspondingly large number of resistors in series between the supply potential and the reference-ground potential. 
     The differential amplifiers DP 11 , DP 12 , DN 13 , DN 14  of the A/D converter according to the invention each have first transistors TP 11 , TN 11  and second transistors TP 12 , TN 12 , the source terminals of the two transistors TP 11 , TP 12 ; TN 11 , TN 12  of a differential amplifier DP 11 , DN 13  being jointly connected to a current source IP 11 , IN 11 . For reasons of clarity, reference symbols for the components of the differential amplifiers are depicted only for the components of the differential amplifiers DP 11 , DN 13 . 
     The construction of the differential amplifier DP 11 , which is connected to the lowest reference potential VRP 1 , is identical to the construction of the differential amplifier DP 12 , which is connected to the second lowest reference potential VRP 2 . The first and second transistors TP 11 , TP 12  of these differential amplifiers DP 11 , DP 12  are designed as p-channel transistors. In this case, the gate terminals of the first transistors TP 11  are connected to the respective reference potential VRP 1 , VRP 2  via first input terminals EP 11  of the differential amplifiers DP 11 , DP 12 , and the gate terminals of the second transistors TP 12  are connected to the first input signal VIP via second input terminals EP 12  of the differential amplifiers DP 11 , DP 12 . The source terminals of the first and second transistors TP 11 , TP 12  of the differential amplifiers DP 11 , DP 12  are in each case connected to a common current source IP 11 , whose other terminal is connected to supply potential Vdd. The drain terminals of the first transistors TP 11  form output terminals AP 11  and the drain terminals of the second transistors TP 12  form second output terminals AP 12  of the differential amplifiers DP 11 , DP 12 . These output terminals are connected to a second supply potential V+ via load resistors RL 11 , RL 21 , RL 12 , RL 22  in the exemplary embodiment in accordance with FIG.  2 . 
     The potentials at the output terminals AP 11 , AP 12  are fed to inputs M 1 , P 1 , M 2 , P 2  of comparators (not specifically illustrated), the comparators evaluating these potentials, which are dependent on the ratio of the input signal VIP and of the respective reference signal VRP 1 , VRP 2  of the differential amplifiers DP 11 , DP 12 . 
     The construction of the differential amplifiers DN 13 , DN 14  connected to the two highest reference potentials VRP 3 , VRP 4  corresponds to that of the differential amplifiers DP 11 , DP 12 , n-channel MOS transistors being used as first and second transistors TN 11 , TN 12  for the differential amplifiers DN 13 , DN 14 . The source terminals of the second transistors TN 11 , TN 12  of one of the differential amplifiers DN 13 , DN 14  are in each case connected to a common current source IN 11 , whose other terminal is connected to reference-ground potential GND. The gate terminals of the first transistors TN 11  are connected to the respective reference potential VRP 3 , VRP 4  via first input terminals EN 11  of the differential amplifiers DN 13 , DN 14  and the input signal VIP is fed to the gate terminals of the second transistors TN 12  via second input terminals EN 12  of the differential amplifiers DN 13 , DN 14 . The drain terminals of the first transistors TN 11  form first output terminals AN 11  and the drain terminals of the second transistors TN 12  form second output terminals AN 12  of the differential amplifiers DN 13 , DN 14 . The output terminals AN 11 , AN 12  of the differential amplifiers DN 13 , DN 14  are likewise connected to the second supply potential V+ via load resistors RL 13 , RL 23 , RL 14 , RL 24 . The potentials at the output terminals AN 11 , AN 12  of the differential amplifiers DN 13 , DN 14  having the n-channel transistors are likewise fed to input terminals M 3 , M 4 , P 3 , P 4  of comparators (not specifically illustrated) for evaluation of the output potentials. 
     The advantage of using differential amplifiers DP 11 , DP 12  having p-channel transistors and differential amplifiers DN 13 , DN 14  having n-channel transistors in an A/D converter consists in the possibility of also being able to process input signals VIP which lie below the minimum gate potential for n-channel transistors, as is explained below. 
     Firstly, the method of operation of a differential amplifier having n-channel transistors in the A/D converter shall be explained using the differential amplifier DN 13 . In this respect, it should be noted that the load resistors RL 11 , . . . , RL 24  preferably have the same value, this being an assumption on which the following explanation is based. 
     If the input signal VIP is greater than the third reference potential VRP 3 , then the second MOS transistor TN 12  conducts better than the first MOS transistor TN 11  and the current from the second supply source V+ via the load resistor RL 23  is greater than the current from the second supply voltage source V+ via the load resistor RL 13 . The sum of the currents via the load resistors RL 13 , RL 23  is determined by the current supplied by the current source IN 11 . The voltage U 23  across the load resistor RL 23  is then greater than the voltage U 13  across the load resistor RL 13 , with the result that the potential at the node P 3 , or the second output terminal AN 12  of the differential amplifier DN 13 , which results from the difference between the second supply potential V+ and the voltage U 23 , is less than the potential at the node M 3 , or the first output terminal AN 11  of the differential amplifier DN 13 , which results from the difference between the second supply potential V+ and the voltage U 13 . If the input signal VIP falls, then the current through the load resistor RL 23  falls and so, too, does the voltage U 23 , as a result of which the potential at the node P 3  rises. When the current through the load resistor RL 23  falls, the current through the load resistor RL 13  rises, as a result of which the potential at the node M 3  falls. The potentials in the nodes M 3 , P 3  have the same magnitude when the input signal VIP corresponds to the third reference potential VRP 3 , and the potential at the node M 3  becomes less than the potential at the node P 3  when the input signal VIP falls below the value of the third reference potential VRP 3 . In order to be able to operate the n-channel transistors in the saturation region, those MOS transistors which are fabricated by means of typical deep submicron processes require gate potentials of at least 0.6 V, of which 0.15 V is allotted to the saturation voltage of the current source IN 11 , 0.30 V is allotted to the threshold voltage of the transistors TN 11 , TN 12 , and 0.15 V is allotted to the effective gate-source voltage of the transistors TN 11 , TN 12 . 
     The method of operation of a differential amplifier having p-channel transistors in the A/D converter is explained using the differential amplifier DP 11 . 
     The first supply potential Vdd and the second supply potential V+ are preferably coordinated with one another in such a way that the first supply potential Vdd is greater than the second supply potential V+, with the result that a current can flow from the current source IP 11  via the transistors TP 11 , TP 12  and the load resistors RL 11 , RL 21  in the direction of the second supply potential V+. If the input signal VIP is greater than the first reference potential VRP 1 , then the gate-source voltage of the second transistor TP 12  is less than the gate-source voltage of the first transistor TP 11 , as a result of which a smaller current flows via the second transistor TP 12  and the load resistor RL 21  than via the first transistor TP 11  and the load resistor RL 11 . The voltage U 21  across the load resistor RL 21  is thus smaller than the voltage U 11  across the load resistor RL 11 . The potential at the node P 1 , or the second output terminal AP 12  of the differential amplifier DP 11 , which results from the sum of the voltage U 21  and the second supply potential V+, is therefore less than the potential at the node M 1 , or the first output terminal AP 11 , of the differential amplifier DP 11 , which results from the sum of the voltage U 21  and the second supply potential V+. If the input signal VIP falls, then the gate-source voltage of the second transistor TP 12  rises, as a result of which the current through this transistor TP 12  and the load resistor RL 21  rises, as a result of which the voltage U 21  rises and the potential at the node P 1  increases. The currents through the first and second transistors TP 11 , TP 12  have the same magnitude when the input signal VIP corresponds to the first reference potential VRP 1 . The potential at the node Ml becomes less than the potential at the node P 11  when the input signal VIP falls below the value of the first reference potential VRP 1 . 
     Both in the case of a differential amplifier DN 13  having n-channel transistors and in the case of a differential amplifier having p-channel transistors, the potential at the node P 1 , P 3  is less than the potential at the node M 1 , M 3  if the input signal VIP is greater than the respective reference potential VRP 1 , VRP 3 . This potential at the node M 1 , M 3  falls as the input signal VIP falls, as a result of which the potential at the node P 1 , P 3  rises correspondingly. The potentials at the output terminals of differential amplifiers having n-channel transistors and differential amplifiers having p-channel transistors therefore behave correspondingly in the event of changes in the input signal VIP. 
     The absolute values of the potentials at the output terminals P 3 , M 3  of differential amplifiers DN 13  having n-channel transistors and output terminals P 1 , M 1  of differential amplifiers DP 11  having p-channel transistors may differ. This is irrelevant to A/D converters, however, since the output signals of the comparators connected downstream, or of other suitable evaluation circuits, such as e.g. convolution stages with a comparator connected downstream, are merely able to differentiate whether the potential at the nodes P 1 , P 3  is greater/less than the potential at the nodes M 1 , M 3 . The zero crossings, that is to say the states in which the potentials at the output terminals of a differential amplifier correspond, result in a corresponding manner in the case of differential amplifiers having p-channel transistors and in the case of differential amplifiers having n-channel transistors in each case when the input signal VIP has exactly the same magnitude as the reference potential VRP 1 ; VRP 3  assigned to the respective differential amplifier. 
     In contrast to differential amplifiers having n-channel transistors in which the input signal VIP or the reference potential VRP 3  must be at least 0.6 V in order to bring the n-channel transistors into the saturation region, the two differential amplifiers DP 11 , DP 12  having p-channel transistors function even with reference potentials VRP 1 , VRP 2  or an input signal VIP which has to be only slightly greater than 0 V. Therefore, with the A/D converter according to the invention as shown in FIG. 2, it is possible to process considerably smaller input signals VIP than in the case of previously known A/D converters. 
     FIG. 3 shows a further exemplary embodiment of an A/D converter according to the invention, in which the A/D converter in accordance with FIG. 2 serves as the first input stage in the left-hand part of the circuit diagram and which has an input stage which is constructed complementarily to the first input stage and is illustrated in the right-hand part of the circuit diagram. 
     The second input stage has a second reference potential source comprising a series circuit of resistors R 21 , R 22 , R 23 , R 24 , R 25  between the supply potential Vdd and reference-ground potential GND. These resistors R 21 , . . . , R 25  preferably have the same value, with the result that reference potentials VRM 1 , VRM 2 , VRM 3 , VRM 4 , which can be tapped off at nodes between the resistors R 21 , . . . , R 25 , differ by multiples of the smallest reference potential VRM 4 . The resistors R 11 , . . . , R 15  of the first reference potential source and the resistors R 21 , . . . , R 25  of the second reference potential source preferably have the same value. The first reference potential VRP 1 —drawn off near the reference-ground potential GND—of the first reference potential source then corresponds to the fourth reference potential VRM 4 —drawn off near the reference-ground potential GND—of the second reference potential source, the reference potential VRP 2  corresponds to the reference potential VRM 3 , the reference potential VRP 3  corresponds to the reference potential VRM 2 , and the reference potential VRP 4 —drawn off near the supply potential Vdd—of the first reference potential source corresponds to the reference potential VRM 1 —drawn off near the supply potential Vdd—of the second reference potential source. 
     The reference potentials VRM 1 , . . . , VRM 4  are fed to first input terminals EN 21 , EP 21  of differential amplifiers DN 21 , DN 22 , DP 23 , DP 24 . A respective second input signal VIM, which preferably results from the difference between the first supply potential Vdd and the first input signal VIP, is fed to second inputs EN 22 , EP 22  of the differential amplifiers DN 21 , DN 22 , DP 23 , DP 24 . The differential amplifiers DN 21 , DN 22 , DP 23 , DP 24  each have a first transistor TN 21 , TP 21  and a second transistor TN 22 , TP 22 . For reasons of clarity, only the components of the differential amplifiers DN 21  and DP 23  are provided with reference symbols in FIG.  2 . The differential amplifiers DN 21 , DN 22  connected to the two highest reference potentials VRM 1 , VRM 2  are constructed identically, their transistors TN 21 , TN 22  being designed as n-channel MOS transistors. Equally, the differential amplifiers DP 23 , DP 24 , which are connected to the two smallest reference potentials VRM 3 , VRM 4 , are of identical design, the first and second transistors TP 21 , TP 22  of these differential amplifiers DP 23 , DP 24  being designed as p-channel MOS transistors. 
     The method of operation of the differential amplifiers DN 21 , DN 22  corresponds to the method of operation of the differential amplifiers DN 13 , DN 14  and the method of operation of the differential amplifiers having the p-channel transistors DP 23 , DP 24  corresponds to the method of operation of the differential amplifiers DP 11 , DP 12 . 
     The differential amplifier DP 11  of the first input stage and the differential amplifier DN 21  of the second input stage form a differential amplifier pair, the first output AP 11  of the differential amplifier DP 11  and a second output AN 22  of the differential amplifier DN 21  being jointly connected to the node M 1 , and the second output AP 12  of the differential amplifier DP 11  and the first output AN 21  of the differential amplifier DN 21  being jointly connected to the node P 1 . In a corresponding manner, the differential amplifiers DP 12 , DN 22  form a second differential amplifier pair, the differential amplifiers DN 13 , DP 23  form a third differential amplifier pair, and the differential amplifiers DN 14 , DP 24  form a fourth differential amplifier pair. The first output AN 11  of the differential amplifier DN 13  is connected with a second output AP 22  of the differential amplifier DP 23  to the node M 3  and the second output AN 12  of the differential amplifier DN 13  is connected with a first output AP 21  of the differential amplifier DP 23  to the third node P 3 . Each of the differential amplifier pairs in the exemplary embodiment in accordance with FIG. 3 thus comprises a differential amplifier having n-channel transistors and a differential amplifier having p-channel transistors. 
     The differential amplifiers of the first and second input stages act in the same sense on the potential at the respective node to which outputs of differential amplifiers of the first and second input stages are jointly connected, as is explained using the differential amplifier pair DP 11 , DN 21 . If the first input signal VIP rises, then, as explained above, the current from the current source IP 11  via the second transistor TP 12  and the load resistor RL 21  falls, as a result of which the potential at the node P 1  falls and, in a corresponding manner, the potential at the node Ml rises. If the first input signal VIP rises then the second input signal VIM falls. As a result, the gate-source voltage of the second transistor TN 22  falls, as a result of which the current from the second supply voltage V+ via the resistor RL 11  and the second transistor TN 22  falls and the potential at the node M 1  likewise rises. The advantage of using a differential amplifier pair DP 11 , DN 21  whose differential amplifiers are jointly connected to comparators for evaluation of the potentials at the nodes M 1 , P 1 , . . . , M 4 , P 4  consists in an increase in the common-mode rejection through a fully differential construction, that is to say common-mode interference signals affect the result of the A/D conversion to a lesser extent than in the case of an A/D converter in accordance with FIG.  2 . 
     The current which is caused by the n-channel transistors TN 22 , TN 21 , TN 11 , TN 12  through the load resistors RL 11 , RL 21 , RL 13 , RL 23  is opposite to the currents which are caused by the p-channel transistors TP 11 , TP 12 , TP 21 , TP 22  through said load resistors RL 11 , RL 21 , RL 13 , RL 23 . However, the changes in the potentials at the nodes M 1 , P 1 , M 3 , P 3  which are brought about by changes in the input signals VIP, VIM, or by changes to said currents which are caused thereby, act in the same sense, as has been explained. 
     In accordance with an embodiment of the A/D converter according to the invention which is illustrated in FIG. 4, it is provided that, in differential amplifier pairs each having a differential amplifier having p-channel transistors and a respective differential amplifier having n-channel transistors, the outputs of these differential amplifiers are connected to the load resistors not directly but via suitable switching means for diverting the output currents. 
     Accordingly, a first switch SM 1  of this type is provided between the differential amplifiers DP 11 , DN 21 , a second switch SM 2  of this type is provided between the differential amplifiers DP 12 , DN 22 , a third switch SM 3  of this type is provided between the differential amplifiers DN 13 , DP 23 , and a fourth switch SM 4  of this type is provided between the differential amplifiers DN 14 , DP 24 . Each of the switches SMx (x hereinafter denotes one of the indices  1  to  4 ) has a first input E 1   x , a second input E 2   x , a third input E 3   x  and a fourth input E 4   x . The connections and method of operation of the identically constructed switches SMx are explained below using the differential amplifier pair DP 11 , DN 21 . 
     The first input E 11  of the switch SM 1  is connected to the second output AN 22  of the differential amplifier DN 21  of the second input stage and the second input E 21  is connected to the first output AN 21  of the differential amplifier DN 21  of the second input stage. The third input E 31  of the switch SM 1  is connected to the first output AP 11  and the fourth input E 41  is connected to the second output AP 12  of the differential amplifier DP 11  of the first input stage. The switch SM 1  has a first output AM 1 , which is connected to the load resistor RL 11  and to the input M 1  of the comparator. The switch SM 1  furthermore has a second output AP 1 , which is connected to the load resistor RL 21  and to the input P 1  of the comparator. 
     The switch SM 1  is preferably designed in such a way that it brings about a current IM 1  via the load resistor RL 11  into the switch SM 1  for which the following holds true: 
     
       
         IM 1 = IL +I 22 −I 11 ,  
       
     
     where I 11  is the load current of the first p-channel transistor TP 11  of the differential amplifier DP 11  and I 22  is the load current of the second n-channel transistor TN 22  of the differential amplifier DN 21 . The current IL is a constant current brought about by current sources in the switch SM 1 , and the current IL may also be zero. The switch SM 1  furthermore brings about, through the load resistor RL 21 , a current IP 1  into the switch SM 1  for which the following holds true: 
     
       
         IP 1 = IL +I 21 −I 12 ,  
       
     
     where I 12  is the load current of the second p-channel transistor TP 12  of the differential amplifier DP 11  and I 21  is the load current of the first n-channel transistor TN 21  of the differential amplifier DN 21 . 
     The function of the switches SM 1 , . . . , SM 4  is to create more favorable and reproducible operating conditions at the outputs of the differential amplifiers, it being endeavored, in particular, to fix the outputs of the differential amplifiers at a potential near the respective supply potential thereof, in order to ensure that the MOS transistors of the differential amplifiers always remain in saturation in a voltage range around the respective reference potential. 
     The construction of a switch of this type is explained below in FIG. 5, the nomenclature of the input currents and of the connecting terminals corresponding to those of the first switching means SM 1  in accordance with FIG.  4 . 
     In order to combine the current I 22  at the first input terminal E 11  and the current I 11  at the third input terminal E 31 , a series circuit comprising a first current source IQ 1 , a p-channel transistor T 54 , an n-channel transistor T 56  and a further current source IQ 3  is connected up between supply potential Vdd and reference-ground potential GND. In this case, the first input terminal E 11  is connected to a node which is common to the current source IQ 1  and the transistor T 54 . The third input terminal E 31  is connected to a node which is common to the current source IQ 3  and the transistor T 56 , and the first output terminal AM 1  is connected to a node which is common to the transistors T 54 , T 56 . In a corresponding manner, in order to combine the currents I 21  at the second input terminal E 21  and I 12  at the fourth input terminal E 41 , the switch has a series circuit comprising a current source IQ 2 , a p-channel transistor T 50 , an n-channel transistor T 52  and a further current source IQ 4 . In this case, the second input terminal E 21  is connected between the current source IQ 2  and the transistor T 50 , the fourth input terminal E 41  is connected between the transistor T 52  and the current source IQ 4 , and the second output terminal AP 1  is connected between the transistors T 50  and T 52 . The gate terminals of the transistors T 50 , T 54  are connected to a common drive potential VBP and the gate terminals of the transistors are connected to a common drive potential VBN. The drive potentials VBP, VBN are chosen suitably here in order to set the operating points of the transistors T 50 , T 52 , T 54 , T 56 . 
     Since differential amplifiers having n-channel transistors and differential amplifiers having p-channel transistors usually have different gains, this can adversely affect the suppression of common-mode interference signals respectively superposed on the input signals VIP, VIM in the case of two such differential amplifiers being connected up to form differential amplifier pairs of an A/D converter in accordance with the exemplary embodiments 3 and 4. FIG. 6 shows an exemplary embodiment of an A/D converter according to the invention in which such problems are reduced, in other words the common-mode interference signal suppression is improved. The A/D converter in accordance with FIG. 6 has a current regulating arrangement SRA, which in each case provides a regulating signal RP for driving the current sources in differential amplifiers having p-channel transistors and a regulating signal RN for driving the current sources in differential amplifiers having n-channel transistors. 
     The current sources IP 11 , IP 21  in the differential amplifiers DP 11 , DP 12 , DP 23 , DP 24  to which the drive signal RP is fed are, in the simplest case, p-channel transistors whose load paths are connected up between the supply potential Vdd and the source terminals of the first and second transistors in the respective differential amplifier, the control signal RP being present at the gate terminal of the transistor used as current source. The current sources IN 11 , IN 21  of the differential amplifiers DN 13 , DN 14 , DN 21 , DN 22  to which the regulating signal RN is fed are correspondingly designed as n-channel transistors in the simplest case, the regulating signal RN being fed to the gate terminals of said transistors. 
     By means of the control signals RN, RP, the current regulating arrangement SRA controls the current flow of the current sources in such a way that the transconductance of the differential amplifier transistors connected to a current source is in each case proportional to the reciprocal of a constant resistance. The driving of the current source by means of the current regulating arrangement SRA means that both the p-channel transistors and n-channel transistors have the same transconductance, with the result that the differential amplifiers of a differential amplifier pair have the same gain in each case. 
     A current regulating arrangement SRA of this type belongs to the prior art and is described for example in Wai-Kai Chen: “The circuit and filters handbook”, CRC press 1995, FIG. 57.56, page 1686. FIG. 7 shows an exemplary embodiment of a further current regulating arrangement SRA for providing the regulating signal RN for the current sources IN 21 , IN 11  comprising n-channel transistors. This current regulating arrangement SRA has two n-channel transistors T 62 , T 66 , whose source terminals are connected to reference-ground potential GND. The gate terminal of the transistor T 66  is connected to the drain terminal of the transistor T 62  and the gate terminal of the transistor T 62  is connected to its drain terminal via a resistor R. A current mirror comprising p-channel transistors T 60 , T 64 , whose source terminals are connected to a supply potential V+ and which have a current ratio of 1:1, brings about identical currents I through the transistors T 62 , T 66 . The current ratio of the transistors T 62  and T 66  is 1:A in this case. 
     A further p-channel current mirror transistor T 68 , whose current ratio to the transistors T 60 , T 64  is 2:1, is connected in series with an n-channel transistor T 70 . The source terminal thereof is connected to reference-ground potential GND and the gate terminal thereof is connected to its drain terminal. The gate potential of this transistor T 70  serves as drive signal RN, that is to say as gate potential for the MOS transistors which are used as current sources and of which the current sources IN 11 , IN 21  are illustrated by way of example in FIG.  7 . 
     A current regulating arrangement for driving the current sources of the differential amplifiers having p-channel transistors can be produced in a corresponding manner from the current regulating arrangement in accordance with FIG. 7 if the p-channel transistors are replaced by n-channel transistors, and vice versa, and if the connecting terminals for the supply potentials are interchanged. 
     Ideally, the current sources of the differential amplifiers are driven in a manner dependent on the respective reference potential to which the differential amplifier is connected. This is indicated in FIG. 8 by the fact that the current sources are connected to the respective reference potential. 
     By virtue of the driving of the current sources in a manner dependent on the reference potential, the gain of the differential amplifiers of a differential amplifier pair can be regulated more accurately than in the embodiment in accordance with FIG. 7, in order thus to attain a gain of the differential amplifiers which comes nearer to a predetermined desired value than in the embodiment in accordance with FIG.  7 . For a circuitry realization of a regulating arrangement, it suffices, in the regulating loop which is disclosed in the abovementioned publication and sets the transconductance of a MOS transistor proportionally to the reciprocal of a resistance, to operate the respective MOS transistor at source and drain voltages which the MOS transistors of the differential amplifier whose current source is intended to be regulated have in the state of equilibrium. Such a state is established when the respective reference potential is fed to the gate of the MOS transistor which is regulated by the current regulating arrangement and is used as current source. 
     Differential amplifier pairs each having a differential amplifier having n-channel transistors and a differential amplifier having p-channel transistors are always represented in the exemplary embodiments in accordance with FIGS. 3,  4  and  8 , which each show A/D converters having two input stages. FIG. 9 shows a further exemplary embodiment of an A/D converter according to the invention, in which differential amplifier pairs having complementary differential amplifiers DP 11 , DN 21 , DN 14 , DP 24  are used only for processing the lowest reference potentials VRP 1 , VRM 4  and the highest reference potentials VRP 4 , VRM 1 . The remaining differential amplifier pairs each comprise two differential amplifiers DN 13 , DN 23 , DN 12 , DN 22  having two n-channel transistors in each case. Switches SM 1 , SM 4  for diverting the output currents of the complementary differential amplifiers, as were explained with reference to FIGS. 4 and 5, are accordingly provided only in the case of differential amplifier pairs having complementary differential amplifiers. In the differential amplifier pairs having two differential amplifiers comprising n-channel transistors, it is respectively the case that, as known from the prior art, outputs of the differential amplifier of the first input stage and outputs of the differential amplifier of the second input stage are connected to one another and to load terminals. 
     Although the A/D converter according to the invention has been explained using a 4-bit converter, the invention is not, of course, restricted thereto. The A/D converter shown in the figures can have virtually any desired number of differential amplifiers or differential amplifier pairs which are connected up in the manner shown in the figures. In the case of high-resolution A/D converters, the further circuit of the A/D converter for evaluation of the potentials at the output terminals of the differential amplifiers can also comprise so-called convolution stages of a convolution A/D converter, downstream of which comparators are again connected. 
     In order to improve the output conductance, it is possible to insert further transistors as cascodes in the circuit paths beginning at the drain terminal of the transistors. 
     It goes without saying that the present invention is not restricted to the use of MOS transistors. The differential amplifiers can equally be realized for example by means of NPN bipolar transistors instead of the n-channel MOS transistors and by means of PNP bipolar transistors instead of the p-channel MOS transistors. 
     List of Reference Symbols 
     A 11 , A 21  First output terminals of the differential amplifiers 
     A 12 , A 22  Second output terminals of the differential amplifiers 
     AMx, APx Output terminals of the switching means 
     AN 11 , AN 21  First output terminals 
     AN 12 , AN 22  Second output terminals 
     AP 11 , AP 21  First output terminals 
     AP 12 , AP 22  Second output terminals 
     DN 21 , DN 22 , DN 13 , DN 14  Differential amplifiers having n channel transistors 
     DP 11 , DP 12 , DP 23 , DP 24  Differential amplifiers having p-channel transistors 
     DV 11 , DV 12 , DV 13 , DV 14  Differential amplifiers of the first input stage 
     DV 21 , DV 22 , DV 23 , DV 24  Differential amplifiers of the second input stage 
     E 1   x , E 2   x , E 3   x , E 4   x  Input terminals of the switching means 
     EN 11 , EN 21  First input terminals 
     EN 12 , EN 22  Second input terminals 
     EP 11 , EP 21  First input terminals 
     EP 12 , EP 22  Second input terminals 
     GND Reference-ground potential 
     IN 11 , IN 21  Current sources 
     IP 11 , IP 21  Current sources 
     IQ 1 , IQ 2 , IQ 3 , IQ 4  Current sources 
     M 1 , M 2 , M 3 , M 4  Second input terminals of a comparator 
     P 1 , P 2 , P 3 , P 4  First input terminals of a comparator 
     R Resistor 
     R 11 , R 12 , R 13 , R 14 , R 15  Resistors 
     R 21 , R 22 , R 23 , R 24 , R 25  Resistors 
     RL 1 , RL 2  Load resistors 
     RL 11 , RL 22 , RL 12 , RL 22 , 
     RL 13 , RL 23 , RL 14 , RL 24  Load resistors 
     RN Second regulating signal 
     RP First regulating signal 
     SM 1 , SM 2 , SM 3 , SM 4  Switching means 
     SRA Current regulating arrangement 
     T 11 , T 21  First transistors 
     T 12 , T 22  Second transistors 
     T 50 , T 54  p-channel transistors 
     T 52 , T 56  n-channel transistors 
     T 60 , T 64 , T 68  p-channel transistors 
     T 62 , T 66 , T 70  n-channel transistors 
     TN 11 , TN 21  First n-channel transistors 
     TN 12 , TN 22  Second n-channel transistors 
     TP 11 , TP 21  First p-channel transistors 
     TP 12 , TP 22  Second p-channel transistors 
     V+ Second supply potential 
     Vdd First supply potential 
     VIP First input signal 
     VRM 1 , VRM 2 , VRM 3 , VRM 4  Reference potentials 
     VRP 1 , VRP 2 , VRP 3 , VRP 4  Reference potentials