Abstract:
A multiple gain state amplifier that provides advantageous port matching, noise characteristics, and current savings while not imposing a phase shift in the amplifier transfer function between gain states. A multiple gain state amplifier according to the present teachings includes amplifier circuit configured for a first gain state using a first transistor and configured for a second gain state using a second transistor and a circuit for changing the amplifier circuit between the first gain state and the second gain state by selectively applying a bias to the first transistor and a bias to the second transistor.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention pertains to the field of electronic amplifiers. More particularly, this invention relates to amplifiers having multiple gain states. 
     2. Art Background 
     It is often desirable in a variety of electronic systems to employ an amplifier that is capable of multiple gain states. For example, it is often desirable in a radio receiver to employ an amplifier having a high gain state that may be used when a received signal is relatively weak and a low gain state that may be used when a received signal is relatively strong. Such changes in received signal strength may be caused, for example, by movement of a mobile radio to different distances relative to its base station. 
     Some prior multiple gain state amplifiers employ an attenuator and a switch that opens and closes to add or remove the attenuator from an input signal path to the amplifier. Unfortunately, such prior amplifiers usually suffer from the excessive noise and signal loss caused by the switch. Moreover, such prior amplifiers typically consume full electrical current in both the high and low gain states which may cause excessive power consumption in a mobile device. 
     Other prior multiple gain state amplifiers employ a bypass switch to route an input signal directly from the input to the output of the amplifier to provide the low gain state. Typically, such a bypass switch arrangement causes a 180-degree phase shift in the transfer function of the amplifier between high and low gain states. Unfortunately, such an abrupt phase shift when it occurs in digital communications typically causes undesirable phase changes in a base band data stream. Moreover, such prior amplifier usually imposes difficulties in maintaining an impedance match at the amplifier input/output ports. 
     Still other prior multiple gain state amplifiers employ mechanisms for switching the gain of the amplifier by switching different values of series or shunt feedback resistance, bias voltages, etc. Unfortunately, such techniques typically have an undesirable impact on input and output port impedance match. 
     Other prior multiple gain state amplifiers employ multiple amplifiers and switches for switching an input signal path among the amplifiers. Unfortunately, such amplifiers typically suffer from the excessive noise and signal loss caused by the switches. In addition, such techniques typically increase the hardware costs due to the presence of the additional amplifiers and related components. 
     SUMMARY OF THE INVENTION 
     A multiple gain state amplifier is disclosed that provides advantageous port matching, noise characteristics, and current savings while not imposing a phase shift in the amplifier transfer function when gain states are changed. A multiple gain state amplifier according to the present teachings includes amplifier circuit configured for a first gain state using a first transistor and configured for a second gain state using a second transistor and a circuit for changing the amplifier circuit between the first gain state and the second gain state by selectively applying a bias to the first transistor and a bias to the second transistor. 
     Other features and advantages of the present invention will be apparent from the detailed description that follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is described with respect to particular exemplary embodiments thereof and reference is accordingly made to the drawings in which: 
         FIG. 1  shows a multiple gain state amplifier according to the present teachings; 
         FIG. 2  shows the biasing elements in one embodiment of a multiple gain state amplifier according to the present teachings. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a multiple gain state amplifier  10  according to the present teachings. The multiple gain state amplifier  10  in one embodiment provides two gain states—a high gain state and a low gain state. The present teachings may nevertheless be extended to amplifiers with more than two gain states. 
     The multiple gain state amplifier  10  is configured for a cascode topology that includes a transistor Q 3  together with either a transistor Q 1  or a transistor Q 2 . An on/off state of a switch S 1  determines whether the transistor Q 1  or the transistor Q 2  is active in the cascode arrangement. 
     The transistor Q 1  is biased by a bias circuit  12  and the transistor Q 2  is biased by a bias circuit  14 . The transistor Q 1  is a relatively large transistor in comparison to the transistor Q 2 . The bias circuit  12  is configured to bias the transistor Q 1  to a substantially higher current level in comparison to the current level to which the bias circuit  14  is configured to bias the transistor Q 2 . 
     The multiple gain state amplifier  10  is set to a high gain state by opening the switch S 1 . When the switch S 1  is open and when the bias from bias circuit  14  is shut down, a bias voltage Vb 2  from the bias circuit  14  is removed and the transistor Q 2  is inactive. Thus, when the switch S 1  is open the cascode is composed of the transistors Q 1  and Q 3  along with the bias circuit  12  that applies a bias voltage Vb 1  to the transistor Q 1 . This configuration that includes the relatively large and high current state of the transistor Q 1  provides a relatively high gain cascode amplifier between an input node  16  to an output node  18  of the multiple gain state amplifier  10 . 
     The multiple gain state amplifier  10  is set to a low gain state by closing the switch S 1  and turning off the bias voltage Vb 1  and turning on the bias voltage Vb 2 . Under these circumstances the transistor Q 1  is switched off and is effectively absent from the circuit and the signal at the input node  16  is coupled to the transistor Q 2  through the switch S 1  and the capacitor C 1 . This selects the transistor Q 2  to form a cascode with the transistor Q 3  which yields a relatively low gain because the transistor Q 2  is substantially smaller than the transistor Q 1  and is biased to a substantially lower current. Residual gain may be reduced via a load Z 1  which may be a shunt resistor. This low gain state still provides a 180 degree phase shift between the input and output nodes  16  and  18  as does the high gain state so that the transfer phase of the multiple gain state amplifier  10  in each state is substantially similar. 
     Given its cascode topology the output impedance of the multiple gain state amplifier  10  is largely determined by the characteristics of the transistor Q 3  which does not change substantially between the high and low gain states. 
     When the switch S 1  is open, no switching element is in the signal path between the input and output nodes  16  and  18 . Thus the noise of the multiple gain state amplifier  10  is not adversely effected by the presence of the low gain circuitry as are prior art multiple gain state amplfiers. Judicious choices of transistor sizes, bias currents, feedback, and matching networks may be used to optimize the noise figure, gain, port match, linearity, and current consumption of the multiple gain state amplifier  10 . The transistor Q 2  is chosen to be smaller in size than the transistor Q 1 , and the bias voltage Vb 2  is adjusted to produce greatly reduced current in the transistor Q 3  compared to the high gain state. The load Z 1  is optional and is positioned at the input of the multiple gain state amplifier  10  to restore input port match and to mitigate the small amount of gain provided by the transistor Q 2 . 
     The cascode topology in the multiple gain state amplifier  10  provides a relatively stable port match at the output node  18  in the high and low gain states. The multiple gain state amplifier  10  exhibits substantially zero phase shift difference between the high and low gain states because each state functions as an active amplifier with substantially the same topology. The input compression point may be very similar in both high and low gain states if the gain and current consumption are made to drop by the same ratio. This is because the output compression point drops by the ratio of the current consumption, and the reduction in gain preserves the input compression point. It is the input compression point that is relevant to receive chain linearity. 
     The sources of the transistors Q 1  and Q 2  may be tied together directly to ground or through inductors. 
       FIG. 2  shows the bias circuits  12  and  14  in one embodiment of the multiple gain state amplifier  10 . Each bias circuit  12 – 14  in this embodiment is arranged as a current mirror circuit. The current mirror elements in the bias circuit  12  include a transistor Q 4  and a pair of resistors R 2 –R 3 . The current mirror elements in the bias circuit  14  include a transistor Q 5  and a pair of resistors R 4 –R 5 . The impedance Z 1  is shown as resistor R 1 . 
     The multiple gain state amplifier  10  in this embodiment includes a switch S 2  for switching on/off the bias supply Vb 2  from the bias circuit  14 . The switching of the bias circuit  12  is accomplished automatically by the switch S 1  and the resistor R 1 . When the switch S 1  is closed, R 1  effectively shorts out the bias supply Vb 1  from the bias circuit  12 . The shorting out of the bias supply Vb 1  from the bias circuit  12  may be enhanced by selecting the resistor R 2  to have a substantially greater value than the resistor R 1 . The actuation of the switches S 1  and S 2  may be coordinated so as to switch together in complementary fashion. 
     The switches S 1  and S 2  may be implemented as field effect transistors (FETs) or some other type of device. The transistors Q 1 –Q 5  may be FETs or bipolar junction transistors (BJTs). 
     The multiple gain state amplifier  10  yields no substantial degradation of a noise figure in the high gain state while providing a good impedance port match in the high and low gain states. Moreover, the multiple gain state amplifier  10  yields a high degree of electrical current savings in the low gain state with no phase change between the input and output ports between the high and low gain states. 
     The foregoing detailed description of the present invention is provided for the purposes of illustration and is not intended to be exhaustive or to limit the invention to the precise embodiment disclosed. Accordingly, the scope of the present invention is defined by the appended claims.