Abstract:
A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based on Japanese Patent Application No. 2007-277209 filed on Oct. 25, 2007, and the contents of which are hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an electric circuit associated with transmission of a clock signal and a method for designing the electric circuit. 
         [0004]    2. Description of Related Art 
         [0005]    Conventionally, electronic equipment including a personal computer or the like uses a memory device of a standard such as Double Data Rate 2 (DDR2) SDRAM, for instance. A plurality of such memory devices may be disposed in electronic equipment for a purpose of securing sufficient memory capacity or other purposes. A schematic structure of an example of the electric circuit having such the structure is shown in  FIG. 2 . 
         [0006]    The electric circuit includes a control IC  101  and a plurality of (e.g., four) SDRAMs  102   a  to  102   d,  which are connected to each other via wirings  103  and  104 . In addition, the control IC  101  is provided with a clock signal output portion  111  for outputting a predetermined clock signal and a data input and output portion  112  for supplying or receiving various data to or from the SDRAMs  102   a  to  102   d.    
         [0007]    Such the electric circuit enables the SDRAMs  102   a  to  102   d  to read or write data in synchronization with a clock signal (external clock) that is sent from the clock signal output portion  111  via the wiring  103 . Note that the clock signal is delivered from the clock signal output portion  111  and is imparted to the SDRAMs  102   a  to  102   d  after branching at a branch node  103   b.    
         [0008]    In addition, the data input and output portion  112  is supplied with the clock signal from the clock signal output portion  111  and performs input and output of data from or to the SDRAMs  102   a  to  102   d  via the wiring  104  in synchronization with the clock signal. 
         [0009]    Noting an operation of writing data in the SDRAMs  102   a  to  102   d,  for instance, it is desirable that the writing operation should be performed in the SDRAMs  102   a  to  102   d  at timings delayed as little as possible from the timing when the data to be written reaches the SDRAMs  102   a  to  102   d  via the wirings  104 . 
         [0010]    However, even if a clock signal that is common to individual operations is used, there may be the case where a time difference occurs between the time period from reception of the clock signal by the data input and output portion  112  until arrival of the data at the SDRAMs  102   a  to  102   d  via the wiring  104  and the time period until reception of the clock signal by the SDRAMs  102   a  to  102   d  via the wiring  103 , due to a delay time of transmission. 
         [0011]    Therefore, when such the electric circuit is designed, a wiring length adjustment portion  103   a  is disposed at each branch of the individual wirings  103  as shown in  FIG. 2 . This wiring length adjustment portion  103   a  is disposed for adjusting the length of the wiring  103  so as to adjust transmission delay time of the clock signal (the longer the wiring, the longer the delay time is). According to the wiring length adjustment portion  103   a  shown in  FIG. 2 , a meandering pattern is adopted so that the wiring  103  is adjusted to be longer intentionally and that the transmission delay times of the clock signal to the SDRAMs  102   a  to  102   d  are increased. 
         [0012]    Thus, it is possible to minimize the time difference by adjusting the wiring lengths as described above, so that the operation of writing data in the SDRAMs  102   a  to  102   d  can be performed more appropriately. Note that the documents below disclose conventional techniques in the art of the present invention. 
         [0013]    JP-A-2004-110103 
         [0014]    JP-A-2000-267756 
         [0015]    JP-A-2006-54348 
         [0016]    JP-A-2000-122751 
         [0017]    JP-A-2000-148282 
         [0018]    However, if it is necessary to increase the length of the wiring length adjustment portion  103   a  in the case where the wiring length adjustment portion  103   a  is disposed at each branch as described above, it is necessary to increase all the plurality of wiring lengths  103   a  of the individual branches. Therefore, the entire length of the wiring  103  becomes very long, so that power loss will increase due to an increase in wiring resistance. As a result, quantity of current of the clock signal to be supplied to the SDRAMs  102   a  to  102   d  may be insufficient. 
         [0019]    If the quantity of current of the clock signal is insufficient, it causes drop of an amplitude level of the clock signal or deterioration of a waveform of the clock signal, so that the clock signal cannot be transmitted accurately. Therefore, a malfunction may occur in writing or the like of the data in the SDRAMs  102   a  to  102   d.    
       SUMMARY OF THE INVENTION 
       [0020]    An object of the present invention is to provide an electric circuit and a method for designing the electric circuit that enable to adjust lengths of wirings for transmitting a clock signal to a plurality of processing circuits (e.g., SDRAMs) and still enable to shorten a total length of the wirings. 
         [0021]    A designing method of an electric circuit according to the present invention includes a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. 
         [0022]    According to this method, the length of the wirings for clock transmission can be set to be a predetermined length. Therefore, a delay time in transmission of the clock signal can be adapted to be a predetermined time. In addition, this setting can be realized by connecting the first point to the clock output circuit by a single wire having the remaining length. As a result, even if a relatively long wiring is required to realize this setting, it is sufficient to increase the length of the single wire. Therefore, it is possible to shorten the entire length of the wirings for transmitting the clock compared with the case where the individual wirings after the branch are required to have increased lengths. 
         [0023]    Further in the above-mentioned designing method, the predetermined length may be the length such that a delay time of the clock signal due to transmission from the clock output circuit to the processing circuit via the wirings for clock transmission becomes a predetermined time. This method enables adjustment of a delay time of the clock signal in the processing circuit to be a predetermined time. 
         [0024]    Further in the above-mentioned designing method, the electric circuit also includes a data output circuit for receiving the clock signal from the clock signal output circuit so as to transmit data to the processing circuit in synchronization with the clock signal, the processing circuit is a memory circuit for writing the transmitted data in synchronization with the clock signal, and the predetermined time is substantially the same as the time from output of the clock signal by the clock signal output circuit to arrival of the data at the processing circuit. 
         [0025]    According to this method, the clock signal and the data can be transmitted to the processing circuit (memory circuit) substantially at the same time. Therefore, a process of writing data in the memory circuit can be performed appropriately. 
         [0026]    Further in the above-mentioned designing method, the wirings for clock transmission may include a branch node disposed between the first point and the processing circuit, and the processing circuit may be disposed at each branch after the branch node. 
         [0027]    According to this structure, wiring lengths after the branch node can be further shortened in the case where the processing circuits are disposed closely or in other cases. 
         [0028]    In addition, more specifically as the above-mentioned designing method, the single wire may be disposed in a meandering manner, and each of the processing circuits may be a DDR2 SDRAM. Furthermore, an electric circuit designed by the above-mentioned designing method and an electrical apparatus equipped with the electric circuit are also useful. 
         [0029]    In addition, an electric circuit according to the present invention includes a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The wirings for clock transmission is connected by a single wire between the clock output circuit and a certain point (as a “first point”) on the electric circuit, and is further connected between the first point and the individual processing circuits by a plurality of wirings branching from the first point so that the wirings have substantially the same length, and the length of the single wire is adjusted so that a delay time of the clock signal due to transmission from the clock output circuit to the processing circuit via the wirings for clock transmission becomes a predetermined time. 
         [0030]    According to this structure, a delay time of the clock signal in the processing circuit can be adapted to be a predetermined time. In addition, since the length of the single wire is adjusted, it is possible to shorten the entire length of the wirings (or decrease power loss) compared with the structure in which lengths of individual wirings after the branch node (after the first point) are adjusted, so that it is easy to avoid insufficient quantity of current of the clock signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]    The above-mentioned and other objects and features of the present invention will be apparent from the following description about a preferred embodiment with reference to the attached drawings as below. 
           [0032]      FIG. 1  is a structural diagram of an electric circuit according to an embodiment of the present invention. 
           [0033]      FIG. 2  is a structural diagram according to an example of a conventional electric circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0034]    Now, an embodiment of the present invention will be described concerning an electric circuit having a structure shown in  FIG. 1 . As shown in this diagram, an electric circuit  9  includes a control IC  1  and four SDRAMs (Synchronous DRAMs)  2   a  to  2   d ). In addition, the control IC includes a clock signal output portion  11  and a data input and output portion  12 . 
         [0035]    The clock signal output portion  11  generates a clock signal having a predetermined frequency, which is transmitted to the data input and output portion  12 , the individual SDRAMs  2   a  to  2   d,  and the like. Note that the transmission of the clock signal to the individual SDRAMs  2   a  to  2   d  is performed via the wiring  3  that connects them with each other. 
         [0036]    The data input and output portion  12  performs input and output of various data with respect to the SDRAMs  2   a  to  2   d.  The input and output of data is performed via the wirings  4  that connect them with each other. In addition, this input and output operation is performed in synchronization with the clock signal supplied from the clock signal output portion  11 . 
         [0037]    The SDRAMs  2   a  to  2   d  to be used are ones of Double Data Rate 2 (DDR2) SDRAM standard, for instance, in which various data are read or written in synchronization with an external clock (here, a clock signal transmitted from the clock signal output portion  11 ). 
         [0038]    According to the electric circuit having the structure described above, the data is written in the SDRAMs  2   a  to  2   d  in synchronization with the clock signal when the data input and output portion  12  delivers data to the SDRAMs  2   a  to  2   d.  Thus, the SDRAMs  2   a  to  2   d  can store the data. 
         [0039]    Here, noting the layout state of the wiring  3 , it is a single line from the clock signal output portion  11  to a first branch node  3   b.  In addition, after the branch node  3   b  it branches into lines including a line directed to the SDRAMs  2   a  and  2   b  and a line directed to the SDRAMs  2   c  and  2   d.    
         [0040]    Furthermore, it branches into a line directed to the SDRAM  2   a  and a line directed to the SDRAM  2   b  at a branch node  3   c.  In the same manner it branches into a line directed to the SDRAM  2   c  and a line directed to the SDRAM  2   d  at a branch node  3   d.  In other words, it can be regarded that each of the SDRAMs  2   a  to  2   d  is connected to the clock signal output portion  11  in a so-called tree structure (or in a two-branch tournament structure). 
         [0041]    In addition, the wiring from the branch node  3   b  to the SDRAM  2   a  via the branch node  3   c,  the wiring from the branch node  3   b  to the SDRAM  2   b  via the branch node  3   c,  the wiring from the branch node  3   b  to the SDRAM  2   c  via the branch node  3   d,  and the wiring from the branch node  3   b  to the SDRAM  2   d  via the branch node  3   d  are designed to have substantially the same length. In other words, wirings from the first branch node  3   b  to the individual SDRAMs  2   a  to  2   d  have substantially the same length. Furthermore, the single wiring from the clock signal output portion  11  to the branch node  3   b,  i.e., the wiring upstream the branch node  3   b  has a wiring length adjustment portion  3   a.    
         [0042]    This wiring length adjustment portion  3   a  is a portion whose wiring length is adjusted arbitrarily in a designing stage of the circuit, and it has a meandering pattern as shown in  FIG. 1 , for instance. This pattern facilitates to adjust the length of the single line wiring by changing a width and/or intervals of the meandering pattern without changing a position of the clock signal output portion  11  and the branch node  3   b.    
         [0043]    The wiring length adjustment portion  3   a  is not limited to the form described above but can have various forms. Thus, in the designing stage of the circuit, delay times of the clock signal to be transmitted to the individual SDRAMs  2   a  to  2   d  can be adjusted easily via a length of the wiring  3 . Note that a delay time of a signal to be transmitted through a wiring is longer as the wiring is longer as understood well. 
         [0044]    This adjustment of the wiring length by the wiring length adjustment portion  3   a  enables to set the time necessary for the data corresponding to the clock to reach the SDRAMs  2   a  to  2   d  via the wiring  4  after the clock output by the clock signal output portion  11  to be substantially the same as the time for the clock to reach the SDRAMs  2   a  to  2   d  via the wiring  3 . In other words, the wiring length in the wiring length adjustment portion  3   a  is adjusted so that the time necessary for the data to reach the SDRAMs  2   a  to  2   d  with respect to the clock output timing by the clock signal output portion  11  becomes the same as the time necessary for the clock signal to reach. 
         [0045]    Since the arrangement and the form of the wiring  3  are set as described above, the electric circuit  9  can perform the process for writing data into the SDRAMs  2   a  to  2   d  in synchronization with the clock signal appropriately. 
         [0046]    Next, a method for designing the above-mentioned electric circuit  9  will be described. Here, an arrangement of the control IC  1 , the individual SDRAMs  2   a  to  2   d  and the wiring  4  for transmitting data is determined in advance. 
         [0047]    First, the individual SDRAMs  2   a  to  2   d  and the point to be a first branch node (hereinafter referred to as a “first point”) in the electric circuit  9  (corresponding to the branch node  3   b ) are connected to each other via the wiring. In this case, the wiring lengths from the first point to the individual SDRAMs  2   a  to  2   d  are adapted to be substantially the same. In addition, although the position of the first point can be arbitrary, it is preferable to be a position that enables the wiring length from the first point to the individual SDRAMs  2   a  to  2   d  to be as short as possible. 
         [0048]    In addition, when they are connected actually, branch nodes ( 3   c  and  3   d ) as shown in  FIG. 1  may be disposed appropriately, so that SDRAMs  2   a  to  2   d  can be arranged at the branches, respectively. Thus, it is possible to shorten the entire length (total sum of the lengths) of the wirings used for connecting the first point and the SDRAMs  2   a  to  2   d  in the case where the SDRAMs  2   a  to  2   d  are arranged to be close to each other. 
         [0049]    After that, the clock signal output portion  11  and the first point are connected to each other by the single wire. In this case, the length of the single wire is adapted so that a length of the wiring  3  becomes a predetermined target length. In other words, the wiring length adjustment portion  3   a  shown in  FIG. 1  is disposed in the single wire. More specifically, the time from the clock signal output by the clock signal output portion  11  to the arrival of the data at the SDRAMs  2   a  to  2   d  is adapted to be substantially the same as the time necessary for the clock signal to reach in the same manner. 
         [0050]    Note that the target length is grasped in advance by determining the time (T 1 ) from the clock signal output by the clock signal output portion  11  to the arrival of the data at the SDRAMs  2   a  to  2   d  and by calculating the wiring length in the case where the transmission delay time of the clock signal becomes the time T 1 , for instance. In other words, a result of this calculation is regarded as the target length. Note that the time T 1  becomes a total sum of the delay time of the clock signal in the transmission from the clock signal output portion  11  to the data input and output portion  12 , the time necessary for the data input and output portion  12  to deliver data to the SDRAMs  2   a  to  2   d  after receiving the clock signal, the delay time of the data in transmission from the data input and output portion  12  to the SDRAMs  2   a  to  2   d,  and delay times due to other factors. 
         [0051]    In addition, the wiring length of the wiring length adjustment portion  3   a  is adjusted in advance so that the length of the single wire connecting the clock signal output portion  11  with the first point becomes the length that is obtained by subtracting the length of the wiring connecting the first point with the SDRAMs  2   a  to  2   d  from the above-mentioned target length (remaining length). 
         [0052]    The above-mentioned adjustment of the wiring length in the wiring length adjustment portion  3   a  can also be regarded as adjustment of the delay time of the clock signal due to transmission from the clock signal output portion  11  to the SDRAMs  2   a  to  2   d  to be a predetermined time. 
         [0053]    The above-mentioned method of designing the electric circuit enables to realize the electric circuit  9  shown in  FIG. 1 . Although wiring extensions for four lines are necessary when the wiring extension is performed by the wiring length adjustment portion  103   a  in the conventional electric circuit shown in  FIG. 2 , the equivalent wiring extension in the electric circuit  9  of this embodiment only requires the wiring extension for one line. Therefore, it can shorten the entire length of the wiring  3  comparing with the conventional electric circuit. In addition, a space necessary for the wiring can be minimized so that a small circuit can be realized. 
         [0054]    Although an example of the embodiment of the present invention is described above, the embodiment of the present invention is not limited to this example but can be modified variously without deviating from the scope of the present invention. In addition, although the SDRAMs are exemplified as devices that receive the clock signal in this embodiment, they can be other devices that perform processes based on the clock signal. In addition, the electric circuit of this embodiment can be applied widely to an electrical apparatus such as a personal computer. 
         [0055]    Note that the length of the wiring for transmitting the clock can be adopted to be a predetermined length according to the method of designing the electric circuit according to the present invention. Therefore, it is possible to set the delay time in transmission of the clock signal to be a predetermined time. In addition, this setting can be realized by connecting the first point to the clock output circuit by the single wire having the remaining length. As a result, even if a relatively long wiring is required to realize this setting, it is sufficient to increase the length of the single wire. Therefore, it is possible to shorten the entire length of the wirings for transmitting the clock compared with the case where the individual wirings after the branch are required to have increased lengths.