Abstract:
In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.

Description:
FIELD OF THE INVENTION 
     The invention relates to the programming of circuit blocks that need to be programmed once only. In particular it relates to the field of fuse cells. 
     BACKGROUND OF THE INVENTION 
     For a number of analog applications a programmable block is required, e.g., in the case of a programmable I/O. 
     One approach that has been adopted in the past is the use of EEPROM cells. The disadvantage of EEPROMs, however, is that they require additional complex programming circuitry and also consume a substantial amount of space. 
     An alternative that has been used in the past in cases where the block needs to be programmed only once, is to make use of fuses. These fuse cells, in contrast to EEPROM cells provide a close to minimum dimension poly resistor. However, they are programmed by burning the fuse cell out using a CMOS switch circuit. In the case of on-chip programming, this requires a rather complex pulsed switch circuit and a sophisticated process to ensure reliable burn out of the fuse cell. 
     The present application seeks to provide another solution to the problem. 
     SUMMARY OF THE INVENTION 
     According to the invention, there is provided an anti-fuse type fuse cell based on an irreversible snapback device such as an NMOS or NPN bipolar transistor or SCR. In particular, the fuse cell includes an NMOS, NPN or SCR that has snapback capability but where the snapback is irreversible, and which is connected between the power supply (VDD) and ground to create a current path to ground prior to programming, and a high resistance path to ground after programming. Typically, prior to programming, the control electrode of the device is connected to a potential that avoids the device being pushed into snapback mode. For purposes of programming, the control electrode is connected to a high enough potential, e.g. VDD, to cause the device to go into snapback mode. 
     Further, according to the invention, there is provided a method of providing an programmable circuit, comprising providing a snapback NMOS or NPN or SCR device that is not capable of reversible snapback, connecting the device between a power supply (VDD) and ground, and controlling the control electrode bias to cause the device to go into snapback mode. The control electrode may be connected to a high voltage such as VDD to cause it to go into snapback mode. Preferably the high voltage to the control electrode is applied as a pulse. The device may be connected to VDD through a resistor to provide a low output while the device is in a conductive state, and a high output once the device has gone into irreversible snapback mode. The output may be connected to an inverter to provide an inverted, buffered output. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is one embodiment of a programmable circuit of the invention, and 
         FIG. 2  is a set of V-I curves for an NMOS transistor under different gate bias conditions. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows one embodiment of a programmable circuit of the invention. 
     The circuit  100  is based on the use of a snapback transistor  102  that burns out when forced into snapback mode. In other words it is a snapback device without reversible snapback capability. The snapback of the device is controlled by controlling the bias of the control electrode  104 . In this embodiment, the transistor  102  is an NMOS transistor and the control electrode  104  is the gate of the NMOS transistor  102 . However, an NPN bipolar transistor could be used in place of the NMOS  102 , in which case the base of the device would be the control electrode that would be biased to control the snapback of the device. It will also be appreciated that the circuit could be reconfigured to make use of an SCR instead. In each case the control electrode bias is controlled to cause the device to go into snapback mode. The high voltage electrode (drain or collector) which is connected to the high voltage rail will be referred to generically as the anode. 
     In the present case, prior to programming, the gate  104  is connected to ground through the resistor  106 , thereby maintaining the gate  104  at a low potential that turns the NMOS transistor off, thereby providing a low leakage path. This pulls node  110  high since it is connected to VDD through resistor  112 . Since the node  110  is connected to an inverter  120 , the output  122  will be low prior to programming. In other words, the circuit is pre-programmed to “0”. The NMOS  102  is programmed to “1” by connecting the gate  104  to the power rail (VDD), which causes the NMOS  102  to go into irreversible snapback and burn out. This creates a low resistance (100Ω-1 kΩ) leakage path to ground, thereby pulling the node  110  low and causing the output  122  to go high. VDD is typically applied to the control gate  104  as a pulse, whereafter the gate  114  returns to its pre-program state. However, since the NMOS burns out during snapback, it remains in a low resistance state and leaves the output  122  as a high. The advantage of this circuit is that even if the programming fails the first time, a high voltage pulse can simply be applied to the gate again. 
       FIG. 2  shows the typical drain-source voltage to current characteristics for an NMOS under different gate bias conditions. Without gate bias, curve  200  shows the device snapping back at about 8.7V. With a gate bias of 1V (curve  202 ), the snapback voltage is reduced to about 7.5 V. At gate bias voltages of 2V (curve  204 ) and 3V (curve  206 ), the snapback occurs at about 5V and 4.5V, respectively. 
     As mentioned above, in the case of an NPN transistor the circuit is much the same as in  FIG. 1 , but the high voltage pulse is applied to the base of the transistor. In the case of an SCR, the high voltage pulse is applied to the gate of the device.