Abstract:
A multiple tap attenuator microchip device is disclosed. The device includes a substrate having two or more attenuator taps formed on a surface of the substrate. One or more ground contacts are also formed on the substrate surface and operatively connected to the attenuator taps. The attenuator taps each include a resistive network that is configured to provide a level of attenuation of an rf signal applied to the attenuator tap that is different from the attenuation level provided by the other attenuator tap(s).

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to chip devices for electronic systems that are operational to modify microwave signals. In particular, the invention relates to a device for the attenuation of an input microwave signal to a fixed power level. 
     2. Description of the Related Art 
     Fixed-chip attenuators are designed to attenuate a signal to a fixed power level. Attenuators are commonly used in communication and audio devices, which often have strict size requirements. Multiple levels of attenuation typically require multiple separate attenuation devices. Until now, it was not believed to be possible to provide multiple levels of attenuation on a single chip because of interference that adversely affects the quality of signals in closely adjacent attenuators. The need to use separate different devices to accomplish multiple levels of attenuation is an inefficient use of available space in an electronic device. In view of the ever increasing demand for more compactness in large-scale integration (LSI) electronic devices, it would be desirable to have a single microchip device which provides multiple levels of attenuation, but which requires less space than multiple discrete devices. Such a device would allow multiple levels of signal attenuation in a single device. In addition, a switch could be used to allow the user to cycle between various levels of attenuation. 
     SUMMARY OF THE INVENTION 
     The problems associated with making a microchip device that provides multiple levels of signal attenuation are overcome to a large degree by a multiple tap attenuator microchip device according to the present invention. A microchip according to the present invention includes a substrate having a surface. A plurality of input contacts is formed on the surface of the substrate and a plurality of output contacts is also formed on the surface of the substrate separate from the input contacts. A plurality of junction pads is formed on the surface of the device separate from the input pads and the output pads to transmit the signal from the input pads to the output pads. A plurality of resistors, each having a preselected specific resistance value, is formed on the substrate, connecting the input pads to the junction pads. A second plurality of resistors, each having a preselected specific resistance value, is formed on the substrate, connecting the junction pads to the output pads. A third plurality of resistors, each having a preselected specific resistance value, is formed on the substrate, connecting the junction pads to one or more grounding planes. The resistance values of the resistors are selected to provide multiple attenuation levels for a signal input to the device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a perspective view of a step multi-tap attenuator according to the present invention. 
         FIG. 2  is a schematic diagram of a typical T-type attenuator circuit used in the multi-tap attenuator of  FIG. 1 . 
         FIG. 3  is a perspective view of a high-frequency multi-tap attenuator according to the present invention. 
         FIG. 4A  is a front perspective view of an alternate embodiment of a high-frequency multi-tap attenuator according to the present invention. 
         FIG. 4B  is a side elevation view of the embodiment shown in  FIG. 4A . 
         FIG. 5  is a partial schematic diagram of a multi-tap attenuator in combination with a switching system. 
     
    
    
     DETAILED DESCRIPTION 
     The chip device in accordance with the present invention is a chip package that provides multiple levels of attenuation of a signal input to the device. Referring now to the drawings, and in particular to  FIG. 1 , there is shown a first embodiment of a chip device according to this invention. Chip device  100  has a substrate  101  that includes a surface  102 . The substrate is preferably formed of a ceramic material such as alumina. It will be appreciated by those skilled in the art that the substrate may also be formed of other materials such as aluminum nitride, silica, or beryllium oxide. 
     A plurality of attenuation taps  190  are formed on the surface of the substrate. A preferred embodiment of a tap  190  will now be described. Attenuation tap  190  includes an input pad  160  formed on the surface  102  of the substrate  101  along a first side thereof. Output pad  170  is formed on the surface  102  of the substrate  101  along another side thereof that is spaced apart from the input pad  160 . A junction pad  120  is formed on the surface  102  of the substrate  101  at a location that is spaced apart from input pad  160  and output pad  170 . A first resistive element  103  is formed on the surface of the device such that it connects input pad  160  and junction pad  120 . A second resistive element  104  is formed on the surface of the substrate such that it connects junction pad  120  and output pad  170 . A third or shunt resistive element  105  is formed on the surface of the substrate such that it connects junction pad  120  to junction pad  130  in an adjacent attenuation tap. Resistive elements  103 ,  104 , and  105  are formed to have resistance values to provide a desired level of attenuation of a signal that has been input to input pad  160 . A portion of the electrical signal transmitted into the tap  190  is directed to resistor  105 , where it is conducted across the junction pads  130 - 150  via connecting resistors and to grounding plane  180 , which is formed on the surface  102  of the substrate  101 . Multiple taps of this design are printed on the surface of the device in a spaced-apart configuration, varying only in the resistance levels of resistive elements  103 - 105 . Junction pad  120  is connected to junction pad  130  via resistive element  105 . Junction pad  130  is connected to junction pad  140  via resistive element  106 . Junction pad  140  is connected to junction pad  150  via resistive element  107 , and junction pad  150  is connected to ground plane  180  via resistive element  108 . This series of connections between the junction pads  120 - 150  and ground plane  180  provides a ground path for the signal currents that pass through any of the attenuation taps formed on the device. 
     The multiple attenuation taps described above provide the device  100  with the capability to perform multiple, different levels of signal attenuation. The plurality of attenuation taps is arranged such that the attenuator with the lowest attenuation value is positioned the farthest away from grounding plate  180 . This results from the fact that the attenuator with the lowest attenuation value also has the highest value shunt resistor. The input pads  160 , output pads  170 , junction pads  120 ,  130 ,  140 , and  150 , and the grounding plane  180  are all formed of a conductive metal such as gold, platinum, or an alloy thereof. The input pads, output pads, junction pads, and the grounding plane may be plated with a nickel and a solder layer deposited thereon. The conductive material is preferably deposited as a thin film, which will be described more fully below. However, the conductive material can be deposited as a thick film in accordance with known thick-film printing techniques. When using thick films, the input pads, output pads, junction pads, and grounding plane may be formed of a silver-platinum alloy, a silver-palladium alloy, or gold. Metal elements made from gold may be coated with a layer of nickel and then a solder material on top of the nickel layer. 
       FIG. 2  is a schematic diagram of attenuation tap  190 . The first resistive element  103  is connected between input contact  160  and junction pad  120 . The second resistive element  104  is connected between junction pad  120  and output contact  170 . The third resistive element  105  is connected between junction pad  120  and junction pad  130 . In this configuration, the three resistive elements  103 ,  104 , and  105  form an attenuator component on the device. The resistive elements  103 ,  104 , and  105  are formed of an electrically resistive material that is preferably deposited as a thin film on the substrate surface. As in the case of the metal contacts, the resistive elements can be formed by using a thick-film technique. The configuration shown in  FIGS. 1 and 2  is well known as a T-type attenuator. Alternately, a II-type attenuator, which is also well known in the art, may be used. The attenuation tap configuration  190  is identical for each tap, and varies only in the resistive values of the resistors  103 ,  104 , and  105  and which connector pads the resistors are connected to. 
     Referring now to  FIG. 3 , a second embodiment of the multi-tap attenuator according to this invention is shown. Chip device  300  includes a plurality of grounding planes  380  formed in a spaced-apart configuration on the surface  302  of the substrate  301 . The grounding planes  380  are positioned on either side of the signal line, also known as a co-planar attenuator design. A first attenuation tap  320  is formed on the surface  302  of the substrate  301  between first and second grounding planes  380 . First attenuation tap  320  consists of a metallic conductive layer and thus, provides minimal attenuation. Resistive elements  305  and  306  connect the first attenuation tap to the grounding planes  380  to provide a grounding path for the current that passes through attenuation tap  320 . A plurality of additional attenuation taps are formed on the surface  302  of the substrate  301  between respective pairs of grounding planes  380 . For example, a second attenuation tap includes input pad  360  and output pad  370  which are formed on the surface  302  of the substrate  301  in a spaced apart configuration between two of the grounding planes  380 . Junction pad  330  is also formed on the surface  302  of the substrate  301  and is spaced apart from input pad  360  and output pad  370 . A first resistive element  303  is formed on the surface  302  of the substrate  301  such that it connects input pad  360  to junction pad  330 . Resistive element  304  is formed on the surface  302  of the substrate  301  such that it connects junction pad  330  to output pad  370 . Resistive elements  307  and  308  are formed on the surface  302  of the substrate  301  such that they connect junction pad  330  with the two immediately adjacent grounding planes  380 . Each attenuation tap is formed on the substrate in a similar fashion. The resistance values of resistors  303 ,  304 ,  307 , and  308  are selected to provide different levels of attenuation to the user in the attenuation taps. The arrangement shown in  FIG. 3  is useful to prevent cross-talk interference between attenuation taps in high-frequency signal attenuation because each attenuator tap is isolated from the other taps by the intervening grounding planes. This configuration is different from that shown in  FIG. 1  where all of the shunt resistors are tied together to a common ground termination. 
     Referring now to  FIG. 4A , an alternate embodiment of the device of  FIG. 3  is shown. Chip device  400  includes a series of grounding planes  480  formed in a spaced-apart configuration on the outer surface  402  of the substrate  401 . The attenuation taps are formed on the surface  402  and disposed between pairs of grounding strips  480 . In this embodiment, however, the grounding strips  480  wrap around the sides of the substrate and connect to a common ground plane  490  formed on the back surface of the substrate  401  as shown in  FIG. 4B . The grounding strips are formed by a metallization process. Notches are formed in the sides of substrate  401  to restrict the metallization process to the areas that require metallization and to prevent metallization in areas that would result in short circuits. The configuration shown and described with reference to  FIGS. 4A and 4B  permits the device to be inserted into a cavity and have the signal lines leading to the input and output contacts attached with ribbon bonds. 
       FIG. 5  depicts an embodiment of a high-frequency switching system that is designed to allow a user to select among different attenuation levels on the device. A signal is sent from a signal source to high frequency switch  505 . The switch  505  can be embodied with any known high-frequency switch devices. Examples of a suitable switch are described in U.S. Pat. No. 6,118,985 owned by Kabushiki Kaisha Toshiba and in U.S. Pat. No. 6,933,543 assigned to the Electronics and Telecommunication Research Institute. Switch 505 routes the signal to one of taps, where it is attenuated and then output in its attenuated form. This creates a complete path for the signal to travel from signal source, through an attenuator, and out of the device, and allows the signal to be selectively attenuated. 
     A method for making a multi-tap attenuator chip device in accordance with this invention will now be described. The process begins with the selection of an appropriate substrate material. Although the preferred substrate material is alumina, other non-conductive materials can also be used. In this regard, ceramic materials such as aluminum nitride, silica, beryllium oxide, and glass-ceramic composites can be used. 
     A layer of electrically resistive material is deposited on a surface of the substrate. Next, a plurality of layers of electrically conductive material is deposited over the resistive layer. The resistive and conductive layers are preferably deposited as thin films. The deposition steps are performed in a vacuum. A photo-sensitive material known as a photoresist is spin-coated onto the multiple layers. An etch pattern is formed on the photoresist using ultraviolet (uv) lithography, a known technique. The metallic layers are then etched through the patterned photoresist to form the contacts and conductive paths of the chip device. The photoresist is then stripped away and a new coating of photoresist is applied. The second photoresist coating is patterned, again using uv lithography. The resistive material is then dry etched through the openings in the pattern to form the geometries of the resistive elements for each chip. The dry etching is preferably performed by an ion milling technique. The remaining photoresist is then removed. 
     The resistive elements are trimmed to final value by any known technique, preferably by laser trimming. Preferably, the chip device is passivated with a polymer to protect it from contamination or physical damage. The substrate is then scored with a laser and separated into individual chip devices. 
     Although the preferred process has been described as including thin film techniques, the inventors believe that the multi-tap attenuator device according to this invention can be made by thick film printing techniques also. In the case of thick film technology, the substrate is scored or scribed using a laser. Then the conductor patterns are screen printed and sintered onto the substrate surface. Then the resistor patterns are screen printed onto the substrate. A plurality of inks may be used depending on the resistor values desired. 
     The foregoing descriptions are directed to embodiments of a multi-tap attenuator chip device in accordance with the present invention which can be used alone or as building blocks for more complex devices. Thus, the inventors contemplate that the various embodiments described may be combined as needed to provide desired levels of signal attenuation for a particular application. 
     The descriptions presented above are also directed to particular embodiments of a multi-tap attenuator chip in accordance with the present invention. It will be recognized by those skilled in the art that changes or modifications may be made to the above-described embodiments without departing from the broad inventive concepts of the invention. It is understood, therefore, that the invention is not limited to the particular embodiments that are described, but is intended to cover all modifications and changes within the scope and spirit of the invention as described above and set forth in the appended claims.