Abstract:
One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material.

Description:
FIELD OF THE INVENTION 
   One or more embodiments of the present invention relate to semiconductor devices and methods of making semiconductor devices. 
   BACKGROUND OF THE INVENTION 
   In order to direct high-voltages from the on-chip charge pumps to the appropriate Flash cell in an embedded Flash technology, special transistors over and above the standard logic CMOS transistors may be required which are robust in the face of such high voltages. These transistors may suffer from gate-induced drain leakage (GIDL) constraints in the off-state which may be avoided through offsetting the source/drain implants from the gate stack edge. Such offsetting may be accomplished through lithographic means and the accuracy of the offset may thus depend on the overlay of the lithographic process. A new way to provide offsetting is needed. 
   SUMMARY OF THE INVENTION 
   One or more embodiments relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material. 
   One or more embodiments an integrated circuit, comprising: a substrate; a memory device including: a first gate stack disposed over the substrate, the first gate stack comprising a control gate disposed over a charge storage layer, and a polysilcon spacer select gate overlying the substrate, the spacer select gate laterally disposed from the first gate stack; and a field effect transistor including: a second gate stack disposed over the substrate, the second gate stack comprising a gate electrode overlying a gate dielectric, and a polysilicon spacer disposed over the substrate and laterally disposed from the transistor gate stack. 
   One or more embodiments relate to a method of forming an integrated circuit, comprising: providing a substrate; forming a first gate stack for a memory device over a first portion of the substrate; forming a second gate stack for a field effect transistor over a second portion of the substrate; forming a polysilicon layer over the first gate stack and over the second gate stack; and etching the polysilicon layer to form polysilicon sidewall spacers over the sidewalls of the first gate stack and the second gate stack. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1 through 14  provide an embodiment of a method of making an embodiment of a memory device, an embodiment of a first transistor and an embodiment of a second transistor accordance with the present invention; 
       FIG. 15  provides an embodiment of a memory device, an embodiment of a first transistor and an embodiment of a second transistor in accordance with the present invention; and 
       FIG. 16  provides an embodiment of a memory device, an embodiment of a first transistor and an embodiment of a second transistor in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. 
     FIGS. 1 through 14  illustrate cross-sectional views of structures of a semiconductor chip or integrated circuit at various stages of fabrication in accordance with one or more embodiments of the invention. The chip or integrated circuit may include at least a first portion  1000 A, a second portion  1000 B and a third portion  1000 C. In the embodiment illustrated in  FIGS. 1 through 14 , the first portion  1000 A of the chip or integrated circuit may be a memory portion of the semiconductor device or chip. The memory portion  1000 A may include, for example, a charge storage memory device such as a floating gate memory device or a charge trapping memory device. In the embodiment illustrated in  FIGS. 1 through 14 , the second portion  1000 B of the chip or integrated circuit may be a first logic portion of the chip or integrated circuit. The first logic portion  1000 B may include a first transistor device. The first transistor device may be a field effect transistor. The field effect transistor may be a MOS transistor. The MOS transistor may be PMOS transistor or an NMOS transistor. The first logic portion may, for example, be a high-voltage logic portion. The transistor may be a high-voltage transistor. The first logic portion may, for example, be used for the peripheral circuitry of a memory array formed in the memory portion. 
   The third portion  1000 C of the semiconductor chip or integrated circuit may be a second logic portion of the chip or integrated circuit. The second logic portion may include a second transistor device. The second transistor may be a field effect transistor. The field effect transistor may be a MOS transistor. The MOS transistor may be an NMOS transistor or a PMOS transistor. The second logic portion may, for example, be a low-voltage logic portion. The second transistor may be a low-voltage transistor. The second logic portion may, for example, be used to form logic gates such as AND, NAND, NOR and OR gates. 
   Hence, in one or more embodiments, the three portions  1000 A,  1000 B and  1000 C may be formed as part of a semiconductor chip or integrated circuit. In one or more embodiments, the three portions  1000 A,  1000 B and  1000 C may be formed on a common semiconductor substrate. In one or more embodiments, the memory portion  1000 A may be in electrical communication with the first logic portion  1000 B. In one or more embodiments, the memory portion  1000 A may be in electrical communication with the second logic portion  1000 C. In one or more embodiments, the first logic portion  1000 B may be in electrical communication with the second logic portion  1000 C. 
     FIGS. 1 through 14  illustrate cross-sectional views showing the formation of a memory device (structures  1010 A through  1140 A), a first transistor (structures  1010 B through  1140 B), and a second transistor (structures  1010 C through  1140 C). 
   Referring to  FIG. 1 , a common semiconductor substrate  210  is provided for the first portion  1000 A, second portion  1000 B and third portion  1000 C. The substrate  210  may be a silicon substrate or other suitable substrate. The substrate  210  may be a silicon-on-insulator (SOI) substrate. The SOI substrate may, for example, be formed by a SIMOX process. The substrate may be a silicon-on-sapphire (SOS) substrate. The substrate  210  may, for example, be a p-doped substrate which may be useful for an n-channel device. The substrate  210  may, for example, be a p-doped substrate that also includes an n-doped well formed in an upper portion of the substrate  210 . The n-doped well may be useful for a p-channel device. 
   Hence, the substrate  210  includes three portions  210 A,  210 B and  210 C. While not shown in  FIG. 1 , isolation regions may be defined in the substrate  210 . For example, isolation regions may be formed in the substrate which isolate one memory or transistor device from another. For example, isolation regions may be formed which isolate one memory device from another. Isolation regions may be formed as trenches that are filled with an insulating material, such as SiO 2  or other suitable insulating material, to insulate one transistor cell from adjacent transistor cells. In one or more embodiments, isolation regions may be formed using a shallow trench isolation (STI) process. In one or more embodiments, isolation regions may be formed otherwise, such as by a LOCOS process. In one or more embodiments, isolation regions may be formed using deep trench processes. 
   Still referring to  FIG. 1 , a first dielectric layer  220  is formed over the substrate  210 . In the embodiment shown, a first dielectric layer  220  is formed over first substrate portion  210 A to form a structure  1010 A, over second substrate portion  210 B to form a structure  1010 B and over third substrate portion  210 C to form a structure  1010 C. The first dielectric layer  220  may include an oxide. An example of an oxide is silicon dioxide (SiO 2 ). In an embodiment of the invention, the first dielectric layer  220  may be an oxide (such as silicon dioxide) that is formed by a growth process. Another example of an oxide is tantalum oxide. In an embodiment, the first dielectric layer  220  may include a nitride. An example of a nitride is silicon nitride. In an embodiment, the first dielectric layer  220  may include a nitrided oxide. In an embodiment, the first dielectric material may include an oxynitride. An example of an oxynitride is SiON. Another example of an oxynitride is SiO x N y . In an embodiment, the first dielectric layer  220  may include a high-k dielectric. As one example, the high-k dielectric may have a dielectric constant greater than that of silicon dioxide. In another example, the high-k dielectric may have a dielectric constant greater than about 3.9. 
   In an embodiment, the first dielectric layer may comprise two or more materials. For example, the first dielectric layer may be a mixture of two or more material. In one or more embodiments, the mixture may be a homogeneous mixture. In one or more embodiments, the mixture may be a heterogeneous mixture. The first dielectric layer  220  may be formed of a composite of two or more materials. In one or more embodiments, the first dielectric layer  220  may be formed as a stack of two or more sub-layers. In one or more embodiments, the first dielectric layer  220  may have a thickness greater than about 5 nm. In one or more embodiments, the first dielectric layer  220  may have a thickness greater than about 10 nm. In one or more embodiments, the first dielectric layer  220  may have a thickness greater than about 15 nm. In one or more embodiments, the first dielectric layer may be about 8 nm. 
   Referring to  FIG. 2 , the dielectric layer  220  is then etched so that it is removed from the portion  210 A and portion  210 C of substrate  210 . As seen, the dielectric layer  220  is not substantially removed from the portion  210 B of substrate  210 . The etching process forms the structures  1020 A,  1020 B and  1020 C. 
   Referring to  FIG. 3 , an additional dielectric material  222  is formed over the first substrate portion  210 A, second substrate portion  210 B and third substrate portion  210 C. In one or more embodiments, the additional dielectric material  222  may be the same material as dielectric layer  220  shown in  FIG. 1 . The additional dielectric material  222  may, for example, be an oxide (such as silicon dioxide) which is formed by a growth process. In one or more embodiments, the additional dielectric material  222  may comprise another type of dielectric material such as a nitride or an oxynitride. 
   The additional dielectric material  222  results in structures  1030 A,B,C shown in  FIG. 3 . The combination of dielectric layer  220  and dielectric layer  222  forms a first dielectric layer  224 . The dielectric layer  222  is referred to as first dielectric layer  222 . In one or more embodiments, the first dielectric layer  222  and the first dielectric layer  224  may be formed of the same material. This same material may be an oxide such as silicon dioxide. The oxide may be formed by a thermal or growth process. 
     FIG. 4  shows structures  1040 A,B,C. A first gate layer  230  is formed over the first dielectric layer  222  of structure  1030 A and over the first dielectric layer  224  of structure  1030 B but not over structure  1030 C. In one or more embodiments, the first gate layer  230  may include a conductive material. In one or more embodiments, the first gate layer  230  may include a polysilicon material. The polysilicon material may be a doped polysilicon material (either n-doped or p-doped). The polysilicon material may be doped in-situ. 
   In one or more embodiments, the first gate layer  230  may include a conductive material. The first gate layer  230  may include a metallic material such as a pure metal or a metal alloy. The first gate layer  230  may be formed as a composite of two or more materials. The first gate layer  230  may be a stack of two or more sub-layers. As an example, the first gate layer  230  may include a metal layer disposed over the top of a polysilicon layer. In one or more embodiments, the first gate layer  230  may include a silicide layer disposed over the top of a polysilicon layer. Examples of a silicide layer include cobalt silicide and tungsten silicide. In one or more embodiments, the first gate layer  230  may have a thickness greater than about 100 nm. In one or more embodiments, the gate layer  230  may have a thickness greater than about 150 nm. In one or more embodiments, the gate layer  230  may have a thickness greater than about 200 nm. 
   Still referring to  FIG. 4 , a second dielectric layer  240  is formed over the first gate layer  230  over portions  210 A and  210 B of substrate  210  but not over the portion  210 C. In one or more embodiments, the second dielectric layer  240  may include an oxide. An example of an oxide is silicon dioxide (SiO 2 ). In one or more embodiments, the second dielectric layer  240  may be an oxide (such as silicon dioxide) that is formed by a growth process. Another example of an oxide is tantalum oxide. In one or more embodiments, the second dielectric layer  240  may include a nitride. An example of a nitride is silicon nitride. In one or more embodiments, the second dielectric layer  240  may include a nitrided oxide. In one or more embodiments, the second dielectric material may include an oxynitride. An example of an oxynitride is SiON. Another example of an oxynitride is SiO x N y . In one or more embodiments, the second dielectric layer  240  may include a high-k dielectric material. As one example, the high-k dielectric may have a dielectric constant greater than that of silicon dioxide. In another example, the high-k dielectric may have a dielectric constant greater than about 3.9. 
   In one or more embodiments, the second dielectric layer  240  may comprise two or more materials. For example, the second dielectric layer may be a mixture of two or more material. In one or more embodiments, the mixture may be a homogeneous mixture. In one or more embodiments, the mixture may be a heterogeneous mixture. In one or more embodiments, the second dielectric layer  240  may be a stack of two or more layers such as an oxide/nitride stack, a nitride/oxide stack or an oxide/nitride/oxide stack. In an embodiment, the second dielectric layer  240  may be formed of a composite of two or more materials. 
   In one or more embodiments, the second dielectric layer  240  may have a thickness greater than about 10 nm. In one or more embodiments, the second dielectric layer  240  may have a thickness greater than about 15 nm. In one or more embodiments, the second dielectric layer  240  may have a thickness greater than about 20 nm. In one or more embodiments, the second dielectric layer may be about 16 nm. 
   Still referring to  FIG. 4 , a second gate layer  250  is formed over the second dielectric layer  240  of structures  1040 A and  1040 B. The second gate layer  250  is also formed over the first dielectric layer  222  of structure  1040 C. In one or more embodiments, the second gate layer  250  may include a conductive material. The second gate layer  250  may include a polysilicon material. The polysilicon material may be a doped polysilicon material (either n-doped or p-doped). The polysilicon material may be doped in-situ. The polysilicon material may be doped by an ion implantation process. For example, the polysilicon material may be doped by a later process (such as one used to later form the extension regions or the source/drain regions). 
   In one or more embodiments, the second gate layer  250  may include a conductive material. In an embodiment, the second gate layer  250  may include a metallic material such as a pure metal or a metal alloy. The second gate layer  250  may be formed as a composite of two or more materials. The second gate layer  250  may be a stack of two or more sub-layers. As an example, the second gate layer  250  may include a metal layer disposed over the top of a polysilicon layer. In one or more embodiments, the second gate layer  250  may include a silicide layer disposed over the top of a polysilicon layer. Examples of a silicide layer include cobalt silicide and tungsten silicide. In one or more embodiments, the second gate layer  250  may have a thickness greater than about 100 nm. In one or more embodiments, the gate electrode layer  250  may have a thickness greater than about 150 nm. In one or more embodiments, the gate electrode layer  250  may have a thickness greater than about 200 nm. 
   The first dielectric layers  222  and  224 , first gate layer  230 , second dielectric layer  240  and second gate layer  250  may then be masked and etched over portions  210 A,  210 B and  210 C of the substrate  210 . The result of the masking and etching is to form a first gate stack  300 A over the first substrate portion  210 A, a second gate stack  300 B over the second substrate portion  210 B and a third gate stack  300 C over the third substrate portion  210 C. This results in the structures  1050 A,  1050 B and  1050 C as shown in  FIG. 5 . 
   The gate stack  300 A shown in  FIG. 5  includes a first dielectric layer  222 ′ (which is a portion of first dielectric layer  222  shown in  FIG. 4 ), a first gate layer  230 A (which is a portion of first gate layer  230  in  FIG. 4 ), a second dielectric layer  240 A (which is a portion of second dielectric layer  240  in  FIG. 4 ) and a second gate layer  250 A (which is a portion of second gate layer  250  in  FIG. 4 ). The first gate layer  230 A may form a charge storage layer for the gate stack  300 A. In one or more embodiments, the charge storage layer may be a floating gate layer (also referred to as a floating gate). In one or more embodiments, the charge storage layer may be a charge trapping layer. The second gate layer  250 A may form a control gate layer (also referred to as a control gate) for the gate stack  300 A. 
   In one or more embodiments, the gate stack  300 A may include one or more additional layers. For example, it is possible that the gate stack  300 A includes an additional pre-gate layer between the first dielectric layer  222 ′ and the substrate portion  210 A. Likewise, it is also possible that the gate stack  300 A may include a buffer layer between the first dielectric layer  222  and the first gate layer  230 A. 
   The gate stack  300 B shown in  FIG. 5  includes a first dielectric layer  224 ′ (which is a portion of first dielectric layer  224  shown in  FIG. 4 ), a first gate layer  230 B (which is a portion of first gate layer  230  in  FIG. 4 ), a second dielectric layer  240 B (which is a portion of second dielectric layer  240  in  FIG. 4 ) and a second gate layer  250 B (which is a portion of second gate layer  250  in  FIG. 4 ). 
   In one or more embodiments, the gate stack  300 B may include one or more additional layers. For example, it is possible that the gate stack  300 B includes an additional pre-gate layer between the first dielectric layer  222  and the substrate portion  210 B. Likewise, it is also possible that the gate stack  300 B may include a buffer layer between the first dielectric layer  224 ′ and the first gate layer  230 B. 
   The gate stack  300 C shown in  FIG. 5  includes a first dielectric layer  222 ′ (which is a portion of first dielectric layer  222  shown in  FIG. 4 ) and a second gate layer  250 C (which is a portion of first gate layer  250  in  FIG. 4 ). The first dielectric layer  222 ′ may be gate dielectric for the gate stack  300 C. The second gate layer  250 C may be a gate electrode layer (also referred to as a gate electrode) for the gate stack  300 C. 
   In one or more embodiments, the gate stack  300 C may include one or more additional layers. For example, it is possible that the gate stack  300 C includes an additional pre-gate layer between the first dielectric layer  222 ′ and the substrate portion  210 C. Likewise, it is also possible that the gate stack  300 C may include a buffer layer between the first dielectric layer  222 ′ and the second gate layer  250 C. 
   After the formation of the gate stacks  300 A,  300 B and  300 C, the structures  1050 A,  1050 B and  1050 C from  FIG. 5  may be appropriately doped using an ion implantation process to form source/drain extension regions EXT as shown in structures  1060 A,  1060 B and  1060 C. In one or more embodiments, the source/drain extension regions EXT may, for example, be lightly doped drain (LDD) regions. In one or more embodiments, the extension regions EXT may, for example, be medium doped drain (MDD) regions. 
   In one or more embodiments, the extension regions EXT may be n-type. In one or more embodiments, the extension regions EXT may be p-type. In one or more embodiments, during the formation of the extension regions EXT, the second gate layers  250 A,  250 B and  250 C may also be doped with n-type and/or p-type dopants. The source/drain extension implant forms the structures  1060 A,  1060 B and  1060 C of  FIG. 6  that include doped extensions regions EXT. In one or more embodiments, the doping of the three structures may take place at the same time. In one or more embodiments, it may take place at different times. 
   In one or more embodiments, the extension regions EXT of the structure  1060 A may be more heavily doped than the extension regions EXT of the structures  1060 B,C. In one or more embodiments, the extension regions EXT of the structure  1060 A may be more lightly doped than the extension regions EXT of the structures  1060 B and  1060 C. In one or more embodiments, the dopant concentration of the extension regions EXT of the structure  1060 A may be about the same as the dopant concentration of the extension regions EXT of the structures  1060 B and  1060 C. 
   In one or more embodiments, the extension regions EXT for the structures  1060 A,B,C may be doped with an n-type material. Examples of n-type materials include phosphorous and arsenic. In one or more embodiments, the extension regions EXT for the structures  1060 A,B,C may be doped with a p-type material. An example of a p-type material is boron. 
   Referring now to  FIG. 7 , after the formation of the extension regions EXT, a layer  260  is formed over the structures  1060 A,B,C of  FIG. 6  to form the structures  1070 A,B,C shown in  FIG. 7 . In one or more embodiments, the layer  260  may be formed by a growth process. In one or more embodiments, the layer  260  may be formed by a deposition process. In one or more embodiments, the layer  260  may be conformally or substantially conformally deposited over the structures  1060 A,B,C. 
   In one or more embodiments, the layer  260  may comprise a dielectric material. In one or more embodiments, the layer  260  may be a dielectric layer. In one or more embodiments, the dielectric layer may be formed by a growth process. In one or more embodiments, the dielectric layer may be formed by a deposition process. 
   In one or more embodiments, the layer  260  may include an oxide. An example of an oxide is silicon dioxide (SiO 2 ). Another example of an oxide is tantalum oxide. In one or more embodiments, the layer  260  may include a nitride. An example of a nitride is silicon nitride. In one or more embodiments, the dielectric material may include an oxynitride. An example of an oxynitride is SiON. Another example of an oxynitride is SiO x N y . In one or more embodiments, the layer  260  may include a high-k dielectric material. As one example, the high-k dielectric may have a dielectric constant greater than that of silicon dioxide. In another example, the high-k dielectric may have a dielectric constant greater than about 3.9. 
   In an embodiment, the layer  260  may comprise two or more materials. For example, the layer  260  may be a mixture of two or more materials. In one or more embodiments, the mixture may be a homogeneous mixture. In one or more embodiments, the mixture may be a heterogeneous mixture. The layer  260  may be formed as a composite of two or more materials. In one or more embodiments, the layer  260  may be formed as a stack of two or more layers. In one or more embodiments, the layer  260  may have a thickness greater than about 10 nm. In one or more embodiments, the layer  260  may have a thickness greater than about 15 nm. In one or more embodiments, the layer  260  may have a thickness greater than about 20 nm. In one or more embodiments, the layer may be about 16 nm. In one or more embodiments, the layer  260  may be conformally or substantially conformally deposited over the structures  1060 A,B,C shown in  FIG. 6 . 
   Referring to  FIG. 8 , a layer  270  is formed over the structures  1070 A,B,C shown in  FIG. 7  to form the structures  1080 A,B,C shown in  FIG. 8 . In one or more embodiments, the layer  270  may be conformally or substantially conformally deposited over the structures  1070 A,B,C shown in  FIG. 7 . In one or more embodiments, the layer  270  may be conformally or substantially conformally deposited over the layer  260 . 
   In one or more embodiments, the layer  270  may comprise a polysilicon material. In one or more embodiments, the layer  270  may be a polysilicon layer. The layer  270  may comprise a doped polysilicon material. In one or more embodiments, the doped polysilicon material may be in-situ doped. In one or more embodiments, the polysilicon material may be dope using an ion implantation process. In one or more embodiments, the polysilicon material may be doped using a downstream doping process such as the one used to form the source/drain regions. In one embodiment, the polysilicon layer may be n-doped. In another embodiment, the polysilicon layer may be p-doped. 
   In one or more embodiments, the layer  270  may comprise a conductive material. 
   Referring to  FIG. 9 , the layer  270  may then be etched to form sidewall spacers  270 A,B,C over the sidewalls of layer  260  as shown in structures  1090 A,B,C. The etch may be an anisotropic etch or a substantially anisotropic etch. In one or more embodiments, the etch may include a dry or plasma etch process. In one or more embodiments, the sidewalls spacers  270 A,B,C may comprise a polysilicon material. In one or more embodiments, the sidewall spacers  270 A,B,C may comprise doped polysilicon. In one or more embodiments, the polysilicon material may be n-doped. In one or more embodiments, the polysilicon material may be p-doped. In one or more embodiments, the sidewall spacers  270 A,  270 B and/or  270 C may be polysilicon sidewall spacers. In one or more embodiments, the polysilicon sidewall spacers  270 A,  270 B and/or  270 C may be doped polysilicon. The doped polysilicon may be n-type doped or p-type doped. As shown in  FIG. 9 , the sidewall spacers  270 A,B,C may be disposed over the substrate portions  210 A,B,C respectively and may be laterally disposed from the gate stacks  300 A,B,C respectively. 
   Referring now to  FIG. 10 , one of the sidewall spacers  270 A may be removed (for example, by an etch process) from the structure  1090 A of  FIG. 9  to form the structure  1100 A shown in  FIG. 10 . In one or more embodiments, the spacers  270 A may comprise a polysilicon material while the layer  260  may comprise a dielectric (such as an oxide). Hence, in one or more embodiments, an appropriate etch may be chosen which is selective to the polysilicon. 
   The layer  260  from  FIG. 10  may be subjected to an etch so as to remove portions of the layer  260  that are disposed over the top surface of the gate stacks  300 A,B,C as well as exposed portions of the layer  260  that exposed on the substrate  210 . The etch may be an anisotropic etch or a substantially anisotropic etch. In one or more embodiments, the etch may include a dry etch or a plasma etch process. After the etch, the structures  1110 A,B,C are formed as shown in  FIG. 11 . The portions  260 A,  260 B and  260 C of layer  260  remain in the structures  1110 A,  1110 B and  1110 C respectively. The etch may be an anisotropic etch. The etch exposes the top surfaces of second gate layers  250 A,  250 B and  250 C. The etch also exposes portions of the substrate portions  210 A,  210 B and  210 C. 
   The structures  1110 A,B,C from  FIG. 11  are each exposed to a doping process to form the structures  1120 A,B,C shown in  FIG. 12 . The doping process may be performed by one or more ion implantation processes. The doping process forms source/drain regions SD in the substrate portions  210 A,B,C. In one or more embodiments, the source/drain regions SD may be formed as heavily doped drain (HDD) regions. 
   In one or more embodiments, the dopant concentrations of the source/drain regions SD of each of the structures  1120 A,B,C may be greater than the dopant concentration of the extension regions EXT of the corresponding structure. Also, in one or more embodiments, the depth of the source/drain regions SD of structures  1120 A,B,C may be greater than the depth of the extension regions of the corresponding structure. 
   In one or more embodiments, the dopant dose of the ion implantation process to form the source/drain regions SD of each of the structures  1120 A,B,C may be greater than the dopant dose to form the extension regions EXT of the corresponding structure. Also, in one or more embodiments, the dopant energy of the ion implantation process to form the source/drain regions SD of structures  1120 A,B,C may be greater than the dopant energy to form the extension regions of the corresponding structure. 
   In one or more embodiments, the source/drain regions SD of the structures  1120 A,B,C may be formed at substantially the same time. In one or more embodiments, the source/drain regions SD of the structures  1120 A,B,C may be formed at different times. 
   In one or more embodiments, the same doping process used to form the source/drain regions SD of the structures  1120 A,B,C may also be used to dope the second gate layers  250 A,B,C of the structures. In one or more embodiments, the second gate layers  250 A,B,C may comprise a polysilicon material. In one or more embodiments, this polysilicon material may be deposited undoped in the structures  1040 A,B,C shown in  FIG. 4 . The polysilicon material may then be doped by the same doping process (such as an ion implantation process) used to form the source/drain SD regions. 
     FIG. 13  shows structures  1130 A,B,C. Referring to  FIG. 13 , an opening may be formed through the second gate layer  250 B and through the second dielectric layer  240 B of structure  1130 B so as to expose the first gate layer  230 B. The opening may be filled with a conductive plug  280 . The conductive plug  280  electrically couples the first gate layer  230 B to the second gate layer  250 B. 
     FIG. 14  shows the addition of contacts  290  to form the structures  1140 A,B,C. In one of more embodiments, the structure  1140 A is memory device. The memory device may be a charge storage memory device. In one or more embodiments, the charge storage device may be a floating gate memory device. The memory device  1140 A includes a gate stack  300 A. The gate stack  300 A includes a first dielectric layer  222 ′, a first gate layer  230 A, a second dielectric layer  240 A and a second gate layer  250 A. The first dielectric layer  222 ′ may, for example, comprise an oxide (such as a silicon dioxide). The first gate layer  230 A may serve a floating gate layer which may also be referred to as a floating gate. The first gate layer  230 A (and, hence, the floating gate) may comprise a doped polysilicon. The second dielectric layer  240 A may serve as an inter-gate dielectric and may, for example, comprise an oxide (such as silicon dioxide). The second gate layer  250 A may be a control gate layer which may also be referred to as a control gate. The second gate layer  250 A may be formed of a doped polysilicon. The memory device  1140 A also includes a sidewall spacer  270 A. The sidewall spacer  270 A may serve as a select gate for the memory device  1140 A. The sidewall spacer  270 A may also comprise a doped polysilicon. 
   It is noted that one or more embodiments, the control gate  250 A may be coupled to a first voltage while the select gate  270 A may be coupled to a second voltage. The first and second voltage may be the same or different voltages. The first or second voltages may be a ground potential. In another embodiment of the invention, it is possible that the control gate  250 A be coupled to voltage while the select gate  270 A be permitted to float. 
   In another embodiment, it is possible that the memory structure  1130 A be formed as a charge trapping device. In this case, the charge storage layer  230 A may be a charge trapping layer. An example of a charge trapping layer is a nitride layer (such as silicon nitride). Another example of a charge trapping layer is a nanocrystalline layer. 
   Still referring to  FIG. 14 , in one or more embodiments, the structure  1140 B may form a transistor device. The transistor device  1140 B includes a gate stack  300 B. The gate stack  300 B includes a first dielectric layer  224 ′. The first dielectric layer  224 ′ may be a gate dielectric for the gate stack  300 B. The gate stack  300 B also includes a first gate layer  230 B, a second dielectric layer  240 B and a second gate layer  250 B. The first gate layer  230 B and the second gate layer  250 B are electrically coupled together to form a gate electrode for the transistor device  1140 B. 
   In an embodiment, the first dielectric layer  224 ′ may be an oxide layer (such as silicon dioxide). In an embodiment, first gate layer  230 B may comprise a doped polysilicon material. In an embodiment, the second dielectric layer  240 B may comprise an oxide material such as a silicon dioxide material. 
   The transistor device  1140 B may be a field-effect transistor device. The field-effect transistor device may, for example, be a MOS field-effect transistor device. The MOS transistor may be an NMOS transistor having an n-channel or a PMOS transistor having a p-channel. It is possible that the substrate region  210 B include at least one NMOS transistor and at least one PMOS transistor to form a CMOS device. The transistor device  1140 B may be a high-voltage transistor device. 
   Referring to the structure  1140 B includes source/drain regions SD and extension regions EXT. It is seen that the distance from the source/drain regions SD to the beginning of the gate stack  300 B is a distance “X 1 ”. The distance X 1  may be changed by changing the thickness of the sidewall spacers  270 B. The thickness of the sidewall spacers  270 B (and, hence, the distance X 1 ) may be increased by increasing the height of the gate stack  300 B. 
   Still referring to  FIG. 14 , in one or more embodiments, the structure  1140 C may form a transistor device. The transistor device  1140 C includes a gate stack  300 C. The gate stack  300 C includes a first dielectric layer  222 ′. The first dielectric layer  222 ′ may be a gate dielectric for the gate stack  300 C. The gate stack  300 C also includes a second gate layer  250 B. The second gate layer  250 C forms a gate electrode for the transistor device  1140 C. 
   In an embodiment, the first dielectric layer  222 ′ may be an oxide layer (such as silicon dioxide). In an embodiment, first gate layer may comprise a doped polysilicon material. 
   The transistor device  1140 C may be a field-effect transistor device. In one or more embodiments, the transistor device  1140 C may be a low-voltage transistor device. The field-effect transistor may be a MOS transistor device. The MOS transistor may be an NMOS transistor having an n-channel or a PMOS transistor having a p-channel. It is possible that the substrate region  210 C include at least one NMOS transistor and at least one PMOS transistor to form a CMOS device. 
   Referring to  FIG. 14 , the structure  1140 C includes source/drain regions SD and extension regions EXT. It is seen that the distance from the source/drain regions SD to the beginning of the gate stack  300 C is a distance “X 2 ”. The distance X 2  may be changed by changing the thickness of the sidewall spacers  270 C. The distance X 2  may be changed by changing the thickness of the sidewall spacers  270 C. The thickness of the sidewall spacers  270 C (and, hence, the distance X 2 ) may be increased by increasing the height of the gate stack  300 C. In one or more embodiments, the thickness of sidewall spacers  270 B may be greater than the thickness of sidewall spacers  270 C. In one or more embodiments, the distance X 1  may be greater than the distance X 2 . 
   It is observed that, in one or more embodiments, the spacers  270 B and  270 C may be formed during the same processing steps used (and at substantially the same time as) the formation of spacers  270 A. 
   Another embodiment of the invention is shown in  FIG. 15 .  FIG. 15  shows a transistor structure  1150 B that only includes a single sidewall spacer  270 B. The sidewall spacer  270 B may be formed of a polysilicon material such as a doped polysilicon material. In an embodiment, the spacer  270 B may be n-doped. In an embodiment, the spacer  270 B may be p-doped.  FIG. 15  also shows a transistor structure  1150 C that only includes a single sidewall spacer  270 C. The sidewall spacer  270 C may be formed of a polysilicon material such as a doped polysilicon material. In an embodiment, the spacer  270 C may be n-doped. In an embodiment, the spacer  270 C may be p-doped. 
   Another embodiment of the invention is shown in  FIG. 16 .  FIG. 16  shows a transistor structure  1160 B that does not include a sidewall spacer  270 B. In one or more embodiments, the structure  1160 B shown in  FIG. 16  may be formed by forming the structure  1140 B in  FIG. 14  and then removing the spacers  270 B to form the structure  1160 B shown in  FIG. 16 . 
     FIG. 16  also shows a transistor structure  1160 C that does not include a sidewall spacer  270 C. In one or more embodiments, the structure  1160 C shown in  FIG. 16  may be formed by forming the structure  1140 C in  FIG. 14  and then removing the spacers  270 C to form the structure  1160 C shown in  FIG. 16 . 
   It is to be understood that the disclosure set forth herein is presented in the form of detailed embodiments described for the purpose of making a full and complete disclosure of the present invention, and that such details are not to be interpreted as limiting the true scope of this invention as set forth and defined in the appended claims.