Abstract:
An on-chip test circuit in an integrated circuit includes a comparison circuit and a fail data register. An output of the comparison circuit is coupled to an input to the fail data register. The comparison circuit includes a first group of inputs coupled to outputs of a function circuit in the integrated circuit. The comparison circuit also includes a second group of inputs coupled to a source of expect data associated with normal function circuit performance. When a comparison between read data from the outputs of the function circuit and corresponding expect data indicates malfunction of the function circuit, data related to the malfunction are stored in the fail data register. A separate integrated circuit select line is coupled to each integrated circuit to allow transmission of the stored failure data without bus contention. As a result, many integrated circuits that are being tested may share an I/O bus, because the integrated circuits under test only output failure data on the I/O bus. Further, each integrated circuit only provides failure data to an external test data evaluation apparatus in response to selection signals from the external test data evaluation apparatus. The efficiency with which integrated circuits may be tested is thereby increased.

Description:
TECHNICAL FIELD 
     The present invention relates generally to testing of integrated circuits, and more specifically to a method and apparatus that reduces the time and testing resources needed for testing of integrated circuits. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits are extensively tested both during and after production, and, in some cases, routinely during use after they have been installed in products. For example, memory devices, such as random access memories (“RAMs”) and dynamic random access memories (“DRAMs”), are tested during production at the wafer level and after packaging, and they are also routinely tested each time a computer system using the DRAMs executes a power-up or “boot” routine when power is initially applied to the computer system. As the capacity of DRAMs and other memory devices continues to increase, the time required to test the DRAMs continues to increase, even though memory access times continue to decrease. 
     A typical RAM integrated circuit includes at least one array of memory cells arranged in rows and columns. Each memory cell must be tested to ensure that it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a “1”) are written to and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a “0”) are typically written to and read from the memory cells. A memory cell is determined to be defective when the data that is read from the memory cell does not equal the data that was written to the memory cell. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern, e.g., 101010. . . , written to the memory cells in each row of the arrays. 
     One situation requiring testing of memory integrated circuits occurs during fabrication of integrated circuits. Fabrication yields are reduced when fabrication errors occur. Testing of integrated circuits during fabrication allows the sources of some fabrication errors to be promptly identified and corrected. Testing during fabrication may reduce costs by reducing the number of integrated circuits affected by a given fabrication error. 
     Another situation requiring testing of integrated circuits also occurs in fabrication of memory integrated circuits. Defective memory cells are identified by testing and are replaced with non-defective memory cells from a set of spare or redundant memory cells. In one conventional method for replacing defective memory cells, fuses on the integrated circuit are blown in a pattern corresponding to the pattern of defective memory cells to select rows or columns of redundant memory cells. The pattern is then read to replace the rows or columns that include the defective memory cells. 
     FIG. 1 is a simplified block diagram of several integrated circuits  10  and an automated tester  12  according to the prior art. Separate buses  14  are dedicated to couple each of the integrated circuits  10  to the automated tester  12 . The data buses  14  convey stimuli, known as background data, from the automated tester  12  to function circuits  16 , such as memory arrays, contained in the integrated circuits  10  that are being tested. Each function circuit  16  generates a response, such as read data, from the background data that are sent to that function circuit  16 . The data buses  14  also convey the read data from each function circuit  16  back to the automated tester  12 . The automated tester  12  compares the read data from each integrated circuit  10  that is being tested to a corresponding set of expect data. The expect data correspond to read data that would be provided by the integrated circuit  10  if its function circuit  16  was operating properly. When the read data and the corresponding expect data match, the integrated circuit  10  is considered to be functioning normally. When the read data do not match the corresponding expect data, the integrated circuit  10  that provided the read data is considered to be malfunctioning. 
     Each bus  14  can only convey data unambiguously from one integrated circuit  10  at a time to the automated tester  12 . In turn, the automated tester  12  can only accommodate a finite number of buses  14 , limiting the number of integrated circuits  10  that may be tested at one time. The number of memory integrated circuits  10  that may be coupled to the automated tester  12  at one time is known as the “fanout” for the automated tester  12 . 
     There is a need for an on-chip test circuit to test function circuits in a group of integrated circuits without requiring a separate module or control integrated circuit to read output signals from the function circuits in order to compare the output signals with expected output signals. 
     SUMMARY OF THE INVENTION 
     An on-chip test circuit is included in an integrated circuit for testing function circuits in the integrated circuit and for storing failure data from the tests. The on-chip test circuit includes an expect data register and a comparison circuit having a first input coupled to an output of the function circuits and a second input coupled to an output of the expect data register. The on-chip test circuit also includes a fail data register having an input coupled to an output of the comparison circuit. The fail data register stores data describing memory array failures. The combination of the comparison circuit and the fail data register allows many integrated circuits to be tested at one time without waiting for the each integrated circuit to provide read data to a tester and without bus contention. Testing of integrated circuits is thereby facilitated, reducing the time required for testing the integrated circuits and increasing the practical fanout from automated testers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram of several integrated circuits and an automated tester according to the prior art. 
     FIG. 2 is a simplified block diagram of a portion of an integrated circuit including an on-chip testing circuit in accordance with an embodiment of the present invention. 
     FIG. 3 is a simplified block diagram of several integrated circuits and an automated tester in accordance with an embodiment of the present invention. 
     FIG. 4 is a flow chart describing an integrated circuit testing method in accordance with an embodiment of the present invention. 
     FIG. 5 is a flow chart describing a method of reading stored failure data from the fail data register of an integrated circuit that has been tested in accordance with an embodiment of the present invention. 
     FIG. 6 is a flow chart describing an integrated circuit speed testing method in accordance with an embodiment of the present invention. 
     FIG. 7 is a simplified block diagram of a computer system including the integrated circuit of FIG. 2 in accordance with an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 is a simplified block diagram of a portion of an integrated circuit  20  including an on-chip testing circuit  22  in accordance with an embodiment of the present invention. The integrated circuit  20  also includes I/O pins or pads  24  coupled to a DQ buffer  26 , allowing data, address and control signals to be coupled between external circuits (not shown in FIG. 4) and a function circuit  28 . The I/O pins or pads  24  used to couple signals to and from the integrated circuit  20  typically include between one and sixty-four pins or pads. In one embodiment, the function circuit  28  includes a microprocessor. In another embodiment, the function circuit  28  includes a memory circuit such as a RAM, DRAM or synchronous DRAM. 
     The on-chip testing circuit  22  includes an expect data register  30  having an input bus coupled to the DQ buffer  26 . A comparison circuit  32  includes a first input coupled to the expect data register  30  and a second input coupled to an output of the function circuit  28 . A test mode enable circuit  33  is responsive to signals provided on a control line TME. A fail data register  34  has a reset input R coupled to the test mode enable circuit  33  and has one or more data inputs coupled to an output of the comparison circuit  32 . In one embodiment, the on-chip testing circuit  22  also includes an OR gate  35  having inputs coupled to the output of the comparison circuit  32  and an output coupled to a first input of an AND gate  36 . The AND gate  36  has a second input coupled to an output of a clock input buffer  38 . The DQ buffer  26 , the function circuit  28  and the expect data register  30  all couple data in or out in response to a clock signal, e.g., CLK IN . 
     The on-chip test circuit  22  operates in one of two modes, a test mode and a pass-through mode, as determined by the state of the test mode enable circuit  33 . In the pass-through mode, an external circuit (not shown in FIG. 2) provides signals on the control line TME causing the test mode enable circuit  33  to deactivate all address and control signals that it develops, allowing the integrated circuit  20  to function in a normal mode. 
     When the external circuit activates the test mode enable circuit  33 , the on-chip test circuit  22  operates in the test mode to test the function circuit  28  in the integrated circuit  20 . In the test mode of operation, command signals are coupled to the test mode enable circuit  33  from the external circuit in order to (i) put the integrated circuit  20  into the test mode, (ii) clear the fail data register  34  using a signal coupled to a reset input R, (iii) load background data into the function circuit  28  through the DQ buffer  26  and (iv) load expect data into the expect data register  30  through the IO pins or pads  24  of the DQ buffer  26 . The comparison circuit  32  then compares read data from the function circuit  28  with corresponding expect data from the expect data register  30  and provides one or more output signals to the fail data register  34  when the read data do not match the corresponding expect data. 
     In one embodiment, the expect data register  30  is omitted. In this embodiment, the expect data may be supplied to the comparison circuit  32  through the I/O pins or pads  24  and the DQ buffer  26 . Alternatively, the expect data may be stored in, e.g. a ROM (not illustrated) that is also a part of the test circuit  22 , or may be stored or generated in the integrated circuit  20 . 
     In another embodiment, the comparison circuit  32  may be a group of exclusive OR (“XOR”) gates (not illustrated) performing bitwise comparisons between the read data from the function circuit  28  and the corresponding expect data. In this embodiment, the output bits from the comparison circuit  32  will all be logical zeroes unless there is an error in the read data indicating a failure in the function circuit  28 . 
     The outputs from the comparison circuit  32  may be used to increment a clock signal to the fail data register  34  by coupling each of the output bits from the comparison circuit  32  to a separate input of the OR gate  35  and coupling an output of the OR gate  35  to a first input of the AND gate  36 . A clock signal from the clock buffer  38  is coupled to a second input of the AND gate  36 . The clock signal from the clock buffer  38  is then passed to the clock input CLK of the fail data register  34  only when one or more bits from the output of the comparison circuit  32  indicate a failure in the function circuit  28 . The fail data register  34  then only records data when there is a mismatch between the read data and the corresponding expect data that is indicative of a failure in the function circuit  28 . Recording only data relating to failures, rather than all of the results of comparing read and expect data, reduces the amount of data to be stored in the fail data register  34 . 
     In one embodiment, the fail data register  34  may be a counter. When a single-bit counter is used, the counter can indicate only that at least one failure occurred or that no failures occurred. When a multi-bit counter is used, the fail data register  34  may record how many failures occurred, up to the capacity of the counter employed for the fail data register  34 . The addition of an overflow bit provides an indication that a greater number of failures occurred than can be recorded by the counter. 
     In some situations, multiple tests of each integrated circuit  20  may require several sets of failure data to be stored in each integrated circuit  20 . In one embodiment, the fail data register  34  is segmented into a series of sub-registers FDR 1 , FDR 2  etc. each dedicated to storing failure data from one of the tests. These kinds of data may be useful in speed grading (determining the maximum clock frequency permitting reliable operation) of the integrated circuits  20 , as is explained below in more detail. 
     When the integrated circuit  20  includes a memory circuit as the function circuit  28 , it may be useful to store additional types of data in the fail data register  34 . For example, it may be desirable to store addresses corresponding to defective memory locations in a failed cell address register that is part of the fail data register  34 . These addresses may be used to repair the function circuit  28  or to avoid writing data to or reading data from the defective memory locations in the function circuit  28 . 
     FIG. 3 is a simplified block diagram of N many integrated circuits  20  and an automated tester  50  in accordance with an embodiment of the present invention. A common, i.e., shared, bus  52  couples the I/O pins or pads  24  of the integrated circuits  20  to the automated tester  50 . At least one dedicated control line  52   n , where n is an element of the set ranging from 1 to N inclusive, is also coupled between each of the control lines TME of the test mode enable circuits  33  (FIG. 2) in the N many integrated circuits  20  and the automated tester  50 . 
     A first advantage that the automated tester  50  provides when testing integrated circuits  20  that include the on-chip testing circuit  22  is that the common bus  52  may be employed to send address, data and control signals to all of the integrated circuits  20  simultaneously. In other words, storing the results of the testing in the fail data registers  34  (FIG. 2) of the integrated circuits  20  allows testing of all of the integrated circuits  20  at the same time but avoids bus contention by storing test results in the fail data register  34 . A second advantage of the embodiment of FIGS. 2 and 3 is that the amount of data that needs to be read from each of the integrated circuits  20  is reduced. Reading read data from, for example, every memory location in a memory array involves more data then merely reading the addresses of failed memory cells. A third advantage of the embodiment of FIGS. 2 and 3 is that testing time is reduced because the comparisons between expect data and read data are performed simultaneously in each of the integrated circuits  20  being tested, rather than being performed by the automated tester  12  of FIG. 1. A fourth advantage is that each additional integrated circuit  20  being tested only requires a single additional dedicated control line  52   n  that is separate from the common bus  52 , rather than separate buses  14  each dedicated to one integrated circuit  10 . 
     When testing of the integrated circuits  20  is complete, the automated tester  50  may read the contents of each of the fail data registers  34 , as is described in more detail below. 
     FIG. 4 is a flow chart describing a process  60  for testing integrated circuits  20  in accordance with one embodiment of the present invention. The process  60  tests functionality of the function circuit  28  of FIG. 2, and may use the automated tester  50  of FIG. 3 to do so, although it will be recognized that other types of controllers might be used. In a step  62 , the automated tester  50  sends control signals to the integrated circuits  20  that are to be tested to set the integrated circuits  20  to the test mode. In a step  64 , the automated tester  50  sends signals to the integrated circuits  20  that clear the fail data registers  34 . In a step  66 , the automated tester  50  writes the expect data into all of the expect data registers  30  using the common bus  52 . In a step  68 , the automated tester  50  writes the background data to the function circuits  28 , again using the common bus  52 . 
     In a step  70 , the on-chip test circuit  22  obtains read data from the function circuit  28  and corresponding expect data from the expect data register  30 . In a query task  72 , the on-chip test circuit  22  compares the read data to the corresponding expect data to determine if a failure of the function circuit  28  has occurred, i.e., the read data do not match the corresponding expect data. When the on-chip test circuit  22  determines that a failure has occurred, the on-chip test circuit  22  initiates a step  74 . In the step  74 , the on-chip test circuit  22  stores data describing the failure in the fail data register  34 . Control passes to a query task  76  when either the query task  72  determines that no failure of the function circuit  28  has occurred or after the failure data have been recorded in the step  74 . The query task  76  determines if the testing has been completed. 
     When the query task  76  determines that the testing has not been completed, a step  78  increments the expect data register  30  and the function circuit  28  to provide new expect and read data, respectively. The on-chip test circuit  22  then returns to the step  70  and continues testing the function circuit  28 . When the query task  76  determines that the testing has been completed, a step  79  returns the integrated circuit  20  to a normal mode of operation and the process  60  ends. 
     FIG. 5 is a flow chart describing a process  80  for reading stored failure data from the fail data registers  34  (FIG. 2) of integrated circuits  20  that have been tested in accordance with an embodiment of the present invention. In one embodiment, the automated tester  50  (FIG. 3) may initiate the process  80  after the process  60  (FIG. 4) ends. In a step  82 , one of the integrated circuits  20  that has new failure data to be downloaded is selected. In one embodiment, a signal is coupled to the control line TME of the selected integrated circuit  20  from the automated tester  50  by the control line  52   n  (FIG. 3) that is dedicated to the selected integrated circuit  20 . 
     In a step  84 , the on-chip testing circuit  22  in the selected integrated circuit  20  downloads data describing the fail status of the function circuit  28  from the fail data register  34  to the automated tester  50  through the common bus  52 . A query task  86  then determines if all of the failure data have been downloaded. When the query task  86  determines that not all of the failure data have been downloaded, control passes back to step  82  to select another one of the integrated circuits  20 , allowing all of the integrated circuits  20  to be selected in turn. When the query task  86  determines that all of the failure data have been downloaded, the process  80  ends. 
     In another embodiment, the integrated circuit  20  may initiate the process  80  each time a failure occurs, or, alternatively, each time the fail data register  34  has accumulated data relevant to a predetermined number of failures. In these embodiments, the integrated circuit  20  executes the step  82  by sending an interrupt to the automated tester  50  through the control line  52   n  (FIG. 3) that is dedicated to the selected integrated circuit  20 . In this embodiment, control passes to step  84  when the query task  86  determines that not all of the failure data have been downloaded. 
     FIG. 6 is a flow chart describing an integrated circuit speed testing process  90  in accordance with an embodiment of the present invention. The speed testing process  90  tests a group of integrated circuits  20  at M many different clock frequencies to determine a maximum clock frequency for reliable operation of each of the integrated circuits  20 . In a step  92 , the automated tester  50  of FIG. 3 sets an index variable m to 1. In a step  94 , the automated tester  50  sets an m TH  clock frequency f m  for a clock signal that is coupled to the input line CLK IN  of the clock buffer  38  in the integrated circuit  20  of FIG. 2. A step  96  invokes the process  60  of FIG.  4 . An optional step  98  invokes the process  80  of FIG.  5 . 
     A query task  100  determines if m=M; when m≠M, a step  102  increments m and control then passes back to the step  94 . When m=M, an optional step  104  may invoke the process  80  of FIG. 5 to download any stored failure data from the fail data registers  34  of the integrated circuits  20  that are being tested. Either the step  98  or the step  104  may be used to download failure data, however, the step  104  will download failure data for all M many tests, which may be separately stored, e.g., in each of the sub-registers FDR 1 , FDR 2  etc. of FIG. 2, while the step  98  downloads a group of failure data for each of the m clock frequencies f m  at the conclusion of the testing at each of the clock frequencies f m . In either case, the step  106  evaluates failure data for each of the integrated circuits  20  to determine a maximum clock frequency for each of the integrated circuits  20  to be able to operate reliably. A step  107  then returns the integrated circuits  20  to the normal mode of operation, and the process  90  then ends. 
     Speed testing of integrated circuits  20  (e.g., the process  90  of FIG. 6) differs from functional testing (e.g., the process  60  of FIG. 4) because speed testing is typically carried out with integrated circuits  20  that have previously been functionally tested and that are therefore known to be functional. In the case of integrated circuits  20  that are read-write memories such as DRAMs, the integrated circuits  20  have previously been tested and defective memory cells have previously been replaced as is conventional. Accordingly, speed testing may not need addresses for memory cells that fail, and may need only the total number of failures, such as memory cell failures, in order to determine a maximum error-free clock frequency for the integrated circuit  20 . When only the total number of failures is needed, the fail data register  34  may include a counter (when step  98  is used to download failure data) or a group of M many counters (when step  104  is used to download failure data). This may permit simplification of the on-chip testing circuit  22  for some applications. 
     FIG. 7 is a simplified block diagram of a portion of a computer system  120  including the integrated circuit  20  of FIG. 2 in accordance with an embodiment of the present invention. The computer system  120  includes a central processing unit  122  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The central processing unit  122  is coupled via a bus  124  to a memory  126 , a user input interface  128 , such as a keyboard or a mouse, and a display  130 . The memory  126  may or may not include a memory management module (not illustrated) and does include ROM for storing instructions providing an operating system and read-write memory for temporary storage of data. The processor  122  operates on data from the memory  126  in response to input data from the user input interface  128  and displays results on the display  130 . The processor  122  also stores data in the read-write portion of the memory  126 . 
     The integrated circuit  20  is particularly useful when it is a memory integrated circuit in the read-write memory portion of the memory  126 , because it may then allow the memory  126  to be tested more rapidly (e.g., using the process  60  of FIG. 4) while booting. Following testing of the memory integrated circuits, the processor  122  may extract the failure data from the memory  126  (e.g., using the process  80  of FIG. 5) in order to form a memory map describing the addresses of the defective memory cells. The memory map allows the processor  122  to avoid writing data to or reading data from the memory cells that were identified as being defective. 
     Examples of systems where the computer system  120  finds application include personal/portable computers, camcorders, televisions, automobile electronic systems, microwave ovens and other home and industrial appliances. 
     It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the appended claims.