Abstract:
A transconductor includes a first transistor having a first electrode electrically coupled to a first node, a control electrode electrically coupled to a first input voltage, and a second electrode connected to a third node; a second transistor having a first electrode electrically coupled to the first node, a control electrode electrically coupled to the first input voltage, and a second electrode connected to a fourth node; a third transistor having a first electrode electrically coupled to a second node, a control electrode electrically coupled to a second input voltage, and a second electrode connected to the fourth node; and a fourth transistor having a first electrode electrically coupled to the second node, a control electrode electrically coupled to the second input voltage, and a second electrode connected to the third node. Transconductance of the transconductor can be adjusted by changing relative widths of the first through fourth transistors.

Description:
BACKGROUND OF INVENTION 
     1. Field of the Invention 
     The present invention relates to a continuous-time filter, and more specifically, to a method of reducing area of a transconductor-capacitor (gm-C) filter. 
     2. Description of the Prior Art 
     A transconductor is a circuit that has a voltage as an input and a current as an output. Filters using transconductors and capacitors are often called gm-C filters, where gm represents a transconductance of the transconductor and C represents a capacitance of the capacitor. 
     Please refer to FIG.  1 . FIG. 1 is a block diagram of a gm-C filter unit  10  according to the prior art. The gm-C filter unit  10  comprises a transconductor  20  with a transconductance of gm 1 , a current summation unit  14 , and an integration capacitor C 1 . A positive input voltage VIP and a negative input voltage VIN are inputted to the gm-C filter unit  10 . 
     The difference between the two input voltages VIP and VIN can be defined as Vin, where Vin=VIP−VIN. Likewise, a positive output voltage VOP and a negative output voltage VON are output from the current summation unit  14 . The difference between the two output voltages VOP and VON can be defined as Vout, where Vout=VOP−VON. A ratio between Vout and Vin is directly proportional to the transconductance gm 1  of the transconductor  20  and inversely proportional to a capacitance C of the capacitor, as shown in Eqn.1 below.                Vout   Vin     ∝     gm1   C             (   1   )                                
     Therefore, if the ratio of Vout to Vin is to be lowered, the transconductance gm 1  of the transconductor  20  can be lowered, or the capacitance C of the capacitor C 1  can be raised. Unfortunately, it is difficult to give the transconductor  20  a very low transconductance value gm 1 . 
     Please refer to FIG.  2 A. FIG. 2A is a circuit diagram of the conventional transconductor  20  formed with NMOS transistors according to the prior art. The transconductor  20  contains first and second current sources  22  and  24 , which provide current to the transconductor  20  at nodes A and B, respectively. The transconductor  20  also contains a differential pair of transistors N 1  and N 2 . Gates of transistors N 1  and N 2  are controlled by VIP and VIN, respectively. The source of transistor N 1  is connected to current source  22  at node A and the source of transistor N 2  is connected to current source  24  at node B. A negative output current IN flows from a drain of transistor N 1  at node C and a positive output current IP flows from a drain of transistor N 2  at node D. Since transistors N 1  and N 2  have the same properties, transistors N 1  and N 2  are formed having identical width-to-length ratios, which can be represented as W/L. 
     The transconductor  20  further comprises a control transistor N 3  connected between the source of transistor N 1  at node A and the source of transistor N 2  at node B. The control transistor N 3  has a gate controlled by a control voltage VCTL. As is well known in the art, parasitic capacitors CP 1  and CP 2  inherently exist on the transconductor  20 , and create an excess positive phase on the negative and positive output currents IN and IP output from the transconductor  20 . In addition, an input capacitance is also associated with the transconductor  20 , and is a property of all transconductors. 
     Please refer to FIG.  2 B. FIG. 2B is a circuit diagram showing current values in the transconductor  20  of FIG.  2 A. Current I flows through the first current source  22  from node A to ground and also travels through the second current source  24  from node B to ground. For simple current analysis, control transistor N 3  can be modeled as a resistor with a current I 2  flowing from node A to node B. Therefore, a current of I+I 2  flows through transistor N 1  from node C to node A. On the other hand, a current of II 2  flows through transistor N 2  from node D to node B. The transconductance of the transconductor  20  will be defined as gmx. An equation for calculating the transconductance gmx is shown in Eqn.2 below.              gmx   =       IP   -   IN       VIP   -   VIN               (   2   )                                
     Therefore, transconductance gmx can be represented as a difference of currents IN and IP divided by ΔV, as shown in Eqn.3.              gmx   =           (     I   -     I      2       )     -     (     I   +     I      2       )         VIP   -   VIN       =     -       2              *     I      2         Δ      V                   (   3   )                                
     Where ΔV represents VIP−VIN. 
     Please refer to FIG.  2 C. FIG. 2C is a circuit diagram of a conventional transconductor  30  formed with PMOS transistors according to the prior art. The transconductor  30  of FIG. 2C is identical to the transconductor  20  of FIG.  2 A and FIG. 2B except that the NMOS transistors N 1 , N 2 , and N 3  have been replaced with PMOS transistors P 1 , P 2 , and P 3 . In addition, parasitic capacitors CP 3  and CP 4  and current sources  32  and  34  of the transconductor  30  are all connected to a voltage source V DD . Since the transconductor  30  operates in the same manner as the transconductor  20 , additional explanation will not be given for the transconductor  30 . 
     Please refer back to FIG.  1  and Eqn.1. As mentioned above, if the ratio of Vout to Vin is to be lowered, the transconductance gm 1  of the transconductor  20  can be lowered, or the capacitance C of the capacitor C 1  can be raised. Unfortunately, it is difficult to give the transconductor  20  a very low transconductance value gm 1  since the parasitic capacitors CP 1  and CP 2  inherently exist on the transconductor  20 , creating a zero and causing positive excess phase. This excess phase distorts the quality of the gm-C filter unit  10 , and is even more serious in high Q or low frequency applications. Therefore, the only alternative is to raise the size of the capacitor C 1 . 
     SUMMARY OF INVENTION 
     It is therefore a primary objective of the claimed invention to provide a transconductor circuit for use in low frequency applications and having a lower transconductance in order to solve the above-mentioned problems. 
     According to the claimed invention, a transconductor circuit includes a first current source electrically connected to a first node of the circuit for supplying a first input current to the circuit; a second current source electrically connected to a second node of the circuit for supplying a second input current to the circuit; a first transistor having a first electrode electrically coupled to the first node, a control electrode electrically coupled to a first input voltage, and a second electrode connected to a third node, the third node being used for outputting a first output current from the circuit; a second transistor having a first electrode electrically coupled to the first node, a control electrode electrically coupled to the first input voltage, and a second electrode connected to a fourth node, the fourth node being used for outputting a second output current from the circuit; a third transistor having a first electrode electrically coupled to the second node, a control electrode electrically coupled to a second input voltage, and a second electrode connected to the fourth node; and a fourth transistor having a first electrode electrically coupled to the second node, a control electrode electrically coupled to the second input voltage, and a second electrode connected to the third node. 
     It is an advantage of the claimed invention that the transconductor circuit has a lower transconductance and does not introduce any additional poles, zeros, input capacitance, or parasitic capacitance into the transconductor circuit. Therefore, the claimed invention transconductor circuit is well suited for use in low frequency applications. 
    
    
     These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings. 
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram of a gm-C filter unit according to the prior art. 
     FIG. 2A is a circuit diagram of a conventional transconductor formed with NMOS transistors according to the prior art. 
     FIG. 2B is a circuit diagram showing current values in the transconductor of FIG.  2 A. 
     FIG. 2C is a circuit diagram of a conventional transconductor formed with PMOS transistors according to the prior art. 
     FIG. 3A is a circuit diagram of a transconductor formed with NMOS transistors according to the present invention. 
     FIG. 3B is a circuit diagram showing current values in the transconductor of FIG.  3 A. 
     FIG. 3C is a circuit diagram of a transconductor formed with PMOS transistors according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     Please refer to FIG.  3 A. FIG. 3A is a circuit diagram of a transconductor  100  formed with NMOS transistors according to the present invention. The transconductor  100  contains first and second current sources  102  and  104 , which provide current to the transconductor  100  at nodes NA and NB, respectively. Unlike the prior art, the present invention transconductor  100  contains four transistors N 11 , N 12 , N 13 , and N 14  instead of the differential pair of transistors N 1  and N 2  used in the prior art transconductor  20 . Gates of transistors N 11  and N 12  are each controlled by VIP, while gates of transistors N 13  and N 14  are each controlled by VIN. The sources of transistors N 11  and N 12  are connected to current source  102  at node NA and the sources of transistors N 13  and N 14  are connected to current source  104  at node NB. 
     A negative output current IN flows from the transconductor  100  at node NC, and a positive output current IP flows from the transconductor  100  at node ND. A drain of transistor N 11  is connected to node NC, and a drain of transistor N 12  is connected to node ND. Similarly, a drain of transistor N 13  is connected to node ND, and a drain of transistor N 14  is connected to node NC. Thus, transistors N 11 , N 12 , N 13 , and N 14  are arranged in a cross-coupled shape. 
     The transconductor  100  further comprises a control transistor N 15  connected between node NA and node NB. The control transistor N 15  has a gate controlled by a control voltage VCTL. 
     Unlike the prior art, transistors N 11 , N 12 , N 13 , and N 14  do not all have the same width-to-length ratios. In a preferred embodiment of the present invention, the transistors N 11 , N 12 , N 13 , and N 14  have the same length, but have two different widths. Specifically, transistors N 11  and N 13  have widths of W 1  and transistors N 12  and N 14  have widths of W 2 . The widths W 1  and W 2  are chosen such that W 1 +W 2 =W, where W is the width of transistors N 1  and N 2  in FIG.  2 A. The gates of transistors N 11  and N 12  are each controlled by the same voltage source, and the sources of each are connected to the same node. Therefore, transistors N 11  and N 12  together have properties similar to transistor N 1  of FIG. 2A since the sum of the widths W 1  and W 2  of transistors N 11  and N 12  is equal to the width W of transistor N 1 . Likewise, transistors N 13  and N 14  together have properties similar to transistor N 2  of FIG. 2A since the sum of the widths W 1  and W 2  of transistors N 13  and N 14  is equal to the width W of transistor N 2 . 
     Like the prior art, parasitic capacitors CP 11  and CP 12  inherently exist on the transconductor  100 , and create an excess positive phase on the negative and positive output currents IN and IP output from the transconductor  100 . In addition, an input capacitance is also associated with the transconductor  100 . Since the pairs of transistors N 11 , N 12  and N 13 , N 14  have the same respective properties of single transistors N 1  and N 2  of the prior art, the parasitic and input capacitances have the same values in the present invention transconductor  100  as with the prior art transconductor  20  shown in FIG.  2 A. 
     Please refer to FIG.  3 B. FIG. 3B is a circuit diagram showing current values in the transconductor  100  of FIG.  3 A. The width W 1  of transistors N 11  and N 13  and width W 2  of transistors N 12  and N 14  are related to each other by a factor k, where k=W 1 /W 2 . Depending on the width of each transistor, a magnitude of current flowing through each transistor varies accordingly, as is shown in Eqn.4.              I   =     µ                   C   ox          W   L            (       V   GS     -     V   T       )     2               (   4   )                                
     Where μ is the mobility of the carriers in the transistor, C ox  is the gate capacitance per unit area, V GS  is the gate-source voltage, and V T  is the threshold voltage of the transistor. 
     Current I flows through the first current source  102  from node NA to ground and also travels through the second current source  104  from node NB to ground. As with the prior art, for simple current analysis, control transistor N 15  can be modeled as a resistor with a current I 2  flowing from node NA to node NB. Therefore, a current of I+I 2  flows from the sources of transistors N 11  and N 12  to node NA. This current is split up, with a current of [k/(k+1)]*(I+I 2 ) flowing through the transistor N 11  from node NC to node NA and a current of [1/(k+1)]*(I+I 2 ) flowing through the transistor N 12  from node ND to node NA. On the other hand, a current of II 2  flows from the sources of transistors N 13  and N 14  to node NB. This current is split up, with a current of [k/(k+1)]*(I−I 2 ) flowing through the transistor N 13  from node ND to node NB and a current of [1/(k+1)]*(I−I 2 ) flowing through the transistor N 14  from node NC to node NB. 
     The transconductance of the transconductor  100  will be defined as gmy. Based on Eqn.2, Eqns.5-7 will be used to calculate the transconductance gmy.              gmy   =       IP   -   IN       VIP   -   VIN               (   5   )               gmy   =         [         1     k   +   1            (     I   +     I                 2       )       +       k     k   +   1            (     I   -     I                 2       )         ]     -     
          [         k     k   +   1            (     I   +     I                 2       )       +       1     k   +   1            (     I   -     I                 2       )         ]         Δ      V               (   6   )               gmy   =               k   -   1       k   +   1            (     I   -     I                 2       )       -         k   -   1       k   +   1            (     I   +     I                 2       )           Δ      V       =           k   -   1       k   +   1            (       -   2     *   I                 2     )         Δ      V                 (   7   )                                
     Then, by substituting with Eqn.3, Eqn.8 shows the present invention transconductance gmy in terms of the prior art transconductance gmx.              gmy   =         k   -   1       k   +   1       *   gmx             (   8   )                                
     Analyzing Eqn.8 allows the significance of the present invention to be clearly seen. By choosing a value of k, such that k is greater than 1, the present invention transconductor  100  can have a lower transconductance than the transconductor  20  of the prior art. For example, suppose that W 1 =3*W/4 and W 2 =W/4. That is, the width of transistors N 11  and N 13  in the present invention transconductor  100  is three-fourths that of transistors N 1  and N 2  in the prior art transconductor  20 , and the width of transistors N 12  and N 14  in the present invention transconductor  100  is one-fourth that of transistors N 1  and N 2  in the prior art transconductor  20 . Since k=W 1 /W 2 , k=3 for this example. By substituting into Eqn.8, the transconductance gmy of the present invention is shown to be equal to one half of the transconductance gmx of the prior art. 
     Please refer to FIG.  3 C. FIG. 3C is a circuit diagram of a transconductor  200  formed with PMOS transistors according to the present invention. The transconductor  200  of FIG. 3C is identical to the transconductor  100  of FIG.  3 A and FIG. 3B except that the NMOS transistors N 11 -N 15  have been replaced with PMOS transistors P 11 -P 15 . In addition, parasitic capacitors CP 13  and CP 14  and current sources  202  and  204  of the transconductor  30  are all connected to a voltage source V DD . Since the transconductor  200  operates in the same manner as the transconductor  100 , additional explanation will not be given for the transconductor  200 . 
     Not only does the present invention transconductor  100  provide a transconductance that is a fraction of the prior art transconductor  20 , but also no additional poles or zeroes are introduced with the present invention transconductor  100  as compared to the prior art transconductor  20 . In fact, all other properties of the transconductor  100  will be the same as the transconductor  20  of the prior art since the only difference between them is each transistor having a width of W is replaced by two transistors with a total width of W. Therefore, the parasitic capacitance present in the present invention transconductor  100  will be equal to the parasitic capacitance present in the prior art transconductor  20 . Furthermore, since the input capacitance is only dependent on the size of the input MOS transistors, input capacitance will be the same in the prior art transconductor  20  and the present invention transconductor  100  since the total widths of the transistors is equal. 
     Since the input capacitance of the present invention transconductor  100  is the same as the input capacitance of the prior art transconductor  20 , no additional dummy transconductors will be needed to match the input capacitance of the transconductor  100  as compared to the prior art transconductor  20 . In addition, all values such as the current I, the current I 2 , the total width of the transistors, and the length of the transistors are the same in the present invention transconductor  100  as in the prior art transconductor  20 . 
     Referring back to FIG. 1, if the ratio of Vout to Vin is to be lowered, the transconductance gm 1  of the transconductor  20  can be lowered, or the capacitance C of the capacitor C 1  can be raised. With the present invention transconductor  100 , the transconductance can easily be lowered by a factor, thus avoiding the need to increase the size of the capacitor C 1 . Therefore, the present invention transconductor  100  allows the designer of an integrated circuit (IC) including a gm-C filter unit to save a great deal of area on the IC that would normally have to be used for forming a larger capacitor. The present invention is particularly useful in low frequency applications, where a low transconductance is desirable. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.