Abstract:
A matched filter having a set of registers to successively store a digital voltage. The matched filter includes a cumulative shift register, a number of exclusive-or circuits, and an analog adder. The cumulative shift register has a number of stages in which each stage has one bit corresponding to the shift register. The exclusive-or circuits each perform an exclusive-or function on each bit of the digital data and the one bit coefficient while the analog adder sums outputs from the exclusive-or circuits.

Description:
DETAILED DESCRIPTION OF THE INVENTION 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a matched filter circuit, particularly to a matched filter used in a signal reception apparatus of a direct sequence code division multiple access (DS-CDMA) communication system. 
     2. Prior Art 
     Recently, a spread spectrum communication system, particularly the DS-CDMA communication system, attracts attention in the field of mobile radio system and of cordless local area network (LAN). 
     In the DS-CDMA system, at a transmitter side, the transmission data is modulated and then spreaded by a PN-code, and at a receiver side, the received signal is despread by the PN-code so that the transmission data is reproduced. A sliding correlator or a matched filter is used for the despreading. The sliding correlator is small in circuit size but needs a long time for the correlation calculation. While, the matched filter is fast in correlation calculation but is rather big in circuit size. 
     The conventional matched filter consists of a charge coupled device (CCD), a surface acoustic wave (SAW) device, or a digital circuit. A matched filter is proposed in a Patent Publication Hei06-164320 by the inventors of the present invention, which consists of an analog circuit and is of high speed as well as low power consumption. The matched filter includes a sampling and holding circuit for holding a plurality of input analog signals as discrete data, a plurality of multiplication circuits for multiplying the analog signals by multipliers that are shifted and circulated and an adder for summing the multiplied data up. 
     The matched filter is of a large circuit size because a lot of sampling and holding circuits and peripheral circuits such as refreshing circuits are needed. 
     SUMMARY OF THE INVENTION 
     The present invention has an object to provide a matched filter circuit of small circuit size with preserving the characteristics of low power consumption. 
     A matched filter according to the present invention includes an A/D converter for converting successive analog input voltage signals into a digital voltage signals and calculates multiplication and addition of the successive digital signals. The addition is performed by an analog current addition circuit, an analog voltage addition circuit or a digital voltage addition circuit. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram showing a signal reception circuit of a DS-CDMA communication system using a first embodiment of a matched filter according to the present invention; 
     FIG. 2 is a general block diagram of the first embodiment; 
     FIG. 3 is a detailed block diagram showing the first embodiment; 
     FIG. 4 is a block diagram showing a current addition circuit of the first embodiment; 
     FIG. 5 is a circuit diagram showing the current addition circuit in FIG. 4; 
     FIG. 6 is a circuit diagram showing another current addition circuit; 
     FIG. 7 is a circuit diagram showing further another current addition circuit; 
     FIG. 8 is a circuit diagram showing a bit addition circuit used in the current addition circuit in FIG. 7; 
     FIG. 9 is a block diagram showing an analog voltage addition circuit; 
     FIG. 10 is a circuit diagram showing a sampling and holding circuit of the matched filter; 
     FIG. 11 is a circuit diagram showing a digital voltage addition circuit; 
     FIG. 12 is a circuit diagram showing a bit addition circuit of the digital voltage addition circuit in FIG. 11; 
     FIG. 13 is a circuit diagram showing another bit addition circuit of the digital voltage addition circuit in FIG. 11; 
     FIG. 14 is a circuit diagram showing further another bit addition circuit of the digital voltage addition circuit in FIG. 11; 
     FIG. 15 is a circuit diagram showing another digital voltage addition circuit; 
     FIG. 16 is a circuit diagram showing a bit addition circuit of the digital voltage addition circuit in FIG. 15; 
     FIG. 17 is a circuit diagram showing a final addition circuit of the digital voltage addition circuit in FIG. 15; 
     FIG. 18 is a circuit diagram showing another bit addition circuit of the digital voltage addition circuit in FIG. 15; 
     FIG. 19 is a circuit diagram showing a logic circuit of the bit addition circuit in FIG. 16; 
     FIG. 20 is a circuit diagram showing a bit addition circuit of another digital voltage addition circuit; 
     FIG. 21 is a circuit diagram showing a final addition circuit of the digital voltage addition circuit in FIG. 20; 
     FIG. 22 is a circuit diagram showing a variation of the bit addition circuit in FIG. 20; and 
     FIG. 23 is a block diagram showing a second embodiment of the matched filter circuit. 
    
    
     PREFERRED EMBODIMENTS 
     Hereinafter, preferred embodiments of matched filter circuits according to the present invention are described with reference to the attached drawings. 
     FIG. 1 is a block diagram showing a signal reception circuit of a DS-CDMA communication system using a first embodiment of a matched filter according to the present invention. 
     In FIG. 1,  1  is a quadrature detection circuit which detects an intermediate frequency (IF) signal and separates the IF signal into an in-phase component (I-component) and a quadrature component (Q-component).  31  and  32  are matched filters receiving I- and Q-components from the quadrature detector  1  through low-pass filters  21  and  22 , and despreads the components. Despread outputs of the matched filter circuits  31  and  32  are input to sampling and holding circuits 81  and  82  and to level detection circuit  4 . 
     The level detection circuit  4  calculates an electric power of the output from the matched filters  31  and  32 , and converts the electric power into a digital signal. An output of the level detection circuit  4  is averaged by recurrent integration for a time period of a plurality of symbols in a recurrent integration circuit  5 . Peak timing of peaks are extracted higher than a predetermined threshold in a peak detection circuit  6 . A number “n” of the peaks extracted is for example “4” at most. An output of the peak detection circuit  6  is input to a sampling and holding control circuit  7  which determines a sampling timing of the sampling and holding circuits  81  and  82 , synchronously to the phase of the peaks extracted. The I- and Q-components of the despread output corresponding to the peaks higher than the threshold are held in the sampling and holding circuits  81  and  82  in response to a control signal of the sampling and holding control circuit  7 . 
     FIG. 2 is a general block diagram of the first embodiment having a sampling and holding circuits  81 . Since the sampling and holding circuit  82  is similar to the sampling and holding circuit  81 , a description therefor is omitted. The sampling and holding circuit  81  includes n number of sampling and holding circuits SH 1  to SHn parallelly connected to inputs of the matched filter circuit  31 , a plurality of A/D converters which convert outputs of the sampling and holding circuits SH 1  to SHn into analog signals, and a multiplexer which selectively output one of outputs of the A/D converters to a coherent detection circuit  9 . 
     The coherent detection circuit  9  detects the peaks of the correlation by the matched filters  31  and  32 . These peaks are combined with synchronization by a rake combiner  10 , and outputs from an output interface (IF) as a demodulated data. 
     Therefore, correlation peaks of predetermined number of paths are sampled and held, and the electric power is decreased. 
     FIG. 3 is a detailed block diagram showing the first embodiment of the matched filters  31  and  32 . The matched filter MF includes an A/D converter (shown by A/D) receiving an analog input signal Ain corresponding to the I- or Q-component in FIG.  1 . An output of the A/D converter is input to data register sequences R 11  to R 1 n and R 21  to R 2 n parallelly. The data registers R 11  to R 1 n are controlled by a clock CLK 0  so that one and only one of the date registers samples the output of the A/D converter at a time. The data registers R 21  to R 2 n are controlled by a clock CLK 1  which is shifted by half an chip time from CLK 0  so that one and only one of the data registers holds the output of the A/D converter at one time. Therefore, a double sampling is performed. 
     Selectors SEL 1  to SELn and exclusive-or-gates XOR 1  to XORn are disposed corresponding to the data registers R 11  and R 1 n and corresponding to the data registers R 21  to R 2 n. The outputs of the date registers R 11  and R 21  are input to the selector SEL 1 , the outputs of the date registers R 12  and R 22  are input to the selector SEL 2 , and the outputs of the data registers R 1 n and R 2 n are input to the selectors CLKS SELn. Each of the selectors SEL 1  to SELn are controlled for selectively outputting one of the connected data registers R 11  to R 1 n, or R 21  to R 2 n. 
     The outputs of the selectors SEL 1  to SELn are input to the corresponding exclusive-or-gates XOR 1  to XORn. Each of the exclusive-or-gates XOR 1  to XORn is a circuit for calculating a logical exclusive-or of each bit of the digital data output from the corresponding data register with a one-bit data of PN code sequence. When the bit of the PN code sequence is “1”, corresponding outputs of the outputs from the SEL 1  to SELn are passed through the exclusive-or gate as they are. When the bit of the PN code sequence is “0”, each bit of the corresponding outputs of the outputs from the SEL 1  to SELn are reversed and output from the exclusive-or gate. 
     The PN code sequence is stored in a shift register SREG a last stage of which is fed back to its first stage. A clock CLKS synchronous with the clocks CLK 1  and CLK 2  is input to the shift register SREG such that the PN code sequence is shifted and circulated corresponding to the data input to the data registers from the A/D converter. 
     When a new PN code sequence is to be loaded in the shift register SREG, the new data is serially input to a data input terminal Din of the shift register SREG in response to the clock CLKS. 
     The outputs of the exclusive-or-gates are input to a current addition circuit ADD which outputs an analog signal A out  corresponding to a total summation of the outputs of the exclusive-or gate. The analog current signal A out  is output to the level detection circuit  4  and the sampling and holding circuits  81  or  82 . 
     The circuit size of the matched filter is smaller than the conventional circuit because the multiplication in the matched filter circuit MF is processed by the digital circuit. The electric power consumption is also decreased. The addition by the current addition circuit ADD is of high speed and of high accuracy. 
     If a single sampling is performed, only one of the data register sequences is used and the selectors SEL 1  to SELn are omitted. Or more than two data register sequences can be used for higher order over-sampling. 
     FIG. 4 is a block diagram showing a current addition circuit. The current addition circuit ADD includes a plurality of D/A converters D/A 1  to D/An corresponding to XOR 1  to XORn, each of which converts the digital voltage signal of each bit of the output of the corresponding exclusive-or-gate into an analog current signal. 
     When the outputs of XOR 1  to XORn are “k” bits digital data, the current signals are classified into “k” number of groups corresponding to “k” bits. The analog current signals corresponding to LSB are input to an analog bit addition circuit AADD 1 , the analog current signals corresponding to the second bit from LSB are input to an analog bit addition circuit AADD 1 , . . . , the analog current signals corresponding to MSB are input to an analog bit addition circuit AADDk. Outputs of the analog bit addition circuits AADD 1  to AADDk are inputs to a current mode weighting addition circuit WADD which multiplies the outputs by weights corresponding to the weights of bits and sums them up. An output Aout of an analog current signal corresponding to a total summation of the outputs of the exclusive-or circuits XOR 1  to XORn. 
     FIG. 5 is a circuit diagram showing the current addition circuit ADD in FIG.  4 . The number of bits of the outputs of the exclusive-or-gates XOR 1  to XORn is 4 bits as an example, that is, XOR 1  outputs 4 bits of b 10 , b 11 , b 12 , b 13 , XOR 2  outputs 4 bits of b 20 , b 21 , b 22 , b 23 , . . . , XORn outputs 4 bits of bn 0 , bn 1 , bn 2 , bn 3 . Each bit “bi,j−1” (jth bit of XORi) of these bits is input to a switch Ti,j which consists of a nMOS transistor and receives the bit at its gate. The switch Ti,j is closed when the bit bi,j−1 is high level. Each switch Ti,j is connected at the drain with a constant current source Iij which outputs a predetermined current when the corresponding switch Ti,j is closed. The source of the switches area commonly connected to an output Aout for outputting a total current flowing through the switches closed, as an analog value corresponding to the total summation. The constant current sources connected to the second bits bi 1  output a current twice as large as the constant current sources of the LSBDO. The constant current four times as large as sources connected to the third bits bi 2  output a current the constant current sources of the LSBDO. The constant current sources connected to the fourth bits bi 3  output a current eighth as that of the current of the constant current sources of the LSB. Therefore, the currents are weighted corresponding to the weight of bits of the binary number. 
     FIG. 6 is a circuit diagram showing another current addition circuit. Similar components to those in FIG. 5 are designated by the same references as in FIG.  5 . Each bit bi,j−1 of the outputs from XORj to XORn is connected to a pair of switches Tij 1  and Tij 2  consisting of nMOSs. The switches Tij 1  and Tij 2  are connected at their drains to a constant current source Iij. The switches Tij 1  and Tij 2  are connected at their sources to positive and negative terminals Ioutp and Ioutm of a subtraction circuit SUB. The bit bi,j−1 is directly connected to the switch Tij 1  and is connected through an inverter IVij to the switch Tij 2 . The switch Tij 1  is closed when bij−1 is high level and the switch Tij 2  is closed when bij−1 is low level. The subtraction circuit SUB subtract a total summation of current input to Ioutm from a total summation of current input to Ioutp such that an offset current is cancelled. A correlation peak has a level about an upper or a lower limit of the output of the subtraction circuit SUB. 
     FIG. 7 is a circuit diagram showing further another current addition circuit. Similar components to those in FIG. 5 are designated by the same references as in FIG.  5 . Each bit bi,j−1 of the outputs from XORj to XORn is connected to a switches Tij consisting of nMOS. The switch Tij are connected at its drain to a constant current source Iij at its source to a bit addition circuit ADDj. The bit addition circuit ADDj calculates a total summation of currents through the switches Tij (i=1 to n) closed, and multiplies the total summation by weights corresponding to the weights of bits. Since the weighting is performed by the bit addition circuits ADD 0  to ADD 3 , it is unnecessary to change the currents of the constant current sources and the circuit is simplified. 
     FIG. 8 is a circuit diagram showing a bit addition circuit ADD 0  used in the current addition circuit in FIG.  7 . Since the other bit addition circuits are similar to ADD 0 , descriptions therefor are omitted. The bit addition circuit ADD 0  consists of a current amplifying circuit, which includes a switch TT 41  receiving the total LSBs I 11  to In 1  of the outputs from XOR 1  to XORn. A switch TT 42  of the same polarity as TT 41  is connected at its gate to a gate of T 41 . The total LSBs are also input to the gate of TT 42 . A constant current sources II 41  and II 42  are connected to sources of the switches TT 41  and TT 42 , respectively. When the currents of the constant current sources II 41  and II 42  are different, a source current of the switch TT 42  is a current of the total summation of the input currents I 11  to I 1 n multiplied by          II                 42       II                 41                            
     (II 41 : current of the current source II 41 /II 42 : current of the current source  1142 ). In the circuit of FIG. 8, II 41 =II 42 . The bit addition circuits ADD 1  to ADD 3  have multipliers          II                 42       II                 41                            
     of “2”, “4” and “8”, respectively. 
     FIG. 9 is a block diagram showing an analog voltage addition circuit. In this circuit, a digital parallel counters PCNT is provided which count number of bits of “1” in the input digital data from the corresponding exclusive-or circuits XOR 1  to XORk. The digital parallel counter may be substituted by a circuit shown in the Technical Report of IEICE, CAS94-103, VLD94-119, ICD94-227 (1995-03), “Design of a Multiplier with Parallel Counters Using NeuMOS” written by Tomomi NAKAGAWA et. al. 
     FIG. 10 is a circuit diagram showing the sampling and holding circuit SH 1  in FIG.  2 . Since sampling and holding circuits SH 2  to SHn are similar to SH 1 , descriptions therefor are omitted. The sampling and holding circuit SH 1  includes MOS transistors TT 51  and TT 52 , constant current sources II 51  and II 52 , a switch SW. A drain and gate of the MOS transistor TT 51  are connected with each other, and the switch SW is connected between the gate of TT 51  and the gate of TT 52 . The switch SW is controlled to be switched by a control signal from the sampling and holding control circuit  7 . 
     FIG. 11 is a circuit diagram showing a digital voltage addition circuit ADD. The outputs b 10 ˜b 1 k, b 20 ˜b 2 k, . . . , bn 0 ˜bnk from the exclusive-or circuits XOR 1  to XORn are input to bit-addition circuits BAD 0  to BADk, respectively, of the adder ADD. Outputs of the bit-addition circuits BAD 0  to BADk are input to shifters BSF 0  to BSFk, respectively. Each of the bit-addition circuits BAD 0  to BADk sums corresponding bits of the total exclusive-or circuits XOR 1  to XORn up, for example, BAD 0  sums b 10 , b 20 , . . . , bn 0  up. Each of the shifter BSFO to BSFk performs bit-shifting of corresponding outputs of the bit-addition circuits BAD 0  to BADk by one or more bits according to weights of the bits input to the shifter. The numbers of bits to be shifted are 0, 1, 2, . . . , k for weights 2 0 , 2 1 , . . . , 2 k  of bit groups b 1 o to bno, b 2 o to b 2 n, . . . , and bk 0  to bkn. Outputs of the shifters BSF 0  to BSFk are summed by a final adder FAD up. 
     The bit-addition circuits BAD 0  to BADk may be constructed by the digital parallel counters which count number of bits of “1” in the input digital data from the corresponding exclusive-or circuits XOR 1  to XORk, as mentioned above. The digital parallel counter may be substituted by the circuit shown in the Technical Report of IEICE, CAS94-103, VLD94-119, ICD94-227 (1995-03), “Design of a Multiplier with Parallel Counters Using NeuMOS” written by Tomomi NAKAGAWA et. al. 
     FIG. 12 shows a threshold type bit-addition circuit corresponding to the above bit-addition circuit BAD 0 . There are provided a plurality of threshold type bit-addition circuits corresponding to number (k+1) of input bits. One threshold type bit addition circuit includes m number of thresholding circuits TH 1  to THm.              m   =       int        [       log        (     n   -   1     )         log                 2       ]       +   1             (   1   )                                
     BAD 0  generates a m bit digital data as a total summation of input LSBs. The threshold circuit THm outputs Bm as MSB of the digital data, THm−1 outputs the second bit Bm−1, . . . , TH 1  outputs the LSB B 1 . A capacitive array consisting of a plurality of parallel capacitances is connected to the thresholding circuits TH 1  to THm. The total LSBs b 10  to bn 0  of the exclusive-or circuits XOR 1  to XORn are input to the total thresholding circuits, The thresholding circuits TH 1  to THm−1 of the second bit and the higher bits receive outputs from upper thresholding circuits TH 2  to THm through inverters. The inverted outputs of the outputs B 1  to Bm are designated B′ 1  to B′m, here. The thresholding circuit THm−2 receives b 10  to bn 0 , B′m and B′m−1, . . . , TH 1  receives b 10  to bn 0  and B′m to B′ 2 . 
     The thresholding circuits TH 1  to THm include inverters or comparators I 11  to Im 1 , respectively, corresponding to output bits B 1  to Bm, and the capacitive array is connected to inputs of these inverters. Outputs of the inverters I 11  to I 1 m are connected to inverters I 21  to I 2 m, respectively. The outputs B 1  to Bm are output from the inverters I 21  to I 2 m, the outputs B′ 1  to B′m are output from the inverters I 11  to I 1 m. 
     In the thresholding circuit TH 1 , the capacitive array includes capacitances C 01  to C 0 n of the same capacities corresponding to a threshold of TH 1 , which are connected to B 1 ,  0  to Bn 0 . Capacitances CB 12  to CB 1 m connected to B′ 2  to B′m have capacities corresponding to thresholds of thresholding circuits TH 2  to THm. The inverters I 11  to I 1 m have a threshold VT=Vdd/2, and a relationship between capacitances is as in the formula (2).                                C01   =     C02   =     …   =     C0n   =       2      CB1m     =           2   2        CB1m     -   1     =     …   =       2     m   -   1          CB12                           ⋮                       CB   m     -   1     ,     1   =     …   =     Cm   -   1         ,       n   -   1     =     Cm   -   1       ,     n   =       2      CBm     -   1       ,   m                       CBm1   =     …   =   Cm       ,       n   -   1     =   Cmn                   (   2   )                                
     The outputs of TH 1  to THm are expressed by the formula (3) using a Gaussian notation [ ]. When the input exceeds the threshold VT, the thresholding circuits output “1”, otherwise “0”. Other bit-addition circuits BAD 1  to BADk are similar to BAD 0 , and descriptions therefor are omitted.                    Bm   =     [         ∑     i   =   1     n            b     i   ,   0       ×     C     m   ,   j               ∑     j   =   1     n          C     m   ,   j           ]                   Bm   -   1     =     [           ∑     i   =   1     n            b     i   ,   0       ×     C       m   -   1     ,   j           +       B   m   ′     ×     CB       m   -   1     ,   m                 ∑     j   =   1     n          C     m   ,   j         +     CB       m   -   1     ,   m           ]               ⋮             B0   =     [           ∑     i   =   1     n            b     i   ,   0       ×     C     0   ,   j           +       ∑     j   =   1     m            B   j   ′     ×     CB     1   ,   j                   ∑     j   =   1     n          C     0   ,   j         +       ∑     j   =   2     m          CB     i   ,   j             ]                   (   3   )                                
     FIG. 13 shows a variation of one of the threshold type bit-addition circuit BAD 0 . In this bit-addition circuit BAD 0 , the outputs from the exclusive-or circuits are indirectly input to the capacitive array, that is, the outputs are input to selectors SEL 41  to SEL 4 n and outputs of these selectors are input to the capacitive array. The selector SEL 4 n receives a reference high voltage VH and a reference low voltage VL such that one of the reference voltages is output in response to the input. By converting the input voltage into the reference voltage, the calculation accuracy of the bit-addition circuit BAD 0 . The outputs of the selector SEL 41  to SEL 4 n are input to the capacitances of the capacitive array; and inverted outputs of the threshold circuits are input through similar selectors (SELBm−1, m, . . . , SELB 1 m, SELB 1 ,m−1, . . . , SELB 1 , 1 ) to the capacitive arrays of the lower bits. 
     The selectors SEL 4 m 1  to SEL 4 mn outputs the reference voltage Vref corresponding to the threshold voltage, when the inverter Im 1  is short-circuited at its input and output. Thus, the reference voltage Vref is input to the total capacitances of the capacitive array for refreshing the residual electric charge such that the calculation accuracy is improved. 
     FIG. 14 shows the second variation of the bit-addition circuit. In this embodiment, one selector is connected to a pair of output bits, that is, there are p=n/2 selectors SEL 51  to SEL 5 p. The selector SEL 51  is controlled to output a three-levels voltage (VH, Vref, VL) corresponding to two input bits b 10  and b 20 . The number of inputs of the capacitive array becomes a half of that in the above embodiment by the multi-level input. 
     FIG. 15 shows the second embodiment using an analog type adder instead of the digital type adder. The adder ADD includes a analog-bit-adder ABAD 0  to ABADk corresponding to outputs b 10  to b 1 k, b 20  to b 2 k, . . . , bn 0  to bnk, respectively, each of which performs analog addition. 
     FIG. 16 shows one bit-addition circuit ABAD 0 . The bit-addition circuit ABAD 0  includes selectors SEL 71  to SEL 7 n receiving bits b 10  to bn, 0 , each of which outputs VH or VL alternatively. The calculation accuracy is high due to the reference voltage conversion. The outputs of the selectors SEL 71  to SEL 7 n are input to capacitances C 71  to C 7 n, corresponding to the selectors, of a capacitive array. An output of the capacitive array is input to an inverting amplifier  17  output of which is fed through a feedback capacitance Cf 7  back to its input. The capacitances C 71  to C 7 n are equal in their capacities, and the capacitance Cf 7  has a capacity equal to the total capacity of the capacitances C 71  to C 7 n. Thus the output BS 0  of the bit-addition circuit is a bit-addition shown in the formula (4). In the formula (4), Vb is a threshold voltage of the inverting amplifier.                    BS0   =       -         ∑     i   =   1     n            (       bi0   ·   VH     -       bi0   _     ·   VL       )     ·   C7i       Cf7       +     2   ·   Vb                   =       -         ∑     i   =   1     n          (       bi0   ·   VH     -       bio   _     ·   VL       )       n       +     2   ·   Vb                     (   4   )                                
     The bit-addition circuits are similar to ABAD 1  to ABADk, so the descriptions therefor are omitted. 
     The selectors SEL 71  to SEL 7 n are allowed to output Vref, and the C 71  to C 7 n and C 75  are refreshed by inputting Vref to I 7  when Cf 7  is short-circuited. The residual electrical charge is canceled and the calculation accuracy is improved by the refreshing. 
     FIG. 17 shows the final adder AFAD in FIG.  15 . The final adder AFAD includes a capacitive array consisting of a capacitances C 80  to C 8 k. An output of the capacitive array is input to a MOS inverting amplifier  18 , an output of I 8  is fed through a feedback capacitance CfF to its input. The capacitances have capacities corresponding to weights of the bits BS 0  to BSk, and a capacity of the CfF is equal to the total capacity of the capacitances C 80  to C 8 k. Thus, an output Out of the final adder AFAD is a weighted addition as shown in the formula (5).              Out   =         -         ∑     j   =   0     k          BSj   ·   C8j       CfF       +     2   ·   Vb       =         ∑     j   =   0     k            ∑     i   =   1     m            (       bij   ·   VH     -       bij   _     ·   VL       )     ·   C8j           n   ·   CfF                 (   5   )                                
     The total capacity of the capacitances decreases and the circuit size becomes small by the weighting at the final adder AFAD. 
     FIG. 18 shows a variation of a bit-addition circuit ABAD 0 . A plurality of selectors SEL 91  to SEL 9 p are provided each corresponding to pairs of exclusive-or circuits. The selector SEL 91  outputs a 3-levels voltage equivalent to 2 bits input b 10  and b 20 . The selector SEL 91  is controlled by the 2 bits input. The selector SEL 91  receives the high reference voltage VH, medium reference voltage Vref and the low reference voltage VL, and outputs VL when b 10 =b 20 =1, Vref when one is “1” and the other is “0”, and VL when b 10 =b 20 =0. 
     FIG. 19 is a circuit diagram showing a logic circuit which performs the calculation of the 3-levels selector SEL 9 P. The output bits b 10  and b 20  are input to an AND gate GH, a NOR gate GL and an EX-OR gate, parallelly. These logic gates controls switches SWH, SWL and SWREF, respectively, which receive VH, VL and Vref, respectively. Thus, the 3-levels output is realized, and number of input lines decreases. 
     FIGS. 20 to  22  show circuits for another adder of digital type which performs bit addition and the final addition by circuitry components of resistances. FIG. 20 shows a bit-addition circuit ABAD 0 . The bit-addition circuit ABAD 0  includes selectors SEL 11 , 1  to SEL 11 n each of which outputs VH or VL alternatively. Outputs of the selectors SEL 11 , 1  to SEL 11 n are connected to resistances R 11 , 1  to R 11 n, respectively, of a resistance array. An output of the resistance array is input to an inverting amplifier I 11  consisting of a MOS inverter, an output of which is fed through a resistance Rf 11  to its input. The resistances R 11 , 1  to R 11 n have the same resistance value and the resistance Rf 11  has a resistance value equal to the total resistance of the resistances R 11 , 1  to R 11 n. Thus, an output of the bit-addition circuit Baad 0  is expressed as in the formula (6)              BS0   =         -           ∑     i   =   1     n          (       bi0   ·   VH     -       bi0   _     ·   VL       )       R11i     Rf11       +     2   ·   Vb       =       -         ∑     i   =   0     n          (       bi                   0   ·   VH       -         bi                 0     _     ·   VL       )       n       +     2   ·   Vb                 (   6   )                                
     Other bit-addition circuits ABAD 1  to ABADk are similar to ABAD 0 , so description therefor are omitted. 
     FIG. 22 is a circuit diagram showing a variation of the bit-addition circuit ABAAD 0  including selectors SEL 131  to SEL 13 p. The selector SEL 131  receives input bits b 10  and b 20  as control signals and outputs a 3-levels output. The reference voltages VH, VL and Vref are input to the selector SEL 131  which selectively outputs one of the reference voltages in response to the input bits b 10  and b 20 . When b 10 =b 20 =1, VH is output, when b 10 ≠b 20 , Vref is output, and when b 10 =b 20 =0, VL is output. 
     It may also possible to combine bit-addition circuits of capacitance-type (FIGS. 5 to  7 , FIG.  16  and FIG. 18) and a final adder (FIG. 21) of a resistance-type, or to combine bit-addition circuits of resistance-type (FIGS. 20 and 22) and a final adder (FIG. 21) of a capacitance-type. 
     FIG. 23 is a block diagram showing a second embodiment of the matched filter MF. An analog input voltage Ain is converted into a digital voltage by an analog to digital converter (A/D) and then input to first stages of shift-registers SFREG 1  and SFREG 2 . The shift-registers SFREG 1  and SFREG 2  shift the input voltages toward the last stages in response to the clock pulses CLK 1  and CLK 2 , respectively. A spreading code PN is input from a register REG to exclusive-or circuits XOR 1  to XORn. Differently from the first embodiment, the spreading code PN is not shifted. Outputs of the shift registers SFREG 1  and SFREG 2  are input to selectors SEL 1  to SELn similar to those in the first embodiment. Similarly to the first embodiment, exclusive-or circuits XOR 1  to XORn and adder ADD are provided.