Abstract:
The invention relates to a linearizer circuit which corrects inherent nonlinearity of a capacitive pressure sensor. The linearizer is based on an operational amplifier configuration comprising a feedback network of switched capacitor type (C 0 -C 5 ,SW 1 -SW 8 ) which is switched between a first switching phase (A) and a second switching phase (B). In such a switched capacitor configuration, dc gain of the operational amplifier configuration in the second switching phase (B) can be adapted to realize a linearization function required to substantially linearize a non-linear capacitance-pressure characteristic of a capacitive pressure sensor (C) when the capacitive pressure sensor is connected to be part of the feedback network.

Description:
FIELD OF THE INVENTION  
       [0001]     The invention relates to a linearizer circuit which corrects inherent nonlinearity of a capacitive pressure sensor.  
       BACKGROUND OF THE INVENTION  
       [0002]     In variable capacitive transducer or capacitive pressure sensors, capacitance varies with the pressure applied to the sensor and can be detected by an appropriate electronic circuitry. A typical capacitive pressure sensor is highly nonlinear. One example of a capacitance-pressure relation is  
               C   ⁡     (   p   )       =       C   00     +     kC   0     +       C   0       1   -         C   0     κ     ⁢   p         +       aC   0       1   -         C   0       b   ⁢           ⁢   κ       ⁢   p                   (   1   )             
        where C 00 , C 0 , and κ are independent statistical parameters of a capacitive pressure sensor. Parameters k, a, and b are constants for a given sensor type. The applied absolute pressure is p.  FIG. 1  shows a capacitance vs. pressure characteristic with parameter values C 00 =0.65 pF, C 0 =3.25 pF, κ=4180 kPa*pF, k=0, a=0.808 and b=1.410.        
 
         [0004]     In a pressure measurement system utilizing this kind of capacitive sensor, nonlinearity must be corrected to obtain an output signal proportional to pressure. In other words, the circuit must have some property which realizes the inverse function for the function presented in Equation 1 and  FIG. 1 . The solution of p from Equation 1 leads to a complex expression involving square root, hardly being feasible from the point of view of circuit design. In any case, a complicated electronic circuitry is required. Even if the capacitance-pressure relation were approximated by an equation simpler than Equation 1, it would still be difficult to design an electronic circuit which outputs signal p(C) when sensor capacitance is C.  
       DISCLOSURE OF THE INVENTION  
       [0005]     An object of the present invention is thus to provide a feasible linearizer circuit for correcting nonlinearity of a capacitive pressure sensor.  
         [0006]     The object of the invention is achieved by a linearizer circuit according to the independent claim. Preferred embodiments of the invention are disclosed in the dependent claims.  
         [0007]     The present invention is based on an operational amplifier configuration comprising a feedback network of switched capacitor type, clock means for controlling the feedback network of switched capacitor type between a first switching phase and a second switching phase. In such a switched capacitor configuration, dc gain of the operational amplifier configuration in the second switching mode can be adapted to realize a linearization function required to substantially linearize a non-linear capacitance-pressure characteristic of a capacitive pressure sensor when the capacitive pressure sensor is connected to be part of the feedback network. Capacitor values required for capacitance value C of the capacitive pressure sensor can be calculated easily. In an embodiment of the invention, the feedback network of switched capacitor type includes adjustable capacitors for adapting the linearizer circuit to parametric variations among different capacitive pressure sensors. In the circuit configuration according to the present invention, the switched capacitor technique offers a way to implement the required linearizing function for a capacitive pressure sensor with a simple circuit. It also easily realizes a capacitance-to-voltage conversion necessary with a capacitive sensor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     In the following, the invention will be described in greater detail by means of exemplary embodiments and with reference to the attached drawings, in which  
         [0009]      FIG. 1  is a graph showing an example of a capacitance vs. pressure characteristic of a capacitive pressure sensor;  
         [0010]      FIG. 2  is a schematic diagram of a circuit according to the present invention;  
         [0011]      FIG. 3  is a timing diagram showing waveforms of switch control signals A and B;  
         [0012]      FIG. 4  is a schematic diagram of another circuit according to the present invention;  
         [0013]      FIG. 5  is a timing diagram showing waveforms of switch control signals A, B, C and D; and  
         [0014]      FIGS. 6 and 7  are schematic diagrams of still further circuits according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]     For purposes of describing the exemplary embodiments, the right-hand side expression in Equation 1 can be accurately approximated by a simpler one:  
                 C   ⁡     (   p   )       =       C   00     +         C   0     ⁢     p   0           p   0     -   p           ,           (   2   )             
        where C00, C0 and p0 are fitting parameters. Then, solving p from Equation 2, we have  
                     p   ⁡     (   C   )       =       p   0     ⁡     (     1   -       C   0       C   -     C   00           )                   =       p   0     ⁢       C   -     C   00     -     C   0         C   -     C   00                       =         C   -     C   00     -     C   0           C     p   0       -       C   00       p   0           .                   (   3   )             
       
 
         [0017]     Equation 3 gives a function necessary for linearizing a capacitive pressure sensor. In the following, examples of linearizer circuits of the invention realizing the function of Equation 3 are described.  
         [0018]      FIG. 2  is a schematic diagram of a circuit according to the present invention realizing the function of Equation 3. In  FIG. 2 , the linearizer circuit is constructed using only one operational amplifier A 1  and five switched capacitors C 0 , C 1 , C 2 , C 3 , C 4 , and C 5 , as well as sensor capacitance C. Switching devices SW 1  to SW 8  associated with the capacitors C 0  to C 5  are controlled by switch control signals A and B. Whenever signal A or B is active, the corresponding switches SW 1 , SW 4 , SW 5 , SW 8 , or SW 2 , SW 3 , SW 6 , SW 7  are closed. Signals A and B must be non-overlapping, i.e. they must never be active at the same time, to prevent any loss of charge in the capacitors and momentarily shortcuts. Waveforms A and B are shown in  FIG. 3 , where the higher level means an active phase (corresponding switches are closed). Waveforms A and B are running continuously and provided by a specific digital circuit. From now on, the times when A is high are called “clock phase A” and the times when B is high are called “clock phase B”. VIN is an input signal, which only needs to be a dc voltage. VOUT is an output signal, which in steady state has a constant value VOUTA in each clock phase A, and another constant value VOUTB in each phase B. AGND is an analog ground, which should be approximately half of the supply voltage.  
         [0019]     In switch phase A, a first terminal N 1  of the capacitor C 1  is switched to an input voltage VIN by the switch SW 1 , and a second terminal N 2  of the capacitor C 1  is switched to a node N 5  and thereby to an inverting input OAINM of the operational amplifier A 1  by the switch SW 4 . A first terminal of the capacitor C 2  is connected to a node N 1 , and a second terminal N 3  is switched to the AGND by the switch SW 5 . A first terminal of the capacitor C 0  is connected to a node N 3 , and a second terminal N 6  is connected to an output N 10  of the operational amplifier A 1  by the switch SW 8 . A first terminal N 4  of the capacitor C 3  is connected to the inverting input of the operational amplifier A 1 , and a second terminal N 9  is connected to the output N 10 . A first terminal N 7  of the capacitor C 4  is connected to a node N 2 , and a second terminal N 8  is connected to the output node N 10  by the switch SW 8 . The capacitive pressure sensor C is connected between the nodes N 7  and N 6 .  
         [0020]     In switch phase B, the first terminal N 1  of the capacitor C 1  is switched to the AGND by the switch SW 2 , and the second terminal N 2  of the capacitor C 1  is switched to the AGND by the switch SW 3 . The first terminal of the capacitor C 2  is connected to the node N 1 , and the second terminal N 3  is switched to the node N 5  by the switch SW 6 . The first terminal of the capacitor C 0  is connected to the node N 3 , and the second terminal N 6  is connected to the AGND by the switch SW 7 . The first terminal N 4  of the capacitor C 3  is connected to the node N 5 , and the second terminal N 9  is connected to the output N 10 . The first terminal N 7  of the capacitor C 4  is connected to the node N 2 , and the second terminal N 8  is connected to the AGND by the switch SW 7 .  
         [0021]     Next it is shown how the steady-state output voltage VOUTB in clock phase B as a function of the sensor capacitance C realizes the function of Equation 3. All voltages are referred to as AGND. The operational amplifier is assumed to be ideal such that the inverting input OAINM remains at AGND voltage. When a new clock phase begins, the charges stored in the capacitors during the previous phase are redistributed.  
         [0022]     In clock phase A, a charge conservation law formulated at the inverting input of the operational amplifier A 1  is 
 
 C 1* V IN+ C 3*( V OUT A   −V OUT B )+( C 4+ C )* V OUT A =0  (4) 
 
 In phase B, the charge conservation yields 
 
 C 2*(0− V IN)+ C 3*( V OUT B   −V OUT A )+ C 0*(0− V OUT A )=0  (5) 
 
         [0023]     The solution from Equations 4 and 5 is  
                 VOUT   B     =           (       C   ⁢           ⁢   3     +     C   ⁢           ⁢   4     +   C     )     ⁢   C   ⁢           ⁢   2     -       (       C   ⁢           ⁢   3     +     C   ⁢           ⁢   0       )     ⁢   C   ⁢           ⁢   1             (       C   ⁢           ⁢   3     +     C   ⁢           ⁢   4     +   C     )     ⁢   C   ⁢           ⁢   3     -     C   ⁢           ⁢   3   ⁢     (       C   ⁢           ⁢   3     +     C   ⁢           ⁢   0       )             ⁢     
     ⁢     VIN   =           C   ⁢           ⁢   3     +     C   ⁢           ⁢   4   ⁢         (       C   ⁢           ⁢   3     +     C   ⁢           ⁢   0       )     ⁢   C   ⁢           ⁢   1       C   ⁢           ⁢   2         +   C             -     (       C   ⁢           ⁢   0     -     C   ⁢           ⁢   4       )       ⁢   C   ⁢           ⁢   3       C   ⁢           ⁢   2       +         C   ⁢           ⁢   3       C   ⁢           ⁢   2       ⁢   C         ⁢   VIN               (   6   )             
 
         [0024]     The dc gain in phase B is  
                   G   =       VOUT   B     VIN                 =         C   ⁢           ⁢   3     +     C   ⁢           ⁢   4   ⁢         (       C   ⁢           ⁢   3     +     C   ⁢           ⁢   0       )     ⁢   C   ⁢           ⁢   1       C   ⁢           ⁢   2         +   C             -     (       C   ⁢           ⁢   0     -     C   ⁢           ⁢   4       )       ⁢           ⁢   C   ⁢           ⁢   3       C   ⁢           ⁢   2       +         C   ⁢           ⁢   3       C   ⁢           ⁢   2       ⁢   C                     =           K   1     +   C         K   2     +       K   3     ⁢   C         .                   (   7   )             
 
         [0025]     The dependency of dc gain G on sensor capacitance C is of the same type in Equations 3 and 7, which proofs that the gain in phase B can implement the required linearization function of Equation 3.  
         [0026]     To calculate the values for the adjustable capacitors C 0 , C 1  and C 3 , a linear gain-pressure relationship must first be defined: 
 
 G ( p )= G   1   p−G   0   (8) 
        and some values for coefficients G 1  and G 0  must be fixed.        
 
         [0028]     The sensor capacitance C solved from Equation 7 gives  
             C   =             K   2     ⁢   G     -     K   1         1   -       K   3     ⁢   G         .             (   9   )             
 
         [0029]     Combining Equations 8 and 9 we have  
                     C   ⁡     (   p   )       =           K   2     ⁢     G   1     ⁢   p     -       K   2     ⁢     G   0       -     K   1         1   -       K   3     ⁢     G   1     ⁢   p     +       K   3     ⁢     G   0                       =               K   2       K   3       ⁢   p     -           K   2     ⁢     G   0       +     K   1           K   3     ⁢     G   1                 1   +       K   3     ⁢     G   0             K   3     ⁢     G   1         -   p       .                   (   10   )             
 
         [0030]     Equation 2 is here rewritten in another form:  
                     C   ⁡     (   p   )       =       C   00     +         C   0     ⁢     p   0           p   0     -   p                     =             C   00     ⁢     p   0       +       C   0     ⁢     p   0       -       C   00     ⁢   p           p   0     -   p       .                   (   11   )             
 
         [0031]     Assuming that the sensor parameters C 00 , C 0  and p 0  are known, we can calculate K 1 , K 2  and K 3  from Equations 10 and 11 as follows:  
                       1   +       K   3     ⁢     G   0             K   3     ⁢     G   1         =       p   0     ⇒     K   3                   =     1       G   1     ⁡     (       p   0     -       G   0       G   1         )                     =     1         G   1     ⁢     p   0       -     G   0                       (   12   )                       K   2     =       K   3     ⁡     (     -     C   00       )                   =     -       C   00           G   1     ⁢     p   e       -     G   0                         (   13   )                       -           K   2     ⁢     G   0       +     K   1           K   3     ⁢     G   1           =           C   00     ⁢     p   0       +       C   0     ⁢     p   0         ⇒     K   1                   =         -     (       C   00     +     C   0       )       ⁢     p   0     ⁢     K   3     ⁢     G   1       -       K   2     ⁢     G   0                     =           -     (       C   00     +     C   0       )       ⁢     p   0     ⁢     G   1       +       C   00     ⁢     G   0               G   1     ⁢     p   0       -     G   0                     =       -     C   00       -     C   0     -           G   0     ⁢     C   0             G   1     ⁢     p   0       -     G   0         .                     (   14   )             
 
 Now the adjustable capacitor values from Equation 7 are:  
               C   ⁢           ⁢   3     =       K   3     ⁢   C   ⁢           ⁢   2             (   15   )                 C   ⁢           ⁢   0     =         C   ⁢           ⁢   4     -       K   2     ⁢       C   ⁢           ⁢   2       C   ⁢           ⁢   3           =       C   ⁢           ⁢   4     -       K   2       K   3                   (   16   )                 C   ⁢           ⁢   1     =           (       C   ⁢           ⁢   3     +     C   ⁢           ⁢   4     -     K   1       )     ⁢   C   ⁢           ⁢   2         C   ⁢           ⁢   3     +     C   ⁢           ⁢   0         .             (   17   )             
 
         [0032]     In practice, the circuit in  FIG. 2  may suffer from offset voltage of the operational amplifier A 1 . Due to the offset, the voltage at the node OAINM differs from the AGND voltage, adding an unwanted component to the output voltage VOUT.  
         [0033]     One possible approach to cancel the offset is presented in  FIG. 4 . The basic circuit is similar to the circuit shown in  FIG. 2 , and therefore only differences are described below. An example of timing for clock signals A, B, C and D is shown in  FIG. 5 . Signals A and B are similar to those shown in  FIGS. 2 and 3 . Signals C and D are non-overlapping signals, i.e. they are never active at the same time. Signal D becomes active before the clock phase A begins but does not become inactive until a predetermined first portion of the clock phase B expires. Signal C is active for the remaining portion of the clock phase B up to the next clock phase A. From now on, the times when D is high are called “clock phase D” and the times when C is high are called “clock phase C”.  
         [0034]     One terminal of an offset cancellation capacitor COF is connected at the inverting input of the operational amplifier A 1 . The other terminal N 11  is switched to the node N 5  by means of a switch SW 9  in the clock phase D, and to the analog ground AGND by means of a switch SW 10  in the clock phase C. A switch SW 11  is provided between the second terminal N 9  of the capacitor C 3  and the output node N 10  such that the capacitor C 3  is switched to the output node N 10  in the clock phase D. A switch SW 12  is provided between the inverting input and the output of the amplifier A 1  such that the input and output are shortcut in the clock phase C. As a result, the capacitor COF stores the offset voltage in the clock phase C. The other capacitors keep their previous voltages. In the clock phase D, the capacitor COF keeps the potential of the node N 5  (virtual ground node VRTGN) at the AGND potential, thereby cancelling the offset.  
         [0035]     The switches SW 1  to SW 12  for the switched capacitor operation can be implemented using various semiconductor switch technologies. In such a case, the switches are realized with metal-oxide-semiconductor (MOS) transistors, and they may cause errors to the capacitor voltages due to a phenomenon called charge injection. When a MOS transistor is turned on, a charge is generated in its channel. This charge is injected from surrounding nodes, possibly changing the capacitor voltages in the circuit of  FIG. 2  or  4 . When the transistor is turned off, the charge is injected out of the transistor.  
         [0036]     In an embodiment of the invention, charge injection errors are decreased by means of dummy switches, which receive charges coming from other switches and which can be added to any nodes in the circuits above, wherever necessary.  
         [0037]      FIGS. 6 and 7  show examples of a dummy switch SW D  connected, on the right side of the capacitor C 3 , to a node N 9  in order to cancel the errors caused by the neighbouring switch SW 11  to the voltage of the capacitor C 3 . In  FIG. 6 , the dummy switch SW D  is left open at the other end. In  FIG. 7 , the dummy switch SW D  is shorted at both ends. Both of these configurations may be used, but they may require different transistor sizing. In both cases, the dummy switch SW D  is a controlled signal XD which is the complement of signal D controlling the switch SW 11 . Similarly, a dummy switch can be added to any circuit node to cancel errors caused by a neighbouring switch.  
         [0038]     The circuits presented above are only examples, and various modifications and changes can be made. For example, the circuits may be simplified by removing the capacitor C 4 , as it is just parallel to the capacitive pressure sensor C, but at the expense of less freedom to select values for the capacitors C 0 , C 1  and C 3 . As another example, the operational amplifier A 1  can also be an operational transconductance (OTA) amplifier. The invention and its embodiments are not limited to the examples described above but may vary within the scope of the claims.