Abstract:
An apparatus comprising a circuit having one or more inputs. The one or more inputs may be configured to provide a device identification (ID) of one or more different device IDs. The one or more inputs may allow implementation of the circuit with one of the one or more different device Ids.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a method and/or architecture for IEEE compliant JTAG devices generally and, more particularly, to a method and/or architecture for soft code for multiple device IDs for IEEE compliant JTAG devices. 
   BACKGROUND OF THE INVENTION 
   Implementing JTAG compliant devices on integrated LLW circuits (ICs) is an industry trend. The Institute of Electrical and Electronics Engineers, Inc. (IEEE) publishes a variety of specifications, such as the IEEE 1149.1 standard, published in 1990, which is hereby incorporated by reference in its entirety. An identification (ID) code is an optional instruction in the IEEE 1149.1 standard which requires a device ID (i.e., a 32-bit register). The IEEE standard 1149.1 permits implementation of a single device ID, while remaining in compliance with the JTAG specification. 
   Referring to  FIG. 1 , a block diagram of a circuit  10  illustrating a conventional JTAG system is shown. The circuit  10  comprises a logic circuit  12 , a multiplexer  14  and a flip-flop  16 . The multiplexer  14  has an input  18  that receives the signal from the logic circuit  12  and an input  20  that receives the signal S 1 . The logic circuit  12  is configured to present either a “1” or a “0” to the multiplexer  14  and cannot be changed. The logic block  12  limits functionality of the JTAG system  10 . 
   The multiplexer  14  also has an input  22  that receives a signal SHIFT. The signal SHIFT selects either the signal received at the input  18  (“0” or “1”) or the signal S 1  received at the input  20  to be presented to an input  24  of the flip-flop  16 . The flip-flop  16  also has a clock input  26  that receives a clock signal CLK. The flip-flop  16  has an output  28  that presents an output signal S 0 . 
   When a design is configured to target a single device, the device is assigned an unique device ID. The IEEE 1149.1 specification describes how to implement the unique device ID in a JTAG device. When one design is configured to target multiple devices, the same metal options and bond options are implemented as when targeting a single device. The metal options and bond options are generally considered hard coded. 
   The logic device  12  is hard coded. Additionally, the hard coded logic block  12  is implemented to provide the device ID. The hard coded device ID logic block  12  (using-metal option or bond options) can not be changed after the device  12  has been fabricated. Hard coded device IDs cannot be used in designs which provide multiple configurations using mark options (i.e., no metal options/bond options). Mark inputs can be implemented to provide a configurable device ID, while metal options/band options provide a permanent non-configurable device ID. 
   Typically, metal options or bond options are used to configure a single design. Conventional JTAG systems implement the same options (metal or bond) to code the ID registers. Device IDs, once hard coded into the ID registers inside JTAG devices, cannot be changed after the device has been fabricated. Conventional hard coded device IDs are not applicable for designs that provide multiple configurations using mark options (no metal options/bond options). 
   SUMMARY OF THE INVENTION 
   The present invention concerns an apparatus comprising circuit having one or more inputs. The inputs may be configured to provide a device identification (ID) of one or more different device IDs. The one or more inputs may allow implementation of the circuit with one of the one or more different device IDs. 
   The objects, features and advantages of the present invention include providing a method and/or architecture for soft coding of multiple device IDs for IEEE compliant JTAG devices that may (i) be configured to different device IDs after an integrated circuit (IC) has been fabricated; (ii) be transparent to users; and/or (iii) provide IEEE compliant JTAG devices. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
       FIG. 1  is a block diagram illustrating a conventional JTAG device; 
       FIG. 2  is a block diagram illustrating a preferred embodiment of the present invention; 
       FIG. 3  is a detailed block diagram illustrating an implementation of the present invention in a FIFO; and 
       FIG. 4  is a detailed block diagram illustrating an implementation of the present invention in a JTAG device. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention provides a method and/or architecture to generate IEEE compliant JTAG devices with unique device IDs that may be used for multiple configuration devices implementing mark options. Certain designs, such as FIFO applications may require IEEE compliant JTAG devices. Certain FIFO designs may not have multiple metal options/bond options configured  6 L to handle ID code registers for multiple configuration devices. Therefore, mark options may be implemented in FIFO designs to provide multiple configuration devices. The multiple device IDs required for multiple configuration devices may be provided by the mark options. 
   Referring to  FIG. 2 , a block diagram of a circuit  100  illustrating a preferred embodiment of the present invention is shown. The circuit  100  generally comprises a logic circuit  102 , a multiplexer  104  and a memory element  106 . In one example, the logic block  102  may be implemented as an AND gate. In another example, the memory element  106  may be implemented as a “D” type flip-flop. However, the logic block  102  and the memory element  106  may be implemented as other appropriate devices in order to meet the criteria of a particular implementation. 
   The logic block  102  may have a number of inputs  108   a - 108   n  that may each receive a signal (e.g., MARKa-MARKn). The signals MARKa-MARKn may be generated externally to the circuit  100 . In one example, the signals MARKa-MARKn may be implemented as mark option inputs. In another example, the signals MARKa-MARKn may be implemented as configuration pins. The logic block  102  may present a signal to an input  110  of the multiplexer  104 . Additionally, the multiplexer  104  may have an input  112  that may receive a signal (e.g., S 1 ). The multiplexer  104  may also have an input  114  that may receive a signal (e.g., SHIFT). The multiplexer  104  may be configured to present a signal to an input  116  of the memory element  106 . The signal SHIFT may select either the signal received at the input  110  or the signal received at the input  112  to be presented to the memory element  106 . The signal SHIFT may control the multiplexer  104 . The memory element  106  may have an input  118  that may receive a clock signal (e.g., CLK). The memory element  106  may have an output  120  that may present an output signal (e.g., S 0 ). The circuit  100  may allow a single device to have multiple device IDs while implemented in an IEEE compliant JTAG device. 
   The external mark options MARKa-MARKn may be used to soft code device IDs. The soft code device IDs may allow a single device to be configured with a number of device IDs. The soft code device IDs may be transparent to customers, while still retaining IEEE 1149.1 compliance in the JTAG specification. The IEEE standard 1149.1 was published in 1990, and is hereby incorporated by reference in its entirety. The following TABLE 1 illustrates soft coding of different mark options (e.g., MARKa-MARKn) for the multiple device IDs: 
   
     
       
             
             
             
             
             
           
         
             
                 
               TABLE 1 
             
             
                 
                 
             
             
                 
               MARKa 
               MARKn 
               Device 
               Device ID 
             
             
                 
                 
             
           
           
             
                 
               GND 
               GND 
               5 M FIFO 
               0C402069 
             
             
                 
               VDD 
               VDD 
               1 M FIFO 
               0C401069 
             
             
                 
               VDD 
               GND 
               ¼ M FIFO 
               0C400069 
             
             
                 
                 
             
           
        
       
     
   
   For example, a FIFO may have two mark option pins (e.g., MARKa and MARKn) for configuring the FIFO. The mark pins MARKa and MARKn may allow the FIFO to implement a number of different device configurations/types. The input pins MARKa and MARKn may be implemented to soft code device IDs as shown in the following TABLE 2: 
   
     
       
             
             
             
             
             
           
         
             
                 
               TABLE 2 
             
             
                 
                 
             
             
                 
               MARKa 
               MARKn 
               Device 
               Device ID 
             
             
                 
                 
             
           
           
             
                 
               0 
               0 
               5 M FIFO 
               0C402069 
             
             
                 
               1 
               1 
               1 M FIFO 
               0C401069 
             
             
                 
               1 
               0 
               ¼ M FIFO 
               0C400069 
             
             
                 
                 
             
           
        
       
     
   
   Soft coded device IDs can cooperate with mark options and enable a single device to have multiple device IDs. The circuit  100  may allow the mark options MARKa-MARKn to be transparent to customers. Additionally, the circuit  100  may allow JTAG devices (e.g., the circuit  100 ) to remain IEEE compliant. 
   Referring to  FIG. 3 , an example implementation circuit (or system)  200  of the present invention is shown. The circuit  200  may be implemented as a FIFO memory. The FIFO  200  generally comprises a controller  202 . The controller  202  may be similar to the circuit  100 . In one example, the controller  202  may be implemented as a JTAG controller. However, the controller  202  may be implemented as another appropriate device in order to meet the criteria of a particular implementation. 
   The controller  202  may control a configuration (e.g., device ID) of the FIFO  200 . The controller  202  may receive a number of signals (e.g., TDI, TCK, TMS and TRST). In one example, each of the signals test data in (TDI), test clock (TCK), test mode select (TMS) and test reset (TRST) may be received from dedicated input pin. In another example, each of the signals TDI, TCK, TMS and TRST may be received from a multi-level input pin. Additionally, the controller  202  may receive a number of mark inputs (to be described in connection with FIG.  4 ). The controller  202  may generate a signal (e.g., test data out TDO). The signal TDO may indicate a device ID of the FIFO  200 . The controller  202  may present a particular device ID (e.g., the signal TDO) in response to the signals TDI, TCK, TMS and TRST. 
   Referring to  FIG. 4 , a detailed block diagram of the controller  202  is shown. The controller  202  may have a number of mark input pins (not shown). The mark input pins may allow configuration for a device ID of a particular circuit. Additionally, the mark inputs may be transparent to a user. The controller  202  generally comprises a register  204 . The register  204  may be implemented as an identification register. The register  204  may capture bits of data that may identify an ID code of a particular device. Once the ID of the device is captured, the ID code may be shifted out of the register  204  via the pin TDO. The JTAG controller  202  may allow implementation of multiple IDs of a particular device. 
   The circuit  100  may allow a device to have multiple device IDs. The multiple device IDs may be provided by a number of mark options. The circuit  100  may enable a single physical device to be configured to one of a number of different devices. The multiple configurations may be provided by the mark pins. The circuit  100  may soft code a device ID register and allow a JTAG device to remain compliant with the IEEE standard. 
   The mark pins may allow the single device to fulfill different customer requirements. The circuit  100  may be configured is to different device IDs (e.g., different configurations) after an initial IC fabrication. The circuit  100  may be transparent to customers. The circuit  100  may allow JTAG devices to remain IEEE compliant. The circuit  100  may be implemented to soft code device IDs inside a JTAG device implementing mark options. Additionally, the circuit  100  may be implemented to configured a single device with multiple device IDs. However, the circuit  100  may require significant design/test overhead. 
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.