Abstract:
A pixel within an array of pixels in which each pixel cell includes circuitry for generating its own DC balance data by utilizing the display data that is transferred to the pixel from an external source. Each pixel cell includes an initial storage node that branches into two separate storage nodes, the first of the branched nodes being used to store data that is used for display by the pixel and the second of the branched nodes being used to generate and hold the DC balance data. Once the display data has been displayed by the pixel, the DC balance data is multiplexed to the pixel and the pixel is driven according to the DC balance data. Generating the DC balance data within a pixel cell, instead of transferring DC balance data to the pixel cell from an external source, reduces the data transfer load to the pixel cell by approximately one-half.

Description:
TECHNICAL FIELD 
     The invention relates generally to liquid crystal displays and more particularly to a liquid crystal display capable of storing video data. 
     DESCRIPTION OF THE RELATED ART 
     Liquid crystal displays (LCDs) have become a popular form of electronic displays. LCDs are composed of liquid crystals which are positioned between two pieces of glass. The crystals can be aligned such that in a normal state, light easily propagates through the liquid crystals. However, when an electrical field is present, the liquid crystals alter their alignment, greatly reducing the amount of light passing through the crystals. By applying an electrical field at different “pixels” or discrete regions on the LCD, an image can be formed on the LCD. An LCD can have more than 1,228,800 pixels. The resolution of the LCD is directly related to the density of pixels in the LCD array. 
     There are a number of alternative types of liquid crystals utilized commercially in LCDs. A first major type is referred to as twisted nematic liquid crystals. LCDs with twisted nematic liquid crystals produce pictures with high contrast. However, LCDs with twisted nematic liquid crystals have relatively narrow viewing angles, as well as slow molecular rotation times. A second type of liquid crystals is referred to as ferroelectric liquid crystals. LCDs with ferroelectric liquid crystals have wider viewing angles, because of their small cell gaps of 1 to 2 microns. In addition, ferroelectric liquid crystal displays (FLCDs) have a faster molecular rotation speed, typically in the range of 50 to 100 micro seconds. 
     A typical FLCD includes a display chip covered with a structure containing the ferroelectric liquid crystals, an illuminator, and viewing optics. Operation of a conventional FLCD is supported by a host computer and an external frame buffer memory. In order to display a color image on the FLCD, a frame of image data is transferred from the host computer to the external frame buffer memory. The external frame buffer memory supplies multi-bit pixel data to each pixel in the FLCD. The color image represented by the frame of pixel data is displayed on the FLCD as a result of a sequential process of loading each pixel of the FLCD with its multi-bit pixel data from the external frame buffer memory. Typically, each pixel in the FLCD has a single-bit storage register  10  and a pixel driver  12 , as depicted in FIG.  1 . Therefore, the external frame buffer memory must supply a series of single bits of pixel data to the pixels through the bit line  14  and word line  16  in order to display a particular color with a particular intensity at each pixel. The number of bits required for each pixel of FLCD to produce a desired color at a desired intensity may be 24 or more bits (e.g., three colors with eight bits of grayscale per color). In addition to the data that is required to display an image, equal and opposite DC balance data is required to be delivered to each pixel after the pixel has displayed a desired image. DC balance is utilized to extend the life of the liquid crystals and is well known in the art. While DC balance data is not visually displayed by the FLCD, the data is still supplied to the pixel from external circuitry. 
     Depending upon the transferred pixel data, light from the illuminator is either reflected to or deflected from the viewing optics. The pixels in the FLCD act as time-modulated micro mirrors in concert with the illuminator to produce the color image, which is determined by the values of the bits of pixel data. The quality of the color image is determined by the density of the pixels, the number of color-related bits within the pixel data transferred to each pixel, and the data transfer rate of the pixel data to the pixels. To display a high quality color image on the FLCD having the single-bit storage registers, a high bandwidth data link from the external frame buffer memory to the individual pixels is required for transferring the display data and the DC balance data. However, high bandwidth data links are expensive, potentially noisy, and require a great amount of power. 
     U.S. Pat. No. 4,432,610 to Kobayashi et al. (hereinafter Kobayashi) entitled “Liquid Crystal Display Device,” describes LCDs with various storage elements in the pixels. All of the storage elements described in Kobayashi are single-bit storage elements. A concern with single-bit storage registers in an LCD is the need to continually supply bits of pixel data at a high data transfer rate to develop a high resolution image on the LCD. Unless a sufficiently high data transfer rate is achieved, there will be limitations on the size of the LCD array, the display frame rate, and/or the number of bits of pixel data that may be transferred per frame. These physical limits affect the quality of the display image. 
     Another LCD with single-bit storage elements is described in U.S. Pat. No. 5,471,225 to Parks entitled “Liquid Crystal Display with Integrated Frame Buffer.” The single-bit storage elements in the LCD of Parks are static random access memory (SRAM) cells comprised of three transistors and two resistors. The SRAM cells allow the LCD to display an image for an indefinite amount of time without refreshing. However, the data transfer rate concern identified above for the LCDs of Kobayashi exists for the LCD of Parks. 
     U.S. Pat. No. 5,627,557 to Yamaguchi et al. (hereinafter Yamaguchi) entitled “Display Devices,” describes an improved pixel for an LCD. The pixel includes circuitry for storing a first bit of display data while displaying a second bit of display data. In addition, Yamaguichi discloses a circuit integrated into the pixel cell that includes a sample-and-hold capacitor for holding a negative scanning signal which may be used for DC balancing. While DC balance data is held simultaneously with display data in the pixel cell, the DC balance data is created by external drive circuitry and transferred from an external frame buffer through the bit line of the pixel cell. 
     In view of the expense of high bandwidth links between the frame buffer and the display pixels and the large volume of display data required to generate high resolution video images, what is needed is a pixel cell that enables a reduction in the requirements of transferring display data and DC balance data to a pixel cell. 
     SUMMARY OF THE INVENTION 
     A method and an apparatus for reducing data transfer requirements to a pixel cell involve an array of pixels in which each pixel cell includes circuitry for generating its own DC balance data by utilizing display data that is transferred to the pixel from an external frame buffer or other source of the display data. Each pixel cell includes an initial storage node that branches into two separate storage nodes, with the first of the branched nodes being used to store data that is used to determine the display condition of the pixel and the second of the branched nodes being used to generate and hold the DC balance data. Once the display data has been utilized for display purposes by the pixel, the DC balance data is multiplexed to the pixel and the pixel is driven according to the DC balance data. By generating the DC balance data within the pixel cell, instead of transferring DC balance data to the pixel cell from an external source, the data transfer load to the pixel cell is reduced by approximately one-half. 
     In a preferred embodiment, a pixel cell with two bits of memory and DC balance generation capability includes an input storage block, a frame transfer block, a drive storage block, a DC balance block, a multiplexer, and a pixel driver. The input storage block includes a circuit for storing a bit of display data that is received from an external display buffer through a write bit line and a write word line. The input storage block consists of three NMOS transistors arranged to create a dynamic storage node. In addition, the input storage block provides a global reset signal that resets the dynamic storage node upon activation of the reset signal. Operation of the input storage block involves sending a pulse to a selected write word line, allowing a bit to be read into the storage node from the write bit line. 
     The frame transfer block is a circuit that allows an entire frame of data to be transferred simultaneously to all of the pixel drivers in an array of pixel cells, instead of scrolling the data to the pixel drivers. A frame transfer is triggered by a global transfer signal that is received from a global timing block. The frame transfer block consists of two NMOS transistors and one dynamic storage node. The two NMOS transistors are located on two separate conductive paths that split from the dynamic storage node, with one conductive path connecting to the drive storage block and the other conductive path connecting to the DC balance block. 
     The drive storage block is a dynamic storage node that holds a bit of display data that is utilized by the pixel driver to drive a pixel. The drive storage block is formed by a current path that extends from the drain of a transistor in one branch of the frame transfer block to the gate of a transistor in the pixel driver. The drive storage block functions to carry display data from the input storage block to the pixel driver. The combination of the bit of display data stored in the input storage block and the bit of display data stored in the drive storage block creates a pixel cell with two bits of memory. 
     The DC balance block generates DC balance data from the branch of the display data that is received from the input storage block. The DC balance block stores the DC balance data until it is time to drive the respective pixel. The DC balance block consists of four NMOS transistors connected to create two dynamic storage nodes. The first storage node receives the display data during the frame transfer and the second storage node stores the DC balance data that is generated in response to the display data that is received during frame transfer. 
     The multiplexer block controls when the drive storage data and the DC balance data will be received by the pixel driver. The multiplexer block consists of two NMOS transistors with one transistor operating to reset the drive storage block to a known state and the other transistor operating as a switch between the DC balance block and the drive storage block. In order to control the pixel driver from the DC balance block, an invert signal is pulsed on one of the two transistors, transferring the DC balance data to the pixel driver. 
     The pixel driver block receives display data from the drive storage block and DC balance data from the DC balance block. The pixel driver controls the voltage supplied to a pixel in accordance with the received display data or DC balance data. The pixel driver block consists of one NMOS transistor and one PMOS transistor connected to form a dynamic storage node. An induced transition or non-transition of the dynamic storage node within the pixel driver determines the voltage with which the liquid crystal will be driven. 
     Operation of a single pixel cell requires a series of reset and precharge stages, followed by reading of display data and transferring of the display data to the pixel driver. The initial reset/precharge stage involves resetting the drive storage block to a known state, resetting and precharging the DC balance block to known states, and precharging the pixel driver to a known state. Writing data to the input storage block involves pulsing the write word line and allowing a bit of data to pass from the write bit line to the input storage block. If the bit of data is a “1” the input storage node will be charged high and, conversely, if the bit of data is a “0” the input storage node will be charged low. Because the pixel cell operation is slightly different depending on whether a “1” or a “0” is written to the input storage block, the two situations are discussed separately with the “1” bit case described first and the “0” bit case described second. 
     To transfer the stored “1” bit of display data from the input storage block to the pixel driver, the transistors of the global transfer block are activated by pulsing the global transfer signal. Pulsing the global transfer signal transfers a high signal simultaneously to the drive storage block and the DC balance block. The high signal at the drive storage block activates a transistor in the pixel driver and transitions the storage node of the pixel driver from precharged high voltage to a low voltage. The transition of the storage node in the pixel driver from high to low is equivalent to driving the pixel with a “1” bit. The high signal at the drive storage block is also simultaneously transferred to the DC balance block, causing the first storage node within the block to transition from low to high. The transition from low to high activates a transistor and drops the second node from high to low, thereby generating the DC balance data that is subsequently transferred to the pixel driver. 
     After the “1” bit has been displayed by the pixel driver for the desired time, it is necessary to drive the pixel according to the DC balance data. Instead of writing the DC balance data from the write line as is known, the pixel cell utilizes the DC balance data that is generated internally to drive the pixel cell. Utilizing the DC balance data requires a reset/precharge operation in which the drive storage node is dropped to a known state and the pixel driver is charged to a known state. Upon completion of the reset/precharge operation, the newly generated DC balance data is transferred from the DC balance block to the pixel driver by pulsing an invert signal within the multiplexer. The invert signal releases the low charge held at the second node of the DC balance block to the pixel driver and since the node is low, the charge does not have any effect on the precharged node of the pixel driver. As a result, the pixel is driven at a voltage that is the inverse of the display data, thereby accomplishing DC balancing with data that was generated within the pixel cell. 
     In the case where a “0” bit is initially written to the input storage block, when the global transfer signal is activated, the drive storage block and the DC balance block simultaneously receive low signals. The low signal received by the drive storage block is transferred to the pixel driver, but does not cause the storage node of the pixel driver to transition from high to low. Likewise, the low signal transferred to the DC balance block does not cause the second storage node within the DC balance block to transition from high to low. 
     After the “0” bit has been displayed by the pixel driver for the desired time interval, the DC balance reset/precharge operation is initiated. As with the case of a displayed “1” bit, the DC balance reset/precharge operation involves resetting the drive storage block to a known state and precharging the pixel driver to a known state. Once the DC balance reset/precharge operation is complete, an invert signal is pulsed in the multiplexer and the DC balance data stored in the second node of the DC balance block is transferred to the pixel driver. Since the storage node within the DC balance block is charged high, the pixel driver is transitioned from high to low, thereby driving the pixel with an opposite signal as the display data. 
     Advantages of the invention include a greater illumination efficiency over a 1-bit display pixel, the potential elimination of color flicker, a reduced display frame rate, and a reduction in the frame buffer to pixel cell interface bandwidth requirement by approximately one-half. Another advantage of the 2-bit pixel over a 1-bit pixel is that the 2-bit pixel allows a change in operation from a scrolling display to a global transfer display. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a depiction of a pixel having a 1-bit storage register and a pixel driver in accordance with the prior art. 
     FIG. 2 is a block diagram of a single pixel cell having 2-bit storage capability as well as internal DC balance generation in accordance with the invention. 
     FIG. 3 is a circuit diagram of a single pixel cell having 2-bit memory and DC balance generation capability in accordance with the invention. 
     FIG. 4 is a depiction of a preset stage of a single pixel cell in accordance with the invention. 
     FIG. 5 is a depiction of a data writing stage of a single pixel cell in accordance with the invention. 
     FIG. 6 is a depiction of a frame transfer stage of a single pixel cell in accordance with the invention. 
     FIG. 7 is a depiction of a DC balance preset stage of a single pixel cell in accordance with the invention. 
     FIG. 8 is a depiction of a DC balance stage of a single pixel cell in accordance with the invention. 
     FIG. 9 is a depiction of a frame transfer stage of a single pixel cell in accordance with the invention. 
     FIG. 10 is a depiction of a DC balance stage of a single pixel cell in accordance with the invention. 
     FIG. 11 is a process flow diagram of a preferred method for driving a pixel in accordance with the invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 is a block diagram of a single pixel cell  20  in accordance with the invention. The pixel of FIG. 2 is one pixel cell in a matrix of pixels that are combined to form a display device. Each block of FIG. 2 is described individually, followed by a description of the overall operation of a pixel cell in accordance with the invention. 
     As is known in the art of liquid crystal displays (LCDs), data is supplied to each pixel cell from external drive circuitry and/or display buffers  24  through a write bit line (wbl)  26  and a write word line (wwl)  28 . The write bit line, also known as the data line, supplies voltage to the pixel that represents display data as “1”s and “0”s. The write word line, also known as the scanning signal line, provides a mechanism to control when data is read from the write bit line. An entire display includes a matrix of write bit lines and write word lines connected to the array of pixel cells to provide individual control of each pixel in the display. 
     The global timing block  32  is a conventional periphery system that controls the timing of all of the pixels in the display device. In addition to conventional timing signals, the global timing block generates a global reset signal, a global transfer signal, and an invert signal for each pixel. The global reset, global transfer, and invert signals are specific to the invention and are described in detail below. 
     The input storage block  30  includes a circuit that stores a bit of data. The bit of data, referred to throughout as the input bit, is received from the display buffer  24  and is the next bit of display data that will be utilized to drive the pixel. A preferred pixel cell circuit layout  60  of the pixel cell of FIG. 2 is depicted in FIG. 3, with the input storage block being identified by dashed line box  70 . The input storage block consists of three NMOS transistors Q 1 , Q 2 , and Q 3 , arranged to create a dynamic storage node at a 1 . The source of Q 1  is connected to the write bit line  66  and the gate of Q 1  is connected to the write word line  68 . The drain of Q 1  is connected to the source of Q 2  and to the source of Q 3 . The gate of Q 2  is connected to receive the global reset signal and the drain of Q 2  is connected to ground. Q 3  functions as a storage capacitor, with the gate of Q 3  being connected to V DD  (typically five volts) and the drain being connected to node b 1 . 
     Operation of the input storage block involves pulsing the write word line, allowing a bit to be read from the write bit line. When the write bit line is high, node a 1  goes to high and is held high by Q 3 . The global reset signal (reset) is used to initialize a display for frame blanking or for test and calibration of the pixel array, where the entire array may be activated to a known state without the need to be connected to a source of display data. The global reset signal is “global” because it has the ability to reset the input storage block of all the pixels in the array. 
     Referring back to FIG. 2, the frame transfer block  36  is a circuit that allows an entire frame of data to be transferred simultaneously to all pixels in an array, instead of scrolling the data to pixels as is conventional in the art. A frame transfer is triggered by a global transfer signal received from the global timing block  32 . A preferred circuit layout for the frame transfer block  36  is depicted in FIG. 3 by dashed line box  76 . The frame transfer block consists of two NMOS transistors Q 4  and Q 5  and one dynamic storage node b 1 . As can be seen, the drain of Q 3  is split into two separate conductive paths  72  and  74  at node b 1 . One conductive path  72  travels from the input storage block to Q 4  and to a drive storage block  40  and  80 , and the other conductive path  74  travels from the input storage block to Q 5  and to a DC balance block  44  and  84 . The gates of both Q 4  and Q 5  are triggered by the global transfer signal, which allows the data at node b 1  to be transferred to nodes c 1  and d 1 . That is, if node b 1  is high when the global transfer signal is pulsed, then nodes c 1  and d 1  will be high, and if node b 1  is low when the global transfer signal is pulsed, then nodes c 1  and d 1  will remain at a precharged low state. Enabling display data to be transferred to pixel drivers on a frame basis eliminates the need for blank frames and allows color bits to be interleaved to minimize color flicker. 
     Referring to FIG. 2, the drive storage block  40  is a storage node that holds the bit of display data that is utilized by the pixel driver  52 . The bit of display data is referred to as the drive bit and is preferably represented as either a high voltage or a low voltage. The drive storage block is depicted in FIG. 3 by dashed line box  80  and does not include any transistors. The drive storage block identified by dynamic storage node c 1  is formed by the current path that extends from the drain of Q 4  to the gate of Q 11 . In operation, node c 1  can be preset low by a pulse from the signal pc 2  of transistor Q 10  and when node c 1  is high, the gate of Q 11  is activated. The combination of the input bit stored at the input storage block and the display bit stored at the drive storage block provides two bits of memory for the pixel cell. 
     The DC balance block  44  shown in FIG. 2 generates DC balance data from display data that is received from the input storage block  30  and then stores the DC balance data until it is time to drive the pixel. A preferred circuit layout for the DC balance block is depicted in FIG. 3 by dashed line box  84  and consists of four NMOS transistors Q 6 , Q 7 , Q 8 , and Q 9  connected to create the dynamic storage nodes d 1  and e 1 . Node d 1  is at the junction of the drain of Q 5 , the source of Q 6 , and the gate of Q 7  and node e 1  is at the junction of the drain of Q 8 , the source of Q 7 , and the source of Q 9 . Transistors Q 6  and Q 8  are activated by a global precharge (pc) signal. Precharging of the DC balance storage block involves pulsing the pc signals of Q 6  and Q 8 , which has the effect of pulling node d 1  low (to ground) and charging node e 1  high (to V DD ). 
     The multiplexer block  48  shown in FIG. 2 controls when the drive storage data and the DC balance data will be received by the pixel driver  52 . A preferred circuit layout for the multiplexer is depicted in FIG. 3 by dashed line box  88  and consists of two NMOS transistors Q 9  and Q 10 . In operation, the pixel driver is normally controlled by the drive storage block  40 . In order to control the pixel driver from the DC balance block, the pc 2  signal is first pulsed to ensure that node c 1  is low. After pulsing pc 2 , the inv signal is pulsed and the data at node e 1  is sensed by the pixel driver. When e 1  is initially high, pulsing the inv signal activates the gate of Q 11 , dropping node o 1  to low and when e 1  is initially low, pulsing the inv signal does not activate the gate of Q 11 . 
     The pixel driver block  52  shown in FIG. 2 receives display data from the drive storage block  40  and DC balance data from the DC balance block  44  and controls the voltage supplied to the pixel in accordance with the received data. A preferred circuit layout for the pixel driver block is depicted in FIG. 3 by dashed line box  92  and consists of one NMOS transistor and one PMOS transistor connected to form a dynamic storage node o 1 . As shown, node o 1  is formed at the junction of the source of Q 11  and the drain of Q 12 . The gate of Q 11  is activated by signals from nodes c 1  or e 1  and the gate of Q 12  is activated by the precharge signal pc 2   b , which is the inverse of the precharge signal pc 2 . Operation of the pixel driver block involves precharging node o 1  to high by pulsing the pc 2   b  signal. Once precharged, if the gate of Q 11  is activated, node o 1  will go from high to low with the transistor driving the attached liquid crystal accordingly. On the other hand, if the gate of Q 11  is not activated, then node o 1  will not transition and the liquid crystal will be driven accordingly. Driving a liquid crystal with a PMOS transistor enables the drive signal to have a full V DD  to ground voltage swing. 
     Pixel cells as described with reference to FIGS. 2 and 3 may be implemented, for example, into a VGA display having 640×480 pixels and/or a QGA display having 1280×960 pixels. The memory cells may be fabricated with, for example, 0.35 micron or 0.18 micron CMOS processes, respectively. 
     Operation of a single pixel cell  20  and  60  is described in stages with reference to FIGS. 4-11, where a bold line indicates a conductive path that is charged to a high voltage. FIG. 4 depicts a reset/precharge stage in which signals reset, pc, pc 2 , and pc 2   b  are all pulsed. Pulsing the reset signal sets node a 1  low. Pulsing the pc signal sets node d 1  low and precharges node e 1  high (to V DD ), as indicated by the bold line. Pulsing the pc 2  signal sets node c 1  low and pulsing the pc 2   b  signal precharges node o 1  high, as indicated by the bold line. The reset/precharge stage is a fundamental procedure necessary to initialize the dynamic pixel driver and sets up the pixel cells, so that only high signals applied to node c 1  will cause node o 1  to transition from high to low. 
     Data writing is performed after the pixel cell is reset/precharged as described above. In the data writing stage, a bit of data is written from the write bit line to node a 1 . Referring to FIG. 5, to write a bit of data to node a 1 , the write word line signal is pulsed high, thereby activating Q 1  and allowing a bit of data to pass from the write bit line to node a 1 . If the write bit line is high, then a 1  will change from low to high and node a 1  will represent a “1”. If the write bit line is low, then a 1  will remain low and node a 1  will represent a “0”. When al is high, Q 3  acts as a storage capacitor to hold the bit value supplied by the write operation. FIG. 5 is depiction of a pixel cell after a “1” bit has been written to node a 1  and stored in the input storage block. As shown, the bold line indicates a conductive path that is charged high. It is important to note that when al is high b 1  is also high and that Q 4  and Q 5  prevent further transfer of the high charge. In addition, it is important to note that nodes e 1  and o 1  are not affected by the write and store operation that has occurred at the input storage block. In the case where a “0” is written to node a 1 , the charging of the pixel cell remains exactly as shown in FIG. 4, where nodes a 1  and b 1  remain low. 
     Because the pixel cell operation is slightly different depending on whether a “1” or a “0” is written to the input storage block, the two situations are discussed separately with the “1” bit case described with reference to FIGS. 5-8 and the “0” bit case described with reference to FIGS. 9 and 10. As shown by the bold line at nodes a 1  and b 1  in FIG. 5, a “1” is stored in the input storage block. To transfer the stored bit to the pixel driver so that the bit can be transformed into display data, the transistors Q 4  and Q 5  of the global transfer block are activated by pulsing the global transfer signal. Referring to FIG. 6, pulsing the global transfer signal transfers a high signal simultaneously to nodes c 1  and d 1 . The high signal on node c 1  turns on Q 11  and causes node o 1  to transition from high to low. The transition of node o 1  from high to low is equivalent to driving the pixel with a “1” bit. The high signal on node d 1  turns on Q 7  and drops node e 1  from high to low, creating the DC balance data for subsequent transfer to the pixel driver. 
     After the “1” bit has been displayed by the pixel for the desired time, it is necessary to drive the pixel with an inverted, or negative, signal for an equivalent period of time to accomplish DC balancing. Instead of writing the DC balance data from the write bit line, as is conventional, the pixel cell utilizes the internally generated DC balance data. To prepare the pixel cell for the DC balance data transfer, the pixel cell again must be reset/precharged by pulsing the pc 2  and pc 2   b  signals. FIG. 7 depicts a pixel cell after the DC balance reset/precharge in the case in which a “1” was just transferred from the input storage node. Pulsing pc 2  turns on Q 10  and causes node c 1  to go low if it was high (as is the case when a “1” was just transferred) and pulsing pc 2   b  turns on Q 12 , causing node o 1  to go high if it was low (as is the case when a “1” was just transferred). In addition, it should be noted that node d 1  remains charged, but more importantly node e 1  is no longer charged because node e 1  was dropped low when Q 7  was turned on by the frame transfer. 
     Referring to FIG. 8, to transfer the DC balance data to the pixel driver, the inv signal is pulsed, causing the data at node e 1  to be transferred to node c 1  and to the gate of Q 11 . In the case when a “1” is initially transferred from the input storage block, node d 1  is high and node e 1  is low. Since node e 1  is low, pulsing the inv signal does not turn on Q 11  and therefore node o 1  remains high. Leaving node o 1  high causes the pixel to be driven at the equivalent of a “0” bit during DC balancing. 
     FIGS. 9 and 10 are referred to in the case in which a “0” bit is initially written into the input storage block. Referring to FIG. 9, as described above, after a “0” bit has been written from the write bit line into node a 1 , node a 1  remains low. Since node a 1  is low when the global transfer signal is activated, nodes c 1  and d 1  remain in their preset low states. Since node c 1  remains low, Q 11  is not activated and as a result node o 1  remains high, driving the pixel according to a “0” bit. Since node d 1  remains low, Q 7  is not activated and as a result node e 1  remains high. 
     After the “0” bit has been displayed for the desired time interval, the DC balance reset/precharge operation is initiated. As with the case of a displayed “1” bit, the DC balance reset/precharge operation involves pulsing the pc 2  signal and pulsing the pc 2   b  signal. Since node c 1  is already low and node o 1  is already high, the DC balance preset function does not change the state of the two nodes, as can be seen in FIG.  9 . 
     Once the DC balance reset/precharge is complete, the inv signal is pulsed high and, as shown in FIG. 10, the charge stored at node e 1  is shared with node c 1  through transistor Q 9 . Causing node c 1  to go high turns on transistor Q 11  and transitions node o 1  from high to low. The transition of node o 1  from high to low supplies the pixel with the proper DC balancing. 
     Upon completion of the DC balance process, one display cycle is complete and the reset/precharge operation is repeated. Display cycles are repeated for each grayscale bit for the color to be displayed. It should be noted that writing the input bit into the input storage block and displaying the drive bit from the drive storage block or the DC balance block are independent operations that can occur during overlapping time periods. That is, a new input bit may be written into the input storage block while a drive bit is being displayed. Providing the independent operation of writing and displaying can eliminate the need for blanking frames that may be necessary while an entire frame of input bits is being written to an array of pixel cells. 
     Because all of the storage nodes are dynamic storage nodes, the transistor count and area requirement are kept to minimums. In addition, the dynamic storage nodes enable a low power mode of operation with no direct DC leakage paths. 
     FIG. 11 is a process flow diagram of a preferred method of the invention. In step  100 , display data is received at a circuit that is integrated into a single pixel cell. In a step  102 , DC balance data is generated from the display data utilizing the circuit that is integrated into the single pixel cell. In a step  104 , the single pixel cell is driven according to the display data. In a step  106 , the single pixel cell is driven according to the DC balance data.