Abstract:
A processor capable of independently adding a specified level of noise to each different frequency-based channel signal of a composite signal, where the specified levels of noise for at least two channel signals are different. In one embodiment, the processor operates in the digital domain after the composite signal can been channelized using a single set of time-multiplexed circuitry for all channel signals.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to signal processing, and, in particular, to techniques for de-sensing received signals.  
       BACKGROUND OF THE INVENTION  
       [0002]     De-sensing refers to the process of a receiver purposely adding noise to a received signal, e.g., to characterize the capabilities of a communication system to operate in the presence of different noise levels. De-sensing has traditionally been performed in the analog domain, but such analog de-sensing does not support the independent addition of noise into individual carriers of frequency-based signal channels.  
         [0003]     There are digital down-converters (DDCs) that provide a de-sense function by injecting a pseudo-noise (PN) sequence in the digital domain at intermediate frequency (IF) after mixing, but prior to channelization and automatic gain control (AGC), but these DDCs do not support individual per-carrier adjustment of the noise level. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]     Aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.  
         [0005]      FIG. 1  is a block diagram of a receiver, according to one embodiment of the present invention;  
         [0006]      FIG. 2  is a block diagram showing the functions implemented by the FPGA of  FIG. 1 ; and  
         [0007]      FIG. 3  is a block diagram of the de-sense circuit of  FIG. 2 , according to one possible embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0008]      FIG. 1  is a block diagram of a wideband receiver  100 , according to one embodiment of the present invention. Receiver  100  may be employed at the base station of a wireless communication network, such as a cellular telephone network having many base stations interconnected via central offices. Receiver  100  has radio processor  102  and baseband processor  104 .  
         [0009]     Radio processor  102  receives radio frequency (RF) signals transmitted over the air from one or more wireless units (e.g., mobile phones). During normal operations, radio processor  102  typically receives multiple RF signals transmitted by multiple wireless units, where each RF signal may be distinguished from other RF signals based on one or more signal characteristics, such as frequency, timing, phase, and/or code. Radio processor  102  processes the received RF analog signals to provide baseband digital signals to baseband processor  104 , which further processes the digital signals and provides resulting digital signals to another node in the wireless communication network (e.g., a central office).  
         [0010]     As shown in  FIG. 1 , radio processor  102  has two parallel sets of front-end circuitry that provide receiver  100  with signal-processing diversity. In particular, radio processor  102  has two antennas  106 , two low-noise amplifiers (LNAs)  108 , two RF-to-IF converters  110 , and two analog-to-digital converters (ADCs)  112 . Each antenna  106  receives a different version of a composite (e.g., multi-carrier) RF signal corresponding to a combination of the RF signals transmitted from the wireless units, each LNA  108  amplifies the corresponding received composite RF signal, each RF-to-IF converter  110  performs mixing and filtering to convert the amplified, received composite RF signal to IF, and each ADC  112  digitizes the analog IF signal.  
         [0011]     Digital down-converter (DDC)  114  performs channelization, decimation, matched filtering, and automatic gain control (AGC) on the two digital IF signals from ADCs  112  to generate a different digital signal for each different carrier in the original received composite RF signals. These digital signals are provide to field-programmable gate array (FPGA)  116 , which demultiplexes, de-senses, and formats the digital signals, e.g., according to the Common Protocol Radio Interface (CPRI) standard.  
         [0012]     The digital signals generated by FPGA  116  are provided to baseband processor  104 , which performs one or more of demodulation, de-spreading, de-interleaving, and decoding ( 118 ) to generate the digital signals that are forwarded on to other parts of the network via network interface  120 .  
         [0013]      FIG. 2  is a block diagram showing the functions implemented by FPGA  116  of  FIG. 1 . DDC  114  of  FIG. 1  generates a serial stream of digital data in which data corresponding to different frequency channels (i.e., corresponding to different RF carriers in the original received composite RF signals) and different receive antennas are time-multiplexed in the serial stream. In addition to the channel data (i.e., in-phase (I) and quadrature (Q) data for each channel and each antenna), the serial stream also includes RSSI (received signal strength indication) data identifying the signal strength (in dB) of each different received RF channel at each antenna, as measured at receiver  100 .  
         [0014]     DDC data/RSSI demux circuit  202  demultiplexes the serial stream received from DDC  114  to provide separated I/Q data stream  204  and RSSI stream  206  to de-sense circuit  208 , which independently adds specified levels of internally generated noise to the I/Q data corresponding to different RF channels. The resulting de-sensed I/Q data stream  210  is provided to CPRI format/mux circuit  212 , which formats and multiplexes I/Q data stream  210  for further processing by baseband processor  104  of  FIG. 1 .  
         [0015]      FIG. 3  is a block diagram of de-sense circuit  208  of  FIG. 2 , according to one possible embodiment of the present invention. This particular embodiment corresponds to a situation in which the received RF signals correspond to two different carriers: Carrier  0  and Carrier  1 , where each antenna (i.e., Antenna A and Antenna B) receives a composite RF signal corresponding to both carriers.  
         [0016]      FIG. 3  indicates the time-multiplexing of four sets of I and Q data (corresponding to the two carriers and two antennas) contained in I/Q data stream  204  from demux circuit  202  of  FIG. 2 . As shown, I/Q data stream  204  comprises a first sample of both I and Q of Carrier  0  received at Antenna A, followed by a first sample of both I and Q of Carrier  0  received at Antenna B, a first sample of both I and Q of Carrier  1  received at Antenna A, followed by a first sample of both I and Q of Carrier I received at Antenna B, and so on, for subsequent samples of each carrier received at each antenna.  
         [0017]     According to this embodiment, certain circuitry in de-sense circuit  208  is time-multiplexed to process the four different sets of data. As described below, this time-multiplexed circuitry includes look-up tables (LUTs)  314 ,  332 ,  338 , and  340 , multipliers  304 ,  326 , and  336 , addition/subtraction nodes  316 ,  318 , and  334  and shift register  342 . This time-multiplexed circuitry is used to sequentially process the eight different sets of data corresponding to the eight different combinations of data I/Q, Antennas A/B, and Carriers  0 / 1 .  
         [0018]     Interface  302  provides I/Q data stream  204  containing the four sets of time-multiplexed I/Q data from demux circuit  202  of  FIG. 2  to multiplier  304 , where each I and Q value is represented by a 6-bit, signed binary number. Interface  302  also demultiplexes RSSI stream  206  to form four separated RSSI streams (A 0 , B 0 , A 1 , and B 1 ), each corresponding to a different carrier/antenna combination. Each of these RSSI streams is provided to both multiplexer  306  and a corresponding summation node  308 . Each summation node  308  adds an externally specified attenuation offset value stored in register  310  to the corresponding RSSI value. The purpose of this offset value is to adjust the “raw” RSSI values as necessary when attenuators are used to increase the dynamic range of ADCs  112  of  FIG. 1 . The resulting “compensated” RSSI value from each summation node  308  is also provided to mux  306 .  
         [0019]     One-bit control signal  312  is a time-multiplexed signal that controls mux  306  to select either the raw or the compensated RSSI values, for each antenna sequentially. Not explicitly shown in  FIG. 3  is a second control signal that controls mux  306  to sequentially select RSSI values corresponding to the four different sets of I/Q data. (Analogous control signals for other multiplexers in  FIG. 3  are also not explicitly shown in the figure.) Each selected RSSI value is provided to LUT  314 , subtraction node  316 , and summation node  318  as a 12-bit, unsigned binary number.  
         [0020]     LUT  314  is a (12-bit by 16-bit) table that maps each different possible 12-bit RSSI digital value (RSSI) (representing dB) to its corresponding 16-bit linear value (RSSI linear ), where the 16-bit unsigned binary value is extended to a 17-bit signed binary value whose sign bit is 0. The mapping of LUT  314  corresponds to Equation (1) as follows:  
                 RSSI   linear     =     Q   ⁡     (     10     (         RSSI   *   α     +   β     20     )       )         ,           (   1   )             
 
 where α is a conversion factor from digital level to dB (e.g., 0.235 dB/level), β is a dynamic range optimization factor (e.g., 120), and Q(.) indicates quantization. The resulting 17-bit, signed RSSI values are applied to multiplier  304  to scale the corresponding I/Q values in stream  204 . Not shown in  FIG. 3  is buffering that ensures that the appropriate I/Q values are multiplied by the corresponding RSSI values as well as other buffering that ensures that other sets of values are properly synchronized at other (e.g., multiplier, summation, subtraction) nodes. Multiplier  304  essentially un-does (i.e., reverses) the AGC processing performed in DDC  114  of  FIG. 1 . 
 
         [0021]     Complex PN sequence generator  320  generates four complex pseudo-noise sequences  322 , one for each combination of Carriers  0 / 1  and Antennas A/B. These four PN sequences  322  are applied to mux  324 , which selects an appropriate one to apply to multiplier  326  as a 6-bit, signed binary number. In one implementation, each complex PN sequence is a random sequence of complex values equal to ±9±9j.  
         [0022]     Registers  328  contain externally specified noise levels (in digital levels representing dB) for each of the four different data streams (A 0 , B 0 , A 1 , B 1 ). The four different noise levels are applied to multiplexer  330 , which selects an appropriate one to apply to both LUT  332  and subtraction node  316 . Like LUT  314 , LUT  332  is a (12-bit by 16-bit) table that maps each different possible 12-bit noise value in dB to its corresponding 16-bit linear value, where the 16-bit unsigned binary value is extended to a 17-bit signed binary value where the sign bit is zero. The resulting 17-bit, signed noise values are applied to multiplier  326 , which scales the corresponding PN sequence values from mux  324 .  
         [0023]     The resulting simulated, 23-bit, signed, internally generated noise values from multiplier  326  are added at summation node  334  to the corresponding 23-bit, signed scaled I/Q values from multiplier  304 . The resulting 23-bit, signed, noise-scaled I/Q values are applied to multiplier  336 . (Note that, in this implementation, the ranges of expected values of the two 23-bit inputs to summation node  334  ensure that the result of the summation is not a 24-bit value.)  
         [0024]     In order to provide baseband processor  104  with appropriate I/Q and RSSI data, the AGC processing that was un-done by multiplier  304  needs to be re-done. One way to re-do the AGC processing would be to divide the noise-scaled I/Q data generated at summation node  334  by RSSI values corresponding to the RSSI values applied by multiplier  304  as adjusted for the level of the internally added noise. For example, if x is the linear RSSI value apply by multiplier  304  and y is the linear representation of the internally added noise value, then re-doing the AGC processing would involve dividing the noise-scaled I/Q values by √{square root over (x 2 +y 2 )}, when the standard deviation of the unscaled noise is equivalent to the standard deviation of the I/Q inputs. However, division operations are typically expensive to implement (in terms of complexity, processing time, and/or layout).  
         [0025]     Instead, division by a particular divisor value may be implemented by multiplication by the reciprocal (i.e., inverse) of that divisor value. As described in the following paragraphs, de-sense circuit  208  takes advantage of this mathematical relationship by implementing the division function to re-do the AGC processing as a combination of an appropriate (inverse scaling) multiplication operation and a corresponding bit-shift operation. As an example, in the decimal domain, division by 2 can be implemented by a multiplication by 5 and a shift of one decimal place to the right (corresponding to dividing by 10 in the decimal domain). Thus, 6 divided by 2 can be implemented as ((6 times 5) followed by a decimal-based right shift).  
         [0026]     In  FIG. 3 , subtraction node  316  subtracts the selected noise levels (Noise in dB) from mux  330  from the selected RSSI values (RSSI in dB) from mux  306  to generate 13-bit, signed data corresponding to the RSSI level minus the added internal noise, which data are applied to LUT  338 . LUT  338  is a (13 bit by 12 bit) table that maps each different possible 13-bit RSSI-minus-noise value in dB to a corresponding 12-bit value representing the adjusted signal-to-noise ratio (adjusted_SNR) in dB. The mapping of LUT  338  corresponds to Equation (2) as follows:  
               adjustedSNR   =     Q   ⁡     (       10   ⁢       log   10     ⁡     (     1   +     10     (       -   SNR     /   10     )         )         α     )         ,           (   2   )             
 
 where: 
 
 SNR =( RSSI −Noise)*α. 
 
 LUT  338  determines how much (in digital level representing dB) the divisor value corresponding to the binary RSSI value applied at multiplier  304  needs to change to adjust for the internally added noise. This adjusted SNR value is added to the selected RSSI value from mux  306  at summation node  318  to generate 12-bit, unsigned data corresponding to a new RSSI value, which is applied to LUT  340 . 
 
         [0027]     LUT  340  is a (12 bit by 16 bit) table that maps each different possible 12-bit new RSSI value (RSSI new  in dB) to a 16-bit binary value corresponding to the inverse of the new RSSI value, where the 16-bit unsigned binary value is extended to a 17-bit signed binary value (inverse) whose sign bit is zero. LUT  340  may be thought of as a combination of a first mapping from RSSI values in dB to linear RSSI values (e.g., according to Equation (1)) and a second mapping from linear RSSI values to binary values representing the reciprocals of the linear RSSI values. The mapping of LUT  340  corresponds to Equation (3) as follows:  
             inverse   =       Q   ⁡     (         2   16     -   1       10     (           RSSI   new     *   α     +   β     20     )         )       .             (   3   )             
 
 Multiplier  336  multiplies the noise-scaled I/Q data from summation node  334  by the inverse values from LUT  340 , and bit-shifter  342  performs a 16-bit arithmetic shift to the right on the resulting 40-bit, signed data. The 6 LSBs in the data generated by bit-shifter  342  correspond to I/Q data stream  210  provided to CPRI format/mux circuit  212  of  FIG. 2 . 
 
         [0028]     As described, de-sense circuit  208  of  FIG. 3  enables each of four different sets of data (corresponding to the four different combinations of Antennas A/B and Carriers  0 / 1 ) to have its own unique level of internally added noise. As such, de-sense circuit  208  provides channel-dependent de-sensing capabilities, in addition to providing antenna-dependent de-sensing capabilities.  
         [0029]     One difference between LUT  314  and LUT  332  is that the 0 th  term in LUT  332  is populated with a zero value. This enables the additive noise component at summation node  334  to be selectively turned off (e.g., when de-sensing is not wanted) by storing zeros in noise registers  328 . These zero values in noise registers  328  will produce the desired results in elements  316 ,  318 ,  336 ,  338 ,  340 , and  342 .  
         [0030]     Although the present invention has been described in the context of a particular implementation, other embodiments are possible. For example, other embodiments may be designed for numbers of carriers other than two and/or numbers of receive antennas other than two (including one).  
         [0031]     Although the implementation of  FIG. 3  relies on time-multiplexing of certain circuitry, the present invention can also be implemented using multiple instances of that circuitry, with as many as one instance for each different set of data processed.  
         [0032]     Although the present invention has been described in the context of a specific implementation of a de-sense circuit having different binary data values of specific bit lengths and types (i.e., signed/unsigned), those skilled in the art will understand that the present invention can be implemented in other contexts having data of different bit lengths and/or types. This applies as well to the sizes of the different LUTs and shift registers. Moreover, it may be possible to implement the functions of one or more of the LUTs using circuitry that implements closed-form expressions corresponding to the LUTs (e.g., Equations (1), (2), and/or (3)).  
         [0033]     Although the present invention has been described in the context of a receiver in which de-sensing is implemented by an FPGA along with other functions (i.e., demultiplexing and CPRI formatting). In other embodiments, one or more of these functions may be implemented using other types of processors, including application-specific integrated circuits (ASICs), microprocessors, mask-programmable gate arrays (MPGAs), and/or other programmable logic devices (PLDs).  
         [0034]     Embodiments of the present invention may be implemented as circuit-based processes, including possible implementation on a single integrated circuit (such as an ASIC or an FPGA), a multi-chip module, a single card, or a multi-card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing steps in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, or general-purpose computer.  
         [0035]     It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims.