Abstract:
An interface between a network cell and an associated network communications transceiver passes both network information and command/control information between the cell and the transceiver. The interface is designed to minimize the number of control lines between the cell and the transceiver. A protocol between the two devices is established to deal with configuration and error reporting as well as the passage of network data. This protocol consists of the cell and the transceiver each exchanging 8 bits of status and 8 bits of data simultaneously and continuously at rates up to 1.25 MBPS. Only a single version of cell firmware is required since a fixed amount of configuration information is sent from the cell to the transceiver, and a fixed amount of status information is returned from the transceiver to the cell.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of digital communications interfaces. More particularly, the invention relates to a dedicated status and data interface between a processor for a node on a communications network and a transceiver coupled to the network communication medium. 
     BACKGROUND OF THE INVENTION 
     U.S. Pat. No. 4,918,690 discloses a network for providing sensing, communications, and control. The disclosure of this patent is incorporated herein by reference. By way of brief summary, the network comprises a plurality of intelligent cells, each of which comprises an integrated circuit having a processor and input/output section. Each of the programmable cells receives a unique identification number which remains permanently within the cell. The cells can be coupled to any one of a variety of media such as power line, twisted pair, radio frequency, infrared, ultrasonic, optical, coaxial, etc. to form the network. Cells communicate with one another on the network by exchanging packets of data. 
     Each network may comprise groups of cells that perform particular functions. Cells can perform multiple functions and be members of multiple groups. The network protocol provides great flexibility and allows groups to be formed and/or changed after the cells are in place. The intelligence of the network is distributed among the cells. In general, the network is lightly loaded, although provisions may be made for contentions and other overload conditions that may arise. Communications between the cells in general is optimized for carrying out the functions assigned to the groups, rather than for transmission of data unrelated to the control function of the network. For this reason, communication packets are relatively short compared to more conventional local area networks. 
     A portion of a network of cells is illustrated in FIG. 1. Here, cells 20 and 30 are coupled to a communications medium 40 by means of respective transceivers 22 and 32. Additionally, each cell may be coupled to one or more of a variety of input/output devices 25, such as sensors and actuators, that interface with the environment and enable the cell to perform its assigned function in the network. For the purpose of the description to follow, the term &#34;cell&#34; will refer to the intelligent device coupled to the network, whereas a cell and its associated peripheral devices, including a transceiver and any input/output devices, will be referred to as a node. 
     As an example of a typical network application, cell 20 may be associated with a lighting fixture in a home, and cell 30 may be associated with a light switch. In this application, medium 40 may be the house wiring, although it could also be any of the other media recited above. Cell 30 would be assigned the function of sensing the opening or closing of its associated switch, while cell 20 would be assigned the function of controlling the flow of power to its associated light fixture in accordance with command and control information received over the network from cell 30 and from any other nodes that are functionally related, such as, for example, a node that senses ambient light levels. 
     Commercial embodiments of a device that may be employed as cells 20,30 are the integrated circuits sold under the trademark &#34;NEURON&#34; by both Motorola and Toshiba. These devices are manufactured under license from Echelon Systems Corp., the assignee of this invention and owner of the aforementioned U.S. Pat. No. 4,918,690. Briefly stated, a &#34;NEURON&#34; cell is a large scale integrated circuit device including a three-processor CPU, internal memory, communications port, I/O section and timing and control section. The three independent processors share a common memory, arithmetic logic unit (ALU) and control circuitry. Two of the processors are dedicated to communications and the third is dedicated to execution of application code. 
     Transceivers 22,32 are specifically designed for the particular network medium 40. Moreover, the transceivers may be simple line drivers in the case of a hardwired network medium or may be more sophisticated devices. Characteristics of a more sophisticated transceiver may include: 
     Multiple channel operation. 
     Multiple speed 
     Use of forward error correction. 
     Media specific modulation techniques requiring special message headers and framing. 
     Programmable and configurable operation. 
     Ability to gather parametric data regarding transmission quality, noise, and received signal strength. 
     Ability to shut down to save power during idle time. 
     SUMMARY OF THE INVENTION 
     The present invention provides an interface between a network cell and an associated network communications transceiver. The interface of the present invention is designed to minimize the number of control lines between the cell and the transceiver. The cell/transceiver interface is designed to pass both network information as well as command/control information between the cell and the associated transceiver. The present invention minimizes the number of pins on each chip to achieve these functions, which has the beneficial effect of reducing the cost associated with the manufacture and testing of the IC&#39;s. 
     A protocol between the two devices is established to deal with configuration and error reporting as well as the passage of network data. This protocol consists of the cell and the transceiver each exchanging 8 bits of status and 8 bits of data simultaneously and continuously at rates up to 1.25 MBPS. The high data rate allows time critical flags such as carrier detect to be exchanged across the interface with network data rates up to 100 KBPS. 
     Because it is desirable that the cell&#39;s communication firmware be the same in all cell-based devices, the interface is general enough to support a variety of transceiver designs with a single version of cell firmware. This is accomplished by writing a fixed amount of configuration information from the cell to the transceiver, and by reading a fixed amount of status information from the transceiver to the cell. All cell chips have some amount of EEPROM on them which is programmed prior to the time that the cell is integrated into a node with the configuration information necessary to initialize the associated transceiver. Upon receipt of a network management message, the cell&#39;s firmware can read the status registers within the transceiver and report their contents to a requesting device for network debugging and analysis. The cell&#39;s firmware need not be able to interpret what the status information indicates since it may be assumed that the application program requesting the status information is able to understand it. 
     Items that are to be defined by a specific transceiver include: 
     Definition of the registers that the cell may read and write. 
     Definition of preamble. 
     Use of watch dog timers on the transceiver (e.g., such that the node does not fail in a way that ties up the network indefinitely). 
     Use of transceiver run/sleep modes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a network in which the present invention may be employed. 
     FIG. 2 illustrates the physical interface between a cell and its associated transceiver. 
     FIG. 3 illustrates the timing relationships between the cell/transceiver interface signals. 
     FIG. 4 illustrates the transmit sequences of the present invention. 
     FIG. 5 illustrates the transmit sequences of the present invention when collision detection is implemented in the transceiver. 
     FIG. 6 illustrates the receive sequences of the present invention. 
     FIG. 7 illustrates the configuration sequences of the present invention. 
     FIG. 8 illustrates the status request sequences of the present invention. 
     FIG. 9 is a transceiver state diagram. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following description, for purposes of explanation and not limitation, specific details are set forth, such as numbers, protocols, circuit implementations, etc. in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known devices and methods are omitted so as not to obscure the description of the present invention with unnecessary detail. 
     Physical Interface 
     The physical interface between an exemplary cell 20 and an associated transceiver 22 is depicted in FIG. 2. When the cell is configured to operate in transceiver mode, the cell and transceiver exchange status and data over a synchronous serial bus coupled to the cell&#39;s comm port comprising pins CP.0, CP.1, CP.2 and CP.4 of the cell. The fifth I/O pin, CP.3, of the cell&#39;s comm port is defined as &#34;sleep&#34;. As indicated above, support of this pin&#39;s function is optional on the transceiver. 
     When CP.3 is connected to a transceiver with sleep capability, the cell can be configured to operate in one of two ways. The cell can be configured so that any incoming message will wake it up, in which case CP.3 is an input to the cell. Alternatively, the cell can be configured so that CP.3 is an output to the transceiver. An application program running on the cell can decide to sleep periodically and assert the pin. This will cause the transceiver to power down whenever the cell&#39;s application program instructs the cell to go to sleep. When the sleep pin is high the transceiver is to be awake; when the pin is asserted low, it is assumed that the transceiver is asleep. 
     The transceiver also has an input (T --  Reset) which is tied to the cell&#39;s external reset pin (N --  Reset). As more fully described below, the transceiver resets its state and internal registers when the external cell reset is asserted. The transceiver must not cause the cell to be reset by asserting this line. 
     CP.0 (RX) is the serial link from the transceiver to the cell. Each frame period, eight bits of status and eight bits of data are sent from the transceiver to the cell. 
     CP.1 (TX) is the serial link from the cell to the transceiver. Each frame period eight bits of status and eight bits of data are sent from the cell to the transceiver. 
     CP.2 (BIT CLK) is a bit clock generated by the cell which clocks data and status in and out of the cell and transceiver. The rate of the bit clock is the same as that of the Comm Port Clock on the cell. It should be noted that the Comm Port Clock rate is related to the cell input clock rate; the relation is configurable to be +8, 16, 32, 64, 128, 256, 512, or 1024. The maximum input clock rate of 10 MHz gives a maximum Comm Clock Rate of 1.25 MHz. 
     CP.4 (FRAME CLK) is a frame clock generated by the cell which pulses high for one bit time every 16 bit times on the serial link. The frame clock establishes a period of 16 bits during which eight bits of status and eight bits of data are exchanged. 
     The timing relationships of the above-described signals are illustrated in FIG. 3. 
     Status Bits 
     The eight-bit status field sent from the cell to the transceiver on CP.1 (TX) is denoted TX.ST. The eight-bit status field sent from the transceiver to the cell on CP.0 (RX) is denoted RX.ST. The individual bits in each of the status fields are named as follows: 
     
         ______________________________________TX.ST            RX.ST______________________________________bit 7 TX.sub.-- FLAG            bit 7 SET.sub.-- TX.sub.-- FLAGbit 6 TX.sub.-- REQ.sub.-- FLAG            bit 6 CLR.sub.-- TX.sub.-- REQ.sub.-- FLAGbit 5 TX.DATA.sub.-- VALID            bit 5 RX.DATA.sub.-- VALIDbit 4 Not assigned            bit 4 TX.DATA.sub.-- CTSbit 3 TX.sub.-- ADDR.R/W            bit 3 SET.sub.-- COLL.sub.-- DETbit 2 TX.sub.-- ADDR.2            bit 2 RX.sub.-- FLAGbit 1 TX.sub.-- ADDR.1            bit 1 RD/WR.sub.-- ACKbit 0 TX.sub.-- ADDR.0            bit 0 TX.sub.-- ON______________________________________ 
    
     The functions of the status bits are described in connection with FIGS. 3-8 which diagrammatically illustrate the handshaking that occurs between the cell and transceiver for different scenarios. In the figures, each pair of arrows represents the exchange of status fields during one frame. The status field from the cell to the transceiver, TX.ST, is on the upper arrow of each pair; the status field from the transceiver to the cell, RX.ST, is on the lower arrow. The values of the status fields are indicated in hexadecimal, with the key bit values in parentheses. The transceiver state for each sequence is indicated to the right of the diagrams. In each scenario, the transceiver begins and ends in the &#34;IDLE&#34; state. 
     Transmit Sequences 
     FIG. 4 diagrammatically illustrates the transmit sequences. As indicated above, the transceiver begins in the &#34;IDLE&#34; state as shown in sequence 4A. Both the cell and the transceiver fill all status fields with zeros. In order for the cell to request to transmit on the network, the cell sets an internal latch whose output is TX --  REQ --  FLAG (TX.ST.6) as shown in sequence 4B. This latch within the cell is cleared by the transceiver via CLR --  TX --  REQ --  FLAG (RX.ST.6), which is asserted by the transceiver for a single frame only. In the same frame that CLR --  TX --  REQ --  FLAG is asserted, the transceiver either accepts or rejects the cell&#39;s request for transmission. The transceiver accepts the request by asserting SET --  TX --  FLAG (RX.ST.7) for a single frame only as also shown in sequence 4B. The transceiver rejects the request by not asserting SET --  TX --  FLAG in the frame. 
     The transceiver looks for carrier on the network right up until it either accepts or rejects the request for transmission. With each transceiver checking to ensure the network is idle immediately before accepting the transmit request and beginning to transmit, the occurrence of collisions on the network is minimized and thus network performance is improved. If the transceiver detects carrier on the network, it rejects the request by setting CLR --  TX --  REQ --  FLAG for one frame and not asserting SET --  TX --  FLAG in the same frame. (The transceiver&#39;s further response to detection of carrier is described below under &#34;Receive Sequences&#34;.) If the transceiver sees no carrier on the network, it accepts the request by setting CLR --  TX --  REQ --  FLAG and SET --  TX --  FLAG for one frame and immediately begins transmitting preamble on the network, as described below. Assertion of SET --  TX --  FLAG for one frame causes a latch within the cell whose output is TX --  FLAG (TX.ST.7) to be set. This latch will later be cleared internally by the cell to end transmission. 
     When the transceiver accepts the request for transmission as just described, the transceiver must assert TX.DATA --  CTS (RX.ST.4) for a single frame only before the cell sends the first byte of data. TX.DATA --  CTS may be set in the same frame as CLR --  TX --  REQ --  FLAG and SET --  TX --  FLAG, i.e., RX.ST=D0 as shown in sequence 4B. 
     When the transceiver has accepted the request for transmission, it begins to send its preamble on the network. The content of the preamble is defined by the transceiver in accordance with the communications protocol for the network. The transceiver may impose a minimum requirement on the duration of the preamble, but the preamble must either be extended until the first byte of data to be transmitted is available from the cell, or be guaranteed to be long enough such that the first byte of data is available before the end of the preamble in accordance with the communications protocol for the network. In this way the transmitting cell determines the minimum length of time a receiving node will have between notification of an incoming packet and when it must be ready to receive the data bytes of the incoming packet. On reception, the node&#39;s transceiver strips off the preamble and returns only valid data bytes to the cell. 
     If the transceiver has previously asserted TX.DATA --  CTS for a single frame, the transceiver has indicated that it is in the &#34;TX:rdy for data&#34; state and the cell may send a byte of data. Until such time as the cell transmits the first byte, the TX --  FLAG is maintained high and the transceiver maintains TX --  ON high (as described below) (sequence 4C). To send a byte of data, the cell shifts eight bits out in the field TX.DATA.7-0. (Bit 7 is the MSB and is shifted out first.) In the same frame as the data is shifted out, the cell asserts TX.DATA --  VALID for a single frame only (sequence 4D). Observe in FIG. 3 that the status field TX.ST precedes TX.DATA in each frame, and therefore TX.DATA --  VALID is asserted before TX.DATA is shifted out. If the transceiver sets TX.DATA --  CTS in the same frame as SET --  TX --  FLAG and CLR --  TX --  REQ --  FLAG, the cell may set TX.DATA --  VALID in the first frame in which TX --  FLAG is set, i.e., sequence 4D may follow immediately after sequence 4B. 
     The cell may not send another byte of data to the transceiver until the transceiver indicates it is ready to accept the next byte by again asserting TX.DATA --  CTS for a single frame only (sequence 4F). In the interim, the cell maintains the TX --  FLAG set and the transceiver maintains TX --  ON set (sequences 4E,4G). If the transceiver is not ready to receive another byte, it enters the state &#34;TX: not rdy for data&#34;. When ready for another byte from the cell, the transceiver asserts TX.DATA --  CTS for a single frame and returns to the state &#34;TX: rdy for data&#34; (sequence 4F). 
     Sequences 4D-4G repeat for each byte of data sent by the cell, except that upon transmission of the last byte, the cell does not look for the transceiver to assert TX.DATA --  CTS (sequences 4H,4I). After the cell has sent the last byte of data, it clears the latch whose output is TX --  FLAG to indicate end of transmission (sequence 4J). In response to TX --  FLAG=0, the transceiver goes to &#34;END OF TX&#34; state, but continues transmitting on the network until all bytes from the cell are transmitted. After the transceiver has completed transmitting the packet on the network, it goes to &#34;IDLE&#34; state (sequence 4K). At any time, if the cell wants to abort transmission, it clears TX --  FLAG. The transceiver transmits the last byte(s) of data and then stops transmitting. 
     TX --  FLAG must be cleared by the cell at least one frame following the last assertion of TX.DATA --  VALID. The cell may cause an extra TX.DATA --  VALID to be asserted after TX --  FLAG has been reset. This TX.DATA --  VALID, asserted when TX --  FLAG is low, must be ignored. 
     The cell must deliver bytes fast enough that the transceiver does not have an underflow condition. An underflow condition exists when the transceiver needs another byte of data to transmit or an indication to stop transmitting, but does not receive it in time. The maximum time between the assertion of TX.DATA --  CTS by the transceiver and either the assertion of TX.DATA --  VALID (another byte to transmit) or the de-assertion of TX --  FLAG (end of transmission) by the cell must be specified by each transceiver. This time depends on the network data rate and the amount of buffering on the transceiver. In case of underflow, the transceiver sends all zeros. As mentioned above, the cell does not need TX.DATA --  CTS to be asserted after sending the last byte of data before it may clear TX --  FLAG. However, the maximum time until TX --  FLAG is cleared must be specified relative to TX.DATA --  CTS being asserted. 
     One of the status bits from the transceiver to the cell (RX.ST.0) is reserved for reporting the state of the transceiver&#39;s transmitter (1=on; 0=off). The cell&#39;s firmware watches this bit after it completes the transmission of a packet (after TX --  FLAG is reset), and if the flag fails to clear, the transceiver will be reset by the cell in the hopes that this will turn the transmitter off. The reset will occur as the result of a watchdog timer reset on the cell. 
     Referring now to FIG. 5, transmit sequences for a transceiver that implements collision detection are illustrated. Transmission proceeds in ordinary fashion until a collision is detected and thus sequences 5A-5C are identical to sequences 4A-4C. If the transceiver detects a collision while transmitting its preamble, it asserts SET --  COLL --  DET (RX.ST.3) for one frame (sequence 5D). SET --  COLL --  DET clears the latch on the cell whose output is TX --  FLAG, thus aborting transmission at sequence 5E. SET --  COLL --  DET also sets a latch on the cell which indicates to the CPU that there was a collision. If the transceiver does not support collision detection, the bit SET --  COLL --  DET must always remain low. 
     Receive Sequences 
     Receive sequences are illustrated in FIG. 6. When the transceiver detects carrier on the line, it attempts to establish with a high level of certainty that the carrier detect indication is indeed an incoming packet and not a false carrier detect indication. When the transceiver establishes that there is an incoming packet, it sets an internal latch whose output is RX --  FLAG (RX.ST.2) as shown in sequence 6B and enters the &#34;RX&#34; state. 
     It should be noted that the transceiver makes two separate determinations: one for &#34;carrier detect&#34; and one for &#34;incoming packet&#34;. As described in &#34;Transmit Sequences&#34; above, in order to avoid collisions, the carrier detect indication causes the transceiver to reject a concurrent request for transmission. However, in order not to falsely indicate to the cell that a packet is incoming, the transceiver processes the signal for some duration to establish with a high level of certainty that there is an incoming packet. This may involve processing carrier sync, bit sync, or word sync, in accordance with the network communications protocol. 
     After setting RX --  FLAG, the transceiver begins to receive data from the network. When the transceiver receives the first byte of data from the network, it shifts eight bits out in the field RX.DATA.7-0. (Bit 7 is the MSB and is shifted out first.) In the same frame, the transceiver asserts RX.DATA --  VALID (RX.ST.5) for one frame only (sequence 6C). Since the status field RX.ST precedes RX.DATA in each frame, RX.DATA --  VALID is asserted before RX.DATA is shifted out. RX --  FLAG must be set at least one frame before the first RX.DATA --  VALID is asserted. 
     Sequences 6C and 6D are repeated for each subsequent byte. The transceiver maintains RX --  FLAG high until the end of packet is detected and all bytes of data have been shifted to the cell. 
     There is no indication from the cell whether or not it is ready to receive another byte. To avoid a requirement that the transceiver have large amounts of buffering, the cell must be able to receive bytes from the transceiver as fast as the transceiver receives them from the network. The minimum time between consecutive bytes of received data, which is dependent on the network data rate, must be specified by each transceiver. 
     After the transceiver has delivered the final byte of data, it clears RX --  FLAG (sequence 6E). The transceiver must not deliver trailing bits of invalid data to the cell. This implies that the transceiver must account for any delay in detecting the end of carrier and any padding with zeros for error coding not done on byte-size blocks. If the transceiver needs to abort the receive sequence for some reason (e.g., bit sync or word sync is lost), it simply clears clears RX --  FLAG. 
     Configuration/Status Request Sequences 
     The cell&#39;s CPU is able to write to seven 8-bit registers in the transceiver and is able to read seven 8-bit registers in the transceiver. The definition of the contents of these registers is specific to each transceiver. However, every transceiver must have at least one configuration register containing at least one configuration bit. The required bit is bit 7 of the transceiver&#39;s configuration register 1. The function of this bit is described below. 
     TX status bit 3, TX --  ADDR.R/W, indicates whether the cell is reading or writing a transceiver register. TX --  ADDR.R/W=0 indicates a write; TX --  ADDR.R/W=1 indicates a read. Status bits 2-0, TX --  ADDR.2-0, designate one of seven possible registers, from 1-7 (bit 2 is the MSB). Register 0 is not defined, and a read or write command to register 0 is invalid. (As will be described below, a read command to register 0 will cause the transceiver to reset.) 
     The transceiver is required to accept and respond to configuration commands and status requests only when in the &#34;IDLE&#34; state, that is, when the transceiver is neither transmitting nor receiving. 
     Configuration 
     Configuration sequences are illustrated in FIG. 7. In order for the cell to write to a transceiver register (send configuration data to the transceiver), the cell CPU writes eight bits of register data which are shifted out in TX.DATA.7-0. (Bit 7 is the MSB and is shifted out first.) The cell CPU also sets TX --  ADDR.R/W=0 (write) and designates the register to be written with TX --  ADDR.2--0=1--7 (sequence 7B). These data indicate to the transceiver that the TX.DATA field of that same frame contains the configuration byte. The transceiver acknowledges that the configuration is complete by asserting RD/WR --  ACK (RX.ST.1) for one frame (sequence 7C). When the cell writes a configuration register, the acknowledgement for the write must be in the next frame. 
     The write register command will be sent by the cell in consecutive frames at least until the transceiver acknowledges the command, and the command will be sent for an indeterminate number of frames after the response until the cell&#39;s CPU clears the latches. The transceiver acknowledges each write command by asserting RD/WR --  ACK for one frame as indicated by sequence 7D. Once the cell deasserts the write register command (sequence 7E), the transceiver deasserts RD/WR --  ACK for the next succeeding frame (sequence 7F). 
     The cell&#39;s firmware writes all of the possible configuration registers in descending order, from register 7 to register 1. If the transceiver implements fewer than the maximum number of 7 registers, exact address decoding for the unused registers is not required. The subset of the registers that are actually implemented on the transceiver will be the last ones written to, and thus contain the correct values. 
     The transceiver must provide a RD/WR --  ACK for configuration of each of the seven registers, regardless of how many registers actually are implemented on the transceiver. The RD/WR --  ACK from the transceiver is issued in the frame following the configuration command. 
     Bit 7 of configuration register 1 is always required. This configuration bit, referred to as ALT --  PATH, indicates which of two possible transmission modes to use. These transmission modes are dependent on the transceiver design, and more than one mode need not be implemented by the transceiver designer. Examples of transmission modes are: two different modulation techniques, two different speeds, two different channels or carriers, or a combined speed and carrier frequency change. The cell&#39;s firmware will switch back and forth between these two alternatives prior to transmitting a packet under normal operation, so the modification of this configuration bit cannot disrupt the operation of the transceiver. The change over from ALT --  PATH=1 to ALT --  PATH=0 or from ALT --  PATH=0 to ALT --  PATH=1 must occur in 1 frame. 
     It is the transceiver designer&#39;s choice as to whether this capability of multi-channel or multi-speed is to be implemented, but if the transceiver does implement this feature, it is required that the transceiver be able to detect carrier on both paths simultaneously, and be able to receive a packet on either channel without any configuration action by the cell. For example, a transmitting node may decide to initiate a re-try message at a lower data rate. The transceivers of all other nodes must be able to detect such a slower data rate message on the channel and adapt their receivers to receive the packet without any configuration command from the cells attached to the transceivers which are receiving the slower packet. The same holds true if, instead of speed, the carrier frequency, modulation technique, etc. is changed by toggling the ALT --  PATH configuration bit. 
     In no case is it required for the transceiver to be able to receive two simultaneous messages, one on each of the ALT --  PATHs. The upper layers of the communications protocol should attempt to make it so that this condition occurs infrequently. When this condition occurs, it is treated as a collision, and it is acceptable that the transceiver receives either one or none of the colliding packets. 
     Whenever the ALT --  PATH function is implemented in the transceiver, ALT --  PATH=1 is understood by the cell firmware to be the more reliable and is used as the &#34;last resort&#34; to get a packet through the network. 
     Status 
     Status request sequences are illustrated in FIG. 8. In order for the cell to read a transceiver register (request status data), the cell&#39;s CPU sets TX --  ADDR.R/W=1 (read), and designates the register to be read with TX --  ADDR.2--0=1--7 (sequence 8B). The transceiver returns the status byte by shifting out the byte in the field RX.DATA.7-0. (Bit 7 is the MSB and is shifted out first.) The transceiver asserts RD/WR --  ACK (sequence 8C) to indicate that the designated register contents are available in RX.DATA.7-0 of the same frame. When the cell requests the contents of a status register, the byte of status information must be in the next frame after the request. The acknowledgement for the request must be in the same frame as the status register contents. 
     The read register command will be sent in consecutive frames at least until the transceiver acknowledges the command and returns the status byte, and the command will be sent for an indeterminate number of frames after the response until the cell CPU clears the latches. The transceiver responds to each read command by returning the data and asserting RD/WR --  ACK for one frame. Once the cell deasserts the read register command (sequence 8D), the transceiver deasserts RD/WR --  ACK for the next succeeding frame (sequence 8E). 
     The transceiver must provide a RD/WR --  ACK for a status request of any register, 1 through 7, regardless of the actual number of status registers implemented on the transceiver. The status registers are read as a result of the node receiving a network management command to do so. It may be assumed that the node issuing the network management command knows which registers are implemented, and what the status registers mean. The RD/WR --  ACK is issued in the frame following the status request command, such that the status byte is in the same frame as the first RD/WR --  ACK. 
     Reset 
     The cell&#39;s external reset signal causes the transceiver to reset its state and internal registers. The transceiver is no longer configured after the external reset signal causes a &#34;hard&#34; reset. Upon hard reset of the transceiver, all configuration information is lost. The cell firmware will then download the configuration registers on the transceiver in descending order. During this time, that is, until configuration register 1 is written, the transceiver must not attempt to send any incoming packets to the cell. 
     The cell may command a &#34;soft&#34; reset by issuing a read status request for register 0 (TX --  ADDR.R/W=1 and TX --  ADDR.2--0=0). If the transceiver is in any state but &#34;IDLE&#34; at the time of such a soft reset, the transceiver aborts whatever it is doing and returns to the &#34;IDLE&#34; state. This soft reset does not cause the transceiver to reset its internal registers. Specifically, the transceiver remains configured after the soft reset command. 
     FIG. 8 shows a state diagram for the transceiver. For each state transition, the input which causes the transition and/or resultant output is identified, together with the resultant output, if any. The input may either be bits of the TX.ST field from the cell, network status, or internal transceiver conditions. The resultant output is the RX.ST field to the cell. 
     Timing 
     The System Clock rate and the Comm Clock rate on the cell must be chosen to ensure proper handshaking; the minimum required clock rates depend on network transmission rate. Timing constraints which are critical to operation of the interface and govern the minimum clock rates are described below: 
     1) To prevent a transmit underflow condition on the transceiver, the transceiver must specify the maximum delay in the cell&#39;s response to TX.DATA --  CTS from the transceiver. The cell&#39;s response may be either TX.DATA --  VALID=1 (another byte to transmit) or TX --  FLAG=0 (end of transmission). 
     2) To prevent receive overrun on cell, the transceiver must specify the minimum time between consecutive assertions of RX.DATA --  VALID from the transceiver, and the cell must be able to receive at that rate. 
     3) All transceivers must be capable of running with the maximum Comm Clock rate of 1.25 MBPS of the cell.