Abstract:
A ΔΣ controlled phase locked loop modulation is used with limited oversampling factors while fulfilling the spectrum and/or phase noise requirements on the modulation in the phase locked loop. By filtering the quantization noise sufficiently then compensating for the distortion of the modulation at the input of the ΔΣ modulator, the required oversampling factor of the ΔΣ controlled phase locked loop modulators can be reduced without loss of performance. The distortion is mitigated by performing a compensation at the input to the ΔΣ modulator. The noise reduction obtained by lowering the bandwidth of the phase locked loop can then be traded to reduce the oversampling factor.

Description:
FIELD OF THE INVENTION 
     The invention relates to all areas where digital communications are performed using phase modulation or other modulation schemes where the phase of the carrier is used to carry information, for example, continuous phase modulation (CPM), frequency shift keying (FSK) and quadrature amplitude modulation (QAM). 
     BACKGROUND OF TIIE INVENTION 
     The implementation of continuous phase modulation has traditionally relied on the use of quadrature modulators. As illustrated in FIG. 1, a digital signal processing unit 101 receives the information to be transmitted via input signal 100 and generates the in-phase and quadrature components of the signal. These components are converted to analog signals using digital/analog converters 102a and 102b and low pass filters 103a and 103b. The output of each filter modulates using multipliers 104a and 104b, one of two carriers 105a or 105b that are separated by 90° in phase. The outputs of the multipliers are then summed in an adder 106 to form the signal 107 which is to be amplified and transmitted. 
     Recently, continuous phase modulation based on using a ΔΣ modulator to control the division factor of a fractional-N phase lock loop was proposed by Riley et al. in &#34;A Simplified Continuous Phase Modulation Technique,&#34; IEEE Transaction on Circuits and Systems-II: Analog and Digital Signal Processing,&#34; Vol. 41, pp. 321-326, May, 1994. Phase locked loop frequency synthesis is a well-known technique for generating one of many related signals from a frequency variable voltage controlled oscillator (VCO). In a phase locked loop (PLL), an output signal from the VCO is coupled to a programmable frequency divider which divides the output signal by a selected integer in order to generate a frequency divided signal that is supplied to a phase detector. The phase detector compares the frequency divided signal to a reference signal from another fixed frequency oscillator which, often, is selected for stability of frequency over time and environmental changes. Any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO in a manner which causes the output signal from the VCO to change in frequency such that the phase error between the frequency divided signal and the reference signal is minimized. With a constant division factor, the output frequency step size is constrained to be equal to the reference signal frequency. With the PLL, an engineering compromise must be struck between the competing requirements of loop lock time, output frequency step size, noise performance and spurious signal generation. 
     In order to overcome the limitations of the PLL, programmable frequency dividers capable of effectively dividing by non-integers have been developed. Output frequency step sizes which are fractions of the reference signal frequency are obtained while maintaining a high reference frequency and wide loop bandwidth. The synthesizers are known as fractional-N frequency synthesizers. 
     Furthermore, a ΔΣ modulator can be used to control the frequency divider of the phase locked loop. Characteristics of a ΔΣ modulator are such that the quantization noise at its output tends to be toward the high end of the spectrum. The ΔΣ modulator is a quantizer that uses feedback to reduce the quantization noise in a limited frequency band. For this application, the ΔΣ modulator should preferably have low quantization noise within the bandwidth of the modulation. The ΔΣ modulator may be any type of ΔΣ modulator, such as one of those described in Steven R. Northsworthy, Richard Schrier and Gabor Temes, Delta-Sigma Data Converters. Theory, Design and Simulation, IEEE Press 1997. 
     A block diagram of a ΔΣ controlled phase locked loop modulator is illustrated in FIG. 2. A periodic reference signal 201 of frequency f ref  is fed to a phase detector 202 together with the phase of the output of the frequency divider 206. The output of the phase detector 202 is a pulse that is related to the phase difference between the reference signal and the output of the frequency divider 206. The output of the phase detector 202 is filtered through a loop filter 203 and fed to a voltage controlled oscillator (VCO) 204. Due to the feedback in the phase locked loop, the frequency of the output 205 of the VCO 204 is driven to equal the reference frequency multiplied by the division factor in the frequency divider 206. Hence, the frequency of the output of the VCO 204 can be controlled by controlling the division factor. In the ΔΣ controlled phase locked loop modulator, the division factors are generated by using a ΔΣ modulator 210. The division factor of the frequency divider can be changed once every period of the reference frequency. A waveform generator 207 generates, based on the information signal 200, the input to the ΔΣ modulator. Channel selection can be performed by adding in an adder 208 an offset 209 to the input of the ΔΣ modulator. The output of the ΔΣ modulator is then used to control the division factor in the frequency divider. 
     The output of the waveform generator is the instantaneous frequency of the desired modulated signal divided by the reference frequency and sampled at the rate of the reference frequency. The oversampling factor, η, of the ΔΣ controlled PLL modulator is ##EQU1## 
     The input to the ΔΣ is the instantaneous frequency of the desired modulated signal sampled at a rate equal to f ref . The reference frequency f ref  is chosen high enough and the bandwidth of the PLL wide enough for the modulation to fulfill the spectrum and/or the phase noise requirement on the modulation. 
     As the phase locked loop is a low pass filter, with respect to the instantaneous frequency, the phase locked loop can be regarded as a means for reconstruction of the desired modulation signal. By choosing the bandwidth of the PLL sufficiently high for the desired modulation to pass, the output of the VCO consists of a signal corresponding to the desired instantaneous frequency and phase noise corresponding to the quantization noise of the ΔΣ modulator. The phase noise can be reduced by either increasing the oversampling factor or by increasing the roll-off of the filtering performed by the phase locked loop. The latter is difficult without jeopardizing the stability margins of the phase locked loop. As a result, prior systems must rely on the use of high oversampling factors. However, a ΔΣ controlled PLL modulator has many benefits. For example, it enables a cost and space efficient implementation, it guarantees continuous phase and the modulation as well as channel selection can be controlled in a purely direct and digital manner. 
     In a mobile station and terminals in cordless cellular and satellite communication systems, or in any other equipment with limited power supply, it is desired to keep the oversampling factor of the PLL as low as possible. With a limited oversampling factor, however, the technique of ΔΣ controlled PLL modulation will fail the spectrum and/or the phase noise requirement on the modulation. This is because the filtering by the PLL will not be able to sufficiently filter the quantization noise without distorting the modulation. Thus, there is a need for a method and apparatus which allows ΔΣ controlled fractional-N PLL modulation with limited oversampling ratios to be used. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, methods and apparatus are disclosed that enable the ΔΣ controlled phase locked loop modulation to be used with limited oversampling factors and thereby fulfill the spectrum and/or phase noise requirements on the modulation in the phase locked loop. By having the phase locked loop filter the quantization noise sufficiently and then compensating for the distortion of the modulation at the input of the ΔΣ modulator, the required oversampling factor of the ΔΣ controlled phase locked loop modulators can be reduced without loss of performance. The present invention mitigates the distortion by performing a compensation at the input to the ΔΣ modulator. This compensation is referred to as pre-filtering. The noise reduction obtained by lowering the bandwidth of the phase locked loop can then be traded to reduce the oversampling factor. 
     According to an exemplary embodiment of the present invention, a continuous phase modulator is disclosed. The continuous phase modulator contains a phase locked loop which has a detector means responsive to a reference signal and a phase control signal for generating a control signal that varies in dependence upon the phase difference between the reference signal and the phase control signal wherein the phase locked loop distorts the modulation of the phase locked loop. Means responsive to the control signal generates an output signal whose frequency varies in dependence upon the control signal. Dividing means divides the output signal to provide the phase control signal, said dividing means having a control input and being operable to vary its division factor in dependence upon a ratio control signal applied to said control input. A ΔΣ modulator provides the division factor control signal. Finally, the input into the ΔΣ modulator means is precompensated so as to compensate for the distortion introduced by the phase locked loop. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will now be described in more detail with reference to the accompanying drawings, in which: 
     FIG. 1 illustrates a prior art quadrature modulator; 
     FIG. 2 illustrates a prior art ΔΣ controlled phase locked loop for generating continuous phase modulation; 
     FIG. 3 illustrates a method for producing a GMSK modulated signal; 
     FIGS. 4(a)-4(b) illustrate the generation of GMSK modulated signals according to several exemplary embodiments of the present invention; 
     FIG. 5 is a block diagram of a radio transceiver which may employ the present invention; 
     FIG. 6 illustrates a predistorted ΔΣ controlled phase locked loop for generating continuous phase modulation according to an exemplary embodiment of the present invention; and 
     FIG. 7 is a graph showing exemplary impulse responses of a pulse-shaping filter in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     The invention relates to continuous phase modulation (CPM). One example of a communication system where CPM is used is the GSM/DCS system. Although the invention is particularly suitable for a portable communications device, such as mobile stations and terminals in cordless cellular and satellite communication systems, the invention is not limited thereto. 
     A radio transceiver that is useful in a digital radio telephone system may advantageously employ the present invention. The GSM Pan European Digital Radio Telephone System requires radio equipment capable of rapid changes of frequency and uses Gaussian Minimum Shift Keying (GMSK) modulation for the transmission of the digital data and digitized voice information. FIG. 3 illustrates a prior art method of producing a GMSK modulated signal. In FIG. 3, a data signal takes on a +1 signal value for a binary `1` and alternatively a -1 signal value for a binary `0`. The data signal is passed through a low-pass filter 300 which has a Gaussian filter response to produce a rounded frequency-modulating waveform. In the context of a modulator having the form illustrated in FIG. 2, the Gaussian low-pass filter 300 corresponds to the waveform generator 207. If the Gaussian filter has a DC gain of unity, the filtered data values (i.e., the rounded frequency-modulating waveform 301) will peak at +1 for a long series of continuous binary `1s` applied to the input, or -1 for a series of binary `0`s. 
     The rounded frequency-modulating waveform 301 is applied to an exact frequency modulator 302 which generates a frequency (Fo+bitrate/4) for a value of +1 at its input and (Fo-bitrate/4) for a value of -1 at its input. The frequency deviation of +bitrate/4 corresponding to +1 at its input causes one quarter of a cycle (i.e., 90°) change in phase over one bit period, while an offset of -bitrate/4 causes a change in phase of -90° over a bit period. It is important for these frequency offsets to be exact or else there will be a cumulative deviation of the signal phase value from its expected phase when a series of `1`s or `0`s is applied at the data input. 
     Two exemplary embodiments of the present invention for generating GMSK modulated signals are illustrated in FIGS. 4(a)-4(b). Comparing FIG. 4(a) with FIG. 3, the ΔΣ modulator together with the PLL can be regarded as a frequency modulator. This frequency modulation is not perfect, however, and therefore compensation is performed at the input to the frequency modulator. In FIG. 4(a), the data signal is supplied to a Gaussian low pass filter 401 which outputs a filtered data signal 402. The filtered data signal 402 is then compensated in a compensator 403 which outputs a filtered and compensated data signal 404. The compensated data signal 404 is combined with a channel selection signal in a combiner 405 and is then applied to the ΔΣ-controlled PLL (distorted frequency modulator 406). The modulator 406 then outputs the GMSK signal 407. In FIG. 4(b), the compensation device and the Gaussian low pass filter are included in the same filter 410. The data signal is applied to the filter 410 which outputs a filtered and compensated signal 411. The compensated signal 411 is combined with the channel selection signal in a combiner 412 and is then supplied to the ΔΣ-controlled PLL (distorted frequency modulator 413). The modulator 413 then outputs the GMSK signal 414. 
     A transceiver which can employ the present invention is illustrated in FIG. 5. A reference oscillator 501 provides a reference signal, f ref , which remains relatively constant in frequency over time and in extremes of environment and is applied to a ΔΣ-controlled phase locked loop 503 along with the information to be transmitted. The output of the ΔΣ-controlled phase locked loop 503 is used by both the receiver 505 and the transmitter 507 to produce the local oscillator signal and the modulated transmit signal, respectively. In particular, the ΔΣ-controlled phase locked loop 503 supplies a phase-modulated signal to the transmitter 507, and a carrier signal to the receiver 505. In alternative embodiments, amplitude modulation can additionally be introduced in the transmitter 507 when, for example QAM is used. In this case, information to be transmitted should also be supplied to the transmitter 507. In any case, control over functions of the transceiver, such as channel of operation frequency, is provided by the control logic 509. 
     According to the present invention, the transceiver can be enhanced by using the predistorted ΔΣ controlled phase locked loop modulator depicted in FIG. 6. The phase locked loop consists of a phase detector 602, a loop filter 603, a voltage controlled oscillator 604, and a frequency divider 606. A periodic reference signal 601 of frequency f ref  is fed to the phase detector 602 together with the phase of the output of the frequency divider 606. The output of the phase detector 602 is a pulse that is related to the phase difference between the reference signal and the output of the frequency divider 606. The output of the frequency detector 602 is filtered through a loop filter 603 and fed to a voltage controlled oscillator (VCO) 604. Due to the feedback in the phase locked loop, the frequency of the output of the VCO 604 is driven to equal the reference frequency multiplied by the division factor in the frequency divider 606. Hence, the frequency of the VCO 604 can be controlled by controlling the division factor. In the ΔΣ controlled phase locked loop modulator, the division factors are generated by using a ΔΣ modulator 610. According to this exemplary embodiment, the phase locked loop is designed so as to filter the phase noise sufficiently to fulfill the spectrum and/or the phase noise requirements on the modulation. 
     A waveform generator 607 receives an information signal 600 and generates an input to the ΔΣ modulator 610. The signal is predistorted in 611 so as to compensate for the distortion caused by the phase locked loop. By having the phase locked loop distort the modulation and by compensating for this distortion at the input of the ΔΣ modulator, the required oversampling factor of the ΔΣ controlled phase locked loop modulators can be reduced without loss of performance. Channel selection can be performed by adding in an adder 608 an offset 609 to the input of the ΔΣ modulator 610. The frequency divider is controlled by the ΔΣ modulator 610. The choice of the ΔΣ modulator is dependent on the application. Higher order ΔΣ modulators, possibly implemented using multi-stage (cascade) structures, could also be used. In general, the sampling rate and the number of stages in the ΔΣ modulator should be optimized with respect to the modulation bandwidth and method. To enable channel selection over a wide frequency range, the ΔΣ modulator 610 is preferably implemented as a multi-level ΔΣ modulator. The reference signal 601 is preferably a periodic signal. The output of the VCO forms the signal 605 which is to be amplified and transmitted. 
     As noted above, predistortion could be implemented by distorting the input of the ΔΣ modulator 610, that is, the desired instantaneous frequency, or by using a waveform generator where the desired predistortion affects the pulse shaping as defined by the modulation scheme. Predistortion enables the use of a phase locked loop with a bandwidth less than the bandwidth of the modulation. Thus, predistortion can be used as a means to relax the requirements on the loop filter, increase the stability margin of the phase locked loop, and enhance the performance. 
     The nature of the predistortion that compensates for the distortion in the phase locked loop will be further understood from the following discussion. A transfer function describing the influence of the division factor, N, on the instantaneous frequency of the output of the VCO 604 is given by ##EQU2## where H(s) is the transfer function of the loop filter 603, f ref  is the frequency of the reference signal 601, K VCO  is the gain in the VCO 604, N 0  is the average value of the division factor, N over time, and I phd  is the gain in the phase detector 602. 
     The loop filter 603 is chosen such that the transfer function shown in Equation (2) is low-pass and the most important design parameter is its bandwidth. With a narrow bandwidth, the phase locked loop efficiently filters reference noise, internal noise and quantization noise. If the bandwidth of the phase locked loop is less than the bandwidth of the modulation, however, the phase locked loop will linearly distort the modulated signal. The invention addresses this problem by having a phase locked loop with a bandwidth less than the bandwidth of the modulation, and compensating for the linear distortion at the input of the ΔΣ modulator 610. The compensation is then a linear filter having an impulse response that equals or approximates the inverse of Equation (2). 
     The compensation may be combined together with the shaping as defined by the modulation. What follows is an example showing how this can be done for GMSK modulation. Let f(t) denote the impulse response of F(s)/f ref . Furthermore, let g(t) denote the desired pulse-shaping. For the GSM system, we have ##EQU3## where the function rect(x) is defined by ##EQU4## and the operator &#34;*&#34; denotes convolution. Also, a(t) is defined by ##EQU5## 
     In order to have a convenient description of the design procedure, the previously mentioned quantities are sampled with a sampling rate equal to 1/T and a matrix formalism is used to represent the signals. Let h denote an L×1 vector which represents the impulse response of the compensated pulse-shaping. Let f denote an N×1-vector containing f(Tk) for k=0, 1, 2 . . . , N-1 and let g denote an N×1-vector containing g(Tk-3/2T b ) for k=0, 1, 2 . . . , N+L-2. A convolution matrix F of dimension ((N+L-2)×L) can now be constructed from f as ##EQU6## and the design problem can be formulated using matrix notations as follows. The overall pulse shaping is given by Fh. The desired pulse-shaping is given by g. The problem is to find an h so that Fh is as close to g as possible. One important characteristic of g is its static gain. This is because a deviation from the correct static gain may cause the phase of the VCO 604 to drift. In this description we consider the criteria: ##EQU7## subject to ##EQU8## The solution is given by ##EQU9## where 
     
         c=(F.sup.T F).sup.-1 F.sup.T g                             (9) 
    
     In FIG. 7, the impulse response of the pulse-shaping filter, g, is depicted for the uncompensated case as defined by GMSK modulation together with impulse responses that are compensated for three different phase locked loops having different bandwidths. Graph 701 depicts the pulse-shaping filter&#39;s impulse response for use with a phase locked loop having a bandwidth of 70 kHz. Graph 703 depicts the pulse-shaping filter&#39;s impulse response for use with a phase locked loop having a bandwidth of 120 kHz. Graph 705 depicts the pulse-shaping filter&#39;s impulse response for use with a phase locked loop having a bandwidth of 220 kHz. Finally, graph 707 depicts the shaping defined by GMSK modulation without any compensation. The sampling rate was 13/48/8 MS/s and the length of each shaping filter is 96 samples (12 symbols). The ringing in the lower right hand side of the figure is associated with graph 701 (i.e., the graph associated with the phase locked loop having a bandwidth equal to 70 kHz), and indicates that the length of the pre-filter may be too short: the compensated shaping may not be able to sufficiently compensate for the distortion in the phase locked loop. 
     It will be apparent to those of ordinary skill in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are, therefore, intended in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes which come within the meaning and range of equivalents thereof are intended to be embraced therein.