Abstract:
The present invention relates to a semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without necessitating a dead cycle. The elimination of the dead cycle between read and write operations improves bus efficiency and thus, speed. The memory device of the present invention includes an address input control means for receiving an external write or read address and delaying the write address by either 1 or 2 cycles. A data input control means receives external write data and delays the write data by a first or second predetermined number of cycles according to the write mode. A data transmission control means transmits the delayed write data responsive to a predetermined set of input commands. The data input control means reads the data from a cell corresponding to the read address, provides the write data to a cell corresponding to the write address, and writes the transmitted delayed data into the cell corresponding to the write address.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device that can perform a write operation 1 cycle or 2 cycles after receiving a write command without a dead cycle. 
     2. Description of the Prior Art 
     A semiconductor memory device provided with a conventional write function after 1 cycle or 2 cycles is provided with a write address during the execution of a write command. After receiving the write command and before executing the write operation, the memory device is also provided with external write data after delaying 1 or 2 cycles measured from the time of the previously provided write address. 
     The semiconductor memory device having such a conventional write function requires a dead cycle when changing from a read operation to a write operation and vice versa. A dead cycle requires a no operation (NOP) state that detrimentally affects bus efficiency. Accordingly, a need remains for a semiconductor memory device that can perform the write operation after 1 or 2 cycles without the need for a dead cycle. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to overcome the problems associated with prior art semiconductor memory devices. 
     A further object of the present invention is to provide a semiconductor memory device for executing a write function after 1 or 2 cycles without necessitating a dead cycle. 
     To achieve the above-described objects, a semiconductor memory device is provided. The memory device comprises address input control means for receiving an external write or read address and delaying the write address by 1 cycle when the memory device operates in a write after 1 cycle mode or by 2 cycles when the memory device operates in a write after 2 cycles mode. A data input control means receives external write data and delaying the write data by a first predetermined number of cycles when the memory device operates in the write after 1 cycle mode or delaying the write data by a second predetermined number of cycles when the memory device operates in the write after 2 cycles mode. A data transmission control means transmits the delayed write data responsive to a predetermined set of input commands. The data input control means reads the data from a cell corresponding to the read address, provides the write data to a cell corresponding to the write address using a flow through method in the write after 1 cycle mode and using a pipeline method in the write after 2 cycles mode, and writes the transmitted delayed data into the cell corresponding to the write address. The first predetermined number of cycles is either 0 or 1 and the second predetermined number of cycles are 0, 1, or 2. The data transmission control means transmits write data delayed by 0 cycles when a write, write command sequence is received in the write after 1 cycle mode, transmits write data delayed by 1 cycle when a read, write command sequence is received in the write after 1 cycle mode, transmits write data delayed by 0 cycles when a write, write, write command sequence is received in the write after 2 cycles mode, transmits write data delayed by 1 cycle when either a write, read, write or a read, write, write command sequence is received in the write after 2 cycles mode, and transmits write data delayed by 2 cycles when a read, read, write command sequence is received in the write after 2 cycles mode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features, and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment that proceeds with reference to the following drawings. 
     FIG. 1 is a block diagram of a semiconductor memory device according to the present invention. 
     FIG. 2 is a circuit diagram of the data input register and the data transmission control part shown in FIG.  1 . 
     FIG. 3 is a circuit diagram of the data signal generating part shown in FIG.  1 . 
     FIG. 4 is a circuit diagram of the data output buffer shown in FIG.  1 . 
     FIG. 5 is a timing diagram of the write operation after 1 cycle for the device shown in FIG. 1 . 
     FIG. 6 is a timing diagram of the write operation after 2 cycles for the device shown in FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram of the semiconductor memory device according to the present invention. The semiconductor memory device is comprised of m×n number of memory cells, e.g.,  10 - 1 ,  10 - 2 , . . . ,  10 -m, precharging and equalizing circuits  12 - 1 ,  12 - 2 , . . . ,  12 -m, column selection switches  14 - 1 ,  14 - 2 , . . . ,  14 -m, a row address decoder  16 , a column address decoder  18 , a write driver  20 , a sense amplifier  22 , an address input buffer  24 , address input registers  26  and  28 , a multiplexer  30 , a data input buffer  32 , data input registers  34 ,  36 , and  38 , a data transmission control part  40 , a data output buffer  42 , switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , and S 7 , a WE input buffer  44 , WE input registers  46 ,  48 , and  50 , and a control signal generating part  52 . 
     The m×n memory cells either transmit the data stored in each memory cell to the pertinent bit line pair (BL 1 , BL 1 B), (BL 2 , BL 2 B), . . . , (BLm, BLmB) or store the data transmitted to the pertinent bit line pair in the corresponding memory cell. The precharging and equalizing circuits  12 - 1 ,  12 - 2 , . . . ,  12 -m precharge and equalize the pertinent bit line pair (BL 1 , BL 1 B), (BL 2 , BL 2 B), . . . , (BLm, BLmB). The column selection switches  14 - 1 ,  14 - 2 , . . . ,  14 -m control the transmission of data between the pertinent bit line pair and the corresponding data line pair DLk, DLBk. The row address decoder  16  decodes the row address signal X and generates n number of word line selection signals WL 1 , WL 2 , . . . , WLn. The column address decoder  18  decodes the column address signal Y and generates the control signals for controlling m number of column selection switches. The address input buffer  24  buffers and outputs the externally provided address XAi. The address input registers  26  and  28  respond to the control signal C 0  and delay the address XAi by one and two cycles, respectively, outputting the signal WA 1  and WA 2 , respectively. The control signal C 0  is the signal resulting from the logical multiplication of a clock signal CLK and a write enable signal WE. The multiplexer  30  selects the read address RA buffered by the address input buffer  24  responsive to a read enable signal RE. During the execution of the write operation after 1 cycle, the multiplexer  30  outputs a write address WA 1  responsive to a write enable signal WE. During the execution of the write operation after 2 cycles the multiplexer  30  selects and outputs a write address WA 2  also responsive to the write enable signal WE. The data input buffer  32  buffers and outputs the externally provided data input signal XDj. The data input registers  34 ,  36 , and  38  generates signals I 1 , I 2 , and I 3 , respectively, by delaying the data input signal XDj buffered by the data input buffer  32  by 0, 1, or 2 cycles, respectively, responsive to the data input control clock DINCLK. The data input control clock DINCLK is synchronized with the clock signal CLK 1 cycle after execution of the write command begins. The data input control clock DINCLK is also synchronized with the clock signal CLK 2 cycles after the execution of the write command begins. After executing write operation for 1 cycle, the data transmission control part  40 , selects the I 1  signal output from the data input register  34  responsive to a control signal C 1  and selects the I 2  signal output from the data input register  36  responsive to a control signal C 2 . 
     After executing the write operation for 2 cycles, the data transmission control part  40 , selects the I 1  signal output from the data input register  34  responsive to control signal C 1 , selects the I 2  signal output from the data input register  36  responsive to the control signal C 2 , and selects the I 3  signal output from the data input register  38  responsive to the control signal C 3 . 
     The data output buffer  42  generates the data amplified by the sense amplifier  22  as an output signal XD 0 y responsive to the signals KDATA and OE after 1 cycle of executing the write operation. The data output buffer generates a 1 cycle delayed version of the output signal XD 0 y responsive to the signal KDATA and OE after 2 cycles of executing the write operation. The WE input buffer  44  receives and buffers the write enable signal WE. The WE input registers  46 ,  48 , and  50  delay by 0,1 and 2 cycles, respectively, the buffered write enable signal and output them as the signals W 1 , W 2 , and W 3 , respectively. The control signal generating part  52  receives the signals W 1  and W 2  during the execution of the write operation after 1 cycle and generates the control signals C 1  and C 2 . The control signal generating part  52  also receives the signals W 1 , W 2 , and W 3  during execution of the write operation after 2 cycles and generates the control signals C 1 , C 2 , C 3 . In other words, the WE input buffer  44 , the WE input registers  46 ,  48 , and  50  and the control signal generating part  52  generate the control signal C 1  when the write, write command is continuously inputted during the execution of the write operation after 1 cycle and generate the control signal C 2  when the read, write command is continuously inputted. In addition, the WE input buffer  44 , WE input registers  46 ,  48 , and  50 , and the control signal generating part  52  generate the control signal C 1  when the write, write, write command is continuously inputted during the execution of the write operation after 2 cycles. The WE input buffer  44 , WE input registers  46 ,  48 , and  50 , and the control signal generating part  52  generate the control signal C 2  when the read, write, write command or the write, read, write command is continuously inputted and generate the control signal C 3  when the read, read, write command is continuously inputted. During the execution of the write command after 1 cycle, the switch S 1  is turned on, and the switches S 2 , S 3 , S 4 , S 5 , S 6 , and S 7  are turned off. During the execution of the write operation after 2 cycles, the switch S 1  is turned off, and the switches S 2 , S 3 , S 4 , S 5 , S 6 , and S 7  are turned on. 
     FIG. 2 shows the circuit of the data transmission control part  40  and the data input registers  34 ,  36 , and  38  shown in FIG.  1 . The data input register  34  is comprised of the latch made of an inverter  60 , a CMOS transmission gate  62 , and inverters  64  and  66 . The CMOS transmission gate  62  responds to a low data input control clock DINCLK and transmits an output signal IN of the data input buffer  32 . The latch made of the inverters  64  and  66  latch and reverse the output signal of the CMOS transmission gate  62  and outputs a signal I 1 . 
     The data input register  36  comprises the latches respectively made of inverters  68  and  76 , CMOS transmission gates  70  and  78 , and inverters  72  and  74  and  80  and  82 . The CMOS transmission gate  70  transmits the signal I 1  responsive to a high data input control clock DINCLK. The latch made of the inverters  72  and  74  latches, inverts and outputs the output signal of the CMOS transmission gate  70 . The CMOS transmission gate  78  transmits the output signal of the inverter  72  responsive to a low data input control clock DINCLK. The latch made of the inverters  80  and  82  latches, inverts, and outputs the output signal of the CMOS transmission gate  78 . 
     The data input register  38  is comprised of the latches respectively made of inverters  84 ,  92 , CMOS transmission gates  86  and  94  and inverters  88  and  90  and  96  and  98 . The construction and function of the data input register  38  is the same as that of the data input register  36 . In other words, the CMOS transmission gate  86  transmits a signal I 2  responsive to a high data input control clock DINCLK. The latch made of the inverters  88  and  90  latches, inverts, and outputs the output signal of the CMOS transmission gate  86 . The CMOS transmission gate  94  transmits an output signal of the inverter  88  responsive to a low data input control clock DINCLK. The latch made of the inverters  96  and  98  latches, inverts, and output as signal I 3 , an output signal of the CMOS transmission gate  94 . 
     The data transmission control part  40  is comprised of the latch made of inverters  100 ,  104  and  108 , CMOS transmission gates  102 ,  106 , and  110  and inverters  112  and  114 . The CMOS transmission gates  102 ,  106 , and  110  respectively transmit the signals I 1 , I 2 , and I 3  responsive to high control signals C 1 , C 2 , and C 3 , respectively. The latch made of the inverters  112  and  114  latches and inverts an output signal of the CMOS transmission gates  102 ,  106  and  110  and outputs it as the signal WD. The construction and function of the switches S 4  and S 5  are well known and will not be described in further detail. 
     FIG. 3 shows the circuit of the control signal generating part  52  shown in FIG.  1 . The write enable signal input buffer  44  is comprised of two serially connected inverters  120  and  122 . The write enable signal input buffer  44  receives the write enable signal WE and buffers it. 
     The WE input register  46  is comprised of the latches respectively made of inverters  124  and  132 , CMOS transmission gates  126  and  134 , inverters  128  and  130  and  136  and  138 . The CMOS transmission gate  126  transmits the buffered write enable signal WE responsive to a low clock signal CLK. The latch made of the inverters  128  and  130  latches, inverts and outputs the buffered write enable signal WE. The CMOS transmission gate  134  transmits an output signal of the inverter  128  responsive to a high clock signal CLK. The latch made of inverters  136  and  138  latches an output signal of the CMOS transmission gate  134 , inverts it, and outputs it as the signal W 1 . 
     The WE input register  48  is comprised of the latches respectively made of inverters  140  and  148 , CMOS transmission gates  142  and  150 , and inverters  144 ,  146 ,  152 , and  154 . The construction and function of the WE input register  48  is the same as that of the WE input register  46 . The circuit outputs an output signal of the inverter  152  as the signal W 2 . 
     The WE input register  50  is comprised of the latches respectively made of inverters  156  and  164 , CMOS transmission gates  158  and  166 , and inverters  160  and  162  and  168  and  170 . The construction and function of the WE input register  50  is the same as that of the WE input registers  46  and  48  described above. The WE input register  50  outputs a W 3  signal out of the inverter  168 . 
     The control signal generating part  52  is comprised of NAND gates  176 ,  182 ,  190 ,  194 , and  198 , NOR gates  174 ,  178 ,  184 ,  192 ,  196 , and  199 , inverters  180  and  188 , a XNOR gate  186  and switches S 8 , S 9 , S 10 , S 11 , S 12 . 
     During the execution of the write operation after 1 cycle, the switches S 9  and S 11  are turned on and the switches S 6 , S 7 , S 8 , S 10 , and S 12  are turned off. In this case, the NAND gate  194  generates a low signal if the signals W 1  and W 2  are at highs. The NOR gate  196  responds to the clock signal inverted by the inverter  172 , inverts an output signal of the NAND gate  194 , and generates the control signal C 1 . In other words, NOR gate  196  inverts the output signal of the NAND gate  194  when the clock signal is at a high. The inverter  180  and the NAND gate  182  generate a low signal if a low signal W 2  and a high signal W 1  are inputted. The NOR gate  184  responds to the inverted clock signal output from inverter  172 , inverts the output signal of the NAND gate  182 , and generates the control signal C 2 . 
     During the execution of the write command after 2 cycles, the switches S 6 , S 7 , S 8 , S 10 , and S 12  are turned on, and the switches S 9  and S 11  are turned off. In this case, the NAND gate  198  generates a low signal if high signals W 1 , W 2 , and W 3  are inputted. The NOR gate  199  responds to the inverted clock signal output from inverter  172 , inverts an output signal of the NAND gate  198  and outputs the control signal C 1 . The XNOR gate  186  and the inverter  188  generate a high signal if a high signal W 2  and a low signal W 3  are inputted or if a low signal W 2  and a high signal W 3  are inputted. The NAND gate  190  generates a low signal if a high signal W 1  and a high signal is output from the inverter  188 . The NOR gate  192  responds to the inverted clock signal output from inverter  172 , inverts an output signal of the NAND gate  182 , and generates the control signal C 2 . The NOR gate  174  generates a high signal if low signals W 2 , W 3  are inputted. The NAND gate  176  generates a low signal if a high signal W 1  and a high output signal of the NOR gate  174  are inputted. The NOR gate  178  responds to the inverted clock signal output from inverter  172 , inverts an output signal of the NAND gate  176 , and generates the control signal C 3 . 
     FIG. 4 shows the circuit of the data output buffer  42  shown in FIG.  1 . The data output buffer  42  is comprised of the latch made of PMOS transistors  200 ,  202 ,  204 ,  218 ,  220 ,  224 , and  226 , NMOS transistors  206 ,  208 ,  210 ,  212 ,  222 , and  228 , inverters  214 ,  216 ,  234 ,  236 ,  244 , and  248 , NOR gates  238  and  240 , NAND gates  242  and  246 , and inverters  230  and  232 . 
     An enable circuit comprises the PMOS transistors  200 ,  202 , and  204  and the NMOS transistors  206 ,  208 ,  210 , and  212 . During the execution of the write operation, the PMOS transistor  200  is turned off because an enable signal KDPRECB has a high level and the NMOS transistors  210  and  212  are turned on. Thus, the data line pair DTA and DTAB is at a low. Because the enable signal KDPRECB is at a low during the execution of the read operation, the PMOS transistors  200  is turned on and the NMOS transistors  210  and  212  are turned off. This results in amplifying the sense amplifier output signals SAS and SASB and transmitting them to the data line pair DTA and DTAB. 
     In the latch made of the inverters  214  and  216 , the PMOS transistors  218 ,  220 ,  224 , and  226 , the NMOS transistors  222  and  228  and the inverters  230  and  232  during the execution of the write operation, the data of the data line pair DTA and DTAB is at a low level, and the PMOS transistors  220 ,  226  and the NMOS transistors  222  and  228  are turned off. The PMOS transistors  218  and  224  are turned on and the data latched in the latch  230  and  232  is maintained in the data line pair DTBB and DTB. During the execution of the read operation, the data transmitted to the data line pair DTA and DTAB is respectively inverted and transmitted as the data line pair DTB and DTBB. 
     The circuit made of the inverters  234  and  236  and the NOR gates  238  and  240  respectively invert the data transmitted to the data line pair DTBB and DTB by the signal synchronized with the clock signal CLK, and output it to the data line pair DTC and DTCB. In other words, the circuit respectively inverts the data transmitted to the data line pair DTBB and DTB and transmits it to the data line pair DTC and DTCB when the signal KDATA changes from a low to high. The signal KDATA is enabled to buffer and output a signal out of the sense amplifier  22  during the execution of the write operation after 1 cycle. The data output buffer  42  buffers and latches the output signal of the sense amplifier  22  during the execution of the write operation after 2 cycles and is enabled to delay the data latched by 1 cycle and output it. In other words, the signal KDATA is enabled in order to output the read data in the current cycle in case the execution of the write operation after 1 cycle. Conversely, the signal KDATA is enabled to output the read data in the next cycle in case of the execution of the write operation after 2 cycles. But the timing of the latch  230  and  232  is the same during the execution of the write operation after 1 cycle or 2 cycles. The only difference is in the timing of the output signal pair D 0 U and D 0 D by the signal KDATA. 
     The circuit comprised of the NAND gates  242  and  246  and the inverters  244  and  248  responds to the output enable signal OE, and respectively outputs the signals transmitted to the data line pair DTC and DTCB as the data output signal pair D 0 U and D 0 D. In other words, the read method during the execution of the write operation after 1 cycle uses a flow-through process responsive to the data latched in the data output buffer  42  and outputs it in the current cycle. During the execution of the read method after 2 cycles, the method uses a pipelined process responsive to the data latched in the data output buffer  42  and outputs it in the next cycle. 
     What follows is an explanation of the address and data processing method during the execution of the write operation after 1 or 2 cycles of the semiconductor memory device of the invention shown in FIG.  1 . First, the write operation after 1 cycle can be classified into two cases. In the first case, the write, write command is continuously inputted and the write data inputted during the second write command is written in the cell. In the second case, the read, write command is continuously inputted and the write data corresponding to the last write command inputted before the continuous read, write command is written in the cell during the second write command. 
     FIG. 5 is a timing diagram of the write operation after 1 cycle of the device shown in FIG. 1 where the write data is inputted after 1 cycle of the write address input. At this time, the switch S 1  is turned on, the switches S 2 , S 3 , S 4 , S 5 , S 6 , and S 7  are turned off, the switches S 8 , S 10 , and S 12  (FIG. 3) are turned off, and the switches S 9  and S 11  are turned on. 
     If the write command is inputted during the first cycle, the address input buffer  24  buffers an external address A 0  and provides it to an address input register. The address input register  26  responds to a high control signal C 0  and latches the address A 0 . The data input buffer  32  buffers the data D 0  and outputs it. The data input register  34  outputs the data D 0  responsive to a low data input control clock DINCLK. The WE input buffer  44  receives the write enable signal WE and buffers it. The WE input register  46  latches the WE signal responsive to the DINCLK signal and outputs the latched signal as W 1 . 
     If the write command is inputted during the second cycle, the address input buffer  24  buffers an external write address A 1  and outputs it to the address input register  26 . The address input register  26  outputs the address A 0  as the signal WA 1  responsive to a high control signal C 0 . The address input register  26  outputs the address A 1  as the signal WA 1  responsive to the low control signal C 0 . The data input register  34  outputs the data D 0  as the signal I 1  responsive to a high data input control clock DINCLK. The data input register  34  outputs the data D 1  as the signal I 1  responsive to a low control clock DINCLK. The data input buffer  32  responds to the low data input control clock DINCLK, buffers the data D 1 , and outputs it. The data input register  36  outputs the data D 0  responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers and outputs the WE signal. The WE input registers  46  and  48  output high W 1  and W 2  signals. The control signal generating part  52  generates the control signal C 1  resulting from the logical multiplication of the signals W 1  and W 2  responsive to a high clock signal CLK. The data transmission control part  40  responds to the control signal C 1 , latches the data D 0  outputted from the data input register  34 , and provides it as the signal WD. Therefore, the write operation of the write data D 0  pertinent to the address A 0  is executed. 
     The first cycle I and the second cycle II in FIG. 5 are pertinent to the first case (write, write case). If the read command is inputted during the third cycle, the address input buffer  24  buffers an external read address A 2  and outputs it to the multiplexer  30 . The address input register  26  outputs the address A 1  as the signal WA 1  responsive to the low control signal C 0 . The data input register  34  transmits the data D 1  as the signal I 1  responsive to the high data input control clock DINCLK. The data input register  36  transmits the data D 1  as the signal I 2  responsive to the high data input control clock DINCLK. The data input register  36  transmits the data D 1  as the signal I 2  responsive to the low control clock DINCLK. The WE input registers  46  and  48  generate low and high signals respectively as the signals W 1  and W 2 . The control signal generating part  52  does not generate the control signals C 1  and C 2  during this period. Therefore, the write operation is not executed. The data read operation by the flow through process is executed and the output data Q 2  is generated as the output signal XD 0 y. 
     If the write command is inputted during the fourth cycle, the address input buffer  24  buffers the address A 3  and outputs it. The address input register  26  outputs the address A 1  as the address WA 1  responsive to the high control signal C 0 . The address input register  26  outputs the address A 3  as the address WA 1  responsive to the low control signal C 0 . The data  20  input buffer  32  buffers the data D 3  and outputs it. The data input register  34  outputs the data D 3  responsive to the low data input control clock DINCLK. The data input register  36  outputs the data D 1  responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers the WE input and outputs it. The WE input registers  46  and  48  provide a high signal W 1  and a low signal W 2 . The control signal generating part  52  generates the  25  control signal C 2  responsive to a high clock signal. The data transmission control part  40  transmits the data D 1  as the signal WD responsive to the control signal C 2 . Therefore, the read operation of the write data D 1  pertinent to the address A 1  is executed. 
     The third cycle III and the fourth cycle IV in FIG. 5 are pertinent to the second case (read, write case). As shown in the timing diagram of FIG. 5, the write data D 0  is transmitted to the data line pair in the second write cycle the read data Q is transmitted from the cell to the data line pair in the third read cycle, and write data D 1  is transmitted to the data line pair in the fourth write cycle. Therefore, the problem of the data collision in the data line pair does not occur. 
     The write operation after 2 cycles can be classified into the three cases described below. In the first case, the write, write, write command is continuously inputted, and the write data inputted during the input of the third write command is written in the cell. In the second case, the write, read, write command is continuously inputted, or the read, write, write command is continuously inputted. The write data corresponding to the last write command before the continuous write, read, write or read, write, write command is written in the cell responsive to the third write command. In the third case, the read, read, write command is inputted and the write data pertinent to the write command inputted first among the 2 numbers of write data inputted before this continuous command is written in the cell. 
     The first cycle I, the second cycle II and the third cycle III in FIG. 6 are pertinent to the first case. The third cycle III, the fourth cycle IV and the fifth cycle V in FIG. 6 are pertinent to the second case. The fourth cycle IV, the fifth cycle V and the sixth cycle VI in FIG. 6 are pertinent to the other second case. The seventh cycle, VII, the eighth cycle VIII  15  and the ninth cycle IX in FIG. 6 are pertinent to the third case described. FIG. 6 is a timing diagram of the write operation after 2 cycles for the device shown in FIG.  1 . The write data is inputted within the 2 cycles of the input of the write address. In this case, the switch S 1  (FIG. 1) is turned off, the switches S 2 , S 3 , S 4 , S 5 , S 6 , and S 7  are turned on, the switches S 8 , S 10 , S 12  (FIG. 3) are turned on, and the switches S 9  and S 11  are turned off. 
     If a write command is input during the first cycle, the address input buffer  24  buffers the address A 0  and outputs it. The address input register  26  outputs the address A 0  responsive to the low control signal C 0 . The WE input buffer  44  buffers and outputs the WE signal. The WE input registers  46 ,  48  and  50  output a high signal W 1 , a low signal W 2 , and a low signal W 3 . 
     If a write command is input during the second cycle, the address input buffer  24  buffers and outputs the address A 1 . The address input register  26  outputs the address A 0  responsive to the high control signal C 0 . The address input register  26  outputs the address A 1  responsive to the low control signal C 0 . The address input register  28  outputs the address A 0  responsive to the low control signal C 0 . The data input buffer  32  buffers and outputs the data D 0 . The data input register  34  outputs the data D 0  responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers the WE signal and outputs it. The WE input registers  46 ,  48 , and  50  respectively generate high W 1  and W 2  signals and a low W 3  signal. 
     If a write command is input during the third cycle, the address input buffer  24  buffers and outputs the address A 2 . The address input registers  26  and  28  output the address A 1  and the address A 0  respectively responsive to the high control signal C 0 . The address input registers  26  and  28  output the address A 2  and the address A 1 , respectively, responsive to the low control signal C 0 . The data input register  34  outputs data D 2  as the signal I 1  responsive to the high data input control clock DINCLK. The data input register  34  outputs the data D 1  as the signal I 1  responsive to the high data input control clock DINCLK. The data input register  36  outputs the data D 0  as the signal I 2  responsive to the low data input control clock DINCLK. The WE input buffer  44  outputs high signals W 1 , W 2 , and W 3 . The control signal generating part  52  receives the signals W 1 , W 2 , and W 3  and generates the control signal C 1  responsive to the high clock signal CLK. The data transmission control part  40  outputs the data D 0  as the signal WD responsive to the control signal C 1 . Thus, the write operation for the write data D 0  corresponding to the address A 0  is executed. 
     If a read command is input during the fourth cycle, the address input buffer  24  buffers the read address A 3  and outputs it to the multiplexer  30 . The address input registers  34  and  36  output the address A 2 , A 1  as the signals WA 1 , WA 2  respectively responsive to the low control signal C 0 . The data buffer  32  buffers and outputs the data D 1 . The data input registers  34  and  36  output the data D 1 , D 0  respectively, responsive to the high data input control clock DINCLK. Additionally, the data input registers  34  and  36  output the data D 2  and D 1 , respectively, responsive to the low data input control clock DINCLK. The data input register  38  outputs the data D 0  responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers the WE signal and outputs the buffered WE signal. The WE input registers  46 ,  48 , and  50  output low, high, and high signals W 1 , W 2 , and W 3 , respectively. Since a read command is input, the control signal generating part  52  does not generate the control signals C 1 , C 2 , and C 3 . The data transmission control part  40  outputs the latched data D 0 . Then, the read operation of the read data pertinent to the address A 3  is executed. 
     If a write command is input during the fifth cycle, the address input buffer receives the address A 4  and buffers it. The address input registers  26  and  28  output the addresses A 2  and A 1 , respectively, responsive to the high control signal C 0 . Conversely, the address input registers  26  and  28  output the addresses A 4  and A 2 , respectively, to the low control signal C 0 . The data input buffer  32  buffers the data D 2  and outputs the buffered data D 2 . The data input register  34  outputs the data D 2  responsive to the high data input control clock DINCLK. The data input registers  36  and  38  output the data D 1  and D 0 , respectively, responsive to the high data input control clock DINCLK. Conversely, the data input registers  36  and  38  generate the data D 2  and D 1 , respectively, responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers the WE signal. The WE input register  46  respectively outputs the high, low, and high signals W 1 , W 2 , and W 3 . The control signal generating part  52  receives the signals W 1 , W 2 , and W 3 , and generates the control signal C 2  responsive to the high clock signal CLK. The data transmission control part  40  outputs the data D 1  as the signal WD responsive to the control signal C 2 . Therefore, the write operation of the write data D 1  corresponding to the address A 0  is executed. 
     If a write command is input during the sixth cycle, the address input buffer  24  buffers and outputs the address A 5 . The address input registers  26  and  28  respectively output the addresses A 4  and A 2  responsive to the high control signal C 0  to the low control signal C 0 . Conversely, the address input registers  26  and  28 , respectively, output the addresses A 5  and A 4 . The data input register  34  outputs the data D 4  responsive to the low data input control clock DINCLK. The data input registers  36  and  38 , respectively, output the data D 2  and D 1  responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers and outputs the WE signal. The WE input registers  46 ,  48 , and  50  respectively output high signals W 1  and W 2  and low signal W 3 . The control signal generating part  52  receives the signals W 1 , W 2 , and W 3  outputs the data D 2  as the signal WD responsive to the high clock signal CLK. Therefore, the write operation of the write data D 2  corresponding to the address A 2  is executed. 
     If a read command is input during the seventh cycle, the address input buffer  24  buffers the read address A 6  and outputs it to the multiplexer  30 . The address input registers  26  and  28  output the addresses A 5  and A 4  responsive to the low control signal C 0 . The data input buffer  32  buffers the data D 4  and outputs it. The data input registers  34 ,  36 , and  38  output the data D 4 , D 2 , and D 1 , respectively, responsive to the high data input control clock DINCLK. Conversely, the data input registers  34 ,  36 , and  38  output the data D 5 , D 4 , and D 2 , respectively, responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers the RE signal. The WE input registers  46 ,  48 , and  50  output a low W 1  signal and high signals W 2  and W 3 , respectively. Since a read command was input, the control signal generating part  52  does not generate the control signals C 1 , C 2 , and C 3 . The data transmission control part  40  transmits the latched data D 2  as the signal WD. Then, the read operation of the read data pertinent to the read address A 6  is executed. 
     If a read command is input during the eighth cycle, the address input buffer  24  buffers the read address A 7  and provides it to the multiplexer  30 . The address input registers  26  and  28  output the addresses A 5  and A 4  responsive to the low control signal C 0 . The data input buffer  32  buffers and outputs the data D 4 . The data input registers  34 ,  36 , and  38  output the data D 5 , D 4 , and D 2 , respectively, responsive to the high data input control clock DINCLK. The data input registers  36  and  38 , respectively, output the data D 5  and D 4  responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers the RE signal. The WE input registers  46 ,  48 , and  50  output low signals W 1  and W 2  and a high signal W 3 , respectively. Since a read command is input, the control signal generating part  52  does not generate the control signals C 1 , C 2 , and C 3 . The data transmission control part  40  outputs the latched data D 2  as the signal WD. Then, the read operation of the read command pertinent to the read address A 7  is executed. 
     If a write command is input during the ninth cycle, the address input buffer  24  buffers the address A 8  and outputs it. The address input registers  26  and  28  output the address A 5  and A 4 , respectively responsive to the high control signal C 0 . Conversely, the address input registers  26  and  28  output the address A 8  and A 5 , respectively, responsive to the low control signal. The data input registers  36  and  38  output the data D 5  and D 4 , respectively, responsive to the low data input control clock DINCLK. The WE input buffer  44  buffers the WE signal. The WE input registers  46 ,  48 ,  50  output a high signal W 1  and low signals W 2  and W 3 , respectively. The control signal generating part  52  receives the signals W 1 , W 2 , and W 3  and generates the control signal C 3  responsive to the high clock signal CLK. The data transmission control part  40  outputs the data D 4  as the signal WD responsive to the control signal C 3 . Therefore, the write operation of the write data D 4  corresponding to the address A 4  is executed. 
     As shown in the timing diagram of FIG. 6, the write data D 0  is transmitted to the data line pair in the third write cycle, the read data Q 3  is transmitted to the data line pair in the fourth read cycle, the write data D 1  is transmitted to the data line pair in the fifth write cycle, the write data D 2  is transmitted to the data line pair in the sixth write cycle, the read data Q 6  is transmitted to the data line pair in the seventh read cycle, the read data Q 7  is transmitted to the data line pair in the eighth read cycle, and the write data D 4  is transmitted to the data line pair in the ninth write cycle. Therefore, the problem of data collision in data line pairs does not occur if the address and the data are controlled as described above. 
     The semiconductor memory device of the present invention was described with respect to the execution of the write operation after 1 or 2 cycles without a dead cycle. However, if a user wants to configure a dead cycle, he can configure a deselect cycle in the middle of the operation cycle. The deselect cycle operates substantially like a read cycle. 
     Having illustrated and described the principles of my invention in a preferred embodiment thereof, it should be readily apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. I claim all modifications coming within the scope and spirit of the accompanying claims.