Abstract:
The present invention is related to a method for forming a capacitor of a semiconductor device capable of obtaining an excellent electronic property corresponding to a high degree of integration by forming a Ta 3 N 5  thin film having a greater dielectric constant than Ta 2 O 5  and TaON thin films through an atomic layer deposition (ALD). Particularly, the Ta 3 N 5  thin film is a dielectric layer of the capacitor. The inventive method, including the steps of: forming a bottom electrode coupled to an active area of a semiconductor substrate; performing an atomic layer deposition (ALD) technique to form a Ta 3 N 5  dielectric layer with use of a gas precursor of TaCl 5  on the bottom electrode; and forming a top electrode on the Ta 3 N 5  dielectric layer.

Description:
FIELD OF INVENTION  
         [0001]    The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a capacitor of a semiconductor device by providing a Ta 3 N 5  thin film for a dielectric layer with use of an atomic layer deposition (ALD) technique so as to obtain a high level of electronic property of the capacitor corresponding to a higher degree of integration.  
         DESCRIPTION OF RELATED ART  
         [0002]    Integration of a device has been accelerated due to highly developed semiconductor processing skills into microscopic levels. This rapid development of the integration skills results in various researches and studies for reducing a cell area and obtaining a low voltage of an operational voltage. However, despite of this decreased cell areas, a capacitor capacitance for operating a memory device is required greater than 25 fF in order to prevent occurrence of soft error and shortening of a refresh time. Accordingly, a dielectric layer is formed with a NO film, which is stacked with nitride and oxide films, instead of depositing a silicon oxide film. In case of a dynamic random access memory (DRAM) device that uses the NO dielectric film, a storage electrode is formed with a structure of hemi-spherical cylinder as a bottom electrode, and a capacitor height is also increased in order to have a sufficient capacitance.  
           [0003]    However, as the height of the capacitor increases, the height difference between a cell area and a peripheral circuit area becomes larger, resulting in a problem of an insufficient margin for depth of focus (DOF) at a later photo exposure process, and this problem has a negative effect on an integration process after a wiring process. Therefore, even a capacitor that uses the NO dielectric film has a limitation to obtain a sufficient capacity required for a next generation DRAM device greater than 256 mega bites.  
           [0004]    As a result, there has been actively developed a future generation Ta 2 O 5  dielectric film of which dielectric constant ranges from 25 to 30. However, since the Ta 2 O 5  film also has an unstable stoichiometry, there exists a Ta substitutional vacancy atom within the thin film due to a compositional ratio difference in between Ta and O. A TaON thin film formation has been suggested to solve this problem by inducing a surface chemical reaction on a wafer with use of evaporation gases such as NH 3  and Ta(OC 2 H 5 ) 5 . The TaON thin film formed by the above mentioned method becomes much stable compared to Ta 2 O 5  film because of a mutual covalent bond formed as in Ta—O—N with a higher bonding force.  
           [0005]    On the other hand, a chemical vapor deposition (CVD) process is employed to form TaON and Ta 2 O 5  thin films. As illustrated in FIG. 1A, this deposition using CVD, a source gas (S), a purge gas (P) and a reactant gas (R) are injected during one cycle (C 1 ). Then, as referred in FIG. 1B, precursor gases are absorbed on a surface of a substrate, and the absorbed precursor gases generate surface reaction (c) through surfacial diffusions (B) so as to form a film. However, the above procedures result in unstable compositions and structures in stoichiometry. Especially, an organic substance, Ta(OC 2 H 5 ) 5  used for forming the TaON and Ta 2 O 5  thin films, leaves carbon residues, increasing leakage current and deteriorating dielectric breakdown voltage of the dielectric layer.  
           [0006]    Meanwhile, in order to obtain a sufficient capacity of a capacitor required for a device operation, a dielectric layer should have uniform thickness over a whole cell, i.e., effective dielectric film thickness (hereinafter, referred as Teff). However, with the continuous growth method adapted the CVD, it is not easy to get a good step coverage over a deep field of a capacitor that has a three dimensional structure. Also, it becomes much difficult to get the good step coverage when a hemi spherical grain (HSG) is applied. That is, the conventional CVD operation has difficulties in obtaining an electronic property of a capacitor and Teff.  
         SUMMARY OF THE INVENTION  
         [0007]    It is, therefore, an object of the present invention to provide a method for forming a capacitor of a semiconductor device by providing a Ta 3 N 5  thin film with the atomic layer deposition (ALD) technique so as to obtain a high level of electronic property of the capacitor corresponding to a high degree of integration of the capacitor.  
           [0008]    In accordance with one aspect of the present invention, there is provided a method for fabricating a capacitor of a semiconductor device, including the steps of: forming a bottom electrode coupled to an active area of a semiconductor substrate; performing an atomic layer deposition (ALD) technique to form a Ta 3 N 5  dielectric layer with use of a gas precursor of TaCl 5  on the bottom electrode; and forming a top electrode on the Ta 3 N 5  dielectric layer.  
           [0009]    Also, a nitridation process is performed between the bottom electrode formation step and the Ta 3 N 5  dielectric layer formation step to form a nitride layer on top portion of the bottom electrode. The nitration layer is formed to a thickness ranging from about 5 Å to 30 Å. In this case, the nitridation layer is operated with an in-situ or ex-situ process, including a plasma process, a rapid thermal process or a furnace process.  
           [0010]    During the Ta 3 N 5  dielectric layer formation, inert gase such as Ar or N 2  is used as a purge gas while NH 3  and TaCl 5  are used as a reactant gas and as a precursor gas, respectively. Also, a flow quantity of the reactant gas is controlled within a range from about 10 sccm to about 500 sccm. Ideally, a growth rate of the Ta 3 N 5  dielectric layer is maintained within a range from about 0.1 Å to about 0.5 Å per cycle so for the Ta 3 N 5  dielectric layer to have a thickness of approximately 150 Å.  
           [0011]    In addition, the Ta 3 N 5  dielectric layer is proceeded with oxidation process between the Ta 3 N 5  dielectric layer formation step and the top electrode formation step. The oxidation process is performed with either a light wet oxidation or an in-situ or ex-situ process that utilizes a plasma process, a rapid thermal process or a furnace process.  
           [0012]    The top electrode having a thickness ranging from about 100 Å to about 600 Å is formed with any of one film selected from TaN, TiN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2  and Pt.  
           [0013]    Lastly, an in-situ or ex-situ process is executed with use of HF vapor or HF solution for a surface treatment so that a native oxide, which is a residue remained on a surface of the bottom electrode, is removed prior to the dielectric layer formation. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING(s)  
       [0014]    The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0015]    [0015]FIG. 1A is a schematic diagram illustrating a deposition mechanism of chemical vapor deposition (CVD);  
         [0016]    [0016]FIG. 1B is a schematic diagram illustrating a deposition mechanism of CVD;  
         [0017]    [0017]FIG. 2A is a schematic diagram illustrating a deposition mechanism of atomic layer deposition (ALD);  
         [0018]    [0018]FIG. 2B is a schematic diagram illustrating a deposition mechanism of ALD;  
         [0019]    [0019]FIGS. 3A to  3 C are cross-sectional views showing a process for forming a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention; and  
         [0020]    [0020]FIG. 4 is a cross-sectional view of a capacitor in a semiconductor device in accordance with another preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]    Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, which is set forth hereinafter.  
         [0022]    Referring to FIGS. 2A and 2B, there briefly described a mechanism of ALD for forming a Ta 3 N 5  thin film in accordance with the present invention.  
         [0023]    As shown in FIG. 2A, unlike to a chemical vapor deposition (CVD) process, in an ALD process a source gas (S), a purge gas (P) and a reactant gas (R) are alternately injected in that order during one cycle (C 1 ). Thus, as illustrated in FIG. 2B, precursor gases required for a formation of a desired thin film are injected alternately in an orderly manner to a surface of a substrate  10 . That is, at step (A), a precursor of the source gas  20  is injected in a saturation state to the surface of the substrate so to perform a chemical reaction and to deposit an atomic layer on the substrate. At step (B), the purge gas (P) removes residues of the source gas (S), and then, the reactant gas (R) react with the atomic layer in a saturation state to form a monolayer. With repeats of the above cycle at step (C) and (D), it is possible to form layers as with desired thicknesses, thereby easily varying the thickness. Also, since each gas reacts in a saturation state, the thin film formed by the ALD possesses superior uniformity in thickness and homogeneity, resulting in excellent step coverage even in three dimensions. Therefore, Teff is easily attainable for a high degree of electron property of a capacitor. Also, since residues such as carbon and so on are not formed, increases of leakage current and dielectric breakdown voltage can be prevented.  
         [0024]    Next, referring FIGS. 3A to  3 C, a method for forming a capacitor of a semiconductor device will be explained in accordance with a preferred embodiment of the present invention wherein an ALD process is applied.  
         [0025]    With reference to FIG. 3A, an inter-layer insulating layer  31  is formed on a semiconductor substrate  30  made up of materials such as silicon, and then a contact hole for connecting a capacitor to the substrate  30  is formed by etching the inter-layer insulating layer  31  to expose an active area (not shown in the diagram) of the substrate  30 . After this formation of the contact hole, a polysilicon layer is deposited by employing a low pressure chemical vapor deposition (LPCVD) and patterned to form a bottom electrode  32  of the capacitor. Here, the bottom electrode can be formed as one of stack, cylinder, fin, or stack cylinder forms, and in this embodiment, it is assumed that the bottom electrode is formed in the stack form. After this bottom electrode formation, in order to remove a native oxide residing on a surface of the bottom electrode  32 , a surface treatment of the bottom electrode  32  is performed by using HF vapor or HF solution with an in-situ or ex-situ operation. At this time, an interfacial treatment is carried out with use of chemical solutions of NH 4 OH or H 2 SO 4  to wash an interface or to improve uniformity before/after the surface treatment using HF.  
         [0026]    Referring to FIG. 3B, in order to prevent a formation of a low dielectric oxide layer, SiO 2 , on the interface between the polysilicon layer of the bottom electrode  32  and a Ta 3 N 5  dielectric layer during a deposition process and a subsequent thermal process for the Ta 3 N 5  dielectric layer, nitridation process is performed to form a nitride layer  33  such as Si 3 N 4  with a thickness ranging from about 5 Å to about 30 Å on a top surface of the bottom electrode  32 . In this case, the nitridation process utilizes a plasma process including an in-situ or ex-situ operation, a rapid thermal process (RTP) or a furnace process. In case of the plasma process, the nitrification process is performed at a temperature ranging from about 300° C. to about 600° C. for about 30 seconds in a NH 3  or a N 2 /H 2  gas ambient. When using the RTP, the nitridation process is performed at a temperature ranging from about 650° C. to about 950° C. with a NH 3  ambient. Also, in case of using the furnace process, the process is performed at a temperature ranging from about 500° C. to about 1000° C. with a NH 3  ambient.  
         [0027]    As a next step, a dielectric layer  34  of the Ta 3 N 5  thin film is formed to a thickness of approximately 150 Å by using TaCl 5  gas on the nitride layer  33 . Referring to FIGS. 2A and 2B, there described in detail the formation of the dielectric layer  34  with the Ta 3 N 5  thin film. Tacl 5  gas precursor, which is a source gas (S), is injected in a saturation state to a surface of the substrate during a first cycle (C 1 ) to deposit chemically a Ta atomic layer at step (A). With use of Ar or N 2  as a purge gas (P), a residue of the source gas (S) is removed at step (B), and then, NH 3  as a reactant gas (R) in a saturation state and is reacted with Ta in the Ta atomic layer so as to form a single layer of the Ta 3 N 5  thin film. The chemical reaction for the above is expected to be the reaction 1 as below.  
         [0028]    &lt;Reaction 1&gt; 
         3TaCl 5 (g)+5NH 3 (g)→Ta 3 N 5 (s)+15HCl(g)  
         [0029]    In this reaction, chemical vapor composed of Ta is provided with greater than 99.999% of TaCl 5  gas precursors with a constant quantity by using a flow controller such as mass flow controller (MFC) via evaporator retained to a temperature above 90° C. At this time, the evaporator including orifice, nozzle and solenoid valves as well as a supplier for a flow path of Ta vapor maintain a temperature to be in a range from about 90° C. to about 200° C. in order to prevent condensation of the Ta vapor. Through this method, a Ta 3 N 5  thin film can be obtained with a thickness as desired by repeatedly depositing the chemically evaporated Ta and NH 3  gas precursors in a unit of atomic layer. In this case, the Ta is chemically evaporated and the NH 3  gas precursors are supplied to a chamber of which temperature is maintained between about 200° C. to about 500° C. in order to perform repetitive depositions. Also, at this time, TaCl 5  gas precursors and NH 3  reactant gas, of which flows are regulated in a surfacial saturation state within a range from about 10 sccm to about 500 sccm, are provided with a fixed quantity. Deposition rate, that is, growth rate of the Ta 3 N 5  thin film is maintained within a range from about 0.1 Å to about 0.5 Å per cycle, and residue gases remained after the surface reaction of the Ta 3 N 5  thin film are removed by a purge gas such as Ar, N 2 , and other inert gases. As a result, there does not occur a gas phase reaction via reactant gas NH 3 .  
         [0030]    After forming the Ta 3 N 5  dielectric layer  34  as described above, a predetermined number of oxidation processes are performed to improve a dielectric constant by correcting and crystallizing structural defects of the dielectric layer  34  such as micro crack or pin hole and non-uniformity. In this case, the oxidation process is operated with use of an in-situ or ex-situ operation, including a plasma process, a RTP or a furnace process. Ideally, in case of using the plasma process, temperature is maintained within a range from about 300° C. to about 600° C. in an ambient of N 2 O or O 2 , and in case of using the RTP, temperature is sustained in between about 600° C. and about 950° C. with an ambient of N 2 O, O 2  or N 2  for about 30 seconds to about 10 minutes. In case of performing the furnace process, temperature is maintained within a range from about 600° C. to about 950° C. in an ambient of N 2 O, O 2  or N 2  for about one minute to about 120 minutes. Also, the oxidation process can be alternatively performed as a light wet oxidation by fixing a quantity of a flow rate of O 2 /H 2  gas less than about 3 in an ambient of O 2  and H 2  with the in-situ or ex-situ process.  
         [0031]    As referred in FIG. 3 c,  a top electrode  35  is formed to completely fabricate a high capacity capacitor. Ideally, the top electrode  35  is formed with a thickness of about 100 Å to about 600 Å in a single layer selected from TaN, TiN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2  and Pt. Then, during a subsequent thermal process, a doped polysilicon layer is formed on a whole surface of a substrate. Herein, the doped polysilicon layer enacts as a buffer layer  36  in order to prevent degradation of the capacitor.  
         [0032]    [0032]FIG. 4 is a cross-sectional view showing a capacitor of a semiconductor device having a Ta 3 N 5  thin film fabricated in accordance with another embodiment of the present embodiment. In this embodiment, a bottom electrode  32 A is formed with a structure of hemispherical convexo-concave. A Ta 3 N 5  dielectric layer  34  is formed on top of the bottom electrode  32 A through the identical procedures as described in the above embodiment.  
         [0033]    According to the present invention, it is possible to augment a capacitor capacity in a higher degree by forming a Ta 3 N 5  thin film with a high dielectric constant greater than 100 for a dielectric layer of the capacitor. Also, since the Ta 3 N 5  thin film is formed with an ALD method, it is possible to prevent carbon radicals from remaining and to obtain excellent step coverage. Therefore, the leakage current via dielectric layer and the degradation of dielectric breakdown voltage characteristic can be prevented, and the effective thickness of the dielectric layer can be easily secured.  
         [0034]    While the present invention has been shown and described with respect to the particular embodiments, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the sprit and scope of the invention as defined in the appended claims.