Abstract:
A semiconductor integrated circuit and method of use improve a rate of defect detection and also facilitate production of test patterns while suppressing an increase of the circuit area. The semiconductor integrated circuit includes a plurality of pairs of a sequence circuit and selector circuit. Each of the sequence circuits stores an operation result of an internal circuit, whereas each selector circuit is responsive to a control signal for selecting one of the data stored in its associated sequence circuit and an inverted version of the data to thereby output the selected data. A control circuit operates to count up or divide clocks and then control the selector circuits constituting the plurality of pairs in accordance with the resultant count values.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to semiconductor integrated circuit devices including sequence circuits such as flip-flops and/or latches as well as testing method for use therewith. More particularly, the invention relates to a semiconductor integrated circuit capable of changing or varying the state of a circuit block of less controllability along with a test method therefor. 
     2. Description of the Prior Art 
     Conventionally, the so-called “scan-pass” test method has been well known as one of test facilitation schemes for semiconductor integrated circuits. 
     This scan-pass test method is for achieving facilitation of test procedures of semiconductor integrated circuits by replacing part or the whole of flip-flops which are sequence circuits in a semiconductor integrated circuit with a scannable flip-flop to provide a shift-register configuration while treating the remaining portions other than such one or more shift registers as a combination circuit thereby controlling the shift registers. 
     More than one latch may be also present in the sequence circuit other than the flip-flops. In cases where this semiconductor integrated circuit including a plurality of latches is tested by the scan-pass test method, two typical approaches have been known as will be described below. 
     The first approach is to perform the intended scan-pass test procedures by rendering the latch&#39;s enable signal active to let the latches operate with their operation mode being fixed in a “through” mode. This approach is to make latches combination circuits. The second approach is such that it is based on implementation of latches with a flop-flop configuration, wherein another latch is provided at the succeeding or post stage of a latch while regarding the pre-stage one as a “master” latch and also regarding its post stage as a “slave” latch operable as a flip-flop, whereby such flip-flop is accommodated into a shift register to thereby perform the scan-pass test. 
     In addition, with the scan-pass test method, when setting data into the shift register configuration, since this data setting is carried out through a shifting operation synchronized with a single clock, it is required that remedy against clock skew be employed in a way such that a buffer which reserves gain for a hold time period is inserted between neighboring flip-flops; or alternatively, for a non-synchronous circuit block in the circuitry, the circuit configuration is modified causing it to perform a synchronized operation with such clock during test operations. 
     However, in the prior known scan-pass test method, detection of defects near or around latches can become deficient due to the fact that the latches must be operatively fixed in the “through” mode according to the scheme of making latch to combination circuit. Furthermore, a feedback loop containing therein a latch or latches will possibly be formed in some cases, which would result in deficiency of defect detectivity also; accordingly, it has been difficult to obtain high defect detectability. On the other hand, with the latch-to-flip/flop function-change or “transmutation” scheme, an extra latch must be added per latch so that it suffers from a problem in that the area overhead can increase in circuitry which employs therein multiple latches. 
     In addition, concerning the scan-pass test method, the technique for inserting the buffer in order to attain the remedy against clock-skew stated supra is associated with a problem: when inserting buffers among all the flip-flops, the resulting area overhead increases; on the other hand, if such buffers are selectively inserted then the static analysis of circuitry should be required. 
     Another problem encountered with the prior art approaches is that with the aforementioned scheme for letting the non-synchronous circuit block operate as a synchronization circuit in the scan-pass test method, if a great number of non-synchronous circuit blocks are contained then the circuitry&#39;s area overhead can increase, which results in an extra delay taking place in a clock system thereby causing generation of extra process steps during design procedures in order to successfully meet the circuit specifications required. 
     Additionally in the recent years, semiconductor integrated circuits employing CMOS technology are the major devices in the art to which the invention pertains. In such semiconductor integrated circuits, small power supply current flows when circuitry is of no abnormality; it can thus be seen that the circuitry must contain certain abnormalities in cases power supply current greater in magnitude than or equal to a predefined level rushes to flow therein. In view of this fact, as one of the procedures for determining whether a semiconductor integrated circuit under inspection is acceptable or rejectable in quality, a test method may be effective which includes the steps of applying a test pattern for use in evaluation of the to-be-tested circuit of such semiconductor integrated circuit while at the same time monitoring the power supply current of the semiconductor integrated circuit. However, in order to increase the defect detectability of semiconductor integrated circuits, creation of a specific test pattern is required for use in sufficiently controlling the state or condition (whether in the ON state or in the OFF state) of elements which constitute the circuit being tested. In recent years, there is a problem which follows: as semiconductor integrated circuits increase both in functionality and in integration density, preparation of such test pattern becomes more difficult. 
     SUMMARY OF THE INVENTION 
     The present invention has been made by taking into consideration the technical background stated above, and its primary object is to provide a semiconductor integrated circuit capable of achieving high defect detectability and also facilitating the productivity of test patterns while reducing or minimizing the circuit area and also provide a testing method for use therewith. 
     To attain the foregoing object the instant invention provides a semiconductor integrated circuit which is featured by including a plurality of pairs of sequence circuit and selector circuit and further including a control circuit, wherein each of the sequence circuits is operable to store therein an operation result of internal circuitry of the semiconductor integrated circuit whereas each selector circuit is responsive to a control signal for selecting one of the data being stored in its associated sequence circuit and an inverted version of the data, and wherein the control circuit is responsible for controlling the selector circuits that constitute the plurality of pairs by counting up clocks or successively dividing the clocks to thereby provide a clock count value for use in controlling the selector circuits. 
     In prior known semiconductor integrated circuits, although the scan-pass testing method has been employed as one of the test facilitation schemes, the prior art is faced with the risk of an increase in area of circuitry for use in execution of the test procedures and an inability to obtain high defect detectability. On the contrary, with the semiconductor integrated circuit in accordance with the present invention, it becomes possible to permit flexible inputting of a test pattern comprised of the data and inverted data to a circuit being tested. This can be said because the semiconductor integrated circuit is specifically designed for the test to make use of a sequence circuit equipped therein for use during a standard operation thereby enabling selective outputting to the to-be-tested circuit one of the data being stored in the sequence circuit and an inverted version of such data. With such an arrangement, it is possible to well control the state of elements constituting such to-be-tested circuit while simultaneously suppressing or minimizing an increase in area of circuitry for testing. This in turn makes it possible to increase the defect detectability of the semiconductor integrated circuit to thereby render easier creation or preparation of the intended test patterns. 
     In accordance with another aspect of the invention to attain the above objective, a testing method is provided for use with a semiconductor integrated circuit including a plurality of pairs of sequence circuit and selector circuit and also including a control circuit, wherein each of the sequence circuits stores therein an operation result of internal circuitry of the semiconductor integrated circuit, whereas each selector circuit is operatively responsive to a control signal for selecting one of the data stored in its associated sequence circuit and an inverted version of the data, and wherein the control circuit controls the selector circuits that constitute the plurality of pairs by counting up clocks or sequentially dividing the same to thereby provide the resultant clock count value for use in controlling the selector circuits, the method being featured by letting the semiconductor integrated circuit perform an operation containing a selector circuit controlling operation by the control circuit. A further feature is that the method includes the steps of monitoring a power supply current of the semiconductor integrated circuit while performing the above-mentioned operation. 
     According to the semiconductor integrated circuit test method of the invention, it becomes possible to allow the defect detectability to increase while making easier the creation of test patterns required. This can be said because the use of the aforesaid method may enable those elements constituting the to-be-tested circuit to be well controlled in state. 
     These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing a pictorial representation of a semiconductor integrated circuit in accordance with the present invention. 
     FIG. 2 is a diagram showing one exemplary timing chart for explanation of an operation of the semiconductor integrated circuit shown in FIG.  1 . 
     FIG. 3 is a diagram showing one exemplary configuration of a unit test circuit shown in FIG.  1 . 
     FIG. 4 is a diagram illustrating another exemplary configuration of the unit test circuit shown in FIG.  1 . 
     FIG. 5 illustrates one example of a detailed configuration of a unit test circuit which consists essentially of a pair of a flip-flop and a selector shown in FIG.  1 . 
     FIG. 6 shows one example of a detailed configuration of a unit test circuit consisting essentially of a pair of a latch and a selector shown in FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Some preferred embodiments of the present invention will be explained with reference to the accompanying drawings. 
     FIG. 1 is a diagram showing the principles of this invention. 
     A semiconductor integrated circuit  100  shown in FIG. 1 is arranged to operate in two different modes: a standard operation mode for execution of an ordinary or standard operation, and a test mode for test/inspection procedures. This semiconductor integrated circuit  100  is provided with random logical circuits  60 ,  70  each of which comprises a combination circuitry. In addition, there are provided between these random logic circuits  60 ,  70  a unit test circuit  10  consisting essentially of a pair of a flip-flop circuit  11  and a selector circuit  12 , a unit test circuit  20  including a pair of a flip-flop  21  and a selector  22 , a unit test circuit  30  including a pair of a flip-flop  31  and selector  32 , and a unit test circuit  40  including a pair of a latch  41  and selector  42 . In the illustrative embodiment, only four unit test circuits  10 - 40  are employed only for purposes of convenience in illustration and discussion herein, but any given number of such circuits may be employable on a case-by-case basis. Moreover in this semiconductor integrated circuit  100 , a control circuit  50  is also provided. 
     In FIG. 1, while the random logic circuit  60  comes with its input nodes or terminals I 1 -Im (where “m” is an integer) for receipt of input signals externally supplied thereto, this is for purposes of facilitation of explanation only, and another random logic circuit and a plurality of unit test circuits may optionally be inserted between the input terminals I 1 -Im and the random logic circuit  60 . Still alternatively, although the illustrative random logic circuit  70  is equipped with output terminals O 1 -On (“n” is an integer) for use in outputting a signal or signals toward external circuitry operatively associated therewith, another random logic circuit and plural unit test circuits may also be inserted between the random logic circuit  70  and the output terminals O 1 -On. 
     The random logic circuit  60  generates data signals D 1 , D 2 , D 3  and clock signals CLK which are input to respective flip-flops  11 ,  21 ,  31 . The logic circuit  60  also generates a data signal D 4  and a latch enable signal LE which are then input to the latch  41 . Here, the clocks CLK may be input externally, or alternatively may be generated internally. 
     The data D 1 , D 2 , D 3  are taken into the flip-flops  11 ,  21 ,  31  in a way synchronized to the clocks CLK whereby data signals Q 1 , Q 2 , Q 3  are output from the flip-flops  11 ,  21 ,  31  along with a logically inverted version of the individual one of such data—i.e. inverted data signals Q 1 N, Q 2 N, Q 3 N. The data Q 1 , Q 2 , Q 3  are then input to respective input terminals “0” of the selectors  12 ,  22 ,  32 , while the inverted data Q 1 N, Q 2 N, Q 3 N are input to respective input terminals “1” of selectors  12 ,  22 ,  32 . On the other hand, the latch  41  is set in a “through” mode in response to the latch enable signal LE having a High or H level, thereby allowing the latch  41  to output the data Q 4  and its inverted data Q 4 N. These data Q 4 , Q 4 N are in turn input to the input terminals “0” and “1” of the selector  42 . 
     An explanation will be given with reference to FIG.  1  and FIG. 2 below. 
     FIG. 2 is one example of a timing chart for explanation of an operation of the semiconductor integrated circuit shown in FIG.  1 . In this timing chart of FIG. 2, the control circuit  50  of FIG. 1 makes use of a divider circuit which is operable to successively divide a test clock signal TCLK to thereby output a 2-frequency-divided signal S 1  and 4-frequency-divided signal S 2 . However, this is also for purposes of convenience in explanation only, and any circuitry capable of generating output signals at any given numbers may be employed alternatively, which signals may be generated preferably by use of more than one counter and/or frequency-divider. 
     First of all, the standard operation mode of the semiconductor integrated circuit  100  will be explained below. 
     In the standard operation mode a test reset signal TRST having a Low or L level as shown in FIG. 2 is input to the control circuit  50 . Then, the control circuit  50  is set in the disenable state causing control signals S 1 , S 2  both at L level to be output from the control circuit  50 , which signals are then input to respective control terminals of the selectors  12 ,  22 ,  32 ,  42 . Substantially simultaneously, the data signals D 1 , D 2 , D 3 , D 4  originated from a standard operation are output from the random logic circuit  60 ; the data D 1 , D 2 , D 3  of these signals are taken into the flip-flops  11 ,  21 ,  31  at a timing synchronized to the clock CLK; and, in responding to receipt of the latch enable signal LE of H level, the data D 4  passes through such latch  41  whereby data Q 1 , Q 2 , Q 3 , Q 4  are input to respective input terminals “0” of respective selectors whereas the inverted data Q 1 N, Q 2 N, Q 3 N, Q 4 N are input to respective input terminals “1”. 
     Since the control signals S 1 , S 2  both of which are at L level are being input from the control circuit  50  to the control terminals of the selectors  12 ,  22 ,  32 ,  42 , the data Q 1 , Q 2 , Q 3 , Q 4  which have been input to respective input terminals “0” are selectively output from these selectors to the random logical circuit  70 . In this way the standard operation of the semiconductor integrated circuit  100  is carried out. 
     An explanation will next be given of the test mode of the semiconductor integrated circuit  100  hereafter. 
     In the test mode the test reset signal TRST having the H level as shown in FIG. 2 is input to the control circuit  50 . Also, a test pattern is input to the random logic circuit  60  via the input terminals I 1 -Im of the semiconductor integrated circuit  100  in a way synchronous with the test clock TCLK. Simultaneously, power supply current of the semiconductor integrated circuit  100  is monitored. 
     In a time period T 0  spanning from a time point at which the test reset signal TRST of H level has been input up to an instant whereat an initial test clock TCLK is input, the control signals S 1 , S 2  both having L level are being output from the control circuit  50 ; thus, at the selectors  12 ,  22 ,  32 ,  42 , the data Q 1 , Q 2 , Q 3 , Q 4  which are continuously being input to the input terminals “0” are being selected and output. 
     Here, a first test clock TCLK is input to the control circuit  50 . The time period T 0  shown in FIG. 2 is shifted to a period T 1 . Also, the data D 1 , D 2 , D 3 , D 4  responsive to a presently available test pattern are output from the random logic circuit  60 ; specified ones of these data D 1 , D 2 , D 3 , D 4 —here, data D 1 , D 2 , D 3 —are accommodated into the flip-flops  11 ,  21 ,  31  in response to the clock CLK. The remaining data D 4  passes through the latch  41  in reply to the latch enable signal LE of H level whereby data Q 1 , Q 2 , Q 3 , Q 4  are input to respective input terminals “0” of the selectors  12 ,  22 ,  32 ,  42  while causing the inverted data Q 1 N, Q 2 N, Q 3 N, Q 4 N to be input to respective input terminals “1”. Because the first test clock TCLK is input to the control circuit  50 , the control signal of L level being output from the control circuit  50  is changed in potential to have H level. This control signal S 1  of H level is then input to the control terminals of the selectors  12 ,  22  whereby at the selectors  12 ,  22  the inverted data Q 1 N, Q 2 N being presently input to respective input terminals “1” thereof are selectively output and then input to the random logic circuit  70 . On the other hand, at the selectors  32 ,  42 , the data Q 3 , Q 4  being input to respective input terminals “0” thereof are directly selected and output, and are then input to the random logic circuit  70 . At the random logic circuit  70 , test is carried out based on these inverted data Q 1 N, Q 2 N and data Q 3 , Q 4  within the period T 1 . 
     Next, a second test clock TCLK is input to the control circuit  50 . Then, the control signal S 1  of H level being output from the control circuit  50  is potentially changed to L level while at the same time letting the control signal S 2  of L level change to H level. Simultaneously, the period T 1  is shifted to a time period T 2 . Since the control signal S 1  of L level is being input to the selectors  12 ,  22 , the data Q 1 , Q 2  being input to their respective input terminals “0” are selected for output at these selectors  12 ,  22 , and are then input to the random logic circuit  70 . On the other hand, the control signal S 2  of H level is input to the selectors  32 ,  42 ; thus, at the selectors  32 ,  42 , the inverted data Q 3 N, Q 4 N being input to respective input terminals are input to the random logic circuit  70 . At the random logic circuit  70  a test is performed on the basis of these data Q 1 , Q 2  and inverted data Q 3 N, Q 4 N in the period T 2 . 
     Thereafter, a third clock TCLK is input to the control circuit  50 . Then, the control signal S 1  of L level being output from the control circuit  50  is changed at H level whereas the control signal S 2  of H level is forced to maintain its present potential level. The period T 2  shown in FIG. 2 is shifted to a time period T 3 . The control signal S 1  of H level is input to the selectors  12 ,  22 ; accordingly, at these selectors  12 ,  22 , the inverted data Q 1 N, Q 2 N being input to respective input terminals “1” thereof are selectively output and are then input to the random logic circuit  70 . On the other hand, the control signal S 2  of H level is being directly input to the selectors  32 ,  42 ; thus, at these selectors  32 ,  42 , the inverted data Q 3 N, Q 4 N that are presently input to respective input terminals “1” are directly selected and output and are then input to the random logic circuit  70 . At the random logic circuit  70  a test is done based on these inverted data Q 1 N, Q 2 N, Q 3 N, Q 4 N within the period T 3 . 
     Next, a fourth test clock TCLK is input to the control circuit  50 . Then, the control signals S 1 , S 2  both of which are at H level and which are presently output from the control circuit  50  are simultaneously changed in potential to L level. Due to this, at the selectors  12 ,  22 ,  32 ,  42 , the data Q 1 , Q 2 , Q 3 , Q 4  being input to respective input terminals “0” are selected for output and are then input to the random logic circuit  70 . At the random logic circuit  70  a test is performed based on these data Q 1 , Q 2 , Q 3 , Q 4  in the period T 4 . In this way, with the semiconductor integrated circuit  100  embodying the invention, it becomes possible to suppress or minimize any possible increase in area of testing circuitry. This can be said because the unit test circuits  10 ,  20 ,  30 ,  40  are configured by using the flip-flops  11 ,  21 ,  31  and the latch  41  provided in the semiconductor integrated circuit  100  to be adapted for use during standard operations while the selectors  12 ,  22 ,  32 ,  42  are used to selectively output the data Q 1 , Q 2 , Q 3 , Q 4  and inverted data Q 1 N, Q 2 N, Q 3 N, Q 4 N as output from these flip-flops  11 ,  21 ,  31  and latch  41  and then outputting to the random logic circuit  70  at the post stage thereof. It is also possible to sufficiently control the state of those elements constituting the random logic circuit  70  due to the fact that a variety of kinds of test patterns that are available by combination of the data Q 1 , Q 2 , Q 3 , Q 4  with the inverted data Q 1 N, Q 2 N, Q 3 N, Q 4 N are to be input to the random logic circuit  70 . Consequently, the defect detectability factor of the semiconductor integrated circuit  100  may increase while at the same time facilitating creation of test patterns required. 
     FIG. 3 is a diagram showing an exemplary configuration of an actually implemented example of one of the unit test circuits shown in FIG.  1 . 
     A unit test circuit  80  includes a pair of a flip-flop circuit  81  and two-input Exclusive-OR gate  82 . Data D and a clock CLK are input to the flip-flop  81 . The data D as input to the flip-flop  81  is then fetched in a way synchronous with the clock CLK so that data Q is output. The output data Q is input to one input node of the 2-input Exclusive-OR gate  82 . A control signal S is input to the remaining input node of the Exclusive-OR gate  82 . When the control signal S of L level, the data Q is directly output from such Exclusive-OR gate  82  without any level conversion effected thereto. On the other hand, when the control signal S of H level is input, an inverted data QN is output from the 2-input Exclusive-OR gate  82 . As stated above, since the unit test circuit  80  is configured from the flip-flop  81  for use during standard operations and simple 2-input Exclusive-OR gate  82 , it becomes possible to decrease the scale of circuitry as required for execution of test procedures. 
     FIG. 4 is a diagram showing a configuration of another actually implemented example of one of the unit test circuits shown in FIG.  1 . 
     The unit test circuit  90  shown in FIG. 4 includes a pair of a latch  91  for use during standard operations and a two-input Exclusive-OR gate  92 . Data D and latch enable signal LE are input to the latch  91 . The data D being input to the latch  91  passes through it in a way synchronous with the latch enable signal LE of H level whereby data Q is output. The output data Q is input to one input of the Exclusive-OR gate  92 . A control signal S is input to the other input of the Exclusive-OR gate  92 . When a control signal S of L level is input as the control signal S, the data Q is directly output from the Exclusive-OR gate  92  with no signal processing applied thereto. On the other hand, when a control signal S of H level is input, an inverted data QN is output from the Exclusive-OR gate  92 . As stated previously, since the unit test circuit  90  is made up of the latch  91  used during standard operations and simple Exclusive-OR gate  92 , it is likewise possible to decrease the scale of circuitry required for execution of test procedures. 
     FIG. 5 is one example of a detailed circuit diagram of the unit test circuit configured including a pair of flip-flop and selector shown in FIG.  1 . 
     In FIG. 5, a circuit configuration of the unit test circuit  10  is shown. An operation of the flip-flop  11  will first be explained below. 
     The flip-flop  11  is provided with clocked inverters  11   a,    11   b  and an inverter  11   c  which may constitute a “master” latch, along with clocked inverters  11   d,    11   e  and an inverter  11   f  constituting a “slave” latch, as well as inverters  11   g,    11   h  that constitute a clock circuit. Data D 1  and clock CLK are input to such flip-flop  11 . At the flip-flop  11 , while its input clock CLK is at L level, a reverse or negative-phase clock CN of H level and positive-phase clock signal CB of L level are input to respective clocked inverters  11   a,    11   b,    11   d,    11   e.  Due to this, the clocked inverters  11   a,    11   e  are set in the ON state whereas the clocked inverters  11   b,    11   d  are in the OFF state. Accordingly, the data D 1  as input to the flip-flop  11  is inverted in polarity at the inverter  11   c  via the clocked inverter  11   a,  and is then input to the slave latch. At the slave latch, since the clocked inverters  11   d,    11   e  are in the OFF state and ON state respectively, data presently being stored in the slave latch is output as the data Q 1  and inverted data Q 1 N of the flip-flop  11  irrespective of the data D 1  being input to the flip-flop  11 . 
     Next, the clock CLK changes in potential from L level to H level. Then, L level is output as the negative-phase clock CN; further, H level is output as the positive-phase clock CB. These negative-phase clock CN of L level and positive-phase clock CB of H level are input to respective clocked inverters. Thus, the clocked inverters  11   a,    11   e  are set in the OFF state, while the clocked inverters  11   b,    11   d  are in the ON state. Then, the data D 1  being input to the master latch is latched at such master latch. The data D 1  latched in the master latch is input to the slave latch. Here, since the clocked inverters  11   d,    11   e  of the slave latch are in the ON state and OFF state respectively, the data D 1  being input to the slave latch is output as the inverted data Q 1 N through the clocked inverter  11   d,  and further inverted by the inverter  11   f  to be output as the data Q. In other words the data D 1  input to the flip-flop  11  is output from the flip-flop  11  as the data Q 1  and inverted data Q 1 N toward the selector  12  at a timing synchronized to the rising edge of a clock CLK. 
     Next, the selector  12  will be explained. 
     The selector  12  is configured including clocked inverters  12   a,    12   b  and inverters  12   c,    12   d,    12   e.  Data Q 1  and its inverted data Q 1 N are input to the clocked inverters  12   a,    12   b  whereas a control signal S 1  is input to the inverter  12   d.  Upon inputting of L level as the control signal S 1 , H level is output from the inverter  12   d  as a negative-phase control signal S 1 N; further, L level is output from the inverter  12   e  as a positive-phase control signal S 1 B. These signals are then input to the clocked inverters  12   a,    12   b.  Thus, the clocked inverters  12   a,    12   b  are set in the ON state and OFF state respectively, thereby allowing data Q 1  to be output via the clocked inverters  12   a,    12   c.    
     On the other hand, when H level is input as the control signal S 1 , L level is output as the negative-phase control signal S 1 N while H level is output as the positive-phase control signal S 1 B at this time. Thus, the clocked inverters  12   a,    12   b  are in the OFF state and ON state respectively letting the inverted data Q 1 N be output via the clocked inverter  12   b  and inverter  12   c.  As stated above, since the unit test circuit  10  is configured from the flip-flop  11  for use during standard operations and the selector  12  that is simple in configuration, it is possible to reduce the area of circuitry required for testing. Note that regarding the unit test circuits  20 ,  30  also, the same circuit configuration is employable as that of the unit test circuit  10 . Also note that although in the above description one detailed example has been explained in regard to the D-type flip-flop, similar circuitry may be considered with respect to flip-flops of other types (e.g. JK type, RS type, and the like). 
     FIG. 6 is one exemplary detailed circuit diagram of the unit test circuit  40  that consists essentially of a pair of the latch  41  and selector  42  shown in FIG.  1 . 
     The latch  41  is configured from clocked inverters  41   a,    41   b  and inverters  41   c,    41   d,    41   e,  while the selector  42  is from clocked inverters  42   a,    42   b  and inverters  42   c,    42   d,    42   e.  Data D 4  and latch enable signal LE are input to the latch  41 . At the latch  41 , when the latch enable signal LE is at L level, H level is being output as a negative-phase latch enable signal LEN, and L level is output as a positive-phase latch enable signal LEB, wherein the clocked inverters  41   a,    41   b  are in the ON state and OFF state, respectively. Accordingly, any data that is presently stored in the latch  41  is being output as the latch  41 &#39;s data Q 4  and inverted data Q 4 N without regard to the state of the data D 4  being input to the latch  41 . 
     Here, when the latch enable signal LE changes in potential at H level, the clocked inverters  41   a,    41   b  are in the On state and OFF state thereby allowing data D 4  to be output as the inverted data Q 4 N via the clocked inverter  41   a  and further be output as data Q 4  via the inverter  41   c.  In other words, the data D 4  as input to the latch  41  passes through it in a way synchronous with the latch enable signal LE of H level, and is then output from the latch  41  as the data Q 4  and inverted data Q 4 N. These data Q 4  and inverted data Q 4 N are input to the clocked inverters  42   a,    42   b  which constitute the selector  42 . At the selector  42 , when L level is input as a control signal S 2 , H level is output as a negative-phase control signal S 2 N whereas L level is output as a positive-phase control signal S 2 B. This allows the clocked inverters  42   a,    42   b  to be in the ON state and OFF state respectively to thereby let the data Q 4  be output via the clocked inverter  42   a  and inverter  42   c.    
     On the other hand, upon inputting of H level as the control signal S 2 , L level is output as the negative-phase control signal S 2 N while H level is output as the positive-phase control signal S 2 B in this case. Thus, the clocked inverters  42   a,    42   b  are set in the OFF state and ON state causing the inverted data Q 4 N to be output via the clocked inverter  42   b  and inverter  42   c.  In the way stated above, since the unit test circuit  40  is also configured from the latch  41  for use during standard operations and simple selector  12 , it is possible to reduce or minimize the circuit area. 
     As has been described above, according to the present invention, it is possible to obtain high defect detectability factor while suppressing an increase in area of testing circuitry and also possible to facilitate creation of test patterns required. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.