Abstract:
A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto. A method and system in accordance with the present invention provides the following advantages: Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates generally to FLASH memory controllers and more particularly to a system and method for configuring a FLASH memory controller for different types of FLASH memory chips.  
       BACKGROUND  
       [0002]     FLASH memory is generally used on a digital media storage product such as Secure Digital (SD), USB drive, Compact FLASH (CF), MultiMediaCard (MMC), Memory Stick (MS), Smart Media (SM) and others. A FLASH memory controller interfaces with various FLASH memory chips to construct one of the above mentioned digital media storage products. Conventional FLASH memory chips include an 8-bit data bus. A 16 bit FLASH memory chip has the same footprint as that of 8 bit FLASH memory chip. The 16 bit FLASH memory chips usually have the same pin assignment on electrical signals such as chip enable, ready, and control bus. However, the pin assignment for the data bus is generally very different between 8-bit and 16-bit FLASH memory. A conventional 16-bit FLASH memory controller is designed to interface with both 8-bit and 16-bit FLASH memory chips. The FLASH memory configuration on a digital media storage has the following four modes:  
         [0003]     1. Single 8-bit access  
         [0004]     2. Dual 8-bit parallel access  
         [0005]     3. Single 16-bit access  
         [0006]     4. Dual 16-bit interleave access  
         [0007]     Mode 4, dual 16-bit interleave access, has the best performance, while Mode 1, single 8-bit access, has the lowest performance. Mode 3, single 16-bit access, and mode 2, dual 8-bit parallel access, have a performance rating in between.  
         [0008]     Due to data bus pin-out difference between 8-bit and 16-bit flash memory chips, conventionally it requires two different printed circuit boards (PCB) to support the four modes above.  
         [0009]     One possible mapping of pins  10  between 8-bit and 16-bit FLASH memory chip is shown in  FIG. 1 . AHD 0  through AHD 15  are 16 bits data bus pins of 16-bit FLASH memory chip  12 . AD 0  through AD 7  are 8 bits data bus pins of 8-bit FLASH memory chip  14 . NC 26 , NC 27 , NC 28 , NC 33 , NC 40 , NC 45 , NC 46 , and NC 47  are 8 non-connect pins of 8-bit FLASH memory chip  14  mapping to 16-bit FLASH memory chip  12 . The term CS- refers to Chip Select, and the term BUSY- refers to Chip Busy. Other FLASH control bus pins are also included.  
         [0010]     The conventional FLASH memory chip  14  has an 8-bit data bus (AD) along with chip select (CS-), busy (BUSY-) and other control signals. A 16-bit FLASH memory chip  12  may reside in the same package as that of an 8-bit FLASH memory chip. These two kinds of FLASH memory chips  12  and  14  have the same pin designation for chip select (CS-), busy (BUSY-) and other control signals, except for data bus signals (AD &amp; AHD). One of pin mapping examples 10 of 8-bit FLASH memory chip  14  and 16-bit FLASH memory chip  12  is shown in  FIG. 1 . Note that data bus pins (AD 0 -AD 7 ) of 8-bit flash memory  14  are not mapped one-to-one to the lower eight bits data bus (AHD 0 -AHD 7 ) of 16-bit FLASH memory chip  12 . In fact, AD 0  through AD 7  are mapped to AHD 9 ,  2 ,  10 ,  3 ,  12 ,  5 ,  13  and  6  respectively. AHD 8 ,  0 ,  1 ,  11 ,  4 ,  7 ,  14  and  15  of 16-bit FLASH memory chip are mapped to the no-connect (NC) pins of 8-bit counter part.  
         [0011]     A 16-bit micro-controller (not shown) interfaces through its read/write control signals and data bus UD to a 16-bit FLASH Control Logic with FLASH data bus FD. The FD bus in turn interfaces with one or more 8-bit or 16-bit FLASH memory chips. Due to pin-out difference between 8-bit and 16-bit FLASH memory chip, conventionally it requires two different circuitries or printed circuit boards (PCBs) for these two different kinds of FLASH memory.  
         [0012]      FIG. 2  is a block diagram of a circuit  100  for a conventional 16-bit FLASH memory controller  102  to support a single 8-bit access (Access mode 1)  108   a  or two 8-bit parallel access (Access mode 2) flash memory chips  108   a  and  108   b.    
         [0013]     As in  FIG. 1 , a FLASH memory controller  102  includes a micro controller  104 , host interface  110 , a ROM  122 , a RAM  124 , an internal data bus (UD 0 -UD 15 )  112 , read/write control  114  and FLASH Control Logic  116 . FLASH Control Logic  116  includes an internal data bus (UD 0 -UD 15 )  112 , a FLASH chip select (FCS 0 -FCS 3 ), a FLASH control bus (Fcontrol Bus)  118 , a FLASH status bus (FBUSY 0 -FBUSY 3 ) and a FLASH data bus (FD 0 -FD 15 ).  
         [0014]     In the case of single 8-bit access, data bus FD 8  through FD 15   120  is not connected. In the case of two 8-bit parallel access, control buses are connected together to the FLASH memory controller  102 . Two 8-bit parallel access mode generally runs twice as fast as single 8-bit access mode because the access bandwidth is twice the size.  
         [0015]      FIG. 3  is a diagram for a conventional 16-bit FLASH memory controller  202  to support a single 16-bit access  208   a  or two 16-bit interleave access FLASH memory chips  208   a  and  208   b . 16-bit access generates the same performance as that of two 8-bit parallel access, while 16-bit interleave access has the best performance among the four access modes.  
         [0016]     In order to have the same 16-bit FLASH memory controller support all four modes of access on the same printed circuit board (PCB), a different routing is required from the high order flash memory controller data bus FD 8  through FD 15   220  to 8-bit and 16-bit FLASH memory chips  208   a  and  208   b , as shown in  FIG. 2  and  FIG. 3 . Referring now to  FIG. 4 , conventionally the routing and mapping is done by adding four sets of resistor networks RA, RHA, RB and RHB between FLASH memory controller and 8/16-bit flash memory chips, as shown in  FIG. 4 .  
         [0017]      FIG. 4  is a diagram of a circuit  300  for a conventional 16-bit FLASH memory controller  302  to support a single 8-bit access  308   a  or two 8-bit parallel access  308   a  and  308   b  or a single 16-bit access  308   a  or two 16-bit interleave access FLASH memory chips  308   a  and  308   b  on the same PCB. Four sets of resistor networks  310   a - 310   b , and  312   a - 312   b  are utilized to select different modes of operation. Table 1 shows the four possible combinations:  
                                                 TABLE 1                           Access       Resistor Network            Mode   Description   RA   RHA   RB   RHB               1   Single 8-bit access   Installed                   2   Dual 8-bit parallel access   Installed       Installed       3   Single 16-bit access       Installed       4   Dual 16-bit interleave access       Installed       Installed                    
         [0018]     One of the possible mappings of pin-outs is shown below:  
                                                                                                                                     TABLE 2                       FLASH                                                               memory           8-bit               16-bit           8 bit   Map-           16-bit       con-       FLASH   FLASH   Mapped       FLASH   FLASH       FLASH   FLASH   ped       FLASH   FLASH       troller   Resistor   Chip A   Chip A   to   Resistor   Chip A   Chip A   Resistor   Chip B   Chip B   to   Resistor   Chip B   Chip B       FD   Network   Pinout   AD   AHD   Network   Pinout   AHD   Network   Pinout   BD   BHD   Network   Pinout   BHD                                0   RA0   29   0   9   RHA0   26   0                   RHB0   26   0       1   RA1   30   1   2   RHA1   28   1                   RHB1   28   1       2   RA2   31   2   10   RHA2   30   2                   RHB2   30   2       3   Wired   32   3   3   Wired   32   3                   RHB3   32   3       4   RA4   41   4   12   RHA4   40   4                   RHB4   40   4       5   Wired   42   5   5   Wired   42   5                   RHB5   42   5       6   RA6   43   6   13   RHA6   44   6                   RHB6   44   6       7   RA7   44   7   6   RHA7   46   7                   RHB7   46   7       8                   Wired   27   8   RB8   29   0   9   RHB8   27   8       9                   RHA9   29   9   RB9   30   1   2   RHB9   29   9       10                   RHA10   31   10   wired   31   2   10   wired   31   10       11                   Wired   33   11   RB11   32   3   3   RHB11   33   11       12                   RHA12   41   12   wired   41   4   12   wired   41   12       13                   RHA13   43   13   RB13   42   5   5   RHB13   43   13       14                   Wired   45   14   RB14   43   6   13   RHB14   45   14       15                   Wired   47   15   RB15   44   7   6   RHB15   47   15                  
 
         [0019]     UD 0  through UD 15 , not shown, are 16 corresponding logical data bus bits from the micro-controller. FD 0  through FD 15  are 16 corresponding logical data bus bits from the FLASH memory controller. UD and FD data bus are wired through.  
         [0020]     AD 0  through AD 7  are 8 corresponding logical data bus bits from 8-bit FLASH chip A  308   a . AHD 0  through AHD 15  are 16 corresponding logical data bus bits from 16-bit FLASH chip A 308   a . BD 0  through BD 7  are 8 corresponding logical data bus bits from 8-bit FLASH chip B  308   b . BHD 0  through BHD 15  are 16 corresponding logical data bus bits from 16-bit FLASH chip B  308   b.    
         [0021]     “Wired” means no resistor network required. The connection is wired directly. Resistor networks RA  310   a  and RHA  310   b  are exclusive. Resistor network RA  310   a  is installed when an 8-bit FLASH chip is in use. Resistor network RHA  310   b  is installed when a 16-bit FLASH is in use. Resistor networks RB  312   a  and RHB  312   b  are exclusive. Resistor network RB  312   a  is installed when an 8-bit FLASH chip is in use. Resistor network RHB  312   b  is installed when a 16-bit FLASH is in use.  
         [0022]     In order to be able to support both types of FLASH memory chips, it is required that both logic circuitries be combined together. Resistor networks RA  310   a  and RHA  310   b  are exclusive pairs serving as selector to select either 8-bit or 16-bit FLASH memory chips at physical location A  308   a . Resistor networks RB  312   a  and RHB  312   b  are exclusive pairs serving as selector to select either 8-bit or 16-bit FLASH memory chips at physical location B  308   b . There are a total of 96 signal traces in this circuit  300  that create great routing complexity in PCB layout. The mapping implementation is shown in Table 2. The corresponding logic equations are shown in Listing 1.  
         [0000]     Listing 1  
         [0023]     Logic equations of the mapping: (* is logical AND operator. + is logical OR operator) 
 
 FD 0=( RA 0 *AHD 9 +RHA 0 *AHD 0)+ RHB 0 *BHD 0 
 
 FD 1=( RA 1 *AHD 2 +RHA 1 *AHD 1)+ RHB 1 *BHD 1 
 
 FD 2=( RA 2 *AHD 10 +RHA 2 *AHD 2)+ RHB 2 *BHD 2 
 
 FD 3 =AHD 3 +RHB 3 *BHD 3 
 
 FD 4=( RA 4 *AHD 12 +RHA 4 *AHD 4)+ RHB 4 *BHD 4 
 
 FD 5 =AHD 5 +RHB 5 *BHD 5 
 
 FD 6=( RA 6 *AHD 13 +RHA 6 *AHD 6)+ RHB 6 *BHD 6 
 
 FD 7=( RA 7 *AHD 6 +RHA 7 *AHD 7)+ RHB 7 *BHD 7 
 
 FD 8 =AHD 8+( RB 8 *BHD 9 +RHB 8 *BHD 8) 
 
FD9 =RHA 9 *AHD 9+( RB 9 *BHD 2 +RHB 9 *BHD 9) 
 
 FD 10 =RHA 10 *AHD 10 +BHD 10 
 
 FD 11 =AHD 11+( RB 11 *BHD 3 +RHB 11 *BHD 11) 
 
 FD 12 =RHA 12 *AHD 12 +BHD 12 
 
 FD 13 =RHA 13 *AHD 13+( RB 13 *BHD 5 +RHB 13 *BHD 13) 
 
 FD 14 =AHD 14+( RB 14 *BHD 13 +RHB 14 *BHD 14) 
 
 FD 15 =AHD 15+( RB 15 *BHD 6 +RHB 15 *BHD 15) 
 
         [0024]     As is shown in  FIG. 4 , there are 48 signal traces on both sides of resistor network RA, RHA, RB and RHB. A total of 96 traces are required to connect between FLASH memory controller and flash memory chips. Routing complexity makes it almost impossible to consider laying out support of both 8-bit and 16-bit FLASH memory chips with 16-bit FLASH memory controller.  
         [0025]     Furthermore, different FLASH technology may have different FLASH memory data bus assignment due to package efficiency consideration. It is desirable to have a FLASH memory controller with flexible and field configurable architecture to accommodate present and future FLASH memory variations.  
         [0026]     As FLASH memory technology becomes more mature, demand for higher performance becomes more imminent. One natural approach to improve the performance is to increase data bus bandwidth either on the FLASH memory controller side or on the FLASH memory side. It is no wonder that FLASH memory controller will expand its data bus bandwidth from 8-bit and 16-bit to 32-bit and beyond in the near future. FLASH memory chip may as well take the same expansion route for wider bandwidth. As the bandwidth increases, conventional way of adding more resistor networks to support all sizes of FLASH memory chips becomes more cumbersome.  
         [0027]     It is desirable to provide a FLASH memory controller system to accommodate the following objectives:  
         [0028]     Supporting 8-bit and 16-bit FLASH memory chips on the same PCB  
         [0029]     Supporting all four FLASH memory access modes  
         [0030]     Supporting all possible FLASH memory configurations  
         [0031]     Improving layout routing complexity on PCB  
         [0032]     Auto-detection and configuration of FLASH memory controller data bus  
         [0033]     Able to scale up the controller data bus bandwidth for higher performance  
         [0034]     The present invention addresses such a need.  
       SUMMARY OF THE INVENTION  
       [0035]     A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto.  
         [0036]     A method and system in accordance with the present invention provides the following advantages:  
         [0037]     Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0038]      FIG. 1  is one possible mapping of pins between 8-bit and 16-bit FLASH memory chip sharing the same footprint and package.  
         [0039]      FIG. 2  is a circuit block diagram for a conventional 16-bit FLASH memory controller to support a single 8-bit access or two 8-bit parallel access FLASH memory chips.  
         [0040]      FIG. 3  is a circuit block diagram for a conventional 16-bit FLASH memory controller to support a single 16-bit access or two 16-bit interleave access FLASH memory chips.  
         [0041]      FIG. 4  is a circuit block diagram for a conventional 16-bit FLASH memory controller to support a single 8-bit access or two 8-bit parallel access or a single 16-bit access or two 16-bit interleave access FLASH memory chips on the same PCB.  
         [0042]      FIG. 5  is a simplified circuit block diagram for configurable data bus on FLASH memory controller interfacing with two 8/16-bit FLASH memory chips.  
         [0043]      FIG. 6  is a generalized logic equation matrix transformation between micro-controller data bus and FLASH memory controller data bus.  
         [0044]      FIG. 7  is one possible mapping of circuit block diagram for configurable data bus on FLASH memory controller interfacing with two 8/16-bit FLASH memory chips.  
         [0045]      FIG. 8  is logic function implementation between FD (FLASH memory controller data bus) and UD (micro-controller data bus).  
         [0046]      FIG. 8A  is FLASH data bus mapper implementation.  
         [0047]      FIG. 9  is logic function implementation between FCS (FLASH chip select) bus and UCS (chip select) bus; as well as a logic function implementation between FBUSY (FLASH chip busy) status and UBUSY (logical chip busy) status.  
         [0048]      FIG. 9A  is FLASH CS/BUSY mapper implementation.  
         [0049]      FIG. 10  is a flow chart for FLASH memory controller to auto-detect the type of FLASH memory and configuration.  
         [0050]      FIG. 11  is a flow chart for FLASH memory controller to test and detect the type of FLASH memory. 
     
    
     DETAILED DESCRIPTION  
       [0051]     The present invention relates generally to flash memory controllers and more particularly to a system and method for configuring a flash memory controller for different types of flash memory chips.  
         [0052]     The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.  
         [0053]     A method in accordance with the present invention supports both 8-bit and 16-bit FLASH memory chips and simplifies routing complexity by offering configurable data bus on FLASH Control Logic through firmware in the microcontroller and mapping logic in the FLASH controller logic.  FIG. 5  is a simplified block diagram of a circuit  400  for a configurable data bus on a FLASH memory controller  402  interfacing with two 8/16-bit FLASH memory chips  408   a  and  408   b . Routing traces are reduced from 96 down to 48, a 50% complexity reduction through the use of firmware  410  in the microntroller  404  and mapping logic  412  in the FLASH controller logic  406 . The pin-out mapping and logic representation of circuitry are shown in Table 3 and Listing 2 respectively.  
                                                                           TABLE 3                           Physical &amp; Logical Mapping on FLASH memory controller and       Memory Pinouts            FLASH       FLASH   FLASH       FLASH           memory   FLASH   x8   x16   FLASH   x8   FLASH       controller   Chip A   Chip A   Chip A   Chip B   Chip B   x16 Chip B       FD   Pinout   AD   AHD   Pinout   BD   BHD                    0   29   0   9   27       8       1   30   1   2   26       0       2   31   2   10   28       1       3   32   3   3   33       11       4   41   4   12   40       4       5   42   5   5   46       7       6   43   6   13   45       14       7   44   7   6   47       15       8   27       8   29   0   9       9   26       0   30   1   2       10   28       1   31   2   10       11   33       11   32   3   3       12   40       4   41   4   12       13   46       7   42   5   5       14   45       14   43   6   13       15   47       15   44   7   6                  
 
 Listing 2. Logic Equations for One of the Possible Configurable Mappings 
 
 (* is Logical AND Operator. + is Logical OR Operator) 
 
 FD 0=Chip A *(8 bit* UD 0+16 bit *UD 9)+Chip B*UD 8 
 
 FD 1=Chip A *(8 bit *UD 1+16 bit *UD 2)+Chip B*UD 0 
 
 FD 2=Chip A *(8 bit *UD   2+16 bit   *UD 10)+Chip B*UD 1 
 
 FD 3=Chip A *(8 bit *UD 3+16 bit *UD 3)+Chip B*UD 11=Chip A*UD 3+Chip B*UD 11 
 
 FD 4=Chip A *(8 bit *UD 4+16 bit *UD 12)+Chip B*UD 4 
 
 FD 5=Chip A *(8 bit *UD 5+16 bit *UD 5)+Chip B*UD 7=Chip A*UD 5+Chip B*UD 7 
 
 FD 6=Chip A *(8 bit *UD 6+16 bit *UD 13)+Chip B*UD 14 
 
 FD 7=Chip A *(8 bit *UD 7+16 bit *UD 6)+Chip B*UD 15 
 
 FD 8=Chip A*UD 8+Chip B *(8 bit *UD 0+16 bit *UD 9) 
 
 FD 9=Chip A*UD 0+Chip B *(8 bit *UD 1+16 bit *UD 2) 
 
 FD 10=Chip A*UD 1+Chip B *(8 bit *UD 2+16 bit *UD 10) 
 
 FD 11=Chip A*UD 11+Chip B *(8 bit *UD 3+16 bit *UD 3)=Chip A*UD 11+Chip B*UD 3 
 
 FD 12=Chip A*UD 4+Chip B *(8 bit *UD 4+16 bit *UD 12) 
 
 FD 13=Chip A*UD 7+Chip B *(8 bit *UD 5+16 bit *UD 5)=Chip A*UD 7+Chip B*UD 5 
 
 FD 14=Chip A*UD 14+Chip B *(8 bit *UD 6+16 bit *UD 13) 
 
 FD 15=Chip A*UD 15+Chip B *(8 bit *UD 7+16 bit *UD 6) 
 
 Note that: 
 
         [0054]     FD 0  through FD 15  are 16 corresponding logical data bus bits from FLASH Control Logic.  
         [0055]     UD 0  through UD 15  are 16 corresponding logical data bus bits from micro-controller.  
         [0056]     AD 0  through AD 7  are 8 corresponding logical data bus bits from 8-bit FLASH memory chip at physical location A.  
         [0057]     AHD 0  through AHD 15  are 16 corresponding logical data bus bits from 16-bit FLASH memory chip at physical location A.  
         [0058]     BD 0  through BD 7  are 8 corresponding logical data bus bits from 8-bit FLASH memory chip at physical location B.  
         [0059]     BHD 0  through BHD 15  are 16 corresponding logical data bus bits from 16-bit FLASH memory chip at physical location B.  
         [0060]     Chip A is a binary representation to select FLASH memory chip at physical location A.  
         [0061]     Chip B is a binary representation to select FLASH memory chip at physical location B. Chip B is usually a logical inversion of Chip A.  
         [0062]     8 bit is a binary representation to select 8-bit FLASH memory chip.  
         [0000]     16 bit is a binary representation to select 16-bit FLASH memory chip. 16 bit is usually a logical inversion of 8 bit.  
         [0063]     The logic equations can be generalized and expressed as matrix transformation as shown in  FIG. 6 . There are five 1×16 matrices in the equations. The first matrix from left hand side defines 16-bit flash memory controller data bus. The second matrix defines corresponding 8-bit data bus on 8-bit FLASH memory chip at physical location A. Those unused bits are filled with Nil. The third matrix defines corresponding 16-bit data bus on 16-bit FLASH memory chip at physical location A. The fourth matrix defines corresponding 8-bit data bus on 8-bit FLASH memory chip at physical location B. Since these 8 bits data bus are connected to second-half of the FLASH memory controller&#39;s 16-bit data bus, the first-half of the matrix unused bits are filled with Nil. The fifth matrix defines corresponding 16-bit data bus on 16-bit FLASH memory chip at physical location B.  
         [0064]     In general, the third and fifth matrix can be modified to accommodate different mappings among different FLASH memory technology. The values can be loaded by firmware  410  on the microcontroller  404 . It literally changes the routing from hardware to software programming that dramatically reduces complexity. The firmware  410  then interacts with mapping logic  412  on the FLASH memory controller  402  to configure the data bus appropriately.  
         [0065]      FIG. 7  is one embodiment of a configurable data bus on a FLASH memory controller  402 ′ interfacing with two 8/16-bit FLASH memory chips  408   a ′ and  408   b ′. Note that FLASH data bus pins FD 0  through FD 7  are connected to AD 0  through AD 7 , which are AHD 9 , 2 , 10 , 3 , 12 , 5 , 13 , 6  respectively. FLASH data bus pins FD 8  through FD 15  are connected to BD 0  through BD 7 , which are BHD 9 , 2 , 10 , 3 , 12 , 5 , 13 , 6  respectively. This circuit diagram is one of the applications of the invention.  
         [0066]     The configurable mapping logic  412  is implemented with sixteen 16-to-1 selectors and a 16-bit configuration register C.  FIG. 8  shows one such implementation of selector  504 . Its function FD(n) is derived from function UD(C(n)), where C(n) is the n-th bit corresponding with configuration C-Register C  502 .  FIG. 8A  shows a FLASH data bus mapper logic  412 , where C-Register  502  is configurable. It uses  FIG. 8  as a building block. Physical FLASH data bus FD( 0 ) through FD( 15 ) can be mapped to logical data bus UD( 0 ) through UD( 15 ) from micro controller  402  ( FIG. 5 ).  
         [0067]     Another feature of a system and method in accordance with the present invention is to offer flexibility of FLASH memory placement by configurable chip select (FCS) and control bus signals. A conventional FLASH memory controller has a very rigid chip select sequence and order. Therefore there is a significant constraint on how a FLASH memory chip is installed and how much the system can be expanded. The FLASH memory location, if not fully populated, should have the memory installed in a fixed order or sequence.  
         [0068]     In a preferred embodiment, a system and method in accordance with the present invention introduces four 4-to-1 selectors and a 4-bit select register SEL to allow for more configurability and for allowing for a more expanded and scalable system.  FIG. 9  shows one such implementation of Chip Select bit n. Its function FCS(n) is derived from function UCS(SEL(n)), where SEL(n) is the n-th bit corresponding with configuration register SEL. UCS is the logical Chip Select register from micro-controller&#39;s perspective. Through this mapping, the physical installation order of FLASH memory chips can be of any sequence and combination. As long as the micro-controller  402  ( FIG. 5 ) has a way to detect type and location of FLASH memory chip, the logical mapping can be done easily through firmware making bookkeeping and management of FLASH memory. Future expansion with any combination of FLASH memory chips becomes a simple reality. A similar mapping selector  600  for FBUSY bus and BUSY bus can be implemented in the same way as in  FIG. 9 .  
         [0069]      FIG. 9A  is a flash CS/BUSY mapper implementation  712 , where SEL-Register  702  is configurable. It uses  FIG. 9  as a building block. Physical chip select signals FCS( 0 ) through FCS( 3 ) can be mapped to logical chip select signals UCS( 0 ) through UCS( 3 ) from microcontroller. Similarly, physical chip busy status FBUSY( 0 ) through FBUSY( 3 ) can be mapped to logical chip busy status UBUSY( 0 ) through UBUSY( 3 ) from microcontroller.  
         [0070]      FIG. 10  is a flow chart for a FLASH memory controller to auto-detect the type of FLASH memory and its configuration. During the auto-detection process, mapping logic first configures the FLASH control logic to work with 8-bit FLASH memory. The corresponding value is loaded into configuration register C. The corresponding chip select register is also loaded with default value. Each physical location is tested one by one through setting selection register SEL.  
         [0071]     First, FLASH controller auto-detection is started, via step  802 . Next, a Flash Data Bus is mapped to the default 8-bit FLASH memory chip, via step  804 . Then, the configuration register is loaded C(N)=N, N=0 to 15, via step  806 . Then, the chip select register is loaded SEL(N)=N, N=0 to 3, via step  810 . Thereafter set M=0, via step  812 . Next FLASH chip M is selected, Set SEL(M), via step  814 . Then, test FLASH memory chip M, via step  816 . Check if this is the last FLASH memory step? via step  820 . If no, M=M+1, via step  822  and return to step  814 . If yes, re-organize the order of chip select, via step  824 .  
         [0072]      FIG. 11  is a flow chart for FLASH memory controller to test and detect the type of FLASH memory. In this embodiment, the micro-controller first tests if FLASH memory chip is responsive, via steps  902  and  904 . If so, 8-bit protocol is used to further test FLASH memory chip  906 . If the result is OK, 8-bit FLASH memory chip is detected, via step  908 . Otherwise, either if FLASH memory is not responsive or 8-bit test fails, micro-controller firmware will reload configuration register C for a 16-bit FLASH memory chip, via step  910 . 16-bit protocol is then used to test FLASH memory chip. If the result is OK, via step  912 , 16-bit FLASH memory chip is detected, via step  916 . If it fails, no FLASH memory chip is detected at this physical location via step  914 . In any case, the Chip Select and FLASH type and/or status are recorded and the process returns to test the next physical location, until all locations are visited.  
         [0073]     After all physical locations are tested, the micro-controller has detected the FLASH memory type and density configuration. It may re-organize the order of chip select signals for easier programming in the firmware.  
         [0074]     Although a system and method has been described utilizing 16-bit FLASH memory controller and 8-bit and 16-bit FLASH memory chips, its architecture is scalable for higher data bus bandwidth support on either FLASH memory controller or FLASH memory chip. Generalized matrix transformation as shown in  FIG. 6  scales to 32-bit data bus and beyond.  
         [0075]     A method and system in accordance with the present invention provides the following advantages:  
         [0076]     a. Configurable data bus on FLASH memory controller through software to simplify routing complexity. 
        i. Routing traces are reduced from 96 down to 48, a 50% complexity reduction.        
 
         [0078]     b. Configurable chip select and control bus for flexibility of FLASH memory placement.  
         [0079]     c. Eliminating external resistor network for layout simplicity.  
         [0080]     d. Scalable architecture for higher data bus bandwidth support. 
        i. Scalable to 32-bit FLASH memory controller, or FLASH memory chip with no external hardware component.        
 
         [0082]     e. Auto-detection of FLASH memory type and capacity configuration.  
         [0083]     Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.