Abstract:
A low distortion sinusoidal oscillator made up of a two transistor negative resistance element combined with an LC tank for generating bias and erase signals for battery powered magnetic media recording apparatus.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     This invention relates generally to circuits for facilitating magnetic reading, writing and erasing. More specifically, this invention relates to providing bias and erase signals which are independent of power supply fluctuations. 
     2. Description of the Prior Art 
     Representative of the closest known prior art patents are U.S. Pat. Nos. 2,810,073; 3,038,036; 3,201,713; 3,305,795; 3,346,821; 3,354,270; and 3,424,871. These patents were developed during a novelty search. Of these U.S. Pat. Nos. 2,810,073 and 3,354,270 are considered the closest in that sinusoidal outputs are generated. The first basically deals with output amplitude stabilization which is accomplished through regulating the power supply voltage. With the subject invention, the circuit is made insensitive to the supply voltage. The second discloses a push/pull circuit configuration rather than a negative resistance oscillator. In addition, the IBM Model 271 Recorder utilizes a soundhead to form a part of an LC tank circuit, but a separate stable reference voltage is not used. 
     When a low distortion sinusoidal bias and erase oscillator is to be provided for use in portable or miniature battery operated magnetic media recorders, a number of problems are encountered. In addition to low distortion, the amplitude and frequency of the oscillator must be insensitive to battery voltage fluctuations, the required battery drain must be low, and the number of circuit components must be low and small in size. These problems are overcome with the oscillator circuit of this invention. 
     SUMMARY OF THE INVENTION 
     An oscillator circuit is provided for obtaining low distortion signals for bias and erase. The circuit is made up primarily of two sections. One of the sections is a frequency determining LC tank. Low distortion oscillation is produced with a low Q tank, and supply current is low relative to the tank current. The other is an AC coupled negative resistance element. 
     The LC tank is made up of a first inductor, and a second inductor which is the erase winding. The tank also has a series combination of first and second capacitors. The negative resistance element is formed by a differential pair of first and second transistors. This pair of transistors is DC biased to a reference voltage through a first resistor, with a capacitor providing decoupling. A second resistor provides a load for the reference voltage. The base of the first transistor is biased by a third resistor. The DC current through the first and second transistors is adjusted by a fourth resistor, while fifth and sixth resistors make the current through the fourth resistor split nearly evenly through the transistors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 illustrates the overall oscillator circuit of this invention; 
     FIG. 2 shows an AC equivalent of the frequency determining LC tank section of the circuit shown in FIG. 1; and 
     FIG. 3 illustrates the AC coupled negative resistance element portion of the circuit shown in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring first to FIG. 1 there is shown the overall circuit diagram for the bias/erase oscillator of this invention. Low distortion sinusoidal oscillations are effected by combining an LC tank with a two transistor negative resistance element. Low distortion is provided even though the Q of the LC tank is low. The frequency of oscillation is determined by the LC tank, thereby making it insensitive to supply voltage fluctuations. The oscillation amplitude is determined by a separate stable reference voltage, and is also insensitive to supply voltage fluctuations. Low battery drain is obtained by keeping the emitter and base voltage excursions of the transistors to a minimum. The circuit uses the erase winding itself as part of the LC tank in order to eliminate an additional driver. The erase current is determined directly by the oscillation amplitude and shares all of the stability advantages of the oscillator. 
     Referring next to FIG. 2 there is shown the AC equivalent of the LC tank section of FIG. 1. This tank is comprised of a first inductor L1 in parallel with an erase winding LE which is in turn in parallel with a series combination of capacitors C3 and C4. Capacitor C1 is in series with erase winding or inductor LE and is used to prevent DC current from entering the erase winding. 
     The tank input is driven from the collector of transistor Q1 (FIG. 1) which is DC biased to the supply Vcc through inductor L1. The output from the tank is derived from between capacitors C3 and C4 which form a capacitive divider. The tank output is applied to the base of transistor Q2 which is the input to the negative resistance element shown in FIG. 3. 
     The negative resistance element is formed by the differential pair of transistors Q1 and Q2. The pair is DC biased to a reference voltage Vref through resistor R3 (FIG. 1) with capacitor C2 providing decoupling. Resistor R2 basically is for providing a load for the reference voltage Vref. 
     The two bases of the transistors Q1 and Q2 are biased closely together by resistor R4. Transistors Q1 and Q2 are conventional NPN transistors. Resistor R4 is representative of a resistance between C2+ and Q1 on one side, and C4+ and Q2 on the other. The DC current through transistors Q1 and Q2 is adjusted by variable resistor R1, while resistors R5 and R6 make the current through resistor R1 split approximately equally through the two transistors Q1 and Q2. 
     Since resistors R5 and R6 reduce the DC gain of the differential pair of transistors Q1 and Q2, capacitor C5 is included to allow the pair to have a maximum AC gain regardless of DC bias. 
     The capacitively divided tank voltage is used to drive the negative resistance element in order that emitter voltage excursions will be relatively small and thereby maintain nearly constant current through resistor R1. 
     Since the input to the pair (the base of transistor Q2) is connected to the output (the collector of Q1) through capacitor C3, the input and output can be considered as being the same AC node. When the voltage at the base of transistor Q2 rises, the output current decreases. Therefore, the transistor pair Q1 and Q2, taken as one element, has a negative resistance characteristic. 
     The amplitude of oscillation will stabilize at the point where the energy added to the tank by the negative resistance element is just equal to the tank losses. The peak-to-peak tank voltage may exceed the supply voltage being limited eventually by saturation of transistor Q1. 
     During normal operation, the circuit will cause relatively low distortion during oscillation, and will not clip. 
     From the above, an AC coupled negative resistance element is used, a low distortion oscillation is produced with a low Q tank, the supply current is low relative to the tank current, a two terminal erase winding with no DC erase current present is utilized in conjunction with a capacitive voltage divider as frequency determining element and sensitivity to minor transistor mismatch is negligible. 
     In summary, an oscillator circuit is provided for obtaining a low distortion signal for bias and erase. The circuit is made up primarily of two sections. One of the sections is a frequency determining LC tank. Low distortion oscillation is produced with a low Q tank having a capacitive voltage divider, and supply current is low relative to the tank current. The other is an AC coupled negative resistance element. 
     The LC tank is made up of a first inductor, and a second inductor which is the erase winding. The tank also has a series combination of first and second capacitors. The negative resistance element is formed by a differential pair of first and second transistors. This pair of transistors is DC biased to a reference voltage through a first resistor, with a capacitor providing decoupling. A second resistor provides a load for the reference voltage. The base of the first transistor is biased by a third resistor. The DC current through the first and second transistors is adjusted by a fourth resistor, while fifth and sixth resistors make the current through the fourth resistor split nearly evenly through the transistors. 
     While the invention has been shown and described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.