Abstract:
A spreading code generating device for a Code Division Multiple Access (CDMA) communication system. The device comprises a PN (Pseudorandom Noise) code sequence generator for generating PN i  and PN q  sequences; an orthogonal code generator for generating first and second orthogonal codes which perform Differential Phase Shift Keying (DPSK) state transitions at intervals of at least two chips; and a spreading code generator for generating spreading codes C i  and C q  by mixing the PN i  and PN q  code sequences with the first and second orthogonal codes such that a present phase of the spreading codes C i and C   q  alternately makes Quadrature Phase Shift Keying (QPSK) and DPSK state transitions with respect to a previous phase of the spreading codes C i  and C q .

Description:
PRIORITY 
     This application claims priority to an application entitled “Device and Method for Generating Spreading Code and Spreading Channel Signals Using Spreading Code in CDMA Communication System” filed in the Korean Industrial Property Office on Sept. 29, 1998 and assigned Ser. No. 98-40507, the contents of which are hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a spread spectrum device and method for a CDMA communication system, and in particular, to a device and method for generating spreading sequences. 
     2. Description of the Related Art 
     Code Division Multiple Access (CDMA) mobile communication systems have developed from an existing mobile communication standard which mainly provides voice service into the IMT-2000 standard which can provide not only voice service but also high speed data transmission service. For example, the IMT-2000 standard can provide high quality voice, moving picture, and Internet search services. In CDMA communication systems, communication links between a base station and a mobile station include a forward link for transmitting from the base station to the mobile station and a reverse link for transmitting from the mobile station to the base station. 
     In CDMA communication systems, the reverse link typically employs a PN (Pseudorandom Noise) code complex spreading scheme as the spread spectrum method. However, the PN code complex spreading scheme has a problem when the power amplifier has an increase in the peak-to-average power ratio (PAR) because of user data. In the reverse link, an increase in the peak-to-average ratio of transmission power causes ‘re-growth,’ described below, which affects the design and performance of the power amplifier in the mobile stations. The characteristic curve of the power amplifier in the mobile station has a linear area and a non-linear area. When the transmission power of the mobile station increases, the signal of the mobile station will enter the non-linear area, interfering with the frequency areas of other users, which is called the “re-growth” phenomenon. In order not to interfere with the frequency areas of the other users, the cell area should be reduced in size and mobile stations in a cell area should transmit to the corresponding base station at a lower transmission power. Therefore, there is a need for a spreading method which decreases PAR while minimizing the degradation of bit error rate (BER) performance which affects the overall system performance. 
     A description of the PN complex spreading scheme will be made herein below with reference to a transmitter in a conventional CDMA communication system. 
     FIG. 1 illustrates a channel transmitter, including a spread spectrum device, for a CDMA communication system. As illustrated, the channel transmitter includes an orthogonal spreader  101 , a complex multiplier  102 , a PN sequence generator  103  and a lowpass filtering and modulation part  104 . 
     Referring to FIG. 1, the transmission data of each channel is applied to the orthogonal spreader  101  after channel coding, repetition and interleaving through corresponding channel coders (not shown). The orthogonal spreader  101  then multiplies the input channel data by a unique orthogonal code assigned to the corresponding channel to orthogonally spread the input channel data. Walsh codes are typically used for the orthogonal codes. The PN sequence generator  103  generates spreading sequences for spreading the transmission signals of the respective channels. PN sequences are typically used for the spreading sequences. The complex multiplier  102  complex multiplies the signals output from the orthogonal spreader  101  by the spreading sequences output from the PN sequence generator  103  to generate complex spread signals. The lowpass filtering and modulation part  104  baseband filters the complex spread signals output from the complex multiplier  102  and then converts the baseband filtered signals to RF (Radio Frequency) signals. 
     FIG. 2 is a detailed diagram illustrating the channel transmitter of FIG. 1 for the reverse link. 
     Referring to FIG. 2, the transmission data of each channel undergoes channel coding, repeating, channel interleaving and binary mapping in such a manner that a signal “0” is mapped to “+1” and a signal “1” to “−1”, prior to being input to the corresponding channel. The data of the respective channels is multiplied by unique orthogonal codes in multipliers  111 ,  121 ,  131  and  141 . In FIG. 2, channel transmitters include a pilot channel transmitter, a control channel transmitter, a supplemental channel transmitter and a fundamental channel transmitter. As stated above, Walsh codes are typically used for the orthogonal codes that spread the respective channels. The orthogonally spread data of the control channel, the supplemental channel and the fundamental channel is multiplied by gains appropriate for each channel by the first to third gain controllers  122 ,  132  and  142 . The channel data is added by binary adders  112  and  133  and then applied to the complex multiplier  102 . Herein, the outputs of the binary adders  112  and  133  will be referred to as “channelized data”. 
     The complex multiplier  102  multiplies the outputs of the adders  112  and  133  by spreading codes to perform spreading. As stated above, the PN codes output from the PN sequence generator  103  are used for the spreading codes. The PN codes input to the complex multiplier  102  have a rate equal to a chip rate and may have a value comprised of “+1” and “−1”. Herein, unless otherwise stated, the PN codes are assumed to have a value of “+1” and “−1”. 
     With regard to the complex multiplier  102 , channelized data output from the adder  112  is applied to multipliers  113  and  143 , and channelized data output from the adder  133  is applied to multipliers  123  and  134 . Further, a spreading code PN i  output from the PN sequence generator  103  is applied to the multipliers  113  and  123  and a spreading code PN q  output from the PN sequence generator  103  is applied to the multipliers  134  and  143 . In addition, outputs of the multipliers  113  and  134  are subtracted from each other by an adder  114  and then applied to a first lowpass filter  115 ; and outputs of the multipliers  123  and  143  are added to each other by an adder  135  and then applied to a second lowpass filter  136 . 
     A real signal out of the outputs from the binary adder  114  is input to the first lowpass filter  115  and an imaginary signal is input to the second lowpass filter  136 . Output signals of the lowpass filters  115  and  136  are gain controlled by fourth and fifth gain controllers  116  and  137 , respectively, then modulated, added together, and transmitted through a transmission channel. The lowpass filtering and modulation part  104  lowpass filters and modulates the output data of the binary adders  114  and  135 , and then outputs the modulated data from a binary adder  118 . 
     Several methods have been proposed for reducing the PAR of the signals output from the first and second lowpass filters  115  and  136 , and those methods are based on how the PN sequence generator  103  generates the spreading codes PN i  and PN q . In general, the peak-to-average power ratio PAR depends on both zero-crossings, which occur when the signs of PN i  and PN q  are simultaneously changed, and hold-phase-state, which occurs when the signs of both PN i  and PN q  are not changed. More specifically, zero-crossings (ZC) happen when, for example, an initial state in the first quadrant transitions to the third quadrant, causing a phase shift of π. Further, a hold-phase-state, or “hold,” happens when, for example, an initial state in the first quadrant remains in the first quadrant, causing no phase shift. 
     As stated above, in conventional QPSK (Quadrature Phase Shift Keying) spreading, a phase of the generated spreading codes can transition from the first quadrant to any of the second, third and fourth quadrants according to the value of the PN codes. Accordingly, when the conventional spreading code generation method is used, the PAR performance may deteriorate due to the zero-crossing phenomenon and the hold-phase-state phenomenon. Therefore, in a CDMA communication system, during spreading, the PAR is increased depending on the PN i  and PN q . 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a device and method for generating a spreading sequence which can decrease the peak-to-average power ratio without degrading BER performance in a CDMA communication system. 
     It is another object of the present invention to provide a device and method for repeatedly generating a QPSK and π/2-DPSK (Differential Phase Shift Keying) phase-shifted PN sequence as a spreading sequence in a CDMA communication system. 
     It is further another object of the present invention to provide a device and method for generating a QPSK, π/2-DPSK, and zero-crossing or hold phase-shifted PN sequence as a spreading sequence in a CDMA communication system. 
     It is still another object of the present invention to provide a device and method for generating a spreading sequence which alternately performs a DPSK phase shift and a QPSK phase shift by mixing a PN sequence with a specific orthogonal code in a CDMA communication system. 
     It is yet another object of the present invention to provide a device and method for generating a DPSK and QPSK phase-shifted spreading sequence by mixing a generated PN sequence with a previous spreading sequence, and generating a spreading sequence which alternately performs a DPSK phase shift and a QPSK phase shift by selecting a generated spreading sequence, in a CDMA communication system. 
     It is yet another object of the present invention to provide a device and method for generating a spreading sequence which repeats the pattern of a QPSK phase shift, a DPSK phase shift, a zero-crossing or hold (ZCH), and a DPSK phase shift by mixing a PN sequence with a specific orthogonal code in a CDMA communication system. 
     It is yet another object of the present invention to provide a device and method for generating a QPSK phase shift, a DPSK phase shift, a 180° or 0° phase-shift (ZCH) spreading sequence by mixing a generated PN sequence with a previous spreading sequence, and generating a spreading sequence which repeatedly performs QPSK, DPSK, zero-crossing or hold, and DPSK phase shifts by selecting the generated spreading sequence, in a CDMA communication system. 
     It is yet another object of the present invention to provide a device and method for alternately generating a QPSK and π/2-DPSK phase-shifted PN sequence as a spreading sequence, and spreading/despreading a channel signal using the generated spreading sequence, in a CDMA communication system. 
     It is yet another object of the present invention to provide a device and method for generating a QPSK, π/2-DPSK, zero-crossing or hold phase-shifted PN sequence as a spreading code, and spreading/despreading a channel signal using the generated spreading sequence, in a CDMA communication system. 
     To achieve the above and other objects, a spreading code generating device is provided for a CDMA communication system. The device is comprised of a PN sequence generator for generating PN i  and PN q  sequences; an orthogonal code generator for generating first and second orthogonal codes which perform DPSK state transitions at intervals of at least two chips; and a spreading code generator for generating spreading codes C i  and C q  by mixing the PN i  and PN q  sequences with the first and second orthogonal codes such that the present phase of the spreading codes C i  and C q  alternately generates QPSK and DPSK state transitions with respect to the phase of the previous spreading codes C i  and C q . 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a block diagram illustrating a channel transmitter for a CDMA communication system; 
     FIG. 2 is a detailed diagram of a reverse link channel transmitter for a CDMA communication system; 
     FIGS. 3 to  6  are diagrams illustrating primitive state transition for zero-crossing, hold, +π/2-DPSK and −π/2-DPSK, respectively; 
     FIG. 7 is a diagram illustrating a π/2-DPSK spreading sequence generating scheme for a spread spectrum device in a CDMA communication system; 
     FIG. 8 is a diagram illustrating a QPSK, π/2-DPSK spreading sequence generating scheme for a spread spectrum device in a CDMA communication system; 
     FIG. 9 is a timing diagram showing the generation of a QPSK, π/2-DPSK spreading sequence using the scheme of FIG. 8; 
     FIG. 10 is a timing diagram showing the QPSK, π/2-DPSK state transitions in a QPSK, π/2-DPSK spreading sequence generating scheme; 
     FIG. 11 is a timing diagram showing the π/2-DPSK, QPSK state transitions in a π/2-DPSK, QPSK spreading sequence generating scheme; 
     FIG. 12 is a timing diagram showing the π/2-DPSK, QPSK state transitions when a spreading sequence is generated with one-chip advanced in a CDMA communication system; 
     FIG. 13 is a timing diagram showing the π/2-DPSK, QPSK state transitions when a spreading sequence is generated with a one-chip delay in a CDMA communication system; 
     FIG. 14 is a block diagram of a spreading code generator which implements D-Q state transitions using a one-chip delay according to an embodiment of the present invention, in a CDMA communication system; 
     FIG. 15 is a block diagram of a spreading code generator which implements D-Q state transitions using a one-chip delay according to another embodiment of the present invention, in a CDMA communication system; 
     FIG. 16 is a block diagram of a D-Q spreading code generator according to an embodiment of the present invention, in a CDMA communication system; 
     FIG. 17 is a timing diagram of the D-Q spreading code generator according to an embodiment of the present invention, in a CDMA communication system; 
     FIG. 18 is a block diagram of a D-Q spreading code generator according to another embodiment of the present invention, in a CDMA communication system; 
     FIG. 19 is a block diagram illustrating a scheme for generating a spreading code by combining QPSK, DPSK and zero-crossing or hold according to an embodiment of the present invention, in a CDMA communication system; 
     FIG. 20A is a block diagram illustrating a Q-D-Z-D (QPSK-DPSK-ZCH-DPSK repeating sequence) spreading code generator according to an embodiment of the present invention, in a CDMA communication system; 
     FIG. 20B is a diagram illustrating symbol variations in terms of time with respect to the output of the decimator in FIG. 20A; 
     FIG. 21A is a block diagram illustrating a Q-D-Z-D spreading code generator according to another embodiment of the present invention, in a CDMA communication system; 
     FIG. 21B is a diagram illustrating symbol variations in terms of time with respect to an output of a decimator in FIG. 21 A; and 
     FIG. 22 is a flow chart illustrating a procedure for generating a spreading sequence according to an embodiment of the present invention, in a CDMA communication system. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. 
     A description will be made below regarding the state transition characteristics of a spreading code. For convenience, it will be assumed that the initial state of the spreading code is placed in the first quadrant. FIGS. 3 to  6  illustrate primitive state transitions, wherein FIG. 3 illustrates a zero-crossing; FIG. 4 illustrates a hold; FIG. 5 illustrates a +π/2-DPSK; and FIG. 6 illustrates a −π/2-DPSK. The above state transitions can be implemented in various methods. 
     Conventional QPSK spreading (hereinafter, referred to as “Q” for short) is memoryless; in other words, a transition to the present state can be made to every quadrant regardless of the previous state. For example, assuming that the previous state has the value (1,1) in the first quadrant, the present state can take on the same value (1,1) in the first quadrant, a value (−1,1) of the second quadrant, a value (−1−1) of the third quadrant or a value (1−1) of the fourth quadrant. 
     The zero-crossing phenomenon, occurring when spreading sequences C i  and C q  generated from a spreading code generator simultaneously vary in sign, and the hold phenomenon, occurring when neither sign of the spreading sequences change, cause a degradation of PAR performance. Therefore, in the CDMA communication system, it is possible to improve the PAR performance by suppressing the zero-crossing and hold phenomena of the spreading codes C i  and C q  during spreading. In one embodiment of the present invention, a first method is provided which alternately performs QPSK and DPSK phase shifts in order to suppress the zero-crossing and hold phenomena of the spreading sequence. Then, although every phase shift to every state can occur in QPSK as shown in FIGS. 3 to  6 , a DPSK phase shift is performed next, making it possible to prevent the zero-crossing and hold phenomena. A second method repeats a pattern of a QPSK, a DPSK, a zero-crossing or hold, and a DPSK phase shift for the spreading sequence. By using the above two methods, it is possible to prevent the zero-crossing and hold phenomenon of the spreading sequence, and suppress continuous zero-crossing or hold. 
     First, a description will be made regarding the first spreading sequence generation method according to an embodiment of the present invention. 
     FIG. 7 illustrates a scheme for generating a ±π/2-DPSK (hereinafter referred to as “D” for short) spreading sequence using an orthogonal code in a CDMA communication system. 
     Referring to FIG. 7, a multiplier  211  multiplies an orthogonal code OC 1 , by a PN code to generate a spreading code C i , and a multiplier  212  multiplies an orthogonal code OC 2  by the PN code to generate a spreading code C q . If the PN code is +1,−1,−1,+1,−1, and initial values of the orthogonal codes OC 1  and OC 2  are both +1, then the multiplier  211  outputs +1,−1,−1,+1,−1, and the multiplier  212  outputs +1,+1,−1,−1,−1. Therefore, the combined outputs (C i ,C q ) of the multipliers  211  and  212  become (+1,+1),(−1,+1),(−1,−1), (+1,−1),(−1,−1), so that the state transitions of the spreading codes are from an initial first quadrant, to the second quadrant, the third quadrant, the fourth quadrant and the third quadrant, causing a ±π/2 phase shift each time. 
     FIG. 8 illustrates a QPSK, π/2-DPSK spreading sequence generating scheme in a spread spectrum device for a CDMA communication system. 
     Referring to FIG. 8, a 2-decimator  222  decimates PN i , and a multiplier  223  multiplies an orthogonal code OC 2  by the output of the 2-decimator  222 . A multiplier  221  multiplies an orthogonal code OC 1  by PN q  to generate a spreading code C i , and a multiplier  224  multiplies the output of the multiplier  223  by PN q  to generate a spreading code C q . 
     FIG. 9 is a timing diagram of the QPSK, π/2-DPSK spreading sequence scheme in FIG.  8 . In FIG. 8, it is assumed that initial values of the orthogonal codes OC 1  and OC 2  are both +1. In FIG. 9, reference numeral  311  represents PN i , reference numeral  312  represents PN i  output from the 2-decimator  222 , reference numeral  313  represents the output of the multiplier  223 , reference numeral  314  represents PN q , reference numeral  315  represents the spreading sequence C i  output from the multiplier  221 , reference numeral  316  represents the spreading sequence C q  output from the multiplier  224 , and reference numeral  317  represents state transition of the spreading codes. 
     Referring to FIGS. 8 and 9, the output of the multiplier  221  and the output of the multiplier  224  constitute the spreading codes C i  and C q , respectively. From reference numerals  315 ,  316  and  317 , the spreading codes C i  and C q  become (+1,+1), (−1,+1), (−1,−1), (+1,−1), (+1,+1), (−1,+1), (+1,−1), (+1,+1), (−1,−1), (−1,+1), (+1,−1), (+1,+1), (+1,+1), (−1,+1), (+1,+1), (+1,−1), so that the state transitions of the spreading codes are from an initial state to the first quadrant (Q transition), the second quadrant (D transition), the third quadrant (Q transition), the fourth quadrant (D transition), the first quadrant (Q transition), the second quadrant (D transition), the fourth quadrant (Q transition), the first quadrant (D transition), the third quadrant (Q transition), the second quadrant (D transition), the fourth quadrant (Q transition), the first quadrant (D transition), the first quadrant (Q transition), the second quadrant (D transition), the first quadrant (Q transition) and the fourth quadrant (D transition). That is, the spreading codes generated by the spreading code generator of FIG. 8 make the repeated state transitions between QPSK and π/2-DPSK as shown by reference numeral  317  of FIG.  9 . 
     FIG. 10 is a timing diagram showing channelized data output from an orthogonal spreader and the output of a spreading code generator performing Q-D state transitions. In FIG. 10, reference numeral  411  represents channelized data output from an orthogonal spreader, which is input to a complex multiplier, and reference numeral  412  represents spreading codes output from a spreading code generator. Referring to FIG. 10, a spreading code making a QPSK state transition is input from the spreading code generator at the time when the channelized data is input to the complex multiplier, on the basis of a time reference. 
     FIG. 11 is a timing diagram showing channelized data output from an orthogonal spreader and the output of a spreading code generator performing D-Q state transitions. In FIG. 11, reference numeral  421  represents channelized data output from an orthogonal spreader, which is input to a complex multiplier, and reference numeral  422  represents spreading codes output from a spreading code generator. Referring to FIG. 11, a spreading code making a π/2-DPSK state transition is input from the spreading code generator at the time when the channelized data is input to the complex multiplier, on the basis of a time reference. 
     Therefore, it is possible to implement a spreading code generator for generating a D-Q spreading sequence of FIG. 11, using the same spreading code generator for generating Q-D spreading sequences in FIG. 10. A first implementing method is to delay or advance the channelized data by one chip on the basis of the time reference. 
     FIG. 12 is a timing diagram for the case where the channelized data is advanced by one chip on the basis of a time reference in FIG.  10 . In FIG. 12, reference numeral  431  represents one-chip advanced channelized data output from an orthogonal spreader, which is input to a complex multiplier, and reference numeral  432  represents spreading codes output from a spreading code generator. Referring to FIG. 12, a spreading code making a π/2-DPSK state transition is input from the spreading code generator at the time when the channelized data is input to the complex multiplier, on the basis of a time reference, thereby implementing a D-Q state transition scheme. 
     FIG. 13 is a timing diagram for the case where the channelized data is delayed by one chip on the basis of a time reference in FIG.  10 . In FIG. 13, reference numeral  441  represents one-chip delayed channelized data output from an orthogonal spreader, which is input to a complex multiplier, and reference numeral  442  represents spreading codes output from a spreading code generator. Referring to FIG. 13, a spreading code making a π/2-DPSK state transition is input from the spreading code generator at the time when the channelized data is input to the complex multiplier, on the basis of a time reference, thereby implementing D-Q state transitions. 
     As can be appreciated from the foregoing description, it is possible to implement D-Q state transitions using a spreading code generator which makes Q-D state transitions, by advancing or delaying the channelized data by one chip. 
     A second implementing method is to implement D-Q state transition by advancing or delaying an output of the Q-D spreading code generator by one chip. Herein, a description will be made regarding a method for delaying the output signal by one chip, which can be relatively easily implemented. 
     FIG. 14 illustrates a scheme for implementing D-Q state transition using a one-chip delay according to an embodiment of the present invention. 
     Referring to FIG. 14, an orthogonal spreader  511  receiving channel coded data, multiplies the coded data by an assigned orthogonal code to generate orthogonally spread channelized data. Herein, a Walsh code is used for the orthogonal code. A one-chip delay  515  delays the channelized data by one chip. A spreading code generator  513  generates spreading codes for spreading the channelized data. Herein, the spreading code generator  513  can generate a spreading sequence which repeats D-Q phase shift, and can also generate a spreading sequence which repeats Q-D-ZCH-D. A complex multiplier  512  complex multiplies the one-chip delayed channelized data by the spreading codes to generate spread transmission signals. Here, PN codes can be used for the spreading codes. The PN codes have a rate equal to the chip rate and can have a value of +1 and −1. A lowpass filtering and modulation part  514  lowpass filters the spread signals output from the complex multiplier  512  and then modulates the lowpass filtered signals into RF signals. A QPSK modulator can be used for the modulator. 
     In FIG. 14, the one-chip delay  515  delays the channelized data by one chip to provide the one-chip delayed channelized data to the complex multiplier  512 . Therefore, the spreading code generator  513  can implement either D-Q state transition or Q-D-ZCH-D state transition. 
     FIG. 15 illustrates a scheme for implementing D-Q state transition or Q-D-ZCH-D state transition using one-chip delay according to another embodiment of the present invention. 
     Referring to FIG. 15, an orthogonal spreader  511  receiving channel coded data, multiplies the coded data by an assigned orthogonal code to generate orthogonally spread channelized data. Herein, a Walsh code is used for the orthogonal code. A spreading code generator  513  generates spreading codes for spreading the channelized data. A one-chip delay  516  delays the spreading codes output from the spreading code generator  513  by one chip. A complex multiplier  512  complex multiplies the channelized data by the onechip delayed spreading codes to generate spread transmission signals. Here, PN codes can be used for the spreading codes. The PN codes have a rate equal to the chip rate and can have a value of +1 and −1. In the embodiment, the PN codes are assumed to have a value of +1 and −1. A lowpass filtering and modulation part  514  lowpass filters the spread signals output from the complex multiplier  512  and then modulates the lowpass filtered signals into RF signals. A QPSK modulator can be used for the modulator. 
     In FIG. 15, the one-chip delay  516  delays the output of the spreading code generator  513  by one chip to provide the one-chip delayed spreading codes to the complex multiplier  512 . Therefore, it is possible to implement either a D-Q state transition scheme or a Q-D-ZCH-D state transition scheme using a Q-D spreading code generator. 
     Alternatively, it is also possible for the spreading code generator  513  to implement D-Q state transition without using the one-chip delay shown in FIGS. 14 and 15. This can be done by delaying, by one chip, the output of the 2-decimator  812  in the conventional Q-D spreading code generator of FIG.  8 . 
     FIG. 16 illustrates a D-Q spreading code generator according to another embodiment of the present invention. 
     Referring to FIG. 16, a 2-decimator  612  decimates PN i , and a delay  615  delays the output of the 2-decimator  612  by one chip. The delay time of the delay  615  can be set to another predetermined chip time rather than a single chip. A multiplier  613  multiplies orthogonal code OC 2  by the output of the delay  615 . A multiplier  611  multiplies an orthogonal code OC 1  by PN q  to generate a spreading code C i , and a multiplier  614  multiplies the output of the multiplier  613  by PN q  to generate a spreading code C q . 
     FIG. 17 is a timing diagram of the QPSK, π/2-DPSK spreading sequence generating scheme of FIG.  16 . In FIG. 17, it is assumed that the initial values of the orthogonal codes OC 1  and OC 2  are both +1. In FIG. 17, reference numeral  711  represents PN i , reference numeral  712  represents PN i  output from the 2-decimator  612 , reference numeral  713  represents delayed PN i  output from the delay  615 , reference numeral  714  represents the output of the multiplier  613  which multiplies the orthogonal code OC 2  by the output of the delay  615 , reference numeral  715  represents PN q , reference numeral  716  represents the spreading code C i  output from the multiplier  611  which multiplies PN q  by the orthogonal code OC 1 , reference numeral  717  represents the spreading code C q  output from the multiplier  614  which multiplies PN q  by the output of the multiplier  613 , and reference numeral  718  represents the state transitions of the spreading codes. 
     In FIG. 17, it is assumed that initial values of the orthogonal codes OC 1  and OC 2  are both +1. Referring to FIGS. 16 and 17, the output of the multiplier  611  and the output of the multiplier  614  constitute the spreading codes C i  and C q , respectively. As shown by reference numeral  718 , the spreading codes C i  and C q  output from the multipliers  611  and  614  become (+1,−1), (−1,−1), (−1,+1), (+1,+1), (+1,−1), (−1,−1), (+1,+1), (+1,−1), (−1,+1), (−1,−1), (+1,+1), (+1,−1), (+1,−1), (−1,−1), (+1,−1).Therefore, for the case of FIG. 16, the state transitions of the spreading codes (C i ,C q ) are from an initial state to the fourth quadrant (Q transition), the third quadrant (D transition), the second quadrant (Q transition), the first quadrant (D transition), the fourth quadrant (Q transition), the third quadrant (D transition), the first quadrant (Q transition), the fourth quadrant (D transition), the second quadrant (Q transition), the third quadrant (D transition), the first quadrant (Q transition), the fourth quadrant (Q transition), the fourth quadrant (D transition), the third quadrant (Q transition) and the fourth quadrant (D transition). It is noted that the state transitions alternate between π/2-DPSK and QPSK on the basis of the time reference. 
     FIG. 18 illustrates a scheme for repeatedly performing QPSK and π/2-DPSK state transition by combining PN sequences without using orthogonal codes according to another embodiment of the present invention. In FIG. 18, signals A represent QPSK signals, which are PN i  and PN q  being output without phase shift, and signals D represent π/2-DPSK signals. 
     Referring to FIG. 18, a delay  811  delays a previous spreading code C i , and a delay  821  delays a previous spreading code C q . A multiplier  815  multiplies a PN q  code by “−1” to invert the PN q  code. A multiplier  814  multiplies the previous spreading code C q  output from the delay  821  by the output of the multiplier  815 . A first selector  812  receiving the PN i  code as a first signal A and the output of the multiplier  814  as a second signal D, selects one of the input signals A and D under the control of a controller  831 . A multiplier  824  multiplies the previous spreading code C i  output from the delay  811  by the PN q  code. A second selector  822  receiving the PN q  code as a first signal A and the output of the multiplier  824  as a second signal D, selects one of the input signals A and D under the control of the controller  831 . Here, the first signals A represent QPSK signals, which are PN i  and PN q  being output without phase shift, and second signals D represent π/2-DPSK signals. 
     In operation, the controller  831  controls the first and second selectors  812  and  822  to sequentially select the signals A and D in a predetermined order. It is also possible to implement various spreading methods having the lower PAR while minimizing degradation of BER performance, by combining QPSK and π/2-DPSK. In the embodiment of FIG. 18, since the input PN i  and PN q  are output as they are (i.e., without phase shift), QPSK is first performed to output the values corresponding to one of the first to fourth quadrants (+1,+1), (−1,+1), (−1,−1), (+1,−1), and next, π/2-DPSK is performed to shift the previous outputs by ±π/2 phase. This can be-done by sequentially repeatedly selecting the signals A and D using the first and second selectors  812  and  822 . The PN i  and PN q  codes in FIG. 18 can be equal to the conventional PN spreading codes. 
     FIG. 19 illustrates a scheme for generating spreading codes by combining QPSK, π/2-DPSK and zero-crossing or hold according to an embodiment of the present invention. In FIG. 19, signals A represent QPSK signals, which are PN i  and PN q  being output without phase shift, signals B and D represent π/2-DPSK signals, and signals C represent ZCH signals. 
     Referring to FIG. 19, a delay  911  delays a previous spreading code C i , and a delay  921  delays a previous spreading code C q . A multiplier  913  multiplies a PN i  code by the previous spreading code C i  output from the delay  911 . A multiplier  915  multiplies a PN q  code by “−1” to invert the PN q  code. A multiplier  914  multiplies the previous spreading code C q  output from the delay  921  by the output of the multiplier  915 . A first selector  912  receiving the PN i  code as a first signal A, the output of the multiplier  913  as a third signal C and the output of the multiplier  914  as second and fourth signals B and D, selects one of the input signals A, B, C and D under the control of a controller  931 . 
     A multiplier  923  multiplies the PN i  code by the previous spreading code C q  output from the delay  921 . A multiplier  924  multiplies the previous spreading code C i  output from the delay  911  by the PN q  code. A second selector  922  receiving the PN q  code as a first signal A, the output of the multiplier  923  as a third signal C and the output of the multiplier  924  as second and fourth signals B and D, selects one of the input signals A, B, C and D under the control of the controller  931 . Here, the first signals A represent QPSK signals, which are PN i  and PN q  being output without phase shift, the second and fourth signals B and D represent π/2-DPSK signals, and the third signals C represent ZCH signals. 
     In operation, the controller  931  controls the first and second selectors  912  and  922  to sequentially select the signals A, B, C and D in a predetermined order. It is also possible to implement various spreading methods having the lower PAR while minimizing degradation of BER performance, by combining QPSK, ZC, π/2-DPSK, and HOLD (hereinafter, referred to as “H” for short). For example, there may be a first spreading method which sequentially uses QPSK-π/2-DPSK-ZCH-π/2-DPSK (hereinafter, referred to as Q-D-Z-D), a second spreading method which uses HOLD-π/2-DPSK, and a third spreading method which uses ZC-π/2-DPSK. In addition, it is also possible to use a spreading method given by combining the above first, second and third spreading methods. This method can be implemented through the following embodiment. 
     A description will be now made regarding an operation of generating spreading codes according to Q-D-Z-D in FIG.  19 . In this method, since the input PN i  and PN q  are output as they are (i.e., without phase shift), QPSK is first performed to output the values corresponding to one of the first to fourth quadrants (+1,+1), (−1,+1), (−1,−1), (+1,−1); next, π/2-DPSK is performed to shift the previous outputs by ±π/2 phase; subsequently, ZCH is performed to output either the same values as the previously output values or change signs of both the previously output values; and finally, ±π/2-DPSK is performed. This can be done by sequentially repeatedly selecting the signals A, B, C and B using the first and second selectors  912  and  922 . The PN i  and PN q  codes in FIG. 19 can be equal to the conventional PN spreading codes. 
     In addition, a description will be made regarding another state transition occurring in FIG.  19 . First, QPSK-ZCH can be performed by alternating between the signals A and C using the first and second selectors  912  and  922 , and ZCH-QPSK can be performed by alternating between the signals C and A using the first and second selectors  912  and  922 . It will be assumed herein that the same spreading codes are generated, when the sequences of outputting spreading codes are different as in the QPSK-ZCH and ZCH-QPSK, i.e, when there occurs a one-chip time delay. ZCH-π/2-DPSK (or π/2-DPSK-ZCH) can be performed by alternating between the signals C and B (or signals B and C) using the first and second selectors  912  and  922 ; QPSK-π/2-DPSK-ZCH-π/2-DPSK can be performed by repeating the pattern of selecting the signals A, B, C and D using the first and second selectors  912  and  922 ; π/2-DPSK-QPSK-ZCH-π/2-DPSK can be performed by repeating the pattern of selecting the signals B, A, C and D using the first and second selectors  912  and  922 ; and QPSK-ZCH-QPSK-π/2-DPSK can be performed by repeating the pattern of selecting the signals A, C, A and B using the first and second selectors  912  and  922 . 
     FIG. 20A illustrates a scheme for generating spreading sequences according to Q-D-Z-D. Referring to FIG. 20A, a 4-decimator  1011  4-decimates a PN 1  code and a 4-decimator  1021  4-decimates a PN 2  code. In this embodiment, “decimating” means that symbols have the same value for a predetermined chip duration. A detailed description will be made below regarding the output of the decimators. 
     FIG. 20B illustrates symbol variation in terms of time with respect to the decimation. In FIG. 20B, reference numeral  1115  represents the 4-decimation result when PN i  is +1 in the 4-decimator  1011  of FIG. 20A, and reference numeral  1117  represents the 4-decimation result when PN 2  is −1 in the 4-decimator  1021  of FIG.  20 A. 
     A multiplier  1013  of FIG. 20A multiplies the output of a multiplier  1012  by the PN 3  code to output a spreading code C i , and a multiplier  1023  multiplies the output of a multiplier  1022  by the PN 3  code to output a spreading code C q . With regard to operation of the spreading code generating scheme of FIG. 20A, the PN 1  and PN 2  codes generated as shown by reference numerals  1111  and  1113  of FIG. 20B decimated by the decimators  1011  and  1021  as shown by reference numerals  1115  and  1117 , and then multiplied by orthogonal codes OC 1  and OC 2  in the multipliers  1012  and  1022 . Thereafter, the outputs of the multipliers  1012  and  1022  are multiplied by the PN 3  code in the multipliers  1013  and  1023 , outputting the final spreading codes C i  and C q . Once the PN 1  and PN 2  codes are determined, they are maintained for  4  chips. The PN 1  and PN 2  codes output from the decimators  1011  and  1021  are multiplied by the corresponding orthogonal codes OC 1  and OC 2  in the multipliers  1012  and  1022 , respectively. At this point, QPSK is performed at the first chip time. If it is assumed that an output at the previous chip time exists in the first quadrant (+1,+1), an output at the second chip time will occur in the second quadrant (−1,+1) or the fourth quadrant (+1,−1), which corresponds to π/2-DPSK. An output at the third chip time occurs in the second quadrant (−1,+1) or the fourth quadrant (+1,−1) by the orthogonal codes and the PN 3  code, which corresponds to ZCH. At the fourth chip time, an output occurs in the first quadrant (+1,+1) or the third quadrant (−1,−1), which corresponds to π/2-DPSK. 
     FIG. 21A illustrates another scheme for generating spreading codes according to Q-D-Z-D. 
     Referring to FIG. 21A, a multiplier  1211  multiplies a PN i  code by an orthogonal code OC 1 , and a multiplier  1221  multiplies the PN i  code by an orthogonal code OC 2 . A serial-to-parallel (S/P) converter  1231  converts a serial PN q  code to parallel data. A 2-decimator  1241  decimates the PN q  code output from the S/P converter  1231  to output odd-numbered PN q  code values, and a 2-decimator  1251  decimates the PN q  code output from the S/P converter  1231  to output even-numbered PN q  code values. 
     A detailed description will be made below regarding the output of the S/P converter  1231  and the outputs of the 2-decimators  1241  and  1251  with reference to FIG. 21B which illustrates symbol variation in terms of time. With regard to the outputs of the 2-decimators  1241  and  1251 , the odd-numbered PN q  code values are changed as shown by reference numeral  1314  of FIG.  21 B and the even-numbered PN q  code values are changed as shown by reference numeral  1315  of FIG. 21B. A multiplier  1212  of FIG. 21A multiplies the output of the decimator  1241  by the output of the multiplier  1211  to generate a spreading code C i , and a multiplier  1222  multiplies the output of the decimator  1251  by the output of the multiplier  1221  to generate a spreading code C q . Although the scheme of FIG. 20A uses three PN codes, the scheme of FIG. 21A can perform the same function using only two PN codes. 
     Referring to FIGS. 21A and 21B, the PN i  code is multiplied by the orthogonal codes OC 1  and OC 2  in the multipliers  1211  and  1221 , respectively. Meanwhile, the PN q  code, after passing the S/P converter  1231  and the 2-decimators  1241  and  1251 , is multiplied by the outputs of the multipliers  1211  and  1221  in the multipliers  1212  and  1222  to be output as the spreading codes C i  and C q . The spreading code generator of FIG. 21A uses the PN q  code for the PN 1  and PN 2  codes of FIG. 20A, and uses the PN i  code for the PN 3  code of FIG.  20 A. 
     FIG. 22 is a flow chart illustrating a method for preventing an increase in PAR not only when a spreading code undergoes zero-crossing (ZC) but also when the spreading code maintains the same value (i.e., HOLD). In FIG. 22, to prevent the zero-crossing and the hold of the spreading codes PN i  and PN q , upon occurrence of a ZCH, the phase of the spreading codes is shifted by +π/2 (or −π/2), and otherwise, the PN i  and PN q  are output as they are. This method is a hybridized method of π/2-DPSK and QPSK, and can exclude ZC and HOLD. 
     Referring to FIG. 22, PN code values are input in step  1411 , and PN i  and PN q  values are compared with previous C i  and C q  values in step  1412 . When C i ≠PN i  and C q ≠PN q , the procedure proceeds to step  1413  where a phase of the spreading codes is shifted by +π/2. However, when any of the PN i  and PN q  values is equal to the corresponding previous C i  and C q  values, the procedure goes to step  1415 . When C i =PN i  and C q =PN q  in step  1415 , the procedure proceeds to step  1414  where a phase of the spreading codes is shifted by −π/2. However, when any of the PN i  and PN q  values is not equal to the corresponding previous C i  and C q  values, the procedure goes to step  1416  where the PN i  value is output as C i  unaltered, and the PN q  value is output as C q  unaltered. 
     As described above, the novel spreading sequence generating scheme generates a spreading sequence which makes repeated state transitions between π/2-DPSK and QPSK, thereby to reduce PAR. 
     While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.