Abstract:
An analog joystick interface system for overcoming the deficiencies of the conventional analog joystick interface by supporting positional tracking in both a legacy and an enhanced mode. In the legacy mode, the host calculates the relative physical orientation of a positional grip of an analog joystick by relying upon continuous polling techniques. In the enhanced mode, a watch dog timer relieves the host of the need to continuously poll by directly providing the host with positional data concerning the relative physical orientation of the positional grip. The ability of the joystick interface to provide both the legacy and enhanced modes ensures that compability issues concerning the legacy DOS-based software applications and CPU allocation problems associated with continuous polling are resolved without considerably increasing cost or complexity of the joystick interface.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a system and method for interfacing an analog joystick with a digital computer. In particular, the present invention relates to a multiple mode joystick interface for providing an interface with digital characteristics to an analog joystick. 
     2. Description of Background Art 
     Many users rely upon electronic computer peripherals as input devices for computer software applications. For example, with regard to word processing software, a conventional keyboard often is used to input text data. In the operation of a graphic design program, a computer mouse or a writing tablet is used to input graphics. With game software, a joystick system usually is used to input two-dimensional positional movement. 
     FIG. 1 illustrates a conventional joystick system 100 for translating these two-dimensional positional movements into digital data. The joystick system 100 includes two analog joysticks 105a and 105b, an analog joystick interface 102 and a host 180. For simplicity, however, only analog joystick 105a will be discussed in detail. Those skilled in the art will recognize that analog joystick 105b operates in a similar fashion as analog joystick 105a. 
     The analog joystick 105a includes a positional grip 103, a first potentiometer 107 and a second potentiometer 109. The positional grip 103 pivots within a two-dimensional plane having an X-axis and a Y-axis. The first potentiometer 107 is physically coupled to the X-axis of the positional grip 103. The second potentiometer 109 is physically coupled to the Y-axis of the positional grip 103. Depending upon the direction a user moves the positional grip 103 within this two-dimensional plane, the positional grip 103 alters the resistance levels of either the first potentiometer 107, the second potentiometer 107 or both. For example, by moving the positional grip 103 along the X-axis to the left of the user, the resistance value of the first potentiometer 107 increases. If the positional grip 103 is moved along the X-axis to the right of the user, the resistance value of the first potentiometer 107 decreases. The second potentiometer 109 has a similar proportional relationship to the movements of the positional grip 103 along the Y-axis. 
     The analog joystick interface 102 includes four charging circuits 101a-d and a positional marker register 160. Each of the charging circuit 101a-d includes an input and an output. The input of the charging circuit (X1) 101a for the X-axis of the first analog joystick 105a is electrically coupled to the first potentiometer 107. The input of charging circuit (Y1) 101b for the Y-axis of the first analog joystick 105a is electrically coupled to the second potentiometer 109. To avoid unnecessary repetition, the charging circuit 101a for the X-axis of the analog joystick 105a will be the focus of the remaining discussion. Those skilled in the art will recognize that charging circuits 101b-101d operate in a similar fashion as charging circuit 101a operates with regard to the X-axis of the first analog joystick 105a. 
     Charging circuit 101a includes a charger 110, a comparator 120 and a reference circuit 115. The charger 110, which is a capacitor, includes a first input, a second input, and a first output. The first input of the charger 110 is electrically coupled to the first potentiometer 107, thereby creating a conventional resistor/capacitor (&#34;RC&#34;) circuit having a conventional variable charging characteristic. As the resistance of the first potentiometer 107 is varied, the voltage V p  across the first potentiometer changes, thereby proportionately altering the charging cycle time t RC  for the charger 110 to raise the charger voltage level V RC  from 0 volts to a predefined reference voltage level V ref . 
     The comparator 120 includes a first input, a second input and a first output. The first input is electrically coupled to the first output of the charger 110, which transmits V RC . The second input is electrically coupled to the reference circuit 115, which transmits V ref . The first output of the comparator 120 is electrically coupled to both the memory cell (&#34;X1&#34;) (not shown) in the positional marker register 160, which corresponds to the X-axis of the analog joystick 105a, and the second input of the charger 110. The positional marker register 160 is a four memory cell register with the first two memory cells (X1) and (Y1) (not shown) representing the X- and Y-axis of the first joystick 105a and the latter two memory cells (X2) and (Y2) (not shown) representing the X- and Y-axis of the second analog joystick 105b. 
     When the first input of the comparator 120 receives a V RC  voltage level, which matches the V ref  voltage level of the second input, the comparator 120 transmits a match signal to the memory cell (X1) of the positional marker register 160 and to the second input of the charger 110. In the positional marker register 160, the match signal inverts the memory cell (X1) from a &#34;1&#34; logic state to a &#34;0&#34; logic state. With regard to the charger 110, the match signal grounds the charger 110 (e.g. lowers V RC  to approximately 0 volts) by turning on a transistor (not shown), which is electrically coupled between the charger 110 and electrical ground. Once reset, the charger 110 will again recharge V RC  to V ref , however, with a new charging rate, which is relative to the new physical orientation of the positional grip 103. 
     The host 180 is electrically coupled to the positional marker register 160. During the continuous recharging of the charger 110 at different charging rates, the host 180 continuously polls each memory cell to detect the moment that the logic state of one of the memory cells is inverted from the &#34;1&#34; to the &#34;0&#34; logic state. When the host 180 detects such a logic state inversion in a memory cell, such as memory cell (X1), the host 180 will record the relative time, which has elapsed since the last time that the memory cell (X1) was inverted to the &#34;0&#34; logic state. The host then sets the memory cell (X1) back to its original &#34;1&#34; logic state and the charger (X1) again begins to raise V RC  from approximately 0 volts to V ref . 
     This relative period of time between inversions of the logic state directly correlates to the charging cycle time t RC  for the charging circuit (X1) 101a raising the charging voltage V RC  from approximately 0 volts to V ref . To calculate the relative position of the positional grip 103 along the X-axis, the host 180 compares this t RC  value with the calibrated t RC  value for the positional grip 103 in a center position t center , a left-most position t left , and a right-most position t right . 
     This method of calculating the relative position of the positional grip 103, however, requires that the host 180 poll the positional marker register 160 without interruption. If the host 180 is interrupted, the charging cycle time t RC  will become inaccurate, thereby resulting in the host 180 generating incorrect calculations of the relative physical orientation of the positional grip 103. 
     As operating systems, such as Windows 95, are transformed into preemptive multitasking operating systems, such as Windows NT, which continuously switch between applications, problems associated with interruptions in the continuous polling of the host 180 become inherent. To rectify this problem, a software technique called &#34;spin lock&#34; is used to prevent the operating system from switching to another application until the designated application completes its operation. 
     This solution to the continuous polling problem, however results in a new difficulty, the reduction of available CPU bandwidth for other applications. Spin lock originally was designed to provide a synchronization mechanism for protecting shared data or resources from simultaneous access by software routines, which are concurrently executed in a preemptive multitasking operating system. When spin lock is used in such a context, CPU bandwidth is partially monopolized for relatively short periods of time (e.g. approximately 25 microseconds). In the continuous polling context, however, spin lock is used to calculate the movements of the positional grip 103 over numerous clock cycles (e.g. periods of time between 500 microseconds-1 millisecond), which is between 20 and 40 times longer than spin lock was designed to operate. Such relatively long periods of time unfortunately result in approximately 5-10% of the overall CPU bandwidth allocation remaining unusable for as long as the host 180 is continuously polling the positional marker register 160. 
     One attempt to avoid this overuse of CPU bandwidth is to avoid the cause of the problem, the need for the host 180 to continuously poll the positional marker register 160. In place of the conventional analog joystick system 100, a conventional digital joystick system, which relies upon a positional time register to record positional data, is used. Typically, the positional time register is an index register. The digital joystick system includes a digital joystick and a digital joystick interface. This design, however, requires both proprietary software protocols and proprietary hardware. For example, in addition to the digital joystick including potentiometers, the design also must utilize both an analog-to-digital (&#34;A/D&#34;) converter and a parallel-to-serial converter. The A/D converter translates the voltage V p  across the potentiometers of the joystick into digital data. The parallel-to-serial converter converts this digital data into a proprietary serial communication protocol, which then is transmitted to the digital joystick interface. To decode the transmitted encoded digital data, the digital joystick interface must rely upon a serial-to-parallel converter. The decoded positional data then is stored in a positional time register, which is accessed without having the host continuously poll. 
     Even though this system resolves the problems associated with the analog joystick system, the proprietary nature of the digital joystick system still results in at least two disadvantages. First, this alternative proprietary digital design costs more than the conventional analog system 100. Secondly, legacy DOS-based applications, which were programmed to only access positional data from the positional marker register 160 in the analog system 100 will not be able to operate in this digital environment. With positional data only stored in the positional time register, legacy DOS-based software applications will have no means of accessing the positional data. 
     What is needed is a system and method for interfacing with an analog joystick, which maintains the advantages of the digital joystick system, but without compromising the compatibility with the legacy DOS-based software applications. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the deficiencies of the conventional art by providing an analog joystick system and method that supports positional tracking of a positional grip of an analog joystick in both a legacy (conventional analog) mode and an enhanced (digital) mode. The joystick interface preferably comprises a plurality of charging modules, a positional marker register, and an enhancement module. Each of the plurality of charging modules includes a charging circuit, a circuit interface, and a transitioner. The enhancement module further includes a watch dog timer and a plurality of positional time registers. 
     In the legacy mode, by inverting a memory cell within the positional marker register to a &#34;0&#34; logic state at a predefined charging circuit reference voltage level, the charging interface marks the completion of a full charging cycle for the corresponding charging circuit. A host, which is continuously polling the positional marker register, then both resets the memory cells in the &#34;0&#34; logic state back to a &#34;1&#34; logic state and uses the relative period of time between consecutive &#34;0&#34; logic state inversions to calculate the charging cycle time t RC  of the charging circuit. The host then translates this t RC  value into a digital representation of the relative physical orientation of the positional grip of the analog joystick by comparing the t RC  value with charging cycle times values of calibrated positions of the positional grip. 
     In the enhanced mode, by directly providing the host with t RC  values of the charging circuits, the watch dog timer relieves the host of the need to continuously poll the positional marker register. Unlike the legacy mode, the host in the enhanced mode no longer has to calculate relative t RC  values. Rather, the host directly polls the plurality of positional time register where the t RC  values, which are generated by the watch dog timer, are latched and stored. 
     The ability of the joystick interface to provide both the legacy and enhanced modes ensures that compatibility issues concerning the legacy DOS-based software applications and the CPU bandwidth allocation problems associated with continuous polling are resolved without considerably increasing the cost or complexity of the joystick interface. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates an analog joystick in conjunction with an analog joystick interface in a conventional design. 
     FIG. 2 illustrates a high level view of the present invention. 
     FIG. 3 illustrates a detailed view of the charging interface of the present invention. 
     FIG. 4 illustrates a detailed view of the enhancement module of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention addresses the inherent CPU usage problems associated with the conventional joystick interface by supporting a legacy (conventional analog)/enhanced (digital) mode approach. In the enhanced mode, by relying upon an enhancement module to supply the host with the necessary positional information, the present invention circumvents the need for the host to continuously poll the positional marker register. In the legacy mode, to ensure that legacy DOS-based software products can obtain the necessary positional information from the positional marker register, the present invention still continuously polls the positional marker register. 
     Such an inventive analog joystick interface system 200 according to the present invention is shown in FIG. 2. The preferred embodiment of the analog joystick interface system 200 comprises at least one conventional analog joystick 105a, a host 280, and a joystick interface 210. In this embodiment, the host 280 is a software application executed by a central processing unit (&#34;CPU&#34;) of an Intel-based personal computer. The joystick interface 210 includes a charging interface 250, a positional marker register 260, and an enhancement module 240. 
     The positional marker register 260 is at least two memory cell register. Each memory cell (not shown) within the positional marker register 260 is either in the &#34;0&#34; or the &#34;1&#34; logic state. In this embodiment, the first memory cell (X1) represents the X-axis of the joystick 105a and the second memory cell (Y1) corresponds to the Y-axis of the joystick 105a. In a default state, each of these memory cells is set to the &#34;1&#34; logic state. When the voltage level V RC  of the charging interface 250, which corresponds to one of the two axes, reaches the reference voltage level V ref , the charging interface 250 changes the logic state of the memory cell corresponding to that axis from the &#34;1&#34; to the &#34;0&#34; logic state. 
     When the system is set to the legacy mode, the host 280 continuously polls each memory cell within the positional marker register 260 to detect each change in the memory cell to the &#34;0&#34; logic state. As soon as a specific memory cell is inverted to the &#34;0&#34; logic state, the host 280 records the elapsed time between the current logic state inversion in that cell and the most recent previous inversion of the logic state in that cell. Once t RC  is recorded, the host 280 resets the memory cell back to the &#34;1&#34; logic state and awaits the next inversion of the memory cell to the &#34;0&#34; logic state. 
     These relative periods of time between inversions of the logic state of the memory cell directly correspond to the charging cycle time t RC , which elapsed for the charging interface 250 to increase the voltage level V RC  for a specific axis from 0 to V ref . By comparing this relative t RC  value to calibrated charging cycle values, the host 280 can calculate the relative positional orientation of the positional grip (not shown). 
     In the enhanced mode, the enhancement module 240 eliminates the need for the host 280 to have to continuously poll the positional marker register 260 and calculate relative t RC  values. As will be discussed in more detail with regard to FIG. 4, the enhancement module 240 directly provides the calculated charging times t RC  to the host 280. 
     The charging interface 250, as illustrated in FIG. 3, comprises a charging module 301a for the X-axis and a charging module 301b for the Y-axis of the analog joystick 105a. As one skilled in the art is well aware, the charging interface 250 has the capability to include more charging modules for accommodating the X- and Y-axes of additional analog joysticks, which could be attached to the system 200. To maintain simplicity, however, throughout FIGS. 2-5, only the system and method associated with the X-axis of analog joystick 105a will be discussed. With regard to the Y-axis of the joystick 105a and the X- and Y-axes of additional analog joysticks, those skilled in the art will recognize that the joystick interface 210 will interact with regard to these axes in a similar fashion as the interface 210 interacts with the X-axis of the joystick 105a. 
     The charging module 301a for the X-axis of analog joystick 105a includes a transitioner 320a, a charging circuit 101a, and a circuit interface 310a. The transitioner 320a, which in this embodiment is a series of logic gates, includes three inputs and two outputs. The first input is electrically coupled to a first output of the host 280. The second input is electrically coupled to a first output of the memory cell (X1) (not shown) in the positional marker register 260. The first output of the transitioner 320a is electrically coupled to a first input in the circuit interface 310a. 
     To initiate the legacy mode, the first output of the host 280 transmits a legacy mode signal S legacy  to the first input of the transitioner 320a, which results in the first output of the transitioner 320a transmitting a start signal S start  in the &#34;1&#34; logic state to the first input of the circuit interface 310a. The first output of the circuit interface 310a responds to the receipt of the &#34;1&#34; logic state by setting the memory cell (X1) in the positional marker register 260 to the &#34;1&#34; logic state. At approximately the same time, the charging circuit 101a begins to charge at a charging rate, which is directly proportional to the resistance value of the X-axis potentiometer (not shown) in the analog joystick 105a. 
     When the second input of the transitioner 320a detects the presence of the &#34;1&#34; logic state in the memory cell (X1), the first output of the transitioner 320a transmits S start  in the &#34;0&#34; logic state to the first input of the circuit interface 310a. A second input of the circuit interface 310a is electrically coupled to a first output of the charging circuit 101a. A first output of the circuit interface 310a is electrically coupled to the memory cell (X1) of the positional marker register 260. In this embodiment, the circuit interface 310a includes logic circuitry and an RS flip flop. The S gate of the RS flip flop corresponds to the first input of the circuit interface 310a. The R gate corresponds to the second input of the circuit interface 310a. 
     Once the charging circuit voltage V RC  matches V ref , the first output of the charging circuit 101a transmits a match signal S match , which is in the &#34;1&#34; logic state, to the second input of the circuit interface 310a. Based upon conventional RS flip flop logic, by receiving S match  in the &#34;1&#34; logic state at the second input of the circuit interface 310a and S start  in the &#34;0&#34; logic state signal at the first input of the circuit interface 310a, the first output of the circuit interface 310a switches the memory cell (X1) in the positional marker register 260 to the &#34;0&#34; logic state. 
     A second output of the circuit interface 310a is electrically coupled to a first input of the charging circuit 101a. In order to reset the charging circuit 101a, the second output of the circuit interface 310a transmits a grounding signal S ground  to the first input of the charging circuit 101a. As is well known in the art, the receipt of the S ground  by the charging circuit 101a results in a transistor (not shown), which is connected between ground and the charging circuit 101a, turning on and lowering V RC  to approximately 0 volts. 
     Once reset, the charging circuit 101a, which includes a second input that is electrically coupled to the analog joystick 105a, recharges V RC  at a new charging rate, which is proportional to the resistive value of the potentiometer relative to the X-axis orientation of the positional grip (not shown) within the analog joystick 105a. As soon as V RC  again matches V ref , the first output of the charging circuit 101a again transmits S match  in the &#34;1&#34; logic state to the second input of the circuit interface 310a, which in turn results in the first output of the circuit interface 310a again switching the logic state in the memory cell (X1) of the positional marker register 260 to the &#34;0&#34; logic state. 
     The host 280, which continuously polls the positional marker register 260, detects and records the relative time period, between inversions of the memory cell (X1) to the &#34;0&#34; logic state. After each recordation of the relative time period, the host 280 sets the memory cell (X1) in the positional marker register 260 back to the &#34;1&#34; logic state. This relative period of time between detections of the &#34;0&#34; logic state is an approximation of the charging cycle time t RC , which has elapsed in recharging V RC  from 0 volts to V ref . By comparing this t RC  value with calibrated charging cycle values for pre-defined physical orientations of the positional grip, the host 280 can calculate the relative position of the positional grip (not shown) within the joystick 105a. The use of continuous polling in this manner ensures that, while operating with the present invention, the large installed base of legacy DOS-based software applications still can obtain the necessary positional information from the positional marker register 260. As one skilled in the art can see from the discussion relating to the relative positional orientation of the positional grip along the X-axis, relative movements along different axes (whether the Y-axis of the joystick 105a or the X- and Y-axis of a second joystick 105b) also can be calculated in a similar manner as that used for the X-axis. 
     The enhancement module 240, as illustrated in FIG. 4, includes a plurality of positional time registers 450a-b and a watch dog timer 430. In this embodiment, the watch dog timer 430 is a 16 bit clock operating at 500 kHz and the plurality of positional time registers 450a-b are index registers. The watch dog timer 430 includes four inputs as well as two outputs. The first and second inputs are electrically coupled to the second and third outputs of the host 280, respectively. The third and fourth inputs are electronically coupled to transitioners 320a and 320b (not shown), respectively. 
     To initiate the enhanced mode, the second output of the host 280 transmits an enhanced mode signal S enhanced  to the first input of the watch dog timer 430. The third output of the host 280 transmits a S threshold  signal, which defines the maximum time value t threshold  for the watch dog timer 430, to the second input of the watch dog timer 430. Upon receipt of S enhanced , the watch dog timer 430 begins to incrementally increase the watch dog time t watch  until it reaches a maximum time value t threshold . To ensure proper calculation for the charging cycle time t RC  of the charging circuit 301a, the host 280 sets t threshold  to a value larger than the theoretical maximum charging cycle time t RCmax . When t watch  reaches t threshold , the first output of the watch dog timer 430 transmits a roll-over signal S roll  to the third input of the transitioner 320a. The S roll  signal results in the second output of the transitioner 320a transmitting a reset signal S reset  to the third input of the watch dog timer 330. Upon receipt of S reset , the watch dog timer 330 resets t watch  and begins to recount from zero. 
     At approximately the same time, the first output of the transitioner 320a also transmits a new start signal S start  in the &#34;1&#34; logic state to the first input of the circuit interface 310a. As previously discussed in FIG. 3, the circuit interface 310a responds to receipt of S start  by initiating a new charging cycle for the charging circuit 101a, which is proportional to the current resistance value of the X-axis potentiometer (not shown) in the analog joystick 105a. Unlike the legacy mode, however, the watch dog timer 430 and not the host 280 serves as a direct timer for the charging cycle time t RC . This reallocation of the timing process to the watch dog timer 430 relieves the host 280 from having to continuously poll the positional marker register 260, which inherently monopolizes part of the CPU bandwidth. 
     In the enhanced mode, when V RC  matches V ref , the third output of the circuit interface 310a, which is electrically coupled to the positional time register (X1) 450a, transmits a load signal S load  to the positional time register (X1) 450a. Upon receipt of S load , the positional time register 450a, latches the current time t watch  within the watch dog timer 430 and stores this value as the charge cycle time t RC  for the charging circuit 101a. Rather than having to continuously poll the positional marker register 260, the host 280 directly obtains this t RC  by polling the positional time register 450a once. This alternative polling technique enables the present system 200 to avoid having to continuously poll the positional marker register 260 in order to calculate t RC . With this system and method, the system 200 can avoid partially monopolizing the limited CPU bandwidth. One skilled in the art can see that the host 280 can obtain t RC  information for the Y-axis of the analog joystick 105a and the X- or Y-axis of any other analog joystick in a similar manner as discussed above with regard to positional time register (X1) 450a. 
     Having described the present invention with reference to specific embodiments, the above description is intended to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the above discussion, many variations will be apparent to one skilled in the art that would yet be encompassed by the true spirit and scope of the present invention.