Abstract:
A frequency-to-current converter includes several capacitances with capacitive values that are effectively multiplied. After each of a series of periodic pulses, the voltage on a &#34;ramp&#34; capacitance is charged to a starting voltage. Then, during the period preceding the subsequent pulse, the ramp capacitance is allowed to discharge at a discharge rate that is a function of a voltage on a discharge-current bias capacitance. At the end of the period, the voltage on the ramp capacitance is sampled and compared to a reference. If the voltage on the ramp capacitance is too low or too high, indicating a discharge current that is too high or too low, respectively, the bias voltage on the bias capacitance is adjusted to compensate for the error. In another embodiment, a small ramp capacitance is repetitively charged and discharged between two reference voltage levels using alternating charge and discharge current levels. The charge and discharge current levels are related to output current levels so that the rate at which the ramp capacitance transitions between the two reference voltages provides an indication of the output current.

Description:
This application is a division of application Ser. No. 08/594,676, filed Feb. 2, 1996, now U.S. Pat. No. 5,736,879. 
     CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is related to application Ser. No. 08/595,812, filed herewith on Feb. 2, 1996, and issued Jun. 16, 1998 as U.S. Pat. No. 5,767,643, entitled &#34;Commutation Delay Generator For Multiphase Brushless DC Motor,&#34; by Giao M. Pham, Barry J. Concklin, and James H. Nguyen, which is incorporated herein by this reference. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     This invention relates generally to frequency-to-voltage and frequency-to-current converters. 
     DESCRIPTION OF RELATED TECHNOLOGY 
     Frequency-to-current converters are typically implemented by combining a frequency-to-voltage converter and a voltage-to-current converter. In a conventional frequency-to-voltage converter, a one-shot-controlled current reference is averaged by an integrating amplifier. The one-shot and the integrating amplifier each employ rather large capacitances that are difficult to integrate, and are therefore typically provided externally. The remaining circuitry may then be provided as one or more integrated circuits. Many conventional frequency-to-voltage converters are available, several of which are described in the 1994 Applications Handbook available from Burr-Brown of Tucson, Ariz. 
     An additional problem of conventional frequency-to-voltage converters results from a trade-off between ripple and settling time. High-resolution frequency-to-voltage converters demand low ripple, but decreasing the ripple increases settling time. In practice, the trade-off between settling time and ripple can be improved by filtering the frequency-to-voltage output with a low-pass filter. Unfortunately, such low-pass filters require some additional capacitance, making the frequency-to-voltage converter even more difficult to integrate. Finally, conventional frequency-to-current converters are typically open-loop systems. As such, conventional frequency-to-current converters are sensitive to external disturbances to the output, such as leakage current. 
     Because of the foregoing problems, there exists a need for a frequency-to-current converter that is insensitive to output disturbances, relies on matched component values to ensure accuracy, and makes use of relatively small, integrable, capacitances. 
     SUMMARY 
     The present invention addresses the aforementioned needs by providing a closed-loop frequency-to-current converter with integrable capacitances. To accomplish this, a frequency-to-current converter in accordance with the present invention includes several capacitances with capacitive values that are effectively multiplied using inventive capacitance-multiplication techniques. 
     One method in accordance with the invention allows for the conversion of a periodic series of input pulses to a proportional current without the use of an external capacitance. After each incoming pulse, the voltage on a &#34;ramp&#34; capacitance is reset to a starting voltage. Then, during the period preceding the subsequent pulse, the ramp capacitance is allowed to discharge at a rate that is controlled by a voltage stored across a discharge-current bias capacitance. Next, following the subsequent input pulse, the voltage on the ramp capacitance is sampled for a sample period that is short relative to the period of the pulse train. 
     During the sample period, the voltage on the ramp capacitance is compared to a fixed reference voltage. If the voltage on the ramp capacitance is lower than the fixed reference voltage, the discharge rate (and therefore the output current) is too high. Conversely, if the voltage on ramp capacitance is higher than the fixed reference voltage, the discharge rate is too low. 
     When the discharge rate of the ramp capacitance is determined to be either too low or too high, the stored voltage across the discharge-current bias capacitance is adjusted to compensate for the error. For example, if after one period of the input signal the voltage on the ramp capacitance is too high, the voltage on the bias capacitance is elevated to increase the discharge rate of the ramp capacitance for the next period. Once the comparison has been made and the voltage on the bias capacitance adjusted accordingly, the ramp capacitance is reset to the starting voltage and the cycle begins again. 
     As will be explained in detail below, the sampling technique is beneficial because the technique 
     1. allows for the use of a much smaller bias capacitance than would otherwise be required to provide a desired time constant, 
     2. allows a user to change the time constant of the bias capacitance without changing the value of the capacitance, and 
     3. eliminates the need to adjust the value of the bias capacitance for different input frequencies. 
     These benefits combined allow the bias capacitance to be integrated. 
     Another method in accordance with the invention, hereafter referred to as a &#34;folding&#34; technique, allows for the use of a relatively small ramp capacitance to establish the appropriate output current level. In accordance with this method, the small ramp capacitance is repetitively charged and discharged between two reference voltage levels using alternating charge and discharge current levels, each of which is a function of the output current level. 
     Because the charge and discharge current levels are related to the output current level, the rate at which the ramp capacitance is charged and discharged between the two reference voltages provides an indication of the output current. For example, if the output current is too high, the related charge and discharge currents will also be too high, resulting in relatively rapid charge and discharge rates. And, due to the rapid charge and discharge rates, the number of times the ramp capacitance will charge and discharge over a given period of time will increase in proportion to the increase in output current. Thus, a method in accordance with the invention includes the step of counting the number of times the ramp capacitance charges and discharges over a given period of time to determine whether to increase or decrease the output current. 
     The inventive folding technique allows for a significant reduction in the size of the ramp capacitance, thereby allowing the ramp capacitance to be easily integrated. Thus, in accordance with the present invention, both the bias capacitance and the ramp capacitance may be advantageously integrated with the other components of the frequency-to-current converter. Moreover, the inventive frequency-to-current converter design takes advantage of the exceptional device matching obtained using integrated circuit technology, as opposed to exact device values, to ensure accurate frequency-to-current conversion. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     These and other features, aspects, and advantages of the present invention will become understood with regard to the following description, appended claims, and accompanying drawings, where: 
     FIG. 1 shows a frequency-to-current converter 10 in accordance with one embodiment of the present invention; 
     FIG. 2 shows various waveforms associated with frequency-to-current converter 10 of FIG. 1; 
     FIG. 3 shows a frequency-to-current converter 50 in accordance with another embodiment of the present invention; 
     FIG. 4 illustrates the concept of &#34;folding&#34; the voltage range applied across a capacitance; 
     FIG. 5 is a schematic diagram of one embodiment of folded ramp capacitance 60; 
     FIG. 6 shows various waveforms associated with a &#34;folded&#34; capacitance; 
     FIG. 7 shows various waveforms associated with folded ramp capacitance 60; 
     FIG. 8 shows a frequency-to-current converter 150 in accordance with yet another embodiment of the present invention; and 
     FIG. 9 is a schematic diagram of a folded ramp capacitance 160. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows a frequency-to-current converter 10 in accordance with one embodiment of the present invention. Frequency-to-current converter 10 includes a sample timer 12, a ramp circuit 20, a differential transconductance amplifier GM1, a first sample gate 30, a second sample gate 31, and an output current generator 32. 
     Sample timer 12 is connected to the gate of a transistor 22 within ramp circuit 20 via a reset line RESET, to the control gate of sample gate 30 via a line SAMPLE, and to the control gate of sample gate 31 via a line SAMPLE. Depending on the voltage applied from sample timer 12 to the control terminal of transistor 22, transistor 22 transfers a reference voltage on a terminal V START  to a terminal of a ramp capacitance C RAMP  within ramp circuit 20. 
     The non-inverting (+) input of transconductance amplifier GM1 is connected to a line V RAMP  shared by transistor 22, capacitance C RAMP , and through sample gate 31 to an output of current generator 32. The inverting (-) terminal of transconductance amplifier GM1 is connected to a fixed reference voltage on terminal V FIXED , and the output of transconductance amplifier GM1 is connected to a current-handling terminal of sample gate 30. The other current-handling terminal of sample gate 30 is connected to the control gates of transistors 34 and 36 in current generator 32, and to one terminal of a discharge-current bias capacitance C CB . 
     Current generator 32 provides an output current I OUT  that is proportional to the input frequency of an input signal on a terminal F INPUT , and is therefore inversely proportional to the average period of the input signal on terminal F INPUT . Stated mathematically, ##EQU1## where T INPUT  is the average period of e.g. one hundred cycles of the input signal in terminal F INPUT  and α is the gain factor of frequency-to-current converter 10. 
     In the circuit of FIG. 1, output current I OUT  is negative (i.e., the current flows into current generator 32). Of course, current generator 32 may also be configured (e.g., using a conventional current mirror) to provide a positive output current I OUT . 
     Conventional current sources 35 and 37 provide offset currents through transistors 34 and 36, respectively, so that frequency-to-current converter 10 provides some specified offset current when the signal on terminal F INPUT  has a frequency of between zero Hz and some selected value. Current sources 35 and 37 each source the same level of current so that the ramp current I RAMP  is equal to the output current I OUT  Where desired, the offset current can be eliminated or set to zero. 
     FIG. 2 shows various waveforms associated with frequency-to-current converter 10 of FIG. 1. The timing of the waveforms of FIG. 2 is not to scale. For example, the period T INPUT  of the input signal on terminal F INPUT  is, in one embodiment, 300 us as compared to the reset period T RES  of 1 us and the sample period T SAM  of from 100 ns to 800 ns. Sample timer 12 is a conventional timing circuit that, based on its function described herein, may easily be implemented by those of skill in the art. 
     Referring to the waveforms of FIG. 2 in conjunction with frequency-to-current converter 10 of FIG. 1, sample timer 12 outputs a sample pulse of period T SAM  on line SAMPLE in response to an incoming pulse on terminal F INPUT . The sample pulse on line SAMPLE turns on sample gate 30, thereby connecting the output of transconductance amplifier GM1 to a terminal of bias capacitance C CB . During the sample period T SAM , a logic zero on line SAMPLE turns gate 31 off so that the voltage on terminal V RAMP  remains constant from e.g. time t 1  to time t 2 . 
     During the sample period T SAM  between times t 1  and t 2  the voltage on terminal V RAMP  is less than the voltage on terminal V FIXED . Thus, transconductance amplifier GM1 will draw charge away from capacitance C CB , thereby decreasing the voltage on the gates of transistors 34 and 36. As a consequence, the current I RAMP  through transistor 34 and the output current I OUT  through transistor 36 will decrease. 
     Subsequent to the sample pulse, sample timer 12 outputs a reset pulse of period T RES  to the gate of transistor 22 in ramp circuit 20. The reset pulse turns transistor 22 on, charging C RAMP  to the reference voltage level on terminal V START , as shown in FIG. 2 at time t 3 . 
     Once the voltage on terminal V RAMP  (and consequently across ramp capacitance C RAMP ) has been reset to the reference voltage on terminal V START , ramp capacitance C RAMP  will discharge through transistor 34 so that the voltage level on terminal V RAMP  will decrease to a level V FIN  at time t 4  when the next input pulse arrives on line 42. Because the voltage V FIN  on line V RAMP  is below the voltage on terminal V FIXED , during the sample period from t 4  to t 5  transconductance amplifier GM1 will again draw charge away from bias capacitance C CB , thereby decreasing the voltage on terminal V CCB . This effect is shown in FIG. 2 as the decrease in the voltage V CCB  that occurs during the second sample period (from t 4  and t 5 ). Having decreased the bias voltage on terminal V CCB , the current through transistors 34 and 36 will also decrease. Thus, capacitance C RAMP  will discharge more slowly than during the prior period, as evidenced by the decreased slope of the voltage on terminal V RAMP  from time t 6  to time t 8 . 
     When, as in the third sample period of FIG. 2 (from time t 7  to time t 8 ), the finish voltage V FIN  on ramp capacitance C RAMP  is greater than the voltage on terminal V FIXED , transconductance amplifier GM1 will provide charge to bias capacitance C CB  through sample gate 30 during the sample period T SAM , as evidenced by the voltage increase on terminal V CCB  from time t 7  to time t 8 . 
     The above-described closed-loop feedback system will eventually cause the voltage on terminal V RAMP  to go from the reference voltage on terminal V START  to the reference voltage on terminal V FIXED  in the period between input pulses. In other words, the voltage level V FIN  for the voltage on terminal on V RAMP  will equal the voltage level on terminal V FIXED  during a sample period T SAM . In such a case, virtually zero current will flow from the output of transconductance amplifier GM1 during the sample period T SAM . This case is illustrated in FIG. 2 between time t 10  and time t 11 . 
     It is important here, as with conventional feedback systems, that the time constant τ Ccb  of current-bias capacitance C CB  be selected to provide a fast response without resulting in instability. The time constant τ Ccb  (measured in units of time) may be calculated as: ##EQU2## where C Ccb  is the capacitance of current-bias capacitance C CB  and g mCcb  is the transconductance providing the charge/discharge current for C CB . 
     The time constant τ Ccb  must be large enough to provide the appropriate response. The time constant τ Ccb  may be increased by decreasing the value of the transconductance g m1  of transconductance amplifier GM1, which provides the charge and discharge currents to capacitance C CB . However, there is a lower limit of g m1  below which noise becomes unacceptably high. Another possibility is to increase the value of capacitive C Ccb . Unfortunately, the frequencies of interest (e.g., 1/T INPUT  or 3.3 KHz) require a relatively large capacitance that may not be integrated practically. 
     The present invention overcomes the foregoing problems associated with increasing the time constant τ Ccb  by employing an inventive sample-and-hold technique. Sample timer 12 and sample gate 30 sample and hold the output of transconductance amplifier GM1 so that the transconductance g mCcb  input to capacitance C CB  is reduced to ##EQU3## Thus, the time constant of C CB , T Ccb , is increased to: ##EQU4## As equation (7) makes clear, the &#34;effective&#34; capacitance of C Ccb  may be expressed as C eff  =C Ccb  (T INPUT  /T SAM ) . In other words, the necessary value (and therefore size) of current-bias capacitance C CB  is reduced by a factor of T SAM  /T INPUT  ; accordingly, C CB  may be reduced to a integrable size while maintaining the appropriate time constant τ Ccb . 
     Without the inventive sample-and-hold technique, the value of C CB  would have to be adjustable to allow for different input frequencies. Fortunately, the inventive sample-and-hold technique eliminates the need to provide a variable capacitance. Substituting 1/T INPUT  in equation (6) with the input frequency f INPUT  shows that the time constant τ Ccb  of bias capacitance C CB  is a function of the input frequency f INPUT . Stated mathematically, ##EQU5## 
     Thus, using the sample-and-hold technique that samples for a fixed time period T SAM  and a fixed capacitance C ccb , the time constant τ Ccb  automatically changes with changes in the input frequency f INPUT . 
     FIG. 3 shows a frequency-to-current converter 50 in accordance with another embodiment of the present invention. To the extent that FIG. 3 is similar to FIG. 1, similar reference numbers are used. Frequency-to-current converter 50 functions in substantially the same way as described above in connection with FIGS. 1 and 2. However, in frequency-to-current converter 50, ramp capacitance C RAMP  is replaced by a folded ramp capacitance 60. For simplicity, the optional offset current sources 35 and 37 are not shown in FIG. 3. 
     In accordance with the embodiment of FIG. 3, ramp capacitance C RAMP  is replaced by a folded ramp capacitance 60. As explained below, the process of &#34;folding&#34; allows for the use of a relatively small value of ramp capacitance C RAMP , resulting in easier, more economical, integration. Folded ramp capacitance 60 receives as inputs a reference voltage on terminal V MAX  and a second reference voltage on a terminal V MIN , the voltages on terminals V MAX  and V MIN  being e.g. 5 volts and 1 volt, respectively. In one embodiment, terminals V MAX  and terminal V REF  are connected so that the reference voltage on terminal V REF  also serves as the reference voltage on terminal V MAX . 
     Capacitance 60 outputs a signal &#34;UNDER&#34; on a line 62 to an input of a transconductance amplifier GM2. Transconductance amplifier GM2 is configured to operate as a conventional differential amplifier when a logic zero (e.g., zero volts) is applied on line 62, and to output its maximum positive output current, regardless of the levels on its differential input terminals (+ and -), when a logic one (e.g., 5 volts) is applied on line 62. 
     The following explanation describes the concept of &#34;folding&#34; in general, which may be used to increase the time constant of a given capacitance C. In the general case, for a given capacitance C with a constant charging current I C , the time constant τ C  is proportional to the product of the change in voltage ΔV and the capacitance C divided by the current I C . This relationship may be expressed mathematically as: ##EQU6## Thus, for a given time constant τC, the necessary value of the capacitance C, and thus the physical area required to integrate such a capacitance, may be minimized by either increasing ΔV or decreasing the current I C . 
     Unfortunately, there is a lower limit to the level of current I C  used to charge the capacitance C, for when the current is too low, noise and leakage produce unacceptably poor accuracy in defining the time constant τ C . Moreover, it is not practical to substantially increase the power supply voltages for integrated circuits to increase the effect of capacitance of a particular capacitance on the integrated circuit. For these reasons, Applicant invented a folding technique that allows for an effective increase in the voltage change ΔV across ramp capacitance C RAMP  without requiring increased voltage potentials. According to this aspect of the invention, the desired voltage range is &#34;folded&#34; into a number of smaller voltage ranges. 
     FIG. 4 illustrates the concept of &#34;folding&#34; the voltage range applied across a capacitance. Paths P 1  and P 2  are discharge paths similar to the V RAMP  discharge paths between times t 3  and t 4 , between times t 6  and t 7 , and between times t 9  and t 10  of FIG. 2. Path P 1  shows the voltage across capacitance C discharging at a constant current I C  from 5 volts to -11 volts (for a total ΔV of 16 volts) over a time period T. Path P 2  shows the voltage across capacitance C discharging at a reduced constant current I C  &#39; so that during the period T the capacitance C discharges from 5 volts to -9 volts, for a total ΔV of only 14 volts. Assuming that the current used to produce path P 1  is the desired current, the voltage difference between path P 1  and path P 2  at the end of period T (i.e., the error voltage V.sub.ε  of 2 volts) may then be used to provide feedback to transconductance amplifier GM2 in the manner described above in connection with transconductance amplifier GM1. 
     According to the inventive folding technique, the 16-volt range of path P 1  may be folded into a number of segments. For example, FIG. 4 shows path P 1  folded into a path P 1  &#39;, which includes four segments, two decreasing and two increasing. The folded path P 1  &#39; represents a voltage change ΔV having an absolute value of 16 volts (i.e., four 4-volt changes) without exceeding 5 volts or going below 1 volt. Similar to path P 1 , path P 2  may folded into e.g. four segments, two decreasing and two increasing, as shown using path P 2  &#39;. Importantly, at the end of period T the folded waveform P 2  &#39; is off by an error voltage V.sub.εF of the same magnitude as the error voltage V.sub.ε  separating paths P 1  and P 2 . 
     The error voltage V.sub.εF may be used to provide feedback for transconductance amplifier GM2. Note that the error voltage V.sub.εF is of the opposite polarity of the voltage V.sub.ε. For this reason, the inverting and non-inverting (- and +) terminals of transconductance amplifier GM2 are reversed in the embodiment of FIGS. 3 and 5 as compared to the terminals of transconductance amplified GM1 of FIG. 1. This and other aspects of the embodiment of FIG. 3 are described below in detail in connection with FIGS. 5 and 6. 
     FIG. 5 is a schematic diagram of one embodiment of folded ramp capacitance 60. Folded ramp capacitance 60 includes ramp capacitance C RAMP , a comparator circuit 70, a counter 80, and a current source 90. 
     Current source 90 receives the ramp current I RAMP  on line 92 from current generator 32 through sample gate 31. The ramp current I RAMP  is mirrored by transistors 94 and 96 to provide a current I RAMP  &#39; substantially equal to the ramp current IRAMP through series-connected transistors 98 and 100. Transistors 102 and 104 conventionally mirror transistors 98 and 100 so that the current I RAMP  &#39; travels through series-connected transistors 96, 98, and 100, and through series-connected transistors 106, 102, and 104. A transistor 108 mirrors transistor 106 so that a current I C  substantially equal to the current I RAMP  &#39; through transistor 106 is conducted by the current-handling terminals of transistor 108. Finally, a current source 110, which includes a transistor 112 and a transistor 114, is biased by the combination of transistors 102 and 104. 
     The pair of transistors 112 and 114 is similar to transistors 102 and 104, except that transistors 112 and 114 have a multiplication factor M of two. Because of the multiplication factor, current source 110 conducts twice as much current for a given bias voltage on the base of transistor 112 as the series connected transistors 102 and 104 (and consequently twice as much current as the current I C  through transistor 108). With this configuration, when transistor 114 is off, the folded ramp current I F  from current source 90 is substantially equal to I C . Conversely, when transistor 114 is conducting, current source 110 conducts a current substantially equal to twice I C  so that the folded ramp current I F  is equal to I C  -2I C  =-I C . Thus, the folded ramp current I F  may be used to alternately charge and discharge ramp capacitance C RAMP  at rates of I C  and -I C , respectively, the direction of folded ramp current I F  depending on whether transistor 114 is on or off. 
     Comparator circuit 70 receives the folded ramp current I F  on an input line 71. Referring to FIGS. 4 and 5, path P 1  &#39; will be used to explain the operation of comparator circuit 70, where the path P 1  &#39; represents the changing voltage level on terminal V RAMP  of FIGS. 3 and 5. 
     Referring to FIG. 5, if we assume that the reset terminal RESET of counter 80 was just supplied a positive (e.g., 12-volt) pulse, the voltage on terminal V RAMP  will be reset to 5 volts, as shown at the Y axis of FIG. 4. And, if we assume that the folded ramp current I F  from current source 90 is equal to -I C  (i.e., that transistor 114 is biased on), the voltage on terminal V RAMP  will begin to discharge as shown in FIG. 4 as element A. 
     Comparator circuit 70 includes a maximum-voltage comparator 72, a minimum-voltage comparator 74, a reset transistor 76, and a conventional cross-coupled latch 78. When the voltage on terminal V RAMP  on the ramp capacitance C RAMP  discharges below V MIN , comparator 74 will output a logic one to latch 78, which will consequently output a logic zero to an input of an AND gate 84. For the time being, assume that other input to AND gate 84 from line 62 is a logic one, so that the logic zero from latch 78 will cause AND gate 84 to output a logic zero to the gate of transistor 114, turning transistor 114 off. 
     With transistor 114 off, the folded ramp current I F  from current source 90 will change from -I C  to +I C , the current through transistor 108. As shown in FIG. 4 as leg B of path P 1  &#39;, the folded ramp current I F  will begin to charge the ramp capacitance C RAMP , thereby increasing the voltage on terminal V RAMP . 
     Next, when the voltage on terminal V RAMP  exceeds the voltage on terminal V MAX  (5 volts in this case), comparator 72 will output a logic one to latch 78 causing latch 78 to output a logic one to transistor 114. As a result, transistor 114 and transistor 112 will conduct twice as much current (2I C ) as transistor 108 (I C ), so that the folded ramp current I F  of current source 90 will return to -I C . Ramp capacitance C RAMP  will consequently begin to discharge, resulting in the steady decrease in the voltage on terminal V RAMP  shown as leg C of path P 1  &#39; in FIG. 4. 
     As long as there is an ramp current I RAMP  through line 92, there will be a folded ramp current I F  that is either charging or discharging ramp capacitance C RAMP . In the case of path P 1  &#39;, the voltage on terminal V RAMP  of ramp capacitance C RAMP  is shown to discharge to 1 volt twice (legs A and C) and charge to 5 volts twice (legs B and D). 
     Counter 80 is connected to comparator circuit 70 on line UNDER --  L, which stands for &#34;under low,&#34; indicating that the voltage on terminal V RAMP  is under the minimum voltage on terminal V MIN . The under-low pulses on line UNDER --  L to counter 80 allow counter 80 to count the number of times the changing ramp voltage on terminal V RAMP  transitions from negative-going to positive-going, thereby providing an indication of the number of &#34;folds.&#34; Once the count received by counter 80 goes above a predetermined number, counter 80 outputs a logic zero on output line 62 to transconductance amplifier GM2 and to AND gate 84. 
     FIG. 6 is similar to FIG. 4 in that FIG. 6 illustrates an example where the voltage across ramp capacitance C RAMP  is folded four times. The voltage V RAMP  on ramp capacitance C RAMP  transitions from 5 volts to 1 volt and then from 1 volt to 5 volts as described above in connection with FIG. 4. Each time the voltage transitions from negative-going to positive-going, comparator 74 of comparator circuit 70 outputs a positive pulse on line UNDER --  L. This positive pulse increments the count stored in counter 80. 
     In the example of FIG. 6, counter 80 is configured to output a logic zero on line 62 only after the count is equal to two. In other words, as long as the count is &#34;under&#34; two, counter 80 will output a logic one as the signal UNDER on line 62. 
     If the ramp current I RAMP  is far too low for a given input frequency, the folded ramp current I F  of current source 90 will also be too low. In such a case, counter 80 will not reach a count of two during one period of the input signal. In such a case, counter 80 will output a logic one on line 62, which will deactivate GM2 so that GM2 will not respond to its positive and negative inputs, but will instead output its maximum output current of, for example, 10 uA. Thus, when the output current I OUT  is far low than is appropriate for a given input frequency, transconductance amplifier GM2 outputs a maximum current to charge bias capacitance C CB . 
     As the value of the output current I OUT  (and therefore the ramp current I RAMP ) increases to more accurately reflect the input frequency, the transition time of the ramp voltage on terminal V RAMP  will continue to decrease until the counter reaches a count of two prior to the end of one period T INPUT  of the input signal. This case is shown in FIG. 6. Once counter 80 reaches a count of two, counter 80 outputs a zero on line 62, which activates transconductance amplifier GM2. Transconductance amplifier GM2 than responds to its inverting and non-inverting inputs. The active region of transconductance amplifier GM2 is illustrated in FIG. 6 as &#34;GM2 active.&#34; 
     Once GM2 is active, frequency-to-current converter 50 works in substantially the same way as described above in connection with frequency-to-converter 10. If at the end of the period T INPUT  of the input signal the ramp voltage on terminal V RAMP  is higher than the reference voltage on terminal V MAX , transconductance amplifier GM2 draws some charge from bias capacitance C CB  during the sample period T SAM , thus decreasing the ramp current I RAMP  (and consequently decreasing the folded ramp current I F ). Conversely, if GM2 is in the active region and the ramp voltage on terminal V RAMP  is below the reference voltage on terminal V MAX  at the end of the period T INPUT , then the active transconductance amplifier GM2 will output current to charge bias capacitance C CB  through sample gate 30 during the sample period T SAM . 
     Using a folding factor of four, the embodiment described in connection with FIG. 6 increases the effective capacitance of ramp capacitance C RAMP  by a factor of four. Of course, the voltage across ramp capacitance C RAMP  can be folded any number of times. For example, FIG. 7 shows various waveforms associated with folded ramp capacitance 60 in an embodiment that multiplies the total voltage change across ramp capacitance C RAMP  by thirty-two times. 
     During the sample period T SAM  of FIG. 7, the voltage on terminal V RAMP  is slightly less than the reference voltage on terminal V MAX . As a result, transconductance amplifier GM2 provides an output current to bias capacitance C CB , thereby increasing the bias voltage on terminal V CCB . Then, during the subsequent reset pulse, the positive reset voltage on the gate of transistor 76 of comparator circuit 70 (see FIG. 5) resets the voltage on terminal V RAMP  to the voltage on terminal V MAX . Once reset, the voltage V RAMP  transitions back and fourth between the voltage on terminal V MAX  and the voltage on terminal V MIN  approximately 32 times before the next sample pulse. 
     In the case of FIG. 7, counter 80 would be configured to activate GM2 after a count of 16. If counter 80 did not sense 16 negative to positive transitions between input pulses, counter 80 would output a logic one on line 62, indicating that the count was &#34;under,&#34; causing transconductance amplifier GM2 to output the maximum available current to bias capacitance C CB . 
     If the folded ramp current I F  were far too high relative to the input frequency, the transitions of the ramp voltage on terminal V RAMP  would occur far more rapidly, causing counter 80 to reach its maximum count and activate transconductance amplifier GM2 well before the end of the period T INPUT . When this happens, the signal from counter 80 on line 62 goes low, causing AND gate 84 to disable transistor 114, consequently disabling the folding action of folded ramp capacitance 60. As a result, the voltage on terminal V RAMP  will continue to climb beyond the reference voltage on terminal V MAX  (to a maximum voltage of e.g. 4 volts above V MAX , or 9 volts), as shown in FIG. 6. Transconductance amplifier GM2 will then output a current to decrease the ramp current I RAMP  in much the same way as described above in connection with FIG. 3. After a number of periods of the input signal, the final voltage on terminal of V RAMP  after a single input period T INPUT  will be precisely equal to the voltage on terminal V MAX . 
     FIG. 8 is a schematic diagram of yet another embodiment of the present invention--frequency-to-current converter 150--wherein the settling time of the output current I OUT  is improved by the addition of a variable current generator 200 and associated circuitry. The schematic of FIG. 8 is similar to that of FIG. 3, like elements having the same reference numbers. 
     A folded ramp capacitance 160 is connected to a transconductance amplifier GM3 via a GM-enable line GM --  EN and to current generator 200 via a current-select bus I SEL , which includes lines CNT&lt;8, 8≦CNT&lt;12, 12≦CNT&lt;16, 17&lt;CNT≦20, and CNT&gt;20 (shown in FIG. 9). 
     FIG. 9 is a schematic diagram of a folded ramp capacitance 160 that is similar to folded ramp capacitance 60 of FIG. 5, like elements having the same reference numbers. When the count stored in a counter 180 is less than eight, counter 180 outputs a logic one on line CNT&lt;8 of bus I SEL . Similarly, when the stored count is from eight to eleven, twelve to fifteen, eighteen to twenty, or greater than twenty-one, counter 180 outputs a logic one on the corresponding one of lines 8≦CNT&lt;12, 12≦CNT&lt;16, 17&lt;CNT≦20, and CNT&gt;20, respectively. When the stored count is sixteen or seventeen, a logic one on line GM --  EN enables transconductance amplifier GM3 to function in the active mode, as described above for transconductance amplifier GM2 in connection with FIG. 6. 
     Current generator 200 of FIG. 8 is conventionally configured to output a current of: 
     1. 1 mA when the voltage on line CNT&lt;8 represents a logic one; 
     2. 100 μA when the voltage on line 8≦CNT&lt;12 represents a logic one; 
     3. 10 μA when the voltage on line 12≦CNT&lt;16 represents a logic one; 
     4. -100 μA when the voltage on line 17&lt;CNT≦20 represents a logic one; and 
     5. -1 mA when the voltage on line CNT&gt;20 represents a logic one. 
     Thus configured, the current used to charge and discharge bias capacitance C CB  in frequency-to-current converter 150 varies depending on the count stored in counter 180. That is, when the voltage on terminal V CCB  is relatively far from that required to provide the correct output current I OUT , the charge or discharge current used to correct the voltage on terminal V CCB  is increased. Then, as the voltage on terminal V CCB  approaches the appropriate fixed voltage V FIXED  during the sample period T SAM , the charge or discharge current decreases. In this way, frequency-to-current converter 150 improves the settling time of ramp current I RAMP  while maintaining stability. 
     Frequency-to-current converters in accordance with the present invention are not limited to the particular applications described above. For example, in one embodiment, sample gate 31 of FIG. 3 is eliminated by connecting line SAMPLE directly to the gate of transistor 104 and, through an additional input (not shown) of AND gate 84, to the gate of transistor 114. Furthermore, frequency-to-current converters that do not require the level of precision provided by the &#34;active&#34; analog mode of the second embodiment could rely only on the count stored in counter 80 to determine the output current level. Therefore, the scope of the appended claims should not be limited to the description of the preferred versions described herein.