Abstract:
A USB peripheral device and a method of determining USB speed mode. The method of determining USB speed mode for an USB peripheral device, wherein the USB peripheral device is coupled to an USB host through an USB transmission cable, and the USB transmission cable comprises power and ground lines for power supply, and first and second data signals for transmitting data, the method comprising the USB peripheral device pulling up voltage level of the first data signal with a first pull-up device, the USB peripheral device pulling up voltage level of the second data signal with a second pull-up device, and the USB host determining a high/full speed mode for the USB peripheral device, when detecting only one of the first and second data signals exceeding a threshold, and then detecting the other data signal exceeding the threshold in a predetermined period.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to Universal Serial Bus (USB) systems, and in particular to a USB peripheral device and a method of determining a speed mode therein. 
         [0003]    2. Description of the Related Art 
         [0004]    USB (Universal Serial Bus) connectivity supports hardware peripherals, such as keyboard, mouse, scanner, printer . . . etc. USB 1.0, USB 1.1, and USB 2.0 standards specify three speed modes. USB 1.0 specifies a low speed mode, applicable to 1.5 Mbps data transmission, such as for keyboard and mouse. USB 1.1 defines full speed mode, capable of transmitting data up to 12 Mbps data rate. USB 2.0 specifies high speed mode, with data rate up to 480 Mbps. Each USB host is required to determine the correct speed mode thereof, such that data transmission can be carried out accordingly. 
         [0005]      FIG. 1  is a block diagram of a USB system, comprising USB host  10 , USB transmission bus  12 , and USB peripheral device  14 . USB host  10  is coupled to USB transmission bus  12 , and then to USB peripheral device  14 . USB host  10  comprises power supply  100  and host transceiver  102 . USB transmission bus  12  comprises Vbus  120 , Data+ line  122 , Data− line  124 , and GND  126 . USB peripheral device  14  comprises power supply  140  and device transceiver  142 . 
         [0006]    Power supply  100  provides 5V power to host transceiver  102 , implemented by hardware comprising a driver interface that receives instruction from a driver program and acts accordingly. Host transceiver  102  transmits signals compliant with USB standards to USB peripheral device  14 . These signals generally are differential signal pair, transmitted through a twisted pair, i.e., Data+ line  122  and Data− line  124 . Data+ and Data− signals on Data+ line  122  and Data− line  124  are half-duplex signals, i.e., the USB signal transmission is conducted by either USB host  10  or USB peripheral device  14  at one time, but not both simultaneously. Power supply  140  is a voltage regulator providing power for device transceiver  142 , converting 5V from Vbus 120 to 3.3V. While  FIG. 1  shows USB host  10  connected to a single USB peripheral device  14 , multiple  14 s may be connected to USB host  10  via branching structure. 
         [0007]      FIGS. 2   a  and  2   b  show waveforms of Data+ and Data− signals compliant with USB standards for determining speed mode of a USB peripheral device, incorporating the USB system in  FIG. 1 , where the horizontal axis represents time, and the vertical axis represents detected voltages. Period T connect  is connection time DCNN  in USB standards. 
         [0008]      FIG. 2   a  depicts a waveform diagram of signals on Data+ line  122  and Data− line  124  for high/full speed or full speed mode. Curve  20   a  is a voltage signal on Data+ line  122  and curve  22   a  a voltage signal on Data− line  124 . Host transceiver  102  detects curve  20   a  increasing at time  200   a , reaching V IH  at time  202   a , while curve  22   a  remains at voltage V SS  throughout. Host transceiver  102  continues monitoring both signals after time  202   a , and, if curve  20   a  stays above V IH  and curve  22   a  remains at VSS in period T connect , host transceiver  102  determines USB peripheral device  14  is either a high/full speed or a full speed USB peripheral device. Actual determination of whether its speed mode is high/full or full occurs only after USB peripheral device  14  receives a reset signal from host transceiver  102 , based upon the following handshake between USB peripheral device  14  and host transceiver  102 . 
         [0009]      FIG. 2   b  depicts a waveform diagram of signals on Data+ line  122  and Data− line  124  for low speed mode.  20   b  is a voltage signal on Data+ line  122  and  22   b  a voltage signal on Data− line  124 . Host transceiver  102  detects  22   b  increasing at time  200   b , reaching V IH  at time  202   b , while  20   b  remains at voltage V SS  throughout. Host transceiver  102  continues monitoring both signals after time  202   a , if  22   b  stays above V IH  and  20   b  remains at VSS in period T connect , host transceiver  102  determines USB peripheral device  14  is a low speed USB peripheral device. Period T connect  is connection time DCNN in USB standards. 
         [0010]    It can be understood from the description above that the conventional method has no problem in recognizing a low speed USB peripheral device. However, the conventional method does have difficulty in distinguishing a high/full speed device from a full speed device, or vice versa, for these two speed devices cause completely the same voltage-to-time curve before the sending or receiving of a reset signal. Before the determination of whether a USB peripheral device is a high/full speed device or a full speed device, the USB peripheral device will first experience a full speed mode, and, after receiving a reset signal from a host transceiver, enter a high speed mode to cause the host transceiver entering the same high speed mode for data communication. Nevertheless, the sending and the receiving of the reset signal happen 100 ms after time  204   a . Thus, the conventional method to identify a high/full device from a high device is too late and renders the delay of data communication. Also is it too complex for it requires the following Data+ and Data− handshake between USB peripheral device  14  and host transceiver  102  to make such identification. 
         [0011]    Thus a need exists for a USB peripheral device and method to efficiently and quickly determine a speed mode thereof. 
       BRIEF SUMMARY OF THE INVENTION 
       [0012]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
         [0013]    A method of determining USB speed mode for an USB peripheral device, wherein the USB peripheral device is coupled to an USB host through an USB transmission cable, and the USB transmission cable comprises power and ground lines for power supply, and first and second data signals for transmitting data, the method comprising the USB peripheral device pulling up voltage level of the first data signal with a first pull-up device, the USB peripheral device pulling up voltage level of the second data signal with a second pull-up device, and the USB host determining a high/full speed mode for the USB peripheral device, when detecting only one of the first and second data signals exceeding a threshold, and then detecting the other data signal exceeding the threshold in a predetermined period. 
         [0014]    Also provided is an USB peripheral device comprising a first pull-up device, a second pull-up device, and an USB device transceiver. The first pull-up device pulls up voltage level of a first signal. The second pull-up device pulls up voltage level of a second signal. The USB device transceiver, coupled to the first pull-up device and the second pull-up device, enables only one of the first and second pull-up devices such that the corresponding signal exceeds a threshold; and enables the other pull-up device such that the corresponding signal exceeds the threshold in a predetermined period, thereby indicating the USB peripheral device is a high/full speed device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0016]      FIG. 1  is a block diagram of a USB system. 
           [0017]      FIGS. 2   a  and  2   b  show waveforms of Data+ and Data− signals compliant with USB standards for determining speed mode of a USB peripheral device. 
           [0018]      FIG. 3  is a block diagram of a USB system according to the invention. 
           [0019]      FIG. 4  is a flowchart of an exemplary method for determining USB speed mode according to the invention. 
           [0020]      FIGS. 5   a  and  5   b  show waveforms of Data+ and Data− signals according to the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limit sense. The scope of the invention is best determined by reference to the appended claims. 
         [0022]      FIG. 3  is a block diagram of a USB system according to the invention, comprising USB host  50 , USB bus  52 , USB peripheral device  54 , and application program  56 . USB host  50  comprises power supply  500  and host transceiver  502 . USB peripheral device  54  comprises power adaptor  540 , device transceiver  542 , and pull-up resisters RI and R 2 . USB bus  52  comprises Vbus  520  for providing power supply, Data+ line  522  and Data− line  524  for data transmission, and GND  526  for grounding. Data+ and Data− signals respectively transmitted on Data+ line  522  and Data− line  524  constitute a differential signal pair. Vbus  520  couples between power supply  500  and power adaptor  540  such that USB host  50  could power USB peripheral device  54 . GND  526  couples the ground of USB host  50  to the ground of USB peripheral device  54 . 
         [0023]    Power adaptor  540  in USB peripheral device  54  converts voltage up or down to provide power supply Vcc for USB peripheral device  54 , for example, converting 5V to 3.3V. Pull-up devices R 1  and R 2  may be 1.5 k ohm, each comprising one end connected to adapted power supply Vcc, and another end connected to first pull-up device  5420   a  or second pull-up device  5420   b . By the control of device transceiver  542 , pull-up resistors R 1  and R 2  may be coupled to Data+  522  and Data−  544  respectively. Device transceiver  542  comprises a Physical layer (referred to as PHY hereinafter) device  5420  and Medium Access Control/Baseband (referred to as MAC/BB hereinafter) device  5422 . PHY device  5420  comprises first pull-up device  5420   a  coupled to resistor R 1  and data+  522 , and second pull-up device  5420   b  coupled to resistor R 2  and data−  524 , for disconnecting or connecting pull-up resistors R 1  and R 2  to Data+  522  and Data−  524 . First pull-up device  5420   a  and second pull-up device  5420   b  may be switches implemented by MOS transistors. 
         [0024]    Host transceiver  502  may comprise a timer (not shown) calculating the connection duration on Data+ line  522  and Data− line  524  between USB host  50  and USB peripheral device  54 . The timer may count connection duration T connect  compliant with the requirement in USB standard, approximately 2.5 ms. 
         [0025]    Table 1 shows a comparison between signal pin settings for the determination of USB peripheral device speed according to the USB standard and the exemplary disclosure of the invention. The signal pin setting determines speed mode of a USB peripheral device. In a conventional method, a common signal pin setting (Data+1=1, Data−=0) is utilized for both high/full and full speeds, and causes the delay of distinguishing between high/full and full speeds. The disclosure utilizes separate pin settings, (Data+1=1, Data−=1) and (Data+1=1, Data−=0), for high/full and full speeds, respectively. Upon power adaptor  540  in USB peripheral device  54  receives the power supply from USB host  50  through Vbus  520  for power adaptation and electronic components in USB peripheral device  54  are properly powered, MAC/BB device  5422  in device transceiver  542  enables first pull-up device  5420   a  and second pull-up device  5420   b  to pull up the voltage potential in Data+  522  and Data−  524  to high voltage potential Vcc, so that host transceiver  502  in USB host  50  can detect “11” from Data+ and Data− pins, indicating USB peripheral device  54  being a high/full speed USB device. These processes are to be complete prior to the occurrence of a reset signal issued by USB host  50 , and, possibly, prior to the end of the duration T connect  when both voltage potentials at Data+  522  and Data−  524  are pulled up to more than threshold V IH . Accordingly, the speed mode of an USB peripheral device is quickly and correctly identified. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 The disclosure 
                   
                 USB 2.0 standard 
               
               
                 USB peripheral device 
                 Pin name 
                 USB peripheral device 
               
             
          
           
               
                 speed mode 
                 Data+ 
                 Data− 
                 speed mode 
               
               
                   
               
               
                 Disconnected 
                 0 
                 0 
                 Disconnected 
               
               
                 Low speed 
                 0 
                 1 
                 Low speed 
               
               
                 Full speed 
                 1 
                 0 
                 high/full or full speed 
               
               
                 high/full speed 
                 1 
                 1 
                 Not applicable 
               
               
                   
               
             
          
         
       
     
         [0026]      FIG. 4  is a flowchart of an exemplary method for determining USB speed mode according to the invention, incorporating the USB system in  FIG. 3 . 
         [0027]    Upon connecting USB peripheral device  54  to USB host  50 , application program  56  directs host transceiver  502  to detect Data+ and Data− signals on Data+ line  522  and Data− line  524  (Step S 600 ). In Step S 602 , host transceiver  502  monitors voltage potential of Data+ signal on Data+ line  522  to determine connection. If host receiver  502  detects the voltage potential at Data+ line  522  exceeding a predetermined threshold, for example, 2.0V, Step S 606  is carried out. If not, Step S 620  proceeds. By doing this way, if the voltage potential of Data+ signal on Data+ line  522  exceeds the predetermined threshold, host transceiver  502  determines a connection is established for Data+ signal, otherwise Data+ signal is disconnected. 
         [0028]    Next in Step S 606 , host transceiver  502  determines whether a connection is established on Data− line  524  in a period T connect  timed by a timer, or prior to the reset signal issued by USB host  50 . If the voltage potential at Data−  524  is also pulled up and exceeds the predetermined threshold in the period T connect , application program  56  directs to a condition depicted in Step S 608 , indicating USB peripheral device  54  is a high/full speed USB device, and proceeding Step S 610 . If not, application program  56  directs to a condition depicted in Step S 614 , indicating a full speed USB device, and Step S 616  is carried out. 
         [0029]    In Step S 610 , since in the period T connect  Data+ and Data− signals both exceed the predetermined threshold, application program  56  determines the speed mode of USB peripheral device  54  is high/full speed, and sends a reset signal to USB peripheral device  54 . Upon the receiving of the reset signal, device transceiver  542  resets Data+ and Data− signals to “LOW” by disabling pull-up devices  5420   a  and  5420   b . MAC/BB module  5422  opens pull-up devices  5420   a  and  5420   b  to disconnect pull-up resistors R 1  and R 2  from Data+ line  522  and Data− line  524 . In Step S 612 , data transmission is performed at high/full speed. 
         [0030]    In Step S 616 , since Data+ signal exceeds the predetermined threshold and Data− signal stays approximately at “LOW”, application program  56  determines the speed mode of USB peripheral device  54  is full speed, and USB host  50  and USB peripheral device  54  start to perform data transmission at full speed after USB host  50  issues a reset signal (Step S 618 ). 
         [0031]    In Step S 620 , since Data+ signal has been recognized as “LOW”, host transceiver  502  monitors whether the voltage potential of Data− signal exceeds the predetermined threshold. If so, Step  624  is carried out, and, if not, indicating USB peripheral device  54  is not properly connected, Steps S 602  is periodically repeated to check whether there is a proper connection established between USB peripheral device  54  and USB host  50 . 
         [0032]    In Step S 624 , host transceiver  502  determines whether a connection is established on Data+ line in a period T connect  timed by the timer, or prior to the reset signal issued by USB host  50 . If the voltage potential at Data−  524  is also pulled up and exceeds the predetermined threshold in the period T connect , application program  56  determines Data+ and Data− signals both exceed the predetermined threshold, and directs to a condition depicted in Step S 626  followed by Step S 610 . In Step S 626 , USB peripheral device  54  is indicated as a high/full speed USB device. As discussed before for step S 610 , USB host  50  then issues a reset signal to reset the voltage potentials at Data+ and Data− lines  522 ,  524  to prevent disturbance to the following high/full speed data transmission. If in step S 624  it is determined that the voltage potential at Data−  524  does not exceed the predetermined threshold in the period T connect , application program  56  determines that Data− signal becomes “HIGH” while Data+ signal remains “LOW”, as depicted in Step S 628 , and Step S 630  follows. In Step S 630 , application program  56  determines the speed mode of USB peripheral device  54  is low speed, such that USB host  50  and USB peripheral device  54  perform data transmission therebetween at low speed after USB host  50  issues a reset signal. 
         [0033]      FIGS. 5   a  and  5   b  show voltage-time waveforms of Data+ and Data− signals according to the invention, incorporating the USB system in  FIG. 3  and the speed determination method in  FIG. 4 . 
         [0034]      FIG. 5   a  shows a waveform detected by host transceiver  502  at Step S 608 , where curve  70   a  is the voltage potential of Data+ signal on Data+ line  522 , curve  72   a  is the voltage potential of Data− signal on Data− line  524 . Host transceiver  502  detects that curve  70   a  starts to rise at time  700   a , reaches predetermined threshold V IH  at time  702   a , and continues rising, Curve  72   a  starts increasing at time  704   a , reaches predetermined threshold V IH  at time  706   a , and continues rising. In case that period P 702   a , the time period from time  702   a  to time  706   a , is shorter than the period T connect  defined in USB standard, then USB peripheral device  54  is determined to be a high/full speed USB device. At time  708   a , host transceiver  502  issues the reset signal to reset  70   a  and  72   a . Host transceiver  502  and device transceiver  542  can then perform data transmission at high/full speed upon completion of the reset. 
         [0035]      FIG. 5   b  shows a waveform detected at Step S 626 , where curve  70   b  is the voltage potential of Data+ signal on Data+ line  522 , curve  72   b  is the voltage potential of Data− signal on Data− line  524 . Host transceiver  502  detects that curve  72   b  starts to rise at time  700   b , reaches predetermined threshold V IH  at time  702   b , and continues rising. Curve  70   b  starts increasing at time  704   b , reaches predetermined threshold V IH  at time  706   b , and continues rising. In case that period P 702   b , the time period from time  702   b  to time  706   b , is shorter than the period T connect  defined in USB standard, then host transceiver  502  determines that USB peripheral device  54  is also a high/full speed USB peripheral device. At time  708   a , host transceiver  502  issues the reset signal to reset  70   a  and  72   a , and then host transceiver  502  and device transceiver  542  perform data transmission at high/full speed upon completion of the reset. 
         [0036]    Apart from the two conditions in  FIGS. 5   a  and  5   b , when the detected voltage potential on the Data+ line exceeds predetermined threshold VIH, but the voltage potential on Data− line remains at approximately Vss, as depicted in  FIG. 2   a , USB peripheral device  54  will be determined as a full speed USB device, thus further determination for a high/full speed USB device is not required. When the detected voltage potential on the Data− line exceeds predetermined threshold VIH, but the voltage potential on Data+ line remains at approximately Vss, as depicted in  FIG. 2   b , USB peripheral device  54  will be determined as a low speed USB device. 
         [0037]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.