Abstract:
A low drop-out DC voltage regulator for regulating a voltage from a DC power supply applied to a load at an output of the regulator and comprising a pass device for controlling flow of current from the power supply to the load so as to control the output voltage at the regulator output, and a feedback loop for controlling the pass device. The feedback loop comprises a resistive feedback path and a capacitive feedback path that includes a feedback capacitive element in series, and comparator means responsive to signals from the feedback paths for applying to the pass device an error signal that is a function of the value of the output voltage relative to a nominal value so as to control the output voltage. The comparator means comprises feedback current producing means for maintaining a common point of the resistive feedback path and the capacitive feedback path at a reference voltage so as to produce a feedback current flowing in the resistive feedback path and in the capacitive feedback path in parallel between the regulator output and the common point, and current comparison means responsive to relative values of the feedback current and of a reference current for producing the error signal.

Description:
FIELD OF THE INVENTION  
       [0001]     This invention relates to a DC voltage regulator and particularly to a low drop-out (LDO) voltage regulator.  
       BACKGROUND OF THE INVENTION  
       [0002]     A DC voltage regulator provides to a load a well-specified and stable DC (‘direct current’) output voltage whose fluctuations from a nominal value are low compared to fluctuations of the power supply that is regulated. The operation of the regulator is based on feeding back an error signal whose value is a function of the difference between the actual output voltage and the nominal value, which is amplified and used to control current flow through a pass device (such as a power transistor) from the power supply to the load. The drop-out voltage is the value of the difference between the power supply voltage and the desired regulated voltage below which regulation is lost. A low drop-out voltage regulator continues to regulate the output voltage effectively until the power supply voltage reduces to a value close to the desired regulated value. A low drop-out voltage regulator is therefore particularly useful in applications where it is powered by the same power supply used to supply the load, since it continues to function almost until the power supply becomes too low to supply the load at the desired voltage in any case.  
         [0003]     The low drop-out nature of the regulator makes it appropriate (over other types of regulators such as dc-dc converters and switching regulators) for use in many applications such as automotive, portable, and industrial applications with an internal power supply, especially a battery. In the automotive industry, the low drop-out voltage is necessary during cold-crank conditions where an automobile&#39;s battery voltage of nominally 12V can drop below 6V, for example. Demand for LDO voltage regulators is also apparent in hand held battery operated products (such as cellular phones, pagers, camera recorders and laptop computers).  
         [0004]     A known LDO voltage regulator comprises a comparator, which is a differential voltage amplifier that produces the feedback error signal by comparing a voltage related to the output voltage to a reference voltage, an intermediate buffer stage responsive to the differential amplifier output, the pass device, and a bypass capacitor coupled to the load. These elements constitute a regulation loop which provides voltage regulation.  
         [0005]     In many known LDO voltage regulators, the bypass capacitor has to have a large capacitance to ensure stability of the operation of the regulator, which is costly, especially since this usually requires the use of an external capacitor. Not only is the cost of the capacitor component itself higher if the component is larger but also the component occupies more space on the circuit board of the regulator. These factors are aggravated if a given device needs several voltage regulators. Moreover, design of the regulator is often complex, and the design complexity increases with the number of different poles in the regulator and with the effects of parasitic impedances and manufacturing tolerances.  
         [0006]     There is a need for an LDO voltage regulator that alleviates some or all of the above disadvantages.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention provides a low drop-out voltage regulator as described in the accompanying claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  is a schematic circuit diagram of a known LDO voltage regulator,  
         [0009]      FIG. 2  is a modelised graph of the gain of the feedback loop of the regulator of  FIG. 1  as a function of frequency,  
         [0010]      FIG. 3  is a schematic circuit diagram of another known LDO voltage regulator,  
         [0011]      FIG. 4  is a modelised graph of the gain of the feedback loop of the regulator of  FIG. 3  as a function of frequency,  
         [0012]      FIG. 5  is a schematic circuit diagram of an LDO voltage regulator in accordance with one embodiment of the invention, given by way of example,  
         [0013]      FIG. 6  is a stability analysis equivalent block diagram of the regulator of  FIG. 5 , and  
         [0014]      FIG. 7  is a modelised graph of transfer functions of the feedback loop of the regulator of  FIG. 5  as a function of frequency. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]      FIG. 1  shows a known LDO voltage regulator that comprises a differential voltage amplifier  1  including a PMOS transistor pair T 1 , T 2  whose source-drain paths are connected in series with a constant current source IS and with respective NMOS transistors T 3  and T 4  whose gates are connected to the connection between the drains of transistors T 1  and T 3 , the output of the amplifier  1  being taken from the connection between the drains of transistors T 2  and T 4 . The regulator of  FIG. 1  also includes an intermediate buffer stage  2  including transistors T 5 , T 6  whose source-drain paths are connected in series across the power supply VSupply, and a pass device T 7  which is a PMOS power transistor whose source-drain path is connected between the power supply VSupply and the load, the gates of transistors T 6  and T 7  being connected to the connection between the drains of transistors T 5  and T 6 . A large external bypass capacitor CL having an equivalent series resistance ESR is connected in parallel with the load.  
         [0016]     The differential amplifier  1  receives a BandGap reference voltage Vbg, on one differential input and on the other differential input receives a voltage proportional to the output voltage of the regulator from a voltage divider comprising two resistors R 1  and R 2  connected in series across the regulator output. The output voltage of the differential amplifier  1  at the connection between the PMOS transistor T 2  and the NMOS transistor T 4  is applied to the gate of the NMOS transistor T 5  and the transistors T 5 , T 6  then apply-this voltage to the gate of the pass device T 7 . These elements constitute a regulation loop which provides low drop-out DC voltage regulation of the output voltage applied to. the external bypass/load capacitor CL. The regulator is supplied with a supply voltage VSupply, for example from a battery, through a current source IS. The battery also supplies power to the load through the pass device T 7  of the regulator.  
         [0017]      FIG. 2  shows a modelised graph of the gain A of the voltage regulation loop against frequency f. Fpout is a dominant pole created by the bypass capacitor CL and depends on the values of CL and the impedance presented by the load (represented here as a resistance RL), Zesr is a ‘zero’ created by the equivalent series resistance ESR of the output capacitor CL and depends on the values of CL and ESR, Fpdiff is a further sub-dominant pole created by the differential amplifier  1  and Fpint is a further sub-dominant pole created by the intermediate stage  2 , depending on the value of RL and the size of the pass device T 7 . It will be appreciated that the use of device T 6  in the intermediate stage  2  in addition to the device T 5  allows pole tracking of the poles Fpout and Fpin as shown by the arrowed dashed lines in  FIG. 2  in response to changes in the current in the load.  
         [0018]     The gain bandwidth GBW of the regulator is given by:  
             GBW   =         A   1     ·     A   2     ·     gm   p         2   ·   π   ·     C   L                 Equation   ⁢           ⁢   1             
 
         [0019]     where A 1  is the gain of the differential amplifier  1 , A 2  is the gain of the intermediate buffer  2 , and gm p  is the transconductance of the pass device T 7 .  
         [0020]     It is found that, to ensure stability, the loop gain must be below 0 dB when the pole Fpint becomes influential and that the ESR ‘zero’ Zesr must be situated close to the pole Fpdiff. Both of these requirements necessitate a large value for the capacitance CL and, in a practical example of this regulator, the value of the capacitance CL is at least 10 μF per 100 mA of output current.  
         [0021]     Some reduction in the bypass capacitance CL is obtained by the known regulator shown in  FIG. 3 . This regulator comprises a DC voltage feedback loop similar to the feedback loop in the regulator of  FIG. 1  and comprising the resistors R 1  and R 2 , a differential amplifier  1  similar to the differential amplifier  1  of  FIG. 1  and a buffer  2  similar to the buffer  2  of  FIG. 1 . The load  3  is represented in  FIG. 3  as a current source, illustrating the more general case where the load presents more than passive impedance.  
         [0022]     In addition, the regulator of  FIG. 3  comprises an AC feedback loop including in series a capacitor Cf and a resistor Rf connected to the source of the DC voltage reference Vref, and a further voltage differential amplifier  4 , similar to the differential amplifier  1  of  FIG. 1 , whose input is responsive to the voltage across the resistor Rf, and hence to the current flowing in the resistor Rf, and whose output is also connected to the input of the buffer  2 .  
         [0023]     It is found that the AC feedback loop with the bypass capacitance Cf creates a very low frequency dominant pole in the DC feedback loop, so that the regulator is stable with smaller values of the bypass capacitor CL than in the regulator of  FIG. 1 . However, it is also found that, when the bypass capacitor CL is further reduced, the output pole comes closer to the input poles and, since there are too many poles in the capacitive feedback loop with this configuration, the result is that the capacitive feedback loop becomes unstable. This appears in the overall loop response as a peak in the gain at a high frequency, as shown in  FIG. 4 . In a practical example of this regulator, the value of the capacitance CL still needs therefore to be at least 1 μF per 100 mA of output current.  
         [0024]      FIG. 5  shows an example of a low drop-out DC voltage regulator in accordance with one embodiment of the present invention. This regulator includes a pass device T 7  controlled by an inverting buffer  2 , like the regulators of  FIGS. 1 and 3 . However the output voltage Vout from the regulator output is sensed through a resistive feedback path  5  and a capacitive feedback path  6  in parallel at a common point  7 . A differential voltage amplifier  8  amplifies any difference in voltage between the common point  7  and a reference voltage Vref. This difference is applied to the gate of a first NMOS transistor  9  of a current mirror pair that also includes a second NMOS transistor  10 . The source-drain conductive path of the first NMOS transistor  9  is connected between the common point  7  and ground and its gate is supplied by the output of the differential amplifier  8 . The output voltage of the amplifier  8  is also applied to the gate of the second NMOS transistor  10 , whose source-drain conductive path is connected in series with a source  11  of a constant current equal to Vref/R 1  between the power supply Vsupply and ground. The connection  12  between the second NMOS transistor  10  and the constant current source  11  is connected to the gate of the NMOS transistor T 5  as input to the inverting buffer  2 .  
         [0025]     In operation, the first NMOS transistor  9  conducts the feedback current flowing in the parallel feedback paths of resistor  5  and capacitor  6  and maintains the voltage of the common point  7  substantially equal to the reference voltage Vref, due to the amplification of any voltage difference by the amplifier  8  applied to the gate of the first NMOS transistor  9 . The same output voltage of the amplifier  8  applied to the gate of the second NMOS transistor  10  causes the second NMOS transistor  10  to conduct the same current. Any difference between the current (Vout−Vref)/R 2  flowing in the second NMOS transistor  10 , mirrored from the first NMOS transistor  9 , and the current Vref/R 1  from the current source  11  constitutes an error signal applied to the buffer  2 . The connection  12  presents a high impedance, so that the error signal appears as an-error voltage.  
         [0026]     The buffer  2  responds to the error signal at the connection  12  corresponding to any difference between the current (Vout−Vref)/R 2  flowing in the second NMOS transistor  10 , mirrored from the first NMOS transistor  9 , and the current Vref/R 1  from the current source  11 . The feedback loop acts to modify the regulator output voltage Vout until the error signal is zero, when  
                 Vout   -   Vref       R   ⁢           ⁢   2       =         Vref     R   ⁢           ⁢   1       ⇒   Vout     =     Vref   ·     (     1   +       R   ⁢           ⁢   2       R   ⁢           ⁢   1         )                 Equation   ⁢           ⁢   2             
 
         [0027]     The presence of the capacitive feedback path including the capacitor  6  forms a very low frequency, dominant pole in the feedback loop. The capacitive path is embedded in the current feedback structure so it has a larger bandwidth and one less pole than a capacitive loop in a voltage feedback structure. This improves the stability of the capacitive path and removes the peaking in the response of the feedback loop that is encountered with the regulator of  FIG. 3 .  
         [0028]     A small capacitor  13  in series with the conductive path of an NMOS transistor  14  are connected in parallel with the conductive path of the second transistor  10  between the connection point  12  and ground. The gate of the transistor  14  is connected to the connection point  12 , so that the transistor  14  acts to present a low resistance that varies as a function of the voltage applied to the gates of the transistors Rz 1  and T 5 , which varies as a function of the output current drawn by the load. The capacitor  13  and transistor  14  reduce the feedback loop gain at high frequencies, where poles due to parasitic capacitances are likely to appear.  
         [0029]      FIG. 6  shows an equivalent block diagram for the purposes of stability analysis of the regulator of  FIG. 5 . The symbols used in  FIG. 6  have the following meanings:  
         [0030]     ro 1 =equivalent resistance at the connection point  12 , forming a high impedance node  
         [0031]     Gm p =transconductance of the T 7 Pass Device  
         [0032]     RL=resistance of the load  3   
         [0033]     R 2 =resistance of the resistor  5   
         [0034]     C 2 =capacitance of the capacitor  6   
         [0035]     A 2 =gain of the inverting buffer  2   
         [0036]     Tv         time constant of the pole formed by the current mirror pair  9  and  10  driven by the amplifier  8   
         [0037]     T 1 =ro 1 .C 1           time constant of the pole formed by the capacitor  13  with the equivalent resistance ro 1  at the connection point  12   
         [0038]     Tz 1 =Rz 1 .C 1           time constant of the ‘zero’ formed by the capacitor  13  with the resistance Rz 1  of the transistor  14  at the connection point  12   
         [0039]     T 2           time constant of the pole formed by the inverting buffer  2   
         [0040]     TL=RL.CL         time constant of the output pole including the load and the bypass capacitor CL  
         [0041]     H T (s)=overall transfer function of the regulator observed by exciting the open-circuit resistive feedback path with the capacitive feedback path through the capacitor  6  active.  
         [0042]     H R (S)=transfer function of the regulator observed by exciting the open-circuit resistive feedback path with the capacitive feedback path through the capacitor  6  open circuit  
         [0043]     H C (s)=transfer function of the regulator observed by exciting the open-circuit capacitive feedback path with the resistive feedback path through the resistor  6  open circuit.  
         [0044]     The overall transfer function is given by  
                   H   T     ⁡     (   s   )       =         H   R     ⁡     (   s   )         (     1   +       H   c     ⁡     (   s   )         )         ⁢     
     ⁢   where           Equation   ⁢           ⁢   3                     H   R     ⁡     (   s   )       =           -       ro   ⁢           ⁢   1       R   ⁢           ⁢   2         ·   A     ⁢           ⁢     2   ·     gm   p     ·   RL   ·     (     1   +       T     Z   ⁢           ⁢   1       .   s       )             (     1   +     T   ⁢           ⁢   1.   ⁢   s       )     ·     (     1   +     T   ⁢           ⁢   2.   ⁢   s       )     ·     (     1   +       T   L     .   s       )     ·     (     1   +       T   V     .   s       )           ⁢     
     ⁢   and           Equation   ⁢           ⁢   4                   H   C     ⁡     (   s   )       =       A   ⁢           ⁢     2   ·     gm   p     ·   RL   ·   ro     ⁢           ⁢     1   ·   C     ⁢           ⁢     2   ·   s   ·     (     1   +       T     Z   ⁢           ⁢   1       .   s       )             (     1   +     T   ⁢           ⁢   1.   ⁢   s       )     ·     (     1   +     T   ⁢           ⁢   2.   ⁢   s       )     ·     (     1   +       T   L     .   s       )     ·     (     1   +       T   V     .   s       )                 Equation   ⁢           ⁢   5             
 
         [0045]     s being the Laplace constant (jω=j.2πf).  
         [0046]     At steady state, where s is substantially zero:  
                   H   C     ⁡     (   s   )       =   0     ⁢     
     ⁢   and           Equation   ⁢           ⁢   6                   H   T     ⁡     (   s   )       =         H   R     ⁡     (   s   )       =         -       ro   ⁢           ⁢   1       R   ⁢           ⁢   2         ·   A     ⁢           ⁢     2   ·     gm   p     ·   RL                 Equation   ⁢           ⁢   7             
 
         [0047]     At low frequencies, that is to say slow changes in the signals, the values of T 1 .s, T 2 .s, T L .S, T V .s, and T Z1 .s are all much smaller than 1 and Equation 3 reduces to:  
                 H   T     ⁡     (   s   )       =           -       ro   ⁢           ⁢   1       R   ⁢           ⁢   2         ·   A     ⁢           ⁢     2   ·     gm   p     ·   RL         (     1   +     A   ⁢           ⁢     2   ·     gm   p     ·   RL   ·   ro     ⁢           ⁢     1   ·   C     ⁢           ⁢     2   ·   s         )               Equation   ⁢           ⁢   8             
 
         [0048]     The dominant pole is formed by the time constant A 2 .gm p .RL.ro 1 .C 2  . As soon as the factor A 2 .gm p .RL.ro 1 .C 2 .s is much greater than 1, H T (S) tends towards  
                 H   T     ⁡     (   s   )       =     -     1     R   ⁢           ⁢     2   ·   C     ⁢           ⁢     2   ·   s                   Equation   ⁢           ⁢   9             
 
         [0049]     For frequencies below GBW C , where the transfer function of the capacitive feedback path falls to 0 dB, there is approximate cancellation between the poles of H R (S) and the poles of H C (s), producing a linear decline of H T (S) in a 1st order approximation. The frequency ranges where the 2 nd  and higher order influence of the poles Tv, T 1 , Tz 1 , T 2 , TL and Tz 1  appears are indicated in  FIG. 7  for one example of implementation of this embodiment of the invention.  
         [0050]     It is found that the capacitance of the bypass capacitor CL can be reduced very significantly compared to the regulators. of  FIGS. 1 and 3  and, in one example of implementation of an embodiment of the invention, the regulator is found to remain stable with a capacitance CL of 100 nF/100 mA.  
         [0051]     Since the feedback current flows in the resistive feedback path and in the capacitive feedback path in parallel, and the capacitive feedback path forms a very low frequency dominant internal pole, all the sub-dominant poles of the regulator tend to be cancelled. It will be appreciated that this reduces the effect of complex poles, or even eliminates them in practice, increasing design robustness concerning regulation stability.  
         [0052]     These factors simplify analysis and design of the regulator as overall constraints can be partitioned at sub-block level, reducing design cycle time.