Abstract:
An apparatus and method for measuring power consumed during operation of an integrated circuit. The apparatus including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of integrated circuits; more specifically, it relates to circuits and the methods of measuring power consumption of integrated circuits. 
       BACKGROUND OF THE INVENTION 
       [0002]    Mitigating power consumption is a requirement in modern integrated circuit design. Existing methods of power consumption mitigation are based on a proactive preventative type approach using, for example, lower power elements, sleep and power-down modes and voltage islands. However, the majority of non-clocked power in a digital design is data dependent. Since the data is usually not known ahead of time it is impossible to accurately predict the power consumption of integrated circuits using these aforementioned power consumption mitigation methods. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove. 
       SUMMARY OF THE INVENTION 
       [0003]    A first aspect of the present invention is an apparatus for measuring power consumed during operation of an integrated circuit, comprising: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on the output based on an input data signal presented to the input; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal. 
         [0004]    A second aspect of the present invention is a method for measuring power consumed during operation of an integrated circuit, comprising: providing a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on the output based on an input data signal presented to the input; measuring an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and storing, in a memory element, a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0006]      FIG. 1  is an exemplary circuit diagram of an integrated circuit according to a first embodiment the present invention; 
           [0007]      FIG. 2  is an exemplary circuit diagram of an integrated circuit according to a second embodiment the present invention; 
           [0008]      FIG. 3  is an exemplary circuit diagram of an integrated circuit according to a third embodiment the present invention; 
           [0009]      FIG. 4  is an exemplary circuit diagram of an integrated circuit according to a fourth embodiment the present invention; 
           [0010]      FIG. 5  is a flowchart of a first method according to the embodiments of the present invention; 
           [0011]      FIG. 6  is a flowchart of a second method according to the embodiments of the present invention; 
           [0012]      FIG. 7  is a flowchart of a third method according to the embodiments of the present invention; and 
           [0013]      FIG. 8  is a flowchart of a fourth method according to the embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0014]    The terms process data and power data are used to distinguish data that is logically processed by a logic circuit (process data) from data representing the power consumed by the logic circuit in processing the process data (power data). Input data, intermediate data and output data are cases of process data relative to the input and output of the processing circuit and stages within the processing circuit. 
         [0015]      FIG. 1  is an exemplary circuit diagram of an integrated circuit according to a first embodiment the present invention. In  FIG. 1 , an integrated circuit  100  includes an input latch  105 , a first processing stage  110 , a first intermediate latch  115 , a second processing stage  120 , a second intermediate latch  125 , a third processing stage  130  and an output latch  135 , all connected in series. Processing stages  110 ,  120  and  130  represent a processing circuit that is to be monitored for power consumption. While only three processing stage are illustrated in  FIG. 1  and processing stages  110 ,  120  and  130  are shown in series so the output of data from processing stage  110  is the input data to processing stage  120  and the output of data from processing stage  120  is the input data to processing stage  130 , there may be more or less processing stages and the logic cone may comprise series and parallel data paths. The input data signal presented on input latch  105  is digital data. Input latch  105  and output latch  135  may be replaced with internal pins (i.e., connections to other circuits) or I/O pads (i.e., off-chip connections). Internal latches  115  and  125  may be independently replaced with registers or eliminated so there are direct wire connections between processing stages  110 ,  120  and  130 . Latches  105 ,  115 ,  125  and  135  may independently be latches in a serial chain of latches (e.g. a scan chain). Latches  105 ,  115 ,  125  and  125  may include logical functions. In one example, processing circuits  110 ,  120  and  130  include one or more logic gates. Examples of logic gates include AND gates, OR gates, NAND gates, NOR gates and multiplexers. Processing data is defined as performing a logical or arithmetic operation on the data. The operation may or may not change the data. 
         [0016]    First processing stage  110  is supplied with a first power supply V 1 , second processing stage  120  is supplied with a second power supply V 2  and third processing stage  130  is supplied with a third power supply V 3 . In one example, power supplies V 1 , V 2  and V 3  are independent power supplies and processing stages  110 ,  120  and  130  are voltage islands. A voltage island is defined as a region of an integrated circuit chip that is supplied power independently from and power-wise isolated from other regions of the integrated circuit chip. In one example, power supplies V 1 , V 2  and V 3  are independent buses from a common power supply. Connected between first processing stage  110  and power supply V 1  is a first power measurement circuit  140 . Connected between second processing stage  120  and power supply V 2  is a second power measurement circuit  145 . Connected between third processing stage  130  and power supply V 3  is a third power measurement circuit  150 . The respective outputs of each of measurement circuits  140 ,  145  and  150  are connected to a memory element  155 . Respective outputs of each of latches circuits  105 ,  115  and  125  are also connected to memory element  155 . 
         [0017]    Each of measurement circuits  140 ,  145  and  150  are configured to measure the power consumed when input data is processed by respective processing stages  110 ,  120  and  130 . Each of measurement circuits  140 ,  145  and  150  may independently measure power, for example, by (i) measuring voltage and current flow to processing stage and calculating power consumed, (ii) by measuring voltage drop across a shunt with known resistance which may be a wire in the power network or (iii) by measuring current if the voltage is constant. In one example, each of elements  140 ,  145  and  150  includes means for converting the power measurement into power data and for storing the power data in memory element  155 . In one example, a data conversion circuit is coupled between each measurement circuit  140 ,  145  and  150  and memory element  155 . The data (or a pointer to that data) that was input to each processing stage as the power consumption was measured is also stored in memory element  155  where the power data and process data are associated to each other. Note, the actual process data need not be stored but metadata may be stored. Metadata is a pointer to memory device and location in that device where the actual process data is stored. This requires logic functions within latches  105 ,  115  and  125  to generate the pointers and additional memory to store the process data. Memory element  155  maybe portioned into a tag section (described infra) and an actual process data section. Association may be, for example by order, timestamp or information contained in the process data or metadata. 
         [0018]    In a multistage pipeline as illustrated in  FIG. 1 , each processing stage is generating power data simultaneously. In the following example, based on  FIG. 1 , association is by ordering. In Table I, process data (or metadata), processing stage that processed the process data, and calculated power consumption (or power data allowing calculation of power consumption) is associated with a Tag ID. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                   
                 PROCESS 
                 PROCESSING 
                 POWER 
               
               
                   
                 TAG ID 
                 DATA 
                 STAGE 
                 CONSUMED 
               
               
                   
                   
               
             
             
               
                   
                 21 
                 A1 
                 1 
                 1.3 
               
               
                   
                 22 
                 B2 
                 2 
                 2.6 
               
               
                   
                 23 
                 C3 
                 3 
                 5.4 
               
               
                   
                 24 
                 D1 
                 1 
                 1.0 
               
               
                   
                 25 
                 A2 
                 2 
                 0.4 
               
               
                   
                 26 
                 B3 
                 3 
                 5.1 
               
               
                   
                   
               
             
          
         
       
     
         [0019]    In TABLE II, the Tags (an entry in memory element  155 ) from TABLE I stored in memory as illustrated. Tags include the stage, process data and power data. Tag IDs are the order in which tags are stored. Using circuit  100  of  FIG. 1 , as process data is processed through the stages power consumption can be associated with each intermediate result. For example, input data stream A is input data A1 as input to stage  1 , intermediate data A2 as input to stage  2  and intermediate data A3 as input to stage  3 . Process data B is B1 as input to stage  1 , B2 as input to stage  2  and B3 as input to stage  3 . 
         [0000]    
       
         
               
               
             
           
               
                   
                 TABLE II 
               
               
                   
                   
               
             
             
               
                   
                 1, A1, 1.3 
               
               
                   
                 2, B2, 2.6 
               
               
                   
                 3, C3, 5.4 
               
               
                   
                 1, D1, 1.0 
               
               
                   
                 1, A2, 0.4 
               
               
                   
                 3, B3, 5.1 
               
               
                   
                 1, E1, 7.0 
               
               
                   
                 2, D2, 4.2 
               
               
                   
                 3, A3, 3.9 
               
               
                   
                   
               
             
          
         
       
     
         [0020]    Returning to TABLE I, it can be seen that the data stream of data signal A (A1 to A2 to A3) is included in Tags 21 and 25 and is non-sequential. It is possible to order the tags before storing them so data streams are sequential. A data stream is defined as the process data from the input data signal to a processing circuit to the output data signal of the processing circuit including the intermediate data generated by stages within the processing circuit. 
         [0021]    Turning to  FIG. 5 ,  FIG. 5  is a flowchart of a first method according to the embodiments of the present invention. Steps  200 ,  205 ,  215 ,  220  and  225  are performed for each processing stage independently. In step  200 , a tag ID is created. In step  205 , power consumption is measured and in step  215  power data is generated. In step  220 , the power data is stored in memory and in step  225  the process data is stored in memory. The sequence that steps  200 ,  205 ,  215 ,  220  and  225  are performed in may vary depending upon the actual circuit implementation. 
         [0022]      FIG. 2  is an exemplary circuit diagram of an integrated circuit according to a second embodiment the present invention. In  FIG. 2 , an integrated circuit  160  is similar to integrated circuit  100  of  FIG. 1  except latches (or registers or logic circuits)  165 ,  170  and  175  are included and instead of the respective outputs of each of measurement circuits  140 ,  145  and  150  being connected to memory element  155  they are connected to respective latches  165 ,  170  and  175  and latches  165 ,  170  and  175  are connected to memory element  155 . Latches  165 ,  170  and  175  combine power data with process data (or metadata) before the data is sent to memory element  155 . This simplifies wiring and generation and control of Tag IDs. The Tags are the same as those illustrated in TABLE II. 
         [0023]    Turning to  FIG. 6 ,  FIG. 6  is a flowchart of a second method according to the embodiments of the present invention. Steps  230  through  250  are performed for each processing stage independently. In step  230 , a tag ID is created. In step  235 , power consumption is measure and in step  235  power data is generated. In step  240 , the power data is attached to the process data in step  225  the combined power/process data is stored in memory. The sequence that steps  230 ,  235 ,  240 ,  245  and  250  are performed in may vary depending upon the actual circuit implementation except steps  235  and  240  are performed before step  245  and step  250  is performed after step  245 . 
         [0024]      FIG. 3  is an exemplary circuit diagram of an integrated circuit according to a third embodiment the present invention. In  FIG. 3 , an integrated circuit  180  is similar to integrated circuit  160  of  FIG. 2  except latches  170 A and  175 A replace latches  170  and  175  respectively, input latch  105  is connected to memory element  155 , there are no connections between latches  115  and  170 A or latches  125  and  175 A, and instead of each of latches  165 ,  170 A and  175 A being connected to memory element  155 , only latch  175 A is connected to memory unit  175 A with latch  165  being connected to latch  170  and latch  170  being connected to latch  175 A. Latch  170 A includes logic to add the power measurement data from latch  165  to the power measurement data from measurement circuit  145  and store the sum. Latch  175 A includes logic to add the power measurement data from latch  170 A to the power measurement data from measurement circuit  150  and store the sum. This arrangement of latches allows the power measured by power measurement circuits  140 ,  145  and  150  to be added before being stored in memory unit  180  and the total power associated with processing a particular process data through all three stages. The Tags for integrated circuit  180  are illustrated in TABLE III. These tags do not include stage identifiers. Timed control of the process input sequence to latch  105  is required in order associate the input process data on latch  105  with the output power data on latch  175 A properly. No new data can be inputted to latch  105  until data is outputted from latch  175 A. 
         [0000]    
       
         
               
               
             
           
               
                   
                 TABLE III 
               
               
                   
                   
               
             
             
               
                   
                 A, 6.5 
               
               
                   
                 B, 7.4 
               
               
                   
                 C, 5.4 
               
               
                   
                 D, 4.0 
               
               
                   
                   
               
             
          
         
       
     
         [0025]    Turning to  FIG. 7 ,  FIG. 7  is a flowchart of a third method according to the embodiments of the present invention. Steps  255 ,  275  and  280  are performed for each new process data entering process stage  1 . Steps  260 ,  265  and  270  are performed for each processing stage independently. In step  255 , a tag ID is created. In step  260 , power consumption is measure and in step  265  power data is generated. In step  270 , for the second and third stages, the power data from the previous processing stage is added to the power data from the current processing stage. In step  275 , the power data is stored in memory and in step  280  the process data is stored in memory. The sequence that steps  255 ,  260 ,  265 ,  270 ,  275  and  280  are performed in may vary depending upon the actual circuit implementation except steps  265  and  270  are performed before step  275 . 
         [0026]      FIG. 4  is an exemplary circuit diagram of an integrated circuit according to a fourth embodiment the present invention. In  FIG. 4 , an integrated circuit  185  is similar to integrated circuit  180  of  FIG. 3  except latch  175 B replaces latch  175 A and the output of latch  105  is connected to latch  175 A instead of memory element  155 . Latch  175 B includes logic to add the power measurement data from latch  170 A to the power measurement data from measurement circuit  150  and store the sum. Latch  175 B also includes storage elements to store the data presented to latch  105  and pass that data along with the summed power data to memory  155 . The Tags are the same as those illustrated in TABLE II. 
         [0027]    Turning to  FIG. 8 ,  FIG. 8  is a flowchart of a fourth method according to the embodiments of the present invention. Steps  285 ,  305  and  100  are performed for each new process data entering process stage  1 . Steps  290 ,  295  and  300  are performed for each processing stage independently. In step  285 , a tag ID is created. In step  290 , power consumption is measure and in step  295  power data is generated. In step  300 , for the second and third stages, the power data from the previous processing stage is added to the power data from the current processing stage. In step  305 , the power data attached to the process data and in step  310 , the combined power and process data is stored in memory. The sequence that steps  285 ,  290 ,  295 ,  300 ,  305  and  315  are performed in may vary depending upon the actual circuit implementation except steps  295  and  300  are performed before step  305  and step  305  is performed before step  310 . 
         [0028]    Thus the present invention provides circuits designs, circuits and methods for determining data dependent power consumption of integrated circuits. 
         [0029]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.