Abstract:
A serial-flash, EPROM, EEPROM, or flash EEPROM nonvolatile memory in AMG configuration includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage.

Description:
TECHNICAL FIELD 
     The present invention relates to a serial-flash, EPROM, EEPROM and flash EEPROM nonvolatile memory in AMG (Alternate Metal Ground) configuration. 
     BACKGROUND OF THE INVENTION 
     As is known, floating gate EEPROM memory cells are programmed (written and/or erased) by Fowler-Nordheim effect, by injecting or extracting charges, through a thin tunnel oxide region, by applying appropriate voltages between the terminals of the cells. In particular, it is necessary to supply high voltages to control terminals of cells to be programmed, which are selected by enable transistors. 
     For greater clarity, reference is made to FIG. 1, which shows an example of a known architecture of an EEPROM memory array  1 , belonging to a memory device  15 . The memory array  1  comprises a plurality of cells  2 , arranged on rows and columns, and each comprises a sense transistor  3  and a select transistor  4 . The cells  2  are connected to one another in groups, to form memory bytes, comprising each for example eight cells  2 . FIG. 1 shows two cells  2  belonging to a single byte. 
     In detail, the control gate terminals of the sense transistors  3  that belong to a single byte are connected by a gate line  5  to a source terminal of a respective byte enable transistor  6 . In addition, the sense transistors  3  have source terminals connected to a common source line  8 , which can be alternatively grounded or left floating by a selector  13 , and drain terminals, each of which is connected to a source terminal of a respective select transistor  4 . 
     The drain terminals of the select transistors  4  are each connected to a respective bit line  10 . FIG. 1 shows two bit lines  10  that belong to the same byte, and are designated respectively as BLO and BL 7 . The select transistors  4  of cells  2  which belong to a single array row also have gate terminals which are connected to a word line  11 . 
     The byte enable transistor  6 , which comprises an N-channel MOS transistor, has a gate terminal connected to the word line  11 , and a drain terminal connected to a control gate line  12 . 
     The known devices have some disadvantages. In particular, during erasing of the cells  2 , the control gate line  12 , via the byte enable transistor  6 , must feed the control gate terminals of the cells  2  to be erased with high voltages, for example 14 V. However, a voltage drop exists between the drain and source terminals of the byte enable transistor  6  and thus the control gate line  12  must be set to a voltage higher than that required for erasing. 
     In addition, the byte enable transistor  6  has a high threshold voltage, since it is N-channel, and, as shown in FIG. 2, it is formed directly in a P-type substrate region  20  of the memory device  15 . In detail, the byte enable transistor  6  comprises a source region  21  and a drain region  22 , both of N + type, embedded in the substrate region  20 , and defining a channel region  23 . In addition, the substrate region  20  defines a bulk region. Normally, the substrate region  20  is at a voltage close to 0 V, and thus, during erasing, high voltages are established between the source region  21  and the bulk of the byte enable transistor  6 . 
     It is known that the threshold voltage of MOS transistors increases as the bulk-source voltage increases (so-called body effect). Consequently, because of this high voltage, there is a considerable increase in the threshold voltage of the byte enable transistor  6 , and the latter can transfer to the source terminal a reduced portion of the voltage that is present at the drain terminal. Therefore, it is necessary to generate and feed the drain terminal of the byte enable transistor  6  with a voltage that is considerably higher than the voltage that must be applied to the control gate terminals of the cells  2 . This requires pumping circuits of an appropriate size, as well as involving higher energy consumption. In addition, it is necessary to provide specific processing phases to produce high voltage components, with high breakdown voltage. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides a non-volatile memory that is free from the disadvantages described, and in particular reduces the body effect on the byte enable transistors, includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the invention, an embodiment is now described, purely by way of non-limiting example, and with reference to the attached drawings, wherein: 
     FIG. 1 illustrates a simplified circuit diagram of a nonvolatile memory of known type; 
     FIG. 2 shows a cross-section of a component used in the memory in FIG. 1; 
     FIG. 3 illustrates a simplified circuit diagram of a nonvolatile memory according to the present invention; 
     FIG. 4 shows a cross-section of a component used in the memory in FIG. 3; and 
     FIG. 5 illustrates a simplified circuit diagram similar to that in FIG. 3, for a different type of memory. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3, in which parts equal to those illustrated in FIG. 1 are indicated by the same reference numbers, shows an EEPROM memory array  25  that belongs to a nonvolatile memory  100  according to an embodiment the present invention. 
     In detail, the memory array  25  comprises a plurality of cells  2  arranged on rows and columns, each of which comprises a sense transistor  3  and a select transistor  4 , and is connected to form memory bytes. The bytes can be selected by a row decoder  45  and a column decoder  46 , to which they are connected respectively via word lines  11  and control gate lines  12 , as illustrated in detail hereinafter. 
     In FIG. 1, the sense transistors  3  have control gate terminals connected to a gate line  5 ; source terminals connected to a common source line  8 , and drain terminals, each connected to a source terminal of a respective select transistor  4 . The drain terminals of the select transistors  4  are each connected to a respective bit line  10 , and the gate terminals are connected to a word line  11 . 
     The memory  100  differs from the memory  15  in FIG. 1 in that the byte enable transistor, here indicated at  30 , is of P-channel type, and has a source terminal  31  (defining an input terminal) connected to the control gate line  12 , a drain terminal  32  (defining an output terminal) connected to the gate line  5 , and a gate terminal  33  (defining a control terminal) connected to the word line  11 . In detail, the source terminal  31  receives an input voltage V IN  via the control gate line  12 , and the drain terminal  32  supplies an output voltage V OUT  to the gate line  5 . In addition, the byte enable transistor  30  has a bulk terminal  34  connected to the source terminal  31 . 
     In particular, as shown in detail in FIG. 4, the byte enable transistor  30  comprises an N-type well  35 , embedded in a substrate region  55 . Inside the well  35 , forming the bulk of the byte enable transistor  30 , there are a source region  36  and a drain region  37 , both of P + -type, which are spaced from each other and delimit between them a channel region  38 ; in addition, a bulk polarization region  39  of N + -type is formed inside the well  35 . The source terminal  31  and the bulk terminal  34  are connected respectively to the source region  36  and bulk bias region  38 , and to each other. Thereby, the source voltage of the source region  36  and the bulk voltage of the well  35  have the same value as the input voltage V IN . Therefore the PN junction (indicated as  40  in FIG. 4) formed by the source region  36  and the well  35 , is prevented from being directly biased, when a positive voltage is supplied to the source terminal  31 . 
     During erasing, when the cells  2  (FIG. 3) are selected, the control gate line  12  is set to an erase voltage, the value of which can be, for example, between approximately  7  and 15 V, according to the type of memory and process used, and the word line  11  is set to a higher voltage than the erase voltage. Consequently, an input voltage V IN  which has the same value as the erase voltage is supplied to the source and bulk terminals  31 ,  34 , which are connected to the control gate line  12  and to each other. Thereby, the source region  36 , the bulk bias region  39  and the well  35  are biased to the same input voltage V IN . Since the bulk-source voltage is zero, the body effect is theoretically zero, and the input voltage V IN  is transferred to the output of the drain terminal  32 , and thus to the gate line  5  and to the gate terminals of the cells  2  to be erased. When an appropriate voltage is supplied to the gate terminal of the byte enable transistor  30 , the drain-source voltage drop can become very low (for example 0.2 V), and the output voltage V OUT  is substantially the same as the input voltage V IN . Consequently, the gate terminals of the cells  2  to be erased are set to a voltage that is close to the erase voltage present on the control gate line  12 . 
     The advantages of the present invention are apparent from the foregoing description. In fact, the use of a byte enable transistor of the type described allows the control gate lines to be supplied with a voltage having a value close to that required by the control gate terminals of the cells  2 , thus it is no longer necessary to generate voltages that are far higher than the operative voltages normally used. 
     In addition, since the various regions which form the byte enable transistor  30  are all at virtually the same voltage, there are no high-voltage junctions, and it is therefore not necessary for the transistor to be manufactured as a high voltage component having high breakdown voltage. This is a financial advantage, since the manufacture of the byte enable transistor  30  does not require specific process steps. 
     Finally, it is apparent that modifications and variants can be made to the memory described, without departing from the scope of the present invention. 
     In particular, it is not essential to bias the well  35  to the same voltage as the source region  36 , although this is particularly advantageous; in fact, it is sufficient to prevent the PN junction  40  from being directly biased, and to prevent the increase of threshold voltage caused by body effect. Therefore, instead of being connected to the source terminal  31 , the bulk terminal  34  can be connected to a different supply source, for example greater than or equal to the erase voltage. 
     The present solution can be applied to all non-volatile memories that include N-channel byte enable transistors, as required at least in some operative conditions of the memory, for example during erasing, to transfer high voltages, and subject to the body effect. For example, FIG. 5 shows a flash or EPROM cell  50  of a memory  70 , having a drain terminal connected to a bit line  51 , a gate terminal connected to a word line  52 , and a source terminal connected to a source line  53 . The bit line  51  is selected by a column decoder  65 ; the word line  52  is selected by a row decoder  55 . In detail, the word line  52  is connected to the drain terminal  62  of a PMOS transistor, which hereinafter, for consistency with FIG. 3, is called enable transistor  54 . The enable transistor  54  has source terminal  60  receiving the input voltage V IN  and connected to the bulk terminal  61  and gate terminal  63  receiving from the line decoder  55  a control signal of an appropriate value, as will be apparent to persons skilled in the art. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.