Abstract:
A method for fabricating a PCRAM includes forming a switching element on a semiconductor substrate, forming an interlayer dielectric layer of a multilayer-structure by sequentially stacking a plurality of material layers having different etching properties on the semiconductor substrate having the switching element formed thereon, and by patterning the plurality of material layers to have different lengths or different side shapes, forming a heating electrode on sidewalls of the interlayer dielectric layer and an upper surface of the switching element, and forming a phase change material layer to fill a space inside of the heating electrode.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean patent application number 10-2010-0074017, filed on Jul. 30, 2010, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a nonvolatile memory apparatus, and more particularly, to a phase change random access memory (PCRAM) and a method for fabricating the same. 
         [0004]    2. Related Art 
         [0005]    A PCRAM causes a phase change of a phase change material by applying joules of heat to the phase change material through a heating electrode serving as a heater. Accordingly, the PCRAM records/erases data by using an electrical resistance difference between a crystalline state and amorphous state of the phase change material. 
         [0006]    As such, the PCRAM may transfer heat to the phase change material through the heating electrode or release the applied heat from the phase change material to the outside. In order to increase a driving speed, the heat releasing speed should be increased. 
       SUMMARY 
       [0007]    A PCRAM having an increased driving speed and a method for fabricating the same are described herein. 
         [0008]    In one exemplary embodiment of the present invention, a method for fabricating a PCRAM includes of: forming a switching element on a semiconductor substrate; forming an interlayer dielectric layer of a multilayer-structure by sequentially stacking a plurality of material layers having different etching properties on the semiconductor substrate having the switching element formed thereon, and by patterning the plurality of material layers to have different lengths or different side shapes; forming a heating electrode on sidewalls of the interlayer dielectric layer and an upper surface of the switching element; and forming a phase change material layer to fill a space inside of the heating electrode. 
         [0009]    In another exemplary embodiment of the present invention, a PCRAM includes: a switching element formed on a semiconductor substrate; an interlayer dielectric layer of a multilayer-structure formed on the semiconductor substrate, exposing the switching element, and having a raised and grooved side surface; a heating electrode formed on sidewalls of the interlayer dielectric layer and an upper surface of the switching element; and a phase change material layer formed to fill a space inside of the heating electrode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    Features, aspects, and embodiments of the present invention will be more clearly understood from the following detailed description and the accompanying drawings, in which: 
           [0011]      FIGS. 1 to 8  are cross-sectional views illustrating a method for fabricating a PCRAM according to one exemplary embodiment of the present invention; and 
           [0012]      FIG. 9  is a cross-sectional view illustrating a method for fabricating a second interlayer dielectric layer of a PCRAM according to another exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Hereinafter, a PCRAM and a method for fabricating the same according to the present invention will be described below with reference to the accompanying drawings through exemplary embodiments. 
         [0014]      FIGS. 1 to 8  are cross-sectional views illustrating a method for fabricating a PCRAM according to one exemplary embodiment of the present invention. 
         [0015]    Referring to  FIG. 1 , an isolation layer  105  is formed in desired portions of a semiconductor substrate  100 , thereby defining a plurality of active areas. A method of forming the isolation layer (e.g., an STI process) is known in the art and omitted for the description purpose. Impurities are implanted into the respective active areas at a desired depth, thereby forming junction-area-shaped word lines (hereinafter, referred to as junction word lines)  110 . 
         [0016]    A first interlayer dielectric layer  115  is formed by depositing a first interlayer material on the semiconductor substrate  100  having the junction word lines  110  formed therein. Then, the first interlayer dielectric layer  115  is etched to expose a desired portion of each junction word line  110 , thereby forming a diode contact hole (not illustrated). 
         [0017]    At this time, the diode contact hole may be positioned in the vicinity of an intersection point between the junction word line  110  and a bit line to be subsequently formed. A diode  120  serving as a switching element is formed in the diode contact hole. In this exemplary embodiment, the diode  120  may include a PN diode. 
         [0018]    The PN diode  120  may be formed by the following process: an n-type selective epitaxial growth (SEG) layer is formed in the diode contact hole, and p-type impurities are implanted onto the n-type SEG layer to form the PN diode  120 . 
         [0019]    When a metal word line (not illustrated) is interposed between the diode  120  and the junction word line  110  in consideration of the resistance of the junction word line  110 , the diode  120  may be implemented as a Schottky diode formed of a polysilicon layer. 
         [0020]    A transition metal layer (not illustrated) is deposited on the resultant substrate structure having the diode  120  formed therein, and a heat treatment is performed on the resultant substrate structure to selectively form an ohmic contact layer  125  on the diode  120 . Then, the remaining transition metal layer is removed. 
         [0021]    Referring to  FIGS. 2 and 3 , a plurality of material layers  130   a  having different etching properties are sequentially deposited on the resultant substrate structure  100  having the ohmic contact layer  125  formed therein, and then patterned to form an interlayer dielectric pattern  130   b  having heating electrode contact holes  121  and  122  which expose the ohmic contact layer  125 . The interlayer dielectric pattern  130   b  has a multilayer structure. 
         [0022]    More specifically, first to fifth material layers  131   a  to  135   a  are sequentially deposited on the resultant substrate structure having the ohmic contact layer  125  formed therein. Then, the multilayer-structure interlayer dielectric pattern  130   b , having the heating electrode contact holes  121  and  122  which expose the upper surface of the ohmic contact layer  125 , is formed by a first etching process in which a wet etching method using CF 4  solution or CHF 3  solution or a dry etching method is applied. 
         [0023]    At this time, the first and fifth material layers  131   a  and  135   a  of  FIG. 2  are material layers for forming first and fifth dielectric patterns  131   b  and  135   b , respectively, formed at the lowermost and uppermost parts of the interlayer dielectric pattern  130   b  of  FIG. 3 . The first and fifth dielectric patterns  131   b  and  135   b  may be formed of silicon nitride. 
         [0024]    The second and fourth material layers  132   a  and  134   a  of  FIG. 2  are material layers for forming second and fourth dielectric patterns  132   b  and  134   b , respectively, formed between the first and fifth dielectric patterns  131   b  and  135   b  of  FIG. 3 . The second and fourth dielectric patterns  131   b  and  135   b  may be formed of silicon oxide or silicon oxynitride. 
         [0025]    The third material layer  133   a  of  FIG. 2  is a material layer for forming a third dielectric pattern  133   b  formed between the second and fourth dielectric patterns  132   b  and  134   b  of  FIG. 3 . The third dielectric pattern  133   b  may be formed of any material selected from a group consisting of a metal layer such as W, Ti, Mo, Ta, and Pt, a metal nitride layer such as TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, and TaAlN, a silicide layer such as TiSi and TaSi, an alloy layer such as TiW, and a metal oxide (nitride) layer such as TiON, TiAlON, WON, TaON, and IrO 2 , in order to increase the thermal conductivity of a heating electrode  140  to be subsequently formed. 
         [0026]    In this exemplary embodiment, the material layers having is different properties are alternately deposited to have a raised and grooved side surface. The positions of the first to fifth material layers  131   a  to  135   a  are not limited to the structure illustrated in  FIGS. 2 and 3 , and may be changed in other exemplary embodiments. 
         [0027]    Referring to  FIG. 4 , a second etching process is performed on the resultant substrate structure having the multilayer-structure interlayer dielectric pattern  130   b , thereby forming a second interlayer dielectric layer  130  of a multilayer-structure having a raised and grooved side surface. 
         [0028]    More specifically, the second etching process, in which a dry etching method or a wet etching method using any one of a HF solution, buffered oxide etch (BOE), and a mixture of SiO 2  and SiN 2  is applied, is performed on the resultant substrate structure having the interlayer dielectric pattern  130   b , thereby removing/etching portions of the second and fourth dielectric patterns  132   b  and  134   b . Accordingly, second and fourth dielectric layers  132  and  134  may be formed to have a smaller length than first, third, and fifth dielectric layers  131 ,  133 , and  135 . At this time, the second and fourth dielectric layers  132  and  134  may be formed of silicon oxide such that they can be etched to have a different length from the other dielectric layers. 
         [0029]    However, the second interlayer dielectric layer  130  according to this exemplary embodiment is not limited to the structure of  FIG. 4 . Referring to  FIG. 9 , the second interlayer dielectric layer  130  may be formed in such a manner that the dielectric layers  131 ,  133 ,  135 ,  136 , and  137  of the respective layers have different shapes. Similar to the second interlayer dielectric layer  130  of  FIG. 4 , the second interlayer dielectric layer  130  of  FIG. 9  may be formed by performing the second etching process, in which a dry etching method or a wet etching method using any one etching material of a HF solution, BOE, and a mixture of SiO 2  and SiN 2  is applied, on the resultant substrate structure having the interlayer dielectric pattern  130   b  formed therein. In this case, the second interlayer dielectric layer  130  of  FIG. 9  may be formed in such a manner that side surfaces of the second and fourth dielectric layers  136  and  137  are curved/rounded. At this time, the second and fourth dielectric layers  136  and  137  may be formed of silicon oxynitride so as to have a curved/rounded shape as described above. 
         [0030]    Where the second interlayer dielectric layer  130  of the multilayer-structure is formed in the above-described manners, a contact area between the second interlayer dielectric layer  130  and a heating electrode to be subsequently formed may be increased. As the surface area of the heating electrode is increased, the transmission speed of heat may be increased. As a result, the driving speed of the memory may be increased. 
         [0031]    Referring to  FIG. 5 , the heating-electrode contact holes  121  and  122  of the resultant substrate structure having the second interlayer dielectric layer  130  of the multilayer-structure formed therein are filled with one or more conductive materials consisting of a metal layer such as W, Ti, Mo, Ta, and Pt, a metal nitride layer such as TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, and TaAlN, a silicide layer such as TiSi and TaSi, an alloy layer such as TiW, and a metal oxide (nitride) layer such as TiON, TiAlON, WON, TaON, and IrO 2 . 
         [0032]    The conductive material filling the heating electrode contact holes  121  and  122  is etched through an etch back process to remain on the sidewalls of the second interlayer dielectric layer  130  and the bottom of the heating electrode contact holes  121  and  122 , thereby forming the heating electrode  140 . 
         [0033]    At this time, a chemical vapor deposition (CVD) method or a deposition method using TiCl 4  may be used to deposit the conductive material for forming the heating electrode  140 . In this case, the conductive material may be smoothly grown on the side walls of the second interlayer dielectric layer  130  having a raised and grooved side surface. 
         [0034]    Referring to  FIG. 6 , a spacer  145  is formed on the sidewalls of the heating electrodes  140 . 
         [0035]    The spacer  145  is formed by the following process. First, a spacer insulation layer (not illustrated) is formed on the entire surface of the semiconductor substrate  100  having the exposed heating electrodes  140 , and an etching process and an etch back process are performed to form the spacer  145 . In this exemplary embodiment, the spacer  145  is used for minimizing the size of the heating electrode contact holes  121  and  122 , and may be formed of nitride or oxide. 
         [0036]    Referring to  FIG. 7 , a phase change material layer  150  is buried in the heating electrode contact holes  121  and  122  partially filled by the heating electrode  140  and the spacer  145 . The contact area between the phase change material layer  150  and the heating electrode  140  may be reduced by the spacer  145 . 
         [0037]    More specifically, a CVD method or an atomic layer deposition (ALD) method is used to grow a phase change material layer (not illustrated) on the entire surface of the resultant substrate structure having the spacer  145  formed therein, and a chemical mechanical polishing process or/and a blanket etching process is performed to form the phase change material layer  150  to have a desired thickness. 
         [0038]    Referring to  FIG. 8 , a conductive layer (not illustrated) is deposited on the resultant substrate structure having the phase change material layer  150  formed therein, and patterned in a direction crossing the junction word line  110  to from an upper electrode  160 . 
         [0039]    At this time, the upper electrode  160  may be formed of Ti or TiN so as to be electrically coupled to the phase change material layer  150 . 
         [0040]    While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.