Abstract:
A control device for a switching converter having a transformer, with a primary winding receiving an input quantity, a secondary winding providing an output quantity, an auxiliary winding providing a feedback quantity, and a switch element. The control device has a processing module for generating a control signal for switching the switch element on the basis of the feedback quantity in order to regulate the output quantity via alternation of phases of storage and transfer of energy. The processing module controls the end of the transfer phase by comparing the feedback quantity with a comparison threshold. A discrimination circuit generates a signal for discrimination between the presence of a short circuit on the output or the fact that the input quantity is lower than a threshold. The processing module controls the end of the energy-transfer phase also on the basis of the discrimination signal.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to control devices for quasi-resonant switching converters; and further to corresponding control methods. 
         [0003]    2. Description of the Related Art 
         [0004]    Power switching converters (also called “switching regulators”) are known, which are designed to convert a quantity received at input, for example an AC voltage coming from the electrical network, into a regulated output quantity, for example a DC voltage. 
         [0005]    Such converters are generally required to meet stringent requirements as regards the corresponding electrical performance, for example, to guarantee a high quality factor, or a substantially unitary power factor. 
         [0006]    A control mode that has proven effective is the quasi-resonant mode;  FIG. 1  illustrates by way of example the configuration of a flyback converter. It is emphasized, however, that what follows also applies to different types of converters, for example those of a buck-boost type. 
         [0007]    The converter, designated as a whole by  1 , comprises a transformer  2 , having a primary winding  2   a , a secondary winding  2   b , and an auxiliary winding  2   c.    
         [0008]    The primary winding  2   a  has a first terminal  2   a ′ connected to a supply line  3 , for example to the electrical mains supplying an AC line voltage V AC , through a rectifier stage  4  that provides an input voltage V in , and a second terminal  2   a ″ connected to a switch element  5 , for example a MOSFET. 
         [0009]    The switch element  5  has a first current-conduction terminal, in particular the drain terminal of the respective MOSFET, connected to the aforesaid second terminal  2   a ″ of the primary winding  2   a , and a second current-conduction terminal, in particular the source terminal of the respective MOSFET, connected to a first reference terminal (ground, GND), through a detection resistor  6 . 
         [0010]    The switch element  5  and the detection resistor  6  define between them a first feedback node FB 1 , providing a first feedback voltage V CS , which is a function of the current flowing through the primary winding of the transformer  2 . 
         [0011]    The secondary winding  2   b  has a respective first terminal  2   b ′ connected to a first output terminal Out 1 , via a diode element  7  (having its anode connected to the same first terminal  2   b ′ and its cathode connected to the first output terminal Out 1 ), and a respective second terminal  2   b ″ connected to a second output terminal Out 2 . A charge-storage element  8  is connected between the first and second output terminals Out 1 , Out 2 , in particular a capacitor, on which an output voltage V out  is present, for example a DC voltage. 
         [0012]    The auxiliary winding  2   c  has a respective first terminal  2   c ′ and a respective second terminal  2   c ″ connected to a resistive divider formed by a first division resistor  9   a  and by a second division resistor  9   b , defining between them a second feedback node FB 2 , on which a second feedback voltage V ZCD  is present. 
         [0013]    The converter  1  further comprises a control device  10  (also defined as “controller”), which, on the basis of the first and second feedback voltages V CS , V ZCD , received on respective input pins, controls in pulse-width modulation (PWM) opening and closing of the switch element  5 , via a control signal S c  provided to the gate terminal of the corresponding MOSFET. 
         [0014]    In detail, the control device  10  implements management of the switch element  5  in a quasi-resonant mode with peak-current control, which envisages two distinct phases that follow one another cyclically: 
         [0015]    1) an energy-storage phase, during which the switch element  5  is closed (the corresponding MOSFET is on, ‘ON’ interval of the duty cycle) so as to store energy in the primary winding  2   a  of the transformer  2 , with the diode element  7  preventing the current in the secondary winding  2   b  from reaching an output load (here not represented). This step terminates (triggering the subsequent energy-transfer step) when the first feedback voltage V CS  reaches a threshold defined by a closed control loop (based upon a peak-current control); and 
         [0016]    2) an energy-transfer phase, during which the switch element  5  is open (the corresponding MOSFET is off, ‘OFF’ interval of the duty cycle), so as to transfer the energy previously stored in the primary winding  2   a  of the transformer  2  to the secondary winding  2   b  and the load connected at the output. Completion of energy transfer is signaled by onset of a condition of resonance on the primary of the transformer  2 , on account of the capacitance present on the drain terminal of the MOSFET of the switch element  5 . This phase terminates (once again triggering the energy-storage phase) when the second feedback voltage V ZCD  drops below a lower threshold close to zero. This control is defined as “zero-current detection” (ZCD) control. 
         [0017]    In greater detail, and as illustrated in  FIG. 2 , closing of the switch element  5  (determined by the control signal S c , which is also represented in  FIG. 2 ) is based upon a peak-current control mode. The current that circulates in the primary of the transformer  2  (designated by I P  in  FIG. 2 ) is compared with a sinusoidal reference current, in phase with the line voltage V AC , generated by the closed control loop for determining the instant of opening of the switch element  5  (and of turning-off of the corresponding MOSFET). 
         [0018]    The envelope of the peaks I PK  of the primary current I P  has a sinusoidal waveform, whereas the current effectively absorbed by the line, designated by I L , represents the mean value of the same primary current I P . This current I L  is practically sinusoidal and in phase with the line voltage V AC , thus enabling a desired correction of the power factor. 
         [0019]    In order to implement the quasi-resonant control mode, the switch element  5  is closed (and the corresponding MOSFET is turned on) at a minimum of the resonant oscillation present on the drain voltage of the corresponding MOSFET, when the transformer  2  completes energy transfer to the secondary winding (reaching a demagnetization condition). It has indeed been shown that the switching losses are markedly reduced if turning-on of the MOSFET occurs when the drain voltage is minimum or close to zero. 
         [0020]      FIG. 3  shows the drain voltage, the gate voltage, coinciding with the control signal S c , and also the second feedback voltage V ZCD . In order to highlight the oscillation, the figure shows the waveforms that these voltages would assume, in the case where the switch element  5  were not closed again in order to implement the quasi-resonant operation described previously. 
         [0021]    As highlighted in  FIG. 3 , the drain voltage, upon turning-off of the MOSFET (upon opening of the switch element  5 ), increases from a substantially zero value up to a value substantially equal to the sum of the input voltage V in  and a voltage V R , which corresponds to the output voltage V out  fed back onto the primary (i.e., multiplied by the ratio of the turns between the primary and secondary windings  2   a ,  2   b  of the transformer  2 ), which it reaches after a settling interval during which oscillations due to the leakage inductances of the transformer  2  occur. 
         [0022]    Next, when the energy transfer is completed, the drain voltage starts to oscillate in a resonance condition, with an amplitude of the oscillation equal to V in +V R , with a mean value equal to V in . 
         [0023]    To establish the instant of turning-on of the MOSFET, the control device  10  uses the second feedback voltage V ZCD , which is a function of the auxiliary voltage V aux . When the current on the secondary of the transformer  2  goes to zero, the voltage on the diode element  7  is zero, so that the voltage on the secondary winding  2   b  (and consequently an auxiliary voltage V aux  across auxiliary winding  2   c ) is proportional to the output voltage V out . 
         [0024]    The control device  10  is thus configured for detection of the “valleys” of the second feedback voltage V ZCD , when, that is, the second feedback voltage V ZCD  drops below a lower threshold, or reaches a substantially zero value. 
         [0025]    In detail, with reference to  FIG. 4 , the control device  10  is configured to analyze the plot of the second feedback voltage V ZCD , obtained starting from the aforesaid auxiliary voltage V aux  by the resistive divider formed by the division resistors  9   a ,  9   b.    
         [0026]    The control device  10  compares, in a comparator, the value of the second feedback voltage V ZCD  with a first threshold Th 1 , referred to as an “arming threshold”. When the second feedback voltage V ZCD  exceeds the first threshold Th 1 , an arming signal ARM is switched, for example to the high logic value, and the comparator is enabled for a subsequent comparison between the same second feedback voltage V ZCD  and a second threshold Th 2 , referred to as “trigger threshold”, of a value lower than the first threshold Th 1  and close to zero. 
         [0027]    When the second feedback voltage V ZCD  drops below the aforesaid second threshold Th 2 , a trigger signal TRIG is switched, for example to the high logic value, and the control device  10  detects a condition indicating occurrence of a valley of the auxiliary voltage V aux , and thus indicating that demagnetization has occurred, thus determining closing of the switch element  5 . 
         [0028]    Crossings of the second threshold Th 2  that occur during a blanking interval, designated by T blank , of a preset minimum value starting from opening of the switch element  5 , are not considered, in order to prevent spurious oscillations on the auxiliary voltage V aux  from possibly causing false detections. 
         [0029]    In  FIG. 4 , detection of the valley, which causes closing again of the switch element  5  (and the end of the OFF′ interval of the PWM control signal S e ), occurs after a detection time interval, designated by T ZCD , starting from the previous opening of the switch element  5 . 
         [0030]    Even though the converter  1  has generally good electrical performance, the performance is not optimized, at least as regards certain operating conditions. 
       BRIEF SUMMARY 
       [0031]    Embodiments of the present disclosure improve quasi-resonant switching converter operation in order to improve the corresponding electrical performance. 
         [0032]    Embodiments of the present disclosure are directed to a device for controlling a converter, a corresponding converter, and a corresponding control method. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0033]    For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, in which: 
           [0034]      FIG. 1  shows a simplified circuit diagram of a quasi-resonant switching converter; 
           [0035]      FIGS. 2-4  show plots of electrical quantities associated to the converter of  FIG. 1 ; 
           [0036]      FIGS. 5A-5C  show further plots of electrical quantities associated to the converter of  FIG. 1 ; 
           [0037]      FIG. 6  shows a simplified block diagram of a control device of the converter of  FIG. 1 , according to an aspect of the present disclosure; 
           [0038]      FIG. 7  shows a discrimination circuit in the control device of  FIG. 6 , according to one embodiment of the present disclosure; 
           [0039]      FIG. 8  is a state diagram regarding control operations performed by the control device of  FIG. 6 ; 
           [0040]      FIG. 9  shows a discrimination circuit in the control device of  FIG. 6 , according to a further embodiment of the present disclosure; 
           [0041]      FIGS. 10A and 10B  are plots of electrical quantities associated to the discrimination circuits of  FIG. 7  and, respectively, of  FIG. 9 ; 
           [0042]      FIGS. 11A-11C  are plots of electrical quantities regarding control operations carried out by the control device of  FIG. 6 ; 
           [0043]      FIG. 12  is a state diagram regarding further control operations carried out by the control device of  FIG. 6 ; and 
           [0044]      FIGS. 13A-13C  show plots of electrical quantities associated to the converter according to the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0045]    As mentioned previously, the known solutions of quasi-resonant power switching converters (for example, the converter  1  of  FIG. 1 , to which reference will once again be made in what follows, purely by way of non-limiting example) have some drawbacks, in certain operating conditions, during which the quasi-resonant control described previously does not enable the desired performance and/or may cause errors or malfunctioning. 
         [0046]    In the first place, it is possible to show that the aforementioned detection interval T ZCD  depends on the peak value of the current I S  that flows in the secondary winding  2   b  of the transformer  2  (having inductance L sec ) and upon the output voltage V out , according to the following expression: 
         [0000]    
       
         
           
             
               T 
               ZCD 
             
             = 
             
               
                 
                   L 
                   
                     se 
                      
                     
                         
                     
                      
                     c 
                   
                 
                 · 
                 
                   I 
                   s 
                 
               
               
                 V 
                 out 
               
             
           
         
       
     
         [0047]    The maximum value of the current I S  is proportional to the power transferred from the primary winding  2   a  to the secondary winding  2   b  of the transformer  2 , whereas the envelope of the peaks of the same current I S  is sinusoidal, like the primary current I P . 
         [0048]    Consequently, the duration of the detection interval T ZCD  varies as the input voltage V in  varies, having a maximum value at the peaks of the input voltage V in  and a minimum value, ideally zero, at the zero-crossing of the line voltage V AC  (or, likewise, upon the input voltage V in  reaching a substantially zero value). 
         [0049]    In this operating condition, as will be clear from what has been discussed previously with reference to  FIG. 4 , the short duration of the detection interval T ZCD  may be masked by the blanking interval T blank , so that no trigger is generated for closing the switch element  5 . 
         [0050]    To overcome the above drawback, some known solutions envisage generation of an artificial trigger event, after a preset time interval, having a rather long duration, comprised, for example, between 500 microseconds (μs) and 2 milliseconds (ms). The aforesaid solution entails a considerable distortion of the input current and a considerable deterioration of the value of the parameters of total harmonic distortion (THD) and of power factor (PF) of the converter. 
         [0051]    In this regard,  FIGS. 5A-5C  show the plots, respectively, of the input voltage V in , of the control signal S c , and of the second feedback voltage V ZCD , at a zero-crossing of the line voltage V AC , clearly highlighting the distortion of the waveforms that occurs in known control solutions. 
         [0052]    In general, at the zero-crossings of the line voltage V AC  (which, in the case of an AC voltage at the frequency of 50 Hz occur every 10 ms), the comparator arming and triggering mechanism implemented by the control device of the converter does not enable correct detection of the valleys or switching of the switch element. Consequently, a time interval exists, in which no switching activity is carried out, power is not transferred at the output, and no current is absorbed from the supply line, with consequent generation of distortions, reduction of the PF, and increase of the THD factor. 
         [0053]    In the case where a short circuit occurs at the output of the converter (for example, in the case where the load of the circuit is damaged, thus setting the output terminals Out 1 , Out 2  in direct connection), the amplitude of the second feedback voltage V ZCD  is too low to arm and trigger the comparator (given that it is lower than the first threshold Th 1  and/or the second threshold Th 2 ), thus generating an effect substantially similar to the one associated with the zero-crossings of the line voltage V AC . 
         [0054]    In the same operating condition, the high-frequency parasitic oscillations caused by the leakage inductance of the transformer  2  have a long duration, which may be longer than the blanking interval T blank . These oscillations may thus arm and trigger the comparator, erroneously. Consequently, the switch element  5  may initiate a very high frequency switching, causing an intense, continuous, magnetization flux in the transformer  2 , which may even cause saturation. 
         [0055]    In the same operating condition, the diode element  7  may undergo damage, even to the point of failure. 
         [0056]    Further operating conditions exist, for example low-load conditions, in which the duration of the blanking interval T blank  is appropriately selected with the aim of increasing the voltage-regulation efficiency. This duration may, consequently, even be longer than the detection interval T ZCD , once again causing a missed triggering of the comparator. 
         [0057]    Also in this condition, known solutions envisage generation of an artificial trigger signal, at a very low repetition frequency, but this causes a reduction of the energy supplied at the output and an intense ripple on the voltage, or current, supplied. 
         [0058]    In order to solve the problems highlighted above, one aspect of the present disclosure envisages (see  FIG. 6 ) that the control device, designated once again by  10 , of the converter (for example, the converter  1  described with reference to  FIG. 1 , to which reference is here made, and which is not described again for reasons of brevity), comprises a discrimination circuit  20  and a processing module  21 , for example including a microprocessor, a microcontroller, an FPGA, or a similar digital computing module, operatively coupled to the same discrimination circuit  20 . 
         [0059]    In a known manner, processing module  21  is further provided with an appropriate nonvolatile memory (not shown in  FIG. 6 ), for example of a RAM type, in which information and control programs may be stored (for implementation of appropriate control strategies, as discussed in detail in what follows), for example in the form of a firmware. 
         [0060]    In detail, the processing module  21  receives at its input the first and second feedback signals V CS , V ZCD  (see the foregoing discussion), on the basis of which it implements a control logic for generation of the control signal S c  for controlling switching of the switch element  5  (here not illustrated). 
         [0061]    Furthermore, the processing module  21  receives a discrimination signal S d  from the discrimination circuit  20  and is configured to generate the control signal S c  also on the basis of the discrimination signal S d . 
         [0062]    The discrimination circuit  20  (see also  FIG. 7 ) has a first input that receives a division voltage V p , deriving from a division of the input voltage V in , by a resistive divider defined by a first division resistor  23   a  and a second division resistor  23   b . In particular, a first input of the discrimination circuit  20  is connected to a division node N p , arranged between the first and second division resistors  23   a ,  23   b . The division voltage V p  is thus proportional to the input voltage V in , and, consequently, to the line voltage V AC . 
         [0063]    The discrimination circuit  20  further has a second input receiving a threshold voltage V gdon , of a preset value close to zero, for example 300 mV, and comprises a multiplier block  25 , and a comparator block  26 . The value of the threshold voltage V gdon  is, in any case, ideally close to zero, compatibly with the precision of the comparator block  26 . 
         [0064]    The multiplier block  25  receives at its input the division voltage V p , the peak value V FF  of the same division voltage V p  (generated in a per-se known manner, here not illustrated), and also a feedback signal V FB , which is an analog voltage proportional to the power transferred from the primary winding  2   a  to the secondary winding  2   b  of the transformer  2 , i.e., from the supply line  3  to the load. 
         [0065]    In one embodiment, the value of the feedback signal V FB  is defined on a so-called “feedback pin” of the control device  10  and is comprised between a minimum level (V FB   _   min , for example, but not necessarily, zero) and a maximum level (V FB   _   max ), which correspond to the case where the power transferred is maximum or minimum (possibly zero). 
         [0066]    The multiplier block  25  supplies at the output a discrimination voltage V d , on the basis of the following expression: 
         [0000]    
       
         
           
             
               V 
               d 
             
             = 
             
               
                 k 
                 · 
                 
                   ( 
                   
                     
                       V 
                       FB 
                     
                     - 
                     
                       V 
                       
                         FB 
                          
                         
                             
                         
                          
                         _ 
                          
                         
                             
                         
                          
                         m 
                          
                         
                             
                         
                          
                         i 
                          
                         
                             
                         
                          
                         n 
                       
                     
                   
                   ) 
                 
                 · 
                 
                   V 
                   p 
                 
               
               
                 V 
                 FF 
               
             
           
         
       
     
         [0000]    where k is a corrective factor strictly less than 1, for example 0.4. 
         [0067]    Consequently, the discrimination voltage V d  is derived as a function of the value of the line voltage V AC  (via the division voltage V p ) and of the factor of power transfer between the primary winding  2   a  and the secondary winding  2   b  of the transformer  2  (via the feedback signal V FB , possibly modified by the factor V FB   _   min ). 
         [0068]    The comparator block  26  has a first input terminal that receives the aforesaid discrimination voltage V d  and a second input terminal that receives the threshold voltage V gdon . 
         [0069]    The comparator block  26  supplies at output the discrimination signal S d , as a result of the comparison between the discrimination voltage V d  and the threshold voltage V gdon . 
         [0070]    According to one aspect of the present disclosure, in the case where the arming and triggering mechanism provided by the quasi-resonant control technique fails, the value of the discrimination signal S d  enables the processing module  21  to discriminate the situation where a short circuit is present at the output, from the situation where a zero-crossing by the line voltage V AC  occurs, or in general a condition where the input voltage V in  reaches a zero value (or is lower than a magnetization threshold close to zero, depending upon the circuit parameters and upon the arming and triggering thresholds), thus having a value such as not to generate an appreciable magnetization of the primary winding  2   a  of the transformer  2 . 
         [0071]    In particular, the aforesaid condition arises if, at the end of a blanking interval T blank  subsequent to opening of the switch element  5 , the second feedback signal V ZCD  has not armed the comparator (i.e., the value of the same second feedback signal V ZCD  is lower than the first threshold Th 1 ). Thus, the arming signal ARM has, for example, a low logic value ‘0’. 
         [0072]    In this condition, if the discrimination signal S d  assumes a first value (for example, low, or logic ‘0’), the processing module  21  obtains an indication of the fact that the input voltage V in  has a low value and that the line voltage V AC  is close to a zero-crossing. 
         [0073]    In this case, the processing module  21  immediately controls switching of the switch element  5  for minimizing distortion and maintaining a high power factor (PF) and a low total harmonic distortion (THD). 
         [0074]    Instead, in the case where the discrimination signal S d  assumes a second value (for example high, or logic ‘1’), the processing module  21  determines that a short circuit is present at the output. In this case, the processing module  21  waits for a given wait time before controlling switching of the switch element  5 . The delay, conveniently of a long duration, thereby enables reduction of the stress on the components of the device until the short circuit condition is removed. 
         [0075]    Basically, the processing module  21  is configured to modify the wait time before turning-on of the switch element  5  (in other words, the end of the step of energy transfer from the primary to the secondary of the transformer  2 ) based on the determination of the occurrence of a zero-crossing by the line voltage V AC  (wait time of a few μs) or of a short circuit at the output (much longer wait time, even of some hundreds of μs). 
         [0076]    A description is now made of the flow of a finite-state machine (FSM) that may be implemented by the processing module  21 , for implementing the control method, according to one aspect of the present disclosure. 
         [0077]    With reference to the diagram of  FIG. 8 , in a first state, designated by  30 , counting is started of a minimum blanking interval T min , of a preset value, for example 3 μs, starting from the instant of opening of the switch element  5  (indicated by switching of the control signal S c ). 
         [0078]    If, at the end of the minimum blanking interval T min  (condition EOC_T min =1), the comparator is armed (the arming signal ARM thus has a high logic value ‘1’, indicating the fact that the second feedback voltage V ZCD  has exceeded the first threshold Th 1 ), the processing module  21  determines that magnetization in the transformer  2  has occurred correctly, so that it continues the quasi-resonant control operations (in a way not illustrated herein in detail and indicated by the dashed arrow; one embodiment of the corresponding control operations will be described hereinafter). 
         [0079]    Instead, if at the end of the minimum blanking interval T min , the comparator is not armed (the arming signal ARM thus has a low logic value ‘0’), the processing module  21  passes to state  31 , in which counting of a variable blanking interval T blank  is started, the value of which may advantageously be set and adjusted (in order to optimize the regulation operations), for example by a setting signal received by the control device  10 . 
         [0080]    Next, if at the end of the variable blanking interval T blank  (condition EOC_T blank =1) the comparator is armed (the arming signal ARM has in the example a high logic value ‘1’), the processing module  21  passes from state  31  to state  32 , for implementation of the quasi-resonant control. 
         [0081]    Consequently, the processing module  21  waits for triggering of the comparator, for example for the trigger signal TRIG to switch to the high logic value due to the fact that the second feedback voltage V ZCD  drops below the second threshold Th 2 , a condition indicating detection of a valley of the same second feedback signal V ZCD  (as discussed in detail previously). 
         [0082]    Next, the algorithm passes to state  33 , in which the switch element  5  is closed (i.e., the corresponding MOSFET is on, ON-state of the duty cycle). At subsequent switching of the control signal S c , from state  33  the processing module  21  returns to the initial state  30 . 
         [0083]    If, instead, at the end of the blanking interval T blank , the comparator is not armed (the arming signal ARM has a low logic value ‘0’), two situations may arise, which correspond to determination of a zero-crossing of the line voltage V AC  and to the presence of a short circuit at the output. 
         [0084]    In particular, in the case where the arming signal ARM has a low logic value and further the discrimination signal S d  has a low logic value, the processing module  21  determines the presence of a zero-crossing of the line voltage V AC  and consequently immediately controls switching of the switch element  5 : from state  31 , the processing module  21  passes directly to state  33 . In other words, a low logic value of the discrimination signal S d  directly forces turning-on of the switch element  5 . 
         [0085]    Instead, in the case where the arming signal ARM has a low logic value and further the discrimination signal S d  has a high logic value, the processing module  21  determines the presence of a short circuit, and consequently this means that it is required to wait for a given wait time. From state  30  the processing module  21  then passes to state  34 . 
         [0086]    In state  34 , the processing module  21  waits for the end of a wait time T starter , of a duration much longer than that of the blanking interval T blank , that may be comprised between 400 μs and 2 ms, for example 500 μs, after which the algorithm passes once again to state  33 . 
         [0087]    With reference to  FIG. 9 , a different embodiment of the discrimination circuit, here designated by  20 ′, is now described. 
         [0088]    The discrimination circuit  20 ′ differs from the circuit  20  described with reference to  FIG. 7  in that it does not envisage use, as an input of the multiplier block  25 , of the peak value V FF  of the division voltage V p . 
         [0089]    In this case, the multiplier block  25  supplies at the output a discrimination voltage V d , on the basis of the following expression: 
         [0000]        V   d   =k ·( V   FB   −V   FB   _   min )· V   p  
 
         [0000]    where k is once again the corrective factor, strictly less than 1, for example 0.4. 
         [0090]    The discrimination voltage V d  is derived as a function of the value of the line voltage V AC  (via the division V p ) and of the power transfer factor between the primary winding  2   a  and the secondary winding  2   b  of the transformer  2  (via the feedback signal V FB ). 
         [0091]    An advantage afforded by this embodiment lies in the fact of eliminating the dependence upon the peak value V FF . 
         [0092]    In particular, in the circuit of  FIG. 7 , the comparator block  26  triggers when the input voltage V in  satisfies the following relation: 
         [0000]    
       
         
           
             
               V 
               
                 i 
                  
                 
                     
                 
                  
                 n 
               
             
             = 
             
               
                 
                   k 
                   p 
                 
                 · 
                 
                   V 
                   gdon 
                 
                 · 
                 
                   V 
                   FF 
                 
               
               
                 k 
                 · 
                 
                   ( 
                   
                     
                       V 
                       FB 
                     
                     - 
                     
                       V 
                       
                         FB 
                          
                         
                             
                         
                          
                         _ 
                          
                         
                             
                         
                          
                         m 
                          
                         
                             
                         
                          
                         i 
                          
                         
                             
                         
                          
                         n 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    where K p  is the division ratio defined by the first and second division resistors  23   a ,  23   b.    
         [0093]    In the embodiment of  FIG. 7 , the value of the input voltage V in  at which the discrimination signal S d  switches has a direct proportionality dependence upon the peak value V FF  of the division voltage V p . 
         [0094]    The above dependence is highlighted in  FIG. 10A , which shows the result of a simulation that envisages that the input voltage V in  is forced to zero when the discrimination signal S d  switches. As it has been pointed out, as the peak value of the input voltage V in , equal to 220 V, 150 V, or 80 V, varies, the value of the input voltage V in  at which the aforesaid switching of the discrimination signal S d  occurs, respectively equal to 155 V, 107 V, and 58 V, varies accordingly. 
         [0095]    The circuit of  FIG. 9  enables, instead, switching of the value of the discrimination signal S d  irrespective of the value of the input voltage V in , according to the expression: 
         [0000]    
       
         
           
             
               V 
               
                 i 
                  
                 
                     
                 
                  
                 n 
               
             
             = 
             
               
                 
                   
                     K 
                     p 
                   
                   · 
                   
                     V 
                     gdon 
                   
                 
                 
                   k 
                   · 
                   
                     ( 
                     
                       
                         V 
                         FB 
                       
                       - 
                       
                         V 
                         
                           FB 
                            
                           
                               
                           
                            
                           _ 
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         [0096]    As illustrated in  FIG. 10B  (which corresponds to  FIG. 10A ), the value of the input voltage V in  at which the discrimination signal S d  switches remains the same, in the example 50 V, as the input voltage V in  varies. 
         [0097]    In any case, the discrimination circuits  20 ,  20 ′ defines a threshold for switching of the discrimination signal S d  (and consequently for the duration of the energy-transfer step), which varies dynamically as a function of the power transfer factor between the primary winding  2   a  and the secondary winding  2   b  of the transformer  2  (via the feedback signal V FB ), and, in the case of the circuit of  FIG. 7 , also as a function of the value of the line voltage V AC  (via the division voltage V p ). 
         [0098]    A description of a further aspect of the present disclosure is now presented, which envisages, once correct magnetization has occurred of the secondary winding  2   b  of the transformer  2  at the end of the minimum blanking interval T min  (the arming signal ARM has a high logic value ‘1’), an appropriate management associated to the variable blanking interval T blank , so as to ensure that the switch element  5  is closed always at a valley of the second feedback voltage V ZCD , or, in any case, when the second feedback voltage V ZCD  has a value close to zero, for minimizing power losses. 
         [0099]    In particular, three different situations may arise, which will now be illustrated with reference to  FIGS. 11A-11C . All these situations arise in any case after, at the end of the minimum blanking interval T min , it has been determined that the arming signal ARM indicates that magnetization of the secondary winding  2   b  of the transformer  2  has occurred (i.e., it has, in the example, a high logic value ‘1’). 
         [0100]    In detail, with reference to  FIG. 11A  (which represents, by way of example, a possible plot of the second feedback voltage V ZCD ), a first situation envisages that, at the end of the variable blanking interval T blank , the arming signal ARM is still high. 
         [0101]    In this case, the control solution, implemented by the processing module  21 , envisages waiting for the next switching of the trigger signal TRIG, and then closing the switch element  5 , in this way ensuring its switching at a valley of the second feedback signal V ZCD . 
         [0102]    In a second situation (illustrated in  FIG. 11B ), at the end of the variable blanking interval T blank , the arming signal ARM has a low value. In this case, the solution envisages starting of the count of a further wait interval T wait , for example equal to 3 μs (or in general comprised between 1 μs and 10 μs). 
         [0103]    At the end of the aforesaid further wait interval T wait , or in the case of switching of the trigger signal TRIG within the same interval (without, that is, it being necessary to wait for the end thereof), the switch element  5  is closed. If, instead, it is the arming signal ARM that switches to the high value prior to completion of the wait time T wait , then sufficient energy is present in the system for supporting the oscillation, and consequently it is likely that a new switching of the trigger signal TRIG will be detected. 
         [0104]    The control solution implemented by the processing module  21  then envisages waiting for the subsequent switching of the trigger signal TRIG, and, in the case where this occurs, closing of the switch element  5 . 
         [0105]    A third situation envisages, instead, as illustrated in  FIG. 11C , that, at the end of the wait interval T wait , the arming signal ARM still has a low value. In this case, it is concluded that the residual energy present in the system is not sufficient, and consequently the switch element  5  is closed immediately, in so far as there is no reason to wait any longer. 
         [0106]      FIG. 12  sums up, in the form of a state diagram, the algorithm described previously, which is integrated with the one discussed with reference to  FIG. 8 . The flow starts in fact once again from the first state  30 , already described with reference to  FIG. 8 , in which counting of the minimum blanking interval T m  is started. 
         [0107]    If, at the end of the minimum blanking interval T min , the comparator is armed (the arming signal ARM has, in the example discussed, a high logic value ‘1’), the processing module  21  determines that magnetization in the transformer  2  has occurred correctly, and flow proceeds towards the state  40 , where counting of the variable blanking interval T blank  is started. 
         [0108]    If, at the end of the variable blanking interval Thank, the arming signal ARM has a high value (the first situation described previously), from state  40  flow proceeds to state  32 , already discussed previously with reference to  FIG. 8 , where the processing module  21  waits for the trigger signal TRIG to switch to the high logic value. After this, flow passes to state  33 , where the switch element  5  is closed (i.e., the corresponding MOSFET is ON). From state  33  flow returns to the initial state  30 . 
         [0109]    Instead, if at the end of the variable blanking interval T blank , the arming signal ARM has a low value, from state  40  flow proceeds to state  41 , where counting of the wait interval T wait  is started. 
         [0110]    Next, if at any instant within the wait interval T wait  the arming signal ARM has a high value, from state  41  flow passes once again to state  32  (described previously) waiting for the trigger signal TRIG. 
         [0111]    Otherwise, if at the end of the wait interval T wait  the arming signal ARM still has a low value, or else if, within the same wait interval T wait , switching of the trigger signal TRIG occurs, from state  41  flow passes directly to state  33 , for closing the switch element  5 . 
         [0112]    The advantages of the proposed solutions are clear from the foregoing description. 
         [0113]    In any case, the above solutions enable, among others, at least some of the following advantages to be obtained: 
         [0114]    a reduction of the THD factor and an increase of the power factor (PF), thanks to the improved management of the situations of zero-crossing of the line voltage V AC ; 
         [0115]    a greater robustness in regard to short circuits at output, which may be detected and appropriately discriminated from the aforesaid situations of zero-crossing of the line voltage V AC ; 
         [0116]    a greater efficiency and a greater accuracy of control, in particular in managing low-load conditions, thanks to the possibility of applying an appropriate variable blanking time and to the associated effective management of the control of switching at the valleys of the feedback signal (also in the case where the aforesaid variable blanking time is particularly long). 
         [0117]    In particular, tests and simulations have shown, in a typical operating configuration, a reduction of the THD factor by 6% and the possibility of the system to remain under control also in the case of transfer of a percentage lower than 5% of the nominal power. 
         [0118]    The advantages outlined above also emerge clearly from a comparison of the plots of  FIGS. 13A-13C  with the corresponding plots of  FIGS. 5A-5C , discussed previously. In particular, it is evident the marked reduction of the distortion of the waveforms that occurs at the zero-crossings of the line voltage V AC . 
         [0119]    Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure. 
         [0120]    In particular, it is clear that the circuit embodiment of the discrimination circuit  20  of the control device  10  could differ from what has been illustrated purely by way of example, as likewise could differ the expression for determination of the discrimination signal S d . 
         [0121]    It is further emphasized that, notwithstanding the fact that the foregoing description refers to a flyback converter, the present disclosure may advantageously be applied also to other types of converters, for example of the boost type, the buck-boost type, and corresponding variants thereof. 
         [0122]    Furthermore, it is evident that the converter could be supplied also by a supply source other than the electrical line, for example also by a DC voltage, without forgoing the advantages regarding efficiency, robustness, and accuracy of regulation. 
         [0123]    Finally, it is emphasized that the converter forming the subject of the present solutions may advantageously provide a voltage regulator or converter, to which the foregoing treatment has made explicit reference, by way of non-limiting example, or, likewise, a current regulator or converter (for instance, in LED drivers, or in battery chargers). 
         [0124]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
         [0125]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.