Abstract:
High-bandwidth, analog multiplexer circuits with low signal feed-through and good common mode properties are described. These are BiCMOS circuits with N-MOS control transistors which emphasize low parasitic capacitance through circuit layout techniques and the use of smaller geometry devices where possible. These circuits can be used in both single-ended and differential configurations and address applications having multiplexing ratio requirements ranging from 2-to-1 up to many-to-1.

Description:
This application claims priority under 35 USC §119(e)(1) of provisional application No. 60/165,345 filed Nov. 12, 1999. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to fast analog BiCMOS multiplexers (MUX) with CMOS control signals and particularly to the elimination of cross-signal feed-through in these high speed circuits. 
     2. Brief Description of the Known Art 
     FIG. 1 shows a fully differentially BiCMOS MUX which can be used to accommodate a wide varying common mode input signal for accomplishing fast analog multiplexing. In this circuit, two differential input signals INP 1 , INM 1  and INP 2 , INM 2  are converted to current by means of bipolar transistors  1 - 2  and resistors  5 - 6  or transistors  3 - 4  and resistors  7 - 8  depending on whether control signal SEL or SELB is selected and then this current is presented at resistors  9  or  10 , respectively. Current always flows in current sources  11 - 14  and is routed by means of NMOS signal control switches  15 - 18  or is dumped to the supply via NMOS switches  19 - 22 . The two output signals OUTP and OUTM are developed by coupling the signals from node N 1  (transistor  17 —resistor  9  connection) and node N 2  (transistor  18 —resistor  10  connection) to respective source followers comprised of bipolar transistors  23  and  24  and current sources  25  and  26 , respectively. This circuit has good common mode characteristics, but is limited in performance by internal parasitic capacitances. It should also be noted that this circuit could be implemented using only CMOS circuitry, although the circuit would be slower and have higher distortion. 
     Analog multiplexers, used to select one of several input signals, often have undesirable signal feed-through where an attenuated level of an unselected signal appears as part of the output signal. This is due primarily to the parasitic capacitances associated with the CMOS transistors used to implement the control switches. As a result, this undesirable feed-through causes a degradation at the output of both signal-to-noise and dynamic range for the selected signal. Also, due to the parasitic capacitances at the nodes of the control switches, these circuits are often limited to the number of input signals which can be multiplexed. 
     Thus, there is a need for an improved high-speed MUX which eliminates the cross-signal feed-through problems of the prior art. The invention and embodiments disclosed herein address this need. 
     For further reference, U.S. Pat. No. 5,744,995 discusses multi-input multiplexer and U.S. Pat. No. 5,598,114 discusses high-speed multiplexers. 
     SUMMARY OF THE INVENTION 
     This invention addresses the shortcomings of conventional analog multiplexers to provide low distortion, high speed solutions with a high input-to-output signal multiplexing ratio. Two embodiments address the signal feed-through issue using BiCMOS circuitry; one with emphasis on improving a more conventional multiplexer circuit and the other using a new diode controlled approach. The first embodiment of this invention addresses the problem of parasitic capacitance in the reference circuit discussed in the prior art and significantly improves this circuit&#39;s performance by means of the CMOS control transistor layout to provide a faster multiplexer, although one which limits the number of input signals which can be multiplexed. A second embodiment uses an entirely new approach to develop a high-speed BiCMOS multiplexer with a large multiplexing ratio and low signal feed-through. In general, these designs take into account such parameters as input signal level, signal bandwidth, common mode operation, parasitic capacitance, and transistor layout. Both of these techniques can be applied to both single-ended and/or differential configurations. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The included drawings are as follows: 
     FIG. 1 shows a schematic for a differential BiCMOS MUX which has high bandwidth, low signal feed-through, and good common mode signal characteristics. (prior art) 
     FIGS. 2 a  and  2   b  illustrate the layout of the CMOS control transistors of this invention with reduced parasitic output capacitance. 
     FIG. 3 shows a schematic for the new single-ended BiCMOS diode controlled MUX of this invention. 
     FIG. 4 shows a schematic for the new single-ended BiCMOS diode controlled MUX of this invention with signal level shifting for better common mode operation. 
     FIG. 5 shows a schematic for the new differential BiCMOS diode controlled MUX of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The differential BICMOS multiplexer circuit with CMOS control transistors, discussed in FIG. 1 of the prior art section above, has good common mode level characteristics, low signal feed-through, and a 2-to-1 MUX ratio. However, in a first embodiment of this invention, the speed of the multiplexer circuit is improved over conventional multiplexers, primarily through the layout of the N-MOS control switches  15 - 18 , as illustrated in FIGS. 2 a  and  2   b.  These switches are made smaller and the layouts use an even number of “fingers” to reduce the parasitic capacitances at nodes N 1  and N 2 . Although this will improve the speed of the multiplexer, it will limit the total number of input signals which can be multiplexed together, depending on the bandwidth requirements of the application. FIG. 2 a  shows a typical layout for a single finger N-MOS transistor which is comprised of a source  27 , a gate  28 , and a drain  29 . In this case the source and drain capacitances are equal and given as the area of the gate width (w) and drain/source length (x), as follows: 
     
       
         
           C 
           S 
           =C 
           D 
           =x·w. 
         
       
     
     On the other hand, for the lower capacitance layout of this invention, shown in FIG. 2 b,  the gate and source are split into two parts, or two “fingers”, so that the transistor is comprised of sources  30  and  31 , gates  32  and  33 , and drain  34 . In this case, the capacitance-to-area relationship becomes: 
     
       
           C   D   =x·w/ 2, 
       
     
     and 
     
       
           C   S =2 ·x·w/ 2 =x·w,   
       
     
     so that 
     
       
           C   S =2 ·C   D . 
       
     
     This means that a two “finger” device has a drain-to-bulk parasitic capacitance, C dB , that is one-half the source capacitance, C S , and as a result the total output capacitance is reduced by one-half. This layout can be used to obtain a significant boost of as much as 2× in the bandwidth of the MUX circuit, although the number of input signals which can be multiplexed is limited. There are many applications where a 2-to-1 or 3-to1 MUX is viable and this high speed circuit can be valuable. 
     FIG. 3 shows yet another new embodiment for a fast analog BiCMOS MUX with CMOS control which has low signal feed-through and can be used to multiplex a large number of input signals. In this circuit, each signal leg is comprised of input emitter followers made up of bipolar transistors  35 - 37  and current sources  38 - 40 , signal coupling diodes  41 - 43 , switchable current sources  44 - 46 , NMOS pull-down transistors  47 - 49 , output emitter follower transistors  50 - 52 , and an output current source  53 . 
     SW 1 , SW 2 , . . . SW n  are small n-channel pull-down switches  47 - 49  used to turn off diodes D 1    41 , D 2    42 , . . . D n    43 . If Sig  1  is selected, current I 1  flowing in switchable current source S 1    44  is turned on, while currents I 2 , . . . I n  flowing in the switchable current sources S 2    45  and S n    46  are turned off and pull-down switch SW 1    47  is inhibited while pull-down switches SW 2    48 , . . . SW n    49  are enabled. Diode D 1    41  is turned on acting as a level shifter and bipolar transistor BP 1y    50  along with the I o  current source  53  form an emitter follower at the circuit&#39;s output, while diodes D 2    42  and D n    43  and a bipolar transistors BP 2y    51  and BP ny    45  are off. 
     On the other hand, when Sig  1  is not selected, current source S 1    44  is turned off and SW 1    47  is enabled causing diode D 1    41  to turn off preventing any signal leakage to the output. In this state, since current source S 1    44  is turned off, SW 1    47  can be made small which reduces the parasitic capacitances at nodes N 1 , N 2 , . . . N n , hence improving the bandwidth of the circuit. This circuit has the advantage of being able to multiplex a large number of signals while maintaining low parasitic capacitance at the output and therefore excellent overall bandwidth. However, one drawback of the circuit is that the output signal&#39;s dc level will be one diode drop lower than that of the input signal since there are diode drops across the emitter-to-base of both transistors  35 - 37  and  50 - 52 , but only one diode rise across diodes  41 - 43 . One leg of the circuit is shown blocked  54  for further reference. 
     FIG. 4 shows another preferred adaptation of the MUX embodiment of FIG. 3 where each leg of the circuit  54  has a second diode  55  included to bring the dc level of the output signal back equal to that of the input signal. The addition of this second diode provides two diode rises to match the base-to-emitter diode drops across the two bipolar transistors. The advantage of such a scheme is that there is no loss in the common mode input vs. output signal. Depending on the application, this extra diode may or may not be required. 
     FIG. 5 shows a practical circuit embodiment of a fully differential 2-to-1 MUX for the approach given in FIG. 3 of this invention. Although shown for a 2-to-1 MUX, the circuit can be expanded to handle N-to-1 multiplexing applications, as well. This circuit is comprised of four of the basic BiCMOS MUX circuits  54  discussed in FIG.  3 . The two differential inputs are INP 1  &amp; INM 1  and INP 2  &amp; INM 2 . In this circuit, the two OUTP outputs are combined and coupled to a common output current source (I OP ) and likewise, the two OUTM outputs are combined and coupled to a common output current source (I ON ). The input control logic is comprised of two CMOS switches  56  and  57 , two diode connected transistors  59  and  60 , and a combined current source  58 . Externally generated control signals SEL and SELB are used to enable the desired differential input signal INP 1 /INM 1  or INP 2 /INM 2  and inhibit the other input signal. This differential MUX has very low signal feed-through, low parasitic capacitance, high bandwidth, and with an expanded control logic can multiplex a large number of input signals. 
     While the invention has been described in the context of several preferred embodiments, it will appear to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.