Abstract:
A substrate having thereon an epitaxial layer is provided. A hard mask having a first opening is formed on the epitaxial layer. A first trench is etched into the epitaxial layer through the first opening. The hard mask is trimmed to widen the first opening to a second opening. An upper corner portion of the first trench is revealed. A dopant layer is filled into the first trench. The dopants are driven into the epitaxial layer to form a doped region within the first trench. The doped region includes a first region adjacent to the surface of the first trench and a second region farther from the surface. The entire dopant layer is then etched and the epitaxial layer within the first region is also etched away to form a second trench.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to the field of semiconductor technology. More particularly, the present invention relates to a method for fabricating a power semiconductor device with super junction structure. 
         [0003]    2. Description of the Prior Art 
         [0004]    As known in the art, super junction power MOSFET devices include alternating p-type and n-type regions below the active regions of the device. The alternating p-type and n-type regions in a super junction power MOSFET device are ideally in charge balance so that those regions deplete one another under a reverse voltage condition, thereby enabling the device to better withstand breakdown. 
         [0005]    It is known to utilize super junction structures in trench type power devices. To form such trench type super junction power devices, typically, deep trenches are etched into a main surface of a semiconductor substrate, and an epitaxial layer is then formed to fill the deep trenches. However, the prior art fabrication method has drawbacks. For example, the surface concentration of the dopants driven into the trench surfaces is too high. This leads to non-uniformity of the carrier concentration distribution. 
       SUMMARY OF THE INVENTION 
       [0006]    It is therefore one object of the present invention to provide an improved fabrication method to form trench type power semiconductor devices in order to solve the above-mentioned overlay problems. 
         [0007]    According to one embodiment, a method for fabricating a power semiconductor device is provided. A semiconductor substrate is prepared. An epitaxial layer is then formed on the semiconductor substrate. A hard mask layer is then formed on the epitaxial layer. At least one first opening is formed in the hard mask layer. The epitaxial layer is then etched through the first opening to form at least one first trench. The hard mask layer is trimmed to enlarge the first opening to a second opening such that upper corners of the first trench are revealed. The first trench is then filled with a doped layer. A thermal drive-in process is performed to diffuse dopants from the doped layer into the epitaxial layer to thereby form a diffusion region in the first trench, wherein the diffusion region comprises a first region that is closer to surface of the first trench and a second region that is formed deeper into the epitaxial layer. Subsequently, a dry etching process is performed, using the trimmed hard mask layer as an etching hard mask, to completely etch away the doped layer and the epitaxial layer in the first region, thereby forming a second trench. 
         [0008]    According to another embodiment, a method for fabricating a power semiconductor device is provided. First, a semiconductor substrate is prepared. An epitaxial layer is formed on the semiconductor substrate. A hard mask layer is then formed on the epitaxial layer. At least one first opening is formed in the hard mask layer. A spacer is then formed on sidewall of the first opening. Through the first opening, the epitaxial layer is etched to thereby form at least one first trench. The spacer is removed to reveal upper corners of the first trench. The first trench is then filled with a doped layer. A thermal drive-in process is performed to diffuse dopants from the doped layer into the epitaxial layer to thereby form a diffusion region in the first trench, wherein the diffusion region comprises a first region that is closer to surface of the first trench and a second region that is formed deeper into the epitaxial layer. A dry etching process is performed, using the hard mask layer as an etching hard mask, to completely etch away the doped layer and the epitaxial layer in the first region, thereby forming a second trench. 
         [0009]    According to still another embodiment, a method for fabricating a power semiconductor device is provided. First, a semiconductor substrate is prepared. An epitaxial layer is formed on the semiconductor substrate. A hard mask layer is then formed on the epitaxial layer. A photoresist pattern is formed on the hard mask layer. The photoresist pattern has at least one first opening. The hard mask layer is etched through the first opening to form at least a second opening. The hard mask layer is trimmed to enlarge the second opening to a third opening. The epitaxial layer is then etched through the first opening to thereby form at least one first trench. The photoresist pattern is removed. The third opening and the first trench are filled with a doped layer. A thermal drive-in process is performed to diffuse dopants from the doped layer into the epitaxial layer to thereby form a diffusion region in the first trench, wherein the diffusion region comprises a first region that is closer to surface of the first trench and a second region that is formed deeper into the epitaxial layer. A dry etching process is performed, using the trimmed hard mask layer as an etching hard mask, to completely etch away the doped layer and the epitaxial layer in the first region, thereby forming a second trench. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIGS. 1-10  are schematic diagrams showing a method for fabricating a trench type power transistor device in accordance with one embodiment of the invention. 
           [0012]      FIGS. 11-16  are schematic diagrams showing a method for fabricating a trench type power transistor device in accordance with another embodiment of the invention. 
           [0013]      FIGS. 17-22  are schematic diagrams showing a method for fabricating a trench type power transistor device in accordance with still another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    In the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details. Furthermore, some well-known process steps such as lithographic and etching processes are not disclosed in detail, as these should be well-known to those skilled in the art. 
         [0015]    The terms wafer or substrate used herein includes any structure having an exposed surface onto which a layer may be deposited according to the present invention, for example, to form the integrated circuit (IC) structure. The term substrate is understood to include semiconductor wafers commonly used in this industry. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate may include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. 
         [0016]    Please refer to  FIGS. 1-10 .  FIGS. 1-10  are schematic diagrams showing a method for fabricating a trench type power transistor device in accordance with one embodiment of the invention. As shown in  FIG. 1 , a semiconductor substrate  10  having a fist conductivity type is provided. For example, the semiconductor substrate  10  may be an N+ heavily doped silicon substrate or wafer and may be act as a drain of the transistor device. An epitaxial growth process is performed to form an epitaxial layer  11  such as an N type epitaxial silicon layer or a P type epitaxial silicon layer on the semiconductor substrate  10 . 
         [0017]    As shown in  FIG. 2 , a hard mask layer  12  such as a silicon oxide layer or silicon nitride layer is formed on a top surface of the epitaxial layer  11 . A lithographic process and an etching process are carried out to form openings  112  in the hard mask layer  12 . For example, the openings  112  are straight line-shaped and each of the openings  112  has a width W1. 
         [0018]    As shown in  FIG. 3 , a dry etching process is performed to etch the epitaxial layer  11  through the openings  112  in the hard mask layer  12  to a depth H1, thereby forming trenches  122 . Each of the trenches  122  has a width that is equal to the width W1. The depth H1 is smaller than the thickness of the epitaxial layer  11 . 
         [0019]    As shown in  FIG. 4 , a hard mask trimming process is carried out. For example, a wet etching process may be used to remove a portion of the hard mask layer  12 . The removed portion has a thickness d such that the opening  112  having the width W1 is enlarged to an opening  112   a  having a width W2. The upper corners  122   a  around the upper ends of the trench  122  are exposed. According to the embodiment, the width d may be about 0.5 micrometers, but not limited thereto. 
         [0020]    As shown in  FIG. 5 , the trenches  122  are filled with a doped polysilicon layer  13 . According to the embodiment, the doped polysilicon layer  13  has a conductivity type that is opposite to the epitaxial layer  11 . For example, when the epitaxial layer  11  is N type, the doped polysilicon layer  13  is P type and when the epitaxial layer  11  is P type, the doped polysilicon layer  13  is N type. According to the embodiment, the epitaxial layer  11  is N type. According to the embodiment, the doped polysilicon layer  13  may cover the hard mask layer  12 . A high-temperature thermal drive-in process is then performed to diffuse dopants from the doped polysilicon layer  13  into the epitaxial layer  11 , thereby forming the PN super junction structure. 
         [0021]    At this point, the diffusion region  210  diffused into the epitaxial layer  11  includes a first region  211  that is closer to the surface of the trench  122  and a second region  212  that is formed deeper into the epitaxial layer  11 . The first region  211  has a doping concentration that is higher than that of the second region  212 . For example, the doping concentration of the first region  211  ranges between about 1E17 atoms/cm3 and 1E19 atoms/cm3, and the doping concentration of the second region  212  may be about 1E16 atoms/cm3, but not limited thereto. According to the embodiment, the width of the first region  211  is substantially equal to the width d of the removed portion of the hard mask layer  12 . 
         [0022]    As shown in  FIG. 6 , a dry etching process is then performed, using the hard mask layer  12  as an etching hard mask, to completely etch away the doped polysilicon layer  13  and the epitaxial layer  11  in the first region  211 , thereby forming trenches  222 . The trench  222  has a width that is substantially equal to the width W2 of the opening  112   a.  The trench  222  has a depth H2 that is greater than the depth H1 of the trench  122 . The depth H2 may be greater than or equal to the thickness of the epitaxial layer  11 . It is noteworthy that when the epitaxial layer  11  is N type, the aforesaid trenches  222  may have an etched depth either penetrating through the epitaxial layer  11  or not penetrating through the epitaxial layer  11 . However, when the epitaxial layer  11  is P type, the trenches  222  has an etched depth that has to be penetrating through the epitaxial layer  11 . 
         [0023]    As shown in  FIG. 7 , a silicon oxide layer  226  is then deposited. The silicon oxide layer  226  fills the trenches  222 . Prior to the deposition of the silicon oxide layer  226 , an oxidation process may be performed to form a sacrificial layer (not shown) on the surface of the trenches  222 . The sacrificial layer is then etched and removed. A chemical mechanical polishing (CMP) process is then performed to polish and remove the silicon oxide layer  226  from the surface of the hard mask layer  12 . A portion of the silicon oxide layer  226  is then removed from the trenches  222  such that a top surface of the silicon oxide layer  226  is lower than the top surface of the hard mask layer  12 . 
         [0024]    As shown in  FIG. 8 , the hard mask layer  12  is removed to reveal the top surface of the epitaxial layer  11 . Subsequently, a gate oxide layer  22  and gates  24  are formed on the top surface of the epitaxial layer  11 . According to the embodiment, the gates  24  may be polysilicon gates. An ion implantation process is then performed to implant dopants with the second conductivity type (e.g. P type) into the epitaxial layer  11  between two adjacent gates  24 , thereby forming ion wells  130 . Thereafter, a thermal drive-in process may be performed. 
         [0025]    As shown in  FIG. 9 , by using a photoresist and a lithographic process, the regions to be formed as sources are defined. Subsequently, an ion implantation process is carried out to implant dopants with the first conductivity type (e.g. N type) into the ion wells  130 , thereby forming the source doping regions  132 . Thereafter, a thermal drive-in process may be performed. 
         [0026]    As shown in  FIG. 10 , contact holes are formed and metalized. To form the metalized contact holes, an inter-layer dielectric (ILD) layer  30  is first deposited. Then, contact holes  230  are formed in the ILD layer  30 . The contact hole  230  reveals a portion of the ion well  130 , the source doping region  132  and the silicon oxide layer  226 . Barrier layer  32  and metal layer  34  are deposited to fill the contact holes  230 , thereby forming the contact elements  34   a  in contact with the ion well  130  and the source doping regions  132 . 
         [0027]      FIGS. 11-16  are schematic diagrams showing a method for fabricating a trench type power transistor device in accordance with another embodiment of the invention. As shown in  FIG. 11 , likewise, a semiconductor substrate  10  having a fist conductivity type is provided. For example, the semiconductor substrate  10  may be an N+ heavily doped silicon substrate or wafer and may be act as a drain of the transistor device. An epitaxial growth process is performed to form an epitaxial layer  11  such as an N type epitaxial silicon layer or a P type epitaxial silicon layer on the semiconductor substrate  10 . A hard mask layer  12  such as a silicon oxide layer or silicon nitride layer is formed on a top surface of the epitaxial layer  11 . A lithographic process is performed to form a photoresist pattern  310  on the hard mask layer  12 . The photoresist pattern  310  has openings  310   a.  Each of the openings  310   a  has a width W1. An etching process is then carried out to form openings  112  in the hard mask layer  12 . The openings  112  are straight line-shaped and each of the openings  112  has the width W1. 
         [0028]    As shown in  FIG. 12 , a hard mask trimming process is carried out. For example, a wet etching process may be used to laterally remove a portion of the hard mask layer  12 . The removed portion has a thickness d such that the opening  112  having the width W1 is now enlarged to an opening  112   a  having a width W2. The upper corners  122   a  around the upper ends of the trench  122  are exposed. According to the embodiment, the width d may be about 0.5 micrometers, but not limited thereto. 
         [0029]    As shown in  FIG. 13 , an anisotropic dry etching process is performed to etch the epitaxial layer  11  through the openings  310   a  in the photoresist pattern  310  to a depth H1, thereby forming trenches  122 . Each of the trenches  122  has a width that is equal to the width W1 of the opening  310   a.  The depth H1 is smaller than the thickness of the epitaxial layer  11 . 
         [0030]    As shown in  FIG. 14 , after forming the trenches  122 , the photoresist pattern  310  is completely removed to reveal the trimmed hard mask layer  12 . 
         [0031]    As shown in  FIG. 15 , the trenches  122  are filled with a doped polysilicon layer  13 . According to the embodiment, the doped polysilicon layer  13  has a conductivity type that is opposite to the epitaxial layer  11 . For example, when the epitaxial layer  11  is N type, the doped polysilicon layer  13  is P type and when the epitaxial layer  11  is P type, the doped polysilicon layer  13  is N type. According to the embodiment, the epitaxial layer  11  is N type. According to the embodiment, the doped polysilicon layer  13  may cover the hard mask layer  12 . A high-temperature thermal drive-in process is then performed to diffuse dopants from the doped polysilicon layer  13  into the epitaxial layer  11 , thereby forming the PN super junction structure. 
         [0032]    At this point, the diffusion region  210  diffused into the epitaxial layer  11  includes a first region  211  that is closer to the surface of the trench  122  and a second region  212  that is formed deeper into the epitaxial layer  11 . The first region  211  has a doping concentration that is higher than that of the second region  212 . For example, the doping concentration of the first region  211  ranges between about 1E17 atoms/cm3 and 1E19 atoms/cm3, and the doping concentration of the second region  212  may be about 1E16 atoms/cm3, but not limited thereto. According to the embodiment, the width of the first region  211  is substantially equal to the width d of the removed portion of the hard mask layer  12 . 
         [0033]    As shown in  FIG. 16 , a dry etching process is then performed, using the trimmed hard mask layer  12  as an etching hard mask, to completely etch away the doped polysilicon layer  13  and the epitaxial layer  11  in the first region  211 , thereby forming trenches  222 . The trench  222  has a width that is substantially equal to the width W2 of the opening  112   a.  The trench  222  has a depth H2 that is greater than the depth H1 of the trench  122 . The depth H2 may be greater than or equal to the thickness of the epitaxial layer  11 . It is noteworthy that when the epitaxial layer  11  is N type, the aforesaid trenches  222  may have an etched depth either penetrating through the epitaxial layer  11  or not penetrating through the epitaxial layer  11 . However, when the epitaxial layer  11  is P type, the trenches  222  has an etched depth that has to be penetrating through the epitaxial layer  11 . The subsequent steps are similar to the steps as described through  FIG. 7  to  FIG. 10 . 
         [0034]      FIGS. 17-22  are schematic diagrams showing a method for fabricating a trench type power transistor device in accordance with still another embodiment of the invention. As shown in  FIG. 17 , likewise, a semiconductor substrate  10  having a fist conductivity type is provided. For example, the semiconductor substrate  10  may be an N+ heavily doped silicon substrate or wafer and may be act as a drain of the transistor device. An epitaxial growth process is performed to form an epitaxial layer  11  such as an N type epitaxial silicon layer or a P type epitaxial silicon layer on the semiconductor substrate  10 . 
         [0035]    As shown in  FIG. 18 , a hard mask layer  12  such as a silicon oxide layer or silicon nitride layer is formed on a top surface of the epitaxial layer  11 . A lithographic process and an etching process are carried out to form openings  112   a  in the hard mask layer  12 . For example, the openings  112   a  are straight line-shaped and each of the openings  112   a  has a width W2. Subsequently, a sidewall spacer  420  is formed on each sidewall of the openings  112   a.  For example, the sidewall spacer  420  may be a silicon oxide or silicon nitride spacer, and has a width d (bottom width). The material of the spacer  420  is different from that of the hard mask layer  12 . According to the embodiment, the width d may be about 0.5 micrometers, but not limited thereto. 
         [0036]    As shown in  FIG. 19 , using the hard mask layer  12  and the sidewall spacer  420  together as an etching hard mask, a dry etching process is performed to etch the epitaxial layer  11  through the openings  112   a  in the hard mask layer  12  to a depth H1, thereby forming trenches  122 . Each of the trenches  122  has a width that is equal to the width W1. The depth H1 is smaller than the thickness of the epitaxial layer  11 . 
         [0037]    As shown in  FIG. 20 , the sidewall spacer  420  is removed to reveal upper corners  122   a  around the upper ends of the trench  122 . According to the embodiment, the width d may be about 0.5 micrometers, but not limited thereto. 
         [0038]    As shown in  FIG. 21 , the trenches  122  are filled with a doped polysilicon layer  13 . According to the embodiment, the doped polysilicon layer  13  has a conductivity type that is opposite to the epitaxial layer  11 . For example, when the epitaxial layer  11  is N type, the doped polysilicon layer  13  is P type and when the epitaxial layer  11  is P type, the doped polysilicon layer  13  is N type. According to the embodiment, the epitaxial layer  11  is N type. According to the embodiment, the doped polysilicon layer  13  may cover the hard mask layer  12 . A high-temperature thermal drive-in process is then performed to diffuse dopants from the doped polysilicon layer  13  into the epitaxial layer  11 , thereby forming the PN super junction structure. 
         [0039]    At this point, the diffusion region  210  diffused into the epitaxial layer  11  includes a first region  211  that is closer to the surface of the trench  122  and a second region  212  that is formed deeper into the epitaxial layer  11 . The first region  211  has a doping concentration that is higher than that of the second region  212 . For example, the doping concentration of the first region  211  ranges between about 1E17 atoms/cm3 and 1E19 atoms/cm3, and the doping concentration of the second region  212  may be about 1E16 atoms/cm3, but not limited thereto. According to the embodiment, the width of the first region  211  is substantially equal to the width d of the sidewall spacer  420 . 
         [0040]    As shown in  FIG. 22 , a dry etching process is then performed, using the hard mask layer  12  as an etching hard mask, to completely etch away the doped polysilicon layer  13  and the epitaxial layer  11  in the first region  211 , thereby forming trenches  222 . The trench  222  has a width that is substantially equal to the width W2 of the opening  112   a.  The trench  222  has a depth H2 that is greater than the depth Hl of the trench  122 . The depth H2 may be greater than or equal to the thickness of the epitaxial layer  11 . It is noteworthy that when the epitaxial layer  11  is N type, the aforesaid trenches  222  may have an etched depth either penetrating through the epitaxial layer  11  or not penetrating through the epitaxial layer  11 . However, when the epitaxial layer  11  is P type, the trenches  222  has an etched depth that has to be penetrating through the epitaxial layer  11 . 
         [0041]    It is one germane feature of the present invention that by using a second trench etching step, the doped polysilicon layer  13  and the high-concentration trench sidewall (first region  211  of the diffusion region  210 ) are both removed, such that the electrical performance and yield of the fabricated power semiconductor device with super junction structure are improved. 
         [0042]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.