Abstract:
An amplifier with Miller-effect frequency compensation in which the Miller feedback capacitor is connected to an internal terminal of the amplifier having a low impedance, and shunt compensation circuitry is connected to an intermediate signal terminal that drives the output amplifier stage. The compensation circuitry, which includes serially coupled capacitive and resistive circuit elements, introduces a high frequency zero to cancel one of the high frequency complex poles introduced by the Miller feedback capacitor connection.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to frequency compensated amplifiers, and in particular, to amplifier circuits with Miller-effect frequency compensation. 
     2. Description of the Related Art 
     Miller feedback is commonly used to compensate multistage amplifiers. By adding a feedback capacitance around an intermediate amplifier stage phase compensation is provided by introducing a pole-zero cancellation. As is well known, due to the Miller effect, a response zero is developed in the amplifier stage having the feedback capacitance such that the response zero is coincident with the pole of the succeeding amplifier stage. 
     A drawback of Miller feedback is a poor power supply rejection ratio (PSRR). At high frequency, standard Miller feedback causes the PSRR to begin to degrade at the dominant pole frequency. This can be improved, as shown by Ribner and Copeland in “Design Techniques for Cascoded CMOS Op Amps With Improved PSRR and Common Mode Input Range”, IEEE JSSCC December 1984 (Ribner et al., incorporated herein by reference), by feeding the Miller capacitance back to a low impedance node. This method provides a significant improvement to the PSRR. However, it also creates two complex poles at high frequency that often cause the amplifier to be unstable. 
     Referring to FIG. 1, a folded cascode amplifier has been proposed using a modified Miller feedback as described by Ribner et al. Capacitor C 2  is traditionally used to compensate the Miller loop. For the following discussion, it is assumed that capacitor C 2  is significantly larger than the gate-to-source capacitance C GS  of transistor M 4 . In cases where this is not true, a low input capacitance buffer (not shown), such as a source follower, can be connected between node N 1  and the gate terminal of transistor M 4  to reduce the capacitive loading on the high impedance node N 1  by transistor M 4 . (In the Figures and throughout the following discussion, transistors M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8  are insulated gate field effect transistors, such as P-type and N-type metal oxide semiconductor field effect transistors (P-MOSFETs and N-MOSFETs), and are depicted using conventional transistor symbols for P-MOSFETs and N-MOSFETs.) 
     Referring to FIGS. 2 and 3, there are two loops in the system that need to be analyzed. The first is the traditional DC loop as depicted in FIG.  2 . The loop characteristics of this DC system are well known in the art and, therefore, need not be analyzed here. The second is the Miller feedback loop as depicted in FIG.  3 . As is well known, when analyzing the Miller loop, the inputs to the DC loop are AC grounded. In this way, the characteristics of the Miller loop can be determined independently of the DC loop. Capacitor C 1  creates a zero at DC and a dominant pole due to the high impedance of node V 3  reflected through transistor M 1 . The Miller loop also has two low frequency poles at nodes V 3  and Vout due to capacitors C 2  and C 1 . It is these two poles that converge when the Miller loop is closed, thus giving rise to a pair of complex poles in the DC loop. Eliminating one of these poles would significantly improve the loops&#39; stability. 
     Referring to FIG. 4, the Miller loop can be simplified as shown. Referring to FIG. 5, this circuit can be modeled to a first order as shown. For simplicity, the capacitance of capacitor C 1  is set to A times the capacitance of capacitor C 2  (Equation 0). The loop transmission can be characterized by Equation 1. As expected, the cascode portion of the loop contributes a DC zero, and two poles, while the output stage contributes a single pole as expressed by Equation 2. 
     
       
           c   1   χAC   2   χAC   Equation 0: 
       
     
     
       
         
           
             
               Equation 
                
               
                   
               
                
               1 
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                 : 
               
                
               
                 
                   V 
                   o 
                 
                 
                   V 
                   i 
                 
               
             
             = 
             
               
                 [ 
                 
                   
                     ( 
                     
                       sAC 
                        
                       
                           
                       
                        
                       
                         ( 
                         
                           
                             gds 
                             1 
                           
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                           ) 
                         
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                 ] 
               
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                       - 
                       
                         gm 
                         4 
                       
                     
                     
                       
                         gds 
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                         s 
                          
                         
                             
                         
                          
                         
                           ( 
                           AC 
                           ) 
                         
                       
                     
                   
                   ] 
                 
               
             
           
         
                 
         
             
         
      
       
         
           
             
               Equation 
                
               
                   
               
                
               2 
                
               
                 : 
               
                
               
                   
               
                
               
                 ω 
                 p3 
               
             
             ≈ 
             
               
                 gds 
                 4 
               
               AC 
             
           
         
                 
         
             
         
       
     
     Finding the poles of the cascoded stage is somewhat more involved. Using the standard form for solving the roots of a second order equation produces Equations 3-9. Equation 10 is presented as a compact expression for the total Miller loop system response.          Equation                 3        :                   r     =         -   b     ±         b   2     -     4      ac             2      a                              b   2   χgds   1   AC+ 2 gds   1 ( gds   3   +gds   1   +gm   1   +gmb   1 ) AC   2 +( (gds   3   +gds   1   +gm   1   +gmb   1 ) 2   C   2   Equation 4: 
     
       
         4 acχ 4 AC   2 ( gds   2   gds   3   +gds   2   gds   1   +gds   2 ( gm   1   +gmb   1 )+ gds   3   gds   1 )  Equation 5: 
       
     
     
       
           b =( gds   1   AC+ ( gds   3   +gds   1   +gm   1   +gmb   1 ) C )  Equation 6: 
       
     
     
       
         2 a= 2 AC   2   Equation 7: 
       
     
     
       
         
           
             
               Equation 
                
               
                   
               
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               8 
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                 : 
               
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                 ω 
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                   ( 
                   
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               Equation 
                
               
                   
               
                
               9 
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                 : 
               
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                
               
                 ω 
                 p1 
               
             
             = 
             
               
                 
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                   ( 
                   
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               Equation 
                
               
                   
               
                
               10 
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                 : 
               
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                
               
                 
                   V 
                   o 
                 
                 
                   V 
                   i 
                 
               
             
             = 
             
               
                 [ 
                 
                   
                     ( 
                     
                       
                         gds 
                         1 
                       
                       + 
                       
                         gm 
                         1 
                       
                       + 
                       
                         gmb 
                         1 
                       
                     
                     ) 
                   
                    
                   
                       
                   
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                       ( 
                       
                         - 
                         
                           gm 
                           4 
                         
                       
                       ) 
                     
                     
                       gds 
                       4 
                     
                   
                 
                 ] 
               
                
               
                  
                 
                   
                     [ 
                     
                       sAC 
                       
                         
                           ( 
                           
                             1 
                             + 
                             
                               s 
                               
                                 ω 
                                 p1 
                               
                             
                           
                           ) 
                         
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                           ( 
                           
                             1 
                             + 
                             
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                           ) 
                         
                       
                     
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                    
                   
                     [ 
                     
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                         1 
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     The pole at frequency ω p1  can be shown to be much lower than the pole at frequency ω p2  and thus of little interest for purposes of this analysis since it is effectively canceled by the zero at DC. Using the assumption expressed by Equation 11 and for moderately low values of the factor A, the expression for the pole at frequency ω p2  can be simplified as shown in Equation 12. 
     
       
           gm≈ 10 gmbs≈ 100 gds   Equation 11: 
       
     
     
       
         
           
             
               Equation 
                
               
                   
               
                
               12 
                
               
                 : 
               
                
               
                   
               
                
               
                 ω 
                 p2 
               
             
             ≈ 
             
               b 
               a 
             
             ≈ 
             
               
                 ( 
                 
                   
                     
                       gds 
                       1 
                     
                      
                     
                         
                     
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                     AC 
                   
                   + 
                   
                     
                       ( 
                       
                         
                           gds 
                           3 
                         
                         + 
                         
                           gds 
                           1 
                         
                         + 
                         
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                           1 
                         
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                           gmb 
                           1 
                         
                       
                       ) 
                     
                      
                     
                         
                     
                      
                     C 
                   
                 
                 ) 
               
               
                 AC 
                 2 
               
             
             ≈ 
             
               
                 ( 
                 
                   
                     
                       gds 
                       1 
                     
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                   + 
                   
                     
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                           gm 
                           1 
                         
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                           gmb 
                           1 
                         
                       
                       ) 
                     
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                     C 
                   
                 
                 ) 
               
               
                 AC 
                 2 
               
             
             ≈ 
             
               
                 
                   gm 
                   1 
                 
                 + 
                 
                   gmb 
                   1 
                 
               
               AC 
             
             ≈ 
             
               
                 gm 
                 1 
               
               AC 
             
           
         
                 
         
             
         
      
     
     Referring to FIGS. 6-9, the open loop frequency responses for two nodes in the circuit of FIG. 5 are produced. FIG. 6 depicts the magnitude response as seen from node voltage Vi to node voltage V 3 , while FIG. 7 depicts the phase response. From this it can be seen that the pole at frequency ω p2  has already degraded the phase margin by 90 degrees. If the pole at the output is sufficiently low, the system will be unstable and exhibit peaking at the unity gain frequency. FIG. 8 depicts the open loop magnitude response from node voltage Vi to node voltage Vo. From this it can be seen that the output pole causes the high frequency rolloff to degrade with two poles before the unity gain frequency. FIG. 8 also depicts the closed loop magnitude response. FIG. 9 depicts the open and closed loop phase response from which it is evident that the phase margin is nearly zero. Therefore, the Miller loop is unstable and will cause severe peaking when inserted in the DC loop. 
     While the DC loop is not analyzed here in detail, a brief explanation of the effect of the Miller loop can be provided. Referring back to FIG. 1, it is clear that transistor M 1  provides a current into the impedance seen at node V 2 . FIG. 10 depicts the impedance at node V 2  when the Miller loop is closed and the DC loop is open. The resonant peak is due to the poorly compensated Miller loop. FIG. 11 depicts the open and closed loop magnitude response of the DC loop. The peaking here is at the same frequency as the peaking in the impedance at node V 2 , as well as the peaking in the frequency response of the Miller feedback loop. FIG. 12 depicts the open and closed loop phase response of the DC loop. Though not depicted in detail here, it should nonetheless be seen that the phase response of the closed loop system is nearly identical to the phase response of the closed loop Miller feedback system as depicted in FIG.  9 . 
     SUMMARY OF THE INVENTION 
     An amplifier with Miller-effect frequency compensation in accordance with the presently claimed invention includes a high frequency zero that cancels one of the high frequency complex poles thereby leaving one real pole. Cancellation of such pole significantly improves the bandwidth and stability of the Miller feedback system, and can be accomplished with consistency over PVT (variations in fabrication processes P, power supply voltage V and temperature T). In accordance with the presently claimed invention, the Miller feedback capacitor is connected to an internal terminal of the amplifier having a low impedance, and shunt compensation circuitry is connected to an intermediate signal terminal that drives the output amplifier stage. The compensation circuitry, which includes serially coupled capacitive and resistive circuit elements, introduces a high frequency zero to cancel one of the high frequency complex poles introduced by the Miller feedback capacitor connection. 
     In accordance with one embodiment of the presently claimed invention, an amplifier with Miller-effect frequency compensation includes first and second amplification circuitry, feedback capacitance and compensation circuitry. The first amplification circuitry, including an internal terminal and a first output terminal, receives and amplifies an input signal to provide a first amplified signal via the first output terminal. The internal terminal has an internal terminal impedance associated therewith, the first output terminal has an output terminal impedance associated therewith, and the internal terminal impedance is substantially lower than the output terminal impedance. The second amplification circuitry, coupled to the first output terminal and including a second output terminal, receives and further amplifies the first amplified signal to provide a second amplified signal via the second output terminal. The feedback capacitance is coupled between the second output terminal and the internal terminal. The compensation circuitry is coupled in shunt to the first output terminal and includes capacitive and resistive circuit elements mutually coupled in series. 
     In accordance with another embodiment of the presently claimed invention, an amplifier with Miller-effect frequency compensation includes first and second power supply terminals, first and second amplification circuitry, feedback capacitance and compensation circuitry. The first amplification circuitry, coupled between the first and second power supply terminals and including an internal terminal and a first output terminal, receives and amplifies an input signal to provide a first amplified signal via the first output terminal. The internal terminal has an internal terminal impedance associated therewith, the first output terminal has an output terminal impedance associated therewith, and the internal terminal impedance is substantially lower than the output terminal impedance. The second amplification circuitry, coupled between the first and second power supply terminals and to the first output terminal and including a second output terminal, receives and further amplifies the first amplified signal to provide a second amplified signal via the second output terminal. The feedback capacitance is coupled between the second output terminal and the internal terminal. The compensation circuitry is coupled between the first output terminal and the first power supply terminal and includes serially coupled capacitive and resistive circuit elements. 
     In accordance with still another embodiment of the presently claimed invention, an amplifier with Miller-effect frequency compensation includes first and second amplifier means, feedback means and shunting means. The first amplifier means is for receiving a feedback signal, receiving and amplifying an input signal and providing a first amplified signal. The second amplifier means is for receiving and further amplifying the first amplified signal and providing a second amplified signal, wherein the first and second amplifier means together have a transfer function associated therewith. The feedback means is for selectively feeding back the second amplified signal as the feedback signal to the first amplifier means, thereby introducing to the transfer function one or more high frequency complex poles. The shunting means is for selectively shunting the first amplified signal, thereby introducing to the transfer function at least one high frequency zero that substantially cancels one of the one or more high frequency complex poles. 
     In accordance with yet another embodiment of the presently claimed invention, an amplifier with Miller-effect frequency compensation includes first and second amplifier means, feedback means and shunting means. The first amplifier means is for receiving a feedback signal, receiving and amplifying an input signal and providing a first amplified signal. The second amplifier means is for receiving and further amplifying the first amplified signal and providing a second amplified signal. The feedback means is for selectively feeding back the second amplified signal as the feedback signal to the first amplifier means. The shunting means is for selectively shunting the first amplified signal. Together the first and second amplifier means, the feedback means and the shunting means have associated therewith a transfer function with one or more high frequency complex poles and a high frequency zero which is complementary to one of the one or more high frequency complex poles. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a multistage amplifier using modified Miller feedback. 
     FIG. 2 is a schematic diagram for the circuit of FIG. 1 for analyzing the DC loop characteristics. 
     FIG. 3 is a schematic diagram for the circuit of FIG. 1 for analyzing the Miller loop characteristics. 
     FIG. 4 is a schematic diagram in which the circuit of FIG. 3 has been simplified for a qualitative analysis of the Miller loop characteristics. 
     FIG. 5 is a schematic diagram of a circuit model for the circuit of FIG.  4 . 
     FIG. 6 is a graph of the open loop magnitude response for the circuit of FIG. 5 from input node voltage Vi to intermediate node voltage V 3 . 
     FIG. 7 is a graph of the open loop phase response for the circuit of FIG. 5 from input node voltage Vi to intermediate node voltage V 3 . 
     FIG. 8 is a graph of the open and closed loop magnitude responses for the circuit of FIG. 5 from input node voltage Vi to output node voltage Vo. 
     FIG. 9 is a graph of the open and closed loop phase responses for the circuit of FIG. 5 from input node voltage Vi to output node voltage Vo. 
     FIG. 10 is a graph of the impedance for the circuit of FIG. 5 at the node for voltage V 2  when the Miller loop is closed and the DC loop is open. 
     FIG. 11 is a graph of the open and closed loop magnitude responses of the DC loop for the circuit of FIG.  5 . 
     FIG. 12 is a graph of the open and closed loop phase responses of the DC loop for the circuit of FIG.  5 . 
     FIG. 13 is a schematic diagram of a folded cascode amplifier in accordance with one embodiment of the presently claimed invention. 
     FIG. 14 is a graph of the open loop magnitude response for the circuit of FIG. 13 from input node voltage Vi to intermediate node voltage V 3 . 
     FIG. 15 is a graph of the open loop phase response for the circuit of FIG. 13 from input node voltage Vi to intermediate node voltage V 3 . 
     FIG. 16 is a graph of the open and closed loop magnitude responses for the circuit of FIG. 13 from input node voltage Vi to output node voltage Vo. 
     FIG. 17 is a graph of the open and closed loop phase responses for the circuit of FIG. 13 from input node voltage Vi to output node voltage Vo. 
     FIG. 18 is a graph of the impedance for the circuit of FIG. 13 at the node for voltage V 2  when the Miller loop is closed and the DC loop is open. 
     FIG. 19 is a graph of the open and closed loop magnitude responses of the DC loop for the circuit of FIG.  13 . 
     FIG. 20 is a graph of the open and closed loop phase responses of the DC loop for the circuit of FIG.  13 . 
     FIG. 21 is a schematic diagram of an input folded cascode amplifier in accordance with another embodiment of the presently claimed invention. 
     FIG. 22 is a schematic diagram of another input folded cascode amplifier in accordance with still another embodiment of the presently claimed invention. 
     FIG. 23 is a schematic diagram of a telescopic amplifier in accordance with another embodiment of the present invention. 
     FIG. 24 is a schematic diagram of another telescopic amplifier in accordance with still another embodiment of the presently claimed invention. 
     FIG. 25 is a schematic diagram of a differential input folded cascode amplifier in accordance with another embodiment of the presently claimed invention. 
     FIG. 26 is a schematic diagram of another differential input folded cascode amplifier in accordance with still another embodiment of the presently claimed invention. 
     FIG. 27 is a schematic diagram of another telescopic amplifier in accordance with another embodiment of the presently claimed invention. 
     FIG. 28 is a schematic diagram of still another telescopic amplifier in accordance with still another embodiment of the presently claimed invention. 
     FIGS. 29A and 29B are schematic diagrams for current source and sink circuits for providing a reference current. 
     FIG. 30 is a schematic diagram of an input folded cascode amplifier using a resistor in accordance with another embodiment of the presently claimed invention. 
     FIG. 31 is a schematic diagram of another input folded cascode amplifier using a resistor in accordance with still another embodiment of the presently claimed invention. 
     FIG. 32 is a schematic diagram of a telescopic amplifier using a resistor in accordance another embodiment of the presently claimed invention. 
     FIG. 33 is a schematic diagram of another telescopic amplifier using a resistor in accordance with still another embodiment of the presently claimed invention. 
     FIG. 34 is a schematic diagram of a differential input folded cascode amplifier using an N-MOSFET in accordance with another embodiment of the presently claimed invention. 
     FIG. 35 is a schematic diagram of a differential input folded cascode amplifier using a P-MOSFET in accordance with still another embodiment of the presently claimed invention. 
     FIG. 36 is a schematic diagram of still another telescopic amplifier using a resistor in accordance with another embodiment of the presently claimed invention. 
     FIG. 37 is a schematic diagram of still another telescopic amplifier using a resistor in accordance with still another embodiment of the presently claimed invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. 
     Referring to FIG. 13, the phase response of the Miller loop can be significantly improved if the pole at frequency ω p2  is eliminated. As expressed in Equation 13, insertion of a resistor of value R z  in series with capacitor C 2  will produce a zero at the frequency ω z2  expressed in Equation 14, thus making this a single pole system as expressed in Equation 15.         Equation                 13        :                     R   z       ≈     A     gm   1                                      Equation                 14        :                     ω   z2       ≈       gm   1     AC                                     Equation                 15        :                       V   o       V   i         =           [       (       gds   1     +     gm   1       )                       (     -     gm   4       )       gds   4         ]          [         sAC                   (     1   +     s     ω   z1         )                        (     1   +     s     ω   p1         )                     (     1   +     s     ω   p2         )         ]            [     1     1   +     s     ω   p3           ]       =         [       (       gds   1     +     gm   1       )                       (     -     gm   4       )       gds   4         ]          [     sAC     (     1   +     s     ω   p1         )       ]            [     1     1   +     s     ω   p3           ]                                 
     The resistance R z  can be implemented in a number of ways. One implementation is shown in FIG. 13 that tracks the transconductance gm 1  of transistor M 1  over process temperature and voltage. A transistor M 8  that has a width-to-length W/L ratio of 1/A times that of transistor M 1 , i.e., W 8 /L 8 =(W 1 /L 1 )/A, is operated with a current I 8  of 1/A times the current I 1  in transistor M 1  so as to provide a diode connected device with an equivalent resistance R z  equal to A/gm 1  in series with capacitor C 2 . 
     FIG. 14 depicts the open loop magnitude response from node voltage Vi to node voltage V 3  with the additional zero ω z2  included. FIG. 15 depicts the phase response. It is clear that the insertion of this additional zero ω z2  has dramatically improved the frequency response. The remaining high frequency pole is associated with the gate-to-drain capacitance Cgd of transistors M 1  and M 2  which can be made quite small. FIGS. 16 and 17 depict the open and closed loop magnitude and phase responses, respectively. The loop now rolls off as a single pole system with a phase margin of 90 degrees. 
     FIGS. 18-20 depict impedance and magnitude and phase responses corresponding to those depicted in FIGS. 10-12 with the additional zero ω z2  in the system. It can be seen that the impedance at node V 2  is dramatically improved. The resonant peak has been eliminated. For the open and closed loop magnitude responses in FIG. 19, the resonant peak is also eliminated. FIG. 20 depicts the open and closed loop phase responses. The system now exhibits a single real non-dominant pole. This pole has not been calculated here, but it is evident that this pole is due to the closed loop response of the Miller feedback system, and is at the frequency at which the Miller feedback system goes below a gain of unity in the open loop case. In other words, the non-dominant pole of the DC loop is equal to the high frequency gain bandwidth of the Miller loop. The low frequency gain bandwidth of the Miller loop determines the dominant pole of the DC loop. 
     Many circuit configurations are possible for implementing an amplifier with Miller-effect frequency compensation in accordance with the presently claimed invention. Two primary requirements are some form of Miller feedback to a low impedance circuit node, such as the source terminal of a cascode circuit. FIGS. 21-28 represent a number of common amplifier types that have been modified to implement amplifiers with Miller-effect frequency compensation in accordance with the presently claimed invention. The primary application of this compensation includes a resistance in series with capacitor C 2 . Other than as a resistor per se, such resistance can be implemented in a number of ways which are well known in the art, such as with a P-MOSFET or an N-MOSFET. Regardless of the specific implementation, it is advantageous to design the circuit such that the resistance tracks the transconductance gm 1  of transistor M 1  and the aforementioned factor A as expressed in Equation 13. In the case of a P-MOSFET or N-MOSFET used as the resistance, the device is biased with a ratio of the same current that flows through the cascode circuitry to provide excellent tracking of transconductance gm over PVT. 
     FIG. 21 is a P-MOSFET input folded cascode amplifier using an N-MOSFET as the resistance to provide the zero. 
     FIG. 22 is an N-MOSFET input folded cascode amplifier using a P-MOSFET as the resistance to provide the zero. 
     FIG. 23 is a P-MOSFET telescopic amplifier using a P-MOSFET as the resistance to provide the zero. 
     FIG. 24 is an N-MOSFET telescopic amplifier using an N-MOSFET as the resistance to provide the zero. 
     FIG. 25 is a differential P-MOSFET input folded cascode amplifier using a an N-MOSFET as the resistance to provide the zero. 
     FIG. 26 is a differential N-MOSFET input folded cascode amplifier using a P-MOSFET as the resistance to provide the zero. 
     FIG. 27 is a P-MOSFET telescopic amplifier using a P-MOSFET as the resistance to provide the zero. 
     FIG. 28 is an N-MOSFET telescopic amplifier using an N-MOSFET as the resistance to provide the zero. 
     Referring to FIGS. 29A and 29B, one example technique, among many others well known in the art, for providing a current that is proportional to a resistance and transconductance gm of known devices can be implemented as shown. If the Miller compensation capacitor feeds back to the source of an N-MOSFET cascode amplifier, the circuit of FIG. 29A is used. If it feeds back to the source of a P-MOSFET cascode amplifier, the circuit of FIG. 29B is used. In both cases, the transcunductance gm of transistor M 1  is defined by Equation 16. Equation 13 (repeated below) describes the resistance needed for the compensation. 
     Equation 13          R   z     ≈     A     gm   1                              
     Equation 16          gm   1     =       2     R   ref            (     1   -     1     K         )                              
     If the circuit is designed such that the reference current Iref from FIG. 29A or  29 B flows through the cascode device, as seen in the amplifiers of FIGS. 30-37, and the cascode device is the same as transistor M 1 , then the compensation resistance is described by Equation 17. It should be understood that the resistance used in this bias circuitry should be of the same material as that used for the resistances in the amplifier for which compensation is intended, thereby ensuring that such resistances will be a function of device ratios only. This biasing technique ensures that the compensation zero more precisely cancels the offending pole over PVT where a resistor is used to provide the zero. 
     Equation 17          R   z     =       R   ref     (     A     2        (     1   -     1     K         )         )                            
     FIG. 30 is a P-MOSFET input folded cascode amplifier using a resistor to provide the zero. 
     FIG. 31 is an N-MOSFET input folded cascode amplifier using a resistor to provide the zero. 
     FIG. 32 is a P-MOSFET telescopic amplifier using a resistor to provide the zero. 
     FIG. 33 is an N-MOSFET telescopic amplifier using a resistor to provide the zero. 
     FIG. 34 is a differential P-MOSFET input folded cascode amplifier using a resistor to provide the zero. 
     FIG. 35 is a differential N-MOSFET input folded cascode amplifier using a resistor to provide the zero. 
     FIG. 36 is a P-MOSFET telescopic amplifier using a resistor to provide the zero. 
     FIG. 37 is an N-MOSFET telescopic amplifier using a resistor to provide the zero. 
     In conformance with the foregoing discussion, while the various embodiments of the presently claimed invention as disclosed in FIGS. 13-37 depict the input stages (transistors M 1 , M 2 , M 3 , M 5 , M 6  and M 7 ) as being differential, it should be understood that the presently claimed invention does not require that the input amplification circuitry be differential. Rather, such differential circuitry as disclosed merely constitutes some of the more preferred embodiments, but amplifiers with Miller-effect frequency compensation in accordance with the presently claimed invention can also have single-ended input amplification circuitry, many forms and implementations of which are well known in the art. 
     Similarly, while the various embodiments of the presently claimed invention as disclosed in FIGS. 13-37 depict the output stage (transistor M 4 ) as being a common source circuit, it should be understood that such an output circuit topology is not required by the presently claimed invention. Rather, such output circuitry as disclosed merely constitutes a more preferred embodiment, but amplifiers with Miller-effect frequency compensation in accordance with the presently claimed invention can also have other topologies, including but not limited to a common drain configuration. 
     Further, more than one amplification stage can be included inside the Miller feedback loop. As discussed above, what is important is that the Miller capacitance be fed back back to a low impedance node. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.