Abstract:
A power converter control system for use with a power converter of the type which comprises a plurality of cascade-connected converter units of which at least one converter unit is subjected to continuous control of its conduction phase angle and the remaining converter units are subjected to on-off control of their conductivity is arranged to include a master controller for instructing the number of the converter units to be rendered operative, a reversible counter operative to change its content in response to a phase controlling command applied to the continuously controlled converter unit indicating a maximum or minimum conduction phase angle or delayed phase angle in conduction, a unit change control unit for producing unit changing operation signals to be applied to the respective converter units for controlling the operation of the same, by using one of the binary bits derived from the counter without modification and decoding the remaining bits, and a comparing and identifying circuit which compares the content of the reversible counter with the output of the master controller and causing the reversible counter to operate in response to the aforementioned phase control command until the content of the same becomes identical to the output of the master controller.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an improvement of the power converter control system for use with a power converter comprising a plurality of rectifier units for converting AC current into DC current. 
     This type of power converter is suitable for AC electric locomotives as disclosed in, for example, &#34;Brown Boveri Review&#34;, December 1973, especially pages 526 to 538 and FIGS. 6 and 7. In such a power converter, in order to prevent an adverse affect upon communication equipment and the like due to high frequency currents of harmonics flowing through the AC section, the DC output section is arranged by a plurality of rectifier units connected in cascade wherein one of the rectifier units is subjected to continuous control of its conduction phase angle and the other rectifier units are subjected to on-off control in their conductivity so that the DC output voltage of the power converter is continuously controlled by a conbination of the continuously controlled rectifier unit and selected ones of the on-off controlled rectifier units. 
     One example of a circuit for digitally producing changing operation signals applied to the respective rectifier units has been proposed in Japanese patent application No. 81,120/1974 filed on July 17, 1974 and laid open to public on Jan. 27, 1976 as Japanese patent laid open specification No. 10,348/1976. 
     According to the laid open specification, the changing operation signals applied to the respective rectifier units are produced in the following manner. 
     Fist, a count output of a reversible counter, which changes the content of count when a phase control-command applied to the continuously controlled rectifier unit reaches a value indicating a maximum or minimum conduction phase angle, is converted into a decimal code by means of a decoder. On the other hand, an output of a master controller indicative of the number of the rectifier units to be operated is compared with the output of the decoder in a comparing and identifying circuit and the content of count of the reversible counter is changed such that both the outputs become identical with each other. By taking into consideration of both the decimal code output converted from the decoder and output of the comparator circuit, changing operation signals to be applied to the respective rectifier units are produced by code-conversion by a code converter. 
     Thus, the code converter requires a large number of inputs for producing the changing operation signals applied to the respective rectifier units, resulting in complexity of circuit and increase in fabrication process responsible for inefficiency. 
     SUMMARY OF THE INVENTION 
     A principal object of this invention is to provide an improved control system for a power converter of the type comprising a continuously controlled rectifier unit and on-off controlled rectifier units. Specifically, this invention contemplates to incorporate the control system with a simplified circuit for producing the changing operation signals applied to the respective rectifier units. 
     According to one aspect of this invention, a binary coded output of a reversible counter is compared with an instruction, in the form of a binary code, indicative of the number of rectifier units to be rendered operative and represented by the notch position of a master controller wherein an output of the first bit in the content of the reversible counter is used for one of the unit changing operation signals without modification and the remaining bits are subjected to code-conversion for producing the remaining ones of the unit changing operation signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic circuit diagram of a principal circuit of a power converter to which the invention is applied. 
     FIG. 2 is a waveform diagram useful to explain the operation of the circuit shown in FIG. 1. 
     FIG. 3 is a circuit diagram of a unit changing control circuit embodying the invention. 
     FIG. 4 is a detailed diagram of a part of the circuit shown in FIG. 3. 
     FIG. 5 is a circuit diagram of another example of principal circuit to which the invention is applicable. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring first to FIG. 1, a principal circuit arrangement of a power converter to which the invention is applied will be explained. 
     A main transformer MT as illustrated in FIG. 1 has a primary winding P 1  connected to a single phase AC power supply and a secondary winding assembly divided into windings S 1  to S 4  which are respectively connected to rectifier units U 1  to U 4  to be described later. The secondary winding S 1  with a center tap is connected to the rectifier unit U 1  which includes thyristors 11P, 12P, 13P, 11N, 12N and 13N connected in a three-phase bridge configuration. The secondary winding S 2  is connected to the rectifier unit U 2  including thyristors 21P, 22P, 21N and 22N connected in a bridge configuration, the secondary winding S 3  to the rectifier unit U 3  including thyristors 31P, 32P, 31N and 32N connected in a bridge configuration, and the secondary winding S 4  to the rectifier unit U 4  including thyristors 41P, 42P, 41N and 42N also connected in a bridge configuration. These secondary windings respectively share the total secondary AC voltage at ratios of 
     
         S.sub.11 :S.sub.12 :S.sub.2 :S.sub.4 = 1:1:1:2:2:2 
    
     where S 11 , S 12  represent two divisions of the secondary winding S 1  with respect to the center tap. 
     DC output sections of the rectifier units U 1  to U 4  are connected in series to form a cascade configuration. These rectifier units U 1  to U 4  constitute a single power converter, the DC output current of which is smoothed by a smoothing reactor DCL and then fed to a DC series motor M comprising an armature A and a field winding F. 
     In the rectifier units U 1  to U 4 , the unit U 1  is used as the one which is subjected to continuous control and the remaining units U 2  to U 4  are used as the other ones which are subjected to one-off control. 
     While the thyristors 11P and 11N of continuously controlled rectifier unit U 1  operate in a mode of diode, other thyristors 12P, 12N, 13P and 13N operate each with a controllable phase lag in conduction which changes continuously in accordance with a phase controlling command from a phase shifter as described later. This rectifier unit U 1  first operates with thyristors 11P, 11N, 12P and 12N connected in a single phase bridge circuit. Namely, the single phase bridge circuit is supplied with the voltage division S 11  of secondary winding S 1  and the controllable lag angle α for the thyristors 12P and 12N is controlled continuously from a maximum phase lag (180°) to a minimum phase lag (0°). When the controllable lag angle α reaches the minimum phase, the thyristors 11P, 11N, 12P and 12N form a so-called full wave rectifier circuit. 
     Thereafter, with the controllable lag angle α for thyristors 12P and 12N maintained at the minimum phase, the controllable lag angle α for thyristors 13P and 13N is continuously controlled from the maximum phase lag to the minimum phase lag. At this time, the DC output voltage of rectifier unit U 1  is equal to the sum of a voltage resulting from the full wave rectification of the AC voltage across the winding S 11  and a voltage resulting from the rectification of the AC voltage across the winding S 12  in accordance with the controllable lag angle for thyristors 13P and 13N. 
     In contrast, the on-off controlled rectifier units U 2  to U 4  each operate, on the one hand, as a full wave rectifier circuit, when being rendered on-state, to provide a DC output voltage corresponding to a full wave rectified voltage and on the other hand, when these rectifier units are rendered off-state, the thyristors 21P, 21N, 31P, 31N, 41P and 41N operate in the mode of diode while the thyristors 22P, 22N, 32P, 32N, 42P and 42N are non-conductive so that the rectifier units U 2  to U 4  provide no DC output voltages. 
     It will be apprecited that although the rectifier units U 1  to U 4  are shown to be constituted by thyristors in order to operate the units not only in a rectifier mode, but also in an inverter mode, they may be constituted, if merely required to operate in the rectifier mode, by a mixed bridge connection of thyristors and diodes, in which diodes may be substituted for thyristors 11P, 11N, 21P, 21N, 31P, 31N, 41P and 41N of the rectifier units U 1  to U 4 . 
     Turning now to FIG. 2, the operation of the principal circuit of FIG. 1 will be described. As diagrammatically shown in FIG. 2, waveforms U 11P  and U 12P  are operation signals applied to the continuously controlled rectifier unit U 1  and more particulary the waveform U 11P  is of an operation signal applied to the single phase bridge circuit of thyristors 11P, 11N, 12P and 12N when the system is rendered operative and the waveform U 12P  is of a changing operation signal applied to the thyristors 13P and 13N of the rectifier unit U 1  when the output voltage of the rectifier unit U is controlled by changing the phase lag of the thyristors 13P and 13N while maintaining the thyristors 12P and 12N at the minimum phase lag. Waveforms U 2P , U 3P  and U 4P  are unit changing operation signals applied to the on-off controlled rectifier units U 2 , U 3  and U 4 , respectively. 
     The operation signal U 11P  is always applied to the rectifier unit U 1  when the system is operating and the changing operation signal U 12P  is applied to the rectifier unit U 1  in response to each of the notch commands 2N, 4N, 6N and 8N which are produced by a master controller as mentioned hereinafter in detail, while the unit changing operation signal U 2P  continuously applied to the rectifier unit U 2  with the notch commands 3N and succeeding thereto, the unit changing operation signal U 3P  is continuously applied to the rectifier unit U 3  with the notch commands 5N and succeeding thereto and the unit changing operation signal U 4P  is continuously applied to the rectifier unit U 4  with the notch commands 7N and succeeding thereto. 
     With the notch command 1N, the operation signal U 11P  is applied to the rectifier unit U 1  and the controllable lag angle α for thyristors 12P and 12N is continuously controlled, in a manner as described hereinafter, from the maximum phase lag (180° ) to the minimum phase lag (0°). When this controllable lag angle α reaches the minimum phase lag and the notch command 2N is given, the operation signal U 12P  is applied, in addition to the operation signal U 11P , to the rectifier unit U 1  whereby the controllable lag angle of the thyristors 12P and 12N is maintained at the minimum phase lag, while the controllable lag angle α for thyristors 13P and 13N is continuously controlled from the maximum phase lag to the minimum phase lag. With this controllable lag angle α for thyristors 13P and 13N reaching the minimum phase and the notch command 3N, the unit changing operation signal U 2P  is applied to the rectifier unit U 2  to render it on-state so that the rectifier unit U 2  shares a DC output voltage equal to the maximum or eventual output of the rectifier unit U 1 , while the DC output voltage of rectifier unit U 1  is returned to zero and the operation signal U 11P , still applied to the rectifier unit U 1 , acts in the same manner as with the notch command 1N, thereby again repeating the continuous control of the controllable lag angle α for thyristors 12P and 12N from the maximum phase to the minimum phase. When the controllable lag angle α for thyristors 12P and 12N reaches the minimum phase with the notch command 3N and then the notch command 4N is given, the operation signal U.sub. 12P is again applied to the rectifier unit U 1 . Further, when the total DC output voltage of rectifier unit U 1  reaches the maximum value (at the minimum phase lag or controllable lag angle for thyristors 13P and 13N, with the notch command 4N and then the notch command 5N is given, the unit changing operation signal U 3P  is applied to the rectifier unit U 3 , thereby rendering it on-state. Consequently, the rectifier unit U 3  thus turned on shares a DC output voltage equal to the maximum DC output of the rectifier unit U 1 . 
     A similar operation is repeated for notch commands 6N to 8N and hence the DC output voltage fed to the DC motor M is increased continuously. 
     Referring now to FIG. 3, a unit change control circuit will be described which produces operation signals U 11P , U 12P , U 2P , U 3P  and U 4P  to be applied to the rectifier units. 
     A master controller 1 is shown in FIG. 3 to have contacts N 0  to N 8  and a decoder 10. The master controller further includes a manual operating mechanism (not shown) for operating the contacts N 1  to N 8 , in a manner as described hereinafter, thereby producing signals corresponding to the notch commands 1N, 2N, . . . 8N, successively. The contact N o , a normally-closed contact, is provided for detecting power failure and in application to the power converter for electric locomotives, it is opened with the absence of the supply line voltage which occurs, for example, when the pantograph removes from the supply line or the locomotive runs on an isolating section of the route where the power supply system is changed from one to another. 
     The contacts N 1  to N 8  are normally closed and selectively opened according to the respective notch commands given by the manual operating mechanism. With the notch command 1N, the contact N 1  is opened; with notch command 2N, the contacts N 1  and N 2  are opened; with notch command 3N, the contacts N 1 , N 2  and N 3  are opened; . . .; and with notch command 8N, the contacts N 1 , N 2 , . . . , N 8  are opened. 
     The closed-state of these contacts N 0  to N 8   corresponds to a logic &#34;0&#34; and the opened-state to a logic &#34;1&#34;. 
     The decoder 10 receives input signals representative of the states of contact N 2  to N 8  and delivers three outputs in the form of a binary code. A signal respresentative of the state of contact N 1  is used as the operation signal U 11P  without modification because the operation signal U 11P  is required to occur for all the notch commands, as shown in FIG. 2, and the contact N 1  which is opened in common to all the notch commands meets this requirement. 
     A phase shifter 2 compares a motor current I M  flowing through the DC motor M shown in FIG. 1 with a current command Ia indicative of a predetermined value of the motor current and instructs the controllable lag angle α for thyristors of the continuously controlled rectifier unit U 1  such that the motor current I M  approaches to the command current Ia. The command current Ia is usually determined to be equal to the upper limit of the motor current at the normal running thereof so that the lag angle α reaches the maximum or minimum value before the motor current I M  reaches the command current Ia. The phase shifter 2 may take the form of a magnetic phase shifter or a semiconductor phase shifter. 
     A phase detector circuit 3 is provided to detect the minimum phase lag (α o ) or the maximum phase lag (α 1 ) of output α from the phase shifter 2. When detecting the minimum phase lag α o , the phase detector circuit delivers a signal which causes the content of a reversible counter 40 in a unit change control circuit 4, as described later, to be increased and when detecting the maximum phase lag α 1 , the phase detector circuit delivers a signal when causes the content of the reversible counter 40 to be decreased. The unit change control circuit 4 operates to change the number of the rectifier units to be operated. This phase detector circuit 3 will be described in move detail with reference to FIG. 4. As shown therein, the phase detector circuit 3 comprises one-shot multivibrator circuits 31 to 34, an inverter gate 35 and AND-gates 36 and 37. The one-shot multivibrator circuits 31 and 32 receive a synchronizing pulse SP which is produced in synchronism with each zero potential of the single phase AC power supply shown in FIG. 1. The one-shot multivibrator circuit 31 delivers a narrow width pulse output to the AND-gate 37 while the other one-shot multivibrator circuit 32 delivers a narrow width pulse output to the AND-gate 36 through the inverter gate 35. That is to say, the one-shot multivibrator 31 determines a timing for detecting the minimum phase lag α o  of the output α from phase shifter 2 and the one-shot multivibrator 32 serves to prevent an erroneous operation of the subsequenct one-shot multivibrator 33 which would occur when the output α of the phase shifter 2 exceeds the minimum phase lag α 1 . 
     The minimum phase lag α o  can be detected in such a manner that when the output α of the phase shifter 2 is changed from the maximum phase lag and reaches the minimum phase lag, both the outputs of AND-gate 36 and one-shot multivibrator 31 assume logic &#34;1&#34; so that the output of the AND-gate 37 changes from a logic &#34;0&#34; to &#34;1&#34;, thereby causing the output of one-shot multivibrator 33 to change from a logic &#34;0&#34; to &#34;1&#34;. 
     The maximum phase lag α 1 , on the other hand, can be detected by the one-shot multivibrator 34 receiving the output of the phase shifter 2. 
     The unit change control circuit 4 as shown in FIG. 3 comprises a reversible counter 40, a decoder 41, NAND-gate 42 amd 43, OR-gates 44 and 45, an inverter gate 46 and a one-shot multivibrator 47. 
     The reversible counter 40 has outputs of three bits, the first bit of which is used as the operation signal U 12P  without modification. Namely, the operation signal U 12P  is generated alternately in accordance with successive changes of the notch command, making it possible to use the first bit output of the reversible counter 40 without modification. Second and third bits O 2  and O 3  are delivered to the decoder 41. When receiving the bits O 2  and O 3 , the decoder 41 converts them into binary code outputs D o  to D 3 . An output b of the NAND-gate 42 causes the content of the reversible counter 40 along with the minimum phase signal α o  from the phase shifter 3 to be increased whereas an output b&#39; of the NAND-gate 43 causes the content of the reversible counter 40 along with the maximum phase signal α 1  to be decreased. In other words, the count content of reversible counter 40 is increased through the NAND-gate 42 when the notch command from the master controller 1 increases successively and it is decreased through the NAND-gate 43 when the notch command decreases successively. When receiving an output of the inverter 46 which corresponds to an inverted signal of the first bit output of reversible counter 40 and the output D 3  of decoder 41, the OR-gate 44 prevents the count content of the reversible counter 40 from being increased. By receiving the first bit O 1  of reversible counter and the output D o  of decoder 41, the OR-gate 45 prevents the count content of the reversible counter 40 from being increased. Irrespective of the notch up operation in which the notch command is changed from a lower value to a higher value and the notch-down operation in which the notch command is reversely changed, these OR-gates 44 and 45 stop the counting operation of the reversible counter whenever the notch command of the master controller 1 reaches the final notch, thereby preventing the operation signals to be applied to the respective rectifier units from being changed. 
     the one-shot multivibrator 47 receives the output b of NAND-gate 42 and delivers a gate interrupting signal go. This gate interrupting signal go operates, through circuits not shown, to rapidly return the phase signal of the phase shifter 2 to a signal indicative of the maximum phase lag from a signal indicative of the minimum phase lag. 
     A comparing and identifying circuit designated at reference numeral 5 compares a signal (in response to the notch command) corresponding to an output of the decoder 10 in the master controller 1, which has been inverted through respective inverter gates 51 to 53, with the respective first to third bit output O 1  to O 3  from the reversible counter 40. When the number represented by the notch command from the master controller 1 exceeds the content of the reversible counter, the comparing and identifying circuit delivers a signal a to the NAND-gate 42 through an AND-gate 55 so that the count content of the reversible counter 40 is increased until the number represented by the notch command coincides with the count content. Conversely, when the number represented by the notch command is smaller than the count content, the comparing and identifying circuit delivers a signal a&#39;  to the NAND-gate 43 so that the content of reversible counter is decreased until the number repesented by notch command coincides with the content content. It will be appreciated tht the AND-gate 55 receives, at one input, the output of the comparing and identifying circuit and, at the other input, a signal which corresponds to an inversion by the inverter gate 54 of the signal representative of the state of contact No. This is to say, on the condition that no power failure is present, the reversible counter 40 is allowed to increase its count content. 
     A code converter 6 comprises NAND-gates 60 and 61 and an inverter gate 62 and receives the outputs D 1  to D 3  of the decoder 41 to produce the operation signals U 2P , U 3P  and U 4P  for the on-off controlled rectifier units. 
     The following is a truth value table of the reversible counter 40, decoder 41 and operation signals with respect to the notch command from master controller 1. 
     
         ______________________________________  1N   2N     3N     4N   5N   6N   7N   8N______________________________________0.sub.1 0      1    0    1    0    1    0    140   0.sub.2 0      0    1    1    0    0    1    10.sub.3 0      0    0    0    1    1    1    1D.sub.0 0      0    1    1    1    1    1    1D.sub.1 1      1    0    0    1    1    1    141D.sub.2 1      1    1    1    0    0    1    1D.sub.3 1      1    1    1    1    1    0    0U.sub.11P    1      1      1    1    1    1    1    1U.sub.12P    0      1      0    1    0    1    0    1U.sub.2P 0      0      1    1    1    1    1    1U.sub.3P 0      0      0    0    1    1    1    1U.sub.4P 0      0      0    0    0    0    1    1______________________________________ 
    
     Taking this table into mind, the opration of the circuit of FIG. 3 will be described with respect to the notch commands 1N to 8N. 
     When the master controller 1 delivers no notch command (that is, the notch is set off), the outputs a and a&#39; both assume &#34;0&#34; so that the outputs b and b&#39;  of NAND gates 42 and 43 both assume &#34; 1&#34;, thereby prohibiting the operation of reversible counter 40. It should be noted that the reversible counter 40 changes its count content when its input b or b&#39;  changes from &#34;1&#34; to &#34;0&#34;. 
     Then when the master controller 1 instructs the notch command 1N at time t 1  or FIG. 2, the operation signal U 11P  for thyristors 12P and 12N is applied to the rectifier unit U 1 . On the other hand, a control input is fed to the phase shifter 2 by way of a separate circuit system and the controllable lag angle α for thyristors 12P and 12N is continuously controlled along with the operation signal U 11P  from the maximum phase lag (180°) to the minimum phase lag (0° ) between times t 1  and t 2  of FIG. 2. As far as the notch command 1N is given, the comparing and identifying circuit 5 ceases its operation and its output a is maintained at &#34;0&#34;. 
     Thereafter, when the notch command 2N is given at time t 2  of FIG. 2, the comparator unit 5 detects that the notch command 2N is larger than the output of reversible counter 40, causing the output a of the comparing and identifying circuit 5 to change from &#34;0&#34; to &#34;1&#34;. On the other hand, as soon as the NAND gate 42 which has been supplied with the minimum phase signal α o  from the phase detector circuit 3 receives the synchronizing pulse SP, the output b of NAND gate 42 is changed from &#34; 1&#34; to &#34;0&#34;, thus delivering a countup signal to the reversible counter 40. 
     Accordingly, at time t 2  of FIG. 2, the count content of reversible counter 40 is incresed by one count. This leads to change of the first bit output O 1  from &#34;0&#34; to &#34;1&#34;, producing the change operation signal U 12P  for the rectifier unit U 1 . 
     The output b of NAND gate 42 is also delivered to the one-shot multivibrator 47, which in turn produces the gate interrupting signal go to be delivered to the control input of the phase shifter 2 so as to rapidly return its phase signal α to the maximum phase lag from the minimum phase lag. As seen, as the phase signal is returned to the maximum from the minimum, the output α o  of the phase detector circuit 3 is again changed to &#34;0&#34;. The output a of the comparing and identifying circuit is also changed from &#34;1&#34; to &#34;0&#34; to prohibit the counting operation of the reversible counter 40 on the condition that the output of reversible counter 40 coincides with the number represented by notch command of the master controller 1. 
     Then, the output α of phase shifter 2 which has once been returned to the maximum phase lag is continuously controlled by the separate circuit system between times t 2  and t 3  of FIG. 2 such that the controllable lag angle α for thyristors 13P and 13N of the rectifier unit U 1  changes from the maximum phase lag to the minimum phase lag. When the output α of this phase shifter 2 reaches the minimum, the phase detector 3 again detects the minimum phase lag α 0  and delivers the output α o  assuming &#34;1&#34;. 
     Under this condition, when receiving the notch command 3N from the master controller 1, the comparing and identifying unit 5 delivers the output a assuming &#34;1&#34; which again opens the NAND-gate 42 for effecting count-up of the reversible counter 40 so that the count content of the reversible counter 40 is increased by one in synchronism with the synchronizing pulse SP. Thus, the first bit output O 1  of reversible counter 40 is changed from &#34;1&#34; to &#34;0&#34; and the second bit output O 2  changes from &#34;0&#34; to &#34;1&#34;. With the first bit output O 1  changes to &#34;0&#34;, the operation signal U 12P  disappears and the unit chaging operation signal U 2P  for the rectifier unit U 2  changes from &#34;0&#34; to &#34;1&#34; thereby to change the number of rectifier units to be operated. Namely, with the notch command 3N, the second and third bit outputs O 2  an O 3  of the reversible counter 40 to be delivered to the decoder 41 assume &#34;1&#34; and &#34;0&#34;, respectively, and hence the outputs D 1 , D 2  and D 3  of the decoder 41 respectively assume &#34;0&#34;, &#34;1&#34; and &#34;1&#34; as shown in the table. In this manner, only the NAND-gate 60 assumes &#34;1&#34; by receiving the output of the decoder 41, thereby causing the operation signal U 2P  to assume &#34;1&#34;. 
     On the other hand, concurrently with change in the number of rectifier units to be operated, the output α of the phase shifter 2 is rapidly returned to the maximum phase lag from the minimum phase lag, while the DC output voltage of the rectifier unit U 1  is reduced to zero by turning off the thyristors 12P, 12N, 13P and 13N, thereby preventing the DC voltage and current applied to the motor circuit from being suddenly changed. 
     A similar operation is repeated with the successive notch commands of higher order until the condition at the time t 9  of FIG. 2 is reached where all the operation signals U 11P , U 12P , U 2P , U 3P  and U 4P  assume &#34;1&#34; so that all the rectifier units are under operation thereby to produce the maximum DC voltage. 
     In the foregoing description, the notch commands are changed successively one by one by means of the master controller 1. However, the rectifier units are operated in the same manner even when the maximum notch command, i.e., notch command 8N, is given without the steps of giving the intermediate notch commands. 
     Conversely, when the notch-down operation in which the notch command is changed from higher to lower, the operations at times t 1  to t 9  are effected reversely. 
     Obviously, the unit changing control operation as having been described in the foregoing is applicable to a power converter whether it operates in the rectifier mode as mentioned hereinbefore or in the inverter mode. 
     Furthermore, the application of the invention is not limited to a power converter of the type as shown in FIG. 1 but the invention is also applicable to a power converter of another type as shown in FIG. 5. 
     The power converter of FIG. 5 with the same elements as FIG. 1 designated at the same reference numerals differs from the circuit of FIG. 1 in that the continuously controlled rectifier unit U 1  is divided into independent single phase bridge circuits U 11  and U 12 . Voltage division ratios between secondary windings of a main transformer MT are 
     
         S.sub.11 :S.sub.12 :S.sub.2 :S.sub.3 :S.sub.4 = 1:1:2:2:2 
    
     in such a power converter circuit, the operation signals for rectifier units U 11 ,U 12 , U 2 , U 3  and U 4  are produced in the same manner as in the operation signals U 11P , U 12P , U 2P , U 3P  and U 4P  as illustrated in FIG. 2 and explained with reference to FIG. 3. 
     Thyristors of both the continuously controlled rectifier units U 11  and U 12  may be controlled to have their controllable lag angle continuously changed or, alternatively, one of the rectifier units U 11  and U 12  is used as a continuously controlled rectifier unit, while the other rectifier unit as an on-off controlled rectifier unit so that the rectifier units U 11  and U 12  are, in combination, served for continuously controlling operation. 
     As having been described, the invention modifies the outputs of the reversible counter following the second bit through the decoder and uses them as operation signals for on-off controlled rectifier units, thereby providing the improved control system for power converter, which improvement includes reduction in the number of parts and wirings and minimized fabrication time, resulting in a simplified circuit arrangement.