Abstract:
A voltage-controlled oscillator that can achieve low phase noise while ensuring stable oscillation startup and stable oscillation maintenance even under low supply voltage conditions. The voltage-controlled oscillator includes an LC parallel resonant circuit, whose impedance varies with a control input voltage and a negative resistance circuit for introducing negative resistance into the LC parallel resonant circuit, wherein the negative resistance circuit includes at least: a first amplifier circuit, provided in parallel with the LC parallel resonant circuit and having a first pair of transistors cross-coupled via a capacitor, that achieves class-C amplifier operation by biasing the gate of each transistor in the first transistor pair with a first bias voltage; and a similarly configured second amplifier circuit that achieves class-C amplifier operation by biasing the gate of each transistor with a second bias voltage which is different from the first bias voltage.

Description:
[0001]    This application claims benefit of Serial No. 2006-121248, filed 19 May 2009 in Japan and which application is incorporated herein by reference. To the extent appropriate, a claim of priority is made to the above disclosed application. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a voltage-controlled oscillator (VCO), which oscillates at a frequency proportional to a control input voltage, and more particularly to an LC-tank voltage-controlled oscillator (LC-VCO). 
         [0004]    2. Description of the Related Art 
         [0005]    The phase noise of an LC-tank voltage-controlled oscillator is determined by the S/N ratio (Signal-to-Noise Ratio) in the LC tank. The root mean square values of signal voltage V sig  and noise voltage V n  are respectively expressed as 
         [0000]      V sig   2 =R t   2 I sig   2    
         [0000]      V n   2 =4kTR t    
         [0000]    where k is the Boltzmann constant, T is the absolute temperature, R t  is the parallel impedance of the LC tank, and I sig  is the signal current amplitude. 
         [0006]    Hence, the root mean square value of the S/N ratio is given as 
         [0000]      ( S/N ) 2   =R   t   2   I   sig   2 /4 kT    
         [0000]    From the above equation, it can be seen that phase noise improves with increasing signal amplitude. However, since the signal amplitude is limited by supply voltage, the phase noise degrades when VCO is operated at a low supply voltage. 
         [0007]    In the prior art, a transformer-feedback (TF) VCO is proposed as a VCO that operates at a low supply voltage (refer to non-patent document 1 listed below). In this transformer-feedback VCO, each source node voltage in a cross-coupled transistor pair is lowered below 0 [V] by a transformer, and the voltage amplitude in the LC tank is increased. However, since the operation involves current flow in a region where the impulse sensitivity function (ISF) is large, it is difficult to achieve a low-phase-noise design with this technique. 
         [0008]    On the other hand, an LC-VCO known as a Class-C VCO is proposed (refer to non-patent documents 2 and 3 listed below). This VCO is constructed so that, in an LC-VCO having a cross-coupled transistor pair, the transistor gate portion is DC-cut by a capacitor to lower the gate bias below the threshold, thereby causing the transistor to operate as if it were a class-C amplifier. 
         [0009]    In a VCO, the ISF from thermal noise to phase noise differs depending on the phase of oscillation. More specifically, the ISF is smaller for a phase where the amplitude of the oscillation voltage is larger. The class-C VCO is intended to achieve low phase noise by flowing a current only in a phase range where the ISF is small. However, in the class-C VCO, the gate bias must be reduced below the threshold voltage. As a result, under low supply voltage conditions, the amplitude cannot be made large enough, and oscillations may not occur. On the other hand, under low amplitude conditions, the conduction angle cannot be reduced to take advantage of the characteristics of the class-C VCO, and the intended low phase noise cannot be achieved. 
         [0010]    Non-patent document 1: K. Kwok, and H. C. Luong, “Ultra-Low-Voltage High-Performance CMOS VCOs Using Transformer Feedback,” IEEE JSSC, vol. 40, no. 3, pp. 652-660, March 2005. 
         [0011]    Non-patent document 2: A. Mazzanti, and P. Andreani, “Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise,” IEEE JSSC, vol. 44, no. 12, pp. 2716-2729, December 2008. 
         [0012]    Non-patent document 3: A. Mazzanti, and P. Andreani, “A 1.4 mW 4.90-to-5.65 GHz Class-C CMOS VCO with an Average FoM of 194.5 dBc/Hz,” ISSCC, No. 26-2, February 2008. 
       SUMMARY OF THE INVENTION 
       [0013]    The present invention has been devised in view of the above problem, and it is an object of the invention to provide a voltage-controlled oscillator that can achieve low phase noise while ensuring stable oscillation startup and stable oscillation maintenance even under low supply voltage conditions. 
         [0014]    To achieve the above object, according to the present invention, a voltage-controlled oscillator is provided, which includes an LC parallel resonant circuit whose impedance varies with a control input voltage and a negative resistance circuit for introducing negative resistance into the LC parallel resonant circuit, the negative resistance circuit comprising at least: a first amplifier circuit, provided in parallel with the LC parallel resonant circuit and having a first pair of transistors cross-coupled via a capacitor, that achieves class-C amplifier operation by biasing a gate or base of each transistor in the first transistor pair with a first bias voltage; and a second amplifier circuit, provided in parallel with the LC parallel resonant circuit and having a second pair of transistors cross-coupled via a capacitor, that achieves class-C amplifier operation by biasing a gate or base of each transistor in the second transistor pair with a second bias voltage which is different from the first bias voltage. 
         [0015]    In the voltage-controlled oscillator according to the present invention, amplifier circuits each having a cross-coupled transistor pair are provided in parallel (dual configuration), and are respectively biased with different DC bias voltages, achieving class-C amplifier operation with different conduction angles. In this configuration, the amplifier circuit having the smaller conduction angle acts to reduce the phase noise, while the amplifier circuit having the larger conduction angle acts to ensure stable oscillation startup. As a result, the voltage-controlled oscillator according to the present invention achieves low phase noise while ensuring stable oscillation startup and stable oscillation maintenance even under low supply voltage conditions. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    Further features and advantages of the present invention will be apparent from the following description with reference to the accompanying drawings, in which: 
           [0017]      FIG. 1  is a circuit diagram showing one embodiment of a voltage-controlled oscillator (VCO) according to the present invention; 
           [0018]      FIG. 2  is a waveform diagram showing the variations of one output signal voltage (drain voltage) and one and other gate voltages in the VCO shown in  FIG. 1 ; 
           [0019]      FIG. 3  is a waveform diagram showing the variation of the current flowing in the VCO of  FIG. 1  for comparison with a conventional class-C VCO; 
           [0020]      FIGS. 4A and 4B  are diagrams showing modified examples of amplifier circuits in the voltage-controlled oscillator (VCO) of  FIG. 1 ; 
           [0021]      FIG. 5  is a circuit diagram showing another embodiment of a voltage-controlled oscillator (VCO) according to the present invention; and 
           [0022]      FIGS. 6A and 6B  are diagrams showing modified examples of amplifier circuits in the voltage-controlled oscillator (VCO) of  FIG. 5 . 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0023]    The embodiments of the present invention will be described below with reference to the accompanying drawings.  FIG. 1  is a circuit diagram showing one embodiment of a voltage-controlled oscillator (VCO) according to the present invention. As shown in  FIG. 1 , the VCO includes an LC parallel resonant circuit (LC tank circuit)  100 , a first amplifier circuit  120 , and a second amplifier circuit  140 . 
         [0024]    The LC parallel resonant circuit  100  is essentially a loop, which as shown in  FIG. 1 , includes an inductor L, two fixed capacitors C 01  and C 02 , and two variable capacitors C 03  and C 04 . An intermediate tap on the inductor L is connected to a supply voltage V DD . The capacitances of the variable capacitors C 03  and C 04  vary with a control input voltage V CTL  which is applied to their input terminals via a node connecting between them. The two ends of the inductor L are connected to output terminals which provide the two output signal voltages V OUT1  and V OUT2  of the VCO. 
         [0025]    The first and second amplifier circuits  120  and  140  act as a negative resistance circuit that supplies energy to the LC parallel resonant circuit  100  in such a manner as to cancel out the resistance of the resonant circuit  100  by introducing negative resistance into the resonant circuit  100 . That is, N-channel MOS (Metal-Oxide Semiconductor) FET (Field-Effect) transistors contained in the respective amplifier circuits act to increase the current that flows through the LC parallel resonant circuit  100 . 
         [0026]    More specifically, the first amplifier circuit  120  is provided in parallel with the LC parallel resonant circuit  100 , and includes a first transistor pair formed from transistors (NMOSFETs) Q 11  and Q 12  cross-coupled via capacitors C 11  and C 12 . That is, the first output signal voltage V OUT1  is connected not only to the drain of the transistor Q 11  but also to the gate of the transistor Q 12  via the DC-cut capacitor C 11 . Likewise, the second output signal voltage V OUT2  is connected not only to the drain of the transistor Q 12  but also to the gate of the transistor Q 11  via the DC-cut capacitor C 12 . The sources of the transistors Q 11  and Q 12  are both grounded. On the other hand, the gates of the transistors Q 11  and Q 12  are connected to a bias voltage V gbias1  via resistors R 11  and R 12 , respectively. 
         [0027]    The second amplifier circuit  140  has essentially the same circuit configuration as the first amplifier circuit  120 . The difference is that the gates of the transistors Q 21  and Q 22  are connected to a bias voltage V gbias2 , which is higher than V gbias1 . 
         [0028]    The VCO shown in  FIG. 1  oscillates while maintaining the oscillations in the LC parallel resonant circuit  100 , by the action of the negative resistance circuit formed by the amplifier circuits  120  and  140 . When the total inductance value in the LC parallel resonant circuit  100  is denoted by L, and the total capacitance value by C, the oscillation frequency f of the resonant circuit  100  is expressed by the following equation. 
         [0000]        f= ½π√( LC ) 
         [0029]    The two output signal voltages V OUT1  and V OUT2  of the VCO are 180° out of phase with each other as shown by the following equations, where A t  is the amplitude of each output voltage and φ is the phase of either one of the output voltages. Here, V DS  represents the drain-source voltage of the transistor Q 11 . 
         [0000]        V   OUT1   =V   DD   −A   t  cos φ= V   DS    
         [0000]        V   OUT2   =V   DD   +A   t  cos φ 
         [0000]      A t &lt;V DD    
         [0030]      FIG. 2  shows the voltage waveform of one output signal voltage V OUT1 , i.e., V DS , along with voltage waveforms for a voltage V gs1 -V th  obtained by subtracting the threshold voltage V th  from the gate-source voltage V gs1  of the transistor Q 11  and a voltage V gs2 -V th  obtained by subtracting the threshold voltage V th  from the gate-source voltage V gs2  of the transistor Q 21 . The abscissa represents the phase φ (−π(rad] to +π(rad]). 
         [0031]    In the amplifier circuits  120  and  140 , the gate bias voltage V gbiasn  (n is 1 or 2) is adjusted relative to the transistor threshold voltage V th  such that 
         [0000]        V   gbiasn   +A   t   −V   th &gt;0 
         [0000]    Further, the gate bias voltage V gbiasn  is set so that the following relationship holds. 
         [0000]      V gbias1 &lt;V gbias2    
         [0032]    The transistor Q 11  conducts in the phase range represented by −Φ 1 [rad]&lt;φ&lt;+Φ 1 [rad] where V gs1 -V th &gt;0. In the illustrated example, Φ 1 =π/5. On the other hand, the transistor Q 21  conducts in the phase range represented by −Φ 2 [rad]&lt;φ&lt;+Φ 2 [rad] where V gs2 V th &gt;0. In the illustrated example, Φ 2 =π/2&gt;Φ 1 . 
         [0033]    As a result, drain-source currents I ds1  and I ds2  with current waveforms shown in  FIG. 3  flow through the respective transistors Q 11  and Q 21 . The waveform of the total current I ds1 +I ds2  and the current waveform of a conventional single-conduction class-C VCO (Φ 0 =0.4 π) are also shown in  FIG. 3 . According to the dual-conduction class-C VCO of the present invention, the equivalent conduction angle can be reduced as shown by the waveform of the current I ds1 +I ds2 . 
         [0034]    Then, the current I ds1  having the smaller conduction angle  2 Φ 1  contributes to achieving low phase noise, since the current flows in a concentrated manner in a region centered about the phase φ=0 where the ISF (Impulse Sensitivity Function) is the smallest. On the other hand, the current I ds2  having the larger conduction angle  2 Φ 2  serves as an oscillation startup current to ensure stable oscillation startup and stable oscillation maintenance. 
         [0035]    For transistors Q 21  and Q 22 , where the current I ds2  having the larger conduction angle flows, it is preferable to reduce their transistor sizes. Further, the conduction angle  2 Φ 1  can be reduced by reducing V gbias1  as much as possible under conditions determined by the amplitude. 
         [0036]    With the above operation, the VCO shown in  FIG. 1  can achieve higher performance than the conventional circuit scheme in terms of FoM (Figure of Merit: Phase noise characteristic normalized by power consumption and oscillation frequency). Table 1 below shows a comparison between the circuit scheme of the present invention and the conventional circuit scheme. In the conventional circuit scheme, the lowest possible operating voltage was about 0.35 [V], but in the circuit scheme of the present invention, the circuit can operate at 0.2 [V], thus achieving low power consumption, as well as low phase noise. 
         [0000]    
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Performance comparison between present invention 
               
               
                 and prior art 
               
             
          
           
               
                   
                 Prior art 1 
                 Prior art 1-2 
                 Prior art 1-3 
                 Present invention 
               
               
                   
                   
               
             
          
           
               
                 Technology 
                 0.13 μm CMOS 
                 0.18 μm CMOS 
                 0.18 μm CMOS 
                 0.18 μm CMOS 
               
             
          
           
               
                 Supply 
                 1.0 V 
                 0.5 V 
                 0.35 V 
                 0.3 V 
                 0.2 V 
               
               
                 voltage 
               
               
                 Power 
                 1.3 mW 
                 0.57 mW 
                 1.46 mW 
                 0.159 mW 
                 0.114 mW 
               
               
                 consumption 
               
               
                 Oscillation 
                 4.9 GHz 
                 3.8 GHz 
                 1.4 GHz 
                 4.5 GHz 
                 4.5 GHz 
               
               
                 frequency 
               
               
                 Phase noise 
                 −130 dBc/Hz 
                 −119 dBc/Hz 
                 −129 dBc/Hz 
                 −109 dBc/Hz 
                 −104 dBc/Hz 
               
               
                   
                 @3 MHz-offset 
                 @1 MHz-offset 
                 @1 MHz-offset 
                 @1 MHz-offset 
                 @1 MHz-offset 
               
               
                 FoM 
                 196 dBc/Hz 
                 193 dBc/Hz 
                 190 dBc/Hz 
                 190 dBc/Hz 
                 187 dBc/Hz 
               
             
          
           
               
                 Chip area 
                 0.50 mm 2   
                 0.23 mm 2   
                 0.76 mm 2   
                 0.29 mm 2   
               
               
                 Topology 
                 Class-C 
                 TF 
                 TF 
                 Class-C (dual) 
               
               
                   
                 (single) 
               
               
                   
               
             
          
         
       
     
         [0037]      FIGS. 4A and 4B  are diagrams showing modified examples of the amplifier circuits  120  and  140  in the voltage-controlled oscillator (VCO) of  FIG. 1 . In the amplifier circuits shown in  FIG. 1 , the source of each transistor is directly grounded. However, as shown in  FIG. 4A , the sources of the two transistors may be connected together and their connection point may be grounded via a parallel circuit comprising a current source that flows a constant bias current I BIAS  and a capacitor C TAL  for flowing an alternating current. This configuration serves to reduce the current. Alternatively, as shown in  FIG. 4B , the current source I BIAS  may be replaced by a resistor R TAIL  that forms a pseudo current source. 
         [0038]      FIG. 5  is a circuit diagram showing another embodiment of a voltage-controlled oscillator (VCO) according to the present invention, and  FIGS. 6A and 6B  are diagrams showing modified examples of the amplifier circuits in the voltage-controlled oscillator (VCO) of  FIG. 5 . In the VCO shown in  FIG. 1 , an N-channel MOSFET is used for each transistor. However, as shown in  FIG. 5 , each amplifier circuit may be constructed using P-channel MOSFETs instead of N-channel MOSFETs. In that case, the sources of the two P-channel MOSFETs may be connected together and their connection point may be connected to the supply voltage V DD  via a parallel circuit comprising a bias current source I BIAS  or resistor R TAIL  and a capacitor C TRL , as shown in  FIGS. 6A and 6B . 
         [0039]    Further, in each of the circuits shown in  FIGS. 1 ,  4 A, and  4 B and  FIGS. 5 ,  6 A, and  6 B, N-channel junction field-effect transistors (JFETs) or P-channel JFETs may be used instead of the N-channel MOSFETs or the P-channel MOSFETs, respectively. 
         [0040]    It is also possible to use NPN bipolar transistors or PNP bipolar transistors instead of the N-channel MOSFETs or the P-channel MOSFETs, respectively. When bipolar transistors are used instead of the field-effect transistors (unipolar transistors), the sources are replaced by the emitters, the gates by the bases, and the drains by the collectors. 
         [0041]    While the above embodiments have each been described as being provided with two amplifiers each having a cross-coupled transistor pair, it is also possible to connect a third amplifier circuit in parallel with the LC parallel resonant circuit and to achieve class-C amplifier operation with a third conduction angle by applying a third bias voltage to its gate or base. Such a VCO configuration can achieve a further precise oscillation-startup and low-noise design. In other words, the number of amplifier circuits each having a cross-coupled transistor pair can be suitably chosen according to the design. 
         [0042]    The voltage-controlled oscillator according to the present invention can be used in application that require ultra-low power consumption, such as wireless sensor networks, battery-driven mobile devices, and biometrics. 
         [0043]    The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiment is therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.