Abstract:
Disclosed herein are a printed circuit board including: an insulating layer; and a metal circuit layer formed on at least one surface of the insulating layer, wherein the metal circuit layer has surface roughness on only its one surface, and a method of manufacturing the same.

Description:
CROSS REFERENCE(S) TO RELATED APPLICATIONS 
       [0001]    This application claims the foreign priority benefit under 35 U.S.C. Section 119 of Korean Patent Application No. 10-2013-0094190, entitled “Printed Circuit Board and Method of Manufacturing the Same” filed on Aug. 8, 2013, which is hereby incorporated by reference in its entirety into this application. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a printed circuit board and a method of manufacturing the same. 
         [0004]    2. Description of the Related Art 
         [0005]    In general, a printed circuit board (PCB) is used in industrial/consumer applications and the like. Such a printed circuit boards is a substrate made of a phenol resin, an epoxy resin and the like, on which circuit wiring is formed so as to mount a variety of components, and mechanically supports and electrically connects electronic components to supply power. 
         [0006]    Recently, as electronic products becomes smaller, thinner, denser, packaged, lighter and simpler in order to improve portability, printed circuit boards have become multi-layered, micro-patterned, smaller and packaged to meet such demands. 
         [0007]    Accordingly, printed circuit boards in which electronic components are embedded need to be highly dense and thin, and thus are changing from single-layer PCB to multi-layered PCBs. Further, components are also changing from a dual in-line package type (DIP) to a surface mount technology type (SMT), such that packaging density is ever-increasing. 
         [0008]    In manufacturing printed circuit boards, since metal circuit layers and insulating layers made of polymer are alternately formed, it is important to strongly attach two different materials to each other. 
         [0009]    To this end, previously, printed circuit boards undergo a preprocess in which surface roughness is formed on a metal circuit layer using an etching solution before an insulating layer is stacked, so as to increase adhesion between the metal circuit layer and the insulating layer. 
         [0010]    However, when preprocessed to form surface roughness on a metal circuit layer using an etching solution, the width and thickness of the metal circuit layer are lost. Therefore, in forming micro metal circuit layers, a metal circuit layer may be lost or a desired electronic property may not be obtained. 
         [0011]    Lately, in forming micro metal circuit layers, instead of the preprocessing using an etching solution to form surface roughness, there has been an attempt to improve materials of metal circuit layers or insulating materials. However, there is still a problem in that a plating solution permeates between a metal circuit layer and an insulating film where adhesion strength is weak in the final plating process to perform surface finish such as electroless nickel electroless palladium immersion gold (ENEPIG) method and the like. 
       PRIOR ART DOCUMENT 
     Patent Document 
       [0000]    
       
         (Patent Document 1) Korean Patent Laid-open Publication No. 2006-0035162 
       
     
       SUMMARY OF THE INVENTION 
       [0013]    An object of the present invention is to provide a printed circuit board capable of preventing loss of metal circuit layers and a method of manufacturing the same. 
         [0014]    According to an exemplary embodiment of the present invention, there is provided a printed circuit board including: an insulating layer; and a metal circuit layer formed on at least one surface of the insulating layer, wherein the metal circuit layer has surface roughness on only its one surface. 
         [0015]    The metal circuit layers may have a width of 1 to 5 μm. 
         [0016]    The surface roughness may have a dimension of 0.1 to 1 μm. 
         [0017]    The printed circuit board may further include a surface finish layer formed on one surface of the metal circuit layers. 
         [0018]    According to another exemplary embodiment of the present invention, there is provided a method of manufacturing a printed circuit board, including: forming a seed layer on at least one surface of a first insulating layer; forming a plating resist on the seed layer, the plating resist having an opening in which a first metal circuit layer is to be formed; forming the first metal circuit layer in the opening of the plating resist; forming surface roughness on only an exposed portion of the first metal circuit layer, leaving the plating resist unremoved; removing the plating resist; and removing the seed layer, leaving the portion where the first metal circuit layer is formed. 
         [0019]    In the forming of the first metal circuit layer in the opening of the plating resist, the first metal circuit layer may have a width of 1 to 5 μm. 
         [0020]    In the forming of the surface roughness on only an exposed portion of the first metal circuit layer, the surface roughness may have a dimension of 0.1 to 1 μm. 
         [0021]    The method may further include, after the removing of the seed layer, forming, on at least one surface of the first insulating layer, a second insulating layer and a second metal circuit layer having surface roughness on only its one surface in this order; forming a solder resist such that a selected portion of the second metal circuit layer is exposed therethrough; and forming a surface finish layer on a surface of the second metal circuit layer. 
         [0022]    In the forming of the second insulating layer and the second metal circuit, the second metal circuit layer may have a width of 1 to 5 μm and the surface roughness may have a dimension of 0.1 to 1 μm. 
         [0023]    The forming of the surface finish layer on the surface of the second metal circuit layer may be performed by an electroless nickel immersion gold (ENIG) method or an electroless nickel electroless palladium immersion gold (ENEPIG) method. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIGS. 1 and 2  are cross-sectional views of a printed circuit board according to an embodiment of the present invention; and 
           [0025]      FIGS. 3 to 9  are cross-sectional views showing the manufacturing process of a printed circuit board according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0026]    Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the exemplary embodiments are merely illustrative and the present invention is not limited thereto. 
         [0027]    In describing the present invention, when a detailed description of well-known technology relating to the present invention may unnecessarily obscure the spirit of the present invention, a detailed description thereof will be omitted. Further, the following terminologies are defined in consideration of the functions in the present invention and may be construed in different ways depending on the intention of users and operators or conventions. Therefore, the definitions thereof should be construed based on the contents throughout the specification. 
         [0028]    As a result, the spirit of the present invention is defined by the claims and the following exemplary embodiments may be provided to efficiently describe the spirit of the present invention to those skilled in the art. 
         [0029]      FIGS. 1 and 2  are cross-sectional views of a printed circuit board according to an embodiment of the present invention. 
         [0030]    As shown in  FIG. 1 , the printed circuit board according to the embodiment of the present invention may be a single-layer printed circuit board. The printed circuit board includes a first insulating layer  100  and a first metal circuit layer  200  formed on at least one surface of the first insulating layer  100 , the first metal circuit layer  200  having surface roughness on only one surface. 
         [0031]    The first insulating layer  100  may be formed of an insulating material and may use an Ajinomoto build up film (ABF) to easily implement microcircuits or use prepreg to manufacture a thin printed circuit board. In addition, the first insulating layer  100  may be formed of an epoxy resin or a modified epoxy resin, a bisphenol A resin, an epoxy-novolak resin, or an aramid-reinforced, glass fiber-reinforced or paper-reinforced epoxy resin. 
         [0032]    The first metal circuit layer  200  may be formed on at least one surface of the first insulating layer  100 . 
         [0033]    Here, the first metal circuit layer  200  may be formed of copper (Cu) which is a metal having electric conductivity or the like. 
         [0034]    Here, the first metal circuit layer  200  may be formed on both surfaces of the first insulating layer  100  by performing a plating process on one surface of seed layers  110  each formed on both surfaces of the first insulating layer  100 . However, the present invention is not limited thereto. The first metal circuit layer  200  may be formed only one of the surfaces of the first insulating layer  100 . 
         [0035]    In addition, the first metal circuit layer  200  may have the surface roughness  210  thereon. 
         [0036]    Here, the surface roughness  210  may be formed on only one surface of the first metal circuit layer  200 . By forming the surface roughness  210  on only one surface of the first metal circuit layer  200 , loss of the metal circuit layer due to an undercut made under the first metal circuit layer  200  is minimized and electrical property is ensured. 
         [0037]    Preferably, the first metal circuit layer  200  may have a width of 1 to 5 μm, and the surface roughness  210  may have a dimension of 0.1 to 1 μm. If the width of the first metal circuit layer  200  is below 1 μm, the first metal circuit layer  200  may be lost during etching to result in a defect. If the width of the first metal circuit layer  200  is above 5 μm, the loss of the first metal circuit layer  200  due to an undercut is not made during etching. Therefore, the first metal circuit layer  200  has a width of preferably 1 to 5 μm. 
         [0038]    In accordance with the first metal circuit layer thus configured, the surface roughness  210  may have a dimension of preferably 0.1 to 1 μm, in order to prevent the loss of the first metal circuit layer  200  and, in a case of a multi-layered printed circuit board, to maximize adhesive strength between the first metal circuit layer  200  and a second insulating layer  300  which may be stacked on the first metal circuit layer  200 . 
         [0039]    As shown in  FIG. 2 , in a case of a multi-layered printed circuit board, the second insulating layer  300  and a second metal circuit layer  201  may be stacked on either surface of the first insulating layer  100  in this order. 
         [0040]    Here, the second insulating layer  300  may be formed on either surface of the first insulating layer  100  so that it covers the first metal circuit layer  200 . In particular, the second insulating layer  300  may be formed of resin material such as an Ajinomoto build-up film (ABF), prepreg (PPG) or polyimide, an epoxy, etc. 
         [0041]    By forming the surface roughness  210  on only one surface of the first metal circuit layer  200 , adhesive strength between the first metal circuit layer  200  and the second insulating layer  300  which may be stacked on the first metal circuit layer  200  is ensured, such that a printed circuit board having micro metal circuit layers with strong adhesion therebetween may be manufactured. 
         [0042]    The second metal circuit layer  201  may be formed on one surface of the second insulating layer  300  through a plating process using a seed layer  111 . The second metal circuit layer  201  may have the same dimensions with the first metal circuit layer  200 , and, like the first metal circuit layer  200 , may have surface roughness  211  on only one side. 
         [0043]    In addition, a solder resist  310  may be formed on one surface of the second insulating layer  300  so that a selected part of the second metal circuit layer  201  is exposed therethrough. The solder resist  310  covers the remaining parts of the second metal circuit layer  201  except for the exposed portion so as to protect it from soldering or other external environment. 
         [0044]    In addition, a surface finish layer  400  may be formed on one surface of the exposed part of the second metal circuit layer  201  through plating such as an Electroless Nickel Immersion Gold (ENIG) method or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) method. 
         [0045]    By forming the surface roughness  211  on one surface of the second metal circuit layer  201 , it is possible to prevent a plating solution from permeating between the second metal circuit layer  201  and the solder resist  310  when the surface finish layer  400  is formed. Therefore, it is possible to prevent insulating property from deteriorating due to the plating solution permeating between the second metal circuit layer  201  and the solder resist  310 , thereby preventing a decrease in product reliability due to damage to the solder resist  310 . 
         [0046]    Hereinafter, a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. 
         [0047]      FIGS. 3 to 9  are cross-sectional views showing the manufacturing process of a printed circuit board according to an embodiment of the present invention. 
         [0048]    Initially, as shown in  FIG. 3 , a seed layer  110  may be formed on one surface of a first insulating layer  100 . 
         [0049]    The first insulating layer  100  may use Ajinomoto build up film (ABF) to easily implement microcircuits or use prepreg to manufacture a thin printed circuit board. The first insulating layer  100  may be formed of an epoxy resin or a modified epoxy resin, a bisphenol A resin, an epoxy-novolak resin, or an aramid-reinforced, glass fiber-reinforced or paper-reinforced epoxy resin. 
         [0050]    The seed layer  110  formed on one surface of the first insulating layer  100  serves as a lead-in line of a first metal circuit layer  200  to be described below, and is typically formed through an electroless copper plating process, sputtering or the like. 
         [0051]    Then, as shown in  FIG. 4 , a plating resist  120  having an opening  121 , in which the first metal circuit layer  200  is to be formed, may be formed on the seed layer  110 . 
         [0052]    The plating resist  120  is provided for selectively forming the first metal circuit layer  200  later to form the first metal circuit layer  200 . 
         [0053]    That is, the first metal circuit layer  200  is not formed on the portion covered by the plating resist  120  and is formed in the opening  121  only. 
         [0054]    In order to form the plating resist  120  having the opening  121 , an exposure process in which a photosensitive ink or a dry film is formed on one surface of the seed layer  110  and selectively curing it by illuminating light thereon through a mask which is patterned to correspond to the first metal circuit layer  200 , and a development process (photolithography process) in which uncured portions are removed may be performed. 
         [0055]    Then, as shown in  FIG. 5 , the first metal circuit layer  120  may be formed in the opening  121  of the plating resist  120 . 
         [0056]    Here, the first metal circuit layer  200  may be formed using the seed layer  110  as a lead-in line through an electroplating process and may be formed by filling the opening  121  of the plating resist  120 . Preferably, the first metal circuit layer  200  is lower than the plating resist  120  in order to form surface roughness  210  to be formed through etching. 
         [0057]    Subsequently, as shown in  FIG. 6 , leaving the plating resist  120  as it is, the surface roughness  210  may be formed on only one surface of the exposed portion of the first metal circuit layer  200 . 
         [0058]    The surface roughness  210  is formed by etching the exposed portion of the first metal circuit layer  200  through the opening  121  of the plating resist  120 , to have a bumpy surface. 
         [0059]    Preferably, the first metal circuit layer  200  may have a width of 1 to 5 μm, and the surface roughness  210  may have a dimension of 0.1 to 1 μm. If the width of the first metal circuit layer  200  is below 1 μm, the first metal circuit layer  200  may be lost during etching to thereby result in a defect. If the width of the first metal circuit layer  200  is above 5 μm, the loss of the metal circuit layer  200  due to an undercut is not made during etching. Therefore, the first metal circuit layer  200  has a width of preferably 1 to 5 μm. In accordance with the first metal circuit layer thus configured, the surface roughness  210  may have a dimension of preferably 0.1 to 1 μm, in order to prevent the loss of the first metal circuit layer  200  and to maximize adhesive strength between the first metal circuit layer  200  and a second insulating layer  300  to be described below. 
         [0060]    Subsequently, as shown in  FIG. 7 , the plating resist  120  may be removed. 
         [0061]    Thereafter, as shown in  FIG. 8 , the seed layer  110  may be removed leaving the portion on which the first metal circuit layer  200  is formed. 
         [0062]    The seed layer  110  covered by the plating resist  120  is exposed to the outside as a result of the previous removal of the plating resist  120 . By removing the portion of the seed layer  110  on which the first metal circuit layer  200  is not formed through wet etching such as flash etching, the first metal circuit layers  200  formed through the plating process are electrically separated from one another so as to function independently. 
         [0063]    Then, as shown in  FIG. 9 , a second insulating layer  300  and a second metal circuit layer  201  having surface roughness  211  on only one surface may be stacked on at least one surface of the first insulating layer  100  in this order. 
         [0064]    Since the surface roughness  210  is formed on only one surface of the first metal circuit layer  200  when the second insulating layer  300  is formed, adhesive strength between the first metal circuit layer  200  and the second insulating layer  300  may be ensured, such that a printed circuit board having micro metal circuit layers with strong adhesion therebetween may be manufactured. 
         [0065]    In addition, a seed layer  111  is formed on one surface of the second insulating layer  300  using a method such as sputtering or electroless plating, and the second metal circuit layer  201  having the surface roughness  211  on only one surface through the same process as the first metal circuit layer  200 . 
         [0066]    Then, a solder resist layer  310  may be formed such that a selected portion of the second metal circuit layer  201  is exposed. The solder resist  310  covers the remaining parts of the second metal circuit layer  201  so as to protect it from soldering or other external environment. 
         [0067]    Then, a surface finish layer  400  may be formed on the surface of the second metal circuit layer  201 . 
         [0068]    Here, a surface finish layer  400  may be formed on the surface of the exposed part of the second metal circuit layer  201 , on which the solder resist  310  is not formed, through plating such as an Electroless Nickel Immersion Gold (ENIG) method or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) method. 
         [0069]    Since the surface roughness  211  is formed on the surface of the second metal circuit layer  201 , it is possible to prevent a plating solution for forming the surface finish layer  400  from permeating between the second metal circuit layer  201  and the solder resist  310 . 
         [0070]    That is, it is possible to prevent insulating property from deteriorating due to the plating solution permeating between the second metal circuit layer  201  and the solder resist  310 , thereby preventing decrease in product reliability due to damage to the solder resist  310 . 
         [0071]    As set forth above, according to the embodiments of the present invention, by forming surface roughness on only one surface of a metal circuit layer, it is possible to prevent an undercut is made in the metal circuit layer, such that loss of the metal circuit layer can be minimized, electrical property can be ensured. Further, adhesive strength between the metal circuit layer and an insulating layer can be ensured such that a printed circuit board having micro metal circuit layers with strong adhesion therebetween can be manufactured. 
         [0072]    Further, it is possible to prevent a plating solution from permeating between a metal circuit layer and a solder resist while performing surface finish on the metal circuit layer. 
         [0073]    Although the exemplary embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art would appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. 
         [0074]    Accordingly, the scope of the present invention is not construed as being limited to the described embodiments but is defined by the appended claims as well as equivalents thereto.