Abstract:
A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a processing unit of a host device, is introduced. Entities are removed from a queue, which are associated with commands issued to a storage device, and the removed entities are processed until a condition is satisfied.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of China Patent Applications No. 201510411607.3, filed on Jul. 14, 2015, and No. 201510740155.3, filed on Nov. 4, 2015, the entirety of which is incorporated by reference herein. 
       BACKGROUND 
       [0002]    Technical Field 
         [0003]    The present invention relates to flash memory, and in particular to methods for reconfiguring a storage controller when control logic fails, and apparatuses using the same. 
         [0004]    Description of the Related Art 
         [0005]    A SEU (Single Event Upset) is one of the reasons causing logic error in a control unit of an SSD (Solid State Disk) storage system encapsulated in FPGA (Field-Programmable Gate Array). The SEU is a change of state caused by alpha-ions or electromagnetic radiation striking a sensitive node of a micro-electronic device. Accordingly, what is needed are methods for reconfiguring a storage controller when control logic fails, and apparatuses using the same. 
       BRIEF SUMMARY 
       [0006]    An embodiment of a method for reconfiguring a storage controller when control logic fails, performed by a processing unit of a host device, is introduced. An access of the storage controller is suspended when it is determined that the storage controller has failed. Reconfiguration control logic of a fixed region of the storage controller is directed to reprogram a whole reconfigurable region of the storage controller. After that, the access of the storage controller is resumed. 
         [0007]    An embodiment of an apparatus for reconfiguring a storage controller when control logic fails is introduced. The apparatus at least contains a fixed region and a reconfigurable region. The fixed region at least contains a processing unit and reconfiguration control logic. 
         [0008]    The processing unit directs the reconfiguration control logic of the fixed region of the storage controller to reprogram the whole reconfigurable region of the storage controller after determining that the storage controller has failed. 
         [0009]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The present invention can be fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0011]      FIG. 1  is the system architecture of an SSD (Solid State Disk) storage system according to an embodiment of the invention; 
           [0012]      FIG. 2  shows a schematic diagram depicting a storage unit of an SSD storage system according to an embodiment of the invention; 
           [0013]      FIG. 3  is a schematic diagram illustrating a logical partition of the storage controller according to an embodiment of the invention; 
           [0014]      FIG. 4  is a flowchart illustrating a method for reconfiguring a storage controller according to an embodiment of the invention; 
           [0015]      FIG. 5  is a flowchart illustrating a method for reconfiguring a storage controller according to an embodiment of the invention; 
           [0016]      FIG. 6  is a flowchart illustrating a method for reconfiguring a storage controller according to an embodiment of the invention; 
           [0017]      FIG. 7  is a flowchart illustrating a method for reconfiguring a storage controller according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0019]    The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0020]    Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements. 
         [0021]      FIG. 1  is the system architecture of an SSD (Solid State Disk) storage system according to an embodiment of the invention. The system architecture  10  of the SSD storage system contains a ROM (Read Only Memory) to store information regarding a reconfiguration of a storage controller. It should be noted that the information may also be duplicated in a storage unit  180 . When executing kernel algorithms of a SRAM (Static Random Access Memory)  130 , a processing unit  110  writes data into a designated address of the storage unit  180 , and reads data from a designated address thereof. Specifically, the processing unit  110  writes data into a designated address of the storage unit  10  through an access interface  170  and reads data from a designated address through the same interface  170  according to commands issued by a master device  160  via an access interface  150 . The system architecture  10  uses several electrical signals for coordinating commands and data transfer between the processing unit  110  and the storage unit  180 , including data lines, a clock signal and control lines. The data lines are employed to transfer commands, addresses and data to be written and read. The control lines are utilized to issue control signals, such as CE (Chip Enable), ALE (Address Latch Enable), CLE (Command Latch Enable), WE (Write Enable), etc. The access interface  170  may communicate with the storage unit  180  using a DDR (Double Data Rate) protocol, such as ONFI (open NAND flash interface), DDR toggle, etc. The processing unit  110  may communicate with the master device  160  through the access interface  150  using a standard protocol, such as USB (Universal Serial Bus), ATA (Advanced Technology Attachment), SATA (Serial ATA), PCI-E (Peripheral Component Interconnect Express) etc. The processing unit  110 , the ROM  120 , the SRAM  130  and the access interfaces  150  and  170  may be referred to collectively as a storage controller. 
         [0022]      FIG. 2  shows a schematic diagram depicting a storage unit of an SSD storage system according to an embodiment of the invention. The storage unit  180  includes an array  210  composed of M×N memory cells, and each memory cell may store at least one bit of information. The flash memory may be a NAND flash memory, etc. In order to appropriately access the desired information, a row-decoding unit  220  is used to select appropriate row lines for access. Similarly, a column-decoding unit  230  is employed to select an appropriate number of bytes within the row for output. An address unit  240  applies row information to the row-decoding unit  220  defining which of the N rows of the memory cell array  210  is to be selected for reading or writing. Similarly, the column-decoding unit  230  receives address information defining which one or ones of the M columns of the memory cell array  210  are to be selected. Rows may be referred to as wordlines by those skilled in the art, and columns may be referred to as bitlines. Data read from or to be applied to the memory cell array  210  is stored in a data buffer  250 . Memory cells may be SLCs (Single-Level Cells), MLCs (Multi-Level Cells) or TLCs (Triple-Level Cells). 
         [0023]      FIG. 3  is a schematic diagram illustrating a logical partition of the storage controller according to an embodiment of the invention. The storage controller may contain a reconfigurable region  300   a  and a fixed region  300   b.  The fixed region  300   b  may contain I/O control logic, master-device communications logic, reconfiguration control logic  310 , and so on. The fixed region  300   b  may further contain an ALU (Arithmetic Logic Unit) of the processing unit  110  for performing mathematics operations and controlling other devices according to the loaded firmware. For example, the I/O control logic controls I/O devices, such as the ROM  120 , the SRAM  130 , and so on. The master-device communications logic may be implemented in the access interface  150 . Logics of the fixed region  330   b  cannot be reconfigured. The reconfigurable region  300   a  is implemented by a FPGA (Field-Programmable Gate Array). The reconfigurable region  300   a  contains kernel algorithms of the SSD storage system and its occupied space may exceed 90%. The reconfigurable region  300   a  contains an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together, for example, many logic gates that can be inter-wired in different configurations. Some logic blocks may be configured to perform complex combinational functions, or merely simple logic gates, such as AND, OR, XOR, etc. Some logic blocks may include memory elements, which may be simple flip-flops or complete blocks of memory. The kernel algorithms of the reconfigurable region  300   a  and the logics of the fixed region  300   b  may be organized into code segments and each code segment is protected by CRC (Cyclic Redundancy Check) code being added therewith. A decoder may use the CRC codes to determine whether the kernel algorithms and the logics have errors and attempt to correct the errors if happened. However, when the kernel algorithms and the logics cannot be recovered (also referred to as control logic fails), it is needed to perform methods for reconfiguring the storage controller. The control logic failure may also indicate that the storage controller has failed. 
         [0024]    In an implementation, the storage controller may inspect which part or parts of the reconfigurable region  300   a  have irrecoverable errors, and then reconfigure the erroneous part or parts only. In order to perform the inspection, additional hardware and/or software instructions need to be implemented. Alternatively, more time is needed to perform the inspection. However, it may be too late to complete the reconfiguration and the processing for a command issued by the master device  160  before the command expires. In another implementation, the storage controller reconfigures the whole reconfigurable region  300   a  without the aforementioned inspection.  FIG. 4  is a flowchart illustrating a method for reconfiguring a storage controller according to an embodiment of the invention. Those skilled in the art will realize that, after receiving commands from the master device  160 , such as data read commands, data write commands, etc., the storage controller employs the kernel algorithms to direct the access interface  170  to complete the received commands. Before the kernel algorithms are employed, the decoder may inspect whether the kernel algorithms and logics are correct. When failing to correct the errors of the kernel algorithms and logics of the storage controller, the decoder issues an interrupt having the highest priority to the processing unit  110 . After receiving the interrupt (step S 410 ), the processing unit  110  suspends an access (step S 420 ). In other words, the processing unit  110  does not employ the kernel algorithms having the irrecoverable errors to direct the access interface  170 . Next, the current execution statuses (such as variables in execution, data yet to be programmed into the storage unit  180 , data which has been read but not been replied to the master device  160 , etc.) are stored in the DRAM  140  (step S 430 ). Specifically, in step S 430 , the processing unit  110  directs the I/O control logic to store the current execution statuses in the DRAM  140 . The processing unit  110  directs the reconfiguration control logic  310  to start a reconfiguration operation for reprogramming the whole reconfigurable region  300   a  (step S 440 ). Specifically, the reconfiguration control logic  310  directs the I/O control logic to read the information in the ROM  120 , such as instructions in HDL (Hardware Description Language), a mapping table describing interconnects among logic blocks, etc., and reprograms the whole reconfigurable region  300   a  according to the information. Next, a loop is repeatedly performed to query whether the reconfiguration operation performed by the reconfiguration control logic  310  has been completed (step S 450 ). After the reconfiguration control logic  310  replies with the completion of the reconfiguration operation to the processing unit  110  (the “Yes” path of step S 450 ), the processing unit  110  performs a re-initiation operation for starting the whole storage controller, thereby enabling the storage controller to be available (step S 460 ). Next, the processing unit  110  restores the execution statuses from the DRAM  140  (step S 470 ) and resumes the access according to the restored execution statuses (step S 480 ). Through the aforementioned method, the unfinished operation can be continued from the point of interruption. The storage controller malfunctions in a short time (shorter than 1 second) and goes back to normal after the reconfiguration operation. 
         [0025]      FIG. 5  is a flowchart illustrating a method for reconfiguring a storage controller according to an embodiment of the invention. After suspending an access (step S 420 ), the processing unit  110  completes the current operations of the pipeline (step S 510 ). After completing the current operations of the pipeline (step S 510 ), the processing unit  110  directs the reconfiguration control logic  310  to start a reconfiguration operation for reprogramming the whole reconfigurable region  300   a  (step S 440 ). Next, after performing a re-initiation operation for starting the whole storage controller, thereby enabling the storage controller to be available (step S 460 ), the processing unit  110  resumes the access (step S 520 ). For details of steps  5410 , S 420 , S 440 , S 450  and S 460 , refer to the descriptions of  FIG. 4 , which are omitted here for brevity. 
         [0026]    As to determining whether the storage controller has errors, please refer to the flowcharts illustrated in  FIGS. 4 and 5 . Some embodiments inspect the SEU (resulting in storage controller fails) via the mechanism of an interrupt handler. Upon receiving an interrupt, the processing unit  110  performs the reconfiguration. In some embodiments, the processing unit  110  periodically polls the decoder if a SEU occurs. Once the decoder replies with indication of an occurrence of the SEU, the processing unit  110  performs the reconfiguration. 
         [0027]      FIG. 6  is a flowchart illustrating a method for reconfiguring a storage controller according to an embodiment of the invention. The flowchart of  FIG. 6  is similar to  FIG. 4 . However, those skilled in the art may revise step S 410  of  FIG. 4  for receiving the interrupt while periodically polling the decoder about whether the storage controller has failed (step S 610 ). When the decoder replies that the storage controller has failed to the processing unit  110  (the “Yes” path of step S 610 ), the processing unit  110  suspends an access (step S 420 ). Refer to the descriptions of  FIG. 4  for details about the following steps, which are omitted here for brevity. 
         [0028]      FIG. 7  is a flowchart illustrating a method for reconfiguring a storage controller according to an embodiment of the invention. The flowchart of  FIG. 7  is similar to  FIG. 5 . However, those skilled in the art may revise step S 410  of  FIG. 5  for receiving the interrupt while periodically polling the decoder about whether the storage controller has failed (step S 610 ). When the decoder replies that the storage controller has failed to the processing unit  110  (the “Yes” path of step S 610 ), the processing unit  110  suspends an access (step S 420 ). The following steps may refer to the descriptions of  FIG. 5  and are omitted for brevity. 
         [0029]    Although the embodiment has been described as having specific elements in  FIGS. 1 and 3 , it should be noted that additional elements may be included to achieve better performance without departing from the spirit of the invention. While the process flow described in  FIGS. 4 to 6  each includes a number of operations that appear to occur in a specific order, it should be apparent that these processes can include more or fewer operations, which can be executed serially or in parallel (e.g., using parallel processors or a multi-threading environment). 
         [0030]    While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.