Abstract:
An analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that concerns voltage and current variables and is related to input to and output from the analog node; convert the variable information into time functions; and compute the time functions upon each occurrence of a given event and execute simulation of the analog node.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of International Application PCT/JP2011/062981, filed on Jun. 6, 2011 and designating the U.S., the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     The embodiment discussed herein is related to an analog circuit simulator and analog circuit verification method that verify analog circuit function. 
     BACKGROUND 
     In conventional analog circuit function verification, an analog circuit simulator, such as one with Simulation Program with Integrated Circuit Emphasis (SPICE, registered trademark) is used. Although such analog circuit simulators can calculate analog properties with high accuracy, an enormous amount of memory is used for the computation. Further, since the number of calculation steps is great and each step is detailed, verification using a typical operation model consumes at least several tens of thousands times more time for the verification of large-scale circuits and therefore, such analog circuit simulators cannot be used. As a result, verification using an operation model describing the analog circuit in hardware description language is commonly performed. 
     For example, concerning matrix constant formularization of circuit partitioning for circuit simulation where a circuit is partitioned into blocks, the partitioned circuit is compiled, current variables of an element that is independent of current variables between nodes outside a block are excluded from internal variables of the block, and simulation is performed (for example, refer to Japanese Laid-Open Patent Publication No. H6-124317). According to another technique, to simulate by numeric computation, the transient state of the waveform of a signal in a circuit having both an analog circuit and digital circuit, the analog circuit is partitioned into circuit blocks and modeled (for example, refer to Japanese Laid-Open Patent Publication No. 2010-92434). 
     Nonetheless, in the verification of analog circuit function, the analog circuit has to be replaced with an operation model that is of a high level of abstraction and described in hardware description language, and then simulated. However, a problem arises with approaches using hardware description language used for large-scale verification. The directions of signals are clearly defined by input and output definitions and consequently, interactions with elements outside the model, the function of circuits having impedance, and the like cannot be expressed by hardware description language. 
     For example, in the case of a circuit configuration having a given impedance and in which the input of a grounded resistor is connected to the output of an operational amplifier, if the downstream circuit connected to the output of the operational amplifier is not determined, the voltage/current of the output and input nodes cannot be defined. Thus, analog circuit simulators have been used for verifying circuits having impedance, and a tremendous amount of time is consumed. 
     SUMMARY 
     According to an aspect of an embodiment, an analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that concerns voltage and current variables and is related to input to and output from the analog node; convert the variable information into time functions; and compute the time functions upon each occurrence of a given event and execute simulation of the analog node. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram of an analog circuit simulator according to an embodiment; 
         FIG. 2  is a flowchart of a process operation of the analog circuit simulator according to the embodiment; 
         FIG. 3  is a diagram depicting an example of an analog model; 
         FIG. 4  is a timing chart depicting operation of the simulator; 
         FIG. 5A  is a circuit diagram of an example of formularization of a model; 
         FIG. 5B  is a diagram describing formularization of an upper layer in  FIG. 5A ; 
         FIG. 5C  is a diagram depicting the waveform of current in  FIG. 5B ; 
         FIG. 6  of is a circuit diagram of another example of formularization of a model; 
         FIG. 7A  is a circuit diagram of yet another example of formularization of a model; 
         FIG. 7B  is a diagram describing formularization of an upper layer in  FIG. 7A ; 
         FIG. 7C  is a diagram depicting the waveform of current in  FIG. 7B ; 
         FIG. 8  is a diagram of yet another example of formularization of a model; 
         FIG. 9  is a timing chart depicting discrete modeling of an analog circuit. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Embodiments will be described in detail with reference to the accompanying drawings.  FIG. 1  is a block diagram of an analog circuit simulator according to an embodiment. An analog circuit simulator  100  includes a CPU  101 , and memory  102 ,  103 . The CPU  101  executes a program (not depicted) that is for analog circuit verification and stored in memory (not depicted) such as ROM and thereby, the CPU  101  causes the device to operate as an analog circuit simulator. 
     The first memory  102  in the figure stores design data  104  and variable-function correspondence information  105  of a circuit under design. The design data  104  is formed by the digital circuit model and the analog circuit model included in the circuit. 
     The CPU  101 , consequent to the execution of a program, has functions including reading out the design data  104 , modeling the circuit, and performing simulation. Description will be given according to function. A searching unit  1  ( 111 ) reads out the design data  104  such as a netlist, searches for the analog circuit at the highest layer of the circuit under verification, further searches for an analog node that connects analog ports (the output of an upstream analog circuit and the input of a downstream analog circuit), and stores to memory  1  ( 121 ), an extracted analog node. 
     A searching unit  2  ( 112 ) sequentially searches for analog nodes stored to the memory  1  ( 121 ), searches for model names correlated with the respective analog nodes, and stores the obtained model names into the memory  2  ( 122 ). 
     A variable information collecting unit  113  collects from a variable information group that corresponds to preliminarily prepared models, variable information that corresponds to the model names stored in the memory  2  ( 122 ) and stores the collected variable information into memory  3  ( 123 ). The variable information is formed from voltage variables and current variables that correspond to the model names and that are preliminarily defined. The variable information collecting unit  113  stores to the memory  3  ( 123 ), the variable information (voltage variable and current variable) that corresponds to the model names. 
     A function converting unit  114  reads out from the memory  3  ( 123 ), the variable information (voltage variable and current variable) correlated with the model names, and based on the variables, performs conversion to a pre-defined time function. Since circuit configuration is determined from the voltage variable and current variable information of the model, the function converting unit  114  determines the time function of the voltage and the current corresponding to the model. The function converting unit  114  converts the voltage and the current of the analog node into a time function and stores the resulting function into the memory  4  ( 124 ). A process for conversion to a function is not absolutely necessary and configuration may be such that functions corresponding to plural models are prepared in advance and from which a function for a model is selected. 
     A model processing unit  115  reads out from the memory  4  ( 124 ), current and voltage functions, and to obtain the values of the current and of the voltage of the model when a given event occurs, the model processing unit  115  extracts from among the functions obtained by the function converting unit  114 , only values at the time when the event occurred. The time when the given event occurs refers to, for example, an output of the current value and the voltage value of the model to the simulation executing unit  116  when an event occurs at the next stage of the model during a simulation performed by a simulation executing unit  116 . For example, coinciding with the cycle operation of the analog circuit operation of the model, the model processing unit  115  extracts only functions of the voltage value and the current value at the start of the cycle operation of a downstream FF circuit. The corrected model is stored to the memory ( 125 ). 
     The simulation executing unit  116  executes simulation for functional verification of an analog circuit, and using the corrected model stored in memory ( 125 ), performs computations based on functions of the values of the voltage and of the current only at the time when an event occurs. For example, the simulation executing unit  116  can use a model described in a hardware description language such as general-purpose Verilog to perform simulation. However, the simulation executing unit  116  performs analysis only when an event occurs and does not perform continuous analysis of transient states in the analog circuit. As result, for an analog circuit, event driven voltage and current analysis that considers impedance (voltage and current) while being temporally discrete is performed as well as fast functional verification. 
       FIG. 2  is a flowchart of a process operation of the analog circuit simulator according to the embodiment. The process depicted in  FIG. 2  describes a preprocess that is performed prior to the execution of the simulation at the simulation executing unit  116 . The searching unit  1  ( 111 ) reads the design data  104  from the memory  102 , searches for an analog circuit at the highest layer of the circuit under verification, and further searches for an analog node that connects analog ports (upstream output and downstream input) (step S 201 ). Each extracted analog node is stored to the memory  1  ( 121 ). 
     The searching unit  2  ( 112 ) sequentially searches for analog nodes stored in the memory  1  ( 121 ), and searches for model names correlated with the respective analog nodes (step S 202 ). The searching unit  2  ( 112 ) stores the obtained model names into the memory  2  ( 122 ). 
     The variable information collecting unit  113  collects variable information that corresponds to the model names stored in the memory  2  ( 122 ) (step S 203 ). The variable information collecting unit  113  stores the collected variable information into the memory  3  ( 123 ). 
     The function converting unit  114  reads out from the memory  3  ( 123 ), variable information (voltage variable and current variable) correlated with the model names, and performs conversion to a pre-defined time function (step S 204 ). Thus, the voltage and current of the converted analog node are converted into time functions and the resulting functions are stored to the memory  4  ( 124 ), thereby ending the pre-process. 
     After the pre-process, execution of the simulation at the simulation executing unit  116  is performed. The model processing unit  115  reads out from the memory  4  ( 124 ), the current and voltage functions, and each time a given event occurs, the function converting unit  114  from among the obtained functions, outputs to the simulation executing unit  116 , a value at the time when the event occurred. Thus, the simulation executing unit  116  suffices to have a general-purpose simulator function, and is able to execute computations based on functions of the values of the voltage and of the current at the time when an event occurs and output a computation result. 
     As described, according to the present embodiment, the analog circuit simulator is implemented by an association of an analog circuit model and a simulator.
     1-1. In the analog circuit model, a voltage variable and current variable are provided to the analog ports of each analog circuit.   1-2. At the highest layer of the circuit under verification, an analog node that connects analog ports is searched for.   1-3. From voltage variable and current variable relations of all models connected to the analog nodes, voltage and current of the analog node are converted into time functions.   2. At the simulator, when an event occurs, necessary analog values (voltage value, current value) are calculated by a function and a verification result is obtained.   

     Details of the processes of the above units will be described. First the analog model will be described.  FIG. 3  is a diagram depicting an example of the analog model. A model  300  depicted in the figured is an example where the analog port_input of a model  2  ( 302 ) having a grounded resistor  302   a  is connected to the analog port_output of a model  1  ( 301 ) that includes a power source  301   a  and an operational amplifier  301   b . In the model  300 , R 2  is input impedance, and R 1  is output impedance. The searching unit  1  ( 111 ) to the variable information collecting unit ( 113 ) search for and obtain voltage variable V 1 −(I 1 ×R 1 ) and a current variable I 1  for the output port of the model  1 . Further, concerning the input port of the model  2 , the voltage variable I 2 ×R 2  and a current variable I 2  are obtained. 
       FIG. 4  is a timing chart depicting operation of the simulator. As depicted by the model  300  in  FIG. 3 , a case where variation of the voltage and of the current remains within 1 cycle, when simulation is executed by the simulation executing unit  116  will be described as an example. Transient voltage variation V(t) at this time is expressed by the following function.
 
 V ( t )= V 1+( V 2 −V 1)[½+( ft−tk )−½)×(−1) k ]
 
     Consequent to input to the model  300 , the output with respect to reference voltage V 1 , the voltage transiently increases up to V 2  according to an RC property function. Here, coinciding with every 1-cycle, which corresponds to the rising edge of a clock input to a downstream FF, the simulation executing unit  116  suffices to calculate the values of the above functions only at times t0, t1, t2, t3, . . . regarded as the time of the occurrence of an event. Thus, the simulation executing unit  116  does not calculate transient properties entirely, but rather according to the processed models stored in the memory ( 125 ) and performs the function computation f(t) only at the time of a designated event t0, t1, t2, t3, . . . , whereby the calculation by the simulation executing unit  116  can be performed easily and with a low load. 
     Another example of an application with respect to the model will be described. When simulation is executed and variation of the voltage and of the current (function values) occurs over plural cycles, affecting other cycles, the following function is used. 1. A case when the effect continues infinitely is expressed by the equation below. (−1) corresponds to waveform inversion. 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       n 
                     
                     ⁡ 
                     
                       ( 
                       t 
                       ) 
                     
                   
                   = 
                   
                     
                       V 
                       1 
                     
                     + 
                     
                       
                         ( 
                         
                           
                             V 
                             2 
                           
                           - 
                           
                             V 
                             1 
                           
                         
                         ) 
                       
                       ⁢ 
                       
                         
                           ∑ 
                           
                             k 
                             = 
                             0 
                           
                           n 
                         
                         ⁢ 
                         
                           
                             f 
                             ⁡ 
                             
                               ( 
                               
                                 t 
                                 - 
                                 
                                   t 
                                   k 
                                 
                               
                               ) 
                             
                           
                           * 
                           
                             
                               ( 
                               
                                 - 
                                 1 
                               
                               ) 
                             
                             k 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     A case where the effect continues for 3 cycles is calculated by
 
 Vn ( t )= V 1+( V 2 −V 1)(−1) n ( f ( t−t   n )− f ( t−t   n-1 )+ f ( t−t   n-2 ))
 
In this manner, addition of the function corresponding in number to the number of cycles that are affected suffices.
 
       FIG. 5A  is a circuit diagram of an example of formularization of a model. A model  500  depicted in the figure is an example where the analog port_input of a model  2  ( 502 ) having a grounded capacitor  502   a  is connected to the analog port_output of a model  1  ( 501 ) that includes a power source  501   a  and an operational amplifier  501   b . In this example, the model  500  is configured by output impedance R 1  and total capacitance C 2 . The searching unit  1  ( 111 ) to the variable information collecting unit ( 113 ) search for and obtain the voltage variable V 1 −I 1 ×R 1  and the current variable I 1  for the output port of the model  1 . Further, concerning the input port of the model  2 , the voltage variable I 2 /jωC 2  and the current variable I 2  are searched for and obtained. The function converting unit  114  performs conversion into a function for an upper layer. 
       FIG. 5B  is a diagram describing formularization of the upper layer in  FIG. 5A .  FIG. 5C  is a diagram depicting the waveform of the current in  FIG. 5B . As depicted in  FIG. 5B , in the function expressed by the upper layer, the power source  501   a  is connected to the resistor R 1  via a switch  510  and the grounded capacitor C 2  becomes connected. The voltage V 1  of the model  500  may be expressed as: 
     
       
         
           
             
               
                 
                   
                     V 
                     1 
                   
                   = 
                   
                     
                       
                         R 
                         1 
                       
                       ⁢ 
                       i 
                     
                     + 
                     
                       
                         1 
                         
                           C 
                           2 
                         
                       
                       ⁢ 
                       
                         ∫ 
                         
                           i 
                           ⁢ 
                           
                             ⅆ 
                             t 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Where, the following are obtained by deriving both terms:
 
 R   1 ( di/dt )+1/ C   2   ·i= 0
 
1/ i ·( di/dt )=−1/ C   2   R   1  
 
The following are obtained by integrating both terms:
 
1 n|i|=−t/C   2   R   1   +A  ( A : constant of integration)
 
 i=e   A   ·e   −(t/C2R1)  
 
     
       
         
           
             
               
                 
                   i 
                   = 
                   
                     
                       
                         V 
                         1 
                       
                       
                         R 
                         1 
                       
                     
                     · 
                     
                       ⅇ 
                       
                         - 
                         
                           t 
                           
                             
                               C 
                               2 
                             
                             ⁢ 
                             
                               R 
                               1 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     from V=V 1 −Ri, 
     
       
         
           
             
               
                 
                   V 
                   = 
                   
                     
                       V 
                       1 
                     
                     ( 
                     
                       1 
                       - 
                       
                         ⅇ 
                         
                           - 
                           
                             t 
                             
                               
                                 C 
                                 2 
                               
                               ⁢ 
                               
                                 R 
                                 1 
                               
                             
                           
                         
                       
                     
                     ) 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     is obtained. The function converting unit  114  respectively converts the voltage V and the current i into time functions. When simulation is executed by the simulation executing unit  116 , at the time when an event at the next stage occurs (refer to  FIG. 4 ), values obtained by an application of the above functions are output as output of the model and the simulation executing unit  116  is caused to execute the simulation. The switch  510  depicted in  FIG. 5B  is operated to open/close at each occurrence of an event, whereby the waveform of the output of the model in  FIG. 4  is obtained. 
       FIG. 6  of is a circuit diagram of another example of formularization of a model. A model  600  depicted in the figure is an example where as the analog port_input of the model  2  ( 602 A- 602 N), parallel N capacitors  602   a  are connected to the analog port_output of the model  1  ( 601 ) that includes a power source  601   a  and an operational amplifier  601   b . Thus, in a case of parallel connection, the model  2  suffices to be formularized by the sum C of the capacitance of the capacitors  602   a . In other words, capacitance C=C 2 ×N. Thus, the function converting unit  114  converts the voltage V and the current i into the time functions below. 
     
       
         
           
             
               
                 
                   V 
                   = 
                   
                     
                       V 
                       1 
                     
                     ( 
                     
                       1 
                       - 
                       
                         ⅇ 
                         
                           - 
                           
                             t 
                             
                               CR 
                               1 
                             
                           
                         
                       
                     
                     ) 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   i 
                   = 
                   
                     
                       
                         V 
                         1 
                       
                       
                         R 
                         1 
                       
                     
                     · 
                     
                       ⅇ 
                       
                         - 
                         
                           t 
                           
                             CR 
                             1 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
       FIG. 7A  is a circuit diagram of yet another example of formularization of a model. A model  700  depicted in the figure is an example where the analog port_input of the model  2  ( 702 ) having a grounded voltage divider resistor  702   a  is connected to the analog port_output of the model  1  ( 701 ) that includes a power source  701   a  and an operational amplifier  701   b . The searching unit  1  ( 111 ) to the variable information collecting unit ( 113 ) search for and obtain the voltage variable V 1 −I 1 ×R 1  and the current variable I 1  for the output port of the model  1 . Further, the voltage variable I 2 ×R 2  and the current variable I 2  are searched for and obtained for the input port of the model  2 . The function converting unit  114  performs conversion into a function for an upper layer. 
       FIG. 7B  is a diagram describing formularization of the upper layer in  FIG. 7A .  FIG. 7C  is a diagram depicting the waveform of the current in  FIG. 7B . The model  700  depicted in  FIG. 7B  is expressed as:
 
voltage  V =( R 2 ·V 1)/( R 1 +R 2)
 
current  i=V 1/( R 1 +R 2)
 
The function converting unit  114  uses the above current i and voltage V as functions. As depicted in  FIG. 7C , the model  700  becomes a value where the current and the voltage are a time-independent DC value (a value not dependent on time).
 
       FIG. 8  is a diagram of yet another example of formularization of a model. A model  800  depicted in the figure is an example where the analog port_input of the model  2  ( 802 ) of an operational amplifier  802   a  to which no load is input, is connected to the analog port_output of the model  1  ( 801 ) that includes a power source  801   a  and an operational amplifier  801   b . Thus, for models where a node is not affected by impedance or in cases where the calculation of impedance is unnecessary, such as with the model  800 , formularization is applicable. In this manner, when impedance computation is unnecessary, the output of the model can be used as is. 
     In the case of the configuration in  FIG. 8 , the searching unit  1  ( 111 ) to the variable information collecting unit ( 113 ) suffice to search for and obtain the voltage variable V=V 1  and the current variable i=V 1 /R 1  for the output port of the model  1 . The function converting unit  114  may use, as a function for the upper layer, the voltage and the current of the output port of the model  1  as is. 
       FIG. 9  is a timing chart depicting discrete modeling of an analog circuit. As described above, temporal discrete modeling is performed for an analog circuit having impedance, by the configuration of the searching unit  1  ( 111 ) to the model processing unit  115 . Thus, since the simulation executing unit  116  suffices to perform computations only at the occurrence of an event, the time consumed for verification is significantly reduced. With conventional simulation (e.g., Verilog-A), verification is performed with respect to voltage variations expressed on the vertical axis and continuously for time expressed on the horizontal axis depicted in  FIG. 7 . On the contrary, for the output of the model upstream, in the embodiment above, by discrete modeling of the analog circuit, calculation of values (as output) obtained by an application of the obtained functions suffices to be performed only when an event occurs such as at the operation timing of a downstream circuit (FF) (at each point depicted in the figure). Thus, the time consumed for verification may be significantly reduced. 
     According to the disclosed technique, an analog circuit is modeled, and for a circuit that has impedance when input/output ports are connected, variables of the current and of the voltage are collected, and at an upper layer, the current and the voltage are converted into functions that vary temporally. Thus, functions of an analog circuit that has impedance may be easily and quickly verified. Further, by performing simulation computations when an event occurs, the time consumed for verification may be significantly reduced. Thus, functions of large-scale mixed signal designs that include not only digital circuits but also analog circuits may be verified. Further, functions of an analog circuit may be verified by a general-purpose simulation computation technique. 
     The analog circuit simulator and analog circuit verification method enable simple and fast functional verification of analog circuits having impedance. 
     All examples and conditional language provided herein are intended for pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.