Abstract:
A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Description:
This application is a continuation of U.S. Ser. No. 08/865,342, filed May 29, 1997, now U.S. Pat. No. 5,877,656, which is a continuation of U.S. Ser. No. 08/549,915, filed Oct. 30, 1995, now U.S. Pat. No. 5,684,434. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to clock generators generally, and more particularly to a phase-locked-loop frequency synthesizer having post production configuration capabilities contained on an EPROM. 
     BACKGROUND OF THE INVENTION 
     It is well. known to construct a clock generator that has a fixed frequency which is determined during the silicon wafer fabrication of the clock generator. The frequency of the clock generator is determined by using a specific pattern during the manufacturing process involved in the wafer production of the clock generator. An important competitive advantage can be obtained by providing a clock generator that can be configured late in the manufacturing process, preferably after wafer fabrication. Phase-locked-loop (PLL) based clock generators typically use read only memory (ROM) tables to store frequency selection and configuration information. This information can be altered by using a device specific mask during wafer fabrication. A disadvantage with this technique is that once the device has been fabricated, the device can no longer be reconfigured. 
     Another technique used to obtain late configuration for PLL-based clock generators is accomplished by implementing a number of electrically programmable fuses made of aluminum, polysilicon or some other type of material that is appropriate for fuse fabrication. These fuses could then be programmed after production of the clock generator. The fuse technique provides somewhat of a competitive advantage by reducing the number of parts required to be, stored in inventory at any given time. The late programming of the fuses also reduces the time necessary to produce the clock generator. However, this technique suffers from the disadvantage of having limited configuration information that can be stored. As a result, the implementation of new frequency clock generators would require mask programming during fabrication to realize the new frequencies. Some prior art devices do implement more than one frequency table on a single ROM, but are limited to the specific pre-defined frequencies available in the ROM mask. Furthermore, it is not possible to test the fuses without blowing them, which permanently alters the device. 
     Another technique which could be used to obtain late configurations for clock generators is accomplished by using laser configurable parts which can be programmed using a polysilicon or aluminum link similar to the fuse technique. Also similar to the fuse technique example would be the disadvantage of storing only a limited amount of configuration information. It does not appear that the prior art has proposed a solution to the problem of providing a clock generator that is programmable late in the manufacturing cycle, can store enough configuration information to be commercially practical and can be manufactured at an acceptable cost. 
     SUMMARY OF THE INVENTION 
     The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming functionality can be verified. All of these features are accomplished without the use of programming fuses. 
     Objects, features and advantages of the present invention are to provide a clock generator that uses an on-chip EPROM in a monolithic clock generator chip, can be adapted to various PLL-based clock generators, can be electrically configured, can be erased prior to packaging, reduces cycle time from customer requests to prototypes, and can be field programmed if desired. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description, the appended claims and the accompanying drawings in which: 
     FIG. 1 is a block diagram representing the overall architecture of the clock generator in accordance with a presently preferred embodiment of the invention; 
     FIG. 2 is a block. diagram of the clock generator incorporating the architecture described in FIG. 1; and 
     FIG. 3B is a diagram illustrating a single-poly EPROM cell in comparison to a conventional EPROM cell in FIG.  3 A. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a block diagram of the frequency generator  10  is shown in accordance with a presently preferred embodiment of the invention. The frequency generator  10  generally comprises a frequency generation block  12 , an output block  14 , a frequency control block  16  and a configuration control block  18 . The frequency generator  10  receives a first input  19  from an external power source (not shown) and receives a second input  21  from a ground. The frequency generation block  12  receives a first input  20  and a second input  22  from an external crystal (not shown). The external crystal produces a fixed frequency signal at the first and second inputs  20  and  22 . A reference crystal oscillator  28  has a first input  24  and a second input  26  that receive the signal from the first and second inputs  20  and  22 . The frequency generation block  12  generally comprises a reference crystal oscillator  28 , a quotient counter  30 , a product counter  32  and a phase-locked-loop (PLL)  34 . The reference crystal oscillator  28  provides a reference signal Fref that is received by the quotient counter  30  through an input line  31 . The quotient counter  30  also receives an input from a bus line  36 . The bus line  36  receives information from the frequency control block  16 . Thus, the bus line  36  may be an extension of the bus line  40 . The quotient counter  30  provides an output that is presented to the PLL  34  through output line  38 . The product counter  32  receives an input Fvco that is received from the PLL  34 . The product counter  32  also receives an input from a bus line  40  that is coupled to the frequency control block  16 . The product counter  32  provides an output  42  that is coupled to the PLL  34 . The quotient counter  30  and the product counter  32  use signals received through the bus line  40  from the frequency control block  16  to provide frequencies at outputs  38  and  42  that are presented to the PLL  34 . This allows the output of the PLL  34  to respond to the signals presented on the bus line  40 . The flexible nature of the quotient counter  30  and the product counter  32  provide programmable outputs  38  and  42  to the PLL  34 . The reference signal Fref and the input Fvco are waveforms of a particular frequency. Conversely, the bus line  36  and the bus line  40  present distinct logic signals. 
     The phase-locked-loop  34  comprises a phase detector  44 , a charge pump  46 , a loop filter  48  and a voltage controlled oscillator  50 . The phase detector  44  has an input R that receives a signal from output  38  of the quotient counter  30 . Similarly, the phase detector  44  has an input V that receives a signal from the output  42  of the product counter  32 . The phase detector  44  has a first output Up and a second output Dn. The charge pump  46  has a first input Up that receives the output Up from the phase detector  44 . The charge pump has a second input Dn that receives an input from the Dn output of the phase detector  44 . The charge pump  44  also has an input  52  that receives frequency configuration information from the frequency control block  16  through the bus line  40 . The charge pump  46  sends an output signal on output line  54  that is received by the loop filter  48 . Additionally, the loop filter  48  receives control information from the frequency control block  16  through the bus line  40 . The loop filter  48  provides a signal on output line  56  that is received by the voltage controlled oscillator  50 . The voltage controlled oscillator  50  provides a signal on line  58  that is received by the output block  14  and is also used in a feedback path  59  to provide the input Fvco to the product counter  32 . The voltage controlled oscillator  50  also receives control information from the frequency control bus  40 . 
     The phase detector  44 , the charge pump  46 , the loop filter  48  and the voltage controlled oscillator  50  are internal components of the PLL  34  and are used to control the frequency of the output  58 . When operating in the closed loop or locked condition, the phase and frequency of the V and R inputs of the phase detector  44  may be equal. When these conditions are met, the output frequency  58  of the phase locked loop  34  is equal to Fref  31  divided by the quotient counter  30  multiplied by the product counter. 
     The output block  14  generally comprises an output multiplexer  60 , an output divider  62  and a buffer  64 . The output multiplexer  60  receives a first input signal  66  from the reference crystal oscillator  28  and a second input signal  68  from the feedback path  59 . The output multiplexer  60  also receives a control input  70  from a bus line  72  that is connected to the configuration block  18 . The output divider  62  receives an input  74  from the PLL  34  that represents the voltage controlled oscillator frequency Fvco. The output divider  62  also receives an input  76  from the bus line  72 . The buffer  64  receives an input  78  from the outputs divider  62  and also receives a control input  80  from the bus line  72 . The buffer  64  has an output Fout that represents a fixed frequency output of the frequency generator  10 . 
     The function of the output block  14  is to receive the voltage controlled oscillator frequency Fvco from the PLL  34  and to manipulate the frequency Fvco in response to configuration information received from the configuration block  18 . The output divider  62  can manipulate the voltage controlled oscillator frequency Fvco to a certain extent by dividing the frequency Fvco by certain predetermined constants. The outputs block  14  may respond to certain control information provided by the configuration block  18  which, once configured, may never change. For example, the output divider  62  can be set to divide the voltage controlled oscillator frequency Fvco by one of a predetermined set of constants. However, once this set of constants is established, it rarely changes. The output multiplexer  60  chooses between an input from the reference crystal oscillator  28  or an input Fvco from the PLL  34  and presents an output signal to the output divider  62 . It should be appreciated that the information stored in the configuration block  18  could be combined with the information stored in the frequency control block  16 . 
     The frequency control block  16  generally comprises a first buffer  82 , a second buffer  84  and a frequency EPROM table  86 . The first buffer  82  receives a first frequency select signal  88  from an external source. The second buffer  84  receives a second frequency select signal  90  from the same external source. Although FIG. 1 shows only two external frequency select signals  88  and  90 , more than two frequency select signals can be used if greater flexability is desired for a particular design application. The number of frequency select signals  88  and  90  directly reflects the number of output frequencies available. Specifically, the number of output frequencies equals two to the I power, where I equals the number of frequencies select signals. In the case of two signals, two to the second power would equal four output frequencies available. Buffers  82  and  84  also receive a signal from the bus  72  which may adjust the input threshold of the buffers. 
     The configuration block  18  is comprised of an EPROM that controls various system configuration parameters that do not normally change once they are programmed. Such parameters include output multiplexer control, output divider control, output drive control and input threshold level. The configuration block  18  may be separated from the frequency control block  16  in an effort to save and optimize chip real estate. The configuration block  18  may not have any external inputs to vary the configuration once it is configured. Since these parameters are normally not altered after the initial configuration is established, this limitation is of little consequence. However, if a certain design criteria required the configuration block  18  to be externally controllable, external inputs could be provided at the expense of cost and chip size. Conversely, the frequency control block  16  contains configuration parameters that may be desirable to change after production of the clock generator  10 . Frequency selection during normal operation is provided by external frequency select signals  88  and  90 . The dividing of the configuration information between the frequency control block  16  and the configuration block  18  is only necessary to maximize efficiency and to provide a balance between cost and performance. 
     The clock generator  10  generally functions by receiving the first and second frequency select signals  88  and  90 . These signals are used by the frequency EPROM table  86  to send information to the PLL  34 . The PLL  34  sends the voltage controlled oscillator frequency Fvco to the output block  14 . The output block  14  presents the output Fout by choosing, through the multiplexer  60 , either the frequency Fvco or the first input signal  66 . 
     Referring to FIG. 2, a block diagram of a clock generator  100  having multiple phase-lock-loops  34  is shown. The clock generator  100  generally comprises an input section  101 , a clock section  102 , an output section  104 , an output multiplexer and divider block  106  and an EPROM section  108 . The input section  101  generally comprises various reference signals necessary to implement the clock generator  100 . A pin  110  represents an input signal Xtal In, which is a 32 Khz reference signal. Similarly, a pin  112  represents an output signal Xtal Out, which is also a 32 Khz output signal. When a 32 Khz crystal is placed across the pin  110  and the pin  112 , a 32 Khz signal is produced by block  140  from the resulting oscillator. A pin  114  represents an input signal Xtal In. A pin  116  represents an input signal Xtal Out. A pin  118  represents a battery signal Vbatt which powers a 32 Khz crystal oscillator. A pin  120  represents a power in signal Vdd (I/O) which powers the output pads. A pin  122  represents a signal Avdd which powers the chip core. A pin  124  represents a ground signal Gnd. A pin  126  represents a first input select signal S 2 . A pin  128  represents a second input select S 1 . A pin  130  represents a third input select signal S 0 . A pin  132  represents a signal Outdis which is used to enable and disable the clock generator  100  output signals. The input select signals S 0 , S 1  and S 2  are externally generated input signals that select a frequency at which the clock generator  100  will operate. 
     The clock section  102  generally comprises a 32 Khz crystal oscillator  140 , a reference crystal oscillator  142 , a system clock PLL  144 , a utility PLL  146  and a CPU PLL  148 . The reference crystal oscillator  142  provides a general circuit timing for the entire clock generator  100 . The crystal oscillator  140  receives an input from the block  110  and presents an output  150  to the output section  104 . The reference crystal oscillator  142  presents the reference signal to the output section  104  through an output line  152 . The system clock PLL  144  receives an input from the reference crystal oscillator  142  through the output line  152 . The system clock PLL  144  also receives signals from the configuration bus  198  through a signal bus  155 . The system clock PLL  144  has an output  154  that is presented to the output multiplexer and divider block  106 . The utility PLL  146  receives an input from the reference crystal oscillator  142  through the output line  152 . The utility PLL  146  also receives a set of signals from the configuration EPROM bus  198  through a signal bus  157 . The utility PLL  146  presents an output  156  to the output multiplexer and divider block  106 . The CPU PLL  148  receives an input from the output  152  of the reference crystal oscillator  142 . The CPU PLL  148  presents an output  158  to the output multiplexer and divider block  106 . The CPU PLL  148  also receives configuration information from the EPROM section  108  on a bus line  159  and a bus line  161 . 
     The output section  104  generally comprises a 32 Khz buffer output  160 , a reference buffer output  162 , a system clock output  164 , a CPU clock output  166 , a clock A output signal  168 , a clock B output signal  170 , a clock C output signal  172  and a clock D output signal  174 . The 32 Khz buffer  160  receives an input through the output line  150  from the 32 Khz crystal oscillator  140 . The reference buffer  162  receives an input from the reference crystal oscillator  142  through the output line  152 . The system clock output  164  receives a signal  154  from the PLL  144  via the bus line  163 . The system clock output  164  divides the output  154  from the system clock PLL  144  by a fixed predetermined value. The CPU clock output  166  also receives an input signal  158  from the PLL  148  via the bus line  163 . The clock A signal  168  receives an input from an output  176  of the multiplexer and divider block  106 . Similarly, the clock B signal  170  receives an input from an output  178  of the multiplexer and divider block  106 . The clock C signal  172  receives an input from an output  180  from the output multiplexer and divider block  106 . The clock D signal  174  receives an input from an output  182  of the multiplexer and divider block  106 . The multiplexer and divider block  106  allows the clock A signal  168 , the clock B signal  170 , the clock C signal  172  and the clock D signal  174  to each be generated from either the system clock PLL  144 , the utility PLL  146  or the CPU PLL  148 . Prior to producing the output signals  168 - 174 , the multiplexer and divider block  106  provides a  2  to the N divider function on each of the signals  168 - 174  where N is a variable controlled by the EPROM section  108 . 
     Each of the output signals  162 - 174  has a switch  184  connected in series with the respective inputs. The switch  184  is controlled by a signal  133  which is controlled by the outdis pin  132 . This allows,all outputs of the chip to be disabled for system test purposes. 
     The EPROM section  108  generally comprises a frequency EPROM  190  and configuration EPROM  192 . The frequency EPROM  90  is similar to the frequency EPROM  86  of FIG.  1 . The configuration EPROM  192  is similar to the configuration control block  18  of FIG.  1 . The frequency EPROM  190  receives an input  194  from the bus  185 . These signals are used for frequency selection during normal operation and for programming control during EPROM programming. The configuration EPROM  192  receives an input  196  from the bus  185  and has an output bus  198 . Configuration information for the system clock PLL  144 , utility PLL  146  and a portion of the CPU PLL  148  are distributed on the configuration signal bus  198 . The EPROM section  108  uses the terminology “EPROM” to generally describe any non-volatile technology. The present invention applies to all non-volatile floating gate technologies, specifically EEPROM and Flash memory. RAM storage where the contents of the RAM are maintained for an extended period (more than 1 year) by an external battery source would also be within the scope contemplated by the present invention as well as any method of memory that is erasable and electrically programmable. 
     The clock generator  100  shown in FIG. 2 generally functions by receiving the select signals  126 ,  128  and  130  to provide information to the EPROM section  108 . The EPROM section  108  then initializes the clock section  102  to produce various specific frequencies from the PLLs  144 ,  146  and  148 . The output section manipulates these frequencies to present multiple outputs from block  104 . 
     Referring to FIG. 3A, a conventional EPROM cell  200  is shown as compared to a single-poly EPROM cell  202 . The conventional EPROM cell  200  generally comprises a source  204 , a drain  206 , a floating gate  208  and a select gate  210 . The floating gate  208  is positioned between the source and drain  204  and  206  and the select gate  210 . 
     Referring to FIG. 3B, a single-poly EPROM cell  202  generally comprises a source  220 , a drain  222 , a floating gate  224 , a tap/diffusion capacitor  226  and an N-Well select line  228 . The tap/diffusion capacitor  226  couples with the floating gate  224 . The single-poly EPROM cell  202  is also known as a planar EPROM. The single-poly EPROM cell  202  is less expensive to manufacture than the conventional EPROM cell  200  because far fewer manufacturing steps are involved due to the elimination of one layer of polysilicon. The disadvantage of the single-poly EPROM cell  202  is that it requires more silicon area to implement. 
     The implementation of the clock generator  10  requires only a few hundred bits of storage capacity, so the small additional cost caused by the area penalty imposed by the use of a single-poly EPROM cell  200  is preferable to the cost of the manufacturing steps required to implement a conventional stacked gate EPROM. The single-poly EPROM cell  202  requires high voltage circuits to be programmed. The single-poly EPROM is also slower than a stacked gate EPROM. However, this is not an important design criteria for the implementation of the clock generator  10 . The single-poly EPROM cell  202  allows a reduced manufacturing process complexity, as well as a reduced cost which are both necessities in the highly competitive clock generator market. Therefore, the advantages of using a single-poly EPROM cell  202  outweigh the sacrifice in speed and chip space. 
     Another advantage or the clock generator  10  is the ability to implement field programming. This allows customers or distributors to stock inventory of clock generators  10  in an unprogrammed state. The unprogrammed clock generators  10  can then be configured by the end user as desired for a particular design. This reduces inventory costs for the end user as well as allows the end user to quickly configure prototype devices to meet their particular design criteria. 
     It is to be understood that modifications to the invention might occur to one with skill in the field of the invention within the scope of the appended claims.