Abstract:
A chip package including a shielding layer conformally covering the underlying molding compound for is provided. The shielding layer can smoothly cover the molding compound and over the rounded or blunted, top edges of the molding compound, which provides better electromagnetic interferences shielding and better shielding performance.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device, and more particularly to a chip package. 
     2. Description of Related Art 
     Electro-magnetic interference (EMI) is a serious and challenging problem for most electronic devices or systems. As EMI disturbances commonly interrupt, degrade or limit the effective performance of the electronic device or the whole circuit of the electronic system, it is necessary for the electronic devices or systems to have efficient EMI protection to ensure the effective and safe operation. 
     EMI protection is particularly important in small-sized, densely packaged or sensitive electronic applications operating at high frequencies. Conventionally, EMI shielding solutions typically involve the use of metal plates and/or conductive gaskets, which are later attached or affixed at higher manufacturing costs. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing, the present invention provides a manufacturing method of a chip package, which offers better design flexibility with less effort. 
     The present invention is further directed to a chip package with enhanced effectiveness of EMI shielding. 
     The present invention provides a chip package including a substrate, at least a chip disposed on the substrate, a molding compound and a shielding layer conformally covering the molding compound. The top edges of the molding compound are blunt or rounded. The shielding layer conformally covers the top edges of the molding compound and a top surface and sidewalls of the molding compound, and the shielding layer is electrically connected to the semiconductor substrate. 
     The invention further provides a manufacturing method of a chip package. At least a chip is disposed on one of the substrate units of the matrix substrate, and the chip is electrically connected to the substrate unit. After forming a molding compound over the matrix substrate to encapsulate the chips, portions of the substrate units, a grinding process and a singulation process are performed to the molding compound. Later, a shielding layer is formed over the molding compound to conformally cover the molding compound of each chip packages. 
     According to one embodiment of the present invention, the grinding process can be performed before or after the singulation process. Also a half-cutting process may be further performed before or after the grinding process. The grinding process may comprise an oblique disc grinding process or a rounding grinding process. 
     According to one embodiment of the present invention, the shielding layer and the connectors are formed from a conductive material by a spraying process, a sputtering process or a plating process. 
     According to the embodiments of the present invention, the grinding process makes the top edges of the molding compound blunt or rounded, so that the later formed shielding layer can smoothly covers the top edges or corners of the molding compound of individual chip packages, without the crevices. 
     Herein, the crevices often occurring at the orthogonal corners or edges of the shielding layer can be avoided, and the shielding layer can uniformly cover the molding compound of the chip package and provide effective EMI shield of the chip package. According to the present invention, owing to the complete coverage of the shielding layer, the reliability of the package and the shielding efficacy can be improved. 
     In order to the make the aforementioned and other objects, features and advantages of the present invention comprehensible, several embodiments accompanied with figures are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A through 1G  are schematic views showing a manufacturing method of the chip package according to one preferred embodiment of the present invention. 
         FIGS. 2A  though  2 C are schematic views showing certain steps of the manufacturing method of the chip package according to another preferred embodiment of the present invention. 
         FIG. 3  is a cross-sectional view of a chip package according to an embodiment of the present invention. 
         FIG. 4  is a cross-sectional view of a chip package according to another embodiment of the present invention. 
         FIG. 5  is a cross-sectional view of a chip package according to another embodiment of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     The manufacturing methods as described in the present invention can be used for fabricating various package structures and are more suitable for fabricating stacked type packages, multiple-chip packages, or high frequency device packages (including radio frequency device packages). 
       FIGS. 1A through 1G  are schematic views showing a manufacturing method of the chip package according to the preferred embodiment of the present invention. FIG.  1 D′ and  1 D″ are exemplary three-dimensional schematic views showing the structure of  FIG. 1D  having grinding trenches of enlarged view A or B. 
     Referring to  FIG. 1A , a matrix substrate  100  having a plurality of substrate  102  (defined by the subsequent sawing lines shown as dotted lines) is provided, while each substrate  102  includes a plurality of contacts  104  thereon and at least a ground via  108  therein. The contacts  104  function as bump pads for flip chip connecting technology. The substrate  100  can be a laminate substrate, for example, a printed circuit board (PCB). Currently achievable designs of the ground via  108  within the substrate  102  are considered encompassed within the present invention. For a laminate substrate, the ground via may extend through the whole substrate (i.e. from the top surface to the bottom surface), or extend from the top or bottom surface to an inner layer thereof, or extend between two inner layers of the substrate. The size of the ground via may be adjusted according to electrical properties of the product, the ground via/plug may be formed from the plated through-hole, or slot hole filled with solder materials. Further, the ground via can be replaced by a ground pad with a conductive solder mass disposed on the upper surface of the substrate. 
     Referring to  FIG. 1B , at least a chip  120  is disposed on the top surface  102   a  of each substrate  102 . Although a chip is provided herein, other surface mount components can be employed, and encompassed within the scope of this invention. The chip  120  is electrically connected to the contacts  104  of the substrate  102  through a plurality of bumps  106  there-between. Although flip chip connecting technology is described herein, it is well encompassed within the scope of this invention to employ wire bonding technology (i.e. through wire connections). The chip  120  preferably is disposed within a central portion of the substrate  102 . 
     Referring to  FIG. 1C , a molding process is carried out to form a molding compound  130  on the matrix substrate  100  to encapsulate the chips  120 , the contacts  104 , the bumps  106  and at least a portion of the substrate  102 . The molding process can be an over-molding process, for example. The material of the molding compound  130  may be epoxy resins or silicon resins, for example. 
     Referring to  FIG. 1D , a grinding process is performed to form a plurality of grinding streaks (grinding trenches)  135  by removing portions of the molding compound  130 . The grinding streaks  135  are arranged surrounding the location of the chip  120 . Preferably, the grinding streaks  135  within the molding compound  130  are arranged right above the boundary or perimeter of each substrate  102 . FIGS.  1 D′ or  1 D″ is the 3D schematic view of the structure depicted in  FIG. 1D  having the grinding trenches of the enlarged view A or B. As shown in FIGS.  1 D and  1 D′, the individual grinding streaks  135  are arranged right on the boundary lines (the dotted lines) of the substrate  102 . In this case, the subsequent sawing process will cut through the grinding streaks  135  arranged at the sawing lines (shown as dotted lines). The grinding process may include an oblique disc grinding process, for example. For the oblique disc grinding process, grinding disc with slanted blade cuts into the molding compound to form sloping trenches. Taking the grinding streaks  135  arranged right above the boundary of each substrate  102  as an example, the grinding process may cause a ring-shaped trench within the molding compound  130 , along the boundary of each substrate  102 . 
     In details, as shown in  FIGS. 1D ,  1 D′ &amp;  1 D″, the grinding streak  135  is preferably a loop trench having a reverse-hat cross-section (i.e. the trench being narrower at the bottom portion but wider around the top portion). In other words, the grinding process makes the top edges  130   e  of the molding compound  130  non-orthogonal or non-right-angular. Preferably, the grinding process makes the top edges  130   e  of the molding compound  130  blunted. The top edges  130   e  of the molding compound  130  either have one obtuse angle θ 1  (as shown in the enlarged view A), or two obtuse angles θ 2 , θ 3  (as shown in the enlarged view B). For example, the obtuse angle θ 1  (between the beveled surface  135   a  of the grinding streak  135  and the top surface  130   a  of the molding compound  130 ) ranges between about 95-165 degrees, while the obtuse angle θ 2  (between the beveled surface  135   a  and the beveled surface  135   b  of the grinding streak  135 ) or the obtuse angle θ 3  (between the beveled surface  135   b  of the grinding streak  135  and the top surface  130   a  of the molding compound  130 ) ranges between about 100-160 degrees, for the grinding streaks  135 . Preferably, the grinding depth d ranges approximately from ⅕ to ⅓ of the thickness D of the molding compound  130 . In general, the sizes or the depth of the grinding streaks  135  can be altered depending on the shielding requisites or other electrical properties of the package or even varied in accordance with the processing parameters. 
     Referring to  FIG. 1E , an optional half-cutting process is performed to remove portions of the molding compound  130 , until the top surface  102   a  of the substrate  102  is partially exposed. In general, the half-cutting process cuts through the grinding streaks  135  arranged on the sawing lines and cuts through the molding compound  130  into the matrix substrate  100  for a pre-determined depth, to form a plurality of trenches  137 . Preferably, the cutting width a of the half-cutting process (i.e. the width a of the trenches  137 ) is smaller than the width A of the grinding streak  135  (i.e. the grinding width A of the grinding process). In this case, even after the half-cutting process, the blunted edges  130   e  of the molding compound  130  are retained. The location or arrangement of the ground via can be varied according to product requirements. One exemplary location of the ground via is positioned right on the sawing lines, and the half-cutting process or the singulation process may cut through the ground via. In  FIG. 1E , the half-cutting process cuts into the ground via  108  arranged on the sawing lines. Although the half-cutting process is performed after the grinding process according to the present embodiment, it is acceptable to perform the half-cutting process prior to the grinding process. When the half-cutting process is performed prior to the grinding process, the subsequent grinding process can still blunt the top edges of the half-cut molding compound. 
     Finally, referring to  FIG. 1F , a shielding layer  140  is formed over the molding compound  130  to conformally cover the top surface  130   a , the sidewalls  130   b  and the top edges  130   e  of the molding compound  130 . The shielding layer  140  can be formed by depositing a metal material (not shown) to conformally cover the molding compound  130  and the matrix substrate  100  exposed by the trenches  137  using a spray coating method, a plating method, or a sputtering method, for example. The metal material can be, for example, aluminum, copper, chromium, gold, silver, nickel, solder materials, or the combinations thereof. 
     In principle, the top edges of the molding compound are neither acute-angled nor right-angled, which is prone to poor coating quality (e.g., formation of crevices). Because the top edges  130   e  of the molding compound  130  according to the present invention are either obtuse or rounded, either the coverage or the conformity of the shielding layer  140  is greatly improved. As much less or no crevices exist in the shielding layer, owing to the uniform coverage of the shielding layer at the corners or edges, the shielding efficacy of the shielding layer is enhanced and the reliability of the package is improved. 
     Referring to  FIG. 1G , from a bottom surface  102   b  of the matrix substrate  100 , a singulation process is performed to cut at the sawing lines and cut through the matrix substrate  100 , so as obtain the individual chip packages  10 . The singulation process may be a blade sawing process or a laser cutting process, for example. 
     In accordance with the present invention, the manufacturing methods of the chip package shown in  FIGS. 1A through 1G  may be further modified and described in the following embodiments. Alternatively, following the process steps of  FIGS. 1A-1C , as shown in  FIG. 2A , a singulation process is performed to cut through the molding compound  130  and the matrix substrate  100  along the sawing lines, so as obtain the individual chip packages  10 . The singulation process also cuts through the ground via  108  within the matrix substrate  100 . The singulation process may be a blade sawing process or a laser cutting process, for example. The boundary regions between the top surface  130   a  and the sidewalls  130   b  of the molding compound  130  are denoted as the top edges  130   e  of the molding compound  130  herein. As shown in  FIG. 2A , the top edges  130   e  of the molding compound  130  are substantially right-angled after singulation. 
     Later, referring to  FIG. 2B , a grinding process is performed to blunt the top edges  130   e  of the molding compound  130  of the singulated packages  10 . As the singulation process cuts through the sawing lines, the grinding process is performed toward the top edges  130   e  of the molding compound  130  right above the boundary or perimeter of each substrate  102 . As described herein, the top edges  130   e  are substantially right-angled before grinding, and the grinding process turns the top edges  130   e  of the molding compound  130  to blunt or rounded top edges  130   e . The grinding process may include an oblique disc grinding process or a rounding grinding process, for example. As shown in  FIG. 2B , the top edges  130   e  of the molding compound  130  become rounded after the grinding process. However, according to the embodiments of this invention, the top edges  130   e  of the molding compound  130  can be either blunted (i.e. having at least one obtuse angle as shown in the enlarged views A-B of  FIG. 1D ), or rounded (i.e. having curved profiles as shown in the enlarged view at the top of  FIG. 2B ). Also, the angle or curvature of the blunted or rounded top edges can be varied according to the processing parameters. 
     Following  FIG. 2B , as shown in  FIG. 2C , a shielding layer  140  is conformally formed over the molding compound  130  to cover the top surface  130   a , the sidewalls  130   b  and the rounded top edges  130   e  of the molding compound  130 . The shielding layer  140  can be formed by depositing a metal material (not shown) to cover the molding compound  130  and sidewalls of the singulated substrate  102  using a spray coating method, a plating method, or a sputtering method, for example. 
     In other words, since the shielding layer  140  conformally covers the obtuse or rounded top edges  130   e  of the molding compound  130 , as shown in the enlarged partial view at the top of  FIG. 2C , the resultant shielding layer  140  also has obtuse or rounded top edges  140   e  (i.e. smooth profiles right above the top edges  130   e  of the molding compound  130 ). 
       FIG. 3  is a cross-sectional view of a chip package according to a preferred embodiment of the present invention. Referring to  FIG. 3 , the chip package  30  of the present embodiment includes a substrate  102 , a plurality of contacts  104 , a plurality of bumps  106 , at least a chip  120 , a molding compound  130  and a shielding layer  140 . The substrate  102  can be a laminated substrate, for example, a two-layered or a four-layered laminated PCB substrate. The chip  120  can be a semiconductor chip, for example, a radio-frequency (RF) chip. The material of the shielding layer  140  may be copper, chromium, gold, silver, nickel, aluminum or alloys thereof or even a solder material, for example. The chip  120  is electrically connected to the substrate  102  through the contacts (bump pads)  104  and the bumps  106 . The molding compound  130  encapsulates portions of the substrates  102 , the bumps  106 , and the chip  120 . As shown in  FIG. 3 , the shielding layer  140  is disposed over the molding compound  130 , covering the top surface  130   a , the sidewalls  130   b  and the blunted top edges  130   e  of the molding compound  130 . The boundary regions between the top surface  130   a  and the sidewalls  130   b  of the molding compound  130  are denoted as the top edges  130   e  of the molding compound  130  herein, and the detailed profile of the blunted top edges  130   e  of the molding compound  130  is similar to the enlarged view B of  FIG. 1D . As the half-cutting process cut through the molding compound  130  along the sawing lines before the formation of the shielding layer  140 , the molding compound  130  are fully covered by the shielding layer and will not be exposed from the chip package  30 . The shielding layer  140  is electrically connected to the substrate  102  through the direct contact with at least a ground vias  108  of the substrate  102 , and the shielding layer  140  is electrically grounded through the ground via  108 . Hence, taking advantage of the metal traces or vias of the substrate, the shielding layer of the present invention can be grounded within the package structure using the ground plane of the substrate. The shielding layer can establish an electrical ground path within the package structure, devoid of using an extra ground plane. 
       FIG. 4  is a cross-sectional view of a chip package according to another preferred embodiment of the present invention. Referring to  FIG. 4 , the chip package  40  is mostly similar to the package structure of  FIG. 3 , except the rounded top edges  130   e  of the molding compound  130 . The detailed profile of the rounded top edges  130   e  of the molding compound  130  is similar to the enlarged view of  FIG. 2B . As the singulation process cut through the molding compound  130  and the matrix substrate along the sawing lines before the formation of the shielding layer  140 , the sidewalls of the substrate  102  and the molding compound  130  are fully covered by the shielding layer and will not be exposed from the chip package  40 . The shielding layer  140  is electrically connected to the substrate  102  through the direct contact with at least a ground plug/solder-filled slot hole  108  of the substrate  102 , and the shielding layer  140  is electrically grounded through the ground plug/solder-filled slot hole  108 . 
       FIG. 5  is a cross-sectional view of a chip package according to another preferred embodiment of the present invention. Referring to  FIG. 5 , the chip package  50  is mostly similar to the package structure of  FIG. 4 . However, the detailed profile of the rounded top edges  130   e  of the molding compound  130  is similar to the enlarged view A of  FIG. 1D . The sidewalls of the substrate  102  and the molding compound  130  are fully covered by the shielding layer and will not be exposed from the chip package  50 . The shielding layer  140  is electrically connected to the substrate  102  through the direct contact with at least a ground plane  109  of the substrate  102 , and is electrically grounded through the ground plane  109 . 
     In brief, due to the rounding or blunting effect of the grinding process, the top edges and top corners of the molding compound become blunted (having an obtuse angle) or rounded, and the subsequently formed shielding layer can satisfactorily covers the molding compound without crevice. In the chip package structures of the present embodiment, the shielding layer disposed over the molding compound and the substrate function as an EMI shield, protecting the package from the EMI radiation from the surrounding radiation sources. In this case, the uniform coverage of the shielding layer over the molding compound, especially around the top edges and the corners, can effectively enhance the EMI shielding efficacy of the packages. In addition, the reliability of the package can be improved. As the top edges and top corners of the package structures become blunted or rounded, the leakage occurring at the corners can also be alleviated, thus boosting the electrical performances of the package structures. Accordingly, such design is compatible with the packaging of high frequency devices, particularly, radio frequency devices. 
     Although the present invention has been disclosed above by the embodiments, they are not intended to limit the present invention. Anyone skilled in the art can make some modifications and alteration without departing from the spirit and scope of the present invention. Therefore, the protecting range of the present invention falls in the appended claims.