Abstract:
A method, apparatus, article of manufacture, and system, the method including, in some embodiments, providing a differential clock ganging structure to receive complementary differential clock signals, the differential clock ganging structure outputting clock ganging output signals, providing a source termination structure for each of the clock ganging output signals, and providing an inductance and capacitance compensation structure to receive an output of the source termination structure and to connect to a terminal interconnect for at least one of the clock ganging output signals.

Description:
BACKGROUND 
   A reliability and stability of a device, system, platform, or operating environment may depend on the device, system, platform, or operating environment operating within design specifications. A number of devices, systems, platforms, and operating environments use reference voltages. Clock skew tolerances and input edge rates are becoming increasingly smaller as systems become more complex and faster. 
   A number of attempts have been proposed to compensate for reference differential clock skew. In particular, pin-to-pin output skew and/or driver induced skew have been addressed by shortening propagation delay differences between clock input-to-output paths inside of a circuit and IC package. However, such approaches are limited in effectiveness and potential gains by, for example, the need to modify the circuits and IC packages. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is an exemplary depiction of a system apparatus, in accordance with some embodiments herein; 
       FIG. 2  is an exemplary depiction of a system, in accordance with some embodiments herein; 
       FIG. 3  is an exemplary flow diagram of a process, in accordance with some embodiments herein; 
       FIG. 4  is an exemplary graph; 
       FIG. 5  is an exemplary graph, in accordance with some embodiments herein; and 
       FIG. 6  is an exemplary graph, according to some embodiments herein. 
   

   DETAILED DESCRIPTION 
   The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations. 
     FIG. 1  is an exemplary depiction of a system  100  including an apparatus, in accordance with some embodiments herein. System  100  may include more, fewer, and alternate components and devices than those shown in  FIG. 1 . A clock driver device  105  provides complementary differential clock signals, as indicated by the (+) and (−) notations on the outputs of the clock driver device. Clock driver device  105  may be, for example, a host clock for a system bus and a reference clock for high speed differential links. The output voltages of clock driver device may vary. 
   The complimentary differential clock signals output by clock driver device  105  are received and conditioned by a differential clock ganging device  110 . Differential clock ganging device  110  operates to reduce a pin-to-pin differential skew that may exist between the received differential clock signals. Like signals of the differential clock outputs are routed to a common junction point. For example, the input legs of the similar differential clock outputs (e.g., (+) CLKP) through inductors  112  and  120  are both routed to gang point  111  and input legs of the similar differential clock outputs (e.g., (−) CLKN) through inductors  116 , and  124  are both routed to gang point  121 . Output legs of clock ganging structure  110  originate at the gang points  111  and  121 . The output legs or clock signal traces after gang points  111  and  121  are the same and are symmetrical in length. By having the same and symmetrical length, the output legs of clock ganging structure  110  may operationally reduce the pin-to-pin skew between the received differential clock signals. For example, a reference clock&#39;s pin-to-pin skew may be reduced to voltage ripples on the respective V high  and V low  signals of a clock driver device. 
   Source termination structures  125 ,  135 ,  145 , and  155  are provided for the outputs of ganging structure  110  for each of the clock ganging output signals. Each of the source termination structures  125 ,  135 ,  145 , and  155  includes a series resistance (e.g.,  128 ,  138 ,  148 , and  158 ) and a shunt resistance (e.g.,  134 ,  146 ,  154 , and  164 ). Also included are inductance components  130 / 132 ,  140 / 142 ,  150 / 152 , and  160 / 162  for each of source termination structures  125 ,  135 ,  145 , and  155 , respectively. Source termination structures  125 ,  135 ,  145 , and  155  operate to provide capacitance isolation and reflected noise reduction for various types of differential clocks, including, for example, high speed transceiver logic and high speed current control steering logic. 
   As shown in  FIG. 1 , a inductance and capacitance (LC) structure is provided at a terminal interconnect for one pair of the clock ganging output signals. In the example of  FIG. 1 , LC structure  168  includes inductor elements  170 ,  174  and capacitor elements  172 ,  176 . 
   Also illustrated in  FIG. 1  is an exemplary component connected to a differential pair of the clock ganging output signals. In the particular example of  FIG. 1 , a socket  180  having received a CPU  182  is shown connected to a differential pair of the clock ganging output signals. 
   LC structure  168  operates to reduce a differential skew that may exist between components supplied by the clock ganging output signals such as, for example, chipset  178  and CPU  182 . The differential skew at the terminal interconnects to components, for example chipset  178  and CPU  182 , may effectively compensate an edge rate and differential skew due to mismatched interconnect characteristics and a capacitive difference the clock paths connecting the components. 
     FIG. 2  is an exemplary depiction of a system  200  including an apparatus, in accordance with some embodiments herein. System  200  is similar in many respects to system  100 . Therefore, a detailed discussion of the components of  FIG. 2  repeated from  FIG. 1  is not seen as necessary since a full understanding of such may be had by referring to  FIG. 1 . 
   Regarding  FIG. 2 , two LC compensation structures are included in contrast to  FIG. 1 . Compensation structure  284  is provided at a terminal interconnect for CPU  282  and compensation structure  268  is provided at a terminal interconnect to chipset  278 . LC compensation structure  284  may be provided to compensate for a skew induced by a capacitance contributed by a socket  280 . 
   In some embodiments, clock routing and compensation techniques of  FIGS. 1 and 2  comprising a differential clock ganging structure, source termination, and LC compensation structure(s) may combine to effectively reduce output clock pin-to-pin skew, interconnect skew between components (e.g., a CPU and a chipset), and capacitive induced skew. 
   In some embodiments, the differential clock ganging structures herein are placed near a clock source and the source termination and LC compensation structures are located near interconnect components to effectively provide skew reduction. 
   Clock ganging structure  110  may provide a printed circuit board (PCB) methodology for reducing pin-to-pin skew of differential clock signals. In this manner, clock ganging structure  110  may be used to reduce pin-to-pin skew of differential clock signals without a need for or modification of input-to-output paths of integrated circuits (IC) and packages. 
   It should be appreciated that although only two complimentary differential clock signals are shown in  FIGS. 1 and 2 , more pairs of differential circuits may be compensated using the systems and methods disclosed herein. 
     FIG. 3  is an exemplary flow diagram of a process  300 , in accordance with some embodiments herein. At operation  305 , a differential clock ganging structure is provided at complementary differential outputs of a differential clock device. The differential clock ganging structure provides clock ganging output signals. The differential clock ganging structure operates to reduce a pin-to-pin skew between outputs of the differential clock device. 
   At operation  310 , a source termination structure is provided for each of the clock ganging output signals of the clock ganging structure. The source termination structures operate to provide capacitance isolation and reflected noise reduction for the clock ganging output signals. 
   At operation  315 , an LC compensation structure is provided at a terminal interconnect for at least one of the clock ganging output signals. In this manner, an interconnect skew induced by a mismatch between components connected to the system and apparatuses herein may be reduced. 
     FIG. 4  is an exemplary graph  400 . Graph  400  provides an illustrative example of two differential clock signals output by a clock driver device at component interconnects. The skew between the differential clock signals is evidenced by the mismatch between graphed voltage  405  and graphed voltage  410 . 
     FIG. 5  is an exemplary graph  500 . Graph  500  provides an illustrative example of two differential clock signals at component interconnects that have been conditioned by a differential clock ganging structure such, in accordance with the disclosures herein. Compared to voltage graphs  405  and  410 , there is a reduction in the difference between voltage graphs  505  and  510 . 
     FIG. 6  is an exemplary graph  600 . Graph  600  provides an illustrative example of two differential clock signals at component interconnects that have been conditioned by a differential clock ganging structure and LC compensation structures, in accordance with the disclosures herein. Compared to voltage graphs  405 ,  410  and  505 ,  510  there is a significant reduction in the difference between voltage graphs  605  and  610 . The reduction is such that voltage graphs  605  and  610  substantially coincide with each other. That is, the skew between the differential clocks signals is effectively reduced or eliminated. 
   It should be appreciated that the drawings herein are illustrative of various aspects of the embodiments herein, not exhaustive of the present disclosure.