Abstract:
A method and device program a dual edge programmable delay unit, that responds to an input signal with a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and fall times of the output signal. Programmable control sources (PCS) provide separate control inputs to a buffer. The FTPCS charges a capacitor in the buffer when the input signal changes from high to low to adjust time delay before the fall of the buffer output signal. The RTPCS discharges the capacitor in the buffer when the input signal changes from low to high to adjust time delay before the rise of the buffer output signal.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to programmable delay units and more particularly to providing a dual edge programmable delay unit.  
         [0003]     2. Description of Related Art  
         [0004]     U.S. Pat. No. 5,933,039 of Hui et al (Hui &#39;039) for “Programmable Delay Line” is related to a voltage comparator-RS register based delay line. The signal chain is long, with a minimum delay as long as 5 nanoseconds (ns). Thus the delay line of Hui &#39;039 cannot be used in a high-speed circuit. The rising edge and the falling edge have the same delay time, so it cannot be used as an on-chip timing adjusting unit. The current source is amplifier-resistor based, and the setting time is quite long depending on the resistance selected and the parasitic capacitance. The delay line operation of Hui &#39;039 is “reset signal” based; and no program code protection function is provided, so it cannot be used in a real time and an on-chip operation. Therefore the delay line units of the Hui et al is related to a different application field and different circuit structure from those of present invention.  
         [0005]     U.S. Pat. No. 5,355,038 of Hui et al (Hui &#39;038) for “Architecture for Programmable Delay Line Integrated Circuit” is similar to Hui &#39;039 in terms of the concepts and the system structure, but the circuit implementation is somewhat different. The delay line is based on a voltage-comparator and an RS register. The minimum delay line is long, 10 ns, so it cannot work in high speed circuits. The rising edge and the falling edge cannot have separate delay settings, so it cannot be used as a on-chip timing adjustment unit. With an amplifier-resistor based current source, the setting time is quite long, depending on the resistance selected and the parasitic capacitance. The delay line operation of Hui &#39;038 is “reset signal” based and there is no program code protection function, so it cannot be used in a real time and on-chip operation. Therefore, the delay line units of Hui &#39;038 are related to a different application field and a different circuit structure from the present invention.  
         [0006]     U.S. Pat. No. 5,936,451 of Phillips entitled “Delay Circuit and Method” describes a delay line related to very low speed applications such as power motors, solenoids, which is an entirely different field from that of present invention. The main purposes of the Phillips patent are to avoid turning on the NFET and the PFET at the same time when they are staked between power supply and ground. The goal of the Phillips patent is to obtain long delays without requiring a large capacitor or a large resistor, which is a completely different purpose and goal from those of present invention. The delay circuit of the Phillips patent has no capability to set different delay times for rising edge and falling edge independently. Therefore the concept, the purpose and the function of the delay circuit in the patent are different from those of present invention.  
         [0007]     U.S. Pat. No. 6,124,745 of Hilton entitled “Delay and Interpolation Timing Structures and Methods” describes a delay circuit based on a differential amplifier with two capacitors. The circuit structure and operation principle are completely different from those of present invention. The delay circuit of the Hilton patent has no capability to set different delay times of the rising edge and the falling edge separately. Therefore the circuit structure, operation principle and the function of the delay line in the Hilton patent are different from those of present invention.  
         [0008]      FIG. 1  shows a schematic circuit diagram of a conventional prior art programmable delay unit  10  of a type that is used widely in industry currently. The delay unit consists of “n” inverter-based delay elements IP 1 , IP 2 , . . . , IPn in series, a series connected set of “n” transmission gates TG 1 , TG 2 , . . . , TGn- 1 , TGn and an “n” bit latch  27 . Inverter-based delay element IP 1 , that includes series connected inverters  14  and  16 , receives an input signal IN on input line  12  and provides a delayed output which is connected via node  17  to the source/drain circuit of transmission gate TG 1 , as well as the input of inverter  18 . Inverter-based delay element IP 2 , which includes series connected inverters  18  and  20 , has its input connected to node  17  and has its output connected via node  21  to the source/drain circuit of transmission gate TG 2 , as well as the input of the next inverter not shown through node  21 . Farther along near the end of the delay unit  10  is a node  23  connected to the source drain circuit of transmission gate TGn- 1 . The final inverter-based delay element IPn in the programmable delay unit  10 , which includes series connected inverters  24  and  26 , has its input connected to node  23  and has its output connected to the source/drain circuit of transmission gate TGn. The source/drain circuits of the transmission gates TG 1 , TG 2 , . . . , TGn- 1 , TGn are connected to the node  22  and output line  29 . The latch  27  provides an turn ON signal to a selected one of the lines L 1 , L 2 , . . . , Ln- 1  and Ln to the gate electrode of a corresponding one of the “n” transmission gates TG 1 , TG 2 , . . . TGn- 1 , TGn as a function of the control word on bus line  28 .  
         [0009]     When the control word on control word bus  28  is latched into the latch  27 , one of the transmission gates TG 1 , TG 2 , . . . TGn- 1 , TGn is selected, i.e. turned on, and the corresponding output of one of the delay elements IP 1 , IP 2 , . . . , IPn is selected to be connected through one of the source drain circuits of the selected transmission gates TG 1 , TG 2 , . . . , TGn- 1 , TGn via node  22  to and through the output line  29  to provide the output signal OUT.  
         [0010]     The problem with the kind of delay unit illustrated by  FIG. 1  is that the rising edge delay time and the falling edge delay time are not set separately. Usually, the two delay times of each delay element are not the same. The result is that delay time differences are accumulated when more than one of the delay elements in series is selected. Thus the problem is that pulse width distortion occurs in the input pulse and the output pulse from the type of circuit shown in  FIG. 1 .  
       SUMMARY OF THE INVENTION  
       [0011]     A typical application of the present invention is described in copending U.S. patent application Ser. No. ______ (IBM Docket No. EN920030078US1) Kai D. Feng and Hongfei Wu entitled “Glitch Free Receiver For High Speed Simultaneous Bidirectional Data Bus”, the teachings of which are incorporated herein by reference.  
         [0012]     The present invention provides a solution to the problem described above with respect to  FIG. 1  by means of providing an inverter based delay unit which features a very short signal chain so that the initial delay time or the minimal delay time is very small, (two inverter delay time) can be down to the picoseconds (ps) range. It can be used as application of on-chip timing adjustment of high speed integrated circuits.  
         [0013]     In accordance with this invention, a dual edge programmable delay unit is provided that includes a circuit with fast setting time, very short minimum delay time, and independent rising edge and falling edge delay time settings. The programmable delay unit of this invention can be used as real time, on-chip timing adjustment unit in a high speed system.  
         [0014]     Further in accordance with this invention, a method and device are provided for programming of a dual edge programmable delay unit a programmable delay unit in response to an input signal. A buffer control circuit is included which receives an input signal with a rise time and a fall time and provides an output signal with variable delays between the rise and fall times of the output signal as programmed to programmable control sources (PCS) providing a separate control inputs to first and RTPCS. The FTPCS provides a first output current which charges a capacitor in the buffer and the RTPCS provides a second output current which discharges the capacitor in the buffer circuit. Variable control signals are provided to the PCS. The FTPCS provides an output current through the buffer circuit when the input signal transits from logic high to logic low and the RTPCS provides an output current through the buffer circuit when the input signal transits from logic low to logic high. The buffer control circuit responds to the output current through the FTPCS when the input signal transits from logic high to logic low or responds the output current through the RTPCS when the input signal transits from logic low to logic high.  
         [0015]     Preferably there are two separate controlled programmable current sources on the P side and the N side. The P side programmable source sets the charge current to the gate capacitance so that it can control the delay time at the falling edge (when the input signal VA changes from logic high to logic low). The N side programmable source sets the discharge current from the gate capacitance so that it can control the delay time at the rising edge (when the input signal VA changes from logic low to logic high). Therefore the two delay times can be adjusted independently. Since the dual edge delay times can be programmable separately, the delay unit can set different delay times for the rising edge and the falling edge, which is a feature that is especially useful in adjusting the timing of integrated circuits.  
         [0016]     Preferably, the programmable current source consists of a pair of switching current mirrors or switching current sources that can be turned ON or turn OFF very fast on the order of picoseconds (ps). There is a code protection circuit in the delay unit, which restricts the P side current source to changing the current setting code only during the time that the input signal VA at logic high. The code protection circuit in the delay unit also restricts the N side current source to changing the current setting code only when the input signal VA is at logic low. Thus all delay times are predictable, because no delay time between two settings would occur. Due to the improved performance of the dual edge programmable delay unit, it can be used for real time and on-chip timing adjustment in integrated circuits to reach glitch free status.  
         [0017]     A buffer circuit is provided which includes a pair of inverters. The second inverter is a Schmitt trigger circuit which has a fast rising time and a fast falling time due to positive feedback.  
         [0018]     Preferably, the buffer control circuit includes a first inverter and a second inverter. A buffer control circuit is provided including a first inverter and a second inverter each having an input and an output with the first having a first input and a first output and the second inverter having a second input and a second output. The first inverter to responds to the FTPCS when the input signal transits from logic high to logic low to connect between the FTPCS and the first output. Provide for the first inverter to respond to the RTPCS when the input signal transits from logic low to logic high to connect between the RTPCS and the first output. Connect the first output of the first inverter to a node connected to the second input of the second inverter with the second inverter providing the output signal at the second output, from the second inverter. Connect a capacitor between the node and a reference potential. Provide a Schmitt trigger circuit as the second inverter. Provide current mirror circuits in the FTPCS and the RTPCS. Provide a first control word to a first latch which in turn provides a first variable control signal to the FTPCS. Provide a second control word to a second latch which in turn provides a second variable control signal to the RTPCS. Provide FET fingers in the FTPCS with each finger thereof being controlled by an output from a register in the first latch. Provide FET fingers in the RTPCS with each finger thereof being controlled by an output from a register in a corresponding latch.  
         [0019]     In accordance with another aspect of this invention, provide dual edge programming using a programmable delay unit with a buffer control circuit including a signal input, a signal output, a PSPC connection line, and a NSPC connection line. Provide a P Side Programmable Current (PSPC) source with a PSPC input and a PSPC current line connected to the buffer through the PSPC connection line. Provide an N side (NS) latch that is adapted to receive an input of an N side control word and a N side write signal and outputs of N side switching signals, which are a function of the N side control word. The NS latch provides outputs of N side switching signals that are a function of the N side control word, with outputs of the N side switching signals being provided to the input of the PSPC source. Provide an N Side Programmable Current (NSPC) source having an NSPC source input and an NSPC current line connected to the buffer through the NSPC connection line. Provide a P side (PS) latch adapted to receive an input of an P side control word and a P side write signal and outputs of P side switching signals, which are a function of the P side control word. The PS latch provides outputs of P side switching signals which are a function of the P side control word with the outputs of the N side switching signals being provided to the input of the PSPC source.  
         [0020]     The buffer control circuit includes a first inverter and a second inverter. Provide the buffer control circuit with a first inverter and a second inverter each having an input and an output with the first having a first input and a first output and the second inverter having a second input and a second output. Provide for the first inverter to respond to the first PSPC source when the input signal transits from logic high to logic low to connect between the first PSPC source and the first output. Provide for the first inverter to respond to the second PSPC source when the input signal transits from logic low to logic high to connect between the second PSPC source and the first output. Connect the first output of the first inverter to a node connected to the second input of the second inverter.  
         [0021]     The second inverter provides the output signal at the second output, from the second inverter. Provide a PMOS FET and an NMOS FET in the first inverter having first ends of source drain circuits thereof connected to the output of the first inverter. Connect the input to the first inverter to gate electrodes of the PMOS FET and the NMOS FET. Connect opposite ends of the source drain circuits of the PMOS FET and the NMOS FET to outputs of the first PSPC source and the second PSPC source.  
         [0022]     In accordance with still another aspect of this invention, a dual edge programmable delay unit responsive to an input signal is provided. A buffer control circuit receives an input signal with a rise time and a fall time, the buffer control circuit providing an output signal with variable delays between rise and fall times of the output signal as a function of programming provided to first and second programmable control sources (PCS). A first control input to the FTPCS and a separate, a second control input to a RTPCS. Each of the FTPCS being programmable to provide a first variable output current. Each of the RTPCS being programmable to provide a second variable output current. A first variable control signal to the FTPCS and a second variable control signal to the RTPCS.  
         [0023]     The buffer control circuit responds (a) when the output current through the FTPCS the input signal transits from logic high to logic low, or (b) when the output current through the RTPCS when the input signal transits from logic low to logic high. The FTPCS is adapted to provide output current to the buffer circuit when the input signal transits from logic high to logic low. The RTPCS is adapted to provide output current to the buffer circuit when the input signal transits from logic low to logic high. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]     The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which:  
         [0025]      FIG. 1  shows a schematic circuit diagram of a conventional prior art programmable delay unit.  
         [0026]      FIG. 2A  is a schematic block diagram of a programmable delay unit in accordance with this invention which can adjust the rising edge delay time and falling edge delay time independently from input signal VA to output signal VAD.  
         [0027]      FIG. 2B  is a schematic diagram of the buffer circuit shown in  FIG. 2A  consisting of two inverters and a capacitor.  
         [0028]      FIG. 2C  shows a Schmitt trigger circuit which is the second inverter of the buffer circuit  FIG. 2B .  
         [0029]      FIG. 2D  shows the P side programmable current source of  FIG. 2A , which is a P type current mirror.  
         [0030]      FIG. 2E  shows the P side latch of  FIG. 2A  which consists of a set of “n” D type registers plus an AND gate.  
         [0031]      FIG. 2F  shows the N side programmable current source of  FIG. 2A , which is an N type current mirror.  
         [0032]      FIG. 2G  shows the N side latch of  FIG. 2A  which consists of a set of “n” D type registers plus an inverter and an AND gate. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0033]      FIG. 2A  is a schematic block diagram of a programmable delay unit  30  in accordance with this invention, which can independently adjust both the rising edge delay time and the falling edge delay time of an output signal VAD which is produced in response to an input signal VA.  
         [0034]     The programmable delay unit  30  shown in  FIG. 2A  consists of five sub-circuits. A first one of those circuits is a buffer circuit U 1 , which receives the input signal VA and produces the output signal VAD. The programmable delay unit  30  also includes a P side Programmable Current (PSPC) source U 2 , a P Side (PS) Latch U 3 , an N side Programmable Current (NSPC) source U 4 , and an N Side (NS).  
         [0035]     The latch U 3  provides digital signals to the PSPC source U 2  to control the adjustment of the falling edge delay time of the output signal VAD relative to the falling edge time of the input signal VA in response to a digital input from P Side Control Word input bus  40  under control of a computer control system (not shown). In turn, the PSPC source U 2  generates a current supplied on line  36  to the buffer circuit U 1  the variable amplitude of which controls the falling edge delay time of the output signal VAD in response to digital falling edge delay control signals from the PS latch U 3   
         [0036]     The latch U 5  provides digital signals to the NSPC source U 4  to control the adjustment of the rising edge delay time of the output signal VAD relative to the rising edge time of the input signal VA in response to a digital input from the N Side Control Word input bus  50  under control of a computer control system (not shown). In turn, the NSPC source U 4  generates a current supplied on the line  38  to the buffer circuit U 1  the variable amplitude of which controls the rising edge delay time of the output signal VAD in response to rising edge delay control signals from the NS latch U 5 .  
         [0037]     Thus, the falling edge delay time and the rising edge delay time of the output signal VAD relative to the falling edge and rising edge time of the input signal VA are controlled independently.  
         [0038]     A power supply with voltage VCC (positive voltage) is connected to all sub-circuits including buffer U 1 , PSPC source U 2 , PS latch U 3 , NSPC source U 4  and NS latch U 5  by line  31  via connected nodes. The ground or reference potential (0V) of the power supply is connected to all sub-circuits including buffer U 1 , PSPC source U 2 , PS latch U 3 , NSPC source U 4 , and NS latch U 5  by line  32  via connected nodes.  
         [0039]     The P side control word is supplied as a digital signal on the bus line  40  to the PS latch U 3  and a write signal is supplied thereto on the line  66 . The P side control word on bus line  40  and the write signal on line  66  are supplied to the PS latch U 3  by the system controller (not shown) which may be a microprocessor, a phase detector, a microcontroller, or a glitch detector, as will be well understood by those skilled in the art.  
         [0040]     The PS latch U 3  supplies a set of digital switching signals PL 1 , . . . , PLn- 1 , PLn on lines  41 ,  42 ,  43  to the PSPC source U 2 , which is connected by the U 2  to U 1  buffer input line  36  to supply an analog current to the buffer U 1 . The analog current passing through the U 2  to U 1  buffer input line  36  varies as a function of the P side control word on line  40 , as registered by P side latch U 3 .  
         [0041]     An N side control word is supplied as a digital signal on bus line  50  to NS latch U 5  and a write signal is supplied thereto on line  76 . The N side control word on bus line  50  and the write signal on line  76  are supplied by the system controller (not shown) which may be a microprocessor, a phase detector, a microcontroller, or a glitch detector, as will be well understood by those skilled in the art.  
         [0042]     The NS latch U 5  supplies a set of digital switching signals NL 1 , . . . , NLn- 1 , NLn on lines  51 ,  52 ,  53  to the NSPC source U 4 , which is connected by line  38  to supply an analog current to the buffer U 1 . The analog current passing through line  38  varies as a function of the N side control word on line  50 , as registered by the N side latch U 5 .  
         [0043]     The input signal VA is connected through line  12 ′ to the buffer U 1 , and from line  12 ′ to line  46  to the PS latch U 3  and from line  12 ′ to line  56  to the NS latch U 5 . Buffer U 1  supplies the output signal VAD on line  39 .  
         [0000]     1. The Buffer Circuit  
         [0044]     Referring to  FIG. 2B , the buffer circuit U 1  consists of two inverters I 1  and  12  plus a capacitor C. The first inverter I 1  has its input connected to receive the input signal VA on line  12 ′ and to provide its output at a node  37 . Line  36  from PSPC source U 2  and line  38  from NSPC source  38  connect to the first inverter I 1 .  
         [0045]     One terminal of the capacitor C is connected to both the output of the first inverter I 1  and the input of the second inverter  12  through the nodes/line  37 . The other terminal of the capacitor C is connected via nodes/line  32  to the reference potential (0V).  
         [0046]     The second inverter  12 , shown in detail in  FIG. 2C , is a Schmitt trigger circuit which has its input connected to node/lines  37  and its output connected to output line  39  to provide the output signal VAD. In addition, the second inverter  12  is connected by line  31  to power supply voltage VCC and to reference potential (0V) via line  32 .  
         [0047]     Referring to  FIG. 2B , the first inverter II includes a CMOS pair of FET devices comprising the PFET PA and the NFET NA with their source/drain circuits connected in series with their drains connected together at node  37 . The source terminal of the PFET PA is connected via line  36  to the PSPC source U 2 . The source terminal of the NFET NA is connected via line  38  to the NSPC source U 4 .  
         [0048]     When the input signal VA on line  12 ′ transits from logic high to logic low, in the inverter I 1  the PFET PA is turned ON and NFET NA is turned OFF. When the PFET PA is turned ON, analog current flows from line  36 . The analog current flowing through line  36 , which varies as a function of the P side digital control word on bus line  40 , flows through the source/drain circuit of the PFET PA into the node  37  to charge the input capacitance C relative to the reference potential. In other words, the current that charges the capacitor C or the input capacitance of the second inverter  12  is the source current flowing through line  36 , which (as stated above) is connected to the PSPC source U 2 , shown in  FIG. 2D .  
         [0049]     If the charging current is large, the voltage on the node  37  across the capacitance C increases rapidly, the output of the second inverter  12  is changed from logic high to logic low early. Thus the delay time of the falling edge of output signal VAD is short. On the other hand, if the charging current is small, the voltage on node  37  across the capacitance C increases slowly, and the output VAD of the second inverter I 2  is changed from logic high to logic low late. Thus the delay time of the falling edge of output signal VAD is long.  
         [0050]     When the input signal VA transits from logic low to logic high, in the inverter I 1 , the PFET PA is turned OFF and NFET NA is turned on. When NFET NA is turned on, analog current flows from the capacitor C through node  37  and line  38  between buffer U 1  and the NSPC U 4 . The analog current, which varies as a function of the digital N side control word on bus line  50 , discharges the input capacitance C at the input of the second inverter  12  as a result of the analog sink current flowing through line  38 , which (as stated above) is connected to the NSPC source U 4 , shown in  FIG. 2F .  
         [0051]     If the discharging current is large, the voltage on the capacitance C decreases rapidly, the output VAD of the second inverter  12  is changed from logic low to logic high early, and the delay time of the rising edge of the output signal VAD is short. If the discharging current is small, the voltage on the capacitance C decreases slowly, the output of the second inverter  12  changes from logic low to logic high late, the delay time of the rising edge of output signal VAD is long.  
         [0052]     The input capacitance C to the second inverter  12  may be a separate capacitor C, as shown in  FIG. 2B . Alternatively, the input capacitance C may comprise the parasitic capacitance of the output circuit of the first inverter I 1  and the input circuit of the second inverter  12 .  
         [0053]     It is obvious that the PSPC source U 2  determines the falling edge delay time and the NSPC source U 4  determines the rising edge delay time. Since there is separate control of the PSPC source U 2  and the NSPC source U 4 , as described above, the falling edge delay time and the rising edge delay time can be set independently.  
         [0054]      FIG. 2C  shows the details of a preferred embodiment of the schematic circuit diagram of the second inverter  12  including PMOS FET devices PB, PC and PD and NMOS FET devices NB, NC and ND connected in a Schmitt trigger configuration. The second inverter  12  can decrease the rising time and falling time of the inverter output signal VAD because of the positive feedback. The nodes/lines  37  serve as the input to the second inverter  12  connecting through nodes/lines  61  to the gates of PMOS FETs PB and PC and the gates of NMOS FETs NB and NC.  
         [0055]     The power supply voltage VCC is connected through line  31  to the node/lines  66  thereby connecting to the source of PMOS FET PB and the drain of NMOS FET ND. The reference potential 0V is connected through line  32  to node and line  65 , which connects to the source of NMOS FET NC and the drain of PMOS FET PD.  
         [0056]     The source/drain circuits of PMOS FETs PB and PC and NMOS FETs NB and NC are connected in series in that order between node  66  (VCC) and node  65  (0V). The drain of PMOS FETs PB is connected through node and lines  62  to the sources of PMOS FETs PD and PC. The drain of NMOS FETs NC is connected through node and lines  63  to the sources of NMOS FETs NB and ND. The drains of PMOS FET PC and NMOS FET NB are connected through nodes and lines  64  and the output line  39  to the terminal for the output signal VAD and the gates of PMOS FET PD and NMOS FET ND.  
         [0000]     2. P Side Programmable Current (PSPC) Source U 2   
         [0057]      FIG. 2D  is a schematic circuit diagram of PSPC source U 2  of  FIG. 2A , which is a P type current mirror that converts a digital input signal on lines  41 - 43  from PS latch U 3  to an analog current through output line  36 . The primary part of the current mirror includes a fixed current source IP and the initial PMOS FET P 0  which provide a current to be mirrored. The source of PMOS FET P 0  is connected via lines/nodes  71  to line  31  to power supply voltage VCC. The drain and gate of PMOS FET P 0  are interconnected to node/lines  72  and the upper end of fixed current source IP. The lower end of fixed current source IP is connected through line  32  to the reference potential (0V) terminal of the power supply.  
         [0058]     The secondary part of the P type current mirror comprises a set of PMOS FET fingers P 1 , . . . , Pn- 1 , Pn comprising programmable current sources that are switched by switch circuits connected to receive the respective digital switching signals PL 1 , . . . , PLn- 1 , PN on lines  41 ,  42 ,  43  from the PS latch U 3 , plus the default PFET PD. The PMOS FET P 0 , the switched PMOS FETs P 1 , . . . Pn- 1 , Pn, and the PMOS default FET PD have the same channel length, but they all have different channel widths. The analog current through each of the fingers P 1 , . . . , Pn- 1 , Pn is the product of the current through the fixed current source IP and the ratio of the channel width of the PMOS FET in that particular finger over the channel width of the PMOS FET P 0 .  
         [0059]     The switch circuits comprise a set of inverters IP 1 , . . . IPn- 1 , IPn, and corresponding series connected pairs of the PMOS FETs P 1 _ 1 , P 1 _ 2 , . . . , Pn- 1 _ 1 , Pn- 1 _ 2 , Pn_ 1 , and Pn_ 2  turn ON or turn OFF each of the fingers P 1 , . . . Pn- 1 , Pn in response to the signals PL 1 , PLn- 1  and PLn on lines  41 ,  42 , 43 . The PMOS FETs P 1 _ 1  and P 1 _ 2 ; PFETs Pn- 1 _ 1  and PFETs Pn- 1 _ 2 ; and Pn_ 1 , and Pn_ 2  are connected as series pairs with their source/drain circuits connected in series. The sources of upper PMOS FETs P 1 _ 1 , Pn- 1 _ 1 , and Pn_ 1 , are connected to power supply VCC via lines/nodes  71  and line  31 . The drains of PFETs P 1 _ 2 , Pn- 1 _ 2 , and Pn_ 2  are connected via lines/nodes  72  to the gate of PMOS FET P 0  and the upper end of current source IP. The drains of PMOS FETs P 1 , Pn- 1 , Pn are connected via lines/nodes  79  and the output line  36  to buffer U 1 .  
         [0060]     First input PL 1  on line  41  from P side latch U 3  connects to node  73  of the first switch circuit that connects to the gate of PMOS FET P 1 _ 2  and input of the inverter IP 1  that provides an output to the gate of PMOS FET P 1 _ 1 . The n- 1   th  input PLn- 1  on line  42  from PS latch U 3  connects to node  75  of the n- 1   th  switch circuit that connects to the gate of PMOS FET Pn- 1 _ 2  and input of the inverter IPn- 1  that provides an output to the gate of PMOS FET Pn- 1 _ 1 . The nth input PLn on line  43  from PS latch U 3  connects to node  77  of the nth switch circuit that connects to the gate of PMOS FET Pn_ 2  and input of the inverter IPn that provides an output to the gate of PMOS FET Pn_ 1 .  
         [0061]     For example, when control signal on PL 1  line  41  from the PS latch U 3  is at its logic low, in the first switch circuit the PMOS FET P 1 _ 1  is turned OFF, and PMOS FET P 1 _ 2  is turned ON causing the PMOS FET P 1  to be turned ON so that the mirrored current through PMOS FET P 1  is ON allowing current to flow from the voltage source VCC through line  31 , node  71 , the source/drain of finger P 1  and node  79  to provide an output flow of current through line  36  to the buffer U 1 . On the other hand, when the control signal on PL 1  line  41  is at its logic high, PMOS FET P 1 _ 1  is turned ON, PMOS FET P 1 _ 2  is turned OFF, so PMOS FET P 1  is turned OFF, so no mirrored current sources (i.e. flows) through the source/drain circuit of finger P 1  through line  79  and line  36  to the buffer U 1 .  
         [0062]     PMOS FET PD is a default finger without any connection of a switch circuit to the gate electrode thereof. The PMOS FET PD always provides a charge current when the PMOS FET PA of the buffer U 1  is turned ON, so that when all programmable fingers are turned OFF, the PMOS FET PD still provides a charge current via line/node  79  through line  36  to the buffer U 1 . All inverters (IP 1 , . . . , IPn- 1 , IPn) are powered by the power supply VCC and 0V.  
         [0000]     3. P Side (PS) Latch U 3   
         [0063]      FIG. 2E  is a schematic, circuit diagram of the PS latch U 3  of  FIG. 2A . PS latch U 3  consists of a set of “n” D type registers PD 1 , . . . , PDn- 1 , PDn. A D type register or a D register is a very popular unit in digital circuits. Such a register has two inputs: D and CLK. When a pulse is applied to the CLK input, the logic status on input D is read to the register output Q. The data terminals of the D type registers are connected to individual lines PCW 1 , . . .PCWn- 1 , PCDWn in bus line  40  that connect bits of the P side control word to individual ones of the registers PD 1 , , . . . ,PDn- 1 , PDn. The complement outputs -Q of the registers PD 1 , . . . , PDn- 1 , PDn provide the digital control signals PL 1 , . . . , PLn- 1 , PLn on lines  41 - 43  to the P side PSPC source U 2 .  
         [0064]     When the P side control word on bus lines  40  is written by a write signal on line  66 , (connected through AND  45  to the node that connects through lines/nodes  44  to the CLK input of the registers PD 1 , . . . , PDn- 1 , PDn by the signal of “write” on line  66 ) the logic status of the control signals of fingers P 1 , Pn- 1 , Pn could be changed. For example, when the bit on line PCW 1  is logic high and written to the register PD 1 , PL 1  line  41  is at a logic low which turns ON the finger P 1  of P side PSPC source U 2 . However, when the bit on line PCW 1  is logic low and written to the register PD 1 , PL 1  line  41  is at logic high, which turns OFF the finger P 1  of the PSPC source U 2 .  
         [0065]     The AND gate  45  is important because it provides protection, that only when the input signal VA on line  46  to AND  45  is at a logic high (because the PMOS FET PA of the first inverter I 1  of buffer U 1  is turned OFF) the “write” signal on line  66  is allowed to write a new status of the P side control word to the registers PD 1 , , . . . ,PDn- 1 , PDn to change the logic statuses of the fingers P 1 , . . . Pn- 1 , Pn.  
         [0066]     The protection function guarantees that the timing of the delay time of each falling edge of the input pulse of input signal VA is predictable and controllable. This function makes the delay unit qualified to adjust the timing of a high speed system both on line and in real time.  
         [0067]     All D type registers (PD 1 , . . . PDn- 1 , PDn) and AND gate  45  are powered by the power supply VCC and 0V.(please delete the connections  31  and  32  on the D type registers).  
         [0000]     4. N Side Programmable Current (NSPC) Source U 4   
         [0068]      FIG. 2F  is a schematic circuit diagram of NSPC source U 4  of  FIG. 2A , which is an N type current mirror that converts a digital input signal on lines  51 - 53  from PS latch U 5  to an analog current through output line  38 . The primary part of the current mirror includes a fixed current source IN and the initial NMOS FET N 0  that provide a current to be mirrored. The source of NMOS FET P 0  is connected via lines/nodes  81  to line  32  to reference potential (0V). The drain and gate of NMOS FET N 0  are interconnected to node/lines  82  and the lower end of fixed current source IN. The upper end of fixed current source IN is connected through line  31  to the terminal of the power supply voltage VCC.  
         [0069]     The NSPC source U 4 , shown in  FIG. 2F  is an N type current mirror. Primary parts of the current mirror are fixed current source IN and PMOS FET N 0 . Secondary parts of current mirror U 4  are a set of switched NMOS FET fingers N 1 , . . . Nn- 1 , Nn plus the default NMOS FET ND. The NFETs NO, N 1 , . . . Nn- 1 , Nn, ND have the same channel length, but different channel widths, the current through each finger is the product of the current through the fixed current source IN and the ratio of the channel width of the NMOS FET in that particular finger over the channel width of the PMOS FET N 0 .  
         [0070]     The inverters of IN 1 , . . . INn- 1 , INn, NMOS FETs N 1 _ 1 , N 1 _ 2 , . . . Nn- 1 _ 1 , Nn- 1 _ 2 , Nn_ 1 , Nn_ 2  are used to turn each of the fingers ON or OFF. For example, when the control signal on NL 1  line  51  from the NS latch U 5  is at logic high, NMOS FET N 1 _ 1  is turned OFF, NMOS FET N 1 _ 2  is turned ON so that NMOS FET N 1  is turned on, the mirrored current through NMOS FET N 1  is ON. When the control signal on NL 1  line  51  is at logic low, NMOS FETs N 1 _ 1  is turned ON, NMOS FET N 1 _ 2  is turned OFF, NMOS FET N 1  is turned OFF, so no mirrored current sources (i.e. flows) from the finger N 1  through the source/drain of the fingers of the NSPC source U 4  and through lines  79  and  38  to buffer U 1 .  
         [0071]     The NMOS FET ND is a default finger without the switch circuits in the gate, The NMOS FET ND always provides discharge current when the NMOS FET NA of the buffer U 1  is turned ON, so that when all programmable fingers are turned OFF, the NMOS FET ND still provides the discharge current. All of the inverters (IN 1 , . . . INn- 1 , INn) are powered by connection across the power supply VCC and reference potential ( 0 V).  
         [0000]     5. N Side (NS) Latch U 5   
         [0072]     The NS latch U 5  shown in  FIG. 2G  consists of a set of D type registers ND 1 , . . . NDn- 1 , NDn, wherein the data terminals of the registers are connected to bits of the N side control word, NCW 1 , . . . NCWn- 1 , NCDWn. The outputs of the registers ND 1 , . . . NDn- 1 , NDn provide the digital control signals NL 1 , . . . ,NLn- 1 , NLn on lines  51 - 53  to the NSPC source U 4 . When the control word on bus lines  50  is written to the registers ND 1 , . . . NDn- 1 , NDn by the signal of “write” on line  76  transmitted through AND  55  to node and lines  54  which are connected to the CLK inputs of the registers ND 1 , . . . NDn- 1 , NDn, the logic status of the control signals of registers NL 1 , NLn- 1 , NLn could be changed.  
         [0073]     For example, when the control word bit on line NCWi from P side control bus line  50  is logic high and written to the register ND 1 , control signal on NL 1  line  51  is at logic high which turns ON the finger N 1  of NSPC source U 4 , when the bit of NCW 1  is logic low and written to the register ND 1 , NL 1  is at logic low which turns OFF the finger N 1  of NSPC source U 4 .  
         [0074]     The combination of the inverter  57  and the AND gate  55  provides an important protection, only when the input signal VA is at logic low, the NMOS FET NA of buffer U 1  is turned OFF, the signal “write” is allowed to write a new status of N side control word to the registers ND 1 , . . . NDn- 1 , NDn to change the logic statuses on lines NL 1 , . . . NLn- 1 , NLn.  
         [0075]     The protection function guarantees the delay time of each rising edge of the input pulse of input signal VA is predictable and controllable. This function makes the delay unit qualified to adjust the timing of high speed system on line and in real time.  
         [0076]     All of the D type registers(ND 1 , . . . NDn- 1 , NDn), the AND gate  55  and the inverter  57  are powered by the power supply VCC and reference potential ( 0 V).  
         [0077]     While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.