Abstract:
A dynamic switching voltage regulator includes a load indicator, power switches, and a controller. The load indicator generates a load signal responsive to different output load conditions of the regulator. The controller receives the load signal and drives the power switches at a first switching frequency. The controller changes the switching frequency to a second frequency in response to a change in the load signal.

Description:
BACKGROUND 
     This disclosure relates to voltage regulators and more specifically, to a hysteretic mode synchronous buck voltage regulator. 
     A voltage regulator converts an input voltage to a regulated output voltage. Although there are many types and applications for voltage regulators, one such type is a switching, DC-to-DC, step-down voltage regulator, or “buck” regulator. The switching regulator is often chosen due to its small size and efficiency. An example of a typical application is a battery-powered electronic device such as a portable computer. In an example such as this, a voltage regulator is required to provide a predetermined and constant output voltage to a load from an often-fluctuating input voltage source, the battery. 
     A hysteretic-mode voltage regulator works by regulating the output voltage according to a particular hysteresis level or output voltage ripple. A hysteretic controller in the voltage regulator maintains the output voltage within a hysteresis band centered about the internal reference voltage. The level of hysteresis or ripple is fixed through the entire load range of the voltage regulator. 
     In a switching regulator, the field-effect transistors (FETs) switch on and off to maintain a certain switching frequency. During this switching time, the transistors enter a linear region where much power is dissipated because the FETs are sourcing current. 
     SUMMARY 
     The inventors noticed that when the voltage regulator is heavily loaded, average transition FET power dissipation increases in response to an increase in switching frequency. However, when the voltage regulator is lightly loaded, the transition FET power dissipation becomes negligible compared to an inductor ripple current. An increase in the ripple current causes magnetic inductor core loss and output capacitor equivalent-series-resistance (ESR) loss. Thus, when the regulator is lightly loaded, the inductor ripple current increases in response to a decrease in switching frequency. Therefore, it is advantageous to vary the switching frequency of the regulator according to the load indication. This ability to vary the switching frequency significantly reduces the quiescent power dissipation of the voltage regulator. 
     A dynamic switching voltage regulator includes a load indicator, power switches, and a controller. The load indicator generates a load signal responsive to different output load conditions of the regulator. The controller receives the load signal and drives the power switches at a first switching frequency. The controller changes the switching frequency to a second frequency in response to a change in the load signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Different aspects of the disclosure will be described in reference to the accompanying drawings wherein: 
     FIG. 1 is a simplified schematic diagram of a dynamic hysteretic-mode synchronous buck voltage regulator; 
     FIG. 2 is a simplified representation of hysteretic-mode switching frequency control; 
     FIGS. 3A through 3D illustrate two exemplary energization/de-energization cycles that last from time T 0  to T 4 ; 
     FIGS. 4A through 4D show a decreased switching frequency, lower than the frequency generated in FIG. 3C, in response to an increase in the hysteretic voltage level; 
     FIGS. 5A through 5D show an increased switching frequency in response to a decrease in the hysteretic voltage level; 
     FIG. 6 shows a change in switching frequency in response to the change in load indication signal; 
     FIG. 7 is a flow diagram of the switching frequency adjustment process; and 
     FIG. 8 is a block diagram of a computer system that includes a dynamic hysteretic-mode voltage regulator. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a simplified schematic diagram of a dynamic hysteretic-mode synchronous buck voltage regulator  100 . The regulator is connected to an output load  112 . The dynamic hysteretic- or ripple-mode voltage regulator  100  includes an input filter  102 , a pair of metal-oxide silicon field-effect transistors (MOSFETs) Q 1  and Q 2 , an output filter  104 , and a controller  106  that provides the synchronous switching function. 
     The controller  106  often interacts with a drive circuit  108  to generate non-overlapping switching voltages, V SW1  and V SW2 . The switching voltages control operations of complementary MOSFETs Q 1  and Q 2 , respectively. The voltage regulator  100  also includes a load indicator  110  that generates an output signal in response to a load indication. The output signal indicates whether the voltage regulator  100  is lightly or heavily loaded. This signal asserts an input pin of the controller  106  to change the hysteretic level and the switching frequency. 
     The load indicator  110  receives a load indication signal, {overscore (STP _ CPU)}, from a processor. The load indication signal is asserted logical high when the regulator output  114  is heavily loaded and is de-asserted logical low when the regulator output  114  is lightly loaded. The signal drives the gate terminal of the n-channel MOSFET switch Q 3 . When the load signal is asserted, the switch Q 3  closes. This drives the load indicator output  116  to logic high. When the signal is de-asserted, the switch Q 3  opens. This drives the load indicator output  116  to a logic low through a resistor R 2 . 
     During the operation of the ripple-mode voltage regulator  100 , the controller  106  controls the output voltage, V CORE . If the output voltage falls below the regulation level, the controller  106  turns on Q 1  and turns off Q 2 . This configuration charges inductor L 1  in the output filter  104  and feeds the output load  112 . When the output voltage exceeds the regulation level, the controller  106  turns off Q 1  to begin an interval during which energy is transferred from the inductor L 1  to the bulk capacitor C 1 . After the switch Q 1  is turned off, the diode D 2  conducts and allows energy to be transferred from the inductor L 1  and to the output load  112 . A short time after the controller  106  de-asserts the V SW1  voltage, the controller  106  asserts the V SW2  voltage to turn on the switch Q 2 . The closed switch Q 2 , in turn, shunts the diode D 2 , and reduces the effective resistance path for the I LD  current. Shunting of the diode D 2  reduces the power that is otherwise dissipated by the diode. This maintains continuous power delivery during the on and off states of Q 1 . 
     The controller  106  also ensures that power MOSFETs Q 1  and Q 2  are never on simultaneously. This condition would place a momentary short across the input power bus and result in lower efficiencies. The condition could also overload, and also potentially destroy the switching devices. 
     A simplified representation of hysteretic control is shown in FIG.  2 . When the output voltage is below the level of the reference  206  minus one-half of the hysteresis (low limit)  202 , the controller turns on Q 1  and turns off Q 2 . This is the power stage ON state. It causes the output voltage to increase. When the output voltage reaches or exceeds the reference  206  plus one-half of the hysteresis (high limit)  200 , the controller turns off Q 1  and turns on Q 2 . This is the power stage OFF state. It causes the output voltage to decrease. This hysteretic method of converter control keeps the output voltage within the hysteresis band  204  around the reference voltage  206 . 
     If output-load current (I LD ) steps or input-voltage (V IN ) transients force the output voltage out of the hysteresis band  204 , the controller  106  sets the power-stage MOSFETs in the continuous ON or OFF state, as required, to return the output voltage to the hysteresis band  204 . Thus, the output voltage is corrected as quickly as the output filter allows. 
     FIGS. 3A through 3D illustrate two exemplary energization/de-energization cycles that last from time T 0  to T 2  and T 2  to T 4 . The controller  106  interacts with the drive circuit  108  to assert the V SW1  voltage at time T 0  (at  300 ). The assertion of the V SW1  voltage causes the switch Q 1  to close. The I LD  current has a positive slope at  302 , as energy is being stored in the inductor L 1  from time T 0  to time T 1 . Also during the interval from time T 0  to T 1 , the V F  voltage rises upwardly from the lower threshold voltage to the upper threshold voltage at  304 . The controller  106  detects this occurrence and responds by interacting with the drive circuit  108  to de-assert the V SW1  voltage to open the switch Q 1 . 
     The opening of the switch Q 1  begins an interval during which energy is transferred from the inductor L 1  to the bulk capacitor C 1 . The I LD  current assumes a negative slope from time T 1  to T 2  at  306 . A short time after the controller  106  de-asserts the V SW1  voltage, the controller  106  asserts the V SW2  voltage at  308  to close the switch Q 2 . 
     The controller  106  asserts the V SW2  voltage from time T 1  to T 2  to allow energy to be transferred from the inductor L 1 . This transfer of energy causes the V F  voltage (and the V CORE  voltage) to decrease from the upper threshold to the low threshold at  310 . When the VF voltage reaches the lower threshold at time T 2  the controller  106  interacts with the drive circuit  108  to de-assert the voltage, which, in turn, causes the switch Q 2  to open. A short time thereafter, the controller  106  closes the switch Q 1  to begin another energization/de-energization cycle from T 2  to T 4 . 
     The controller  106 , in the above process, fixes the switching frequency, f SW , by controlling the hysteretic voltage level, V HYST . 
     FIGS. 4A through 4D show a decreased switching frequency, f′ SW  in response to an increase in the hysteretic voltage level, V′ HYST . FIG. 4B shows a higher ripple voltage level than the voltage level shown in FIG.  3 B. This results in the switching frequency f′ SW  (shown in FIG. 4C) being higher than the switching frequency f SW  generated in FIG.  3 C. 
     Similarly, FIGS. 5A through 5D show an increased switching frequency, f″ SW , that is higher than the switching frequency generated in FIG.  3 C. The increased frequency is generated in response to a decrease in the hysteretic voltage level, V″ HYST . FIG. 5B shows a lower ripple voltage level than the level shown in FIG.  3 B. FIGS. 5C and 5D indicate a higher switching frequency. 
     In one embodiment, shown in FIG. 6, the load indication signal ({overscore (STP _ CPU)}) is asserted at  500 , which indicates a heavy load. During this period, the controller  106  runs the switching frequency of the V SW1  voltage at 220 KHz (at  504 ). When the load indication signal is de-asserted at  502 , indicating a light load, the controller  106  increases the switching frequency to 350 KHz at  506 . 
     FIG. 7 is a flow diagram of the switching frequency adjustment process residing in the controller  106 . If the load indication signal ({overscore (STP _ CPU)}) indicates a heavy load at  700 , the controller  106  switches the MOSFETs at a first predetermined switching frequency by adjusting the hysteresis level to a first level at  702 . On the other hand, if the load indication signal indicates a light load at  700 , the controller  106  switches the MOSFETs at another predetermined switching frequency higher than the first frequency at  704 . Adjusting the hysteresis to a level lower than the first level generates the higher frequency. 
     A block diagram of a computer system  800 , such as a battery-powered portable computer, is shown in FIG.  8 . In some embodiments, the computer system is a file server, a mainframe computer, or other electrical device. The computer system  800  includes a dynamic hysteretic voltage regulator  100 , which controls the switching frequency by varying the hysteresis level in response to a load indication signal, {overscore (STP _ CPU)}. The voltage regulator  100  receives a DC input voltage and outputs a regulated DC output voltage. The computer also includes an AC-to-DC power converter  802 , a processor  804 , a memory  806 , and I/O devices  808 , such as display devices and disk drives. The processor  804 , the memory  806 , and I/O devices are representative of a plurality of electronic devices of the computer. These devices are collectively represented as a load  810 . 
     The advantages of the dynamic hysteretic-mode voltage regulator  100  and the switching frequency adjustment process include significant improvement in quiescent power dissipation and easy of implementation. The load indicator requires only one MOSFET switch and two resistors. Further, a computer program residing on a computer readable medium, such as a controller, can implement the adjustment process. The program comprises executable instructions that enable the computer to adjust the voltage ripple or hysteresis level in response to the load indication. other embodiments are within the scope of the following claims. For example, instead of the load indication signal, {overscore (STP _ CPU)}, a load indication circuit can be implemented to directly feed the output load information back to the load indicator. In an alternative embodiment, the load indication signal is fed back directly into the controller which can be modified to receive such a signal.