Abstract:
A high unity current gain frequency composite switching device, having high voltage compliance and capable of handling high power signals. A current switch comprising of the composite switching devices including a switch stage implemented in a InP-HBT technology and a cascode stage implemented in a GaN FET technology. A digital-to-analog converter comprising a plurality of the current switches, wherein selected output of the switches are electrically coupled to form an output of the digital-to-analog converter.

Description:
TECHNICAL FIELD 
     The present application relates to a four terminal composite switching device and in particular to a high unity current gain frequency four terminal composite switching device with a high voltage compliance. The present invention also relates to the field of current switches using four terminal composite switching devices. The present invention also relates to the field of digital to analog converters using current switches and in particular to high efficiency, high power digital to analog converters. 
     BACKGROUND 
     The ability of prior art devices to perform high power amplification and signal generation at microwave and millimeter wave frequencies is limited by the breakdown voltage and/or high unity current gain frequency, f t , of the device. For such devices, high breakdown voltage and high f t  characteristics are generally mutually exclusive since high breakdown voltage semiconductor materials have larger bandgaps and hence lower electron mobility, and conversely, high frequency performance semiconductors have higher electron mobility but lower breakdown voltages. 
     Traditionally, microwave and millimeter wave power amplification has been dominated by mostly analog class AB implementations. Other configurations such as class E, F, and S implementations have been used to improve the efficiency or linearity of generated signals, but simultaneous performance improvement in linearity, power output and maximum frequency has been difficult to achieve. 
     In microwave and millimeter wave applications, a high speed and high power Digital to Analog Converter (DAC) could be used to replace power amplifiers allowing for improved system linearity. In addition, high unity current gain frequency, high power DACs could be used to generate microwave signals straight from digital signals without the need for analog up-converters. The ability to translate digital signals to analog signals without analog up-converters improves the system performance by eliminating the degradation caused by out-of-band spurs generated by analog up-conversion. The functional operation of a DAC is well known. Generally, a DAC accepts a digital input signal and converts it into an analog output signal. The digital input signal has a range of digital codes which are converted into a continuous range of analog signal levels of the analog output signal. 
     Referring now to FIG. 1, a functional block diagram is shown of a conventional DAC  100  that is capable of high speed switching. This DAC  100  is a differential binary weighted converter comprising two inverted R-2R resistance ladder circuits  101 ,  102  having resistors whose resistance values are R and 2R and a plurality of differential current-switch circuits  120 , structured identically to one another. The number of current switches is equal to the number of input bits of the DAC  100 . The current switch circuits  120  are electrically connected between the R-2R ladder networks and a negative potential voltage V ee , i.e. −5 volts. The true outputs of each of the current switches are electrically connected to one of the two inverted R-2R resistance ladders. The false outputs of each of the current switches are electrically connected to the other of the two inverted R-2R resistance ladders. An external reference is applied to V DAC , and the R-2R ladder divides the input current into binary weighted currents. The digital input is used to control the position of the switches. 
     Further, in the prior art, digital to analog design utilizing the highest speed, high unity current gain frequency, integrated circuit technology for clock rates greater than 1 GHz results in technologies that have lower breakdown voltages than the higher voltage technology used for power applications, such as microwave and millimeter applications. The present invention enables a fully digital architecture through a power amplifier with speeds commensurate with lower breakdown voltage technologies and output powers commensurate with higher breakdown voltage, lower frequency technologies. 
     One object of the present invention is to provide a switching architecture that can support both high unity current gain frequency, f t , and high voltages and that effectively provides the ability to simultaneously achieve linearity, high power output and maximum frequency. 
     According to one embodiment of the present invention, the current switch comprises a first stage fabricated in a high f t , low band gap semiconductor such as an InP HBT (Heterojunction Bipolar Transistor). The critical property of this technology is that it provides the highest possible current switching speed. The current output drives a second stage comprising of a cascoded three terminal device fabricated in a high breakdown voltage semiconductor such as a GaN Field-Effect Transistor (FET) or HBT. By operating the second stage as a cascode, the device can switch at much higher speed than would normally be obtained with such device. 
     SUMMARY 
     It is an object of this invention to provide a high unity current gain frequency composite device with high voltage compliance. A device in accordance with the present invention comprises a switch stage implemented in a high unity current gain frequency, f t , technology with low breakdown voltage, combined with a second stage having a high maximum oscillation frequency, f max  and a high breakdown voltage. High f t  technology preferably refers to f t  greater than or equal to 150 GHz for HBT technologies and f t  greater than or equal to 100 GHz for FET technologies. High breakdown voltages are preferably greater than low breakdown voltages, and low breakdown voltages are preferably less than or equal to 5V. 
     In another embodiment, the device is preferably electrically coupled to a current source. The result is a high unity current gain frequency current switch with high voltage compliance. 
     In a preferred embodiment the first stage utilizes InP-HBT technology to achieve high unity current gain frequency, in a hybrid, possibly flip-chip assembly, while the second cascode switch stage utilizes GaN FET technology for high voltage. 
     In one embodiment, the present invention relates to digital to analog converters comprising a plurality of high f t , high voltage compliance current switches. The digital to analog converters are especially suited for microwave and millimeter wave applications. 
     In one embodiment, the present invention relates to a device comprising: a first stage comprising at least one first stage semiconductor device, said at least one first stage semiconductor device having a first stage semiconductor device breakdown voltage less than or equal to 5 volts, said at least one first stage semiconductor device having a unity current gain frequency greater than or equal to 100 GHz; and a second stage comprising at least one second stage semiconductor device, said at least one second stage semiconductor device having a second stage semiconductor breakdown voltage greater than the first stage semiconductor device breakdown voltage, and said second stage being electrically coupled to said first stage. 
     In one embodiment, the present invention relates to a dual-ended current switch comprising: a current source; a first stage comprising at least one first stage semiconductor device, said at least one first stage semiconductor device having a first stage semiconductor device breakdown voltage less than or equal to 5 volts, said at least one first stage semiconductor device having a unity current gain frequency greater than or equal to 100 GHz, and said first stage being electrically coupled to said current source; and a second stage comprising at least one second stage semiconductor device, said at least one second stage semiconductor device having a second stage semiconductor breakdown voltage greater than the first stage semiconductor device breakdown voltage, and said second stage being electrically coupled to said first stage such that said first stage is in between said current source and said second stage. 
     In another embodiment, the present invention relates to a single-ended current switch comprising: a current source; a first stage comprising at least one first stage semiconductor device, said at least one first stage semiconductor device having a first stage semiconductor device breakdown voltage less than or equal to 5 volts, said at least one first stage semiconductor device having a unity current gain frequency greater than or equal to 100 GHz, and said first stage being electrically coupled to said current source; and a second stage comprising at least one second stage semiconductor device, said at least one second stage semiconductor device having a second stage semiconductor breakdown voltage greater than the first stage semiconductor device breakdown voltage, and said second stage being electrically coupled to said first stage such that said first stage is in between said current source and said second stage 
     It is another object of this invention to provide a digital-to-analog converter comprising: a plurality of current switches; and a plurality of R-2R ladder networks electrically coupled to said plurality of current switches; wherein each of said plurality of current switches comprises: a current source; a first stage comprising at least one first stage semiconductor device, said at least one first stage semiconductor device having a first stage semiconductor device breakdown voltage less than or equal to 5 volts, said at least one first stage semiconductor device having a unity current gain frequency greater than or equal to 100 GHz, and said first stage being electrically coupled to said current source; and a second stage comprising at least one second stage semiconductor device, said at least one second stage semiconductor device having a second stage semiconductor breakdown voltage greater than the first stage semiconductor device breakdown voltage, and said second stage being electrically coupled to said first stage such that said first stage is in between said current source and said second stage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a prior art digital to analog converter 
     FIG. 2 is a schematic diagram illustrating one embodiment of a current switch in accordance with the present invention; 
     FIG. 3 is a schematic diagram illustrating another embodiment of a current switch in accordance with the present invention; 
     FIG. 4 is a graph of a simulation illustrating operation of the embodiment FIG. 3; 
     FIG. 5 is a schematic diagram of an embodiment of a single-ended current switch in accordance with the present invention; 
     FIG. 6 is a graph of a simulation illustrating operation of the embodiment of FIG. 5; 
     FIG. 7 is a schematic diagram of a digital to analog converter in accordance with the present invention; 
     FIG. 8 is a graph of a simulation illustrating operation of the embodiment of FIG. 7; 
     FIG. 9 a  is a schematic diagram illustrating another embodiment of the present invention; 
     FIG. 9 b  is a schematic diagram illustrating another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Turning to FIG. 2, one embodiment of a current switch  1  in accordance with the present invention is shown. The square boxes T 1 , T 2 , T 3 , T 4  and T 5  are generic representations of semiconductor devices which may be of any type, herein referred to as transistors. There are three terminals on a transistor, each have different names depending on the type of transistor. Thus, the nature of each terminal is indicated next to the terminal. The first terminal of the device is labeled “c/d” for collector/drain, the second terminal is labeled by “b/g” for base/gate, and the third terminal is labeled “e/s” for emitter/source to reflect the fact that either bipolar transistor and/or field effect transistor technology can be utilized. 
     The differential current switch  1  preferably comprises a current source  2 , a first stage  3  and a second stage  4 , as illustrated in FIG.  2 . The current source  2  is electrically coupled to the first stage  3 . The current source  2  shown may be provided by a single transistor T 3  with a resistor R 0 ; however, one skilled in the art will appreciate that the current source may be formed by any current source circuit which produces a predetermined constant current. Voltage V CS  at terminal  8  is a node voltage which, together with transistor T 3  and resistor R 0 , controls the current through the current source. 
     The first stage  3  provides for current switching in this system. The first stage  3  comprises at least one semiconductor device preferably fabricated from a high f t , low breakdown voltage technology. The second stage  4  provides the switch with the ability to provide the high voltages required for millimeter and microwave technologies. The second stage  4  is comprised of at least one semiconductor device preferably fabricated from a breakdown voltage technology which is higher than the breakdown voltage technology used in the first stage. 
     In one embodiment, as shown in FIG. 2, the first stage  3  comprises two three terminal semiconductor devices, transistors T 1  and T 2 . The third terminal  5  of T 1  is preferably electrically coupled with the third terminal  6  of T 2 , resulting in the transistors being electrically connected as a differential pair. The third terminals  5 ,  6  of T 1  and T 2  are also electrically coupled to the current source  2 . The current source controls the current through the first stage. Connectors  9  and  10  are complementary input node voltages which drive the switch. Voltage applied to connector  9  switches ON and OFF transistor T 1 , while voltage applied to connector  10  switches ON and OFF transistor T 2 . 
     As shown in FIG. 2, the second stage  4  is electrically coupled to the first stage  3  such that the first stage  3  is between the current source  2  and the second stage  4 . The second stage  4  preferably includes two three terminal semiconductor devices, transistors T 4  and T 5 . The second terminal  16  of T 4  is preferably electrically coupled to the second terminal  17  of T 5 , resulting in the transistors being electrically connected as a cascode. By operating transistors T 4  and T 5  as a cascode, the second stage can switch at a much higher speed than would normally be obtained with other configurations. The output current of transistor T 1  drives the third terminal  18  of transistor T 4 , while the output current of transistor T 2  drives the third terminal  19  of transistor T 5 . The second terminals  16 ,  17  of transistors T 4  and T 5  are controlled by voltage V bias  at terminal node  11 . V bias  at terminal node  11  is preferably chosen such that the voltage on transistors T 1  and T 2  does not exceed the breakdown voltages of these transistors. For example, V bias  at terminal node  11  is preferably set to −3 Volts. The outputs  12 ,  13  of T 4  and T 5  provide a differential output of the current switch. 
     Transistors T 1 , T 2  and T 3  are preferably fabricated in a high f t , low breakdown voltage technology. InP single HBTs (Heterojunction Bipolar Transistors) with InP substrates, InGaAs collectors and breakdown voltages of roughly 3V are particularly adequate. Other possible high f t , low voltage technologies for transistors T 1 , T 2  and T 3  include, but are not limited to, InP Single HBTs, thin collector InP Double HBTs, InP High Electron Mobility Transistors (HEMTs), InP Field-Effect Transistors (FETs), GaAs Metal-Semiconductor Field-Effect Transistors (MESFETs), Si Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) (designed for high unity current gain frequencies, low breakdown voltages), and thin collector SiGe HBTs. Thin collector technology is characterized by collectors with a thickness of less than 4000 angstroms. Those skilled in the art will recognize that there are several well known processes available to manufacture the variety of semiconductor devices that may be used in the first stage  3  of the present invention. One article of reference for the manufacture of the first stage  3  is C. H. Fields, M. Sokolich, S. Thomas, K. Elliott and J. Jensen, “Progress toward 100 GHz Logic in InP HBT IC Technology”, 2001, International Journal of High Speed Electronics and Systems, Vol. 11, No. 1 pages 217-243. 
     Transistors T 4  and T 5  are preferably Field-Effect Transistors (FETs) fabricated from a high breakdown voltage material such as GaN. Other possible high breakdown voltage technologies for transistors T 4  and T 5  include, but are not limited to, GaN FETs, GaN HBTs, thick collector InP DHBTs, Silicon Carbide based (SiC-based) transistors, and GaAs HBTs. Thick collector technology is characterized by collectors with a thickness greater than 4000 angstroms. Those skilled in the art will recognize that there are several well known processes available to manufacture the variety of semiconductor devices that may be used in the second stage  4  of the present invention. One article of reference for the manufacture of the second stage  4  is M. Micovic, N. X. Nguyen, P. Janke, W.-S. Wong, P. Hashimoto, L.-M. McCray, C. Nguyen, “GaN/AIGaN high electron mobility transistors with f t  of 110 GHz”, Feb. 17, 2000, Electronic Letters, vol. 36, no. 4, pages: 358-359. 
     The output compliance, or the maximum voltage output of the transistor during nominal operation, is limited by the safe breakdown operating margin of the transistor. As shown in FIG. 2, transistors T 4  and T 5  are preferably configured in a common gate/base cascode, and consequently the maximum operating frequency is determined by the common gate/base cutoff frequency which is typically much higher than the common source/emitter operating frequency. 
     The resulting current switch can be used to obtain higher output voltage compliance at higher switching frequency than could be obtained otherwise. 
     A preferred embodiment of a current switch in accordance with the present invention is shown in FIG.  3 . Current source  2  is represented by four legs, each comprising a transistor Q 2  and a resistor R 0  such that the current is equally divided between the four legs of the current source  2 . One skilled in the art will appreciate that current source  2  may take on many forms well known in the art. 
     Turning to FIG. 4, the results of a computer simulation of the current switch of FIG. 3 is shown. In this simulation transistors M 79  and M 0  were modeled as 1 millimeter wide GaN FETs with a 0.1 micrometer gate length. Transistors Q 0 , Q 1 , and Q 2  were modeled as InP HBTs with 1 micrometer wide by 5 micrometers long emitters. The GaN FETs modeled in the simulation had their threshold voltage parameter set to −3 Volts. For simulation purposes, resistors R L  were electrically coupled to output nodes  12  and  13  at one end and a voltage supply V L  at the other to provide a load for the differential current switch. In the simulation, R L  was chosen to be 1350Ω and V L  was chosen to be 30 Volts. The input voltages applied to nodes  9  and  10  varied between −0.8 Volts and −1.5 Volts. A voltage of −3 Volts was applied to nodes  11  and  20 . A voltage of −1.8 Volts was applied to node  8 . The top trace  25  of FIG. 4 represents the output voltage at terminal  13  of FET M 0  when driving a load resistance electrically connected to terminal  13 . The next trace  27  shows the collector voltage  15  of HBT Q 1 . The final trace  29  shows the base voltage  10  of HBT Q 1 . FIG. 4 shows how the voltage across high unity current gain frequency HBT Q 1  is reduced to safe levels, less than the breakdown voltage of Q 1 , and the maximum frequency of FET M 0  is realized. In view of the symmetry of the circuit, the same observations would apply to FET M 79  and HBT Q 0 . 
     In FIG. 5 a single ended current switch in accordance with the present invention. In FIG. 5, transistor Q 1  is used to provide a bias reference to Q 0 . The value of the bias, V DC , is chosen to be in between the maximum and minimum input levels into node  9 . In a computer simulation of the single ended current switch of FIG. 5, the results of which are shown in FIG. 6, the reference level V DC  is chosen to be −1.2 Volts. In the case of a single ended current switch, only one transistor M 79  is necessary in the second stage  4 . The transistors are modeled in the computer simulation with the same parameters as were set in the model of the differential current switch as discussed above. The voltage levels at node  9  range between −0.8 Volts and −1.5 Volts. A 1350Ω resistor R L  is electrically connected between node  12  and a 30 Volt voltage source V L  in order to provide a load to the single ended current switch in the simulation. The voltage V bias  provided at node  16  is −3 Volts. The current source  2  is the same as the current source used in the simulation of the differential current switch discussed above. The GaN FET M 79  modeled in the simulation had its threshold voltage parameter set to −3 Volts. 
     FIG. 6 shows the results of the computer simulation using the embodiment of FIG. 5 with the values as discussed above. The top trace  35  represents the output voltage at terminal  12  of FET M 79  when driving a load resistance electrically connected to terminal  12 . The next trace  37  shows the collector voltage  14  of HBT Q 0 . The final trace  39  shows the base voltage  9  of HBT Q 0 . FIG. 6 shows how the voltage across high unity current gain frequency HBT Q 0  is reduced to safe levels, less than the breakdown voltage of Q 0 , and the maximum frequency of FET M 79  is realized. 
     Turning to FIG. 7, a digital-to-analog converter (DAC)  600  with two R-2R ladder networks  605 ,  607  in accordance with the present invention is shown. The DAC  600  comprises a plurality of differential current switches  602  in accordance with the present invention and two R-2R resistive ladder networks  605 ,  607  to generate the analog voltage signal responsive to a digital input signal. Each differential current switch comprises a current source  2 , a first stage  3  and a second stage  4  as previously described in reference to FIGS. 2 and 3. The operation of the DAC  600  is principally the same as the operation of DAC  100  of FIG.  1 . The added benefit of DAC  600  is that the voltage supplied to V DAC  is no longer required to be a low voltage of approximately −1 Volt, but rather can be higher voltages greater than 5V. Typical voltages applied to V DAC  are preferably 20 to 40 volts or higher. Each output  12   a - 12   n  from each current switch is electrically connected to one R-2R ladder network  605 , while each output  13   a - 13   n  from each current switch is electrically connected to the other R-2R ladder network  607 . The sum of the currents at each node drive the R-2R resistive ladder network. 
     FIG. 8 shows the computer simulation results of the DAC shown in FIG.  7 . In the computer simulation the value R in the R-2R ladder networks was chosen to be 500Ω. The differential current switches were modeled very much like the differential current switches in FIG.  3 . Transistors T 4  and T 5  were modeled as 1 millimeter wide GaN FETs with a 0.1 micrometer gate length. Transistors T 1 , T 2 , and T 3  were modeled as InP HBTs with 1 micrometer wide by 5 micrometers long emitters. The GaN FETs T 4 , T 5  modeled in the simulation had their threshold voltage parameter set to −3 Volts. The input voltages applied to nodes  9   a - 9   n  and  10   a - 10   n  varied between −0.8 Volts and 1.5 Volts. A voltage of −3 Volts was applied to nodes  11 ′ and  20 ′. A voltage of −1.8 Volts was applied to nodes  8   a - 8   n . A voltage of 30 Volts was applied at V DAC , terminal node  611 . The current through each of the current sources  2  is 26 mA. The curve  41 , in FIG. 8, depicts the voltage at the output  603  of the DAC  600 . The curve  43  depicts the voltage at the output  609  of the DAC  600 . As is evident from FIG. 8, the two outputs  603 ,  609  of the DAC  600  are a complement of each other. 
     The desired output voltage swing can be adjusted by adjusting the currents though the current sources  2 . The maximum output voltage swing that can be obtained depends on the voltage swing of the voltage applied to V DAC  terminal node  611 . In the case of the present example the maximum output voltage swing is approximately 27 Volts. 
     One skilled in the art will appreciate that there are a variety of different DACs that use current switches in which the current switch of the present invention may be used. For example, the current switch as shown in FIG. 5 could be used with a single R-2R ladder network in a digital to analog converter. 
     Turning to FIGS. 9 a  and  9   b  another embodiment of the present invention is depicted. This configuration results in a four terminal composite switching device able to simultaneously provide both high f t , and high voltage operation. This device is comprised of at least two stages. The first stage  3  comprises at least one semiconductor device preferably fabricated from a high f t , low breakdown voltage technology. The second stage  4  comprises of at least one semiconductor device preferably fabricated from a breakdown voltage technology which is higher than the breakdown voltage technology used in the first stage  3 . 
     FIG. 9 a  is a generic representation of a four terminal composite switching device. The square boxes T 1  and T 4  are generic representations of semiconductor devices which may be of any type. Transistor T 1  is preferably fabricated in a high f t , low breakdown voltage technology. InP single HBTs with InGaAs collectors and breakdown voltages of roughly 3 Volts are particularly adequate. Transistor T 4  is preferably a FET fabricated from a high breakdown voltage material such as GaN. The same technologies that are mentioned above for use in the first  3  and second  4  stages of the current switches may also be used in the first  3  and second  4  stages of the four terminal composite switching devices. 
     FIG. 9 b  provides a more detailed representation of a four terminal composite switching device, where Q 0  is an InP single HBT with an InGaAs collector and M 79  is a GaN FET. The operation of the four terminal composite switching device is herein described in relation to FIG. 9 b  as an example. In general the voltage at node  93  is limited to the difference between V bias  and the threshold voltage of M 79 . Thus, the source voltage V ee  of Q 0  is preferably chosen such that the voltage across Q 0  is within a safe operating range for that transistor. For example, by choosing the threshold voltage for M 79  to be −3 Volts and supplying −3 Volts at terminal node  11 , the voltage at node  93  is limited to a small voltage, approximately 0 volts. However, a higher voltage than the breakdown voltage of the first stage  3  can be applied to the output  95  of the second stage  4 , such that the four terminal composite switching device is able to provide both high f t  and high voltage operation simultaneously. 
     One skilled in the art will appreciate that any number of composite devices may be integrated to form larger circuits enabling a variety of applications. In addition, any number of devices, for example resistors, may be inserted in between the first 3 and second stage  4  of the four terminal composite switching device without changing the ability of the four terminal composite switching device to provide for both high f t  and high voltage operation simultaneously. The four terminal composite switching device may be incorporated into a high bias voltage cascade amplifier. 
     Having described the invention in connection with certain preferred embodiments thereof, modification will now certainly suggest itself to those skilled in the art. As such, the invention is not to be limited to the disclosed embodiments except as is specifically required by the appended claims.