Abstract:
A multi-mode modular pulse-width-modulator capable of outputting low-speed and high-speed control signals is presented. The operation of the modulator is determined by parameters that are stored within the modulator and provide for high-speed updating and control capability in response to changes in voltage or current. In one mode, an update and control signal is generated based on timing parametric data stored in a local memory. In a second mode, an update and control signal is generated based on timing parametric data that provided by an external input device. Furthermore, control variables are also stored locally which control the position of switches, which alter signal paths within the modulator.

Description:
RELATED APPLICATION 
     This application relates to commonly assigned: 
     U.S. patent application Ser. No. 09/406,648, entitled, MODULAR MASTER-SLAVE POWER SUPPLY CONTROLLER, filed, Sep. 22, 1999; and 
     U.S. patent application Ser. No. 09/781,473 entitled DUAL-MODE PULSE-WIDTH MODULATOR FOR POWER CONTROL APPLICATIONS, filed Feb. 12, 2001. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of control systems. More specifically, this invention relates to modular power control systems using pulse-width control modulators. 
     BACKGROUND OF THE INVENTION 
     FIG. 1 illustrates a conventional switching power module. As illustrated, an alternating (AC) voltage is input into power conversion module  110 , which produces a direct (DC) output voltage, Vo. Output voltage, Vo, is input to feedback compensation control circuit  150 , which monitors the value of output voltage Vo and adjusts the internal parameters of power conversion module  110  to maintain Vo relatively constant. The processing of feedback compensation control circuit  150  is well known in the art and may be implemented in special-purpose circuits, such a Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs). 
     The use of Application Specific Integrated Circuits to implement the control of power supplies is well known in the art. ASICs can perform the functions of a variety of discrete components on a single Integrated Circuit (IC). This is advantageous as the size of the controller and the overall size of the power supply can be reduced. Also, in large quantity, the cost of an ASIC is significantly less than the cost of discrete components that are required to perform the same functions. Hence, the overall cost and physical size of power supply units is reduced when ASIC technology is employed. 
     ASICs may be custom-made for the application or may be “off-the-self” components. Custom-made ASICs are expensive and time-consuming to develop. Since the initial development cost for custom-made ASICs may be high, these devices are used in high volume applications. In such cases the development costs can be spread-out over the price of all the units sold. In addition, custom-made ASICs are typically designed to operate with a particular type of component or a component manufactured by a particular manufacturer. 
     Off-the-shelf ASICs are typically preprogrammed with known functions and interface to external devices, components or other hardware, in order to use them in a designated application. The external components interface the off-the-shelf ASIC to other devices or components. The use of external components, however, is disadvantageous as their use increases the cost and the size of the power supply. It is further disadvantageous when components are changed as the interface and the ASIC may also have to be changed. 
     One method of creating power supply controllers using off-the-shelf components is to distribute processing among generic component blocks. The generic component blocks can consist of programmable micro-controllers that communicate operational commands to control devices, such as Pulse Width Modulators (PWM), over a data bus. Pulse Width Modulators are routinely included as peripherals in micro-controller based integrated circuits. Timing parameters, such as frequency, i.e., period, on-time, off-time, etc., which are used to control the output voltage level are stored in registers accessible by a micro-controller. Power supply controllers are well known in the art. 
     FIG. 2 illustrates a conventional modular digital power supply controller  150  comprised of a master unit  200  and at least one slave unit  210   a ,  210   b . As illustrated, master unit  200  is composed of processor  202 , memory  204  and communication interface  206 . Analog-to-digital (A/D) converter  201  may optionally be included for conversion of analog signals to digital form for processing by processor  201 . Slave units  210   a ,  210   b  are composed of communication interface  222 , PWM generator  218 , registers  212  and micro-controller or DSP  214 . Analog-to-digital (A/D) converter  216  may optionally be included for conversion of analog signals to digital form for processing. PWM generators  218  are routinely included as peripherals in micro-controller integrated circuits. In such cases, timing parameters, e.g., frequency, on-time, off-time, etc., can be are stored in register  212 , These values can be set in register  212  by local micro-controller  214  or remotely by processor  202  over communication link  208 . 
     Remotely controlled operation of PWM is, however, limited because of bandwidth constraints. In voltage-mode control applications, the control of power module  150 , of FIG. 1, by PWM  218  is in the order of few hundred or a few thousand hertz. In this case, the rate of updating the register content is relatively low, hence, the limited bandwidth of micro-controller  202 , such as, 80C51-based micro-controllers, or data bus  208  is sufficient for updating the registers stored, for example, in slave unit  210   a . On the other hand, in current-mode control applications the PWM output is required to respond within a few hundred nanoseconds. Being bandwidth limited, the earlier described distributed power supply controller cannot respond within such a short time period. Hence, there is in a need in the art to provide a means for high-speed updating of pulse width modulator parameters that does not require expensive high-speed components, control signals or increased bandwidth 
     SUMMARY OF THE INVENTION 
     A multi-mode pulse width modulator (PWM) capable of exercising control signals in voltage-controlled, i.e., low-speed, and current-controlled, i.e., high-speed, power supply controllers is presented. The pulse width modulator, responsive to initial or slowly updated control signals can initiate control signals that provide either a slow-speed or high-speed changes. In one aspect of the invention, where the PWM is in communication with a relatively slow processor over a band-limited digital communication link, the PWM can internally generate a high-speed control signal in response to a rapidly changing input signal. In this aspect of the invention, the modular construction of power supply controller provides flexibility and interchangeability without incurring the cost of custom-made integrated circuit development. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 illustrates a block diagram of a conventional switching power supply; 
     FIG. 2 illustrates a conventional distributed power supply feedback compensation control circuit; 
     FIG. 3 a  illustrates a block diagram of an exemplary multi-mode pulse width modulator in accordance with the principles of the invention; 
     FIG. 3 b  illustrates a detailed block diagram of an exemplary multi-mode pulse width modulator in accordance with the principles of the invention; 
     FIG. 4 illustrates timing diagrams of signal waveforms generated by the exemplary pulse width modulator depicted in FIG. 3 b  operating in a fixed frequency voltage-control mode; 
     FIG. 5 illustrates timing diagrams of signal waveforms generated by the exemplary pulse width modulator depicted in FIG. 3 b  operating in a variable frequency current-control mode; 
     FIG. 6 illustrates timing diagrams of signal waveforms generated by the exemplary pulse width modulator depicted in FIG. 3 b  operating in a variable frequency voltage-control mode; 
     FIG. 7 illustrates timing diagrams of signal waveforms generated by the exemplary pulse width modulator depicted in FIG. 3 b  operating in a fixed frequency current-control mode; and 
     FIG. 8 illustrates another exemplary embodiment of a remote PWM in accordance with the principles of the present invention. 
     It is to be understood that these drawings are solely for purposes of illustrating the concepts of the invention and are not intended as a definition of the limits of the invention. It will be appreciated that the same reference numerals, possibly supplemented with reference characters where appropriate, have been used throughout to identify corresponding parts. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 a  illustrates a block diagram of an exemplary remote multi-mode pulse width modulator (PWM)  210   a  in accordance with the principles of the present invention. In this illustrative block diagram, command signals are input across a network (not shown) and received by communication interface  222  and stored in register unit  212 . Input command may, be timing parameters, configuration commands, etc., which configure remote PWM module  210   a  into a known configuration. In one aspect, remote PWM module  210   a  can be configured into a current mode processing  301  or a voltage mode processing  302 . Both current mode processing  301  or voltage mode processing  302  are capable of operating as in variable frequency or fixed frequency modes. In the current mode processing latching device  335  is directed to select between variable frequency current and fixed frequency current operation as will be explained in more detail with regard to FIG. 3 b . In the voltage mode processing multiplexer/switch  313  (i.e., Mux_ 2 ) is directed to select between variable frequency voltage and fixed frequency voltage operation by control signal  312 , which may be stored in register unit  212 , and will be explained in more detail in regard to FIG. 3 b . Multiplexer/switch Mux_ 4 ,  317  is directed to select between the cur-rent mode operation or the voltage mode operation by control signal  316 . Multiplexer/switch Mux_ 3 ,  315  is directed to select between the output of Mux_ 4   317  or the output of the intervening inverter stage by control signal  314 . 
     FIG. 3 b  illustrates an exemplary embodiment  300  of a multi-mode pulse width modulator (PWM)  210   a  in accordance with the principles of the present invention. In this exemplary embodiment control signals  310 ,  312 ,  314 ,  316  and  318 , respectively labeled CMux_ 1 , CMux_ 2 , CMux_ 3 , CMux_ 4  and CMux_ 5 , are stored in control register  212 . Control signals CMux_ 1  through CMux_ 5  are used to program the functionality of PWM  300  by controlling signal paths, i.e., the state of multiplexers/switches  311 ,  313 ,  315 ,  317  and  319 , respectively, through PWM  300 . In one aspect of the invention, control signals Mux_ 1 , Mux_ 2 , Mux_ 3  Mux_ 4  and Mux_ 5  may be set by an external micro-controller  212  (not shown) via communication link  208  and interface  222 . In a second aspect of the invention, and the one discussed herein, control signals CMux_ 1 , CMux-_ 2 , CMux_ 3 , CMux_ 4 , and CMux_ 5  are pre-stored in registers or memory  212 . In this case, the values in the registers or memory  212  can be pre-set by an external micro-controller or may be pre-loaded by pre-programming memory  212 . 
     Each of the individual modes of operation of a multi-mode PWM will now be disclosed with regard to the illustrated exemplary circuit shown in FIG. 3 b . In fixed frequency voltage-control mode, generator  330 , receives at least one known value,  331 , which is stored in control register  212 , and generates a signal, herein, labeled Count_per. In an alternate embodiment signal Count_per can be synchronized to a fixed external signal (not shown). Pulse generator  332 , receiving signal Count_per generates signal Pulsegen_ 1  responsive to the transitions of signal Count_per. Signal Pulsegen_ 1 , hence, is representative of a transition of signal Count_per from one fixed state to a second fixed state. Pulse generator  332 , for example, may be a “one-shot” pulse generator that generates a pulse upon detection of transition of an input signal. In one embodiment of the invention, pulse generator  332  can generate signal Pulsegen_ 1  on a leading edge of signal Count_per. In an alternate embodiment, pulse generator  332  can generate signal Pulsegen_ 1  on a trailing edge of signal Count_per. 
     Signal Pulsegen_ 1  is next input to multiplexer/switch  319 , (i.e., Mux_ 5 ). In this mode of fixed frequency voltage operation, Mux_ 5 ,  319  is directed by control signal  318  (CMux_ 5 ) to select input signal Pulsegen_ 1 . The output of Mux_ 5 ,  319  is then input to generator  334 . 
     Generator  334  receiving at least one input value  333  stored in control register  212  and the output of Mux_ 5 ,  319  generates signal Count_del. Generator  334  generates signal Count_del synchronously with the output of Mux_ 5 ,  319 , i.e., signal Pulsegen_ 1 , and with a known pulse width set by the received at least one known value stored in register  212 . Signal Count_del is next input to Pulse generator  336 , which generates a pulse signal, labeled Pulsegen_ 2  responsive to the transition of signal Count_del. In one embodiment of the invention, pulse generator  336  can generate signal Pulsegen_ 2  on a tailing edge of signal Count_del. Alternatively, pulse generator  336  can generate signal Pulsegen_ 2  on a leading edge of signal Count_del. Similar, to generator  332 , generator  336  may be a “one-shot” generator. 
     Signal Pulsegen_ 2  is then input to multiplexer/switch MUX_ 2 ,  313 , which under to the direction of control signal CMUX_ 2 ,  312  directs signal Pulsegen_ 2  to pulse generator  338 . Pulse generator  338  next generates signal Count_pulse in response to the output of Mux_ 2 ,  313  and with a known pulse width determined by at least one known value  337  stored in register  212 . 
     Signal Count_pulse is next applied to multiplexer/switch Mux_ 4 ,  317 . Under the direction of control signal CMUX_ 4 ,  316 , switch Mux_ 4 ,  317  is directed, in this case, to pass signal Count_pulse to multiplex/switch Mux_ 3 ,  315 . 
     In one aspect of invention, multiplex/switch Mux_ 3 ,  315  can be directed by control signal CMux_ 3 ,  314  to select signal Count-pulse as the output of PWM  210   a  (i.e., signal PWMOUT  350 ). In another aspect of the invention, signal Count_pulse can be inverted by inverter  344  and multiplexer/switch MUX_ 3 ,  315  can be directed by control signal CMUX_ 3 ,  314  to select an inverted form of signal Count_pulse as representative of signal PWMOUT  350 . Signal PWMOUT  350  controls the switching frequency of PWM  210   a.    
     FIG. 4 illustrates timing relations among the signals used to process fixed frequency voltage-control mode of PWM  300 . In this exemplary timing diagram, signal Count_per, represented as signal  330   a , is a square wave having a known, fixed period, i.e., frequency, represented as T per . Period T per  is representative of at least one known value stored in register  212 . Signal Pulsegen_ 1 , represented as signal  332   a , is generated responsive to the transitions of signal Count_per. Signal  332   a  can be generated, as illustrated, on a leading edge of signal  330   a , or, as would be understand in the art, can be generated on a tailing edge of signal  330   a . Signal Count_del, represented as signal  334   a , is generated responsive to the transitions of signal  332   a  and has a pulse duration representative of at least one known value, represented as T del . The at least one known value representative of duration, T del , is stored in register  212 . In one embodiment of the invention can be loaded through communication interface  222  over communication link  208 . In a second embodiment of the invention, duration T del  can be pre-loaded in register  212 . 
     Signal Pulsegen_ 2 , represented as signal  336   a , is generated responsive to the transitions of signal Count_del. In this illustrative example, signal  336   a  is generated on a trailing edge of signal  334   a . As would be understood, signal  336   a  may alternatively be generated responsive to a leading edge of signal  334   a.    
     Signal Count_pulse, represented as signal  338   a , is next generated responsive to the transitions of signal  336   a  and has a pulse duration represented as T pulse , which is representative of at least one value stored in register  212 . Duration T pulse  in one aspect of the invention can be loaded through communication interface  222  over communication link  208 . In a second aspect of the invention, duration T pulse , can be pre-loaded in register  212 . 
     Signal PWMOUT, as represented by signal  350   a , in this illustrative example, corresponds to the illustrated signal Count_pulse  338   a . In a second aspect of the invention, signal PWMOUT  350  may be selected as an inverted signal  338   a , which is illustrated as signal  350   b.    
     Return now to FIG. 3 b , the variable frequency current mode of operation of the exemplary PWM  300  illustrated is more fully disclosed. In this mode, a digital representation of a reference voltage is stored in control register  212 . As previously discussed, the value stored can be pre-stored in register  212  or can be received via communication link  208  and stored in register  212 . The stored digital representation of reference voltage is input to Digital-to-Analog (D/A) converter  340 . D/A converter, as is known, converts a digitally represented value into a comparable analog value using known scaling factors. Details of D/A conversion are well known in the art and need not be discussed herein. The converted output voltage level of D/A converter, referred to as Vref, is then input to comparator  342 . 
     Signal  320 , labeled herein as V i , is also input into comparator  342 . Signal V i , is representative of a current passing through a control transistor. Signal  320  is a high-speed signal as it is changing on each cycle and must be evaluated and processed in a short period of time. 
     The output of comparator  342  is next input to pulse generator  346 . Pulse generator  346  generates signal Pulsegen_ 3 , when, in this illustrated case, signal V i    320  is greater than reference voltage, Vref. The output of comparator  342  is also input to inverter  348 , which is used to reverse the sense of the input signal. The output of inverter  348  is input to pulse generator  345 , which generates signal Pulsegen_ 4 . 
     Signals Pulsegen_ 3  and Pulsegen_ 4  are next applied to multiplexer/switcher,  311 , labeled Mux_ 1 . Control signal, CMUX_ 1 ,  310  determines whether signal Pulsegen_ 3  or Pulsegen_ 4  is selected for further processing. The signal selected by multiplexer/switch  311  is next applied to multiplexer/switch  313 , (i.e., Mux_ 2 ). Mux_ 2 ,  313 , is directed, in this current mode of operation, by control signal CMux_ 2 ,  312  to select the output of Mux_ 1 ,  311 . 
     The selected output of Mux_ 1 ,  311 , is then applied to generator  338 , which generates signal Count_pulse as previously discussed. Signal Count_pulse is next applied to multiplexer/switch Mux_ 4 ,  317 . Under the direction of control signal CMUX_ 4 ,  316 , switch Mux_ 4 ,  317  is directed to pass signal Count_pulse to multiplex/switch Mux_ 3 ,  315 . As previously discussed, Mux_ 3 ,  315  is directed by control signal CMux_ 3 ,  314 , to select signal Count_pulse or its inverse as the output signal PWMOUT  350   a.    
     FIG. 5 illustrates exemplary timing signals in accordance with one embodiment of variable frequency current-mode operation of the circuit illustrated in FIG. 3 b . In this embodiment, reference voltage, Vref,  510 , is illustrated as a steady reference value, which may be stored in digital form in register unit  212 . Voltage V i , labeled  320   a , is illustrated as a voltage having a triangular waveform, which is representative of a raising and falling voltage as a power transistor is turned off and on. 
     Signal Pulsegen_ 3 , represented as signal  546   a , is generated, in this example, when voltage V i ,  320   a , is greater than reference voltage, Vref,  510 . With appropriate selection by control signals CMux_ 1 ,  310  and CMux_ 2 ,  312 , signal Pulsegen_ 3  is applied to pulse generator  338  through multiplex/switches Mux_ 1 ,  311  and Mux_ 2 , respectively. Pulse generator  338 , as previously discussed, generates signal Count_pulse, represented as signal  338   a , responsive to the input signal and having a pulse duration represented as T pulse . Signal Count_pulse  338   a , in this illustrated case, is selected as the output signal PWMOUT  350   a.    
     Returning now to FIG. 3 b , the operation of variable frequency voltage mode of the exemplary PWM  300  illustrated is more fully discussed. In this aspect of the invention, signal Count_pulse is concurrently applied to Mux_ 4 ,  317  and generator  362 . Generator  362  generates a signal, Pulsegen_ 5 , responsive to the transitions of signal Count_pulse. Signal Pulsegen_ 5  is next applied to multiplexer/switch Mux_ 5 ,  319 , which is directed by control signal CMux_ 5 ,  318 , to select signal Pulsegen_ 5  as an input signal to generator  334 . Generator  334 , in this case, generates signal Count_del, responsive to the input signal and having a pulse width determined by the at least one value  333 , which is stored in register/memory unit  212 . Signal Count_del is next input into generator  336 , which generates signal Pulsegen_ 2 . as previously discussed. Signal Pulsegen_ 2  is then applied to multiplexer/switch  313 , which is directed by control signal CMux_ 2 ,  312  to select signal Pulsegen_ 2 , in this case. The selected signal Pulsegen_ 2  is then applied to generator  338  to generate signal Count_pulse. As discussed previously, signal Count_pulse is then selected by multiplexer/switch  317  to be representative of the output of PWM  210   a , i.e., signal  350   a.    
     FIG. 6 illustrates exemplary timing signals in accordance with the variable frequency voltage-mode operation of the exemplary circuit illustrated in FIG. 3 b . In this example, signal Pulsegen_ 5 , represented at  362   a  is generated in relation to the transitions of signal Count_pulse,  338   a . In this case, Pulsegen_ 5  is generated on the tailing edge of signal Count_pulse,  338   a . It will be appreciated that signal Pulsegen_ 5  could be similarly generated on the leading edge of signal Count_pulse. Signal Count_del  334   a  is next generated in relation to signal Pulsegen_ 5 . Signal Count_del  334   a , as previously discussed, has a known pulse width, represented as T del , which is determined from information stored in register/memory unit  212 . Signal Pulsegen_ 2   336   a  is next generated in response to the transitions of signal Count_del  334   a . Signal Pulsegen_ 2  is then applied to generator  338 , which generates signal Count_pulse with a known pulse width. 
     Return now to FIG. 3 b , the fixed frequency current mode of operation of exemplary PWM  300  is more fully disclosed. In this operational mode, signal Count_del is applied to a clock input of latching device  335  and the output of Mux_ 1 ,  311 , is applied to a reset input of latching device  335 . A second input of latching device is held at a logic high value. The output of latching device  335  is then selected as the output of the PWM  210  by Mux_ 4 ,  317  and Mux_ 3 ,  315 . 
     FIG. 7 illustrates an exemplary timing diagram in accordance with the principles of the invention. In this illustrative example, when Vin  320   a  exceeds a reference voltage Vref,  510 , the signal Pulsegen_ 4 ,  348   a , is selected by Mux_ 1 ,  311 . The output is then applied to the reset port of latching device  335 , which causes the output of latching device  335  to be set to zero. However, at the next clock pulse, as determined by signal Count_del, the output of latching device is reversed, as is shown here as a logical “high” value. The output of latching device  335  is next applied to Mux_ 4 ,  317  which controlled by control signal C_Mux_ 4 , selects the output of latching device  335  as the output of PWM  210 , i.e., signal  350 . 
     Although the multi-mode PWM depicted in FIG. 3 b  has been shown capable of performing both fixed- and variable- frequency current and voltage operation, it would be appreciated that a voltage only or current only PWM can be constructed by selectively including only those components applicable to a specific mode of operation in the exemplary multi-mode PWM shown in FIG. 3 b . Accordingly, fixed-frequency only or variable frequency only modes of operations may be constructed in accordance with the principles of the invention by removing components from the exemplary multi-mode PWM shown in FIG. 3 b . FIG. 8 illustrates a second exemplary embodiment of a multi-mode PWM  800  is accordance to the principles of the present invention. In this embodiment, PWM  800  is operable for fixed and variable voltage control and variable current control operation only. 
     Although the invention has been described and pictured in a preferred form with a certain degree of particularity, it is understood that the present disclosure of the preferred form, has been made only by way of example, and that numerous changes in the details of construction and combination and arrangement of parts may be made without departing from the spirit and scope of the invention as hereinafter claimed. For example, it will be appreciated that in one aspect of the invention, control signals or variables CMux_ 1  through CMux_ 5 , and known time values or variable T per , T del , and T pulse  can be set by controller  200  by an internal bus when register  212  and controller  202  are fabricated on the same chip or wafer. Furthermore, control signals CMux_ 1  through CMux_ 5 , and known time values T per , T del , and T pulse  can be preset in register  212 . 
     It is expressly intended that all combinations of those elements and/or method steps which perform substantially the same function is substantially the same way to achieve the same results are within the scope of the invention. Substitutions of elements from one described embodiment to another are also fully intended and contemplated.