Abstract:
A memory device capable of rewriting data with smaller current consumption than a case of feeding a rewrite current every bit line is obtained. This memory device comprises a first bit line and a second bit line having a current path independently of the first bit line, and renders write current paths of the first and second bit lines in common. Thus, the memory device can rewrite data with smaller current consumption as compared with the case of feeding the rewrite current every bit line.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a memory device, and more specifically, it relates to a memory device such as a magnetic memory device including storage elements exhibiting a ferromagnetic tunnel effect or the like.  
           [0003]    2. Description of the Background Art  
           [0004]    An MRAM (magnetic random access memory), i.e., a nonvolatile memory recording data through magnetism, is known in general. This MRAM is disclosed in Nikkei Electronics, 1999. 11. 15 (No. 757), pp. 49-56 or the like in detail.  
           [0005]    [0005]FIGS. 7 and 8 are schematic diagrams for illustrating the structure of a storage element  110  forming the MRAM disclosed in the aforementioned literature. Referring to FIG. 7, the storage element  110  of the conventional MRAM comprises a ferromagnetic layer  101 , another ferromagnetic layer  103  and a non-magnetic layer  102  arranged between the ferromagnetic layers  101  and  103 .  
           [0006]    The ferromagnetic layer  101  is harder to invert than the ferromagnetic layer  103 . The term “ferromagnetism” denotes such magnetism that magnetic atoms or free atoms of a metal parallelly align magnetic moments due to positive exchange interaction for forming spontaneous magnetization, and a substance exhibiting such ferromagnetism is referred to as a ferromagnetic substance. The ferromagnetic layers  101  and  103  consist of such a ferromagnetic substance. In general, the non-magnetic layer  102  is formed by a GMR (giant magnetoresistance) film employing a metal. A TMR (tunneling magnetoresistance) film employing an insulator has recently been developed as the non-magnetic layer  102 . The TMR film advantageously has larger resistance than the GMR film. More specifically, the MR ratio (resistance change) of the GMR film is on the 10% mark, while that of the TMR film is at least 20%. The storage element  110  consisting of the TMR film is hereinafter referred to as a TMR element  110 .  
           [0007]    The storage principle of the conventional MRAM employing the TMR element  110  is now described with reference to FIGS. 7 and 8. First, the state where the directions of magnetization of the two ferromagnetic layers  101  and  103  are identical to each other (parallel) is associated with data “0”, as shown in FIG. 7. The state where the directions of magnetization of the two ferromagnetic layers  101  and  103  are opposite to each other (antiparallel) is associated with data “1”, as shown in FIG. 8. The TMR element  110  exhibits small resistance (R 0 ) when the directions of magnetization are parallel, while exhibiting large resistance (R 1 ) when the directions of magnetization are antiparallel. The MRAM determines whether the data is “0” or “1” through the property of the TMR element  110  exhibiting different resistance values in response to the directions of magnetization.  
           [0008]    [0008]FIG. 9 is a block diagram showing the overall structure of a conventional MRAM  150  having memory cells each formed by a single TMR element and a single transistor. The structure of the conventional MRAM  150  is now described with reference to FIG. 9.  
           [0009]    A memory cell array  151  is formed by arranging a plurality of memory cells  120  in the form of a matrix (FIG. 9 shows only four memory cells  120 , in order to simplify the illustration). Each memory cell  120  is formed by a single TMR element  110  and a single NMOS transistor  111 .  
           [0010]    In the memory cells  120  arranged in a row direction, the gates of the NMOS transistors  111  are connected to common read word lines RWL 1  to RWL n . In the memory cells  120  arranged in the row direction, further, rewrite word lines WWL 1  to WWL n  are arranged on first ferromagnetic layers of the TMR elements  110 .  
           [0011]    In the memory cells  120  arranged in a column direction, first ferromagnetic layers of the TMR elements  110  are connected to common bit lines BL 1  to BL n .  
           [0012]    The read word lines RWL 1  to RWL n  are connected to a row decoder  152 , and the bit lines BL 1  to BL n  are connected to a column decoder  153 .  
           [0013]    Externally specified row and column addresses are input in an address pin  154 . The address pin  154  transfers the row and column addresses to an address latch  155 . In the row and column addresses latched in the address latch  155 , the row address is transferred to the row decoder  152  through an address buffer  156 , and the column address is transferred to the column decoder  153  through the address buffer  156 .  
           [0014]    The row decoder  152  selects a read word line RWL corresponding to the row address latched in the address latch  155  from among the read word lines RWL 1  to RWL n , while selecting a rewrite word line WWL corresponding to the row address latched in the address latch  155  from among the rewrite word lines WWL 1  to WWL n . The row decoder  152  further controls the potentials of the read word lines RWL 1  to RWL n  and the rewrite word lines WWL 1  to WWL n  on the basis of a signal from a voltage control circuit  157 .  
           [0015]    The column decoder  153  selects a bit line BL corresponding to the column address latched in the address latch  155  from among the bit lines BL 1  to BL n , while controlling the potentials of the bit lines BL 1  to BL n  on the basis of a signal from another voltage control circuit  158 .  
           [0016]    Externally specified data is input in a data pin  159 . The data pin  159  transfers the data to the column decoder  153  through an input buffer  160 . The column decoder  153  controls the potentials of the bit lines BL 1  to BL n  in correspondence to the data.  
           [0017]    Data read from an arbitrary memory cell  120  is transferred from any of the bit lines BL 1  to BL n  to a sense amplifier group  161  through the column decoder  153 . The sense amplifier group  161  is formed by current sense amplifiers. The data determined by the sense amplifier group  161  is output from an output buffer  162  through the data pin  159 .  
           [0018]    A control core circuit  163  controls the aforementioned operations of the circuits  152  to  162 .  
           [0019]    A write (rewrite) operation and a read operation of the conventional MRAM  150  having the aforementioned structure are now described.  
           [0020]    (Write Operation)  
           [0021]    In the write operation, the MRAM  150  feeds orthogonal currents to the selected rewrite word line WWL and the selected bit line BL. Thus, data can be rewritten only in the TMR element  110  located on the intersection between the rewrite word line WWL and the bit line BL. More specifically, the currents flowing through the rewrite word line WWL and the bit line BL form magnetic fields, so that the sum (composite field) of the two magnetic fields acts on the TMR element  110 . The directions of magnetization of the TMR element  110  change from “1” to “0”, for example, due to the composite field.  
           [0022]    The remaining TMR elements  110  located on intersections excluding the aforementioned one include those fed with absolutely no currents and those fed with only unidirectional currents. In each TMR element  110  fed with no current, no magnetic fields are formed and hence the directions of magnetization remain unchanged. In each TMR element  110  fed with only a unidirectional current, formed magnetic fields are insufficient in strength for inverting the directions of magnetization. Therefore, the directions of magnetization remain unchanged also in the TMR element  110  fed with only a unidirectional current.  
           [0023]    As hereinabove described, the MRAM  150  can write the directions of magnetization of the TMR element  110  located on the intersection between the selected bit line BL and the selected rewrite word line WWL as shown in FIG. 7 or  8  by feeding the currents to the bit line BL and the rewrite word line WWL corresponding to the selected address. Thus, the MRAM  150  can write data “0” or “1”.  
           [0024]    (Read Operation)  
           [0025]    In order to read the data written in the aforementioned manner, the MRAM  150  applies a voltage to the read word line RWL for rendering the NMOS transistor  111  conductive. In this state, the MRAM  150  determines whether the value of the current flowing through the bit line BL is larger or smaller than a reference current value, thereby determining “1” or “0”.  
           [0026]    In the case of the data “0” shown in FIG. 7, the directions of magnetization are parallel and hence the TMR element  110  exhibits a small resistance value (R 0 ). Therefore, the value of the current flowing through the bit line BL is larger than the reference current value. In the case of the data “1” shown in FIG. 8, on the contrary, the directions of magnetization are antiparallel and hence the TMR element  110  exhibits a larger resistance value (R 1 ) than that in the case shown in FIG. 7. Therefore, the value of the current flowing through the bit line BL is smaller than the reference current value.  
           [0027]    The aforementioned conventional MRAM  150  feeds the orthogonal currents to the selected rewrite word line WWL and the selected bit line BL in order to write data. If the TMR element  110  is refined, however, the directions of magnetization are so hard to invert that it is difficult to rewrite the data unless the values of the currents for writing are increased. Further, the conventional MRAM  150 , which must feed a current every bit line in order to simultaneously rewrite data in the memory cells  120  connected to the selected rewrite word line WWL, requires currents in a number corresponding to the product of the current necessary for each memory cell  120  and the number of the bit lines BL 1  to BL n . Thus, the MRAM  150  disadvantageously requires extremely large currents.  
           [0028]    The MRAM  150  also requires rewrite currents in a number corresponding to the product of a rewrite cycle and the number of the bit lines BL 1  to BL n  in order to continuously rewrite data stored in the memory cells  120  connected with the selected rewrite word line WWL. Thus, the MRAM  150  requires large currents also in this case.  
         SUMMARY OF THE INVENTION  
         [0029]    An object of the present invention is to provide a memory device capable of rewriting data with smaller current consumption as compared with a case of feeding a rewrite current every bit line.  
           [0030]    Another object of the present invention is to easily connect current paths of first and second bit lines with each other in the aforementioned memory device.  
           [0031]    In order to attain the aforementioned objects, a memory device according to a first aspect of the present invention comprises a first bit line and a second bit line having a current path independently of the first bit line, while rendering write current paths of the first bit line and the second bit line in common.  
           [0032]    The memory device according to the first aspect can rewrite data with smaller current consumption as compared with a case of feeding a rewrite current every bit line by rendering the rewrite current paths of the first bit line and the second bit line having the current path independently of the first bit line in common as hereinabove described.  
           [0033]    A memory device according to a second aspect of the present invention comprises a first bit line, a first pair line paired with the first bit line, a second bit line, a second pair line paired with the second bit line and a current path control circuit connecting either the first bit line or the first pair line and either the second bit line or the second pair line with each other in writing thereby connecting current paths of the first bit line and the second bit line with each other.  
           [0034]    The memory device according to the second aspect is provided with the current path control circuit connecting either the first bit line or the first pair line and either the second bit line or the second pair line with each other in writing thereby connecting the current paths of the first bit line and the second bit line with each other as hereinabove described, to be capable of feeding a rewrite current to the first and second bit lines through a single current path in writing. Thus, the memory device can rewrite data with smaller current consumption as compared with the case of feeding a rewrite current every bit line.  
           [0035]    The aforementioned memory device according to the second aspect preferably further comprises a first latch circuit for storing write data for the first bit line and a second latch circuit for storing write data for the second bit line, and connects the current path of the first bit line and the current path of the second bit line with each other on the basis of outputs from the first latch circuit and the second latch circuit. According to this structure, the memory device can easily connect the current paths of the first and second bit lines with each other through the first and second latch circuits.  
           [0036]    In this case, the current path control circuit preferably includes a logic circuit operating on the basis of the outputs from the first latch circuit and the second latch circuit and a switching element on-off controlled on the basis of an output from the logic circuit. According to this structure, the memory device can easily connect the current paths of the first and second bit lines by on-off controlling the switching element. In this case, further, a write enable signal line may be connected to an input terminal of the logic circuit. According to this structure, the memory device can easily control the output of the logic circuit through the write enable signal line.  
           [0037]    In the aforementioned memory device according to the second aspect, a memory cell including a storage element exhibiting a magnetoresistance effect is preferably connected to at least the first bit line and the second bit line. According to this structure, the memory device can write data in the memory cell including the storage element exhibiting a magnetoresistance effect by feeding a current to the first and second bit lines. In this case, the storage element exhibiting a magnetoresistance effect may include a TMR element exhibiting a ferromagnetic tunnel effect.  
           [0038]    The aforementioned memory device having the memory cell including the storage element exhibiting a magnetoresistance effect preferably further comprises a plurality of word lines arranged to intersect with the first bit line, the first pair line, the second bit line and the second pair line and a plurality of auxiliary word lines provided in correspondence to the word lines respectively and connected with the memory cell, and performs a data write operation by feeding mutually intersecting currents to one of the auxiliary word lines and the first and second bit lines. According to this structure, the memory device can write data in the memory cell located on the intersection between the auxiliary word line and the first and second bit lines through a composite field of a magnetic field formed by the current flowing through the auxiliary word line and a magnetic field formed by the current flowing through the first and second bit lines.  
           [0039]    The aforementioned memory device having the memory cell including the storage element exhibiting a magnetoresistance effect preferably connects the current path of the first bit line and the current path of the second bit line with each other so that currents oppositely flow through the first bit line and the second bit line when data written in a memory cell connected to the first bit line and a memory cell connected to the second bit line are different from each other. According to this structure, the memory device can easily write different data in the memory cells including the storage elements exhibiting a magnetoresistance effect. In this case, currents may oppositely flow through the first bit line and the first pair line, and currents may oppositely flow through the second bit line and the second pair line.  
           [0040]    In the aforementioned memory device according to the second aspect, the first pair line preferably includes a first inverted bit line paired with the first bit line and supplied with a signal level complementary to the first bit line, and the second pair line preferably includes a second inverted bit line paired with the second bit line and supplied with a signal level complementary to the second bit line. According to this structure, the memory device can write data, reverse to those in memory cells connected with the first and second bit lines, in memory cells connected with the first and second inverted bit lines respectively by connecting the memory cells to the first and second inverted bit lines. In this case, a memory cell is preferably connected to the first bit line and the first inverted bit line, and another memory cell is preferably connected to the second bit line and the second inverted bit line.  
           [0041]    In this case, each of the memory cells connected to the first bit line and the first inverted bit line and to the second bit line and the second inverted bit line may include two storage elements having a magnetoresistance effect and two transistors. Thus, the memory device can write data corresponding to the first and second bit lines in the first storage element of each memory cell while writing data corresponding to the first and second inverted bit lines in the second storage element.  
           [0042]    In this case, the memory device preferably further comprises a first latch circuit for storing write data for the first bit line and a second latch circuit for storing write data for the second bit line, while the first and second latch circuits preferably include sense amplifiers. According to this structure, the memory device can use the first and second latch circuits also as sense amplifiers for determining read data in data reading.  
           [0043]    In the aforementioned memory device according to the second aspect, the first pair line may include a first auxiliary bit line paired with the first bit line and connected with no memory cell, and the second pair line may include a second auxiliary bit line paired with the second bit line and connected with no memory cell. According to this structure, the memory device can easily connect the current paths of the first and second bit lines with each other through the first and second auxiliary bit lines. In this case, each of memory cells connected to the first bit line and to the second bit line may include a storage element having a magnetoresistance effect and a transistor. Further, the storage element exhibiting a magnetoresistance effect may include a TMR element exhibiting a ferromagnetic tunnel effect.  
           [0044]    The aforementioned memory device including the first and second auxiliary bit lines preferably further comprises a reference bit line and an auxiliary reference bit line, while a reference memory cell including a resistance element and a transistor is preferably connected to the reference bit line. According to this structure, the memory device can easily determine data stored in the memory cell on the basis of resistance resulting from the resistance element of the reference memory cell and resistance resulting from the storage element of the memory cell exhibiting a magnetoresistance effect.  
           [0045]    In this case, the memory device further comprises a first latch circuit for storing write data for the first bit line, a second latch circuit for storing write data for the second bit line and a sense amplifier connected with at least the reference bit line and provided independently of the first latch circuit and the second latch circuit. According to this structure, the memory device can store data to be written in the memory cell through the first and second latch circuits while determining the data written in the memory cell through the sense amplifier.  
           [0046]    The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0047]    [0047]FIG. 1 is a block diagram showing the overall structure of an MRAM according to a first embodiment of the present invention;  
         [0048]    [0048]FIG. 2 is a circuit diagram showing the structure of a memory cell part of the MRAM according to the first embodiment shown in FIG. 1;  
         [0049]    [0049]FIG. 3 is a circuit diagram showing a memory cell array part and a current path control circuit part of the MRAM according to the first embodiment shown in FIGS. 1 and 2;  
         [0050]    [0050]FIG. 4 is an operation waveform diagram for illustrating a read operation of the MRAM according to the first embodiment shown in FIGS. 1 and 2;  
         [0051]    [0051]FIG. 5 is a block diagram showing the overall structure of an MRAM according to a second embodiment of the present invention;  
         [0052]    [0052]FIG. 6 is a circuit diagram showing a memory cell array part and a current path control circuit part of the MRAM according to the second embodiment shown in FIG. 5;  
         [0053]    [0053]FIGS. 7 and 8 are schematic diagrams for illustrating the structure of a storage element of a conventional MRAM; and  
         [0054]    [0054]FIG. 9 is a block diagram showing the overall structure of another conventional MRAM. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0055]    Embodiments of the present invention are now described with reference to the drawings.  
         [0056]    (First Embodiment)  
         [0057]    The overall structure of an MRAM according to a first embodiment of the present invention is described with reference to FIGS. 1 and 2. The MRAM according to the first embodiment is mainly formed by a memory cell array  51  in the form of a matrix. The memory cell array  51  is formed by memory cells  52  arranged in row and column directions. Each memory cell  52  stores 1-bit data, which is the minimum unit of storage.  
         [0058]    In the MRAM according to the first embodiment, each memory cell  52  is formed by two TMR elements  4   a  and  4   b  and two NMOS transistors  5   a  and  5   b . As shown in FIG. 2, the TMR element  4   a  includes a ferromagnetic layer  3   a , an insulating barrier layer  2   a  and another ferromagnetic layer  1   a  harder to invert than the ferromagnetic layer  3   a . The TMR element  4   b  includes a ferromagnetic layer  3   b , an insulating barrier layer  2   b  and another ferromagnetic layer  1   b  harder to invert than the ferromagnetic layer  3   b . A word line WL is connected to the gates of the two NMOS transistors  5   a  and  5   b.    
         [0059]    In the memory cell array  51 , each memory cell  52  arranged in the row direction (vertical direction in FIG. 1) is connected to a word line WL and an auxiliary word line SWL. Each memory cell  52  arranged in the column direction (horizontal direction in FIG. 1) is connected to a bit line BL and an inverted bit line /BL, which forms a pair of bit lines BL and /BL with the corresponding bit line BL. The inverted bit line /BL is an example of the “pair line” in the present invention.  
         [0060]    Each pair of bit lines BL and /BL are connected to a cross-coupled latch sense amplifier (SA)  53 . The signal levels of the bit line BL and the inverted bit line /BL forming each pair of bit lines BL and /BL complementarily change.  
         [0061]    In the MRAM according to the first embodiment, a current path control circuit  70  is provided between the pairs of bit lines BL and /BL and the sense amplifiers (SA)  53  for connecting current paths of the bit lines BL with each other in data writing. As shown in FIG. 3, the current path control circuit  70  includes NAND circuits  71  and  72 , AND circuits  73  to  78 , switching transistors Tr 1  and Tr 2  consisting of PMOS transistors, switching transistors Tr 3  to Tr 8  consisting of NMOS transistors and NMOS transistors  8   a  and  8   b . The NAND circuits  71  and  72  and the AND circuits  73  to  78  are examples of the “logic circuit” in the present invention. The switching transistors Tr 1  to Tr 8  are examples of the “switching element” in the present invention.  
         [0062]    The NMOS transistors  8   a  and  8   b  are provided in order to separate each pair of bit lines BL and /BL from the sense amplifier (SA)  53 . A signal line Φ 3  is connected to the gates of the NMOS transistors  8   a  and  8   b.    
         [0063]    Outputs of the NAND circuits  71  and  72  are connected to the gates of the switching transistors Tr 1  and Tr 2  consisting of PMOS transistors respectively. Outputs of the AND circuits  73  to  78  are connected to the gates of the switching transistors Tr 3  to Tr 8  consisting of NMOS transistors respectively. Therefore, the switching transistors Tr 1  and Tr 2  consisting of PMOS transistors are turned on when the outputs of the NAND circuits  71  and  72  are low. Further, the switching transistors Tr 3  to Tr 8  consisting of NMOS transistors are turned on when the outputs of the AND circuits  73  to  78  are high.  
         [0064]    A first source/drain of the switching transistor Tr 1  is connected to a driving voltage Vcc, and a second source/drain thereof is connected to a bit line BL 0 . A first source/drain of the switching transistor Tr 2  is connected to the driving voltage Vcc, and a second source/drain thereof is connected to an inverted bit line /BL 0 .  
         [0065]    A first source/drain of the switching transistor Tr 3  is connected to the bit line BL 0 , and a second source/drain thereof is connected to a bit line BL 1 . A first source/drain of the switching transistor Tr 4  is connected to the bit line BL 0 , and a second source/drain thereof is connected to an inverted bit line /BL 1 . A first source/drain of the switching transistor Tr 5  is connected to the inverted bit line /BL 0 , and a second source/drain thereof is connected to the bit line BL 1 . A first source/drain of the switching transistor Tr 6  is connected to the inverted bit line /BL 0 , and a second source/drain thereof is connected to the inverted bit line /BL 1 . Such switching transistors Tr 3  to Tr 6  and AND circuits  73  to  76  are similarly provided also for bit lines BL 2 , BL 3 , . . . (not shown).  
         [0066]    A first source/drain of the switching transistor Tr 7  is connected to a bit line BLn, and a second source/drain thereof is grounded. A first source/drain of the switching transistor Tr 8  is connected to an inverted bit line /BLn, and a second source/drain thereof is grounded.  
         [0067]    A write enable signal line WE is connected to first input terminals of the NAND circuits  71  and  72 , second input terminals of the AND circuits  73  to  76  and first input terminals of the AND circuits  77  and  78  respectively.  
         [0068]    Second input terminals of the NAND circuits  71  and  72  are connected to the bit line BL 0  and the inverted bit line /BL 0  respectively. A first input terminal of the AND circuit  73  is connected to the bit line BL 1  and a third input terminal of the AND circuit  75 . A third input terminal of the AND circuit  73  is connected to the inverted bit line /BL 0  and a third input terminal of the AND circuit  74 . A first input terminal of the AND circuit  74  is connected to the inverted bit line /BL 1  and a third input terminal of the AND circuit  76 . A first input terminal of the AND circuit  75  is connected to the bit line BL 0  and a first input terminal of the AND circuit  76 . A third input terminal of the AND circuit  76  is connected to the inverted bit line /BL 1  and the first input terminal of the AND circuit  74 .  
         [0069]    A second input terminal of the AND circuit  77  is connected to the inverted bit line /BLn. A second input terminal of the AND circuit  78  is connected to the bit line BLn.  
         [0070]    As shown in FIG. 1, the word lines WL are connected to a row decoder  54 . A row address buffer  55  supplies an externally specified row address RA to the row decoder  54 . Thus, the row decoder  54  selects the word line WL corresponding to the row address RA.  
         [0071]    A first end of the auxiliary word line SWL is connected to each word line WL through an inverter circuit including an NMOS transistor  6  and a PMOS transistor  7 . The driving voltage Vcc is connected to a second end of the auxiliary word line SWL through a PMOS transistor  9 . A signal line Φ 4  is connected to the gate of the PMOS transistor  9 .  
         [0072]    The word line WL is connected to a first input terminal and an output terminal of an AND circuit  11 . A signal line Φ 6  regularly reaching zero (low) in writing is connected to a second input terminal of the AND circuit  11 .  
         [0073]    NMOS transistors  10   a  and  10   b  are connected to the bit line BL and the inverted bit line /BL respectively. A signal line Φ 5  is connected to the gates of the NMOS transistors  10   a  and  10   b . First ends of the NMOS transistors  10   a  and  10   b  are interconnected. A precharge circuit  67  is connected to the interconnected NMOS transistors  10   a  and  10   b.    
         [0074]    An NMOS transistor  100  is arranged between the bit line BL and the inverted bit line /BL for connecting the bit line BL and the inverted bit line /BL with each other. A signal line Φ 10  is connected to the gate of the NMOS transistor  100 .  
         [0075]    The sense amplifiers  53  are connected to an input/output line I/O and an inverted input/output line /I/O through the transfer gates  56 . The input/output line I/O and the inverted input/output line /I/O form a pair of input/output lines I/O and /I/O. The pair of input/output lines I/O and /I/O are connected to a read amplifier  57 . The read amplifier  57  is connected to an output circuit  58  for data through a data bus DB and an inverted data bus /DB. The data bus DB and the inverted data bus /DB form a pair of data buses DB and /DB. A precharge circuit  59  is connected to the pair of input/output lines I/O and /I/O.  
         [0076]    The levels of the input/output line I/O and the inverted input/output line /I/O complementarily change. The levels of the data bus DB and the inverted data bus /DB also complementarily change. The output circuit  58  outputs data.  
         [0077]    The transfer gates  56  are connected to a column decoder  60  through column selection lines CSL. Each transfer gate  56  is formed by a pair of NMOS transistors connected between the pair of input/output lines I/O and /I/O and the sense amplifier  53 . The gates of the pair of NMOS transistors are connected to the column decoder  60  through a single column selection line CSL. When the column selection line CSL goes high, therefore, the pair of NMOS transistors are turned on to turn on the transfer gate  56 . FIG. 3 illustrates no transfer gates  56 , no pair of input/output lines I/O and /I/O and no column selection lines CSL, in order to simplify the illustration.  
         [0078]    A column address buffer  61  supplies an externally specified column address CA to the column decoder  60  and an address transition detector (hereinafter abbreviated as “ATD”)  62 .  
         [0079]    The ATD  62  detects external specification of the column address CA by detecting change of the column address CA, and generates a pulse signal ATD 1 . In other words, the ATD  62  generates the pulse signal ATD 1  every change of the column address CA. The ATD  62  outputs the pulse signal ATD 1  to a column decoder control circuit  63 , a precharge control circuit  64  and a read amplifier control circuit  65 .  
         [0080]    The precharge control circuit  64  generates a 1-pulse precharge circuit activation signal PC going high for a predetermined time on the basis of the pulse signal ATD 1  falling from a high level to a low level, and outputs the activation signal PC to the precharge circuit  59 .  
         [0081]    When activated, the precharge circuit  59  performs precharging of setting the pair of input/output lines I/O and /I/O to the same potential of a prescribed level ½Vcc, for example (Vcc: driving voltage for the MRAM).  
         [0082]    When receiving the activation signal PC, the precharge circuit  59  is inactivated (enters an activation standby state) and stops precharging the pair of input/output lines I/O and /I/O. The column decoder control circuit  63  generates a 1-pulse column decoder activation signal YS going high for a predetermined time on the basis of the pulse signal ATD 1  falling from a high level to a low level, and outputs the activation signal YS to the column decoder  60 .  
         [0083]    When receiving the activation signal YS, the column decoder  60  is activated to select a column (a pair of bit lines BL and /BL) of the memory cell array  51  corresponding to the externally specified column address CA. In other words, the column decoder  60  is activated when receiving the activation signal YS. When activated, the column decoder  60  selects the column selection line CSL corresponding to the externally specified column address CA and sets the column selection line CS high. Thus, the transfer gate  56  connected to the column selection line CSL is turned on. Therefore, the column of the memory cell array  51  corresponding to the externally specified column address CA is selected through the sense amplifier  53  corresponding to the transfer gate  56 .  
         [0084]    The read amplifier control circuit  65  generates a 1-pulse read amplifier activation signal READ obtained by delaying the pulse signal ATD 1  by a prescribed time on the basis of the pulse signal ATD 1  falling from a high level to a low level. The timing and the pulse width of the activation signal READ are previously set. The activation signal READ is output to the read amplifier  57 .  
         [0085]    The delay time of the activation signal READ corresponds to a time required for developing sufficient potential difference between the pair of input/output lines I/O and /I/O for reading data. In other words, the delay time is set to a time for waiting until the potentials of the pair of input/output lines I/O and /I/O change from the precharged level to levels exhibiting sufficient potential difference for preventing the read amplifier  57  from false reading.  
         [0086]    That is, the control circuits  63  to  65  serve as delay circuits and pulse generation circuits generating the activation signals YS, PC and READ at proper timing with proper pulse widths when the pulse signal ATD 1  falls from a high level to a low level.  
         [0087]    The MRAM is further provided with a read detection circuit  66  detecting potential difference between the pair of data buses DB and /DB and generating a high-level read detection signal READ on the basis of the result of the detection. Thus, data read from any memory cell  52  is defined and output when the potential difference between the pair of data buses DB and /DB exceeds a prescribed level. Thus, a data output (read operation) can be detected by detecting the potential difference between the pair of data buses DB and /DB. The read detection circuit  66  detects the read operation on the basis of the potential difference between the pair of data buses DB and /DB while generating the high-level read detection signal READ on the basis of the result of the detection. The read detection circuit  66  outputs the detection signal READ to the column decoder control circuit  63 , the precharge control circuit  64  and the read amplifier  65 .  
         [0088]    Write and read operations of the MRAM according to the first embodiment having the aforementioned structure are now described.  
         [0089]    (Write Operation)  
         [0090]    An operation of writing data in the memory cells  52  connected to the word line WL 1  is described. As shown in FIG. 3, the MRAM stores write data in the latch sense amplifiers  53 . In this case, the bit lines BL 0 , BL 1  and BLn store high, low and low levels respectively.  
         [0091]    In order to write the data, the MRAM sets the signal line Φ 6  (FIG. 2) low. Thus, a low-level signal is input in the second input terminal of the AND circuit  11 . In this case, the word line WL 1  input in the first input terminal of the AND circuit  11  is high due to the selection by the row decoder  54 . Therefore, a part output from the AND circuit  11  for the selected word line WL 1  goes low. Thus, the MRAM sets the signal line Φ 6  low thereby forcibly setting the word line WL 1  connected to the output of the AND circuit  11  low.  
         [0092]    Thus, the NMOS transistors  5   a  and  5   b  connected to the word line WL 1  connected to the output terminal of the AND circuit  11  are turned off. The signal line Φ 4  falls to a low level thereby turning on the PMOS transistor  9 . In this case, the word line WL 1  connected to an auxiliary word line SWL 1  through an inverter is high and hence the NMOS transistor  6  forming the inverter is turned on. Thus, the lower potion of the auxiliary word line SWL 1  reaches a ground potential GND. As to the upper portion of the auxiliary word line SWL 1 , the PMOS transistor  9  is turned on to reach the driving voltage Vcc due to fall of the signal line Φ 4 , and hence a current downwardly flows through the auxiliary word line SWL 1 .  
         [0093]    As shown in FIG. 3, the bit lines BL 0 , BL 1  and BLn are high, low and low respectively, whereby the inverted bit lines /BL 0 , /BL 1  and /BLn go low, high and high respectively. In this case, the first input terminals of the NAND circuits  71  and  72  go high and low respectively. In this state, the MRAM sets the write enable signal line WE high while setting the signal line Φ 3  low. Thus, outputs of the NAND circuits  71  and  72  go low and high respectively, thereby turning the switching transistors Tr 1  and Tr 2  on and off respectively.  
         [0094]    Further, an output of the AND circuit  76  goes high, thereby turning on the switching transistor Tr 6 . Thus, the inverted bit lines /BL 0  and /BL 1  are connected with each other thereby connecting current paths of the pairs of bit lines BL 0  and /BL 0  and BL 1  and /BL 1 . Outputs of the AND circuits  73  to  75  go low, thereby turning off the switching transistors Tr 3  to Tr 5 . The MRAM similarly connects current paths of the bit lines BL 2 , BL 3 , . . . (not shown) through the switching transistors Tr 3  to Tr 6  and the AND circuits  73  to  76 .  
         [0095]    Outputs of the AND circuits  77  and  78  go high and low respectively, thereby turning the switching transistors Tr 7  and Tr 8  on and off respectively. The signal line Φ 10  goes high, and the NMOS transistor  100  is turned on.  
         [0096]    The current paths of the bit lines BL 0 , BL 1 , . . . BLn are connected with each other due to the aforementioned on-off states of the switching transistors Tr 1  to Tr 8 , whereby a current uninterruptedly flows through the bit lines BL 0 , BL 1 , . . . BLn as shown by wide lines in FIG. 3. In other words, the current path control circuit  70  connects the current paths of the bit lines BL 0 , BL 1 , . . . BLn with each other, whereby a write current can be fed to the bit lines BL 0 , BL 1 , . . . BLn through a single current path. Thus, data are rewritten in all memory cells  52  intersecting with the selected auxiliary word line SWL 1  due to a composite magnetic field of those resulting from a current flowing through the auxiliary word line SWL 1  and the directions of the current flowing through the respective bit lines BL 0 , BL 1 , . . . BLn. The current oppositely flows through each pair of bit lines BL and /BL.  
         [0097]    According to the first embodiment, the MRAM can feed a rewrite current through a single current path by connecting the current paths of the bit lines BL 0 , BL 1 , . . . BLn through the current path control circuit  70  in data writing, whereby the data can be rewritten with smaller current consumption as compared with a case of feeding a rewrite current every bit line.  
         [0098]    As hereinabove described, further, the MRAM can easily write reverse data (e.g., “1” and “0”) in the ferromagnetic layers  3   a  and  3   b  of the TMR elements  4   a  and  4   b  of the selected memory cells  52  by downwardly feeding the current to the auxiliary word line SWL 1  while feeding the current oppositely to each pair of bit lines BL and /BL.  
         [0099]    In order to write data (e.g., “0” and “1”) reverse to the above in the ferromagnetic layers  3   a  and  3   b  of the TMR elements  4   a  and  4   b , the MRAM may feed the current to each pair of bit lines BL and /BL oppositely to the above.  
         [0100]    (Read Operation)  
         [0101]    As hereinabove described, the MRAM writes data forming reverse magnetic fields in the ferromagnetic layers  3   a  and  3   b  of the TMR elements  4   a  and  4   b  connected to each bit line BL and each inverted bit line /BL respectively in the data write operation. The read operation is now described with reference to FIGS. 2 and 4 with respect to a case of selecting the memory cells  52  connected to the word line WL 1 .  
         [0102]    Before rising, the word line WL 1  (FIG. 2) is low. In this case, the PMOS transistor  7  of the inverter circuit connected to the word line WL 1  is turned on, whereby the potential of the auxiliary word line SWL 1  reaches the driving voltage Vcc. Thus, the potentials of nodes a also reach the driving voltage Vcc. The potentials of the TMR elements  4   a  and  4   b  formed by conductors also reach the driving potential Vcc. In this state, the signal line Φ 5  goes high while the precharge circuit  67  precharges each bit line BL and each inverted bit line /BL to the driving voltage Vcc. Upon rising, the word line WL 1  is set high by the row decoder  54  thereby turning on the NMOS transistors  5   a  and  5   b  connected thereto. Thus, each bit line BL and each inverted bit line /BL and the TMR elements  4   a  and  4   b  are rendered conductive. In this case, the potentials of the bit line BL, the inverted bit line /BL and each node a are at the driving voltage Vcc.  
         [0103]    When the word line WL 1  rises high, the signal line Φ 5  goes low and the precharge circuit  67  is cut off while the NMOS transistor  6  of the inverted circuit connected to the word line WL 1  is turned on, whereby the potential of the auxiliary word line SWL 1  is gradually lowered toward the ground potential GND. Thus, the potential of the node a is also gradually lowered toward the ground potential GND. Therefore, the potentials of the bit line BL and the inverted bit line /BL are also gradually lowered toward the ground potential GND. The TMR element  4   a  connected to the bit line BL is slightly higher in resistance than the TMR element  4   b  connected to the inverted bit line /BL since the directions of the magnetic fields are opposite in the ferromagnetic layers  3   a  and  1   a.    
         [0104]    When the MRAM starts lowering the potentials of the bit line BL and the inverted bit line /BL toward the ground potential GND, the MR ratio (resistance change) is maximized due to slight potential difference between the bit line BL and the inverted bit line /BL and the node a.  
         [0105]    The potentials of the bit line BL and the inverted bit line /BL also lower as the potential of the node a lowers. In this case, the potential of the TMR element  4   a  connected to the bit line BL lowers at a slower speed than that of the TMR element  4   b  connected to the inverted bit line /BL due to the slightly high resistance. Thus, potential difference is caused between the bit line BL and the inverted bit line /BL. The word line WL 1  falls from a high level to a low level at the timing of the potential difference, as shown in FIG. 4.  
         [0106]    The word line WL 1  falls before the potential of the node a reaches the ground potential GND for the following reason: The potential difference between the bit line BL and the inverted bit line /BL is caused only in a transient state. When the potentials (potential the of node a) of the ferromagnetic layers  1   a  and  1   b  of the TMR elements  4   a  and  4   b  reach the ground potential GND, therefore, the potentials of the bit line BL and the inverted bit line /BL connected with the ferromagnetic layers  3   a  and  3   b  respectively also reach the ground potential GND. In this case, no detectable potential difference is caused between the bit line BL and the inverted bit line /BL.  
         [0107]    While potential difference is caused between the bit line BL and the inverted bit line /BL at transient timing, the TMR elements  4   a  and  4   b  are formed by conductors and hence the potentials of the bit line BL and the inverted bit line /BL finally reach the same level. Therefore, the signal line Φ 3  (see FIG. 3) falls in response to the fall timing of the word line WL 1 . Thus, the NMOS transistors (separation transistors)  8   a  and  8   b  are turned off, thereby separating the bit line BL and the inverted bit line /BL from the sense amplifier  53 . Thereafter the signal lines Φ 1  and Φ 2  for the sense amplifier  53  rise thereby activating the sense amplifier  53 . Thus, the potential difference between the bit line BL and the inverted bit line /BL is so amplified that the potentials of the bit line BL and the inverted bit line /BL reach the driving voltage Vcc and the ground potential GND respectively. Thus, the MRAM reads data.  
         [0108]    The signal line Φ 5  rises and the precharge circuit  67  is turned on at the fall timing of the signal line Φ 3  for precharging the bit line BL and the inverted bit line /BL to the driving voltage Vcc.  
         [0109]    (Second Embodiment)  
         [0110]    Referring to FIGS. 5 and 6 showing an MRAM according to a second embodiment of the present invention, each memory cell is formed by a transistor and a TMR element, dissimilarly to the aforementioned first embodiment.  
         [0111]    According to the second embodiment, each memory cell  92  is formed by a transistor  5   a  and a TMR element  4   a , as shown in FIG. 5. The MRAM according to the second embodiment is provided with an auxiliary bit line SBL corresponding to each bit line BL. The auxiliary bit line SBL is an example of the “pair line” in the present invention. The auxiliary bit line SBL consists or a mere wire.  
         [0112]    According to the second embodiment, latches  83  are provided between a current path control circuit  70  and a column decoder  60 . The latches  83 , having a function of holding write data received from the column decoder  60 , are similar in circuit structure to the sense amplifiers  53  according to the first embodiment shown in FIG. 3. The latches  83  are examples of the “latch circuit” in the present invention.  
         [0113]    The MRAM according to the second embodiment is further provided with a reference bit line BLr and an auxiliary reference bit line SBLr. The reference bit line BLr includes a reference memory cell  93  consisting of a resistance element  14   a  and an NMOS transistor  5   a  every word line WL. The resistance element  14   a  of the reference memory cell  93  has an intermediate resistance value Rr between resistance values of the TMR element  4   a  exhibited when the directions of magnetization are parallel and antiparallel respectively. The reference bit line BLr and the auxiliary reference bit line SBLr are connected to a sense amplifier  57   a  through a precharge circuit  59 . According to the second embodiment, a sense amplifier control-circuit  65   a  is connected to the sense amplifier  57   a . An input/output line I/O and an inverted input/output line /I/O are also connected to the sense amplifier  57   a  through the precharge circuit  59 .  
         [0114]    The current path control circuit  70  according to the second embodiment is similar in internal structure to the current path control circuit  70  according to the first embodiment shown in FIG. 3. The remaining structure of the MRAM according to the second embodiment is also similar to that of the MRAM according to the first embodiment.  
         [0115]    The MRAM according to the second embodiment is provided with the auxiliary bit line SBL paired with each bit line BL as hereinabove described. Also when each memory cell  92  is formed by the single transistor  5   a  and the single TMR element  4   a , therefore, the current path control circuit  70  can connect current paths of the bit lines BL with each other, whereby the MRAM can feed a rewrite current to the bit lines BL through a single current path. Thus, the MRAM can rewrite data with smaller current consumption as compared with a case of feeding a rewrite current every bit line.  
         [0116]    (Write Operation)  
         [0117]    A write operation (rewrite operation) of the MRAM according to the second embodiment is similar to that of the aforementioned MRAM according to the first embodiment. In the write operation, the MRAM operates the column decoder  60  for storing write data in the latches  83 , as shown in FIG. 6. The write operation is described with respect to a case of storing high, low and low levels in bit lines BL 0 , BL 1  and BLn respectively.  
         [0118]    The MRAM downwardly feeds current to an auxiliary word line SWL 1  by a method similar to that in the first embodiment.  
         [0119]    The bit lines BL 0  BL 1  and BLn are high, low and low respectively as shown in FIG. 6, and hence inverted bit lines /BL 0 , /BL 1  and /BLn go low, high and high respectively. In this case, switching transistors Tr 1  and Tr 2  are turned on and off respectively. Further, switching transistors Tr 6  are turned on and switching transistors Tr 3  to Tr 5  are turned off respectively. In addition, switching transistors Tr 7  and Tr 8  are turned on and off respectively.  
         [0120]    Current paths of the bit lines BL 0 , BL 1 , . . . BLn are connected with each other due to the aforementioned on-off states of the switching transistors Tr 1  to Tr 8 , whereby a current uninterruptedly flows through the bit lines BL 0 , BL 1 , . . . BLn as shown by wide lines in FIG. 6. In other words, the current path control circuit  70  connects the current paths of the bit lines BL 0 , BL 1 , . . . BLn with each other, whereby a write current can be fed to the bit lines BL 0 , BL 1 , . . . BLn through a single current path. Thus, data are rewritten in all memory cells  52  intersecting with the selected auxiliary word line SWL 1  due to a composite magnetic field of those resulting from a current flowing through the auxiliary word line SWL 1  and the directions of the current flowing through the respective bit lines BL 0 , BL 1 , . . . BLn. The current oppositely flows through each pair of bit lines BL and /BL.  
         [0121]    (Read Operation)  
         [0122]    A read operation is now described with reference to FIGS. 5 and 6 as to a case of selecting a memory cell  92  connected with the word line WL 1  and a bit line BL 2 .  
         [0123]    In an initial state, the potentials of each bit line BL, each auxiliary word line SWL, the input/output line I/O and the reference bit line BLr are at a driving voltage Vcc (high). Thereafter each bit line BL and each auxiliary word line SWL enter floating states of the voltage Vcc. When an address is input in a row decoder  54  and a signal line Φ 6  is activated high, an output of an AND circuit  11  goes high and hence the selected word line WL 1  goes high. When the selected word line WL 1  input in the AND circuit  11  goes high, an NMOS transistor  6  connected to an auxiliary word line SWL 1  corresponding to the selected word line WL 1  is turned on. Thus, the potential of the auxiliary word line SWL 1  in the floating state of the voltage Vcc gradually starts to lower from the voltage Vcc to a ground potential (Vss).  
         [0124]    At this time, the bit line BL 2  and the auxiliary bit line SBL are connected to the input/output line I/O and the inverted input/output line /I/O respectively due to an address input in the column decoder  60 . The reference bit line BLr and the auxiliary reference bit line SBLr are connected to the precharge circuit  59 . When the potential of the auxiliary word line SWL 1  starts to lower from the voltage Vcc to the ground potential (Vss), the potentials of the bit line BL 2  and the reference bit line BLr also start to lower from the voltage Vcc to the ground potential (Vss). Thus, the potentials of the input/output line I/O input in the sense amplifier  57   a  and the reference bit line BLr also start to lower from the voltage Vcc to the ground potential (Vss).  
         [0125]    In this case, the resistance value of the TMR element  4   a  of the selected memory cell  52  is smaller than a resistance value Rr of the resistance element  14   a  of the reference bit line BLr assuming that the directions of magnetization are parallel. Therefore, the potentials of the input/output line I/O connected to the bit line BL 2  and the reference bit line BLr lower from the voltage Vcc toward the ground potential (Vss) at different speeds. More specifically, the potential of the input/output line I/O connected with the bit line BL 2  is to lower faster than that of the reference bit line BLr, to result in potential difference between the input/output line I/O connected with the bit line BL 2  and the reference bit line BLr.  
         [0126]    The MRAM detects this potential difference at proper timing, thereby activating the sense amplifier  57   a . The MRAM amplifies the potential difference between the input/output line I/O connected with the bit line BL 2  and the reference bit line BLr through the activated sense amplifier  57   a , so that the input/output line I/O connected with the bit line BL 2  and the reference bit line BLr go low and high respectively. The MRAM outputs a signal corresponding thereto from an output circuit  58 .  
         [0127]    When the selected memory cell  92  stores data having antiparallel directions of magnetization, the resistance value Rr of the resistance element  14   a , connected with the reference bit line BLr is smaller than the resistance value of the TMR element  4   a  of the selected memory cell  52  and hence the potential of the reference bit line BLr is to lower faster than that of the input/output line I/O connected with the bit line BL 2  contrarily to the above. When the MRAM amplifies the potential difference through the sense amplifier  57   a , the input/output line I/O and the reference bit line BLr go high and low respectively.  
         [0128]    The MRAM detects the potential difference between the input/output line I/O and the reference bit line BLr before the potentials of the bit line BL 2  and the reference bit line BLr reach the ground potential GND for the following reason: While potential difference is caused between each bit line BL and the reference bit line BLr at transient timing, the TMR element  4   a  and the resistance element  14   a  are made of conductors and hence the potentials of the bit line BL and the reference bit line BLr finally reach the same level.  
         [0129]    As hereinabove described, the MRAM according to the second embodiment can easily read data by forming each memory cell  52  by the single TMR element  4   a  and the single NMOS transistor  5   a  while detecting the potential difference between the bit line BL connected with the single TMR element  4   a  and the reference bit line BLr through the sense amplifier  57   a.    
         [0130]    Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.  
         [0131]    For example, while the MRAM according to each of the aforementioned embodiments employs the TMR element(s) as the storage element(s) forming each memory cell, the present invention is not restricted to this but a storage element other than the TMR element is also employable so far as the same exhibits a ferromagnetic tunnel effect. Also when employing a storage element exhibiting a magnetoresistance effect other than the ferromagnetic tunnel effect, further, an effect similar to those of the aforementioned embodiments can be attained.