Abstract:
A cyclic analog-to-digital converter includes two arithmetic circuits and a single comparator. The output of each arithmetic circuit is connected to the input of the other arithmetic circuit. Each arithmetic circuit can modify the analog signal being converted in accordance with output signals from the comparator. Embodiments are disclosed in which the arithmetic circuits include switched capacitors and separate or shared operational amplifiers.

Description:
FIELD OF THE INVENTION 
     This invention relates to analog-to-digital (&#34;A/D&#34;) converters, and more particularly to cyclic or algorithmic A/D converters implemented with switched-capacitance circuits. 
     BACKGROUND OF THE INVENTION 
     A/D converters are widely used in many applications. Cyclic or algorithmic A/D converters, in which an analog signal to be converted is cycled serially through analog arithmetic and comparator circuits, are useful in applications requiring small circuit size and power drain, but are somewhat slower than alternatives such as &#34;flash&#34; converters or &#34;pipeline&#34; converters that can perform conversion steps in parallel. A prior-art algorithmic A/D converter using switched-capacitance techniques is described in McCharles et al., &#34;An Algorithmic Analog-to-Digital Converter,&#34; IEEE International Solid-State Circuits Conference Digest of Technical Papers (1977), pp 96-97. A similar A/D converter in which a multiply-by-two function is achieved by addition is disclosed in U.S. Pat. No. 4,529,965. 
     Algorithmic A/D converters typically operate by sequentially comparing an analog signal with a reference, multiplying the signal by a constant (usually 2), subtracting a value from the result of the multiplication depending on the result of the comparison and repeating the comparison, multiplication and subtraction sequence until the required number of binary digits (&#34;bits&#34;) is obtained. In some converters the multiplication and subtraction steps are interchanged. Each cycle generates one bit of the digital representation of the analog signal being converted. The prior art converters referred to above include an arithmetic circuit to perform the subtraction and multiplication and a sample-and-hold circuit to store the analog residue from the preceding cycle. 
     In a fast A/D converter the comparator may not have time to completely settle before its output is used. For this reason, and also because the inputs to the comparator may be very close in value, the output of the comparator can be in error. Improvements employing multi-level comparators and digital correction to compensate for errors thus made are known in the art, for example, as disclosed in U. S. Pat. No. 5,017,920. 
     The need is for fast, accurate A/D converters that can be implemented with a minimum of circuitry, thus requiring less area on a semiconductor chip and less operating power. 
     SUMMARY OF THE INVENTION 
     A cyclic or algorithmic A/D converter is disclosed in which conversion cycles are overlapped to speed up conversion time. To accomplish this result, the sample-and-hold circuit used in prior-art converters is replaced with a second arithmetic circuit. Embodiments are disclosed using switched capacitors and either one or two operational amplifiers. Another embodiment is disclosed for use with digital correction logic. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a prior-art algorithmic A/D converter. 
     FIG. 2 is a block diagram of an algorithmic A/D converter constructed in accordance with the invention. 
     FIG. 3 is a schematic diagram of a switched-capacitor algorithmic A/D converter constructed in accordance with the invention using two operational amplifiers. 
     FIG. 4 is a schematic diagram of a switched-capacitor algorithmic A/D converter constructed in accordance with the invention using a single operational amplifier. 
     FIG. 5 is a schematic diagram of a switched-capacitor algorithmic converter constructed in accordance with the invention and having three comparator levels for use with digital correction. 
    
    
     DETAILED DESCRIPTION 
     In the exemplary prior-art A/D algorithmic converter shown in FIG. 1, an analog input signal to be converted is applied to lead 10 and passes through switch 11 and via lead 12 to the positive terminal of comparator 13 and to the input of sample-and-hold circuit 15. Comparator 13 compares the input signal with a threshold voltage V t  connected to its negative terminal. If the input signal exceeds the threshold, the output of the comparator is a binary &#34;1&#34;; if the input signal is less than the threshold, the output of the comparator is a binary &#34;0&#34;. The output of comparator 13, which is a serial digital representation of the analog input signal, is applied to shift register 14, which accumulates the successive bits of the digital representation in parallel form, and to selector 18. Shift register 14 is not needed if a serial digital representation is sufficient. 
     The signal stored in sample-and-hold circuit 15 is multiplied by a constant (two) in multiplier 16 and applied to the positive terminal of subtracter 17 and a signal from selector 18 is connected to the negative terminal of subtracter 17. Selector 18 determines such signal in accordance with the last-received bit from comparator 13. If the last-received bit is a &#34;1&#34;, indicating that the input signal exceeded threshold V t , then selector 18 supplies a first signal to subtracter 17. If the last-received bit is a &#34;0&#34;, indicating that the input signal did not exceed the threshold, then selector 18 applies a second signal to subtracter 17. In an embodiment as shown in FIG. 1, if V t  =0, typically the first signal is a negative voltage and the second signal is a positive voltage. 
     To generate the remaining bits of the digital representation, switch 11 is moved to connect the output of subtracter 17 to the input of comparator 14 and the above-described comparison, subtraction and multiplication steps are performed repeatedly on the residue from sutracter 17 until the desired number of bits is obtained. 
     It should be noted that the operation of the A/D converter of FIG. 1 occurs in two phases, a first phase P1 during which the result of the subtraction (or the input signal during the first cycle) are applied to comparator 13 and sample-and-hold circuit 15 and a second phase P2 during which inputs are applied to subtracter 17. During P2, comparator 13 is idle. 
     As is well known in the art, there are a number of variations possible in choosing the threshold V t  for comparator 13 and the related signals to be applied to subtracter 17 by selector 18. For example, if the input analog signal is bipolar and has a total swing of V r , V t  can be zero (ground), and the magnitudes of the signals applied by selector 18 can be+V r  /2 or-V r  /2 and the first bit converted will signify the polarity of such signal. If the input signal is always positive and has a total swing of V r , V t  can be V r  /2 and the magnitudes of the signals applied by selector 18 can be V r  or 0. There are also variations known in the art in which the multiplier and the subtracter of the circuit of FIG. 1 are interchanged. 
     FIG. 2 shows an algorithmic A/D converter in accordance with the present invention. Referring to FIG. 2, sample-and-hold circuit 15 of FIG. 1 is replaced with a second multiplier 16&#39;, a second subtracter 17&#39; and a second selector 18&#39;. Comparator 13 is shared through switches 21 and 22 so that during P1 comparator 13 compares the signal on lead 12 with threshold V t  and sets selector 18&#39; and during P2 compares the signal on lead 12&#39; with threshold V t  and sets selector 18. The converter of FIG. 2 performs a full comparison, subtraction and multiplication cycle during both P1 and P2. Thus, given equivalent clock rates, the converter of FIG. 2 operates at twice the speed of the converter of FIG. 1. 
     FIG. 3 shows an embodiment of the present invention using dual operational amplifiers, a single comparator and switched capacitors for storage of analog signal samples. The various switches, such as switch 31, shown in FIG. 3 can be MOS field-effect transistors, as is well known in the art. Such switches are selectively closed by a clock circuit (not shown) during the phases P0, P1 or P2 indicated for each switch. Such phases must be nonoverlapping. P0 is an initial phase during which the analog input signal to be converted is sampled onto capacitor 32. After P0 occurs, P1 and P2 are repeated until the desired number of bits is generated in shift register 33. The switches in FIG. 3 are shown in the open and closed positions that occur during P1. 
     During P0, the input signal on lead 30 passes through switch 31 to a first terminal of capacitor 32. Switch 34 across operational amplifier 35 is also closed during P0, which effectively grounds the negative input terminal of amplifier 35 and the second terminal of capacitor 32. Capacitor 32 thus charges to the magnitude of the input signal. Switch 37 also closes during P0 to keep capacitor 38 discharged. 
     Next, during P1, switch 34 opens and switch 36 closes, connecting capacitor 32 between the negative input terminal and the output terminal of operational amplifier 35, and switch 39 closes, placing the output of selector 40 on one terminal of capacitor 38. Thus, during P1, the output signal of amplifier 35 at node 41 stabilizes to become the algebraic sum of the output of selector 40, the voltage across capacitor 38 and the voltage across capacitor 32. During the first P1 after P0, the output of selector 40 and the voltage across capacitor 38 can both be assumed to be zero. Thus, during such first P1, the voltage at node 41 becomes equal in magnitude to the analog input signal on lead 30. 
     During P1, node 41 is connected through switch 45 to the positive input terminal of comparator 50. The output of comparator 50 will be &#34;1&#34; if the voltage at node 41 exceeds threshold V t  during P1 and &#34;0&#34; if the voltage at node 41 does not exceed such threshold. Selector 40&#39; becomes set via switch 51 to provide a signal during P2 in accordance with the bit generated during P1. 
     Switches 34&#39;, 42 and 43 are also closed during P1, thereby connecting both capacitors 32&#39; and 38&#39; between node 41 and effective ground at the negative input terminal of amplifier 35&#39;. Thus, capacitors 32&#39; and 38&#39; each charge to the voltage at node 41. Capacitors 32&#39; and 38&#39; are arranged to be equal in value, as are capacitors 32 and 38. 
     During P2, when switches 34&#39;, 42 and 43 open and switches 36&#39; and 39&#39; close, the voltage at node 41&#39; becomes the algebraic sum of the output of selector 40&#39; and the voltages across capacitors 32&#39; and 38&#39;. Because capacitors 32&#39; and 38&#39; are of equal value, this switching of capacitors 32&#39; and 38&#39; doubles the voltage at node 41 by adding such voltage to itself. The output of selector 40&#39; is subtracted by algebraic addition. That is, if it is desired to subtract a positive voltage of a given magnitude, the output of selector 40&#39; is chosen to be a negative voltage of such magnitude. 
     Also during P2, the voltage at node 41&#39; is applied through switch 45&#39; to comparator 50 and through switches 42&#39; and 43&#39; to capacitors 38 and 32. Comparator 50 then sets selector 40 through switch 51&#39; and capacitors 38 and 32 become charged in readiness for the next P1. The contents of shift register 33 are shifted to the right one position after P0 and each P1 and P2 by a signal from the clock (not shown) to accumulate the desired digital representation of the analog input signal. P1 and P2 are repeated until the required number of bits is obtained. 
     FIG. 4 shows an alternate embodiment of an A/D converter in accordance with the present invention using only a single operational amplifier 50. The converter of FIG. 4 operates in a similar manner to that of FIG. 3. Again, the various switches are marked to show the phases P0, P1 or P2 during which they are closed and the switches are shown in their P1 conditions. Switch 51 is marked P0&#39; to indicate that it is open during P0 and closed otherwise. 
     During P0, the analog input signal to be converted on lead 49 is connected to a first terminal of capacitor 52 through switch 53. The second terminal of capacitor 52 is grounded through switch 54 so that capacitor 52 charges to the magnitude of the input signal. During P0, switch 55 is closed and capacitor 56 remains discharged. 
     During the first P1, capacitor 52 is connected across amplifier 50 by the closing of switches 51 and 57 and the voltage at node 60 becomes equal to that on lead 49. Switch 61 also closes, but the output of selector 65&#39; can be assumed to be zero during the first P1, and has no effect on the node 60 voltage. Switches 58 and 59 also close, charging capacitors 52&#39; and 56&#39; to the voltage at node 60. Selector 65&#39; is set by comparator 63 through switch 62 in preparation for P2. Again, successive outputs from comparator 63 are assembled in shift register 64 to give the digital representation of the analog input signal on lead 49. 
     During P2, when the switches marked P1 open and the switches marked P2 close, the voltage at node 60 becomes the sum of the output of selector 65&#39; and the voltages across capacitors 52&#39; and 56&#39;, capacitors 52 and 56 charge to the voltage at node 60, and selector 65 becomes set by comparator 63 through switch 62&#39; in preparation for the next P1. As with the circuit in FIG. 3, P1 and P2 are repeated until the desired number of bits is accumulated in shift register 64. Again the clock signals to the various switches and to shift register 64 are generated by a clock circuit (not shown) and must be non-overlapping. 
     FIG. 5 shows an A/D converter in accordance with the invention and arranged for digital correction, which is described more fully in U.S. Pat. No. 5,017,920 mentioned previously. Arithmetic circuits 70 inside the dotted lines are is identical to the corresponding arithmetic circuits 70 shown in FIG. 4. In the converter of FIG. 5, the voltage on node 60 is applied to input terminals of both comparators 71 and 72. Typically, V t2  is more positive than V t1 . 
     If the voltage on node 60 is below V t1 , then the outputs of both comparators 71 and 72 will be low or &#34;0&#34;. If the voltage on node 60 is between V t1  and V t2 , then the output of comparator 72 will be &#34;1&#34; and that of comparator 71 will be &#34;0&#34;. If the node 60 voltage is above V t2 , then the output of both comparators will be &#34;1&#34;. Thus, the combined outputs of converters 71 and 72 give a three-state indication (&#34;00&#34;, &#34;10&#34; or &#34;11&#34;) of the magnitude of the voltage on node 60. Such three-state indication is applied to shift registers 73 and 74 and through switches 75, 75&#39;, 76 and 76&#39; to selectors 77 and 77&#39; in a manner comparable to the application of the output of comparator 63 to shift register 64 and selectors 65 and 65&#39; in FIG. 4. Selectors 77 and 77&#39; apply three-state outputs to circuitry 70, for example +V, 0  and -V, in accordance with the indication received from the comparators. Again, the relationships between the range of the analog input signal, the thresholds V t1  and V t2  and the magnitudes of the outputs of selectors 77 and 77&#39; are well known in the art. 
     The outputs from shift registers 73 and 74 are combined in correction circuit 78 to provide the digital output. Correction circuit 78 typically comprises digital adders and other logic. A description of one embodiment of such digital correction circuitry is included in U.S. Pat. No. 5,017,920. 
     The converters of FIGS. 3, 4 and 5 can also be implemented with differential operational amplifiers and comparators. Such a differential embodiment typically requires twice the number of switches and capacitors as a single-ended embodiment, but can provide increased accuracy, as is well known in the art. Examples of differential embodiments of prior-art A/D converters are shown in U.S. Pat. No. 5,027,116. 
     It would be apparent to those skilled in the art that other embodiments incorporating the principles of the present invention are possible. The above disclosure is merely illustrative and is not intended to be limiting in any respect.