Abstract:
A semiconductor device, such as a GaAs FET, has low-noise, ultra-high frequency operation. The semiconductor device has at least one bonding pad for applying potential to the gate electrode lying outside of the source region. In practice, one or more bonding pads are deposited in the general vicinity of the gate electrode and outside of the source region. This allows the number of supply points P to be increased without lengthening the source region and thus expanding the chip. With regard to the drain-gate capacitance, the bonding pad or pads can be surrounded by an electrode other than the drain region electrode or the gate electrode to ensure that the drain-gate capacitance is not increased.

Description:
This application is a continuation of application Ser. No. 726,228, filed Apr. 23, 1985. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to a semiconductor device having a field-effect transistor (FET) structure. More particularly, the invention relates to an FET, such as a GaAs FET designed for ultra-high frequency operation. 
     In recent years, satellite broadcasting systems have become increasingly available. In such satellite broadcasting systems, high-quality data, such as image data, pulse-code-modulated signals, and so forth, are broadcast at ultra-high frequencies, e.g. at about 12 GHz. Thus, receiving systems for satellite broadcasting systems have increased the demand for low-noise, ultra-high-frequency FET&#39;s. 
     The ultra-high-frequency FET, such as a GaAs FET can be represented by the equivalent circuit shown in FIG. 1. The noise figure F 0  of an FET can be described by the following equation: ##EQU1## 
     where K f  is a unique constant for each individual device, the so-called &#34;fitting factor&#34;; 
     C gs  is the gate-source capacitance (=input capacitance) 
     R g  is the gate resistance at high frequencies; 
     R s  is the source resistance; and 
     gm is the transmission conductance of the FET. 
     One way to reduce the noise figure F 0  is to reduce the gate resistance R g . The gate resistance R g  can be expressed by the following equation: ##EQU2## 
     where π g  is the resistivity of the gate metal; 
     S is the cross-sectional area of the gate; 
     Z u  is the unit gate width, and 
     Z t  is the total gate width. 
     As shown in FIGS. 2(A) to 2(C), the unit gate width Z u  can be reduced by increasing the number of supply points P relative to the total gate width Z t . For instance, as shown in FIG. 2(A), when one supply point P is active in the gate electrode 1, the unit gate width Z u  becomes 1/2Z t . When two supply points P are active, the unit gate width Z u  1/4Z t , as shown in FIG. 2(B). By further increasing the number of supply points to three as shown in FIG. 2(C), the unit gate width Z u  become 1/6Z t . 
     As will be appreciated herefrom, in general, if N supply points are built into the gate electrode 1, the unit gate width Z u  will be Z u  =Z t  /2N. Since the gate resistance R g  varies in proportion to the square of the unit gate width Z u , when two supply points are active, the gate resistance R g  the gate electrode 1 will be 1/4 of that when a single supply point P is available. Similarly, when three supply points P are provided for the gate electrode 1, the gate resistance R g  will be 1/9 of that when a single supply point is used. 
     In summary, increasing the number of supply points P in the gate electrode reduces the gate resistance R g  and thus the noise figure F 0  significantly. 
     On the other hand, in order to increase the number of supply points P in the gate electrode 1, an increased number of electrodes, so-called bonding pads, are required to supply the gate potential for the corresponding supply points P. This results in expansion of the gate cell area, resulting in a larger chip overall. For instance, as shown in FIGS. 3(A) to 3(C), a semiconductor device with an FET structure has a source region 2 and a drain region 3 on opposite sides of the gate electrode 1. The bonding pads 4 are installed on the source region side in order to prevent undue increase in the gate-drain capacitance C dg . The bonding pads 4 are surrounded by the source region 2 for the sake of shielding. Sine it has been considered essential to shield the bonding pads 4 by surrounding them with the source region metallization, it has been considered inevitable that the total length of the source region 2 will increase as the number of bonding pads 4 increases. 
     Therefore, as shown FIGS. 3(A) to 3(C), when two bonding pads 4 are connected to two supply points P on the gate electrode 1, as shown in FIG. 3(B), the required total length W 2  is greater than that length W 1  required for a single bonding pad for a single supply point. Similarly, when three bonding pads 4 is provided for three supply points, the total length W 3  of the source region 2 is even greater than that length W 2  for two bonding pads. In summary, increasing the number of supply points P in the gate electrode 1 thus results in an increase in the number of bonding pads 4 and in the total length W of the source region. This implies expansion of the gate cell dimensions and thus of the chip overall. Therefore, the finished GaAs FET becomes more expensive due to the increased cost of materials and so forth. In addition, expanding the chip size lowers the production yield of the semiconductor chip and of course expansion of the chip size is considered unfavorable in itself. 
     As far as the chip area alone is concerned, these problems can be resolved by using a multi-level structure for the semiconductor device. In the multi-level integration structure, the bonding pads 4 need not multiply as the number of supply points P in the gate electrode 1 increases. On the other hand, in the multi-level structure, it is necessary to deposit additional insulating layers by way of the CVD process or the like in order to limit the gate-source capacitance (input capacitance). Furthermore, it is also necessary to form through openings through the insulating layers to allow contacts to establish electrical connections. This results in relatively high production costs. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the invention to provide a semiconductor device, such as GaAs FET. which is of simple structure and which suppresses noise in the ultra-high-frequency range. 
     Another and more specific object of the invention is to provide a semiconductor device which can limit gate resistance R g  and thus reduce the noise figure of the device without requiring expansion of the chip. 
     In order to accomplish the above-mentioned and other objects, a semiconductor device, according to the present invention, has at least one bonding pad for applying potential to the gate electrode lying outside of the source region. 
     In practice, one or more bonding pads are deposited in the general vicinity of the gate electrode and outside of the source region. This allows the number of supply points P to be increased without lengthening the source region and thus expanding the chip. 
     With regard to the gate-source capacitance, the bonding pad or pads can be surrounded by an electrode other than the drain region electrode or the gate electrode to ensure that the gate-source capacitance is not increased. 
     According to one aspect of the invention, a semiconductor device comprises a semiconductor substrate having a source region and a drain region formed therein, a gate electrode formed on the substrate, a source electrode formed on the substrate and electrically connected to the source region, the source electrode being located at one side of the gate electrode, a drain electrode formed on the substrate and electrically connected to the drain region, the drain electrode being located at the other side of the gate electrode, and means for supplying a potential for the gate electrode, the means including a gate pad connected to a feeding point of the gate electrode, the gate pad lying outside of the source electrode. 
     According to another aspect of the invention, a field effect transistor comprises a semiconductor substrate, a gate electrode having a plurality of feeding points, a source electrode arranged at a first side of the gate electrode and defining essentially an enclosed space therein, a drain electrode arranged at a second side of the gate electrode, which second side is opposite of the first side with respect to the gate electrode, and means for supplying a potential to the gate electrode through the feeding points, the means including a plurality of gate pads, each of which is connected the corresponding one of the feeding points, the gate pads comprising at least one first pad arranged within the enclosed space of the source electrode and at least one second gate pad arranged outside of the enclosed space. 
     According to a further aspect of the invention, a field effect transistor comprises a semiconductor substrate, an elongated gate electrode, a source electrode arranged at a first side with respect to the gate electrode, a drain electrode arranged at a second side opposite to the first side with respect to the gate electrode, and means for providing a plurality of feeding points for the gate electrode, through which gating potential is supplied, the means connecting at least one first feeding point connected to a first potential source in a space generally shielded from the gate electrode by the source electrode, and at least one second feeding point connected to a second potential source lying outside of the shielded space. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only. 
     In the drawings: 
     FIG. 1, as set forth above, is a schematic diagram of an equivalent circuit for a typical field-effect transistor; 
     FIGS. 2(A) to 2(C) are diagrams illustrating the relationship between the unit gate resistance Z u  and the number of supply points P; 
     FIGS. 3(A) to 3(C) are plan views of the electrode arrangement on semiconductor devices employing different numbers of supply points; 
     FIG. 4 is a partial plan view of the first embodiment of a semiconductor device according to the present invention; 
     FIG. 5 is a cross-section taken along line V--V of FIG. 4; 
     FIGS. 6 to 8 are partial plan views of modifications to the first embodiment of FIG. 4; 
     FIG. 9 is a partial plan view of the second embodiment of a semiconductor device according to the invention; 
     FIG. 10 is a cross-section taken along line X--X of FIG. 9; 
     FIGS. 11 to 13 are partial plan views of modifications to the second embodiment of FIG. 9. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIGS. 4 and 5, the first embodiment of a semiconductor device according to the invention has a base 10 made of a semiconducting material such as gallium arsenide (GaAs). A gate electrode 11 made of tungsten silicide, aluminum or the like is deposited on the semiconductor base 10 in short-key contact with the base. The gate electrode 11 has gate length L g  and gate width Z t . A source electrode 12 and a drain electrode 13 are disposed on opposite sides of the gate electrode 11. 
     The semiconductor base 10 has a source region 16 and a drain region 17 formed by diffusion or equivalent processes and having high dopant concentrations and correspondingly low resistances. The source electrode 12 is electrically connected to the source region 16 by direct ohmic contact. Similarly, the drain electrode 13 is electrically connected to the drain region 17 by ohmic contact. 
     The gate electrode 11 is biased via three supply points Pa, Pb and Pc. The supply point Pc is disposed at the longitudinal center of the gate electrode 11. On the other hand, the supply points Pa and Pb are separated from the respectively corresponding longitudinal ends of the gate electrode 11 by Z t  /6. In this arrangement, the unit gate length Z u  is Z t  /6. The supply points Pa and Pb are connected to corresponding potential supply electrodes 14a and 14b, or so-called gate bonding pads, which will be referred to hereafter as &#34;gate pads&#34;, through electrode leads 14d and 14e. The gate pads 14a and 14b overlie the source region 16 of the base 10 and are surrounded by the source electrode 12. On the other hand, the central supply point Pc is connected to a gate pad 14c via an electrode lead 14f. The gate pad 14c overlies the drain region 17. 
     Each of the gate pads 14a, 14b and 14c is essentially square in plan view and are approximately 50 μm to 80 μm on a side, in which is considered to be the minimum required for wire bonding. As will be appreciated, the bonding pads of the same size are required for the source electrode 12 and the drain electrode 13. The gate electrode 12 has the gate width Z t  of about 200 μm to 300 μm. If all of the gate pads were embedded in the source electrode as shown in FIG. 3(C), the maximum length would have to be expanded. But in the shown embodiment, by disposing the central gate pad Pc outside of the source electrode and on the drain electrode side, the maximum length of the source electrode 12 becomes equivalent to that illustrated in FIG. 3(B) wherein two supply points are used for the gate electrode. 
     On the other hand, locating the gate pad outside of the source electrode 12 on the drain electrode side can be expected to increase the drain-gate capacitance C dg  and degrade the shielding effect. Therefore, in the conventional semiconductor device, gate pads have been embedded within the source electrode of apparent necessity. As is well known, the drain-gate capacitance C dg  acts as a feedback capacitance between the input and the output of the FET which lowers the gain. 
     The FET constructed as set forth above has been compared with the conventional FET of FIG. 3(B) which is of approximately the same size as the first embodiment but which has only two supply points. Since the conventional device has only two supply points, the unit gate length is Z t  /4. Assuming the FET&#39;s of FIGS. 3(B) and 4 have same gate length L g  =0.05 μm, and have same gate width Z t  and electrode dimensions including the source gate width W 2 , the gain Ga at an input signal frequency of 12 GHz will be approximately 9 dB for both FETs. The noise figure NZ of the conventional FET is approximately 1.5 dB. On the other hand, the noise figure NZ of the FET of the shown embodiment is 1.25 dB. Using the conventional geometry, in order to achieve an equivalent noise figure, i.e. 1.25 dB, the gate electrode must have a gate length L g  of only 0.03 μm. Therefore, in the prior art, ultra-fine-resolution technology is needed to achieve a noise figure level of 1.25 dB. According to the shown embodiment, the 1.25 dB noise figure can be achieved with a gate electrode gate length L g  as large as 0.05 μm. 
     In analysing the above results, it should be noted that although the drain-gate capacitance C dg  increases from about 20 fF to 30 fF in the shown embodiment, the favorable effect of the reduction of the gate resistance R g  due to the increase in the number of supply points outweighs this, resulting in a net reduction of the noise figure. 
     Accordingly, the first embodiment of the semiconductor device of the present invention makes it possible to connect three supply points to the gate electrode for an FET of the same size as a conventional FET using only two supply points. The above-mentioned tests have confirmed that the FET of the first embodiment of the invention achieves a reduced noise figure NF=1.25 dB at ultra-high frequencies, e.g. 12 GHz, which is comparable to that achieved conventionally only by limiting the gate length to 0.3 μm. Furthermore, since the shown embodiment allows a relatively high reduction in the noise figure NF, it is not necessary to employ a multi-level geometry for the sake of reducing noise at ultra-high frequencies nor to use a very thin gate electrode. Thus low-noise, high-performance semiconductor devices can be fabricated without increasing the chip size or employing more complicated manufacturing processes. Therefore, according to the shown embodiment, an excellent cost/performance ratio can be achieved for ultra-high-frequency low-noise FET&#39;s. 
     FIG. 6 shows a first modification to the first embodiment of the semiconductor device according to the invention. As in the first embodiment, a gate electrode 21 is provided with three supply points Pa, Pb and Pc. The supply points Pa and Pb are connected to opposite longitudinal ends of the gate electrode 21. Therefore, the unit gate length Z u  this case is Z t  /4. Gate pads 24a and 24b are disposed opposite the drain electrode 23 from the gate electrode 21. The gate pads 24a and 24b are connected to respectively corresponding supply points Pa and Pb of the gate electrode. In addition, a third gate pad 24c is embedded within the source electrode 22 and connected to the supply point Pc in the usual manner. 
     In this arrangement, the total length of the source electrode is the same as that of a conventional FET with a single supply point. Therefore, the chip size is comparable to that shown in FIG. 3(A). 
     It should be noted that, if desired, the positions of the gate pads 24a, 24b and 24c can be reversed. That is, if necessary, the gate pads can be arranged with the gate pads 24a and 24b on the source electrode side and the gate pad 24c on the drain electrode side. Furthermore, in this modified arrangement, a chip size comparable to that shown in FIG. 3(A) can be achieved by locating one of the gate pads 24a and 24b outside of the source electrode. 
     FIG. 7 shows a second modification to the foregoing first embodiment of the present invention. In this arrangement, five supply points Pa, Pb, Pc, Pd and Pe are connected to the gate electrode 31. The supply points Pa and Pb are connected to opposite longitudinal ends of the gate electrode 31. The other three supply points Pc, Pd and Pe are spaced at constant intervals of Z t  /4 along the gate electrode 31. Thus, the unit gate length Z u  is Z t  /8. The supply points Pd and Pe are connected to gate pads 34d and 34e embedded within the source electrode. The other three supply points Pa, Pb and Pc are connected to respectively corresponding gate pads 34a, 34b and 34c located on the drain electrode side of the gate electrode 32. 
     As will be appreciated herefrom, by adding two supply points Pa and Pb to the geometry of the first embodiment, the unit gate length Z u  can be reduced to Z t  /8 from the Z t  /6 value achieved by the first embodiment. In this case, the source electrode 32 can be held to a size comparable to that of the first embodiment of FIGS. 4 and 5. 
     FIG. 8 shows a third modification to the foregoing first embodiment of the semiconductor device, e.g. an FET, according to the invention. As in the first modification, a gate electrode 41 is provided with three supply points Pa, Pb and Pc. The supply points Pa and Pb are at opposite longitudinal ends of the gate electrode. The supply point Pc is at the longitudinal center of the gate electrode. The supply point Pc is connected to a gate pad 44c embedded within the source electrode 42 which is separated into two pieces. The supply points Pa and Pb are connected to gate pads 44a and 44b configured as longitudinal extensions of the gate electrode. 
     This third modification would have substantially the same properties as the first modification of FIG. 6. 
     FIGS. 9 and 10 show the second embodiment of the semiconductor device according to the invention, which prevents increase in the drain-gate capacitance C dg  while allowing the unit gate length Z u  to be shortened to substantially the same degree as in the first embodiment. 
     In this second embodiment, FET 50 has essentially the same geometry as disclosed with respect to the first embodiment of the invention. For instance, the FET generally comprises a gate electrode 51, a source electrode 52 and a drain electrode 53. As shown in FIG. 10, the source electrode 52 and the drain electrode 53 are located on opposite sides of the gate electrode 51. The edges of the source electrode 52 and the drain electrode 53 opposing the gate electrode 51 are separated by a distance L S-D  which is short enough to prevent generation of a gate-source capacitance C gs  or a drain-gate capacitance C dg  large enough to affect the performance of the FET. 
     The source electrode 52 is electrically connected to a source region 50S formed in the semiconductor base 50 made, for example, of GaAs. Likewise, the drain electrode 53 is electrically connected to a drain region 50D. 
     As in the first embodiment, the gate electrode 51 has three supply points Pa, Pb and Pc. The supply point Pc is at the longitudinal center of the gate electrode 51 and supply points Pa and Pb are each located one-sixth of the length of the gate electrode 51 from the opposite longitudinal ends of the gate electrode. 
     The supply points Pa and Pb are connected to gate pads 54a and 54b respectively which are on the same side of the gate electrode as the source electrode 52 and surrounded by the latter. On the other hand, the supply point Pc is connected to a gate pad 54c which is located on the drain electrode side. The gate pad 54c lies between the two separate elements making up the drain electrode 53. 
     In this second embodiment, a pair of shielding electrodes 55a and 55b extend from the longitudinal edges of the source electrode 52 past the ends of the gate electrode 51 onto the drain electrode side and partially surround the gate pad 54c. The shielding electrodes 55a and 55b cooperate to isolate the gate pad 54c from the drain electrode 53 in order to limit the drain-gate capacitance C dg . In the case shown in FIG. 9, the shielding electrodes 55a and 55b are connected to the source electrode, but this need not necessarily be the case. The shielding electrodes of this second embodiment need only be interposed between the gate pad 54c and the drain electrode 53 to provide the additional effect of preventing the increase in the drain-gate capacity C dg  incurred in the first embodiment. 
     As shown in FIG. 11, the shielding electrodes 56a, 56b can be directly connected to the semiconductor substrate 50 for grounding. This geometry has substantially the same effect as the embodiment of FIGS. 9 and 10. 
     Furthermore, in the shown embodiment, it is possible to use a single gate pad 64 connected to a single supply point P on the gate electrode on the drain electrode side due to the effect of shielding electrodes 65a and 65b, as shown in FIG. 12. In this modification, as in the embodiment shown in FIGS. 9 and 10, the shielding electrodes 65a and 65b are connected to a source electrode 62. In this case, since the source electrode 63 need not accommodate the gate pad, the chip size can be reduced. 
     FIG. 13 shows another modification to the second embodiment of FIGS. 9 and 10, which may also be considered to be a modified version of the embodiment of FIG. 6. Gate pads 74a and 74b located to either side of a drain electrode 73 are shielded from the drain electrode by shielding electrodes 75a, 75b. The gate pads 74a and 74b are connected to supply points Pa and Pb of the gate electrode 71. On the other hand, as explained with respect to the embodiment of FIG. 6, a gate pad 74c for a central supply point Pc on the gate electrode 71 is located on the source electrode side and surrounded by the source electrode 72. 
     The shielding electrodes 75a and 75b are connected to the source electrode 72. 
     Therefore, according to this modification, the shielding effect can be obtained in addition to the unit gate length reduction achieved by the foregoing embodiment of FIG. 6. 
     In summary, according to the present invention, the noise figure NF of an ultra-high-frequency semiconductor device, e.g. FET can be reduced significantly without increasing the chip size and without additionally complicated fabrication techniques. 
     While the present invention has been disclosed in terms of the preferred embodiments, the invention is not limited to those preferred embodiments. The invention should be understood to include all possible embodiments and modifications of the shown embodiments which can be embodied without departing from the principles of the invention set out in the appended claims.