Abstract:
An output stage for an operational amplifier includes a dynamically activated CMOS drive circuit that is arranged to improve the drive characteristics of the operational amplifier. The output stage includes bipolar transistors that are arranged to clamp the signal swing at an intermediary node in the operational amplifier. The bipolar transistors activate respective portions of the CMOS drive circuit based on the signal drive at the intermediary node. The CMOS driver circuit includes a p-type field effect transistor that sources additional current into the output signal when active, and an n-type field effect transistor that sinks additional current from the output terminal when active. The output stage may include additional circuitry to ensure that parasitic capacitances associated with the gates of the p-type field effect transistor and the n-type field effect transistors are discharged at appropriate times such that power consumption is reduced and high-speed operation is enhanced.

Description:
FIELD OF THE INVENTION 
     The present invention is related to operational amplifier output stages. More particular, the present invention is related to an output stage that includes a dynamically activated CMOS drive circuit that is arranged to improve the drive characteristics of the operational amplifier. Additional circuitry may be arranged to enhance the high frequency performance of the CMOS drive circuit by discharging critical nodes and reducing the quiescent current of the operational amplifier. 
     BACKGROUND OF THE INVENTION 
     Operational amplifiers are a basic building block in electronic systems. Typical operational amplifiers are two-stage amplifiers that include an input stage and an output stage. The input stage is arranged to receive a differential input signal and provide an intermediary signal at an intermediary node. The differential input signal is related to the differential input signal according to a first gain. The output stage is arranged to receive the intermediary signal and provide an output signal to an output node. The output signal is related to the intermediary signal according to a second gain. The output signal is related to the differential input signal according to the product of the first and second gains. 
     Two-stage operational amplifiers often have high gain levels that may become unstable at high frequencies. Instability in the operational amplifier may cause problems such as oscillations in the output signal. An AC compensation circuit is coupled to a high gain node in the operational amplifier to reduce the gain such that the operational amplifier is stable over all relevant operating frequencies. The AC compensation circuit is often provided between the intermediary node and the output node. The AC compensation circuit reduces high frequency gain by bypassing the output stage. 
     SUMMARY OF THE INVENTION 
     Briefly stated, an output stage for an operational amplifier includes a dynamically activated CMOS drive circuit that is arranged to improve the drive characteristics of the operational amplifier. The output stage includes bipolar transistors that are arranged to clamp the signal swing at an intermediary node in the operational amplifier. The bipolar transistors activate respective portions of the CMOS drive circuit based on the signal drive at the intermediary node. The CMOS driver circuit includes a p-type field effect transistor that sources additional current into the output signal when active, and an n-type field effect transistor that sinks additional current from the output terminal when active. The output stage may include additional circuitry to ensure that parasitic capacitances associated with the gates of the p-type field effect transistor and the n-type field effect transistors are discharged at appropriate times such that power consumption is reduced and high-speed operation is enhanced. 
     A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of an operational amplifier that includes an output stage; and 
     FIG. 2 is a schematic diagram of another operational amplifier that includes an output stage, in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediary devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” means at least one current signal, voltage signal or data signal. The meaning of “a”, “an”, and “the” include plural references. The meaning of “in” includes “in” and “on”. 
     In accordance with the present invention, an output stage is arranged to improve the drive performance of an operational amplifier. An input stage of the operational amplifier provides an intermediary signal to an intermediary node in response to a differential input signal. The output stage includes a transconductance amplifier that is arranged to provide an output signal to a load in response to the intermediary signal. A bipolar transistor circuit is coupled to the intermediary node. A PMOS transistor circuit is arranged to provide additional current drive to the output signal when the intermediary signal swings below a mid-supply voltage by a first predetermined amount. An NMOS transistor circuit is arranged to provide additional current sinking to the output signal when the intermediary signal swings below the mid-supply voltage by a second predetermined amount. The bipolar transistor circuit determines the first and second predetermined amounts. The output stage is arranged such that large capacitive loads may be driven. 
     Operational amplifiers that are arranged in accordance with the present invention have been implemented using BiCMOS technology. The operational amplifiers provide rail-to-rail input and output performance with a gain-bandwidth of 50 MHz, while drawing 600 uA of quiescent current, and providing 90 mA of drive current to a capacitive load of 1000 pF. 
     FIG. 1 is a schematic diagram of an operational amplifier ( 100 ) that includes an exemplary output stage that is arranged in accordance with the present invention. The operational amplifier ( 100 ) includes an input stage, an output stage, and a compensation circuit. The input stage includes a first transconductance amplifier (X 1 ). The output stage includes a second transconductance amplifier (X 2 ), a bipolar transistor circuit, a PMOS transistor circuit, and an NMOS transistor circuit. The bipolar transistor circuit includes an NPN transistor (Q 1 ) and a PNP transistor (Q 2 ). The NMOS transistor circuit includes a first NMOS transistor (MN 1 ) and a second NMOS transistor (MN 2 ). The PMOS transistor circuit includes a first PMOS transistor (MP 1 ) and a second PMOS transistor (MP 2 ). The compensation circuit includes a compensation capacitor (Ccomp). 
     The first transconductance amplifier (X 1 ) includes an inverting input that is coupled to a non-inverting input terminal (INP), a non-inverting input that is coupled to an inverting input terminal (INM), and an output that is coupled to a first node ( 1 ). The second transconductance amplifier (X 2 ) includes an inverting input that is coupled to the first node ( 1 ), a non-inverting input that is coupled to a mid-supply voltage (Vcc/2), and an output that is coupled to an output terminal (OUT). The NPN transistor (Q 1 ) includes a collector that is coupled to a second node ( 2 ), a base that is coupled to the mid-supply voltage (Vcc/2), and an emitter that is coupled to the first node ( 1 ). The PNP transistor (Q 2 ) includes a collector that is coupled to a third node ( 3 ), a base that is coupled to the mid-supply voltage (Vcc/2), and an emitter that is coupled to the first node ( 1 ). The first NMOS transistor (MN 1 ) includes a drain and gate that is coupled to the third node, and a source that is coupled to a circuit ground. The second NMOS transistor (MN 2 ) includes a drain that is coupled to the output terminal (OUT), a gate that is coupled to the third node ( 3 ), and a source that is coupled to the circuit ground. The first PMOS transistor (MP 1 ) includes a drain and gate that is coupled to the second node, and a source that is coupled to a power supply voltage (Vcc). The second PMOS transistor (MP 2 ) includes a drain that is coupled to the output terminal (OUT), a gate that is coupled to the second node ( 2 ), and a source that is coupled to the power supply voltage (Vcc). Capacitor Ccomp is coupled between node  1  and the output terminal to provide stable operation of the operational amplifier. 
     In operation, a differential input signal is applied across the differential input terminals (INP, INM) and a load (ZL) is coupled to the output terminal. The first transconductance amplifier provides an intermediary signal to the first node ( 1 ) in response to the differential input signal. The second transconductance amplifier is arranged to provide an output signal to the output terminal when the intermediary signal has a level that is sufficiently low such that the bipolar transistor circuit is inactive. Transconductance amplifier X 2  will drive the output terminal to equalize node  1  to the same voltage as the non-inverting input of transconductance amplifier X 2 . Under typical operating conditions, node  1  will have an associated voltage that corresponds to the mid-supply voltage, which is coupled to the non-inverting input of the second transconductance amplifier (X 2 ). Transistors Q 1  and Q 2  are biased by the mid-supply voltage such that neither transistor is active when the first node corresponds to the mid-supply voltage. 
     Transistor Q 1  is active when the voltage associated with node  1  decreases below the mid-supply voltage by a first predetermined amount (amt 1 ), and transistor Q 2  is active when the voltage associated with node  1  increases above the mid-supply voltage by a second predetermined amount (amt 2 ). The first predetermined amount (amt) corresponds to the forward bias voltage of transistor Q 1  (e.g., 0.6V), while the second predetermined amount (amt 2 ) corresponds to the forward bias voltage of transistor Q 2  (e.g., −0.6V). The bipolar transistor circuit is arranged to operate as a peak detector circuit that detects peaks in the signal swing of the first node ( 1 ) above the mid-supply voltage. Also, each of transistors Q 1  and Q 2  limits the signal swing at the first node ( 1 ) such that the voltage associated with the first node ( 1 ) does not swing beyond mid-supply voltage by the first and second predetermined amounts. 
     Transconductance amplifier X 2  provides current to load ZL when the voltage associated with the first node ( 1 ) is below the mid-supply voltage (Vcc/2). Transistor MP 2  is arranged to provide additional current to the load (ZL) to assist transconductance amplifier X 2  when the drive associated with the first node ( 1 ) is sufficient to activated transistor Q 1 . The PMOS circuit is inactive when transistor Q 1  is inactive. Thus, when the voltage associated with the first node ( 1 ) is greater than ([Vcc/2]−amt 1 ), transistors MP 1  and MP 2  are also inactive and no current is provided to the load from transistor MP 2 . Transistor Q 1  is forward biased such that current flows through transistor MP 1  when the voltage associated with the first node ( 1 ) is less than ([Vcc/2]−amt 1 ). Transistor MP 1  is arranged in a current-mirror configuration with transistor MP 2  such that transistor MP 2  is biased in active operation when transistor MP 1  is active. Transistor MP 2  is arranged to provide additional current drive to the load (ZL) when active. 
     Transconductance amplifier X 2  sinks current from load ZL when the voltage associated with the first node ( 1 ) is above the mid-supply voltage (Vcc/2). Transistor MN 2  is arranged to sink additional current from load ZL such that transconductance amplifier X 2  is assisted when the drive associated with the first node ( 1 ) is sufficient to activated transistor Q 2 . The NMOS circuit is inactive when transistor Q 2  is inactive. Thus, when the voltage associated with the first node ( 1 ) is less than ([Vcc/2]+amt 2 ), transistors MN 1  and MN 2  are also inactive and no current sinking from the load is provided by transistor MN 2 . Transistor Q 2  is forward biased such that current flows through transistor MN 1  when the voltage associated with the first node ( 1 ) is greater than ([Vcc/2]+amt 2 ). Transistor MN 1  is arranged in a current-mirror configuration with transistor MN 2  such that transistor MN 2  is biased in active operation when transistor MN 1  is active. Transistor MN 2  is arranged to provide additional current sinking from load ZL when active. 
     In one example, transconductance amplifiers X 1  and X 2  are bipolar transistor amplifiers. The nodes in the bipolar transistor amplifier may be clamped such that the base-emitter junctions are prevented from zenering under certain operating conditions. The bipolar transistor circuit described previously above is arranged to limit (or clamp) the inverting input of the second transconductance amplifier. The clamping of transistors in the bipolar transistor amplifier may result in limited output current capabilities. The MOS circuits described-above are arranged to provide additional sourcing and sinking currents such that the MOS circuits assist the bipolar transistor amplifiers in driving the load. The MOS circuits also assist the output signal swing in achieving rail-to-rail performance. 
     FIG. 2 is a schematic diagram of another operational amplifier ( 200 ) that includes an exemplary output stage that is arranged in accordance with the present invention. The operational amplifier ( 200 ) includes an input stage, an output stage, and a compensation circuit. The input stage includes a first transconductance amplifier (X 1 ). The output stage includes a second transconductance amplifier (X 2 ), a bipolar transistor circuit, a PMOS transistor circuit, an NMOS transistor circuit, a pair of clamp circuits, and a pair of peak detector circuits. The bipolar transistor circuit includes an NPN transistor (Q 1 ) and a PNP transistor (Q 2 ). The NMOS transistor circuit includes a first NMOS transistor (MN 1 ) and a second NMOS transistor (MN 2 ). The PMOS transistor circuit includes a first PMOS transistor (MP 1 ) and a second PMOS transistor (MP 2 ). The compensation circuit includes a compensation capacitor (CCOMP). Each clamp circuit includes a diode (D 1 , D 2 ). The peak detector circuits (X 3 , X 4 ) include a third NMOS transistor (MN 3 ), a fourth NMOS transistor (MN 4 ), a third PMOS transistor (MP 3 ), and a fourth PMOS transistor (MP 4 ). 
     The arrangement of like parts and nodes are labeled identically in FIG.  1  and FIG.  2 . FIG. 2 is similar to FIG. 1, except for the addition of the clamp circuits, and the peak detector circuits (X 3 , X 4 ). Diode D 1  is coupled between node  2  and the mid-supply voltage (Vcc/2). Diode D 2  is coupled between the mid-supply voltage (Vcc/2) and node  3 . The third NMOS transistor (MN 3 ) includes a drain and gate that are coupled to node  3 , and a source that is coupled to node  4 . The fourth NMOS transistor (MN 4 ) includes a drain that is coupled to node  3 , a gate that is coupled to node  4 , and a source that is coupled to the circuit ground. The third PMOS transistor (MP 3 ) includes a drain and gate that are coupled to node  2 , and a source that is coupled to node  5 . The fourth PMOS transistor (MP 4 ) includes a drain that is coupled to node  2 , a gate that is coupled to node  5 , and a source that is coupled to the power supply voltage (Vcc). 
     The basic operation of the operational amplifier described in FIG. 2 is substantially similar to the operation described with respect to FIG.  1 . However, the additional clamp and peak detector circuits are arranged to enhance the high frequency performance of the circuit, and to minimize the overall power consumption. Transistor MP 1  and MP 2  include parasitic capacitances that are associated with node  2 . Similarly, transistors MN 1  and MN 2  include parasitic capacitances that are associated with node  3 . When the intermediary signal at node  1  changes rapidly, transistors Q 1  and Q 2  are activated and deactivated in a short time interval. The parasitic capacitances at nodes  2  and  3  store charge when their respective conduction paths are active via transistors Q 1  and Q 2 . The parasitic capacitances associated with nodes  2  and  3  may store sufficient charge such that transistors MP 2  and MN 2  are active at the same time, resulting in high current consumption. 
     Transistors MN 3  and MN 4  are arranged in a configuration that is similar to a Darlington pair. Transistor MN 4  has a parasitic capacitance associated with the gate at node  4 . Transistors MN 3  provides a charge conduction path to node  4  when active such that the gate of transistor MN 4  is charged. Transistor MN 3  is active when the voltage associated with node  3  corresponds to two threshold voltages above the circuit ground. The voltage associated with node  3  corresponds to two threshold voltages above the circuit ground when the load (ZL) is demanding heavier current sinking (a hard drive condition). Thus, the parasitic capacitance at node  4  is charged and transistor MN 4  is activated when the hard drive condition is present (Q 2  is active). When transistor MN 3  is deactivated there is no conduction path (other than leakage) to discharge node  4 , and transistor MN 4  remains active even though transistor Q 2  is inactive. Transistor MN 4  is arranged to discharge the parasitic capacitance at node  3  when transistor Q 2  turns off, such that transistor MN 2  is deactivated and power consumption is reduced. Transistors MN 3 -MN 4  are arranged to shut off transistor MN 2  to enhance high-speed performance of the operational amplifier. 
     Transistors MP 3  and MP 4  are also arranged in a configuration that is similar to a Darlington pair. Transistor MP 4  has a parasitic capacitance associated with the gate at node  5 . Transistors MP 3  provides a charge conduction path from node  5  when active such that the gate of transistor MP 4  is charged low. Transistor MP 3  is active when the voltage associated with node  2  corresponds to two threshold voltages below the supply voltage. The voltage associated with node  2  corresponds to two threshold voltages below the supply voltage when the load (ZL) is demanding heavier current drive (a hard drive condition). Thus, the parasitic capacitance at node  5  is charged low and transistor MP 4  is activated when the hard drive condition is present (Q 1  is active). When transistor MP 3  is deactivated there is no conduction path (other than leakage) to discharge node  5 , and transistor MP 4  remains active even though transistor Q 1  is inactive. Transistor MP 4  is arranged to discharge the parasitic capacitance at node  2  to the power supply voltage (Vcc) when transistor Q 1  turns off, such that transistor MP 2  is deactivated and power consumption is reduced. Transistors MP 3 -MP 4  are arranged to shut off transistor MP 2  to enhance high-speed performance of the operational amplifier. 
     Diode D 1  is couples to across the base and collector of transistor Q 2  such that the collector voltage of transistor Q 2  is limited. The collector voltage of transistor Q 2  is limited to a diode voltage below the mid-supply voltage (Vcc/2). Diode D 1  is thus arranged to operate as a clamp circuit that limits the collector voltage and prevents transistor Q 2  from becoming saturated. Similarly, diode D 2  is coupled across the base and collector of transistor Q 1  such that the collector voltage of transistor Q 1  is limited. The collector voltage of transistor Q 1  is limited to a diode voltage above the mid-supply voltage (Vcc/2). Diode D 2  is thus arranged to operate as a clamp circuit that limits the collector voltage and prevents transistor Q 1  from becoming saturated. 
     The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.