Abstract:
A photocell used with an optical mouse, a CMOS sensor of a digital camera module, or a scanner includes a photo element in which a feedback circuit to maintain a base terminal voltage of the photo element constant, is not directly connected to a base terminal to control the voltage to directly maintain an emitter terminal voltage so that a stable bias voltage is generated compared to a conventional photo element. The photocell includes a stepping element to increase the voltage applied to the base terminal of the photocell, thereby improving sensitivity of the photocell and increasing effectiveness of light.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of Korean Patent Application No. 2004-13106 filed with the Korea Industrial Property Office on Feb. 26, 2004, the disclosure of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a photocell constituting a photocell array, and more particularly, to a photocell used with an optical mouse, a CMOS sensor of a digital camera module, or a scanner to maintain a uniform base terminal voltage of a phototransistor which is an amplifying element to form the photo element using a voltage stepping element and a voltage regulating loop circuit, to simultaneously generate a more stable bias voltage than a conventional circuit by increasing a base terminal voltage of the phototransistor, and to increase a light effectiveness by increasing a light sensitivity of the phototransistor.  
         [0004]     2. Description of the Related Art  
         [0005]     An IC is used with an optical mouse, a CMOS sensor of a digital camera module or a scanner to sense strength of light through a plurality of photocells to generate an image. In a case of the optical mouse, a movement direction of the optical mouse is transmitted to a PC according to the image sequentially caught in a time axis.  
         [0006]     The photocell is generally constituted of a sub-PNP type (substrate PNP type) transistor made using a conventional CMOS manufacturing process different from the photodiode.  
         [0007]     Since the conventional CMOS manufacturing process can be used to produce the sub-PNP type transistor, a cell library provided in a semiconductor manufacturing process can be used to secure a product reliability with a digital circuit, and a product developing period can be shortened according to a regulated flow of the manufacturing process to provide advantages in manufacturing the sub-PNP type transistor as the photocell.  
         [0008]     A characteristic of the sub-PNP type transistor can deteriorate more than a general photodiode because the CMOS manufacturing process is not a specialized process of manufacturing the sub-PNP type transistor, and therefore, the sub-PNP type transistor needs an additional circuit to compensate for the deteriorating characteristic.  
         [0009]     Since the additional circuit includes a plurality of arrays, the additional circuit should have a minimum size, and a design of the additional circuit should not be complicated. The sub-PNP type transistor should be satisfied with the above conditions, and the photocell is required to operate the sub-PNP type transistor at an optimized condition at the same time.  
         [0010]      FIG. 1  is a view showing a structure of a sub-PNP type transistor  100  manufactured using a conventional CMOS process. Referring to  FIG. 1 , the sub-PNP type transistor  100  has a vertical structure. Since a substrate  106  of a p type base forms a collector, the collector is always connected to ground  104 .  
         [0011]     In a conventional CMOS manufacturing process, a PNP or NPN element cannot be used unless an additional layer is added. However, the sub-PNP type transistor  100  can be realized using an n-well  105  and the p-substrate (substrate having the p type base)  106 . A SiO 2  layer  107  is formed (stacked) on the substrate  106 .  
         [0012]     As shown in  FIG. 1 , the p-substrate  106  of the sub-PNP type transistor  100  is always connected to the ground  104  to generate a reverse directional bias between a base terminal  101  and a collector terminal  103 . A depletion region is formed due to the reverse directional bias.  
         [0013]     In an area of the n-well  105 , chargers formed by light may be recombined through a recombination process, but the chargers can be converted into a current in the depletion region. Accordingly, the light should arrive the depletion region in order fro the photocell to react the light. In order for the light to arrive the depletion region, the depletion region should be formed to be disposed adjacent to a surface of the photocell, and thus, sensitivity of the photocell can be improved as a reverse direction voltage between the base terminal  101  and the collector terminal  103  increases.  
         [0014]     A CMOS (complementary MOSFET) has a structure having P- or N-doping formed on p-doped silicon, and a general CMOS is an NMOS or a PMOS. A conventional CMOS manufacturing process includes a method of doping the P or N doped on a base substrate. This conventional CMOS manufacturing process also includes a manufacturing method of forming a bipolar junction transistor (BJT) having a PNP bonding.  
         [0015]     In contrast to the CMOS manufacturing process, the PNP or NPN bonding element is used to manufacture the BJT, and also a bi0CMOS manufacturing process can be used to use all of PNP, NPN, NMOS, and PMOS elements.  
         [0016]     A photocell circuit includes a charging capacitor charging and discharging an electrical signal, and also includes a bias circuit or a stabilizing circuit to maintain a uniform base voltage of the phototransistor so as to stabilize an entire circuit by stabilizing an charging and discharging operation of the charging capacitor.  
         [0017]      FIG. 2  is a view showing a photocell having a bias circuit to maintain a uniform voltage of a base terminal of a conventional photo sensor.  
         [0018]     When a reset switch  207  is turned on, a charging capacitor  210  is charged to a predetermined voltage, for example 3.25V. A photodiode  203 , a phototransistor  201 , and a parasitic capacitor  202  form a photo element  204 .  
         [0019]     A current is generated when light is incident on the photodiode  203 , which is a photoreceptor, and the phototransistor  201  is turned on according to the generated current so that the chargers of the charging capacitor  210  is transmitted to ground through the phototransistor  201 . Accordingly, the charging capacitor  210  is discharged to a predetermined voltage.  
         [0020]     As shown in  FIG. 2 . a base node (terminal) of the phototransistor  201  is connected to a gate terminal of a first transistor  205 , and a drain terminal of the first transistor  205  is connected to a constant current source and a gate terminal of a second transistor  208 .  
         [0021]     A source terminal of the second transistor  208  is connected to an emitter terminal of the phototransistor  201 . The second transistor  208  is operated as a source follower to transmit a drain voltage of the first transistor  205  to the emitter terminal of the phototransistor  201 . The source follower is a circuit to transmit an input AC signal as an output AC signal. That is, although a DC bias is changed, an amplitude of an input signal has the same as an output signal in a circuit of the source follower. The AC signal inputted to the collector terminal of the second transistor  208  is transmitted to the collector terminal of the phototransistor  201  while maintaining the amplitude.  
         [0022]     A negative feedback loop having MOS transistors  205  and  208  is formed between the base terminal and the emitter terminal of the phototransistor  201 . With this native feedback loop, the bias voltage of the base terminal of the phototransistor  201  is maintained constant.  
         [0023]     That is, a voltage of the base terminal of the phototransistor  201  increases, a resistance of the first transistor  205  is decreased, and a voltage of the gate terminal of the second transistor  208  is decreased. According to a source follower operation of the second transistor  208 , a voltage of the emitter terminal of the first transistor  201  is decreased, and the voltage of the base terminal of the phototransistor  201  is decreased.  
         [0024]     The voltage of the base terminal of the phototransistor  201  decreases, the resistance of the first transistor  205  is increased, and the voltage of the gate terminal of the second transistor  208  is increased. According to the source follower operation of the second transistor  208 , the voltage of the emitter terminal of the first transistor  201  is increased, and the voltage of the base terminal of the phototransistor  201  is increased.  
         [0025]     After the charging capacitor  210  is discharged, the chargers charged in the charging capacitor  210  is transmitted to a transfer capacitor  211  when a read switch is turned on, and the transmitted chargers is amplified to be transmitted to an external circuit which reads the chargers (current).  
         [0026]     U.S. Pat. No. 5,769,384 discloses a photocell having a bias circuit to maintain a bias voltage constant to supply a base terminal of a phototransistor.  
         [0027]     However, since a voltage of the base terminal of the phototransistor shown in U.S. Pat. No. 5,769,384 is low, the sensitivity of the phototransistor is decreased, and light effectiveness of the phototransistor deteriorates.  
         [0028]     As described above, the bias voltage supplied to the base terminal of the phototransistor is required to be increased in order to solve problems occurring in a conventional circuit, and a photocell IC circuit is required to provide a simply and easily designed and manufactured structure while the light sensitivity of the photocell circuit is improved.  
       SUMMARY OF THE INVENTION  
       [0029]     In order to solve the above and/or other problems, it is an aspect of the present invention to provide a photocell forming a photocell array, the photocell being simple in designing and being able to operate a sub-PNP type transistor at an optimized state.  
         [0030]     It is another aspect of the present invention to provide a photocell generating a more stable phototransistor bias voltage by increasing a voltage of a base terminal of the phototransistor, which is an amplifying element of a photo element, to improve light effectiveness and sensitivity of the phototransistor.  
         [0031]     Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.  
         [0032]     The above and/or other aspects of the present invention can be achieved by providing a photocell including: a photo element having an emitter terminal and a base terminal to generate a current according to an incident light signal; a charging capacitor to discharge current charged therein when the light signal is inputted to the photo element; a voltage control circuit connected to the emitter terminal of the photo element to maintain a voltage of the emitter terminal of the photo element constant; and at least one voltage stepping element connected to the voltage control circuit to step the voltage of the emitter of the photo element by a predetermined segment.  
         [0033]     According to another aspect of the present invention, the photo element comprises a photo receptor to receive the light signal, and a current amplifier, and the photo receptor is connected to the base terminal of the current amplifier.  
         [0034]     According to yet another aspect of the present invention, the voltage of the base terminal of the photo element linearly varies according to a variation of a voltage of the emitter terminal of the photo element.  
         [0035]     According to still another aspect of the present invention, the photo element further includes a reset unit to reset the charging capacitor to charge the charging capacitor.  
         [0036]     According to still yet another aspect of the present invention, the photo element further includes a constant current source connected to the voltage control circuit to supply a constant current to the photo element.  
         [0037]     According to also an aspect of the present invention, the voltage stepping element comprises a MOS transistor having a drain terminal and a gate terminal connected to each other.  
         [0038]     According to another aspect of the present invention, the voltage stepping element comprises a diode.  
         [0039]     According to another aspect of the present invention, the voltage stepping element comprises a plurality of sub-voltage stepping elements connected in series.  
         [0040]     According to another aspect of the present invention, the voltage control circuit comprises a first MOS transistor and a second MOS transistor, a drain terminal of the first MOS transistor is connected to a gate terminal of the second MOS transistor, and a gate terminal of the first MOS transistor is connected to a source terminal of the second MOS transistor and an emitter terminal of the photo element.  
         [0041]     The above and/or other aspects of the present invention can also be achieved by providing a photocell including: a photo element having an emitter terminal and a base terminal to generate a current according to an incident light signal; a charging capacitor to discharge current charged therein when the light signal is inputted to the photo element; a voltage control circuit connected to the emitter terminal of the photo element to maintain a voltage of the emitter terminal of the photo element constant; at least one voltage stepping element connected to the voltage control circuit to step the voltage of the emitter of the photo element by a predetermined segment; and a shutter to control a discharging characteristic of the charging capacitor according to strength of light incident on the photo element.  
         [0042]     According to another aspect of the present invention, the photo element comprises a photo receptor to receive the light signal, and a current amplifier, and the photo receptor is connected to the base terminal of the current amplifier.  
         [0043]     According to yet another aspect of the present invention, the voltage of the base terminal of the photo element linearly varies according to a variation of a voltage of the emitter terminal of the photo element.  
         [0044]     According to still another aspect of the present invention, the photocell further includes a reset unit to reset the charging capacitor to charge the charging capacitor.  
         [0045]     According to still yet another aspect of the present invention, the photocell further includes a constant current source connected to the voltage control circuit to supply a constant current to the photo element.  
         [0046]     According to another aspect of the present invention, the voltage stepping element comprises a MOS transistor having a drain terminal and a gate terminal connected to each other.  
         [0047]     According to another aspect of the present invention, the voltage stepping element comprises a diode.  
         [0048]     According to another aspect of the present invention, the voltage stepping element comprises a plurality of sub-voltage stepping elements connected in series.  
         [0049]     According to another aspect of the present invention, the voltage control circuit includes a first MOS transistor and a second MOS transistor, a drain terminal of the first MOS transistor is connected to a gate terminal of the second MOS transistor, and a gate terminal of the first MOS transistor is connected to a source terminal of the second MOS transistor and an emitter terminal of the photo element.  
         [0050]     According to another aspect of the present invention, the discharging characteristic of the charging capacitor is a first speed when the strength of the light incident on the photo element is in a first state, and the discharging characteristic of the charging capacitor is a second speed slower than the first speed when the strength of the light incident on the photo element is in a second state weaker than the first state.  
         [0051]     The above and/or other aspects of the present invention can be also achieved by providing an automatic gain control method of a photocell, the method including: generating a current according to an incident light signal in a photo element having an emitter terminal and a base terminal; discharging current charged in a charging capacitor when the light signal is inputted to the photo element; maintaining a voltage of the emitter terminal of the photo element constant in a voltage control circuit connected to the emitter terminal of the photo element; and controlling the voltage of the emitter of the photo element to be constant in at least one voltage stepping element connected to the voltage control circuit.  
         [0052]     According to another aspect of the present invention, the maintaining of the voltage comprises maintaining a voltage of the base terminal of the photo element constant, and the voltage of the base terminal of the photo element linearly varies according to a variation of the voltage of the base terminal of the photo element.  
         [0053]     According to yet another aspect of the present invention, the automatic gain control method further includes charging the charging capacitor according to a reset signal.  
         [0054]     According to still another aspect of the present invention, the automatic gain control method further includes reading a voltage generated from the charging capacitor after the discharging of the charging capacitor is completed.  
         [0055]     The above and/or other aspects of the present invention can be also achieved by providing an automatic gain control method of a photocell, the method including: generating a current according to an incident light signal in a photo element having an emitter terminal and a base terminal; discharging current charged in a charging capacitor when the light signal is inputted to the photo element; controlling a discharging time of the charging capacitor according to the light signal in a shutter; maintaining a voltage of the emitter terminal of the photo element constant in a voltage control circuit connected to the emitter terminal of the photo element; and controlling the voltage of the emitter of the photo element to be constant in at least one voltage stepping element connected to the voltage control circuit.  
         [0056]     According to another aspect of the present invention, the maintaining of the voltage comprises maintaining a voltage of the base terminal of the photo element constant.  
         [0057]     According to yet another aspect of the present invention, the voltage of the base terminal of the photo element linearly varies according to a variation of the voltage of the base terminal of the photo element.  
         [0058]     According to still another aspect of the present invention, the automatic gain control method further includes charging the charging capacitor according to a reset signal.  
         [0059]     According to still yet another aspect of the present invention, the charging capacitor is discharged when a shutter signal is a first state in the shutter, and the discharging of the charging capacitor is stopped when the shutter signal is a second state in the shutter.  
         [0060]     According to yet another aspect of the present invention, the automatic gain control method further includes reading a voltage generated from the charging capacitor after the discharging of the charging capacitor is completed.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0061]     These and/or other aspects and advantages of the present invention will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:  
         [0062]      FIG. 1  is a view showing a structure of a sub-PNP type transistor manufactured using a conventional CMOS process;  
         [0063]      FIG. 2  is a view showing a photocell having a bias circuit to maintain a uniform voltage of a base terminal of a conventional photo sensor;  
         [0064]      FIG. 3  is a view showing a photocell according to an embodiment of the present invention;  
         [0065]      FIG. 4  is a view showing an MOSFET used with the photocell shown in  FIG. 3 ;  
         [0066]      FIG. 5  is a view showing a photocell according to another embodiment of the present invention; and  
         [0067]      FIG. 6  is a graph showing outputs of the photocell of  FIGS. 3 and 5  and a conventional photocell when light is incident on the photocell of  FIGS. 3 and 5  and the conventional photocell, respectively. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0068]     Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.  
         [0069]      FIG. 3  is a view showing a photocell  300  according to an embodiment of the present invention.  
         [0070]     A photocell element  301  may include a photodiode  302  to receive a light signal, generate a current in response to the received light signal, and amplify the generated current, and a phototransistor  303  to amplify the current generated from photodiode  302  as an amplifying element.  
         [0071]     A voltage control circuit  304  may include a first MOS transistor  305  and a second MOS transistor  306  to maintain a base terminal voltage V bnode  constant according to this embodiment.  
         [0072]     As shown in  FIG. 3 , the voltage control circuit  304  may include the first MOS transistor  305  and the second MOS transistor  306 , a drain terminal of the first MOS transistor  305  is connected to a gate terminal of the second MOS transistor  306 , and a gate terminal of the first MOS transistor  305  can be connected to a source terminal of the second MOS transistor  306  and an emitter terminal of the phototransistor  303 .  
         [0073]     When a voltage V emt  of the emitter terminal of the phototransistor  303  is increased, a resistance of the first MOS transistor  305  is decreased, a voltage of the gate terminal of the second MOS transistor  306  is decreased, a voltage of a source terminal of the second MOS transistor  306  is decreased, and accordingly the voltage V emt  of the emitter terminal of the phototransistor  303  is increased. When the voltage V emt  of the emitter terminal of the phototransistor  303  is decreased, the resistance of the first MOS transistor  305  is increased, a voltage of a drain terminal of the first MOS transistor, that is, the voltage of the gate terminal of the second MOS transistor  306 , is increased, and accordingly the voltage V emt  of the emitter terminal of the phototransistor  303  is increased 
        According to the above-described mechanism of the photocell  300 , the voltage V emt  of the emitter terminal of the phototransistor  303  can be maintained a constant voltage, and also the voltage V bnode  of the base terminal of the phototransistor  303  can be maintained constant.        
 
         [0075]     In the photocell  300  according to this embodiment, one or more voltage stepping elements  307  can be connected to the first MOS transistor  305  to increase the voltage V bnode  of the emitter terminal maintained by the above-described mechanism. In this embodiment as shown in  FIG. 3 , an MOS transistor having a drain terminal and a gate terminal, which are connected to each other, is used as the one or more voltage stepping elements  307 . When a number of MOS transistors are connected, the voltage V bnode  can be increased according to a total voltage proportional to a multiplication of a threshold voltage and the number of the voltage stepping elements  307 , thereby increasing a reverse directional bias voltage applied to the base terminal of the phototransistor  303 .  
         [0076]     According to another aspect of the present invention, a diode or a resistance element having a predetermined threshold voltage can be used as the voltage stepping element  307 .  
         [0077]     A base terminal of the phototransistor  303  is an input terminal to receive an optical signal and is in an open state.  
         [0078]     The constant current source  308  is a portion of a mirror circuit to supply a current to operate the photocell  300 .  
         [0079]     An operation of the photocell will be described hereinafter.  
         [0080]     A bias voltage can be inputted from the constant current source  308  as a bias signal, such as less than ten nA. When a reset signal is inputted, a reset unit  309  is turned on, the charging capacitor  310  is charged to a predetermined voltage. When the light signal is inputted to the photodiode  302 , a current is generated to discharge a charged current from the charging capacitor  310  through the phototransistor  303 .  
         [0081]     Here, the voltage control circuit  304  maintains the voltage V bnode  of the emitter terminal of the phototransistor  303  constant using the above-described mechanism.  
         [0082]     During discharging the charging capacitor  310 , a remaining charge remaining on the charging capacitor  310  is outputted to an external circuit to be read as an output.  
         [0083]     In the photocell  300  according to this embodiment of the present invention, the bias voltage applied to the base terminal of the phototransistor  303  is explained hereinafter.  
         [0084]      FIG. 4  is a view showing an n-channel MOSFET used with the photocell shown in  FIG. 3 . Referring to  FIG. 4 , when a transistor is saturated, a drain current i D  is as follows.  
               i   D     =           W   ⁢           ⁢     μ   0     ⁢     C   ox       L     ⁡     [         (       v   GS     -     V   T       )     ⁢     v   DS       -       v   DS   2     2       ]       ⁢     (     1   +     λ   ⁢           ⁢     v   DS         )               (   1   )               
         [0085]     When the transistor is not saturated, the drain current i D  is as follows.  
               i   D     =           W   ⁢           ⁢     μ   0     ⁢     C   ox       L     ⁡     [       (       v   GS     -     V   T       )     ⁢     v       DS   ⁡     (   sat   )       -       ⁢       v     DS   ⁡     (   sat   )       2     2       ]       ⁢     (     1   +     λ   ⁢           ⁢     v   DS         )               (   2   )                       ⁢     =         W   ⁢           ⁢     μ   0     ⁢     C   ox         2   ⁢   L       ⁢       (       v   GS     -     V   T       )     2     ⁢     (     1   +     λ   ⁢           ⁢     v   DS         )                               
 
         [0086]     Here, μ o (cm 2/volt·sec ) is a movement when an electrical field is zero, C ox (F/cm 2 ) i s  a unit of gate oxide capacitance per area, λ(volts −1 ) is a channel modulation parameter, V T =V TO +γ({square root}{square root over (2|ψ f |+|v BS |)}−{square root}{square root over (2|ψ f |)}), V TO  is a critical voltage when a bias is zero, γ(volts −0.5)  is a bulk critical parameter, and 2|ψ f |(volts) is a strong reverse surface potential.  
         [0087]     With respect to a p-channel MOSFET, the same formula as the above formula is used except a reverse direction of the current.  
         [0088]     According to the above formula (2), when the n channel MOS is saturated, λ&lt;&lt;1.  
               i   D     =       W     2   ⁢   L       ⁢           ⁢     μ   0     ⁢         C   ox     ⁡     (       v   GS     -     V   T       )       2               (   3   )                 v   GS     =           2   ⁢           ⁢     i   D           W   L     ⁢           ⁢     μ   0     ⁢     C   ox           +     V   T               (   4   )             
 
         [0089]     Referring to  FIG. 3 , when a voltage between the gate and the source of the voltage stepping element  307  is V GS1 , and a voltage between the gate and the source of the first MOS transistor  305  is V GS2 , V emt  is as follows. 
 
 V   emt   =V   GS1   +V   GS2    (5) 
 
         [0090]     When the drain voltage of the voltage stepping element  307  and the first MOS transistor  305  is I, V emt  is as follows.  
             Vemt   =           2   ⁢   I         μ   0     ⁢     C   ox     ⁢       W   1       L   1             +         2   ⁢   I         μ   0     ⁢     C   ox     ⁢       W   2       L   2             +     V   T1     +     V   T2               (   6   )             
 
         [0091]     In the above formula, a subscript  1  indicates the voltage stepping element  307 , and a subscript  2  indicates the first MOS transistor  305 .  
         [0092]     In  FIG. 3 , when V bnode =V emt −V be (7), a voltage of the base terminal of the phototransistor  303  is as follows.  
           A         (   8   )               Vbnode   =           2   ⁢   I         μ   0     ⁢     C   ox     ⁢       W   1       L   1             +         2   ⁢   I         μ   0     ⁢     C   ox     ⁢       W   2       L   2             +     V   T1     +     V   T2     -     V   be                             
 
         [0093]     In a conventional circuit, the voltage V bnode  of the base terminal is as follows.  
       Vbnode   =           2   ⁢   I         μ   0     ⁢     C   ox     ⁢     W   L           +     V   T     -     V     b   ⁢           ⁢   e             
 
         [0094]     According to the formulas (8) and (9), the voltage V bnode  can be increased higher than a conventional circuit using a W/L ratio of the voltage stepping element.  
         [0095]      FIG. 5  is a view showing a photocell  500  according to another embodiment of the present invention.  
         [0096]     A photocell element  301  may include a photodiode  502  to receive a light signal, generate a current in response to the received light signal, and amplify the generated current, and a phototransistor  503  to amplify the current generated from photodiode  502  as an amplifying element.  
         [0097]     The phototransistor  503  is a sub-PNP type transistor.  
         [0098]     A voltage control circuit  504  may include a first MOS transistor  505  and a second MOS transistor  506  to maintain a base terminal voltage V bnode  constant according to this embodiment.  
         [0099]     As shown in  FIG. 5 , the voltage control circuit  504  may include the first MOS transistor  505  and the second MOS transistor  506 , a drain terminal of the first MOS transistor  505  is connected to a gate terminal of the second MOS transistor  506 , and a gate terminal of the first MOS transistor  505  can be connected to both a source terminal of the second MOS transistor  506  and an emitter terminal of the phototransistor  503 .  
         [0100]     When a voltage V emt  of the emitter terminal of the phototransistor  503  is increased, a resistance of the first MOS transistor  505  is decreased, a voltage of the gate terminal of the second MOS transistor  506  is decreased, a voltage of a source terminal of the second MOS transistor  356  is decreased, and accordingly the voltage V emt  of the emitter terminal of the phototransistor  503  is increased. When the voltage V emt  of the emitter terminal of the phototransistor  503  is decreased, the resistance of the first MOS transistor  505  is increased, a voltage of a drain terminal of the first MOS transistor  505 , that is, the voltage of the gate terminal of the second MOS transistor  506 , is increased, and accordingly the voltage V emt  of the emitter terminal of the phototransistor  503  is increased  
         [0101]     According to the above-described mechanism of the photocell  500 , the voltage V emt  of the emitter terminal of the phototransistor  503  can be maintained a constant voltage, and also the voltage V bnode  of the base terminal of the phototransistor  503  can be maintained constant.  
         [0102]     In the photocell  500  according to this embodiment, one or more voltage stepping elements  507  can be connected to the first MOS transistor  505  to increase the voltage V bnode  of the emitter terminal maintained by the above-described mechanism. In this embodiment as shown in  FIG. 5 , an MOS transistor having a drain terminal and a gate terminal, which are connected to each other, is used as the one or more voltage stepping elements  507 . When a number of MOS transistors are connected, the voltage V bnode  can be increased according to a total voltage proportional to a multiplication of a threshold voltage and the number of the voltage stepping elements  507 , thereby increasing a reverse directional bias voltage applied to the base terminal of the phototransistor  503 .  
         [0103]     According to another aspect of the present invention, a diode or a resistance element having a predetermined threshold voltage can be used as the voltage stepping element  507 .  
         [0104]     A base terminal of the phototransistor  503  is an input terminal to receive an optical signal and is in an open state.  
         [0105]     A constant current source  508  is a portion of a mirror circuit to supply a current to operate the photocell  500 .  
         [0106]     An operation of the photocell  500  will be described hereinafter.  
         [0107]     A bias voltage can be inputted from the constant current source  308  as a bias signal, such as less than ten nA. When a reset signal is inputted, a reset unit  509  is turned on, the charging capacitor  510  is charged to a predetermined voltage. When the light signal is inputted to the photodiode  502 , a current is generated to discharge a charged current from the charging capacitor  510  through the phototransistor  503 .  
         [0108]     Here, the voltage control circuit  504  maintains the voltage V bnode  of the emitter terminal of the phototransistor  503  constant using the above-described mechanism.  
         [0109]     During discharging the charging capacitor  510 , a remaining charge remaining on the charging capacitor  510  is outputted to an external circuit to be read as an output.  
         [0110]     A shutter  511  controls a discharging time of the charges charged in the charging capacitor  510  according to a strength of light incident on the photo element  501 . That is, the discharging time of the charging capacitor  510  is determined from a time when the reset signal is changed to a low signal, to a time when an input of the shutter  511  is changed to a low signal. When the light strength is strong, the shutter  511  is turned on during a shortened period of time so that the discharging time of the charging capacitor  510  is shortened. However, the light strength is weak, the shutter  511  is turned on during an extended period of time so that the discharging time of the charging capacitor  510  is extended (lengthened).  
         [0111]     When the shutter  511  is shut (turned off), that is, the discharging of the charging capacitor  510  is finished (stopped), the voltage value due to the charges remaining on the charging capacitor  510  is outputted to an external circuit as an output signal V OUT .  
         [0112]     In the photocell  500  according to this embodiment of the present invention, the voltage V bnode  of the base terminal of the phototransistor  503  is higher than the voltage shown in Formula (10) and supplies the higher reverse directional bias voltage to the base terminal of the phototransistor  503  than a conventional circuit.  
         [0113]     Since the voltage of the base terminal of the photocell  500  is increased, the sensitivity of the photocell is improved.  
         [0114]     That is, referring to  FIG. 1 , a depletion region should be disposed adjacent to a surface of a photocell so that light reaches the depletion region of the sub-PNP type transistor, and the reverse directional voltage should be increased to dispose the depletion region adjacent to the surface. According to the embodiments of the present invention, the reverse directional voltage between the baser terminal and the emitter terminal is higher than a conventional circuit, thereby improving the sensitivity of the photocell.  
         [0115]      FIG. 6  is a graph showing outputs of the photocell shown in  FIGS. 3 and 5  and a conventional photocell when light is incident on the photocell of the present invention and the conventional photocell, respectively. When the light having the same strength is incident on the photocell, the read output voltage signals are shown in a solid line and a broken line.  
         [0116]     As shown in  FIG. 6 , when the light having the same strength is incident on the phototransistor, the output signal level of a conventional circuit B is about 1.79V according to a current generated from the incident light. However, the output signal level of the present embodiment circuit A is about 2.1V. The photocell of the present embodiment circuit A is improved by about 17% with respect to the same light having the same strength compared to the conventional circuit A.  
         [0117]     According to an aspect of the present invention, although the photocell has a minimum circuit size, the design of the photocell does not become complicated, and a plurality of photocells can be arranged using an additional circuit. In addition, the photocell can operate the sub-PNP type transistor at the optimized state.  
         [0118]     According to another aspect of the present invention, in the photocell circuit, the sensitivity of the phototransistor can be improved when the voltage of the base terminal of the phototransistor is increased.  
         [0119]     According to another aspect of the present invention, the voltage of the base terminal of the phototransistor can be higher than a conventional photocell circuit, thereby improving the light effectiveness of the phototransistor.  
         [0120]     The photocell described above is an example according to the embodiments of the present invention. However, the present invention is not limited thereto.  
         [0121]     Although a few embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and equivalents thereof.