Abstract:
A nonvolatile semiconductor memory according to an aspect of the invention includes a memory cell array and a power supply circuit. The memory cell array includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break the insulating film. The power supply circuit supplies to the memory cell a program voltage for the electric stress depending on a negative temperature coefficient the electric stress.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-5336, filed on Jan. 14, 2009, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a nonvolatile semiconductor memory, particularly to an OTP (One-Time Programmable) memory using an anti-fuse element. 
         [0004]    2. Description of the Related Art 
         [0005]    Recently, a nonvolatile memory which continuously retains information under the power off has been widely spread. In some applications of the nonvolatile memory, data is not repeatedly rewritten, but the data is written only once. As one of such applications, a nonvolatile semiconductor memory using an anti-fuse element has been proposed. 
         [0006]    The anti-fuse element initially becomes a high-resistance state by a function of an insulating film in the anti-fuse element. However, when a high voltage for an electric stress is applied to the anti-fuse element once, a composition of the insulating film is broken to lower an electric resistance. Thereby, one-bit data can be recorded in a nonvolatile manner. In order to prevent false read, it is necessary to completely break the insulating film. 
         [0007]    Generally, the breakdown feature of the insulating film depends on an applied voltage and an environmental temperature such that the time the insulating film is completely broken extends as the applied voltage or the environmental temperature decreases. Therefore, depending on the applied voltage or the environmental temperature, the insulating film is sometimes incompletely broken when the program operation is shortened. On the other hand, when the program operation is excessively lengthened, the excessive electric stress applied to the anti-fuse element, which causes a problem from the viewpoint of reliability. 
         [0008]    For example, Japanese Patent Application Laid-Open (JP-A) No. 2006-196079 discloses a technique in order to solve the problems. In the technique disclosed in JP-A No. 2006-196079, a function of sensing an insulation breakdown state is provided in a power supply circuit that supplies a voltage to the anti-fuse memory element, and the application of the voltage to the anti-fuse memory element is maintained until the insulating film is completely broken. Therefore, not only a good read characteristic is obtained, but also the excessive electric stress is not applied to the anti-fuse memory element because the program operation is performed only for a necessary time. 
         [0009]    However, in such cases, there is a problem that a program time varies by the applied voltage or the environmental temperature. 
       SUMMARY OF THE INVENTION 
       [0010]    In accordance with a first aspect of the invention, a nonvolatile semiconductor memory includes a memory cell array that includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break the insulating film; and a power supply circuit that supplies to the memory cell a program voltage for the electric stress depending on a negative temperature coefficient. 
         [0011]    In accordance with a second aspect of the invention, a nonvolatile semiconductor memory includes a memory cell array that includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break the insulating film, a time necessary to break the insulating film correlating with a temperature and the electric stress; and a power supply circuit that supplies to the memory cell a program voltage for the electric stress having the predetermined correlation with the temperature. 
         [0012]    In accordance with a third aspect of the invention, a nonvolatile semiconductor memory includes a memory cell array that includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break the insulating film; and a power supply circuit that includes a band gap reference circuit, the band gap reference circuit including plural resistance elements and plural diodes to generate a reference voltage, the plurality for resistance elements including a variable resistive element the power supply circuit generating a program voltage for the electric stress to supply the program voltage to the memory cell based on the reference voltage. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a graph illustrating voltage dependence of a breakdown time of a memory cell in a nonvolatile semiconductor memory according to an embodiment of the invention; 
           [0014]      FIG. 2  is a graph illustrating temperature dependence of the breakdown time of the memory cell in the nonvolatile semiconductor memory of the embodiment; 
           [0015]      FIG. 3  illustrates an operating concept of the nonvolatile semiconductor memory of the embodiment; 
           [0016]      FIG. 4  is a block diagram partially illustrating the nonvolatile semiconductor memory of the embodiment; and 
           [0017]      FIG. 5  is a circuit diagram illustrating a reference power supply voltage of the nonvolatile semiconductor memory of the embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0018]    A nonvolatile semiconductor memory according to an exemplary embodiment of the invention will be described below with reference to the drawings. 
         [0019]    [Characteristic of Anti-Fuse Memory Element] 
         [0020]    A characteristic of an anti-fuse memory element used in the embodiment will be described prior to the specific embodiment of the invention. 
         [0021]    The anti-fuse memory element has the substantially same structure as a normal MOS transistor, and information is stored based on whether a gate insulating film is broken or not. The gate insulating film is broken by applying a high voltage (hereinafter referred to as “program voltage”), and usually a pinhole having a diameter of about 50 nm is made by the breakage of the gate insulating film. Hereinafter a time until the pinhole is made since the program voltage is applied is referred to as “breakdown time”. 
         [0022]      FIG. 1  is a graph illustrating voltage dependence of the breakdown time of the anti-fuse memory element. In  FIG. 1 , a horizontal axis indicates a program voltage VPP, and a vertical axis indicates a breakdown time tBD. 
         [0023]    As can be seen from  FIG. 1 , the breakdown time tBD is about 30 μs at the program voltage VPP of 6.4 V, while the breakdown time tBD is about 3 μs at the program voltage VPP of 6.8 V. Therefore, the breakdown time tBD has a gradient of about −10 dB/0.4 V with respect to the program voltage VPP, and the breakdown time tBD has the high voltage dependence. 
         [0024]      FIG. 2  is a graph illustrating temperature dependence of the breakdown time of the anti-fuse memory element. In  FIG. 2 , a horizontal axis indicates an environmental temperature T, and a vertical axis indicates the breakdown time tBD. 
         [0025]    As can be seen from  FIG. 2 , the breakdown time tBD is about 10 μs at the environmental temperature T of 25° C., while the breakdown time tBD is about 1 μs at the environmental temperature T of 125° C. Therefore, the breakdown time tBD has a gradient of about −10 dB/100 K with respect to the environmental temperature T, and the breakdown time tBD has the high temperature dependence. 
         [0026]    In the embodiment, the breakdown time tBD is kept constant by utilizing the characteristics of  FIGS. 1 and 2 . That is, as illustrated in  FIG. 3 , the high program voltage VPP is applied at the low environmental temperature T (I in  FIG. 3 ), and the low program voltage VPP is applied at the high environmental temperature T (II in  FIG. 3 ). The temperature dependence can be cancelled by positively utilizing the voltage dependence of the breakdown time tBD of the anti-fuse memory element. 
         [0027]    [Entire Configuration] 
         [0028]    A configuration of the nonvolatile semiconductor memory of the embodiment will be described below. 
         [0029]      FIG. 4  is a block diagram partially illustrating the nonvolatile semiconductor memory of the embodiment. 
         [0030]    Referring to  FIG. 4 , the nonvolatile semiconductor memory includes a memory cell array  100 . The memory cell array  100  includes plural word lines WL&lt; 0 &gt; to &lt; 3 &gt;, plural bit lines BL&lt; 0 &gt; to &lt; 3 &gt;, and plural memory cells  110 . The word lines WL&lt; 0 &gt; to &lt; 3 &gt; and the bit lines BL&lt; 0 &gt; to &lt; 3 &gt; are orthogonal to each other. Each of the memory cells  110  is disposed in intersection portion of the word line and the bit line. The nonvolatile semiconductor memory also includes a row decoder  200  and a data buffer group  300 . The row decoder  200  is disposed at one end of the word line WL to selectively activate the word line WL. The data buffer group  300  is disposed at one end of the bit line BL, the data buffer group  300  amplifies a minute signal from the memory cell  110  during data read, and the data buffer group  300  drives the bit line BL according to data from the outside. The nonvolatile semiconductor memory also includes a power supply circuit  400  that supplies the program voltage VPP to the memory cell  110 . 
         [0031]    Each memory cell  110  of the memory cell array  100  includes an anti-fuse element  111  and a selection transistor  112 . Gates of the selection transistors  112  of the plural memory cells  110  arranged in the same row are commonly connected to each of the word lines WL&lt; 0 &gt; to WL&lt; 3 &gt;. Sources of the selection transistors  112  of the plural memory cells  110  arranged in the same column are commonly connected to each of the bit lines BL&lt; 0 &gt; to BL&lt; 3 &gt;. A drain of the selection transistor  112  is connected to one end of the anti-fuse element  111 . On the other hand, the other end of the anti-fuse elements  111  is connected to an output terminal of the power supply circuit  400 . 
         [0032]    The row decoder  200  includes word line selection logic circuits  210  and word line driving circuits  220 . The word line selection logic circuit  210  and the word line driving circuit  220  are connected to each of the word lines WL&lt; 0 &gt; to WL&lt; 3 &gt;. An output terminal of an OR gate  230  is connected to one of input terminals of the word line selection logic circuit  210 , and a write instruction signal WE and a read instruction signal RE are fed into the OR gate  230 . Address signals A&lt; 0 &gt; and A&lt; 1 &gt; are input to other input terminals of the word line selection logic circuit  210 . Inverting processing and non-inverting processing are performed to the address signals A&lt; 0 &gt; and A&lt; 1 &gt; such that one word line WL is uniquely selected according to states of the address signals A&lt; 0 &gt; and A&lt; 1 &gt;, and the address signals A&lt; 0 &gt; and A&lt; 1 &gt; are fed into the word line selection logic circuit  210 . An output of the word line selection logic circuit  210  is fed into the word line driving circuit  220 . The word line driving circuit  220  inverts the input states to drive each of the word lines WL&lt; 0 &gt; to WL&lt; 3 &gt;. 
         [0033]    The data buffer group  300  includes data buffers that are connected to the bit lines BL&lt; 0 &gt; to BL&lt; 3 &gt; respectively. Each data buffer includes a write buffer  310  and a sense amplifier  320 . The write buffers  310  receive data input signals D&lt; 0 &gt; to D&lt; 3 &gt; to drive the bit lines BL&lt; 0 &gt; to BL&lt; 3 &gt; when a write instruction signal WE is fed. The sense amplifiers  320  amplify minute potential differences between bit lines BL&lt; 0 &gt; to BL&lt; 3 &gt; and a reference potential VSAREF to output data output signals Q&lt; 0 &gt; to Q&lt; 3 &gt; when a read instruction signal RE is fed. 
         [0034]    The power supply circuit  400  includes a boosting circuit  440  and a reference power supply circuit  410 . The boosting circuit  440  boosts a supply voltage VDD to supply the program voltage VPP. The reference power supply circuit  410  supplies the reference voltage VREF having a negative temperature coefficient (negative correlation with respect to temperature). The power supply circuit  400  also includes a voltage dividing circuit  420  and a differential amplifier  430 . The voltage dividing circuit  420  includes series connection of a resistor  421  having a resistance value Ra and a variable resistor  422  having a resistance value Rb. The voltage dividing circuit  420  divides the fed back program voltage VPP to supply a monitor voltage VMON. The differential amplifier  430  compares the reference voltage VREF and the monitor voltage VMON, and the differential amplifier  430  supplies a boosting activation signal BACT according to the comparison result in order to activate the boosting circuit  440 . The power supply circuit  400  also includes a power switch  450  that is controlled by a read instruction signal RE to impart the supply voltage VDD to the memory cell  110  during data read. 
         [0035]    An operation of the nonvolatile semiconductor memory will be described below. 
         [0036]    When the power supply circuit  400  receives the write signal WE, the reference power supply circuit  410  generates and supplies the reference voltage VREF having the negative temperature coefficient. The reference voltage VREF and the monitor voltage VMON supplied from the voltage dividing circuit  420  are fed into a non-inverting input terminal (+) and an inverting input terminal (−) of the differential amplifier  430 , respectively. The differential amplifier  430  amplifies a difference between the reference voltage VREF and the monitor voltage VMON to generate the boosting activation signal BACT. The boosting activation signal BACT is transmitted to the boosting circuit  440 . Accordingly, the boosting circuit  440  is activated to generate the program voltage VPP that is higher than the supply voltage VDD. The program voltage VPP is simultaneously supplied to the memory cell  110  and the voltage dividing circuit  420 . The voltage dividing circuit  420  divides the program voltage VPP to supply the monitor voltage VMON from a connection point of the resistance element  421  and the variable resistive element  422 . Even if using a fixed resistance element instead of the variable resistive element  422 , the effect of the embodiment can be obtained. However, the use of the variable resistive element  422  can adjust a voltage dividing ratio to control a multiplying factor of the program voltage VPP to the reference voltage VREF. 
         [0037]    When the power supply circuit  400  receives the read signal RE, the reference power supply circuit  410  is not activated. On the other hand, because the power switch  450  is turned on when the power supply circuit  400  receives the read signal RE, the supply voltage VDD is supplied to the memory cell  110 . 
         [0038]    [Reference Power Supply Circuit] 
         [0039]    The reference power supply circuit  410  of the embodiment will be described below. The band gap reference circuit is used as the reference power supply circuit  410 . A normal band gap reference circuit generates a reference voltage that does not have the temperature dependence. On the other hand, in the reference power supply circuit  410  of the embodiment, the reference voltage VREF having the negative temperature coefficient is obtained by adjusting the resistance value of the resistor constituting the band gap reference circuit. 
         [0040]      FIG. 5  is a circuit diagram of the reference power supply circuit  410 . 
         [0041]    The reference power supply circuit  410  includes a first voltage generating circuit, a second voltage generating circuit, and an operational amplifying circuit  413 . The first voltage generating circuit generates a first voltage from the reference voltage VREF. The second voltage generating circuit generates a second voltage from the reference voltage VREF. The first voltage and the second voltage are fed into the operational amplifying circuit  413 , and the operational amplifying circuit  413  supplies the reference voltage VREF. 
         [0042]    The first voltage generating circuit includes a series-connected circuit of a resistance element  411  having a resistance value R 1  and a diode  412  whose anode is connected to the resistance element  411 . 
         [0043]    The second voltage generating circuit includes a series-connected of a resistance element  414 , a variable resistive element  415 , and a diode group  416 . The resistance element  414  is equal to the resistance element  411 . The variable resistive element  415  is means for adjusting the temperature coefficient. The diode group  416  includes  100  diodes  416   a,    416   b,  . . . that are connected in parallel. Each of the diodes  416   a,    416   b,  . . . constituting the diode group  416  has a characteristic equal to that of the diode  412  of the first voltage generating circuit. 
         [0044]    A non-inverting input terminal (+) of the differential amplifier  413  is connected to a connection point of the resistance element  411  and the diode  412  of the first voltage generating circuit. On the other hand, an inverting input terminal (−) of the differential amplifier  413  is connected to a connection point of the resistance element  414  and the variable resistive element  415  of the second voltage generating circuit. An output terminal of the differential amplifier  413  supplies the reference voltage VREF, and the output terminal of the differential amplifier  413  is connected to the non-inverting input terminal (+) and the inverting input terminal (−) through the resistance element  411  and the resistance element  414 . 
         [0045]    At this point, the differential amplifier  413 , the resistance element  414 , the variable resistive element  415 , and the diode group  416  constitute a feedback control circuit. Thereby, the output of the differential amplifier  413  as the reference voltage VREF is generated such that a voltage at the inverting input terminal (−) and a voltage at the non-inverting input terminal (+) of the differential amplifier  413  are equal to each other. As described above, one end of the resistance element  411  and one end of the resistance element  414  are commonly connected. On the other hand, because the other end of the resistance element  411  and the other end of the resistance element  414  are connected to the non-inverting input terminal (+) and inverting input terminal (−) of the differential amplifier  413 , the input terminals of the differential amplifier  413  becomes the identical voltage by action of the feedback control circuit. Because the resistance elements  411  and  413  have the same resistance value R 1 , an identical current Id 1  is passed through the resistance elements  411  and  414 . 
         [0046]    When the differential amplifier  413  is in a stable state, because no current flows into the non-inverting input terminal (+) of the differential amplifier  413 , the current Id 1  passed through the resistance element  411  is directly passed through the diode  412 . A relationship between the current Id 1  passed through the diode  412  and the voltage Vd 1  between both ends of the diode  412  can be expressed as follows: 
         [0000]      [Formula 1] 
         [0000]        Id 1= Is 1×{exp( Vd 1× q/kB/T )−1}  (1) 
         [0000]    Where Is 1  is a reverse saturation current of the diode  412 , q is an electron charge (1.602×10 −19  C), kB is a Boltzmann constant (1.381×10 −23  J/K), and T is the absolute temperature. At this point, assuming that the absolute temperature T is 300 K that is close to a room temperature, kB×T/q=26 mV is obtained. The equation (1) can be approximated to an equation (2) in a range where Vd 1  is sufficiently larger than 26 mV: 
         [0000]      [Formula 2] 
         [0000]        Id 1= Is 1×exp( Vd 1× q/kB/T )   (2) 
         [0000]    The equation (2) is deformed to obtain an equation (3): 
         [0000]      [Formula 3] 
         [0000]        Vd 1= kB×T/q ×log( Id 1/ Is 1)   (3) 
         [0047]    Similarly, when the differential amplifier  413  is in the stable state, because no current flows into the non-inverting input terminal (−) of the differential amplifier  413 , the current Id 1  passed through the resistance element  414  is directly passed through the variable resistive element  415 . A relationship between the current Id 2  passed through the diode group  416  and the voltage Vd 2  between both ends of the diode group  416  can be expressed as follows: 
         [0000]      [Formula 4] 
         [0000]        Vd 2= kB×T/q ×log( Id 2/ Is 2)   (4) 
         [0048]    At this point, the 100 diodes  416   a,    416   b,  . . . constituting the diode group  416  have the same characteristic as the diode  412 , so that equations (5) and (6) can be derived: 
         [0000]      [Formula 5] 
         [0000]        Id 1=100× Id 2   (5) 
         [0000]      [Formula 6] 
         [0000]        Is 1= Is 2= Is    (6) 
         [0000]    Accordingly, a potential difference ΔVd between Vd 1  and Vd 2  can be expressed as follows: 
         [0000]    
       
         
           
             
               
                 
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                      
                     7 
                   
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         [0000]    That is, as can be seen from the equation (7), the potential difference ΔVd is proportional to the temperature with a positive gradient. For example, ΔVd 300K =120 mV is obtained at T=300 K, and ΔVd 400K =160 mV is obtained at T=400 K. 
         [0049]    On the other hand, the voltage Vd between both the ends of the diode has a negative gradient with respect to the temperature: 
         [0000]      [Formula 8] 
         [0000]        d ( Vd )/ dT=− 2 m[V/K]  (8) 
         [0050]    Because a normal band gap reference circuit generates a reference voltage VBGR that does not have the temperature dependence, a resistance ratio R 1 /R 2  of the resistance elements  411  and  415  is adjusted such that the temperature coefficient −2 mV/K is cancelled. 
         [0051]    The reference voltage VBGR can be expressed as follows: 
         [0000]      [Formula 9] 
         [0000]        VBGR=R 1 /R 2×Δ Vd+Vd 1   (9) 
         [0000]    An equation (10) is obtained when both sides of the equation (9) are differentiated with respect to the temperature T: 
         [0000]      [Formula 10] 
         [0000]        d ( VBGR )/ dT=R 1/ R 2× d (Δ Vd )/ dT+d ( Vd )/ dT    (10) 
         [0000]    At this point, because of d(VBGR)/dT=0, R 1 /R 2  is expressed as follows: 
         [0000]    
       
         
           
             
               
                 
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                     Formula 
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                      
                     11 
                   
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                            
                           
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                            
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         [0052]    On the other hand, in the reference power supply circuit  410  of the embodiment, R 1 /R 2  is adjusted such that the output VREF has the temperature coefficient. It is assumed that the reference voltage VREF has the temperature coefficient of −0.5 mV/K. 
         [0053]    The reference voltage VREF is expressed as follows: 
         [0000]      [Formula 12] 
         [0000]        V REF= R 1/ R 2×Δ Vd+Vd 1   (12) 
         [0000]    An equation (13) is obtained when both sides of the equation (12) are differentiated with respect to the temperature T: 
         [0000]      [Formula 13] 
         [0000]        d ( V REF)/ dT=R 1/ R 2× d (Δ Vd )/ dT+d ( Vd )/ dT    (13) 
         [0000]    At this point, because of d(VREF)/dT=−0.5 mV/K, R 1 /R 2  is expressed as follows: 
         [0000]    
       
         
           
             
               
                 
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                   ( 
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         [0054]    In the reference power supply circuit  410 , assuming that Vd 1   300K =0.6 V is the voltage between the ends of the diode  412  at the absolute temperature T=300 K, ΔVd 300K =120 mV and R 1 /R 2 =3.75 are obtained. Therefore, the reference voltage VREF 300K  is obtained at the absolute temperature T=300 K by an equation (15): 
         [0000]    
       
         
           
             
               
                 
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                     Formula 
                      
                     
                         
                     
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                     15 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         
                           VREF 
                           
                             300 
                              
                             K 
                           
                         
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                                 300 
                                  
                                 K 
                               
                             
                           
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                              
                             
                               1 
                               
                                 300 
                                  
                                 K 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
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                             3.75 
                             × 
                             120 
                              
                             m 
                           
                           + 
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                         = 
                           
                          
                         
                           1.05 
                            
                           
                             [ 
                             V 
                             ] 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
         [0055]    At the absolute temperature T=400 K, because the temperature coefficient of the diode  412  becomes d(Vd)/dT=−2 mV/K, ΔVd 400K =160 mV, R 1 /R 2 =3.75, the reference voltage VREF 400K  is expressed as follows: 
         [0000]    
       
         
           
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     16 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         
                           VREF 
                           
                             400 
                              
                             K 
                           
                         
                         = 
                           
                          
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             
                               1 
                               / 
                               R 
                             
                              
                             
                                 
                             
                              
                             2 
                             × 
                             Δ 
                              
                             
                                 
                             
                              
                             
                               Vd 
                               
                                 400 
                                  
                                 K 
                               
                             
                           
                           + 
                           
                             ( 
                             
                               
                                 Vd 
                                  
                                 
                                     
                                 
                                  
                                 
                                   1 
                                   
                                     300 
                                      
                                     K 
                                   
                                 
                               
                               - 
                               
                                 2 
                                  
                                 m 
                                 × 
                                 100 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             3.75 
                             × 
                             160 
                              
                             m 
                           
                           + 
                           0.6 
                           - 
                           
                             2 
                              
                             m 
                             × 
                             100 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           1 
                            
                           
                             [ 
                             V 
                             ] 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   16 
                   ) 
                 
               
             
           
         
       
     
         [0056]    The obtained reference power supply VREF having the negative temperature dependence is fed into the non-inverting input terminal (+) of the differential amplifier  430 . On the other hand, the monitor voltage VMON generated by the voltage dividing circuit  420  is fed into the inverting input terminal (−) of the differential amplifier  430 . Because the voltage dividing circuit  420 , the differential amplifier  430 , and the boosting circuit  440  constitute the feedback control circuit, the program voltage VPP is controlled such that the reference power supply VREF is equal to the monitor voltage VMON. That is, the program voltage VPP is expressed from a voltage dividing ratio Rb/(Ra+Rb) of the voltage dividing circuit  420  by an equation (17): 
         [0000]      [Formula 17] 
         [0000]        VPP =( Ra+Rb )/ Rb×V REF   (17) 
         [0057]    At this point, Rb is set to 10 kΩ and Ra is set to 50 kΩ such that the voltage dividing ratio Rb/(Ra+Rb) becomes ⅙. In such cases, the reference voltage VREF 300K  is 1.05 V at the absolute temperature T=300 K, the reference voltage VREF 400K  is 1.0V at the absolute temperature T=400 K. Therefore, the program voltage VPP 300K  at the absolute temperature T=300 K and the program voltage VPP 400K  at the absolute temperature T=400 K are expressed as follows: 
         [0000]    
       
         
           
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     18 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         
                           VPP 
                           
                             300 
                              
                             K 
                           
                         
                         = 
                           
                          
                         
                           6 
                           × 
                           
                             VREF 
                             
                               300 
                                
                               K 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           6 
                           × 
                           1.05 
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           6.3 
                            
                           
                             [ 
                             V 
                             ] 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   18 
                   ) 
                 
               
             
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     19 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         
                           VPP 
                           
                             400 
                              
                             K 
                           
                         
                         = 
                           
                          
                         
                           6 
                           × 
                           
                             VREF 
                             
                               400 
                                
                               K 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           6 
                           × 
                           1.0 
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           6.0 
                            
                           
                             [ 
                             V 
                             ] 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   19 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The generated program voltage VPP is supplied to the anti-fuse element  110  during data write. The anti-fuse element  110  has a characteristic in which the breakdown time is shortened to 1/10 when the program voltage is increased by 0.3 V. The anti-fuse element  110  also has a characteristic in which the breakdown time is shortened to 1/10 when the environmental temperature is raised by 100° C. Accordingly, the program voltage VPP having the temperature dependence is supplied to the anti-fuse element  110 , so that the breakdown time can be kept constant irrespective of the environmental temperature. 
         [0058]    Even if using a fixed resistance element instead of the variable resistive element  415 , the effect of the embodiment can be obtained. However, the use of the variable resistive element  415  can easily adjust the temperature coefficient of the reference voltage VREF. 
         [0059]    [Write Operation and Read Operation] 
         [0060]    An operation of the nonvolatile semiconductor memory of the embodiment will be described below. 
         [0061]    First the write instruction signal WE is fed in a write operation. When receiving the write instruction signal WE, the power supply circuit  400  generates the program voltage VPP. At the same time, the row decoder  200  selects any one of the word lines WL according to the states of the address signals A&lt; 0 &gt; and A&lt; 1 &gt;. 
         [0062]    Then, for example, data “ 1 ” is fed into a data input terminal of the write buffer  310  that drives the bit line BL connected to the memory cell  110  of the write target. In such cases, the write buffer  310  drives the bit line BL in a low-voltage state. Thereby, the selection transistor  112  of the memory cell  110  that becomes write target is turned on to lower the voltage at the connection point with the anti-fuse element  111 . Through the series of operations, a high voltage that becomes an electric stress is applied to any anti-fuse element  111 . Because the application of the high voltage to the anti-fuse element  111  is maintained for a while, the insulating film of the anti-fuse element  111  is broken to become the low-resistance state. 
         [0063]    Finally the write instruction signal WE is inactivated to complete the write operation. 
         [0064]    On the other hand, first the read instruction signal RE is fed in a read operation. When receiving the read instruction signal RE, the power switch  450  directly connects the supply voltage VDD and the program voltage VPP. Therefore, the voltage necessary for the data read is supplied to all the anti-fuse elements  111  in the cell array  100  without breaking the insulating film of the anti-fuse element  111 . At the same time, when receiving the read instruction signal RE, the row decoder  200  selects any one of word lines WL according to the states of the address signals A&lt; 0 &gt; and A&lt; 1 &gt;. Accordingly, the anti-fuse element  111  and the bit line BL are electrically connected by the selection transistor  112  connected to the selected word line WL. When the insulating film of the anti-fuse element  111  is broken, the supply voltage VDD is electrically connected to the selected bit line BL through the anti-fuse element  111 , thereby increasing the voltage at the bit line BL. On the other hand, when the insulating film of the anti-fuse element  111  is not broken, because the anti-fuse element  111  becomes an electrically insulating state, the voltage at the bit line BL is maintained at a low level. 
         [0065]    Finally the sense amplifier  320  amplifies a different between the voltage at the bit line BL and the voltage at the sense amplifier reference voltage VSAREF, and the amplified difference is supplied as the data output signals Q&lt; 0 &gt; to Q&lt; 3 &gt;. 
         [0066]    As described above, the anti-fuse element has the characteristic in which the breakdown is generated early as the program voltage or environmental temperature is increased. Accordingly, the breakdown time is lengthened at the low environmental temperature, and a risk of false write is increased at the high environmental temperature. 
         [0067]    On the other hand, in the embodiment, the program voltage VPP that is higher than usual is supplied to the anti-fuse element  111  at the low environmental temperature, so that the breakdown time can be shortened. The program voltage VPP that is lower than usual is supplied to the anti-fuse element  111  at the high environmental temperature, so that the risk of false write can be reduced. 
         [0068]    Therefore, the nonvolatile semiconductor memory, in which the write speed is kept constant irrespective of the environmental temperature and the risk of false write is lowered, can be provided.