Abstract:
Herein described is a control device of a device for the correction of the power factor in forced switching power supplies; said device for the correction of the power factor comprises a converter and said control device is coupled to the converter to obtain from an alternating input line voltage a regulated output voltage. The control device comprises generating means associated to a capacitor for generating a signal representative of the root-mean-square value of the alternating line voltage; the generating means are associated to means for discharging said capacitor. The control device comprises further means for discharging the capacitor suitable for discharging said capacitor when the signal representative of the root-mean-square value of the alternating line voltage goes below a given value.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation-in-part of International Patent Application No. PCT/IT2006/000606, filed Aug. 7, 2006, now pending, which application is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure refers to a control device for a power factor correction device in forced switching power supplies. 
     2. Description of the Related Art 
     The use of devices for active power factor correction (PFC) is generally known for forced switching power supplies used in the electronic appliances of common use such as computers, televisions, monitors, etc. and for the supply of fluorescent lamps, that is of forced switching pre-regulator stages whose task is to absorb from the line an almost sinusoidal current in phase with the line voltage. Therefore a forced switching power supply of the current type comprises a PFC and a direct current to direct current converter or DC-DC converter connected to the output of the PFC. 
     A forced switching power supply of the traditional type comprises a DC-DC converter and an input stage connected to the electricity distribution line made up of a full wave diode rectifier bridge and by a capacitor connected immediately downstream so as to produce a non-regulated direct current starting from the alternating sinusoidal line voltage. The capacitor&#39;s capacitance is large enough to ensure that at its terminals a relatively small ripple is present in relation to a direct level. The rectifier diodes of the bridge, therefore, will conduct only for a small portion of each half-cycle of the line voltage, given that the instantaneous value of this is lower than the voltage on the capacitor for the greatest part of the cycle. The consequence is that the current absorbed from the line will be formed by a series of narrow pulses whose width is 5-10 times the average resulting value. 
     This presents considerable consequences: the current absorbed by the line has much greater peak and root-mean-square (RMS) values in comparison to the case of absorption of sinusoidal current, the line voltage is distorted by effect of the nearly simultaneous impulsive absorption of all the utilities connected to the line, in the case of three-phase systems the current in the neutral conductor results much increased and there is a low utilization of the energetic potential of the electricity production system. In fact, the waveform of impulsive current is very rich with uneven harmonics which, even though not contributing to the power given to the load, contribute to increasing the effective current absorbed from the line and thus to increasing the dissipation of energy. 
     In quantitative terms all this can be expressed both in terms of power factor (PF), intended as ratio between the real power (that which the power supply gives to the load plus that dissipated internally in the form of heat) and the apparent power (the product of the effective line voltage by the effective current absorbed), and in terms of total harmonic distortion (THD), generally intended as percentage ratio between the energy associated with all the higher order harmonics and that associated with the fundamental harmonic. Typically, a power supply with capacitive filter has a PF between 0.4-0.6 and a THD exceeding 100%. 
     A PFC, placed between the rectifier bridge and the input of the DC-DC converter, permits the absorption from the line of a nearly sinusoidal current in phase with the voltage, making the PF near 1 and reducing the THD. 
     In  FIG. 1  a pre-regulator stage PFC is schematically shown comprising a boost converter  20  and a control device  1 , in this case the control device L6563 produced by STMicroelectronics S.p.A. The boost converter  20  comprises a full wave diode rectifier bridge  2  having in input an alternating line voltage Vin, a capacitor Cin (that serves as filter for the high frequency) having the terminals connected to the terminals of the diode bridge  2 , an inductance L connected to a terminal of the capacitor Cin, a power MOS transistor M having the drain terminal connected to a terminal of the inductance L downstream of the latter and having the source terminal coupled to ground by means of a resistance Rs suitable for enabling the reading of the current that flows in the transistor M, a diode D having the anode connected to the common terminal of the inductance L and of the transistor M and the cathode connected to a capacitor Co having the other terminal connected to ground. The boost converter  20  generates in output a direct current Vout on the capacitor Co, which is the input voltage of a user stage connected in cascade, for example a DC-DC converter. 
     The control device  1  maintains the output voltage Vout at a constant value by means of a feedback control action. The control device  1  comprises an operational error amplifier  3  suitable for comparing a part of the output voltage Vout, that is the voltage Vr given by Vr=R 2 *Vout/(R 2 +R 1 ) (where the resistances R 1  and R 2  are connected in series with each other and in parallel to the capacitor Co) with a reference voltage Vref, for example of the value of 2.5V, and suitable for generating an error signal Se proportional to their difference. The output voltage Vout presents a ripple at a frequency that is double that of the line and superimposed to the continuous value. If however the bandwidth of the error amplifier is considerably reduced (typically lower than 20 Hz) by means of the use of a suitable compensation line comprising at least one capacitor and assuming an almost stationary regular operation, that is with constant effective input voltage and output load, this ripple will be greatly mitigated and the error signal will become constant. 
     The error signal Se is sent to a multiplier  4  where it is multiplied by a signal Vi given by a part of the line voltage rectified by the diode bridge  2 . 
     At the output of the multiplier  4  a signal Imolt is present given by a rectified sinusoid whose width depends on the effective line voltage and on the error signal Se. Said signal Imolt represents the sinusoidal reference for the modulation PWM. Said signal is placed in input to the non-inverting terminal of a comparator  6  at whose inverting input the voltage present on the resistance Rs is proportional to the current I L . 
     If the signals in input to the comparator  6  are equal the same comparator  6  sends a signal to a control block  10  suitable for driving the transistor M and which, in this case, causes its turning off; therefore the output of the multiplier produces the peak current of the MOS transistor M which is enveloped by a rectified sinusoid. 
     After the transistor M has been turned off the inductor L discharges the energy stored in it on the load until it is completely emptied. At this point, the diode D opens and the drain node of the transistor M remains floating, therefore its voltage tends to the instantaneous input voltage through the resonance oscillations between the stray capacitance of the node and the inductance of the inductor L. Thus we see a rapid diminution of the voltage on the drain terminal of the transistor M that is sent in input to a device for detecting the passage through zero  13  through the auxiliary winding of the inductor L. The device  13  commands the turning on again of the transistor M, thus starting a new switching cycle. 
     The current absorbed from the line will be the low frequency component of the current of the inductor L, that is the average current per switching cycle (the switching frequency component is almost totally eliminated by the line filter placed at the input of the boost converter stage, always present for the electromagnetic compatibility regulations). For evident geometric reasons, the average current of the inductor is equal to half of the envelope of the peaks, and thus has a sinusoidal trend. 
     The multiplier  4  adjusts, by means of the error signal, the value of the sinusoidal reference for the PWM modulation upon variation of the load conditions and of the line voltage. In particular, considering the variations of the effective line voltage, if it, for example, doubles, the peak value also doubles; if the load does not change, and thus the power absorbed is constant, the input current, both the effective and the peak, once the transitory phase is over, halves in relation to the value that it had previously. The sinusoidal reference, nevertheless, is taken right from the rectified line voltage that is doubled. If the error signal did not intervene to correct the reference of the current (that is, if the regulation loop was open and thus the error signal was manually fixed), this would also become double (instead of half), thus giving place to a transfer of power four times greater. As the power requested by the load is constant, it would result in a considerable increase of the output voltage. The control loop, instead, reacting to this tendency, diminishes the value of the error signal so that the output of the multiplier becomes half of what it was previously. 
     Therefore the gain of the power block of a pre-regulator PFC depends in a quadratic manner on the line voltage and the error amplifier intervenes heavily to set the sinusoidal reference for the PWM modulation at the correct value independently from the line voltage. 
     Apart from the difficulties of planning the error amplifier, this strong dependence of its output voltage on the input voltage of the pre-regulator presents considerable consequences on the system. In first place, the quadratic variation of the gain of the power part implies a similar variation of the cutoff frequency of the open loop transfer function. If, then, the error amplifier is compensated to have 20 Hz band for the open loop transfer function at maximum line voltage, the band will be about 2 Hz at minimum line voltage, with the result of having an even slower dynamic response. In second place, by effect of the narrow band, the transient responses to sudden variations of the line voltage and of the output load will be very poor and there can be peaks of high voltage, limited only by the output dynamics of the multiplier, which is of the sinusoidal reference. These dynamics are set in such a manner that the maximum power requested by the load can pass to minimum line voltage, but this means that at maximum line voltage the pre-regulator is capable of carrying a power at least three times greater. 
     Finally, the fact that the output voltage of the error amplifier diminishes at the increase of the line voltage has a negative impact of the input current on the THD. In fact it can be demonstrated that the distortion of third harmonic introduced by the residual ripple superimposed at the continuous value present at the output of the error amplifier (whose gain at 100 Hz, for as much as it is low, is null) is proportional to the ratio between the peak-peak width of said ripple and the continuous value. The peak-peak width of the ripple is constant upon the variation of the line voltage, while the continuous value diminishes, thus the distortion of third harmonic increases. 
     These problems are usually solved by introducing in the control loop a feedforward of the line voltage and an inverter-squarer block (1/V 2 ) like that included in the marked box of  FIG. 1 . In input to the multiplier  4  there is therefore a signal in output from an inverter-squarer block  41  at whose input is present a voltage signal Vff representative of the root-mean-square value of the line voltage obtained by means of a block  42 ; the signal in output from the block  41  is 1/Vff 2 . The function of this circuitry is that, in the first place, to generate a continuous level of voltage representative of the effective line voltage and, in second place, to use said level to adapt the output voltage of the multiplier to the variations of the input voltage without moving the output of the error amplifier. 
     This voltage representative of the effective line voltage is generated by means of a circuit detecting the peak of the voltage V 1  that comprises a diode and a capacitor Cff. 
     To eliminate the detection error caused by the direct fall of the diode use is made of a so-called “ideal diode”, provided by interposing an operational amplifier connected to a non-inverting buffer and including the diode in the feedback. The capacitor Cff is equipped with a discharging means, that is, the resistance in parallel Rff so that the voltage at its terminals can adapt itself to the diminishing of the effective input voltage. This discharge, however, should be imperceptible in the environment of each half line cycle, so that the voltage at its terminals is, as much as possible, close to continuous. With the above mentioned conditions and considering the capacitance and resistance values that can be obtained in integrated form, it is convenient for the Rff and Cff to be elements placed outside the integrated control circuit. 
     However in the case of sudden drop in the line voltage, the system in  FIG. 1  replies with an exponential trend having a time constant Rff*Cff which, for what was said, will be to the order of many hundreds of milliseconds. This leads to the feedforward system losing effectiveness for a time which is as long as the variation of the input voltage is large and is as long as the time constant Rff*Cff. In fact, even though the signal on the comparator  6  tends to increase, the signal Vff is still too high because of the slow discharging and the output of the multiplier cannot adapt itself to the new level of current in input requested. The result is that the error amplifier tends to go out of its range and its output to saturate high. This causes a deep undershoot in the output voltage that can carry the converter downstream, fed by the stage PFC, out of regulation. 
     BRIEF SUMMARY 
     One embodiment is a control device for power factor correction device in forced switching power supplies. 
     One embodiment is a control device of a device for the correction of the power factor in forced switching power supplies, said device for the correction of the power factor comprising a converter and said control device being coupled to the converter to obtain from an alternating input line voltage a regulated output voltage, said control device comprising generating means associated with a capacitor for generating a signal representative of the root-mean-square value of the alternating line voltage, said generating means being associated with means for discharging said capacitor, characterized in that it comprises further means for discharging said capacitor suitable for discharging said capacitor when said signal representative of the root-mean-square value of the alternating line voltage goes below a given value. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The characteristics and advantages of the present disclosure will appear evident from the following detailed description of an embodiment, illustrated as non-limiting example in the enclosed drawings, in which: 
         FIG. 1  shows schematically a pre-regulator stage PFC in accordance with the known art; 
         FIG. 2  shows a feedforward circuit of a control device of a pre-regulator PFC in accordance with a first embodiment; 
         FIG. 3  shows a feedforward circuit of a control device of a pre-regulator PFC in accordance with a second embodiment; 
         FIG. 4  shows a feedforward circuit of a control device of a pre-regulator PFC in accordance with a third embodiment; 
         FIG. 5  shows a feedforward circuit of a control device of a pre-regulator PFC in accordance with a fourth embodiment; 
         FIG. 6  shows the time diagrams of the voltage Vff in the control circuit of the known art and in the control circuit in accordance with the first embodiment; 
         FIG. 7  shows the time diagram of the voltage Vff in the control circuit in accordance with the second embodiment; 
         FIG. 8  shows the time diagram of the voltage Vff in the control circuit in accordance with the third embodiment; 
         FIG. 9  shows the time diagram of the voltage Vff in the control circuit in accordance with the fourth embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     With reference to  FIG. 2  a feedforward circuit  421  is shown of a control device of a pre-regulator PFC in accordance with a first embodiment of the invention. Considering the pre-regulator PFC of  FIG. 1 , the feedforward circuit  421  is placed in substitution of the block  42 . The feedforward circuit  421  comprises an operational amplifier B 1  connected as a buffer and having the non-inverting input terminal connected to the voltage V 1 , the inverting input terminal connected to the cathode of a diode D 2  having the anode connected with the output of the buffer B 1 . The feedforward circuit  421  comprises a capacitor C 1  in which the peak value of the voltage V 1  is memorized at less than a voltage offset due to a Schottky diode D 1 . The voltage Vffi on the capacitor C 1  is used as a threshold of a comparator COMP 1  that compares it with the voltage Vff. The offset on the voltage Vffi in comparison to the peak on the voltage V 1  is sized keeping in consideration the time constant Rff*Cff and of the ripple to be obtained on the voltage Vff; during the normal functioning of the control device, the voltage Vffi should not have such a value that would change status at the output of the comparator COMP 1 . When instead there is a sudden drop in the line voltage, the voltage Vff goes below the voltage Vffi causing the triggering of the comparator COMP 1 . The output of the comparator COMP 1  is coupled to the set input S of a set-reset latch SR 1 ; with the signal of the set input S high, the signal Q of output of the set-reset latch SR 1  is high and turns on a MOS transistor M 1  having the drain terminal coupled with a terminal of the capacity Cff and the source terminal coupled with the other terminal of the capacitance Cff. The transistor M 1  permits the rapid discharging of the capacitance Cff. The discharge remains until the voltage Vff hooks up to the line voltage; in that instant the set-reset latch is reset and the MOS transistor M 1  is turned off. This is carried out by a comparator COMP 3  having the inverting and non-inverting inputs connected to the terminals of the diode D 2 ; the comparator COMP 3  switches when current flows through the diode D 2 , that is during the charging of the capacitance Cff. 
     Preferably, should values of voltage Vff that are too low represent a problem for the input of the multiplier  4 , the output of the comparator Comp 1  is masked sending it in input to an AND gate AND 1  having in input the output of a further comparator COMP 2  having the non-inverting terminal connected to the voltage V 1  and the inverting terminal connected to a reference voltage OS 3  that remains low for a certain interval of time around the low of the signal Vi. 
     The circuit  421  also comprises a second MOS transistor M 2  having the drain and source terminals connected to the terminals of the capacitance C 1  and controlled by the signal Q in output from the latch SR 1 . The transistor M 2  permits the discharge of the capacitor C 1  to zero the voltage Vffi in relation to the new level of the line voltage. A buffer B 2  is also provided placed between the output Q of the latch SR 1  and the gate terminal of the transistor M 1 . 
     In  FIG. 6  the time diagrams are shown of the voltage Vi and of the voltage Vff (in continuous line) for the circuit of the known art and the voltage Vff for the circuit of  FIG. 2  (dotted line). 
     With reference to  FIG. 3  a feedforward circuit  422  of a control device of a pre-regulator PFC is shown in accordance with a second embodiment. The circuit  422  comprises a differential couple of transistors M 11 -M 12  having in input the voltages Vi and Vff and a current mirror of transistors M 13 -M 14  connected at the drain terminals of the transistors of the differential couple M 11 -M 12 ; a Darlington transistor T 1  is also present and the union of the circuit of transistors M 1 -M 14  and of the transistor T 1  constitutes the overall of the buffer B 1  and of the diode D 2  of  FIG. 2 . A MOS transistor M 15  has the gate terminal connected to the drain terminal of the transistors M 11 , M 13 , the source terminal connected to ground GND and the drain terminal coupled to the supply voltage Vcc by means of a resistance, connected to the input terminal of the transistor T 1  and connected to the input of a buffer B 22  connected to the gate terminal of a transistor M 55 . A resistive divider R 11 -R 12  takes a signal representative of the voltage Vff that is sent to the inverting terminal of a comparator COMP 11 . On the non-inverting terminal of the comparator COMP 11  a capacitance C 11  is placed suitably sized and connected to an end of the transistor M 55  that puts it in communication with the divider R 11 -R 12  and to ground GND. The transistor M 55  is driven by a signal determined from the comparison between the voltage Vff and the signal Vi and is turned on every time there is an increase in load of the capacitance Cff through the transistor T 1 . If the peak voltage of the signal Vi diminishes, the transistor T 1  does not turn on, the voltage Vff is not increased and the transistor M 55  is not turned on. The voltage Vff will then tend to diminish by effect of the discharge of the capacitance Cff through the parallel of the resistances R 11 -R 12  and Rff. If the comparator COMP 11  is sized so that it has an offset exceeding the ripple present on the voltage Vff in normal conditions, the comparator switches only in the case of sudden drops in line voltage. In these cases the switching of the comparator turns on a MOS transistor M 16  connected to the capacitance Cff to discharge it and thus permitting a more rapid convergence of the voltage Vff at its new regular working value. 
     In  FIG. 7  are shown the time diagrams of the voltage V 1  and of the voltage Vff for the circuit of  FIG. 3 . 
     With reference to  FIG. 4  a feedforward circuit  423  of a control device of a pre-regulator PFC is shown in accordance with a third embodiment. The circuit  423  comprises, like the circuit of  FIG. 2 , an operational amplifier B 1  connected as a buffer and having the non-inverting input terminal connected to the voltage V 1 , the inverting input terminal connected to the cathode of a diode D 2  having the anode connected with the output of the buffer B 1 . The circuit  423  also comprises another operational amplifier connected to buffer B 3  having the non-inverting input terminal connected to the voltage V 1 , the inverting input terminal connected to the cathode of a diode D 3  having the anode connected with the output of the buffer B 3 ; a capacitor Cint is placed between the cathode of the diode D 3  and ground GND. Said circuit part acts as a peak detector and samples the peak value of the voltage V 1  each half cycle. The moment the ideal diode composed of the buffer B 3  and the diode D 3  opens because the peak has been exceeded, which is detected by the comparator COMP 3  having the inverting and non-inverting input terminals at the ends of the diode D 3 , an output signal is produced which is the set input S of a flip-flop FF 2 . The latter is set and in turn activates a monostable device MS 1  that generates a pulse Tm of preset length, for example 20 μs; the monostable device MS 1 , through the AND gate AND 11 , enables for this period of time Tm the comparison between the voltage Vff and the value sampled on Cint. Said comparison is carried out by the comparator COMP 22  if the difference Vff−Vint, where Vint is the voltage on Cint, exceeds a certain threshold (in the example, 25 mV), meaning that there has been a consistent diminishing of the line voltage, the flip-flop FF 1  is set by means of the output of the AND gate AND 11  which is the signal set s of the flip-flop FF 1  and the MOS transistor M 50 , having the drain and source terminals placed at the ends of the capacitance Cff, is turned on rapidly discharging the capacitance Cff until its voltage reaches the instantaneous value of the voltage V 1 ; this is signaled by the triggering of the comparator COMP 21  having the non-inverting and inverting input terminals placed at the ends of the diode D 2  and supplying an output signal that coincides with the input signal reset R of the flip-flop FF 1 . If not, FF 1  is not set and the transistor M 1  remains turned off. 
     Independently of the fact that the transistor M 1  has been turned on or not, the capacitance Cint is discharged so that in the successive half cycle the capacitance Cint correctly samples the voltage V 1 . This is accomplished, after a certain delay Td from the activation of the flip-flop FF 1 , by a transistor M 51 , having the drain and source terminals placed at the ends of the capacity Cint, that is turned on to then be turned off as soon as FF 2  is reset, that is when the voltage on Cint has gone below a certain level, definitely lower than the minimum value foreseen for the peak of the voltage V 1 . 
     In  FIG. 8  the time diagrams of the voltage V 1  and of the voltage Vff for the circuit  423  are shown in accordance with the third embodiment. From the graph it can be seen that in the case of the circuit of  FIG. 4 , the inconvenience of the circuits of the first and second embodiments caused by the delay between the moment in which there is the variation of the line voltage and the moment in which the system reacts adapting the value of the voltage Vff to the new condition, is limited to half a line cycle. This delay is caused by the decay time of the voltage Vff by effect of the resistance Rff, as well as of any internal resistances R 1 -R 12 . Wanting to contain this speed of decay to minimize the distortion brought about by the consequent ripple, the delay in intervention could also be relatively long. 
     Following very big transients the value of the voltage Vff can considerably go down below that which will be the new value. To avoid this with reference to  FIG. 5 , a feedforward circuit  424  of a control device of a pre-regulator PFC is provided in accordance with a fourth embodiment. 
     The circuit  424  differs from the circuit  423  of  FIG. 4  because the comparator COMP 21  that resets the flip-flop FF 1  compares the voltage Vff with the peak voltage sampled by the capacitor Cint, so as to turn off the transistor M 50  as soon as the voltage Vff becomes lower than the voltage Vint and because the transistor M 51  is turned on and, thus the capacitor Cint is discharged when, after having charged Cint to the peak value, the transistor M 50  has completed the discharging of the capacitance Cff. The transistor M 51  would be turned on immediately after the capacitor Cint has been charged to the value of peak if the transistor M 50  is not completely turned on (because there has not been a diminishing of the input voltage). The results of the simulation of said circuit are given in the time diagrams of the voltages Vi and Vff of  FIG. 9 . 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.