Abstract:
So as to compare an amplitude of a differential input signal to a threshold, a signal detection circuit includes first and second matched input signal level-shifters, a comparator threshold generation circuit, and a two-stage comparator. The differential input signal is comprised of a true input signal and a complement input signal, and the first input signal level-shifter is coupled to the true input signal, and the second input level-shifter is coupled to the complement input signal. The comparator threshold generation circuit is matched to the input signal level-shifters and outputs first and second compare voltages. The first stage of the two-stage comparator outputs a low signal if the more positive of the level-shifted input signals is greater than the more positive of the compare voltages. The second stage of the two-stage comparator amplifies the output of the first stage of the two-stage comparator, includes positive feedback to inhibit comparator self-oscillation, and has a sufficiently low bandwidth so as not to pass to its output a momentary pulse at its input during a transition in the differential input signal.

Description:
RELATED APPLICATIONS  
       [0001]     This application claims the benefit of priority pursuant to 35 USC §11 9(e) from U.S. provisional patent application Ser. No. 60/445,751, filed Feb. 7, 2003, and entirely incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     This invention relates to semiconductor integrated circuits and, more particularly, to a signal detection circuit. The function of the signal detection circuit is to compare an amplitude of a differential input signal to a comparator threshold voltage and to produce an output signal which is either high or low depending on whether the signal&#39;s amplitude is less than or greater than the comparator threshold voltage. This invention is similar to a method of detecting an amplitude of a signal which uses a current-source-biased comparator, but replaces the current source with a short to a power supply terminal and adds input signal level-shifters, providing for a much-improved differential input signal common-mode range.  
         [0003]      FIG. 1  is a schematic diagram illustrating a signal detection circuit of the prior art. A differential input signal comprises input signals INP and INM, with INP coupled to the gate terminal of M 8 , and INM coupled to the gate terminal of M 9 . A compare voltage THRESH, coupled to a gate terminal of M 4 , is set to a voltage equal to an average of INP and INM plus the comparator threshold voltage. The drain terminals of M 8  and M 9  are coupled together and to output terminal OUT 1 , and the source terminals of M 4 , M 8 , and M 9  are coupled together and to current source I 1 . A current mirror comprising M 6  and M 7  has an input coupled to the drain of M 4  and an output coupled to OUT 1 . N-type transistors M 4 , M 8 , and M 9  are of equal size, and p-type transistors M 6  and M 7  are of equal size. When the amplitude of the differential input signal exceeds the comparator threshold voltage, input signal INP or INM is more positive than THRESH, and output terminal OUT 1  will then be substantially low, indicating detection of the differential input signal. When the amplitude of the differential input signal is less than the comparator threshold voltage, input signal INP or INM is always more negative than THRESH, and output terminal OUT 1  will then be substantially high. For most practical values of the compare voltage THRESH, during a transition of the differential input signal from one state to another (for example, from a “one” state to a “zero” state), OUT 1  may tend to momentarily pulse from a low to a high voltage and then return to a low voltage when the transition is complete. In one embodiment, this pulse is inhibited with a capacitor coupled to OUT 1 .  
       SUMMARY OF THE INVENTION  
       [0004]     To compare the amplitude of a differential input signal to a comparator threshold voltage, a signal detection circuit includes first and second matched input signal level-shifters, a compare voltage generation circuit, and a two-stage comparator. The differential input signal is comprised of a true input signal and a complement input signal, and the first input signal level-shifter is coupled to the true input signal, and the second input level-shifter is coupled to the complement input signal. The compare voltage generation circuit outputs a first compare voltage set to an average voltage of the output signals of the level-shifters plus the comparator threshold voltage, and a second compare voltage set to the average voltage of the output signals of the level-shifters minus the comparator threshold voltage. The first stage of the two-stage comparator outputs a low signal if the more positive of the level-shifted input signals is greater than the more positive of the compare voltages. The second stage of the two-stage comparator amplifies the output of the first stage of the two-stage comparator, includes positive feedback to inhibit comparator self-oscillation, and has a sufficiently low bandwidth so as not to pass to its output a momentary pulse at its input due to a transition in the differential input signal.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]      FIG. 1  is a schematic diagram of a prior-art signal detection circuit.  
         [0006]      FIG. 2  is a schematic diagram of components of a signal detection circuit in accordance with one embodiment of the present invention.  
         [0007]      FIG. 3  is a waveform diagram illustrating operation of the signal detection circuit of  FIG. 2 .  
         [0008]      FIG. 4  is a schematic diagram of the signal detection circuit with additional components, in accordance with the present invention.  
         [0009]      FIG. 5  is a schematic diagram of a differential to single-ended amplifier, in accordance with the present invention.  
         [0010]      FIG. 6  is a schematic diagram of a logic inverter, in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0011]     The signal detection circuits of  FIG. 2  illustrate components of one embodiment of the invention.  FIG. 2   a  shows input signal level-shifters  5  and a matched circuit  6  which sets the voltage of a common signal to that of the average voltage of the input signal level-shifter output signals. Also included are level-shifting voltage sources  7  referenced to the common signal which assist in setting the compare voltages for the two-stage comparator illustrated in  FIG. 2   b.    
         [0012]     The differential input signal is comprised of input signals INP and INM, which are coupled to the matched input signal level-shifters. Input signal INP is coupled to level-shifted signal INPX through series components R 1  and C 1 . A level-shift current from transistor M 1  induces a voltage drop across R 1 , and capacitor C 1  provides a low-impedance signal path to couple INP to INPX with minimal high-frequency signal loss. Similarly, input signal INM is coupled to level-shifted signal INMX through series components R 2  and C 2 , and a level-shift current from transistor M 2  sets a voltage drop across R 2 , and capacitor C 2  provides a low-impedance signal path to couple INM to INMX with minimal high-frequency signal loss. These two level-shifters are matched: R 1  and R 2  are the same size and resistance value, C 1  and C 2  are the same size and capacitance value, and M 1  and M 2  are the same size and have matched K-factors (voltage-to-current conversion gain).  
         [0013]     The matched circuit sets the voltage of the common signal COM to that of the average voltage of INPX and INMX, and comprises resistors R 3  and R 4 , and transistor M 3 . In a preferred embodiment, resistors R 1 , R 2 , R 3 , and R 4  are the same size and value, the gate width of M 3  is twice the gate width of M 1  and M 2  (or, alternatively, M 3  comprises two transistors matched to M 1  and M 2 ), and the gate lengths of M 1 , M 2 , and M 3  are equal. Two final components of the circuit of  FIG. 2   a  are level-shifting voltage sources V 1  and V 2 . In a preferred embodiment, V 1  and V 2  are each set to a voltage equal to the comparator threshold voltage.  
         [0014]      FIG. 2   b  depicts the two-stage comparator, comprising a first comparator  8  and a second comparator  9 . A first dual-input voltage-to-current converter comprised of transistors M 4  and M 5  has an output and its inputs are coupled to compare voltages THRESHP and THRESHM. A second dual-input voltage-to-current converter comprised of transistors M 8  and M 9  has an output coupled to OUT 1 , and its inputs are coupled to level-shifted signals INPX and INMX. A current mirror comprised of transistors M 6  and M 7  has an input coupled to the output of the first dual-input voltage-to-current converter and an output coupled to OUT 1  and to an input of the second comparator. Coupled to a second input of the second comparator is a threshold voltage THRESH.  
         [0015]      FIG. 3  illustrates the functionality of the circuits of  FIG. 2 . Waveforms labeled INP, INM, THRESHP, THRESHM, INPX, INMX, COM, THRESH, OUT 1 , and OUT 2  depict signals at nodes of  FIG. 2  having the same designations. In this illustration, the amplitude of differential signal INP-INM diminishes over time until below a threshold, at which time OUT 1  and OUT 2  each transition from a low level to a high level. The first comparator takes advantage of a square-law dependence of voltage-to-current conversion gain of transistors M 4 , M 5 , M 8 , and M 9 .  
         [0016]     Consider currents I 1  and  12  of  FIG. 2  flowing through transistors M 4  and M 5 , and transistors M 8  and M 9 , respectively, given by the equations 
 
 I   1 = K   M4 ( V   GS,M4   −V   T,M4 ) 2   +K   M5 ( V   GS,M5   −V   T,M5 ) 2    (1) 
 
 I   2 = K   M8 ( V   GS,M8   −V   T,M8 ) 2   +K   M9 ( V   GS,M9   −V   T,M9 ) 2    (2) 
 
         [0017]     Each of the constants K Mn  and V T,Mn  (n=4,5,8,9) represent a transistor&#39;s K-factor (voltage-to-current conversion gain) and threshold voltage, respectively. In a preferred embodiment, and for the purposes of simplifying the following analysis, the gate length of all transistors of  FIG. 2  are equal, the gate widths of M 1  and M 2  are equal, the gate width of M 3  is twice that of M 1  and M 2  (or, alternatively, M 3  comprises first and second transistors matched to M 1  and M 2 , respectively), the gate widths of M 4 , M 5 , M 8 , and M 9  are equal, and the gate widths of M 6  and M 7  are equal. Additionally, resistors R 1 , R 2 , R 3 , and R 4  are equal in resistance value. It is further assumed that all the transistor K-factors are equal and are equal to K and that all the transistor threshold voltages are equal and are equal to V T . With a current gain of the current mirror substantially equal to one because M 6  and M 7  are of equal size, the voltage of OUT 1  will be substantially near VDD when I 1 &gt;I 2  and near VSS when I 1 &lt;I 2 . With voltage sources V 1  and V 2  set to comparator threshold voltage V 1 , the following relations are evident from  FIG. 2 : 
 
 V   GS,M4   =V   THRESHP   −V   VSS    (3) 
 
 V   GS,M5   =V   THRESHM   −V   VSS    (4) 
 
 V   GS,M8   =V   INPX   −V   VSS    (5) 
 
 V   GS,M9   =V   INMX   −V   VSS    (6) 
 
 V   THRESHP   =V   COM   +V   1    (7) 
 
 V   THRESHM   =V   COM   −V   1    (8) 
 
         [0018]     Defining V PEAK  as a peak voltage of signals INP and INM above average voltage (V INP +V INM )/2, and with a voltage drop across each of level-shifting resistors R 1 -R 4  being substantially equal, the following relations are true: 
 
 V   INPX   =V   COM   +V   PEAK    (9) 
 
 V   INMX   =V   COM   −V   PEAK    (10) 
 
         [0019]     Combining equations (1) through (10) gives the following result: 
 
 I   2 − I   1 =2 K ( V   PEAK   2   −V   1   2 )   (11) 
 
         [0020]     The signal detection circuit is operating at a threshold when I 1 =I 2 . When I 1 &gt;I 2 , a net positive current will charge OUT 1  to a voltage substantially near VDD, and when I 1 &lt;I 2 , a net negative current will discharge OUT 1  to a voltage substantially near VSS. A condition for which the first comparator is at its threshold is given by that voltage of V PEAK  for which I 2 −I 1 =0, and is obtained by inspection as V PEAK =V 1 , thereby confirming the proper definition of V 1  as the comparator threshold voltage.  
         [0021]     Finally, it is instructive to differentiate equation (11): 
 
∂( I   2 − I   1 )/∂ V   PEAK =4 KV   1    (12) 
 
         [0022]     The quantity 4KV 1  is a measure of the first comparator&#39;s voltage-to-current gain, and this gain is a non-zero quantity if V 1 #0. In all practical applications of this signal detection circuit, this is indeed the case.  
         [0023]      FIG. 4  illustrates a detailed schematic of the complete signal detection circuit.  
         [0024]      FIG. 4   a  illustrates the circuit of  FIG. 2   a,  but with voltage sources V 1  and V 2  removed.  
         [0025]      FIG. 4   b  illustrates the circuit of  FIG. 2   b,  but includes transistors M 18  and M 19  used to set threshold voltage THRESH, and also includes transistors M 16  and M 17  and inverter U 3  so as to provide positive feedback to the operation of the second comparator. This last addition inhibits comparator self-oscillation when operating near threshold for an extended period of time.  
         [0026]      FIG. 4   c  illustrates a circuit which implements the functionality of voltage sources V 1  and V 2  of  FIG. 2   a,  and comprises bias generator  15 , switched current-source  16 , and current-to-voltage converter  17 . Bias generator  15  consists of a resistor string made from R 8 -R 11 , used to generate reference voltage REF, and a feedback circuit consisting of differential-to-single-ended amplifier U 4 , transistor M 10 , and reference resistor R 7 . Negative feedback forces feedback reference node voltage V FBREF  to be substantially equal to V REF . It then follows that current through M 10  and R 7  is given by 
 I M10   =I   R7 =(V VDD   −V   REF )/ R   R7    (13)  
         [0027]     Switched current-source  16  is a binary-weighted switched current source and is comprised of dual-gate transistors M 20 , M 21 , M 22 , and M 23 . In a preferred embodiment, these dual-gate transistors each consist of two series transistors having a gate width and an equal gate length. The gate width of the transistors of dual-gate transistor M 22  is twice that of the transistors of dual-gate transistor M 23 ; the gate width of the transistors of dual-gate transistor M 21  is twice that of the transistors of dual-gate transistor M 22 ; and the gate width of the transistors of dual-gate transistor M 20  is twice that of the transistors of dual-gate transistor M 21 . Additionally, the gate width of transistor M 10  is twice the gate width of the transistors of dual-gate transistor M 20 . In combination, bias generator  15  and switched current-source  16  form a binary-weighted, programmable current source controlled by logic terminals IN 0 , IN 1 , IN 2 , and IN 3  and having an output current given by 
 
 I   X =( IN /16)* I   M10    (14) 
 
 where IN is a decimal number between 0 and 15 and is set by logic levels IN[3:0]. 
 
         [0028]     Current-to-voltage converter  17  comprises three current mirrors each with a gain substantially equal to 1, and resistors R 5  and R 6 . A first current mirror comprising M 11  and M 12  generates output current I 12  equal to input current I X ; a second current mirror comprising M 11  and M 13  generates output current I 13  equal to input current I X ; and a third current mirror comprising M 14  and M 15  generates output current I 15  equal to input current I 12 . It then follows that compare voltages V THRESHP  and V THRESHM  are given by 
 
 V   THRESHP   =V   COM   +I   X   *R   R5    (15) 
 
 V   THRESHM   =V   COM   −I   X   *R   R6    (16) 
 
         [0029]     In a preferred embodiment, all resistors of  FIG. 4   c  are of equal value, and equations (13)-(16) can then be combined and simplified to obtain 
 
 V   THRESHP   =V   COM   +V   1    (17) 
 
 V   THRESHM   =V   COM   −V   1    (18) 
 
 where V 1 =(V VDD /4)*( IN /16)   (19) 
 
         [0030]     This final equation (19) illustrates the influence of logic terminals IN[3:0] on the comparator threshold voltage, V 1 .  
         [0031]      FIG. 5  illustrates the differential to single-ended amplifier, instantiated as U 1  in  FIG. 2   b,  as U 2  in  FIG. 4   b,  and as U 4  in  FIG. 4   c,  and is comprised of transistors M 1 -M 9 . Transistor M 1  is a resistive current source which biases differential transistor pair M 2  and M 3 . The drain of M 2  is coupled to output OUT through two series current mirrors comprising p-type transistors M 4  and M 6 , and n-type transistors M 7  and M 8 . The drain of M 3  is coupled to OUT through a single current mirror comprising p-type transistors M 5  and M 9 . In a preferred embodiment, the gate lengths of all transistors but M 1  are the same, the gate width of n-type transistors M 2 , M 3 , M 7 , and M 8  are the same, and the gate width of p-type transistors M 4 , M 5 , M 6 , and M 9  are the same. Additionally, the gate width of n-type transistor M 1  is equal to the gate width of the other n-type transistors, and the gate length of M 1  is at least 5 times longer than the gate length of the other n-type transistors. In U 2 , so as to prevent false switching at its output when the differential input signals transition from low to high or from high to low, the gate length of M 1  is increased to 10 times (or more) that of the gate length of the other n-type transistors, for the purpose of decreasing the bandwidth and switching speed of U 2 .  
         [0032]      FIG. 6  illustrates logic inverter U 3  of  FIG. 4   b,  used to facilitate positive feedback to inhibit comparator self-oscillation. The logic inverter comprises n-type transistor M 20  and p-type transistor M 21 . The gate of each transistor is coupled to input IN, and the drain of each transistor is coupled to output OUT.  
         [0033]     The signal detection circuit can be implemented with discreet components, with semiconductor devices embedded in an integrated circuit such as an application specific integrated circuit (ASIC), or with a combination of both. Individual signals or devices can be active high or low, and corresponding circuitry can be converted or complemented to suit any particular convention. The term “coupled” used in the claims includes various types of connections or couplings and includes a direct connection or a connection through one or more intermediate components. Except to the extent specified in the following claims, circuit configurations and device sizes shown herein are provided as examples only. Those skilled in the art will recognize that desired and proper circuit operation can be achieved with other circuit configurations, device sizes, and/or combinations of device sizes.