Abstract:
A composite electronic structure comprising at least one feature layer and at least one adjacent via layer, said layers extending in an X-Y plane and having height z, wherein the structure comprises at least one capacitor coupled in series or parallel to at least one inductor to provide at least one filter; 
     the at least one capacitor being sandwiched between the at least one feature layer and at least one via in said at least adjacent via layer, such that the at least one via stands on the at least one capacitor, and the at least one of the first feature layer and the adjacent via layer includes at least one inductor extending in the XY plane.

Description:
BACKGROUND 
       [0001]    1. Field of the Disclosure 
         [0002]    The present invention is directed to passive components such as filters, and to multilayer interconnect structures with embedded filters and the like. 
         [0003]    2. Description of the Related Art 
         [0004]    Driven by an ever greater demand for miniaturization of ever more complex electronic components, consumer electronics such as computing and telecommunication devices are becoming more integrated. This has created a need for support structures such as IC substrates and IC interposers that have a high density of multiple conductive layers and vias that are electrically insulated from each other by a dielectric material. 
         [0005]    The general requirement for such support structures is reliability and appropriate electrical performance, thinness, stiffness, planarity, good heat dissipation and a competitive unit price. 
         [0006]    Of the various approaches for achieving these requirements, one widely implemented manufacturing technique that creates interconnecting vias between layers uses lasers to drill holes through the subsequently laid down dielectric substrate through to the latest metal layer for subsequent filling with a metal, usually copper, that is deposited therein by a plating technique. This approach to creating vias is sometimes referred to as ‘drill &amp; fill’, and the vias created thereby may be referred to as ‘drilled &amp; filled vias’. 
         [0007]    There are a number of disadvantages with the drilled &amp; filled via approach. Since each via is required to be separately drilled, the throughput rate is limited, and the costs of fabricating sophisticated, multi-via IC substrates and interposers becomes prohibitive. In large arrays it is difficult to produce a high density of high quality vias having different sizes and shapes in close proximity to each other by the drill &amp; fill methodology. Furthermore, laser drilled vias have rough sides walls and taper inwards through the thickness of the dielectric material. This tapering reduces the effective diameter of the via. It may also adversely affect the electrical contact to the previous conductive metal layer especially at ultra small via diameters, thereby causing reliability issues. Additionally, the side walls are particularly rough where the dielectric being drilled is a composite material comprising glass or ceramic fibers in a polymer matrix, and this roughness may create additional stray inductances. 
         [0008]    The filling process of the drilled via holes is usually achieved by copper electroplating. The electroplating deposition technique may result in dimpling, where a small crater appears at the top of the via. Alternatively, overfill may result, where a via channel is filled with more copper than it can hold, and a domed upper surface that protrudes over the surrounding material is created. Both dimpling and overfill tend to create difficulties when subsequently stacking vias one on top of the other, as required when fabricating high-density substrates and interposers. Furthermore, it will be appreciated that large via channels are difficult to fill uniformly, especially when they are in proximity to smaller vias within the same interconnecting layer of the interposer or IC substrate design. 
         [0009]    While the range of acceptable sizes and reliability is improving over time, the disadvantages described hereinabove are intrinsic to the drill &amp; fill technology and are expected to limit the range of possible via sizes. It will further be noted that laser drilling is best for creating round via channels. Although slot shaped via channels may theoretically be fabricated by laser milling, in practice, the range of geometries that may be fabricated is somewhat limited and vias in a given support structure are typically cylindrical and substantially identical. 
         [0010]    Fabrication of vias by drill &amp; fill is expensive and it is difficult to evenly and consistently fill the via channels created thereby with copper using the relatively, cost-effective electroplating process. 
         [0011]    Laser drilled vias in composite dielectric materials are practically limited to 60×10 −6  m (60 microns) diameter, and even so suffer from significant tapering shape as well as rough side walls due to the nature of the composite material drilled, in consequence of the ablation process involved. 
         [0012]    In addition to the other limitations of laser drilling as described hereinabove, there is a further limitation of the drill &amp; fill technology in that it is difficult to create different diameter vias in the same layer, since when drill different sized via channels are drilled and then filled with metal to fabricate different sized vias, the via channels fill up at different rates. Consequently, the typical problems of dimpling or overfill that characterize drill &amp; fill technology are exasperated, since it is impossible to simultaneously optimize deposition techniques for different sized vias. 
         [0013]    An alternative solution that overcomes many of the disadvantages of the drill &amp; fill approach, is to fabricate vias by depositing copper or other metal into a pattern created in a photo-resist, using a technology otherwise known as ‘pattern plating’. 
         [0014]    In pattern plating, a seed layer is first deposited. Then a layer of photo-resist is deposited thereover and subsequently exposed to create a pattern, and selectively removed to make trenches that expose the seed layer. Via posts are created by depositing Copper into the photo-resist trenches. The remaining photo-resist is then removed, the seed layer is etched away, and a dielectric material, that is typically a polymer impregnated glass fiber mat, is laminated thereover and therearound to encase the vias posts. Various techniques and processes can then be used to planarize the dielectric material, removing part of it to expose the tops of the via posts to allow conductive connection to ground thereby, for building up the next metal layer thereupon. Subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure. 
         [0015]    In an alternative but closely linked technology, known hereinafter as ‘panel plating’, a continuous layer of metal or alloy is deposited onto a substrate. A layer of photo-resist is deposited on top of the substrate, and a pattern is developed therein. The pattern of developed photo-resist is stripped away, selectively exposing the metal thereunder, which may then be etched away. The undeveloped photo-resist protects the underlying metal from being etched away, and leaves a pattern of upstanding features and vias. 
         [0016]    After stripping away the undeveloped photo-resist, a dielectric material, such as a polymer impregnated glass fiber mat, may be laminated around and over the upstanding copper features and/or via posts. After planarizing, subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure. 
         [0017]    The via layers created by pattern plating or panel plating methodologies described above are typically known as ‘via posts’ and feature layers from copper. 
         [0018]    It will be appreciated that the general thrust of the microelectronic evolution is directed towards fabricating ever smaller, thinner, lighter and more powerful products having high reliability. The use of thick cored interconnects prevents ultra-thin products being attainable. To create ever higher densities of structures in the interconnect IC substrate or ‘interposer’, ever more layers of ever smaller connections are required. Indeed, sometimes it is desirable to stack components on top of each other. 
         [0019]    If plated, laminated structures are deposited on a copper or other appropriate sacrificial substrate, the substrate may be etched away leaving free standing, coreless laminar structures. Further layers may be deposited on the side previously adhered to the sacrificial substrate, thereby enabling a two sided build up, which minimizes warping and aids the attaining of planarity. 
         [0020]    One flexible technology for fabricating high density interconnects is to build up pattern or panel plated multilayer structures consisting of metal vias or features in a dielectric matrix. The metal may be copper and the dielectric may be a fiber reinforced polymer. Typically a polymer with a high glass transition temperature (T g ) is used, such as polyimide, for example. These interconnects may be cored or coreless, and may include cavities for stacking components. They may have odd or even numbers of layers. Enabling technology is described in previous patents issued to Amitec-Advanced Multilayer Interconnect Technologies Ltd. 
         [0021]    For example, U.S. Pat. No. 7,682,972 to Hurwitz et al. titled “Advanced multilayer coreless support structures and method for their fabrication” describes a method of fabricating a free standing membrane including a via array in a dielectric, for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing the laminated array, followed by terminating the vias. This publication is incorporated herein by reference in its entirety. 
         [0022]    U.S. Pat. No. 7,669,320 to Hurwitz et al. titled “Coreless cavity substrates for chip packaging and their fabrication” describes a method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper. This publication is incorporated herein by reference in its entirety. 
         [0023]    U.S. Pat. No. 7,635,641 to Hurwitz et al. titled “integrated circuit support structures and their fabrication” describes a method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (E) applying a protective coating of photo-resist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photo-resist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto. This publication is incorporated herein by reference in its entirety. 
         [0024]    RF (Radio Frequency) technologies, such as Wifi, Bluetooth and the like, are becoming widely implemented in various devices, including mobile phones and automobiles. 
         [0025]    In addition to Base Band processing and memory chips, RF devices in particular, require passive components such as capacitors, inductors and filters of various sorts. Such passive components may be surface mounted, but to enable ever greater miniaturization and cost savings, such devices may be embedded within the chip or substrates. 
         [0026]    One advantage of the via post fabrication process is that shaped vias may be generated instead of simple cylindrical ones. This provides great flexibility in shaping of capacitors and also enables fabrication of high inductance vias that function as conductors between different positions in the xy plan, and facilitates the formation of filters consisting of combination of capacitors and inductors. 
       BRIEF SUMMARY 
       [0027]    A first aspect of the invention is directed to providing a composite electronic structure comprising at least one feature layer and at least one adjacent via layer, said layers extending in an X-Y plane and having height z, wherein the composite electronic structure comprises at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a lower electrode and a dielectric layer and being incorporated at a base of a via layer sandwiched between the at least one feature layer and a via post, such that the at least one via stands on the at least one capacitor, and optionally forms an upper electrode, wherein the via layer is embedded in a polymer matrix, and wherein the at least one inductor is formed in at least one of the first feature layer and the adjacent via layer. 
         [0028]    Optionally, the at least one capacitor and the at least one inductor are coupled in series. 
         [0029]    Optionally, the at least one capacitor and the at least one inductor are coupled in parallel. 
         [0030]    The at least one inductor may be fabricated in the feature layer. 
         [0031]    The at least one inductor in the feature layer is typically spirally coiled. 
         [0032]    Typically, the inductance of the inductor in the feature layer is at least 0.1 nH. 
         [0033]    Typically, the inductance of the inductor in the feature layer is less than 50 nH. 
         [0034]    Optionally, a further inductor is fabricated in a via layer. 
         [0035]    In some embodiments, the at least one inductor is fabricated in a via layer. 
         [0036]    In such cases, the inductance of the inductor is typically, at least 1 nH. 
         [0037]    In such cases, the inductance of the inductor is typically less than 10 nH 
         [0038]    In some structures, the at least one inductor and said at least one capacitor provide a filter, said filter being selected from the group consisting of basic LC low pass filters, LC high pass filters, LC series band pass filters, LC parallel band pass filters and Low Pass Parallel-Chebyshev filters. 
         [0039]    Optionally, the polymer matrix comprises a polymer selected from the group comprising polyimides, epoxys, BT (Bismaleimide/Triazine) and their blends. 
         [0040]    Optionally, the polymer matrix further comprises glass fibers. 
         [0041]    Optionally, the polymer matrix further comprises inorganic particulate fillers having mean particle size of between 0.5 microns and 30 microns and between 15% and 30% of particulate by weight. 
         [0042]    Typically, the capacitor comprises a ceramic dielectric. 
         [0043]    Optionally, the dielectric of the capacitor comprises at least one of the group consisting of Ta2O5, TiO 2 , BaO 4 SrTi and Al 2 O 3 . 
         [0044]    Typically, the lower electrode comprises a noble metal. 
         [0045]    Optionally, the lower electrode comprises a metal selected from the group consisting of gold, platinum and tantalum. 
         [0046]    Optionally, the upper electrode comprises a metal selected from the group consisting of gold, platinum and tantalum. 
         [0047]    Alternatively, the upper electrode comprises the via post. 
         [0048]    In some embodiments, the capacitor has a cross sectional area defined by a cross sectional area of the via post, that is carefully controlled to tune capacitance of capacitor. 
         [0049]    Typically, the at least one capacitor has a capacitance of between 1.5 pF and 300 pF. 
         [0050]    Optionally, the at least one capacitor has a capacitance of between 5 and 15 pF. 
         [0051]    A second aspect is directed to providing a method of fabricating filters in an array, comprising fabricating capacitors by depositing a first electrode and a layer of ceramic and applying a via post over part of the layer of ceramic such that size of footprint of the via post on the layer of ceramic defines controls capacitance of the capacitor, and fabricating inductors by electroplating copper into a pattern of photoresist, stripping away the photoresist and laminating. 
         [0052]    Typically, the dielectric material comprises a ceramic material selected from the group consisting of Ta2O5, TiO 2 , BaO 4 SrTi and Al 2 O 3 . 
         [0053]    Typically, the layer of electrode is selected from the group consisting of gold, platinum and tantalum. 
         [0054]    Optionally, the method further comprises depositing an upper electrode selected from the group consisting of gold, platinum and tantalum, depositing accurately sized copper via posts over the upper electrode, and selectively removing excess upper electrode, dielectric and lower electrode to control size of the capacitor. 
         [0055]    Optionally, the excess upper electrode, the dielectric and the lower electrode are removed by plasma etching. 
         [0056]    In some embodiments, the capacitors are fabricated by a method comprising the steps of: (i) procuring a carrier; (ii) depositing a barrier layer; (iii) thinning barrier layer; (iv) depositing a thin layer of copper above the carrier layer; (v) depositing a first layer of electrode material; (vi) depositing a layer of dielectric material; (vii) depositing a second layer of electrode material; (viii) depositing an upper copper layer over the second electrode, (ix) applying photoresist over the upper copper layer and patterning; (x) etching away exposed copper of the upper copper layer; (xi) etching away exposed material of the second electrode layer, exposed dielectric material in the layer of dielectric material and exposed material in the first layer of electrode, and (xii) stripping away the photoresist. 
         [0057]    Optionally, step (vi) of depositing a layer of dielectric material comprises sputtering a layer of ceramic, and further comprises previously or subsequently depositing a layer of aluminium, and then oxidizing the aluminium to less dense aluminium-oxide, thereby growing aluminum-oxide into defects in the layer of ceramic and sealing the defects. 
         [0058]    Optionally, the carrier is selected from the group consisting of a sacrificial copper substrate and a copper carrier with a quick release thin film of copper appended thereto. 
         [0059]    In some embodiments, inductors are fabricated by depositing a copper seed layer over a dielectric polymer that is thinned to expose at least one copper via, thereby providing conductive connection; laying down a layer of photoresist; patterning the photoresist to create a shaped via that is elongated; depositing copper into the photoresist to create an inductor; stripping away the photoresist; etching away the seed layer, and laminating. 
         [0060]    Optionally, a titanium seed layer is deposited prior to the copper seed layer. 
         [0061]    Optionally, inductors are fabricated by depositing a copper seed layer over a dielectric polymer that is thinned to expose at least one copper via, thereby providing conductive connection; laying down a layer of photoresist; patterning the photoresist to create a spiral feature; depositing copper into the photoresist to create an inductor; stripping away the photoresist, and etching away the seed layer. 
         [0062]    Typically, he method further comprising laminating. 
         [0063]    In some embodiments, a titanium seed layer is deposited prior to the copper seed layer. 
         [0064]    In some embodiments, the array of filters is embedded in a polymer matrix; thinned to expose ends of vias; then terminations are applied by laying down photoresist on each side of the thinned polymer matrix; deposing copper pads into the pattern of photoresist; stripping away the photoresist; laying down soldermask between the copper pads, and applying a protective coating. 
         [0065]    The protective coating may be selected from ENEPIG and an organic varnish 
         [0066]    The term microns or μm refers to micrometers, or 10 −6 m. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0067]    For a better understanding of the invention and to show how it may be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings. 
           [0068]    With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention; the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice. In the accompanying drawings: 
           [0069]      FIG. 1  is a simplified section through a multilayer composite support structure of the prior art; 
           [0070]      FIG. 2  is a schematic cross-section through a substrate that includes a single layer capacitor and copper vias within a polymer based matrix; 
           [0071]      FIG. 3  is a schematic projection of an inductor within a feature layer and an adjacent via post in a via post layer standing on a capacitor that is coupled in series with the inductor; 
           [0072]      FIG. 4  is a schematic projection of an inductor via within a via layer coupled in series with a capacitor at a base of a via post; 
           [0073]      FIG. 5  is a schematic projection of a pair of inductors, one within a feature layer and one within a via layer, coupled in series to each other and to a capacitor at the base of a via post within the via layer of the via inductor; 
           [0074]      FIG. 6  is a schematic projection of an inductor in a feature layer, coupled in parallel with a capacitor, the capacitor and the inductor being coupled together by via posts and a trace in a second, upper feature layer or on the outside of the multilayer structure. 
           [0075]      FIG. 7  is a schematic projection of an inductor in a feature layer, coupled in series with an inductive via, and in parallel with a capacitor, the capacitor and the inductive via being coupled together by a trace in a second, upper feature layer or on the outside of the multilayer structure. 
           [0076]      FIG. 8  is a flow chart illustrating a process for fabricating a substrate with an embedded filter consisting of a capacitor and inductors; 
           [0077]      FIG. 8(   i ) to  FIG. 8(   xxxi ) are a series of schematic cross section illustrations illustrating a process for fabricating a substrate with an embedded filter consisting of a capacitor and inductor; 
           [0078]      FIG. 9  is a flow chart illustrating a process for terminating the filter of  FIG. 8 ; 
           [0079]      FIG. 9(   xxxii ) to  FIG. 9(   xxxix ) are a series of schematic cross section illustrations illustrating a process for termination a substrate with an embedded filter; 
           [0080]      FIG. 10   a  is a schematic three dimensional view of a basic LC low pass filter; 
           [0081]      FIG. 10   b  shows how the basic LC low pass filter of  FIG. 11   a  may be represented as an LC filter circuit; 
           [0082]      FIG. 10   c  is a schematic cross section of the basic LC low pass filter of  FIG. 10   a;    
           [0083]      FIG. 10   d  is a schematic cross section of the basic LC low pass filter of  FIG. 10   a  wherein the capacitor is sized to the via pillar thereover, which defines the effective capacitance of the capacitor; 
           [0084]      FIG. 10   e  is a schematic cross section of the basic LC low pass filter of  FIG. 10   a  wherein the top electrode is the via pillar thereover; 
           [0085]      FIG. 11   a  is a schematic three dimensional view of a basic LC high pass filter; 
           [0086]      FIG. 11   b  shows how the basic LC high pass filter of  FIG. 11   a  may be represented as an LC filter circuit component; 
           [0087]      FIG. 12   a  is a schematic three dimensional view of a basic LC band pass series filter; 
           [0088]      FIG. 12   b  shows how the basic LC band pass series filter of  FIG. 12   a  may be represented as an LC filter circuit component. 
           [0089]      FIG. 13   a  is a schematic three dimensional view of basic LC band pass parallel filter comprising a capacitor and inductors; 
           [0090]      FIG. 13   b  shows how the basic LC band pass parallel filter of  FIG. 13   a  may be represented as an LC filter circuit component; 
           [0091]      FIG. 14   a  is a schematic three dimensional view of a Low Pass Parallel-Chebyshev Filter, and 
           [0092]      FIG. 14   b  shows how the Low Pass Parallel-Chebyshev Filter may be represented as an LC filter. 
       
    
    
       [0093]    It will be appreciated that the Figures are schematic illustrations only, and are not to scale. Very thin layers may appear thick. The width of features may appear out of proportion to their length, etc. 
       DETAILED DESCRIPTION  
       [0094]    In the description hereinbelow, support structures consisting of metal vias in a dielectric matrix, particularly, copper via posts in a polymer matrix, such as polyimide, epoxy or BT (Bismaleimide/Triazine) or their blends, reinforced with glass fibers are considered. 
         [0095]    Structures described below include capacitors. Since parallel plate capacitors comprise a dielectric material sandwiched between electrodes, typically a material with a very high dielectric constant, the dielectric material used for encapsulation is referred to hereinbelow as an encapsulation dielectric to differentiate it from the dielectric of the capacitor. 
         [0096]    The figures are illustrative, and no attempt is made to indicate scale. Furthermore, small numbers of vias and individual capacitors and filters are shown, whereas an individual substrate may include several capacitors and filters and large numbers of vias. Indeed, typically large arrays of substrates are cofabricated. 
         [0097]      FIG. 1  is a simplified section through a multilayer composite support structure of the prior art. Multilayer support structures  100  of the prior art include functional layers  102 ,  104 ,  106  of components or features  108  separated by layers of encapsulating dielectric  110 ,  112 ,  114 ,  116 , which insulate the individual layers. Vias  118  through the encapsulating dielectric layer provide electrical connection between the adjacent functional or feature layers. Thus the feature layers  102 ,  104 ,  106  include features  108  generally laid out within the layer, in the X-Y plane, and vias  118  that conduct current across the encapsulating dielectric layers  110 ,  112 ,  114 ,  116 . Vias  118  are designed to have minimal inductance and are sufficiently separated to have minimum capacitances therebetween. 
         [0098]    Where vias are fabricated with drill &amp; fill technology, the vias generally have a substantially circular cross-section, as they are fabricated by first drilling a laser hole in the dielectric. Since the encapsulating dielectric is heterogeneous and anisotropic, and consists of a polymer matrix with inorganic fillers and glass fiber reinforcements, the circular cross-section thereof is typically rough edged and the cross-sections thereof may be slightly distorted from a true circular shape. Furthermore, the vias tend to taper somewhat, being inverse frusto-conical instead of cylindrical. 
         [0099]    It is a feature of Access&#39; photo-resist and pattern or panel plating and laminating technology, as described in U.S. Pat. No. 7,682,972, U.S. Pat. No. 7,669,320 and U.S. Pat. No. 7,635,641 to Hurwitz et al., incorporated herein by reference, that there is no effective upper limit to the in-plane dimensions of a feature. 
         [0100]    As described in U.S. Pat. No. 7,682,972, U.S. Pat. No. 7,669,320 and U.S. Pat. No. 7,635,641, for example, the structure of  FIG. 1  may alternatively be fabricated by plating within a pattern developed in a photo-resist (pattern plating), or by panel plating and then selectively etching, either way leaving up standing via posts, and then laminating an encapsulating dielectric pre-preg thereover. 
         [0101]    Using the ‘drilled and filled via’ approach, it becomes prohibitive to fabricate non-circular vias due to difficulties in cross-section control and shape. There is also a minimum via size of about 50-60 micron diameter due to the limitations of the laser drilling. These difficulties were described at length in the background section hereinabove and are related, inter-alia, to dimpling and/or domed shaping that result from the copper via fill electro-plating process, via tapering shape and side wall roughness that result from the laser drilling process and higher cost that results from using the expensive laser drilling machine for milling slots, in a ‘routing’ mode to generate trenches in the polymer/glass dielectrics. 
         [0102]    In addition to the other limitations of laser drilling as described hereinabove, there is a further limitation of the drill &amp; fill technology in that it is difficult to create different diameter vias in the same layer, since when different sized via channels are drilled and then filled with metal to fabricate different sized vias, the via channels fill up at different rates. Consequently, the typical problems of dimpling or overfill (doming) that characterize drill &amp; fill technology are exasperated, since it is impossible to simultaneously optimize deposition techniques for different sized vias. Thus in practical applications, drill &amp; fill vias have substantially circular cross-sections albeit sometimes distorted somewhat due to the heterogeneous nature of the substrate, and all vias have substantially similar cross-sections. 
         [0103]    Furthermore, it will be noted that laser drilled vias in composite dielectric materials such as polyimide/glass or epoxy/glass or BT (Bismaleimide/Triazine)/glass or their blends with ceramic and/or other filler particles, are practically limited to about 60×10 −6  m diameter, and even so suffer from significant tapering shape as well as rough side walls due to the nature of the composite material drilled, in consequence of the ablation process involved. 
         [0104]    It has been surprisingly found that using the flexibility of the plating and photo-resist techniques, a wide range of via shapes and sizes may be cost-effectively fabricated. Furthermore, different via shapes and sizes may be fabricated in the same layer. This is especially facilitated when the copper pattern plating approach is used, by first depositing a metal seed layer and then depositing a photo-resist material and developing smooth, straight, non-tapering trenches therein which may subsequently be filled by depositing copper into these trenches by pattern plating onto the exposed seed layer. In contrast to the drilled &amp; filled via approach, via post technology enables trenches in a photoresist layer to be filled to obtain dimple-less and dome-less copper connectors. After deposition of the copper, the photoresist is subsequent stripped away, the metal seed layer is removed and a peitilanent, polymer-glass composite encapsulating material is applied thereover and therearound. The ‘via conductor’ structure thus created may use the process flows as described in U.S. Pat. No. 7,682,972, U.S. Pat. No. 7,669,320 and U.S. Pat. No. 7,635,641 to Hurwitz et al. 
         [0105]    In addition to via conductor and features, it has been found possible to fabricate passive components such as capacitors and filters, within structures that include via post technology, by using electroplating, PVD and encapsulation technologies for creating the capacitors and filters. 
         [0106]    With respect to  FIG. 2 , a cross section through a one layer parallel plate capacitor  20  is shown consisting of a dielectric material layer  22  deposited over a copper feature layer  24 , with a copper pillar  26  grown over the dielectric layer  22 . The dielectric material may be Ta 2 O 5 , BaO 4 SrTi, TiO 2 , Al 2 O 3 , for example, and may be deposited by a physical vapor deposition process, such as sputtering, for example, or by a chemical vapor deposition process. 
         [0107]    To obtain high quality capacitors, the dielectric may include Ta 2 O 5 , BaO 4 SrTi, TiO 2  deposited by a physical vapor process, and may further comprise a layer of aluminium metal that is previously or subsequently deposited, possibly by sputtering along side the ceramic. After depositing, the structure is heated up in the presence of oxygen, either in a furnace or oven, or by exposing to infra red radiation. The aluminium is then converted in situ into aluminium oxide (alumina Al 2 O 3 ). Since Al 2 O 3 , is less dense than aluminium, it spreads and seals defects into the ceramic layer, ensuring a high dielectric constant, and preventing leakage. 
         [0108]    The copper pillars  26 ,  28 ,  30 ,  32  are encapsulated in an encapsulating dielectric material  34 . Where copper pillars  26 ,  28 ,  30 ,  32  are fabricated as via posts using electroplating, the encapsulating dielectric material  34  may be a glass fiber reinforced polymer resin prepreg that is laminated over the copper pillars  26 ,  28 ,  30 ,  32 . 
         [0109]    The copper feature layer  24  may have a thickness of about 15 microns, with a tolerance of about +−5 microns. Each via post layer is typically about 40 microns but may be anywhere from, say, 20 microns to 80 microns. Outer feature layers  24 ,  38  which may be termination pads, are again typically about 15 microns but may be anywhere from, say, 10 microns to 25 microns. 
         [0110]    The capacitance of a capacitor is defined by the dielectric constant of the dielectric layer multiplied by the surface area of the capacitor, which is the area of the via pillar  26 , divided by the thickness of the dielectric layer  22 . 
         [0111]    Using the simple one layer capacitor of  FIG. 2 , it is possible to optimize the thickness of the dielectric material  22  and the deposition process thereof. The capacitance is a property of the dielectric constant of the dielectric material  22 , and of the area of the metal electrodes, which, in this case, is the cross-sectional area of the copper pillar  26 . 
         [0112]    In typical embodiments, noble metal electrodes, typically from tantalum, but optionally from gold or platinum are applied on either side of the dielectric layer. The capacitor is thus incorporated within a via layer at the base of a via post. Keeping the thickness and nature of the dielectric layer constant, where the via post defines the upper electrode, it defines and can be used to fine tune the capacitance, 
         [0113]    As explained in more detail hereinbelow, even where tantalum electrodes are used, deposition of a carefully sized via post, which may be formed by electroplating and thus need not be cylindrical, but may be rectangular or have another cross-section shape, enables plasma etching away of the electrode and dielectric layers of the capacitor, leaving the capacitor sandwich only by a selective etch that removes tantalum and tantalum oxide but does not harm copper, such as Hydrogen fluoride and oxygen, for example. 
         [0114]    Combinations of capacitors and inductors may serve as filters, protecting chips from fluctuating currents and noise. Such filters are of particular importance with regard to RF telecommunications, such as WIFI, Bluetooth, and the like. Filters may serve to isolate parts of a circuit from other elements, to prevent interference. 
         [0115]    With reference to  FIG. 3 , there is shown a schematic projection of an inductor  40  within a feature layer and an adjacent via post  42  in a via post layer standing on a capacitor  44  that is coupled in series with the inductor  40 . The structure shown may be fabricated from copper, with the capacitor  44  comprising a dielectric material such as Ta 2 O 5 , BaO 4 SrTi, and TiO 2 , and typically has electrodes of tantalum or another noble metal. Typically, the via post will be encapsulated within a polymer dielectric, which may include fillers, and may be a woven fiber prepreg. The feature layer including the inductor  40  may be first deposited with the capacitor  44  and via post  42  built up thereover, the polymer based dielectric material, which may be a polymer film or a woven fiber pre-preg, may be laminated over the feature and via layers. Alternatively, the via post  42  and capacitor  44  may be fabricated and laminated first, with the inductor  40  then deposited thereover, and left non-laminated, or may be subsequently laminated with additional via layers, not shown. 
         [0116]    It will be appreciated that the feature layer is very thin, typically about  10  microns. The via layer however, is rather thicker.  FIG. 4  is a schematic projection of an inductor via  56  that extends within the via layer coupled in series with a capacitor  54  at a base of a via post  52 . The capacitor  54  is coupled to the inductor via  56  by a trace  58  deposited in the feature layer. Inductor via  56  has a thickness of about  30  microns and has different characteristics from feature layer inductor  40  of  FIG. 3 . Typically, the inductor via  40  is a high Q inductor having an inductance ranging from about 0.1 nH to about 10 nH. 
         [0117]    With reference to  FIG. 5 , a filter may be fabricated that includes a pair of inductors, a first inductor  60  within a feature layer and a second inductor  66  within a via layer, coupled in series to each other and to a capacitor  64  at the base of a via post  62  within the via layer of the via inductor  66 . 
         [0118]    It will be appreciated that for some filtering purposes, it is required to couple the components in parallel. 
         [0119]      FIG. 6  is a schematic projection of an inductor  70  in a feature layer, coupled in parallel with a capacitor  74 . The capacitor  74  and the inductor  70  are coupled together by via posts  71 ,  72  and a trace  78  in a second, upper feature layer or on the outside of the multilayer structure. 
         [0120]      FIG. 7  is a schematic projection of an inductor  80  in a feature layer, coupled in series with an inductive via  86 , and in parallel with a capacitor  84 , the capacitor  84  and the inductive via  86  being coupled together by a trace  88  in a second, (shown as upper) feature layer or on the outside of the multilayer structure. 
         [0121]    With reference to  FIG. 8  and to  FIGS. 8(   i ) to  8 ( xx ), a method of fabricating a capacitor embedded in a dielectric is shown. The capacitor  248  shown in  FIG. 8(   xx ) has dedicated electrodes of a different material, typically a noble metal such as gold, platinum or tantalum. Generally tantalum is used, as it cheaper than gold or platinum. 
         [0122]    Firstly, a carrier  210  is procured—step  8 (i). The carrier  210  is typically a sacrificial copper substrate. In some embodiments, it may be a copper carrier with a quick release thin film of copper appended thereto. 
         [0123]    A barrier layer  212  is deposited onto the copper carrier  210 —step  8 (ii). The barrier metal layer  212  may be fabricated from Nickel, Gold, Tin, Lead, Palladium, Silver and combinations thereof. In some embodiments, the barrier metal layer has a thickness in a range of from 1 micron to 10 microns. Typically, the barrier layer  212  comprises nickel. A thin layer of nickel may be deposited by a physical vapor deposition process or by a chemical deposition process, and typically it is sputtered or electroplated onto the copper carrier. For fast processing, the barrier layer  212  may be electroplated. To ensure planarity and a smooth surface, it may then be planarized—step  8 (iii) ( FIG. 8(   iii )), by chemical mechanical polishing (CMP) for example. 
         [0124]    A thin layer of copper  214  is now deposited onto the barrier layer  212 —step  8 (iv). The thickness of the copper layer  214  is typically several microns and may be fabricated by sputtering or by electroplating. 
         [0125]    A first electrode  216  is now deposited—step  8 (v). By way of example, first electrode  216  may be fabricated from tantalum by sputtering. 
         [0126]    A dielectric layer  218  is now deposited—step  8 (vi). For high performance capacitors, the dielectric layer  218  must be kept as thin as possible, without risking faults that enable charge leakage. There are various candidate materials that may be used. These include Ta 2 O 5 , BaO 4 SrTi, and TiO 2 , which may be deposited by sputtering, for example. Typically the thickness of the dielectric layer  218  is in the range of 0.1 to 0.3 microns. 
         [0127]    A second electrode  220  may now be deposited step  8 (vii). By way of example, second electrode  220  may be fabricated from tantalum by sputtering. 
         [0128]    In a variant process, a second noble electrode  220  is not applied. Rather, a copper via is deposited directly onto the dielectric, its footprint defining the upper electrode and thus the effective area and capacitance of the capacitor. 
         [0129]    Furthermore, it is difficult to fabricate thin dielectric layers of Ta 2 O 5 , BaO 4 SrTi, or TiO 2  without defects that may result in charge leakage. To overcome this problem, in some embodiments an aluminium layer (not shown) is deposited before or after depositing the Ta 2 O 5 , BaO 4 SrTi, or TiO 2  layer, and by exposure to heat in an oxygen environment, the aluminium layer is oxidized into the high dielectric ceramic alumina (Al 2 O 3 ). In this manner, it is possible to cure defects and to ensure that a continuous thin dielectric separates the electrodes. 
         [0130]    In the main process, a further layer of copper  222  is deposited over the second electrode  220 —step  8 (viii). Further layer of copper  222  may be deposited by sputtering or by electroplating, for example. The upper copper layer  222  may be patterned using photoresists to pattern plate or by printing and etching to fabricate pads, conductors and inductors, for example. A layer of photoresist  208  may be applied beneath the copper carrier  210 , and a second layer of photoresist  224  is applied over the further layer of copper  222  and developed into a pattern—step  8 (ix). 
         [0131]    Areas of the further layer of copper  222  that are not protected by the patterned photoresist  224  are etched away—step  8 (x). A wet etch may be used. By way of example, one way of etching away the areas of the further layer of copper  222  not protected by the patterned photoresist  224  consists of exposing the sacrificial substrate to a solution of ammonium hydroxide at an elevated temperature. Alternatively copper chloride or a wet Ferric Chloride etch may be used. 
         [0132]    The exposed electrode layers  216 ,  220  and dielectric layer  218  may be removed by dry etching using a plasma etching process—step  8 (xi). For example hydrogen fluouride and oxygen may be used to etch TiO 2  or Ta 2 O 5  and hydrogen fluoride and Argon to etch BaO 4 SrTi (BST). Typical concentration ratios for CF 4 :O 2  are in the range of between  50 : 50  to 95:5 where 95 is for the CF 4 . Typical concentration ratios for CF 4 :Ar can be any ratio between 50:50 to 95:5 where 95 if for Ar. 
         [0133]    In a variant method, as described hereinabove, no upper electrode  220  is deposited. Rather a copper via is fabricated directly onto the dielectric material. Patterning a photoresist, either with a stencil or with a laser, enables accurate control of the cross-sectional size and shape of the via, which serves as the upper electrode and defines the capacitance of the capacitor, since the capacitance is proportional to the effective area of the via electrode. 
         [0134]    In the main process, the patterned photoresist  224  is now stripped away—step  8 (xii) as is generally, the second layer of photoresist  208 , which is shortly replaced with a similar layer of photoresist  228 —so could be retained. 
         [0135]    A seed layer of copper is deposited  226  over and around the capacitor and exposed copper layer  214 . To help adhesion, a first seed layer of titanium may be first deposited—step  8 (xiii)  FIG. 8(   xiii ). 
         [0136]    Now moving to a different scale for  FIG. 8(   xiv ) onwards, a further layer of photoresist  228  is applied to protect the copper substrate (assuming that layer  208  was removed), and a thick layer of photoresist  230  is deposited and patterned over the seed layer  226 . Copper interconnects  232  are electroplated into the pattern created by the photoresist  230 —step  8 (xv). 
         [0137]    The photoresist  228  ( 208 ),  230  is now stripped away, leaving the capacitor  248  shorted by seed layer  226 , and the copper via post  232  interconnect, exposed—step  8 (xvi). 
         [0138]    The seed layer  226  is etched away—step  8 (xvii), with a quick etch to do minimal damage to the copper layer  214  and the via  232 , but to ensure that the copper layer  214  and the copper via  232  are isolated from each other by the capacitor. A layer of a polymer based dielectric material  234  is now laminated over the copper substrate and via—step  8 (xviii). The polymer based dielectric material  234  is typically a polyimide, epoxy or BT (Bismaleimide/Triazine) or their blends, and may be reinforced with glass fibers. In some embodiments, a prepreg consisting of woven fiber mats in a polymer resin may be used. The polymer matrix may include inorganic particulate fillers that typically have a mean particle size of between 0.5 microns and 30 microns and the polymer typically includes between 15% and 30% of particulate by weight. 
         [0139]    Although sometimes referred to as a being a dielectric, the polymer based dielectric material  234  has a lower dielectric constant than that of the dielectric layer  218 , which is typically a more exotic material such as Ta 2 O 5  or BaO 4 SrTi or TiO 2 . 
         [0140]    The cured polymer based dielectric material  234  is then thinned and planarized, by chemical mechanical polishing (CMP) for example, thereby exposing the end of the copper via  232 —step  8 (xix). A further seed layer of copper  236  is then deposited over the polymer based dielectric material  234  and the end of the copper vias  232 —step  8 (xx). A layer of photoresist  238  is deposited over the seed layer  236  and the layer of photoresist  238  is patterned—step  8 (xxi). A feature layer of copper  240  is then electroplated into the pattern—step  8 (xxii). 
         [0141]    The photoresist  238  may now be stripped away—Step  8 (xxiii). 
         [0142]    At this stage, the lower copper layer  214  is coupled by the copper interconnect  232  to the upper copper layer  240 , via a capacitor  248  embedded in the copper interconnect  232 . 
         [0143]    A further layer of photoresist  242  may be deposited and patterned—step  8 (xxiv), and copper vias  244  may be electroplated into the pattern—step  8 (xxv). 
         [0144]    The photoresist  242  may be stripped away leaving the upstanding copper vias  244 —step  8 (xxvi), and the copper seed layer  236  is etched away—step  8 (xvii). This may be removed by a dry plasma etch, or by a short etch with copper chloride or with ammonium chloride solution. 
         [0145]    The present invention is capable of many variations, with reference to  FIG. 8(   xviii ), prior to laminating the polymer based dielectric material  234  over the copper substrate and via, the structure is plasma etched with a plasma etch that copper is resistant to, but which tantalum and titanium oxide are susceptible to, such as a mix of hydrogen fluoride and oxygen.—step  10 (xviii). This reduces the dimensions of the capacitor to that of the via post  232 . Since the via post  232  is fabricated by electroplating into a photoresist, this provides the possibility of fabricating to virtually any size and shape with high accuracy, and may be square or rectangular, instead of round, to enable high packing density. Removing the excess capacitor material enables high packing density between components. Capacitor  348  or capacitor  248  is then embedded in a polymer based dielectric material  234  that is typically a polyimide, epoxy or BT (Bismaleimide/Triazine) or their blends, and may be reinforced with glass fibers— 10 (xix). In some embodiments, a prepreg consisting of woven fiber mats in a polymer resin may be used for the encapsulation. The polymer matrix  234  may include inorganic particulate fillers that typically have a mean particle size of between 0.5 microns and 30 microns and the polymer typically includes between 15% and 30% of particulate by weight. 
         [0146]    With reference to  FIG. 8(   xx ) the dielectric material  232  may be thinned and planarized, exposing the end of the copper via  232 , and a copper seed layer  236  may be deposited thereover—step(xxi). Photoresist  238  may be deposited and patterned—step(xxii) and a copper feature layer  240  may be deposited into the pattern—step(xxiii). The pattern of photoresist  238  may be stripped away leaving the feature layer  240  upstanding—step (xxiv), and a further layer of vias  244  may be built up by laying down and patterning a thicker layer of photoresist  242 —step  8 (xxiv), and then pattern plating copper vias  244  into the patterned photoresist  238 —step  8 (xxv). 
         [0147]    The copper carrier  212  may also be etched away, typically using a copper chloride or ammonium chloride solution for so doing—step  8 (xxvi), the (typically nickel) barrier layer  212  serving as an etch stop. 
         [0148]    The barrier layer  214  may then be removed with an appropriate etching technique, such as plasma etching, or with a specific chemical etchant—step  8 (xxvii). For example, to etch away nickel without removing copper, a mixture of nitric acid hydrogen peroxide may be used. Possible alternatives that dissolve nickel include hydrochloric acid +hydrogen peroxide, hot concentrated sulfuric acid and iron(III) chloride acidified with hydrochloric acid. 
         [0149]    The polymer layer  246  is then thinned and planarized—step  8 (xxviii), to expose the ends of the copper vias  244 . Grinding, polishing or a combined chemical mechanical polishing (CMP) may be used. 
         [0150]    Thus far, we&#39;ve shown how an advanced, high performance capacitor  248  may be embedded into a composite structure  250  comprising copper feature layers  216 ,  240  and copper vias  232 ,  244 , embedded in a polymer based dielectric matrix  234 ,  246 . 
         [0151]    Since the in-plane shape of the capacitor plates and dielectrics are determined by patterning photoresist, it will be appreciated that the capacitor may take substantially any shape, and typically will be square or rectangular, but may be circular, or indeed may have practically any other shape. The capacitor may have one, two, three or more layers. The thickness of the dielectric may be carefully controlled, so it is possible to tailor capacitors of the invention to have substantially any capacitance over a large range, and it is possible to accurately control the capacitance, optimizing it for particular operating frequencies. 
         [0152]    It will also be noted that via  244  is not restricted to being a simple cylindrical via post, since it is not fabricated by the drill &amp; fill technology. By fabricating using electroplating into a pattern within a photoresist  242 , via  244  may also have substantially any shape and size. Since via  244  may be an extensive wire within the via layer, via  244  may be an inductor and is preferably a high Q inductor having an inductance ranging from about 0.1 nH to about 10 nH. It should be also noted that such an “inductor via” may be combined with an inductor structure from the feature layers  214 ,  240  and/or  260 ,  262 , shown hereinbelow, with reference to  FIG. 8(   xxxv ), etc. The combination of a capacitor  248  and an inductor  244  enables the provision of an RF filter. 
         [0153]    With reference to—steps  9 (xxxiii) to steps  9 (xL), a technology for fabricating the ports of a filter is described. 
         [0154]    With reference to step  9 (xxxiii), a titanium seed layer  252  is now sputtered over the matrix  246  and the exposed ends of the copper (inductor) vias  244 . Referring to step  6 (xxxiv), a copper layer  254  is now sputtered over the titanium layer  252 . 
         [0155]    With reference to step  9 (xxxv), layers of photoresist  256 ,  258  are laid down and patterned on each side of the composite structure  250 . Referring to step  9 (xxxvi), copper  260 ,  262  is electroplated into the patterned photoresist  256 ,  258  to create ports. 
         [0156]    With reference to step  9 (xxxvii), the layers of photoresist  256 ,  258  are now stripped away leaving the copper upstanding. With reference to step  9 (xxxviii), the titanium and copper layers are etched away. Copper pads  260 ,  262  will be slightly damaged in this process. 
         [0157]    The hollows thus formed may be filled with solder mask  264 —step  9 (xxxix), and the copper protected with ENEPIG  266 —step  9 (xL) or other appropriate termination technology. 
         [0158]    With reference to  FIG. 10   a , which is a three dimensional representation shows the structure of  FIG. 9(   x L), to  FIG. 10   b  which is an equivalent circuit diagram, and to  FIG. 10   c , which is essentially the structure of  FIG. 9(   x L), it will be appreciated that the structure thus created is essentially a basic LC low pass filter  300  consisting of four ports, P 1 , P 2 , P 3 , P 4 , a capacitor C and an inductor L. 
         [0159]    Referring to  FIG. 10   d , in a variant manufacturing technique using the plasma etching step shown in  FIG. 10(   xxxiii ), the footprint of via V 2  defines the capacitance and the size of the capacitor C 2 , where excess material is etched away with a plasma etch. Thus  10   d  is a schematic cross section of a basic LC low pass filter equivalent to  FIG. 10   a  wherein the top the via pillar V 2  defines the size of the electrodes and dielectric layer of the capacitor, as in the structures of  FIGS. 2 to 7 . 
         [0160]      FIG. 10   e  is a schematic cross section of yet another basic LC low pass filter of  FIG. 10   a  wherein the top electrode of the capacitor C 3  is the via pillar V 3  without depositing an upper electrode of noble metal. Here care must be taken to remove all of the copper seed layer from the dielectric. 
         [0161]    It will be appreciated that the technology detailed in  FIG. 8  and  FIGS. 8(   i ) to  FIG. 8(   xxxii ) and  FIG. 9(   xxxiii ) to  FIG. 9(   x L) can be used to create a very wide range of filters circuits with different characteristics. For example, with reference to  FIGS. 11   a  and  11   b  a basic LC high pass filter may be fabricated. With reference to  FIGS. 12   a  and  12   b , a basic LC series band pass filter may be fabricated, as, with reference to  FIGS. 13   a  and  13   b , a basic LC parallel band pass filter may be fabricated. With reference to  FIGS. 14   a  and  14   b , with appropriate variations, mutatis mutandis, a Low Pass Parallel-Chebyshev filter can be fabricated. 
         [0162]    Although single filters have been illustrated, it will be appreciated that in practice, vast arrays of such filters are cofabricated in large plates that may then be singulated. Other components may be cofabricated together with the filters. The filter  260  may be surface mounted on a substrate or embedded into a substrate by depositing further feature and via layers there-around. 
         [0163]    In general, there is an inherent disadvantage with embedded components, in that if something goes wrong, the component and the structure into which it is embedded must be discarded. Sometimes, diagnosing the route cause of a problem may be difficult where a component cannot be isolated and tested individually. However, due to demands for the expensive (real estate) on the surface of the substrate and a general trend towards miniaturization, there are significant advantages in embedding filters and other passive components. 
         [0164]    It is a feature of the present invention, that filters and other passive components may be fabricated as stand alone products for surface mounting, but may be optimized and then the processing may be integrated into the fabrication processing of the substrate to embed such components. 
         [0165]    The capacitances of capacitors formed depend on the electrode plate area, the thickness of the dielectric and its dielectric constant. Typically, capacitors for RF filters have capacitances of between about 5 and about 15 pF. It is possible to control the capacitance to a narrow range, such as between 9 and 12 pF, and even to between 10 and 11 pF. 
         [0166]    Inductors of the invention may have inductances in the range of nano-Henrys. Say from 0.2 nH to 300 nH, but typically, from 1 nH to about 10 nH. 
         [0167]    It is possible to control the inductances of these inductors to narrow ranges, such as has to the range of from about 4 nH to about 8 nH, or even, where required to a range of less than one nano Henry, say between about 5 nH and about 6 nH. 
         [0168]    The above description is provided by way of explanation only. It will be appreciated that the present invention is capable of many variations. 
         [0169]    Several embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims. 
         [0170]    Thus persons skilled in the art will appreciate that the present invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined by the appended claims and includes both combinations and sub combinations of the various features described hereinabove as well as variations and modifications thereof, which would occur to persons skilled in the art upon reading the foregoing description. 
         [0171]    In the claims, the word “comprise”, and variations thereof such as “comprises”, “comprising” and the like indicate that the components listed are included, but not generally to the exclusion of other components.