Abstract:
An integrated amplifier may include a transconductance stage including a differential pair of input transistors of a first type of conductivity, respective resistive loads coupled to said input transistors, and a first bias circuit coupled to the input transistors. The first bias circuit may include a second differential pair of bias transistors having first conduction terminals coupled in common and second conduction terminals coupled to respective conduction terminals of the input transistors. The first bias circuit may also include respective second bias circuits coupled to the bias transistors to enable the input transistors in a conduction state with the input transistors being biased by a same respective bias current that flows through the respective input transistors. The first bias circuit may also include a capacitive network coupled to the bias transistors to define with the input transistors a feedback loop.

Description:
FIELD OF THE INVENTION 
   This invention relates to AC amplifiers, and more particularly, to a low noise differential AC amplifier with reduced low corner frequency and reduced current consumption. 
   BACKGROUND OF THE INVENTION 
   In many applications it may be desirable to amplify an AC signal superimposed to a relatively large DC component. In these cases, an AC amplifier input with this signal through decoupling capacitors is commonly used. In particular, this happens in signal channels for recording data in hard disk drives (HDD). 
   Two modes of recording data on a HDD are the so-called longitudinal recording and the vertical recording. As far as the AC amplifier is concerned, the main difference between these two techniques is that when using the longitudinal recording technique, a typical spectrum of an AC signal to be amplified, differs relevantly from the spectrum of the corresponding signal when using the vertical recording technique. As may be observed by comparing the two diagrams of  FIG. 1 , signals used for recording data on a HDD using the vertical recording technique have a non-negligible power content at low frequencies. 
   Therefore, the pass-band of AC amplifiers optimized for vertical recording may extend to relatively low frequencies, in other words they may have a small low corner frequency (LCF). 
   Typically, an AC amplifier includes a differential amplifier, as that of  FIG. 2 . A differential input signal is fed to the inputs INA and INB through respective decoupling input capacitors C. The architecture of this amplifier is very simple, but a sufficiently reduced LCF may be achieved using relatively large decoupling capacitors C. 
   Unfortunately, in integrated circuits, when the size of the decoupling capacitors C is enlarged, the parasitic capacitances CP 1  and CP 2  between the plates of the integrated capacitors, and the silicon substrate on which the amplifier is integrated, significantly increase. Thus, also, the input capacitance of the amplifier increases. 
   In order to keep parasitic capacitances below a maximum acceptable value, these relatively large DC-decoupling capacitors are fabricated with expensive techniques that may require additional masks and fabrication steps. 
   This drawback may be obviated with the AC amplifier disclosed in the European patent application No. 03425561.2 and depicted in  FIGS. 3 and 4 . It has been found possible to effectively decouple the DC component of the input signal by employing, for this purpose, decoupling capacitors in a position such that parasitic capacitances associated to the plates of decoupling capacitors do not degrade the input capacitance figure of the stage. The LCF is increased and effects of parasitic capacitances are reduced with the circuit of  FIGS. 3 and 4  at the cost of increasing noise and current consumption (for an unchanged overall gain). 
   SUMMARY OF THE INVENTION 
   An architecture of an AC differential amplifier that, while providing for a desirably small input capacitance, restrains any increase of current consumption to practically maintain it identical to that of the prior art amplifier of  FIG. 2  has now been found. 
   This result may be attained by connecting to the current nodes (for leaving unchanged the input capacitance) of the transistors of the differential pair, that amplifies the input differential signal, a degeneration network that constitutes with the first differential pair a high frequency feedback loop. The degeneration network may include a capacitive network and a second differential pair of transistors of an opposite type of conductivity to that of the first differential pair, and may be connected in series thereto, such that the same bias current of the first pair also biases the second pair. 
   The amplifier of the preferred embodiments overcomes the drawbacks of known amplifiers because its capacitive network does not alter the input capacitance of the differential input pair of transistors, because it is connected to the current nodes of the transistors and it is not in the path of the differential input signal, the low corner frequency (LCF) is determined by the capacitance of the capacitive network combined with the π resistance of the transistors of the second differential pair or with a resistance of the network and not by eventual parasitic capacitances, and the same bias current that flows through the first differential pair biases also the second differential pair. Thus, a single current generator is sufficient instead of two current generators as in the prior circuit of  FIGS. 3 and 4 . 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1   a  and  1   b  show sample power frequency spectra of signals used in longitudinal recording and vertical recording of HDDs, respectively as in the prior art. 
       FIG. 2  depicts a known AC amplifier as in the prior art. 
       FIG. 3  shows an embodiment of a differential AC amplifier according to the European patent application No. 03425561.2 as in the prior art. 
       FIG. 4  shows a detailed embodiment of the amplifier of  FIG. 3  as in the prior art. 
       FIG. 5  shows a first embodiment of the integrated AC amplifier of this invention. 
       FIG. 6   a  is a single-ended architecture of an alternative embodiment of the integrated AC amplifier of this invention. 
       FIG. 6   b  depicts Bode diagrams of the main parameters of the circuit of  FIG. 6   a.    
       FIG. 7   a  is a single-ended architecture of another alternative embodiment of the integrated AC amplifier of this invention. 
       FIG. 7   b  depicts Bode diagrams of the main parameters of the circuit of  FIG. 7   a.    
       FIG. 8  is a single-ended architecture of yet another alternative embodiment of the integrated AC amplifier of this invention. 
       FIG. 9  is a single-ended architecture of a fifth alternative embodiment. 
       FIG. 10  is a single-ended architecture of a sixth alternative embodiment. 
       FIG. 11  is a single-ended architecture of a seventh alternative embodiment. 
       FIG. 12  is a single-ended architecture of an eighth alternative embodiment. 
       FIG. 13   a  is a single-ended architecture of a modified embodiment of the integrated AC amplifier of  FIG. 12 . 
       FIG. 13   b  depicts Bode diagrams of the main parameters of the circuit of  FIG. 13   a.    
       FIG. 14   a  is a single-ended architecture of a tenth alternative embodiment. 
       FIG. 14   b  depicts Bode diagrams of the main parameters of the circuit of  FIG. 14   a.    
       FIG. 15  is a single-ended architecture of an eleventh alternative embodiment. 
       FIG. 16   a  is a single-ended architecture of a twelfth embodiment of the integrated AC amplifier with small bias current of this invention. 
       FIG. 16   b  depicts Bode diagrams of the main parameters of the circuit of  FIG. 16   a.    
       FIGS. 17 to 20  depict yet other embodiments of the integrated AC amplifier of this invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 5  depicts a first embodiment of the integrated AC amplifier with a small bias current. The proposed structure substantially includes a transconductance stage having a differential input pair of transistors Q 1   a  and Q 1   b , that in the embodiment of  FIG. 5  are two bipolar transistors NPN, connected to load resistors R 2   a  and R 2   b , and a second differential pair of transistors Q 2   a , Q 2   b , each biased by the same current that flows in the respective input transistor Q 1   a , Q 1   b . The transistors of the second differential pair Q 2   a , Q 2   b  are biased by dedicated bias means or current generators Ia and Ib, as in the case shown in  FIG. 4 . 
   Preferably, the currents Ia and Ib are fixed or controlled through a feedback loop for substantially nullifying the output offset voltage. 
   To better understand the functioning of the circuit of  FIG. 5 , let us refer to the single-ended circuit of  FIG. 6   a , that corresponds to a half of the integrated pre-amplifier. In the equivalent scheme, the capacitor C 2  connected between the bases of the transistors of the second differential pair Q 2   a , Q 2   b  is substituted with a capacitor of double capacitance 2*C 2 . 
   The gain of the amplifier is:
 
GAIN= Gm ( s )· Z load( s )
 
wherein Gm is the transconductance of the degenerated input stage and Zload is the impedance of the load R 2   a . Being gm 1  and gm 2  the transconductances of the transistors Q 1   a  and Q 2   a , respectively, Zdeg the impedance of the degeneration network 2*C 2 , Q 2   a , Ia, seen from the emitter of the input transistor Q 1   a , and being β 2  the current gain of the transistor Q 2   a , the gain of the transconductance stage is:
 
             Gm   ⁡     (   s   )       =       gm   1       1   +       gm   1     ·     Zdeg   ⁡     (   s   )                       wherein               Zdeg   ⁡     (   s   )       =       1   +       2   ·   s   ·   C     ⁢           ⁢     2   ·   R     ⁢           ⁢   π   ⁢           ⁢   2           2   ·   s   ·   C     ⁢           ⁢     2   ·     (       β   ⁢           ⁢   2     +   1     )                     and               Zload   ⁡     (   s   )       =     R   ⁢           ⁢   2   ⁢   a           
The Bode diagrams of Gm, Zdeg and Zload are depicted in  FIG. 6   b.    
The low corner frequency of the circuit is given by the following formula:
 
                 LCF   ≈       ⁢         gm   ⁢           ⁢   2         2   ·   β   ·   C     ⁢           ⁢   2       ·       gm   ⁢           ⁢   1         gm   ⁢           ⁢   1     +     gm   ⁢           ⁢   2                       ≈       ⁢       1   2     ·       gm   ⁢           ⁢   2     β     ·     1       2   ·   C     ⁢           ⁢   2                     ≈       ⁢       1   2     ·     1     R   ⁢           ⁢   π   ⁢           ⁢   2       ·     1       2   ·   C     ⁢           ⁢   2                     
By contrast, the LCF of the prior circuit of  FIG. 2  is:
 
   
     
       
         
           LCF 
           ≈ 
           
             1 
             
               R 
               ⁢ 
               
                   
               
               ⁢ 
               
                 π2 
                 · 
                 C 
               
             
           
         
       
     
   
   By biasing the proposed circuit with the same bias current used in the circuit of  FIG. 2 , the following condition is satisfied:
 
Rπ=Rπ2
 
   The same low corner frequency of the prior circuit of  FIG. 2  may be attained with a single differential capacitor C 2  four times smaller of each of the two single-end capacitors C. Moreover, parasitic capacitances of C 2  are connected to nodes that, at high frequency, are grounded and do not influence the AC functioning of the amplifier. 
   In practice, with the circuit of  FIG. 5  or  6   a  it is possible to reduce the sensitivity to parasitic capacitances and obtain enhanced noise figures in respect to the prior circuit of  FIG. 3 , absorbing only half of the bias current. The pre-amplifiers of  FIGS. 5 and 6   a  have the same power consumption of the known circuit of  FIG. 2  but a larger band-pass and noise figures that are almost equal to that of the circuit of  FIG. 2 . This could be due to the fact that the transistors of the second differential pair Q 2   a  and Q 2   b  generate extra noise and for this reason the noise figures worsen. This worsening is relatively small, and it is largely compensated by the increase of band-pass and by reduction to sensitivity to parasitic capacitances. 
   It is possible to limit degradation of noise immunity performances in the frequency range from 0 to gm2/(2*C 1 ) using a capacitor C 1 , as depicted in  FIG. 7   a . The filters R 1   a , C 3   a  and R 1   b , C 3   b  are used to keep the frequency response substantially flat by compensating the zero-pole pair introduced by the capacitor C 1 . 
   The low-corner frequency is substantially unchanged in respect to the circuit of  FIG. 6   a  or  5 . The gain of the transconductance stage is: 
   
     
       
         
           
             Gm 
             ⁡ 
             
               ( 
               s 
               ) 
             
           
           = 
           
             
               gm 
               ⁢ 
               
                   
               
               ⁢ 
               1 
             
             
               1 
               + 
               
                 gm 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   1 
                   · 
                   
                     Zdeg 
                     ⁡ 
                     
                       ( 
                       s 
                       ) 
                     
                   
                 
               
             
           
         
       
     
     
       
         wherein 
       
     
     
       
         
           
             Zdeg 
             ⁡ 
             
               ( 
               s 
               ) 
             
           
           = 
           
             
               s 
               + 
               
                 
                   gm 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
                 
                   
                     2 
                     · 
                     β 
                     · 
                     C 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
             
             
               
                 s 
                 · 
                 C 
               
               ⁢ 
               
                   
               
               ⁢ 
               
                 1 
                 · 
                 
                   ( 
                   
                     s 
                     + 
                     
                       
                         gm 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                       
                         
                           2 
                           · 
                           C 
                         
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     + 
                     
                       
                         gm 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                       
                         
                           2 
                           · 
                           β 
                           · 
                           C 
                         
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
     
       
         and 
       
     
     
       
         
           
             Zload 
             ⁡ 
             
               ( 
               s 
               ) 
             
           
           = 
           
             R 
             ⁢ 
             
                 
             
             ⁢ 
             2 
             ⁢ 
             
               a 
               · 
               
                 
                   R 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                   ⁢ 
                   a 
                 
                 
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                     ⁢ 
                     a 
                   
                   + 
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                     ⁢ 
                     a 
                   
                 
               
               · 
               
                 
                   s 
                   + 
                   
                     1 
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                       ⁢ 
                       
                         a 
                         · 
                         C 
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                   
                 
                 
                   s 
                   + 
                   
                     1 
                     
                       
                         
                           ( 
                           
                             
                               R 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                               ⁢ 
                               a 
                             
                             + 
                             
                               R 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                               ⁢ 
                               a 
                             
                           
                           ) 
                         
                         · 
                         C 
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                   
                 
               
             
           
         
       
     
   
   The Bode diagrams of Gm, Zdeg, Zload are depicted in  FIG. 7   b.    
   These three amplifiers are largely used for controlling hard disk drivers. Typically, the input of a pre-amplifier used in a hard disk drive is controlled by a transductor, commonly called a resistive head, the resistance of which depends on the magnetic field applied thereon. Generally, the resistive head is biased with a DC current. Thus, the voltage drop thereon is the sum of a DC component and of a signal that depends on the magnetic field. 
   The magnetic field is generated by a constant current, and thus, the resistive head can be modeled as a constant voltage generator Vhead with a resistor Rhead connected in series therewith. The architectures of  FIGS. 5 ,  6   a  and  7   a  can be modified as depicted in  FIG. 8  for compensating the effects caused by the presence of the resistive head input to the differential pair Q 1   a  and Q 1   b.    
   The two voltage generators Va and Vb fix the common mode voltage and the differential voltage applied to the resistive head. The DC current that flows through the transistors Q 2   a , Q 1   a  and through the resistor R 2   a  and through the transistors Q 2   b , Q 1   b  and through the resistor R 2   b  is fixed by elements present on the feedback lines, more precisely R 3 , C 4 , A, Q 3 . These feedback lines allow correction of both the common mode voltage and the offset voltage. The amplifier Aa does not absorb any input current, thus, DC current does not flow in the resistor R 3   a . As a consequence, there is a voltage drop across on the resistor R 2   a , the DC component of which is VCC-Vref. The DC component of the current that flows through the resistor R 2   a  and through the transistors Q 1   a  and Q 2   a  is: 
           Ia   =       VCC   -   Vref       R   ⁢           ⁢   2   ⁢   a             
the RC pair, including the resistor R 3   a  and the capacitor C 4   a , introduces a dominating pole that fixes the low corner frequency to the value:
 
   
     
       
         
           LCF 
           ≈ 
           
             1 
             
               R 
               ⁢ 
               
                   
               
               ⁢ 
               
                 3 
                 · 
                 C 
               
               ⁢ 
               
                   
               
               ⁢ 
               4 
             
           
         
       
     
   
   Alternatives of the circuit of  FIG. 8  may be obtained by inserting a capacitor C 1  between the emitters of the transistors of the second differential pair Q 2   a  and Q 2   b , as depicted in  FIG. 7   a . By inserting RC pairs, including a resistor R 1  in series to a capacitor C 3 , as shown in  FIG. 7   a , thus obtained the amplifier depicted in  FIG. 9 . The bias network could be as depicted in  FIG. 5  or  7   a , that includes two current generators Ia and Ib that ground the bases of the transistors of the second differential pair Q 2   a  and Q 2   b , these two bases being connected by a capacitor C 2 , as shown above. 
   During the functioning of hard disk drives, the so-called thermal asperity effect (TA) may occur. During this phenomenon, the input DC offset voltage varies rapidly (in few nanoseconds), and thus, it returns relatively slowly (within few microseconds) to a normal value. 
   A widely used technique for reducing the effects of thermal asperity includes increasing the LCF when the thermal asperity starts and bringing this frequency back to its nominal value. The circuits depicted in  FIGS. 8 and 9  may easily perform this task. Indeed, the low corner frequency, as stated above, is substantially fixed by the resistor R 3   a  and by the capacitor C 4   a  (the resistor R 3   b  and the capacitor C 4   b  are equal to the resistor R 3   a  and to the capacitor C 4   a ). Thus, it is sufficient, for example, to vary the resistance R 3   a  (and the resistance R 3   b ) for adjusting the value of the low corner frequency. 
     FIGS. 10 and 11  depict another two embodiments of the pre-amplifier, wherein there are two identical resistors R 4   a  connected electrically in parallel to the resistors R 3   a  and R 3   b , such that the resistor connected to the amplifiers Aa and Ab is reduced. As a consequence the low corner frequency of the pre-amplifier increases. These two additional resistors are connected electrically in parallel by closing the switches at the instant in which the thermal asperity effect takes place and are for being opened when the pre-amplifier returns in its normal functioning conditions. 
   Another embodiment of the pre-amplifier is depicted in  FIG. 12 . Compared with the architecture depicted in  FIG. 5 , the current generators are not grounded, but are connected to the supply voltage line Vcc, and there is not a single capacitor that couples the bases of the transistors of the second differential pair Q 2   a  and Q 2   b  (that are NPN transistors and not PNP transistors). There are two identical transistors C 2   a  and C 2   b  connected between the base and the collector of the transistors of the second differential pair. The functioning of the circuit of  FIG. 12  may be analyzed according to the circuit of  FIG. 5 , that is, referring to the circuit of  FIG. 13   a  that depicts a single-end embodiment of the circuit of  FIG. 12 . Gm, Zdeg and Zload are given by the following equations: 
             Gm   ⁡     (   s   )       =       gm   ⁢           ⁢   1       1   +     gm   ⁢           ⁢     1   ·     Zdeg   ⁡     (   s   )                             Zdeg   ⁡     (   s   )       =       1   +       s   ·   C     ⁢           ⁢     2   ·   R     ⁢           ⁢   π2           s   ·   C     ⁢           ⁢     2   ·     (       β   ⁢           ⁢   2     +   1     )                         Zload   ⁡     (   s   )       =     R   ⁢           ⁢   2   ⁢   a           
and the relative Bode diagrams are depicted in  FIG. 13   b . Even in this case, the low corner frequency is:
 
           LCF   ≈         gm   ⁢           ⁢   2         β   ·   C     ⁢           ⁢   2       ·       gm   ⁢           ⁢   1         gm   ⁢           ⁢   1     +     gm   ⁢           ⁢   2           ≈         gm   ⁢           ⁢   2     β     ·     1       2   ·   C     ⁢           ⁢   2         ≈       1     R   ⁢           ⁢   π   ⁢           ⁢   2       ·     1       2   ·   C     ⁢           ⁢   2               
and the considerations made referring to the circuit of  FIG. 1   a  hold for the circuit of  FIG. 6   a.    
   Alternatives of the circuit of  FIG. 12  may be obtained by repeating the same observations made for the circuit of  FIG. 5 . Thus, the circuit of  FIG. 14   a  is obtained with a capacitor C 1  connected between the emitters of the transistors of the first input differential pair Q 1   a , Q 1   b  and with the filters R 1   a , C 3   a , and R 1   b . C 3   b  is for keeping the frequency response substantially flat. 
   It is possible to demonstrate for the circuit of  FIG. 14   a  that Zdeg and Zload are given by the following equations: 
             Zdeg   ⁡     (   s   )       =       s   +       gm   ⁢           ⁢   2         β   ·   C     ⁢           ⁢   2             2   ·   s   ·   C     ⁢           ⁢     1   ·     (     s   +       gm   ⁢           ⁢   2         2   ·   C     ⁢           ⁢   1       +       gm   ⁢           ⁢   2         β   ·   C     ⁢           ⁢   2         )                         Zload   ⁡     (   s   )       =     R   ⁢           ⁢   2   ⁢     a   ·       R   ⁢           ⁢   1   ⁢   a         R   ⁢           ⁢   1   ⁢   a     +     R   ⁢           ⁢   2   ⁢   a         ·       s   +     1     R   ⁢           ⁢   1   ⁢     a   ·   C     ⁢           ⁢   3           s   +     1         (       R   ⁢           ⁢   1   ⁢   a     +     R   ⁢           ⁢   2   ⁢   a       )     ·   C     ⁢           ⁢   3                     
and the relative Bode diagrams are depicted in  FIG. 14   b.    
   Instead of biasing the transistors of the second differential pair Q 2   a  and Q 2   b  with two current generators Ia and Ib, it is possible to use two buffers, as depicted in  FIGS. 15 and 16   a . The two buffers A 2   a  and A 2   b  are substantially voltage followers with high input impedance and drive the base terminals of the transistors of the second differential pair Q 2   a  and Q 2   b . The resistors R 3   a  and R 3   b  fix the DC value of the base voltage of these two transistors. The voltage followers decouple the capacitor C 2   a  (C 2   b ) from the resistance Rπ of the transistor Q 2   a  (Q 2   b ). It is possible to demonstrate that with this technique there is a pole at a frequency 1/(R 3 ·C 2 ) in the Bode diagram of the gain. By contrast, without the voltage follower this pole is at the frequency: 
   
     
       
         
           
             
               gm 
               ⁢ 
               
                   
               
               ⁢ 
               2 
             
             
               
                 β 
                 · 
                 C 
               
               ⁢ 
               
                   
               
               ⁢ 
               2 
             
           
           = 
           
             1 
             
               R 
               ⁢ 
               
                   
               
               ⁢ 
               
                 π 
                 · 
                 C 
               
               ⁢ 
               
                   
               
               ⁢ 
               2 
             
           
         
       
     
   
   Because the resistance R 3  may be much greater than the resistance Rπ of the transistors of the second differential pair, it is possible to reduce the low corner frequency, thus also reducing noise sensitivity. 
   This reduction of the low corner frequency is obtained at the cost of increasing the power absorbed by the voltage follower. The parameters Gm, Zdeg and Zload are given by the following equations: 
             Gm   ⁡     (   s   )       =       gm   ⁢           ⁢   1       1   +     gm   ⁢           ⁢     1   ·     Zdeg   ⁡     (   s   )                             Zdeg   ⁡     (   s   )       =       s   +     1     R   ⁢           ⁢     3   ·   C     ⁢           ⁢   2             2   ·   s   ·   C     ⁢           ⁢     1   ·     (     s   +       gm   ⁢           ⁢   2         2   ·   C     ⁢           ⁢   1       +     1     R   ⁢           ⁢     3   ·   C     ⁢           ⁢   2         )                         Zload   ⁡     (   s   )       =     R   ⁢           ⁢   2   ⁢     a   ·       R   ⁢           ⁢   1   ⁢   a         R   ⁢           ⁢   1   ⁢   a     +     R   ⁢           ⁢   2   ⁢   a         ·       s   +     1     R   ⁢           ⁢   1   ⁢     a   ·   C     ⁢           ⁢   3           s   +     1         (       R   ⁢           ⁢   1   ⁢   a     +     R   ⁢           ⁢   2   ⁢   a       )     ·   C     ⁢           ⁢   3                     
and the respective Bode diagrams are depicted in  FIG. 16   b.    
   For the circuit of  FIG. 12 , the low corner frequency is estimated by the following formula: 
   
     
       
         
           LCF 
           ≈ 
           
             
               1 
               
                 R 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 π 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 2 
               
             
             · 
             
               
                 1 
                 
                   
                     2 
                     · 
                     C 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
               . 
             
           
         
       
     
   
   For the circuits of  FIGS. 15 and 16   a  the LCF is: 
   
     
       
         
           LCF 
           ≈ 
           
             
               1 
               
                 R 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 3 
               
             
             · 
             
               
                 1 
                 
                   
                     2 
                     · 
                     C 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
               . 
             
           
         
       
     
   
   Even the pre-amplifiers of these two embodiments can be adapted to obviate the problems due to the thermal asperity. By connecting a resistor R 4 , as depicted in  FIGS. 17 to 20 , the resistance seen from capacitors C 2   a  and C 2   b  is reduced and, as a consequence, the low corner frequency is increased. 
   Other architectures of pre-amplifiers can be obtained by combining features of the embodiments discussed above. For example, the amplifiers depicted in  FIG. 8  (Aa, Ab), and the respective R-C input branches could also be connected to the amplifiers depicted in  FIGS. 18 to 20  for compensating the effects induced by the resistive heads.