Abstract:
The present invention discloses an FFT-based ADC calibration system able to solve the problems of capacitor mismatch and finite Op-Amp open loop gain, which result in that the radix of the gain of each stage is not exactly equal to 2. The present invention uses an FFT processor to calculate the real radix of each stage and uses a digital method to generate new digital outputs. As the present invention can compensate the finite gain of Op-Amp, the specification of Op-Amp is not so critical in designing ADC. Therefore, the low-gain Op-Amp can be used to reduce the power consumption of ADC. Further, the FFT-based calibration technology can considerably promote the performance of ADC.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a calibration technology for a pipeline ADC, particularly to an FFT-based ADC calibration system. 
         [0003]    2. Description of the Related Art 
         [0004]    Recently, many communication systems need ADC (Analog-to-Digital Converter) to bridge the analog signal and DSP (Digital Signal Processor), especially the high-resolution and high-sample rate ADC facilitating the fast development of communication systems, and the pipeline ADC is a frequently used architecture among them. 
         [0005]    The performance of the conventional ADC is affected by capacitor mismatch, finite Op-Amp (Operation Amplifier) open loop gain, and comparator offset. Therefore, calibration systems are used to achieve a high-resolution ADC, and the digital calibration system is a frequently-used one among them. The digital calibration system performs additional coding on the digital output. 
         [0006]    The present invention uses an FFT processor to calculate the errors of all the stages of the pipeline ADC and performs coding calibration in the digital output terminal to promote ADC performance. 
       SUMMARY OF THE INVENTION 
       [0007]    One objective of the present invention is to provide a calibration system for a pipeline ADC to overcome the abovementioned problems. 
         [0008]    To achieve the abovementioned objective, the present invention proposes an FFT-based ADC calibration system. In one embodiment, the FFT-based ADC calibration system comprises a pipeline ADC, an FFT processor, and a digital control system. 
         [0009]    More and more OFDM (Orthogonal Frequency Division Multiplexing) systems are used now, and the OFDM system itself contains an FFT processor. Therefore, the FFT processor of the OFDM system can be directly used in ADC calibration. 
         [0010]    The FFT-based ADC calibration system is a digital calibration technology and uses an FFT processor to perform a fast Fourier transformation on the output of ADC and calculate the errors of ADC. Then, the FFT-based ADC calibration system recodes the output of ADC, and the recoded digital data is the final digital output. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a flowchart of the operation of an FFT-based ADC calibration system according to one embodiment of the present invention; 
           [0012]      FIG. 2  is a block diagram schematically showing the architecture of an FFT-based pipeline ADC calibration system according to one embodiment of the present invention; 
           [0013]      FIG. 3  is a block diagram schematically showing a digital calibration circuit of an FFT-based ADC calibration system according to one embodiment of the present invention; and 
           [0014]      FIG. 4  is a block diagram schematically showing a multi-bit ADC. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    Refer to  FIG. 2  a diagram schematically showing the architecture of an FFT-based calibration system  200  for a pipeline ADC according to one embodiment of the present invention. The FFT-based calibration system  200  comprises a pipeline structure, an FFT processor  230  and a digital control circuit  240 . The pipeline structure further comprises a sample-and-hold circuit  210  and several stages  220  cascaded in sequence. In this embodiment, the pipeline ADC is exemplified with a 1.5 bit/stage architecture. 
         [0016]    Suppose V in,k  is the input of the kth stage and V out,k  is the output of the kth stage. For the 1.5 bit/stage architecture, 
         [0000]        V   out,k =2( V   in,k   +αV   ref /2)  (1) 
         [0000]    wherein α is −1, 0, or 1. When V in,k &gt;V ref /4, α=−1. When V ref /4&gt;V in,k &gt;−V ref /4, α=0. When −V ref /4&gt;V in,k , α=1. A charge redistribution method is usually used to achieve a gain of 2. Refer to  FIG. 4 , wherein one stage is exemplified with MDAC (Multiplying Digital-to-Analog Converter). The transfer function of MDAC is expressed by 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    wherein C s  is the sampling capacitance, C f  is the feedback capacitance, C p  is the input parasitic capacitance of Op-Amp (Operation Amplifier), and A vo  is the Op-Amp open loop gain. According to Equation (2), V out,k =2(V in,k +αV ref /2) if A vo , is infinite and C s =C f . Owing to process variation, the sampling capacitor may not match the feedback capacitor, and the Op-Amp open loop gain is unlikely to be infinite. Therefore, the radix of gain is not necessarily equal to 2. Considering capacitor mismatch and finite Op-Amp open loop gain, Equation (2) should be revised into 
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         [0000]    wherein ΔC s  and ΔC f  are process variation-induced errors of the sampling capacitor and the feedback capacitor. From Equation (2), it is known: if the capacitors mismatch and the Op-Amp open loop gain is finite, the radix of the gain is not equal to 2, and 
         [0000]        V   out,k =(2 +Δg   1 )( V   in,k   +αV   ref /2)  (4) 
         [0000]    wherein Δg 1  is the Op-Amp&#39;s error caused by capacitor mismatch and finite Op-Amp open loop gain. Comparing Equation (4) with Equation (1), it is known: Δg i (V in,k +αV ref /2) is the difference between the ideal radix and the real radix caused by capacitor mismatch and finite Op-Amp open loop gain. 
         [0017]    Suppose the stages of the pipeline ADC have been calibrated except the first stage, and suppose the input signal V in =A cos(ωt), V ref =A, and the error e(t)=Δg 1 (V in +αV ref /2). Below, the present invention performs a Fourier transformation on e(t) to find the coefficient of the third order harmonic. 
         [0018]    (1) When −V ref /4&gt;V in,k , α=1, and e(t)=αg 1 (A cos(ωt)+A/2), and the coefficients of the nth-order harmonic is expressed by 
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         [0019]    (2) When V ref /4&gt;V in,k &gt;−V ref /4, α=0, and e(t)=Δg 1 (A cos(ωt)), and the coefficients of the nth-order harmonic is expressed by 
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         [0020]    (3) When V in,k &gt;V ref /4, α=−1, and e(t)=Δg 1 (A cos(ωt)−A/2), and the coefficients of the nth-order harmonic is expressed by 
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                                               1 
                                             
                                             ) 
                                           
                                         
                                          
                                         
                                           ( 
                                           
                                             
                                               cos 
                                               
                                                 - 
                                                 1 
                                               
                                             
                                              
                                             
                                               ( 
                                               
                                                 1 
                                                 / 
                                                 4 
                                               
                                               ) 
                                             
                                           
                                           ) 
                                         
                                       
                                       
                                         
                                           ( 
                                           
                                             n 
                                             - 
                                             1 
                                           
                                           ) 
                                         
                                          
                                         ω 
                                       
                                     
                                   
                                 
                               
                               ] 
                             
                           
                           - 
                         
                       
                     
                   
                   
                     
                       
                           
                          
                         
                           
                             A 
                              
                             
                                 
                             
                              
                             Δ 
                              
                             
                                 
                             
                              
                             g 
                              
                             
                                 
                             
                              
                             1 
                              
                             
                                 
                             
                              
                             
                               sin 
                                
                               
                                 ( 
                                 
                                   
                                     cos 
                                     
                                       - 
                                       1 
                                     
                                   
                                    
                                   
                                     ( 
                                     
                                       1 
                                       / 
                                       4 
                                     
                                     ) 
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             2 
                              
                             n 
                              
                             
                                 
                             
                              
                             ω 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0000]    As the output is symmetric, it is sufficient to only concern the range π/ω&gt;t&gt;0. Via adding up Equations (5), (6) and (7) and dividing the sum with π/2ω, the coefficients of the nth-order harmonic is revised into 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         - 
                         A 
                       
                        
                       
                           
                       
                        
                       Δ 
                        
                       
                           
                       
                        
                       
                         g 
                         1 
                       
                     
                     
                       n 
                        
                       
                           
                       
                        
                       π 
                     
                   
                    
                   
                     ( 
                     
                       
                         sin 
                          
                         
                           ( 
                           
                             n 
                              
                             
                                 
                             
                              
                             
                               
                                 cos 
                                 
                                   - 
                                   1 
                                 
                               
                                
                               
                                 ( 
                                 
                                   
                                     - 
                                     1 
                                   
                                   / 
                                   4 
                                 
                                 ) 
                               
                             
                           
                           ) 
                         
                       
                       + 
                       
                         sin 
                          
                         
                           ( 
                           
                             n 
                              
                             
                                 
                             
                              
                             
                               
                                 cos 
                                 
                                   - 
                                   1 
                                 
                               
                                
                               
                                 ( 
                                 
                                   1 
                                   / 
                                   4 
                                 
                                 ) 
                               
                             
                           
                           ) 
                         
                       
                     
                     ) 
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Thus, the coefficient of third order harmonic is 
         [0000]      0.154×Δg 1 ×A  (9) 
         [0000]    In the 1.5 bit/stage pipeline ADC, the offset of the comparator has only a minor influence on the performance. Therefore, the offset of the comparator is neglected in the above deduction. 
         [0021]    Refer to  FIG. 1  a flowchart of the operation of an FFT-based pipeline ADC calibration system according to one embodiment of the present invention. The flowchart  100  contains nine steps: start (Step  110 ), signal test (Step  120 ), pipeline ADC (Step  130 ), FFT processor (Step  140 ), calculating physical errors (Step  150 ), determining whether all the succeeding stages have been calibrated (Step  160 ), finding out the uncalibrated stages (Step  170 ), calculating the physical digital output (Step  180 ), and outputting data (Step  190 ). 
         [0022]    In Step  120 , an input test signal is a sinusoidal signal with an amplitude of A and a frequency of 2πf. Generally, a sinusoidal wave with a lower frequency and an amplitude exactly equal to V ref  will be adopted as the test signal. Also, how many stages need calibrating are determined in this step. 
         [0023]    In Step  130 , the pipeline ADC receives the input sinusoidal wave and converts the analog sinusoidal signal into a digital signal. 
         [0024]    In Step  140 , the FFT processor receives the digital signal output by the pipeline ADC and performs a fast Fourier transformation on the digital signal to work out the third order harmonic. 
         [0025]    In Step  150 , the third order harmonic obtained in Step  140  is used to calculate the error Δg k  of the kth stage with Equation (9), and the error is stored in the register. 
         [0026]    In Step  160 , the system checks whether the error of the first stage has been obtained. If the error of the first stage has not been obtained yet, continue to calculate the error of the (k−1)th stage until the error of the first order is obtained. 
         [0027]    In Step  170 , if the error of the first stage has been obtained in Step  160 , the analog signal, which is to be converted into a digital signal, is input, and the digital output is calibrated. In Step  150 , the errors of all the stages have been worked out, and the real radix of each stage can also be worked out thereby. Then, the following equation can be used to calculate the final digital output. 
         [0000]    
       
         
           
             
               
                 
                   D 
                   = 
                   
                     
                       ∑ 
                       
                         i 
                         = 
                         1 
                       
                       N 
                     
                      
                     
                       
                         G 
                         e 
                         i 
                       
                        
                       
                         d 
                         i 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0000]    wherein D is the final digital output, N is the ordinal number of the stage in the pipeline ADC, G e   i  is the real radix of the ith stage, and d i  is the digital signal generated by the ith stage. 
         [0028]    Refer to  FIG. 3  a diagram schematically showing a digital calibration circuit  300 . The digital calibration circuit  300  includes an error calculation unit  310 , a register  320  and a multiplier  330 . The digital calibration circuit  300  performs digital calibration. The error calculation unit  310  calculates the errors according to Equation (9) and stores the errors in the register  320 . Then, the multiplier  330  realizes Equation (10) and outputs the data. 
         [0029]    From the above description, it is known the present invention has the following advantages: 
         [0030]    (1) The present invention uses an FFT processor to calibrate the pipeline ADC, whereby the pipeline ADC is less sensitive to process variation. 
         [0031]    (2) The present invention can also calibrate the Op-Amp open loop gain, whereby a low-gain Op-Amp can be used to reduce the power consumption of ADC. 
         [0032]    The embodiments described above are only to exemplify the present invention but not to limit the scope of the present invention. Any equivalent modification or variation according to the spirit of the present invention is to be also included within the scope of the present invention, which is based on the claims stated below.