Abstract:
A method is provided for programming a non-volatile memory having a plurality of word lines, the method comprising: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the applying of one of the first and second program voltages increases the pass voltage with a single increment.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority to Italian patent application No, 102015000020953 filed on Jun. 5, 2015, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    The present disclosure relates to a method and controller for programming a non-volatile memory. 
         [0004]    The disclosure particularly, but not exclusively, relates to a method and controller capable of controlling a slope of voltage driven to a selected word line of the non-volatile memory to be less steep. 
         [0005]    2. Description of the Related Art 
         [0006]    Among the various types of flash memory devices, NAND-type flash memory devices are increasingly used as a high capacity data storage media. Each cell of a flash memory is programmed to store information by trapping electrons in the floating gate of the cell. The programming operation is performed by driving a strong positive voltage on the control gate to force a current to flow from the channel through the floating gate to the control gate, a phenomenon known as the “Fowler Nordheim Tunnelling” effect. A control gate is connected to a word line of the flash memory, and a voltage is provided to the control gate through the word line. Each memory cell can store a single bit which is referred to as a single level memory cell (SLC) or alternatively, each cell can store multiple bits which is referred to as a multiple level memory cell (MLC). In both of the SLC and MLC, the information stored in each cell s defined by a corresponding threshold voltage of the memory cell. 
       SUMMARY 
       [0007]    Embodiments of the invention are directed to a method and a controller for programming a non-volatile memory, capable of sophisticatedly controlling the slope of programming pulses and avoiding a program disturb effect by using a novel and simple scheme, when different programming voltages are required. 
         [0008]    In an embodiment of the invention, a method is provided for programming a non-volatile memory having a plurality of word lines, the method comprising: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the applying of one of the first and second program voltages increases the pass voltage with a single increment. 
         [0009]    In an embodiment of the invention, a controller is provided for programming a non-volatile memory having a plurality of word lines, the controller comprising: a processor; and a DA converter operable under a control of the processor, and suitable for: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the DA converter increases the pass voltage with a single increment. 
         [0010]    The processor comprises: a microprocessor; and a dedicated logic block, wherein the DA converter is operable under a control of the dedicated logic block. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The characteristics and advantages of the disclosure will be apparent from the following description of embodiments thereof given by way of indicative and non-limiting examples with reference to the annexed drawings, in which: 
           [0012]      FIG. 1A  is a timing diagram of a programming operation employing a programming voltage of VPGM 1  according to an embodiment. 
           [0013]      FIG. 1 b    is a timing diagram of programming operation employing a programming voltage of VPGM 4  according to the embodiment. 
           [0014]      FIG. 1C  is a timing diagram showing the programming operations of  FIGS. 1A and 1B  together. 
           [0015]      FIG. 1D  is a timing diagram showing programming operations according to another embodiment. 
           [0016]      FIG. 2A  is a flow chart of an exemplary process of the programming operation. 
           [0017]      FIG. 2B  is a flow chart of another exemplary process of the programming operation. 
           [0018]      FIG. 3A  schematically shows an exemplary circuit block diagram illustrating a controller suitable to generate the programming voltage according to an embodiment. 
           [0019]      FIG. 3B  schematically shows another exemplary circuit block diagram illustrating a controller suitable to generate the programming voltage according to the embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. While the present invention is shown and described in connection with exemplary embodiments thereof, it aril be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention. The terms and words used in the specification and claims should not be construed according to their ordinary or dictionary meaning. In addition, detailed descriptions of constructions well known in the art may be omitted to avoid unnecessarily obscuring the gist of the present invention. 
         [0021]    It will be also understood that, although the terms “first”, “second”, “third”, and so on may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element described below could also be termed as a second or third element without departing from the spirit and scope of the present disclosure. 
         [0022]    It will be further understood that when an element is referred to as being “connected to”, or “coupled to” another element, it can be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. 
         [0023]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. 
         [0024]    It will be further understood that the terms “comprises”, “comprising”, “includes”, and “including” when used in this specification, specify the presence of the stated elements but do not preclude the presence or addition of one or more other elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0025]    Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0026]    In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process structures and/or processes have not been described in detail in order not to unnecessarily obscure the present disclosure. 
         [0027]    Hereinafter, the various embodiments of the present disclosure will be described in details with reference to attached drawings 
         [0028]    Referring now to  FIG. 1A  a timing diagram of a programming operation which employs a programming voltage VPGM 1  is provided, according to an embodiment of the present invention. 
         [0029]    In  FIG. 1A , a selected word line is a word line coupled to a control gate of a cell which undergoes a programming operation. An unselected word line is a word line not coupled to a control gate of a cell which undergoes a programming operation. The unselected word line may be coupled to cells of the same string or same block with the cell to be programmed. 
         [0030]    From a time point t 0 ′ to a time point t 1 ′, a pass voltage VPASS is applied to the selected word-line SEL.WL while the same VPASS is applied to the unselected word lines UNSEL.WL. At time point t 0 ′, the voltages of unselected word lines are synchronized with the voltage of selected word line SEL.WL, but the embodiment is not limited thereto. 
         [0031]    Then, at time point t 1 ′, the voltage driven to the selected word-line is gradually increased by a step value ΔV during a time step Δt. This step-wise increment is repeated until the voltage driven to the selected word line reaches a programming voltage VPGM 1  at time point t 2 ′. Then, the voltage applied to the selected word line is maintained as VPGM 1  for a specific period, e.g. from time point t 2 ′ to time point t 4 ′. From time point t 0 ′ to time point t 5 ′, the pass voltage VPASS may be driven to the unselected word lines UNSEL.WL, but the embodiment is not limited thereto. 
         [0032]    The duration from t 1 ′ to t 2 ′ may be defined as a rising time  40 , and the duration from t 2 ′ to t 4 ′ may be defined as a plateau time  41 . The timing of the programming or a program time can be controlled so that the sum of the rising time  40  and the plateau time  41  may be constant regardless of the programming voltage VPGM 1 . 
         [0033]    In  FIG. 1A , it is shown that during the rising time  40 , in each step increase of the voltage, the voltage rises to as much as a step value ΔV, then stays flat at the increased specific value for the remaining time of the time step Δt, and then transits to the next step. In other words, the slope of the voltage rise (or the rate of the voltage increase) is “0” for the remaining time of the time step Δt, in  FIG. 1A . However, the time step Δt can also be designed in a way so that there is not any substantial period during which the voltage slope is zero, during each time step Δt during the rising time  40 , because it is not necessary to introduce the flat status in each step. In other words, the step value ΔV and the time step Δt can be chosen so that the voltage may increase during the rising time  40  (period from t 1 ′ to t 2 ′) without having a severe fluctuation of its slope. Stated otherwise the voltage may be increased from an initial value of VPASS at time t 1 ′ to the program voltage value of VPGM 1  at time t 2 ′ with a less severe fluctuation of its slope, i.e. its rate of increase. 
         [0034]      FIG. 1B  is a timing diagram of a programming operation employing a programming voltage of VPGM 4  according to an embodiment. The programming voltage of VPGM 4  is greater than the programming voltage of VPGM 1  of  FIG. 1A . The programming voltage can differ in each pulse of the ISPP scheme. 
         [0035]    In  FIG. 1B , from t 0 ′ to t 1 ′, a pass voltage VPASS is applied to the selected word line SEL.WL while the same VPASS is applied to the unselected word lines UNSEL.WL. At t 0 ′, the voltages of unselected word lines are synchronized with the voltage of selected word line SEL. WL, but the embodiment is not limited thereto. 
         [0036]    Then, at t 1 ′, the voltage driven to the selected word line is gradually increased by a step value ΔV during a time step Δt. This step-wise increment is repeated until the voltage driven to the selected word line reaches a programming voltage VPGM 4  at t 3 ′. Then, the voltage applied to the selected word line is maintained as VPGM 4  for a specific period, e.g., from t 3 ′ to t 4 ′. From t 0 ′ to t 5 ′, the pass voltage VPASS is driven to the unselected word lines UNSEL.WL. 
         [0037]    In  FIG. 1B , the duration from t 1 ′ to t 3 ′ may be defined as a rising time  42 , and the duration from t 3 ′ to t 4 ′ may be defined as a plateau time  43 . The program time can be controlled so that the sum of the rising time  42  and the plateau time  43  may be constant regardless of the programming voltage VPGM. 
         [0038]      FIG. 1C  is a timing diagram showing the programming operations of  FIGS. 1A and 1B  together. 
         [0039]    As shown in  FIG. 1C , the slope of the driven voltage from the time point t 1 ′ to the time point t 2 ′ is regular regardless of the final values of the programming voltages VPGM 1  and VPGM 4 . The rising times  40  and  42  may vary depending on the programming voltage values VPGM 1  and VPGM 4 . For the programming voltage VPGM 1 , there are three steps during the rising time  40 , while there are six steps during the rising time  42  for the programming voltage VPGM 4 , as shown in  FIG. 1C . The plateau times  41  and  43  may also vary depending on the programming voltage values VPGM 1  and VPGM 4 . Even though the rising times and/or the plateau times may vary, the sum of the rising time and the plateau time or the program time may be kept constant. 
         [0040]    In the example of  FIG. 1C , it is shown that there are three steps during the period from t 1 ′ to t 2 ′, during the rising time  40 . However, the number of steps in  FIG. 1C  is just an example, and the number of the steps during the rising time  40  may vary based, for example, on the time step Δt, the step voltage ΔV, the pass voltage VPASS, and the programming voltage VPGM 1 . Thus, the embodiment is not limited to the number of steps during the rising time. 
         [0041]    The step value ΔV and the time step Δt are independent of the programming voltages VPGM 1  and VPGM 4 . That is to say, the step value ΔV and the time step Δt may be predetermined, and used for the different programming values VPGM 1  and VPGM 4 . 
         [0042]    The step value ΔV and the time step Δt may be constant during the rising times  40  and/or  42 , but the embodiment is not limited thereto. 
         [0043]    The plateau times  41  and  43  are greater than a predetermined minimum value in order to guarantee correct programming with the target programming voltages VPGM 1  and VPGM 4 . 
         [0044]    By using the programming method of the present invention the control of the slope of the voltage increase during the rising time may be simplified. Also, it may be possible to control the slope not to exceed a predetermined value. 
         [0045]    The embodiment has been explained with the programming voltages VPGM 1  and VPGM 4 , however, it is noted that the invention is not limited to any specific programming voltages. For example, more than two programming voltages of different programming voltage values may be used in the current scheme. 
         [0046]      FIG. 1D  is a timing diagram showing the programming operations according to another embodiment. 
         [0047]    The timing diagram of  FIG. 1D  is identical to that of  FIG. 1C  except that the plateau time  41  of programming voltage VPGM 1  is identical to the plateau time  43  of programming voltage VPGM 4  and thus the sums of the rising time and the plateau time or the program time for the programming voltages of VPGM 1  and VPGM 4  are different from each other. 
         [0048]    Therefore, the driven voltage starts to drop at t 4 ′ when the programming voltage of VPGM 1  is applied, while the driven voltage starts to drop at t 6 ′ when the programming voltage of VPGM 4  is applied. The timing when the driven voltage drops from the target programming voltages VPGM 1  and VPGM 4  may vary depending on the level of the target programming voltages VPGM 1  and VPGM 4 . 
         [0049]      FIG. 2A  is a flow chart of an exemplary process of the programming operation. The process of  FIG. 2A  can be implemented by a microcontroller  100  and a DA converter (DAC)  101  as shown in  FIG. 3A , or can also be implemented by the microcontroller  100 , a dedicated logic  102 , and the DA converter (DAC)  101  as shown in  FIG. 3B . 
         [0050]    Once the programming voltage VPGM, the time step Δt, and the step value ΔV are determined, the method starts at step  50 . At step  51 , it is checked whether or not the voltage selWL for the selected word line SEL.WL has reached the programming voltage of VPGM. The voltage selWL for the selected word line SEL.WL is not a voltage directly driven to the selected word line SEL.WL, but is a digital value stored in a memory of the microprocessor  100  or in a register or the dedicated logic  102 . The value selWL may be used as an input to the DAC converter  101  whose output voltage value (analogue value) is provided to the selected word line SEL.WL. 
         [0051]    If the voltage selWL of the selected word line SEL.WL has not reached the programming voltage of VPGM, then the process transits to step  52 . At step  52 , the next voltage selWL for the selected word line SEL.WL is set at a value derived by the sum of the current voltage selWL for the selected word line SEL.WL and the step value ΔV. After setting the next voltage selWL for the selected word line SEL.WL, the process waits for the time step Δt to elapse at step  53 . After the time step Δt elapses, the process transits to step  51  again, and checks whether the voltage selWL for the selected word line SEL.WL has reached the programming voltage of VPGM. The loop from step  51  to step  53  is repeated as many times as may be needed until the voltage for the selected word line selWL reaches the programming voltage VPGM. 
         [0052]    When the voltage for the selected word line selWL reaches the programming voltage of VPGM, the process transits to step  54 . At step  54 , the process waits for the plateau time elapse. The plateau time may be defined as a constant time. Once the voltage for the selected word line selWL is set at the programming voltage value of VPGM it remains constant for the preset plateau time at step  54 , and when the plateau time elapses, then the process terminates at step  55 . 
         [0053]    In particular, it should be remarked that the waveform of  FIG. 1D  shows the process of  FIG. 2A . More particularly, according to this process shown in  FIGS. 1D and 2A , the loop of steps  51 ,  52  and  53  is performed for each of the rising time  42  for the programming voltage of VPGM 4  and the rising time  40  for VPGM 1 ; afterwards, then the process waits for each of the plateau time  43  for the programming voltage of VPGM 4  and the plateau time  41  for the programming voltage of VPGM 1  during the step  54 . The sums of the rising time and the plateau time or the program time for the programming voltages of VPGM 1  and VPGM 4  are different from each other. 
         [0054]    In this way, the process of  FIG. 2A  always provides for fixed plateaus  41  and  43  for the programming voltages of VPGM 1  and VPGM 4 , respectively, and hence a variable programming time; in particular, the programming time would be longer for higher programming voltage of VPGM. 
         [0055]      FIG. 2B  is a flow chart showing another exemplary process of the programming operation. The process of  FIG. 2B  may be implemented by the microcontroller  100  and the DAC  101  as shown in  FIG. 3A , or can also be implemented by the microcontroller  100 , the dedicated logic  102 , and the DAC  101  as shown in  FIG. 3B . 
         [0056]    Once the programming voltage VPGM, the time step Δt, and the step value ΔV are determined, the method starts at step  56 . At step  57 , it is checked whether or not the voltage selWL for the selected word line SEL.WL has reached the value of the programming voltage VPGM. The voltage selWL for the selected word line SEL.WL is not a voltage directly driven to the selected word line SEL.WL, but is a digital value stored in a memory of the microprocessor  100  or in a register or the dedicated logic  102 . The value selWL can be used as an input to the DAC converter  101  whose output voltage value (analogue value) is provided to the selected word line SEL.WL. 
         [0057]    If the voltage selWL of the selected word line SEL.WL has not reached the programming voltage of VPGM, then the process transits to step  58 . At the step  58 , the next voltage selWL for the selected word line SEL.WL value is set at a value derived by the sum of the current voltage selWL for the selected word line SEL.WL and the step value ΔV. After setting the next voltage selWL for the selected word line SEL.WL, the process waits for the time step Δt to elapse at step  59 . 
         [0058]    After the time step Δt elapses, the process transits to step  60 , and determines whether a program time is over or not. The program time may be defined as a total constant programming time, e.g. the sum of the rising time and the plateau time. 
         [0059]    If the program time is not over, the process transits to step  57  and determines whether the voltage selWL for the selected word line SEL.WL has reached the programming voltage of VPGM or not. So, until the voltage selWL for the selected word line SEL.WL reaches the programming voltage of VPGM, the process of the loops formed by the steps  57 ,  58 ,  59  and  60  is repeated. 
         [0060]    Once the voltage selWL for the selected word line SEL.WL reaches the programming voltage of VPGM, the process transits from step  57  to step  59  without increasing the voltage selWL for the selected word line SEL.WL. 
         [0061]    Then, unless the PGM time is over, the process transits from step  60  to step  57 . So, the process of the loops formed by the steps  57 ,  59 , and  60 , is repeated and an input to the DAC  101  is set as the programming voltage of VPGM constantly. When the program time expires, the loop of steps  57 ,  59 , and  60  terminates, and the process transits to step  61 . 
         [0062]    In particular, it should be remarked that the waveform of  FIG. 1C  shows the process of  FIG. 2B . More particularly, according to this process, the program time (i.e., the sum of the rising time and the plateau time) is fixed. 
         [0063]    As already indicated, the process of  FIGS. 1C and 2B , waits until the desired programming voltage VPGM is reached and/or the plateau time has consumed the remaining time of the total program time. The plateau time may be different for different programming voltages VPGMs. 
         [0064]    In particular, as shown in  FIGS. 1C and 2B , according to this process, the loop of steps  57 ,  58 ,  59  and  60  is repeated (answer NO to the questions of step  57  and  60 ) during the rising time  42  for the programming voltage of VPGM 4 . Similarly, the loop of steps  57 ,  59  and  60  is repeated (answer YES to the question of step  57  and answer NO to the question of step  60 ) during the plateau time  43  for the programming voltage of VPGM 4  till the end of the program time. In this sense, the process of  FIG. 2B  also comprises a counter for the program time, in parallel to the shown flow chart, ending with the answer YES to the question of step  60 . 
         [0065]      FIG. 3A  schematically shows an exemplary circuit block diagram illustrating a controller suitable to generate the programming voltage VPGM according to an embodiment of the invention. 
         [0066]    The controller comprises microcontroller  100  and DAC  101 . The microcontroller  100  may output a clock signal and a numerical value to the DAC  101 . The numerical value may be a digital value consisting of several bits. The output value of the DAC  101 , i.e., an analog value, is determined according to the numerical value inputted to the DAC  101 . The clock signal can synchronize the operation of the DAC  101 . In other words, the DAC  101  may read the numerical value at a rising edge or a falling edge of the clock signal or when the clock signal has a logic low or high value, depending on the specific implementation of the DAC  101 . 
         [0067]    The clock signal provided to the DAC  101  may be configured so that the numerical value is read by DAC  101  at every time step Δt. 
         [0068]    The microcontroller  100  carries out the process illustrated in  FIGS. 2A and 2B  by controlling the output to the DAC  101 , e.g., the numerical value and the clock signal. The numerical value provided to DAC  101  corresponds to the voltage selWL for the selected word line SEL.WL of  FIGS. 2A and 2B . 
         [0069]    The microcontroller  100  may store the voltage selWL for the selected word line SEL.WL in its own register or cache memory, and update them as shown in steps  52  and  58  of  FIGS. 2A and 2B . Alternatively, the microcontroller  100  may store the voltage selWL for the selected word line SEL.WL in a memory located out of the microprocessor and it may update them as shown in steps  52  and  58  of  FIGS. 2A and 2B . 
         [0070]      FIG. 3B  schematically shows another exemplary circuit block diagram illustrating a controller suitable to generate the programming voltage according to an embodiment of the invention. 
         [0071]    The controller comprises the microcontroller  100 , the dedicated logic block  102  and the DA converter or DAC  101 . The dedicated logic block  102  may output a clock signal and a numerical value to the DAC  101 . The numerical value is a digital value consisting of several bits. The output value of the DAC  101 , i.e. an analog value, is determined according to the numerical value inputted to the DAC  101 . The clock signal can synchronize the operation of the DAC  101 . In other words, the DAC  101  may read the numerical value at a rising edge or a falling edge of the clock signal or when the clock signal has a logic low or high value, depending on the specific implementation of the DAC  101 . 
         [0072]    The clock signal provided to the DAC  101  may be configured so that the numerical value is read by DAC  101  at every time step Δt. 
         [0073]    The microcontroller  100  may provide a command and data to the dedicated logic block  102 . 
         [0074]    The dedicated logic block  102  carries out the process illustrated in  FIGS. 2A and 2B  by controlling the output to the DAC  101 , e.g., the numerical value and the clock signal. The numerical value provided to DAC  101  corresponds to the voltage selWL for the selected word line SEL.WL of  FIGS. 2A and 2B . 
         [0075]    The dedicated logic block  102  may store the voltage selWL for the selected word line SEL.WL in its own register, and it may update them as shown in steps  52  and  58  of  FIGS. 2A and 2B . Alternatively, the dedicated logic block  102  may store the voltage selWL for the selected word line SEL.WL in a memory located out of the dedicated logic block  102 , and it may update them as shown in steps  52  and  58  of  FIGS. 2A and 2B . 
         [0076]    The dedicated logic block  102  can be made by a finite state machine (FSM) that may be initialized with start value, stop value, the program time, step value ΔV, and time step Δt by the microcontroller  100  through the command and data signals. The start value can be the pass voltage VPASS. The stop value, or final value may be the programming value of VPGM 1  or VPGM 4 . The program time may be the sum of the rising time  40  and the plateau time  41  or the sum of the rising time  42  and the plateau time  43  as defined in  FIGS. 1A and 1B . 
         [0077]    The dedicated logic block  102  may send feedback to the microcontroller  100 , for example, when the programming operation with the inputted program voltage is terminated. That is to say, the dedicated logic block  102  may control the DAC  101  asynchronously with the microcontroller  100 . 
         [0078]    The microcontroller  100  may initialize, through the command and data signals, the dedicated logic block  102  for a next programming operation before the current programming operation is terminated. The microcontroller  100  may send a start instruction to the dedicated logic block  102  through the command signal. 
         [0079]    With the aforementioned method for programming a cell of a non-volatile memory, control for the slope of increase of the voltage driven to a selected word line of the non-volatile memory can be facilitated. Moreover, the slope of increase of the voltage can be controlled to be less steep so that a program disturbance may be avoided. 
         [0080]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and/or scope of the invention. Accordingly, the invention is not limited except as by the appended claims.