Abstract:
A dynamic MOS-circuit comprising a bootstrap capacitor decoupled by an output transistor and wherein the bootstrap capacitor is discharged via a MOS-FET. The MOS-FET is connected as a constant current source. With the invention, a control voltage at an output MOS-FET is nearly double an operating voltage of the circuit.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a dynamic MOS circuit comprised of a series connection of a first control MOS-FET, a discharge MOS-FET whose drain input is connected to a bootstrap capacitor, and a first switching MOS-FET. The circuit further comprises a second series connection of a second control MOS-FET and a second switching transistor activatable via the discharge MOS-FET. 
     An important feature of a MOS circuit, as is known, is its dynamic behavior. Related to this is the dependency of the switching speed upon the load capacitances, since with an increasing load, the switching speed decreases. In addition, the height of the output level is to be noted which should lie as close as possible to the operating voltage. From Electronics, June 30, 1981, Page 128, incorporated herein by reference, a dynamic MOS-circuit is known which switches or connects high load capacitances and exhibits an output voltage which corresponds approximately to the operating voltage. This driver module consists of an input inverter and two switching stages with a bootstrap capacitor decoupled from the input of the output transistor. In the case of a low-value input signal, the capacitor is charged so that a transistor, activated by the input signal, reduces a flowing-off of the charge. The voltage at the capacitor here lies below the operating voltage. If the input signal increases, the output transistor is activated, in dependence on the capacitor voltage, via the above-mentioned discharge transistor. It is disadvantageous here that the control voltage generated in this fashion has a relatively low maximum value. Moreover, the edge steepness of the output signal is dependent upon the edge steepness of the input signal. A shallow rise is automatically transmitted from the input to the output. However, signal edges which are as steep as possible are desired. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the invention is to disclose a circuit of the initially cited type with which output signals of high edge steepness and high levels are generated. 
     This object is achieved by virtue of the fact that the discharge MOS-FET is connected as a constant current source. 
     In this manner, the discharge operation of the boot-strap capacitor becomes independent of the progression of the input signal. In addition, the invention has the advantage that a control voltage for the output MOS-FET is generated which approximately corresponds to double the operating voltage. In addition, the circuit expense is reduced, since no input inverter is required. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 and 2 respectively show a MOS circuit; and 
     FIG. 3 shows a further development of the circuit according to FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The single-channel MOS-driver circuit of FIG. 1 is comprised of a first series connection of a first control MOS-FET 2 of the enhancement type, a load MOS-FET 1 as the discharge MOS-FET and connected as a constant source, and a first switching MOS-FET 4 of the depletion type, respectively. In addition, it exhibits a second series connection of a second control MOS-FET 5 and a second switching MOS-FET 3 of the enhancement type. The control input of the second switching MOS-FET 3 is connected to a first node 40 in the control path between the first control MOS-FET 2 and the load MOS-FET 1. A bootstrap capacitor 10 connects a second node 50 with a third node 60 which represents the output of the circuit. The node 50 is disposed in the controlled path between the load MOS-FET 1 and the first switching MOS-FET 4. 
     In the case of an input signal E which is high, the two control MOS-FETs 2 and 5 are conductive and the first and the third node 40, 60 lie at a reference potential in the proximity of V ss . Via the first switching MOS-FET 4, likewise activated by the input signal E, the bootstrap capacitor 10, and hence the second node 50, is charged to the value of an operating voltage V DD . The difference in relation to the operating voltage V DD  is apparent from the voltage drops at the second control MOS-FET 5 and at the first switching MOS-FET 4. 
     If the input signal E changes to the reference potential V ss , the two control MOS-FETs 2 and 5 block. The voltage at the first node 40 rises to the value of the voltage at the second node 50. The second switching MOS-FET 3 is thus opened. It thus causes the rise of the third node 60 to the operating voltage V DD . Since the first switching MOS-FET 4 blocks, the control voltage of the second switching MOS-FET 3 (output MOS-FET) at the first node 40 is composed of the operating voltage V DD  and the voltage dropping at the bootstrap capacitor 10. The value of the summed-up voltage more closely approximates the value of double the operating voltage V DD  the smaller the schematically indicated parasitic capacitances are at the first and second nodes 40 and 50 in relation to the capacitance of the bootstrap capacitor 10. 
     Through a capacitive coupling (capacitor 12) between the input of the circuit and the second node 50, an edge delay, desired in some instances, can be adjusted. 
     FIG. 2 shows an additional single channel MOS-driver circuit comprising a push-pull output stage (MOS-FETs 6 and 7 of the enhancement type). In contrast to the circuit in FIG. 1, the control input of the first switching MOS-FET 4 is subjected to the reference potential V ss . Like the circuit reproduced in FIG. 3, it is particularly suited for the connection of higher capacitive loads at the output which are represented as capacitor 11. The control voltage of the MOS-FET 6 is tapped off at the first node 40. Thus, the third node 60 is decoupled from the capacitive load 11. The voltage progression of the output signal A at the third node 60 thus directly follows the voltage progression of the first node 40. 
     In FIG. 3, a driver stage consisting of two additional MOS-FETs 8 and 9 of the enhancement type is connected before the push-pull output stage. The controlled path of the additional MOS-FETs 8 and 9 connected in series, connects the second node 50 with the reference potential V ss . In this manner, the first node 40 is further unloaded. The activation of the MOS-FET 6 proceeds via the common connection point of the MOS-FETs 8 and 9. 
     In a further advantageous sample embodiment, the first switching MOS-FET 4 is of the enhancement type. Its control input, in this case, is connected to the operating voltage V DD  (not shown in FIG. 3). 
     Although various minor changes and modifications might be suggested by those skilled in the art, it will be understood that we wish to include within the claims of the patent warranted hereon all such changes and modifications as reasonably come without our contribution to the art.