Abstract:
To reduce gate-drive losses caused by high switching frequency operation, embodiments herein include a novel resonant gate driver circuit for driving switches. This gate drive circuit can include a simple two-half-bridge structure. A coupling inductor of the resonant gate driver circuit can provide energy circulation between gates of high and low side switches and also works as a voltage-boost transformer. According to one configuration, the resonant gate driver circuit can be extended to drive two MOSFETs with a common ground. Both theoretical and simulation results for the new resonant gate driver circuit illustrate increased efficiency via lower switching losses.

Description:
BACKGROUND 
     A voltage regulator module (e.g., a VRM) can be used to regulate a DC voltage supplied to a load, such as a microprocessor. A VRM can include a power converter, such as a DC-DC converter, and may include other components such as a controller for controlling operation of the power converter. 
     An example of a DC-DC converter is a synchronous buck converter, which has minimal components, and therefore is widely used in VRM applications. In an example application, the input voltage to the buck converter is typically 12V DC . An output voltage produced by the VRM may be 5.0V DC , 3.3 V DC , or lower. 
     Multiphase interleaved VRM topologies include two or more power converters operated in parallel with each other to convert power and apply it to a corresponding load. In each of the power converters (or each power converter phase), the filter inductor can be smaller than that of a single phase power converter in order to achieve a faster dynamic response. The large output voltage ripple in each phase due to the small inductance can be cancelled by the ripple of other phases. Use of more phases in parallel reduces the ripple voltage. Implementation of a multiphase voltage converter topology (as compared to a single voltage converter phase topology) can therefore enhance the output current capability of a power supply system. 
     A typical configuration of a VRM such as a so-called synchronous buck converter includes an inductor, a high side switch, and a low side switch. A controller associated with the buck converter repeatedly pulses the high side switch ON to convey power from a power source through the inductor to a dynamic load. The controller repeatedly pulses the low side switch ON to provide a low impedance path from a node of the inductor to ground in order to control an output of the buck converter. Thus, the energy stored in the inductor increases during a time when the high side switch is ON and decreases during a time when the low side switch is ON. During switching operation, the inductor transfers energy from the input to the output of the converter. 
     SUMMARY 
     Conventional voltage converter circuits as discussed above suffer from a number of deficiencies. For example, conventional synchronous buck converters typically dissipate a portion of energy received from a respective power source in lieu of conveying all of the energy received from a respective power source to a corresponding load. This wasted energy precipitates out of the buck converter circuit as unwanted heat, which (if too high) can increase the likelihood of damage to the buck converter or other nearby electronic components. These losses (e.g., dissipation of unwanted heat) increase an amount of power that must be provided to merely operate buck converter. In certain cases, inefficiencies in the buck converter can require that the power supply be oversized to account for losses in the buck converter and increases the cost of energy. 
     Switching frequencies associated with switching circuits such as those implemented in power converters are being pushed into the Mega-Hertz range to provide small component size and fast transient response. However, an issue related to high frequency applications is the significant gate driving losses, especially in high-current switching applications requiring larger switch die sizes such as those found in MOSFET devices. At higher switching frequencies, the increased gate-drive losses can be so large as to offset the advantages gained by the lower conduction losses associated with large die sized MOSFETs used for switching. 
     For a conventional gate drive circuit, gate drive losses include the capacitive power losses Pcap related to a main power MOSFET (M) gate charge, the switching losses Psw_sm, and driving losses Pdr_sm of a small driving MOSFETs (M 1  &amp; M 2 ). Such losses can be quantified as follows:
 
 P   CAP   =Qg×Vg×Fsw  
 
 Psw   —   sm= 2 ×Coss   —   sm×Vg×Fsw  
 
 Pdr   —   sm= 2 ×Qg   —   sm×Vdr×Fsw  
 
     Where, Qg is the total charge of the main power MOSFET when the gate is charged to voltage level Vg, and Fsw is the switching frequency. Coss_sm is the equivalent output capacitance, and Qg_sm is the total charge when the gate is charged to voltage level Vdr of a respective driving MOSFET that drives the gate resistor of the switching MOSFET. 
     In order to reduce the gate driving losses, one or more of the three power losses mentioned above should be reduced or eliminated. 
     Conventional resonant gate driver methods present an alternative to the conventional gate driver to reduce such losses as mentioned above. In the past, many conventional resonant gate drive techniques have been developed to reduce these driving losses. However, such conventional drive circuits are only suitable for use with a single switch. For example, according to conventional techniques, to drive both a top switch and bottom switch (e.g., a high side switch and low side switch) in a circuit such as a synchronous buck converter, two independent sets of drive circuits and corresponding two different sets of magnetic components are needed. The size of such conventional resonant gate drive circuits can be relatively large and thus prohibitive in certain applications. 
     Techniques discussed herein deviate with respect to conventional applications such as those discussed above as well as other techniques known in the prior art. For example, certain embodiments herein are directed to improving the efficiency of switching power supply circuits. For example, to reduce gate driving losses caused by high frequency switching operation, embodiments herein include a novel switch driver circuit. 
     More specifically, a switch driver circuit according to embodiments herein can include a first driver circuit to control switching of a first switch device, a second driver circuit to control switching of a second switch device, and an intermediary circuit (e.g., bridge circuit) between the first driver circuit and the second driver circuit. The intermediary circuit can be configured to transfer gate energy between the first switch driver circuit and the second switch driver circuit. Assume that the energy or charge is initially used to activate the first switch device. The intermediary circuit initiates a transfer of the energy or charge to the second switch device. Transferring the gate energy causes activation of the second switch and deactivation of the first switch device. In a following cycle, the intermediary circuit supports a transfer of the energy or charge back to the first switch driver circuit, resulting in deactivation of the second switch device and activation of the first switch device. Reuse of the switch activation energy between switches reduces overall losses as the switches are activated and deactivated over time. 
     In addition to the apparatus (e.g., bridge circuitry) as discussed above, embodiments herein include a method of controlling switching of a first switch device and controlling switching of a second switch device. Such a process can include activating the first switch device by applying energy to a respective gate of the first switch device and, thereafter, activating the second switch by initiating a transfer of the applied energy from the respective gate of the first switch device to a respective gate of the second switch device. 
     In further embodiments, the bridge circuit or intermediary circuit enables a transfer of the switch activation energy from the respective gate of a first switch device to a respective gate of a second switch device. The transfer of the switch activation energy from the respective gate of the first switch device to the second switch device results in deactivation (e.g., turn OFF) of the first switch device as mentioned above as well as activation (e.g., turn ON) of the second switch device. Transfer of the switch activation energy from the respective gate of the second switch device to the first switch device results in deactivation (e.g., turn OFF) of the second switch device as well as activation (e.g., turn ON) of the first switch device, and so on. 
     In yet more specific embodiments, the novel gate drive circuit as described herein can include a simple two-half-bridge structure. An energy storage device such as an inductor and/or capacitor couples the first drive circuit and the second drive circuit and provides a bridge for energy re-circulation between gates of high and low side switches. 
     The bridge can potentially operate as a voltage-boost transformer. 
     According to further configurations, the gate driver circuit as described herein can be extended to drive two field effect transistor devices (e.g., MOSFETs) having a common ground. 
     Both theoretical and simulation results indicate that the gate driver circuit as described herein provides benefits over conventional methods. For example, the novel gate driver circuit as described herein increases efficiency via lower switching losses. In other words, switch activation energy is reused to reduce power losses. Reducing losses via reuse translates into lower dissipated heat. Dissipation of less heat relaxes the need for a heat dissipation mechanism (which may be expensive and cumbersome to implement) in the corresponding switching circuit. In addition to reduced heat, the driver circuit as described herein can be implemented in a smaller form factor than conventional circuits. 
     As discussed above, techniques herein are well suited for use in switching power supply circuitry. However, it should be noted that embodiments herein are not limited to use in such applications and that the techniques discussed herein are well suited for other applications as well. 
     Note also that each of the different features, techniques, configurations, etc. discussed herein can be executed independently or in combination with any or all other features also described herein. Accordingly, the present invention can be embodied, viewed, and claimed in many different ways. 
     This summary section does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty over conventional techniques. For additional details and/or possible perspectives (permutations) of the invention, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments herein, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, with emphasis instead being placed upon illustrating the embodiments, principles and concepts. 
         FIG. 1  is an example diagram of a switch driver circuit in the context of a switching power supply according to embodiments herein. 
         FIG. 2  is an example diagram illustrating a switch driver circuit including a bridge circuit according to embodiments herein. 
         FIG. 3  is an example diagram illustrating timing information associated with operations of a switch driver circuit according to embodiments herein. 
         FIG. 4  is a flowchart illustrating an example of a method for implementing reuse of switch activation energy or charge according to embodiments herein. 
         FIGS. 5A ,  5 B,  5 C, and  5 D are example diagrams of different switch driver circuits and corresponding bridge circuits according to embodiments herein. 
         FIG. 6  is an example diagram illustrating timing information associated with operations of a switch driver circuit according to embodiments herein. 
         FIG. 7  is an example diagram of a switch driver circuit according to embodiments herein. 
         FIG. 8  is an example diagram illustrating a percentage of savings in driving losses of a switch driver circuit according to embodiments herein compared to a conventional switch driver circuit. 
         FIG. 9  is an example diagram of simulation results according to embodiments herein. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments herein include a bridge circuit to reduce gate driving losses caused by high frequency switching operation. For example, a switch control circuit can include a bridge circuit to transfer switch activation energy (e.g., charge, current, energy, voltage, etc.) between a first drive circuit and a second drive circuit. The bridge circuit reduces losses based on reuse of the switch activation energy. In other words, switch activation energy can be used to activate a first switch device for a first duration while a second switch device is deactivated. Via the bridge circuit, the switch activation energy can be transferred from the first switch device to the second switch device to deactivate the first switch device and activate the second switch device. This process can be repeated to turn the first and second switch device ON and OFF over time. 
       FIG. 1  is a diagram illustrating an example switch driver circuit  150  in the context of a switching power supply circuit  100  according to embodiments herein. Although the switch driver circuit  150  is shown in the context of a switching power supply circuit  100  (e.g., a DC-DC power converter), note that the switch driver circuit  150  and/or corresponding bridge circuit  125  can be used in other suitable applications in which it is useful to transfer, relay, etc. switch activation energy amongst multiple switch devices that turn on at different times. 
     As shown, switch driver circuit  150  includes switch element  140 - 1  (e.g., a high side switch device) and switch element  140 - 2  (e.g., a low side switch device). Switch driver circuit  120 - 1  controls operation of switch element  140 - 1  while switch driver circuit  120 - 2  controls operation of switch element  140 - 2 . Thus, one embodiment herein includes switch driver circuit  120 - 1  configured to control an ON/OFF state of switch device  140 - 1  and second switch driver circuit  120 - 2  configured to control an ON/OFF state of switch device  140 - 2 . 
     In the context of the present example, the switch driver circuits  120  (e.g., switch driver circuit  120 - 1  and switch driver circuit  120 - 2 ) operate in such a way that both switch elements  140  are not fully activated at the same time. That is, when the switch element  140 - 1  is activated, switch element  140 - 2  is deactivated. When the switch element  140 - 2  is activated, switch element  140 - 1  is deactivated. 
     General operation of switch driver circuit  150  includes providing input control signals from a source such as controller  110  to switch driver circuit  120 - 1  and switch driver circuit  120 - 2 . 
     As mentioned above, the switch driver circuits  120  apply switch activation energy (e.g., charge) to the switch elements  140  to turn them to an ON state (e.g., conductive state). Bridge circuit  125  supports reuse of switch activation energy to activate the switches. 
     For example, switch driver circuit  120 - 1  initiates activation of switch element  140 - 1  by driving switch element  140 - 1  with switch activation energy (e.g., gate current to charge a corresponding gate of a field effect transistor). Switch driver circuit  120 - 1  eventually deactivates the switch element  140 - 1  by removing the switch activation energy. Bridge circuit  125  transfers the switch activation energy (previously used to activate switch element  140 - 1 ) from switch driver circuit  120 - 1  and respective switch element  140 - 1  to switch driver circuit  120 - 2  and switch element  140 - 2 . Application of switch activation energy or charge to a respective gate of switch element  140 - 2  via switch driver circuit  120 - 2  causes switch element  140 - 2  to turn ON. 
     Reuse of switch activation energy in this way to activate different switch devices (e.g., switch elements  140 ) over time reduces an amount of power losses associated with power supply circuit  100 . 
     During operation, power supply circuit  100  supports conversion of a DC voltage to another DC voltage. For example, as shown, power supply system  100  includes a voltage source  130  (e.g., +12 VDC), a controller  110 , drive circuit DR 1  and drive circuit DR 2 , high side switch device  142 , low side switch device  146 , element  144  (e.g., an energy storage device such as an inductor, filter, etc.), and dynamic load  118 . 
     A combination of the components shown in power supply system  100  (e.g., a single phase synchronous buck converter) comprises a switching power supply system that produces a substantially constant voltage  180  for driving dynamic load  118 . 
     Controller circuit  110  originates control signals (e.g., logic signals) to initiate opening and closing of switch elements  140  at appropriate times such that voltage  180  is maintained within a specified range such as 1.5+/−0.05 VDC. 
     For example, in one embodiment, controller circuit  110  utilizes feedback signal (e.g., the voltage provided to dynamic load  118 ) on which to base opening and closing of a respective high side switch device (e.g., switch element  140 - 1 ) and respective low side switch device (e.g., switch element  140 - 2 ). When feedback signal  185  is below the specified range or a respective chosen threshold value, controller  110  initiates activation of switch element  140 - 1  and deactivation of switch element  140 - 2 . When feedback signal  185  indicates that the voltage  180  is above the specified range or greater than a respective threshold value, controller  110  initiates deactivation of switch element  140 - 1  and activation of switch element  140 - 2 . Thus, controller  110  can be configured to control the transfer of the switch activation energy between multiple switch devices  140  by circulating at least a portion of electrical charge between a respective gate of switch device  140 - 1  and a respective gate of switch device  140 - 2 . 
     Of course, some of the energy used to activate switch elements  140  can be lost as heat during a respective transfer due to resistance associated with the switch driver circuit  150  and/or bridge circuit  125 . However, bridge circuit  125  can enable reuse of a majority of switch energy used to activate the switches from one cycle to the next. The switch driver circuit  120  and/or bridge circuit  125  can be configured to replenish any lost charge so that switch element  140  can be appropriately turned on and off. 
       FIG. 2  is an example diagram of switch driver circuit  150  according to embodiments herein. As shown, switch driver circuit includes switch element  140 - 1  (also labeled M H ), switch element  140 - 2  (also labeled M L ), switch M 1 , switch M 2 , switch M 3 , switch M 4 , and bridge circuit  125 . Controller  110  drives each of switches M 1 , M 2 , M 3 , and M 4  to control activation and deactivation of switch elements  140 . As previously discussed, bridge circuit  125  enables reuse of gate activation energy to reduce switching losses. 
     In the context of the present example, bridge circuit  125  in  FIG. 2  includes two half-bridge circuits (e.g., inductor Lr 1  and inductor Lr 2 ). Each half of such a bridge circuit  125  couples to a corresponding switch element  140 . Thus, bridge circuit  125  couples a respective gate of switch device  140 - 1  to a respective gate of switch device  140 - 2  enabling the transfer of the switch activation energy (e.g., charge or other mechanism in which to activate switches) between switch devices  140 . In this example embodiment shown, bridge circuit  125  also includes four capacitors (C 1 , C 2 , C 3 , and C 4 ). 
     In one embodiment, the two resonant inductors Lr 1  and Lr 2  are coupled to each other via a common magnetic core. Voltage source Vcc provides power to switch driver circuit  150  and bridge circuit  125  and replenishes gate activation energy as necessary as a result of losses. 
     Note that during operation, coupling inductors Lr 1  and Lr 2  can operate as a voltage boost transformer. 
     According to one embodiment, the driving MOSFET pairs (e.g., switches M 1 , M 2 , M 3 , and M 4 ) work in the complementary control mode respectively. The controller  110  can incorporate a dead time in respective one or more transitions (on→off, off→on) to prevent cross-conduction. In other words, the switch driver circuit is operated such that there is at least a small delay between activating switch element  140 - 1  and activating switch element  140 - 2 . 
       FIG. 3  is an example diagram illustrating timing information associated with switch driver circuit  150  according to embodiments herein. The principle operation of switch driver circuit  150  (in  FIG. 2 ) is discussed below. Controller  110  produces and drives switch driver circuit  150  with signal VgsM 1  (e.g., the gate voltage of switch element  140 - 1 ), signal VgsM 1  (e.g., the gate voltage of switch element M 1 ), signal VgsM 2  (e.g., the gate voltage of switch element M 2 ), signal VgsM 3  (e.g., the gate voltage of switch element M 3 ), and signal VgsM 4  (e.g., the gate voltage of switch element M 4 ). In represents current through inductor Lr 1 . Ir 2  represents current through inductor Lr 2 . VgsL is a gate voltage of switch element  140 - 2  (e.g., switch element ML). VgsH is a gate voltage of switch element  140 - 1  (e.g., switch element MH). As mentioned above, inductor Lr 1  and inductor Lr 2  of bridge circuit  125  can have a common magnetic core. 
     1). Turning Off Switch ML (e.g., Switch Element  140 - 2 ) 
     At t 0  of  FIG. 3 , controller  110  switches M 1  off to induce the resonant action to turn off the bottom switch ML (e.g., switch element  140 - 2 ). Energy (e.g., gate activation energy) stored in the input gate capacitor CissL (e.g., inherent gate capacitance of gate M L ) and the inductor Lr 1  is recovered through the inductor Lr 2  and the input capacitor. Before t 1 , the voltage VgsL on the gate capacitor CissL is decreased to zero and is clamped to zero by the body diode (e.g., inherent diode) of switch M 2 . At t 1 , the controller  110  turns on switch M 2  under Zero Voltage Switching (ZVS) condition, and the gate voltage VgsL is clamped to zero and provides low impedance. The interval (t 2 -t 1 ) is the dead time between gate signals VgsL and VgsH. 
     2). Turning on Switch MH (e.g., Switch Element  140 - 1 ) 
     At t 2 , the controller  110  turns off switch M 4 , inducing the resonant action to turn on the top switch MH (e.g., switch element  140 - 1 ). Energy is transferred from the large capacitor C 3  to the input gate capacitor CissH. Before t 3 , the voltage VgsH on the gate capacitor CissH is increased to Vcb, which is the voltage across the capacitors C 3  and C 4  and normally equals the source voltage Vcc, and is clamped to Vcb by the body diode of switch M 3 . At t 3 , the controller  110  turns on switch M 3  under ZVS condition, and the gate voltage VgsH is clamped to Vcb; switch element  140 - 1  thus provides low impedance because it is turned on. Typical values for CissH, CissL can be in the order of 1-10 nF. An example value for the resonant inductors (Lr 1  and Lr 2 ) are 1 uH and the coupling inductor LM can be 0.9 uH. Example values for input capacitors C 1  through C 4  are in the order of few uF. Of course, these are only a few examples of the typical and any value capacitors and inductors can be used in the circuit. 
     3). Turning Off the Switch MH (e.g., Switch Element  140 - 1 ) 
     At t 4 , the controller  110  turns off switch M 3 , inducing the resonant action to turn off the top switch MH. Energy in the input gate capacitor CissH and the inductor Lr 2  is recovered through the inductor Lr 1  and the input capacitor. Before t 5 , the voltage VgsH on the gate capacitor CissH decreases to zero and is clamped to zero by the body diode of switch M 4 . At t 5 , controller  110  turns on switch M 4  under ZVS condition, and the gate voltage VgsH is clamped to zero and provides low impedance. The interval (t 6 -t 5 ) represents the dead time between gate signals VgsL and VgsH. 
     4). Turning On the Switch ML (e.g., Switch Element  140 - 2 ) 
     At t 6 , the controller  110  turns off switch M 2 , inducing the resonant action to turn on the bottom switch ML. Energy is transferred from the large capacitor to the input gate capacitor CissL. Before t 7 , the voltage VgsL on the gate capacitor CissL increases to the source voltage Vcc, and is clamped to Vcc by the body diode of switch M 1 . At t 7 , the controller  110  turns on switch M 1  under ZVS condition, and the gate voltage VgsL is clamped to Vcc. 
     Via bridge circuit  125  (e.g., a resonance circuit supporting switching as described herein), energy (i.e., switch activation energy) is recovered during both charging and discharging transitions. Such energy circulates between the top driving circuit (e.g., the circuit driving switch element  140 - 1 ) and the bottom driving circuit (e.g., the circuit driving the switch element  140 - 2 ). Under steady state conditions, the boosted voltage Vcb is around Vcc. For example, Vcb is a little higher in value than Vcc for smaller duty cycles and a little lower than Vcc at larger duty cycles. 
       FIG. 4  is an example flowchart  400  illustrating a technique of supplying power according to embodiments herein. 
     In step  410 , the controller  110  activates switch element  140 - 1  by applying energy to a respective gate of switch element  140 - 1 . 
     In step  420 , the controller  110  activates switch element  140 - 2  by initiating a transfer of the applied energy from the respective gate of switch element  140 - 1  to a respective gate of switch element  140 - 2 . 
     Note that controller  110  can also be used to drive two MOSFETs (e.g., a resonant gate driver circuit including a set of synchronous rectifying MOSFETs) having a common ground as shown in the example embodiment of  FIG. 5A . Implementing the switch driver circuit  150  to have a common ground as in  FIG. 5A  simplifies the driving circuit. According to such an implementation, the two half-bridge type driving circuits operate in parallel relative to a common ground reference. 
     Under different duty cycles, a voltage difference can develop between Vc 1  and Vc 2 . So a relatively large capacitor Cb (as specified in  FIG. 5B ) can be added between the two gate driving circuits to balance the voltage difference. Accordingly, embodiments herein include a bridge circuit  125  including a capacitor (e.g., Cb) coupling the multiple inductors Lr 1  and Lr 2 . 
     As shown in  FIG. 5C , capacitors (C 1 , C 2 , C 3 , and C 4 ) can be eliminated from circuit  150 . 
     In  FIG. 5D , the inductors Lr 1  and Lr 2  are replaced with a single inductor Lr. The capacitors C 1 , C 2 , C 3 , and C 4  are replaced with a single capacitor Cb. 
     Accordingly, as shown in  FIGS. 5A ,  5 B,  5 C, and  5 D, bridge circuit  125  can be implemented in a number of different ways. 
     The example timing diagram as illustrated in  FIG. 3  can be used to operate the circuits in  FIGS. 5A ,  5 B, and  5 C. 
     The example timing diagram as illustrated in  FIG. 6  can be used to operate the switch driver circuit  FIG. 5D . As shown, the bridge circuit  125  in  FIG. 5D  includes an inductor Lr in series with capacitor Cb. A combination of the inductor and capacitor couples a respective gate of switch device Mh to a respective gate of switch device M 1 . 
     Note that both of the switch driver circuits (e.g., gate drivers circuits in  FIG. 5A  and  FIG. 5D ) can be utilized for driving synchronous rectifier MOSFETs in asymmetrical and symmetrical power circuits. 
     Loss Analysis 
     Ideally, the switch driver circuit  150  (e.g., resonant gate switch driver circuit) as discussed herein is lossless. However, as mentioned above, there is always some resistance in charging and discharging paths resulting in heat loss. Note that there is also energy loss in the on-state resistor Rds of driving MOSFETs (e.g., switch elements  140 ) and the gate resistor Rg (inherent or extra discrete gate resistor in series with the gate) of the power FETs. However, this loss can be minimal compared to the energy savings as a result of reusing switch activation energy. 
     During the turning-on or turning-off transition, the equivalent circuit associated with switch driver circuit  150  can be summarized as specified in circuit  700  of  FIG. 7 . Re 1  and Re 2  represent the sum of all resistances in each respective path. Vs 1  and Vs 2  represent the equivalent voltage sources in each path. Lr 1  and Lr 2  are the resonant inductors. Ci 1  and Ci 2  are the equivalent input gate capacitance of the respective switch elements  140  (e.g., power MOSFETs) during turning-on/off transitions. During the steady-state, Ci 1  and Ci 2  are treated as infinite-value capacitors. 
     The fourth-order mathematical model shown in  FIG. 7  can be expressed as: 
                 ⅆ     ⅆ   t       ⁡     [           i     r   ⁢           ⁢   1                 i     r   ⁢           ⁢   2                 v     g   ⁢           ⁢   1                 v     g   ⁢           ⁢   2             ]       =         [             -     k   2       ⁢     R     e   ⁢           ⁢   1                 -     k   3       ⁢     R     e   ⁢           ⁢   2               -     k   2             -     k   3                   -     k   3       ⁢     R     e   ⁢           ⁢   1                 -     k   1       ⁢     R     e   ⁢           ⁢   2               -     k   3             -     k   1                 m   1         0       0       0           0         m   2         0       0         ]     ⁡     [           i     r   ⁢           ⁢   1                 i     r   ⁢           ⁢   2                 v     g   ⁢           ⁢   1                 v     g   ⁢           ⁢   2             ]       +       [           k   2           k   3               k   3           k   1             0       0           0       0         ]     ⁡     [           V     s   ⁢           ⁢   1                 V     s   ⁢           ⁢   2             ]               
Where
 
     
       
         
           
             
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     During different time intervals, this four-order mathematical model may be reduced to a three-order or two-order mathematical model. For example, during turning-on of bottom switch, Ci 2  is treated as an infinite-value capacitor and vg 2  equals zero, so it will be a three-order system. If there is no turning-on/off transition (steady-state), both Ci 1  and Ci 2  are treated as infinite-value capacitors, and both vg 1  and vg 2  equal zero, so it will be reduced to be a two-order mathematical model. 
     Table I below lists different parameters for different intervals for solving differential equations. 
     
       
         
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                 M L   
                   
                 M H   
                 M H   
                 M H    
                   
                 M L    
                 M L   
               
               
                   
                 turning off 
                 Dead time 
                 turning on 
                 ON state 
                 turning off 
                 Dead time 
                 turning on 
                 ON state 
               
               
                   
                 (t 1 -t 0 ) 
                 (t 2 -t 1 ) 
                 (t 3 -t 2 ) 
                 (t 4 -t 3 ) 
                 t 5 -t 4 ) 
                 (t 6 -t 5 ) 
                 (t 7 -t 6 ) 
                 (t 0 -t 7)   
               
               
                   
               
             
             
               
                 System Order 
                 3 
                 2 
                 3 
                 2 
                 3 
                 2 
                 3 
                 2 
               
               
                 V s1   
                 V c1   
                 V c1   
                 V c1   
                 V c1   
                 V c1   
                 V c1   
                 V c1   
                 V c1 -V cc   
               
               
                 V s2   
                 V c2   
                 V c2   
                 V c2   
                 V c2 -V cc   
                 V c2   
                 V c2   
                 V c2   
                 V c2   
               
               
                 R e1   
                 R g   
                 R ds   
                 R ds   
                 R ds   
                 R d   
                 R ds   
                 R g   
                 R ds   
               
               
                 R e2   
                 R ds   
                 R ds   
                 R g   
                 R ds   
                 R ds   
                 R ds   
                 R ds   
                 R ds   
               
               
                 C i1   
                 C issL   
                 Inf. 
                 Inf. 
                 Inf. 
                 Inf. 
                 Inf. 
                 C issL   
                 Inf. 
               
               
                 C i2   
                 Inf. 
                 Inf. 
                 C issH   
                 Inf. 
                 C issH   
                 Inf. 
                 Inf. 
                 Inf. 
               
               
                 ν g1   
                 ν g1   
                 0 
                 0 
                 0 
                 0 
                 0 
                 ν g1   
                 0 
               
               
                 ν g2   
                 0 
                 0 
                 ν g2   
                 0 
                 ν g2   
                 0 
                 0 
                 0 
               
               
                 V gs0   
                 V cc   
                 0 
                 0 
                 0 
                 V cc   
                 0 
                 0 
                 0 
               
               
                   
               
             
          
         
       
     
     So, the resistive power loss can be estimated as: 
     
       
         
           
             
               
                 p 
                 r 
               
               ⁡ 
               
                 ( 
                 t 
                 ) 
               
             
             = 
             
               
                 
                   
                     R 
                     
                       e 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   
                     T 
                     s 
                   
                 
                 ⁢ 
                 
                   
                     ∫ 
                     0 
                     
                       T 
                       s 
                     
                   
                   ⁢ 
                   
                     
                       
                         i 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         2 
                       
                       ⁡ 
                       
                         ( 
                         t 
                         ) 
                       
                     
                     · 
                     
                       ⅆ 
                       t 
                     
                   
                 
               
               + 
               
                 
                   
                     R 
                     
                       e 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   
                     T 
                     s 
                   
                 
                 ⁢ 
                 
                   
                     ∫ 
                     0 
                     
                       T 
                       s 
                     
                   
                   ⁢ 
                   
                     
                       
                         i 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                         2 
                       
                       ⁡ 
                       
                         ( 
                         t 
                         ) 
                       
                     
                     · 
                     
                       ⅆ 
                       t 
                     
                   
                 
               
             
           
         
       
     
       FIG. 8  is an example diagram illustrating the percentage savings in driving losses of the proposed resonant gate driver as compared to losses in conventional gate driver circuits. The rise/fall time is about 35 ns. Larger gate resistor values result in more driving losses at the same rise/fall time. In order to reduce driving losses, one embodiment herein includes utilizing power field effect transistors with small gate resistor values. 
     Example Simulation Results 
     To verify the performance of an example embodiment of switch driver circuit  150 , simulations run in PSPICE. SPICE model IRLMS  1902  from International Rectifier Co. was chosen for the small driving switches (M 1 , M 2 , M 3 , and M 4 ). The voltage source was set to 5 volts. The gate resistor Rg is assumed to be 1Ω, and CissH, CissL was assumed to be 5 nF (nanofarads). The resonant inductors (Lr 1  and Lr 2 ) are 1 uH (microhenry) and the coupling coefficient was set be 0.9, thus LM was set to is 0.9 uH. The switching frequency is 1 MHz (megahertz). 
       FIG. 9  is an example diagram illustrating simulation results associated with switch driver circuit  150  for the parameter settings as indicated above. The rise/fall time is about 35 ns (nanoseconds) and the power consumption is about 90 mW (milliwatts), which is a very small loss amount. 
     Note that techniques herein are well suited for use in switching applications. However, it should be noted that embodiments herein are not limited to use in such applications and that the techniques discussed herein are well suited for other applications as well. 
     While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application as defined by the appended claims. Such variations are intended to be covered by the scope of this present application. As such, the foregoing description of embodiments of the present application is not intended to be limiting. Rather, any limitations to the invention are presented in the following claims.