Abstract:
A direct-current current-voltage (DCIV) method enables rapid evaluation of the degradation of deep-submicron nMOSTs and pMOSTs under channel hot carrier stress resulting from a p/n junction forward biased at a safe operating voltage level.

Description:
This application is a 371 of PCT/US98/06703 filed Apr. 4, 1998 which claims benefit of 60/043,370 filed Apr. 4, 1997. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to the field of testing and diagnosing MOS transistors and MOS transistor fabrication and design. 
     2. Description of the Related Art 
     A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. The technique uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density. The debase and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping. 
     It is well recognized that the electrical characteristics of metal-oxide-semiconductor transistors (MOST&#39;s) and bipolar junction transistors (BJT&#39;s) degrade during circuit operation due to channel-hot-electron (CHE) and substrate-hot-electron (SHE) stresses which increase oxide (Q OT ) and interface trap (Q IT ) densities [1], [2] 1 . In MOST&#39;s , the trapped charges reduce the mobility (Δμ) and shift the threshold gate voltage (ΔV GT ), both of which reduce drain saturation current (ΔI D ) which slows down the switching speed due to longer charging time of interconnect or load capacitances at lower currents. The trapped charges also shift the subthreshold gate voltage (ΔV GT-sub ), and decrease subthreshold slope of the drain-current versus gate-voltage curve, which reduces the current cut-off sharpness, thereby increasing leakage current or standby power and decreasing the noise margin. In BJT&#39;s , Q IT  and Q OT  will increase the minority carrier recombination rate in the base, thereby reducing its current gain, such as the common-emitter current gain, β F  [3]. Thus, a quantative separation of the effects of Q OT  and Q IT  is necessary to delineate the location and physical origin of the degradation in order to design and manufacture highly reliable integrated circuits with ten-year or longer operating life. 
     The separation of Q OT  and Q IT  is generally difficult. It has not been reliably separated using the traditional capacitance and conductance methods or the transient methods because the test structures are two-terminal capacitors, or very small test transistors which give extremely small capacitances due to the very small device area. Many traditional methods for separating Q OT  and Q IT  were reviewed [4], and a two-step method was demonstrated. However, it uses the subthreshold slope to monitor Q IT  which is reliable only when there is not an inhomogeneous or lateral distribution of Q IT  and Q OT . Hence, it is not reliable for monitoring the highly nonuniform Q IT  and Q OT  generated by CHE stress. 
     A novel method is demonstrated in this paper which measures the de base and collector currents versus the gate voltage, to be known as DCIV method (in analogy to the traditional usage such as HFCV for high-frequency capacitance-voltage or QSCV for quasi-static CV), to monitor the Q IT  and Q OT . The novel DCIV method contains two features: 1) The base current (I B ) of the vertical BJT is used to measure the recombination current at the interface traps generated during fabrication or operation which avoids the error from lateral distribution or areal nonuniformity of Q IT  and Q OT  because I B  is directly proportional to N IT  or Q IT /q. 2) The Collector current (I C ) of the vertical BJT is used to measure the Q OT  because I C  increases sharply when the gate voltage passes the flat-band value toward depletion and inversion. The method will be described in this article using the nMOST and npnBJT of the BiMOS structure shown in FIG.  1 . This BiMOS structure has been used previously to fabricate large test transistors wish nearly 400,000 μm 2  gate oxide area by Thompson ([8] and [9] cited in [4]), but it is also present in the submicrometer nMOST&#39;s in a p-well on n-substrate of production CMOS (Complementary MOS) inverter circuits. Thus, the novel DCIV method to be described can be easily applied to production test transistors and some examples to be given were data measured on micrometer and submicrometer MOST-BIT production structures. 
     With reference to FIG. 1, the BIT can be measured before and after a stress in two configurations: The top-emitter (top-E) or bottom-emitter (bottom-E) measurement configurations, with the n+drain/p-base or n+substrate/n-epitaxy/p-base as the forward biased emitter/base junction. Our geometrical terminology deviates from the traditional, emitter-up and emitter-down, which confuses the geometrical location of the emitter with the emitted-charge flow direction. In both configurations, the shape of the I B −V GB  curve and the magnitude of I B  at a constant V EB  will measure Q IT  [5], [6]. However, we recently anticipated that the shape and magnitude of I C  will also be a strong function of V GB  in both configurations because I C  increases sharply at the flat-band gate voltage, V GB-flatband , from a low constant current t a high constant current at strong inversion voltage V GB-threshold . This sharp increase occurs when the electron-channel between the n+drain and n+drain and n+source appears at V GB-flatband  which abruptly increases the emitter/base area in the top-E configuration and the collector/base area in the bottom-E configuration. 
     The stress-induced base current, ΔI B , is solely due to electron-hole recombination at the stress-generated interface traps [5], [6], hence, is a function of stress-induced interface charge and trap concentrations, ΔQ IT  and ΔN IT , to the stress-induced density-of-states of the interface traps and surface recombination velocity, ΔD IT  and ΔS Q . However, the increase of the collector current with V GB  is nearly all from geometrical increase in the emitter or collector area contributed from the nMOST&#39;s electron channel. Therefore; the lateral shift in the I C −V GB  curve, ΔV-GB, is mainly a function of the stress-induced change of flatband gate voltage, ΔV GB-flatband+  and hence is a very sensitive monitor of ΔQ QT +ΔQ IT . Thus, combining the ΔI B −V GB  and I C −V GB  data will enable the separation of ΔQ OT  and ΔQ IT . Experimental data in the following section will demonstrate this capability of the novel DCIV method. 
     Minority carrier surface recombination rate or velocity S o at the Si/SiQ 2  interface was studied extensively since the use of MOS-gate-controlled BJT was demonstrated by one of us in 1961-1962 [5], [6]. In the early and follow-up experiments, I B  was measured in either the top-emitter configuration [5]-[9] or bottom-emitter configuration [10]-[13], to evaluate S O . In [7] through [9], the BJT β F  degradation during emitter-base reverse-bias stress at the junction breakdown voltage was also studied. In many of these earlier measurements, the I B −V GB  curve was also displaced along the gate-voltage axis due to stress, but the peak in I B −V GB  was not very sharp. In some cases no peak was observed. In addition, the magnitude of I B  was greatly increased by the generated N IT . Thus, an estimate of ΔQ OT  from the shift of V GB  at the peak ΔI B  in the ΔI B −V GB  curve cannot be very accurate and reliable. 
     Production n-channel MOST fabricated by state-of-the-art CMOS process is measured to demonstrate the proposed DCIV method. The starting n-Si wafer has a p-base well with surface concentration of 1×10 16  cm −3 , gate oxide thickness of x O ≅150 Å. channel length L=1.6 μm, and the gate area of A G =1.6×100 μm 2 . The cross-sectional view was shown in FIG.  1 . 
     FIG.  2 ( a ) and ( b ) shows the npn-BJT&#39;s I B −V GB  and I C −V GB  curves, measured in both the top-E and bottom-E configurations, before and after SHE stress as labeled. The oxide charges and interface traps were generated by areally uniform SHE stress with V SB =V DB =4 V, and V GB =7.5 V. During SHE stress, the bottom emitter junction (n+substrate/n−epitaxy/p-base shown in FIG. 1) was forward-biased to inject electrons into the p-base. Some of these electrons are accelerated (designated as hot electrons), by the reverse-biased surface space-charge layer (V SB −V DB =4V) of gate-induced collector/base junction area, to &gt;3.2 eV kinetic energy. These hot electrons are then injected into the gate oxide over the 3.12 eV SiO 2 /Si electron potential barrier. Some of the injected electrons are captured by the neutral oxygen 
     vacancy centers [14]-[15], giving V O +e − →V O   −  and the negative Q OT  or positive ΔV GT . Because of their high kinetic energy (˜4 eV from V DB =V SB =4V) which is greater than the bond energy (˜3 eV) of the strained Si—Si and Si—O interfacial bonds and the interfacial Si—H and Si—O bonds, the hot electrons also created some new interface traps, N IT  or D IT , as indicated by the large increase of I B  in FIG.  2 ( a ) measure in both the top-emitter and bottom-emitter configurations. The build-up of Q IT  also decreases the subthreshold slope of the nMOST&#39;s I D −V GB  curve shown in FIG.  2 ( c ), however, the V GB  shift in I D−V   GB  is due to the build-up of both Q OT  and Q IT                 Δ                   V   GB       =       Δ                   V     GB   -   OT         +     ΔV     GB   -   IT                 (   1   )                               ≡       -     (       Δ                   Q   OT       +     Δ                   Q   IT         )       /     C   O               (1a)                                
     which cannot be separated by this MOST I D −V GB  measurement alone unless additional properties of the interface traps are known or assumed, a limitation also present in Terman&#39;s method to obtain D IT  from HFCV characteristics. The two BJT measurements just described in FIG.  2 ( a ) and ( b ) can help to separate the Q OT  and Q IT , which are analyzed as follows. 
     The stress-generated increase of the I B  shown in FIG.  2 ( a ) gives a direct measure of the surface recombination velocity S O  and the density-of-the-state of the interface traps, D IT  because it is proportional to the maximum of the stress induced I B ΔI B ≡I B  (post-stress) −I B  (pre-stress). Its peak and shape can be distorted by areal nonuniformity of Q OT , D IT , or other device parameters, such as base dopant concentration and oxide thickness. But areal nonuniformity alone cannot produce a base current which must come from electron-hole recombination, unlike the HFCV (C gb −V GB ) used in Terman&#39;s analysis and the I D −V GB  in the subthreshold slope analysis of the interface trap density, whose distortion could solely arise from areal inhomogeneity even when D IT =0. 
     The V GB-IT  component can then be calculated from (2B) given below [5] 
     
       
         ΔI B ≅(qA G n i ΔS O /2)exp (qV BE /2kT)  (2) 
       
     
     
       
         ΔS O ≅(π/2)τ O (−) th •ΔN IT   (2a) 
       
     
     
       
         ΔQ IT ≡−C O ΔV GB-IT ≡qΔN IT ≅qΔD IT •ΔE IT   (2b) 
       
     
     The density-of-state, ΔD IT  (1/cm 2 −eV), and carrier capture cross sections, τ n =τ p =τ O  (cm 2 ), of the interface traps are assumed to be independent of the binding energy in the energy range ΔE IT  in the Si energy gap [16]. The calculation of ΔV GB-IT  is more complex than (2)-(2B) for an energy distribution of interface traps with energy-dependent density-of-state, D IT (E IT ) and carrier capture cross sections, τ n (E IT ) and τ p (E IT ). However, S O  calculated from measured ΔI B  after stress using (2), can still be used to monitor the build-up of the interface traps and the associated ΔV GB-IT . In the example shown in FIG.  2 ( a ), the numerical results are ΔS O ≅1600 cm/s at the I B-pak  which occurs at the gap energy position of V S −V F =−0.24 V below the midgap for the top-E curve stressed with a fluence of 5×10 18  electron/cm 2 , and ΔS O ≅40 cm/s at V S −V F =−0.26 V for the bottom-E curve stressed at a fluence of 1×10 17  electron/cm 2 . For many devices measured, I B-peak  of the bottom-E was about five times smaller than that of top-E. 
     The prestress-poststress I C −V GB  curves of both the top-E and bottom-E configurations shown in FIG.  2 ( b ) give a very sensitive measure of the stress-generated V GB  shift. I C  is flat in the accumulation range and is proportional to the area of the n+drain/p-base well junction (or the sum of the area of n+drain and n+source if drain and source are tied together during the I C  measurement). When V GB ≧V FB ≅−0.55 V (Greater sign is for nMOST), an electron surface channel begins to form which will collect the electrons injected by the bottom-emitter and pass the collected electrons to the n+drain or/and n+source, causing an increase of I C  (I D +I S ). The I C  quickly reaches a high plateau as V GB  increases further to about −0.15V. This increase of I C  is proportional to the added collector area from the gate-induced electron-channel. The three characteristic Si surface potentials of Si energy band bendings (FB−flatband at V S −0 V, INV=inversion at equal electron-hold surface concentration N S =P S  or V S =V F −V BE /2, and TH=threshold or strong inversion at N S =P base  or V S =2V F −V BE ) are marked by dots on the pre-stress I C −V GB  curve in FIG.  2 ( b ). They show that I C  starts to rise sharply at V FB ≅−0.55 V at flatband in this example, reaching the higher plateau about halfway between inversion V GB-inversion ≅−0.25 V and the MOST threshold voltage, V GB-th ≅+0.05 V. Thus, the rise of I C  is sharp and occurs in a short range of V GB , in this case, −0.05 V−(−0.55 V)=0.5 V. 
     It was asserted in the preceding discussion that I C  is not caused by carrier recombination or generation of the newly generated interface traps, but solely by the increase of the emitter or collector area from the gate-induced electron channel described above. This is not experimentally proven in FIG.  2 ( b ) by the nearly parallel V GB  shift of the post-stress I C  from its-pre-stress range with the nearly identical height for both the top-E and bottom-E measurement configurations, although this stress has generated a large N IT  to give the large increase of I B  shown in FIG.  2 ( a ). This model is further supported by the observed and anticipated reduction of slope of the post-stress I C −V GB  at higher V EB  bias reflecting a larger negative Q IT  (≅ΔD IT •ΔE IT ). This is expected from the higher surface electron concentration injected by the emitter to charge the interface traps negatively due to i) the added stress-induced ΔD IT , and ii) a larger energy range of N IT  towards the Si conduction band edge, estimated by ΔE T ˜V BE . 
     A quantitative analysis of the Q IT  contribution to I C −V CB  shift in FIG.  2 ( b ) can be made from 
     
       
         ΔV GB-IT =−ΔQ it (V F −V FN )/C O   (3) 
       
     
     by using the fundamental property of intrinsic interface traps whose charge state is acceptor-like (negatively charged) near the conduction band edge and donor-like (Positively charged) near the valence band edge, because they are localized or bound electron states which are split-off states from the respective band states by random atomic location perturbation of the crystalline periodic potential at the SiO 2 /Si interface. This charge state assignment was implied by Bardeen when he introduced the concept of neutral Fermi level V FN [17]. For Si, V FN  is at about E V +(⅓)E G  [17], [18]. Thus, V F −V FN ≅O at flat-band for the  p —Si used here which was doped with N AA ˜10 16  cm −3  of boron acceptors, and C o ΔV GB ≅−ΔQ QT . The stress induced V GB-FB  shift in the I C −V CB  curves of FIG.  2 ( b ) then gives 
     
       
         ΔN OT =(C o / q )ΔV GB-OT   (4) 
       
     
     
       
         ≅(C o /q)[−0.2−(−0.55)]=4.3×10 11  cm −2   (4a) 
       
     
     which can then be used in (1) to separate Q IT  and Q QT . In view of the nearly parallel shift of the I C −V GB  curves at low V BE (˜0.3 V in these examples), it is not necessary to locate the V GB-FB  point to get ΔV GB-OT  point to get ΔV GB-OT  in practical applications. The change of the subthreshold slope of the MOST I D −V GB  slope has been commonly used to monitor Q it . It is accurate if N it  is areally constant. This is untenable in the practical CHE stress and can give erroneous results [4], [19]. 2  In the present example, N it  was generated by the areally uniform SHEi stress, thus, a decreasing slope of I D −V GB  shown in FIG.  2 ( c ) gives an indication of a real stress-induced N IT  rather than inhomogeneity, analogous to the reasoning for the anticipated experimental post-stress slope reduction of the I C −V GB  just discussed. However, an important point is frequently overlooked: N it  or D IT (E IT )ΔE it  from the I P −V GB  in FIG.  2 ( c ) is in the strong inversion voltage range, V GB &gt;V CB-TH  or in the Si-gap energy range V S &gt;2V F −V BE (2kT/q) near the conduction band edge. In contrast, N IT  or D it  (E it )ΔE it  in FIG.  2 ( b ) is in the mid-range of the Si energy gap from flat-band (V s =0) to strong inversion or threshold (V S =2V F −V BE ). Thus, the subthreshold slope monitors an additional energy range of D IT  near the minority band edge, which is application-important because the MOST operates in this strong inversion range when it is turned on. But it is also fundamentally significant because the decreasing post-stress subthreshold slope [compressed by logarithmic I d  but still visible in the solid curve FIG.  2 ( e )] indicates an increasing D IT  with energy towards the conduction band edge, which is consistent with the commonly depicted U-shaped D IT  as anticipated by the fundamental microscopic-atomic model of interface states implied by Bardeen [17]. A qualitative estimate from the subthreshold slope change in FIG.  2 ( c ), using the well known equation [20] gives 
     
       
         D IT =(C O / q )( q /2.303 kT)ΔS  
       
     
     
       
          ≅10 12  cm −2   c V −1   
       
     
     Additional examples are given in FIG.  3 ( a )-( e ) for the bottom-Emitter configuration which use I C  to monitor negative, positive, and turn-around ΔQ QT  induced by stress. FIG.  3 ( a ) is identical to FIG.  2 ( b ) showing positive ΔV CB  from negative ΔQ GB  after SHEi stress (curve 2) with V GB =12 V and V DB =V SB =10 V, due to positive ΔQ QT , as anticipated [15] by the electron-impact emission of electrons trapped at the neutral oxygen vacancy, V ( ) +c o →V ( ) +2e−. FIG.  3 ( c ) demonstrates the successive stresses that gave negative ΔQ QT  first and then positive ΔQ QT , which is the so-called turn-around effect coined by Young [21]. Curve 1, showing positive ΔV GB , was measured after a short (˜1 s) CHEi stress at V GB =V DB ≅15 V with the source floating, indicating negative ΔQ QT  due to capture of the electrons injected into the oxide along the entire length of the strongly inverted n-channel because V GB &gt;&gt;V TH . Curve 2, showing negative ΔV GB , was measured after an additional 500 s stress, indicating that some originally trapped electrons (not the captured electrons during the short stress) are emitted via a second pathway, the impact emission just described for FIG.  3 ( b ). 
     The stress condition used in FIG.  3 ( c ), with source floating or shorted to drain, approximates that in BJT under emitter-base junction reverse-bias stress. Thus, the bottom-emitter measurement configuration can be used to study the fundamental degradation mechanisms in BJT even without a separated gate over the emitter-base junction [3]. 
     The sensitivity of this new DCIV is demonstrated experimentally in FIG. 4 which gives a sensitivity limit or minimum measurable S O &lt;˜1 cm/s and N IT ≦10 9  cm −2 . 
     SUMMARY OF THE INVENTION 
     A new direct-current current-voltage (DCIV) method for separating the oxide charge and interface traps in oxidized silicon is presented. The inventive method has several unique features difficult to attain previously. 1) It is a purely de method resulting in ease of instrumentation and extremely high detection sensitivity 2) It gives. true D IT , not affected by inhomogeneity and hence usable for profiling D it  and Q IT . 3) It has very high D IT  sensitivity in presence of large Q QT . 4) It is applicable to submicrometer area devices in conventional production CMOS and nMOST junction well structure. 5) It can monitor the degradation kinetics of both MOST&#39;s and BJT&#39;s. 
     Several demonstrations are given to illustrate the simple and high-sensitivity of the DC-IV method for monitoring the variation of the electrical characteristics of submicron silicon MOS transistors during channel hot carrier stress. Examples are given on interface traps generated during channel hot electron and hole stress of submicron nMOST&#39;s and pMOST&#39;s with 0.35 to 100 micrometer channels from quarter-micron (1996) to two-micron (&lt;1990) technologies. 
     The simple and high-sensitivity d.c. current-voltage 9DCIV) method was first employed nearly four-decades ago to characterize surface recombination and channel on silicon transistors [1]. It was recently reintroduced by Neugroschel and Sah [2], to measure the volume and areal densities of oxide (N OT ) and interface traps (N it ) in stressed silicon MOS and bipolar junction transistors (MOST&#39;s and BJT&#39;s). The DCIV is a plot of the base or body terminal-current versus the gate-base or gate-body voltage. Its high sensitivity derives from the common-emitter current gain, beta, of the bipolar junction transistor 9BJT) which also exists in all MOST structures. In contrast to the gated-diode method (gain=1) [1]. The DCIV method has been applied rather successfully by Neugroschel and Sah and their graduate students to delineate the mechanisms-origins and to analyze the kinetics of interface and oxide trap generation by energetic or hot carriers, and to predict the ten-year operation time-to-failure (TTF OP ) of deep-submicron silicon n-channel and p-channel MOS transistors (nMOST&#39;s) and pMOST&#39;s) under channel hot electron (CHE) or hole (CHH) stress [3]. It was also used by them to characterize deep-submicron silicon npn and pnp BJT&#39;s [4] and germanium-silicon-based DJT&#39;s [5], stressed by reverse emitter-base biases. Recently, the DCIV method was used in an experimental verification of a new two-parameter bond-breaking theory of interface trap generation [6], and in a demonstration of the current-accelerated channel hot carrier stress methodology to shorten the 10-year TTF OP  determination from about three years to 18-days [7]. This paper provides several demonstration examples of the DCIV method applied to Si nMOST&#39;s and pMOST&#39;s manufactured by 2-micron 1990 and quarter-micron 1996 technologies, using computer-controlled data acquisition equipment such as the HP4145 and HP4156. 
     FIG. 5 shows the drain-emitter DCIV bias configuration (the other is the source-emitter to measure N QR  and N IT  near the source) of a stressed nMOST in p-well on p+substrate, which is to be measured by the DCIV method to give the I B −V GB  characteristics. 
     The SiO 2 /Si interface traps (open triangles) were generated over the drain/channel junction space-charge region and over the n-channel region during the CHE stress from hot carriers breaking the hydrogen bonds (Si:H and SiO:H), I B  contains two emitter (not shown) and six base recombination components, the latter from p-well holes recombining with the drain-emitter injected electrons at the electron-hole (e-h) recombination centers or interface traps located in the six regions. They are distinguished by one alphabetic and one numeric subscript: c-channel region, s=surface space-charge region, b=bulk space-charge region; 1 and 2 from I B ≅exp(qV BE /nk B T) where n=1 for Shockley&#39;s ideal p/n junction diode law and n=2 for the ideal Sah-Noyce-Shockley (SNS) space-charge-layer recombination law. Fom left to right in FIG. 5, these are: (1)I B-c1  over the n-channel region, (2) I B.     —     2  over the  s urface space-charge region of the drain/body junction along the n-channel-perimeter, (3) I B-b2  in the drain/body junction&#39;s  b ulk-space-charge region, (4) I B-b1  in the drain/body junction&#39;s  b ulk-quasi-neutral region, (5) I B-b2  same as (2) but outside of the n-channel-perimeter, and (6) I B-c1  same as (1) but outside of the n-channel-perimeter. For studying kinetics and mechanisms, and extrapolating TTF OP , the channel component, ΔI B =ΔI B-c1 +ΔI B-2 . generated by channel hot carriers (electrons), must be plotted against the channel hot carrier stress fluence. I channel-hot xi stress /qxArea. ΔI B  is obtained from I B-stress vs V GB  and I B-prestress vs V GB  curves, and similarly, I channel-hot  fromΔI D =I D −I D-no-channel-hot vsV GB . 
     FIGS.  6 ( a )-( d ) show a sample set of stress-and-measure 9SAM) DCIV data of long-, short-, n- and p-channel MOST&#39;s with W/L=100/100, 20/20, 17.5/0.35 and 20/0.7 μm 2 . 
     The Is measured at the low drain-emitter forward-bias (O4V) follows the n=2 SNS law indicating c-h recombination at the interface traps located in the drain junction surface-space-charge region, I B.s2 . Higher drain-emitter forward-bias gives the n=1 component from the interface traps in the channel region, I B-c1 . The stress-generated base current, ΔI B  (n=2), increases linearly with stress-time or stress-fluence initially, as t ½  at intermediate fluence, and toward a constant at long stress time. The appearance of the two peaks depends on channel length and technology. The growth rates of the two peaks, keeping the stress voltage V stress =V D −(V G −V T ) constant, were also very different. The threshold stress voltage was determined for several MOST designs using the two-parameter bond breaking model proposed by SAH [6], 1.87V for a npnBJT and 3.06V for both the long-channel nMOST&#39;s and pMOST&#39;s , which were thought to be dependent on the gate oxide-technology and channel-impurity-profile as anticipated by the theory. Based on these considerations, the fast-growing peak is tentatively identified as the Si.interface trap from breaking the Si:H bond by the channel hot carriers while the nearly constant or slow-growing peak, the SiO. interface trap from breaking the SiO:H bond. 
     FIGS.  7 ( a ) and ( b ) illustrate the application of the DCIV method for extrapolating the 10-year TTF OP  using the current-accelerated CHE and CHH stress methodology (CACHE and CACHH), based on the TTF criteria of ΔI B /I B =+100% for (100/100) nMOST and 20% for (20/20) pMOST. The ΔI B  is proportional to the subthreshold-leakage current or standby-power failure in mega-transistor CMOS circuits. The fluence-to-failure (FTF) in FIG.  3 ( b ) is computed from FTF=∫ΔI D dt/qA drain  where ΔI D  is the channel hot electron current component of the total drain current during stress with (V BE-stress &gt;0) or without (V BE-stress =0) acceleration for the nMOST datapoints in FIG.  3 ( a ). A drain  should be the channel cross-sectional area, however, the drain contact area was used for normalization. TTF OP  is obtained from TTF OP =FTF/(I I)-no-acceleration /qA drain . 
     The following table gives the SAM times (not including data analysis time) to determine the 10-year TTF OP  using current-acceleration up to 50×. It can be further sped up by 20× using the two-parameter theory. 
     
       
         
               
             
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
             
               
               
               
             
           
               
                   
               
               
                 nMOST CACHE and CHE SAM Times 
               
             
          
           
               
                 Stress 
                 CACHE 
                 CHE 
               
             
          
           
               
                 V DS  Volt 
                 Stress 
                 Meas. 
                 Stress 
                 Meas. 
               
               
                   
               
             
          
           
               
                 7.0 
                 1.4 
                 m 
                 50 
                 m 
                 21 
                 m 
                 1.8 
                 h 
               
               
                 6.5 
                 3.3 
                 m 
                 1.0 
                 h 
                 2.8 
                 h 
                 3.3 
                 h 
               
               
                 6.0 
                 28.8 
                 m 
                 2.5 
                 h 
                 11.5 
                 h 
                 3.8 
                 h 
               
               
                 5.5 
                 3.9 
                 h 
                 2.8 
                 h 
                 56.3 
                 h 
                 4.5 
                 h 
               
               
                 5.0 
                 38.7 
                 h 
                 6.0 
                 h 
                 *556 
                 h 
                 6.0 
                 h 
               
               
                 4.5 
                 365. 
                 h 
                 9.3 
                 h 
                 *22.8 
                 kh 
                 9.3 
                 h 
               
               
                 Subtotal 
                 408.2 
                 h 
                 22.4 
                 h 
                 *23.4 
                 kh 
                 29.7 
                 h 
               
             
          
           
               
                 TOTAL SAM 
                 430.6 hours 
                 23,456.7 hours 
               
               
                 −computed 
                 (−18 days) 
                 (−977 days) 
               
               
                   
               
             
          
         
       
     
     Application of the DCIV method is described for rapid evaluation of the degradation of deep-submicron nMOSTs and pMOSTs under channel hot carrier stress. At a 50× current-acceleration the 10-year operation time-to-failure was obtained from data taken in 430 hours (18 days-3 weeks) instead of 977 days (−3 years). 
     The D.C. Current-Voltage method is demonstrated as a diagnosis monitor to evaluate process variations and device designs of silicon n-channel and p-channel Metal-Oxide-Semiconductor Transistors (MOSTs) fabricated from 0.35-micron and advanced sub-0.25-micron technologies. Source-drain asymmetry, areal nonuniformity, residual interface trap density-location-energy-level, minute variation of dopant impurity concentration at the drain-channel and source-channel perimeters under the gate oxide, and well-body and contact defects are measured by the gate-voltage variation of the base recombination currents via interface traps and p/n-junction tunneling. The minority carriers injected by a forward-biased junction serves as the sensitive probe for measuring the interface trap properties. Demonstrations of all the combinations of forward or zero bias applied to the two or three p/n junctions of generic MOST designs for CMOS are presented 
     The DCIV measurement method described above to measures the volume density of oxide traps (N OT  in cm −3 ) and areal density of interface traps (N IT  in cm −2 ) in electrically stressed silicon bipolar-junction and metal-oxide-semiconductor transistors (BJTs and MOSTs). Due to industrial interests on using the DCIV method to evaluate the operation time-to-failure (TTF OP ) of the transistor fabrication technology and device design to meet the ten-year TTF OP  requirement of integrated circuit chips, the DCIV method has been implemented in the HP4156A (Hewlett-Packard D.C. Parameter Analyzer) by customized turn-key control-programs stored on the HP4156A diskette with a user manual giving demonstrations of the stress-and˜measure (SAM) experiments on nMOST and pMOST from 0.35-2.0 micron technologies fabricated during the past decade (1988-1997). Applications of the DCIV method included lateral profiling the interface traps, evaluation of the hydrogen bond-brealting theory of interface trap generation, separation of the interface and areal nonuniform oxide traps, linear dependence of stress-induced drain-saturation current on the stress-generated DCIV base current, reliability of transistors with low-K interconnect materials, reduction of interface trap density in p-channel MOS transistors during channel-hot-hole stress due to hydrogenation of silicon dangling-bond interface traps over the channel by hydrogen released by hot holes from hydrogenated boron acceptors in the p+drain region, a most important manufacturing application: interface trap generation by current-accelerated channel hot carrier stress to reduce the TTF OP  determination time by 100-fold from six-month or more to less than 100 hours, and reduced hot-carrier degradation rate from using deuterium annealing. The purpose of this memorandum is to illustrate a new application of the DCIV method, the diagnosis of the transistor design and fabrication technology before stress. Examples on ˜3 nm and ˜5 nm gate-oxides are given for state-of-the-art and future sub-0.25-micron CMOS technologies. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross-sectional view of the BiMOS BJT-MOST transistor structure with a nMOST in a p-base well on a n-epitaxy/n+ substrate silicon wafer with the parasitic n+/p/n+ BJT. 
     FIG. 2 is a graph depicting the effect of area-uniform SHEi stress on the npnBJT and nMOST characteristics as a function of the MOS gate voltage. 
     FIG. 3 is a graph depicting the effect of stress on collector current. 
     FIG. 4 is a graph depicting a sensitivity test of the top-emitter I B  measurement of interface traps of an unstressed BiMOS. 
     FIG. 5 is a cross-sectional view of a stressed nMOST 
     FIGS.  6 ( a )-( d ) illustrate a sample set of stress-and-measurement DCIV data of long-, short-, n- and p-channel MOSTs. 
     FIGS.  7 ( a  and  b ) provide a graphical representation of the TTT OP  extrapolation algorithm. 
     FIG. 8 is a graph depicting DE-DCIV curves. 
     FIG. 9 is a graph depicting SE-DCIV curves. 
     FIG. 10 is a graph depicting SEDE-DCIV curves. 
     FIG. 11 is a graph depicting DE-DCIV curves. 
     FIG. 12 is a graph depicting SE-DCIV curves. 
     FIG. 13 is a graph depicting SEDE-DCIV curves. 
     FIG. 14 is a graph depicting DE-DCIV curves. 
     FIG. 15 is a graph depicting SE-DCIV curves. 
     FIG. 16 is a graph depicting SEDE-DCIV curves. 
     FIG. 17 is a graph depicting BE-DCIV curves. 
     FIG. 18 is a graph depicting BE-DCIV curves. 
     FIG. 19 is a graph depicting BESE-DCIV curves. 
     FIG. 20 is a graph depicting DE-DCIV curves. 
     FIG. 21 is a graph depicting SE-DCIV curves. 
     FIG. 22 is a graph depicting SEDE-DCIV curves. 
     FIG. 23 is a cross-sectional view of generic CMOS transistors. 
     FIGS.  24 ( a  and  b ) are curves depicting the DE-DCIV and SE-DCIV of a prestressed long-channel silicon nMOST and pMOST. 
     FIGS.  25 ( a  and  b ) are curves depicting the DE-DCIV and SE-DCIV of a prestressed short-channel silicon nMOST and pMOST. 
     FIGS.  26 ( a  and  b ) are curves depicting the drain and source transfer characteristics of a short and long channel nMOST and pMOST. 
     FIGS.  27 ( a  and  b ) are curves depicting the drain and source junction diode current-voltage characteristics of a long- and short nMOST. 
     FIGS.  28 ( a  and  b ) are curves depicting the drain and source junction diode current-voltage characteristics of a long- and short pMOSTs. 
     FIGS.  29 ( a  and  b ) represent diagnostic bottom-emitter DCIV data of long-channel pMOSTs. 
     FIG. 30 is a curve depicting the scaling law demonstration of the BE-DCIV using long-channel pMOSTs from two technologies. 
     FIG. 31 is a BE-FBIV plot for long-channel pMOSTs from two technologies. 
     FIG. 32 is a graphical representation of top-emitter DCIV data. 
     FIG. 33 is a graphical representation of the injection efficiency difference between the BE and TE DCIV configurations in a PMOST. 
     FIG. 34 is a TE-FBIV plot. 
     FIG. 35 is a graphical comparison of the gate tunneling and base recombination currents in a pMOST. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIGS. 8-22 clearly show the distinct differences between the base current, IB, measured from the drain-emitter (DE), source-emitter (SE), and bulk bottom-emitter (BE) bias configurations. For the DE-DCIV, there are two peaks in long-channel nMOST and pMOST, one growing with stress and the other nearly fixed; and there is only one observable peak in the short-channel nMOST which grew with stress. For SE-DCIV, there is only one fixed peak in the long-channel and short-channel nMOST: and there are two fixed peaks in the long-channel pMOST. For BE-DCIV, there is only one fixed peak in the long-channel nMOST and a decreasing peak in the short-channel pMOST as predicted by Sah&#39;s hydrogen-bond-breaking theory. 
     The similarities and differences between the DE-DCIV, SE-CIV and BE-DCIV curves provide a rapid determination of the properties of the interface traps, including their spatial location, energy levels, and fabrication process dependencies. A number of examples are described below. 
     Spatial Location of CHC-Generated Interface Traps 
     (1) In all three MOSTs, the long-channel nMOST (FIG. 10) and pMOST (FIG. 13) and short-channel nMOST (FIG.  16 ), the DE-DCIV growing peak (blue) indicates increasing SiO2/Si interface-trap density over the drain-junction space-charge region. This is expected and verified by the SNS (Sah-Noyce-Shockley) theory with n=2 in IB-peak ∝exp(qIVDBI/nkBT) from electron-hole recombination at interface traps in the junction space-charge region at the 0.4V forward junction bias. This is consistent with that expected from hydrogen-bond (or any weak-bond) breaking by the energetic carriers accelerated in the high-field drain-junction space-charge region. 
     (2) The constant peak in the DE-DCIV-curve (FIGS. 10 and 13) of both long-channel nMOST and pMOST indicates nearly constant SiO2/Si interface-trap density in the middle part of the channel during CHC stress. This was verified by the ideal Shockley diode law, n=1in IB∝exp(qVDB/nkBT), and is expected from the surface energy band bending and the recombination of the drain-junction injected minority carriers with the base-body-well majority carriers. 
     (3) In the short-channel nMOST the DE-DCIV curve (FIG.  16 ), there is no visible fixed (second) peak as those in the long-channel LMOST and pMOST of (2). This indicates that if interface traps are generated in the mid-channel location in this short-channel nMOST, its density is low and not observable at the VDB=−0.4V n+drain/p-body forward bias. This was indeed verified by DE-DCIV curves obtained at higher forward VDB. 
     (4) The SE-DCIV curves of the long-channel MOSTs (FIGS. 10 and 13) show no visible change with increasing stress fluence, indicating little interface traps generated in the source junction and in the mid-channel region during CHC stress. 
     (5) The SE-DCIV curves of the 17/0.35 nMOST (FIG. 16) increases with stress, indicating some interface traps were generated in the mid-channel (n=1) during CHC stress. 
     Residual Interface Traps from Fabrication Processes 
     (6) Result of (2) also states that there are considerable residual interface traps in the mid-channel region (n=1) from fabrication processes of the 20/20 pMOST and the 100/100 nMOST and this is true also in the 17/0.35 nMOST (prestress blue curve in FIG.  9 ). 
     (7) The prestress SE-DCIV curve of both 20/20 pMOST and 17/0.35 nMOST (FIGS. 13 and 16) show also a nongrowing peak at the same gate voltage as that of the growing DE-DCIV peak of these two MOSTs. This indicates that the technologies produced considerable residual interface traps in the source (also drain) junction space-charge layer. 
     Detection of Drain-Source Asymmetry 
     (Drain-Source Engineering or Areal Inhomogeneity) 
     (8) The noticeable difference between the prestress SE-DCIV curves at VGB=+2.25V of the 20/20 pMOST (FIG. 13) suggests a drain-source engineering difference, if this difference is not due to areal nonuniformity. The almost similar peaks of the 17/0.35 nMOST suggest identical drain-source engineering. 
     Interface Trap Energy Level in the Silicon Energy Gap 
     (9) The non-growing DCIV peak from the mid-channel range gives the more accurate estimate of the energy level of the interface trap. For all three MOSTs, the peak appears in the subthreshold ID-VGB curve. 
     Oxide Trap Charging 
     (10) The rather small initial relative then positive gate voltage shift (ΔVGB-peak) of the growing DE-DCIV peak of the 20/20-pMOST and 17/0.35-nMOST (FIGS. 13 and 16) indicate a small positive then negative charging of the oxide trap (ΔQOT) over the drain junction space-charge region during CHC stress. The slight +ΔVGB-peak of the small growing SE-DCIV peak of the 17/0.35-nMOST (FIG. 16) indicates a small −ΔQOT over the mid-channel region. Similarly, the unobservable ΔVGB of the non-growing IB peak of the two long-channel MOSTs (FIGS. 10 and 13) indicate no observable oxide trap charging (ΔQOT=0) over the mid-channel region. The noticeable negative ΔVGB of the growing peak of the 100/100 nMOST (FIG. 10) indicate +ΔQOT over the drain junction space-charge region during CHC stress 
     Bottom(Bulk)-Emitter Applications 
     (11) The BE-DCIV curve of the 100/100 nMOST (FIG. 17) shows only one observable peak and there is no observable increase. The n-factory also confirmed its ideal Shockley diode current origin. These affirm that this fixed IB peak is due to e-h recombination at the interface traps located at the mid-channel region. The IB current component (holes) from e-h generation at the interface traps located in the space-charge layer of the zero-biased or reverse-biased source and drain junctions is many orders of magnitude (depending on the forward bottom-emitter bias) smaller than that from e-h recombination which can only occur in the quasi-neutral region such as the mid-channel. 
     (12) The BE-DCIV/DE-DCIV comparison in FIG. 18 shows similar features as that of the SE-DCIV/DE-DCIV comparison in FIG. 22 except the VGB location of the IB peak of the SE-DCIV or DE-DCIV is shifted positively relative to that of the BE-DCIV. This understood as follows. The shape and position of the IB peak is determined by the lateral (source-to-drain) variation of the concentration of three species: boron acceptors (from drain engineering), interface traps (from hydrogen diffusion profile), and injected minority carriers (short diffusion length). Only the last would give the observed positive gate voltage shift which is consistent with the interface minority carrier (electron) concentration decay due to small diffusion length. 
     Basic Principles of DCIV 
     The DCIV method leverages the MOS &gt;field-effect=modulation of the bipolar transistor actions (minority carrier injection, and minority carrier recombination with the majority carriers at the interface traps) to monitor the gate-oxide/silicon-channel interface properties. It gives a graph of experimental base or body terminal current, I B , versus the gate-base voltage, V GB , with one of the transistor&#39;s p/n junction forward-biased to inject and increase the minority carrier concentration which increases the sensitivity, and with some of the nearby p/n junctions short-circuited to serve as the collector junctions of not-recombined minority carriers which could provide a higher differential sensitivity. 
     The metal-oxide-silicon transistor (MOST) contains at least two p/n junctions (the source and drain) and four contact pads on a chip or wafer and four terminals in a package (the source, drain, gate, and body or well-substrate wafer). For CMOS (complementary MOS) technology on p-type Si (p-Si) wafers, the p-channel MOS transistor (pMOST) is an n-well and contains three p/n junctions (the p+source/n-well, p+drain/n-well and n-well/p-wafer junctions). For the bipolar CMOS (BiCMOS) technology on p-Si wafer with an n-well, with or without an n+Si buried region, the nMOST in hte p-well/n+buried-layer contains the three p/n junctions (the n+source/p-well, n+drain/p-well, and p-well/n-well) and a fourth p/n junction (n-well/p-wafer) which is short-circuited and not used by the DCIV method. 
     The minority carriers (electrons in the p-well of an nMOST), injected by the forward-biased source, drain, or well-body emitter junction, recombine with the majority carriers (holes in the p-well or p-wafer) at the SiO 2 /Si interface under the gate to give the gate-voltage dependent base-terminal current, I B , which is proportional to the density of interface traps under the gate oxide. Because of this gate-voltage dependence, there is no ambiguity on the interface-trap origin of the peaked structures observed in the base terminal current, I B . The ease of the DC base current measurement and its unambiguous interface-trap-density proportionality were leveraged in the recently proposed and demonstrated reliability monitor of transistors underwent channel and substrate hot carriers (CHC and SHC) stress to determine the bias conditions to meet the 10-year circuit TTF OP  criteria. The salient feature of the DCIV method is its tremendously enhanced detection sensitivity from forward-biasing one of the p/n junctions of the MOST structure to serve as the emitter/base junction of the lateral or vertical bipolar-junction transistor (LBJT and VBJT) in order to inject minority carriers into the base-body well and the SiO 2 /Si interface under the gate-oxide. At an applied forward PN junction voltage of VP N  the minority carrier density is increased by exp(qV PN /kT). Thus at V PN =357.13 mV and kT/q=25.85 mV (T=300K), the sensitivity is increased by exp(qV PN /kT)=exp(357.13 mV/25.85 mV)=exp(13.816)=10 6  over the reverse-biasedjunction-leakage-current method. This memoranda demonstrates the obvious new application of the DCIV method, namely, as the prestress monitor for diagnosis of fabrication technology and device design, which is facilitated by the increasingly higher sensitivity of the new current measurement instruments and meters, from 1 pA in HP4145B to 1 fA in HP4156B and going down to 0.1 fA (100 aA) and 0.01 fA (10 aA=60 electrons per second) resolutions in off-the-shelf atto-ampere (atto=10 −18 ) electrometers (Keithley 6517A). 
     Results 
     3.1 Transistor Used 
     The data presented here were taken on silicon MOS transistors of the latest two technology generations: the advanced sub-0.25-micron and production 0.35-micron technologies, with ˜3 nm and ˜5 nm gate oxides as defined in Table 14 on page 46 of the December-1997 edition of the SIA Semiconductor Technology National Roadmap. Both were fabricated using the 0.35-micron CMOS technology on 8-inch 50-ohm-cm (2.5×10 14  boron/cm −3 ) p-type wafers with ion-implanted source, drain and well junctions and 1-5×10 17  cm −3  well-impurity concentration at the SiO 2 /Si interface. Transistors from each generation with two drawn gate-width/channel-length ratios were measured in order to also illustrate the application of the scaling law to the DCIV methodology: W/L (μm/μm) 12.5/12.6 and 12.5/0.40 for the sub-0.25-micron and 20/20 and 20/0.4 for the 0.35-micron technologies. The cross-sectional view of the NMOST and pMOST are shown in FIGS.  23 ( a ) and ( b ). 
     3.2 Measurement Instrumentation 
     The DCIV data were taken using a HP4156A (1 fA sensitivity) or a custom stress-and-measure (SAM) station consisting of a 19-inch rack with rack-mounted and programmable (via IEEE-488 bus) digital voltage sources, microvolt and femto-atto-ampere meters, scanners, and low-leakage Reed relays. The HP4156A and SAM station are controlled via the IEEE488 bus by FORTRAN programs running on a MicroVAX-2 minicomputer running Open-VMS 5.5-2 operating system. The data are stored and analyzed in a DECNETed VAX-4096 workstation. The 8-inch test-transistor wafers were probed by a donated wafer probe station (WPS) modified by us for manual operation. Low-noise cable-and-wiring (CAW) practice is followed to connect the WPS to the HP4156A or SAM. The WPS has no temperature control, thus, offset currents arisen from contact-potential-differences of the various metal/metal junctions of the CAW connectors at different temperatures must be subtracted. This subtraction is easily and rather accurately made by software during data analysis or plotting when the minute residual ground-loop currents (1-10 fA) become appreciable compared with the measured base and gate currents. 
     3.3 Lateral BJTs 
     Experimental results and elementary device-material-physics based explanation are given in this section (3.3) for prestress data taken in the lateral BJT bias configurations. Results from the vertical BJT bias configurations are given in the following subsection (3.4). More advanced and detailed explanations are given in later sections. 
     3.3.1 Base-Recombination Current versus Gate Voltage 
     FIGS.  24 ( a ) and ( b ) show the prestress drain-emitter I B −V GB  (SE-DCIV) in lines measured on the long-channel (12/12) nMOSTs and pMOSTs in the drain-emitter and source-emitter forward-bias voltage range (,V DB , and ,V SB ,=V PN ) of 200 to 400 mV. FIGS.  25 ( a ) and ( b ) show the corresponding data for the short-channel (12/0.4) nMOST and pMOST. The following conclusions can be deduced from these four figures. Each is given an industrial-application-specific subsection title based on elementary material-and-device physics. 
     331A Detection of Source-Drain-Engineering Design Symmetry 
     The nearly coincidence of the entire DE-DCIV and SE-DCIV curve at each forward bias level, for both the long and short nMOSTs and pMOSTs, indicates that the dopant impurity concentration profile of the drain and source junction are identical in this transistor device design. (The fine structure differences in these four figures reveal process-residual and macroscopic-microscopy inhomogeneities which will be described later on imperfection monitoring and process-technology transistor-design diagnosis.) 
     331B Scaling Law of the Baseline Current 
     The I B  baselines (I B-baseline ) of the long nMOST are nearly identical to those of the short nMOST at each DE or SE forward bias voltage. This identity or non-scaling is observed also in the long and short pMOSTs. The independence of the I B-baseline  on the channel length is expected since this current arises from recombination in the well and junctions space-charge regions (JSCR&#39;s) outside of the gate-oxide covered channel. 
     331C Monitoring Back Contact Quality of pn-Junctionless Well Structure 
     The I B-baseline  at 200 mV forward drain or source bias is 10-times smaller in the pMOSTs (10 fA) than the nMOSTs (100 fA). The larger nMOST current arises from the recombination at the p-wafer/gold-metal back contact in the nMOST. This ‘infinite’ recombination velocity interface is shielded by the n-well/p-wafer junction in the pMOST˜ Thus, if this S=∞ contact is shielded by a low/high p-wafer/p+implant ‘back surface field’ junction in the nMOST to prevent the minority carriers (electrons) from reaching the S=∞ p-wafer/gold-metal interface, the large nMOST baseline current could be significantly reduced. Thus, this I B-baseline  serves as a monitor on fabrication technology and transistor design of (i) the back-contact, (ii) the p-well/p-wafer low/high junction, and (iii) the n-well/p-wafer n/p junction and its surface oxide passivation. Although the numerical example just described is at the femto-ampere range, the current level can be easily increased to the pico-ampere range by increasing the forward bias in order to facilitate factory applications, such as the 3 pA and 30 pA values measured at 400 mV forward bias illustrated in these four figure parts. 
     331D Scaling Law and Applications of Recombination at Interface Traps in the Channel 
     The I B-peak  (defined as I B-peak  h I B-peak −I B-baseline ) scales according to the channel length and provides further details on the drain-source junction impurity profiles. For the two channel lengths, the geometrical I B-peak  ratio is 12.60/0.40=31.5. At 400 mV forward bias (or any of the other four lower voltages), the I B-peak  ratios are 37 pA/1.03 pA=35.9 (nMOSTs) and 106 pA/1.7 pA-62 (pMOST). 
     There are several conclusions on transistor design and fabrication technology which are revealed by leveraging this undesirable current, I B-peak , from recombination of the minority carriers injected by the forward-biased p/n junction with the majority carriers of the well or wafer at the fabrication-residual interface traps under the gate oxide. 
     331D1 Location of the Interface Traps 
     The approximate scaling means that recombination must occur at the residual interface traps in the middle channel region (MCR) and not in the drain and source emitter junction space-charge-regions (DE-JSCR and SE-JSCR). 
     331D2 Process Controlled Lateral Interface Trap Distribution 
     The absence of the contribution to I B  from the JSCR&#39;s can be because these traps in the DE-JSCR and SE-JSCR were inactivated by hydrogenation of the Si 2  and SiO 2  dangling bonds during the final-wafer-anneal in hydrogen to form the electrically inactive Si:H and SiO:H because the dangling bonds in the JSCR&#39;s are closer to the hydrogen sources in metal/drain and metal/source contact regions. 
     331D3 Quantum Density of States of Interface Traps 
     The absence of JSCR contributions can also be due to interface trap energy levels far from the midgap and the absence of midgap levels. Actually two peaks and broadened peaks were observed suggesting contributions from both the MCR and the JSCR locations and/or many energy levels from many species of interface traps. The one-energy-level Shockley-Read-Hall (SRH) recombination-rate theory, modified for recombination of injected minority carriers at interface traps, shows the I B-MCR  α exp(qV/nkT) with n=1.00 when V PN &lt;˜400 mV and n=2.00 when VPN&gt;˜400 mV and a rather small transition range of V PN  (V PN &lt;˜4kT/q or I B ˜one decade) where 1&lt;n&lt;2. Thus, if there is a large V PN  range (more than˜two decades of I B ) over which n is a constant between 1 and 2 but not equal to 1 or 2, then there must be a lateral or y-dependent variation of the injected minority carrier concentration at the SiO 2 /Si interface between the drain and source junction. This could not be distinguished from the contribution from the JSCRs, I B-JSCR , whose n factor is between 1 and 2 over many decades of I B  and n is not equal to 1.0 or 2.0, until V PN  is sufficiently high (V PN &gt;˜400 mV) that the contribution from the quasi-neutral regions (QNRs) of the base-well-substrate regions, I B-QNR  (n=1.00), is ten times or more larger than I B-JSCR . 
     331D4 True Channel Length and Lateral Source-Drain Diffusion Distance 
     The slightly larger experimental ratio I B-PEAK  (L=12.6 μm)/I B-PEAK  (L=0.40 μm)=35.9 compared with the drawn ratio, 31.5, suggests a better way to measure the diffusion of the drain and source impurity into the channel. The effective channel length is then given by (31.5/35.9)×(0.40)=0.877×0.40=0.35 μm which is consistent with (or accidentally equal to) the 0.35-micron technology employed here to fabricate the transistors. This gives a lateral n+impurity diffusion of (0.40-0.35)/2=0.025 μm=250A which is insignificant in the L=12.6 μm. The p-channel length is (31.5/62)×(0.40)=0.203 μm and the boron lateral diffusion distance is (0.40-0.20)/2=0.050 μm=500 □. 
     331D5 Delineation of Process Variables 
     The much larger experimental pMOST I B-PEAK  ratio (62) could arise from the following possible causes: 
     331D5A the cumulated p+boron (Dt) ½  along the SiO 2 /Si interface was larger than that of the n+As or n+P from process temperature and time differences and from other fundamental and impurity-profile-difference reasons not accounted for in the process design models such as 
     331D5B the faster SiO 2 /Si interfacial diffusion of the p+drain/p+source boron into the n-well than the arsenic or phosphorus of the n+drain/n+source, and 
     331D5C the As or P concentration on the n-well surface of the pMOST could be too low which would further increase the lateral diffusion distance of the boron into the n-well, or 
     331D5D the enhancement of the boron diffusivity by the higher piled-up As or P surface concentrations at the SiO 2 /Si interface. 
     All of these possibilities could be included in the computer-aided process models. However the submicron channel length cannot be easily measured by conventional semiconductor distance measurement methods because of the very small surface distances. The above IB-PEAK method gives an unambiguous and easy solution. 
     331E Junction Tunneling at Gate-Covered p/n Junction Perimeter 
     The rapid exponential rise of I B  with increasing accumulation ,V GB , signifies recombination of the drain-source majority carriers (electrons in n+drain of nMOST with the accumulation-surface-channel majority carriers (holes in the p-well&#39;s surface accumulation layer) via elastic (or even inelastic—phonon-assisted) tunneling transition of the n+drain electrons into the p-well holes. This tunneling pathway has a very sharp onset or threshold, V GB-tunnel-p/n ≡V GB-ptn , at the point when E V-channel  at the SiO 2 /Si interface is pulled up (nMOST) or down (PMOST) by the applied gate voltage to line up with E C-drain . The magnitude of this threshold gate voltage is affected by the amount of the forward voltage applied to the p/n junction, as indicated by the discernible shift of V GB-ptn  with V DB  or V SB  shown in the four figures. The threshold is very sharp indeed even at room temperatures because the thermal distribution of the carriers, ˜2kT/q=50 mV, is rather small compared with V GB-ptn  which is of the order of 1000 mV. The four figures also show that V GB-ptn  is independent of the channel length and is V GB =˜+0.5V for the two pMOSTs and −1.5V for the two nMOSTs at ,V DB , or ,V SB ,=200 mV. There are several monitoring and diagnostic applications of this p/n junction tunneling recombination current described below. 
     331E1 Tunneling Threshold Gate Voltage 
     The tunneling threshold gate voltage is determined by surface energy band bending qY s-tunnel  required to cross drain conduction and channel valence band edges, E C-drain  and E V-channel , at the SiO 2 /Si interface. This is given by                    Y     S   -   tunnel       =.            E   G     /     q   .     -     V   bi                           (   surface   )                 =.       E   G     /     q   .     -     (     kT   /   a     )                             log   10          (       N   DD            P   BB     /     n   I   2         )                                                 
     which provides a design criteria on the standby current in the subthreshold or off range. 
     331E2 Sensitive Surface Impurity Concentration Monitor 
     The very strong exponential dependence of I B-ptn  on barrier thickness or dopant impurity concentration provides an extremely sensitive way to monitor the surface concentration of the well impurity at the SiO 2 Si interface, such as that due to the retrograded well-impurity-profile designed to prevent drain-to-source punch-through at large (reverse-biased) drain-junction voltages. The nearly equal threshold of the 12.6 and 0.4 micron channels indicates that the lateral impurity profile is not altered significantly when the channel is shortened from 12.6 micron to 0.4 micron. 
     The observed difference between the pMOST (+0.5V) and the nMOST (−1.5V) is consistent with large drop of the boron surface concentration of the p-well in the nMOST and the pile-up of the phosphorus or arsenic surface concentration of the n-well in the pMOST. Thus, for the nMOST, the lower boron surface concentration in the p-well would give a thicker perimeter JSCR at the Sio 2 /Si interface and require a larger accumulation gate voltage to narrow the thickness of the perimeter JSCR sufficiently to start tunneling. In addition, the retrograde and pileup impurity surface concentrations at the poly-Si/SiO 2  and SiO 2 /Si interfaces would give an additional gate/well workfunction difference between the nMOST and pMOST which would also add toys-tunnel. 
     331E3 Monitoring Microscopic Inhomogeneities 
     The gate-voltage-dependent p/n junction perimeter tunneling current is such a strong exponential function of the local barrier thickness of the p/n junction that minute macroscopic-microscopic variations along the junction perimeter (z-direction) are amplified tremendously. The observed small source-drain differences of the I B  in the accumulation-tunneling range shown in the four figures could be due to perimeter variations of 
     331E3A the impurity concentration at the Sio 2 /Si interface, 
     331E3B oxide and interface traps and charges and 
       331 E3C oxide thickness between the source and the drain within one transistor and among transistors on the same and different sites/dies on each wafer, and inter-wafer variations. 
     Small long-short-channel differences of the I B −V GB  in the accumulation range are also evident in the four figures and on other sites of this wafer and on other wafers, suggesting the presence of unintentional microscopic and macroscopic technology-residual-random imperfections and nonuniformities across the wafer and between wafers. 
     331F The clearly visible I B-peak  superimposed on the rising I B-ptn  at about x0.5Vx beyond the V GB-ptn  threshold, as displayed in the four figures, are listed below: 
     342A Minority Carrier Injection from Inversion Channel into Base Well 
     This is clearly indicated in FIG.  32 ( b ) for the 12/12-3 nm nMOST by the distinct baseline current step on the two sides of the main peak at V GB-peak =−0.4V. On the inversion side of the p-well (V GB &gt;V GI =−0.3V where U S =U F ), I B-inv =106.788 pA, while on the inversion side (V GB &lt;−1.0V where U S =2U F ) I B-inv =70.036 pA. This difference is a geometrical effect from the larger n-emitter area when the p-well surface is inverted to n-channel which is connected to the n+drain and n+source. The electron-emitter area is increased by 106.788 pA/70.036 pA −1.5248 which is almost exactly that predicted by the geometrical dimension of L=12.60 lm which gives 3L/2L=1.5 from the assumption that the drain and source junctions and the channel each has an area of L×W, thus, (As_A D + AC )/A S +A D )=3LW/2LW=1.5. 
     The minority carrier injection feature from the inverted channel is not evident in the TE-DCIV data of the 20/20 and 20/0.04 5 nm-pMOST in FIG.  32 ( a ) which actually shows that I B-inv &lt;I B-acc . The reason is that the difference is masked by the large p/n junction tunneling current in the accumulation range which increases I B  much above its accumulation baseline value, I B-acc . The causes of the higher p/n junction tunneling current with a lower tunnel-onset gate voltage in pMOST [V GB-ptn ˜+0.5V in FIG.  32 ( a )] than that in the nMOST [V GB-ptn˜− 1.5V in FIG.  32 ( b )] were discussed in subsection 331E and its subsections on the DE-DCIV and SE-DCIV bias configurations. The well-dopant-impurity profile or surface concentration at the SiO 2 /Si interface was the cause: retrograded boron surface concentration in the p-well of the nMOST is lower than the graded phosphorous or arsenic surface concentration in the n-well of the pMOST making the perimeter JSCR under the gate thicker in nMOST and its p/n junction tunneling onset gate voltage higher (−1.5V). In FIG.  32 ( a ) is shown the 1.5×geometrical extrapolation of the I B-acc  at the 200 mV forward bias voltage as a broken line, I B-acc =29 fA.