Abstract:
A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.

Description:
FIELD OF INVENTION 
     This application is related to machine resets and latches. 
     BACKGROUND 
     Computer processor resets may be performed by distributing a reset signal to each state element, logic cone or the like, to clear the current state. This may be done at initialization so that each state element is at a known state. Scan chains, which may be used to detect manufacturing defects in integrated circuits, may also be used to reset the initial state of a machine such as a central processing unit. Scan chains, however, may interact with different parts such as the array. If the array has a stuck-at fault, then this fault may be propagated onto the scan chain and may prevent debug, repairability, or resetting the machine or part. 
     SUMMARY OF EMBODIMENTS 
     A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is provided. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been tri-stated due to the stuck-at zero fault. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an embodiment of a glitch latch; 
         FIG. 2  is an embodiment of a scannable latch of a glitch latch; 
         FIG. 3  is a timing diagram for the glitch latch and scannable latch of  FIGS. 1 and 2 , respectively, with a stuck-at zero fault; 
         FIG. 4  is an example embodiment of a fault tolerant scannable glitch latch; 
         FIG. 5  is an example embodiment of a scan circuit of a fault tolerant scannable glitch latch; 
         FIG. 6  is an example timing diagram for a fault tolerant scannable glitch latch with no faults; and 
         FIG. 7  is an example timing diagram for a fault tolerant scannable glitch latch with a stuck-at zero fault. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The scan chain is a serial chain that connects all state elements or nodes in a machine such as a central processing unit and allows all state elements to be resettable and in particular, to be reset to a known state. However, as shown herein, the scan chain working with a standard glitch latch is susceptible to stuck-at faults. Stuck-at faults, for example, may provide a value of zero/one when the value is supposed to be one/zero. Since the scan chain is a serial chain, the stuck-at fault may propagate down the chain. This prevents proper debug, reset and repair of the machine or part. For example, during a logic test a value may be shifted into the machine through the scan chain to reset and put the machine into any state. The machine is stopped after running several cycles and the data is captured that reflects the current state of the machine. If a stuck-at fault exists on the scan chain, then the resulting scan capture will be overwritten by the stuck-at fault when shifting the captured data out of the machine. 
     Described herein is a fault tolerant scannable glitch latch that may prevent stuck-at faults from propagating onto a scan chain and enable proper reset, array repair and debug. The fault tolerant scannable glitch latch may prevent stuck-at zero faults from propagating through a scannable glitch latch and creating a stuck-at fault on the scan chain. Scan chains together with the fault tolerant scannable glitch latch, therefore, may be used to reset the machine without impacting debug and repairability, enabling the machine to be initialized to a known state without a reset signal having to be distributed to each state element. A faulty array may be properly repaired and reset using the scan chain even in the presence of a stuck-at zero fault. 
       FIG. 1  is a standard glitch latch  100 . Glitch latch  100  includes an input circuit  110  that may be electrically and/or operatively connected to a scannable latch  120  and a logic circuit  130 . 
     Input circuit  110  includes a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (PMOS) transistor  112  having a source connected to supply voltage (V DD ), a gate connected to a super-bitline input (D_F) and a drain connected to a drain of n-channel MOSFET (NMOS) transistor  114 . The NMOS transistor  114  has a gate connected to a clock signal (CLK) and a source connected to a drain of a NMOS transistor  116 . The NMOS transistor  116  has a gate connected to D_F and a source connected to ground (Vss). A state node (qf) is situated between the drain of PMOS transistor  112  and the drain of NMOS transistor  114 . 
     The scannable latch  120  has inputs for the CLK signal, the D_F signal (at input CLK_B), the state node (qf), a scan clock  1  signal (SC 1 ) and scan clock  2  signal (SC 2 ). It also has a scan data input (SDI) for scan data input signal (SDIX) and a scan data output (SDO) for scan data output signal (SDOX). The SDOX is used to connect the serial scan shift chain but is otherwise inoperative during normal operation. 
     The logic circuit  130  includes an inverter  132  having state node (qf) as an input and an output connected to one input of a logical Not And (NAND) gate  134 . A second input of the NAND gate  134  is tied to D_F. The logical output of the NAND gate  134  is the signal QB, which is the data output of the glitch latch  100  during normal operations. 
       FIG. 2  is a schematic of the scannable latch  120 . Scannable latch  120  has a master scan latch  210 , a slave scan latch  212  and an output circuit  214 . Master scan latch  210  includes a PMOS transistor  216  having a source connected to V DD , a gate connected to a SDI input, and a drain connected to a source of PMOS transistor  218 . The PMOS transistor  218  has a drain connected to a drain of NMOS transistor  220  and a gate connected to a SC 1  signal via an inverter  224 . The NMOS transistor  220  has a gate connected to a SC 1  signal and a source connected to a drain of NMOS transistor  222 . The NMOS transistor  222  has a gate connected to a SDI input and a source connected to ground. Master scan latch  210  further includes a PMOS transistor  224  having a source connected to V DD , a gate connected to the output of inverter  232 , and a drain connected to a source of PMOS transistor  226 . The PMOS transistor  226  has a drain connected to a drain of NMOS transistor  228  and a gate connected to a SC 1  signal. The NMOS transistor  228  has a gate connected to a SC 1  signal via an inverter  224  and a source connected to a drain of NMOS transistor  230 . The NMOS transistor  230  has a gate connected to the output of inverter  232  and a source connected to ground. An input for inverter  232  is obtained from the connection between PMOS transistor  218  and NMOS transistor  220  and the connection between PMOS transistor  226  and NMOS transistor  228 . 
     Slave scan latch  212  includes a PMOS transistor  240  having a source connected to V DD , a gate connected to an output of inverter  232 , and a drain connected to a source of PMOS transistor  242 . The PMOS transistor  242  has a drain connected to a drain of NMOS transistor  244  and a gate connected to a SC 2  signal via an inverter  248 . The NMOS transistor  244  has a gate connected to a SC 2  signal and a source connected to a drain of NMOS transistor  246 . The NMOS transistor  246  has a gate connected to the output of inverter gate  232  and a source connected to ground. Slave scan latch  212  further includes a PMOS transistor  250  having a source connected to V DD , a gate connected to qf, and a drain connected to a source of PMOS transistor  252 . The PMOS transistor  252  has a drain connected to a drain of NMOS transistor  254  and a gate connected to a SC 2  signal. The NMOS transistor  254  has a gate connected to a SC 2  signal via an inverter  248  and a source connected to a drain of NMOS transistor  256 . The NMOS transistor  256  has a gate connected qf and a source connected to ground. A qf_x value may be obtained from the connection between PMOS transistor  242  and NMOS transistor  244  and the connection between PMOS transistor  252  and NMOS transistor  254 . 
     Output circuit  214  includes a PMOS transistor  260  having a source connected to V DD , a gate tied to qf_x, and a drain connected to a source of PMOS transistor  262 . The PMOS transistor  262  has a drain connected to a drain of NMOS transistor  264  and a gate connected to a CLK signal. The NMOS transistor  264  has a gate connected to a CLK_B signal (which is the D_F signal) and a source connected to a drain of NMOS transistor  268 . The NMOS transistor  268  has a gate tied to qf_x and a source connected to ground. An inverter  270  has qf_x as an input and SDO as an output. The state node qf is situated between the drain of PMOS transistor  262  and the drain of NMOS transistor  264 . During a normal scan shift operation, (as explained in greater detail below), CLK is disabled and set to low and CLK_B is set to high. Therefore the state node qf will be driven low when qf_x (also SDO) is high. However, during a stuck-at zero fault scenario, CLK_B is low, and the state node qf will be driven high when qf_x (SDO) is high. Therefore even if the scan data is trying to reset this state element to zero it can&#39;t because the state node is pulled high. 
       FIG. 3  illustrates a scan timing diagram  300  for glitch latch  100  and scannable latch  200  with a stuck-at zero fault at the D_F input. In summary and explained in more detail below, the CLK is disabled and set to low during a scan shift operation. SDIX scans data in via SC 1  and SC 2 . In particular, SC 1  clocks scan data input into the master scan latch  210  and SC 2  clocks scan data input from the master scan latch  210  into the slave scan latch  212 . The data output, QB, is driven high due to the stuck-at zero fault at the D_F input. The scan data output, SDOX, is driven high due to the stuck-at zero fault at the D_F input except when SC 2  is asserted. The state node, qf, is driven high due to the stuck-at zero fault at the D_F input. 
     The standard glitch latch  100 , shown in  FIGS. 1 and 2  and operationally in  FIG. 3 , is susceptible to stuck-at zero faults. A stuck-at zero fault being a situation when a circuit, such as a memory array or the like, has an element that is defective and outputs a zero when a one is supposed to be present. Operationally, the standard glitch latch  100  shown in  FIGS. 1 and 2  allows a stuck-at zero fault to propagate through the glitch latch  100  when a shift scan operation is enabled. During a scan shift operation, the array is in a precharge state (i.e., the array superbit lines are set to high) and the clock, CLK, is low. This combination of inputs tri-states input circuit  110 , meaning that input circuit  110  does not actively drive a voltage onto state node qf during a scan shift operation when no stuck-at zero fault is present. This allows the output circuit  214  to drive data from the slave scan latch onto the state node qf, thereby initializing the state through use of the scan chain. In particular, SDIX scans data in via SC 1  and SC 2  and an inverted version is presented at the state node. In effect, data that may be used to reset the state node is scanned and shifted onto the scan chain using SC 1  and SC 2 . If a stuck-at zero fault exists on the array, then the stuck-at zero fault is present at the D_F input. If a stuck-at zero fault exists, then D_F will be zero even when D_F is supposed to be at a precharged high value. For example, during a scan operation, PMOS transistor  112  is supposed to be off. However, in the case of a stuck-at zero fault, the PMOS transistor  112  will be on. The state node (i.e., qf) will be driven to V DD . Therefore even if the scan data is trying to reset this state element to zero it can&#39;t because the state node is pulled high. The state node, therefore, may not be reset to the desired value and may propagate to the rest of the scan chain as it will be serially shifted downstream from this point. The downstream state elements will be reset to a value based on the stuck-at fault rather than the intended value that was applied on the scan chain. 
     As shown in  FIG. 2 , the stuck-at zero fault prevents a path to ground for the state node during scan shift since CLK_B is zero rather than its intended value of one. This results in the state node being driven to a one thru PMOS device  112  and prevents scan data shifted onto node qf_x from being able to drive state node qf low through output circuit  214 . 
       FIG. 4  is an example embodiment of a fault tolerant scannable glitch latch  400 . Fault tolerant scannable glitch latch  400  includes an input circuit  410  that may be electrically and/or operatively connected to a scannable latch  420  and a logic circuit  430 . 
     Input circuit  410  includes a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (PMOS) transistor  412  having a source connected to supply voltage (V DD ), a gate connected to scan shift enable (SSE) and a drain connected to a source of PMOS transistor  414 . The PMOS transistor  414  has a gate connected to a super-bitline input (D_F) and a drain connected to a drain of n-channel MOSFET (NMOS) transistor  416 . The NMOS transistor  416  has a gate connected to a clock signal (CLK) and a source connected to a drain of a NMOS transistor  418 . The NMOS transistor  418  has a gate connected to D_F and a source connected to ground (Vss). A state node (qf) value is obtained from the connection between PMOS transistor  414  and PMOS transistor  416 . The D_F input to the fault tolerant scannable glitch latch  400  may be held in precharge during scan. This allows scan data to propagate through the fault tolerant scannable glitch latch  400  when a scan is enabled. 
     The scannable latch  420  has inputs for the CLK signal, the SSE signal, the D_F signal (CLK_B), the state node (qf), a scan clock  1  signal (SC 1 ) and scan clock  2  signal (SC 2 ). It also has a scan data input (SDI) for scan data input signal (SDIX) and a scan data output (SDO) for scan data output signal (SDOX). 
     The logic circuit  430  includes an inverter  432  having state node (qf) as an input and an output connected to one input of a logical Not And (NAND) gate  434 . A second input of the NAND gate  434  is tied to D_F. The logical output of the NAND gate  434  is the signal QB. 
       FIG. 5  is an example embodiment of the scannable latch  420 . Scannable latch  420  has a master scan latch  510 , a slave scan latch  512  and an output circuit  514 . Master scan latch  510  includes a PMOS transistor  516  having a source connected to V DD , a gate connected to a SDI input, and a drain connected to a source of PMOS transistor  518 . The PMOS transistor  518  has a drain connected to a drain of NMOS transistor  520  and a gate connected to a SC 1  signal via an inverter  524 . The NMOS transistor  520  has a gate connected to a SC 1  signal and a source connected to a drain of NMOS transistor  522 . The NMOS transistor  522  has a gate connected to a SDI input and a source connected to ground. Master scan latch  510  further includes a PMOS transistor  524  having a source connected to V DD , a gate connected to the output of an inverter  532 , and a drain connected to a source of PMOS transistor  526 . The PMOS transistor  526  has a drain connected to a drain of NMOS transistor  528  and a gate connected to a SC 1  signal. The NMOS transistor  528  has a gate connected to a SC 1  signal via an inverter  524  and a source connected to a drain of NMOS transistor  530 . The NMOS transistor  530  has a gate connected to an output of inverter  532  and a source connected to ground. An input for inverter  532  is obtained from the connection between PMOS transistor  518  and NMOS transistor  520  and the connection between PMOS transistor  526  and NMOS transistor  528 . 
     State element circuit  512  includes a PMOS transistor  540  having a source connected to V DD , a gate connected to an output of inverter  532 , and a drain connected to a source of PMOS transistor  542 . The PMOS transistor  542  has a drain connected to a drain of NMOS transistor  544  and a gate connected to a SC 2  signal via an inverter  548 . The NMOS transistor  544  has a gate connected to a SC 2  signal and a source connected to a drain of NMOS transistor  546 . The NMOS transistor  546  has a gate connected to an output of inverter gate  532  and a source connected to ground. Input circuit  512  further includes a PMOS transistor  550  having a source connected to V DD , a gate connected to qf, and a drain connected to a source of PMOS transistor  552 . The PMOS transistor  552  has a drain connected to a drain of NMOS transistor  554  and a gate connected to a SC 2  signal. The NMOS transistor  554  has a gate connected to a SC 2  signal via an inverter  548  and a source connected to a drain of NMOS transistor  556 . The NMOS transistor  556  has a gate connected qf and a source connected to ground. A qf_x value may be obtained from the connection between PMOS transistor  542  and NMOS transistor  544  and the connection between PMOS transistor  552  and NMOS transistor  554 . 
     Output circuit  514  includes a PMOS transistor  560  having a source connected to V DD , a gate tied to qf_x, and a drain connected to a source of PMOS transistor  562 . The PMOS transistor  562  has a drain connected to a drain of NMOS transistor  564  and a gate connected to a CLK signal. The NMOS transistor  564  has a gate connected to a CLK_B signal (which is the D_F signal) and a source connected to a drain of NMOS transistor  568 . A NMOS transistor  572  is connected in parallel with NMOS transistor  564 , the NMOS transistor  572  having a gated connected to a SSE signal. The NMOS transistor  568  has a gate tied to qf_x and a source connected to ground. An inverter  570  has qf_x as an input and SDO as an output. 
     Operationally, the fault tolerant glitch latch  400  shown in  FIGS. 4 and 5  prevents a stuck-at zero fault from propagating through the fault tolerant glitch latch  400 . The scan shift enable signal controls a switch connected in series with the data input switch such that a stuck-at zero fault is prevented from driving voltage to a state node (i.e., qf) during a scan shift operation. In particular, by connecting the PMOS transistor  412  (a first SSE transistor) in series with the PMOS transistor  414  (the data input or data fault transistor), assertion of the scan shift enable signal during a scan operation turns off the PMOS transistor  412  and prevents the state node from being pulled high even if the PMOS transistor  414  is turned on due to the stuck-at zero fault. The state node therefore can be driven by the scan data. 
     In addition, as shown in  FIG. 5 , by connecting the NMOS transistor  572  (the second SSE transistor) in parallel with the NMOS transistor  564  (the second data input or data fault transistor), assertion of the scan shift enable during the scan operation turns on the NMOS transistor  572  and provides a path for qf to be driven to ground through the scan path when the scan data is low. The state node therefore is driven by the scan data during a scan shift operation and a stuck-at zero fault is operationally transparent. During a non-scan shift operation, SSE is not asserted and the fault tolerant glitch latch  400  functionally behaves as a standard glitch latch. 
       FIG. 6  illustrates a scan timing diagram  600  for the fault tolerant scannable glitch latch  600  with no faults. The SSE is asserted during a scan shift operation and is set to high. During a scan shift operation, the array is in a precharge state (i.e., the array superbit lines are set to high) and the D_F input is high. The CLK is disabled and set to low during a scan shift. SDIX scans data in via SC 1  and SC 2 . In particular, SC 1  clocks scan data input into the master scan latch  510 . SC 2  clocks scan data input from the master scan latch  510  into the slave scan latch  512  and the two outputs QB and SDOX. The state node, qf, also follows the scan data input. 
       FIG. 7  illustrates a scan timing diagram  700  for the fault tolerant scannable glitch latch  600  with a stuck-at zero fault at the D_F input. Again, the SSE is asserted during a scan shift operation and is set to high. During a scan shift operation, the array is in a precharge state (i.e., the array superbit lines are set to high), but due to the stuck-at zero fault, the D_F input is low. As before, the CLK is disabled and set to low during a scan shift. SDIX scans data in via SC 1  and SC 2 . In particular, SC 1  clocks scan data input into the master scan latch  510 . SC 2  clocks scan data input from the master scan latch  510  into the slave scan latch  512  and the two outputs QB and SDOX. Although QB is stuck-at one due to the stuck-at zero fault, the addition of the PMOS and NMOS switches as discussed herein and the assertion of the SSE during the scan shift operation allows qf to be driven by the scan data input. 
     Embodiments of the present invention may be represented as instructions and data stored in a computer-readable storage medium. For example, aspects of the present invention may be implemented using Verilog, which is a hardware description language (HDL). When processed, Verilog data instructions may generate other intermediary data, (e.g., netlists, GDS data, or the like), that may be used to perform a manufacturing process implemented in a semiconductor fabrication facility. The manufacturing process may be adapted to manufacture semiconductor devices (e.g., processors) that embody various aspects of the present invention. 
     Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements. The methods or flow charts provided herein may be implemented in a computer program, software, or firmware incorporated in a computer-readable storage medium for execution by a general purpose computer or a processor. Examples of computer-readable storage mediums include a read only memory (ROM), a random access memory (RAM), a register, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks, and digital versatile disks (DVDs). 
     Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, any other type of integrated circuit (IC), and/or a state machine. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions (such instructions capable of being stored on a computer readable media). The results of such processing may be maskworks that are then used in a semiconductor manufacturing process to manufacture a processor which implements aspects of the present invention.