Abstract:
A linear programmable switch-capacitance gain amplifier (PGA) is described. The PGA divides the dB-gain curve into several parts by the concept of piece-wise linearity, and then simultaneously executes the dB-linear gain adjustment of MSB and the LSB at the same gain stage. Present invention achieves the PGA dB-linearity by setting up every capacitance of the sampling capacitor array and the holding capacitor array, then arranging the sampling capacitor array and the holding capacitor array by coordinating the switching of the capacitor switches.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention is related to a gain amplifier, in particular, to a linear programmable switch-capacitance gain amplifier (PGA). 
   2. Description of Related Art 
   A commonly used linear programmable switch-capacitance gain amplifier (PGA) employs 
             1   +   x       1   -   x           
for approximating operations. In case of applications requiring wider range of adjustment and better precision, the entire linear programmable switch-capacitance gain amplifier will be divided into two or more parts, as shown in  FIG. 7 , which illustrates an architecture of a prior art linear programmable switch-capacitance gain amplifier using 2 parts of operation, as well as shown in  FIG. 8 , which illustrates an architecture of a prior art linear programmable switch-capacitance gain amplifier using several parts of operation. At the stage of Least Significance Bits (LSB), it generally uses the approximately linear
 
             1   +   x       1   -   x           
for implementing 0-6 dB, from which the derived maximum error will be about −0.09 dB, as shown in  FIG. 9 , which shows a diagram representing the error in a prior art linear programmable switch-capacitance gain amplifier. However, even though the error is of small magnitude, there exists a disadvantage in that such a linear programmable switch-capacitance gain amplifier needs at least one more gain stage.
 
   SUMMARY OF THE INVENTION 
   In view of the aforementioned disadvantage, the present invention is, by means of allowing multiplication/division relation between sampling capacitors and holding capacitors at the same gain stage, to realize gain (dB)=sampling capacitor CS (dB)−holding capacitor CH (dB), so as to be able to accomplish the entire programmable switch-capacitance gain amplification at the same gain stage. 
   To achieve the objective described supra, the present invention provides a linear programmable switch-capacitance gain amplifier, which includes a first sampling capacitor array, a first holding capacitor array, an operational amplifier, a second sampling capacitor array and a second holding capacitor array. 
   One end of the above-mentioned first sampling capacitor array is connected to a positive voltage input through a first switch, and the first sampling capacitor array consists of: a first sampling capacitor; and a plurality of second sampling capacitance switch sets, which are mutually connected in parallel, each having a second sampling capacitor and a switch, whereas the second sampling capacitor and the switch are connected in series; wherein the first sampling capacitor and these second sampling capacitance switch sets are connected in parallel. 
   One end of the above-mentioned first holding capacitor array is connected to the opposite end of the end at which the first sampling capacitor array connects to the positive voltage input, and connected to a bias voltage through a second switch, whereas the other end of the first holding capacitor array is connected to a positive voltage output through a third switch, and connected to the bias voltage via a fourth switch, wherein the first holding capacitor array consists of: a plurality of first holding capacitance switch sets, which are mutually connected in parallel, each having a first holding capacitor and a switch, in which the first holding capacitor and the switch are connected in series. 
   The positive input of the aforementioned operational amplifier is connected between the first sampling capacitor array and the first holding capacitor array, and connected to the bias voltage through the second switch, whereas the negative input of the operational amplifier is connected to the bias voltage via a fifth switch, and the negative voltage output of the operational amplifier is, via the third switch, connected between the first holding capacitor array and the fourth switch, and the positive voltage output of the operational amplifier is connected to the negative voltage output of the operational amplifier through a sixth switch. 
   One end of the above-mentioned second sampling capacitor array is connected to a negative voltage input via a seventh switch, and connected between the first switch and the first sampling capacitor array via an eighth switch, whereas the other end of second sampling capacitor array is connected between the fifth switch and the negative voltage input of the operational amplifier, wherein the second sampling capacitor array includes: a third sampling capacitor; and a plurality of fourth sampling capacitance switch sets, which are mutually connected in parallel, each having a fourth sampling capacitor and a switch, wherein the fourth sampling capacitor is connected with the switch in series; in which the third sampling capacitor and those fourth sampling capacitance switch sets are connected in parallel. 
   One end of the above-mentioned second holding capacitor array is connected to the opposite end of the end at which the second sampling capacitor array connects to the negative voltage input, and connected between through the fifth switch and the negative voltage input of the operational amplifier, whereas the other end of the second holding capacitor array is connected to the negative voltage output through a ninth switch, and connected to the bias voltage via a tenth switch, wherein the second holding capacitor array consists of: a plurality of second holding capacitance switch sets, which are mutually connected in parallel, each having a second holding capacitor and a switch, in which the second holding capacitor and the switch are connected in series. 
   In order to further understand the techniques, means and effects the present invention takes to achieve the prescribed objectives, the following detailed descriptions and appended drawings are hereby referred, such that, through which, the purposes, features and aspects of the present invention can be thoroughly and concretely appreciated; however, the appended drawings are merely provided for reference and illustration, without any intention to be used for limiting the present invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a curve chart of Maximum Significance Bits (MSB) gain adjustment; 
       FIG. 2  shows a circuit diagram of a general typical switch-capacitance gain amplifier; 
       FIG. 3A  shows a circuit diagram of a linear programmable switch-capacitance gain amplifier according to the present invention; 
       FIG. 3B  shows a time sequence diagram of each switch in a linear programmable switch-capacitance gain amplifier according to the present invention; 
       FIG. 4  shows a transition curve chart of PGA code vs. PGA gain (dB); 
       FIG. 5  shows a representation diagram of errors between the transition curve simulation values and ideal values; 
       FIG. 6  shows a circuit diagram of the single-side linear programmable switch-capacitance gain amplifier according to the present invention; 
       FIG. 7  shows an architecture diagram of a prior art linear programmable switch-capacitance gain amplifier using  2  parts of operation; 
       FIG. 8  shows an architecture diagram of a prior art linear programmable switch-capacitance gain amplifier using several parts of operation; and 
       FIG. 9  shows a representation diagram of error values of a prior art linear programmable switch-capacitance gain amplifier. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring now to  FIG. 1 , in which a curve chart of Maximum Significance Bits (MSB) gain adjustment is illustrated. As shown, the present invention, using a concept of piece-wise linearity, divides first the entire dB gain curve into 2 m  parts, wherein m represents the number of bits in the Maximum Significance Bits (MSB), meanwhile the rest n bits are the Least Significance Bits (LSB), and N represents the total number of bit which equals m+n 
   In general, two gain stages are taken for implementing, in which one stage is responsible for MSB, and the other is for LSB. But this approach will require one more operational amplifier (OPAMP), which occupies usable area and consumes more energy. Hence, the present invention proposes a method of implementing both the MSB and LSB dB-linear gain adjustments at the same gain stage. 
   Since LSB is a smaller part of a code, we are aware that, when x→0, e x ≈1+x, which means we can implement LSB in a fashion of linear increment, while avoiding causing unacceptable errors. In addition, in the MSB part, since it is impossible to implement by means of 
             1   +   x       1   -   x           
because the error resulted might become too big, thus the present invention will, with pre-calculated gains, implement MSB directly by means of switch selections.
 
   Referring now to  FIG. 2 , in which a circuit diagram of a general typical switch-capacitance gain amplifier is shown. When a common switch capacitance gain amplifier  2  is at a sampling phase, the first switch  21 , second switch  22 , fourth switch  24 , fifth switch  25 , sixth switch  26 , seventh switch  27  and tenth switch  30  are closed (logic 1, high), but the third switch  23 , eighth switch  28  and ninth switch  29  are disconnected (logic 0, low), and at this moment, the sampling capacitor arrays C 221 , C 222  are respectively connected to positive voltage input VIN+ and negative voltage input VIN− on one end, while on the other end thereof are connected to the bias voltage VBIAS; the holding capacitor arrays C 231 , C 232  are connected to the bias voltage VBIAS on two ends; the operational amplifier forms an open-loop status, whose positive output voltage end VOUT+ and negative output voltage end VOUT− are short circuited together by means of the sixth switch  26 . 
   When at the holding phase, the first switch  21 , second switch  22 , fourth switch  24 , fifth switch  25 , sixth switch  26 , seventh switch  27  and tenth switch  30  are disconnected (logic 0, low), whereas the third switch  23 , eighth switch  28  and ninth switch  29  are closed (logic 1, high), and at this moment, the charges inside the sampling capacitor arrays C 221 , C 222  will transfer to the holding capacitor arrays C 231 , C 232 . Therefore, the operational amplifier  240  may obtain an amplification output of 
                 VOUT   +     -     VOUT   -       =         C   ⁢           ⁢   221       C   ⁢           ⁢   231       *     (       VIN   +     -     VIN   -       )         ,         
according the principle of conservation of charge.
 
   Referring next to  FIG. 3A , in which a circuit diagram of a linear programmable switch-capacitance gain amplifier according to the present invention is shown, and concurrently also referring to  FIG. 3B , therein a time sequence diagram of each switch in a linear programmable switch-capacitance gain amplifier according to the present invention is illustrated. When the first switch  31 , fourth switch  34 , sixth switch  36 , seventh switch  37  and tenth switch  40  are closed (logic 1, high) subject to the control of the first clock signal Φ 1 , the analog input signals of the positive voltage input VIN+ and the negative voltage input VIN− will be stored inside sampling capacitor arrays C 321  (the first sampling capacitor array) and C 322  (the second sampling capacitor array) in the form of charges. Charges in the holding capacitor arrays C 331 , C 332  will be zero (0), since both ends thereof are connected to the bias voltage VBIAS of the same potential. Next, before the disconnection (logic 0, low) of the first switch  31 , fourth switch  34 , sixth switch  36 , seventh switch  37  and tenth switch  40  subject to the control of the first clock signal Φ 1 , the second switch  32  and fifth switch  35  will be cut and become disconnected (logic 0, low) subject to the control of the second clock signal Φ 2 , i.e. the conventional so-called bottom sampling approach. At last, the third switch  33 , eighth  38  and ninth switch  39  will be closed (logic 1, high) subject to the control of the third clock signal Φ 3 , transferring the charges stored in the sampling capacitor arrays C 321 , C 322  to the holding capacitor arrays C 331 , C 332 , thus generating amplified voltage at the voltage output VOUT, wherein VOUT=VIN*(C 321 /C 331 ) or VOUT=VIN*(C 322 /C 332 ). 
   In the sampling capacitor arrays C 321 , C 322  and holding capacitor arrays C 331 , C 332 , the relations among each capacitor follow the equations as below:
 
 C   n−1 =2 *C   n−2 =4 *C   n−3 = . . . =2 n−1   *C   0   (1)
 
                   C   Hx     =       C   S       10           max   ⁢   _   ⁢   dB     ⁢     _   ⁢   gain       20     ×     x     2   m                     (   2   )                     C   0       C   S       ×     2   n       =         C     H   ⁢           ⁢   0         C     H   ⁢           ⁢   1         -   1             (   3   )               
wherein x=0˜2 m −1, and according to equation (2) it is possible to obtain the relation between the capacitor CHx in the holding capacitor arrays C 331 , C 332  and the capacitor Cs in the sampling capacitor arrays C 321 , C 322 ; Also, according to equation (3), it is possible to obtain the relation between the capacitor C 0  in the sampling capacitor arrays C 321 , C 322  and the Cs.
 
   The gain in the linear programmable switch-capacitance gain amplifier  3  is PGA gain 
               (         2   n     ·   x     +   p     )     =           C   S     +       C   0     ·   p         C   Hx       =         C   S       C   Hx       ·         C   S     +       C   0     ·   p         C   S             ,         
in which p=0˜2 n −1, and x=0˜2 m −1. Next, suppose the PGA gain is taken in dB, then it means that dB_gain can be represented as
 
               (         2   n     ·   x     +   p     )     =       20   ·     log   ⁡     (       C   S       C   Hx       )         +     20   ·     log   ⁡     (     1   +     p   ·       C   0       C   S           )             ,         
and the linear-in-dB gain adjustment transfer curve with piece-wise linear approximation can be thus be obtained.
 
   On the other hand, a binary PGA code is divided into MSB of m bits and LSB of n bits. Here, the binary code of MSB will go through a decoder for decoding, so as to generate the switching that controls the switches (SWHx, x=0˜2 m −1) to which the capacitor CHx (x=0˜2 m −1) in the holding capacitor arrays C 331 , C 332  corresponds; and the binary code of LSB directly controls the switching of switches (SWx, x=0˜n−1) to which the capacitor Cx (x=0˜n−1) in the sampling capacitor arrays C 321 , C 322  corresponds. 
   Therefore, by means of the above-mentioned equations, the present invention implements each capacitance in conjunction with the delicate arrangements of the sampling capacitor arrays C 321 , C 322  and holding capacitor arrays C 331 , C 332 , thus achieving the PGA dB-linearity of the programmable switch-capacitance gain amplifier. Which when compared with a conventional fashion of using sampling capacitor arrays fitted to the holding capacitor array with a constant value then later adjust the capacitances in the sampling capacitor arrays and holding capacitor arrays in the holding stage, this 
             1   +   x       1   -   x           
dB-linear approach indeed offer better precision. Futhermore, one single operational amplifier can accomplish a wide range of programmable switch-capacitance gain amplifier gains (PGA gain), compared with the conventional amplifiers requiring two or more operational amplifiers, the present invention saves more usable area and consumes less energy.
 
   Subsequently, take a 9-bit dB linear gain adjustment for max dB gain of 18.0625 dB for example. 1 LSB=max dB gain/511□0.035 dB. Let&#39;s first assume the number of bits m for MSB is 3, the number of bits n for LSB is 6, and capacitor Cs=5000 fF. From the aforementioned equations, it can be known that, in the holding capacitor arrays C 331 , C 332 , CHO 0 =5000 fF, CH 1 =3855.5 fF, CH 2 =2973.0 fF, CH 3 =2292.4 fF, . . . , CH 7 =810.5 fF, and also, in the sampling capacitor arrays C 321 , C 322 , C 0 =23.2 fF, C 1 =2*C 0 =46.4 fF, C 2 =2*C 1 =92.8 fF, . . . , C 5 =742.4 fF. Placing these data for simulation, it will give the results shown in  FIGS. 4 and 5 , in which  FIG. 4  shows a transition curve chart of PGA code vs. PGA gain (dB), herein the solid line represents simulation results of the above-mentioned data, and the dotted line depicts the ideal result;  FIG. 5  shows a representation diagram of errors between the transition curve simulation values and ideal values. From  FIGS. 4 and 5 , it can be seen that the linear programmable switch-capacitance gain amplifier according to the present invention implements a nearly ideal linear gain curve. 
   Next referring to  FIG. 6 , a circuit diagram of the single-side linear programmable switch-capacitance gain amplifier according to the present invention is shown. The operational principle is, as described supra, the individual capacitances of the sampling capacitor array C 621  and the holding capacitor array C 631  are decided by equations 1, 2 and 3, manipulating the transfers of charges between the sampling capacitor array C 621  and the holding capacitor array C 631  through using the first clock signal (e.g. Φ 1  in  FIG. 3B ) to control the first switch  61  and third switch  63 , the second clock signal (e.g. Φ 2  in  FIG. 3B ) to control the second switch  62 , and the third clock signal (e.g. Φ 3  in  FIG. 3B ) to control the fourth switch  64  and fifth switch  65 . The adjustment of capacitance in the sampling capacitor array C 621  and the holding capacitor array C 631 , also as above illustrated, is performed by letting the binary code of MSB go through a decoder for decoding, so as to control the switching of the switch to which the capacitor CHx (x=0˜2 m −1) in the holding capacitor array C 631  corresponds; whereas the binary code of LSB directly controls the switching of the switch to which the capacitor Cx (x=0˜n−1) in the sampling capacitor array C 621  corresponds, wherein m is the number of bits in MSB, n is the number of bits in LSB. In this way, it is possible to enable the single side linear programmable switch-capacitance gain amplifier  6  to implement a nearly ideal linear gain curve. 
   In summary, the linear programmable switch-capacitance gain amplifier according to the present invention provides the function of achieving the entire programmable gain amplification at the same stage, thus simplifying design works for cost-savings, and also reducing power consumptions, suitable for applications on consumer, portable devices. 
   The above-mentioned descriptions represent merely the preferred embodiment of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alternations or modifications based on the claims of present invention are all consequently viewed as being embraced by the scope of the present invention.