Abstract:
An analogue to digital converter (ADC) of the recirculating type is described. In one embodiment, the ADC is composed of three storage and residual determination units, which, in cooperation with an operational amplifier, and suitable comparator means, are operable to re-present residual signals for analogue to digital conversion. To enhance settling at the beginning of a cycle, the first storage and residual determination unit is used once, with remaining recirculation being conducted between the other two storage and residual determination units. 
     Another embodiment presents a recirculating ADC stage which comprises a plurality of capacitor banks operable to be switched into and out of connection with other components of the ADC stage, in order to recirculate residual values for calculation of further bits of a digital output. Each bank comprises a plurality of capacitors, and cooperating switching means for connecting each bank in turn with the other components. The switching means are controlled by timing signals, wherein the switching means for each capacitor in each capacitor bank interpose the same number of switches between that capacitor and fed-back signals to that capacitor as to other capacitors of that bank.

Description:
FIELD OF THE INVENTION 
   This invention relates to an Analogue to Digital Converter-(ADC), and particularly to a recirculating or algorithmic ADC. 
   BACKGROUND OF THE INVENTION 
   Pipeline ADCs are today commonly used for applications requiring 10 to 16 bits resolution at 1 MHz to 100 MHz sample rates, for example for digitising the outputs of CCD or CMOS linear or area image sensors or for digitising analogue video signals. A basic pipeline ADC includes several stages in cascade. Each stage uses a comparator to extract the most significant bit, and then the stage subtracts an analogue signal corresponding to the extracted bit, and amplifies the remaining residue, for use by the next stage. Commonly, more than one bit per stage is extracted, by using multiple comparators. Also, certain arrangements allow over-ranging of the input of each stage to accommodate comparator offsets so that, provided that each stage subtracts an accurate amount and gives an accurate analogue gain, the eventual digital output conversion remains accurate. These ADCs are commonly implemented in CMOS using switched-capacitor technology. However, other techniques, such as switched current, have also been used. 
   In practice, especially where the input signal amplitude can vary widely, as with an image sensor or communications link, a common implementation has the ADC preceded by an amplifier with controllable gain, termed a Programmable Gain Amplifier (PGA). This gain is often digitally controllable, but may be controlled by other means, such as voltage control or current control in some systems. 
   The PGA is controlled to amplify or attenuate the input signal so that it is of an amplitude that uses up a substantial proportion (as much as practicable) of the full-scale input range of the ADC. In this way the ADC thermal noise referred to the signal source is proportionately kept as low as possible relative to the signal source, and so its impact is minimised; likewise, the signal presented to the ADC is maximised. Thus, using a PGA, it is possible to make use of the full effective resolution of the ADC. 
   So as not to degrade the performance of the ADC, the PGA should be at least as linear as the ADC. The PGA should also be operable to settle linearly and quickly into the input impedance of the ADC, and to maintain this settling behaviour over a wide range of programmed gain values. Again, CMOS switched-capacitor technology is often used for this PGA, though alternatives such as op amp circuits using multiple-tapped resistor ladders, or bipolar multiplier cells or other voltage-controlled amplifiers, are also possible. 
   The PGA op amp can often present greater design challenges than the ADC op amps. It is required to have enough gain-bandwidth to settle accurately in typically half a sample period at maximum gain (say 20 dB or even greater), but has to remain stable when configured with higher feedback factors to give closed loop gain less than unity. It is also necessary for the input-referred noise of the PGA op amp to be low, even when amplifying a small input signal, and the capacitors or resistors around it will be of low impedance to minimise noise. Therefore the operating current will often be as much as all of the amplifiers in the ADC. While the op amps in the ADC also have to settle inside half a sample period, they can be optimised for a fixed closed-loop gain, and will only receive amplified input signals, so can be higher noise and drive higher-impedance circuitry, so power minimisation will be less critical. Also the PGA has to settle to the full resolution of the ADC, whereas the ADC op amps only have to settle to the resolution of the following stage. 
   For example, for a sample rate of 10 Ms/s, the sample period will be 100 ns. Thus, the PGA will need to settle to within the ADC resolution (say 14 bits) in 50 ns, which is half of this sample period. Assuming a single-pole settling model, this implies settling to 10 time constants in 50 ns, i.e. with a time constant of 5 ns, or a closed-loop bandwidth of 30 MHz. If the PGA is set to a gain of 10, this thus requires an op amp with open-loop gain-bandwidth of approximately 300 MHz, but stable at closed loop gain &lt;&lt;1. 
   In practice, allowing for clock under-lap, the available settling time may be less than 50 ns, and slewing, clock injection effects, or other second-order effects may require an even faster op amp. 
   This is inherently more difficult to achieve than in an ADC, which has a closed loop gain of, for example, 2, thus requiring a gain bandwidth of 60 MHz and only needing to be stable for constant gain A=2. 
   An n-bit pipeline ADC extracting one bit per stage requires n separate stages, each including an op amp, comparators, and a switched-capacitor array. This uses significant silicon area, each stage adding to die cost, but these ADCs are often required in high-volume consumer equipment, where manufacturing cost is very important. Also each stage consumes power, whereas many applications such as Digital Cameras are battery-powered portable equipment, so low power is important. Pipeline ADCs extracting more than one bit per stage have fewer stages, but each is more complex, consuming more area and more power per stage, so the net saving in terms of power and area is limited. 
   Thus, it would be desirable to obtain the performance of a pipeline ADC, with improved use of the active area of a solid state device. It would further be desirable to obtain the performance of a pipeline ADC with improved power consumption. 
   In the event that improved use of active area of a solid state device can be achieved, with improved power consumption, it could, in certain circumstances, be desirable to sacrifice this improvement in these performance criteria to the benefit of improved performance in terms of other performance criteria, such as noise, resolution and/or linearity. 
   For a given manufacturing technology, there comes a performance threshold at which it becomes increasingly difficult for a designer to get higher speed or better performance, without consuming a lot of extra power or requiring complicated and area-consuming topologies or requiring exceptional skill and the invention of novel circuit techniques. However, using common 0.35 μm CMOS, it is quite possible for a person reasonably skilled in the art to design an op amp capable of use in implementing an ADC operating up to 30 Ms/s at (say) 12 bits resolution, without hitting this performance threshold. 
   For applications at lower sample rates, say 3 Ms/s, one possibility is to use the same comfortably designed 30 Ms/s amplifier in successive 30 Ms/s clock cycles to implement the processing of successive stages, rather than dedicating an amplifier to each stage, just operating at 3 Ms/s. This results in a circuit architecture similar to cyclic (also termed recirculating, or algorithmic) ADCs. For a given sample rate, this requires faster settling, since all the processing for n stages needs to be squeezed into one sample clock cycle. The main problem is that the PGA now has to drive the input capacitors in a small fraction of the 3 Ms/s sample rate. 
   Examples of circuit designs comparable with specific embodiments from the state of the art will now be described, with discussion of their features, operation and certain disadvantages. 
     FIG. 1   a  shows a switched-capacitor PGA  10  driving a 1-bit per stage switched-capacitor pipeline ADC  20 , extracting 1 bit per stage. One stage  22  of the pipeline ADC is illustrated in detail, and a second stage schematically, it being understood that further stages are to be added to the output to this stage until the desired resolution is reached. 
   The switched capacitor PGA  10  comprises an op amp  12  whose non-inverting input is tied to ground. One terminal of a variable input capacitance Ca 1  is connected to an input on which an input signal Vin is received in use, via a switch Sw 1 . Another switch Sw 3  lies between the same end of the input capacitance Ca 1  and ground. A further switch Sw 4  connects the other terminal of the input capacitance Ca 1  to ground, and a further switch Sw 2  connects that latter terminal to the inverting input of the op amp  12 . 
   In use, switches Sw 1  and Sw 4  close on receipt of a clock signal φ 1 , as marked, and switches Sw 2  and Sw 3  close on receipt of another clock signal φ 2 . 
   The system is driven by these two-phase, non-overlapping clocks φ 1 , φ 2 , whose timing diagrams are illustrated in  FIG. 1   b . Because the clocks are non-overlapping, actions dependent on one of the clock signals being high are completed before actions dependent on the other of the clock signals being high, as the two clock signals are never simultaneously high. For convenience in the following description, the phase wherein φ 1  is high is expressed as ‘phase φ 1 ’ and the phase wherein φ 2  is high is similarly expressed as ‘phase φ 2 ’. 
   A second feedback capacitance Ca 2  is connected between the output of the op amp  12  and the inverting input and a switch Sw 5 , which also closes in phase φ 1 , is connected across this feedback capacitance Ca 2 . 
   The illustrated first stage  22  of a pipeline ADC  20  comprises a further op amp  24 , whose non-inverting input is tied to ground. The stage also comprises first and second input capacitors C 1   a  and C 1   b  respectively, and a flash ADC  26  and a DAC  28  in the usual manner. The flash ADC compares its input against one or more reference levels, which may include ground. It may be regarded as a set of one or more comparators. The output of the flash ADC  26  is connected to the input of the DAC  28  and also comprises the output of the bit extracted from the ADC stage  22 . The output of the DAC  28  feeds back, via a switch Sw 9 , which switches in phase φ 1 , to one end of the first input capacitor C 1   a . The same end of the first input capacitor is connected, via a switch Sw 8 , which switches in phase  42 , to the input to the stage  22 , which receives a signal Vsig output from the input PGA  10 . 
   One terminal of the other input capacitor C 1   b  is connected, via a phase φ 2  switch Sw 7 , to the same input of the stage  22 . That terminal is also connected, via a further phase φ 1  switch Sw 6 , to the output of the op amp  24 . 
   The other terminal of the first input capacitor C 1   a  is connected, via a phase φ 2  switch Sw 13 , to ground, and, via another phase φ 1  switch Sw 12 , to the inverting input of the op amp  24 . Similarly, the other terminal of the second input capacitor C 1   b  is connected, via a phase φ 2  switch Sw 11 , to ground, and, via another phase φ 1  switch Sw 10 , to the inverting input of the op amp  24 . 
   The inverting input is further connected to the output of the op amp  24 , via a phase φ 2  switch Sw 14 ; the stage input Vsig feeds into the flash ADC  26  via another phase φ 2  switch Sw 15 . In this example, this is a 1-bit flash ADC, functionally equivalent to a simple comparator, which senses whether the input voltage Vsig is greater or less than ground. Its digital output drives a DAC  28 , in this case a simple 1-bit DAC, delivering a conversion result signal or voltage Vdac equal to +Vref or −Vref depending on the polarity of Vsig. 
   With reference to the timing diagram of  FIG. 1   b , switches Sw 1 , Sw 4  and Sw 5  of the PGA are driven closed by the first clock signal φ 1 . Switches Sw 2  and Sw 3  are driven closed by the second clock signal  42 , as illustrated in  FIG. 1   a.    
   Operation of the input PGA will now be described. In phase φ 1 , input capacitance Ca 1  is charged between Vin and ground by closing switches Sw 1  and Sw 4  as shown. Meanwhile capacitance Ca 2  is discharged by the closed switch Sw 5  across its terminals, and the op amp inverting input is driven to a virtual earth by the op amp  12  via the short circuit formed by this switch Sw 5 . 
   In the other phase φ 2 , when the phase φ 1  switches are open, the input side of Ca 1  is grounded by closing the appropriate switches Sw 2  and Sw 3 , and the op amp forces the other end of Ca 1  (connected thereto by the closing of the phase φ 2  switch Sw 2 ) to virtual ground by passing its charge onto Ca 2 . By charge conservation on the common node of Ca 1  and Ca 2 , the op amp output Vsig=(Ca 1 /Ca 2 )*Vin. The gain of the PGA  10  is programmed by varying Ca 1  and Ca 2 —in a practical implementation each of these would usually be implemented by banks of parallel capacitors selected by CMOS switches. 
   Operation of stage  1  of the ADC will now be described. In phase φ 2 , the op amp  12  of the input PGA also charges up the ADC input capacitors C 1   a , C 1   b  to Vsig via the phase φ 2  switches Sw 7 , Sw 11 , Sw 8  and Sw 13 . This is the familiar sampling step of pipeline ADCs. 
   In stage  1  of the ADC, during phase φ 2 , the op amp  24  is reset by switch sw 14  to discharge parasitics on its inverting input to ground. 
   Then, switches Sw 7 , Sw 11 , Sw 8 , Sw 13  and Sw 14 , previously closed, are opened, retaining Vsig stored on capacitors C 1   a  and C 1   b . This is the ‘hold’ step, and thus this arrangement is the familiar ‘sample and hold’ aspect of the ADC. 
   In the next phase  1 , the Vsig end of C 1   a  is switched to Vdac by means of the phase φ 1  switch Sw 9 , and the Vsig end of C 1   b  is connected to the op amp output Vout 1  by means of the corresponding phase φ 1  switch Sw 6 . The other ends of these capacitors are connected to the virtual earth created at the op amp inverting input via switches Sw 10  and Sw 12  respectively. 
   The total charge on the plates of C 1   a  and C 1   b  opposite from those connectable to the stage input is thus Vdac*C 1   a +Vout 1 *C 1   b . However the total charge on these plates at the end of the previous phase φ 2  is Vsig*(C 1   a +C 1   b ). Equating these charges gives:
 
 V dac* C 1 a+V out1 *C 1 b=V sig*( C 1 a+C 1 b )
 
   In this example C 1   a  is selected to be equal to C 1   b , so:
 
 V dac+ V out1=2 *V sig
 
So
 
 V out1=2 *V sig− V dac
 
For example, if  V sig=+ V ref, then  V dac=+ V ref, and  V out1 =+V ref.
 
If  V sig=+10 mV, then  V dac=+ V ref, so  V out1=20 mV− V ref.
 
If  V sig=−10 mV, then  V dac=− V ref, so  V out1=−20 mV+ V ref.
 
   The transfer characteristic is shown in  FIG. 2   a . This residue signal 2*(Vsig+/−Vref/2) charges up the input capacitors of the ADC second stage in φ 1 , ready to give its output in turn at the next phase φ 2 . 
   This arrangement has the disadvantage that, unless the input offset of the flash ADC comparator is less than 1LSB (for 14 bits, Vref=1V, 1LSB=1V/16384=60 μV, which is impractical in terms of offset voltage and overdrive required for reasonable response time), the extreme outputs of stage  1  will exceed or not get to the full-scale input range of the subsequent processing, so the whole pipeline ADC will exhibit missing or duplicate codes as the input is swept over the signal range. The effect of this on the transfer characteristic is illustrated in  FIG. 2   b.    
   To avoid this, a well-known modification to this arrangement replaces the single comparator in the flash ADC  26  by a pair of comparators with thresholds +/−(Vref/2), which can be regarded as a two-threshold comparator, and the two-level DAC by a three-level DAC with three possible conversion results or outputs:
 
 V dac={− V ref, 0 , +V ref}.
 
   The transfer function for this modification is illustrated in  FIG. 2   c . If there is a comparator error, the output of the corresponding pipeline stage will exceed +/−Vref, but since the useful input range of the following stage is now extended past +/−Vref, this merely alters the codes generated downstream to compensate, and so reasonable errors in the comparators can be corrected for. This technique is known as the Digital Error Correction (DEC). DEC also relaxes the comparator input overdrive specification, since there is a wide band of “don&#39;t care” levels for the comparator, for instance +/−(Vref/10) or 100 mV, rather than 1LSB or 60 μV. Thus, a simple comparator is adequate yet will still react swiftly to the larger overdrive, and so can be designed to sample the input almost at the end of φ 2 , and be ready to drive the DAC at the start of non-overlapping clock φ 1 , thereby allowing the PGA op amp (or the ADC op amp, in the case of later stages of a multi-stage converter) the maximum time to settle, i.e. almost half of the input signal sample period. 
   A further modification, as mentioned above, is to extract two or more bits per stage, using a higher-resolution flash ADC (or multi-threshold comparator) and DAC giving fewer, but more complex stages, and thus introducing an extra degree of freedom in the optimisation of power, area and performance. To illustrate this variant,  FIG. 3  shows an ADC stage comprising a capacitor bank structure  40  for extracting 2 bits per stage. 
   In the capacitor bank structure, five capacitors C 1   a , C 1   b , C 1   c , C 1   d  and C 1   e  are provided. A first terminal of each of four of the capacitors (C 1   a  through C 1   d ) is connected to Vdac via a switch (Sw 29 , Sw 26 , Sw 25 , Sw 22  respectively) closed in a first clock phase φ 1 . The same terminal of each of the said four capacitors (C 1   a  though C 1   d ) is connected to Vsig via a switch (Sw 28 , Sw 27 , Sw 24 , Sw 23  respectively) closed in a second clock phase φ 2 . 
   The other terminal of each of the said four capacitors is connected to the inverting input of the op amp  24 , as is a terminal of the fifth capacitor C 1   e , each via a respective switch (Sw 39 , Sw 36 , Sw 35 , Sw 32 , Sw 30 ) closed in the first clock phase φ 1 . Said five capacitor terminals are also connected to ground via respective switches (Sw 38 , Sw 37 , Sw 34 , Sw 33 , Sw 31 ) closed in the second clock phase φ 2 . 
   The opposite terminal of the fifth capacitor C 1   e  is connected to the output of the op amp  24  via a switch Sw 20  closed in the first clock phase φ 1 . That output is also connected to ground, via a switch Sw 21  closed in the second clock phase φ 2 . 
   A reset switch Sw 40  is connected across the output and the inverting input of the op amp, closed during a reset phase φR. 
   The stage input Vsig feeds into the flash ADC via another phase φ 2  switch Sw 41 , whose digital output drives a DAC, delivering a conversion result signal or voltage Vdac. 
   In this example, the flash ADC levels are −¾*Vref, −¼*Vref, +¼*Vref, and +¾*Vref, and the capacitor array consists of 4 equal input capacitors C 1   a , C 1   b , C 1   c , C 1   d , and a fifth capacitor C 1   e , which is thus grounded in the first clock phase φ 2 , then switched in feedback in the alternate clock phase φ 1 , while the input capacitors are connected to the DAC, whose output is one of {−Vref, −Vref/2, 0, +Vref/2, +Vref}. 
   The DAC illustrated in  FIG. 3  may comprise a resistor potential divider to generate these levels. Alternatively, to avoid this potential divider, the switching of C 1   a , C 1   b , C 1   c , C 1   d  in phase φ 1  may be modified by adding extra switches controlled by the DAC control word, to switch them to +Vref and −Vref in combinations of (4,0) (3,1) (2,2) (1,3) (0,4) to generate net charge corresponding to −Vref, −Vref/2, 0, +Vref/2, and +Vref (i.e. −Vref*Ctot, −Vref/2*Ctot, . . . , where Ctot=C 1   a +C 1   b +C 1   c +C 1   d ) according to the DAC control word. These switches may either be extra series switches directly controlled by the DAC control word, or may be the switches Sw 29  etc. as shown, connected directly between +/−Vref and the respective capacitors, but controlled by bits derived from the DAC word and gated with the appropriate clock phase. 
   Whereas the examples described above, with reference to  FIGS. 1 to 3 , all rely on the provision of several stages to construct an ADC of desired resolution, it would be advantageous to reduce the number of op amps and capacitor banks to reduce chip area and total power consumption, especially for desired sample rates well within the speed capabilities of the technology. 
   “Efficient Circuit Configurations for Algorithmic Analog to Digital Converters” (K. Nagaraj, IEEE Trans. on Circuits and Systems II vol. 40 No. 12 Dec. 1993) describes a recirculating ADC arrangement in which banks of capacitors are used to store residual voltages, for re-presentation to conversion means. 
     FIG. 4  shows a similar arrangement, providing the same simple function as the ADC  20  illustrated in  FIG. 1 , but using only one amplifier and flash ADC. The schematic is similar to  FIG. 1 , but a second capacitor bank C 2   a , C 2   b  is added. 
   Thus, as illustrated in  FIG. 4 , the output of the DAC  28  feeds back, via switch Sw 59 , which switches in phase φ 1 , to one end of the first input capacitor C 1   a . The same end of the first input capacitor is connected, via a switch Sw 58 , which switches in phase φ 2 , to a node A connected to the input to the stage  22  (which receives a signal Vsig output from the input PGA  10 ) via a switch Sw 51  closed in a sub-phase φ 2   x  of the phase φ 2 , and to the output of the op amp  24  via a switch Sw 50  closed in a sub-phase φ 2   y  of the phase φ 2 . 
   One terminal of the other input capacitor C 1   b  in that bank is connected, via a phase φ 2  switch Sw 57 , to the same node A of the stage  22 . That terminal is also connected, via a further phase φ 1  switch Sw 56 , to the output of the op amp  24 . 
   The other terminal of the first input capacitor C 1   a  is connected, via a phase φ 2  switch Sw 68 , to ground, and, via another phase φ 1  switch Sw 69 , to the inverting input of the op amp  24 . Similarly, the other terminal of the second input capacitor C 1   b  is connected, via a phase φ 2  switch Sw 67 , to ground, and, via another phase φ 1  switch Sw 66 , to the inverting input of the op amp  24 . 
   The other capacitor bank C 2   a , C 2   b  is clocked in anti-phase to the original ADC input bank C 1   a , C 1   b . This arises because the output of the DAC  28  feeds back, via switch Sw 55 , which switches in phase φ 2   y , to one end of the first input capacitor C 2   a  of that bank. The same end of the first input capacitor C 2   a  is connected, via a switch Sw 54 , which switches in phase φ 1 , to the output of the op amp  24 . 
   One terminal of the other input capacitor C 2   b  in that bank is connected, via a phase φ 1  switch Sw 53 , to the output of the op amp  24 . That terminal is also connected, via a further phase φ 2   y  switch Sw 52 , to the output of the op amp  24 . 
   The other terminal of the first input capacitor C 2   a  is connected, via a phase φ 1  switch Sw 64 , to ground, and, via another phase φ 2   y  switch Sw 65 , to the inverting input of the op amp  24 . Similarly, the other terminal of the second input capacitor C 2   b  is connected, via a phase φ 1  switch Sw 63 , to ground, and, via another phase φ 2   y  switch Sw 62 , to the inverting input of the op amp  24 . 
   A switch Sw 60  presents the voltage at node A to the Flash ADC  26  in phase φ 2  while, in phase φ 1 , the voltage on the output of the op amp is presented to the Flash ADC  26 , by means of a switch Sw 61 . 
   A reset switch Sw 70  across the op amp is also provided. 
     FIG. 5   a  shows a suitable clocking scheme, here illustrating only a 6-bit conversion for simplicity. 
   The underlying principle of operation is that capacitors C 2   a , C 2   b  sample the output of the op amp in one phase, this output being based on the charge currently on C 1   b  resulting from charge on C 1   a  corresponding to the DAC output or conversion result signal Vdac and charge previously on C 1   a  and C 1   b  due to the previous op amp output. Then, in the next phase, C 1   a , C 1   b  sample the op amp output based on the previous op amp output stored on C 2   a , C 2   b  and the updated Vdac. This continues in a recirculating manner until the required degree of resolution has been reached. 
   Operation of the arrangement of  FIG. 4  will now be described, with reference to  FIG. 5   a  which shows a suitable clocking scheme.
     a) In a first phase (φ 2   x ) of the conversion cycle, Vsig charges up C 1   a  and C 1   b , via an additional switch Sw 51  interposed on the stage input. The flash ADC samples this Vsig, and latches its output for later use by the DAC. At the end of this phase, C 1   a , C 1   b  are disconnected, to store the sampled Vsig.   b) Then, the op amp is reset by φR. For this first phase, this action could be performed simultaneously with the above φ 2   x  phase, since the op amp output is not used, but on subsequent phases, this would short out a desired op amp output. Thus, in the illustrated example, phase φR comprises a signal which, for all cycles, closes the reset switch after completion of each of phases φ 1 , φ 2   x , and φ 2   y , as illustrated in  FIG. 5   a.      c) In the next phase, φ 1 , a residue 2*(Vsig+/−Vref/2) appears on the op amp output. This arises in a similar way to that described in relation to  FIG. 1 , with C 1   b  acting as a feedback capacitor and C 1   a  driven by the DAC, itself driven by the previously latched flash ADC output. The flash ADC samples the op amp output signal, and again latches its output for later use by the DAC. The op amp output is fed round to charge C 2   a  and C 2   b . Then all capacitors are isolated again at the end of this phase.   d) Then the op amp is reset (by closing switch φR), ready for the next phase.   e) In the next phase φ 2   y , C 2   b  acts as a feedback capacitor, C 2   a  is driven by the DAC according to the previous flash ADC output, and the op amp delivers the next residue to C 1   a , C 1   b  via switch Sw 50  (with the Vsig switch sw 51 , closed in φ 2   x , being open in this phase).   f) Then, again, the op amp is reset (φR), ready for the next phase φ 1 .   g) In the next phase φ 1 , configured as (b), the next residue appears at the op amp, and is fed back to C 2   a , C 2   b . The cycle then continues from (d) until a desired number of bits is extracted.   h) Once the desired number of bits has been extracted, the entire process is restarted from step (a) with a new sample of Vsig.   

   The cycle described above with regard to  FIG. 4  includes a reset every phase, analogous to the op amp reset in  FIG. 1 . However it is not necessary to reset every cycle. In an ideal implementation of this embodiment, it will be understood that it is only necessary to reset the op amp at the very start of operation, for example on power-up, since the op amp inverting input will settle back to very close to virtual earth voltage before the end of each phase, at which time the capacitors on that node are disconnected, leaving the inverting input voltage unchanged, still at the voltage to which it was reset, and hence not requiring further resetting. 
   However, incomplete settling of the op amp, in conjunction with parasitic capacitances on that node, may lead to some residual virtual earth signal charge propagating from one phase to the next. Assuming settling to less than 1LSB at the output, and parasitic capacitances smaller than the signal capacitances, this effect will be negligible during a few conversions, but over thousands of conversions the resulting errors might accumulate. Also, there is the possibility of other second-order effects, such as some pumping of charge by switch clock feed-through. Further, there will be some small but non-zero leakage currents associated with real switches on this node. 
   Therefore, it is typically convenient to reset once every complete conversion, during clock phase φ 2   x , in which case the clocking arrangement of  FIG. 5   b  is possible, giving almost a complete half-sample-period for each phase rather than only a quarter-sample-period. For a conversion of N bits, N/2 clock cycles are required. So, a 12-bit 5 Ms/s converter would require a clock of 6×5 Ms/s=30 Ms/s, and op amp settling in less than 1/(2*30 Ms/s)=16.7 ns, the same as a more conventional 30 Ms/s multi-stage pipeline converter. 
   It will be appreciated that the comparators in the flash ADC need to sample every half-cycle. Typically such a flash ADC will contain clocked comparators, which need a reset phase before each cycle. It would be possible to use two flash ADCs in parallel, resetting each on alternate phases. Alternatively, and preferably, given that the ADC will respond with adequate accuracy very quickly as discussed above, ADC clocks, shown as φRS, can be introduced. The flash ADC is then reset when φRS is low, it is operable to sample at the rising edge of φRS, and to latch data into the DAC control word on the falling edge of φRS. Clock φRS rises at or shortly before the falling edge of φ 2  and falls at or shortly before the rising edge of φ 1 . 
   It is noted that the above scheme can be readily extended to allow comparator offset correction, by DEC as described above, by setting the flash ADC comparator levels to +/−Vref/2 and Vdac to {−Vref, 0, Vref}. 
   In the arrangement of  FIG. 4 , the preceding PGA still only has the width of φ 2   x  (16.7 ns in this example), to settle into the ADC input capacitors. As discussed above, it is desirable to maximise the time available for the PGA amplifier to settle, to reduce its required gain-bandwidth requirement and hence its area and power requirements. 
   Some improvement could be obtained by stretching the on-time of the initial phase comprising φ 2   x  but, for a given input sample rate, this implies decreasing the time for the remaining conversion phases, so only limited improvement is available without reducing the available settling time for the later stages to well below 16.7 ns. 
   SUMMARY OF THE INVENTION 
   An aspect of the invention improves previous embodiments of recirculating or algorithmic ADCs by incorporating the use of capacitors and switches into an ADC to allow the use of only one amplifier such as an op amp in the ADC, while still allowing most of a sample period for the corresponding PGA to settle into the ADC input. 
   Another aspect of the invention provides a recirculating ADC with two feedback units for use with a single amplifier such as an op amp, characterised by a third feedback unit to be used in an initial step with the initial sample. In that way, settling time as a proportion of the whole conversion cycle can be reduced. 
   Another aspect of the invention provides a method of converting an analogue signal to a digital equivalent, using a recirculating method, and wherein a first recirculation means is used in a first cycle and second and third recirculating means are used alternately in subsequent cycles of the conversion. 
   A further aspect of the invention provides a device operable to receive an analogue signal and in response to generate a digital signal commensurate with an amplitude value of said analogue signal at a given instant, said device comprising a recirculating analogue to digital converter including flash conversion means, and residual determination means, having first and second storage means alternately operable to store a voltage for presentation to said flash conversion means on the one hand and to receive the result of operation of the residual determination means on the other hand, the device further comprising switching means operable to switch one of said storage means into one of first and second receiving modes, in a first mode the switching means being operable to receive an analogue signal to be converted, and in said second mode the switching means being operable to receive, in turn, the result of operation of the residual determination means. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Specific embodiments of the invention will now be described by way of example only, with reference to the drawings, and in view of the foregoing description of examples of other ADCs. In the appended drawings: 
       FIG. 1   a  illustrates a circuit diagram of an analogue to digital conversion system, comprising a switched-capacitor PGA driving a 1-bit per stage switched-capacitor pipeline ADC, extracting 1 bit per stage; 
       FIG. 1   b  illustrates timing diagrams for the arrangement illustrated in  FIG. 1   a;    
       FIG. 2   a  illustrates a transfer characteristic for the ADC stage illustrated in  FIG. 1   a;    
       FIG. 2   b  illustrates the transfer characteristic of a first modification of the ADC stage illustrated in  FIG. 1   a;    
       FIG. 2   c  illustrates the transfer characteristic of a second modification of the ADC stage illustrated in  FIG. 1   a;    
       FIG. 3  illustrates a circuit diagram of an ADC stage comprising a capacitor bank structure for extracting 2 bits per stage; 
       FIG. 4  illustrates a circuit diagram of an ADC stage comprising an alternative capacitor bank structure for extracting 2 bits per stage; 
       FIG. 5   a  shows a clocking scheme for use with the arrangement illustrated in  FIG. 3 ; 
       FIG. 5   b  shows a clocking scheme for use with the arrangement illustrated in  FIG. 4 ; 
       FIG. 6  illustrates a circuit diagram of a recirculating ADC stage in accordance with a first embodiment of the invention; 
       FIG. 7  illustrates a circuit diagram of a recirculating ADC in accordance with an second embodiment of the invention; 
       FIG. 8  illustrates a timing diagram governing operation of the recirculating ADC illustrated in  FIG. 7 ; 
       FIG. 9  illustrates a circuit diagram of a recirculating ADC in accordance with a third embodiment of the invention; 
       FIG. 10  illustrates a circuit diagram of a recirculating ADC in accordance with a fourth embodiment of the invention; and 
       FIG. 11  illustrates a timing diagram governing operation of the recirculating ADC illustrated in  FIG. 10 . 
   

   DETAILED DESCRIPTION 
   The circuit of  FIG. 6  shows a recirculating stage of an ADC, similar to that illustrated in  FIG. 4 , but with functional and operational distinctions. Table 1 illustrates a correspondence between the functional equivalence of certain of the switches of the arrangement of  FIG. 4  and that of  FIG. 6 . 
   
     
       
             
             
             
           
         
             
                 
               TABLE 1 
             
             
                 
                 
             
             
                 
               FIG. 4 
               FIG. 6 
             
             
                 
                 
             
           
           
             
                 
               Sw52 
               Sw84 
             
             
                 
               Sw53 
               Sw85 
             
             
                 
               Sw54 
               Sw86 
             
             
                 
               Sw55 
               Sw87 
             
             
                 
               Sw56 
               Sw92 
             
             
                 
               Sw59 
               Sw97 
             
             
                 
               Sw61 
               Sw98 
             
             
                 
               Sw62 
               Sw80 
             
             
                 
               Sw63 
               Sw81 
             
             
                 
               Sw64 
               Sw82 
             
             
                 
               Sw65 
               Sw83 
             
             
                 
               Sw66 
               Sw88 
             
             
                 
               Sw67 
               Sw89 
             
             
                 
               Sw68 
               Sw90 
             
             
                 
               Sw69 
               Sw91 
             
             
                 
               Sw70 
               Sw101 
             
             
                 
                 
             
           
        
       
     
   
   The structural difference is that the φ 2  switches (Sw 57 , Sw 58 , Sw 60 ) that were connected to C 1   a , C 1   b  and the flash ADC, in series with other switches (Sw 50 , Sw 51 ) driven by φ 2   x , φ 2   y  respectively have been replaced by parallel switches (Sw 93 , Sw 94 ; Sw 95 , Sw 96 ; Sw 99 , Sw 100 ) connected to φ 2   x , φ 2   y . Since φ 2  is equivalent to φ 2   x .OR.φ 2   y , this connection is equivalent. The total number of switches is increased by one, but each switch can be of higher on-resistance and thus occupy less area. 
   An advantage of this arrangement is that it requires no additional modification to the timing signals provided to the device. As discussed above, this circuit requires the preceding PGA to settle into the capacitors C 1   a , C 1   b  within one clock phase φ 2   x , say 16 ns. 
     FIG. 7  shows a circuit according to a further embodiment of the invention, which in conjunction with the clock phases illustrated in  FIG. 8 , allows more time for this PGA settling. Compared to the arrangement illustrated in  FIG. 6 , a third capacitor array C 3   a , C 3   b  and associated switches are added and the clock phases applied to C 1   a , C 1   b  switches are modified so that C 1   a , C 1   b  are now only used to sample the input and generate the first residue, stored on C 2   a , C 2   b . C 3   a , C 3   b , with switches driven by appropriate clock phase switches are used instead of C 1   a , C 1   b , alternating with C 2   a , C 2   b , for all other phases of the complete conversion cycle 
   The structure of the device illustrated in  FIG. 7  will now be described. The first bank of capacitors C 1   a , C 1   b  are connected as follows. A terminal of capacitor C 1   a  is connected to the device input Vsig by means of a switch Sw 132  which closes in phase φ 2   z . The same terminal is connected to the output of the DAC  28  by means of a further switch Sw 133  which closes in a phase φ 1   z . Similarly, a terminal of capacitor C 1   b  is connected to the device input Vsig by means of a switch Sw 131  which closes in phase φ 2   z . The same terminal is connected to the output of the amplifier  24  by means of a further switch Sw 130  which closes in a phase φ 1   z.    
   The opposite terminals of the capacitors C 1   a , C 1   b  of the first bank are connected to ground by means of respective switches Sw 120 , Sw 119 , which close in phase φ 2   z . These terminals are also connected to the inverting input of the op amp by means of respective switches Sw 121  and Sw 118  which close in a phase φ 1   z.    
   The second bank of capacitors C 2   a , C 2   b  are connected as follows. A terminal of capacitor C 2   a  is connected to the op amp output by means of a switch Sw 128  which closes in phase φ 1 . The same terminal is connected to the output of the DAC  28  by means of a further switch Sw 129  which closes in phase φ 2   y . Similarly, a terminal of capacitor C 2   b  is connected to the op amp output by means of a switch Sw 127  which closes in phase φ 1 . The same terminal is connected to the op amp output by means of a further switch Sw 126  which closes in a phase φ 2   y.    
   The opposite terminals of the capacitors C 2   a , C 2   b  of the second bank are connected to ground by means of respective switches Sw 116 , Sw 115 , which close in phase  1 . These terminals are also connected to the inverting input of the op amp by means of respective switches Sw 117  and Sw 114  which close in phase φ 2   y.    
   The third bank of capacitors C 3   a , C 3   b  are connected as follows. A terminal of capacitor C 3   a  is connected to the op amp output by means of a switch Sw 124  which closes in phase φ 2   y . The same terminal is connected to the output of the DAC  28  by means of a further switch Sw 125  which closes in a phase φ 1   y . Similarly, a terminal of capacitor C 3   b  is connected to the op amp output by means of a switch Sw 123  which closes in phase φ 2   y . The same terminal is connected to the op amp output by means of a further switch Sw 122  which closes in a phase φ 1   y.    
   The opposite terminals of the capacitors C 3   a , C 3   b  of the third bank are connected to ground by means of respective switches Sw 112 , Sw 111 , which close in phase φ 2   y . These terminals are also connected to the inverting input of the op amp by means of respective switches Sw 113  and Sw 110  which close in phase φ 1   y.    
   The flash ADC input is connected to Vsig by switch Sw 136  which closes in phase φ 2   x  and to the operational amplifier output by switches sw 134 ,  135  which close in phases φ 1  and φ 2   y  respectively. 
   A description of operation of the circuit illustrated in  FIG. 7  now follows.
     (a) In a first phase (φ 2 , φ 2   x ) of the conversion cycle, the op amp is reset by switch Sw 137  acting in phase φR, and capacitors C 1   a , C 1   b  are charged to Vsig via switches Sw 119 , Sw 120 , Sw 131  and Sw 132  acting in phase φ 2   z.      

   Meanwhile the input voltage Vsig is also presented to the flash ADC, by closing switch Sw 136 , and the flash ADC samples and converts on the positive φRS edge shortly before the end of this φ 2  phase, thus deciding the first bit of the conversion. 
   Then, phase (φ 2 , φ 2   x ) ends and all of the aforementioned switches of this phase re-open. The first bit of the conversion is then latched into the DAC, at the falling edge of φRS to give an output +/−Vref for use in the next phase.
     (b) In the next phase, (φ 1 , φ 1   z ), switches Sw 118 , Sw 121 , Sw 130  and Sw 133  close to connect capacitor C 1   a  between the Vdac output and the inverting input of the op amp, and capacitor C 1   b  between the inverting input of the op amp (virtual earth) and the output of the op amp (Vout). This causes the op amp output voltage Vout to become the first residual voltage Vres 1 =2.Vsig+/−Vref, as discussed above.   

   Further, switches Sw 127 , Sw 128 , Sw 115  and Sw 116  are closed, bringing capacitors C 2   a  and C 2   b  into connection between the op amp output Vres 1  and ground. This charges C 2   a  and C 2   b  up to Vres 1 , storing this residual signal for use in a later phase. 
   Meanwhile the residual voltage Vres 1  is presented to the flash ADC, by closing switch Sw 134  to bring the output Vout of the op amp to the flash ADC input, and the flash ADC samples and converts on the positive φRS edge shortly before the end of this φ 1  phase, thus deciding the second bit of the conversion. 
   All of the aforementioned switches of this phase are then re-opened. The second bit of the conversion is then latched into the DAC, to give an output +/−Vref for use in the next phase.
     (c) Then, in a further (φ 2 , φ 2   y ) phase, switches Sw 114 , Sw 117 , Sw 126  and Sw 129  close, connecting capacitor C 2   a  between the inverting input of the op amp and the DAC output Vdac, and capacitor C 2   b  between the inverting input and the output of the op amp. This causes the op amp output voltage to become the second residual voltage Vres 2 =2.Vres 1 +/−Vref, as discussed above.   

   Switches Sw 123 , Sw 124 , Sw 111  and Sw 112  close to connect capacitors C 3   a  and C 3   b  between the op amp output Vres 2  and ground. This charges C 3   a  and C 3   b  up to Vres 2 , storing this residual signal for use in a later phase. 
   At the same time, Sw 135  closes to present the op amp output Vout, equal to Vres 2 , to the flash ADC and the flash ADC samples and converts on the positive φRS edge shortly before the end of this φ 2  phase, thus generating the third bit. 
   Also, in this phase, φ 2   z  switches Sw 119 , Sw 120 , Sw 131  and Sw 132  can close, to allow the PGA to start to charge capacitors C 1   a  and C 1   b  up to the next Vsig voltage sample, since C 1   a  and C 1   b  have completed their function for this cycle. 
   All of the aforementioned switches of this phase, except the four φ 2   z  switches are then re-opened. The third bit of the conversion is then latched into the DAC, to give an output +/−Vref for use in the next phase.
     (d) In the next (φ 1 , φ 1   y ) phase, switches Sw 110 , Sw 113 , Sw 122  and Sw 125  close to connect capacitors C 3   a  and C 3   b  (previously charged with a residual voltage Vres 2  determined by the op amp) as an input impedance between Vdac and the inverting input of the op amp on the one hand, and as a feedback capacitor over the op amp on the other, respectively. This causes the op amp output voltage to become the third residual voltage Vres 3 =2.Vres 2 +/−Vref, as discussed above.   

   Capacitors C 2   a  and C 2   b  are connected between Vres 3  and ground, by closing switches Sw 115 , Sw 116 , Sw 127  and Sw 128 . These capacitors thus store residual voltage Vres 3  for use in a later phase. 
   Meanwhile the residual voltage Vres 3  is presented to the flash ADC, by closing switch Sw 134  to bring the output Vout of the op amp to the flash ADC input, and the flash ADC samples and converts on the positive φRS edge shortly before the end of this φ 1  phase, thus deciding the fourth bit of the conversion. 
   All of the aforementioned switches of this phase are then re-opened.
     (e) Then, the steps undertaken in phase (c) are repeated in a further (φ 2 , φ 2   y ) phase to generate a fourth residue voltage Vres 4  and extract the fifth bit.   (f) Finally, in a further (φ 1 , φ 1   y ) phase the sixth bit is extracted on the basis of a fifth residue voltage Vres 5  generated by the operation of switches as in phase (d).   (g) Then a new conversion cycle starts with a new (φ 2 , φ 2   x ) phase as in phase (a) above.   

   In summary, therefore, compared to the clock scheme of  FIG. 5   b , the scheme of  FIG. 8  includes three extra phases: φ 1   z , φ 1   y , φ 2   z . Phase φ 1   z  is only high during the phase φ 1  immediately after the input signal sampling phase φ 2   x , and is used to connect C 1   a , C 1   b  to the op amp negative input. At all other times, C 1   a , C 1   b  are disconnected from the op amp, and so can be used to track the signal on Vsig via switches driven by φ 2   z , which is a non-overlapping inverse clock to φ 1   z . Phase φ 1   y  is high during the remaining phases φ 1 , to connect C 3   a , C 3   b  into the circuit, in conjunction with the phase φ 2   y.    
   This means that the PGA now has the full duration of φ 2   z  rather than just φ 2   x  in which to settle. For the present example of a 6-bit conversion, the PGA thus potentially has ⅚ of conversion cycle available to drive and settle into the input of the ADC. Usually, the PGA will sample its input Vin in the alternate clock phase to the phase in which it drives the ADC, as shown in  FIG. 1 . So this would only leave ⅙ of the conversion cycle for the circuit driving into the PGA input to settle. So to relax the settling requirement of this preceding amplifier, and avoid low resistance, large, switches connecting Vin to the input capacitors, for some applications a lower duty cycle than ⅚ for φ 2   z  would be used. But for other applications where Vin is only valid for a short time (for example where only 1 in 3 pixels is extracted from an image sensor output in a fast preview mode) the full ⅚ duty cycle might be used for φ 2   z  to avoid the PGA settling limiting performance at speed. 
   It is to be noted that C 2   a , C 2   b  (and C 3   a , C 3   b ) can be smaller than C 1   a , C 1   b  since both matching and kTC noise constraints are reduced by the gain of the first stage. In many cases, however, they will be the same size, to ensure that first-stage noise and mismatch dominates, since the first stage gain is only 2 in this example. Also, this eases the ADC op amp design, since its settling characteristics need only be optimised for one load. 
   These improved circuits can be designed with or without Digital Error Correction to render (or not) the circuit insensitive to comparator offsets, by appropriately setting the input thresholds of the flash ADC and appropriate choice of effective DAC output signals and appropriate processing of the extracted digital bits. For example, the thresholds could be set at +/−Vref/2 and the DAC outputs at {−Vref, 0, +Vref} as above, 
   As with a pipeline, even with DEC to compensate for comparator errors, achieving full linearity (e.g. no missing or duplicate codes) requires full accuracy, to the resolution remaining to be extracted, to be maintained down the analogue signal path. 
   Especially for the first stage, where the signal must be processed to maximum resolution, accuracy is affected by finite gain of op amps, but these can be designed by those skilled in the art with very much greater than say 14 bit gain (84 dB). 
   It will be appreciated that the example is a six bit converter, whereas further bit conversions could be made with mere extension of the timing diagram illustrated in  FIG. 8 . 
   A further embodiment of the invention is illustrated in  FIG. 9 . This circuit takes advantage of the fact that the C 1   a , C 1   b  capacitor plates facing the op amp inverting input are connected to the same node as each other in each clock phase by connecting these plates together and connecting this common node to the op amp or ground by common switches. A similar approach can be taken for the corresponding plates of pairs of capacitors C 2   a , C 2   b  and C 3   a , C 3   b.    
   It will be appreciated that various of the switches of the device illustrated in  FIG. 9  will be functionally equivalent to switches provided in the example illustrated in  FIG. 7 . For the benefit of the reader, these are set out in table 2. 
   
     
       
             
             
             
           
         
             
                 
               TABLE 2 
             
             
                 
                 
             
             
                 
               FIG. 7 
               FIG. 9 
             
             
                 
                 
             
           
           
             
                 
               Sw110, Sw113 
               Sw150 
             
             
                 
               Sw111, Sw112 
               Sw151 
             
             
                 
               Sw114, Sw117 
               Sw152 
             
             
                 
               Sw115, Sw116 
               Sw153 
             
             
                 
               Sw118, Sw121 
               Sw154 
             
             
                 
               Sw119, Sw120 
               Sw155 
             
             
                 
               Sw122 
               Sw140 
             
             
                 
               Sw123 
               Sw141 
             
             
                 
               Sw124 
               Sw142 
             
             
                 
               Sw125 
               Sw143 
             
             
                 
               Sw126, Sw127 
               Sw145a, sw144a 
             
             
                 
               Sw128 
               Sw144 
             
             
                 
               Sw129 
               Sw145 
             
             
                 
               Sw130 
               Sw146 
             
             
                 
               Sw131 
               Sw147 
             
             
                 
               Sw132 
               Sw148 
             
             
                 
               Sw133 
               Sw149 
             
             
                 
               Sw134 
               Sw157 
             
             
                 
               Sw135 
               Sw158 
             
             
                 
               Sw136 
               Sw159 
             
             
                 
               Sw137 
               Sw156 
             
             
                 
                 
             
           
        
       
     
   
   In the illustrated embodiments of the invention set out above, conversion accuracy can also be sensitive to capacitor mismatch between C 1   a , C 1   b , etc. This is because this affects the gain factor (2 in the single-bit example) applied to the signal in each stage of conversion. With very careful device design, particularly with regard to layout of a solid state device, better than 12-bit matching can be achieved. However, for improved accuracy, the devices disclosed here before can incorporate further features operable to deliver additional accuracy. 
     FIG. 10  illustrates an example of such a device, incorporating modifications with regard to the arrangement illustrated in  FIG. 7 . As before, it is possible to identify switches of equivalent function, or groups of switches which, taking into account the enhanced function of the device illustrated in  FIG. 10 , are collectively functionally equivalent to groups of switches of the device of  FIG. 7 . Such equivalence is set out in table 3 below: 
   
     
       
             
             
             
           
         
             
                 
               TABLE 3 
             
             
                 
                 
             
             
                 
               FIG. 7 
               FIG. 10 
             
             
                 
                 
             
           
           
             
                 
               Sw110 
               Sw181 
             
             
                 
               Sw111 
               Sw182 
             
             
                 
               Sw112 
               Sw183 
             
             
                 
               Sw113 
               Sw184 
             
             
                 
               Sw114, 
               Sw185 
             
             
                 
               Sw115 
               Sw186 
             
             
                 
               Sw116 
               Sw187 
             
             
                 
               Sw117 
               Sw188 
             
             
                 
               Sw118 
               Sw189 
             
             
                 
               Sw119 
               Sw190 
             
             
                 
               Sw120 
               Sw191 
             
             
                 
               Sw121 
               Sw192 
             
             
                 
               Sw122 
               Sw160, Sw161 
             
             
                 
               Sw123 
               Sw162 
             
             
                 
               Sw124 
               Sw163 
             
             
                 
               Sw125 
               Sw164, Sw165 
             
             
                 
               Sw126 
               Sw166, Sw167 
             
             
                 
               Sw127 
               Sw168 
             
             
                 
               Sw128 
               Sw169 
             
             
                 
               Sw129 
               Sw170, Sw171 
             
             
                 
               Sw130 
               Sw172, Sw173 
             
             
                 
               Sw131 
               Sw174 
             
             
                 
               Sw132 
               Sw175 
             
             
                 
               Sw133 
               Sw176, Sw177 
             
             
                 
               Sw134 
               Sw180 
             
             
                 
               Sw135 
               Sw179 
             
             
                 
               Sw136 
               Sw178 
             
             
                 
               Sw137 
               Sw193 
             
             
                 
                 
             
           
        
       
     
   
   With the following exceptions, the function and timing of switches is as described above with regard to  FIG. 7 . However, as shown in the circuit of  FIG. 10  and clock timing diagram of  FIG. 11 , phases φ 1  and φ 1   x  are split into two pairs of respective non-overlapping sub-phases φ 1   a , φ 1   b  and φ 1   xa , φ 1   xb : in φ 1   xa , C 1   a  is the input capacitor connected to the DAC, C 1   b  is the feedback capacitor, in the second sub-phase these connections to C 1   a  and C 1   b  are interchanged. The first output is stored on C 2   a  via a φ 1   a  switch (Sw 169 ), the second on C 2   b  via a φ 1   b  switch (Sw 168 ). 
   The total charge on C 2   a  and C 2   b  then represents a signal with only second-order symptoms of the capacitor mismatches. In this way the error in gain due to C 1   a  mismatch to C 1   b  is reduced to second order. Similar modification has been made to the switching of capacitors C 2   a , C 2   b  and C 3   a , C 3   b . In this way, compared with the arrangement of  FIG. 7 , phase φ 2   y  is split into two sub-phases to allow the effect of C 2   a , C 2   b  mismatch to be reduced, with respective outputs stored on C 3   a , C 3   b.    
   The penalty for this is a decrease by nearly a factor of two of the settling time available to the op amps, either requiring faster more power-hungry op amps, or halving the specified maximum conversion rate. This may still be an acceptable compromise for applications at lower sample rate or higher linearity, or where cost dictates the use of small and hence less well matched capacitors. 
   One skilled in the art could modify this scheme to extract multiple bits per cycle by increasing the resolution of the flash ADC and DAC, perhaps with the DAC merged into C 1   a , C 1   b , C 2   a , C 2   b , C 3   a , C 3   b  by splitting these capacitors and adding extra switches in a similar way to that described in respect of  FIG. 3 . 
   As is well known by those skilled in the art, all of the devices described in relation to specific embodiments of the invention can readily be converted to fully-differential equivalents by standard methods-including either duplicating the whole circuit with opposite signal polarities or replacing the op amp by a fully-differential equivalent and duplicating the switch and capacitor network on the second input of the op amp and inverting appropriate signals. 
   The timing diagrams shown illustrate the nominal timings of the clock phases, but as is customary in the art, optimum performance may require some adjustment of the precise timing of some clock edges. For instance switches attached to the virtual earth will normally be disconnected marginally before switches on the remote end of the capacitors, to reduce charge injection onto the sensitive virtual earth node, and the flash ADC may sample before any other clock activity on the nearby edge to avoid clock-induced spikes just as it samples the signal. 
   Whereas the described embodiments have been illustrated with a view to implementation in CMOS technology, it will be appreciated that equivalent arrangements, whether or not making use of switches and capacitors, can be provided in other technologies. 
   Referring to  FIG. 9 , the capacitors C 1   a , C 1   b  and switches connected thereto can be regarded as a first means  201  for storage and residual determination, operable to store for later presentation a sample of the input signal, and operable in conjunction with the flash ADC or comparator  26  and amplifier  24  to determine a residual for presentation to a second storage and residual determination means. Similarly the capacitors C 2   a , C 2   b  and switches connected thereto can be regarded as second storage and residual determination means  202  operable to store for later presentation a signal corresponding to a determined residual, and operable in conjunction with the flash ADC or comparator  26  and amplifier  24  to determine a further residual for presentation to a third storage and residual determination means. Similarly the capacitors C 3   a , C 3   b  and switches connected thereto can be regarded as third storage and residual determination means  203  operable to store for later presentation a signal corresponding to a determined residual, and operable in conjunction with the flash ADC or comparator  26  and amplifier  24  to determine a further residual for presentation to a said second storage and residual determination means. Broken lines are indicated in  FIG. 9  to demonstrate these first, second and third storage and determination means of these arrangements—it will be appreciated that these groupings of components are by way of example only, and other groupings would equally deliver the same function to an ADC stage with other arrangements of switches and storage means (e.g. capacitors). 
   In the embodiment illustrated in  FIG. 9  and described above, the storage means comprises pairs of capacitors: in one clock phase both capacitors of a pair are connected to charge up to an applied voltage, this applied voltage being one of the ADC input voltage and the op amp output voltage; in another clock phase one is connected to the DAC output and the other is connected in feedback between input and output of the op amp. In the circuit of  FIG. 10 , switched capacitors are used in a similar fashion, albeit with extra clock phases, in this case to desensitise the design to capacitor mismatch. Other similar extensions and variations of these switched capacitor schemes will be apparent to those skilled in the art. In each case, the arrangement comprises storage means operable to be switched into and out of operational connection with the op amp and the flash conversion means, thereby providing the recirculating function of the ADC stage. 
   Although in circuits described herein, the storage means use switched capacitors as analogue memory elements, other possibilities exist. Known switched-current techniques could be used to implement similar storage means, probably in conjunction with current-mode op amps and current comparators. Other possibilities could include the use of floating-gate or integrated ferro-magnetic elements as analogue memory elements. 
   While the description has implied monolithic implementation using-CMOS technology, the present invention can deliver corresponding advantages, for instance, in discrete component implementation. 
   The invention for which protection is sought is defined in the claims appended hereto. While the claims appended hereto are to be construed with reference to the description of specific embodiments, it will be appreciated that the scope of the claims are not to be limited to the strict interpretation of features of the claims as corresponding directly to the exemplary features of the described embodiments, but rather to the generality, whether of function or of structure, implicit in the disclosure.