Abstract:
Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.

Description:
BACKGROUND 
   1. Technical Field 
   The present invention relates generally to Programmable Logic Devices (PLDs). More particularly, the present invention relates to connection of a Serial Peripheral Interface (SPI) to a PLD. 
   2. Related Art 
   Programmable. Logic Devices (PLDs) exist as well-known types of integrated circuits (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost. 
   A FPGA can be used with a serial peripheral interface programmable read-only memory (SPI PROM), a permanent memory chip in which the content for programming the FPGA is created by a user of the FPGA chip. In order to configure the FPGA, contents of the SPI PROM are loaded into the FPGA configuration memory. 
   It would be desirable to provide processes to optimize the data transfer between a FPGA and a SPI PROM. 
   SUMMARY 
   Embodiments of the present invention optimize the link between a FPGA and a SPI PROM by enabling multiple configurations of a PLD, such as a FPGA, to be provided from a single SPI PROM. The multiple configurations are loaded when the PLD is connected to a SPI PROM using a programmable SPI address register incorporated into a SPI state machine of the PLD. With the SPI state machine, a read command followed by a first address where configuration data is to be retrieved is sent from the SPI address register of the PLD to the SPI PROM. Configuration data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address where additional second configuration data is stored in the SPI PROM. The data read is stored in the PLD memory, and the second address where additional data is to be read is stored in the SPI address register. These steps may be repeated to retrieve the second configuration data as well as other configurations for subsequent boots of the PLD, with the second address providing the start address for locating the next configuration in the SPI PROM. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further details of the present invention are explained with the help of the attached drawings in which: 
       FIG. 1  illustrates exemplary FPGA and SPI PROM connections; 
       FIG. 2  illustrates exemplary FPGA and SPI PROM waveforms during FPGA configuration for the typical FPGA and SPI PROM connection of  FIG. 1 ; 
       FIG. 3  illustrates FPGA and SPI PROM connections according to embodiments of the present invention; and 
       FIG. 4  depicts a flow chart showing an exemplary FPGA configuration process according to embodiments of the present invention. 
   

   DETAILED DESCRIPTION 
   Although the exemplary device described herein is a FPGA, a number of different types of devices can be used, including PLAs and CPLDs. The following description herein will refer to a FPGA for convenience. 
     FIG. 1  illustrates exemplary FPGA and SPI PROM connections. FPGA  100  sends commands to the SPI PROM  110  via a four wire interface  120 . Specifically, the output of “Master Out Slave In” of FPGA  100 , shown as MOSI, is the input to “Serial In” of SPI PROM  110 . The output “Serial Out” of the SPI PROM is the input to “Master In Slave Out” of the FPGA, shown as MISO. Data is provided serially between the MOSI/Serial In and MISO/Serial Out connections. 
   FPGA  100  sends control signals on the chip select bar of the FPGA, shown as CS_B (_B indicating select is active low). The chip select signal CS_B is synchronized with the serial clock of the FPGA, shown as “Serial Clk.” The output of the serial clock of the FPGA is the input of the serial clock of the SPI PROM, shown as “Serial Clk.” The signals making up Interface  120  are used for configuration purposes. To configure the FPGA, the FPGA sends data such as a “read” command to the SPI PROM on MOSI, and the SPI PROM sends data to the FPGA on MISO to load the contents of the SPI PROM into the FPGA configuration memory. 
   The FPGA  100  of  FIG. 1  typically includes a core  130  and a configuration memory  160 . A core is a large general purpose logic function used as a building block in chip design, the core sometimes being a microprocessor or microcontroller. The configuration memory  160  stores data for programming the logic of the FPGA so that the FPGA forms a desired component. Pull-up resistors (not shown) typically found at the interface  120  because the FPGA  100  and the SPI PROM  110  may operate with different power supply voltages. 
   Conventional FPGAs have not yet made use of this available SPI PROM 24-bit address functionality. Currently, when programming or configuring one FPGA with one SPI PROM, the FPGA is loaded with contents starting from the SPI PROM 24-bit address of all zeros. 
     FIG. 2  illustrates exemplary FPGA and SPI PROM waveforms during FPGA configuration for the typical FPGA and SPI PROM connection of  FIG. 1 . For convenience, components carried over from  FIG. 1  to  FIG. 2  are similarly labeled. A weak pull-up voltage is shown on the three outputs of the FPGA in  FIG. 2 . Once the FPGA powers on, the FPGA outputs signals to the SPI PROM that are used to load the FPGA memory. The FPGA output signals include the serial clock on “Serial Clk,” and the chip select CS_B, on which the FPGA selects the SPI PROM. The FPGA output signals also include an “8-bit command” output by the FPGA on MOSI after an initial “Delay” to assure synchronization. SPI PROMs allow for a 24-bit address to be immediately loaded after the 8-bit command. The 24-bit address is typically twenty-four bits of zeros and represents the starting address of data to be read within the SPI PROM. The “24-bit Address” on MOSI is followed by another “Delay.” The SPI PROM then loads the “Data” on MISO to download the contents of the SPI PROM into FPGA memory. 
     FIG. 3  illustrates connection of a FPGA  300  and SPI PROM  310  according to embodiments of the present invention. Embodiments of the present invention incorporate a programmable address register  350  into a SPI state machine  340  in the FPGA  300 . For configuration purposes, when loading the contents of a SPI PROM  310  into FPGA configuration memory  360 , the FPGA  300  when powered up will output to SPI PROM  310  an 8-bit “read” command and a 24-bit programmable start address retrieved from the programmable address register  350  of the FPGA&#39;s SPI state machine  340 . The SPI PROM  310  then outputs its data to the FPGA  300 . The 24-bit programmable start address appended to the 8-bit read command will allow for multiple FPGA configurations, or “Config  1 ” through “Config N”  370   1N , to be loaded in FPGA  300  from the single SPI PROM  310  using embodiments of the present invention. An address of all zeros identifies the first configuration “Data  1 ”  390   1 , in the SPI PROM  310  similar to that stored in a conventional manner. Further, additional loadable start addresses “Start address Data  2 ” through “Start address Data N”  380   2−N  are depicted in the SPI PROM  310  along with configuration “Data  2 ” through configuration “Data N”  390   2−N . These addresses  380   2−N  allow addressing and subsequent loading of the additional configurations Data  2  through Data N  390   2−N  stored in the SPI PROM  310 . 
     FIG. 4  depicts a flow chart showing an exemplary FPGA configuration process according to embodiments of the present invention.  FIG. 4  is used in conjunction with  FIGS. 2 and 3 . The FPGA configuration process begins in step  405 . In step  410 , the FPGA  300  powers up and the 24-bit SPI address register  350  that was incorporated into the SPI state machine  350  of the FPGA  300  is set to zero. In step  415 , on the clock “Serial Clk” of interface  320 , the SPI state machine  340  of the FPGA  300  instructs the FPGA  300  to output the chip select CS_B to select the SPI PROM  310 . After a delay, the SPI state machine  340  of the FPGA  300  instructs the FPGA  300  to output an 8-bit command on MOSI, typically a “read” command. The SPI state machine  340  of the FPGA  300  will also instruct the FPGA to output the 24 bits of zeros from the SPI address register  350  on MOSI to the SPI PROM  310 , followed by another delay. The 24 bits of zeros represent the first address for configuration Data  1   390   1  within the SPI PROM  310 . 
   In step  420 , the SPI PROM  310  outputs a functional pattern on MISO to load on the FPGA  300 . The functional pattern includes Data  1   390   1  that starts at the first address of all zeros in the SPI PROM  310 . The core  330  of the FPGA handles storing this data sent by the SPI PROM to a first configuration Config  1   370   1  in the FPGA memory. The functional pattern loaded into the FPGA  300  by the SPI PROM  310  also includes the 24-bit next starting address, or Start address Data  2   380   2 , within the SPI PROM for the next configuration of the FPGA. This 24-bit address is stored in the SPI address register  350  of the FPGA&#39;s SPI state machine  340 . 
   The functional pattern also includes a bit that turns on or off multi-boot mode, or capability, of the FPGA  300 . The FPGA  300  decodes the functional pattern to turn on/off multi-boot mode. The multi-boot bit is routed to the FPGA core  330 , or configuration controller, and allows the core to start the next configuration sequence of the FPGA. The multi-boot mode of the FPGA allows the loading of various multi-boot kernels using a single compliant boot loader. The multi-boot mode is turned on or off based on the configuration options the user feeds the FPGA&#39;s SPI state machine  340 . A single SPI PROM can store multiple boot patterns, or Data  1  through Data N  390   1−N , each boot pattern at a different address, including Start address Data  2  through Start address Data N  380   2−N , within the SPI PROM  310 . Each boot pattern in an SPI PROM can be used multiple times. Once the multi-boot mode is turned off, the 24-bit address identifying the start address of the next configuration in the SPI PROM previously sent to and stored by the FPGA is unneeded. The functional pattern for the multi-boot mode includes two or more multi-boot mode bits, such that the extra bit(s) is used for redundancy. 
   In step  425 , the FPGA is started up from the first boot. If in step  430 , the multi-boot mode is active, then in step  435 , the FPGA is exercised with the last functional pattern from the SPI PROM  310  in normal user-mode. If in step  440  a new boot from the core is not triggered, the FPGA continues to be exercised in step  435  and additional configurations are not loaded. If in step  440 , a new boot from the core is triggered, the process loops back to step  415 . In step  415 , the process enters the loop, and on the clock “Serial Clk,” the SPI state machine of the FPGA instructs the FPGA to output the chip select CS_B to select the SPI PROM. After a delay, the SPI state machine of the FPGA instructs the FPGA to output an 8-bit read command on MOSI, as well as the pre-stored 24-bit starting address, now Start address Data  2   380   2 , from the SPI address register  350  of the FPGA&#39;s SPI state machine  340  that was sent by the SPI PROM  310  on the previous iteration. In step  420 , the process proceeds as described above for the first iteration of the loop. In step  425 , the FPGA is started up from the new boot triggered from the core in step  440 . 
   By allowing a 24-bit address to be programmed into the FPGA&#39;s SPI state machine  340 , anytime the SPI PROM  310  is queried by the FPGA  300  the SPI PROM  310  accesses data starting at that new address. Because of this, every time the SPI PROM  310  is queried, it can be given a different address and so load the FPGA  300  with a completely different configuration pattern each time. 
   The process can be repeated as many times as desired by the programmer of the SPI PROM and the FPGA. If in step  430 , the most recently loaded pattern has disabled the multi-boot mode, making the multi-boot mode no longer active, then in step  445 , the FPGA is exercised with the last functional pattern from the SPI PROM. In step  450 , the process ends. 
   In some embodiments, a programmable 8-bit command can be used, as opposed to the hard coded 8-bit command of the embodiments above. The programmable 8-bit command can be used in addition to the programmable 24-bit address register. 
   In some embodiments, SPI commands other than read can include, but are not limited to, programming, erasing, or getting the idcode for the SPI PROM. 
   In some embodiments, the 24-bit address allows for any number of FPGA configurations from a single SPI PROM. The 24-bit address also allows for any number of FPGA configurations from multiple SPI PROMs, using a decode external to the FPGA of the most significant bits (MSBs) as SPI PROM chip selects. The FPGA configurations from multiple SPI PROMS can be read using multiple address registers, multiple CS_B pins, or the user could direct the CS_B signal to different SPI PROMs on the user&#39;s board as needed. 
   In some embodiments, instead of turning off the multi-boot mode in step  420 , the user can leave multi-boot mode on in step  420  but choose not to exercise the FPGA at any point. 
   The SPI PROM can be located external to the FPGA or internal to the FPGA. Some PLDs are a combination of a FPGA and a SPI PROM stacked inside of the same package. 
   Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. For example, although 8-bit commands and 24-bit addresses are used in the descriptions of embodiments herein, a person of ordinary skill in the art could use other length commands and addresses. Many additional modifications will fall within the scope of the invention, as that scope is defined by the following claims.