Abstract:
A torque meter for measuring the torque of a rotating shaft includes at least two sensing devices providing pulses corresponding to the rotation of the shaft. A pulse source provides clock pulses. A network connected to the sensors determines if the shaft is rotating in the proper direction and provides a signal accordingly. A circuit receiving the pulses from the sensors, the signal from the network and the clock pulses provides groups of clock pulses wherein the number of pulses in each group corresponds to the torque of the shaft when the shaft is rotating in the proper direction.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to meters in general and, more particularly, to torque meters. 
     SUMMARY OF THE INVENTION 
     A torque meter for measuring a torque on a rotating shaft includes at least two sensors having a predetermined relationship to the shaft and providing shaft pulses at the same frequency but differing in phase, said phase difference corresponding to the torque of the shaft. A clock provides clock pulses having a substantially greater frequency than the frequency of the shaft pulses. A circuit determines if the shaft is rotating in a proper direction and provides a signal accordingly. A network connected to the sensors, to the circuit and to the pulse source provides groups of clock pulses in accordance with the shaft pulses and the signal from the circuit so that the number of pulses in each group corresponds to the torque of the shaft when the shaft is rotating in the proper direction. 
     The objects and advantages of the invention will appear more fully hereinafter from a consideration of the detailed description which follows, taken together with the accompanying drawings wherein one embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawings are for illustration purposes only and are not to be construed as defining the limits of the invention. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram of a torque meter, constructed in accordance with the present invention for measuring the torque in a rotating shaft. 
     FIGS. 2A through 2H are graphical representations of voltages occurring during operation of the torque meter of FIG. 1. 
     FIG. 3 is a detailed block diagram of the detector shown in FIG. 1. 
    
    
     DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, there is shown a torque meter having a wheel 1, with teeth mounted on a shaft 3. At another location on shaft 3, there is mounted another wheel 5 substantially identical to wheel 1. As shaft 3 is rotated, the teeth in wheels 1, 5, pass pick-up coils 7 and 9, respectively, which are connected to ground 10. Each coil has a magnetized core. An alternate arrangement would have each tooth of the wheels magnetized instead of the cores of the coils. As each tooth passes a corresponding coil an electric voltage is induced therein so that during rotation of shaft 3, coils 7 and 9 provide pulses. 
     The pulses from coils 7, 9 are applied to squaring amplifiers 11 and 14, respectively, which provide pulses E 1  and E 2 , respectively, as shown in FIGS. 2B and 2A, respectively. Squaring amplifiers 11 and 14 may be omitted if the pulses provided by coils 7, 9 are suitable. Pulses E 1 , E 2  from squaring amplifiers 11 and 14, respectively, are applied to an exclusive NOR gate 17 and to a detector 18. 
     When amplifiers 11, 14 are simultaneously providing a pulse E 1  and E 2 , exclusive NOR gate 17 provides a high logic level output. When one and only one of the amplifiers 11 or 14 is providing a pulse, exclusive NOR gate 17 provides a low logic level output. If both amplifiers 11 and 14 are not providing a pulse exclusive NOR gate 17 produces a high output. Thus, the duration of a low output from exclusive NOR gate 17 corresponds to the torque. The output from exclusive NOR gate 17 is applied to an OR gate 20. 
     Pulses E 2  are applied to a phase lock-loop comprising a phase comparator 23 providing a voltage to a filter 25 which provides a filtered voltage to a voltage controlled oscillator 27. The voltage provided by comparator 23 corresponds to the phase difference between pulses E 2  from amplifier 14 and other pulses applied to comparator 23, as hereinafter explained. Oscillator 27 provides a plurality of clock pulses whose frequency is determined by the voltage applied to oscillator 27. The clock pulses are provided to a `divide by N` divider 30 whose pulses are applied to phase comparator 23. In operation oscillator 27 provides the clock pulses at a frequency N times greater than the frequency of pulses E 2  provided by squaring amplifier 14. 
     The clock pulses from oscillator 27 are provided to OR gate 20. OR gate 20 provides an output to a `divide by 2 T` divider 35 where T is the number of teeth on either wheel 1 or 5. The operation of exclusive NOR gate 17 and OR gate 20 is such that while amplifiers 11 and 14 simultaneously are providing pulses E 1  and E 2 , respectively, the high output from NOR gate 17 in effect blanks out the clock pulses from oscillator 27. When one of the amplifiers 11, 14, does not provide a pulse, while the other amplifier is providing a pulse, OR gate 20 provides pulses to divider 35. The pulses from divider 35 are provided to counter means 37 for counting. 
     The pulses from amplifier 14 are applied to a `divide by T` divider 40 which in effect provides a pulse for every complete rotation of wheel 5. The pulses from divider 40 are applied to delay means 43 and to an AND gate 44. Delay means 43 provides a delayed pulse to divider 35, to counter means 37, and to an inverter 46. The leading edge of the delayed pulse resets divider 35 and counter means 37 while the trailing edge loads counter means 37 with digital signals provided by pre-set means 50. Inverter 46 provides inverted pulses E 3  to detector 18 which provides a control signal E 4  to light means 41 and to an AND gate 44. AND gate 44 is controlled by signal E 4  to pass or block the pulses from `divide by T` 40. The passed pulses are provided to latch means 45. 
     Referring now to FIGS. 1, 2A through 2H, and 3, detector 18 determines whether the shaft is rotating in a wrong direction or that amplifier 14 is providing pulses as a result of vibration or noise. Reverse rotation yields an erroneous indication since the teeth on wheels 1 and 5 are rarely in alignment and do not have the same dimensions due to machining errors. There is a small offset in the number of pulses occurring when the shaft is rotating in one direction which is accounted for in calibrating the torque meter. However, when the shaft is rotating in an opposite direction a different offset in the number of pulses occurs which results in an erroneous count in counter means 37. Should either of these conditions occur, the current erroneous data is prevented from entering latch means 45 so that latch means 45 provides the latest valid data. 
     Pulses E 2  are applied to the clock or `C` input of `D` type flip-flop 89 and to an inverter 90, while pulses E 1  are applied to the data or `D` input of `D` type flip-flop 89 and to an inverter 95. Inverters 90, 95 provide inverted pulses E 2  and E 1 , respectively, to the `C` input and the D input, respectively, of flip-flop 94. The Q outputs of flip-flops 89, 94 are provided to an OR gate 97. OR gate 97 is connected to a set or `S` input of yet another `D` type flip-flop 100. Pulses E 3  are applied to the `C` input of flip-flop 100 while flip-flop 100 `D` input is grounded. Flip-flop 100 provides its Q output as signal E 4 . A `D` type flip-flop will provide its Q and Q outputs at low and high logic levels, respectively, when in a clear state and at high and low logic levels, respectively, when in a set state. Further, when an input of one logic level is applied to the `D`, the flip-flop is triggered by a rising pulse to provide a Q output at the same logic level as provided to the `D` input. 
     In normal operation, pulses E 1  lag pulses E 2 . Thus, when pulse E 2  is rising pulse E 1  is low so that flip-flop 89 is triggered to provide its Q output at a low logic level. Similarly, due to the effect of inverters 90 and 95, flip-flop 94 is triggered by the trailing edge of pulses E 2  to provide its Q output at a low logic level. Thus for normal rotation both flip-flops 89, 94 provide low logic level Q outputs to OR gate 97 causing it to provide a low logic level output to flip-flop 100. Flip-flop 100 is not affected by the low logic level output from OR gate 97 and continues to provide signal E 4  at a high logic level. 
     When reverse rotation occurs, pulses E 1  lead pulses E 2  as is shown in FIGS. 2C and 2D so that pulse E 1  is at a high level when pulse E 2  rises. In response to this condition, flip-flop 89 is triggered to provide its Q output at a high logic level. Once this occurs, flip-flop 94 is of no importance. Since flip-flop 89 is at a high logic level, OR gate 97 provides a high level output triggering flip-flop 100 to a set state. While in a set state, flip-flop 100 provides signal E 4  at a low logic level to disable AND gate 44 to prevent the entry of data into latch means 45. Thus latch means 45 provides signals corresponding to the last valid data obtained. Further, signal E 4  is going to a low logic level causes light means 42 to light thus visibly indicating malfunctioning. 
     Signal E 3 , as can be seen in the description regarding FIG. 1, is a pulse which occurs every cycle. Its occurrance when flip-flop 100 is in a set state, resets flip-flop 100 to a clear state causing signal E 4  to go to a high logic level. Latch means 45 can then again enter valid data. 
     When noise or vibration causes an amplifier 11 or 14 to provide an erroneous output, that condition may be seen either in FIGS. 2E, 2F or 2G, 2H. With regard to FIGS. 2F and 2G, the output of an amplifier 11 or 14 should be at a steady state, which may be at a high logic level or at a low logic level. The solid line is for a low logic level, while the dash line represents a high logic level steady output. When pulse E 1  does not occur and the output of amplifier 11 is at a high logic level, flip-flop 89 is triggered by the leading edge of a pulse E 2 . Similarly if the signal from amplifier 11 is at a steady state low logic level, the trailing edge of a pulse E 2  triggers flip-flop 94 to provide its Q output at a high logic level. As noted hereinbefore, a high logic level Q output from either flip-flop 89 or 94, causes flip-flop 100 to be triggered to a set state. 
     A final erroneous condition, that is where amplifier 14 provides a steady state signal, while noise or vibration cause amplifier 11 to provide pulses E 1 , is not controlled by detector 89 but by the inherent operation of system itself. Since amplifier 14 is not providing pulses E 2 , `divide by T` 40 does not provide a pulse therefor, latch means 45 cannot enter the erroneous data. 
     It would be obvious to one skilled in the art that if only reverse rotation was to be detected flip-flop 89 would be needed solely or in conjunction with flip-flop 106. For the solo case, flip-flop 89 would provide its output as signal E 4  and there would be no cyclic resetting of flip-flop 89. The resetting would occur with normal rotation. 
     The invention hereinbefore described is a digital torque meter for measuring the torque on a rotating shaft. The torque is determined by developing two signals whose difference in phase corresponds to the torque experienced by the shaft. The phase difference is then used to generate pulses corresponding in number to the torque. The pulses are then counted, displayed and recorded. The torque meter does not record and display erroneous data due to reverse rotation of the shaft or due to vibration or noise.