Abstract:
The present invention relates to a method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising: attaching a post wafer to a resonator wafer, forming a bottom post from the post wafer being attached to the resonator wafer, attaching the resonator wafer to a base wafer, wherein the bottom post fits into a post hole in the base wafer, forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis, preparing a cap with backside metallization, and attaching a cap wafer on top of the base wafer. The present invention relates further to a gyroscope containing an integrated post with on or off-chip electronics.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention refers to an integrated all-Si capacitive microgyroscope with vertical differential Sense and Control and process for preparing an integrated all-Si capacitive microgyro with vertical differential Sense. 
   2. Description of Related Art 
   U.S. Pat. No. 5,894,090 to Tang et al., which is incorporated herein by reference, discloses a micromachined symmetrical leaf structure having a plurality of symmetrically disposed leaves about a defined center. At least one micromachined spring is disposed symmetrically with respect to the symmetrical leaf structure and supporting the symmetrical leaf structure, a rim/base structure to which the spring is coupled. The rim/base structure includes a plurality of sensing and drive electrodes and a circuit electrically coupled to the electrodes included within the rim/base structure. The circuit provides drive signals to the drive electrodes to oscillate the symmetrical leaf structure and to receive a sensing signal from the sensing electrodes to detect response of the oscillating symmetrical leaf structure to physical phenomena exterior to the micromachined resonator. The micromachined resonator has a manually inserted post. It shows a lack of a silicon based vacuum encapsulation. A low yield is obtained during the separation. The manufacturing of the resonator involves high fabrication costs. It shows large vibration sensitivity and no clear path to electronic integration. 
   The known manufacturing processes make it very difficult to manufacture a microgyroscope. The central post is inserted by hand, the device has to be vacuum packaged in a custom package and there is no ability to integrate control electronics with the silicon structure. 
   What is needed is a cloverleaf microgyroscope and a process for manufacturing a cloverleaf microgyroscope with an integrated central post and electronics with the resonator and vacuum package at wafer-level with a single crystal silicon construction. 
   BRIEF SUMMARY OF THE INVENTION 
   This invention addresses the above needs. 
   One aspect of the present invention is a method of manufacturing a process for preparing an integrated all-Si capacitive microgyro with vertical differential Sense comprising:
         a) attaching a post wafer to a resonator wafer,   b) forming a bottom post from the post wafer,   c) attaching the resonator wafer to a base wafer, wherein the bottom post fits into a post hole in the base wafer,   d) forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis,   e) preparing a cap with backside metallization, and   f) attaching a cap wafer on top of the base wafer.       

   Another aspect of the present invention is an integrated all-Si capacitive microgyro with vertical differential Sense manufactured by this method. 
   For improved vibration immunity, a set of control and sense electrodes located above the resonator offers advantages. This invention refers to a method for adding an array of bump bonds on the base wafer that then forms electrical interconnects to the top electrodes when the capping wafer is bonded to the base wafer. A cut-out in the resonator frame allows the interconnects to be connected to the top electrodes without having to transverse deep groves. The height of the added bump bonds are adjustable to be equal to the metal seal ring on the base wafer so that vacuum sealing and top electrode connection is performed in the same bonding step. 
   Since the resonator is supported by four springs attached to an outer frame, any vibration along the axis of the post can deflect the resonator and thereby change the gap spacing between the resonator and the electrodes. This change in gap spacing results in changes in the detected capacitance for a given absolute deflection and changes in the rebalance force for a given applied voltage. By using differential detection and drive, these changes can be minimized, but not totally eliminated, and thereby the scale factor of the device can be stabilized during high loading. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     These and other features, aspects and advantages of the present invention will become better understood with reference to the following description, appended claims, and accompanying drawings where 
       FIG. 1   a  is a top plan view of the preferred starting material of a resonator SOI wafer A and  FIG. 1   b  is a cross-sectional view through wafer A of  FIG. 1   a  at line  1   b — 1   b  of the resonator SOI wafer A; 
       FIG. 2   a  is a top plan view of the preferred starting material of a resonator SOI wafer A and  FIG. 2   b  is a cross-sectional view through wafer A of  FIG. 2   a  at line  2   b — 2   b  of the resonator SOI wafer A; 
       FIG. 3   a  is a top plan view of the preferred starting material of a resonator SOI wafer B and  FIG. 3   b  is a cross-sectional view through wafer B of  FIG. 3   a  at line  3   b — 3   b  of the bottom-portion wafer B; 
       FIG. 4   a  is a cross-sectional view at line  3   b — 3   b  of the bond wafer B; 
       FIG. 4   b  is a cross-sectional view at line  2   b — 2   b  of bonded to wafer A; 
       FIG. 5   a  is a top plan view of the resonator SOI wafer A and a bottom post B′ and  FIG. 5   b  is a cross-sectional view through wafer A and bottom post B′ of  FIG. 5   a  at line  5   b — 5   b  of the resonator SOI wafer A and bottom post B′; 
       FIG. 6   a  is a top plan view of the resonator SOI wafer A and a bottom post B′ and  FIG. 6   b  is a cross-sectional view through wafer A and bottom post B′ of  FIG. 6   a  at line  6   b — 6   b  of the resonator SOI wafer A and bottom post B′ after several contacts are attached to it; 
       FIG. 7   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 7   b  is a cross-sectional view through wafer C of  FIG. 7   a  at line  7   b — 7   b  of the base wafer C; 
       FIG. 8   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 8   b  is a cross-sectional view through wafer C  FIG. 8   a  at line  8   b — 8   b  of the base wafer C, after on both surfaces of base wafer C a silicon dioxide layer is grown; 
       FIG. 9   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 9   b  is a cross-sectional view through wafer C of  FIG. 9   a  at line  9   b — 9   b  of the base wafer C, after pillar fabrication; 
       FIG. 10   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 10   b  is a cross-sectional view through wafer C of  FIG. 10   a  at line  10   b — 10   b  of the base wafer C, after on both surfaces of base wafer C a silicon dioxide layer is grown; 
       FIG. 11   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 11   b  is a cross-sectional view through wafer C of  FIG. 11   a  at line  11   b — 11   b  of the base wafer C after an ohmic contact and interconnect metal patterning; 
       FIG. 12   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 12   b  is a cross-sectional view through wafer C of  FIG. 12   a  at line  12   b — 12   b  of the base wafer C after electrode, bond pad, and wire bond metal were provided on the base wafer C; 
       FIG. 13   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 13   b  is a cross-sectional view through wafer C of  FIG. 13   a  at line  13   b — 13   b  of the base wafer C after silicon nitride is provided on the base wafer C; 
       FIG. 14   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 14   b  is a cross-sectional view through wafer C of  FIG. 14   a  at line  14   b — 14   b  of the base wafer C after a seal ring deposition; 
       FIG. 15   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 15   b  is a cross-sectional view through wafer C of  FIG. 15   a  at line  15   b — 15   b  of the base wafer C after a post hole etch is carried out in the base wafer C; 
       FIG. 16   a  is a top plan view of the preferred starting material of the bottom surface of wafer A and  FIG. 16   b  is a cross-sectional view through the base wafer A, post B′, and base wafer C of  FIG. 16   a  at line  16   b — 16   b  of the base wafer A, post B′, and base wafer C; 
       FIG. 17   a  is a top plan view depicting post A′ and base wafer C and  FIG. 17   b  is a cross-sectional view through the base wafer A, post B′, and base wafer C of  FIG. 17   a  at line  17   b — 17   b  depicting post A′, post B′, and base wafer C after post formation; 
       FIG. 18   a  is a bottom view of the preferred starting material of a cap wafer D and  FIG. 18   b  is a cross-sectional view through the cap wafer D of  FIG. 18   a  at line  18   b — 18   b  of the cap wafer D; 
       FIG. 19   a  is a bottom view of the preferred starting material of a cap wafer D and  FIG. 19   b  is a cross-sectional view through the cap wafer D of  FIG. 19   a  at line  19   b — 19   b  of the cap wafer D after preparing main cavity formation; 
       FIG. 20   a  is a bottom plan view of the preferred starting material of a cap wafer D and  FIG. 20   b  is a cross-sectional view through the cap wafer D of  FIG. 20   a  at line  20   b — 20   b  of the cap wafer D thermal oxidation; 
       FIG. 21   a  is a bottom plan view of the preferred starting material of a cap wafer D and  FIG. 21   b  is a cross-sectional view through the cap wafer D of  FIG. 21   a  at line  21   b — 21   b  of the cap wafer D after opening of oxide holes; 
       FIG. 22   a  is a bottom plan view of the preferred starting material of a cap wafer D and  FIG. 22   b  is a cross-sectional view through the cap wafer D of  FIG. 22   a  at line  22   b — 22   b  of the cap wafer D after backside metallization; 
       FIG. 23   a  is a bottom plan view of the preferred starting material of a cap wafer D and  FIG. 23   b  is a cross-sectional view through the cap wafer D of  FIG. 23   a  at line  23   b — 23   b  of the cap wafer D after backside solder metallization; 
       FIG. 24   a  is a bottom plan view of the preferred starting material of a cap wafer D and  FIG. 24   b  is a cross-sectional view through the cap wafer D of  FIG. 2   a  at line  24   b — 24   b  of the cap wafer D after formation of backside cavities; 
       FIG. 25   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 25   b  is a cross-sectional view through the cap wafer D and the base wafer C of FIG; 
       FIG. 26   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 26   b  is a cross-sectional view through the cap wafer D and the base wafer C of  FIG. 26   a  at line  26   b — 26   b  of the cap wafer D bonded to the base wafer C after etching remaining silicon in the cap wafer D, to produce a channel for a wire dicing; 
       FIG. 27   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 27   b  is a cross-sectional view through the cap wafer D and the base wafer C of  FIG. 27   a  at line  27   b — 27   b  of the cap wafer D bonded to the base wafer C after dicing and ball-bonding of wires. 
   

   DETAILED DESCRIPTION 
   The resonator wafer A, preferably a silicon-on-insulator (SOI) wafer, is preferably prepared first. On a bulk silicon base  1  having a preferable thickness of ≦500 μm, which is optionally lightly-doped bulk silicon about 1e15 cm −3 , a silicon dioxide layer  2  having a preferable thickness of ≦2 μm is formed preferably by thermal oxidation at a temperature between 800° C. and 1000° C. On top of the silicon dioxide layer  2  a heavily doped silicon epi-layer, p-type, 1e19–1e20 cm −3    3  is preferably provided having a preferable thickness of 10 μm to 20 μm, as shown in  FIGS. 1   a  and  1   b.    
   Then the cloverleaf petal and spring of the resonator wafer A is prepared. Parts of the heavily-doped silicon epi-layer  3  are removed, preferably by photoresist lithography, deep reactive ion etching (DRIE) and photoresist removal, as shown in  FIGS. 2   a  and  2   b . Photoresist lithography and DRIE are described in inter alia Veljko Milanovic et al. “Deep Reactive Ion Etching for Lateral Field Emission Devices”, IEEE Electron Device Letters, Vol. 21, No. 6, June 2000, which is incorporated herein by reference. 
   The process preferably comprises:
         1. The top silicon layer of the wafer is coated with a layer of photoresist.   2. Light from an illuminator is projected through a mask that contains the pattern to be created on the wafer. The light patterns that pass through the mask are projected onto the photoresist-coated layer.   3. The photoresist that is exposed to the light becomes soluble and is rinsed away, leaving miniature images of the mask pattern. It remains as an etch mask on the silicon surface of the wafer.   4. Regions unprotected by photoresist are etched preferably by gases utilizing Deep Reactive Ion Etching (DRIE). DRIE involves repeated exposure of a photoresist-masked silicon wafer to an etchant (usually SF 6 ) plasma in alternation with a passivant (usually C 4 F 8 ) plasma. So the etching process preferably cycles between etching and deposition steps several times to achieve a deep etching with a quite vertical profile. The etch rate, profile and selectivity to the mask are controlled by adjusting etch and passivation efficiency or the time ratio of the two steps. Average etch rate is around 2.7 μm/min, and etching is terminated when the SiO 2  layer  2  is reached. The SiO 2  layer  2  serves as a stop layer.   5. After the DRIE process the photoresist is removed. Photoresist removal with solvents is a preferred process in the semiconductor manufacturing and is used extensively after any metal processing. Organic strippers may have any number of different components such as NMP, glycol ether, amine, and DMSO.       

   The process parameters for the photoresist lithography are preferably as follows: 
   a) Resist Application.
         2.07 μm   AZI 1350J, 3500 RPM   100° C. Hotplate bake for 45 sec.       

   b) Resist Exposure
         Photomask # C1   Time=7 sec.   Mask Offset=0.2 μm       

   c) Develop &amp; Bake:
         MF351:H 2 O, 1:5 for 60 sec   100C Hotplate Bake for 45 sec.       

   The bottom post wafer B is prepared next. On a bulk silicon base  1  having a preferable thickness of ≦500 μm, which is optionally lightly-doped bulk silicon layer (about 1e15 cm −3 )  2  a silicon dioxide layer, having a preferable thickness of ≦2 μm, is formed preferably by thermal oxidation between 800° C. and 1000° C. as shown in  FIGS. 3   a  and  3   b.    
   Wafer B is bonded to resonator wafer A. The bondage between heavily-doped silicon epi-layer  3  of the bottom portion of wafer A and the silicon dioxide layer  2  of the wafer B may be achieved by heating to a temperature from 800° C. to 1000° C., as diagrammatically shown in  FIGS. 4   a  and  4   b . In this process the SiO 2  layer  2  of wafer B is preferably bonded to the heavily doped silicon epi-layer,  3  of the SOI wafer A. The epi-layer  3  is preferably p-type, 1e19–1e20 cm −3 . 
   Then the bottom post B′ and rib pattern are prepared. The bulk silicon layer  1  and silicon dioxide  2  of the wafer B have been partially removed to yield a post B′ as shown in  FIGS. 5   a  and  5   b.    
   The process preferably comprises:
         1. Coating the top silicon layer  1  of the wafer B with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern to be created on the wafer B,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer B.   4. Etching silicon layer  1  unprotected by photoresist by gases utilizing the deep reactive ion etch (DRIE).   5. Removing SiO 2  layer  2  of wafer B by CF 4 /O 2  plasma etch, and   6. Removing photoresist on the surface of the post B′.       

   Then ohmic contacts are formed. On the heavily doped silicon epi-layer  3  several contacts  4  are preferably formed by sputtering metal. The contacts  4  are placed preferably symmetrically around the post B′. The contacts  4  contain preferably Ti/Pd/Au, Ti/Pt/Au or mixtures thereof. The contacts  4  are prepared, for example, by photoresist lithography, wet etching the metal and removing the photoresist (photoresist spray lithography, metallization Ti/Pt/Au and metal lift-off), as shown in  FIGS. 6   a  and  6   b . Metal liftoff is a common means of creating narrow metal lines for metals. A metal liftoff process is preferably done in a spray system. The process including resist photoresist, spray lithography, metallization and metal lift-off is described for example, in inter alia, in Andrea Via et al. “Metal Lift-off on InP HBTs Using Carbon Dioxide Snow Spray” (see: www1.boc.com/eco-snow/pdf/CS-MAX%202002.pdf.) 
   The process preferably comprises:
         1. Coating the heavily doped silicon epi-layer, p-type, 1e19–1e20 cm −3    3  of the wafer A by metallization with sputter metal (Ti/Pd/Au).   2. Coating metal (Ti/Pd/Au) on the layer  3  with a layer of photoresist,   3. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contacts  4  to be created, on the layer  3  of wafer A,   4. Washing the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer A,
           Removing the metal which is not covered by photoresist by wet etch,   
           5. Removing photoresist on the surface of the ohmic contacts  4 .       

   The process for photoresist spray lithography, metallization Ti/Pt/Au and metal lift-off preferably comprises:
         1. Coating layer  3  with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contacts Ti/Pt/Au  4  to be created, on the layer on the layer  3  of wafer A,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer A,
           Removing the metal which is not covered by photoresist by wet etch,   
           4. Depositing Ti/Pt/Au  4  by spray lithography,   5. Removing Ti/Pt/Au  4  covering the photoresist by a metal lift-off process,   6. Stripping the remaining photoresist yielding an Ti/Pt/Au  4  pattern on the surface of wafer C.       

   Then a base wafer C is prepared. The preferred starting material  5  of the base wafer C has a preferable thickness of about ≦800 μm and preferably contains a moderately doped silicon substrate p-type, 1e 19 cm −3 , as shown in  FIGS. 7   a  and  7   b.    
   On both surfaces of the preferred starting material  5  of the base wafer C a silicon dioxide layer  2  of ≦0.3 μm-thick is provided, preferably by thermal oxidation at a temperature of about 950° C., as shown in  FIGS. 8   a  and  8   b.    
   Then a pillar fabrication is carried out. From the preferred starting silicon material  5  a thickness of preferably about 5 μm to 8 μm is removed by photoresist lithography, wet etch SiO 2  and photoresist removal, wet KOH etch of silicon and SiO 2  removal in order to form pillars PI, as shown in  FIGS. 9   a  and  9   b.    
   The process preferably comprises:
         1. Coating the top and bottom SiO 2  layer  2  of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the pillars PI to be created, on the top layer  2  of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C,   4. Removing the SiO 2  layer  2 , which is not covered by photoresist, by CF 4 /O 2  plasma etch,   5. Removing 5–8 μm of moderate doped Si preferred starting material  5  by wet KOH etch to produce a cavity CA,   6. Removing remaining photoresist, and   7. Removing SiO 2  layer  2  on the pillars and on the bottom layer by CF 4 /O 2  plasma etch.       

   On both surfaces of the preferred starting material  5  of the base wafer C (with pillars PI) a SiO 2  layer of ≦2 μm thick is provided, preferably by thermal oxidation at a temperature of about 1050° C., as shown in  FIGS. 10   a  and  10   b.    
   An ohmic contact metal Al  6  and interconnect metal Ti/Al  7  may be attached to the preferred starting material  5  of the base wafer C by photoresist spray lithography and metal deposition and liftoff, as shown in  FIGS. 11   a  and  11  b. 
   The process preferably comprises:
         1. Coating SiO 2  layer  2  with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contact Al  6  to be created, on the layer  2  of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C,   4. Removing the SiO 2  layer  2  by wet etch which is not covered by photoresist,   5. Depositing Al  6  by spray lithography,   6. Removing Al  6  covering the photoresist by a metal lift-off process,   7. Stripping the remaining photoresist yielding an Al  6  pattern on the to surface of wafer C,   8. Coating the top layer  2  of wafer C again with a layer of photoresist,   9. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the interconnect metal Ti/Al  7  to be created, on the SiO 2  layer  2  of wafer C,   10. Depositing Ti/Al  7  by spray lithography,   11. Removing Ti/Al  7  covering the photoresist by a metal lift-off process,   12. Stripping remaining photoresist and yielding a Ti/Al  7  pattern on the wafer C.       

   Electrode metal (drive/sense electrodes) Ti/Pt/Au  8   b , wire bond metal Ti/Pt/Au  8   c , and wafer bonding metal Ti/Pt/Au  8   d  may be provided by photoresist lithography and metal deposition and liftoff, as shown in  FIGS. 12   a  and  12   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the wire bond metal Ti/Pt/Au  8  to be created, on the top surface of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer C,   4. Depositing Ti/PT/Au  8  on the surface of wafer C by spray lithography,   5. Removing excess Ti/PT/Au  8  covering the photoresist by a metal lift-off process,   6. Stripping remaining photoresist yielding a wire bond Ti/Pt/Au  8 .       

   A Si 3 N 4  nitride  9  layer is preferably provided on the top of base wafer C by dielectric layer deposition and patterning. A Si 3 N 4  layer 9≦0.5 μm thick is preferably provided by deposition and photoresist lithography and removed by CF 4 /O 2  plasma etch of Si 3 N 4  in device and wire bond regions and by photoresist removal, as shown in  FIGS. 13   a  and  13   b.    
   The process preferably comprises:
         1. Coating the surface of wafer C with Si 3 N 4    9 , with a thickness of about 0.5 μm,   2. Coating Si 3 N 4    9  with a layer of photoresist,   3. Projecting light from an illuminator through a mask that contains the pattern, namely covering the places for the interconnect metal dielectric layer Si 3 N 4    9  to be created, on the surface of wafer C,   4. Washing the exposed regions of the photoresist layer and leaving mask on Si 3 N 4    9 ,   5. Removing the Si 3 N 4    9  which is not covered by CF 4 /O 2  plasma etch, and   6. Stripping remaining photoresist.       

   A seal ring  8   a  containing Ti/Pt/Au is provided on the silicon nitride  9  by metal patterning and deposition, particularly by photoresist lithography spray on thick resist and metal deposition and liftoff, as shown in  FIGS. 14   a  and  14   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for seal ring metal  8   a  containing Ti/Pt/Au provided on the silicon nitride  9  to be created, on the top surface of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer C,   4. Depositing Ti/Pt/Au on the surface of wafer C,   5. Removing excess Ti/Pt/Au  8   a  covering the photoresist by a metal lift-off process,   6. Stripping remaining photoresist yielding removing of excess Ti/Pt/Au  8   a  covering the photoresist by a metal lift-off process,   7. Stripping remaining photoresist yielding a seal ring  8   a  containing Ti/Pt/Au on the silicon nitride  9 .       

   As a next step a post hole etch  5 ′ is preferably carried out by photoresist lithography (spray on thick resist), CF 4 /O 2  plasma etch of silicon dioxide in the hole region, DRIE of silicon hole and photoresist removal as shown in  FIGS. 15   a  and  15   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region, on the top surface of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer C,   4. CF 4 /O 2  plasma etch of silicon dioxide in hole region,   5. DRIE remove to create a silicon hole, and   6. Stripping the remaining photoresist layer.       

   As a next step, a bonding of resonator wafer A according to  FIG. 6   b  and to base wafer C according to  FIG. 15   b  is carried out preferably by an Au to Au thermo compression bond at a temperature of 300° C. to 400° C., as shown in  FIGS. 16   a  and  16   b . The bonding is carried out between the contacts  4  of resonator wafer A-B and the seal ring metal  8   a  of the base wafer C. Post B′ of resonator wafer A-B fits into the post hole  5 ′ of base wafer C. 
   The post fabrication on wafer A is preferably carried out by photoresist lithography (spray on thick resist), CF 4 /O 2  plasma etching of silicon dioxide, photoresist removal by dry etch. Thereby a post A′ and optional frame formation in the top layer A″ is obtained, as shown in  FIGS. 17   a  and  17   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer A with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region on the top surface of wafer A,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer A,   4. DRIE remove of silicon from wafer A,   5. CF 4 /O 2  plasma etch of silicon dioxide from wafer A, whereby a post A′ and optional frame formation in the top layer A″ is obtained, and   6. Stripping the remaining photoresist layer.       

   A cap wafer D is prepared with a preferred starting material of lightly doped bulk silicon  1  having a thickness of ≦800 μm and having on top and bottom a thin silicon dioxide layer  2 , as shown in  FIGS. 18   a  and  18   b.    
     FIG. 19  to  FIG. 24  show the preferred preparation of the cap, which has a backside metallization. The backside metallization is inside of the integrated all-Si capacitive microgyro after the cap wafer D is bonded to the base wafer C. 
   A main cavity  15  is preferably formed on the backside of the cap wafer D by photoresist lithography, DRIE and photoresist removal, as shown in  FIGS. 19   a  and  19   b.    
   The process preferably comprises:
         1. Coating the bottom silicon  1  of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the cavity  15  to be created,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the silicon  1  of the wafer C patterning the cavity  15 ,   4. Removing 25–35 μm of moderate doped Si preferred starting material  1  by DRIE to yield the cavity  15 , and removing remaining photoresist.       

   The cap wafer D is preferably treated by 1050° C. in a furnace yielding a SiO 2  layer  2  on the top and bottom side of the silicon  1 , as shown in  FIGS. 20   a  and  20   b.    
   An opening  1   b  into the top silicon dioxide layer  2  to form silicon dioxide holes for front side silicon etching of wire bonding pad  8   c  is preferably carried out by photoresist lithography, dry etch of silicon dioxide and photoresist removal, as shown in  FIGS. 21   a  and  21   b.    
   The process preferably comprises:
         1. Coating the top surface SiO 2  of the cap wafer D with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region on the top surface of cap wafer D,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer D,   4. CF 4 /O 2  plasma etch of silicon dioxide until the Silicon starts yielding a hole  1   b  into the top silicon dioxide layer  2 ,   5. Stripping the remaining photoresist layer.       

   Then a backside metallization is preferably carried out by photoresist lithography and metal deposition and liftoff. Thereby Ti/Pt/Au  16  is attached on the backside of the wafer D, as shown in  FIGS. 22   a  and  22   b . The backside metallization can be applied by photoresist spray lithography, metal deposit and lift off or metal deposition, resist lithograph, and metal etching. 
   The process preferably comprises:
         1. Coating the bottom surface of cap wafer D with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for seal ring Ti/Pt/Au  16  to be attached, on the bottom surface of wafer cap wafer D,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer D,   4. Depositing Ti/PT/Au on the bottom surface of cap wafer D,   5. Depositing solder metal  12  on the bottom surface of cap wafer D,   6. Removing excess Ti/Pt/Au  16  and covering the photoresist by a metal lift-off process,   7. Stripping remaining photoresist yielding a Ti/Pt/Au  16 .       

   Then a backside metallization is preferably carried out to attach solder metal to the backside of the wafer D by photoresist lithography and metal deposition and liftoff. Thereby solder metal  12  is attached on the backside of the wafer D, as shown in  FIGS. 23   a  and  23   b . The backside metallization can be applied by photoresist spray lithography, metal deposit and lift off or metal deposition, resist lithograph, and metal etching. 
   The process preferably comprises:
         1. Coating the bottom surface of cap wafer D with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for solder metal  12  to be attached, on the bottom surface of wafer cap wafer D,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer D,   4. Depositing solder metal on Ti/Pt/Au  16  on the bottom surface of cap wafer D,   5. Depositing solder metal  12  on the bottom surface of cap wafer D,   6. Removing excess solder metal  12  and covering the photoresist by a metal lift-off process,   7. Stripping remaining photoresist yielding a solder metal  12 .       

   Then backside cavities  13   a    13   b  and  13   c  are preferably formed on the cap wafer D by spray thick photoresist on the backside, DRIE etch SiO 2 , DRIE cavities and remove photoresist, as shown in  FIGS. 24   a  and  24   b.    
   The process preferably comprises:
         1. Coating the bottom silicon dioxide layer  2  of the cap wafer D with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern to be created on bottom layer  2  of the cap wafer D,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the bottom silicon dioxide layer  2  of the cap wafer D,   4. Removing SiO 2  layer  2  of wafer D by CF 4 /O 2  plasma etch,   5. Etching silicon layer  1  unprotected by photoresist by gases utilizing the deep reactive ion etch (DRIE) on the bottom of the cap wafer D, and   6. Removing photoresist from the bottom silicon dioxide layer  2  of the cap wafer D yielding cavities  13   a ,  13   b  and  13   c.          

   The cap wafer D is bonded to the base wafer C. The cap wafer D is positioned on top of base wafer C. A solder bond is preferably carried out at low temperature at about 200° C. between the solder metal  12  of the cap wafer D and the seal ring metal  8   a  of the base wafer C, as shown in  FIGS. 25   a  and  25   b.    
   An opening  1   b  is preferably formed by wet etch (KOH) of silicon from the top of cap wafer D. The opening  1   b  combines with the cavity  13   a  to form a channel  17  for wire bonding as shown in  FIGS. 26   a  and  26   b.    
   The process preferably comprises: 
   Wet etching (KOH) of silicon from the top of the cap wafer D in the position of the hole  1   b  and generating a hole. The hole from the top of the cap wafer D forms with the cavity  13   a  from the bottom of the cap wafer D a channel  17 . 
   A ball bonding of wires  18  by vacuum oven bake is carried out as shown in  FIGS. 27   a  and  27   b . The process preferably comprises leading a wire  18  from the top of the cap wafer D through channel  17  and attaching the wire to the wire bonding pad Ti/Pt/Au  8   c  on the bottom wafer C. 
   Differential sensing for capacitive sensors can be implemented on in-plane devices where the motion to be detected and controlled is in the lateral direction. The accurate alignment coupled with new wafer-level vacuum packaging techniques and anisotropic DRIE provide the capabilities of fabricating the inventive structure. It is not known to apply the wafer-level vacuum packaging method of the present invention. The present invention provides a unique method of device assembly during vacuum packaging. 
   Although certain preferred embodiments of the present invention have been described above, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention. Those skilled in the art will appreciate the fact that both the order in which the described processes are carried out and the described process parameters may be varied if needed to suit local requirements.