Abstract:
A digital-to-analog converter (DAC) for use in high-speed wireless communications. The DAC of the invention comprises a plurality of current steering cells to bi-directionally provide a differential current output. When the DAC sets the differential current output to zero for example, each of the current steering cells establishes dummy branches between a pair of current sources and thereby prevents the current sources from floating. This in turn enables the DAC to operate with a higher update rate.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to integrated circuits, and more particularly to integrated circuits which convert a digital signal to an analog signal. 
     2. Description of the Related Art 
     As semiconductor manufacturing technology is rapidly progressing, it is possible to integrate analog and digital circuitry, which was previously implemented on a conventional board, on a single chip. Therefore, digital-to-analog converters (DACs), the interface between digital and analog systems, are regarded as key components in accomplishing integrated system design. 
     Digital-to-analog conversion refers to the process of converting discrete digital signals into a continuous-time range of analog signals. The trend in DACs is toward higher speeds and higher resolutions at reduced power levels. However, DACs tend to have relatively poor dynamic performance as they operate with high update rates. This is because the dynamic performance of a DAC is adversely affected by a “glitch”. Transient voltages may appear at the DAC output due to the periodic code updates applied to the DAC. More succinctly, input code transitions for DACs frequently incur a glitch in the analog output. Glitches obscure the generation of the analog output representing the digital input code. This problem becomes pronounced particularly when the DACs operate at high frequencies. It is desirable to provide a DAC having significant reduction in the glitch. Furthermore, DACs employed in modern communications applications preferably offer the ability to control the common-mode voltage appearing on differential outputs. There is a need to provide a differential voltage output DAC, addressing the above-described requirements. 
     SUMMARY OF THE INVENTION 
     The present invention is generally directed to a digital-to-analog converter (DAC). According to one aspect of the invention, a differential voltage output DAC is disclosed. The DAC of the invention comprises a plurality of current steering cells and two differential output operational amplifiers. The current steering cells are jointly coupled at a first and second pair of output nodes and controlled by a first and second coded word. Each current steering cell comprises a pair of current sources, two differential input stages, and two bypass units. The current sources are employed to supply a pair of input currents substantially equal in magnitude. The two differential input stages are connected at the first pair of output nodes and in series between the current sources. In response to a corresponding bit of the first coded word and a corresponding bit of the second coded word, the differential input stages steer the pair of input currents through the first pair of output nodes at which the pair of input currents are opposite in direction. Thus a pair of complementary currents is developed at the first pair of output nodes. The two bypass units are connected at the second pair of output nodes and in series between the pair of current sources. When the corresponding bit of the first coded word and the corresponding bit of the second coded word are both in a predetermined state, the bypass units establish a pair of dummy branches in parallel with the differential input stages, whereby the input currents are diverted to the second pair of output nodes. The first differential output operational amplifier is connected to the first pair of output nodes at its noninverting and inverting input terminals. Arranged in transimpedance output configuration, the first operational amplifier not only converts the total complementary currents into a differential voltage signal but also maintains the first pair of output nodes fixed at a predetermined voltage. The second differential output operational amplifier is connected to the second pair of output nodes at its noninverting and inverting input terminals. Similarly, the second operational amplifier is arranged in transimpedance output configuration to maintain the second pair of output nodes fixed at the predetermined voltage. 
     According to another aspect of the invention, a digital-to-analog converter comprises a plurality of current steering cells under control of a first and second coded word. The current steering cells are jointly coupled at a first and second pair of output nodes. Each current steering cell comprises a pair of current sources, two differential input stages, and two bypass units. The current sources are employed to supply a pair of input currents substantially equal in magnitude. The two differential input stages are connected at the first pair of output nodes and in series between the current sources. In response to a corresponding bit of the first coded word and a corresponding bit of the second coded word, the differential input stages steer the pair of input currents through the first pair of output nodes at which the pair of input currents are opposite in direction. Thus a pair of complementary currents is developed bi-directionally at the first pair of output nodes. The two bypass units are connected at the second pair of output nodes and in series between the pair of current sources. When the corresponding bit of the first coded word and the corresponding bit of the second coded word are both in a predetermined state, the bypass units establish a pair of dummy branches in parallel with the differential input stages, whereby the input currents are diverted to the second pair of output nodes. This prevents the pair of current sources from floating. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
       The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which: 
         FIG. 1  is a block diagram of a differential voltage output digital-to-analog converter according to an embodiment of the invention; 
         FIG. 2  is a simplified diagram of a current steering cell according to an embodiment of the invention; and 
         FIG. 3  is a schematic diagram of a current steering cell according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference throughout this specification to “one embodiment” or “an embodiment” indicates that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least one embodiment of the present invention. Thus, the appearance of the phrases “in one embodiment” or “an embodiment” in various places throughout this specification is not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in one or more embodiments. As to the accompanying drawings, it should be appreciated that not all components necessary for a complete implementation of a practical system are illustrated or described in detail. Rather, only those components necessary for a thorough understanding of the invention are illustrated and described. Furthermore, components which are either conventional or may be readily designed and fabricated in accordance with the teachings provided herein are not described in detail. 
       FIG. 1  shows a differential voltage output DAC  100  of the invention. The DAC  100  comprises n number of current steering cells  110   l - 110   n  under control of two n-bit coded words Q p [n:1] and Q n [n:1]. In one embodiment, a decoder (not shown) first converts a digital input code into Q p [n:1] and Q N [n:1] in the form of thermometer code, which, in turn, improves the dynamic performance and linearity of the DAC  100 . The thermometer decoder is beyond the scope of the invention and is not described in detail herein. As depicted, the current steering cells  110   1 - 110   n  are jointly coupled at a pair of output nodes  112   a-b  and another pair of output nodes  114   a-b . Each of the current steering cells  110   l-110   n  accepts a corresponding bit Q p [m] of coded word Q p [n:1] and a corresponding bit Q N [m] of coded word Q N [n:1], where m=1, 2, . . . , n. Depending on Q p [m] and Q N [m], the mth current steering cell  110   m  renders a pair of complementary currents I D+ [m] and I O− [m] to the output nodes  112   a-b , or renders another pair of complementary currents I D+ [m] and I D− [m] to the output nodes  114   a-b . All complementary currents I o+ [n:1] and I o [n:1] are summed at the output nodes  112   a-b , respectively, so as to form a pair of complementary output currents I OUT+  and I OUT−  that represent a digital input code. Likewise, complementary currents I D [n:1] and I D [n:1] are summed at the output nodes  114   a-b , respectively, thus forming a pair of complementary dummy currents I DUMMY+  and I DUMMY− . Double-headed arrows in accompanying drawings here denote bi-directional currents. A differential output operational amplifier  120  and two resistors  122   a-b  are set up as a current-to-voltage converter. In this way, the complementary output currents I OUT+  and I OUT−  are converted into a differential voltage signal, V OUT+  and V OUT− . Note that differential output operational amplifier  130  and resistors  132   a-b  are arranged in a similar manner and serve as a counterpart to eliminate glitches in the differential voltage outputs V OUT+  and V OUT−.    
       Fig. 2  is a block diagram illustrating one of the current steering cells according to an embodiment of the invention. The mth current steering cell  110   m  comprises a pair of differential input stages  210   a  and  210   b . The differential input stages  210   a-b  are connected at the pair of output nodes  112   a-b , and are connected in series between a pair of current sources  230   a-b  supplying a pair of input currents I p  and I N  of equal magnitude. In response to Q p [m] and Q N [m], the differential input stages  210   a  and  210   b  steer the pair of input currents I p  and I N  through the pair of output nodes  112   a-b  at which the currents I p  and I N  are opposite in direction. For example, the input current I p  is steered to the node  112   a  and the input current I N  is steered away from the node  112   b  when Q p [m] is logical “I” and Q N [m] is logical “0”. Conversely, the input current I p  is steered to the node  112   b  and the input current I N  is steered away from the node  112   a  when Q p [m] is logical “0” and Q N [m] is logical “I”. With the use of the differential input stage pair, the complementary currents I o [m] and I o− [m] are bi-directionally developed at the nodes  112   a-b , and are suitable for common-mode voltage control. 
     With continued reference to  FIG. 2 , the mth current steering cell  110   m  preferably includes a pair of bypass units  220   a-b  connected together at the pair of output nodes  114   a-b  and in series between the pair of current sources  230   a-b . In one embodiment, the bypass unit  220   a  comprises two switch devices  223 - 224  and two NOR gates  221 - 222 . Similarly, the bypass unit  220   b  comprises two switch devices  227 - 228  and two NOR gates  225 - 226 . However, this is merely an example and embodiments of the present invention are not limited in this respect. As depicted, all of the NOR gates receive Q p [m] and Q N [m] as input. The switch device  223  has a control terminal coupled to receive the output of the NOR gate  221 , an input terminal coupled to the current source  230   a , and an output terminal coupled to the output node  114   a . The switch device  224  has a control terminal coupled to receive the output of the NOR gate  222 , an input terminal coupled to the input terminal of the current source  230   a , and an output terminal coupled to the output node  114   b . The switch device  227  has a control terminal coupled to the output of the NOR gate  225 , an input terminal coupled to the output node  114   a , and an output terminal coupled to the current source  230   b . The switch device  228  has a control terminal coupled to the output of the NOR gate  226 , an input terminal coupled to the output node  114   b , and an output terminal coupled to the current source  230   b . When Q p [m] and Q N [m] are both in a predetermined state, the mth current steering cell  110 , is inhibited from delivering the complementary currents I o +[m] and I o [m]. For example, in the case where both Q p [m] and Q N [m] are logical “0”, all of the switch devices are turned on accordingly while the differential input stages  210   a-b  are deactivated. Hence, the bypass units  220   a-b  establish a pair of dummy branches  240   a-b  in parallel with the differential input stages  210   a-b , whereby the input currents I p  and I N  are diverted through the output nodes  114   a-b . This prevents the current sources  230   a-b  from floating, which, in turn, enables the DAC  100  to operate with a higher update rate. It should be understood by one skilled in the art that there are other ways of accomplishing the same result, and the method will vary based upon the type of device chosen to make up the bypass units. 
       FIG. 3  shows a schematic diagram of the mth current steering cell  110   m . The differential input stage  210   a  comprises transistors  311  and  312 ; the differential input stage  210   a  comprises transistors  313  and  314 . Each transistor described herein is either a p-channel or n-channel MOS transistor having a gate, a drain and a source. Since a MOS transistor is typically a symmetrical device, the true designation of “source” and “drain” is only possible once a voltage is impressed on the terminals. The designations of source and drain herein should be interpreted, therefore, in the broadest sense. The transistor  331  has a gate coupled to receive Q p [m], a drain coupled to the current source  230   a , and a source coupled to the output node  112   a . The transistor  312  has a gate coupled to receive Q N [m], a drain coupled to the current source  230   a , and a source coupled to the output node  112   a . The transistor  313  has a gate coupled to receive Q N [m], a drain coupled to the output node  112   a , and a source coupled to the current source  230   b . The transistor  314  has a gate coupled to receive Q p [m], a drain coupled to the output node  112   b , and a source coupled to the current source  230   b . According to an alternative embodiment of the invention, the bypass unit  220   a  comprises transistors  321 - 324 , and the bypass unit  220   b  comprises transistors  325 - 328 . The transistors  321 ,  323 ,  325  and  327  are connected in series between the pair of current sources  230   a-b . Likewise, the transistors  322 ,  324 ,  326  and  328  are connected in series between the pair of current sources  230   a-b . The gates of the transistors  321 ,  322 ,  325  and  326  are coupled to receive a complement of Q p [m], i.e. {overscore (Q p )}[m], while the transistors  323 ,  324 ,  327  and  328  have their gates coupled to receive a complement of Q N [m], i.e. {overscore (Q N )}[m]. 
     In operation, when Q p [m] is logical “1” and Q N [m] is logical “0”, the transistors  311  and  314  are made conductive, but the transistors  312  and  313  are made nonconductive. Thus the input current I N  is steered to the node  112   a  and the input current I N  is steered away from the node  112   b . According to Kirchhoff&#39;s current law, currents directed toward a node are usually taken as positive and those directed away are taken as negative. In the above case, the direction of the current I o [m] is positive while the direction of the current I o [m] is negative. When Q p [m] is logical “0” and Q N [m] is logical “1”, the transistors  311  and  314  are made nonconductive, but the transistors  312  and  313  become conductive. Thus the input current I p   is steered to the node  112   b  and the input current I N  is steered away from the node  112   a . As a result, the direction of the current I o+ [m] is negative while the direction of the current I o [m] is positive. Furthermore, in the case where both Q p [m] and Q N [m] are logical “0”, the transistors  321 - 328  become conductive while the transistors  311 - 314  are made nonconductive accordingly. The input currents I p  and I N  are shunted to the dummy branches  240   a-b  and no current reaches the output nodes  112   a-b . It should be appreciated by one skilled in the art that other transistor technologies are contemplated for implementing the transistors illustrated in  FIG. 3  based upon the principles of the invention. 
     Returning to  FIG. 1 , the operational amplifier  120  is arranged in transimpedance output configuration and connected to the pair of output nodes  112   a-b  at its noninverting and inverting input terminals. The two input terminals of the operational amplifier  120  may track each other in potential because of the operational amplifier  120  being in the form of “negative feedback”, that is, a “virtual short circuit” exists between its noninverting and inverting input terminals. A “virtual short circuit” means that whatever voltage at the noninverting input terminal will automatically appear at the inverting input terminal. Hence, not only does the operational amplifier  120  convert the complementary output currents I OUT+  and I OUT  into the differential voltage outputs V OUT+  and V OUT− , it maintains the output nodes  112   a-b  fixed at a common-mode voltage of V OUT+  and V OUT− . Another operational amplifier  130  is connected to the second pair of output nodes  114   a-b  at its noninverting and inverting input terminals. In similar fashion, the operational amplifier is arranged in transimpedance output configuration to maintain the output nodes  114   a-b  fixed at the common-mode voltage. Therefore, the DAC of the invention significantly reduces glitches in the differential voltage outputs V OUT+  and V OUT−.    
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.