Abstract:
A system and method for encrypting data provides for retrievial of an encryption key; identification of the address in memory of a first portion of the data to be encrypted; derivation of a first unique key from the encryption key and the address of the first portion of data; encryption of the first portion of data using the first unique key; identification of the address in memory of a second portion of data to be encrypted; derivation of a second unique key from the encryption key and the address of the second portion of data; and encryption of the second portion of data using the second unique key.

Description:
REFERENCE TO PRIOR APPLICATIONS 
       [0001]    This is a continuation of U.S. patent application Ser. No. 11/051,560 filed on Feb. 4, 2005, which claims priority from U.S. Provisional Application No. 60/541,972, filed Feb. 5, 2004, the entireties of which are incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    This disclosure relates to data processing systems and in particular to a data security system using on-chip secure key storage, which is particularly suitable for use in portable data processing devices. 
         [0004]    2. Description of Related Art 
         [0005]    The use of portable data processing systems has increased significantly in recent years. In addition to so called “laptop” and “tablet” computers, there is a growing popularity in handheld data processing devices, often called a “personal digital assistant” or “PDA.” All of these devices are capable of storing a significant amount of user data, including calendar, address book, tasks and numerous other types of data for business and personal use. Most handheld data processing devices have the ability to connect to a personal computer for data exchange, and many are equipped for wireless communications using, for example, conventional email messaging systems. Depending upon the user&#39;s needs much of this data can be highly sensitive in nature, especially for example in a government, military or commercial context. 
         [0006]    Portable data processing systems are typically password protected, which is sufficient to protect the information against attack by ordinary individuals. However, if the device were to fall into the hands of a technically sophisticated individual with malicious intent, there are ways to obtain the data stored in memory in such a device. For example, if the data is not encrypted, a technically skilled individual can remove the memory chip and extract the data directly from the chip. 
         [0007]    If the data is encrypted, it can only be compromised if the attacker has access to the encryption key. In a software-based encryption system, the encryption key is accessible to a technically sophisticated individual who has unlimited access to the device. Furthermore, software-based encryption systems are often cumbersome, and as such degrade processing speed and overall system performance. 
         [0008]    It is accordingly desirable to provide a hardware-based encryption system that encrypts and decrypts data in real time, without markedly reducing the operating speed of the device or markedly increasing energy consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    In drawings which illustrate by way of example only an example embodiment of the system, 
           [0010]      FIG. 1  is a block diagram of a system overview of a conventional hand-held data processing device. 
           [0011]      FIG. 2  is a system interface block diagram of a data processing device. 
           [0012]      FIG. 3 , comprising segments  3 A through  3 I, is a detailed block diagram of the memory controller interface in the data processing device of  FIG. 2 , wherein  FIG. 3I  illustrates the arrangement of  FIGS. 3A through 3H . 
           [0013]      FIG. 4  is a detailed block diagram of an AES encryption module in the data processing device of  FIG. 2 . 
           [0014]      FIG. 5  is a Configuration Registers Map for the encryption module of  FIG. 4 . 
           [0015]      FIG. 6  is an AES Plaintext Register Field table for the encryption module of  FIG. 4 . 
           [0016]      FIG. 7  is an AES Ciphertext Register Field table for the encryption module of  FIG. 4 . 
           [0017]      FIG. 8  is an AES Key Peripheral Register Field table for the encryption module of  FIG. 4 . 
           [0018]      FIG. 9  is an AES Manual Register table for the encryption module of  FIG. 4 . 
           [0019]      FIG. 10  is an AES Status Register table for the encryption module of  FIG. 4 . 
           [0020]      FIG. 11  is an AES Control Register table for the encryption module of  FIG. 4 . 
           [0021]      FIG. 12  is a State Diagram showing the encryption and decryption timing in the encryption module of  FIG. 4 . 
           [0022]      FIG. 13  is a block diagram of a Serial EEPROM Controller in the encryption module of  FIG. 4 . 
           [0023]      FIG. 14  is a state diagram for the Serial EEPROM Controller of  FIG. 13 . 
           [0024]      FIG. 15  is a Configuration Registers Map for the Serial EEPROM Controller of  FIG. 13 . 
           [0025]      FIGS. 16A and 16B  are first and second parts of a Control Register table for the Serial EEPROM Controller of  FIG. 13 . 
           [0026]      FIGS. 17A and 17B  are first and second parts of a Status Register table for the Serial EEPROM Controller of  FIG. 13 . 
           [0027]      FIG. 18  is a Version Control Register table for the Serial EEPROM Controller of  FIG. 13 . 
           [0028]      FIG. 19  is a Password Register Field table for the Serial EEPROM Controller of  FIG. 13 . 
           [0029]      FIG. 20  is a Key Seed Register Field table for the Serial EEPROM Controller of  FIG. 13 . 
           [0030]      FIG. 21  is a flowchart of an embodiment of an encryption method carried out by the system. 
           [0031]      FIG. 22  is a flowchart of an embodiment of an encryption method carried out by the system. 
           [0032]      FIG. 23  is a flowchart of an embodiment of a decryption method carried out by the system. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    The system will be described in detail below, by way of example only, in the context of a hand-held data processing device having wireless communications capabilities as illustrated in  FIGS. 1 to 3 . However, it will be appreciated that the principles apply to other data processing devices and the system is not intended to be limited thereby. 
         [0034]    The present system provides an on-chip encryption system in which the encryption key is hardware-based. The hardware-based encryption system encrypts and decrypts that data in real time, without markedly reducing the operating speed of the device or markedly increasing energy consumption. 
         [0035]    In the system, the data is encrypted using a hardware implementation of any suitable encryption algorithm, for example Advanced Encryption Standard (AES). In the preferred embodiment an initial encryption key is selected randomly and embedded at the time of manufacture of the chip, and preferably even the manufacturer does not retain any record of the randomly-selected initial encryption key. If the encryption key is to be changed after manufacture, all of the encrypted data must be read out of memory, decrypted using the key existing at the time of encryption, re-encrypted with the new key, and written back into memory. As the encryption key is changed, the components of the prior key(s) accumulate and form part of the new key together with an existing password and a seed value. 
         [0036]    To further increase security, in the preferred embodiment the encryption algorithm uses the address location of the data, so that the same data will be encrypted differently in successive encryption cycles because the location of the data in memory will typically differ from the previous location in which it had been stored. In the preferred embodiment, bits of the data sector address are exclusive-or&#39;ed with the encryption/decryption key(s) to generate unique key(s). Since the encryption key is typically longer than the data sector address, not all the bits in the unique key thus generated will be distinct from the bits in the original encryption key; regardless, in the preferred embodiment, the keys thus generated will still be unique and specific to the location of the data to be encrypted. In this manner, a unique key is used for identical pieces of data stored in different memory locations. The encryption algorithm generates the necessary unique keys on the fly. As shown in  FIG. 21 , the encryption algorithm identifies the address of the data to be encrypted at step  600 ; retrieves the encryption key  610 ; generates the unique key(s)  620 ; and then encrypts the blocks of data at step  630 . 
         [0037]    In the preferred embodiment the encryption system performs a password verification before any data from memory can be decrypted. Also, in the preferred embodiment the encryption key is not derived from the password, so even a weak password will not compromise the key, and before any data from memory can be decrypted a security controller performs a password verification. It is possible to change the value of the key at anytime by transitioning through a state machine that requires successful entry of the password, and once the key is changed, all of the existing data that is encrypted with the old key must be read out using the old key and re-written using the new key. 
         [0038]    Preferably the system will store up to four independent keys in non-volatile memory. The software may chose to use one or more of the extra key slots for redundant storage of a master key. The extra keys could also be used for different encryption purposes; for example, email could be encrypted with one key while a second key can be used to encrypt third party JAVA applications. 
         [0039]    The use of a hardware-based encryption engine gives the manufacturer of the chip complete control over the encryption key that is inaccessible to software, even in debugging modes. This significantly reduces opportunities for attack. It also accelerates the encryption process and uses less energy than software-based systems. 
         [0040]    These and other advantages of the system will become apparent from the description which follows. 
         [0041]    The hand-held mobile communication devices  10  include a housing, a keyboard  14  and an output device  16 . The output device shown is a display  16 , which is preferably a full graphic LCD. Other types of input devices and output devices may alternatively be utilized. A processor  18 , which is shown schematically in  FIG. 1 , is contained within the housing and is coupled between the keyboard  14  and the display  16 . The processor  18  controls the operation of the display  16 , as well as the overall operation of the mobile device  10 , in response to actuation of keys on the keyboard  14  by the user. 
         [0042]    The housing may be elongated vertically, or may take on other sizes and shapes (including clamshell housing structures). The keyboard may include a mode selection key, or other hardware or software for switching between text entry and telephony entry. 
         [0043]    In addition to the processor  18 , other parts of the mobile device  10  are shown schematically in  FIG. 1 . These include a communications subsystem  100 ; a short-range communications subsystem; the keyboard  14  and the display  16 , along with other input/output devices  106 ,  108 ,  110  and  112 ; as well as memory devices  116 ,  118  and various other device subsystems  120 . The mobile device  10  is preferably a two-way RF communication device having voice and data communication capabilities. In addition, the mobile device  10  preferably has the capability to communicate with other computer systems via the Internet. 
         [0044]    Operating system software executed by the processor  18  is preferably stored in a persistent store, such as a flash memory  116 , but may be stored in other types of memory devices, such as a read only memory (ROM) or similar storage element. In addition, system software, specific device applications, or parts thereof, may be temporarily loaded into a volatile store, such as a random access memory (RAM), in this embodiment SDRAM  118 . Communication signals received by the mobile device may also be stored to the SDRAM  118 . 
         [0045]    The processor  18 , in addition to its operating system functions, enables execution of software applications  130 A- 130 N on the device  10 . A predetermined set of applications that control basic device operations, such as data and voice communications  130 A and  130 B, may be installed on the device  10  during manufacture. In addition, a personal information manager (PIM) application may be installed during manufacture. The PIM is preferably capable of organizing and managing data items, such as e-mail, calendar events, voice mails, appointments, and task items. The PIM application is also preferably capable of sending and receiving data items via a wireless network  140 . Preferably, the PIM data items are seamlessly integrated, synchronized and updated via the wireless network  140  with the device user&#39;s corresponding data items stored or associated with a host computer system. 
         [0046]    Communication functions, including data and voice communications, are performed through the communication subsystem  100 , and possibly through the short-range communications subsystem. The communication subsystem  100  includes a receiver  150 , a transmitter  152 , and one or more antennas  154  and  156 . In addition, the communication subsystem  100  also includes a processing module, such as a digital signal processor (DSP)  158 , and local oscillators (LOs)  160 . The specific design and implementation of the communication subsystem  100  is dependent upon the communication network in which the mobile device  10  is intended to operate. For example, a mobile device  10  may include a communication subsystem  100  designed to operate with the Mobitex™, Data TAC™ or General Packet Radio Service (GPRS) mobile data communication networks and also designed to operate with any of a variety of voice communication networks, such as Advanced Mobile Phone Service (AMPS), Time Division Multiple Access (TDMA), Code Division Multiple Access (CDMA), Personal Communications Service (PCS), Global System for Mobile Communications (GSM), etc. Other types of data and voice networks, both separate and integrated, may also be utilized with the mobile device  10 . 
         [0047]    Network access requirements vary depending upon the type of communication system. For example, in the Mobitex and DataTAC networks, mobile devices are registered on the network using a unique personal identification number or PIN associated with each device. In GPRS networks, however, network access is associated with a subscriber or user of a device. A GPRS device therefore requires a subscriber identity module, commonly referred to as a SIM card, in order to operate on a GPRS network. 
         [0048]    When required network registration or activation procedures have been completed, the mobile device  10  may send and receive communication signals over the communication network  140 . Signals received from the communication network  140  by the antenna  154  are routed to the receiver  150 , which provides for signal amplification, frequency down conversion, filtering, channel selection, etc., and may also provide analog to digital conversion. Analog-to-digital conversion of the received signal allows the DSP  158  to perform more complex communication functions, such as demodulation and decoding. In a similar manner, signals to be transmitted to the network  140  are processed (e.g. modulated and encoded) by the DSP  158  and are then provided to the transmitter  152  for digital to analog conversion, frequency up conversion, filtering, amplification and transmission to the communication network  140  (or networks) via the antenna  156 . 
         [0049]    In addition to processing communication signals, the DSP  158  provides for control of the receiver  150  and the transmitter  152 . For example, gains applied to communication signals in the receiver  150  and transmitter  152  may be adaptively controlled through automatic gain control algorithms implemented in the DSP  158 . 
         [0050]    In a data communication mode, a received signal, such as a text message or web page download, is processed by the communication subsystem  100  and is input to the processor  18 . The received signal is then further processed by the processor  18  for an output to the display  16 , or alternatively to some other auxiliary I/O device  106 . A device user may also compose data items, such as e-mail messages, using the keyboard  14  and/or some other auxiliary I/O device  106 , such as a touchpad, a rocker switch, a thumb-wheel, or some other type of input device. The composed data items may then be transmitted over the communication network  140  via the communication subsystem  100 . 
         [0051]    In a voice communication mode, overall operation of the device is substantially similar to the data communication mode, except that received signals are output to a speaker  110 , and signals for transmission are generated by a microphone  112 . Alternative voice or audio I/O subsystems, such as a voice message recording subsystem, may also be implemented on the device  10 . In addition, the display  16  may also be utilized in voice communication mode, for example to display the identity of a calling party, the duration of a voice call, or other voice call related information. 
         [0052]    The short-range communications subsystem enables communication between the mobile device  10  and other proximate systems or devices, which need not necessarily be similar devices. For example, the short-range communications subsystem may include an infrared device and associated circuits and components, or a Bluetooth™ communication module to provide for communication with similarly-enabled systems and devices. 
         [0053]      FIG. 3 , comprising  FIGS. 3A through 3I , is a detailed block diagram of an embodiment of a memory controller interface  200  in the data processing device of  FIG. 2 . As would be understood by a person skilled in the art,  FIGS. 3A through 3H  represent portions of the memory controller interface  200  and may be arranged in the manner indicated in the grid  3000  of  FIG. 3I , which indicates the relative placement of each of  FIGS. 3A through 3H  with textual labels. A power module  190  and a phase locked loop filter  220  interface with the system control module  216 . A test controller  225  interfaces with a test control module  310  using a JTAG interface. The host processor  18  signals are managed by a microprocessor controller unit (MCU) interface control module  304 . An interrupt generator  306  provides notice to the host processor  18  that the memory controller interface  200  has data, status, and/or instructions to send. An IO pad control module  308  permits pull down, pull up, or other test operations on the IO signals. The memory controller interface  200  is implemented with a flash memory interface controller, in this embodiment a NAND flash interface controller (NIC)  214 , in communication with the flash memory; a memory interface controller for the ram, in this embodiment a SDRAM interface controller  300 ; and possibly other memory control interfaces, such as an auxiliary interface controller  328 . 
         [0054]    An interface  322  for a serial memory, such as a serial electrical programmable read only memory  334 , may be provided for managing encryption keys for the memory interface controller  200 . As noted above, preferably multiple keys may be stored in non-volatile memory, such as EEPROM. Also preferably, the encryption algorithm is implemented in hardware, and the keys cannot be read by software. In this embodiment, the serial memory interface  322  is a serial EEPROM controller. A state diagram and a configuration register map for the preferred embodiment of the serial EEPROM controller  322  is provided in  FIGS. 14 and 15 . A control register table and a status register table for the serial EEPROM controller  332  is shown in FIGS.  16 A/B and FIGS.  17 A/B, respectively. A detailed block diagram of an embodiment of the controller  322  is provided in  FIG. 13 . Referring to the block diagram, a key manager state machine  450  receives commands from the memory controller interface  200 . The controller further comprises a password compare block  460  for authenticating supplied passwords, and XOR blocks  452  and  454  for generating new keys; a first XOR block  452  receives a key seed value and XORs this value with a current key value, then XORs the result with the current password to produce a new key. The new key is written as shown in block  464 , and the controller  332  further comprises a key compare block  461  for verifying the written key. 
         [0055]    Other components within the memory controller interface  200  usually include a cache control manager  210 , a read/write buffer  212 , an encryption block  316 , an error correction coding module  324 , and an error correction coding read buffer  326 . The encryption block  316  is disposed upstream or downstream between the microprocessor controller unit  304  and the NIC  214 . A configuration register map for an embodiment of the encryption block  316  is shown in  FIG. 5 . 
         [0056]    The system relates to an encryption system for data processing devices such as the hand-held mobile communication device of  FIG. 1 . The encryption module, illustrated in  FIG. 4 , encrypts and decrypts in two different modes: peripheral mode and datapath mode. Peripheral mode allows a programmer to access the encryption module through a peripheral interface, while datapath mode incorporates the encryption module in the chain of functions that bridge SDRAM  118  with NAND  116 . The datapath mode happens automatically due to a request from an upstream or downstream block. A peripheral encryption module operation cannot be interrupted by a datapath operation and vice versa. This means that a peripheral operation can be held off by a datapath operation, so a status register is provided for polling. 
         [0057]    Preferably, while in datapath mode it is possible to bypass the encryption module  316  such that what comes out is what went in. There are two datapath keys supplied, along with bypass and select signals. The high level management of the keys is done in the serial memory interface block  322 . The encryption module  316  accommodates such modes as debug and datacopy. The encryption module  316  functions as a peripheral, which can be loaded with a key and plaintext, and then launched. AES plaintext, AES ciphertext, key peripheral, manual, status, and control register tables for use with the preferred embodiment are shown in  FIGS. 6 through 11 . Once the status declares the operation is done, the result can be read from the cipher register. A launch can be done automatically or manually. In the automatic case, the encryption module  316  launches once a specific data register is written, and this register can be selected in anticipation of a big or little endian processor. 
         [0058]    Under datapath operation there are two keys to choose from when not in bypass: the current key and a new key. Although encryption and decryption can be done with either key, in practical terms decryption will always be done with the current key. Encryption will normally be done with the current key but would be done with the new key during datacopy when the user wants to change over to a new key. 
         [0059]    Communication is through a request and acknowledge protocol. The receiver sends a request for data, along with the address of a sector. The server acknowledges the request and provides data. Both the Ack and Req can be pulled low to stall the flow. The receiver asserts a sector frame signal until it has received all the data. 
         [0060]    Preferably, requests to the encryption module  316  will always be a perfect multiple of the encryption module packet size of 128 bits. Preferably, it will be one NAND sector, which is 512 bytes. Requests from the encryption module  316  will always be in the encryption module packet size. 
         [0061]      FIG. 4  illustrates the two different interfaces to the block, as well as the implementation of the encryption module  316  encryption and decryption algorithms in hardware. The main areas are the peripheral  402  and datapath  404  interfaces, key expander  410 , and individual encryption and decryption blocks. The peripheral bus preferably uses a dedicated write clock, which saves power over a scheme that simply qualifies the high speed system clock. The dedicated read enable signal, and read data bus allow a simple OR of all the peripheral data return buses since they return zero when not selected. 
         [0062]    The encryption module clock enable is set when a datapath request is in force or a peripheral operation is pending and held until the encryption module state machine  440  has found its way back to idle. The other clock-gating domain lies with the datapath request-acknowledge handshake scheme. The acknowledge can be used to either gate the clock to a register, or qualify that clock. Whoever is sending data in response to an acknowledge has this choice. In the encryption module design the clock is qualified. 
         [0063]    The datapath keys are supplied and managed from the serial memory interface block  322 . The encryption module block  316  is flanked on two sides by the read/write buffer (RWB)  212  and the error correction coding module. It follows that there must be input and output data buses to each of these blocks, along with the handshaking signals. Dataflow can be stalled by either Ack or Req going low, so to know that a datapath operation is incomplete, a sector frame signal is used to bracket the entire transaction. The sector address consists of address bit  9  and upwards. A four bit address runs in the opposite direction and is used to select a buffer bank within the RWB  212 . The architecture consists of dedicated combinational logic for a round of encryption and a round of decryption. Their contents are similar in size and function, but they are inverses. A round companion module  412  accepts plaintext input and works with either Round  420  or InvRound  422  iteratively to produce a result, which is latched in the multiplexer block  430  and is accessible in either peripheral or datapath mode. 
         [0064]    Preferably, if both datapath and peripheral mode requests were to arrive simultaneously, the datapath request has priority. This is unlikely, and in general, whatever operation is ongoing is allowed to finish. A peripheral operation is short while a datapath operation consists of 32 encryption module implementations. If one type of operation is requested while another is in progress, the request is queued. The queuing realistically assumes that a second operation of the same type will not or cannot be requested. It is possible that a peripheral mode operation will take just 11 or 23 clocks to complete, or be held off for one full datapath time, so pending, ongoing and completed status are provided. A datapath launch becomes pending when the 8th halfword arrives, while a peripheral launch becomes pending when the 8th halfword location is written. 
         [0065]    As illustrated in  FIG. 12 , encryption of data to be written to NAND  116  takes 11 clocks while decryption takes 23 clocks. The discrepancy arises because the key is expanded to 11 unique keys and the order in which they are generated matches the requirement for them during encryption, but is in the opposite order to the sequence needed for decryption. This means they must be pre-expanded into a dual-port register file, taking 11 clocks. The register file&#39;s output is clocked so there is a clock cycle handoff time between the end of writing and the start of reading. Total decryption time is 11 clocks for expansion plus 1 clock handoff, and finally 11 clocks for actual decryption. Thus, referring to  FIG. 22 , preferably encryption by the encryption module  316  first retrieves the encryption key  650 ; identifies the 1st through nth sectors of data to be encrypted  660 , then generates the 1st through nth unique keys based on the location of the data sectors, then encrypts the n data sectors using the n unique keys. When the same data is to be decrypted, as shown in  FIG. 23 , once a decryption request is received 700, the address of each of the sectors to be decrypted is identified  710 , and the 1st though nth unique keys to be used for decryption are generated as above based on the location of the data sectors  720  before decrypting the n data sectors  730 . Most preferably, the step of generating the unique key  720  includes the step of expanding the unique keys to a dual-port register file, or otherwise reordering the unique keys to the order needed to accomplish decryption. 
         [0066]    PseudoCode for the Encryption Module Peripheral Mode is as follows: 
         [0000]    
       
         
               
             
           
               
                   
               
             
             
               
                 define false = 0x0; 
               
               
                 define Manual = 0b1; // Manual ENCRYPTION MODULE launch 
               
               
                 define Auto = 0b0; // Auto ENCRYPTION MODULE launch 
               
               
                 define le_not_be = 0b10; // If the processor splits a word write into 
               
               
                  two halfword writes, with le_not_be 
               
               
                 // set the halfword write to the upper address (vs. lower address) will 
               
               
                  be the one 
               
               
                 // that causes launch. Make your choice such that this is the last write. 
               
               
                 define d_not_e = 0b100; // decryption. 
               
               
                 define peri_enable = 0b1000; // Enable the clock while you use the 
               
               
                  ENCRYPTION MODULE or expect nothing. 
               
               
                 define key = 0x000102030405060708090a0b0c0d0e0f; 
               
               
                 define plain = 0x00112233445566778899aabbccddeeff; 
               
               
                 define cipher = 0x69c4e0d86a7b0430d8cdb78070b4c55a; 
               
               
                 // &lt;&gt;&lt;Manual Launch &gt;&lt;&gt; 
               
               
                 Configure_encryption module_control_reg(Manual | le_not_be | 
               
               
                  d_not_e | peri_enable, ENCRYPTION MODULEbase+0x18); 
               
               
                 Load_encryption module_plain_reg(cipher, ENCRYPTION 
               
               
                  MODULEbase+0x0); // ENCRYPTION MODULE input data 
               
               
                  (encryption or decryption) always goes in the 
               
               
                 // plain register 
               
               
                 Load_encryption module_key_reg(key, ENCRYPTION 
               
               
                  MODULEbase+0x10); 
               
               
                 Launch_manual(ENCRYPTION MODULEbase+0x1a); 
               
               
                 while (get_status(ENCRYPTION 
               
               
                  MODULEbase+0x19)&amp;0x4)==false); 
               
               
                 plain = retreive_cipher(ENCRYPTION MODULEbase+0x8); 
               
               
                 // &lt;&gt;&lt;Auto Launch &gt;&lt;&gt; 
               
               
                 Configure_encryption module_control_reg(Auto| le_not_be | d_not_e | 
               
               
                  peri_enable, ENCRYPTION MODULEbase+0x18); 
               
               
                 Load_encryption module_key_reg(key, ENCRYPTION 
               
               
                  MODULEbase+0x10); 
               
               
                 Load_encryption module_plain_reg(cipher, ENCRYPTION 
               
               
                  MODULEbase+0x0); // eighth halfword write causes encryption 
               
               
                  module to launch. 
               
               
                 while (get_status(ENCRYPTION 
               
               
                  MODULEbase+0x19)&amp;0x4)==false); 
               
               
                 plain = retreive_cipher(ENCRYPTION MODULEbase+0x8); 
               
               
                   
               
             
          
         
       
     
         [0067]    The datapath mode is more involved but has some simple governing rules. Communication is through a request and acknowledge protocol as shown in  FIG. 4 . The requesting block has a known amount of data to send, and the acknowledgement block  406  uses acknowledge to gate the sender&#39;s data and thus regulate the data flow. 
         [0068]    Preferably, eight clocks are needed to assemble an encryption module packet before the encryption module  316  can proceed. It also takes eight clocks to send off the result. When a request to the encryption module  316  is received, the data is always read in without stalling, and the encryption module algorithm proceeds as far as it can before it would overwrite an old result, which has not yet been fully sent off. In short, any stalling is governed by the sending rather then the receiving. This simplifies the logic and allows the process to proceed as far as it possibly can before it needs to stall. If NAND Twc=70 ns minimum (14 Mhz) and the encryption module is run at 52 Mhz, the ratio is 1:4 if the word width is 16 bits. Thus, in this embodiment, the encryption module  316  should not present a bottleneck. 
         [0069]    The user is able to access the serial EEPROM controller module  322  through the configuration bus interface, as shown in  FIG. 2 . The configuration bus is controllable from the MCU interface control  304 , and from the JTAG interface. When the JTAG interface is used, the ENTER_DEBUG command is permitted, and changing of DIS_ENCRYPT in SEC_CTRL is prohibited. 
         [0070]    Referring to  FIGS. 13 and 14 , in the preferred embodiment the serial EEPROM controller module  322  comprises a version control register, a password register, and a key seed register such as those set out in  FIGS. 18 ,  19 , and  20  for use in command execution. The following commands can be executed in the operation of the serial EEPROM controller module  322  described above, using the registers set out in  FIG. 15 .
   The GET_KEY command  502  is issued when CMD[2:0]=“000” is written to the SEC-CTRL register. This command retrieves the current key  458  and password  456  set from the EEPROM  334 . The key and password set is determined by KEY_SELECT[1:0] found in the SEC-CTRL register.   The COMPARE_KEYS command  504  is issued when CMD[2:0]=“001” is written to the SEC-CTRL register. This command provides the results of two comparisons. It compares the current password  456  with the test password  464  using the password compare block  460 , and it compares the current key  458  with the previously written key  464  using the key compare block  461 . The results are provided in the SEC-STATUS register.   The ADD_KEY command  506  is issued when CMD[2:0]=“010” is written to the SEC-CTRL register. This command forms the new key  470  from the current password  456 , current key  458 , and the software supplied key seed  462 . This new key  470  can be used in the datacopy operations. A new password is also supplied by software and will come into effect when the UPDATE command is executed. The current key  458  and current password  456  are retrieved with the GET_KEY command.   The REMOVE_KEY command  510  is issued when CMD[2:0]=“011” is written to the SEC-CTRL register. This command transitions to the Remove key state where the datacopy can be completed.   The CHANGE_KEY command  512  is issued when CMD[2:0]=“100” is written to the SEC-CTRL register. This command forms the new key  470  from the current password  456 , current key  458 , and a software supplied key seed  462 . This new key can be used in the datacopy operations. A new password is also supplied by software and will come into effect when the UPDATE command is executed. The current key  458  and current password  456  are retrieved with the GET_KEY command. Reading the SEC_STATUS register provides the current key state status.   The UPDATE_KEY command  508  is issued when CMD[2:0]=“101” is written to the SEC-CTRL register. The generated key  470  and new password are written into EEPROM  334  at the KEY_SELECT location.   The ENTER_DEBUG command  514  is issued when CMD[2:0]=“110” is written to the SEC-CTRL register. This command must be executes from the JTAG interface. It transitions control to either the Insecure Debug state (through Clear SDRAM) or to the Secure Debug state. The ENTER_DEBUG command is issued when CMD[2:0]=“111” is written to the SEC-CTRL register. This command transitions control to the Insecure state.   
 
         [0078]    The following states are possible in the operation of the serial EEPROM controller  322  described above, with reference to the state diagram of  FIG. 14 :
   Insecure  519 : The device  10  is powered up in the Insecure state. In this state, a password is not required, and a key is not used to read and write data to NAND flash  116 .   Clear SDRAM  515 : This state asserts the CLEAR_SDRAM signal for the SDRAM interface controller  300 . Transfer to the Insecure Debug state  513  will be completed upon receiving the SDRAM_CLEAR signal from the SDRAM interface controller  300 . Clearing the SDRAM  118  prohibits the use of JTAG to read the contents of the SDRAM  118  in Debug mode.   Insecure Debug  513 : This state asserts the DEBUG_EN signal, allowing the memory interface controller  200 &#39;s debug functions with the encryption module  316  in bypass mode. Executing the EXIT_DEBUG command will transition control to the Insecure state  500 .   Get Key  509 : This state is entered with the Get_Key command  502 . The password and key set is read from the EEPROM  334 . If successful, the current key and current password are updated and control is transferred to the Key Loaded state  508 . Control will be transferred back to the Insecure state  519  if the EEPROM  334  is busy writing, or if an error is encountered.   Key Loaded  511 : This state is entered upon the successful read of the key and password from the EEPROM  334 . A key comparison can be made by loading the compare keys commands, or a new key can be created by loading the add key command.   Compare  521 : In this state, the current password is compared with the test password, and the current key is compared with the key written. Results are available upon completion. If the passwords match, control will be transferred to the Secure state  512 . If the passwords did not match, control will be transferred back to the Insecure state  500 .   Add Key  525 : In this state, software can read in unencrypted data and write back using the newly generated encryption key. Since reading is done in bypass mode, all previously stored encrypted data is lost. Once the data copy operation is complete, the UPDATE_KEY command  508  is used to write the new key and password to the EEPROM  334 . The Insecure state  519  is entered on completion.   Remove Key  511 : The REMOVE_KEY command allows software to read encrypted data with the current key, and to write data back with no key. Once the data transfer is complete, the UPDATE_KEY command  508  is executed to write the new key into EEPROM  334 .   Change Key  527 : The CHANGE_KEY command allows software to read encrypted data with the current key, and to write data back with the new key. Once the data transfer is complete, the UPDATE_KEY command  508  is executed to write the new key into EEPROM  334 .   Update Key  529 : This state is entered with the Update command  508 . The new password and newly form key are written to the EEPROM  334 . On completion, control is transferred to the Insecure state  519 .   Secure  523 : In the Secure state, encrypted data is written to and read from NAND flash using the current key. In this mode, the COMPARE command must be executed. If the passwords match, the Validate state will  531  be entered. If the passwords do not match, the Insecure state  519  is entered.   Compare2: This state is entered from the Secure state  523 . In this state, the current password is compared with the test password, and the current key is compared with the key written. Results are available upon completion. If the passwords match, control will be transferred to the Validate state  531 . If the passwords did not match, control will be transferred back to the Insecure state  519 .   Validate  531 : This state ensures that a valid password is present prior to allowing the change of a key, the removal of a key, or the debugging with keys.   Secure Debug  517 : This state asserts the DEBUG_EN signal, allowing the memory controller interface&#39;s debug functions with the encryption module  316  operational. Executing the EXIT_DEBUG command will transition control to the Insecure state  519 .   
 
         [0093]    Preferably the software supplied key seed  462 , which is used in generating a new key  470 , is created using a randomizing function, a random seed, or using data gathered from random sources, such as key hits. In the preferred embodiment, the new key  470  thus generated from the key seed  462 , current password  456 , and current key  458 , is a bitwise XOR of the current key and key seed (via XOR  452 ) and of the current password (via XOR  454 ). Thus, the initially unknown encryption key embedded during manufacturing, as well as the initial password used to secure the device, is used to derive all future encryption keys, without any need for the user or manufacturer to know the value of the initial encryption key. If passwords for the communication device are set by the user rather than by software, it does not matter if a user chooses a weak password. The use of the key seed  462  and the current key  458  ensure that the newly generated encryption key is sufficiently strong, and not determinable from a user-chosen password. Further, new keys can be formulated by modifying the key seed. Bits can be inverted by seeding a bit position with a logic 1. At no time is the actual key known by software; only the comparison results from the compare block  461 . Once the encryption key has been changed using the CHANGE_KEY command  512 , the data encrypted using the previous (“current”) 
         [0094]    EEPROM testing is accommodated with the use of the current key, the key written, and the key compare block. A key can be generated and written into the EEPROM  334 . This key can be read out and compared with the key written using the COMPARE command and monitoring using the KEY_STATUS[1:0] found in the SEC-STATUS register. 
         [0095]    Various embodiments of the system having been thus described in detail by way of example, it will be apparent to those skilled in the art that variations and modifications may be made without departing from the invention.