Abstract:
A semiconductor device includes: an insulating film provided on a back surface of a semiconductor substrate; a plurality of isolation regions provided to reach the insulating film from a main surface of the semiconductor substrate; at least a first semiconductor layer and a second semiconductor layer which are electrically insulated from each other by the isolation regions in the semiconductor substrate; a first voltage applied terminal electrically connected to a front surface of the first semiconductor layer; a second voltage applied terminal electrically connected to a front surface of the second semiconductor layer; a selector circuit receiving voltages from the first voltage applied terminal and the second voltage applied terminal, and supplying an output in accordance with a combination of the voltages; and a conductive layer provided so as to contact with the insulating film provided to the back side of the semiconductor substrate.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-1098, filed on Jan. 8, 2008, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device and method for manufacturing the same. 
         [0004]    2. Related Art 
         [0005]    After a semiconductor wafer is produced or a semiconductor chip is fabricated, a test is conducted and, for example, a failure element is replaced with a redundant circuit and voltage values are switched to obtain a power supply voltage with a desired accuracy level, which is called trimming. 
         [0006]    Related-art technologies employ zener zaps, which are devices required for trimming purposes. A power supply voltage is applied in advance to two input terminals of a selector circuit, and a zener zap is coupled in series between a ground terminal and each of the input terminals. One of the zener zaps with this state is selectively applied with large current, whereby heat is generated to break down the device to be short-circuited to the ground terminal. A combination of voltages input to the selector circuit is thus determined. 
         [0007]    Such zener zaps, however, occupy some area on the wafer exclusively for trimming purposes, which inevitably increases the circuit area. This configuration also requires isolation of the zener zaps, into which large current is flown, to avoid any impact on other circuit elements. As a consequence, area efficiency remains low. 
         [0008]    Another concern is residual resistance remaining after the breakdown of the zener zap. Further, the short-circuited state after the breakdown cannot be maintained stably, possibly resulting in an increase in resistance values or complete fracture to cause an open state. 
         [0009]    The document mentioned below discloses a trimming technology without the use of zener zaps. 
         [0010]    Japanese Patent Application Publication No. 8-055961 describes a technology used for a structure having a resistor provided on a surface of a semiconductor substrate, a thick insulating film provided above the resistor, a contact hole coupled to the resistor through the insulating film, a thin insulating film provided on the surface of the resistor in the contact hole, and metal wiring coupled to the contact hole. By the technology, the thin insulating film is applied with a voltage and broken down, whereby the resistor and the metal wiring are short-circuited to adjust resistance values. 
         [0011]    The technology described in Japanese Patent Application Publication No. 8-055961, however, requires an additional step to provide an insulating film having a thickness small enough to be broken down by a lower voltage compared with the voltage required for breaking down the zener zap. This increases manufacturing steps and cost. 
         [0012]    Furthermore, a diffusion layer serving as a resistor is also applied with the voltage for breaking down the insulating film, which may adversely affect resistance values of the diffusion layer after the breakdown of the insulating film. 
       SUMMARY OF THE INVENTION 
       [0013]    A semiconductor device according to an embodiment of the present invention comprises: an insulating film provided on a back surface of a semiconductor substrate; a plurality of isolation regions provided to reach the insulating film from a main surface of the semiconductor substrate; at least a first semiconductor layer and a second semiconductor layer which are electrically insulated from each other by the isolation regions in the semiconductor substrate; a first voltage applied terminal electrically connected to a front surface of the first semiconductor layer; a second voltage applied terminal electrically connected to a front surface of the second semiconductor layer; a selector circuit receiving voltages from the first voltage applied terminal and the second voltage applied terminal, and supplying an output in accordance with a combination of the voltages; and a conductive layer provided so as to contact with the insulating film provided to the back side of the semiconductor substrate. 
         [0014]    A semiconductor device according to an embodiment of the present invention comprises: an insulating film provided on a back surface of a semiconductor substrate; a plurality of isolation regions provided to reach the insulating film from a main surface of the semiconductor substrate; at least a first semiconductor layer and a second semiconductor layer which are electrically insulated from each other by the isolation regions in the semiconductor substrate; a first voltage applied terminal electrically connected to a front surface of the first semiconductor layer; a second voltage applied terminal electrically connected to a front surface of the second semiconductor layer; a first switch connected in series between the first voltage applied terminal and a first node which is applicable with a predetermined voltage; a second switch connected in series between the second voltage applied terminal and a second node which is applicable with the predetermined voltage; a selector circuit receiving voltages from the first voltage applied terminal and the second voltage applied terminal, and supplying an output in accordance with a combination of the voltages; a power supply circuit connected to the first node and the second node and applying a predetermined voltage, respectively; and a conductive layer provided so as to contact with the insulating film provided to the back side of the semiconductor substrate. 
         [0015]    A method for manufacturing a semiconductor device according to an embodiment of the present invention comprises:, the method comprises: 
         [0016]    forming a plurality of deep trench isolations on a main surface of a semiconductor substrate by embedding an insulating material in deep trenches; 
         [0017]    providing, on the semiconductor substrate, a first voltage applied terminal electrically connected to a front surface of a first semiconductor layer provided between two of the deep trench isolations which are adjacent to each other, a second voltage applied terminal electrically connected to a front surface of a second semiconductor layer provided between other two of the deep trench isolations which are adjacent to each other, and a selector circuit which receives voltages from the first voltage applied terminal and the second voltage applied terminal and supplies an output in accordance with a combination of the voltages; 
         [0018]    polishing a back surface of the semiconductor substrate until the plurality of deep trench isolations are exposed on the back surface of the semiconductor substrate; 
         [0019]    providing an insulating film on the back surface of the semiconductor substrate; and 
         [0020]    providing a conductive layer under the insulating film. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  is a sectional view of the semiconductor device before trimming according to an embodiment of the present invention; 
           [0022]      FIG. 2  is a sectional view of the semiconductor device that is subject to trimming; 
           [0023]      FIG. 3  is a sectional view of the semiconductor device after trimming; 
           [0024]      FIGS. 4 to 6  are sectional views showing steps of process, in which isolation regions having DTI structure are formed; and 
           [0025]      FIG. 7  is a sectional view of the semiconductor device before trimming according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    Embodiments according to the present invention will now be explained with reference to the accompanying drawings. 
         [0027]    An insulating film  2 , such as a silicon oxide film or a silicon nitride film, is provided on the back side of a semiconductor substrate  1 . To reach the back side of the semiconductor substrate  1  from the front side thereof, isolation regions  31 ,  32 ,  33  formed by embedding an insulating film in deep trench isolations (DTI) serving as isolation trenches are provided, thereby electrically isolating semiconductor regions  41 ,  42 . Portions in the insulating film  2  each corresponding to the semiconductor region  41 ,  42  are selectively broken down and short-circuited to define an area for storing data for trimming in a non-volatile manner, which will be described in greater detail later. 
         [0028]    The front side of the semiconductor substrate  1  is provided with circuit elements as described later, and a wiring layer  4  is further provided on the front sides thereof. The wiring layer  4  is provided with contacts  21 ,  22  each embedded with a conductive material in through-holes formed to expose the front sides of the semiconductor layers  41 ,  42 . The contact  21  is coupled to a voltage applied terminal  11 , while the contact  22  is coupled to a voltage applied terminal  12 . In addition, a voltage applied terminal  13  is provided on the wiring layer  4 , and coupled with a power supply  5  that supplies a predetermined voltage. 
         [0029]    A switch SW 1  and a resistor R 1  connected in series are provided as circuit elements between the contact  21  and the voltage applied terminal  13  of the front surface of the semiconductor substrate  1 , while a switch SW 2  and a resistor R 2  connected in series are provided between the contact  22  and the voltage applied terminal  13 . The switches SW 1 , SW 2  and the resistors R 1 , R 2  may configured by metal-oxide semiconductor field-effect transistors (MOSFET), for example. The switches SW 1 , SW 2  receive signals for switching from a control terminal (not shown) to control ON/OFF operation. 
         [0030]    A node N 1  connecting the resistor R 1  and the switch SW 1  is connected to one input terminal of a selector circuit SR 1  provided on the front surface of the semiconductor substrate  1 . A node N 2  connecting the resistor R 2  and the switch SW 2  is connected to the other input terminal of the selector circuit SR 1 . 
         [0031]    Prior to trimming, the switches SW 1 , SW 2  are in the ON state as shown in  FIG. 1 . The semiconductor substrate  1  is mounted with the insulating film  2  therebetween on a conductive layer  3 , such as a frame, that is grounded and conductive. 
         [0032]      FIG. 2  is a sectional view of the semiconductor device that is subject to trimming. First, the switches SW 1 , SW 2  are turned OFF. Then, either the voltage applied terminal  11  or  12  (the voltage applied terminal  11  in this example) is selectively connected to a variable voltage power supply  6  via a switch SW 11 . Note that the variable voltage power supply  6  may be a power supply that outputs a fixed voltage. 
         [0033]    Subsequently, with the switch SW 11  being turned on, a power supply voltage is applied to the insulating film  2  through the voltage applied terminal  11 , the contact  21 , and the semiconductor layer  41 , thereby causing insulation breakdown. As a consequence, a portion in between the contact  21  and the conductive layer  3  is grounded via a conduction path  52 , resulting in a short circuit. 
         [0034]      FIG. 3  is a sectional view of the semiconductor device after trimming. The switches SW 1 , SW 2  are turned ON after trimming. 
         [0035]    The voltage applied terminal  11  and the contact  21  are grounded and short-circuited to the conductive layer  3  via the conduction path  52  between the semiconductor layer  41  and the insulating film  2 . Consequently, a ground voltage is input to one input terminal of the selector circuit SR 1  connected to the voltage applied terminal  11  via the contact  21 , the switch SW 1 , and the node N 1 . 
         [0036]    On the other hand, the other input terminal of the selector circuit SR 1  connected to the voltage applied terminal  12  via the contact  22  and the switch SW 2  receives a power supply voltage from the power supply  5 . A combination of voltage values input to the selector circuit SR 1  is determined accordingly. The selector circuit SR 1  outputs a selection signal in accordance with the combination, and the signal is supplied to a power supply circuit or a redundant circuit (not shown) to perform predetermined selection. 
         [0037]    The above-described process of trimming may be performed during a semiconductor wafer manufacturing process or after assembling a semiconductor chip. In either case, each chip region requires the voltage applied terminals  11 ,  12 ,  13 , the switches SW 1 , SW 2 , and the selector circuit SRi. 
         [0038]    The present embodiment requires no exclusive devices, namely, zener zaps occupying some area, on the wafer for trimming purposes, thereby preventing an increase in the circuit area. 
         [0039]    While breaking down a zener zap requires large current, the present embodiment needs a voltage to be applied that is high enough to break down the insulating film  2 , which is significantly smaller than the voltage required for breaking down a zener zap. This configuration leads to no restrictions on the layout that may affect other circuit elements, and thus enhances area efficiency. It should be noted that the thickness of the insulating film  2  is determined depending on pressure resistance levels required between adjacent semiconductor layers. For example, the insulating film  2  with a thickness of from 200 to 1000 angstroms can be broken down and short-circuited with a voltage of about 10 to 50 volts applied. 
         [0040]    After breaking down the insulating film  2 , the insulating film  2  is stably in the short-circuited state, so that it can input a stable value to the selector circuit. 
         [0041]    The following paragraphs describe a technology for separating a semiconductor substrate into a plurality of semiconductor layers that are insulated electrically from each other by means of the DTI structure. 
         [0042]    To lower a capacity between the drain of a transistor and a semiconductor substrate to achieve high-speed operation, silicon-on-insulator (SOI) substrates are widely used. Manufacturing an SOI substrate, however, requires complicated and costly processes including preparing two silicon substrates, bonding a silicon oxide film between the two substrates, and providing a silicon oxide film in the silicon substrates by ion implantation. 
         [0043]    To address this problem, DTI is used to separate a semiconductor substrate into a plurality of semiconductor layers that are insulated electrically from each other as described below. 
         [0044]    Referring to  FIG. 4 , the semiconductor substrate  1  having a predetermined thickness is prepared and the main surface thereof is provided with a deep trench. Then, an insulating film, such as a silicon oxide film, is embedded in the deep trench to provide the isolation regions  31 ,  32 ,  33  of the DTI structure. The isolation regions  31 ,  32 ,  33  define the semiconductor layers  41 ,  42 . The front side of the semiconductor layers  41 ,  42  are provided with the switches SW 1 , SW 2 , the resistors R 1 , R 2 , the selector circuit (not shown) and other circuit elements, while the wiring layer  4  is further provided on the front sides thereof. 
         [0045]    Referring next to  FIG. 5 , the back side  1 A of the semiconductor substrate  1  is subject to polishing, e.g., chemical mechanical polishing (CMP), or etching to reduce the thickness until the bottom surfaces  31 A,  32 A,  33 A of the isolation regions  31 ,  32 ,  33  are exposed. 
         [0046]    Referring now to  FIG. 6 , an insulating film  51  is provided on the back side  1 A of the semiconductor substrate  1 . Accordingly, the semiconductor layers  41 ,  42  are separated and insulated electrically from each other by means of the isolation regions  31 ,  32 ,  33  and the insulating film  51 . Then, the conductive layer  3  is provided under the insulating film  51 . 
         [0047]    The insulating film  51  is provided to separate the semiconductor substrate into a plurality of semiconductor layers by means of the DTI structure, and is not provided for trimming purposes. Therefore, no additional step is required exclusively for trimming, which does not increase the number of steps in the manufacturing process. 
         [0048]    The embodiments are described by way of example, and various modifications can be made within the spirit and scope of the present invention. For example, two semiconductor layers  41 ,  42  are separated and insulated electrically from each other and the insulating film  2  corresponding to each semiconductor layer  41 ,  42  is selectively broken down to input two-bit voltage values to the selector circuit SR 1  for trimming in the above-described embodiments. Alternatively, trimming can be performed by separating and electrically insulating three or more semiconductor layers, selectively breaking down an insulating film corresponding to each of the layers, and inputting a voltage value of three bits or more. 
         [0049]    While the voltage applied terminal  13  is provided on the wiring layer  4  and connected to the power supply  5  to supply a predetermined voltage in the above-described embodiments, the voltage applied terminal  13  is not necessarily required. For example, as a semiconductor device according to an alternative embodiment of the present invention illustrated in  FIG. 7  shows, a built-in power supply circuit PSI may supply a predetermined voltage to the nodes N 1 , N 2  through the resistors R 1 , R 2 .