Abstract:
In a memory system, a plurality of memories having different bit widths from each other and each including at least one block and a plurality of buses are provided. At least one selector is connected between the block and at least two of the buses and selectively connects the block to one of the at least two buses.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a memory system included in a digital signal processor or the like. 
     2. Description of the Related Art 
     Generally, in a digital signal processor, separate memory spaces are provided for programs and data. Sometimes, however, program memory space runs short, and excess data memory space exists, and it would be desirable to be able to reallocate memory from one to the other. Typically, however, the memory space is completely divided into a program space and a data space. That is, a program memory is connected to only a data bus. Thus, since the program memory and the data memory are completely independent of each other, there is no way to use part of the program memory data memory and vice versa. 
     In order to permit reallocation between the program memory and the data memory, in one digital signal processor design, the system includes a program bus, a data bus, a large scale memory space and a memory priority sequence controller, so that the user can freely allocate the memory space between the memory spaces for the program bus and the data bus as required. A system of this kind is shown in Japan patent application 63-303452, published Dec. 12, 1988. 
     In the above-described prior art memory system, however, the program bus has the same bit width as the data bus. However, in some digital signal processors such as the PD7701X family manufactured by NEC Corporation, a program memory having a bit width of 32 bits and two data memories each having a bit width of 16 bits are provided. That is, a program memory space and two data memory spaces are provided. The two data memory spaces are helpful in carrying out pipeline processing Because the program bus and the data bus in these digital signal processors have different bit widths, the memory management scheme shown in Japan published application 63-303452 can not be used. If additional data or program memory is needed, the onboard memory must be increased, or external memory must be provided, which increases the manufacturing cost. In addition, the memory priority sequence controller in the published application dissipates a large amount of power. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to improve the adaptability of memory space in a memory system including a program memory and at least two data memories having a different bit width from the program memory. 
     According to the present invention, in a memory system, a plurality of memories having different bit widths from each other and each including at least one memory block and a plurality of buses are provided. At least one selector is connected between the block and at least two of the buses and selectively connects the block to one of the at least the buses. 
     The selector freely allocates the memory spaces of the memories, thus substantially increasing the memory capacity. In addition, the selector dissipates hardly any power. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block circuit diagram illustrating a first embodiment of the memory system according to the present invention; 
     FIG. 2 is a block circuit diagram of the fixed areas of FIG. 1; 
     FIG. 3A is a detailed block circuit diagram of the selector of FIG. 1; 
     FIGS. 3B and 3C are block circuit diagrams for explaining the operation of the selector of FIG. 3A; 
     FIG. 4 is a diagram showing memory spaces of the memories of FIG. 1; 
     FIG. 5 is a block circuit diagram illustrating a second embodiment of the memory system according to the present invention; 
     FIG. 6A is a detailed block circuit diagram of the selector of FIG. 5; 
     FIGS. 6B and 6C are block circuit diagrams for explaining the operation of the selector of FIG. 6A; 
     FIG. 7 is a diagram showing memory spaces of the memories of FIG. 5; and 
     FIG. 8 is a block circuit diagram illustrating a third embodiment of the memory system according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, which illustrates a first embodiment of the memory system according to the present invention, reference numeral  1  designates a 32-bit program memory formed by blocks B 10 , B 11 , . . . , B 1m ,  2  designates a 16-bit X-data memory formed by a block B 20 , and  3  designates a 16-bit Y-data memory formed by a block B 30 . Also, reference numeral  4  designates a 32-bit program bus,  5  designates a 16-bit X-data bus, and  6  designates a 16-bit Y-data bus. 
     In the program memory  1 , the block B 10  is connected to the data bus  4 , while the blocks B 11 , B 12 , . . . , B 1     m    are connected by respective multi-state selectors SEL 11 , SEL 12 , . . . , SEL 1     m    to the program bus  4  or the data buses  5  and  6 . For example, if a control signal S 1  is “1”, the selector SEL 11  is operated to a state to connect the block B 11  to the program memory  4 , while, if the control signal S 1  is “1”, the selector SEL 11  connects the blocks B 11  to the data buses  5  and  6 . 
     In the X-data memory  2 , the block B 20  is connected to the X-data bus  5 , and in the Y-data memory  3 , the block B 30  is connected to the Y-data bus  6 . 
     Further, reference numeral  7  designates a program counter for generating a value PC,  8  designates an X-data pointer for generating a value XDP, and  9  designates a Y-data pointer for generating a value YDP. 
     The program memory  1 , the X-data memory  2  and the Y-data memory  3  are accessed by using the values PC, XDP and YDP. 
     The blocks B 10 , B 20  and B 30  are fixed, i.e., dedicated memory areas, with block B 10  permanently assigned for program use, and blocks B 20  and B 30  permanently assigned for data use. Therefore, as illustrated in FIG. 2, the block B 10  is accessed by an address decoder  11  that receives the value PC, the block B 20  is accessed by an address decoder  12  that receives the value XDP, and the block B 30  is accessed by an address decoder  13  that receives the value YDP. 
     The blocks B 11 , B 12 , . . . , B 1     m    of the program memory  1  are variable non-dedicated memory areas, and may be reallocated for use as data memory if needed. One of the blocks such as B 1     i    is explained next in detail with reference to FIGS. 3A,  3 B and  3 C. 
     As illustrated in FIG. 3A, the selector SEL 1     i    is formed by selectors  31  and  32 . The selector  31  is connected via an address decoder  33  to the block B 1     i   . The state of selector SEL 1i  determines if memory block B 1i  serves as a 32 bit program memory block or as two 16 bit data memory blocks. 
     As illustrated in FIG. 3B, when the control signal S i  is “0”, the selector  31  selects the value PC and transmits it to the address decoder  33 . Simultaneously, the selector  32  connects the 32-bit input/outputs of the block B 1     i    to the program bus  4 . Thus, the block B 1     i    serves as a program memory block. 
     On the other hand, as illustrated in FIG. 3C, when the control signal S i  is “1”, the selector  31  selects the value XDP (or YDP) and transmits it to the address decoder  33 . Simultaneously, the selector  32  connects the 32-bit input/outputs of the block B 1     i    to the X-data bus  5  and the Y-data bus  6 . Thus, the block B 1     i    serves as two data memory blocks. 
     The control signal S i  (i−1, 2, . . . , m) can be generated by a switch circuit formed by two MOS transistors one of which is normally turned ON by using an impurity diffusion process in advance. Therefore, as illustrated in FIG. 4, if the control signals S 1 , . . . , S k−1  are “0” and the control signals S k , . . . , S m  are “1”, the blocks B 11 , . . . , B 1,      k−1    as well as the block B 10  serve as a program memory, and the blocks B 20  and B 30  serve as a data memory. 
     In FIG. 5, which illustrates a second embodiment of the memory system according to the present invention, the blocks variable B 11 , B 12 , . . . , B 2     m    of the program memory are not provided. Instead of this, variable blocks B 21 , B 22 , . . . , B 2     n    are provided in the X-data memory  2  and variable blocks B 31 , B 32 , . . . , B 3     n    are provided in the Y-data memory  3 . 
     In the X-data memory  2 , the blocks B 21 , B 22 , . . . , B 2     n    are connected by respective selectors SEL 21 , SEL 22 , . . . , SEL 2     n    to the program bus  4  or the data bus  5 . For example, if a control signal S 1 ′ is “0”, the selector SEL 21  connects the block B 21  to the X-data bus  5 , while, if the control signal S 1 ′ is “1”, the selector SEL 21  connects the blocks B 21  to the program bus  4 . 
     In the Y-data memory  3  the blocks B 31 , B 32 , . . . , B 3     n    are connected by respective multi-state selectors SEL 31 , SEL 32 , . . . , SEL 3     m    to the program bus  4  or the data bus  6 . For example, if the control signal S 1 ′ is “0”, the selector SEL 31  connects the block B 31  to the Y-data bus  6 , while, if the control signal S 1 ′ is “1”, the selector SEL 31  connects the blocks B 31  to the program bus  4 . 
     Also, note that the blocks B 10 , B 20  and B 30  are fixed areas, as illustrated in FIG. 2, in the same way as in the first embodiment. 
     The blocks B 21 , B 22 , . . . , B 2     n    of the X-data memory  2  and the blocks B 31 , B 32 , . . . , B 3     n    of the Y-data memory  3  are variable areas. One of the blocks B 21 , B 22 , . . . , B 2     n    such as B 2     i   , and one of the blocks B 31 , B 32 , . . . , B 3     n    such as B 3     i    are explained next in detail with reference to FIGS. 6A,  6 B and  6 C. 
     As illustrated in FIG. 6A, the selector SEL 2     i    is formed by selectors  61  and  62 . The selector  61  is connected via an address decoder  63  to the block B 2     i   . Similarly, the selector SEL 3     i    is formed by selectors  64  and  65 . The selector  64  is connected via an address decoder  66  to the block B 3     i   . The state of selectors SEL 2i  and SEL 3i  determines if memory blocks B 2i  and B 3i  serves as separate 16 bit data memory blocks or as a combined 32 bit program memory block. 
     As illustrated in FIG. 6B, when the control signal S i ′ is “0”, the selector  61  selects the value XDP and transmits it to the address decoder  63 . Simultaneously, the selector  62  connects the 16-bit input/outputs of the block B 2     i    to the X-data bus  5 . Similarly, the selector  64  selects the value YDP and transmits it to the address decoder  66 . Simultaneously, the selector  65  connects the 16-bit input/outputs of the block B 3     i    serve as data memory blocks. 
     On the other hand, as illustrated in FIG. 6C, when the control signal S i ′ is “1”, the selector  61  selects the value PC and transmits it to the address decoder  63 . Simultaneously, the selector  62  connects the 16-bit input/outputs of the block B 2     i    to the program bus  4 . Similarly, the selector  64  selects the value PC and transmits it to the address decoder  66 . Simultaneously, the selector  65  connects the 16-bit input/outputs of the block B 3     i    to the program bus  4 . Thus, the blocks B 2     i    and B 3     i    serve as a program memory block. 
     As illustrated in FIG. 7, if the control signals S 1 ′, . . . , S k−1 ′ are “0” and the control signals S k ′, . . . , S n ′ are “1”, the blocks B 2     k   , . . . , B 2     n   , and B 3     k   , . . . , B 3     n    as well as the block B 10  serve as a program memory, and the blocks B 21 , . . . , B 2,      k−1   and B 31 , . . . , B 3,      k−1    as well as the blocks B 20  and B 30  serve as a data memory. 
     In FIG. 8, which illustrates a third embodiment of the memory system according to the present invention, the memory system of FIG. 1 is combined with the memory system of FIG.  5 . That is, in the program memory  1 , the block B 10  is a fixed area which serves as a program memory block, and the blocks B 11 , B 12 , . . . , B 1     m    serve as program memory blocks or data memory blocks in accordance with the control signals S 1 , S 2 , . . . , S m , and the resulting states of selectors SEL 11 , SEL 12 , . . . , SEL 1m . Also, in the program memories  2  and  3 , the blocks B 20  and B 30  are fixed areas which serve as data memory blocks, and the blocks B 21 , B 22 , . . . , B 2     n    and B 31 , B 32 , . . . , B 3     n    serve as program memory blocks or data memory blocks in accordance with the control signals S 1 ′, S 2 ′, . . . , S m ′. 
     As explained hereinabove, according to the present invention, since a program space and a data space are relocatable between the program memory and the data memories, effective use is made of the program memory and the data memories.