Abstract:
A shift register increases a number of thin film transistors for lowering drive and a manner of alternatively applying clock signals every other frame, lowers duty cycle of the thin film transistors for lowering drive, and effectively prevents a biasing effect by the thin film transistors for lowering drive, thereby reliability of the shift register unit is guaranteed.

Description:
TECHNICAL FIELD 
     The present invention relates to a shift register, a gate drive apparatus and a data line apparatus for a liquid crystal display (LCD). 
     BACKGROUND 
     A shift register unit in related arts includes a signal output terminal for outputting a driving signal. The shift register unit controls a row of thin film transistors (TFTs) to be turned on when the driving signal is at a high level and to be turned off when the driving signal is at a low level. 
     A LCD generally employs a way of progressive scanning, in which when a certain row or column is scanned, a corresponding shift register unit outputs a driving signal at a high level, and each of the other shift register units outputs a driving signal at a low level. It can be seen that, for one shift register unit, the driving signal thereof is at a low level for most of time. 
     During a period when the driving signal is at a low level, the driving signal is highly inclined to be influenced by an inputted clock signal, so that a noise may be generated. To suppress the noise, the shift register unit generally includes a lowering signal TFT for pulling down the driving signal during a period when the driving signal is at the low level. A junction node connected to the gate of the lowering signal TFT controls the lowering signal TFT to be turned on, thereby the level of the gate driving signal at the signal output terminal can be pulled down. 
     A problem existing in the shift register unit of the related art is that, the node connected to the gate of the lowering signal TFT is generally kept at a high level for most of time. and in this way, the lowering signal TFT remains conductive for most of time, which makes the threshold voltage of the lowering signal TFT generate a relatively large offset. If the threshold voltage of the lowering signal TFT is boosted constantly. it may cause the lowering signal TFT to fail to turn on and thereby to fail to serve to suppress the noise, thus performance of the shift register as a whole will be influenced. 
     SUMMARY 
     An embodiment of the present invention provides a shift register comprising at least two shift register units, one of which comprising: a boosting signal TFT for receiving a first clock signal, and outputting a high voltage signal to an output terminal in a conductive state thereof; a first boosting drive TFT for receiving a frame start signal or an output signal of another shift register unit so as to turn on the boosting signal TFT; a second boosting drive TFT for receiving a reset signal or an output signal of another shift register so as to turn on the boosting signal TFT; a first lowering signal TFT for receiving the reset signal or the output signal of the other shift register, and outputting a low voltage signal to the output terminal in conductive state thereof; a first lowering drive TFT for receiving a second clock signal so as to turn on a lowering signal TFT; a second lowering drive TFT for receiving a third clock signal so as to turn on the lowering signal TFT; a second lowering signal TFT for receiving the output signal of the first lowering drive TFT, and lowering the output signal of the output terminal in conductive state thereof; a third lowering signal TFT for receiving the output signal of the first lowering drive TFT, and lowering output signal of the output terminal in conductive state thereof; a first off-drive TFT for receiving the output signal of the first boosting drive TFT, and turning off the second lowering signal TFT and the third lowering signal TFT in conductive state thereof; a fourth lowering signal TFT for receiving the output signal of the second lowering drive TFT, and lowering the output signal of the output terminal in conductive state thereof; a fifth lowering signal TFT for receiving the output signal of the second lowering drive TFT, and lowering the output signal of the output terminal in conductive state thereof; and a second off-drive TFT for receiving the output signal of the first boosting drive TFT, and turning off the fourth lowering signal TFT and the fifth lowering signal TFT in conductive state thereof, and in the other shift register unit adjacent to said shift register unit, a boosting signal TFT, a first lowering drive TFT and a second lowering drive TFT receiving a fourth clock signal, a fifth clock signal and a sixth clock signal respectively. 
     Hereinafter, a further detailed description will be made to the present invention with specific embodiments and in connection with appended drawings. dr 
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1   a  shows a structure diagram for a shift register unit according to the invention; 
       FIG. 1   b  shows a timing chart of input versus output of the shift register unit shown in  FIG. 1   a;    
       FIG. 2   a  shows a structure diagram for another shift register unit according to the invention; and 
       FIG. 2   b  shows a timing chart of input versus output of the other shift register unit shown in  FIG. 2   a.    
    
    
     DETAILED DESCRIPTION 
     In embodiments of the present invention, there is disclosed a shift register comprising at lease two shift register units. 
     As shown in  FIG. 1   a , in the shift registers according to an embodiment of the present invention, at least one shift register unit comprises a boosting signal TFT T 3  for receiving a first clock signal CLK, and outputting a high voltage signal to an output terminal in a conductive state thereof; a first boosting drive TFT T 1  for receiving a frame start signal or an output signal of the previous one shift register unit so as to turn on the boosting signal TFT T 3 ; a second boosting drive TFT T 2  for receiving an output signal of the next one shift register so as to turn on the boosting signal TFT T 3 ; a first lowering signal TFT T 4  for receiving the output signal of the next one shift register, and outputting a low voltage signal to the output terminal in the conductive state thereof; a first lowering drive TFT T 5  for receiving a second clock signal CLKB 1  so as to turn on a second lowering signal TFT T 10  and a third lowering signal TFT T 11 ; a second lowering drive TFT T 5 - 1  for receiving a third clock signal CLKB 2  so as to turn on a fourth lowering signal TFT T 10 - 1  and a fifth lowering signal TFT T 11 - 1 ; a second lowering signal TFT T 10  for receiving an output signal of the first lowering drive TFT T 5 , and lowering the output signal of the output terminal in conductive state thereof; a third lowering signal TFT T 11  for receiving the output signal of the first lowering drive TFT T 5 , and lowering the output signal of the output terminal in conductive state thereof; the fourth lowering signal TFT T 10 - 1  for receiving an output signal of the second lowering drive TFT T 5 - 1 , and lowering the output signal of the output terminal in conductive state thereof; a first off-drive TFT T 6  for receiving the output signal of the first boosting drive TFT T 1 , and turning off the second lowering signal TFT T 10  and the third lowering signal TFT T 11  in conductive state thereof; a second off-drive TFT T 6 - 1  for receiving the output signal of the first boosting drive TFT T 1 , and turning off the fourth lowering signal TFT T 10 - 1  and the fifth lowering signal TFT T 11 - 1  in conductive state thereof. 
     As shown in  FIG. 2   a , in another shift register unit of the shift register according to the embodiment of the present invention, the boosting signal TFT t 3 , the first lowering drive TFT t 5  and the second lowering drive TFT t 5 - 1  respectively receive a fourth clock signal CLKB, a fifth clock signal CLK 1  and a sixth clock signal CLK 2 . 
     The second clock signal and the third clock signal received by the shift register unit provided in the embodiment of the present invention are clock signals alternatively outputted every other frame. 
     The fifth clock signal and the sixth clock signal received by the shift register unit provided in the embodiment of the present invention are clock signals alternatively outputted every other frame. 
     It should be explained that, for the TFT employed in the field of the liquid crystal display, the drain and the source can be exchanged with each other. Therefore, the source of TFT mentioned in the embodiment of the present invention can be replaced with the drain of the TFT, and the drain of the TFT also can be replaced with the source of the TFT. 
     Hereinafter, the operation principle of the shift register units according to the embodiment of the present invention will be explained in connection with the  FIGS. 1   a  and  1   b.    
     A part of the first frame of the timing chart shown in  FIG. 1   b  is selected and a first two stages thereof are selected. At the first stage, an input signal (INPUT) is a frame start signal (STV), which is at the high level, and the first boosting drive TFT T 1  is turned on and the voltage at PU node is boosted; the first off-drive TFT T 6  and the second off-drive TFT T 6 - 1  are turned on, so that the voltages at PD 1  and PD 2  nodes are at the low level, thus the second lowering signal TFT T 10  and the third lowering signal TFT T 11  are turned off; the auxiliary TFTs T 8  and T 8 - 1  are turned on, and the first lowering drive TFT T 5  and the second lowering drive TFT T 5 - 1  are discharged; the boosting signal TFT T 3  is turned on, and the first clock signal CLK is at the high level at this timing, therefore the output signal (OUTPUT) of the signal output terminal (OUT) is at the high level, the input signal (RESET) of the reset signal input terminal (RESETIN) is at the low level, and the second boosting drive TFT T 2  and the first lowering signal TFT T 4  are turned off. 
     At the second stage, the input signal (INPUT) is at the low level, and the first boosting drive TFT T 1  is turned off; the reset signal (RESET) is at the high level, the second boosting drive TFT T 2 , the first lowering signal TFT T 4  are turned on, the PU node is discharged to become a the low level, and the output signal (OUTPUT) of the signal output terminal (OUT) becomes a the low level under effect of pulling down by the first lowering signal TFT T 4 ; the second clock signal (CLKB 1 ) is at the high level, the first lowering drive TFT T 5  is turned on and the voltage at PD 1  node is boosted, so that the second lowering signal TFT T 10  and the third lowering signal TFT T 11  are turned on, and the output signal (OUTPUT) of the signal output terminal (OUT) becomes a the low level under effect of pulling down by the second lowering signal TFT T 10  and the third lowering signal TFT T 11 . Therefore, a duty cycle of the lowering drive TFT is lowered as compared with that of the existing lowering drive TFT, and a biasing effect of the TFTs for lowering drive can be effectively prevented. That is, the first lowering signal TFT T 4 , the second lowering signal TFT T 10  and the third lowering signal TFT T 11  are allowed to serve to suppress the noise, and the reliability of the shift register unit can be guaranteed. 
     A part of the second frame of the timing chart shown in  FIG. 1   b  is selected and a first two stages thereof are selected. At the first stage, the input signal (INPUT) is a frame start signal (STV), which is at the high level, and the first boosting drive TFT T 1  is turned on and the voltage at PU node is boosted; the first off-drive TFT T 6  and the second off-drive TFT  16 - 1  are turned on, so that the voltages at PD 1  and PD 2  nodes are at the low level, thus the second lowering signal TFT T 10  and the third lowering signal TFT T 11  are turned off; the auxiliary TFTs T 8  and T 8 - 1  are turned on, and the first lowering drive TFT T 5  and the second lowering drive TFT T 5 - 1  are discharged; the boosting signal TFT T 3  is turned on, and the first clock signal CLK is at the high level at this timing, therefore the output signal (OUTPUT) of the signal output terminal (OUT) is at the high level, the input signal (RESET) of the reset signal input terminal (RESETIN) is at the low level, and the second boosting drive TFT T 2  and the first lowering signal TFT T 4  are turned off. 
     At the second stage, the input signal (INPUT) is at the low level, and the first boosting drive TFT T 1  is turned off; the reset signal (RESET) is at the high level, the second boosting drive TFT T 2  and the first lowering signal TFT T 4  are turned on, the PU node is discharged to the low level, and the output signal (OUTPUT) of the signal output terminal (OUT) becomes the low level under effect of pulling down by the first lowering signal TFT T 4 ; the third clock signal (CLKB 1 ) is at the high level, the second lowering drive TFT T 5 - 1  is turned on and the voltage at PD 2  node is boosted, so that the fourth lowering signal TFT T 10 - 1 , the fifth lowering signal TFT T 11 - 1  are turned on, and the output signal (OUTPUT) of the signal output terminal (OUT) becomes the low level under effect of pulling down by the fourth lowering signal TFT T 10 - 1  and the fifth lowering signal TFT T 11 - 1 . Therefore, a duty cycle of lowering drive TFT is lowered as compared with that of the existing lowering drive TFT, and a biasing effect of the TFTs for lowering drive can be effectively prevented. That is, the first lowering signal TFT T 4 , the fourth lowering signal TFT T 10 - 1  and the fifth lowering signal TFT T 11 - 1  are allowed to serve to suppress the noise, and the reliability of the shift register unit can be guaranteed. 
     In the process of operation of the above shift register, the first auxiliary TFT T 8  and the second auxiliary TFT T 8 - 1  respectively receive the output signal of the first boosting drive TFT T 1 , and in conductive state thereof discharge the first lowering drive TFT T 5  and the second lowering drive TFT T 5 - 1 ; the third auxiliary TFT T 7 , the fourth auxiliary TFT T 9  and the fifth auxiliary TFT T 9 - 1  respectively receive the first clock signal CLK 1 , the second clock signal CLKB 1  and the third clock signal CLKB 2 , and in conductive state thereof reduce biasing effects of the boosting signal TFT T 3 , the first lowering drive TFT T 5  and the second lowering drive TFT T 5 - 1 . 
     In the above shift register unit, two terminals of a capacitor C 1  are respectively connected to the gate of the boosting signal TFT T 3  and the signal output terminal (OUT). When the shift register unit is operated, the level of signal at the PU junction node can be boosted to a relatively high level due to coupling effect by the first capacitor C 1 . 
     Shown in  FIG. 2   a  is a structure diagram for another shift register unit according to an embodiment of the present invention. 
     Shown in the  FIG. 2   b  is a timing chart of input versus output of the other shift register unit shown in  FIG. 2   a.    
     The operation principles of the other shift register as shown in  FIGS. 2   a  and  2   b  are similar to those of the above shift register, and description thereof will be no more repeated herein. 
     In other embodiments of the present invention, there are further provided a gate drive apparatus and a data line drive apparatus for a LCD comprising the above shift register (not shown). The gate drive apparatus and the data line drive apparatus can be arranged on the display panel of the LCD. 
     The shift register provided in the embodiments of the present invention can lower the duty cycle of the TFTs for lowering drive and effectively lower the bias effect by the TFTs for lowering drive, thereby the reliability of the shift register unit can be guaranteed. 
     Finally, it should be explained that, the above embodiments are only used to explain the technical solution of the present invention, and not for limitation thereto. Although the present invention has been explained in details with reference to the above embodiments, it should be understood by those skilled in the art that, the technical solution described in the above respective embodiments still can be modified, or part of the technical features thereof can be equivalently substituted, and these modifications or substitutions can not depart the essence of a corresponding technical solution from the spirit and scope of the technical solution according to the embodiments of present invention.