Abstract:
A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a multi-port memory device, and more particularly, to a bank control logic unit of a multi-port memory device having a command generating circuit. 
     DESCRIPTION OF RELATED ARTS 
     Currently, most dynamic random access memory (DRAM) are used in a high definition television (HDTV) and a liquid crystal display (LCD) TV as well as traditional devices such as a desktop computer, a notebook computer and a server. Accordingly, there is a demand for a new data communication instead of a conventional data communication having a single port with a plurality of input/output (I/O) pin sets, i.e., a parallel I/O interface. 
       FIG. 1  is a block diagram of a conventional single port memory device. For convenience of explanation, a conventional x16 512M DRAM device having eight banks as the single port memory device is illustrated. 
     The conventional x16 512M DRAM device includes a plurality of memory cells, first to eighth banks BANK 0  to BANK 7 , a single port PORT, and a plurality of global input/output (I/O) data buses GIO. The plurality of memory cells is arranged with a plurality of N×M memory cells having a matrix form, M and N being positive integers. The first to eighth banks BANK 0  to BANK 7  include a row/column decoder for selecting a specific memory cell by row and column lines. The single port PORT controls signals inputted from or outputted to the first to eighth banks BANK 0  to BANK 7 . The global I/O data buses GIO transfers signals between the single port and the banks, and between the single port and input/output (I/O) pins. Referring to  FIG. 1 , the global I/O data buses GIO include a control bus, fifteen address buses and sixteen data buses. 
     As described above, the single port memory device includes only a single port with a plurality of I/O pin sets for transferring data signals between the single port memory device and external devices via an external chipset. 
     A process for transferring signals from the banks to the external devices is described. The signals outputted from the first to eighth banks BANK 0  to BANK 7  through the sixteen data buses are transferred to the external devices in parallel through the external chipset by way of the single port PORT. 
     A process for transferring signals from the external devices to the banks is described. The signals outputted from the external devices in parallel through the external chipset are transferred to the single port PORT, and then are transferred to the first to eighth banks BANK 0  to BANK 7  through the sixteen data buses. The transferred signals are transferred to the memory cells under the control of a control unit provided within the banks, e.g., a decoder and a driver. 
     Meanwhile, the signals transferred to the external devices from the first to eighth banks BANK 0  to BANK 7  include an address and a command as well as data signals. The address and command are transferred to the single port PORT from the external devices in parallel via extra input/output address and command pins except for the sixteen data buses. The command transferred to the single port PORT is inputted to the banks through the single control bus, and the address transferred to the single port PORT is inputted to the banks through the fifteen address buses. 
     However, in the single port memory device, it is difficult to implement various multimedia functions because the single port memory device uses only one port. To implement the various multimedia functions in the single port memory device, each DRAM device has to be constituted independent of each other so as to perform its unique function. When the DRAM devices are constituted independent of each other, it is difficult to allocate a proper memory amount between memory devices based on the number of access times. As a result, an efficiency of utilization to density of the whole memory device is decreased. 
     For reference, there is suggested a semiconductor memory device described in a commonly owned copending application, U.S. Ser. No. 11/528,970, filed on Sep. 27, 2006, entitled “MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE”. 
       FIG. 2  is a block diagram of a multi-port memory device described in accordance with Korea application No. 2006-0032948. For convenience of explanation, the multi-port memory device having four ports and eight banks is illustrated. Particularly, it is assumed that the multi-port memory device has a 16-bit data frame and performs a 64-bit prefetch operation. 
     The multi-port memory device includes first to fourth ports PORT 0  and PORT 3 , first to eighth banks BANK 0  to BANK 7 , first and second global input/output (I/O) data buses GIO_OUT and GIO_IN, first to eighth bank control logic units BCL 0  to BCL 7 , and a phase locked loop (PLL)  101 . 
     Each of the first to fourth ports PORT 0  and PORT 3  located at a center of a core is arranged in a row direction, and performs a serial data communication with its own external device independent of each other. The first to eighth banks BANK 0  to BANK 7  are divided into upper banks BANK 0  to BANK 3  and lower banks BANK 4  to BANK 7  based on the first to fourth ports PORT 0  to PORT 3  and arranged in the row direction. 
     The first global I/O bus GIO_OUT is arranged in the row direction between the upper banks BANK 0  to BANK 3  and the first to fourth ports PORT 0  to PORT 3 , and transmits output data in parallel. The second global I/O bus GIO_IN is arranged in the row direction between the lower banks BANK 4  to BANK 7  and the first to fourth ports PORT 0  to PORT 3 , and transmits input data in parallel. 
     The first to eighth bank control logic units BCL 0  to BCL 7  control a signal transmission between the first and second global I/O buses GIO_OUT and GIO_IN and the first to eighth banks BANK 0  to BANK 7 . 
     The PLL  101  is located between the second port PORT 1  and the third port PORT 2  and generates an internal clock for synchronizing internal commands and I/O data applied to the first to fourth ports PORT 0  to PORT 3 . 
     The multi-port memory device can be used as a memory device of a digital device for processing mass data at a high speed because the multi-port memory device includes the plurality of ports PORT 0  to PORT 3  and each port can perform its own operation independently. 
     The multi-port memory device generates addresses and internal commands by receiving input parallel data from the first to fourth ports PORT 0  to PORT 3 . Further, the multi-port memory device recognizes whether the input parallel data are addresses/internal commands or data based on a predetermined protocol, i.e., data frames. 
       FIG. 3  illustrates data frame formats of the multi-port memory device shown in  FIG. 2 . Specifically,  FIGS. 3A to 3F  illustrate a basic data frame format, a write command frame format, a write data frame format, a read command frame format, a read data frame format, and a command frame format, respectively. 
     Referring to  FIG. 3B , the write command frame is a unit of 20-bit serialized signals input from the external devices. 18 th  and 19 th  bits “PHY” among the 20-bit serialized signals correspond to a physical link coding bit which is substantially not used, a 17 th  bit “CMD” means a command start point, a 16 th  bit “ACT” indicates an internal active state, a 15 th  bit “WT” corresponds to an internal write command, and a 14 th  bit “PCG” indicates an internal inactive state. For example, during a normal write operation, 17 th  to 14 th  bits become “1010”. During an auto-precharge write operation, 17 th  to 14 th  bits become “1011”. 13 th  to 10 th  bits “UDM” are used as an upper-byte write data mask signal of write data applied over four clocks, 9 th  to 6 th  bits “BANK” mean bank information during the write operation, and the 5 th  to 0 th  bits “COLUMN ADDRESS” mean a column address. 
     Referring to  FIG. 3C , 18 th  and 19 th  bits “PHY” of the write data frame correspond to a physical link coding bit which is substantially not used, a 17 th  bit “CMD” means a command start point, a 16 th  bit “LDM” is used as a lower-byte write data mask signal of the write data, and each of 15 th  to 8 th  bits “UPPER BYTE” and 7 th  to 0 th  bits “LOWER BYTE” means an upper byte and a lower byte of the write data, respectively. Herein, if the write data is normally applied, the 17 th  bit “CMD” becomes a logic low level “0”. 
     Referring to  FIG. 3D , 18 th  and 19 th  bits “PHY” of the read command frame correspond to a physical link coding bit which is substantially not used, a 17 th  bit “CMD” means a command start point, a 16 th  bit “ACT” indicates an internal active state, a 15 th  bit “WT” corresponds to an internal write command, a 14 th  bit “PCG” indicates an internal inactive state and a 13 th  bit “RD” is indicates a read command. For a normal read operation, the 17 th  to 13 th  bits become “10001”. During an auto-precharge read operation, the 17 th  to 13 th  bits become “10011”. 
     Meanwhile, a 12 th  bit “ESC” of the read command frame indicates a command expansion bit. For instance, if the 17 th  bit “CMD” is a logic high level “1”, the 14 th  bit “PCG” is a logic high level “1”, and the 13 th  bit “RD” is a logic high level “1”, all banks perform a precharge operation. That is, the precharge operation or an auto refresh operation of all banks is performed by using the command expansion bit “ESC” and other command bits because there is no command representing “PRECHARGE ALL” bit. 
     An 11 th  bit “ABNK” of the read command frame indicates a bank active bit setting while the 13 th  bit “RD” is set. 9 th  to 6 th  bits “BANK” mean bank information during the read operation, and the 5 th  to 0 th  bits “COLUMN ADDRESS” mean a column address. 
     Referring to  FIG. 3E , 18 th  and 19 th  bits “PHY” of the read data frame correspond to a physical link coding bit which is substantially not used, and each of 15 th  to 8 th  bits “UPPER BYTE” and 7 th  to 0 th  bits “LOWER BYTE” means an upper byte and a lower byte of the read data, respectively. 
     The multi-port memory device using the above data frames receives and transmits parallel data from the memory cells via the first and second global I/O data buses GIO_OUT and GIO_IN. Herein, because the first and second global I/O data buses GIO_OUT and GIO_IN have lots of lines, the first to eighth bank control logic units BCL 0  to BCL 7  share the first and second global I/O data buses GIO_OUT and GIO_IN. 
     The multi-port memory device generates commands and addresses based on the parallel data. The conventional DRAM device decodes the commands input from command pins, and transmits the decoded commands to the banks. On the other hand, the multi-port memory device for concurrently performing various operations requires a new method to generate commands and addresses, different from that of the conventional DRAM device. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a multi-port memory device for simultaneously generating internal commands of each bank control logic unit. 
     It is, therefore, another object of the present invention to provide a multi-port memory device for simultaneously applying parallel data to each bank control logic unit. 
     In accordance with an aspect of the present invention, there is provided a multi-port memory device having a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes: a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal. 
     In accordance with a further aspect of the present invention, there is provided a multi-port memory device including: a plurality of ports for performing a serial input/output (I/O) communication with external devices; a plurality of banks for performing a parallel I/O communication with the ports through a plurality of global I/O lines; a plurality of bank controllers, each corresponding to each of the banks, for sharing the plurality of global I/O lines and controlling the parallel I/O communication between the ports and the banks; and a phase locked loop (PLL) unit for generating an internal clock signal and simultaneously transmitting the internal clock signal to the bank controllers, wherein each of the bank controllers includes a command signal generating unit for simultaneously generating command signals in response to the internal clock signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a conventional single-port memory device; 
         FIG. 2  is a block diagram of a multi-port memory device described in accordance with Korea application No. 2006-0032948; 
         FIG. 3  illustrates data frames of the multi-port memory device shown in  FIG. 2 ; 
         FIG. 4  is a block diagram of a multi-port memory device in accordance with an embodiment of the present invention; 
         FIG. 5  is a block diagram of a first command signal generating unit provided in a first bank control logic unit of the multi-port memory device shown in  FIG. 4 ; 
         FIG. 6  is a circuit diagram of a serializer of the first command signal generating unit shown in  FIG. 5 ; 
         FIG. 7  is a circuit diagram of a command decoder of first command signal generating unit shown in  FIG. 5 ; and 
         FIG. 8  is a timing diagram showing an operation of the first command signal generating unit shown in  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, a multi-port memory device in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
       FIG. 4  is a block diagram of a multi-port memory device in accordance with an embodiment of the present invention. 
     The present invention delays a clock signal for clocking an input/output of parallel data which is generated by a PLL and output from each of first to fourth ports PORT 0  to PORT 3 , and generates command signals after all of the parallel data are applied. Herein, the parallel data are applied with a time lag due to a loading difference. 
     As shown in  FIG. 4 , because a global clock bar signal GCLKB output from the PLL is transmitted to all constituents of the multi-port memory device, the global clock bar signal GCLKB has a great loading time to thereby occur a skew at each bank. To minimize the skew at each bank, the multi-port memory device of the present invention includes a first repeater  301  between the first port PORT 0  and the second port PORT 1 , and a second repeater  303  between the third port PORT 2  and the fourth port PORT 3 , each repeater for repeating the global clock bar signal GCLKB output from the PLL. 
     The first repeater  301  receives the global clock bar signal GCLKB from the PLL to generate first sub-global clock signal GCLK_ 01  and second sub-global clock signal GCLK_ 23 . The first sub-global clock signal GCLK_ 01  is input to first and second bank control logic units BCL 0  and BCL 1  as an internal clock signal and the second sub-global clock signal GCLK_ 23  is input to third and fourth bank control logic units BCL 2  and BCL 3  as an internal clock signal. 
     The second repeater  303  receives the global clock bar signal GCLKB to generate third sub-global clock signal GCLK_ 45  and fourth sub-global clock signal GCLK_ 67 . The third sub-global clock signal GCLK_ 45  is input to fifth and sixth bank control logic units BCL 4  and BCL 5  as an internal clock signal and the fourth sub-global clock signal GCLK_ 67  is input to seventh and eighth bank control logic units BCL 6  and BCL 7  as an internal clock signal. 
     As described above, the first and second repeaters  301  and  303  repeat the global clock bar signal GCLKB and generate a plurality of sub-global clock signals, each for inputting a corresponding one of the bank control logic units BCL 0  to BCL 7  at the same time. As a result, the skew between the bank control logic units BCL 0  to BCL 7  can be removed, and thus, the command signals of each bank control logic unit BCL 0  to BCL 7  are simultaneously generated. 
       FIG. 5  is a block diagram of a first command signal generating unit IG 0  provided in the first bank control logic unit BCL 0  of the multi-port memory device shown in  FIG. 4 . The other command signal generating units provided in the second to eighth bank control logic units BCL 1  to BCL 7  have substantially the same structure as that of the first command signal generating unit IG 0  provided in the first bank control logic unit BCL 0 . 
     The first command signal generating unit IG 0  includes first and second delay units  601  and  603 , a serializer  605  and a command decoder  607 . 
     The first delay unit  601  delays the global clock bar signal GCLKB by a predetermined time to generate a first delayed clock signal BCLK. The second delay unit  603  delays the first delayed clock signal BCLK by a predetermined time to generate a second delayed clock signal CCLK. The serializer  605  receives a plurality of parallel data PORTi_RX&lt; 0 : 17 &gt; from the first and fourth ports PORT 0  to PORT 3 , i being a positive integer corresponding to the number of ports, to fit the parallel data for a corresponding data frame in response to the first delayed clock signal BCLK. Herein, the serializer  605  can be implemented with a flip-flop. The command decoder  607  decodes output data B_RXT&lt; 0 : 17 &gt; output from the serializer  605  to generates the command signals such as an active command signal ACTP, a read command signal CASPRD and a write command signal ECASPWT, in response to the second delayed clock signal CCLK. 
     As described above, the present invention repeats the global clock bar signal GCLKB to thereby generate the sub-global clock signals GCLK_ 01  to GCLK_ 67  having different delay times according to the bank control logic units BCL 0  to BCL 7 . As a result, all of the bank control logic units BCL 0  to BCL 7  receive the parallel data PORTi_RX&lt; 0 : 17 &gt; from the first and fourth ports PORT 0  to PORT 3  in response to its own sub-global clock signal. 
     Further, the command signal generating unit of each bank control logic unit BCL 0  to BCL 7  uses the first delayed clock signal BCLK generated by delaying the global clock bar signal GCLKB, and the second delayed clock signal CCLK generated by delaying the first delayed clock signal BCLK. Herein, the first delayed clock signal BCLK is generated by delaying the global clock bar signal GCLKB until all of the parallel data PORTi_RX&lt; 0 : 17 &gt; are applied. Accordingly, the parallel data PORTi_RX&lt; 0 : 17 &gt; are applied and output as the output data B_RXT&lt; 0 : 17 &gt; in response to the first delayed clock signal BCLK, and the command signals are generated in response to the second delayed clock signal CCLK. 
     Therefore, in the present invention, though the parallel data PORTi_RX&lt; 0 : 17 &gt; are applied with the time lag due to the loading difference between the bank control logic units BCL 0  to BCL 7 , the command signals are simultaneously generated after all of the parallel data PORTi_RX&lt; 0 : 17 &gt; are applied. 
       FIG. 6  is a circuit diagram of the serializer  605  of the first command signal generating unit shown in  FIG. 5 . 
     The serializer  605  includes a transmission unit  701 , a latch unit  703 , a multiplexing unit  705 , and first and second inverters INV 8  and INV 9 . 
     The multiplexing unit  705  selects one of the plurality of parallel data PORTi_RX&lt; 0 : 17 &gt; from the first and fourth ports PORT 0  to PORT 3  in response to the bank selection signal BK 13  SELECT, and fits the selected parallel data PORT_RX&lt; 0 : 17 &gt; for the corresponding data frame. The first inverter INV 8  inverts the first delayed clock signal BCLK. The transmission unit  701  transmits the selected parallel data PORT_RX&lt; 0 : 17 &gt; in response to an output of the first inverter INV 8 . The latch unit  703  latches an output of the transmission unit  701 . The second inverter INV 9  inverts an output of the latch unit  703  to output the output data B_RXT&lt; 0 : 17 &gt;. 
       FIG. 7  is a circuit diagram of the command decoder  607  of the first command signal generating unit shown in  FIG. 5 . 
     The command decoder  607  includes first to sixth AND gates AND 1  to AND 6 , first to seventh inverters INV 1  to INV 7 , and first and second NOR gate NOR 1  and NOR 2 . 
     The first AND gate AND 1  performs an AND operation to a 17 th  bit B_RXT&lt; 17 &gt; “CMD” and a 16 th  bit B_RXT&lt; 16 &gt; “ACT” of the output data B_RXT&lt; 0 : 17 &gt;. The first inverter INVL inverts an output of the first AND gate AND 1  to output a pre-active command signal PACT. The second AND gate AND 2  performs an AND operation to the pre-active command signal PACT and the second delayed clock signal CCLK output from the second delay unit  603 . The second inverter INV 2  inverts an output of the second AND gate AND 2  to output the active command signal ACTP. 
     The third inverter INV 3  inverts the 16 th  bit B_RXT&lt; 16 &gt; “ACT” of the output data B_RXT&lt; 0 : 17 &gt;. The third AND gate AND 3  performs an AND operation to an output of the third inverter INV 3  and the 17 th  bit B_RXT&lt; 17 &gt; “CMD” of the output data B_RXT&lt; 0 : 17 &gt;, thereby outputting a pre-read command signal CAS. The fourth inverter INV 4  inverts a 15 th  bit B_RXT&lt; 15 &gt; “WT” of the output data B_RXT&lt; 0 : 17 &gt;. The first NOR gate NOR 1  performs a NOR operation to an output of the fourth inverter INV 4  and the pre-read command signal CAS. The fourth AND gate AND 4  performs an AND operation to the pre-read command signal CAS and the second delayed clock signal CCLK. The fifth inverter INV 5  inverts an output of the fourth AND gate AND 4  to output the write command signal ECASPWT. 
     The sixth inverter INV 6  inverts a 12 th  bit B_RXT&lt; 12 &gt; “ESC” of the output data B_RXT&lt; 0 : 17 &gt;. The fifth AND gate AND 5  performs an AND operation to a 13 th  bit B_RXT&lt; 13 &gt; “RD” of the output data B_RXT&lt; 0 : 17 &gt; and outputs of the fourth and sixth inverters INV 4  and INV 6 . The second NOR gate NOR 2  performs a NOR operation to an output of the fifth AND gate AND 5  and the pre-read command signal CAS, thereby outputting a pre-write command signal PRD. The sixth AND gate AND 6  performs an AND operation to the pre-read command signal PRD and the second delayed clock signal CCLK. The seventh inverter INV 7  inverts an output of the sixth AND gate AND 6  to output the read command signal CASPRD. 
       FIG. 8  is a timing diagram showing an operation of the first command signal generating unit shown in  FIG. 5 . 
     Each port PORT 0  to PORT 3  transmits the parallel data PORTi_RX&lt; 0 : 17 &gt; to each bank control logic unit BCL 0  to BCL 7  via the second global I/O bus GIO_IN. (see {circle around (1)}). At this time, the parallel data PORTi_RX&lt; 0 : 17 &gt; are applied with the time lag due to the loading difference between the bank control logic units BCL 0  to BCL 7  (see {circle around (2)} and {circle around (3)}). The present invention includes the first and second repeaters  301  and  303  for repeating the global clock bar signal GCLKB and generating the first to fourth sub-global clock signals GCLK_ 01  to GCLK_ 67  having different the delay times according to the bank control logic units BCL 0  to BCL 7 . Accordingly, all of bank control logic units BCL 0  to BCL 7  receive the parallel data PORTi_RX&lt; 0 : 17 &gt; from the first and fourth ports PORT 0  to PORT 3  in response to its own sub-global clock signal. As a result, it is possible to reduce the time lag due to the loading difference of the second global I/O bus GIO_IN between the bank control logic units BCL 0  to BCL 7 . 
     Furthermore, the command signal generating unit of each bank control logic unit BCL 0  to BCL 7  delays the global clock bar signal GCLKB to generate the second delayed clock signal CCLK, and generates the internal command signals in response to the second delayed clock signal CCLK so that the internal command signals are generated after the parallel data PORTi_RX&lt; 0 : 17 &gt; input to all of the bank control logic units BCL 0  to BCL 7  are applied. Accordingly, the command signal generating unit of each bank control logic unit BCL 0  to BCL 7  generates the internal command signals at the same time (see {circle around (4)}). 
     As described above, in accordance with the present invention, the multi-port memory device generates the internal command by simultaneously inputting the global clock bar signal GCLKB from the PLL to each bank control logic unit BCL 0  to BCL 7 . After inputting the global clock bar signal GCLKB simultaneously, each bank control logic unit BCL 0  to BCL 7  delays its own global clock bar signal GCLKB by a predetermined time and generates the internal clock signals in response to the delayed clock signal so as to generate the internal command signals after the parallel data PORTi_ RX&lt; 0 : 17 &gt; input to all of the bank control logic units BCL 0  to BCL 7  are applied. As a result, each bank control logic unit BCL 0  to BCL 7  of the present invention can generate the internal command signals simultaneously. 
     Further, the multi-port memory device in accordance with the present invention can easily set a generation point of the command signals, and has good performance of a clock time in a DRAM core, i.e., tCK, because variation of the command signals at the generation point of the command signals is small. 
     The present application contains subject matter related to Korean patent application No. 2006-91628, filed in the Korean Intellectual Property Office on Sep. 21, 2006, the entire contents of which are incorporated herein by reference. 
     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.