Abstract:
A pulse generator is provided that includes: a current source, a source follower whose output controls the gate of a FET and a differential stage whose input voltage consists of inverting square waves and its output voltage consists of extremely narrow pulses widths, for example, of 30 to 40 ps and amplitude of 1.5 Volts.

Description:
TECHNICAL FIELD 
   The present invention relates generally to pulse generation and more particularly to ultra-wideband pulse generation. 
   BACKGROUND 
   The generation of narrow pulses occurs in a variety of fields including ultra-wideband (UWB) radios/radars and “Clock Data Recovery” (CDR) circuits. For example, ultra-wideband radios transmit information using narrow pulses with very small duty cycles. In this fashion the signal spectrum extends over a large bandwidth and can be buried in the ambient noise in a way that does not interfere with other services. Another important application of narrow pulses is in CDR circuits which retime the received data and remove the jitter accumulated during data transmission. For example, the random binary data obtained by optical receivers can not provide any direct information about the clock since it contains no spectral line at the bit rate. To create a frequency component at the bit rate, the data must undergo differentiation and rectification, which is also called “edge detection”. To realize differentiation and rectification in CDR integrated circuits, it is necessary to create short pulses during each data transition. 
   In general, the narrower the pulse that is generated, the more “ultra-wideband” is the resulting signal spectrum. Current state-of-the-art pulse generators are considered ultra-wideband with pulse widths in the hundreds of pico-seconds. But for certain high-frequency data transmission applications, such a pulse width is too broad. Moreover, an UWB radar increases its range resolution as the pulse width is narrowed. 
   Accordingly, there is a need in the art for improved UWB pulse generators. 
   SUMMARY 
   In accordance with an aspect of the invention, a pulse generator is provided that includes: a differential pair of transistors coupled between a first node and a second node, wherein a first one of the transistors in the pair has its gate driven by a voltage Vip that transitions periodically between a power supply voltage and wherein a remaining one of the transistors has its gate driven by a voltage Vin that is complementary to voltage Vip; a first current source that biases a current that flows between the first and second nodes; and a third transistor coupled between the first current source and the second node, wherein the third transistor is matched to the differential pair of transistors and driven by a level-shifted version of Vip, whereby as Vip is periodically brought low, a voltage pulse occurs at the first and second nodes, and whereby as Vin is periodically brought low, a voltage pulse also occurs at the first and second nodes. 
   In accordance with another aspect of the invention, a method of generating pulses for a circuit is provided. The circuit includes a differential pair of transistors coupled between a first node and a second node, a first current source that biases a current that flows between the first and second nodes, and a third transistor coupled between the current source and the second node, wherein the third transistor is matched to the differential pair of transistors. The method comprises the acts of: driving a gate of a first one of the transistors in the differential pair with a first square wave voltage that oscillates between ground and a power supply voltage while driving a gate of a remaining one of the transistors in the differential pair with a second square wave voltage that is complementary to the first square wave voltage; and driving a gate of the third transistor with a level-shifted version of the first square wave voltage, the level-shifting being such that the gate of the third transistor oscillates between a voltage lower than the power supply voltage and ground synchronously with the voltage oscillation at the gate of the first one of the transistor in the differential pair. 
   In accordance with another aspect of the invention, the pulse generator can be used for edge detection in CDR circuits. 
   The invention will be more fully understood upon consideration of the following detailed description, taken together with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram of an example pulse generator. 
       FIG. 2  illustrates simulated waveforms for the voltage at the source of Q 4  and the source of Q 2  in  FIG. 1 . 
       FIG. 3  illustrates the voltage waveforms at the source and gate of Q 4  in  FIG. 1 . 
       FIG. 4  illustrates the voltage waveforms at the source and gate of Q 3  in  FIG. 1 . 
       FIG. 5  illustrates the voltage waveform at the drains of Q 3  and Q 4  in  FIG. 1 . Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. 
   

   DETAILED DESCRIPTION 
   Reference will now be made in detail to one or more embodiments of the invention. While the invention will be described with respect to these embodiments, it should be understood that the invention is not limited to any particular embodiment. On the contrary, the invention includes alternatives, modifications, and equivalents as may come within the spirit and scope of the appended claims. Furthermore, in the following description, numerous specific details are set forth to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known structures and principles of operation have not been described in detail to avoid obscuring the invention. 
     FIG. 1  illustrates an example pulse generator  100 . A differential pair of transistors Q 4  and Q 3  have their gates driven by complementary rail-to-rail voltages Vip and Vin, respectively. In one embodiment, Vip is periodically asserted for 200 pico-seconds at a 50% duty cycle. Thus, in such an embodiment, Vin would also be asserted for 200 pico-seconds at a 50% duty cycle. The tail current through the differential pair of transistors Q 4  and Q 2  flows through a transistor Q 2  whose gate voltage is driven by a level-shifted version of either Vip or Vin. In pulse generator  100 , the gate of transistor Q 2  is driven by a level-shifted voltage Va derived from Vip. The drains of Q 4  and Q 3  are coupled through a resistor  105  to the power supply voltage VCC. Resistor  105  may comprise a transistor biased to operate in the triode mode of operation or other suitable means in the semiconductor arts for forming resistors. The level-shifting for Va and the resistor  105  ensure that Q 2  and Q 4  will be in the same mode of operation (saturation) when Vip is asserted. In addition, Q 2  should be matched to transistors Q 4  and Q 3  to further ensure this common saturation mode of operation when Vip is asserted. The power supply voltage applied when either of voltages Vip or Vin is asserted depends on the semiconductor manufacturing process used to manufacture the pulse generator. In one embodiment, the power supply may be 3 V such as used in 3V CMOS circuits but it will be appreciated that the power supply voltage may be widely varied depending upon the types of transistors used to implement the pulse generator. 
   In one embodiment, the level-shifting of voltage Va occurs through series-connected transistors M 2  and M 1  that couple between the power supply voltage VCC and ground. Va is the source voltage for M 2  (or equivalently, the drain voltage for M 1 ). M 1  has its gate driven by a constant voltage Vb, which may be derived from a suitable source such as a band gap reference (not illustrated). M 2  has its gate driven by the voltage-to-be-level-shifted, which in this embodiment is Vip. It may thus be seen that when Vip is asserted, Va will approximately equal Vip minus the gate-to-source voltage (Vgs) for transistor M 2 . M 1  will act as a current source while Vip is asserted. When Vip is de-asserted (grounded), transistor M 2  will no longer conduct. Because the current source transistor M 1  will also have to stop conducting at this time despite it constant gate voltage. Thus, the drain voltage of M 1  must go low when Vip is brought low, thereby pulling Va low as well. 
   A current source such as a transistor Q 1  couples between the drain of Q 2  and ground. Analogous to M 1 , the gate of Q 1  may be driven by the constant voltage Vb. It can be seen that the behavior of Q 2  and Q 1  will be similar to that of M 2  and M 1 , respectively. Thus, Q 2  will conduct a current determined by current source transistor Q 1  while Vip/Va is asserted. When Vip/Va are brought low, the current source transistor Q 1  must stop conducting despite its constant gate voltage. Thus, the drain of Q 1  (and thus the source of Q 2 ) will go low in response to Va going low. This abrupt voltage drop at the source of Q 2  affects the source of Q 4  as well—note that when Vip is asserted, transistors Q 2  and Q 4  are both in saturation and conducting the tail current determined by current source transistor Q 1 . The drain currents of Q 2  and Q 4  will be the same in saturation and are proportional to the quantity (Vgs−Vt) 2 , where Vgs is the gate-to-source voltage and Vt is the threshold voltage. Because the gate voltage Vip is higher than Va by the Vgs for transistor M 2 , the source voltage for Q 4  will equal the source voltage for Q 2  plus the Vgs for M 2 . Thus, when Vip is brought low, the source voltage for Q 4  will also abruptly drop in voltage as shown by the simulation results in  FIG. 2  for these source voltages where Vip and Vin each have an on-time of 200 pico-seconds with a rise/fall time of 10 pico-seconds.  FIG. 3  illustrates simulation results for the voltage drop at the source of Q 4  as compared to its gate voltage for the same driving waveform. This voltage drop form a pulse because transistor Q 3  will be transitioning on as Vip is brought low due to complementary voltage Vin being asserted. The source voltage of Q 4  will thus start to increase after its abrupt drop to ensure that the drain current of Q 3  does not become too large. 
   This abrupt voltage pulse at the source of Q 4  will also occur as Vip transitions high because the source of Q 4  must abruptly drop as Vip rises to supply the current to the turning-on current source transistor Q 1  and Q 2 . It will be appreciated that any real-world voltage has a finite rise time—i.e., Vip cannot instantaneously change from ground to the power supply voltage. As Vip continues to rise high, the source of Q 4  must rise from its abrupt voltage drop to limit the drain current flowing through Q 4  to the appropriate value as determined by the current source transistor Q 1 .  FIG. 4  illustrates simulation results showing the drop at the source of Q 3  as Vin falls (which corresponds to Vip rising). It will thus be seen that the abrupt pulsing change in voltage at the sources of Q 3  and Q 4  will occur at every transition of Vip (at both the rising and falling edges) as shown by the simulation results of  FIGS. 3 and 4 . 
   Advantageously, the abrupt pulsing voltage at the sources of Q 4  and Q 3  will be as brief as just tens of pico-seconds (such as, for example, 40 pico-seconds) with an amplitude of 1.5 V. Current state of the art clock generation for high-speed data transmission allows a rise and fall time of just 10 picoseconds for a 3V rail-to-rail signal. It will be appreciated that pulse width will be increased if a driving source for Vip and Vin does not offer speedy rise and fall times. In general, it is desired to minimize the rise and fall time for these driving voltages as much as possible. Although pulse generator  100  is shown with all NMOS transistors, those of ordinary skill in the art will appreciate that an analogous PMOS pulse generator may be implemented by replacing the NMOS transistors with PMOS transistors and reversing the power supply and drain nodes. 
   Thus, the voltage at the sources of Q 4  and Q 3  may be used as an extremely narrow pulse train. It may be seen that the drain voltage of Q 4  and Q 3  will also mirror their source voltages as shown by the simulation results of  FIG. 5 . Thus very narrow pulse trains may be obtained at either the drain or the sources of Q 4  and Q 3 . Pulse generator  100  shows an output voltage Vout being derived from the drain of Q 4  but it could just have readily been taken at the source. Simulation results show that achieving such narrow pulses is enhanced if Q 1  through Q 4  are relatively large transistors. For example, the length of Q 4 /Q 3  may be one micron and the width may be 100 microns. Not only do such large transistors enhance narrow pulse formation, the capacitance and other stray effects of whatever circuit that couples to the drain (or source) of Q 4  to receive the pulse train will have relatively little effect on the pulse formation. 
   Although the pulse generators discussed herein have been described with respect to particular embodiments, this description is only an example of certain applications and should not be taken as a limitation. Thus, those of ordinary skill will appreciate that alternative embodiments may be constructed according to the principles discussed above. Consequently, the scope of the claimed subject matter is set forth as follows.