Abstract:
A semiconductor transistor device comprises a gate electrode disposed over an insulating surface, a spacer element located at the end of the gate electrode, a gate insulating film covering the gate electrode, a first diffusion region spaced apart from one end of the gate electrode, separated therefrom by the gate insulating film and by the spacer element which reduces the electric field between the gate and first diffusion region, the first diffusion region extending vertically above the gate insulating film, and a second diffusion region disposed above the gate insulating film having one end spaced from the first diffusion vertically extending region.

Description:
This application is a divisional of application Ser. No. 07/936,247 filed Aug. 27, 1992. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a semiconductor device having a thin film transistor (TFT). 
     BACKGROUND OF THE INVENTION 
     One kind of MOS static RAMs uses a complete CMOS type memory cell. As shown in FIG. 2, this CMOS type memory cell comprises a flip-flop circuit having a first inverter including driver transistor Q 1  and load transistor Q 2  and a second inverter including driver transistor Q 3  and load transistor Q 4  in which an input of one inverter is connected with an output of the other inverter, and a pair of access transistors Q 5  and Q 6  for data communication with an exterior of the cell. In FIG. 2, WL denotes a word line; BL and BL&#39; denote bit lines, respectively; and V denotes a power supply voltage. 
     In recent years, frequently, the load transistors Q 2  and Q 4  in the above complete CMOS type memory cell are each formed by a p-channel thin film transistor (TFT: Thin Film Transistor). FIG. 3 shows a cross-section of the main part of the p-channel TFT serving as a load transistor. In FIG. 3, reference numeral 101 denotes an interlayer insulation film; 102 denotes a gate electrode; 103 denotes a gate insulating film; and 104 denotes a polycrystalline silicon (hereinafter referred to as polysilicon) film. It should be noted that the polysilicon film 104 is formed so as to cover an end portion of the gate electrode 102. The polysilicon film 104 includes a p +  -type source region 105 and a p +  -type drain region 106. The gate electrode 102, source region 105 and drain region 106 constitute a p-channel TFT serving as a load transistor. 
     In known CMOS type memory cell, as shown in FIG. 3, the drain region 106 of the p-channel TFT serving as a load transistor is usually formed so that its end portion is close to the end portion of the gate electrode 102. For this reason, hot carriers are generated during operation by the electric field between the end portion of the gate electrode 102 and the drain region 106, resulting in deterioration of the characteristic of the p-channel TFT as a load transistor. 
     SUMMARY OF THE INVENTION 
     An object of the present invention, therefore, is to provide a semiconductor device which can prevent generation of hot carriers due to the electric field between the end portion of the gate electrode and the drain region of the thin film transistor, thereby preventing deterioration of the characteristic of the thin film transistor. 
     In order to achieve the above purpose, in accordance with the present invention, there is provided a semiconductor device comprising a thin film transistor having a gate electrode and a semiconductor thin film formed so as to cover at least an end portion of the gate electrode through a gate insulating film. A side wall spacer is provided on a side wall of at least the end portion of said gate electrode. 
     In the semiconductor device according to a preferred embodiment of the present invention, a side wall spacer is provided on the side wall of at least the end portion of the gate electrode, and the distance between the gate electrode and a drain region formed in the semiconductor thin film is increased by the width of the side wall spacer. Thus, in operation, the electric field between the end portion and the drain region can be reduced. This prevents generation of hot carriers due to the electric field between the end portion of the gate electrode and the drain region, and prevents deterioration in the characteristic of the thin film transistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     One preferred embodiment of the present invention is described in the following with reference being made to the accompanying drawings: 
     FIG. 1 is a sectional view of a main part of a complete CMOS type static RAM according to one embodiment of the present invention; 
     FIG. 2 is circuit diagram of the equivalent circuit of a complete CMOS type memory cell; and 
     FIG. 3 is a sectional view of the p-channel TFT serving as a load transistor in the conventional CMOS type static RAM; 
     FIG. 4A illustrates the first step in a method of making the embodiment shown in FIG. 1; 
     FIG. 4B illustrates an intermediate step for forming a spacer element between the gate electrode and drain region; 
     FIG. 4C illustrates the etching step in forming the spacer element; and 
     FIG. 4D illustrates the resulting structure following etching of FIG. 4C. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Now referring to FIG. 1, and explanation will be given of an embodiment of the present invention. 
     FIG. 1 is a sectional view showing a main part of a complete CMOS type static RAM according to one embodiment of the present invention. The equivalent circuit of the memory cell of the complete CMOS type static RAM is shown in FIG. 2. 
     In FIG. 1, reference numeral 1 denotes a p-type silicon (Si) substrate; 2 denotes a gate insulating film made of silicon dioxide (SiO 2 ) film; 3 denotes a gate electrode; and WL denotes a word line. The gate electrode 3 and the word line WL can be formed of e.g. a first layer of polysilicon film or polycide film which is formed by stacking a refractory metal silicide film on the polysilicon film. 
     Reference numerals 4, 5 and 6 are n +  -type diffused layers which are used as source or drain regions. The gate electrode 3 and the diffused layers 4 and 5 constitute and n-channel MOS transistor serving as a driver transistor (e.g., Q 1  in FIG. 2.). The word line WL and the diffused layers 5 and 6 constitute and n-channel MOS transistor (e.g., Q 5  in FIG. 2) serving as an access transistor. 
     Reference numeral 7 denotes an interlayer insulating film made of e.g. silicon dioxide film or phospho-silicate glass (PSG) film, and reference numeral 8 denotes a gate electrode. This gate electrode 8 is formed by e.g. a second layer of polysilicon film or polycide film which is e.g., about 3000 Å thick. The gate electrode 8 is kept in contact with the diffused layer 5 through a contact hole C 1  formed in the interlayer insulating film 7. 
     In this embodiment, side wall spacers 9 of SiO 2  are formed on the side walls of the end portions of the gate electrode 8. These side wall spacers 9 are formed in such a way that after the gate electrode 8 if formed, an SiO 2  film is formed on the entire surface of the substrate and the SiO 2  film is etched back. The side wall spacers are e.g. about 0.2-0.3 μm wide. 
     Reference numeral 10 denotes a gate insulating film made of e.g. SiO 2  film. The gate insulating film 10 is e.g. 100-300 Å. Reference numeral 11 denotes e.g. a third layer of polysilicon film. The polysilicon film 11 is formed so as to cover an end portion of the gate electrode 8 through the gate insulating film 10. The polysilicon film 11 is e.g. 500-1000 Å. This polysilicon film 11 includes a p +  -type source diffusion region 12 and a p-type drain diffusion region 13. The gate electrode 8, the source region 12 and the drain region 13 constitute a p-channel TFT serving as a load transistor (e.g. Q 4  in FIG. 2). 
     Reference numeral 14 denotes an interlayer insulating film of e.g. a PSG film. Reference symbol BL denotes a bit line of e.g. an aluminum film. The bit line BL is kept in contact with the diffused layer 6 (which is the source region of an access transistor (e.g. Q 5  in FIG. 2) through the contact hole C 2  formed in the interlayer insulating films 7 and 14. 
     As described above, in the complete CMOS type static RAM according to the embodiment, the side wall spacer 9 is formed on the side wall of the end portion of the gate electrode 8 of the p-channel TFT serving as a load transistor so that the distance between the end portion of the gate electrode 8 and the drain region 13 is made larger by the width of the side wall spacer 9 than that of the prior art. For this reason, during operation, the electric field between the end portion of the gate electrode 8 and the drain region 13 can be reduced. This effectively prevents generation of hot carriers due to the electric field between the end portion of the gate electrode 8 and the drain region 13, thereby preventing deterioration in the characteristic of the p-channel TFT serving as a load transistor, thus improving its reliability. 
     Further, since the distance between the end portion of the gate electrode 8 and the drain region 13 is controlled by provision of the side wall spacer 9, it can be controlled very easily and with great accuracy. 
     The method of making side wall spacer 9 will be described in conjunction with FIGS. 4A to 4D. 
     As shown in FIG. 4A, a gate electrode 8 is formed on n +  -type diffusion layer 5 and insulating film 7. As shown in FIG. 4B, an insulating film 9A such as SiO 2  is deposited by CVD (Chemical Vapor Deposition) on the entire surface of a wafer at a substantially constant thickness D1 of 0.2 to 0.3 μm corresponding to that of the side wall spacer to be made. The gate electrode 8 and end portion of the gate electrode 8 are covered by the insulating film 9A. The portion of the insulating film 9A at the end portion 8B of the gate electrode 8 forms a transition region of depth D2 which is deeper than the depth D1 of the other portion of the insulation film 9A. The entire wafer surface is then subjected to anisotropic etching to etch the insulating film 9A. The etching depth is set to D1, represented by the length of arrows in FIG. 4C, and is uniform over all surfaces. After the etching, the portions of the insulating film 9B which exceeds the depth D1, i.e. D2-D1, is left at the step portions, i.e. at the transition adjacent the end portion of the gate electrode so as to form the side wall spacer 9B as shown in FIG. 4D. 
     Although only one embodiment of the present invention has been explained in detail, the present invention has been explained concretely, the present invention should not be limited to the above embodiment. 
     For example, in the above embodiment, the present invention is applied to a complete CMOS type static RAM in which the load transistor of a memory cell is constructed by a TFT. However, the present invention can also be applied to various kinds of semiconductor devices including the TFT. 
     As described above, in accordance with the present invention, since a side wall spacer is provided on the side wall of at least an end portion of the gate electrode of a thin film transistor (TFT), it is possible to prevent generation of hot carriers due to the electric field between the end portion of the gate electrode and the drain region, thereby preventing deterioration in the characteristic of the thin film transistor.