Abstract:
In a comparator including a first differential amplifier stage for amplifying the difference in potential between input signals, a second differential amplifier stage for amplifying the difference in potential between output signals of the first differential amplifier stage, and a latch stage for positively feeding output signals of the second amplifier stage back thereto, a first differential switch circuit alternately activates the second differential amplifier stage and the latch stage, and a second differential switch circuit alternately activates the first differential amplifier stage and the latch stage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a comparator having two differential amplifiers and a latch circuit, which can be applied to an analog/digital (A/D) converter. 
     2. Description of the Related Art 
     Conventionally, a comparator includes a differential amplifier and a latch circuit for latching the outputs of the differential amplifier, which, however, requires a high power consumption. 
     In order to reduce the power consumption, a first prior art comparator includes a prestage differential amplifier in front of the conventional comparator (see: M. Hotta et al., &#34;A 150-mV 8-Bit Video-Freguency A/D Converter&#34;, IEEE Journal of Solid-State Circuits, vol. SC-21, No. 2, pp. 318-323, April 1986). This will be explained later in detail. 
     In the first prior art comparator, however, the operation speed of the latch stage cannot be increased, and therefore, the operation speed of the comparator cannot be increased. 
     In order to increase the operation speed, a second prior art comparator includes emitter-follower type buffers connected to the latch stage (see: T. Wakimoto et al., &#34;Si Bipolar 2-GHz 6-bit Flash A/D Conversion LSI&#34;, IEEE Journal of Solid-State Circuits, vol. 23, No. 6, December 1988). This will be explained later in detail. 
     In the second prior art comparator, however, the operation speed of the latch stage is still low, and therefore, the operation speed of the comparator is still low. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a high speed comparator having two differential amplifier stages and a latch stage. 
     According to the present invention, in a comparator including a first differential amplifier stage for amplifying the difference in potential between input signals, a second differential amplifier stage for amplifying the difference in potential between output signals of the first differential amplifier stage, and a latch stage for positively feeding output signals of the second amplifier stage back thereto, a first differential switch circuit alternately switches the second differential amplifier stage and the latch stage, and a second differential switch circuit alternately switches the first differential amplifier stage and the latch stage. Thus, when the latch stage is activated, the two differential amplifiers can be deactivated. As a result, the operation speed of the latch stage can be increased, and therefore, the operation speed of the comparator can be increased. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram illustrating a first prior art comparator; 
     FIGS. 2A through 2D are timing diagrams for explaining the operation of the comparator of FIG. 1; 
     FIG. 3 is a circuit diagram illustrating a second prior art comparator; 
     FIG. 4 is a circuit diagram illustrating a first embodiment of the comparator according to the present invention; 
     FIGS. 5A through 5D are timing diagrams for explaining the operation of the comparator of FIG. 1; 
     FIG. 6 is a circuit diagram illustrating a second embodiment of the comparator according to the present invention; 
     FIG. 7 is a circuit diagram illustrating a third embodiment of the comparator according to the present invention; 
     FIG. 8 is a circuit diagram illustrating a fourth embodiment of the comparator according to the present invention; 
     FIG. 9 is a circuit diagram illustrating a fifth embodiment of the comparator according to the present invention; 
     FIG. 10 is a circuit diagram illustrating a sixth embodiment of the comparator according to the present invention; 
     FIG. 11 is a circuit diagram illustrating a modification of the comparator of FIG. 4; 
     FIG. 12 is a circuit diagram illustrating another modification of the comparator of FIG. 4; 
     FIG. 13 is a circuit diagram illustrating a modification of the comparator of FIG. 6; 
     FIG. 14 is a circuit diagram illustrating a modification of the comparator of FIG. 7; 
     FIG. 15 is a circuit diagram illustrating a modification of the comparator of FIG. 8; 
     FIG. 16 is a circuit diagram Illustrating a modification of the comparator of FIG. 9; and 
     FIG. 17 is a circuit diagram illustrating a modification of the comparator of FIG. 10. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiments, prior art comparators will be explained with reference to FIGS. 1 and 2. 
     In FIG. 1 which illustrates a first prior art comparator (see: the M. Hotta document), reference numeral 1 designates a first differential amplifier stage formed by two resistors R 1  and R 2  connected to a high power supply V cc  and transistors Q 1  and Q 2  having collectors connected to the resistors R 1  and R 2 , respectively. Also, emitters of the transistors Q 1  and Q 2  are connected commonly to a constant current source CS 1  having a current I 1  flowing therethrough, which source is connected to a low power supply V EE . Further, input signals V in .spsb.1 and V in .spsb.2 are supplied to bases of the transistors Q 1  and Q 2 , respectively. Thus, the first differential amplifier stage 1 with the constant current source CS 1  always amplifies the difference in potential between the input signals V in .spsb.1 and V in .spsb.2 to generate differential output signals V 1  and V 2 . 
     Also, in FIG. 1, a second differential amplifier stage 2 is formed by resistors R 3  and R 4  connected to the high power supply V cc , and transistors Q 3  and Q 4  having collectors connected to the resistors R 3  and R 4 , respectively. Also, emitters of the transistors Q 3  and Q 4  are connected via a transistor Q 7  to a constant current source CS 2  having a current I 2  flowing therethrough, which source is connected to the low power supply V EE . Further, the differential output signals V 1  and V 2  of the first differential amplifier stage 1 are supplied to the bases of the trasistors Q 3  and Q 4 , respectively. Thus, when the transistor Q 7  is turned ON, the second differential amplifier stage 2 with the constant current source CS 2  amplifies the difference in potential between the signals V 1  and V 2  to generate differential output signals V 3  and V 4 . 
     Further, in FIG. 1, a latch stage 3 is formed by the resistors R 3  and R 4 , and transistors Q 5  and Q 6  having collectors connected to the resistors R 3  and R 4 , respectively. Also, emitters of the transistors Q 5  and Q 6  are connected via a transistor Q 8  to the constant current source CS 2 . Further, the differential output signals V 3  and V 4  of the first differential amplifier stage 2 are supplied to the bases of the transistors Q 3  and Q 4 , respectively, and to the collectors of the transistors Q 4  and Q 3 , respectively. Thus, when the transistor Q 8  is turned ON, the latch stage 3 with the constant current source CS 2  amplifies the difference in potential between the signals V 3  and V 4  and feeds it back to the second differential amplifier 2. As a result, the output signals V 4  and V 3  are latched by the activated latch stage 3, and output as output signals V out .spsb.1 and V out .spsb.2, respectively, of the comparator of FIG. 1. 
     The bases of the transistors Q 7  and Q 8  are controlled by complementary control signals .o slashed. 1  and .o slashed. 2  opposite in phase to each other. Since the transistors Q 7  and Q 8  with the constant current source CS 2  activate only one of the second differential stage 2 and the latch stage 3, the transistors Q 7  and Q 8  and the constant current source CS 2  form a differential switch circuit 4. 
     The operation of the comparator of FIG. 1 is shown in FIGS. 2A, 2B, 2C and 2D. 
     Assume that the difference in potential between the input signals V in .spsb.1 and V in .spsb.2 is changed as shown in FIG. 2A, and the control signals .o slashed. 1  and .o slashed. 2  are changed as shown in FIGS. 2B and 2C. 
     When the control signals .o slashed. 1  and .o slashed. 2  are high and low, respectively, the transistors Q 7  and Q 8  are turned ON and OFF, respectively, so that the second differential stage 2 is activated by the constant current source CS 1  and the latch stage 3 is deactivated. Therefore, the control is in a sampling mode, i.e., in a comparison mode. As a result, as shown in FIG. 2D, the differential output signals V 1  and V 2  of the first differential amplifier stage 1 are amplified by the second differential amplifier stage 2. 
     Next, when the control signals .o slashed. 1  and .o slashed. 2  are low and high, respectively, the transistors Q 7  and Q 8  are turned OFF and ON, respectively, so that the latch stage 3 is activated by the constant current source CS 2  and the second differential amplifier stage 2 is deactivated. Therefore, the control is in a latch mode. As a result, as shown in FIG. 2D, the output signal V out .spsb.1 is determined whether or not the difference (V in .spsb.1 -V in .spsb.2) is positive. 
     In order to reduce the power consumption, the current I 2  of the constant current source CS 2  is preferably as small as possible. In this case, a time t1 required for the determination of the output signal V out .spsb.1 is so large that the frequency of the control signals .o slashed. 1  and .o slashed. 2  cannot be increased, i.e., the operation speed of the comparator cannot be increased. 
     In FIG. 3, which illustrates a second prior art comparator (see: the T. Wakimoto document), an emitter-follower type buffer 5 is interposed between the second differential amplifier stage 2 and the latch stage 3. That is, the buffer 5 is formed by an emitter follower Q 9 , a constant current source CS 3  having a current I 3  flowing therethrough, an emitter follower Q 10  and a constant current source CS 4  having a current I 4  flowing therethrough. In more detail, the emitter follower Q 9  has a collector connected to the high power supply V cc , a base connected to the resistor R 3 , and an emitter connected to the constant current source CS 3 . Similarly, the emitter follower Q 10  has a collector connected to the high power supply V cc , a base connected to the resistor R 4 , and an emitter connected to the constant current source CS 4 . As a result, the collector-emitter voltage of each of the transistors Q 5  and Q 6  is increased by the base-emitter voltage of each of the emitter followers Q 10  and Q 9 , respectively. Thus, a time required for a latch operation can be reduced; however, the speed of latch operation is still low. Note that emitter voltages of the emitter followers Q 9  and Q 10  can be used as output signals V&#39; out .spsb.1 and V&#39; out .spsb.2. 
     In FIG. 4, which illustrates a first embodiment of the present invention transistors Q 11  and Q 12  are added to the elements of FIG. 1. That is, the transistor Q 11 , which is controlled by the control signal .o slashed. 1 , is interposed between the first differential amplifier stage 1 and the constant current source CS 1 , and the transistor Q 12 , which is controlled by the control signal .o slashed. 2 , is interposed between the latch stage 3 and the constant current source CS 1 . Since the transistors Q 11  and Q 12  with the constant current source CS 1  activate only one of the first differential amplifier stage 1 and the latch stage 3, the transistors Q 11  and Q 12  and the constant current source CS 1  form a differential switch circuit 6. 
     The operation of the comparator of FIG. 4 is shown in FIGS. 5A, 5B, 5C and 5D. 
     Also, in this case, assume that the difference in potential between the input signals V in .spsb.1 and V in .spsb.2 is changed as shown in FIG. 5A, and the control signals .o slashed. 1  and .o slashed. 2  are changed as shown in FIGS. 5B and 5C. 
     When the control signals .o slashed. 1  and .o slashed. 2  are high and low, respectively, the transistors Q 7  and Q 11  are turned ON and the transistors Q 8  and Q 12  are turned OFF, respectively, so that the second differential stage 2 is activated by the constant current source CS 1  and the latch stage 3 is deactivated, in the same way as in the prior art comparator of FIG. 1 (see FIGS. 2A through 2D). Therefore, the control is in a sampling mode, i.e., in a comparison mode. As a result, as shown in FIG. 5D, the differential output signals V 1  and V 2  of the first differential amplifier stage 1 are amplified by the second differential amplifier stage 2. 
     Next, when the control signals .o slashed. 1  and .o slashed. 2  are low and high, respectively, the transistors Q 7  and Q 11  are turned OFF and the transistors Q 8  and Q 12  are turned ON, so that the latch stage 3 is activated by the constant current sources CS 1  and CS 2 , and the differential amplifier stages 1 and 2 are deactivated. Therefore, the control is in a latch mode. As a result, as shown in FIG. 5D, the output signal V out .spsb.1 is determined whether or not the difference (V in .spsb.1 -V in .spsb.2) is positive. 
     Thus, in the first embodiment as illustrated in FIG. 4, the latch stage 3 is activated by the two constant current sources CS 1  and CS 2 , in other words, a current flowing through the latch stage 3 is I 1  +I 2 . Therefore, a time t2 required for the determination of the output signal V out .spsb.1 is 
     
         t2≈t1·I.sub.1 /(I.sub.1 +I.sub.2) 
    
     If I 1  =I 2 , then 
     
         t2≈t1/2 
    
     Therefore, since the operation speed of the latch stage 3 can be increased, it is possible to increase the frequency of the control signals .o slashed. 1  and .o slashed. 2 , to increase the operation speed of the comparator of FIG. 4. 
     In FIG. 6, which illustrates a second embodiment of the present invention, the buffer 5 formed by the emitter followers Q 9  and Q 10  and the constant current sources IS 3  and IS 4  of FIG. 3 is added to the elements of FIG. 4. As a result, the collector-emitter voltage of each of the transistors Q 5  and Q 8  is increased by the base-emitter voltage of each of the emitter followers Q 10  and Q 9 , respectively. Thus, the time t2 required for a latch operation can be further reduced. 
     In FIG. 7, which illustrates a third embodiment of the present invention, the constant current sources CS 1  and CS 2  are replaced with a constant current source CS 5  having a current (I 1  +I 2 ) flowing therethrough. In this case, the differential switch circuit 4 is formed by the transistors Q 7  and Q 8  and the constant current source CS 5 , and the differential switch circuit 6 is formed by the transistors Q 11  and Q 12  and the constant current source CS 5 . Thus, the comparator of FIG. 7 can be reduced in size as compared with the comparator of FIG. 4. 
     In FIG. 8, which illustrates a fourth embodiment of the present invention, the transistors Q 8  and Q 12  of FIG. 7 are replaced with a transistor Q 13 . Thus, the comparator of FIG. 8 can be reduced in size as compared with the comparator of FIG. 7. 
     In FIG. 9, which illustrates a fifth embodiment of the present invention, the comparator of FIG. 6 is combined with that of FIG. 7. Thus, the comparator of FIG. 9 can be reduced in size as compared with the comparator of FIG. 6. 
     In FIG. 10, which illustrates a sixth embodiment of the present invention, the comparator of FIG. 6 is combined with that of FIG. 8. Thus, the comparator of FIG. 10 can be reduced in size as compared with the comparator of FIG. 9. 
     Although the transistors in the first to sixth embodiments are of an NPN type, the transistors can be of a PNP type. For example, the comparator of FIG. 4 can be modified into a comparator as illustrated in FIG. 11. 
     Further, although the transistors in the first to sixth embodiments are of a bipolar type, the transistors can be of a MOS type. That is, the comparators of FIG. 4, 6, 7, 8, 9 and 10 can be modified into comparators of FIGS. 12, 13, 14, 15, 16 and 17, respectively, where all transistors are of an N channel MOS type. 
     As explained hereinbefore, according to the present invention, since the operation speed of the latch stage can be increased, the operation speed of the comparator can be increased.