Abstract:
A selecting machine of the type commonly used for addressing mailed material from individual data-bearing cards, using tri-level logical comparator circuitry to compare the individual cards against an interchangeable master card. Both the individual and the master cards are perforated in files of holes longitudinal to the direction in which they are synchronously moved by the machine, the files of perforations being sensed by phototransistors connected in turn to the logic circuitry. For each potentially perforable site on the individual card, there are two corresponding locations on the master card, one of which when matched by a perforation on the individual card indicates nominal selection of the individual card, the other of which indicates positive rejection of the individual card, overriding any nominal selection, with rejection by default occurring if neither location on the master is perforated to correspond with a perforation at the equivalent site on the individual card. Synchronization pulses for gating the logic circuitry in the examination process are derived from a completely perforate file on the master card.

Description:
This application is related to application Ser. No. 364,010, filed May 25, 1973, now U.S. Pat. No. 3,817,171, the disclosure of which is hereby incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     This invention relates to a TRI-LEVEL SELECTOR and more particularly to a device for selecting desired individual information-bearing media from a group of such media scanned by the device. 
     Devices of the present type are often used for such purposes as addressing mailed material, as more fully disclosed in the above-cited co-pending application. A typical machine of this type operates on a stack of embossed or ink-transferring individual cards, selecting certain ones of the cards to be imprinted against a receiving medium, typically an envelope, in accordance with selection criteria programmed into the machine by various means, including cams and linkages such as found in calculating machines, or electric plugboards. 
     The problems with many prior art devices in this field are discussed in greater detail in the above-cited application, but the present application is directed to the problems encountered by the use of only a single exclusionary mode in the operation of prior machines. For example, in the prior art machines, a complete reprogramming of the selection criteria would be required in order to positively exclude a single narrow class of cards from selection. This need might arise from the use of the cards to address a mailing, where it was desired to exclude from the mailing those persons receiving a previous, small mailing, as well as those excluded by other characteristics from both mailings. 
     SUMMARY OF THE INVENTION 
     The apparatus of the present invention simultaneously scans a perforated master card and a perforated individual data card, photoelectrically sensing the patterns of perforations and comparing the patterns in a tri-level logic circuit. The logic circuit is capable of exercising two distinct modes of exclusion, as well as a single inclusion mode. 
     The provision of two exclusionary modes, one operating by default and one by specific indication, allows much greater flexibility in the programming and use of the machine. For example, certain members of a mailing list may receive an advance mailing of particular marerial, with certain other members to receive another mailing, from which the first group are excluded, with the balance of the list excluded from both mailings. In this example, the first group can be programmed through tri-level logic to be included in the first mailing and specifically excluded from the second, with a third group falling into the default exclusion mode from both mailings. 
     A further programming simplification results when the master card is made longitudinally symmetric in the position of its data fields indicating inclusion and positive exclusion. With such symmetry, nominal inclusion, or &#34;acceptance,&#34; can be changed to positive exclusion by a simple inversion of the master card. In the example given above. the operator would merely have to turn over the master card to change the machine from the first mailing to the second mailing. 
     Accordingly, it is a principal object of the present invention to provide a selector device of the character described which simplifies the programming of a specifically excluded class of cards while retaining a generally excluded class. 
     A further principal object of the present invention is to provide a device of the character described which performs a highly sophisticated discrimination among the individual cards with a minimum of both mechanical complexity and electronic memory capacity. 
     Yet another object of the present invention is to provide a device of the character described having a rapid changeover from specific exclusion to nominal inclusion and vice versa. 
     A still further object of the present invention is to provide a device of the character described having ready interchangeability of the master means which specifies the selection criteria. 
     Another object of the present invention is to provide a device of the character described which synchronously scans the master and individual media for comparison. 
     Further objects and advantages of the invention will become apparent as the specification progresses, and the new and useful features of the tri-level selector will be more fully defined in the claims attached hereto. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The preferred forms of the present invention are illustrated in the accompanying drawings forming part of this specification, in which: 
     FIG. 1 is a schematic diagram of the tri-level selector of the present invention; 
     FIG. 2 is a plan view on an enlarged scale of the individual and master media of the present invention; 
     FIG. 3 is a schematic diagram of the logic circuitry of the selector; and 
     FIG. 4 is a fragmentary schematic diagram of an alternate form of a portion of the logic circuitry. 
     While only the preferred forms of the present invention have been shown here, it should be appreciated that various changes or modifications may be made within the scope of the claims attached hereto without departing from the spirit of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the drawings in detail, it will be seen that the selection device 11 of the present invention selects among a plurality of individual information-bearing media 12 which are moved in synchronism with a master indicia-bearing medium 13 through a scanning station generally indicated at 14 by a transport means schematically indicated at 16. The transport means may be any appropriate to provide the jointly synchronous, substantially continuous motion of the two media 12 and 13 for the simultaneous scanning and any other desired operations. Two examples of suitable transport means, a rotating drum and a conveyor belt, are shown in the above-cited co-pending application and incorporated herein by reference. 
     The individual medium 12 and the master medium 13 each bear a pattern of perforate and imperforate areas, shown in more detail in FIG. 2. The perforations of the individual medium 12 bear data relevant to the information imprintable from that medium, and those of the master medium 13 specify the characteristics of the individual media 12 to be selected or rejected for further operation by the machine, such as imprinting. The perforations and the imperforate areas are located in a rectangular grid of potentially perforable points on the media 12 and 13, with a pair of points on the master medium 13 corresponding to each point on the individual medium 12. 
     The points on the master medium 13 are organized into two fields, an &#34;accept&#34; field 22 and a &#34;reject&#34; field 23. The points in the &#34;accept&#34; field 22 correspond to nominally desired selection of the individual medium having a corresponding perforation in its &#34;identity&#34; field 24, and those in the &#34;reject&#34; field 23 correspond to positive rejection of an individual medium 12 having a matching perforation in its identity field 24. The rectangular grids on both media 12 and 13 are oriented with one axis parallel to the direction of longitudinal motion of the media past the scanning means 17, so that it may be said that the perforate and imperforate areas in each field form files parallel to the direction of motion of the media. 
     The scanning of the media 12 and 13 at the scanning station 14 is done by a scanning means generally indicated at 17, adjacent the scanning station 14. The scanning means 17 is responsive to the characteristics of the individual medium 12 as compared simultaneously with the master medium 13 to detect the individual media 12 appropriate for selection and issue a &#34;select&#34; signal upon such detection. The scanning means 17 includes a light source 18, which may be one or more small incandescent lamps, a plurality of photosensitive devices, schematically indicated at 19 positioned to sense light from the light source 18 passing through the perforate areas of the media 12 and 13, and a logical comparator circuit, schematically indicated at 21 and shown in more detail in FIG. 3. 
     The logical comparator circuit 21 receives signals from the detection means, the photosensitive devices 19, and compares the signals from the individual medium 12 with those from the master medium 13 to determine whether the individual medium 12 is to be included in the selected class, positively excluded from that class, or excluded by default. The logical comparator circuit 21 may thus be seen to operate on three levels, or in three states. The first state is that calling for selection of the individual meduim 12, and is produced by correspondence of a perforation on the individual medium with one at the corresponding location in the &#34;accept&#34; field 22 on the master medium 13. 
     The second state is that calling for positive rejection of the individual meduim 12, and is produced by correspondence of a perforation on the individual medium with one at the corresponding location in the &#34;reject&#34; field 23 on the master medium. The third, or rejection by default, stage is produced by lack of correspondence of a perforation in either of the fields 22 or 23 on the master medium with a perforation at the equivalent location on the individual medium 12. These three levels or states converge to two states, &#34;select&#34; and &#34;do not select&#34; in the output stages of the comparator circuit 21. 
     As here shown, the second state is given logical priority over the first, and the first logical priority over the third by the arrangement of the logical comparator circuitry shown in FIG. 3. This arrangement of priorities allows positive exclusion to take precedence over nominal inclusion, which in turn takes precedence over default exclusion. While the appropriate changes in the logic circuitry could be made to alter those relative priorities, the present order has been found to be the most useful for applicant&#39;s purposes. Whatever the order of priority, the flexibility of programming is greatly enhanced by the availability of three levels of choice. 
     The photosensitive devices 19 include first, second and third photosensitive devices, indicated at 26, 27 and 28, respectively in FIG. 3. As shown in this diagram, the photosensitive devices are phototransistors, but it should be appreciated that a number of other devices are also suitable, with the appropriate changes in associated circuitry well understood in the art, such as photodiodes, photoresistive and photovoltaic cells, photo-SCRs, etc. The logical comparator circuit 21 receives the outputs of each of the photosensitive devices 26, 27 and 28, with each output being inverted by an inverter 29. 
     The phototransistor 26 is positioned so that it observes one of the longitudinal files in the &#34;accept&#34; field 22 on the master medium 13, and the phototransistor 27 is similarly positioned to observe the corresponding file in the &#34;reject&#34; field 23. The phototransistor 28 observes the file of perforations and potentially perforable areas in the &#34;identity&#34; field 24 on the individual medium 12 which corresponds to the &#34;accept&#34; and &#34;reject&#34; files read by the phototransistors 26 and 27. Only one such triplet of phototransistors 26, 27 and 28 is illustrated in FIG. 3, but as many such triplets are provided as these are longitudinal files to be observed in any one of the three fields 22, 23 and 24. 
     The inverted outputs of the phototransistors 26, 27 and 28 are fed to a first logic circuit 30 which includes NAND units 31 and 32, with the NAND 31 receiving the inverted outputs of phototransistors 26 and 28 and the NAND 32 receiving the inverted outputs of phototransistors 27 and 28. The output of the NAND 31 will therefore be a logical 0 if holes are detected by both phototransistors 26 and 28, and a logical 1 if a hole is detected by one and not the other, or by neither. The logical 0 output of the NAND 31 corresponds to nominal acceptance of the individual medium 12 (so far as that particular datum is concerned), and the logical 1 at this point corresponds to default rejection, so far as the particular datum is concerned. 
     The output of the NAND 32 will be a logical 0 if holes are detected by both phototransistors 27 and 28, and a logical 1 if a hole is detected by one and not the other, or no holes by either. The logical 0 output of the NAND 32 corresponds to positive rejection of the individual medium 12, despite any nominal acceptance indicated by any other datum. The logical 1 output from the NAND 32 corresponds to the lack of positive rejection by the particular datum concerned, leaving the fate of the individual medium 12 to determination by the accept or default rejection modes, or positive rejection based on other perforations at other locations on the master medium 13. 
     As noted above, a plurality of triplets of photosensitive devices 26, 27 and 28 may be provided to observe a plurality of longitudinal files of perforations in the &#34;identity&#34; field 24 on the individual medium 12, and the corresponding pairs of files in the accept and reject fields 22 and 23 on the master medium 13. Each of the triplets of phototransistors is connected to a pair of NANDs 31 and 32, and these NANDs are of the open-collector output type, so that the outputs of the NANDs 31 can be connected together to perform a &#34;wire-OR&#34; function, as schematically indicated at 33. The total output of all the NANDs 31 will thus be a logical 0 if any of the outputs of the individual NANDs 31 is a logical 0, yielding nominal acceptance of the individual medium 12 if acceptance is indicated by a matching of perforations between any one of the files in the &#34;accept&#34; field 22 and the corresponding file of the &#34;identity&#34; field 24 on the individual medium 12. The line 36 from the bottom of the wire-OR symbol 33 indicates a connection to the output of each of the NANDs 31. 
     Similarly, the outputs of the NANDs 32 are connected together to perform a &#34;wire-OR&#34; function schematically indicated at 34, making their joint output a logical 0 if any of the outputs are a logical 0. In other words, light activation of the second photosensitive device 27 in any of the plurality of triplets or groups 38, with light activation of the third photosensitive device 28 in the same group or triplet, will produce an output signifying positive rejection on line 39. Likewise, the activation of the second photosensitive device 27 in any of the groups or triplets 38, with activation of the first photosensitive device 26 in the same group will produce an output signifying nominal acceptance on line 41 from the wire-OR combination of outputs from all of the NANDs 31. 
     The priority of the positive rejection determination over nominal acceptance, and of nominal acceptance over default rejection, is governed by a second logic circuit generally indicated at 44, which includes two memory circuits formed by AND-ing type J-K flip-flops 42 and 43, and a NAND logic unit 46. The J* (inverted) and K 1  inputs of the flip-flops 42 and 43 receive their signals from the lines 41 and 39, respectively, and the NAND 46 receives as one input the Q output of the flip-flop 42 and as its other input the Q output of the flip-flop 43. The Q outputs of both flip-flops 42 and 43 are fed back to their respective J 2  and K 2  inputs to lock the flip-flops in their set state despite changes in the signals on lines 41 and 39. 
     Since the logical 0 signal on line 41 is the &#34;accept&#34; signal and the logical 0 signal on line 39 is the &#34;positive reject&#34; signals, the memory circuit represented by the J-K flip-flop 42 will set and remain set upon receipt of an &#34;accept&#34; signal, and the memory circuit represented by the J-K flip-flop 43 will set and remain set upon receipt of a &#34;positive reject&#34; signals. As the NAND gate 46 receives the Q output of flip-flop 42 and the Q output of the flip-flop 43, it will produce its &#34;accept&#34; output, here a logical 0 signal, only when flip-flop 42 is set (logical 1 output on line 47) and flip-flop 43 is not set (logical 1 output on line 48). The connection of the Q and Q outputs of the flip-flops 42 and 43 respectively to the NAND gate 46 thus enforces the priority of the &#34;positive reject&#34; determination over the &#34;nominal accept&#34; determination. 
     As may be seen from FIG. 2, the master indicia-bearing medium 13 has an additional logitudinal file of perforations 49, with one perforation aligned with and corresponding to each one of the transverse rows of potentially perforable areas in the master medium 13. A fourth photosensitive device 51 is positioned to observe passage of light through the perforations of the file 49, and may be located with the other photosensitive devices in the block generally indicated at 19. The phototransistor 51 generates synchronization pulses in response to the passage of light through the perforations of the file 49, and the pulses (negative for each perforation) are then inverted by an inverter 52. 
     After inversion by the inverter 52, the synchronization pulses are delayed by a &#34;one-shot&#34; delay unit 53 which acts as a noise filter and allows time for all of the perforations to be centered over their respective photosensitive devices before &#34;reading&#34; takes place. The pulses are received at the B, or Schmitt trigger on positive-going edge, input of the unit 53, and the Q output of the unit 53 is communicated to the A input (negative-going edge) of a &#34;one-shot&#34; unit 54 to provide further noise elimination and pulse shaping. The Q output of the one-shot unit 54 is communicated to one input of a NAND gate 56. The timing of the delay unit 53 is selected in accordance with the speed of the transport means 16, and in the present instance 0.7 millisecond has been found satisfactory. The one-shot 54 delays the signal an additional 0.1 millisecond. 
     A fifth photosensitive device 57 is positioned to observe an entirely imperforate area of the individual information-bearing medium 12, that is, an area outside the identity field 24, and generate a &#34;card present&#34; signal when light is blocked from the phototransistor 57 by the presence of one of the individual cards or information-bearing media 12. The fifth photosensitive device 57 may also be included within the block 19 at the scanning station 14, adjacent the third photosensitive devices 28. The &#34;card present&#34; signal is inverted by an inverter 58 and inverted again by a NAND gate 59 having its inputs tied together. The output of the NAND gate 59 is communicated to the remaining input of the NAND gate 56, where it serves to gate through the synchronization pulses from the pulse unit 54 so long as one of the individual media is seen by the phototransistor 57. 
     In the absence of an individual medium 12 at the scanning station 14, the lack of the logical 1 &#34;card present&#34; signal from the NAND gate 59 at one input of the NAND gate 56 will block the synchronization pulses from passing through the NAND gate 56. When both a synchronization pulse and a card present signal are furnished to the NAND gate 56, its output becomes a logical 0, and this signal is communicated to the B input of a one-shot unit 61, which acts as a filter and pulse shaper, with a pulse length of 0.1 millisecond. The Q output of the pulse unit 61, representing the confluence of the synchronization pulses with the card present signal, is communicated to the clock inputs (not shown) of the J-K flip-flops 42 and 43. The clocking of the flip-flops 42 and 43 by the synchronization pulses ensures that the flip-flops are receptive to data only at the point when all perforations and potentially perforable areas are correctly aligned with the phototransistors which read them. 
     In the form of the invention shown in FIG. 3, a memory circuit, formed by a D-type flip-flop 62, receives the output of the NAND gate 46, to hold that result until the individual medium 12 travels through the machine from the scanning station 14 to another operational station, such as imprinting or segregation. This memory is needed where the scanning station 14 is removed from that operational station, as another medium 12 may be being scanned by the scanning means 14 when the first medium 12 reaches the operational station. The clock signal which gates the output of the NAND gate 46 into the flip-flop 62 is derived from the output of the NAND gate 59, the card present signal. 
     As a new individual medium 12 moves into the view of the phototransistor 57, the cutoff of light from that phototransistor produces a positive-going signal which is supplied through the inverters 58 and 59 to the B input (Schmitt trigger on positive-going edge) of a filter &#34;one-shot&#34; unit 63, whose output rejects further transitions on its B input for 200 milliseconds to ensure that only a single pulse is produced by the unit 64 for the leading edge of each card. The Q output of the unit 63 is supplied to a one-shot unit 64, which then supplies a 0.01 millisecond pulse to the clock input (not shown) of the flip-flop 62. The decision on the previous individual medium 12 is thus gated into the memory unit 62 just as a new card 12 has begun to be scanned. The Q output of the one-shot unit 64 is communicated to the clear inputs (not shown) of the J-K flip-flops 42 and 43, so that their state resulting from the examination of the previous card 12 is cleared as the examination of a new card 12 begins. 
     The Q output of the D-type flip-flop 62 is communicated to a relay driver unit 67, which is turn operates equipment producing the desired physical action by the machine, such as a solenoid governing an imprinting mechanism, as shown in the above-cited application. A momentary normally-open switch 66 is operated by the insertion of a new tray of individual media 12 to produce a negative-going pulse which is communicated to the clear inputs (not shown) of the D-type flip-flops 62 to clear them from the state determined by the last card (or cards) 12 of any previous tray. 
     One D-type flip-flop 62 is shown here, but it should be appreciated that as many such flip-flops may be provided in series as there are cards 12 moving between the scanning station 14 and the operation station at which the select signal will have physical significance. For example, if one card is at the scanning station 14, one between that station and the operation station, and one card 12 at the operation station, two D-type flip-flop memory units should be provided, one to remember the &#34;accept&#34;/&#34;reject&#34; status of the card 12 lying between the stations, and the other memory unit 62, downstream of the first, to remember the &#34;accept&#34;/ &#34;reject&#34; status of the card 12 at the operation station. All of the D-type flip-flops would be clocked and cleared together by the clock and clear signals for the one D-type flip-flop 62 shown. 
     In applications where no memory unit 62 is needed, as in machines having the operation station immediately adjacent the scanning station 14, or no physical operation on the card 12 is required, as in counting, the alternate output circuit shown in FIG. 4 may be used. In this circuit, a negated-input OR-gate 68 receives the output of the NAND gate 46 and functions itself as a NAND gate, gating a logical 0 level &#34;accept&#34; signal from the NAND gate 46 through when its other input is supplied with a logical 0 level signal from the output of an inverter 69 in response to the logical 1 level card present signal from the output of the NAND gate 59. The &#34;accept&#34;/&#34;reject&#34; determination for the card 12 will thus not be gated through from the NAND gate 46 to the driver unit 67 by the gate 68 until the card 12 leaves the scanning station 14. 
     As may be seen from FIG. 2, the corresponding files in the accept field 22 and the reject field 23 of the master medium 13 may be arranged to lie symmetrically on either side of the central row of timing perforations 49, in other words, with accept and reject files which correspond lying equidistant from the longitudinal centerline of the master card 13. If the master card 13 is then inverted about the centerline, the accept field 22 will be interchanged with the reject field 23, and the operator of the machine may make a quick and reliable change from acceptance of a particular group of individual media 12 to rejection of that group or vice versa by simply flipping over the master medium 13 and reinserting it into the machine. 
     The numbers appearing in the center of the logic symbols (except for the relay driver 67) represent the final digits of the standardized part numbers for TTL logic units, and are preceded by a prefix 74 so that a NAND gate 01 becomes 7401. The relay driver 67 belongs to a different series of parts, and its National Semiconductor Co. part number is NH 006C. While the circuit has been shown with positive logic and TTL logic units, it should be appreciated that it likewise be constructed with negative logic, or using diode, DTL, RTL, or MOS-type logic units. 
     From the foregoing, it may be seen that a tri-level selector device has been provided which allows simplified programming of a specifically excluded class, together with a generally excluded class, and rapid changeover from inclusion to specific exclusion. The selector is capable of complex discrimination among individual cards without requiring either mechanical or electronic complexity. The master and individual media are synchronously scanned for simultaneous comparison, and the master medium which sets selection criteria is readily interchangeable.