Abstract:
Problem to Be Solved 
     It is to evaluate whether or not various types of devices can achieve the required performances. 
     Means to Solve the Problem 
     An evaluation device  20  comprises a circuit element comprising respective pairs of inputs and outputs including several capacitances  25   a - 25   c  and resistances  26   a - 26   d , one end of each being connected to both ends of the capacitances  25   a - 25   c , wherein a resistance value of a signal input side is generally equal to that of a signal output side. The evaluation device  20  is further provided with a connecting terminal with an output device  10  for outputting signals to a device to be evaluated  30  on the signal input side, and is provided with a connecting terminal with the device to be evaluated  30  on the signal output side.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to an evaluation device and an evaluation system, more particularly, an evaluation device and an evaluation system for evaluating whether or not a transmitting device and a receiving device can communicate with each other. 
       BACKGROUND OF THE INVENTION 
       [0002]    Japanese Patent Laid-open No. 2001-505014 discloses a measuring device for the interface of a transmission link with full duplex transmission in a two-wire common frequency operation, wherein an interface module is on the one hand connected to said interface via a hybrid circuit and a transformer, and a line termination or a network termination is connected thereto as a test object on the other hand, said measuring device including a means for evaluating the arrangement of the hybrid circuit, the transformer and the line or the network termination, the input of said means being connected to transmission outputs of the interface module via a high-impedance differential amplifier and the output thereof being connected to an input of a subtracter via a further high-impedance differential amplifier, a further input of the subtracter being connected to the interface via an additional high-impedance differential amplifier, the output of the subtracter communicates with a measuring system, a differentiator followed by a comparator being connected to the output of the subtracter, and a jitter measuring device as the measuring system being post-connected to the comparator. 
       DISCLOSURE OF THE INVENTION 
     Problem to be Solved by the Invention 
       [0003]    However, the measuring device disclosed in Japanese Patent Laid-open No. 2001-505014 may evaluate the interface of a transmission link with full duplex transmission, but cannot evaluate whether or not a transmitting device and a receiving device can communicate with each other. 
         [0004]    Since various types of communication devices exist in a transmitting device and a receiving device, and furthermore various kinds of communication protocols exist in each communication device, it is important to evaluate whether or not a transmitting device and the receiving device can communicate to each other. 
         [0005]    In addition, the measuring device disclosed by Japanese Patent Laid-open No. 2001-505014 cannot evaluate whether or not a device without communication facility can realize the required performances. 
         [0006]    Thus, it is an object of the present invention to evaluate whether or not various kinds of devices can realize the required performances. 
       Means to Solve the Problems 
       [0007]    To solve the above problem, an evaluation device or an evaluation system of the present invention comprises: 
         [0008]    a circuit element comprising respective pairs of inputs and outputs including respectively several capacitances and resistances respective one end of which is connected to either end of the capacitances, wherein a resistance value of a signal input side is almost equal to that of a signal output side; 
         [0009]    a connecting terminal with an output device for outputting signals to a device to be evaluated; and 
         [0010]    a connecting terminal with the device to be evaluated on the signal output side. 
         [0011]    In addition, the evaluation device or the evaluation system of the present invention comprises: 
         [0012]    a first amplifier whose output is connected to one pair of the circuit element; and 
         [0013]    a second amplifier whose input is connected to one pair of the circuit element or a further circuit element, wherein the device to be evaluated is connected to the other pair of the circuit element, and an output device for outputting signals to the device to be evaluated is connected to the first and second amplifiers. 
         [0014]    Here, capacitances of different capacitance values may be used, or variable capacitances may be used. In addition, it should be noted that the scope of the invention includes the case where a capacitance value is zero, that is, there is no capacitance. Resistances may be placed upstream of the capacitances, may be placed downstream of the capacitances, or further may be placed both upstream and downstream of the capacitances. 
         [0015]    The first amplifier achieves one input and two outputs. The second amplifier achieves two inputs and one output. In addition, in the case where each amplifier has two inputs, when either of the inputs is connected to ground or a constant potential, connections to those potentials are also included in the inputs. This is also the case for the output side. When the inputs of the second amplifier are connected to one pair of the circuit element, the evaluation device may be suitably used for one where the so-called full duplex communication can be used. On the other hand, when the inputs of the second amplifier are connected to one pair of the further circuit element, the evaluation device may be suitably used for one where so-called half-duplex communication can be used. 
         [0016]    The device to be evaluated itself may be a communication device or a device without communication facility. In case of the latter, it is possible to evaluate whether or not the device to be evaluated responds to signals or power from the output device, and further whether or not the response is enough even if the device responds to them. In an example wherein the device to be evaluated itself is a device without communication facility, an output device is a generator and a device to be evaluated is a motor. In this case, it is possible to evaluate whether or not the shaft of the motor has been well rotated by the output power from the generator. 
         [0017]    Between each amplifier and the circuit element, a magnetic coupling member such as a pulse transformer or a capacitive coupling member such as a capacitor may be provided. In addition, the circuit element may include a load circuit composed of resistive elements or the like. 
         [0018]    In addition, the evaluation system of the present invention is provided with the above evaluation device and the output device connected to the evaluation device for outputting signals to the device to be evaluated. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    Now, the evaluation device and the evaluation system of the present invention will be described with reference to the drawings. 
       Embodiment 1 
       [0020]      FIG. 1  is a circuit diagram showing a schematic configuration of an evaluation system of the embodiment 1 of the present invention. An evaluation system shown in  FIG. 1  is classified roughly into an output device  10 , an evaluation device  20  and a device to be evaluated  30 , which will be described below. 
         [0021]    The output device  10  outputs signals or power to the device to be evaluated  30 . Typically, the output device  10  can be a communication device. This communication device includes, for example, a device for outputting signals corresponding to a command packet to the device to be evaluated  30 , and then for inputting signals corresponding to a response packet from the device to be evaluated  30  during the required receiving period. 
         [0022]    In addition, this kind of communication device may be a device to be evaluated  30 , and an output device may be a communication device corresponding to said communication device. In fact, both the output device  10  and the device to be evaluated  30  may be able to communicate both the signal corresponding to a command packet and the signal corresponding to a response packet against a communication device in the other side party. 
         [0023]    The evaluation device  20  is provided with a circuit element  24  including a first amplifier  21 , a second amplifier  22 , capacitive elements  25   a - 25   c  and resistive elements  26   a - 26   d , which will be described below. 
         [0024]    The first amplifier  21  is a differential amplifier. In the first amplifier  21 , a waveform input terminal  21   a  is connected to a TXD output terminal  11  of the output device  10 , an input enable terminal  21   b  is connected to the TXE output terminal  12 , a positive output terminal  21   c  is connected to the resistive element  26   a , and a negative output terminal  21   d  is connected to the resistive element  26   b . The TXD output terminal  11  is a terminal for outputting signals corresponding to a command packet, and the TXE output terminal  12  is a terminal for outputting signals to show the presence or absence of the output from the TXD output terminal  11 . 
         [0025]    The second amplifier  22  is a differential amplifier. In the second amplifier  22 , the positive input terminal  22   a  is connected to the resistive element  26   a , the negative input terminal  22   b  is connected to the resistive element  26   b , and the output terminal  22   c  is connected to the input terminal  13  of the output device  10 . 
         [0026]    In addition, the first amplifier  21  or the second amplifier  22  is not needed to be implemented in the evaluation device  20 , and may be implemented, for example in the output device  10 . Further, the second amplifier  22  may be selectively implemented according to the output form of the device to be evaluated  30 . 
         [0027]    For example, if the output device  10  is a motor driver, the device to be evaluated  30  is a motor, the output is power, and the second amplifier  22  can be omitted. Typically, the first amplifier  21  realizes one input and two outputs, and the second amplifier  22  realizes two inputs and one output. 
         [0028]    The present invention was explained referring to one example where the output device  10  is a motor driver and the device to be evaluated  30  is a motor, but it is not limited to this example, as long as it should be evaluated whether or not the device to be evaluated  30  responds to the signals or power from the output device  10  (whether or not the power arrived to the device to be evaluated  30  is equal to or more than the given value). That is, in case of a generator or a battery being an output device  10 , by the output from this it is also possible to evaluate whether or not the power necessary for turning on a lamp as a device to be evaluated  30  in required illuminance is supplied. 
         [0029]    Three capacitive elements  25   a - 25   c  are shown as an example in  FIG. 1 . They have different capacitance values each other. In an example, the capacitance value of the capacitive element  25   a  is 0.0001-0.1 μF, the capacitance value of the capacitive element  25   b  is 0.0002-0.2 μF, and the capacitance value of the capacitive element  25   c  is 0.0004-0.4 μF. For the capacitance value, if transmission speed is relatively low, the capacitive element  25   c  is selected, and if it is fast, the capacitive element  25   a  is selected, and if it is middle, the capacitive element  25   b  is selected. 
         [0030]    Thus, by providing capacitive elements  25   a - 25   c  with various capacitance values, together with resistive elements  26   a - 26   d , the virtual condition that the output device and the device to be evaluated  30  might be connected by connecting wires of different lengths can be achieved. In fact, instead of three capacitive elements  25   a - 25   c , variable capacitances may be used. 
         [0031]    The resistive elements  26   a - 26   d  are connected to the capacitive elements  25   a - 25   c  in parallel. In an example of  FIG. 1 , four resistive elements  26   a - 26   d  are provided, but two resistive elements such as the resistive elements  26   a ,  26   b , the resistive elements  26   c ,  26   d , the resistive elements  26   a ,  26   c  or the resistive elements  26   b ,  26   d  may be also used. 
         [0032]    In addition, the resistance values of the resistive elements  26   a - 26   d  are generally equal to one another, and may be set from the range of 10-10 kΩ. As an example, the resistance value may be set at the value almost one-half of the impedance resistance value of the cable actually connected to the device to be evaluated  30 . That is, for example, if the cable having the impedance resistance value of 50 Ω is used, the resistance value of the resistive elements  26   a - 26   d  may be set at 10-30 Ω. 
         [0033]    The device to be evaluated  30  is a device which evaluates whether or not the required response is made with respect to signals outputted from the output device  10  and attenuated by the evaluation device  20 . Therefore, if the device to be evaluated  30  satisfies the following three conditions: it corresponds to the output device  10 ; it inputs signals outputted from the output device  10  and attenuated; and it outputs given signals depending on said input; it is evaluated that the required response has been made. 
         [0034]    The device to be evaluated  30  is provided with an input device  31 , a first amplifier circuit  32 , and a second amplifier circuit  33 , which will be described below. 
         [0035]    The input device  31  is a device for inputting signals corresponding to a command packet outputted from the output device  10  and attenuated in the evaluation device  20 , and then outputting signals corresponding to a response packet to the output device  10  within a given period after. 
         [0036]    The first amplifier  32  is a differential amplifier. In the first amplifier  32 , a waveform input terminal  32   a  is connected to a TXD output terminal  31   a  of the input device  31 , an input enable terminal  32   b  is connected to the TXE output terminal  31   b , a positive output terminal  32   c  is connected to the resistive element  26   c , and a negative output terminal  32   d  is connected to the resistive element  26   d . The TXD output terminal  31   a  is a terminal for outputting signals corresponding to a response packet, and the TXE output terminal  31   b  is a terminal for outputting the presence or absence of signals from the TXD output terminal  31   a.    
         [0037]    The second amplifier  33  is a differential amplifier. In the second amplifier  33 , a positive input terminal  33   a  is connected to the resistive element  26   c , a negative input child  33   b  is connected to the resistive element  26   d , and an output terminal  33   c  is connected to the input terminal  31   c  of the output device  31 . In addition, the second amplifier  33  can input a rectangular wave to the input device  31  by amplifying the power of input signals attenuated by the evaluation device  20 . 
         [0038]    Next, an operation of the evaluation system shown in  FIG. 1  will be explained. The evaluation system shown in  FIG. 1  outputs signals toward the device to be evaluated  30  from the TXD output terminal  11  and the TXE output terminal  12  of the output device  10 . These signals are inputted at the waveform input terminal  21   a  and at the input enable terminal  21   b  of the first amplifier  21  of the evaluation device  20 , respectively. 
         [0039]    If signals from the output device  10  are inputted, the first amplifier  21  generates those differential amplified signals, and outputs them from the positive output terminal  21   c  and the negative output terminal  21   d . These signals are inputted into the circuit element  24 . 
         [0040]    If signals from the first amplifier  21  are inputted, the circuit element  24  attenuates said signals by the resistive element  26   a  and the resistive element  26   b , any one of the capacitive elements  25   a - 25   c , as well as the resistive element  26   c  and the resistive element  26   d , and outputs them. These signals are inputted into the device to be evaluated  30 . 
         [0041]    The device to be evaluated  30  receives the signals from the evaluation device  20  at the positive input terminal  33   a  and the negative input terminal  33   b  of the second amplifier  33 . Here, if the second amplifier  33  is abnormal or has not enough performance, the second amplifier  33  cannot output an amplified signal from the output terminal  33   c . On the other hand, if the second amplifier  33  is not abnormal or has enough performance, the second amplifier  33  outputs an amplified signal from the output terminal  33   c . These signals are inputted into the input device  31 . 
         [0042]    The input device  31  receives the output signals from the second amplifier  33  at the input terminal  31   c . Here, if the input device  31  is abnormal or has not enough performance, signals in response to signals from the output device  10  cannot be outputted from the TXD output terminal  31   a  and the TXE output terminal  31   b . On the other hand, if the input device  31  is not abnormal or has enough performance, signals in response to signals from the output device  10  are outputted from the TXD output terminal  31   a  and the TXE output terminal  31   b . These signals are inputted into the first amplifier  32 . 
         [0043]    The first amplifier  32  receives signals from the input device  31  at the waveform input terminal  32   a  and the input enable terminal  32   b . Here, if the first amplifier  32  is abnormal or has not enough performance, the differential amplified signals of the waveform input terminal  32   a  and the input enable terminal  32   b  cannot be outputted from the positive output terminal  32   c  and the negative output terminal  32   d . On the other hand, if the first amplifier  32  is not abnormal or has enough performance, the differential amplified signals of the waveform input terminal  32   a  and the input enable terminal  32   b  are generated and outputted from the positive output terminal  32   c  and the negative output terminal  32   d . These signals are inputted into the circuit element  24 . 
         [0044]    If signals from the device to be evaluated  30  are inputted, the circuit element  24  attenuates said signals by the resistive element  26   c  and the resistive element  26   d , any of capacitive elements  25   a - 25   c , as well as the resistive element  26   a  and the resistive element  26   b , and outputs them. These signals are inputted into the second amplifier  22 . 
         [0045]    The second amplifier  22  receives signals from the circuit element  24  at the positive input terminal  22   a  and the negative input terminal  22   b , and outputs an amplified signal from the output terminal  22   c . These signals are inputted at the output device  10 . 
         [0046]    As discussed above, if the device to be evaluated  30  is not abnormal or has enough performance, when the signals are outputted from the output device  10 , the signals outputted from the device to be evaluated  30  in response to those signals can be inputted by the output device  10 . 
         [0047]      FIG. 2  is a view showing a variation of the evaluation system shown in  FIG. 1 , and is a configuration diagram of the evaluation system suitable for evaluation of so-called full duplex communication device. 
         [0048]    Here, the evaluation device  20  shown in  FIG. 1  is mainly a device for evaluating a so-called half-duplex communication device. In contrast, if a full duplex communication device is evaluated as shown in  FIG. 2 , there may be provided an evaluation device  20 ′ comprising a circuit element  24  for attenuating the signals outputted from the output device  10  and inputted to the device to be evaluated  30 , and a circuit element  24 ′ for attenuating the signals outputted from the device to be evaluated  30  and inputted to the output device  10 . 
         [0049]    In addition, the internal configuration of the circuit element  24  may be similar to that of the circuit element  24 ′. Therefore, for example, it is possible to implement an embodiment where four resistances  26   a - 26   d  are implemented in the circuit element  24 , and two resistances  26   a ′,  26   d ′ are implemented in the circuit element  24 ′. 
         [0050]      FIG. 3  is a signal view showing characteristics of the evaluation device  20  shown in  FIG. 1  or the evaluation device  20 ′ shown in  FIG. 2 .  FIG. 3  shows signals for evaluating the signal inputting capability of the device to be evaluated  30 .  FIG. 3  ( a ) shows an example of signals inputted to the evaluation device  20  or the like.  FIG. 3  ( b ) shows an example of signals outputted from the first amplifier  21 , if the signals shown in  FIG. 3  ( a ) have been inputted to the first amplifier  21 .  FIG. 3  ( c ) shows an example of the signals outputted from the circuit element  24  or the like if the signals shown in  FIG. 3  ( b ) have been inputted to the circuit element  24 . 
         [0051]      FIG. 4  is a signal view showing characteristics of the evaluation device  20  shown in  FIG. 1  or the evaluation device  20 ′ shown in  FIG. 2 .  FIG. 4  shows signals for evaluating the signal outputting capability of the device to be evaluated  30 .  FIG. 4  ( a ) shows an example of signals inputted to the evaluation device  20  or the like.  FIG. 4  ( b ) shows an example of signals outputted from the circuit element  24  or the like, if inputted to the circuit element  24  or the like.  FIG. 4  ( c ) shows an example of signals outputted from the second amplifier  22 , if the signals shown in  FIG. 4  ( b ) have been inputted to the second amplifier  22 . 
         [0052]    If signals with a rectangular wave as shown in  FIG. 3  ( a ) are inputted to the evaluation device  20 , power is amplified in the first amplifier  21  and rectangular waves, whose waveform is almost the same, are outputted as shown in  FIG. 3  ( b ). Next, the signals with the rectangular wave shown in  FIG. 3  ( b ) are attenuated by the resistive element  26   a  or the like and the capacitive element  25   a  or the like of the circuit element  24  or the like, and become signals with a waveform as shown in  FIG. 3  ( c ). If the device to be evaluated  30  performs the required performances, when the signals with a waveform shown in  FIG. 3  ( c ) are inputted, power of this signal is amplified by the second amplifier  33  and the signals are then inputted to the input device  31 . 
         [0053]    If the input device  31  performs the required performances, when the signals with a rectangular wave as shown in  FIG. 4  ( a ) are inputted to the evaluation device  20 , the signals with the rectangular wave shown in  FIG. 4  ( a ) are attenuated by the resistive element  26   a  or the like and the capacitive element  25   a  or the like of the circuit element  24  or the like, and become signals with a waveform as shown in  FIG. 4  ( c ). Next, if the signals with the waveform shown in  FIG. 4  ( b ) are inputted, power is amplified by the second amplifier  22  and the signals are then outputted toward the output device  10 . 
         [0054]    In other words, if the device to be evaluated  30  does not perform the required performances, that is, the device to be evaluated  30  is abnormal or has not enough performance, the signals are not outputted toward the output device  10  from the device to be evaluated  30 , or meaningless signals not corresponding to the waveform shown in  FIG. 4  ( a ) are outputted. 
       Embodiment 2 
       [0055]      FIG. 5  is a circuit diagram showing a schematic configuration of the evaluation system of the embodiment 2 of the present invention. This evaluation device  20  differs from the evaluation system shown to  FIG. 1  in that a pulse transformer  23  is provided between the first amplifier  21  and the second amplifier  22  and the circuit element  24 , in order to reduce noise of a direct current and to evaluate the capability of the pulse transformer  34 , which will be described below. 
         [0056]    Concretely, a pulse transformer  23  is provided in such a way that the connecting wire by which the first amplifier  21  and the circuit element  24  are connected is coupled with the connecting wire by which the second amplifier  22  and the circuit element  24  are connected. The operation of the evaluation system of the present embodiment is similar to that of the evaluation system of the embodiment 1. 
         [0057]    In addition, this pulse transformer  23  may be, of course, replaced with a capacitive coupling. Further, for similar reasons, a further pulse transformer may be also provided on the device to be evaluated  30  at the side of the circuit element  24  in the evaluation device  20 . However, if the pulse transformer  34  is provided in the device to be evaluated  30  as shown in  FIG. 5 , a further pulse transformer is unnecessary. 
         [0058]      FIG. 6  is a view showing a variation of the evaluation system shown in  FIG. 5 , and is a configuration diagram of the evaluation system suitable for the case where the so-called full duplex communication device is evaluated. As the evaluation system shown in  FIG. 2  corresponds to the evaluation system shown in  FIG. 1 , the evaluation system shown in  FIG. 6  corresponds to the evaluation system shown in  FIG. 5 . Therefore, a pulse transformer  23  is provided between the first amplifier  21  and the circuit element  24 , and a pulse transformer  23 ′ is provided between the second amplifier  22  and the circuit element  24 ′. 
         [0059]    In addition, the operation of the evaluation system shown in  FIG. 5  and  FIG. 6  is similar to that of the evaluation system shown in  FIG. 1  and  FIG. 2 , but when the signals outputted from the device to be evaluated  30  and attenuated by the circuit element  24  pass through the pulse transformer  23 , noise due to a direct current is reduced. In addition, if the pulse transformer  34  is provided in the device to be evaluated  30 , a pulse transformer may be also provided in a transmission path, so that the evaluation under the similar situation is possible, and the capability evaluation of the pulse transformer  34  can be also performed. 
       Embodiment 3 
       [0060]      FIG. 7  is a circuit diagram showing a schematic configuration of the evaluation system of the embodiment 3 of the present invention. This evaluation device  20  differs from the evaluation system shown to  FIG. 1  in that a pulse transformer  23  is provided between the first amplifier  21  and the second amplifier  22  and the circuit element  24 , and the circuit element  24  is comprised of a plurality of resistive element  25 . 
         [0061]    Each resistive element  25  is in parallel provided between the connecting wires via switches. For example, all resistive elements  25  may be, for example, 10 Ω and resistive values may be different for respective switch. 
         [0062]    If such evaluation device  20  is used, the amplifying capability of the first amplifier  32  of the device to be evaluated  30  can be evaluated. Here, it is possible technically to employ a cement resistor as a circuit element  24 , but because the cement resistor is expensive, it is hard to employ the cement resistor in the evaluation device  20 . Thus, in this embodiment, to achieve the circuit element  24  having enough power resistance for evaluating the amplifying capability of the first amplifier  32 , the circuit element  24  is comprised of a plurality of resistive elements  25 . 
       Embodiment 4 
       [0063]      FIG. 8  is a configuration diagram of the evaluation system of the embodiment of the present invention.  FIG. 8  shows a configuration in which choke coils  27 ,  28  are provided between the second amplifier  22  and the circuit element  24 ′ of the evaluation system shown to in  FIG. 2 . 
         [0064]      FIG. 9  is a waveform diagram of the signals outputted from the circuit element  24 ′ of  FIG. 8 . 
         [0065]      FIG. 10  is a waveform diagram of the signals in which high frequency components have been removed by the choke coils  27 ,  28  of  FIG. 8 . 
         [0066]    As shown in  FIG. 9 , when the level of the signal is changed, high frequency components referred to as so-called “glitches” are superimposed on the signals outputted from the circuit element  24 ′. The choke coils  27 ,  28  remove the high frequency components from the signals outputted from the circuit element  24 ′. That is, the choke coils  27 ,  28  function as a low-pass filter with respect to the signals outputted from the circuit element  24 ′. The choke coils  27 ,  28  may be appropriately selected from those of, for example, 1 μH-10 mH. 
         [0067]    In this embodiment, usage of the choke coils  27 ,  28  of 400 μH results in that the above high frequency components have been clealy removed as shown in  FIG. 10 . 
         [0068]    In addition, in this embodiment, the configuration in which choke coils  27 ,  28  are provided was explained for the evaluation system shown in  FIG. 2 , but the present embodiment may be applied to other evaluation systems of  FIG. 1  or the like shown in the previously mentioned embodiments. 
       BRIEF DESCRIPTION OF THE DRAWINGS  
       [0069]      FIG. 1  is a circuit diagram showing a schematic configuration of an evaluation system of an embodiment 1 of the present invention. 
         [0070]      FIG. 2  is a view showing a variation of an evaluation system shown in  FIG. 1 . 
         [0071]      FIG. 3  is a signal view showing characteristics of the evaluation device  20  shown in  FIG. 1  or the evaluation device  20 ′ shown in  FIG. 2 . 
         [0072]      FIG. 4  is a signal view showing characteristics of the evaluation device  20  shown in  FIG. 1  or the evaluation device  20 ′ shown in  FIG. 2 . 
         [0073]      FIG. 5  is a circuit diagram showing a schematic configuration of the evaluation system of the embodiment 2 of the present invention. 
         [0074]      FIG. 6  is a view showing a variation of the evaluation system shown in  FIG. 5 . 
         [0075]      FIG. 7  is a circuit diagram showing a schematic configuration of the evaluation system of the embodiment 3 of the present invention. 
         [0076]      FIG. 8  is a configuration diagram of the evaluation system of the embodiment of the present invention. 
         [0077]      FIG. 9  is a waveform diagram of the signals outputted by the circuit element  24 ′ in  FIG. 8 . 
         [0078]      FIG. 10  is a waveform diagram of the signals in which high frequency components have been removed by the choke coils  27 ,  28  in  FIG. 8 .