Abstract:
A system for DMA transfer includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus interface, wherein the bus interface is configured to allocate the plurality of registers doubly to nonconsecutive addresses and consecutive addresses to allow the DMA controller to access the plurality of registers through the consecutive addresses.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-064358 filed on Mar. 8, 2005, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention generally relates to data transfer systems and data transfer methods, and particularly relates to a DMA transfer system and DMA transfer method.  
         [0004]     2. Description of the Related Art  
         [0005]     A DMA (direct memory access) transfer system achieves high-speed data transfer by transferring data directly from a source to a destination without having an intervening CPU.  FIG. 1  is a drawing showing an example of the configuration of a related-art DMA transfer system.  
         [0006]     A DMA transfer system  10  shown in  FIG. 1  includes a CPU  11 , an interruption controller  12 , a DMA controller  13 , a memory  14 , event counters  15 - 1  through  15 - 4 , and bus interfaces  16 - 1  through  16 - 4 . The CPU  11 , the interruption controller  12 , the DMA controller  13 , and the memory  14  are coupled to each other via a bus  17 . Further, the event counters  15 - 1  through  15 - 4  are coupled to the bus  17  through the respective bus interfaces  16 - 1  through  16 - 4 .  
         [0007]     The CPU  11  specifies a transfer source address, a transfer destination address, transfer data size, an increment/decrement of the transfer source address, an increment/decrement of the transfer destination address, etc., for DMA, thereby determining the settings of DMA transfer with respect to the DMA controller  13 . In response, the DMA controller  13  performs the specified DMA transfer.  
         [0008]     A description will be given below with respect to an example in which register data is transferred through DMA from the event counters  15 - 1  through  15 - 4  to the memory  14 . Although the event counters are used as an example here, the operation of the DMA transfer remains the same even if macros having other functions are used.  
         [0009]     The event counters  15 - 1  through  15 - 4  serve to count the pulses of data signals D 0  through D 4  during a period indicated by trigger signals TRG 0  through TRG 4 , respectively. Namely, the event counter  15 - 1  starts counting the pulses of the data signal D 0  when the trigger signal TRG 0  becomes HIGH, and continues counting until the trigger signal TRG 0  becomes LOW. When the counting comes to an end upon the change to LOW of the trigger signal TRG 0 , the count value is stored in an internal register of the event counter  15 - 1 .  
         [0010]     Upon completion of counting, the event counters  15 - 1  through  15 - 4  generate interruption signals INT 0  through INT 3 . These interruption signals INT 0  through INT 3  are supplied to the interruption controller  12 . In response to the interruption signals INT 0  through INT 3 , the interruption controller  12  instructs the DMA controller  13  to start DMA transfer. In response, the DMA controller  13  performs DMA transfer.  
         [0011]      FIG. 2  is a drawing showing the details of the event counters  15 - 1  through  15 - 4  and the bus interfaces  16 - 1  through  16 - 4  for the purpose of explaining DMA transfer operation. As shown in  FIG. 2 , the event counters  15 - 1  through  15 - 4  are provided with respective register sets  20 - 1  through  20 - 4 . Further, the bus interfaces  16 - 1  through  16 - 4  include decoder selectors  21 - 1  through  21 - 4 , respectively.  
         [0012]     The register set  20 - 1  of the event counter  15 - 1  includes registers RA 0 , RB 0 , and RC 0 . The register set  20 - 2  of the event counter  15 - 2  includes registers RA 1 , RB 1 , and RC 1 . The register set  20 - 3  of the event counter  15 - 3  includes registers RA 2 , RB 2 , and RC 2 . The register set  20 - 4  of the event counter  15 - 4  includes registers RA 3 , RB 3 , and RC 3 . Each register is configured to store 8-bit data.  
         [0013]     The bus  17  includes 32-bit address bus A[31:0], 2-bit control bus RW[1:0] for specifying write/read operation, and 32-bit data bus D[31:0]. As shown in the event counter  15 - 1 , the data of the register RA 0  corresponds to D[31:24] that represents bit  31  through bit  24  of the data bus. The data of the register RB 0  corresponds to D[23:16] that represents bit  23  through bit  16  of the data bus. Further, the data of the register RC 0  corresponds to D[15:8] that represents bit  15  through bit  8  of the data bus. Although illustration is omitted with respect to the event counters  15 - 2  through  15 - 4  due to the lack of space, the relationship between each of the register sets  20 - 2  through  20 - 4  and the data bus D[31:0] is the same as that of the register set  20 - 1 .  
         [0014]     With this configuration that assigns the registers RA 0 , RB 0 , and RC 0  to the respective portions of the data bus D[31:0], it is possible to transfer all the data of the register set  20 - 1  at once by transferring 32-bit data on the D[31:0]. Accordingly, not only a DMA transfer that transfers 8-bit data three times, but also a DMA transfer that transfers 32-bit data only once, can be used for the purpose of transferring the data of the register set  20 - 1 .  
         [0015]     As shown in the event counter  15 - 1  and the bus interface  16 - 1 , the registers RA 0 , RB 0 , and RC 0  are allocated to addresses 0x1000, 0x1001, and 0x1002, respectively. Selecting a desired register by use of these addresses makes it possible to perform read access or write access to the selected register. By the same token, addresses 0x1004 through 0x1006 are allocated to the register set  20 - 2 , addresses 0x1008 through 0x100A to the register set  20 - 3 , and addresses 0x100C through 0x100E to the register set  20 - 4 .  
         [0016]      FIG. 3  is a drawing showing the allocation of the registers shown in  FIG. 2  to the address space. As shown on the left-hand side of  FIG. 3 , the registers RA 0 , RB 0 , and RC 0  are allocated to 0x1000, 0x1001, and 0x1002, respectively, the resisters RA 1 , RB 1 , and RC 1  to 0x1004, 0x1005, and 0x1006, respectively, the resisters RA 2 , RB 2 , and RC 2  to 0x1008, 0x1009, and 0x100A, respectively, and the resisters RA 3 , RB 3 , and RC 3  to 0x100C, 0x100D, and 0x100E, respectively. This is the same as what is already described above.  
         [0017]     It is assumed that the count values as previously described are stored as the data indicative of the results of counting in the RA 0 , RA 1 , RA 2 , and RA 3  of the event counters  15 - 1  through  15 - 4 . A case will then be examined below in which these count values are read out and transferred to addresses 0x2000 through 0x2003 in the memory  14  ( FIG. 1 ). In such a case, the start address of the transfer source is set to 0x1000, the data transfer width to 8 bits, and an address increment at the transfer source to +4. These settings make it possible to perform DMA transfer with respect to the count values stored in the registers. This DMA transfer is performed by transferring 8-bit data four times.  
         [0018]     In this case, the size of transfer data is 32 bits in total. Despite the fact that the data bus D[31:0] provides a 32-bit data width, however, a single 32-bit-width DMA transfer cannot be utilized in this case. This is because the addresses of the registers RA 0 , RA 1 , RA 2 , and RA 3  are not arranged as consecutive addresses. Even if these addresses are arranged consecutively, these registers are all allocated to the same portion D[31:24] of the data bus, so that it is impossible to perform a 32-bit-width DMA transfer.  
         [0019]     As another example, it is assumed that the count values as described above are stored as the data indicative of the results of counting in the registers RB 0 , RA 1 , RC 2 , and RA 3  of the event counters  15 - 1  through  15 - 4 . Address increments between the registers are +3, +6, and +2 in this case. Since the address increments are not constant, the DMA transfer that transfers 8-bit data four times cannot be performed. Further, because of the same reasons as in the previous case, the DMA transfer that transfers 32-bit data once cannot be performed. That is, no DMA transfer is possible in this case.  
         [0020]     When there is a need to transfer the data of registers that are allocated to nonconsecutive or unequal-interval addresses, conventionally, data transfer is performed by CPU-based software operations. In the case of such software-based data transfer, all the four operation steps, i.e., setting of a read address, reading of data, setting of a write address, and writing of the data, need to be performed for each transfer action. Such transfer operation is thus extremely inefficient compared with DMA transfer, failing to achieve high-speed data transfer.  
         [0021]     As a reference, Japanese Patent Application Publication No. 2001-256104 discloses a configuration for performing efficient access to nonconsecutive addresses.  
         [0022]     Accordingly, there is a need for a DMA transfer system which can perform efficient DMA transfer with respect to data stored in the registers that are allocated to nonconsecutive or unequal-interval addresses.  
       SUMMARY OF THE INVENTION  
       [0023]     It is a general object of the present invention to provide a DMA transfer system that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.  
         [0024]     Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a DMA transfer system particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.  
         [0025]     To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a system for DMA transfer which includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus interface, wherein the bus interface is configured to allocate the plurality of registers doubly to nonconsecutive addresses and consecutive addresses to allow the DMA controller to access the plurality of registers through the consecutive addresses.  
         [0026]     Further, a DMA transfer method according to the present invention includes allocating to consecutive addresses a plurality of registers allocated to nonconsecutive addresses, and performing DMA transfer to transfer data of the plurality of registers to a destination from the consecutive addresses serving as source addresses.  
         [0027]     According to at least one embodiment of the present invention, even if the resisters serving as sources of DMA transfer are not allocated to consecutive addresses, the data can be accessed as a single contiguous chunk in the address space by assigning these registers to consecutive addresses by use of mirror registers. With this provision, it is possible to perform a single DMA transfer for a single contiguous data chunk even when the registers serving as the sources of DMA transfer are not allocated to consecutive addresses.  
         [0028]     Further, registers that have uneven address increments therebetween and thus cannot be subjected to DMA transfer may also be assigned as mirror registers to consecutive addresses. This makes it possible to set constant address increments so as to achieve DMA transfer. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:  
         [0030]      FIG. 1  is a drawing showing an example of the configuration of a related-art DMA transfer system;  
         [0031]      FIG. 2  is a drawing showing the detail of event counters and bus interfaces for the purpose of explaining DMA transfer operation;  
         [0032]      FIG. 3  is a drawing showing the allocation of registers shown in  FIG. 2  to the address space;  
         [0033]      FIG. 4  is a drawing showing an example of the configuration of a DMA transfer system according to the present invention;  
         [0034]      FIG. 5  is a drawing showing the detail of event counters and a bus interface for the purpose of explaining DMA transfer operation;  
         [0035]      FIG. 6  is a drawing showing the allocation of registers shown in  FIG. 5  to the address space;  
         [0036]      FIG. 7  is a drawing showing the 8-bit data register map of  FIG. 6  as rearranged into a 32-bit register map; and  
         [0037]      FIG. 8  is a flowchart showing a procedure for a DMA transfer process performed by the DMA transfer system of  FIG. 4 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0038]     In the following, embodiments of the present invention will be described with reference to the accompanying drawings.  
         [0039]      FIG. 4  is a drawing showing an example of the configuration of a DMA transfer system according to the present invention. In  FIG. 4 , the same elements as those of  FIG. 1  are referred to by the same numerals.  
         [0040]     A DMA transfer system  30  shown in  FIG. 4  includes the CPU  11 , the interruption controller  12 , the DMA controller  13 , the memory  14 , the event counters  15 - 1  through  15 - 4 , and a bus interface  31 . The CPU  11 , the interruption controller  12 , the DMA controller  13 , and the memory  14  are coupled to each other via the bus  17 . Further, the event counters  15 - 1  through  15 - 4  are coupled to the bus  17  through the bus interface  31 .  
         [0041]     A description will be given below with respect to an example in which register data is transferred through DMA from the event counters  15 - 1  through  15 - 4  to the memory  14 . Although the event counters are used as an example here, the operation of the DMA transfer remains the same even if macros having other functions are used.  
         [0042]     The event counters  15 - 1  through  15 - 4  serve to count the pulses of data signals D 0  through D 4  during the period indicated by trigger signals TRG 0  through TRG 4 , respectively. When the counting comes to an end, the count values are stored in the internal registers of the event counters  15 - 1  through  15 - 4 , and the interruption signals INT 0  through INT 3  are generated. These interruption signals INT 0  through INT 3  are supplied to the interruption controller  12 . In response to the interruption signals INT 0  through INT 3 , the interruption controller  12  instructs the DMA controller  13  to start DMA transfer. In response, the DMA controller  13  performs DMA transfer.  
         [0043]      FIG. 5  is a drawing showing the details of the event counters  15 - 1  through  15 - 4  and the bus interface  31  for the purpose of explaining DMA transfer operation. In  FIG. 5 , the same elements as those of  FIG. 2  are referred to by the same numerals.  
         [0044]     As shown in  FIG. 5 , the event counters  15 - 1  through  15 - 4  are provided with the respective register sets  20 - 1  through  20 - 4 . Further, the bus interface  31  includes a decoder-&amp;-selector  32  and OR gates  33 - 1  through  33 - 4 .  
         [0045]     The register set  20 - 1  of the event counter  15 - 1  includes registers RA 0 , RB 0 , and RC 0 . The register set  20 - 2  of the event counter  15 - 2  includes registers RA 1 , RB 1 , and RC 1 . The register set  20 - 3  of the event counter  15 - 3  includes registers RA 2 , RB 2 , and RC 2 . The register set  20 - 4  of the event counter  15 - 4  includes registers RA 3 , RB 3 , and RC 3 . Each register is configured to store 8-bit data.  
         [0046]     The bus  17  includes the 32-bit address bus A[31:0], the 2-bit control bus RW[1:0] for specifying write/read operation, and the 32-bit data bus D[31:0]. As shown in the event counter  15 - 1 , the data of the register RA 0  corresponds to D[31:24] that represents bit  31  through bit  24  of the data bus. The data of the register RB 0  corresponds to D[23:16] that represents bit  23  through bit  16  of the data bus. Further, the data of the register RC 0  corresponds to D[15:8] that represents bit  15  through bit  8  of the data bus. Although illustration is omitted with respect to the event counters  15 - 2  through  15 - 4  due to the lack of space, the relationship between each of the register sets  20 - 2  through  20 - 4  and the data bus D[31:0] is the same as that of the register set  20 - 1 .  
         [0047]     As shown in the event counter  15 - 1  and the bus interface  31 , the registers RA 0 , RB 0 , and RC 0  are allocated to addresses 0x1000, 0x1001, and 0x1002, respectively. When the decoder-&amp;-selector  32  decodes the address on the address bus A[31:0] to assert a decode signal corresponding to address 0x1000, access to the register RA 0  becomes possible in response to the assertion of this decode signal.  
         [0048]     Namely, in the case of a read operation as in this DMA transfer example, the content of the register RA 0  is read to the data bus D[31:24] in response to the assertion of the decode signal. If a decode signal corresponding to address 0x1001 is asserted, the content of the register RB 0  is read to the data bus D[23:16] in response to this assertion. If a decode signal corresponding to address 0x1002 is asserted, the content of the register RC 0  is read to the data bus D[15:8] in response to this assertion.  
         [0049]     Further, the OR gate  33 - 1  provided in the bus interface  31  is configured to perform an OR operation between the decode signal corresponding to address 0x1000 output from the decoder-&amp;-selector  32  and the decode signal corresponding to address 0x1010. A signal resulting from this OR operation is supplied to the register RA 0 . Accordingly, the register RA 0  is allocated to address 0x1000 and also to address 0x1010. When the decoder-&amp;-selector  32  decodes an address on the address bus A[31:0] to assert the decode signal corresponding to address 0x1010, thus, the content of the register RA 0  is read out to the portion D 0 [31:24] of the data bus D 0 [31:0] between the event counter  15 - 1  and the bus interface  31 .  
         [0050]     The same applies in the case of the event counter  15 - 2 . That is, the register RA 1 , RB 1 , and RC 1  are allocated to addresses 0x1004, 0x1005, and 0x1006, respectively, and the OR gate  33 - 2  performs an OR operation between the decode signal corresponding to address 0x1004 and the decode signal corresponding to address 0x1011. A signal resulting from this OR operation is supplied to the register RA 1 . Accordingly, the register RA 1  is allocated to address 0x1004 and also to address 0x1011. When the decoder-&amp;-selector  32  decodes an address on the address bus A[31:0] to assert the decode signal corresponding to address 0x1011, thus, the content of the register RA 1  is read out to the portion D 1 [31:24] of the data bus D 1 [31:0] between the event counter  15 - 2  and the bus interface  31 .  
         [0051]     The same applies in the case of the event counter  15 - 3 . That is, the register RA 2 , RB 2 , and RC 2  are allocated to addresses 0x1008, 0x1009, and 0x100A, respectively, and the OR gate  33 - 3  performs an OR operation between the decode signal corresponding to address 0x1008 and the decode signal corresponding to address 0x1012. A signal resulting from this OR operation is supplied to the register RA 2 . Accordingly, the register RA 2  is allocated to address 0x1008 and also to address 0x1012. When the decoder-&amp;-selector  32  decodes an address on the address bus A[31:0] to assert the decode signal corresponding to address 0x1012, thus, the content of the register RA 2  is read out to the portion D 2 [31:24] of the data bus D 2 [31:0] between the event counter  15 - 3  and the bus interface  31 .  
         [0052]     The same applies in the case of the event counter  15 - 4 . That is, the register RA 3 , RB 3 , and RC 3  are allocated to addresses 0x100C, 0x100D, and 0x100E, respectively, and the OR gate  33 - 4  performs an OR operation between the decode signal corresponding to address 0x100C and the decode signal corresponding to address 0x1013. A signal resulting from this OR operation is supplied to the register RA 3 . Accordingly, the register RA 3  is allocated to address 0x100C and also to address 0x1013. When the decoder-&amp;-selector  32  decodes an address on the address bus A[31:0] to assert the decode signal corresponding to address 0x1013, thus, the content of the register RA 3  is read out to the portion D 3 [31:24] of the data bus D 3 [31:0] between the event counter  15 - 4  and the bus interface  31 .  
         [0053]      FIG. 6  is a drawing showing the allocation of the registers shown in  FIG. 5  to the address space. As shown in  FIG. 6 , the registers RA 0 , RB 0 , and RC 0  are allocated to addresses 0x1000, 0x1001, and 0x1002, respectively, the resisters RA 1 , RB 1 , and RC 1  to addresses 0x1004, 0x1005, and 0x1006, respectively, the resisters RA 2 , RB 2 , and RC 2  to addresses 0x1008, 0x1009, and 0x100A, respectively, and the resisters RA 3 , RB 3 , and RC 3  to addresses 0x100C, 0x100D, and 0x100E, respectively.  
         [0054]     Based on the functions of the OR gates  33 - 1  through  33 - 4  of the bus interface  31 , further, the registers RA 0 , RA 1 , RA 2 , and RA 3  are allocated as mirror registers to addresses 0x1010, 0x1011, 0x1012, and 0x1013, respectively.  
         [0055]     In this case, the mirror registers are allocated consecutive addresses 0x1010 through 0x1013, so that the data of these registers can be treated as 32-bit data starting at address 0x1010 in the address space. However, the registers RA 0 , RA 1 , RA 2 , and RA 3  are all assigned to the same portion D[31:24] of the data bus, i.e., not arranged as 32-bit-wdith data on the data bus D[31:0]. Without any change, thus, it is not possible to perform 32-bit-width DMA transfer.  
         [0056]     In the present invention, when the registers RA 0 , RA 1 , RA 2 , and RA 3  are accessed as mirror registers located at addresses 0x1010 through 0x1013, the decoder-&amp;-selector  32  shown in  FIG. 5  rearranges the data read from the registers RA 0 , RA 1 , RA 2 , and RA 3  into 32-bit data on the data bus [31:0] of the bus  17 . Namely, the decoder-&amp;-selector  32  rearranges D 0 [31:24], D 1 [31:24], D 2 [31:24], and D 3 [31:24] to make them correspond to D[31:24], D[23:16], D[15:8], and D[7:0], respectively, thereby forming 32-bit data, which is then output to the data bus of the bus  17 .  
         [0057]      FIG. 7  is a drawing showing the 8-bit data register map of  FIG. 6  as rearranged into a 32-bit register map. As shown in  FIG. 7 , the registers RA 0 , RB 0 , and RC 0  correspond to the 24 upper-order bits of the 32-bit data starting at address 0x1000.  
         [0058]     As described above, data read from the mirror registers are rearranged by the decoder-&amp;-selector  32  as to their positions on the data bus. As a result, the mirror registers corresponding to the registers RA 0 , RA 1 , RA 2 , and RA 3  (shown in brackets) are assigned to every 8 bits successively from the highest-order bit as shown in  FIG. 7 , thereby forming 32-bit data. With this provision, it is possible to transfer the contents of the registers RA 0 , RA 1 , RA 2 , and RA 3  to address 0x2000 of the memory  14  through a single 32-bit-width DMA transfer by treating them as 32-bit data starting at address 0x1010.  
         [0059]     In this manner, even if the resisters serving as sources of DMA transfer are not allocated to consecutive addresses, the present invention provides for data to be accessed as a single contiguous chunk in the address space by assigning these registers to consecutive addresses by use of mirror registers. Further, the data read by accessing the mirror registers are rearranged such that the data can be transferred as a single data chunk on the data bus. With this provision, it is possible to perform a single DMA transfer for a single contiguous data chunk even when the registers serving as the sources of DMA transfer are not allocated to consecutive addresses.  
         [0060]     As another example, it is assumed that the count values as previously described are stored as the data indicative of the results of counting in the registers RB 0 , RA 1 , RC 2 , and RA 3  of the event counters  15 - 1  through  15 - 4 . Address increments between the registers are +3, +6, and +2 in this case. Since the address increments are not constant, the DMA transfer that transfers 8-bit data four times cannot be performed.  
         [0061]     Even in such a case, the OR gates  33 - 1  through  33 - 4  of the bus interface  31  shown in  FIG. 5  may be provided for the registers RB 0 , RA 1 , RC 2 , and RA 3 , respectively, thereby assigning the registers RB 0 , RA 1 , RC 2 , and RA 3  to addresses 0x1010, 0x1011, 0x1012, and 0x10 13  as mirror registers. This makes it possible to transfer the contents of the registers RB 0 , RA 1 , RC 2 , and RA 3  to a desired address in the memory  14  through a single 32-bit-width DMA transfer by treating them as 32-bit data starting at address 0x1010. In this manner, registers that have uneven address increments therebetween and thus cannot be subjected to DMA transfer may be assigned as mirror registers to consecutive addresses, thereby being possible to be accessed as a signal contiguous data chunk in the address space. Further, the data read by accessing the mirror registers may be rearranged such that the data can be transferred through DMA as a single data chunk on the data bus.  
         [0062]      FIG. 8  is a flowchart showing a procedure for the DMA transfer process performed by the DMA transfer system  30  of  FIG. 4 . At step S 1  of  FIG. 8 , an interruption occurs. This corresponds to the occurrence of interruption signals from the event counters  15 - 1  through  15 - 4 . At step S 2 , a DMA operation is activated. That is, the interruption controller  12  requests the DMA controller  13  to activate DMA in response to the interruption signals from the event counters  15 - 1  through  15 - 4 , so that the DMA controller  13  activates the DMA operation.  
         [0063]     At step S 3 , the bus interface  31  supplies a register-read request to the event counters  15 - 1  through  15 - 4 . Namely, in response to a request from the DMA controller  13  to read 32-bit data from a predetermined address (i.e., 0x1010 in the example of  FIG. 5 ), the decoder-&amp;-selector  32  of the bus interface  31  asserts address decode signals corresponding to addresses 0x1010, 0x1011, 0x1012, and 0x1013. In response to this register-read request, steps S 4  through S 7  are performed in parallel, so that the event counters  15 - 1  through  15 - 4  (DMA channels ch 0  through ch 3 ) outputs the data of the register RA 0 , the register RA 1 , the register RA 2 , and the register RA 3 , respectively, in parallel.  
         [0064]     At step S 8 , the decoder-&amp;-selector  32  of the bus interface  31  rearranges the data read from the register RA 0 , the register RA 1 , the register RA 2 , and the register RA 3  into 32-bit data. At step S 9 , the decoder-&amp;-selector  32  outputs the 32-bit data to the data bus D[31:0] of the bus  17 . Thereafter, the DMA controller  13  performs a process that writes the data on the data bus D[31:0] to a specified address in the memory  14 . At step S 9 , the interruption is cleared. That is, the state in which an interruption process is performed by the interruption controller  12  is brought to an end.  
         [0065]     Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.