Abstract:
A time base correcting apparatus for removing time base errors from video signals in a video tape playback device which is operable in either a first normal or high speed operation mode or a second still motion or slow speed operation mode. In the first operation mode, first and second fields are reproduced in succession from successive tracks and in the second operation mode, the same field is reproduced at least twice in succession from the same track. The video signals are received and stored in a memory. First and second synchronizing signals corresponding to the first and second fields are alternately generated and include equalizing, vertical and horizontal sync pulses. Corrected first and second synchronizing signals are selectively generated during the second operation mode as a function of whether the second field or the first field is reproduced twice in succession. The first and second synchronizing signals are added to the first and second fields of video signals read out from the memory during the first operation mode; and during the second operation mode, when the first field is reproduced twice in succession, the first synchronizing signal and the corrected second synchronizing signal are added thereto, respectively, and when the second field is reproduced twice in succession, the second synchronizing signal and the corrected first synchronizing signal are added thereto.

Description:
FIELD OF INDUSTRIAL USE 
     The present invention generally relates to a time base correcting apparatus for correcting time base errors of a video signal caused by fluctuation in rotations of a rotary magnetic head and by variations in a tape drive operation with regard to, for instance, a reproduced video signal of a VTR (video tape recorder). More specifically, the present invention is directed to such a time base correcting apparatus for correcting temporal jitter and time base errors of a reproduced video signal when a video (image) signal of either a first field or a second field is repeatedly and continuously reproduced in either slow mode or still mode. 
     DESCRIPTION OF THE PRIOR ART 
     In conventional VTRs (video tape recorders), a time base correcting apparatus is provided such as is described in U.S. Pat. No. 4,063,284 and other publications as an apparatus for correcting time base errors of video signals reproduced by a rotary magnetic head from inclined tracks of a magnetic tape. Referring now to FIG. 1, one of these conventional time base correcting apparatuses will be described. A video (image) signal reproduced by the rotary head and the like from an inclined track of a magnetic tape contains temporal fluctuation (jitter). This reproduced video signal containing jitter is received as the input video signal. The input video signal is A/D-converted by an A/D (analog-to-digital) converting circuit 1, and then stored in a memory 2. 
     The video signal stored in the memory 2 is read out by a clock having a constant time period with no jitter. In other words, the jitter is absorbed via the memory 2. The read video signal is D/A-converted by a D/A (digital-to-analog) converter 3, and thereafter, the D/A-converted video signal is supplied to a synchronization signal adding circuit 4 in which a synchronization signal newly generated by a synchronization signal generating circuit 5 irrelevant to the synchronization signal of the input video signal is added to this D/A-converted video signal. 
     As represented in FIG. 2, as to the synchronization signal generated by the synchronization signal generating circuit 5, the vertical synchronization pulse of the second field is shifted by 0.5 H (symbol &#34;H&#34; denotes a horizontal scanning period) with respect to the vertical synchronization pulse of the first field. In this case, the number of equalizing pulses in the first field, prior to the vertical synchronization pulse, is selected as an even number, i.e., 6, whereas the number of equalizing pulses in the second field is selected as an odd number, i.e., 7, so that the first field is discriminated from the second field. As described above, the video signal to which the newly generated stable synchronization signal has been added is output and supplied thereafter to a video signal processing circuit (not shown) coupled to the above-described synchronization signal adding circuit 4. 
     As previously explained, in the synchronization signal added to the video signal read out from the memory 2 according to the conventional time base collector, the first field and the second field are alternately repeated. As a consequence, since the video signal in the first field and the video signal in the second field are alternately reproduced during normal or high-speed reproduction mode, both the synchronization signal in the first field and the synchronization signal in the second field are added to these video signals in the above-described manner, whereby a normal image can be reproduced. 
     On the other hand, slow-mode reproduction and still-mode reproduction are frequently performed in medical diagnostic VTRs and monitoring VTRs. In the case of slow-mode reproduction and the still-mode reproduction, since the same inclined track recorded on the magnetic tape is repeatedly scanned by the reproducing rotary head (not shown), a video signal of the same field is repeatedly reproduced. For instance, when the video signal in the first field is repeatedly reproduced in slow-mode reproduction, if the synchronization signal of the first field and the synchronization signal of the second field are alternately added to these repeatedly reproduced video signals, then the synchronization signal of the first field is added to a image appearing only in this first field, namely an image indicated by a circle a shown in FIG. 2a, which does not cause a problem. However, as represented in FIG. 2b, the synchronization signal of the second field is added to this image which is originally present in the first field, which causes the following problems. 
     That is, in this case, the image (indicated by a circle in FIG. 3a) which should be originally displayed only in the first field of the monitor 30, would be also displayed in the second field, as represented in FIG. 3b. This implies that an image which is not originally present is output. This is because a judgement is made in the monitor 30 as to whether the image is present in the first field, or in the second field based on the quantity of the equalizing pulse appearing before the vertical synchronization pulse. 
     In this case, an elongate ellipse can be seen, as indicated by the dotted line in FIG. 3b, although a circle should be originally seen. Such an adverse phenomenon may cause various problems. For example, when a medical diagnostic operation is carried out, or an object is observed, an image different from an originally recorded image would be displayed, which may lead to misjudgments. 
     OBJECT 
     An object of the present invention is to provide a time base correcting apparatus capable of correctly reproducing a image in a VTR even when either a video (image) signal of a first field, or a video (image) signal of a second field is repeatedly and continuously reproduced during variable speed reproduction such as slow-mode reproduction or still-mode reproduction. 
     SUMMARY OF THE INVENTION 
     To achieve the above-described object, a time base correcting apparatus for removing time base errors from video signals, according to one aspect of the present invention, comprises: 
     means for receiving video information; 
     means for detecting field information contained in said video information; 
     memory for storing both said video information and said field information; 
     means coupled to said receiving means, for generating a write clock pulse used to write said video information into said memory and for providing said write clock pulse to said memory; 
     means for generating a synchronizing signal to be synchronized with video signals stored in said memory; 
     means coupled to said synchronizing signal generating means, for generating a read clock pulse used to read from said memory correction video signals from which time base errors have been removed in response to said synchronizing signal and for providing said read clock pulse to said memory; 
     means coupled to said synchronizing signal generating means, for generating a correction synchronizing signal corresponding to said correcting video signals in response to said field information read from said memory; and 
     means for adding said correcting synchronizing signal to said correction video signals. 
     Furthermore, a time base correcting apparatus for removing time base errors from video signals, according to another aspect of the present invention, comprises: 
     means for receiving analog video signals; 
     A/D converting means for converting said analog video signals to digital video signals; 
     means coupled to said receiving means, for detecting a quantity of equalizing pulses existing before vertical synchronizing pulses of said analog video signals to discriminate a first field from a second field of said analog video signals, and for outputting a field discriminating signal indicative of one of said first and second fields of said analog video signals; 
     means for adding said field discriminating signal to said digital video signals to output added digital video signals; 
     first and second memories for storing said digital video signal; 
     first selecting means for alternately supplying said added digital video signals to one of said first memory and said second memory for every field in response to said field discriminating signal; 
     means coupled to said receiving means, for generating a clock signal synchronized with said analog video signals, which is used to write said added digital video signals into said first and second memories, and for supplying said generated clock signal to said first and second memories; 
     means for alternately producing a first synchronizing signal and a second synchronizing signal at a predetermined time period; 
     means coupled to said synchronizing signal generating means, for generating a clock signal synchronized with the synchronizing signal generated by said synchronizing signal generating means in order to read digital correction video signals from said first and second memories, from which time base errors have been removed, and for supplying said generated clock signal to said first and second memories; 
     a D/A converting circuit for converting said digital correction video signals derived from said first and second memory to analog correction video signals; 
     means for detecting changes in a field in response to said first and second synchronizing signals produced by said synchronizing signal generating means and for outputting a field change detecting signal indicative of said change in the field; 
     second selecting means for alternately providing said digital correction video signals read out from said first and second memories to said D/A converting circuit in response to said field change detecting signal; 
     means for converting said first and second field synchronizing signals produced by said synchronization signal generating circuit to synchronizing signals corresponding to the field of said analog correction signal; 
     said synchronizing signal converting means comprising; 
     first converting means for converting said first field synchronizing signal to a second field synchronizing signal; 
     second converting means for converting said second field synchronizing signal to a first field synchronizing signal; 
     means for detecting a first or second field from said digital correction video signals read from said first or second memory and for outputting a field detecting signal indicative of the first field or the second field; and 
     third selecting means coupled to said synchronizing means and said first and second converting means, for selectively outputting respective output signals from said synchronizing signal generating means and said first and second converting means in response to said field detecting signal; 
     said time base correcting apparatus further comprising: 
     a synchronizing signal adding circuit for adding said synchronizing signals from said third selecting means to said analog correction video signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram for explaining a conventional time base correcting apparatus. 
     FIG. 2 shows waveforms of synchronization signals in a first field and a second field of the NTSC system. 
     FIG. 3 is an explanatory diagram for explaining the relationship between an input image and an output image of a conventional time base correcting apparatus. 
     FIG. 4 is a schematic block diagram for showing a time base correcting apparatus according to a preferred embodiment of the present invention. 
     FIG. 5 is a schematic block diagram for representing a synchronization signal controlling circuit of the time base correcting apparatus according to the present invention. 
     FIG. 6 schematically indicates a process operation of a first field converting circuit for converting an NTSC system video signal into a synchronization signal of the first field. 
     FIG. 7 schematically represents a process operation of a second field converting circuit for converting an NTSC system video signal into a synchronization signal of the second field. 
     FIG. 8 schematically shows a process operation of a first field converting circuit for converting a PAL system video signal into a synchronization signal of the first field. 
     FIG. 9 schematically denotes a process operation of a second field converting circuit for converting a PAL system video signal into a synchronization signal of the second field. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the drawings, a time base correcting apparatus according to a preferred embodiment of the present invention will now be described. 
     FIG. 4 is a schematic block diagram for showing a time base correcting apparatus according to one preferred embodiment of the present invention. In the time base correcting apparatus, for instance, a video signal reproduced from an inclined track of the magnetic tape by a rotary head is received as an input video signal, and the input video signal is A/D-converted by an A/D converter 1 into a digital video signal which will then be supplied to an adder circuit 6. Also, this input video signal is supplied to a write field detecting circuit 7 and a write address controller 8. 
     The write field detecting circuit 7 detects the number of equalizing pulses present before the vertical synchronization pulse to judge whether the input video signal corresponds to a first field or a second field, and thus outputs a field. discriminating signal indicative of the sort of field for the input video signal. In the case of the first field, for instance, a &#34;High&#34; signal is output, whereas a &#34;Low&#34; signal is output in the case of the second field. 
     As a consequence, during reproducing modes such as the normal or high-speed reproduction modes, since the first field and the second field are alternately input at a predetermined time period, the &#34;High&#34; signal indicative of the first field and the &#34;Low&#34; signal representative of the second field are alternately output at a preselected time period from the write field detecting circuit 7. In the case of either slow-mode reproduction or still-mode reproduction, a video signal in either a first field or a second field is continuously input. The &#34;High&#34; signals are continuously derived from the write field detecting circuit 7 when the video signal of the first field is repeatedly reproduced. In the case of either the slow-mode reproduction or the still-mode reproduction, when the video signal of the second field is repeatedly reproduced, the &#34;Low&#34; signals are continuously derived from the write field detecting circuit 7. In this case, a signal for sectioning one field is also derived at the same time. 
     The above-described field discriminating signal is supplied to an adder circuit 6 by which this field discriminating signal is added to the digital video signal obtained from the A/D converter 1, and the resultant added signal is supplied to a changeover switch 9. This changeover switch 9 is switched every one field. When the field discriminating signal is high during the normal or high-speed reproductions, for instance, this switch 9 is switched to a field memory 2A side, whereas during the slow-mode reproduction this switch 9 is switched to a field memory 2B side. 
     Where field discriminating signals having high levels are consecutively supplied during either slow-mode reproduction or still-mode reproduction, the changeover switch 9 is alternately switched to the side of the field memory 2A and the side of the field memory 2B for every one field. Similarly, when field discriminating signals having low levels are continuously supplied, the changeover switch 9 is alternately switched to the side of the field memory 2A and the side of the field memory 2B every one field. As described above, the video signals output from the adder circuit 6 are alternately written via the changeover switch 9 into the field memories 2A and 2B every one field. 
     On the other hand, as previously described, the input video signal is supplied to a write address controller 8 in which a clock synchronized with the video signal is produced. Then, the clock is supplied to the field memories 2A and 2B. As a result, the writing operations of the video signals in the field memories 2A and 2B are performed in synchronism with the input video signals. 
     As will be described later, the video signals which have been written into the field memories 2A and 2B are read out at the timing of a newly generated synchronization signal (sync signal). In other words, in a synchronization (sync) signal generating circuit 5, the normal sync signals, namely the sync signal in the first field and the sync signal in the second field, are alternately and repeatedly produced at a predetermined time period, and the normal sync signals are supplied to an address controller 10 in which a clock is produced in synchronism with the sync signal. This clock is supplied to the field memories 2A and 2B respectively, so that the video signals are read out in response to this clock in synchronism with the new sync signal. Thus, jitter in the input video signals can be absorbed. 
     The read video signals are supplied via a changeover switch 11 to a D/A converter 3. The changeover switch 11 is switched at the timing of the sync signal generated by the sync signal generating circuit 5. That is to say, both the sync signal in the first field and the sync signal in the second field, which are generated by the sync signal generating circuit 5, are supplied to a read field detecting circuit 12 from which a &#34;High&#34; signal is output in the case of the first field and a &#34;Low&#34; signal is output in the case of the second field. 
     Then, the changeover switch 11 is switched to the field memory 2A side when a &#34;High&#34; signal is supplied to this changeover switch 11. The changeover switch 11 is switched to the field memory 2B side when a &#34;Low&#34; signal is supplied to this switch 11. In other words, the changeover switch 11 is switched every one field. As a consequence, the video signal of the first field is read out in synchronism with the sync signal in the first field which is newly produced, and the video signal of the second field is read out in synchronism with the sync signal in the second field during the normal or high-speed reproduction. 
     During either slow-mode reproduction or still-mode reproduction, since the video signal in the same field has been stored in the field memories 2A and 2B, the video signal in the same field is read out in synchronism with the sync signal of the first field and the sync signal of the second field, which have been newly generated. The read video signals are D/A-converted by the D/A converter 3, and thereafter the D/A-converted video signals are supplied to a sync signal adding circuit 4. 
     Meanwhile, the sync signal of the first field and the sync signal of the second field, which have been generated in the sync signal generating circuit 5, are supplied to a sync signal control circuit 13. In this sync signal control circuit 13, as will be explained later, these sync signals of the first and second fields are converted into sync signals corresponding to the fields of the input video signal, and the converted sync signals are supplied to the sync signal adding circuit 4. 
     FIG. 5 represents a block diagram of the sync signal control circuit 13. The video signal output from the changeover switch 11 is supplied to a field discriminating signal detecting circuit 21 employed in the sync signal control circuit: 13, by which the field discriminating signal contained in the video signal is detected. Then, a switching signal which discriminates between normal or high-speed reproduction, a video signal of the first field for slow-mode reproduction or still-mode reproduction, and a video signal of the second field for slow-mode reproduction or still-mode reproduction. These switching signals are furnished to a switch 22. 
     When the switching signal indicates the normal or high-speed reproduction mode, a changeover switch 22 is switched to a terminal &#34;a&#34; of the normal or high-speed reproduction mode. When the switching signal represents the first field of either slow-mode reproduction or still-mode reproduction, the changeover switch 22 is switched to a terminal &#34;b&#34; of the first field. Furthermore, when the switching signal indicates the second field of either slow-mode reproduction or still-mode reproduction, the changeover switch 22 is switched to a terminal &#34;c&#34; of the second field. 
     The terminal &#34;a&#34; of the normal or high-speed reproduction mode is directly connected to the sync signal generating circuit 5, so that the sync signal generated in the sync signal generating circuit is directly output. That is, the sync signal of the first field and the sync signal of the second field are alternately derived from this terminal &#34;a&#34; in predetermined time periods. 
     The terminal &#34;b&#34; of the first field is connected via a first field converting circuit 23 to the sync signal generating circuit 5. As will be explained later, in the first field converting circuit 23, the sync signal of the first field is directly output, the sync signal of the second field is converted into a sync signal equivalent to that of the first field, and then the converted sync signal is output. 
     FIG. 6 represents the content of the processing operation performed in the first field converting circuit 23. It should be noted that a description will now be made of a case in which an input video signal corresponds to a television signal of the NTSC system. As shown in FIG. 6, the sync signal of the first field is directly output from this first field converting circuit 23. 
     As represented in FIG. 6(1), as to the sync signal of the second field, the vertical sync pulse is delayed by 0.5 H (symbol &#34;H&#34; indicates the horizontal scanning period) with respect to the first field. If the sync signal of the second field were to be directly added to the video signal, the image of the second field would be delayed by 1 H with regard to the image (indicated by a circle) of the first field. Therefore, as indicated by FIG. 6(2), the entire sync signal of the second field is shifted by 1 H in a backward direction. As a result, the image of the second field is located at the same position as the image of the first field. 
     However, under such circumstance, since the vertical sync pulse in the second field is shifted by 0.5 H with respect to the first field along the backward direction, the image in the first field would be overlapped by the image in the second field in a slightly shifted state. Accordingly, it may appear that the image is vibrating. To avoid this difficulty, as shown in FIG. 6(3), the vertical sync pulse is omitted, and subsequently a quasi-vertical sync pulse is inserted into the same position as the vertical sync pulse of the first field. 
     As a consequence, since the number of equalizing pulses in the second field present before the vertical sync pulse becomes 8, i.e., an even number, a judgement is made of the first field in the monitor 30, and then the same scanning line of the first field is traced. Thus, the image of the first field can be completely overlapped by the image of the second field. 
     In FIG. 5, the terminal &#34;C&#34; of the second field of the changeover switch 22 is connected via a second field converting circuit 24 to the sync signal generating circuit 5. In the second field converting circuit 24, as shown in FIG. 7, the sync signal of the second field is directly output, and the sync signal of the first field is converted into a sync signal equivalent to that of the second field, and then the converted sync signal is output. A description will now be made of the conversion operation for the sync signal in the second field in the NTSC system. 
     In FIG. 7, the sync signal of the first field indicated by FIG. 7(1) is first shifted by 1 H, as shown in FIG. 7(2), along the forward direction. This is because when the sync signal of the first field is added to the image of the second field, the image of the second field is 1 H earlier with respect to the image of the first field, contrary to the situation of FIG. 6. As a result, the image of the first field can be located at the same image position as that of the second field. 
     Under this condition, since the vertical synchronizing pulse of the first field is shifted by 0.5 H with respect to the second field, it may appear that the image is vibrating. To avoid such a difficulty, as indicated in FIG. 7(3), the vertical synchronizing pulses are omitted. Then, as shown in FIG. 7(4), a quasi-vertical sync pulse is inserted into the same position as the vertical synchronizing pulse of the second field. 
     Accordingly, since the number of equalizing pulses prior to the vertical synchronizing pulse becomes 5, namely an odd number, a judgement is made of the second field by the monitor 30, and the same scanning line of the second field is traced. Thus, the image of the first field can be completely overlapped by the image of the second field. 
     FIG. 8 represents a conversion process of the first field converting circuit 23 in the PAL system, whereas FIG. 9 indicates a conversion process of the second field converting circuit 24 in the PAL system. It should be understood that since the number of equalizing pulses and vertical synchronizing pulses contained in the sync signal of the PAL system is merely different from that of the NTSC system, and furthermore the conversion sequence of the PAL system is similar to that of the NTSC system, a description thereof is omitted in this specification. 
     As a consequence, as previously described, any one of a sync signal produced during the normal or high-speed reproduction modes, a sync signal of the first field produced during either slow-mode reproduction or still-mode reproduction, and a sync signal of the second field produced during either slow-mode reproduction or still-mode reproduction, is output from the changeover switch 22. The output sync signal is added to the video signal in the sync signal adding circuit 4, and the resultant video signal is supplied to an external signal processing circuit (not shown). 
     As previously explained in detail, in accordance with the present invention, for instance, when a video signal of a first field is repeatedly and continuously input during either slow-mode reproduction or still-mode reproduction, the sync signal of the first field can be added to all of the video signals by converting a sync signal of a second field into an equivalent sync signal to that of the first field. Also, for example, when a video signal of a second field is repeatedly and consecutively input during either slow-mode reproduction or still-mode reproduction, the sync signal of the second field can be added to all of the video signals by converting the sync signal of the first field into an equivalent sync signal to that of the second field. Then, when the video signal of the second field is repeatedly and continuously input, the synchronizing signal of the second field can be added to all of the video signals. Furthermore, when the video signal of the first field is repeatedly and continuously input, the sync signal of the first field can be added to all of the video signals. 
     As a consequence, if the present invention were to be applied to, for instance, a VTR and the like, when a video signal of either a first field or a second field is repeatedly and continuously reproduced during slow-mode reproduction or still-mode reproduction, and this video signal is supplied to the monitor, the video signal of the first field is necessarily traced along the scanning line of the first field, and also the video signal of the second field is necessarily traced along the scanning line of the second field. Accordingly, there is the advantage that images can be correctly reproduced.