Abstract:
A dynamically matched mixer system ( 200 ) for use in a direct conversion radio frequency (RF) receiver includes a frequency generator ( 201, 203, 205 ) that includes plurality of dividers ( 407 ) for providing differential local oscillator reference sources (F LO+  and F LO− ) and mitigation frequency reference sources (F 1  and F 2 ) from reference oscillator ( 205 ). A mixer ( 209 ) mixes the differential local oscillator reference sources (F LO+  and F LO− ) and the mitigation frequency reference sources (F 1  and F 2 ) while dynamic matching units ( 211, 213 ) are used for receiving the mitigation frequency reference sources and matching switching parameters of differential input signals (I RF+  and I RF− ) and differential baseband output signals (I BB+  and I BB− ). The frequencies of the mitigation frequency reference sources (F 1  and F 2 ) are selected so as to establish a non-integer relationship to the reference oscillator ( 201 ) for mitigating the occurrence of interference with F LO+  and F LO−

Description:
TECHNICAL FIELD  
       [0001]     This invention relates in general to radio frequency (RF) mixers and more particularly to a system and method for mitigating signal spur interference between input signals in an RF mixer.  
       BACKGROUND  
       [0002]     Present direct conversion receiver (DCR) architectures often incorporate a dynamically matched architecture that uses a single reference signal source which operates at two times the carrier frequency. This generates both the local oscillator (LO) signal and a mitigation frequency reference signal which is typically less than 300 MHz. To avoid “self quieting” interference between the LO and the mitigation signals as well as their harmonics, the mitigation frequency reference signal is generated by using odd integer dividers to generate odd integer sub-multiples of the voltage controlled oscillator (VCO) frequency. The LO frequency is generated by dividing down the VCO frequency by an even multiple for an even integer divider or by an odd multiple for an odd multiple divider. While this arrangement is typically used in DCR architectures, further optimization is necessary to provide margin to system receiver requirements such as terrestrial trunked radio (TETRA) blocking and frequency modulated digital private line (FM DPL) distortion mitigation. In-phase (I) and quadrature (O) matching directly influences sideband suppression which, in turn, directly affects the generation of sub-audible signaling distortion products. In addition, excessive I and Q mismatch can degrade second order intercept point (IP2) performance which bears directly on the receiver&#39;s interference blocking performance.  
         [0003]     Prior art dynamically matched mixer systems include U.S. Pat. No. 6,125,272 to Bautista et al. that teaches a method and apparatus for providing improved intermodulation distortion protection. U.S. Pat. No. 6,125,272 is herein incorporated by reference. The prior art techniques involve the use of dynamic matching to transform coefficients of the IM2 distortion from constant values into functions of time where they may be handled by known rejection techniques. This involves using odd and even integer dividers used to divide down from a single VCO source so that an even division multiple is used with the LO and the odd division multiple is used for quadrature generation. Thus, there is a finite point at which the divider multiple will create an even multiple mixed with the odd multiple causing a “spur” which self quiets the receiver. This relationship between even and odd frequency relationship can be a problem in this type of design. The system as defined by Bautista et al. limits the overall benefit of this dynamically matched mixer design since it decreases the receiver&#39;s IP2 performance by randomizing the second order distortion product. Thus, Bautista et al. fail to address system level implementation issues that can degrade I/Q channel matching due to mitigation coupling between the LO quadrature generation circuitry and reference signal mitigation circuitry.  
         [0004]     The prior art dynamically matched differential I channel mixer  100  is illustrated in prior art  FIG. 1 , where reference oscillator  101  and PLL  103  represent a phase locked loop that provides a stable radio frequency (RF) source at some predetermined frequency. The PLL  103  provides differential inputs to a plurality of frequency harmonic dividers namely N even  divider  105  and N odd  divider  107 . Each respective harmonic divider provides a means to provide an even or odd multiple harmonic frequency from the source provided by PLL  103 . The output of the N even  divider  105  provides local oscillator (LO) differential inputs (F LO+  and F LO− ) to a mixer  109  while the output of the N odd  divider  107  supplies a mitigation signal (F 1 ) to both the dynamic matching network  111  and the dynamic matching network  113 .  
         [0005]     As will be recognized by those skilled in the art, the mixer  109  is a standard Gilbert cell mixer which enables differential RF input signals (I RF + and I RF −) to be mixed with both the LO differential signal (F LO+  and F LO− ) and mitigation signal F 1 . The dynamic matching network  111  and dynamic matching network  113  are essentially a switching network. These switching networks switch between transistor components within the in-phase (I) or quadrature (Q) mixer branches so as to average imperfections in the mixer&#39;s components to provide substantially enhanced mixer linearity. A plurality of alternating current (AC) couplers  115 ,  116  are used to couple the mixer  109  and dynamic matching network  113  which helps to eliminate temperature compensating direct current (DC) mismatch, improves system common mode rejection of the dynamic mixer and eliminates the use of an 1/f noise adder by the LO. Finally, the differential baseband output signals (I BB + and I BB −) for either an in-phase or quadrature channel is provided at an output of the dynamic matching network  113 . As noted with other prior art designs, the circuit topology of prior art  FIG. 1  creates a spur which causes problems depending on what harmonics are used at the LO and the mitigation signal F 1 . As will be recognized by those skilled in the art, prior art  FIG. 1  shows a differential I-channel mixer while a differential Q-channel mixer will be similarly configured.  
         [0006]     Therefore, it would be advantageous to provide a system and method of using a dynamic matched mixer which provides improved second order intermodulation distortion (IP2) performance. It would also be advantageous to apply this system and method to wireless and wireline communications devices that employ mixer circuits, switches, and other components that exhibit parametric mismatch or imbalance.  
       SUMMARY OF THE INVENTION  
       [0007]     Briefly, according to the invention, there is provided a direct conversion receiver architecture incorporating a dynamically matched mixer where the local oscillator and mitigation signal frequency are generated from non-integer related sources. This can include either two independent frequency generation units or using a direct digital synthesizer (DDS) with multiple independent outputs derived from a digital-to-time converter. This enables a single high frequency and high stability reference oscillator to drive a series of delay line structures of sufficient quantity to provide resolution in generating the targeted frequency. The DDS with digital-to-time conversion provides performance benefits in terms of flexibility, signal quality, integration, die area and current drain. The advantages of the invention include eliminating the need for a single frequency generation unit (FGU) to drive both the LO and mitigation frequency reference sources, real time variation of mitigation frequency to eliminate interference and increased flexibility in the selection of the mitigation frequency relative to the LO. This allows fractional selection of the mitigation rate. The architecture incorporates a single high frequency reference for generating multiple frequency sources to drive a differential DCR mixing structure.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may best be understood by reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which:  
         [0009]      FIG. 1  is a prior art block diagram illustrating a dynamically matched balance mixer known in the prior art.  
         [0010]      FIG. 2  is a block diagram illustrating a dynamically matched mixer system according to the preferred embodiment of the invention.  
         [0011]      FIG. 3  is a block diagram shown a dynamically matched mixer system according to an alternative embodiment of the invention.  
         [0012]      FIG. 4  is a block diagram of a multiple frequency generation unit as utilized in the preferred embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0013]     While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures, in which like reference numerals are carried forward.  
         [0014]     Referring now to  FIG. 2 , the dynamically matched mixer system with improved I/Q balance and IP2 performance  200  includes a reference oscillator  201  coupled to a phase locked loop (PLL)  203  that generates a high frequency reference signal F ref . This F ref  signal provides an input to the direct digital synthesizer (DDS)  205 . The DDS  205  employs a delay locked loop that allows for the generation of multiple independent output frequencies, namely, differential local oscillator signals (F LO + and F LO −) and a first mitigation reference signal F  1  and a second mitigation reference signal F 2 . These outputs are non-integer related to one another and the F ref . The F ref  signal PLL  203  and the DDS  205  form a highly stable and versatile frequency generation unit (FGU). As compared with the typical PLL as shown in prior art  FIG. 1 , the DDS  205  operates to mitigate spur interference through the intelligent selection of the first mitigation frequency signal F  1  and the second mitigation frequency signal F 2 . This is accomplished by using a digital processing circuit ( FIG. 4 ) to select taps from a tapped delay line (not shown) in an organized manner such that the differential frequency signals (F LO + and F LO −), the first mitigation signal F 1  and the second mitigation signal F 2  are provided according to the following equations: 
 
 F   LO(+ and −)   =F   ref   /N 1 
 
 F   1 = F   ref   /N 2; and 
 
 F   2 = F   ref   /N 3 where N1, N2 and N3 are real numbers. 
 
         [0015]     As will be recognized by those skilled in the art, for direct conversion receiver (DCR) applications: 
 
 F   LO(+ or −)   =F   RF  and N3=N2; and 
 
         [0016]     Very Low Frequency Intermediate Frequency (VLIF) applications: 
        Where N3#N2 then 
 
 F   LO (+ or −)   =F   RF  then  F   VLIF =( F   2 − F   3 ); and 
 
 F   LO   ≠F   RF , then  F   VLIF   =+/−F   RF   −/+{F   LO +/−( F   2 − F   3 )}
       
 
         [0018]     The VLIF strategy is a specialized application of DCR where the RF, LO and mitigation frequencies are selected such that the output I BB+  and I BB−  are typically 100&#39;s of kHz. VLIF strategies are typically used in global system for mobile communication (GSM) receiver mixers where the receiving protocol does not utilize contiguous occupied channels. As is known in the art, the GSM protocol specifies that certain adjacent frequency channels may be “open” or unoccupied. Thus, the F LO +/− or a mitigation signal as described herein may be selected such that any spurious response falls in the unoccupied channel spectrum thus mitigating any undesired interference. This creates a great deal of extra flexibility in the intermediate frequency selection of the GSM mixer.  
         [0019]     As illustrated in  FIG. 2 , the dynamically matched mixer system  200  includes the differential local oscillator signals (F LO + and F LO −) that are provided to a mixer  209 . A first mitigation reference signal F 1  is supplied from the DDS  205  to the input dynamic matching network  211 . The dynamic matching network  211  provides a differential input signal (I RF + and I RF −) to the mixer  209  which is then coupled through AC couplers  215 ,  216  to the output dynamic matching network  213 . Similarly, a second mitigation reference signal F 2  is supplied from the DDS  205  to the output dynamic matching network  213 . The differential output signals (I BB + or I BB −) of the output dynamic matching network  213  represent either an in-phase or quadrature baseband output signal depending upon which type of mixer is used for the representative digital channel.  
         [0020]      FIG. 3  illustrates a block diagram of the dynamically matched mixer system  300  according to an alternative embodiment of the invention. As noted in  FIG. 2 , the reference oscillator (F ref )  205 , the PLL  203  and the DDS  205  work to provide a differential local oscillator signal (F LO + and F LO −) as well as a mitigation signal F  1 . This embodiment differs from that of  FIG. 2 , through the use of a state selection manager  301 . The state select manager  301  operates to control the input dynamic matching network  211  in order to preset the state of the switch to a “low” or “high” state. This fixes the state of the switch without any time dependence that would occur with the use of a mitigation signal. The use of the state select manager  301  permits the input signal to no longer be dynamically matched to the input stage to the mixer  209 . This operationally simplifies the dynamically matched mixer system  300  by minimizing the spurious signal contributions of the input dynamic matching network  211  and improving overall IP2 performance over that achieved using a classic single mixer topology. Thus, the embodiment as shown in  FIG. 3  while using only one switching network, namely, output dynamic switching network  213 , allows substantially the similar performance to the dual switching network topology shown in  FIG. 2  if the local oscillator frequency (F LO + and F LO −) and mitigation signal frequency (F 1 ) are carefully selected.  
         [0021]      FIG. 4  illustrates a block diagram showing details of a multiple frequency generation unit (FGU)  400  used in accordance with the dynamic match mixers as describer herein. As illustrated in  FIGS. 2 and 3 , a reference oscillator  201  supplies a reference signal to a voltage controlled oscillator (VCO) which is a high stable PLL oscillator producing an F ref  signal. The F ref  is supplied to the direct digital synthesizer (DDS)  205 . The DDS  205  is comprised of a digital processor  407  and a digital-to-time converter  409 . The multiple frequency generation unit  400  utilizes a DDS synthesizer  205  where each output (F 1  to FN) is independent yet is derived from a signal high frequency reference (F ref ). A principal benefit of this topology is that only the single VCO  203  is required. An output signal is constructed when the digital processor  407  selects taps from the digital-to-time converter  409  which is a tapped delay line. The use of this system and method of frequency generation yields a number of benefits, namely, high frequency resolution, broad frequency tuning range and low current drain, as compared with other DDS synthesizers. Moreover, there is a phase coherent relationship between the differential local oscillator frequency (F LO + and F LO −) and the mitigation signal frequency (F 2 ) and there is an ability to phase shift the output of the DDS  205  relative to one another. The DDS  205  also enables the system to provide both quadrature and differential signals. Finally, a major benefit in using the DDS  205  is spur mitigation through the intelligent selection of the mitigation frequency signal (F 2 ).  
         [0022]     Thus, the present invention provides a fractional non-harmonic frequency generation architecture with independent mitigation and LO frequency paths. The non-harmonic fractional relationship between the mitigation and LO frequencies enhances I/Q matching and IP2 performance over a wide range of RF bandwidths. The digital nature of the frequency synthesizer allows for “dithering” or spreading capabilities of the mitigation frequency to reduce discrete harmonic spurious content that would otherwise be mixed into the base band signal. Moreover, agile interference rejection enhancement allows very fast adjustment of the mitigation frequency in real time relative to the LO. Hence, spurious interference can be detected, e.g., degraded bit error rate (BER) in strong signal conditions where the mitigation frequency can be adjusted to a new frequency unrelated to the local oscillator while still receiving the desired signal in an attempt to eliminate the interference.  
         [0023]     While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not so limited. Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.