Abstract:
A voltage reference source is provided that includes a Brokaw bandgap core comprising a first set of transistors, a second set of transistors coupled to the first set of transistors and serving as load devices to the first set of transistors, and a dynamic element matching circuit coupled to the first and second sets of transistors so as to cancel the offset and noise produced by a selective number of the second set of transistors.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The invention is related to the field of electronic circuitry, and in particular to a bandgap voltage reference with dynamic element matching. 
         [0002]    A Brokaw bandgap reference circuit is a voltage reference circuit widely used in integrated circuits, with an output voltage around 1.25 V with little temperature dependence. Like all temperature-independent bandgap references, the circuit maintains an internal voltage source having a positive temperature coefficient and another internal voltage source that has a negative temperature coefficient. By summing the two together, the temperature dependence can be canceled. Additionally, either of the two internal sources can be used as a temperature sensor. 
         [0003]    The Brokaw bandgap reference circuit uses negative feedback (with an operational amplifier) to force an identical current through two bipolar transistors with different emitter areas. The transistor with the larger emitter area requires a smaller base-emitter voltage for the same current. The base-emitter voltage for either transistor has a negative temperature coefficient (i.e. value decreases with temperature). The difference between the two base-emitter voltages has a positive temperature coefficient (i.e. value increases with temperature). 
         [0004]    To take full advantage of the low noise and high accuracy of the Brokaw circuit, an amplifier that uses both PNP and NPN type bipolar transistors is required. In a modern CMOS integrated circuit process, the NPN bipolar device can be fabricated, but not the PNP bipolar device. Therefore, there is a need to provide a low-noise, high-accuracy bandgap reference using the Brokaw core without using any PNP bipolar transistors. Furthermore, the reference should use as few current paths as possible, to minimize power consumption. 
       SUMMARY OF THE INVENTION 
       [0005]    According to one aspect of the invention, there is provided a voltage reference source. The voltage reference source includes a Brokaw bandgap core comprising a first set of transistors. A second set of transistors is coupled to the first set of transistors. The second set of transistors serves as load devices to the first set of transistors. A dynamic element matching circuit is coupled to the first and second sets of transistors so as to cancel offset and noise produced by a selective number of the second set of transistors. 
         [0006]    According to another aspect of the invention, there is provided a method of providing a reference voltage. The method includes arranging a first set of transistors in a Brokaw bandgap core arrangement. Also, the method includes selectively coupling a second set of transistors to the first set of transistors. The second set of transistors serves as load devices to the first set of transistors. The selectively coupling step decrease offset and noise produced by a selective number of the second set of transistors. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a circuit diagram illustrating a modified Brokaw bandgap reference circuit with PMOS active load and common-source amplifier in accordance with the invention; 
           [0008]      FIG. 2  is a circuit diagram illustrating another embodiment of the modified Brokaw bandgap reference circuit with PMOS active load and common-source amplifier and a dynamic element matching in accordance with the invention; 
           [0009]      FIGS. 3A-3C  are graphs illustrating the effect of the dynamic element matching; and 
           [0010]      FIG. 4  is a circuit diagram illustrating an embodiment of the dynamic element matching circuit shown in  FIG. 2  in accordance with the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0011]    The invention involves a bandgap voltage reference circuit based on the Brokaw bandgap reference circuit. This reference circuit can be implemented using PMOS transistors as the load devices. The technique of dynamic element matching is used to cancel the offset of these PMOS transistors. 
         [0012]      FIG. 1  shows an exemplary embodiment of the bandgap voltage reference circuit  2  in accordance with the invention. The bandgap voltage reference circuit  2  includes a Brokaw bandgap core  20 , where the Brokaw bandgap core  20  includes bipolar transistors qn 0  and qn 1  operated at different current densities, a resistive element (such as a resistor) R 2  coupled between the emitters of the bipolar transistors qn 0  and qn 1 , and a resistive element (such as a resistor) R 1  coupled between the emitter of the bipolar transistor qn 0  and ground. The bandgap voltage reference circuit  2  further includes a PMOS device mp 0  having its gate and drain coupled to the collector of bipolar transistor qn 0 , a PMOS device mp 1  having its gate coupled to the drain and gate of PMOS device mp 0  and drain coupled to the collector of the bipolar transistor qn 1 , and a PMOS device mp 3  having its gate coupled to the drain of PMOS mp 1  and collector of bipolar transistor qn 1 . The bases of bipolar transistors qn 0 , qn 1  and the drain of PMOS device mp 3  are coupled to the voltage source Vref. The sources of PMOS devices mp 0 , mp 1 , mp 3  are coupled to the voltage source AVDD. Please note the Brokaw bandgap core  20  shown in  FIG. 1  is only an embodiment rather than a limitation; that is, other Brokaw bandgap structures can also be utilized and similar results can be achieved. For example, a resistive element may be added between the gates of the bipolar transistors qn 0  and qn 1 . 
         [0013]    The bandgap voltage reference circuit  2  provides the basis for a voltage reference. The conventional 8:1 ratio of emitter areas can be used due to the convenience of laying out this ratio in a common-centroid 3×3 array. Compared with the conventional Brokaw bandgap reference circuit which couples resistors to the collectors of bipolar transistors qn 0  and qn 1 , the bandgap voltage reference circuit  2  using PMOS devices mp 0  and mp 1  as an active load uses no PNP bipolar transistors and fewer current paths. The PMOS device mp 3  supplies the base currents to bipolar transistors qn 0  and qn 1 , and can be regarded as a common-source stage providing enough gain and current drive to the core  20 . The common-source stage may be sized to supply the base current if the gate voltages of transistors qn 0  and qn 1  are balanced under nominal conditions. 
         [0014]      FIG. 2  shows another exemplary embodiment of a bandgap voltage reference circuit  4  where a dynamic element matching circuit  6  is used. The bandgap voltage reference circuit  4  includes a Brokaw bandgap core  12 , a dynamic element matching circuit  6 , and a load stage including PMOS devices mp 0  and mp 1 . The PMOS device mp 0  having its gate coupled to the collector of bipolar transistor qn 0 , and its drain selectively coupled to the collector of bipolar transistor qn 0  or the collector of bipolar transistor qn 1 , depending on the operation of the dynamic element matching circuit  6 . The gate of the PMOS device mp 1  is coupled to the gate of PMOS device mp 0 . The drain of PMOS device mp 1  is selectively coupled to the collector of bipolar transistor qn 0  or the collector of bipolar transistor qn 1 , depending on the operation of the dynamic element matching circuit  6 . The gate of a PMOS device mp 3  is coupled to the collector of bipolar transistor qn 1 , providing gain and current drive to the core  12 . The gates of bipolar transistors qn 0 , qn 1  and the drain of PMOS device mp 3  are coupled to the voltage source Vref and resistor Resd. The sources of PMOS devices mp 0 , mp 1 , mp 3  are coupled to the voltage source AVDD. The emitter of bipolar transistor qn 1  is coupled to one terminal of a resistor R 2  and the emitter of bipolar transistor qn 0  is coupled to resistor R 1  and another terminal of the resister R 2 . The resistor R 1  is coupled between the resistor R 2  and ground. A capacitance element Cext is coupled to Vref and resistor Resd. 
         [0015]    The dynamic element matching circuit  6  includes switches  8 ,  10 . The switches  8  are controlled by a clock signal Φ 1 , and the switches  10  are controlled by another clock signal Φ 2 . The clock signals Φ 1  and Φ 2  are non-overlapped. When the switches  10  are closed by control signal Φ 1 , the switches  8  are open, and the bandgap voltage reference circuit  4  is similar to the structure  2  of  FIG. 1  (the PMOS device mp 0  is coupled to the bipolar transistor qn 0 , while the PMOS device mp 1  is coupled to the bipolar transistor qn 1 ). When the switches  10  are open and the switches  8  are closed by the clock signals, the drain of PMOS device mp 0  is coupled to the collector of bipolar transistor qn 1 , and the drain of PMOS device mp 1  is coupled to the collector of bipolar transistor qn 0 , i.e., the connection relationship between the PMOS devices and bipolar transistor devices are swapped. 
         [0016]    The PMOS active load is retained with the addition of the dynamic element matching circuit  6  that nulls out the offset and 1/f noise of mp 0  and mp 1 , as shown in  FIG. 2 . The dynamic element matching circuit  6  effectively swaps the position of mp 0  and mp 1  in the circuit topology once per clock cycle during phases Φ 1  and Φ 2 . However, this is not meant to be a limitation; for example, the swapping cycles may be various and not exactly identical to one clock cycle of the clock signals Φ 1  and Φ 2 . Since PMOS devices mp 0  and mp 1  operate under the same nominal Vgs, Vds and Id, the disturbance generated is minimal when the PMOS devices mp 0  and mp 1  are matched. If the PMOS devices mp 0  and mp 1  are mismatched, an AC current is injected onto the gate of PMOS device mp 3 . As will be shown, this bandgap voltage reference circuit  4  has two low-frequency poles (and one low-frequency zero). The AC current that results from PMOS offset is filtered once by the pole resulting from the capacitance at the gate of PMOS device mp 3  and again by the pole resulting from the series combination of the resistor Resd and the capacitor Cext at the output of the bandgap voltage reference circuit  4 . As a result, the upmixed spur from the offset undergoes second-order filtering. Choosing a relatively high modulation frequency can further ensure that this spur is filtered down to an insignificant level. 
         [0017]    In other embodiments of the invention, other transistor elements besides PMOS and bipolar transistors can be used that exhibit similar properties without deviating from the basic concept of the invention. 
         [0018]      FIG. 3A-3C  illustrate the effects of dynamic element matching within the bandgap voltage reference circuit  4 . A reference with a 5 mV offset between mp 0  and mp 1  is simulated, clocked at 1.8 MHz.  FIG. 3A  shows the output reference voltage Vref, which appears clean—at least the ripple is small compared to a 100 nV grid spacing.  FIG. 3B  shows the reference voltage measured internal to the Resd resistor. The effect of the dynamic element matching current through the PMOS device mp 3  can be observed due to the voltage drop across the Resd resistor.  FIG. 3C  shows voltages at the collectors of qn 0  (vc 0 ) and qn 1  (vc 1 ). The voltage at vc 0  is a square wave with an amplitude of 5 mV, reflecting the offset. The voltage at vc 1  is a triangle wave, showing that the error current generated by dynamic element matching circuit  6  is integrated on the gate of mp 3 . 
         [0019]    The dynamic element matching circuit  6  of  FIG. 2  cancels the DC error due to PMOS offset to first order, and modulates the 1/f noise of the PMOS devices mp 0  and mp 1  to the modulation frequency in the same way that it upmixes offsets. Since noise at the modulation frequency is highly filtered, overall noise is reduced at low frequencies, and largely insignificant at frequencies over about 1 kHz. 
         [0020]      FIG. 4  describes an embodiment of the dynamic element matching circuit. The dynamic matching circuit  21  includes a PMOS device mp 1  whose gate is coupled to the gate of PMOS device  24 . The gates of PMOS devices  22  and  24  are coupled to a voltage source phi 1  corresponding to the clock signal Φ 1 . The drains of PMOS devices  22  and  28  are coupled to node c 0 . The drains of PMOS devices  24  and  26  are coupled to node c 1 . The gates of PMOS devices  26  and  28  are coupled to a voltage source phi 2  corresponding to the clock signal Φ 2 . The sources of PMOS devices  22  and  26  are coupled to node d 0 . The sources of PMOS devices  24  and  28  are coupled to node d 1 . 
         [0021]    When the dynamic matching circuit  21  is implemented within the bandgap voltage reference circuit  4 , for example, the collector of bipolar transistor qn 0  is coupled to the node c 0 , the collector of bipolar transistor qn 1  is coupled to the node c 1 , the drain of the PMOS device mp 0  is coupled to the node d 0 , and the drain of the PMOS device mp 1  is coupled to the node d 1 . In this way, the connection relationship between the PMOS devices mp 0  and mp 1  and the bipolar transistors qn 0  and qn 1  are swapped during the first phase and the second phase. This configuration decreases or removes DC error due to PMOS offset to first order, and modulates the 1/f noise of the PMOS devices mp 0  and mp 1 . 
         [0022]    Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.