Abstract:
A method of arbitration among a plurality of n units which seek access to a resource is regulated according to grants identified by means of an arbitration method, which compares between one another the priorities, generating, for each pair of the units comprising in general a unit x and a unit y with respective priorities Px and Py, a selection signal at a high level if the result of the operation Px&gt;=Py is true. The method generates, for the pairs of the units, respective cross-request signals and generates the grant for the ith unit as a logical product of all the cross-request signals req i x with x ranging from 1 to n, excluding the case of x=i.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to arbitration techniques implemented in the framework of information-processing systems.  
         BRIEF DESCRIPTION  
         [0002]    The increasing complexity in terms of architecture of information-processing systems, and in particular of the so-called “embedded” systems, renders increasingly more important the optimization of the cycles of transfer of data flow from the so-called “initiators” to the so-called “targets” of a system.  
           [0003]    In general, the definition of initiator applies to any unit that is able to initiate autonomously a transaction such as to involve the use of a resource (for instance, a dedicated or shared bus) in order to read or write data.  
           [0004]    The definition of target applies to any unit starting from which or with which an initiator is able to read or write data.  
           [0005]    A system such as an embedded system may have a large number of initiator units, as well as a large number of target units.  
           [0006]    At the moment in which two or more initiators simultaneously endeavor to start a transaction aimed at an identical target, it is necessary to solve the conflict by means of an arbitration function. The implementation of such a function may often prove burdensome, in particular in terms of speed of execution.  
           [0007]    [0007]FIG. 2 of the annexed drawings shows an arbitration procedure carried out according to a solution known in the art within the framework of a generic system (for example, of the embedded type), represented in FIG. 1, a figure which in itself applies both to the prior art and to the invention.  
           [0008]    At the start of the respective transaction, each initiator I 1 , I 2 , I 3 , etc., presents a priority to the so-called system arbiter A, which solves the conflict by enabling start of the transactions by the initiators having the highest priority and proceeding progressively down to the ones with the lowest priority. Data transactions towards any target T are thus regulated by the arbiter A, which solves the possible conflicts by means of the priority information supplied by the initiators themselves. A transaction consists in the transfer of a data packet from the initiator involved to the target T or vice versa.  
           [0009]    At the start of transaction, each initiator I 1 , I 2 , I 3 , etc., asserts a request signal to the arbiter A. The arbiter signals that the transaction has been accepted by means of a grant signal asserted to the initiator with the highest priority among the ones that wish to start the transaction simultaneously. Then it signals, in the subsequent cycles, acceptance of the transactions to the initiators having lower priorities when the transactions having higher priorities have been completed.  
           [0010]    This procedure is shown schematically in FIG. 2 with reference to a system comprising three initiators I 1 , I 2 , I 3  and a target T. The arbiter A, which operates according to the clock signal represented in the diagram at the top of FIG. 2, solves any conflicts on the basis of the priorities received with the timings shown in the FIG. All this is done by applying basically a mechanism of comparison of inequalities in sequential order, as represented in FIG. 2. Here, it is assumed that initiator I 1  has a higher priority than initiator I 2 , which in turn has a higher priority than initiator I 3 , so that grants are granted in order first to initiator I 1 , then to initiator I 2 , and finally to initiator I 3 .  
           [0011]    Albeit functional, the mechanism described above presents intrinsic limits related to the speed of execution of the arbitration algorithm, to the sensitivity of the speed of execution of arbitration according to the coding of the priority (typically on a generic number n of bits), and to a marked increase in the execution delay as the number of initiators increases.  
         SUMMARY OF THE INVENTION  
         [0012]    An embodiment of the present invention provides a solution that is able to overcome the drawbacks referred to above.  
           [0013]    The arbitration procedure according to an embodiment of the invention is basically a variable-priority arbitration mechanism that can be used advantageously in high-speed applications, such as in decoders for high-definition television signals. The corresponding interconnection subsystem, comprising three initiators or requesters (LMI, up-Interface, and GPx Interface units) and a target T (the SDRAM memory interface), is able to operate with a clock signal, for example, at 100 MHz. The solution makes it possible to differentiate processes having different priorities, which can access the external SDRAM through the same initiator.  
           [0014]    In general, the solution may, however, be used in NxM systems (i.e., with N initiators and M targets) by introducing an arbiter for each destination. The time of execution of the procedure increases only as a result of the decoding of the destination address; hence—referring to current technologies (such as 0.25-micron technology)—with values of a few tenths of nanoseconds for each destination. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    The invention will now be described, purely to provide a non-limiting example, with reference to the attached drawings in which:  
         [0016]    [0016]FIGS. 1 and 2, the latter referring specifically to the prior art, have already been described previously; and  
         [0017]    [0017]FIG. 3 illustrates, in the form of a block diagram, the possible architecture of an arbitration system operating according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]    An embodiment according to the invention is designed to operate in a situation which—as regards the aspects of a general nature—corresponds to the solution represented in FIG. 1.  
         [0019]    Specifically, the block diagram of FIG. 3 represents the architecture of the arbiter A which can be adopted for implementing an embedded system in which three initiators I 1 , I 2  and I 3  designed to access a single target T are present.  
         [0020]    In practice, the architecture of the arbiter represented in FIG. 3 comprises three stages, designated by A 1 , A 2 , and A 3 , and designed to perform in a staggered arrangement three successive steps of the arbitration procedure.  
         [0021]    The above-mentioned steps (and consequently the corresponding stages A 1 , A 2 , and A 3 ) may be generally identified as:  
         [0022]    comparison of priorities (stage A 1 );  
         [0023]    cross generation of requests (stage A 2 ); and  
         [0024]    cross generation of grants (stage A 3 ).  
         [0025]    Each of the stages A 1 , A 2 , and A 3  in turn comprises three modules or blocks that are substantially identical to each other.  
         [0026]    The three blocks of stage Al, designated by A 11 , A 12 , and A 13 , receive as their inputs the priority signals or data corresponding to a respective pair of initiators; these are (in the embodiment illustrated), in order, the pair I 1 , I 2 , the pair I 1 , I 3 , and the pair I 2 , I 3 .  
         [0027]    The respective output signals are sent, in order, to the modules of stage A 2 , designated A 21 , A 22 , and A 23 . The latter receive, respectively and in order, also the request signals generated by the initiators of the pair I 1 , I 2 , of the pair I 1 , I 3 , and of the pair I 2 , I 3 .  
         [0028]    Each of the modules A 21 , A 22 , and A 23  generates as its output two crosstype request signals designed to be sent on to the three modules of stage A 3 , designated in order by A 31 , A 32 , and A 33 .  
         [0029]    In particular, of the two outputs of the module A 21 , one is sent to the module A 31  and the other to the module A 32 . Of the two outputs of the module A 22 , one is sent to the module A 31  and the other to the module A 33 . Finally, of the two outputs of the module A 23 , one is sent to the module A 32  and the other to the module A 33 .  
         [0030]    The output signals of the modules A 31 , A 32 , and A 33  constitute the grant signals that represent the result of the arbitration procedure and are designed to be assigned, respectively, to the initiator I 1 , to the initiator I 2 , and to the initiator I 3 .  
         [0031]    In the sequel of the present description, the arbitration procedure according to the invention will, however, be illustrated referring, in general terms, to the generic presence of N initiators or requestors.  
         [0032]    Stage No. 1: Comparison  
         [0033]    Assuming that there are N requesters, and that associated to the ith requestor is the priority Pi (for example, P1 is the priority of the requestor  1 ), the following operations are performed in parallel:  
         [0034]    P1&gt;=P2 (generates the signal sel  1  not  2 , high if the result of the operation is true)  
         [0035]    p1&gt;=P3 (generates the signal sel 1 not 3 )  
         [0036]    P1&gt;=Pn (generates the signal sel 1 notn)  
         [0037]    P2&gt;=P3 (generates the signal sel 2 not 3 )  
         [0038]    P2&gt;=P4 (generates the signal sel 2 not 4 )  
         [0039]    P2&gt;=P3 (generates the signal sel 2 notn)  
         [0040]    Pn−1&gt;=Pn (generates the signal sel 1 n- 1 notn)  
         [0041]    Hence, in general terms, for each pair of requestors, identified in general as x and y, the stage A 1  generates the signal selxnoty at a high level if it is true that Px&gt;=Py.  
         [0042]    For Example  
         [0043]    1. with 2 requesters: P1&gt;=P2 (1 comparator)  
         [0044]    2. with 3 requesters: P1&gt;=P2, P1&gt;=P3, P2&gt;=P3 (3 comparators)  
         [0045]    3. with 4 requestors: P1&gt;=P2, P1&gt;=P3, P1&gt;=P4, P2&gt;=P3, P2&gt;=P4, P3&gt;=P4 (6 comparators)  
         [0046]    4. with 6 requestors: P1&gt;=P2, P1&gt;=P3, P1&gt;=P4, P1&gt;=P5, P1&gt;=P6, P2&gt;=P3, P2&gt;=P4, P2&gt;=P5, P2&gt;=P6, P3&gt;=P4, P3&gt;=P5, P3&gt;=P6, P4&gt;=P5, P4&gt;=P6, P5&gt;=P6 (total 15 comparators)  
         [0047]    5. with n requesters: (total=1+2+3+4+. . . n−2+n−1, which, setting y=n−1 means total=(y/2* (y+1)) comparators  
         [0048]    In a preferred way, all the comparisons are performed simultaneously, and their complexity depends on the priority range. For example, in a high-definition TV decoder the priority range may be between 0 and 15.  
         [0049]    Stage No. 2: Cross Generation of Requests  
         [0050]    This stage uses the requests coming from the initiators and the results coming from the comparators of the stage upstream so as to calculate intermediate parameters that are useful for the generation of the grants.  
         [0051]    In particular, the following function is implemented: req_arb (selxnoty, req_x, req_y, req_x_y, req y x), where req_x (respectively req_y) is the request coming from the initiator x (respectively y), whilst req_x_y and req_y_x are, respectively, the outputs of the functions:  
         [0052]    req_x_y=req_x AND (selxnoty OR NOT req_y), and  
         [0053]    req_y_x=req_y AND (NOT selxnoty) OR (NOT req_x)).  
         [0054]    In practice, req_arb corresponds to a three-input and two-output module:  
         [0055]    req_arb (INPUTS: selxnoty, reqx, reqy  
         [0056]    OUTPUTS: reqx_y, reqy_x)  
         [0057]    This performs an arbitration function between the pairs of requests reqx, reqy (in the example illustrated in FIG. 3: req 1 , req 2 , or req 1 , req 3 , or again req 2 , req  3 ), the result having a coding of the one-hot type, ie., of the type in which there are n results representable using n binary figures; in the present case  01  or  10 .  
         [0058]    The result of such an operation depends on the following factors:  
         [0059]    i) priority of reqx with respect to reqy: reqx having a higher priority than reqy when selxnoty is at a high logic level, and vice versa, when it is at a low logic level;  
         [0060]    ii) presence of the requests: the decision is affected by the actual presence of requests; in fact, even in the situation in which selxnoty is at a high logic level, reqy could be served (this being only an intermediate result) in the absence of reqx.  
         [0061]    Consequently:  
         [0062]    the output reqx_y will be at a high logic level (certainly reqx is to be privileged with respect to reqy) when the signal reqx is at a high logic level (presence of the request) and, at the same time, when reqx has the higher priority with respect to reqy (selxnoty at a high logic level) or when reqy is at a low logic level (absence of request);  
         [0063]    the output reqy_x will be at a high logic level (certainly reqy is to be privileged with respect to reqx) when the signal reqy is at a high logic level (presence of the request) and, at the same time, when reqy has the higher priority with respect to reqx (selxnoty at a low logic level) or when reqx is at a low logic level (absence of request).  
         [0064]    In all, y/2*(y+1) req_arb modules will be required.  
         [0065]    Stage No. 3: Cross Generation of Grants  
         [0066]    Once the requests have been re-ordered, the final operation consists in the generation of the grants.  
         [0067]    For each ith requestor, the grant_i is simply obtained by operating the logical AND among all the signals req_i_x, with x ranging from 1 to N, excluding the case ofx=i.  
         [0068]    Examples  
         [0069]    a) 3 requestors  
         [0070]    Stage 1:  
         [0071]    Calculation in parallel of  
         [0072]    P1&gt;=P2,P1&gt;=P3,P2&gt;=P3  
         [0073]    Stage 2:  
         [0074]    Calculation in parallel of  
         [0075]    req_arb(P1&gt;=P2, req 1 , req 2 , req 1 _ 2 , req 2 _ 1 )  
         [0076]    req_arb(P1&gt;=P3, req 1 , req 3 , req 1 _, req 3 _ 1 )  
         [0077]    req_arb(P2&gt;=P — 3, req 2 , req_ 3 , req 2_3, req3_2)    
         [0078]    Stage 3:  
         [0079]    grant 1 =req 1 _ 2  AND req 1 _ 3   
         [0080]    grant 2 =req 2 _ 1  AND req 2 _ 3   
         [0081]    grant 3 =req 3 _ 1  AND req 3 _ 2   
         [0082]    b) 4 Requestors  
         [0083]    Stage 1:  
         [0084]    Calculation in parallel of  
         [0085]    P1&gt;=P2, P1&gt;=P3, P1&gt;=P4, P2&gt;=P3, P2&gt;=P4, P3&gt;=P4  
         [0086]    Stage 2:  
         [0087]    Calculation in parallel of  
         [0088]    req_arb(P1&gt;=P2, req 1 , req 2 , req 1 _ 2 , req 2_1)    
         [0089]    req_arb(P1&gt;=P3, req 1 , req 3 , req 1 _ 3 , req 3 _ 1 )  
         [0090]    req_arb(P1&gt;=P4, req 1 , req 4 , req 1 _ 4 , req 4 _ 1 )  
         [0091]    req_arb(P2&gt;=P3, req 2 , req 3 , req 2 _ 3 , req 3 _ 2 )  
         [0092]    req_arb(P2&gt;=P4, req 2 , req 4 , req 2 _ 4 , req 4 _ 2 ) req_arb(P3&gt;=P4, req 3 , req 4 , req 3 _ 4 , req 4 _ 3 )  
         [0093]    Stage 3:  
         [0094]    grant 1 =req 1 _ 2  AND req 1 _ 3  AND req 1 _ 4   
         [0095]    grant 2 =req 2 _ 1  AND req 2 _ 3  AND req 2 _ 4   
         [0096]    grant 3 =req 3 _ 1  AND req 3 _ 2  AND req 3 _ 4   
         [0097]    grant 4 =req 4 _ 1  AND req 4 _ 2  AND req 4 _ 3   
         [0098]    In brief, the described embodiment of the invention enables a faster execution of the variable-priority arbitration algorithm. All this in a situation in which the time of execution is not very sensitive to coding of priority. In addition, the time of execution of the arbitration is not strongly influenced by the number of initiators. The implementation is of a modular type, whereby the elements that distinguish it (see diagram of FIG. 3) can be replicated to implement arbiters with a generic number n of choices.  
         [0099]    For example, experiments conducted by the present applicant have shown that, in the case of an embedded system with 9 initiators in 0.25-micron technology, the time of generation of the grants with respect to the requests is 3 nanoseconds.  
         [0100]    Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what is described and illustrated herein, without thereby departing from the scope of the present invention as defined in the annexed claims.