Abstract:
A method for measuring quality of a stream of data, which was transmitted in accordance with a transmit clock, the method consisting of generating samples of the stream of data at sample times determined in accordance with a receive clock, and averaging values of the samples so as to generate a metric indicative of the quality of the stream of data. The receive clock is characterized as operating independently of the transmit clock.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit of U.S. Provisional Patent Applications No. 60/341,525, filed Dec. 17, 2001 and 60/345,483, filed Jan. 3, 2002, which are incorporated herein by reference. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates generally to data communication, and specifically to converting between serial and parallel data.  
         BACKGROUND OF THE INVENTION  
         [0003]    Conversion of parallel data to serial data, termed serialization, and the converse operation, deserialization, are required for many data communication processes. The parallel data is generated on a bus, and is converted to serial data for transmission on one channel. As busses increase in width, typical busses having 64 lines or even more, the speed at which data which has been serialized needs to be transmitted must of necessity increase, to avoid data build-up at the serializer interface. Serial data rates of Gigabits/s are typically required to avoid the build-up. Multichannel SERDES (serializer-deserializer) devices comprise multiple serializers each having a serializer interface. Each interface generates a channel of serial data which is then transmitted to a receiver.  
           [0004]    Recovery of such high speed multichannel serialized data presents considerable problems at the receiver. In systems known in the art a clock is recovered for each channel of the received data, and each clock is used to sample the received data. Typically, each recovered clock is locked to its own phase locked loop (PLL) oscillator. Furthermore, multiple sampling PLL clocks require respective elastic buffers for storing the sampled data, and there is typically an extra PLL clock for synchronizing all the sampling clocks to a common local clock.  
           [0005]    However, each PLL may suffer from its own jitter, since it is locked to incoming data; in addition, problems are caused by the multiplicity of PLL clocks. The PLL is a highly sensitive circuit, so that in layout of a device having PLLs, each PLL is, for example, isolated as much as possible and has its own ground and supply lines. Devices requiring multiple PLL oscillators thus require more area and more pins, and typically give lower yields because one PLL failure causes device failure.  
           [0006]    Data which is initially in an 8-bit ( 8   b ) form is typically encoded at the transmitter into an alternative form so that errors in the received data may be detected. An IEEE standard 802.3 z, published by the Institute of Electronic and Electrical Engineers, New York, N.Y., describes an  8   b / 10   b  coding scheme, originally developed by IBM Corporation. Using the scheme, a transmitter maintains a table having a one-to-two correspondence, so that each  8   b  word may be transmitted as one of two  10   b  words. Each  10   b  word in the table has between 4 and 6 ones (and correspondingly 6 and 4 zeroes). A partial list of  8   b  and corresponding  10   b  words, according to the scheme, is shown in Table I below.  
                               TABLE I                               First   Second   Running           Decimal   mapping B1   mapping B2   Disparity       8-bit word   value   (RD−)   (RD+)   (RD)                   00000000    0   100111 0100   011000 1011   same       00000001    1   011101 0100   100010 1011   same       00000010    2   101101 0100   010010 1011   same       00000011    3   110001 1011   110001 0100   switch       00000100    4   110101 0100   001010 1011   same       00000101    5   101001 1011   101001 0100   switch       00000110    6   011001 1011   011001 0100   switch       00000111    7   111000 1011   000111 0100   switch       00001000    8   111001 0100   000110 1011   same       00001001    9   100101 1011   100101 0100   switch       . . .   . . .   . . .   . . .   . . .       10111100   188   001110 1010   001110 1010   same       10111101   189   101110 1010   010001 1010   switch       . . .   . . .   . . .   . . .   . . .       11000100   196   110101 0110   001010 0110   switch       . . .   . . .   . . .   . . .   . . .       11100100   228   110101 0001   001010 1110   same       . . .   . . .   . . .   . . .   . . .       11111111   255   101011 0001   010100 1110   same                  
 
           [0007]    A complete listing of Table I comprises 256 rows. As shown in Table I, each  8   b  word is mapped to one of two  10   b  words. The first mapping B 1  comprises words having 5 or 6 ones. The second mapping B 2  comprises words having 4 or 5 ones. In transmitting a string of  8   b  words, a transmitter calculates a total running disparity (RD) of the string—the difference between the total number of ones and the total number of zeroes transmitted. After each  10   b  word has been transmitted, the transmitter evaluates if RD is positive, negative, or zero. For RD+ the following  10   b  word is transmitted from the first mapping B 1 , and for RD− the following  10   b  word is transmitted from the second mapping B 2 . If RD is zero, the fourth column, stating whether the same mapping is used or if the mapping switches, is used. The transmitter is thus able to maintain the disparity of the transmitted string within the bounds of +1 and −1.  
           [0008]    A receiver of the encoded data is able to use the disparity properties to detect if there are errors in the received data. Typically, the receiver calculates and updates a disparity status of the received string, and if this results in a value outside the bounds, the receiver knows that there is an error in the received data. Similarly, in receiving any two sequential  10   b  words, if the instruction in column four is violated, there is an error in the received data. However, in most cases the receiver is not able to know in exactly which received word the error occurred. Even if it does know the exact word, the receiver is not able to correct the error.  
           [0009]    Performance of both data transmitters and data receivers is an important factor in their operation. One of the measurements of performance is signal quality, both transmitted signal quality and received signal quality. A method for measuring signal quality, known in the art, is by generating an “eye” pattern. The eye pattern may be generated in specialized equipment by repeatedly sampling the signal level and plotting the level on a vertical axis, while triggering a horizontal axis to a signal clock. A “perfect” signal would give a rectangle, and the quality of the actual signal is proportional to the “openness” of the eye pattern generated—the more open the center of the eye, the higher the signal quality.  
           [0010]    The specialized equipment for generating eye patterns may be available in a facility where the transmitter and/or receiver are produced, so that adjustments to the transmitter and/or receiver may be made at the facility to improve signal quality. However, such signal quality measurements and adjustments to improve the quality may not be able to be made in an “on-site” situation, because of the lack of specialized equipment. There is thus a need for a signal quality indicator that overcomes these problems.  
         SUMMARY OF THE INVENTION  
         [0011]    It is an object of some aspects of the present invention to provide a signal quality indicator.  
           [0012]    In preferred embodiments of the present invention, input data which has been generated at a transmission frequency is received in a data receiver. Each bit of the data is sampled at two or more positions, the positions being determined by respective phases of an internal clock of the receiver, to produce samples having respective sampled values. The internal clock runs independently of a transmit clock frequency, so that there is a temporal drift of the sampling positions with respect to the input data. Thus, over the course of many clock cycles, the sampling positions effectively scan across the input data. A bit average based on the sampled values for each bit is calculated, and the bit average, due to the sample scanning across the input data, gives a very good metric of the overall signal quality of the input data.  
           [0013]    In some preferred embodiments of the present invention, one of the samples of each bit, most preferably the sample farthest from edges of the bit, is identified as an optimum sample. In calculating the bit average, the optimum sample value is given greater weight than the other samples of the bit. In addition, the bit averages are preferably decimated. The decimation is most preferably implemented according to the temporal drift, so that there are substantially equal numbers of bit averages used to determine a final overall signal quality, independent of a rate of the drift.  
           [0014]    There is therefore provided, according to a preferred embodiment of the present invention, a method for measuring quality of a stream of data, which was transmitted in accordance with a transmit clock, the method including:  
           [0015]    generating samples of the stream of data at sample times determined in accordance with a receive clock, which is characterized as operating independently of the transmit clock; and  
           [0016]    averaging values of the samples so as to generate a metric indicative of the quality of the stream of data.  
           [0017]    Preferably, the data includes a first plurality of bits, and generating the samples includes generating a second plurality of the values for each bit of the data, and averaging the values includes averaging the second plurality of values.  
           [0018]    Generating the second plurality of the values preferably includes assigning a grade to each of the values, and averaging the values includes weighting the metric in response to the grade.  
           [0019]    Preferably, generating the second plurality of the values for each bit of the data includes determining respective second pluralities of positions of the values for each bit of the data, and assigning the grade includes assigning a higher grade in response to a distance of the position of the grade from a transition edge of the bit.  
           [0020]    Further preferably, assigning the higher grade includes determining a period for which the higher grade is assigned in response to the temporal drift, and generating the samples includes generating a number of the samples during the period that is substantially independent of the temporal drift.  
           [0021]    Preferably, averaging the values of the samples includes decimating the averaging in response to the temporal drift, and decimating the averaging includes generating a number of the samples that is substantially independent of the temporal drift.  
           [0022]    Preferably, the receive clock is characterized by a temporal drift relative to the transmit clock.  
           [0023]    There is further provided, according to a preferred embodiment of the present invention, apparatus for measuring quality of a stream of data which was transmitted in accordance with a transmit clock, comprising:  
           [0024]    a receive clock which is characterized as operating independently of the transmit clock;  
           [0025]    a sample generator that is adapted to generate samples of the stream of data at sample times determined in accordance with the receive clock; and  
           [0026]    digital circuitry that is adapted to average values of the samples so as to generate a metric indicative of the quality of the stream of data.  
           [0027]    Preferably, the data includes a first plurality of bits, and the samples consist of a second plurality of the values for each bit of the data.  
           [0028]    Further preferably, the digital circuitry is adapted to assign a grade to each of the second plurality of the values, and to weight the metric in response to the grade, and the digital circuitry is also adapted to determine respective second pluralities of positions of the values for each bit of the data, and to assign a higher grade in response to a distance of the position of the grade from a transition edge of the bit.  
           [0029]    Further preferably, the digital circuitry is adapted to determine a period for which the higher grade is assigned in response to the temporal drift, to generate a number of the samples during the period that is substantially independent of the temporal drift, to decimate averaging of the values in response to the temporal drift, and to generate a number of the samples that is substantially independent of the temporal drift.  
           [0030]    Preferably, the receive clock is characterized by a temporal drift relative to the transmit clock.  
           [0031]    The present invention will be more fully understood from the following detailed description of the preferred embodiments thereof, taken together with the drawings, in which:  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]    [0032]FIG. 1 is a schematic block diagram of a deserializer, according to a preferred embodiment of the present invention;  
         [0033]    [0033]FIG. 2 are schematic graphs of data received by the deserializer of FIG. 1, according to a preferred embodiment of the present invention;  
         [0034]    [0034]FIG. 3 is a schematic block diagram of an initial grading module, according to a preferred embodiment of the present invention;  
         [0035]    [0035]FIG. 4 is a schematic block diagram of a leakage integrator, according to a preferred embodiment of the present invention;  
         [0036]    [0036]FIG. 5 is a schematic block diagram of a single bit corrector, according to a preferred embodiment of the present invention;  
         [0037]    [0037]FIG. 6 is a schematic block diagram illustrating an error correction system, according to a preferred embodiment of the present invention;  
         [0038]    [0038]FIG. 7 is a logical flow diagram which schematically illustrates a process carried out by the error correction system of FIG. 6, according to a preferred embodiment of the present invention;  
         [0039]    [0039]FIG. 8 is a flowchart showing steps in the process of FIG. 7, according to a preferred embodiment of the present invention;  
         [0040]    [0040]FIG. 9 is a schematic block diagram of a signal quality indicator (SQI), according to a preferred embodiment of the present invention;  
         [0041]    [0041]FIG. 10 is a schematic block diagram of leakage integrators, according to a preferred embodiment of the present invention;  
         [0042]    [0042]FIG. 11 shows schematic graphs of values of the final signal quality grade from the SQI of FIG. 9, for different input signals, according to a preferred embodiment of the present invention; and  
         [0043]    [0043]FIG. 12 is a schematic block diagram of a multi-channel deserializer, according to a preferred embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0044]    Reference is now made to FIG. 1, which is a schematic block diagram of a deserializer  10 , and to FIG. 2, which comprises schematic graphs of data received by the deserializer, according to a preferred embodiment of the present invention. In an analog front end  11 , deserializer  10  receives incoming serial data which may be transmitted according to substantially any serial data protocol. Hereinbelow, by way of example, the data is assumed to be transmitted in the form of  8   b / 10   b  encoded data according to IEEE standard 802.3 z, as described in the Background of the Invention. The data is received on a channel, herein assumed to comprise two differential lines  12 , although it will be understood that the channel may not comprise differential lines.  
         [0045]    The data is combined in an input cell  13  as a single data stream  50  of bits  54 , as shown in a graph  52  (FIG. 2), and the single bit stream is fed to a sample generator  20 . Bits  54  are also referred to herein as bits B 1 , B 2 , . . . , B 10 . A section of graph  52  is shown in more detail in a graph  56 . Data stream  50  is assumed to be transmitted at 3.125 Gb/s, so that each bit  54  of stream  50  has a nominal width of 320 ps. However, it will be appreciated that the transmission rate and nominal width are examples, and that substantially any transmission rate and bit width may apply to the data received.  
         [0046]    A free-running reference receive clock  14  driving a phase-locked loop (PLL) oscillator  16  generates a base frequency of 625 MHz. The 625 MHz base frequency is used to generate  20  substantially equally spaced phases, ph 0 , ph 1 , . . . , ph 19  which are separated by 80 ps. The phases are input to a multiplexer  18 , and contiguous phases from the multiplexer are used to sample bits  54  in sample generator  20 . Sample generator  20  effectively acts as a slicer, providing a decision of 0 or 1 at each sample point.  
         [0047]    As shown in graph  52 , the 20 phases are used to sample a first set of five bits {B 1 , B 2 , B 3 , B 4 , B 5 }, and are also used to sample a second set of five bits {B 6 , B 7 , B 8 , B 9 , B 10 }, each bit being nominally sampled at four positions. Generator  20  thus generates a total of forty samples in a cycle defined by the ten bits. The samples are provided in the form of respective decisions which are transferred to a digital circuitry section  22 , which also receives general timing signals derived from clock  14  and/or PLL oscillator  16 . It will be appreciated that the separation of 80 ps is a fourth of the period of the nominal width. It will also be appreciated that the separation of 80 ps is chosen by way of example, and that the phases may be separated by substantially any integral sub-multiple of the nominal width, the number of decisions generated by generator  20  altering accordingly.  
         [0048]    In digital circuitry  22  the forty decisions are grouped into four sampling sets A, B, C, D. Referring to FIG. 2, first set A comprises ten decisions—two decisions for each phase—generated by phases {ph 0 , ph 4 , ph 8 , ph 12 , ph 16 }. Sets B, C, and D respectively comprise ten decisions having phases {ph 1 , ph 5 , ph 9 , ph 13 , ph 17 }, {ph 2 , ph 6 , ph 10 , ph 14 , ph 18 }, and {ph 3 , ph 7 , ph 11 , ph 15 , ph 19 }. Each sampling set is fed through one of four substantially similar initial grading modules  24 . Each module  24  determines a quality of its respective sample set as a temporal grade, by comparing values of a present decision with values of adjacent decisions. The initial grades generated in each module  24  are integrated in respective leakage integrators  26 , and the integrated grades are used in a main phase selector  28 , as is described in more detail hereinbelow, to determine an optimal sampling set from amongst sampling sets A, B, C, D. Both the integrated grades supplied to main phase selector  28 , and a grade determined by the selector, are thus determined by averaging decisions of more than one phase or phase set.  
         [0049]    The optimal sampling set, together with the original decisions, are processed in a single bit corrector  32  wherein errors that may be caused by a “high frequency” single bit occurring within a “low frequency” pattern are eliminated. Bits from corrector  32  are processed through a symbol alignment block  34 , wherein symbols input to deserializer  10  are recovered. Symbols from deserializer  10  are preferably output via an error correction block  150 . Corrector  32  and blocks  34  and  150  are also described in more detail below. Most preferably, main phase selector  28  also provides outputs which are used as inputs to a signal quality indicator  27 , preferably comprised in deserializer  10 , and described with reference to FIGS. 8, 9, and  10  below.  
         [0050]    [0050]FIG. 3 is a schematic block diagram of one of initial grading modules  24 , according to a preferred embodiment of the present invention. Each module  24  operates in parallel on the ten decisions of its sampling set, so that elements  60 ,  62 ,  68 ,  70 ,  72 ,  74 , and  76 , in the module are replicated ten times. Elements  60  and  62  respectively comprise comparators, and are herein referred to as comparators  60  and  62 ; elements  68  and  70  respectively comprise XOR gates, and are herein referred to as gates  68  and  70 ; elements  72  and  74  respectively comprise AND gates, and are herein referred to as gates  72  and  74 ; element  76  comprises a summer and is herein referred to as summer  76 .  
         [0051]    Comparator  60  compares a decision value D(p,n), for a bit n, of the present phase p with a decision value D(p−1,n) of a phase prior to the present phase. The output of comparator  60  is a first input to AND gate  72 . Comparator  62  compares decision value D(p,n) of the present phase with a decision value D(p+1,n) of a phase after the present phase. The output of comparator  62  is a first input to AND gate  74 .  
         [0052]    Module  24  also comprises selectors  64  and  66 , which receive  12  decision values D(M) of a main phase M. Generation of main phase M is described in more detail below. Selector  64  selects ten decision values D(M,n+1), corresponding to main phase decisions of a bit after bit n, and outputs the selected decisions as a first input of XOR gate  68 . Selector  66  selects ten decision values D(M,n−1), corresponding to main phase decisions of a bit before bit n, and outputs the selected decisions as a first input of XOR gate  70 . The result of gate  68  provides a second input to gate  74 , and the result of gate  70  provides a second input to gate  72 .  
         [0053]    The respective outputs of gates  72  and  74  are summed in summers  76 . Summers  76  thus output ten separate values, herein termed partial sums PS n , for each of the ten bits considered in stream  50 . The ten values PS n  are summed in a second summer  78  to give one value, which is delayed in a delay  80  before outputting a temporal grade TG(p) for present phase p from initial grading module  24 .  
         [0054]    The output of each module  24  may be represented by the following equation:  
                     TG        (   p   )       =              ∑     n   =   1       n   =   10            PS   n                   =              ∑     n   =   1       n   =   10            {               (       D   (     M   ,     n   -   1       )     ≠     D   (     p   ,   n     )       )     ⊕     (       D   (     p   ,   n     )     =     D   (       p   -   1     ,   n     )       )       +                 (       D   (     M   ,     n   +   1       )     ≠     D   (     p   ,   n     )       )     ⊕     (       D   (     p   ,   n     )     =     D   (       p   +   1     ,   n     )       )             }                     (   1   )                               
 
         [0055]    where TG(p) is the temporal grade of phase p,  
         [0056]    D(M,n) is the decision of the main phase M for bit n,  
         [0057]    D(p,n) is the decision of phase p for bit n, p+1, p−1 are respectively next and prior phases to phase p, and  
         [0058]    n+1, n−1 are respectively next and prior bits to bit n.  
         [0059]    Each module  24  compares sample decisions of three consecutive bits, (n−1, n, n+1, where n=1, . . . ,10) . The ten results of these comparisons are summed, as shown by equation (1), in order to grade each of the sampling phase sets.  
         [0060]    Graph  56  illustrates the summation. In graph  56  bits B 4 , B 5 , and B 6  are respectively assumed to have the values 0, 1, and 0, and n has the value 5.  
         [0061]    Assume M=A, so that p=12, 16 and 0 for bits B 4 , B 5 , and B 6 .  
         [0062]    From graph  56 ,  
         [0063]    D(M,n−1)=0  
         [0064]    D(p,n)=1  
         [0065]    D(p−1,n)=0  
         [0066]    D(M,n+1)=0  
         [0067]    D(p+1,n)=1  
         [0068]    Thus PS 5  for sampling set A, herein termed PS 5A , is given by:  
           PS   5A =(0≠1)⊕(1=0)+(0≠1)⊕(1=1)=1  (2) 
         [0069]    Assume M=B, so that p=13, 17 and 1 for bits B 4 , B 5 , and B 6 .  
         [0070]    Then,  
         [0071]    D(M,n−1)=0  
         [0072]    D(p,n)=1  
         [0073]    D(p−1,n)=1  
         [0074]    D(M,n+1)=0  
         [0075]    D(p+1,n)=1  
         [0076]    Thus PS 5B  is given by:  
           PS   5B =(0≠1)⊕(1=1)+(0≠1)⊕(1=1)=2  (3) 
         [0077]    Assume M=C, so that p=14, 18 and 2 for bits B 4 , B 5 , and B 6 .  
         [0078]    Then,  
         [0079]    D(M,n−1)=0  
         [0080]    D(p,n)=1  
         [0081]    D(p−1,n)=1  
         [0082]    D(M,n+1)=0  
         [0083]    D(p+1,n)=1  
         [0084]    Thus PS 5C  is given by:  
           PS   5C =(0≠1)⊕(1=1)+(0≠1)⊕(1=1)=2  (4) 
         [0085]    Assume M=D, so that p=15, 19 and 3 for bits B 4 , B 5 , and B 6 .  
         [0086]    Then,  
         [0087]    D(M,n−1)=0  
         [0088]    D(p,n)=1  
         [0089]    D(p−1,n)=1  
         [0090]    D(M,n+1)=0  
         [0091]    D(p+1,n)=0  
         [0092]    Thus PS 5D  is given by:  
           PS   5D =(0≠1)⊕(1=1)+(0≠1)⊕(1=0)=1  (5) 
         [0093]    Each initial grading module  24  evaluates ten partial sums PS n , by using a total of forty samples from the ten bits being processed by the modules. As shown by equation (1), the evaluation compares values generated by three consecutive bits (n−1, n, n+1). It will be appreciated that in order to evaluate the first bit (n=1) of a specific group of ten bits, values for the tenth bit of the preceding group are required for the evaluation. Similarly, to evaluate the tenth bit of the specific group, values for the first bit of the following group are required for the evaluation. The total of 48 samples of the twelve bits are stored in multiplexers  64  and  66 .  
         [0094]    Performing similar calculations to equations (2)-(5) for all bits and assuming the bits alternate sequentially in value between 0 and 1, gives results for TG(p) as shown in Table II below.  
                           TABLE II                                   Phase p   TG(p)                           A   10           B   20           C   20           D   10                      
 
         [0095]    Temporal grades TG(p) form a basis for deserializer  10  to decide which sampling phases to use in evaluating bits (B 1 , . . . , B 10 . As is apparent from Table II, phases which are closer to transitions between values, i.e., phase A and D in the table, receive substantially lower grades than phases which are farther from the transitions, i.e., phases B and C. The calculations of grades thus enable the deserializer to select a sampling phase furthest from transitions between values. The selected sampling phase, also herein termed the main phase, is used by the deserializer as a decoding phase, i.e., as an optimal phase at which bits  54  are to be decoded.  
         [0096]    It will be understood that while the examples above with reference to the graphs of FIG. 2 have used substantially ideal values, the principles of grading incoming bits as described hereinabove apply to non-ideal received bits. In the case of non-ideal bits, deserializer  10  continuously grades the bits and determines a highest grade G from amongst three adjacent phases, as is shown in equation (7) below. Except when there is a change in phase, it will be appreciated that the highest grade phase, i.e. the main phase, will be the “center” of the three graded phases. When there is a change in main phase, then for one cycle the highest graded phase will be one of the non-central graded phases.  
         [0097]    The resultant TG(p) of each initial grading module  24  is integrated in a respective leakage integrator  26 .  
         [0098]    [0098]FIG. 4 is a schematic block diagram of leakage integrator  26 , according to a preferred embodiment of the present invention. Each integrator  26  performs a weighted time integration of the value TG(p) received from its respective initial grading module  24 . TG(p) is input to a shifter  90 , which shifts the value of TG(p) to the right by a predetermined number, preferably 2. The output of shifter  90  is a first input to a summer  92 . The output of summer  92  is passed through a register  96  acting as a time delay, and the output of register  96  is fed back directly to the summer. The output of register  96 , after being shifted right by the predetermined number in a shifter  94 , is also subtracted in summer  92 . The output from the integrator, after being adjusted in a fixed point converter  98 , is represented by the following equation:  
           G ( p,t )= G ( p,t− 1)− G ( p,t− 1)&gt;&gt; a+TG ( p )&gt;&gt; a   (6) 
         [0099]    where G(p,t) is the final grade of phase p at a  
         [0100]    time t, and  
         [0101]    a is the predetermined shifted right value.  
         [0102]    Each of the four final grades is input to a main phase selector  28  (FIG. 1). In each cycle of the 625 MHz clock selector  28  selects a main phase M(t+1) for a next cycle by finding a highest grade G from three adjacent phases of the present cycle, as shown in the following equation:  
           M ( t+ 1)=Max[ G ( M,t ), G ( M− 1,  t ), G ( M+ 1,  t )]  (7) 
         [0103]    The selected main phase M(t+1) is used, as shown in equation (1), as an input for determining the partial sums PS n . Preferably, if there is no clear-cut maximum in equation (7), G(M,t) is assumed to be the maximum value.  
         [0104]    Returning to FIG. 1, an index D 1  of main phase M and an index D 2  of a second phase, the second phase having a grade closest to main phase M, are transferred from main phase selector  28  to single bit corrector  32 . Corrector  32  also receives decisions from sample generator  20 , via a delay  30 . Corrector  32  uses the phase indices and decisions corresponding to main phase M to allow a decision made by the main phase to be overwritten in predetermined situations, usually caused by inter-symbol interference (ISI) . Typically, ISI is most troublesome when a single bit value is different from a train of bits on either side of the single bit, for example 1111110111. Most preferably, a main phase decision is overwritten if the following condition is true:  
         (( D ( M,n− 1)= D ( M,n )=( D ( M,n+ 1))⊕( D ( p,n )≠ D ( M,n ))  (8) 
         [0105]    where p may be M−1 or M+1.  
         [0106]    Condition ( 8 ) is true if three consecutive main phase decisions are the same, and if the central main phase decision is not the same as a phase on either side of the central main phase. The latter typically occurs if the main phase “missed” a transition. If condition ( 8 ) is not true, the decision of the main phase is not overwritten.  
         [0107]    [0107]FIG. 5 is a schematic block diagram of single bit corrector  32 , according to a preferred embodiment of the present invention. Correctors substantially similar to single bit corrector  32  are most preferably implemented in parallel, the number of correctors preferably corresponding to ten. Corrector  32  comprises a comparator  100  which checks for equality of decisions D(M,n−1), D(M,n), and D(M,n+1). The decisions are received via delay  30 . The output of comparator  100  is a first input to an AND gate  108 . Two other substantially similar comparators  102 ,  104  check respectively for inequality of decisions D(M−1,n) and D(M,n), and decisions D(M+1,n) and D(M,n), which are also received via delay  30 . D(M,n) corresponds to main phase index D 1 , and either D(M+1,n) or D(M−1,n) correspond to second phase index D 2 . The decision D(M+1,n) or D(M−1,n) which does not correspond to D 2  represents a third phase decision, on the opposite side of the main phase from D 2 . The outputs of comparators  102  and  104  are transferred to an OR gate  106 , which generates a second input to AND gate  108 . The output of AND gate  108 , corresponding to equation (8), is exclusively ORed in a gate  110  to decide if main decision D(M,n) is to be overwritten.  
         [0108]    It will be appreciated that since the frequency of receiver clock  14  and the effective frequency of the received bits may not be identical, there may typically be drift between the sampling positions generated by the clock and the received bits. Typically, there is a standard number of bits resolved per cycle, the standard in the examples described above being ten; the drift will cause, for one cycle, typically the cycle when there is a change in main phase , resolution of one extra bit or one less bit in the cycle compared to the standard number of bits resolved. Thus corrector  32  may output, in each cycle of the receiver clock, 9, 10, or 11 bits.  
         [0109]    Decisions from corrector  32  for phase index D 1 , as well as decisions for phase D 2 , are transferred to symbol alignment block  34  which temporarily stores the decisions as sets of D 1  decisions and sets of D 2  decisions. Bits  52  are preferably transmitted as symbols, also termed words, formed according to a predetermined coding scheme, most preferably the  8   b / 10   b  word coding scheme described in the Background of the Invention. Block  34  analyzes the stored values to determine boundaries between symbols, by methods which are well known in the art, and outputs the symbols evaluated. Typically one symbol formed from the D 1  decisions, herein termed W 1 , is output per cycle, but it will be appreciated that in a generally similar manner to corrector  32  outputting one extra or one less bit per cycle, alignment block  34  may be able to resolve and output  0 ,  1 , or 2 symbols per cycle. A second symbol, formed from the D 2  decisions and herein termed W 2 , is also output from block  34 . Symbols W 1  and W 2  are also termed candidate words hereinbelow. It will be appreciated that, since its bits are derived from main phase decisions, W 1  has a significantly higher probability of being correct than W 2 , which is derived from second phase decisions. The property of the difference in probability, generated by assigning a main phase and a second phase for each bit, is used in error correction block  150 .  
         [0110]    As outlined in the Background of the Invention, encoding  8   b  words to  10   b  words enables errors in reception of the  10   b  words to be detected.  
         [0111]    Table III below shows how the errors introduced by an incorrect single bit in the  10   b  word may be classified.  
                           TABLE III                                   No.   Class Description                           1   The 10b word is invalid i.e., it is not present in               mapping B1 or B2, Table I.           2   The 10b word belongs to an incorrect mapping,               according to the disparity status of a string of               10b words already received.           3   The 10b word belongs to a correct mapping, but               causes the string to expect a disparity switch               when no switch should occur.           4   The 10b word belongs to a correct mapping, but               causes the string not to expect a disparity switch               when such a switch should occur.                      
 
         [0112]    Block  34  is most preferably implemented so as not to output  10   b  words in classification  1 . Preferred embodiments of the present invention are implemented to correct errors in classifications  2 ,  3 , and  4 , as described hereinbelow.  
         [0113]    [0113]FIG. 6 is a schematic block diagram illustrating an error correction system, according to a preferred embodiment of the present invention. W 1  and W 2  are input to error correction block  150 , which recovers errors in the  8   b / 10   b  words it receives. It will be appreciated that block  150  may be implemented to recover errors generated by transmission of other types of encoded signals which have redundancy.  
         [0114]    Block  150  maintains a multiplicity of sequences of previously transmitted candidate words Wx(t), Wx(t−1), . . . , Wx(t−N+1), where x may be 1 or 2, and where N is the number of words W 1 , W 2  comprised in each sequence. The sequences are stored in a memory  152  in correction block  150 . Herein, by way of example, the number of sequences is assumed to be three, and the sequences, also herein termed tracks, are referred to as T 1 , T 2 , and T 3 . Except as described below, track T 1  in general receives W 1 , and track T 2  in general receives W 2 . T 1  is assumed to be a preferred track, and gives a final output from block  150 . T 2  is assumed to be a less preferred track. Track T 3  is used as a reserve track.  
         [0115]    A processor  154  in block  150  calculates a running disparity (RD) of each sequence, determining if the disparity status is positive, zero, or negative. Disparity and running disparity, and the concept of a transmitter generating strings of  10   b  words having their RD maintained within bounds, are described in more detail in the Background of the Invention.  
         [0116]    As shown in Table III, errors may be classified as class  2 ,  3 , or  4 . A class  2  error is immediately apparent, assuming there are no prior errors in the string to which the word is being inserted. A class  3  or  4  error may not be immediately apparent, but eventually causes a disparity error similar to class  2 . Processor  154  accommodates the differing errors by copying tracks T 1 , T 2 , and T 3  to each other, and by assigning W 1  and W 2  to the tracks, so as to maintain T 1  as the preferred track with the highest probability of having correct words in the track.  
         [0117]    As candidate words W 1  and W 2  are generated, processor  154  checks if the candidate words “fit” the sequences, updates the sequences, and inserts W 1  and W 2  into the updated sequences according to the most probably correct arrangement.  
         [0118]    For example, if W 1  fits T 1 , W 2  fits T 2 , but neither fit T 3 , T 1  is first copied to T 3  since T 1  is more probably correct than T 2 . W 1  is then inserted to T 1  and T 3 , and W 2  is inserted to T 2 . If W 1  or W 2  fit T 3 , no tracks are copied, W 1  is inserted to T 1 , W 2  is inserted to T 1 , and either W 1  or W 2  is inserted to D 3 , depending which of W 1 , W 2  fits T 3 . If both W 1 , W 2  fit T 3 , then W 1  is inserted to T 3 , since W 1  is more probably correct than W 2 . (This example is also considered with reference to Table V below.)  
         [0119]    [0119]FIG. 7 is a schematic diagram illustrating stages in a process  160  operated by error correction block  150 , and FIG. 8 is a flowchart for the process, according to a preferred embodiment of the present invention. Process  160  is applied by processor  154  to each candidate word as it is received from symbol alignment block  34 .  
         [0120]    In a first step  162  of the process, corresponding to a first stage  161 , processor  154  receives the two possible candidate words W 1  and W 2 . Except for the case of W 1 =W 2  words W 1  and W 2  may differ by one or more bits, the probability of a specific number of bits difference decreasing as the number increases. In most cases of a difference existing, the difference is one bit. Examples of possible pairs of words differing by one bit (derived from Table I) are given in Table IV below. The “difference” bit is underlined for each  10   b  word.  
                           TABLE IV                                   Position in Table I   W1/W2                           Decimal 0, Second mapping   01100 0  1011           Decimal 6, First mapping   01100 1  1011           Decimal 188, First mapping     0 01110 1010           Decimal 189, First mapping     1 01110 1010           Decimal 196, Second mapping   001010  0 110           Decimal 228, Second mapping   001010  1 110                      
 
         [0121]    In a second step  164 , processor  154  utilizes Table I, stored in memory  152 , to determine to which mapping, B 1  or B 2 , each word W 1  and W 2  belongs.  
         [0122]    In a third step  166 , for each W 1 , W 2  word received in step  162 , processor  154  determines a respective grade G 1 , G 2 . The grade is an ordered triple (Fit T 3 , Fit T 2 , Fit T 1 ), each element of the triple comprising a binary value of 0 or 1. A “1” indicates a “fit,” i.e., that the word may be inserted into the respective track T 1 , T 2 , or T 3 , without an error being apparent in the updated track. A “0” indicates a “no-fit,” i.e., that inserting the word would generate an error in the track. For example a grade (0,1,1) assigned to W 1  means that W 1  does not fit track T 3 , but does fit tracks T 2  and T 1 . If W 1 =W 2  then G 2  is automatically allocated the value (0,0,0).  
         [0123]    It will be appreciated that a fit does not necessarily mean that a sequence with the inserted word has no erroneous words. A sequence after the word has been inserted may comprise a “hidden” error corresponding to a category  3  or  4  error. The error may be in the inserted word, or in a word further back in the sequence. Similarly, a no-fit does not necessarily mean that the word being inserted has an error. The no-fit may also be the result of a sequence having a hidden category  3  or  4  error.  
         [0124]    In a fourth step  168 , corresponding to a second stage  163 , processor  154  uses Table V below to assign which tracks replace each other, and also into which tracks words W 1  and W 2  are inserted. Table V is stored in memory  152 . In the table T 1 →T 2  means that track T 1  is copied to track T 2 , W 1 →T 1  means that W 1  is inserted to the head of track T 1 . It will be understood that entries in the table such as  
                         
 
         [0125]    mean that the track initially labeled T 1  is copied to T 2 , and the track initially labeled T 2  is copied to T 1 , so that in this case the tracks essentially switch labels. Processor  154  copies the tracks, with their running disparity, as indicated in the table.  
                                                             TABLE V                                       G2            G1   000   001   010   011   100   101   110   111               000       T1 → T2   T2 → T1   T1 → T3   T3 → T1   T1 → T2   T2 → T1                   T1 → T3   T2 → T3       T3 → T2           W1 → T1   W2 → T1   W2 → T1   W2 → T1   W2 → T1   W2 → T1   W2 → T1   W2 → T1           W1 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2           W1 → T3   W2 → T3   W2 → T3   W2 → T3   W2 → T3   W2 → T3   W2 → T3   W2 → T3       001   T1 → T2   T1 → T2   T1 → T3   T1 → T3   T3 → T2   T1 → T2       T1 → T3           T1 → T3   T1 → T3           T1 → T3           W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1           W1 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2           W1 → T3   W1 → T3   W1 → T3   W2 → T3   W1 → T3   W2 → T3   W2 → T3   W2 → T3       010   T2 → T1   T1 → T2   T2 → T1   T2 → T1   T3 → T2   T2 → T1   T2 → T1   T2 → T1           T2 → T3   T2 → T1   T2 → T3       T2 → T1   T1 → T2       T1 → T3               T2 → T3           T2 → T3           W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1           W1 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2           W1 → T3   W1 → T3   W1 → T3   W2 → T3   W1 → T3   W2 → T3   W2 → T3   W2 → T3       011   T1 → T3   T1 → T2   T2 → T3   T2 → T3   T2 → T3   T1 → T2   T2 → T3   T2 → T3               T2 → T3           T3 → T2   T2 → T3           W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1           W1 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2           W1 → T3   W1 → T3   W1 → T3   W1 → T3   W1 → T3   W1 → T3   W1 → T3   W1 → T3       100   T3 → T1   T1 → T2   T3 → T1   T1 → T3   T3 → T1   T1 → T2   T3 → T1   T3 → T1           T3 → T2   T3 → T1       T3 → T1   T3 → T2   T3 → T1       T1 → T3           W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1           W1 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2           W1 → T3   W1 → T3   W1 → T3   W2 → T3   W1 → T3   W2 → T3   W2 → T3   W2 → T3       101   T1 → T2   T1 → T2       T1 → T3   T3 → T2   T1 → T2       T1 → T3           W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1           W1 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2           W1 → T3   W1 → T3   W1 → T3   W2 → T3   W1 → T3   W1 → T3   W1 → T3   W2 → T3       110   T2 → T1   T1 → T2   T2 → T1   T1 → T3   T2 → T1       T2 → T1   T2 → T1               T2 → T1       T2 → T1   T3 → T2           T1 → T3           W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1           W1 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2           W1 → T3   W1 → T3   W1 → T3   W2 → T3   W1 → T3   W1 → T3   W1 → T3   W2 → T3       111       T1 → T2   T2 → T3   T2 → T3   T2 → T3   T2 → T3   T2 → T3   T2 → T3               T2 → T3           T3 → T2   T1 → T2           W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1   W1 → T1           W1 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2   W2 → T2           W1 → T3   W1 → T3   W1 → T3   W1 → T3   W1 → T3   W1 → T3   W1 → T3   W1 → T3                  
 
         [0126]    It will be understood that the operations listed in Table V are based on maintaining track T 1  as the track being most likely to comprise a correct string of received words. To illustrate the operations listed in Table V, consider the example described above, which corresponds to a set of four ordered pairs of triples: {(G 1 , G 2 )}={(0,0,1), (0,1,0)}; {(1,0,1),(0,1,0)}; ((0,0,1), (1,1,0)); ((1,0,1), (1,1,0))}. Inspection of the four cells of Table V corresponding to the ordered pairs shows that the actions carried out correspond to those described above in the example. Actions listed for other cells of Table V are generated in a generally similar manner as those described for the cells of the example.  
         [0127]    In a final step  170 , processor  152  outputs as a final decision the word that is in track T 1 .  
         [0128]    It will be understood that the principles of the present invention may be applied to correcting erroneous words which have been encoded in formats other than the  8   b / 10   b  format described above, or that may not be encoded, and for correcting errors in words which have one or more incorrect bits. It will be further understood that while the preferred embodiments described above use three sequences of stored words, other numbers of sequences may also be used. For example, the number of sequences may be set to four, so that there are two reserve sequences, each of which may have either word W 1  or W 2  inserted. All such numbers are assumed to be comprised within the scope of the present invention.  
         [0129]    In an alternative preferred embodiment of the present invention error, correction block  150  does not receive two words W 1  and W 2  from symbol alignment block  34 . Rather block  150  receives one word, preferably W 1 , from block  34  and a single bit quality value Q (FIG. 6). Most preferably, the single bit quality value is in the form of a flag assigned to a specific bit in the word received by block  150  whose quality has been assessed and which is considered to be problematic on the basis of the assessment. It will be appreciated that in performing their tasks, both selector  28  and corrector  32  are able to generate a measure of the quality of each single bit they analyze. For example, if single bit corrector  32  does perform a correction using condition ( 8 ), the bit value output from the corrector may be considered to have a high probability of being correct. Thus the bit quality of the bit value output is high, and correspondingly, a bit quality for the opposite bit value for this bit is low. Those skilled in the art will be able to assign a bit quality for bits output from selector  28 .  
         [0130]    Preferably, if the bit quality is outside a predetermined value, so indicating that the bit may not be correct and that the bit is problematic, bit quality Q is input to error correction block  150 , most preferably by setting the flag if implemented. If the bit quality is within the predetermined value, so that the corresponding bit is assumed to be correct, no bit quality value is input to block  150 , and the flag is not set.  
         [0131]    Block  150  uses the bit quality and the symbol associated with the bit to construct a second word W 2 . Process  160 , as described above with respect to FIGS. 7 and 8, is then applied to W 1  and W 2 .  
         [0132]    As stated above, since clock  14  is not locked to a transmit clock of the incoming signal, the sampling positions of sampling phase sets A, B, C, D, (FIG. 2) may drift relative to data stream  50 . As the positions drift, they effectively scan across the data stream. The scanning, and the fact that a single value of G(p,t) (equation (6)) acts as a weighted average of signal levels at three adjacent phases, are used by preferred embodiments of the present invention to implement a signal quality indicator  27  (FIG. 1). The signal quality indicator may be advantageously used in place of specialized signal quality measurement equipment such as that described in the Background of the Invention. Signal quality indicator  27  receives its inputs, an index D 1  of the main phase and a grade G(p,t) of that phase, from main phase selector  28 .  
         [0133]    [0133]FIG. 9 is a schematic block diagram of signal quality indicator (SQI)  27 , according to a preferred embodiment of the present invention. SQI  27  comprises a first leakage integrator  180  in series with a second leakage integrator  182 . Both integrators integrate their respective inputs so as to effectively smooth them. Leakage integrator  182  may be activated by an enable signal generated by a multiplexer  184 , so that in addition to integrating its input, decimation may be performed on the output of SQI  27 . The enable signal for the decimation is derived from a multiplexer  184 , which activates the enable signal according to a decimation factor received by the multiplexer.  
         [0134]    The decimation factor is most preferably generated automatically by a drift estimation block  186 . Block  186  receives, from main phase selector  28 , the phase value that has been selected as the main phase. Block  186  also receives a timing signal, preferably generated from clock  14 , which enables the block to determine a duration of time for which a specific phase is the main phase. During operation of deserializer  10  the main phase changes because of drift of the sampling phase sets, as described above. Block  186  measures a “phase time” during which a specific phase of the sampling phase sets is chosen as the main phase. The measured phase time is approximately inversely proportional to a “drift speed” of the sampling phases on the data stream.  
         [0135]    In order to scan across the data stream at a rate which is approximately independent of drift speed, block  186  preferably sets the decimation factor to be approximately inversely proportional to the drift speed, so that the lower the drift speed the higher the decimation factor. Block  186  thus preferably sets the decimation factor to be directly proportional to the phase time. In a preferred example of the present invention, Block  186  automatically sets the decimation factor so that eight samples are taken from a specific phase, i.e., during the phase time. Optionally, multiplexer  184  may also receive an alternative decimation factor, which may be input directly to the multiplexer from an operator of SQI  27 . Such an operator input may be used, for example, in a case where the drift speed is very low or even substantially zero.  
         [0136]    [0136]FIG. 10 is a schematic block diagram of leakage integrators  180 ,  182 , according to a preferred embodiment of the present invention. Apart from the differences described below, the operation of integrators  180  and  182  is generally similar to that of integrator  26  (FIG. 4), so that elements indicated by the same reference numerals in integrators  26 ,  180 , and  182  are generally identical in construction and in operation. In integrators  180  and  182 , shifters  90  and  94  preferably shift their input to the right by 6, the value effectively controlling the size of a “sliding window” over which samples are integrated. Unlike integrator  26 , neither of integrators  180 ,  182  have a fixed point converter  98  at their output. Integrator  182  also receives an enable input to shifter  90 , so that the shifter is activated according to the decimation factor used by multiplexer  184 , and so that integrator  182  performs its integration only when enabled. Integrator  182  outputs a final signal quality grade.  
         [0137]    The combination of two integrators in series, the second having decimation, gives sufficient averaging to substantially eliminate noise effects and also effectively scan across each bit of the incoming data. The two integrators give more flexible and better control of integration parameters, as well as using less hardware than an equivalent single integrator providing the same functions as the two integrators.  
         [0138]    Measurements of the signal quality grade are preferably made on incoming signals having the same data, for example, random idle signals. Such measurements on the same data may be performed, for example, during initial setup and adjustment of deserializer  10  and its incoming lines, when a remote transmitter may be requested to transmit specific data.  
         [0139]    [0139]FIG. 11 shows schematic graphs of values of the final signal quality grade for different input signals, according to a preferred embodiment of the present invention. Five different input signals were simulated and input to deserializer  10 . The five signals had different qualities, as determined by an eye opening measurement based on the system described in the Background of the Invention. Graphs  202 ,  204 ,  206 ,  208 , and  210  show values of the signal quality grade, as measured by SQI  27 , vs. time. It is seen that the grades for each input signal stabilize to a substantially constant value. Furthermore, the values obtained are substantially independent of the rate of decimation introduced in integrator  182 , and of the drift speed, even when the latter is very low or substantially zero. Table VI shows the stabilized grade values, from SQI  27  for the different input signals, together with the eye opening measurement for the signals.  
                       TABLE VI                           Stabilized Signal Quality           Graph   Grade   Eye Opening Value                   202   0.47   0.427       204   0.64   0.490       206   0.65   0.494       208   0.72   0.525       210   0.72   0.526                  
 
         [0140]    Graph  212  plots the stabilized signal quality grades vs. the eye opening values. It is seen both from Table VI and from graph  212  that there is a substantially linear relationship between the signal quality grades and the eye opening values, so that the grades provide a good metric of the signal quality.  
         [0141]    [0141]FIG. 12 is a schematic block diagram of a multi-channel deserializer  230 , according to a preferred embodiment of the present invention. Multi-channel deserializer  230  comprises a plurality of separate deserializers  232 . Apart from the differences described below, the operation of each deserializer  232  is generally similar to that of deserializer  10 , so that elements indicated by the same reference numerals in both deserializers  10  and  232  are generally identical in construction and in operation. Preferably, none of analog sections  11  of deserializers  232  have clock  14 , PLL oscillator  16 , or multiplexer  18 . Rather multi-channel deserializer  230  comprises a phase generation block  234 , comprising a single clock  264 , a PLL oscillator  256 , and a multiplexer  268 , respectively substantially similar to clock  14 , PLL oscillator  16 , and multiplexer  18 . Block  234  provides twenty phases ph 0 , ph 19 , substantially as described above with reference to FIG. 1, to each of sample generators  20  in deserializers  232 , and general timing signals to each of their digital circuitry  22 . Alternatively, instead of phase generation block  234 , one of analog sections  11  in a specific deserializer  232  comprises single clock  264 , PLL oscillator  256 , and multiplexer  268 , which generate the twenty phases and general timing signals for the deserializer, and which provide the twenty phases and timing signals to the other analog sections  11  and digital circuitry sections  22  respectively of the other deserializers  232 .  
         [0142]    Each deserializer  232  receives a channel A, B, C, of data, and de-serializes its respective data stream substantially as described above for deserializer  10 . It will be appreciated that multi-channel deserializer  230  is able to deserialize substantially any number of channels of incoming serial data, one deserializer  232  for each channel, using only one PLL clock. Multi-channel deserializer  230  thus saves significant numbers of components, as well as significantly reducing the complexity and difficulty of their arrangement, compared to multi-channel deserializers comprising more than one PLL clock, typically one per channel plus a synchronizing PLL clock, and which may also require elastic buffers. It will be appreciated that multi-channel deserializers such as deserializer  230 , when implemented on a single die, have significant improvements in yields compared to deserializers having multiple PLL clocks, since any single PLL failure leads to failure of the whole deserializer. Furthermore, it will be apparent that there is no requirement to synchronize the one PLL clock of multi-channel deserializer  230  to the incoming data channels, and that the incoming data channels to the deserializer may be transmitted with different clocks.  
         [0143]    It will thus be appreciated that the preferred embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.