Abstract:
A solid-state imaging device includes a transfer element line for transferring an electric charge that is photoelectrically converted in a photoelectric conversion element line formed of a plurality of photoelectric conversion elements, and a charge detector for detecting an electric charge that is transferred by the transfer element line. The charge detector includes output gates disposed adjacently to a final transfer gate of the transfer element line, a reset gate for resetting an electric charge in the charge detector, a floating diffusion formed on a substrate surface adjacently to the output gates and the reset gate, and addition gates formed above the floating diffusion and along the direction from the output gates to the reset gate.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a solid-state imaging device of converting light into an electric charge for detection and, particularly, to a solid-state imaging device with improved charge detection efficiency.  
         [0003]     2. Description of Related Art  
         [0004]      FIG. 1  shows the configuration of a typical CCD image sensor. As shown in  FIG. 1 , a typical CCD image sensor  10  includes a photodiode line  11 , a register  13 , a transfer gate  12 , and a charge detector  14 . The photodiode line  11  is formed of a line of photodiodes that convert incident light into a signal electron by photoelectric conversion to accumulate electric charges. The register  13  transfers a signal charge. The transfer gate  12  transfers a signal charge from the photodiode to the register  13 . The charge detector  14  converts a charge signal into a voltage signal.  
         [0005]     In the CCD image sensor  10  having such a configuration, the electric charge which is photoelectrically converted and accumulated in each photodiode is transferred through the transfer gate  12  to the register  13 . In the register  13 , the electric charge is sequentially transferred by two-phase driving to the charge detector  14 .  
         [0006]      FIG. 19  shows a charge detector that is typically used in the above CCD image sensor, which is referred to hereinafter as the related art 1. The charge detector  104  includes two output gates  201  and  202  which are connected to a final-stage transfer gate (register gate)  209  and supplied with a constant voltage, a reset gate  203 , and a reset drain  204  which is supplied with a constant voltage. The charge detector  104  converts an electric charge into a voltage and then transfers the voltage signal through a contact  105  to an amplifier  16  shown in  FIG. 1 . The amplifier  16  amplifies the voltage signal as needed and outputs the amplified signal.  
         [0007]     The electric charge in the charge detector  104  is abandoned to the reset drain  204  to which a constant voltage is applied when the reset gate  203  is set to High, thereby entering the reference output mode in which the output signal is 0.  
         [0008]     The CCD image sensor can convert from a smaller amount of electric charges into a larger amount of voltages as the detection efficiency is higher. The detection efficiency is a coefficient for converting an electric charge into a voltage. The high detection efficiency enables high-speed operation by suppressing the gain of the amplifier in the subsequent stage. Further, an increase in the signal gives a higher signal-to-noise (S/N) ratio.  
         [0009]     The detection efficiency is represented by the floating capacitance (=C) of the portion for accumulating electric charges in the charge detector and an elementary charge (=e) as follows: 
 
Detection efficiency= e/C ( V /electron). 
 
 Thus, the detection efficiency can be enhanced if the floating capacitance C is reduced. Because the floating capacitance C is a sum of the base capacitance and the side capacitance of the portion where electric charges are accumulated (i.e. floating diffusion: FD), the capacitance can be reduced by decreasing the area of the floating diffusion and the area of the side surfaces surrounding the portion. 
 
         [0010]      FIG. 20  shows another example of a charge detector as disclosed in Japanese Unexamined Patent Application Publication No. 1-196175, for example, which is referred to herein as the related art 2.  FIG. 20  corresponds to the section along XX-XX′ in  FIG. 19 . The charge detector includes a final-stage register gate  219 , an output gate  212 , a contact  215 , a reset gate  213   a , a reset gate  213   b  as a reset noise reduction gate to which a constant voltage is applied, a drain  214 , and a floating diffusion  216 . The reset noise reduction gate  213   b  which is supplied with a constant current is disposed in the previous stage of the reset gate  213   a , thereby enabling the reduction of reset noise.  
         [0011]     Further, a technique of establishing connection with a wide register or a narrow charge detector without deteriorating the charge transfer efficiency is disclosed in Japanese Unexamined Patent Application Publication No. 5-325589, which is referred to herein as the related art 3. According to this technique, the use of a narrow charge detector enables the reduction of floating capacitance to thereby enhance the detection efficiency.  
         [0012]     Because the area of the floating diffusion  216  and the area of the side surfaces surrounding this portion in the related art 2 is the same as that in the related art 1, the floating capacitance C stays the same. The detection sensitivity thus cannot be improved.  
         [0013]     According to the related art 3, if the width of the register is inherently narrow, it is unable to reduce the floating capacitance to enhance the detection efficiency. Further, because the area of the floating diffusion cannot be reduced drastically, the effect of enhancing the detection efficiency is small.  
       SUMMARY OF THE INVENTION  
       [0014]     According to an aspect of the present invention, there is provided a solid-state imaging device including a transfer element line transferring an electric charge photoelectrically converted in a photoelectric conversion element line formed of a plurality of photoelectric conversion elements, and a charge detector detecting an electric charge transferred by the transfer element line. The charge detector includes an output gate connected to a final stage of the transfer element line, a floating diffusion converting an electric charge transferred through the output gate into a voltage, a reset gate resetting the floating diffusion, and an addition gate formed above the floating diffusion and along an end from the output gate to the reset gate and supplied with a constant voltage.  
         [0015]     In this invention, because of the presence of the addition gate that is disposed above the floating diffusion and along the end from the output gate to the reset gate and supplied with a constant voltage, the potential gradient is given to the floating diffusion to thereby reduce the capacitance.  
         [0016]     The present invention thereby provides a solid-state imaging device capable of reducing the floating capacitance to improve the detection sensitivity. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:  
         [0018]      FIG. 1  is a pattern diagram showing a typical CCD image sensor;  
         [0019]      FIG. 2  is a view showing a charge detector of a CCD image sensor according to a first embodiment of the present invention;  
         [0020]      FIGS. 3A and 3B  are sectional views along the line III-III′ in  FIG. 1 ,  
         [0021]      FIG. 4  is a sectional view along the line IV-IV′ in  FIG. 2 ,  
         [0022]      FIG. 5  is a view showing potentials P 1  and P 2  in the section IV-IV′ and the section V-V′ in  FIG. 2 ;  
         [0023]      FIG. 6  is a view to describe the potential gradient along the points A 1 , B 1  and C 1  in  FIG. 2 ;  
         [0024]      FIG. 7  is a view showing a CCD image sensor according to a second embodiment of the present invention;  
         [0025]      FIG. 8  is a view showing a charge detector of charge composition type according to a related art;  
         [0026]      FIG. 9  is a view showing a charge detector according to a second embodiment of the invention;  
         [0027]      FIGS. 10A and 10B  are sectional views along the line X-X′ in  FIG. 9 ;  
         [0028]      FIG. 11  is a view showing a charge detector according to a third embodiment of the present invention;  
         [0029]      FIGS. 12A and 12B  are sectional views along the line XII-XII′ in  FIG. 11 ;  
         [0030]      FIG. 13  is a view showing a charge detector according to a fourth embodiment of the present invention;  
         [0031]      FIGS. 14A and 14B  are sectional views along the line XIV-XIV′ in  FIG. 13 ;  
         [0032]      FIG. 15  is a view showing the potential gradient along the line XIV-XIV′ in  FIG. 13 ;  
         [0033]      FIG. 16  is a view showing a charge detector according to a fifth embodiment of the present invention;  
         [0034]      FIGS. 17A and 17B  are sectional views along the line XVII-XVII′ in  FIG. 16 ;  
         [0035]      FIG. 18  is a view to describe the potential gradient along the points A 2 , B 2  and C 2  in  FIG. 16 ;  
         [0036]      FIG. 19  is a view showing a charge detector according to the related art 1; and  
         [0037]      FIG. 20  is a view showing a charge detector according to the related art 2. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0038]     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.  
       First Embodiment  
       [0039]     Exemplary embodiments of the present invention are described hereinafter in detail with respect to the drawings. To begin with, the configuration of a typical CCD image sensor is described hereinafter.  FIG. 1  shows the configuration of a typical CCD image sensor. As shown in  FIG. 1 , a CCD image sensor  10  includes a photodiode line  11 , a register  13 , a transfer gate  12 , and a charge detector  14 . The photodiode line  11  is formed of a line of photodiodes that convert incident light into a signal electron by photoelectric conversion to accumulate electric charges. The register  13  transfers a signal charge. The transfer gate  12  transfers a signal charge from the photodiode to the register  13 . The charge detector  14  converts a charge signal into a voltage signal.  
         [0040]     In the CCD image sensor  10  having such a configuration, the electric charge which is photoelectrically converted and accumulated in each photodiode is transferred through the transfer gate  12  to the register  13 . In the register  13 , the electric charge is sequentially transferred by two-phase driving to the charge detector  14 .  
         [0041]      FIG. 2  shows a charge detector of the CCD image sensor according to a first embodiment of the present invention. The charge detector of this embodiment has lower floating capacitance than the charge detector of the related art 1 shown in  FIG. 19  to thereby improve the detection sensitivity. To this end, the charge detector of this embodiment has two more gates in addition to the charge detector of the related art 1 shown in  FIG. 19 .  
         [0042]     Specifically, the charge detector  14  of this embodiment includes two output gates  21  and  22  which are disposed adjacent to a final transfer gate  29  and supplied with a constant voltage, a reset gate  23 , a reset drain  24  which is supplied with a constant voltage, and addition gates  31   a  and  31   b . In the charge detector  14 , a channel stopper  28  is formed below the final transfer gate  29  and the first output gate  21 , and a locos oxide film  27  is formed to extend from the second output gate  22  to the reset drain  24 . The charge detector  14  converts an electric charge into a voltage and then transfers the voltage signal through a contact  15  to an amplifier  16  shown in  FIG. 1 . The amplifier  16  amplifies the voltage signal as needed and outputs the amplified signal. The electric charge in the charge detector  14  is abandoned to the reset drain  24  to which a constant voltage is applied when the reset gate  23  is set to High, thereby entering the reference output mode in which the output signal is 0.  
         [0043]     The addition gates  31   a  and  31   b  are formed to act as a bridge between the reset gate  23  and the first and second output gates  21  and  22  which are adjacent to the final-stage register gate. The addition gates  31   a  and  31   b  are formed in a different layer from the second output gate  22  and the reset gate  23 . Therefore, compared with the related art in which the floating diffusion (floating capacitor) is a diffusion area surrounded by the second output gate  22 , the reset gate  23  and the locos oxide film  27 , the width of the diffusion area is narrowed by the addition gates  31   a  and  31   b  in this embodiment. Specifically, the floating diffusion of this embodiment is the area surrounded by the second output gate  22 , the addition gate  31   a , the reset gate  23 , and the addition gate  31   b  as shown in  FIG. 2 , which is smaller than that in the related art.  
         [0044]     The positions of the addition gates  31   a  and  31   b  are as follows.  FIG. 3A  shows the cross section along the line III-III′ in  FIG. 2 .  FIG. 3B  shows another example of the cross section. In  FIG. 3B , the elements corresponding to the first output gate  21 , the second output gate  22 , the reset gate  23 , the addition gate  31   b , and the final transfer gate  29  are indicated as a first output gate  21 ′, a second output gate  22 ′, a reset gate  23 ′, an addition gate  31   b ′, and a final transfer gate  29 ′, respectively.  
         [0045]     In the charge detector  14  of this embodiment, the addition gate  31   b  may be disposed above the reset gate  23  and the second output gate  22  above a silicon substrate  30  as shown in  FIG. 3A . The charge detector  14 , however, does not necessarily have the configuration of  FIG. 3A . For example, the addition gate  31   b ′ may be disposed below the reset gate  23 ′ and the second output gate  22 ′ as shown in  FIG. 3B . Thus, the configuration may be such that the addition gate  31   b  is disposed above the reset gate  23  and the second output gate  22  or the addition gate  31   b ′ is disposed below the reset gate  23 ′ and the second output gate  22 ′. They should be arranged so that the addition gates  31   a ,  31   b  ( 31   a ′,  31   b ′) is not short-circuited with the second output gate  22  ( 22 ′) or the reset gate  23  and ( 23 ′).  
         [0046]     The effects of this embodiment are described hereinafter.  FIG. 4  shows the cross section along the line IV-IV′ in  FIG. 2 .  FIG. 5  shows the potentials P 1  and P 2  in the cross section along the line IV-IV′ and the cross section along the line IV-IV′, respectively.  
         [0047]     As shown in  FIG. 5 , a constant voltage is applied to the addition gates  31   a  and  31   b  in order that the potentials below the addition gates  31   a  and  31   b  are in the range between the potential below the second output gate  22  (the middle part of the cross section V-V′) and the potential of the floating diffusion  26  (the bottom part of the cross section IV-IV′), that is, equal to or higher than the potential below the second output gate  22  and equal to or lower than the potential of the floating diffusion  26 . Due to the presence of the addition gates  31   a  and  31   b , the potential P 1  has a step-like shape in which the width of the part where the potential is deepest, i.e. the voltage is highest (the middle part of the cross section IV-IV′) is narrowed. By way of comparison,  FIG. 5  also shows the potential P 11  (the cross section XX-XX′) of the charge detector of the related art 1 which corresponds to the potential P 1  of this embodiment.  
         [0048]     The electrons flow to the part where the potential is deep (i.e. the voltage is high). As a result, the electrons are concentrated around the middle part where the potential well is deepest. By accumulating the electrons around the middle part and thereby reducing the volume of the accumulated electrons, the floating capacitance C can be reduced accordingly. Further, if the semiconductor substrate is P-type, a large amount of P+ is injected below the locos oxide film  27  for device isolation so that the concentration of P+ is high there. Therefore, the contact with an N-type diffusion layer as the floating diffusion  26  forms PN junction capacitance, which deteriorates the detection efficiency. By applying a voltage to the addition gates  31   a  and  31   b  so that the electrons are concentrated around the middle part of the floating diffusion  26 , a distance between the parts where the electrons are accumulated can be separated from the locos oxide film  27 , thereby eliminating the PN junction capacitance.  
         [0049]     In this way, this embodiment arranges the addition gates  31   a  and  31   b  so as to act as a bridge between the ends of the reset gate  23  and the second output gate  22  and applies a constant voltage to the addition gates  31   a  and  31   b . This embodiment thereby enables the reduction of the floating capacitance as a first effect. As described above, the detection efficiency is represented by the floating capacitance (=C) and the elementary charge (=e) as: 
 
Detection efficiency= e/C ( V /electron). 
 
 The reduction of the floating capacitance leads to the improvement of the detection efficiency to thereby increase the detection sensitivity. This embodiment further has the following effects. 
 
         [0050]     This embodiment also enables the reduction of reset noise as a second effect. The reset noise generally occurs in an output signal because the inductive portion of the reset pulse is superposed thereon. If the reset noise is low, the output can be amplified without range over before it is input to an analog-digital converter (ADC), thereby increasing the voltage resolution. Further, if the reset noise is low, the reset noise can be cancelled easily in a circuit of a subsequent stage.  
         [0051]     As described above, the presence of the addition gates  31   a  and  31   b  reduces a distance L (see  FIG. 2 ) where the reset gate  23  and the floating diffusion  26  contact with each other to thereby reduce the contact area thereof. In this configuration, the parasitic capacitance between the reset gate  23  and the floating diffusion  26  is reduced. Consequently, the floating diffusion  26  is less likely to be affected by the reset signal. Further, because the channel becomes wider toward the reset drain  24  in this configuration, the electrons which are accumulated below the reset gate  23  when the reset signal is OFF are more likely to flow toward the reset drain  24  than toward the floating diffusion  26 . The reset noise can be thereby reduced.  
         [0052]     This embodiment further enables, as a third effect, the suppression of a change in the floating capacitance in spite of misalignment. Because the reset gate  23  and the second output gate  22  are formed in the same layer, and the two addition gates  31   a  and  31   b  are formed in the same layer, the floating diffusion  26  can be horizontally interposed between the electrodes of the same layer (i.e. the reset gate  23  and the second output gate  22 , or the addition gates  31   a  and  31   b ). In this configuration, even if the position of the electrode formed of polysilicon or the like is displaced due to misalignment, for example, the area and shape of the floating diffusion  26  do not substantially change. The change in the floating capacitance can be thereby suppressed.  
         [0053]     This embodiment further enables, as a fourth effect, the smooth transfer of electric charges to the floating diffusion  26 .  FIG. 6  is a view to describe the potential gradient along the points A 1 , B 1  and C 1  in  FIG. 2 . In  FIG. 6 ,  29 _Low and  29 -High indicate the voltages which are applied to the final-stage register gate. A constant voltage is applied to the addition gates  31   a  and  31   b  so that they act in the same manner as a third output gate. This provides a sufficient channel width and a smooth potential gradient, thereby preventing the reduction of a charge transfer speed.  
         [0054]     Further, as a fifth effect, this embodiment allows electrons to drift away from the floating diffusion  26  toward the reset drain  24  easily, thereby shortening a minimum width of a reset pulse required. This reduces a required time for reset ON to thereby increase an electron drift speed upon reset ON.  
         [0055]     Although two addition gates are added in the configuration described in this embodiment, either one addition gate may be added instead with equal effects.  
       Second Embodiment  
       [0056]      FIG. 7  shows a CCD image sensor according to a second embodiment of the present invention. A CCD image sensor  40  of this embodiment includes a photodiode line  41 , a first register  43   a , a second register  43   b , a first transfer gate  42   a , a second transfer gate  42   b , and a charge detector  44 . The photodiode line  41  is formed of a line of photodiodes that convert incident light into a signal electron by photoelectric conversion to accumulate electric charges. The registers  43   a  and  43   b  transfer a signal charge. The transfer gates  42   a  and  42   b  transfer a signal charge from the photodiode to the registers  43   a  and  43   b . The charge detector  44  converts a charge signal into a voltage signal.  
         [0057]     In the CCD image sensor  40  having such a configuration, the electric charge which is photoelectrically converted and accumulated in each photodiode is transferred alternately through the transfer gates  42   a  and  42   b  to the registers  43   a  and  43   b , respectively. In the registers  43   a  and  43   b , the electric charge is sequentially transferred to the charge detector  44 . The charge detector  44  converts an electric charge into a voltage and then transfers the voltage signal through a contact  45  to an amplifier  46 . The amplifier  46  amplifies the voltage signal as needed and outputs the amplified signal.  
         [0058]     In the CCD image sensor having such a configuration where the charge detector  44  is shared by two registers  43   a  and  43   b , the effects described in the first embodiment, such as the reduction of the floating capacitance to improve the detection sensitivity and the reduction of reset noise, become more significant. The effect of the present embodiment is described herein below.  
         [0059]      FIG. 8  is a view showing a charge detector of charge composition type according to a related art.  FIG. 9  is a view showing a charge detector according to this embodiment, which is an enlarged view of the area S in  FIG. 7 .  FIGS. 10A and 10B  are sectional views along the line X-X′ in  FIG. 9 . In FIGS.  8  and  9 , the respective charge detectors include a contact  245 ,  45 , a first output gate  251 ,  51 , a second output gate  252 ,  52 , a reset gate  253 ,  53 , a drain  254 ,  54 , a floating diffusion  256 ,  56 , a locos oxide film  257 ,  57 , a channel stopper  258 ,  58 , and a register final gate  259   a ,  259   b ,  59   a ,  59   b.    
         [0060]     As shown in  FIG. 8 , in the charge detector  244  of two-phase driving type, the output gates  251  and  252  are narrowed for high-speed operation, and the reset gate  253  is placed so as to reduce the area of the floating diffusion  256 . In such a configuration, the reset gate is bent elbow-shaped, and the area in contact with the floating diffusion  256  largely increases. This causes an increase in reset noise. Further, because the floating capacitance exists in the contact area of the reset gate  253  and the floating diffusion  256 , the floating capacitance C cannot be reduced.  
         [0061]     On the other hand, the charge detector  44  of this embodiment has such a configuration that the addition gates  61   a  and  61   b  are added to the configuration of  FIG. 8  as in the first embodiment. This enables the reduction of the contact area with the reset gate  53  and the reduction of the area of the floating diffusion  56 . The floating capacitance C can be thereby reduced.  
         [0062]      FIG. 10A  shows the cross section along the line X-X′ in  FIG. 9 .  FIG. 10B  shows another example of the cross section, in which the corresponding elements are denoted by the corresponding reference numerals with an apostrophe (′). As in the first embodiment, the addition gate  61   b  may be disposed above the reset gate  53  and the second output gate  52  as shown in  FIG. 10A . Alternatively, the addition gate  61   b ′ may be disposed below the reset gate  53 ′ and the second output gate  52 ′ as shown in  FIG. 10B . Specifically, the configuration should be such that the layer of the addition gates  61   a ,  61   b  ( 61   a ′,  61   b ′) and the layer of the second output gate  52  ( 52 ′) are different in order that the addition gates  61   a ,  61   b  ( 61   a ′,  61   b ′) are not short-circuited with the reset gate  53  and ( 53 ′) or the second output gate  52  ( 52 ′).  
         [0063]     This embodiment has the effects of the reduction of the floating capacitance, the reduction of reset noise, the suppression of a change in the floating capacitance due to misalignment, the smooth transfer of electric charges to the floating diffusion and so on, as in the first embodiment. In addition, as shown in  FIG. 9 , this embodiment enables the further reduction of the area of the floating diffusion  56  compared with the first embodiment and also enables the reduction of the side capacitance in the contact area with the reset gate  53 , thereby further enhancing the effect of improving the detection sensitivity.  
       Third Embodiment  
       [0064]      FIG. 11  is a view showing a charge detector according to a third embodiment of the present invention. In the following description, the same elements as in the first embodiment shown in  FIG. 1  are denoted by the same reference numerals and not described in detail. As shown in  FIG. 11 , addition gates  71   a  and  71   b  are disposed in the position which is between the reset gate  23  and the second output gate  22  and in the upper end of the floating diffusion  26 . In this embodiment, one ends of the addition gates  71   a  and  71   b  overlap with the end of the second output gate  22 , and the other ends do not overlap with the reset gate  23 . In this configuration, the channel becomes wider toward the reset drain  24  because of the presence of the addition gates  71   a  and  71   b , and the electrons are more likely to flow toward the reset drain  24  upon reset ON. This shortens a minimum width of a reset pulse required.  
         [0065]      FIG. 12A  shows the cross section along the line XII-XII′ in  FIG. 11 .  FIG. 12B  shows another example of the cross section, in which the corresponding elements are denoted by the corresponding reference numerals with an apostrophe (′). As in the first embodiment, the addition gate  71   b  may be disposed above the reset gate  23  and the second output gate  22  as shown in  FIG. 12A . Alternatively, the addition gate  71   b ′ may be disposed below the reset gate  23 ′ and the second output gate  22 ′ as shown in  FIG. 12B . Specifically, the configuration should be such that the layer of the addition gates  71   a ,  71   b  ( 71   a ′,  71   b ′) and the layer of the second output gate  22  ( 22 ′) are different in order that the addition gates  71   a ,  71   b  ( 71   a ′,  71   b ′) are not short-circuited with the second output gate  22  ( 22 ′). This embodiment enables the reduction of the floating capacitance as in the first embodiment.  
         [0066]     Further, this embodiment can shorten a minimum width of a reset pulse required in addition to having the effects such as the reduction of the floating capacitance and the suppression of a change in the floating capacitance in spite of misalignment. This reduces a required time for reset ON to thereby increase an electron drift speed upon reset ON.  
       Fourth Embodiment  
       [0067]      FIG. 13  is a view showing a charge detector according to a fourth embodiment of the present invention. In this embodiment, addition gates  81   a  and  81   b  are disposed in the position which is between the reset gate  23  and the second output gate  22  and in the upper end of the floating diffusion  26 . In this embodiment, one ends of the addition gates  81   a  and  81   b  overlap with a part of the reset gate  23 , and the other ends do not overlap with the second output gate  22 . In this configuration, although the effect of reducing the floating capacitance is not as high as the first embodiment, the reset noise can be reduced equally to the first embodiment.  
         [0068]      FIG. 14A  shows the cross section along the line XIV-XIV′ in  FIG. 13 .  FIG. 14B  shows another example of the cross section, in which the corresponding elements are denoted by the corresponding reference numerals with an apostrophe (′). As in the first embodiment, the addition gate  81   b  may be disposed above the reset gate  23  and the second output gate  22  as shown in FIG.  14 A. Alternatively, the addition gate  81   b ′ may be disposed below the reset gate  23 ′ and the second output gate  22 ′ as shown in  FIG. 14B . Specifically, the configuration should be such that the layer of the addition gates  81   a ,  81   b  ( 81   a ′,  81   b ′) and the layer of the reset gate  23  ( 23 ′) are different in order that the addition gates  81   a ,  81   b  ( 81   a ′,  81   b ′) are not short-circuited with the reset gate  23  ( 23 ′). This embodiment enables the reduction in the floating capacitance as in the first embodiment.  
         [0069]      FIG. 15  is a view showing the potential gradient P 4  along the cross section XIV-XIV′ in  FIG. 13 . In  FIG. 15 ,  29 _High and  29 _Low indicate the voltages which are applied to the final-stage register gate, and  23 _Low and  23 _High indicate the voltages which are applied to the reset gate. The deepest part of the potential which surrounds the floating diffusion  26  where the voltage is highest in the first embodiment is below the addition gates  31   a  and  31   b , and the second-deepest part is below the second output gate  22 .  
         [0070]     In this embodiment, on the other hand, a constant current is applied to the addition gates  81   a  and  81   b  in order that the potential below the addition gates  81   a  and  81   b  is smaller than the potential below the second output gate  22 . In such voltage setting, the deepest (greatest) part of the potential surrounding the floating diffusion  26  is below the second output gate  22 . Consequently, a potential difference R 1  between the potential of the floating diffusion  26  and the potential below the second output gate  22  is larger than the potential difference in the first embodiment. As a result, the dynamic range of the detection electric charge in this embodiment is wider than that in first to third embodiments.  
         [0071]     Therefore, this embodiment has the effect of preventing a decrease in the dynamic range in addition to the effects of reducing the floating capacitance and reducing the reset noise because of the presence of the addition gates  81   a  and  81   b.    
       Fifth Embodiment  
       [0072]      FIG. 16  is a view showing a charge detector according to a fifth embodiment of the present invention. In this embodiment, a second output gate  92  and the reset gate  23  are formed of electrodes in different layers. Further, the both ends of the second output gate  92  are extended to the reset gate  23  so that the second output gate  92  has a horseshoe-shape. The second output gate  92  of this embodiment is equivalent with a combination of the second output gate  22  and the addition gates  31   a  and  31   b  of the first embodiment which are formed integrally of the same electrode. This embodiment thus has the same effects regarding the floating capacitance and the reset noise as in the first embodiment.  
         [0073]      FIG. 17A  shows the cross section along the line XVII-XVII′ in  FIG. 16 .  FIG. 17B  shows another example of the cross section, in which the corresponding elements are denoted by the corresponding reference numerals with an apostrophe (′). The second output gate  92  may be disposed above the reset gate  23  as shown in  FIG. 17A . Alternatively, the second output gate  92 ′ may be disposed below the reset gate  23 ′ as shown in  FIG. 17B . Specifically, the configuration should be such that the layer of the second output gate  92  ( 92 ′) and the layer of the reset gate  23  ( 23 ′) are different in order that the second output gate  92  ( 92 ′) is not short-circuited with the reset gate  23  ( 23 ′). This embodiment enables the reduction in the floating capacitance as in the first embodiment and further enables the reduction in reset noise.  
         [0074]      FIG. 18  is a view showing the potential gradient P 5  along the points A 2 , B 2 , C 2  in  FIG. 16 . By way of comparison,  FIG. 18  also shows the potential gradient P 3  along the cross section A 1  to C 1  in the first embodiment. In the first embodiment, three gates, i.e. the first and second output gates and the addition gates, are employed and a voltage is applied to the floating capacitance so that the potential increases gradually. A difference between the potential of the floating diffusion  26  and the potential below the addition gates is R 3  in the first embodiment.  
         [0075]     This embodiment, on the other hand, employs two gates to thereby increase a difference R 2  between the potential of the floating diffusion  26  and the potential below the second output gate  92  by the amount of the potential difference in one stage. This enlarges the dynamic range compared with the first to third embodiments.  
         [0076]     In this embodiment, the both ends of the second output gate are extended to the reset gate so that the second output gate has a horseshoe-shape to cover the end of the floating diffusion. This configuration reduces the floating capacitance and also reduces the reset noise. In addition, because the second output gate is combined with the addition gate, this embodiment further prevents the reduction of the dynamic range compared with the first embodiment or the like.  
         [0077]     As described in the foregoing, the first to fifth embodiments enable the reduction of floating capacitance to thereby improve the detection sensitivity. The first, second, fourth, and fifth embodiments enable the reduction of reset noise. The first to fourth embodiments enable the suppression of a change in floating capacitance in spite of misalignment. The first to third embodiments enable the smooth transfer of electric charges to the floating diffusion. The fourth and fifth embodiments prevent the reduction of dynamic range. The first to third embodiments enable the reduction of a required time of applying a reset pulse.  
         [0078]     It is apparent that the present invention is not limited to the above embodiment that may be modified and changed without departing from the scope and spirit of the invention.