Abstract:
A power supply circuit providing selectable voltages, includes a signal input control circuit, a power output control circuit, and a power output switching circuit. The signal input circuit is for connecting external devices to the motherboard. The output control circuit includes a first output control circuit for outputting a first voltage, a second output control circuit for outputting a second voltage and a third output control circuit for outputting a third voltage. The power output switching circuit is used for switching between the first output control circuit and the second output control circuit.

Description:
FIELD 
       [0001]    The subject matter herein generally relates to power supplies. 
       BACKGROUND 
       [0002]    Computers have become part of our daily life. There may be two input/output devices connected to the computer, one requires no power supply, such as a mouse, the other requires a power supply, such as a printer. The power supplies required by common output devices are mostly 5V, 12V, or 24V, and different output devices need different external power supplies. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
           [0004]      FIG. 1  is a circuit diagram of a signal input control circuit of a selectable power supply circuit. 
           [0005]      FIG. 2  is a circuit diagram of a power supply output control circuit of the power supply circuit of  FIG. 1 . 
           [0006]      FIG. 3  is a circuit diagram of a power supply output switch circuit of the power supply circuit of  FIG. 1 . 
           [0007]      FIG. 4  is a structure diagram of the power supply circuit of  FIG. 1  used with a computer host and output devices. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiment described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure. 
         [0009]    The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
         [0010]    The present disclosure is in relation to a power supply circuit. 
         [0011]      FIGS. 1 to 4  illustrate one or more embodiment of a power supply circuit. A basic input output system (BIOS) controls an RI signal of an external device  110 , such as a data input device, to input to a computer host  100 , or control the computer host  100  to output a voltage of 5V or 12V or 24V to external devices  120 ,  130 , and  140  respectively, such as an audio player, a printer, or a scanner. In this embodiment, the RI signal is a ringing instruction signal of a data input device. The RI signal is communicated through a ninth pin (COM 1 A-pin9) of a serial data interface RS-232C connected between the computer host  100  and the external device  110 , such as a data machine. The computer host  100  outputs a voltage of 5V, 12V, or 24V through the ninth pin (COM 1 A-pin9) of the serial data interface RS-232C connecting the computer host  100  and the external device  110 . 
         [0012]    The power supply circuit comprises a signal input control circuit  10 , a power output control circuit  20 , and a power output switching circuit  30 . 
         [0013]    The signal input control circuit  10  comprises an AND gate U 1 , three n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) Q 1 -Q 3 , and three resistors R 1 -R 3 . The two input terminals of the AND gate U 1  respectively receive two control signals GPIO 40  and GPIO 41 . The output terminal of the AND gate U 1  outputs a first selection signal GPIOA 1 . The output terminal of the AND gate U 1  is connected to a gate of the MOSFET Q 1 . The gate of the MOSFET Q 1  is connected to a first power source 3VSB through the resistor R 1 . A source of the MOSFET Q 1  is grounded. A drain of the MOSFET Q 1  is connected to a second power source 3VSB through the resistor R 2 . The drain of the MOSFET Q 1  is connected to a gate of the MOSFET Q 2 . A drain of the MOSFET Q 2  is connected to a power source 12V through a resistor R 3  and is connected to a gate of the MOSFET Q 3 . A source of the MOSFET Q 2  is grounded. A drain of the MOSFET Q 3  functions as a signal input X of the signal input control circuit  10 , and a source of the MOSFET Q 3  functions as a signal output Y of the signal input control circuit  10 . In this embodiment, the two control signals GPIO 40  and GPIO 41  are controlled by the BIOS. 
         [0014]    The power output control circuit  20  comprises a first output control circuit  22 , a second output control circuit  24 , and a third output control circuit  26 . The first output control circuit  22  can output a voltage of 5V to the external device  120 . The second output control circuit  24  can output a voltage of 12V to the external device  130 . The third output control circuit  26  can output a voltage of 24V to the external device  140 . 
         [0015]    The first output control circuit  22  comprises three n-channel MOSFETs Q 4 -Q 6 , a resistor R 4 , and a capacitor C 1 . A gate of the MOSFET Q 4  receives the control signal GPIO 40 . A source of the MOSFET Q 4  is grounded. A drain of the MOSFET Q 4  is connected to a power source 12V through the resistor R 4 . The drain of the MOSFET Q 4  is grounded through the capacitor C 1 . The drain of the MOSFET Q 4  is connected to a first switch signal COM 1 −5V. A gate of the MOSFET Q 5  is connected to a node between the MOSFET Q 4  and the resistor R 4 . A drain of the MOSFET Q 5  is connected to a power of VCC 5V. A source of the MOSFET Q 5  is connected to a source of the MOSFET Q 6 . A gate of the MOSFET Q 6  is connected to a node between the MOSFET Q 4  and the resistor R 4 . A drain of the MOSFET Q 6  outputs a first signal Vout through a fuse F. 
         [0016]    The second output control circuit  24  comprises three n-channel MOSFETs Q 7 -Q 9 , a resistor R 5 , a resistor R 6 , and a capacitor C 2 . A gate of the MOSFET Q 7  receives the control signal GPIO 41 . A source of the MOSFET Q 7  is grounded. A drain of the MOSFET Q 7  is connected to a power of 24V through the resistor R 5 . A node between the MOSFET Q 7  and the resistor R 5  is grounded through the resistor R 6 . The node between the MOSFET Q 7  and the resistor R 5  is grounded through the capacitor C 2 . The node between the MOSFET Q 7  and the resistor R 5  is connected to a second switch signal COM 1 −12V. A gate of the MOSFET Q 8  is connected to the node between the MOSFET Q 7  and the resistor R 5 . A drain of the MOSFET Q 5  is connected to a power source of +12V. A source of the MOSFET Q 8  is connected to a source of the MOSFET Q 9 . A gate of the MOSFET Q 9  is connected to the node between the MOSFET Q 7  and the resistor R 5 . A drain of the MOSFET Q 9  outputs a second signal Vout through the fuse F. 
         [0017]    The third output control circuit  26  comprises three n-channel MOSFETs Q 10 -Q 12 , a p-channel MOSFET Q 13 , three resistors R 7 -R 9 , and two capacitors C 3 -C 4 . A gate of the MOSFET Q 10  receives the control signal GPIO 40 . A source of the MOSFET Q 10  is grounded. A drain of the MOSFET Q 10  is connected to a power source 3VSB through the resistor R 7 . A gate of the MOSFET Q 11  receives the control signal GPIO 41 . A source of the MOSFET Q 11  is grounded. A drain of the MOSFET Q 11  is connected to a node between the MOSFET Q 10  and the resistor R 7  and outputs a second switch signal GPIOA 2 . A gate of the MOSFET Q 12  is connected to a node between the MOSFET Q 11  and the resistor R 7 . A drain of the MOSFET Q 12  is connected to a power source +24V through the resistor R 8  and resistor R 9 . A source of the MOSFET Q 12  is grounded. One end of the capacitor C 3  is connected to a node of the resistor R 8  and resistor R 9 , and the other end of the capacitor C 3  is grounded. One end of the capacitor C 4  is connected to the node between the resistor R 8  and resistor R 9 , and the other end of the capacitor C 4  is connected to a source of the MOSFET Q 13 . A gate of the MOSFET Q 13  is connected to a node between the resistor R 8  and resistor R 9 . A source of the MOSFET Q 13  is connected to a power source of +24V. A drain of the MOSFET Q 13  outputs a third signal Vout through the fuse F. 
         [0018]    The power output switching circuit  30  can switch between an output voltage of 5V and 12V. The power output switching circuit  30  comprises an OR gate U 2 , a resistor R 10 , and two n-channel MOSFETs Q 14 -Q 15 . Two input ends of the OR gate respectively receive the first control signal GPIOA 1  and the second control signal GPIOA 2 , and an output end of the OR gate is grounded through the resistor R 10 . The output end of the OR gate U 2  is connected to the gate of the MOSFET Q 14  and the gate of the MOSFET Q 15 . A drain of the MOSFET Q 14  is connected to the drain of the MOSFET Q 15  for outputting the first switching signal COM 1 −5V. A source of the MOSFET Q 14  is grounded. A drain of the MOSFET Q 15  is connected to a drain of the MOSFET Q 7  for outputting a second switching signal COM 1 −12V. 
         [0019]    When the control signal GPIO 40  and GPIO 41  are both low, the AND gate U 1  outputs a low signal, the first selection signal GPIOA 1  is low, and the control circuit  10  is turned off. The control signals GPIO 40  and GPIO 41  are both low, and the MOSFET Q 10  and MOSFET Q 11  of the third output control circuit  26  are turned off. The second selection signal GPIOA 2  is connected to the power source of 3V and gets a high signal, thus the MOSFET Q 12  is turned on. The resistor R 8  reduces the voltage of the gate of the MOSFET Q 13  to lower than 24V. The voltage of the power source of the MOSFET Q 13  is 24V, so the voltage of the gate is lower than the power source voltage of the MOSFET Q 13 , and the MOSFET Q 13  is turned on. The third signal Vout output from the third output control circuit  26  is 24V. 
         [0020]    The second selection signal GPIOA 2  is high and the first selection signal GPIOA 1  is low. The OR gate U 2  of the power output switching circuit  30  outputs a high signal and the MOSFET Q 14  and the MOSFET Q 15  are turned on. The first switching signal COM 1 −5V and the second switching signal COM 1 −12V are both low, and make the MOSFETs Q 5 , Q 6 , Q 8 , and Q 9  turn off. The first output control circuit  22  and the second output control circuit  24  have no output. 
         [0021]    When the control signal GPIO 40  is a high signal, the control signal GPIO 41  is low, the AND gate U 1  outputs a low signal, the first selection signal GPIOA 1  is low, and the control circuit  10  is turned off. The control signal GPIO 41  is low and the MOSFET Q 7  of the second output control circuit  24  is turned off. The gate of the MOSFET Q 7  is a high signal and the gates of the MOSFET Q 8  and the MOSFET Q 9  have high signals. The MOSFET Q 8  and the MOSFET Q 9  are turned on. The second signal Vout output from the second output control circuit  24  is 12V. 
         [0022]    The control signal GPIO 40  is a high signal, the MOSFET Q 10  of the third output control circuit  26  is turned on, the MOSFET Q 11  is turned off, so the second selection signal GPIOA 2  is low, and the MOSFET Q 12  is turned off. A gate voltage of the MOSFET Q 13  is equal to the source voltage of the MOSFET Q 13  and the MOSFET Q 13  is turned off. The third output control circuit  26  has no output. 
         [0023]    The control signal GPIO 40  is high signal, the MOSFET Q 4  of the first output control circuit  22  is turned on, the drain of the MOSFET Q 4  is low, and the gates of the MOSFET Q 5  and the MOSFET Q 6  are low. The MOSFET Q 5  and the MOSFET Q 6  are turned off, and the first output control circuit  22  has no output. 
         [0024]    When the control signal GPIO 40  is low, the control signal GPIO 41  is high signal, the AND gate U 1  outputs a low signal, the first selection signal GPIOA 1  is low, the control circuit  10  is turned off. The control signal GPIO 40  is low, the MOSFET Q 4  of the first output control circuit  22  is turned off. The gates of the MOSFET Q 5  and the MOSFET Q 6  are high signal. The MOSFET Q 5  and the MOSFET Q 6  are turned on. The first signal Vout output from the first output control circuit  22  is 5V. 
         [0025]    The control signal GPIO 41  is a high signal, the MOSFET Q 11  of the third output control circuit  26  is turned on, so the second selection signal GPIOA 2  is low, and the MOSFET Q 12  is turned off. The gate voltage of the MOSFET Q 13  is equal to the source voltage of the MOSFET Q 13  and the MOSFET Q 13  is turned off. The third output control circuit  26  has no output. 
         [0026]    The control signal GPIO 41  is a high signal, the MOSFET Q 7  of the second output control circuit  24  is turned on and the gates of the MOSFET Q 8  and the MOSFET Q 9  are low. The MOSFET Q 8  and the MOSFET Q 9  are turned off, and the second output control circuit  24  has no output. 
         [0027]    When the control signal GPIO 40  and GPIO 41  are both high signals, the AND gate U 1  of the control circuit  10  outputs a high signal, the first selection signal GPIOA 1  is a high signal, and the MOSFET Q 1  is turned on. The gate of the MOSFET Q 2  is low, and the MOSFET Q 2  is turned off. The gate of the MOSFET Q 3  is a high signal and the MOSFET Q 3  is turned on, thus an external device, such as a modem, can communicate with a computer host through the MOSFET Q 3 . 
         [0028]    The control signal GPIO 40  and GPIO 41  are both high signals and the MOSFET Q 10  and the MOSFET Q 11  of the third output control circuit  26  are turned on. The second selection signal GPIOA 2  is low and the MOSFET Q 12  is turned off. So the voltage of the gate is equal to the power source voltage of the MOSFET Q 13 , and the MOSFET Q 13  is turned off. The third output control circuit  26  has no output. 
         [0029]    The control signal GPIO 40  is a high signal and the MOSFET Q 4  of the first output control circuit  22  is turned on. The gate of the MOSFET Q 4  is low. The gates of the MOSFET Q 5  and the MOSFET Q 6  are low. The MOSFET Q 5  and the MOSFET Q 6  are turned off. The first output control circuit  22  has no output. 
         [0030]    The control signal GPIO 41  is a high signal, the MOSFET Q 7  of the second output control circuit  24  is turned on, and the gates of the MOSFET Q 8  and the MOSFET Q 9  are low. The MOSFET Q 8  and the MOSFET Q 9  are turned off, and the second output control circuit  24  has no output. 
         [0031]    Users can choose the output voltage or the input signal by setting the control signals GPIO 40  and GPIO 41 . 
         [0032]    It is to be understood, however, that even though numerous characteristics and advantages of the embodiments have been set forth in the foregoing description, together with details of the structure and function of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.