Abstract:
A keyboard operated musical instrument is disclosed in which the number of tone generators can be less than the number of keyswitches in a keyboard array of keyswitches. A binary-tree search is programmed to search subsets of the keyswitches to find keyswitches that have been actuated. The subsets are selected in an adaptive fashion which minimizes the search time required to detect and identify all the actuated keyswitches. A modular assignment subsystem is described whereby tone generators are assigned to actuated keyswitches according to a predetermined priority logic.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     A hardware problem can arise in the economical implementation of a keyswitch detect means in a keyboard operated electronic musical instrument which is constructed with microelectronic circuits. This problem is one of interfacing signal leads from a large number of keyswitches to a limited number of leads that are usually available in microelectronic circuit packages. 
     One approach that has been employed to deal with the multiple lead interfacing problem is to use time division multiplexing of the keyswitch states. This technique is implemented by assigning a unique time slot to each keyboard switch. The state of each keyswitch is indicated by the presence or absence of a signal pulse in the time slot assigned to the switch. An advantage of time division multiplexing is that the entire status of all the instrument&#39;s keyboard switches can be transmitted on a single signal wire. A negative attribute of time division multiplexing is that the scanning, or search, time for the multiplicity of keyswitches is fixed and is independent of the number of keyswitches that have been closed, or actuated. Such a fixed scan time can be a detrimental attribute of a keyswitch detect system because the wasted time used to sequentially scan an entire array of keyswitches when only a limited small number could possibly be actuated can result in a loss or delay of a keyswitch state change detection when the musician plays very fast. A time division multiplex note detection system is described in U.S. Pat. No. 3,610,799. 
     A time division multiplex system for a keyboard operated electronic musical instrument is described in U.S. Pat. No. 4,022,098. In the system described in this patent provision is made for intermanual coupling. By using pulse controlled sequential connection of manual coupling and keyboard switches an economy in wiring is obtained and keys operated on one keyboard can cause tones to sound which are associated with the same or another keyboard. 
     A keyswitch detect and assignor system for a keyboard operated electronic musical instrument is described in U.S. Pat. No. 4,022,098. In the described system the keyboard switches are arranged in groups of P switches, with Q groups per set of switches, and S sets of switches per keying system. During a search cycle, each group of P switches is sequentially examined to detect a change in a switch state of any member since the preceding search cycle. A change in a switch state causes the system to enter into an assign node cycle during which a data word is created in memory corresponding to a newly detected switch closure, or is removed from memory corresponding to a newly detected switch opening. After an assignment of a newly detected switch closure has been completed the system returns to the search cycle. 
     SUMMARY OF THE INVENTION 
     In a keyboard operated musical instrument having an array of keyswitches and having a number of tone generators that is generally less than the number of keyswitches, a keyswitch detect system is employed which detects actuated keyswitches and assigns tone generators to these keyswitches. 
     A binary-tree search is implemented which efficiently and quickly determines which keyswitches have been actuated without having to test each keyswitch on an individual basis. Preselected subsets of the keyswitches are tested simultaneously. Changes in the subsets are made in a programmed manner which is adaptive to the test results. The test results for each group are encoded so that at the end of each complete search sequence all the actuated keyswitches have been assigned identification code numbers. The search sequence is not fixed in time but varies adaptively to the set of keyswitches that have been actuated. 
     A modular assignment logic is used to assign tone generators to the actuated keyswitches. Any number of assignors can be used without any change in the system logic or timing functions. The assignment is made on the basis of a predetermined priority logic. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The detailed description of the invention is made with reference to the accompanying drawings wherein like numerals designate like components in the figures. 
     FIG. 1 is a schematic diagram of an embodiment of the invention. 
     FIG. 2 is a schematic diagram of switches connected for a binary-tree search. 
     FIG. 3 is a schematic diagram of the keyboard switch array 14. 
     FIG. 4 is a schematic diagram of the utilization means 23. 
     FIG. 5 is a schematic diagram of the assignor 25. 
     FIG. 6 is a schematic diagram of the priority logic 29. 
     FIG. 7 is a schematic diagram of an alternate embodiment of the invention. 
     FIG. 8 is a schematic diagram of the invention incorporated into a musical instrument. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is directed toward a system for detecting the change of states in a keyboard array of keyswitches and for assigning tone generators to actuated keyswitches. 
     FIG. 1 shows an embodiment of the present invention as incorporated into a keyboard operated electronic musical tone generator. The system searches for switch closures, or switch actuations (&#34;on&#34; switch state) using a search algorithm which is often referred to as a &#34;binary-tree search.&#34; A general description of a binary-tree search algorithm is presented in the technical article: A. Chaturvedi, &#34;Tree Structures.&#34; PC Tech Journal, February 1985, pp 78-87. 
     The general form of a binary-tree search algorithm is illustrated in FIG. 2 for a set of 16 keyswitches. The search operation starts by applying a logic &#34;1&#34; state signal to node B which is connected to the left half, or left 8 switches of the keyswitch array. All the output signals from the entire array of keyswitches are combined on the single signal detect line. If a &#34;1&#34; signal on node B causes a &#34;1&#34; signal on the signal detect line then at least one of the keyswitches in the left-half of the keyswitch array must be actuated (closed switch position). If a &#34;1&#34; signal is detected at any search state, such as the first for node B, then the search is extended to the next lower node. The left node is also chosen first when the search is extended to a lower node. The search continues in this one-half search sequence until either the search stage reaches a single keyswitch or until a &#34;1&#34; signal on a node produces a &#34;0&#34; state on the signal detect line. 
     For illustration, assume that in FIG. 2 switches 3 and 12 are closed and all the other switches are open. At the first step in the binary-tree search a &#34;1&#34; signal is transmitted from node A to node B. A &#34;1&#34; signal will appear on the signal detect line because switch 3 is connected to node B via nodes F and C. At the second step in the search, a &#34;1&#34; signal is transmitted through nodes B and C. A &#34;1&#34; signal will appear on the signal detect line because switch 3 is connected to node C via node F. At the third step a &#34;1&#34; signal is transmitted via nodes, A,B,C to node E. At the third step a &#34;0&#34; signal will appear on the signal detect line. The appearance of the &#34;0&#34; signal causes the search to return to the last successful node, which in the illustrative case is node C, and then the tree to the right of this node, node F, is selected for the next step. Therefore at the fourth step a &#34;1&#34; signal is transmitted to node F via nodes A,B, and C. A &#34;1&#34; signal will occur on the signal detect line because the actuated switch 3 is connected to the node F. Then a &#34;1&#34; signal is transmitted via nodes A,B,C,F and R. The appearance of a &#34;1&#34; signal on the signal detect line now verifies that switch 3 has been detected to be in its actuated state. 
     At the next step the search returns to the last successful multiple node F and then a search to the right is made by transmitting a &#34;1&#34; signal via nodes A,B,D,F to S. Since switch 4 is not actuated a &#34;0&#34; signal will appear on the signal detect line. Thus the search will again return to the last highest successful node which is node B and the next search step will investigate the network nodes to the right of B. A &#34;1&#34; pulse is now transmitted via nodes A,B and D. Since none of the keyswitches in the corresponding nodes are actuated, a &#34;0&#34; signal will appear on the signal detect line. 
     The search now returns to the last highest successful node which is node A and the next search step will be to investigate the network nodes to the right of node A. The next step will be to send a &#34;1&#34;  signal to node J via nodes A and I. Since switch 12 is connected to node J a &#34;1&#34; signal to node L via nodes A,I, and J. A &#34;0&#34; signal will appear on the signal detect line. The search then returns to J which is the last successful node. The next step is to transmit a &#34;1&#34; signal to Node M via nodes A,I, and J. A &#34;1&#34; signal will appear on the signal detect line so the next step is to transmit a &#34;1&#34; signal to node Z via nodes A,I,J, and M. A &#34;0&#34; signal will appear on the signal detect line. The search returns to the last successful node M and a &#34;1&#34; signal is then transmitted via nodes A,I,J, and M to node AA. A &#34;1&#34; signal on the signal detect line now verifies that switch 12 has been detected to be in its actuated state. 
     At the next step the search returns to the last highest successful node I and then a search to the right is made by transmitting a &#34;1&#34; signal via nodes A and I to node K. A &#34;0&#34; signal will appear on the signal detect line because none of the keyswitches connected to node K are in their actuated state. The search now returns to node A and the entire search sequence is repeated. 
     To illustrate the system operation of the system shown in FIG. 1, the keyboard swithc array 14 comprises an array of 64 keyswitches. This number is chosen for illustrative purposes and does not imply a limitation or restriction for the present invention. The manner of extending the number of keyswitches will be evident from the following description. 
     The logic clock provides timing signals which are used to time the operation of the various system components. Adder 11 is implemented to add modulo 126 which is two less than two times the number of switches in the array of keyswitches contained in the keyboard switch array 14. 
     The content of the adder 11 is used to address data words out from the keycode memory 12. The data words stored in the keycode memory 12 are listed in Table 1. ##SPC1## 
     Each bit of the keycode data word, shown in the second column of Table 1, which is read out from the keycode memory 12 is connected to an individual keyswitch contained in the keyboard switch array 14 with the LSB (least significant bit) connected to the keyswitch having the digit one as its identifying number. The MSB (most significant bit) is connected to the keyswitch having the number 64 as its identifying number. FIG. 3 illustrates the detail of the keyboard switch array 14. 
     The data words stored in the keycode memory 12 apply the same binary-tree search code signals to the array of keyswitches corresponding to the search nodes shown in FIG. 2. The data shown in the columns labeled Inc and Action in Table 1 are listed in their equivalent decimal form as a space saving abbreviation. In practice these data would also be stored in a binary digital format and the description will assume that these numbers are in the equivalent binary digital format. 
     The output signals from the keyswitches in the keyboard switch array 14 are combined onto a single signal detect line by means of the switch data combine 15. the switch data combine 15 can be implemented as a multi-input OR-gate. A simpler implementation is to use diodes or resistors in series with each switch&#39;s output line and to connect the other ends in common to the signal detect line. 
     For notational convenience, the keyswitches are numbered with zero for the lowest keyswitch on the keyboard. The lowest keyswitch corresponds to the lowest frequency musical tone generated the musical instrument. In Table 1, the left-most bit in keycode word corresponds to the keyswitch numbered as zero. 
     In response to each data word read out from the keycode memory 12 either a logic binary state of &#34;0&#34; or &#34;1&#34; will appear on the signal detect line connected to the output of the switch data combine 15. If at any stage in the search sequence a &#34;1&#34; signal appears on the signal detect line and the Action word for the data word read out from the keycode memory is a logic binary &#34;0&#34;, then the AND-gate 17 transmits a &#34;0&#34; signal to the select gate 18. In response to the value of the Inc signal read out from the keycode memory 12 along with the Keycode data word, the select gate 18 places the binary state output from the AND-gate 17 into the latch at the bit location corresponding to the Inc signal value. The same data store will also take place if the AND-gate 17 produces a &#34;1&#34; logic binary state. As explained below the action of the combination of the AND-gate 18, the Inc signal, and the select gate 18 is to place a binary digital number in the latch 19 which identifies any keyswitch which is found to be in its actuated keyswitch state. 
     If a &#34;1&#34; signal appears on the signal detect line, then the gate 22 transmits a &#34;1&#34; logic signal to the adder 11. The delay 13 causes the adder 11 to have the previous count added to the value transmitted to it by the gate 22. Thus a &#34;1&#34; signal on the signal detect lines simply increments the adder 11 to its next highest count. If a &#34;0&#34; signal appears on the signal detect lines, then the gate 22 transmits the current value of the Inc read out of the keycode memory 12 to the adder 11. 
     If the Inc signal has a zero value then the increment 21 sends a binary logic &#34;1&#34; singal to the AND-gate 24. If at the same time the logic &#34;1&#34; appears on the signal detect line then the AND-gate 24 sends a &#34;1&#34; signal to the gate 20. In response to an input &#34;1&#34; signal, the gate 20 transfers the keyswitch identification code word from the latch 19 to the utilization means. 
     Table 2 lists the system operation steps for an illustrative situation in which only switches 3 and 41 are simultaneously closed. Each time that the adder 11 is incremented so that it returns to its initial state a SCAN START signal is generated. In a manner described below, the utilization means 23 uses the SCAN START signal for the assignment of system operations such as the assignment of the tone generators in a keyboard operated musical instrument. 
     
                       TABLE 2______________________________________                                       GateStep Adder 11 Detect signal                    Action Inc  Latch 19                                       20______________________________________ 1    0       1          0      63   0----- N 2    1       1          0      31   00---- N 3    2       1          0      15   000--- N 4    3       1          0      7    0000-- N 5    4       0          0      3    00000- N 6    5       1          1      3    00001- N 7    6       0          0      1    000010 N 8    9       1          1      1    000011 Y 9   10       0          7      1    000011 N10   17       0          15     1    000011 N11   32       0          31     1    000011 N12   63       1          1      63   100011 N13   64       1          0      31   100011 N14   65       0          0      15   100011 N15   80       1          1      15   101011 N16   81       1          0      7    101011 N17   82       1          0      3    101001 N18   83       1          0      1    101001 Y19   84       0          1      1    101001 N20   85       0          3      1    101001 N21   88       0          7      1    101001 N22   95       0          1      31   101001 N23   126 = 0  0          0      63   001001 N______________________________________ 
    
     An examination of the first keycode word addressed out from the keycode address for the adder 11 value of 0 is that a &#34;1&#34; signal will appear on the signal detect line because keyswitch 3 is actuated and it receives a logic &#34;1&#34; signal. Since the action value for word 0 has a &#34;0&#34; value, the AND-gate 17 transfers a &#34;0&#34; signal to the select gate 18. The select gate 18 will place a &#34;0&#34; in the latch 19 at the 6th bit position as directed by the current 63 value of the Inc read out from the keycode memory. Thus at this first step the latch 19 will have the keyswitch identification code word 0-----. A dash indicates that the bit state at this position can have any value such as that remaining from a previous binary tree search of a set of nodes. The N in the last column of Table 2 indicates that the gate 20 does not transfer the keyswitch identification code word to the utilization means. 
     In response to a &#34;1&#34; state on the signal detect line, the gate 22 will select a &#34;1&#34; signal to be sent ot the adder 11. The adder 11 in combination with the delay 13 now has the count state of 1. 
     The second keycode word in Table 1 is now read out of the keycode memory 12. It is noted from an examination of this word that because keyswitch 3 is actuated, a &#34;1&#34; state will appear on the signal detect line. Since the action now has a &#34;0&#34; value, the select gate 18 will place a &#34;0&#34; in the latch 19 at the 5th bit position as directed by the value of the Inc =31. At this stage in the search sequence, the latch 19 will contain the keyswitch identification code word of 00----. 
     In the manner previously described, the &#34;1&#34; state on the signal detect line will cause the adder 11 to be incremented to the binary state corresponding to the decimal value of 2. 
     The third word in Table 1 is now read out of the keycode memory 12. Again a &#34;1&#34; will appear on the signal detect line because a &#34;1&#34; signal has been sent to the actuated keyswitch 3. Because the action has a &#34;0&#34; value, the select gate 18 will place a &#34;0&#34; in the latch 19 at the 4th bit position as directed by the value of the Inc=15. At this stage in the search sequence the latch 19 will contain the keyswitch identification code word of 000---. 
     In response to the &#34;1&#34; state on the signal detect line, the adder 11 will be incremented to the state 3 in the manner previously described. 
     The 4th word in Table 1 is now read out of the keycode memory 12. Since switch 3 is actuated, a &#34;1&#34; will appear on the signal detect line. Because at this stage the action has a &#34;0&#34; value, the select gate 18 will place a &#34;0&#34; in the latch 19 at the 3rd bit position as directed by the value of the Inc=7. At this stage the latch 19 will contain 0000-- as the keyswitch identification code word. 
     In response to the &#34;1&#34; state on the signal detect line, the adder 11 will be incremented to the state 4 in the manner previously described. 
     The 5th word in Table 1 is now read out of the keycode memory 12. At this stage a &#34;0&#34; signal is sent to the actuated switch 3 so that a &#34;0&#34; signal will appear on the signal detect line. Therefore the select gate 18 will place a &#34;0&#34; in the latch 19 at 2nd bit position as directed by the value of the Inc=3. At this stage the latch 19 will contain 00000- as the keyswitch identification code. 
     In response to a &#34;0&#34; state on the signal detect line, the gate 22 will select the Inc value read out of the keycode memory 12 to be added to the state of the adder 11. Since at this stage the Inc=3, the adder 11 will be incremented to the state of 4+3=7. 
     The 9th word in Table 1 is now read out from the keycode memory 12. Because switch 3 is actuated, a &#34;1&#34; state signal will be transmitted to the signal detect line. At this step the action is a state &#34;1&#34; so that the AND-gate 17 transmits a &#34;1&#34; binary logic signal to the select gate 18. Therefore the select gate 18 places a &#34;1&#34; in the 2nd bit position of the latch 19 as directed by the value of the Inc=3. At this search stage the latch 19 will contain 00001- as the keyswitch identification code. 
     In response to the &#34;1&#34; state on the signal detect line, the adder 11 will be incremented to the state 9. 
     The 10th word in Table 1 is now read out from the keycode memory 12. Because switch 3 is actuated, a &#34;1&#34; state signal will be transmitted to the signal detect line. At this step the action is a state &#34;1&#34; so that the select gate 18 will place a &#34;1&#34; in the first bit position of the latch 19 as directed by the value of the Inc=1. At this step in the search sequence the latch will contain 000011 as the keyswitch identification code which correctly identifies keyswitch 3 as the actuated keyswitch. 
     In response to the value of Inc=1, the increment 21 causes the keyswitch identification code word to be transmitted via gate 20 to the utilization means 23. 
     The remainder of the steps in the search sequence which will identify switch 41 as the second actuated keyswitch as shown in Table 2. It should be noted that at step 23 the adder 11 is reset to a zero value because it is implemented as a modulo 126 adder. Thus a new search sequence will be initiated when this step is reached. 
     The function of the AND-gate 24 is to insure that gate 20 will only transfer the keyswitch identification code from latch 19 to the utilization means 23 if the Inc has the value one and if a &#34;1&#34; signal appears on the signal detect line. 
     FIG. 8 illustrates a keyboard operated musical instrument incorporating the present invention. 
     FIG. 4 illustrates the details of a utilization means 23. This subsystem is used to assign musical tone generators contained in the box shown in FIG. 8 labeled tone generators 102 to actuated keyswitches in the keyboard switch array 14. While only three assignors are shown explicitly in FIG. 4, it is obvious from the following description that any number of assignors can be incorporated into the subsystem. It is a feature of the present invention that the assignors are modular units so that the same basic subsystem can be used to implement any number of assignors up to the number of keyswitches contained in the keyboard switch array 14. 
     Each of the assignors 25-27 contains a comparator. The detailed logic of the assignor units is described later. Each time that the gate 20 transmits a keyswitch identification code in response to the signal from the AND-gate 24, each of the assignors compares the transferred keyswitch identification code with a previous number that is stored in an assignor. If the new keyswitch identification code is not equal to the internally stored keyswitch identification code, a logic binary &#34;1&#34; signal is transmitted to the AND-gate 28. Thus the AND-gate 28 will only generate a NEW NOTE signal when a logic &#34;1&#34; is generated by the AND-gate 24 and when the keyswitch associated with a new switch actuation has not been previously assigned to any of the assignors 25-27. 
     Each of the assignors 25-27 sends a TAKE signal to the priority logic 29 in a manner described below. A TAKE signal will be a logic binary &#34;1&#34; signal if the associated assignor is still assigned to an actuated keyswitch. The task of the priority logic 29 is to decide which is the lowest numbered assignor which is not in an assigned state. Each of the assignors 25-27 is given a numerical label which is used to identify an assignor. The description number of the lowest numbered assignor which is not assigned is transferred from the priority logic 29 to the assign select 30. The assign select 30 will assign the keyswitch identification code to the lowest numbered assignor which is in its unassigned mode if the NEW NOTE signal is generated. If all the assignors have been assigned and a NEW NOTE signal is generated, the keyswitch identification code transmitted by the gate 20 is ignored. 
     The detailed logic of the assignor #1 25 is shown in FIG. 5. To illustrate the operation of the assignor it is assumed that the operation starts in the condition that no assignment has been made. In the unassigned state the flip-flop 35 has been reset so that the signal TAKE-1 has a binary logic state of &#34;1&#34;. The unassigned condition is one in which the flip-flop 36 has been set so that its output state is Q=&#34;1&#34;. 
     A new keyswitch is actuated. At the start of search sequence the SCANSTART signal will not alter the state of the flip-flop 36 which had been previously set. Each time that the comparator 33 compares the data previously stored in the note number register 34 with the keyswitch identification code transferred by the gate 20, no equality will be found in the comparison. A &#34;0&#34; state will be generated by the comparator 33 if there is no equality in the comparison. The &#34;0&#34; state is inverted into a &#34;1&#34; state by the inverter 60 and then it is sent to the AND-gate 28. 
     At some stage during the search sequence the system will find that a new keyswitch closure has been detected because each of the assignors will each have sent a &#34;1&#34; state signal to the AND-gate 28. At this stage the NEW NOTE signal will be generated by the AND-gate 28. In a manner described below, it is assumed that the priority logic decides that the assignor #1 25 is the lowest numbered assignor which is presently unassigned. 
     The assign select 30 will generate a WRITE signal which is transmitted to the note number register 34. In response to the WRITE signal the note number register 34 will store the keyswitch identification code transferred by the gate 20 which corresponds to the newly actuated keyswitch in the keyboard switch array 14. The WRITE signal will also set the flip-flop 35 so that the signal TAKE-1 is a logic &#34;1&#34; state to indicate that assignor #25 is now in its assigned state. 
     The next case to consider is the action that occurs during a search sequence during which the keyswitch assigned to assignor #1 25 remains in its actuated state. Because the flip-flop 36 is still in its set condition, the SCAN START signal generated at the start of a search sequence will not change the current state of the flip-flop 35. At some stage in the search sequence the comparator 33 will find an equality match between the data value stored in the note number register 34 and the keyswitch identification code transferred by the gate 20. When an equality is found the YES signal will be generated as a &#34;1&#34; binary logic state. 
     The &#34;1&#34; signal state for the YES signal resets the flip-flop 36 so that its output logic state is Q=&#34;0&#34; and the corresponding input signal to the AND-gate 37 is a logic &#34;1&#34; state. Since this reset of the flip-flop does not occur simultaneously with the generation of the SCAN START signal, no change is made in the state of the flip-flop 35 at this time. 
     For the next search sequence, assuming that the assigned keyswitch remains actuated, the SCAN START signal sets the flip-flop 36 at the start of the sequence. The AND-gate 37 will not generate a &#34;1&#34; output logic state because the YES=&#34;1&#34; signal and the SCAN START=&#34;1&#34; signal do not occur simultaneously. The net result is that the flip-flop 36 will toggle between its two states with no effect on the remainder of the system logic. Under these conditions the flip-flop 36 will always be in its reset state at the end of a search sequence. 
     The last case to consider is that for the search sequence that starts immediately following the release (unactuated state) of the keyswitch that had been assigned to the assignor #1 25. At the end of this search sequence the flip-flop 36 is not reset because the YES=&#34;1&#34; signal is not generated by the comparator 33 because the assigned keyswitch is no longer actuated. At the start of the next search sequence the state of the flip-flop remains at Q=&#34;0&#34; so that the SCAN START=&#34;1&#34; signal causes the AND-gate 37 to generate the ASSIGNOR RELEASE signal. The generation of the ASSIGNOR RELEASE signal will reset the flip-flop 35 so that its output is TAKE-1=&#34;0&#34;. The TAKE-1=&#34;0&#34; signal indicates that the assignor #1 25 has been released and its in its unassigned state. 
     The states of the TAKE-1 can be used to initiate and terminate an ADSR (attack/decay/sustain/release) envelope generator which is used to apply the transient envelope modulations to a musical tone created by a tone generator associated with an assignor subsystem. The keyswitch identification code stored in the note number register 34 can be used to assign a musical frequency to a musical tone generator. 
     A system for using keyswitch identification code number for controlling the frequency of a musical tone generator is described in U.S. Pat. No. 4,114,496 entitled &#34;Note Frequency Generator For A Polyphonic Tone Generator.&#34; This patent is hereby incorporated by by reference. 
     A system for generating an envelope ADSR modulation function in response to a control signal, such as the TAKE-1 signal, is described in U.S. Pat. No. 4,079,650 entitled &#34;ADSR Envelope Generator.&#34; This patent is hereby incorporated by reference. 
     While the tone generators and ADSR envelopes are not shown explicitly in FIG. 4, they are implemented as subsystems contained in each of the assignors. 
     The details of the priority logic are shown in FIG. 6. To illustrate the operation of the logic, consider the case in which TAKE-1=&#34;1&#34;, TAKE-2=&#34;0&#34;, and TAKE-3=&#34;0&#34;. In this case the inverter 40 will transmit a &#34;0&#34; logic state signal ot the assign select 30 which indicates that assignor #1 is presently in its assigned state. 
     In response to the &#34;0&#34; output from the inverter 40, the inverter 43 sends a &#34;1&#34; signal to one input of the AND-gate 44. Since TAKE-2=&#34;0&#34;, the inverter 41 also sends a &#34;1&#34; signal to the other input to the AND-gate 44. Therefore the AND-gate 44 generates a &#34;1&#34; signal which is sent to the assign select to indicate that an assignment can be made to the assignor #2. 
     The OR-gate 45 will transfer a &#34;1&#34; state to the inverter 46 and the OR-gate 48. Since the AND-gate 47 receives a &#34;0&#34; state on one of its input lines connected to the inverter 46, a &#34;0&#34; state signal is generated by the AND-gate 47. This &#34;0&#34; signal is sent to the assign select 30 to indicate that either assignor #3 is currently assigned or that assigned state should be ignored because it has already been determined that assignor #2 is the lowest numbered assignor which is unassigned. Note that if all the assignors have been assigned then the output from the OR-gate 48 is a &#34;0&#34; binary logic state which denotes the condition that all the assignors are in their assigned state. 
     The assign select 30 can be implemented by the means of the set of AND-gates shown in FIG. 6. When the NEW NOTE signal is generated a &#34;1&#34; binary logic state signal will be sent to the note number register of an assignor corresponding to the AND-gate in the set 71-73 that has its second input at a &#34;1&#34; state indicating that the corresponding assignor has been found to be unassigned by the priority logic. 
     An alternate version of the present invention is shown in FIG. 7. This version eliminates the logic employed in the system shown in FIG. 1 which incorporated a subsystem for bit-by-bit encoding of the keyswitching identification. In the alternate implementation the select gate 18, latch 19 and the ACTION signal used in the version shown in FIG. 1 are eliminated. The bit-by-bit encoding of the keyswitch identification code is replaced by storing these codes in the keycode memory 12. In Table 1, for each word shown having only a single &#34;1&#34; state for a switch signal, the corresponding keyswitch identification code is stored instead of the ACTION signal shown in the table. When the output of the increment 21 is a &#34;1&#34; state and a &#34;1&#34; also exists on the signal detect line, the gate 20 transmits the keyswitch identification code read out of the keycode memory to the utilization means.