Abstract:
An IC isolation structure includes a recess disposed in a conductive layer having a surface portion. The recess has a side wall adjacent to the surface portion, and the isolation structure also includes an insulator disposed in the recess and overlapping the surface portion. Thus, if a transistor is disposed in the conductive layer adjacent to the recess side wall, the overlapping portion of the insulator increases the distance between the upper recess corner and the gate electrode. This increased distance reduces hump effects to tolerable levels.

Description:
TECHNICAL FIELD 
     The invention relates generally to integrated circuits (ICs), and more particularly to an improved isolation structure and a method for forming the same. For example, the isolation structure reduces “hump” effects in transistors that are adjacent to the structure, particularly in transistors having a feature size of 0.25 microns (μm) or less. 
     BACKGROUND OF THE INVENTION 
     To meet the industry demand for ICs that pack greater functionality into the same or a smaller die area, IC manufacturers continue to research and develop processes that allow integrated devices such as transistors to have smaller geometries. For example, a few years ago, many IC manufacturers used a 4 μm process, which can form devices having a feature size (e.g., the width of a transistor gate) as small as 4 μm. But today, 1 μm processes are common, and 0.25 μm, 0.18 μm and 0.1 μm processes are under development. These smaller-geometry processes allow the formation of integrated devices having smaller geometries. Consequently, such processes allow more devices—and thus more functionality—on a given die area than larger-geometry processes do. 
     Unfortunately, merely scaling down the dimensions of an integrated device to take advantage of a smaller-geometry process may render the device inoperable. For example, due to known short-channel effects, a transistor having a gate width of 4 μm may operate improperly if it is scaled down to have a gate width of 1 μm. 
     FIG. 1 is a cross-sectional view of a conventional silicon-trench isolation (STI) structure  10 , which is part of an IC  11  such as a memory circuit. The IC  11  includes transistors  12   a  and  12   b , which are disposed in a substrate  13  having a surface  14  and corners  16   a  and  16   b . The transistors  12   a  and  12   b  include respective body regions  18   a  and  18   b , which are disposed in the substrate  13  and which electrically invert during transistor operation to form respective channel regions. Gate insulators  20   a  and  20   b  are respectively disposed on the body regions  16   a  and  16   b . A conductor  22 , such as a word line, extends over the isolation structure  10  and the gate insulators  20   a  and  20   b  and acts as a gate electrode for both the transistors  12   a  and  12   b.    
     Unfortunately, the isolation structure  10  may cause the transistors  12   a  and  12   b  to operate improperly. The isolation structure  10  includes an isolation trench  24  disposed in the substrate  13 . The trench  24  is filled with an insulator  26  having side walls that often taper inwardly as they extend from the trench  24  above the surface  14  of the substrate  13 . This narrowing forms gaps  28   a  and  28   b , which allow the gate conductor  20  to closely overlap the corners  16   a  and  16   b , respectively. During operation of the transistors  12   a  and  12   b , this overlap often causes undesirable fringe, i.e., “hump,” effects in the respective regions of the transistors&#39; electric fields near the corners  16   a  and  16   b . If the transistors  12   a  and  12   b  have relatively large feature sizes, then these hump effects typically have only a negligible affect on transistor operation. But if the transistors  12   a  and  12   b  have relatively small feature sizes, particularly feature sizes of 0.25 μm or less, then these hump effects may severely degrade the transistor operation, and may even render the transistors  12   a  and  12   b  unusable. Furthermore, even if the side walls of the insulator  26  are straight outside of the trench  24 , the conductor  22  may still be close enough to the corners  16   a  and  16   b  to cause significant hump effects. 
     SUMMARY OF THE INVENTION 
     In one aspect of the invention, an IC isolation structure includes a recess disposed in a conductive layer having a surface portion. The recess has a side wall adjacent to the surface portion, and the isolation structure also includes an insulator disposed in the recess and overlapping the surface portion. 
     Thus, if a transistor is disposed in the conductive layer adjacent to the recess side wall, the overlapping portion of the insulator increases the distance between the recess corner and the gate electrode. This increased distance reduces hump effects to tolerable levels. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross-sectional view of a conventional IC isolation structure. 
     FIG. 2 is a cross-sectional view of an IC isolation structure according to an embodiment of the invention. 
     FIG. 3 is a top view of the IC isolation structure of FIG.  2 . 
     FIG. 4 is a cross-sectional view of a semiconductor structure at a point in a process for forming the isolation structure of FIGS. 2 and 3 according to an embodiment of the invention. 
     FIG. 5 is a cross-sectional view of the semiconductor structure of FIG. 4 at a subsequent point in the process. 
     FIG. 6 is a cross-sectional view of the semiconductor structure of FIG. 5 at a subsequent point in the process. 
     FIG. 7 is a cross-sectional view of the semiconductor structure of FIG. 6 at a subsequent point in the process. 
     FIG. 8 is a cross-sectional view of the semiconductor structure of FIG. 7 at a subsequent point in the process. 
     FIG. 9 is a cross-sectional view of the semiconductor structure of FIG. 8 at a subsequent point in the process. 
     FIG. 10 is a cross-sectional view of the semiconductor structure of FIG. 9 at a subsequent point in the process. 
     FIG. 11 is a cross-sectional view of an IC isolation structure according to another embodiment of the invention. 
     FIG. 12 is a top view of the IC isolation structure of FIG.  11 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 is a cross-sectional view of an IC isolation structure  40  according to an embodiment of the invention. The isolation structure  40  is part of an IC  42 , which in one embodiment is similar to the IC  11  of FIG.  1 . The IC  42  includes transistors  44   a  and  44   b , which are disposed in a conductive layer  46  having a surface  48  and corners  50   a  and  50   b . In one embodiment, the layer  46  is a semiconductor substrate. The transistors  44   a  and  44   b  include respective body regions  52   a  and  52   b , which are disposed in the layer  46 . Gate insulators  54   a  and  54   b  are respectively disposed on the body regions  52   a  and  52   b , and a conductor  55  such as a word line extends over the isolation structure  40  and the gate insulators  54   a  and  54   b  and acts as a gate electrode for both the transistors  44   a  and  44   b . Although shown laterally spaced from the corners  50   a  and  50   b , in another embodiment the body regions  52   a  and  52   b  extend to the respective corners. 
     The isolation structure  40  reduces or eliminates hump effects in the transistors  44   a  and  44   b  by increasing the distance and decreasing the overlap between the gate electrode  55  and the corners  50   a  and  50   b . Specifically, the isolation structure  40  includes an isolation recess  56  disposed in the layer  46  and having side walls  58   a  and  58   b . In the illustrated embodiment, the recess  56  is a trench. A mushroom-shaped trench insulator  60  is disposed in the trench  56  and includes an inner portion, i.e., “stem,”  62  and an outer portion, i.e., “cap,”  64 . In one embodiment, the insulator  60  includes two insulator layers  66  and  68 , although it may include a single layer or three or more layers in other embodiments. The cap  64  is wider than the stem  62 , and thus laterally extends beyond the side walls  58   a  and  58   b  to overlap the corners  50   a  and  50   b  and the adjacent portions of the conductive-layer surface  48 . But although described as overlapping both corners  50   a  and  50   b , in another embodiment the cap  64  overlaps only one of the corners. The overlapping portions of the cap  64  increase the respective distances between the gate electrode  55  and the corners  50   a  and  50   b . These increased distances reduce the electrical fields between the electrode  55  and the corners  50   a  and  50   b , and thus reduce the hump effects caused by the electrode  55  during operation of the transistors  44   a  and  44   b . Therefore, the isolation structure  40  is particularly advantageous for use in 0.25 μm or smaller processes. 
     FIG. 3 is a top view of the isolation structure  40  and the surrounding portions of the IC  42  of FIG.  2 . The transistor  44   a  includes source/drain regions  70  and  72 , and the transistor  44   b  includes source/drain regions  74  and  76 . Although not shown, the transistors  44   a  and  44   b  may be bounded on one or more of their other sides by isolation structures that are similar to the structure  40 . 
     FIGS. 4-10 show steps of a process for forming the IC isolation structure  40  of FIGS. 2 and 3 according to an embodiment of the invention. 
     Referring to FIG. 4, a mask layer  90  is conventionally formed on the conductive layer  46 , and an opening  92  is conventionally formed in the mask layer  90  to expose a portion of the layer  46 . In one embodiment, the layer  46  is a semiconductor substrate such as a silicon substrate, the mask layer  90  is a nitride layer, and the opening  92  has a width approximately equal to the minimum feature size of the process. 
     Referring to FIG. 5, spacers  94   a  and  94   b  are conventionally formed on the side walls of the opening  92  to narrow the width thereof. In one embodiment, the spacers  94   a  and  94   b  are formed from tetraethylorthosilicate (TEOS) and each have a width of approximately 300-400 Angstroms (Å). 
     Referring to FIG. 6, the conductive layer  46  is conventionally etched through the narrowed opening  92  to form the trench  56 . In one embodiment, the conductive layer  46  is anisotropically etched to a depth of approximately 0.2-0.4 μm to form the trench  56 . 
     Referring to FIG. 7, the spacers  94   a  and  94   b  are conventionally removed. 
     Referring to FIG. 8, the trench  56  is conventionally filled with the first insulator layer  66  to form the stem  62  of the trench insulator  60 . In one embodiment, the layer  66  is an oxide that completely fills the trench  56  and the opening  92  such that the trench insulator  60  is formed from a single layer. In the illustrated embodiment, however, the first layer  66  partially fills the opening  92  and the second insulator layer  68  is conventionally formed on the layer  66 . In one embodiment, the second layer  68  is TEOS. In yet another embodiment, the trench insulator  60  may include more than two layers. 
     Referring to FIG. 9, the insulator  60  is conventionally polished back to the mask layer  90 , which acts as a polish stop. In the illustrated embodiment, the layer  68  is polished back to the layer  90 . 
     Still referring to FIG. 9, because the cap  64  fills the voids left by the spacers  94   a  and  94   b  (FIGS.  5 - 6 ), in one embodiment it overlaps the corners  50   a  and  50   b  by approximately 300-400 Å with respect to the side walls  58   a  and  58   b  and is approximately 300-400 Å high with respect to the surface  48 . The cap overlap distances and height can be different, however, depending upon the process. 
     Referring to FIG. 10, the mask layer  90  is conventionally removed. In one embodiment, the step of removing the layer  90  also rounds the upper corners  96   a  and  96   b  of the cap  64 . Thus, the trench insulator  60  “mushrooms” laterally beyond the trench side walls  58   a  and  58   b  and overlaps adjacent regions of the surface  48  of the conductive layer  46 . In another embodiment, however, the corners  96   a  and  96   b  are not rounded. 
     Referring again to FIGS. 2 and 3, the body regions  52   a  and  52   b , conductor  55 , gate insulators  54   a  and  54   b , and source/drain regions  70 ,  72 ,  74 , and  76  are conventionally formed. 
     The isolation structure  42  of FIGS. 11 and 12 is similar to the isolation structure  42  of FIGS. 2 and 3 except that the body regions  52   a  and  52   b  and the source/drain regions  70 ,  72 ,  74 , and  76  extend beneath the cap  64 . 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, instead of being disposed in the trench  56 , the insulator  60  can be disposed in a recess having more than two side walls, with the cap  64  overlapping at least one of the side walls. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.