Abstract:
Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.

Description:
TECHNICAL FIELD  
         [0001]    The present invention is generally related to microchip fabrication. More particularly, the invention relates to elemental semiconductor device simulation, modeling and parameter extractions.  
         BACKGROUND OF THE INVENTION  
         [0002]    In the development of integrated circuits, particularly very large scale integrated circuits, it is desirable to reduce the number of design/prototype iterations. One tool available to circuit designers used to minimize the prototyping needed to validate performance of circuit designs is modeling and simulation. Modeling and simulation may be performed at various levels of circuitry, from complex networks down to individual elements, devices or even portions thereof.  
           [0003]    In the simplest sense models are mathematical representations of certain performance characteristics of the device being modeled. Simulations rely upon these models and specific predetermined device parameters which correspond to model parameters. Simulations solve the model equations, alone or in combination with a network of other models. Some models are utilized by circuit designers to define a device as part of a circuit to evaluate a circuit performance. Other models may be utilized by a designer of a device in order to model and simulate the device itself through manipulation of certain parameter variables.  
           [0004]    Relatively speaking, diode or semiconductor junction models are among the simplest of semiconductor device models. Junction models include formulas to calculate steady-state current vs. voltage (I-V characteristics), and charge storage within the device (typically, a nonlinear capacitance vs. applied voltage). Steady state current can usually be modeled well using the classical SPICE formula. In its basic form, the formula models current to increase substantially exponentially with forward voltage. The model also includes a parasitic series resistance term or parameter (series resistance).  
           [0005]    The general form of such a model may be expressed as follows:  
           [0006]    I D =I S ( e   q(V     Dx     −I     D     R     total     )/nkT −1), or alternatively through rearrangement as  
           V   Dx     =         nkT   q          ln        (         I   D       I   S       +   1     )         +       I   D     ×     R   total           ,                         
 
           [0007]    wherein;  
           [0008]    V Dx  is voltage across the semiconductor device (device voltage),  
           [0009]    I D  is current through the semiconductor device (device current),  
           [0010]    I S  is the semiconductor device reverse saturation current,  
           [0011]    R total  is the semiconductor device lumped parasitic series resistance (series resistance),  
           [0012]    n is the emission coefficient,  
           [0013]    k is the boltzman constant  
           [0014]    T is temperature, and  
           [0015]    q is the electronic charge.  
           [0016]    An even more simplified model equation may be expressed as  
             V   Dx   =V   D   +I   D   R   total , wherein  
           [0017]    V D  is a semiconductor junction voltage,  
           [0018]    V Dx  is a semiconductor device voltage,  
           [0019]    I D  is a semiconductor device current, and  
           [0020]    R total  is the semiconductor device lumped parasitic series resistance (series resistance).  
           [0021]    Certain models also have a variety of parameters to describe avalanche breakdown current or AC response, which parameters are not specifically called out in the above equations nor further addressed herein.  
           [0022]    Typically, the basic SPICE model for a junction device is adequate to obtain reasonably good results. Of course, a model&#39;s fidelity is always dependent upon its parameter values and extraction techniques. The exponential nature of the junction model equations together with compromises in extraction techniques and parameter assumptions result in compromised accuracy, particularly in the so-called forward biased high current or knee region of the current-voltage characterization curve. A classic extraction technique and associated assumption regarding the series resistance of a semiconductor junction device relies upon defining the series resistance as a simple fixed value equaling sheet resistance divided by the active area of the device. FIG. 1 illustrates such a typical shortfall at  10  when such parasitic extraction technique is followed wherein modeled results (solid line) are shown to deviate from measured results (data points) on a typical linear scale of device voltage (V) versus device current (I D ). Such an assumption regarding the relationship between series resistance and active area geometry will result in additional errors if carried through to modeling and simulation directed toward scaling devices and simulations of scaled devices.  
           [0023]    Therefore, what is needed is an improved method of modeling the parasitic resistance of a semiconductor junction device, particularly in the high current region of operation. What is also needed is an improved manner of simulating a semiconductor junction device having improved fidelity and accuracy.  
         SUMMARY OF THE INVENTION  
         [0024]    Therefore, in accordance with one aspect of the present invention, an improved method of modeling the parasitic resistance of a semiconductor junction device is provided. In accordance with another aspect of the present invention, simulation of a semiconductor device utilizing an improved parasitic resistance model provides for improved correlation between measured and simulated parameters for such a device.  
           [0025]    In accordance with one embodiment of the present invention, a method for extracting series resistance from a semiconductor device for use in a semiconductor device model includes the steps of: providing empirical current-voltage characterization data for the semiconductor device; providing extrapolated current-voltage characterization data from the empirical current-voltage characterization data in an exponential region thereof; calculating a series resistance of the semiconductor device as a function of a) the difference between the empirical and extrapolated voltage characterization data corresponding to a current point in a high current region of the semiconductor device and b) said current point.  
           [0026]    In accordance with another embodiment of the present invention, a method for modeling series resistance in a semiconductor device model for use in simulating a semiconductor device includes the steps of: providing empirical current-voltage characterization data for a semiconductor device; providing extrapolated current-voltage characterization data from the empirical current-voltage characterization data in an exponential region thereof; for each of a plurality of current points within a high current region of the semiconductor device, calculating a respective series resistance of the semiconductor device corresponding thereto; extrapolating current-resistance characterization data from the plurality of high current region current points and respective series resistances to define a semiconductor device current-series resistance model.  
           [0027]    In accordance with another embodiment of the present invention, a method for simulating a semiconductor device having a semiconductor junction includes the steps of: providing a semiconductor device model including a junction voltage portion and a parasitic voltage drop portion, said parasitic voltage drop portion being based upon a parasitic resistance through the semiconductor device characterized as a sigmoidal function of device current; and, solving the semiconductor device model to characterize the semiconductor device in accordance with a set of predetermined semiconductor device parameters. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:  
         [0029]    [0029]FIG. 1 illustrates a shortfall of known modeling and parasitic resistance extraction techniques in the high current region of device operation;  
         [0030]    [0030]FIG. 2 is a block-schematic of a typical control and acquisition apparatus for model parameter extraction from test devices, a portion of which may be used for subsequent semiconductor device simulation in accordance with the present invention;  
         [0031]    [0031]FIG. 3 exemplary test device patterns in sufficient plan-view or layout detail for an understanding of the present invention;  
         [0032]    [0032]FIG. 4 illustrates empirical current-voltage data plotting and extrapolation useful in exemplifying the series resistance extraction method of the present invention;  
         [0033]    [0033]FIG. 5 illustrates lumped series resistance-device current data plotting and extrapolation useful in exemplifying the series resistance model of the present invention;  
         [0034]    [0034]FIG. 6 illustrates active region resistance limit- reciprocal active area perimeter data plotting and extrapolation useful in exemplifying the series resistance model of the present invention;  
         [0035]    [0035]FIG. 7 illustrates an oxide/metal region resistance-metal square data plotting and extrapolation useful in exemplifying the series resistance model of the present invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0036]    With reference first to FIG. 1, a block-schematic of a typical control and acquisition apparatus for model parameter extraction shows a semiconductor device under test (DUT) within a test fixture  20 . A wafer contains a plurality of test devices for the purpose of being probed for signal stimulation  21  by test equipment  24  and response measurement  23  also by test equipment  24 . In the present invention, the test signals applied are steady state or DC signals, voltage or current. The measured response signals are similarly steady state or DC quantities of voltage or current. Test equipment  24  may be programmable or, as illustrated, controlled by a PC, workstation or other user interface  25 . In short, as is well understood by those skilled in the art, the plurality of test devices are subjected to a stimulus and measurement routine wherein current-voltage characterization data is acquired and stored in data files for later use and applications.  
         [0037]    In characterizing a particular semiconductor device design, all of the plurality of individual devices under test will share the same design factors, including geometric scaling, within the production process limits and tolerances. It may be useful, however, as seen at a later point herein, that certain design factors may be different among the plurality of the individual devices under test in accordance with the purpose of the ultimate use of the characterization data. In the present invention, and in accordance with various embodiments thereof, the plurality of the individual devices under test may have different geometries, in particular differences in active region perimeters.  
         [0038]    [0038]FIG. 3 illustrates exemplary test device patterns in sufficient plan-view or layout detail for an understanding of the present invention. Each of the exemplary devices comprises a well junction device, for example a PN diode, compatible with conventional CMOS processes; however, other types of diode or junction devices, such as a planar diode may be utilized. Each device is characterized by a respective active region  30  substantially defined by a respective perimeter P. An oxide and well-pickup region  31  substantially at the periphery of the active region  30  of each device is also shown, its import being more apparent at further points in the specification. Not separately shown are metal regions for interconnects which couple on opposite sides of the counter-doped regions comprising the junction. Connecting to the counter-doped regions at the active region may be accomplished on the upper surface, on the opposite side of the substrate or outside of the active region on the upper surface in accordance with the particular junction device type and design. Such metalization and interconnects are well known and further exposition is not required herein.  
         [0039]    Current-voltage (I-V) characterization data are empirically determined with respect to the exemplary apparatus of FIG. 2. FIG. 4 illustrates the plotting of such I-V characterization data as discrete dots. As is conventional practice, semiconductor device reverse saturation current I s  and the emission coefficient n are extracted from the exponential region of the device current I D  versus device voltage V Dx  data-Is from the intercept of the extrapolated exponential region data line  40  and n from the slope of ln(I D ) versus V Dx .  
         [0040]    The series resistance R total  is next extracted in accordance with the present invention. Series resistance is calculated as a function of a) the difference between the empirical and extrapolated voltage characterization data corresponding to a common current point (I com )  41  in a high current region of the semiconductor device and b) that current point. I com  is selected from the empirically determined current points of the I-V characterization data. The intersection of I com  and the extrapolation  40  provides a first voltage and the empirically determined I-V voltage data point corresponding to I com  provides a second voltage. R total  corresponding to I com  is then calculated as the difference between the first and second voltages at this common current point I com  divided by I com . For each pair of empirically determined I-V characterization data, the current and voltage data are similarly utilized in the calculation of a plurality of series resistance R total  extractions corresponding to respective current points.  
         [0041]    Turning now to FIG. 5, the extracted R total  data is shown plotted as individual points against an axis of device current I D  on an exponential scale. The device current corresponds to the I com  current point utilized in extracting the respective R total  data. An extrapolation of the R total -I D  data is performed. A non-linear curve fitting function having substantially sigmoidal characteristics provides the preferred fit. Series resistance R total  limits are established for corresponding device current I D  limits at zero and infinity. The following equation provides satisfactory modeling of series resistance R total  in accordance with the previously described extraction and extrapolation steps.  
         R   total     =         R   OD         (     1   +         I   D     ×     R   OD         2   ×     kT   q           )     m       +     R   OM                             
 
         [0042]    wherein  
         [0043]    I D  is a semiconductor device current,  
         [0044]    k is the boltzman constant,  
         [0045]    T is a semiconductor device temperature,  
         [0046]    q is the electronic charge constant,  
         [0047]    m is a fitting parameter,  
         [0048]    R OD  is a first resistance limit for the semiconductor device as semiconductor device current (I D ) approaches zero, and  
         [0049]    R OM  is a second resistance limit for the semiconductor device as semiconductor device current (I D ) approaches infinity.  
         [0050]    The first term containing the first resistance limit R OD  varies as a function of device current I D . The term is derived from factors that affect resistance under the active region, including current crowding effects. The second term containing the second resistance limit R OM  does not vary in this model with device current I D  and corresponds to resistance factors that are not influenced by active region factors including resistance under the oxide and metal routing or interconnect resistance. Therefore, R OD  is an active region resistance limit for the semiconductor device as semiconductor device current (I D ) approaches zero, and R OM  is a semiconductor device resistance limit as semiconductor device current (I D ) approaches infinity.  
         [0051]    As had been previously alluded to, current-voltage characterizations of different test devices having geometrical dissimilarities in active region perimeter are useful in developing an even more sophisticated device design model that accounts for and allows its use in scaling of the modeled semiconductor device. It has been determined that a device parameter having significantly more influence upon geometric scaling accuracy than the oft cited active region area is the active region perimeter. Furthermore, it can be said that the series resistance of a subject semiconductor device varies inversely to the active region perimeter.  
         [0052]    Taking the expanded version of R total  wherein  
           R   total     =         R   OD         (     1   +         I   D     ×     R   OD         2   ×     kT   q           )     m       +     R   OM         ,                         
 
         [0053]    R OD  is expanded to the form  
         R   OD     =       R   OD1     P                           
 
         [0054]    and  
         [0055]    R OM  is expanded to the form  
           R   OX1     P     +       R   C     *   N                           
 
         [0056]    wherein  
         [0057]    R OD1  is a line resistance for the active region,  
         [0058]    R OX1  is a line resistance for the oxide region,  
         [0059]    P is an active region perimeter,  
         [0060]    R C  is a sheet resistance of a metal line layer, and  
         [0061]    N is the square of the metal interconnects.  
         [0062]    Therefore, the model equation for R total  becomes:  
         R   total     =           R   OD1     P         (     1   +         I   D     ×       R   OD1     P         2   ×     kT   q           )     m       +       R   OX1     P     +       R   C     ×   N                             
 
         [0063]    The same methodology is followed in extracting R total  and its resistance limits R OD  and R OM  for each of a plurality of semiconductor devices having diverse active region perimeters. These data are plotted against perimeter dependent axes as shown in FIGS. 6 and 7 wherefrom R OX1  and R OD1  can be readily extracted whereby geometric scaling is now within the capabilities of the model.  
         [0064]    The invention has been described with respect to certain preferred embodiments intended to be taken by way of example and not by way of limitation. Certain alternative implementations and modifications may be apparent to one exercising ordinary skill in the art. Therefore, the scope of invention as disclosed herein is to be limited only with respect to the appended claims.  
         [0065]    The invention in which an exclusive property or privilege is claimed are defined as follows: