Abstract:
Analog echo-cancelling circuitry ( 611  and  627 ) operates on an input analog signal that includes an echo of an output signal, or on an analog signal generated from the input signal, to produce an analog signal with reduced echo. An analog-to-digital converter ( 210 ) converts the echo-reduced analog signal, or an analog signal generated therefrom, into a digital signal. Digital echo-cancelling circuitry ( 615  and  621 ) operates on the digital signal, or on a digital signal generated therefrom, to produce a digital signal with further reduced echo. An output decoder ( 605 ) decodes the echo-reduced digital signal, or a digital signal generated therefrom, into a stream of symbols. The echo-filtering characteristics of both echo-cancelling circuitries are typically adaptively adjusted during generation of the symbol stream. The analog echo-filtering characteristics may be adapted in response to information provided by operating on the echo-reduced digital signal or on a digital signal generated therefrom.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This is a division of U.S. patent application Ser. No. 09/561,086, filed Apr. 28, 2000, now U.S. Pat. No. 7,254,198 B1. 

   FIELD OF THE INVENTION 
   This invention relates to digital communication systems and, more particularly, to an optimal architecture for receiver processing. 
   BACKGROUND 
   The dramatic increase in desktop computing power driven by intranet-based operations and the increased demand for time-sensitive delivery between users has spurred development of high speed Ethernet local area networks (LANs). 100BASE-TX Ethernet (see IEEE Std. 802.3u-1995 CSMA/CD Access Method, Type 100 Base-T) using existing category 5 (CAT-5) copper wire, and the newly developing 1000BASE-T Ethernet (see IEEE Draft P802.3ab/D4.0 Physical Layer Specification for 1000 Mb/s Operation on Four Pairs of Category 5 or Better Twisted Pair Cable (1000 Base-T)) for gigabit-per-second transfer of data over category 5 data grade copper wiring, require new techniques in high speed symbol processing. On category 5 cabling, gigabit-per-second transfer can be accomplished utilizing four twisted pairs and a 125 megasymbol-per-second transfer rate on each pair where each symbol represents two bits. 
   Physically, data is transferred using a set of voltage pulses where each voltage represents one or more bits of data. Each voltage in the set is referred to as a symbol and the whole set of voltages is referred to as a symbol alphabet. 
   One system of transferring data at high rates is Non-Return-to-Zero (NRZ) signaling. In NRZ, the symbol alphabet {A} is {−1, +1}. A logical “1” is transmitted as a positive voltage while a logical “0” is transmitted as a negative voltage. At 125 megasymbols per second, the pulse width of each symbol (the positive or negative voltage) is 8 ns. 
   An alternative modulation method for high speed symbol transfer is Multilevel Threshold-3 (MLT3) and involves a three-level system. (See American National Standard Information System, Fibre Distributed Data Interface (FDDI)-Part: Token Ring Twisted Pair Physical Layer Medium Dependent (TP-PMD), ANSI X3.263:199X.) The symbol alphabet {A} for MLT3 is {−1, 0, +1}. In MLT3 transmission, a logical “1” is transmitted by either a −1 or a +1 while a logical “0” is transmitted as a 0. A transmission of two consecutive logical “1”s does not require the system to pass through zero in the transition. A transmission of the logical sequence (“1”, “0”, “1”) results in transmission of the symbols (+1, 0, −1) or (−1, 0, +1), depending on the symbols transmitted prior to this sequence. If the symbol transmitted immediately prior to the sequence was a +1, the symbols (+1, 0, −1) are transmitted. If the symbol transmitted before this sequence was a −1, the symbols (−1, 0, +1) are transmitted. If the symbol transmitted immediately before this sequence was a 0, the first symbol of the sequence transmitted will be a +1 if the previous logical “1” was transmitted as a −1 and will be a −1 if the previous logical “1” was transmitted as a +1. 
   The detection system in the MLT3 standard, however, needs to distinguish between three levels, instead of two levels as in a more typical two-level system. The signal-to-noise ratio required to achieve a particular bit error rate is higher for MLT3 signaling than for two-level systems. The advantage of the MLT3 system, however, is that the energy spectrum of the emitted radiation from the MLT3 system is concentrated at lower frequencies and therefore more easily meets FCC radiation emission standards for transmission over twisted pair cables. Other communication systems may use a symbol alphabet having more than two voltage levels in the physical layer in order to transmit multiple bits of data using each individual symbol. In Gigabit Ethernet over twisted pair CAT-5 cabling, for example, five-level Pulse-Amplitude Modulation (PAM-5) data can be transmitted at a baud rate of 125 megabaud. (See IEEE Draft P802.3ab/D4.0 Physical Layer Specification for 1000 Mb/s Operation on Four Pairs of Category 5 or Better Twisted Pair Cable (1000 Base-T).) 
   Therefore, there is a necessity for a receiver capable of receiving signals having large intersymbol interference from long transmission cables. There is also a necessity for reducing the difficulties associated with digital equalization of signals with large intersymbol interference without losing the equalization versatility required to optimize the receiver. 
   SUMMARY OF THE INVENTION 
   In accordance with the invention, a receiver system for providing signal equalization is partitioned into an analog pre-filter and a digital receiver. At least some of the intersymbol interference is removed from the signal by the analog pre-filter before the signal is processed through a digital equalizer in the digital receiver. Signals having a large amount of intersymbol interference, such as those transmitted through long cables, are preprocessed through the pre-filter, thereby reducing the difficulties of digital equalization without losing the versatility of the digital equalizer. 
   Embodiments of the invention can include any equalization scheme, including linear equalization, decision feedback equalization, trellis decoding and sequence decoding, separately or in combination. Embodiments of the invention may also include cable quality and cable length indication and baseline wander correction. Further, embodiments of receivers according to the present invention can also include echo cancellation and near end crosstalk (NEXT) cancellation. 
   These and other embodiments of the invention are further explained below along with the following figures. 

   
     DESCRIPTION OF THE FIGURES 
       FIG. 1A  shows a transmission system with an entirely digital equalizer in the receiver. 
       FIG. 1B  shows a transmission system with an entirely analog equalizer in the receiver. 
       FIG. 2A  shows a transmission system that contains a receiver system according to the present invention. 
       FIG. 2B  shows an analog model of a transmission channel. 
       FIG. 3A  shows an exemplary transfer function representing a transmission channel. 
       FIG. 3B  shows the exponential component of the signal distortion. 
       FIG. 3C  shows an exemplary transfer function of a pre-filter according to the present invention. 
       FIG. 3D  shows the combined influence of the functions shown in  FIGS. 3A ,  3 B and  3 C on an input signal. 
       FIG. 4  shows a discrete time model of signal transmission through a transmission channel in combination with a pre-filter according to the present invention. 
       FIG. 5A  shows another embodiment of a receiver according to the present invention. 
       FIGS. 5B and 5C  show embodiments of pre-filters for a receiver according to the present invention. 
       FIGS. 6A ,  6 B,  6 C,  6 D and  6 E show embodiments of a multi-wire receiver system according to the present invention. 
   

   In the figures, elements having similar or identical functions have identical identifiers. 
   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1A  shows a block diagram of a typical transmission system  100  for a single-wire transmission channel. Transmission system  100  includes transmitter  107 , transmission channel  102  and receiver  103 . Transmitter  107  transmits a symbol stream {a k } and can perform some signal shaping on the waveform formed by symbol stream {a k }. Notationally, a particular symbol in clock cycle k is denoted without brackets as a k  whereas the symbol sequence or stream is denoted with curly brackets as {a k }. 
   Transmission channel  102  which can be any transmission medium distorts the transmitted waveform, creates intersymbol interference, and adds noise to the transmitted signal. Receiver  103  receives the transmitted signals from transmission channel  102 . Receiver  103  includes an analog-to-digital converter (ADC)  104  and an equalizer  106  connected in series. In receiver  103  of  FIG. 1A , the equalization of an input signal to receiver  103  is accomplished digitally. Digital equalization becomes problematic as the cable length increases due to the large intersymbol interference associated with longer cables. 
   In general, a signal received by receiver  103  includes contributions from several transmitted symbols as well as noise and channel distortions. Each transmitted symbol is diffused in the transmission process so that it is commingled with symbols being transmitted at later transmission times. This effect is known as “intersymbol interference” (ISI). (See E. A. L EE AND  D. G. M ESSERCHMITT , D IGITAL  C OMMUNICATIONS  (1988).) 
   Intersymbol interference is a result of the dispersive nature of the communication channel. The IEEE LAN standards require that LAN communication systems be capable of transmitting and receiving data through at least a 100 meter cable. In a 100 meter cable, the signal strength at the Nyquist frequency of 62.5 Mhz is reduced nearly 20 db at the receiving end of the cable. Given this dispersion, a single symbol may affect symbols throughout the transmission cable of transmission channel  102 . 
   An input signal x k  to receiver  103  at sample time k, neglecting channel distortion and noise, can be digitally represented as
 
 x   k   =C   0   a   k   +C   1   a   k−1   + . . . +C   j   a   k−j   (1)
 
where a k−j  represents the (k−j)th symbol in the symbol sequence and coefficient C j  represents the contribution of the (k−j)th symbol to signal x k . Equalizer  106  receives digitized sample x k  and deduces currently received symbol â k  by removing, usually adaptively, the contribution of previous symbols a k−j  from detected sample x k  (i.e., by removing the intersymbol interference). The deduced symbol â k  represents the best estimation by receiver  103  as to what the transmitted symbol a k  was.
 
   However, with long cable lengths, the contribution of earlier received symbols becomes significant. For example, with cable lengths above about 100 meters, coefficient C 1  for immediately previous symbol a k−1  can be as high as 0.95 (i.e., 95% of symbol a k−1  may be represented in the input signal). Contributions from other previous symbols can also be high. Given that equalizer  106  cannot adjust for the contribution of symbols not yet received (e.g., the kth detected sample cannot include contributions from the (k+1)th transmitted symbol), equalizer  106  has a difficult time distinguishing the kth and the (k−1)th symbol under these circumstances. An adaptive receiver can have particular difficulty upon startup in distinguishing the contribution of the kth symbol from the contribution of the (k−1)th symbol and in determining the equalizer parameters corresponding to the mixing parameters {C j }. 
   Therefore, for large cable lengths a digital equalizer is faced with deducing the current symbol from a sample containing significant contributions from numerous previously received symbols. The difficulty is not only deducing the symbols but in adaptively choosing the operating parameters of the equalizer in order to optimize the performance of receiver  103 . 
   An alternative approach to digital equalization is analog equalization.  FIG. 1B  shows a block diagram of a transmission system  110  having an analog receiver  111  coupled to transmission channel  102 . Receiver  111  includes an analog equalizer  112  having an analog filter tailored to remove intersymbol interference from the received signal. Although having the advantage of processing loop speed, equalizer  112  cannot be adaptively optimized for the performance of receiver  111 . 
     FIG. 2A  shows a transmission system  200  according to the present invention. Transmission system  200  includes a transmitter  221 , a transmission channel  201  and a receiver system  206 . Transmitter  221  outputs a symbol stream {a k } to transmission channel  201 ; Transmitter  221  can output symbol stream {a k } directly or, in some embodiments of the invention, perform some pre-processing of the waveform formed by the sequential transmission of the symbol stream {a k }. 
   Transmission channel  201  represents the transmission of a signal between transmitter  221  and receiver  206  and can include any transmission medium, including twisted copper, coaxial cable or optical fiber. The symbol stream {a k } can be composed of any symbol alphabet, including NRZ, MLT3, PAM-5 (where the symbol alphabet is given by {−2,−1,0,1,2}) or any other symbol alphabet and modulation that are used in transceivers such as transmission system  200 . 
   Transmission system  200  may be a portion of a larger transceiver system. In general, transceivers of this type may have any number of transmission channels similar to transmission channel  201 . For example, gigabit-per-second transfer of data can be accomplished using four transmission channels, each with one twisted pair cable. Further, transmission channels such as transmission channel  201  can be bi-directional, i.e., transmit data in both directions. For example, receiver  206  may be associated with a transmitter that transmits symbol streams to other receivers coupled to the same cable as is included in transmission channel  201 . Any number of transmitters and receivers may be coupled to the cable associated with transmission channel  201 . Each coupling may affect the response of transmission channel  201 . 
   The transmitted symbols in the sequence {a k } are members of the symbol alphabet {A}. In the exemplary case of PAM-5 signaling, the symbol alphabet {A} is given by {−2, −1, 0, +1, +2}. The index k again represents the time index for each transmitted symbol, i.e., at sample time k, the symbol being transmitted to transmission channel  201  is given by a k . 
   The real-time output of transmitter  221  can be represented as A S (ω), where A S (ω) is the Fourier transform of the analog signal a s (t) that represents the symbol stream {a k }. Therefore, 
                     A   s     ⁡     (   ω   )       =       ∫     -   ∞     ∞     ⁢         a   s     ⁡     (   t   )       ⁢     ⅇ     -   jωt       ⁢           ⁢       ⅆ   t     .                 (   2   )               
Signal a S (t) also represents the effects of any pre-shaping that may be performed by transmitter  221 .
 
   The output signal y k  or Y S (ω) from transmission channel  201 , now treated as an analog signal, suffers from channel distortion, the addition of random noise, and a flat signal loss. Referring to  FIG. 2A , channel output signal Y S (ω) is the Fourier transform of the analog signal that represents the output signal stream {y k } from transmission channel  201 . Channel output signal y k  or Y S (ω) is input to receiver  206 . 
   As shown in  FIG. 2B , transmission channel  201  can be modeled as having a linear, time invariant portion  202  with transfer function H S (ω) and a noise portion represented as noise adder  203 . The transfer function H S (ω) includes the effects of transmit and receive transformers and the transmission medium (e.g., cable) on the transmitted signal. The input signal A S (ω) to transmission channel  201  and thus to portion  202  is related to the output signal X S (ω) of portion  202  by the relationship
 
 X   S (ω)= H   S (ω) A   S (ω).  (3)
 
The total output signal Y S (ω) from transmission channel  201  then is
 
 Y   S (ω)= H   S (ω) A   S (ω)+ n   S (ω),  (4)
 
where n S (ω) is a random noise component. Equations 3 and 4 assume a linear, time invariant transmission system.
 
   For long cable lengths, the intersymbol interference contained in signal Y S (ω) can be severe, including significant portions of previously transmitted symbols in Y S (ω). For example, at a cable length of above about 100 meters, the contribution of the last sent symbol to the currently received signal may be as high as 95%. 
   Receiver system  206  contains an analog amplifier  222 , a pre-filter  207 , and a receiver  208  constituted as a digital filter. Amplifier  222  amplifies signal y k  or Y S (ω) from transmission channel  201 . Pre-filter  207  is described in the immediately following paragraphs. Digital filter  208  contains an anti-aliasing filter  209 , an analog-to-digital converter  210 , a digital amplifier  211 , a digital equalizer  212 , a slicer  213 , a coefficient update  214 , a digital automatic gain control  215 , a clock recovery  216 , a phase detector  217 , and an analog automatic gain control  220 . Similar to how components  217  and  220  are depicted in  FIG. 6B  below, components  217  and  220  could be described as outside digital filter  208  since their output signals go to components that precede digital filter  208 . 
   Pre-filter  207  receives the amplified signal from amplifier  222  and pre-shapes that signal for input to digital filter (receiver)  208 . The pre-shaping performed by pre-filter  207  can include partial removal of intersymbol interference so that less intersymbol interference remains to be removed by digital equalizer  212 . 
   Pre-filter  207  can be designed based on frequency-sampling methods in which a desired frequency response is uniformly sampled and filter coefficients are then determined from these samples using an inverse discrete Fourier transform. For example, one embodiment of pre-filter  207  includes a one-zero two-pole filter having a frequency response of approximately the inverse of, for example, the transfer function H S (ω) associated with a 50 meter cable (CAT-5) in combination with any pre-shaping that may have been performed by transmitter  221 . Pre-filter  207 , therefore, can be fixed to remove the influence of intersymbol interference from a given cable configuration, e.g., a twisted-copper pair having a particular length. Variations in the intersymbol interference inherent in variations of the cable or its length from that expected can be accommodated by adaptive functions in digital equalizer  212 . 
   Although pre-filter  207  can be any number of filters coupled in series, pre-filter  207  can be represented with a transfer function H PF (ω) that represents the effects on an input signal of all of the filters in pre-filter  207 . Therefore, assuming that pre-filter  207  is linear and time-invariant, the Fourier transform output signal Z S (ω) from pre-filter  207  is given by
 
 Z   S (ω)= GH   PF (ω) Y   S (ω),  (5)
 
where G is the analog gain of analog amplifier  222 . The transfer function H T (ω) that represents the combination of transmission channel  201 , amplifier  222 , and pre-filter  207  is given by
 
 H   T (ω)= GH   S (ω) H   PF (ω).  (6)
 
Ideally, if pre-filter  207  completely compensates for transmission channel  201 , the total transfer function H T (ω) is unity. In a practical transmission system, the transfer function H PF (ω) of pre-filter  207  is determined by inverting the predicted or measured transfer function H S (ω) of transmission channel  201 .
 
   The frequency response H c (f,l) of the complete channel, i.e., transmission system  200  including transmission channel  201  and digital filter  208 , neglecting random noise n S (ω) and not including the frequency response of pre-filter  207 , can be modeled as
 
 H   c ( f,l )= H   PR ( z ) H   S ( f,l ) H   EQ ( z ) gG H   co ( f )  (7)
 
where H PR (z) is the partial response shaping accomplished by transmitter  221  before transmission, z equals e jωT , ω equals 2πf, f is the frequency, and T is the symbol (and sampling) interval. H S (f,l) is the frequency response of transmission channel  201 , e.g., the CAT-5 cable, of length l and the transmit and receive transformers. In one embodiment, the partial response shaping H PR (z) equals 0.75+0.25z −1  where z −1  represents a one-symbol period delay. H EQ (z) is the transfer function of digital equalizer  212  and is generally given by
 
             ∑     i   =     -   N       M     ⁢           ⁢       c   i     ⁢     z     -   i               
where N and M are positive integers. Inasmuch as z −1  represents a one-symbol period delay, z represents a one-symbol period advance. In one embodiment, equalizer transfer function H EQ (z) is chosen to be c −1 z+c 0 +c 1 z −1 . The parameter g is the output gain of automatic gain control (AGC)  215  in digital filter  208 . H co (f) represents the frequency response of the remaining elements of the complete channel, e.g., analog-to-digital converter  210  (whose pulse can be a rectangular pulse of length T or a trapezoidal pulse with rising and falling edges of length T/2 and flat portion of length T/2) and other elements of transmission channel  201 .
 
   The frequency response H S (f,l) of transmission channel  201  is a function of cable length l. Both gain g and digital equalizer transfer function H EQ (z) depend on cable length l. The gain g is increased for increased cable length l due to increased signal loss. The coefficient parameters c −1 , c 0 , and c 1  of equalizer transfer function H EQ (z) also depend on cable length l. Channel-remainder frequency response H co (f) is not a function of cable length l. 
   Examples of the frequency response for transmission system  200  are shown in  FIGS. 3A through 3D .  FIG. 3A  shows the transfer function H S (ω) of transmission channel  201 . As shown in  FIG. 3A , transmission-channel transfer function H S (ω) approaches zero asymptotically.  FIG. 3B  shows signal e −Sτ  where s equals jω, and τ is the timing phase difference discussed below.  FIG. 3C  represents the transfer function H PF (s) of pre-filter  207 .  FIG. 3D  represents the total frequency response or the product of the signals represented in  FIGS. 3A ,  3 B and  3 C. 
   The frequency response H c (f,l) of the complete channel does not include the effects of pre-filter  207 . The transfer function H PF (s) of analog pre-filter  207  can be represented by (b 1 s+1)/(a 2 s 2 +a 1 s+1), where s again equals jω. Pre-filter transfer function H PF (s), therefore, is characterized by the filter parameters b 1 , a 1 , and a 2 . Transfer function H PF (s) can be determined by minimizing a cost function that is related to the total intersymbol interference found in transmission system  200 . 
   A measure E(1) of the intersymbol interference due to the comparison of the folded spectrum with a flat spectrum can be expressed as
 
 E ( l )=∫ −1/2T   1/2T   |[H   c ( f,l ) H   PF ( s ) e   jωτ ] fold −1| 2   df.   (8)
 
The parameter τ is the timing phase difference between the transmitter digital-to-analog converter (not shown) and the receiver analog-to-digital converter (ADC)  210  as calculated by clock recovery  216 . The integral in Equation 8 represents the inverse discrete Fourier transform of all signals received in one period, e.g., −0.5/T to 0.5/T. The folded spectrum in the integral can be described by spectrum folding, which can be defined as
 
                       [     X   ⁡     (   f   )       ]     fold     =       1   T     ⁢       ∑   i             ⁢           ⁢     X   ⁡     (     f   -     i   T       )             ,           (   9   )               
where X(f) is any general function of frequency.
 
   In one embodiment, the transfer function H PF (s) of analog pre-filter  207  is obtained by minimizing the cost function C given as 
                 C   =         ∑     i   =   1     K     ⁢           ⁢       w   i     ⁢     E   ⁡     (     l   i     )           +       w     K   +   1       ⁢   P               (   10   )               
with respect to the filter parameters b 1 , a 1 , and a 2  where w i  is a weight factor, l i  is the ith cable length, K is the number of cable lengths, and P is a high frequency penalty. The first K terms are a measure of intersymbol interference at cable lengths l 1 , l 2 , . . . l K . In one embodiment, K equals 3. Although any number K of cable lengths can generally be used, minimizing cost function C for K equal to 1 results in an implementation of pre-filter  207  optimized for only one cable length. Alternatively, using too many cable lengths complicates the optimization.
 
   The last term P in Equation 10,
 
 P=∫   1/2   T   ∞   |H   PF ( s )| 2   df   (11)
 
imposes an additional penalty on the high frequency components of pre-filter transfer function H PF (s). The high frequency penalty P operates to attenuate high frequency echoes. Other factors can be included in a cost function. For example, a term to reduce quantization noise can be added. This quantization term would be proportional to g√{square root over (c 1   2 +c 2   2 + . . . +c K   2 )}.
 
   Each term in the cost shown in Equation 10 is weighted by a weight factor w i . These weights specify the importance of each term. The weights are chosen such that the peak magnitude of pre-filter transfer function H PF (s) is not too large and so that transfer function H PF (s) is small at high frequencies. The analog pre-filter  207  determined by transfer function H PF (s) found by optimizing cost function C of Equation 10 minimizes the intersymbol interference for cable lengths l 1  through l K  and attenuates high frequency echo signals. 
   As previously described, transmission-channel transfer function H S (ω,l), gain g, and equalizer transfer function H EQ (z) all depend on cable length l. Timing phase difference τ from clock recovery  216  also depends on cable length l. Therefore, intersymbol interference measures E(1 1 ) through E(1 K ) are all different. The parameters G, g, τ, the equalizer parameters in equalizer transfer function H EQ (z) (e.g., c −1 , c 0 , and c 1 ), and the measurement parameters in intersymbol interference measures E(1 1 ) through E(1 K ) are those parameters that the adaptive loops in analog gain control  220 , gain control  215 , clock recovery  216 , and coefficient update  214  converge for cable lengths l through l K , respectively. 
   Minimizing intersymbol interference measure E(1) with respect to parameters b 1 , a 1 , and a 2  should enable transfer function H PF (s) for pre-filter  207  to produce a flat folded spectrum if the cable length is l. However, this is based on the assumption that the actual equalizer parameters for equalizer transfer function H EQ (z), analog gain G, digital gain g, and timing phase τ are the same as those used in Equation 8 for measure E(1). If they are different, the results are less useful. 
   The better determination of equalizer parameters for equalizer transfer function H EQ (z), gain g, and timing phase τ is found by an iterative procedure as described below, resulting in determination of pre-filter transfer function H PF (s). With an initial choice of equalizer parameters for equalizer transfer function H EQ (z), gain g, and timing phase τ, the cost function C is minimized to determine an initial version of pre-filter transfer function H PF (s). Using this H PF (s) version, the equalizer parameters for equalizer transfer function H EQ (z), gain g, and timing phase τ are determined for each cable length l 1  through l K . Using these new sets of equalizer parameters for transfer function H EQ (z), gain g, and timing phase τ (one set of parameters for each cable length l 1  through l K ) in the cost function C, pre-filter transfer function H PF (s) is recomputed. This process is repeated until there are no significant changes between successive iterations. In other words, the above procedure converges to a particular set of filter parameters for transfer function H PF (s) that determines pre-filter  207 . 
   In one case, transmission-channel transfer function H S (ω) includes the frequency response of the transmit and receive transformers, each of which is modeled as a first order transfer function with −3 dB cutoff at 100 MHz. Additionally, transmission channel  201  is a category-5 twisted copper pair cable, equalizer transfer function H EQ (z) equals c −1 z+c 0 +c 1 z −1 , partial response shaping H PR (z) equals 0.75+0.25z −1 , and pulse length T equals 8 ns. The optimization of the cost function C in Equation 10 with K equal to 3 and cable lengths l 1  equal to 0 m, l 2  equal to 50 m, and l 3  equal to 120 m leads to filter transfer function H PF (s) for pre-filter  207  described by 
                       H   PF     ⁡     (   s   )       =         0.8077   ⁢     s   ^       +   1         0.1174   ⁢       s   ^     2       +     0.1255   ⁢     s   ^       +   1         ,           (   12   )               
where ŝ equals sT.
 
   Alternatively, pre-filter  207  can be an adaptive analog filter. Transfer function H PF (s) for an adaptive analog version of pre-filter  207  can be of the form
 
 H   PF ( s )=(1 −V   c )+ V   c   PF ( s )  (13)
 
and is controlled by the single parameter V c  where PF(s) is an analog filter function. The parameter V c  is varied in the range 0&lt;V c &lt;1 to achieve partial equalization for various cable lengths. If V c  equals 0, pre-filter transfer function H PF (s) is 1 (unity), i.e., no equalization is performed by pre-filter  207 . If V c  equals 1, transfer function H PF (s) is analog filter function PF(s), i.e., maximum attainable equalization is achieved by the filter structure defined by analog function PF(s) for pre-filter  207 . As V c  is varied linearly from 0 to 1, pre-filter transfer function H PF (s) varies from unity to analog function PF(s).
 
   Analog filter function PF(s) can represent a band-pass or high-pass filter. Therefore, the peak magnitude of the frequency response of pre-filter transfer function H PF (s) increases with increasing V c . If analog function PF(s) performs suitable equalization for a particular cable length l o , pre-filter  207  with V c &lt;1 performs suitably for cable length l&lt;l o . Hence V c  is monotonic with cable length l. 
   For example, analog filter function PF(s) can have one zero and two poles (complex-conjugate pair) in the form 
                     PF   ⁡     (   s   )       =         ω   n   2       ω   z       ·       s   +     ω   z           s   2     +     2   ⁢     δω   n     ⁢   s     +     ω   n   2             ,           (   14   )               
where ω z  is the zero frequency, ω n  is the pole frequency, and δ is a damping factor.
 
   At low frequency, the filter described by Equation 14 starts from unity and rolls off as 1/s at high frequencies. Hence the filter passes less noise and high frequency echo. Moreover, a small order PF(s) requires fewer resistors, capacitors, and operational amplifiers to realize the circuit, which implies less sources of circuit noise and also easier and cheaper implementation for pre-filter  207 . In another embodiment, analog filter function PF(s) is the optimized analog filter function that optimizes the cost C described in Equation 10 for one cable length where that length is the maximum targeted cable length. Parameter V C  can be adapted, then, to shorter cable lengths. 
   To minimize the peak magnitude of the filter structure H PF (s), two stages of filter structures, namely pre-filter transfer function H PF (s) equals H 1 (s)H 2 (s) where H 1 (s) and H 2 (s) are the respective transfer functions for a pair of cascaded analog filters, can be utilized. In this case,
 
 H   1 ( s )=(1 −V   c1 )+ V   c1   PF ( s ),  (15)
 
and
 
 H   2 ( s )=(1 −V   c2 )+ V   c2   PF ( s ).  (16)
 
For example, analog filter function PF(s) could be a one-zero two-pole filter with the zero at 30 MHz and complex-conjugate pair poles at 70 MHz with a damping factor of 0.4. That is, zero frequency ω z  equals 60π×10 6  radians/sec., pole frequency ω n  equals 140π×10 6  radians/sec., and damping factor δ equals 0.4 in Equation 14 above. A cascade of filter transfer functions H 1 (s) and H 2 (s) each with the above PF(s) analog function can provide good partial equalization for a wide range of cable lengths.
 
   In one embodiment, the digital equalizer transfer function H EQ (z) executed by equalizer  212  can be expressed in the form
 
 H   EQ ( z )= c   −1   z+c   0   +c   1   z   −1   +c   2   z   −2   + . . . +c   K   z   −K   (17)
 
The first two coefficients c −1  and c 0  can be fixed (i.e., coefficient update  214  does not alter coefficient c −1  or c 0 ). For example, the first two equalizer coefficients can be set at c −1  equal to −⅛ and c 0  equal to 1. The remaining equalizer coefficients c 1  through c K  are adaptively chosen by coefficient update  214 . The parameter K can be any positive integer. For a fixed (non-adaptive) analog filter, equalizer coefficient c 1  decreases monotonically with cable length. Therefore, equalizer coefficient c 1  is a good indicator of cable length. Additionally, AGC gain g is also a good indicator of cable length. Equalizer coefficient c 1  or gain g can be compared to a threshold Th AEQ  and the result of that comparison used to adapt analog pre-filter  207 .
 
   In  FIG. 2A , phase detector  217  executes an updating algorithm with equalizer coefficient c 1  in order to choose adaptive parameters for analog pre-filter  207 . In phase detector  217 , a phase detection parameter PD AEQ  can be calculated by
 
 PD   AEQ =−( c   1   −Th   AEQ ).  (18)
 
The amount of threshold Th AEQ  determines how much equalization is performed in analog pre-filter  207  and how much is performed in digital equalizer  212 . In one example, coefficient c 1  varies between about −0.35 to about −1.0 and threshold Th AEQ  is chosen to be about −0.4.
 
   Phase detector  217  operates to control pre-filter parameter V c . In a cascading prefilter, phase detector  217  controls any number of adaptive analog filter parameters V c1  through V cN  where N is the total number of cascaded analog prefilters included in analog pre-filter  207 . One method of adaptively choosing a value for parameter V c  (or each of parameters V c1  through V cN ) is to increment or decrement the value of V c  based on whether the calculated phase detection parameter PD AEQ  is positive or negative. Alternatively, phase detector  217  may include an accumulator that inputs the calculated parameter PD AEQ  and outputs a signal that controls parameter V c . 
   Additionally, in receiver (digital filter)  208  of  FIG. 2A , analog AGC  220  and analog amplifier  222  scale the input signal to analog pre-filter  207 , and thus input signal Z S (ω) to digital filter  208 , so that the entire dynamic range of ADC  210  is utilized while keeping the probability of saturation very low. Analog AGC  220  inputs the signal output of ADC  210 . 
   Analog AGC  220  outputs a signal to amplifier  222  which adjusts the output level of pre-filter  207  to optimize the functionality of ADC  210 . In one embodiment, AGC  220  calculates a phase detector parameter PD AGC  for the loop, accumulates the results of the phase detect parameter calculation, and converts the accumulated phase detector parameter to an analog signal which is input by pre-filter  207 . Phase detector parameter PD AGC  for this loop can be defined as
 
 PD   AGC   [k]=α   k,1 +α k,2 ,  (19)
 
where
 
                     α     k   ,   1       =     (           -   1             if   ⁢           ⁢          α   k            &gt;     Th   AGC               0       otherwise         )       ,           (   20   )                 α     k   ,   2       =       (         1           if   ⁢           ⁢   k   ⁢           ⁢     mod   ⁡     (   N   )         =   0             0       otherwise         )     .             (   21   )               
Variable α k  is the output signal from ADC  210  during time period k, i.e., at time instant t equal to kT, and modulus number N is chosen to make use of the range of ADC  210 .
 
   At the convergence of the phase loop in AGC  220 , i.e., the steady-state condition, the expected value of phase detection parameter PD AGC  is 0. This ensures that the probability of |α k | being greater than Th AGC  is 1/N for any time period k. The threshold value Th AGC  and modulus number N are suitably chosen to make good use of the A/D range. For the application of Gigabit Ethernet, Th AGC  and N are chosen such that the probability of saturation of ADC  210  is less than about 10 −6 . In one example, Th AGC  is about 0.8 of the range of ADC  210 , for example, 50 in a 7 bit ADC, and N is about 1024. 
   In general, pre-filter  207  can be arranged to reduce or eliminate the intersymbol interference inherent in any length cable. Once a transfer function, such as that given in Equation 12 or 14, is determined for a particular configuration of transmission channel  201 , one skilled in the art of filter design can construct the appropriate filter. Therefore, a transfer function such as that shown in Equation 12 or 14 completely describes an analog filter which can be utilized for equalization in pre-filter  207 . 
   As shown in  FIG. 2A , the analog signal output Z S (ω), which is the input symbol sequence {a k } distorted by the transmission channel and filtered by pre-filter  207  in the above described fashion, is input to digital receiver  208 . Anti-aliasing filter  209  receives analog signal Z S (ω) from analog pre-filter  207 . In most embodiments, anti-aliasing filter  209  is an analog low pass filter. 
   Analog-to-digital converter  210  is coupled to receive an output signal from anti-aliasing filter  209 . ADC  210  can have any accuracy, but in most embodiments a six to eight bit converter is utilized. Due to pre-filter  207 , the linearity, i.e., number of bits, requirement of ADC  210  is reduced. For example, by using a 50-meter cable (CAT-5) plus transmit shaping, as described above, the ADC requirements can be significantly reduced if receiver  206  includes a pre-filter implementing the transfer function described by Equation 8. The requirements of ADC  210  may be reduced from an 8-bit ADC to a 6-bit ADC at 125 megasamples per second, for example. 
   By reducing the linearity of the ADC requirements, a linear equalizer is used in one embodiment rather than a decision feedback equalizer or a more complicated trellis decoder. In addition, by using pre-filter  207 , critical timing loops normally associated with Gigabit receiver designs are eliminated. Experiment has shown that the time complexity of the critical path required to implement a 4D, 8-state trellis decoder in a Gigabit receiver is reduced. The reduction in complexity inherent in reducing the distortion in the signal input to digital receiver  208  can result in receivers having fewer components and simpler implementations. 
   A discrete-time model of the response of transmission channel  201  in combination with pre-filter  207  is shown in  FIG. 4  and includes a channel response  204 , represented by the channel function (f(z), and a noise adder  205 . Noise adder  205  represents addition of a random noise factor n k  to the transmitted signal. The discrete-time model is particularly applicable for digital receiver  208 . In that case, transfer function f(z) is a folded spectrum of the combined frequency response H PR (z)H S (ω)H PF (ω)H co (ω). 
   It is assumed that the channel model includes the effect of transmit and receive filtering. In addition, transmission channel  201  is assumed to be linear in that two overlapping signals simply add as a linear superposition. Therefore, the channel function polynomial f(z) of channel response  204  can be defined as
 
 f ( z )= f   0   +f   1   z   −1   +f   2   z   −2   + . . . +f   N   z   −N ,  (22)
 
where f 0 , . . . , f j , . . . , and f N  are the polynomial coefficients representing the dispersed component of the (k−j)th symbol present in the symbol a k , z −1  represents a one-symbol period delay, and N is a cut-off integer such that f j  for j&gt;N is negligible. The polynomial f(z) represents the frequency response of transmission channel  201  in combination with pre-filter  207 . See A. V. O PPENHEIM  &amp; R. W. S CHAFER , D ISCRETE -T IME  S IGNAL  P ROCESSING  1989.
 
   The noiseless output signal x k  of transmission channel  201  at sample time k, i.e., the output signal from channel response  204 , is then given by
 
 x   k   =f   0   *a   k   +f   1   *a   k−1   + . . . f   N   *a   k−N   (23)
 
Thus, the channel output signal at time k depends, not only on transmitted data at time k, but also on past values of the transmitted data, i.e., there remains some intersymbol interference.
 
   The noise element of the input signal, represented by noise adder  205 , is represented by the sequence {n k }. Therefore, the noisy output α k  of the channel, i.e., the output signal from ADC  210 , is given by
 
α k   =x   k   +n   k ,  (24)
 
where the noise samples {n k } are assumed to be independent and identically distributed Gaussian random variables (See E. A. L EE AND  D. G. M ESSERCHMITT , D IGITAL  C OMMUNICATIONS  (1988)) with variance equal to σ 2 .
 
   Digital amplifier  211  amplifies the output signal α k  from analog-to-digital converter  210  to adjust for the loss of signal resulting from the transmission through transmission channel  201  and pre-filter  207 . Equalizer  212  equalizes the amplified version of signal α k  to produce equalized signal a k  as indicated in  FIG. 2A . 
   Equalizer  212  can be any type of equalizer including a linear equalizer, a decision feedback equalizer, or a sequence detector, alone or in combination. Examples of equalizers applicable to 100 or 1000 BASE-T Ethernet over category-5 wiring, 24 gauge twisted copper pair, are discussed in U.S. patent application Ser. No. 08/974,450, filed Nov. 20, 1997, Raghavan, assigned to the same assignee as the present application, now U.S. Pat. No. 6,083,269, herein incorporated by reference in its entirety; and U.S. patent application Ser. No. 09/020,628, filed Feb. 9, 1998, Raghavan, assigned to the same assignee as the present application, now U.S. Pat. No. 6,115,418, herein incorporated by reference in its entirety. 
   Further examples of equalization systems are described in U.S. patent application Ser. No. 09/296,086, filed Apr. 21, 1999, Raghavan et al., assigned to the same assignee as the present application, now U.S. Pat. No. 6,418,172 B1, herein incorporated by reference in its entirety; U.S. patent application Ser. No. 09/151,525, filed Sep. 11, 1998, Raghavan, assigned to the same assignee as the present application, now U.S. Pat. No. 6,415,003 B1, herein incorporated by reference in its entirety; U.S. patent application Ser. No. 09/161,346, filed Sep. 25, 1998, Raghavan et al., assigned to the same assignee as the present application, now U.S. Pat. No. 6,438,163 B1, herein incorporated by reference in its entirety; and U.S. patent application Ser. No. 09/560,109, filed Apr. 28, 2000, Sallaway et al., assigned to the same assignee as the present application, now U.S. Pat. No. 7,050,517 B1, herein incorporated by reference in its entirety. 
   Slicer  213  receives signal stream {a k } from equalizer  212  and, based on that stream {a k }, decides on an output symbol stream {â k }. The output symbol stream {â k } represents the best estimate of receiver  208  of the symbol stream {a k } that was originally transmitted by transmitter  221 . 
   Receiver  208  may be an adaptive receiver, further including coefficient update  214  that adjusts the coefficient parameters of equalizer  212  in order to optimize the performance of receiver  208 . Receiver  208  may also include automatic gain control (AGC)  215  that dynamically adjusts the gain of amplifier  211  in order to maximize the efficiency of receiver  208 . Furthermore, clock recovery  216  can provide timing and framing for analog-to-digital converter  210 , representing an element of a phase-locked loop. 
     FIG. 5A  shows an embodiment of another receiver  506  according to the present invention. Receiver  506  includes pre-filter  207 , anti-aliasing filter  209 , analog-to-digital converter  210 , amplifier  211 , and digital equalizer  212 . Although digital equalizer  212  can be any equalizer system, as has been previously described, digital equalizer  212  in  FIG. 5A  is shown as having an equalizer  511  coupled in series with a trellis decoder  512 . Equalizer systems are described in U.S. patent application Ser. Nos. 08/974,450, 09/020,628, 09/161,346, 09/296,086, 09/151,525, and 09/560,109, all cited above, and will not be further discussed here. 
   Receiver  506  also includes adaptive coefficient update  214  which adaptively chooses the operating parameters of equalizer  511 , gain control  215  which adaptively chooses the gain setting of amplifier  211 , and clock recovery  216  which forms the phase-locked-loop required to frame the data acquisition by analog-to-digital converter  210 . 
   Receiver  506  can further include a baseline wander correction circuit  510  that, when combined with adder  515 , corrects the output signal α k  of analog-to-digital converter  210  for signal wander. Baseline wander correction is further described in U.S. patent application Ser. No. 09/151,525, cited above. Receiver  506  can also include an A/D reference adjuster  517 , which adjusts the reference voltage of analog-to-digital converter  210  according to the measured apparent length of the cable associated with transmission channel  201 . 
   Receiver  506  can include a cable quality and length calculator  518 . As described in U.S. patent application Ser. No. 09/161,346, cited above, cable quality and length calculator  518  calculates the length of cable in transmission channel  201  and the quality of transmission channel  201  based on the gain calculation of gain control  215  or the equalizer coefficients of equalizer  511 . Both A/D reference adjuster  517  and cable quality and length calculator  518  are affected by pre-filter  207 , which has the effect of simultaneously making transmission channel  201  appear to be of very high quality and to make the cable length of transmission channel  201  appear longer. The apparent quality increases because pre-filter  207  removes some of the interference caused by transmission channel  201 . The cable appears longer if there is any loss of signal strength in pre-filter  207 . Cable quality and length calculator  518  can, however, adjust for the presence of pre-filter  207  in order to have accurate calculations of cable length and quality. 
   Receiver  506  can also include an echo canceller  513  and a NEXT canceller  514 . NEXT canceller  514  cancels interference on one transmission line based on the transmission of symbols over neighboring lines. Echo canceller  513  cancels interference from symbols transmitted by a transmitter (not shown) associated with receiver  506 . 
   In some transmission systems, signals are transmitted over a cable having multiple wires. Transmission channel  201  and receiver  506  represent detection of the transmitted signal over one of the multiple wires. In that case, signals on neighboring wires affect the transmitted signal on transmission channel  201 . NEXT canceller  514  computes the influence of transmitted signal from other pairs of wires at the input of adder  519 . The projected influence from symbols transmitted on neighboring lines is subtracted from the digitized symbol by adder  519 . 
   Echo canceller  513  subtracts the influence of symbols that are reflected back into receiver  506  by transmission along a cable associated with transmission channel  201 . In most transceiver systems, receiver  506  and a transmitter (not shown) are coupled to a common host. The transmitter transmits signals through transmission channel  201  to a receiver counterpart (not shown) of transmitter  221 . Some of that transmitted signal may be reflected back into receiver  506 . Echo canceller  513  projects the reflected signal based on the transmitted signals and subtracts the influence of that signal at adder  516  and adder  519 . 
     FIG. 5B  shows an embodiment of pre-filter  207  that is sensitive to the cable length of transmission channel  201 . Pre-filter  207  as shown in  FIG. 5B  includes pre-filters  520 - 1  through  520 -N. Pre-filters  520 - 1  through  520 -N execute transfer functions H PF   1 (ω) through H PF   N (ω), respectively. Each of pre-filters  520 - 1  through  520 -N is optimized to counter the interference from a transmission channel having a particular cable length. Each pre-filter  520 - i  can be designed by minimizing a cost function such as that shown in Equation 10. A selector  521 , in response to the cable length L calculated by cable quality and length calculator  518  ( FIG. 5A ), selects one of pre-filters  520 - 1  through  520 -N. Selector  521  controls a switch  522  which supplies input signal Y S (ω) to the selected one of pre-filters  520 - 1  through  520 -N. Therefore, pre-filter  207  can be selected in order to optimize the performance of receiver  506 . 
     FIG. 5C  shows another embodiment of pre-filter  207  according to the present invention. Pre-filter  207  of  FIG. 5C  executes the adaptively controlled transfer function of Equation 13. Input signal Y S (ω) is input to block  525  which executes the transfer function PF(s). Transfer function PF(s) can, for example, be the transfer function of Equation 14. The input signal Y S (ω) is also input to block  526  which executes the transfer function one. The output signal from block  525  is multiplied by the adaptively chosen parameter V c  in multiplier  527  and input to adder  529 . The output signal from block  526  is multiplied by 1−V c  in multiplier  218  and added to the output signal from multiplier  527  by adder  529 . The output signal from adder  529  is the output signal Z S (ω) from pre-filter  207 . 
     FIG. 6A  shows a multi-wire receiver  600  according to the present invention. Transmission receiver  600  receives input analog signal streams {y k   (1) } through {y k   (M) } from M wires  603 - 1  through  603 -M, respectively. Signal streams {y k   (1) } through {y k   (M) } are also indicated as input signals Y S   (1) (ω) through Y S   (M) (ω), respectively, in  FIG. 6A . Each receiver input signal Y S   (i) (ω) is the Fourier transform of receiver input analog signal y k   (i)  for integer i running from 1 to M. Each of input signals Y S   (1) (ω) through Y S   (M) (ω) includes the effects of a transmission channel  601 , as described above for transmission channel  201 . Additionally, each of signals Y S   (1) (ω) through Y S   (M) (ω) includes effects of cross talk between wires so that, for example, signal Y S   (i) (ω), where the ith wire  603 - i  is an arbitrary one of wires  603 - 1  through  603 -M, includes a contribution from signals on all of the other wires, i.e., wires  603 - 1  through  603 -( i− 1) and wires  603 -( i+ 1) through  603 -M. 
   Individual receivers  602 - 1  through  602 -M receive input signals Y S   (1) (ω) through Y S   (M) (ω), respectively, i.e., input analog signal streams {y k   (1) } through {y k   (M) }, respectively, and generate output signal streams {a k ′ (1) } through {a k ′ (M) }, respectively. In some embodiments, signal streams {a k ′ (1) } through {a k ′ (M) } are input to slicers (not shown in  FIG. 6A ) within receivers  602 - 1  through  602 -M, respectively. The slicers in receivers  602 - 1  through  602 -M determine symbol streams {â k   (1) } through {â k   (M) } (also not shown in  FIG. 6A ), respectively, as discussed below in connection with  FIG. 6B  for an embodiment of one of receivers  602 - 1  through  602 -M. Symbol streams {â k   (1) } through {â k   (M) } here are temporary decisions made in order to control the adaptation of parameters within receivers  602 - 1  through  602 -M, respectively. 
   An arbitrary receiver  602 - i , which is one of receivers  602 - 1  through  602 -M, also inputs the output symbol streams {Tx k   (1) } through {Tx k   (M) } from a transmitter  606  associated with receiver  600 . Each of receivers  602 - 1  through  602 -M can then include echo cancellation and near end crosstalk (NEXT) cancellation due to the transmitted symbols of transmitter  606 . As indicated in  FIG. 6A , each output symbol stream {Tx k   (i) } is also supplied on corresponding wire  603 - i  to transmission channel  601 . 
   In some embodiments, receiver output signal streams {a k ′ (1) } through {a k ′ (M) } are input to a delay skew compensator  604 .  FIG. 6A  depicts such an embodiment. Delay skew compensator  604  provides output signal streams, also denoted as {a k ′ (1) } through {a k ′ (M) } here, that are input to a multi-dimensional (M-D) decoder  605  for final decision on the received symbols. 
   Delay skew compensator  604  aligns the M signal streams {a k ′ (1) } through {a k ′ (M) }, i.e., compensator  604  aligns signals a k ′ (1)  through a k ′ (M)  at each time period (or clock cycle) k, so that any delays between signal streams {a k ′ (1) } through {a k ′ (M) } received from receivers  602 - 1  through  602 -M, respectively, are removed. Relative delays between signal streams {a k ′ (1) } through {a k ′ (M) } may be introduced in transmission channel  601  or by receivers  602 - 1  through  602 -M. The aligned signals a k ′ (1)  through a k ′ (M)  from delay skew compensator  604  for a particular clock cycle k arrive at M-D decoder  605  simultaneously. 
   Decoder  605 , which may be a Viterbi decoder, uses aligned signal streams {a k ′ (1) } through {a k ′ (M) } to make a final decision on the incoming data. The final decision of decoder  605  is indicated in  FIG. 6A  as M output symbol streams {a k ′ (1) } through {a k ′ (M) }. 
   Additionally, decoder  605  may utilize an error detecting code such as that defined in the IEEE standard for Gigabit Ethernet. See, e.g., IEEE 802.3ab, “Gigabit Long Haul Copper Physical Layer Standards Committee”, 1997 Standard. In one embodiment, M-D decoder  605  is a Viterbi decoder which makes a final decision on data which has been encoded by an 8-state Ungerboeck code, as described in the IEEE Gigabit Spec. The Viterbi decoder in this embodiment is a maximum likelihood sequence estimator, as described in Viterbi, A. J., “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Trans. Inf. Theory, IT-13, pages 260-269, April 1967, herein incorporated by reference in its entirety. M-D decoder  605 , therefore, maximizes the probability of correctly estimating the entire sequence of symbols. 
     FIG. 6B  shows an embodiment of a receiver  602 - i  that includes an analog prefilter  619  and a digital filter  620 . Analog prefilter  619  includes a DC offset adder  610  coupled to a DC offset correction circuit  628 , an echo canceller adder  611  coupled to an analog echo canceller circuit  627 , an analog multiplier  612  coupled to analog automatic gain control circuit  220 , and analog equalizers  613  and  614  coupled to analog equalizer adaptor circuit (phase detector)  217 . Digital filter  620  includes digital equalizer  212 , a digital echo/NEXT canceller adder  615  coupled to a digital echo canceller  621  and to NEXT cancellers  618 - 1  through  618 -M without a canceller  618 - i , AGC booster (digital amplifier)  211  coupled to digital automatic gain control circuit  215 , a baseline wander subtracter (or adder)  616  coupled to a baseline wander correction circuit  617 , and slicer  213 . Analog portion  619  is coupled to digital portion  620  through analog-to-digital converter  210 . For exemplary purposes, slicer  213  is shown as a PAM-5 decoder. Timing recovery loop (clock recovery)  216  controls a clock used in both the analog and digital portions of receiver  602 - i  and calculates the timing phase parameter τ k   (i) . 
   Slicer  213  provides (a) a temporary decision â k   (i)  on the kth symbol a k   (i)  intended to be transmitted in signal stream {y k   (i) } on wire  603 - i  and (b) an error e k   (i)  based on input signal a k ′ (i) , where error e k   (i)  is defined as
 
 e   k   (i)   =a   k ′ (i)   â   k   (i)   (25)
 
The temporary decision â k   (i)  and error e k   (i)  are utilized in various circuit loops in receiver  602 - i  in order to adapt parameters in receiver  602 - i . As discussed below and indicated in  FIG. 6B , temporary decision â k   (i)  and error e k   (i)  are also utilized to adapt parameters in analog prefilter  619 .
 
   DC offset correction circuit  628  includes an ADCO control  633  coupled to a digital-to-analog converter (DAC)  634 . DAC  634  provides a signal which is negatively added to the received signal Y S   (i) (ω) in DC offset adder  610 . ADCO control  633  inputs the output signal α k   (i)  from ADC  210  and estimates the DC offset that occurs in analog prefilter  619 . This calculated DC offset, upon being converted from digital to analog form by DAC  634 , is then subtracted from the input signal Y S   (i) (ω) in adder  610 . 
   Analog echo canceller circuit  627  includes an AEC control  629 , DACs  630  and  631 , and an RC circuit  632 . AEC control  629  inputs the error signal e k   (i)  as well as the transmitted symbol stream {Tx k   (i) } on wire  603 - i  ( FIG. 6A ) and adapts the resistance R k   (i)  and capacitance C k   (i)  in RC circuit  632 . Transmit signal Tx k   (i)  is filtered in RC circuit  632 . Echo adder  611  subtracts the resultant filtered signal from input signal Y S   (i) (ω) minus the DC offset determined by DC offset correction circuit  628 . The parameters R k   (i)  and C k   (i)  are adapted to approximately duplicate the effects of the transmit signal Tx k   (i)  on the signal input to adder  611 . Appropriate values for R k   (i)  and C k   (i)  minimize the residual echo from the transmit signal Tx k   (i) , which results in minimizing the requirements of digital echo canceller circuit  621 . Furthermore, by minimizing the residual echo, analog AGC  220  can provide for maximum boost to input signal Y S   (i) (ω) through multiplier  612  without overloading ADC  210 , which results in clipping. The additional boost at multiplier  612  results in a lessened need for amplification at digital AGC booster  211 , thereby minimizing quantization noise. 
   Analogous to what occurs in receiver  206  of  FIG. 2A , analog gain control circuit  220  outputs a gain signal to multiplier  612  that adjusts the output levels of prefilter  619  to optimize the functionality of ADC  210 . Analog gain control circuit  220  contains AGC control circuit  625  and DAC  626 .  FIGS. 6C and 6D  show embodiments of analog gain control circuit  220 , specifically embodiments of AGC control circuit  625 . 
   One embodiment of AGC control circuit  625  is shown in  FIG. 6C . Test block  630  compares signal α k   (i)  with threshold Th AGC  and calculates, for each receiver  602 - i , value α k,1  according to Equation 20. The value α k,2  is calculated according to Equation 21. The value of PD AGC  is calculated according to Equation 19 in adder  631 . The value of PD AGC  is input to an adder  632 . The output signal of adder  632  goes to saturation block  633 . Saturation block  633  saturates at, for example, 13 bits. The output from saturation block  633  is delayed one clock cycle and added to PD AGC  at adder  632 . The combination of adder  632 , saturation block  633 , and delay  635  forms an accumulator. 
   The output signal of saturation block  633  is right shifted by a particular number of bits, for example, 7 bits, in shifter  634  to give an output signal of a particular number of bits, for example, 6 bits. The output signal from shifter  634  provides an input signal to DAC  626 . Multiplier  612  multiplies the analog output signal from DAC  626 , which is the output signal from analog AGC control circuit  220  ( FIG. 6B ), by the input signal Y S   (i) (ω) as modified by the subtractions at adders  610  and  611 . 
   Because of the low frequency nature, the input signal to DAC  626  of AGC  220  has very small variations from sample to sample. In most cases, the variation is at most one count.  FIG. 6D  shows an embodiment of analog AGC control circuit  220  (AGC control  625  and DAC  626 ) that takes advantage of this feature. Instead of a “general purpose” 6 bit D/A, a less expensive Sigma-Delta D/A is used for DAC  626  in the embodiment of  FIG. 6D . In that case, saturation block  633  is replaced with a smaller block  636  of size, for example, 7 bits. The accumulated value, i.e., the output signal from the accumulator formed by adder  632 , block  636  and delay  635 , is wrapped around (modulo) to a particular number of bits, for example 7 bits. 
   The output of block  636  is a three-level signal representing overflow, no change, or underflow of the accumulation value. The three-level signal is the output signal received by DAC  626  implemented as a Sigma-Delta DAC. DAC  626  then outputs an analog value which multiplier  612  multiplies by the input signal Y S   (i) (ω) again as modified by the subtractions at adders  610  and  611 . 
   In the embodiment shown in  FIG. 6B , the analog equalization is accomplished by analog equalizer  613  cascaded with analog equalizer  614 . Each of analog equalizer  613  and analog equalizer  614  is controlled by analog equalizer control circuit (phase detector)  217 . Analog equalizer control circuit  217  includes AEQ control  622  coupled to DAC  623 , which is coupled to control analog equalizer  613 , and coupled to DAC  624 , which is coupled to control analog equalizer  614 . Analog equalizers  613  and  614  accomplish partial equalization of the input signal Y S   (i) (ω), resulting in a lessened requirement for digital equalization. Analog equalizers  613  and  614  and analog equalization control circuit  217  operate as is described above in connection with Equations 14 through 18. 
   Analog-to-digital converter  210  receives the output signal Z S   (i) (ω) from analog prefilter  619  and digitizes the signal. The output from ADC  210  is signal α k   (i) . 
   ADC  210  samples input signal Z S   (i) (ω) based upon the clock output from timing recovery loop (clock recovery)  216  and phase τ k   (i) . Clock recovery  216  recovers the frequency of the received signal (i.e., the frequency of transmitter  221  ( FIG. 2 )) and finds the optimal value τ of the timing phase τ k   (i)  of the incoming signal. For a constant clock frequency offset between the remote transmitter&#39;s digital-to-analog converter and ADC  210 , the optimal timing phase τ varies linearly with time. The rate of change of phase τ k   (i)  is proportional to the clock frequency offset. 
   Clock recovery  216  can be a second order loop. One embodiment of clock recovery  216  is shown in  FIG. 6E . A phase detector  650  estimates the difference between the optimal phase τ and the current value of τ k   (i)  based on the output symbol â k   (i)  and the error calculation e k   (i) . The output signal PD CR  from phase detector  650  for receiver  602 - i  can be determined in several manners, including a slope method and a Mueller &amp; Muller (M&amp;M) method. In the M&amp;M method, the output signal PD CR  from phase detector  650  is
 
 PD   CR   =e   k−1   (i)   â   k   (i)   −e   k   (i)   â   k−1   (i)   (26)
 
In the slope method,
 
 PD   CR   =e   k   (i) slope( k ),  (27)
 
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   The output signal PD CR  from the phase detector  650  is input to a loop filter  651  that has a proportional part and an integral part. The output signal from loop filter  651 , indicating the correction on the clock frequency, is input to a frequency controlled oscillator  652  which causes ADC  210  to sample at an optimal phase by controlling the sampling frequency of ADC  210 . Frequency controlled oscillator  652 , in other words, outputs a clock signal whose zero-crossings are given by NT+τ k   (i) . 
   If the coefficient c −1  of digital equalizer  212  is adapted, the adaptation algorithms between coefficient update  214  and clock recovery  216  will interact adversely, often causing failure of receiver  600 . To prevent this interaction, coefficient c −1  is fixed, for example, at −⅛, in order that the timing loop can converge to an optimum phase. 
   Since part of the equalization is accomplished in analog equalizers  613  and  614 , digital equalizer  212  can be simplified. For example, digital equalizer  212  can be a linear equalizer without causing large amounts of noise enhancement. Of course, as has been previously discussed, other embodiments of digital equalizer  212  can use any equalization scheme. 
   High frequency signals are attenuated more by transmission channel  601  than are low frequency signals. The equalization, between analog equalizers  613  and  614  and digital equalizer  212 , then should equalize the attenuation difference across the frequency band. 
   In one embodiment, digital equalizer  212  in each receiver  602 - i  is a linear equalizer executing the transfer function H EQ   (i) (z) given as
 
 H   EQ   (i) ( z )= c   k,−1   (i)   z+c   k,0   (i)   +c   k,1   (i)   z   −1   + . . . +c   k,K   (i)   z   −K   (29)
 
The parameter K can be any positive integer, for example, 1 in some embodiments. The coefficient c k,−1   (i)  can be fixed, for example, at −⅛, to avoid interaction with the adaptation performed by timing recovery loop  216 . Further, the coefficient c k,0   (i)  can be fixed, for example, at 1, to avoid interaction with digital AGC  215 . The remaining equalizer coefficients c k,1   (i)  through c k,K   (i)  are adaptively chosen by coefficient update  214 . Equalizer transfer function H EQ   (i)  (z) of Equation 29 corresponds to equalizer transfer function H EQ (z) of Equation 17 with each coefficient c k,j   (i)  of Equation 29 replacing corresponding coefficient c j  of Equation 17.
 
   Coefficient update  214  can use a least mean squares (LMS) technique to continuously adjust the equalizer coefficients c k,j   (i)  such that
 
 c   k+1,j   (i)   =c   k,j   (i) −μ EQ,j   (i) sign(α k−j   (i) ) e   k   (i) .  (30)
 
The LMS technique minimizes the mean squared error, which is a function of intersymbol interference and random noise, of the input signal at slicer  213 . The parameter μ EQ,j   (i)  controls the rate at which the coefficient c k,j   (i)  changes. In some embodiments, the parameter μ EQ,j   (i)  is set to about 10 −3  on chip powerup and reduced to about 10 −5  for continuous operation.
 
   After equalization with digital equalizer  212 , digital echo canceller  621  removes the residual echo due to transmitter  606  transmitting on wire  603 - i  which is left by analog echo canceller circuit  627 . The M-1 NEXT cancellers  618 - 1  through  618 -M remove the near end crosstalk from transmitter  606  on wires  603 - 1  through  603 -M, respectively, other than wire  603 - i . In a four-wire system (M=4), there are three NEXT cancellers  618 - 1  through  618 -M except for  618 - i  and one echo canceller  621  for signals transmitted on wire  603 - i.    
   Digital echo canceller  621  cancels the residual echo not cancelled by analog echo canceller circuit  627 . The bulk of the echo cancellation is accomplished by analog echo canceller circuit  627 . Removing the residual echo by digital echo canceller  621  is necessary to achieve the bit-error rate (BER) performance of receiver  602 - i.    
   In one embodiment, echo canceller  621  uses a finite-impulse response (FIR) filter to estimate the residual echo on the channel. FIR echo canceller  621  executes a transfer function EC k   (i)  given by 
                     EC   k     (   i   )       =       ∑     j   =   0     L     ⁢           ⁢       ς     k   ,   j       (   i   )       ⁢     z     -   j             ,           (   31   )               
where L is an integer, for example, 64 or 56. Echo canceller  621  inputs the transmitted symbol stream {Tx k   (i) } and estimates the residual echo at that point in the data path, including the impulse response of the residual echo channel after analog echo canceller  627 , analog AGC  625 , analog equalizers  613  and  614 , and digital equalizer  212 .
 
   Each of the coefficients ζ k,j   (i)  in Equation 31 is chosen by an adaptation loop using a least mean squares technique such that
 
ζ k+1,j   (i) =ζ k,j   (i) −μ EC,j   (i)sign ( Tx   k−j   (i) ) e   k   (i) .  (32)
 
The coefficients ζ k,j   (i)  are continuously adjusted to maintain the minimum mean squared error at slicer  213 . The parameter μ EC,j   (i)  may initially be set high (e.g., 10 −3 ) and then lowered (e.g., 10 −5 ) for continuous operation.
 
   As mentioned above, the M-1 NEXT cancellers  618 - 1  through  618 -M in receiver  602 - i  cancel the near end crosstalk which is a result of transmitter  606  transmitting on wires  603 - 1  through  603 -M other than wire  603 - i . Note that there is no NEXT canceller ( 618 - i ) for receiver  602 - i  because the effects of transmitting symbols on wire  603 - i  are cancelled by analog echo canceller  627  and digital echo canceller  621 . Each of the M-1 NEXT cancellers  618 - 1  through  618 -M estimates the impulse response from the NEXT in an FIR block. The impulse response that is used to estimate the NEXT at this point in the data path is the impulse response of the NEXT contribution in transmission channel  601  that has been added to the receive signal filtered by analog prefilter  619  and digital equalizer  212 . Each of the M-1 NEXT cancellers  618 - 1  through  618 -M executes a transfer function NE p,k   (i)  given by 
                     NE     p   ,   k       (   i   )       =       ∑     j   =   0     L     ⁢           ⁢       ξ     p   ,   k   ,   j       (   i   )       ⁢     z     -   j             ,           (   33   )               
where p denotes a channel that is not channel i and L can be any positive integer, for example, 44 or 16.
 
   Each of the coefficients ξ p,k,j   (i)  is adaptively chosen according to a least mean squares technique such that
 
ξ p,k+1,j   (i) =ξ p,k,j   (i) +μ NE,p,j   (i)sign ( Tx   k−j   (p) ) e   k   (i) .  (34)
 
The coefficients ξ p,k,j   (i)  are continuously updated to maintain the minimum mean squared error at slicer  213 . The parameter μ NE,p,j   (i)  may initially be set high (e.g., ˜10 −3 ) and then lowered (e.g., ˜10 −5 ) for steady state operation.
 
   The echo and NEXT estimations performed by echo canceller  621  and the M-1 NEXT cancellers  618 - 1  through  618 -M are subtracted from the output signal of equalizer  212  by adder  615 . 
   Digital AGC  215  inputs a gain signal g k   (i)  to AGC booster  211  which digitally amplifies the output signal from adder  615 . The signal is boosted by AGC booster  211  to levels determined by slicer  213 . The gain g k   (i)  is set to counter the losses resulting from transmission channel  601  and not recovered in analog prefilter  619 . During acquisition, the gain g k   (i)  can be updated by the equation
 
 g   k+1   (i)   =g   k   (i) −μ AGC   (i) ( e   non,k   (i) ),  (35)
 
with error e non,k   (i)  determined from
 
 e   non,k   (i)   =|a   k ′ (i)   |−Th   AGC   (i) .  (36)
 
where Th AGC   (i)  is the average absolute value of a k ′ (i) . The parameter μ AGC   (i)  can initially be set high and then lowered during steady state operation. During steady state operation, a least mean squares approach can be taken, in which case
 
 g   k+1   (i)   =g   k   (i) −μ AGC   (i)sign ( â   k   (i) ) e   k   (i) .  (37)
 
   Finally, baseline wander correction circuit  617 , in combination with baseline wander subtracter  616 , corrects for baseline wander. A discussion of baseline wander can be found in U.S. patent application Ser. No. 09/151,525, cited above. 
   One skilled in the art will recognize that the components of receiver  506  may be arranged differently. For example, in  FIG. 6B  amplifier  211  follows equalizer  212  while in  FIG. 2A  equalizer  212  follows amplifier  211 . One skilled in the art will also recognize that receivers according to the present invention may not have some of the features shown in  FIGS. 2A ,  5 A, and  6 B or, alternatively, may have other features not shown in  FIGS. 2A ,  5 A, and  6 B.  FIGS. 2A ,  5 A, and  6 B, therefore, are not exhaustive of all configurations of receivers that are nonetheless within the scope of this disclosure. 
   The above examples, therefore, are demonstrative only. One skilled in the art can recognize variations which fall within the scope of this invention. As such, the invention is limited only by the following claims.