Abstract:
A voltage regulator with load pole stabilization is disclosed. The voltage regulator consists of an output stage, a comparator stage, and an active load. The active load draws current from the output of the voltage regulator inversely proportional to the current demand on the voltage regulator. When the output current demand is low, the active load draws relatively low current. When the output current demand is large, the active load draws a relatively large amount of current. Consequently, the disclosed voltage regulator has high stability without consuming excess power.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to electronic circuits used as voltage regulators and more specifically to circuits and methods used to stabilize a voltage regulator. 
     2. Description of the Relevant Art 
     The problem addressed by this invention is encountered in voltage regulation circuits. Voltage regulators are inherently medium to high gain circuits, typically 50 db or greater, with low bandwidth. With this high gain and low bandwidth, stability is often achieved by setting a dominate pole with the load capacitor. Achieving stability over a wide range of load currents with a low value load capacitor (˜0.1 uF) is difficult because the load pole formed by the load capacitor and load resistor can vary by more than three decades of frequency and be as high as tens of KHz requiring the circuit to have a very broad band of greater than 3 MHz which is incompatible with the power process used for voltage regulators. 
     FIG. 1 shows a prior art solution to the stabilization problem. The voltage regulator 24 in FIG. 1 converts an unregulated Vdd voltage, 12 volts in this example, into a regulated voltage at node 26, 5 volts in this example. Capacitor 8, resistor 10, amplifier 12, and resistor 14 are configured as an integrator having the output voltage node 26 as an inverting input and a voltage reference as the non-inverting input. The integrator drives bipolar transistor 4 which is connected in series with an output current mirror formed by p-channel transistors 2 and 16, as is known in the art. Resistor 18 is a pull down resistor added to increase the stability of the circuit. 
     In this prior art example, the pole associated with the pull down resistor can be calculated as: 
     
         f=1/2πR.sub.L C.sub.L 
    
     where 
     R L  =resistance of the load=R18 in parallel with R20 and 
     C L  =is typically around 0.1 microfarad 
     Therefore, the pole associated with the prior art circuit is load dependent and can vary from 16 Hz to 32 KHz for an R18 equal to 100 kilo-ohms and R20 ranging from 50 ohms to 1 mega-ohm. The wide variation of the pole frequency is difficult to stabilize, as will be appreciated by persons skilled in the art. A prior art solution to this problem is to change the pull down resistor R18 from 500 kilo-ohms to around 500 ohms which changes the pole frequency to a range of 3.2 KHz to 32 KHz, which is a frequency spread of 1 decade instead of 3 decades. However, the power dissipated by the output transistor 16 increases, as shown below: 
     
         power=(12 v-5 v)(I.sub.load +I.sub.pull down)=(7 v)(100 mA)+(7 v)(10 mA) 
    
     Therefore, the 500 ohm resistor adds 70 milli-watts of power dissipation in the chip which is approximately a 10% increase in power dissipation for the added stability. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the invention to increase the stability of a voltage regulator without increasing the power dissipated in the circuit. Additionally, it is an object of the invention to have an active pull down resistor which decreases resistance when necessary to maintain stability and increases resistance to decrease power consumption. These and other objects, features, and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read with the drawings and appended claims. 
     The invention can be summarized as a voltage regulator with load pole stabilization. The voltage regulator consists of an output stage, a comparator stage, and an active load. The active load draws current from the output of the voltage regulator inversely proportional to the current demand on the voltage regulator. When the output current demand is large, the active load draws relatively low current. When the output current demand is low the active load draws a relatively large amount of current. Consequently, the disclosed voltage regulator has high stability without consuming excess power. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic diagram of a voltage regulator with a pull down resistor as is known in the prior art. 
     FIG. 2 is a schematic diagram of a voltage regulator with an active load. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A voltage regulator constructed according to the preferred embodiment of the invention in FIG. 2 will be described. The voltage regulator 60 comprises a comparator stage 62, an output stage 64, and an active load 66. 
     The comparator stage 62 is constructed by connecting a base of a NPN transistor to a first plate of capacitor 44 and to an output of an operational amplifier 46. The emitter of transistor 40 is connected an emitter of a NPN transistor 36 and to a draining end of a current source 42. The sourcing end of the current source is connected to a voltage reference, ground. The base of transistor 36 is connected to a bias voltage which is not shown. The second plate of capacitor 44 is connected to a first end of resistor 45. The second end of resistor 45 is connected to an inverting input of amplifier 46 and to the first end of resistor 48. The non-inverting input is connected to a reference voltage, which is this example is 5 volts. The regulator will track the reference voltage, as is understood in the art. 
     The output stage is constructed by connecting a drain and a gate of P-channel transistor 38 and a gate of a P-channel transistor 50 to the collector of transistor 40. This connection comprises the output of the comparator stage and the input of the output stage. The sources of transistors 38 and 50 are connected to a Vdd, which in this example is 12 volts. The drain of transistor 50 is connected to the second end of resistor 48 and to a drain of N-channel transistor 54. This connection forms the output of the output stage, the output of the voltage regulator, and the input of the comparator stage. 
     The active load 66 is constructed by connecting the collector of transistor 36 to the drain and the gate of a P-channel transistor 34 transistor and to the gate of a P-channel transistor 30. The sources of transistors 30 and 34 are connected Vdd. The drain of transistor 30 is connected to the drain and gate of N-channel transistor 32 and to the gate of an N-channel transistor 54. The sources of transistors 32 and 54 are connected to ground. 
     The load which is not part of the invention is shown as a resistor 56 connected in parallel with a capacitor 58. 
     In operation, the current mirror created by transistor 38 being connected to transistor 50 comprise the output stage. The output stage drives current onto node 52 responsive to a comparator stage. The current flowing through transistor 50 is proportional to the current flowing through transistor 38 where the proportion is determined by the relative areas of the transistors as is known in the art. The resulting voltage on node 52 is sensed through resistor 48 and compared to the voltage reference on the non-inverting input of amplifier 46. The integrator formed by capacitor 44 and resistor 45 create the dominate pole and has a zero that cancels the load pole. The output of amplifier 46 drives transistor 40 which drives the current through the current mirror of the output stage. The current through transistor 40 is limited by the current source 42. 
     Transistor 36, transistor 40 and current source 42 are configured as a differential pair. Therefore, the current through transistors 36 and 40 equals the current of current source 42. As the current demand on the output stage increases, current through transistor 40 increases and current through transistor 36 decreases by a proportional amount. Conversely, as the current through transistor 40 decreases, the current through transistor 36 increases by a proportional amount. 
     The current through transistor 36 is mirrored through the current mirror created by transistors 30 and 34. The current through transistor 30 is mirrored by the current mirror created by transistor 32 and transistor 54. Consequently, the active load 66 current increases as the current through output stage 64 decreases; conversely, if the current through the output stage 64 increases, the current through the active load 54 decreases. 
     The operation of the circuit can be described quantitatively by the equations listed below: 
     
         I.sub.36 +I.sub.40 =I.sub.42                               1) 
    
     
         I.sub.54 =nI.sub.36                                        2) 
    
     where, ##EQU1## 
     
         I.sub.50 =mI.sub.40                                        3) 
    
     where, ##EQU2## 4) ##EQU3## 5) For I LOAD  =0 I 54  =nI 42  so, 
     the resistance of transistor 54 is effectively: ##EQU4## 6) So at maximum output current, I LOAD  =mI 42  and I 54  =0 
     Thus, R EFF  =infinity 
     Additionally, the load poles are calculated as follows: since, ##EQU5## where R=R EFF  and C=C 22  7) ##EQU6## 8) ##EQU7## 9) Load pole variation is ratio of R for I L  =0; I L  =I max  ##EQU8## for n=m Fixed load pole 
     10 n=m Load pole varies˜1 decade frequency 
     The power dissipation in transistor 16 can be calculated as follows: 
     10) ##EQU9## P=(V -V   0 )(I m1 ) (where (V +  -V 0 )=V DS ) P ∝I m1  for fixed supply 
     
         ______________________________________P = (V.sup.+ - V.sub.0)(I.sub.ml) (where (V.sup.+ - V.sub.0) = V.sub.DS)P α I.sub.ml for fixed supplyI.sub.LOAD I.sub.50     P.sub.50______________________________________0          nI.sub.42    V.sub.16(DS) nI.sub.42.1I.sub.max = .1mI.sub.42      .1mI.sub.42 + .9nI.sub.42                   V.sub.16(DS) nI.sub.42.2I.sub.max = .2mI.sub.42      .2mI.sub.42 + .8nI.sub.42                   V.sub.16(DS) nI.sub.42.5I.sub.max = .5mI.sub.42      .5mI.sub.42 + .5nI.sub.42                   (.5mI.sub.42 + .5nI.sub.42)V.sub.(16)DSI.sub.max = mI.sub.42      mI.sub.42    (mI.sub.T)V.sub.16(DS)______________________________________ I.sub.50 = I.sub.LOAD + I.sub.54 Note: As L increases the current in transistor 50 decreases as does its contribution to power dissipation. 
    
     
         I.sub.50 =I.sub.LOAD +I.sub.54 
    
     Note: As I L  increases the current in transistor 50 decreases as does its contribution to power dissipation. 
     By using an active load, the voltage regulator 60 provides the advantage of increasing the stability of voltage regulator 60 without increasing the power dissipated in the circuit. Additionally, voltage regulator 60 has an active pull down resistor which decreases in resistance when necessary to maintain stability and increases resistance to decrease power consumption when the extra load is not needed for stability. 
     Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.