Abstract:
A dynamic random access memory structure. The structure includes a substrate having protruding sections and recessed sections, in which the protruding sections have sidewalls and a substrate surface is located between the protruding sections and the recessed sections. A gate oxide layer is formed on the sidewalls of the protruding sections and on the surfaces between the protruding sections and the recessed sections. A doped region is formed near the bottom of each protruding section, and these doped regions serve as buried bit lines. A channel region is formed in the protruding section and a gate electrode is formed on each side of the channel region. A storage electrode is connected to the other end of the protruding section and a word line is connected to the gate electrode. The word line and the buried bit line are perpendicular to each other.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a dynamic random access memory (DRAM) structure. More particularly, the present invention relates to a vertical DRAM structure. 
     2. Description of the Related Art 
     As the level of integration of semiconductor devices increases, dimensions of circuit devices must be reduced according to design rules. Theoretically, line width of gates can be reduced ad infinitum. In practice, however, line width is limited by the resolution in photolithographic operations as well as length of device channel. Since a source/drain region is formed using the gate line as an ion mask in an ion implantation, line width of the gate is almost equivalent to length of the channel. Although the reduction of channel length is able to increase drifting speed of carriers from one source/drain terminal to the next, the hot carrier effect will intensify resulting in a higher rate of device failure. Hence, an upper limit is set on the possible level of integration for conventional DRAM devices. 
     SUMMARY OF THE INVENTION 
     This invention also provides a dynamic random access memory structure. The structure includes a substrate having protruding sections and recessed sections, in which the protruding sections have sidewalls and a substrate surface is located between the protruding sections and the recessed sections. A gate oxide layer is formed on the sidewalls of the protruding sections and on the surfaces between the protruding sections and the recessed sections. A doped region is formed near the bottom of each protruding section, and these doped regions serve as buried bit lines. A channel region is formed in the protruding section and a gate electrode is formed on each side of the channel region. A storage electrode is connected to the other end of the protruding section and a word line is connected to the gate electrode. The word line and the buried bit line are perpendicular to each other. The aforementioned structure further includes a shallow trench isolation structure in the recessed section of the substrate. 
     Accordingly, the present invention is to provide a dynamic random access memory (DRAM) structure capable of increasing the level of integration for DRAM devices. In addition, the invention also provides a DRAM structure capable of packing more devices onto a piece of silicon chip so that the level of device integration is increased. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIGS. 1A through 1I are schematic, cross-sectional views showing the progression of steps for manufacturing flash memory according to one preferred embodiment of the invention; 
     FIG. 2 is a top view of FIG. 1G; 
     FIG. 3 is a top view of FIG. 1H after the landing pads of word lines are formed; 
     FIG. 4 is a top view of FIG. 1H after the word lines are formed; and 
     FIG. 5 is a top view of FIG. 1I after the storage electrodes are formed. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     FIGS. 1A through 1I are schematic, cross-sectional views showing the progression of steps for manufacturing flash memory according to one preferred embodiment of the invention. 
     As shown in FIG. 1A, a substrate  100  such as a semiconductor silicon substrate is provided. A pad oxide layer  102  and a mask layer  104  are sequentially formed over the substrate  100 . The pad oxide layer  102  can be formed by, for example, thermal oxidation. The mask layer  104  can be a silicon nitride layer formed by, for example, chemical vapor deposition. 
     As shown in FIG. 1B, the mask layer  104  is patterned to form a patterned mask layer  104   a . Using the patterned mask layer  104   a  as an etching mask, the pad oxide layer  102  and the substrate  100  are sequentially etched to form openings  106  in the substrate  100 . The pad oxide layer  102  becomes a pad oxide layer  102   a  and the desired regions for forming DRAM cells are patterned out. Regions outside the openings  106  become protruding sections  120 . Since depth of the opening  106  is related to the length of device channel, depth of the opening  106  is determined entirely by the length of channel desired. A liner oxide layer  108  is formed over the exposed substrate  100  inside the openings  106 . The liner oxide layer  108  can be formed by, for example, thermal oxidation. Using the patterned mask layer  104   a  as an ion mask, dopants are implanted into the substrate  100  at the bottom of the openings  106  to form a plurality of doped regions  110 . 
     As shown in FIG. 1C, spacers  112  are formed over the liner oxide layer  108  on the sidewalls of the openings  106 . The spacers  112  are preferably silicon nitride layers formed by depositing a conformal silicon nitride layer over the substrate  100  and then performing an anisotropic etching of the silicon nitride layer. 
     FIGS. 1D and 1E illustrate the steps for forming shallow trench isolation structures. As shown in FIG. 1D, using the patterned mask layer  104   a  and spacers  112  as an etching mask, the exposed substrate  100  at the bottom of the openings  106  is etched. The liner oxide layer  108  becomes a liner oxide layer  108   a  and a trench  114  is formed further down each opening  106 . Each trench  114  is also defined as a recessed section in this invention. There is a substrate surface between the protruding section  120  and the recessed section. This substrate surface is under the spacers  112 . The trenches  114  also have a depth much greater than the thickness of the doped layer  110  so that each doped region  110  is divided into two separate doped regions  110   a . Since the dimensions of each trench  114  are determined by the spacers  112  within the opening  106  instead of by a photolithographic process, area occupation of the shallow trench isolation can be reduced without affecting the degree of electrical isolation between devices. 
     As shown in FIG. 1E, a liner oxide layer  116  is formed over the exposed substrate surface within the trenches  114 . The liner oxide layer  116  forms a continuous layer with the liner oxide layer  108   a  near the upper corners of the trench  114 . The liner oxide layer  116  can be formed by, for example, thermal oxidation. An insulation layer  118  is formed inside each trench  114 , thereby forming a shallow trench isolation (STI) structure. The STI structures are roughly parallel to the doped regions  110   a . The insulation layer can be a silicon oxide layer formed by, for example, depositing oxide material into the openings  106  and the trenches  114 , and then etching back the oxide layer so that only the trenches  114  are filled. To increase electrical insulation, a high-temperature annealing operation is carried out to densify the insulation layer  118 . The densified insulation layer  118  and the liner oxide layer  116  together function as an STI structure. 
     Both the formation of the liner oxide layer  116  and the densification of the insulation layer  118  are conducted at an elevated temperature. At a high temperature, dopants in two independent regions  110   a  bounded within two neighboring STI structures can diffuse towards each other, thereby forming a linked doped region  110   b . The doped regions  110   b  form buried bit lines. Consequently, the protruding sections  120  are separated from the substrate  100  below to become isolated protruding sections  120   a . The protruding sections  120   a  are later transformed into channel regions. 
     As shown in FIG. 1F, the spacers  112 , the patterned mask layer  104   a , the pad oxide layer  102   a  and the liner oxide layer  108   a  are removed. The spacers  112  and the patterned mask layer  104   a  can be removed by, for example, wet etching. For example, the spacers  112  and the patterned mask layer  104   a  are silicon nitride layers, hot phosphoric acid (H 3 PO 4 ) solution can be used. The pad oxide layer  102   a  and the liner oxide layer  108   a  can be removed by, for example, wet etching using hydrofluoric acid (HF) solution. 
     As shown in FIG. 1G, a gate oxide layer  122  is formed over the substrate  100  and in the openings  106 . The gate oxide layer  122  can be formed by, for example, thermal oxidation. A conductive layer  124  is formed inside each opening  106 . The conductive layer  124  can be a doped polysilicon layer formed by, for example depositing conductive material over the substrate  100  followed by etching back. In this manner, the conductive layer  124  and the neighboring conductive layer  124  are separated by the opening  106 . FIG. 2 is a top view of FIG.  1 G. The conductive layer  124  inside each opening  106  will eventually become a gate electrode. 
     As shown in FIG. 1H, the conductive layer  124 , the gate oxide layer  122  and the protruding sections  120   a  are patterned to form a conductive layer  124   a , a gate oxide layer  122   a  and channel regions  120   b . FIG. 3 is a top view of FIG. 1H after the landing pads of word lines are formed. As shown in FIG. 3, the conductive layer  124   a  is the landing pad of a word line as well as a gate electrode. 
     A stop layer  126  is formed over the conductive layer  124   a . The stop layer  126  can be a silicon nitride layer formed by, for example, nitriding the conductive layer  124   a  such as a doped polysilicon layer. An insulation layer  128  is formed over the stop layer  126 . The insulation layer  128  can be a silicon oxide layer. Contact openings  130  are formed in the insulation layer  128  and the stop layer  126 . Word lines  132  are formed over the insulation layer  128 . The word lines  132  are electrically connected to the respective landing pads  124   a  through a contact formed within the opening  130 . The word lines  132  can be formed from a material such as aluminum, aluminum-copper alloy or copper. The word lines  132  runs in a direction roughly perpendicular to the doped regions  110   b . FIG. 4 is a top view of FIG. 1H after the word lines  132  are formed. 
     As shown in FIG. 1I, an insulation layer  134  is formed over the word lines  132 . A node contact opening  136  is formed through the insulation layers  134  and  128 . The insulation layer  134  can be a silicon oxide layer. Storage electrodes  138  are formed over the insulation layer  134 . The storage electrodes  138  are electrically connected to the respective channel regions  120   a  through the node contact openings  136 . The storage electrodes  138  can be formed using, for example, doped polysilicon. FIG. 5 is a top view of FIG. 1I after the storage electrodes  138  are formed. In FIG. 1I, the word lines  132  and the storage electrodes  138  are drawn in the same cross-section. In reality, the word lines  132  and the storage electrodes  138  are separate and independent. 
     In the subsequent operation, steps for forming capacitors and interconnects are carried out. Since these steps are not directly related to this invention, detailed descriptions are omitted here. 
     The DRAM formed according to method of this invention works in a manner similar to a conventional DRAM. The only difference is that each DRAM cell in this invention is simultaneously controlled by the gate electrodes  124   a  on each side of the channel region  120   b . Consequently, data accessing and reading is faster. 
     In summary, the advantages of this invention include: 
     1. Only current semiconductor manufacturing techniques are used. Moreover, the DRAM structure of this invention is formed in a vertical direction, and hence the level of integration can be increased. 
     2. Steps for forming the DRAM structure are simple. In addition, self-aligned processes are often used. flence, the number of photomasks required is greatly reduced and cost of production is lowered. 
     3. The DRAM cell of this invention is simultaneously controlled by the gate electrodes on each side of the channel region. Therefore, reading and data accessing can be faster. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.