Abstract:
A device having two or more programmable logic devices within an assembly apparatus. A first programmable logic device may be configured to have (i) a first signal interface and (ii) a second signal interface. A second programmable logic device may be configured to have (i) a third signal interface and (ii) a fourth signal interface. The assembly apparatus is generally configured to (i) mount the first programmable logic device and (ii) mount the second programmable logic device. A first external contact may be connected to the first signal interface. A second external contact may be connected to the fourth signal interface. A direct connection may be provided between the second signal interface and the third signal interface.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method and/or architecture for a package integrating multiple chips generally and, more particularly, to a package having multiple programmable logic devices interconnected with each other. 
     BACKGROUND OF THE INVENTION 
     A design cycle for a newer and larger complex programmable logic device (CPLD) can require several months to complete. Considerable resources must be spent in design, simulations, and test cycles for the new CPLD prior to producing a working prototype in silicon. After the working prototypes are available, additional resources can be expended for additional testing. 
     While the new CPLD is being developed, customers must use multiple existing CPLD devices to meet design requirements for a number of gates greater than in an individual CPLD device. Using multiple CPLD devices requires additional time and effort to segregate functionality among the CPLD devices, program the individual CPLD devices, and assemble the individual CPLD devices onto the boards. Multiple CPLD devices can consume greater power and require more board space that a single CPLD device. 
     SUMMARY OF THE INVENTION 
     The present invention concerns a device having two or more programmable logic devices within an assembly apparatus. A first programmable logic device may be configured to have (i) a first signal interface and (ii) a second signal interface. A second programmable logic device may be configured to have (i) a third signal interface and (ii) a fourth signal interface. The assembly apparatus is generally configured to (i) mount the first programmable logic device and (ii) mount the second programmable logic device. A first external contact may be connected to the first signal interface. A second external contact may be connected to the fourth signal interface. A direct connection may be provided between the second signal interface and the third signal interface. 
     The objects, features and advantages of the present invention include providing a package having multiple programmable logic devices that may provide for (i) a high gate density, (ii) inter-PLD communications within the package, and/or (iii) external access to the inter-PLD communications. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a block diagram of a device having two PLDs; 
     FIG. 2 is a block diagram of another device having multiple die; 
     FIG. 3 is a flow diagram of a method of fabricating the device; 
     FIG. 4 is a block diagram of a first embodiment of the present invention; 
     FIG. 5 is a detailed block diagram of a portion of a CPLD of FIG. 4; 
     FIG. 6 is a block diagram of a second embodiment of the present invention; and 
     FIG. 7 is a detailed block diagram of a portion of a CPLD of FIG.  6 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a block diagram of a device  100  is shown in accordance with a preferred embodiment of the present invention. The device  100  generally comprises an assembly apparatus (or assembly)  102 , a die (or chip)  104 , another die (or chip)  106 , and multiple external contacts  108 A-B. The assembly  102  may include multiple traces  110 A-B that route signals, power, ground, clocks, and the like among the die  104 , the die  106  and the external contacts  108 A-B. The assembly  102  may also include one or more traces  112  that route signals between the die  104  and the die  106 . In one embodiment, the traces  112  may be wire-bond wires, ribbons, beams, or equivalent that may form direct connections among the die  104 , the die  106 , and the external contacts  108 A-B. 
     The die  104  may have multiple interfaces  114  for exchanging signals, power, grounds, clocks, and the like with the external contacts  108 A. The interfaces  114  may be wire-bonded to pads (not shown) at the end of the traces  110 A adjacent to the die  104 . The die  104  may have one or more interfaces  116  for exchanging signals with the die  106 . The signal interfaces  116  may be wire-bonded to pads (not shown) at the end of the traces  112  adjacent to the die  104 . 
     The die  106  may have multiple interfaces  118  for exchanging signals, power, ground, clocks, and the like with the external contacts  108 B. The interfaces  118  may be wire-bonded to pads (not shown) at the end of the traces  110 B adjacent to the die  106 . The die  106  may have one or more interfaces  120  for exchanging signals with the die  104 . The signal interface  120  may be wire-bonded to pads (not shown) at the end of the traces  112  adjacent to the die  106 . In one embodiment, the signal interfaces  116  may be wire-bonded directly to the signal interfaces  120  independently of the assembly  102 . 
     In one embodiment, the die  104  and the die  106  may be oriented so that the signal interfaces  116  and the signal interfaces  120  are on sides facing each other. In another embodiment, the signal interfaces  116  and the signal interfaces  120  may be on non-facing sides of the die  104  and the die  106 . In still another embodiment, the signal interfaces  116  and the signal interfaces  120  may be distributed among facing and non-facing sides of the die  104  and the die  106 . 
     The assembly  102  may have multiple layers that may allow traces to cross. In particular, the assembly  102  may include one or more traces  122 . Each trace  122  may connect a trace  112  to an external contact  108 . Each trace  122  may allow inter-die signals to be shared with the external contacts  108 . In one embodiment, a signal interface  116  and a signal interface  120  may be wired bonded directly to an external contact  108  thus forming a three-node connection. 
     The assembly  102  may include one or more traces  110 C along the same side of the die  104  as the signal interfaces  116 . The assembly  102  may also include one or more traces  110 D along the same side of the die  106  as the signal interfaces  120 . The traces  110 C-D may be used to provide additional external connections in applications where there are more than sufficient signal interfaces  116  and/or signal interfaces  120  to meet an inter-die communication requirement for the device  100 . 
     The assembly  102  may be implemented having a single conductive layer or multiple-conductive layers. The assembly  102  may be a substrate, a carrier, a lead frame, a housing, a base, or other equivalent structure. The die  104  may be implemented as a programmable logic device (PLD) or a complex programmable logic device (CPLD). The die  106  may be implemented as another PLD or CPLD. The die  104  and the die  106  may be similar to each other or different types and/or sizes of PLD/CPLDs. The external contacts  108  may be implemented as pins, balls, land grid, bumps, leads, solder joint pads, or the like. 
     Referring to FIG. 2, a block diagram of a device  100 A implementing an alternative embodiment is shown. The device  100 A generally includes an assembly  102 A, a die  104 A, a die  106 A, a die  107 A, and multiple external contacts  108 A-C. The assembly  102 A may include the traces  110 A-B,  110 E and the traces  112 . The traces  110 A-C and  110 E may route between the external contacts  108  and the die  104 A, the die  106 A, and the die  107 A. The assembly  102 A may include one or more additional inter-die traces  112 A between the die  106 A and the die  107 A. In one embodiment, additional traces  109  may be included within the assembly  102 A to route signals between the die  104 A and the die  107 A to meet the design criteria of a particular implementation. Generally, one or more additional dies may be mounted on the assembly  102 A along with the die  104 A and the die  106 B. 
     The die  104 A may include the interfaces  114  to exchange signals, power, ground, clocks, and the like with the external contacts  108 A. The die  104 A may include the signal interfaces  116  to exchange signals with the die  106 A. The die  106 A may include the interfaces  118  to exchange signal, power, ground, clocks, and the like with the external contacts  108 B. Thedie  106 A may include the signal interfaces  120  to exchange signals with the die  104 A. The die  106 A may also include one or more interfaces  124  to exchange signals with the die  107 A. 
     The die  107 A may include multiple interfaces  126  to exchange signals, power, ground, clocks, and the like with the external contacts  108 C. The interfaces  126  may be wire-bonded to pads (not shown) at the ends of the traces  110 E adjacent to the die  107 A. The die  107 A may have one or more interfaces  128  to exchange signals with the die  106 A. The signal interfaces  128  may be wire-bonded to the pads (not shown) at the ends of the traces  112 A adjacent to the die  107 A. In one embodiment, the traces  112 A may be wire-bond wires, ribbon, beams, or equivalent connected directly between the die  106 A and the die  107 A. Likewise, the traces  110 E between the die  107 A and the external contacts  108 C may be implemented independently of the assembly  102 A. 
     The die  107 A may be implemented as another PLD or CPLD. The die  107 A may be similar to the die  104 A, similar to the die  106 A, or a different type and/or size of PLD/CPLD. In other embodiments, the die  107 A may be a bus interface chip, a memory, a processor, an analog to digital converter, a digital to analog converter, field programmable gate array, application specific integrated circuit, digital signal processor, or any other device compatible with the interfaces  124 . 
     Referring to FIG,  3 , a flow diagram of a process of assembling the device  100  is shown. The process may begin by orienting and mounting the die (chips)  104  and  106  to the assembly  102  (e.g., block  130 ). Once the die  104  and  106  are mounted, the die  104  and  106  may be connected to each other (e.g., block  132 ). As mentioned earlier, inter-connecting the die may be accomplished by wire bonding to traces  112  in the assembly  102  and/or wiring directly from pad to pad between the die  104  and  106 . The die  104  and  106  may also be connected to the external contacts  108 A-D (e.g. block  134 ). Connections to the external contacts  108 A-B tnay be made by wire-bonding to traces  110 A-D in thlo assembly  102  and/or wiring directly between the die pads and the external contacts  108 A-B. The sequence of connecting the die  104  and  106  to the external contacts  108 A-B and to each other may be performed in any order. After all of the connections have been made, a lid may be attached to the assembly to protect the dies  104  and  106  and wire-bonds (e.g., block  136 ). 
     Referring to FIG. 4, a block diagram of a device  100 B illustrating an example implementation is shown. The device  100 B may be implemented using CPLDs of the Ultra37000™ family of CPLDs. available from Cypress Semiconductor of San Jose, Calif. The device  100 B generally comprises an assembly  102 B, a first CPLD  104 B, and a second CPLD  106 B. The CPLD  104 B and the CPLD  106 B are shown as similar parts. In other embodiments, the CPLD  104 B may be a different part than the CPLD  106 B. 
     Each CPLD  104 B and  106 B generally comprises multiple buffers  138 A-B, multiple logic blocks (LB)  140 A-B, and a programmable interconnect matrix (PIM)  142 A-B. The CPLD  104 B may have multiple interfaces  114 B connected to the external contacts  108 D. The CPLD  104 B may have multiple signal interfaces  116 B connected to the CPLD  106 B. The PIM  142 A of the CPLD  104 B may have an interface  144 A that may receive the signals present at the interfaces  114 B and the signal interfaces  116 B. 
     The CPLD  106 B may have multiple interfaces  118 B connected to the external contacts  108 E. The CPLD  106 B may have multiple signal interfaces  120 B connected to the signal interfaces  116 B of the CPLD  104 B. The PIM  142 B of the CPLD  106 B may have the interface  144 B that may receive the signals present at the interfaces  118 B and the signal interfaces  120 B. 
     The interfaces  114 B,  116 B,  118 B and  120 B as shown in FIG. 4 may represent several interfaces  114 ,  116 ,  118  and  120  as shown in FIG.  1  and FIG.  2 . Consequently, each buffer  138 A-B shown in FIG. 4 may represent several buffers, one for each individual signal or bit of the signal presented by a logic block  140 A-B. Likewise, each external contact  108 D-E as shown in FIG. 4 may represent several external contacts  108 A-B as shown in FIG.  1  and FIG. 2 to accommodate the multiple-bit signals. 
     The CPLD  104 B may communicate with the CPLD  106 B by generating a signal in a sending logic block  140 A. The signal may then be presented at a signal interface  116 B by a buffer  138 A associated with the sending logic block  140 A. The CPLD  106 B may receive the signal at a signal interface  120 B connected to the signal interface  116 B. The signal may then be routed to interface  144 B of the PIM  142  of the CPLD  106 B. The PIM  142 B may route the signal to a receiving logic block  140 B in the CPLD  106 B. The same basic process may be used to send a signal from the CPLD  106 B to the CPLD  104 B. 
     Referring to FIG. 5, a detailed block diagram of a portion of a logic block  140  is shown. Each logic block  140  may include a macrocell  146  and an input/output (I/O) cell  148 . The macrocell  146  may be connected to the I/O cell  148  to present a single-bit or multiple-bit signal. The I/O cell  148  may be connected to the buffer  138 . The buffer  138  may be connected to an interface  149  to present the signal. The interface  149  may represent the interfaces  114 B,  116 B,  118 B and  120 B. 
     Programming of inter-die communications between the CPLD  104 B and the CPLD  106 B may be flexible due to the PIMs  142 . Each logic block  140  directly associated with a signal interface  116 B or  120 B may present a signal to the PIM  142  of the other CPLD. The PIM  142  receiving the signal may route the signal to any of the logic blocks  140  within the same CPLD. Thus, several logic blocks  140  of a CPLD may send signals to any of the logic blocks  140  of the other CPLD. 
     Referring to FIG. 6, a block diagram of a device  100 C illustrating another example implementation is shown. The device  100 C may be implemented using CPLDs of the Delta39K™ family of CPLDs available from Cypress Semiconductor of San Jose, Calif. The device  100 C generally comprises an assembly  102 C, a first CPLD  104 C, and a second CPLD  106 C. The CPLD  104 C and the CPLD  106 C are shown as similar parts. In other embodiments, the CPLD  104 C may be a different part than the CPLD  106 C. 
     Each CPLD  104 C and  106 C generally comprises multiple clusters (CL)  150 , multiple channels  152 A-B, and multiple I/O banks  154 . The CPLD  104 C may have multiple interfaces  114 C connected to the external contacts  108 F. The CPLD  104 C may have multiple signal interfaces  116 C connected to the CPLD  106 C. One or more of the signal interfaces  116 C may also be Connected to the external contacts  108 G. 
     The CPLD  106 C may have multiple interfaces  118 C connected to the external contacts  108 H. The CPLD  106 C may have multiple signal interfaces  120 C connected to the signal interfaces  116 C of the CPLD  104 C. One or more of thegnal interfaces  120 C may also be connected to the external contacts  108 G. 
     The interfaces  114 C,  116 C,  118 C and  120 C as shown in FIG. 6 may represent several interfaces  114 ,  116 ,  118  and  120  as shown in FIG.  1  and FIG.  2 . As a result, each external contact  108 C as shown in FIG. 6 may represent several external contacts  108  as shown in FIG.  1  and FIG. 2 to accommodate multiple-bit signals. 
     The CPLD  104 C may communicate with the CPLD  106 C by generating a signal in a cluster  150 . The signal may be programmably routed through the channels  152  to an I/O bank  154 . The I/O bank  154  may present the signal to another I/O bank  154  within the CPLD  106 C. The I/O bank  154  of the CPLD  106 C may programmably route the signal to any cluster  150  of the CPLD  106 C. 
     The same basic process may be used to send a signal from the CPLD  106 C to the CPLD  104 C. 
     Referring to FIG. 7, a detailed block diagram of a cluster  150  and an I/O bank  154  is shown. Each cluster  150  generally comprises several logic blocks  140  (only one is shown for clarity) and a PIM  142 . As before, each logic block  140  may include several macrocells  146  (only one shown for clarity). Each I/O bank  154  generally comprises several I/O cells  156  (only one is shown for clarity). A multiple-bit interface  158  may connect an I/O cell  156  externally to the CPLD. The interfaces  158  may represent the interfaces  114 C,  116 C,  118 C and  120 C. The channels  152  may programmably interconnect the PIM  142  with the I/O cell  156 . The PIM  142  and the I/O cells  156  may exchange signals in either direction thus allowing the macrocell  146  to send and receive to and from the interface  158 . 
     The channels  152  may provide for very flexible inter-die communications between the CPLD  104 C and the CPLD  106 C. The channels  152  may be programmed so that any macrocell  146  in any logic block  140  in any cluster  150  may be connected with any I/O cell  156  in any I/O bank  154 . As a result, any macrocell  146  in the CPLD  104 C may communicate with any other macrocell  146  in the CPLD  106 C using any signal interfaces  116 C and  120 C. 
     The I/O cells  156  may contribute to the flexibility of the inter-die communications between the CPLD  104 C and the CPLD  106 C. The I/O cells  156  may be capable of programmably enabling/disabling individual lines of the interface  158 . Furthermore, the I/O cells  156  may be capable of programmably defining the direction (input or output) of the individual lines of the interface  158 . As a result, each multiple-bit interface  158  may convey several signals simultaneously on different lines. The various signals may also be routed in different directions simultaneously with some being received by the I/O cell  156  and some being presented by the I/o cell  156 . 
     The various signals of the present invention may be implemented as single-bit or multi-bit signals in a serial and/or parallel configuration. As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.