Abstract:
A method for optimizing voltage and frequency for pipelined architectures that offers better power efficiency. The invention provides methods for low-power high-throughput hardware implementations to stream computations by partitioning a computation into temporally distinct stages, assigning a clock frequency to each stage such that an overall computational throughput is met and assigning to each stage a supply voltage according to its respective clock frequency and circuit parameters.

Description:
BACKGROUND  
       [0001]     The invention relates generally to the field of pipelined hardware architecture. More specifically, embodiments of the invention relate to systems and methods for implementing power efficient hardware solutions for streaming computations.  
         [0002]     Low power consumption and high performance are important requirements for any signal processing hardware design. Mobile multimedia systems are becoming popular consumer items, but limited battery life continues to be a problem. Energy efficiency must be balanced against the fact that users demand a high quality of service. With the ever increasing number of battery-operated devices, the need for minimizing power consumption without compromising performance is essential.  
         [0003]     The practice of using data pipelines for streaming computations leads to high performance. Pipelining breaks up a complex operation performed on a stream of data into smaller sequential stages or subprocesses where the output of one subprocess feeds into the next. When implemented properly, multiple operations can be performed concurrently even if one step normally would depend on the result of the preceding step before it can start. Pipelining improves performance by reducing the idle time or latency of each piece of hardware. Conversely, the pipelined stages must be designed to make the pipeline balanced, so that the different stages take approximately the same time to complete. With each clock cycle, new data is input to one end of the pipeline and a completed result will be output from the other end.  
         [0004]     Pipelining enables the realization of high-speed, high-efficiency complementary metal oxide semiconductor (CMOS) data paths by allowing for the reduction of supply voltages to the lowest possible levels while still satisfying throughput constraints. In deep pipelines, however, registers and corresponding clock trees are responsible for an increasingly large fraction of total dissipation, no matter how efficiently they may have been implemented.  
         [0005]     One application that naturally lends itself to pipelining is video processing, a key component of streaming multimedia communications and an integral part of next-generation portable devices. Currently, there are several video standards established for different purposes such as MPEG, JPEG 2000 and others, and their implementations for mobile systems-on-a-chip (SoCs) provide substantial computing capabilities at low energy consumption levels. The requirements of these standards incorporate demanding computations that include the discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT), the discrete wavelet transform (DWT) and inverse discrete wavelet transform (IDWT), motion estimation, motion compensation, variable-length coding/decoding, quantization and inverse quantization. JPEG 2000 is a recently developed standard for digital image processing and individually compresses each frame in a moving picture. Implementations of JPEG 2000 may be used in applications ranging from battery-operated cameras where low-power consumption is desirable, to digital cinema which requires real-time decompression of high-resolution images.  
         [0006]     Streaming computations are numeric operations in which data flow is unidirectional and uninterrupted from a primary input or inputs, to a primary output or outputs. During computation, however, the data flow can experience transformations where the amount of data being processed changes. Data can increase progressively as it is processed through a plurality of stages due to external inputs or internal generation due in part to signal processing techniques like the Nyquist criteria. Most current implementations are synchronous, using a global clock to pace all operations of a system or device where all components of the system operate once per clock cycle. However, using a global clock reduces efficiency.  
         [0007]     To illustrate the association of power and frequency, the delay of a logic gate T d  is given by  
                 T   d     =         C   L     ⁢     xV   dd         μ   ⁢           ⁢       C   ox     ⁡     (     W   /   L     )       ⁢       (       V   dd     -     V   th       )     2           ,           (   1   )             
 
         [0008]     where C L  is the load capacitance, V dd  the supply voltage, V th  the device threshold voltage, W and L the width and length of the transistor channels, C ox  the oxide capacitance and μ the mobility. CMOS transistors have a source-drain channel formed only when their gate voltage is larger than V th . If the source-drain voltage V dd  is greater than the gate voltage, the transistor operates in a saturation mode where they exhibit switch-like properties required for logic circuit design. Keeping all device parameters and circuit topology constant, T d  is inversely proportional to the supply voltage V dd  if operation is over the threshold voltage.  
         [0009]     The delay T d  approximately doubles if the voltage is halved. Conversely, if the frequency is halved, the voltage can be reduced in practice.  
         [0010]     In addition to logic gate delay Td, the power P consumed by a CMOS device is 
 
 P=C   L   V   dd   2   f   (2) 
 
         [0011]     where f is the frequency. As can be seen, power has a quadratic dependence on the supply voltage V dd , and a linear relationship with the frequency f of operation. Since power consumption is proportional to clock frequency, the difference becomes more important at higher operating frequencies.  
         [0012]      FIG. 1   a  shows a single computation block C transformed into two discrete computation blocks that can be evaluated in a parallel configuration (spatially parallel) as shown in  FIG. 1   b  or in a pipelined configuration (temporally parallel) as shown in  FIG. 1   c . Computation block C has two inputs, D in1  and D in2  and a single output D out . Each data element in the data stream has a binary word length and communication can be serial (w=1) or parallel (w=2, 3, 4, . . . n, a plurality of lines corresponding to a binary word length). In order to operate, computation block C requires a supply voltage V and a clock frequency f.  
         [0013]     When the functional requirement of computation block C is decomposed into a system of parallel computation blocks C 1  and C 2  as in  FIG. 1   b , each block can be clocked at half the frequency of computation block C,  
         f   2     ,       
 
 while maintaining the same data throughput. Voltages V 1  and V 2  supplied to blocks C 1  and C 2  can be reduced by  
         1   2     ⁢     (     V   2     )         
 
 in proportion to the frequency  
       f   2       
 
 and are equal V 1 =V 2 . While voltage and frequency decrease by a factor of two, the total system capacitance increases approximately by a factor of two due to the parallel implementation. Power has a cubic relationship with voltage and frequency as shown in equations (1) and (2), leading to a 4× reduction in power. In practice, the power reduction is not as great due to additional wiring capacitances and smaller voltage reductions due to threshold voltage restrictions. 
 
         [0014]     When computation block C is functionally decomposed into a pipeline comprising serial computation blocks C 3  and C 4  as in  FIG. 1   c , additional latches are inserted at the boundary between blocks C 3  and C 4 . The latches enable the components of a pipeline to operate on different portions of the same data stream. Even though the frequency is f, the critical path through the computation block C is split by the latches. In  FIG. 1   a , the delay through computation block C is  
         1   f     .       
 
 In  FIG. 1   c , the delay through each computation block is  
       1   f       
 
 yielding a total delay of  
         2   f     ,       
 
 and the number of circuit elements in the critical path is reduced by two. The circuit elements within blocks C 3  and C 4  can have a larger delay and supply voltage V 3  can be reduced (V 3 &lt;V). The supply voltage V 3  and frequency f can be reduced by a factor of two leading to a 4× reduction in power. However, capacitance remains unchanged since the hardware for blocks C 3  and C 4  together constitute computation block C. In practice, power reduction is not as great due to extra capacitance added by latches and smaller voltage reductions. 
 
         [0015]     In terms of power consumption, the transformation of computation block C shown in  FIG. 1   b  is better than the transformation shown in  FIG. 1   c . In terms of performance, the transformations shown in  FIGS. 1   b  and  1   c  are approximately equal.  
         [0016]     Most existing parallel and pipelined computations use a single global clock and voltage supply. To decrease power consumption, voltage scaling has been employed which uses software controlled voltage modulation based on run-time demands. Other current design efforts for low power operation lower voltage for portions of the circuit, i.e., voltage islands, which are removed from the critical path. A power efficient solution for stream-based pipelines having a plurality of stages but with different computational requirements in each stage has not yet been proposed.  
       SUMMARY  
       [0017]     A method for optimizing voltage and frequency for pipelined architectures that offers better power efficiency is not available. The inventors have discovered that it would be desirable to have a method of implementing pipelined architectures that result in reduced power consumption while maintaining high throughput by determining frequencies and voltages in conjunction with semiconductor parameters that are dependent upon the amount of streaming data processed in each stage of the pipeline.  
         [0018]     One aspect of the invention provides methods for implementing a computation as a pipeline that processes streaming data. Methods according to this aspect of the invention preferably start with partitioning the computation into a plurality of temporal stages, each stage having at least one input and at least one output, wherein one of the stages is a first stage having at least one primary input and one of the stages is a last stage having at least one primary output, each stage defined by a clock frequency. Forming a pipeline by coupling at least one output from the first stage to at least one input of another one of the plurality of stages, and coupling at least one output from another one of the plurality of stages to at least one input for the last stage. Assigning a clock frequency to each one of the stages in the pipeline such that an overall throughput requirement is met and not all of the assigned stage clock frequencies are equal and assigning to each stage in the pipeline a supply voltage where not all of the assigned stage voltages are equal.  
         [0019]     Another aspect of the method of the invention is inserting at least one storage element in at least one of the plurality of stages in the pipeline to allow for operational independence between the storage element stage and another one of the plurality of stages.  
         [0020]     Yet another aspect of the method of the invention is an inverse discrete wavelet pipeline implementation having at least one reconstruction channel having a low input, a high input and an output, a row processing stage having a row reconstruction channel; the row reconstruction channel output coupled to a row stage storage element first input, the row storage element having a corresponding first output, and the row storage element having a second input and a corresponding second output, a third input and a corresponding third output, and a fourth input and a corresponding fourth output.  
         [0021]     Other objects and advantages of the systems and methods will become apparent to those skilled in the art after reading the detailed description of the preferred embodiments. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]      FIG. 1   a  is a diagram of an exemplary single computation block.  
         [0023]      FIG. 1   b  is a diagram of an exemplary parallel computation.  
         [0024]      FIG. 1   c  is a diagram of an exemplary pipeline computation.  
         [0025]      FIGS. 2   a  and  2   b  is a diagram of an exemplary method of the invention.  
         [0026]      FIG. 3  is a diagram of an exemplary pipeline in accordance with the invention.  
         [0027]      FIG. 4  is a diagram of an exemplary pipeline including a storage element in accordance with the invention.  
         [0028]      FIG. 5  is a diagram of an exemplary forward DWT.  
         [0029]      FIG. 6  is a diagram of an exemplary transverse digital filter.  
         [0030]      FIG. 7   a  is a diagram of an exemplary N row by M column array.  
         [0031]      FIG. 7   b  is a diagram of an exemplary row decomposition of the array of  FIG. 7   a.    
         [0032]      FIG. 7   c  is a diagram of an exemplary one level decomposition of the array of  FIG. 7   a.    
         [0033]      FIG. 7   d  is a diagram of an exemplary two level decomposition of the array of  FIG. 7   a.    
         [0034]      FIG. 7   e  is a diagram of an exemplary three level decomposition of the array of  FIG. 7   a.    
         [0035]      FIG. 7   f  is a diagram of an exemplary four level decomposition of the array of  FIG. 7   a.    
         [0036]      FIG. 8  is a data flow of an exemplary two level DWT.  
         [0037]      FIG. 9  is a diagram of an exemplary IDWT.  
         [0038]      FIG. 10   a  is a schematic of an exemplary IDWT column stage in accordance with the invention.  
         [0039]      FIG. 10   b  is a schematic of an exemplary IDWT row stage in accordance with the invention.  
         [0040]      FIGS. 11   a - 11   e  is an exemplary data flow of a five level, IDWT using the stages of  FIGS. 10   a  and  10   b.    
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0041]     Embodiments of the invention will be described with reference to the accompanying drawing figures wherein like numbers represent like elements throughout. Before embodiments of the invention are explained in detail, it is to be understood that the invention is not limited in its application to the details of the examples set forth in the following description or illustrated in the figures. The invention is capable of other embodiments and of being practiced or carried out in a variety of applications and in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms “mounted,” “connected,” and “coupled” are used broadly and encompass both direct and indirect mounting, connecting, and coupling. Further, “connected” and “coupled” are not restricted to physical or mechanical connections or couplings.  
         [0042]     Shown in  FIGS. 2   a  and  2   b  is the method of the invention. The method begins (step  101 ) with the examination of the computation for pipelining to determine performance requirements such as overall throughput required, number of bits for each data element in the data stream, number of discrete operations, inputs and outputs, and the like (step  103 ). The computation is partitioned temporally into a plurality of distinct pipeline stages (step  105 ) defined by a clock frequency.  
         [0043]     A typical high-level synthesis algorithm comprises a number of steps. The operations within a computation are decomposed into a standard set of operations supported by the pipeline stages. For example, multiplications are broken up into addition and shift operations. Then, an interconnected network of standard operations is formed and allocated to available stages in the pipeline. One algorithm for performing this task is list scheduling, where the given network is topologically sorted and each operation is assigned to a component in the pipeline stage capable of executing it. An operation is assigned only after its predecessors in the network have been assigned. Based on granularity, different operations in the network may be allocated to the same pipeline stage or different stages. Operations in different pipeline stages are temporally divided from each other by latches between stages. Several practical heuristics exist to synthesize a pipeline with minimal stages, minimal latency, etc. A more detailed discussion of the synthesis step is beyond the scope of this disclosure. After synthesis, the operation(s) performed within each stage is translated into a hardware equivalent (step  107 ).  
         [0044]     Depending upon the performance/computation requirements (step  103 ) and synthesis (step  105 ), a storage element with write and read functionality may be inserted within a pipeline stage (steps  109 ,  111 ) if required. Storage elements are used to maintain continuous data flow and may or may not be required.  
         [0045]     Once the hardware is synthesized and storage element allocation is complete, clock frequencies are assigned to each pipeline stage, starting with the final stage (step  113 ). The frequency of the final stage is determined to be as low as possible while maintaining the design throughput requirement. The clock frequency for each preceding stage is determined, set as low as possible while maintaining the design throughput (steps  115 ,  117 ,  119 ) until the clock frequencies for all stages in the pipeline are set to their lowest possible values.  
         [0046]     After all stage clock frequencies have been assigned, the operating voltage for each pipeline stage is determined according to the respective clock frequencies (steps  121 ,  123 ). As discussed above, supply voltage V dd  and time delay T d  are inversely proportional, which makes voltage V dd  and frequency f directly proportional. If the clock frequency for a preceding stage is halved, its supply voltage can likewise be halved so long as the stage supply voltage V dd  is higher than the hardware threshold voltage V th  as previously discussed.  
         [0047]      FIG. 3  shows an exemplary pipeline resulting from the method of the invention. For an overall process or computation block C, such as that shown in  FIG. 1   a , block C is partitioned into a plurality of stages. For this example, bock C is partitioned into two stages, C 5  and C 6 . Based upon the data processing functions performed within stage C 5 , the clock frequency f 5  supplied to stage C 5  is twice the frequency of f 6 (f 5 =2f 6 ) and a switching element sw is required at the input of stage C 5  to ensure both inputs, D in1  and D in2 , are provided to stage C 5  at the predetermined frequency f 5 . Switching element sw time-multiplexes the two inputs D in1 , and D in2  into a single input at twice the frequency. The voltage V 6  supplied to stage C 6  is set as low as possible, corresponding to the clock frequency f 6  requirements of stage C 6 , but greater than the hardware threshold voltage V th  of stage C 6 . The voltage V 5  supplied to stage C 5  is then set as low as possible, corresponding to the clock f 5  requirements of stage C 5 , but greater than the hardware threshold voltage V th  of stage C 5 .  
         [0048]      FIG. 4  shows the use of a storage element str between two consecutive pipeline stages, C 7  and C 8 . The storage element str allocates two memory spaces mem 1 , mem 2 . The use of the two memory spaces mem 1 , mem 2  accessed using associated write sw write  and read sw read  functions allows each pipeline stage C 7 , C 8  to work independently of the other. Each write/read function sw write , sw read  can be a functional equivalent of a single-pole double-throw switch, having one pole that can throw or make electrical contact with two separate stationary contacts such as an addressing function of the storage element str, an addressing function of a multiple input port—multiple output port static RAM, a memory space access device, a latch, and the like. The write/read function sw write , sw read  equivalents can switch one or a plurality of data lines w depending if the data path is serial or parallel to each memory space mem 1 , mem 2  memory content location. The memory spaces mem 1 , mem 2  in the storage element str are accessed independently, in an exclusive or arrangement by the write/read functions sw write , sw read  allowing for a write function sw write  to “write to” either memory space, and a read function sw read  to “read from” either memory space. The “writing to” and “reading from” functions can access the memory content locations of the memory spaces mem 1 , mem 2  in any predetermined pattern. The memory spaces mem 1 , mem 2  can have the same or different storage capacities.  
         [0049]     Depending upon the access of the read function sw read , storage element sir contents mem 1  or mem 2  can be read by stage C 8 . Depending upon the access of the write function sw write , storage element str contents mem 1  or mem 2  can be written to by stage C 7 . In this example, the access of the write sw write  and read sw read  functions are controlled in opposite correspondence—one memory space mem 2  is read from while the other memory space mem 1  is written to.  
         [0050]     Each stage C 7 , C 8  can process data until it reads (stage C 8 ) all data (mem 2 ), or writes (stage C 7 ) all data (mem 1 ). The separation of stage operations using a storage element sir is desirable when different stages have to write or read data in different patterns. The storage capacity of a memory space is greater than or equal to the latency of a following stage. A classic, prior art pipeline implementation only permits sequential dataflow, i.e., the output of a stage is accessed in the same order by the input of a subsequent stage. The operating frequency of the storage elements sir is that of its associated stage. The voltage V 8  supplied to stage C 8  is set as low as possible, corresponding to the clock f 8  requirements of stage C 8 , but greater than the hardware threshold voltage V th  of stage C 8 . The voltage V 7  supplied to stage C 7  is then set as low as possible, corresponding to the clock f 7  requirements of stage C 7 , but greater than the hardware threshold voltage V th  of stage C 7 .  
         [0051]     The advantage of the method of the invention is reduced power consumption. As discussed above, power has a quadratic relationship with voltage and a linear relationship with frequency. Power therefore has a cubic relationship with voltage and frequency together. If frequency and voltage are both halved, power consumption reduces by a factor of 8. Another advantage is the use of storage elements providing for high throughput.  
         [0052]     The invention is used to optimally realize in hardware operationally complex computations. What follows is an example of a low-power, high-throughput hardware implementation of multi-stage digital signal transformations based upon the teachings of the invention. The example implements one of the more complex portions of JPEG 2000 image reconstruction—a 2-dimensional IDWT.  
         [0053]     When reconstructing an image using a 2-dimensional IDWT, the amount of data increases with each successive level until the image is formed. To sustain the IDWT throughput, the hardware implementation requires resources that provide considerable storage, multipliers, and arithmetic logic units (ALUs). The method of the invention creates an efficient stream-based architecture employing polyphase reconstruction, multiple voltage levels, multiple clocked pipelines, and storage elements as will be described.  
         [0054]     By way of background, the wavelet transform converts a time-domain signal to the frequency-domain. The wavelet analysis filters different frequency bands, and then sections each band into slices in time. Unlike a Fourier transform, the wavelet transform can provide time and location information of the frequencies, i.e., which frequency components exist at different time intervals. Image compression is achieved using a source encoder, a quantizer and an entropy encoder. Wavelet decomposition is the source encoder for image compression. Computation time for both the forward and inverse DWT is great and increases exponentially with signal size.  
         [0055]     Wavelet analysis separates the smooth variations and details of an image by decomposing the image using a DWT into subband coefficients. The advantage of wavelet subband compression includes gain control for image softening and sharpening, and a scalable compressed data stream. Wavelet image processing keeps an image intact once it is compressed obviating distortions.  
         [0056]     A typical digital image is represented as a two-dimensional array of pixels, with each pixel representing the brightness level at that point. In a color image, each pixel is a triplet of red, green and blue (RGB) subpixel intensities. The number of distinct colors that can be represented by a pixel depends on the color depth, i.e., the number of bits per pixel (bpp).  
         [0057]     Images are transformed from an RGB color space to either a YCrCb or a reversible component transform (RCT) space leading to three components. After transformation, the image array can be processed.  
         [0058]     A time-domain function f(t) can be expressed in terms of wavelets using the wavelet series  
                 f   ⁡     (   t   )       =       ∑   s     ⁢       ∑   τ     ⁢       a     s   ,   τ       ⁢   ψ   ⁢           ⁢     (     s   ,   τ   ,   t     )     ⁢   dt           ,           (   3   )             
 
         [0059]     where ψ(S, τ, t) represents the different wavelets obtained from the “mother wavelet” ψ, and S indicates dilations of the wavelet. A large S indicates a wide wavelet that can extract low frequency components when convolved with the input signal, while a small S indicates a narrow wavelet that can extract high frequency components. τ represents different translations of the mother wavelet in time and is used to extract frequency components at different time intervals of the input signal.  
         [0060]     The coefficients a s,τ  of the wavelets are found using  
               a     s   ,   τ       =       ∫     -   ∞     ∞     ⁢       f   ⁡     (   t   )       ⁢     ψ   ⁡     (     s   ,   τ   ,   t     )       ⁢           ⁢       ⅆ   t     .                 (   4   )             
 
         [0061]     The discrete wavelet transform applies the wavelet transform to a discrete-time signal x(n) of finite length having N components. Filter banks are used to approximate the behavior of a continuous wavelet transform. Subband coefficients are found using a series of filtering operations.  
         [0062]     Wavelet decomposition—applying a DWT in a forward direction—is performed using two-channel analysis filters where the signal is decomposed using a pair of filters, a half band low pass filter and a half band high pass filter, into high and low frequency components followed by down-sampling. A forward DWT is shown in  FIG. 5 .  
         [0063]     Filtering a signal in the digital domain corresponds to the mathematical operation of convolution, where the signal is convolved with the impulse response of the filter. The half band low pass filter removes all frequencies that are above half of the highest frequency in the signal. The half band high pass filter removes all frequencies that are below half of the highest frequency in the signal. The low-frequency component usually contains most of the frequency of the signal and is referred to as the approximation. The high-frequency component contains the details of the signal.  
         [0064]     Most natural images have smooth color variations with fine details represented as sharp edges in between the smooth variations. The smooth variations in color can be referred to as low frequency variations and the sharp variations as high frequency variations. The low frequency components constitute the base of an image, and the high frequency components add upon them to refine the image giving detail.  
         [0065]     For image processing, digital high and low pass filters are commonly employed in the DWT and DCT processes as one or two-dimensional filters. One-dimensional filters operate on a serial stream of data, whereas two-dimensional filters comprise two one-dimensional filters that alternately operate on the data stream and its transpose.  
         [0066]     The filters used for decomposition are typically transverse digital filters as shown in  FIG. 6 . Transverse filters can be implemented using a weighted average. Filtering involves convolving the filter coefficients with the input signal, or stream of pixels 
 
 y[k]=Σ   i=−∞   i=∞   H[i].x[k−i]=Σ   i=0   i=K   H[i].x[k−i],   (5) 
 
         [0067]     where H 0 , H 1 , H 2 , H 3 , . . . H k  are predefined filter coefficients or weights and z −1  are shift register positions temporarily storing incoming values. With each new value, the filter calculates an output value for a given instant in time by observing the input values surrounding that instant of time. As a new value arrives, the shift register values are displaced discarding the oldest value. The process consists of multiplying each input value by the filter weights which define the filtering action. By adjusting the weights, a low pass or a high pass filter can be obtained. Since the filters employed are half band low pass and half band high pass filters, the filter architectures are the same for each level of decomposition.  
         [0068]     Decomposition of an N×M color space is performed in levels with each level performing a row-by-row (N) and a column-by-column (M) analysis. This type of wavelet decomposition is referred to as a 2-dimensional DWT, an example where N&lt;M is shown in  FIGS. 7   a - 7   f . Each N row contains M pixels, with each pixel typically having three color space multi-bit values. Decomposition is performed for each color space value. In image processing, the input signal is not a time-domain signal, but pixels distributed in space.  
         [0069]     Each row of pixels (sub pixel) is low and high pass filtered. After filtering, half of the samples can be eliminated or down-sampled, yielding two  
       N   ×     M   2         
 
 images referred to as L (low) and H (high) row subband coefficients. The intermediate results are indexed as an array in memory as shown in  FIG. 7   b.  
 
         [0070]     The Nyquist theorem states that the minimum number of discrete samples to perfectly reconstruct a signal is twice the maximum frequency component of the signal. Therefore, if a half band low pass filter, which removes all frequency components larger than the median frequency, is applied to a signal, every other sample in the output can be discarded. Discarding every other sample subsamples the signal by two whereby the signal will have half the number of discrete samples effectively doubling the scale. A variation of the theorem makes down-sampling applicable for a high pass filter that removes all frequency components smaller than the median frequency.  
         [0071]     Decomposition halves the time resolution since half of the number of samples characterizes the entire signal. However, the operation doubles the frequency resolution since the frequency band of the signal now spans only half the previous frequency band, effectively reducing the uncertainty in the frequency by half. This is referred to as subband coding.  
         [0072]     From the data store, each column (M) of coefficients is low and high pass filtered, down-sampled, and stored yielding four  
         N   2     ×     M   2         
 
 sub images as shown in  FIG. 7   c . The four sub images are the resultant coefficients of a one level, 2-dimensional decomposition. Of the four sub images obtained, the image obtained by low pass filtering the columns and rows is referred to as the LL (column low, row low) sub image. The image obtained by high pass filtering the columns and low pass filtering the rows is referred to as the HL (column high, row low) sub image. The image obtained by low pass filtering the columns and high pass filtering the rows is referred to as the LH (column low, row high) sub image. And the image obtained by high pass filtering the columns and rows is referred to as the HH (column high, row high) sub image. Each sub image obtained can then be filtered and subsampled to obtain four more sub images. This process can be continued for a desired subband structure. A subband is a set of real number coefficients which represent aspects of the image associated with a certain frequency range as well as a spatial area of the image. The result is a collection of subbands which represent several approximation scales. 
 
         [0073]     JPEG 2000 supports pyramid decomposition. Pyramid decomposition only decomposes the LL sub image in subsequent levels, each leading to four more sub images as shown in  FIGS. 7   d - 7   f .  FIG. 7   d  shows a two level decomposition producing second level subbands L 4 , HL 3 , LHL 2  and H 2 L 2 .  FIG. 7   e  shows a three level decomposition producing third level subbands L 6 , HL 5 , LHL 4  and H 2 L 4 .  FIG. 7   f  shows a four level decomposition producing fourth level subbands L 8 , HL 7 , LHL 6  and H 2 L 6 . At this level, the L 8  subband coefficients occupy  
         N   16     ×     M   16         
 
 of the original image space. A fifth level decomposition would produce fifth level subbands L 10 , HL 9 , LHL 8  and H 2 L 8  (not shown). The subbands for a five level decomposition of one video frame are: L 10 , HL 9 , LHL 8 , H 2 L 8 ; HL 7 , LHL 6 , H 2 L 6 ; HL 5 , LHL 4 , H 2 L 4 ; HL 3 , LHL 2 , H 2 L 2 ; HL, LH and HH. 
 
         [0074]     Shown in  FIG. 8  is the data flow for the two level, 2-dimensional forward DWT producing  FIG. 7   d . Each level of decomposition reduces the image resolution by a factor of two in each dimension. Each row process uses one analysis filter pair and each column process uses two analysis filter pairs. All of the subband coefficients represent the same image, but correspond to different frequency bands. The LL subband at the highest level contains the most information while the other detail bands contain relatively less information—image details such as sharp edges.  
         [0075]     The forward DWT analyzes the image data producing a series of subband coefficients. Rather than discarding some of the subband information and losing detail, all subband coefficients are kept and compression results from subsequent subband quantization and the compression scheme used in the entropy encoder. The quantizer reduces the precision of the values generated from the encoder reducing the number of bits required to save the transform coefficients.  
         [0076]     Reconstruction of the original image is performed in reverse; by entropy decoding, inverse quantization, and source decoding—the later performing the DWT in an inverse direction as shown in  FIG. 9 . The forward DWT separates image data into various classes of importance; the IDWT reconstructs the various classes of data back into the image.  
         [0077]     A filter pair comprising high and low pass filters is used and is referred to as a synthesis filter. The inverse process begins using the subband coefficients output from the last level of a forward DWT, applying the filters column wise and then row wise for each level, with the number of levels corresponding to the number of levels used in the forward DWT until image reconstruction is complete. The inputs at each level of reconstruction are subband coefficients.  
         [0078]     The IDWT can be implemented as a pipelined data path. Owing to up-sampling, successive stages of the pipeline operate on progressively higher amounts of data. For an N×M image, the last level of reconstruction operates on four subbands, each of size  
         N   2     ×       M   2     .         
 
 The four subbands of the preceding level are  
         N   4     ×       M   4     .         
 
         [0079]     The input to each level of the IDWT consists of four subbands and the final output is an N×M image. Each level consists of column and row processing. The column stage which includes up-sampling produces two subbands. These subbands are row processed which includes up-sampling to produce another subband. For a given level of reconstruction, the rows cannot be processed until all of the columns are processed. For a high throughput, the row and column stages must be able to operate independently of each other to ensure continuous data flow.  
         [0080]     Using the method of the invention shown in  FIGS. 2   a - 2   b  to implement an IDWT for a particular image resolution, the entire IDWT is analyzed and a performance requirement is established (steps  101 ,  103 ). For this example, a five level IDWT is to be implemented complementing the forward DWT described above. The overall computation is synthesized (step  105 ) into a plurality of levels (n=5), with each level comprising a column and a row stage. The column stage comprises two reconstruction channels; the row stage one reconstruction channel. Each reconstruction channel ( FIG. 9 ) comprises two up-samplers coupled to a synthesis filter and an adder providing a subband coefficient (summed filter) output. The fifth level subband coefficients output from the forward DWT are ultimately input at the n th -level (5 th  level) of the IDWT. Three subband coefficients are input at each subsequent level. The last level (1 st  level) outputs the image.  
         [0081]     From the synthesis step (step  105 ) one stage is produced for column processing  17  and another stage is produced for row processing  33  as shown in  FIGS. 10   a  and  10   b  respectively. The operations used in each stage are translated (step  107 ) into a hardware equivalent. As one skilled in the art will appreciate, the data paths show in  FIGS. 10   a ,  10   b , and  11   a - 11   e  can be serial (w=1) or parallel (w=2, 3, . . . n) data lines. Storage elements comprising allocated memory spaces (steps  109 ,  111 ) are employed between column and row processing. For each memory space within a storage element, one space is written to while the other space is read from, keeping the pipeline filled. Once each memory space write/read is completed, the memory space pair is exchanged, allowing for continuous data flow. The entire pipeline is choreographed such that every register in every function in every stage of the pipeline is filled, and with each clock cycle, data is moved forward with no stalling. Each stage  17 ,  33  has its own predetermined clock frequency clk colx , clk rowx  (step  115 ).  
         [0082]      FIG. 10   a  shows the column processing stage  17  derived for each level of the IDWT according to the teachings of the invention. The column processing stage  17  comprises two reconstruction channels having four inputs c in1 , c in2 , c in3 , c in4 , four up-samplers up 1 , up 2 , up 3 , up 4 , each coupled to an input, the up-sampler outputs coupled to two synthesis filters  19   1 ,  19   2  each synthesis filter comprising a low LPF 1 , LPF 3  and a high HPF 2 , HPF 4  pass filter, each filter having an input LPF in1 , HPF in2 , LPF in3 , HPF in4  coupled to a respective up-sampler up 1 , up 2 , up 3 , up 4 . Each synthesis filter pair  19   1 ,  19   2  output LPF out1 , HPF out2 , LPF out3 , HPF out4  is coupled to an adder  21   1 ,  21   2 . Each adder  21   1 ,  21   2  output is coupled to a storage element str col  write function sw 1   write .  
         [0083]     As described above, each storage element str col  allocates memory spaces for storing data output from an upstream computation, while allowing a downstream computation to read previously written data in any pattern. For each pair of memory spaces, write/read functions are used to direct data exclusively to and from each memory space for simultaneous writing and reading, allowing upstream and downstream computation stages to function independently.  
         [0084]     The storage element str col  for the column stage  17  has two pairs of allocated memory spaces mem 1   a , mem 1   b , mem 2   a , mem 2   b  accessed by write/read functions sw 1   write , sw 1   read , sw 2   write , sw 2   read . The common pole of the write function sw 1   write  is coupled to the output of the first channel adder  21   1 . The common pole of the write function sw 2   write  is coupled to the output of the second channel adder  21   2 . The common pole of the two read functions sw 1   read , sw 2   read  are coupled to stage outputs c out1 , c out2 . The column IDWT stage  17  is used in conjunction with the row IDWT stage  33  for 2-dimensional IDWT, n level reconstruction.  
         [0085]     A voltage input Vcol x  provides operating voltage for the column x stage  17  based upon clock  27  frequency. A controller  31  accepts an image information signal setting forth the size of the image, frame rate, color depth (bpp), level of reconstruction known a priori from a common bus BUS coupling all stages in all levels and controls the switching action of the storage element str col  write/read functions over line  29 . The image information is obtained either from an external control such as a user configurable setting, or more advantageously, decoded upstream prior to entropy decoding in the incoming data stream header. A maximum image size determines the required storage element capacity for each column  17  and row  33  stage. Image sizes less than the maximum can be processed. Each smaller image size has a correspondingly smaller memory footprint in the allocated memory spaces. The image information changes each storage element memory space access write/read function pattern for each image size.  
         [0086]      FIG. 10   b  shows the row processing stage  33  derived for each level of the IDWT according to the teachings of the invention. The row processing stage  33  comprises one reconstruction channel and five inputs r in1 , r in2 , r in3 , r in4 , r in5 , two up-samplers up L , up H , coupled to inputs r in1 , r in2 , the up-sampler outputs coupled to a synthesis filter  19  comprising a low LPF and a high HPF pass filter, each filter having an input LPF in , HPF in  coupled to a respective up-sampler up L , up H , and an output LPF out , HPF out  coupled to the reconstruction channel adder  21 . The adder  21  output is coupled to a storage element str row  write function sw write .  
         [0087]     The storage element str row  for the row stage  33  has four pairs of allocated memory spaces mem a , mem b , mem 3   a , mem 3   b , mem 4   a , mem 4   b , mem 5   a , mem 5   b  accessed by four write/read functions sw write , sw read , sw 3   write , sw 3   read , sw 4   write , sw 4   read , sw 5   write , sw 5   read . Write function sw write  is coupled to the output of the adder  21 . The three remaining write functions sw 3   write , sw 4   write , sw 5   write  are coupled to stage inputs r in3 , r in4 , r in5  to receive subband coefficients available and waiting to be processed. The four read functions sw read , sw 3   read , sw 4   read , sw 5   read  couple to row stage outputs r out , r out3 , r out4 , r out5 .  
         [0088]     A voltage input Vrow x  provides operating voltage for the row x stage  33  based upon clock  37  frequency. A controller  41  accepts a signal setting forth the size of the image, color depth (bpp) and level of reconstruction, known a priori, from a common bus BUS and controls the switching action of the storage element str row  write/read functions over line  39 . The row processing stage  33  for the last level is simplified needing only the reconstruction channel.  
         [0089]      FIGS. 11   a - 11   e . show a five level IDWT using the column  17  and row  33  stages. The beginning of the inverse transform is the fifth level as shown in  FIG. 11   a . The fifth level column stage clock frequency clk col5  is the slowest. Each subsequent stage processes twice as much data as the one before, requiring double the clock frequency. The voltage of each subsequent stage must increase for maximum power efficiency, or can be set at any level as long as the hardware voltage threshold V th  for the respective level is met. The voltage Vcol x  of each column stage  17  can be approximately half the voltage Vrow x  of each row stage  33  for a given level.  
         [0090]     By knowing the reconstructed image size, bpp and number of levels of reconstruction; the column str col5 , str col4 , str col3 , str col2 , str col1  and row Str row5 , Str row4 , Str row3 , str row2  storage element memory spaces, clock frequencies clk col5 , clk row5 , clk col4 , Clk row4 , clk col3 , clk row3 , clk col2 , clk row2 , clk col1 , clk row1  and stage voltages V col5 , V row5 , V col4 , V row4 , V col3 , V row3 , V col2 , V row2 , V col1 , V row1  and can be determined.  
         [0091]     Continuing with the example, for real-time reconstruction of one color plane of a moving picture having an image resolution of 1024(2 10 )×2048(2 11 ) pixels (i.e., sub pixels) at a frame rate of 48 frames per second, wavelet reconstruction of the 1024(N)×2048(M) color space would assemble an image having 2,097,152 pixels, requiring the source decoder (IDWT) to process 100,663,296 pixels per second with each pixel having an associated color depth. For this example, each pixel has a 16 bit value. The larger the color depth, the more storage element memory required. The clock rate supporting real-time reconstruction would be ˜9.9 ns per pixel or ˜101 MHz at the output of the last (1 st ) level (step  115 ).  
         [0092]     For moving images having a frame rate of 48 fps, each frame of the moving image is processed for display every 0.0208 seconds. For the five level IDWT  51  shown in  FIGS. 11   a - 11   e , the clock frequency of the level  1  row stage Clk row1  must process each pixel at ˜101 MHz. As described above, each subsequent stage in an IDWT operates at twice the frequency of the previous stage. Each previous stage operates slower. In inverse order, clk col1 =50.5 MHz; clk row2 =25.3 MHz, clk col2 =12.6 MHz, clk row3 =6.3 MHz, clk col3 =3.16 MHz, Clk row4 =1.58 MHz, clk col4 =789 kHz, Clk row5 =395 kHz, clk col5 =197 kHz, and clk x =98,600 Hz (steps  117 ,  119 ).  
         [0093]     The last step of the invention is assigning operating voltages (steps  121 ,  123 ) to each stage in the pipeline  51 . The ten stage voltages V col5 , V row5 , V col4 , V row4 , V col3 , V row3 , V col2 , V row2 , V col1 , V row1  can be determined since each stage voltage is proportional with the stage operating frequency. Each stage voltage must be greater than the threshold voltage V th  of the respective stage hardware. A theoretical value can be approximated for each stage threshold voltage V th  or obtained empirically. For the streaming computation to have maximum power efficiency, the stage in the pipeline having the fastest clock frequency clk row1  will typically have the highest voltage V row1  and the stage having the slowest clock frequency clk col5  will have the lowest voltage level V col5 . The stage voltages residing between the maximum V row1  and minimum V col5  vary accordingly V row5 , V col4 , V row4 , V col3 , V row3 , V col2 , V row2 , V col1 . Alternatively, each stage voltage in the pipeline can have the same value, or at least one or more different values, so long as the voltage threshold requirement for each stage is met.  
         [0094]     After entropy decoding, inverse quantization and removal of any header information is complete, the subband pixel coefficients for each frame of the one color plane enter the source decoder  51  at a clock clk x  rate of 98,600 Hz.  
         [0095]      FIGS. 11   a - 11   d  shows an incoming frame subband coefficient data stream L 10 , HL 9 , LHL 8 , H 2 L 8 ; HL 7 , LHL 6 , H 2 L 6 ; HL 5 , LHL 4 , H 2 L 4 ; HL 3 , LHL 2 , H 2 L 2 ; HL, LH and HH, and their respective storage element memory spaces  53   a ,  53   b ,  55   a ,  55   b ,  57   a ,  57   b ,  59   a ,  59   b ,  61   a ,  61   b . Each storage element memory space alternately stores subband coefficients for one incoming frame for reconstruction. For this example, the incoming frame subband coefficients would be continuously written 48 times per second in alternate a, b memory spaces of the incoming frame  53   a ,  53   b , and fifth  55   a ,  55   b , fourth  57   a ,  57   b , third  59   a ,  59   b , and second  61   a ,  61   b  level row storage elements str rowx . The fifth level subband coefficients L 10 , HL 9 , LHL 8 , H 2 L 8 , fourth level subband coefficients HL 7 , LHL 6 , H 2 L 6 , third level subband coefficients HL 5 , LHL 4 , H 2 L 4 , second level subband coefficients HL 3 , LHL 2 , H 2 L 2  and first level subband coefficients HL, LH and HH for frame  1  are written into one of the memory spaces (a) of the storage elements, completing all subband coefficients for one frame. The coefficients arrive in time for each level of reconstruction. A discussion of inverse quantization which controls the incoming subband coefficients is beyond the scope of this disclosure. The process continues by writing the fifth level subband coefficients L 10 , HL 9 , LHL 8 , H 2 L 8  for the next frame ( 2 ) into the other memory space (b) of the incoming frame storage element  53 .  
         [0096]     As can be seen in  FIG. 11   a , fifth level reconstruction for frame  1  can commence as soon as fifth level subband coefficients L 10 , HL 9 , LHL 8 , H 2 L 8  are written into incoming frame storage element  53  memory space  53   a . The processing rate for the column stage clk col5  is 197 kHz. The fourth level subband coefficients HL 7 , LHL 6 , H 2 L 6  are written into fifth level row storage element  55  memory spaces  55   a  at the clk row5  clock rate. The output of the fifth level, L 8 , is written into a first memory space  63   a  of the fifth level row storage element with fourth level subband coefficients HL 7 , LHL 6 , and H 2 L 6  for fourth level processing.  
         [0097]     Fourth level reconstruction ( FIG. 11   b ) commences and the outputs are computed at the clk col4  clock rate. The third level subband coefficients HL 5 , LHL 4 , H 2 L 4  are written into fourth level row storage element  57  memory spaces  57   a  at the clk row4  clock rate. The output of the fourth level, L 6 , is written into one memory space  65   a  of the fourth level row storage element with third level subband coefficients HL 5 , LHL 4 , and H 2 L 4  for third level processing.  
         [0098]     Third level reconstruction ( FIG. 11   c ) commences and is performed at the clk col3  clock rate. The second level subband coefficients HL 3 , LHL 2 , H 2 L 2  are written into third level row storage element  59  memory spaces  59   a  at the clk row3  clock rate. The output of the third level, L 4 , is written into one memory space  67   a  of the third level row storage element with second level subband coefficients HL 3 , LHL 2 , and H 2 L 2  for second level processing.  
         [0099]     Second level reconstruction ( FIG. 11   d ) can commence and is performed at the clk col2  clock rate. The first level subband coefficients HL, LH and HH are written into second level row storage element  61  memory spaces  61   a  at the clk row2  clock rate. The output of the second level, L 2 , is written into one memory space  69   a  of the second level row storage element with first level subband coefficients HL, LH and HH for first level processing.  
         [0100]     First level reconstruction ( FIG. 11   e ) can commence and is performed at the clk col1  clock rate. The output of the first level is a one color plane reconstruction of the 1024(N)×2048(M) image.  
         [0101]     The entire five level IDWT  51  is filled and busy, with each stage of each level processing coefficients belonging to a subsequent frame. Column  17  and row  33  stages of each level of the IDWT  51  contain storage elements str colx , str rowx  for allocating memory spaces mem a , mem b  for the fifth level  71   a ,  71   b ,  63   a ,  63   b ,  55   a ,  55   b , fourth level  73   a ,  73   b ,  65   a ,  65   b ,  57   a ,  57   b , third level  75   a ,  75   b ,  67   a ,  67   b ,  59   a ,  59   b , second level  77   a ,  77   b ,  69   a ,  69   b ,  61   a ,  61   b , and first level  79   a ,  79   b , for holding the results of column processing  17  before row processing  33  and allowing the row processing stages  33  to access the memory spaces in a transpose read.  
         [0102]     The fifth level subband coefficients L 10 , HL 9 , LHL 8  and H 2 L 8  each comprise 32×64 values ( FIG. 11   a ). For a color depth of 16 bpp, the memory required for one memory space  53   a  of the incoming frame storage element  53  would be 32,768 bits, or 4,096 bytes for all coefficients of one subband. Since there are four subbands L 10 , HL 9 , LHL 8  and H 2 L 8 , and the invention allocates two memory spaces for coefficients of each subband, the total subband coefficient memory required for the fifth level incoming frame storage element  53  is approximately (4,096 bytes)×(4 subbands)×(2 memory spaces)≅32 KB.  
         [0103]     The four subbands L 10 , HL 9 , LHL 8  and H 2 L 8  are read by column, up-sampled up 1 , up 2 , up 3 , up 4  by inserting a zero between each coefficient, and low pass and high pass filtered using the two synthesis filters  19   1 ,  19   2 . Up-sampling increases the clock rate by a factor of two, transitioning from 98,600 Hz (clk x ) to 197 kHz (clk col5 ). The synthesis filter  19   1 ,  19   2  outputs are summed  21   1 ,  21   2  forming two subbands L 9  and HL 8  each comprising 64×64 coefficients which are written into a fifth level column storage element  71 . The memory required would be 65,536 bits, or 8,192 bytes for all coefficients of one subband. Since there are two subbands L 9  and HL 8 , and two memory spaces are employed, the total subband memory required for the fifth level row storage element  71  is approximately (8,192 bytes)×(2 subbands)×(2 memory spaces)≅32 KB.  
         [0104]     The coefficients of subbands L 9  and HL 8  are read by rows in a row stage  33 , up-sampled up L , up H , and low pass and high pass filtered using one synthesis filter  19 . The 197 kHz clock rate (clk col5 ) transitions to 395 kHz (clk row5 ). The values are summed  21  forming subband coefficients L 8  and are written into a fourth level row storage element  63 ,  55 .  
         [0105]     The amount of memory required to store subband coefficients for each level of the IDWT progressively increases by a factor of four. The fourth level subbands L 8 , HL 7 , LHL 6  and H 2 L 6  each comprise 64×128 coefficients. For a sixteen bit color depth, 131,072 bits or 16,384 bytes are required. Using two memory spaces, (16,384 bytes)×(4 subbands)×(2 memory spaces)≅131 KB are required.  
         [0106]     At the fourth level, subbands L 8 , HL 7 , LHL 6  and H 2 L 6  are up-sampled and column  17  processed ( FIG. 11   b ). The 395 kHz clock rate (clk row5 ) transitions to 789 kHz (clk col4 ). After column processing  17 , subbands L 7  and HL 6  each comprising 128×128 coefficients are written into a fourth level column storage element  73  and are available for row processing  33 . The memory required would be 262,144 bits, or 32,768 bytes for all coefficients of one subband. Since there are two subbands and two memory spaces are employed, the total subband memory required for the fourth level column storage element  73  is approximately (32,768 bytes)×(2 subbands)×(2 memory spaces)≅131 KB. After row processing  33 , subband L 6  coefficients are written into a third level row storage element  65 ,  57 . The 789 kHz clock rate (clk col4 ) transitions to 1.58 MHz (clk row4 ). The third level subbands L 6 , HL 5 , LHL 4  and H 2 L 4  each comprise 128×256 coefficients. For a sixteen bit color depth, 524,288 bits or 65,536 bytes are required. Using two memory spaces  65   a ,  65   b ,  57   a ,  57   b , (65,536 bytes)×(4 subbands)×(2 memory spaces)≅524 KB are required.  
         [0107]     At the third level, subbands L 6 , HL 5 , LHL 4  and H 2 L 4  are up-sampled and column processed  17  ( FIG. 11   c ). The 1.58 MHz clock rate (Clk row4 ) transitions to 3.16 MHz (clk col3 ). After column processing  17 , subbands L 5  and HL 4  each comprising 256×256 coefficients are written into a third level column storage element  75  and are available for row processing  33 . The memory required would be 1,048,576 bits, or 131,072 bytes for all coefficients of one subband. Since there are two subbands and two memory spaces are employed, the total subband memory required for the third level  75   a ,  75   b  is approximately (131,072 bytes)×(2 subbands)×(2 memory spaces)≅524 KB. After row processing  33 , subband coefficients L 4  are written into a third level row storage element  67 ,  59 . The 3.16 MHz clock rate (clk col3 ) transitions to 6.3 MHz (Clk row3 ). The second level subbands L 4 , HL 3 , LHL 2  and H 2 L 2  each comprise 256×512 coefficients. For a sixteen bit color depth, 2,097,152 bits or 262,144 bytes are required. Using memory spaces  67   a ,  67   b ,  59   a ,  59   b , (262,144 bytes)×(4 subbands)×(2 memory spaces)≅2 MB are required.  
         [0108]     At the second level, subbands L 4 , HL 3 , LHL 2  and H 2 L 2  are column processed  17  ( FIG. 1   d ). The 6.3 MHz clock rate (clk row3 ) transitions to 12.6 MHz (clk col2 ). After column processing  17 , subbands L 3  and HL 2  each comprising 512×512 coefficients are written into a second level column storage element  77  and are available for row processing  33 . The memory required would be 4,194,304 bits, or 524,288 bytes for all coefficients of one subband. Since there are two subbands and memory spaces are employed, the total subband memory required for the second level column storage element  77  is approximately (524,288 bytes)×(2 subbands)×(2 memory spaces)≅2 MB. After row processing  33 , subband coefficients L 2  are written into a second level row storage element  69 ,  61 . The 12.6 MHz clock rate (clk col2 ) transitions to 25.3 MHz (clk row2 ). The first level subbands LL, HL, LH and HH each comprise 512×1024 values. For a sixteen bit color depth, 8,388,608 bits or 1,048,576 bytes are required. Using memory spaces  69   a ,  69   b ,  61   a ,  61   b , (1,048,576 bytes)×(4 subbands)×(2 memory spaces)≅8 MB are required.  
         [0109]     At the first level, subbands L 2 , HL, LH and HH are column processed  17  ( FIG. 11   e ). The 25.3 MHz clock rate (clk row2 ) transitions to 50.5 MHz (clk col1 ). After column processing  17 , subbands L and H each comprising 1024×1024 coefficients are written into a first level column storage element  79  and are available for row processing  33 . The memory required would be 16,777,216 bits, or 2,097,152 bytes for all coefficients of one subband. Since there are two subbands and memory spaces are employed, the total subband memory required for the first level column storage element  79  is approximately (2,097,152 bytes)×(2 subbands)×(2 memory spaces)≅8 MB. The 50.5 MHz clock rate (clk col1 ) transitions to 101 MHz (clk row1 ) during row processing  17 .  
         [0110]     The above example shows the method of the invention as applied to one type of signal processing transform, the IDWT, requiring multiple temporal stages, each stage having a storage element allocating memory spaces and its own operating frequency and voltage for maximum power efficiency. The invention can likewise be used to derive pipeline stages for a DWT, DCT, IDCT and other signal processing streaming calculations.  
         [0111]     Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.