Abstract:
Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.

Description:
FIELD OF THE INVENTION 
   The present invention relates to methods of fabricating semiconductor structures, and particularly to methods of fabricating semiconductor structures having a polysilicon gate MOSFET and a high-K dielectric metal gate MOSFET on the same semiconductor substrate. 
   BACKGROUND OF THE INVENTION 
   Enhancement of complementary metal oxide semiconductor (CMOS) circuit requires improvement in the performance of both the p-type metal oxide semiconductor field effect transistors (PMOSFETs) and n-type metal oxide semiconductor field effect transistors (NMOSFETs). While the same material and processing steps were shared between PMOSFETs and NMOSFETs in the past, recent trends in high performance PMOSFETs and NMOSFETs show increased use of different materials and different processing steps among the two types of transistors. 
   An example in which differences in the manufacture of the transistors are preferred is in the selection of the gate conductor material. In the case of an NMOSFET, it is preferred that a work function of a gate electrode material is close to a conduction band edge. In contrast, in the case of a PMOSFET, it is preferred that a work function of a gate electrode material is close to a balance band edge. Since the conduction band edge is separated by the balance band edge by a band gap in a semiconductor material, the work function of the gate electrode material for the PMOSFET needs to be different from the work function of the gate electrode material for the NMOSFET. Hence, the need arises to utilize two different gate electrode materials for a high performance CMOS circuit, in which one material is utilized for the gates of PMOSFETs while another material is utilized for the gates of the NMOSFETs. 
   Various CMOS device structures with two different gate electrode materials and methods of manufacturing the same have been known in the art. For example, Rhee et al., in U.S. Patent Application Publication No. 2002/0113294 discloses CMOS devices with doped silicon germanium alloy gate electrodes with differing concentration gradients of germanium between PMOSFET electrodes and NMOSFET electrodes. Similarly, Takayanagi et al., in U.S. Pat. No. 6,746,943, disclose compensation for differences in activation of p-type dopants and n-type dopants with polysilicon-germanium alloy material having different germanium concentrations between PMOSFET electrodes and NMOSFET electrodes. Further, Polishchuk et al., in U.S. Pat. No. 6,794,234 discloses CMOS devices in which PMOSFET gate electrodes comprise a first metal, while NMOSFET gate electrodes comprise a second metal. Some of the prior art listed above also enables use of at least one high-k dielectric material within metal gate structures. 
   Using one metal for one type of gate electrode and polysilicon for another type of gate electrode is an alternative to the above listed prior art. An advantage of such an approach is that process integration is less complex compared to integration schemes that utilize two metal gate materials since processing of each metal gate material tends to introduce challenges. At the same time, utilization of a metal gate offers a control mechanism for gate work function that is effective enough to achieve substantial improvement in the performance of one type of transistors. 
   Since the use of a metal gate electrode with a high-K dielectric often introduces additional challenging, and oftentimes costly, processing steps, improvement of device performance through use of a metal gate electrode needs to be evaluated against the cost of the additional processes. For example, performance of NMOSFETs may improve significantly with the use of a metal gate electrode and a high-K dielectric to justify the associated additional cost while improvement of performance of PMOSFETs may not be sufficient to justify associated incremental cost. 
   Therefore, there exists a need for integration schemes that employ a metal gate material and a high-K dielectric on one type of MOSFET while utilizing a polysilicon gate on the other type of MOSFET. 
   Furthermore, there exists a need for integration schemes that manufacture a high-K dielectric metal gate MOSFET and a polysilicon gate MOSFET on the same semiconductor substrate with as little additional process complexity and processing cost as possible. 
   SUMMARY OF THE INVENTION 
   The present invention addresses the needs described above by providing methods of manufacturing a semiconductor structure with a polysilicon gate electrode and a high-K dielectric metal gate electrode on the same semiconductor substrate. 
   A method of forming a semiconductor structure according to the present invention comprises: 
   forming a first stack of a first gate dielectric layer and a first polysilicon layer directly on a first portion of a semiconductor substrate; 
   forming a second stack of a second gate dielectric, a metal gate layer, and a silicon-containing layer directly on the first stack and on a second portion of a semiconductor substrate; and 
   forming a second polysilicon layer directly on the first polysilicon layer and directly on the silicon-containing layer. 
   According to a first embodiment, a second embodiment, and a third embodiment of the present invention, the method of forming the semiconductor structure further comprises forming a gate cap dielectric layer on the second polysilicon layer. 
   According to the first embodiment of the present invention, the method of forming the semiconductor structure still further comprises: 
   forming a patterning in the first polysilicon layer over the first portion and in the silicon-containing layer over the second portion; 
   masking the first portion with a photoresist; 
   transferring the pattern into the second gate dielectric layer over the second portion; 
   removing the photoresist from over the first portion; and 
   transferring the pattern into the first gate dielectric layer from over the first portion. 
   According to the second embodiment of the present invention, the method of forming the semiconductor structure still further comprises: 
   forming a patterning in the gate cap dielectric; 
   masking the second portion with a first photoresist; 
   transferring the pattern into the first polysilicon layer from over the first portion; 
   masking the first portion with a second photoresist; 
   transferring the pattern into the metal gate layer and the second gate dielectric layer over the second portion; and 
   etching the first gate dielectric layer from the first portion. 
   According to the third embodiment of the present invention, the method of forming the semiconductor structure still further comprises: 
   forming a patterning in the gate cap dielectric; 
   masking the first portion with a first photoresist; 
   transferring the pattern into the metal gate layer and the second gate dielectric layer over the second portion; 
   masking the second portion with a second photoresist; 
   transferring the pattern into the first polysilicon layer from over the first portion; and 
   etching the first gate dielectric layer from the first portion. 
   According to a fourth embodiment, of the present invention, the method of forming the semiconductor structure further comprises: 
   masking the first portion with a first photoresist 
   recessing the second polysilicon layer from the second portion; 
   lithographically forming a pattern containing at least one first gate electrode over the first portion and at least one second gate electrode over the second portion; 
   transferring the pattern into the metal gate layer over the second portion and into an upper portion of the first polysilicon layer in the first portion, while not etching a lower portion of the first polysilicon layer; and 
   transferring the pattern into the second gate dielectric layer, the lower portion of the first polysilicon layer, and the first gate dielectric layer. 
   According to all embodiments of the present invention, the second gate dielectric layer preferably comprises a stack of an oxide-containing dielectric layer less than about 1 nm in thickness and a high-K dielectric layer, wherein the oxide-containing dielectric layer is an oxide layer or an oxynitride layer. Further, the first gate dielectric layer preferably comprises a material selected from the group consisting of silicon oxide and silicon oxynitride. 
   According to all embodiments of the present invention, the first polysilicon layer is preferably formed by deposition of a blanket polysilicon layer followed by a partial etch of said blanket polysilicon layer and has a thickness in the range from about 10 nm to about 50 nm. The second gate dielectric layer preferably has a thickness in the range from about 2 nm to about 10 nm. The metal gate layer preferably has a thickness in the range from about 2 nm to about 10 nm. 
   According to all embodiments of the present invention, said silicon-containing layer is an amorphous silicon layer and has a thickness in the range from about 10 nm to about 50 nm, and said second polysilicon layer has a thickness in the range from about 40 nm to about 120 nm n. 
   According to the first through third embodiments of the present invention, and the gate cap dielectric layer preferably has a thickness in the range from about 15 nm to about 60 nm. 
   Optionally, the present invention may further comprise ion-bombarding the second dielectric layer prior to transferring the pattern into the second gate dielectric layer. 
   The present invention forms a structure with two types of gate electrodes in which at least one first gate electrode comprises a vertical stack of a first gate dielectric layer, a first polysilicon layer, and a second polysilicon layer while at least one second gate electrode comprises a second gate dielectric layer, a metal gate layer, a silicon-containing layer, and a second polysilicon layer. Both gate electrodes may have a gate cap dielectric layer on top of the second polysilicon layer. The silicon-containing layer preferably contains amorphous silicon, and more preferably, is an amorphous silicon layer. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1-6  are sequential vertical cross-sectional views of an exemplary semiconductor structure according to the first through fourth embodiments of the present invention. 
       FIG. 7  is a vertical cross-sectional view of the exemplary semiconductor structure according to the first through third embodiments of the present invention. 
       FIGS. 8-10  are sequential vertical cross-sectional views of the exemplary semiconductor structure according to the first embodiment of the present invention. 
       FIG. 11  is a vertical cross-sectional view of the exemplary semiconductor structure according to the second and third embodiments of the present invention. 
       FIGS. 12-16  are sequential vertical cross-sectional views of the exemplary semiconductor structure according to the second embodiment of the present invention. 
       FIGS. 17-21  are sequential vertical cross-sectional views of the exemplary semiconductor structure according to the third embodiment of the present invention. 
       FIGS. 22-25  are sequential vertical cross-sectional views of the exemplary semiconductor structure according to the fourth embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   As stated above, the present invention relates to methods of manufacturing a semiconductor structures with at least one polysilicon gate electrode and at least one high-K dielectric metal gate electrode, which will now be described in greater detail by referring to the drawings that accompany the present application. 
   According to  FIGS. 1-6 , a series of vertical cross-sectional views demonstrating formation of an exemplary semiconductor structure with a polysilicon gate electrode, a high-K dielectric metal gate electrode, and shallow trench isolation are sequentially shown.  FIGS. 1-6  are common processing steps according to the four embodiments of the present invention to be shown below. The non-limiting four embodiments of the present invention are shown for demonstration of the practicability of the present invention and obvious alterations and variations of these methods are implied in the present disclosure. Manufacture of more than two gate electrodes according to the spirit of the present invention is straightforward to one of ordinary skill in the art, and such applications are also implied herein. 
   Referring to  FIG. 1 , there is shown a semiconductor substrate  8  which comprises a first portion  10 , a second portion  12 , and shallow trench isolation  20  between the two portions ( 10 ,  12 ). The first portion  10  and the second portion  12  may have the same crystallographic orientations, which is the case for a bulk substrate or a non-hybrid silicon-on-insulator (SOI) substrate, or they may have different crystallographic orientations, which is the case for a hybrid orientation substrate with or without a buried oxide layer. It is preferred that the first portion  10  and the second portion  12  have different crystallographic orientations. For example, the first portion may have a (110) surface orientation and the second portion may have an (100) orientation. While the present invention is demonstrated with a polysilicon gate on the first portion  10  and with a high-K dielectric metal gate on the second portion  12 , reversing the two portions ( 10 ,  12 ) is also straightforward. Further, changing the crystallographic orientations of each portion to any of the major crystallographic orientations such as (100), (110), (11), (211), (221), (311), and (331) is also practicable and is herein explicitly contemplated. 
   A first gate dielectric layer  30  is formed over the first portion  10 , the second portion  12 , and the shallow trench isolation  20 . The first gate dielectric layer  30  may be a conventional dielectric layer and, for example, may comprise a material selected from the group consisting of silicon oxide and silicon oxynitride. 
   Preferably, a blanket polysilicon layer  31  is deposited as shown in  FIG. 1  and thinned to a first polysilicon layer  32  as shown in  FIG. 2 . Alternatively, the first polysilicon layer  32  may be deposited with the required thickness The first polysilicon layer  32  is preferably formed by deposition of a blanket polysilicon layer  31  followed by a partial etch of the blanket polysilicon layer  31 . The first polysilicon layer  32  preferably has a thickness in the range from about 10 nm to about 50 nm. The thickness of the blanket polysilicon layer  31  as deposited is greater than 50 nm to insure continuity of the film and is preferably in the range from about 60 nm to about 200 nm. The first polysilicon layer  32  is preferably undoped. 
   Referring to  FIG. 3 , a first photoresist  35  is applied to the top surface of the semiconductor structure above and lithographically patterned to block the first portion  10  of the semiconductor substrate  8 , while exposing the second portion  12  of the semiconductor substrate  8 . The exposed portions of the first polysilicon layer  32  and the first gate dielectric layer  30  over the second portion  12  of the semiconductor substrate  8  are etched preferably by a first reactive ion etch (RIE). 
   Referring to  FIG. 4 , a stack of a second gate dielectric layer  40  and a metal gate layer  42  are formed directly on the remaining first polysilicon layer  32  over the first portion  10  of the semiconductor substrate  8  and on the exposed semiconductor surface of the second portion  12  of the semiconductor substrate  8 . Preferably, the second gate dielectric layer  40  comprises a stack of an oxide-containing dielectric layer less than about 1 nm in thickness and a high-K dielectric layer. The oxide containing dielectric layer contacts the exposed semiconductor surface of the second portion  12 . The oxide containing dielectric layer may be a silicon oxide layer, a silicon oxynitride layer, or a stack of at least one oxide layer and at least one nitride layer. The high-K dielectric layer may comprise a metal oxide such as HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , and LaAlO 3 . Alternatively, the high-K dielectric layer may comprise hafnium silicates, barium-strontium-titantates (BSTs) or lead-zirconate-titanates (PZTs). The gate dielectric materials may be formed by atomic layer deposition (ALD)), thermal or plasma oxidation, thermal or plasma nitridation, chemical vapor deposition (CVD), and physical vapor deposition (PVD). The total thickness of the second gate dielectric layer  40  is in the range from about 2 (1 nm) nm to about 10 nm, and preferably in the range from about 2 (1 nm) nm to about 5 nm. 
   A metal gate layer  42  is formed directly on top of the second gate dielectric  40 . The metal gate layer  42  may comprise base metals, metal alloys or conductive refractory metal nitrides such as TaN, TiN, and WN. The material for the metal gate layer  42  is selected for optimal work function for the MOSFET device to be built over the second portion  12  of the semiconductor substrate  8 . Preferably, the thickness of the metal gate layer  42  is in the range from about 2 nm to about 10 nm. 
   A silicon-containing layer  50  is formed directly on the top of the metal gate layer  42 . The silicon-containing layer  50  may be an amorphous silicon layer, a polysilicon layer, an amorphous silicon alloy, or a polycrystalline silicon alloy. Preferably, the silicon-containing layer  50  is an amorphous silicon layer. The thickness of the silicon-containing layer  50  may be in the range from about 10 nm to about 50 nm. Preferably, the silicon-containing layer  50  is not doped. 
   Referring to  FIG. 5 , a second photoresist  55  is applied to the top surface of the semiconductor structure above and lithographically patterned to block the portion of the silicon-containing layer  50  over the second portion  12  of the semiconductor substrate  8  while exposing the area over the first portion  10 . The exposed portion of the stack of the silicon-containing layer  50 , the metal gate layer  42 , and the second gate dielectric layer  40 , is etched preferably by a second reactive ion etch (RIE) and removed from over the first portion  10  of the semiconductor substrate  8 . The second photoresist  55  is thereafter removed. The top surface of the silicon-containing silicon layer  50  over the second portion  12  of the semiconductor substrate  8  may be higher as shown in  FIG. 5  or may be lower than the top surface of the first polysilicon layer  32  over the first portion  10  depending on the thickness of the various layers. Alternatively, both surfaces may be substantially at the same level with a minimal or no step height. 
   Referring to  FIG. 6 , a second polysilicon layer  60  is formed on the first polysilicon layer  32  over the first portion  10  and on the silicon-containing layer  50  over the second portion of the semiconductor substrate  8 . The first polysilicon layer  60  preferably has a thickness in the range from about 40 nm to about 120 nm. The second polysilicon layer  60  is preferably undoped. (The second polysilicon layer  60  is preferably doped on second portion  12 ) Features of the step, such as height and direction of the step, in the silicon-containing-layer  50  are carried over to the step on the top surface of the second polysilicon layer  60 . 
   According to the first through third embodiments of the present invention, a gate cap dielectric layer  70  is deposited on the second polysilicon layer  60 . The gate cap dielectric layer  70  typically comprises a silicon oxide, silicon nitride or a stack thereof. Preferably, the gate cap dielectric layer  70  is a silicon oxide layer (should be silicon nitride). More preferably, the gate cap dielectric layer  70  is a TEOS oxide layer (delete this sentence). The gate cap dielectric layer has a thickness in the range from about 15 nm to about 60 nm. 
   An anti-reflective coating (ARC) layer  81  and a third photoresist  83  are applied over the top surface of the gate cap dielectric layer  70 . The third photoresist  83  is subsequently lithographically patterned as shown in  FIG. 7 . The pattern in the third photoresist  83  contains at least one first gate electrode over the first portion  10  and at least one second gate electrode over the second portion  12  of the semiconductor substrate  8 . The thickness of the ARC layer  81  is preferably in the range from about 60 nm to about 120 nm. 
   According to the first embodiment of the present invention, the pattern in the third photoresist  83  is transferred into the underlying layers, specifically, into a stack comprising the ARC layer  81 , the gate cap dielectric layer  70 , the second polysilicon layer  60 , and the first polysilicon layer  32  over the first portion  12  and into a stack comprising the ARC layer  81 , the gate cap dielectric layer  70 , the second polysilicon layer  60 , and the silicon-containing layer  50  over the second portion  10  of the semiconductor substrate  8  by a third reactive ion etch (RIE) as shown in  FIG. 8 . The third RIE stops on the surface of the first gate dielectric  30  over the first portion  10  and on the surface of the metal gate layer  42  over the second portion  12  of the semiconductor substrate  8 . The remaining third photoresist  83 ′ and the ARC layer  81  are removed thereafter. 
   Referring to  FIG. 9 , a block photoresist  95  is applied and lithographically patterned to block the at least one stack of the gate cap dielectric layer  70 , the second polysilicon layer  60 , and the first polysilicon layer  32  as well as the underlying first gate dielectric  30  over the first portion  10  of the semiconductor substrate  8 . The semiconductor structure over the second portion  12  of the semiconductor substrate  8  is exposed at this point. The exposed portions of the metal gate layer  42  is etched by a fourth reactive ion etch (RIE) at this point. 
   Preferably, ion-bombardment of the second gate dielectric  40  follows the fourth etch while the semiconductor structure over the first portion  10  is covered by the fourth photoresist  95 . Inert ion species such as Ar, Xe, and Kr may be used to loosen the high-K dielectric layer portion of the second dielectric layer  40  and facilitate subsequent etching. The second dielectric layer  40  is thereafter etched by a fifth reactive ion etch (RIE). Thereafter, the block photoresist  95  is removed. 
   Referring to  FIG. 10 , the exposed portion of the first dielectric layer  30  is etched either by a wet etch or by a reactive ion etch. The resulting exemplary semiconductor structure has a first gate electrode which comprises a first gate dielectric layer  30 , a first gate conductor stack  62 , and a gate cap dielectric layer  70 . The first gate conductor stack  62  comprises a first gate polysilicon layer  32  and a second gate polysilicon layer  60 . The resulting exemplary semiconductor structure also has a second gate electrode which comprises a second gate dielectric layer  40 , a metal gate layer  42 , a second gate conductor stack  64 , and a gate cap dielectric layer  70 . The second gate conductor stack  64  comprises a silicon-containing layer  50  and a second gate polysilicon layer  60 . Preferably, the silicon-containing layer  50  is an amorphous silicon layer. 
   According to the second embodiment of the present invention, the initial processing steps corresponding to  FIGS. 1-7  are identical to those according to the first embodiment of the present invention. Thereafter, the pattern in the third photoresist  83  is transferred into the stack comprising the ARC layer  81  and the gate cap dielectric layer  70 . Unlike the first embodiment, however, the pattern transfer stops on top of the second polysilicon layer  60  after the third RIE as shown in  FIG. 11  according to the second embodiment of the present invention. The remaining third photoresist  83 ′ and the ARC layer  81  are thereafter removed. 
   Referring to  FIG. 12 , a fourth photoresist  85  is applied over the patterned gate cap dielectric layer  70  and over the underlying second polysilicon layer  60 . The fourth photoresist  85  is subsequently lithographically patterned so that the semiconductor structure over the second portion  12  of the semiconductor substrate  8  is covered while the area over the first portion  10  is exposed. Preferably, the edge of the fourth photoresist  85  extends over the boundary between the remaining second gate dielectric layer  40  and the remaining first gate dielectric layer  30  so that the boundary is underneath the patterned fourth photoresist  85 . 
   Referring to  FIG. 13 , a first gate electrode is formed by a fourth reactive ion etch (RIE) that etches the exposed portions of the second polysilicon layer  60  and the first polysilicon layer  32 . Preferably, the fourth RIE stops on the top surface of the first gate dielectric  30 . The structure under the fourth photoresist  85  is protected from the etch process. 
   Referring to  FIG. 14 , a fifth photoresist  87  is applied and lithographically patterned to cover the structure over the first portion  10  of the semiconductor substrate  8 . Preferably, the fifth photoresist  87  is patterned with enough overlap with the edge of the stack of the second polysilicon layer  60  and remaining first polysilicon layer  32  on top of the shallow trench isolation  20  such that the outer edges of the fifth photoresist  87  may be trimmed back by a trimming etch of the fifth photoresist  87 . With a controlled overlay tolerance and the trimming etch, the edge of the fifth photoresist  87  may be self-aligned to the edge of the stack of the second polysilicon layer  60  and the remaining first polysilicon layer  32  on top of the shallow trench isolation  20  as shown in  FIG. 14 . 
   Referring to  FIG. 15 , a second gate electrode is formed over the second portion  12  of the semiconductor substrate  8  by etching the stack of the second polysilicon layer  60 , a silicon-containing layer  50 , a metal gate layer  42 , and the second gate dielectric layer  40 . Preferably, ion-bombardment of the second gate dielectric layer  40  with inert ion species such as Ar, Xe, and Kr precedes the etching of the second gate dielectric layer  40 . The ion bombardment is used to loosen the high-K dielectric layer portion of the second dielectric layer  40  and thereby to facilitate subsequent etching. 
   Referring to  FIG. 16 , the firth photoresist  87  is thereafter removed and the first gate dielectric layer  30  is etched either by a wet etch or by a reactive ion etch (RIE). The resulting structure according to the second embodiment of the present invention is identical to the structure shown in  FIG. 10  according to the first embodiment of the present invention. 
   According to the third embodiment of the present invention, the initial processing steps corresponding to  FIGS. 1-7  are identical to those according to the first embodiment of the present invention. Thereafter, the pattern in the third photoresist  83  is transferred into the stack comprising the ARC layer  81  and the gate cap dielectric layer  70  in exactly the same manner as in the second embodiment of the present invention as shown in  FIG. 11 . The remaining third photoresist  83 ′ and the ARC layer  81  are thereafter removed. 
   Referring to  FIG. 17 , a fifth photoresist  87  is applied over the patterned gate cap dielectric layer  70  and over the underlying second polysilicon layer  60 . The fifth photoresist  87  is subsequently lithographically patterned so that the semiconductor structure over the first portion  10  of the semiconductor substrate  8  is covered, while the area over the second portion  12  is exposed. (A fourth photoresist has not been used yet according to the third embodiment at this point but the functional equivalence of the fifth photoresist  87  according to the third embodiment of the present invention as shown in  FIG. 17  to the fifth photoresist  87  according to the second embodiment as shown in  FIGS. 14-15  is conveyed by the same reference numeral and the same name across the second and third embodiments.) Preferably, the fifth photoresist  87  does not overlap the boundary between the remaining second gate dielectric layer  40  and the remaining first gate dielectric layer  30  so that that boundary is outside the area of the patterned fifth photoresist  87 . 
   Referring to  FIG. 18 , the second gate electrode is formed by a fourth reactive ion etch (RIE) that etches the exposed portions of the second polysilicon layer  60 , the silicon-containing layer  50 , and the metal gate layer  42 . Preferably, ion-bombardment of the second gate dielectric layer  40  with inert ion species such as Ar, Xe, and Kr is performed after the etching of the metal gate layer  42  and prior to the etching the second gate dielectric layer  40 . The ion bombardment is used to loosen the high-K dielectric layer portion of the second dielectric layer  40  and thereby to facilitate subsequent etching. The second dielectric layer  40  is subsequently etched by another reactive ion etch. The structure under the fifth photoresist  87  is protected from the etch process. 
   Referring to  FIG. 19 , a fourth photoresist  85  is applied and lithographically patterned to cover the structure over the second portion  12  of the semiconductor substrate  8 . Preferably, the fourth photoresist  85  is patterned with enough overlap with the edge of the stack of the second polysilicon layer  60  and remaining first polysilicon layer  32  on top of the shallow trench isolation  20  such that the outer edges of the fourth photoresist  85  may be trimmed back by a trimming etch of the fourth photoresist  85 . With a controlled overlay tolerance and the trimming etch, the edge of the fourth photoresist  85  may be self-aligned to the edge of the stack of the second polysilicon layer  60  and remaining first polysilicon layer  32  on top of the shallow trench isolation  20  as shown in  FIG. 19 . 
   Referring to  FIG. 20 , a first gate electrode is formed over the first portion  10  of the semiconductor substrate  8  by etching the stack of the second polysilicon layer  60 , a first polysilicon layer  32 , and the first gate dielectric layer  30 . The second polysilicon layer  60  and the first polysilicon layer  32  are etched by a fifth reactive ion etch. The first gate dielectric layer  30  may be etched by a wet etch or by a reactive ion etch. The fourth photoresist  85  is thereafter removed. 
   Referring to  FIG. 21 , the resulting structure according to the third embodiment of the present invention is shown, which is identical to the structure shown in  FIG. 10  according to the first embodiment of the present invention and to the structure shown in  FIG. 16  according to the second embodiment of the present invention. 
   According to the fourth embodiment of the present invention, the initial processing steps corresponding to  FIGS. 1-6  are identical to those according to the first embodiment of the present invention. Thereafter, a sixth photoresist  65  is applied over the surface of the second polysilicon layer  60 . The sixth photoresist  65  is subsequently lithographically patterned so that the second polysilicon layer  60  is covered by the sixth photoresist over the first portion  10  of the semiconductor substrate  8  and is exposed over the second portion  12  of the semiconductor substrate  8 . (The term, “sixth photoresist” does not refer to a cumulative count of photoresists used in the fourth embodiment but is used only to distinguish the sixth photoresist  65  from the fourth and fifth photoresists in the second and third embodiments since the sixth photoresist  65  serves a different function. A fourth photoresist or a fifth photoresist is not used according to the fourth embodiment of the present invention.) The exposed portion of the second polysilicon layer  60  is recessed by a reactive ion etch as shown in  FIG. 22  while the patterned sixth photoresist  65  protects the semiconductor structure therebeneath. According to the fourth embodiment of the present invention, the thickness of the second polysilicon layer  60  is less over the second portion  12  compared to the thickness of that layer over the first portion  10  of the semiconductor substrate  10 . The sixth photoresist  65  is thereafter removed. 
   Referring to  FIG. 23 , an anti-reflective coating (ARC) layer  81  and a third photoresist  83  are applied over the top surface of the second polysilicon layer  60 . The third photoresist  83  is subsequently lithographically patterned and as shown in  FIG. 23 . The pattern in the third photoresist  83  contains at least one first gate electrode over the first portion  10  and at least one second gate electrode over the second portion  12  of the semiconductor substrate  8 . The thickness of the ARC layer  81  is in the range from about 60 nm to about 120 nm. 
   Referring to  FIG. 24 , the pattern in the third photoresist  83  is transferred into the underlying layers, specifically, into a stack comprising the ARC layer  81 , into the second polysilicon layer  60 , and partly into the first polysilicon layer  32  over the first portion  12  and into a stack comprising the ARC layer  81 , the second polysilicon layer  60 , the silicon-containing layer  50 , and the metal gate layer  42  over the second portion  10  of the semiconductor substrate  8  by a third reactive ion etch (RIE). Preferably, the third RIE stops on the second gate dielectric layer  40  over the second portion  12  of the semiconductor substrate  8 . Also preferably, the third RIE stops on top of first gate dielectric over the first portion  10  of the semiconductor substrate  8 . 
   Preferably, a high temperature chemical driven plasma etch is used to remove the second gate dielectric layer  40 . The temperature is about 150 C to 300 C. The plasma etch process used here should leave the first gate dielectric layer  30  un-attacked. 
   Referring to  FIG. 25 , the remaining third photoresist  83 ′ and the ARC layer  81  are removed. The resulting exemplary semiconductor structure has a first gate electrode which comprises a first gate dielectric layer  30 , and a first gate conductor stack  62 . The first gate conductor stack  62  comprises a first gate polysilicon layer  32  and a second gate polysilicon layer  60 . The resulting exemplary semiconductor structure also has a second gate electrode which comprises a second gate dielectric  40 , a metal gate layer  42 , and a second gate conductor stack  64 . The second gate conductor stack  64  comprises a silicon-containing layer  50  and a second gate polysilicon  60 . Preferably, the silicon-containing layer  50  is an amorphous silicon layer. Except for the composition of the first polysilicon layer by two layers and the absence of a gate cap dielectric layer, the structure shown in  FIG. 25  according to the fourth embodiment of the present invention is identical to the structures according to the first through third embodiments of the present invention at equivalent stages. 
   While the invention has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the invention is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the invention and the following claims.