Abstract:
The present invention provides a semiconductor device which can reduce consumption electric power even though high integration and technologies such as microfabrication further proceeds in future and a method of manufacturing the same. The present invention comprises a semiconductor substrate, a transistor formed on said semiconductor substrate, a first electric element electrically connected to said transistor, and a second electric element electrically connected to said first electric element, wherein said first electric element and said second electric element are connected in such way that at least two planes parallel with said semiconductor substrate surface and passing through both of said first electric element and said second electric element.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device of DRAM (Dynamic Random Access Memory) and the like, and a method for manufacturing same, more particularly a semiconductor device comprising electric elements such as a capacitance element, bit contact, etc. and a manufacturing the same. 
         [0003]    2. Description of the Related Art 
         [0004]    Generally a memory cell included in DRAM and a line consists of electric elements such as a transistor for memory cells, a cell contact, a capacitance element, abit contact, abit line (Japanese Patent Application publication 2005-72176). 
         [0005]      FIG. 53  is a schematic sectional diagram explaining the memory cells in the conventional DRAM. 
         [0006]    As shown in  FIG. 53 , the MOS field-effect transistor  100  formed on the semiconductor substrate  1  such as semiconductor device silicon substrate. This MOS field-effect transistor  100  functions as a transistor for memory cells. 
         [0007]    A cell contact  2  electrically connected to said MOS field-effect transistor  100  is formed on the upper layer said MOS field-effect transistor  100 . 
         [0008]    A capacitance contact  3  electrically connected to said cell contact  2  if formed on the upper layer of said cell contact  2 . 
         [0009]    A capacitance element  400  electrically connected to said capacitance contact  3  is formed on the upper layer of said capacitance contact  3 . 
         [0010]    The side face of said cell contact  2 , the side face of said capacitance contact  3 , the side face of said capacitance element  400  are respectively insulated by first interlayer insulation film  5 , the second interlayer insulation film  6  and the third interlayer insulator  7 . These interlayer insulators are formed of silicon oxide and the like. 
         [0011]    Said capacitance element  400  comprise an upper electrode  8  formed of TiN, a capacitance film  9  formed of hafnium oxide and aluminum oxide, and a lower electrode  10  formed of TiN. 
         [0012]    Said cell contact  2  and said capacitance contact  3  are formed polysilicon containing impurity. 
         [0013]    And a TiSi layer  11  is formed on the upper end surface of said capacitance contact  3 . 
         [0014]    While, as shown in  FIG. 53 , a cell contact  40  electrically connected to said MOS field-effect transistor  100  is formed on the upper layer of said MOS field-effect transistor  100 . 
         [0015]    A bit contact  41  electrically connected to said cell contact  40  is formed on the upper layer of said cell contact  40 . 
         [0016]    A bit line  43  electrically connected to said bit contact  41  is formed on the upper layer of said bit contact  41 . 
         [0017]    A side face of said cell contact  40 , side of a said face of said bit contact  41 , and a side face of said bit line  43  are insulated with first interlayer insulation film  5  and second interlayer insulation film  6  respectively. 
         [0018]    Further, a WSi 2  layer  42  is formed on an upper end face of said cell contact  40 . 
         [0019]      FIG. 54  is a schematic sectional diagram showing said second interlayer insulation film  6  and said third interlayer insulation film  7  crossed with plane parallel with said semiconductor substrate  1  in view of normal direction with said semiconductor substrate  1 . 
         [0020]    A circular shape  51  expresses the upper end face of said capacitance contact  3 , and an oval shape  50  expresses the lower end face of said capacitance element  400 . 
         [0021]    Thus said capacitance contact  3  and said capacitance element  400  are electrically connected. 
         [0022]    Said cell contact  40  and said bit contact  41  are same. 
         [0023]    However, with the recent technical progress of high integration and microfabrication of semiconductor devices such as DRAM, the contact area between said capacitance contact  3  and said capacitance element  400 , and the contact area between said cell contact  40  and said bit contact  41  tend to be reduced. 
         [0024]    When said contact areas become reduced, the resistance against electric current between said capacitance contact  3  and said capacitance element  400  and the resistance against electric current between said cell contact  40  and said bit contact  41  become increased and as a result electric power consumption of obtained semiconductor devices of DRAM becomes increased. There was such problem. 
         [0025]    Further, as shown in  FIG. 54  explained above, some cases are that the upper end  51  of said capacitance contact  3  and the lower end  50  of said capacitance element  400  are not superimposed to each other as designed, thereby for example as shown by  FIG. 55 , the upper end  51  of said capacitance contact  3  and the lower end  50  of said capacitance  400  are not connected without corresponding to each other. 
         [0026]    In these cases, the contact area between said capacitance contact  3  and said capacitance element  400  becomes smaller, thereby obtained consumption electric power becomes larger. 
       BRIEF SUMMARY OF THE INVENTION 
       [0027]    An object of the present invention is to provide a semiconductor device that can keep the electric power consumption low even if technologies such as high integration and microbabrication proceed in future, and a method of manufacturing the same. 
         [0028]    That means, the present invention provides
   [1] a semiconductor device comprising:   
 
         [0030]    a semiconductor substrate; 
         [0031]    a transistor formed on the said semiconductor substrate; 
         [0032]    a first electric element electrically connected to said transistor; and 
         [0033]    a second electric element electrically connected to said first electric element; 
         [0034]    wherein said first electric element and said second electric element are connected in such say that at least two planes are parallel to said semiconductor substrate surface and passing through both of said first electric element and said second electric element. 
       And the present invention provides 
       [0000]    
       
         [2] a semiconductor device comprising: 
       
     
         [0036]    a semiconductor substrate; 
         [0037]    a transistor formed on said semiconductor substrate; 
         [0038]    a cell contact electrically connected to said transistor; 
         [0039]    a capacitance contact electrically connected to said cell contact; and 
         [0040]    a capacitance element electrically connected to said capacitance contact, 
         [0041]    wherein said capacitance contact and said capacitance element are connected in such way that at least two planes are parallel to said semiconductor substrate surface and passing through both of said capacitance contact and said capacitance element. 
         [0042]    And the present invention provides
   [3] a semiconductor device according to the above [2], wherein a connection surface of said capacitance contact and said capacitance element comprises a connection portion in parallel direction with said semiconductor substrate surface and a connection portion in perpendicular direction with said semiconductor substrate surface.   
 
         [0044]    And the present invention provides
   [4] a semiconductor-device according to any one of the above [2] to [3], wherein said capacitance contact comprises at least one step (A) at end portion connected to said capacitance element, said capacitance element is assembled in such way that said capacitance element is electrically connected to at least one portion of said step (A).   
 
         [0046]    And the present invention provides
   [5] a semiconductor device according to any one of the above [2] to [4], wherein said capacitance element comprises a lower electrode, a capacitance film and an upper electrode.   
 
         [0048]    And the present invention provides
   [6] a method of manufacturing a semiconductor device in which a capacitance element electrically connected to a transistor is formed on an upper layer of said transistor formed on a semiconductor substrate comprising steps of:   
 
         [0050]    (a) forming a transistor on the semiconductor substrate; 
         [0051]    (b) forming a first interlayer insulation film covering said transistor, 
         [0052]    (c) forming a cell contact electrically connected to said transistor in said first interlayer insulation film, 
         [0053]    (d) forming a second interlayer insulation film covering said first interlayer insulation film and said cell contact, 
         [0054]    (e) forming a capacitance contact electrically connected to said cell contact in said second interlayer insulation film, 
         [0055]    (f) forming a third interlayer insulation film covering said second interlayer insulation film and said capacitance contact, 
         [0056]    (g) etching at least one selected from a group of said capacitance contact, said second interlayer insulation film and said third interlayer insulation film in perpendicular direction of said semiconductor substrate, and 
         [0057]    (h) forming a capacitance element comprising a portion electrically connected in parallel direction with said semiconductor substrate, and a portion electrically connected to said semiconductor substrate in perpendicular direction, with respect to said capacitance contact. 
         [0058]    And the present invention provides
   [7] a method of manufacturing a semiconductor device according to the above [6], wherein the step (h) of forming said capacitance element comprises a step of forming a lower electrode, a capacitance film and an upper electrode.   
 
         [0060]    And the present invention provides
   [8] a semiconductor device comprising:   
 
         [0062]    a semiconductor substrate; 
         [0063]    a transistor formed on said semiconductor substrate; 
         [0064]    a cell contact electrically connected to said transistor; 
         [0065]    a bit contact electrically connected to said cell contact; and 
         [0066]    a bit line electrically connected to said bit contact; 
         [0067]    wherein said cell contact and said bit contact are connected in such way that at least two planes are parallel with said semiconductor substrate surface and passing through both of said cell contact and said bit contact. 
         [0068]    The present invention provides
   [9] a semiconductor device according to the above [8], wherein a connection surface between said cell contact and said bit contact has a connection portion parallel with said semiconductor substrate surface, and a connection portion perpendicular with said semiconductor substrate surface.   
 
         [0070]    The present invention provides
   [10] a semiconductor device according to any one of the above [8] to [9], wherein said cell contact comprises at least one step (A) at end portion connected to said bit contact, and said bit contact is assembled so as to be electrically connected to at least one portion.   
 
         [0072]    The present invention provides
   [11] a method of manufacturing a semiconductor device in which a bit line electrically connected to a transistor is formed on an upper layer of said transistor formed on a semiconductor substrate comprising steps of:   
 
         [0074]    (a) forming a transistor on the semiconductor substrate; 
         [0075]    (b) forming a first interlayer insulation film covering said transistor, 
         [0076]    (c) forming a cell contact electrically connected to said transistor in said first interlayer insulation film, 
         [0077]    (d) forming a second interlayer insulation film covering said first interlayer insulation film and said cell contact, 
         [0078]    (e) etching at least one selected from a group of said cell contact, said first interlayer insulation film and said second interlayer insulation film in perpendicular direction of said semiconductor substrate, 
         [0079]    (f) forming a bit contact comprising a portion electrically connected in parallel direction with said semiconductor substrate, and a portion electrically connected to said semiconductor substrate in perpendicular direction, with respect to said cell contact, and 
         [0080]    (g) forming a bit line electrically connected to said bit contact. 
         [0081]    With the present invention, provided area semiconductor device that can keep the electric power consumption low even if technologies such as high integration and microfabrication proceed in future, and a method of manufacturing the same. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0082]    The above and other objects and features of the invention will appear more fully hereinafter from a consideration of the following description taken in connection with the accompanying drawing wherein one example is illustrated by way of example, in which; 
           [0083]      FIG. 1  is a schematic sectional diagram explaining a first embodiment related to a semiconductor device of the present invention; 
           [0084]      FIG. 2  is a schematic sectional diagram explaining a second embodiment related to a semiconductor device of the present invention; 
           [0085]      FIG. 3  is an enlarged schematic sectional diagram explaining a connection portion between said capacitance contact and said capacitance element; 
           [0086]      FIG. 4  is a schematic sectional diagram showing a modified example of a connection portion between the capacitance contact and the capacitance element; 
           [0087]      FIG. 5  is a schematic sectional diagram showing a modified example of a connection portion between the capacitance contact and the capacitance element; 
           [0088]      FIG. 6  is a schematic sectional diagram explaining each portion of the capacitance contact and the capacitance element; 
           [0089]      FIG. 7  is a schematic sectional diagram explaining each portion of the capacitance contact and the capacitance element; 
           [0090]      FIG. 8  is a schematic sectional diagram explaining a third embodiment related to a semiconductor device of the present invention; 
           [0091]      FIG. 9  is a schematic sectional diagram explaining a forth embodiment related to a semiconductor device of the present invention; 
           [0092]      FIG. 10  is a schematic sectional diagram explaining a fifth embodiment related to a semiconductor device of the present invention; 
           [0093]      FIG. 11  is a schematic sectional diagram explaining a sixth embodiment related to a semiconductor device of the present invention; 
           [0094]      FIG. 12  is a schematic sectional diagram explaining a modified example of a connection portion between a cell contact and a bit contact; 
           [0095]      FIG. 13  is an schematic sectional diagram explaining a modified example of a connection portion between a cell contact and a bit contact; 
           [0096]      FIG. 14  is a schematic sectional diagram explaining a sixth embodiment related to a semiconductor device of the present invention; 
           [0097]      FIG. 15  is a schematic sectional diagram explaining a seventh embodiment related to a semiconductor device of the present invention; 
           [0098]      FIG. 16  is as schematic sectional diagram explaining each portion of a cell contact and a bit contact; 
           [0099]      FIG. 17  is a schematic sectional diagram explaining an eighth embodiment related to a semiconductor device of the present invention; 
           [0100]      FIG. 18  is a schematic sectional diagram explaining a ninth embodiment related to a semiconductor device of the present invention; 
           [0101]      FIG. 19  is a schematic sectional diagram explaining a process of forming a MOS field-effect transistor on the semiconductor substrate; 
           [0102]      FIG. 20  is a schematic sectional diagram explaining a process of forming a cell contact; 
           [0103]      FIG. 21  is a schematic sectional diagram explaining a process of forming a cell contact; 
           [0104]      FIG. 22  is a schematic sectional diagram explaining a process of forming a cell contact; 
           [0105]      FIG. 23  is a schematic sectional diagram explaining a process of forming a capacitance contact; 
           [0106]      FIG. 24  is a schematic sectional diagram explaining a process of forming a capacitance contact; 
           [0107]      FIG. 25  is a schematic sectional diagram explaining a process of forming a capacitance contact; 
           [0108]      FIG. 26  is a schematic sectional diagram explaining a process of etching a capacitance contact, a second interlayer insulation film and a third interlayer insulation film in a normal direction with the semiconductor substrate; 
           [0109]      FIG. 27  is a schematic sectional diagram explaining a process of forming a contact hole of a first embodiment; 
           [0110]      FIG. 28  is a schematic sectional diagram explaining a process of forming a contact hole of a first embodiment; 
           [0111]      FIG. 29  is a schematic sectional diagram explaining a process of forming a contact hole of a first embodiment; 
           [0112]      FIG. 30  is a schematic sectional diagram explaining a process of forming a contact hole of a first embodiment. 
           [0113]      FIG. 31  is a schematic sectional diagram explaining a process of forming a contact hole, a modified example of the contact hole of the first embodiment; 
           [0114]      FIG. 32  is a schematic sectional diagram explaining a process of forming a contact hole, a modified example of the contact hole of the first embodiment; 
           [0115]      FIG. 33  is a schematic sectional diagram explaining a process of forming a contact hole, a modified example of the contact hole of the first embodiment; 
           [0116]      FIG. 34  is a schematic sectional diagram explaining a process of forming a contact hole, a modified example of the contact hole of the first embodiment; 
           [0117]      FIG. 35  is a schematic sectional diagram explaining a process of forming a contact hole, a modified example of the contact hole of the first embodiment; 
           [0118]      FIG. 36  is a schematic sectional diagram explaining a process of forming a contact hole, a modified example of the contact hole of the first embodiment; 
           [0119]      FIG. 37  is a schematic sectional diagram explaining a process of forming a contact hole of a third embodiment; 
           [0120]      FIG. 38  is a schematic sectional diagram explaining a process of forming a contact hole of a third embodiment; 
           [0121]      FIG. 39  is a schematic sectional diagram explaining a process of forming a contact hole of a fourth embodiment; 
           [0122]      FIG. 40  is a schematic sectional diagram explaining a process of forming a contact hole of a fourth embodiment; 
           [0123]      FIG. 41  is a schematic sectional diagram explaining a process of forming a contact hole of a fourth embodiment; 
           [0124]      FIG. 42  is a schematic sectional diagram explaining a process of forming a contact hole of a fourth embodiment; 
           [0125]      FIG. 43  is a schematic sectional diagram explaining a process of forming a contact hole of a fourth embodiment; 
           [0126]      FIG. 44  is a schematic sectional diagram explaining a process of forming a contact hole of a fifth embodiment; 
           [0127]      FIG. 45  is a schematic sectional diagram explaining a process of forming a contact hole of a fifth embodiment; 
           [0128]      FIG. 46  is a schematic sectional diagram explaining a process of forming a contact hole of a fifth embodiment; 
           [0129]      FIG. 47  is a schematic sectional diagram explaining a process of forming a capacitance element of a first embodiment; 
           [0130]      FIG. 48  is a schematic sectional diagram explaining a process of forming a capacitance element of a first embodiment; 
           [0131]      FIG. 49  is a schematic sectional diagram explaining a process of forming a capacitance element of a first embodiment; 
           [0132]      FIG. 50  is a schematic sectional diagram explaining a process of forming contact cell, a bit cell and a bit line of sixth embodiment; 
           [0133]      FIG. 51  is a schematic sectional diagram explaining a process of forming contact cell, a bit cell and a bit line of sixth embodiment; 
           [0134]      FIG. 52  is a schematic sectional diagram explaining a process of forming contact cell, a bit cell and a bit line of sixth embodiment; 
           [0135]      FIG. 53  is a schematic sectional diagram showing a memory cell included in the conventional DRAM; 
           [0136]      FIG. 54  is a schematic sectional diagram showing a connection surface between a first electric element and a second electric element; and 
           [0137]      FIG. 55  is a schematic sectional diagram showing a connection surface between a first electric element and a second electric element. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0138]    Embodiments of the present invention will be described in detail with reference to drawings. 
         [0139]      FIG. 1  is a schematic sectional diagram of a first embodiment related to a semiconductor device of the present invention. 
         [0140]    A semiconductor device of the present invention has memorial cells. As shown in  FIG. 1 , a semiconductor substrate  1  of semiconductor silicon and the like is provided with an element separation insulation film  12 , and cell regions are individually divided in memory cell regions. A source drain region  13  is formed by introducing impurities into said semiconductor substrate  1  divided by this element separation insulation film  12 . And a cobalt silicide layer  14  is provided on the upper end of said source drain region  13 . 
         [0141]    Said source drain region  13  is provided with a gate electrode which is not especially shown. 
         [0142]    Like this MOS field-effect transistor  100  is formed in the semiconductor substrate  1  and functions as a transistor for memorial. 
         [0143]    A cell contact  2  electrically connected to said MOS field-effect transistor  100  through said cobalt silicide layer  14  is formed on said MOS field-effect transistor  100 . 
         [0144]    A capacitance contact  3  electrically connected to said cell contact  2  is formed on said cell contact  2 . 
         [0145]    Said capacitance contact  3  is formed of polysilicon containing impurity element, and a TiSi layer  11  is formed on the connection face with said capacitance element  400 . 
         [0146]    Said capacitance element  400  electrically connected to said capacitance contact  3  is formed on a part of the side face of this capacitance contact  3 . 
         [0147]    Said capacitance element  400  comprises an upper electrode  8  formed of TiN, a capacitance film  9  formed of hafnium oxide and aluminum oxide, and a lower electrode  10  formed of TiN. 
         [0148]    A side face of said cell contact  2 , a side face of said capacitance contact  3 , and a side face of said capacitance element  400  are insulated with each other respectively by a first interlayer insulation film  5 , a second interlayer insulation film  6 , and a third interlayer insulation film  7 . 
         [0149]    A part of the side face and a part of the bottom face of said capacitance element  400  are insulated by said second interlayer insulation film  6 . 
         [0150]    These interlayer insulation films are each formed of silicon oxide and the like. 
         [0151]    In said first embodiment as shown in  FIG. 1 , there exist at least two planes parallel to said semiconductor substrate surface and passing through both of said capacitance contact  3  as a first electric element and said capacitance element  400  as a second electric element. 
         [0152]    Specifically, there exist at least two planes parallel to said semiconductor substrate surface and passing through respectively a dot-dash line a-a, and a dot-dash line b-b in  FIG. 1 . 
         [0153]    As shown in  FIG. 53  which was explained before, a plane parallel to said semiconductor substrate surface and passing through both of said capacitance contact  3  and said capacitance element  400  is one of planes passing through a dot-dash line i-i in  FIG. 53 . 
         [0154]    In the case of said first embodiment as shown in  FIG. 1 , there exists at least one plane perpendicular to said semiconductor substrate surface and passing through both of said capacitance contact  3  and said capacitance element  400 . 
         [0155]    Specifically, there exists one plane perpendicular to said semiconductor substrate surface and passing a dot-dash line c-c in  FIG. 1 . 
         [0156]    A second embodiment shown in  FIG. 2  is a modified example of the first embodiment. 
         [0157]    Here  FIG. 2  is a schematic sectional diagram explaining a second embodiment related to the semiconductor device of the first invention and enlarged views of said capacitance element  400 , said capacitance contact  3  and said cell contact  2 . 
         [0158]    As shown in  FIG. 2 , the bottom face of said capacitance element  400  may be arranged near the bottom of said capacitance contact  3 . 
         [0159]    In this case, in said second embodiment as shown in  FIG. 2 , there exist at least two or more planes parallel to said semiconductor substrate surface and passing through both of said capacitance contact  3  as a first electric element and said capacitance element  400  as a second electric element. 
         [0160]    Specifically, at least two planes parallel to said semiconductor substrate surface and passing through respectively a dot-dash line a-a, and a dot-dash line b-b in  FIG. 2 . 
         [0161]    In the case of said second embodiment, there exists at least one plane perpendicular to said semi conductor substrate  1  surface passing both of said capacitance contact  3  and said capacitance element  400 . 
         [0162]    Specifically, there exists one plane perpendicular to said semiconductor substrate  1  surface and passing through a dot-dash line d-d in  FIG. 2 . 
         [0163]    The bottom of said capacitance element  400  may be arranged so as to correspond the bottom of said capacitance contact  3 . Further the bottom of said capacitance element  400  may be arranged so as to reach said cell contact  2  (not shown). 
         [0164]    The bottom of said capacitance element  400  is preferably located in the scope from ½ to ¾ of height of said capacitance contact on basis of the bottom face of said capacitance contact  3 . 
         [0165]      FIG. 3  is an enlarged schematic sectional diagram explaining the connection portion between said capacitance contact  3  and said capacitance element  400  in the semiconductor device shown in FIG.  1  previously described. 
         [0166]    The connection surface between said capacitance contact  3  and said capacitance element  400  includes a connection portion parallel to said semiconductor substrate  1  surface (a dot-dash line e-e) and the connection portion perpendicular to said semiconductor substrate  1  surface (a dot-dash line f-f). 
         [0167]    The connection surface between said capacitance contact  3  and said capacitance element  400  may include a connection portion parallel to said semiconductor substrate  1  surface and the connection portion perpendicular to said semiconductor substrate  1  surface as a whole. As shown in  FIG. 4 , the connection surface between said capacitance contact  3  and said capacitance element  400  may include a curved surface. As shown in  FIG. 5 , the connection surface between said capacitance contact  3  and said capacitance element  400  may have an oblique plane with respect of the semiconductor substrate  1  surface. 
         [0168]      FIG. 6  is a schematic sectional diagram explaining portions of said capacitance contact  3  and said capacitance element  40  shown in  FIG. 3 , respectively. 
         [0169]    In the first embodiment of the semiconductor device of the present invention as shown in  FIG. 6 , said capacitance contact  3  has at least one step (A) at an end portion connected to said capacitance element  400 . As shown in  FIG. 3 , at least one of these steps (A) is electrically connected to said capacitance element  400 . 
         [0170]      FIG. 7  is a schematic sectional diagram explaining a third embodiment related to the semiconductor device of the present invention and portions of said capacitance contact  3  and said capacitance element  400 , respectively. 
         [0171]    Said connection surface included in the semiconductor of the present invention is not limited to the example shown by  FIG. 3 . The connection surface with said capacitance element  400  may have at least one step (B) at end portion connected to said capacitance contact  3 . 
         [0172]    And said capacitance contact  3  has at least one step (A) at end portion connected to said capacitance element  400 . 
         [0173]    These steps (A) and (B) as shown in  FIG. 8  are complimentarily assembled, thereby said capacitance contact  3  and said capacitance element  400  are electrically connected with each other. 
         [0174]    As shown in  FIG. 8 , cross-sectional shapes of the connection surfaces of said capacitance contact  3  and said capacitance element  400 , which are formed by assembling said steps (A) and (B) may have two or more steps respectively. 
         [0175]      FIG. 9  is a schematic sectional diagram explaining a fourth embodiment related to the semiconductor device of the present invention and portions of said capacitance contact  3  and said capacitance element  400 , respectively. 
         [0176]    The cross-sectional shape of the connection surface between said capacitance contact  3  and said capacitance element  400  is not limited to the step shape exemplified by  FIGS. 3 ,  8 , etc. For example, as shown in  FIG. 9 , the cross-sectional shape of the connection surface between said capacitance contact  3  and said capacitance element  400 , may be in shape of concave and convex which are assembled with each other. 
         [0177]      FIG. 10  is a schematic sectional diagram explaining a fifth embodiment related to the semiconductor device of the present invention and portions of said capacitance contact  3  and said capacitance element  400 , respectively. 
         [0178]    A relation of the connection surface between said capacitance contact  3  and said capacitance element  400  is conversed with that of the fourth embodiment. These surface cross-sectional shapes are formed by assembling concave-convex shapes with each other. 
         [0179]    Next, different embodiments of the present invention will be described. 
         [0180]    In the above mentioned embodiments of 1st to 5th, the capacitance contact is exemplified as said first electric element and the capacitance element is exemplified as said second electric element. 
         [0181]    In the embodiments described next is a cell contact is exemplified as said first electric element and a bit contact is exemplified as said second electric element. 
         [0182]      FIG. 11  is a schematic sectional diagram explaining a sixth embodiment related to the semiconductor device of the present invention and portions of said bit contact  41  and said cell contact  40 , respectively. 
         [0183]    On the upper surface of the above mentioned MOS field-effect transistor  100  is formed with the cell contact  40  electrically connected through said cobalt silicide layer (not shown). 
         [0184]    Said cell contact  40  is formed of polysilicon containing impurity element, and WSi 2  layer  42  is formed on said bit contact  41 . 
         [0185]    Said bit contact  41  electrically connected to said cell contact  40  is formed on an upper layer and a part of a side face of said cell contact  40 . 
         [0186]    Said bit contact  41  is formed of metals including W. This bit contact  41  is provided with a bit line  43  formed of metals including W on the upper layer thereof. 
         [0187]    A side face of said cell contact  40 , a side face of said bit contact  41 , and a side face of said bit line  43  are insulated with each other by a first interlayer insulation film  5 , a second interlayer insulation film  6 , and a second interlayer insulation film  6 , respectively. 
         [0188]    A part of the side face and a part of the bottom face of said bit contact  41  are insulated by said first interlayer insulation film  5 . 
         [0189]    These interlayer insulation films are each formed of silicon oxide. 
         [0190]    In said sixth embodiment as shown in  FIG. 11 , there exist at least two planes parallel to said semiconductor substrate surface and passing through both of said cell contact  40  as a first electric element and said bit contact  41  as a second electric element. 
         [0191]    Specifically, there exist at least two planes parallel to said semiconductor substrate surface and passing through respectively a dot-dash line a-a, and a dot-dash line b-b in  FIG. 11 . 
         [0192]    Further, a connection surface between said cell contact  40  and said bit contact  41  includes a connection portion (a dot-dash line k-k) in direction of parallel to said semiconductor substrate  1  surface and a connection portion (a dot-dash line  1 - 1 ) in direction of perpendicular to said semiconductor substrate  1  surface. 
         [0193]    The connection surface between said cell contact  40  and said bit contact  40  may include a connection portion parallel to said semiconductor substrate  1  surface and the connection portion perpendicular to said semiconductor substrate  1  surface as a whole. As shown in  FIG. 12 , the connection surface between said cell contact  40  and said bit contact  41  may include a curved surface. As shown in  FIG. 13 , the connection surface between said cell contact  40  and said bit contact  41  may have an oblique plane with respect to said semiconductor substrate  1 . 
         [0194]      FIG. 14  is a schematic sectional diagram explaining a sixth embodiment related to the semiconductor device of the present invention and portions of cell contact  40 , said bit contact  41  and said bit line  43 , respectively. 
         [0195]    In the sixth embodiment of the semiconductor device of the present invention, as shown in  FIG. 14 , said cell contact  40  has at least one step (A) at an end portion connected to said bit contact  41 . As shown in  FIG. 11 , at least one of these steps (A) is electrically connected to said bit contact  41 . 
         [0196]      FIG. 15  is a schematic sectional diagram explaining a sixth embodiment related to the semiconductor device of the present invention and portions of cell contact  40 , said bit contact  41  and said bit line  43 , respectively. 
         [0197]    Said connection surface included in the semiconductor of the present invention is not limited to the example shown by  FIG. 11 . The connection surface with said bit contact  41  may have step (B) at end portion connected to said cell contact  40 . 
         [0198]    And said cell contact  40  has at least one step (A) at end portion connected to said bit contact  41 . 
         [0199]    These steps (A) and (B) as shown in  FIG. 16  are complimentarily assembled, thereby said cell contact  40  and said bit contact  41  are electrically connected with each other. 
         [0200]    As shown in  FIG. 16 , cross-sectional shapes of the connection surfaces of said cell contact  40  and said bit contact  41  which are formed by assembling said steps (A) and (B) may have two or more steps respectively. 
         [0201]      FIG. 17  is a schematic sectional diagram explaining an eighth embodiment related to the semiconductor device of the present invention. 
         [0202]    The cross-sectional shape of the connection surface between said cell contact  40  and said bit contact  41  is not limited to the step shape exemplified by  FIGS. 11 ,  16 , etc. For example, as shown in  FIG. 17 , the cross-sectional shape of the connection surface between said cell contact  40  and said bit contact  41  may be in shape of concave and convex which are assembled with each other. 
         [0203]      FIG. 18  is a schematic sectional diagram explaining a ninth embodiment related to the semiconductor device of the present invention. 
         [0204]    A relation of the connection surface between said cell contact  40  and said bit contacet  41  is conversed with that of the eighth embodiment. These surface cross-sectional shapes are formed by assembling concave-convex shapes with each other. 
         [0205]    Next a method of manufacturing the semiconductor device related to the present invention will be described. 
         [0206]      FIG. 19  is a schematic sectional diagram explaining a method of forming a MOS field-effect transistor  100  on the semiconductor substrate. 
         [0207]    A semiconductor substrate  1  of the present invention is for example a semiconductor silicon substrate. The semiconductor silicon substrate employed in the present invention is not especially limited and commercial product is usable. 
         [0208]    As shown in  FIG. 19 , first a shallow slot is formed in a semiconductor substrate  1 , and an insulation material is buried in this slot to form an isolation insulator layer  12 . 
         [0209]    Cells in a memory array region in said semiconductor substrate are individually divided by this isolation insulator layer  12 . 
         [0210]    And an impurity is introduced into said semiconductor substrate  1  divided by this isolation insulator film  12  to form a source/drain region  13 . Said source/drain region  13  is silicided by cobalt at an upper end to form cobalt silicide layer  14 . A gate electrode (not shown) corresponding to said source drain region is separately provided. 
         [0211]    Then, the predetermined surface of said isolation insulator film  12  and said MOS field-effect transistor  100  is covered with silicon nitride layer  15   
         [0212]    With these processes, said MOS field-effect transistor  100  can be formed as a transistor for memory cells. 
         [0213]      FIG. 20  is a schematic sectional diagram explaining a process of forming a cell contact  2  electrically connected to said MOS field-effect transistor  100 . 
         [0214]    As shown in  FIG. 20 , a first interlayer insulation film  5  covering said MOS field-effect transistor  100  is formed by a method for depositing insulation material such as silicon oxide on the whole surface of silicon nitride layer  15  of said MOS field-effect transistor  100 , said isolation insulator file  12  and others. 
         [0215]    Subsequently, a photo resist layer  16  is formed on said first insulation layer  5  and a resist pattern is formed by a known lithography process for a cell contact. 
         [0216]    As shown in  FIG. 21 , a contact hole  17  is formed by a selective etching to open for a cell contact electrically connected to said transistor with the resister pattern as a mask. 
         [0217]    Next, as shown in  FIG. 22 , a cell contact  2  electrically connected to said MOS field-effect transistor  100  can be formed by removing said photo resist layer  16 , and by an ashing process and a stripping process after burying polysilicon in said contact hall  17 . 
         [0218]    A length of said cell contact  2  in a direction normal to said semiconductor substrate  1  is generally in a range from 400 to 800 nm, preferably 550 to 750 nm, and more preferably 600 to 650 nm. 
         [0219]    Said polysilicon is added with p-type impurity such as boron, and n-type impurity such as phosphorus and said cell contact  2  can be passed through with electric current. 
         [0220]      FIG. 23  is a schematic sectional diagram explaining a process of forming a capacitance contact  3  electrically connected to said cell contact  2 . 
         [0221]    As shown in  FIG. 23 , a second interlayer insulation film  6  covering said cell contact  2  can be formed by a method for depositing insulation material such as silicon oxide on the whole surface of said first interlay insulator film  5  and said cell contact  2 . 
         [0222]    Subsequently, a photo resist layer  18  is formed on said second insulation layer  6  and a resist pattern is formed by a known lithography process for a capacitance contact. 
         [0223]    As shown in  FIG. 24 , a contact hole  19  is formed by a selective etching to open for a capacitance contact electrically connected to said cell contact  2  with the resist pattern as a mask. 
         [0224]    Next, as shown in  FIG. 25 , a capacitance contact  3  electrically connected to said cell contact  2  can be formed by removing said photo resist layer  18  by an ashing process and a stripping process after burying polysilicon in said contact hall  19 . 
         [0225]    Said polysilicon is added with p-type impurity such as boron, and n-type impurity such as phosphoric acid and said capacitance contact  3  can be passed through with electric current, as well as the case of said cell contact  2 . 
         [0226]    A length of said capacitance contact  3  in a direction of perpendicular to said semiconductor substrate  1  (normal direction to said semiconductor substrate surface) is generally in a range from 300 to 700 nm, preferably 400 to 600 nm, and more preferably 450 to 550 nm. 
         [0227]    The method for manufacturing said cell contact  2  and said capacitance contact  3  by one step method was explained above. However, polysilicon may be buried in series for said contact hole  17  or said contact hole  19 . 
         [0228]      FIG. 26  is a schematic sectional diagram explaining a process of etching said capacitance contact  3 , said second interlayer insulation film  6  and the third interlay insulation film  7  in a direction normal to said semiconductor substrate. 
         [0229]    With a method of depositing insulation material such as silicon oxide to the whole surface of said second interlay insulation film  6  and said capacitance contact  3  using TEOS 
         [0230]    (Terraethoxysilane) and others, the third interlayer insulation film  7  covering said capacitance contact  3  is formed as shown in  FIG. 26 . 
         [0231]    As shown in  FIG. 27 , a photo resist layer  20  is formed on said third interlayer insulation film  7  to form a resist pattern for a capacitance element by a known lithography process. 
         [0232]    With this resist pattern as a mask, the etching process is performed. 
         [0233]    Said third interlayer insulation film  7  as shown in  FIG. 27  is removed by reactive ion etching which is performed, for example, with gas for etching: CF 4 /O 2 /Ar, CHF 3 /O 2 /Ar, C 4 F 8 /O 2 /Ar, etc., under conditions of Ar: 20 volume %, temperature: 40 to 60° C., pressure: 50 to 100 m torr, high frequency power: 3000 W, bias: 2000 W. 
         [0234]    Further, polysilicon of said capacitance contact  3  as shown in  FIG. 28  is partly removed by continuing the reactive ion etching. 
         [0235]    In this case, said second interlayer insulation film  6  alone is removed by reactive ion etching which is performed, for example, with gas for etching: C 4 F 8 /C 4 F 6 /O 2 /Ar, etc., flow rate: 15 ml/min. for C 4 F 8 , 10 ml/min. for C 4 F 6 , 20 ml/min. for O 2 , 150 ml/min. for Ar, pressure: 15 m torr, high frequency power: 3000 W, bias: 2000 W. And then, polysilicon of said capacitance contact  3  may be partly removed by reactive ion etching which is performed, for example, gas for etching: Cl 2 /HBr/O 2 , etc., flow rate: 10 ml/min. for Cl 2 , 180 ml/min. for HBr, 5 ml/min. for O 2 , pressure: 15 m torr, high frequency power: 3000 W, bias: 2000 W. 
         [0236]    Further, said second interlayer insulation, film  6  and a part of polysilicon of said capacitance contact  3  may be simultaneously removed by plasma etching which is performed with gas for etching: CHF 3 /CF 4 /O 2 , etc., flow rate adjusted to: 100 ml/min. for these gases in total and 30 to 40 ml/min. for O 2 , frequency: 13.56 MHz. 
         [0237]    Next, the contact hole  21  as shown in  FIG. 28  is obtained by removing said resist pattern by ashing process, stripping process, etc. 
         [0238]    Depth of said contact hole  21  is in a range, preferably from 1 to 5 μm, more preferably 2 to 4 μm with respect of a distance between upper end of said third interlayer insulation film  7  to bottom face of said contact hole  21 . 
         [0239]      FIG. 29  is a schematic sectional diagram explaining a process of forming a contact hole  22  of second embodiment by etching said capacitance contact  3 , said second interlayer insulation film  6  and said third interlayer insulation film  7  in a direction normal to said semiconductor substrate. 
         [0240]    By the same process of obtaining the contact hole  21  as shown in  FIG. 28  through the same etching process as explained above, etching of said contact hole  21  and said capacitance contact  3  is continued. With this process, the bottom face of said contact hole  22  is provided in such way that it is located near said first interlayer insulation film  5 . 
         [0241]    Next, said resist pattern is removed by ashing process, stripping process, etc. to obtain the contact hole  22  as shown in  FIG. 30 . 
         [0242]      FIG. 31  is a schematic sectional diagram explaining a process of forming a contact hole  21   a  of the contact hole  21  of the first embodiment. 
         [0243]    By the same process of obtaining the contact hole  21  as shown in  FIG. 31 , through the same etching process as explained above, etching of said contact hole  21   a  and said capacitance contact  3  is continued. 
         [0244]    In this case, a shape of the bottom face of the contact hole  21   a  can be adjusted to substantially sphere by increasing a flow rate of the etching gas. The same as above. 
         [0245]    Preferably, said capacitance contact  3  and said second interlayer insulation layer  6  are simultaneously etched. With this process, curved face can be included in inner surface of said contact hole  21   a  as shown in  FIG. 32 . 
         [0246]      FIG. 33  is a schematic sectional diagram explaining a process of a contact hole  21   b  of another modification example of forming of said first embodiment. 
         [0247]    By the same process of obtaining the contact hole  21  as shown in  FIG. 27 , through the same etching process as explained above, etching of said contact hole  21   b  and said capacitance contact  3  is continued. 
         [0248]    In this case, an etching speed of said capacitance contact  3  and said second interlayer insulation film  6  can be made substantially same by plasma etching which is performed with gas for etching: CHF 3 /CF 4 /O 2 , etc., flow rate adjusted to: 100 ml/min. for these gases in total, frequency: 13.56 MHz. 
         [0249]    With this, the bottom portion of said contact hole  21   n  as shown in  FIG. 34  can be kept in substantially horizontal position. 
         [0250]    Next, for example, a portion of said second interlayer insulation film  6  can be etched more faster than that of said capacitance contact  6  by decreasing the component rate of etching gas, CF 4 ., thereby forming slope included in the inner surface of said contact hole  21  as shown in  FIG. 35 . It is similar processing as follows. 
         [0251]      FIG. 36  is a schematic sectional diagram explaining a process of forming a contact hole  24  of said third embodiment by etching the said capacitance contact  3 , said second interlayer insulation film  6  and third interlayer insulation film in a direction normal to said semiconductor substrate. 
         [0252]    A photo resist layer  23  is formed on said contact hole  21  and said third interlayer insulation film  7  as in above mentioned  FIG. 28 . Next, a resist pattern is formed by a known lithography process for capacitance element. As a result, said contact hole  21  is buried by said photo resist layer  23  as shown in  FIG. 36 . 
         [0253]    With this resist pattern as a mask, etching process can be performed. 
         [0254]    Said third interlayer insulation film  7  as shown in  FIG. 36  can be removed by plasma etching using said etching gas. 
         [0255]    Subsequently, polysilicon of said capacitance contact  3  can be partly removed as shown in  FIG. 36  by continuing said plasma etching. 
         [0256]    Next, said resist pattern is removed by ashing process, stripping process, and others to obtain contact hole  24  as shown in  FIG. 38 . 
         [0257]      FIG. 39  is a schematic sectional diagram explaining a process of forming a contact hole  26  of fourth embodiment by etching said capacitance contact  3  and said third interlayer insulation film  7  in a direction normal to said semiconductor substrate. 
         [0258]    With a method of depositing insulation material such as silicon oxide to the whole surface of said second interlay insulation film  6  and said capacitance contact  3  using TEOS (Terraethoxysilane) and others, the third interlayer insulation film  7  covering said capacitance contact  3  is formed as shown in  FIG. 25 . 
         [0259]    As shown in  FIG. 39 , a photo resist layer  25  is formed on said third interlayer insulation film  7  to form a resist pattern for a capacitance element by a known lithography process. 
         [0260]    With this resist pattern as a mask, the etching process is performed. 
         [0261]    Said third interlayer insulation film  7  as shown in  FIG. 39  can be removed by plasma etching using above mentioned etching gas. 
         [0262]    Further, polysilicon of said capacitance contact  3  as shown in  FIG. 40  can be partly removed by continuing said plasma etching. 
         [0263]    With these operations, a contact hole  26  can be formed. 
         [0264]    Next, after said resist pattern is removed by ashing process, stripping process, and others, the photo resist layer  27  can be buried in said contact hole  26  and hardened as shown in  FIG. 41 . 
         [0265]    Further, as shown in  FIG. 42 , a photo resist layer  28  is formed on said third interlayer insulation film  7  and said photo resist layer  27  to form a resist pattern for a capacitance element by a known lithography process. 
         [0266]    With this resist pattern as a mask, the etching process is performed. 
         [0267]    Said third interlayer insulation film  7  as shown in  FIG. 42  can be removed by plasma etching using above mentioned etching gas. 
         [0268]    Next, said resist pattern is removed by ashing process, stripping process, and others, to obtain a contact hole  29 . 
         [0269]      FIG. 44  is a schematic sectional diagram explaining a process of forming a contact hole  30  of fourth embodiment by etching said capacitance contact  3  and said third interlayer insulation film  7  in a direction normal to said semiconductor substrate. 
         [0270]    With a method of depositing insulation material such as silicon oxide to the whole surface of said second interlayer insulation film  6  and said capacitance contact  3  using TEOS (Terraethoxysilane) and others, the third interlayer insulation film  7  covering said capacitance contact  3  is formed as shown in  FIG. 25 . 
         [0271]    Subsequently a photo resist layer  31  is formed on said third interlayer insulation film  7  to form a resist pattern for a capacitance element by a known lithography process. 
         [0272]    With this resist pattern as a mask, the etching process is performed. 
         [0273]    Said third interlayer insulation film  7  as shown in  FIG. 44  can be removed by plasma etching using above mentioned etching gas. 
         [0274]    Further, said second interlayer insulation film  6  alone can be removed without removing polysilicon of said capacitance contact  3  as shown in  FIG. 45  by previously mentioned reactive ion etching. With these operations, a contract hole  30  can be formed. 
         [0275]    And after said resist pattern is removed by ashing process, stripping process and others, said contact hole  30  can be obtained as shown in  FIG. 46 . 
         [0276]    Next, a process forming the capacitance element will be explained. 
         [0277]      FIG. 47  is a schematic sectional diagram explaining a process of forming said capacitance element  400  of said first embodiment by forming a lower electrode  10 , a capacitance film  9  and an upper electrode  8  inside said capacitance contact hole  21 . 
         [0278]    First, an oxide film inside the contact hole  21  is removed as shown in  FIG. 47 . 
         [0279]    Next, under conditions of temperature in a range from 600 to 700° C., Ti is deposited inside said contact hole  21  by a CVD method with thickness in a range from 5 to 20 nm, preferably 10 to 20 nm. Further under the same temperature, TiN is deposited by a CVD method with thickness in a range from 10 to 30 nm, preferably 15 to 25 nm. 
         [0280]    And then, TiSi layer  11  and the lower electrode  10  is formed on said capacitance contact  3 , as shown in  FIG. 48 , by etch backing said TiN while supplying Cl 2  at a speed of 40 ml/min. and Ar at 40 ml/min. under a pressure of 1.0×10 −2  torr. 
         [0281]    Subsequently, by a CVD method, a capacitance film  9  can be formed by depositing Al 2 O 3  on a surface of said lower electrode  10  with thickness in a range from 2 to 5 nm, and HfO 2  in a range from 3 to 6 nm. 
         [0282]    Next, the upper electrode  8  is formed by depositing TiN on a surface of said capacitance film  9  under conditions of 450 to 550° C. by a CVD method. 
         [0283]    With this process, a capacitance element  400  electrically connected to said capacitance contact  3  can be formed as shown in  FIG. 49 . 
         [0284]    With respect to said capacitance contact  3 , said capacitance element  400  includes a portion electrically connected in a normal direction with said semiconductor substrate (a dot-dash line g-g) and a portion electrically connected in a parallel direction with said semi conductor substrate (a dot-dash line h-h). 
         [0285]    In the same way, with respect the contact hole as shown by the second embodiment to the fifth embodiment, the capacitance element comprising the TiSi layer  11 , the lower electrode  10 , the capacitance film  9  and the upper electrode  8  can be formed. 
         [0286]    Thus, semiconductor device according to the first embodiment to the fifth embodiment of the present invention is manufactured. 
         [0287]      FIG. 50  is a schematic sectional diagram explaining a process of forming said cell contact  40 , said bit contact  41 , and said bit line  43  which are included in the sixth embodiment of the present invention. 
         [0288]    A process of forming the contact cell  40  on the first interlayer insulation film  5  covering said MOS field-effect transistor  100  is the same with that of the first embodiment of the present invention as mentioned previously. 
         [0289]    By a method of depositing insulation material such as silicon oxide on the whole surface of said first interlayer insulation film  5  and said cell contact  40 , an inter layer insulation film  60  covering said cell contact  40  can be formed. 
         [0290]    Next, a photo resist layer is formed on said interlayer insulation film  60  (not shown), and a resist pattern is formed for capacitance contact by a known lithography process. 
         [0291]    With this resist patter as a mask, a contact hole  44  is opened by selective etching for the bit contact  41  electrically connected to said cell contact  40  as shown in  FIG. 50 . 
         [0292]    Subsequently, after removing the oxide film inside said contact hole  44 , a WSi2 layer  42  is formed on the boundary surface of the cell contact  40  at the bottom face of said contact hole  44 , and the bit contact  41  is formed as shown in  FIG. 51  by burying W in said contact hole. 
         [0293]    Similarly, a bit line  43  formed of W electrically connected to said bit contact  41  is formed as shown in  FIG. 52 . 
         [0294]    Thus, with this method, semiconductor device according to the sixth embodiment to the ninth embodiment of the present invention as previously described can be manufactured. 
         [0295]    With the semiconductor device of the present invention obtained in this way, a connection area between said capacitance element and said capacitance contact is larger than that of the conventional semiconductor device, thereby electric power saving is realized. 
         [0296]    The present invention is not limited to the above described embodiments, and various variations and modifications may be possible without departing from the scope of the present invention. 
         [0297]    This application is based on the Japanese Patent application No. 2006-192226 filed on Jul. 12, 2006, entire content of which is expressly incorporated by reference herein.