Abstract:
Test functions are expanded by adopting a test part, and an increase in circuit scale is reduced by adding the test part. A semiconductor integrated circuit comprises a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in how to update X addresses, Y addresses, and bank addresses. A variety of addressing modes provided for testing contribute to the expansion of BIST-based test functions. Since the self-test part has plural test sequencers corresponding to plural test modes, the area of the semiconductor integrated circuit can be easily reduced in comparison with program-controlled general-purpose sequencers requiring memory for storing programs.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a Continuation of U.S. application Ser. No. 10/892,298 filed Jul. 16, 2004. Priority is claimed based on U.S. application Ser. No. 10/892,298 filed Jul. 16, 2004, which claims the priority of Japanese application 2003-304277 filed on Aug. 28, 2003. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to BIST (built-in self-test) technology and more particularly to technology effectively applied to a semiconductor integrated circuit in which a test circuit for testing memory is built in on a chip. 
         [0003]    As a memory having a BIST circuit, patent publication 1 describes a semiconductor integrated circuit having a BIST circuit capable of high-speed processing by command sequencers and internal clock generating circuits. Patent publication 2 describes semiconductor storage with a built-in BIST circuit comprising a test clock generator, an address counter, and a sequencer. 
         [0000]    [Patent publication 1] Japanese Unexamined Patent Publication No. Hei 11(1999)-329000
 
[Patent publication 2] Japanese Unexamined Patent Publication No. Hei 10(1998)-162600
 
       SUMMARY OF THE INVENTION 
       [0004]    The patent publication 1, which discloses sequencer-based BIST technology, is limited in test sequences and does not cover a variety of test sequences. In patent publication 2, the circuit scale increases since a PLL circuit is adopted for a test clock generator. This is because the PLL circuit requires a voltage controlled oscillator and a D/A converter that require voltage controlled current source and the like. 
         [0005]    The inventors discovered that since much time is required for data retention tests in semiconductor storages such as DRAM, if a high-speed tester is used for the tests, wait time in the date retention tests becomes useless, resulting in higher test costs. Accordingly, the inventors studied the use of a low-speed tester and making up for functional lacks by a BIST circuit built in on a chip. 
         [0006]    An object of the present invention is to provide a semiconductor integrated circuit that expands test functions by adopting a self-test unit such as a BIST circuit, and reduces an increase in circuit scale by adding the self-test unit. 
         [0007]    The aforementioned and other objects and novel characteristics of the present invention will become apparent from the description of this specification and the accompanying drawings. 
         [0008]    The typical disclosures of the invention will be summarized in brief as follows. 
       &lt;A Variety of Addressing Modes&gt; 
       [0009]    A semiconductor integrated circuit according to the present invention comprises a memory ( 5 ) that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part ( 3 ) that tests the memory in response to commands. The self-test part has plural modes of generating access addresses to test the memory. The plural modes of generating access addresses differ from each other in the modes of updating X addresses, Y addresses, and bank addresses. In other words, the self-test part has an address counter ( 35 ) accommodating plural addressing modes that are different in how to update X addresses, Y addresses, and bank addresses. A variety of addressing modes provided for testing contribute to the expansion of BIST-based test functions. The memory banks have plural dynamic-type memory cells arrayed in matrix, and the semiconductor integrated circuit is configured as synchronous DRAM, for example. 
         [0010]    The modes of generating access addresses are plural modes selected from among single bank X scanning that updates bank addresses after one round of X addresses, single bank Y scanning that updates bank addresses after one round of Y addresses, and multi-bank X scanning that updates X addresses after one round of bank addresses. 
       &lt;Sequencer for Timing Generation&gt; 
       [0011]    The self-test part has plural test sequencers ( 31 ) corresponding to plural test modes. The plural test sequencers are selected according to the result of decoding the commands. By providing plural sequencers each corresponding to each test timing, the area of the semiconductor integrated circuit can be easily reduced in comparison with program-controlled general-purpose sequencers requiring memory for storing programs. In short, it is easy to add and delete individual sequencers according to the necessity of test timing, customizing becomes possible for each of the products and kinds of semiconductor integrated circuits, and area overhead can be reduced. 
       &lt;Write Data Generating Circuit&gt; 
       [0012]    The semiconductor integrated circuit according to the present invention includes a write data generating circuit ( 36 ) that generates write data for test in plural modes by using a shift register having a feedback loop. The write data generating circuit includes: a shift register (QW 0  to QW 3 ) of plural bits; a first feedback loop ( 61 ) through which the output of an output side start storage stage (QW 0 ) of the shift register is fed back to the input of an output side end storage stage (QW 3 ); a first selector ( 62 ) that selectively feeds back the output of the output side start storage stage of the shift register to the input of the start storage stage; and a second selector ( 64 ) that selects between the output and input of the output side start storage stage of the shift register. Since the write data generating circuit uses the shift register having the feedback loop, in comparison with general-purpose pattern generating circuits configured to selectively generate given patterns upon the loading of control data stored in ROM as typified by ALPG (algorithmic pattern generator), write data of a variety of patterns can be easily generated on a comparatively small logical scale. 
       &lt;Clock Generating Circuit&gt; 
       [0013]    A clock generating circuit ( 32 ) is adopted that generates a clock signal for test (CKIN) supplied to the memory. The clock generating circuit comprises: a ring oscillator ( 70 ) capable of changing the number of gate stages of oscillation loop; changeable frequency dividers ( 71  to  73 ) that frequency-divide the output of the ring oscillator; and an oscillation frequency control circuit that controls the number of gate stages of the oscillation loop based on a result of comparison between predetermined output of the changeable frequency dividers and an external clock signal. The external clock signal (CKEX) may be a clock signal of a relatively low frequency such as operation frequencies supported by low-speed testers. If the frequency division ratio of the clock signal used as a test clock signal is smaller than that of the clock signal (CKC) inputted to the comparator ( 74 ), the frequency of the test clock signal (CKIN) can be made higher than the low-speed clock signal (CKEX) of the tester, contributing to speedup in tests. Here, since the ring oscillator ( 70 ) capable of changing the number of gate stages of an oscillation loop is used to generate a desired frequency, in comparison with PLL circuits, circuit scale can be significantly reduced at some cost of the accuracy of frequency synchronization, contributing to reduction in chip occupation area. 
         [0014]    Specifically, the ring oscillator includes plural selectable oscillation loops that are different from each other in the number of gate stages. The oscillation frequency control circuit includes: a frequency comparator  74  that compares predetermined output of the changeable frequency dividers with the frequency of an external clock signal; and a counter  75  that increments or decrements a count value according to comparison results by the frequency comparator. A count value of the counter is used to select an oscillation loop of the ring oscillator so as to match the predetermined output of the changeable frequency dividers to the frequency of the external clock signal. 
         [0015]    Effects obtained by typical disclosures of the invention will be described in brief as follows. 
         [0016]    Test functions can be expanded by adopting a test part such as a BIST circuit into a semiconductor integrated circuit such as synchronous DRAM, and an increase in circuit scale can be reduced by adding a self-test part. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0017]      FIG. 1  is a block diagram showing a detailed example of a BIST circuit; 
           [0018]      FIG. 2  is a block diagram showing an outline of a synchronous DRAM (SDRAM) according to an embodiment of the present invention; 
           [0019]      FIG. 3  is a block diagram showing an example of a memory core included in the SDRAM; 
           [0020]      FIG. 4  is a block diagram showing an example of an address counter; 
           [0021]      FIG. 5  illustrates addressing modes by an address counter; 
           [0022]      FIG. 6  is a timing chart showing the operation timing of an address counter in SB-XSCAN, its operation timing in SB-YSCAN, and its operation timing in MB-XSCAN; 
           [0023]      FIG. 7  is a block diagram showing a configuration of test sequencers; 
           [0024]      FIG. 8  is a timing chart showing the state of a starter sequencer and the state of a tri-state buffer; 
           [0025]      FIG. 9  is a state transition diagram of starter sequencer; 
           [0026]      FIG. 10  is a logical circuit diagram showing a logical configuration of a state machine of starter sequencer; 
           [0027]      FIG. 11  is a logical circuit diagram showing a decoding part for 2 bits QS 0  and QS 1  of the state machine; 
           [0028]      FIG. 12  illustrates a timing sequence of SB-Write/Read; 
           [0029]      FIG. 13  is a diagram showing state transition of subsequencer associated with SB-Write/Read; 
           [0030]      FIG. 14  is a diagram showing state transition of a general-purpose timer of a subsequencer; 
           [0031]      FIG. 15  is a logical circuit diagram showing a logical configuration of a general-purpose timer; 
           [0032]      FIG. 16  is a logical circuit diagram showing a logical configuration of a state machine of a subsequencer; 
           [0033]      FIG. 17  illustrates a decoding part for 3 bits QC 0 , QC 1 , and QC 2  of a state machine; 
           [0034]      FIG. 18  illustrates timing sequences achieved by other plural test sequencers; 
           [0035]      FIG. 19  is a timing chart of a timing generation operation of a test sequencer; 
           [0036]      FIG. 20  is a logical circuit diagram showing an example of a write data generating circuit; 
           [0037]      FIG. 21  illustrates operation modes of the write data generating circuit by equivalent circuits; 
           [0038]      FIG. 22  illustrates some concrete examples of generating write data by the write data generating circuit; 
           [0039]      FIG. 23  is a block diagram showing a clock generating circuit; 
           [0040]      FIG. 24  is a logical circuit diagram showing a ring oscillator; 
           [0041]      FIG. 25  is a logical circuit diagram showing a frequency comparator; 
           [0042]      FIG. 26  is a timing chart showing operation waveforms of the frequency comparator; 
           [0043]      FIG. 27  is a timing chart showing clock generation operation timing by a clock generating circuit; and 
           [0044]      FIG. 28  is a diagram showing a test flow of SDRAM. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     &lt;Synchronous DRAM Incorporating a BIST Circuit&gt; 
       [0045]      FIG. 2  shows an outline of a synchronous DRAM (SDRAM) according to an embodiment of the present invention. SDRAM  1  is formed on one semiconductor board such as a single-crystal silicon by a well-known semiconductor integrated circuit manufacturing technology. The synchronous DRAM  1  includes a chip interface circuit  2 , a BIST circuit  3  as a self-test part, a selector  4 , and a memory core  5  as a memory. The chip interface circuit  2  is supplied with an address signal and a memory access control signal. When a test enable signal EN is put into an enable level by the supplied memory access control signal, test operations by the BIST circuit  3  are enabled, and the selector  4  selects a test address and a test control signal which are generated in the BIST circuit  3 , and supplies them to the memory core  5 . If the test operations on the memory core  5  by the test address and the test control signal result in an error, a fail signal FAIL rises. When the test enable signal EN is at a disable level, the selector  4  supplies the address signal and the memory access control signal which are supplied to the chip interface circuit  2 , to the memory core  5 . Thereby, the memory core  5  operates as usual. 
         [0046]      FIG. 3  shows an example of the memory core  5 . The memory core  5  has four memory banks BNK 0  to BNK 3 . Each of the memory banks BNK 0  to BNK 3  has memory cells of dynamic type arranged in matrix, and terminals for selecting the memory cells are connected to word lines and data input-output terminals are connected to bit lines. The bit lines are connected with a sense amplifier train (SA)  10  and a column selection switch train (CSW)  11 . The sense amplifier train  10  senses and amplifies storage information read into the bit lines. As external address signals used to select a memory cell, a bank address signal BA for selecting a bank, and an X, Y address signal Ai for specifying X address (row address) and column address (Y address) in the bank are supplied. A row address signal is supplied to a row address buffer (RAB)  12  and supplied to the row decoder (RDEC)  13  for selecting the word line. A column address signal is supplied to a column address buffer (CAB)  14 , and supplied to a column decoder (CDEC)  15  for selecting the column selection switch train  11 . A bit line selected by the column decoder  15  is conducted to a latch circuit (DLAT)  18  through a data control circuit (DCNT)  17 . Data read from the memory banks and latched into the latch circuit  18  is outputted as DQ from a data input-output buffer (DIO)  19 . Write data DI supplied to the data input-output buffer  19  is latched into the latch circuit  18  and supplied to the memory banks. 
         [0047]    A command decoder (CDEC)  20 , a command logic (CLOG)  21 , and a mode register (MREG)  22  are provided to control the operation of the memory core  5 . The command decoder  20  is supplied with access control signals /RAS, /CAS, and /WE, which are generally used in DRAM. Furthermore, a part of the X, Y address signal Ai is supplied to the command decoder  20  as an access command. The command decoder  20  gives a command decode signal corresponding to a combination of levels of the /RAS, /CAS, and /WE signals and the access command to the command logic  21 . The command logic  21  controls operation timing for internal circuits such as the row address decoder and the sense amplifier train. An internal clock signal used for timing control is generated by a clock generator (CPG)  24  inputting a clock signal /CKIN. Data output timing is synchronized to a delay locked loop circuit (DLL)  25  synchronizing to a clock signal /CKIN. A refresh circuit is included in a functional block of the row address buffer  12 . 
       &lt;BIST Circuit&gt; 
       [0048]      FIG. 1  shows an example of a BIST circuit  3 . In  FIG. 1 , the selector  4  of  FIG. 2  is omitted. The BIST circuit  3  includes a BIST control circuit  30 , plural test sequencers  31 , a clock generating circuit  32 , and a pattern generating circuit  33 . The pattern generating circuit  33  includes an address counter  35 , a write data generating circuit  36 , a scrambler  37 , a multiplexer (MUX)  38 , and a command encoder  39 . 
         [0049]    The chip interface circuit  2  admits control signals /CS, /RAS, /CAS, and /WE, a bank address signal BA, an X, Y address signal Ai, a clock enable signal/CKE, and an external clock signal CKEX. The external clock signal CKEX has the low-speed clock cycle time of 600 ns. /CS designates a chip select signal that selects the operation of SDRAM 1 . /RAS designates a row address strobe signal. /CAS designates a column address strobe signal. /WE designates a write enable signal. The chip interface circuit  2  enables the external clock signal CKEX when the clock enable signal /CKE is enabled, and synchronously with the external clock signal CKEX, captures other signals /CS, /RAS, /CAS, and /WE, the address signals BA and Ai. When the captured signals /CS, /RAS, /CAS, and /WE are a prescribed combination of levels, the chip interface circuit  2  assumes the enable signal EN to be at an enable level, and directs the BIST circuit  3  to enter the BIST mode. 
         [0050]    When the signal EN is at an enable level, the BIST control circuit  30  captures the control signals /RAS, /CAS, and /WE, the bank address signal BA, the X, Y address signal Ai, and the external clock signal CKEX, which are outputted from the chip interface circuit  2 . Upon recognizing the BIST mode by the signal EN, the BIST control circuit  30  successively captures a start address of the test, an initial value of write data, a sequence command, and other control information from an input route of the address signal Ai. The BIST control circuit  30  gives control information for clock generation to the clock generating circuit  32  to decide the frequency of clock signals CKIN and /CKIN for the test, gives the sequence command to the test sequencer  31 , and gives control information to the pattern generating circuit  33 . 
         [0051]    Plural test sequencers  31  are provided correspondingly to plural test modes. One test sequencer  31  corresponding to a given sequence command generates test control codes ACT, WRIT, READ, PRE, and REF according to the test operation procedure and gives them to a command encoder  39 . The command encoder  39  generates the test control signal /RAS, /CAS, or /WE according to a test control code, and gives it to the memory core  5 . In parallel with this, the test sequencer  31  controls the address counter  35  over the generation of an address pattern corresponding to the sequence command, and generates an X address signal PX, a Y address signal PY, and the bank address signal BA. The X address signal PX and the Y address signal PY are scrambled in the scrambler  37  and given to the memory core  5  by the address multiplex system by the multiplexer  38 , and the bank address signal BA is given to the memory core  5 . The initial value of write data necessary for the test operation is loaded from the BIST control circuit  30  into the write data generating circuit  36 , and according to the test procedure by the test sequencer  31 , write data generated by the write data generating circuit  36  is supplied to the memory core  5  as write data DI through the scrambler  37 . The test control code ACT denotes a word line selection operation, WRIT denotes a data write operation, READ denotes a data read operation, PRE denotes a precharge operation, and REF denotes a refresh operation. 
         [0052]    The memory core  5  performs memory test operations according to the control of the BIST circuit  3 . For example, the memory core  5  internally detects a mismatch between write data and read data, and outputs a detection result as parallel test result PTE. According to this example, the parallel test result PTE is put into a high level (logical value “1”) when a mismatch is detected. For mismatch detection by the parallel test result PTE or anomaly detection by state anomaly detection result ERR of the BIST circuit  3 , the result is held in a latch  40  and outputted to the outside as a fail signal FAIL. Here, the fail signal FAIL is a test result by the BIST circuit  3 . 
       &lt;A Variety of Addressing Modes&gt; 
       [0053]      FIG. 4  shows an example of the address counter  35 . The address counter  35  includes a counter (XCUNT)  40  for X address PX, a counter (BCUNT)  41  for bank address BA, a counter (YCUNT)  42  for Y address, and selection gates (SGT)  43  to  45  that selectively connect or disconnect carry output CO and carry input CI of the counters  40  to  42 . The SGT  43  can select high power impedance, and the SGTs  44  and  45  can select output for one of two inputs or high power impedance. By switching carry transmission paths between the counters  40  and  42  by the SGTs  43  to  45 , a variety of addressing modes are achieved. A start address is preset at the counters  40  to  42  by the BIST control circuit  30 . The counters  40  to  42  perform count operation synchronously with the clock signal CKIN. The operation of the counters  40  to  42  and the selection gates  43  to  45  is controlled by output of the test sequencer  31 . 
         [0054]      FIG. 5  shows addressing modes by the address counter  35 . The figure shows single bank X scanning (SB-XSCAN) that updates bank addresses after one round of X addresses, single bank Y scanning (SB-YSCAN) that updates bank addresses after one round of Y addresses, and multi-bank X scanning (MB-XSCAN) that updates X addresses after one round of bank addresses. Addressing modes in the individual addressing modes and the connection states of carry transmission paths are as shown in the figure. 
         [0055]      FIG. 6  shows the operation timing of the address counter  35  in SB-XSCAN, its operation timing in SB-YSCAN, and its operation timing in MB-XSCAN. CO(PX) designates carry output of XCUNT  40 , CO(BA) designates carry output of BCUNT 41 , and CO(PY) designates carry output of YCUNT  42 . The field of MB-SCAN (last timing) shows that a bank address BA (WRIT) and a Y address PY (WRIT) for data write operation (WRIT) are outputted out of phase with those for word line selection operation (ACT). This is done to prevent the occurrence of access inconvenience caused by successively updating bank addresses. 
         [0056]    The address counter  35  covers the SB-XSCAN, SB-YSCAN, and MB-XSCAN addressing modes, and can provide for the addressing modes by switching the carry paths among the counters  40  to  42  for bank addresses, X addresses, and Y addresses. Since the address counter  35  provides for the MB-XSCN mode, it can also apply to multi-bank memories adopted by mass-storage memories. Since it covers a variety of addressing modes for memory tests, the BIST circuit  3  can be used for not only burn-in and probe inspection but also selection. 
       &lt;Sequencer for Timing Generation&gt; 
       [0057]      FIG. 7  shows a configuration of the test sequencers  31 . The test sequencers  31  for test timing generation each constitute a single control logic by one set of a starter sequencer  50 - i  (i=0 to n) and a subsequencer  51 - i,  and the BIST circuit  3  includes plural sets. 
         [0058]    A starter sequencer  50 - i  is triggered to start operation by a selection signal SENi outputted from the BIST control circuit  30 . The sequence enable signal SENi can be regarded as a signal corresponding to a sequence command given from the BIST control circuit  30 . The starter sequencer  50 - i  functions as a state machine that controls state transition, and the state is caused to transition by an IDLEi signal sent from a subsequencer  51 - i  corresponding to the signal SENi. According to the state, the starter sequencer  50 - i  outputs the signals SRUNi, SIDLEi, and SENDi. A subsequencer  51 - i  is also a state machine that controls state transition, and the state is caused to transition by the signals SRUNi and SIDLEi. According to the state, the subsequencer  51 - i  outputs a 16-bit control signal. The 16-bit control signal is supplied from a 16-bit bus  53  to subsequent stages through a tri-state buffer  52 - i.  The tri-state buffer  52  is put into a high power impedance state by the signal SENDi being put into a high level. The signal SENDi is put into a high level when the starter sequencer  50 - i  is in an idle state or wait state, that is, when control of the pattern generating circuit  33  is substantially stopped. As a result, only the output of a test sequencer  31  selected to operate is supplied to the bus  53 . Control wirings do not need to be routed for each of the test sequencers  31 . To suppress a floating state of the bus  53  when the operation of all the test sequencers  31  is stopped, a tri-state buffer  54  is provided to forcibly put the bus  53  into a low level by a logical product signal ANDSEND of all signals SEND 0  to SENDn. 
         [0059]      FIG. 8  shows the state of a starter sequencer  50 - i  and the state of a tri-state buffer  52 - i.  The tri-state buffer  52 - i  is put into a high power impedance state when the starter sequencer  50 - i  is in an idle state or wait state, that is, when control of the pattern generating circuit  33  is substantially stopped. 
         [0060]      FIG. 9  shows a state transition diagram of starter sequencer  50 - i.  Among states are IDLE, SRUN, SBUSY, and SWAIT. SEN(/SEN) and IDLE are shown as trigger signals for state transition. Suffix i is omitted in  FIG. 9 . 
         [0061]      FIG. 10  shows a logical configuration of a state machine  55  of starter sequencer  50 - i.  The state machine  55  is configured by a 2-bit Johnson counter consisting of QS 0  and QS 1 . 
         [0062]      FIG. 11  shows a decoding part  56  for the 2 bits QS 0  and QS 1  of the state machine  55 . The decoding part  56  outputs the signals SIDLE, SRUN, and SEND. 2-bit values (00, 10, 11, 01) shown in the individual states of  FIG. 9  denote the values of QS 0  and QS 1  (QS&lt; 0 : 1 &gt;) in the states. 
         [0063]    Any of the starter sequencers  50 - i  has the same logical configuration. The logical configurations of the subsequencers  51 - i  are individualized depending on the mode of test operation. As one of the logical configurations of the subsequencers  51 - i,  single bank read/write (SB-Write/Read) will be described in detail. 
         [0064]      FIG. 12  shows a timing sequence of SB-Write/Read. In a write operation, ACT, WRIT, NOP, NOP, NOP, and PRE are executed in that order. In a read operation, ACT, READ, NOP, NOP, NOP, and PRE are executed in that order. In the PRE, the X address counter is forcibly incremented. This is done to perform writing or reading for the next address. 
         [0065]      FIG. 13  shows state transition (timing state transition diagram) of subsequencer associated with SB-Write/Read. The timing sequence of  FIG. 12  is achieved. W/R denotes WRITE or READ. CO(Y) denotes carry output of Y counter YCUNT 42 . The precharge (PRE) state is switched to the idle state (IDLE) by the carry output because, during a single bank operation, bank addresses are updated after one round of X addresses, Y addresses are updated after one round of bank addresses, and a test terminates after one round of Y addresses. 
         [0066]      FIG. 14  shows a state transition diagram of a general-purpose timer of the subsequencer. A general-purpose timer is adopted to prevent an increase in the logical size of the sequencers no matter how small or large the number of consecutive NOPs is. The states of the general-purpose timer can be caused to transition from C 0  to C 7  at maximum by a timer call signal TIMER. Each of the states C 1  to C 7  corresponds to one NOP. 
         [0067]      FIG. 15  shows a logical configuration of a general-purpose timer  57 . The general-purpose timer  57  is configured with a 3-bit binary counter. The 3 bits QT 0  to QT 2  of the binary counter are decoded into an 8-bit signal C&lt; 7 : 0 &gt;. When the timer call signal TIMER is put into a low level, a count operation is halted, and when put into a high level, the count operation is started. 
         [0068]      FIG. 16  shows a logical configuration of a state machine  58  of a subsequencer. The state machine  58  is configured by a 3-bit Johnson counter consisting of QC 0 , QC 1 , and QC 2 . 
         [0069]      FIG. 17  shows a decoding part  59  for the 3 bits QC 0 , QC 1 , and QC 2  of the state machine  58 . The decoding part  59  outputs the signals IDLE, ACT, WRIT, READ, TIMER, and PRE. IDLE, ACT, WRIT, READ, and PRE are supplied to the command encoder  39 . TIMER is supplied to a general-purpose timer  57 . MWRT is a write mode signal given by the BIST control circuit  30  as a result of decoding a test command. 3-bit values (000, 100, 110, 111, 011, 001) shown in the individual states of  FIG. 13  denote the values of QC 0 , QC 1 , and QC 2  (QC&lt; 0 : 2 &gt;) in the states. 
         [0070]      FIG. 18  shows examples of timing sequences achieved by other plural test sequencers  31 . MB (Multi Bank)-Write/Read sequence is shown. In this sequence, write or read is repeated plural times. Suffixes 0 to 3 denote memory bank names. In WRIT 3 , WRIT 0 , WRIT 1 , WRIT 2 , READ 3 , READ 0 , READ 1 , and READ 2 , the bank address counter  41  is forcibly incremented. This is done to alternately switch among memory banks. 
         [0071]    SB (Single Bank)-R/W sequence is shown. In this sequence, read and write are performed. In PRE, the X address counter  40  is forcibly incremented. This is done to successively select X addresses for processing. 
         [0072]    PR (Pseudo Random)-MB (Multi Bank) sequence is shown. Suffixes a, b, c, and d denote memory bank names 0 to 3, respectively. 
         [0073]    SB-ROR (RAS Only Refresh) sequence is shown. In NOP, the bank address counter  41  is forcibly incremented. This is done to perform RAS only refresh by changing a memory bank. In  FIG. 22 , MB-ROR (RAS Only Refresh)  2  sequence is shown. Suffixes 0 to 3 denote memory bank names. 
         [0074]    REF 2  sequence is shown. NOP is repeated 15 times. Repeat counts are managed using the general-purpose timer  57  as previously described. 
         [0075]    PAGE-Write/Read sequence is shown. In this sequence, page writing is performed in a word line unit by repeating WRIT, or page reading is performed in a word line unit by repeating READ. Therefore, in WRIT and READ, the Y address counter  42  is forcibly incremented. In NOP, the X address counter  40  is incremented. This is done to proceed to processing for the next page. 
         [0076]      FIG. 19  shows a timing generation operation of the test sequencers  31 . In this example, as subsequencer  51   i,  the SB-Write/Read timing sequence of  FIG. 12  is performed. 
         [0077]    As mentioned above, the BIST circuit  3  adopts plural test sequencers  31  to generate test timing. By providing plural test sequencers  31  different from each other, the BIST circuit  3  can meet a variety of test timings. Thereby, in comparison with ALPG requiring a memory for program storage, a logical size and a chip occupation area can be reduced. Since specific test sequencers  31  are mounted, the test sequencers to be mounted can be easily customized by product and product kind, and area overhead can be further reduced. Since timing output of each test sequencer  31 , that is, output of subsequencer  51   i  is selected by the tri-state buffer  52   i  before being supplied to the bus  53 , the number of wirings of sequencer output can be reduced more greatly than in the AND-OR multiplexer system. 
       &lt;Write Data Generating Circuit&gt; 
       [0078]      FIG. 20  shows an example of the write data generating circuit  36 . Noting the periodicity of test pattern data, the write data generating circuit  36  is configured so as to generate write data PD for test in plural modes by use of a shift register having a feedback loop. The shift register consists of latches QW 3  to QW 0  of four stages (4 bits) connected in series as plural bits of storage stages. A first feedback loop  61  is provided in which the output of a first latch QW 0  of output side is fed back to the input of a last latch QW 3  of output side. A selector  62  (first selector) that selects between the output of latch QW 1  and the output of latch QW 0  is disposed between the latches QW 1  and QW 0 . A selector  63  that selects between the output of latch QW 3  and the output of latch QW 0  is disposed between the latches QW 3  and QW 2 . Furthermore, a selector  64  (second selector) that selects between the output and input of latch QW 0  is disposed. SD, TRC, and PCB, which are selection signals of the selectors  62 ,  63 , and  64 , respectively, are outputted from the BIST control circuit  30 . Here, input selected by a logical value of the selection signals is as shown in the figure. For example, when SD=1, the output of QW 0  is selected, and when SD=0, the output of QW 1  is selected. The clock terminals of the latches QW 3  to QW 0  are supplied with an X address transition clock TX that synchronizes with change in X address, or a Y address transition clock TY signal that synchronizes with change in Y address. Which of the transition clock signals TX and TY is used is controlled dynamically by the test sequencers  31  according to the addressing mode. 
         [0079]      FIG. 21  shows operation modes of the write data generating circuit  36  by equivalent circuits. When write data PD for test with 0 or 1 in all bits is to be generated, the output of the latch QW 0  has to be fed back to its input as in (a). This is equivalent to a shift register operation of one cycle per round. When write data PD for test is to be generated at a 4-bit cycle, the output of the latch QW 0  has to be fed back to the input of the latch QW 3  as in (b). This is equivalent to a shift register operation of four cycles per round. When write data PD for test is to be generated at a 3-bit cycle, the output of the latch QW 0  has to be fed back to the input of the latch QW 2  as in (c). This is equivalent to a shift register operation of three cycles per round. When write data PD for test is to be generated by a so-called checker board, as in (d), the output of the latch QW 0  has to be fed back to the input of the latch QW 3 , and the output of the latch QW 0  and the output of the latch QW 1  have to be outputted as data in an even Y address and data in an odd Y address, respectively. 
         [0080]      FIG. 22  shows some concrete examples of generating write data by the write data generating circuit  36 . In the figure, a symbol * means that an item concerned is undefined. (a) in  FIG. 22  shows the operation of generating write data of all one bits or all zero bits by the write data generating circuit  36 . The figure shows a memory cell array to which zero data has been written. 
         [0081]    (b) in  FIG. 22  shows an example of generating write data of single row/column stripe by the write data generating circuit  36 . The generation operation is performed at a 4-bit cycle. The figure shows a memory cell array to which data of QW&lt; 3 : 0 &gt;=1010 has been written in single row stripe mode. TX is used for a transition clock. The transition clock TY is used for writing in single column stripe mode. 
         [0082]    (c) in  FIG. 22  shows an example of generating write data of double row/column stripe by the write data generating circuit  36 . The generation operation is performed at a 4-bit cycle. The figure shows a memory cell array to which data of QW&lt; 3 : 0 &gt;=1100 has been written in double row stripe mode. TX is used for a transition clock. The transition clock TY is used for writing in double column stripe mode. 
         [0083]    (d) in  FIG. 22  shows an example of generating write data of checker board by the write data generating circuit  36 . The generation operation is performed at a 4-bit cycle. The figure shows a memory cell array to which writing has been performed with checkerboard of QW&lt; 3 : 0 &gt;=1010. TX is used for a transition clock. 
         [0084]    (e) in  FIG. 22  shows an example of generating write data of 3-bit cycle by the write data generating circuit  36 . The figure shows a memory cell array to which writing has been performed with QW&lt; 3 : 0 &gt;=*010. TX is used for a transition clock. 
         [0085]    By adopting the write data generating circuit  36  of the above-mentioned shift register configuration, in comparison with general-purpose pattern generating circuits configured to selectively generate given patterns upon the loading of control data stored in ROM as typified by ALPG, write data of a variety of patterns can be easily generated on a comparatively small logical scale. 
       &lt;Clock Generating Circuit&gt; 
       [0086]      FIG. 23  shows the clock generating circuit  32 . The clock generating circuit  32  includes: a ring oscillator  70  capable of changing the number of gate stages of an oscillation loop; changeable frequency dividers  71  to  73  that frequency-divide the output of the ring oscillator  70 ; a frequency comparator  74  that compares predetermined output of the changeable frequency divider  72  with the frequency of an external clock signal CKEX; and a counter  75  for adjusting the number of stages that increments or decrements according to a comparison result by the frequency comparator  74 . A count value KCNT of the counter  75  is used to select an oscillation loop of the ring oscillator  70  so as to match predetermined output of the changeable frequency divider  72  to the frequency of an external clock signal CKEX. The frequency comparator  74  and the counter  75  include an oscillation frequency control circuit that adjusts the number of gate stages of the oscillation loop based on the result of comparing an predetermined output of the changeable frequency divider  72  and the external clock signal CKEX. 
         [0087]    The frequency divider  71  frequency-divides oscillation output CKRO of the ring oscillator  70  at a frequency division ratio of 2 0  to 2 −7  to output eight kinds of clock signals CKD&lt; 7 : 0 &gt;. The frequency divider  72  inputs one clock signal selected from among the eight kinds of clock signals by a selector  76  and frequency-divides it at a frequency division ratio of 5 0  to 5 −3  to output four kinds of clock signals CKD&lt; 11 : 8 &gt;. One of the four kinds of clock signals CKD&lt; 11 : 8 &gt; is selected by a selector  77  and supplied to the frequency comparator  74  as a clock signal CKC. The frequency divider  73  inputs one clock signal selected from among the 12 kinds of clock signals CKD&lt; 11 : 0 &gt; by a selector  78  and frequency-divides it at a frequency division ratio of 3 0  to 3 −1  to output two kinds of clock signal CKDD&lt; 1 : 0 &gt;. One of the two kinds of clock signals CKDD&lt; 1 : 0 &gt; is selected by a selector  79  and outputted as the internal clock signal CKIN. KRC&lt; 2 : 0 &gt; and KRC&lt; 4 : 3 &gt; are selection control signals of the selectors  76  and  77 , respectively. KRIN&lt; 3 : 0 &gt; and KRIN&lt; 4 &gt; are selection control signals of the selectors  78  and  79 , respectively. The selection control signals KRC&lt; 4 : 0 &gt; and KRIN&lt; 4 : 0 &gt; are supplied from the BIST control circuit  30 . 
         [0088]      FIG. 24  shows the ring oscillator  70 . The ring oscillator  70  shown in the figure variably adjusts the number of gate stages of an oscillation loop by 16 steps. The ring oscillator  70  has 16 delay gate units  80 . The delay gate units  80  each include a three-input NAND gate NAND  81 , and inverters  82  and  83  connected in series with the NAND  81 . The NAND gate NAND 81  admits PDU&lt;i&gt;, PDL&lt;j&gt;, and output of the inverter  83 . Output of an inverter  83  of a delay gate unit  80  of a preceding stage is connected to input of an inverter  82  of a delay gate unit  80  of a following stage. In this way, an oscillation loop is formed by 16 stages of the delay gate units  80 . Outputs of NAND gate NANDs  81  of delay gate units  80  of first four stages are inputted to a four-input NAND gate NAND  84 . Outputs of NAND gate NANDs  81  of delay gate units  80  of next four stages are inputted to a four-input NAND gate NAND  85 . Outputs of NAND gate NANDs  81  of delay gate units  80  of next four stages are inputted to a four-input NAND gate NAND  86 . Outputs of NAND gate NANDs  81  of delay gate units  80  of last four stages are inputted to a four-input NAND gate NAND  87 . Outputs of the NAND gates NAND  84  to NAND  87  are inputted to a four-input NAND gate NAND  92  through inverters  88 ,  89 ,  90 , and  91 . Output of the NAND gate NAND  92  is fed back to the first-stage delay gate unit  80  through a two-input NAND gate NAND  93 . Output of a NAND gate NAND 92  is inverted by an inverter  94  and supplied to the frequency divider  71  as a clock signal CKRO. 
         [0089]    The count value KCNT consists of 4 bits (KCNT&lt; 3 : 0 &gt;) and decoded into control signals PDU&lt; 3 : 0 &gt; and PDL&lt; 3 : 0 &gt; by pre-decoders  95  and  96 . The control signals PDU&lt; 3 : 0 &gt; and PDL&lt; 3 : 0 &gt; are supplied to the individual NAND gates NAND 81  as PDU&lt;i&gt; and PDL&lt;j&gt; according to a predetermined decoding logic. One PDU&lt;i&gt; and one PDU&lt;j&gt; of the eight control signals PDU&lt; 3 : 0 &gt; and PDL&lt; 3 : 0 &gt; are put into a high level. One NAND gate  81  to which both PDU&lt;i&gt; and PDL&lt;j&gt; of a high level are supplied can form logic output conforming to an output of the inverter  82 . The number of gate stages of the oscillation loop differs according to the position of the NAND gate  81  that can form the logic output. Thereby, oscillation frequencies of the ring oscillator  70  are made variable. 
         [0090]      FIG. 25  shows the frequency comparator  74 . The frequency comparator  74  includes: a pulse generating circuit  100  that outputs a single pulse signal each time the rising edge of the clock signal CKC as a reference signal appears; a pulse generating circuit  101  that outputs a single pulse signal each time the rising edge of the clock signal CKC as a feedback signal appears; a flipflop  102  of set/reset type; and flipflops  103  and  104  of edge-triggered type. In this circuit, when the reference signal CKEX falls, a single pulse signal is outputted from the pulse generating circuit  100  and serves as a clock signal of the flipflop  103 . When the single pulse signal is generated, output  105  of the flipflop  102  is captured, and put into a low level a little later by the single pulse signal. When the feedback signal CKC falls, a single pulse signal is outputted from the pulse generating circuit  101 . The single pulse signal serves as a clock signal of the flipflop  104 . When the single pulse signal is generated, output  106  of the flipflop  102  is captured into the flipflop  104 , and put into a low level a little later by the single pulse signal. Unless the falling reference signal CKEX and the falling feedback signal CKC appear at the same time, if one of  105  and  106  goes into a low level, the other goes into a high level. Even if they appear at the same time, a high level develops on the side where a single pulse disappears earlier, and a low level develops on the other side. Accordingly, after the reference signal CKEX and the feedback signal CKC become almost equal to each other in phase and frequency, since the falling reference signal CKEX and the falling feedback signal CKC appear alternately without fail almost every half cycle, a high level is captured in the flipflops  103  and  104  without fail. However, if one of the frequencies of the reference signal CKEX and the feedback signal CKC remains high, each time a phase difference of one cycle occurs, a single pulse appears twice in succession on the side of higher frequency and a low level is captured in the flipflop  103  or  104  of the side. This is outputted as signals UP and DOWN indicating that there is a difference in frequencies. 
         [0091]      FIG. 26  shows operation waveforms of the frequency comparator  74 . As shown in the part of operation waveform  110 , if a low-level period of one of the waveforms of node signals  100 A and  101 A is contained in a low-level period of the other, output corresponding to the former goes into a high level. Since sensitivity becomes higher in either of the node signals  100 A and  101 A that has a smaller duty ratio of their waveforms, it is desirable to provide the pulse generating circuits  100  and  101  as shown in  FIG. 25 . From a different viewpoint, if the duties of the clock signals CKEX and CKC are small, the pulse generating circuits  100  and  101  are not required and may be omitted. 
         [0092]      FIG. 27  shows clock generation operation timing by the clock generating circuit  32 . As an example, a clock signal CKC is generated through CKD&lt; 2 &gt;, CKD&lt; 8 &gt;, and CKD&lt; 9 &gt;. In this example, at times t 1 , t 2 , and t 3 , KCNT is successively decremented, and CKIN increases gradually in frequency. 
         [0093]    If the clock generating circuit  32  is adopted, the external clock signal CKEX may be a clock signal of a relatively low frequency such as operation frequencies supported by low-speed testers. If the frequency division ratio of the clock signal CKIN used as a test clock signal is smaller than that of the clock signal CKC inputted to the comparator  74 , the frequency of the test clock signal CKIN can be made higher than the low-speed clock signal CKEX of the tester, contributing to speedup in tests. For example, a frequency hundreds of times as high as that of the external clock signal CKEX can be obtained. Here, since the ring oscillator  70  capable of changing the number of gate stages of an oscillation loop is used to generate a desired frequency, in comparison with PLL circuits, circuit scale can be significantly reduced at some cost of the accuracy of frequency synchronization, contributing to reduction in chip occupation area. 
         [0094]      FIG. 28  shows a test flow of SDRAM. Non-defective SDRAM is obtained through wafer inspection, probe inspection, packaging, first selection by a high-speed tester, burn-in, second selection and third selection by a low-speed tester. In the second selection, low-speed function tests are performed at low and high temperatures. In the third selection, a data retention test is performed for almost one-third the period. Accordingly, use of the low-speed tester is desirable to reduce test costs. In other tests, since a BIST circuit is used, use of the low-speed tester will not result in significant increase in test time. Simple function tests and simple data retention tests, which are performed in the first high-speed selection, may be achieved using a low-speed tester and a BIST circuit on a chip. 
         [0095]    Here, a description will be made of cost reduction effects when tests by use of a high-speed tester are replaced by tests by use of a low-speed tester and the BIST circuit  3  on the chip. For example, in the case where the BIST circuit is added to DDR-SDRAM, if it is estimated that circuit elements increase by 5590 NAND gates and wiring areas increase by 20 areas, with 1.3 μm process, the former increases the area by 0.56 mm 2  and the latter increases the area by 0.40 mm 2 , thereby bringing an estimated increase in manufacturing costs into about 15 yen. It is estimated that test time is reduced by about 2000 seconds by building in the BIST circuit  3 . If test cost is 0.05 yen per second, building in the BIST circuit  3  on the chip would reduce costs by about 85 yen per chip. 
         [0096]    Hereinbefore, though the invention made by the inventors of the present invention has been described in detail based on the preferred embodiments, it goes without saying that the present invention is not limited to the preferred embodiments, but may be modified in various ways without changing the main purports of the present invention. 
         [0097]    For example, the number of memory banks may be changed as required without being limited to 4. The addressing modes are not limited to those shown in  FIG. 5 , and the write data generation patterns are not limited to those shown in  FIG. 21 . The memory, without being limited to SDRAM, may be SRAM, MRAM, FeRAM, flash memory, and other ROMs. The memory may be a multiport memory without being limited to a single port memory. Furthermore, the present invention may also apply to an associative memory. Also, the present invention may apply to not only memory LSI but liquid crystal drive circuits equipped with memory, and semiconductor integrated circuits such as graphic control devices and microcomputers.