Abstract:
A decoding circuit receives signals encoded in differential logical conversion, and decodes the received signals into original signals. During the decoding, a predetermined data bit position included in the original signals is detected in the received signal, and also the predetermined data is forcedly set to the bit position of the decoded signal, thereby bit error propagation is suppressed up to the position of the known data.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a decoding circuit where codes created by differential encoding are decoded. 
     2. Description of the Prior Art 
     FIG. 1 is a block diagram showing a decoding circuit where codes created by differential logical conversion are decoded (hereinafter referred to as &#34;sum decoding circuit&#34;) together with a differential logical circuit at the transmitting side of a communication system in the prior art. In FIG. 1, numeral 1 designates an input terminal where digital data a are input, numeral 2 designates a one-bit delay circuit constituted by one D-type flip-flop for example, numeral 3 designates an exclusive-OR circuit (hereinafter referred to as &#34;EX-OR&#34;) for creating a difference, numeral 4 designates an output terminal where transmitting data b are output, numeral 5 designates a transmission path having noise, numeral 6 designates an input terminal where received data c including error are input, numeral 7 designates a one-bit delay circuit, numeral 8 designates an EX-OR for creating a sum, and numeral 9 designates an output terminal where data d after the sum decoding are output. 
     Next, operation will be described. The differential logical conversion at the transmitting side is expressed by the following formula. 
     
         b.sub.i =a.sub.i ⊕a.sub.i-1                            ( 1) 
    
     Where a i  designates data before the conversion, and b i  designates data after the conversion, and a i  and b i  correspond to a, b respectively in FIG. 1. Subscript 1 represents the i-th data. Also ⊕ represents the addition using 2 as modulus (modulo-2 addition). The input data a is input to one of two input terminals of the EX-OR 3, and also input to the one-bit delay circuit 2. Consequently, viewing the input data from a time series, the output signal of the one-bit delay circuit 2 is one-bit previous data a i-1 . The EX-OR 3 performs modulo-2 addition of the data signal a, i.e., a i  as one input and the output signal a i-1  of the one-bit delay circuit 2 as the other input, and obtains the output data signal b, i.e., b i . FIG. 2 shows the relation between a i  and b i , for example. 
     The decoding on the receiving side is expressed by the following formula. 
     
         d.sub.i =c.sub.i ⊕d.sub.i-1                            ( 2) 
    
     Where d i  designates decoded data, and c i  designates the received data before the decoding. Formula (2) represents that in order to obtain the i-th decoded data, one-bit previously decoded data [(i-1)th data] may be added to the i-th received data using 2 as modulus. So, the decoded data d is input to the one-bit delay circuit 7 and delayed by one bit, and then adding it to the received data c using 2 as modulus is performed in the EX-OR 8 thereby next decoded data d is obtained. This state is shown in c i , d i  in FIG. 2. 
     In the sum conversion decoding at the receiving side, two problems occur as follows. 
     One is a problem in the initial value of the decoded data stream. Transforming the formula (2), it follows that 
     
         d.sub.i =c.sub.i ⊕c.sub.i-1 ⊕c.sub.i-2 ⊕. . . ⊕c.sub.2 ⊕c.sub.1 ⊕d.sub.o                                 ( 3) 
    
     The decoded data d i  is determined by the received data series c 1  -c i  and the initial value d o  which cannot be determined only by the received data. The initial value d o  is usually specified in the system whereby the problem is solved. 
     A second problem is in that since the data transmission path 5 includes noise, the received data c includes error, and after decoding this error propagates in the subsequent data through the sum conversion and so-called error propagation occurs. This state is shown in c i , d i  of FIG. 2. In the received data c i , error occurs in c 11  and c 17 . In the data d i  after the decoding, not only does the error of c 11  result in the error of one bit in d 11 , but the inversion of data continues subsequently and the error of the decoded data d i  continues until the data is inverted again in the next received error bit c 17  and returned to the original state. Thus, if a one-bit error occurs in the received data, all of the following decoded data is inverted and results in error until the next one-bit error of the received data occurs. 
     Since the sum decoding circuit in the prior art is constituted as described above, problems exist in that the error propagation is produced and the error is enlarged significantly in the decoding circuit. 
     SUMMARY OF THE INVENTION 
     In view of the above-mentioned problems in the prior art, an object of the present invention is to provide a sum decoding circuit wherein the error propagation due to the sum decoding is stopped at regular intervals, spread of the error is suppressed and the error rate characteristics can be improved. 
     In order to attain such object, the invention provides data setting means using known data as feedback data at the transmitter and matching the known data with the receiving timing of the known data inserted in the data series at the receiver. 
     In the decoding circuit according to the invention, known data is inserted in the data series before the transmission difference conversion and the created difference codes are received, and at the receiving timing of the known data, the known correct data is applied as the data after the decoding. Since the correct data is forcedly fed back as the data after the decoding as above described, the error propagation is stopped and the enlargement of the error is inhibited. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing a sum decoding circuit and a differential logical conversion circuit in the prior art; 
     FIG. 2 is an explanation diagram illustrating an example of coding and decoding of differential codes; 
     FIG. 3 is a block diagram showing a decoding circuit as a first embodiment of the invention; 
     FIGS. 4(A) through (d) are timing charts illustrating operation of the decoding circuit shown in FIG. 3; 
     FIG. 5 is a circuit diagram showing a frame recovery circuit; 
     FIG. 6 is a circuit diagram showing a timing generator for generating the receiving timing of the known data; 
     FIG. 7 is a block diagram showing a decoding circuit as a second embodiment of the invention; 
     FIG. 8 is a data constitution diagram illustrating constitution of data having mid-amble; 
     FIG. 9 is a block diagram showing a decoding circuit as a third embodiment of the invention; 
     FIG. 10 is a block diagram showing a decoding circuit as a fourth embodiment of the invention; and 
     FIG. 11 is a logic diagram illustrating operation of the logical circuit shown in FIG. 10. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A sum decoding circuit as an embodiment of the invention will now be described referring to the accompanying drawings. 
     FIG. 3 is a block diagram showing a sum decoding circuit as a first embodiment of the invention. In FIG. 3, numeral 6 designates an input terminal where received data c are input, numeral 7 designates a one-bit delay circuit, numeral 8 designates an EX-OR, numeral 9 designates an output terminal where decoded data d after the decoding are output, numeral 10 designates a clock recovery circuit, numeral 11 designates a frame recovery circuit, numeral 12 designates a timing generator used in conjunction with receiving the known data, and numeral 13 designates the a data selector. Also e1 designates output signal of the one-bit delay circuit 7 (being one-bit previously decoded data), e2 designates the initial value of the decoded data stream (The initial value is 1 or &#34;H&#34; level in this case.), and e3 designates the known data (the known data is 0 or &#34;L&#34; level in this case.). 
     FIG. 4 is a diagram illustrating the state in which the error propagation is stopped by inserting the known data, where c i  in FIG. 4(a) designates the received data, d i  in FIG. 4(b) designates the data after the decoding, numerals 14a, 14b designate the frame synchronization bit series before the decoding and after the decoding respectively, numeral 15 designates the known data series included in the data after the decoding, and numeral 16 designates the error portion of the data d i  after the decoding. Also f in FIG. 4(c) designates the frame synchronization signal, and g in FIG. 4(d) designates the timing signal of receiving the known data. 
     Next, operation will be described. Signal transmitted by the transmitting side is one obtained by differentially coding the frame synchronization bit series and the effective data. In the effective data, a known data bit is inserted in a prescribed bit position. In the decoding circuit, the clock signal h is regenerated from the input signal c in the clock recovery circuit 10. In this case, the clock recovery circuit 10 is constituted by a PLL (Phrase Locked Loop) for example. Also the frame synchronization signal f is generated from the input signal c and the recovery clock signal h in the frame recovery circuit 11. 
     The frame recovery circuit 11, for example, as shown in FIG. 5, is realized by a digital correlator comprising a shift register 111, a switch group 112, EX-OR 113, a parallel counter 114 and a digital comparator 115. First, the input data c is input to the shift register 111, and is shifted to the right direction one bit by one bit by the recovered clock signal h and stored. The switch group 112 is set to either &#34;H&#34; level or &#34;L&#34; level of each bit corresponding to the known frame synchronization signal before the decoding. The reference pattern by the switch group 112 and the received data are compared in parallel by the EX-OR 113, and a number of coincident data is output from the parallel counter 114 in binary notation. The digital comparator 115 compares the output data of the parallel counter 114 with the threshold data (constant value) previously set, and when the output data value of the parallel counter 114 exceeds the constant threshold value, the frame synchronization signal f is output. 
     The frame synchronization signal f is input to the data selector 13 and the timing generator 12 for generating the timing of receiving the known data in FIG. 3. Since the position of the known data inserted into the generated data from the transmitting side, for example, a 128th bit of data succeeding the frame synchronization bit series is known, the timing generator 12 can be realized in the constitution shown in FIG. 6 for example. 
     In FIG. 6, numeral 121 designates a counter, and numeral 122 designates a digital comparator. The counter 121 is reset by the frame synchronization signal f, and advances at each rise of the clock signal h. Consequently, the number of the counter 121 indicates the number of bits from the top end of the data frame. The digital comparator 122 compares the count value with the reference data representing the position of the known data previously set, and when both are coincident, the timing signal g of receiving the known data is output. The timing signal g of receiving the known data is input to the select input of the data selector 13. 
     FIG. 4 shows the timing of the received data c, the frame synchronization signal f and the timing signal g of receiving the known data. Operation of the data selector 13 will be described referring to FIG. 4. At the usual data receiving state, both the frame synchronization signal f and the timing signal g of receiving the known data are at &#34;L&#34; level. Then the data selector 13 selects el among three inputs of data e1, e2, e3, thus the one-bit previously decoded data is input to the EX-OR 8. Consequently, the decoding is performed in similar manner to that in the decoding circuit in the prior art. When the frame synchronization signal f is at &#34;H&#34; (then the timing signal g of receiving the known data is at &#34;L&#34;), the data selector 13 selects the data e2. The data e2 corresponds to the initial value of the decoded data stream, and d o  shown in formula (3) is input to the decoding circuit EX-OR 8 then. When the timing signal g of receiving the known data is at &#34;H&#34; (then the signal h is at &#34; L&#34;), the data selector 13 selects the data e3. The data e3 is data equal to the known data, and is made &#34;L&#34; in the embodiment. Consequently, at the time of receiving the known data, the feedback loop of the decoding circuit is cut, and the correct decoded data is supplied to the decoding circuit irrespectively of whether the one-bit previously decoded data is correct or not. Consequently, the error propagation is stopped at the time of receiving the known data. In FIG. 4, &#34;x&#34; at (a) indicates the occurrence of a data error, and numeral 16 indicates the error portion of the data after the decoding. 
     FIG. 7 is a block diagram showing a decoding circuit as a second embodiment of the invention. The decoding circuit is constituted so that data generated by the transmitting side has the known data series including frame synchronization bits (hereinafter referred to as &#34;mid-amble&#34;) at the center portion as shown in FIG. 8. 
     In FIG. 7, numeral 11a designates a frame recovery circuit, numeral 12 designates a timing generator for timing reception of the known data, numeral 13 designates a data selector, numeral 21 designates a data buffer circuit, numeral 22 designates a high-speed clock generator for generating the high speed clock i, and numeral 23 designates a frequency divider. Also in FIG. 8, numerals 24a, 24b designate non-transmitting portions, numeral 25a designates rising portion of the transmitting power, numeral 25b designates falling portion of the transmitting power, numerals 26a, 26b designate tail bits, numerals 27a, 27b designate data carrying the information, and numeral 28 designates a mid-amble frame section. 
     Operation of the second embodiment will be described. As shown in FIG. 8, the mid-amble 28 for the frame synchronization is arranged at the center portion of the received signal. The received signal c is sampled with the high speed clock i, and stored in the buffer circuit 21 temporarily. In this case, the buffer circuit 21 is realized by a shift register, for example. The frame recovery circuit 11a of FIG. 7 is driven by the clock in at a higher speed than the bit rate, and detects the mid-amble from the received signal c. That is, the frame recovery circuit 11a may be constituted in similar manner to the frame recovery circuit 11 shown in FIG. 5, but the number of steps of the shift register is ##EQU1## Also the number of switches in the switch group 112 is equal to the number of steps of the shift register in this case. 
     Also the recovery clock signal h is created as follows. First, the frequency divider 23 is reset by the frame synchronization signal f. Consequently, the phase of the recovery clock signal h is coincident to the phase of received signal c with reference to the frame synchronization signal f. And then the frequency divider 23 performs the frequency dividing of the high speed clock signal at the frequency dividing ratio of ##EQU2## 
     If the number of steps of the buffer circuit 21 being the shift register is set so that the data received before the frame synchronization signal is stored in the buffer circuit 21, the first bit of the received signal c is input to the EX-OR 8 when the frame synchronization signal f is output, thereby the subsequent operation can be explained in similar manner to the first embodiment. However, the tail bit is used as the initial data, and any one bit among the mid-amble 28 is used as the inserted known data. 
     In the embodiment shown in FIG. 3, the known data after the frame synchronization signal f appears at one position, but it may appear at plural positions. An embodiment in this case is shown in FIG. 9. The decoding circuit shown in FIG. 9 can be used when the known data to be utilized for stopping the error propagation exists at seven positions at most. In this case, the output signal lines of the timing generator 12a are enlarged to three lines, and prescribed pattern is output at respective timings of the known data existing at seven positions at most. Corresponding to this pattern, the data selector 13 selects either one among seven data previously set as the known data and the initial value or the ordinarily decoded data. 
     The timing generator 12a may be constituted in similar manner to that shown in FIG. 6, but the digital comparator 122 is constituted to enable comparison of the comparing data of seven values at most with the output of the counter 121, and when each comparing data and the output of the counter 121 are coincident, pattern corresponding to each comparing data is output. 
     FIG. 10 is a block diagram of a decoding circuit as a fourth embodiment of the invention where the feedback data is determined by a logical circuit 29 in place of the set value and the data selector 13 of FIG. 9. The output signal of the logical circuit 29 is determined as shown in FIG. 11, and the decoding circuit performs operation in similar manner to the data selector 13 shown in FIG. 3 and the circuit using the set values e1-e3.