Abstract:
A method for reducing sub-threshold leakage during the burn-in procedure for a semi-conductor is disclosed. The method includes applying a back-bias voltage to the device during the burn-in procedure. The back-bias voltage increases the threshold voltage of the semi-conductor device and consequently, reduces the sub-threshold leakage current.

Description:
BACKGROUND OF INVENTION  
         [0001]    When semi-conductor circuits are fabricated to manufacture such items as a computer microprocessor or other microelectronics, a certain number of failures from the total production run is expected. Typically, these failures come early or late in the life of the circuit. FIG. 1 shows a graph  10  of the number of expected failures over a period of time. The curve is commonly referred to as a “bathtub curve”. It shows three distinct regions: the “infant stage”  12 , the “operational life stage”  14 ; and the “old age stage”  16 . During the infant stage  12 , the number of failures maybe high and they decrease in number rapidly as the curve moves in the operational life stage  14 . While in the operational stage  14 , the number of failures falls to practically zero until the curve moves in the old age stage  16 . Once in the old age stage  16 , the number of failures begins the increase rapidly as the product&#39;s effective life expires.  
           [0002]    A goal of manufacturers is to get a product over the infant stage  12  quickly in order to weed out defects prior to shipment to the customer. In the case of semi-conductor circuits, this goal is accomplished by a procedure called “burn-in”. The procedure includes subjecting the circuit to stresses such as elevated temperatures and supply voltages as a technique of accelerating the operational life. For example, some semi-conductors have an infant stage that could last as long as 3-4 years of normal operation, while the operational life may last as long as 10 years. Obviously in such a case, a successful burn-in procedure must accelerate the time frame of the bathtub curve. As a result, a standard burn-in process can last about 36-48 hours. The net result is 48 hours in a burn-in procedure can simulate four years of normal operation and thereby greatly increase product reliability for the customer.  
           [0003]    [0003]FIG. 2 shows a cross-sectional view of a prior art N-type metal oxide semi-conductor field effect transistor (N-type MOSFET). This type of transistor is well known in the art and is a fundamental component of many micro-electronic devices. The transistor includes a gate  26  region, a source  28  region, and a drain  30  region. These regions are located in an architectural layer  32  of P-type material. This P layer  32  further overlays a conductive substrate  34  of doped P+ type material. This P+ substrate  34  is connected to the source voltage (Vss)  38  for the circuit. The source  28 , the gate  26 , and the drain  30  are each provided with a separate metallic lead  22   a ,  22   b ,  22   c  respectively. Each lead  22   a ,  22   b ,  22   c  is connected to its respective region  28 ,  26 ,  30  through a conductive contact  24   a ,  24   b ,  24   c . Finally, the source  28  and drain  30  are isolated from other elements of the circuit by respective field oxide regions  36   a ,  36   b . These regions  36   a ,  36   b  are made of a non-conductive material which prevents the transfer of any transient currents outside the transistor  20 .  
           [0004]    During normal operation, a positive voltage is applied to the gate  26  from its metallic lead  22   b . This effectively turns the transistor  20  “on” and current flows through the device. In order to turn the transistor on, the voltage applied to the gate  26  must be sufficient to overcome the threshold voltage (Vt) that is an inherent characteristic of the device. As the name implies, the threshold voltage is the point where the device switches from the “off” state to the “on” state and vice-versa. Another characteristic of the device is the leakage or standby current. This is the current that normally flows through the device when it is in the “off” state. The threshold voltage and the leakage current have an exponential relationship.  
           [0005]    In current circuit design trends, the threshold voltage of semi-conductor devices is being reduced as much as possible to increase the speed of the circuit. While this technique is successful in achieving performance gains, it causes difficulties during the burn-in procedure when the temperatures are increased and the supply voltage may be increased as much as 50% above normal levels. The stresses of burn-in have the effect of increasing the leakage current to unacceptable levels. The solution has been to back off on performance improvements by raising the threshold voltages in order to hold leakage current to acceptable levels during the burn-in procedure.  
         SUMMARY OF INVENTION  
         [0006]    In some aspects the invention relates to a method for conducting a burn-in procedure for a semi-conductor device comprising: applying a burn-in procedure stress to the semi-conductor device; and applying a negative back-bias voltage to the semi-conductor device.  
           [0007]    In an alternative embodiment, the invention relates to a method for conducting a burn-in procedure for a semi-conductor device comprising: step for applying a burn-in procedure stress to the semi-conductor device; and step for applying a negative back-bias voltage to the semi-conductor device.  
           [0008]    Advantages of the invention may include, one or more of the following.  
           [0009]    There is no reduction in performance characteristics of semi-conductors due to leakage current constraints during the burn-in procedure. No alterations of existing statistical reliability baselines are necessary due to modifications in burn-in procedures to accommodate leakage current constraints.  
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0010]    [0010]FIG. 1 shows a graph of expected failures of semi-conductor components over time.  
         [0011]    [0011]FIG. 2 shows a prior art cross section of an N-type transistor.  
         [0012]    [0012]FIG. 3 shows one embodiment of a cross section of an N-type transistor in accordance with the present invention.  
         [0013]    [0013]FIG. 4 shows a graph of the relationship between the threshold voltage and the back-bias voltage.  
         [0014]    [0014]FIG. 5 shows an alternative embodiment of a cross section of an N-type transistor in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0015]    Exemplary embodiments of the invention will be described with reference to the accompanying drawings. Like items in the drawings are shown with the same reference numbers.  
         [0016]    [0016]FIG. 3 shows one embodiment of a cross-sectional view of an N-type MOSFET transistor in accordance with the present invention. As can be seen, the physical arrangement of the transistor  20  is the same as shown in FIG. 2. The difference is that a negative “back-bias” voltage (−Vbb)  42  is applied to the P+ conductive substrate  34 . When the back-bias voltage  42  is applied, it has the effect of creating a depletion region  40  within the layer of P-type material  32 . The depletion region  40  is formed in the section of the P layer  32  that is immediately adjacent to the P+ substrate  34 .  
         [0017]    The addition of the back-bias voltage  42  raises the value of the threshold voltage (Vt) of the transistor by neutralizing a portion the positive voltage applied on the gate  26 . The net result is a reduction in the leakage current due to the increased threshold voltage. The relationship between the threshold voltage (Vt) and the back-bias voltage (−Vbb) is shown in FIG. 4. The baseline threshold voltage (Vto) represents the threshold voltage value before the application of the back-bias voltage. The graph  44  shows the curve of the increased threshold voltage (Vt) is proportional to the square root of the absolute value of Vbb. As shown, a small initial increase in −Vbb will result in a significant increase in Vt.  
         [0018]    In some embodiments, a back-bias voltage of as little as 0.5 volts will result in an order of magnitude (10×) improvement in the threshold voltage. During a burn-in procedure, the addition of 0.5-1.0 volts is not a significant increase in stress on the circuit when it is added to the source voltage (Vss) with its 50% increase from its normal value. Consequently, when back-biasing as shown in FIG. 3 is applied during a burn-in procedure, the threshold voltage can be raised and leakage current can be reduced without sacrificing performance for the sake of the burn-in.  
         [0019]    An alternative embodiment of the present invention is shown in FIG. 5. In this embodiment, the arrangement of the components of the transistor  20  is the same as shown in FIG. 3 and FIG. 4, with the exception of the point of application of the negative back-bias voltage  42 . This embodiment shows the back-bias voltage  42  being applied to a plug of P+ type material  46  that is located in a channel within the layer of P material  32 . The effect of the back-biasing is same as shown in FIG. 3. The only difference is the location of the application point of −Vbb  42 .  
         [0020]    Although only two exemplary embodiments of back-biasing have been disclosed, it is intended that this invention would be able to make use of any suitable alternative methods of back-biasing in order to diminish current leakage during a burn-in procedure. Additionally, while embodiments are shown using an N-type MOSFET, the invention could be used on other types of transistors such as P-type MOSFETs.  
         [0021]    Advantages of the invention may include, one or more of the following. There is no reduction in performance characteristics of semi-conductors due to leakage current constraints during the burn-in procedure. No alterations of existing statistical reliability baselines are necessary due to modifications in burn-in procedures to accommodate leakage current constraints.  
         [0022]    While the invention has been disclosed with reference to specific examples of embodiments, numerous variations and modifications are possible. Therefore, it is intended that the invention not be limited by the description in the specification, but rather the claims that follow.