Abstract:
A gate stack ( 104 ) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric ( 108 ) is formed over the silicon substrate ( 102 ). Remote plasma nitridation of the high-k dielectric is performed to create a nitride layer ( 107 ) over the high-k dielectric ( 107 ). A conductive layer ( 110 ) is formed over the nitride layer ( 107 ) forming the gate electrode.

Description:
This application claims priority under 35 USC §119(e)(l) of provisional application number 60/109,685 filed Nov. 24, 1998. 
    
    
     CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS 
     The following co-assigned pending patent applications are hereby incorporated by reference: 
     
       
         
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Patent 
                   
                   
                   
               
               
                   
                 No./Ser. 
                   
                 TI Case 
               
               
                   
                 No. 
                 Filling Date 
                 Number 
                 Inventors 
               
               
                   
                   
               
             
             
               
                   
                 60/019,429 
                 6/7/96 
                 TI-23502P 
                 Hattangady et al. 
               
               
                   
                 60/035,375 
                 12/5/96 
                 TI-22980P 
                 Kraft et al. 
               
               
                   
                 60/092,909 
                 07/15/98 
                 TI-27159P 
                 Hattangady et al. 
               
               
                   
                   
               
             
          
         
       
     
     FIELD OF THE INVENTION 
     The invention is generally related to the field of MOSFET transistors and more specifically to the gate stack formation including a high-K gate dielectric. 
     BACKGROUND OF THE INVENTION 
     Presently, there is a great demand for shrinking semiconductor devices to provide an increased density of devices on the semiconductor chip that are faster and consume less power. The scaling of devices in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the effective electrical thickness of the gate dielectric to be reduced so as to provide the required device performance. 
     Silicon dioxide has been the preferred gate dielectric material. However, newer technologies are requiring effective thicknesses of the silicon dioxide below currently believed limits (e.g., &lt;10 Angstroms). Therefore, there is interest in using higher dielectric constant (high-K) materials such as tantalum pentoxide and barium-strontium-titanate. Using a higher-K material allows for a greater physical thickness while obtaining a lower effective electrical thickness. 
     Unfortunately, most of the high-K materials being considered contain oxygen and/or are formed in an oxygen ambient. Therefore, during formation, silicon dioxide is formed on the surface of the substrate between the high-K dielectric and the substrate. The thickness of the silicon dioxide is such that much of the advantage to be obtained with the high-K material is lost. 
     In addition to silicon dioxide that can be formed during dielectric formation, the formation of polycrystalline silicon as a gate material on the high-K dielectric can also result in the formation of silicon dioxide. This has led to the use of metal gates on high-K dielectric material. 
     The threshold voltage of CMOS transistors is a critical parameter for the proper functioning of circuits made up of these devices. Among other factors, the threshold voltage is determined by the work function of the gate material and the semiconductor substrate. In using metal gates, the work function of the metal used is such that additional processing steps are required to obtain the correct threshold voltage. This additional processing can degrade the CMOS transistor performance. It is therefore desirable to use polycrystalline silicon for the gate material over high-K dielectrics without forming silicon dioxide on the high-K dielectric material. 
     High-K dielectrics are also being evaluated for memory applications as a storage capacitor cell dielectric. In some memory applications, it will also be desirable to form a polycrystalline gate over a high-K dielectric. 
     SUMMARY OF THE INVENTION 
     An embodiment of the instant invention uses remote plasma nitridation (RPN) of the high-K dielectric prior to the formation of a polycrystalline silicon gate. The RPN inhibits oxidation of the high-K dielectric during polycrystalline silicon gate formation resulting in a gate dielectric structure having a thinner effective electrical thickness. 
     An advantage of the invention is providing a gate dielectric structure having a reduced effective electrical thickness. 
     This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a cross-sectional diagram of a transistor having gate dielectric according to the invention; and 
     FIGS. 2A-2D are cross-sectional diagrams of a partially fabricated transistor at various steps in the fabrication of the transistor of FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention will now be described in conjunction with a 0.1 micron MOSFET transistor. It will be apparent to those of ordinary skill in the art that the benefits of the invention can be applied to other transistor sizes with appropriate scaling of the dimensions described herein. The benefits can also be applied to transistor structures different from that described below, such as those transistors having raised source/drain regions. 
     A MOSFET transistor  100  having a gate stack  104  according to the invention is shown in FIG.  1 . Transistor  100  is located in semiconductor body  102  and is separated from other transistors (not shown) by isolation regions  112 . As shown isolation regions  112  are shallow trench isolation. However, other isolation mechanisms known in the art may alternatively be used. Source/drain regions  114  and drain extension regions  116  are located in semiconductor body  102  on opposite sides of gate stack  104 . 
     Gate stack  104  comprises a multi-layer gate dielectric. The first layer is an interface control layer preferably a silicon-oxynitride layer  106 . It has a physical thickness on the order of around 5 to 20 Angstroms (preferably around 10 Angstroms) and a dielectric constant greater than that of silicon dioxide (˜4) and less than that of silicon nitride (˜7). Overlying silicon-oxynitride layer  106  is a high-K dielectric layer  108 . High-K is used herein to refer to a dielectric material having a dielectric constant greater than  10 . Layer  108  will typically comprise an oxygen-containing high-K dielectric material such as Ta2O5, BaTiO3, TiO2, CeO2, or BST. However, layer  108  may alternatively comprise a high-K material that is formed using a process that allows oxygen from another source to enter the environment. The thickness of high-K layer  108  is on the order of 50 Å to 110 Å. The gate stack further comprises a layer of nitride  107  which overlies the high-K dielectric with a thickness on the order of 2-10 Angstroms. 
     Gate stack  104  further comprises a gate electrode  110  overlying the nitride layer  107 . Gate electrode  110  preferably comprises polysilicon as the nitride layer  107  will prevent the formation of silicon dioxide. Gate electrode  110  can also comprise a metal. The metal chosen may need to be matched to the dielectric layer  108  in terms of process integration and its work function that ultimately dictates the threshold voltage of the device. In an embodiment of the invention, the high-K layer  108  comprises Ta2O5 and the gate electrode  110  comprises a layer of tungsten (W) overlying the nitride layer  107 . 
     A method for forming gate stack  104  according to an embodiment of the invention will now be described. A thin silicon dioxide layer  118  is formed over the surface of semiconductor body  102  as shown in FIG.  2 A. Layer  118  has a thickness on the order of 10 Angstroms to 20 Angstroms (preferably around 15 Angstroms). Layer  118  may be as thin as possible while still obtaining a continuous layer of oxide. The maximum thickness for layer  118  depends on the desired electrical thickness of the final gate dielectric. For practical purposes, this may be 15-20 Angstroms for a 0.10 micron technology. 
     Referring to FIG. 2B, silicon dioxide layer  118  is subjected to remote plasma nitridation (RPN). RPN converts layer  118  from silicon dioxide to silicon-oxynitride layer  106 . The effective electrical thickness of layer  106  is decreased due to a change in the dielectric constant of the material. Silicon oxynitride layer  106  has a physical thickness on the order of 15 Angstroms and a dielectric constant greater than that of silicon dioxide (˜4) and less than that of silicon nitride (˜7). 
     The source of nitrogen for the plasma may be a nitrogen containing precursor such as N 2  or NH 3  or their mixture with each other or any other inert gas (He, Ar, etc.) or oxidizing gas (NO, N 2 O, O 2 , etc.). The plasma is preferably a high density plasma. The plasma may be generated by any one of a number of sources. For example, one of the following sources may be used: helicon; helical-resonator; electron-cyclotron resonance; or inductively coupled. The substrate  102  can be unbiased, in which case the ionized substances are accelerated by the plasma potential (on the order of 20 Volts) and then implanted into the silicon dioxide layer  118  surface. A bias can be applied to the substrate  102  to further accelerate the ions from the plasma and implant them deeper into the surface. Either a DC or RF bias may be applied to the substrate  102 . As an example, the following process conditions may be used: plasma density between 1×10 10  to 1×10 12 ; nitrogen flow between 1 and 100 sccm; pressures on the order of 1 to 50 mTorr, temperature in the range of 77 K to 773 K; substrate bias in the range of 0 to 50 Volts; and a duration in the range of 10 to 60 seconds. 
     After RPN, high-K dielectric layer  108  is formed over silicon oxynitride layer  106  as shown in FIG.  2 C. Layer  108  will typically comprise an oxygen-containing high-K dielectric material such as Ta2O5, BaTiO2, TiO2, CeO2, or BST. However, layer  108  may alternatively comprise a high-K material that is formed using a process that allows oxygen from another source to enter the environment. The method for forming high-K dielectric layer  108  will vary depending on the material used. Improved methods for depositing many of these materials are currently being developed. 
     In a preferred embodiment of the invention, Ta2O5 is used as layer  108 . It may be formed in the following manner using a LPCVD process. After RPN, the device is loaded into a furnace at low temperature (e.g., ˜300° C.). The wafers are preferably placed in alternating slots of a ring boat with side dummy wafers at the ends. The boat and side dummy wafers should be coated with at least 100 Å of TaO5, otherwise thickness uniformity may be a problem. 
     After loading, the furnace pump is purged and the temperature is ramped to the deposition temperature (i.e., on the order of 410-450° C.) and stabilized before the reactive gases are introduced. N2 or NH3 may be used as a carrier gas during the heating phase. NH3 may ensure that the surface stays nitrided. 
     A metalorganic source is then introduced to react with oxygen at low pressure for deposition. Metalorganic sources include tantalum pentaethoxide (TAETO) or tantalum tetraethoxide (TATDMAE). The tantalum sources are viscous liquids and could be supplied in bubblers with a carrier gas such as N2 bubbled through to carry the tantalum to the furnace. However, the bubbler would have to be operated at 120-150° C. and long-term stability may be a problem. A preferred delivery technique is to use a positive displacement or CVD pump. The tantalum source is then dispensed to a heated vaporizer and mixed with a carrier gas such as N2 and then delivered to the furnace. alternatively, the tantalum source may be supplied via a liquid MFC (mass flow controller) that injects the source liquid into the heated vaporizer. 
     Exemplary Deposition Conditions are: 
     Pressure: 0.1 to 1 Torr (typically 0.2-0.3 Torr) 
     TAETO flow: 0.1 to 1.0 cc/min (typically 0.2-0.4 cc/min) 
     O2 flow: 500-1000 sccm (typically 1000 sccm) 
     N2 carrier flow: 500-1000 sccm (typically 750 sccm) 
     Temperature: 410-450° C. 
     Time: on the order of 10 minutes with a growth rate of 10-15 Å/min. 
     After deposition, the furnace tube is cycle purged to remove any TAETO before cooling down to unload temperature and to bring the chamber back to atmospheric pressure. The overall process takes approximately 3-4 hours. Alternatively, a RTP process may be used with temperatures of 400-500° C. and shorter duration. 
     Following high-K formation, the stack is again subjected to the remote plasma process described above and a top portion of the high-K dielectric will be converted to a nitride  107 . The nitride layer  107  will have a thickness on the order of 2-50 Angstroms. The formation of the nitride layer  107  may be followed by an optional anneal to reduce leakage and provide for a robust interface. For example, the device may be annealed in nitrogen at a temperature on the order of 800° C. for a duration on the order of two minutes in an RTA system or for on the order of 30 minutes in a furnace. 
     Referring to FIG. 2D, gate electrode material,  110  is deposited over the nitride layer  107 . Gate electrode  110  preferably comprises polysilicon. In another embodiment, the gate electrode comprises a metal gate. The metal chosen may need to be matched to the dielectric layer  108 . For example, gate electrode  110  may comprise a stack of tungsten, aluminum, or copper along with the nitride layer  107 . In another embodiment, gate electrode  110  comprises a layer of tungsten (W) having a thickness on the order of 800 Å overlying a layer of titanium-nitride (TiN) having a thickness on the order of 200 Å. 
     Finally, gate electrode material  110 , high-K layer  108  and silicon-oxynitride layer  106 , and nitride layer  107  are patterned and etched to form gate stack  104  as shown in FIG.  2 A. Fabrication of transistor  100  is completed by implanting drain extension regions  116 , depositing and etching a dielectric to form sidewall spacers  117 , and implanting source/drain regions  114 . 
     In another embodiment of the instant invention, the high-K dielectric is formed directly on the silicon substrate  102 . The formation of the remaining layers of the dielectric stack will then be as described above. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.