Abstract:
A D.C. power control for a D.C. solenoid actuator which may be used for a D.C. solenoid operated valve uses a timer circuit for switching from an initial high pull-in power after a predetermined delay to a low hold power for the valve solenoid utilizing a pulse control where the valve &#34;on&#34; time is held constant and the &#34;off&#34; time is varied. The pulses are high frequency to prevent the valve from switching with each of the pulses while enabling the average current in the valve solenoid coil to be controlled independently between the pull-in and hold current values.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to solenoid actuators. More specifically, the present invention is directed to power control circuits for direct current solenoid valves. 
     2. Description of the Prior Art 
     Direct current (D.C.) operated solenoid valves have functional characteristics that make them unacceptable for long stroke applications. The power required for long stroke valves is very high for D.C. solenoid operators, and since with D.C. there is no impedance change from an open magnetic gap to a closed magnetic gap, the holding power is the same as the pull-in power. This produces thermal problems which can result in coil burnout. In order to enable the D.C. operated solenoid valves to be used successfully in long stroke applications, it is necessary to reduce or eliminate the thermal problem associated with the conventional long stroke D.C. operation while providing high current pull-in and low current hold in a cost effective package which could fit within the normal valve housing. Accordingly, it is desirable to provide a power management system for a D.C. valve operator solenoid to control the D.C. valve without the aforesaid problems. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an improved D.C. power control circuit for a D.C. solenoid actuator. 
     Another object of the present invention is to provide an improved D.C. power control circuit for a D.C. valve operator solenoid. 
     In accomplishing these and other objects, there has been provided, a D.C. power control circuit having a source of high frequency pulses, circuit means for applying the pulses to an electromagnetic solenoid and means for reducing the number of pulses applied to the solenoid after an initial full number of pulse applications. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A better understanding of the present invention may be had when the following detailed description is read in connection with the accompanying drawings, in which 
     FIG. 1 is shown a schematic illustration of an example of a D.C. power control circuit for a D.C. valve embodiment of the present invention and 
     FIG. 2 is a waveshape diagram showing the high and low current operation of the output of the circuit shown in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1 in more detail, there is shown a timer 2 having a control input &#34; ○4 &#34; connected via line 4 to a control signal input terminal 6. An output line 8 from the output terminal &#34; ○3 &#34; of the timer 2 is connected through a first resistor 10 to a Darlington amplifier having a pair of transistors 12 and 14 and a second resistor 13. The D.C. solenoid coil 16 for a solenoid valve (not shown) is connected between the output collector of the Darlington amplifier and a direct current voltage terminal 18. A first diode 20 is connected across the solenoid coil 16 to maintain the current flow in one direction for the solenoid coil 16 whereby any backward current would be bypassed by the diode 20 which functions as a suppressor. A delay or timing circuit 21 includes a second diode 22 having one side connected to the control input terminal 6 and a second side connected to one side of a first capacitor 24. The other side of the first capacitor 24 is connected through a third resistor 26 to a common ground connection. A third diode 28 is arranged to provide a bypass for the second resistor 26. Concurrently, a fourth resistor 30 is connected from the second side of the diode 22 to the common ground connection. 
     The timing circuit 21 comprising the first capacitor 24, the second diode 28 and the second and third resistors 26, 30 forms a signal delay circuit which determines when a third transistor 32 is switched to a low power mode of operation. Specifically, the junction between the capacitor 24 and the resistor 26 is connected through a fifth resistor 33 to the base electrode input of the third transistor 32. A sixth resistor 36 is connected across the emitter and collector electrodes of the third transistor 32 while the collector electrode is connected through a second capacitor 38 to a common ground connection. The emitter of the third transistor 32 is connected through a sixth resistor 40 to the &#34; ○7 &#34; input of the timer 2 while the collector electrode is connected directly to the &#34; ○6 &#34; input of the timer 2. A third diode 41 is also connected across the &#34; ○6 &#34; and &#34; ○7 &#34; inputs of the timer 2. The &#34; ○5 &#34; terminal of the timer 2 is connected to ground through a third capacitor 39 while the &#34; ○2 &#34; terminal is connected to &#34; ○6 &#34; terminal. The power input terminal &#34; ○8 &#34; of the timer 2 is connected to a D.C. power regulating circuit 42 through a seventh resistor 43. The power regulating circuit 42 includes a fourth transistor 44, an eighth resistor 45, a ninth resistor 46, a voltage limiting Zener diodes 47 and a fourth capacitor 48. A D.C. power input terminal 49 is connected to a source of D.C. power (not shown) which is regulated by the regulating circuit 42 and applied to the timer 2 and the solenoid coil power terminal 18. 
     In operation, the circuit of the present invention is effective to provide a high pull-in current which is the average of the output pulses from the timer 2. Specifically, when the control input signal applied to the control terminal 6 goes &#34;high&#34;, e.g., 5 volts, the third transistor 32 and the timer 2 are turned &#34;on&#34;. The timer 2 now runs as a free-running multivibrator producing a high frequency, e.g., 2 kHz, output which drives the Darlington amplifier consisting of the first and second transistors 12,14 whereby the average current through the solenoid coil 16 is controlled by the pulses applied to the first transistor 12. The timing circuit 21 will determine when the third transistor 32 is turned &#34;off&#34; to switch the average current to the low power, or hold, mode. Thus, when the valve &#34;off&#34; time is increased, the average current in the coil 16 will decrease to the &#34;hold&#34; value. On the other hand, when the valve is turned &#34;on&#34;, i.e., during the pull-in current value, the &#34;off&#34; time is very short. 
     After a suitable delay time of approximately two times the &#34;pull-in&#34; time, e.g., 4 to 100 millisecond, the power to the coil is switched to the low power or &#34;hold-in&#34; mode. Specifically, as the first capacitor 24 charges up from the input terminal 6 through the diode 22, the third transistor 32 is eventually turned &#34;off&#34;. The voltage drop across the resistor 36 is now effective to determine the holding current, i.e., the valve &#34;off&#34; time. The free running frequency of the timer 2 is selected to be high enough, to eliminate the switching of the valve from &#34;on&#34; to &#34;off&#34; with the output pulses from the timer 2. Thus, the average current and therefore the average power to the valve is controlled. The high and low power current outputs are shown in the waveshape diagram of FIG. 2., i.e., waveshape A illustrating the low power operating mode and waveshape B illustrating the high power operating mode. 
     Accordingly, a D.C. operated solenoid valve can be used in a power control circuit for extending the pressure/flow requirements to reduce the powe supplied to the solenoid operator and/or to provide a universal type valve whose operating characteristics can be selected by the power control circuit. With the control circuit, power management optimization is realizable, and a direct microprocessor interface can be provided as a one gate load for operating the timer 2. Further, overheating and/or burnout of the solenoid coil 16 is eliminated, e.g., pull-in power can be 14 watts while a comparable hold-in power would be 380 milliwatts whereby power supply requirements are drastically reduced. Finally, it should be noted that while the present invention has been presented in the context of a D.C. valve solenoid operating circuit, the present invention is obviously applicable to other D.C. operated electromagnetic circuits which can operate between high and low power modes, e.g., electromagnetic relays. 
     The following is a detailed list of the circuit components used in a preferred construction of the illustrated example of the present invention as shown in the single figure drawing: 
     
         ______________________________________Timer             Motorola Type LM555Transistor 32,44  2N3904Transistor 12     MPSU45Transistor 14     2N5655Diodes 22,41      IN914Diodes 20,28      IN4006Diodes 42         IN5239Resistor 10       IKResistors 13,45   100Resistor 26       Selected for ValveResistor 30       27KResistor 33       68KResistor 36       Selected for ValveResistor 40       4.1KResistor 43       3.22KResistor 46       1.8KCapacitor 24      1 μfCapacitors 38,39  .001 μfCapacitor 48      .47 μf______________________________________ 
    
     Accordingly, it may be seen that there has been provided, in accordance with the present invention, an improved D.C. power control circuit for a D.C. solenoid operator.