Abstract:
A switching circuit is provided to process a DC voltage and apply a low frequency AC voltage, having a trapezoidal waveform, to a co-axial cable transmitting the low frequency AC voltage to a load which may be powered by the low frequency AC voltage as well as a DC voltage. In one specific embodiment two of the switches are connected as part of buck regulation circuits to serve a dual purpose of polarity switching and regulation.

Description:
FIELD OF THE INVENTION 
     This invention relates to a power train to supply a low frequency AC voltage to a co-axial load. It particularly concerns a switching circuit to convert DC (e.g.,battery) voltage to a low frequency AC voltage and to such a switching circuit providing a regulated low frequency AC voltage with a defined waveform. 
     BACKGROUND OF THE INVENTION 
     In some power system loads requiring a DC voltage, the power equipment used therein has operating characteristics that are desirable to avoid, in certain circumstances. An example is the supplying of a DC voltage over a co-axial cable. Corrosion becomes a serious problem if the co-axial cable is damaged however so slightly. 
     Corrosion can be substantially eliminated by converting the DC voltage to an AC voltage, however the requirement of the provision of a DC voltage places strict limits upon this option. 
     DC voltage equipment can, in many instances be powered by an extremely low frequency AC voltage. The provision of a low frequency AC voltage by inverter circuits is not economically and technically efficient in many applications, however, because of the size and expense of the magnetics required at low frequency. 
     A voltage polarity switch, of the prior art, is configured as a bridge circuit in the schematic of FIG. 3. In this particular arrangement all of the illustrated FET switches Q 1 , Q 2 , Q 3  and Q 4  are driven by a PWM signal which is divided into PHASE-A and PHASE-B PWM series of pulses. This particular circuit is most profitably used with the generation of low frequency voltages with a substantially sinusoidal waveform. A sinusoidal waveform is not very suitable for powering DC voltage equipment with a low frequency AC voltage. Such a circuit is disclosed in &#34;Power Electronics, Converters, Applications, and Design&#34; by Ned Mohan et al, Wiley, c1989 pg. 115, 116. 
     SUMMARY OF THE INVENTION 
     Therefore in accordance with the invention, a polarity switch is provided to process a DC voltage into a very low frequency AC voltage with a trapezoidal waveform, as described in the claims. 
     In an illustrative embodiment described, a switching circuit is provided to process a DC voltage and apply a regulated low frequency AC voltage, having a trapezoidal waveform, to a co-axial cable which is transmitting the low frequency AC voltage to a load which may be powered by the low frequency AC voltage as well as a DC voltage. Two of four of the switches are connected as part of buck regulation circuits to serve a dual purpose of polarity switching and regulation. All switches, of the polarity switching circuit are paired and connected to alternately connect a DC voltage polarity to a co-axial cable. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic of a H bridge polarity switch with dual use switches; 
     FIG. 2 is a schematic of a polarity switch following a regulator, and 
     FIG. 3 is a schematic of a prior art full bridge inverter type polarity switch, discussed above. 
    
    
     DETAILED DESCRIPTION 
     A polarity switch, as shown in the FIG. 1, includes four FET power switches Q 1 , Q 2 , Q 3  and Q 4  connected into a power train in the form of an H bridge connection. Positive and negative polarities of a DC voltage are accepted at the input terminals designated V DC  + and V DC  -. V DC  + is connected to the drains of Q 1  and Q 3 , respectively. V DC  - is connected to the source of Q 2  and to the source of Q 4 . The source of Q 1  is clamped to V DC  - by the diode CR1 and the drain of Q 2  is clamped to V DC  + by the diode CR2. The two polarity switches Q 1  and Q 2  are isolated from one another by the two inductors L 1  and L 2  so that any overlap in conduction between the two polarity switches, during a phase/switching state transition, is not destructive to the polarity switches. 
     A phase clock CLK generates alternate phases A and B which are applied, via the PHASE-A and the PHASE-B terminals to the gate terminals of the polarity switches Q 3  and Q 4  enabling these switches to alternately conducting to one. The alternate phases A and B are also applied to the gate circuits GA and GB respectively. The A and B phase signals enable transmission, via the gate circuits, of a PWM drive signal supplied by a PWM circuit PWM-REG. PWM-REG supplies a high frequency pulse width modulated signal whose modulation permits regulation of the DC voltage supplied at the inputs V DC  - and V DC  + by the power switches Q 2  and Q 1 , respectively. The regulated output voltage difference, between the two output terminals INNER and OUTER, is defined as the voltage of the inner sheath of the co-axial cable minus the voltage of the outer sheath of the co-axial cable. 
     The immediate lead to be energized is a co-axial cable to which an INNER output lead and an OUTER output lead is connected to the inner and outer sheath of the co-axial cable, respectively. The source of the switch Q 1  and the drain of the switch Q 2  are connected to the INNER output lead via the filter/isolation inductors L 1  and L 2  respectively. The source of switch Q 2  is also connected to the source of switch Q 4  and the drain of switch Q 1  is connected to the drain of Q 3 . The common node N of the source of switch Q 3  and the drain of switch Q 4  is connected to the OUTER output lead connected to the outer sheath of the co-axial cable. 
     In operation the polarity switch responds to the alternating PHASE-A and PHASE-B signals to generate an alternating polarity trapezoidal waveform applied to the output co-axial cable. The switches Q 3  and Q 4  alternately connect the OUTER lead to the V DC  + and V DC  - voltages, respectively. The switches Q 1  and Q 2  operate at the PWM frequency and in conjunction with L 1  and L 2  operate as buck regulators to regulate the voltage applied by the INNER output lead to the inner sheath of the co-axial cable. During PHASE-A the FET switch Q 2  is modulated at the PWM frequency, applied via gate GA, with a controlled duty cycle to act as a buck regulator and supply a regulated negative voltage to the INNER output Q 3  connects V DC  + to the OUTER output lead. CR2 acts as a clamp diode for the buck regulator and conducts when Q 2  is off. L 2  acts as the buck regulator choke. When PHASE-B occurs the outer sheath of the co-axial cable is connected via the OUTER output lead and Q 4  to the voltage V DC .spsb.-. Q 1 , CR1 and inductor L 1  operate as a buck regulator to supply a regulated positive voltage to the INNER output lead and in turn the inner sheath of the co-axial cable. Q 1  is modulated by the PWM drive supplied through the gate GB. Q 1  source is isolated from Q 2  drain by the two separate buck regulator chokes, L 1  and L 2  to insure that high speed diodes CR1 and CR2 clamp the currents of Q 1  and Q 2  respectively upon turn off; and not allow the slow drain to source diodes inherent in Q 1  and Q 2 , to facilitate a cross-connect. The faster diodes improve efficiency and reduce EMI. Also, the two inductors serve to isolate Q 1  from Q 2 , so that if they are both on simultaneously for a short period, large destructive currents do not flow. 
     When PHASE-A is activated the outer sheath of the co-axial cable is connected to the V DC  + voltage through Q 3 . When the PHASE-B is activated the outer sheath of the co-axial cable is connected to the V DC  - voltage. Q 3  and Q 4  are alternately driven conducting in phase with the alternation of the PHASE-A and PHASE-B states. Q 1  and Q 2  are driven by the PWM pulse series to provide regulation of the voltage supplied to the co-axial cable. 
     A linear regulator LR is provided at the input to the voltage polarity switching circuit of FIG. 2. This eliminates the need for the gates GA and GB shown in the circuit of FIG. 1. The power train comprising FET switches Q 1 , Q 2 , Q 3  and Q 4  is similar to that of the circuit of FIG. 1 except that the pre regulator LR is connected to the input hence relieving the FET switches Q 1  and Q 2  from the responsibility of regulation. The regulator LR may be comprised of any type regulator switching, series etc. The requirements of size and efficiency, however, generally require the use of a switching type regulator.