Abstract:
A method of fabricating a semiconductor device includes forming a coating type carbon film on a semiconductor substrate, patterning the coating type carbon film according to trenches formed in the semiconductor substrate and having different opening widths, and etching the semiconductor substrate with the patterned coating type carbon film serving as a mask, thereby simultaneously forming a deeper trench in a part with a larger opening width and a shallower trench in another part with a smaller opening width.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-207367, filed on Jul. 14, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor device having a plurality of trenches with different opening widths and a method of fabricating the semiconductor device.  
         [0004]     2. Description of the Related Art  
         [0005]     Semiconductor devices of the above-described type include a semiconductor storage device provided with a number of memory cell transistors, for example. One type of the memory cell transistor is formed with an element isolation region called “shallow trench isolation (STI)” in order that memory cell transistors and peripheral circuit transistors may electrically be isolated. The STI is formed by burying insulating films in a surface of a semiconductor substrate. Each transistor is formed in an active region isolated by the STI.  
         [0006]     In a memory cell transistor forming region, a trench of the STI has a smaller width and a smaller depth in order that a degree of integration may be improved. The depth of the trench is rendered smaller in order that the insulating film may desirably be buried in the trench with a small opening width. Furthermore, regarding high-breakdown voltage transistors in the peripheral circuit region, the trench has a larger width and a larger depth than the trench at the memory cell transistor side in order that a prescribed breakdown voltage may be ensured.  
         [0007]     In view of these limitations, trenches with different depths in a chip need to be formed in order that the STI may meet the above conditions. For this purpose, a photolithography process has conventionally been carried out twice so that a deep part and a shallow part have been individually formed.  
         [0008]     However, carrying out the photolithography process twice is undesirable from the viewpoint of cost reduction. Furthermore, the photolithography process carried out twice results in a stepped portion due to etching in a boundary between the deeper and shallower trenches. A dummy region has conventionally been provided for preventing an element property from being adversely affected by the stepped portion.  
         [0009]     JP-A-2000-323564 discloses a technique of carrying out the photolithography process only once even when the trenches with different depths are formed. In the disclosed technique, the photolithography process is carried out only once so that trenches having the same depth are formed in the memory cell region and the peripheral circuit region. A hydrogen heat treatment is carried out in a second half process of the semiconductor manufacture so that the bottom of the narrow trench is raised upward. As a result, the trenches having different depths are formed.  
         [0010]     However, the hydrogen heat treatment is required although the photolithography process can be reduced. Accordingly, when a process in which a gate electrode is previously formed and separated by the forming of the element isolation regions, there is a possibility that the previously formed gate oxide film may be damaged by hydrogen anneal, whereupon the film quality may be reduced with the result of reduction in the reliability of elements.  
       BRIEF SUMMARY OF THE INVENTION  
       [0011]     Therefore, an object of the present invention is to provide a semiconductor device in which the number of execution times of the photolithography process can be reduced by once but another step such as the hydrogen heat treatment need not be added, and a method of fabricating the semiconductor device.  
         [0012]     The present invention provides a method of fabricating a semiconductor device comprising forming a coating type carbon film on a semiconductor substrate, patterning the coating type carbon film according to trenches formed in the semiconductor substrate and having different opening widths, and etching the semiconductor substrate with the patterned coating type carbon film serving as a mask, thereby simultaneously forming a deeper trench in a part with a larger opening width and a shallower trench in another part with a smaller opening width.  
         [0013]     The invention also provides a semiconductor device comprising a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, a plurality of memory cell transistors formed in the memory cell forming region of the substrate, a first insulating film formed in a first trench so as to isolate the memory cell transistors, a plurality of peripheral circuit transistors formed in the peripheral circuit region of the substrate, and a second insulating film formed in a second trench so as to isolate the peripheral circuit transistors, the second insulating film having a larger opening width and a lower aspect ratio than the first insulating film, wherein the first and second trenches are formed by an etching technique in which a coating type carbon film serves as a mask controlling an etching speed according to the opening width. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     Other objects, features and advantages of the present invention will become clear upon reviewing the following description of the embodiment with reference to the accompanying drawings, in which:  
         [0015]      FIGS. 1A and 1B  are schematic sectional views of a semiconductor device according to one embodiment of the invention, showing the condition immediately after completion of an etching process;  
         [0016]      FIGS. 2A and 2B  are typical sectional views of the semiconductor device at a phase of the fabrication process (phase 1 );  
         [0017]      FIGS. 3A and 3B  are typical sectional views of the semiconductor device at another phase of the fabrication process (phase 2);  
         [0018]      FIGS. 4A and 4B  are typical sectional views of the semiconductor device at a further another phase of the fabrication process (phase 3);  
         [0019]      FIGS. 5A and 5B  are typical sectional views of the semiconductor device at a still further another phase of the fabrication process (phase 4); and  
         [0020]      FIG. 6  is a graph showing the relationship between carbon content and the difference between trench depths. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]     One embodiment of the present invention will be described with reference to the accompanying drawings. The invention is applied to a NAND flash memory in the embodiment. In a fabrication process of the NAND flash memory in the embodiment, trenches are formed in a semiconductor substrate which has previously been formed with part of film structure for a gate electrode. The structure of the semiconductor device in the trench forming steps and the fabrication process of the semiconductor device will hereinafter be described.  
         [0022]     Referring to  FIGS. 1A and 1B , schematic sectional views of the semiconductor device are shown. These views show the condition immediately after completion of an etching process. Trenches  4   a  and  4   b  are formed in a memory cell region  2  and a peripheral circuit region  3  so as to have different depths respectively. On an upper surface of the silicon substrate  1  are deposited a silicon oxide film  5  serving as a gate insulating film, a polycrystalline silicon film  6  composing a floating gate, a silicon nitride film  7  serving as a stopper in a chemical mechanical polishing (CMP) process, and a coating type carbon film  8  (a coating film containing carbon) sequentially. These films constitute parts of gate electrodes of the memory cell and peripheral circuit regions  2  and  3 .  
         [0023]     The coating type carbon film  8  will be described in conjunction with an etching process by a reactive ion etching (RIE) process. The coating type carbon film  8  is generally defined as a film which is formed by coating a chemical containing carbon (C) similar to photoresist and has not less than 80 weight % carbon after the baking. An ordinary resist film has a carbon content of about 70 weight %. Thus, the carbon content of the coating type carbon film  8  is higher than the ordinary resist film. Furthermore, the chemical of the coating type carbon film is a material similar to photoresist containing a high carbon content but cannot be exposed to light and developed as the photoresist is processed.  
         [0024]     Reference symbol A 1  in  FIG. 1A  designates a gap between memory cell transistors in the memory cell region  2 , namely, an opening width of the trench. The opening width A 1  is set according to the design standard which can ensure breakdown voltage and enables processing. Furthermore, reference symbol A 2  in  FIG. 1B  designates a gap between high breakdown voltage transistors in the peripheral circuit region  3 , namely, an opening width of the trench. The opening width A 2  is set so as to be wider than the opening width A 1  in order that the necessary breakdown voltage may be ensured.  
         [0025]     Furthermore, the depth D 1  of the trench  4   a  having the smaller opening width at the memory cell region  2  is smaller than the depth D 2  of the trench  4   b  having the larger opening width at the peripheral circuit region  3 . In the trench forming process, the trench  4   a  in the memory cell region  2  and the trench  4   b  in the peripheral circuit region  3  are simultaneously processed so as to have different depths.  
         [0026]     The fabrication process for forming the trenches  4   a  and  4   b  will now be described with further reference to  FIGS. 2A  to  5 B. Firstly, a silicon oxide film  5  serving as the gate insulating film is formed on the silicon substrate  1  so as to have a film thickness of 10 nm as shown in  FIGS. 2A and 2B . The polycrystalline silicon film  6  is continuously formed on the silicon oxide film  5  so as to have a film thickness of 140 nm. The silicon nitride film  7  is formed on the polycrystalline silicon film  6  so as to have a film thickness of 90 nm. The polycrystalline silicon film  6  constitutes the floating gate. The remaining polycrystalline silicon film is formed after formation of the trenches. The silicon nitride film  7  functions as a stopper in the CMP process in the formation of the STI.  
         [0027]     Subsequently, the silicon nitride film  7 , the polycrystalline silicon film  6 , the silicon oxide film  5  and the silicon substrate  1  are etched so that the photolithography process is carried out for formation of the trenches  4   a  and  4   b . Firstly, a liquid phase of coating type carbon material  8  is coated on an upper surface of the silicon nitride film  7  and then baked at a baking temperature of 200° C. so that the coating type carbon film  8  having a film thickness of 450 nm is formed. In this case, a recommended baking temperature for the coating type carbon film  8  ranges from 50 to 600° C. The film thickness of the coating type carbon film  8  ranges from 300 to 500 nm.  
         [0028]     Subsequently, a coating type oxide film  9  is coated on an upper side of the coating type carbon film  8  so as to have a film thickness of 100 nm and a resist  10  is formed on the upper side of the coating type carbon film  8 . The coating type oxide film  9  is formed by coating a silica film forming coating liquid such as polysilazane.  
         [0029]     The resist  10  is then exposed to light in a predetermined pattern and developed thereby to be formed into a resist pattern  10   a , as shown in  FIGS. 3A and 3B . The coating type oxide film  9  is then etched with the resist pattern  10   a  serving as a mask thereby to be formed into a coating type oxide film pattern  9   a , as shown in  FIGS. 4A and 4B . The coating type carbon film  8  is then processed with the coating type oxide film pattern  9   a  serving as a mask. A resist pattern  10   a  has already been etched thereby to disappear, and the coating type oxide film pattern  9   a  has been rendered thinner than at the film formation.  
         [0030]     Subsequently, the silicon nitride film  7  is etched with the coating type oxide and carbon film patterns  9   a  and  8   a  serving as masks, as shown in  FIGS. 5A and 5B . The coating oxide film pattern  9   a  has already been etched thereby to disappear, and the coating type carbon film pattern  8   a  has been rendered thinner than at the film formation.  
         [0031]     The polycrystalline silicon film  6  and the silicon oxide film  5  are then etched with the patterns  8   a  and  7   a  serving as masks as shown in  FIGS. 1A and 1B . The silicon substrate  1  is also etched until a predetermined depth is reached. In this case, normal silicon etching conditions are employed in the step of etching the silicon substrate  1 . For example, hydrogen bromide (HBr), chlorine gas (Cl 2 ) and oxygen gas (O 2 ) are used at respective flow rates of 40 standard cubic centimeter per minute (SCCM), 90 SCCM and 30 SCCM. As a result, the depths of the trenches  4   a  and  4   b  differs from each other on the basis of the opening widths A 1  and A 2 .  
         [0032]     The following mechanism is conjectured when the etching process is carried out under the above-described conditions by the RIE process. Upon start of the etching process, silicon, Br ions and Cl ions react such that reaction products such as SiBrα and SiClβ are produced. These reaction products should be evacuated. Not all the reaction product is evacuated but part of the reaction product tends to remain on the silicon substrate.  
         [0033]     Furthermore, when carbon (C) contained in the coating type carbon film  8 , Si, Br and the like react together, a reaction product such as SiBrCθ is also produced. Since the vapor pressure of the SiC reaction product is low, most of the SiC reaction product is deposited on the silicon substrate  1 . On the other hand, part of the reaction product reacts with O 2  such that carbon is evacuated as COγ. Furthermore, since Cl ions react with a carbon film thereby to produce CCl product, an amount of Cl ion supplied to the silicon which is a film to be etched is reduced.  
         [0034]     Etching progresses while deposited reaction product and the substrate  1  are dug down. Accordingly, an amount of deposited low-pressure SiC reaction product is necessarily increased in the memory cell region  2  such that a difference in the etching rate is produced as compared with the peripheral circuit region  3 . More specifically, the etching rate in the memory cell region  2  becomes lower than the peripheral circuit region  3  by the microloading effect.  
         [0035]     In an actually fabricated semiconductor device, the trench  4   a  with the depth D 1  of 220 nm and the trench  4   b  with the depth D 2  of 360 nm were formed by a single etching process. Thus, the depths which were 1.6 times larger were formed simultaneously. The reason for this is considered as follows: carbon C serving as a basic material of the reaction product is supplied from the coating type carbon film  8  employed as the mask material, whereupon the etching rate was lowered at the memory cell region  2  side.  
         [0036]     The difference in the etching rate depends upon the use of the coating type carbon film  8  having a larger carbon content than the normal photoresist. As a result, trench depth D 1 &lt;trench depth D 2  when opening width A 1 &lt;opening depth A 2 . Furthermore, the degree of difference in the etching rate depends upon a carbon content. In order to verify this dependence, the inventors measured data from the following samples. The samples included sample (1) in which a tetraethyl orthosilicate (TEOS) film was formed on a base obtained by depositing a silicon oxide film and a silicon nitride film on a silicon substrate in turn and which had a carbon content of 0 weight %, sample (2) in which a coating type carbon film A was formed on the base and which had a carbon content of A weight %, and sample (3) in which a coating type carbon film B was formed on the base and which had a carbon content of B weight % when B&lt;A.  
         [0037]     The TEOS film and coating type carbon films A and B formed on the three substrates were etched by the photolithography process so that a pattern having opening widths corresponding to the memory cell region and the peripheral circuit region respectively were formed. The etching process was carried out on the silicon substrate under the same conditions as described above.  
         [0038]     Regarding the depths of trenches obtained as the result of the foregoing etching process, calculation was carried out to obtain the difference A (=D 2 −D 1 ) between the trench depths D 1  and D 2  of the memory cell region and the peripheral circuit region respectively.  FIG. 6  shows carbon content by weight % on the axis of abscissas and the difference Δ between the trench depths on the axis of ordinates. From the results as shown in  FIG. 6 , it is understood that the difference Δ changes according to a type of mask material or carbon content of mask material used in the forming of the trench. In other words, the difference Δ between the trench depths can be set to a desired level by selecting a carbon content of the mask material. This indicates that a plurality of trenches having desired different depths can simultaneously be formed by a single time of etching process. Consequently, a plurality of trenches having different depths can simultaneously be formed with high controllability.  
         [0039]     The invention should not be limited to the foregoing embodiment. The above-described embodiment may be modified or expanded as follows. The invention should not be limited to the process of forming trenches of the NAND flash memory. The invention may be applied to all types of semiconductor devices in which a plurality of trenches have different depths.  
         [0040]     The difference in the trench depth due to the difference in the opening width of the trench depends upon carbon content of the coating type carbon film  8  as described above. Additionally, there is a possibility that the difference in the trench depth may be changed by changing etching conditions. Thus, the carbon content and the etching conditions may be set in a complex manner so that a desired difference in the etching rate can be set, whereby the depths of the trenches can be controlled.  
         [0041]     The foregoing description and drawings are merely illustrative of the principles of the present invention and are not to be construed in a limiting sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the scope of the invention as defined by the appended claims.