Abstract:
The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store/load queue. In this invention, store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. When the modification is an invalidate, the check tests that the two share the same physical addressable location. When the modification is a validate, the check tests that the two involve the same data cache line.

Description:
TECHNICAL FIELD 
   The present invention relates generally to memory management and, more particularly, to a method of handling reload-hit-store in a high frequency system where stores only read the cache state information upon entering the queue. 
   BACKGROUND 
   The state of a cache may change between the placing of an operation storing data from the cache into the unit pipe or into the store portion of the store and load queue and the completion of the store operation. Store operations are queued to allow the program code to move forward. Because of the nature of store ordering requirements on cache coherency, older operations may modify the validity or location of the cache line within the data cache. These modifications may cause the cache state information which the store operations received upon issue to become old or outdated. Maintaining data integrity requires some mechanism to allow the cache state information for the store operations to be updated. 
   One way to update transactions is to read the cache state information. It may, however, be desirable to limit access to the cache. For example, a cache may be designed with a single read/write access point, or port. The design may afford simplicity, or be suitable for a smaller or low-power cache. With such a design, to read the cache state information, it is necessary to recycle operations through the unit pipe. Repeated recycling to update the store transaction requires many cycles and blocks other accesses to the cache. 
   Therefore, there is a need for a method of updating the cache state information for store transactions without reading the cache state information in a manner that addresses at least some of the issues associated with conventional updating of store transactions. 
   SUMMARY OF THE INVENTION 
   The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store and load queue. Store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  shows a block diagram of a unit pipe and load and store queue configured to update cache state information for the store transactions without using a cache access cycle; 
       FIG. 2  shows a flow diagram illustrating the updating of cache state information for store transactions after a modification of the data cache; 
       FIG. 3A  shows a block diagram of the organization of a data cache; and 
       FIG. 3B  shows a block diagram of the segments of a cacheable memory address. 
   

   DETAILED DESCRIPTION 
   In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. 
   It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor such as a computer or an electronic data processor in accordance with code such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise. 
     FIG. 1  shows a block diagram of a unit pipe and load and store queue configured to update cache state information for the store transactions without using a cache access cycle. Transactions enter the unit pipe  110  and proceed in stages, pipe stage  112 , pipe stage  114 , and pipe stage  116 . The ellipsis indicates the possible presence of other stages. The transactions entering the unit pipe  110  can be any type of operation, including but not limited to load, store, and snoop. 
   From the unit pipe  110 , transactions can pass to the load queue  120  or the store queue  130 . A number of load transactions have passed to the load queue  120 , load transactions  122 ,  124 , and  126 . The ellipsis indicates the possible presence of other transactions. A number of store transactions have passed to the store queue  130 , store transactions  132 ,  134 , and  136 . The ellipsis indicates the possible presence of other transactions. 
   When the cache is modified, the store transactions are examined to determine if they are affected by the modification to the cache. The address for the cache line being modified is compared to the address for the cache line of the storage transaction. In  FIG. 1 , the store transactions are the store transactions located in the unit pipe  110  and the store transactions located in the store queue  130 , store transactions  132 ,  134  and  136 . The address comparisons are performed on the store transaction in the unit pipe  110  in comparisons  152  and  154  and on the transactions in the store queue  130  in comparisons  156 ,  158 ,  160  and  162 . Load transactions  122 ,  124 , and  126  are not store transactions, and the address comparison is not performed on them. 
   Depending upon the result of the comparisons, and the nature of the modification to the cache, the store queue collision logic  140  updates the cache state information for those store transactions affected by the modification to the data cache. 
     FIG. 2  shows a flow diagram illustrating the updating of cache status information for store transactions after a modification of the data cache. In step  202 , the type of the modification to the cache is checked. When a cache line is invalidated, in step  204  the store queue collision logic  140  checks the store transactions to see if they used data from the same physical addressable location in the data cache as the invalidated cache line. If the comparison is a match, in step  206  the cache status information of the store is updated to indicate that its line has been removed from the cache. If the comparison does not produce a match, in step  208  there is no change to the cache status information for the store transaction. 
   When a cache line is validated, in step  210  the store queue collision logic  140  checks the store transaction to see if the store involves data from the same cache line. If so, in step  212 , the store transaction will be updated with the information about the validated cache line. In an embodiment with set-association and aliasing, the updated information includes the aliased location, congruence class and hit/miss information. In an embodiment of the invention which does not support aliasing, the aliased location information is not maintained and not updated. In an embodiment of the invention which does not have a set-associative cache, the congruence class information is not maintained and updated. If the store is not to the same cache line as the validated cache line, then in step  214  there is no change to the status information. 
   The nature of the comparison in steps  204  and  210  depend upon the method of organization of the cache and the method of assignment of data blocks to locations within the cache.  FIG. 3A  shows a block diagram of the organization of a cache. The cache  300  contains 32 addressable locations. Shown are addressable location  0  and addressable location  31 . Each addressable location contains a block of eight cache lines. Addressable location  0  contains the block of eight cache lines  302 . An aliasing feature narrows the block down to four cache lines. These remaining four lines are set-associative. The location of a cache line in the cache  300  can be specified by specifying the addressable location and the location within the block. Other embodiments of a cache do not support aliasing or set associativity. 
     FIG. 3B  shows a block diagram of the segments of a cacheable memory address. The defined address ranges from bit  22  to  63 . Bits  22 : 51  indicate the real page number. Bits  52 : 56  are used to address one of the 32 addressable locations of the cache. Bits  57 : 63  are the offset, the location of addressed data within the cache line. Whenever a store gets issued, a cache lookup is performed to determine whether the cache line is in the data cache or not. In an embodiment, the lookup returns an 8-bit vector to the store queue collection logic  140  identifying the location of the cache line within the block of eight cache lines contained at an addressable location. The 8-bit vector identifies a set and an aliased location. 
   Returning to the address comparison in Step  204 , in an embodiment with the cache organized as in  FIG. 3A  and the correspondence between the real address and the cache location as in  FIG. 3B , the comparison proceeds in stages. First, bits  52 : 56  of the real address of the cache line being invalidated are compared with bits  52 : 56  of the real address of the data contained within the store transaction to check that addressable locations in the data cache match. If so, the 8-bit vector kept by the store queue collection logic  140  is used to determine if the cache line being invalidated is at the same location within the block of eight at the addressable location as the cache line for the data. If the location within the eight cache lines also matches, then the store queue collection logic updates the 8-bit vector for the store transaction to indicate that the line is no longer valid. If either comparison is not a match, then the cache state information of the store transaction is not changed. 
   In other embodiments, the address comparison in Step  204  operates differently. For example, in a direct-mapped cache, the address comparison can simply be of the bits in the real address that determines the location of the cache line in the data cache. There is no need to store additional information about the location of the cache line within the data cache. 
   The comparison in step  210  is performed when a new cache line is allocated to the data cache. In this comparison, the full cache line of the new allocate is compared to the full cache line of the store operation. Bits  22 : 51  and bits  52 : 56  of each are compared. If there is a match, the store and the new allocate are actually the same cache line. The store transaction is updated by updating its 8-bit vector to describe the location to which the new cache line will be allocated. In other embodiments, the comparison may involve a different bit range. 
   This method of updating the cache status information of the store transactions updates the information without using a cache access cycle. Instead, information about changes in the cache flows through the unit pipe and the store portion of the store and load queue, and the store transactions there are updated. This method of updating thereby avoids a potential bottleneck in some designs. In a design with a single read/write access point, or port, this method avoids recycling operations through the unit pipe, the only way to read the cache state information. Repeated recycling to update the store transaction requires many cycles and blocks other accesses to the cache. 
   Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.