Abstract:
An internal voltage generator includes an output node, a bit line precharge voltage generating unit for generating a bit line precharge voltage, and a voltage drop block for dropping a voltage level of the bit line precharge voltage according to operating modes.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a semiconductor memory device, and more particularly, to a bit line precharge voltage generator of a semiconductor memory device. 
       DESCRIPTION OF RELATED ART 
       [0002]    In semiconductor memory devices, the biggest issue is the large capacity and high operating speed. In addition, many efforts have been made to develop semiconductor memory devices that can secure a reliable operation in a low power environment. Specifically, memory devices mounted on portable systems, e.g., mobile phones, notebook computers, etc., have been developed to minimize power consumption. 
         [0003]    One of these efforts is a technique to minimize power consumption in a core region of a memory device. The core region includes a memory cell, a bit line, and a word line and is designed based on an ultra-fine design rule. Therefore, the memory cell has a very small size and uses a low power. 
         [0004]    A bit line precharge is an important technique related to a cell data access speed. The bit line precharge is a technique to precharge a bit line to a predetermined voltage level prior to a data access in order to increase a data access speed. 
         [0005]    In such an environment, the memory cells are arranged in a mesh form in which a plurality of word lines and a plurality of bit lines are crossed. A gate residue occurs due to a manufacturing process problem when the word lines and the bit lines are formed, causing a bridge phenomenon. 
         [0006]      FIGS. 1A and 1B  are diagrams illustrating the generation of a bridge between a word line and a bit line. 
         [0007]    Referring to  FIG. 1A , a bridge A is caused by a reduced gate pitch size. 
         [0008]    The bridge A may be caused by a residue that is generated by a moat occurring during a shallow trench isolation (STI) process of forming a gate pattern for a word line, or may be caused when a gate shoulder portion is weakened during a process of forming a bit line contact. 
         [0009]    One of the results of the bridge is a gate pattern failure. 
         [0010]    The bridge serves as a resistive short between a word line and a bit line. The resistive short causes a bit line precharge voltage to leak out during a bit line precharge operation. 
         [0011]      FIG. 1B  illustrates various bridge resistances of the word line and the gate line because the gate pattern failure is different in size. When the semiconductor memory device is in a stand-by mode, a leakage current flowing from the bit line to the word line through the bridge having various resistances is in a range from several microamperes to several hundred microamperes. 
         [0012]      FIG. 2  is a circuit diagram illustrating the leakage phenomenon caused by the resistive short between the word line and the bit line. 
         [0013]    The resistive short occurs between the word line WL and the bit line BL due to the bridge A. 
         [0014]    In this case, when the semiconductor memory device is in a stand-by mode, the word line WL and the bit lines BL and BLB maintain a ground voltage VSS and a half core voltage VCORE/ 2 , respectively. Since a transistor N 1  isolating the bit lines BL and BLB is turned on, a leakage current continuously flows from the bit lines BL and BLB to the word line WL. The half core voltage VCORE/ 2  is a bit line precharge voltage VBLP outputted from a precharge unit  102  to precharge the bit lines BL and BLB. 
         [0015]    Such a manufacturing process problem increases the power consumption of the semiconductor memory device, degrading the power efficiency and performance of products. 
         [0016]    In the case of a 32M-P Pseudo SRAM, a leakage current per bridge is approximately 9 μA and deceases the yield by approximately 6% in favorable conditions to approximately 40% in unfavorable conditions. 
         [0017]      FIG. 3  is a graph illustrating the variation of a leakage current with respect to the number of bridges. 
         [0018]    As the number of bridges increases, a current ISB in a stand-by mode and a current ISB 1  in a self-refresh mode increases. 
         [0019]    These leakage currents are a significant factor to decrease the yield because a low-power product has a 7-10% portion based on the stand-by current ISB versus 1 bridge. 
         [0020]    To solve the leakage current problem, a voltage drop transistor having a fixed resistance is used. 
         [0021]    However, since an amount of a leakage current is different according to the size of the gate pattern failure, it is difficult to solve the leakage current problem by using the conventional voltage drop transistor, a so-called bleeder. That is, the conventional drop transistor cannot cope with the bridge having various resistances. 
       SUMMARY OF THE INVENTION 
       [0022]    It is, therefore, an object of the present invention to provide an internal voltage generator that can solve a leakage current problem caused by a bridge between a word line and a bit line in a power-down mode. 
         [0023]    It is another aspect of the present invention to provide an internal voltage generator that can obtain a stable and reliable bit line precharge voltage when a power down mode is exited. 
         [0024]    In accordance with an aspect of the present invention, there is provided an internal voltage generator including: an output node; a bit line precharge voltage generating unit for generating a bit line precharge voltage; and a voltage drop block for dropping a voltage level of the bit line precharge voltage according to operating modes. 
         [0025]    In accordance with another aspect of the present invention, there is provided a method for driving an internal voltage generator, including: dropping a bit line precharge voltage by a first voltage drop level in a normal mode, and outputting the dropped voltage to a bit line precharge voltage supply terminal; and dropping the bit line precharge voltage by a second voltage drop level in a power down mode, and outputting the dropped voltage to the bit line precharge voltage supply terminal, the second voltage drop level being greater than the first voltage drop level. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0026]    The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
           [0027]      FIGS. 1A and 1B  are diagrams illustrating the generation of a bridge between a word line and a bit line; 
           [0028]      FIG. 2  is a circuit diagram illustrating a leakage phenomenon caused by a resistive short between a word line and a bit line; 
           [0029]      FIG. 3  is a graph illustrating the variation of a leakage current with respect to the number of bridges; 
           [0030]      FIG. 4  is a circuit diagram of a bit line precharge voltage generator in accordance with an embodiment of the present invention; 
           [0031]      FIGS. 5A to 5C  are circuit diagrams of a voltage drop transistor driving unit shown in  FIG. 4 ; 
           [0032]      FIG. 6  is a circuit diagram of a test mode signal generating unit shown in  FIG. 4 ; and 
           [0033]      FIG. 7  is a graph illustrating a leakage current reduced by the bit line precharge voltage generator of  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0034]    An internal voltage generator in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
         [0035]      FIG. 4  is a circuit diagram of a bit line precharge voltage generator in accordance with an embodiment of the present invention. 
         [0036]    The bit line precharge voltage generator  200  outputs a bit line precharge voltage VBLPNEW having different voltage levels according to a power down mode and a non power down mode. 
         [0037]    The bit line precharge voltage generator  200  includes an NMOS transistor N 1 , a mode determining unit  201 , a plurality of voltage drop transistors P 1  to P 4 , a voltage drop transistor driving unit  202 , and a precharge voltage generating unit  203 . The NMOS transistor N 1  outputs a bit line precharge voltage VBLPNEW in a normal mode, and the mode determining unit  201  determines a power down mode and a non power down mode in response to a power down mode signal PWDD and a test mode signal TMSIG. The plurality of voltage drop transistors P 1  to P 4  have different resistances in the power down mode and output the bit line precharge voltage VBLPNEW having different voltage levels. The voltage drop transistor driving unit  202  selectively drives the voltage drop transistors P 1  to P 4 , and the precharge voltage generating unit  203  outputs a half core voltage VCORE/ 2 . 
         [0038]    The bit line precharge voltage generator  200  further includes a test mode signal generating unit  204  that outputs the test mode signal TMSIG for selecting an amount of voltage drop according to a leakage current. The test mode signal TMSIG is a signal used to check if the bit line precharge voltage VBLPNEW is substantially dropped. 
         [0039]    An output signal of the mode determining unit  201 , which is inputted to a gate of the NMOS transistor N 1 , has a high voltage (VPP) level in order to prevent an output signal of the NMOS transistor N 1  from being dropped by its threshold voltage (Vt). Alternatively, the NMOS transistor N 1  is provided with a slim transistor having a low threshold voltage. 
         [0040]    The mode determining unit  201  includes a first NOR gate NOR 1  receiving the power down mode signal PWDD and the test mode signal TMSIG, and a buffer INV 1  and INV 2  buffering an output signal of the first NOR gate NOR 1 . 
         [0041]    The voltage drop transistors P 1  to P 4  are PMOS transistors having different gate lengths. In  FIG. 4 , the first PMOS transistor P 1  has the smallest gate length and the fourth PMOS transistor P 4  has the greatest gate length. 
         [0042]      FIGS. 5A to 5C  are circuit diagrams of the voltage drop transistor driving unit  202  shown in  FIG. 4 . 
         [0043]    The voltage drop transistor driving unit  202  includes a transistor select source signal generating circuit  202 A, a fuse circuit  202 B, and a transistor select signal generating circuit  202 C. 
         [0044]    Referring to  FIG. 5A , the transistor select source signal generating circuit  202 A outputs first and second transistor select source signals TSEL 1  and TSEL 2  in response to different address signals ADD 1  to ADD 6 . 
         [0045]    A circuit configuration for generating the first transistor select source signal TSEL 1  will be described in more detail. A first NAND gate NAND 1  receives three different address signals ADD 1  to ADD 3 , and a second NAND gate NAND 2  receives an output signal of the first NAND gate NAND 1  as a first input signal. A third NAND gate NAND 3  receives an output signal of the second NAND gate NAND 2  as a first input signal and a first reset signal RST 1  as a second input signal and outputs a NANDed signal as a second input signal of the second NAND gate NAND 2 . A buffer INV 3  and INV 4  buffers an output signal of the second NAND gate NAND 2  to output the first transistor select source signal TSEL 1 . 
         [0046]    A circuit configuration for generating the second transistor select source signal TSEL 2  is the same as the circuit configuration for generating the first transistor select source signal TSEL 1 , except for the inputted address signals ADD 4  to ADD 6 . 
         [0047]    Referring to  FIG. 5B , the fuse circuit  202 B outputs first and second fuse cut signals FUCUT 1  and FUCUT 2  for selectively cutting the transistor select source signals TSEL 1  and TSEL 2 . 
         [0048]    A circuit configuration for generating the first fuse cut signal FUCUT 1  will be described in more detail. A first fuse FUS 1  cuts a power voltage (VDD) transmission line, and a second NMOS transistor N 2  changes the fuse cut signal FUCUT 1  to a logic low level in response to a power-up signal PWR. A stabilization circuit N 3 , N 4  and INV 7  outputs a stabilized fuse cut signal FUCUT 1 . A first buffer INV 8  and INV 9  buffers an output signal of the seventh inverter INV 7  to output the first fuse cut signal FUCUT 1 . 
         [0049]    A circuit configuration for generating the second fuse cut signal FUCUT 2  is the same as the circuit configuration for generating the first fuse cut signal FUCUT 1 . 
         [0050]    Referring to  FIG. 5C , the transistor select signal generating circuit  202 C includes a signal dividing unit  301  and a signal generating unit  302 . The signal dividing unit  301  receives the 2-bit transistor select source signals TSEL 1  and TSEL 2  to output 4-bit transistor select source signals TSEL 3  to TSEL 6  in response to the fuse cut signals FUCUT 1  and FUCUT 2 . The signal generating unit  302  outputs signals S, M, L and XL for driving the voltage drop transistors P 1  to P 4  in response to the transistor select source signals TSEL 3  to TSEL 6 . 
         [0051]    The signal dividing unit  301  includes a second NOR gate NOR 2  receiving the first transistor select source signal TSEL 1  and the first fuse cut signal FUCUT 1 , a thirteenth inverter INV 13  inverting an output signal of the second NOR gate NOR 2  to output the fourth transistor select source signal TSEL 4 , a fourteenth inverter INV 14  inverting an output signal of the thirteenth inverter INV 13  to output the third transistor select source signal TSEL 3 , a third NOR gate NOR 3  receiving the second transistor select source signal TSEL 2  and the second fuse cut signal FUCUT 2 , a fifteenth inverter INV 15  inverting an output signal of the third NOR gate NOR 3  to output the sixth transistor select source signal TSEL 6 , and a sixteenth inverter INV 16  inverting an output signal of the fifteenth inverter INV 15  to output the fifth transistor select source signal TSEL 5 . 
         [0052]    In the signal generating unit  302 , a seventh NAND gate NAND 7  receives the fourth transistor select source signal TSEL 4  and the sixth transistor select source signal TSEL 6 . A buffer INV 17  and INV 18  buffers an output signal of the seventh NAND gate NAND 7  to output the first transistor select signal S. 
         [0053]    An eighth NAND gate NAND 8  receives the third transistor select source signal TSEL 3  and the sixth transistor select source signal TSEL 6 . A buffer INV 19  and INV 20  buffers an output signal of the eighth NAND gate NAND 8  to output the second transistor select signal M. 
         [0054]    A ninth NAND gate NAND 9  receives the fourth transistor select source signal TSEL 4  and the fifth transistor select source signal TSEL 5 . A buffer INV 21  and INV 22  buffers an output signal of the ninth NAND gate NAND 9  to output the third transistor select signal L. 
         [0055]    A tenth NAND gate NAND 10  receives the third transistor select source signal TSEL 3  and the fifth transistor select source signal TSEL 5 . A buffer INV 23  and INV 24  buffers an output signal of the tenth NAND gate NAND 10  to output the fourth transistor select signal XL. 
         [0056]      FIG. 6  is a circuit diagram of the test mode signal generating unit  204  shown in  FIG. 4 . 
         [0057]    The test mode signal generating unit  204  includes an eleventh NAND gate NAND 11  receiving three different address signals ADD 7  to ADD 9 , a twelfth NAND gate NAND 12  receiving an output signal of the eleventh NAND gate NAND 11  as a first input signal, a thirteenth NAND gate NAND 13  receiving an output signal of the twelfth NAND gate NAND 12  as a first input signal and a reset signal RST 3  as a second signal and outputting a NANDed signal as a second input signal of the twelfth NAND gate NAND 12 , and a buffer INV 25  and INV 26  buffering the output signal of the twelfth NAND gate NAND 12 . 
         [0058]    In a test mode, the bit line precharge voltage generator  200  turns off the NMOS transistor N 1  for transferring the bit line precharge voltage VBLP and selectively turns on the voltage drop transistors P 1  to P 4  having the different gate lengths during a normal operation mode. This operation can obtain the same effect as varying the resistance, thereby solving the leakage current problem. The turning-on of the voltage drop transistors P 1  to P 4  is selected through the fuse cut when the amount of the leakage current is minimized in the power down mode through the test mode. 
         [0059]    When the semiconductor memory device enters the power down mode, the NMOS transistor N 1  transfers the bit line precharge voltage VBLP to the supply source through the voltage drop transistors P 1  to P 4  selected when the NMOS transistor N 1  is turned off. 
         [0060]    In the normal operation mode, the bit line precharge voltage VBLP is transferred to the supply source through the NMOS transistor N 1 , and the selected voltage drop transistors P 1  to P 4  are also turned on. That is, the voltage drop transistors P 1  to P 4  selected in the normal operation mode and the power down mode are turned on. The NMOS transistor N 1  is a thick transistor and is driven at a relatively higher voltage (VPP) than the bit line precharge voltage VBLP. 
         [0061]      FIG. 7  is a graph illustrating a leakage current reduced by the bit line precharge voltage generator  200  of  FIG. 4 . 
         [0062]    A current-time graph shows an amount of a leakage current and a voltage-time graph shows a voltage level of the bit line precharge voltage. 
         [0063]    As can be seen from the current-time graph, the amount of the leakage current is reduced in the power down mode by the bit line precharge voltage generator of the present invention, thereby causing no bridges. 
         [0064]    As can be seen from the voltage-time graph, the conventional bleeder using a fixed resistance for solving the leakage current problem cannot increase up to the voltage level of the desired bit line precharge voltage VBLP even when the power down mode is exited. However, the bit line precharge voltage generator of the present invention obtains the desired bit line precharge voltage VBLP because it can transfer the bit line precharge voltage VBLP due to the NMOS transistor N 1 . 
         [0065]    As described above, the bit line precharge voltage generator drives the bit line precharge voltage at a drivability adjusted in the power down mode through the test mode, thereby reducing the leakage current caused by the bridge between the word line and the bit line. 
         [0066]    In addition, the malfunction of the semiconductor memory device can be prevented by obtaining the stable and reliable bit line precharge voltage for precharging the bit line and the power line of the bit line sense amplifier. 
         [0067]    Consequently, the semiconductor memory device can operate reliably and stably at low power. 
         [0068]    The present application contains subject matter related to Korean patent application No. 2006-59261, filed in the Korean Intellectual Property Office on Jun. 29, 2006, the entire contents of which are incorporated herein by reference. 
         [0069]    While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.