Abstract:
Band limited standard video signals are sampled with line coupled sampling clock pulses. The sampling clock pulses are shifted from field to field by one-half a sampling interval. The sampling clock pulse rate is twice the frequency at the center of the Nyquist edge of the transmission channel. The received signal is sampled in synchronism, line coupled and offset from field to field. A video memory records the sampled values and furnishes them to the monitor at twice the sampling frequency and without flicker as a full frame. The video playback takes place at twice the line frequency or alternatively with the same line frequency and synchronous spot wobbling.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a method for a compatible increase in resolution in television systems for black and white and color picture transmission wherein the luminance signal of a signal source is scanned line by line with line interlacing and is limited by a transmitter lowpass filter. 
     The state of the art is defined by the presently used black and white systems as well as the PAL, SECAM and NTSC color television systems and is illustrated in the book entitled &#34;Fernsehtechnik&#34; [Television] by R. Theile published by Springer Verlag, Berlin-Heidelberg-New York, 1973. 
     These present-day television systems are not ideal with respect to fidelity in the reproduction of the transmitted images. The major drawbacks are, in particular, insufficient detail resolution, annoying line flicker, line travel and 25 Hz flicker along the horizontal outlines. 
     New system uses, such as video text, screen text, still picture transmission, home terminals, etc. cause these drawbacks to become even more evident. For example, television grid displays are almost unsuitable for computer graphics or for information retrieval. Considering the long-term outlook, however, a uniform display technique for all these cited uses seems to be desirable. 
     Morever, the trend to ever larger and brighter screens puts greater demands on detail resolution and freedom from flicker. The demand for increased detail resolution is especially applicable to large screen reproductions, e.g. with the aid of projection devices or on large planar displays. 
     SUMMARY OF THE INVENTION 
     It is the object of the invention to provide, by means of circuit arrangements in the television transmitter and in the television receiver, suitable prior and subsequent signal processing means which, with the existing transmission channel capacities and retained compatibility for existing receiver designs, improve the image quality on suitably equipped receivers. The solutions for this problem are described below. 
     The object is here to realize high detail resolution and avoid all flicker effects. For a monitor display on a conventional size screen this results in better legibility and less tiring reading, and for large-screen displays it becomes possible to use a larger field of observation at a greater distance which results in a substantial subjective increase in quality. 
     Advantageous embodiments of the solutions according to the invention can be found in the dependent claims. 
    
    
     The invention will now be explained in detail with the aid of the drawing figures. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block circuit diagram of an arrangement according to the invention; 
     FIG. 2 is a pictorial view showing the spatial arrangement of scanned image points in a system according to the invention; 
     FIG. 3 is a diagram illustrating the transfer function of a transmission channel; 
     FIG. 4 is a block circuit diagram of a first embodiment of a video memory which can be employed in a system according to the invention; 
     FIG. 5 is a view similar to that of FIG. 4 of a second embodiment of the video memory; 
     FIG. 6 is a pictorial view showing the spatial arrangement of the image points on a monitor when the playback beam is wobbled according to the invention; 
     FIG. 7 is a circuit diagram of a scanner which can be used in a system according to the invention; 
     FIG. 8 is a block circuit diagram of a video memory clock pulse center which can be used in a system according to the invention; 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows that at the transmitting end the luminance signal from a signal source 1 is fed to a transmitter lowpass filter 2 whose output signal is fed to the input 12 of a transmitter scanner sampling switch 3 and that a clock pulse generator 4 furnishes, on the one hand, synchronizing signals to the input 11 of the signal source 1 and, on the other hand, a line coupled sampling clock pulse to the input 13 of the transmitter sampling switch 3. 
     During the first field of a picture frame, the transmitter sampling switch 3 generates samples, and during the second field, it generates samples which are offset by one-half a sampling interval, or period, as shown in FIG. 2. 
     These samples are fed to a transmission channel 5 which exhibits a Nyquist edge centered at the frequency f O  as shown in FIG. 3. The horizontal, or line, coupled sampling clock pulse frequency f T  is twice as high as the frequency f O  (f T  =2f O , Nyquist rate). At the receiving end, the synchronizing pulses in the received signal synchronize a clock pulse center 8, which generates sampling clock pulses in offset position corresponding to the clock pulse generator 4 and controls, via the input 15 of a sampling switch 6, the sampling of the received signals appearing at the input 14 of the switch 6 and furthermore via the input 16 the storing of the scanned values at the input 17 of a video memory 7. The clock pulse center 8 controls, via the input 18 of the video memory 7, the synchronization of the image storage and the twice as rapid image readout. The output signals from the video memory 7 are fed to a lowpass filter 9 whose lower limit frequency is twice as high as that of the lowpass filter 2 and the scanned values filtered by the lowpass filter 9 are fed to a monitor 10. 
     The source 1 may be, for example, a television camera, including a clock pulse generator which, in order to perform the method according to the invention, requires an additional output so as to furnish a line coupled sampling clock pulse in the offset position as shown in FIG. 2. The lowpass filter 2 is likewise realized by the conventional circuitry of such a camera. The effect of the required lowpass filter 2 can already be produced by the camera. 
     FIG. 7 shows a sampling switch as it is used to practice the method according to the invention as the transmitter switch 3 as well as the receiver switch 6. 
     With a suitable analog/digital converter 30, shown in FIGS. 4 and 5, having a sufficiently small sampling time (about 1 nsec), the receiver switch 6 could be omitted. 
     A favorable embodiment of the flicker free image reproduction with increased resolution employs the video memory of FIG. 4. The video memory according to FIG. 4 receives, at the input 17 of the analog/digital converter 30, the scanned, or sampled, values of the received signal. From the sampling clock pulse at frequency f T  at input 16 and from the image synchronizing signal at input 18 the video memory clock pulse center 33 generates at its output 64 the readout clock pulse whose frequency is twice that of the sampling clock pulse. This clock pulse is coupled with the field clock pulse at the output 65 and with the line frequency pulse at the output 66 and with the synchronous mixture for the twice as fast, or double frequency, readout at the output 67. 
     The sampling clock pulse at the input 16 of the video memory clock pulse center 33 is fed to the gating input 50 of the analog/digital converter 30. The digital output signals of the analog/digital converter 30 are fed, via the input 51 to a demultiplexer 31 whose second input 52 receives the field clock pulse from the video memory clock pulse center. 
     The signals associated with the first field are fed, via the input 53 to a first field memory 34 and the signals associated with the second field are fed to a second field memory 35. 
     A read-in control 36 which receives at its input the sampling clock pulse of the input signal at the input 16 of the video memory clock pulse center, generates the memory addresses and control instructions associated with the respective fields. 
     These memory addresses are fed to the input 54 or 57, respectively, of the field memory 34 or 35, respectively. A readout control 37, which receives at its input the readout clock pulse at twice the frequency of the sampling clock pulse from the output 64 of the video memory clock pulse center 33, generates the memory addresses and control instructions associated with the respective lines to be read out. 
     These memory addresses are fed to the input 55 or 58, respectively of the field memory 34 or 35, respectively. At the outputs of the two field memories there appear, in succession, during the line duration of a stored line, one line of the first field and one line of the second field. 
     These output signals from the two field memories are fed to the respective inputs 59 and 60 of a multiplexer 38. At the input 61 of the multiplexer 38 there appears the line frequency pulses from the output 66 of the video memory clock pulse center 33. The output signal of the multiplexer 38 is fed to a digital/analog converter 39 whose output signal is fed to one input 62 of an adder stage 40 whose other input 63 receives the synchronous mixture for the double frequency readout from the output 67 of the video memory clock pulse center 33 and furnishes at its output the corrected video signal to the lowpass filter 9 of FIG. 1 at tiwce the line frequency and at the image, or field, frequency so as to produce an entire frame. 
     In cases where a change of the line frequency is impossible or not desirable, the configuration according to FIG. 5 represents a favorable embodiment for a flicker free increase in resolution. The video memory according to FIG. 5 receives the sampled values of the received signals at the input 17 of the analog/digital converter 30. The video memory clock pulse center 33 generates from the sampling clock pulse f T  at the input 16 and from the image synchronizing signal at the input 18 the field clock pulse at the output 65 and the synchronous mixture at the output 71; the sampling clock pulse at the input 16 of the video memory clock pulse center 33 is fed to the input 50 of the analog/digital converter 30. 
     The digital output signals of the analog/digital converter 30 are fed, via the input 51, to a demultiplexer 31 whose second input 52 receives the field clock pulse from the video memory clock pulse center. 
     The signals associated with the first field are fed, via the input 53 to the first field memory 34 and the signals associated with the second field are fed, via the input 56 to the second field memory 35. 
     The write-in control 36, which receives at its input the sampling clock pulse of the input signal at the input 16 of the video memory clock pulse center, generates the memory addresses and control instructions associated with the respective fields. 
     These memory addresses are fed to the input 54 or 57, respectively, of the field memory 34 or 35, respectively. 
     The read-out control 37, whose input receives the sampling clock pulse, generates the memory addresses and control instructions associated with the respective lines to be read out. 
     These memory addresses are fed to the input 55 or 58, respectively, of the field memory 34 or 35, respectively. At the respective outputs of the two field memories there appears a line of the first field and a line of the second field, respectively. These output signals of the two field memories are fed to the respective inputs 59 and 60 of the multiplexer 38. The sampling clock pulse f T  appears at the input 61 of the multiplexer 38 and alternatingly switches to its output a point of a line from the first field and the adjacent point of the next locally adjacent line of the other field. If the line frequency is the same, this causes all image points of both fields to appear at the output of the multiplexer during the duration of one field. 
     The output signal of the multiplexer 38 is fed to a digital/analog converter 39 whose analog output signal is fed to the input 62 of an adder stage 40 which receives at its other input 63 the synchronous mixture at the output 71 of the video memory clock pulse center 33 and furnishes at its output the corrected video signal to the lowpass filter 9. The lowpass limited signal is fed to the input 68 of the monitor 41 which can be wobbled to trace the picture elements of two lines in alternation and the sampling clock pulse f T  is fed to the input 69 of the monitor 41. The sampling clock pulse f T  synchronizes the wobbling circuitry of the monitor and the spot of the playback beam in the monitor 41 is additionally wobbled vertically as shown in FIG. 6. 
     In those cases where an increase in the line frequency in the monitor is impossible or not desirable, the method according to the invention therefore proposes to wobble the electron beam of the video tube by means of a device, e.g., a magnetic field, in such a way that during one line sweep the image points of one line appear at the appropriate locations and the image points of the adjacent lines are locally vertically offset therefrom. 
     The above circuit arrangement for increasing resolution can also be used with advantage for video recording and playback and for video telephone systems. 
     The video memory clock pulse center is constructed, for example, as shown in FIG. 8. 
     A conventional frequency doubling circuit is disposed between the input 16 and the output 64. The input 18 is connected to a pulse separating stage whose horizontal output H leads to a phase locked loop circuit (PLL) having an output frequency of 2 MHz whose output actuates a video clock pulse center marketed under the name &#34;Video-Taktzentrale&#34; S 178 by Siemens AG. This clock pulse center is additionally actuated by the vertical output V of the pulse separating stage. 
     From the actuating signals, the video clock pulse center generates the synchronous mixture at the output 67 at double the line scanning frequency and at the same video frequency and makes available to the PLL circuit, via an additional 2:1 frequency divider, the horizontal comparison pulses which the PLL circuit synchronizes with the horizontal pulses from the pulse separating stage. The horizontal pulses from the additional 2:1 frequency divider are fed to the output 66. The input 18 to which is fed the vertical synchronizing signal is connected directly with the output 71. The vertical signal from the pulse separating stage is fed to the output 65. The terminals are identified in the same manner as in FIGS. 1, 4 and 5.