Abstract:
The present invention relates to a printed circuit board, and in particular, to a printed circuit board for a package of electronic components and manufacturing method thereof. One aspect of present invention provides a manufacturing method of a printed circuit board for an electronic component package, which includes: forming a circuit pattern including bonding pads on one side of a first insulation layer, laminating a second insulation layer onto one side of the first insulation layer, and exposing the bonding pads by removing a part of the first insulation layer and the second insulation layer corresponding to the location in which the bonding pads is formed.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of Korean Patent Application No. 2006-0054459 filed with the Korean Intellectual Property Office on Jun. 16, 2006, the disclosure of which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a printed circuit board, and in particular, to a printed circuit board for a package of electronic components and manufacturing method thereof. 
         [0004]    2. Description of the Related Art 
         [0005]    With developments in the electronics industry, the use of the memory packages mounted with memory chips in electronic devices is rapidly increasing. Moreover, companies manufacturing and supplying memory packages are also increasing, with companies expanding their business to fields concerning memory packages. In this competitive market situation, various plans have been suggested for decreasing costs. 
         [0006]    Presently, in most cases, a memory package is implemented by making one package using wire bonding, as shown in  FIGS. 1   a ,  1   b , and this package is called a BOC (Board-on-chip). The BOC has been specially developed for the characteristics of the memory chip, and has the pads of the memory chip positioned at the center of a substrate, with the structure of pads positioned for connecting directly with the substrate. The BOC is a structure in which a slot is formed where the pads are positioned in order to attach the memory chip under the substrate, where wire bonding can be performed through the slot. Thus, the BOC requires only one metal layer, which gives it dominance in price competitiveness of the memory package. 
         [0007]    However, with the very rapid developments in the technology of manufacturing semiconductors, the capacity of the memory package is also increasing. This creates a risk of signal losses at the wires in cases of using the conventional BOC. 
       SUMMARY 
       [0008]    An aspect of the present invention is to provide a printed circuit board for mounting an electronic component package and manufacture thereof that allow the mounting of a high-capacity memory chip. 
         [0009]    Additional aspects and advantages of the present invention will become apparent and more readily appreciated from the following description, including the appended drawings and claims, or may be learned by practice of the invention. 
         [0010]    One aspect of the present invention provides a manufacturing method of a printed circuit board for an electronic component package, which includes: forming a circuit pattern including bonding pads on one side of a first insulation layer, laminating a second insulation layer onto one side of the first insulation layer, and exposing the bonding pads by removing a part of the first insulation layer and the second insulation layer corresponding to the location in which the bonding pads are formed. 
         [0011]    The circuit pattern may further include solder ball pads, and the exposing of the bonding pads may further comprise exposing the solder ball pads by removing the part of the first insulation layer or the part of the second insulation layer which correspond to the location of the solder ball pads. 
         [0012]    The forming of a circuit pattern may further include laminating a seed layer onto a carrier board, forming the circuit pattern on the seed layer, laminating the first insulation layer onto the carrier board such that the circuit pattern is embedded in the first insulation layer, and removing the carrier board and the seed layer. 
         [0013]    The first insulation layer and the second insulation layer may include a photoresist material, and the exposing of the bonding pads comprises removing the part of the first insulation layer and the part of the second insulation layer by exposure and development. 
         [0014]    Another aspect of the present invention provides a printed circuit board for an electronic component package, which includes: a first insulation layer, a circuit pattern laminated on one side of the first insulation layer and comprising the bonding pads and the solder ball pads, a second insulation layer laminated on the one side of the first insulation layer, a cavity that is formed by removing a part of the first insulation layer and a part of the second insulation layer in correspondence to the location of the bonding pads and the solder ball pads for exposing the bonding pads and the solder ball pads. 
         [0015]    The first insulation layer and the second insulation layer may be photosensitive. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which: 
           [0017]      FIG. 1   a  is a perspective view of an electronic component package according to prior art. 
           [0018]      FIG. 1   b  is a cross-sectional view of an electronic component package according to prior art. 
           [0019]      FIG. 2  is a flowchart of a manufacturing method of a printed circuit board for an-electronic component package according to a first disclosed embodiment of the invention. 
           [0020]      FIG. 3  is a fabrication diagram of a memory package according to the first disclosed embodiment of the invention. 
           [0021]      FIG. 4  is a cross-sectional view of a printed circuit board for an electronic components package according to a second disclosed embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Embodiments of the printed circuit board for the electronic component package and manufacturing thereof according to the invention will be described below in more detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, those components are rendered the same reference number that are the same or are in correspondence regardless of the figure number, and redundant explanations are omitted. 
         [0023]      FIG. 2  is a flowchart of the manufacturing method of a printed circuit board for an electronic component package according to a first disclosed embodiment of the invention, and  FIG. 3  is a fabrication diagram of the memory package according to the first disclosed embodiment of the invention. Referring to  FIG. 3 , a carrier board  31 , a seed layer  32 , a dry film  33 , a first insulation layer  34   a , a second insulation layer  34   b , solder ball pads  36   a , a circuit pattern  36 , bonding pads  36   c , and a plating layer  37  are illustrated. 
         [0024]    S 21  of  FIG. 2  is the operation for forming the circuit pattern  36 , which includes the bonding pads  36   c  and the solder ball pads  36   a , on the first insulation layer  34   a . Drawings (a) to (f) of  FIG. 3  correspond to S 21 . 
         [0025]    Drawing (a) of  FIG. 3  describes the operation for laminating the seed layer  32  onto the carrier board  31 . The seed layer  32  may be formed by electroless plating, but any material adhered with a thin copper foil may be used. Any material that allows ready detachment may be used as the carrier board  31 . 
         [0026]    Drawing (b) of  FIG. 3  describes the process for laminating the dry film  33  onto the seed layer  32 , and removing parts of the dry film  33 , in which the circuit pattern  36  including the solder ball pads  36   a  and bonding pads  36   c  will be formed, through exposure and development processes. After electro plating and removing the dry film  33 , the circuit pattern  36  including the bonding pads  36   c  and solder ball pads  36   a  is formed on the seed layer  32  as shown in  FIG. 3 . 
         [0027]    Drawing (d) of  FIG. 3  is the process for laminating the carrier board  31  on the first insulation layer  34   a . At this time, the circuit pattern  36  is impregnated to the first insulation layer  34   a  as shown in  FIG. 3 . 
         [0028]    Afterwards, the carrier board  31  and the seed layer  32  are removed as in (e) and (f) of  FIG. 3 , at which the buried pattern substrate  30  is complete. The buried pattern substrate  30  has an advantage that a semiconductor chip can be mounted easily, because the surface of the buried pattern substrate  30  is flat. 
         [0029]    Various methods, besides the method shown in (a) to (f) of  FIG. 3 , may be applied for forming the buried pattern substrate in S 21  of  FIG. 2 . For example, a subtractive method of forming a circuit pattern after removing the copper foil of a copper-clad laminate, or a semi-additive method of forming a circuit pattern after laminating a seed layer on the insulation layer may be used. 
         [0030]    S 22  of  FIG. 2  is the operation for laminating the second insulation layer  34   b  onto the one side of the first insulation layer  34   a . Drawings (g) and (h) of  FIG. 3  describe process that are in correspondence to S 22 . The second insulation layer  34   b  is laminated onto the one side of the first insulation layer  34   a  on which the circuit pattern  36  has been impregnated as in (g) of  FIG. 3 . Consequently, the circuit pattern  36  including the bonding pads  36   c  and solder ball pads  36   a  is positioned between the first insulation layer  34   a  and the second insulation layer  34   b , as in (i) of  FIG. 3 . 
         [0031]    S 23  of  FIG. 2  is the operation for exposing the bonding pads  36  and solder ball pads  36   a  after removing a part of first insulation layer  34   a  and a part of second insulation layer  34   b . The first insulation layer  34   a  and second insulation layer  34   b  may be made of photosensitive material, whereby the first insulation layer  34   a  and second insulation layer  34   b  can be removed after the exposure and development processes. As shown in (j) of  FIG. 3 , the solder ball pads  36   a  are exposed as a result of removing the first insulation layer  34   a , and the bonding pads  36  are exposed after the second insulation layer  34   b  is removed. The bonding pads  36   a  are the parts where the semiconductor chip will be mounted, and the solder ball pads  36   a  are the parts where the solder balls will be adhered. 
         [0032]    A surface treatment process may additionally be performed on the exposed solder ball pads  36   a  and the exposed bonding pads  36 . The plating layer  37  is formed after the surface process is completed. The plating layer  37  is formed by gold plating after nickel plating. 
         [0033]      FIG. 4  is a cross-sectional view of the printed circuit board for an electronic component package according to a second disclosed embodiment. Referring to  FIG. 4 , a printed circuit board  40  for a package, a first insulation layer  44   a , a second insulation layer  44   b , solder ball pads  46   a , a circuit pattern  46 , bonding pads  46   c , and a cavity  47  are illustrated. 
         [0034]    As shown in  FIG. 4 , the printed circuit board  40  for a package according to this embodiment has the circuit pattern  46   b  including the solder ball pads  36   a  and the bonding pads  46   c  positioned on a single layer interposed between the first insulation layer  44   a  and the second insulation layer  44   b.    
         [0035]    The first insulation layer  44   a  and second insulation layer  44   b  may be made of photosensitive material, and parts of the first insulation layer  44   a  and the second insulation layer  44   b  are removed in order to expose the solder ball pads  46   a  and bonding pads  46   c . The removal may be effected through exposure and development processes performed on the first photosensitive insulation layer  44   a  and second photosensitive insulation layer  44   b . Meanwhile, the solder ball pads  46   a  and bonding pads  46   c  are exposed due to the forming of the cavity  47 . Surface-treatment may be applied to the exposed solder ball pads  46   a . The surface-treatment may be in the form of gold-plating over nickel-plating. 
         [0036]    According to certain embodiments of the invention as described in the above, the length of the signal wire becomes shorter than in a conventional printed circuit board for an electronic component package and fast signal processing is possible. Also, it is possible to form high density circuits due to the use of the semi additive method. Moreover, because the circuit pattern layer is implemented as a single layer, superb heat releasing properties are obtained. 
         [0037]    While the above description has pointed out novel features of the invention as applied to various embodiments, the skilled person will understand that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made without departing from the scope of the invention. Therefore, the scope of the invention is defined by the appended claims rather than by the foregoing description. All variations coming within the meaning and range of equivalency of the claims are embraced within their scope.