Abstract:
The present invention relates to an oscillating apparatus. The oscillating apparatus includes a biasing circuit, a multi-vibrator, a detecting circuit, and a selecting circuit. The biasing circuit is for generating a bias signal, wherein the biasing circuit includes a connecting port for using an impedance device to control an oscillating frequency or for directly connecting to external clock source as a reference clock. The multi-vibrator coupled to the biasing circuit for generating the oscillating frequency according to the quantity of the biasing signal. The detecting circuit coupled to the connecting port for generating a detecting signal whether the connecting port is coupled to the impedance device or the external clock source. The selecting circuit includes an AND gate coupled to the multi-vibrator and the selection signal and an OR gate coupled to the AND gate and the connecting port.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention is related to an oscillating apparatus, and more particularly, to an adjustable oscillating frequency and oscillating apparatus with high power supply rejection. 
         [0003]    2. Description of the Prior Art 
         [0004]    In digital electronic devices, a clock generator is used for generating a clock signal, in which the clock signal is utilized as a reference clock for the digital circuit application. Normally, an external low-frequency clock source (e.g. a crystal oscillator) is utilized to generate a higher frequency clock inside the chip by a synthesizer. A self-resonated circuit within the chip generates reference clocks for some digital electronic devices. The former requires an off-chip oscillating device, and a synthesizer, which is implemented by a phase locked loop circuit; however the latter only requires a simple self-resonated structure, thus the latter is widely used in the driver of the small sized thin film transistor-liquid crystal display (TFT-LCD). Therefore, the chip area and power consumption of the latter are smaller than that of the former. 
         [0005]    Ideally, when the self-resonated circuit oscillates, the resistor-capacitor (RC) value and the amplifier configuration within the self-resonated circuit will decide the range of the oscillating frequencies. However the variation of the external environment, such as supply voltage, manufacturing process, and temperature will change the oscillation condition of the self-resonated circuit and consequently cause a shift of the oscillating frequency from ideal conditions. 
         [0006]    The oscillating period (T) of an oscillator can be approximated as 
         [0000]        T =(2 CV   SW )/ I +( X   non-linear term )=2 RC +( X   non-linear term ), 
         [0007]    wherein C is a charging/discharging capacitor, V SW  is signal amplitude in the capacitor, and I is the average current. X non-linear term  is a non-linear factor from voltage swing and current, and the active device also induces some non-linear effects. 
         [0008]    Accordingly, the external environment is changed, the value of V SW , and I are also changed to cause the departure of the frequency of the oscillating signal from an ideal condition. Thus, the frequency derivation would be reduced by the external fixed resistance that generated the biasing current of the oscillator. The linear relationship between resistance and V SW /I in the oscillator portion would reflect the variation of oscillated frequency. Furthermore, the departure of oscillating frequency is apparently affected by the non-linear term that includes oscillator configurations and circuit limitations. 
       SUMMARY OF THE INVENTION 
       [0009]    It is therefore one of the objectives of the claimed invention to provide an oscillating apparatus with adjustable oscillating frequency and high power supply rejection ratio mechanisms to solve the above-mentioned problems. 
         [0010]    According to the present invention, an oscillating apparatus is disclosed. The oscillating apparatus comprises: a biasing circuit and a multi-vibrator. The biasing circuit is employed for dynamically adjusting a bias quantity of the oscillating apparatus; the multi-vibrator, coupled to the biasing circuit, is to generate an oscillating signal according to the biasing signal. 
         [0011]    According to the present invention, an oscillating apparatus is disclosed. The oscillating apparatus comprises: a biasing circuit, an oscillator, an impedance device, a detecting circuit, and a selecting circuit. In which the biasing circuit generates a biasing signal; the oscillator coupled to the biasing circuit, for generating an oscillating signal; and the impedance device coupled to the biasing circuit for controlling a frequency of the oscillating signal; wherein the biasing circuit and the oscillator are positioned on a chip. The impedance device is off-chip or on-chip. Thus, the impedance device is for controlling a frequency of an oscillating signal or for coupling a clock source to receive a reference clock. The detecting circuit, coupled to the connecting port, is for detecting whether the connecting port is coupled to the impedance component or the clock source. The selecting circuit, comprising an AND gate coupled to the oscillator output and the selection signal, is for blocking the internal oscillating signal while there exists an external clock source. An OR gate, coupled to the AND gate output and the connecting port, is for bypassing the signal from an internal oscillator or external clocking reference. 
         [0012]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  illustrates an oscillating apparatus according to an embodiment of the present invention. 
           [0014]      FIG. 2  illustrates an embodiment of the constant Gm biasing circuit and the multi-vibrator of  FIG. 1 . 
           [0015]      FIG. 3  illustrates an embodiment of the detecting circuit of  FIG. 1 . 
           [0016]      FIG. 4  illustrates a waveform of the voltage of connector within the detecting circuit of  FIG. 3 . 
           [0017]      FIG. 5  illustrates a waveform of the selective signal within the detecting circuit of  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, consumer electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
         [0019]      FIG. 1  illustrates an oscillating apparatus  100  according to an embodiment of the present invention. The oscillating apparatus  100  comprises a constant Gm biasing circuit  102  (consists a connector  1021 ), a multi-vibrator  104 , a detecting circuit  106 , a selective circuit  108 , a startup circuit  100 , and a wave-shaping circuit  112 . The multi-vibrator  104  is coupled to the constant Gm biasing circuit  102 , the detecting circuit  106  is coupled to the connector  1021 , the selective circuit  108  comprises an AND gate G 1  coupled to the multi-vibrator  104  and a selective signal, and an OR gate G 2  coupled to the AND gate G 1  and the connector  1021 . In the embodiment, the constant Gm biasing circuit  102  is used for generating a first bias signal Bias 1  and a second bias signal Bias 2 , wherein the connector  1021  is used for coupling an off-chip resistor R EXT  to control oscillating frequency of a oscillating signal OSC OUT  or coupling a clock source to receive a reference clock F EXT ; the multi-vibrator  104  is used for generating the required oscillating signal OSC OUT  according to the first bias signal Bias 1  and the second bias signal Bias 2 ; the detecting circuit  106  is used for detecting whether the connector  1021  is coupled to the resistor R EXT  or the reference clock F EXT  for generating a selective signal SEL; the selective circuit  108  is used for selectively outputting the oscillating signal OSC OUT  or the reference clock F EXT ; the startup circuit  110  guarantees that the constant Gm biasing circuit  102  is workable at normal operation mode, and the wave-shaping circuit  112  is used for pulling the level of the output signal of the multi-vibrator  104  into the digital voltage level. 
         [0020]      FIG. 2  illustrates an embodiment of the constant Gm biasing circuit  102  and the multi-vibrator  104  of  FIG. 1 . In the embodiment of the constant Gm biasing circuit  102 , comprises a resistor R; a cascoded structure, comprising a transistor M 1  cascoded with a transistor M 2 , wherein gate terminals of the transistors M 1 , M 2  are coupled to the two terminals of the resistor R, respectively; a second cascoded structure, comprising a transistor M 3  cascoded with a transistor M 4 , thus M 1 ˜M 4  transistors are formed as a high-impedance PMOS current mirror; an NMOS current mirror  1022 , comprising transistors M NB1 , M NB2 , wherein a current path of the current mirror  1022  are coupled to the connector  1021 ; and a capacitor C 1 , with two terminals is coupled between the transistor M 1  and transistor M NB2 . In the embodiment, the multi-vibrator  104  is well-known to those having average skill in this art, and is specifically a voltage-controlled oscillator with a cross-coupled capacitor C MOS , in which the voltage-controlled oscillator is controlled by the bias signal Bias 1  and Bias 2 , therefore, further details are omitted for the sake of brevity. 
         [0021]    Accordingly, when the oscillating apparatus  100  utilizes the off chip resistor R EXT  to generate the oscillating signal OSC OUT , the oscillating frequency f osc  of the multi-vibrator  104  approaches: 
         [0000]        f   osc =½Π( R   EXT   C   MOS ) 
         [0022]    wherein the channel width ratio of the transistors M NB1 , M NB2  within the current mirror  1022  is 1:N, and because V gs(NB2) =V gs(NB1) +I*R EXT  in the constant Gm biasing circuit  102 , thus the biasing current I that pass through the resistor R is: 
         [0000]        I =(2/(( U   n   C   ox )( W/L ) NB1 ))*(1 /R   EXT )*((1−(1 /N   1/2 )) 2 ). 
         [0023]    According to the equation of I, the biasing current I of the constant Gm biasing circuit  102  can be adjusted according to resistance of the resistor R. Accordingly, the oscillating apparatus  100  of the present invention has a better biasing current-oscillating signal transfer characteristic that reduces/improves the power supply rejection (PSR). In other words, the utilization of cascoded PMOS transistor improves the operation of biasing current to the power noise. 
         [0024]    Because the connector  1021  is selectively coupled to the off-chip resistor R EXT  or reference clock F EXT , thus a large parasitic capacitor will exist at the connector  1021 , in which the parasitic capacitor and the off-chip resistor R EXT  form a zero. The zero will cause the constant Gm biasing circuit  102  be unstable. In order to improve the unstable condition of the constant Gm biasing circuit  102 , a capacitor should be connected to the common gate terminal of the transistors M NB1 , M NB2 , and the capacitance of the capacitor should be 1/(N)̂(½) of the parasitic capacitance of the connector  1021  to form a capacitance compensation circuit at the constant Gm biasing circuit  102 . Accordingly, the embodiment utilizes the concept of Miller compensation to eliminate the value of the compensated capacitance effectively. As shown in  FIG. 2 , a compensated capacitor C 1  is coupled between the drain terminal of the first transistor M 1  and the common gate terminal of the transistors M NB1 , M NB2 . 
         [0025]      FIG. 3  illustrates an embodiment of the detecting circuit  106  of  FIG. 1 . In the embodiment, the detecting circuit  106  comprises a capacitor C 2 , charged transistors M 5 , M 6 , and discharged transistor M 7 . In which the gate terminal of the transistor M 7  is coupled to the connector  1021 , the drain terminal is coupled to the capacitor C 2  and transistors M 5 , M 6  to generate a selective signal SEL.  FIG. 4  illustrates a waveform of detecting signal transferred from the voltage V osc1  input format.  FIG. 5  illustrates an output waveform of the selective signal SEL within the detecting circuit  106  of  FIG. 3 . When the connector  1021  is coupled to the off-chip resistor R EXT , the output of detecting circuit  106  will cause the voltage V osc1  of the connector  1021  to be lower than the threshold voltage (Vth) of the transistor M 7 , as shown in waveform  501  of  FIG. 4 . Accordingly, the transistor M 7  is off, and the conducting of the transistors M 5 , M 6  will charge the capacitor C 2  to a high voltage level, which causes the selective SEL to also be at a high voltage level, as shown waveform  502  of  FIG. 5 . Alternatively, when the connector  1021  is coupled to the reference clock F EXT , as shown in waveform  503  of  FIG. 4 , because the reference clock F EXT  causes the transistor M 7  to be in an on state in a half-period and off in a other half-period, thus the transistors M 5 , M 6  will charge the capacitor C 2  to be higher than the voltage level of the selective signal SEL when the transistor M 7  is off; furthermore, the equivalent circuit of the embodiment will discharge the capacitor C 2  to lower the voltage level of the selective signal SEL when the transistor M 7  is on. The voltage level variation of the selective signal SEL is waveform  504  of  FIG. 5 . Accordingly, when the connector  1021  is coupled to the reference clock F EXT , the voltage level of the selective signal SEL is lower than the threshold voltage (VTH) and can be treated as low logic level “0”, and when the connector  1021  is coupled to the off-chip resistor R EXT , the voltage level of the selective signal SEL is higher and can be treated as high logic level “1”. Therefore, when the selective signal SEL is high logic level “1”, the output signal f out  of the selective circuit  108  be the oscillating signal OSC OUT  that via the wave-shaping circuit  112 , and when the selective signal SEL is low logic level “0”, the output signal f out  of the selective circuit  108  will be the reference clock F EXT  from off-chip. 
         [0026]    Accordingly, the embodiment according to the present invention is able to adjust the oscillating frequency of the oscillating signal OSC out  through the off-chip resistor R EXT , or provide the reference clock F EXT  from off-chip; furthermore, the selectivity connection of off-chip resistor R EXT  or reference clock F EXT  can be detected by the on-chip detecting circuit  106 . The detecting circuit  106  controls the selective circuit  108  to select one of the self-resonated oscillating signal OSC OUT  or off-chip reference clock F EXT  as the required output signal f out . 
         [0027]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.