Abstract:
A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a phase change memory, and in particular to a multilevel phase change memory. 
     2. Description of the Related Art 
     Phase change memories with competitive advantages of speed, low power consumption, high capacity, CMOS fabrication process compatibility and low costs, are suitable for use as high density stand-alone or embedded memories. Phase change memories are thus considered to have potentiality to replace currently commercial and competitive volatile memories such as SRAM and DRAM and non-volatile memories such as Flash. Bottlenecks in development of phase change memory mainly result from high writing current of the memory elements, since high writing current dictates increased area of connected driving transistors, leading to large memory cell area and low memory density. One method of increasing the phase change memory density is to decrease contact area between heater electrode and phase change recording layer so that the writing current can be reduced. However, this method is restricted by lithography and fabrication process technologies and thus harder to be implemented. Another method develops multilevel phase change memories with the same memory cells. However, this makes it difficult to control programming current and complicate process integration of various materials. 
     Multilevel phase change memories are proposed by Ovonyx in Elec_Memory_Research_Report in 1999, as shown in  FIG. 1 , by the relationship of memory state with writing current interval. Lateral axis represents writing current and vertical axis represents cell resistance resulting from the corresponding writing current. Different values of cell resistance are representative of different memory states. While an advantage of the multilevel operation can increase memory states, current programming intervals (1.42-1.51-1.51, 1.51-1.60, . . . , and 2.73-2.82 mA) corresponding to different memory states (or cell resistance) are extremely small and thus difficult to define and control, resulting in data storage errors. Additionally, resistance uniformity of respective states in different memory cells cannot be controlled precisely due to the possible deviation of fabrication process. 
     Japanese Matsushita Electronics Cooperation discloses another multilevel memory cell having various recording materials in U.S. Pat. No. 6,809,401.  FIG. 2  is a cross section of a multilevel memory cell  200  disclosed therein. As shown, the multilevel phase change memory cell  200  comprises a substrate  21 , a bottom electrode  22  and a top electrode  23 , first to Nth recording layers  24   1 - 24   N  of different materials, and first to (N-1)th interlayers  25   1 - 25   N-1  respectively disposed between two adjacent recording layers  24   1 - 24   N . Although the multilevel phase change memory cell  200  provides multilevel operation, different properties of the recording layers  24   1 - 24   N  of different materials result in high control difficulty and fabrication process complexity. 
     Accordingly, a multilevel phase change memory cell having larger current programming intervals, recording layers of the same materials and simple fabrication process is called for. 
     BRIEF SUMMARY OF THE INVENTION 
     The invention provides a phase change memory cell providing multilevel operation to increase memory density, is realized using the same phase change material. The phase change memory cell also has large current programming intervals. Moreover, the phase change memory can be fabricated utilizing currently developed CMOS fabrication process technologies. 
     The invention provides a phase change memory cell comprising a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be reversibly changed between crystalline and amorphous state which is determined by current pulse and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such as cross-sectional area and/or thickness so that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. 
     The invention provides another phase change memory cell comprising a first electrode and a second electrode, a plurality of recording layers disposed between the first and second electrodes, and a plurality of heating plugs each disposed between two of the recording layers or between one of the recording layers and one of the first and second electrodes. The phase of an active region of each of the recording layers can be reversibly changed between crystalline and amorphous state which is determined by current pulse and hence respectively has crystalline resistance or amorphous resistance. At least two of the contact areas between the recording layers and the heating plugs are different so that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. 
     The invention provides another phase change memory cell comprising a first electrode and a second electrode, a plurality of recording layers disposed between the first and second electrodes, a plurality of heating plugs each disposed between two of the recording layers or between one of the recording layers and one of the first and second electrodes, and at least one interlayer each connected between one of the recording layers and one of the heating plugs. The phase of an active region of each of the recording layers can be reversibly changed between crystalline and amorphous state which is determined by current pulse and hence respectively has crystalline resistance or amorphous resistance. The interlayer is disposed such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. 
     In the phase change memory cells of the invention, the recording layers can be of the same material. Accordingly, properties of only one material need to be considered, and the fabrication process is thus very simple and can be realized by currently developed CMOS fabrication process technologies. Additionally, current programming intervals are larger and programming control in different memory states can thus be performed readily. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows the relationship between memory state and programming current interval in a conventional phase change memory cell; 
         FIG. 2  is a cross section of another conventional multilevel memory cell; 
         FIG. 3  is a cross section of a phase change memory cell in accordance with an embodiment of the invention; 
         FIG. 4  shows the relationship between reset current and top-view area of a phase change recording layer; 
         FIG. 5  shows respective programming curves for the first and second recording layers of  FIG. 3 , illustrating the relationship between resistance values and writing current.; 
         FIG. 6  shows programming curves for the phase change memory cell of  FIG. 3 , illustrating the relationship between resistance values and writing current; 
         FIGS. 7A and 7B  are relational tables of written states to writing current in accordance with two embodiments of the invention; 
         FIG. 8  is a cross section of a phase change memory cell in accordance with another embodiment of the invention; 
         FIG. 9  shows relationship between reset current and thickness of a phase change recording layer; 
         FIG. 10  shows respective programming curves for first and second recording layers of  FIG. 8 , illustrating the relationship between resistance values and writing current; 
         FIG. 11  shows programming curves for phase change memory cell of  FIG. 8 , illustrating the relationship between resistance values and writing current; 
         FIG. 12  is a cross section of a phase change memory cell in accordance with another embodiment of the invention; 
         FIG. 13  shows relationship between reset current and contact area between heating plug and phase change recording layer; 
         FIG. 14  shows respective programming curves for first and second recording layers in  FIG. 12 , illustrating the relationship between resistance values and writing current; 
         FIG. 15  shows programming curves for the phase change memory cell of  FIG. 12 , illustrating the relationship between resistance values and writing current; 
         FIG. 16  is a cross section of a phase change memory cell in accordance with another embodiment of the invention; 
         FIG. 17  shows respective programming curves for first and second recording layers in  FIG. 16 , illustrating the relationship between resistance values and writing current; 
         FIG. 18  shows programming curves for the phase change memory cell of  FIG. 16 , illustrating the relationship between resistance values and writing current; 
         FIG. 19  is a cross section of a phase change memory cell in accordance with another embodiment of the invention; 
         FIG. 20  is a cross section of a phase change memory cell in accordance with another embodiment of the invention; 
         FIG. 21  is a cross section of a phase change memory cell in accordance with another embodiment of the invention; and 
         FIG. 22  is a cross section of a phase change memory cell in accordance with another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 3  is a cross section of a phase change memory cell  300  in accordance with an embodiment of the invention. As shown, the phase change memory cell  300  comprises a first electrode  31   1  and a second electrode  31   2  such as a single metallic or alloy layer of Al, Au, Ag, Cu, Pt, Ti and W or other metallic compounds. Additionally, between the first and second electrode  31   1  and  31   2 , from bottom to top, are disposed a first heating plug  33   1 , a first recording layer  32   1 , a first blocking layer  34   1 , a second heating plug  33   2 , a second recording layer  32   2  and a second blocking layer  34   2 . 
     The first and second blocking layers  34   1  and  34   2  are, for example, single metallic or alloy layers of Al, Au, Ag, Cu, Pt, Ti and W or other metallic compounds, respectively blocking diffusion of atoms between the first recording layer  32   1  and second heating plug  33   2 , and between the second recording layer  32   2  and second electrode  31   2 . However, it is noted that when the materials of the first recording layer  32   1  and second heating plug  33   2  are chosen such that atoms therein will not diffuse to each other, the disposing of the first blocking layer  34   1  is dispensable. Similarly, when the materials of the second recording layer  32   2  and second electrode  31   2  are chosen such that atoms therein will not diffuse to each other, the disposing of the second block layer  34   2  is dispensable. 
     The materials of the first and second recording layers  32   1  and  32   2  are selected such that their phases of respective active regions therein can be reversible between crystalline and amorphous states when they receive corresponding electronic energy to cause temperature rising via Joule heating, resulting in a resistance transition between a lower value of the crystalline state and a higher value of the amorphous state. The materials of the first and second recording layers  32   1  and  32   2  can be S-based, Se-based or Sb-based alloy, for example, binary alloy such as GaSb, In Sb, InSe, Sb 2 Te3 and GeTe, ternary alloy such as Ge 2 Sb 2 T 5 , InSbTe, GaSeTe, SnSbTe 4  and InSbGe, or quaternary alloy such as AgInSbTe, (Ge, Sn)SbTe, GeSb(SeTe) and Te 81 Ge 15 Sb 2 S 2 . 
     As shown in  FIG. 3 , the top-view areas of the first and second recording layers  32   1  and  32   2  in the memory cell  300  are different and respectively denoted as PA 1  and PA 2 , while the materials of the same can be the same or different. The different top-view areas of the first and second recording layers  32   1  and  32   2 , for example, can be realized as different top-view diameters or edge lengths of the same. The embodiment shown comprises PA 2  larger than PA 1 , but PA 2  can also be smaller than PA 1 . In addition, the materials of the first and second recording layers  32   1  and  32   2  are the same in the embodiment to simplify the description. 
       FIG. 4  shows relationship between reset current and the top-view areas of a phase change recording layer proposed by Samsung corporation in IEDM  2003 , illustrating programming mechanism of the phase change memory cell  300  of the invention, wherein the reset current is one to transfer the phase change material from crystalline state to amorphous state. As shown, phase change recording layers with different top-view areas have different magnitudes of reset currents. It can thus be seen that, even though the first and second recording layers  32   1  and  32   2  are the same material and fed with the same writing current, the active regions thereof can have different phases. As such, different information can be recorded using different effective resistance values generated by different phase combinations. This is achieved by adopting the adequate top-view areas for the first and second recording layers  32   1  and  32   2  so that different phase combinations are distinguishable, for example, by measuring the effective resistance value between the first and second electrodes  31   1  and  31   2 . 
       FIG. 5  shows respective programming curves for the first and second recording layers  32   1  and  32   2  of  FIG. 3 , illustrating the relationship between resistance values and writing current. The lateral axis represents the writing current through the first or second recording layer  32   1  or  32   2  and the vertical axis represents the resulting resistance value of the same. The initial phase at the beginning of a write operation is determined by the previous writing state. In the figure, curves GST 1   1  and GST 1   2  respectively represent programming curves of the first recording layers  32   1  with the initial phase in crystalline and amorphous states, and curves GST 2   1  and GST 2   2  respectively represent programming curves of the second recording layers  32   2  with the initial phase in crystalline and amorphous states. The discussion is now made for the first recording layer  32   1  first. If the first recording layer  32   1  is initially in a crystalline state, as shown by the curve GST 1   1 , when the writing current falls below I 3 , the first recording layer  32   1  stays in the crystalline state and thus has a crystalline resistance value R L1 , however, when the writing current exceeds I 3 , the active region of the first recording layer  32   1  melts by Joule heating and then cools immediately to change to amorphous state and the first recording layer  32   1  thus has an amorphous resistance value R H1 . Conversely, if the first recording layer  32   1  is initially in an amorphous state, as shown by the curve GST 1   2 , when the writing current falls below I 1 , since the thermal energy is insufficient to change the phase of the first recording layer  32   1 , the first recording layer  32   1  stays in the amorphous state and thus has the amorphous resistance value R H1 ; when the writing current falls beyond I 1  but below I 3 , since the temperature of the active region of the first recording layer  32   1  increases beyond the crystallization temperature by Joule heating, the active region goes through a nucleation and growth process to reach a crystalline state and thus has the crystalline resistance value R L1 ; when the writing current is further increased to exceed I 3 , the active region melts by Joule heating and then cools down immediately once more, consequently returning to the amorphous state and thus having the amorphous resistance value R H1 . The current I 3  is thus referred to as a reset current of the first recording layer  32   1 . 
     The second recording layer  32   2  undergoes similar transition process. If the second recording layer  32   2  is in a crystalline state initially, as shown by the curve GST 2   1 , when the writing current falls below I 4 , the second recording layer  32   2  stays in the crystalline state and thus has a crystalline resistance value R L2 ; however, when the writing current exceeds I 4 , the active region of the second recording layer  32   2  transits from the crystalline state to an amorphous state and thus has an amorphous resistance value R H2 . Conversely, if the second recording layer  32   2  is initially in an amorphous state, as shown by the curve GST 2   2 , when the writing current falls below I 2 , since the thermal energy is insufficient to change the crystal structure of the second recording layer  32   2 , the second recording layer  32   2  stays in the amorphous state and thus has the amorphous resistance value R H2 ; when the writing current falls beyond I 2  but below I 4 , since the temperature of the active region of the second recording layer  32   2  increases beyond the crystallization temperature by Joule heating, the active region goes through a nucleation and growth process to reach a crystalline state and thus has the crystalline resistance value R L2 ; when the writing current is further increased to exceed I 4 , the active region melts by Joule heating and then cools immediately once more, consequently returning to the amorphous state and thus having the amorphous resistance value R H2 . The current I 4  is thus referred to as a reset current of the second recording layer  32   2 . 
     As shown in  FIG. 4 , because the top-view area of the first recording layer  32   1  is smaller than that of the second recording layer  32   2 , the reset current I 3  of the first recording layer  32   1  is lower than the reset current I 4  of the second recording layer  32   2 . 
       FIG. 6  shows programming curves for the phase change memory cell  300  of  FIG. 3 , illustrating the relationship between resistance values and writing current. The lateral axis represents the writing current from the first recording layer  32   1  to the second recording layer  32   2  and the vertical axis represents the resulting effective resistance value between the first and second electrodes  31   1  and  31   2 , which is substantially equal to series resistance of the first and second recording layers  32   1  and  32   2 . Different programming curves correspond to different initial phase combinations of the first and second recording layers  32   1  and  32   2  dependent upon the previous writing state. In the figure, curves GST_ 1 , GST_ 2  and GST_ 3  are respectively programming curves with the first and second recording layers  32   1  and  32   2  both in crystalline state (denoted as state  0 ), respectively in amorphous and crystalline states (denoted as state  1 ) and both in amorphous state (denoted as state  2 ) after the previous writing operation. 
     As shown in  FIG. 6 , programming curves GST_ 1 -GST_ 3  differ greatly for the current below I 2  due to different initial states, so programming current below I 2  is not adequate to be used in write operations. Conversely, programming curves GST_ 1 -GST_ 3  are almost the same for the current beyond I 2 , that is, the effective resistance values are undistinguishable even with different initial states. For this reason, current beyond I 2  can be used in write operation. As shown, when the writing current is between I 2  and I 3 , between I 3  and I 4 , and beyond I 4 , the phase change memory cell  300  is respectively in state  0 , state  1 , and state  2 , having a corresponding resistance value R( 0 )=R L1 +R L2 , R( 1 )=R H1 +R L2 , and R( 2 )=R H1 +R H2 . 
     Accordingly, write operations are performed on the phase change memory cell  300  by feeding writing current through the first and second recording layers  32   1  and  32   2 , wherein the magnitude of the writing current is determined according to which of the states  0 - 2  is to be written. 
       FIG. 7A  is a relational table of written states to writing current in accordance with a first embodiment of the invention. When a writing operating is performed to achieve state  0 ,  1  or  2 , the writing current I is respectively I 2 &lt;I&lt;I 3 , I 3 &lt;I&lt;I 4  and I 4 &lt;I. 
       FIG. 7B  is a relational table of written states to writing current in accordance with a second embodiment of the invention, differing from the first embodiment only in that, during any write operation, a first-stage write operation is first performed using a reset current between I 2  and I 3  to reset the cell to state  0 , and a second-stage operation is then performed using a writing current dependent on the state to be written. The second stage operation is similar to the first embodiment, differing in that when the state  0  is to be written, the writing current can be lower than  13  because the cell has been reset to state  0  regardless of the initial state. The second embodiment ensures the accuracy of the written data while consuming longer writing time than the first embodiment. 
     When a read operation is performed on the phase change memory cell  300  to determine the data stored therein, reading current is fed through the first and second recording layer  32   1  and  32   2  and the resistance value between the first and second electrodes  31   1  and  31   2  is measured. The magnitude of the reading current is kept low enough not to change the phase of the recording layers. When the resistance value is R( 0 )=R L1 +R L2 , R( 1 )=R H1 +R L2 , and R( 2 )=R H1 +R H2 , the phase change memory cell  300  stores respectively state  0 , state  1  and state  2 . 
       FIG. 8  is a cross section of a phase change memory cell  800  in accordance with another embodiment of the invention, differing from the phase change memory cell  300  only in that the first recording layer  82   1  and the second recording layer  82   2  have different thicknesses (respectively denoted as PT 1  and PT 2 ) while having the same the top-view areas (that is, the diameters or edge lengths under a top-view of recording layers  82   1  and  82   2  in the memory cell  800 ). Reference numbers  84   1  and  84   2  respectively represent first and second blocking layers. The embodiment shown comprises PT 1  larger than PT 2 , but PT 1  can also be smaller than PT 2 . Similarly, the materials-of the first and second recording layers  82   1  and  82   2  can be the same or different. The embodiment uses the former to simplify the description. 
       FIG. 9  shows relationship of reset current with the thickness of a phase change material proposed by Samsung corporation in IEDM  2003 , illustrating programming mechanism of the phase change memory cell  800  of the invention. As shown, phase change materials with different thicknesses have different magnitudes of reset current. Thus, even though the first and second recording layers  82   1  and  82   2  are the same material and fed with the same writing current, the active regions of them can have different phases. 
       FIG. 10  shows respective programming curves for the first and second recording layers  82   1  and  82   2  of  FIG. 8 , illustrating the relationship between resistance values and writing current. In the figure, curves GST 1   1  and GST 1   2  respectively represent programming curves of the first recording layers  82   1  with the initial phase in crystalline and amorphous states, and curves GST 2   1  and GST 2   2  respectively represent programming curves of the second recording layers  82   2  with the initial phase in crystalline and amorphous states. As shown, the first and second recording layers  82   1  and  82   2  have resistance values R L1  and R L2  respectively in crystalline state and R H1  and R H2  respectively in amorphous state. As shown in  FIG. 9 , because the thickness of the first recording layer  82   1  is higher than that of the second recording layer  82   2 , the reset current I 3  of the first recording layer  82   1  is lower than the reset current I 4  of the second recording layer  82   2 . The figure is similar to  FIG. 5  and the description is thus omitted for brevity. 
       FIG. 11  shows programming curves for the phase change memory cell  800  of  FIG. 8 , illustrating the relationship between resistance values and writing current. In the figure, curves GST_ 1 , GST_ 2  and GST_ 3  are respectively programming curves with the first and second recording layers  82   1  and  82   2  both in crystalline state (denoted as state  0 ), respectively in amorphous and crystalline states (denoted as state  1 ) and both in amorphous state (denoted as state  2 ) after the previous writing operation. As shown, writing currents in intervals between I 2  and I 3 , between I 3  and I 4 , and beyond I 4  correspond respectively to diverse resistance values R( 0 )=R L1 +R L2 , R( 1 )=R H1 +R L2 , and R( 2 )=R H1 +R H2 . The figure is similar to  FIG. 6  and the description is thus omitted for brevity. 
     Accordingly, write operation is performed on the phase change memory cell  800  by feeding writing current through the first and second recording layers  82   1  and  82   2 , wherein the magnitude of the writing current is determined according to which of the states  0 - 2  is to be written. Embodiments of writing currents corresponding to written states can also be referenced in  FIGS. 7A and 7B . Similarly, when a read operation is performed on the phase change memory cell  800  to determine the data stored therein, reading current of appropriate magnitude is fed through the first and second recording layer  82   1  and  82   2  and the resistance value between the first and second electrodes  31   1  and  31   2  is measured. 
     It is noted that, the embodiments shown in  FIGS. 3 and 8  respectively, the first and second recording layers have different top-view areas and thicknesses. The two embodiments, however, can be combined. That is, the first and second recording layers differ in not only top-view area but also thickness. In summary, the first and second recording layers have different “dimensions” such that different combinations of the crystalline and amorphous resistance are generated with different writing currents. 
       FIG. 12  is a cross section of a phase change memory cell  1200  in accordance with another embodiment of the invention, differing from the phase change memory cell  300  only in that the first recording layer  122   1  and the second recording layer  122   2  have the same dimensions (in both thicknesses and top-view areas). Furthermore, the contact area between the first heating plug  123   1  and the first recording layer  122   1  (denoted as VA 1 ) and the contact area between the second heating plug  123   2  and the second recording layer  122   2  (denoted as VA 2 ) are different. Reference numbers  124   1  and  124   2  respectively represent first and second blocking layers. The embodiment shown comprises VA 1  smaller than VA 2 , but VA 1  can also be larger than VA 2 . 
       FIG. 13  shows relationship between reset current and the contact area of heating plugs of a phase change material proposed by Samsung corporation in IEDM  2003 , illustrating programming mechanism of the phase change memory cell  1200  of the invention. As shown, phase change materials with different contact areas of heating plugs have different magnitudes of reset current. Thus, even though the first and second recording layers  122   1  and  122   2  are the same material and fed with the same writing current, the active regions thereof can have different phases. 
       FIG. 14  shows respective programming curves for the first and second recording layers  122   1  and  122   2  of  FIG. 12 , illustrating the relationship between resistance values and writing current. In the figure, curves GST 1   1  and GST 1   2  respectively represent programming curves of the first recording layers  122   1  with the initial phase in crystalline and amorphous states, and curves GST 2   1  and GST 2   2  respectively represent programming curves of the second recording layers  122   2  with the initial phase in crystalline and amorphous states. As shown, the first and second recording layers  122   1  and  122   2  have resistance values R L1  and R L2  respectively in crystalline state and R H1  and R H2  respectively in amorphous state. As shown in  FIG. 13 , because VA 1  is smaller than VA 2 , the reset current I 3  of the first recording layer  122   1  is lower than the reset current I 4  of the second recording layer  122   2 . The figure is similar to  FIG. 5  and the description is thus omitted for brevity. 
       FIG. 15  shows programming curves for the phase change memory cell  1200  of  FIG. 12 , illustrating the relationship between resistance values and writing current. In the figure, curves GST_ 1 , GST_ 2  and GST_ 3  are respectively programming curves with the first and second recording layers  122   1  and  122   2  both in crystalline state (denoted as state  0 ), respectively in amorphous and crystalline states (denoted as state  1 ) and both in amorphous state (denoted as state  2 ) after the previous writing operation. As shown, writing currents in intervals between I 2  and I 3 , between I 3  and I 4 , and beyond I 4  correspond respectively to diverse resistance values R( 0 )=R L1 +R L2 , R( 1 )=R H1 +R L2 , and R( 2 )=R H1 +R H2 . The figure is similar to  FIG. 6  and the description is thus omitted for brevity. 
     Accordingly, write operation is performed on the phase change memory cell  1200  by feeding writing current through the first and second recording layers  122   1  and  122   2 , wherein the magnitude of the writing current is determined according to which of the states  0 - 2  is to be written. Embodiments of writing currents corresponding to written states can also be referenced in  FIGS. 7A and 7B . Similarly, when a read operation is performed on the phase change memory cell  1200  to determine the data stored therein, reading current of appropriate magnitude is fed through the first and second recording layer  122   1  and  122   2  and the resistance value between the first and second electrodes  31   1  and  31   2  is measured. 
       FIG. 16  is a cross section of a phase change memory cell  1600  in accordance with another embodiment of the invention, differing from the phase change memory cell  300  only in that the first recording layer  162   1  and the second recording layer  162   2  have the same dimensions (in both thicknesses and top-view areas). Furthermore, an interlayer  161  is inserted between the first heating plug  33   1  and the first recording layer  162   1 . Preferably, the material of the interlayer  161  is metal, semimetal or semiconductor with low thermal conductivity and high resistivity, such as TiN, TiAlN, TiW and SiC, to improve heating effect of writing current on the first recording layer  162   1 . Reference numbers  164   1  and  164   2  respectively represent first and second blocking layers. The embodiment shown comprises the interlayer  161  disposed between the first heating plug  33   1  and the first recording layer  162   1 , but the interlayer  161  can also be disposed between the second heating plug  33   2  and the second recording layer  162   2 . Additionally, the interlayer  161  is not required to cover the entire bottom surface of the first recording layer  162   1 , only to cover a partial area of the contact area of the first recording layer  162   1  with the first heating plug  33   1 . 
       FIG. 17  shows respective programming curves for the first and second recording layers  162   1  and  162   2  of  FIG. 16 , illustrating the relationship between resistance values and writing current. In the figure, curves GST 1   1  and GST 1   2  respectively represent programming curves of the first recording layers  162   1  with the initial phase in crystalline and amorphous states, and curves GST 2   1  and GST 2   2  respectively represent programming curves of the second recording layers  162   2  with the initial phase in crystalline and amorphous states. As shown, the first and second recording layers  162   1  and  162   2  have resistance values R L1  and R L2  respectively in crystalline states and R H1  and R H2  respectively in amorphous states. Because the first recording layer  162   1  is close to the interlayer  161 , the heating effect of the writing current on the first recording layer  162   1  is thus better than that on the second recording layer  162   2 , and the temperature increase of an active area of the first recording layer  162   1  accordingly exceeds that of the second recording layer  162   2 , the reset current I 3  of the first recording layer  162   1  is lower than the reset current I 4  of the second recording layer  162   2 . The figure is similar to  FIG. 5  and the description is thus omitted for brevity. 
       FIG. 18  shows programming curves for the phase change memory cell  1600  of  FIG. 16 , illustrating the relationship between resistance values and writing current. In the figure, curves GST_ 1 , GST_ 2  and GST_ 3  are respectively programming curves with the first and second recording layers  162   1  and  162   2  both in crystalline state (denoted as state  0 ), respectively in amorphous and crystalline states (denoted as state  1 ) and both in amorphous state (denoted as state  2 ) after the previous writing operation. As shown, writing currents in intervals between I 2  and I 3 , between I 3  and I 4 , and beyond I 4  correspond respectively to diverse resistance values R( 0 )=R L1 +R L2 , R( 1 )=R H1 +R L2 , and R( 2 )=R H1 +R H2 . The figure is similar to  FIG. 6  and the description is thus omitted for brevity. 
     Accordingly, write operation is performed on the phase change memory cell  1600  by feeding writing current through the first and second recording layers  162   1  and  162   2 , wherein the magnitude of the writing current is determined according to which of the states  0 - 2  is to be written. Embodiments of writing currents corresponding to written states can also be referenced in  FIGS. 7A and 7B . Similarly, when a read operation is performed on the phase change memory cell  1600  to determine the data stored therein, reading current of appropriate magnitude is fed through the first and second recording layer  162   1  and  162   2  and the resistance value between the first and second electrodes  31   1  and  31   2  is measured. 
     The first and second recording layers are connected in series in  FIGS. 3 ,  8 ,  12  and  16 . The invention, however, is not limited thereto, and the first and second recording layers can be connected in parallel as shown in  FIGS. 19 ,  20 ,  21  and  22 . As such, resistance corresponding to states  0  to  2  are respectively R( 0 )=(R L1 ·R L2 )/(R L1 +R L2 ), R( 1 )=(R H1 ·R L2 )/(R H1 +R L2 ), and R( 2 )=(R H1 ·R H2 )/(R H1 +R H2 ). Similarly, when a write operation is performed, the magnitude of the writing current is determined according to which of the states  0 - 2  is to be written. When a read operation is performed to determine the stored state, a reading current of appropriate magnitude is fed through the first and second recording layer  162   1  and  162   2  and the resistance value between the first and second electrodes  31   1  and  31   2  is measured. 
     It is noted that the embodiments can be combined as required. For example, in an embodiment, the first and second recording layers differ not only in dimensions, but also in the contact areas respectively with the first and second heating plugs. Additionally, although the embodiments all have two recording layers and provide three-level operations, the phase change memory cell of the invention can be realized with more than two recording layers and/or provision of more-than-three level operation. When a phase change memory cell has more than three recording layers, the recording layers are not required to have only a series or parallel connection, but can have combinations of series and parallel connections, such as one recording layer connected in parallel with other two recording layers connected in series. 
     The invention increases memory cell density since not only multilevel operation is achieved but also recording layers can be stacked perpendicularly between the first and second electrode thereby not occupying excess area. Furthermore, the invention can be implemented with a single phase change material of the recording layers, so fabrication process is simpler and process compatibility is better than in the conventional phase change memories implemented with various phase change materials. The invention can be realized by currently developed semiconductor fabrication process technologies. Furthermore, the invention has better controllability in multilevel operation, since programming current can be readily adjusted through structural parameters of recording layers, heating plugs and interlayer(s), operation characteristics of only one recording layer can be considered, and operation between different states is easily controlled due to sufficiently large current programming intervals corresponding to different states. 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.