Abstract:
An apparatus and method of shifting a low-voltage-swing digital signal to a signal of the same polarity with a relatively higher voltage swing are described which eliminate static current consumption by way of a feedback circuit and a pull-up device. By the use of embodiments according to the invention, little power is consumed, and hot electron injection as a mechanism for FET degradation is of little concern. Additionally, no specialized reference voltage is necessary, and precise layout of the circuit is not critical to proper circuit performance.

Description:
BACKGROUND OF THE INVENTION 
     Over the last few years, CMOS-based (complementary metal-oxide-semiconductor) digital logic IC (integrated circuit) technologies have been devised which operate at progressively lower power supply voltages with each passing design generation. Lower supply voltages dictate lower voltage swings for the associated digital signals, which typically traverse between ground and the power supply voltage. The benefits of using lower supply voltages are lower power consumption and faster signal switching times. However, along with these advantages comes the consequence of lower noise margins. CMOS logic IC power supply voltages currently available include, for example, 3.3 V, 2.5 V, 1.8 V, and 1.5 V. Depending on the application, a mix of the various CMOS technologies may be used in any particular electronic product, necessitating the use of digital voltage level shifters to translate CMOS signals generated using one power supply voltage to signals based on a different voltage level. 
     With respect to transforming a low-voltage-swing digital signal to a higher-voltage-swing signal, various types of CMOS voltage level shifters have been devised over the last few years. One simple example is depicted in FIG. 1, utilizing a pair of complementary MOS FETs (Field Effect Transistors) structured as CMOS inverters. A P-FET (p-channel FET) P IN , and an N-FET (n-channel FET) N IN , form an input signal inverter  100 , and another pair of complementary FETs, a P-FET P OUT  and an N-FET N OUT , make up an output signal inverter  110 . With such a circuit, an input signal V IN  with a voltage swing between ground and a low power supply voltage V DDL , is converted to an output signal V OUT , with a voltage swing between ground and a high power supply voltage V DDH . Input signal V IN  is passed to input signal inverter  100 , which logically inverts input signal V IN  to the opposite polarity at a node  120 . The signal at node  120  is then inverted once again by output signal inverter  110  to yield output signal V OUT  that is of the same polarity as V IN , but possesses a higher voltage swing. 
     Normally, the two FETS of a CMOS inverter, such as those in FIG. 1, will work in tandem so that one FET is completely “ON”, or conducting current between the drain and source terminals of the FET, while the other is “OFF”. When V IN  is at a logic LOW of approximately zero volts, for example, FET N IN  will be OFF, while FET P IN  will be fully ON, causing node  120  to be pulled up substantially to voltage V DDH . This voltage at node  120 , in turn, causes, FET P OUT  to turn OFF completely, while N OUT  is fully ON, causing V OUT  to be pulled down essentially to ground. However, in the case where V IN  is at a HIGH logic state of V DDL  volts, N IN  is ON, while P IN  is partially ON. P IN  is not completely OFF in this case since the voltage at the gate of P IN  is not as high as the V DDH  volts imposed on the drain of P IN . Having both P IN  and N IN  ON results in a static current flowing from high power supply voltage V DDH  to ground through input signal inverter  100 . Having such static current flowing during a time when no signal transitions are occurring causes increased power consumption and unwanted heat generation by the circuit. Additionally, the phenomenon of hot electron injection, which degrades FET performance by changing the characteristics of the FET, becomes a possibility. 
     Other level shifters from the prior art include those employing a differential amplifier, an example of which is shown in FIG.  2 . In this circuit, a bias voltage V BIAS  drives the gate of an N-FET N SOURCE , to implement a constant current source  200 . Connected in series with current source  200  is a left-hand branch  210 . (consisting of a first load FET P LD1  and a first input FET N IN1 ), in parallel with a right-hand branch  220  (formed from a second load FET P LD2  and a second input FET N IN2 ). A reference voltage V REF  is used in right-hand branch  220  as a threshold against which an input signal V IN , used by left-hand branch  210 , is compared. If V IN  is less than V REF , more current flows in right-hand branch  220  than in left-hand branch  210 , causing node  230  to be pulled toward ground. Node  230 , in turn, is input to a digital buffer  240 , which converts the substantially analog signal on node  230  into a digital output signal V OUT  with a voltage swing between ground and V DDH . With V IN  less than V REF , output signal V OUT  will be at a logic LOW, or essentially ground. Conversely, V IN  being greater than V REF  causes less current to flow in right-hand branch  220 , thus causing node  230  to be pulled toward V DDH . Digital buffer  240  then converts the analog signal of node  230  to a digital HIGH level of V DDH  at V OUT . The disadvantage of this circuit is similar to those of the level shifter of FIG.  1 : static current being drawn, resulting in increased power consumption and heat generation. Additionally, the circuit of FIG. 2 requires an extremely stable reference voltage V REF . Furthermore, the like components of left-hand branch  210  and right-hand branch  220  must be closely matched in size, making the physical layout of branches  210  and  220  critical. 
     In addition to the aforementioned problems, neither of the level shifting circuits of FIG. 1 or FIG. 2 offers any input hysteresis. In other words, a value of input signal V IN  which causes a change in output signal V OUT  is the same regardless of whether input signal V IN  changes from a logic LOW to HIGH, or from HIGH to LOW. Input hysteresis is valuable in noise-prone environments, and especially when using low-voltage digital logic technologies, such as those mentioned earlier, since digital signals with low-voltage swings typically allow small amounts of noise to force a signal past the threshold voltage for that logic family. 
     Other voltage level shifters other than those mentioned above have been developed over the years, and, by way of example, various forms of such devices can be found in U.S. Pat. Nos. 4,486,670, 4,501,978, 5,742,183, and 6,005,432. 
     From the foregoing, it is apparent that a need exists for a digital voltage level circuit, which converts lower-voltage-swing digital signals, to those of a higher voltage swing, while at the same time producing essentially no static current, thereby consuming less power and generating less heat. It is also desirable for such a circuit to require no reference voltage, to require no special layout considerations, and to provide some input hysteresis to protect against false logic triggering by local noise sources. 
     SUMMARY OF THE INVENTION 
     Embodiments of the invention, to be discussed in detail below, convert a digital signal with a low-voltage swing to a digital signal with a relative high-voltage swing without consuming power by way of static current. Also, no special layout considerations are required, and input hysteresis is provided to counteract the effects of noise injected into the input signal. 
     In one embodiment of the invention, the input signal drives a first and second input signal inverter of the voltage level shifter apparatus simultaneously. The first inverter transforms the input signal into a logically inverted form of the input signal with a high-voltage swing, while the second inverter transforms the input signal into a logically inverted signal with a relatively lower voltage swing. It is this low-voltage-swing inverter that helps provide the hysteresis exhibited by the embodiments of the invention. A third inverter is then used to invert the high-voltage-swing signal so that the proper high-voltage-swing output signal is produced. Both the high-voltage-swing signals and the low-voltage-swing signals are used to drive a feedback unit. This feedback unit, in turn, produces a feedback signal for controlling a pull-up device responsible for delivering power to the first inverter. When necessary, as will be discussed later, the pull-up device shuts off power to the first high-voltage inverter so that the voltage level shifter will draw no static current. 
     Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a first digital level shift circuit from the prior art. 
     FIG. 2 is a schematic diagram of a second digital level shift circuit from the prior art. 
     FIG. 3 is a schematic diagram of a digital level shift circuit according to an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     One embodiment of the invention is displayed in FIG. 3. A digital low-voltage-swing input signal to be shifted is represented by an input signal V IN , which, in this case, is a digital signal that exhibits a logic LOW level of ground, or zero volts, and a HIGH level of a low voltage supply V DDL . The level shifter generates an output signal V OUT , which is a digital signal having a LOW level of ground and a HIGH level of a high voltage supply V DDH , where V DDH  is greater than V DDL . In one embodiment, V DDH  is 3.3V, while V DDL  is 1.5V. Many other combinations for V DDH  and V DDL , respectively, are also possible, such as 3.3V and 2.5V, 2.5V and 1.8V, and so on. Additionally, other embodiments of the invention exist such that the LOW level voltage can be positive or negative compared to some arbitrary ground reference, as long as V DDH  and V DDL  are both at a higher voltage potential than the LOW level voltage. 
     From the embodiment of FIG. 3, V IN  drives two inverters: a first inverter  300  and a second inverter  310 , which are composed of complementary MOS FET pairs connected in series as CMOS inverters. For example, first inverter  300  is made up of a p-channel FET P 1  connected in series with an n-channel FET N 1 . The gate terminals of P 1  and N 1  are connected together and constitute the input of first inverter  300 , and the drain terminals of P 1  and N 1  are tied together to provide the inverter output. To provide power for first inverter  300 , the source terminal of N 1  is connected to ground, and the source of P 1  is connected indirectly to high voltage supply V DDH  by way of pull-up device  340 . (The use of pull-up device  340  will be discussed in detail below.) The output of first inverter  300  drives both a third inverter  320 , and an input of a feedback unit  330 , to be discussed later. 
     A second inverter  310  is, in the embodiment of FIG. 3, made up of the same type of CMOS inverter used for first inverter  300 . In this particular case, p-channel FET P 2  and n-channel FET N 2  form second inverter  310 . The source of P 2  is attached to low voltage supply V DDL , while the source of N 2  is connected to ground. As stated earlier, second inverter  310  is driven by input signal V IN . In turn, the output of second inverter  310  drives a second input of feedback unit  330 . 
     Third inverter  320 , in the embodiment of FIG. 3, is another CMOS inverter, made of p-channel FET P 3  and n-channel FET N 3 , with its output generating output signal V OUT . 
     Feedback unit  330  provides a way of using the outputs of first inverter  300  and second inverter  310  to control pull-up device  340 . In the embodiment shown in FIG. 3, a p-channel FET P FB  and an n-channel FET N FB  are connected in series at their respective drains, which are also connected to the input of pull-up device  340 . The source of P FB  is attached to V DDH , while the source of N FB  is connected to ground. Unlike a CMOS inverter, the gates of P FB  and N FB  are not tied together; instead, the gate of P FB  is tied to the output of first inverter  300 , while the gate of N FB  is tied to second inverter  310 . 
     Finally, pull-up device  340 , in the embodiment of FIG. 3, comprises a single p-channel FET P PU . The source of P PU  is tied to high voltage supply V DDH , while the associated drain is tied to the source of P 1  of first inverter  300 . The source-to-drain path of P PU  selectively provides a power connection between first inverter  300  and high-voltage supply V DDH , based on the state of the output of feedback unit  330  being attached to the gate of P PU . During times when the gate of P PU  is pulled toward ground, P PU  conducts, or is ON, therefore connecting high voltage supply V DDH  with first inverter  300 . Otherwise, the gate of P PU  is pulled toward V DDH , thereby turning OFF P PU , and isolating high-voltage supply V DDH  from first inverter  300 , which prohibits any potential static current to flow through P 1  and N 1  to ground. 
     To fully understand the benefits of the digital voltage level shift circuit of FIG. 3, a step-by-step analysis of its operation is instructive. Beginning with V IN  at a voltage level of zero volts, or a LOW logic state, then N 1  is OFF, and P 1  is ON. If node  370  is initially in a HIGH state of V DDH  volts, P PU  is OFF, causing node  350  to float, or not being driven to any particular voltage, since the source of P 1  is not connected with V DDH  at that time. Concurrently, V IN  being LOW also causes N 2  to be OFF and P 2  to be ON, thereby raising node  360  to a logic HIGH of V DDL  volts. As a result, N FB  is turned ON, thus pulling node  370  substantially to ground, which turns ON P PU  and supplies the source of P 1  with V DDH  volts. Since P 1  is ON, node  350  is pulled up to V DDH  volts as well, causing P 3  to turn OFF, and N 3  to turn ON. As a result, output signal V OUT  is pulled to ground, which matches the level of V IN . Node  350  being at V DDH  volts also causes P FB  to turn OFF, thereby eliminating any static current that may flow through P FB  and N FB . 
     Analyzing the case when V IN  rises to a logic HIGH of V DDL  volts, FET N 1  turns ON, but P 1  does not completely turn OFF initially since the source of P 1  is at a voltage level of V DDH  volts. Thus, static current flows through P PU , P 1 , and N 1  temporarily. Given the nature of normal CMOS processes that are well-known in the art, n-channel FETs have approximately twice the current sinking and sourcing capability of identically-sized p-channel FETs. Additionally, the circuit of FIG. 3 has two p-channel FETs, P 1  and P PU , connected in series, thereby further reducing the “strength” of P 1  and P PU  in comparison to N 1 . Therefore, N 1  succeeds in pulling node  350  substantially to ground. V IN  also turns N 2  ON and P 2  completely OFF (since the source of P 2  is attached to V DDL ), thus pulling node  360  substantially to ground. With the gates of both P FB  and N FB  pulled LOW, node  370  is pulled up substantially to V DDH  volts, thereby shutting OFF P PU  and eliminating the static current that previous flowed through P PU , P 1 , and N 1 , and terminating the drive fight between P 1  and N 1 . Also, with node  350  being substantially at zero volts, P 3  is ON, N 3  is OFF, and V OUT  is pulled up to V DDH  volts, all in response to V IN  rising to V DDL  volts. 
     To complete the description of the entire cycle, assume input signal V IN  returns to zero volts. In response, FETs P 1  and P 2  turn ON, and N 1  and N 2  turn OFF completely, causing node  360  to be raised to V DDL  volts once again. As a result, N FB  is turned ON, causing P PU  to turn back ON, thus raising node  350  to V DDH  volts, turning off P FB  in the process to once again eliminate static current through P FB  and N FB . Also, the gates of P 3  and N 3  are pulled to V DDH , causing N 3  to turn ON, P 3  to turn OFF completely, and V OUT  to be pulled substantially to ground, thereby following the logic state of V IN . 
     Additionally, the embodiment of FIG. 3 exhibits hysteresis as a result of first inverter  300  being connected with high voltage supply V DDH  while second inverter  310  is coupled with low voltage supply V DDL . When V IN  is transitioning from a LOW to a HIGH logic state, V IN  must reach a voltage that is typically close to the midpoint between V DDH  and zero so that N 1  may win the drive fight with P 1 , as described earlier, so that node  350  may attain substantially zero volts, since the source of P 1  is at a voltage level of about V DDH  volts. This voltage required for V IN  to be considered a HIGH, which is related somewhat to the relative size of P 1  compared to N 1 , is typically higher than the voltage required for V IN  to be perceived as a LOW state when transitioning from the HIGH state, according to the operation of the embodiment of FIG.  3 . For V OUT  to go LOW, V IN  must be close enough to ground to shut OFF N 2  and turn ON P 2  sufficiently for N FB  to turn ON and start the process of switching V OUT  from a logic HIGH to a logic LOW, since the source of P 2  is attached to low-voltage supply V DDL . Hence, with a higher voltage required of V IN  to switch V OUT  HIGH when compared to the voltage required to switch V OUT  LOW, the voltage level shifter of FIG. 3 thus exhibits hysteresis. 
     Up to this point, it has been assumed that all p-channel and n-channel FETs of the embodiment of FIG. 3 are essentially the same size. However, in other embodiments of the invention, it may be desirable to change the size of the FETs in relation to each other to improve certain performance characteristics of the voltage level shifter. For example, it may be desirable to make N 1  larger than P 1  to further ensure that N 1  wins the drive fight with P 1  when Vin rises to V DDL , as described earlier. Similarly, it may be advantageous for P 2  to be made larger than N 2 , and for N 3  to made larger than P 3 , so that the switching voltages for second inverter  310  and third inverter  320  are modified to decrease the switching time involved when V IN  rises to V DDL . N FB  may also be made larger than P FB  toward the same timing goal. The particular timing needs of an electronic circuit that includes the voltage level shifter of FIG. 3 can be used to determine the appropriate sizes of the FETs used. 
     From the foregoing, it will be apparent that the invention provides a simple digital voltage level shifting circuit that consumes virtually no static current while the input signal of the shifter maintains a stable logic state. Additionally, input hysteresis is provided by embodiments of the invention so that the generated output signal is resistant to the effects of noise at the input of the level shifter. Embodiments other than that shown in FIG. 3 are also possible. As a result, the invention is not to be limited to the specific forms and arrangement of components so described and illustrated; the invention is limited only by the claims.