Abstract:
The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (R LRS ), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.

Description:
BACKGROUND 
       [0001]    The present application relates to a device and a method for writing data into a resistive memory. 
       DISCUSSION OF THE RELATED ART 
       [0002]    Resistive memories are non-volatile memories comprising memory cells each having at least one resistive element capable of having at least two different resistance values, for example, a low value, noted Ron, and a high value, noted Roff. As an example, the resistive element may comprise an electrically-insulating material, data being stored in the resistive element by the presence or the absence of a continuous conductive filament in the electrically-insulating material. When the conductive filament is present, resistance Ron of the resistive element is low, while when the filament is broken or is absent, resistance Roff of the resistive element is high. The passing of the resistance of the resistance element of a memory cell from Ron to Roff and conversely is called switching of the memory cell. 
         [0003]    The fact of switching the resistance of the resistive element of the memory cell from Roff to Ron is called a memory cell write operation. A write operation corresponds to the forming of the conductive filament in the resistive element of the memory cell. This may be obtained by applying a determined voltage for a determined time between a first terminal and a second terminal of the memory cell. The fact of switching the resistance of the resistive element of the memory cell from Ron to Roff is called memory cell delete operation. A delete operation corresponds to the breaking of the filament of the resistive element of the memory cell. For a bipolar memory cell, this may be obtained by applying a determined voltage for a determined time between the second terminal and the first terminal of the memory cell, that is, with a polarity inverted with respect to the write operation. For a unipolar memory cell, this may be obtained by applying a determined voltage having an amplitude different from that of the voltage applied during the write operation. An initialization operation should generally be provided before the first write operation to form the first filament by applying, between the first and second terminals, a higher voltage than that applied during a write operation. The operation of writing into a resistive memory thus corresponds to the performing of operations of writing into and/or deleting from memory cells of the resistive memory. 
         [0004]    A disadvantage of resistive memories is that resistances Ron and Roff obtained after a write operation or a delete operation having a high variability from one memory cell to the other. Further, for a same memory cell, resistance Ron or Roff may vary for two successive write or delete operations. Thereby, the determination of the write or delete voltage and of the duration of application of this voltage is difficult. Indeed, if the write or delete voltage is too low and/or if the duration of application of this voltage is too short, certain memory cells may not switch. However, if the write or delete voltage is too high and/or if the duration of application of this voltage is too long, certain memory cells may deteriorate, which causes a decrease in the lifetime of such memory cells. 
       SUMMARY 
       [0005]    An object of an embodiment is to overcome all or part of the disadvantages of previously-described devices for writing into and deleting from a resistive memory. 
         [0006]    Another object of an embodiment is to increase the robustness of the resistive memory, particularly to decrease the dispersion of resistances Ron and Roff of the memory cells of the resistive memory. 
         [0007]    Another object of an embodiment is to increase the reliability of the resistive memory, that is, to increase the life expectancy of memory cells and to limit the duration of application to the memory cells of excessive currents and voltages during read and write operations. 
         [0008]    Another object of an embodiment is to improve the energetic efficiency of the resistive memory, that is, to decrease the power consumption of the resistive memory while applying conditions sufficient for the read and write operations to occur properly. 
         [0009]    Thus, an embodiment provides a resistive memory comprising resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device comprising a first circuit capable of circulating a first current through at least one first reference resistive component, a second circuit capable, during a switching operations, of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of a first voltage which depends on the voltage across the first reference resistive component with a second voltage which depends on the voltage across the selected resistive element or from the comparison of a third current which depends on the first current with a fourth current which depends on the second current, and a fourth circuit capable of interrupting the second current flowing through the selected resistive element on detection of the switching. 
         [0010]    According to an embodiment, the first circuit is capable of circulating a fifth current proportional to the first current through at least one second reference resistive component. 
         [0011]    According to an embodiment, the memory comprises a current mirror capable of copying the first current flowing through the first reference resistive component, or the fifth current flowing through the second reference resistive component, in said selected resistive element, possibly modified by a multiplication factor. 
         [0012]    According to an embodiment, the resistive elements are arranged in rows and in columns, the memory further comprising, for each row, at least one first conductive track connected to each resistive element in the row and, for each column, a second conductive track connected to each resistive element in the column, the memory further comprising at least one third conductive track connected to the first resistive component, each first conductive track being connected to the third conductive track. 
         [0013]    According to an embodiment, the memory further comprises, for each resistive element, a first switch series-connected with the resistive element, the first conductive track being connected to each first switch in the row, the memory comprising, for each row, a second switch connected to the first conductive track and to the first reference resistive component. 
         [0014]    According to an embodiment, the memory further comprises, for each column, a fourth conductive track, each resistive element being series-connected with the first associated switch between the fourth conductive track and the second conductive track, the memory further comprising a fifth conductive track, each second switch being interposed between the third conductive track and the fifth conductive track. 
         [0015]    According to an embodiment, for each column, the second and fourth conductive tracks are connected to the current mirror and the third conductive track is connected to the current mirror. 
         [0016]    According to an embodiment, the memory comprises a circuit for supplying a reference voltage connected, for each column, to the second and fourth conductive tracks and connected to the fifth conductive track. 
         [0017]    According to an embodiment, the memory comprises, for each row, said first reference resistive component series-connected with the second switch, the fifth conductive track being connected, for each row, to the second switch in the row and the third track being connected, for each row, to the first reference resistive component in the row. 
         [0018]    According to an embodiment, the memory comprises a single first reference resistive component, the third and fifth conductive tracks being connected, for each row, to the second switch in the row and the third track being connected to the single first reference resistive component. 
         [0019]    According to an embodiment, the memory further comprises sixth and seventh conductive tracks, and for each row, a third switch connecting the sixth and seventh conductive tracks, the sixth and/or the seventh conductive track being connected to the second reference resistive component. 
         [0020]    According to an embodiment, the third circuit comprises a comparator receiving the first voltage and the second voltage and providing a binary signal which depends on the sign of the difference between the first voltage and the second voltage. 
         [0021]    According to an embodiment, the memory comprises a fourth switch connected to the fourth conductive track and a fifth switch connected to the second conductive track, the fourth and fifth switches being controlled by the binary signal or a signal derived from the binary signal. 
         [0022]    An embodiment also provides a method of controlling a resistive memory comprising resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, for the switching of the resistance of a resistive element selected from among the resistive elements between the high and low values, the method comprising the steps of: 
         [0023]    circulating a first current through at least one first reference resistive component; 
         [0024]    circulating, during a switching operation, a second current proportional to the first current in the selected resistive element; 
         [0025]    detecting the switching of the resistance of the selected resistive element from the comparison of a first voltage which depends on the voltage across the first reference resistive component with a second voltage which depends on the voltage across the selected resistive element or from the comparison of a third current which depends on the first current with a fourth current which depends on the second current; and 
         [0026]    interrupting the second current flowing through the selected resistive element on detection of the switching. 
         [0027]    According to an embodiment, the first current is increasing during the switching operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, among which: 
           [0029]      FIG. 1  is an electric diagram of an embodiment of a device for deleting from a resistive memory; 
           [0030]      FIG. 2  shows timing diagrams of signals implemented by the device of  FIG. 1  during a delete operation; 
           [0031]      FIGS. 3 to 6  are electric diagrams of embodiments of portions of the delete device of  FIG. 1 ; 
           [0032]      FIGS. 7 and 8  are partial electric diagrams of other embodiments of a resistive memory delete device; 
           [0033]      FIG. 9  is an electric diagram of an embodiment of a device for writing into a resistive memory; 
           [0034]      FIG. 10  shows timing diagrams of signals implemented by the device of  FIG. 9  during a write operation; 
           [0035]      FIG. 11  is an electric diagram of another embodiment of a device for writing into a memory cell of a resistive memory; 
           [0036]      FIGS. 12 and 13  are partial electric diagrams of embodiments of a device for deleting from a memory cell of a resistive memory; 
           [0037]      FIGS. 14 to 16  are electric diagrams of embodiments of a device for writing into a plurality of memory cells of a resistive memory; 
           [0038]      FIG. 17  is an electric diagram of an embodiment of a device for writing into and for deleting from a plurality of memory cells of a resistive memory; 
           [0039]      FIG. 18  is a more detailed electric diagram of an embodiment of a device for writing into and for deleting from memory cells of a resistive memory; and 
           [0040]      FIGS. 19 to 21  are electric diagrams of embodiments of a device for deleting from/writing into a plurality of memory cells of a resistive memory. 
       
    
    
     DETAILED DESCRIPTION 
       [0041]    For clarity, the same elements have been designated with the same reference numerals in the different drawings. In the following description, expressions “substantially”, “around”, and “approximately” mean “to within 10%”. 
         [0042]    In the following description, a signal which alternates between a first constant state, for example, a low state, noted “0”, and a second constant state, for example, a high state, noted “1”, is called “binary signal”. In practice, the binary signals may correspond to voltages or to currents which may not be perfectly constant in the high or low state. The high and low states of binary signals of a same electronic circuit may be different. 
         [0043]    According to an embodiment, an operation of writing into a memory cell of a resistive memory and/or of deleting from the memory cell is carried out as follows:
       application of an increasing voltage or current across the memory cell;   detection of the memory cell switching; and   automatic cutting of the current flowing through the memory cell after the detection.       
 
         [0047]    For each memory cell, the switching of the memory cell occurs when the voltage applied thereacross reaches the voltage necessary for its switching. The switching voltage may thus be different from one memory cell to the other. The memory cell lifetime is advantageously increased since each memory cell is not submitted longer than necessary to the voltage or to the current enabling it to switch. Further, the power consumption of the resistive memory is decreased since the current supplying each memory cell is interrupted as soon as the memory cell has switched. 
         [0048]      FIG. 1  shows an embodiment of a resistive cell  5  comprising an array  10  of memory cells Cell i,j , for example, with N rows and M columns, where N and M are integers greater than 2 and where i is an integer varying from 1 to N and j is an integer which varies from 1 to M. Memory  5  further comprises a device  14  for deleting from memory cells Cell i,j . 
         [0049]    Each memory cell Cell i,j  comprises first and second terminals. For each row of array  10 , the first terminals of the memory cells Cell i,j  in the row are connected to a word line WL i . For each column of array  10 , the second terminals of the memory cells Cell i,j  in the column are connected to a bit line BL j . Each word line WL i , with i varying from 1 to N, is connected to a source of a low reference potential, for example, ground GND, via a switch  16   i . Switches  16   i  are controlled by a word line selection unit  18 . As an example, each switch  16   i  corresponds to a metal-oxide gate field-effect transistor, or MOS transistor, for example, with an N channel, having its drain is connected to word line WL i , having its source connected to ground GND and having its gate controlled by unit  18 . Each bit lines BL j , with j varying from 1 to M, is connected to a switch  20   j . Switches  20   j  are controlled by a bit line selection unit  22 . As an example, each switch  20   j  corresponds to a MOS transistor, for example, with a P channel, having its drain connected to bit line BL j , having its source connected to a node A, and having its gate controlled by unit  22 . 
         [0050]    As an example, each memory cell Cell i,j  may comprise a resistive element where a conductive filament may be formed, in series with a non-linear component. According to another example, each memory cell Cell i,j  may comprise a resistive element in series with a MOS transistor. In this case, the gate of the MOS transistor may be connected to word line W i , one of the terminals of memory cell Cell i,j  being connected to bit line BL j  and the other terminal of memory cell Cell i,j  being connected to a source of a variable potential. 
         [0051]    Delete device  14  comprises a circuit  30  for providing an increasing voltage VRamp at a node B and a circuit  32  receiving voltage VRamp and delivering an increasing reference voltage Vref smaller than voltage VRamp. As an example, circuit  30  is capable of providing a voltage ramp, that is, voltage VRamp is a function linearly increasing along time. As a variation, the first time derivative of voltage VRamp decreases along time. As an example, voltage VRamp successively comprises a first ramp and a second ramp, the first time derivative of voltage VRamp for the second ramp being smaller than the first time derivative of voltage VRamp for the first ramp. 
         [0052]    According to an embodiment, voltage Vref is proportional to voltage VRamp with a proportionality ratio smaller than 1. 
         [0053]    Delete device  14  comprises a resistor Rm between node B and a node C. Resistor Rm may be formed by a polysilicon track. Call Vrm the voltage between node C and ground GND. A switch  34  controlled by a binary signal Din is provided between node C and a node D. Two switches  36  and  38 , assembled in parallel, are provided between nodes D and A. Switch  36  is controlled by a binary signal Rst and switch  38  is controlled by a binary signal G. As an example, each switch  34 ,  36 ,  38  is on when the associated control signal is in a first state, for example, in the low state, and is off when the associated control signal is in a second state, for example, in the high state. According to an embodiment, each switch  34 ,  36 ,  38  corresponds to a P-channel MOS transistor having its gate controlled by the associated control signal. 
         [0054]    Delete device  14  comprises an operational amplifier  40 , assembled as a comparator, having its non-inverting input (+) connected to node C and receiving voltage Vrm and having its inverting input (−) connected to circuit  32  and receiving voltage Vref. Comparator  40  provides signal G. As an example, signal G is at “0” when voltage Vrm is smaller than voltage Vref and is at “1” when voltage Vrm is greater than voltage Vref. 
         [0055]    When a memory cell Cell i,j  is selected for a delete operation, memory cell Cell i,j  and resistor Rm form a voltage dividing bridge. Voltage Vrm is provided by the following relation (1): 
         [0000]    
       
         
           
             
               
                 
                   Vrm 
                   = 
                   
                     
                       RCell 
                       
                         RCell 
                         + 
                         Rm 
                       
                     
                      
                     VRamp 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Rcell is the resistance of the selected memory cell Cell i,j  and is equal to Ron or Roff. 
         [0056]    Resistance Rm is selected so that voltage Vrm is sufficiently high to be measurable and not too high to avoid hindering memory cell write or delete operations or imposing too high a voltage Vramp. As an example, resistance Rm may be substantially equal to Ron/ 10 . Then, voltage Vref is selected so that, when the resistance of the resistive element of the selected memory cell Cell i,j  is equal to Roff, voltage Vrm is smaller than voltage Vref and, when the resistance of the resistive element of memory cell Cell i,j  is equal to Ron, voltage Vrm is greater than voltage Vref. 
         [0057]    Memory array  10  may be divided into a plurality of column groups. The columns of each group of columns may be connected to different nodes A and delete device  14  may be partially duplicated for each group of columns. More specifically, resistor Rm, switches  34 ,  36 ,  38 , and comparator  40  are repeated for each group of columns and circuits  30  and  32  may be common to all the columns groups. 
         [0058]      FIG. 2  shows timing diagrams of signals implemented by memory  5  of  FIG. 1  during a delete operation. Times t 0  to t 5  are successive times. 
         [0059]    At time t 0 , memory cell Cell i,j  where a delete operation should be performed is selected. This is obtained by connecting word line WL i  to ground GND and by turning on transistor  20   j . Further, signal Rst is set to “0”, which turns on transistor  36 . Signal Din is at “0” when a delete operation should be performed in the selected memory cell. Transistor  34  is then conductive. 
         [0060]    At time t 1 , voltage VRamp starts increasing from the zero value. Voltages Vref and Vrm thus start increasing. Further, a current I starts flowing through the selected memory cell Cell i,j . The resistance of the resistive element of memory cell Cell i,j  being equal to Ron, voltage Vrm is smaller than voltage Vref. Signal G delivered by comparator  40  is at “0” as soon as the difference between voltages Vrm and Vref is sufficient. Since the value of signal G may be uncertain as long as voltages Vrm and Vref are not sufficiently different, transistor  36 , which is conductive, enables to provide a conduction path between nodes A and D until it is certain that signal G is at “0”. 
         [0061]    At time t 2 , signal Rst switches from “0” to “1”. Transistor  36  switches to the off state. 
         [0062]    At time t 3 , the voltage applied to memory cell Cell i,j  is sufficiently high to cause the switching of the memory cell. The resistance of the resistive element of memory cell Cell i,j  switches from Ron to Roff. Voltage Vrm then rises above Vref. Current I decreases. 
         [0063]    At time t 4 , signal G provided by comparator  40  switches to “1”. Transistor  38  switches to the off state. Current I cancels and no voltage is applied to memory cell Cell i,j  any longer. 
         [0064]    A time t 5 , circuit  30  interrupts the supply of voltage VRamp, for example, after a determined time. 
         [0065]    As a variation, transistor  36  may be omitted. Delete device  14  may then comprise means for ensuring that signal G is at “0” at the beginning of a delete operation. As an example, delete device  14  may comprise a storage element of flip-flop type between comparator  40  and transistor  38 . 
         [0066]      FIG. 3  shows an embodiment of circuit  30  for supplying voltage VRamp. In this embodiment, circuit  30  comprises a capacitor  42  having an electrode connected to ground GND and having its other electrode connected to the non-inverting input (+) of a follower-assembled operational amplifier  44 . The inverting input (−) of operational amplifier  44  is connected to the output of operational amplifier  44 . Operational amplifier  44  supplies voltage VRamp. Circuit  30  further comprises a P-channel MOS transistor  46  and an N-channel MOS transistor  48 . The source of transistor  46  is connected to a source of a high potential VDD. The drains of transistors  46  and  48  are connected to the non-inverting input (+) of operational amplifier  44 . The source of transistor  48  is connected to ground GND. The gate of the MOS transistor receives a binary signal Ramp_Cmd and the gate of transistor  48  receives a binary signal Ramp_reset. 
         [0067]    Circuit  30  of  FIG. 3  operates as follows. Capacitor  42  is discharged by turning on transistor  48 , transistor  46  being off. Transistor  48  is then turned on and transistor  46  is off. The conduction properties of transistor  46  are selected so that the charge of capacitor  42  is progressive. The voltage across capacitor  42  corresponds to voltage VRamp. Operational amplifier  44  copies voltage Vramp. 
         [0068]      FIG. 4  shows another embodiment of circuit  30  for delivering voltage VRamp. In this embodiment, instead of transistor  46 , a current mirror comprising two P-channel MOS transistors  50  and  52 , a current source  54  delivering a current Iref, and an N-channel MOS transistor  56  are provided. The sources of transistors  50  and  52  are connected to the source of potential VDD. The drain of transistor  52  is connected to the non-inverting input (+) of operational amplifier  44 . The gate of transistor  50  is connected to the gate of transistor  52 , to the drain of transistor  50 , and to a terminal of current source  54 . The other terminal of current source  54  is connected to the drain of transistor  56  and the source of transistor  56  is connected to ground GND. 
         [0069]    The current mirror copies current Iref delivered by current source  54  with a multiplication factor equal to the ratio between the gate widths of transistors  52  and  50 . When transistor  56  is on and transistor  48  is off, capacitor  42  is charged at constant current with the current copied by the current mirror. The embodiment shown in  FIG. 4  enables to obtain a more linear ramp and to better control the duration of the ramp with respect to the embodiment shown in  FIG. 3 . 
         [0070]      FIG. 5  shows another embodiment of circuit  30  for delivering voltage VRamp. As compared with the embodiment shown in  FIG. 4 , capacitor  42  and operational amplifier  44  are not present. The function of capacitor  42  is fulfilled in the present embodiment by the stray capacitance, illustrated in  FIG. 5  by capacitors  58  shown in dotted lines, of the conductive track which transmits voltage VRamp. 
         [0071]      FIG. 6  shows another embodiment of circuit  30  for supplying voltage VRamp. In this embodiment, circuit  30  comprises a counter  60  (Counter) rated by a clock signal CK and delivering a digital signal NUM coded over a plurality of bits. Signal NUM is received by a digital-to-analog converter  62  (DAC) which converts digital signal NUM into an analog signal delivered to the non-inverting input (+) of operational amplifier  44 . The increase rate of signal VRamp is determined by the frequency of clock signal CK and the number of bits of signal NUM. As a variation, a low-pass filter may be interposed between digital-to-analog converter  62  and operational amplifier  44  to smooth voltage VRamp. In practice, the low-pass filter function may be fulfilled by operational amplifier  44  and the stray capacitance of the conductive track transmitting voltage VRamp. 
         [0072]      FIG. 7  shows a more detailed embodiment of delete device  14  where resistor Rm is formed of a diode-assembled P-channel MOS transistor  72 . The source of transistor  72  is connected to node B, the drain and the gate of transistor  72  being connected to node C. 
         [0073]    Circuit  32  for delivering voltage VRamp comprises a diode-assembled P-channel MOS transistor  74  between a node E and a node F. Node E receives voltage VRamp. The source of transistor  74  is connected to node E, the drain and the gate of transistor  74  being connected to node F. Preferably, transistor  74  is identical to transistor  72 . When resistor Rm is formed by a polysilicon track, MOS transistor  74  is preferably replaced with an identical polysilicon resistor. 
         [0074]    Circuit  32  further comprises, between node F and ground GND, an assembly of memory cells  76  assembled in series and in parallel so that equivalent resistance Req of the assembly of memory cells  76  is smaller than Roff. As an example, an assembly of six memory cells  72 , each having a resistance Roff, is shown in  FIG. 7  and the memory cells of this assembly are arranged so that equivalent resistance Req of the assembly of memory cells  76  is equal to ¾*Roff. As a variation, memory cells  76  each having a resistance Ron may be used. Circuit  32  may further comprise, in series with the assembly of memory cells  76 , a resistance representative of the parasitic resistances on bit line BL j  and word line WL i  on selection of memory cell Cell i,j . Since memory cells  76  are series-connected, each memory cell  76  does not see a sufficiently high voltage to switch. Circuit  32  plays the role of a voltage divider. Voltage Vref is provided by the following relation (2): 
         [0000]    
       
         
           
             
               
                 
                   Vref 
                   = 
                   
                     
                       Req 
                       
                         Req 
                         + 
                         Rm 
                       
                     
                      
                     VRamp 
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0075]      FIG. 8  shows another more detailed embodiment of delete device  14  where resistor Rm and transistor  34  shown in  FIG. 1  are replaced with a P-channel MOS transistor  78  having its source connected to node B, having its drain connected to node D, having its gate receiving signal Din, and having its substrate connected to the drain. This means that, in the case where the substrate of transistor  78  corresponds to an N-type doped region where P-type doped regions corresponding to the drain and to the source of transistor  78  are formed, the drain and the substrate are substantially taken to the same potential. 
         [0076]    The embodiment shown in  FIG. 8  advantageously enables to suppress one of MOS transistors  72  and  34  with respect to the embodiment shown in  FIG. 7 . Since the substrate and the drain of transistor  78  are interconnected, the threshold voltage of transistor  78  is all the smaller as voltage Vrm is low. Thereby, it is avoided to lose the threshold voltage of diode-assembled transistor  72  in voltage VRamp. A lower voltage VRamp may thus be used, which enables to decrease the electric power consumption of delete device  14 . 
         [0077]    Preferably, circuit  32  for supplying voltage Vref, shown in  FIG. 8 , comprises, instead of transistor  74  shown in  FIG. 7 , a P-channel MOS transistor  80  identical to transistor  78 , having its source connected to node E, having its drain connected to node F, having its gate connected to ground GND, and having its substrate connected to the drain. 
         [0078]      FIG. 9  shows an embodiment of memory  5  where memory  5  comprises a device  90  for writing into memory cells Cell i,j , that is, capable of having the resistance of the resistive element of a memory cell Cell i,j  switch from Roff to Ron. The elements common with delete device  14  shown in  FIG. 1  are designated with the same reference numerals. 
         [0079]    Each word line WL i , with i ranging from 1 to N, is connected to circuit  30  for supplying voltage VRamp via a switch  92   i . Switches  92   i  are controlled by word line selection unit  18 . As an example, each switch  92  corresponds to a P-channel MOS transistor having its drain connected to word line WL i , having its source connected to circuit  30 , and having its gate controlled by unit  18 . Each bit line BL j , with j varying from 1 to M, is connected to node A via a switch  94   j . Switches  94  are controlled by bit line selection unit  22 . As an example, each switch  94   j  corresponds to an N-channel MOS transistor, having its drain connected to bit line BL j , having its source connected to node A, and having its gate controlled by unit  22 . 
         [0080]    Write device  90  comprises an N-channel MOS transistor  96  having its source connected to ground GND, having its drain connected to a node H, having its gate receiving signal Din, and having its substrate connected to the drain. Call Rm′ the equivalent resistance of transistor  96 . Call Vrm′ the voltage between node H and ground GND. A switch  98  is assembled between nodes H and A. Switch  98  is controlled by a binary signal G′. As an example, switch  98  corresponds to an N-channel MOS transistor, having its source connected to node H, having its drain connected to node A, and having its gate controlled by signal G′. 
         [0081]    Write device  90  further comprises an operational amplifier  100 , assembled as a comparator, having its non-inverting input (+) connected to node H and receiving voltage Vrm′ and having its inverting input (−) connected to circuit  32  and receiving voltage Vref. Comparator  100  provides a binary signal R. As an example, signal R is at “0” when voltage Vrm′ is smaller than voltage Vref and is at “1” when voltage Vrm′ is greater than voltage Vref. 
         [0082]    Write device  90  further comprises a flip-flop type storage element  102 , which delivers signal G′. Flip-flop  102  comprises an S control input receiving binary signal Rst and a R reset input receiving signal R. Conventionally, when signal Rst on the S control input switches from “0” to “1”, output G′ of flip-flop  102  is set to “1”. When signal R on the R reset input switches from “0” to “1”, output G′ of flip-flop  102  switches to “0”. When signal R on the R reset input switches from “1” to “0” or when signal Rst on the S control input switches from “1” to “0”, output G′ of flip-flop  102  is not modified. 
         [0083]    When a memory cell Cell i,j  is selected for a write operation, memory cell Cell i,j  and equivalent resistor Rm′ of MOS transistor  96  form a voltage dividing bridge. Voltage Vrm′ is provided by the following relation (3): 
         [0000]    
       
         
           
             
               
                 
                   
                     Vrm 
                     ′ 
                   
                   = 
                   
                     
                       
                         Rm 
                         ′ 
                       
                       
                         RCell 
                         + 
                         
                           Rm 
                           ′ 
                         
                       
                     
                      
                     VRamp 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0084]      FIG. 10  shows timing diagrams of signals implemented by memory  5  of  FIG. 9  during a write operation. Times t′ 0  to t′ 6  are successive times. 
         [0085]    At time t′ 0 , signal Rst switches to “1”, which causes the setting to “1” of output signal G′ of flip-flop  102 . Transistor  98  thus turns on. Signal Din is at “1” when a write operation should be performed in the selected memory cell. Transistor  96  is then conductive. 
         [0086]    At time t′ 1 , voltage VRamp starts increasing from the zero value. Voltages Vref and Vrm′ thus start increasing. Further, a current I starts flowing through the selected memory cell Cell i,j . The resistance of memory cell Cell i,j  being equal to Roff, voltage Vrm′ is smaller than voltage Vref. Signal R output by comparator  100  is at “0”. However, output G′ of the flip-flop remains at “1”. 
         [0087]    At time t′ 2 , signal Rst switches from “1” to “0”. Output signal G′ of flip-flop  102  is however not modified. 
         [0088]    At time t′ 3 , the voltage applied to memory cell Cell i,j  is sufficiently high to cause the switching of the memory cell. The resistance of the resistive element of memory cell Cell i,j  switches from Roff to Ron. Voltage Vrm′ then rises above Vref. Current I decreases and signal R output by comparator  100  switches to “1”. 
         [0089]    At time t′ 5 , flip-flop  102  receiving signal R sets signal G′ to “0”. Switch  98  switches to the off state. Current I cancels and no voltage is applied to memory cell Cell i,j  any longer. During its drop, voltage Vrm′ becomes smaller than voltage Vref and signal R′ switches to “0”. However, signal G′ is maintained at “0”. 
         [0090]    At time t′ 6 , circuit  30  interrupts the supply of voltage VRamp. 
         [0091]    In the embodiment shown in  FIG. 9 , to perform a write operation, bit line BL j  connected to the selected memory cell Cell i,j  is set to ground GND and word line WL i  connected to the selected memory cell Cell i,j  receives voltage VRamp. This advantageously enables to use the same circuit  30  for a write operation and for a delete operation. According to another embodiment, to perform a delete operation, word line WL i  connected to the selected memory cell Cell i,j  may be set to high potential VDD and bit line BL j  connected to the selected memory cell Cell i,j  may receive a voltage continuously decreasing, for example, from VDD to 0 V. 
         [0092]    According to an embodiment, memory  5  may comprise delete device  14  shown in  FIG. 1  and write device  90  shown in  FIG. 9 . In this case, circuits  30  and  32  may be common to the write and delete devices. Further, in the case where delete device  14  also comprises a flip-flop, flip-flop  102  and operational amplifier  100  may be common to delete device  14  and to write device  90 . 
         [0093]    According to another embodiment, an operation of writing into a memory cell of a resistive memory and/or of deleting from the memory cell is carried out as follows:
       circulating of a current through the memory cell;   comparison of the voltage across the memory cell with a reference voltage;   detection of the switching of the memory cell from the comparison of the voltage across the memory cell with the reference voltage; and   automatic cutting of the current flowing through the memory cell after the detection.       
 
         [0098]    For each memory cell, the power consumption of the memory cell is decreased since the current supplying each memory cell is interrupted as soon as the memory cell has switched. The memory cell lifetime is advantageously preserved since the memory cell is not submitted to the switching voltage longer than necessary. Further, the current flowing through the memory cell is interrupted when the voltage across the memory cell reaches a determined voltage, that is, when the resistance of the memory cell reaches a determined resistance. Advantageously, resistances Ron of the memory cells after a write operation are substantially equal and resistances Roff of the memory cells after a delete operation are substantially equal. 
         [0099]    The operating principle of a write device and of a delete device will first be described for a write or delete operation for a single memory cell. This is followed by the description of the use of the write device and of the delete device with a resistive memory comprising a plurality of memory cells. 
         [0100]      FIG. 11  shows another embodiment of a device  110  for writing into a resistive element R of a memory cell. Write device  110  comprises a programming circuit  114 , an end-of writing detection circuit  116  and a logic feedback circuit  118 . 
         [0101]    Programming circuit  114  comprises a circuit  120  for providing a programming voltage VProg to a node T. Voltage VProg may be a constant voltage or a stepped monotonous voltage, for example, continuously increasing, for example, a voltage ramp, for part of a write or delete operation, for example the beginning of a write or delete operation at least until the switching of the memory cell, and then decreasing at the end of the write or delete operation. Circuit  120  may have the same structure as previously-described circuit  30 . Programming circuit  114  further comprises a reference resistor R LRS  between nodes J and K and a switch  122  controlled by a binary signal SET_ACT between node T and node J. Switch  122  may correspond to a P-channel MOS transistor having its source connected to node T, having its drain connected to node J, and having its gate receiving signal SET_ACT. According to an embodiment, reference resistance R LRS  is substantially equal to the resistance level Ron desired for resistive element R. Resistor R LRS  may be formed by a polysilicon track. 
         [0102]    Resistive element R is placed between nodes L and Z. Programming circuit  114  comprises a switch  124  controlled by a binary signal EN_set_H between node T and node L. Switch  124  may correspond to a P-channel MOS transistor having its source connected to node T, having its drain connected to node L, and having its gate receiving signal EN_set_H. 
         [0103]    Programming circuit  114  comprises a current mirror which copies the current flowing through resistor R LRS  in resistive element R. The current mirror for example comprises a diode-assembled N-channel MOS transistor  126 , having its drain connected to node K, having its source connected to ground GND, and having its gate connected to the drain. The current mirror further comprises an N-channel MOS transistor  128 , having its drain connected to node Z, having its source connected to ground GND, and having its gate connected to the gate of transistor  126 . Call V SET  the voltage between node K and ground GND and V R  the voltage between node Z and ground GND. 
         [0104]    Detection circuit  116  is capable of comparing voltages V SET  and V R . It comprises an N-channel MOS transistor  130  having its source connected to a node O, having its drain connected to a node P, and having its gate connected to node K and receiving voltage V SET . Call V COMP  the voltage between node P and ground GND. Node P is connected to the drain of a P-channel MOS transistor  132 . Detection circuit  116  further comprises an N-channel MOS transistor  134  having its source connected to node O, having its drain connected to the drain of a P-channel MOS transistor  136 , and having its gate connected to node Z and receiving voltage V R . The sources of MOS transistors  132  and  136  are connected to a source of a high reference potential VDD. The gate of transistor  132  is connected to the drain of transistor  136  and the gate of transistor  136  is connected to the drain of transistor  132 . Preferably, the gate width of transistor  134  is larger than the gate width of transistor  130 . As an example, the gate width of transistor  134  is equal to twice the gate width of transistor  130 . 
         [0105]    Detection circuit  116  comprises, between node P and ground GND, a switch  138  controlled by binary signal SET_ACT. Switch  138  may correspond to an N-channel MOS transistor having its source connected to ground GND, having its drain connected to node P, and having its gate receiving signal SET_ACT. Detection circuit  116  further comprises, between node O and ground GND, a switch  140  controlled by a binary signal ENb. Switch  140  may correspond to an N-channel MOS transistor having its source connected to ground GND, having its drain connected to node O, and having its gate receiving signal ENb. The gate width of transistor  140  may be equal to the sum of the gate width of transistor  134  and of the gate width of transistor  130 . 
         [0106]    Logic circuit  118  comprises a block  142  carrying out the “OR” logic function, receiving signals V COMP  and SET_ACT and delivering a binary signal EN. Logic circuit  118  further comprises a block  144  carrying out the “NO” logic function, receiving signal EN and delivering signal ENb. Logic circuit  118  may further comprise a level conversion circuit  146  receiving signal EN and delivering signal EN_set_H. The high state of signal EN_set_H is at a voltage greater than the high state of signal EN and is capable of controlling certain MOS transistors. As an example, the high state of signal EN_set_H corresponds to VProg. As a variation, circuit  146  may be absent. 
         [0107]    According to an embodiment, device  110  may further comprise a voltage converter receiving signal SET_ACT and having its output connected to the gate of transistor  138  and to the gate of transistor  122 . 
         [0108]    Write device  110  operates as follows. Before the beginning of a write operation, signal SET_ACT is at “1”. Transistor  138  is thus conductive, which maintains voltage V COMP  at “0”. Further, transistor  122  is off. No current flows through resistor R LRS . Signal EN is at “1” and signal ENb is at “0”. Transistor  140  is thus off. Signal EN_set_H is at “1”. Transistor  124  is thus off. No current flows through resistive element R. 
         [0109]    At the beginning of a write operation, signal SET_ACT is set to “0”. Transistor  122  thus becomes conductive. Since signal V COMP  is at “0”, signal EN switches to “0” and signal ENb switches to “1”. Transistor  140  thus becomes conductive. Signal EN_set_H switches to “0”. Transistor  124  thus becomes conductive. Circuit  120  supplying programming voltage VProg causes the flowing of a current I LRS  through resistor R LRS . Current I LRS  is copied by the current mirror and flows through resistive element R. Since the resistance of resistive element R can be assumed to be equal to Roff, that is, greater than R LRS , voltage U NVM  across resistive element R is greater than voltage U LRS  across resistor R LRS . Since the drain-source voltages of transistors  122  and  124  are identical and substantially zero, voltage V R  is smaller than voltage V SET . Transistor  130  is thus more conductive than transistor  134 . Signal V COMP  remains at “0”, transistor  136  being conductive and transistor  132  being off. 
         [0110]    When resistive element R switches, the resistance of resistive element R decreases. When the resistance of resistive element R becomes substantially equal to R LRS , voltage U NVM  becomes substantially equal to voltage U LRS  and voltage V R  becomes substantially equal to V SET . Since the gate width of transistor  134  is greater than the gate width of transistor  130 , transistor  134  is more conductive than transistor  130 . This causes a switching of V COMP  from “0” to “1”, transistor  132  becoming conductive and transistor  136  turning off. Signal EN, and thus signal EN_set_H, then switch from “0” to “1”. Transistor  124  is turned off, interrupting the current flow in resistive element R. Further, signal ENb switches from “1” to “0”, thus turning off transistor  140 . 
         [0111]    According to another embodiment, the gate width of transistor  134  may not be larger than the gate width of transistor  130 . In this case, reference resistance R LRS  is greater than the desired resistance Ron. When resistive element R switches, the resistance of resistive element R decreases from Roff to Ron. When the resistance of resistive element R becomes smaller than resistance R LRS , voltage U NVM  becomes smaller than voltage U LRS  and voltage V R  becomes greater than V SET . Transistor  134  is more conductive than transistor  130 . This causes a switching of V COMP  from “0” to “1”. 
         [0112]    For each memory cell, the current flowing through the memory cell is interrupted as soon as the memory cell has switched. The memory cell lifetime is advantageously preserved since the memory cell is not submitted longer than necessary to the voltage and to the current enabling it to switch. Further, the memory cell power consumption during a write operation is decreased. Further, in the present embodiment, the current flow in resistive element R is interrupted after the resistance of resistive element R has reached a determined value for which signal V COMP  switches from “0” to “1”. The resistance of resistive element R after the switching is thus controlled. 
         [0113]      FIG. 12  shows an embodiment of a device  150  for deleting from a resistive element R. 
         [0114]    Delete device  150  comprises a programming circuit  152 , a circuit for detecting the end of a delete operation  154 , and a logic feedback circuit  156 . Detection circuit  154  may be identical to previously-described circuit  116 , with the difference that signal SET_ACT is replaced with a binary signal RST_ACT. Logic circuit  156  may be identical to previously-described logic circuit  118 , with the difference that signal SET_ACT is replaced with a binary signal RST_ACT and in that signal EN_set_H is replaced with a binary signal EN_rst_H. 
         [0115]    Programming circuit  152  comprises certain elements of previously-described programming circuit  114 . Programming circuit  152  comprises, in particular, circuit  120  for supplying voltage VProg to node T. Programming circuit  152  comprises a switch  158  controlled by binary signal EN_rst_H between node T and node Z. Switch  158  may correspond to a P-channel MOS transistor having its source connected to node T, having its drain connected to node Z, and having its gate receiving signal EN_rst_H. 
         [0116]    Programming circuit  152  comprises an N-channel MOS transistor  160  having its drain connected to node L, having its source connected to ground GND, and having its gate connected to the gate of MOS transistor  126 . Call V R ′ the voltage between node L and ground GND. 
         [0117]    Programming circuit  152  further comprises a reference resistor R HRS  between nodes Q and V and a switch  162  controlled by binary signal RST_ACT between node T and node Q. Switch  162  may correspond to a P-channel MOS transistor having its source connected to node T, having its drain connected to node Q, and having its gate receiving signal RST_ACT. In the present embodiment, resistance R HRS  is substantially equal to resistance Roff desired for resistive element R. Resistor R HRS  may be formed by a polysilicon track. Call U HRS  the voltage across resistor R HRS  and V RST  the voltage between node V and ground GND. Programming circuit  152  further comprises an N-channel MOS transistor  164  having its drain connected to node V, having its source connected to ground GND, and having its gate connected to the gate of transistor  126 . Node V is connected to the gate of transistor  134  and node L is connected to the gate of transistor  130 . 
         [0118]    The gate width of transistor  160  may be larger than the gate width of transistor  126 . 
         [0119]    Delete device  150  operates as follows. Before the beginning of a delete operation, signal RST_ACT is at “1”. Transistor  138  is thus conductive, which maintains signal V COMP  at “0”. Further, transistors  122  and  162  are off. No current flows through resistors R LRS  and R HRS . Signal EN is at “1” and signal ENb is at “0”. Transistor  140  is thus off. Signal EN_rst_H is at “1”. Transistor  158  is thus off. No current flows through resistive element R. 
         [0120]    At the beginning of a delete operation, signal RST_ACT is set to “0”. Transistors  122  and  162  thus become conductive. Since signal V COMP  is at “0”, signal EN switches to “0” and signal ENb switches to “1”. Transistor  140  thus becomes conductive. Signal EN_rst_H switches to “0”. Transistor  158  thus turns on. Circuit  120  supplies programming voltage VProg. It results in the flowing of a current I LRS  through resistor R LRS . Current I LRS , copied by the current mirror, possibly with a multiplication factor greater than 1, flows through resistor element R and through resistor R HRS . Since the resistance of resistive element is of low level, voltage U NVM  across resistive element R is smaller than voltage U HRS  across resistor R HRS  and voltage V R ′ is greater than voltage V RST . Transistor  130  is thus more conductive than transistor  134 . Signal V COMP  thus remains at “0”, transistor  136  being conductive and transistor  132  being off. 
         [0121]    When resistive element R switches, the resistance of resistive element R increases. When voltage U NVM  becomes substantially equal to voltage U HRS , voltage V R ′ becomes substantially equal to V RST . Since the gate width of transistor  134  is larger than the gate width of transistor  130 , transistor  134  is more conductive than transistor  130 . This causes a switching of V COMP  from state “0” to state “1”, transistor  132  becoming conductive and transistor  136  turning off. Signal EN and signal EN_rst_H then switch from “0” to “1”. Transistor  158  is then turned off, interrupting the current flow in resistive element R. Further, signal ENb switches from “1” to “0”, thus turning off transistor  140 . 
         [0122]    According to another embodiment, the gate width of transistor  134  may not be larger than the gate width of transistor  130 . In this case, reference resistance R HRS  is smaller than the desired resistance Roff. When resistive element R switches, the resistance of resistive element R increases from Ron to Roff. When the resistance of resistive element R becomes greater than resistance R HRS , voltage U NVM  becomes greater than voltage U HRS  and voltage V R , becomes smaller than V RST . Transistor  134  is more conductive than transistor  130 . This causes a switching of V COMP  from “0” to “1”. 
         [0123]    For each memory cell, the current flowing through the memory cell is interrupted as soon as the memory cell has switched. The memory cell lifetime is advantageously preserved since the memory cell is not submitted longer than necessary to the voltage and to the current enabling it to switch. Further, the memory cell power consumption during a delete operation is decreased. Further, in the present embodiment, the current flow in resistive element R is interrupted after the resistance of resistive element R reaches a determined value for which signal V COMP  switches from “0” to “1”. The resistance of resistive element R after the switching is thus controlled. 
         [0124]      FIG. 13  shows another embodiment of a device  170  for deleting from a resistive element R. 
         [0125]    Delete device  170  comprises a programming circuit  172 , a circuit for detecting the end of a delete operation  174 , and a logic feedback circuit  176 . Programming circuit  172  comprises transistors  122  and  126  and resistor R LRS  of circuit  114  previously described in relation with  FIG. 11 . Programming circuit  172  further comprises transistor  158  of circuit  152  previously described in relation with  FIG. 12 . Resistive element R is connected in the same way as for circuit  152 . Programming circuit  172  further comprises an N-channel MOS transistor  178  having its source connected to ground GND, having its gate connected to the gate of transistor  126 , and having its drain connected to node L. The gate width of transistor  178  may be larger, for example, by a factor n greater than 1, than the gate width of transistor  126 . Logic circuit  176  may comprise previously-described logic block  142  and level conversion circuit  146  of logic circuit  156 . 
         [0126]    Detection circuit  174  comprises a P-channel MOS transistor  180  having its source connected to the source of reference potential VDD, having its gate connected to node K and receiving voltage V SET , and having its drain connected to a node X. Detection circuit  174  comprises an N-channel MOS transistor  182  having its source connected to ground GND, having its gate connected to node L and receiving voltage V R ′, and having its drain connected to node. Node X delivers signal V COMP  received by “OR” logic gate  142 . Detection circuit  174  comprises an N-channel MOS transistor  184  having its source connected to ground GND, having its gate receiving signal RST_ACT, and having its drain connected to node X. 
         [0127]    Delete device  170  operates as follows. Before the beginning of a delete operation, signal RST_ACT is at “1”. Transistor  122  is thus off. No current flows through resistor R LRS . Transistor  184  is conductive and signal V COMP  is at “0”. Signal EN is at “1” and signal EN_rst_H is at “1”. Transistor  158  is thus off. No current flows through resistive element R. 
         [0128]    At the beginning of a delete operation, signal RST_ACT is set to “0”. Transistor  122  thus becomes conductive and transistor  184  is turned off. Since signal V COMP  is at “0”, signal EN and signal EN_rst_H switch to “0”. Transistor  158  thus becomes conductive. Circuit  120  supplies programming voltage VProg. It results in the flowing of a current I LRS  through resistor R LRS . Current I LRS  is copied by the current mirror and flows through resistive element R multiplied by multiplication factor n. Since the resistance of resistive element R initially has value Ron, voltage U NVM  across resistive element R is in the order of n times voltage U LRS  across resistor R LRS . Transistors  180  and  182  are sized so that in this configuration, transistor  182  is more conductive than transistor  180 . Signal V COMP  thus remains at “0”. 
         [0129]    When resistive element R switches, the resistance of resistive element R increases from Ron to Roff. Voltage U NVM  increases and signal V R ′ decreases. Transistor  180  is more conductive than transistor  182 . This causes a switching of V COMP  from “0” to “1”. Signal EN and signal EN_rst_H then switch from “0” to “1”. Transistor  158  is then turned off, interrupting the current flow through resistive element R and thus the delete operation. 
         [0130]    For each memory cell, the current flowing through the memory cell is interrupted as soon as the memory cell has switched. The memory cell lifetime is advantageously preserved since the memory cell is not submitted longer than necessary to the voltage and to the current enabling it to switch. Further, the memory cell power consumption during a delete operation is decreased. Further, in the present embodiment, the current flow through resistive element R is interrupted after the resistance of resistive element R has reached a determined resistance value for which signal V COMP  switches from “0” to “1”. The resistance of resistive element R after the switching is thus controlled. 
         [0131]      FIG. 14  shows an embodiment of a memory  190  comprising a write device having an operation which may be similar to what has previously described for write device  110  shown in  FIG. 11 . Memory  190  comprises an array of resistive elements R i,j  arranged in N rows and M columns, where i varies from 1 to N and j varies from 1 to M.  FIG. 14  shows the resistive elements of the first row and of the last row for column “j”. Further, the elements of memory  190  identical to the elements of the write or delete device previously described in relation with  FIGS. 11 to 13  are designated with the same reference numerals, to which an index may be added to indicate that the element is repeated for each row “i” and/or for each column “j”. 
         [0132]    As an example, two resistive elements R 1,j  and R N,j  of column j are shown in  FIG. 14 . Each resistive element R i,j  comprises a first terminal (+) and a second terminal (−). Terminal (+) is connected to the source of a P-channel MOS transistor  192   i,j . For each row “i”, the gate of each transistor  192   i,j  in the row is connected to a word line WL i . For each column “j”, the source of each transistor  192   i,j  in the column is connected to a first bit line BL 1   j  and terminal (−) of each resistive element R i,j  in the column is connected to a second bit line BL 2   j . Bit line BL 1   j  is connected to the drain of transistor  124   j  and to the drain of transistor  160   j . Bit line BL 2   j  is connected to the drain of transistor  158   j  and to the drain of transistor  128   j . 
         [0133]    Memory  190  comprises a circuit for detecting the end of a write and/or delete operation SA j  which is connected to bit lines BL 1   j  and BL 2   j  and to the gate of transistor  126 . The operation of circuit SA j  may be similar to that of previously described circuit  116  or  174  for detecting the end of a write operation. Memory  190  comprises a logic circuit Logic j  which is connected to circuit SA j  and which provides signals EN_set_H j  and EN_rst_H j . The operation of circuit Logic j  may be similar to that of previously-described logic circuit  118  or  176 . 
         [0134]    Memory  190  further comprises an N-channel MOS transistor  194   j  having its source connected to ground GND, having its drain connected to the gate of transistor  128   j , and having its gate receiving signal EN_set_H j . Memory  190  further comprises a P-channel MOS transistor  196   j  having its source connected to the gate of transistor  126 , having its drain connected to the gate of transistor  128   j , and having its gate receiving signal EN_set_H j . Memory  190  further comprises an N-channel MOS transistor  198   j  having its source connected to ground GND, having its drain connected to the gate of transistor  160   j , and having its gate receiving signal EN_rst_H j . Memory  190  further comprises a P-channel MOS transistor  200   j  having its source connected to the gate of transistor  126 , having its drain connected to the gate of transistor  160   j , and having its gate receiving signal EN_rst_H j . 
         [0135]    In the embodiment shown in  FIG. 14 , a reference resistor R LRSi  and a P-channel MOS transistor  202   i  are provided for each row “i”. The gate of transistor  202   i  is connected to word line WL i  and the drain of transistor  202   i  is connected to a first terminal of resistor R LRSi . For the first row, the source of transistor  202   1  is connected to the drain of transistor  122 . For the other rows, the source of transistor  202   i  of the row is connected to the source of transistor  202   i−1  of the previous row. For the last row, the second terminal of resistor R LRSN  is connected to the drain of transistor  126 . For the other rows, the second terminal of resistor R LRSi  is connected to the second terminal of resistor R LRSi+1  of the next row.  FIG. 14  shows parasitic resistors  204  which are substantially homogeneously distributed on the conductive tracks connecting switches  202   i . 
         [0136]    Memory  190  operates as follows. The resistive element R i,j  where a write or delete operation should be performed is selected by the grounding of word line WL i  so that transistor  192   i,j  becomes conductive, the other word lines being maintained at high potential VDD. Further, transistor  122  is conductive so that a current flows through the resistor R LRSi  of the same row as the selected resistive element R i,j . 
         [0137]    For an operation of writing into resistive element R i,j  of column “j”, signal EN_set_H j  is set to “0” and signal EN_rst_H j  is set to “1”. Transistor  196   j  is thus conductive and transistor  194   j  is off. A current can thus flow through transistor  128   j . Transistor  198   j  is conductive and transistor  200   j  is off. Transistor  160   j  is thus off and no current can flow therethrough. Thereby, during the write operation, a current successively flows through transistor  124   j , transistor  192   i,j , resistive element R i,j , from terminal (+) to terminal (−), and through transistor  128   j . The current path is shown by a stripe-dot line  206 . 
         [0138]    For an operation of deleting resistive element R i,j  of column “j”, signal EN_set_H j  is set to “1” and signal EN_rst_H j  is set to “0”. Transistor  200   j  is thus conductive and transistor  198   j  is off. A current can thus flow through transistor  160   j . Transistor  194   j  is conductive and transistor  196   j  is off. Transistor  128   j  is thus off and no current can flow therethrough. Thereby, during the delete operation, a current successively flows through transistor  158   j , through resistive element R i,j , from terminal (−) to terminal (+), through transistor  192   i,j , and through transistor  160   j . The current path is shown by a dotted line  208 . 
         [0139]    The arrangement of resistors R LRSi  results in that the parasitic resistances seen by current I LRS  flowing through resistor R LRSi  are substantially the same whatever the selected resistive element R i,j . 
         [0140]      FIG. 15  shows another embodiment of a memory  210 . Memory  210  comprises all the elements of memory  190 , with the difference that a single resistor R LRS  is present and is used whatever the selected resistive element R i,j . There thus advantageously is a surface area gain with respect to memory  190  and less variability on current I LRS  since the same resistor R LRS  is used. Further, the parasitic resistances seen by current I LRS  crossing resistor R LRS  are substantially the same whatever the selected resistive element R i,j . 
         [0141]      FIG. 16  shows another embodiment of a memory  220 . Memory  220  comprises all the elements of memory  190  with the difference that transistors  194   j ,  196   j ,  198   j , and  200   j  are not present. Memory  220  comprises an N-channel MOS transistor  222   j  having its source connected to the drain of transistor  128   j  and to circuit SA j , having its drain connected to line BL 2   j , and having its gate receiving signal EN_rst_H j . Memory  220  comprises an N-channel MOS transistor  224   j  having its source connected to the drain of transistor  160   j  and to circuit SA j , having its drain connected to line BL 1   j , and having its gate receiving signal EN_set_H j . Memory  220  further comprises an N-channel MOS transistor  226  having its source connected to the drain of transistor  126 , having its drain connected to a terminal of each resistor R LRSi , and having its gate connected to the drain of transistor  122 . 
         [0142]    For an operation of writing into resistive element R i,j  of column “j”, signal EN_set_H j  is set to “0” and signal EN_rst_H j  is set to “1”. Transistor  222   j  is thus conductive and transistor  224   j  is off. Thereby, the current flows as shown by stripe-dot line  206 . For an operation of deleting from resistive element R i,j  of column “j”, signal EN_set_H j  is set to “1” and signal EN_rst_H j  is set to “0”. Transistor  224   j  is thus conductive and transistor  222   j  is off. Thereby, the current flows as shown by dotted line  208 . 
         [0143]    In the embodiment shown in  FIG. 16 , memory  220  advantageously has a simplified structure with a decreased number of transistors with respect to memory  190 . 
         [0144]      FIG. 17  shows another embodiment of a memory  230  where delete device  170  previously described in relation with  FIG. 13  may be used. Memory  230  has the same structure as memory  210  shown in  FIG. 15 . Memory  230  further comprises, of each row, a P-channel MOS transistor  232   i  having its gate connected to word line WL i . For the first row, the source of transistor  232   1  is connected to the drain of transistor  158 . For the other rows, the source of transistor  232   i  of the row is connected to the source of transistor  232   i−1  of the previous row. For the last row, the drain of transistor  232   N  is connected to a terminal of resistor R HRS . For the other rows, the drain of transistor  232   i  of the row is connected to the drain of transistor  232   i+1  of the next row.  FIG. 17  shows parasitic resistors  234  which are substantially homogeneously distributed on the conductive tracks connecting switches  232   i . Of course, a resistor R HRS  may be provided for each row similarly to what has been described for resistors R LRSi  in  FIG. 16 . Detection circuit SA j  is further connected to the drain of transistor  164 . The operation of circuit SA j  may be similar to that of previously described circuit  156  for detecting the end of a write operation. 
         [0145]      FIG. 18  shows a more detailed embodiment of a write and delete device  240  capable of being used with memory  230  of  FIG. 17 . The elements common with write device  110  shown in  FIG. 11  and delete device  150  shown in  FIG. 12  are designated with the same reference numerals, to which an index may be added to indicate that the element is repeated for each row “i” and/or for each column “j”. 
         [0146]    The gate of transistor  122  receives a signal ACT and the gate of transistor  162  receives signal RST_ACT. 
         [0147]    Circuit SA j  for detecting the end of a write and/or delete operation comprises all the elements of circuit  154 , with the difference that transistor  140  is replaced with two N-channel MOS transistors  242   j ,  244   j . The drain of transistor  242   j  is connected to the source of transistor  130   j . The source of transistor  242   j  is connected to ground GND and the gate of transistor  242   j  receives signal ENb j . The drain of transistor  244   j  is connected to the source of transistor  134   j . The source of transistor  244   j  is connected to ground GND and the gate of transistor  244   j  receives high reference potential VDD. Transistor  244   j  is thus conductive. 
         [0148]    Circuit SA j  further comprises an N-channel MOS transistor  246   j  having its drain receiving signal V Rj ′ and having its gate receiving signal EN_rst_Hb j . Circuit SA j  further comprises an N-channel MOS transistor  248   j  having its drain receiving signal V SET  and having its gate receiving signal EN_set Hb j . The sources of transistors  246   j  and  248   j  are connected to the gate of transistor  130   j . Circuit SA j  further comprises an N-channel MOS transistor  250   j  having its drain receiving signal V RST  and having its gate receiving signal EN_rst_Hb j . Circuit SA j  further comprises an N-channel MOS transistor  252   j  having its drain receiving signal V Rj  and having its gate receiving signal EN_set_Hb j . The sources of transistors  250   j  and  252   j  are connected to the gate of transistor  134   j . 
         [0149]    The control of the write and read operations is performed by binary signals SET_ACT and RST_ACT. Logic circuit Logic j  comprises four logic blocks  254   j ,  256   j ,  258   j , and  260   j . Block  254   j  carries out the “OR” logic function and receives signals SET_ACT and V COMPj . Block  256   j  carries out the “OR” logic function and receives signals RST_ACT and V COMPj . Block  258   j  carries out the “NAND” logic function, receives the outputs of blocks  254   j  and  256   j , and outputs signal ENb j . Block  260   j  carries out the “AND” logic function, receives signals SET_ACT and RST_ACT, and outputs signal ACT. 
         [0150]    Logic circuit Logic j  comprises a level conversion circuit  262   j  receiving the output of block  254   j . The output of level conversion circuit  262   j  drives an inverter  264   j  which outputs signal EN_set_Hb j . Signal EN_set_Hb j  drives an inverter  266   j  which outputs signal EN_set_H j . Logic circuit Logic j  comprises a level conversion circuit  268   j  receiving the output of block  256   j . The output of level conversion circuit  268   j  drives an inverter  270   j  which outputs signal EN_rst_Hb j . Signal EN_rst_Hb j  drives an inverter  272   j  which outputs signal EN_rst_H j . 
         [0151]    Signals SET_ACT and RST_ACT are at “1” by default. Signal ACT thus is at “1”. Transistor  138  is thus conductive, which maintains signal V COMPj  at “0”. Further, transistors  122 ,  162  are off. No current flows through resistors R LRS  and R HRS . Signal ENb j  is at “0”. Transistor  242   j  is thus off. Signals EN_set_Hb j  and EN_rst_Hb j  are at “0”. Transistors  246   j ,  248   j ,  250   j , and  252   j  are thus off. Signals EN_set_H j  and EN_rst_H j  are at “1”, transistors  124   j  and  158   j  are thus off. No current flows through resistive element R i,j . Signals SET_ACT and RST_ACT are identical for all the columns in the array. 
         [0152]    To perform an operation of writing into resistive element R i,j  of column “j”, signal SET_ACT is set to “0”, signal RST_ACT remaining at “1”. Signal ACT thus switches to “0”. Transistor  138   j  is thus turned off and transistor  122  becomes conductive. Further, signal ENb j  switches to “0”. Transistor  242   j  thus turns on. Signal EN_set_H j  switches to “0”. Transistor  124   j  thus becomes conductive. Signal EN_set_Hb j  switches to “1” while signal EN_rst_Hb j  remains at “0”. The gate of transistor  130   j  receives signal V SET  and the gate of transistor  134   j  receives signal V Rj . Circuit SA j  then operates like end-of-writing detection circuit  116  previously-described in relation with  FIG. 11 . 
         [0153]    To perform an operation of deleting from resistive element R i,j  of column “j”, signal RST_ACT is set to “0”, signal SET_ACT remaining at “1”. Signal ACT thus switches to “0”. Transistor  138   j  is thus turned off and transistor  122  becomes conductive. Further, signal ENb j  switches to “0”. Transistor  242   j  thus turns on. Signal EN_rst_Hj switches to “0”. Transistor  124   j  thus becomes conductive. Signal EN_rst_Hb j  switches to “1” while signal EN_set_Hb j  remains at “0”. The gate of transistor  130   j  receives signal V Rj ′ and the gate of transistor  134   j  receives signal V RST . Circuit SA j  then operates like end-of-deleting detection circuit  154  previously-described in relation with  FIG. 12 . 
         [0154]      FIG. 19  shows another embodiment of a memory  270 . The elements common with memory  5  shown in  FIG. 1  are designated with the same reference numerals. 
         [0155]    Memory  270  especially comprises memory cells Cell i,j  distributed in rows and in columns. Each bit line BL j , with j varying from 1 to M, is connected via switch  20   j  to an additional word line DWL. One end of additional word line DWL is connected to a delete and/or write device  272 . As an example, each memory cell Cell i  comprises a reference resistive element R i,j  in series with a non-linear component, for example, a diode D i,j . Memory  270  further comprises an additional column of reference cells DCell i , with i varying from 1 to N. As an example, each reference cell DCell i  may have a structure similar to that of memory cell Cell i,j  and comprise a reference element DR i  in series with a non-linear component, for example, a diode DD i . Each reference cell DCell i  comprises a first terminal connected to a word line WL i  and a second terminal connected to an additional bit lines DBL. Additional bit line DBL is connected to delete and/or write device  272  via a switch DT controlled by bit line selection unit  22 . Switch DT for example corresponds to a MOS transistor, for example, with a P channel, having its drain connected to reference bit line DBL, having its source connected to a node A′, and having its gate controlled by unit  22 . 
         [0156]    As an example, device  272  may operate similarly to delete device  14  previously described in relation with  FIG. 1 , circuit  32  being then replaced with additional bit line DBL and reference cells DCell i . According to another example, device  272  may operate similarly to end-of-writing detection circuit SA j  and logic feedback circuit Logic j  previously described in relation with  FIG. 14 . As an example, to carry out an operation of writing into and/or deleting memory cell Cell i,j , device  272  is capable of: 
         [0157]    circulating current through reference cell DCell i  and through memory cell Cell i,j ; 
         [0158]    detecting the switching of the resistance of memory cell Cell i,j , for example, by comparing voltages representative of the voltage across reference cell DCell i  and of the voltage across memory cell Cell i,j ; and 
         [0159]    interrupting the current flowing through memory cell Cell i,j  on detection of the switching. 
         [0160]    During the write and/or delete operation, current flows through the selected memory cell Cell i,j , through the portion of word line WL i  between switch  16   i  and memory cell Cell i,j , the portion of bit line BL j  between memory cell Cell i,j  and switch  20   j , and the portion of the additional bit line between switch  20   j  and device  272 . Further, current flows through reference cell DCell i,  through the portion of word line WL i  between switch  16   i  and reference cell DCell i  and the portion of additional bit line DBL between reference cell DCell i  and switch DT which is directly connected to device  272 . Thereby, the parasitic resistances seen by the current flowing through memory cell Cell i,j  are substantially the same as the parasitic resistances seen by the current flowing through reference cell DCell i . 
         [0161]      FIG. 20  shows another embodiment of a memory  280 . Memory  280  comprises all the elements of memory  270 , with the difference that reference resistive elements DR i  are replaced with a single resistor DR present at the base of additional word line DBL and which is used whatever the selected memory cell Cell i,j . There thus advantageously is a gain in surface area with respect to memory  270  and less current variability since the same resistor DR is used. 
         [0162]      FIG. 21  shows another embodiment of a memory  290 . Memory  290  comprises all the elements of memory  280 , with the difference that certain bit lines BL i  are not connected to additional word line DWL but are connected to a second additional word line DWL′ via switch  20   j . One end of second additional word line DWL′ is connected to a delete and/or write device  292 , for example, identical to device  272 , to which additional bit line DBL is also connected. This embodiment enables to simultaneously write into/delete from memory cells of different columns. Second additional word line DWL′ is arranged so that the parasitic resistances seen by the current flowing through the memory cell Cell i,j  connected to device  292  are substantially the same as the parasitic resistances seen by the current flowing through resistor DR connected to device  292 . 
         [0163]    Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the N-channel MOS transistors may be replaced with P-channel MOS transistors and the P-channel MOS transistors may be replaced with N-channel MOS transistors by adapting the control signals of these transistors. 
         [0164]    Further, although the previously-described embodiments relate to bipolar memory cells for which the polarity of the voltage applied across the memory cell is inverted between a write operation and a delete operation, it should be clear that these embodiments may be adapted to unipolar memory cells for which the polarity of the voltage applied across the memory cell is the same for a write operation and a delete operation, only the amplitude range of the applied voltage being different between a write operation and a delete operation. 
         [0165]    Further, although in the embodiments previously described in relation with  FIGS. 11 to 18 , each memory cell comprises a resistive element series-connected with a switch, particularly a MOS transistor, these embodiments may be implemented with other types of memory cells. As an example, each memory cell may comprise a diode series-connected with the resistive element.