Abstract:
In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     This invention relates to semiconductor devices and more particular to electrostatic discharge devices with a guard ring structure to block high energy current from the internal circuits. 
     2. Description of the Related Art 
     An ESD (electrostatic discharge) device or circuit is used to protect internal circuitry on a semiconductor chip. The ESD devices and circuits are connected to each chip I/O (input/output) and power pad. When an electrostatic discharge external to the chip enters a chip pad, the ESD devices and circuits absorb the resulting high current and protect the internal chip circuitry form damage. The ESD circuits are comprised of diodes and bipolar and MOS devices, and the ESD devices or circuits are usually located near the chip pad to which they are connected. 
     In U.S. Pat. No. 5,912,494 (Yu) an ESD structure is described in which a heavily doped polycrystalline region is deposited on the surface of a semiconductor substrate. The polycrystalline region is used to create a lightly doped region to be formed which in turn increases the turn on voltage of a parasitic bipolar transistor. The parasitic transistor is prevented from turning on during an ESD event, allowing an ESD device to protect the internal circuits of the chip. In U.S. Pat. No. 5,438,005 (Jang) a CMOS device is provided with a deep collector guard ring which provide immunity to latch-up of the CMOS device. In U.S. Pat. No. 5,223,737 (Canclini) An ESD circuit is created with a deep N-well which forms a bipolar transistor with a resistor and zener diode to form ESD protection to internal circuits from electrostatic discharge entering a chip pad. 
     An ESD device or circuit is necessary for each chip bond pad to prevent damage or latch-up during an electrostatic discharge or applied voltage overshoot and voltage undershoot. When an electrostatic discharge enters a bond pad, the ESD device will attempt to absorb the resulting high current so that the internal circuits are not affected. Usually the ESD device or circuit is surrounded by either a N+, a P+, or both guard rings. These guard rings are used to prevent damage from voltage latch-up resulting from ESD and voltage overshooting or undershooting. Absorption of high current by the guard rings from an ESD or a voltage overshoot or undershoot helps prevent damage of the ESD device from overheating and resists current further flow to the internal circuits of the semiconductor chip. The effectiveness of the guard rings depend on the depth to which the guard rings are produced to block and absorb unwanted currents. 
     SUMMARY OF THE INVENTION 
     In this invention a P+ guard ring and an N+ guard ring surround the area of an ESD device or circuit. The ESD device or circuit is close to a chip bond pad and is electrically connected to the bond pad. Each bond pad has a similar arrangement for protection from an electrostatic discharge and voltage overshoot and undershoot. On a P-substrate the P+ guard ring is closest to the area containing the ESD device or circuit and surrounds that area. Surrounding and separated from the P+ guard ring is an N+ guard ring. The N+ guard ring is formed within an N-well which rests on top of a deep N-well. 
     The vertical structure comprising a deep N-well, an N-well sitting on top of the deep N-well and a N+ guard ring within the N-well creates a tall fence for high current from an electrostatic discharge or a voltage overshoot, absorbing unwanted current and preventing damage from heating or circuit latch-up. The P+ guard ring which resides inside and separated from the N+ guard ring is used to absorb current from electrostatic discharge or a voltage overshoot of opposite polarity from the current absorbed by the N+ Guard ring. The P+ guard ring can be created inside of a P-well 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This invention will be described with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block diagram of the connection of an ESD device to a chip bond pad, 
     FIG. 2 is a plan view of prior art of an ESD device or circuit with guard rings of, 
     FIG. 3 is a cross section view of prior art of an ESD device with guard rings. 
     FIG. 4 is a cross section view of prior art of an ESD device with an N+ guard ring within an N-well, 
     FIG. 5 a  is a plan view of the ESD device and guard rings of this invention, and 
     FIG. 5 b  is a cross section view of the ESD device and guard rings of this invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Shown in FIG. 1 is a block diagram of the connection of an ESD device  11  between the chip bond pad  10  and the internal chip circuitry  12 . Every chip pad  10  is associated with an ESD device  11 . The ESD device  11  could be an ESD circuit made of various configurations of diodes transistors and resistors. The ESD device  11  is physically placed close to the bond pad  10  to minimize the impedance to the electrostatic discharge or voltage overshoot and undershoot. The ESD device or circuit absorbs the excess current resulting from an electrostatic discharge or a voltage overshoot/undershoot, and thus protecting the internal circuitry from damage or latch-up. 
     In FIG. 2 is shown a plan view of prior art of an ESD device or circuit  15  surrounded by a P+ guard ring  16  which is surrounded by a N+ guard ring  17 . The two guard rings  16   17  are separated from each other, and each is intended to absorb current of different polarities. In FIG. 3 is show a cross section view of the ESD device  15 , P+ guard ring  16  and N+ guard ring  17  of prior art on a P-substrate  20  shown in a plan view in FIG.  2 . The depth of the P+ and N+ diffusions that form guard rings  16  and  17  provide some protection to the excess current flow caused by and ESD event or a voltage overshoot/undershoot; however, higher energy currents can go under the guard rings  16   17  and be absorbed by the internal circuitry  18 . In FIG. 4 is shown another ESD and guard ring configuration of prior art on a P-substrate  20 . An ESD device or circuit  15  is surrounded by a P+ guard ring  16  within an N+ guard ring  17 . The N+ guard ring  17  is implanted within an N-well  19 . The added depth of the N-well  19  helps to further reduces excess current flow from an ESD event or a voltage overshoot/undershoot to the internal circuit  18 . 
     In FIG. 5 a  is shown the plan view of an ESD device or circuit  30  and the associated guard rings of this invention An ESD device or circuit  30  is surrounded by a P+ guard ring  31 . Surrounding the P+ guard ring  31  is an N+ guard ring  32 . The N+ guard ring  32  sits in an N-well  34  shown in FIG. 5 b  and on top of a deep N-well shown as dashed lines  33  in FIG. 5 a.  The P+ guard ring  31  is separated from the ESD device  30  and the N+ guard ring  32  is separated from the P+ guard ring  31 . Although not shown, the P+ guard ring could be diffused into a P-well. The shape of the guard rings  31 ,  32  is shown as a square or rectangular shape, but any appropriate shape can be used including the N-well  34  and the deep N-well  35 . 
     In FIG. 5 b  is shown a cross section view of the ESD device  30 , or circuit, and the P+  31  and N+  32  guard rings. The N+ guard ring  32  is diffused into an N-well  34  which rests on top of a deep N-well  35 . The vertical structure of the N+ diffusion  32 , the N-well  34  and the deep N-well  35  extends deep into the P-substrate  36  and provides additional protection to the internal circuitry  37  from an ESD event and voltage overshoot. The N+ guard ring  32  is connected to Vdd  38 , and the P+ guard ring  31  is connected to Vss  39 , or circuit ground. 
     Continuing to refer to FIG. 5 b,  the P+ diffusion  31  is formed with a boron dopant having an implant dosage of approximately about 1E14 to 1E16 ions per square centimeter using an implant energy of approximately about 20 KeV to 100 KeV. A P-well, not shown, in which the P+ diffusion  31  could be implanted, would be formed with a boron dopant to a depth of approximately about 1 to 2 micrometers with an implant dosage of approximately about 2E12 to 1E13 ions per square centimeter using an implant energy of approximately about 100 KeV to 1 MeV and being annealed for approximately about 60 to 180 minutes at a temperature of about 900 to 1150 degrees centigrade. 
     Continuing to refer to FIG. 5 b,  the N+ diffusion  32  is formed from a dopant of arsenic or phosphorus with an implant dosage of approximately about 1E14 to 1E16 ions per square centimeter and having an implant energy of approximately about 20 KeV to 100 KeV. The N-well  34  is formed to depth of approximately about 1 to 2 micrometers from a dopant of arsenic or phosphorus with an implant dosage of approximately about 2E12 to 1E13 ions per square centimeter having an implant energy of approximately about 100 KeV to 1 MeV and being annealed for approximately about 60 to 180 minutes at a temperature of about 900 to 1150 degrees centigrade. The deep N-well  35  is formed to a depth of approximately about 2 to 3 micrometers at a height of approximately about 2 to 3 micrometers from a dopant of arsenic or phosphorus with an implant dosage of approximately about 1E12 to 1E14 ions per square centimeter at an implant energy of approximately about 800 KeV to 2 MeV and being annealed for approximately about 60 to 180 minutes at a temperature of approximately about 900 to 1150 degrees centigrade. 
     In FIG. 6 is shown the method of forming the ESD device, or circuit, with P+ and N+ guard rings including a deep N-well and an N-well associated with the N+ guard ring. A deep N-well  35  is formed on a P-substrate surrounding an area for an ESD device, or circuit, and for a P+ guard ring  50 . The deep N-well  35  is formed to a depth of approximately about 2 to 3 micrometers at a height of approximately about 2 to 3 micrometers from a dopant of arsenic or phosphorus with an implant dosage of approximately about 1E12 to 1E14 ions per square centimeter at an implant energy of approximately about 800 KeV to 2 MeV and being annealed for approximately about 60 to 180 minutes at a temperature of approximately about 900 to 1150 degrees centigrade. Next an N-well  34  is formed on top of the deep N-well  35  and surrounding the area for the ESD device or circuit and for the P+ guard ring  51 . The N-well  34  is formed to depth of approximately about 1 to 2 micrometers from a dopant of arsenic or phosphorus with an implant dosage of approximately about 2E12 to 1E13 ions per square centimeter having an implant energy of approximately about 100 KeV to 1 MeV and being annealed for approximately about 60 to 180 minutes at a temperature of about 900 to 1150 degrees centigrade. 
     Continuing to refer to FIG. 6, an N+ diffusion  32 , creating an N+ guard ring, is formed inside the N-well  34  and surrounding the area for the ESD device, or circuit, and for the P+ guard ring  52 . The N+ diffusion  32  is formed from a dopant of arsenic or phosphorus with an implant dosage of approximately about 1E14 to 1E16 ions per square centimeter and having an implant energy of approximately about 20 KeV to 100 KeV. A P+ diffusion  31 , creating a P+ guard ring, is formed inside and separated from the N+ guard ring and surrounding the area of the ESD device, or circuit  53 . The P+ diffusion  31  is formed with a boron dopant having an implant dosage of approximately about 1E14 to 1E16 ions per square centimeter using an implant energy of approximately about 20 KeV to 100 KeV. 
     Continuing to refer to FIG. 6, an ESD device or circuit is formed inside the P+ guard ring  31  using various circuit components comprising diodes, resistors, bipolar and MOS transistors  54 . The N+ diffusion which makes up the N+ guard ring is connected to the Vdd semiconductor chip bias, and the P+ diffusion is connected to circuit ground  55 . The P+ diffusion making up the P+ guard ring is used to pick up P-substrate current generated by an ESD event or a voltage overshoot. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.