Abstract:
A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer.

Description:
FIELD 
       [0001]    This disclosure relates generally to the field of field effect transistor (FET) fabrication. 
       DESCRIPTION OF RELATED ART 
       [0002]    A field effect transistor (FET) comprises source/drain regions and a gate region. The gate, source and drain regions may comprise doped silicon (Si), and be contacted by metal silicide contacts, or the source and drain Si can be fully silicided to form a Schottky junction FET . As FETs are made increasingly smaller, the contact resistance of the metal silicide to Si at the source/drain must also be commensurately reduced. One way to reduce the contact resistance is to reduce the Schottky barrier height (SBH) of the respective silicon-metal silicide interfaces. The gate silicon may be fully silicided (FUSI) to eliminate the poly-depletion effect. The workfunction of the FUSI gate needs to be tuned to set an appropriate threshold voltage (V t ) for the FET. 
       SUMMARY 
       [0003]    In one aspect, a method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer. 
         [0004]    In one aspect, a field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer. 
         [0005]    Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0006]    Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
           [0007]      FIG. 1  illustrates an embodiment of a method of fabricating a doped source/drain FET with a FUSI gate and reduced source/drain contact resistance. 
           [0008]      FIG. 2  illustrates an embodiment of gate stack deposition on silicon. 
           [0009]      FIG. 3  illustrates an embodiment of the device of  FIG. 2  after gate stack patterning and spacer formation. 
           [0010]      FIG. 4  illustrates an embodiment of implantation of the device of  FIG. 3 . 
           [0011]      FIG. 5  illustrates an embodiment of the device of  FIG. 4  after activation. 
           [0012]      FIG. 6  illustrates an embodiment of the device of  FIG. 3  after removal of the sacrificial layer. 
           [0013]      FIG. 7  illustrates an embodiment of the device of  FIG. 4  after formation of gate and source/drain silicide. 
           [0014]      FIG. 8  illustrates an embodiment of the device of  FIG. 5  during implantation of the gate and source/drain silicide. 
           [0015]      FIG. 9  illustrates an embodiment of a FET with a FUSI gate and reduced source/drain contact resistance. 
           [0016]      FIG. 10  illustrates an embodiment of a method of fabricating a Schottky source/drain FET with a FUSI gate and reduced source/drain contact resistance. 
           [0017]      FIG. 11  illustrates an embodiment of gate stack deposition on extremely thin silicon on insulator (ETSOI). 
           [0018]      FIG. 12  illustrates an embodiment of the device of  FIG. 11  after gate stack patterning and spacer formation. 
           [0019]      FIG. 13  illustrates an embodiment of the device of  FIG. 12  after removal of the sacrificial layer. 
           [0020]      FIG. 14  illustrates an embodiment of the device of  FIG. 13  after formation of gate and source/drain silicide. 
           [0021]      FIG. 15  illustrates an embodiment of the device of  FIG. 14  during implantation of the gate and source/drain silicide. 
           [0022]      FIG. 16  illustrates an embodiment of a Schottky source/drain FET with a FUSI gate and reduced source/drain contact resistance. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Embodiments of systems and methods for a FET with a fully silicided (FUSI) gate and reduced source/drain contact resistance are provided, with exemplary embodiments being discussed below in detail. The FET gate may comprise silicide; the source/drain regions of the FET may also comprise silicide. The gate and source/drain silicide that are formed simultaneously, and may have approximately equal thickness. After silicide formation, the SBH of the silicon-metal silicide interfaces at the source/drain regions, and the workfunction of the FUSI gate, may be modified by formation of segregated interfacial layers. The segregated interfacial layers may be formed by implanting dopants into the gate and source/drain silicide, followed by a low temperature anneal to diffuse the implanted dopants to the silicide/Si interface at the source/drain, or to the silicide/oxide interface at the gate. 
         [0024]      FIG. 1  illustrates a method of fabricating a FET with a FUSI gate and reduced source/drain contact resistance.  FIG. 1  is discussed with reference to  FIGS. 2-9 . In block  101 , gate stack deposition is performed on silicon  204 , as shown in  FIG. 2 . Gate stack deposition comprises formation of gate oxide layer  203 , polysilicon layer  202 , and sacrificial layer  201 . Sacrificial layer  201  may comprise silicon germanium (SiGe) in some embodiments. The thickness of polysilicon  202  may be less than or equal to the amount of silicon that will be consumed in the silicide process, which is discussed below with respect to block  104 . 
         [0025]    In block  102 , sacrificial layer  201 , polysilicon layer  202 , and gate oxide layer  203  are patterned to form the FET gate stack, and spacers  301 A-B are formed adjacent to the FET gate stack, as shown in  FIG. 3 . Spacers  301 A-B may comprise a nitride in some embodiments. 
         [0026]    In block  103 , implantation  401  of dopants is performed, as is shown in  FIG. 4 . Implantation  401  may comprise shallow implantation of n-type dopants, including but not limited to arsenic or phosphorous, to form an n-FET, or p-type dopants, including but not limited to boron, indium, or aluminum, to form a p-FET. Then, the implanted device  400  is activated to form highly doped source/drain regions  501 A-B in silicon  204 , as shown in  FIG. 5 . Activation may comprise annealing. In block  104 , the sacrificial layer  201  is removed, as shown in  FIG. 6 . The sacrificial layer  201  may be removed using a wet etch in some embodiments. For example, a SiGe sacrificial layer may be etched using a H2O:NH4OH:H2O2=5:1:1 solution at 85° C., which has good selectivity to polysilicon layer  202 . 
         [0027]    In block  105 , the gate and source/drain silicide are formed simultaneously on device  600  of  FIG. 6 . The silicide may be formed by depositing a layer of a metal on device  600  such that the metal layer covers polysilicon layer  202  and the exposed portion of silicon  204 , then annealing device  600  after the metal deposition to cause the metal to react with the silicon to form silicide, and then removing any unreacted metal, resulting in gate silicide  701  and source/drain silicide  702 A-B, as shown in  FIG. 7 . Source/drain silicide  702 A-B are located in high doped source/drain regions  501 A-B. The deposited metal may comprise nickel (Ni) or nickel platinum (NiPt) in some embodiments. The material comprising spacers  301 A-B may be selected such that spacers  301 A-B do not react with the deposited metal. The thickness of the deposited metal may be determined based on the thickness of polysilicon layer  202 , so that all of the polysilicon  202  is converted into gate silicide  701 , resulting in a FUSI gate. In embodiments in which the deposited metal comprises Ni, the ratio of the thickness of polysilicon layer  202  to the thickness of the deposited Ni may be about 1.8 or lower to guarantee formation of a FUSI gate. Therefore, if polysilicon layer  202  is about 18 nm thick, deposition of an Ni layer having a thickness of about 10 nm may allow all of polysilicon  202  to be consumed in the silicide process, resulting in a gate silicide  701  that comprises NiSi having a thickness of about 22 nm. Gate silicide  701  and source/drain silicide regions  702 A-B may have approximately the same thickness. 
         [0028]    In block  106 , gate silicide  701  and source drain silicide  702 A-B are implanted with dopants, as shown in  FIG. 8 . Implantation  801  may comprise shallow implantation of n-type dopants, including but not limited to arsenic or phosphorous, to form an n-FET, or p-type dopants, including but not limited to boron, indium, or aluminum, to form a p-FET. After implantation, low-temperature RTA is performed on device  800  in block  107 , resulting in FET  900  as shown in  FIG. 9 . The RTA acts to drive the dopants implanted in block  106  into the silicide regions  701  and  701 A-B, forming gate interface layer  901  between gate silicide  701  and gate oxide  203 , and source/drain interface layers  902 A-B between source/drain silicide regions  702 A-B and highly doped source/drain regions  501 A-B. Gate interface layer  901  comprises a segregated interfacial layer, and acts set the gate workfunction for FET  900 . Source/drain interface layers  902 A-B comprise segregated interfacial layers, and act to reduce the source/drain contact resistance of FET  900 . 
         [0029]      FIG. 10  illustrates a method of fabricating a Schottky source/drain FET with a FUSI gate and reduced source/drain contact resistance.  FIG. 10  is discussed with reference to  FIGS. 11-16 . In block  1001 , gate stack deposition is performed on extremely thin silicon on insulator (ETSOI), comprising silicon layer  1104  on insulator layer  1105 , as shown in  FIG. 11 . Gate stack deposition comprises formation of gate oxide layer  1103 , polysilicon layer  1102 , and sacrificial layer  1101 . Sacrificial layer  1101  may comprise silicon germanium (SiGe) in some embodiments. The thickness of polysilicon  1102  may be less than or equal to the amount of silicon that will be consumed in the silicide process, which is discussed below with respect to block  1004 . 
         [0030]    In block  1002 , sacrificial layer  1101 , polysilicon layer  1102 , and gate oxide layer  1103  are patterned to form the FET gate stack, and spacers  1201 A-B are formed adjacent to the FET gate stack, as shown in  FIG. 12 . Spacers  1201 A-B may comprise a nitride in some embodiments. In block  1003 , the sacrificial layer  1101  is removed, as shown in  FIG. 13 . The sacrificial layer  1101  may be removed using a wet etch in some embodiments. For example, a SiGe sacrificial layer may be etched using a H2O:NH4OH:H2O2=5:1:1 solution at 85° C., which has good selectivity to polysilicon layer  1102 . 
         [0031]    In block  1004 , the gate and source/drain silicide are formed simultaneously on device  1300  of  FIG. 13 . The silicide may be formed by depositing a layer of a metal on device  1400  such that the metal layer covers polysilicon layer  1102  and the exposed portion of SOI  1104 , then annealing device  1300  after the metal deposition to cause the metal to react with the silicon to form silicide, and then removing any unreacted metal, resulting in gate silicide  1401  and source/drain silicide  1402 A-B, as shown in  FIG. 14 . The deposited metal may comprise nickel (Ni) or nickel platinum (NiPt) in some embodiments. The material comprising spacers  1201 A-B may be selected such that spacers  1201 A-B do not react with the deposited metal. The thickness of the deposited metal may be determined based on the thickness of polysilicon layer  1102 , so that all of the polysilicon  1102  is converted into gate silicide  1401 , resulting in a FUSI gate. In embodiments in which the deposited metal comprises Ni, the ratio of the thickness of polysilicon layer  1102  to the thickness of the deposited Ni may be about 1.8 or lower to guarantee formation of a FUSI gate. Therefore, if polysilicon layer  1102  is about 18 nm thick, deposition of an Ni layer having a thickness of about 10 nm may allow all of polysilicon  1102  to be consumed in the silicide process, resulting in a gate silicide  1401  that comprises NiSi having a thickness of about 22 nm. Gate silicide  1401  and source/drain silicide regions  1402 A-B may have approximately the same thickness. 
         [0032]    In block  1005 , gate silicide  1401  and source drain silicide  1402 A-B are implanted with dopants, as shown in  FIG. 15 . Implantation  1501  may comprise shallow implantation of n-type dopants, including but not limited to arsenic or phosphorous, to form an n-FET, or p-type dopants, including but not limited to boron, indium, or aluminum, to form a p-FET. After implantation, low-temperature RTA is performed on device  1500  in block  1006 , resulting in Schottky source/drain FET  1600  as shown in  FIG. 16 . The RTA acts to drive the dopants implanted in block  1005  into the silicide regions  1401  and  1401 A-B, forming gate interface layer  1601  between gate silicide  1401  and gate oxide  1103 , and source/drain interface layers  1602 A-B between source/drain silicide regions  1402 A-B and SOI  1104 . Gate interface layer  1601  comprises a segregated interfacial layer, and acts set the gate workfunction for FET  1600 . Source/drain interface layers  1602 A-B comprise segregated interfacial layers, and act to reduce the source/drain contact resistance of FET  1600 . FET  1600  comprises a FUSI gate. 
         [0033]    The technical effects and benefits of exemplary embodiments include simultaneous formation of gate and source/ silicide regions, resulting in a FET with a FUSI gate having an appropriate workfunction, and reduced source/drain contact resistance. 
         [0034]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0035]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.