Abstract:
An interface device for exchanging data between a first bus system and a second bus system, wherein an input/output device is connectable to the second bus system and within the input/output device includes an addressable slot and an addressable subslot for output or acceptance of input/output data to optimize the consistent exchange of the data between the bus systems. A data transfer device including a transfer memory is connected via the control device and a list storage device in which a data structure for addressing the data for the input/output device is stored, and wherein the data structure is predetermined for a plurality of subslots in a telegram format of the telegrams of the first bus system.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to an interface device for exchanging data between a first bus system and a second bus system, where an input/output device is connectable to the second bus system and an addressable slot and an addressable subslot is located within the input/output device for outputting or receiving input/output data, and where the interface device comprises a first transceiver device for the data of the first bus system, a second transceiver device for the data of the second bus system, a data transfer to device with a transfer memory, and a control device configured to control the data storage and coordinate write accesses into or at the data transfer device. 
         [0003]    2. Description of the Related Art 
         [0004]    In automation technology, there is particularly an exchange of payload data, i.e., input and output data from components to be automated such as machines, actuator drives or sensors, between input/output devices such as modular decentralized peripheral systems for example and higher-ranking automation devices via field buses. Known examples of field buses are Profibus or Profinet. Within an input/output device of a decentralized peripheral station, payload data can be distributed to individual modules or read out from the individual modules. The field bus and the backplane bus system generally operate asynchronously in relation to one another and an updating of data, for example, of a subslot payload data packet, is also only possible in some cases. As a reusit, a buffer is necessary to ensure data consistency between the two bus systems. 
         [0005]    Such buffers, or also alternating buffers, are known from the European patent application EP 1 253 494 B1. In the known open-loop and/or closed-loop control system where via a field bus a decentralized peripheral is accessed, it is disadvantageous that it can no longer keep pace with the current speed demands made on payload data exchanges. 
       SUMMARY OF THE INVENTION 
       [0006]    It is therefore an object of the invention to provide an interface device exchanging data or a method for consistently exchanging data that is optimized and achieves the previous exchange of data more quickly while consistently data safeguarding the data. 
         [0007]    This and other objects and advantages are achieved in accordance with the invention by providing a control device of an interface which is connected to a list storage device, in which a data structure for addressing the data for the input/output device is stored, where the data structure is predetermined for a plurality of subslots in a telegram format of the telegrams of the first bus system and in each case has a memory offset related to a start address of the transfer memory and a data link of the input/output data, where an index is assigned to the subslots in the data structure, where the control device is further configured, when the input output data is updated, to coordinate with the aid of the index the write accesses into the data transfer device byte-by-byte. The interface device is, for example, implemented in an interface module between a higher-ranking automation device and a subordinate decentralized periphery. In relation to a Profinet application, such a Profinet I/O-system comprises the following devices: an I/O controller, which represents the control unit which handles the automation tasks. An I/O device, which represents a field device, especially an input/output device, which is monitored and controlled by the I/O controller. An I/O device can consist of a number of modules and submodules. An I/O supervisor, which represents a development tool, typically based on a PC, in order to set the parameters for and perform diagnostics for the individual I/O devices and I/O controllers. In relation to the list storage device, the parameterization data of the I/O device, i.e., of the input/output devices, is advantageously used for the byte-by-byte coordination of write accesses in the data transfer device of the interface device. With the list storage device, the interface device now has a reference list available to it which is used for fast addressing of the data in the data transfer device or in the transfer memory. 
         [0008]    Advantageously, the transfer memory is subdivided into an output buffer and an input buffer. In this case, the output buffer is configured to buffer data from the first bus system and to provide the buffered data for the second bus system as output data for the input/output device and the input buffer is configured to buffer data from the second bus system and provide the buffered data for the first bus system as input data of the input/output device. 
         [0009]    Preferably, the transfer memory is comprises a first transfer memory and a second transfer memory, where the transfer memory is connected to the control device such that data can only be stored in or a write access can only be performed to the first transfer memory or to the second transfer memory. In this case, each transfer memory now in its turn has an output buffer and an input buffer, respectively. 
         [0010]    In order to further optimize the data transfer and especially the data consistency, the control device has a blocking device which is configured, before a write access with output data to the output buffer or before a read access of input data to the input buffer, to set a status indicator, where the control device is further configured so that the blocking device blocks a switch between the first and the second transfer memory when the status indicator is set. 
         [0011]    In the byte-by-byte setup of the transfer memory, it has proved to be especially advantageous for the control device to further, for a read access of output data at the output buffer, to interrogate a semaphore and, depending on the status of the semaphore, to either read out the output data from the first transfer buffer or from the second transfer buffer. A semaphore variable is, for example, a data structure that consists of an integer and usage operations, such as “reserve, test” and “release”. It is especially suitable for administration of restricted enumerable resources to which a number of processes or threads are preferably to have access, such as a generator and a load. By contrast with locking variables, the lock, the activity carriers, the “reserve” and “release”, do not need to be identical. 
         [0012]    In order to optimize an updating of data the transfer memory is set up byte-by-byte and each byte is assigned a semaphore with the index, in this case a byte in the first transfer memory is assigned the semaphore with the first state and a corresponding byte in the second transfer memory is assigned the semaphore with the second state, where the second state corresponds to the negated first state. 
         [0013]    So that during ongoing operation of an automation device with a decentralized peripheral, in relation to the issuing of data of the I/O device, for example, when setting up or clearing down additional application relationships (connections) with further Profinet controllers, jumpering becomes possible, the list storage device is specified in duplicate and configured as a first list storage device and a second list storage device. 
         [0014]    With respect to the industrial automation technology already mentioned, an especially advantageous embodiment of the interface device is configured to operate within the network of an industrial automation system, where the first transceiver device is configured for data of the first bus system to send and receive data of a field bus of industrial automation technology and the second transceiver device for data of the second bus system is configured to send and receive data of a backplane bus of the input/output device which comprises a decentralized peripheral of the industrial automation technology, where the control device also includes a backplane controller and a field bus controller. 
         [0015]    The task stated at the outset of optimizing the operation in a decentralized peripheral system is likewise achieved by a method for consistent exchange of data between a first bus system and the second bus system, where an input/output device is connected to the second bus system and within the input/output device a slot and a subslot for output or receipt of input/output data is addressed, where a data transfer device with a transfer memory is controlled by a control device for controlling the data storage and for coordination of write accesses into or at the data transfer device, where the control device evaluates a data structure from a list storage means, where the data structure for addressing the data for the input/output device has been stored before the beginning of the data exchange in the list storage device and the data structure is defined based on a plurality of subslots in a telegram format of the telegrams of the first bus system and in each case has a memory offset related to a start address of the transfer memory and a data length of the input/output data, where an index is assigned to the subslots in the data structure, where the control device, during updating of the input/output data, coordinates the write accesses in the data transmission device with the aid of the index. 
         [0016]    Preferably, the transfer memory is divided into an output buffer and an input buffer, where the output buffer is operated to buffer data from the first bus system and provide the buffered data for the second bus system as output data for an input/output device and the input buffer is operated to buffer data from the second bus system and provide the buffered data for the first bus system as input data of the input/output device. 
         [0017]    The transfer memory is divided into the first transfer memory and a second transfer memory, and the storage of data or a write access are controlled so that there is only access to the first transfer memory or to the second transfer memory. 
         [0018]    In accordance with the method, a locking device is operated in the control device, where before a write access with output data to the output buffer or before a read access of input data at the input buffer, a status indicator is set, and once the status indicator is set, a switch between the first and the second transfer memory is blocked. 
         [0019]    Regarding the byte-by-byte addressing of the transfer memory, i.e., the output buffer and the input buffer, for a read access of output data from the output buffer, a semaphore is interrogated and depending on the status of the semaphore, the output data is either read from the first transfer memory or from the second transfer memory. The data is stored byte-by-byte in the transfer memory and each byte is assigned a semaphore with the index. As a result, a byte in the first transfer memory is assigned the semaphore with a first state and a corresponding byte in the second transfer memory is assigned the semaphore with a second state, where the second state corresponds to the negated first state. For data consistency the transfer memory is duplicated, which is why a byte and a corresponding byte will be referred to here. 
         [0020]    The list storage device is advantageously a duplicated list and operated in duplicate, and indeed a first list storage device and a second list storage device is set up. 
         [0021]    The method is used to particular advantage in the network of an industrial automation system, where the first transceiver device is operated for data of a field bus of the industrial automation technology and the second transceiver device is operated for data of a backplane bus of the input/output device which comprises a decentralized peripheral of the industrial automation technology. In this case, a backplane bus controller and a field bus controller are also operated in the control device. 
         [0022]    Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    The drawing shows a possible exemplary embodiment of the interface device or a possible execution sequence of the method, in which: 
           [0024]      FIG. 1  shows an automation device with a connected decentralized peripheral in accordance with the invention; 
           [0025]      FIG. 2  shows a schematic block circuit diagram of a controller and a list storage device of an interface device in accordance with the invention; 
           [0026]      FIG. 3  shows a program flowchart for writing output data in accordance with the invention; 
           [0027]      FIG. 4  shows a program flowchart for reading output data in accordance with the invention; 
           [0028]      FIG. 5  shows a program flowchart for writing data from a backplane bus controller into an input buffer in accordance with the invention; and 
           [0029]      FIG. 6  shows a program flowchart for reading data out of the input buffer in accordance with the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0030]    In accordance with  FIG. 1 , an automation device  110  is connected to a first bus system  11   a,  where an interface device  1  with an input/output device  100  in a modular decentralized peripheral design is connected to the first bus system  11   a.  A connection exists via a first transceiver device  11  between the interface device  1  and the automation device  110 . There is a connection via a second transceiver device  12  between the interface device  1  via a second bus system  12   a  and the input/output device  100 , where the input/output device  100  has a first slot  101 , a second slot  102  and a third slot  103 . The slots  101 ,  102 ,  103  in their turn each divided into three subslots, i.e.,  111 ,  121 ,  131  and  112 ,  122 ,  132  and  113 ,  123 ,  133 . 
         [0031]    For exchange of data between the automation device  110  and the slots  101 , . . . ,  103 , which are configured as input/output modules, the interface device  1  has a data transfer device  20 , which is divided up into a first transfer memory  21  and a second transfer memory  22 . 
         [0032]    In accordance with  FIG. 2 , the interface device  1  of  FIG. 1  is shown schematically in a block circuit diagram. The interface device  1  for exchanging data of the first bus system  11   a  and of the second bus system  12   a  is connected to the first bus system  11   a  at a first transceiver unit  11 , where the first bus system  11   a  comprises, for example, an industrial Profinet field bus. The second bus system  12   a,  which comprises, for example, the backplane bus of a modular-construction peripheral system, is connected to the second transceiver device  12   a.  The transceiver devices  11 ,  12  are linked to an addressing system  49 . The addressing system  49  obtains notification via a list storage device  40  of a data structure for addressing the data for the input/output device  100  (see  FIG. 1 ), the data structure in this case contains a plurality of subslots  111 ,  112 ,  113  in a telegram format of the telegrams of the first bus system  11   a.    
         [0033]    The respective data structure in this case has the following structure: For each byte to be addressed in the first transfer memory  21  or the second transfer memory  22 , there is a memory offset  44  available, related to a start address  45  of the first and/or second transfer memory  21 ,  22 . Furthermore the list storage device  40  also has a data length  46  of the input/output data. The data structure with the memory offset  44  and the data length  46  is assigned to the subslots  111 ,  112 ,  113  via an index (i). The list storage device  40  is formed in duplicate as a first list storage device  41  and as a second list storage device  42 . It is determined via a selector  48  in each case whether the first list storage device  41  or the second list storage device  42  provides input data for the addressing system  49 . 
         [0034]    A switchover from a first list storage device  41  to the second list storage device  42  can be advantageous if, for example, a Profinet I/O constellation is changed via an engineering system during the course of operation. Thus, up to the time at which the changed data is to be accepted, operation will be with the configuration in the first list storage device  41  and, after a switchover point, operation is with a new configuration, which has been stored, for example, in the second list storage  42 . 
         [0035]    The addressing system  49  is supported via a command list  43 . In this example, the controller  30  simultaneously contains the data transfer device  20 , which is basically subdivided into a first transfer memory  21  and into a second transfer memory  22 , where the first transfer memory  21  is subdivided for its part into a first output buffer  21   a  and into a second output buffer  22   a  and the second transfer memory into a first input buffer  21   b  and into a second input buffer  22   b.  The start address  45  points in each case to a start of a memory area. 
         [0036]    A backplane controller  32  and a field bus controller  33  are available to coordinate write/read accesses to the memory areas. 
         [0037]    In order to obtain a coordinated access, a first status indicator  50  and a second status indicator  51  are set via a blocking device  31 . 
         [0038]    The first status indicator  50  could also be referred to as a global bit OB_Freeze, e.g., a bit in a register of the controller  30 , and must be set and reset by software before or after an access to the output buffer. Likewise, the second status indicator  51  can be set and reset by software before or after an access to the output buffer as a global bit IB_Freeze, this bit too is a bit in a register of the controller  30 . 
         [0039]    To this end, the blocking device  31  is operated in the control device  30  such that, before a write access with output data to the output buffer  21   a,    22   a  or before a read access of input data to the input buffer  21   b,    22   b,  either the first status indicator  50  or the second status indicator  51  is set, so that with one of the set status indicators  50 ,  51 , a switch between the first and the second transfer memory is blocked, whereby data consistency is achieved. 
         [0040]      FIG. 3  shows a program execution sequence  300  for the writing of output data, where the output data is sent from the automation device  110  shown in  FIG. 1  by the first bus system  11   a  to the interface device and is accepted from the interface device  1  in the first transceiver device  11 . The program execution sequence  300  shows a possible implementation in a suitable programming language for an Application Specific IC (ASIC), for example, where this ASIC would then be used in the interface device  1  as a control device  30 . 
         [0041]    The program execution sequence  300  starts with a write order  301 , in which the order is contained to write a byte i, which is likewise provided in the list storage device  40  with the index i, into one of the two output buffers  21   a  and  22   a.  The decision as to which of the two output buffers  21   a,    22   a  into which the byte i is ultimately written, is made via an interrogation operation  303 . 
         [0042]    In any event, the first status indicator  50  is preset to the value “1” using a set operation  302 . By software implemented, for example, in the ASIC, preferably before data is written into the data transfer device  20  before data is read from the data transfer device, a bit is to be set, where the set bit serves to indicate that at this point in time no change of memory may be performed. In relation to the writing of output data, this means that the first output buffer  21   a  and the second output buffer  22   a  are frozen. 
         [0043]    With the interrogation operation  303 , a semaphore S i  is interrogated. The semaphore S i  is also embodied as a bit, for example, which can assume the state “0” or “1”. 
         [0044]    In accordance with  FIG. 3 , in addition to the program execution sequence  300 , a first stable state A and a second stable state B are shown. In this diagram of the stable states A, B, a state of the byte of a payload data block, preferably of a subslot, is shown in each case. In this case, this byte is an extract from the byte-oriented first transfer memory  21  or second transfer memory  22 . In particular, in the presentation of the first stable state A and of the second stable state B, a byte of the first output buffer  21   a  or a byte of the second output buffer  22   a  is meant in the program execution sequence  300  for the writing of output data. 
         [0045]    The semaphore S i  or the negated value of the semaphore S i   −1  each represent the permissibility of a possible write access to this byte-oriented address of the output buffer  21   a  or  22   a.    
         [0046]    From the interrogation operation  303  of the semaphore S i , the sequence reaches a write access  304  to the first output buffer  21   a  via a NO branch, i.e., the semaphore S i  has a value S i =“1”. 
         [0047]    The write order  301  initiated at the start now has permission to write into the byte-granular memory cell of first output buffer  21   a  addressed with the index i, an arrow starting from the NO branch of the interrogation operation  303  points symbolically to the first stable state A, which is a representation before the write access. After the write access  304  to the first output buffer  21   a,  a further arrow points symbolically to the second stable state B of the byte-granular memory cells of the first output buffer  21   a  and of the second output buffer  22   a.    
         [0048]    The second stable state B has been reached via a notification  307  to change memory and via a further interrogation operation  308  as to whether the first status indicator  50  is set to “0” again, and whether a further variable “backplane bus in operation” (short form: RBSY[i]) likewise has the value “0”. If this is the case, the correspondingly previously initiated semaphore S i  is negated by a memory change action  309  and an auxiliary vector is set (New Data[N:0]) which is used for notification of the memory change after a write access to the byte i. 
         [0049]    If the interrogation operation  303  had produced the value of the semaphore S i =“0”, the program execution sequence  300  would have been continued with the YES branch of the interrogation operation  303  and a write access  305  to the second output buffer  22   a  would have been allowed. The semaphore S i  has the value “0” for this state. As a result, the second stable state B of a byte-granular memory value in the output buffer  21   a,    22   a  would now have been valid. This is again indicated by a symbolic arrow. After successful write access  305  to the second output buffer  22   a  and the notification  307  for a memory switchover with the continuous interrogation operation  308  of whether the first status indicator  50 =“0” and the RBSY[i]-variable=“0” and the semaphore S i  has ultimately been negated in the memory switch action  309 , in this lower part of the program execution sequence  300  after the write access  305 , the first stable state A is now reached starting from the second stable state B. 
         [0050]      FIG. 4  shows a program execution sequence  400  for reading output data from the corresponding first output buffer  21   a  or the second output buffer  22   a.  The program execution sequence  400  starts with an order  401  to read a byte i. The byte i can, for example, be a byte within a payload data block of a subslot. The memory address of this byte i is determined via the list storage device  40 . 
         [0051]    In relation to  FIG. 1 , the read order  401  means that the input/output device  100 , for example, via the first slot  101 , via the first subslot  111 , has provided a byte or an entire payload data block via the backplane bus of the interface device  1 . 
         [0052]    The read order  401  is followed by an interrogation operation  403  as to whether the semaphore S i  belonging to the byte i=“1”. If it does, there is an exit from the interrogation operation  403  via the YES branch and a set operation  405  follows in which the variable RBSY[i]=“1” is set. There now exists an identifier that the backplane bus is in operation. There may now be a read access  407  to the second output buffer  22   a.  The first stable state A is presented to symbolize the byte-granular access. After a successful read access to the second output buffer  22   a,  the variable RBSY[i] can be reset to “0” via a further setting operation, which means that the backplane bus is not in operation. 
         [0053]    If exit from the interrogation operation  403  was with the NO branch, which means that the semaphore S i  had the value “0”, then the variable RBSY[i] is once again set via a set operation  404  and there is a read access  406  to the first output buffer  21   a.  This state in its turn is symbolized by the second stable state B. After the successful access  406  to the first output buffer  21   a,  the variable RBSY[i] is set to “0” in a setting operation  408 . 
         [0054]      FIG. 5  presents a program execution sequence  500  for writing data of the backplane bus controller  32  into the input buffer or buffers  21   b,    22   b.  Starting with a write order  501 , in which the backplane bus controller wishes to write the byte i into the corresponding input buffer  21   b,    22   b,  an interrogation is first performed in an interrogation operation  502  as to whether the semaphore S i  belonging to the byte i has the value “0”. If the semaphore has the value “1”, then the sequence exit from the interrogation operation  501 ,  502  is via the NO branch and a write access  503  to the first input buffer  21   b  with the byte I is allowed. 
         [0055]    If the semaphore S i  had the value=“0”, then a write access  504  to the second input buffer  22   b  would be allowed via the YES branch of the interrogation operation  502 . After a successful write access either to the first input buffer  21   b  or to the second input buffer  22   b,  there is an interrogation with an interrogation operation  506  via a notification  505  of change of memory as to whether the second status indicator  51 =“0”. There is also an interrogation as to whether a release signal for a memory switchover is present. The release signal comes from the backplane bus controller, for example, and signifies whether the entered data is complete, or whether there are still data packets missing. If the release signal is set, the memory switchover is performed and the semaphore S i  is negated, through which there is a switch in the upper branch with the write access  503  to the first input buffer  21   b  from the first stable state A into the second stable state B, and via the write access  504  to the second input buffer  22   b  there is conversely a switch from the second stable state B into the first stable state A of the byte-granular addressed memory cells. 
         [0056]      FIG. 6  shows a program execution sequence  600  for reading data from the input buffers  21   b,    22   b.  Beginning with a read order  601 , a read access is initiated with the software implemented in the ASIC to the input buffer  21   b,    21   a.  Since input data is now to be forwarded from the backplane bus to the automation device, before the read access the second status indicator  51  must be set via a setting operation  602 , through which ultimately a “IB_FREEZE” command is issued, which means that the corresponding input buffers  21   a  and  21   b  are now frozen. An interrogation operation  603  interrogates via the byte-granular addressing with the index i as to whether the semaphore S i  of this byte to be read i=“1”. If it is, there may be access via a read access  605  to the second input buffer  22   b  and in the event that the semaphore S i =“0”, there may be access via a further read access  604  to the first input buffer  21   a.  By way of explanation, the program execution sequence  600  is once again assigned the first stable state A and the second stable state B of the byte-granular memory cells at the corresponding memory access branches. 
         [0057]    While there have been shown, described, and pointed out fundamental novel features of the invention as applied to a preferred embodiment thereof, it will be understood that various omissions and substitutions and changes in the form and details of the methods described and the devices illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit of the invention. For example, it is expressly intended that all combinations of those elements and/or method steps which perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Moreover, it should be recognized that structures and/or elements and/or method steps shown and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.