Abstract:
The present invention offers a low cost, reliable, on chip implementation that provides driving voltages to VCSEL devices. One feature of the invention is the buffer circuit that adjusts the buffered driving voltage using feedback from the output circuit. The present invention therefore may be used in a varying number of VCSEL circuits that require different voltage levels and headrooms for proper operation.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
         [0001]    None  
         STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH  
         [0002]    None  
         BACKGROUND OF THE INVENTION  
         [0003]    The invention relates to a method and apparatus for driving high speed VCSEL circuits.  
           [0004]    The term VCSEL stands for Vertical Cavity Surface Emitting Laser. These relatively new devices are semiconductor devices that emit light from a flat surface area of a chip analogous to an LED. The VCSEL device offers the performance advantages of an LED while producing laser type light. The application of these devices are numerous and varied. The present invention would use VCSEL&#39;s in an ethernet or optical data transmitting environment.  
           [0005]    As VCSEL devices are connected in a common cathode configuration, switching current through them at high speeds is a challenge. This is primarily due to the unavailability in integrated circuits of high speed current sourcing devices such as pnp or PMOS transistors. The npn transistors available in integrated circuits are capable of high speed operation, however it is difficult to use them because of the low output headroom dictated by the ground-connected VCSEL&#39;s.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention is a buffer and output stage for providing the high-speed data signal to a common cathode VCSEL. The differential output signals of the buffer have a common-mode voltage that allows the transistors in the output stage to operate at high speeds with minimum collector-emitter voltages. The buffer has an adaptive feature for accommodating different VCSEL drive currents and for ensuring a proper bias voltage across the tail current source of the output differential stage. Also covered by this disclosure is a current-splitting technique that is used in the output stage for minimizing the transient currents through the bias source. The present invention includes three separate embodiments of the buffer circuit and two separate embodiments of the output stage circuit.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1 shows a block diagram of the high speed VCSEL driver circuit.  
         [0008]    [0008]FIG. 2 shows a first embodiment of the buffer stage of the VCSEL driver circuit as in the present invention.  
         [0009]    [0009]FIG. 3 shows a first embodiment of the output stage of the VCSEL driver circuit of the present invention.  
         [0010]    [0010]FIG. 4 shows a second embodiment of the buffer stage of the VCSEL driver circuit as in the present invention.  
         [0011]    [0011]FIG. 5 shows a third embodiment of the buffer stage of the VCSEL driver circuit as in the present invention.  
         [0012]    [0012]FIG. 6 shows a second embodiment of the output stage of the VCSEL driver circuit as in the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]    A block diagram of the driver which is composed of a buffer stage ( 10 ) an output stage ( 12 ) and a bias control ( 11 ) connected as shown in FIG. 1. The driver circuit operates from a single power supply and provides high-speed current data to a grounded-cathode VCSEL ( 13 ). The buffer ( 10 ) accepts the differential signals Vin+ and Vin− from another circuit which may be present on the same chip, and provides the differential signals VoutB+ and VoutB− to the npn output stage ( 12 ). A bias control circuit ( 11 ) provides an adjustable dc bias voltage VBIAS to the output stage ( 12 ). Prior art circuits do not employ any type of buffer circuit as disclosed in the present invention. The present invention allows for high speed npn transistors to be used to drive VCSEL&#39;s connected in a common cathode configuration.  
         [0014]    A first embodiment of the present invention can be seen in FIG. 2. FIG. 2 is a schematic diagram of the buffer ( 10 ) as shown in FIG. 1. The inputs to the buffer Vin+ and Vin− are first applied into emitter followers Q 1 B and Q 2 B. This differential signal is then applied to the differential pair comprising Q 3 B and Q 4 B. The output signal of the differential pair is developed across identical collector resistors R 1 B and R 2 B and then applied to the output stage shown in FIG. 3. Emitter followers Q 5 B and Q 6 B are used to couple the signal to the output stage ( 12 ). The dc voltage Vmodset, generated in the output stage of FIG. 3, is used in the circuit of FIG. 2. This voltage, along with transistor Q 7 B and resistor R 3 B, provides for the adaptive drive feature of the present invention. This adaptive drive feature allows for the output voltages provided by the buffer to be larger when the VCSEL modulation current is larger.  
         [0015]    The amplifier ABUF and resistors R 4 B and R 5 B essentially close a feedback loop that provides an appropriate operating condition in this circuit. This operating condition is that the common-mode voltage of the buffer output signals VoutB+ and VoutB− equals Vmodset+VDC 1 . In this way the buffer circuit outputs the proper voltages that will be used in the next circuit, i.e. the output stage of the driver. This compensation allows the buffer of the present invention to be used in a variety of VCSEL driver circuits. If the gain of amplifier ABUF is much greater than one, the common mode voltage VoutBcm may be calculated as  
               V                 o                 u                 t                 B                 c                 m     =           VoutB   ++        VoutB     2     ≅     Vmodset   +   VDC1               (   1   )                               
 
         [0016]    The output stage of the present invention is shown in FIG. 3. The differential output signals of the buffer VoutB+ and VoutB− are applied to the differential amplifier made up of transistors Q 1 M, Q 2 M and Q 3 M. The modulation current IMODT is generated in a closed-loop configuration using operational amplifier AMOD, transistor QMOD and resistor RMOD, and an external adjustable voltage VMOD. This current is switched through Q 3 M according to the polarity of (VoutB+−VoutB−). An output resistor ROUT, whose value is matched to the internal resistance of the VCSEL, is used in conjunction with a voltage VBIAS (which may also be generated by an operational amplifier) to establish the desired bias current through the VCSEL. The areas of transistors Q 1 M and Q 2 M are exactly half the area of transistor Q 3 M for ensuring minimum transient currents through VBIAS. On-chip inductor LT is used in series with the collector of QMOD for increasing the impedance of the modulation current source at high frequencies. Resistor RT is connected in parallel with LT for minimizing the effect of possible resonances. A resistor RBAL is connected in series with the collector of Q 1 M for balancing the base-collector capacitance reflected through the Miller effect on the inputs of the differential amplifier.  
         [0017]    Under dynamic conditions, transistor QMOD of FIG. 3 has minimum collector voltage (and maximum base-collector voltage) when VoutB+ and VoutB− become equal (and equal to the common-mode voltage VoutBcm given by equation (1)). Then, using equation (1), the maximum base-collector voltage of QMOD is obtained as:  
           VbcMOD max≅Vbe 1 M−VDC 1 .  (2)  
         [0018]    By properly generating VDC 1  in the circuit of FIG. 2, it is possible to have VbcMODmax approximately equal to 0.2-0.3 V (slight forward bias for the base-collector junction), which ensures that QMOD is still practically in the forward active region and its collector voltage has the minimum possible value for high-speed operation. A value larger than 0.2 to 0.3 V for the forward bias voltage of the base-collector junction will push the transistor into saturation, where the transistor beta and output impedance are significantly degraded both at dc and at high frequencies.  
         [0019]    Besides ensuring a minimum possible voltage for the collector voltage of QMOD, the small common-mode voltage VoutBcm also ensures the proper headroom for the output device Q 3 M in FIG. 3. Thus, if the input signal in FIG. 2 is overdriving the differential pair Q 3 B and Q 4 B, the maximum output buffer voltage present on the base of Q 3 M is:  
               V                 o                 u                 t                 B                 max     =       V                 o                 u                 t                 B                 c                 m     +       I3B   ×   R1B     2               (   3   )                               
 
         [0020]    If the minimum VCSEL voltage is denoted by VVCSELmin, the maximum base-collector voltage Vbc 3 Mmax of transistor Q 3 M is:  
         Vbc 3 Mmax= VoutB max− VVCSEL min  (4)  
         [0021]    With VVCSELmin on the order of 1.4 V it is possible to obtain values on the order of 0.2 to 0.3 V for Vbc 3 Mmax as well as for VbcMODmax. This ensures high-speed operation and virtually the same device benefits as in the forward active region.  
         [0022]    The buffer in FIG. 2 has the disadvantage that the common-mode voltage that is fed back to amplifier ABUF is obtained directly from the high-frequency output signals VoutB+ and VoutB−. This results in propagating any signal due to the mismatch between the two outputs through the low-frequency feedback loop. A circuit which eliminates this disadvantage is illustrated in FIG. 4, where the common-mode voltage fed to the amplifier is obtained indirectly by means of transistors Q 9 B and Q 10 B, resistor R 5 B, and current source I 6 B. In FIG. 4, assuming that all the transistor base-emitter voltages are equal (device scaling is used to ensure equal de current densities through the transistors), and the following conditions are met,  
           I3B   ×   R1B     2     =     I6B   ×   R5B               R1B     2      R3B       =     R5B   R4B                           
 
         [0023]    then the emitter voltage of Q 11  is equal to the common-mode output voltage which is a function of dc currents only, even in the case of a mismatch in the signal path. In this way, the common-mode voltage of the high-frequency output differential signal is established by feedback in a separate low-frequency loop. An optional on-chip capacitor C 1 B can be connected as shown in FIG. 4. This capacitor prevents high-frequency transients on the emitter of Q 9 B due to the large-signal operation of the differential pair Q 3 B and Q 4 B from being injected into the feedback loop and provides good-quality ground-referenced output signals.  
         [0024]    The circuit in FIG. 5 is similar to the circuit of FIG. 4, and details the implementation of amplifier ABUF using differential pair Q 12 B−Q 13 B and resistor R 6 B, and the implementation of VDC 1  using transistor Q 14 B and Schottky diode D 1 B. With a properly chosen bias current I 9 B the diode voltage VD 1 B can be as low as 0.2 to 0.3 V and VDC 1  becomes:  
         VDC 1 =Vbe 14 B−VD 1 B.  (7)  
         [0025]    Using equations (2) and (7), the maximum base-collector voltage of QMOD in FIG. 3 is approximately 0.2 to 0.3 V because:  
           VbcMOD max=Vbe 1 M−Vbe 14 B+VD 1 B≅VD 1 B.  (8)  
         [0026]    The circuit of FIG. 6 is similar to the circuit of FIG. 3 and has an additional loop for generating the bias voltage VBIAS. The circuit is intended for applications where there exists a photodiode optically coupled with the VCSEL. The feedback loop ensures that the current through the VCSEL is maintained at a prescribed value by developing a voltage across resistor RPD using the current of the photodiode, comparing it to an adjustable voltage set using resistor RREF and adjustable resistor RPWR, and amplifying the difference using amplifier ABIAS. The current splitting ensured by Q 2 M is used to minimize the current transients through the non-ideal output of ABIAS.  
         [0027]    As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalence of such metes and bounds are therefore intended to be embraced by the appended claims.