Abstract:
A method for producing integrated circuit devices comprises the steps of forming and packaging such devices at the wafer scale, including forming a plurality of chip circuits with bond pads, adhesively fixing a plate of glass to the active surface of the wafer, slicing the wafer, applying a sealant layer to the backside of the wafer, forming contact holes through the upper glass plate, metallizing the glass plate and singulating the individual chips. Use of etchable glass for the package and palladium for metallization provides an advantageous construction method.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]    This application is a continuation of application Ser. No. 09/388,033, filed Sep. 1, 1999, pending, which is a continuation of 09/082,745, filed May 21, 1998, now U.S. Pat. No. 6,008,070, issued Dec. 28, 1999. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    This invention relates to packaged semiconductor devices and methods for manufacture thereof. More particularly, the invention pertains to ultra-thin devices having a small footprint and simplified processes for their manufacture including device packaging at the wafer scale.  
           [0004]    2. Description of the Related Art  
           [0005]    Solid state electronic devices, more colloquially known as semiconductor chips or dice, are typically manufactured from a semiconductor material such as silicon, germanium or gallium/arsenide. Circuitry is formed on one surface of the device with input and output (I/O) pads formed around the periphery or centrally positioned to facilitate electrical connection with a host electrical apparatus.  
           [0006]    A profusion of small electronic consumer products includes pagers, notebook computers, cellular telephones, digital cameras, modems, global position systems and electronic watches, to name a few. The rapidly growing consumer demand for small product size and low profile products drives the search for ways to construct smaller, thinner, more powerful semiconductor devices. The development of inexpensive, ultra-thin, compact devices is needed to enable the proliferation of large numbers of miniature electronic apparatus in the near future.  
           [0007]    Currently, semiconductor chips are typically packaged to protect the chip from mechanical damage, external contamination and moisture. Most commonly, semiconductor chips are encapsulated, i.e. packaged within a polymeric material which sometimes provides opportunity for moisture ingress, gas diffusion, corrosion, etc. Thus, plastic encapsulated chips may be subject to performance degradation and abbreviated life.  
           [0008]    Ceramic encapsulation provides a higher level of protection for the chip. However, the process is more complex and results in an expensive package of increased size.  
           [0009]    Sealing of the semiconductor chip active circuitry at the wafer stage is known. In this process, a passivation coating of ceramic materials such as silica and/or silicon nitride may be applied by chemical vapor deposition (CVD). However, the subsequent etching back of the passivation coating at the bond pads of the semiconductor chip may damage the coating around the bond pads, resulting in a non-hermetic seal and permitting corrosion to deleteriously affect chip reliability and life.  
           [0010]    U.S. Pat. No. 5,336,928 of Neugebauer et al. discloses a hermetically sealed device construction.  
           [0011]    U.S. Pat. Nos. 5,455,459 and 5,497,033 of Fillion et al. disclose systems for enclosing and interconnecting multiple semiconductor chips.  
           [0012]    U.S. Pat. No. 5,481,135 of Chandra et al. discloses the use of ceramic materials in hermetically sealed device packages.  
           [0013]    U.S. Pat. No. 4,769,345 of Butt et al., U.S. Pat. Nos. 4,866,571, 4,967,260 and 5,014,159 of Butt, U.S. Pat. No. 5,323,051 of Adams et al., and U.S. Pat. No. 4,821,151 of Pryor et al. disclose the use of glass in the packaging of certain types of semiconductor devices.  
           [0014]    U.S. Pat. Nos. 4,749,631 and 4,756,977 of Haluska et al. disclose ceramic and ceramic-like compositions which may be used for coating electronic devices.  
           [0015]    In U.S. Pat. No. 5,682,065 of Famworth et al., a fully hermetically sealed semiconductor chip is disclosed. The bare die is covered with a coating of glass using a spin-on-glass (SOG) process, a dip process or flow coating. The glass is applied as a mixture of small glass particles and a polymeric carrier, and subsequently heated to evaporate solvent(s) from the mixture and harden the applied material. Also disclosed are steps of thinning the wafer.  
           [0016]    U.S. Pat. No. 5,547,906 of Badehi discloses a method for forming semiconductor chip packages with edge connections. The step of singulation with a cutting tool exposes the array of contacts. A glass may be used as covers sandwiching the chip therebetween.  
         SUMMARY OF THE INVENTION  
         [0017]    The invention comprises a method for fabricating size-efficient semiconductor devices, including hermetically sealed devices, wherein most of the operations are conducted at the wafer scale. The method enables the simplified manufacture of ultra-thin packaged devices, having a footprint only slightly larger than the die size.  
           [0018]    A wafer is prepared with multiple die sectors having internal circuits with conductive bond pads. A thin plate of glass is then adhesively attached to the active side of the wafer. The glass is configured for photo-etching, making repatterning of the wafer front side prior to glass overlay unnecessary. Furthermore, scribing of the wafer prior to metallization of the glass plate is unnecessary.  
           [0019]    If needed, the exterior surface of the glass plate is leveled and made parallel to the front side (active surface) of the wafer and polished, based on the wafer&#39;s parallel backside. The leveling, paralleling and cleaning of the glass plate prepares the exterior glass surface for metallization.  
           [0020]    The backside of the wafer is then reduced in thickness by chemical, mechanical, or chemical-mechanical means, such as are known in the art, to provide chip substrates with minimum thickness. The wafer is then cut or etched in the street areas between the chip sectors to individualize the chips, while leaving intact the upper glass plate to which the chips are individually attached. The glass plate enhances the resistance to premature breakage along the street areas or of the chips themselves.  
           [0021]    A second glass plate is then adhesively affixed to the backside of the wafer, the adhesive filling the opened street areas between the chip sectors.  
           [0022]    Alternatively, a polymeric sealant material may be applied over the backside of the wafer, instead of adhesively attaching the second plate of glass. In addition, another alternative is applying a mixture of glass particles and polymer, which may be applied in a spin-on-glass process.  
           [0023]    On the upper glass plate, contact holes are formed through the glass and adhesive to access the bond pads, using a photolithographic etching process. The glass plate is then metallized and etched to define leads thereon.  
           [0024]    Preferably, metallization of the front side of the glass plate is based on palladium or a palladium alloy, which, because of its solder wettability, eliminates the need for a solder mask limiting layer. A chemical vapor deposition (CVD) process or sputtering process deposits the conductive metal in the contact holes and on the glass surface, and a subsequent patterning of the metallization enables the formation of interconnects on the glass surface. Alternately, deposit may be made by wet deposition by first sputtering metal, such as aluminum, etc., then patterning the metal (aluminum), then using a zincate process, applying nickel, then applying a flash plating of palladium, which results in a thicker metal and a lower resistance with less palladium being required.  
           [0025]    The chips may then be singulated by e.g., sawing, and the die of each chip will be entirely enclosed.  
           [0026]    To ensure that the chip is fully hermetically sealed, a coating of silicon nitride may be applied prior to, or following, the step of metallizing the upper glass surface.  
           [0027]    In an alternative embodiment of the invention, glass is applied to the front side and/or backside of the wafer as spin-on-glass (SOG), which may be polished flat. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0028]    The invention is illustrated in the following figures, wherein the elements are not necessarily shown to scale but are uniformly identified throughout:  
         [0029]    [0029]FIG. 1 is a plan view of a semiconductor wafer having a plurality of semiconductor chips formed thereon;  
         [0030]    [0030]FIG. 2 is a plan view of a bare semiconductor chip having a bond pad arrangement applicable to the method of the invention;  
         [0031]    [0031]FIG. 3 is a plan view of another type of semiconductor chip having a bond pad arrangement applicable to the method of the invention;  
         [0032]    [0032]FIG. 4 is a partial cross-sectional view of a wafer of semiconductor chips illustrating initial steps of the method of the invention;  
         [0033]    [0033]FIG. 5 is a partial cross-sectional view of a wafer of semiconductor chips illustrating further steps of the method of the invention;  
         [0034]    [0034]FIG. 6 is a partial cross-sectional view of a wafer of semiconductor chips illustrating additional steps of the method of the invention;  
         [0035]    [0035]FIG. 7 is a partial cross-sectional view of a wafer of semiconductor chips illustrating still further steps of the method of the invention;  
         [0036]    [0036]FIG. 8 is a partial cross-sectional view of a wafer of semiconductor chips illustrating added steps of the method of the invention;  
         [0037]    [0037]FIG. 9 is a partial cross-sectional view of a wafer of semiconductor chips illustrating additional steps of the method of the invention;  
         [0038]    [0038]FIG. 10 is a partial cross-sectional view of an alternative wafer of semiconductor chips illustrating alternative steps of the method of the invention; and  
         [0039]    [0039]FIG. 11 is a partial cross-sectional view of an alternative wafer of semiconductor chips illustrating additional alternative steps of the method of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0040]    Referring to drawing FIG. 1, a wafer  10  is shown comprising a plurality of semiconductor chips or dice  12  formed thereon. Each semiconductor chip  12  may include a suitable passivation layer or layers (not shown) which is well known in the art for providing a degree of protection for the active circuitry on the chip  12 . As shown, the semiconductor chips or dice  12  have not been separated but remain in the form of a wafer  10  for additional wafer processing. While in wafer form, each individual semiconductor chip  12  is distinguished from adjacent chips by generally circuit-free street areas  22  therebetween.  
         [0041]    In the following description, the term “silicon” will be used in a generic sense to include other semiconductive materials such as gallium/arsenide or germanium, which are useful for fabricating electronic devices.  
         [0042]    As depicted in drawing FIG. 2, a semiconductor chip  12  has a leads-over-chip configuration. Bond pads  14  are connected to circuitry within the chip  12  for access by a host electronic apparatus, not shown. The bond pads  14  are typically arrayed in one or two rows near a central axis  16  of the chip  12 , as shown by representation in drawing FIG. 2, and may comprise a large number.  
         [0043]    In drawing FIG. 3, another semiconductor chip  12  is shown with bond pads  14  positioned near opposed edges of the chip.  
         [0044]    Chips may be formed with other bond pad configurations. The invention as described herein is applicable irrespective of the bond pad position on the chip  12 .  
         [0045]    Referring now to drawing FIGS. 4 through 11, the method of the present invention will be described with reference to a portion of a wafer  10  showing portions of several semiconductor chips  12  located thereon.  
         [0046]    In drawing FIG. 4 is shown a portion of a silicon substrate wafer  10  which may be prepared in accordance with procedures common in the art. The substrate wafer  10  has a first side  24  and an opposed second side  26 , and a thickness  32 . The wafer  10  is shown with portions of two semiconductor chips  12  formed therein. Each chip  12  has an integrated circuitry  18  which is connected to bond pads  14  on the first side  24 , also known as an “active surface”. Passivation coatings, not shown, may be applied to portions of the first side  24 , as known in the art. Street areas  22  separate the individual chips  12  on the wafer  10 .  
         [0047]    Before separating the chips  12  from the unitary wafer  10 , a first thin plate  30  of glass is affixed to the first side  24  of the wafer  10  by an adhesive  20  to preferably overcover the entire wafer. The adhesive  20  may be, for example, an epoxy, polyimide, etc. Examples of such are two-part epoxies, low temperature curing polyimide-siloxanes, two-part adhesives, etc. The first glass plate  30  is preferably a photo-etchable glass having an exposed or outer surface  34  and an inner surface  36 , with a thickness  28  of about 200 to about 2000 μm. An example of such a first glass plate  30  is photosensitive glass sold by SchottGlass of Yonkers, New York, under the trademark FOTURAN™. The photo-etchable glass plate  30  is commercially available in thicknesses of 200 to 2000 μm.  
         [0048]    If necessary, the exposed or outer surface  34  of the glass plate  30  is planarized and polished, based on the second side  26 , i.e., backside of the wafer  10 . Use of the second side  26  as a level surface standard may be particularly required if less expensive glass plate of less stringent tolerances is used. In any event, the outer surface  34  of the glass plate  30  must meet surface requirements for subsequent application of metallization thereto.  
         [0049]    Turning now to drawing FIG. 5, the wafer  10  is shown with a reduced thickness  32 . The second side  26  of the wafer  10  is subjected to a thinning step which may comprise a chemical etching process, a mechanical abrasion process, or a process by which the wafer surface is wet-polished with a chemical etchant/abrasive slurry. The second side  26  is also planarized, based on the exposed outer surface  34  of the first glass plate  30 . Alternatively, if no further thinning of the wafer  10  is desired, the step is omitted. Etching through of the wafer  10  in street areas  22  is more readily accomplished when the wafer is relatively thin.  
         [0050]    As depicted in drawing FIG. 6, the chips  12  are separated by dividing the wafer along the street areas  22 . The street areas  22  of the wafer are, for example, etched out to separate the chips  12 , while each chip remains attached to the unitary first glass plate  30 . Etching processes and systems which may be used to etch the semiconductor material are well known in the art, and include the application and development of resist material, not shown, for limiting the etched area. Alternatively, the street area  22  may be mechanically scribed to provide individual chips  12  on first glass plate  30 . The assembly of the wafer  10  and the first glass plate  30  is then coated with a hermetic coating, such as silicon nitride, on the backside thereof.  
         [0051]    As shown in drawing FIG. 7, a second glass plate  40  is then fixed to the second (backside) side  26  of the chips  12  by a sealant adhesive  38 . The adhesive  38  fills the street area  22  removed to separate the chips  12 , and is configured to be sealingly bonded to the first adhesive  20 . Thus, each chip  12  is completely surrounded by a sealing adhesive. The second glass plate  40  is shown with an exterior surface  42  which generally forms one surface of the completed semiconductor device.  
         [0052]    Turning to drawing FIG. 8, the next step of the process is illustrated as comprising the formation of linear contact holes  50  through the first (upper) glass plate  30  and adhesive  20 . These holes  50  are formed by etching or by a mechanical, e.g., drilling, process. The holes  50  are aligned in an array which is identical to the array of bond pads  14  on the first side  24  of the wafer  10 . The holes typically have an internal diameter of about 20 to 100 μm. An aspect ratio of about 30 to 1 is desirable for consistent filling of the contact holes with metal.  
         [0053]    As shown in drawing FIG. 9, external leads  44  are formed by metallizing the outer surface  34  of the first glass plate  30 , using a photo-lithographic process. While metals such as tungsten, aluminum and copper, or alloys thereof, may be deposited as leads, a preferred conductive material is palladium or an alloy thereof, because of its wettability for subsequent soldering.  
         [0054]    The metallization includes an interconnect for each lead  44  by which connection may be made to an electrical apparatus such as a circuit board. If desired, a lead frame, not shown, may be attached to the packaged chip and wire bonded thereto. Surface mount interconnects including ball grid arrays (BGA) may be formed on the first glass for attachment to a circuit board or other substrate.  
         [0055]    Singulation of the chips  12  results from cutting through the glass plates  30  and  40  and the adhesives  20  and  38  along paths  48  through the street areas  22 .  
         [0056]    In drawing FIGS. 10 and 11, depicted is an alternative configuration of the semiconductor package, in which the sealant layer  60  applied to the second side  26  (backside) of the wafer  10  may be (a) a glass-polymer mixture applied by spin-on-glass techniques or (b) a layer of sealant polymer. The glass-polymer is hardened by a heat treatment step which drives off solvent.  
         [0057]    In summary, the steps of the process for making semiconductor chips are:  
         [0058]    1. Individual integrated circuits  18  are formed in a plurality of semiconductor chips  12  on a wafer  10 , each chip having electrically conductive bond pads  14  on the first side  24  of the wafer  10 .  
         [0059]    2. The chip integrated circuits  18  are optionally tested in wafer form.  
         [0060]    3. A first glass plate  30  is fixed to the active first side  24  of a wafer  10  with adhesive  20  (or, alternatively, glass can be applied as SOG).  
         [0061]    4. Optionally, the first glass plate  30  is polished and flattened to planarize it parallel to the second side  26  of the wafer  10 .  
         [0062]    5. The wafer  10  is thinned by grinding/etching (preferably by Chemical-Mechanical Polishing (CMP)) to planarize the second side  26 .  
         [0063]    6. Use chemical, mechanical, or CMP process to cut through the street areas  22  of the wafer  10  and separate individual chips  12  while maintaining their attachment to the unitary first glass plate  30 .  
         [0064]    7. An insulative material is applied to the second side  26  of the wafer  10 . The layer may comprise a second glass plate  40  adhesively applied to the wafer, a sealant layer  60  of spin-on-glass (SOG), or a polymeric material.  
         [0065]    8. An array of linear contact holes  50  is formed through the first glass plate  30  to contact the bond pads  14 .  
         [0066]    9. The first glass plate  30  is metallized to fill the contact holes  50  and form interconnects on the glass outer surface  34 . The metal leads  44  may comprise any of a large number of metals or alloys in use. Preferably, however, the metallization comprises palladium or a palladium alloy, whose use obviates a solder mask to limit solder reflow.  
         [0067]    10. Optionally, a coat of silicon nitride may be applied to the device to enhance hermeticity of the package. This application may be prior to or following metallization.  
         [0068]    11. The chips  12  are singulated by cutting through the street areas  22  surrounding each chip.  
         [0069]    The semiconductor chips  12  may be subjected to testing at the wafer stage either prior to encapsulating with glass or following completion of the metallization step, preferably before chip singulation.  
         [0070]    There are a number of advantages which accrue from the use of the present invention.  
         [0071]    First, the package may be made truly hermetically sealed.  
         [0072]    Second, use of the backside of the silicon wafer permits paralleling the first glass plate to the wafer front, thus eliminating a process step and allowing the use of an unground, inexpensive glass plate material.  
         [0073]    Third, the surface of the first glass plate may be prepared for metallization during its planarization, eliminating a separate step.  
         [0074]    Fourth, the use of photo-etchable glass obviates a repattern step prior to overlay of the first glass plate, resulting in lower trace resistance and parasitic losses as well as shorter traces for increased speed.  
         [0075]    Fifth, the use of photo-etchable glass eliminates the need to scribe the wafer prior to the metallization step.  
         [0076]    Sixth, the use of palladium metallization eliminates the need to add a solder mask limiting layer after the under bump metallization (UBM) is applied.  
         [0077]    It is apparent to those skilled in the art that various changes and modifications may be made to the chip configurations of the invention and methods of making and practicing the invention as disclosed herein without departing from the spirit and scope of the invention as defined in the following claims.