Abstract:
An avalanche photodetector device includes a substrate having a front side and a back side, an avalanche photo detector structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality of reflecting islands disposed on the back side of the substrate.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to an avalanche photo detector (hereinafter abbreviated as APD) device and a manufacturing method thereof, and more particularly, to an APD device including heat sinks and a manufacturing method thereof. 
         [0003]    2. Description of the Prior Art 
         [0004]    APD devices are sensitive semiconductor photo detectors, and are used in applications where high sensitivity is desired, such as, example but not limited, a long haul fiber-optic telecommunication, Laser rangefinders, and single photo level detection and imaging. Conventionally, the APD devices can include at least silicon (Si) and germanium (Ge). For example, in a Si/Ge separate absorption charge multiplication (SACM) APD device, Ge provides high responsibility at near-infrared wavelengths (850 nanometers, (hereinafter abbreviated as nm)) while Si is capable of amplifying the generated photo-carriers with low noise. APD devices formed from Si and Ge therefore can provide devices capable of detecting near-infrared optical signals. However, other materials APD devices and SACM. APD devices can be formed from, for example but not limited to, groups III and V of the periodic table such as InGaAs, InGaAsP, and InP, and combinations thereof. The APD device therefore can detect light with wavelength of about not only 850 nm but also 1310 nm nm or 1577 nm. 
       SUMMARY OF THE INVENTION 
       [0005]    According to an aspect of the present invention, there is provided an APD device. The APD device includes a substrate comprising a front side and a back side, at least an APD structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality reflecting islands disposed on the back side of the substrate. 
         [0006]    According to an aspect of the present invention, there is provided a method for manufacturing an APD device. The method includes following steps. A substrate including a front side and a back side is provided. An APD structure is then formed on the front side of the substrate and followed by patterning the back side of the substrate to form a plurality of heat sinks on the back side of the substrate and a plurality of recesses defined in between the heat sinks. Next, a plurality of reflecting islands are formed on bottoms of the recesses, respectively. 
         [0007]    According to the APD device provided by the present invention, at least an APD structure is formed on the front side of the substrate while the reflecting islands and the heat sinks are formed on the back sides of the substrate. Accordingly, lights passing through the APD structure are reflected back to it by the reflecting islands, and thus responsibility and sensitivity of the APD device are improved. More important, the heat sinks improve heat dissipation by increasing thermal paths. Consequently, impacts to the device performance due to overheat is diminished. 
         [0008]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIGS. 1-7  are schematic drawing illustrating a method for manufacturing an APD device provided by a first preferred embodiment of the present invention, wherein 
           [0010]      FIG. 2  is a schematic drawing in a step subsequent to  FIG. 1 , 
           [0011]      FIG. 3  is a schematic drawing in a step subsequent to  FIG. 2 , 
           [0012]      FIG. 4  is a schematic drawing in a step subsequent to  FIG. 3 , 
           [0013]      FIG. 5  is a schematic drawing in a step subsequent to  FIG. 4 , 
           [0014]      FIG. 6  is a schematic drawing in a step subsequent to  FIG. 5 , and 
           [0015]      FIG. 7  is a schematic drawing in a step subsequent to  FIG. 6 . 
           [0016]      FIGS. 8-11  are top views of the back side of the APD structures provided by different embodiments of the present invention, respectively. 
           [0017]      FIG. 12  is a schematic drawing illustrating an APD device provided by a second preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have been described in detail in order to avoid obscuring the invention. 
         [0019]    It will be understood that when an element is referred to as being “formed” on another element, it can be directly or indirectly, formed on the given element by growth, deposition, etch, attach, connect, or couple. And it will be understood that when an elements or a layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. 
         [0020]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the disclosure. 
         [0021]    Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper”, “in”, “on” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figures in turned over, elements described as “below” or “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
         [0022]    The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the inventions. As used herein, the singular form “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. 
         [0023]    Please refer to  FIGS. 1-7 , which are schematic drawings illustrating a method for manufacturing an APD device provided by a first preferred embodiment of the present invention. As shown in  FIG. 1 , according to the method for manufacturing the APD structure provided by the present invention, a substrate  100  including a front side  100 F and a back side  100 B is provided. In some embodiments of the present invention, the substrate  100  is preferably a silicon-on-insulator (hereinafter abbreviated as SOI) substrate, but not limited to this. It is well-known to those skilled in the art that the SOI substrate upwardly includes a silicon layer  102 , a bottom oxide (hereinafter abbreviated as BOX) layer  104 , and a semiconductor layer  106  such as a single crystalline silicon layer formed on the BOX layer  104 . Furthermore, in some embodiments of the present invention, the semiconductor layer  106  formed on the BOX layer  104  further includes an n-doped region  108 . It is noteworthy that a semiconductor mesa  110  is formed on the semiconductor layer  106 , and the semiconductor mesa  110  upwardly and sequentially includes an n-doped semiconductor layer  112 , an intrinsic semiconductor layer  114 , and a p-doped semiconductor layer  116  as shown in  FIG. 1 . In some embodiments of the present invention, a concentration of the n-doped semiconductor layer  112  is lower than a concentration of the n-doped region  108 . Additionally, the intrinsic semiconductor layer  114  is an undoped semiconductor layer. In other words, the intrinsic semiconductor layer  114  includes no conductive dopants. However, it should be easily realized by those skilled in the art that layers and concentration of the layers of the semiconductor mesa  110  can be modified and adjusted according to different product requirements. 
         [0024]    Please refer to  FIGS. 2 and 3 . Next, a patterned oxide layer  118  is formed on the front side  100 F of the substrate  100 . The patterned oxide layer  118  includes an opening  1180 , and the semiconductor mesa  110  is exposed on a bottom of the opening  1180  as shown in  FIG. 2 . Then, an epitaxial semiconductor layer  120  is formed in the opening  1180 . In some embodiments of the present invention, the epitaxial semiconductor layer  120  can be formed by a selective epitaxial growth (hereinafter abbreviated as SEG) method, but not limited to this. Consequently, the epitaxial semiconductor layer  120  formed in the opening  1180 , and the p-doped semiconductor layer  116 , the intrinsic semiconductor layer  114  and the n-doped semiconductor layer  112  of the semiconductor mesa  110  form an APD structure  130  as shown in  FIG. 3 . 
         [0025]    Please still refer to  FIG. 3 . After forming the epitaxial semiconductor layer  120  by the SEG method and thus constructing the APD structure  130 , a deposition process can be in-situ performed to form an amorphous silicon layer  122  on the front side  110 F of the substrate  100 . A thickness of the amorphous silicon layer  122  can be 1 angstrom (Å), but not limited to this. 
         [0026]    Please refer to  FIG. 4 . After forming the amorphous silicon layer  122 , a patterned protecting layer (not shown) is formed on the front side  100 F of the substrate  100 , and the patterned protecting layer covers and protects the semiconductor mesa  110 . Thereafter, an etching process is performed to remove a portion of the amorphous silicon layer  122  not covered and protected by the patterned protecting layer. Consequently, the semiconductor layer  106  and a portion of the n-doped region  108  are exposed and followed by performing an ion implantation. Thus, a heavily n-doped region  124  is formed in the exposed semiconductor layer  106 . In some embodiments of the present invention, a concentration of the heavily n-doped region  124  is larger than a concentration of the n-doped region  108 , and the concentration of the n-doped region  108  is larger than a concentration of the n-doped semiconductor layer  112  of the semiconductor mesa  110 . Please refer to  FIG. 4  still. After forming the heavily n-doped region  124 , another patterned protecting layer (not shown) is formed to cover and protect the APD structure  130  and the heavily n-doped region  124 . An etching process is then performed to remove the semiconductor layer  106  not covered by the patterned protecting layer such that the BOX layer  104  is exposed as shown in  FIG. 4 . 
         [0027]    Please refer to  FIG. 5 . Next, a dielectric layer  140  is formed on the front side  100 F of the substrate  100 . In some embodiments of the present invention, the dielectric layer  140  can be an interlayer dielectric (ILD) layer, but not limited to this. A plurality of openings  140 C are then formed in the dielectric layer  140 . Thus, the heavily n-doped region  124  and a portion of the amorphous silicon layer  122  formed on the epitaxial semiconductor layer  120  are exposed by the openings  140 C as shown in  FIG. 5 . It is noteworthy that a silicide process can be performed before forming the dielectric layer  140  or performed after forming the dielectric layer  140  and the openings  140 C. Thus metal silicides (not shown) are formed on surfaces of the heavily n-doped region  124  and the portion of the amorphous silicon layer  122  formed on the epitaxial semiconductor layer  120 . 
         [0028]    Please refer to  FIG. 6 . Next, a conductive structure  142  is formed in the openings  140 C, respectively. As shown in  FIG. 6 , some conductive structures  142  are electrically connected to APD structure  130 , and the other conductive structures  142  are electrically connected to the heavily n-doped region  124  in the n-doped region  108 . In some embodiments of the present invention, the conductive structures  142  electrically connected to the APD structure  130  are further electrically connected to a supply voltage VDD while the conductive structures  142  electrically connected to the heavily n-doped region  124  are further electrically connected to a ground voltage VSS. And in some embodiments of the present invention, the conductive structures  142  can be a first metal layer (Ml) of an interconnection, but not limited to this. After forming the conductive structures  142 , an anti-reflection layer  144  is formed on the front side  100 F of the substrate  100  to cover the APD structure  130  and the front side  100 F of the substrate  100 . 
         [0029]    Please refer to  FIG. 7 . After forming the APD structure  130 , the dielectric layer  140 , and the conductive structures  142 , a protecting layer and a carrier substrate (both not shown) are formed on the front side  100 F of the substrate  100 . Then, the substrate  100  is flipped and followed by patterning the back side  100 B of the substrate  100 . Consequently, the back side  100 B of the substrate  100  is patterned, thus a plurality of heat sinks  150  are formed on the back side  100 B of the substrate  100  and a plurality of recesses  152  are defined therebetween as shown in  FIG. 7 . It is noteworthy that the substrate  100  is patterned from the back side  100 B to the front side  100 F of the SOI substrate  100 . In other words, the silicon layer  102  of the SOI substrate  100  is etched and patterned such that the BOX layer  104  is exposed on bottoms of the recesses  152 . It should be easily realized by those skilled in the art that in some embodiments of the present invention, the silicon layer  102  is remained and thus exposed on the bottoms of the recesses  152  by modifying and adjusting parameters of the patterning step. 
         [0030]    Please still refer to  FIG. 7 . After forming the heat sinks  150  and the recesses  152  defined therebetween, a metal layer is formed on the bottoms of the recesses  152 , respectively. The metal layer respectively serves as a reflecting structure  160  for the APD structure  130 . As shown in  FIG. 7 , the metal layer in each recess  152  is referred as a reflecting island  160 . And a thickness of the heat sinks  150  is larger than a thickness of the reflecting islands  160 . Therefore the reflecting islands  160  are spaced apart from each other by the heat sinks  150 . Briefly speaking, the heat sinks  150  include a semiconductor material, and the semiconductor material is the same with at least a portion of the substrate  100  while the reflecting structures (the reflecting islands)  160  include metal materials. As mentioned above, since the heat sinks  150  are formed by patterning the silicon layer  102  of the SOI substrate  100 , the heat sinks  150  includes the semiconductor material the same with the silicon layer  102  of the substrate  100 . Consequently, an APD device  200  including the APD structure  130 , the reflecting structures  160 , and the heat sinks  150  is obtained, as shown in  FIG. 7 . 
         [0031]    Please refer to  FIGS. 8-11 , wherein  FIGS. 8-11  are top views of the back side of the APD structure  200  provided the present invention, and  FIG. 7  is a cross-sectional view taken along a line A-A′ of  FIGS. 8-11 . More important,  FIGS. 8-11  illustrate different embodiments for the heat sinks  150  and the reflecting islands  160 . As shown in  FIG. 8 , in an embodiment of the present invention, at least one reflecting island  160  is disposed correspondingly to a center of the APD device  200 , and as shown in  FIG. 7 , that reflecting island  160  is aligned with the APD structure  130 . And the heat sinks  150  surround the central reflecting island  160 . The heat sinks  150  include a radial pattern as shown in  FIG. 8 . It is noteworthy that the reflecting islands  160  are always spaced apart from each other by the heat sinks  150 . As shown in  FIG. 9 , in another embodiment of the present invention, the heat sinks  150  include a concentric circle pattern and the reflecting islands  160  are disposed in between each concentric circle and thus are spaced apart from each other by the heat sinks  150 . It is noteworthy that in the embodiment, at least a reflecting island  160  is preferably aligned with the APD structure  130 , as shown in  FIG. 7 . As shown in  FIG. 10 , in another embodiment of the present invention, the heat sinks  150  include a mesh pattern and the reflecting islands  160  are disposed in the mesh openings. And thus the reflecting islands  160  are spaced apart from each other by the heat sinks  150 . It is noteworthy that in the embodiment, at least a reflecting island  160  is preferably aligned with the APD structure  130 , as shown in  FIG. 7 . As shown in  FIG. 10 , in still another embodiment of the present invention, the heat sinks  150  include a radial pattern and the reflecting islands  160  are spaced apart from each other by the heat sinks  150 . 
         [0032]    Please refer to  FIG. 7  again. According to the APD device and the manufacturing method thereof provided by the present invention, the heat sinks  150  and the reflecting islands  160  are formed on the back side  100 B of the substrate  100  after forming the APD structure  130  on the front side  100 F of the substrate  100 . As shown in FOG.  7 , at least one of the reflecting islands  160  is preferably aligned with the APD structure  130 . Consequently, lights passing through the APD structure  130  are reflected and redirected back to the APD structure  130 , and thus responsibility and sensitivity of the APD device  200  are both improved at least 2 dBm, but not limited to this. More important, though the reflecting islands  160  increase light reflections and thus improve the responsibility and the sensitivity, it block the contact between the APD structure  130  and ambience air. Consequently, heat dissipation is reduced. However, due to the heat sinks  150 , thermal paths and contact areas between the APD device  200  and ambience air are increased. Therefore, heat dissipation is improved and overheat impacts to the device performance is diminished. 
         [0033]    Please refer to  FIG. 12 , which is a schematic drawing illustrating and APD device provided by a second preferred embodiment of the present invention. It is noteworthy that elements the same in the first and second preferred embodiments are designated by the same numerals. Furthermore, elements the same in the first and second preferred embodiments can include the same material and be formed by the same method, therefore those details are omitted in the interest of brevity. The difference between the first and the second embodiments is: After forming the heat sinks  150  and the recesses  152 , not only the reflecting islands  160  are formed on the bottoms of the recesses  152 , but also a plurality of reflecting layers  162  are formed on the back side  100 B of the substrate  100 . According to the preferred embodiment, the reflecting layers  162  cover sidewalls of the recesses  152  and top surfaces of the heat sinks  150  as shown in  FIG. 12 . Furthermore, the reflecting layers  162  contact the reflecting islands  160  and thus to a continuous reflecting film  160 R on the back side  100 B of the substrate  100 . 
         [0034]    According to the second embodiment, the reflecting islands  160  and the reflecting layers  162  form the continuous reflecting film  160 R, therefore the lights passing through the APD structure  130  are reflected and redirected back to the APD structure  130  by the continuous reflecting film  160 R while thermal paths are increased due to the heat sinks  150 . Consequently, the responsibility and the sensitivity of the APD device  200  are both improved and overheat impacts to the device performance is diminished. 
         [0035]    Briefly speaking, according to the APD device provided by the present invention, at least an APD structure is formed on the front side of the substrate while the reflecting islands and the heat sinks are formed on the back sides of the substrate. Accordingly, lights passing through the APD structure are reflected back to the APD structure by the reflecting islands and thus responsibility and sensitivity of the APD device are both improved. More important, the heat sinks improve heat dissipation. Consequently, impact to the device performance due to overheat is diminished. 
         [0036]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.