Abstract:
An integrated electrostatic discharge (ESD) protection circuitry for a signal electrode. Coupled in shunt between the signal electrode and the positive and negative power supply electrodes are opposing sets of multiple diodes coupled in series. Each set includes a diode across which is applied a nominal reverse bias voltage. These opposing reverse bias voltages are maintained at substantially constant predetermined nominal magnitudes in relation to the voltage at the signal electrode, thereby ensuring minimal leakage current via the signal electrode over the full dynamic range of the signal.

Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention relates to electrostatic discharge (ESD) protection circuits, and in particular, to ESD protection circuits with reduced leakage currents. 
     2. Related Art 
     As is well known, integrated circuits have many semiconductor devices formed on semiconductor chips mounted in packages having multiple pins or electrodes. An ESD event at one or more of the pins of the package can cause a current flow through one or more of the semiconductor devices with such magnitude as to significantly damage or destroy the device. This is particularly true for more sensitive devices such as metal oxide semiconductor (MOS) devices which typically have thin gate oxides. 
     As is also well known, ESD circuits are often formed with and connected to vulnerable electrodes so as to absorb energy from an ESD event, thereby preventing damage or destruction of semiconductor devices connected such electrode. 
     A problem that often occurs with such ESD protection circuits, however, is that the introduction of such circuitry creates additional sources of or paths for leakage currents. Such leakage currents can reduce signal-to-noise ratios and dynamic signal operating ranges. This can be particularly true for complementary MOS (CMOS) operational amplifiers with their high input impedances and low input bias currents. With ESD protection diodes connected to the input devices, the resulting leakage reverse bias currents can vary significantly over temperature and semiconductor fabrication processes. This results in circuits having relatively large limits on the input bias current specifications. 
     SUMMARY 
     In accordance with the presently claimed invention, an integrated electrostatic discharge (ESD) protection circuitry for a signal electrode is provided. Coupled in shunt between the signal electrode and the positive and negative power supply electrodes are opposing sets of multiple diodes coupled in series. Each set includes a diode across which is applied a nominal reverse bias voltage. These opposing reverse bias voltages are maintained at substantially constant predetermined nominal magnitudes in relation to the voltage at the signal electrode, thereby ensuring minimal leakage current via the signal electrode over the full dynamic range of the signal. 
     In accordance with one embodiment of the presently claimed invention, integrated electrostatic discharge (ESD) protection circuitry for a signal electrode, including: 
     first and second power supply electrodes to convey a power supply voltage; 
     differential amplifier circuitry including first and second input electrodes and an output electrode; 
     a first plurality of diodes coupled between the first input electrode and the first power supply electrode, and including first and second diodes coupled via a shared electrode; 
     a second plurality of diodes coupled between the first input electrode and the second power supply electrode, and including third and fourth diodes coupled via the output electrode; 
     a first resistance coupled between the shared electrode and the second input electrode; and 
     a second resistance coupled between the second input electrode and the output electrode. 
     In accordance with another embodiment of the presently claimed invention, integrated electrostatic discharge (ESD) protection circuitry for a signal electrode, including: 
     first and second power supply electrodes to convey a power supply voltage; 
     a signal electrode to convey a signal; 
     a first plurality of diodes coupled between the signal electrode and the first power supply electrode, and including first and second diodes coupled via a first shared electrode; 
     a second plurality of diodes coupled between the signal electrode and the second power supply electrode, and including third and fourth diodes coupled via a second shared electrode; 
     a plurality of resistances coupled between the first and second shared electrodes, and including first second resistances coupled via a third shared electrode; and 
     differential amplifier circuitry including first and second amplifier inputs and an amplifier output, with the first amplifier input coupled to the signal electrode, the second amplifier input coupled to the third shared electrode and the amplifier output coupled to the second shared electrode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram depicting ESD protection circuitry for a signal electrode in accordance with one embodiment of the presently claimed invention. 
         FIG. 2  is a schematic diagram illustrating the circuitry of  FIG. 1  in more detail. 
         FIGS. 3A and 3B  are graphs of input bias current versus common mode voltage based on test versions of the circuit of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. 
     Referring to  FIG. 1 , an ESD protection circuit in accordance with one embodiment of the presently claimed invention includes a first set (e.g., two) of diodes D 1   p , D 2   p  coupling the signal electrode  1   s  and the positive power supply electrode VDD, a second set (e.g., two) of diodes D 1   n , D 2   n  coupling the signal electrode  1   s  to the negative power supply electrode VSS/GND, a differential amplifier A 1  (e.g., an operational amplifier), and resistances R 1  R 2 , all interconnected substantially as shown. A current source P 1  can also be included to provide a source current Is (discussed in more detail below). The input signal, having a voltage Vin and current Iin, is conveyed via the signal electrode Is to host circuitry elsewhere within the integrated circuit (not shown). The diodes D 1   p , D 2   p , D 1   n , D 2   n  provide ESD protection for the signal electrode  1   s  in accordance with well known principles. The ESD protection circuitry, comprising the diodes D 1   p , D 2   p , D 1   n , D 2   n , the amplifier A 1  and resistances R 1 , R 2 , and preferably the current source P 1 , provides reverse biasing voltages Vb 1 , Vb 2  across the inner diodes D 1   p , D 1   n . This has the effect of matching the reverse bias currents Ip, In for these diodes D 1   p , D 1   n . Assuring negligible current into the MOS input of the host circuitry (not shown), as well as the amplifier A 1 , the input current Iin to the signal electrode  1   s  will be equal to the difference of the reverse bias currents Ip, In (in accordance with Kirchoff s Current Law). By measuring the voltages Vb 1 , Vb 2  across these diodes D 1   p , D 1   n , and verifying that they are at least substantially equal, it can be ensured that the input current Iin due to ESD device leakage is virtually zero. 
     Referring to  FIG. 2 , P-type MOS (PMOS) transistors P 3  and P 4 , and N-type MOS (NMOS) transistors N 1  and N 2  form the input stage of the amplifier A 1 , with NMOS transistor N 3  forming the output stage. Biasing in the form of a tail current It is provided by PMOS transistor P 2 , which can be biased by the same voltage Vbias as PMOS transistor P 1  that provides the source current Is. As discussed above, nominal reverse bias voltages Vb 1 , Vb 2  are maintained across the inner two diodes D 1   p , D 1   n  with the resistances R 1 , R 2  and negative feedback loop formed with the amplifier A 1 . 
     If the input voltage Vin increases, the gate voltage of transistor P 4  increases, thereby also causing the drain voltage of transistor P 4  to decrease. This decreasing voltage, which is also the gate voltage of transistor N 3 , causes the drain voltage of transistor N 3  to increase. This increase in voltage “pushes up” both the resistances R 1 , R 2 , i.e., causing the voltages at nodes  2   p ,  2  and  2   n  to increase relative to the circuit reference VSS/GND. Accordingly, the reverse bias voltages Vb 1 , Vb 2  across the inner diodes D 1   p , D 1   n  are maintained. Conversely, when the input voltage Vin decreases, the voltages at nodes  2   p ,  2 ,  2   n  are “pulled downs” in a similar manner. 
     The amplifier A 1  needed for this is simple in that it uses small devices. Notwithstanding the input offset voltage Vos, the resistances R 1 , R 12  can be sized such that the voltages Vf across them ensure that the two inner diodes D 1   p , D 1   n  are maintained in a reverse biased condition. The offset voltage Vos of the amplifier A 1  can cause asymmetric reverse bias currents Ip, In through the inner diodes D 1   p , D 1   n , thereby causing a higher input current Iin into the input node  1   s . However, if probe pads are included at nodes  1   p  and  1   n , then the voltages Vb 1 , Vb 2  across the diodes D 1   p , D 1   n  can be measured during production. If the measured voltages Vb 1 , Vb 2  are significantly different than the offset voltage Vos, and hence the input current in is too high, the unit can be rejected. A simple limit on the difference in measured voltages Vb 1 , Vb 2  can then be used to guarantee the input current In by design, thereby ensuring a higher quality product. 
     Assuming the voltages Vf across the resistors are fixed non-zero values, relationships among this voltage Vf, the diode bias voltages Vb 1 , Vb 2 , diode threshold voltage Vt and amplifier offset voltage Vos can be expressed as follows:
 
 Vb 1 /Vt =−( Vf+Vos )/ Vt   (1)
 
 Vb 2 /Vt =−( Vf−Vos )/ Vt   (2)
 
     With the use of the resistances R 1 , R 2 , the input current IinR can be expresses as follows:
 
 I in R=Ip−In   (3)
 
 I in R=Is ( e   Vp/Vt −1)− Is ( e   Vn/Vt −1)  (4)
 
 I in R=Is ( e   −(Vf+Vos)/Vt   −e   −(Vf−Vos)/Vt )  (5)
 
     Without the use of the resistances R 1 , R 2 , the input current Iin 0  can be expressed as follows:
 
 I in0 =Is ( e   −Vos/Vt   −e   Vos/Vt )  (6)
 
     The ratio of the input current with resistances IinR to the input current without resistances Iin 0  can then be expressed as follows: 
     
       
         
           
             
               
                 
                   
                     IinR 
                     
                       Iin 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       0 
                     
                   
                   = 
                   
                     
                       Is 
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                           ⅇ 
                           
                             
                               - 
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                             / 
                             Vt 
                           
                         
                         ⁡ 
                         
                           ( 
                           
                             
                               ⅇ 
                               
                                 
                                   - 
                                   Vos 
                                 
                                 / 
                                 Vt 
                               
                             
                             - 
                             
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                                 Vos 
                                 / 
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                       Is 
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                                 - 
                                 Vos 
                               
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                               Vos 
                               / 
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                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     IinR 
                     
                       Iin 
                       ⁢ 
                       
                           
                       
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                           - 
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                     1.0 
                   
                 
               
               
                 
                   ( 
                   8 
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     Hence, it can be seen that with the use of the resistances R 1 , R 2 , the leakage input current Iin will be less. 
     Referring to  FIGS. 3A and 3B , some test circuits were measured at elevated temperatures to compare input leakage current Iin of a circuit with conventional ESD protection (i.e., no amplifier providing constant reverse bias for the inner diodes D 1   p , D 1   n ) and an ESD protection circuit in accordance with the presently claimed invention. As can be seen, the leakage currents  30   a ,  30   b  for a conventional ESD protection circuit vary over a much wider range than the currents  31   a ,  31   b  for an ESD protection circuit in accordance with the presently claimed invention. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.