Abstract:
A semiconductor device fabrication method includes forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate; forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate; forming a first insulating film; forming a second insulating film; forming a mask having a pattern corresponding to the P-type semiconductor region; etching away the second insulating film by using the mask; removing the mask; and forming a first gate electrode sidewall insulating film and forming a second gate electrode sidewall insulating film.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2005-281537, filed on Sep. 28, 2005, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to a semiconductor device and a method of fabricating the same. 
         [0003]    Recently, the film thickness of a gate insulating film decreases as downsizing of MOSFETs advances, and this poses the problem that a gate leakage current increases. To suppress this gate leakage current, therefore, it is proposed to use a high-k film having a relative dielectric constant higher than that of a silicon oxide (SiO 2 ) film as a gate insulating film. An example of this high-k film is a hafnium silicate nitride (HfSiON) film. 
         [0004]    When a complementary MOS transistor (to be referred to as a CMOSFET hereinafter) including a PMOSFET and NMOSFET is to be formed, however, if this hafnium silicate nitride (HfSiON) film is used as a gate insulating film, the gate threshold voltage of the PMOSFET fluctuates more than that of the NMOSFET. 
         [0005]    In this case, a driving current flowing through a channel region reduces more in the PMOSFET than in the NMOSFET, so the drivability of the PMOSFET decreases. This produces a large difference in drivability between the PMOSFET and NMOSFET. 
         [0006]    A reference related to a CMOSFET using a high-k gate insulating film is as follows. 
         [0007]    Japanese Patent Laid-Open No. 2004-289061 
       SUMMARY OF THE INVENTION 
       [0008]    According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: 
         [0009]    forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate; 
         [0010]    forming a first insulating film on side surfaces of the first gate electrode and the first gate insulating film, and forming a second insulating film on side surfaces of the second gate electrode and the second gate insulating film; 
         [0011]    forming a mask having a pattern corresponding to the P-type semiconductor region; 
         [0012]    etching away the second insulating film by using the mask; 
         [0013]    removing the mask; and 
         [0014]    forming a first gate electrode sidewall insulating film on the side surfaces of the first insulating film, and forming a second gate electrode sidewall insulating film on the side surfaces of the second gate electrode and the second gate insulating film, thereby forming an interface insulating film in an interface between the second gate electrode and the second gate insulating film. 
         [0015]    According to one aspect of the invention, there is provided a semiconductor device comprising: 
         [0016]    a first gate insulating film formed on a P-type semiconductor region in a surface portion of a semiconductor substrate; 
         [0017]    a first gate electrode formed on said first gate insulating film; 
         [0018]    a first gate electrode sidewall insulating film formed on side surfaces of said first gate electrode and said first gate insulating film via an insulating film; 
         [0019]    an N-channel transistor having a first source region and a first drain region formed on two sides of a first channel region formed in a surface portion of said P-type semiconductor region below said first gate electrode; 
         [0020]    a second gate insulating film formed on an N-type semiconductor region in the surface portion of said semiconductor substrate; 
         [0021]    a second gate electrode formed on said second gate insulating film via an interface insulating film; 
         [0022]    a second gate electrode sidewall insulating film formed on side surfaces of said second gate electrode, said interface insulating film, and said second gate insulating film; and 
         [0023]    a P-channel transistor having a second source region and a second drain region formed on two sides of a second channel region formed in a surface portion of said N-type semiconductor region below said second gate electrode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIG. 1  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating a CMOSFET according to an embodiment of the present invention; 
           [0025]      FIG. 2  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0026]      FIG. 3  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0027]      FIG. 4  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0028]      FIG. 5  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0029]      FIG. 6  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0030]      FIG. 7  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0031]      FIG. 8  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0032]      FIG. 9  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0033]      FIG. 10  is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; 
           [0034]      FIG. 11  is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOSFET; and 
           [0035]      FIG. 12  is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOS FET. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0036]    An embodiment of the present invention will be described below with reference to the accompanying drawings. 
         [0037]      FIGS. 1 to 10  illustrate a method of fabricating a CMOSFET according to an embodiment of the present invention. First, a resist mask having a desired pattern is formed on a semiconductor substrate  10  by photolithography, and used as a mask to ion-implant boron (B), gallium (G), indium (In), or the like. 
         [0038]    Similarly, a resist mask having a desired pattern is formed on the semiconductor substrate  10 , and used as a mask to ion-implant phosphorus (P), arsenic (As), antimony (Sb), or the like. Annealing is then performed to form a P-type semiconductor region  20  and N-type semiconductor region  30  as shown in  FIG. 1 . Subsequently, as shown in  FIG. 2 , an element isolation insulating film  40  is formed in a desired region on the semiconductor substrate  10 . 
         [0039]    After that, an insulating film made of, e.g., a hafnium silicate nitride (HfSiON) film is formed on the surface of the semiconductor substrate  10 . Note that this insulating film is not limited to the hafnium silicate nitride film. That is, it is possible to use various types of high-k films having relative dielectric constants higher than that of a silicon oxide (SiO 2 ) film. Examples are a hafnium oxide (HfOx) film, a zirconium oxide (ZrOx) film, a silicate film of a hafnium oxide film, an aluminate film of a hafnium oxide film, a silicate film of a zirconium oxide film, an aluminate film of a zirconium oxide film, a silicate nitride film of a hafnium oxide film, an aluminate nitride film of a hafnium oxide film, a silicate nitride film of a zirconium oxide film, and an aluminate nitride film of a zirconium oxide film. 
         [0040]    Polysilicon is deposited on this insulating film by CVD or the like to form a polysilicon film. In this case, a polysilicon germanium film may also be formed by depositing polysilicon germanium on the insulating film. 
         [0041]    As shown in  FIG. 3 , the polysilicon film and hafnium silicate nitride (HfSiON) film are sequentially patterned by lithography and RIE, thereby forming a gate electrode  70  and gate insulating film  50  on the P-type semiconductor region  20 , and a gate electrode  80  and gate insulating film  60  on the N-type semiconductor region  30 . 
         [0042]    As shown in  FIG. 4 , a silicon nitride (SiN) film  90  about 2 nm thick is formed on the entire surface. As shown in  FIG. 5 , the silicon nitride (SiN) film  90  is removed by RIE except for the silicon nitride (SiN) film  90  formed on the side surfaces of the gate electrode  70  and gate insulating film  50 , and on the side surfaces of the gate electrode  80  and gate insulating film  60 . In this manner, offset spacers  100 A and  100 B are formed on the side surfaces of the gate electrode  70  and gate insulating film  50 , and offset spacers  110 A and  110 B are formed on the side surfaces of the gate electrode  80  and gate insulating film  60 . 
         [0043]    As shown in  FIG. 6 , an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region  20 , and annealing is so performed as to diffuse this phosphorus (P), thereby forming a shallow-junction, lightly doped source extension region  120 A and drain extension region  120 B. 
         [0044]    Also, a P-type dopant such as boron (B) is ion-implanted into the N-type semiconductor region  30 , and annealing is so performed as to diffuse this boron (B), thereby forming a shallow-junction, lightly doped source extension region  130 A and drain extension region  130 B. 
         [0045]    As shown in  FIG. 7 , the semiconductor substrate  10 , gate electrodes  70  and  80 , and offset spacers  100  and  110  are coated with a photoresist, and the photoresist is exposed and developed to form a resist mask  140  having a pattern which opens over the N-type semiconductor region  30 , thereby covering the P-type semiconductor region  20  with the resist mask  140 . 
         [0046]    The resist mask  140  is used as a mask to etch away the offset spacers  110 A and  110 B formed in the N-type semiconductor region  30 . 
         [0047]    Note that wet etching using hydrofluoric acid (HF) may also be performed instead of RIE. In this case, the offset spacers  110 A and  110 B may also be removed after they are changed into an oxynitride film or oxide film by radical oxidation or thermal oxidation. Alternatively, the source extension region  130 A and drain extension region  130 B may also be formed after the offset spacers  110 A and  110 B are removed. 
         [0048]    As shown in  FIG. 8 , after the resist mask  90  is removed, a silicon oxide (SiO 2 ) film made of, e.g., a TEOS (tetraethoxysilane) film is formed on the entire surface of the semiconductor substrate  10 . As shown in  FIG. 9 , this silicon oxide (SiO 2 ) film is etched by RIE to form gate electrode side walls  150 A and  150 B on the side surfaces of the offset spacers  100 A and  100 B, and gate electrode side walls  160 A and  160 B on the side surfaces of the gate electrode  80  and gate insulating film  60 . 
         [0049]    In this state, the gate electrode side walls  160 A and  160 B act on the interface between the gate electrode  80  and gate insulating film  60  formed on the N-type semiconductor region  30 , thereby forming a low-k interface insulating film (interface layer)  170  made of a silicon oxide (SiO 2 ) film about 2 to 3 nm thick in the interface between the gate electrode  80  and gate insulating film  60 . 
         [0050]    On the other hand, the offset spacers  100 A and  100 B are already formed on the side surfaces of the gate electrode  70  and gate insulating film  50  formed on the P-type semiconductor region  20 . Therefore, even when the gate electrode side walls  150 A and  150 B are formed, they do not act on the interface between the gate electrode  70  and gate insulating film  50 , so almost no interface insulating film forms. 
         [0051]    Although a silicon oxide film made of a TEOS film is used as the gate electrode side walls  150  and  160  in this embodiment, it is also possible to use any of various silicon oxide films such as HTO (High Temperature Oxide), BPSG (Borophosphosilicate Glass), PSG (Phosphosilicate Glass), and BSG (Boron-Silicate Glass). 
         [0052]    As shown in  FIG. 10 , an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region  20 , and annealing is so performed as to diffuse this phosphorus (P), thereby forming a source region  180 A and drain region  180 B. 
         [0053]    Also, a P-type dopant such as boron (B) is ion-implanted into the N-type semiconductor region  30 , and annealing is so performed as to diffuse this boron (B), thereby forming a source region  190 A and drain region  190 B. 
         [0054]    After a metal film made of, e.g., cobalt (Co), nickel (Ni), or platinum (Pt) is formed by sputtering, annealing is performed to form silicides  200 A to  200 C for reducing the parasitic resistance on the surface of the gate electrode  70  and in the surface portions of the source region  180 A and drain region  180 B, and form silicides  210 A to  210 C on the surface of the gate electrode  80  and in the surface portions of the source region  190 A and drain region  190 B. 
         [0055]    Subsequently, an interlayer dielectric film (not shown) is formed, and a wiring step is performed by forming contact plugs (not shown) in this interlayer dielectric film, thereby forming a CMOSFET  240  including an NMOSFET  220  and PMOSFET  230 . 
         [0056]    In the CMOSFET  240  fabricated by the above method, as shown in  FIG. 10 , the element isolation insulating film  40  is formed in the surface portion of the semiconductor substrate  10 . 
         [0057]    Near the central portion of the P-type semiconductor region  20  isolated by the element isolation insulating film  40 , the gate electrode  70  is formed via the gate insulating film  50  formed on the surface of the semiconductor substrate  10 . 
         [0058]    The gate electrode side walls  150 A and  150 B are formed on the side surfaces of the gate electrode  70  and gate insulating film  50  via the offset spacers  100 A and  100 B about 2 nm thick. Also, a channel region  250  is formed near the surface of the 
         [0059]    semiconductor substrate  10  below the gate electrode  70 . The source extension region  120 A and drain extension region  120 B are formed on the two ends of the channel region  250 . 
         [0060]    The source region  180 A is formed between the source extension region  120 A and an element isolation insulating film (not shown). The drain region  180 B is formed between the drain extension region  120 B and element isolation insulating film  40 . 
         [0061]    In addition, the silicides  200 A to  200 C for reducing the parasitic resistance are formed on the surface of the gate electrode  70  and on the surfaces of the source region  180 A and drain region  180 B. 
         [0062]    On the other hand, the gate electrode  80  is formed near the central portion of the N-type semiconductor region  30  via the gate insulating film  60  formed on the surface of the semiconductor substrate  10 , and the interface insulating film  170  made of a silicon oxide (SiO 2 ) film about 2 to 3 nm thick. 
         [0063]    The gate electrode side walls  160 A and  160 B are formed on the side surfaces of the gate electrode  80 , interface insulating film  170 , and gate insulating film  60 . Also, a channel region  260  is formed near the surface of the semiconductor substrate  10  below the gate electrode  80 . 
         [0064]    The source extension region  130 A and drain extension region  130 B are formed on the two ends of the channel region  260 . 
         [0065]    The source region  190 A is formed between the source extension region  130 A and element isolation insulating film  40 . 
         [0066]    The drain region  190 B is formed between the drain extension region  130 B and an element isolation insulating film (not shown). 
         [0067]    In addition, the silicides  210 A to  210 C for reducing the parasitic resistance are formed on the surface of the gate electrode  80  and on the surfaces of the source region  190 A and drain region  190 B. 
         [0068]      FIGS. 11 and 12  illustrate the current-voltage characteristics of the NMOSFET and PMOSFET forming the CMOSFET. In each of  FIGS. 11 and 12 , the abscissa indicates the gate voltage applied to the gate electrode, and the ordinate indicates the drain current (the driving current flowing through the channel region). 
         [0069]    As shown in  FIG. 11 , when a hafnium silicate nitride (HfSiON) film is used as the gate insulating film, the gate threshold voltage of the PMOSFET changes by about 0.6 V in the negative direction, but that of the NMOSFET changes only by about 0.2 V in the positive direction, compared to the case in which a silicon oxide (SiO 2 ) film is used as the gate insulating film. 
         [0070]    As described above, the driving current flowing through the channel region reduces more in the PMOSFET than in the NMOSFET, so the drivability of the PMOSFET decreases. This produces a large difference in drivability between the PMOSFET and NMOSFET. 
         [0071]    In this embodiment, therefore, the offset spacers  100 A and  100 B are formed on the side surfaces of the gate electrode  70  and gate insulating film  50  only in the NMOSFET  220 , and no offset spacers are formed in the PMOSFET  230 , thereby forming the interface insulating film  170  in the interface between the gate electrode  80  and gate insulating film  60  in the PMOSFET  230 . 
         [0072]    Negative fixed electric charge is generated in the interface insulating film  170 . When the interface insulating film  170  is formed, therefore, the gate threshold voltage of the PMOSFET  230  changes by about 0.16 V in the positive direction ( FIG. 12 ), compared to the case in which no interface insulating film is formed. 
         [0073]    As described above, when the interface insulating film  170  is formed, the driving current largely increases, and this improves the drivability of the PMOSFET  230 , compared to the case in which no interface insulating film is formed. Consequently, the difference in drivability between the NMOSFET  220  and PMOSFET  230  can be reduced. 
         [0074]    Accordingly, the semiconductor device and the method of fabricating the same according to the above embodiment can improve the drivability of a PMOSFET in a CMOSFET using a high-k gate insulating film. 
         [0075]    Note that the above embodiment is merely an example and does not limit the present invention. For example, it is also possible to form an N-type semiconductor region in the surface portion of a P-type semiconductor substrate, and a P-type semiconductor region in the surface portion of an N-type semiconductor substrate, instead of forming the P-type semiconductor region  20  and N-type semiconductor region  30  in the surface portion of the semiconductor substrate  10 .