Abstract:
In a computer or microprocessor-based system having a plurality of resources making memory requests of a plurality of banks of memory, a switch-based interconnect system allows multiple simultaneous connections between resources and memory banks, maximizing memory throughput and bandwidth concurrency. The invention is particularly useful in devices having embedded banks of memory, where there are no external constraints requiring use of a bus architecture, but can be used with discrete devices as well.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to memory flow control in a microprocessor-based system having embedded DRAM. More particularly, this invention relates to a switch-based controller for memory requests in a microprocessor-based system having multiple DRAM banks.  
           [0002]    It is becoming increasingly common to provide integrated circuit devices having both logic and DRAM memory on-board; such devices are known as “embedded DRAM” devices. Such devices can include complete or nearly complete microprocessor systems, with the microprocessor and other logic (e.g., coprocessors, I/O controllers, etc.), as well as multiple banks of DRAM, all included on the same chip or on chips within the same chipset.  
           [0003]    Those various logic and embedded DRAM components could communicate just as they do in systems in which they are provided as discrete devices—i.e., using a bus architecture. However, in a bus architecture, only one device can use the bus at a time, which causes a bottleneck that affects data throughput. Moreover, with embedded devices, there are no external interfaces that would constrain one to use a bus architecture. Therefore, a need exists for a faster system and method for communication between logic devices and DRAMs embedded therewith.  
         SUMMARY OF THE INVENTION  
         [0004]    In accordance with the present invention, the standard bus architecture for communicating between various banks of memory and various system resources is replaced by a switch-based architecture. The switch receives memory requests from system resources and relays each request to the appropriate bank of memory when that bank indicates that it is not busy. When the bank of memory returns the result of the request, the switch establishes a connection between that bank of memory and the system resource that made the request, as soon as that resource is also free. While the invention is particularly useful in systems in which the memory banks are embedded DRAM memory, it is also applicable where any one or more of the memory banks and other system resources are discrete devices.  
           [0005]    In order to facilitate the routing of requests and returned data by the switch to the appropriate memory bank or system resource, each request preferably includes both a source tag and a destination tag. The destination tag is applied to a request by the system resource making the request. The source tag also may be applied to the request by the system resource making the request, but alternatively may be applied by the switch, which knows the identity of the resource by virtue of the requestor port through which the system resource is attached to the switch.  
           [0006]    Similarly, each memory bank is attached to the switch through a respective memory port. When a memory bank returns the result of a memory request, the identity of the memory bank is preferably ascertained based on the memory port to which it is attached. The destination system resource for the result can be indicated by a destination tag applied by the local controller of the memory bank, or the switch can keep track of which memory requests have been routed to which memory banks and which resources made the requests, so that when a particular memory bank returns its result, the switch “knows” which system resource made the request that that memory bank was working on, and therefore to which system resource the result should be returned.  
           [0007]    Thus, in accordance with the invention, a computer system is provided having a plurality of banks of memory and a plurality of system resources that submit memory requests to the memory. The system is preferably a single chip having both logic and embedded memory, particularly DRAM memory. A switch interconnects the plurality of banks of memory and the plurality of system resources, and establishes communications between (a) a respective one of the resources, and (b) a respective one of the banks of memory of which the respective one of the resources makes a request. The connection is not established until the respective one of the resources and the respective one of the banks of memory are both available. The switch architecture allows multiple connections to exist between different memory port/requester port pairs, although at any one time, each memory port can be connected to only one requester port and vice-versa. 
       
    
    
     BRIEF DESCRIPTION OF THE INVENTION  
       [0008]    The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:  
         [0009]    [0009]FIG. 1 is a schematic representation of a system in accordance with the present invention;  
         [0010]    FIGS.  2 - 6  are schematic representations of various steps in the processing of a memory request by a system resource to a memory bank in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]    As described above, the present invention provides a switch-based interconnection between various banks of memory and various system resources, of the type that make memory requests, in a processor system or computer system. The invention is particularly advantageous in an embedded system in which at least some of the memory banks are banks of DRAM memory embedded in the same chip or chip set as the switch itself and at least one of the system resources. However, it presents advantages even in the case of systems where some or all of the system components are discrete.  
         [0012]    The primary advantage, whether in embedded, discrete or mixed systems, is that more than one memory/system resource pair can communicate at one time. Depending on the degree to which the switch is populated, and the relative numbers of resources and memory banks, it may be possible for every resource to be communicating with a memory bank simultaneously. If, as is preferably the case, the switch is fully populated—i.e., every requestor port can communicate with every memory port and vice-versa—then if the numbers of memory banks and resources are equal, every resource can communicate with every memory bank simultaneously. If the numbers are unequal, then for whichever group (i.e., memory banks vs. resources) the number is lower, all members of that group can communicate with a member of the other group simultaneously. This contrasts with a system that uses a bus in which only one resource/memory bank pair can communicate at any one time, and only when no other type of system resource is using the bus.  
         [0013]    The result is a high-bandwidth interactive structure that maximizes data throughput and bandwidth concurrency. Moreover, the structure is easily scaled to systems having any number of memory banks and any number of system resources, simply by increasing the number of ports on the switch.  
         [0014]    In accordance with the invention, when a system resource makes a memory request directed to a certain bank of memory, the memory request is tagged by the requesting system resource with a tag identifying the destination memory bank. The tag may be a separate message accompanying the request, or may be a field within the request. The request is transmitted to the switch via the dedicated connection between the system resource and a requester port, dedicated to that resource, on the switch. A source tag preferably is also attached to the request, either by the resource issuing the request or by the switch, as discussed below.  
         [0015]    Next, the switch checks the destination tag of the request to see which memory bank it is for. The system then queues the request and waits until that memory bank is ready to accept requests, as signalled to the switch by the dropping of the memory bank&#39;s “request busy” indicator. At that time, the switch routes the request to the memory bank. The switch may or may not keep a record of the request as being pending, and may or may not include the source and request tags when it sends the request to the memory bank.  
         [0016]    Specifically, if the switch sends the source and destination tags (especially the source tag) to the memory bank with the request, then the memory bank, or its local controller, can send the source tag back with the resulting data as a destination tag, and the switch can use that destination tag to identify the requester to which the data should be returned. On the other hand, the switch could keep a record of which memory banks have been sent requests and which system resources are the requestors of those requests. Assuming that a particular memory bank can only respond to one request at a time, when a memory bank returns data, the switch can “know” from its record which resource made the original request, and return the data accordingly.  
         [0017]    If the memory bank accepts the request, it sends an acknowledgment signal to the switch which returns the acknowledgment to the requesting resource, which then “knows” its request has been accepted. Otherwise, the resource might repeat the request periodically until it is acknowledged.  
         [0018]    To return the data once the memory bank has signalled that is ready to do so by deactivating its data busy indicator (meaning that it is no longer busy retrieving the data, and therefore is ready to return it), the switch checks to see if the data ready indicator of the requesting resource is active (meaning that is ready to accept data). If the data ready indicator is not active, the response is queued and the switch waits until the data ready indicator becomes active. Once the data ready indicator of the requesting resource is active, the switch establishes a connection between the memory port serving the memory bank to which the request was made and the requester port serving the system resource that made the request, and the data are returned to the requesting resource. Many such connections can be active at once, allowing multiple simultaneous transfers of data from individual memory banks to different system resources that have requested data.  
         [0019]    In accordance with the invention, the source tag may be attached to memory requests by the system resource that makes the request, which can be given sufficient awareness of its own identity to be able to attach the tags. Alternatively, the switch could assign the source tag, based on its “knowledge” of which requestor port the request was received on. As long as each requester port serves only one system resource, it is sufficient for the switch to “know” which port to return the data to once it has been retrieved. However, the destination tag would have to be applied by the requesting resource; there is no way the switch could know on its own which memory bank is being queried by the requesting resource.  
         [0020]    Similarly, when data are being returned by a memory bank, the local controller of the memory bank could apply a source and destination tag, but both tags could also be applied by the switch. In this case, as long as each memory port serves only one memory bank, the switch knows which memory bank is returning the data, and can apply a source tag to the data. And if the switch has kept a record as described above of which memory bank it has sent each request to and where that request originated, it also can apply a destination tag to the data. Of course, in both of those cases, it is actually unnecessary to apply the tags, because the switch can merely set up the connection based on its stored record, once the busy indicators of the memory bank and the requesting resource show that both are ready to return and accept the data, respectively.  
         [0021]    Indeed, a source tag on data being returned is unnecessary unless the destination system resource that originally requested the data has outstanding requests to more than one memory bank. Otherwise, it is sufficient that the data is tagged with the identification of the destination system resource; that resource will “know” that the returned data are in response to the only outstanding request it has pending. Preferably, however, the present invention accommodates system resources that can have multiple requests outstanding, because multiple requestor/memory bank pairs may be active at once. If one memory bank of which a particular resource has made a request is busy dealing with another resource, then the particular resource can deal with a different memory bank of which it has also made a request.  
         [0022]    The invention will now be described with reference to FIGS.  1 - 6 .  
         [0023]    A memory control system  10  according to the present invention may be used, e.g., in a personal computer, server or workstation. Memory control system  10  preferably includes a plurality of banks  11 ,  12 ,  13 ,  14  of memory (preferably DRAM memory), each having its own respective local controller or slave  110 ,  120 ,  130 ,  140 . System  10  also preferably includes a multi-port memory control switch  15  having a plurality of memory ports  16  at least equal in number to the number of memory banks  11 ,  12 ,  13 ,  14 . Memory control switch  15  also has a plurality of requester ports  17  through which it interfaces with system resources  18 ,  19 ,  100 , which issue memory requests and receive the resulting data. It should be noted that while the primary functions of system resources  18 ,  19 ,  100  are not memory control—e.g., in a computer system each could be an input/output device, an arithmetic logic unit, etc., or even the central processing unit (CPU) itself—resources  18 ,  19 ,  100  are considered part of memory control system  10  because the flow of memory requests is controlled in part by tags that they apply to requests and by how they react to tags that are included in replies to requests that they have made, and they have the ability to pace data by how they assert or deassert their respective data ready and/or data busy indicators.  
         [0024]    In one embodiment of the invention, each of requesting system resources  18 ,  19 ,  100  preferably has a unique identification code. In this embodiment, when one of system resources  18 ,  19   100  makes a memory request, it preferably includes that unique identification code in the request—preferably, e.g., as a distinct field within the same message as the request—as a source tag, preferably along with a destination tag identifying the appropriate one of memory banks  11 ,  12 ,  13 ,  14  as the destination of the request. The request preferably is passed along to switch  15  through one of requestor ports  17 , and then through the appropriate one of memory ports  16  to the desired memory bank  11 ,  12 ,  13 ,  14 .  
         [0025]    According to this embodiment, each memory bank  11 ,  12 ,  13 ,  14  preferably also has a unique identification code, and preferably it is that code which is used by the requesting resource  18 ,  19 ,  100  in the destination tag. When the desired memory bank  11 ,  12 ,  13 ,  14  has retrieved the data specified in the request, it preferably sends the data back to the requesting resource  18 ,  19 ,  100  through switch  15 , attaching a source tag including its own unique identification code (what was the destination tag in the original request), and a destination tag including the unique identification code of the requesting resource (what was the source tag in the original request).  
         [0026]    For purposes of both source and destination tags, each memory bank  11 ,  12 ,  13 ,  14 , and resource  18 ,  19 ,  100  could be assigned an identification code that is used in those tags. Alternatively, each memory bank  11 ,  12 ,  13 ,  14 , and resource  18 ,  19 ,  100  could be known by the number of the memory port  16  or requester port  17  to which it is attached. This latter alternative is particularly (but not exclusively) suited to an embodiment where switch  15  keeps track of which requests are pending at which memory bank and who the requester is, or to an embodiment wherein the switch uses the port data to assign source and/or destination tags.  
         [0027]    FIGS.  2 - 6  show the interaction between one system resource  20  (which could be any of system resources  18 ,  19 ,  100 ) and one memory bank  21  (which could be any one of memory banks  11 ,  12 ,  13 ,  14 ) through switch  15 .  
         [0028]    As seen in FIG. 1, switch  15  preferably includes a fully populated set of interconnections  150  between memory ports  16  and requestor ports  17 , so that any memory port can communicate with any requester port and vice-versa. Switch  15  preferably also includes logic  151  and memory  152  for keeping track of and controlling the flow of memory requests and responses to those requests. A request  22  issued by system resource  20  preferably includes three fields  220 ,  221 ,  222 , respectively containing the source tag (indicated as “SS”), the destination tag (“DD”) and the request itself (“RRRR”). In this case, the destination tag has been applied by system resource  20 , while the source tag can be applied by either system resource  20  or by switch  15  based on the identity of requester port  23  through which resource  20  is connected to switch  15 .  
         [0029]    In FIG. 3, switch  15  is holding request  22  in memory  152  while logic  151  ascertains the status of the request busy indicator  30  of memory bank  21  (status not shown in this drawing). In FIG. 4, logic  151  ascertains that request busy indicator  30  is not asserted (memory bank  21  is not busy), either because indicator  30  was not asserted when request  22  arrived, or because indicator  30  was asserted when request  22  arrived, but switch  15  has held request  22  until indicator  30  has been deasserted.  
         [0030]    In FIG. 5, local controller  210  of memory bank  21  has accepted request  22 , asserting request busy indicator  30  as it works to fulfill request  22 , and issuing an acknowledgment signal (ACK)  50  which switch  15  returns to resource  20 .  
         [0031]    Switch  15  stores in memory  152  the fact that memory bank  21  is working on a request for resource  20  (memory  152  may also be storing information regarding other requests being processed by other memory banks for other system resources). During this time, if system resource  20  is able to perform other operations, it may issue additional memory requests (not shown); otherwise system resource  20  must wait idly until memory bank  21  fulfills request  22 . In the latter case, data ready indicator  51  of resource  20  will be asserted, meaning that resource  20  is ready to receive data. In the former case, data ready indicator  51  may be deasserted during other operations as resource  20  is occupied with those other operations and temporarily unable to receive the data requested in request  22 .  
         [0032]    In FIG. 6, memory bank  21  has retrieved the data requested by resource  20  in request  22 , and signals its readiness to return the requested data to resource  20  by asserting its data ready indicator  60  and deasserting its data busy indicator  30 . The message  61  including the retrieved data may have a format similar to request  22 , including three fields  610 ,  611 ,  612 , respectively containing the source tag (indicated as “SS”), the destination tag (“DD”) and the data themselves (“IIII”). In this transmission, memory bank  21  is the “source” and resource  20  is the “destination.” 
         [0033]    The source and destination tags  610 ,  611  can be applied by the local memory controller  210  based on the information contained in the original request  22 . Alternatively, if each memory bank  21  is capable of responding to only one request at a time, then if logic  151  of switch  15  has stored in memory  152  the fact that memory bank  21  is working on a request for resource  20 , then upon receipt of data from memory bank  21 , logic  151  “knows” that they come from memory bank  21  and must be intended for resource  20 , and can apply the source and destination tags  610 ,  611 .  
         [0034]    In fact, logic  151  can simply set switch  15  to establish a connection between memory bank  21  and resource  20  without applying any source or destination tag at all, assuming that resource  20  is not capable of having more than one outstanding data request, meaning that when switch  15  establishes a connection and resource  20  receives data, there will not be any ambiguity as to where the data come from. Even if resource  20  can have multiple requests outstanding, switch  15  can set up a connection and apply source tag  610  without a destination tag  611 , because resource  20  does not need to know that it is the destination once the connection has been set up.  
         [0035]    Similarly, it may be that resource  20  cannot perform other functions while awaiting fulfillment of request  22 , but each memory bank  21  can handle multiple requests  22 . In such a case, local memory controller  210  can apply a destination tag  611  but can omit source tag  610 , because switch  15  cannot know without destination tag  611  which of several requests being handled by memory bank  21  is being responded to, and therefore cannot determine the destination resource  20  on its own, but resource  20  can only have one outstanding request and therefore does not need to be told which memory bank has sent the requested data.  
         [0036]    Other combinations are possible. For example, even if resource  20  can have multiple outstanding requests, local controller  210  can apply a destination tag  611  (because switch  15  cannot know which of several requests being handled by memory bank  21  is being responded to, and therefore cannot determine the destination resource  20  on its own) but can omit source tag  610 , and then logic  151  of switch  15  can apply the source tag  610  based on its “knowledge,” by virtue of which memory port  16  the response comes from, of the identity of memory bank  21 .  
         [0037]    Preferably, the requesting resource  20  returns an acknowledgment signal to memory bank  21  upon receiving the requested data. This allows memory bank  21  to mark the request as fulfilled and move on to other requests. If memory bank  21  does not receive an acknowledgment from resource  20 , it may queue the requested data in a buffer (not shown) for later retransmission while it moves on to other requests, or it may wait and retransmit the data at set intervals. While it is waiting to retransmit the data, local memory controller  210  would keep its data busy indicator  30  to prevent being disturbed by new requests. Similarly, controller  210  could inhibit the issuance of a column address strobe (CAS) signal, thereby preventing the reading of any other data from memory bank  21 , until receipt of the retrieved data is acknowledged by resource  20 .  
         [0038]    Although the system  10  as shown in FIG. 1 includes three system resources and four memory banks, any number of resources and memory banks can be included.  
         [0039]    In addition, although FIGS.  2 - 6  have been described in connection with a single transaction between system resource  20  and memory bank  21 , multiple such transactions can occur simultaneously, among unique pairs of system resources memory banks. Accordingly, a system according to the invention allows faster communications between a system resources and memory banks in a computer or processor system than is possible in a bus architecture.  
         [0040]    One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.