Abstract:
An up/down counter within a phase locked loop is gated to count high frequency clock pulses during the first cycle of the input signal. Upon detection of a transition in the input signal indicating the end of the first cycle, the direction of the count is reversed until the count is reduced to zero, thereby assuring equal widths for the first and second half cycles of each output cycle. The system may be implemented with or without a voltage controlled oscillator. In the latter implementation, the count in the up/down counter at the time of a reversal in the count direction is compared with the count in a preset counter. A difference counter compares the differences in a count in the two counters and adjusts the count in the preset counter to match that in the up/down counter at the time of transition. The widths of the successive cycles, rather than half cycles, may be made by doubling the output frequency relative to the input frequency.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to phase tracking devices that dynamically track the phase or frequency of an input signal within a given bandwidth as in the case of a phase lock loop. More particularly, the invention relates to a phase tracking device that maintains a constant duty cycle for the half cycles within each complete cycle despite rapid changes in the input frequency being tracked. 
     2. Description of the Prior Art 
     Various phase lock loops are known. A typical phase lock loop utilizes a voltage controllable oscillator (VC0) whose output frequency is controlled by a control voltage. A phase detector compares the phase difference between the signal from the VCO and the signal being tracked and provides an output signal proportional to the phases of the two signals. The output signal from the phase detector is applied to the frequency controlling input of the VCO and adjusts the frequency of the VCO until the phase difference between the two signals is zero or another desired value. The VCO will then track any changes in the frequency of the input signal. However, if the input frequency has a step change, the output of the phase lock loop will slew over to the new frequency with a continuously changing frequency until the loop settles. The continuously changing frequency of the phase lock loop during the slewing period will result in a waveformat the output of the phase lock loop that does not have a 50% duty cycle. For example, if the phase lock loop is being utilized as a demodulator, it is important that the phase lock loop signal applied to the phase detector and compared with the input signal have an exact 50% duty cycle. If the first half cycle is not equal to the second half cycle, then the demodulated output will contain rectified information, such as a DC offset, in addition to the desired AC signal information. 
     SUMMARY 
     It is an object of the present invention to provide a signal wherein each cycle has equal width half cycles. 
     It is another object of the present invention to provide a phase lock loop having a signal wherein two successive cycles are of equal width. 
     It is yet another object of the present invention to provide a phase lock loop type of circuit that provides a signal having equal width half cycles without the use of a voltage controlled oscillator. 
     In accordance with a preferred embodiment of the invention, an up/down counter is connected inside the loop of a phase lock loop. The output signal from the voltage controlled oscillator (VCO) controls a gate to the up/down counter and causes the up/down counter to count high frequency clock pulses during the first half of each cycle of the VCO output signal. When a transition in the VCO signal is detected, the counting direction of the up/down counter is reversed and the counter is allowed to count down to zero. When underflow occurs, counting is again resumed in the up direction. Consequently, since the width of the second half cycle was determined by the width of the first half cycle, the widths of the two half cycles are equal. The up/down control signal to the up/down counter is then divided by two and applied to the phase detector rather than the output of the VCO as is conventionally done. In another embodiment, the VCO is eliminated and the up/down counter is driven directly by the input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     These and other objects and advantages of the present invention will become readily apparent upon consideration of the following detailed description and attached drawing, wherein: 
     FIG. 1 is a schematic block diagram of the invention; 
     FIG. 2 is a timing diagram illustrating the operation of the circuit of FIG. 1; 
     FIG. 3 is a schematic block diagram illustrating an embodiment of the invention that does not utilize a voltage controlled oscillator; and 
     FIG. 4 is a timing diagram illustrating the operation of the circuit of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the drawing, with particular attention to FIG. 1, there is shown a block diagram of the precision duty cycle phase lock loop according to the invention generally designated by the reference numeral 10. The loop 10 includes an input port 12 for receiving an input signal dividing by 2 and applying it to a phase detector 14. The output of the phase detector 14 is applied to an amplifier 16 that amplifies the phase detector signal and applies it to a voltage controlled oscillator 18 to control the frequency of the output signal from the voltage controlled oscillator 18. 
     In a standard phase lock loop, the output signal from the voltage controlled oscillator 18 would be fed back to the phase detector 14 and the phase detector 14 would provide an output signal representative of the phase difference between the signal from the voltage controlled oscillator 18 and the input signal received at the input port 12. The output voltage of the phase detector would be amplified by the amplifier 16 and applied to the voltage controlled oscillator 18 to lock the phase of the output signal from the voltage controlled oscillator 18 to the phase of the signal received at the input port 12. However, such a system does not provide equal width output pulses from the VCO 18 during rapid changes or step changes in the frequency of the input signal applied to the port 12. Consequently, circuitry including a bi-directional counter, commonly known as an up/down counter, such as a counter 20, an D-flip-flop 22, gate logic 24, an inverting amplifier 26 and a divide-by-two circuit 28 are provided to equalize the half cycles. The output of the divide-by-two circuit 28, which receives the up/down commands applied to the up/down counter 20 is applied to the phase detector 14. 
     In operation, the output of the VCO 18 is connected to an input of the D-flip-flop 22 that synchronizes the transitions in the VCO signal to the clock signal and is used to control the gate logic circuit 24 to control the counting of clock pulses by the bi-directional or up/down counter 20. Typically, the frequency of the clock pulses is substantially higher than that of the output signal from the VCO 18, for example, the output of the VCO 18 may have an output frequency on the order of 1200 Hz while the clock frequency may be on the order of 30 MHz. The VCO controls the gate logic 24 to cause the gate logic 24 to cause the up/down counter to count clock pulses during one cycle of the VCO signal and after one cycle has been completed, to count down until an underflow signal is generated. Specifically, clock pulses are counted by the up/down counter 20 during the one full cycle from the VCO 18. The clock pulses are counted until the output of the VCO 18 completes a full cycle at which point the gate logic 24 reverses the direction of the count and the up/down counter counts down until the count is reduced to zero and underflow occurs. The underflow signal from the up/down counter 20 is then applied to the gate logic 24, which again reverses the count direction of the up/down counter 20 and the cycle is repeated. The output from the gate logic 24 that controls the direction of count of the up/down counter is a signal that has a frequency equal to the frequency of the input signal at the input port 12. This signal is inverted by the inverter 26 and divided by two by the divider 28 and applied to the phase detector 14. Thus, phase detector 14 is supplied with a signal having a 90° phase shift to align the output f 0  phase to the input f in  phase, but f 0  has equal first and second half cycles. 
     It should also be noted that the up/down counter 20 can also be pre-loaded with a predetermined number that is counted down during a full cycle of the VCO signal and then counted back up to the predetermined number at which point &#34;underflow&#34; occurs. Thus, it should be understood that the term &#34;underflow&#34; is intended to cover both of the above-described cases. 
     The operation of the circuit of FIG. 1 is readily understood from the timing diagram of FIG. 2. The input signal to the input port 12 is illustrated as the waveform 30 of FIG. 2A. This input signal FIG. 2B is divided by 2 as shown in FIG. 2B. The VCO 18 operates at a frequency of four times that of its input signal as shown by the graph 32 in FIG. 2C. The VCO signal triggers a change in the up/down counter during each rising edge of the VCO signal as illustrated in graph 34 of FIG. 2D. The underflow signal triggers the up/down signal in the opposite direction upon each occurrence thereof as shown by the graph 36 of FIG. 2E. Thus, the up/down signal is alternately toggled by the rising edge of the VCO signal and by the underflow signal. Thus, the frequency of the up/down signal 34 is one-half the frequency of the VCO signal or twice the frequency of the VCO input signal FIG. 2B and corresponds to one complete up/down count cycle of the counter 20 as illustrated by the graph 40 in FIG. 2G. The up/down signal is then divided by two by the divider 28 and results in the f det  signal 38 of FIG. 2F which has a frequency f det  that is one half the frequency as the frequency of the input signal f in  and a width corresponding to a complete up/down cycle of the counter 20. 
     FIG. 3 shows an equal period demodulator that provides an equal period output signal as does the circuit of FIG. 1. However, the circuit of FIG. 3 does not require a voltage controlled oscillator. The circuit of FIG. 3 operates on the principal that the approximate period of the input signal is known. A count value corresponding to this period is input into a preset counter from a stored reference count. The input signal is applied to an up/down counter that counts up during the first half cycle and counts down until underflow is achieved in the manner previously discussed. The maximum count in the up/down counter which represents the width of the first half cycle is compared with the count in the preset counter and a difference in the two counts is taken. If there is a non-zero difference, the difference is divided by two and the preset counter is adjusted by one-half the difference. 
     Referring to FIG. 3, a preset counter 50 is loaded with a count representative of the approximate width of one-half cycle of the input signal. The preset count may be loaded in from an external computer or may be a default condition whereby the preset counter returns to the preset count upon a reset or an interruption of power. An up/down counter 52 receives the input signal and a comparator 54 compares the counts in the counters 50 and 52. A set/reset flip-flop 56 and a D-flip-flop 58 control the application of the input signal to the up/down counter. A difference counter 60 that is enabled by an exclusive OR gate 62 takes the difference between the counts in the up/down counter 52 and the preset counter 50, divides it by two by shifting the count one stage to the right as indicated by the line 64 and stores in counter 61 (one cycle) and adjusts the preset counter 50 using adder 53 by adding the current count in 60 and subtracting one-half count (n-1) delayed in 61 to make the count in the preset counter more closely match the count in the up/down counter 52. This delayed count 61 stabilizes the preset counter value, a similar scheme may be used in the system of FIG. 1. Alternatively, one half of the full count error 60 can be added to the preset 50 while one-quarter of 60 (delay one cycle) is subtracted the next two consecutive cycles. 
     In operation, the input signal is applied to the divide by 2 flip-flop 51 then to the D input of the D-flip-flop 58 and upon receipt of the next clock pulse, the input signal is transferred to the Q output of the D-flip-flop 58. Thus, the function of the D-flip-flop 58 is to synchronize the input signal to the clock to permit an accurate count by the up/down counter 52. The Q output of the D flip-flop 58 is applied to the set input of the set/reset flip-flop 56. When the flip-flop 56 is set, a high appears at its Q output and the up/down counter begins to count up. The counter continues to count up until the comparator 54 indicates that the counts in the two counters are equal and resets the set/reset flip-flop 56. When the flip-flop 56 is reset, the counter 52 will begin counting down until an underflow condition is reached. If the first half cycle of the input signal is not wide enough to cause the count in the up/down counter 52 to reach the count in the preset counter 50, the direction of the count will be reversed by the transition in the input signal. The Q output of the flip-flop 66, f o , has the same frequency as the input signal, f in , but has equal period half cycles because the period of each second half cycle is determined by the maximum value of the count in the up/down counter which is in turn determined by the period of each first half cycle. 
     An exclusive OR gate 62 receives the Q output from the flip-flop 58 and the underflow signal from the up/down counter 52 and enables the difference counter 60 to count clock pulses during the time interval between the transition of the Q signal and the generation of the underflow signal. The count obtained in the difference counter during the time between the transition of the Q output of the flip-flop 58 and the underflow is divided by two by shifting the contents of the counter one stage to the right beyond the line 64, and a count equal to half the difference in the difference counter is applied to the delay counter 61 to adjust the count therein as described before. If the transition in the input signal is ahead of the underflow signal, the number is subtracted from the preset value. If the underflow signal is ahead of the input signal transition, half the count in the difference counter is added to the preset value. 
     As described above, the frequency of the f o  signal is the same as the frequency of the input signal f in , but the periods of the first and second half cycles of the f o  signal are equal. This is accomplished by the flip-flop 66 that provides a f o  signal at its Q output. This is accomplished by the flip-flop 66 that is set by an OR gate 68 that receives the equal signal (EQ) and the underflow signal (UF) and sets the flip-flop 66 when either the EQ or the UF signal occurs. The flip-flop 66 is reset by the comparator 54 that provides an EQ/2 signal that has a period of onehalf of the EQ signal. The EQ/2 signal is readily obtained from the comparator 54 by shifting the sampling point of the comparator 54 one stage to the right. 
     The timing diagram for the circuit of FIG. 3 is illustrated in FIG. 4. The graph 70 of FIG. 4A shows the input signal. FIG. 4B shows the input signal divided by two. Graph 72 of FIG. 4C shows the EQ signal that is produced by the comparator 54 when the counts in the up/down counter 52 and the preset counter 50 are equal. Graph 74 in FIG. 4D shows the underflow pulses produced each time the up/down counter 52 underflows. The graph 76 in FIG. 4E shows the EQ/2 signal. Graph 78 in FIG. 4F shows the set signal that is generated by the OR gate 68 in response to a UF or EQ input. Graph 80 in FIG. 4G shows an equal period output signal at the frequency of the input signal that is obtained by setting a set/reset flip-flop by an OR of the EQ and underflow signals and resetting it with the EQ/2 signal. 
     Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.