Abstract:
A memory block has an increased quantity of memory cells while keeping the erase block the same size. The memory block is broken down into at least two memory sub-blocks. While one sub-block is biased with erase voltages, the other sub-block or shadow block is biased with erase inhibit voltages. For wear leveling purposes, the shadow block only experiences a predetermined quantity of program/erase cycles that is less than the maximum experienced by the normal memory sub-block.

Description:
TECHNICAL FIELD OF THE INVENTION  
       [0001]     The present invention relates generally to memory devices and in particular the present invention relates to erasing flash memory devices.  
       BACKGROUND OF THE INVENTION  
       [0002]     Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.  
         [0003]     A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. Each of the cells can be electrically programmed on a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation.  
         [0004]      FIG. 1  illustrates a simplified schematic diagram of a NAND flash memory array. The memory array of  FIG. 1 , for purposes of clarity, does not show all of the elements typically required in a memory array. For example, only three bit lines are shown (BL 1 , BL 2 , and BL 3 ) when the number of bit lines required actually depends upon the memory density. The bit lines are subsequently referred to as (BL 1 -BLN).  
         [0005]     The array is comprised of an array of floating gate cells  101  arranged in series columns  103 ,  104 ,  105 . Each of the floating gate cells  101  are coupled drain to source in each series chain  103 ,  104 ,  105 . A word line (WL 0 -WL 31 ) that spans across multiple series strings  103 ,  104 ,  105  is coupled to the control gates of every floating gate cell in a row in order to control their operation. The bit lines (BL 1 -BLN) are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.  
         [0006]     In operation, the word lines (WL 0 -WL 31 ) select the individual floating gate memory cells in the series chain  103 ,  104 ,  105  to be written to or read from and operate the remaining floating gate memory cells in each series string  103 ,  104 ,  105  in a pass through mode. Each series string  103 ,  104 ,  105  of floating gate memory cells is coupled to a source line  106  by a source select gate  115 ,  116 ,  117  and to an individual bit line (BL 1 -BLN) by a drain select gate  111 ,  112 ,  113 . The source select gates  115 ,  116 ,  117  are controlled by a source select gate control line SG(S)  118  coupled to their control gates. The drain select gates  111 ,  112 ,  113  are controlled by a drain select gate control line SG(D)  114 .  
         [0007]     The memory cells are usually grouped into memory blocks. A block is typically defined by the total number of bits per word line multiplied by the total number of cells per string. A block is further broken down into pages. A memory block is typically comprised of 64 pages.  
         [0008]     During an erase operation, all of the cells of the memory block are erased at the same time by biasing the gates of the block being erased at 0V while the tub (i.e., portion of the substrate in which the cells are fabricated) and the source are biased at 20V. The electric field that is oriented with the minus side from the floating gate and the positive side from the body or substrate would attract the electrons off of the floating gate, thus erasing the cell. Typical prior art memory designs let the word lines of unselected blocks float so that coupling from the substrate charges up all of the unselected word lines to a higher value. The electric field across the floating gate and the substrate is not enough to erase the blocks.  
         [0009]     The total physical size of a NAND string is dictated by the total size of the cells plus the overhead of the select transistors and corresponding contacts. The memory cells may be scaled to their minimum sizes but the select transistors are typically CMOS-type transistors and are much larger. For example, older memory devices had 16 cells per serial string with the same size and quantity of select transistors. In order to decrease the cost of memory, integrated circuit manufacturers went to 32 cells per serial string, thus decreasing the overhead per string. However, the size of the block was doubled so that the end user now has to erase twice as many cells at the same time. This could create problems for systems having software written for a predetermined number of cells. The additional erasing could also create erase stress on those cells not required to be erased.  
         [0010]     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flash memory device that has reduced overhead due to select transistors without increasing the erase stress associated with increased block sizes.  
       SUMMARY  
       [0011]     The above-mentioned problems with erasing a non-volatile memory device and other problems are addressed by the present invention and will be understood by reading and studying the following specification.  
         [0012]     The present invention encompasses a method for erasing a memory device comprising a memory array. The memory array is comprised of a plurality of memory strings that are coupled to a source line and fabricated on a substrate. Each memory string is made up of at least two memory cell subsets. The method comprises biasing a first memory cell subset with erase voltages while a second memory cell subset is biased with erase inhibit voltages.  
         [0013]     Further embodiments of the invention include methods and apparatus of varying 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  shows a simplified schematic diagram of a typical prior art flash memory array.  
         [0015]      FIG. 2  shows a simplified schematic diagram of one embodiment of a portion of the flash memory array of the present invention.  
         [0016]      FIG. 3  shows a flowchart of one embodiment of the partial string erase scheme of the present invention.  
         [0017]      FIG. 4  shows a flowchart of one embodiment of a method for memory cell wear leveling.  
         [0018]      FIG. 5  shows a block diagram of one embodiment of an electronic system of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0019]     In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.  
         [0020]      FIG. 2  illustrates a simplified schematic diagram of one embodiment of the memory block of the present invention. The present invention increases the quantity of the total memory cells in a string while maintaining the erasable memory block size. This is accomplished by creating two or more separately erasable subsets within the memory block. In one embodiment, a shadow block is created that is comprised of half of the memory cells in an increased size memory block. During an erase operation, only the normal memory block or its shadow block would be erased at any one time.  
         [0021]     The embodiment of  FIG. 2  illustrates an embodiment where the quantity of rows is increased to 64 (WL 0 -WL 63 ). Doubling the quantity of rows is for purposes of illustration only. The present invention is not limited to any one increased quantity of rows.  
         [0022]     By increasing the quantity of memory cells in each series string  210 - 212 , the quantity of memory cells per select transistor  201 - 206  is thereby increased as well. This decreases the physical size of the required overhead for each string.  
         [0023]     In the embodiment of  FIG. 2 , the first series string  210  is connected to the first bit line BL 1  through a drain select transistor  201  and to the source line (SL) through a source select transistor  204 . The second series string  211  is connected to the second bit line (BL 2 ) through a second drain select transistor  202  and to the source line (SL) through a second source select transistor  205 . Similarly, the third series string  212  is connected to the third bit line (BL 3 ) through a third drain select transistor  203  and to the source line (SL) through a third source select transistor  206 . The drain select transistors  201 - 203  are controlled by the select gate drain control line SG(D) while the source select transistors  204 - 206  are controlled by the select gate source control line SG(S).  
         [0024]     For purposes of clarity, only three bit lines BL 1 -BL 3  are shown in the embodiment of  FIG. 2 . However, it is well known in the art that a large quantity of bit lines would be used.  
         [0025]     In one embodiment, the shadow block of the present invention is comprised of word lines  32 - 63  so that the “normal” memory block is comprised of word lines  0 - 31 . Alternate embodiments may divide up the increased quantity of word lines in different ways. The quantity of rows in the normal memory block and the shadow memory block do not have to be equal.  
         [0026]     One embodiment for an erase operation of the present invention biases the selected word lines of the memory block to be erased (e.g., normal memory block or shadow memory block) at 0V. The unselected word lines of the remaining memory block are biased at some high voltage (e.g., 20V) that would inhibit erase of those rows. The source line and the tub would be biased at 20V. Since both the normal and the shadow blocks share the same source and tub, both blocks would experience this biasing. The biasing of the memory blocks could then be switched in order to erase the block that was not erased previously.  
         [0027]     During a program operation, the normal and shadow blocks are independent from each other except that the bit lines of the shadow block will be exercised whenever the other block is programmed. The same is true of the normal block when the shadow block is programmed. The embodiments of the present invention use a wear leveling scheme to track the number of times that each of these blocks are cycled between erase and program states. A lower quantity of cycles would then be allowed for the shadow block, in one embodiment. Thus, if a normal memory block is allowed to experience 10,000 erase/program cycles, the shadow block would only be allowed 5,000 cycles.  
         [0028]      FIG. 3  illustrates a flowchart of one embodiment of a method for a partial string erase operation of the present invention. It is determined whether the shadow block or the normal block is to be erased  301 . This determines how the word lines are to be biased.  
         [0029]     The selected word lines are biased at ground potential  303 . The unselected word lines are biased at some high inhibit voltage  305  that is greater than V CC  such as a voltage in the range of 16-20V. The source lines and tub are also biased at a high voltage  307 . In one embodiment, this voltage is the same as the inhibit voltage. Alternate embodiments can use a voltage that is greater than V CC .  
         [0030]     In another embodiment, instead of biasing the unselected word lines at some high inhibit voltage, the unselected word lines can be left floating. Since the tub is biased at some high voltage, such as 20V, the floating word lines would be coupled up substantially close to that high tub voltage. This would perform the same inhibit function as in the bias voltage greater than V CC .  
         [0031]     In this alternate embodiment, there is the possibility that one or more of the unselected word lines nearest the selected word lines at ground potential might not have a high enough voltage to inhibit the erase operation. In such an embodiment, the word lines closest to the selected word lines could be biased at some high inhibit voltage as stated previously.  
         [0032]      FIG. 4  illustrates a flowchart of one embodiment of a method for memory cell wear leveling. This method provides more even memory block cycling between the shadow block and the normal block due to the program or erase disturb condition.  
         [0033]     It is determined whether the shadow block or the normal block is being programmed or erased  401 . If the normal memory block is being programmed/erased, a normal program/erase operation is performed on the memory block  409 .  
         [0034]     If the shadow memory block is to be programmed/erased, the quantity of program/erase cycles is checked to determine if a maximum quantity of cycles have occurred  403 . If the quantity of cycles is less than the maximum threshold, a normal program/erase operation is performed  405 . If the maximum threshold has been reached or exceeded, the program/erase operation is prohibited  407 .  
         [0035]      FIG. 5  illustrates a functional block diagram of a memory device  500  of one embodiment of the present invention that is coupled to a processor  510 . The processor  510  may be a microprocessor, a processor, or some other type of controlling circuitry. The memory device  500  and the processor  510  form part of an electronic system  520 . The memory device  500  has been simplified to focus on features of the memory that are helpful in understanding the present invention.  
         [0036]     The memory device includes an array of memory cells  530 . In one embodiment, the memory cells are non-volatile floating-gate memory cells and the memory array  530  is arranged in banks of rows and columns.  
         [0037]     An address buffer circuit  540  is provided to latch address signals provided on address input connections A 0 -Ax  542 . Address signals are received and decoded by a row decoder  544  and a column decoder  546  to access the memory array  530 . It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array  530 . That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.  
         [0038]     The above-described embodiments have focused on a NAND architecture memory array. However, the present invention is not limited to this architecture. The embodiments of the memory block erase method of the present invention can be used in any architecture of memory device (e.g., NAND, NOR, AND).  
         [0039]     The memory device  500  reads data in the memory array  530  by sensing voltage or current changes in the memory array columns using sense/latch circuitry  550 . The sense/latch circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array  530 . Data input and output buffer circuitry  560  is included for bidirectional data communication over a plurality of data connections  562  with the controller  510 ). Write circuitry  555  is provided to write data to the memory array.  
         [0040]     Control circuitry  570  decodes signals provided on control connections  572  from the processor  510 . These signals are used to control the operations on the memory array  530 , including data read, data write, and erase operations. In one embodiment, the control circuitry  570  executes the embodiments of the partial string erase scheme of the present invention. The control circuitry  570  can also be responsible for preventing further program/erase cycles on the shadow memory once the program/erase cycle threshold has been reached. The control circuitry  570  may be a state machine, a sequencer, or some other type of controller.  
         [0041]     The flash memory device illustrated in  FIG. 5  has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.  
       CONCLUSION  
       [0042]     In summary, the embodiments of the present invention increase the quantity of cells per string while keeping the erasable block the same size, thus reducing the total overhead of the select transistors. A partial string erase scheme is used during the erase operation to erase only a portion of the larger memory block, effectively reducing the larger memory block during an erase operation to a normal memory block and a shadow memory block. A wear leveling scheme reduces the impact of the block cycling on the shadow block.  
         [0043]     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.