Abstract:
The present invention relates to a new method of power converter regulation, in particular regulation of very high frequency (VHF) power converters operating at frequencies in the MHz range, wherein accurate output regulation utilises inherent delays in the regulation loop, whereby, contrary to hysteresis on/off control, the new method does not require immediate responses to comparisons of a sense voltage to two reference voltages; rather, according to the new method, only one reference voltage is used, and delays in the feedback loop are allowed to cause some variation of an output of the power converter.

Description:
[0001]    The present invention relates to a new method of power converter regulation, in particular regulation of very high frequency (VHF) power converters operating at frequencies in the MHz range. 
       BACKGROUND OF THE INVENTION 
       [0002]    Reducing the physical size of electronic equipment in power applications is desired in order to add more features into existing products, integrate power converters in places normally unfit for such equipment, and reduce system cost. Increasing the operating frequency of the converter is a direct way of reducing the size of energy storage elements such as bulky capacitors and inductors, which usually dominate the overall converter volume. Due to reduction in energy storage requirements the transient response is dramatically increased. LED lighting applications and point-of-load (PoL) converters particularly benefit from very high frequency (VHF) converters due to size, price, and weight reduction, and faster transient response. 
         [0003]    Conventionally, burst mode control is used to control the output voltage or current of resonant power converters. Burst mode control allows the converter designer to optimize resonant power converters for operation in one operating point. The output voltage or current is controlled by turning the resonant power converters on or off as necessary to maintain constant output voltage or current. A disadvantage of burst mode control is that the EMI performance is the same or worse compared to hard switched converters at the same modulation frequency. Typically, the modulation frequency ranges from 20 kHz to 1 Mhz. 
         [0004]    Typically, prior art burst mode control is either hysteresis based, or pulse width modulation (PWM) based with constant switching frequency. 
         [0005]    With hysteresis and PWM control, fast responses—ideally zero time delays—of the components of the regulation loop are required so that low cost components cannot be used. 
         [0006]    The converter start-up circuit must also provide very little delay. As a consequence, passive start-up circuits (which have lower cost) are usually not an option. 
         [0007]    Hysteresis based control results in tight output regulation, but requires a high cost, high performance comparator with very small propagation delays. 
         [0008]    A conventional hysteretic burst mode control method of controlling a power converter, comprises the steps of
       turning the power converter on when an absolute value of a sense voltage is less than or equal to an absolute value of a first reference voltage, and   turning the power converter off when the absolute value of the sense voltage is larger than or equal to an absolute value of a second reference voltage that is larger than the absolute value of the first reference voltage.       
 
         [0011]    Typically, the difference between the first and second reference voltages is a predetermined fixed value. 
       SUMMARY OF THE INVENTION 
       [0012]    The present invention provides a modulation method for obtaining accurate output regulation of a power converter while exploiting inherent delays in the feedback loop. 
         [0013]    Contrary to hysteresis on/off control, i.e. hysteretic burst mode control, the new method does not require immediate responses to comparisons of a sense voltage to two reference voltages. Rather, according to the new method, only one reference voltage is used, and delays in the feedback loop are allowed to cause some variation of an output of the power converter. The variation can be predicted and accounted for during the converter design process. 
         [0014]    Thus, a new method of controlling a power converter is provided, comprising the steps of
       turning the power converter on when an absolute value of a sense voltage is less than or equal to an absolute value of a reference voltage and a first time period has elapsed since a previous turn-off of the power converter, and   turning the power converter off when the absolute value of the sense voltage is larger than or equal to the absolute value of the reference voltage and a second time period has elapsed since a previous turn-on of the power converter.       
 
         [0017]    In the following, the new method is termed phase-shift burst mode control due to the phase shift caused by the first and second time periods. According to the new method, hysteresis is provided in the time domain. 
         [0018]    A power converter operating in accordance with the new method is also provided. 
         [0019]    Thus, a new power converter is provided, comprising a control circuit coupled to compare a sense voltage with a reference voltage, and having a control output that is coupled to control turn-on and turn-off of the power converter in such a way that
       the power converter is turned-on when the absolute value of the sense voltage is less than or equal to the absolute value of the reference voltage and a first time period has elapsed since a previous turn-off of the power converter, and   the power converter is turned-off when the absolute value of the sense voltage is larger than or equal to the absolute value of the reference voltage and a second time period has elapsed since a previous turn-on of the power converter.       
 
         [0022]    The first time period may include a third time period of a predetermined duration that has to elapse from the point in time when the absolute value of the sense voltage drops below the absolute value of the reference voltage until the power converter is turned-on. 
         [0023]    The second time period may include a fourth time period of a predetermined duration that has to elapse from the point in time when the absolute value of the sense voltage raises above the absolute value of the reference voltage until the power converter is turned-off. 
         [0024]    The predetermined durations of the third and fourth time periods may be different. 
         [0025]    Throughout the following disclosure, the process of alternatingly turning a power converter on and off, is termed “modulation” of the power converter, and the time between two consecutive turn-on events is termed a “modulation period”, and the rate of turn-on is termed the “modulation frequency”. 
         [0026]    The sense voltage may correspond to an output voltage of the power converter; or an output current of the power converter; or another desired characteristic of the power converter. 
         [0027]    An output current of the power converter is a current consumed by a load connected to an output of the power converter. 
         [0028]    The control circuit may perform turn-off of the power converter by turning at least one switch of the power converter off, e.g. by short-circuiting the gate of a Field-Effect-Transistor (FET) to its source; or, the base of a bipolar transistor to its emitter, and turn-on of the power converter by allowing the at least one switch of the power converter to turn-on again, e.g. by opening the short-circuit. 
         [0029]    The control circuit may also perform turn-on and turn-off of a resonant power converter by changing the impedance or the loop-gain of the resonant part of the power circuit, whereby the resonant power converter is turned-off by changing the impedance or loop-gain to a first value at which the resonant part of the power circuit does not oscillate, and whereby the resonant power converter is turned-on by changing the impedance or loop-gain to a second value at which the resonant part of the power circuit oscillates. 
         [0030]    The control circuit may comprise one or more delays configured to provide at least part of one or more of the respective first and second time periods. Propagation delays in circuit components, such as propagation delays in a comparator, filtering elements, the power circuit, etc., may advantageously be incorporated into the appropriate time period. 
         [0031]    The control circuit may comprise a comparator coupled to compare the sense voltage with the reference voltage, and an output of the comparator may constitute the control output that is coupled to control turn-on and turn-off of the power converter, and thus, the delays with which the comparator changes state of its output from high to low and vice versa, in response to changed input(s), constitute part of the respective first and second time periods. 
         [0032]    The delays with which the comparator changes state of its output from high to low and vice versa, in response to changed input(s), may provide at least part of the third and fourth time periods. 
         [0033]    The output voltage of the power converter may be coupled to signal conditioning circuit, such as a low-pass filter, etc., configured to output the sense voltage. 
         [0034]    The power converter may be of any known type of power converters, and in particular any type of VHF power converters, such as square wave power converters, quasi-square wave power converters, resonant transition power converters, resonant power converters, etc. 
         [0035]    The power converter may have a plurality of power circuits operating in series and/or in parallel and/or interleaved, e.g. with inputs in series and/or parallel and/or with outputs in series and/or parallel. All or some of the plurality of power circuits may be controlled with a single control circuit. 
         [0036]    A resonant power converter may be of any known type of resonant power converters, such as converters comprising: a class E inverter and a class E rectifier, a class DE inverter and a class DE rectifier, a class DE inverter and a class E rectifier, etc.; or, class EF2 (or class φ) converters, resonant Single-Ended Primary-Inductor Converters (SEPIC), etc. 
         [0037]    The power converter may be driven by an oscillator, or the converter may be self-oscillating. Further, the power converter may be interleaved. 
         [0038]    Basing control of the output of the power converter on a single reference voltage and time periods during which the power converter does not change state from a turned-on state to a turned-off state, or vice-versa, leads to lowered performance requirements for control circuit components as compared to components of conventional control circuits, e.g. utilizing PWM-control or hysteresis control. E.g., low cost components and passive start-up circuits may be used in the new control circuit. 
         [0039]    Furthermore, it is possible to include low-pass filtering, or other signal conditioning, of the output voltage for provision of the sense voltage, thus improving signal integrity. 
         [0040]    Increasing at least one of the first and second time periods provided by the control circuit lowers modulation frequency of the control output signal controlling the on/off states of the power converter. This in turn increases variation of the output voltage; however, output voltage variations may be lowered by provision of a suitable output filter at the output of the power converter. 
         [0041]    Due to the time periods provided by the control circuit, the response time of the control circuit is longer than the response time of hysteresis control. Still, desired regulation is achieved within one modulation cycle. 
         [0042]    Conventional control circuits, such as PWM-control or hysteresis control, rely on high-end components and on minimizing time delays in the control circuit, leading to higher cost and lower component availability than for the corresponding components of the new control circuit. 
         [0043]    For example, a comparator used in the new control circuit may be 9-10 times slower than a comparator used in a conventional control circuit, e.g. 4.5 ns vs 40 ns. 
         [0044]    As further explained below, at least one of, or both of, the first and second time periods may be equal to, or substantially equal to, one fourth the modulation period, e.g. at 50% duty cycle, for example at least one of, or both of, the third and fourth time periods may be equal to, or substantially equal to, one fourth the modulation period, e.g. at 50% duty cycle. 
         [0045]    The sense voltage may be a function of the output voltage supplied to a load connected to an output of the power converter; or, the sense voltage may be a function of the output current supplied to a load connected to an output of the power converter; or, the sense voltage may be a function of power, i.e. output voltage times output current, supplied to a load connected to an output of the power converter; etc. 
         [0046]    An output capacitor connected to an output of the power converter stabilizes the output voltage supplied by the power converter. The output capacitor is charged during turn-on of the power converter and discharged during turn-off of the power converter. During turn-on, the capacitor is charged with the current supplied by the power stage of the power converter minus the current supplied to the load connected to the output of the power converter. During turn-off, the capacitor is discharged with the load current. Thus, the slope of the voltage ripple ΔV out  developed across the output capacitor as a result of the charging and discharging of the output capacitor depends on the output current. If the output current is low, the slope of the voltage ripple is steep during turn-on of the power converter and low during turn-off of the power converter, and vice versa if the output current is high. This together with the first and second time periods causes the output voltage ripple to vary with varying output current and also causes the mean value of the output voltage V out  to vary with varying output current. Correspondingly, the ripple of the output current I out  and output power P out , and the mean value of output power P out  may also vary with varying output current. 
         [0047]    This variation may be compensated in various ways in order to lower the amount of variation and making the desired output value more constant and independent of the output current at least within a predetermined output current range. 
         [0048]    For example, the control circuit may be configured to compensate a dependence of the sense voltage, and thereby a dependence of the output voltage; or, the output current; or the output power; etc., on the output current, for example by varying the reference voltage in dependence on the output current in such a way that the dependence of the sense voltage on the output current is compensated. For example, an increase in output voltage may be compensated by lowering the reference voltage so that the power converter is turned-on at a lower voltage thereby lowering the resulting output voltage. The change in reference voltage takes place over a plurality of modulation periods. When the load is constant, the reference voltage does not change unless an adjustment of the output, such as the output voltage or current, is performed. 
         [0049]    Additionally; or, alternatively, the control circuit may be configured to vary at least one of the first and second time periods in dependence of the output current, whereby the dependence of the sense voltage on the output current is compensated. For example, an increase in output voltage may be compensated by lowering the second time period so that the power converter is turned-on during a shorter time period thereby lowering the resulting output voltage. When the load is constant, the first and second time periods do not change. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0050]    Below, the new method and the new power converter are explained in more detail with reference to the drawings in which various resonant examples of the new power converter are shown. In the drawings: 
           [0051]      FIG. 1  shows a schematic diagram of a resonant power converter with the new control circuit, 
           [0052]      FIG. 2  shows a schematic circuit diagram of an exemplary new resonant power converter, 
           [0053]      FIG. 3  shows a schematic circuit diagram of an exemplary new resonant power converter, 
           [0054]      FIG. 4  shows a schematic circuit diagram of an exemplary new resonant power converter, 
           [0055]      FIG. 5  shows a schematic circuit diagram of an exemplary new resonant power converter, 
           [0056]      FIG. 6  shows exemplary signal conditioning circuits, 
           [0057]      FIG. 7  shows exemplary switch drivers, 
           [0058]      FIG. 8  shows a schematic circuit diagram of an exemplary new resonant power converter with a stop circuit, 
           [0059]      FIG. 9  shows a switch driver with oscillator turn-off, 
           [0060]      FIG. 10  shows a power circuit diagram of a VHF interleaved self-oscillating resonant SEPIC converter, 
           [0061]      FIG. 11  is a plot of simulated waveforms of the power circuit shown in  FIG. 10 , 
           [0062]      FIG. 12  shows a schematic circuit diagram of a model of a new resonant power converter used for calculation of component values, 
           [0063]      FIG. 13  shows a circuit diagram of a control circuit used to control the power circuit shown in  FIG. 10 , 
           [0064]      FIG. 14  is a plot of characteristic waveforms of the model shown in  FIG. 12 , 
           [0065]      FIG. 15  is a plot of experimental waveforms of the control circuit shown in  FIG. 13 , 
           [0066]      FIG. 16  is a plot of experimental waveforms of the power circuit shown in  FIG. 10 , 
           [0067]      FIG. 17( a )  shows a plot of converter efficiency as a function of output power and ( b ) shows a plot of output voltage offset as a function of the load, 
           [0068]      FIG. 18  is a flowchart of the new method, 
           [0069]      FIG. 19  shows (a) a schematic circuit diagram of a model of the new resonant power converter together with (b) a conventional hysteretic control circuit and (c) a phase-shift burst mode control circuit, 
           [0070]      FIG. 20  shows a plot of simulated waveforms of the model converter current and voltages controlled by the hysteretic control circuit, 
           [0071]      FIG. 21  shows a plot of simulated waveforms of the model converter current and voltages controlled by the phase-shift burst mode control circuit, and 
           [0072]      FIG. 22  shows schematic circuit diagrams of control circuits with varying sense voltage. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0073]    The accompanying drawings are schematic and simplified for clarity, and they merely show details which are essential to the understanding of the new resonant power converter, while other details have been left out. The new resonant power converter according to the appended claims may be embodied in different forms not shown in the accompanying drawings and should not be construed as limited to the examples set forth herein. 
         [0074]    Like reference numerals refer to like elements throughout. Like elements may, thus, not be described in detail with respect to the description of each figure. 
         [0075]      FIG. 1  shows a schematic block diagram of a resonant power converter  10  controlled in accordance with the new method. The illustrated resonant power converter  10  comprises a VHF power circuit  12 , a control circuit  14  with a control output  16 , and a signal conditioning circuit  18  providing a sense voltage  20  based on and corresponding to the output voltage  22 . 
         [0076]    The control circuit  14  is coupled to compare the sense voltage  20  with a reference voltage  24 . 
         [0077]    Alternatively, the sense voltage  20  may be provided by a current sensor, such as a resistor, a hall element, etc., coupled so that the sense voltage corresponds to an output current of the resonant power converter  10 . 
         [0078]    The control circuit  14  has a control output  16  that is coupled to control turn-on and turn-off of the VHF power circuit  12  of the resonant power converter. 
         [0079]    In the illustrated examples, the output voltage and the sense voltage have positive values, so that the absolute value of the sense voltage or the output voltage is equal to the value itself. 
         [0080]    The VHF power circuit  12  of the resonant power converter  10  is turned-on when the sense voltage  20  is less than or equal to the reference voltage  24  and a first time period has elapsed since a previous turn-off of the VHF power circuit  12 . The VHF power circuit  12  of the resonant power converter  10  is turned-off when the sense voltage  20  is larger than or equal to the reference voltage  24  and a second time period has elapsed since a previous turn-on of the VHF power circuit  12 . 
         [0081]    The VHF power circuit  12  may be of any known resonant power converter topology with a frequency of operation in the MHz range, such as at or above 20 MHz, such as at or above 30 MHz, such as in the 30 MHz-300 MHz range, such as converters comprising: a class E inverter and a class E rectifier, a class DE inverter and a class DE rectifier, a class DE inverter and a class E rectifier, etc.; or, class EF2 (or class φ) converters, resonant SEPIC converters, etc. 
         [0082]    The resonant power converter may be driven by an oscillator, or the converter may be self-oscillating. Further, the resonant power converter may be interleaved. 
         [0083]    Inherent signal propagation delays of the components of the control circuit  14  forms parts of the first and second time periods, and the inherent signal propagation delays may form the entire first and second time periods. Additionally, one or more delay circuits may provide part of the first time period and/or part of the second time period, namely part of the third time period and/or part of the fourth time period. 
         [0084]    The control circuit  14  may comprise a comparator that is coupled to compare the sense voltage  20  with the reference voltage  24 , and having a comparator output that is the control output  16 . 
         [0085]    The delays with which the comparator changes state of its output from high to low and vice versa, in response to changed input(s), constitute part of the respective first and second time periods, namely part of the third time period and/or part of the fourth time period. 
         [0086]    The signal conditioning circuit  18  may be a low-pass filter configured to output the sense voltage. 
         [0087]    The control output  16  may be coupled to control turn-off of at least one power switch (not shown) of the resonant power converter  10  thereby turning the resonant power converter off. 
         [0088]    This is illustrated in the class E inverter based resonant power converters shown in  FIGS. 2 and 3 . The only difference between the resonant power converter of  FIG. 2  and the resonant power converter of  FIG. 3  is that inductor L 3  of  FIG. 2  has been substituted by rectifier D 1  in  FIG. 3 . 
         [0089]    Alternatively, or additionally, the control output  16  may be coupled to control other parts of the resonant power converter circuit than the power switches, e.g. by enabling and disabling energy transfer from the input to the output of the resonant power converter  10 , e.g. by turning the resonant power converter on and off by changing the impedance or the loop-gain of the resonant part of the power circuit, whereby the resonant power converter is turned-off by changing the impedance to a first value at which the power circuit does not oscillate, and whereby the resonant power converter is turned-on by changing the impedance to a second value at which the power circuit oscillates. 
         [0090]    This is illustrated in  FIGS. 4 and 5  showing a class E inverter based resonant power converter similar to the class E inverter based resonant power converters shown in  FIG. 3  except for the fact that the control output  16  turns S 2  on and off. 
         [0091]    In  FIG. 4 , the resonant part of the resonant power converter  10  does not oscillate when switch S 2  is turned-on, and the resonant part of the resonant power converter  10  oscillates and operates like the resonant power converter  10  of  FIG. 3  when switch S 2  is turned-off. 
         [0092]    In  FIG. 5 , the functions of rectifier D 2  and switch S 2  of  FIG. 4  are combined in switch S 2  functioning as a synchronous rectifier in  FIG. 5  when the second self-oscillating gate driver is enabled so that the resonant power converter is turned on. 
         [0093]      FIG. 6  shows circuit diagrams of two examples of low-pass filters that may constitute the signal conditioner  18 . 
         [0094]    The signal conditioners shown in  FIGS. 6( a ) and ( b )  may be substituted with any suitable signal conditioner chosen from other signal conditioner designs available to the person skilled in the art. 
         [0095]    Examples of self-oscillating gate drivers are shown in  FIG. 7 . 
         [0096]    In  FIG. 7( a ) , a low enable signal keeps the gate of the power switch at zero voltage, whereby oscillation of the power circuit is inhibited, while a high enable signal allows propagation of the VHF oscillator signal driving the gate of the power switch causing the power circuit to oscillate. 
         [0097]    In  FIG. 7( b ) , a low enable signal switches switch transistor S aux  off and keeps the gate of the power switch at a constant voltage, whereby oscillation of the power circuit is inhibited, while a high enable signal allows propagation of the VHF oscillator signal driving the switch transistor S aux  on and off thereby driving the power switch on and off causing the power circuit to oscillate. 
         [0098]    The gate drivers shown in  FIGS. 7( a ) and ( b )  may be substituted with any suitable gate driver chosen from other gate driver designs available to the person skilled in the art. 
         [0099]      FIG. 8  shows a schematic circuit diagram of an exemplary new resonant power converter with a stop circuit, 
         [0100]      FIG. 9  shows a switch driver with oscillator turn-off, 
         [0101]      FIG. 10  is a circuit diagram of a power circuit  12  of an interleaved self-oscillating resonant SEPIC converter, wherein two power circuits  12   a ,  12   b  drive each other via capacitive coupling C X1  and C X2  between the switches S 1  and S 2  and operate in interleaved mode. 
         [0102]    The power circuits are substantially identical, i.e.: 
         [0000]      L I1 =L I2 =L I    
         [0000]      C I1 =C I2 =C I    
         [0000]      C X1 =C X2 =C X    
         [0000]      C S1 =C S2 =C S    
         [0103]    The values of the most important parasitic components of the semiconductor devices, namely diode junction capacitors and parasitic capacitors of the semiconductor switches, are included in determination of operating frequency of the resonant power converter. The oscillation frequency f S  is determined mainly by the inductance L I  and the total capacitance seen from the drain when the rectifiers are shorted, C DS,tot    
         [0000]    
       
         
           
             
               f 
               s 
             
             = 
             
               1 
               
                 2 
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                  
                 
                   
                     
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                       I 
                     
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                         DS 
                         , 
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           where 
         
       
       
         
           
             
               C 
               
                 DS 
                 , 
                 tot 
               
             
             = 
             
               
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               C 
               ISS 
             
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         [0104]    Oscillations start once the gate voltages of the MOSFET switches S 1  and S 2  become slightly higher than the MOSFET threshold voltage. Simulated waveforms of the resonant power circuit of  FIG. 10  are shown in  FIG. 11 . Ideally, respective waveforms of the two interleaved power converters are identical and shifted 180° with relation to each other. 
         [0105]    If VHF ripple is neglected, the converter output can be modeled as a current source with the current value of I 0 . When an on/off modulation is applied on the converter, the current supplied by the converter i conv  to C out  and the load may be approximately modeled as a current square wave: 
         [0000]    
       
         
           
             
               i 
               conv 
             
             = 
             
               { 
               
                 
                   
                     
                       
                         I 
                         0 
                       
                       , 
                     
                   
                   
                     
                       when 
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         [0106]    Output current I out  is equal to average value of i conv  over one modulation cycle. The resulting current going into C out  is i conv −I out , which has no DC component in steady state. If parasitics of C out  are negligible, the resulting V out  voltage waveform is a triangular wave. Assuming that turn-on and turn-off delays are independent of the output voltage rate of change, the output voltage ripple is 
         [0000]    
       
         
           
             
               Δ 
                
               
                   
               
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                 out 
               
             
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         [0000]    where t D,on  is the fourth time period and t D,off  is the third time period, i.e. t D,on  and t D,off  are the control loop turn-on and turn-off delays, respectively, from the sense voltage crossing the reference voltage and to turn-on or turn-off, respectively, of the power converter. If the control circuit&#39;s delays are constant, the equation shows that V out  is a linear function of I out , and the longer delay defines V out,max . In the special case of t D,on  and t D,off  being equal, V out  is independent of I out . At any given load, the offset of V out : ΔV out,off , and f M  are determined from the values of C out  and the delays t D,on  and t D,off  by: 
         [0000]    
       
         
           
             
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         [0107]    Modulation frequency is highest at 50% duty cycle, i.e. the power converter is turned on half the time: 
         [0000]    
       
         
           
             
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                 , 
                 max 
               
             
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                         off 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0108]    I 0  is not known from values of circuit components. An approximate value of I 0  can be determined from Spice simulations. Once I 0  is obtained, the output filter and the feedback circuit need to be designed to provide a desired modulation frequency f M  at a specified load. 
         [0109]      FIG. 12  shows a block diagram of such a low frequency model of a resonant power. The VHF power circuit  12  is modelled as an on-off controllable DC current source. 
         [0110]    The conditioning circuit  18  at the input of the control circuit  14 , see  FIG. 13 , has a simple transfer function: 
         [0000]    
       
         
           
             
               H 
                
               
                 ( 
                 s 
                 ) 
               
             
             = 
             
               
                 A 
                 FB 
               
               
                 1 
                 + 
                 
                   s 
                    
                   
                       
                   
                    
                   
                     τ 
                     FB 
                   
                 
               
             
           
         
       
       
         
           Where 
         
       
       
         
           
             
               A 
               FB 
             
             = 
             
               
                 R 
                 
                   FB 
                    
                   
                       
                   
                    
                   2 
                 
               
               
                 
                   R 
                   
                     FB 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 + 
                 
                   R 
                   
                     FB 
                      
                     
                         
                     
                      
                     2 
                   
                 
               
             
           
         
       
       
         
           
             
               τ 
               FB 
             
             = 
             
               
                 
                   
                     R 
                     
                       FB 
                        
                       
                           
                       
                        
                       1 
                     
                   
                    
                   
                     R 
                     
                       FB 
                        
                       
                           
                       
                        
                       2 
                     
                   
                 
                 
                   
                     R 
                     
                       FB 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   + 
                   
                     R 
                     
                       FB 
                        
                       
                           
                       
                        
                       2 
                     
                   
                 
               
                
               
                 C 
                 FB 
               
             
           
         
       
     
         [0111]    The comparator  26  of the control circuit  14  model is ideal; the propagation delay of the real comparator is added into the delay block. The delay block is represented by two different time delays, since the shutdown of the power circuit is significantly faster than the start-up sequence. This is because shutdown is performed by the auxiliary switches S aux1  and S aux2 , while during start-up C ISS  is passively charged from the bias voltage V B  through the biasing resistors. 
         [0112]      FIG. 13  shows the control circuit  14 . The sense voltage  20  is low-pass filtered in H(s), a voltage divider/low pass filter  18  formed by R FB1 , R FB2 , and C FB , and input to the comparator  26 . The comparator output  16  turns the switches S aux1  and S aux2  on and off in response to the voltage difference at the comparator inputs. When S aux1  and S aux2  are on, v GS1  and v GS2  are zero and the power circuit oscillations are inhibited. Once S aux1  and S aux2  are off, c ISS1  and C ISS2  are charged through R B1  and R B2 , whereby v GS1  and v GS2  start to increase from 0 to V B . After the first time period, when v GS1  and V GS2  exceed the power MOSFET threshold voltage V th , switches S 1  and S 2  enter saturation and initiate oscillations in the power circuit. H(s) has two primary purposes: to filter high frequency noise and adjust the feedback voltage level. It also contributes to propagation delay in the feedback loop. 
         [0113]    In  FIG. 14 , characteristic voltage and current levels from a numerical example of the model are shown, where
       C out =3.3 μF   I 0 =1.04 A, I out =0.52 A   R FB2 =2 kΩ, R FB1 =8.2 kΩ   C FB =22 pF   t d,on =700 ns+170 ns=870 ns   t d,off =170 ns       
 
         [0120]    The parameters are chosen to approximate the experimental setup described below. v gate (t) represents the gate voltages of S 1  and S 2  with removed VHF component. V out (t) passes through the single pole transfer function H(s) and results in a distorted triangular waveform v FB (t). Average value of v FB (t) is slightly lower than the reference V ref  voltage, which is due to t d,on &gt;t d,off . This is also the cause of the duty cycle of the comparator output v cmp (t) to be lower than 50%. Since the referent output voltage is 10 V, a small offset can be observed in V out (t). This offset is dependent on the duty cycle of the power circuit, the time difference t d,on −t d,off , and C out . t d,on  depends on the voltage difference between V B  and V th . Obtained modulation frequency is very close to 300 kHz. 
         [0121]    In order to verify the analysis explained above, a 10.5 W prototype converter with regulation of the output voltage was produced and the measurements for the prototype converter is disclosed below. 
         [0122]    Plots of drain, gate, and rectifier voltages in the power circuit are shown in  FIG. 15 . The drain and rectifier voltages were measured with capacitance of 2.2 pF in series with an oscilloscope probe, in order to reduce influence of the probe to the power circuit. This introduces attenuation of A=0.19 in the measurement and removes the DC component of the measured voltages. Component values of the power circuit are listed in Table I. Switching frequency of the power circuit is f S =49 MHz. Open loop output voltage and output voltage and current are V out =10.2 V and I 0 =1.04 A, respectively. 
         [0123]    When the duty cycle of 50% is obtained, I out =0.5 I 0 =0.52 A. Plots of the waveforms of the relevant voltages in the converter for this case are shown in  FIG. 9 . Modulation frequency f M  is at its maximum value of 300 KHz at 50% duty cycle, and drops as the duty cycle moves away from 50%. In addition, under these conditions output voltage ripple Δ V out , pp  is at its maximum as well. 
         [0124]    The comparator used in the circuit is AD8468 from Analog Devices. The component datasheet specifies 40 ns propagation delay. For comparison, a high speed TLV3501 comparator has a 4.5 ns propagation delay, which is a reduction by a factor of 9. This is by no means a limit since there are other significant contributors as well (conditioning and power circuit on-off circuit). This delay may be increased even further at a cost of a lower modulation frequency f M  and higher output voltage ripple for a given C out . 
         [0125]      FIGS. 15 and 16  illustrate relationships between the signals in time domain, V cmp+ , v cmp− , v GS , v DS , and v out  (upper waveforms) with respect to the comparator output (lower waveforms). High output voltage ripple is caused by a small output filtering capacitance (C out =3.3 pF). 
         [0126]    Efficiency of the converter is shown in  FIG. 17( a )  as a function of output power. Since f M  is allowed to drop significantly under light load conditions, efficiency is maintained high over wide load range (η&gt;75% above 20% load) with peak efficiency above 81%. 
         [0127]    Since the control is based on phase shift, a small DC error is introduced in the value of v out , which varies with the load. If the output voltage ripple is assumed triangular (which is reasonable since i conv  is a current square wave), the peak values of v out  are determined as: 
         [0000]    
       
         
           
             
               V 
               
                 out 
                 + 
               
             
             = 
             
               
                 V 
                 
                   out 
                   , 
                   ref 
                 
               
               + 
               
                 
                   
                     
                       I 
                       0 
                     
                     - 
                     
                       I 
                       out 
                     
                   
                   
                     C 
                     out 
                   
                 
                  
                 Δ 
                  
                 
                     
                 
                  
                 
                   t 
                   + 
                 
               
             
           
         
       
       
         
           
             
               V 
               
                 out 
                 - 
               
             
             = 
             
               
                 V 
                 
                   out 
                   , 
                   ref 
                 
               
               + 
               
                 
                   
                     - 
                     
                       I 
                       out 
                     
                   
                   
                     C 
                     out 
                   
                 
                  
                 Δ 
                  
                 
                     
                 
                  
                 
                   t 
                   - 
                 
               
             
           
         
       
     
         [0128]    So that the offset of V out  is determined by 
         [0000]    
       
         
           
             
               V 
               
                 out 
                 , 
                 offset 
               
             
             = 
             
               
                 V 
                 
                   out 
                   , 
                   ref 
                 
               
               - 
               
                 
                   
                     
                       Δ 
                        
                       
                           
                       
                        
                       
                         V 
                         
                           out 
                           + 
                         
                       
                     
                     + 
                     
                       Δ 
                        
                       
                           
                       
                        
                       
                         V 
                         
                           out 
                           - 
                         
                       
                     
                   
                   
                     C 
                     out 
                   
                 
                  
                 Δ 
                  
                 
                     
                 
                  
                 
                   t 
                   - 
                 
               
             
           
         
       
     
         [0129]    V out,ref  is a target value for the output voltage set by V ref  and R FB1 −R FB2  voltage divider. Δt +  and Δt −  are the time delays from a point when v out  crosses v out,ref  to a point where v out  reaches its maximum and minimum value, respectively. Depending on the variables in these equations, v out,offset  may be either positive or negative, and decreases with I out . Measured dependence of Δv out  is shown in the lower plot of  FIG. 17 . Both the offset and the output ripple are reduced with increase in C out , while the switching frequency will be reduced. 
         [0130]    A comparison between the model disclosed above and experimental results show close, but not perfect matching. The reasons for this are subjects of further investigation; it is assumed that imperfections in the active components and tolerances of the passive components are the main contributors. Still, the model gives significant insight into the system operation, and can be used as a good estimate during the converter design. 
         [0131]    Compared to hysteresis based burst mode control, the new method of controlling the resonant power converter allows use of a significantly slower and less expensive components in the control circuit, which is of importance for cost sensitive applications such as LED lighting and PoL converters. The illustrated power circuits and control circuits were implemented using only low cost commercially available components, with peak efficiency above 81% and high efficiency over wide load range. 
         [0132]      FIG. 18  is a flowchart  100  of the new method of controlling a resonant power converter. The method starts with method step  110  wherein the resonant power converter is turned on. 
         [0133]    When the resonant power converter is turned on, the output voltage and/or output current increases. A sense voltage is provided in the resonant power converter that corresponds to the output voltage or output current, and a reference voltage is provided in the resonant power converter that corresponds to a desired resulting output voltage or output current of the resonant power converter. 
         [0134]    According to method step  120 , the output voltage and/or output current continue to increase until the corresponding sense voltage V sense  is equal to or larger than the reference voltage V ref , and 
         [0135]    according to method step  130 , the output voltage and/or output current continue to increase until also a second time period t 2  has elapsed since a previous turn-on of the resonant power converter. 
         [0136]    Thus, when the sense voltage V sense  is equal to or larger than the reference voltage V ref , and a second time period t 2  has elapsed since a previous turn-on of the resonant power converter, the resonant power converter is turned-off in method step  140 . 
         [0137]    When the resonant power converter is turned on, the output voltage and/or output current decreases. 
         [0138]    According to method step  150 , the output voltage and/or output current continue to decrease until the corresponding sense voltage V sense  is equal to or less than the reference voltage V ref , and 
         [0139]    according to method step  160 , the output voltage and/or output current continue to decrease until also a first time period t 1  has elapsed since a previous turn-off of the resonant power converter. 
         [0140]    Thus, when the sense voltage V sense  is equal to or less than the reference voltage V ref , and a first time period t 1  has elapsed since a previous turn-off of the resonant power converter, the resonant power converter is turned-off in method step  110 . 
         [0141]    In the following, properties of the phase-shift burst mode control method for very high frequency (VHF) DC-DC converters are compared with a conventional control method with hysteresis based on comparison of a sense voltage with two threshold values. Again, an on-off controllable current source is used to model the low-frequency behaviour of VHF converters. Large output capacitance is used for output voltage filtering. The model is shown in  FIG. 19( a ) . 
         [0142]      FIG. 19( b )  shows the model of  FIG. 19( a )  controlled with a conventional hysteretic control circuit and  FIG. 19( c )  shows the model of  FIG. 19( a )  controlled with a phase-shift burst mode control circuit. 
         [0143]    For both circuits, the VHF power converter is operating (turned-on) when V ctrl  is high, e.g. 2 Volt, delivering an average current of I 0 =2 A. The VHF power converter is turned-off when V ctrl  is low, e.g. 0 Volt. In the present example, capacitor C out  and load R load  are set to 10 μF and 10Ω, respectively. Reference voltage V ref  equals 1 V, high impedance signal conditioning network H(s) has ratio of V sense /V out =1:N, e.g. 1:10, independent of frequency. The circuit configurations and component values are selected so that the target output V out  is equal to 10 V and at nominal load, the VHF power converter operates at a 50% duty cycle. It is assumed that gate drivers do not introduce any delay in any of the circuits of  FIGS. 19( a )-( c )  so that V ctrl =V cmp . 
         [0144]    In the control circuit with hysteresis shown in  FIG. 19( b ) , instantaneous response of the comparator is assumed so that the comparator does not add a delay in the control loop. In the present example, the hysteresis window is V H =20 mV. The comparator turns the converter on when V sense &lt;V ref  and turns it off otherwise. Simulated waveforms of the converter voltages of the converter with hysteresis control are shown in  FIG. 20 . 
         [0145]    Modulation frequency f M , i.e. the frequency at which the converter turns on and off, is given by: 
         [0000]    
       
         
           
             
               f 
               M 
             
             = 
             
               
                 
                   
                     I 
                     0 
                   
                   / 
                   2 
                 
                 
                   2 
                    
                   Δ 
                    
                   
                       
                   
                    
                   
                     V 
                     out 
                   
                    
                   
                     C 
                     out 
                   
                 
               
               = 
               
                 
                   
                     I 
                     0 
                   
                   / 
                   2 
                 
                 
                   2 
                    
                   
                     NV 
                     H 
                   
                    
                   
                     C 
                     out 
                   
                 
               
             
           
         
       
     
         [0146]    This equation is derived under the assumption that propagation delay t D  of the comparator, the gate driver, and the power stage of the converter is zero, and the equation is a good approximation when t D            1/f M . Expensive components, e.g. comparators, gate drivers, etc., have to be used in VHF designs to realize small propagation delays in the feedback loop. 
         [0147]    Time difference ΔT from V sense =V ref  until V sense =V ref +V H  in  FIG. 20  equals 1/(4 f M ). If V H -&gt;0 and t D -&gt;1/(4 f M ), the waveforms shown in  FIG. 20  turn into the waveforms shown in  FIG. 21  showing simulated waveforms of the converter voltages of the converter with phase shift burst mode control. The waveforms in  FIGS. 20 and 21  are aligned so that V sense  voltages cross the respective V ref  voltages at the same time, e.g. 2 μs, 4 μs, 6 μs, etc. The output voltage ripples are identical in  FIGS. 20 and 21 , however the signal propagation delay through the feedback loop is 1/(4 f M ), see the time difference between converter currents I conv,H/PS , comparator output voltages V cmp,H/PS , etc. 
         [0148]    With the component values mentioned above, the modulation frequency is 250 kHz. 
         [0149]    In  FIG. 21 , the power converter is turned-on at 3 μs, 7 μs, 11 μs, and 15 μs, and the power converter is turned-off at 1 μs, 5 μs, 9 μs, and 13 μs, and the first time period is equal to the second time period that is equal to 2 μs and the fourth time period, i.e. the turn-on delay t D,on , is equal to the third time period, i.e. the turn-off delay t D,off , that is equal to 1 μs. 
         [0150]    The converter with phase shift burst mode control provides the same output voltage ripple (i.e. ΔV out,H =ΔV out,PS ) as the converter with conventional hysteresis control, while using one or more components in the feedback loop with significantly larger respective delays. The resulting delay may be distributed arbitrarily between the power stage, the comparator, and the gate driver(s). This is very important for VHF converters, since numerous start-up and shutdown techniques (self-oscillating gate drivers and converters) with small, but finite delays may be utilized in a VHF converter with phase shift burst mode control. 
         [0151]    Turn-on and turn-off delay (t D,on  and t D,off ) do not need to be equal, either. Any one of the components in the feedback loop in any combination may contribute to the values of the turn-on and turn-off delays, with the restraint that: 
         [0000]    
       
         
           
             
               
                 t 
                 
                   D 
                   , 
                   on 
                 
               
               + 
               
                 t 
                 
                   D 
                   , 
                   off 
                 
               
             
             = 
             
               1 
               
                 2 
                  
                 
                   f 
                   M 
                 
               
             
           
         
       
     
         [0152]    Output voltage of a converter with hysteresis control resides within the range from H(s) −1 (V ref,H −V H ) to H(s) −1 (V ref,H +V H ), resulting in a voltage ripple of ΔV out,H . 
         [0153]    This is different of a converter with phase shift burst mode control as illustrate in  FIG. 19( c )  in which the output voltage V 0  is load dependent. The output voltage V 0  decreases with increased load. If output voltage ripple at I out =1A is ΔV out,PS  and under assumptions of constant delay in the comparator (and otherwise ideal components), average value of V out,PS  ranges from ΔV out,PS /2 at I out =0 to −ΔV out,PS  at I out =I 0  linearly with I out . 
         [0154]    The variation of the output voltage V o  as a function of output current may be decreased in various ways. One way is to allow the reference voltage to change as a function of the output voltage V o  to compensate for the change in the output voltage V o . 
         [0155]      FIG. 22( a )  shows a control circuit in which the sense voltage  20  is compared to a reference voltage  28  that is adjusted as a function of the mean output voltage V o . H 1 (s) is an ordinary low-pass filter. In the illustrated circuit V ref1 =V ref −(V ref,mean −V ref ), where V ref,mean  is the output of the low-pass filter H 1 (s). Thus, V ref1 =V ref  when V ref,mean =V ref  and V ref1  decreases when the mean output voltage V o  increases and vice versa whereby the variation of the mean output voltage V o  as a function of output current is counteracted. 
         [0156]      FIG. 22( b )  shows another control circuit in which the sense voltage  20  is compared to a reference voltage  28  that is adjusted as a function of the mean of the comparator output voltage V cmp,PS    16 . The operation of the illustrated control circuit is based on the fact that the average value of V cmp,PS  varies linearly with the output current I out . 
         [0157]    Reference voltage V ref1  is formed by superposition of V ref,PS  and low-pass filtered V cmp,PS . The resistor and capacitor values in the compensation network need to be chosen to provide sufficient attenuation of the ac component of V cmp,PS . 
         [0158]    In the illustrated control circuit, when the converter operates at 50% modulation, the average of V cmp,PS  equals V ref . If the output current I out  is reduced, the average value of V cmp,PS  is reduced, thus decreasing reference voltage V ref1    28  thereby counteracting the increase of the output voltage V o  that would otherwise result for the reduced output current I out . If the output current I out  is increased, the average value of V cmp,PS  is increased, thus increasing reference voltage V ref1    28  thereby counteracting the decrease of the output voltage V o  that would otherwise result from the increased output current I out . V ref1  is calculated with the following formulae: 
         [0000]    
       
         
           
             
               V 
               
                 ref 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   V 
                   
                     ref 
                     , 
                     PS 
                   
                 
                  
                 
                   
                     
                       R 
                       1 
                     
                      
                     
                        
                        
                     
                      
                     
                       ( 
                       
                         
                           R 
                           2 
                         
                         + 
                         
                           R 
                           3 
                         
                       
                       ) 
                     
                   
                   
                     R 
                     1 
                   
                 
               
               + 
               
                 
                   V 
                   
                     cmp 
                     , 
                     PS 
                     , 
                     high 
                   
                 
                  
                 
                   
                     I 
                     out 
                   
                   
                     I 
                     0 
                   
                 
                  
                 
                   
                     
                       
                         R 
                         1 
                       
                        
                       
                          
                          
                       
                        
                       
                         ( 
                         
                           
                             R 
                             2 
                           
                           + 
                           
                             R 
                             3 
                           
                         
                         ) 
                       
                     
                     
                       R 
                       1 
                     
                   
                   .