Abstract:
An over current protection circuit controls connection and disconnection of an electronic device. When the electronic device is turned off because of over current, the over current protection circuit automatically resets the electronic device after a delay time.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to over current protection circuits, and particularly, to an over current protection circuit with an automatically reset capability. 
         [0003]    2. Description of Related Art 
         [0004]    Over current protection circuits have been extensively applied to electronic devices to protect the electronic devices from being damaged in case of excessive current. Generally, when the current in the electronic device exceeds a safe level, the over current protection circuit opens the circuit of the electronic device. However, current over current protection circuits typically do not automatically reset. As such, it is inconvenient to use over current protection circuits. 
         [0005]    Therefore, an over current protection circuit which can overcome the above-described problems is desirable. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0006]    Many aspects of the embodiments can be better understood with reference to the following drawing. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. 
           [0007]    The FIGURE is a circuit diagram of an over current protection circuit for an electronic device in accordance with an exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    Embodiments of the disclosure are now described in detail with reference to the drawing. 
         [0009]    Referring to the FIGURE, an over current protection circuit  100 , according to an exemplary embodiment, is configured to provide over current protection to an electronic device  200 . The electronic device  200  includes an input terminal  202  connected to a power source Vcc and an output terminal  204 . In one non-limiting embodiment, the electronic device  200  is a fan, but the disclosure is not limited thereto. 
         [0010]    The over current protection circuit  100  includes a switching element K 1 , a voltage dividing resistor Rf, a voltage detecting circuit  10 , a pulse generation circuit  20 , a RC discharging circuit  30 , a comparison circuit  40 , and a force restart circuit  50 . 
         [0011]    The switching element K 1  includes a first terminal d, a second terminal s, and a control terminal g. The control terminal g is used to control connection and disconnection between the first terminal d and the second terminal s. The first terminal d is coupled to the output terminal  204  of the electronic device  200 . The second terminal s is grounded via the voltage dividing resistor Rf. In this embodiment, the switching element K 1  is a p-channel metal oxide semiconductor (PMOS) transistor, wherein the first terminal d is the drain, the second terminal s is the source, and the control terminal g is the gate. 
         [0012]    The voltage detecting circuit  10  includes an amplifier Q 1 , a first capacitor C 1 , and a first resistor R 1 . The amplifier Q 1  includes a positive input terminal coupled to the second terminal s of the switching element K 1 , a negative input terminal that is grounded, and an output terminal. The first capacitor C 1  includes a first terminal coupled to the output terminal of the amplifier Q 1  and a second terminal that is grounded. The first resistor R 1  includes a first terminal coupled to the output terminal of the amplifier Q 1  and a second terminal that is grounded. 
         [0013]    The pulse generation circuit  20  includes a first comparator A 1 , a second comparator A 2 , a second resistor R 2 , a third resistor R 3 , and a first transistor K 2 . The first comparator A 1  includes a positive input terminal coupled to the output terminal of the amplifier Q 1 , a negative input terminal, and an output terminal. The second comparator A 2  includes a positive input terminal coupled to the output terminal of the first comparator A 1 , a negative input terminal coupled to a first reference voltage Vref 1 , and an output terminal. The second resistor R 2  includes a first terminal coupled to the negative input terminal of the second comparator A 2  and a second terminal coupled to the negative input terminal of the first comparator A 1 . The third resistor R 3  includes a first terminal coupled to the negative input terminal of the first comparator A 1  and a second terminal. The first transistor K 2  is a pnp transistor of which the collector c is coupled to the second terminal of the third resistor R 3 , the emitter e is grounded, and the base b is coupled to the output terminal of the first comparator A 1 . 
         [0014]    The RC discharging circuit  30  includes a second capacitor C 2  and a fourth resistor R 4 . The second capacitor C 2  includes a first terminal coupled to the output terminal of the second comparator A 2  and a second terminal that is grounded. The fourth resistor R 4  includes a first terminal coupled to the output terminal of the second comparator A 2  and a second terminal that is grounded. 
         [0015]    The comparison circuit  40  includes a third comparator A 3 . The third comparator A 3  includes a negative input terminal coupled to the output terminal of the second comparator A 2 , a positive input terminal coupled to a second reference voltage Vref 2 , and an output terminal coupled to the control terminal of the switching element K 1 . 
         [0016]    The force restart circuit  50  includes a monopole single throw switch S, a third capacitor C 3 , a fifth resistor R 5 , a sixth resistor R 6 , and a second transistor K 3 . The monopole single throw switch S includes a first terminal coupled to the power source Vcc and a second terminal. The third capacitor C 3  includes a first terminal coupled to the second terminal of the monopole single throw switch S and second terminal grounded. The fifth resistor R 5  includes a first terminal coupled to the first terminal of the third capacitor C 3  and a second terminal. The sixth resistor R 6  includes a first terminal coupled to the second terminal of the fifth resistor R 5  and a second terminal grounded. The second transistor K 3  is a pnp transistor of which the collector c is coupled to the negative input terminal of the third comparator A 3 , the emitter e is grounded, and the base b is coupled to the second terminal of the sixth resistor R 6 . 
         [0017]    In a normal operating condition, the control terminal g of the switching element K 1  is at a low level signal (e.g., logical “0”). Therefore, the first terminal d and the second terminal s of the switching element K 1  are conducted, and the electronic device  200  is powered by the power source Vcc. The positive input terminal of the amplifier Q 1  acquires a divided voltage of the voltage dividing resistor Rf. The amplifier Q 1  amplifies the divided voltage and outputs the amplified divided voltage to the positive input terminal of the first comparator A 1 , and charges the first capacitor C 1 . The first comparator A 1  compares the amplified divided voltage with the first reference voltage Vref 1 . If the amplified divided voltage is lower than the first reference voltage Vref 1 , then current in the electronic device  200  is at or below a predetermined safe level, and the first comparator A 1  outputs a low level signal to the positive input terminal of the second comparator A 2  and the base of the first transistor K 2 . In this embodiment, the first reference voltage Vref 1  is lower than a high level signal (e.g., logical “1”) and higher than the low level signal, and the threshold voltage of the first transistor is higher than the low level signal and lower than the high level signal. The first transistor K 2  remains in the cut-off state. The second comparator A 2  compares the low level signal with the first reference voltage Vref 1 , and outputs a low level signal to the negative input terminal of the third comparator A 3 . In this embodiment, the second reference voltage Vref 2  is lower than the high level signal and higher than the low level signal. The third comparator A 3  compares the low level signal with the second reference voltage Vref 2 , and outputs a low level signal to the control terminal g of the switching element K 1 . The switching element K 1  remains on. 
         [0018]    If the amplified divided voltage exceeds the first reference voltage Vref 1 , then current in the electronic device  200  exceeds the predetermined safe level, the electronic device  200  is in the over current state. The first comparator A 1  outputs a high level signal to the positive input terminal of the second comparator A 2  and the base b of the first transistor K 2 . The collector c and the emitter e of the first transistor K 2  are conducted. The second comparator A 2  compares the high level signal with the first reference voltage Vref 1 , and outputs a high level signal to the negative input terminal of the third comparator A 3 . The third comparator A 3  compares the high level signal with the second reference voltage Vref 2 , and outputs a high level signal to the control terminal g of the switching element K 1 . The switching element K 1  turns off power to the electronic device  200 . 
         [0019]    After the switching element K 1  turns off, the first capacitor C 1  discharges quickly. As the collector and the emitter of the first transistor K 2  are conducted, the voltage of the negative input terminal of the first comparator A 1  is [R 3 /(R 3 +R 2 )]*Vref 1 . During the initial discharge, the discharge voltage of the first capacitor C 1  is higher than the [R 3 /(R 3 +R 2 )]*Vref 1 , the first comparator A 1  outputs a high level signal to the positive input terminal of the second comparator A 2 . The second comparator A 2  compares the high level signal with the first reference voltage Vref 1 , and outputs a high level signal. Then, the second capacitor C 2  is charged by the high level signal. When the discharge voltage of the first capacitor C 1  is lower than the [R 3 /(R 3 +R 2 )]*Vref 1 , the first comparator A 1  outputs a low level signal to the positive input terminal of the second comparator A 2  and the base b of the first transistor K 2  simultaneously. The first transistor K 2  turns off. The second comparator A 2  compares the low level signal with the first reference voltage Vref 1 , and outputs a low level signal. Then, the second capacitor C 2  generates a discharging voltage to the negative input terminal of the third comparator A 3 . The third comparator A 3  compares the discharging voltage with the second reference voltage Vref 2 . When the discharging voltage of the second capacitor is lower than the second reference voltage Vref 2 , the third comparator A 3  outputs a low level signal to the control terminal g of the switching element K 1 . The switching element K 1  turns on again, and the electronic device  200  receives power. 
         [0020]    Alternatively, when power supply of the electronic device  200  is turned off by the over current protection circuit  100 , a user can turn off the monopole single throw switch S. Then, the second transistor K 3  turns on, and the collector of the second transistor K 3  is grounded. The output terminal of the third comparator A 3  output a low level signal. The switching element K 1  turns on, and the electronic device  200  receives power again. 
         [0021]    It will be understood that the above particular embodiments and methods are shown and described by way of illustration only. The principles and the features of the present invention may be employed in various and numerous embodiment thereof without departing from the scope of the invention as claimed. The above-described embodiments illustrate the scope of the invention but do not restrict the scope of the invention.