Abstract:
A method and apparatus controls the memory data access of memory devices in order to utilize partially defective memory devices to construct usable memory chip or module assemblies that meet the specification of a fully or partially functional assembly.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to semiconductor memory devices, memory chips, memory modules, and the handling of defective memory components.  
           [0002]    Due to the yield limitation of semiconductor fabrication process, a semiconductor memory wafer usually contains defective memory devices. As the cell density of the semiconductor device increases, it is becoming harder to achieve high production yield.  
           [0003]    During the device fabrication process, certain repairing process may be used to replace defective rows or columns in the memory cell array. However, there is a limit as to the capability of such repairing process. Certain memory devices remain defective at the semiconductor die level after the fabrication process.  
           [0004]    To repair the memory devices above the die level is a complex issue regarding feasibility, efficiency, and performance.  
         BRIEF SUMMARY OF THE INVENTION  
         [0005]    This invention proposes a method and apparatus to efficiently utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a functional package.  
           [0006]    This invention provides a method that maximizes the usage of non-defective memory data bits in the partially defective memory devices.  
           [0007]    The present invention provides a method that simplifies the production and process of memory chips or modules.  
           [0008]    This invention further provides a method to minimize or eliminate the initialization of the chips or modules. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 is a diagram of a prior art memory chip.  
         [0010]    [0010]FIG. 2 is a diagram of a prior art memory module.  
         [0011]    [0011]FIG. 3 shows a preferred embodiment of the present invention for a memory chip package.  
         [0012]    [0012]FIG. 4 shows a preferred embodiment of the present invention for a memory access controller.  
         [0013]    [0013]FIG. 5 shows another preferred embodiment of the present invention for a memory access controller.  
         [0014]    [0014]FIG. 6 shows a preferred embodiment of the present invention for a memory module package.  
         [0015]    [0015]FIG. 7 shows a preferred embodiment of the present invention for a data selector in a memory access controller for FIG. 6.  
         [0016]    [0016]FIG. 8 shows a preferred embodiment of the present invention for a memory access controller for FIG. 6.  
         [0017]    [0017]FIG. 9 shows another preferred embodiment of the present invention for a memory module package.  
         [0018]    [0018]FIG. 10 shows a preferred embodiment of the present invention for a data selector in a memory access controller for FIG. 9.  
         [0019]    [0019]FIG. 11 shows a different preferred embodiment of the present invention for a memory module package.  
         [0020]    [0020]FIG. 12 shows a preferred embodiment of the present invention for a data selector in a memory access controller for FIG. 11.  
         [0021]    [0021]FIG. 13 shows a still another preferred embodiment of the present invention for a memory module package.  
         [0022]    [0022]FIG. 14 shows another different preferred embodiment of the present invention for a memory module package. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]    The present invention will be illustrated with some preferred embodiments.  
         [0024]    [0024]FIG. 1 is a diagram of a prior art memory chip. The memory device  101  contains device data port  102 , a memory address unit  103 , and a memory control unit  104 , and a memory cell array  105 . The device data port  102  is connected to the chip data bus  106 . The device address unit  103  is connected to the chip address bus  107 . The device control unit  104  is connected to the chip control bus  108 .  
         [0025]    [0025]FIG. 2 is a diagram of a prior art memory module. The memory module data ports  201  are connected to the corresponding chip data ports of the memory chip  202 . This combination constitutes a memory unit  203 . This memory module contains a total of eight memory units. The module is built on a printed circuit board  204  with an edge connection  205  to interface with other system components.  
         [0026]    [0026]FIG. 3 shows a preferred embodiment of the present invention for a memory chip package. The memory access controller  303  controls the data input and output of the two memory devices  301  and  302 .  
         [0027]    In memory device  301 , the memory cell array is divided into eight memory blocks. Each memory block contains four memory data segments. Assuming a memory data width of eight, each data segment contains two data bits.  
         [0028]    Memory device  301  contains defective memory cells within memory blocks  304 ,  305 ,  306 , and  307 . Memory device  302  contains defective memory cells within memory blocks  308 ,  309 ,  310 ,  311 , and  312 . For defective memory blocks  304  and  307  in memory device  301 , the corresponding memory blocks in m memory device  302  are fully functional. For defective memory blocks  305  and  306  in memory device  301 , the corresponding memory blocks in memory device  302  are blocks  311 , and  312 . Although memory blocks  311 , and  312  are not fully functional, for the defective data segments in blocks  305  and  306 , the corresponding data segments in blocks  311 , and  312  are functional.  
         [0029]    [0029]FIG. 4 shows a preferred embodiment of a memory access controller for the memory chip package in FIG. 3. The memory access controller  401  consists of a data routing unit  402  and a data control unit  403 .  
         [0030]    The data control unit  403  receives the status of the memory blocks and data segments from the memory status unit  404 . The memory status unit  404  contains a table with eight entries, one for each memory block in memory device  301 . Each table entry contains four status bits, one for each data segment within the corresponding memory block. The status bit value is a 0 if the corresponding data segment is functional. The value is a 1 if the corresponding data segment is defective.  
         [0031]    Upon control signals, a decoder logic block  405  decodes three block address lines  406  into eight block selection lines. The decoded block selection line selects the memory status entry in selection logic unit  407  and sends the selected entry  408  to the memory data routing unit  402 .  
         [0032]    The memory data routing unit  402  routes the selected memory data bits to the memory data bus for memory read and write operations. The memory data routing unit  402  consists of four data multiplexing elements. Each multiplexing element controls a 2-bit data segment.  
         [0033]    Assuming a memory block address of 4, which corresponds to memory block  306  in FIG. 3, the selected status entry is binary 0010. For data segments  0 ,  1 , and  3 , the control bits are 0. The corresponding data segments on the memory data bus  411  are connected to the data segments on the memory data lines  409  for memory device  301 . For data segments  2 , the control bit is a 1. The corresponding data segment on the memory data bus is connected to the data segment on the memory data lines  410  for memory device  302 .  
         [0034]    [0034]FIG. 5 shows another preferred embodiment of a memory access controller for the memory chip package in FIG. 3. The memory access controller  501  consists of a data routing unit  502  and a data control unit  503 .  
         [0035]    In this embodiment, the memory status unit  504  is constructed in a different fashion. It contains an entry for each defective memory block in FIG. 3. Beside the memory data status bits, each status entry also contains the block address of the defective block. For example, there is an entry with a block address  4  and status bits 0010 binary.  
         [0036]    Upon control signals, the block address unit  505  routes the block address lines  506  to the selection logic unit  507 . The selection logic unit  507  compares the address lines with the defective block addresses in the status table and sends the selected entry  508  to the memory data routing unit  502 .  
         [0037]    The memory data routing unit  502  routes the selected memory data bits to the memory data bus for memory read and write operations. The memory data routing unit  502  consists of four data multiplexing elements. Each data routing element controls a 2-bit data segment.  
         [0038]    [0038]FIG. 6 shows a preferred embodiment of the present invention for a memory module package. The first group of memory chips contains four memory units  601 . The second group of memory chips contains four other memory units  602 . The memory access controller  603  controls the data routing of these two memory groups.  
         [0039]    [0039]FIG. 7 shows a preferred embodiment of the present invention for a data selector in a memory access controller for FIG. 6. The memory data routing unit  701  consists of 16 data multiplexing elements. Each multiplexing element controls a 2-bit data segment within a memory chip. These multiplexing elements are grouped into 4 multiplexing element units  702 , one for each 8-bit memory byte. In this preferred embodiment, a data multiplexing element consists of two 2-to- 1 data multiplexing components.  
         [0040]    For a control bit of 1 on the control line  703 , the corresponding data segment on the memory data bus is connected to the data segments on the memory data lines  704  for memory device  601 . For a control bit of 1, the corresponding data segment on the memory data bus is connected to the data segment on the memory data lines  705  for memory device  602 .  
         [0041]    As an example, assume that there are thirty-two data bits D 0  to D 31 . Data multiplexing unit number  0  supports data bits D 0  to D 7 . Data multiplexing unit number  1  supports data bits D 8  to D 15 . Data multiplexing unit number  2  supports data bits D  16  to D 23 . Data multiplexing unit number  3  supports data bits D 24  to D 31 .  
         [0042]    [0042]FIG. 8 shows a preferred embodiment of a memory access controller for the memory chip package in FIG. 6. The memory access controller  801  consists of a data routing unit  802  and a data control unit  803 .  
         [0043]    The data control unit  803  receives the status of the memory blocks and data segments from the memory status unit  804 . The memory status unit  804  contains a table with eight entries, one for each memory block in memory group  601 . Each table entry now contains 16 status bits, 4 for each memory chip and 1 for each data segment within the memory chips.  
         [0044]    For the same reason, the memory data routing unit  802  consists of 16 data multiplexing elements as illustrated in FIG. 7.  
         [0045]    [0045]FIG. 9 shows another preferred embodiment of the present invention for a memory module package. The first group of memory chips contains four memory units  901 . The second group of memory chips contains one memory unit  902 . The memory access controller  903  controls the data routing of these two memory groups.  
         [0046]    [0046]FIG. 10 shows a preferred embodiment of the present invention for a data selector in a memory access controller for FIG. 9. The memory data routing unit  1001  consists of 16 data multiplexing elements. Each multiplexing element controls a 2-bit data segment within a memory chip. These multiplexing elements are grouped into 4 multiplexing element units  1002 , one for each 8-bit memory byte. In this preferred embodiment, a data multiplexing element consists of two 2-to-1 data multiplexing components.  
         [0047]    For a control bit of 1 on the control lines  1003 , the corresponding data segment on the memory data bus is connected to the data segments on the memory data lines  1004  for memory group  901 . For a control bit of 1, the corresponding data segment on the memory data bus is connected to the data segment on the memory data lines  1005  for memory group  902 .  
         [0048]    For FIG. 9 and FIG. 10, the memory data lines  1005  are from the same chip in memory group  902 . It differs from FIG. 6 and FIG. 7 where the memory data lines  705  are from four different chips in memory group  602 .  
         [0049]    In this preferred embodiment, a functional data segment in  902  can only replace a defective data segment at the corresponding chip location in memory group  901 .  
         [0050]    [0050]FIG. 11 shows another preferred embodiment of the present invention for a memory module package. The first group of memory chips contains four memory units  1101 . The second group of memory chips contains one memory unit  1102 . The memory access controller  1103  controls the data routing of these two memory groups.  
         [0051]    In this preferred embodiment, three defective data segments  1104  are at the same chip location, a situation that is not curable with a data selector in FIG. 10.  
         [0052]    [0052]FIG. 12 shows a preferred embodiment of the present invention for a data selector in a memory access controller for FIG. 11. The memory data routing unit  1201  consists of 16 data multiplexing elements. Each multiplexing element controls a 2-bit data segment within a memory chip. These multiplexing elements are grouped into 4 multiplexing element units  1202 , one for each 8-bit memory byte. In this preferred embodiment, a data multiplexing element consists of two 5-to-1 data multiplexing components.  
         [0053]    For each data segment on the memory data bus, the control signal on the control lines  1203  selects either the corresponding data segment from memory group  1101  or any of the 4 data segments in memory group  1102 . This arrangement can repair any 4 defective data segments at one memory block location.  
         [0054]    [0054]FIG. 13 shows another preferred embodiment of the present invention for a memory module package. The first group of memory chips contains four memory units  1301 . The second group of memory chips contains one memory unit  1302 . The memory access controller  1303  controls the data routing of these two memory groups.  
         [0055]    In this preferred embodiment, there is an address-mapping unit  1304  that converts the memory block address on the memory address bus to memory block addresses to the memory units.  
         [0056]    As illustrated, memory block number  0  originally contains more than 4 defective data segments. After an address mapping to exchange the memory block  1305  and memory block  1306  in the third unit for D 16  to D 23  in memory group  1301 , the new memory block number  0  contains only 4 defective data segments. At the same time, memory block number  4  also contains just 4 defective data segments.  
         [0057]    In fact, the memory structure of FIG. 13 after the address mapping is the same as the memory structure shown in FIG. 11.  
         [0058]    [0058]FIG. 14 shows another different preferred embodiment of the present invention for a memory module package. The memory access controller  1403  controls the data routing of the memory groups  1401  and  1402 . The address-mapping unit  1404  converts the memory block address on the memory address bus to memory block addresses to the memory units.  
         [0059]    The memory address-mapping unit  1404  reassigns the address space for the memory units in order to place them in the appropriate memory regions. First, the number of defective data segments is kept within the 4-segment limit whenever possible. Second, any memory blocks that cannot be kept within the 4-segment limit are mapped to the high address regions such that the memory module can be used in a degraded manner. In this preferred embodiment, six of the eight memory regions remain functional after the mapping.