Abstract:
A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity thereof. The super-junction semiconductor device includes a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer on low resistance layer, and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer including regions of a first conductivity type and regions of a second conductivity type arranged alternately with each other. The second alternating conductivity type layer including regions of the first conductivity type and regions of the second conductivity type arranged alternately with each other. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer.

Description:
FIELD OF THE INVENTION 
     The present invention relates to semiconductor devices which include, between the major surfaces thereof, a layer with low electrical resistance and an alternating conductivity type layer formed of regions of a first conductivity type and regions of a second conductivity type alternately arranged with each other. Specifically, the present invention relates to vertical semiconductor devices, which facilitate the realization of a high breakdown voltage and a high current capacity, such as MOSFET&#39;s (insulated gate field effect transistors), IGBT&#39;s (conductivity-modulation-type MOSFET&#39;s), bipolar transistors and diodes. The present invention relates also to the method of manufacturing the semiconductor devices described above. 
     BACKGROUND 
     The semiconductor devices may be roughly classified into lateral semiconductor devices arranged with electrodes on a major surface, and vertical semiconductor devices which distribute electrodes on both major surfaces facing opposite to each other. When the vertical semiconductor device is ON, a drift current flows in the thickness direction of the semiconductor chip (vertical direction). When the vertical semiconductor device is OFF, the depletion layers caused by applying a reverse bias voltage also expands in the vertical direction. 
     FIG. 7 is a cross sectional view of a conventional planar-type n-channel vertical MOSFET. Referring now to FIG. 7, the vertical MOSFET includes an n + -type drain layer  11  with low electrical resistance, a drain electrode  18  in electrical contact with n + -type drain layer  11 , a highly resistive n − -type drift layer  12  on n + -type drain layer  11 , p-type base regions  13  formed selectively in the surface portion of n − -type drift layer  12 , a heavily doped n + -type source region  14  formed selectively in p-type base region  13 , a gate insulation film  15  on the extended portion of p-type base region  13  extended between n + -type source region  14  and n − -type drift layer  12 , a gate electrode layer  16  on gate insulation film  15 , and a source electrode  17  in electrical contact commonly with n + -type source regions  14  and p-type base region  13 , and a drain electrode  18  on the back surface of n + -type drain layer  11 . 
     In the vertical semiconductor device shown in FIG. 7, highly resistive n − -type drift layer  12  works as a region for making a drift current flow vertically when the MOSFET is in the ON-state. In the OFF-state of the MOSFET, n-type drift layer  12  is depleted, causing a high breakdown voltage. Thinning highly resistive n − -type drift layer  12 , that is shortening the drift current path, is effective for substantially reducing the on-resistance (resistance between the drain and the source) of the MOSFET, since the drift resistance is lowered in the ON-state of the device. However, since the space between the drain and the source, into that the depletion layers expand from the pn-junctions between p-type base regions  13  and n − -type drift layer  12  in the OFF-state of the device, is narrowed by shortening the drift current path in n − -type drift layer  12 , the electric field strength in the depletion layers soon reaches the maximum (critical) value for silicon. Therefore, breakdown is caused before the voltage between the drain and the source reaches the designed breakdown voltage of the device. 
     A high breakdown voltage is obtained by thickening n − -type drift layer  12 . However, a thick n − -type drift layer  12  inevitably causes high on-resistance and loss increase. In short, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage of the MOSFET. 
     The tradeoff relation exists in the other semiconductor devices, such as IGBT&#39;s, bipolar transistors and diodes. The tradeoff relation exists also in the lateral semiconductor devices, therein the flow direction of the drift current in the ON-state of the devices is different from the expansion direction of the depletion layers in the OFF-state of the devices. 
     European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, and Japanese Unexamined Laid Open Patent Application H09(1997)-266311 disclose semiconductor devices, which reduce the tradeoff relation described above by employing an alternating-conductivity-type drift layer formed of heavily doped n-type regions and p-type regions alternately laminated horizontally with each other. 
     FIG. 8 is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to FIG. 8, the vertical MOSFET of FIG. 8 is different from the vertical MOSFET of FIG. 7 in that the vertical MOSFET of FIG. 8 includes an alternating conductivity type drift layer  22  that is not a single-layered one but formed of n-type drift regions  22   a  and p-type partition regions  22   b  alternately laminated horizontally with each other. In FIG. 8, p-type base regions  23 , n + -type source regions  24 , gate insulation film  25 , gate electrodes  26 , a source electrode  27 , and a drain electrode  28  are also shown. 
     Drift layer  22  is formed in the following way. A highly resistive n-type layer is formed epitaxially on n + -type drain layer  21  as a substrate. Trenches are dug selectively in the n-type layer down to n + -type drain layer  21  by etching, leaving n-type drift regions  22   a.  Then, p-type partition regions  22   b  are formed by epitaxially growing p-type layers in the trenches. 
     The alternating conductivity type layer provides a drift current path in the ON-state of the device and is depleted in the OFF-state of the device. Hereinafter, the semiconductor device including an alternating conductivity type drift layer will be referred to as the “super-junction semiconductor device”. 
     The dimensions and the impurity concentrations of the constituent elements in the super-junction semiconductor device described in U.S. Pat. No. 5,216,275 are as follows. Assuming that the breakdown voltage is V B , drift layer  22  is 0.024 V B   1.2  (μm) in thickness, and n-type drift region  22   a  and p-type partition region  22   b  have the same width b and the same impurity concentration, the impurity concentrations in n-type drift region  22   a  and p-type partition region  22   b  are expressed by 7.2×10 16 V B   −0.2 /b(cm −3 ). When V B =800 V and b=5 μm, drift layer  22  is 73 μm in thickness and the impurity concentration thereof is 1.9×10 16  cm −3 . Obviously, the alternating conductivity type drift layer reduces the on-resistance, since the impurity concentration in the single-layered drift layer is around 2×10 14  cm- 3 . However, it is very difficult for the epitaxial growth technique available at present to bury semiconductor layers with a good quality in such narrow and deep trenches, that is trenches with a large aspect ratio. 
     As described above, the tradeoff relation between the on-resistance and the breakdown voltage poses a problem also on the lateral semiconductor devices. European Patent 0 053 854, U.S. Pat. No. 5,438,215, and Japanese Unexamined Laid Open Patent Application H09(1997)-266311 disclose also lateral super-junction semiconductor devices and the methods of manufacturing the lateral super-junction semiconductor devices. The disclosed methods employ selective etching to dig trenches and epitaxial growth to bury the trenches. It is not so difficult for the selective etching technique and the epitaxial growth technique to form the alternating-conductivity-type drift layer for the lateral super-junction semiconductor device, since the lateral alternating-conductivity-type drift layer is formed by laminating thin epitaxial layers vertically. 
     However, the conventional selective etching and epitaxial growth techniques are not so effective to form the vertical alternating-conductivity-type drift layer described in U.S. Pat. No. 5,216,275. Japanese Unexamined Laid Open Patent Application H09(1997)-266311 describes a nuclear transformation technique that uses a neutron beam and such a radioactive ray for forming n-type regions and p-type regions in the alternating-conductivity-type drift layer. However, it is not so easy to apply the nuclear transformation technique which employs large facilities. 
     For reducing the chip size of the conventional super-junction semiconductor device, it is necessary to reduce the dimensions of the constituent layers and regions constituting the surface semiconductor structure of the device. The reduced dimensions inevitably lower the mass-productivity of the device. Change of the surface structure causes additional manufacturing costs. 
     In view of the foregoing, it would be desirable to provide a super-junction semiconductor device that facilitates reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity. It would further be desirable to provide the method for manufacturing a super-junction semiconductor device easily with excellent mass-productivity. 
     SUMMARY OF THE INVENTION 
     According to an aspect of the invention, there is provided a semiconductor device including: a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer above the layer with low electrical resistance, the first alternating conductivity type layer including one or more first regions of a first conductivity type and second regions of a second conductivity type, the one or more first regions and the second regions forming first pn-junctions therebetween; and a second alternating conductivity type layer in plane contact with the first alternating conductivity type layer, the second alternating conductivity type layer including one or more third regions of the first conductivity type and fourth regions of the second conductivity type, the one or more third regions and the fourth regions forming second pn-junctions therebetween; the second pn-junctions in the second alternating conductivity type layer being spaced apart from each other more widely than the first pn-junctions in the first alternating conductivity type layer. 
     Advantageously, the boundary between the first alternating conductivity type layer and the second alternating conductivity type layer extends almost in parallel to the first major surface. 
     Advantageously, the second alternating conductivity type layer is between the first alternating conductivity type layer and the first major surface. 
     Advantageously, the surfaces of the first pn-junctions in the first alternating conductivity type layer are almost perpendicular to surfaces of the second pn-junctions in the second alternating conductivity type layer. 
     Advantageously, the one or more first regions of the first conductivity type in the first alternating conductivity type layer are connected to the one or more third regions of the first conductivity type in the second alternating conductivity type layer, and the second regions of the second conductivity type in the first alternating conductivity type layer are connected to the fourth regions of the second conductivity type in the second alternating conductivity type layer. 
     Advantageously, the one or more third regions and the fourth regions in second alternating conductivity type layer are arranged differently from the one or more first regions and the second regions in first alternating conductivity type layer. 
     The super-junction semiconductor device according to the invention, in that the spacing between the second pn-junctions in the second alternating conductivity type layer is wider than the spacing between the first pn-junctions in the first alternating conductivity type layer, facilitates reducing the on-resistance without condensing the surface structure of the semiconductor chip and, therefore, without increasing the manufacturing costs. Even when the boundary between the first alternating conductivity type layer and the second alternating conductivity type layer extends in perpendicular to the first major surface, the on-resistance is reduced without condensing the surface structure of the semiconductor chip. Since the super-junction semiconductor device according to the invention reduces the on-resistance simply by narrowing the spacing between the pn-junctions in the alternating conductivity type layer inside the semiconductor chip, the costs of mass-producing the super-junction semiconductor device are reduced. 
     According to another aspect of the invention, there is provided the method of manufacturing a semiconductor device including a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer above the layer with low electrical resistance, the first alternating conductivity type layer being formed of one or more first regions of a first conductivity type and second regions of a second conductivity type, the one or more first regions and the second regions forming first pn-junctions therebetween; and a second alternating conductivity type layer in plane contact with the first alternating conductivity type layer, the second alternating conductivity type layer being formed of one or more third regions of the first conductivity type and fourth regions of the second conductivity type, the one or more third regions and the fourth regions forming second pn-junctions therebetween; the second pn-junctions in the second alternating conductivity type layer being spaced apart from each other more widely than the first pn-junctions in the first alternating conductivity type layer, the method including the steps of: (a) forming an epitaxial layer; (b) implanting an impurity of the second conductivity type selectively into first surface portions of the epitaxial layer; (c) implanting an impurity of the first conductivity type selectively into second surface portions of the epitaxial layer; (d) repeating the steps (a) through (c) as many times as necessary; and (e) thermally driving all the implanted impurities, whereby to form the first alternating conductivity type layer and the second alternating conductivity type layer. Preferably, the steps (a) through (c) are repeated three times or more. 
     The method of manufacturing the super-junction semiconductor device according to the invention facilitates changing the spacing between the pn-junctions in the second alternating conductivity type layer on the side of the first major surface form the spacing between the pn-junctions in the first alternating conductivity type layer on the side of the second major surface. In other words, the method of manufacturing the super-junction semiconductor device according to the invention facilitates reducing the on-resistance simply by narrowing the spacing between the pn-junctions in the alternating conductivity type layer inside the semiconductor chip. Therefore, the method of manufacturing the super-junction semiconductor device according to the invention is effective to reduce the costs of mass-producing the super-junction semiconductor devices. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES 
     The invention will be described with reference to certain preferred embodiments and the accompanying drawings, wherein: 
     FIGS.  1 ( a ) through  1 ( i ) are cross sectional views for explaining the steps for manufacturing a super-junction semiconductor device according to the first embodiment of the invention; 
     FIGS.  2 ( a ) through  2 ( f ) are top plan views for explaining the steps for manufacturing a super-junction semiconductor device according to the second embodiment of the invention; 
     FIG.  2 ( g ) is a perspective view of the super-junction semiconductor device according to the second embodiment of the invention; 
     FIGS.  3 ( a ) through  3 ( f ) are top plan views for explaining the steps for manufacturing a super-junction semiconductor device according to the third embodiment of the invention; 
     FIG.  3 ( g ) is a vertical cross section along A-A′ of FIG.  3 ( f ); 
     FIGS.  4 ( a ) through  4 ( f ) are top plan views for explaining the steps for manufacturing a super-junction semiconductor device according to the fourth embodiment of the invention; 
     FIG.  4 ( g ) is a vertical cross section along B-B′ of FIG.  4 ( f ); 
     FIGS.  5 ( a ) through  5 ( f ) are cross sectional views for explaining the steps for manufacturing a super-junction semiconductor device according to the fifth embodiment of the invention; 
     FIG. 6 is a cross sectional view of the super-junction semiconductor device according to the fifth embodiment of the invention; 
     FIG. 7 is a cross sectional view of a conventional planar-type n-channel vertical MOSFET; and 
     FIG. 8 is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides a super-junction semiconductor device that includes a semiconductor chip having a first major surface and a second major surface. The semiconductor chip includes a layer with low electrical resistance on the side of the second major surface and two or more alternating conductivity type layers between the layer with low electrical resistance and the first major surface. Each alternating conductivity type layer includes one or more regions of a first conductivity type and regions of a second conductivity type spaced apart from each other by the one or more regions of the first conductivity type. The alternating conductivity type layers provide a drift current path in the ON-state of the device and are depleted in the OFF-state of the device. 
     First Embodiment 
     FIGS.  1 ( a ) through  1 ( i ) are cross sectional views explaining the steps for manufacturing a super-junction semiconductor device according to a first embodiment of the invention employing the ion implantation technique. 
     The super-junction semiconductor device according to the first embodiment includes a first alternating conductivity type layer on a layer with low electrical resistance and a second alternating conductivity type layer on the first alternating conductivity type layer. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer. The regions of the first conductivity type and the regions of the second conductivity type in the second alternating conductivity type layer are extended in parallel to the regions of the first conductivity type and the regions of the second conductivity type in the first alternating conductivity type layer. 
     Referring now to FIG.  1 ( a ), a highly resistive n − -type layer  2 A is deposited epitaxially on an n-type substrate  1  with low electrical resistance. The n − -type layer  2 A is 4 μm in thickness. 
     Referring now to FIG.  1 ( b ) a resist mask  5 A is formed on n − -type layer  2 A by photolithography. Boron ions  6  are implanted as p-type impurity ions into first surface portions of n − -type layer  2 A at the dose amount of 2×10 13  cm −2  of boron atoms  7 . Resist mask  5 A includes first windows, through which boron ions  6  are implanted. The first windows are 2 μm in width and spaced apart for 6 μm from each other. 
     Referring now to FIG.  1 ( c ), resist mask  5 A is removed. Then, a resist mask  5 B having second windows is formed on n − -type layer  2 A by photolithography such that the second windows are at the midpoints between the first windows of resist mask  5 A. The second windows of resist mask  5 B are 2 μm in width and spaced apart for 6 μm from each other. Phosphorus ions  3  are implanted as n-type impurity ions through the second windows into second surface portions of n − -type layer  2 A at the dose amount of 2×10 13  cm −2  of phosphorus atoms  4 . 
     Referring now to FIG.  1 ( d ), the steps described above with reference to FIGS.  1 ( a ) through  1 ( c ) are repeated as many times as necessary. 
     Referring now to FIG.  1 ( e ) resist mask  5 B is removed. A highly resistive n − -type layer  2 B of 6 μm in thickness is deposited epitaxially on the uppermost n − -type layer  2 A. Then, a resist mask  5 C having third windows is formed on n − -type layer  2 B by photolithography. Boron ions  6  are implanted through the third windows into first surface portions of n − -type layer  2 B at the dose amount of 1×10 13  cm −2  of boron atoms  7 . The third windows in resist mask  5 C are wider than the first windows in FIG.  1 ( b ) or the second windows in FIG.  1 ( c ) and spaced apart from each other more widely than the first windows or the second windows. More in detail, third windows in resist mask  5 C are 4 μm in width and spaced apart for 12 μm from each other. The third windows in resist mask  5 C are positioned above every other location of the first windows in resist mask  5 A. 
     Referring now to FIG.  1 ( f ), resist mask  5 C is removed. Then, a resist mask  5 D having fourth windows is formed on n − -type layer  2 B by photolithography such that the fourth windows are at the midpoints between the third windows of resist mask  5 C. The fourth windows in resist mask  5 D are 4 μm in width and spaced apart for 12 μm from each other. Phosphorus ions  3  are implanted through the fourth windows into second surface portions of n − -type layer  2 B at the dose amount of 1×10 13  cm −2  of phosphorus atoms  4 . Resist mask  5 D is patterned in such a way that the pattern of resist mask  5 D is a displacement of the pattern of resist mask  5 C. The fourth windows in resist mask  5 D are positioned above the centers of the spaces between the third windows in resist mask  5 C. 
     Referring now to FIG.  1 ( g ), resist mask  5 D is removed. A highly resistive n − -type layer  2 C of 8 μm in thickness is deposited epitaxially on n − -type layer  2 B. 
     Referring now to FIG.  1 ( h ), a first alternating conductivity type layer and a second alternating conductivity type layer on the first alternating conductivity type layer are formed by thermally treating the laminate including n − -type layers  2 A,  2 B and  2 C formed so far at 1150° C. for 20 hours to drive all the implanted impurity atoms. The first alternating conductivity type layer is formed of n-type drift regions  8   a  and p-type partition regions  8   b  arranged alternately with each other. The second alternating conductivity type layer is formed of n-type drift regions  18   a  and p-type partition regions  18   b  arranged alternately with each other. 
     Referring now to FIG.  1 ( i ), n-type drain regions  29  are formed on n-type drift regions  18   a  and p-type partition regions  18   b.  Then, a surface MOSFET structure is formed through the conventional steps of forming the MOSFET structure. 
     More in detail, n-type drain regions  29  are formed in the surface portion of the semiconductor chip by selective implanting impurity ions and by thermally driving the implanted impurity atoms. Gate insulation films  25  are formed by thermal oxidation. A polycrystalline silicon film is deposited by the vacuum CVD method and gate electrode layers  26  are formed by patterning the deposited polycrystalline silicon film by photolithography. Then, p-type base regions  23 , n + -type source regions  24  and p + -type contact regions  30  are formed by selective implanting impurity ions and by thermally driving the implanted impurity atoms. Then, an insulation film  31  is deposited and windows are opened through insulation film  31  by photolithography. Aluminum alloy films are deposited. A source electrode  27 , a drain electrode  28  and not shown gate electrodes are formed by patterning the deposited aluminum alloy films. Thus, a MOSFET is obtained. 
     Second Embodiment 
     FIGS.  2 ( a ) through  2 ( f ) are top plan views for explaining the steps for manufacturing a super-junction semiconductor device according to a second embodiment of the invention. FIG.  2 ( g ) is a perspective view of the super-junction semiconductor device according to the second embodiment of the invention. 
     The super-junction semiconductor device according to the second embodiment includes a first alternating conductivity type layer on a layer with low electrical resistance and a second alternating conductivity type layer on the first alternating conductivity type layer. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer. The regions of the first conductivity type and the regions of the second conductivity type in the second alternating conductivity type layer are extended in perpendicular to the regions of the first conductivity type and the regions of the second conductivity type in the first alternating conductivity type layer. 
     Referring at first to FIG.  2 ( c ), a highly resistive n − -type layer  21 A is deposited epitaxially on an n-type substrate with low electrical resistance. The n − -type layer  21 A is 4 μm in thickness. 
     Referring now to FIG.  2 ( a ), a resist mask  51 A is formed on n − -type layer  21 A by photolithography. Boron ions are implanted into first surface portions of n − -type layer  21 A at the dose amount of 2×10 13  cm −2  of boron atoms  7 . Resist mask  51 A includes first windows, through which boron ions are implanted. The first windows are 2 μm in width and spaced apart for 6 μm from each other. 
     Referring now to FIG.  2 ( b ), resist mask  51 A is removed. Then, a resist mask  51 B having second windows is formed on n − -type layer  21 A by photolithography such that the second windows are at the midpoints between the first windows of resist mask  51 A Phosphorus ions are implanted through the second windows into second surface portions of n − -type layer  2 A at the dose amount of 2×10 13  cm −2  of phosphorus atoms  4 . The second windows are 2 μm in width and spaced apart for 6 μm from each other. 
     Referring now to FIG.  2 ( c ), the steps of the epitaxial growth and the boron ion implantation described above with reference to FIG.  2 ( a ) and the step of phosphorus ion implantation described above with reference to FIG.  2 ( b ) are repeated as many times as necessary. 
     Referring now to FIG.  2 ( f ), resist mask  51 B is removed. A highly resistive n − -type layer  21 B of 6 μm in thickness is deposited epitaxially on the uppermost n − -type layer  2 A. 
     Referring now to FIG.  2 ( d ), a resist mask  5 C having third windows is formed on n − -type layer  21 B by photolithography. Boron ions are implanted through the third windows into first surface portions of n − -type layer  21 B at the dose amount of 1×10 13  cm −2  of boron atoms  7 . Resist mask  51 C is positioned such that the third windows thereof extend in perpendicular to the first windows or the second windows of the preceding resist mask  51 A or  51 B. The third windows in resist mask  51 C are wider than the first windows shown in FIG.  2 ( a ) or the second windows in FIG.  2 ( b ) and spaced apart from each other more widely than the first windows or the second windows. More in detail, third windows in resist mask  51 C are 4 μm in width and spaced apart for 12 μm from each other. 
     Referring now to FIG.  2 ( e ), resist mask  5 C is removed. Then, a resist mask  51 D having fourth windows is formed on if-type layer  21 B by photolithography such that the fourth windows are at the midpoints between the third windows of resist mask  51 C. The fourth windows in resist mask  5 D are 4 μm in width and spaced apart for 12 μm from each other. Phosphorus ions are implanted through the fourth windows into second surface portions of if-type layer  21 B at the dose amount of 1×10 13  cm −2  of phosphorus atoms  4 . Resist mask  51 D is patterned in such a way that the pattern of resist mask  51 D is a displacement of the pattern of resist mask  51 C. The fourth windows in resist mask  51 D are positioned above the centers of the spaces between the third windows in resist mask  51 C. 
     Referring now to FIG.  2 ( f ), resist mask  51 D is removed. A highly resistive n − -type layer  21 B of 8 μm in thickness is deposited epitaxially on n − -type layer  2 B. 
     Referring back to FIG.  1 ( g ), a first alternating conductivity type layer and a second alternating conductivity type layer on the first alternating conductivity type layer are formed by thermally treating the laminate including n − -type layers  21 A and  21 B formed so far at 1150° C. for 20 hours to drive all the implanted impurity atoms. The first alternating conductivity type layer is formed of n-type drift regions  8   a  and p-type partition regions  8   b  arranged alternately with each other. The second alternating conductivity type layer is formed of n-type drift regions  18   a  and p-type partition regions  18   b  arranged alternately with each other. 
     Then, a surface MOSFET structure is formed in the same way as according to the first embodiment through the conventional steps of forming the MOSFET structure. 
     Third Embodiment 
     FIGS.  3 ( a ) through  3 ( f ) are top plan views for explaining the steps for manufacturing a super-junction semiconductor device according to a third embodiment of the invention. FIG.  3 ( g ) is a vertical cross section along A-A′ of FIG.  3 ( f ). 
     The super-junction semiconductor device according to the third embodiment includes a first alternating conductivity type layer on a layer with low electrical resistance and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer includes columnar regions of the second conductivity type and a region of the first conductivity type filling the space between the columnar regions of the second conductivity type. And, the second alternating conductivity type layer includes columnar regions of the second conductivity type and a region of the first conductivity type filling the space between the columnar regions of the second conductivity type. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer. 
     Referring now to FIG.  3 ( a ), a highly resistive n − -type layer is deposited epitaxially on an n-type substrate with low electrical resistance. The n − -type epitaxial layer is 4 μm in thickness. 
     A resist mask  52 A is formed on the n − -type epitaxial layer by photolithography. Boron ions as p-type impurity ions are implanted into first surface portions of the n − -type epitaxial layer at the dose amount of 1.2×10 14  cm −2  of boron atoms  7 . Resist mask  52 A includes first square windows, through which boron ions are implanted. The first square windows are 2 μm×2 μm in area and spaced apart for 2 μm from each other. In other words, the first square windows of 2 μm×2 μm in area are aligned at the pitch of 4 μm. 
     Referring now to FIG.  3 ( b ), resist mask  52 A is removed. Then, resist masks  52 B are formed by photolithography on the portions of the n − -type epitaxial layer, thereon the first square windows of resist mask  52 A were positioned. Phosphorus ions are implanted as n-type impurity ions into a second surface portion of the n − -type epitaxial layer at the dose amount of 4×10 13  cm −2  of phosphorus atoms  4 . 
     Referring now to FIG.  3 ( c ), the steps described above with reference to FIGS.  3 ( a ) and  3 ( b ) are repeated as many times as necessary. 
     Referring now to FIG.  3 ( d ), resist masks  52 B are removed. A highly resistive n − -type layer of 6 μm in thickness is deposited epitaxially on the uppermost n − -type epitaxial layer. Then, a resist mask  52 C having second square windows is formed on the uppermost n − -type epitaxial layer by photolithography. Boron ions are implanted through the second square windows into first surface portions of the uppermost n − -type layer at the dose amount of 3×10 13  cm −2  of boron atoms  7 . The second windows in resist mask  52 C are 4 μm×4 μm in area and aligned at the pitch of 8 μm. Resist mask  52 C is positioned such that the resulting columnar p-type regions in the second alternating conductivity type layer are connected to the resulting columnar p-type regions in the first alternating conductivity type layer. 
     Referring now to FIG.  3 ( e ), resist mask  52 C is removed. Then, resist masks  52 D are formed by photolithography on the portions of the uppermost n − -type epitaxial layer, thereon the second square windows of resist mask  52 C were positioned. Phosphorus ions are implanted into a second surface portion of the uppermost n − -type layer at the dose amount of 1×10 13  cm −2  of phosphorus atoms  4 . 
     Referring now to FIG.  3 ( f ), resist masks  52 D are removed. A highly resistive n − -type layer of 8 μm in thickness is deposited epitaxially on the uppermost n − -type epitaxial layer. 
     Referring now to FIG.  3 ( g ), a first alternating conductivity type layer and a second alternating conductivity type layer on the first alternating conductivity type layer are formed by thermally treating the laminate including the n − -type epitaxial layers formed so far at 1150° C. for 20 hours to drive all the implanted impurity atoms. The first alternating conductivity type layer is formed of an n-type drift region  8   a  and p-type partition regions  8   b  spaced apart from each other by n-type drift region  8   a.  The second alternating conductivity type layer is formed of an n-type drift region  18   a  and p-type partition regions  18   b  spaced apart from each other by n-type drift region  18   a.  As exemplary shown in FIGS.  3 ( f ) and  3 ( g ), the four corners of the square lower end face of p-type partition region  18   b  are located at the centers of the square upper end faces of the nearest four p-type partition regions  8   b.  in short, four p-type partition regions  8   b  are connected to p-type partition region  18   b.    
     Then, a surface MOSFET structure is formed in the same way as according to the first embodiment through the conventional steps of forming the MOSFET structure. 
     Fourth Embodiment 
     FIGS.  4 ( a ) through  4 ( f ) are top plan views for explaining the steps for manufacturing a super-junction semiconductor device according to a fourth embodiment of the invention. FIG.  4 ( g ) is a vertical cross section along B-B′ of FIG.  4 ( f ). 
     The super-junction semiconductor device according to the fourth embodiment includes a first alternating conductivity type layer on a layer with low electrical resistance and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer includes columnar regions of the second conductivity type and a region of the first conductivity type filling the space between the columnar regions of the second conductivity type. And, the second alternating conductivity type layer includes regions of the first conductivity type and regions of the second conductivity type extending in parallel to each other and alternately arranged with each other. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer. 
     Referring now to FIG.  4 ( a ), a highly resistive n − -type layer is deposited epitaxially on an n-type substrate with low electrical resistance. The n − -type epitaxial layer is 4 μm in thickness. 
     A resist mask  53 A is formed on the n − -type epitaxial layer by photolithography. Boron ions as p-type impurity ions are implanted into first surface portions of the n − -type epitaxial layer at the dose amount of 1.2×10 14  cm −2  of boron atoms  7 . Resist mask  53 A includes square windows, through which boron ions are implanted. The square windows are 4 μm×4 μm in area and spaced apart for 4 μm from each other. In other words, the square windows of 4 μm×4 μm in area are aligned at the pitch of 8 μm. 
     Referring now to FIG.  4 ( b ), resist mask  53 A is removed. Then, resist masks  53 B are formed by photolithography on the portions of the n − -type epitaxial layer, thereon the square windows of resist mask  53 A were positioned. Phosphorus ions are implanted as n-type impurity ions into second surface portions of the n − -type epitaxial layer at the dose amount of 4×10 13  cm −2  of phosphorus atoms  4 . 
     Referring now to FIG.  4 ( c ), the steps described above with reference to FIGS.  4 ( a ) and  4 ( b ) are repeated as many times as necessary. 
     Referring now to FIG.  4 ( d ), resist masks  53 B are removed. A highly resistive n − -type layer of 6 μm in thickness is deposited epitaxially on the uppermost n − -type epitaxial layer. Then, resist masks  53 C are formed on the uppermost n − -type epitaxial layer by photolithography. Boron ions are implanted through resist masks  53 C into first surface portions of the uppermost n − -type epitaxial layer at the dose amount of 2×10 13  cm −2  of boron atoms  7 . Resist masks  53 C are stripes 8 μm in width, extending in parallel to each other and spaced apart for 8 μm. As described later, resist masks  53 C are positioned such that the stripe-shaped p-type regions in the second alternating conductivity type layer are connected to the columnar p-type regions in the first alternating conductivity type layer. 
     Referring now to FIG.  4 ( e ), resist masks  53 C are removed. Then, resist masks  53 D are formed by photolithography on the first portions of the uppermost n − -type epitaxial layer, therein the boron ions were implanted. Phosphorus ions are implanted through resist masks  53 D into second surface portions of the uppermost n − -type layer at the dose amount of 2×10 13  cm −2  of phosphorus atoms  4 . Resist masks  53 D are stripes 8 μm in width, extending in parallel to each other and spaced apart for 8 μm. Resist masks  53 D are positioned such that the resulting stripe-shaped n-type regions in the second alternating conductivity type layer are connected to the resulting n-type region in the first alternating conductivity type layer. 
     Referring now to FIG.  4 ( f ), resist masks  53 D are removed. A highly resistive n − -type layer of 8 μm in thickness is deposited epitaxially on the uppermost n − -type epitaxial layer. 
     Referring now to FIG.  4 ( g ), a first alternating conductivity type layer and a second alternating conductivity type layer on the first alternating conductivity type layer are formed by thermally treating the laminate including the n − -type layers so far at 1150° C. for 20 hours to drive all the implanted impurity atoms. The first alternating conductivity type layer is formed of an n-type drift region  8   a  and p-type partition regions  8   b  spaced apart from each other by n-type drift region  8   a.  The second alternating conductivity type layer is formed of n-type drift regions  18   a  and p-type partition regions  18   b  extending in parallel to each other and arranged alternately with each other. As exemplary shown in FIGS.  4 ( f ) and  4 ( g ), p-type partition region  18   b  is connected to two arrays of p-type partition regions  8   b.    
     Then, a surface MOSFET structure is formed in the same way as according to the first embodiment through the conventional steps of forming the MOSFET structure. 
     Fifth Embodiment 
     FIGS.  5 ( a ) through  5 ( f ) are cross sectional views for explaining the steps for manufacturing a super-junction semiconductor device according to a fifth embodiment of the invention. FIG. 6 is a cross sectional view of the super-junction semiconductor device according to the fifth embodiment of the invention. The super-junction semiconductor device according to the fifth embodiment includes a first alternating conductivity type layer and a second alternating conductivity type layer between a layer with low electrical resistance and a first major surface of a semiconductor chip. As shown in FIG. 6, the spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer. In FIG. 6, the regions of a first conductivity type and the regions of a second conductivity type in the first alternating conductivity type layer are extended in parallel to the regions of the first conductivity type and the regions of the second conductivity type in the second alternating conductivity type layer. Alternatively, the regions of the first conductivity type and the regions of the second conductivity type in the first alternating conductivity type layer may be extended in perpendicular to the regions of the first conductivity type and the regions of the second conductivity type in the second alternating conductivity type layer. 
     Now the steps for manufacturing the super-junction semiconductor device according to the fifth embodiment will be explained with reference to FIGS.  5 ( a ) through  5 ( f ). 
     Referring at first to FIG.  5 ( a ), a highly resistive n − -type layer  2 A is deposited epitaxially on an n-type substrate  1  with low electrical resistance. The n − -type layer  2 A is 4 μm in thickness. 
     A resist mask  54 A is formed on the n − -type epitaxial layer. First windows are opened in a predetermined portion of resist mask  54 A by photolithography. Boron ions  6  as p-type impurity ions are implanted through the first windows into first surface portions of n − -type layer  2 A at the dose amount of 2×10 13  cm −2  of boron atoms  7 . The first windows are 2 μm in width and spaced apart for 6 μm from each other. In other words, the first windows are arranged at the pitch of 8 μm. 
     Referring now to FIG.  5 ( b ), resist mask  54 A is removed. Then, a resist mask  54 B is formed by photolithography on n − -type layer  2 A. Second windows are opened in a predetermined portion of resist mask  54 B above a second surface portion of n − -type layer  2 A. Boron ions  6  as p-type impurity ions are implanted through the second windows into the second surface portion of n − -type layer  2 A at the dose amount of 1×10 13  cm −2  of phosphorus atoms  4 . The second windows are 4 μm in width and spaced apart for 12 μm from each other. In other words, the second windows are arranged at the pitch of 16 μm. 
     Referring now to FIG.  5 ( c ), resist mask  54 B is removed. Then, a resist mask  54 C is formed by photolithography on n − -type epitaxial layer  2 A. Third windows are opened by photolithography in the portion of resist mask  54 C above the first surface portion of n − -type layer  2 A. The third windows are positioned at the midpoints between the locations of the first windows of resist mask  54 A. Phosphorus ions  3  are implanted as n-type impurity ions into the first surface portions of n − -type layer  2 A at the dose amount of 2×10 13  cm −2  of phosphorus atoms  4 . The third windows are 2 μm in width and arranged at the pitch of 8 μm 
     Referring now to FIG.  5 ( d ), resist mask  54 C is removed. Then, a resist mask  54 D is formed by photolithography on n − -type layer  2 A. Fourth windows are opened by photolithography in the portion of resist mask  54 D above the second surface portion of n − -type layer  2 A. The fourth windows are positioned at the midpoints between the locations of the second windows of resist mask  54 B. Phosphorus ions  3  are implanted through the fourth windows into the second surface portions of n − -type layer  2 A at the dose amount of 1×10 13  cm −2  of phosphorus atoms  4 . The third windows are 4 μm in width and arranged at the pitch of 16 μm. 
     Referring now to FIG.  5 ( e ), the steps of epitaxial growth, boron ion implantation and phosphorus ion implantation described above with reference to FIGS.  5 ( a ) through  5 ( d ) are repeated as many times as necessary. 
     Referring now to FIG.  5 ( f ), resist mask  54 D is removed. A highly resistive n − -type layer  21 A of 4 μm in thickness is deposited epitaxially on the uppermost n − -type layer  2 A. 
     A first alternating conductivity type layer and a second alternating conductivity type layer on the first alternating conductivity type layer are formed by thermally treating the laminate including n − -type layers  21 A formed so far at 1150° C. for 20 hours to drive all the implanted impurity atoms. The first alternating conductivity type layer is formed of n-type drift regions  8   a  and p-type partition regions  8   b  arranged alternately with each other. The second alternating conductivity type layer is formed of n-type drift regions  18   a  and p-type partition regions  18   b  arranged alternately with each other. The pn-junctions between n-type drift regions  18   a  and p-type partition regions  18   b  are spaced apart more widely from each other than the pn-junctions between n-type drift regions  8   a  and p-type partition regions  8   b.    
     Finally, a surface MOSFET structure is formed in the same way as according to the first embodiment through the conventional steps of forming the MOSFET structure. 
     Although the invention has been explained in connection with n-channel super-junction MOSFET&#39;s and the manufacturing methods thereof, it is obvious to those skilled in the art that the invention is applicable also to the p-channel super-junction MOSFET&#39;s by interchanging the conductivity types of the constituent layers and regions according to the foregoing embodiments. Although the invention has been explained in connection with the super-junction MOSFET&#39;s including one second alternating conductivity layer, the super-junction semiconductor devices may include a plurality of second alternating conductivity layer formed of regions of the first conductivity type and regions of the second conductivity type. The spacing between the pn-junctions in the second alternating conductivity layer is wider than the spacing between the pn-junctions in the first alternating conductivity layer. Boron ions and phosphorous ions are implanted at the respective dose amounts, which facilitate depleting n-type drift regions  8   a  and  18   a  and p-type partition regions  8   b  and  18   b.    
     The super-junction semiconductor device according to the invention, that widens the spacing between the pn-junctions in the alternating conductivity type layer on the side of the first major surface of the semiconductor chip, facilitates narrowing the spacing between the pn-junctions in the alternating conductivity type layer inside the semiconductor chip without increasing the manufacturing costs. Therefore, the super-junction semiconductor device according to the invention facilitates reducing the on-resistance while keeping a high breakdown voltage. The manufacturing method according to the invention facilitates manufacturing super-junction semiconductor devices with low costs and with excellent mass-productivity. 
     The invention has been described with reference to certain preferred embodiments thereof. It will be understood, however, that the invention is not limited to the specifically described embodiments and modifications and variations thereof are possible within the scope of the appended claims.