Abstract:
In a matrix multiplication in which each element of the resultant matrix is the dot product of a row of a first matrix and a column of a second matrix, each row and column can be broken into manageable blocks, with each block loaded in turn to compute a smaller dot product, and then the results can be added together to obtain the desired row-column dot product. The earliest results for each dot product are saved for a number of clock cycles equal to the number of portions into which each row or column is divided. The results are then added to provide an element of the resultant matrix. To avoid repeated loading and unloading of the same data, all multiplications involving a particular row-block can be performed upon loading that row-block, with the results cached until other multiplications for the resultant elements that use the cached results are complete.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This claims the benefit of commonly-assigned U.S. Provisional Patent Application No. 61/080,499, filed Jul. 14, 2008, which is hereby incorporated by reference herein in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to the use of programmable integrated circuit devices (e.g., field-programmable gate arrays or other programmable logic devices (PLDs)) to perform matrix multiplication operations. 
     In a multiplication of two input matrices AA and BB to form resultant matrix CC, each resultant element c ij  in the resultant matrix CC will be the dot product of the ith row in matrix AA and the jth column in matrix BB. For example, c 57  will be the dot product of the fifth row of matrix AA and the seventh column of matrix BB. The length of a row of (i.e., the number of columns, k, in) matrix AA is equal to the height of a column of (i.e., the number of rows in) matrix BB. As is evident, the computation of each element c ij  requires k multiplications. Moreover, there are i×j elements c ij  in matrix CC, for a total of i×j×k multiplications. For large matrices (with, e.g., hundreds of elements per dimension), there may not be enough multipliers and logic resources available on a programmable integrated circuit device, such as an FPGA, to perform even the k multiplications to multiply just one row and column together for a single resultant element c ij . k−1 adders also are required to add the individual products to obtain the dot product. 
     SUMMARY OF THE INVENTION 
     This disclosure describes a method and a structure whereby multiple small dot products can be effectively combined to generate a larger dot product, for each element of a matrix multiplication. A programmable integrated circuit device may be configured as such a structure, to carry out the method. 
     Specifically, to deal with the need for a greater number of multipliers than are available just to perform one row-column dot product for one resultant element c ij , each row and each column can be broken into manageable blocks, with each block loaded in turn to compute a smaller dot product, and then the results can be added together to obtain the desired row-column dot product. The earliest results for each dot product are saved for a number of clock cycles equal to the number of portions N into which each row or column is divided. This can be done with an N-element shift register. The contents of the elements are then added, using N−1 adders, to provide an element c ij  of the resultant matrix. No accumulation is required. 
     However, as described in more detail below, this results in repeated loading and unloading of the same blocks at different times as different elements are computed. Moreover, one must have sufficient bandwidth to load all of the values, and memory bandwidth decreases with increasing memory size (because the ratio of edge to area decreases), so that the delays in multiple loadings and unloadings of the same blocks is magnified by the bandwidth bottleneck, increasing the number of clock cycles required to compute a single c ij  calculation. 
     Accordingly, pursuant to another aspect of the invention, instead of performing all parts of one c ij  calculation in order and then moving on to the next c ij  calculation, each block or portion of a row is loaded and all calculations that use that block or portion with a block or portion of any column—for any of the c ij —are carried out. As a result, no c ij  computation can be completed until the partial calculations using the last block or portion of the row in question begin. Therefore, the partial calculations are stored in a set of cache memories. 
     In one embodiment, the number of caches is equal to the number N of portions into which each row or column is divided. Each nth cache stores the respective dot products of an nth row-block of matrix AA with the respective nth column-blocks of the columns of matrix BB. Therefore, each c ij  is spread across corresponding locations in the N caches—i.e., c ij  is spread across the N jth locations of the N caches. However, once the Nth cache begins to fill, each c ij  can be burst out as soon as the corresponding location in the Nth cache is computed. Thus, once results start to become available, a new result is burst out on each clock cycle. Specifically, each c ij  for the ith row will be available on (N(N−1)+j)th clock cycle of computations for that row. 
     By using one loading of a partial row of matrix AA to compute all products of that partial row and any partial column of matrix BB with which it must be multiplied, this approach increases the effective bandwidth of the memory used to store matrix AA, and reduces power consumption by reducing memory access. 
     Therefore, in accordance with the present invention, there is provided a method of configuring a programmable integrated circuit device to perform multiplication of a first multiplicand matrix by a second multiplicand matrix to form a resultant matrix, where the first multiplicand matrix has a first number of rows and a second number of columns, the second multiplicand matrix has that second number of rows and a third number of columns, and the resultant matrix has a number of elements equal to a product of the first and third numbers. The method includes configuring logic of the programmable integrated circuit device as a fourth number of multipliers, where the fourth number is one-Nth of the second number. Logic of the programmable integrated circuit device is configured to break down each row of the first multiplicand matrix into N row-blocks and to break down each column of the second multiplicand matrix into N column-blocks, and to use the fourth number of multipliers to form a respective dot-product of each of the row-blocks with a respective one of the column-blocks to form N partial dot products of each respective row of the first multiplicand matrix and a corresponding column of the second multiplicand matrix. Logic of the programmable integrated circuit device is configured to save each of the N partial dot products until all of the N partial dot products have been computed. Logic of the programmable integrated circuit device is configured to add the N partial dot products to provide an element of the resultant matrix corresponding to the respective row of the first multiplicand matrix and the corresponding column of the second multiplicand matrix. 
     A programmable logic device so configured, and a machine-readable data storage medium encoded with software for performing the method, are also provided. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Further features of the invention, its nature and various advantages will be apparent upon consideration of the following detailed description, taken in conjunction with the following drawings, in which like reference characters refer to like parts throughout, and in which: 
         FIG. 1  is a logical representation of two matrices to be multiplied; 
         FIG. 2  shows a first embodiment of a structure for matrix multiplication in accordance with the present invention; 
         FIG. 3  shows a second embodiment of a structure for matrix multiplication in accordance with the present invention; 
         FIG. 4  shows an example of a cache addressing scheme in accordance with the invention; 
         FIG. 5  shows an example of an output element calculation in accordance with the invention; 
         FIG. 6  shows the physical storage of one of the input matrices in accordance with the invention, to illustrate an example of a read pattern when using the invention; 
         FIG. 7  is a cross-sectional view of a magnetic data storage medium encoded with a set of machine-executable instructions for performing the method according to the present invention; 
         FIG. 8  is a cross-sectional view of an optically readable data storage medium encoded with a set of machine executable instructions for performing the method according to the present invention; and 
         FIG. 9  is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A matrix multiplier according to the present invention for use in programmable integrated circuit devices (such as, e.g., FPGAs) uses dot product calculation circuitry which may be built from programmable logic of the programmable integrated circuit device, and can process arbitrarily-sized matrices by using blocking within a row or column—i.e., by dividing each row or column into row-blocks or column-blocks. The dot product calculation circuitry may be constructed using a monolithic block of multipliers and adders. For example, such circuitry can be efficiently designed with a floating point compiler such as that described in copending, commonly-assigned U.S. patent application Ser. No. 11/625,655, filed Jan. 22, 2007, which is hereby incorporated by reference herein in its entirety. 
     For the purposes of illustration one can consider dot product calculation circuitry that has 32 elements, and therefore can process 32 inputs from a matrix AA row and 32 inputs from a matrix BB column. Such circuitry would include 32 multipliers, and a tree of 31 adders to sum all of the multipliers. One can further assume a matrix AA that is 10 rows by 96 columns (10×96), and a matrix BB that is 96 rows by 15 columns (96×15). Three separate 32-element dot products are required to calculate the 96-element dot product for each element in the resultant 10×15 matrix. The three smaller dot products, which are scalar numbers, are simply summed to generate the larger dot product. 
     Two examples will be shown. In a first, generic, example, both input matrices are stored in memory banks with symmetric bandwidth. In a second example, the two matrices are stored in memory banks with asymmetric bandwidth, such as devices sold by Altera Corporation, of San Jose, Calif., which have TriMatrix™ memory including memories of three different sizes located throughout the device for user applications. 
       FIG. 1  shows the logical storage of matrix AA on the left ( 101 ), and matrix BB on the right ( 102 ), where the dot product is ⅓ the size of the matrix dimension, as in the 96/32 example above, so that each row of matrix AA and each column of matrix BB is divided into three portions (row-blocks or column-blocks). A straightforward matrix multiplication implementation would calculate each resultant element before moving on to the next. For example, the first three resultant elements (top row of the resultant matrix) would be &lt;A1, E1&gt;+&lt;A2, E2&gt;+&lt;A3, E3&gt;, &lt;A1, F1&gt;+&lt;A2, F2&gt;+&lt;A3, F3&gt;, and &lt;A1, G1&gt;+&lt;A2, G2&gt;+&lt;A3, G3&gt;. Assuming the physical memories were arranged so that all 32 elements of A1, A2, etc. could be read in a single clock cycle (i.e., with each column of matrix AA and each row of matrix BB in respective individual memories), then the sequence of reads would be as shown below in Table 1 (first seven reads shown). 
     
       
         
               
             
               
               
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 AA and BB Read Sequences 
               
             
          
           
               
                 Time Slot 
                 Matrix AA 
                 Matrix BB 
               
               
                   
               
             
          
           
               
                 0 
                 A1 
                 E1 
               
               
                 1 
                 A2 
                 E2 
               
               
                 2 
                 A3 
                 E3 
               
               
                 3 
                 A1 
                 F1 
               
               
                 4 
                 A2 
                 F2 
               
               
                 5 
                 A3 
                 F3 
               
               
                 6 
                 A1 
                 G1 
               
               
                   
               
             
          
         
       
     
     Three clock cycles would be required to perform three dot product operations to generate one resultant element. The dot product datapath would have to be deeply pipelined because of its complexity, and may have a long latency, but once the first result arrived, the three dot product results would arrive on consecutive clock cycles. The earlier dot product results would have to be delayed, so that all three results could be added together when available. Accordingly, one resultant element would be generated every three clock cycles. 
     The architecture for this approach is shown in  FIG. 2 . Each row-block or column-block of each matrix AA or BB may be stored in a separate, relatively small memory block  201 , such as one of the M9K RAM blocks provided in STRATIX® FPGAs from Altera Corporation. There may be as many separate blocks  201  for each dimension as there are elements in the dot product calculation circuitry  202 , referred to in  FIG. 2  as the HPC (high-performance computing) Dot Product. In other words, where the first row of a 96-column matrix AA includes columns 1-32 in row-block A1, columns 33-64 in row-block A2, and columns 65-96 in row-block A3, the three row-blocks are stored across 32 separate memory blocks  201 . As among the three row-blocks of each row, corresponding values have the same column index (0:31), but a different sub-row index (0:2). Row-blocks B1, B2, B3 and the sub-rows of all subsequent rows are stored in the same way. 
     The column-blocks E1, E2, and E3 may be stored in a similar way in another bank of similar memory blocks  201 . The subsequent column-blocks F1, F2, F3, and G1, G2, G3, etc. are stored with the row indices (0:2) and column indices (0:31). 
     The products of the row-blocks and the column-blocks may be stored in N shift registers  203 . After N clock cycles, all shift registers  203  are filled and their contents can be added by HPC adder block  204 , which is equivalent to N−1 adders. Thus, one result is output every N cycles. No accumulation is required. To support dynamic matrix sizes, there may be a large number of shift registers  203  of which only N are used, while the remainder are ignored. To that end, after each result is obtained, the contents of shift registers  203  may be zeroed by resetting or by clocking in a string of zeroes. 
     In the embodiment  200  of  FIG. 2 , two vectors are loaded in every clock cycle, which may consume a lot of power. In addition, there must be as much memory bandwidth available as the vector width. Some FPGAs (such as the STRATIX® family from Altera Corporation) have differing sizes of memory blocks. Larger memories are more area efficient, but have less bandwidth. Such devices can be used to support larger matrix sizes in the larger memories, but a different type of architecture  300  may be provided, as shown in  FIG. 3 . 
     Here, matrix BB may be stored as before, in smaller memories  201  such as the M9K memories described above. However, matrix AA may be stored in larger memory blocks  301 , such as M144K memories available in certain STRATIX® FPGAs from Altera Corporation. As a result, the bandwidth of the matrix AA storage may be less than that of the vector multiplier. Therefore, multiple loads from the matrix AA storage may be needed, and are stored in local registers  303 . 
     As before, each row-block of matrix AA (A1, A2, A3, B1, etc.) is multiplied multiple times by successive column-blocks of matrix BB. Each matrix AA row-block may be loaded once per group of matrix BB column-blocks. Each matrix AA row-block may be read over multiple clock cycles into the local registers  303 , while each of the matrix BB column-blocks (E1, F1, G1, E2, etc.) may be loaded in a single clock cycle. The matrix BB bandwidth may be the same as that of the dot product calculating circuitry  202 , so processing can be done at a rate of one row-block/one column-block per clock cycle. A conceptual representation of these memory accesses are shown in Table 2. 
     
       
         
               
             
               
               
               
             
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 AA and BB Read Sequences - Conceptual 
               
             
          
           
               
                 Time Slot 
                 Matrix AA 
                 Matrix BB 
               
               
                   
               
             
          
           
               
                 0 
                 A1 
                 E1 
               
               
                 1 
                   
                 F1 
               
               
                 2 
                   
                 G1 
               
               
                 3 
                 A2 
                 E2 
               
               
                 4 
                   
                 F2 
               
               
                 5 
                   
                 G2 
               
               
                 6 
                 A3 
                 E3 
               
               
                 7 
                   
                 F3 
               
               
                 8 
                   
                 G3 
               
               
                   
               
             
          
         
       
     
     Multiple reads are required for each vector from matrix AA. For example, assuming that four reads are required for each matrix AA row-block—i.e., there are eight larger memories, and four reads are required to fetch a new 32-element vector—the actual sequence (of the conceptual sequence shown in Table 2) is shown in Table 3. 
     
       
         
               
             
               
               
               
             
               
               
               
             
           
               
                 TABLE 3 
               
             
             
               
                   
               
               
                 AA and BB Read Sequences - Actual 
               
             
          
           
               
                 Time Slot 
                 Matrix AA 
                 Matrix BB 
               
               
                   
               
             
          
           
               
                 0 
                 A1-1 
                   
               
               
                 1 
                 A1-2 
                   
               
               
                 2 
                 A1-3 
                   
               
               
                 3 
                 A1-4 
                 E1 
               
               
                 4 
                   
                 F1 
               
               
                 5 
                   
                 G1 
               
               
                 6 
                 A2-1 
                   
               
               
                 7 
                 A2-2 
                   
               
               
                 8 
                 A2-3 
                   
               
               
                 9 
                 A2-4 
                 E2 
               
               
                 10 
                   
                 F2 
               
               
                 11 
                   
                 G2 
               
               
                 12 
                 A3-1 
                   
               
               
                 13 
                 A3-2 
                   
               
               
                 14 
                 A3-3 
                   
               
               
                 15 
                 A3-4 
                 E3 
               
               
                 16 
                   
                 F3 
               
               
                 17 
                   
                 G3 
               
               
                   
               
             
          
         
       
     
     The difference in bandwidth causes a processing stall at the beginning of each row-block, and in this example with three matrix BB columns, the penalty is severe on a relative basis, but in a more realistic case of matrix dimensions with hundreds of elements, the penalty would be very small on a relative basis. 
     Because the portions of the result are computed out of order, the dot product results for each row-block/column-block pair may be stored in a cache  401  as described below. Once an entire row of sub-columns of matrix BB (in the example E1, F1 and G1, or E2, F2 and G2, or E3, F3 and G3) has been processed, the matrix AA row index and matrix BB column index are increased by the number of elements in the vector, a new matrix AA row-block is loaded, and a new set of matrix BB sub-column processing is started. The results are again stored in a cache  401 , in the next memory location. 
     The cache addressing scheme is shown in  FIG. 4 , which shows three cache memories (out of a potentially larger number), which are written to sequentially, but read in parallel. From  FIG. 1 , the first element in the resultant matrix is the sum of the dot products A1×E1, A2×E2, and A3×E3. The sequence of vector operations is A1×E1, A1×F1, A1×G1, A2×E2, and so on, which are stored in Cache 0/Address 0, Cache 0/Address 1, Cache 0/Address 2, Cache 1/Address 0, etc., respectively. 
     By the end of the computation of the ith row of resultant matrix CC, all of the row-blocks of the ith row of matrix AA will have been used for the last time, freeing up the cache memories for the (i+1)th row. Accordingly, the number of iterations per element—i.e., the number N of row-blocks per row of matrix AA, which is the same as the number of column-blocks per column of matrix BB (in this example, three) determines the number of cache memories  401  used. 
     A generic cache structure may be provided to support dynamic matrix sizes, in which case a larger number of memories  401  is provided in the cache. In such a case, the outputs of any unused cache memories  401  are zeroed. The depth of each cache memory  401  may be the same as number of columns in matrix AA (which is the number of rows in matrix BB). Cache memories  401  need not be double-buffered, because reading of the start of the memory may begin before writing of the partial vector products of the current matrix is complete. 
     Once a corresponding location has been written to in all of the cache memories that are being used, reading of all memories starts in parallel, beginning with location 0. In other words, taking a three-cache example, cache 0 will fill up first, followed by cache 1. After that, as soon as a location has been filled in cache 2, it may be read. Thus, as soon as cache 2/location 0 has been written, cache 0/location 0, cache 1/location 0, and cache 2/location 0 may be read, even though subsequent locations in cache2 are still being written. The outputs of the corresponding locations in each memory (e.g., cache 0/location 0, cache 1/location 0, and cache 2/location 0) are then summed, bursting out the result of computations involving an entire row of matrix AA (and column of matrix BB) as result as c ij , with no accumulation required. The output burst for each element of matrix CC (i.e., for each c ij ) will follow the last cache memory write for a component of that element by the latency of summing block  304 , but once started, a burst of a new c ij  will occur on each of j consecutive clock cycles until the ith row of matrix CC is complete. The process will then begin again for the (i+1)th row, with another (N(N−1)+1) clock cycles passing until the (i+1)th row begins to burst out. 
       FIG. 5  shows the output element calculation, and comparison with  FIG. 4  shows how each output calculation correlates to the cache storage locations. 
       FIG. 6  shows the physical storage of matrix BB. There are as many memory blocks as the number of elements in the dot product, which are all read in parallel. In this example, matrix BB is written to the storage column-by-column (E1, E2, E3, F1, F2, . . . ). However, the column-blocks are read row-by-row in order E1, F1, G1—in this case column-block 0/Address 0, column-block 0/Address 3, column-block 0/Address 6, column-block 1/Address 0, and so on, so the dot-product-width parallel access in this example uses an address sequence of 0, 3, 6, 1, 4, 7, 2, 5, 8. 
     In accordance with this invention, the time required for calculation of a matrix multiplication is reduced, both by avoiding multiple reads of the matrix AA row-blocks, and by bursting of the result cache element-by-element as a row of matrix CC is completed. This provides scalable and consistently high performance (e.g., greater than 100 billion floating-point operations per second—i.e., &gt;100 GFLOPs). 
     Instructions for carrying out the method according to this invention may be encoded on a machine-readable medium, to be executed by a suitable computer or similar device to implement the method of the invention for programming or configuring PLDs to perform arithmetic operations in accordance with the format describe above. For example, a personal computer may be equipped with an interface to which a PLD can be connected, and the personal computer can be used by a user to program the PLD using a suitable software tool, such as the QUARTUS® II software available from Altera Corporation, of San Jose, Calif. 
       FIG. 7  presents a cross section of a magnetic data storage medium  600  which can be encoded with a machine executable program that can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium  600  can be a floppy diskette or hard disk, or magnetic tape, having a suitable substrate  601 , which may be conventional, and a suitable coating  602 , which may be conventional, on one or both sides, containing magnetic domains (not visible) whose polarity or orientation can be altered magnetically. Except in the case where it is magnetic tape, medium  600  may also have an opening (not shown) for receiving the spindle of a disk drive or other data storage device. 
     The magnetic domains of coating  602  of medium  600  are polarized or oriented so as to encode, in manner which may be conventional, a machine-executable program, for execution by a programming system such as a personal computer or other computer or similar system, having a socket or peripheral attachment into which the PLD to be programmed may be inserted, to configure appropriate portions of the PLD, including its specialized processing blocks, if any, in accordance with the invention. 
       FIG. 8  shows a cross section of an optically-readable data storage medium  700  which also can be encoded with such a machine-executable program, which can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium  700  can be a conventional compact disk read only memory (CD-ROM) or digital video disk read only memory (DVD-ROM) or a rewriteable medium such as a CD-R, CD-RW, DVD-R, DVD-RW, DVD+R, DVD+RW, or DVD-RAM or a magneto-optical disk which is optically readable and magneto-optically rewriteable. Medium  700  preferably has a suitable substrate  701 , which may be conventional, and a suitable coating  702 , which may be conventional, usually on one or both sides of substrate  701 . 
     In the case of a CD-based or DVD-based medium, as is well known, coating  702  is reflective and is impressed with a plurality of pits  703 , arranged on one or more layers, to encode the machine-executable program. The arrangement of pits is read by reflecting laser light off the surface of coating  702 . A protective coating  704 , which preferably is substantially transparent, is provided on top of coating  702 . 
     In the case of magneto-optical disk, as is well known, coating  702  has no pits  703 , but has a plurality of magnetic domains whose polarity or orientation can be changed magnetically when heated above a certain temperature, as by a laser (not shown). The orientation of the domains can be read by measuring the polarization of laser light reflected from coating  702 . The arrangement of the domains encodes the program as described above. 
     Thus it is seen that a method for carrying out matrix multiplication, a programmable integrated circuit device programmed to perform the method, and software for carrying out the programming, have been provided. 
     A PLD  90  configured according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system  900  shown in  FIG. 9 . Data processing system  900  may include one or more of the following components: a processor  901 ; memory  902 ; I/O circuitry  903 ; and peripheral devices  904 . These components are coupled together by a system bus  905  and are populated on a circuit board  906  which is contained in an end-user system  907 . 
     System  900  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD  90  can be used to perform a variety of different logic functions. For example, PLD  90  can be configured as a processor or controller that works in cooperation with processor  281 . PLD  90  may also be used as an arbiter for arbitrating access to a shared resources in system  900 . In yet another example, PLD  90  can be configured as an interface between processor  281  and one of the other components in system  900 . It should be noted that system  900  is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. 
     Various technologies can be used to implement PLDs  90  as described above and incorporating this invention. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.