Abstract:
A driving circuit for a multi-phase switched reluctance (SR) machine, wherein a reduced number of wire connections between the machine and driving circuit are needed. In addition, one embodiment of the driving circuit requires the use of fewer individual diodes for the circuit design. The reduction in the number of wire connections and diodes provides greater reliability, improved efficiency, and lower production costs.

Description:
FIELD OF INVENTION 
     The present invention generally relates to a driving circuit, and more particularly to a driving circuit for multi-phase SR machines. 
     BACKGROUND OF THE INVENTION 
     There are numerous driving circuits known in the prior art for energizing switched reluctance (SR) machines, such as those shown in FIGS. 1A and 1B. One commonly used circuit is comprised of an independent &#34;half-bridge&#34; for each phase. FIG. 2 illustrates such a circuit 100 for a two-phase machine. Circuit 100 uses two switches SA1 and SA2 and two freewheeling diodes DA1 and DA2 for phase winding A. Likewise, this circuit uses two switches SB1 and SB2 and two freewheeling diodes DB1 and DB2 for phase winding B. Phase windings A and B are respectively connected to the circuit at connections CA1, CA2 and CB1, CB2. Accordingly, 2N wire connections are needed to connect a typical drive circuit to an SR machine having N phases. 
     Another well known SR machine driving circuit, known as the &#34;Oulton&#34; (TM) driving circuit 102, is shown in FIG. 3, as configured for two phases. While driving circuit 102 requires only three connections (CN1, CN2 and CN3) for connection to an SR machine having 2 phases, Oulton driving circuit 102 requires the use of two capacitors (CB1 and CB2). The DC link voltage is split with the capacitors. 
     Other prior art SR machine driving circuits are described in &#34;Switched Reluctance Motors and Their Control&#34; (1993) by T. J. E. Miller, as well U.S. Pat. Nos. 5,075,610; 5,084,662 and 5,115,181. 
     For driving circuits requiring 2N connections (where N is the number of phases) there are several disadvantages. Where the driving circuit is located remote from the machine, a large number of wire connections can be costly, and result in reliability and efficiency problems. In cases where long wire leads are needed to connect the SR machine with the drive circuit (e.g., where the SR machine is to be located in a deep well) a substantial cost is incurred for the wires. Reliability is also a potential problem, since the more wire leads needed, the greater the chance for disconnection of a wire at the machine or drive circuit. Moreover, there are more opportunities for a wire to be severed along the length thereof. With regard to efficiency, potential energy loss may increase with the number of wires. 
     In the case of the prior art SR machine driving circuits requiring fewer than 2N connections, other drawbacks are encountered. In this regard, these driving circuits may require additional circuit elements (e.g., capacitors or inductors), require a split supply, prohibit phase overlap, or lack all three modes of operation (i.e., positive voltage loop, zero voltage loop and negative voltage loop). 
     In view of the foregoing, there is a need for a driving circuit which reduces the number of connections needed per phase, but does not have the drawbacks associated with prior art driving circuit designs. 
     SUMMARY OF THE INVENTION 
     According to the present invention there is provided a driving circuit for multi-phase switched reluctance machines. 
     An advantage of the present invention is the provision of an SR machine driving circuit which reduces the number of wires needed to connect a multi-phase SR machine to the driving circuit. 
     Another advantage of the present invention is the provision of an SR machine driving circuit which reduces the number of individual freewheeling diodes. 
     Still another advantage of the present invention is the provision of an SR machine driving circuit which reduces the losses associated with the current exiting the machine and being re-routed back from the driving circuit. 
     Yet another advantage of the present invention is the provision of an SR machine driving circuit which requires only two power leads for a two phase SR machine. 
    
    
     Still other advantages of the invention will become apparent to those skilled in the art upon a reading and understanding of the following detailed description, accompanying drawings and appended claims. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention may take physical form in certain parts and arrangements of parts, a preferred embodiment and method of which will be described in detail in this specification and illustrated in the accompanying drawings which form a part hereof, and wherein: 
     FIG. 1A illustrates an exemplary two-phase &#34;staggered-tooth&#34; switched reluctance motor; 
     FIG. 1B illustrates an exemplary two-phase &#34;stepped-gap&#34; switched reluctance motor; 
     FIG. 2 is a schematic of a first prior art driving circuit; 
     FIG. 3 is a schematic of a second prior art driving circuit; 
     FIG. 4 is a schematic of a driving circuit according to a preferred embodiment of the present invention; 
     FIGS. 5A-5C show current flow in the driving circuit of FIG. 4, in various modes of operation during excitation of the phase A windings; 
     FIGS. 6A-6C show current flow in the driving circuit of FIG. 4, in various modes of operation during excitation of the phase B windings; 
     FIG. 7 shows the current flow in the driving circuit of FIG. 4, during a transition mode of operation, according to an alternative embodiment of the present invention; 
     FIG. 8A is a current waveform diagram showing the current in phase windings A and B as a function of time, for the driving circuit of FIG. 4 in a standard operating sequence; 
     FIG. 8B is a current waveform diagram showing the current in phase windings A and B as a function of time, for the driving circuit of FIG. 4 in an operating sequence including a transition mode; 
     FIG. 9 shows a driving circuit for an SR motor having N phase windings, according to a preferred embodiment of the present invention; 
     FIG. 10 is an SR motor driving circuit requiring only two power wires, according to another embodiment of the present invention; 
     FIGS. 11A-11C show current flow in the driving circuit of FIG. 10, in various modes of operation during excitation of the phase A windings; and 
     FIGS. 12A-12C show current flow in the driving circuit of FIG. 10, in various modes of operation during excitation of the phase B windings. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the drawings wherein the showings are for the purposes of illustrating a preferred embodiment of the invention only and not for purposes of limiting same, FIG. 1A illustrates an exemplary SR motor 5. In particular, SR motor 5 is a two phase &#34;staggered-tooth&#34; switched reluctance motor. It should be appreciated that the term &#34;switched reluctance,&#34; as used herein, is also intended to refer to &#34;variable reluctance&#34; and &#34;synchronous reluctance.&#34; Moreover, while the present invention is described with particular reference to a switched reluctance motor, the present invention also finds application in connection with a switched reluctance generator. 
     Motor 5 is generally comprised of a stator 10 and a rotor 30. Stator 10 includes stator poles 12 and 14. Each stator pole 12 and 14 is surrounded by a winding (not shown) of one or more turns of electrically conductive material and appropriate insulation. Each phase winding is a set of connected windings respectively wound on stator poles 12 (phase A) and stator poles 14 (phase B). Rotor 30 includes two sets of rotor poles 32 and 34. Rotor poles 32 and 34 differ from each other with regard to their size. As a result, motor 5 is referred to as a &#34;staggered-tooth&#34; SR motor. It should be appreciated that motor 5 is shown solely for the purpose of illustrating a preferred embodiment of the present invention, and that the present invention is suitably used with other SR machine designs. For instance, the present invention is suitably used in connection with exemplary &#34;stepped-gap&#34; SR motor 7 shown in FIG. 1B, as well as more conventional SR machine designs. 
     The phase A and phase B windings are grouped together so that a balanced torque is produced in the motor when the windings are excited from an external source of electrical energy. A variation in reluctance occurs when rotor 30 is rotated with respect to stationary stator poles 12, 14. The variation in reluctance is the result of the variation in the inductance of the phase windings, as is well known by those of ordinary skill in the art. 
     When the respective phase winding is excited with an electrical current as the inductance is increasing from minimum to maximum, a motor torque is developed on shaft 40. In contrast, when the respective phase winding is excited as the inductance is decreasing from a maximum to a minimum, torque opposing the direction of rotation is developed on shaft 40 (i.e., generator torque). 
     The switching or &#34;excitation&#34; of the phase windings is typically accomplished by solid state switching devices such as MOSFETS, transistors, thyristors, insulated gate bipolar transistors (IGBTs), and the like, including combinations thereof. However, benefits of the present invention are most realized when MOSFETS are used, since they include intrinsic diodes, as will be explained in detail below. 
     FIG. 4 illustrates a driving circuit 70 for driving a 2-phase SR motor in accordance with a preferred embodiment of the present invention. Driving circuit 70 is generally comprised of phase windings A and B, switches Q1, Q2, Q3 and Q4, and a pair of individual freewheeling diodes D1 and D2. Switches Q2 and Q3 are associated with phase winding A, and switches Q1 and Q4 are associated with phase winding B, as will be described below. It should be appreciated that since MOSFETS are used as the preferred switching device, circuit 70 includes intrinsic diodes ID1, ID2, ID3 and ID4, respectfully associated with switches Q1, Q2, Q3 and Q4. Switches Q1, Q2, Q3 and Q4, each have three electrodes, one of which is a control electrode for controlling the turning ON and OFF of the respective switch. A capacitor C1 filters the DC energy source (supply voltage Vs). Supply voltage Vs provides a source of electrical energy to driving circuit 70. It should be appreciated that the MOSFETS can also be used as synchronous rectifiers, and reduce power (I 2  R) losses. An optional sense resistor R1 may be arranged between terminals 74 and 75. This allows the current flowing through the supply voltage Vs to be measured by a suitable current sensing circuit. As a result, the current flowing through the phase windings can be measured. 
     It should be understood that a switching controller (not shown) generates control signals to control the switching of switches Q1, Q2, Q3 and Q4. The control signals are generated in accordance with prior art techniques and may be in response to sensor signals, pre-programmed signals (e.g., stored in ROM), manually-controlled signals, or a combination thereof. The design of the switch controller does not form a part of the present invention, except that it must be capable of operating switches Q1, Q2, Q3 and Q4 to provide appropriate gate trigger signals. It should be appreciated that the sequence of current flow for each phase winding may take many suitable forms, including sequential or overlapping. 
     Driving circuit 70 has three basic modes of operation for current control, namely, a positive voltage loop (PVL), a zero voltage loop (ZVL) and a negative voltage loop (NVL). During the PVL mode a positive voltage is applied across the respective phase winding, generally resulting in an increase in the current flowing therethrough. During the ZVL mode a short circuit is placed across the respective phase winding. However, with practical circuit components, the current in the respective phase winding will slowly decay, as the energy is dissipated in the phase winding resistance. As a result, a ZVL mode is usually alternated with a PVL mode to regulate the current in the respective winding (i.e., &#34;chopping&#34;). Lastly, in the NVL mode a negative voltage is applied across the respective phase winding. This causes the current in the respective phase winding to fall as energy is returned from the respective phase winding to the supply voltage Vs. It will be appreciated that an important advantage of the present invention is the redirection of a portion of the current to the adjacent phase during the transition without exiting the motor. This results in a significant improvement in efficiency. 
     Operation of driving circuit 70 in each of the foregoing modes will now be described in detail with reference to FIGS. 5A-5C and 6A-6C. FIGS. 5A-5C illustrate circuit operation during the excitation period for phase A, while FIGS. 6A-6C illustrate circuit operation during the excitation period for phase B. 
     To begin phase A excitation, switches Q2 and Q3 are switched ON. As a result, the positive terminal 72 of DC supply voltage Vs is connected to terminal 82 of phase winding A, and the negative terminal 74 of DC supply voltage Vs is connected to terminal 84, which is a common node shared by phase windings A and B. Diodes D1, D2 are reverse biased. Accordingly, supply voltage Vs is applied to the inductors comprising phase winding A in a positive voltage loop (PVL). This results in an increase in the phase A current. Current flows in the following loop (FIG. 5A): phase winding A--switch Q3--supply voltage Vs--switch Q2. 
     When the peak current level is reached, switch Q2 is turned OFF, while switch Q3 remains ON. As a result, freewheeling diode D1 becomes forward biased. Accordingly, terminal 82 is connected to negative terminal 74 through diode D1. Since switch Q3 remains ON, terminal 84 is also connected to negative terminal 74. Therefore, the inductors comprising phase winding A are short circuited in a zero voltage loop (ZVL). The current flows in the following loop (FIG. 5B): phase winding A--switch Q3--diode D1. 
     As indicated above, the phase A current will slowly decay. To maintain the current in phase winding A for the desired duration, switch Q2 is toggled between ON and OFF. When switch Q2 is ON, the circuit returns to the PVL mode, whereas, when switch Q2 is OFF, the circuit returns to the ZVL mode. The changes in the phase A current are observed as ripples in the current waveforms shown in FIGS. 8A and 8B, which are described below. It should be understood that alternatively switch Q2 may remain ON, while switch Q3 is toggled OFF and ON. 
     When it is the appropriate time to decrease the phase A current to zero, switches Q2 and Q3 are both turned OFF. As a result, diode D1 and intrinsic diode ID1 of switch Q1 become forward biased. As a result, the current flows in a NVL as follows (FIG. 5C): phase winding A--intrinsic diode ID1--supply voltage Vs--diode D1. It should be understood that all switches Q1, Q2, Q3 and Q4 will typically remain OFF for only a relatively short period of time. 
     To begin the subsequent excitation of the phase B winding, switches Q1 and Q4 are turned ON. Therefore, current flows in a PVL as follows (FIG. 6A): phase winding B--switch Q4--supply voltage Vs--switch Q1. Consequently, the current in the inductors comprising phase winding B will steadily increase. The phase A winding will remain in an NVL, as shown by the dashed lines of FIG. 6A, during at least a portion of the phase B winding PVL. In this respect, the current flowing through the phase A winding may reduce to zero before, concurrent with, or after, the current flowing through the phase B winding has reached its peak level (i.e., the end of the phase B PVL). 
     When the peak current level is reached, switch Q1 is turned OFF. As a result, intrinsic diode ID3 of switch Q3 becomes forward biased. Therefore, current flows in a ZVL as follows (FIG. 6B): phase winding B--switch Q4--intrinsic diode ID3. This results a gradual decay in the phase B current. To maintain the current for the desired duration, switch Q1 is toggled between ON and OFF. When switch Q1 is ON, the circuit is in the PVL mode, and when switch Q1 is OFF, the circuit is in the ZVL mode. It should be understood that alternatively switch Q1 may remain ON, while switch Q4 is toggled OFF and ON. 
     When it is the appropriate time to decrease the phase B current to zero, switches Q1 and Q4 are both turned OFF. As a result, diode D2 and intrinsic diode ID3 become forward biased. Therefore, the current flows in a NVL as follows (FIG. 6C): phase winding B--diode D2--supply voltage Vs--intrinsic diode ID3. It should be understood that all switches Q1, Q2, Q3 and Q4 will typically remain OFF for only a relatively short period of time. 
     To begin the subsequent excitation of the phase A winding, switches Q2 and Q3 are turned ON. Therefore, current flows in a PVL as follows (FIG. 5A): phase winding A--switch Q3--supply voltage Vs--switch Q2. Consequently, the current in the inductors comprising phase winding A will steadily increase. The phase B winding will remain in an NVL, as shown by the dashed lines of FIG. 5A, during at least a portion of the phase A winding PVL. In this respect, the current flowing through the phase B winding may reduce to zero before, concurrent with, or after, the current flowing through the phase A winding has reached its peak level (i.e. the end of the phase A PVL). 
     The phase A excitation will continue as described above, followed by the phase B excitation, as also described above. 
     According to an alternative embodiment of the present invention, a transition mode is used in the period between the ending of a first phase excitation, and the beginning of a subsequent phase excitation. Referring now to FIG. 7, the transition mode will be described in detail. Prior to the transition mode between phase A and phase B, switch Q3 will be turned ON, and switch Q2 will be toggled between ON and OFF (chopping), as the circuit alternates between a ZVL (FIG. 5B) and PVL (FIG. 5A) to regulate the current. To begin the transition mode, switch Q3 is turned OFF, switches Q2 and Q4 are turned ON, and switch Q1 remains OFF. As a result, current simultaneously flows through both phase A and phase B windings, as illustrated in FIG. 7. However, the current flow in the phase A winding is decreasing while the current flow in the phase winding B is increasing. During the transition mode, the current in the phase A winding will decrease to a current level approximately one-half the peak current level, while the phase B winding will increase to a current level approximately one-half the peak current level. The current flow loop during the transition mode is as follows: phase A winding phase B winding--switch Q4--supply voltage Vs--switch Q2. 
     In order for the current flowing through the phase A winding to reduce to zero, the circuit must change to a PVL for phase B (FIG. 6A). Thus, switches Q1 and Q4 are ON, while switches Q2 and Q3 are OFF. When the phase B PVL is initiated, the phase A winding is in a NVL (i.e., &#34;phase A NVL&#34;), as illustrated by the dashed lines in FIG. 6A (it should be noted that there is no FIG. 5C NVL in this alternative embodiment). The current flowing through the phase A winding will continue to reduce to zero. It should be appreciated that the current flowing through the phase A winding may reduce to zero before, concurrent with, or after, the current flowing through the phase B winding has reached its peak level (i.e. the end of the phase B PVL). 
     In a similar manner, prior to the transition mode between phase B and phase A, switch Q4 will be turned ON, and switch Q1 will be toggled between ON and OFF (chopping), as the circuit alternates between a ZVL (FIG. 6B) and PVL (FIG. 6A) to regulate the current. To begin the transition mode, switch Q1 in turned OFF, switches Q2 and Q4 are turned ON, and switch Q3 remains OFF. As a result, current simultaneously flows through both phase A and phase B windings, as illustrated in FIG. 7. However, the current flow in the phase B winding is decreasing while the current flow in the phase winding A is increasing. During the transition mode, the current in the phase B winding will decrease to a current level approximately one-half the peak current level, while the phase A winding will increase to a current level approximately one-half the peak current level. The current flow loop during the transition mode is as follows: phase A winding phase B winding--switch Q4--supply voltage Vs--switch Q2. 
     In order for the current flowing through the phase B winding to reduce to zero, the circuit must change to a PVL for phase A (FIG. 5A). Thus, switches Q2 and Q3 are ON, while switches Q1 and Q4 are OFF. When the phase A PVL is initiated, the phase B winding is in a NVL (i.e., &#34;phase B NVL&#34;), as illustrated by the dashed lines in FIG. 5A (it should be noted that there is no FIG. 6C NVL in this alternative embodiment). The current flowing through the phase B winding will continue to reduce to zero. It should be appreciated that the current flowing through the phase B winding may reduce to zero before, concurrent with, or after, the current flowing through the phase A winding has reached its peak level (i.e. the end of the phase A PVL). 
     Referring now to FIG. 8A, current waveforms for phase A and phase B are shown for the embodiment of driving circuit having a standard operating sequence (i.e., no transition mode). It should be understood that the waveforms are shown solely for the purpose of illustrating the general waveform shape and sequence, and are not shown to scale. 
     During period T 1  phases A and B are overlapped. In this regard, the phase A winding is in the PVL mode, while the phase B winding is in the NVL mode (FIG. 5A). Thus, the current in the phase A winding is increasing, while the current in the phase B windings is decreasing. In this regard, current in the phase A winding flows in the loop: phase A winding--switch Q3--supply voltage Vs--switch Q2. Simultaneously, current in the phase B winding flows in the loop: phase B winding--diode D2--supply voltage Vs--switch Q3. When the current through phase A has reached a maximum current level, period T 2  will begin. 
     As indicated above, the current flowing through the phase B winding may reduce to zero before, concurrent with, or after, the current flowing through the phase A winding has reached its peak level. In FIG. 8A, the current in the phase B winding reaches zero before the current in the phase A winding has reached its peak. 
     During period T 2  the phase A winding toggles between ZVL and PVL modes, while the phase B winding remains inactive. Following period T 2 , the operation continues to period T 3 . 
     During period T 3  the phase A and B are overlapped. In this regard, phase A winding is in the NVL mode, while the phase B winding is simultaneously in the PVL mode (FIG. 6A). Thus, the current in the phase A winding is decreasing, while the current in the phase B windings is increasing. In this regard, current in the phase A winding flows in the loop: phase A winding--switch Q1--supply voltage Vs--diode D1. Simultaneously, current in the phase B winding flows in the loop: phase B winding--switch Q4--supply voltage Vs--switch Q1. When the current through phase B has reached a maximum current level, period T 4  will begin. 
     As indicated above, the current flowing through the phase A winding may reduce to zero before, concurrent with, or after, the current flowing through the phase B winding has reached its peak level. In FIG. 5A, the current in the phase A winding reaches zero before the current in the phase B winding has reached its peak. 
     During period T 4  the phase B winding toggles between ZVL and PVL modes, while the phase A winding remains inactive. Following period T 4 , the operation returns to period T 1 . 
     As indicated above, in an alternative embodiment of the present invention, a transition mode is used. Referring now to FIG. 8B, current waveforms for phase A and phase B are shown for the embodiment of driving circuit having a modified operating sequence (i.e., includes a transition mode). It should be understood that the waveforms are shown solely for the purpose of illustrating the general waveform shape and sequence, and are not shown to scale. 
     During period T 1 , phase A winding is in a PVL, while phase B winding is in a NVL (FIG. 5A). As indicated above, the current flowing through the phase B winding may reduce to zero before, concurrent with, or after, the current flowing through the phase A winding has reached its peak level. In FIG. 8B, the current in the phase B winding reaches zero after the current in the phase A winding has reached its peak. 
     During period T 2 , the current in the phase A winding is maintained, while the current in the phase B winding is reduced to zero. 
     Period T 3  is the transition mode (FIG. 7), wherein the current in the phase A winding is decreasing (NVL), while the current in the phase B winding is increasing (PVL). During period T 4 , the phase A winding is in a NVL, while the phase B winding is in a PVL (FIG. 6A). As indicated above, the current flowing through the phase A winding may reduce to zero before, concurrent with, or after, the current flowing through the phase B winding has reached its peak level. In FIG. 8B, the current in the phase A winding reaches zero after the current in the phase B winding has reached its peak. 
     During period T 5 , the current in the phase B winding is maintained, while the current in phase A winding is reduced to zero. Period T 6  is another transition mode, wherein the current in the phase B winding is decreasing (NVL), while the current in the phase A winding is increasing (PVL). 
     Referring now to FIG. 9, there is shown a schematic illustrating the driving circuit of the present invention as configured for use with an SR machine having N phases, where N is greater than 2. It should be appreciated that the total switch count becomes 2N, where N is the number of phases, while the total number of individual diodes remains at two (i.e., diodes D1 and D2). Moreover, the number of machine lead connections remains at N+1. A pair of switches is associated with each phase winding. In this respect, the first switch is connected between the positive terminal of the DC supply voltage potential and a first terminal of the phase winding, while the second switch is connected between the negative terminal of the DC supply voltage potential and a second terminal of the phase winding. 
     The operation of driving circuit 70N for N phase windings is similar to the operation of driving circuit 70 for two phase windings. In this regard, switches Q1A and Q1B are turned ON and OFF in the manner discussed above to control the flow of current through the phase 1 winding. In particular, switches Q1A and Q1B are turned ON during a PVL. During a ZVL, switch Q1A is turned OFF, switch Q1B is turned ON, and diode D1 is forward biased. Switch Q1A may be toggled ON and OFF, while switch Q1B is ON, in order to regulate the current through the phase winding. During a NVL, switches Q1A and Q1B are turned OFF, while diode D1 and the intrinsic diode of switch Q2A are forward biased. 
     Similarly, switches Q2A and Q2B are turned ON and OFF in the manner discussed above to control the flow of current through the phase 2 winding. In particular, switches Q2A and Q2B are turned ON during a PVL. During a ZVL, switch Q2A is turned OFF, switch Q2B is turned ON, and the intrinsic diode of switch Q1B is forward biased. Switch Q2A may be toggled ON and OFF, while switch Q2B is ON, in order to regulate the current through the phase winding. During a NVL, switches Q1A and Q1B are turned OFF, and the intrinsic diodes of switches Q1B and QNA are forward biased. 
     For the phase N winding, switches QNA and QNB are likewise turned ON and OFF to control current flow through the phase N winding. In particular, switches QNA and QNB are turned ON during a PVL. During a ZVL, switch QNA is turned OFF, switch QNB is turned ON, and the intrinsic diode of switch Q2B is forward biased. Switch QNA may be toggled ON and OFF, while switch QNB is ON, in order to regulate the current through the phase winding. During a NVL, switches QNA and QNB are turned OFF, and the intrinsic diode of switch Q2B and diode D2 are forward biased. 
     When driving circuit 70N is used in the transition mode described above, the first switch associated with the phase winding whose excitation period is ending and the second switch associated with the phase winding whose excitation period is beginning are turned ON, while the remaining switches of the driving circuit are turned OFF. As a result, current flow decreases in the phase winding that is ending its excitation period and current flow increases in the phase winding that is beginning its excitation period. For example, where N=3, switches Q2A and QNB will be turned ON during the transition mode from phase 2 to phase N. Likewise, switches Q1A and Q2B will be turned ON during the transition mode from phase 1 to phase 2. 
     As can be observed from FIG. 9, a pair of switches is added to the driving circuit for each additional phase winding. Accordingly, the driving circuit of the present invention may be configured for use in connection with SR machines having a large number of phases. 
     FIG. 10 illustrates yet another embodiment of the present invention. Driver circuit 170 is adapted to drive a 2-phase SR motor, using only two power wires. As noted above, a typical driving scheme used to energize an SR machine is the independent half bridge output stage (FIG. 2). One important drawback to this driving scheme, as well as other prior art driving schemes, is the need for two connections per phase for power leads. Moreover, they lack the ability to use standard full bridge output modules designed for PM brushless motors. 
     The two power wires are connected at terminals T1 and T2. Essentially, driver circuit 170 uses a standard full bridge output module, with 2 diodes D A  and D B  embedded in the machine (e.g., motor). Accordingly, in a preferred embodiment of the present invention, driver circuit 170 is generally comprised of switching means Q1-Q4 (with associated intrinsic diodes ID1-ID4), and diodes D A  and D B . Diodes D A  and D B  are located local to the motor. 
     Operation of driving circuit 170 will now be described in detail with reference to FIGS. 11A-11C and 12A-12C. FIGS. 11A-11C illustrate circuit operation during the excitation period for phase A, while FIGS. 12A-12C illustrate circuit operation during the excitation period for phase B. 
     To begin phase A excitation, switches Q1 and Q4 are switched ON. As a result, the positive terminal 72 of DC supply voltage Vs is connected to terminal T1, and the negative terminal 174 of supply voltage Vs is connected to terminal T2. Diode D A  is forward biased, while diode D B  is reverse biased. Accordingly, supply voltage Vs is applied to the inductors comprising phase winding A in a positive voltage loop (PVL). This results in a steady increase in the phase A current. Current flows in the following loop (FIG. 11A): phase winding A--diode DA--switch Q4--supply voltage Vs--switch Q1. 
     When the peak current level is reached, switch Q1 is turned OFF, while switch Q4 remains ON. As a result, intrinsic diode ID3 of switch Q3 becomes forward biased. Accordingly, terminal T1 is connected to negative terminal 174 through intrinsic diode ID3. Since switch Q4 remains ON, terminal T2 is also connected to negative terminal 174. Therefore, the inductors comprising phase winding A are short circuited in a zero voltage loop (ZVL). The current flows in the following loop (FIG. 11B): phase winding A--diode DA--switch Q4--intrinsic diode ID3. 
     The phase A current will slowly decay. To maintain the current in phase winding A for the desired duration, switch Q1 is toggled between ON and OFF (i.e., chopping). When switch Q1 is ON, the circuit returns to the PVL mode, whereas, when switch Q1 is OFF, the circuit returns to the ZVL mode. 
     When it is the appropriate time to decrease the phase A current to zero, switches Q1 and Q4 are both turned OFF. As a result, intrinsic diode ID2 of switch Q2 and intrinsic diode ID3 of switch Q3 become forward biased. As a result, a negative supply voltage Vs is applied to the windings of phase A. The current flows in a NVL as follows (FIG. 11C): phase winding A--diode D A  --intrinsic diode ID2--supply voltage Vs--intrinsic diode ID3. 
     To begin the subsequent excitation of the phase B winding, switches Q2 and Q3 are turned ON. Therefore, current flows in a PVL as follows (FIG. 12A): phase winding B--switch Q3--supply voltage Vs--switch Q2--diode D B . Consequently, the current in the inductors comprising phase winding B will steadily increase. 
     When the peak current level is reached, switch Q2 is turned OFF. As a result, intrinsic diode ID4 of switch Q4 becomes forward biased. Therefore, current flows in a ZVL as follows (FIG. 12B): phase winding B--switch Q3--intrinsic diode ID4--diode D B . This results in a gradual decay in the phase B current. To maintain the current for the desired duration, switch Q2 is toggled between ON and OFF (i.e., chopped). When switch Q2 is ON, the circuit is in the PVL mode, and when switch Q2 is OFF, the circuit is in the ZVL mode. 
     When it is the appropriate time to decrease the phase B current to zero, switches Q1 and Q4 are both turned OFF. As a result, intrinsic diode ID1 of switch Q1 and intrinsic diode ID4 of switch Q4 become forward biased. As a result, a negative supply voltage Vs is applied to the windings of phase B. The current flows in a NVL as follows (FIG. 12C): phase winding B--intrinsic diode ID1--supply voltage Vs--intrinsic diode ID4--diode D B . The foregoing cycle repeats itself again with the excitation of phase A, as described above. 
     Notably, driver circuit 170 allows decaying current from a phase just turned OFF to be routed to the other phase, just turned ON, internal to the motor. This reduces the losses associated with the current normally exiting the motor and being rerouted back from the driver circuit. The free-wheeling current from one phase gets shunted to the opposite phase, thus reducing the current that the power leads and driver circuit need to manage. The energized phase is determined by the polarity of the voltage across the two power leads. With reference to FIGS. 11A-11C and 12A-12C, it should be understood that the phase B PVL will initially overlap with the end of the phase A NVL. In this respect, the current flowing through the phase A winding will be decreasing as the current flowing through the phase B winding is increasing. The simultaneous current flow through phase A winding is shown by the dashed lines in FIG. 12A. Likewise, the phase B NVL will also initially overlap with the end of the phase A PVL. Thus, the current flowing through the phase B winding will be decreasing as the current flowing through the phase A winding is increasing. The simultaneous current flow through phase B winding is shown by the dashed lines in FIG. 11A. It should be noted that the waveform for circuit 170 will be similar to the waveform shown in FIG. 8A. 
     It will be appreciated that an SR machine having an even multiple of phases can be driven by using one driver circuit 170 for every two phases. For instance, a four phase SR machine requires two driver circuits 170, wherein the first driver circuit is for phases 1 and 2, and the second driver circuit is for phases 3 and 4. 
     The invention has been described with reference to a preferred embodiment. Obviously, modifications and alterations will occur to others upon a reading and understanding of this specification. It is intended that all such modifications and alterations be included insofar as they come within the scope of the appended claims or the equivalents thereof.