Abstract:
A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to clock generation circuitry and, in particular, the clock generation which includes duty cycle control. 
         [0003]    2. Description of Related Art 
         [0004]    There are many applications for clock generation circuitry. In some instances, the clock produced by such circuitry must have a very precise duty cycle. The usual definition of duty cycle is the ratio of the clock high period to the total clock period in terms of percentage. One problem frequently encountered in oscillator and clock generator design is the difficulty in obtaining a symmetrical duty cycle of 50%, which is clock having equal high and low periods. This is particularly true when an odd integer divider is involved. Various circuits and methods have been proposed to address these issues. As will be seen, many of the solutions may provide acceptable performance in some circumstances but are not able to accommodate the precision and wide dynamic rage required in certain applications such as clock drivers used for switching DC to DC converters used in modern integrated power management systems. 
         [0005]    Generally, previous designs for duty cycle control utilize a digital delay line approach or an analog delay line approach. Referring to the drawings,  FIG. 1  is a simplified diagram of an exemplary prior art clock generator circuit utilizing a digital delay line which is configured to produce a nominal 50% duty cycle which can be varied in a somewhat controlled manner.  FIG. 2  is a related timing diagram. Further details of the circuit are disclosed in U.S. Pat. No. 6,822,497, the contents of which are fully incorporated herein by reference. Clock Fin shown in  FIG. 2  is provided by an oscillator or other clock generator  20 . It can be seen from waveform  28 A that the duty cycle of Fin is substantially less than 50%. 
         [0006]    Clock Fin and a delayed version DFin (waveform  28 B) are coupled to the S and R inputs of a latch  24 . The output clock Fout having the controlled duty cycle is produced as the Q output of latch  24 . A current controlled delay circuit  22  provides a delay D to produce DFin. In order to provide a nominal 50% duty cycle, delay D has a duration equal to one-half the period of clock Fin. Delay circuit  22  typically includes one or more CMOS gates, having a controllable power supply current which alters the propagation delay through the gates. These delay gates may be followed by R and C elements. In this case, the value of delay D can be altered over a given range by controlling the current through line  32  connected to the power source for the delay gates. The rising edge  34 A of clock Fin triggers a one shot within latch  24  to produce a narrow pulse that will set the latch output Q to a high state. The rising edge  34 B of delay clock DFin also triggers a one shot within latch  24  which resets the latch causing Fout to switch back to a low state. 
         [0007]    A delay setting circuit  30  produces a current on line  32  for setting the duty cycle of Fout. In addition, a duty cycle converter  26  provides a fed back correction current on line  32  to maintain the duty cycle at the desired point. Circuit  26  typically includes a pair of equal current sources, with a first current source charging a capacitor when Fout is in a first state and with the second current source discharging the capacitor when Fout is in a second state, with the voltage on the capacitor representing the duty cycle. Converter  26  produces a correction current on line  32  from the duty cycle voltage on the capacitor which is also indicative of the sensed duty cycle. This correction current in combination with the primary current provided by the current produced by circuit  30  operates to maintain Fout at the desired duty cycle. 
         [0008]      FIGS. 3 and 4  illustrate a further approach to producing a clock having a precise duty cycle. Generally, an analog pulse reshaping monostable multivibrator scheme is employed. Further details of this approach are set forth in U.S. Pat. No. 7,123,179, the contents of which are fully incorporated herein by reference. An oscillator circuit  36  produces a clock Fin having a duty cycle in this example of significantly less than 50% ( FIG. 4 ). The rising edge of Fin triggers a one shot  38  that produces a relatively narrow pulse that operates to momentarily turn ON a transistor  40  so as to discharge a capacitor C 1 . When the pulse terminates, transistor  40  is turned OFF so that a current source  42  can charge capacitor C 1  thereby producing a ramp voltage Ramp at the positive input of a comparator  44 . The other input to comparator  44  is a voltage Vref to be described. 
         [0009]    Comparator  44  produces the clock output Fout. A duty cycle to voltage converter circuit  46  splits Fout into two channels  48 A and  48 B. The input of channel  48 A has an exclusive OR circuit (a high output is produced when the inputs differ), with one input for receiving Fout and the other input connected to a logic “0”. The result is Fout+ shown in  FIG. 4  which is in phase with Fout. The input of channel  48 B also has an exclusive OR circuit with one input for receiving Fout and the other input connected to a logic “1”. The result is Fout− shown in  FIG. 4  which is out of phase with respect to Fout and Fout+. Circuit  48 A includes an RC circuit which operates to integrate Fout− to provide a voltage Vavg 1  at node  50 A indicative of the duration of the high state of Fout−. Similarly, circuit  48 B includes an RC circuit which operates to integrate Fout+ to produce a voltage Vavg 2  at node  50 B indicative of the high state of Fout+. 
         [0010]    An error amplifier  52  provides an output Vref indicative of the difference between Vavg 1  and Vavg 2  which is filtered by a capacitor C 2 . Voltage Vref is also indicative of the duty cycle of Fout. If Vavg 1  and Vavg 2  are equal, the duty cycle is 50%. An offset circuit  52  can be used in one of the channels (Fout+ in this case) to provide an adjustable offset for target duty cycles other than 50%. Comparator  44  changes state when voltage Ramp has increased to Vref, thereby producing a falling edge on Fout. Feedback of voltage Vref tends to maintain Fout at the desired duty cycle. 
         [0011]    The above described exemplary approaches for providing an output clock having a controlled duty cycle are adequate under many operating conditions. However, shortcomings exist limiting their use in certain high performance applications. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention, the present invention addresses many of those shortcomings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a circuit diagram of a prior art clock generator with duty cycle control. 
           [0013]      FIG. 2  is a timing diagram illustrating operation of the  FIG. 1  clock generator. 
           [0014]      FIG. 3  is a circuit diagram of another prior art clock generator with duty cycle control. 
           [0015]      FIG. 4  is a timing diagram illustrating operation of the  FIG. 3  clock generator. 
           [0016]      FIG. 5  is circuit diagram of a clock generator circuit in accordance with a first embodiment of the present invention. 
           [0017]      FIG. 6  is a timing diagram illustrating operation of the  FIG. 5  clock generator. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    Referring again to the drawing, the previously described clock generation circuitry of  FIG. 1  provides acceptable performance for many applications. However, current clock accuracy requirements require duty cycle control over a ±50% dynamic range for frequencies ranging from 250 KHz to 6 MHz which translates to a delay circuit with an operable span from ±1 μs to ±42 ns. It is not practical or cost effective to provide this kind of performance using the approach of  FIG. 1 , including the delay circuit  22 . In addition, the duty cycle to current converter  26  tends to be sensitive to variations in power supply and the various RC elements used in the circuit. 
         [0019]    Similarly, although the previously described clock generator circuit of  FIG. 3  provides a relatively wide range of duty cycles, there are shortcomings. Since a comparator  44  is used directly as a pulse shaper, the slow rising edge of voltage Ramp at the input requires that the comparator have a moderate degree of hysteresis to suppress multiple pulses due to noise. This poses a limitation on generating a high frequency clock. Further, the  FIG. 3  circuit is sensitive to variations in power supply voltage(s) because the rail to rail output of comparator  44  is directly integrated by the RC circuits of elements  48 A and  48 B. These and other errors attributable to supply voltage changes could be mitigated to some extent using an internal LDO voltage regulator, but this adds complexity. Further, a voltage regulator has a limited bandwidth which cannot nullify high frequency noise present on the power supply. 
         [0020]      FIG. 5  depicts one embodiment of the present invention which addresses the above-described shortcomings. The clock generator circuit  54  includes an oscillator circuit  56  which produces an input clock Fin as shown in the timing diagram of  FIG. 5 . A first one shot  58 A produces an output pulse in response to the rising edge, with the short pulse width corresponding to the delay provided by an inverter (not designated) in the one shot. The pulse operates to clock a bi-stable circuit. In the present case, the bi-stable circuit a D type flip-flop circuit (flip-flop)  62  by way of an OR gate  60 . The output clock Fout is produced at the Q output of flip-flop  62 . As is well known, a D type flip-flop transfers the state at the D input to the Q output upon receipt of a clock. A power on resent (POR) initializes flip-flop  62  so that the Q output Fin is a “1”. Since the D input is connected to the Q —  output, the D input is a “0” so that the Q output Fout transitions to a low state upon receipt of the clock pulse as shown in the  FIG. 5  timing diagram. Eventually, a second one shot  58 B will be triggered thereby producing a narrow pulse that again clocks flip-flop  62  by way of gate  60 , causing the Q output Fout to transition to a high state. 
         [0021]    P type transistor  64  and N type transistor  66  form part of a duty cycle detection circuit, with the respective gates connected in common to the Q —  output of flip-flop  62 . The respective drain electrodes of the two transistors are connected together, with the source electrode of transistor  64  connected to a current source I 1  and with the source electrode of transistor  66  connected to another current source I 2 , with sources I 1  and I 2  being equal. Current source I 1  and switch  64  are connected intermediate a common node and the upper supply rail (VDD), with current source I 2  and switch  66  being connected intermediate the common node and the lower supply rail (ground). Thus, when Q —  is high, transistor  66  is ON and transistor  64  is OFF so that current I 2  is sunk from line  67 . Conversely, with Q —  is low, transistor  64  is ON and transistor  66  is OFF so that current I 1  is sourced onto line  67 . When Fout has a 50% duty cycle, the net current flowing though line  67  over time, sometimes referred to as the duty cycle current, is zero. 
         [0022]    A third current source I 3  has an output connected to a current summing node  68 , with line  67  also being connected to the node. The current one line  67  along with that from source I 3  flows through a capacitor C, with the capacitor being charged by the sum of the two currents flowing into node  68 . Capacitor C is discharged at the beginning of each cycle when the output of one shot  58 A momentarily turns ON a transistor  72 . The values of current I 1 /I 2  and I 3  along with that of capacitor C are selected such that for a duty cycle near the target duty cycle, the voltage Vcap on node  68  is midway between the power supply rails near the end of each clock cycle. That means that I 3  must be substantially larger than I 1 /I 2 . A comparator  70  compares the voltage Vcap with a reference voltage Vref, with the comparator  70  output switching to a high state when Vcap has charged up to Vref as shown in the  FIG. 6  timing diagram. 
         [0023]    When comparator  70  switches to a high state, the rising edge of the output triggers one shot  58 B which clocks flip-flop  62  though OR gate  60 . Since Q —  is high at this point, the D input is low so that output Q and Fout transition back to the high state. The target duty cycle can be varied by changing the value of Vref and/or the value of I 3 . Should the actual duty cycle increase from the target value for some reason, transistor  64  will be conductive longer than it should be and transistor  66  will be conductive for too short a time. This means that the net current on line  67  will be too large so that capacitor C will charge more quickly to Vref. This increased rate of change of Vcap means that comparator  70  will change state sooner in the cycle. Thus, feedback provided by comparator  70  to one shot  58 B will cause output Q and Fout to switch to the high state earlier in the cycle thereby correcting for the duty cycle error. In the event the duty cycle is below the target value for some reason, the net current on line  67  will be too low so that Vcap will take more time to transition up to Vref. Thus, output Q and Fout will switch to the high state later in the cycle thereby compensating for the duty cycle error. Note that for duty cycles that differ substantially from 50% can be accommodated so that the switching voltage for comparator  70  remains within the ideal operating range. 
         [0024]    The voltage references and current sources can be accurately generated by central biasing circuitry. The references should have precision parameters which are independent of temperature and supply voltage and can be process trimmed. Further, pulse width shaping using edge triggered logic such as flip-flop  62  performs time domain filtering which eliminates level/noise issues. Comparator  70  can be a very high speed device which utilizes little or no hysteresis thereby increasing the circuit bandwidth. Circuit complexity is reduced since only a single capacitor need be used versus banks of capacitors and resistors. In addition, only a single comparator need be used. This in combination with current mode processing at node  68 , as opposed to integrating voltage signals, results shorter transport delays which also allows higher frequency operation. 
         [0025]    Thus, an embodiment of the present invention has been disclosed. Although this embodiment have been described in some detail, changes can be made by those of ordinary skill in the art without departing from the spirit and scope of the present invention as defined by the appended claims.