Abstract:
A method for fabricating a recessed-gate transistor is disclosed. A trench is recessed into a substrate. A poly/nitride spacer is formed on sidewalls of the trench. A trench bottom oxide is formed. The spacer is then stripped off. A source/drain doping region is formed on the exposed sidewalls of the trench in a self-aligned fashion. The trench bottom oxide is then stripped, thereby forming a curved gate channel.

Description:
BACKGROUND OF THE INVENTION  
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to method of fabricating a semiconductor device and, more particularly, to a method for fabricating a recessed-gate metal-oxide-semiconductor (MOS) transistor device having a self-aligned arc-shaped trench bottom channel. 
         [0003]    2. Description of the Prior Art 
         [0004]    With the continuing shrinkage of device feature size, the so-called short channel effect (SCE) due to shrunk gate channel length has been found that it can hinder the integrity of integrated circuit chips. Many efforts have been made for solving this problem, for example, by reducing the thickness of the gate oxide dielectric or by increasing the doping concentration of source/drain. However, these approaches adversely affect the device reliability and speed of data transfer on the other hand, and are thus impractical. 
         [0005]    A newly developed recessed-gate MOS transistor becomes most promising. In the filed of Dynamic Random Access Memory (DRAM), the recessed-gate technology may be used to improve the integrity of the memory chip. Typically, the recess-gate MOS transistor has a gate insulation layer formed on sidewalls and bottom surface of a recess etched into a substrate, a conductive filling the recess, contrary to a planar gate type transistor having a gate electrode formed on a planar surface of a substrate. 
         [0006]    However, the aforesaid recess-gate MOS transistor has some shortcomings. For example, the recess for accommodating the gate of the MOS transistor is etched into a semiconductor wafer by using conventional dry etching methods. It is so difficult to form recesses having the same depth across the wafer that a threshold voltage control problem arises. Further, as the width of the recess shrinks, the channel length is reduced, resulting in short channel effect. 
       SUMMARY OF THE INVENTION  
       [0007]    It is one object of this invention to provide a method of fabricating a recess-gate MOS transistor device having a self-aligned arc-shaped channel at trench bottom in order to solve the above-mentioned problems. 
         [0008]    According to the claimed invention, a method of fabricating a recess-gate transistor device is disclosed. A semiconductor substrate is provided. A gate trench is etched into the semiconductor substrate. The gate trench comprises a trench bottom and a trench sidewall. A spacer comprising a polysilicon layer is formed on the trench sidewall. A trench bottom oxide layer is formed at the trench bottom. The spacer is removed to expose the trench sidewall. A source/drain diffusion region is doped into the trench sidewall. An insulating mask layer is formed on the trench sidewall. The trench bottom oxide layer is removed to form an arc-shaped trench bottom. A gate dielectric layer is formed on the arc-shaped trench bottom. The gate trench is then filled with conductive gate material. 
         [0009]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0010]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: 
           [0011]      FIGS. 1-7  are schematic, cross-sectional diagrams illustrating a method of fabricating a recess-gate MOS transistor in accordance with one preferred embodiment of this invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0012]      FIGS. 1-7  are schematic, cross-sectional diagrams illustrating a method of fabricating a recess-gate MOS transistor in accordance with one preferred embodiment of this invention. As shown in  FIG. 1 , a semiconductor substrate  10  such as a silicon substrate, silicon epitaxital substrate or Silicon-On-Insulator (SOI) substrate is provided. A pad oxide layer  12  is then formed on the main surface of the semiconductor substrate  10 . A pad nitride layer  14  is then deposited on the pad oxide layer  12 . 
         [0013]    The aforesaid pad oxide layer  12  may be formed by conventional thermal oxidation methods or Chemical Vapor Deposition (CVD) methods. Preferably, the pad oxide layer  12  has a thickness of about 10-500 angstroms. The pad nitride layer  14  may be formed by low-pressure CVD methods or other CVD methods. The pad nitride layer  14  has a thickness of about 500-5000 angstroms. 
         [0014]    Subsequently, a lithographic and etching process is carried out to form a gate trench  16  in the semiconductor substrate  10 . The gate trench  16  has a trench bottom  16   a  and trench sidewall  16   b.  The aforesaid lithographic and etching process generally comprises the steps of forming a photoresist layer on the pad nitride layer  14 , exposing the photoresist layer to light, developing the photoresist layer to form an opening therein, etching the exposed pad nitride layer  14 , the pad oxide layer  12  and the semiconductor substrate  10  via the opening, thereby forming the gate trench  16 . The photoresist layer is then stripped off. 
         [0015]    As shown in  FIG. 2 , after the formation of the gate trench  16 , an oxidation process is performed to form a thin silicon oxide layer  18  on both the trench bottom  16   a  and the trench sidewall  16   b.  Preferably, the thin silicon oxide layer  18  has a thickness of about 10-500 angstroms. Thereafter, a conformal polysilicon layer  42  is deposited on the pad nitride layer  14  and covers the trench sidewall  16   b  and trench bottom  16   a.  A thin silicon nitride layer  44  is then deposited on the conformal polysilicon layer  42 . An anisotropic dry etching process is carried out to etch the thin silicon nitride layer  44  and exposes the underlying polysilicon layer  42  at the trench bottom  16   a.  An isotropic etching process is then carried out to etch away the exposed polysilicon layer  42  at the trench bottom  16   a  to expose the underlying silicon oxide layer  18 , thereby forming a polysilicon/nitride spacer  46  on trench sidewall  16   b.  The lateral etching of the polysilicon layer  42  at the trench bottom  16   a  leads to a reverse-T shaped gate trench  16 . 
         [0016]    As shown in  FIG. 3 , using the polysilicon/nitride spacer  46  as a hard mask, a thermal oxidation process such as Localized Oxidation of Silicon (LOCOS) process is carried out to grow a trench bottom oxide layer  20  at the exposed trench bottom  16   a  of the gate trench  16 . The trench sidewall  16   b  is masked and protected by the polysilicon/nitride spacer  46 . 
         [0017]    It is one salient feature that the lower portion of the polysilicon layer  42  of the polysilicon/nitride spacer  46  alleviates so-called bird&#39;s beak effect during the aforesaid thermal oxidation process for the formation of the trench bottom oxide layer  20 . The polysilicon layer  42  of the polysilicon/nitride spacer  46  stops the over-oxidation of the lower portion of the trench sidewall  16   b  during the thermal oxidation. 
         [0018]    As shown in  FIG. 4 , the polysilicon/nitride spacer  46  on the trench sidewall  16   b  of the gate trench  16  is removed to expose the thin silicon oxide layer  18 . The polysilicon/nitride spacer  46  may be removed by conventional wet etching process such as heated phosphoric acid solution for removing the nitride and ammonia solution for removing polysilicon, but not limited thereto. Optionally, the silicon oxide layer  18  on the trench sidewall  16   n  is removed after removing the polysilicon/nitride spacer  46 . 
         [0019]    As shown in  FIG. 5 , a source/drain diffusion region  22  is formed on the trench sidewall  16   b  of the gate trench  16 . To form the source/drain diffusion region  22 , a conventional Gas-Phase Diffusion (GPD) may be employed. Alternatively, the source/drain diffusion region  22  may be formed by first depositing a doped silicate glass such as Phosphorus-doped Silicate Glass (PSG), Arsenic-doped Silicate Glass (ASG) or Boron-doped Silicate Glass (BSG), followed by thermal drive-in. In another case, the source/drain diffusion region  22  may be formed by tilt-angle ion implantation methods. 
         [0020]    As shown in  FIG. 6 , after the formation of the source/drain diffusion region  22 , a silicon nitride spacer  23  is then formed on the trench sidewall  16   b.  The silicon nitride spacer  23  covers the source/drain diffusion region  22  and exposes the trench bottom oxide layer  20 . An etching process is then carried out to remove the trench bottom oxide layer  20 , thereby forming an arc-shaped trench bottom  16   c  in the gate trench  16  and an extended, curved channel region  24  between the source/drain diffusion regions  22 . The etching process for removing the trench bottom oxide layer  20  may be conventional wet etching processes such as diluted HF, but not limited thereto. 
         [0021]    The aforesaid silicon nitride spacer  23  may be formed by first depositing a conformal silicon nitride layer that covers the pad nitride layer  14 , the trench sidewall  16   b  and the trench bottom oxide layer  20 , then anisotropically dry etching the silicon nitride layer to remove the silicon nitride layer that covers the pad nitride layer  14  and trench bottom oxide layer  20 . 
         [0022]    As shown in  FIG. 7 , on the exposed arc-shaped trench bottom  16   c  in the gate trench  16 , a gate oxide layer  28  is formed. According to the preferred embodiment of this invention, the gate oxide layer  28  is formed by In-Situ Steam Growth (ISSG) method, but not limited thereto. Preferably, the gate oxide layer  28  has a thickness of about 10-500 angstroms. 
         [0023]    Finally, the gate trench  16  is filled with conductive gate material  36  such as doped polysilicon. Preferably, a Chemical Mechanical Polishing (CMP) is performed to remove excess conductive gate material  36  outside the gate trench  16 . 
         [0024]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.