Abstract:
A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates to receiving and decoding serial digital data, and particularly to a high resolution, high speed, digital phase lock loop circuit that decodes Manchester encoded data into NRZ data and a clock signal. 
     2. Description of the Prior Art 
     Many kinds of information can be encoded and represented by binary numbers. A binary number has a predetermined length or number of digits, for example eight, and each digit has one of two possible values. A binary number may be expressed electronically by using high and low voltage signals known as no return to zero (&#34;NRZ&#34;) bit signals, as shown, for example, in FIG. 1(a). These signals may be communicated from a transmitter to a receiver. It is commonly desirable to perform such communications through a single wire or equivalent path. This is done by transmitting the bits of one binary number (byte) serially, followed by the bits of the next byte, and so on. 
     For successful error free communication, the receiver must be able to distinguish individual bits. For example, two successive low voltage signals must not be mistaken for a single low signal. In general, serial transmitters use a precision clock to transmit data bits at a specified rate, and the receiver uses a matched clock to predict where to look for the boundaries of received data bits. As the transmission proceeds, however, the receiver clock will inevitably &#34;drift&#34; relative to the timing of the transmitter clock, impairing the receiver&#39;s tolerance of phase jitter and noise in the received signal. 
     One prior art solution to the problem of drift is to provide the transmitter clock signals to the receiver so that the two clocks may be resynchronized. One conventional technique for doing this is known as &#34;Manchester&#34; encoding of the data bits. According to that technique, the transmitter uses an exclusive OR (XOR) gate to combine the NRZ data bit signals to be communicated (FIG. 1a) with transmitter clock signals (FIG. 1b) which oscillate at twice the data bit transmission frequency. This produces a Manchester encoded data bit stream (FIG. 1c) in which the first half of each bit is the inverse value of the original NRZ data bit value, and the last half is the same value as the NRZ data bit. Any steps at boundaries of the original NRZ data bits are eliminated. However, more importantly, halfway between the boundaries of every Manchester data bit there is a step corresponding to a transmitter clock signal. A &#34;preamble&#34; of alternating NRZ 1&#39;s and 0&#39;s which are Manchester encoded without steps at bit boundaries, (FIG. 1c) is transmitted to enable the receiver to synchronize with and lock onto the transmitter clock signal. The receiver is thus able to distinguish individually received data bits, and to synchronize its internal processes to those of the transmitter without the need for a separately transmitted clock signal. 
     The receiver decodes the Manchester data to recover NRZ data by sampling each received data bit at several points. The receiver clock must be matched within 25% of the transmitter clock to sample for the transmitter clock within 1/4 bit of the transmitted clock edges, or samples will be taken on the wrong side of the mid-bit steps or outside the bit boundaries. With a 10 MHz clock signal, as typically used on Ethernet® local area networks, bits are each 100 nanoseconds (nsec) in duration, so the combined transmitter and receiver tolerance must be ±25 nsec (25% of 100 nsec) to assure accurate decoding. Because bit boundary deviations of 22 nsec are not unusual, the receiver must predict the transmitter clock to within ±3 nsec, and preferably to within ±2 nsec. 
     A conventional Phase Lock Loop (PLL) receiver circuit maintains its synchronization by comparing and adjusting its clock to received clock edges. High speed PLL receivers usually use analog circuitry. In an analog PLL, the received and receiver clock signals are supplied to a comparator which produces a constant voltage output pulse for the duration of the phase difference of the clock signals. The output pulse is integrated to produce a voltage, which is applied to a voltage controlled oscillator (VCO), to produce a phaselocked receiver clock signal. Analog PLL&#39;s have the potential for infinite resolution, but require external precision resistors and capacitors. Furthermore, analog circuits are susceptible to signal noise, which limits their resolution in practical implementations. 
     Digital PLL circuits do not require external precision components. However, the resolution of a digital PLL circuit is limited to its &#34;effective&#34; sampling interval, the minimum interval at which samples may be taken. In a PLL circuit a high speed clock signal increments a counter to a preselected number, and the counter supplies a sample clock pulse to a comparator for comparison with the received clock signals. Conventionally, if the sample clock signals lead, a pulse is dropped from the pulse stream supplied to a counter input terminal, to delay the count. If the sample clock signals lag, an extra pulse is inserted into the counter input stream. 
     This method of operation is undesirable because of the speed with which pulses must be added or subtracted. For example, for a digital PLL to operate by the conventional method within a 2 nsec margin of error desirable for receiving data at 10 MHz, samples would have to be taken at least once per 2 nsec, or at a 500  MHz rate. To insert an extra pulse into the counter input stream, the driver clock would have to operate at twice the sampling rate, 1 GHz, which is a 1 nsec pulse period. The pulses must be less than half of the period, say 0.4 nsec, with rise and fall times of 0.05 nsec each. Because the fastest satisfactory clock signal that can be generated by present technology is about 250 MHz, digital PLL decoding of a 10 MHz signal by conventional techniques cannot be achieved with the needed resolution. There is, therefore, a need for a digital PLL technique to provide an effective sampling interval shorter tha the driver clock period. 
     SUMMARY OF THE INVENTION 
     The present invention uses a driver clock generator which supplies a series of clock signals of different phases, and a clock signal phase selector to attain an effective phase lock resolution equal to the time difference between different phase clock signals from the driver clock. The driver clock has multiple stages, and the time difference between adjacent phases is the driver clock period divided by the number of stages. A selected phase of the driver clock signal increments a counter in a system clock generator to produce a sample clock signal at four times the received bit rate, and to produce a data clock signal at the bit rate. 
     The sample clock causes a shift register to sample received signals at the bit quarter points when the circuit is locked. The sample pattern indicates whether the sample clock needs to catch up or to drop back. If the sample taken at the mid-bit clock edge matches the first quarter sample, the driver clock signal is leading and needs to be retarded by being switched to a lagging phase signal from the driver clock generator. Conversely, if the mid-bit sample matches the third quarter sample, the driver clock signal is lagging and needs to be advanced to a leading phase. A phase selector or commutator makes corrections to the driver clock timing by selecting a leading or lagging output signal of the multi-phase clock generator to replace the phase currently used as the driver clock signal. The phase locked data clock signals are used to reclock the received data bits, which are provided as an output signal. The data clock signals are also provided as a separate output signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows how NRZ data bits may be combined with a transmitter clock to form a Manchester encoded data stream; 
     FIG. 2 is a diagram showing how Manchester encoded data bits are sampled by the invention when the sample clock leads of lags the data bit; 
     FIG. 3 shows how the driver clock oscillator stage output signals are reshaped by flip-flops and how any given driver clock phase signal is preceded and followed at the effective phase lock interval by the phases of the other driver clock signals; 
     FIG. 4 is a block diagram of a decoder according to the present invention; 
     FIG. 5. is a schematic of TTL implementation of the decoder of FIG. 4; and 
     FIG. 6 is a schematic of a an ECL implementation of the decoder. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 4, the digital phase lock loop circuit of the present invention 100 receives Manchester encoded serial data at input terminal 101 and provides a phase locked data clock signal and a decoded NRZ data stream at output terminals 200 and 201, respectively. 
     A driver clock generator 120 generates a high speed driver clock signal from which N clock signals having a predetermined (equally spaced) phase relationship, are provided as φ1, φ2, φ3 (, . . .,φN) at N respective output terminals. These clock signals are shown in FIG. 3. At a given time, a selected one of the different phase clock signals is used as the driver clock signal on line 130, which is applied to system clock generator 140. Generator 140 produces a sample clock signal 144 at four times the received data bit rate and a data clock signal 145 at the data bit rate. Sample clock signal 144 clocks data bit samples into shift register 110. The first (boundary) sample of each bit is not used. The samples at the one-quarter, one-half, and three-quarters points of the data bit are then clocked by data clock 145 into a phase decoder 150. In a pattern of data bit samples taken across an edge, termed a &#34;valid&#34; pattern herein, the first and third samples have opposite values. See FIG. 2. The middle sample agrees with the sample on the side of the clock edge on which it was taken, thereby indicating whether the timing of sample clock 144 needs to be advanced or retarded. Accordingly, phase decoder 150 applies an UP/DOWN signal to line 158 to commutator 160, which switches driver clock signal line 130 from the present clock phase φ to the present leading or lagging phase, as appropriate. 
     The commutator should not, while the circuit is essentially synchronized, jump back and forth between driver clock phases on successive bits in an attempt to lock more precisely than the lock resolution. Similarly, the commutator should not try to track individual bits in a jittery (quavering) data clock signal. To damp such activity, phase decoder 150 also applies a HOLD signal to line 159 when it has applied an UP/DOWN signal calling for an opposite correction on the preceding bit. 
     Because normal phase corrections are only as large as the intentionally fine lock resolution, making a large adjustment would take numerous bits. To converge initially on the received data clock, the invention preferably employs a fast lock circuit 180 rather than making repetitious slight corrections. Whenever phase decoder 150 does not recognize a valid sample pattern, with opposite value first and third bits, it applies a &#34;no carrier&#34; or &#34;invalid code&#34; signal to line 154, causing the frequency of the system clock generator 140 to increase, to preferably double, the sample clock 144 frequency, thereby halving the sample interval. While the circuit is in locked mode, and a carrier is detected, clock generator 140 will produce sample clock 144 pulses at four times the data bit rate. A &#34;no carrier&#34; signal on line 154, however, will cause fast lock circuit 180 to apply a high signal to line 181, putting system clock generator 140 in fast lock mode, when the generator produces sample clock and latch pulses eight times per bit. Referring to FIG. 2, the first valid code (A, B, C) will be recognized when sample C is taken, presumably within one-eighth of a bit after the mid-bit clock edge, and fast lock circuit 180 applies low signals to lines 181 and 182, forcing system clock generator 140 to that point. When bit boundary &#34;D&#34; passes, system clock generator 140 will sample at its normal four-times-per-bit rate. 
     Although phase lock resolution depends upon the driver clock stage delay, multiple phase difference corrections could be made by sampling each bit more often, say six or eight times, to obtain sample patterns indicating not just the direction but also the magnitude of clock deviations. Although an inverting ring oscillator will usually have an odd number of stages in the loop, an extra even numbered stage could be added outside the loop, and if all stages were part of one integrated circuit, their delays would be substantially identical. More sophisticated logic in commutator 160 and sufficient oscillator stages in generator 120 could switch an arbitrary number of stage delays ahead or behind. This would offset the need for fast lock circuit 180. 
     The invention may be implemented using TTL components as shown in FIG. 5. Pin numbers are shown for the suggested components. Driver clock generator 120 comprises a multi-stage inverting oscillator 121 using inverters 122 such as type 74C14 and amplifiers 123 such as type 74C906. The oscillator period is a function of the control voltage on line 124, which is regulated by an analog phase lock loop 125. The analog PLL needs only to lock to a reference frequency 126 from a stable crystal oscillator (not shown), and is not a critical design. The filter components can vary significantly without affecting performance of the invention. Any one of the oscillator output phases, for example θ1, is fed back to analog PLL 125 and divided by 127 such as a type CD4024. The counter 127 output is compared by comparator 128, which may be a type CD4046, to reference frequency 126. Comparator 128 produces a pulse of a width in proportion to the phase difference. The width of the pulse charges capacitor 129, and maintains a voltage on the base of preferably a type P04 transistor 131. Current through the transistor regulates the control voltage 124 supplied to the oscillator 121 stages. 
     Referring also to FIG. 3, a θ1 down step &#34;H&#34; from inverter 122 will cause, after one (inverter+amplifier) stage delay, a θ2 up step &#34;I&#34;, then after the next delay, a θ3 down step &#34;J,&#34; and after another delay a θ1 up step &#34;K.&#34; Thus, the period of θ1 (as well as of θ2 and θ3) is six stage delays. In the oscillator 121 or at the output terminals of flip flop 136, 137, 138, any step, say R&#39;, is paralleled by a step T&#39; one-third of a period later in another phase, and a step P&#39; one-third of a period earlier in the remaining phase. 
     Pulse trains θ1, θ2, and θ3 are buffered by amplifiers 135, preferably type 74C906. The pulse trains are reshaped by Set-Reset flip flops 136, 137, and 138 for which a type CD4044 may be used. Falling edges from each oscillator stage output line θ set a flip flop, and four stages later, reset the same flip flop to produce the θ waveforms as shown in FIG. 3. Thus, the θ signals have a period 4 stage delays high and 2 stage delays low. 
     When power is initially supplied to circuit 100, commutator 160 arbitrarily selects φ2 by default. If all three select lines SEL-1, SEL-2, and SEL-3 are high, AND gate 161 resets flip flops 162 and 164, allowing φ2 to set flip flop 163 high, and its Q output terminal 165 low. If all three select lines are low, NOR gate 166 sets flip flop 163. The commutator flip flops may be type CD4013. 
     Until phase decoder 150 detects a valid sample pattern, it applies a high signal to line 154, causing fast lock circuit 180 to apply a high signal to line 181, and loading counter 141 to a value of seven. On the next driver clock 130 pulse, when counter 141 increments to eight, every counter output pin changes value, and one of these applied to the latch clock 146 line and cycled through fast lock circuit 180 will reset, on the next driver clock 130 pulse, counter 141 to seven again, producing latch clock 146 pulses at eight times the normal rate. 
     When the circuit is locked onto the received data clock using φ2, latch 167 output line SEL-2 is high and lines SEL-1 and SEL-3 are low. Latch 167 is preferably a type 74C173. Each select line is applied to the &#34;D&#34; input, and the corresponding driver clock phase output φ is applied to the clock input, of a respective flip flop 162, 163, or 164. The non-selected flip flops 162 and 164 apply a high Q signal to respective NOR gates 168 and 170, holding the NOR gate outputs low and blocking the φ1 and φ3 signals. Selected flip flop 163 applies a low Q to line 165 to NOR gate 169, allowing the φ2 signal to pass gate 169 inverted, and NOR gate 171 reinverted. The output of NOR gate 171 is the system driver clock on line 130 which drives the commutator itself, and the system clock generator 140, and consequently the input shift register 110 and phase decoder 150. 
     In response to phase decoder UP/DOWN signals on line 158, commutator 160 switches; among phases to advance or retard the driver clock pulses being counted by system clock generator 140. A data bit sample pattern of (0, 1, 1) or (1, 0, 0) (see FIG. 2), in type 74C174 latch 151 makes type 74S288 decoder ROM 152 output UP/DOWN line 158 low, indicating that the sample clock 144 should be advanced. Commutator logic in gates 172, 173 and MUX 174, or in a ROM, determines that for the present phase φ2, the leading phase is φ3. MUX 174 holds pin 9 high, and pin 7 low. These are input to latch 167. Within the half data bit between taking the third quarter sample of one data bit and taking the first quarter sample of the succeeding data bit, ROM decoder 142 applies a signal to &#34;enable φ change&#34; line 143 to enable latch 167 for a phase switch. On the next driver clock 130 edge, say, L&#39;, SEL-2 goes low and SEL-3 goes high. The next rising edge in φ3 is P&#39;, which is applied to flip flop 164, producing a low Q to NOR gate 170 and passing the φ3 clock to commutator output NOR gate 171. Likewise, with SEL-2 line now low, the next φ2 rising edge R&#39; is applied to flip-flop 163 to produce a high Q signal which will block φ2 from passing NOR gate 169. Driver clock 130 has now been switched to a leading phase. The first change to appear in the driver clock signal is falling edge S&#39;. The new rising edge V&#39; counted by counter 141 will be one-third of a period sooner than the edge it replaces, X&#39;. 
     The sequence for switching to a lagging phase is similar. Going from phase φ2 to φ1, SEL-2 goes low and SEL-1 goes high at, say, L&#39;. The flip-flop 162 Q output is clocked low by edge N&#39;, allowing φ1 to pass NOR gate 168. φ2 clocks the flip flop 163 Q output high on edge R&#39;, and φ1 edge Q&#39; causes a low output from NOR gate 171 rather than former edge R&#39;. The new rising edge T&#39; is one stage delay later. 
     Driver clock pulses are counted by counter 141, preferably a type 74C163, which applies a rising edge to sample clock line 144 when the second least significant bit of the counter is set to one on every fourth driver clock pulse. Counter 141 applies a decoder latch-clock rising edge to line 146 when the fourth least significant bit is set to one on every sixteenth driver clock pulse. Counter 141 also applies signals to retiming ROM 142, preferably type 74S288, which produces the &#34;enable φ change&#34; signal 143, and, offset from that, a data retiming pulse 145 for re-timing latch 155. Latch 155 uses driver clock 130 to clock the data clock 145 pulse out. The data clock pulse is output on line 200 and is used to clock the three-quarter bit sample into data latch 156, preferably type CD4013, and onto NRZ data output line 201. 
     The invention as implemented using the TTL components described above and using a 2 KHz reference frequency will have a driver clock frequency in the range of 16 KHz and will decode Manchester data received at 1 KHz. Those skilled in the art may implement the inventive concept in ECL components as shown in FIG. 6, or in a single integrated circuit, to decode Manchester data at 10 MHz. The reference numbers in FIG. 6 denote elements corresponding to equivalent elements labeled by numbers 100 less in FIG. 5. With a 160 MHz driver clock, the driver clock phases φ are 2 nsec apart, and phase lock resolution is 2 nsec. This eliminates the need for a 1 GHz clock that would be required in a prior art circuit of comparable resolution. Furthermore, the shortest pulses in 10 MHz embodiments are 2 nsec, avoiding the present impossibility of producing pulses onefifth that long which would be required by the prior art technique. 
     Details have been disclosed to illustrate the invention in a preferred embodiment of which adaptations and modifications within the spirit and scope of the invention will occur to those skilled in the art. For example, the invention could be adapted to lock onto an NRZ data transmission by sampling for clock edges in start/stop bits while skipping data bits. The scope of the invention is limited only by the following claims.