Abstract:
A device and method for planarizing a film layer device on a silicon wafer. The device has a circular track whose surface faces the track center, a carrier capable of moving along the track and carrying wafers around with their front surfaces facing the center, and a set of heating elements for heating the film layers on the wafers to make them fluid. Utilizing the centrifugal force on the film layer generated by the circular movement and the fluidity of the film layer provided by heating, planarization of the film layer is achieved.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 88110181, filed Jun. 17, 1999, the full disclosure of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a semiconductor manufacturing device and a method. More particularly, the present invention relates to a device and method for planarizing a film layer. 
     2. Description of Related Art 
     As semiconductor manufacturing passes into the deep submicron scale, dimensions of each device shrink. Hence, a higher operating speed for each integrated circuit results. For an integrated circuit with the same device layout, operating speed is closely related to density of the devices. 
     One major problem often encountered in metal plug fabrication, damascene processes or the deposition of a layer of dielectric material between neighboring lines or devices is the gap-filling capability of the material involved. Following the reduction of device dimensions and width of circuit lines, device density increases. In the process of filling the gaps or trenches on a silicon wafer, voids may be formed especially when the gaps or trenches are smaller than 0.1 μm. 
     FIG. 1 is a schematic, cross-sectional view after forming an inter-layer dielectric (ILD) layer over a substrate that has circuit lines thereon in a multi-level metallization process. As shown in FIG. 1, metal lines  110  are formed on a substrate  100  so that there is a gap  120  between two neighboring metal lines  110 . A dielectric layer  130  is formed over the substrate and the metal lines  110 . Due to the poor gap-filling capability of the deposited dielectric material when the dielectric layer  130  is formed, a void  140  is likely to form within the dielectric layer  130  inside the gap region  120 . The void  140  not only can lead to poor insulation, but can also enclose some corrosive chemicals that can corrode the metallic lines  110  and result in circuit problems. In addition, too much topographical height difference H after the deposition of the dielectric layer  130  is likely to affect subsequent photolithographic and etching processes as well. This is because only a highly planar surface can avoid the problems due to light diffusion during exposure so that a clear pattern is transferred. 
     SUMMARY OF THE INVENTION 
     The invention provides a method for planarizing a film layer so that voids are eliminated and topographical height differences are reduced. 
     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for planarizing a film layer. A film layer is deposited over a silicon wafer. The wafer is next placed inside a carrier with a front face of the wafer facing a centrifugal center. The wafer inside the carrier is heated so that the film layer becomes fluid. In the meantime, the wafer is also driven in a circular movement so that the film layer can be planarized. 
     The invention also provides a device for planarizing a film layer in semiconductor manufacturing. The device includes a circular track having a track surface that faces the track center, a carrier that moves along the track carrying silicon wafers around the track center, and a set of heating elements within the carrier and/or the track for heating the film layers on the wafers and making the film layers fluid. 
     According to this invention, silicon wafers having their front surfaces all facing the track center are placed inside the carrier. The carrier then runs on the track, and hence follows a circular path. The wafers are heated while the carrier is in motion so that the film layers on the wafers become fluid. The centrifugal force exerted on the thin films accelerate the movement of the film layer, thus planarizing the film layer and removing any voids therein. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIG. 1 is a schematic, cross-sectional view of a substrate that has circuit lines thereon in a multi-level metallization process and an inter-layer dielectric (ILD) layer thereover; 
     FIGS. 2A and 2B are schematic, cross-sectional views showing the process of planarizing a film layer according to this invention; 
     FIGS. 3A and 3B are sketches showing a device for planarizing a film layer according to one preferred embodiment of this invention; and 
     FIG. 4 is a schematic, cross-sectional view along line IV-IV′ of FIG. 3B showing a set of heating elements for heating silicon wafers. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     FIGS. 2A and 2B are schematic, cross-sectional views showing the process of planarizing a film layer according to this invention. The process of forming an interlayer dielectric (ILD) layer over a substrate that has circuit lines thereon in a multi-level metallization, similar to the one shown in FIG. 1, is used as an illustration. 
     As shown in FIG. 2A, metal lines  210  are formed on a substrate  200 . A dielectric layer  230  is formed over the substrate and the metal lines  210  so that a void  240  is formed in a gap between two neighboring metal lines  210 . When the substrate  200  is heated to a certain temperature, the dielectric layer  230  becomes fluid. In the meantime, if an external pressure F is applied to a top surface of the dielectric layer  230 , the fluid dielectric layer  230  moves in a direction as indicated by a set of arrows f. Due to the downward pressure on the dielectric layer  230 , the dielectric material on a top surface of the metal lines  210  is forced to move sideways down the sidewalls of the metal lines  210 . As the dielectric material moves down towards the gap, the void  240  is forced to move up as indicated by an arrow b. When the void  240  reaches a top surface of the dielectric layer  230 , the void  240  bursts open and disappears. Meanwhile, the dielectric material within the dielectric layer  230  continues to flow until all the voids inside the dielectric layer are removed and a level upper surface is formed as shown in FIG.  2 B. 
     Utilizing the aforementioned theoretical consideration, a device capable of planarizing a film layer on a silicon wafer is designed. FIGS. 3A and 3B are sketches showing a device for planarizing a film layer according to one preferred embodiment of this invention. As shown in FIG. 3A, a circular track  300  having a center O and a radius R that permits a wafer carrier  310  to move along at a velocity v is provided. The wafer carrier  310  can be, for example, a small cart with a set of wheels below for engaging with the track  300 . A magnified view of the area enclosed by a frame  310  in FIG. 3A is shown in FIG.  3 B. FIG. 3B provides a clearer view of the carrier  310  moving at a velocity v using its set of wheels on the track  300 . A stack of wafers  340  is placed inside the carrier  310  in such a way that their front surfaces all face the center O. When the carrier  310  moves in a circle along the track  300 , a relative centrifugal force F′ is exerted on a top surface of the wafer. Magnitude of the relative centrifugal force F′ is given by the following formula: 
     
       
           F′= 1.118×10 −3   R×N   2   ×g   (1); 
       
     
     where F′ is the relative centrifugal force (in g, g is the acceleration due to gravity, which is a value of 9.8 m/s 2 ), R is the radius of the track  300  (in m), N is the number of revolutions around the track  300  per minute (in rpm) and. 
     When the carrier  310  is moving at a suitable velocity v around the track  300 , a relative centrifugal force F′ having a magnitude of between 50 to 100 g can be created. The relative centrifugal force F′ is able to planarize a fluid film layer on a wafer and remove any voids therein. The solid film layer can be converted to a fluid film layer by heating the wafer beyond its fluid transition temperature. Typically, a wafer can be heated up to a temperature of about 800° C. Of course, the temperature to which the wafer is heated depends on wafer processing consideration and fluidity of the film layer demanded. For example, if the film layer is made from aluminum/copper alloy, the alloy will start to melt at a temperature of about 400 to 500° C. when heated under atmospheric pressure. 
     FIG. 4 is a schematic, cross-sectional view along line IV-IV′ of FIG. 3B showing a set of heating elements for heating silicon wafers. The heating elements can be heating coils  350  and  360  that are installed inside the sidewalls of the carrier  310  and/or along the track  300 , respectively. 
     As the relative centrifugal force F′ is increased, effectiveness of the planarization increases so that a film layer may be planarized at a lower temperature or a lower fluidity level. According to formula (1), the relative centrifugal force F′ can also be increased by increasing the revolution speed N of the carrier  310  or increasing the radius R of the track  300 . However, it would be more convenient to increase the revolving speed N instead of physically adjusting the track  300  just to increase the radius R. 
     In summary, the advantages of the invention include: 
     1. The invention is capable of removing any voids inside a film layer on a silicon wafer. 
     2. The invention is capable of reducing the topographical height difference of a film layer. 
     3. The invention is capable of reducing the time needed to planarize a film layer. 
     4. Productivity can be increased by increasing the revolution speed of the carrier so that the centrifugal force is increased and the film layer becomes more fluid. 
     5. Surface planarity of a silicon wafer can be improved to such a level that the topographical height difference from the center of a wafer to its rim is only about 0.02 percentage. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.