Abstract:
An image data decoding method of an image vertical blanking interval (VBI) and device thereof in accordance with the present invention can adjust a run-in clock signal of data lines of teletext to be corresponding to a data phase of teletext data lines. The present invention can accurately decode data of the teletext data lines to avoid a phase bias and an erroneous decoding result. A main technical method to decode the data of the VBI is to extract the data of the teletext data lines to determine corresponding bit logical values of the image data and then to output a decode result and also output a phase adjustment value. The phase adjustment value is used to adjust a read phase value of the extracted image, to feedback and adjust a phase of a sampling clock signal to synchronize a data phase in VBI.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to an image data decoding method of image vertical blanking interval (VBI) and a device to perform the method, and more particularly to an image data decoding method for high-frequency teletext image data of the image vertical blanking interval.  
         [0003]     2. Description of the Related Art  
         [0004]     When processing an image display, VBI (vertical blanking interval) and HBI (horizontal interval) signals are normally reserved without showing. Conventional VBI data types are mainly three types, TeleText, Closed Caption (CC), and Wide Screen Signal (WSS). With reference to  FIG. 5 , every data line of the teletext-type VBI data includes a 2-byte run-in clock signal and a 43-byte data string. With reference to  FIG. 6 , every data line of the CC-type or WSS-type data includes a 1-byte run-in clock signal and a 2-byte data string.  
         [0005]     When processing the VBI data, the VBI data has to be decoded in advance. A decoding method for the teletext-type data is more complicated because the run-in clock signal of the teletext includes a higher frequency than that of the CC or WSS, and also the data volume of the teletext is larger than that of the CC or WSS.  
         [0006]     With reference to  FIG. 7 , a teletext decoder uses a closed phase locked loop (PLL) circuit to lock the run-in clock signal. The closed phase locked loop circuit separates the teletext data lines through a run-in clock signal separator to accurately read the data of the teletext data lines.  
         [0007]     Although the described closed phase locked loop circuit is beneficial to adjust different phases of the data in the teletext data lines, the run-in clock signal of the teletext data lines is only a small part of the data, which does not occur frequently. Moreover, the closed phase locked loop needs to take quite some time to be able to accurately lock the run-in clock signal. Since digital data of the teletext data lines is not continuous, a phase error when decoding the teletext data lines can easily occur by using the closed phase locked loop method to track data over a long term.  
         [0008]     With reference to  FIG. 8 , U.S. Pat. No. 5,657,088 entitled “System and method for extracting caption teletext information from a video signal” uses a threshold value to determine logical values of the data. When the input digital image data exceeds a setup turning point, the logical value is determined to be 1 or 0. On the other hand, when the input digital image data is lower than the setup turning point, the logical value is determined to be 0 or 1.  
         [0009]     Further, a delay time can be set for the current input digital image data, so the digital input data can be determined whether beyond or below a turning point to complete decoding the digital image data. The decoding method in this patent is rather simple and can save space in a layout area of image processing chips. However, the turning point is not easy to change, which tends to cause an erroneous decoding result when the image processing chips process image signals in an inferior signal environment.  
       SUMMARY OF THE INVENTION  
       [0010]     An image data decoding method of an image vertical blanking interval (VBI) and device thereof of the present invention is provided, which can adjust a run-in clock signal of data lines of teletext to be corresponding to a data phase of the data lines of the teletext. Hence the present invention can accurately decode data of the data lines of the teletext to avoid a phase bias and an erroneous decoding result.  
         [0011]     To achieve the above-described objective, a main technical method to decode the data of the VBI of the present invention is to extract the data of the teletext data lines to determine corresponding bit logical values of the image data and then to output a decode result and also output a phase adjustment value. The phase adjustment value is used to adjust a read phase value of the extracted image to feedback and adjust a phase of a sampling clock signal to synchronize a data phase in VBI. Therefore, the present invention can achieve the objective to accurately acquire the data of the teletext data lines without the closed phase locked loop (PLL) or a direct digital frequency synthesizer (DDFS). 
     
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0012]      FIG. 1  is a block diagram of a preferred embodiment of a device to perform an image data decoding method of image vertical blanking interval in accordance with the present invention.  
         [0013]      FIG. 2  is a circuit diagram of an example of a preferred embodiment of a delay circuit of the device in  FIG. 1 .  
         [0014]      FIG. 3  is a circuit diagram of an example of a preferred embodiment of a phase accumulator of the device in  FIG. 1 .  
         [0015]      FIG. 4  shows a timing diagram of a frequency of a phase accumulation signal of the phase accumulator, a wave signal equivalent to a run-in clock signal and a data output signal of the data extractor.  
         [0016]      FIG. 5  is a diagram of a conventional teletext-type VBI data line in accordance with the prior art.  
         [0017]      FIG. 6  is a diagram of either a conventional close caption (CC) data line or a wide screen signal (WSS) data line in accordance with the prior art.  
         [0018]      FIG. 7  is a block diagram of a conventional decoder for a teletext-type VBI data line in accordance with the prior art.  
         [0019]      FIG. 8  is a block diagram of a preferred embodiment of U.S. Pat. No. 5,657,088 entitled “System and method for extracting caption teletext  10  information from a video signal.” 
         [0020]      FIG. 9  is a look-up table for bit sampling lengths of 2N in accordance with the present invention.  
         [0021]      FIG. 10  is a look-up table for bit sampling lengths of 2N+1 in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]     With reference to  FIG. 1 , a preferred embodiment of an image data decoding device for an image vertical blanking interval (VBI) in accordance with the present invention includes an analog-to-digital converter (ADC) ( 10 ), a level adjuster ( 11 ), a delay circuit ( 12 ), a data extractor ( 13 ), a phase accumulator ( 14 ) and a memory ( 15 ).  
         [0023]     The ADC ( 10 ) follows a sampling clock signal to sample and digitize an analog image signal and then to output the digitized image signal. The level adjuster ( 11 ) is coupled to an output terminal of the ADC ( 10 ) to remove a blanking level and a signal carrier of the analog image signal to convert the digitized image signal to an AC (alternating current) signal.  
         [0024]     With further reference to  FIG. 2 , the delay circuit ( 12 ) comprises multiple registers ( 121 ). The delay circuit ( 12 ) is coupled to an output terminal of the level adjuster ( 11 ) for storing digital data of a teletext data line that is regulated by the level adjuster ( 11 ). The data extractor ( 13 ) is coupled to output terminals of the delay circuit ( 12 ) to read a logical value of a most significant bit (MSB) of the digital data of the delay circuit ( 12 ) with a specific sampling clock signal, and then to determine a data bit according to every logical value of the MSB, to output a phase adjustment value.  
         [0025]     The phase accumulator ( 14 ) is coupled to an output terminal of the data extractor ( 13 ) to adjust an accumulated phase based on the phase adjustment value outputted by the data extractor ( 13 ) and to feedback to the data extractor ( 13 ) to compose a closed circuit with the data extractor ( 13 ) to reduce a phase error. The memory ( 15 ) is connected to the data extractor ( 12 ) for storing the decoded bit data (i.e. the VBI) according to every logical value of the MSB.  
         [0026]     With further reference to  FIG. 3 , the phase accumulator ( 14 ) includes a register ( 141 ), an adder ( 142 ) and an adder/substractor ( 143 ) that also can be a second adder. The register ( 141 ) is coupled to its own output terminal and an output terminal of the adder/substractor ( 143 ) by the adder ( 142 ) to compose an accumulation structure. Phase adjustment steps follow. A first input terminal of the adder/substractor ( 143 ) receives the phase adjustment value of the data extractor ( 13 ), and a second input terminal of the adder/substractor ( 143 ) receives a phase constant for a phase accumulation. In this way, the output terminal of the register ( 141 ) can acquire a continuous adjusted accumulated phase.  
         [0027]     An image data decoding method for an image vertical blanking interval (VBI) of the present invention includes steps of converting an input analog image signal to a digital image signal according to a specific sampling timing signal, removing a blanking level of the digital image signal and a DC (direct current) level of a signal carrier by the level adjuster ( 11 ), storing the digital data in the delay circuit ( 12 ) and extracting the MSB data from the registers ( 121 ) of the delay circuit ( 12 ) by the data extractor ( 13 ) to determine its logical values. Thereby multiple sample points can be acquired. If the specific sampling clock signal makes a bit data signal include 2N+1 sample points, then the delay circuit ( 12 ) includes at least 2N+1 registers ( 121 ).  
         [0028]     Since the data extractor ( 13 ) is used to extract the output data of the delay circuit ( 12 ) to decode and determine the bit logical value of the extracted data with the logical value of the most significant bit (MSB) of the registers ( 121 ), the sampling clock signal for the data extractor ( 13 ) must be synchronous with the input signal to ensure an accuracy of a judgment on bit logical values. Thereby the data extractor ( 13 ) decodes the MSB logical value and outputs a corresponding phase adjustment value to the phase accumulator ( 14 ). When the phase accumulator ( 14 ) accumulates to phases of 0° and 180°, a strobe signal is output to the data extractor ( 13 ) to make the data extractor ( 13 ) adjust the phase of the decoded data bit.  
         [0029]     According to the foregoing phase adjustment steps, the data extractor ( 13 ) first reads the sampled bit data that is temporarily stored in the delay circuit ( 12 ). The valid bit data is determined by the temporarily stored MSB logical values of multiple sample points. When all of the sample points are determined with the logical values, the logical values of the bit data are then acquired.  
         [0030]     An example of a determination method follows. Simultaneously, the data extractor ( 13 ) determines the phase adjustment values by the logical values of the sample points and outputs to the phase accumulator ( 14 ). The phase accumulator ( 14 ) can adjust the phases according to the phase adjustment values and also feedback the strobe signal to the data extractor ( 13 ) when reaching some specific phases. Hence, the data extractor ( 13 ) and the phase accumulator ( 14 ) form a closed circuit so the data extractor ( 13 ) provides the phase adjustment values according to the latest input image signal, and the phase accumulator ( 14 ) will dynamically adjust the accumulated phase value to make the data tractor ( 13 ) correctly extract the sample points from the delay circuit ( 12 ) according to the phase adjustment values.  
         [0031]     With further reference to  FIG. 4 , when the phase accumulator ( 14 ) determines the phase equals 180°, a 180°-phase signal is output to the data extractor ( 13 ). Then the data extractor ( 13 ) adjusts the phases of the sampling clock signal extracted from the registers ( 121 ) of the delay circuit ( 12 ). Similarly, when the phase accumulator ( 14 ) determines the phase equals 360°, which means a cycle ends, the phase accumulator ( 14 ) also repeats the aforesaid operation. When the data extractor ( 13 ) extracts one row of temporarily stored sample points in the delay circuit ( 12 ), whether the logical values of the sample points are 1 or 0 are determined. Therefore, the blanking signal contained in the image vertical blanking interval (VBI) can be successfully decoded and output to the memory ( 15 ).  
         [0032]     An actual implementation method of the data extractor ( 13 ) is easily achieved by setting up a look-up table. The look-up table includes the most significant bit extracted from every register ( 121 ) in the delay circuit ( 12 ), phase adjustment values and decoded bit data. The input image data may be changed. Hence when the data extractor ( 13 ) performs sampling, the bit sampling length may be different. With reference to  FIGS. 9 and 10 , the look-up tables show bit sampling lengths of 2N and 2N+1 respectively, as an example.  
         [0033]     The look-up tables show that when the data extractor ( 13 ) determines a decoded bit data, a corresponding phase adjustment value is also generated and sent to the phase accumulator ( 14 ) to adjust the accumulated phase. The data extractor ( 13 ) extracting positive half cycle bit data of the corresponding input image signal negative bit data should have been extracted indicates the phase is not synchronous. Thus the accumulated phase can be adjusted to make the data extractor ( 13 ) adjust the extracted sampling clock signal of the next row of bit data. Moreover, since the input image data may include noise data, if the data extractor extracts an opposite logical value to a sequence of continuous 1 or continuous 0, the opposite logical value can be determined to be the noise data and ignored.  
         [0034]     To conclude, the image data decoding method of the present invention performs a digitizing sampling on an input image signal and converts the digitized image signal into a from of an AC (alternating current) signal. The values of the positive half cycle and the negative half cycle of the AC signal being significantly different provides the basis to the data extractor to determine the decoded bit data and the phase adjustment value. Especially the data extractor and the phase accumulator compose a feedback closed circuit, so that the phase of the sampling clock signal of the data extractor can be adjusted to output accurate decoded bit data. Therefore, the present invention can achieve the objective to accurately acquire the data of the teletext data lines without the closed phase locked loop (PLL) or a direct digital frequency synthesizer (DDFS).  
         [0035]     Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and features of the invention, the disclosure is illustrative only. Changes may be made in the details, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.