Abstract:
There is provided a semiconductor device which has a CMOS inverter circuit and which can accomplish high-integration by configuring an inverter circuit with a columnar structural body. A semiconductor device includes a columnar structural body which is arranged on a substrate and which comprises a p-type silicon, an n-type silicon, and an oxide arranged between the p-type silicon and the n-type silicon and running in the vertical direction to the substrate, n-type high-concentration silicon layers arranged on and below the p-type silicon, p-type high-concentration silicon layers arrange on and below the n-type silicon, an insulator which surrounds the p-type silicon, the n-type silicon, and the oxide, and which serves as a gate insulator, and a conductive body which surrounds the insulator and which serves as a gate electrode.

Description:
RELATED APPLICATIONS 
       [0001]    Pursuant to 35 U.S.C. §119(e), this application claims the benefit of the filing date of Provisional U.S. Patent Application Ser. No. 61/278,204 filed on Oct. 2, 2009. This application also claims priority under 35 U.S.C. §119(a) to JP2009-229591 filed on Oct. 1, 2009. The entire contents of these applications are hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This application relates generally to a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    High-integration of integrated circuits using a semiconductor device, in particular, a MOS (Metal Oxide Semiconductor) transistor which is a field effect transistor having a gate electrode with a MOS structure is advancing. Together with advancement of high-integration, microfabrication of such MOS transistor used in the integrated circuit is progressed in the range of a nano order. When a MOS transistor configures an inverter circuit (NOT circuit) that is one of the basic circuits for digital circuits, if microfabrication of that MOS transistor advances, it becomes difficult to suppress any leak current, and the reliability is deteriorated because of a hot-carrier effect. Moreover, reduction of an occupy area of a circuit is not easily accomplished because of the necessity of ensuring a necessary current amount. In order to overcome such problems, there is proposed a Surrounding Gate Transistor (SGT) having an island semiconductor layer where a source, a gate, and a drain are arranged in the vertical direction relative to a substrate, and employing a structure that the island semiconductor layer is surrounded by a gate, and there are also proposed CMOS inverter circuits using such SGT (see, S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, “A Nobel Circuit Technology with Surrounding Gate Transistors (SGT&#39;s) for Ultra High Density DRAM&#39;s”, IEEE JSSC, Vol. 30, No. 9, 1995.). Size reduction can be accomplished by such CMOS inverter circuit using the SGT, but further size reduction of the CMOS inverter circuits using the SGT is desired. 
         [0006]    The present invention has been made in view of the foregoing circumstances, and it is an object of the present invention to provide a semiconductor device which has a CMOS inverter circuit with an SGT and which accomplishes high-integration. 
       SUMMARY OF THE INVENTION 
       [0007]    A semiconductor device according to a first aspect of the present invention comprises: a columnar structural body which is arranged on a substrate and which includes a first silicon, a second silicon having a different conductivity type from the first silicon, and a first insulator held between the first silicon and the second silicon, which runs in a vertical direction to the substrate; a pair of first upper and lower silicon layers arranged on and below the first silicon so as to sandwich the first silicon, and containing a first high-concentration dopant that has a different conductivity type from the first silicon; a pair of second upper and lower silicon layers arranged on and below the second silicon so as to sandwich the second silicon, and containing a second high-concentration dopant that has a different conductivity type from the second silicon; a second insulator which surrounds respective peripheries of the first silicon, the second silicon, the pair of first upper and lower silicon layers, and the pair of second upper and lower silicon layers, and the first insulator; and a conductive body surrounding a periphery of the second insulator, wherein the silicon layer in the pair of first upper and lower silicon layers arranged on the first silicon is electrically connected to the silicon layer in the pair of second upper and lower silicon layers arranged on the second silicon, and a first power is supplied to the lower silicon layer in the pair of first upper and lower silicon layers, and a second power is supplied to the lower silicon layer in the pair of second upper and lower silicon layers arranged. 
         [0008]    In a preferable mode of the present invention, in the columnar structural body, the first silicon is a p-type or intrinsic silicon, the second silicon is an n-type or intrinsic silicon, and the first insulator is a first oxide film, the pair of first upper and lower silicon layers are each a silicon layer containing an n-type high-concentration dopant, the pair of second upper and lower silicon layers are each a silicon layer containing a p-type high-concentration dopant, and the second insulator and the conductive body serve as a gate insulating film and a gate electrode, respectively. 
         [0009]    In a preferable mode of the present invention, the first silicon and the second silicon are each formed in a quadrangular column shape. 
         [0010]    In a preferable mode of the present invention, a length L 1  of a side of a bottom quadrangle which is of the first silicon formed in a quadrangular column shape and which contacts the first oxide film satisfies a following relational expression 1. 
         [0000]        L   1 &lt;2×√{(2×φ F )×(2×∈silicon)/( q×N   A )}  [Relational Expression 1]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N A  is a dopant concentration of the first silicon. 
         [0011]    In a preferable mode of the present invention, a length L 2  of a side of a bottom quadrangle which is of the first silicon formed in a quadrangular column shape and which is orthogonal to a side contacting the first oxide film satisfies a following relational expression 2. 
         [0000]        L   2 &lt;√{(2×φ F )×(2×∈silicon)/( q×N   A )}  [Relational Expression 2]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N A  is a dopant concentration of the first silicon. 
         [0012]    In a preferable mode of the present invention, a length L 3  of a side of a bottom quadrangle which is of the second silicon formed in a quadrangular column shape and which contacts the first oxide film satisfies a following relational expression 3. 
         [0000]        L   3 &lt;2×√{(2×φ F )×(2×∈silicon)/( q×N   D )}  [Relational Expression 3]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N D  is a dopant concentration of the second silicon. 
         [0013]    In a preferable mode of the present invention, a length L 4  of a side of a bottom quadrangle which is of the second silicon formed in a quadrangular column shape and which is orthogonal to a side contacting the first oxide film satisfies a following relational expression 4. 
         [0000]        L   4 &lt;√{(2×φ F )×(2×∈silicon)/( q×N   D )}  [Relational Expression 4]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N D  is a dopant concentration of the second silicon. 
         [0014]    In a preferable mode of the present invention, the first silicon and the second silicon are each formed in a semicircular column shape. 
         [0015]    In a preferable mode of the present invention, the second insulator serving as a gate insulating film, the conductive body surrounding the periphery of the second insulator and serving as a gate electrode, the first silicon, and the pair of first upper and lower silicon layers configure an enhancement type nMOS transistor, the second insulator serving as a gate insulating film, the conductive body surrounding the periphery of the second insulator and serving as a gate electrode, the second silicon, and the pair of second upper and lower silicon layers configure an enhancement type pMOS transistor, and the conductive body is formed of a material which causes the nMOS transistor and the pMOS transistor to be an enhancement type. 
         [0016]    According to the first aspect of the present invention, it is possible to configure a CMOS inverter circuit by using a columnar structural body, which results in accomplishment of high-integration of the CMOS inverter circuit. 
         [0017]    It is preferable that the first silicon and the second silicon should be each formed in a quadrangular column shape. 
         [0018]    It is preferable that a length L 1  of a side of a bottom quadrangle which is of the first silicon formed in a quadrangular column shape and which contacts the first oxide film should satisfy a following relational expression 1. 
         [0000]        L   1 &lt;2×√{(2×φ F )×(2×∈silicon)/( q×N   A )}  [Relational Expression 1]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N A  is a dopant concentration of the first silicon. 
         [0019]    Accordingly, the p-type or intrinsic silicon which is the first silicon can be depleted, thereby making it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0020]    It is preferable that a length L 2  of a side of a bottom quadrangle which is of the first silicon formed in a quadrangular column shape and which is orthogonal to a side contacting the first oxide film should satisfy a following relational expression 2. 
         [0000]        L   2 &lt;√{(2×φ F )×(2×∈silicon)/( q×N   A )}  [Relational Expression 2]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N A  is a dopant concentration of the first silicon. 
         [0021]    Accordingly, the p-type or intrinsic silicon which is the first silicon can be depleted, thereby making it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0022]    It is preferable that a length L 3  of a side of a bottom quadrangle which is of the second silicon formed in a quadrangular column shape and which contacts the first oxide film should satisfy a following relational expression 3. 
         [0000]        L   3 &lt;2×√{(2×φ F )×(2×∈silicon)/( q×N   D )}  [Relational Expression 3]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N D  is a dopant concentration of the second silicon. 
         [0023]    Accordingly, the n-type or intrinsic silicon that is the second silicon can be depleted, thereby making it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0024]    It is preferable that a length L 4  of a side of a bottom quadrangle which is of the second silicon formed in a quadrangular column shape and which is orthogonal to a side contacting the first oxide film satisfies a following relational expression 4. 
         [0000]        L   4 &lt;√{(2×φ F )×(2×∈silicon)/( q×N   D )}  [Relational Expression 4]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N D  is a dopant concentration of the second silicon. 
         [0025]    Accordingly, the n-type or intrinsic silicon that is the second silicon can be depleted, thereby making it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0026]    Moreover, it is preferable that the first silicon and the second silicon should be each formed in a semicircular column shape. 
         [0027]    Accordingly, a columnar structural body can be formed by using a circular resist, thereby making it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0028]    It is preferable that the second insulator serving as a gate insulating film, the conductive body surrounding the periphery of the second insulator and serving as a gate electrode, the first silicon, and the pair of first upper and lower silicon layers should configure an enhancement type nMOS transistor, the second insulator serving as a gate insulating film, the conductive body surrounding the periphery of the second insulator and serving as a gate electrode, the second silicon, and the pair of second upper and lower silicon layers should configure an enhancement type pMOS transistor, and the conductive body should be formed of a material which causes the nMOS transistor and the pMOS transistor to be an enhancement type. 
         [0029]    Accordingly, both pMOS transistor and nMOS transistor are allowed to be an enhancement type. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]    A more complete understanding of this application can be obtained when the following detailed description is considered in conjunction with the following drawings, in which: 
           [0031]      FIG. 1  shows a semiconductor device according to one embodiment of the present invention, wherein (a), (b) and (c) are a schematic diagram of the semiconductor device in a plane view, taken along the line X-X′ in (a) and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0032]      FIG. 2  shows a step in one example of a manufacturing process for the semiconductor device according to the embodiment, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0033]      FIG. 3  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0034]      FIG. 4  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0035]      FIG. 5  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0036]      FIG. 6  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0037]      FIG. 7  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0038]      FIG. 8  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0039]      FIG. 9  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0040]      FIG. 10  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0041]      FIG. 11  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0042]      FIG. 12  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0043]      FIG. 13  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0044]      FIG. 14  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0045]      FIG. 15  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0046]      FIG. 16  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0047]      FIG. 17  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0048]      FIG. 18  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0049]      FIG. 19  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0050]      FIG. 20  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0051]      FIG. 21  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0052]      FIG. 22  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0053]      FIG. 23  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0054]      FIG. 24  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0055]      FIG. 25  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0056]      FIG. 26  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0057]      FIG. 27  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0058]      FIG. 28  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0059]      FIG. 29  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0060]      FIG. 30  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0061]      FIG. 31  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0062]      FIG. 32  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0063]      FIG. 33  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0064]      FIG. 34  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0065]      FIG. 35  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0066]      FIG. 36  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0067]      FIG. 37  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0068]      FIG. 38  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0069]      FIG. 39  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0070]      FIG. 40  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0071]      FIG. 41  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0072]      FIG. 42  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0073]      FIG. 43  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0074]      FIG. 44  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0075]      FIG. 45  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0076]      FIG. 46  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0077]      FIG. 47  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0078]      FIG. 48  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0079]      FIG. 49  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0080]      FIG. 50  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0081]      FIG. 51  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0082]      FIG. 52  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0083]      FIG. 53  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0084]      FIG. 54  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0085]      FIG. 55  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0086]      FIG. 56  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0087]      FIG. 57  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0088]      FIG. 58  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0089]      FIG. 59  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0090]      FIG. 60  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0091]      FIG. 61  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0092]      FIG. 62  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0093]      FIG. 63  shows a step in the example of the manufacturing process, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
           [0094]      FIG. 64  shows a plan view showing a semiconductor device according to a modified example of the embodiment of the preset invention, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0095]    An explanation will be given of a semiconductor device and a manufacturing method of same according to an embodiment of the present invention with reference to the accompanying drawings. 
         [0096]      FIG. 1  shows a semiconductor device according to one embodiment of the present invention, wherein (a), (b) and (c) are a schematic diagram of the semiconductor device in a plane view, taken along the line X-X′ in (a) and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
         [0097]    As shown in  FIG. 1 , a semiconductor device of the present embodiment has a CMOS inverter circuit (a MOS transistor), and has a columnar structural body configuring a MOS transistor which is arranged on a substrate (not shown) and which includes a p-type or intrinsic silicon  102 , an n-type or intrinsic silicon  104 , and a first oxide film  116  held between the silicon  102  and the silicon  104 , which runs in the vertical direction to the substrate. 
         [0098]    The semiconductor device of the present embodiment further includes a pair of upper and lower silicon layers  134 ,  122  which are arranged up and down so as to sandwich the p-type or intrinsic silicon  102  therebetween, and which contain n-type high-concentration dopants, a pair of upper and lower silicon layers  136 ,  124  which are arranged up and down so as to sandwich the n-type or intrinsic silicon  104  therebetween and which contain p-type high-concentration dopant, a gate insulating film  127  surrounding respective peripheries of the p-type or intrinsic silicon  102  and the n-type or intrinsic silicon  104 , and a gate electrode  128  surrounding the periphery of the gate insulating film  127 . 
         [0099]    According to the semiconductor device of the present embodiment, the silicon layer  134  and the silicon layer  136  are electrically connected together. A first power is supplied to the silicon layer  122 , while a second power is supplied to the silicon layer  124 . 
         [0100]    According to the semiconductor device of the present embodiment, a metal/silicon compound  138  is formed on the silicon layer  134  containing n-type high-concentration dopants, a metal/silicon compound  137  is formed on the silicon layer  122  containing n-type high-concentration dopants, a metal/silicon compound  139  is formed on the silicon layer  136  containing p-type high-concentration dopants, and a metal/silicon compound  140  is formed on the silicon layer  124  containing p-type high-concentration dopants. 
         [0101]    As shown in  FIG. 1 , a contact  148  is formed on the metal/silicon compound  138  and on the metal/silicon compound  139 , and electrically connects the compounds  138 ,  139  together. 
         [0102]    Moreover, a contact  147  is formed on the metal/silicon compound  137 , a contact  149  is formed on the metal/silicon compound  140 , and a contact  150  is formed on the gate electrode  128 . 
         [0103]    A first metal  151  is formed on the contact  147 , and the first power is supplied to the contact  147  through the first metal  151 . A first metal  153  is formed on the contact  149 , and the second power is supplied to the contact  149  through the first metal  153 . 
         [0104]    Moreover, a first metal  152  and a first metal  154  are formed on the contact  148  and the contact  150 , respectively. 
         [0105]    The p-type or intrinsic silicon  102  and the n-type or intrinsic silicon  104  are each formed in a quadrangular column shape. Accordingly, the columnar structural body of the semiconductor device of the present embodiment can be formed by using a resist in a quadrangular shape in a planar view. 
         [0106]    It is preferable that a length L 1  of a side of a bottom quadrangle which is of the p-type or intrinsic silicon  102  formed in a quadrangular column shape and which contacts the first oxide film  116  should satisfy a following relational expression 1. 
         [0000]        L   1 &lt;2×√{(2×φ F )×(2×∈silicon)/( q×N   A )}  [Relational Expression 1]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N A  is a dopant concentration of the silicon  102   
         [0107]    Accordingly, the p-type or intrinsic silicon  102  can be depleted, which makes it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0108]    It is preferable that a length L 2  of a side of a bottom quadrangle which is of the p-type or intrinsic silicon  102  formed in a quadrangular column shape and which is orthogonal to a side contacting the first oxide film  116  should satisfy a following relational expression 2. 
         [0000]        L   2 &lt;√{(2×φ F )×(2×∈silicon)/( q×N   A )}  [Relational Expression 2]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N A  is a dopant concentration of the silicon  102 . 
         [0109]    Accordingly, the p-type or intrinsic silicon  102  can be depleted, which makes it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0110]    It is preferable that a length L 3  of a side of a bottom quadrangle which is of the n-type or intrinsic silicon  104  formed in a quadrangular column shape and which contacts the first oxide film  116  should satisfy a following relational expression 3. 
         [0000]        L   3 &lt;2×√{(2×φ F )×(2×∈silicon)/( q×N   D )}  [Relational Expression 3]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N D  is a dopant concentration of the silicon  104 . 
         [0111]    Accordingly, the n-type or intrinsic silicon  104  can be depleted, which makes it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0112]    Furthermore, it is preferable that a length L 4  of a side of a bottom quadrangle which is of the n-type or intrinsic silicon  104  formed in a quadrangular column shape and which is orthogonal to a side contacting the first oxide film  116  should satisfy a following relational expression 4. 
         [0000]        L   4 &lt;√{(2×φ F )×(2×∈silicon)/( q×N   D )}  [Relational Expression 4]
 
         [0000]    where φ F  is a Fermi potential, ∈silicon is a dielectric constant of silicon, q is a charge amount of electron, and N D  is a dopant concentration of the silicon  104 . 
         [0113]    Accordingly, the n-type or intrinsic silicon  104  can be depleted, which makes it possible to provide the semiconductor device having a highly integrated and fast CMOS inverter circuit. 
         [0114]    An explanation will now be given of an example of the manufacturing process of the semiconductor device according to the present embodiment with reference to  FIGS. 2 to 63 . Note that the same structural element will be denoted by the same reference numeral in these figures. In  FIGS. 2 to 63 , all A-figures are plan views for explaining the manufacturing process of the semiconductor device of the present embodiment, all B-figures are cross-sectional views along a line X-X′, and all C-figures are cross-sectional views along a line Y-Y′. 
         [0115]    With reference to  FIG. 2 , a resist  103  for forming an n-type silicon is formed on a predetermined area of the p-type or intrinsic silicon  102  formed on an oxide film  101 . If the silicon  102  is intrinsic, this step is unnecessary. 
         [0116]    With reference to  FIG. 3 , the n-type or intrinsic silicon  104  is formed by introducing dopants like phosphorous into a predetermined area of the silicon  102  by using the resist  103  as a mask. If the silicon  104  is intrinsic, this step is unnecessary. 
         [0117]    With reference to  FIG. 4 , the resist  103  is peeled. 
         [0118]    With reference to  FIG. 5 , an oxide film  105  and a nitride film  106  are deposited in this order on the silicon layers  102 ,  104 . 
         [0119]    With reference to  FIG. 6 , resists  107 ,  108  for etching the nitride film  106  are formed on a predetermined area of the nitride film  106 . 
         [0120]    With reference to  FIG. 7 , the nitride film  106  and the oxide film  105  are etched by using the resists  107 ,  108  as masks, thereby separating those films into nitride films  109 ,  110  and oxide films  111 ,  112 , respectively. 
         [0121]    With reference to  FIG. 8 , the resists  107 ,  108  are peeled. 
         [0122]    With reference to  FIG. 9 , a nitride film  113  is deposited on the silicon layers  102 ,  104  so as to cover the nitride films  109 ,  110  and the oxide films  111 ,  112 . A recess for forming nitride-film sidewalls  114 ,  115  is formed at a predetermined portion of the nitride film  113 . 
         [0123]    With reference to  FIG. 10 , the nitride film  113  is subjected to etch-back up to a predetermined depth, thereby forming the nitride-film sidewalls  114 ,  115  between the nitride films  109 ,  110  and between the oxide films  111 ,  112 . 
         [0124]    With reference to  FIG. 11 , the silicones  102 ,  104  are etched by using the nitride-film sidewalls  114 ,  115  as masks to form a groove reaching the oxide film  101 . 
         [0125]    With reference to  FIG. 12 , the first oxide film  116  is deposited in the groove and planarized by CMP (Chemical Mechanical Polishing). 
         [0126]    With reference to  FIG. 13 , a nitride film  117  is deposited on the plane. 
         [0127]    With reference to  FIG. 14 , a quadrangular resist  118  for forming a columnar structural body which will configure a MOS transistor is formed on a predetermined position of the nitride film  117 . 
         [0128]    With reference to  FIG. 15 , the nitride films  117 ,  109  are etched by using the resist  118  as a mask. At this time, the oxide films  111 ,  112  and respective pieces of the nitride-film sidewalls  114 ,  115  are left on the silicon layers  102 ,  104 . 
         [0129]    With reference to  FIG. 16 , the oxide films  111 ,  112  on the silicon layers  102 ,  104  are etched and eliminated. 
         [0130]    With reference to  FIG. 17 , the resist  118  is peeled. 
         [0131]    With reference to  FIG. 18 , the silicon layers  102 ,  104  are etched so as to be left on the oxide film  101  with a predetermined thickness, thereby forming a column having the silicon layers  102 ,  104 . 
         [0132]    With reference to  FIG. 19 , an oxide film  119  is deposited so as to thinly cover the surface of the structural body including the column with the silicon layers  102 ,  104  at a uniform thickness. 
         [0133]    With reference to  FIG. 20 , the oxide film  119  is etched so as to be left in a sidewall-like shape at side walls of the column having the silicon layers  102 ,  104 . 
         [0134]    With reference to  FIG. 21 , a resist  120  for element isolation is formed on the silicon layers  102 ,  104  so as to cover the column having the silicon layers  102 ,  104 . 
         [0135]    With reference to  FIG. 22 , the silicon layers  102 ,  104  are etched by using the resist  120  as a mask to carry out element isolation over the oxide film  101 . 
         [0136]    With reference to  FIG. 23 , the resist  120  is peeled. 
         [0137]    With reference to  FIG. 24 , a resist  121  for introducing dopants over the oxide film  101  is formed so as to cover the right part of the column having the silicon layers  102 ,  104  and the silicon layer  104 . 
         [0138]    With reference to  FIG. 25 , dopants like phosphorous are doped in the silicon layer  102  by using the resist  121  as a mask, and the silicon layer  122  containing n-type high-concentration dopants is formed at the left part of the column having the silicon layers  102 ,  104 . 
         [0139]    With reference to  FIG. 26 , the resist  121  is peeled. 
         [0140]    With reference to  FIG. 27 , a resist  123  for introducing dopants over the oxide film  101  is formed so as to cover the left part of the column having the silicon layers  102 ,  104  and the silicon layer  122 . 
         [0141]    With reference to  FIG. 28 , dopants like arsenic are doped in the silicon layer  104  by using the resist  123  as a mask, and the silicon layer  124  containing p-type high-concentration dopants is formed at the right part of the column having the silicon layers  102 ,  104 . 
         [0142]    With reference to  FIG. 29 , the resist  123  is peeled. 
         [0143]    With reference to  FIG. 30 , the oxide film  119  formed at the side wall of the column having the silicon layers  102 ,  104  is etched and eliminated. 
         [0144]    With reference to  FIG. 31 , an oxide film  125  is deposited over the oxide film  101  so as to cover the column having the silicon layers  102 ,  104  and the silicon layers  122 ,  124 . 
         [0145]    With reference to  FIG. 32 , the oxide film  125  is subjected to etch-back up to a predetermined depth. At this time, an oxide film  126  is caused to be left on the nitride film  117 . 
         [0146]    With reference to  FIG. 33 , a high-dielectric film  127  which will be the gate insulating film is thinly deposited on the oxide film  125  so as to cover the column having the silicon layers  102 ,  104  and the silicon layers  122 ,  124 , and, the metal  128  which will be the gate electrode is deposited and planarized by CMP. In planarization, the oxide film  126  is etched and eliminated. 
         [0147]    The gate insulating film  127  functions as a gate insulating film in both pMOS transistor and nMOS transistor each of which is an enhancement type in the semiconductor device of the present embodiment. Moreover, the gate electrode  128  is a gate electrode formed of a conducting material that allows each of the nMOS transistor and the pMOS transistor to be an enhancement type. Examples of such conducting material for forming the gate electrode are titanium, titanium nitride, tantalum, and tantalum nitride. 
         [0148]    With reference to  FIG. 34 , the metal  128  around the column having the silicon layers  102 ,  104  is subjected to etch-back up to a predetermined depth. 
         [0149]    With reference to  FIG. 35 , an oxide film  129  is deposited on the metal  128  so as to surround the periphery of the column having the silicon layers  102 ,  104  and planarized by CMP. 
         [0150]    With reference to  FIG. 36 , the oxide film  129  around the column having the silicon layers  102 ,  104  is subjected to etch-back up to a predetermined depth. 
         [0151]    With reference to  FIG. 37 , a nitride film  130  with a predetermined thickness is deposited so that the nitride film  117  on the column having the silicon layers  102 ,  104  is completely covered. 
         [0152]    With reference to  FIG. 38 , the nitride film  130  is etched so as to be left in a sidewall-like shape at the sidewall of the high-dielectric film  127  around the nitride-film sidewalls  114 ,  115  and the nitride film  117 . 
         [0153]    With reference to  FIG. 39 , a resist  131  for forming a gate is formed at a predetermined position on the nitride film  117  and on the oxide film  129 . 
         [0154]    With reference to  FIG. 40 , the oxide film  129  is etched by using the resist  131  as a mask so as to be left in a sidewall-like shape at the sidewall of the high-dielectric film  127  around the column having the silicon layers  102 ,  104  and around the nitride film  117 . 
         [0155]    With reference to  FIG. 41 , the metal  128  is etched by using the nitride film  130  as a mask to form a gate electrode surrounding the side wall of the high-dielectric film  127  around the column having the silicon layers  102 ,  104 . 
         [0156]    With reference to  FIG. 42 , the resist  131  is peeled. 
         [0157]    With reference to  FIG. 43 , an oxide film  132  is deposited so as to cover the surface of the structural body with a uniform thickness. 
         [0158]    With reference to  FIG. 44 , the oxide film  132  is etched so as to be left in a sidewall-like shape around the column having the silicon layers  102 ,  104 . 
         [0159]    With reference to  FIG. 45 , the high-dielectric film  127  is etched so as to allow only the high-dielectric film  127  under the oxide film  132  to be left. 
         [0160]    With reference to  FIG. 46 , the nitride films  130 ,  117 ,  114 , and  115  are all etched and eliminated. 
         [0161]    With reference to  FIG. 47 , the high-dielectric film  127  is etched and eliminated up to respective heights of the silicon layers  102 ,  104 . 
         [0162]    With reference to  FIG. 48 , the oxide film  125  exposed outwardly of the oxide film  132  is etched to make the silicon layer  122  containing n-type high-concentration dopants and the silicon layer  124  containing p-type high-concentration dopants exposed. 
         [0163]    With reference to  FIG. 49 , a resist  133  for introducing dopants over the oxide film  101  is formed so as to cover the right part of the column having the silicon layers  102 ,  104  and the silicon layer  124 . 
         [0164]    With reference to  FIG. 50 , dopants like phosphorus are doped in the surface part of the silicon layer  122  by using the resist  133  as a mask and the silicon layer  134  containing n-type high-concentration dopants is formed. 
         [0165]    With reference to  FIG. 51 , the resist  133  is peeled. 
         [0166]    With reference to  FIG. 52 , a resist  135  for introducing dopants over the oxide film  101  is formed so as to cover the left part of the column having the silicon layers  102 ,  104  and the silicon layer  122 . 
         [0167]    With reference to  FIG. 53 , dopants like arsenic are doped in the surface part of the silicon layer  104  by using the resist  135  as a mask, and the silicon layer  136  containing p-type high-concentration dopants is formed. 
         [0168]    With reference to  FIG. 54 , the resist  135  is peeled. 
         [0169]    With reference to  FIG. 55 , the metal/silicon compounds  137 ,  138 ,  139 , and  140  are formed at respective surface parts of the silicon layers  122 ,  134 ,  136 , and  124 . An example of such a metal usable is Ni (nickel) or Co (cobalt), and the compound layer is formed by, for example, depositing a nickel film on a silicon, and by performing a heat treatment thereon to form an Ni silicide film on the silicon surface. 
         [0170]    With reference to  FIG. 56 , a nitride film  141  is deposited on the structural body with a uniform thickness, and an oxide film  142  is also deposited thereon and planarized. 
         [0171]    With reference to  FIG. 57 , contact holes  143 ,  144  reaching the nitride film  141  on the metal/silicon compounds  137 ,  140  are formed. 
         [0172]    With reference to  FIG. 58 , a contact hole  145  reaching the nitride film  141  on the metal/silicon compounds  138 ,  139  is formed. 
         [0173]    With reference to  FIG. 59 , a contact hole  146  is formed in a predetermined portion of the oxide film  142  so as to reach the oxide film  129 . 
         [0174]    With reference to  FIG. 60 , the nitride film  141  at respective bottom faces of the contact holes  143 ,  144 ,  145 , and  146  is etched to make respective metal/silicon compounds  137 ,  140 ,  138 , and  139 , and a part of the oxide film  129  exposed. 
         [0175]    With reference to  FIG. 61 , the oxide film  129  in the contact hole  146  is etched to make the gate electrode  128  exposed. 
         [0176]    With reference to  FIG. 62 , the contacts  147 ,  148 ,  149 , and  150  are formed by burring metallic materials in the contact holes  143 ,  144 ,  145 , and  146 , respectively. 
         [0177]    Finally, with reference to  FIG. 63 , the first metals  151 ,  152 ,  153 , and  154  are formed on the contacts  147 ,  148 ,  149 , and  150 , respectively. 
         [0178]    In the foregoing embodiment, the p-type or intrinsic silicon  102  and the n-type or intrinsic silicon  104  are both in a quadrangular column shape, but as shown in  FIG. 64 , may be both in a semicircular column shape.  FIG. 64  shows a plan view showing a semiconductor device according to a modified example of the embodiment of the preset invention, wherein (a), (b) and (c) are a top plan view, a cross-sectional view taken along the line X-X′ in (a), and a cross-sectional view taken along the line Y-Y′ in (a), respectively. 
         [0179]    The semiconductor device of the modified example has a MOS inverter circuit (a MOS transistor), and comprises a columnar structural body configuring a MOS transistor which is arranged on a substrate (not shown) and which includes a p-type or intrinsic silicon  202 , an n-type or intrinsic silicon  204 , and a first oxide film  216  held between the silicon  202  and the silicon  204  and running in a vertical direction to the substrate. 
         [0180]    The semiconductor device of the modified example includes a pair of upper and lower silicon layers  234 ,  222  which are arranged up and down so as to sandwich the p-type or intrinsic silicon  202  therebetween, and which contain n-type high-concentration dopants, a pair of upper and lower silicon layers  236 ,  224  which are arranged up and down so as to sandwich the n-type or intrinsic silicon  204  therebetween and which contain p-type high-concentration dopant, a gate insulating film  227  surrounding respective peripheries of the p-type or intrinsic silicon  202 , the n-type or intrinsic silicon  204 , and the pair of upper and lower silicon layers  234 ,  222 , and a gate electrode  228  surrounding the periphery of the gate insulating film  227 . 
         [0181]    According to the semiconductor device of the modified example, the silicon layer  234  and the silicon layer  236  are electrically connected together. A first power is supplied to the silicon layer  222 , while a second power is supplied to the silicon layer  224 . 
         [0182]    According to the semiconductor device of the modified example, a metal/silicon compound  238  is formed on the silicon layer  234  containing n-type high-concentration dopants, a metal/silicon compound  237  is formed on the silicon layer  222  containing n-type high-concentration dopants, a metal/silicon compound  239  is formed on the silicon layer  236  containing p-type high-concentration dopants, and a metal/silicon compound  240  is formed on the silicon layer  224  containing p-type high-concentration dopants. 
         [0183]    As shown in  FIG. 64 , a contact  248  is formed on the metal/silicon compound  238  and on the metal/silicon compound  239 , and electrically connects the compounds  238 ,  239  together. 
         [0184]    Moreover, a contact  247  is formed on the metal/silicon compound  237 , a contact  249  is formed on the metal/silicon compound  240 , and a contact  250  is formed on the gate electrode  228 . 
         [0185]    A first metal  251  is formed on the contact  247 , and the first power is supplied to the contact  247  through the first metal  251 . A first metal  253  is formed on the contact  249 , and the second power is supplied to the contact  249  through the first metal  253 . 
         [0186]    Moreover, a first metal  252  and a first metal  254  are formed on the contact  248  and the contact  250 , respectively. 
         [0187]    The present invention is not limited to the foregoing embodiment and example, and can be changed and modified in various forms without departing from the scope and the spirit of the present invention. The device structure is merely an example, and can be changed and modified as needed. 
         [0188]    Having described and illustrated the principles of this application by reference to one or more preferred embodiments, it should be apparent that the preferred embodiments may be modified in arrangement and detail without departing from the principles disclosed herein and that it is intended that the application be construed as including all such modifications and variations insofar as they come within the spirit and scope of the subject matter disclosed herein.