Abstract:
A photoelement for an image sensor is described which does not require a charge-to-voltage conversion, but instead outputs a voltage directly related to the intensity of the light impinging on the photoelement. In one embodiment, only parasitic capacitance is used for the integrating function. A transistor connected in a source follower configuration couples the parasitic capacitance to a read transistor. The source follower shields the integrating capacitance from any other parasitic capacitances not intended to be part of the integrating capacitance, thus making the output of the photoelement highly accurate with high gain.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to image sensors for converting an optical image into electrical signals and, in particular, to a pixel element in such a sensor.  
         BACKGROUND  
         [0002]    One common type of image sensor, commonly found in digital and video cameras, includes an array of photoelements, where each photoelement generates a signal approximately proportional to the light impinging upon the photoelement area. As shown in FIG. 1, such a photoelement array  10  outputs its signals, typically pursuant to an addressing operation, to an analog-to-digital converter  12  to produce digital signals. Processing circuitry  14  then performs the required processing of the digital data to, for example, display the image on a screen or store the image in a memory.  
           [0003]    [0003]FIG. 2 illustrates one photoelement  20  (or pixel element) in the photoelement array  10  and serves to illustrate a common drawback of photoelements. The circuit of FIG. 1 is described in detail in U.S. Pat. No. 6,037,643, assigned to Hewlett-Packard Company and Agilent Technologies. A similar circuit is described in U.S. Pat. No. 5,769,384, also assigned to Hewlett-Packard Company and Agilent Technologies.  
           [0004]    Typically photoelements, such as shown in FIG. 2, generate a charge on an integrating capacitor  22  proportional to the light impinging upon the photoelement and the time the shutter is open (i.e., the integration time). The charge is converted to a voltage outside of the photoelement during a reading cycle. The voltage output is then applied to an analog-to-digital converter, as shown in FIG. 1.  
           [0005]    In FIG. 2, a bias current is set up by a bias signal PBB controlling a transistor  24 . Transistors  26  and  28  form a bias point amplifier for setting the base bias of a phototransistor  30  at a fixed level with respect to its emitter. Transistors  26  and  28  operate as a negative feedback loop, wherein an increased emitter voltage pulls up the gate of transistor  26 , which causes transistor  28 , connected as a source follower, to lower the emitter voltage. Transistor  28  also provides isolation of the phototransistor  30  emitter from fluctuations at node  32 .  
           [0006]    In operation, the integrating capacitor  22  is assumed to be initially charged to a reset voltage by coupling the capacitor to the summing node of the transfer amplifier  44  while read transistor  36  is on. A shutter signal is high during the initial charging of capacitor  22  so that the shutter transistor  38  is off and transistor  40  is on. Transistor  40 , when on, provides a path for phototransistor  30  to draw current from the power supply.  
           [0007]    When the shutter signal goes low, transistor  40  is turned off and transistor  38  is turned on, discharging capacitor  22  through phototransistor  30  at a rate depending on the light impinging on the base of phototransistor  30 . At the end of the shutter period (e.g., 20 microseconds), the shutter signal goes high, decoupling phototransistor  30  from capacitor  22 . Since the rate of discharge of capacitor  22  during the shutter period is approximately proportional to the light incident upon the phototransistor  30 , the charge on capacitor  22  after the shutter is closed now reflects the integral of the light intensity during the time that the shutter was open.  
           [0008]    A read signal NRD then goes low to couple capacitor  22  to an output line  34  and to the input of a transfer amplifier  44 . Transfer amplifier  44  converts the charge on capacitor  22  to a voltage signal. The transfer amplifier  44  pulls the output line  34  up to Vref (basically a reset level of capacitor  22 ), resulting in the charge that was removed from capacitor  22  by the light-induced current during the shutter open time being transferred to a transfer capacitor  48 . The read signal is now raised to turn off transistor  36 .  
           [0009]    The output of the transfer amplifier  44  now corresponds to the amount of light that impinged on phototransistor  30  while the shutter was open. This voltage is processed as shown in FIG. 1 for that particular pixel position. The output line  34  may be connected to all pixel elements in a column, where only one row of photoelements is addressed at a time by the NRD line being common to a row of pixels.  
           [0010]    One problem with such image sensors that convert a charge on an integrating capacitor internal to the pixel area to a voltage outside the pixel area is that the transfer capacitor  48  and integrating capacitor  22  must be fairly large to prevent the capacitors&#39; signals from being significantly distorted by stray capacitances that are coupled to the transfer capacitor  48 , the integrating capacitor  22 , or any of the interconnects between the two when the read transistor  36  is turned on. Further, the additional charge-to-voltage conversion circuitry takes up chip area.  
           [0011]    Accordingly, the design of the pixel element is relatively inflexible, and its sensitivity (ability to produce large signals in low light conditions) is limited due to the required size of the transfer capacitor  48 . The size of the transfer capacitor  48  has an inverse relationship to both the settling time of the transfer amplifier  44  and the substrate noise coupling into the signal. This means that as the transfer capacitor is made smaller to increase the sensitivity of the photodetector, the settling time and noise get worse.  
           [0012]    What is needed is a photoelement that does not suffer from the drawbacks of the prior art.  
         SUMMARY  
         [0013]    A photoelement (or pixel element) for an image sensor is described that does not require a charge-to-voltage conversion, but instead outputs a voltage directly related to the intensity of the light impinging on the photoelement. Hence, a relatively large integrating capacitor is not needed. In one embodiment, only parasitic capacitance is used for the integrating function. Additional capacitance may be added to control the gain of the photoelement.  
           [0014]    The integrating capacitance is initially charged to a reset voltage. A shutter signal closes a switch that couples the capacitance to a phototransistor or photodiode to discharge the capacitance. The switch is opened after the shutter period so that the remaining charge corresponds to the integral of the light that impinged on the photoelement during the shutter period.  
           [0015]    An MOS transistor, connected in a source follower configuration, has its gate connected to the integrating capacitance and its source coupled to an MOS read transistor. The read transistor is also connected to an output pin of the photoelement. When the read transistor is turned on, the voltage at the source of the source follower is applied to the output pin. There is no external charge-to-voltage transfer circuitry used.  
           [0016]    The source follower shields the integrating capacitance from any other parasitic capacitances not intended to be part of the integrating capacitance, thus making the output of the photoelement highly accurate with high gain. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 shows functional blocks of a conventional image sensor circuit.  
         [0018]    [0018]FIG. 2 is one type of pixel element circuit using a charge-to-voltage converter.  
         [0019]    [0019]FIG. 3 is a circuit in accordance with one embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0020]    [0020]FIG. 3 illustrates a single photoelement  50  in an image sensor array of photoelements. A controller  52  (outside of the photoelement) controls the various signals, such as shutter, read, and reset, to the various photoelements in the array in a conventional manner, and such detail need not be supplied. The photoelements are typically arranged in a two dimensional array, and the elements are addressed by row and column in a typical application.  
         [0021]    A phototransistor  60  and biasing network comprising transistors  64 ,  66 , and  68  may be similar to those shown in FIG. 2. A bias signal is applied to pin  70 , which sets up a bias condition between transistors  64 ,  66  and  68  to maintain a stable base-to-collector voltage across phototransistor  60 . Transistor  64  also provides shielding of node  72  from phototransistor  60 .  
         [0022]    Likewise, a photodiode could be used in place of the phototransistor with the cathode of the diode connected to the source of transistor  64  and its anode connected to ground. Transistor  64  acts as a buffering device so the voltage on the reversed bias capacitance of the diode does not change when the voltage on line  85  changes. If the cathode voltage were allowed to change, the change would result in stealing signal charge away from the generated signal current.  
         [0023]    In operation, a low reset pulse on pin  72  turns on transistor  74  to couple the power supply voltage VDD to line  76 . The low reset pulse is also applied to an inverter formed by transistors  78  and  80  so as to invert the reset signal. This inverted reset signal is applied to a gate of PMOS transistor  82 , which acts as a charge compensator to absorb the charge spike generated by later switching off transistor  74 . The source and drain of transistor  82  are shorted together.  
         [0024]    During this initial charging time, a shutter signal applied to pin  83  is low, causing the PMOS shutter transistor  84  to be on. Shutter transistor  84  couples line  85  to line  86 . Thus, VDD charges the parasitic capacitance on lines  76 ,  85  and  86  during the reset period.  
         [0025]    The shutter signal is also inverted by transistors  87  and  88  so as to generate an inverted reset signal on line  90 . This inverted reset signal is coupled the gates of PMOS transistors  92  and  94 , which act as charge compensators to absorb the charge spike generated when shutter transistor  84  is later turned off.  
         [0026]    Also at this time, a read signal applied to read pin  96  is made high to turn on the NMOS read transistor  98 . The output voltage at pin  99  is then sampled, such as by the analog-to-digital converter (ADC)  12  in FIG. 1 or a capacitor in the sampling circuit of the ADC, to provide a baseline voltage.  
         [0027]    The read signal is then pulled low to shut off read transistor  98 .  
         [0028]    To detect the amount of light impinging on the photoelement  50 , a high signal is applied to reset pin  72  to turn off transistor  74  and isolate line  76  from VDD. The low shutter signal remains applied to pin  83 . Phototransistor  60 , which draws a current proportional to the intensity of light impinging upon the base of phototransistor  60 , discharges the initial charge on lines  76 ,  85 , and  86  during this time.  
         [0029]    After a small (e.g., 20 microsecond) shutter period, the shutter signal is then raised to shut off transistor  84 , isolating line  86  from the phototransistor  60 . As mentioned above, transistors  92  and  94  absorb any charge spike when shutter transistor  84  is turned off. Transistors  92  and  94 , acting as charge compensators, are particularly needed when using very small integrating capacitors to avoid large voltage offsets. Also at this time, the reset signal at pin  72  is driven low to connect VDD to line  76  to provide a source for the current through phototransistor  60  and prevent lines  76  and  85  from being pulled low.  
         [0030]    The remaining charge on line  86  is thus related to the intensity of light that impinged upon phototransistor  60  during the shutter period. Line  86  is coupled to the gate of an NMOS transistor  102  connected as a source follower between VDD and the read transistor  98 . The output pin  99  is coupled to a current source to ground. The charge on line  86  creates a threshold voltage drop across transistor  102  that turns on transistor  102  to a degree so that current flows in transistor  102 . Since transistor  102  is connected as a source follower, the source voltage of transistor  102  is one threshold voltage less than its gate voltage and tracks the gate voltage, so that the source voltage corresponds to the light intensity that impinged upon phototransistor  60  during the shutter period. Transistor  102  also buffers line  86  from any output circuit so any external parasitic capacitances do not distort the charge signal on line  86 .  
         [0031]    A high read signal applied to pin  96  then turns on NMOS read transistor  98  to output a voltage on pin  99  approximately equal to that at the source of transistor  102 . The voltage at the output pin  99  (connected to a column line) may be applied to an analog-to-digital converter without any conversion of charge into voltage, in contrast to the circuit of FIG. 2. The difference between the output voltage at reset and the output voltage after integration is used in one embodiment to generate the light information. Using the difference provides offset cancellation and first order cancellation of variations in the source followers that form the output buffer of each pixel.  
         [0032]    After the voltage at pin  99  is read by conventional circuitry, typically pursuant to row and column addressing operations, the reset signal and shutter signal are pulled low to charge lines  76 ,  85 , and  86  for a new detection cycle. A voltage other than VDD may be used to charge the lines  76 ,  85 , and  86 .  
         [0033]    Additional integrating capacitance may be added to line  86  for any reason, such as for gain control. Such capacitance may be provided as parasitic capacitance, FET capacitors, or other types of capacitors.  
         [0034]    Numerous advantages result from the disclosed photodetector:  
         [0035]    1. a small integrating capacitor can be used, resulting in increased light sensitivity of the pixel and a smaller pixel area;  
         [0036]    2. the source follower isolates the integrating capacitor from other circuitry, reducing noise and increasing design freedom;  
         [0037]    3. there is no need for a charge-to-voltage converter;  
         [0038]    4. decoupling the capacitance of the light sensitive device (e.g., phototransistor  60 ) from the integrating capacitance by transistor  64  allows the use of either a phototransistor or photodiode as the light gathering device. It also allows the detector to be made larger to gather more light, but this increase in detector size and detector capacitance does not cause the sensitivity of this circuit to be reduced as it does in prior art sensors.  
         [0039]    While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.