Abstract:
A device outputting a plurality of paths to a terminal after rearranging the plurality of paths when the paths are arranged in an order of free choice, the device having a counter which receives a path number of a path in response to first data about the path, and increments a count, starting from the path number, in response to additional data arriving and a storage unit, on a side of a communication line, shared by the plurality of paths, which stores real data of the path at positions indicated by the count, wherein the real data stored in the storage unit is output to the terminal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application is a continuation of, and claims the priority of, U.S. patent application No. 09/060,349, now allowed, filed Apr. 15, 1998, the contents of which is incorporated by reference herein. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention generally relates to circuits for connecting communication lines with a terminal, and particularly relates to a circuit which connects communication lines with a terminal when a point-to-multipoint connection is established in a communication system such as a SDH-ring system.  
           [0004]    2. Description of the Related Art  
           [0005]    [0005]FIG. 1 is an illustrative drawing showing an example of an SDH-ring system. The SDH-ring system of FIG. 1 includes communication lines (SDH ring)  500 , a plurality of LSIs  501 , and a plurality of terminals  502  connected to the communication lines  500  via a corresponding one of the LSIs  501 . The LSIs  501  receives data transmitted via the communication lines  500 , and outputs the data to the terminals  502 . The terminals  502  are devices such as a PBX, an ISDN-TD, or the like, to which a telephone, a TV set, etc., can be connected.  
           [0006]    The simplest configuration to achieve a point-to-multipoint connection is to use a fixed communication baud rate in each of the terminals  502 . In order to have simultaneous communication with as many terminals  502  as possible, the communication lines  500  must be provided with channels in the same number as the number of terminal channels defined by a terminal format.  
           [0007]    In detail, a frame pulse XHFO/ 1  is used for indicating a start timing of each frame of communication data, and a HW (highway: communication line) clock HWCO/ 1  is used for establishing synchronization with a plurality of time slots contained in each frame. Each time slot is comprised of 8-bit data, and 32 time slots, for example, together make up one frame. In one frame, one or more time slots are put together to form a channel. When a communication slots. Each channel is called a path, and each path is used for communicating with a corresponding one of the terminals. Within one frame, an order of the path is not restricted but free to be set, and the order can be path  1 , path  7 , path  3 , path  5 , . . . , and so on, for example.  
           [0008]    The start timing of each path on the side of the communication lines  500  is indicated by an offset number which is obtained by counting the number of pulses of HW clock HWC 0 / 1  from the timing of the frame pulse XHFO/ 1 . This offset number is stored in a register inside each LSI  501 . In the case of a fixed communication baud rate, therefore, a fixed number of time slots starting from a timing indicated by the offset number are read from the communication lines  500 , and are output to the terminal. Namely, when the communication baud rate is fixed to four time slots, for example, arrival of the path  1  results in writing data in addresses  0  through  3  of the output to the terminal, and the arrival of the path  3  leads to writing data in addresses  8  through  11 . Such processing is conducted with regard to each path so as to output each path in a predetermined order to the terminal  502 . In this case, the LSI  501  can be implemented by using a simple configuration.  
           [0009]    When a communication baud rate is different for each path, however, the number of time slots varies for different paths. In this case, a simple process as described above is not applicable when paths arranged in an order of free choice on the side of the communication lines  500  need to be output to the terminal  502  in the order of path numbers. The communication baud rate (the number of time slots) of each path is stored in the register inside the LSI  501 , as described above. The communication baud rate thus may be decoded with respect to each path so as to control a position of data writing, so that data of each path is written at an appropriate address position in the output to the terminal. Such a process, however, requires a complex and large circuit structure, resulting in an undesirable enlargement of a circuit size of the LSI  501 .  
           [0010]    Accordingly, there is a need for a small-scale circuit which can output data of paths to the terminal by using a simple process when the paths are provided in an order of free choice on the side of the communication lines in a system employing a point-to-multipoint connection and an adjustable communication baud rate.  
         SUMMARY OF THE INVENTION  
         [0011]    Accordingly, it is a general object of the present invention to provide a small-scale circuit which can satisfy the need described above.  
           [0012]    It is another and more specific object of the present invention to provide a small-scale circuit which can output data of paths to the terminal by using a simple process when the paths are provided in an order of free choice on the side of the communication lines in a system employing a point-to-multipoint connection and an adjustable communication baud rate.  
           [0013]    In order to achieve the above objects according to the present invention, a device for outputting paths to a terminal after rearranging the paths when the paths are arranged in an order of free choice on a side of communication line includes a counter which receives a path number of a path in response to first data of the path, and counts up a count starting from the path number in response to second and following data of the path. The device further includes a storage unit which stores real data of the path at positions indicated by the count, wherein the real data stored in the storage unit is output to the terminal.  
           [0014]    In the device described above, the real data of the path is written at positions controlled by the counter, so that terminal-side output is obtained such that the real data of path n holds an output position thereof in the n-th and following time slots. In this manner, a simple process and a simple circuit based on path numbers can rearrange communication-line data into terminal-side data.  
           [0015]    According to one aspect of the present invention, the device further includes a data-enable circuit which holds 1 at positions therein indicated by the count when the real data is written at the positions indicated by the count in the storage unit, wherein the data-enable circuit holds zero at all positions therein at an initial state with respect to each frame.  
           [0016]    In the device described above, the data “1” is set in the data-enable circuit so as to correspond, in terms of positions thereof, to the read data output to the terminal. In this manner, data for indicating a valid/invalid status of each time slot can be readily obtained with regard to the real data output to the terminal.  
           [0017]    According to another aspect of the present invention, the device further includes a circuit which masks the real data output to the terminal by using data held in the data-enable circuit.  
           [0018]    In the device described above, a valid/invalid status of each time slot can be found by using the data-enable circuit, so that invalid data can be masked so as not to be output.  
           [0019]    According to another aspect of the present invention, the device further includes control-information-allocation circuit which receives control information allocated to the paths, and outputs the control information to the terminal in synchronism with the real data output to the terminal.  
           [0020]    In the device described above, control information such as error information contained in paths can be output to the terminal in synchronism with the real data.  
           [0021]    According to another aspect of the present invention, the control-information-allocation circuit includes a plurality of selectors which are connected in series such that one of the selectors receives as one of inputs thereof an output from a preceding one of the selectors.  
           [0022]    In the device described above, the circuit comprised of the plurality of selectors can allocate the control information.  
           [0023]    According to another aspect of the present invention, each of the plurality of selectors selects either the output from the preceding one of the selectors or the control information on a corresponding path, depending on whether a communication-data rate of the corresponding path is zero.  
           [0024]    In the device described above, the circuit comprised of the plurality of selectors can allocate the control information by using the communication-data rate.  
           [0025]    According to another aspect of the present invention, the device further includes a data-enable circuit which holds 1 at positions therein indicated by the count when the real data is written at the positions indicated by the count in the storage unit, wherein the data-enable circuit holds zero at all positions therein at an initial state with respect to each frame.  
           [0026]    In the device described above, the data “1” is set in the data-enable circuit so as to correspond, in terms of positions thereof, to the read data output to the terminal. In this manner, data for indicating a valid/invalid status of each time slot can be readily obtained with regard to the real data output to the terminal.  
           [0027]    According to another aspect of the present invention, the device further includes a circuit which masks the control information output to the terminal by using data held in the data-enable circuit.  
           [0028]    In the device described above, a valid/invalid status of each time slot can be found by using the data-enable circuit, so that invalid data can be masked so as not to be output.  
           [0029]    According to another aspect of the present invention, the device further includes a frame buffer which holds the real data for at least one frame period.  
           [0030]    In the device described above, the frame buffer can hold an amount of the real data commensurate with one frame.  
           [0031]    According to another aspect of the present invention, the device further includes a converting circuit which converts an output of the frame buffer from parallel data to serial data, the serial data being output to the terminal.  
           [0032]    In the device described above, the parallel output from the frame buffer can be converted into the serial data before being output to the terminal.  
           [0033]    According to another aspect of the present invention, a device is presented for outputting real data of paths to a terminal at terminal-output data positions corresponding to path numbers of the paths when receiving the paths arranged in an order of free choice on a side of communication line, and for outputting multiplexed signaling information contained in the paths in a form of multi-frames to the terminal. The device includes a write-signal-generation circuit which generates write signals with respect to each path by detecting synchronization of the multi-frames, a rotation shifter which performs a rotation shift of a predetermined number of signaling signals contained in each frame of the multi-frames in accordance with the path numbers, a write-signal-control circuit which selects at least one of the write signals in accordance with the path numbers, and a storage unit which stores outputs from the rotation shifter at positions indicated by the write signals selected by the write-signal-control circuit.  
           [0034]    In the device described above, when the signaling signals are supplied in the form of multi-frames during the multiplexed signaling mode, the signaling signals can be output to the terminal so as to have positions thereof corresponding to those of the real data of each path which is also output to the terminal.  
           [0035]    According to another aspect of the present invention, the rotation shifter performs a rotation shift of the predetermined number of signaling signals by {(a path number−1)%(the predetermined number)} bits.  
           [0036]    In the device described above, the signaling signals can be allocated at appropriate positions in the storage unit.  
           [0037]    According to another aspect of the present invention, the write-signal-control circuit comprises a plurality of selectors connected in series such that one of the selectors receives as one of inputs thereof an output from a preceding one of the selectors, each of the selectors having {(a corresponding path number−1)/(the predetermined number)+2} inputs.  
           [0038]    In the device described above, the plurality of selectors connected in series such that one of the selectors receives as one of inputs thereof an output from a preceding one of the selectors is used for selecting the write signals, thereby allocating the signaling signals at appropriate positions in the storage unit.  
           [0039]    According to another aspect of the present invention, each of the selectors comprises a 2-input selector and 3-input selectors provided in a total number of {(the corresponding path number−1)/(the predetermined number)+1}.  
           [0040]    In the device describe above, the write-signal-control circuit can be implemented by using a 2 input selector and a plurality of 3-input selectors.  
           [0041]    According to another aspect of the present invention, each of the selectors comprises 2-input selectors provided in a total number of {(the corresponding path number−1)/(the predetermined number)+1}.  
           [0042]    In the device describe above, the write-signal-control circuit can be implemented by using a plurality of 2-input selectors.  
           [0043]    According to another aspect of the present invention, the device further includes a register which sets mode information with respect to each path, the mode information indicating one of a normal signaling mode and a multiplexed signaling mode, and a selector which receiving the signaling signals corresponding to the multiplexed signaling mode as first inputs and the signaling signals contained in attached information of the paths corresponding to the normal signaling mode as second inputs, and selects one of the first inputs and the second inputs based on the mode information set in the register.  
           [0044]    In the device described above, one of the multiplexed signaling mode and the normal signaling mode can be indicated with respect to each different path, so that the multiplexed signaling mode and the normal signaling mode are allowed to coexist.  
           [0045]    According to another aspect of the present invention, the device further includes signal-allocation circuit which receives the signaling signals contained in the attached information, and outputs the signaling signals contained in the attached information to the terminal in synchronism with the real data output to the terminal.  
           [0046]    In the device described above, the signaling signals contained in the attached information of the paths can be output to the terminal in synchronism with the real data.  
           [0047]    According to another aspect of the present invention, the signal-allocation circuit comprises a plurality of selectors which are connected in series such that one of the selectors receives as one of inputs thereof an output from a preceding one of the selectors.  
           [0048]    In the device described above, the circuit comprised of the plurality of selectors can allocate the signaling signals contained in the attached information.  
           [0049]    According to another aspect of the present invention, each of the plurality of selectors selects either the output from the preceding one of the selectors or a signaling signal contained in the attached information of a corresponding path, depending on whether a communication-data rate of the corresponding path is zero.  
           [0050]    In the device described above, the circuit comprised of the plurality of selectors can allocate the signaling signal(s) by using the communication-data rate.  
           [0051]    According to another aspect of the present invention, the device further includes mode-information-allocation circuit which receives the mode information from the register, and outputs the mode information to the terminal in synchronism with the real data output to the terminal.  
           [0052]    In the device described above, the mode information stored in the register with respect to each path can be output to the terminal in synchronism with the real data.  
           [0053]    According to another aspect of the present invention, the mode-information-allocation circuit comprises a plurality of selectors which are connected in series such that one of the selectors receives as one of inputs thereof an output from a preceding one of the selectors.  
           [0054]    In the device described above, the circuit comprised of the plurality of selectors can allocate the mode information.  
           [0055]    According to another aspect of the present invention, each of the plurality of selectors selects either the output from the preceding one of the selectors or the mode information of a corresponding path, depending on whether a communication-data rate of the corresponding path is zero.  
           [0056]    In the device described above, the circuit comprised of the plurality of selectors can allocate the mode information by using the communication-data rate.  
           [0057]    Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0058]    [0058]FIG. 1 is an illustrative drawing showing an example of an SDH-ring system of the related art;  
         [0059]    [0059]FIG. 2 is an illustrative drawing showing path allocation according to the principle of the present invention;  
         [0060]    [0060]FIG. 3A is a block diagram of a HW-timing-control unit which generates signals for controlling a timing of communication-line data;  
         [0061]    [0061]FIG. 3B is a block diagram of a real-data-TSW unit which converts input-communication data to terminal-output data based on signals from the HW-timing-control unit;  
         [0062]    [0062]FIGS. 4A through 4N are timing charts showing operations of the HW-timing-control unit and the realdata-TSW unit;  
         [0063]    [0063]FIGS. 5A through 5G are timing charts for explaining operations of a data-enable-buffer unit and a portion relevant thereto;  
         [0064]    [0064]FIG. 6 is a block diagram showing an embodiment of a receiver circuit which employs the HWtiming-control unit and the real-data-TSW unit according to the present invention;  
         [0065]    [0065]FIG. 7 is a block diagram showing a control/error-TSW unit and a signaling-TSW unit together;  
         [0066]    [0066]FIG. 8 is a circuit diagram of one of terminal-TS-allocation units;  
         [0067]    [0067]FIG. 9 is an illustrative drawing showing a resulting output of the terminal-TS-allocation unit shown in FIG. 8;  
         [0068]    [0068]FIG. 10 is an illustrative drawing showing a configuration of a signaling multi-frame;  
         [0069]    [0069]FIG. 11 is a block diagram of a signaling separation unit of FIG. 6;  
         [0070]    [0070]FIG. 12 is an illustrative drawing showing relations between a rotation shifter and D-FFs;  
         [0071]    [0071]FIG. 13 is an illustrative drawing for explaining operations of a signaling-data holding unit shown in FIG. 11;  
         [0072]    [0072]FIG. 14 is a circuit diagram of a write-control unit;  
         [0073]    [0073]FIG. 15 is a block diagram of a selector shown in FIG. 14;  
         [0074]    [0074]FIG. 16 is a block diagram showing a generalized configuration of a selector shown in FIG. 15;  
         [0075]    [0075]FIG. 17 is a block diagram showing another configuration of a selector shown in FIG. 14;  
         [0076]    [0076]FIG. 18 is a block diagram showing a variation of the selector shown in FIG. 17;  
         [0077]    [0077]FIG. 19 is a block diagram of a generalized configuration of a selector shown in FIG. 18;  
         [0078]    [0078]FIG. 20A is a block diagram of a timing-generation circuit;  
         [0079]    [0079]FIG. 20B is a block diagram of a configuration which makes a route selection based on timing signals generated by the timing-generation unit;  
         [0080]    [0080]FIG. 21 is a circuit diagram showing detailed configurations of a terminal-TS-counter unit, a pathtiming-signal-generation unit, an active-TS-countercontrol unit, and an active-TS-signal-generation unit of FIG. 20A;  
         [0081]    [0081]FIG. 22 is a block diagram of a parallel/serial-conversion unit;  
         [0082]    [0082]FIGS. 23A through 23Y are timing charts showing route-selection operations performed by the configurations of FIGS. 20A and 20B;  
         [0083]    [0083]FIG. 24A is a block diagram of a test-control unit;  
         [0084]    [0084]FIG. 24B is a block diagram of a configuration which performs insertion/check of test patterns based on timing signals generated by the test-control unit;  
         [0085]    [0085]FIG. 25 is a circuit diagram showing detailed configurations of a terminal-TS-counter unit, a pathtiming-signal-generation unit, and a valid-TS-signal-generation unit of the test-control unit shown in FIG. 24A;  
         [0086]    [0086]FIG. 26 is a circuit diagram of a test-insertion/check-signal-generation unit shown in FIG. 24A; and  
         [0087]    [0087]FIGS. 27A through 27Q are timing charts showing the test-insertion/check operations which are performed by the configurations of FIGS. 24A and 24B. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0088]    In the following, a principle and embodiments of the present invention will be described with reference to the accompanying drawings.  
         [0089]    [0089]FIG. 2 is an illustrative drawing showing path allocation according to a principle of the present invention.  
         [0090]    According to the present invention as shown in FIG. 2, a communication-line path n (i.e., CHn) is assigned to time slots starting from the n-th time slot in an output to a terminal regardless of a communication baud rate of the path n. In order to make this allocation viable, communication-line paths n+l through n+m−1 are not used when the communication-line path n is comprised of real data equivalent to m time slots. When communication-line paths are structured in this manner, arrival of the path n including m time slots is dealt with simply by writing data to m time slots starting from the n-th time slot in the output to the terminal. This provides a simple process of outputting data of communication-line paths to the terminal in an order of path numbers.  
         [0091]    In FIG. 2, F indicates attached information which is comprised of 8 bits to represent error-control information, etc., and time slots labeled by numbers represent real data.  
         [0092]    [0092]FIG. 3A is a block diagram of a HW-timing-control unit  10  which generates signals for controlling a timing of communication-line data. FIG. 3B is a block diagram of a real-data-TSW unit  20  which converts input-communication data to terminal-output data based on the signals from the HW-timing-control unit  10 .  
         [0093]    The HW-timing-control unit  10  of FIG. 3A includes a decoder  11 , a match-detection circuit  12 , an encoder  13 , an OR circuit  14 , a latch  15 , a selector  16 , a baud-rate counter  17 , a timing-generation circuit  18 , and a HW-time-slot counter  19 .  
         [0094]    The HW-time-slot counter  19  receives a frame pulse XHF and a HW clock HWC, and counts pulses of the HW clock HWC by starting from the frame pulse XHF. The count number is decoded by the decoder  11  to generate a read-address signal WADR 3 - 0  and a read-timing signal RTSW 2 ES. Details of these signals will be described later. In FIGS. 3A and 3B and hereinafter, the symbol “n-0” following a signal name indicates that this signal is parallel data comprised n+l bits from bit  0  to bit n. (For example, WADR 3 - 0  is parallel data comprised of 4 bits.) By the same token, the symbol “n-1” means that the pertinent signal is parallel data comprised of n bits from bit  1  to bit n.  
         [0095]    The count number (HWTSC) of the HW-time-slot counter  19  is supplied to the match-detection circuit  12 , where it is compared with an offset OFFSET stored in a register. The offset OFFSET indicates a start timing of each path relative to the frame pulse XHF by using a count of pulses of the HW clock HWC, and is provided for each of 30 paths. The match-detection circuit  12  makes a comparison with regard to the 30 paths, and outputs data comprised of 30 bits. This output data has a bit of “1” at a bit position corresponding to a path number when the offset OFFSET of this path number matches the count number. Namely, this bit position of “1” indicates a path number of a path which starts at a position inside a current frame indicated by a current pulse of the HW clock HWC.  
         [0096]    The output data from the match-detection circuit  12  is encoded by the encoder  13 , and is stored in the latch  15  as a path ID p-id. The OR circuit  14  executes an OR operation with respect to all bits of the output data from the match-detection circuit  12 , and changes an output (RATELOAD) thereof to HIGH when at least one of these bits is HIGH. The latch  15  performs a latch operation in response to the output of the OR circuit  14 . Namely, data RPATH 4 - 0  stored in the latch  15  indicates a path number of a path which is present at a inside-frame position indicated by the current pulse of the HW clock HWC.  
         [0097]    The path ID p-id is input to the selector  16 . The selector  16  selects one of the data rates RATE corresponding to 30 respective paths stored in the register, such that the selected one of the data rates RATE corresponds to the path ID p-id. The selected one of the data rates RATE is supplied to the baud-rate counter  17 . The baud-rate counter  17  reads the data rate of the path ID p-id at a timing indicated by the output of the OR circuit  14 , and, then, counts down the received data rate to output the count. The timing-generation circuit  18  decodes the count, and outputs a path-start signal RDTST 1  and a slot-counter signal RDTST. The path-start signal RDTST 1  becomes HIGH at a start timing of a given path, and the slot-counter signal RDTST is comprised of the same number of pulses as the number of data slots of this path.  
         [0098]    Each signal output from the HW-timing-control unit  10  of FIG. 3A is supplied to the real-data-TSW unit  20  of FIG. 3B.  
         [0099]    The real-data-TSW unit  20  includes a latch  21 , a latch  22 , a write-address counter  23 , a real-data-buffer unit  24 , a falling-edge-detection circuit  25 , a data-enable-buffer unit  26 , a latch  27 , a selector  28 , and D-FFs  29 - 1  and  29 - 2 .  
         [0100]    The latch  21  latches input-communication data HWRD 7 - 0  which is 8-bit data corresponding to a single time slot, and supplies same to the real-data-buffer unit  24 . The real-data-buffer unit  24  is comprised of a RAM, for example, and stores the input-communication data HWRD 7 - 0  at an indicated address. This address is controlled in order to generate the terminal-output data shown in FIG. 2.  
         [0101]    The address is generated by the write-address counter  23 . The write-address counter  23  reads a path number RPATH 4 - 0  in response to the path-start signal RDTST 1 , and counts up the path number in synchronism with the slot-counter signal RDTST. Actually, the path number is first subtracted by one, and is counted up by using the slot-counter signal RDTST. Subtraction by one is necessary because addresses of the real-data-buffer unit  24  start from 0 rather than 1, so that the path number minus one is actually a start address at which the path should be written. The write-address counter  23  supplies the count number to the real-data-buffer unit  24  as a write address tawa 4 - 0 . The slot-counter signal RDTST is delayed by the latch  22 , and, then, is supplied to the real-data-buffer unit  24  as a write-enable signal wen.  
         [0102]    In this manner, the m time slots of the path n on the side of the communication lines are written at addresses n-1 to n−l+m−1 in the real-data-buffer unit  24 .  
         [0103]    [0103]FIGS. 4A through 4N are timing charts showing operations of the HW-timing-control unit  10  and the real-data-TSW unit  20  described above. In the figures, a signal RATECNT indicates a count number of the baud rate counter  17  shown in FIG. 3A. Other signals have been already described in the above description.  
         [0104]    According to the principle of the present invention shown in FIG. 2, the terminal-output data is generated as described above to output communication-line paths to the terminal in an order of path numbers. Elements of FIG. 3B which have not been described are those which become necessary in a practical system implementation, and will be described below.  
         [0105]    The terminal-output data stored in the real-data-buffer unit  24  is read two time slots by two time slots by using the read-address signal WADR 3 - 0 , and is stored in the D-FF  29 - 2 . The latch timing of the D-FF  29 - 2  is defined by the read-timing signal RTSW 2 ES. The output of the D-FF  29 - 2  is terminal-output data Rdata.  
         [0106]    The data-enable-buffer unit  26  is a register which indicates a valid/invalid status of the terminal-output data. All bits of the terminal-output data do not have valid data written therein. Some bits include invalid data. In order to indicate a valid/invalid status of these bits, the data-enable-buffer unit  26  assign “1” to bits when real data is written in corresponding addresses (time slot positions), and assign “0” to other bits. This is achieved by supplying the write address tswa 4 - 0  from the write-address counter  23  and the write-enable signal wen from the latch  22  to the data-enable-buffer unit  26  so as to write “1” at the write address tswa4-0. Here, the data-enable-buffer unit  26  stores “0” in all bits thereof at an initial state.  
         [0107]    To ensure that the data-enable-buffer unit  26  have “0” in all bits thereof at the initial state, the falling-edge-detection circuit  25  detects a falling edge of the read-timing signal RTSW 2 ES, and generates a clear signal so as to clear the data-enable-buffer unit  26  at this falling-edge timing. That is, the dataenable-buffer unit  26  is cleared immediately after the data is read. The latch  27  introduces a predetermined length of delay to the read-address signal WADR 3 - 0 . Based on the read-address signal WADR 3 - 0  which is delayed by the predetermined length of delay, the selector  28  selects data of two time slots from the 32-bit output of the data-enable-buffer unit  26  such that the selected data corresponds to the output data from the real-data-buffer unit  24 . The selected data is provided to the D-FF  29 - 1 . An output of the D-FF  29 - 1  is data-enable signal Den indicating a valid/invalid status of each bit of the terminal-output data Rdata.  
         [0108]    [0108]FIGS. 5A through 5G are timing charts for explaining operations of the data-enable-buffer unit  26  and a portion relevant thereto. As shown in the figures, the data-enable-buffer unit  26  is cleared by the clear signal immediately after the data is read.  
         [0109]    [0109]FIG. 6 is a block diagram showing an embodiment of a receiver circuit of the LSI  501  (FIG. 1) which employs the HW-timing-control unit  10  and the real-data-TSW unit  20  according to the present invention.  
         [0110]    The receiver circuit of FIG. 6 includes a serial-to-parallel-conversion unit  30 , an attached-TSseparation-and-error-detection unit  31 , a signaling-separation unit  32 , a control/error-TSW unit  33 , a signaling-TSW unit  34 , a register unit  35 , a decoder  36 , a receiver-ES unit  37 , a valid-bit unit  38 , a realdata-P/S unit  39 , a control-bit unit  40 , a signaling unit  41 , mask units  42  through  44 , and a terminal-lineside-timing-control unit  45  in addition to the HW-timing-control unit  10  and the real-data-TSW unit  20 .  
         [0111]    The serial-to-parallel-conversion unit  30  converts  4 -bit data input from the communication lines to 8-bit data (HWRD 7 - 0 ). The attached-TS-separation-and-error-detection unit  31  separates an attachedinformation time slot of each path, and attends-to error detection and protection. This process is performed with respect to each path. The signaling separation unit  32  separates and keeps signaling data during a multiple-signaling mode. The control/errorTSW unit  33  rearranges error information (attached information) in terminal-side time slots. The signaling-TSW unit  34  rearranges the signaling data in the terminal-side time slots. The register unit  35  keeps the offset OFFSET, the communication-data rate RATE, and SIGMOD information with respect to each path. The decoder  36  decodes the communication-data rate RATE of each path and generates active signals PACT 30 - 1  (30 bits) with respect to respective paths. If the communication-data rate RATE is zero for a given path, the active signal PACT of this path is zero. If the communication-data rate RATE is not zero for a given path, the active signal PACT of this path is 1.  
         [0112]    The receiver-ES unit  37  serves as a means for synchronization since communication-line-side (HW-side) timings (HWC) are asynchronous with terminal-side timings (PCLK), and makes the HW data synchronize with PCLK by use of ES (elastic buffer). If the HW side and the PCLK side are in synchronism with each other, the receiver-ES unit  37  may be a simple one-frame buffer. The receiver-ES unit  37  may be implemented by using a dual-port RAM or the like.  
         [0113]    The valid-bit unit  38 , the real-data-P/S unit  39 , the control-bit unit  40 , the signaling unit  41 , and the mask units  42  through  44  together form a P/S-conversion unit, which holds an output of the receiver-ES unit  37 , and applies a serial conversion to 8-bit real data. When a valid bit of the valid-bit unit  38  receiving data from the data-enable-buffer unit  26  of FIG. 3B is zero, a current time slot is regarded as unused time slot, so that the mask units  42  through  44  attend to the mask processing of the terminal output. The terminal-line-side-timing-control unit  45  generates a receiver-ES-read-timing signal for outputting the terminal output.  
         [0114]    In what follows, those elements of the receiver circuit of FIG. 6 which are relevant to the present invention will be described in detail.  
         [0115]    [0115]FIG. 7 is a block diagram showing the control/error-TSW unit  33  and the signaling-TSW unit  34  together.  
         [0116]    A configuration of FIG. 7 performs processing of allocating control/error information of each path to terminal-output time slots so as to fit in the terminal-output data after the control/error information (attached information) shown as F in FIG. 2 is separated from each path. Further, the configuration of FIG. 7 performs allocation to the terminal-output time slots so as to fit in the terminal-output data with regard to signaling information included in the attached information F in the normal mode.  
         [0117]    A signaling signal indicates that the line is busy in the case of telephone, for example, and generally represents whether communication is in place or not. There are two modes for transmitting the signaling signal. One is a normal mode, and the other is a multiplex mode. In the normal mode, a 1-bit signaling signal is included in the attached information F. In the multiplex mode, a signaling time slot is attached to the real data at the front thereof to transmit signaling signals because a 1-bit signaling signal cannot represent information on a plurality of terminals when the plurality of terminals are multiplexed in the same path (e.g., when a plurality of telephones are connected to a single terminal). Detailed account of multiplexed signaling will be provided later. In FIG. 7, it is assumed that multiplexed-signaling signals SIGA 30 - 1  have been already allocated to terminal-output time slots.  
         [0118]    A configuration of FIG. 7 includes terminal-TS-allocation units  50  through  52 , a selector  53 , a latch  54 , selectors  55  and  56 , and D-FFs  57  and  58 . The terminal-TS-allocation unit  50  receives the control/error signal from the attached-TS-separation-and-error-detection unit  31  of FIG. 6, and further receives the active signals PACT 30 - 1  from the decoder  36  of FIG. 6. The terminal-TS-allocation unit  50  allocates the control/error signal to the terminal-output time slots based on the active signals PACT 30 - 1 . The terminal-TS-allocation unit  51  receives the signaling signals RST 30 - 1  of the normal mode from the attached-TS-separationand-error-detection unit  31  of FIG. 6, and, also, receives the active signals PACT 30 - 1  from the decoder  36  of FIG. 6. The terminal-TS-allocation unit  51  allocates the signaling signals RST 30 - 1  to the terminal-output time slots based on the active signals PACT 30 - 1 . The terminal-TS-allocation unit  52  receives mode signals SIGMOD 30 - 1  indicative of a signaling mode from the register  35  of FIG. 6, and, also, receives the active signals PACT 30 - 1  from the decoder  36  of FIG. 6 . The terminal-TS-allocation unit  51  allocates the mode signals SIGMOD 30 - 1  to the terminal-output time slots based on the active signals PACT 30 - 1 .  
         [0119]    The latch  54  delays the read-address signal WADR 3 - 0  from the HW-timing-control unit  10  shown in FIG. 6. Based on the delayed read-address signal WADR 30 , the selector  55  reads the control/error information two time slots by two time slots from the terminal-TS-allocation unit  50 . The control/error information is then stored in the D-FF  57 . The latch timing of the DFF  57  is defined by the read-timing signal RTSW 2 ES.  
         [0120]    The selector  53  receives from the terminal-TS-allocation unit  50  the signaling-mode signals SIGMOD 30 - 1  allocated to the terminal-output time slots. The selector  53  selects the multiplexed-signaling signals SIGA 30 - 1  when the signaling mode is a multiplex mode, and selects the signaling signals RST 30 - 1  output from the terminal-TS-allocation unit  51  when the signaling mode is a normal mode. The multiplexed-signaling signals SIGA 30 - 1  or the signaling signals RST 30 - 1  of the normal mode selected by the selector  53  is read by a unit of two time slots at a time by the selector  56 . The signaling signals are then stored in the D-FF  58 . The latch timing of the DFF  58  is defined by the read-timing signal RTSW 2 ES. Outputs of the D-FFs  57  and  58  are supplied to the receiver-ES unit  37  shown in FIG. 6.  
         [0121]    [0121]FIG. 8 is a circuit diagram of one of the terminal-TS-allocation-units  50  through  52 .  
         [0122]    The terminal-TS-allocation unit of FIG. 8 includes selectors  60 - 1  through  60 - 30 , which are connected in series to form a chain structure. The nth selector  60 -n among the selectors  60 - 1  through  60 - 30  receives the active signal PACTn corresponding to the n-th time slot among the active signals PACT 30 - 1 , and further receives a signal Cn. The signal Cn is one of the n-th bit of the control/error information, the n-th bit of the signaling signals RST 30 - 1 , and the n-th bit of the signaling-mode signals SIGMOD 30 - 1 . In the case of the terminal-TS-allocation unit  51 , for example, signals C 1  through C 30  are the signaling signals RST 301 .  
         [0123]    The selector  60 - 1  further receives a signal “0”. The selector  60 - 1  selects the signal C 1  when the active signal PACT 1  is 1, and selects the signal “0” when the active signal PACT 1  is 0. The other selectors  60 - 2  through  60 - 30  receive an output of the respective preceding selector. The selector  60 -n selects the signal Cn when the active signal PACTn is 1, and selects the output of the preceding selector when the, active signal PACTn is 0. As previously described, when the communication-data rate RATE of a given path is zero, the active signal PACT of this path is zero. On the other hand, a non-zero value of the communication-data rate RATE for a given path means that the active signal PACT of this path is 1.  
         [0124]    [0124]FIG. 9.is an illustrative drawing showing a resulting output of the terminal-TS-allocation unit shown in FIG. 8.  
         [0125]    In FIG. 9, path  1  has the communication-data rate of 4, and path  5  has the communication-data rate of 10. Further, the communication-data rate of path  15  is 8, and the communication-data rate of path  28  is 3. Other paths have the communication-data rate of zero.  
         [0126]    As shown in FIG. 9, the fifth time slot, which has a non-zero communication-data rate, is provided with a corresponding signal C 5  as an output to this time slot. The sixth through fourteenth time slots also have the signal C 5  as an output to these time slots since the corresponding selectors  60 - 6  through  60 - 14  select an output of the preceding selector.  
         [0127]    In this manner, the signals C 1 - 30  are provided at time-slot positions when paths are in existence at these time-slot positions on the side of the communication lines, i.e., when the communication data rate is not zero at these time-slot positions, and the signals C 1 - 30  are extrapolated to other time slots where the communication-data rate is zero. This makes it possible to allocate the control/error information, the signaling signals, etc., to all the time slots which are used by the paths on the side of the terminal-output data.  
         [0128]    In what follows, the signaling multiplexing will be described.  
         [0129]    As previously stated, a time slot for signaling purposes is attached to the real data of each path at the front thereof in the multiplexed signaling mode. This signaling-purpose time slot is transmitted by use of multi-frames. Namely, a single signaling-purpose time slot is transmitted for a given path with respect to each frame. When a plurality of signaling-purpose time slots are put together over a plurality of frames, the data which is put together has a meaning thereto as signaling information regarding the given path.  
         [0130]    [0130]FIG. 10 is an illustrative drawing showing a configuration of a signaling multi-frame.  
         [0131]    In FIG. 10, signaling-purpose time slots which are supplied over 8 frames with respect to a given path are shown. Each signaling-purpose time slot is comprised of 8 bits from b 0  to b 7 . Bits denoted as F, S, and X are not used. A signaling-purpose time slot of the first frame, for example, includes 8 bits (F, 0, S, X, X, X, X, X). A signaling-purpose time slot of the second frame is comprised of 8 bits (F, 1, S, A1, A2, A3, A4, A5).  
         [0132]    The bit b 1  of these signaling-purpose time slots makes up a bit pattern (0, 1, 1, 1, 1, 1, 1, 1) over the 8 frames. This bit pattern is used as a synchronization pattern. The bit An represents the nth signaling signal.  
         [0133]    The entirety of what is shown in FIG. 10 constitutes signaling information on a given path. That is, a total of 30 signaling signals A 1  through A 30  can be transmitted with respect to a single path. In other words, a maximum of 30 multiple terminals can be provided for a single path. Since the maximum number of paths on the communication-line side is 30, a circuit for processing signaling information needs to have a capacity to process 30 signaling signals for 30 paths. A simple configuration would require a storage capacity of 900-bit (30×30 bit) information.  
         [0134]    In the following, a circuit structure which can process signaling information by use of a small-scale circuit without a need to have a 900-bitinformatin-storage capacity will be described.  
         [0135]    [0135]FIG. 11 is a block diagram of the signaling-separation unit  32  of FIG. 6.  
         [0136]    The signaling-separation unit  32  of Fig- 11  includes a multi-frame-synch-detection/write-generation unit  70  and a signaling-data holding unit  80 .  
         [0137]    The multi-frame-synch-detection/write-generation unit  70  includes a multi-framesynchronization-detection unit  71  and a write-signal-generation unit  72 . The multi-frame-synchronizationdetection unit  71  receives a multi-frame-synchronization signal HWRD 1  (bit bl of FIG. 10), and further receives signaling-TS-valid-timing signals RSTST 30 - 1  from the HW-timing-control unit  10  of FIG. 6. Based on these received signals, the multi-frame-synchronization-detection unit  71  generates a synchronization signal SYNCm (m=1, 2, . . . 30) which is 1 when synchronization is established, and is 0 when no synchronization is in place. The synchronization signal SYNCm is a one-bit signal generated with respect to each of the 30 paths. The write-signal-generation unit  72  generates a write signal Wm-n based on the synchronization signal SYNCm. Here, m represents a path number, and n denotes a frame number. That is, the write signal W 3 - 2 , for example, corresponds to the second frame of the path  3 , and is used for writing a signaling signal in the signaling-data holding unit  80  when the second frame of the path  3  is input.  
         [0138]    The multi-frame-synch-detection/write-generation unit  70  has a configuration which is well within ordinary skill in the art, and is comprised of logic circuits such as flip-flops, counters, etc. The signaling-TS-valid-timing signals RSTST 30 - 1  includes RSTST 1  through RSTST 30  corresponding to path  1  through path  30 , respectively. One of the signaling-TS-valid-timing signals RSTST 30 - 1  becomes active in response to the active path.  
         [0139]    The signaling-data holding unit  80  includes a write-control unit  81 , a rotation shifter  82 , and 30 DFFs  83 . Each of the D-FFs  83  stores 1-bit data, so that the set of the D-FFs  83  stores 30-bit data. The write-control unit  81  receives the write signal Wm-n to generate write signals WA 30 - 1 , which are respectively supplied to the D-FFs  83  as a write-enable signal. Further, the write-control unit  81  receives the synchronization signal SYNCm to generate synchronization-establishment signals sx 3 O- 1 , thereby enabling data to be written in the D-FFs  83  only when synchronization is established. Data stored in the DFFs  83  is the input-communication data HWRD 7 - 3  (from third bit to the seventh bit), which is supplied via the rotation shifter  82 . The data stored in the D-FFs  83  is output as the multiplexed-signaling signals SIGA 30 - 1  allocated to the terminal-output time slots.  
         [0140]    [0140]FIG. 12 is an illustrative drawing showing relations between the rotation shifter  82  and the D-FFs  83 . The rotation shifter  82  receives HWRD 3  through HWRD 7 , which are respectively the third bit through the seventh bit of the input-communication data HWRD 7 - 0  (i.e., the data from the bit b 3  to the bit b 7  of FIG. 10), and applies an appropriate rotation shift before outputting the data to the D-FFs  83 . An output line S 3  of the rotation shifter  82  is connected in parallel to the first D-FF  83  corresponding to SIGA 1 , the sixth D-FF  83  corresponding to SIGA 6 , the eleventh D-FF  83  corresponding to SIGA 11 , the sixteenth D-FF  83  corresponding to SIGA 16 , the twenty first D-FF  83  corresponding to SIGA 21 , and the twenty sixth D-FF  83  corresponding to SIGA 26 . By the same token, each of output lines S 4  through S 7  is connected in parallel to a corresponding set of D-FFs  83  vertically aligned as shown in FIG. 12.  
         [0141]    [0141]FIG. 13 is an illustrative drawing for explaining operations of the signaling-data holding unit  80  shown in FIG. 11. FIG. 13 shows an exemplary case in which the path  1 , the path  5 , the path  15 , and the path  28  have the communication-data rate RATE of 4, 10 , 8, and 3, respectively. Other paths have the communication-data rate of zero. In FIG. 13, Am-n represents a signaling signal An of path m.  
         [0142]    As shown in FIG. 13, the signaling signals A 1  through A 4  of the path  1  are stored in the first one through the fourth one of the D-FFs  83  as SIGAl through SIGA 4 , respectively. The signaling signals A 1  through A 10  of the path  5  are stored in the fifth one through the fourteenth one of the D-FFs  83  as SIGA 5  through SIGA 14 , respectively. Further, the signaling signals A 1  through A 8  of the path  15  are stored in the fifteenth one through the twenty second one of the DFFs  83  as SIGA 15  through SIG 22 , respectively. Finally, the signaling signals A 1  through A 3  of the path  28 . are stored in the twenty eighth one through the thirtieth one of the D-FFs  83  as SIGA 28  through SIGA 30 , respectively. In this case, SIGA 23  through SIGA 27  are actually unused, but the signaling signals A 9  through A 13  of the path  15  are written as shown in the figure. These unused portions are later masked by the data-enable signals, so that the data written in these portions does not cause any problem.  
         [0143]    When the example of FIG. 13 is related to the illustration of FIG. 12, it is understood that Al through A 5  (bit b 3  through bit b 7 ) of the path  1  should be output to the output lines S 3  through S 7 , respectively, without any rotation shift, so that Al through A 4  are written in the first one through the fourth one of the D-FFs  83 . Further, Al through A 5  (bit b 3  through bit b 7 ) which are the signaling signals included in the first frame among the signaling signals A 1  through A 10  of the path  5  should be subjected to a rotation shift to the right by 4 bits, so that Al is supplied to the output line S 7 , and A 2  through A 5  are supplied to the output lines S 3  through S 6 , respectively, being stored in the fifth one through the ninth one of the D-FFs  83 . A 6  through A 10  (bit b 3  through bit b 7 ) which are included in the second frame among the signaling signals A 1  through A 10  of the path  5  should also be subjected to a 4-bit-to-the-right rotation shift so as to be stored in the tenth through fourteenth ones of the D-FFs  83 . By the same token, the path  15  should undergo a rotation shift to the right by 4 bits, and the path  28  should experience a rotation shift to the right by 2 bits.  
         [0144]    In general, the path n should be subjected to a rotation shift by (n-1)%5 bits (x%y means a residual after dividing x by y).  
         [0145]    In order to achieve this operation, OR circuits  84 - 1  through  84 - 5  are provided as shown in FIG. 12 to perform a rotation shift to the right by an appropriate number of bits in accordance with a given path number. The OR circuit  84 -n receives the signaling-TS-valid-timing signals RSTSTn, RSTSTn+ 5 , RSTSTn+ 10 , RSTSTn+ 15 , RSTSTn+ 20 , and RSTSTn+ 25  (i.e., n+multiple of 5). When a certain path is valid, one of the OR circuits  84 - 1  through  84 - 5  which receives a signaling-TS-valid-timing signal corresponding to this valid path generates an active output. Outputs of the OR circuits  84 - 1  through  84 - 5  control the operations of the rotation shifter  82 , thereby achieving a rotation shift to the right by a bit number ranging from 0 bit to 4 bits. By use of this configuration, an arrangement of FIG. 13 can be put in place by performing no rotation shift with respect to the path  1 , a 4-bit-to-the-right rotation shift with respect to the path  5  and the path  15 , and a 2-bit-to-the-right rotation shift with respect to the path  28 .  
         [0146]    In order to write the outputs from the rotation shifter  82  in the D-FFs  83 , the enable signals are supplied to the D-FFs  83 . As previously described, a signaling signal corresponding to the n 4 h frame of the path m is written by using the write signal Wm-n. To this end, the write signal Wm-n should be supplied to an appropriate one of the D-FFs  83  as an enable signal. This control is attended to by the write-control unit  81 .  
         [0147]    [0147]FIG. 14 is a circuit diagram of the write-control unit  81 .  
         [0148]    The write-control unit  81  of Fig- 14  includes selectors  90 - 1  through  90 - 30 . The selectors  90 - 1  through  90 - 30  are connected in series to form a chain structure in which a selector receives as an input thereof an output from a preceding selector. Each of the selectors  90 - 1  through  90 - 30  receives one or more write signals Wm-n (write signal for the path m of the n-th frame) in addition to the output from the preceding selector.  
         [0149]    Signals supplied to the selectors  90 - 1  through  90 - 30  for the purpose of selection control are one or more bits of the active signals PACT 30 - 1 . Each of the selectors  90 - 1  through  90 - 30  selects the output from the preceding selector when one or more bits of the supplied active signals PACT 30 - 1  are all zero. When one of these bits is 1 and there is a write signal input corresponding to this bit, this write signal is selected. If there is no write signal input corresponding to this bit having the value of 1, the output from the preceding selector is selected. Here, the active signals PACT 30 - 1  have a respective priority order in accordance with the ordinal numbers thereof (see the following example). Outputs WA 1  through WA 30  from the selectors  90 - 1  through  90 - 30  are respectively supplied to the first through thirtieth ones of the DFFs  83  as an enable signal for writing data.  
         [0150]    A description of operations will be given below by taking the  15 -th selector  90 - 15  as an example. The selector  90 - 15  receives an output from the preceding selector  90 - 14 , and, also, receives the write signals W 15 - 1 , W 10 - 2 , and W 5 - 3 . As selection-control signals, the active signals PACT 15 - 5  (from  5 -th PACT 5  to  15 -th PACT 15 ) are supplied.  
         [0151]    If all the bits from PACT 5  to PACT 15  are zero, the output of the preceding selector  90 - 14  is selected.  
         [0152]    If PACT 15  is 1, the write signal W 15 - 1  is selected;  
         [0153]    else if one of PACT 11  through PACT 14  is 1, the output of the preceding selector  90 - 14  is selected;  
         [0154]    else if PACT 10  is 1, the write signal W 10 - 2  is selected;  
         [0155]    else if one of PACT 6  through PACT 9  is 1, the output of the preceding selector  90 - 14  is selected;  
         [0156]    else if PACT 5  is 1, the write signal W 5 - 3  is selected.  
         [0157]    In this manner, if PACTn is 1, selection is made to pick the write signal Wn-x (x is one of 1 through 6).  
         [0158]    The reason why selection is made this way is as follows. In the example of FIG. 13, the signaling signal stored in the  15 -th D-FF  83 -is the signaling signal A 15 - 1  which is the first signaling signal of the path  15 . When an example having a path configuration different from that of the example of FIG. 13 is considered, however, the  15 -th D-FF  83  may store another signaling signal in stead of the signaling signal A 15 - 1 . For example, if path  14  was in existence, it would be possible that the signaling signal A 14 - 2 , which is the second signaling signal of the path  14 , is stored in the  15 -th D-FF  83 . By the same token, if path  13  was in existence, the signaling signal A 13 - 3  would be possibly stored. Alternately, it would be possible that the signaling signal A 1 - 15  of the path  1  is stored. In this manner, the  15 -th D-FF  83  may store a signaling signal-of any one of the path  1  through the path  15 .  
         [0159]    First, consideration is given to the example in which the signaling signal A 15 - 1  of the path  15  is stored. In this case, the active signal PACT 15  is 1, so that the write signal W 15 - 1  is selected to place the  15 -th D-FF  83  in a write-enable condition. The rotation shifter  82  of FIG. 12 performs a rotation shift to the right by 4 bits, so that the signaling signal A 15 - 1  (bit b 3 ) of the path  15  is stored in the  15 -th DFF  83  via the output line S 7 .  
         [0160]    Next, consideration is given to the example in which the signaling signal A 14 - 2  of the path  14  is stored. In this case, the active signal PACT 14  is  1 , so that the output of the preceding selector  90 - 14  is selected. In the preceding selector  90 - 14 , the write signal W 14 - 1  is selected by PACT 14 . The selector  90 - 15  thus selects the write signal W 14 - 1  output from the preceding selector  90 - 14 , and places the  15 -th D-FF  83  in a write-enable condition. The rotation shifter  82  of FIG. 12 performs a rotation shift to the right by 3 bits, so that the signaling signal A 14 - 2  (bit b 4 ) of the path  14  is stored in the  15 -th D-FF  83  via the output line S 7 .  
         [0161]    Next, consideration is given to the example in which the signaling signal A 1 - 15  of the path  1  is stored. In this case, the active signal PACT 1  is 1. Since all the active signals PACT 15 - 5  are zero, the selector  90 - 15  selects the output of the preceding selector  90 - 14 . In the preceding selector  90 - 14 , all the active signals PACT 14 - 4  are also zero, so that the output of the preceding selector  90 - 13  is selected. The active signal PACT 1  having the value of 1 is used for signal selection only in the selector  90 - 11 , where the write signal W 1 - 3  is selected because of this PACT 1 . The write signal W 1 - 3  is for the third frame of the path  1 . This corresponds to the fact that A 1 - 15  is contained in the third frame.  
         [0162]    As can be known from the above description, the selector  90 - 15  ends up outputting the write signal W 1 - 3  which is passed over from the selector  90 - 11 . The write signal W 1 - 3  prompts the  15 -th D-FF  83  to be in a write-enable condition. The rotation shifter  82  of FIG. 12 performs no rotation shift in this case, so that the signaling signal A 1 - 15  (bit b 7 ) of the path  1  is stored in the  15 -th D-FF  83  via the output line S 7 .  
         [0163]    In this manner, the outputs of the rotation shifter  82  of FIG. 12 are written in the D-FFs  83  based on the write signal WA 1  through WA 30  generated by the write-control unit  81  of FIG. 14. This achieves appropriate allocation of the signaling signals to the terminal-output time slots in the signaling multiplex mode, thereby generating the multiplexed-signaling signals SIGA 30 - 1 .  
         [0164]    In general, the write signal WAn for path n (n-th time slot on the side of the terminal) can be generated by a selector which has {(n-1)/(the number of signaling signals in one frame of the signaling-purpose time slot)+2} inputs. In the example of FIG. 14, the number of signaling signals in one frame is five (bit b 3  through bit b 7 ), so that the selector  90 - 15  for outputting WA 15  has 4 inputs (i.e., {(15-1)/5 +2} inputs).  
         [0165]    [0165]FIG. 15 is a block diagram of a selector shown in FIG. 14. FIG. 15 shows a configuration of the selector  90 - 20  as an example.  
         [0166]    The selector  90 - 20  of FIG. 15 includes a 2-input selector  101  and  3 -input selectors  102 - 1  through  102 - 3 . The  2 -input selector  101  receives the output WA 19  of the selector  90 - 19  shown in FIG. 14, and further receives the write signal W 5 - 4 . As a selection-control signal, the active signal PACT 5  is also supplied to the 2-input selector  101 . As shown in FIG. 15, one of the write signals W 5 - 4  and WA 19  is selected based on the value of the active signal PACT 5 .  
         [0167]    The 3-input selectors  102 - 1  through  102 - 3  receive, as three inputs thereof, the output WA 19  of the selector  90 - 19  shown in FIG. 14, an output of a respective preceding selector of FIG. 15, and a corresponding one of the write signals W 10 - 3 , W 15 - 2 , and W 20 - 1 . As shown in FIG. 15, one of these three inputs is selected in accordance with a bit pattern of corresponding active signals PACT.  
         [0168]    [0168]FIG. 16 is a block diagram showing a generalized configuration of a selector shown in FIG. 14.  
         [0169]    As shown in FIG. 16, a selector  90 -n includes selectors  110 - 1  through  110 -i. The number i of the selectors is determined as {(n-1)/(the number of signaling signals in one frame of the signaling-purpose time slot)+1}. Among the i selectors, only the leftmost selector  110 -i is a 2-input selector. Others are 3-input selectors. The selector  90 - 20 , for example, can be implemented by using four selectors (i.e., {( 20 - 1 )/ 5  + 1 } selectors).  
         [0170]    Based on the configuration of FIG. 16, any one of the selectors  90 - 1  through  90 - 30  of FIG. 14 can be implemented by using a 2-input selector and 3-input selectors.  
         [0171]    [0171]FIG. 17 is a block diagram showing another configuration of a selector shown in FIG. 14. FIG. 17 shows a configuration of the selector  90 - 20  as an example.  
         [0172]    The selector configuration shown in FIG. 15 has room for improvement since a selector of each stage receives the write signal WA 19  from the preceding selector  90 - 19 . A selector of FIG. 17 has a configuration in which only the leftmost selector receives the write signal WA 19 , so that all the selectors can be comprised of a 2-input selector.  
         [0173]    The selector  90 - 20  of FIG. 17 includes 2-input selectors  121  through  124 . The leftmost 2-input selector  121  receives the output WA 19  of the selector  90 - 19  of FIG. 14 and the write signal W 5 - 4  as two inputs thereof. As selection-control signals, the active signals PACT 20 - 5  are supplied. As shown in FIG. 17, one of the write signals W 5 - 4  and WA 19  is selected based on a bit pattern of the active signals PACT 20 - 5 .  
         [0174]    The 2-input selectors  122  through  124  receive, as two inputs thereof, an output of a respective preceding-stage selector and a corresponding one of the write signals W 10 - 3 , W 15 - 2 , and W 20 - 1 . As shown in FIG. 17, one of these two inputs is selected in accordance with a bit pattern of corresponding active signals PACT.  
         [0175]    [0175]FIG. 18 is a block diagram showing a variation of the selector  90 - 20  shown in FIG. 17.  
         [0176]    Each of the selectors  121  through  124  shown in FIG. 17 makes a signal selection based on active signals regarding a corresponding path and following paths (i.e. paths having a larger path number than the corresponding path). What matters with regard to the active signals for the following paths is whether all the bits thereof are zero. Because of this, it is inefficient to supply active signals regarding the following paths to a selector of each stage. In the configuration of FIG. 18, thus, circuits are provided with an aim of checking whether all the bits of the active signals are zero, thereby achieving a more straightforward configuration.  
         [0177]    The selector  90 - 20  of FIG. 18 includes 2-input selectors  131  through  134  and zero-check circuits  135  through  138 . The leftmost  2 -input selector  131  receives the output WA 19  of the selector  90 - 19  of FIG. 14 and the write signal W 5 - 4 . As a selection-cotnrol signal, an output of the zero-check circuit  135  is supplied. As shown in FIG. 18, one of the write signals W 5 - 4  and WA 19  is selected based on a combination of the active signal PACT 5  and a signal ZI, which is received from the zero-check circuit  136  provided at the following stage.  
         [0178]    The 2-input selectors  132  through  134  receive the output of a respective preceding-stage selector and a corresponding one of the write signals W 10 - 3 , W 15 - 2 , and W 20 - 1 . As a selection-control signal, an output of a corresponding one of the zero-check circuits  136  through  138  is supplied. As shown in FIG. 18, one of the two input signals is selected based on a combination of a 1-bit information of a corresponding active signal PACT and a signal ZI input to the corresponding zero-check circuit. As an exception, however, the 2-input selector  134  makes an input selection by using only a 1-bit information of a corresponding active signal PACT 20 .  
         [0179]    The zero-check circuit  138  receives the active signals PACT 20 - 16 , and outputs “0” to the preceding zero-check circuit  137  if all the bits of the active signals PACT 20 - 16  are zero. If all the bits are not zero, the preceding zero-check circuit  137  receives “1”.  
         [0180]    The zero-check circuits  136  and  137  receive active signals PACT 10 - 6  and PACT 15 - 11 , respectively. If all the bits of the corresponding active signals and the input ZI from the following zero-check circuit are 0, an output of “0” is supplied to the preceding zero-check circuit. If there is at least one bit which is 1, an output of “1” is supplied to the preceding zerocheck circuit.  
         [0181]    The zero-check circuit  135  receives the active signal PACT 5  and a signal from the following zero-check circuit  136 , and supplies a selection-control signal to the selector  131  in accordance with these signals.  
         [0182]    [0182]FIG. 19 is a block diagram of a generalized configuration of a selector shown in FIG. 18.  
         [0183]    As shown in FIG. 19, a selector  90 -n includes i 2-input selectors  140 - 1  through  140 -i and i zero-check circuits  150 - 1  through  150 -i. The number i of the 2-input selectors and the zero-check circuits is determined as {(n-1)/(the number of signaling signals in one frame of the signaling-purpose time slot)+1}. The selector  90 - 20 , for example, is implemented by using four 2-input selectors and four zero-check circuits (i.e., {(20-1)/5+1} 2-input selectors and {(20-1)/ 5+1} zero-check circuits).    
         [0184]    Based on the configuration of FIG. 19, any one of the selectors  90 - 1  through  90 - 30  of FIG. 14 can be implemented by using 2-input selectors.  
         [0185]    The above description has been provided with regard to a system which generates the terminal-output data according to the principle of the present invention. In the following, issues on enhancement of reliability of such a system will be described.  
         [0186]    In a communication system such as the system described above, two transmission routes are generally provided in order to enhance reliability of the communication line. In FIG. 1, these two transmission routs are shown as #0-route HW and #1-route HW. With the two transmission routes put in place, errors occurred in a route of current use can be escaped by switching to the other route.  
         [0187]    In the case of a point-to-point communication format, the switching of the routes can be performed with regard to all the data of one frame since there is only one partner to communicate. A circuit configuration to achieve the switching of the routes can be relatively simple. In the case of a point-to-multipoint communication format as shown in FIG. 1 where there are a plurality of parties to communicate, a route switch must be made with respect to each different path since data are multiplexed in the terminal output with regard to a plurality of communication parties. A communication baud rate may vary for each path, so that the circuit for achieving the switching of the routes is likely to be complex and of a large scale.  
         [0188]    In such a communication system as described in a previous part of this specification, further, functions to insert and/or check test patterns and conduct loop-back operations are provided for the purpose of testing the system. In the case of a point-to-point communication format, the insertion/check of test patterns and the loop-back operations can be performed with regard to all the data of one frame since there is only one partner to communicate. A circuit configuration to achieve this can be relatively simple. In the case of a point-to-multipoint communication format as shown in FIG. 1 where there are a plurality of parties to communicate, the insertion/check of test patterns and the loop-back operations must be performed only with respect to a particular path since data are multiplexed in the terminal output with regard to a plurality of communication parties. A communication baud rate may vary for each path, so that the circuit for achieving this is likely to be complex and of a large scale.  
         [0189]    Accordingly, there is a need for a small-scale circuit which can switch the routes with respect to each path when the paths are provided in an order of free choice on the side of the communication lines in a system employing a point-to-multipoint connection and an adjustable communication baud rate.  
         [0190]    Further, there is a need for a small-scale circuit which inserts and/or checks a test pattern with respect to a particular path when the paths are provided in an order of free choice on the side of the communication lines in a system employing a point-to-multipoint connection and an adjustable communication baud rate.  
         [0191]    In the following, a circuit configuration which switches the routes with respect to each different path will be described according to the present invention.  
         [0192]    When two transmission routes #0-route HW and #1-route HW are put in place, the system shown in FIG- 6  is provided for each of the routes, so that two sets of terminal outputs are obtained. The two sets of terminal outputs (outputs from the P/S-conversion unit) need to be subjected to path-wise selection.  
         [0193]    [0193]FIG. 20A is a block diagram of a timing-generation circuit, and FIG. 20B is a block diagram of a configuration which makes a route selection based on timing signals generated by the timing-generation unit.  
         [0194]    A timing-generation circuit  200  of FIG. 20A includes a terminal-TS-counter unit  201 , a baud-rateselector unit  202 , an active-signal-selector unit  203 , a path-timing-signal-generation unit  204 , an active-TScounter-control unit  205 , and an active-TS-signal-generation unit  206 .  
         [0195]    [0195]FIG. 21 is a circuit diagram showing detailed configurations of the terminal-TS-counter unit  201 , the path-timing-signal-generation unit  204 , the active-TS-counter-control unit  205 , and the active-TS-signalgeneration unit  206  of FIG. 20A.  
         [0196]    The terminal-TS-counter unit  201  counts  32  terminal TSs (time slots) by starting at the input of the frame pulse FP. Since 1 TS is comprised of 8 bits, a 3-bit TS counter  222  and a TS address counter  221  are used. The TS address counter  221  outputs a TS-address signal TSOA, which is supplied to the baud-rateselector unit  202  and the active-signal-selector unit  203 . Further, the TS-address signal TSOA is supplied to an increment unit  227 , where the address is incremented by 1. The reason to increment the address is that since path identifications are provided as time-slot addresses  1  through  32 , the TS-address-signal TSOA ranging from 0 to 31 needs to be converted to count numbers ranging from 1 to 32. An output of the increment unit  227  is supplied to a D-FF (flip-flop)  225 , which then outputs a TS-address signal TSA. The TS-address signal TSA is delayed by one clock cycle behind the TS-address signal TSOA.  
         [0197]    An output of the 3-bit TS counter  222  is provided to a decoder  223 . The decoder  223  changes an output signal cnt 7  thereof to HIGH when the input thereto becomes 7. The signal cnt- 7  and the frame pulse FP are supplied to a D-FF  226  via an OR circuit  224 . In response, the D-FF  226  generates a TS-timing signal TSTIM which is a pulse signal indicating- a start of each terminal TS (time slot). The TS-timing signal  
         [0198]    TSTIM is supplied to the path-timing-signal-generation unit  204  and the active-TS-counter-control unit  205 .  
         [0199]    The baud-rate-selector unit  202  selects a baud rate with respect to each path based on the TSaddress signal TSOA. Path baud rates are given as baud-rate signals BR: 30 - 1 , and a baud rate of a selected path is output as a baud-rate signal BRS. Path  1  is selected when TSOA is equal to 0, and path  2  is selected when TSOA is equal to 1. The same applies in the case of path  3 , path  4 , and so on, with path  30  being selected when TSOA is equal to 29. When TSOA is either 30 or 31, the baud-rate signal BRS becomes zero. Namely, for example, path  1  is selected with respect to the first time slot, and path  2  is selected with respect to the second time slot.  
         [0200]    The active-signal-selector unit  203  selects an active signal with respect to each path based on the TS-address signal TSOA. Active signals indicative of an active status of respective paths are given as active signals ACT: 30 - 1 , and an active signal of a selected path is output as an active signal ACTS. Path  1  is selected when TSOA is equal to 0, and path  2  is selected when TSOA is equal to 1. The same applies in the case of path  3 , path  4 , and so on, with path  30  being selected when TSOA is equal to 29. When TSOA is either 30 or 31, the active signal ACTS becomes zero. Namely, for example, path  1  is selected with respect to the first time slot, and path  2  is selected with respect to the second time slot.  
         [0201]    The path-timing-signal-generation unit  204  generates a pulse signal indicating a start of a valid path by using mainly the baud-rate signal BRS and the TS-timing signal TSTIM. The path-timing-signal-generation unit  204  includes a decoder  231 , an AND circuit  232 , a zero-check circuit  233 , an inverter circuit  234 , an AND circuit  235 , D-FFs  236 , and D-FFs  237 .  
         [0202]    According to the present invention, path n is supposed to be output by starting at the n-th TS (time slot). With respect to the n-th TS, the baud rate of the path n is selected as the baud-rate signal BRS, so that a check can be made whether the path is valid or invalid based on whether the baud-rate signal BRS is zero. An output of the inverter circuit  234  becomes TRUE when a given path is valid (i.e., BRS is not zero). By performing an AND-logic operation between the output of the inverter circuit  234  and the TS-timing signal TSTIM, a path-timing signal PATHTIM is generated so as to indicate a start of a valid path.  
         [0203]    Based on decoding results of the TS-address signal TSOA and the path-timing signal PATHTIM, the AND circuit  232  and the D-FFs  236  generate valid-path-start-indicator signals TIMPATH: 30 - 1  indicating a start of a valid path with respect to each path.  
         [0204]    The D-FFs  237  generates a signal PATHTIM 2  which is delayed by 2 clock cycles behind the pathtiming signal PATHTIM.  
         [0205]    Based on the active signal ACTS and the TS-timing signal TSTIM, the active-TS-counter-control unit  205  generates a load signal CNTLO and a count-enable signal CNTEN supplied to the active-TS-signalgeneration unit  206 . The active-TS-counter-control unit  205  includes a zero-check circuit  241 , a NOT circuit  242 , and AND circuits  243  and  244 . The load signal CNTLO is generated by the AND circuit  243  when both the active signal ACTS and the TS-timing signal TSTIM are both 1. That is, the load signal CNTLO becomes HIGH at a start of TS of an active path. The count-enable signal CNTEN is generated by the AND circuit  244  when the active signal ACTS is 0 and the TS-timing signal TSTIM is 1. That is, the count-enable signal CNTEN becomes HIGH at a start of TS of an inactive path.  
         [0206]    The active-TS-signal-generation unit  206  includes a baud-rate counter  251  and a non-zero-check circuit  252 . In the present invention, a baud rate and an active setting are provided with respect to each path. Basically, the system of the present invention is operable by solely depending on the baud rate settings. There is a need, however, to mask received data of paths which are set to be inactive. To this end, a signal indicating a active-TS period become necessary.  
         [0207]    The baud-rate counter  251  loads the baud-rate signal BRS in response to the load signal CNTLO, and counts down a counter output in response to the count-enable signal CNTEN, thereby generating an active-TS signal TSACT. When the non-zero-check circuit  252  finds that the counter output is not zero, the active-TS signal TSACT becomes TRUE.  
         [0208]    The signals generated by the configurations of FIG. 20A and FIG. 21 described above are used by the configuration of FIG. 20B to make a path selection.  
         [0209]    The path selection is made with respect to each path at a timing indicated by the valid-path- start-indicator signals TIMPATH: 30 - 1  when error signals regrading the #0 route or the #1 route are provided in synchronism with the received data. When either the #0 route or the #1 route suffers an error, a switch is made to the other route.  
         [0210]    The route-determination/mask-signal-generation unit  211  is provided for each path, and generates a mask signal to mask received data when a route switch is made. Since two sets of identical data are input as received data with respect to the #0 route and the #1 route, some type of terminals may experience a hang-up when receiving the identical sets of data unless data masking is performed. The mask signal for preventing double reception of data is generated for a predetermined period of time counted by a built-in timer after detecting a switch of route-determination signals. The route-determination/mask-signal-generation unit  211  generates route-determination signals RUTE: 30 - 1  for the 30 paths and mask signals MASK: 30 - 1  also for the 30 paths. A configuration of the route-determination/mask-signal-generation unit  211  is the same as that of the prior art, and a description thereof will be omitted.  
         [0211]    A parallel/serial-conversion unit  212  converts the route-determination signals RUTE: 30 - 1  and the mask signals MASK: 30 - 1  into serial signals which are in synchronism with the received data.  
         [0212]    [0212]FIG. 22 is a block diagram of the parallel/serial-conversion unit  212 . The parallel/serial-conversion unit  212  of FIG. 22 includes a D-FF  261  and selectors  262  and  263 . The selectors  262  and  263  select one signal from the 30 signals. The D-FF  261  latches the TS-address signal TSA in response to the signal PATHTIM 2  indicating a start of each valid path, and supplies an output thereof to the selectors  262  and  263 . The selectors  262  and  263  perform the parallel-to-serial conversion by successively selecting one of the route-determination signals RUTE: 30 - 1  and one of the mask signals MASK: 30 - 1 , respectively, in response to the TS-address signal TSA latched by the DFF  261 .  
         [0213]    With reference to FIG. 20B again, a data-selection/mask-processing unit  213  attend to the selection and mask processing of the received data with respect to the #0 route and the #1 route. This is performed based on the route-determination signal RUTE and the mask signal MASK obtained after the parallel-to-serial conversion. Further, the dataselection/mask-processing unit  213  applies mask processing to the received data based on the active-TS signal TSACT. The data-selection/mask-processing unit  213  has the same configuration as that of the prior art, and a description thereof will be omitted.  
         [0214]    [0214]FIGS. 23A through 23Y are timing charts showing route-selection operations performed by the configurations of FIGS. 20A and 20B. Functional ramifications and operations of signals shown in the timing charts should be found by referring to the previous descriptions. A case shown in FIGS. 23A through 23Y assumes that paths  1 ,  3 ,  5 , and  7  have a baud rate of  2 , and paths  1 ,  5 , and  7  are active while path  3  is inactive. As shown in the figures, a path-wise selection can be made with regard to terminal outputs of the two routes.  
         [0215]    In the following, a circuit configuration for performing the insertion/check of test patterns with respect to a particular path will be described according to the present invention.  
         [0216]    As previously described, there is a need to perform the insertion/check of test patterns with respect to a particular path when data after the serial conversion is output from the P/S-conversion unit shown in FIG. 6.  
         [0217]    [0217]FIG. 24A is a block diagram of a test-control unit, and FIG. 24B is a block diagram of a configuration which performs the insertion/check of test patterns based on timing signals generated by the test-control unit.  
         [0218]    The test-control unit  300  of FIG. 24A includes a terminal-TS-counter unit  301 , a baud-rate-selector unit  302 , a path-timing-signal-generation unit  303 , a valid-TS-signal-generation unit  304 , and a.testinsertion/check-signal-generation unit  305 .  
         [0219]    [0219]FIG. 25 is a circuit diagram showing detailed configurations of the terminal-TS-counter unit  301 , the path-timing-signal-generation unit  303 , and the valid-TS-signal-generation unit  304  of the test-control unit  300  shown in FIG. 24A. As is apparent from a comparison with the configuration of FIG. 21, the terminal-TS- counter unit  301 , the path-timing-signal-generation unit  303 , and the valid-TS-signal-generation unit  304  of FIG. 25 have the same configurations as those of the terminal-TS-counter unit  201 , the active-TS-counter-control unit  205 , and the active-TS-signal-generation unit  206  of FIG. 21, respectively, and a detailed description thereof will be omitted.  
         [0220]    The active-TS-counter-control unit  205  of FIG. 21 generates the load signal CNTLO and the countenable signal CNTEN based on the active signal ACTS and the TS-timing signal TSTIM. In contrast, the pathtiming-signal-generation unit  303  of FIG. 25 generates the path-timing signal PATHTIM (identical to that of FIG. 21) indicating a start of each valid path and the count-enable signal CNTEN indicating a start of each invalid path. The generation of these signals is effected based on the baud-rate signal BRS and the TS-timing signal TSTIM.  
         [0221]    Further, a valid-TS signal TSEN output from the valid-TS-signal-generation unit  304  is generated by loading the baud-rate signal BRS in response to the path-timing signal PATHTIM and counting down a counter output in response to the count-enable signal CNTEN. When the counter output is found to be non-zero, the valid-TS signal TSEN becomes TRUE. The valid-TS signal TSEN serves to indicate a valid-time-slot period.  
         [0222]    [0222]FIG. 26 is a circuit diagram of the test-insertion/check-signal-generation unit  305  shown in FIG. 24A.  
         [0223]    The test-insertion/check-signal-generation unit  305  of FIG. 26 includes a match-detection circuit  321 , D-FF  322 , and AND circuits  323  through  325 .  
         [0224]    The test-insertion/check-signal-generation unit  305  receives test-set signals and timing-control signals, and generates test-pattern-insertion/check signals based on these received signals. The test-set signals are set by register values, and includes a test-path-indication signal TESTPA, a test-insertion signal TSTEN, and a check signal CHKEN. The timing-control signals includes the TS-address signal TSA from the terminal-TS-counter unit  301 , the path-timing signal PATHTIM from the path-timing-signal-generation unit  303 , and the valid-TS signal TSEN from the valid-TS-signal-generation unit  304 . As previously described, the path-timing signal PATHTIM is a pulse signal indicating a start of each valid path.  
         [0225]    The match-detection circuit  321  compares the test-path-indication signal TESTPA with the TS-address signal TSA, and changes an output thereof to HIGH as a match-detection result when a match is found. The match-detection result is latched by the D-FF  322  at a timing of the path-timing signal PATHTIM. The value latched by the D-FF  322  is output as a test-path-span signal tpathO. Unfortunately, there are cases in which an unused time slot(s) is present between a pulse of the path-timing signal PATHTIM indicative of a start of a valid path and a next pulse of the path-timing signal PATHTIM indicative of a start of a next valid path. To cope with such a circumstance, the AND circuit  323  performs an AND-logic operation between the test-path-span signal tpathO and the valid-TS signal TSEN, thereby generating a test-path-span signal tpath indicating a correct test-path period.  
         [0226]    A test-pattern-generation signal GEN is generated by the AND circuit  324  performing an AND operation between the test-path-span signal tpath and the test-insertion signal TSTEN. Namely, the testpattern-generation signal GEN is generated to specify a test-path period only when the test insertion is indicated.  
         [0227]    A test-pattern-check signal CHK is generated by the AND circuit  325  performing an AND operation between the test-path-span signal tpath and the check signal CHKEN. Namely, the test-pattern-check signal CHK is generated to specify a test-path period only when a check operation is indicated.  
         [0228]    With reference to FIG. 24B again, the test-pattern-generation signal GEN is supplied to a testpattern-generation unit  311  and a terminal-output-selector unit  313 . The test-pattern-check signal CHK is supplied to a test-pattern-check unit  312 .  
         [0229]    The test-pattern-generation unit  311  generate a test pattern in synchronism with the clock signal when the test-pattern-generation signal GEN is HIGH. The test-pattern-generation unit  311  has a configuration the same as that of the prior art, and a description thereof will be omitted.  
         [0230]    The test-pattern-check unit  312  compares the received data with the test pattern in synchronism with the clock signal when the test-pattern-check signal CHK is HIGH, thereby checking errors. A configuration of the test-pattern-check unit  312  is the same as that of the prior art, and a description thereof will be omitted.  
         [0231]    The terminal-output-selector unit  313  selects the test pattern provided from the test-pattern-generation unit  311  to output the same as terminal-output data when the test-pattern-generation signal GEN is HIGH. When the test-pattern-generation signal GEN is LOW, the received data is selected, and is output as the terminal-output data. The terminal-output-selector unit  313  has the same configuration as that of the prior art, and a description thereof will be omitted.  
         [0232]    [0232]FIGS. 27A through 27Q are timing charts showing the test-insertion/check operations which are performed by the configurations of FIGS. 24A and 24B. The descriptions provided in the above should be referred to with regard to functional ramifications and behaviors of these signals shown in FIGS. 27A through 27Q. An example shown in the figures is a case in which paths  1  and  4  have baud rates 2 and 10, respectively, and other paths have a zero baud rate. In this example, the test-path setting is made to the path  1 . As shown in FIGS. 27A through 27Q, the insertion/check of test patterns are carried out only with respect to a particular path.  
         [0233]    In this manner, the present invention achieves the switching of routes with respect to each different path by using a relatively simple process and a relatively small circuit size. Further, the present invention achieves the insertion of a test pattern and/or the checking of errors with respect to a particular path by using a relatively simple process and a relatively small circuit size.  
         [0234]    Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.