Abstract:
A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     (Not Applicable) 
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH 
     (Not Applicable) 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is directed generally to a semiconductor raised source-drain structure and, more particularly, to a semiconductor raised source-drain structure with gate side gaps and pocket junctions. 
     2. Description of the Background 
     Raised source and drains have been demonstrated in submicron semiconductor devices. In contrast to conventional source and drains, raised source and drains are vertical structures formed on top of the substrate instead of implanted structures in the substrate surface. Thin film structures are typically inserted between the sidewalls of the gate and the top regions of the raised source and drains to isolate the gate from the source and drains. Such an isolation arrangement, however, can cause excessive capacitive loading from gate to source and drain. 
     Devices incorporating raised source and drains typically include implanted n-regions under the source and drain regions to create conductive channels between the gate and the source and drains. Such channels do not have good drive and punchthrough capabilities. Also, it is difficult to implant the conductive channels after the polysilicon pattern defining the source and drain structures. 
     Thus, there is a need for a semiconductor device with raised source and drains that has improved series resistance, good I DS  currant drive, improved punchthrough leakage, and reduced sidewall capacitance that can be fabricated using standard fabrication techniques. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a fin gap between the gate and the source and a second gap between the gate and the drain. 
     The present invention represents a substantial advance over prior raised source and drain structures. The present invention has the advantage that it improves the sidewall decoupling of the raised source-drain to the polysilicon gate. In one embodiment, the present invention also has the advantage that it connects the source and drain to the pocket junction next to the gate edge with a high dose implant for reduced series resistance. In another embodiment, the present invention has the fiber advantage that the full CMOS process flow is seduced compared to typical raised source-drain CMOS process flows by making raised source-drain structures of n+ and p+ polysilicon with respective pocket junctions by implantation. The present invention also has the advantage that conductive source and drain structures can be placed closer to the polysilicion gate, thereby reducing the size of the structure. The present invention also has the advantage that implanted areas between the gate and source and drain structures can be fabricated using conventional semiconductor processing techniques. The present invention has the farther advantage that current may move from the implanted areas to the raised source and drain structures with minimal resistance. Those and other advantages and benefits of the present invention will become apparent from the description of the preferred embodiments hereinbelow. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     For the present invention to be clearly understood and readily practiced, the present invention will be described in conjunction with the following figures, wherein: 
     FIG. 1 is a cross-sectional view, of a substrate assembly at an early stage of the fabrication process of the present invention; 
     FIG. 2 is a cross-sectional view of the substrate assembly of FIG. 1 after portions of the sacrificial layer have been removed; 
     FIG. 3 is a cross-sectional view of the substrate assembly of FIG. 2 after portions of the oxide layer have been removed; 
     FIG. 4 is a cross-sectional view of the substrate assembly of FIG. 3 after it has been subject to mechanical abrasion to remove portions of the polysilicon layer; 
     FIG. 5 is a cross-sectional view of the substrate assembly of FIG. 4 after the polysilicon layer has been patterned; 
     FIG. 6 is a cross-sectional view of the substrate assembly of FIG. 5 after a conductive layer has been formed; 
     FIG. 7 is a cross-sectional view of the substrate assembly of FIG. 6 after portions of the conductive layer have been removed; 
     FIG. 8 is a cross-sectional view of the substrate assembly of FIG. 7 after a nonconformal capping layer has been deposited; 
     FIG. 9 is a is a cross-sectional view of the substrate assembly of FIG. 8 after an insulative layer has been deposited and the substrate assembly has been subject to a mechanical abrasion process; 
     FIG. 10 is a cross-sectional view of the substrate assembly of FIG. 9 after contact areas have been patterned and plugs have been formed; 
     FIG. 11 is a cross-sectional view of the substrate assembly of FIG. 10 after metal layers have been formed and patterned; 
     FIG. 12 illustrates a semiconductor device in which the present invention may be employed; and 
     FIG. 13 is a block diagram illustrating a computer system. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements and process steps that are relevant for a clear understanding of the present invention while eliminating, for purposes of clarity, other elements and process steps found in a typical semiconductor topography. For example, specific methods and steps of removing layers or portions of layers using techniques such as lithography and etching are not described. Those of ordinary skill ill the art will recognize that other elements and process steps are desirable and/or required to produce an operational device incorporating the present invention. However, because such elements and process steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and process steps is not provided herein. 
     FIG. 1 is a cross-sectional view of a substrate assembly  10  at an early stage of the fabrication process of the present invention. The substrate assembly  10  includes a substrate layer  12 , which is the lowest layer of semiconductor material on a wafer, and additional layers or structures formed thereon. Layers of oxide  14  are formed on the substrate layer  12  to create field oxide regions  16  and gate oxide region  18 . The gate oxide region  18  can be, for example, 40 Å thick. The oxide layers  14  can be formed using any conventional process such as, for example, any form of a shallow trench isolation process or any form of a LOCOS process. A polysilicon layer  20  is formed, typically by deposition, and patterned using, for example, a lithography and etch process to provide a gate terminal of a transistor. The layer  20  can extend over the field to form a terminal for interconnect or may be limited to extending over an active channel area. The formation of the polysilicon layer  20  may include deposition of polysilicon by a chemical vapor deposition (CVD) process followed by an ion implantation of a dopant, such as phosphorous, to dope the polysilicon layer  20 . 
     A sacrificial layer  22  is formed on the substrate assembly  10 . The sacrificial layer  22  can be any type of dielectric material that is not difficult to remove using typical semiconductor processing techniques such as, for example, a thin layer of a nitride, a photoresist layer, a layer of a polyimide, or a layer of a spin on glass (SOG) material. The sacrificial layer  22  can be deposited by a CVD process or by a spin deposition process and if the layer  22  is applied in a liquid form, it can be baked to form a solid. 
     FIG. 2 is a cross-sectional view of the substrate assembly  10  of FIG,  1  after portions of the sacrificial layer  22  have been removed. Spacers  24  of the sacrificial layer  22  remain after the removal step. The spacers may be rectangular in shape or may have a curve shape. Portions of the sacrificial layer may be removed using a standard removal technique such as, for example, plasma etching or lithography and etching. 
     FIG. 3 is a cross-sectional view of the substrate assembly  10  of FIG. 2 after portions of the oxide layers  14  have been removed by a removal process such as, for example, a lithography and etching process. The field oxide regions  16  and the gate oxide regions  18  remain after the removal step. A polysilicon layer  26  is formed on the substrate assembly  10 , such as by a CVD process. 
     FIG. 4 is a cross-sectional view of the substrate assembly  10  of FIG. 3 after it has been planarized, such as by mechanical abrasion, to remove portions of the polysilicon layer  26 . The mechanical abrasion may be performed by a technique such as, for example, chemical mechanical polishing (CMP). The substrate assembly  10  is substantially planar after the planarization. 
     FIG. 5 is a cross-sectional view of the substrate assembly  10  of FIG. 4 after the polysilicon layer  26  has been patterned by, for example, a lithography and etch process. Raised areas  28  and  30  of the polysilicon layer  26  may be raised source and drain regions, respectively, of a transistor. 
     FIG. 6 is a cross-sectional view of the substrate assembly  10  of FIG. 5 after a conductive layer  32  is formed. The conductive layer  32  acts as a conductive path which carries excess charge built up from the ion implantation process off of the wafer, which is connected to an electrical ground. The conductive layer  32  can be any type of conductor suitable for use in a semiconductor such as, for example, titanium silicide or titanium. The substrate assembly  10  is then masked (not shown) and n+ or p+ dopants are implanted into the polysilicon layer  20  and the raised areas  28  and  30  depending on the type of device being fabricated. The dopants may be, for example, phosphorous, arsenic, or boron atoms. 
     FIG. 7 is a cross-sectional view of the substrate assembly  10  of FIG. 6 after portions of the conductive layer  32  have been removed The portions of the conductive layer  32  can be removed by, for example, a lithography and etch process. Although certain portion of the conductive layer  32  are shown, the lithography and etch process may eliminate more or less of the conductive layer  32  than is shown in FIG. 7 depending on variations in fabrication processes and depending on whether a mask is used in the etch process. The amount of the conductive layer  32  that is removed does not affect the resultant substrate assembly  10 . The spacer areas  24  are also removed by a process such as etching to create gaps  34 . The gaps  34  may be 100 to 100 Å wide, depending on the height of the polysilicon layer  20  and the raised areas  28  and  30 . The gaps  34  may be filled with a gas such as, for example, nitrogen, argon, oxygen, or a mixture of such gases (air). A vacuum may also be created in the gaps  34 . 
     The substrate assembly  10  may be masked and blankets of n+ or p+ dopants may be implanted, depending on he type of device being fabricated, beneath the gaps  34  and into the substrate lager  12  to create pocket implant junction areas  36 , which extend partially under the polysilicon layer  20  and the raised areas  28  and  30 . The areas  36  thus create low series resistance paths. The n+ blanket implant diffuses into the p-channel but is counterdoped by the p+ blanket implant The excess dopant thus acts as a p-channel punchthrough halo implant. The doping process of the polysilicon layer  20  and the raised areas  28  and  30  as described in conjunction with FIG. 6 creates negatively doped outdiffusion areas  38 . The outdiffusion areas  38  may be 50 to  200 Å thick.    
     The substrate assembly  10  is subject to a low temperature RTP sinter process. Portions of the conductive layer  32  are converted to a nitride by the sinter process. The substrate is then subjected to a lithography and etch process to remove some of the nitride in the conductive layer  32 . The substrate assembly  10  is then subject to an RTP anneal process. The anneal process causes the conductive layer  32  to become more dense and to better adhere to the substrate assembly  10 . 
     FIG. 8 is a cross-sectional view of the substrate assembly  10  of FIG. 7 after a nonconformal capping layer  40  has been deposited. The nonconformal layer  40  can be any type of insulative material suitable to seal the gaps  34  such as, for example, a deposited layer is of oxide. 
     FIG. 9 is a cross-sectional view of the substrate assembly  10  of FIG. 8 after an insulative layer  42  has been deposited and the substrate assembly  10  has been subject to a planarization process, such as mechanical abrasion. The mechanical abrasion may be performed by, for example, chemical mechanical polishing. The substrate assembly  10  is substantially planar after the planarization. The layer  42  may be a material such as doped oxide that is formed by a CVD process. Such doped oxide may be, for example, phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). 
     FIG. 10 is a cross-sectional view of the substrate assembly  10  of FIG. 9 after contact areas have been patterned by, for example, a lithography and etch process, and plugs  44  have been formed. The plug areas  44  may consist of any type of material suitable such as, for example, aluminum, copper, or tungsten. An adhesion layer  45  may be deposited in the contact areas to promote adhesion of the plugs  44  to the conductive layer  32 , the polysilicon layer  20 , and the raised areas  28  and  30 ., The adhesion layer may be a material such as, for example, Ti, TiW, TiN, WSi x , Ti/TiN, Ti/Cu, Cr/Cu, TiN/Cu, or Ta/Cu. 
     FIG. 11 s a cross-sectional view of the substrate assembly  10  of FIG. 10 after metal layers  46  have been formed and patterned. The metal layers  46  may be constructed of any material suitable for semiconductor interconnect structures such as, for example, aluminum or copper, The metal layers way be formed by, for example, a CVD process, by electroplating, or by electroless plating. Further metal layers may be formed on the substrate assembly  10  to from an interconnect structure. Such metal layers are not illustrated in FIG.  11 . 
     FIG. 12 illustrates a semiconductor device  48  in which the present invention may be employed. The semiconductor device  48  may be any type of solid state device such as for example, a memory device. 
     FIG. 13 is a block diagram illustrating a computer system  50 . The system  50  utilizes a memory controller  52  in communication with RAMs  54  through a bus  56 . The memory controller  52  is also in communication with a processor  58  through a bus  60 . The processor can perform a plurality of functions based on information and data stored in the RAMs  54 . One or more input devices  62 , such as, for example, a keypad or a mouse, are connected to the processor  58  to allow an operator to manually input data, instructions, etc. One or more output devices  64  are provided to display or otherwise output data generated by the processor  58 . Examples of output devices include printers and video display units. On or more data storage devices  66  may be coupled to the processor  58  to store data on, or retrieve information from, storage media. Examples of storage devices  66  and storage media include drives that accept hard and floppy disks, tape cassettes, and CD read only memories. The raised source-drain structures of the present invention can be incorporated in circuits on all of the devices in the system  50 . 
     While the present invention has been described in conjunction with preferred embodiments thereof, many modifications and variations will be apparent to those of ordinary skill in the art. The foregoing description and the following claims are intended to cover all such modifications and variations.