Abstract:
The present invention is a method and apparatus for mitigating phase noise in data communication systems. The present invention provides effective phase noise mitigation with very low latency by combining the decision feedback equalizer and carrier recovery loop effectively. The phase noise estimate is obtained by calculating the phase difference between the input and output of the decision device (DD) in the decision feedback equalizer (DFE) and then applying a digital phase locked loop (DPLL) on the phase difference. Deriving the phase noise estimate from the phase noise estimation process, phase noise mitigation is obtained by multiplying the phase noise estimate at the input signal of the feedforward filter (FFF) and at the input signal of the DD in DFE. An accurate signal-to-noise ratio (SNR) estimate is also obtained in the process of the filter coefficient update process in the DFE.

Description:
FIELD OF THE INVENTION 
     Phase noise is one of the most critically destructive noises affecting the performance of wireless high speed communication systems. In the general application area, a higher speed communication system requires the use of a higher order QAM (quadrature amplitude modulation) system. We need to use more accurate and more recently measured (i.e., low latency) phase noise estimates for a higher order QAM to mitigate the phase noise effect on the signal. The present invention provides an effective phase noise mitigation approach with good accuracy and very low latency. 
     DISCUSSION OF RELATED ART 
     The need to increase the channel data rate in data communication systems without increasing the signal bandwidth drives the development toward more spectrally efficient modulation formats. QAM modulation is widely used in digital wireless communication systems for achieving high data transmission rates over relatively narrow signal bandwidth. Digital radio systems designed using such modulation schemes must balance the effects of phase noise from local oscillators with the demodulator parameters in determining overall performance. In a M-QAM system each symbol transmitted contains k bits, where 2 k =M. In contrast, BPSK (binary phase shift keying) system transmits 1 bit per symbol and QPSK (quadrature phase shift keying) system transmits 2 bits per symbol while requiring the same RF (radio frequency) bandwidth for a given symbol rate. 
     The M states in a high order M-QAM constellations are more closely spaced than in BPSK or QPSK constellations and therefore require lower noise relative to the average carrier power to eliminate errors. The RMS (root mean square) phase noise of the local oscillators, after being filtered by demodulator, must be sufficiently low to not cause bit errors. For a QPSK or M-PSK schemes (or systems), a multitude of carrier recovery algorithms exist that provide a high phase noise tolerance. However, those algorithms fail when applied to most of the higher order QAM constellations because these lack equidistant phases. Additionally, it has been shown that most of decision-directed carrier recovery is also not a viable option for higher order QAM constellations due to the inevitable relatively long feedback delay (or latency) in practical systems. 
     The present invention provides a phase noise tolerant method with very low latency by combining the decision feedback equalizer (DFE) and the carrier recovery loop effectively. 
     REFERENCES 
     
         
         Cheng-I Hwang, David W. Lin, “Joint Low-Complexity Blind Equalization, Carrier Recovery, and Timing Recovery with Application to Cable Modem Transmission”, IECE Trans., Commun., Vol. E82-B, No. 1 Jan. 1999 
       
    
     SUMMARY OF THE INVENTION 
     The present invention is related to a method and apparatus for mitigating phase noise in data communication system. The present invention provides effective phase noise mitigation with very low latency by effectively combing decision feedback equalizer (DFE) and carrier recovery loop. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of the present invention. 
         FIG. 2  is a circuit diagram of the present invention. 
         FIG. 3  is a diagram of the present invention. 
     
    
    
     The following callout list of elements can be a useful guide in referencing the elements of the drawings.
       100  DD/Input Signal of the DFE u(n)     102  Multiplier/Phase Noise Compensator     103  Phase Noise Compensated Input Signal x(n)     104  FFF/Feed Forward Filter     106  Adder     107  Output Signal of the DFE q(n)     108  Multiplier/Phase Noise Compensator/Second Phase Noise Compensator     109  Phase Noise Compensated Signal/Input Signal Q(n)     110  The DD     112  Adder/Error Signal Calculator     113  Error Signal e(n)     114  Filter Coefficient Adaption Block     115  Step Size μ     116  Filter Coefficient Adaption Block     118 -FBF/Feedback Filter     120  Data Signal energy sample |{circumflex over (d)}(n)| 2        122  First Low Pass Filter     124  Error Energy Estimate of the Error Signal |e(n)| 2        126  Second Low Pass Filter     128  Output Signal of the DD {circumflex over (d)}(n)     212  DD Input Signal Normalizer     214  Phase Noise Calculator     216  Complex Conjugator Block/Complex Conjugator     218  Imaginary Part Selector Block/Imaginary Part Selector     220  Low Pass Filter     222  Adder     223  Symbol Delay Operator/Symbol Delay Block     226  Phase Noise Estimate/Phase Noise Estimate Block/Complex Number Conversion Block   

     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Glossary of Terms 
     Input Signal u(n): An input signal is a noisy signal that is the input of the phase noise compensator. The output of the phase noise compensator is the phase noise compensated input signal x(n). 
     Decision feedback equalizer (DFE): A DFE is a nonlinear equalizer that automatically adapts to time varying properties of the communication channel. It is frequently used in coherent modulation systems to mitigate the channel effect and the inter symbol interference in the received data.
 
Phase Noise Compensator: a complex multiplier that is used to reduce phase noise by multiplying the negative value of the phase noise estimate with the phase noisy signal.
 
Phase Noise Compensated Input Signal x(n): The phase noise compensated signal is obtained from the output of phase noise compensator. The phase noise compensated signal which is the input to the FFF in DFE is x(n).
 
Feedforward Filters (FFF): FFF consists of finite impulse response filter. FFF combines delayed versions of signals to mitigate the channel effect in the received input signal.
 
Adder: adds input signals together to produce an output signal.
 
Output Signal of the DFE q(n): a signal that outputs from the DFE. The output signal of the DFE, q(n), is used as the input of the phase noise compensator to generate DD input signal Q(n).
 
Phase Noise Compensated Signal: A signal after it is compensated for phase noise.
 
Decision Device (DD) Input Signal Q(n): A phase noise compensated signal from the phase noise compensator. It is an input signal that is received into a decision device.
 
Error Signal Calculator: an adder that calculates an error signal.
 
Error Signal e(n): The difference between the DD output and phase noise compensated DFE output.
 
Filter Coefficient Adaption Block: The function block updates the adaptive filter coefficient iteratively. The function block use the error signal, step size, and input signal of the each filter coefficient.
 
Step Size μ: a small proportional constant which is used in the Least Mean Squared (LMS) algorithm for adaptive filter coefficient update.
 
FBF/Feedback Filter: Feedback filter is a part of decision feedback equalizer. It is effective to mitigate inter symbol interference cancellation.
 
Data Signal Energy Sample: |{circumflex over (d)}(n)| 2 : Energy of data signal sample.
 
Low Pass Filter: A filter that allows low frequency to pass, but not high-frequency.
 
Error Signal Energy Sample |e(n)| 2 : Energy of the Error Signal sample.
 
Output Signal of the DD {circumflex over (d)}(n): An output signal from the decision device.
 
Input Signal Normalizer: Function block which divide the input signal by the energy of the input signal.
 
Phase Noise Calculator: A Multiplier that calculates phase noise sample.
 
Complex Conjugator Block: Function block which apply the conjugate function on the input complex signal.
 
Imaginary Part Selector Block: The function block which takes the imaginary part of the input complex signal.
 
Symbol Delay Operator: A block that introduces a symbol delay to a signal.
 
Phase Noise Estimate Block: A block that converts a phase noise estimate into a complex number using complex number conversion function.
 
Equalization
 
     Equalization is used to mitigate the channel effect on the signal for reliable communication. The equalizer estimates the communication channel distortion (such as amplitude distortion, phase distortion, fading, and interference, etc.) and mitigates the channel effect by compensating the channel distortion on the received signal. 
     In micro-wave or millimeter-wave communications that use high radio carrier frequency, the phase noise is high because the amount of phase noise is proportional to the carrier frequency used. In communication systems such as these, one of the most powerful solutions to fight against phase noise is to combine the equalizer with carrier recovery while exploiting the latency reduction between phase noise estimation and correction. 
     We use a fractional or symbol spaced decision feedback equalizer (DFE) to mitigate the channel effect and inter-symbol interference. The DFE consists of two sections in equalizer: one is Feed Forward Filter (FFF) and the other is Feedback Filter (FBF). Both the FFF and FBF consist of a finite impulse response (FIR) filter. 
       FIG. 1  is the function block diagram of the DFE which gets the phase noise estimate from carrier recovery loop. The input signal of the DFE, u(n)  100 , is the transmitted signal through the noisy communication channel from the transmitter and is the signal received at the receiver. This is a noisy signal. The output signal, q(n)  107 , of the DFE is the summation of the output signal of the FFF  104  and the output signal of the FBF  118  in the adder  106 . The output signal, {circumflex over (d)}(n)  128 , of the DD  110  is used in the decoder. 
     The phase noise correction (or compensation) is obtained by multiplying the respective input signal of the DFE, u(n)  100 , and the output signal, q(n)  107 , of the DFE with the negative value of the phase noise estimate  226 , which is obtained from the carrier recovery DPLL (digital phase locked loop) in the multipliers  102  and  108 , respectively. The multiplier  102  is the name of the hardware component and its function is a phase noise compensator. The phase noise compensated signal, Q(n)  109 , is the input of the DD  110 . The DD  110  uses the input signal, Q(n)  109 , to find its output from M QAM constellation by finding one of the M signal constellation points which is closest to the input signal, Q(n)  109 , and selects the closest signal point to Q(N)  109  as the output signal, {circumflex over (d)}(n)  128 , of the DD  110 . The error signalm, e(n)  113 , is obtained by subtracting the output signal, {circumflex over (d)}(n)  128 , from the input signal, Q(n)  109 , of the DD  110  in the adder  112 , which is the error signal calculator. 
     The error signal, e(n)  113 , the phase noise compensated input signal, x(n)  103 , and the step size, μ  115 , are used in the filter coefficient adaption block  114  to update the filter coefficient of the FFF  104 . The error signal, e(n)  113 , the output signal, {circumflex over (d)}(n)  128 , and the step size, μ  115  are used in filter coefficient adaption block  116  to update the filter coefficient of the FBF  118 . 
     Both the FFF  104  and the FBF  118  are asymmetric complex FIR filters. The least mean square (LMS) algorithm can be used to update the filter coefficients in both the FFF  104  and the FBF  118 . The step size (μ) used for the filter coefficient update in the LMS algorithm is programmable. 
     The filter coefficient adaption blocks of  114  and  116  performs filter coefficient update process based on the following procedures; 
     a) Calculate the output signal q(n)  107  of the DFE in the adder  106 ; 
               q   ⁡     (   n   )       =         ∑     k   =   1     K     ⁢         f   k     ⁡     (   n   )       ⁢       x   k     ⁡     (     n   -   k     )           +       ∑     l   =   1     L     ⁢         b   l     ⁡     (   n   )       ⁢         d   ^     l     ⁡     (     n   -   l     )                   
b) Calculate the phase noise compensated signal Q(n)  109 ;
 
 Q ( n )= q ( n ) e   −j{circumflex over (θ)}     n-Δ     ={circumflex over (d)}   n   e   j{circumflex over (θ)}     n    
 
where K and L are filter order of FFF and FBF, respectively, θ n-Δ  is the phase noise estimate obtained from carrier recovery loop, and {circumflex over (θ)} n , is the residual phase noise after phase noise compensation.
 
c) Generate the output signal, {circumflex over (d)}(n)  128 , of the DD  110  based on Q(n)  109  using the selection process mentioned above.
 
d) Calculate the error signal e(n)  113  by subtracting the output signal {circumflex over (d)}(n)  128  from the phase noise compensated input signal Q(n)  109 ;
 
 e ( n )= Q ( n )−{circumflex over ( d )}( n ),
 
e) Update the filter coefficients of the FFF  104  and FBF  118  using the LMS algorithm as follows;
 
 f   k ( n+ 1)= f   k ( n )+μ* e ( n )* x   k ( n ),  k= 1,2, . . . , K  
 
 b   l ( n+ 1)= b   l ( n )+μ* e ( n )* {circumflex over (d)}   l ( n ),  l= 1,2, . . . , L  
 
for FF filter and FB filter, respectively. Where f k (n) and f k (n+1) are present k th  FFF coefficient and next k th  FFF coefficient, respectively. The b l (n) and b l (n+1) are present l th  FBF coefficient and next l th  FBF coefficient, respectively. The x k (n) and {circumflex over (d)} l (n) are the input of filter coefficient of the k th  FFF and the input of l th  filter coefficient of the FBF, respectively.
 
     The signal to noise ratio (SNR) estimate is obtained by applying a time averaging first low pass filter (LPF)  122  on the data energy estimate, |{circumflex over (d)}(n)| 2    120 , of the data signal and by applying a time averaging second low pass filter (LPF)  126  on the error energy estimate, |e(n)| 2    124 , of the error signal using 1-pole IIR (infinite impulse response) filter as follows;
 
 S   2 ( n )=α S   2 =( n− 1)+(1−α){circumflex over ( d )}( n ){circumflex over ( d )}·( n )=α S   2 ( n− 1)+(1−α)|{circumflex over ( d )}( n )| 2  
 
 N   2 ( n )=α N   2 ( n− 1)+(1−α) e ( n ) e *( n )=α N   2 ( n− 1)+(1−α)| e ( n )| 2  
 
SNR=10*log 10( S   2 ( n )/ N   2 ( n )),
 
Where is S 2 (n) the signal energy, N 2 (n) is the noise energy, and a is an average parameter of the LPF  126 . The value of the α is 0&lt;α&lt;1 and is close to 1.
 
Carrier Recovery
 
       FIG. 2  is the function block diagram of the carrier recovery loop (CRL) combined with the part of the DFE that is designed for joint detection, estimation, and compensation of the phase noise. In  FIG. 2 , the carrier recovery loop consists of the multiplier (phase noise compensator)  108 , the DD  110 , the adder (error signal calculator)  112 , the complex conjugator  216 , DD input signal normalizer  212 , multiplier (phase noise calculator)  214 , imaginary part selector  218 , low pass filter  220 , the oscillator which consists of the adder  222  and one symbol delay operator  223 , and the phase noise estimator  226 . The CRL is a 2 nd  order type II digital phase locked loop (DPLL) operating at the symbol rate. The CRL tracks the phase error at the input of the DD  110  in the DFE. In  FIG. 2 , the part of DFE consists of the multiplier (phase noise compensator)  102 , the FFF  104 , the multiplier (phase noise compensator)  108 , the DD  110 , the adder (error signal calculator)  112 , and the FBF  118 . 
     The signal processing used to obtain the phase noise compensated signal Q(n)  109 , the output signal {circumflex over (d)}(n)  128 , and the error signal e(n)  113  from the input signal u(n)  100  in  FIG. 2  is the same as those explained above in DFE section. 
     The input signal u(n)  100  of the DFE is the signal transmitted through the noisy communication channel from the transmitter and is the received signal at the receiver, which is a noisy signal. The output signal q(n)  107  of the DFE is the summation of the output signal of the FFF  104  and the output signal of the FBF  118  in the adder  106 . The output signal {circumflex over (d)}(n)  128  of the DD  110  can be used in the decoder. 
     The phase noise correction (or compensation) is obtained by multiplying the respective input signal of the DFE, u(n)  100 , and the output signal of the DFE, q(n)  107 , with the negative value of the phase noise estimate  226 , which is obtained from carrier recovery DPLL (digital phase locked loop) in the multipliers  102  and  108 , respectively. The phase noise compensated signal, Q(n)  109 , is the input of the DD  110 . The DD  110  uses the input signal Q(n)  109  to find its output from M QAM constellation by finding one of the M signal constellation points which is closest to the input signal, Q(n)  109 , and selects the closest signal point to Q(N)  109  as the output signal  128 , of the DD  110 . The error signal e(n)  113  is obtained by subtracting the output signal {circumflex over (d)}(n)  128  from the input signal Q(n)  109  of the DD in the adder  112  (error signal calculator). a 3   
     The CRL uses the DD input Q(n)  109  and the error signal e(n)  113  to obtain the phase noise estimate. The CRL obtains the phase noise estimates based on the following procedure; 
     a) Obtain the input signal, x(n)  103 , of the FFF by performing the phase noise correction (or compensation) by multiplying the input signal, u(n)  100 , of the DFE with the negative value of the phase noise estimate  226  that is obtained from the carrier recovery DPLL (digital phase locked loop);
 
 x ( n )= u ( n ) e   −jθ 
 
b) Obtain the phase noise compensated input signal of the DD (DD input), Q(n)  109 , by performing the phase noise correction (or compensation) by multiplying the output signal, q(n)  107 , of the DFE with the negative value of the phase noise estimate  226  which is obtained from carrier recovery DPLL (digital phase locked loop);
 
 Q ( n )= q ( n ) e   −j{circumflex over (θ)}     n-     Δ={circumflex over (d)} ( n ) e   j{circumflex over (θ)}     n    
 
where {circumflex over (θ)} n-Δ  is the phase noise estimate obtained from the carrier recovery loop, and {circumflex over (θ)} n  is the residual phase noise after phase noise compensation.
 
c) Generate the output signal, {circumflex over (d)}(n)  128 , of the DD  110  based on the DD input, Q(n)  109 , using the selection process mentioned above.
 
d) Calculate the error signal e(n)  113  (or DD Noise ) by subtracting the DD output signal, {circumflex over (d)}(n)  128 , from the DD input signal, Q(n)  109 ;
 
 e ( n )= Q ( n )−{circumflex over ( d )}( n )
 
e1) Calculate the output signal, q(n)  107 , of the DFE in the adder  106 ;
 
               q   ⁡     (   n   )       =         ∑     k   =   1     K     ⁢         f   k     ⁡     (   n   )       ⁢       x   k     ⁡     (     n   -   k     )           +       ∑     l   =   1     L     ⁢         b   l     ⁡     (   n   )       ⁢         d   ^     l     ⁡     (     n   -   l     )                   
where K and L are the filter order of FFF and FBF, respectively.
 
e2) Calculate the normalized DD input, N_Q, by dividing the DD input signal, Q(n)  109 , by the energy of the DD input signal, |Q(n)| 2 , in the DD input signal normalizer  212 ;
 
 N   Q               Q   n   /|Q   n | 2  
 
f) Calculate the complex conjugate value of the DD error, CC_DE, by applying the complex conjugate function on the DD error signal, e(n)  113 , in the complex conjugator block  216 ;
 
CC_DE           e ·( n )*=( n )−{circumflex over ( d )}( n ))*
 
g) Calculate the normalized DD error, N_E, by multiplying the complex conjugate of the DD error signal with the normalized DD input, N_Q, in the multiplier  214 ;

               N_E   ⁢   ⁢           e   ⁡     (   n   )       *     ⁢     Q   ⁡     (   n   )                  Q   ⁡     (   n   )            2         =         (       Q   ⁡     (   n   )       -       d   ^     ⁡     (   n   )         )     *     ⁢       Q   ⁡     (   n   )                Q   ⁡     (   n   )            2               
h) Calculate the phase noise sample by taking the imaginary part of the normalized DD error signal in the imaginary part selector  218 ;
 
     Phase noise sample 
             ⁢           ⁢   Im   ⁢     {         (       Q   (   n   )     -       d   ^     ⁡     (   n   )         )     *     ⁢       Q   ⁡     (   n   )                Q   ⁡     (   n   )            2         }           
i) Calculate the phase noise estimate by taking the time averaging on the phase noise samples. The time averaging is achieved by passing the phase noise samples to the low pass filter  220  and then to the oscillator which is consisted of the adder  222  and the symbol delay operator  223  in the digital phase locked loop (DPLL);
 
     Phase noise estimate 
               ⁢           ⁢     E   ⁡     [     Im   ⁢     {         (       Q   ⁡     (   n   )       -       d   ^     ⁡     (   n   )         )     *     ⁢       Q   ⁡     (   n   )                Q   ⁡     (   n   )            2         }       ]         =     E   ⁡     [     Im   ⁢     {     1   -     ⅇ     j   ⁢           ⁢       θ   ^             }       ]             ≈             [−{circumflex over (θ)}   n ]=−{circumflex over (θ)},when {circumflex over (θ)} n  is small

     j) Convert the phase noise estimate into complex valued phase noise estimate using the phase noise estimator  226  and then perform phase noise correction (or compensation) by multiplying the respective input signal of the DFE, u(n)  100 , and the output signal, q(n)  107 , of the DFE-with the negative value of the phase noise estimate  226 , which is obtained from carrier recovery DPLL (digital phase locked loop) in the multipliers  102  and  108 , respectively, and then generate the input signal, x(n)  103 , of the FFF and the input signal, Q(n)  109 , of the DD;
 
 x ( n )= u ( n ) e   −jθ 
 
 Q ( n )= q ( n ) e   −jθ 
 
     The LPF (low pass filter) in the Digital Phase Locked Loop (DPLL) in the above  FIG. 2  is used for phase noise averaging purpose. The LPF used in DPLL is a classic filter. The LPF in the DPLL has two signal paths in it; one is a proportional path and the other is an integration path as shown in the following  FIG. 3 . As can be seen in the  FIG. 3 , the proportional path gain K p  and integration path gain K i  in the LFP determines the bandwidth of the carrier recovery loop filter. Note that the T in  FIG. 3  represents one symbol delay operator. 
     The carrier recovery loop supports a range of loop bandwidths designed to maximize phase noise tracking capability and minimize the effect of Additive White Gaussian Noise (AWGN). We need to optimize the loop bandwidth based on expected Signal to Noise Ratio (SNR) and phase noise.