Abstract:
A slew rate enhancement circuit for adjusting a gamma curve including a main output stage, a monitoring stage, an assistant output stage and a gamma curve generating device is provided. The main output stage also generates a first push signal and a first pull signal according to the input voltage, and thereafter the second push signal and second pull signal are level shifted by the monitoring stage. A second push signal and second pull signal will turn on or turn off the assistant output stage to decided whether to output an assistant current to the load or not. The gamma curve generating device receives the assistant current to outputs at least one gamma reference voltage for adjusting a gamma curve. Specially, the improved compact circuit does not increase static operating current for the original operational amplifier and occupy a small chip area.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application is a continuation-in-part of a prior application Ser. No. 10/707,354, filed Dec. 8, 2003, which claims the priority benefit of Taiwan application Ser. No. 92105571, filed on Mar. 14, 2003. All disclosures are incorporated herewith by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of Invention  
         [0003]     The present invention relates to a slew rate enhancement circuit for adjusting a gamma curve. More particularly, the present invention relates to a slew rate enhancement circuit for adjusting a gamma curve, which is compact and occupies small chip area.  
         [0004]     2. Description of Related Art  
         [0005]     Generally speaking, the color of each sub-pixel of a liquid crystal display is determined by twisting the angle of each corresponding liquid crystal, thereby to control the color of each pixel. Furthermore, the gamma curve, which defines the relation between the twisting angle of the liquid crystal and the voltage applied to the liquid crystal, is used for adjusting the chromaticity.  
         [0006]      FIG. 1A  is a gamma curve adjusting circuit according to a prior art. The circuit includes a plurality of amplifiers A 1 ˜A N+1 , which are in the external of driver circuit of the panel and a plurality of resisters R 1 ˜R N , which are in the internal of driver circuit of the panel. The gamma signals Gammal˜GammaM are outputted to the external amplifiers A 1 ˜A N+1 . Then, the external amplifiers A 1 ˜A N+1  drive the resisters R 1 ˜R N  so as to output different gamma reference voltages in the external of the system region of the panel. The different gamma reference voltages are combined to form a gamma curve for adjusting the chromaticity of the whole panel.  
         [0007]     In order to reduce the circuit area, the manufacturing production costs and the number of components, the amplifiers A 1 ˜A N+1  are integrated and moved from the external of driver circuit to the internal of driver circuit. Otherwise, the amplifiers A 1 ˜A N+1  may have stronger driving ability, because the resistors R 1 ˜R N  are not easy to drive. As a result, the conventional circuit should reinforce the driving ability of output stage of the amplifiers A 1 ˜A N+1  by increasing the static operating currents of the circuit. In the conventional circuit, when the amplifiers A 1 ˜A N+1  are integrated and moves from the external of driver the circuit to internal of driver circuit, the static operating currents are increased with causing problems of reliability and power consumption.  
         [0008]     To achieve high slew rate, when the operational amplifier (“OPAMP”) drives heavy load. Many techniques are used to enhance slew rate, such as: increase operating current of OPAMP, reduce compensation capacitor, or connect with error amplifier. Except for the high slew rate, a lot of disadvantages such as high operating current and stability degradation for original OPAMP, a large chip area, complexity of circuit design, noise and offset are introduced from error amplifiers succeed.  
         [0009]      FIG. 1B  illustrates a high slew rate amplifier according to a prior art. The circuit in  FIG. 1B  includes an OPAMP  102 , error amplifiers  104 ,  106  and a push-pull output stage  112 . The push-pull output stage includes a P-type Metal Oxide Semiconductor (“PMOS”) transistor  108  and an N-type Metal Oxide Semiconductor (“NMOS”) transistor  110 . The inverting inputs of the error amplifier  104  and the error amplifier  106  are connected to the output of the OPAMP  102  at a node N 11 . The non-inverting inputs of the error amplifier  104  and the error amplifier  106  are connected to a load at a node N 12 . The loop of connection between an output of the error amplifier  104  and the gate of the PMOS transistor  108 , and the loop of connection between the drain of the PMOS transistor  108  and the non-inverting input of the error amplifier  104  formed a negative feedback loop. Likewise, the loop of connection between the output of the error amplifier  106  and the gate of the NMOS transistor  110 , and the loop of connection between the drain of the NMOS transistor  110  and the non-inverting input of the error amplifier  106  also formed a negative feedback loop. The node N 11  and the loop including node N 12  construct a virtual short loop. The virtual short loop and both of the negative feedback loops are applied to control the PMOS transistor  108  to push current to the load or to control the NMOS transistor  110  to pull current from the load.  
         [0010]     The error amplifier  104  and the error amplifier  106  are applied to monitor the output signals of the OPAMP  102 . When a non-inverting input Vin 10  is not equal to an inverting input Vout 10 , the error amplifier  104  and the error amplifier  106  turn on the PMOS transistor  108  to push a current to the load, or turn on the NMOS transistor  110  to pull a current from the load. On the other hand, when the signal Vin 10  is equal to the signal Vout 10 , the PMOS transistor  108  and the NMOS transistor  110  work under the DC bias condition.  
         [0011]     In general, the circuit of  FIG. 1B  is usually applied to a buffer amplifier. In order to provide a large current from the PMOS transistor  108  and the NMOS transistor  110 , aspect ratios of the PMOS transistor  108  and the NMOS transistor  110  should be as large as possible, but a static operating current is also increased according to the aspect ratio. Furthermore, a real circuit on a chip is more complicated than  FIG. 1B , since the error amplifier  104  is constructed by at least 5 pieces of Metal Oxide Semiconductor (“MOS”) transistors, and so dose the error amplifier  106 . If the Miller Compensation is applied to compensate the pole/zero location shifts, the other two compensation capacitors are introduced into the circuit of  FIG. 1B . If the offset voltage, symmetry of layout, cross distortion, linearity, bandwidth and noise of and from the error amplifier  104  and error amplifier  106  are calibrated, additional circuits will be added to the circuit of  FIG. 1B . Therefore, the manufacturing of the circuit of  FIG. 1B  on a chip will occupy a huge chip area and consume a high static operating current of the original OPAMP.  
       SUMMARY OF THE INVENTION  
       [0012]     As embodied and broadly described herein, the invention provides an improved circuit for adjusting a gamma curve, denoted as the dynamic output stage for enhancement of the slew rate. The original operational amplifier includes a differential amplifier and a main output stage. The dynamic output stage includes a monitoring stage and an assistant output stage. The main output stage detects an input voltage from a differential amplifier to decide for outputting a main current to the load or not. The main output stage also generates a push signal and a pull signal for the monitoring stage. The monitoring stage decays the push signal and the pull signal, and the assistant output stage will receive the decayed push signal and the decayed pull signal to decide for providing an assistant current to the load or not. The assistant current is an additional huge current for enhancing the slew rate. The assistant current is turned on/off automatically and will not affect the operation status of the original OPAMP and the main output stage. A gamma curve generating device receives the main current to outputs at least one gamma reference voltage for adjusting a gamma curve. The present invention is used for a liquid crystal panel to increase the reliability and reduce the manufacturing production costs. Furthermore, the dynamic output stage does not consume static operating current. Compare with the error amplifiers in the prior art, this invention will not introduce the offset voltage, compensation, distortion and noise Therefore, no calibration will be necessary.  
         [0013]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0015]      FIG. 1A  is a gamma curve adjusting circuit according to a prior art.  
         [0016]      Fig. 1B  is a high slew rate amplifier according to a prior art.  
         [0017]      FIG. 2A  is a gamma curve adjusting circuit of a preferred embodiment of the present invention.  
         [0018]      FIG. 2B  is a sketch of the dynamic output stage of amplifiers D 1 ˜D N+1  of a preferred embodiment of the present invention.  
         [0019]      FIG. 3  is a detail circuit of the dynamic output stage of amplifiers D 1 ˜D N+1  of a preferred embodiment of the present invention.  
         [0020]      FIG. 4  is the graph of the final push current and the final pull current at the node N 25  versus the push and pull signal of OPAMP with and without this art. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]      FIG. 2A  is a gamma curve adjusting circuit of a preferred embodiment of the present invention. The circuit includes a plurality of amplifiers D 1 ˜D N+1  and a plurality of resistors R 1 ˜R N . The amplifiers D 1 ˜D N+1  drive the resistors R 1 ˜R N  in the internal of driver circuit of the panel. Furthermore, the plurality of resistors R 1 ˜R N  are connected as a resistor string to form a gamma curve generating device for outputting different gamma reference voltages. The main dynamic output stage of each of the amplifiers D 1 ˜D N+1  comprises a monitoring stage and an assistant output stage. Those skilled in the art should understand that not all amplifiers should have the same structure in the present invention. Any circuit which has at least one amplifier with the dynamic output stage for driving resistors to adjust a gamma curve is in the scope of the present invention.  
         [0022]      FIG. 2B  illustrates a sketch of the dynamic output stage of amplifiers D 1 ˜D N+1  of a preferred embodiment of the present invention. The amplifier includes a differential amplifier  202  and a main output stage  204 . The differential amplifier has an inverting input, denoted as Vout 20  and a non-inverting input, denoted as Vin 21 . The output of the differential amplifier, denoted as node N 21 , is connected to the main output stage  204 . The main output stage  204  includes a plurality of sub-circuits; which comprises a voltage source  220 , a first field effect transistor (FET) with a first type, for example, a first PMOS transistor  216 , a voltage source  222  and a second FET with a second type, for example, a second NMOS transistor  218 . The first and second field effect transistors provide a first push current and a first pull current, respectively. The output of the differential amplifier  202  is connected to the voltage source  220  and the voltage source  222  at a node N 21 . The drain of the first PMOS transistor  216  is connected to the drain of the second NMOS transistor  218  at a node N 22 . The gate of the first PMOS transistor  216  is connected with the voltage source  220  and with a voltage source  208  at a node N 23 . A first push signal Vg 1  is generated by the main output stage  204  at the node N 23  and the signal Vg 1  also stands for the voltage of the node N 23 . The source of the first PMOS transistor  216  is connected to a power Vdd. The gate of the second NMOS transistor  218  is connected to the voltage source  222  and with a voltage source  210  at a node N 24 . A first pull signal Vg 2  is generated by the main output stage  204  at the node N 24  and the signal Vg 2  also stands for the voltage of the node N 24 . The source of the second NMOS transistor  218  is connected to the ground. The voltage of the voltage source  208  is V 1  and the voltage of the voltage source  210  is V 2 . An assistant output stage  206  includes a third FET with the first type, for example, a third PMOS transistor  212  and a fourth FET with the second type, for example, a fourth NMOS transistor  214 . The third and fourth field effect transistors provide the second push current and second pull current, respectively. The drain of the third PMOS transistor  212  is connected to the drain of the fourth NMOS transistor  214  at a node N 25 . The node N 22  is connected to the node N 25  and the load. The gate of the third PMOS transistor  212  is connected to the voltage source  208  and the gate of the fourth NMOS transistor  214  is connected to the voltage source  210 .  
         [0023]     In a steady state, the voltage Vin 21  is close to the voltage Vout 20 , the main output stage  204  does not apply any current to the load. A second push signal Vg 3 , denoting the gate voltage of the third PMOS transistor  212  is equal to the first push signal Vg 1  minus the voltage V 1 . The voltage V 1  is large enough, so the second push signal Vg 3  is not able to turn on the third PMOS transistor  212 . Likewise, a second pull signal Vg 4 , denoting the gate voltage of the fourth NMOS transistor  214  is equal to the first pull signal Vg 2  minus the voltage V 2 . The voltage V 2  is large enough, so the second pull signal Vg 4  is not able to turn on the fourth NMOS transistor  214 . No current will be applied to the load from the assistant output stage  206 .  
         [0024]     When the steady state no longer exists, the voltage Vin 21  is larger than the voltage Vout 20 . The output node N 21  of differential amplifier  202  will approach to the GND potential. The gate voltage N 23  of the first PMOS  216  will approach to the GND potential, too. Thus, the first PMOS  216  will apply a main current to the load from node N 22 . The load, the gamma curve generating device having resistors R 1 ˜RN, receives the main current to output at least one gamma reference voltage for adjusting a gamma curve. The first push signal Vg 1  is fed forward to the assistant output stage  206  via the voltage source  208 . The first push signal Vg 1  is decayed by the voltage source  208 , which results in a second push signal Vg 3 . This second push signal Vg 3  will approach to the GND potential, even though the potential voltage of Vg 3  is ‘Vg 1 +V 1 ’. The second push signal is large enough to turn on the third PMOS  216 . Meanwhile, the gate voltage N 24  of the second NMOS  218  will approach to the GND potential, thus the second NMOS  218  is turned off. The first pull signal Vg 2  is fed forward to the assistant output stage  206  via the voltage source  210 . The first pull signal Vg 2  is decayed by the voltage source  210 , which results in a second pull signal Vg 4 . This second pull signal will approach the GND potential, and the fourth NMOS  214  is turned off. Therefore, the assistant output stage  206  will also apply an assistant current to the load from the node N 25 . When the voltage Vin 21  turns into a little larger than the voltage Vout 20 , the gate voltage N 23  of the first PMOS  216  and the gate voltage N 24  of the second NMOS  218  will return to a steady state condition. Due to the voltage source  208  and  210 , the assistant output stage  206  will turn off and no longer apply an assistant current to the load. The main output stage will apply current to the load until the voltage Vin 21  equals Vout 20 .  
         [0025]     When the voltage Vin 21  is smaller than the voltage Vout 20 , the output node N 21  of differential amplifier  202  will approach to Vdd. The gate voltage N 24  of the second NMOS  218  will approach to Vdd, too. Thus, the second NMOS  218  will apply a main current to the load from node N 22 . The first pull signal Vg 2  is fed forward to the assistant output stage  206  via the voltage source  210 . The first pull signal Vg 2  is decayed by the voltage source  210 , which results in a second pull signal Vg 4 . This result in the second pull signal Vg 4  will approach to Vdd, even though the potential voltage of Vg 4  is ‘Vg 2 +V 2 ’. The second pull signal is large enough to turn on the NMOS  214 . Meanwhile, the gate voltage N 23  of the first PMOS  216  will approach to Vdd, thus the first PMOS  216  is turned off. The first push signal Vg 1  is fed forward to the assistant output stage  206  via the voltage source  208 . The first push signal Vg 1  is decayed by the voltage source  208 , which results in a second push signal Vg 3 . This second push signal will approach to Vdd, and the third PMOS  212  is turned off. Therefore, the assistant output stage will also apply an assistant current to the load from the node N 25 . When the voltage Vin 21  turns into a little smaller than the voltage Vout 20 , the gate voltage N 23  of the first PMOS  216  and the gate voltage N 24  of the second NMOS  218  will return to a steady state condition. Due to the voltage source  208  and  210 , the assistant stage  206  will turned off and no longer apply an assistant current to the load. The main output stage will apply current to the load until the voltage Vin 21  closes to Vout 20 . The novel technology presented above is the dynamic output stage.  
         [0026]      FIG. 3  is a detail circuit of the dynamic output stage of amplifiers D 1 ˜D N+1  in the present invention, wherein the voltage sources  208  and  210  are replaced by a monitoring stage  302 . The monitoring stage  302  includes a fifth FET with the first type, for example, a fifth PMOS transistor  304 , a current source  308 , a sixth FET with the second type, for example, a sixth NMOS transistor  306  and a current source  310 . The gate of the fifth PMOS transistor  304  is connected to the gate of the first PMOS transistor  216  at the node N 23 . The source of the fifth PMOS transistor  304  is connected to the gate of the third PMOS transistor  212  and to the current source  308  at a node N 26 . The drain of the fifth PMOS transistor  304  is connected to the ground. The gate of the sixth NMOS transistor  306  is connected to the gate of the second NMOS transistor  218  at the node N 24 . The source of the sixth NMOS transistor  306  is connected to the gate of the fourth NMOS transistor  214  and to the current source  310  at a node N 27 . The drain of the sixth NMOS transistor  306  is connected to Vdd. The other circuit devices and connections between these devices in  FIG. 3  are the same as those in  FIG.2B .  
         [0027]     In  FIG. 3 , when the voltage Vin 21  is close to the voltage Vout 20  in the steady state, the main output stage  204  does not apply any current to the load. The first PMOS transistor  216  and the second NMOS transistor  218  will work under the quiescent current bias condition so that even a voltage at the inverting input is equal to that at the non-inverting input, there exists a quiescent DC biased current at the node N 22 . A voltage difference between the node N 26  and the node N 23  will be equal to a threshold voltage Vt 1  of the fifth PMOS  304  at least. Likewise, the voltage difference between the node N 27  and the node N 24  will be at least equal to a threshold voltage Vt 2  of the sixth NMOS  306 . The first push signal Vg 1  is decreased by the threshold voltage Vtl, and therefore the second push signal Vg 3  will close to Vdd, thus the third PMOS transistor  212  will be turned off. The first pull signal Vg 2  is also increased by the threshold voltage Vt 2 , and therefore the second pull signal Vg 4  will close to the ground, thus the third NMOS transistor  214  will also be turned off. Therefore, the assistant output stage will not apply any current to the load.  
         [0028]     When the steady state no longer exists, the voltage Vin 21  is larger than the voltage Vout 20 , the first pull signal Vg 2  will approach to the GND potential, and therefore the second NMOS transistor  218  will be turned off. The first push signal Vg 1  will approach to the GND potential, and therefore the first PMOS transistor  216  will be turned on. The result is that the main output stage  204  pushes a main current to the load. The second push signal Vg 3  is equal to the first push signal Vg 1  plus the absolute value of the voltage difference between the gate and the source of the fifth PMOS transistor  304 . Likewise, the second pull signal Vg 4  is equal to the first pull signal Vg 2  minus the absolute value of the voltage difference between the gate and the source of the sixth NMOS transistor  306 . Since the second NMOS transistor  218  is turned off, the fourth NMOS transistor  214  will also be turned off. The first PMOS transistor  216  is turned on, the second push signal Vg 3  is able to turn on the third PMOS transistor  212  to push an extra current to the load. The final result is that the assistant output stage will push an assistant current to the load. When the voltage Vin 21  turns into a little larger than the voltage Vout 20 , the push signal Vg 1  and the pull signal Vg 2  will return to a quiescent bias condition. Since Vg 1  and Vg 2  are level shifted by the fifth PMOS transistor  304  and the sixth NMOS transistor  306 , the second push signal Vg 3  and the second pull signal Vg 4  will be not enough to turn on the third PMOS transistor  212  and the fourth NMOS transistor  214 . Therefore the assistant output stage will not apply current to the load. The load will be driven by the current from the main output stage  204  till the voltage Vin 21  closes to the Vout 20 .  
         [0029]     When the steady state no longer exists, the voltage Vin 21  is smaller than the voltage Vout 20 , the push signal Vg 1  will approach to Vdd, and therefore the first PMOS transistor  216  will be turned off. The first pull signal Vg 2  will approach to Vdd, and therefore the second NMOS transistor  218  will be turned on. The result is the main output stage  204  will pull a main current from the load. Since the first PMOS transistor  216  is turned off, the third PMOS transistor  212  will also be turned off. The second NMOS transistor  218  is turned on, the second pull signal Vg 4  is able to turn on the fourth NMOS transistor  214  to pull an extra current from the load. The final result is that the assistant output stage will pull an assistant current from the load. When the voltage Vin 21  turns into a little smaller than the voltage Vout 20 , the first push signal Vg 1  and the first pull signal Vg 2  will return to the quiescent bias condition. Since Vg 1  and Vg 2  are level shifted by the fifth PMOS transistor  304  and the sixth NMOS transistor  306 , the second push signal Vg 3  and the second pull signal Vg 4  will not be enough for the third PMOS transistor  212  and the fourth NMOS transistor  214 . Therefore, the assistant output stage will not pull any current from the load. The load will be driven by the current from the main output stage  204  till the voltage Vin 21  closes to the Vout 20 .  
         [0030]     The assistant output stage is an apparatus, which could provide the extra current to the load. The assistant output stage is controlled by the fifth PMOS transistor  304  and the sixth NMOS transistor  306 , which operate as a source follower. Thus, the assistant output stage will be turned on after the main output stage is turned on, and be turned off before the main output stage is turned off. The assistant output stage is turned on/off automatically, and furthermore the assistant output stage does not consume the static operating current. The problem of prior art, such as: offset voltage, pole/zero location, and linearity, will no longer exist. The slew rate of operational amplifier is increased without consuming the extra operating current and degrades stability.  
         [0031]      FIG. 4  is the graph of the final push current and the final pull current at the node N 25  versus the push and pull signal of the amplifier with and without this invention. The final push current and the final pull current are obviously increased by the assistant output stage. In  FIG. 4 , the push current with this invention is larger than the push current without this invention under the same push signal V 01 . Likewise, the pull current with this invention is larger than the pull current without this invention under the same pull signal V 02 . Therefore, the final push current or pull current is higher than the push or pull current of the original amplifier without this invention. With the dynamic output stage in this invention, it is easy to enhance the slew rate without increasing static operating current of the original amplifier. Because the amplifiers have a monitoring stage and an assistant output stage, the static operating current is designed to be much less. Therefore, the present invention not only reduces the area of the system board and minimize the number of the external components, but also solves the problem of reliability and power consumption.  
         [0032]     Accordingly, the circuit and method provided in the present invention can be used to any circuit having at least two inputs, for example, a first input and a second input and a main current. The method of the invention includes that, first of all, detecting a first input and a second input. Secondly, a push current is generated when a voltage of the second input is larger than a voltage of the first input and their difference is large enough to turn on at least one of the switches. Thirdly, a pull current is generated when a voltage of the first input is larger than a voltage of the second input and their difference is large enough to turn on at least one of the switches. Otherwise, the main current is used to generate at least one gamma reference voltage for adjusting a gamma curve. Thus, the push circuit and the pull circuit can be used to enlarge the main current to enhance the slew rate. Moreover, the push current and the pull current are further fed back to one of the first input and the second input. Furthermore, the push current and the pull current is turned on automatically after the main current is turned on, and is turned off automatically before the main current is turned off.  
         [0033]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.