Abstract:
Power switch controllers and methods used therein are disclosed. An exemplifying power switch controller includes a window provider, a sensor and a logic controller. The window provider provides minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively. The sensor detects a terminal of an inductive device, to generate a trigger signal. The logic controller prevents a power switch connected to the inductive device from being turned on before the elapse of the minimum time, forces the power switch to be turned on after the elapse of the maximum time, and turns on the power switch if the trigger signal is asserted.

Description:
BACKGROUND 
       [0001]    The present disclosure relates generally to power supplies and the control methods used therein. 
         [0002]    Power converters or adapters are devices that convert electric energy provided from batteries or power grid lines into power source with a specific voltage or current, such that electronic apparatuses are powered accordingly. For modern apparatuses that are required to be friendly to the world we live, conversion efficiency, which is the ratio of the power provided to a load powered by a power converter over the power delivered to the power converter over, is always a big concern. The less the power consumed by a power converter itself, the higher the conversion efficiency of the power converter. 
         [0003]    Power converters operating in quasi-resonant (QR) mode are proved, in both theory and practice, to work more efficiently than most of other power converters, due to that power switches operated in QR mode are switched at zero current or voltage, resulting in an essentially lossless switch. 
         [0004]      FIG. 1  illustrates a flyback converter  8 , which is capable of operating in QR mode. Circuit  10  illustrates flyback topology, including power switch  15 , primary winding PRM and secondary winding SEC of a transformer, a diode, and a current sense resistor. When power switch  15  is ON, performing a short circuit, primary winding PRM energizes. When power switch  15  is OFF, performing an open circuit, secondary winding SEC de-energizes to power node OUT through a diode. Power switch controller  18  controls ON time T ON  or OFF time T OFF  of power switch  15 , based on feedback signal V FB  provided at node FB by feedback circuit  20 , which monitors node OUT. The higher the feedback signal V FB , the higher the output power required to maintain the voltage at node OUT. Operating voltage source generator  12  provides voltage source V cc  at node VCC to power switch controller  18 . Resistor  14  connects one terminal of auxiliary winding AUX to node ZCD of power switch controller  18 , to provide the energy status of the transformer. 
         [0005]      FIGS. 2A and 2B  show waveforms of voltage signal V ZCD  at node ZCD under different load conditions.  FIG. 2A  corresponds to a relatively heavier load, and  FIG. 2B  to a relatively lighter load. It can be seen from  FIGS. 2A and 2B  that voltage signal V ZCD  starts to oscillate after the transformer de-energizes completely and results in voltage valleys VLY 1 , VLY 2 , VLY 3 , and so forth. The lighter the load, the earlier the completion of de-energizing, the earlier the occurrences of voltage valleys. A power supply in QR mode can operate to start energizing at the moment when any one of the voltage valleys occurs.  FIG. 3  illustrates the relationships between switch frequency f CYC  and feedback signal V FB  at node FB, where switch frequency f CYC  is the inverse of cycle time T CYC , which is the summation of ON time T ON  and OFF time T OFF , ON time T ON  referring to the time period when a power switch is ON, and OFF time T OFF  to the time period when it is OFF. For example, Curve  22   1  shows the V FB -to-f CYC  relationship if power switch  15  is switched at the moment when voltage valley VLY 1  occurs. Curve  22   2  shows the V FB -to-f CYC  relationship if power switch  15  is switched at the moment when voltage valley VLY 2  occurs. And so forth. As shown in  FIG. 3 , if a power supply is designed to switch its power switch at a specific voltage valley, switch frequency f CYC  increases adversely as feedback V FB  decreases. The higher switch frequency f CYC , the higher power to charge and discharge a control node of a power switch, resulting in less conversion efficiency. 
       SUMMARY 
       [0006]    Embodiments of the present invention disclose a power switch controller suitable to control a power switch connected to an inductive device. The power switch controller includes a window provider, a sensor and a logic controller. The window provider provides minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively. The sensor detects a terminal of the inductive device, to generate a trigger signal. The logic controller prevents the power switch from being turned on before the elapse of the minimum time, forces the power switch to be turned on after the elapse of the maximum time, and turns on the power switch if the trigger signal is asserted. 
         [0007]    Embodiments of the present invention disclose a method for controlling a power switch connected to an inductive device. A terminal of the inductive device is detected to generate a trigger signal. The power switch is turned on if the trigger signal is asserted. Before the elapse of a minimum time, the power switch is prevented from being turned on. After the elapse of a maximum time, the power switch is enforced to be turned on. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0009]      FIG. 1  illustrates a flyback converter; 
           [0010]      FIGS. 2A and 2B  show waveforms of voltage signal V ZCD  at node ZCD under different load conditions; 
           [0011]      FIG. 3  illustrates the relationships between switch frequency f CYC  and feedback signal V FB  at node FB; 
           [0012]      FIG. 4  exemplifies a power switch controller adaptable to the flayback converter of  FIG. 1 ; 
           [0013]      FIG. 5  exemplifies a window provider; 
           [0014]      FIG. 6  illustrates the waveforms of signals in  FIGS. 4 and 5 ; 
           [0015]      FIG. 7  illustrates two diagrams, the upper one showing the changes of minimum time T MIN  and maximum time T MAX  vs. feedback signal V FB , and the lower one showing the changes of maximum frequency f MAX  and minimum frequency f MIN  vs. feedback signal V FB ; 
           [0016]      FIG. 8  includes curve  50  illustrating the relationship between switch frequency f CYC  and feedback signal V FB  for power switch controller  30  in  FIG. 4 ; 
           [0017]      FIGS. 9A and 9B  show two window providers; and 
           [0018]      FIG. 10  illustrates the relationship between switch frequency f CYC  and feedback signal V FB  for power switch controller  30  in  FIG. 4  if window provider  40  is embodied by window provider  60   a  or  60   b.    
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Objects of the present invention and more practical merits obtained by the present invention will become more apparent from the description of the embodiments which will be given below with reference to the accompanying drawings. For explanation purposes, components with equivalent or similar functionalities are represented by the same symbols. Hence components of different embodiments with the same symbol are not necessarily identical. Here, it is to be noted that the present invention is not limited thereto. 
         [0020]    The following embodiments are exemplified by flyback converters, but are not intended to limit the scope of the invention. A person skilled in the art could apply the concept of the invention to converters with different topologies, such as bulk converters, buck-boost converters, boost converters, and so forth. 
         [0021]      FIG. 4  exemplifies power switch controller  30  adaptable to flyback converter  8  of  FIG. 1 . Comparator  32 , delay circuit  33  and pulse generator  36 , as a whole acting as a sensor, detects one terminal of auxiliary winding AUX to generate trigger signal S PLS  with pulses, each expectedly corresponding to an occurrence of a voltage valley at node ZCD. Window provider  40  provides minimum and maximum time signals, S MIN  and S MAX , to indicate the elapses of a minimum time T MIN  and a maximum time T MAX . Logic controller  38  includes several logic gates, controls the S terminal of SR register  34 , and determines when power switch  15  is switched to be ON. Only when minimum time signal S MIN  is asserted to indicate that minimum time T MIN  has elapsed, trigger signal S PLS  is possible to pass through logic controller  38  and, if asserted, set SR register  34 . In other words, logic controller  38  prevents power switch  15  from being turned on before the elapse of minimum time T MIN . If trigger signal S PLS  is not asserted and maximum time T MAX  elapses, maximum time signal S MAX  sets SR register  34  anyway, power switch  15  is forced to be turned ON, and the flyback converter enters into a following switch cycle. When signal V CS  at current sense node CS exceeds the voltage at the inverse input of comparator  42 , SR register  34  is reset and power switch  15  is switched to be OFF. Accordingly, feedback signal V FB  at node FB substantially decides the peak voltage of signal V CS  or the power supplied to node OUT in a switch cycle. 
         [0022]      FIG. 5  exemplifies window provider  40 , which receives set signal S SET , and outputs minimum and maximum time signals, S MIN  and S MAX . When set signal is asserted, ramp signal V RMP  is grounded. When set signal is de-asserted, ramp signal V RMP  starts to increase, with a slope determined by the output current of voltage-controllable current source  70 , which is controlled by feedback signal V FB  at node FB. Feedback signal V FB  substantially represents the power required by a load at node OUT. At the moments when ramp signal V RMP  exceeds reference voltages V REFL  and V REFH , minimum and maximum time signals S MIN  and S MAX  are toggled or asserted, respectively, indicating the elapses of minimum time T MIN  and maximum time T MAX , respectively. Reference voltage V REFL  should be less than reference voltage V REFH , such that minimum time signal S MIN  is asserted earlier. If the output current of voltage-controllable current source  70  decreases, the slope of ramp signal V RMP  is less and it takes more time for ramp signal V RMP  to reach reference voltages V REFL  and V REFH , such that both minimum time T MIN  and maximum time T MAX  increase. It can be derived by those skilled in the art that minimum time T MIN  and maximum time T MAX  provided in  FIG. 5  are in proportion. 
         [0023]      FIG. 6  illustrates the waveforms of signals in  FIGS. 4 and 5 . Waveforms in  FIG. 6  are, from top to bottom, voltage signal V ZCD  at node ZCD, signal S DET  from comparator  32 , signal S DLY  from delay circuit  33 , trigger signal S PLS  from pulse generator  36 , set signal S SET  at S terminal of SR register  34 , gate signal S GATE  at node GATE, ramp signal V RMP  in  FIG. 5 , and minimum time signal S MIN  from comparator  42 . The pulse of set signal S SET  at time t 1  turns on power switch  15  and grounds ramp signal V RMP . ON time T ON  is determined by feedback signal V FB , such that gate signal S GATE  changes at time t 2 , causing the rising of voltage signal V ZCD , the logic change of signal S DET , and the logic change of signal S DLY , which is delayed by delay time T delay  in comparison with signal S DET . At time t 3 , it is the first time that voltage signal V ZCD  drops across 0V after the completion of de-energization, causing after delay time T delay  the rising edge of signal S DLY , which accordingly results in a pulse in trigger signal S PLS  output from pulse generator  36 . Before time t 4 , as ramp signal V RMP  is under reference voltage V REFL , minimum time signal S MIN  remains 0 in logic, such that pulses in trigger signal S PLS , if any, are blocked from reaching S terminal of SR register  34  and set signal S SET  remains 0 in logic. After time t 4  when minimum time T MIN  has elapsed, ramp signal V RMP  has exceeded reference voltage V REFL  and minimum time signal S MIN  changes into logic 1, such that at time t 5  the pulse in trigger signal S PLS  is passed to be set signal S SET  and turn on power switch  15 , starting a following switch cycle. As shown in  FIG. 6 , if delay time T delay  is well designed, each pulse in trigger signal S PLS  could represent the occurrence of a voltage valley of voltage signal V ZCD  and power switch  15  is turned ON at time t 5  when voltage valley VLY 3  occurs, substantially performing an operation in QR mode. 
         [0024]      FIG. 7  illustrates two diagrams, the upper one showing the changes of minimum time T MIN  and maximum time T MAX  vs. feedback signal V FB , and the lower one showing the changes of maximum frequency f MAX  and minimum frequency f MIN  vs. feedback signal V FB . As minimum time T MIN  is the earliest time that power switch controller  30  in  FIG. 4  can turn ON a power switch, its inverse, 1/T MIN , defines a maximum switching frequency f MAX  that power switch controller  30  can perform. Similarly, 1/T MAX , the inverse of maximum time T MAX , defines a minimum frequency f MIN . 
         [0025]    Voltage-controllable current source  70  in  FIG. 5  could be well designed to achieve the curves in  FIG. 7 . For example, the output current from voltage-controllable current source  70  is a respectively-lower constant if feedback signal V FB  is under reference voltage V REF2 , increases linearly if feedback signal V FB  approaches from reference voltage V REF2  to reference voltage V REF3 , and is a respectively-higher constant if feedback signal V FB  is over reference voltage V REF3 . It is shown in  FIG. 7  that minimum time T MIN  decreases as feedback signal V FB  increases if feedback signal V FB  is between reference voltages V REF2  and V REF3 . 
         [0026]      FIG. 8  includes curve  50  illustrating the relationship between switch frequency f CYC  and feedback signal V FB  for power switch controller  30  in  FIG. 4 . The dashed curves in  FIG. 8  duplicate maximum frequency f MAX  and minimum frequency f MIN  of  FIG. 7 , and the curves in  FIG. 3  showing the relationships between switch frequency f CYC  and feedback signal V FB . It can be derived based on the aforementioned teaching that power switch controller  30  turns on power switch  15  substantially at the occurrence of the earlier voltage valley after minimum time T MIN , but no later than maximum T MAX . Accordingly, curve  50  is limited to locate somewhere between minimum frequency f MIN  and maximum frequency f MAX , and traces the highest one among curves  22   1 ,  22   2 ,  22   3  . . . . It can be seen from  FIG. 8  that switch frequency f CYC  power switch controller  30  provides is somehow lower for light load when feedback signal V FB  is less, because the switching of a power switch might shift to the moment when a subsequent voltage valley occurs. Within the time period of a switch cycle, the control node of power switch  15  is charged and discharged once, requiring a certain amount of power. Less switch frequency f CYC  results in less power for charging and discharging the control node of power switch  15 , increasing power conversion efficiency for light load. 
         [0027]    As shown in  FIG. 8 , for very heavy load when feedback signal V FB  is so high, switch frequency f CYC  substantially stays at the constant defined by minimum frequency f MIN , raising the concern of electromagnetic interference (EMI).  FIGS. 9A and 9B  show window providers  60   a  and  60   b  that are two alternatives to window provider  40  and could solve this concern, using the technology of jittering. In addition to what is shown in window provider  40  of  FIG. 5 , each of window providers  60   a  and  60   b  has counter  66  cycling its digital outputs S 0 ˜S n  every several milliseconds while switch frequency f CYC  has a clock cycle time around the order of microseconds. Of window provider  60   a , there is a digital-to-analog converter  72  that receives digital outputs S 0 ˜S n  and generates a corresponding relatively-little current I JIT , such that the total current charging the capacitor jitters over time. Of window provider  60   b , the effective capacitance of capacitor array  76  in  FIG. 9B  jitters because it is slightly changed by digital outputs S 0 ˜S n . As the current charging the capacitor or the capacitance of the capacitor array jitters, both minimum frequency f MIN  and maximum frequency f MAX  are no more two constants for a certain feedback signal V FB , but jitter over time.  FIG. 10  illustrates the relationship between switch frequency f CYC  and feedback signal V FB  for power switch controller  30  in  FIG. 4  if window provider  40  is embodied by window provider  60   a  or  60   b . In  FIG. 10 , the curves representing minimum frequency f MIM  and maximum frequency f MAX  are dashed and triple-lined to indicate that they are not constant but jittering. Shown in  FIG. 10 , for very heavy load when feedback signal V FB  is so high, switch frequency f CYC  is no more a constant but jitters as minimum frequency f MIN  does. 
         [0028]    Benefits of the aforementioned embodiments include the followings. A power switch controller according to the invention could switch a power switch at the moment when the voltage cross the power switch is around a voltage valley, performing almost lossless switching. For heavy load, this valley could be the 1 st  voltage valley. For light load or even no load, as switch frequency f CYC  is limited to be between minimum frequency f MIM  and maximum frequency f MAX , this valley could change into the 2 nd , 3 rd  or even a further subsequent voltage valley. For light load or no load, since minimum frequency f MIM  and maximum frequency f MAX  become lower, switch frequency f CYC  become lower too, saving the power to charge or discharge the control node of the power switch. In case of the very heavy load condition, uttering minimum frequency f MIM  prevents or reduces the concern of EMI. 
         [0029]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.