Abstract:
The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell array for storing address mapping information that indicates one or more locations of one or more memory cells in the second memory cell array. The second memory cell array endures substantially more programming cycles than the first memory cell array does.

Description:
BACKGROUND  
       [0001]     The present invention relates to integrated circuit (IC) designs, and more particularly to a non-volatile memory device with various types of memory cell arrays.  
         [0002]     Flash memory is one of the most popular volatile memory devices available in the market. The flash memory provides easy and fast permanent data storage ability for electronic devices such as computers, digital cameras, and other portable devices. The flash memory is considered as a solid state device, meaning that, unlike a hard drive, it contains no moving part. The lack of moving parts allows the flash memory to provide a quicker and more reliable data storage than the hard disc drive. Thus, the flash memory has been considered as one of the candidates that has the potential to replace the hard disc drive as a mass data storage device in the future.  
         [0003]     One technical challenge for the flash memory to function as a mass data storage device is that it needs to endure many programming cycles without failure. A typical flash memory cell includes a floating gate disposed on a gate oxide above a channel region. In a programming operation, electrons are injected through the gate oxide and trapped within the floating gate to program the memory cell with a predetermined bit value. This electron injection may cause the gate oxide&#39;s failure after many programming cycles.  
         [0004]     High endurance flash memory has been developed in order to sustain more programming cycles. The high endurance memory cells used in such flash memory are often large in size. For example, extra components such as charge pumps may be necessary to provide the required potential for operation. Many reserve memory cells may be implemented in the flash memory for replacing the high endurance memory cells once they fail. The high endurance flash memory comes with a trade-off.  
         [0005]     While the high endurance flash memory is good for some purposes, it is not necessary for all operations. For example, many codes within a memory device need not to be updated very often, and only some data require frequent updates. It would be more cost efficient to store these codes in memory devices, such as transitional read only memory (ROM) than in the high endurance flash memory. Storing both the codes and data in the high endurance flash memory is wasteful and cost inefficient.  
         [0006]     It is therefore desirable to design a memory device that contains high endurance memory cells for storing frequently updated data and typical memory cells for storing less frequently updated codes in order to improve the cost efficiency.  
       SUMMARY  
       [0007]     The present invention discloses a memory device. In one embodiment of the invention, the memory device includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell array for storing address mapping information that indicates one or more locations of one or more memory cells in the second memory cell array. The second memory cell array endures substantially more programming cycles than the first memory cell array does.  
         [0008]     The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1A  illustrates a memory device that is partitioned into several memory cell arrays of different types of memory cells in accordance with one embodiment of the present invention.  
         [0010]      FIG. 1B  illustrates a diagram showing a micro-processing system using the memory device illustrated in  FIG. 1A  in accordance with another embodiment of the present invention. 
     
    
     DESCRIPTION  
       [0011]      FIG. 1A  illustrates a non-volatile memory device  100  that is partitioned into several memory cell arrays of different types of memory cells in accordance with one embodiment of the present invention. This memory device  100  is divided into three different memory cell arrays: a code storage array  102 , a data storage array  104 , and an address mapping information array  106 . The code storage array  102  is designated for storing codes that are less frequently updated, while the data storage array  104  is designated for storing data that are more frequently updated. The address mapping array  106  is used for storing address mapping information that indicates the physical locations of the memory cells in the data storage array  102 .  
         [0012]     The data storage array  104  is constructed by high endurance memory cells to sustain the frequent updates of the data stored therein, while the code storage array  102  is constructed by typical memory cells for storing the less frequently updated codes. As a result, the data storage array  104  is able to sustain more programming cycles than the data storage array  104 . In this embodiment, the data storage array is able to endure at least 100K programming cycles, while the code storage array  102  is only able to endure at least 1K programming cycles.  
         [0013]     The memory cells in the code storage array  102  can be typical one-transistor non-volatile memory cells. These one-transistor memory cells are not designed for high endurance, therefore requiring a small area to implement. Thus, they are ideal for code storage, not for data storage. The high endurance cells in the data storage array  104  can be typical two-transistor flash memory cells for sustaining more programming cycles. Thus, they are ideal for data storage, not for code storage.  
         [0014]     These two-transistor memory cells are larger than the one-transistor cells and require more silicon area to implement. For this reason, it is important to limit the number of high endurance memory cells implemented in order to save silicon area. In many instances, information to be stored in a memory device includes not only the data, but also the codes. Thus, it would be desired to adjust the capacities of the data storage array  104  and the code storage array  102  in accommodation of the quantities of the data and codes.  
         [0015]     The sizes of the data storage array  104  and the code storage array  102  are determined based on practical needs. Thus, the non-volatile memory device  100  can utilize the layout area more efficiently. While this embodiment only presents a data storage array  104  and a code storage array  102 , it is understood that the memory device  100  can be partitioned into more memory cell arrays of various levels of endurance without departing from the spirit of the invention.  
         [0016]     In order for a computer device to locate the different memory cell arrays within the memory device  100 , an address mapping information array  106  is required to provide the computer with the locations of the memory cells for the data storage array  104 . The interaction between the computer device and the non-volatile memory device  100  is detailed in reference with  FIG. 1B .  
         [0017]      FIG. 1B  illustrates a micro-processing system  108  using the non-volatile memory device  100  as illustrated in  FIG. 1A  in accordance with another embodiment of the present invention. The device  110 , designed to interact with the non-volatile memory array  100 , includes a controller  112 , a comparator  114 , and a volatile memory device  116 , such as random-access memory (RAM). The controller  112  is capable of outputting data associated with logical addresses. The volatile memory device  116  coupled with the non-volatile memory device  100  temporarily stores the address mapping information retrieved from the address mapping array  106 . The address mapping information indicates the physical locations of the memory cells in the data storage array  104 . The comparator  114  coupled among the controller  112 , the volatile memory device  116  and the non-volatile memory device  100  stores the data received from the controller into the data storage array  104  based on the address mapping information forwarded by the volatile memory device  116 .  
         [0018]     In operation, the information stored in the address mapping information array  106  is downloaded into the volatile memory device  116  after the device  110  is powered up. The type of memory array that will be read from and written into is decided by the controller  112 . For example, when the device  110  requires the data from the data storage array  104 , the comparator  114  will compare the output of the controller  112  with the address mapping information temporarily stored within the volatile memory device  116  to locate the memory cell locations in the data storage array  104 . When the device  100  requires the less frequently updated codes from the code storage array  102 , the comparator  114  will compare the output of the controller  112  with the address mapping information temporarily stored within the volatile memory device  116  to locate the memory cell locations in the code storage array  104 .  
         [0019]     In the embodiment of this invention, the data storage array  104  can be made of high endurance flash memory cells and the code storage array  102  can be made of typical flash memory cells. The typical flash memory cell occupies less silicon area than the high endurance flash memory cell. The high endurance flash memory cells can be called upon by using the information within the address mapping information array  106 . The combination of the high endurance memory cells and the typical memory cells optimizes the area utilization and costs for the non-volatile memory device  100  that is designed to store both the frequently updated data and the less frequently updated codes.  
         [0020]     The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.  
         [0021]     Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.