Abstract:
A converter includes first and second input terminals and first and second output terminals. The converter also includes an output capacitor coupled between the first output terminal and the second output terminal, and a magnetic component having two input terminals and three output terminals. A first output terminal of the magnetic component is coupled through a first electronic switch to the second output terminal of the converter, a second output terminal of the magnetic component is coupled to the first output terminal of the converter, and a third output terminal of the magnetic component is coupled through a second electronic switch to the second output terminal of the electronic converter. In addition, the converter includes a switching stage configured to transfer current pulses from the first input terminal and the second input terminal of the converter to the two input terminals of the magnetic component.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to electronic converters. Embodiments of the present disclosure regard approaches that enable implementation of the inductances of a current-doubler rectifier with a magnetic component. 
       BACKGROUND 
       [0002]    Supply circuits, such as for example, AC/DC or DC/DC switching power supplies, are well known in the art. There are many types of electronic converters that may be divided mainly into insulated and non-insulated converters. For example, non-insulated electronic converters are converters of the buck, boost, buck-boost, Cuk, SEPIC, and ZETA types. Insulated converters are, for example, converters of the flyback, forward, half-bridge, and full-bridge types. These types of converters are well known to the person skilled in the art. 
         [0003]      FIG. 1  shows a possible architecture of a full-bridge converter with current doubler  20 . 
         [0004]    In particular, such a converter comprises a transformer T with a primary winding T 1  and a secondary winding T 2 . In particular, the transformer T can be modelled as a first inductor coupled in parallel to the primary winding T 1 , which represents the magnetizing inductance of the transformer T, a second inductor coupled in series to the primary winding T 1 , which represents the leakage inductance of the transformer T, and an ideal transformer with a given turn ratio N:1. 
         [0005]    In the example considered, the converter  20  receives a DC voltage V in  at an input through two input terminals  202  and GND 1 , and supplies a voltage V o  at an output through two output terminals  206  and GND 2 . 
         [0006]    In general, the voltage V in  may also be obtained from an AC input current, for example, via an input stage comprising a rectifier, such as a diode or a diode bridge and possibly one or more filters, such as capacitors. 
         [0007]    In the example considered, the converter  20  comprises, on the primary side of the transformer T, an H-bridge (or full-bridge), which comprises four electronic switches Q 1 , Q 2 , Q 3 , and Q 4 , such as n-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), which can be used for selectively connecting the two terminals of the primary winding T 1  of the transformer T to the line  202  or to the ground GND 1 . 
         [0008]    In particular, in the example considered, the electronic switches Q 1  and Q 2  are coupled in series between the lines  202  and GND 1  and also the electronic switches Q 3  and Q 4  are coupled in series between the lines  202  and GND 1 . Furthermore, the intermediate point A between the switches Q 1  and Q 2  is coupled to the first terminal of the primary winding T 1 , and the intermediate point B between the switches Q 3  and Q 4  is coupled to the second terminal of the primary winding T 1 . Consequently, an H-bridge (or full-bridge) comprises two half-bridges. 
         [0009]    The converter  20  comprises, on the secondary side of the transformer T, a current doubler, which includes two inductors Lout 1 /Lout 2 , two diodes S 1 /S 2 , and an output capacitor Cout. The person skilled in the art will appreciate that, instead of the diodes S 1 /S 2 , in general, other electronic switches may also be used, such as, for example, n-channel MOSFETs, which are driven in an appropriate way. 
         [0010]    In particular, the above circuit has the purpose of transferring both of the half-waves of the oscillation at the secondary T 2  of the transformer T to the capacitor Cout. For this purpose, a first terminal of the secondary winding T 2  is coupled, through the inductor Lout 1 , to the positive terminal of the capacitor Cout, i.e., the terminal  206  and the second terminal are coupled through the inductor Lout 2  to the positive terminal of the capacitor Cout. The negative terminal of the capacitor Cout that represents the second ground GND 2 , which on account of the insulating effect of the transformer T is preferably different from the ground GND 1  and is consequently represented with a different ground symbol, is coupled through the diode S 2  to the first terminal of the secondary winding T 2  and through the diode S 1  to the second terminal of the secondary winding T 2 . 
         [0011]    Consequently, during a positive half-wave, the current flows through the inductor Lout 1 , the capacitor Cout, and the diode S 1 , and during a negative half-wave, the current flows through the inductor Lout 2 , the capacitor Cout, and the diode S 2 . 
         [0012]    Finally, the voltage on the capacitor Cout corresponds to the voltage V o  that is supplied through the output terminals  206  and GND 2 . 
         [0013]    Typically, the converter  20  comprises a control unit (not shown) that drives the switches Q 1 , Q 2 , Q 3 , and Q 4  (and possibly the switches S 1 /S 2 ). The possible forms of driving such a full-bridge converter are well known in the art, and a possible type of driving is described, for example, in the paper by Douglas Sterk, et al., “ High Frequency ZVS Self - driven Full - Bridge Using Full Integration of Magnetics ”, Applied Power Electronics Conference and Exposition, 2005 (APEC 2005), the contents of which are incorporated herein for reference for this purpose. 
         [0014]    For example, these DC-DC converters are frequently driven in resonant or quasi-resonant mode, since this offers a high efficiency of conversion for input voltages V in  (referred to as “bus voltages”) higher than 12 V, and consequently these converters are frequently used in applications where the power bus voltages are, for example, 24 V, 48 V, or 400 V. 
         [0015]    For example, frequently a first half-bridge is driven with a given duty cycle and the other half-bridge is switched at the same frequency and with a known delay, or time-shift, with respect to the first. These converters offer high efficiency because an appropriate series and/or parallel resonant network provided by dual elements (capacitance and inductance) is designed so that the switchings of the switches Q 1 -Q 4  and preferably also the switches S 1 /S 2  occur in conditions of zero voltage drop across them (zero-voltage switch—ZVS) and possibly also in condition of zero current flowing through them (zero-current switch—ZCS). For these conditions to be present, an accurate selection of the switching frequencies and of the time-shift is usually necessary. 
         [0016]    Frequently, the specifications for these converters are stringent in terms of accuracy of the output voltage V o . Consequently, to minimize the oscillations given by the resonance or by the switching frequency, the current doubler is provided with a second-order low-pass filter, i.e., the inductors Lout 1 , Lout 2  and the capacitor Cout. 
         [0017]    In general, the current-doubler rectifier (which comprises the transformer T, the inductors Lout 1 /Lout 2 , the capacitor Cout, and the switches S 1 /S 2 ) can also be used in other converters. For example, the paper by Jian Sun, et al., “ An Improved Current - Doubler Rectifier with Integrated Magnetics ”, Applied Power Electronics Conference and Exposition, 2002 (APEC 2002), shows that, instead of an H-bridge, a half-bridge and two capacitors may also be used. The person skilled in the art will appreciate that the choice of using a full-bridge or a half-bridge typically depends upon the power supplied by the converter  20 . 
         [0018]    Consequently, the resonant circuit of the converter  20  comprises the inductances of the transformer T, the inductors Lout 1 /Lout 2 , the capacitor Cout, and the capacitances of the switches Q 1 -Q 4  of the half-bridge or full-bridge. The documents cited previously show in this context the possibility of integrating the transformer T and the inductances Lout 1 , Lout 2  in a single magnetic component. For example, in  FIG. 2 a    of the paper by Jian Sun, winding of the primary is performed in the magnetic circuit (generally provided by ferromagnetic material) on the central leg where the secondary winding is present, coupling therewith and thus providing the transformer, whereas on the lateral legs of the core the resulting magnetic flux is captured by the auxiliary windings of the secondary, thus providing the inductances Lout 1  and Lout 2  (inductances L 1  and L 2  in the paper). The remaining  FIGS. 2 b  and 2 c    of the paper show similar implementations. 
         [0019]    Consequently, it is possible to obtain in a single magnetic component the transformer T and the inductances Lout 1 , Lout 2  according to the known art. 
         [0020]    In general, the resonance network of the primary is given by the parasitic capacitance through the terminals of the switches of the half-bridge or full-bridge and the parasitic or leakage inductance of the transformer T. However, as explained previously, the resonance frequency is fundamental for proper operation of the circuit, and the dependence upon the leakage inductance means having a dependence of a fundamental parameter upon the variation of the manufacturing parameters of the transformer T and of the board that contains the circuit. Another disadvantage of this approach lies in the fact that the greater the leakage inductance of the transformer T, the greater also the power losses of the transformer T. 
         [0021]    Furthermore, there are resonant converters in which proper operation of the circuit and maintenance of the ZVS conditions are ensured for a given range of values of inductance at the primary T 1  and, consequently, the magnetic integration as per the known art may prove difficult because the converter may require a real inductance on the primary. 
       SUMMARY 
       [0022]    The present disclosure provides approaches that enable one or more of the disadvantages outlined above to be addressed. 
         [0023]    With a view to achieving the aforesaid object, the subject of the present disclosure is an electronic converter. Embodiments also regard a corresponding method for designing a magnetic component. Further advantageous characteristics of the embodiments are also disclosed. 
         [0024]    As mentioned previously, one object of the present disclosure is to provide approaches that enable a magnetic circuit to be obtained that make it possible to implement the inductances of the current-doubler rectifier described previously with a magnetic component having five poles, namely, two input poles and three output poles. 
         [0025]    For example, such a magnetic component may be used in an electronic converter that comprises two input terminals and two output terminals. In particular, the converter comprises an output capacitor coupled between the two output terminals and a switching stage, such as for example, a half-bridge or full-bridge. In this case, the magnetic component comprises two input terminals and three output terminals. The two input terminals are coupled to the switching stage, in such a way that this stage can transfer current pulses to the magnetic component. The first output terminal is coupled through a first electronic switch, such as a diode, to the second output terminal of the converter (negative terminal), the second output terminal of the magnetic component is coupled to the first output terminal of the converter (positive terminal), and the third output terminal is coupled through a second electronic switch, such as a diode, to the second output terminal of the electronic converter (negative terminal). 
         [0026]    In various embodiments, the magnetic component is implemented via four transformers, where each transformer comprises a respective primary winding and a respective secondary winding. In particular, in various embodiments, the primary windings of the transformers are coupled in series between the two input terminals of the magnetic component. The secondary windings of the first and second transformers are coupled in series between the first and second output terminals of the magnetic component, and the secondary windings of the third and fourth transformers are coupled in series between the second output terminal and the third output terminal. 
         [0027]    In various embodiments, the transformers are designed in such a way that their leakage inductance is low. As will be described hereinafter, in this case, the inductance between the two input terminals of the magnetic component is given mostly by the magnetizing inductances of the transformers. 
         [0028]    In various embodiments, the first and third transformers substantially have the same turn ratio and the same magnetizing inductance, and the second and fourth transformers substantially have the same turn ratio and the same magnetizing inductance. 
         [0029]    In general, the primary and secondary windings may be coupled together in series in different configurations. However, it is desirable for the primary windings of the transformers to have substantially the same turn ratio and the same magnetizing inductance to be coupled directly in series. 
         [0030]    In various embodiments, the magnetic component comprises a magnetic core having a ferromagnetic material comprising four separate or detached zones, where the primary winding and the secondary winding of a respective transformer are arranged in each zone. For example, in various embodiments, these windings are obtained via stacked layers comprising a conductive or metal material. 
         [0031]    As will be described hereinafter, the magnetic component may be modelled as an equivalent transformer with a respective turn ratio N: 1  and a respective equivalent leakage inductance, and having two equivalent output inductances. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0032]    Embodiments of the present disclosure will now be described purely by way of non-limiting example with reference to the annexed drawings, wherein: 
           [0033]      FIG. 1  is a circuit diagram of converter of the prior art; 
           [0034]      FIG. 2  shows the inductive components of the converter of  FIG. 1 ; 
           [0035]      FIG. 3  is a circuit diagram of an embodiment of a magnetic component that is able to implement the inductive components of  FIG. 2  according to the invention; 
           [0036]      FIG. 4  illustrates a circuit diagram of an electronic converter that uses the magnetic component of  FIG. 3 ; 
           [0037]      FIG. 5  shows a condition of the circuit of  FIG. 4 ; 
           [0038]      FIG. 6  shows a different condition of the circuit of  FIG. 4 ; 
           [0039]      FIG. 7 a    is an axonometric view of a core of the magnetic component of  FIG. 3 ; 
           [0040]      FIG. 7 b    is a side elevational view of the core of the magnetic component of  FIG. 7   a;    
           [0041]      FIG. 8 a    illustrates layers that implement primary windings W 1  of the magnetic component; 
           [0042]      FIG. 8 b    illustrates layers that implement the secondary windings of the transformers Tb and Tc of the magnetic component; 
           [0043]      FIG. 8 c    illustrates layers that implement the secondary windings of the transformers Ta and Td of the magnetic component; 
           [0044]      FIG. 9 a    is a front elevational view of an embodiment of the magnetic component; 
           [0045]      FIG. 9 b    is a rear elevational view of the magnetic component of  FIG. 9 a   ; and 
           [0046]      FIG. 9 c    is a top plan view of the magnetic component of  FIG. 9   a.    
       
    
    
     DETAILED DESCRIPTION 
       [0047]    In the ensuing description, various specific details are illustrated aimed at providing an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured. 
         [0048]    Reference to “an embodiment” or “one embodiment” in the framework of the present description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in various points of this description do not necessarily refer to one and the same embodiment. Furthermore, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments. 
         [0049]    The references used herein are provided only for convenience and hence do not define the sphere of protection or the scope of the embodiments. 
         [0050]    As mentioned previously, one object of the present disclosure is to provide approaches that enable a magnetic circuit to be obtained that makes it possible to implement the inductances of the current-doubler rectifier described previously. 
         [0051]      FIG. 2  shows in this context the inductances of the current-doubler rectifier described with reference to  FIG. 1 . 
         [0052]    In particular, also in this case, the component has two input terminals A and B that are designed to be coupled to a half-bridge or full-bridge, or in general a switching stage. 
         [0053]    The terminals R 1  and R 2  are coupled to the rectifier circuits of the current doubler, i.e., the switches or diodes S 1  and S 2 , and the terminal COM are coupled to the output voltage V o , i.e., the positive terminal of the capacitor Cout, i.e., the terminal  206 . 
         [0054]    Consequently, in general, the integrated magnetic component has five terminals, namely, two input terminals and three output terminals. 
         [0055]    If the magnetizing inductance of the transformer is disregarded, this component can be described as the equivalent of an ideal transformer having a turn ratio N:1, having at the primary winding a series inductance L RES  that represents the leakage inductance of the transformer T, and at the secondary two inductances between the terminals R 1 -COM and R 2 -COM that have a value Lout 1  and Lout 2 , respectively. 
         [0056]      FIG. 3  shows a possible embodiment of an electrical circuit designed to implement the ideal component described in  FIG. 2 . 
         [0057]    In particular, in the embodiment considered, the component comprises four transformers Ta, Tb, Tc, and Td. 
         [0058]    In the embodiment considered, the primary windings of these transformers Ta-Td are coupled in series between the terminals A and B, and the secondary windings of the transformers Ta-Td are coupled in series between the terminals R 1  and R 2 , where the intermediate point between the secondary winding of the second transformer Tb and the secondary winding of the third transformer Tc is coupled to the terminal COM. 
         [0059]    Consequently, the transformers Ta and Tb can also be swapped around, as likewise the transformers Tc and Td. In fact, in general, it is sufficient for the primary windings of the four transformers Ta-Td to be coupled in series between the terminals A and B, for the secondary windings of the transformers Ta and Td to be coupled in series between the terminals R 1  and COM, and for the secondary windings of the transformers Tc and Td to be coupled in series between the terminals R 2  and COM. 
         [0060]    In one embodiment, the circuit is made up of two types of transformers electrically modelled by a turn ratio equal to N 1 :1 and N 2 :1 and by their respective magnetizing inductances L 1  and L 2 , i.e., their equivalent output inductances. Consequently, in the embodiment considered, it is assumed that the transformers Ta-Td are designed for having an optimal efficiency, i.e., a negligible equivalent leakage inductance, which is consequently omitted in the circuit representation, for instance, lower than 100 nH. 
         [0061]    In particular, one of the transformers Ta or Tb is of the first type and the other is of the second type, and likewise one of the transformers To or Td is of the first type and the other is of the second type. For example, in the embodiment considered, the transformers Ta and Tc are of the first type (N 1 :1, L 1 ) and the transformers Tb and Td are of the second type (N 2 :1, L 2 ). 
         [0062]    As will be described hereinafter, from this circuit it is possible to obtain the main parameters of the ideal equivalent component of  FIG. 2  by using the circuit equations. In these equations (since it is a calculation of impedances seen at the terminals of the component), since the node COM is coupled to the voltage V o , i.e., a node at extremely low impedance as represented in  FIG. 1 , it can also be replaced with the ground GND 2 . 
         [0063]      FIG. 4  shows in this context the generalized scheme of a half-bridge converter or a full-bridge converter, which substantially results from the combination of the circuit of  FIG. 1  with the circuit of  FIG. 3 . 
         [0064]    On the basis of the above circuit, the circuit equations may be applied to obtain the mathematical expressions that reconstruct the parameters of  FIG. 2 , such as L RES , N, Lout 1 , and Lout 2 . 
         [0065]    In particular, during operation of the converter and according to the switching state of the switches on the primary winding (half-bridge or full-bridge) it is possible to identify two operating areas: ZVS or magnetization of the magnetic circuit, and resonance region. 
       ZVS and Magnetization of the Circuit 
       [0066]    As shown in  FIG. 5 , during this step, it is necessary to calculate the impedance at the input between the terminals A and B while the switches S 1  and S 2  of the current doubler are closed and hence R 1  and R 2  are grounded. In this case, the input impedance should be given by the resonance inductance L RES . 
         [0067]    Applying the circuit equation of the voltage mesh at input for the voltages V 1 , V 2 , V 3 , and V 4  respectively across the secondary windings of the transformers Ta, Tb, Tc, and Td, will obtain 
         [0000]    
       
      
       V 
       IN 
       =N 
       1 
       ·V 
       1 
       +N 
       2 
       ·V 
       2 
       +N 
       1 
       ·V 
       3 
       +N 
       2 
       ·V 
       4  
      
     
         [0000]    
       
      
       V 
       2 
       =−V 
       1  
      
     
         [0000]    
       
      
       V 
       4 
       =−V 
       3  
      
     
         [0000]      whence 
         [0000]        V   IN =( V   1   +V   3 )·( N   1   −N   2 )
 
         [0068]    Applying the circuit equation of the currents I CC1  and I CC2  that flow through the secondary windings of the transformers Ta/Tb and Tc/Td, respectively, will obtain 
         [0000]    
       
      
       N 
       1 
       ·I 
       IN 
       +I 
       CC1 
       =I 
       L1  
      
     
         [0000]    
       
      
       N 
       2 
       ·I 
       IN 
       +I 
       CC1 
       =I 
       L2  
      
     
         [0000]    
       
      
       N 
       1 
       ·I 
       IN 
       +I 
       CC2 
       =I 
       L1  
      
     
         [0000]    
       
      
       N 
       2 
       ·I 
       IN 
       +I 
       CC2 
       =I 
       L2  
      
     
         [0069]    From these equations it follows that I CC1 =I CC2 =I CC  and consequently also the equalities between the voltages V 1 =V 3  and V 2 =V 4  apply so that no current generated in these conditions exits from the node COM towards the output. Hence, the equations become 
         [0000]    
       
      
       N 
       1 
       ·I 
       IN 
       +I 
       CC1 
       =I 
       L1  
      
     
         [0000]    
       
      
       N 
       2 
       ·I 
       IN 
       +I 
       CC1 
       =I 
       L2  
      
     
         [0000]        V   IN =2· V   1 ·( N   1   −N   2 )
 
         [0070]    By solving the system of equations, will obtain 
         [0000]    
       
         
           
             
               I 
               IN 
             
             = 
             
               
                 
                   I 
                   
                     L 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 - 
                 
                   I 
                   
                     L 
                      
                     
                         
                     
                      
                     2 
                   
                 
               
               
                 
                   N 
                   1 
                 
                 - 
                 
                   N 
                   2 
                 
               
             
           
         
       
       
         
           
             
               V 
               IN 
             
             = 
             
               2 
               · 
               
                 V 
                 1 
               
               · 
               
                 ( 
                 
                   
                     N 
                     1 
                   
                   - 
                   
                     N 
                     2 
                   
                 
                 ) 
               
             
           
         
       
       
         
           
             
               V 
               1 
             
             = 
             
               
                 V 
                 IN 
               
               
                 2 
                 · 
                 
                   ( 
                   
                     
                       N 
                       1 
                     
                     - 
                     
                       N 
                       2 
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0071]    Passing to the s-domain, will obtain 
         [0000]    
       
         
           
             
               I 
               
                 L 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   V 
                   1 
                 
                 
                   sL 
                   1 
                 
               
               = 
               
                 
                   V 
                   IN 
                 
                 
                   s 
                    
                   
                       
                   
                    
                   
                     2 
                     · 
                     
                       L 
                       1 
                     
                     · 
                     
                       ( 
                       
                         
                           N 
                           1 
                         
                         - 
                         
                           N 
                           2 
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
       
         
           
             
               I 
               
                 L 
                  
                 
                     
                 
                  
                 2 
               
             
             = 
             
               
                 
                   V 
                   2 
                 
                 
                   sL 
                   2 
                 
               
               = 
               
                 
                   - 
                   
                     
                       V 
                       1 
                     
                     
                       sL 
                       2 
                     
                   
                 
                 = 
                 
                   - 
                   
                     
                       V 
                       IN 
                     
                     
                       s 
                        
                       
                           
                       
                        
                       
                         2 
                         · 
                         
                           L 
                           2 
                         
                         · 
                         
                           ( 
                           
                             
                               N 
                               1 
                             
                             - 
                             
                               N 
                               2 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
             
           
         
       
     
         [0072]    and the input impedance can be calculated as follows: 
         [0000]    
       
         
           
             
               
                 V 
                 IN 
               
               
                 I 
                 IN 
               
             
             = 
             
               
                 sL 
                 RES 
               
               = 
               
                 
                   2 
                   · 
                   s 
                 
                  
                 
                   
                     
                       
                         L 
                         1 
                       
                       · 
                       
                         L 
                         2 
                       
                     
                     
                       
                         L 
                         1 
                       
                       + 
                       
                         L 
                         2 
                       
                     
                   
                   · 
                   
                     
                       ( 
                       
                         
                           N 
                           1 
                         
                         - 
                         
                           N 
                           2 
                         
                       
                       ) 
                     
                     2 
                   
                 
               
             
           
         
       
     
         [0073]    Hence, the equivalent inductance seen at input with the output in short-circuit is: 
         [0000]    
       
         
           
             
               L 
               RES 
             
             = 
             
               2 
               · 
               
                 
                   
                     L 
                     1 
                   
                   · 
                   
                     L 
                     2 
                   
                 
                 
                   
                     L 
                     1 
                   
                   + 
                   
                     L 
                     2 
                   
                 
               
               · 
               
                 
                   ( 
                   
                     
                       N 
                       1 
                     
                     - 
                     
                       N 
                       2 
                     
                   
                   ) 
                 
                 2 
               
             
           
         
       
     
         [0074]    Finally, the short-circuit current I CC  is calculated that circulates in the secondary taking into consideration that the switches S 1 /S 2  of the current doubler are closed and the poles R 1 /R 2  are at ground. From the ratio between the currents in the secondary and in the primary winding, will obtain the equivalent turn ratio of the magnetic component (parameter N of  FIG. 3 ). 
         [0075]    The short-circuit current I CC  circulating in the secondary in the s-domain is 
         [0000]    
       
         
           
             
               I 
               CC 
             
             = 
             
               
                 
                   I 
                   
                     L 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 - 
                 
                   
                     N 
                     1 
                   
                   · 
                   
                     I 
                     IN 
                   
                 
               
               = 
               
                 
                   
                     V 
                     IN 
                   
                   · 
                   
                     
                       
                         
                           
                             L 
                             2 
                           
                           
                             
                               L 
                               1 
                             
                             + 
                             
                               L 
                               2 
                             
                           
                         
                         · 
                         
                           ( 
                           
                             
                               N 
                               1 
                             
                             - 
                             
                               N 
                               2 
                             
                           
                           ) 
                         
                       
                       - 
                       
                         N 
                         1 
                       
                     
                     
                       s 
                       · 
                       2 
                       · 
                       
                         
                           
                             L 
                             1 
                           
                           · 
                           
                             L 
                             2 
                           
                         
                         
                           
                             L 
                             1 
                           
                           + 
                           
                             L 
                             2 
                           
                         
                       
                       · 
                       
                         
                           ( 
                           
                             
                               N 
                               1 
                             
                             - 
                             
                               N 
                               2 
                             
                           
                           ) 
                         
                         2 
                       
                     
                   
                 
                 = 
                 
                   
                     - 
                     
                       V 
                       IN 
                     
                   
                   · 
                   
                     
                       
                         
                           N 
                           1 
                         
                         · 
                         
                           L 
                           1 
                         
                       
                       + 
                       
                         
                           N 
                           2 
                         
                          
                         
                           L 
                           2 
                         
                       
                     
                     
                       s 
                       · 
                       2 
                       · 
                       
                         L 
                         1 
                       
                       · 
                       
                         L 
                         2 
                       
                       · 
                       
                         
                           ( 
                           
                             
                               N 
                               1 
                             
                             - 
                             
                               N 
                               2 
                             
                           
                           ) 
                         
                         2 
                       
                     
                   
                 
               
             
           
         
       
     
         [0076]    From this relation, and substituting the expression of L RES , will obtain 
         [0000]    
       
         
           
             
               I 
               CC 
             
             = 
             
               
                 - 
                 
                   
                     V 
                     IN 
                   
                   
                     sL 
                     RES 
                   
                 
               
               · 
               
                 
                   
                     
                       N 
                       1 
                     
                     · 
                     
                       L 
                       1 
                     
                   
                   + 
                   
                     
                       N 
                       2 
                     
                      
                     
                       L 
                       2 
                     
                   
                 
                 
                   
                     L 
                     1 
                   
                   + 
                   
                     L 
                     2 
                   
                 
               
             
           
         
       
     
         [0077]    The turn ratio N of the equivalent transformer is obtained as the ratio of the current in the secondary to the current in the primary winding, as follows: 
         [0000]    
       
         
           
             N 
             = 
             
               
                 
                   I 
                   CC 
                 
                 
                   
                     V 
                     IN 
                   
                   
                     sL 
                     RES 
                   
                 
               
               = 
               
                 
                   
                     
                       N 
                       1 
                     
                     · 
                     
                       L 
                       1 
                     
                   
                   + 
                   
                     
                       N 
                       2 
                     
                      
                     
                       L 
                       2 
                     
                   
                 
                 
                   
                     L 
                     1 
                   
                   + 
                   
                     L 
                     2 
                   
                 
               
             
           
         
       
     
       Resonance Region 
       [0078]    As shown in  FIG. 6 , during this step the converter maintains the primary side shorted, appropriately driving the half-bridge or the full-bridge, and the secondary side is open, i.e., with the switches S 1  and S 2  of the current doubler alternatively open. To obtain the parameters Lout 1  and Lout 2  with reference to  FIG. 3 , it is sufficient to note that at the primary winding there is no voltage drop, since the primary winding is shorted, and necessarily no current I IN  flows in the primary winding, and the current I OUTX  that flows through the secondary side of the transformer Ta corresponds to the current I L1  supplied by the magnetizing inductance L 1 . Thus, obtaining 
         [0000]    
       
      
       N 
       1 
       ·I 
       IN 
       +I 
       OUTX 
       =I 
       L1  
      
     
         [0000]        I   IN =0 
         [0000]    
       
      
       I 
       OUTX 
       =I 
       L1  
      
     
         [0079]    Consequently the inductance L out  seen at output between the terminals R 1  and COM is 
         [0000]    
       
         
           
             
               V 
               SECX 
             
             = 
             
               
                 V 
                 
                   L 
                    
                   
                       
                   
                    
                   1 
                 
               
               + 
               
                 V 
                 
                   L 
                    
                   
                       
                   
                    
                   2 
                 
               
             
           
         
       
       
         
           
             
               V 
               
                 L 
                  
                 
                     
                 
                  
                 2 
               
             
             = 
             
               
                 sL 
                 2 
               
               · 
               
                 I 
                 
                   L 
                    
                   
                       
                   
                    
                   1 
                 
               
             
           
         
       
       
         
           
             
               V 
               SECX 
             
             = 
             
               
                 
                   sL 
                   1 
                 
                 · 
                 
                   I 
                   
                     L 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
               + 
               
                 
                   sL 
                   2 
                 
                 · 
                 
                   I 
                   
                     L 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 V 
                 SECX 
               
               
                 I 
                 OUTX 
               
             
             = 
             
               s 
               · 
               
                 ( 
                 
                   
                     L 
                     1 
                   
                   + 
                   
                     L 
                     2 
                   
                 
                 ) 
               
             
           
         
       
       
         
           
             
               L 
               
                 OUT 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 L 
                 1 
               
               + 
               
                 L 
                 2 
               
             
           
         
       
     
         [0080]    where V SECX  is the voltage between the terminals COM and R 1  that is applied to the capacitor Cout, V L1  and V L2  are the voltages across the secondary windings of the transformers Ta and Tb, respectively, and I L1  is the current that flows through the secondary windings of the transformer Ta, which necessarily corresponds to the current I L2  that flows through the secondary windings of the transformer Tb. 
         [0081]    Similar considerations apply for calculation of the output inductance L out2  between the terminals COM and R 2  on the second output branch for which the same result is obtained, by symmetry. 
         [0082]    To sum up, the magnetic circuit behaves as represented schematically in  FIG. 3  and has the following concentrated parameters: 
         [0000]    
       
         
           
             
               L 
               RES 
             
             = 
             
               2 
               · 
               
                 
                   
                     L 
                     1 
                   
                   · 
                   
                     L 
                     2 
                   
                 
                 
                   
                     L 
                     1 
                   
                   + 
                   
                     L 
                     2 
                   
                 
               
               · 
               
                 
                   ( 
                   
                     
                       N 
                       1 
                     
                     - 
                     
                       N 
                       2 
                     
                   
                   ) 
                 
                 2 
               
             
           
         
       
       
         
           
             N 
             = 
             
               
                 
                   
                     N 
                     1 
                   
                   · 
                   
                     L 
                     1 
                   
                 
                 + 
                 
                   
                     N 
                     2 
                   
                    
                   
                     L 
                     2 
                   
                 
               
               
                 
                   L 
                   1 
                 
                 + 
                 
                   L 
                   2 
                 
               
             
           
         
       
       
         
           
             
               L 
               OUT 
             
             = 
             
               
                 L 
                 1 
               
               + 
               
                 L 
                 2 
               
             
           
         
       
     
         [0083]    For instance, the inductances L 1  and L 2  may be between 10 and 500 nH, preferably between 20 and 200 nH. For example, assuming an inductance L 1  of 45 nH and assuming an inductance L 2  of 75 nH, the inductances Lout 1  and Lout 2  would be 120 nH. 
         [0084]    From these equations, it is also possible to appreciate an advantage of the present approach as compared to the implementations proposed in the paper by Jian Sun that are substantially based upon the use of a magnetic component with just two secondary windings. In particular, in the paper by Jian Sun, the magnetic component is designed in such a way that the inductance L RES  on the primary side (that serves for the resonance at the primary side) will be implemented with the magnetic flux in the winding of the component, i.e., with the leakage inductance, which increases the losses of the component. In the approaches described herein, the magnetic component comprises four transformers substantially independent of one another, and the inductance L RES  on the primary side is implemented with the magnetic flux in the core/airgap of the component, i.e., with the magnetizing inductances L 1  and L 2  of the transformers Ta, Td, as follows: 
         [0000]    
       
         
           
             
               L 
               RES 
             
             = 
             
               2 
               · 
               
                 
                   
                     L 
                     1 
                   
                   · 
                   
                     L 
                     2 
                   
                 
                 
                   
                     L 
                     1 
                   
                   + 
                   
                     L 
                     2 
                   
                 
               
               · 
               
                 
                   ( 
                   
                     
                       N 
                       1 
                     
                     - 
                     
                       N 
                       2 
                     
                   
                   ) 
                 
                 2 
               
             
           
         
       
     
         [0085]    The person skilled in the art will appreciate that the above equation applies in the case where the component comprises four transformers with the respective magnetizing inductances, i.e., L 1  and L 2 &gt;0. In this context, the phrase “substantially independent transformers” is meant to indicate a component that comprises four zones detached from one another where associated to each zone is a respective primary winding and a respective secondary winding. For example, this does not apply to the component proposed by Jian Sun, because even though the windings can be virtually divided into a number of stretches, these do not implement independent transformers. 
       Variation of the Parameters 
       [0086]    In this section, the effect of the tolerances of the magnetizing inductances is determined purely by way of illustration (the turn ratios are considered deterministic). The inductances L 1  and L 2  are considered not correlated with one another. 
         [0000]    
       
         
           
             
               ∂ 
               
                 L 
                 RES 
               
             
             = 
             
               
                 2 
                 · 
                 
                   
                     L 
                     2 
                     2 
                   
                   
                     
                       ( 
                       
                         
                           L 
                           1 
                         
                         + 
                         
                           L 
                           2 
                         
                       
                       ) 
                     
                     2 
                   
                 
                 · 
                 
                   
                     ( 
                     
                       
                         N 
                         1 
                       
                       - 
                       
                         N 
                         2 
                       
                     
                     ) 
                   
                   2 
                 
                 · 
                 
                   ∂ 
                   
                     L 
                     1 
                   
                 
               
               + 
               
                 2 
                 · 
                 
                   
                     L 
                     1 
                     2 
                   
                   
                     
                       ( 
                       
                         
                           L 
                           1 
                         
                         + 
                         
                           L 
                           2 
                         
                       
                       ) 
                     
                     2 
                   
                 
                 · 
                 
                   
                     ( 
                     
                       
                         N 
                         1 
                       
                       - 
                       
                         N 
                         2 
                       
                     
                     ) 
                   
                   2 
                 
                 · 
                 
                   ∂ 
                   
                     L 
                     2 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 u 
                 2 
               
                
               
                 ( 
                 
                   L 
                   RES 
                 
                 ) 
               
             
             = 
             
               
                 4 
                 · 
                 
                   
                     L 
                     2 
                     4 
                   
                   
                     
                       ( 
                       
                         
                           L 
                           1 
                         
                         + 
                         
                           L 
                           2 
                         
                       
                       ) 
                     
                     4 
                   
                 
                 · 
                 
                   
                     ( 
                     
                       
                         N 
                         1 
                       
                       - 
                       
                         N 
                         2 
                       
                     
                     ) 
                   
                   4 
                 
                 · 
                 
                   
                     u 
                     2 
                   
                    
                   
                     ( 
                     
                       L 
                       1 
                     
                     ) 
                   
                 
               
               + 
               
                 4 
                 · 
                 
                   
                     L 
                     1 
                     4 
                   
                   
                     
                       ( 
                       
                         
                           L 
                           1 
                         
                         + 
                         
                           L 
                           2 
                         
                       
                       ) 
                     
                     4 
                   
                 
                 · 
                 
                   
                     ( 
                     
                       
                         N 
                         1 
                       
                       - 
                       
                         N 
                         2 
                       
                     
                     ) 
                   
                   4 
                 
                 · 
                 
                   
                     u 
                     2 
                   
                    
                   
                     ( 
                     
                       L 
                       2 
                     
                     ) 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 u 
                  
                 
                   ( 
                   
                     L 
                     RES 
                   
                   ) 
                 
               
               = 
               
                 ∂ 
                 
                   L 
                   RES 
                 
               
             
             ; 
             
               
                 u 
                  
                 
                   ( 
                   
                     L 
                     1 
                   
                   ) 
                 
               
               = 
               
                 ∂ 
                 
                   L 
                   1 
                 
               
             
             ; 
             
               
                 u 
                  
                 
                   ( 
                   
                     L 
                     2 
                   
                   ) 
                 
               
               = 
               
                 ∂ 
                 
                   L 
                   2 
                 
               
             
           
         
       
       
         
           
             
               
                 u 
                 R 
                 2 
               
                
               
                 ( 
                 
                   L 
                   RES 
                 
                 ) 
               
             
             = 
             
               
                 
                   
                     L 
                     2 
                     2 
                   
                   
                     
                       ( 
                       
                         
                           L 
                           1 
                         
                         + 
                         
                           L 
                           2 
                         
                       
                       ) 
                     
                     2 
                   
                 
                 · 
                 
                   
                     u 
                     R 
                     2 
                   
                    
                   
                     ( 
                     
                       L 
                       1 
                     
                     ) 
                   
                 
               
               + 
               
                 
                   
                     L 
                     1 
                     2 
                   
                   
                     
                       ( 
                       
                         
                           L 
                           1 
                         
                         + 
                         
                           L 
                           2 
                         
                       
                       ) 
                     
                     2 
                   
                 
                 · 
                 
                   
                     u 
                     R 
                     2 
                   
                    
                   
                     ( 
                     
                       L 
                       2 
                     
                     ) 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 
                   u 
                   R 
                 
                  
                 
                   ( 
                   
                     L 
                     RES 
                   
                   ) 
                 
               
               = 
               
                 
                   ∂ 
                   
                     L 
                     RES 
                   
                 
                 
                   L 
                   RES 
                 
               
             
             ; 
             
               
                 
                   u 
                   R 
                 
                  
                 
                   ( 
                   
                     L 
                     1 
                   
                   ) 
                 
               
               = 
               
                 
                   ∂ 
                   
                     L 
                     1 
                   
                 
                 
                   L 
                   1 
                 
               
             
             ; 
             
               
                 
                   u 
                   R 
                 
                  
                 
                   ( 
                   
                     L 
                     2 
                   
                   ) 
                 
               
               = 
               
                 
                   ∂ 
                   
                     L 
                     2 
                   
                 
                 
                   L 
                   2 
                 
               
             
           
         
       
     
         [0087]    Assuming the same tolerances for both of the inductances we obtain 
         [0000]    
       
         
           
             
               
                 u 
                 R 
               
                
               
                 ( 
                 
                   L 
                   RES 
                 
                 ) 
               
             
             = 
             
               
                 
                   
                     
                       L 
                       1 
                       2 
                     
                     + 
                     
                       L 
                       2 
                       2 
                     
                   
                 
                 
                   ( 
                   
                     
                       L 
                       1 
                     
                     + 
                     
                       L 
                       2 
                     
                   
                   ) 
                 
               
               · 
               
                 
                   u 
                   R 
                 
                  
                 
                   ( 
                   L 
                   ) 
                 
               
             
           
         
       
     
         [0088]    Consequently, the tolerance of the inductance L RES  is lower than the variation of the output inductance and hence the procedure for manufacturing the magnetic component. 
         [0089]    This provides an advantage of the magnetic circuit according to the present disclosure, whereby not only is an inductance on the primary winding obtained having the desired value independent of the leakage inductance and hence of the efficiency of the transformer, but also the precision of the value of inductance is better than the one given by the manufacturing tolerances of L 1  and L 2 . 
       Example of an Embodiment 
       [0090]      FIGS. 7 a  and 7 b    show a possible example of embodiment of a magnetic component having N 1 =2 and N 2 =7. 
         [0091]    In particular, in the embodiment considered, to reduce the length of the windings and hence the power losses due to the resistance thereof, the turn ratios N 1  and N 2  can be halved. Consequently, in the embodiment considered, the transformers Ta and Td have a turn ratio 1:0.5 and the transformers Tb and Tc have a turn ratio 3.5:0.5. 
         [0092]    In the embodiment considered, the magnetic component that implements the transformers Ta-Td is provided via a structure with layers that are positioned around a core  80 . 
         [0093]    For example,  FIG. 7 a    is an axonometric view of a possible embodiment of the core  80 . In particular, in the embodiment considered, the core  80  comprises three portions  802 ,  804 , and  806  that can be obtained also separately and fixed together during assembly. In particular, the lateral portions  802  and  806  are shaped like an E, and the central portion  804  is a plate. 
         [0094]      FIG. 7 b    shows a side view of the complete core  80 . In particular, the portions  802  and  806  are configured in such a way that the core  80  has spaces A 1 , A 2  (referred to as “airgaps”) between the outer legs of the E-shaped portions ( 802  and  806 ) and the central plate  804 , i.e., the lateral portions of the portions  802 / 806  are shorter than the central leg. These airgaps A 1 , A 2  are designed so as to obtain the desired inductances L 1  and L 2 . In particular, in the embodiment considered, the bottom airgap A 2  will determine L 1 , whereas the top airgap A 1  will determine L 2 . In various embodiments, the portions  802  and  806  have the same width, but can have different heights, i.e., the central legs can have different lengths in such a way that a different number of layers can be obtained for the portions  802  and  806 . 
         [0095]      FIGS. 8 a  to 8 c    show possible embodiments of the layers that implement the primary windings W 1  ( FIG. 8 a   ), the secondary windings of the transformers Tb and Tc designated by the reference W 2  ( FIG. 8 b   ), and the secondary windings of the transformers Ta and Td designated by the reference W 3  ( FIG. 8 c   ). 
         [0096]    In the embodiment considered, the layers have a width that is smaller than the width between the lateral legs of the portions  802  and  804 . Furthermore, the layers have a central opening for the central leg of the portions  802  and  804 . 
         [0097]    Finally,  FIGS. 9 a  to 9 c    show, respectively, the view from the primary side, from the secondary side, and from above of the entire magnetic component. 
         [0098]    In particular, in the embodiment considered, set between the portion  802  and the portion  804  of the core  80  is a layered structure that implements the transformers Tb and Td, and set between the portion  804  and the portion  806  of the core  80  is a layered structure that implements the transformers Ta and Tc. For example, the respective layers can be slid over the central leg of the portions  802  and  806 , and the portions  802  and  806  can then be fixed to the central plate  804 . For example, the layered structure may be obtained via a stack of printed circuit boards (PCB) or a multi-layer PCB. 
         [0099]    For example, in the case of the number of turns referred to previously, the top layered structure comprises seven layers of the primary winding W 1 . In particular, the winding starts from an electrical contact  900 , which is coupled to the terminal A and develops via appropriate electrical connections between the individual layers W 1  around the top central leg horizontally for seven turns (see in particular  FIG. 9 a   ). The connection proceeds through a vertical electrical connection  902  and performs a further two turns around the bottom central leg with the layers W 1  and is finally coupled, through an electrical connection  904 , to the terminal B. 
         [0100]    Consequently, the above windings provide the connection in series of the primary windings shown in  FIG. 7 , which in the specific case correspond to the sequence Tb, Td, Tc, Ta. 
         [0101]    In particular, in the embodiment considered, the layers W 1  in the bottom part are coupled together in such a way that the current flux is opposite to the current flux in the layers W 1  in the top part. Consequently, as represented schematically in  FIG. 9 a   , a current that traverses the layers W 1  will generate two magnetic fluxes MFa and MFc in the bottom part, which have a direction opposite to that of the corresponding magnetic fluxes MFb and MFd generated in the top part of the core  80 , and consequently there is a cancelling-out of magnetic flux, with consequent reduction of the power losses of the component. 
         [0102]    The magnetic flux generated by the winding W 1  in the top part is captured by the secondary W 2 , the winding of which is made up, for example, of five layers coupled in parallel, which provide together half a turn (i.e., 0.5) and are coupled via an electrical contact  906  to the central node COM (see  FIG. 9 b   ). In general, even just one layer W 2  could be sufficient, but a plurality of layers coupled in parallel is advantageous to reduce the electrical resistance of the connection. For example, in the embodiment considered, the layered scheme has the structure W 2 , W 1 , W 1 , W 2 , W 1 , W 2 , W 1 , W 1 , W 2 , W 1 , W 1 , W 2 . 
         [0103]    Consequently, the top structure provides the transformers Tb and Td with the inductance L 2 . For this purpose, the layers W 1  that provide the primary windings have shapes that envelop almost completely the central leg of the portion  802  (except for a small portion for the connections between the layers W 1 ) in such a way as to create substantially a helix (see  FIG. 9 a   ). 
         [0104]    In the embodiment considered, the layers W 2  that provide the secondary windings of the transformers Tb and Td are obtained via two strips W 2   a  and W 2   b  that can also be coupled together by connection to the contact  906 , i.e., the terminal COM. For example, as shown in  FIG. 8 b   , U-shaped profiles may be used for this purpose for the layers W 2 . 
         [0105]    Likewise, the magnetic flux generated by the winding W 1  in the bottom part is captured by the secondary W 3 . In particular, in the embodiment considered, the layer W 3  that provides the secondary windings of the transformers Ta and Tc in the bottom structure comprises two strips W 3   a  and W 3   b  that are independent; i.e., the layer comprises two lateral portions W 3   a  and W 3   b  that are not coupled together (as opposed to what occurs for the layer W 2 ). Also in this case, a number of layers W 3  may be provided, for example two layers, which are coupled in parallel and together provide half a turn, i.e., 0.5 turns. 
         [0106]    The two windings W 3   a  and W 3   b  of the layer W 3  are coupled via respective electrical connections  908  and  910  to the terminals R 1  and R 2  (see  FIG. 9 b   ). 
         [0107]    Finally, two further electrical contacts  912  and  914  are provided that form the connections between the secondary windings of the transformers Ta-Td. In particular, the connection  912  connects the part W 2   a  of the layer W 2  that provides the secondary of the transformer Tb to the part W 3   a  of the layer W 3  that provides the secondary of the transformer Ta, and the connection  914  connects the part W 2   b  of the layer W 2  that provides the secondary of the transformer Td to the part W 3   b  of the layer W 3  that provides the secondary of the transformer Tc. 
         [0108]    Consequently, in the embodiment considered, the secondary windings of the transformers Ta-Td are obtained via a single respective half turn (W 2   a , W 2   b , W 3   a  or W 3   b ), obtained for example via a strip of a metal material. This half turn may be obtained also from a plurality of layers coupled in parallel, for example to reduce the electrical resistance. The number of turns of the primary winding W 1  in the top part and in the bottom part are sized accordingly, taking into account that a single turn of the layer W 1  corresponds to half a turn for the transformer Tb and half a turn for the transformer Td, and likewise half a turn for the transformer Ta and half a turn for the transformer Tc. Consequently, the number of layers W 1  coupled in series will correspond to the number N 2  for the top part and to the number N 1  for the bottom part. 
         [0109]    Consequently, in the embodiment considered, no complex connections are required for connecting the respective portions W 2   a , W 2   b , W 3   a  and W 3   b  together in series (as in any case occurs for the primary winding). 
         [0110]    Thanks to the above connection in parallel, the contacts  906 ,  908 ,  910 ,  912  and/or  914  can also perform a function of mechanical support for the layers. For example, in one embodiment, the contacts  900 ,  904 ,  906 ,  908 , and  910  may be fixed with respect to the core  80 , for example via a base plate, for instance made of a plastic material. In this case, the contacts  908  and  910  can support the layers W 3 , and the contact  906  can support the layers W 2 . The contacts  912  and  914  can further block the layers W 2  and W 3 . 
         [0111]    Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined in the ensuing claims. 
         [0112]    For example, the person skilled in the art will appreciate that numerous variants are possible in the choice of N 1  and N 2 , in the construction and alternation of the primary and secondary windings, in the determination of L 1  and L 2 , which in general could be set also in some other way and not via the airgap.