Abstract:
Undersired glitches in output signals from TSPC- 1  flip-flop circuits having an output stage comprising an node and a second node are removed by precharging the second node (prior to a clock transition) to a value desired at the output node during a period following the clock transition, and connecting the output node to the second node upon such clock transition. Corrective circuitry illustratively comprising two NMOS transistors added to the output stage and receiving an input reflecting the desired future output is active during a portion of the operating cycle when the output stage exhibits a high impedance tristate condition.

Description:
RELATED APPLICATIONS 
     The present application is related to concurrently filed non-provisional applications: 
     (i) by A. W. Hietala entitled Fractional-N Modulation with Analog IQ Interface; 
     (ii) by S. R. Humphreys and B. T. Hunt entitled Dual-Modulus Prescaler; 
     (iii) by A. W. Hietala and S. R. Humphreys entitled Fractional-N Synthesizer with Improved Noise Performance; and 
     (iv) by A. W. Hietala and S. R. Humphreys entitled Accumulator with Programmable Full-Scale Range, which non-provisional applications are assigned to the assignee of the present invention, and are hereby incorporated in the present application as if set forth in their entirety herein. 
     FIELD OF THE INVENTION 
     The present invention relates to digital logic circuits. More particularly, the present invention relates to dynamic flip-flop circuits. Still more particularly, the present invention relates to true single-phase dynamic flip-flop circuits. 
     BACKGROUND OF THE INVENTION 
     The class of logic circuits known as dynamic logic circuits has gained considerable favor in recent years by offering advantages in many applications in speed and power dissipation when compared with many prior circuit techniques. See, for example, J. M. Rabaey,  Digital Integrated Circuits , Prentice-Hall, 1996, especially pp. 222-234 and 347-363. Early dynamic flip-flops employed a two-phase clock controlling operations in precharge and evaluation modes of operation. 
     More recently, a variety of so-called true single-phase clock (TSPC) dynamic circuits have provided increased flexibility in designs while maintaining speed and power advantages. See, J. Yuan and C. Svensson, “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,”  IEEE J Solid-State Circuits , vol. 32, pp. 62-69, January, 1997, and Rabaey, supra, at pp. 359-363. 
     FIG. 1 shows a prior art TSPC- 1  full-latch flip-flop (sometimes, TSPC 1 FL, but hereinafter TSPC- 1  flip-flop) of a type described generally in the above-cited paper by Yuan and Svensson. This circuit operates as a negative edge-triggered flip-flop that is advantageously viewed as comprising three CMOS stages: an input stage (from input D to node A), a middle stage (from node A to node B), and an output stage (from node B to output /Q). In FIG. 1, the MPi, i=1-4 are PMOS devices and the MNj,j=1-6 are NMOS devices. 
     Table 1 illustrates operation of the respective stages of the circuit of FIG. 1 during high and low clock phases. 
     
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Clock 
                 Input Stage 
                 Middle Stage 
                 Output Stage 
               
               
                   
                   
               
             
             
               
                   
                 High 
                 Evaluate 
                 Invert 
                 Tristate 
               
               
                   
                 Low 
                 Precharge 
                 Tristate 
                 Invert 
               
               
                   
                   
               
             
          
         
       
     
     In Table 1, tristate refers to a high impedance state that effectively disconnects devices MP 4  and MN 5  from output lead /Q, (as well as MP 2  and MN 3  from node B) in accordance with standard industry usage. 
     FIG. 2 shows waveforms appearing over time at identified locations in the circuit of FIG. 1 in relation to an input clock signal (CLK). The output at /Q is updated at each high-to-low transition of CLK, at which time the output stage changes from a tristate holding state to operation as a CMOS inverter in accordance with Table 1. The circuit of FIG. 1 avoids one glitch that occurs due to charge sharing when an input at node D remains low for more than one cycle of CLK. See further, Q. Huang and R. Rogenmoser, “Speed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks,”  IEEE J Solid-State Circuits , vol. 31, pp. 456-465, March 1996. 
     However, the TSPC- 1  flip-flop of FIG. 1 exhibits another glitch in high frequency operation across process and environmental variations that arises from a different mechanism than that identified by Huang et al., cited above. To illustrate this latter glitch it proves useful to consider the following example. Assume the clock signal is high and the D input signal is at a logic high. Also assume that the output (/Q) is currently holding a low logic level during its tristate mode. Under these conditions the input stage has discharged so that node A is a logic low and the middle stage is performing the function of an inverter so that node B is a logic high. The output stage is in the tristate mode with the output holding a logic low signal from the previous low phase of the input clock. 
     Since the D input is at a logic high, when the clock transitions from high to low, the /Q output value should remain at a logic low as the output stage transitions from tristate operation to inverter operation. However, the /Q output signal will exhibit a glitch where the output logic low value spikes high on the high-to-low transition of CLK before returning to the correct logic low value after the clock settles low. This is shown in the /Q waveform of FIG. 2 at reference numeral  3 . Across temperature and process variations, the magnitude of this glitch is large enough to improperly trigger following logic stages. 
     It has previously been found that proper operation of TSPC- 1  flip-flops can be improved by judiciously choosing sizes of critical transistors to reduce glitches. Unfortunately, most transistors in TSPC- 1  flip-flops have conflicting sizing requirements; roles played by individual transistors change, e.g., from drivers to loads, and vice versa, with clock phase changes. Thus, for a given clock phase, a particular transistor may function as a driver (indicating that it should have a relatively large size). In contrast, the same transistor may switch roles and function as a load (indicating that the it should have a relatively small size) on the next phase of the clock. Therefore, sizing of transistors in a TSPC- 1  flip-flop to achieve maximum operating frequency is a balance between two conflicting sizing requirements, as noted in the above-cited paper by Huang and Rogenmoser. 
     Particular sizing of transistors in a TSPC- 1  flip-flop for high frequency operation may introduce glitches like the one demonstrated above, but resizing to reduce glitches can reduce the maximum operating frequency of these flip-flops. Furthermore, sizing compromises generally result in increases in the overall size of the flip-flop, thereby reducing its maximum operating frequency. In addition, if it is possible to remove the dual (driver/load) nature of a critical transistor, the size of the transistor can be optimized for maximum operating frequency, but often at the expense of increased circuit complexity and/or power dissipation. 
     Accordingly, a need exists to improve the circuit of FIG. 1 to remove glitches of the type shown in FIG.  2 . Moreover, such needed improvements desirably avoid any substantial increase in power consumption, undue circuit complexity, or reduced maximum operating frequency while removing such glitches. A particular need exists for such improved operation for application to circuits such as the dual-modulus synchronous divider sections of a dual-modulus prescaler of the types described in incorporated patent application (ii) cited above. 
     SUMMARY OF THE INVENTION 
     Limitations of the prior are overcome and a technical advance is made in accordance with the present invention, typical embodiments of which are described below. 
     In particular, illustrative embodiments of improved TSPC- 1  flip-flop circuits are described that are based, in part, on the observation that the logic level stored on node B of the circuit of FIG. 1 during the high phase of the clock is the inverse of the future logic value to be transferred to the /Q output on the subsequent high to low transition of the clock. It therefore proves advantageous to invert this logic level and transfer it directly to node C, preserving the current value of the /Q output. This approach exploits the off state of MP 4  occurring during the high clock phase, while pre-setting the logic level at node C to the correct future /Q output value. This method also allows any charge that might be previously stored on node C, to discharge to VSS during the high clock phase. In this manner, the momentary connection of the /Q output to node C does not cause a glitch in the output-since the final value of the output has already been pre-set on node C. 
     In accordance with one illustrative embodiment of the present invention the TSPC- 1 FL flip-flop of FIG. 1 is modified by the addition of corrective circuitry applied to node C. Corrective circuitry in the illustrative embodiment comprises two NMOS transistors added to the TSPC- 1  flip-flop of FIG. 1 that are only active during the high clock phase (while the output stage exhibits tristate operation), thereby avoiding interference with operation of the output stage in its inverter mode. 
     Other illustrative embodiments also include a NAND input logic arrangement and additional output circuitry to provide complementary output signals. 
     These and other embodiments of the present invention may be realized in circuit designs that avoid transistor size increases in selected transistors as suggested in prior work. Embodiments based on present inventive teachings therefore remove the undesired glitches without reducing maximum operating frequency and without substantial increase of power consumption. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES 
     The above-summarized invention will be more fully understood upon consideration of the following detailed description and the attached drawing wherein: 
     FIG.1 shows a prior art TSPC- 1 FL flip-flop. 
     FIG. 2 shows waveforms associated with operation of the flip-flop of FIG.  1 . 
     FIG. 3 shows an illustrative embodiment of the present invention incorporating corrective circuitry to avoid shortcomings of the circuit of FIG.  1 . 
     FIG. 4 shows waveforms associated with illustrative operation of the flip-flop of FIG.  3 . 
     FIG. 5 shows an alternative illustrative embodiment of the present invention incorporating an integrated NAND input as well as corrective circuitry of the type shown in FIG.  3 . 
     FIG. 6 shows an alternative illustrative embodiment of the present invention incorporating corrective circuitry of the type shown in FIG.  3  and providing complementary outputs. 
    
    
     DETAILED DESCRIPTION 
     The following detailed description and accompanying drawing figures depict illustrative embodiments of the present invention. Those skilled in the art will discern alternative system and method embodiments within the spirit of the present invention, and within the scope of the attached claims, from consideration of the present inventive teachings. 
     To better understand the mechanism giving rise to the glitch on the /Q waveform shown in FIG. 2, it proves useful to examine how the output stage of FIG. 1 produces a logic low output during the low clock phase under the cited conditions. In such case, the output switches to operation as an inverter as the clock falls from high to low. Since node B is charged to a logic high during the high clock phase, the output stage should produce the logic low output value by connecting the /Q output node to the VSS supply through NMOS transistors MN 5  and MN 6 . Since the clock is low, PMOS transistor MP 4  will also be conducting. The node B logic high will prevent the PMOS transistor MP 3  from conducting, but will cause NMOS transistor MN 6  to be conducting. Therefore, only the MP 4  and MN 5  transistors must switch states of operation (both from the off state to the conducting state) on the clock transition from low to high. 
     It will be noted, however, that there is an inherent delay between the conduction of transistor MP 4  and transistor MN 5  upon a high-to-low transition of CLK: transistor MP 4  will always receive a change of gate potential before transistor MN 5 . This is due to the fact that the gate of MP 4  is connected directly to the clock signal, whereas the gate of MN 5  is connected to node A. Node A, in turn, always exhibits a logic high during the low clock phase due to precharging of the input stage during low clock phases. But Node A can rise to a logic high level only after MP 1  switches from the off state to the conducting state following the high-to-low transition of CLK. Accordingly, there is a non-zero delay between a change of potential at the gate of MP 1  and the change in potential of node A, and equivalently, the gate of MN 5 . Therefore, MP 1  and MP 4  will experience a change in gate potential simultaneously, with a change in the gate potential occurring at the gate of MN 5  only after a non-zero delay associated with the time to charge the load and parasitic capacitance on node A through the resistance of the conductive channel of MP 1 . It follows, then, that MP 4  will begin to conduct before MN 5  for reasonably sized transistors. 
     The result of the delay between MP 4  conducting and MN 5  conducting is that the /Q output will have a conducting path to node C before the conduction path (through MN 5 ) to VSS is established. Since the /Q output is holding a charge level set by a previous low clock phase, the update to the /Q output will initially be determined by the charge stored on node C-until the conduction path between /Q and VSS can be established. If node C is at a high charge level, the /Q output will momentarily spike high as the charge is transferred from node C to /Q during the period before MN 5  begins to conduct. For the example conditions given above, the conventional TSPC- 1  flip-flop of FIG. 1 will, in fact, have a high charge level stored on node C, thereby creating the output glitch cited above. 
     Continuing with the example above, it will be noted that node C acquires a high charge level following the immediately preceding clock transition (from low to high) prior to the high-to-low clock transition associated with the output glitch  3  on the IQ waveform in FIG.  2 . There are two mechanisms contributing to the high charge level at node C in the example. First, as the clock transitions from low to high, the change in gate potential on the MP 4  transistor causes some of the charge that is being deposited on that gate by the clock signal to “feed through” the parasitic gate-to-source capacitance and charge node C slightly. This mechanism only produces a slight increase in the potential at node C and is not itself significant enough to cause the glitch observed at  3  on the /Q waveform. 
     The predominant mechanism contributing to the increase in node C potential involves the operation of the middle stage of the flip-flop during the low to high clock transition. More specifically, with the clock in the low phase, node A is precharged to a logic high. This causes NMOS transistor MN 4  to conduct. The MN 3  transistor is off, as is the MP 2  transistor. This enforces the correct middle stage tristate condition. As the clock transitions from low to high with the D input at a logic high, both MN 1  and MN 2  will begin to conduct, thus pulling node A to a logic low. As node A lowers in potential, the MN 4  transistor will begin to switch from the conduction state to the off state. Also, as the clock signal becomes high, MN 3  will begin to conduct. This places the middle branch in the correct inverter mode of operation and the low potential at node A will cause MP 2  to conduct, placing the correct logic high on node B. 
     If node B was previously tristating with a logic high during the low phase of the clock, then a clock change from low to high should cause the potential on node B to remain at a logic high as the middle branch moves from the tristate to the inverter mode of operation. However, if MN 3  begins to conduct before node A is pulled sufficiently low (via the conduction of MN 1  and MN 2 ) to turn MN 4  off, there will be a short time when both MN 3  and MN 4  are conducting before MP 2  can start to conduct. This will cause node B to momentarily discharge to VSS, thus causing a momentary drop in potential shown at reference numeral  1  on the B waveform in FIG.  2 . This lower voltage level at node B will, in turn, cause MP 3  to conduct briefly. If MP 4  has already transitioned to the off state, node C will briefly be connected to VDD and the charge transfer will increase the potential at node C towards VDD. As node A eventually is discharged to VSS, MN 4  will switch to the off state and MP 2  will begin to conduct, once again charging node B to a logic high and turning off MP 3 . At this point, the charge stored on node C is prevented from discharging since both MP 3  and MP 4  are in the off state. Therefore, node C contains a high charge throughout the high clock phase, as shown at reference numeral  2  on the C waveform in FIG.  2 . Subsequently, when the clock transitions from high to low in the example above and the /Q output is momentarily connected to node C before being discharged to VSS, the high charge level on node C will be transferred to the /Q output, thus causing the observed glitch at reference numeral  3  in FIG.  2 . 
     Process variations can cause the threshold voltage (Vt) for some realizations of MP 3  to drop, thus allowing such MP 3 s to conduct for a longer period of time and increasing the total charge transferred to node C and its corresponding potential. Therefore, the output spike shown at  3  in FIG. 2 tends to increase in peak voltage level as device processing tends towards lower values of Vt associated with faster device operating speeds. 
     The occurrence of output glitches ( 3  in FIG. 2) for the case of an extended logic high on the input D (extended logic low on the output /Q) can be summarized as: ( 1 ) with the clock low, /Q is assumed low and as the clock transitions from low to high, the momentary simultaneous conduction of MN 3  and MN 4  cause node B to momentarily glitch low, placing a high charge on node C; and, ( 2 ) when the clock then transitions from high to low, the conduction of MP 4  before MN 5  causes the high charge stored on node C to be transferred to /Q, thereby causing the /Q output to spike high until MN 5  begins to conduct and the output returns to the correct logic low. 
     As noted above, judicious sizing of particular transistors in TSPC- 1  flip-flops can offer some help in avoiding certain glitch conditions. For example, the size of MN 1  and MN 2  can be increased to speed the discharge of node A in an attempt to more quickly switch off MN 4  and prevent the undesired charging of node C in the example given above. However this approach results in a larger capacitive load for the clock (MN 2 ) and the input D (MN 1 ). Such increase in capacitance, in turn, increases power dissipation in the clock driver and flip-flop outputs (that illustratively drive D inputs in the dual-modulus synchronous divider in incorporated patent application (ii) cited above), or result in a lowered maximum operating frequency. Improved Flip-Flop Circuit 
     A modified version of the TSPC- 1  flip-flop of FIG. 1 is shown in FIG.  3 . The modified circuit of FIG. 3 includes corrective circuitry applied to node C that avoids transistor size increases in selected transistors as suggested in prior work. The improved circuit of FIG. 3 thus removes the undesired glitch without reducing maximum operating frequency and without substantial increase of power consumption. In typical realizations, the flip-flop of FIG. 3 incurs power dissipation increases on the order of only two percent compared with that of the circuit of FIG.  1 . Present inventive solutions avoid limitations in prior approaches, such as those described in U.S. Pat. No. 6,100,730 issued Aug. 8, 2000 to Davis, et al., and in the Huang and Rogenmoser paper cited above. 
     The improved circuit of FIG. 3 is based, in part, on the observation that the logic level stored on node B during the high phase of the clock is the inverse of the future logic value to be transferred to the /Q output on the subsequent high to low transition of the clock. It therefore proves advantageous to invert this logic level and transfer it directly to node C, preserving the current value of the /Q output. This approach exploits the off state of MP 4  during the high clock phase while pre-setting the logic level at node C to the correct future /Q output value. This method also allows any charge that might be previously stored on node C, as described in the example above, to discharge to VSS during the high clock phase. In this manner, the momentary connection of the /Q output to node C does not cause a glitch in the output-since the final value of the output has already been pre-set on node C. 
     Corrective circuitry in the illustrative embodiment shown in FIG. 3 comprises two NMOS transistors added to the TSPC- 1  flip-flop of FIG.  1 . In particular, the illustrative embodiment comprises added transistors MN 7  and MN 8  that are advantageously selected to be minimum size transistors, thereby minimizing any increase in clock load and load at node B. Corrective circuitry reflected as MN 7  and MN 8  is only active during the high clock phase (while the output stage exhibits tristate operation), thereby avoiding interference with operation of the output stage in its inverter mode. 
     Illustrative operation of the corrective circuitry of FIG. 3 will now be described. When the clock is high, if node B is logic high (indicating that /Q will be low after the next high to low clock transition), both MN 7  and MN 8  conduct, thus connecting node C to VSS. This places a logic low on node C in anticipation of the update to /Q. If instead, node B is low, MN 8  does not conduct but MP 3  does, thus connecting node C to VDD in anticipation of the update for the /Q output. Therefore, if the /Q output is briefly connected to node C before all the transistors in the output branch have settled to their final state of operation for the low clock phase, the output will not glitch, but will hold its then-current value or will begin to transition to an updated state as appropriate. 
     Effectively, the corrective circuitry of FIG. 3 removes the glitch described previously without adversely affecting outputs for consecutive clock periods, regardless of the pattern of inputs on D. That is, with four possible output possibilities on consecutive falling clock edges (low-to-low, low-to-high, high-to-high, high-to-low), it will be seen that only the low-to-low output case treated in the above example and the high-to-low output transition involve a delay problem between MP 4  and MN 5  in the circuit of FIG.  1 . Since the corrective circuitry of FIG. 3 always presets node C to the appropriate future output value, proper functioning of the flip-flop of FIG. 3 is assured. 
     FIG. 4 shows waveforms of signals appearing on respective nodes of the circuit of FIG. 3 during several CLK cycles. While the glitch, at reference numeral Ion the node B waveform in FIG. 4 that accompanies a high-to-low transition of CLK persists, it will be seen that an undesired charged condition of node C at such high-to-low transition is avoided (reference numeral  2 ), thereby avoiding the undesired glitch on the /Q output. That is, only the desired output condition appears at reference numeral  3  on the /Q output shown in FIG.  4 . 
     Alternate illustrative embodiments of the present invention are shown in FIGS. 5 and 6. The circuit of FIG. 5 shows dual inputs (D 1  and D 2 ) to respective NMOS devices MN 1  and MN 2  to provide a NAND logic input. FIG. 6 shows the circuit of FIG. 4 further modified to include PMOS device MP 5  and NMOS device MN 9  connected across the VDD and VSS supply voltages for purposes of accepting the /Q output and providing a complementary output on the output path Q. Such alternative TSPC- 1  flip-flop embodiments will provide flexibility desired in demanding applications such as dual-modulus synchronous dividers described in above-cited incorporated patent application (ii). 
     Other alternative embodiments based on the above-described illustrative embodiments will employ different particular logic structures and conventions (including voltage conventions) while adhering to present inventive teachings. While particular NMOS and PMOS devices are used by way of illustration in the preceding detailed descriptions, different but equivalent devices and logical combinations of devices known in the art will be used in some applications. The term device as used in the present detailed description will be understood to mean, unless the context requires a different meaning, a MOSFET device, or other transistor or other switching element, including non-CMOS devices-such as gallium arsenide MESFETS. 
     Further, particular logical input configurations other than the illustrative inverter and NAND logical input configurations will be employed in applying present inventive teachings, as is well known in the art. Moreover, circuit arrangements including NAND and other input logic functions will be implemented in TSPC- 1  flip-flop circuits also including circuitry for providing complementary outputs-all within the scope of present inventive teachings. 
     Still further, it will be recognized by those skilled in the art that the ordering of devices MN 7  and MN 8  is merely illustrative, and may be reversed in particular applications while continuing to provide desired corrective functionality in substantially eliminating glitches of the types described above in prior TSPC- 1  flip-flop circuits. Thus, MN 7  in FIGS. 3,  5  and  7  may be adapted to connect node C to the node intermediate MN 7  and MN 8  in response to signals appearing at node B, and MN 8  may be adapted to connect this intermediate node to the supply voltage VSS in response to applied clock signals.