Abstract:
A CMOS OR circuit is fast and has a reduced sensitivity to the variations in the process, temperature and voltage supply. When the input signal to any one of a plurality of select transistor is in a logic high, a fixed supply of current is provided to the common drain terminal of the select transistors thereby to limit the amount of voltage swing of the common drain terminal and the common source terminal of the select transistors. A maximum power sensor senses the voltage differential developed between the common drain and the common source terminals of the select transistors and in response thereto generates a control signal which varies the amount of current that a variable current supply delivers to the common drain terminal thereby to prevent the output signal of the OR circuit from switching to the wrong state.

Description:
FIELD OF THE INVENTION 
     The present invention relates to an integrated circuit, more particularly, to a fast OR logic circuit implemented in integrated circuit form. 
     BACKGROUND OF THE INVENTION 
     A conventional CMOS OR circuit (e.g. the 3-input OR circuit  10  of FIG. 1) is slow, inhibiting its use in the critical speed path of an Integrated Circuit (IC). 
     FIG. 2 shows a known 3-input OR circuit  20 , which is undesirably slow when designed to be operable under all temperatures, process corners and supply voltages. Furthermore, the speed of OR circuit  20  varies significantly with temperature, process and supply voltage variations. 
     FIG. 3 shows a computer simulation of a timing delay between input terminal IN 1  and output terminal OUT of OR circuit  20 , under a nominal operation condition, (i.e. typical process corner, 25° C. and 5 volts supply voltage). Using the midpoint between the positive and the negative supply voltages (i.e. 2.5 volts) to measure the delay, it is seen from FIG. 3 that a delay of 0.36 nsec exists between the time the input signal IN 1  crosses the 2.5 volts and the time when output signal OUT crosses the same voltage level. The 0.36 nsec delay is undesirably high for some applications. 
     Therefore a need exists for a CMOS OR circuit which is relatively insensitive to changes in temperature, process and supply voltage variations and operates at a high speed under a nominal operating condition. 
     SUMMARY OF THE INVENTION 
     The high-speed CMOS OR circuit, in accordance with one embodiment of the present invention, includes a select transistor for each input signal, a circuit for supplying a fixed current to the common drain terminals of the select transistors and a maximum power sensor circuit for controlling the amount of current that is supplied by a variable current supply to the common drain terminals of the select transistors. 
     The fixed current supply turns on only when the OR circuit is in a selected state thereby to limit the voltage swing across the common drain and common source terminals of the select transistors and thus to improve the speed of the OR circuit. A delay circuit formed by a string of inverters receives the voltage signal generated at the output terminal of the OR circuit and supplies an inverted voltage signal to a gate terminal of a PMOS transistor to turn on or turn off the fixed current supply. 
     To ensure that the OR circuit is fast under all process corners, temperatures and voltage supplies, the maximum power sensor senses the voltage signals across the common drain and common source terminals of the select transistors thereby to adjust the amount of current that the variable current supply supplies to the common drain node. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a transistor schematic diagram of a 3-input CMOS OR circuit as known in the prior art. 
     FIG. 2 shows a transistor schematic diagram of another 3-input CMOS OR circuit as known in the prior art. 
     FIG. 3 shows the timing delay between an input signal and the output signal of the OR circuit of FIG.  2 . 
     FIG. 4 shows a transistor schematic diagram of a 3-input high-speed CMOS OR circuit, in accordance with one embodiment of the present invention. 
     FIG. 5 shows the timing delay between an input signal and the output signal of the OR circuit of FIG.  4 . 
     FIG. 6 shows the voltage signals at various nodes of the OR circuit of FIG. 2 as the OR circuit transitions from a selected state to a non-selected state. 
     FIG. 7 shows a schematic diagram of a high-speed OR circuit, in accordance with another embodiment of the present invention. 
     FIG. 8 shows a top view of the physical layout of two of the transistors of the OR circuit of FIG.  4 . 
    
    
     DETAILED DESCRIPTION 
     A 3-input CMOS OR circuit  100 , in accordance with one embodiment of the present invention, is shown in FIG.  4 . NMOS transistors  2 ,  6  and  8  which receive input signals IN 1 , IN 2  and IN 3  at their respective gate terminals, have their drain terminals coupled to node N 1 , which in turn, is coupled to the gate terminal of NMOS transistor  12  and to the input terminal of CMOS inverter  60 . The output terminal of inverter  60  generates signal OUT of OR circuit  100 . 
     During normal operation, when at least one of the voltage signals IN 1 -IN 3  goes to a high logic level, (high) node N 1  is pulled to a low logic level (low) which, in turn, causes signal OUT to go to a high logic level. On the other hand, when none of the voltage signals IN 1 -IN 3  are at a high logic level, node Nl is at a high logic level, causing voltage signal OUT to go to a low logic level. 
     As seen from FIG. 4, the drain terminals of select transistors  2 ,  6  and  8  are coupled to node N 1 , which is coupled to supply voltage Vcc. Similarly, the source terminals of select transistors  2 ,  6  and  8  are coupled to node N 2 , which is coupled to supply voltage Vss. PMOS transistor  3 , and NMOS transistors  10  and  16 , reduce the amount of voltage swing on relatively high capacitive nodes N 1  and N 2 . PMOS transistor  1  ensures that node N 1  is not floating when none of input transistors  2 ,  6  and  8  are selected and, accordingly, transistor  1  has a relatively narrow channel width and a relatively long channel length. 
     When none of transistors  2 ,  6  and  8  are selected, (i.e. all three signals IN 1 -IN 3  are low), node N 1  is pulled to supply voltage Vcc, thereby forcing transistor  10  to be in a strong-on state, in turn, pulling node N 2  to supply voltage Vss. On the other hand, when at least one of transistors  2 ,  6  and  8  is selected, (i.e. at least one of signals IN 1 -IN 3  is high), node N 1  is pulled low, reducing the gate voltage of transistor  10 , thereby forcing transistor  10  to a weak-on state, in turn reducing the conductance by which nodes N 1  and N 2  are pulled low. Because transistors  3 ,  16  and  10  limit the amount of voltage variations on relatively high capacitive nodes N 1  and N 2 , transistors  3 ,  16  and  10  minimize the time delay between the input signals IN 1 -IN 3  and the output signal OUT of OR  100 . 
     As stated earlier, nodes N 1  and N 2  have relatively large capacitances. Thus, to improve the speed of OR circuit  100 , the voltage swing on these two nodes is kept small, in part, by using PMOS transistor  3  whose gate terminal is coupled to node N 3 . The output terminal of delay circuit  50 , which includes a string of three CMOS inverters  32 ,  34  and  36 , is also coupled to node N 3 . When all three input signals IN 1 -IN 3  are low, node N 1  and, consequently, node N 3  both are at a high logic level, therefore transistor  3  is off, inhibiting the flow of current I 1  from supply voltage Vcc to node N 1 . 
     When at least one of signals IN 1 -IN 3  is high, the voltage of node N 1  is lowered, therefore, node N 3  is pulled low, turning on PMOS transistor  3  which supplies a fixed amount of current I 1  to node N 1 , thus preventing the voltage signal at node N 1  to reach to that at node N 2 . Thus, delay circuit  50  and PMOS transistor  3 , by maintaining a DC voltage differential across nodes N 1  and N 2  when OR circuit  100  is in a selected state, minimize the time period for charging node N 1  and discharging node N 2  when OR circuit  100  is switched to a non-selected state and thus increase the speed of OR circuit  100 . The channel dimensions of PMOS transistor  3  is selected such that under the highest power conditions, namely under the lowest operating temperatures, the highest specified voltage supplies and the fastest processing conditions, the voltage differential between nodes N 1  and N 2  is still small enough to prevent NMOS transistor  14  from turning on and causing signal OUT to go to a low level. 
     To achieve the highest speed of operation across different process, temperature and supply voltage variations, while inhibiting the voltage differential from increasing to such levels that would cause transistor  14  to turn on when OR circuit  100  is in a selected state, Maximum Power Sensor (MPS) circuit  40  is provided in OR circuit  100 , which is described next. 
     MPS  40  includes NMOS transistors  12 ,  18  and PMOS transistors  5 ,  7 . When control signal LOWICC, which is applied to the gate terminals of PMOS transistor  5  and NMOS transistor  18 , is at a high logic level, the drain terminal of transistor  18  is pulled to a low logic state, thereby disabling MPS  40  and simultaneously turning off NMOS transistors  16 . When signal LOWICC is low, NMOS transistor  18  is switched off and PMOS transistor  5  is switched on, thereby charging the source region of PMOS transistor  7  to supply voltage Vcc. When control signal LOWICC is low, MPS  40  is enabled. 
     When all three input signals IN 1 , IN 2  and IN 3  are low and MPS  40  is enabled, nodes N 1  and N 3  are both high. Consequently, NMOS transistor  12  is turned on and PMOS transistor  7  is turned off. Therefore, the drain terminal of PMOS transistor  7  is uncoupled from its source terminal (which is at supply voltage Vcc) and is pulled to supply voltage Vss and thus no current flows through MPS  40 . 
     When at least one of the input signals IN 1 -IN 3  goes high and MPS  40  is enabled, the voltage level at node N 1  begins to fall. Thereafter, transistor  3  begins to provide current I 1  to node N 1  to maintain a voltage differential between nodes N 1  and N 2 . If the voltage differential between nodes N 1  and N 2  is smaller than the threshold voltage of transistor  12 , transistor  12  remains off. Accordingly, node N 4  is pulled to supply voltage Vcc causing transistor  16  to turn on which supplies a maximum possible amount of current I 2  to node N 1 . If, on the other hand, the voltage differential between nodes N 1  and N 2  is greater than the threshold voltage of transistor  12 , transistor  12  turns on to decrease the voltage at node N 1  thereby ensuring that transistor  14  turns off. Because, both PMOS transistors  5  and  7  as well as NMOS transistor  12  are on, the magnitude of the voltage drop at node N 1  is dependent on the relative sizes of PMOS transistors  5 ,  7  and NMOS transistor  12 . In a steady state, the voltage at node N 4  decreases to a value between the supply voltage Vcc and the voltage at node N 2 . The decrease in the voltage at node N 4  causes the gate voltage of transistor  16  to go down, reducing the current I 2 , and thereby reducing the voltage at node N 1 . The greater the voltage differential between nodes N 1  and N 2  becomes, the stronger the on-state of transistor  12 , the greater the reduction in the voltage at node N 4 , and hence the smaller is the magnitude of current I 2  delivered to node N 1 . Conversely, the smaller the voltage differential between nodes N 1  and N 2  becomes, the weaker the on-state of transistor  12 , the smaller the reduction in voltage at node N 4 , and hence the greater is the magnitude of current I 2  delivered to node N 1 . 
     To ensure that the threshold voltages of NMOS transistors  12  and  14  track each other when variation in fabrication processing occurs, transistors  12  and  14  are placed adjacent each other and have similar layout and physical orientation. As seen from FIG. 8, because transistor  14  typically has a much wider channel than transistor  12 , transistor  14  is physically laid out using multiple gate fingers, each having the same size as that of the gate of transistor  12 . 
     MPS  40  by sensing the voltage of node N 1  and accordingly adjusting the gate voltage of transistor  16 , in accordance with the present invention, increases the speed and simultaneously minimizes the sensitivity of OR  100  to process, temperature and power supply variations. 
     Delay circuit  50 , ensures a delay before signal OUT is applied to the gate terminal of transistor  3 , thereby stabilizing OR circuit  100 . 
     Inverter  60 , inverts the voltage signal of node N 1  and delivers it to the output terminal OUT of OR circuit  100 . 
     In one embodiment of the present invention capacitor  19  is disposed between node N 4  and supply voltage Vcc to stabilize OR circuit  100  and to inhibit oscillation. If the inherent capacitance of node N 4  is sufficient to stabilize OR circuit  100 , capacitor  19  is unnecessary. 
     In one embodiment of the present invention, the transistor sizes of OR circuit  100  are as shown in the following table, where channel width is designated as W and channel length is designated as L. 
     
       
         
               
               
               
             
               
               
               
             
           
               
                   
               
               
                 Transistor No. 
                 W (μm) 
                 L (μm) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 1 
                 2.0 
                 2.0 
               
               
                 2 
                 11.2 
                 0.7 
               
               
                 3 
                 5.4 
                 0.75 
               
               
                 4 
                 22.4 
                 0.7 
               
               
                 5 
                 1.4 
                 1.0 
               
               
                 6 
                 9.0 
                 0.7 
               
               
                 7 
                 1.4 
                 1.0 
               
               
                 8 
                 9.0 
                 0.7 
               
               
                 9 
                 40.2 
                 0.75 
               
               
                 10 
                 15.8 
                 0.8 
               
               
                 12 
                 3.0 
                 0.7 
               
               
                 14 
                 36.0 
                 0.7 
               
               
                 16 
                 14.0 
                 0.7 
               
               
                 18 
                 1.4 
                 1.0 
               
               
                   
               
             
          
         
       
     
     FIG. 5 shows the results of a computer simulation of the time delay between input signal IN 1  and output signal OUT of OR circuit  100  using the transistor sizes in the above table, and nominal operating conditions (i.e., typical process parameters, 25° C. temperature and 5 volts supply voltage Vcc). Using the midpoint between the two supply voltages, (i.e. 2.5 volts) to measure the delay, FIG. 5 shows a delay of 0.22 nsec between the time input signal IN 1  crosses 2.5 volts and the time output signal OUT crosses 2.5 volts, resulting in almost 39% improvement in speed over prior art OR circuit  20  of FIG.  2 . 
     FIG. 6 shows the result of a computer simulation showing the voltages of nodes N 1 , N 2 , N 3 , N 4  and signal OUT, as OR circuit  100  transitions from a selected state (i.e. input signal IN 1  is selected) to a non-selected state. While in the selected state, nodes N 1  and N 2  are respectively, at 2.75 and 1.5 volts. During the selected state, both PMOS transistors  1  and  3  supply current to node N 1 , thereby preventing this node from being pulled to the Vss voltage level. Simultaneously, node N 2  is pulled above the Vss voltage level. The voltage differential between nodes N 1  and N 2 , (i.e. approximately 1.25 volts), forces transistor  12  into a weak turn-on state, thereby preventing node N 4  from reaching 5 volts. Because transistors  5 ,  7  and  12  are on, node N 4  settles at 4.5 volts, thereby turning on transistor  16  whose source voltage is at 2.75 volts. Therefore, while in the selected state, all three transistors  1 ,  3  and  16  supply current to node N 2 . 
     Because the magnitude of the voltage swings on nodes N 1  and N 2  are kept at 2.25 volts and 1.5 volts, respectively, the time period required for charging and discharging these two nodes is relatively small, causing OR circuit  100  to be fast. At the same time, the difference of 1.25 volts appearing across nodes N 1  and N 2 , (i.e. the gate-to-source voltage of transistor  14 ), induces only a weak-on state on transistor  14 , thereby maintaining signal OUT at a logic high. 
     The channel length of NMOS transistor  10  is 0.1 μm longer than the minimum length (i.e. 0.7 μm) to substantially decrease its substrate current that would otherwise be undesirably large due to the biasing conditions and the relatively large current that flows through NMOS transistor  10 . 
     When OR circuit  100  is in a non-selected state, nodes N 1  and N 3  are at 5 volts, while node N 2  and N 4  are at 0 volt. Therefore, both transistors  16  and  3  turn off, disconnecting the supply of currents I 1  and I 2  to node N 1 . 
     In one embodiment of the present invention, transistor  4  is disposed between transistor  2  and node N 2  to enable or disable select transistor  2 , as is shown in FIG.  7 . Signal ARCHBIT turns on or off NMOS transistor  4 , thereby enabling or disabling logic input IN 1 . 
     The exemplary embodiments of the invention disclosed above are illustrative and not limiting. Other embodiments of this invention are possible within the scope of the appended claims.