Abstract:
A composite amplifier is constructed by connecting the respective input terminals of a high-frequency amplifier and a precision amplifier together and by connecting the output of the precision amplifier to the offset trim port of the high-frequency amplifier. The amplifiers are structured such than a pole in the frequency response curve of the high-frequency amplifier cancels a zero in the frequency response curve of the precision amplifier, thereby producing a single pole roll off response curve for the composite amplifier. In the preferred embodiment the high-frequency and precision amplifiers are formed on a single chip and the pole-zero match is therefore maintained at all conditions of temperature and other variables.

Description:
FIELD OF THE INVENTION 
     This invention relates to operational amplifiers and in particular to an operational amplifier which combines good precision and high-frequency characteristics with a rail-to-rail output. 
     BACKGROUND OF THE INVENTION 
     Amplifiers generally fall into different categories, depending on their performance characteristics. One such category includes high-frequency amplifiers, which are characterized by a wide bandwidth and a low open-loop gain. Another such category includes precision amplifiers, which are characterized by a narrower bandwidth but a higher open-loop gain, the latter feature making them more precise, i.e., the voltage drop across the inputs is very small when the amplifier is connected in a closed-loop configuration. 
     It is difficult to achieve the dual objectives of high-frequency and precise operation in a single amplifier because the very features which broaden the bandwidth of the amplifier also tend to reduce its open-loop gain. Similarly, the design criteria which increase open-loop gain tend to reduce the high-frequency response of the amplifier. 
     As shown in U.S. Pat. No. 5,045,805, it is known to increase open-loop gain by connecting a pair of high-frequency amplifiers in a cascade arrangement. Since the total gain is then the product of the individual gains, the precision of the amplifier pair is improved. However, such arrangements require a compensation network to maintain stability and adjustable circuitry for proper operation. 
     SUMMARY OF THE INVENTION 
     In a composite amplifier according to this invention, a high-frequency amplifier and a precision amplifier are interconnected. The inputs of the precision amplifier are connected across the inputs of the high-frequency amplifier. The output of the precision amplifier is connected to an offset trim port of the high-frequency amplifier. At high frequencies, the precision amplifier has relatively little effect, and the output of the composite amplifier is therefore dominated by the high-frequency amplifier. Conversely, at low frequencies, the precision amplifier contributes gain over and above the high-frequency amplifier, and the input offset is dominated by the offset of the precision amplifier. 
     The frequency response curve of the composite amplifier has a single pole and no zeros. This desirable curve is achieved by fabricating the high-frequency and precision amplifiers on a single chip and by arranging the parameters of the circuitry such that the pole of the high-frequency amplifier matches (i.e., cancels) the zero of the precision amplifier under all conditions of time, temperature, process, etc. Thus the pole of the composite amplifier is determined by the pole of the precision amplifier. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The principles of this invention will be best understood by reference to the following figures of the drawing, in which like elements are identified by similar reference numerals. 
     FIG. 1 illustrates a schematic block diagram of a composite amplifier in accordance with this invention. 
     FIG. 2 illustrates an equivalent circuit for the composite amplifier. 
     FIG. 3 illustrates a graph showing the frequency response curves of the precision amplifier, the high-frequency amplifier and the composite amplifier, respectively. 
     FIG. 4 illustrates a block diagram of a conventional operational amplifier. 
     FIG. 5 illustrates a block diagram of a conventional operational amplifier having an offset trim port. 
     FIG. 6 illustrates a more detailed block diagram of the high-frequency amplifier which forms a part of the composite amplifier of this invention. 
     FIG. 7 illustrates a frequency response curve of the high-frequency amplifier shown in FIG. 6. 
     FIG. 8 illustrates a more detailed block diagram of the composite amplifier, showing both the high-frequency amplifier and the precision amplifier. 
     FIG. 9 illustrates curves showing the frequency response of the high-frequency and precision amplifiers, respectively. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a composite amplifier A c  in accordance with the invention which includes a precision amplifier A p  and a high-frequency amplifier A hf . The inputs of amplifiers A p  and A hf  are connected in the manner shown to input terminals T 1  and T 2 , which receive a differential input signal V in . The output of precision amplifier A p  is connected through a resistor R to an offset trim port T 3  of high-frequency amplifier A hf . A single-ended output signal V out  is generated at a terminal T 4 . 
     FIG. 2 illustrates an equivalent circuit which helps to show the operation of composite amplifier A c . Feeding the output of amplifier A p  to the offset trim port T 3  is equivalent to inserting a voltage source V s  in series with the input of the high-frequency amplifier A hf . At high frequencies, amplifier A p  has very little effect, and the high-frequency amplifier A hf  dominates. At low frequencies, amplifier A p  contributes gain over and above the gain provided by amplifier A hf . Note that the voltage source V s  is connected in the series path between terminals T 1  and T 2 . Thus, for example, if the offset of amplifier A hf  is 1 mV and amplifier A p  contributes a gain of 99, then the offset at the input terminals of composite amplifier A c  will be only 10 μV. 
     Illustrative frequency response curves for amplifiers A p , A hf  and A c  are shown in FIG. 3. As indicated, the frequency response of precision amplifier A p , represented by curve 1, has a pole at a low frequency and a zero at a frequency f pz  which coincides with unity gain of amplifier A p  into the voltage source V s . The frequency response of high-frequency amplifier A hf , represented by curve 2, has a single pole which also occurs at frequency f pz . The frequency response of the composite amplifier A c  is represented by curve 3, which is the product of curves 1 and 2. Curve 3 has a single pole which coincides with the pole of amplifier A p . Because the zero of curve 1 matches the pole of curve 2, cancellation occurs in the corresponding region of curve 3. The frequency response of the composite amplifier (curve 3) therefore exhibits a high gain at low frequencies and, after its single pole is passed, a smooth decrease in gain until unity gain is reached at a frequency substantially higher than f pz . 
     Obtaining this smooth decrease depends upon insuring that the pole of curve 2 matches the zero of curve 1 under all conditions of temperature, time, etc. How this is accomplished will now be described. 
     FIG. 4 illustrates a more detailed block diagram of a conventional operational amplifier. This represents the structure of precision amplifier A p  and high-frequency amplifier A hf  (less the offset trim port). The amplifier shown in FIG. 4 includes an input stage, a second stage and an output stage. This structure is described in greater detail in numerous sources, including, for example, Thomas M. Frederiksen, &#34;Intuitive IC OP Amps&#34;, 1984, pages 12-16, which is incorporated herein by reference. The input stage includes a differential amplifier and a current mirror, which together operate to transform the differential input voltage V in  into a single-ended current I out . The combination of the differential amplifier and current mirror are sometimes referred to as a &#34;transconductance amplifier&#34; which has a transfer function I out  /V in  and which is designated by the reference gm1 in FIG. 4. 
     The second stage includes a compensation capacitor C1. The bandwidth of the amplifier depends on where the current I out  has a unity gain into capacitor C1 referenced to V in . The low-frequency pole is normally set by a parasitic resistance, shown as R1, that can be viewed as connected in parallel with capacitor C1. Since the input stage is CMOS, the output of the transconductance amplifier gm1 will be somewhat dependent on process and temperature. 
     The output stage includes a buffer B1 which has a high input impedance and is connected in a unity gain configuration. 
     A more detailed description of an input stage, a second stage and an output stage is found in application Ser. No. 08/205,530, filed Mar. 3, 1994 (now U.S. Pat. No. 5,414,388), application Ser. No. 08/205,573, filed Mar. 3, 1994, and application Ser. No. 08/148,121, filed Nov. 5, 1993, respectively, each of which is commonly owned by the assignee hereof and is incorporated herein by reference in its entirety. 
     FIG. 5 illustrates a block diagram of the amplifier A hf  including the offset trim port T 3 . A second transconductance amplifier gm2 introduces a current I trim  into capacitor C1 (actually, as shown by the arrow, I trim  flows out of capacitor C1). The voltage at the trim port T 3  is adjusted such that in the presence of negative feedback, the voltage V in  is equal to zero. 
     FIG. 6 illustrates the high-frequency amplifier A hf  configured in accordance with the invention. In amplifier A hf , the capacitor/buffer configuration of FIG. 5 is replaced with a transconductance (gm3)/virtual ground configuration in order to provide a rail-to-rail output stage. The output of transconductance amplifier gm1 now goes to a virtual ground, which means that the output of gm1 effectively sees a short to ground. Transconductance stage gm3 is also a CMOS input stage. This removes any bias current loading at the output of transconductance amplifier gm1. Thus, with this architecture, the open-loop gain of the amplifier is very high even when the output is heavily loaded. The compensation capacitor C1 is shown in parallel with transconductance amplifier gm3. 
     With the arrangement shown in FIG. 6 the resistor R1 in FIGS. 4 and 5 has effectively been replaced by the combination of a network of resistors R2 and R3 and transconductance amplifier gm2. Since the transfer function of a transconductance amplifier is in the form I/V, a transconductance amplifier can be viewed as the equivalent of a resistor have a value equal to the inverse of the transfer function. Therefore, the total resistance in parallel with capacitor C1 is equal to (1/gm2)*(R2+R3)/R2. 
     The transfer function of amplifier A hf  is shown in FIG. 7. As is well known, the pole occurs at a frequency equal to 1/2πRC. Substituting the value C1 for the compensation capacitor C1 and the value (1/gm2)*(R2+R3)/R2 for R yields the following expression of the pole frequency f pole  in terms of C1, gm2, R2 and R3: 
     
         F.sub.pole =gm2*R2/((R2+R3)*2*π*C1) 
    
     Amplifier A hf  reaches unity gain at a frequency equal to gm1/2πC1. 
     FIG. 8 shows amplifiers A hf  and A p  connected together so as to form a composite amplifier in accordance with the invention. Precision amplifier A p  includes a transconductance amplifier gm4 and a compensation capacitor C2. Transconductance amplifier gm4 should be formed in CMOS, and transconductance amplifiers gm1 and gm4 should be formed on the same chip and fabricated such that they essentially track each other regardless of process, temperature, output load, etc. 
     Referring now to FIG. 9, the zero in the transfer function for amplifier A p  occurs where the gain of gm4 through gm2 equals the gain of gm1. At the zero frequency f zero , the following relationship holds: 
     
         gm1=(gm4/(2*π*f.sub.zero *C2))*(R3&#39;/(R4+R3&#39;))*gm2 
    
     where R3&#39;=R2*R3/(R2+R3) 
     Solving for f zero  yields the following: 
     
         f.sub.zero =(gm4/gm1)*(1/2*π*C2)*(R3&#39;/(R4+R3&#39;))*gm2 
    
     As noted above, it is desired to have the pole amplifier A hf  cancel the zero of amplifier A p . In this situation f pole  =f zero  =f pz  (see FIG. 3). 
     Equating the above expressions for f pole  and f zero  yields: 
     
         ((R2+R3&#39;)/R2)*(R4/(R4+R3&#39;))=(gm4/gm1)*(C2/C1) 
    
     Thus gm2 drops out of the equation, and the pole and zero are found to track each other if the required ratios of resistors (R2, R3, R4), capacitors (C1, C2) and gains (gm1, gm4) are maintained. In particular, the transconductance amplifiers gm2 and gm3 need not track each other or gm1 or gm4. 
     The composite amplifier disclosed herein has extremely high open loop gain, extremely high bandwidth and extremely low offset. Because the CMOS transconductance amplifier gm3 is used in place of a conventional buffer in the output stage of the high-frequency amplifier A hf , the composite amplifier operates rail-to-rail. 
     While a particular embodiment of this invention has been described, numerous alternative embodiments within the spirit of this invention are possible and will be apparent to person skilled in the art.