Abstract:
Systems and methods for manufacturing multiple integrated tip probes for scanning probe microscopy. According to an embodiment is a microscope probe configured to analyze a sample, the microscope probe including: a movable probe tip including a terminal probe end; a first actuator configured to displace the movable probe tip along a first axis; and a detection component configured to detect motion of the movable probe tip in response to an applied signal; where the moveable probe tip comprises a metal layer affixed to a supporting layer, at least a portion of the metal layer at the terminal probe end extending past the supporting layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to U.S. Provisional Patent Application Ser. No. 62/121,208, filed on Feb. 26, 2015 and entitled “Systems and Methods for Manufacturing Nano-Electric-Mechanical-System Probes,” the entire disclosure of which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present disclosure is directed generally to systems and methods for manufacturing multiple integrated tip probes for scanning probe microscopy. 
       BACKGROUND 
       [0003]    In order to achieve low-powered high-performance electronics, the size of transistors forming the building block of very large scale integrated (VLSI) circuits are drastically decreasing. However, tool resolution and sensitivity continue to be major challenges in semiconductor device fault isolation and analysis. As transistors continue to scale down to 10 nm nodes and beyond, well-known optical microscopy techniques no longer work due to wavelength limitations. For instance, conventional failure analysis methods involve the use of Focused Ion Beam (FIB) deposited pads or Scanning Electron Microscope (SEM). However, minute charge currents from the FIB and SEM adversely affect measured results. The induced charge from the FIB and SEM can even break the ultra-thin transistor tunneling gate oxide layer. In addition to this, Passive Voltage Contrast (PVC) techniques lack the sensitivity to identify faulty vias and contacts. 
         [0004]    Single-tip Scanning Probe Microscopy, such as Atomic Force Probing (AFP) and Atomic Force Microscopy (AFM), is a powerful tool for non-destructive determination of root causes of IC chip failure, including extension to the sub 10 nm node regimes. However, AFM effectiveness is severely limited by its single tip design. As a result, a range of fundamental phenomena that exist in thin film materials and devices are inaccessible. As just one example, the effects of dislocations and grain boundaries in thin films cannot be characterized, as the ability to perform trans-conductance (conduction between two tips) measurements at the nanoscale is a critical gap. Trans-conductance would enable a richer understanding of how electrons transport and interact with their surroundings by offering insight into the local density of states, tip-sample coupling, transport mechanisms, scattering phase shifts and inelastic free mean paths of electrons. 
         [0005]    Multiple-tips SPMs have been proposed as a way of overcoming the inherent limitations of the single-tip SPM. However, there have been significant challenges to engineering a suitable multiple-tips SPM. Previous approaches to a multiple-tip SPM have relied on independent macroscopically-fabricated probes. These platforms are complex, difficult to actuate, and have limited scale-down. They are also prohibitively expensive to manufacture. 
         [0006]    Accordingly, there is a continued need in the art for multiple-tips SPMs that are both cost-effective and easily manufactured and functionalized to the specific investigation for which they will be utilized. Also needed are efficient and cost-effective methods of manufacturing multiple integrated tip probes. 
       SUMMARY OF THE INVENTION 
       [0007]    The present disclosure is directed to systems and methods for manufacturing multiple integrated tip (MiT) probes for scanning probe microscopy. The MiT probe is a Nano-Electro-Mechanical System (NEMS) that integrates mechanical and electrical functionality in a monolithically-fabricated nano-structure which is tailored and functionalized to the specific investigation. The MiT scanning probe microscope provides two or more monolithically integrated cantilever tips that can be placed within nanometers of each other, with monolithically integrated transistors to amplify signals. As a result, the MiT SPM is able to perform atomic force microscopy without the need for laser tip alignment. Further, the MiT SPM is capable of nanoprobing surfaces where at least two of the integrated tips are in direct contact or in close proximity with the sample. 
         [0008]    According to an aspect is a microscope probe configured to analyze a sample. The microscope probe includes a movable probe tip comprising a terminal probe end, wherein the moveable probe tip comprises a metal layer affixed to a supporting layer, at least a portion of the metal layer at the terminal probe end extending past the supporting layer. 
         [0009]    According to an embodiment, the microscope probe includes a first actuator configured to displace the movable probe tip along a first axis, and a detection component configured to detect motion of the movable probe tip in response to an applied signal. 
         [0010]    According to an embodiment, the metal is platinum, gold, tungsten, or nickel. 
         [0011]    According to an embodiment, the supporting layer is silicon, silicon dioxide, or silicon nitride. 
         [0012]    According to an embodiment, the microscope probe includes a plurality of probe tips each comprising a terminal probe end, each of the plurality of probe tips further comprising a metal layer affixed to a supporting layer, at least a portion of the metal layer at the terminal probe ends extending past the supporting layer. 
         [0013]    According to an embodiment, the probe further includes an insulated interdigitated structure positioned between each of the plurality of probe tips. 
         [0014]    According to an aspect is a microscope probe configured to analyze a sample. The microscope probe includes: a plurality of probe tips and an insulated interdigitated structure positioned between each of the plurality of probe tips. 
         [0015]    According to an embodiment, the probe includes a first actuator configured to displace at least one of the plurality of probe tips along a first axis; and a detection component configured to detect motion of the at least one of the plurality of probe tips in response to an applied signal. 
         [0016]    According to an aspect is a microscope probe configured to analyze a sample. The microscope probe includes: (i) a first probe tip; and (ii) a second probe tip positioned a first distance from the first probe tip, wherein the second probe tip is positioned vertically underneath the first probe tip. 
         [0017]    According to an embodiment, the probe includes a first actuator configured to displace at least one of the first and second probe tips along a first axis; and a detection component configured to detect motion of the at least one of the first and second probe tips in response to an applied signal. 
         [0018]    According to an embodiment, the first and second probe tips comprise a metal. According to an embodiment, the first and second probe tips comprise the same metal. According to an embodiment, the first and second probe tips each comprise a different metal. 
         [0019]    According to another aspect is a microscope probe configured to analyze a sample. The microscope probe includes: (i) a movable probe tip supported by a substrate; (ii) a first actuator configured to displace the movable probe tip along a first axis; and (iii) a detection component configured to detect motion of the movable probe tip in response to an applied signal; (iv) a resonator configured to vibrate when the probe is in a vibrational mode; and (v) a capacitor affixed to the substrate. 
         [0020]    According to another aspect is a method for analyzing a sample using a microscope probe, the method comprising the steps of: providing a microscope probe comprising: (i) a movable probe tip supported by a substrate; (ii) a resonator configured to vibrate when the probe is in a vibrational mode; and (iii) a capacitor affixed to the substrate; receiving a current from the capacitor; receiving a current from the resonator; electrically combining the current from the capacitor and the current from the resonator; and using the electrically combined current to improve a signal-to-noise ratio of the sample analysis. 
         [0021]    According to an aspect is a method for implementing a transistor. The method includes the steps of: providing a sample; providing a microscope probe comprising a plurality of probe tips; contacting a first, outer probe tip of the plurality of probe tips to the sample, wherein the first outer probe tip is configured to act as a source terminal for the transistor; contacting a second, outer probe tip of the plurality of probe tips to the sample, wherein the second outer probe tip is configured to act as a drain terminal for the transistor; using a third, inner probe tip of the plurality of probe tips as a gate terminal for the transistor; and characterizing the sample with the plurality of probe tips. 
         [0022]    According to an embodiment, the inner probe tip comprises a dielectric coating, and further wherein the dielectric coating is in contact with the surface. 
         [0023]    According to an aspect is a method for implementing a variable resistor. The method includes the steps of: providing a sample; providing a microscope probe comprising a plurality of probe tips; contacting a first, outer probe tip of the plurality of probe tips to the sample; contacting a second, outer probe tip of the plurality of probe tips to the sample; contacting a third, inner probe tip of the plurality of probe tips to the sample; applying a voltage to either of the first and second outer probe tips, wherein the inner probe tip is deflected toward either the first or second outer probe tips; and characterizing the sample based on the deflection of the inner probe tip. 
         [0024]    These and other aspects of the invention will be apparent from the embodiment(s) described hereinafter. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]    The present invention will be more fully understood and appreciated by reading the following Detailed Description in conjunction with the accompanying drawings, in which: 
           [0026]      FIG. 1  is a schematic representation of a Butterworth-Van Dyke equivalent circuit for a NEMS resonator, in accordance with an embodiment. 
           [0027]      FIG. 2  is schematic representation of a circuit depicting parallel connection of a compensation capacitor (Static) to a resonator, resulting in parasitic feedthrough self-cancelation, in accordance with an embodiment. 
           [0028]      FIG. 3  is a schematic representation of a MiT probe with a compensation device structured identically to the resonator, in accordance with an embodiment. 
           [0029]      FIG. 4  is a schematic representation of a MiT probe with on-chip feedthrough cancellation using monolithically integrated static and resonating structures, in accordance with an embodiment. 
           [0030]      FIG. 5  is a SEM scanning electron microscope (SEM) image of a MiT probe with gold probe tips, in accordance with an embodiment. 
           [0031]      FIG. 6  is a SEM image of a MiT probe with MoSi 2  probe tips, in accordance with an embodiment. 
           [0032]      FIG. 7  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0033]      FIG. 8  is a SEM image of a MiT probe with a platinum metal layer that sits on a silicon supporting structure, in accordance with an embodiment. 
           [0034]      FIG. 9  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0035]      FIG. 10  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0036]      FIG. 11  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0037]      FIG. 12  is a top view schematic of a MiT probe with three degrees of freedom, in accordance with an embodiment. 
           [0038]      FIG. 13  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0039]      FIG. 14  is a top view schematic representation of a MiT probe with three degrees of freedom, in accordance with an embodiment. 
           [0040]      FIG. 15  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0041]      FIG. 16  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0042]      FIG. 17  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0043]      FIG. 18  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0044]      FIG. 19  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0045]      FIG. 20  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0046]      FIG. 21  is a schematic representation of a MiT probe, in accordance with an embodiment. 
           [0047]      FIG. 22  is a schematic representation of a MiT probe where the middle probe tip represents a gate and the side probe tips are source and drain terminals of a transistor, in accordance with an embodiment. 
           [0048]      FIG. 23  is a top view schematic representation of a MiT probe, in accordance with an embodiment. 
           [0049]      FIG. 24  is a schematic representation of a probe tip of a MiT probe where the middle probe tip is shorter than the side probe tips, in accordance with an embodiment. 
           [0050]      FIG. 25  is a schematic representation of a probe tip of a MiT probe where the middle probe tip is shorter than the side tips, in accordance with an embodiment. 
           [0051]      FIG. 26  is a schematic representation of a probe tip of a MiT probe where a high or low-k dielectric is deposited at the apex of the middle probe tip, in accordance with an embodiment. 
           [0052]      FIG. 27  is a schematic representation of resistors which can be implemented with an MiT probe, in accordance with an embodiment. 
           [0053]      FIG. 28  is a schematic representation of a variable resistor which can be implemented with an MiT probe, in accordance with an embodiment. 
           [0054]      FIG. 29  is a schematic representation of a common source amplifier which can be implemented with a MiT probe, in accordance with an embodiment. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0055]    The present disclosure includes various embodiments of a system and method for manufacturing multiple integrated tips (MiT) probes for use with a scanning probe microscope (SPM) system. The MiT-SPM enables nanoscale atomic imaging, electrical probing of trans-conductance, and parametric analysis of a transistor, among many other aspects. 
         [0056]    Capacitive coupling and low signal-to-noise ratio leads to passive Nano-Electro-Mechanical-System (NEMS) devices generally having lower performance.  FIG. 1  shows the small signal electrical equivalent circuit of a NEMS resonator structure. The resonator can be modeled as a typical Butterworth-Van Dyke equivalent circuit where L x , C x , and R x  represent the motional inductance, capacitance and resistance respectively. C 0  is the parasitic DC capacitance of the resonator and C p  represents the total parasitic capacitance introduced from the wirebonds, circuit board and packaging. If C 0  and C p  are large, they will generate large amounts of current that will obscure the motional current of the resonator. The current from the input (V in ) to the output of the NEMS resonator has three main paths: 
         [0000]        I   f   =I   co   +I   x   +I   cp   (Eq. 1)
 
         [0057]    The admittance of the NEMS resonator is given by the following equation: 
         [0000]    
       
         
           
             
               
                 
                   Y 
                   = 
                   
                     
                       SC 
                       0 
                     
                     + 
                     
                       
                         SC 
                         X 
                       
                       
                         
                           
                             S 
                             2 
                           
                            
                           
                             L 
                             X 
                           
                            
                           
                             C 
                             X 
                           
                         
                         + 
                         
                           
                             SR 
                             X 
                           
                            
                           
                             C 
                             X 
                           
                         
                         + 
                         1 
                       
                     
                     + 
                     
                       SC 
                       p 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                      
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
         [0058]    From Equation 2, if the feedback capacitor C 0  and parasitic capacitor C p  increases, their effective impedance decreases and would sink most of the input current thus masking the motional current I x  which is the parameter of interest. To minimize the effect of C 0  and C p , either an on-board or off-board compensating capacitor can be added in parallel to cancel their effect.  FIG. 2  illustrates the parallel connection of the compensation capacitor (Static) to the resonator. The compensation capacitor is fixed to the substrate so does not generate motional current. The current from the Static structure (I co +I cp ) is inverted into I comp . I comp  is electrically combined with the current from the resonator I f . I Total  is fed into an off board transimpedance amplifier. 
         [0000]        I   comp =−( I   co   +I   cp )  (Eq. 3)
 
         [0000]        I   Total   +I   f   +I   comp   =I   x   (Eq. 4)
 
         [0059]    The compensation device is structurally identical to the resonator as shown in  FIG. 3 . The comb-drives that form the static component  112  in  FIG. 3  are fixed where as those that form the resonator component  114  are fully released from the substrate and capable of vibrating. Both AC and DC voltages are applied to electrode A 2 . The parasitic current (I co +I cp ) through the static component is inverted by on-board inverter into I comp  which is then combined with the resonator current I f . The combined current is fed into a transimpedance amplifier. The probe tip device depicted in  FIG. 3  has both a static component  112  and a resonating component  114 . The static structures are fixed on the substrate whereas the resonating structures are free to mechanically move and can be excited in a vibrational mode. 
         [0060]    The probe tip can be used to image surfaces in both AFM and Scanning Tunneling Microscopy (STM) modes. In contact mode AFM, the tip is dragged across the surface of a sample. As the tip encounters different roughness of the surface, since the tip is supported by springs, it moves up and down. This up and down movement of the tip can be sensed by the differential capacitors B 1  and B 2 . The device is biased as shown in  FIG. 4 , where AC voltages are applied to B 1  and B 2  and DC voltage applied to the probe tip. STM images can also be acquired with the biased probe tip. 
         [0061]    V SENSE  changes with the displacement of the probe tip and its value can be used to create a 3D topographical image of the surface. For small probe tip displacement the following equation is utilized: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     SENSE 
                   
                   = 
                   
                     
                       V 
                       IN 
                     
                      
                     
                       ( 
                       
                         y 
                         
                           y 
                           0 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                      
                     5 
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    where y is a small displacement caused by the probe tip in contact with a surface and y 0  is the default smallest gap between any of the fingers on B 1  or B 2  and a probe tip finger. 
       Example 1 
     Fabrication of all-Metal Probe Tips with Differential Sensing Capacitors and Feedback Cancellation Structure 
       [0062]    To ensure that there is good ohmics between the probe tip and the sample, the workfunction of the probe tip and sample should be closely matched. In most semiconductor technology nodes, tungsten plugs are used to connect a metal to the source, drain, and gate regions of the transistor. To probe these plugs, tungsten probe tips are usually used due to its hardness and high conductivity. But the tungsten probes are susceptible to oxidation which in effect render them insulating and non-ideal for electrical probing. Both chemical and mechanical techniques are used to remove the oxide on the probe tip. 
         [0063]    Other structures with different workfunctions would require different conducting probe tip materials. Platinum and gold are metals of interest for nanoprobing due to their high conductivity and non-oxidation tendencies. Gold is pretty soft and might stick to surfaces. To this end, probe tip devices with different conducting materials or metals have been fabricated as shown in the SEM image in  FIGS. 5 and 6 . Table 1, in accordance with an embodiment, provides a method for the nanofabrication of an all-metal integrated probe tip device. Referring to  FIG. 7  is an image of the finalized probe device according to the method of Table 1. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Method for Nanofabrication of All- 
               
               
                 Metal Integrated Probe Tip Device 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 100 
                 A Double Sided Polished (DSP) silicon wafer is provided. 
               
               
                 102 
                 SiO 2  is deposited via Plasma Enhanced Chemical 
               
               
                   
                 Vapor Deposition (PECVD) on both the front side and backside 
               
               
                   
                 of the wafer. Approximately 2 μm of SiO 2  is deposited, 
               
               
                   
                 although other amounts are possible. 
               
               
                 104 
                 Chromium is sputtered as an adhesion layer, followed by 
               
               
                   
                 sputtering a metal of choice, including but not limited 
               
               
                   
                 to gold, MoSi 2 , Pt, and other metals. 
               
               
                 106 
                 The photoresist is then spun, patterned, and developed. 
               
               
                 108 
                 The metal is dry etched with, for example, either ion mill or 
               
               
                   
                 Cl 2  chemistry. 
               
               
                 110 
                 Strip resist. 
               
               
                 112 
                 Spin resist on backside of wafer and pattern it, and then 
               
               
                   
                 develop the resist. 
               
               
                 114 
                 Use the resist as an etch mask to etch the backside SiO 2  layer. 
               
               
                 116 
                 Use the backside SiO 2  layer as an etch mask to etch 
               
               
                   
                 the bulk Si wafer to the front side oxide layer. 
               
               
                 118 
                 Use either vapor Hydrofluoric Acid (HF) or Buffered Oxide 
               
               
                   
                 Etch (BOE) to etch both the front side and backside SiO 2   
               
               
                   
                 layers. The probe device is fully released at this stage. 
               
               
                   
               
             
          
         
       
     
       Example 2 
     Fabrication of Probe Tip Device with Metal Overhang, Parasitic Feedthrough Self-Cancelation and Differential Sensing Capacitors 
       [0064]    The stress gradient in the metal films might bend the probe tip either upwards or downward. To mitigate the effect of stress gradient, the metal can be mechanically attached to a supporting material. 
         [0065]    According to an embodiment,  FIGS. 8, 9, and 10 , for example, show a metal terminal probe end  80  of a probe tip which sits on, is supported by, or is affixed to, a silicon supporting layer  82 . The metal probe tip  80  extends past the silicon support layer  82  and during AFM/STM imaging and nanoprobing, only the metal probe tip  80  is in contact with the sample. The metal of choice is not limited to platinum, but gold and other conductive materials can also be utilized. Also, various materials such as silicon dioxide, silicon nitride can be used for the structural support layer. The platinum tip can be used for both AFM/STM imaging and nanoprobing. An embodiment of the nanofabrication method for the metal-overhang probe tip is outlined in Table 2. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Method for Nanofabrication of a Probe Device with 
               
               
                 an Extended Conductive Material/Metal Over-Hang 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 200 
                 A Double Sided Polished (DSP) silicon wafer is provided. 
               
               
                 202 
                 Perform PECVD deposition of 2 μm SiO 2  on the handle 
               
               
                   
                 layer (back side of SOI wafer). 
               
               
                 204 
                 Sputter chromium, such as a few nanometers, as an adhesion 
               
               
                   
                 layer followed by the sputtering of metal, such as platinum 
               
               
                   
                 (Pt) on the front side of wafer. 
               
               
                 206 
                 Spin negative tone photoresist on the Pt layer. 
               
               
                 208 
                 Lithographically pattern the probe tip device, and then 
               
               
                   
                 develop the resist. 
               
               
                 210 
                 Ion mill the Pt and Cr layers, then use Deep Reactive Ion 
               
               
                   
                 Etching (DRIE) to etch the Si device layer. 
               
               
                 212 
                 Strip the photoresist. 
               
               
                 214 
                 Process the SOI handle layer by patterning the oxide etch 
               
               
                   
                 mask. Spin resist, pattern, and develop. 
               
               
                 216 
                 Use CHF 3 /O 2  chemistry to dry etch the oxide layer. 
               
               
                 218 
                 Spin positive tone resist on the SOI device layer. 
               
               
                 220 
                 Expose a few μm or nm of the tip of the probe. 
               
               
                 222 
                 Etching the silicon material below the exposed Pt layer. 
               
               
                 224 
                 Strip the resist. 
               
               
                 226 
                 Use the SiO 2  layer as an etch masks to DRIE the handle layer 
               
               
                   
                 and terminate on the BOX. 
               
               
                 228 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to etch the 
               
               
                   
                 SiO 2  backside etch mask and BOX. The probe device is fully 
               
               
                   
                 released at this stage. 
               
               
                   
               
             
          
         
       
     
         [0066]    The support layer for the metal is not limited to silicon but other materials such as silicon dioxide, silicon nitride, and MoSi 2 , among others. Two or more individual probe tips can be synchronously and simultaneously used to perform AFM or STM imaging of a sample. Using the acquired image, individual tips can be navigated to specific points on the sample. For example, the plugs in an Integrated Circuit (IC) can be nanoprobed using the device, where all the four individual probe tips are scanned simultaneously to acquire STM or AFM image and subsequently navigated to specific plugs for nanoprobing. The 3D image can then be used as feedback for positioning each tip at a particular point on the sample. 
         [0067]    According to an embodiment using the fabrication process outlined in Table 2 above, curved probe tips can be realized as shown in  FIG. 10 . These tips could have integrated deflection electrodes that can actuate and sense the probe tip in resonance as well as integrated differential capacitive sensors for sensing the motion of the probe tip device. Two or more of these curved tips can be synchronized and used to perform Atomic Force Probing of a device. 
         [0068]    According to an embodiment using the fabrication process outlined in Table 2, predefined shaped single tips with extended metal overhangs can be realized. These probe tips can be used as fabricated, or soldered to metal shank, and inserted into manipulators. If the SOI device layer is thick, then the buried oxide layer can be fully etched away to release probe tips. 
       Example 3 
     Fabrication of Monolithically Integrated Probe Tips with Interdigitated Structures Between Two or More Probe Tips 
       [0069]    Freely released and suspended multiple integrated tips tend to pull-in to each other after the release process or during nanoprobing. To mitigate the pull-in effect, interdigitated structures can be monolithically inserted between the probes. Table 3 below illustrates the fabrication process for monolithically implementing the interdigitated structures, in accordance with an embodiment. Referring to  FIG. 11  is an image of the finalized probe device according to the method of Table 3. In  FIG. 11 , for example, the probe includes a structure  90  with interdigitated structures  92  positioned between and on the outer side of the probe tips  94 . 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Method for Implementing Monolithically Interdigitated 
               
               
                 Structures Between Probe Tips. 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 300 
                 Start with an SOI wafer. 2 μm device layer and 2 μm buried 
               
               
                   
                 oxide (BOX) layer. 
               
               
                 302 
                 PECVD deposition of 2 μm SiO 2  on the handle layer (backside 
               
               
                   
                 of SOI wafer). 
               
               
                 304 
                 Sputter a few nanometers of Cr as an adhesion layer followed 
               
               
                   
                 by sputtering a metal of choice, such as gold, MoSi 2 , Pt, and 
               
               
                   
                 others. 
               
               
                 306 
                 Spin negative tone photoresist on the metal layer. 
               
               
                 308 
                 Lithographically pattern the probe tip device. Develop the 
               
               
                   
                 resist. 
               
               
                 310 
                 Ion mill the Pt and Cr layers. Then use DRIE to etch the Si 
               
               
                   
                 device layer. 
               
               
                 312 
                 Strip the photoresist. 
               
               
                 314 
                 Process the SOI handle layer by patterning the SiO 2  etch mask. 
               
               
                   
                 Spin resist, pattern and develop. 
               
               
                 316 
                 Use CHF 3 /O 2  chemistry to dry etch the oxide layer. Strip the 
               
               
                   
                 resist. 
               
               
                 318 
                 Deposit a few nanometers of conformal SiO 2  by Atomic Layer 
               
               
                   
                 Deposition (ALD). Then deposit another layer of conformal 
               
               
                   
                 undoped Si (polysilicon or amorphous). Spray coat photoresist, 
               
               
                   
                 pattern and etch undoped Si and SiO 2  layers. The probes tips 
               
               
                   
                 are sandwiched in SiO 2  and Si interdigitated structures. 
               
               
                 320 
                 Spray coat photoresist on the SOI device layer. 
               
               
                 322 
                 Expose a few μm or nm of the tip of the probe device. 
               
               
                 324 
                 Etch the silicon material below the exposed Pt layer. 
               
               
                 326 
                 Strip the resist. 
               
               
                 328 
                 Use the SiO 2  layer as an etch masks to DRIE the handle layer 
               
               
                   
                 and terminate on the BOX. 
               
               
                 330 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to etch 
               
               
                   
                 the SiO 2  etch mask and BOX layer. The SiO 2  layers 
               
               
                   
                 surrounding the interdigitated structures are also removed 
               
               
                   
                 with vapor HF or BOE. The probe device is fully released at 
               
               
                   
                 this stage. 
               
               
                   
               
             
          
         
       
     
         [0070]    The 4-tip MiT probe can be considered as a Ground-Signal-Ground Signal (GSGS) probe device where two signals that are out-of-phase can be introduced on the Signal probes and shielded by the Ground probes. Bottom electrodes can also be placed below each probe tip for controlled downward deflection of each probe tip. The tips can be used for conventional 4-point probing. Also, the 4 probes can be scanned across a sample surface and the current between any of the two tips can be used for imaging the surface. 
       Example 4 
     Fabrication of Monolithically Integrated Probe Tips with Bottom Actuation Electrodes 
       [0071]    Certain STM/AFM imaging and nanoprobing require that probe tips exhibit 3 Degrees of Freedom (DOF).  FIG. 12  is the top view of a monolithically integrated tips device with 3 DOF. Applied voltages to electrode A 2  move the middle probe tip in-plane whereas applied voltages to electrodes C 1  or C 2  laterally deflects the middle probe tip. Electrode E 3  runs below the middle probe tip and applied voltages to E 3  bends down the middle probe tip towards the substrate. The side probe tips also have electrodes E 1  and E 2  that bend down the tips when actuated. Table 4 illustrates the fabrication of MiT probe with 3 DOF where the bottom electrodes (E 1 , E 2  and E 3 ) are used to deflect the probe tips out of plane. Referring to  FIG. 13  is an image of the finalized probe device according to the method of Table 4. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 4 
               
             
             
               
                   
               
               
                 Fabrication of MiT Probe With 3 DOF. 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 400 
                 Start with undoped Double Sided Polished (DSP) silicon wafer. 
               
               
                 402 
                 Deposit 2 μm of PECVD SiO 2  on one side of the DSP polished 
               
               
                   
                 wafer. 
               
               
                 404 
                 Pattern the SiO 2  layer with photoresist then etch the SiO 2  layer. 
               
               
                 406 
                 Strip the photoresist 
               
               
                 408 
                 Spin resist on frontside of the wafer. 
               
               
                 410 
                 Pattern the bottom actuation electrodes. 
               
               
                 412 
                 Using the resist as an etch mask, etch about 500 nm into the 
               
               
                   
                 silicon wafer. Strip resist. 
               
               
                 414 
                 Sputter about 1 μm of 1 st  metal layer to fill-in the etched 
               
               
                   
                 trenches. 
               
               
                 416 
                 Perform Chemical Mechanical Polishing (CMP) to planarize 
               
               
                   
                 the wafer surface. The bottom electrodes are embedded into 
               
               
                   
                 the silicon wafer. 
               
               
                 418 
                 Deposit 2 μm of PECVD SiO 2  on the frontside of the wafer. 
               
               
                 420 
                 Deposit highly doped polysilicon, amorphous silicon or MoSi 2   
               
               
                   
                 onto the frontside SiO 2  layer. 
               
               
                 422 
                 Sputter a few nanometers of Cr to serve as adhesion layer 
               
               
                   
                 followed by sputtering of 2 nd  metal layer. 
               
               
                 424 
                 Spin resist, pattern, and develop the photoresist. Ion mill 
               
               
                   
                 the Cr and 2 nd  metal layer and use DRIE to etch the 
               
               
                   
                 polysilicon layer. 
               
               
                 426 
                 Strip resist. 
               
               
                 428 
                 Spray resist and pattern a region to expose the tips. 
               
               
                 430 
                 Etch the silicon material below the exposed Pt layer. 
               
               
                 432 
                 Strip resist. 
               
               
                 434 
                 Process the backside of the wafer by DRIE the wafer using the 
               
               
                   
                 backside SiO 2  layer. 
               
               
                 436 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both 
               
               
                   
                 the frontside and backside SiO 2  layers. The probe device is 
               
               
                   
                 fully released at this stage. 
               
               
                   
               
             
          
         
       
     
         [0072]    The bottom electrodes are used to deflect the probes out-of-plane. The metal choice for the actuation electrodes (1 st  metal layer) and the probe tips (2 nd  metal layer) could be the same or different. The 3-Tip MiT probe configuration allows these probes to be used as Ground-Signal-Ground (GSG) RF/microwave probes for testing microwave and RF circuits. The 3-Tip MiT probe can also be used for AFP. Using the fabrication process outlined in Table 4 above, a 5-point probe device can be realized. The middle probe tip is used for AFM/STM imaging then it is retracted and the remaining 4 probe tips are used for conventional 4-point probe measurements. 
       Example 5 
     Fabrication of Monolithically Integrated Probe Tips with Bottom and Side Actuation Electrodes 
       [0073]    According to an embodiment is the fabrication of monolithically integrated probe tips with bottom and side actuation electrodes, where the side tips are laterally deflected. The side probe tips can be independently controlled by applying voltages to electrodes E 1  and E 2  (bottom electrodes) and F 1  and F 2  (side electrodes) as shown in  FIG. 14 . Illustrated in Table 5 below is the fabrication of an MiT probe with 3 DOF where the bottom electrodes (E 1 , E 2  and E 3 ) are used to deflect the probe tips out-of-plane. F 1  and F 2  are independently used to laterally deflect the side tips. Referring to  FIG. 15  is an image of the finalized probe device according to the method of Table 5. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 5 
               
             
             
               
                   
               
               
                 Fabrication of MiT Probe with 3 DOF 
               
               
                 and Side Actuation Electrodes. 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 500 
                 Start with undoped DSP silicon wafer. 
               
               
                 502 
                 Deposit 2 μm of PECVD SiO 2  on one side of the DSP polished 
               
               
                   
                 wafer. 
               
               
                 504 
                 Pattern the SiO 2  layer with photoresist then etch the SiO 2   
               
               
                   
                 layer. 
               
               
                 506 
                 Strip the photoresist. 
               
               
                 508 
                 Spin resist on frontside of the wafer. 
               
               
                 510 
                 Pattern the bottom actuation electrodes. 
               
               
                 512 
                 Using the resist as an etch mask, etch about 500 nm into 
               
               
                   
                 the silicon wafer. Strip resist. 
               
               
                 514 
                 Sputter about 1 μm of 1 st  metal layer to fill-in the 
               
               
                   
                 etched trenches. 
               
               
                 516 
                 Perform CMP to planarize the wafer surface. The bottom 
               
               
                   
                 electrodes are embedded into the silicon wafer. 
               
               
                 518 
                 Deposit 2 μm of PECVD SiO 2  on the frontside of the wafer. 
               
               
                 520 
                 Deposit highly doped polysilicon, amorphous silicon or MoSi 2   
               
               
                   
                 onto the frontside SiO 2  layer. 
               
               
                 522 
                 Sputter a few nanometers of Cr to serve as adhesion layer 
               
               
                   
                 followed by sputtering of 2 nd  metal layer. 
               
               
                 524 
                 Spin resist, pattern, and develop the photoresist. Ion mill 
               
               
                   
                 the Cr and 2 nd  metal layer and use DRIE to etch the 
               
               
                   
                 polysilicon layer. 
               
               
                 526 
                 Strip resist. 
               
               
                 528 
                 Spray coat resist and pattern a region to expose the tips. 
               
               
                 530 
                 Etch the silicon material below the exposed Pt layer. 
               
               
                 532 
                 Strip resist. 
               
               
                 534 
                 Process the backside of the wafer by DRIE the wafer using the 
               
               
                   
                 backside SiO 2  layer. 
               
               
                 536 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both 
               
               
                   
                 the frontside and backside SiO 2  layers. The probe device is 
               
               
                   
                 fully released at this stage. 
               
               
                   
               
             
          
         
       
     
       Example 6 
     Fabrication of Monolithically Integrated Probe Tips with Top and Bottom Actuation Electrodes 
       [0074]    In certain applications, the middle probe tip might be required to be deflected both down (towards the substrate) and up (away from the substrate). Table 6 illustrates the fabrication process steps in realizing such a device. The metal choice for the actuation electrodes (1 st  metal) and the probe tips (2 nd  metal) could be the same or different. Referring to  FIG. 16  is an image of the finalized probe device according to the method of Table 6, where the middle probe tip can deflect both up and down with respect to the substrate. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 6 
               
             
             
               
                   
               
               
                 Fabrication Process for Making MiT Probe with 3 DOF. 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 600 
                 Start with an undoped DSP silicon wafer. 
               
               
                 602 
                 Deposit 2 μm of PECVD SiO 2  on one side of the DSP 
               
               
                   
                 polished wafer. 
               
               
                 604 
                 Pattern the SiO 2  layer with photoresist then etch the 
               
               
                   
                 SiO 2  layer. 
               
               
                 606 
                 Strip the photoresist 
               
               
                 608 
                 Spin resist on frontside of the wafer. 
               
               
                 610 
                 Pattern the bottom actuation electrodes. 
               
               
                 612 
                 Using the resist as an etch mask, etch about 500 nm into 
               
               
                   
                 the silicon wafer. Strip resist. 
               
               
                 614 
                 Sputter about 1 μm of 1 st  metal to fill-in the etched 
               
               
                   
                 trenches. 
               
               
                 616 
                 Perform CMP to planarize the wafer surface. The bottom 
               
               
                   
                 electrode is embedded into the silicon wafer. 
               
               
                 618 
                 Deposit 2 μm of PECVD SiO 2  on the frontside of the wafer. 
               
               
                 620 
                 Deposit highly doped polysilicon, amorphous silicon or MoSi 2   
               
               
                   
                 onto the frontside SiO 2  layer. 
               
               
                 622 
                 Sputter a few nanometers of Cr to serve as adhesion layer 
               
               
                   
                 followed by sputtering of 2 nd  metal. 
               
               
                 624 
                 Spin resist, pattern, and develop the photoresist. Ion mill 
               
               
                   
                 the Cr and 2 nd  metal layer and use DRIE to etch the 
               
               
                   
                 polysilicon layer. 
               
               
                 626 
                 Strip resist 
               
               
                 628 
                 Deposit PECVD SiO 2  and planarize by CMP. Next, deposit 
               
               
                   
                 undoped polysilicon or undoped amorphous silicon. Spin 
               
               
                   
                 resist and pattern the silicon top bridge. Etch the 
               
               
                   
                 pattern into the undoped polysilicon or amorphous 
               
               
                   
                 silicon layer. Strip resist. 
               
               
                 630 
                 Sputter top metal layer. 
               
               
                   
                 Spin resist and pattern the top metal layer. Use the resist 
               
               
                   
                 as an etch mask and use the ion mill to etch the metal layer. 
               
               
                 632 
                 Spin and pattern the photoresist. 
               
               
                 634 
                 Pattern the resist and etch the SiO 2  layer to expose the probe 
               
               
                   
                 tips. Etch the silicon material below the exposed Pt layer. 
               
               
                 636 
                 Strip resist. 
               
               
                 638 
                 Use the backside SiO 2  layer as DRIE etch mask to etch the 
               
               
                   
                 wafer. 
               
               
                 640 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both 
               
               
                   
                 the frontside and backside SiO 2  layers. The probe device is fully 
               
               
                   
                 released at this stage. The top electrode is suspended above the 
               
               
                   
                 middle probe tip. 
               
               
                   
               
             
          
         
       
     
       Example 7 
     Fabrication of Monolithically Integrated Self-Aligned Stacked Probe Devices 
       [0075]    Several MiT probes can be monolithically vertically integrated to offer several probe tips that can be used to probe structures on a wafer. Table 7 illustrates the fabrication process for the vertically stacked MiT probes. The metal choice used in the MiT probe stack could be the same (1 st  metal is the same as 2 nd  metal) or different (1 st  metal is different from 2 nd  metal). The MiT probe stack is not limited to two layers but several layers can also be implemented using the outlined fabrication process flow. The stacked MiT probes can also be realized in standard CMOS processes where the different metal layers can be used as the probe tips. Referring to  FIG. 17  is an image of the finalized probe device according to the method of Table 7. The finalized probe comprises a first probe set  96  and a second probe set  98 , the first probe set being vertically stacked compared to the second probe set. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 7 
               
             
             
               
                   
               
               
                 Fabrication Process for Vertically Stacked Monolithically 
               
               
                 Integrated Probe Tip Devices. 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 700 
                 Start with a DSP silicon wafer. 
               
               
                 702 
                 Deposit SiO 2  on both frontside and backside of wafer. 
               
               
                 704 
                 Pattern the SiO 2  layer with photoresist then etch the SiO 2  layer. 
               
               
                 706 
                 Strip the photoresist. 
               
               
                 708 
                 On the fronside of the wafer, sequentially deposit 1 st  metal, SiO 2   
               
               
                   
                 and 2 nd  metal layers. 
               
               
                 710 
                 Spin resist and pattern it. 
               
               
                 712 
                 Etch the 2 nd  metal, SiO 2  and 1 st  metal layers. 
               
               
                 714 
                 Strip the resist. 
               
               
                 716 
                 Use the backside SiO 2  layer as DRIE etch mask to etch the 
               
               
                   
                 wafer. 
               
               
                 718 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both 
               
               
                   
                 the frontside and backside SiO 2  layers. The probe device is 
               
               
                   
                 fully released at this stage. 
               
               
                   
               
             
          
         
       
     
       Example 8 
     Fabrication of Monolithically Integrated Fabrication of Monolithically Integrated Self-Aligned Stacked Probe Devices with Post Processed Probe Tip Configuration. Self-Aligned Stacked Probe Devices 
       [0076]    Each MiT probe that makeup the vertically stacked monolithically integrated probe tip devices that was illustrated in Table 7 above have the same number of probe tips. In certain applications, a modified probe tip configuration might be required. In such situations, the FIB can be used to remove unneeded probe tips, as shown in Table 8. Removal of unneeded probe tips is not limited to the use of FIB but other means such as ion milling and reactive ion etching are possible. The metal choice used in the MiT probe stack could be the same (1 st  metal the same as 2 nd  metal) or different (1 st  metal different from 2 nd  metal). The MiT probe stack is not limited to two layers but several layers can also be implemented using the outlined fabrication process flow. Referring to  FIG. 18  is an image of the finalized probe device according to the method of Table 8. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 8 
               
             
             
               
                   
               
               
                 Fabrication Process for Vertically Stacked Monolithically Integrated 
               
               
                 Probe Tip Devices with FIB-Modified Probe Tip Configuration. 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 800 
                 Start with DSP silicon wafer. 
               
               
                 802 
                 Deposit SiO 2  on both frontside and backside of wafer. 
               
               
                 804 
                 Pattern the SiO 2  layer with photoresist then etch the 
               
               
                   
                 SiO 2  layer. 
               
               
                 806 
                 Strip the photoresist. 
               
               
                 808 
                 On the frontside of the wafer, sequentially deposit 
               
               
                   
                 1 st  metal, SiO 2  and 2 metal layers. 
               
               
                 810 
                 Spin resist and pattern it. 
               
               
                 812 
                 Etch the 2 nd  metal, SiO 2  and 1 st  metal layers. 
               
               
                 814 
                 Strip the resist. 
               
               
                 816 
                 From the backside of the wafer, etch the Si wafer 
               
               
                   
                 and SiO 2  layer on both the backside and the 
               
               
                   
                 exposed part of the frontside. 
               
               
                 818 
                 Use the FIB to mill part of the 1 st  metal of the 
               
               
                   
                 middle probe tip. 
               
               
                 820 
                 Use the FIB to mill part of the 2 nd  metal of the 
               
               
                   
                 side tips. 
               
               
                 822 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to 
               
               
                   
                 etch the frontside SiO 2  layers. The probe device is 
               
               
                   
                 fully released at this stage. 
               
               
                   
               
             
          
         
       
     
       Example 9 
     Fabrication of Monolithically Integrated Out-of-Plane Probe Tip Device 
       [0077]    SRAM, DRAM and flash memory are typically arrayed and the plug spacing for the source, drain and gate are fixed. These plugs could be relatively easily accessed with MiT probes that have predefined tip configurations that directly address these specific plug layouts. The MiT probes can be designed specifically for a particular technology node and semiconductor foundry. The metal choice used for the probe tips in the MiT probe could be the same (1 st  metal the same as 2 nd  metal) or different (1 st  metal different from 2 nd  metal), as shown in Table 9. Referring to  FIG. 19  is an image of the finalized probe device according to the method of Table 9. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 9 
               
             
             
               
                   
               
               
                 Fabrication Process for Out-of-Plane MiT Probe. 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 900 
                 Start with a DSP silicon wafer. 
               
               
                 902 
                 Deposit SiO 2  on both sides of the wafer. 
               
               
                 904 
                 Spin photoresist and pattern the backside of the wafer. 
               
               
                   
                 Etch the backside SiO 2  layer. 
               
               
                 906 
                 Strip the photoresist. 
               
               
                 908 
                 Spin photoresist on the frontside and pattern the side 
               
               
                   
                 probe tips. Reactive Ion Etching (RIE) halfway into the 
               
               
                   
                 SiO 2  layer and strip the photoresist. 
               
               
                 910 
                 Sputter the 1 st  metal layer on the frontside of the wafer. 
               
               
                 912 
                 Perform Chemical Mechanical Polishing (CMP) to planarize 
               
               
                   
                 the frontside of wafer. 
               
               
                 914 
                 On the frontside of the wafer, sequentially deposit another 
               
               
                   
                 SiO 2  layer followed by sputtering a 2 nd  metal layer. The 1 st   
               
               
                   
                 and 2 nd  metal layers could be the same or different metals. 
               
               
                 916 
                 Spin resist and pattern it. 
               
               
                 918 
                 Etch 2 nd  metal layer and frontside SiO 2  layer. Strip photoresist. 
               
               
                 920 
                 Use the backside SiO 2  layer as an etch mask to DRIE the wafer 
               
               
                   
                 to the frontside SiO 2  layer. 
               
               
                 922 
                 Dry etch both the backside and frontside SiO 2  layers. 
               
               
                 924 
                 The side probe tips are embedded in the SiO 2  layer while the 
               
               
                   
                 middle probe tip sits on a SiO 2  support layer. 
               
               
                   
               
             
          
         
       
     
       Example 10 
     Fabrication of Monolithically Integrated Freely Suspended Out-of-Plane Probe Tip Device 
       [0078]    The out-of-plane MiT probe that was illustrated in Table 9 above had the middle probe tip fixed to the SiO 2  support layer. Table 10 below details out the fabrication of a fully suspended and movable out-of-plane middle probe tip device. Referring to  FIG. 20  is an image of the finalized probe according to the method of Table 10. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 10 
               
             
             
               
                   
               
               
                 Process for Making Monolithically Integrated 
               
               
                 Freely Suspended Out-of-Plane MiT Probe 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 1000 
                 Start with DSP silicon wafer. 
               
               
                 1002 
                 Deposit SiO 2  on both sides of the wafer. 
               
               
                 1004 
                 Spin photoresist and pattern the backside of the wafer. 
               
               
                   
                 Etch the backside SiO 2  layer. 
               
               
                 1006 
                 Strip the photoresist. 
               
               
                 1008 
                 Spin photoresist on the frontside and pattern the side 
               
               
                   
                 probe tips. RIE halfway into the SiO 2  layer and strip 
               
               
                   
                 the photoresist. 
               
               
                 1010 
                 Sputter the 1 st  metal layer on the frontside of the wafer. 
               
               
                 1012 
                 Perform Chemical Mechanical Polishing (CMP) to planarize 
               
               
                   
                 the frontside of wafer. 
               
               
                 1014 
                 On the frontside of the wafer, sequentially deposit another 
               
               
                   
                 SiO 2  layer followed by sputtering a 2 nd  metal layer. The 1 st   
               
               
                   
                 and 2 nd  metal layers could be the same or different metals. 
               
               
                 1016 
                 Spin resist and pattern it. 
               
               
                 1018 
                 Etch 2 nd  metal layer and strip photoresist. 
               
               
                 1020 
                 Use the backside SiO 2  layer as an etch mask to DRIE the wafer 
               
               
                   
                 to the frontside SiO 2  layer. 
               
               
                 1022 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both 
               
               
                   
                 the frontside and backside SiO 2  layers. The probe device is 
               
               
                   
                 fully released at this stage. 
               
               
                   
               
             
          
         
       
     
         [0079]    According to an embodiment, various combinations of the different probe configurations (single tip, 2, 3 and/or 4-Tip MiT probes) can be simultaneously used to scan and nanoprobe. According to one example, a 3-Tip MiT probe could be utilized to access the source, drain, gate plugs of a transistor then bringing in an independent single tip device to probe the bulk (body) of the transistor. 
         [0080]    Fabrication of monolithically integrated freely suspended out-of-plane probe tip device with bottom and side actuation electrodes. 
         [0081]    Bottom electrodes are used to deflect the probe tips up or down with respect to the substrate. But in certain applications, the side probe tips might need to be laterally deflected. For instance, when the gate length of two transistors varies, the side tips must be laterally deflected in order to access the source and drain plugs. Table 11 below illustrates the fabrication process flow for making MiT probes with side actuation electrodes. Referring to  FIG. 21  is an image of the finalized probe device according to the method of Table 11. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 11 
               
             
             
               
                   
               
               
                 Fabrication Process Flow for Making Monolithically 
               
               
                 Integrated Freely Suspended Out-of-Plane MiT Probe 
               
               
                 with Side and Bottom Actuation Electrodes. 
               
             
          
           
               
                 Step # 
                 Process 
               
               
                   
               
               
                 1100 
                 Start with undoped DSP silicon wafer. 
               
               
                 1102 
                 Deposit 2 μm of PECVD SiO 2  on one side of the DSP polished 
               
               
                   
                 wafer. 
               
               
                 1104 
                 Pattern the SiO 2  layer with photoresist then etch the SiO 2  layer. 
               
               
                 1106 
                 Strip the photoresist 
               
               
                 1108 
                 Spin resist on frontside of the wafer. 
               
               
                 1110 
                 Pattern the bottom actuation electrodes. 
               
               
                 1112 
                 Using the resist as an etch mask, etch about 500 nm into the 
               
               
                   
                 silicon wafer. Strip resist. 
               
               
                 1114 
                 Sputter about 1 μm of 1 st  metal layer to fill-in the etched 
               
               
                   
                 trenches. 
               
               
                 1116 
                 Perform Chemical Mechanical Polishing (CMP) to planarize the 
               
               
                   
                 wafer surface. The bottom electrodes are embedded into the 
               
               
                   
                 silicon wafer. 
               
               
                 1118 
                 Spin photoresist on the frontside and pattern the side probe tips. 
               
               
                   
                 RIE halfway into the SiO 2  layer and strip the photoresist. 
               
               
                 1120 
                 Sputter the 1 st  metal layer on the frontside of the wafer. 
               
               
                 1122 
                 Perform Chemical Mechanical Polishing (CMP) to planarize the 
               
               
                   
                 frontside of wafer. 
               
               
                 1124 
                 On the frontside of the wafer, sequentially deposit another 
               
               
                   
                 SiO 2  layer followed by sputtering a 2 nd  metal layer. The 1 st   
               
               
                   
                 and 2 nd  metal layers could be the same or different metals. 
               
               
                 1126 
                 Spin resist and pattern it. 
               
               
                 1128 
                 Etch 2 nd  metal layer and strip photoresist. 
               
               
                 1130 
                 Use the backside SiO 2  layer as an etch mask to DRIE the wafer 
               
               
                   
                 to the frontside SiO 2  layer. 
               
               
                 1132 
                 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both 
               
               
                   
                 the frontside and backside SiO 2  layers. The probe device is 
               
               
                   
                 fully released at this stage. 
               
               
                   
               
             
          
         
       
     
         [0082]    According to an embodiment, the lateral actuation electrodes for the side probe tips can be implemented for all the above MiT probe designs. 
         [0083]    Implementation of Mobile Circuits with Multiple Integrated Tip Device. 
         [0084]    The MiT probes can be used to implement various active and passive circuit components (transistor, resistor, diode and capacitor) on substrates. Since the MiT probe is capable of electrically mapping different regions of a substrate, at each spot, an active or passive component can be implemented on the substrate. Thus, these components are not lithographically fixed to the substrate but are mobile. For example, the 3-Tips MiT probe can be used to implement a transistor on a substrate. The middle probe tip represents the gate and the side probe tips are the source and drain terminals as shown in  FIG. 22 . The side tips are in soft contact with the substrate whereas the middle probe tip can either be in soft contact (the tip has a dielectric coating) or proximity (air gap serves as the gate dielectric). At any location on the substrate, a transistor can be formed. Thus, both the output and transfer curves of a transistor can be mapped at each point on the surface of a substrate. The substrate could be a 2D material such as graphene, molybdenum disulphide, silicon substrate, GaN wafer substrate, etc. 
         [0085]    Referring to  FIG. 23  is the design of the 3-Tip MiT probe showing various actuation electrodes.  FIGS. 24 and 25  show the tip design of the 3-Tip MiT probe and the gate capacitance between the middle probe tip and the substrate respectively. The middle tip is designed to be shorter than the side probe tips. The gate capacitance can be varied by applying DC voltages to electrode A 2  which would retract or extend the middle probe tip. Thus, the effect of the gate capacitance on the transistor performance can be measured and investigated.  FIG. 26  on the other hand shows a 3-Tip MiT probe which has a few nanometers of either high or low-k dielectric that is deposited at the apex of the middle probe tip. The dielectric layer serves as the gate oxide and the middle probe tip is aligned with the side probe tips. 
         [0086]    A variable resistor on the other hand can be implemented by changing the spacing between the middle probe tip and any of the side tips. Applied voltages to C 1  or C 2  would laterally deflect the middle probe tip. By varying the tip spacing and contacting the substrate, different substrate resistance values can be achieved as demonstrated in  FIGS. 27 and 28 . 
         [0087]    Two or more active or passive circuit components that are implemented with two or more MiT probes can be cascaded to form various circuits such as common source amplifier, common gate amplifier, a source follower, etc.  FIG. 29  shows the typical circuit configuration of a common source amplifier. This circuit could be implemented by at least a 3-Tip MiT probe and either a 2, 3, or 4-Tip MiT probe. As an example, two 3-Tip MiT probes where one of the MiT probes would implement the transistor and the other would implement the resistor. Or a 3-Tip MiT probe for the transistor and 2-Tips or 4-Tips MiT probe for the resistor. 
         [0088]    While various embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, embodiments may be practiced otherwise than as specifically described and claimed. Embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure. 
         [0089]    The above-described embodiments of the described subject matter can be implemented in any of numerous ways. For example, some embodiments may be implemented using hardware, software or a combination thereof. When any aspect of an embodiment is implemented at least in part in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single device or computer or distributed among multiple devices/computers.