Abstract:
A level shift circuit in accordance with the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. A dv/dt sensing circuit is provided to detect any slew in offset between negative supply voltages and ground in a circuit. This detection is used to control a noise canceling circuit to ensure that noise that results from that offset is not propagated to the output of the level shift circuit. A parasitic emulator is preferably used to provide dv/dt sensing. The output of the parasitic emulator is used to activate a noise canceling circuit to prevent noise from reaching the output terminal of the level shift circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims benefit of and priority to U.S. Provisional Patent Application Ser. No. 60/915,155 entitled CURRENT MODE NOISE IMMUNE HIGH VOLTAGE LEVEL SHIFTING SCHEME filed May 1, 2007, the entire contents of which are hereby incorporated by reference herein. 
     
    
     BACKGROUND 
       [0002]    1. Field of the Disclosure 
         [0003]    The present invention relates to a level shift circuit with improved dv/dt sensing and noise blocking. 
         [0004]    2. Related Art 
         [0005]    Level shift of high voltage signals (up to several hundred volts) is an essential feature of most power systems. Level shifting allows for isolation between low voltage control signals and a relatively high voltage switching power output, for example. High voltage level shifting is typically accomplished using high voltage isolation technology. However, this technology typically has long propagation delays and a relatively low operating speed. As new applications and system architectures are developed, operational speed requirements are often in the range of Megahertz, thus the delays present in the conventional technology are not acceptable. 
         [0006]    More specifically, traditional high voltage level shift schemes have several disadvantages in both cost and performance. First, the Hall effect sensors and optical isolation devices typically used are bulky and slow. Further, these elements are also difficult to integrate onto a chip. As is mentioned above, present technology is also typically subject to low frequency operation in light of the propagation delays noted above. In addition, these systems are also subject to limited pulse width linearity and high power dissipation. Further, some of these systems such as, for example, the cross-coupled high speed level shift circuit described in U.S. Pat. No. 7,212,033 are sensitive to fabrication mismatches. 
         [0007]    Accordingly, it would be beneficial to provide a level shift circuit that avoids the problems discussed above. 
       SUMMARY OF THE INVENTION 
       [0008]    It is an object of the present invention to provide a monolithic, high speed, common mode noise immune level shift circuit using dv/dt sensing and control to provide signal level shifting up to several hundreds of volts or more with an operating speed of 10 Mbits or more. 
         [0009]    The level shift circuit of the present application preferably uses dv/dt sensing, mismatch filtering and noise signal blocking techniques. An emulator is preferably provided to detect any positive swing in the floating ground and to generate a logic signal that quickly turns on the noise blanking circuit. 
         [0010]    The level shift circuit of the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation for dv/dt sensing, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. The parasitic capacitance emulating element is chosen as an element similar to the devices causing common mode noise in the high voltage level shift node. The output of the parasitic emulator prevents noise from reaching the level shift output terminal. The level shift signal and noise is delayed through a pulse filter. The pulse filter delay is chosen long enough to compensate for a timing mismatch between the level shift noise, the common mode noise detector signal, and the delay to disable noise from propagating to the output terminal. 
         [0011]    A dv/dt sensing circuit for use in a level shift down circuit including a midwell and a lowside in accordance with an embodiment of the present application includes a parasitic capacitance emulator positioned in the midwell and a resistor positioned in the lowside and connected to the parasitic capacitance emulator, such that a detect voltage is provided at a node between the parasitic capacitance emulator and the resistor when a midwell negative supply voltage changes relative to ground. The dv/dt sensing circuit provides a detect signal based on the detect voltage. 
         [0012]    A dv/dt sensing circuit for use in a level shift up circuit including a highside and a lowside in accordance with an embodiment of the present application includes a parasitic capacitance emulator positioned in the lowside and a resistor positioned in the highside and connected to the parasitic capacitance emulator, such that a detect voltage is provided at a node between the parasitic capacitance emulator and the resistor when a highside negative supply voltage changes relative to ground. The dv/dt sensing circuit provides a detect signal based on the detect voltage. 
         [0013]    A noise canceling circuit for use in a level shift down circuit including a midwell and a lowside in accordance with an embodiment of the present application includes a first disable block positioned in the lowside and operable to disable level shift signaling based on a control signal. A second disable block may be positioned in the lowside in front a pulse filter and operable to prevent a noise signal from passing to the pulse filter based on the control signal. In addition, a third disable block may be positioned in the lowside at an output of the pulse filter and prior to an output terminal of the level shift down circuit, the third disable device is preferably operable to prevent any noise signal from passing from the pulse filter to the output terminal of the level shift down circuit based on the control signal. Preferably, at least one of the first disable block, the second disable block and/or the third disable block prevents propagation of noise signals to the output terminal of the level shift down circuit. 
         [0014]    A noise canceling circuit for use in a level shift up circuit including a highside and a lowside in accordance with an embodiment of the present application includes a first disable block positioned in the highside and operable to disable level shift signaling based on a control signal. A second disable block may be positioned in the highside in front of a pulse filter and operable to prevent a noise signal from passing to the pulse filter. A third disable block positioned in the highside at an output of the pulse filter and prior to an output terminal of the level shift up circuit, the third disable device operable to prevent any noise signal from passing from the pulse filter to the output terminal based on the control signal. In a preferred embodiment, at least one of the first disable block, the second disable block and/or the third disable block prevents propagation of noise signals to the output terminal of the level shift up circuit. 
         [0015]    A level shift down integrated circuit including a midwell and a lowside in accordance with an embodiment of the present application includes a dv/dt sensing circuit operable to detect when a midwell negative supply voltage changes relative to ground and to provide a detect signal indicating that the midwell negative supply voltage has changed relative to ground and a noise canceling circuit positioned in the lowside and operable to prevent a noise signal from propagating to an output of the level shift down circuit based on the detect signal. 
         [0016]    A level shift up integrated circuit including a highside and a lowside in accordance with an embodiment of the present application includes a dv/dt sensing circuit operable to detect when a highside negative supply voltage changes relative to ground and to provide a detect signal indicating that the highside negative supply voltage has changed relative to ground and a noise canceling circuit positioned in the highside and operable to prevent a noise signal from propagating to an output of the level shift up circuit based on the detect signal. 
         [0017]    Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING(S) 
         [0018]      FIG. 1  illustrates an example of a convention level shift down circuit; 
           [0019]      FIG. 2  illustrates an example of a convention level shift up circuit; 
           [0020]      FIG. 3  illustrates the level shift down circuit of  FIG. 1  with parasitic capacitances shown explicitly; 
           [0021]      FIG. 4  illustrates a dv/dt sensing circuit in accordance with an embodiment of the present application; 
           [0022]      FIG. 4A  is a detailed view of a parasitic capacitance emulator of the dv/dt sensing circuit of  FIG. 4 ; 
           [0023]      FIG. 5  illustrates a noise blocking circuit in accordance with an embodiment of the present application; 
           [0024]      FIG. 6A  illustrates a level shift down circuit including the dv/dt sensing circuit of  FIG. 4  and the noise canceling circuit of  FIG. 5 ; 
           [0025]      FIG. 6B  illustrates a level shift up circuit including the dv/dt sensing circuit of  FIG. 4  and the noise canceling circuit of  FIG. 5 . 
           [0026]      FIG. 7  is a graph illustrating typical waveforms of the level shift down circuit of  FIG. 1 ; 
           [0027]      FIG. 8  is a graph illustrating the timing diagram of the level shift down circuit of  FIG. 3 ; 
           [0028]      FIG. 9  is a graph illustrating the waveforms of the circuit of  FIG. 4 ; 
           [0029]      FIG. 10  is a graph illustrating the waveforms of  FIG. 6A ; and 
           [0030]      FIG. 11  is a graph illustrating the waveforms of  FIG. 6B . 
       
    
    
     DETAILED DESCRIPTION  
       [0031]    The level shift circuit of the present application provides a novel approach to high speed level shifting with hundreds of volts isolation that also allows for the rejection of common mode noise up to 100V/ns using standard CMOS processing technology, 
         [0032]    The level shift circuit of the present application integrates dv/dt sensing and noise signal blocking techniques. An active device is used as the sensing element to detect any swing in the floating ground and to generate a logic level and quickly turn on the noise blanking circuit. 
         [0033]    Electrical signaling between circuits whose ground references differ by several hundred volts requires a level shift circuit. Level shift circuits that transmit a signal from a high ground potential to a low ground potential are referred to as level shift down circuits, and level shift circuits that transmit a signal from a low ground potential to a high ground potential are called level shift up circuits.  FIG. 1  illustrates an example of a prior art level shift down circuit while  FIG. 2  illustrates an example of a level shift up circuit. 
         [0034]    The isolated high voltage (HV) domains of a monolithic integrated circuit are referred to as the midwell, lowside and highside. The prior art level shift down circuit  10  of  FIG. 1  has a midwell  10   a  and a lowside  10   b . The midwell typically includes an input terminal (V 1 ), pulse generator  2 , a high voltage PMOS transistor  4  and a power supply  3 . The pulse generator  2  typically generates a pulse of fixed length when triggered which controls the transistor  4 , for example, in  FIG. 1 . In  FIG. 1 , the drain of the transistor  4  includes a node designated V 3  and connects to a pull down resistor R on the lowside  10   b . The lowside  10   b  typically includes a resistor R, an amplifier  6 , a pulse filter  8  and a power supply  9 . The pulse filter  8  delays positive edges but feeds forward negative edges without significant delay. VDD and VCC are positive supply terminals, VSS is a negative supply terminal and COM is ground. The midwell&#39;s negative supply is elevated by Vsscom volts relative to COM. 
         [0035]    The prior art level shift up circuit  20  illustrated in  FIG. 2  includes a lowside  20   b  and a highside  20   a . The lowside  20   b  includes input terminal  21 , pulse generator  22 , high voltage NMOS level shift transistor  24  and power supply  23 . The drain of the transistor  24  is referred to as the level shift node and connects to a pull up resistor R 1  of the highside  20   a . The highside  20   a  includes the resistor R 1 , a comparator  26 , a pulse filter  28  and a power supply  29 . The pulse filter  28  is provided to reject any common mode or dv/dt related noise in the level shift channel, thus the pulsewidth from the lowside  20   b  must have a duration that is longer than the harmful dv/dt slew time. VB and VC are positive supply terminals and VS is a negative supply terminal while COM is ground, The highside negative supply VS is elevated by Vscon relative to ground. 
         [0036]      FIG. 7  illustrates typical waveforms during operation of a prior art level shift down circuit, such as that illustrated in  FIG. 1 . Activity at the input node (V 1 ) triggers the pulse generator  2  to generate a pulsed control waveform (on V 2 ) to the high voltage PMOS transistor  4 . When active, the transistor  4  pulls up the voltage at node V 3  (the level shift node). The pulse waveform is transferred via the comparator (amplifier  6 ) to the pulse filter  8 , and after a delay to the output node or terminal V 4 . 
         [0037]      FIG. 3  illustrates a level shift down circuit  10   1  with parasitic capacitance C 1  between VDD and V 3  and C 2  from VSS to V 3 . Otherwise, the circuit  101  is substantially similar to the circuit  10  of  FIG. 1 . These capacitances may be the result of a reverse-biased junction of the PMOS transistor  4 , for example. When the VSS potential changes compared to COM, a current is injected via these capacitors to node V 3 . The pulse filter  8  operates to block noise during the maximum assumed slew rate time and therefore the transmitted pulse width and pulse filter delay is long.  FIG. 8  shows the timing diagram of the prior art level shift down circuit where the time constant of the pulse filter  8  is incorrectly chosen to be shorter than the dv/dt event duration such that noise is provided at the level shift channel output node V 4 . 
         [0038]    A dv/dt event is defined as an event when switching ground potentials, such as VSS or VS switch relative to COM such that an error may result at the level shift output.  FIG. 4  illustrates an example of a dv/dt sensing circuit in accordance with an embodiment of the present application. The circuit  100  includes a parasitic capacitance emulator  102  in the midwell  10   a . The midwell  10   a  also include a power source  103 . The emulator  102  is connected to a lowside resistor R 2  which is preferably positioned in the lowside  10   b . The emulator  102  and the resistor R 2  are connected to the node V 5 , which also provides the detect signal. The emulator emulates the parasitic capacitances C 1 , C 2 , for example of  FIG. 3  to predict when noise will be introduced into the circuit. The detect signal provided from node V 5  activates at any positive offset shift and assumes amplitude, timing and duration similar to that of the noise in the level shift channel. The detect signal is used to control the blocking of the dv/dt related noise in the level shift channel.  FIG. 4A  illustrates an exemplary embodiment of the emulator  102 . In this embodiment, the emulator  102  is implemented as a diode connected high voltage PMOS transistor  114 . That is, the gate of the transistor  114  is tied to VDD. The amplitude of the detect signal at node V 5  may be adjusted by changing the value of the resistor R 2  and/or by increasing the emulated parasitic capacitance. 
         [0039]      FIG. 9  illustrates timing waveforms of the circuit of  FIG. 4 . When the VSS potential changes relative to COM, a current is injected into node V 5  leading to a voltage developing across resistor R 2 . The parasitic capacitance emulator  102  is connected to the pull down resistor R 2  in the lowside  102   b  such that any alteration in the ground offset (VSS-COM) between the midwell  102   a  and lowside causes a voltage across the resistor R 2 . 
         [0040]      FIG. 5  illustrates a level shift down circuit  200  in accordance with an embodiment of the present application that blocks level shift signaling whenever noise is predicted. The circuit preferably includes three disable blocks, or devices,  202   a ,  202   b ,  202   c  but otherwise includes components similar to the circuit of  FIG. 1 . The first disable block  202   a  prevents level shift signaling based on a control signal, preferably the detect signal from node V 5  mentioned above. The second disable block  202   b  prevents noise from entering the pulse filter  8 . That is, it is positioned at an input to the pulse filter  8  and prevent noise signals from being passed to the filter  8  based on the control signal. The third disable block  202   c  prevents noise at the pulse filter output from reaching the output terminal of the level shift circuit based on the detect signal. As is noted above, the disable blocks  202   a ,  202   b ,  202   c  are controlled by the detect signal (from node V 5 ). However, the disable blocks  202   a ,  202   b ,  202   c , are preferably only active when the detect signal is large enough to potentially cause an error at the output terminal of the level shift circuit. That is, when the floating ground changes relative to ground by a sufficient amount to introduce noise. While the blocks  202   a,    202 , b,    202   c  are all illustrated in  FIG. 5 , any one of the disable blocks may be used to prevent noise from propagating to the output terminal of the level shift circuit. That is, the circuit  200  need not include all of the disable blocks  202   a,    202   b,    202   c  to prevent noise from propagating to the output of the circuit. Any individual block or combination of the disable blocks may be used instead. While it is preferable to provide the disable block, or blocks, prior to the filter  8 , any desired configuration may be used. The disable blocks  202   a ,  202   b  and  202   c  may be implemented to block noise signals in any desired manner, including but not limited to logic units. 
         [0041]    The pulse filter  8  in  FIG. 5  prevents dv/dt induced noise from propagating to the output whenever there is a mismatch between the level shift channel noise and the blocking mechanism including dv/dt detect signal delay. Since the mismatch time is typically much shorter than the dv/dt event duration, the pulse filter time constant can be made much shorter compared to the prior art level shift circuits discussed above where the pulse filter time must be longer than the maximum dv/dt event duration. Shorter pulse filter time reduces propagation delay and allows for reduced pulse generator time, and thus reduces power consumption. Thus, using a shorter pulse filter delay also allows the duration of the level shift pulse width to be reduced such that shorter throughput delay and reduced power consumption is achieved. 
         [0042]      FIG. 6A  illustrates a level shift down circuit  300  in accordance with an embodiment of the present application that includes the dv/dt sensing provided by the circuit of  FIG. 4  and the noise blocking provided by the circuit of  FIG. 5 . The circuit of  FIG. 6A  is similar to that of  FIG. 3  except that it also includes the improvements provided by the circuits of  FIGS. 4 and 5 .  FIG. 10  illustrates a timing diagram for the circuit  300  of  FIG. 7 . The diagram of  FIG. 10  illustrates the input voltage (V 1 ) the HV PMOS transistor control voltage (V 2 ), the positive slew of vss-com offset voltage (VSS-COM), the dv/dt detect signal voltage (V 5 ), the level shift channel voltage (V 3 ), the buffered level shift voltage before and after the level shift channel voltage (V 6  and V 7 ), the pulse filter output voltage (V 13 ) and the level shift circuit output voltage (V 4 ). The waveforms on the left side of the diagram show successful blocking of noise during a dv/dt event by the disable block  202   a.  The waveforms in the center show successful blocking of noise during a dv/dt event by disable block  202   b . The waveforms on the right side of  FIG. 10  show successful blocking of noise during a dv/dt event by the disable block  202   c . However, as is noted above with respect to  FIG. 5 , it is not necessary to use all three disable blocks to block noise. 
         [0043]      FIG. 6B  illustrates a level shift up circuit  400  in accordance with an embodiment of the present application that includes the dv/dt sensing provided by the circuit of  FIG. 4  and the noise blocking provided by the circuit of  FIG. 5 . The circuit of  FIG. 6B  is similar to that of  FIG. 2  except that it includes the advantages offered by the circuits of  FIGS. 4 and 5 . The polarity of both of these circuits is reversed since the circuit  400  is a level shift up circuit and the circuits of  FIGS. 4 and 5  were discussed above relative to a level shift down circuit. Otherwise, their operation is very similar to that described above.  FIG. 11  illustrates a timing diagram of the circuit  FIG. 8 . The diagram of  FIG. 11  illustrates the input voltage (V 1 ) the HV NMOS transistor control voltage (V 8 ), the positive slew of vs-com offset voltage (VS-COM), the dv/dt detect signal voltage (V 10 ), the level shift channel voltage (V 9 ), the buffered level shift voltage before and after the disable block (V 11  and V 12 ), the pulse filter output voltage (V 14 ) and the level shift circuit output voltage (V 4 ). The waveforms on the left side of the diagram show successful blocking of noise during a dv/dt event by the disable block  202   a . The waveforms in the center show successful blocking of noise during a dv/dt event by disable block  202   b . The waveforms on the right side show successful blocking of noise during a dv/dt event by disable block  202   c . As is noted above, it is not necessary to use all three disable blocks to block noise from reaching the output. 
         [0044]    Thus, the level shift circuit of the present application provides improved dv/dt sensing which can be used to trigger noise blocking such that propagation delays can be minimized and power consumption reduced. 
         [0045]    Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.