Abstract:
A circuit board includes a substrate and a conductor layer disposed on the substrate. The conductor layer includes conducting wires and gapped electrostatic protected areas (EPAs) forming a reticulated pattern and electrically isolated from the conducting wires. The manner and method of construction of the circuit board reduces warping and bulging, to induce more reliable component connections. A method for manufacturing the circuit board is also provided.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure generally relates to circuit boards such as printed circuit boards (PCBs), and to methods of manufacturing circuit boards such as PCBs. 
         [0003]    2. Description of Related Art 
         [0004]    Circuit boards are used in electronic products as a connection medium connecting electronic components. In manufacturing, the electronic components are usually soldered to a circuit board in a reflow oven at a high temperature. However, warping and bulging may occur on a PCB when the PCB is processed in the reflow oven. The warping of a PCB may result in weak and unreliable electrical connections between the electronic components disposed on the PCB. Therefore, the quality and performance of an electronic component on the PCB may be compromised due to the warping and bulging. 
         [0005]    What is needed, therefore, is a circuit board which can overcome the described limitations, and a method of manufacturing such a circuit board. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views, and all the views are schematic. 
           [0007]      FIG. 1  is a cross-sectional view of part of a circuit board according to one embodiment, the circuit board including a conductor layer and an insulating layer disposed on the conductor layer. 
           [0008]      FIG. 2  is a plan view of the whole conductor layer partly shown in  FIG. 1 , according to one embodiment. 
           [0009]      FIG. 3  is an enlarged view of the circled part III of the conductor layer of  FIG. 2 . 
           [0010]      FIG. 4  is a plan view of the whole insulating layer partly shown in  FIG. 1 . 
           [0011]      FIG. 5  is similar to  FIG. 2 , but showing a whole conductor layer according to another embodiment. 
           [0012]      FIG. 6  is a flowchart of an exemplary method of manufacturing the circuit board of  FIG. 1 . 
           [0013]      FIGS. 7-9  are cross-sectional views showing some successive stages of the method of  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    Reference will be made to the drawings to describe certain exemplary embodiments in detail. 
         [0015]    Referring to  FIG. 1 , a cross-sectional view of part of a circuit board  1  according to one embodiment is shown. The circuit board  1  may be a PCB, and includes, from bottom to top, a substrate  15 , a conductor layer  13 , and an insulating layer  11 . The insulating layer  11  and the substrate  15  may be made of a resinous material. The conductor layer  13  may be made of a metallic material, preferably copper. 
         [0016]    In this embodiment, the conductor layer  13  is attached to the substrate  15  by means of an adhesive layer  17 . The adhesive layer  17  may be derived from a liquid adhesive applied during manufacturing of the circuit board  1 . In an alternative embodiment, the conductor layer  13  can be directly bonded to the substrate  15  without the adhesive layer  17 . In another alternative embodiment, the conductor layer  13  and the substrate  15  can be formed as one piece in one process by employing a double molding method. 
         [0017]    Referring also to  FIGS. 2 and 3 , the conductor layer  13  includes a plurality of conducting wires or traces (hereinafter, “conducting wires”)  132 , and a plurality of electrostatic protected areas (EPAs)  134  physically separated and electrically isolated from the plurality of conducting wires  132 . The conducting wires  132  are configured to connect electronic components and realize electronic interconnections between the electronic components. The EPAs  134  are connected to grounding terminals (not shown) of the circuit board  1  to achieve electrostatic protection. The conducting wires  132  and the EPAs  134  are made of the same metallic material, and are formed separately from each other via an etching process. For example, when the conductor layer  13  is made of copper and etched, this forms a plurality of copper wires (or traces) serving as the conducting wires  132 , and a plurality of copper foils (or patches) serving as the EPAs  134  and being separate from the copper wires. In particular, first portions of the conductor layer  13  between the copper wires and the copper foils are etched away, and second portions of the adhesive layer  17  corresponding to the first portions are also etched away. Thereby, a plurality of gaps  133  are formed in the conductor layer  13 , and prevent the copper wires and the copper foils from being electrically connected. Further, the gaps  133  also extend through the adhesive layer  17 . Therefore, parts of the insulating layer  11  can be directly exposed to the substrate  15  via the gaps  133 . 
         [0018]    Each EPA  134  includes a plurality of openings  137 , with each opening  137  being defined through a thickness of the EPA  134 . The openings  137  are arranged in a matrix. Preferably, each opening  137  is rectangular, with a size in the range from 1 mm×1 mm to 3 mm×3 mm. In the illustrated embodiment, each opening  137  is square. A distance separating each two adjacent openings  137  is approximately 1 mm. Further, the openings  137  also extend through the adhesive layer  17 . Therefore, parts of the insulating layer  11  can be directly exposed to the substrate  15  via the openings  137 . Preferably, the openings  137  do not divide the EPA  134  into separate independent portions. In this way, the interconnecting wires between the EPA  134  and the grounding terminals of the circuit board  1  are simplified. Referring to  FIG. 5 , in other embodiments, the shapes of openings  237  can be triangular, circular, elliptical, wave-like, diamond-shaped, or of other irregular shape; and such shaped openings  237  can be randomly arranged. 
         [0019]    Referring to  FIG. 4 , the insulating layer  11  includes a plurality of holes  110 , with each hole  110  being defined through a thickness of the insulating layer  11 . The holes  110  are configured to allow connections between the electronic components and the conducting wires  132  of the conductor layer  13 . Preferably, the holes  110  have metallic pads therein, such as copper pads. The metallic pads are electrically connected to certain of the conducting wires  132 , and have pins configured to allow the soldering of the electronic components to the conducting wires  132 . Therefore, the conducting wires  132  may be connected to the electronic components by means of the metallic pads in the holes  110 . 
         [0020]    Even under high temperature conditions, the gaps  133  and the openings  137  can provide spaces for any lateral expansion of the EPAs  134  when the conductor layer  13  is heated. Therefore, any warping and bulging in the EPAs  134  is lessened, and the surface of the circuit board  1  can thereby remain flat. Thus, the electronic connections between the electronic components disposed on the circuit board  1  and the conducting wires  132  are firmer and more reliable, and the quality of the circuit board  1  is improved. 
         [0021]    Referring to  FIG. 6 , a flowchart of an exemplary method of manufacturing the circuit board  1  is shown. The method includes the following steps. 
         [0022]    In step S 1 , referring to  FIG. 7 , a substrate  15  covered with a conducting layer  130  is provided. 
         [0023]    The conducting layer  130  can be attached to the substrate  15  by means of an adhesive layer  17 . In an alternative embodiment, the conducting layer  130  can be directly bonded to the substrate  15  without an adhesive layer  17 . In another alternative embodiment, the conducting layer  130  and the substrate  15  can be formed as one piece in one process by employing a double molding method. The conducting layer  130  is preferably made of copper. 
         [0024]    In step S 2 , a conductor layer  13  is formed by etching the conducting layer  130 . 
         [0025]    Referring to  FIG. 8 , a photo resist layer  100  is applied on the conducting layer  130 , and a mask  190  is employed to expose and develop the conducting layer  130 . The mask  190  includes a plurality of holes  199 . Holes (not labeled) are formed in the photo resist layer  100  as a result of the exposure and development of the photo resist layer  100 , with the holes being located corresponding to the holes  199 . Then the exposed portions of the conducting layer  130  beneath the holes are etched away, whereby the gaps  133  and the openings  137  of the conducting layer  130  are formed. Further, the exposed portions of the adhesive layer  17  below the conducting layer  130  are etched away, whereby the gaps  133  and the openings  137  also extend through the adhesive layer  17 . Referring to  FIG. 9 , the photo resist layer  100  is removed after the etching of the conducting layer  130  and the adhesive layer  17 . In an alternative embodiment, the parts of the adhesive layer  17  corresponding to the gaps  133  and the openings  137  can be removed by using other film-removing methods known in the art. Thereby, the conductor layer  13  having the gaps  133  between the conducting wires  132  and the EPAs  134 , and having the openings  137  in the EPAs  134 , is formed. 
         [0026]    In step S 3 , an insulating layer  11  is formed on the conductor layer  13 . 
         [0027]    In particular, holes  110  corresponding to the pins of the electronic components are first made in the insulating layer  11 , and then the insulating layer  11  having the holes  110  is disposed on the conductor layer  13 . 
         [0028]    The circuit board  1  as shown in  FIG. 1  is finally formed by being heated in a reflow oven, for example. When the circuit board  1  is placed in the reflow oven, the gaps  133  and the openings  137  can provide spaces for any lateral expansion of the EPAs  134  when the conductor layer  13  is heated. Therefore, any warping and bulging in the EPAs  134  is lessened, and the surface of the circuit board  1  can thereby remain flat. 
         [0029]    It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the embodiments or sacrificing all of their material advantages.