Abstract:
A method, system and apparatus for ensuring that only randomly generated numbers that have passed a test is used for cryptographic purposes are provided. When a random number is generated, it undergoes a built-in self-test (BIST). If the number passes the test, it is forwarded to a cryptographic device to be used for cryptographic purposes. If the number does not pass the test, a signal is instead forwarded to the cryptographic device to indicate the failure of the test. In a particular embodiment, only one data line is used to forward either the randomly generated number or the signal. A selector is used to facilitate the selection between the number and the signal.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Technical Field  
           [0002]    The present invention is directed to secure communications networks. More specifically, the present invention is directed to a method, system and apparatus for ascertaining that only randomly generated numbers that have passed a test are used in encrypting and decrypting data.  
           [0003]    2. Description of Related Art  
           [0004]    The Internet is being used more and more to transact sensitive information. Sensitive information includes proprietary documents, credit card information, financial data or any data or information that a user may not want the public at large to obtain. The Internet, however, is an open network environment and thus requires a high level of security to ensure that sensitive information remains private. To provide the requisite security, encryption is used.  
           [0005]    When data is encrypted, the data is ciphered. To decipher the data, a secret key or password is used. Specifically, when two computer systems have to transfer sensitive information to each other over the Internet, they do so by opening a Secure Socket Layer (SSL) connection. SSL is a security protocol that uses a public key to encrypt data and a private key to decrypt the encrypted data. The public key can be obtained from the computer systems themselves while the private key is kept secret. For example, when a client system needs to establish a secure connection with a server (or with any other computer system for that matter), it contacts the server to indicate so. The server then generates a public key/private key pair and passes the public key to the client. Using the public key, the client encrypts the sensitive data that is to be transferred to the server. Only the server has the corresponding private key to decrypt the encrypted data.  
           [0006]    The client may also generate its own public key/private key pair and pass the public key to the server. The server will then encrypt all sensitive information that is to be transferred to the client using the client&#39;s public key. As in the case of the server, only the client has the private key with which the encrypted data may be decrypted.  
           [0007]    As is well known in the field, to generate public key/private key pairs, random number generators (RNGs) are used. However, computer systems are deterministic devices. That is, for every input there is a particular output and thus, true random number generators (TRNGs) are difficult to implement. Consequently, pseudo-random number generators (PRNGs) are mostly used. A PRNG uses a seed (a random stream of bits that is used to generate a usually longer stream of bits) to produce numbers that have a random distribution of bits. Hence, the seeds used to generate the numbers have to themselves be random in order for the generated numbers to be random.  
           [0008]    In any event, because security protocols, such as SSL, rely on the unpredictable nature of the keys they use, RNGs must meet stringent requirements. One of those requirements is that users who are bent on breaking encryption code (i.e., attackers, as known in the field), including those who know the RNG design, must not be able to make any useful predictions about the generated numbers. Thus, to ensure that is indeed so, each number generated by an RNG is tested for its relative unpredictability. If the number passes the test, it is used; otherwise, it is discarded. Most RNGs use an integrated hardware device known as a built-in self-test or BIST to perform the test.  
           [0009]    Presently, RNG cores that contain an RNG and a BIST hardware are being manufactured and sold. The RNG cores have two outputs, a test status line to provide the status of the test and a data line to provide the generated number. To implement a cryptographic module, both the test status line and the data line have to be connected to a cryptographic device (i.e., the device performing the cryptographic functions).  
           [0010]    Using a test status line to provide the result of the test and a data lien to provide the data to the cryptographic device may not be an ideal configuration. For example, suppose the BIST outputs a logical one (1) to indicate that a number has passed the test and a logical zero (0) to indicate that it has failed the test. Suppose further that due to a mechanical, electrical or any other problem including an attacker-induced problem, the test result always comes out as a one (1). If a generated number did not pass the test, the cryptographic device will nonetheless use the number. Hence, if the seeds used are a recurring sequence of numbers, an attacker may be able to predict the corresponding generated numbers and thus the cryptographic keys based on previously observed recurring sequences of numbers.  
           [0011]    Alternatively, if due to any of the problems mentioned above, the RNG core constantly outputs a particular number or a sequence of numbers. Further, if the numbers that have actually passed the test are different from the numbers transferred. Then, the cryptographic device will use the transferred numbers. Thus, an attacker may be able to predict the numbers based on previously observed recurring numbers or sequences of numbers.  
           [0012]    Thus, what is needed is a method, system and apparatus for ensuring that only generated random numbers that have truly passed a BIST are used for encryption purposes.  
         SUMMARY OF THE INVENTION  
         [0013]    The present invention provides a method, system and apparatus for ensuring that only randomly generated numbers that have passed a test is used for cryptographic purposes. When a random number is generated, it undergoes a built-in self-test (BIST). If the number passes the test, it is forwarded to a cryptographic device to be used for cryptographic purposes. If the number does not pass the test, a signal is instead forwarded to the cryptographic device to indicate that the number does not pass the test. In a particular embodiment, only one connection line is used to forward either the randomly generated number or the signal. A selector is used to select between the number and the signal.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0015]    [0015]FIG. 1 is an exemplary block diagram illustrating a distributed data processing system according to the present invention.  
         [0016]    [0016]FIG. 2 is an exemplary block diagram of a server apparatus according to the present invention.  
         [0017]    [0017]FIG. 3 is an exemplary block diagram of a client apparatus according to the present invention.  
         [0018]    [0018]FIG. 4 is a prior art cryptographic core.  
         [0019]    [0019]FIG. 5 is a particular embodiment of a cryptographic core of the present invention.  
         [0020]    [0020]FIG. 6 is a detailed implementation of FIG. 5.  
         [0021]    [0021]FIG. 7 is a truth table of a cryptographic module used in the present invention.  
         [0022]    [0022]FIG. 8 is a portion of a timing diagram of the truyh table in FIG. 7.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0023]    With reference now to the figures, FIG. 1 depicts a pictorial representation of a network of data processing systems in which the present invention may be implemented. Network data processing system  100  is a network of computers in which the present invention may be implemented. Network data processing system  100  contains a network  102 , which is the medium used to provide communications links between various devices and computers connected together within network data processing system  100 . Network  102  may include connections, such as wire, wireless communication links, or fiber optic cables.  
         [0024]    In the depicted example, server  104  is connected to network  102  along with storage unit  106 . In addition, clients  108 ,  110 , and  112  are connected to network  102 . These clients  108 ,  110 , and  112  may be, for example, personal computers or network computers. In the depicted example, server  104  provides data, such as boot files, operating system images, and applications to clients  108 ,  110  and  112 . Clients  108 ,  110  and  112  are clients to server  104 . Network data processing system  100  may include additional servers, clients, and other devices not shown. In the depicted example, network data processing system  100  is the Internet with network  102  representing a worldwide collection of networks and gateways that use the TCP/IP suite of protocols to communicate with one another. At the heart of the Internet is a backbone of high-speed data communication lines between major nodes or host computers, consisting of thousands of commercial, government, educational and other computer systems that route data and messages. Of course, network data processing system  100  also may be implemented as a number of different types of networks, such as for example, an intranet, a local area network (LAN), or a wide area network (WAN). FIG. 1 is intended as an example, and not as an architectural limitation for the present invention.  
         [0025]    Referring to FIG. 2, a block diagram of a data processing system that may be implemented as a server, such as server  104  in FIG. 1, is depicted in accordance with a preferred embodiment of the present invention. Data processing system  200  may be a symmetric multiprocessor (SMP) system including a plurality of processors  202  and  204  connected to system bus  206 . Alternatively, a single processor system may be employed. Also connected to system bus  206  is memory controller/cache  208 , which provides an interface to local memory  209 . I/O bus bridge  210  is connected to system bus  206  and provides an interface to I/O bus  212 . Memory controller/cache  208  and I/O bus bridge  210  may be integrated as depicted.  
         [0026]    Peripheral component interconnect (PCI) bus bridge  214  connected to I/O bus  212  provides an interface to PCI local bus  216 . A number of modems may be connected to PCI local bus  216 . Typical PCI bus implementations will support four PCI expansion slots or add-in connectors. Communications links to network computers  108 ,  110  and  112  in FIG. 1 may be provided through modem  218  and network adapter  220  connected to PCI local bus  216  through add-in boards. Additional PCI bus bridges  222  and  224  provide interfaces for additional PCI local buses  226  and  228 , from which additional modems or network adapters may be supported. In this manner, data processing system  200  allows connections to multiple network computers. A memory-mapped graphics adapter  230  and: hard disk  232  may also be connected to I/O bus  212  as depicted, either directly or indirectly.  
         [0027]    Those of ordinary skill in the art will appreciate that the hardware depicted in FIG. 2 may vary. For example, other peripheral devices, such as optical disk drives and the like, also may be used in addition to or in place of the hardware depicted. The depicted example is not meant to imply architectural limitations with respect to the present invention.  
         [0028]    The data processing system depicted in FIG. 2 may be, for example, an IBM e-Server pSeries system, a product of International Business Machines Corporation in Armonk, New York, running the Advanced Interactive Executive (AIX) operating system or LINUX operating system.  
         [0029]    With reference now to FIG. 3, a block diagram illustrating a data processing system is depicted in which the present invention may be implemented. Data processing system  300  is an example of a client computer. Data processing system  300  employs a peripheral component interconnect (PCI) local bus architecture. Although the depicted example employs a PCI bus, other bus architectures such as Accelerated Graphics Port (AGP) and Industry Standard Architecture (ISA) may be used. Processor  302  and main memory  304  are connected to PCI local bus  306  through PCI bridge  308 . PCI bridge  308  also may include an integrated memory controller and cache memory for processor  302 . Additional connections to PCI local bus  306  may be made through direct component interconnection or through add-in boards. In the depicted example, local area network (LAN) adapter  310 , SCSI host bus adapter  312 , and expansion bus interface  314  are connected to PCI local bus  306  by direct component connection. In contrast, audio adapter  316 , graphics adapter  318 , and audio/video adapter  319  are connected to PCI local bus  306  by add-in boards inserted into expansion slots. Expansion bus interface  314  provides a connection for a keyboard and mouse adapter  320 , modem  322 , and additional memory  324 . Small computer system interface (SCSI) host bus adapter  312  provides a connection for hard disk drive  326 , tape drive  328 , and CD-ROM drive  330 . Typical PCI local bus implementations will support three or four PCI expansion slots or add-in connectors.  
         [0030]    An operating system runs on processor  302  and is used to coordinate and provide control of various components within data processing system  300  in FIG. 3. The operating system may be a commercially available operating system, such as Windows  2000 , which is available from Microsoft Corporation. An object oriented programming system such as Java may run in conjunction with the operating system and provide calls to the operating system from Java programs or applications executing on data processing system  300 . “Java” is a trademark of Sun Microsystems, Inc. Instructions for the operating system, the object-oriented operating system, and applications or programs are located on storage devices, such as hard disk drive  326 , and may be loaded into main memory  304  for execution by processor  302 .  
         [0031]    Those of ordinary skill in the art will appreciate that the hardware in FIG. 3 may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash ROM (or equivalent nonvolatile memory) or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in FIG. 3. Also, the processes of the present invention may be applied to a multiprocessor data processing system.  
         [0032]    As another example, data processing system  300  may be a stand-alone system configured to be bootable without relying on some type of network communication interface, whether or not data processing system  300  comprises some type of network communication interface. As a further example, data processing system  300  may be a Personal Digital Assistant (PDA) device, which is configured with ROM and/or flash ROM in order to provide non-volatile memory for storing operating system files and/or user-generated data.  
         [0033]    The depicted example in FIG. 3 and above-described examples are not meant to imply architectural limitations. For example, data processing system  300  may also be a notebook computer or hand held computer in addition to taking the form of a PDA. Data processing system  300  also may be a kiosk or a Web appliance.  
         [0034]    The present invention may be implemented in a hardware security module (HSM). An HSM is a tamper-resistant adapter or a piece of hardware that provides secure key generation, secure key storage and secure key archival. If an HSM is ever tampered with, all information is zeroed out. A co-processor inside the HSMs handles the generation of public key/private key pairs, encryption as well as decryption of sensitive information. Thus, the invention may reside in network adapter  220  of FIG. 2 and LAN adapter  310  of FIG. 3 provided that they are HSMs. Alternatively, the invention may reside anywhere in the computer systems illustrated in FIGS. 2 and 3 so long as sensitive data is encrypted before entering network  102  of FIG. 1 and decrypted once received from the network.  
         [0035]    [0035]FIG. 4 is a prior art cryptographic module  400 . The cryptographic module  400  contains a random number generator (RNG) core  405  and a cryptographic device  440 . The RNG core  405  includes an RNG  410  and a BIST  420 . The RNG  410  uses a storage device (not shown) to store collected random bits (i.e., the seed). Depending on the implementation of the RNG  410 , the random bits may be collected from a user&#39;s keystrokes, mouse movements, Johnson noise, the radioactive decay of an object or any source that provides random bits or a combination thereof. When the cryptographic device  440  is in need of a random number, it makes a request or a call to the RNG core  405 . At that point, the BIST  420  performs a random test on n bits (i.e., the number).  
         [0036]    The number of bits (i.e., n) is dependent upon the processor used to implement the cryptographic device. If a 16-bit or a 32-bit processor is used then n=16 or 32, respectively. Most modern cryptographic devices use at least 128-bit numbers or data and at least a 16-bit processor to perform cryptographic functions. Thus, if a 128-bit data is used for performing the cryptographic functions, a 16-bit processor will have to make eight (8) calls to the RNG core  405  to obtain the 128-bit data.  
         [0037]    The test must be administered on m bits, where m&gt;15. But, in cases where a less than 16-bit processor is used (e.g., an 8-bit processor), n bits are generated at a time, where n&lt;15. Consequently, at least two generated numbers have to be combined together to obtain the requisite m bits. However, since as mentioned above, at least 16-bit processors are used in cryptography, then at least 16-bit numbers are generated at a time, where n&gt;16. Thus, it will henceforth be assumed that the test is performed on each single n-bit number generated, where n=m&gt;15.  
         [0038]    The BIST  420  passes both the generated number and the result of the test to the cryptographic device  440  using data line  425  and test status line  430 , respectively. As mentioned earlier there may be instances when a number that has not been tested or that was tested, but failed the test, is nonetheless used. The present invention ensures that only generated numbers that have truly passed the BIST are used.  
         [0039]    [0039]FIG. 5 is a particular embodiment of a cryptographic module  500  of the present invention. The cryptographic module  500  contains an RNG core  505  and a cryptographic device  540 . Just as before, the RNG core  505  includes an RNG  510  that collects and stores random bits in a storage device (not shown). When the cryptographic device  540  is in need of a random number, n bits (or a number), where n≧16 are tested for their randomness. However, only one transmission line (i.e., transmission line  530 ) is used to transfer either the result of the test or the generated number to the cryptographic device  540 . For example, when the test has failed, a signal indicating that the test has failed is passed to the cryptographic device  540 . If the test has passed, the generated n-bit number is instead transferred. Note that although one line is shown to represent transmission line  530 , transmission line  530  may be a plurality of lines to enable parallel transfer of the bits that make up the number to the cryptographic device  540 .  
         [0040]    [0040]FIG. 6 is a detailed implementation of FIG. 5. In FIG. 6, cryptographic module  600  is shown containing an RNG core  605  and a cryptographic core  610 . The RNG core  605  includes an RNG  615  that collects and stores random bits in a storage device (not shown). Again, when the cryptographic device wants a random number, it places a call to the RNG core  605 . Upon receiving the call, n-bit random bits (where n&gt;16) are tested by BIST  620  for randomness. The BIST  620  includes a statistical test hardware  625  and a continuous test hardware  630 . The statistical test hardware  625  performs a statistical test on each 20,000 bits collected and the continuous test hardware  630  performs a continuous test on each generated n-bit number.  
         [0041]    Both tests are well delineated in Chapter 4.9 entitled Self-Tests of the Federal Information Processing Standards Publication 140-2 (or FIPS PUB 140-2); thus, they will not be further explained in this disclosure. FIPS PUB 140-2 is a United States Department of Commerce publication that contains security requirements for cryptographic modules. It may be found at http://csrc.nist.gov/publications/fips/fips140-2/fips1402.pdf. Nonetheless as a reference, a current copy is provided in an Information Disclosure Statement filed concurrently with the present application. The publication is hereby incorporated by reference.  
         [0042]    The result of the statistical test and continuous test may each be used as inputs to a two-input AND gate  645 . The output of the AND gate  645  may be used to drive a selector  640 . In addition to the output of the AND gate  645 , the selector  640  has two more inputs and one output. The additional inputs are the output of RNG  610  and the output of a device  635  that generates n-bit blocks of “9119”, where n=the number of bits in a generated number. According to this particular implementation of the invention, when the BIST is passed, the selector  640  outputs the randomly generated number. When any one of the two tests or both tests are not passed, the RNG core  605  is in an error state and outputs a string of n-bit blocks of “9119” as a signal to indicate that the BIST has failed. In this embodiment, three n-bit blocks of “9119” are used to make up the string, although two may suffice.  
         [0043]    Note that in this embodiment an AND gate is used to drive the selector  640 . However, any combinational logic gate or equivalent device may be used so long as the output of the logical gate or the device drives the selector  640  to choose the randomly generated number if both tests are passed or the n-bit blocks of “9119” if any one or both tests are not passed. Consequently the present invention is not restricted to the use of an AND gate.  
         [0044]    The output of the selector  640  is fed into comparator  670 . The comparator  670  has two n-bit shift registers, registers  655  and  660 , where n=the number of bits in a generated number. The data or the numbers in the two shift registers are compared to determine whether or not they are different from each other. If they are different from each other, a logical zero (0) or low bit is outputted. Otherwise, a logical one (1) or high bit is outputted. The output of the comparator  670  goes into a latch  675  and to one of two inputs of an OR gate or equivalent device  680 .  
         [0045]    The latch  675  is used as a delaying mechanism. Any bit that goes into the latch is delayed by one processing step. The output of the latch is used as the other input of the OR gate  680 . The output of the OR gate is used to drive the cryptographic device  690 . For example, a low bit from the OR gate  680  enables the cryptographic device  690  to use the number in shift register  660  whereas a high bit inhibits the cryptographic device from using the number.  
         [0046]    [0046]FIG. 7 is a truth table of the cryptographic core  610 . For a better understanding, FIG. 7 should be viewed in conjunction with FIG. 6. In any event, N 1 , where i=1, 2, 3, . . . , represents the random numbers in the order they are generated and “?” is an undetermined value. Undetermined values are discarded. The output of the comparator, latch and OR gate is indicated as zero (0) denoting a low bit and one (1) a high bit. As mentioned before, when two random numbers or a random number and a “9119” number are each in the shift registers  655  and  660 , the comparator outputs a low bit (assuming that the numbers are different from each other). When both registers contain each the same number, as in the case when a string of “9119s” is transferred to the cryptographic core  610 , the comparator outputs a high bit.  
         [0047]    In Chapter 4.9 of FIPS PUB 140-2, it is specifically stated that a first number should be generated upon powering the system up. This first number should only be used for testing purposes and not for cryptographic purposes. The truth table includes this first number (i.e., N 1 ) generated from a power-up state and therefore is not used (see step 2). Note that if previous numbers had been generated or used before, then N 1 , will not be present in the table and nor will any undetermined value be present.  
         [0048]    In any case, at step 3, both registers contain a different random number (i.e., N 2  and N 3 ). Consequently, N 2  is used as the output of the OR gate is low. When the first “9119” number is in register  655 , shift register  660  will contain a random number. Again, assuming that the random number and the “9119” are different from each other, the comparator will output a low bit. The latch will also output a low bit, since the previous output of the comparator was a low bit. Hence, the output of the OR gate  680  will be low, indicating that the number in register  660  is to be used (step 5). At step 6, both registers will contain a “9119” number; hence, the output of the comparator will be high. This, in turn, will have the OR gate output a high bit and the number in shift register  660  will be discarded. The cryptographic device  690  will resume using numbers from the shift register  660  at step 9.  
         [0049]    [0049]FIG. 8 is a portion of a timing diagram of the cryptographic module  610  as depicted in the truth table of FIG. 7. There, it is shown that whenever the shift register  660  (i.e., right shifter as used in the figure) contains a “9119” number, the output of the OR gate is high inhibiting the cryptographic device  690  from using the number.  
         [0050]    The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. For example, any method of signaling the cryptographic device to stop cryptographic functions may be used instead of the n-bit blocks of “9119”. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.