Abstract:
The phase-frequency detector (PFD) includes a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between a reference signal and a feedback signal; a FD voltage-to-current converter arranged to convert the frequency error into a first current; a phase detector (PD) arranged to receive the orthogonal signal pairs and estimate a phase error between the reference signal and the feedback signal, and a PD voltage-to-current converter arranged to convert the phase error into a second current.

Description:
CROSS REFERENCE 
     This application is a Continuation of application Ser. No. 12/145,247, filed Jun. 24, 2008, which claims the benefit of U.S. provisional application Ser. No. 60/952,609 filed Jul. 30, 2007, the subject matter of which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates in general to electronic circuits, and in particular, to electronic circuits of phase locked loops (PLL), voltage controlled oscillators (VCO), and phase-frequency detectors (PFD). 
     2. Description of the Related Art 
     As device size scales down, CMOS devices are achieving higher operating speeds. The low power consumption and high circuit integration of miniaturized devices, along with the improvement of broadband techniques, make CMOS technology attractive in realizing ultra-fast phase locked loop (PLL) circuits. 
       FIG. 1  is a block diagram of a conventional PLL, comprising phase-frequency detector  10 , charge pump circuit  12 , voltage controlled oscillator (VCO)  14 , and divider  16 . Phase-frequency detector  10  is coupled to charge pump circuit  12 , voltage controlled oscillator (VCO)  14 , and divider  16 , and back to phase-frequency detector  10  in a loop. 
     Phase-frequency detector  10  compares reference signal CK in  with a feedback signal to determine a phase and frequency error therebetween to charge or discharge charge pump circuit  12 . The accumulated charges in charge pump circuit  12  produce a control voltage to VCO  14  to generate clock signal CK out . Divider  16  receives clock signal CK out  to perform a frequency division thereon to generate the feedback signal to phase-frequency detector  10  for phase and frequency error detection. 
     A number of considerations are taken into account for a PLL system, for example, parasitic capacitance in the PLL circuit may cause frequency shift of signals in the VCO or frequency divider to prevent the PLL from locking. Spurs in the reference signal also present an issue for conventional charge pump PLLs, where pulse-width comparison is performed in the phase detector, leading to interference problems to adjacent transmission channels. The reference clock feedthrough for conventional charge pump PLLs has always been an issue, wherein attempts have been made to minimize the reference spurs by: a charge transfer technique to spread out the momentary signal surge over a period; an analog phase detector using current-mode logic to reduce swing; a compensated charge-pump design to balance the device mismatch; and a distributed phase detector to avoid abrupt changes on the control voltage. However, none of the approaches eliminates pulse generation, so the control line ripple is never entirely removed. 
     Thus, a need exists for phase locked loop, voltage controlled oscillators (VCO), and phase-frequency detectors (PFD) to provide a high-speed and low-noise clock signal. 
     BRIEF SUMMARY OF THE INVENTION 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     A phase locked loop is provided, comprising a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF, coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. The PFD comprises a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between a reference signal and a feedback signal; a FD voltage-to-current converter arranged to convert the frequency error into a first current; a phase detector (PD) arranged to receive the orthogonal signal pairs and estimate a phase error between the reference signal and the feedback signal, and a PD voltage-to-current converter arranged to convert the phase error into a second current. 
     According to another embodiment of the invention, a phase-frequency detector is provided, comprising a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between the reference signal and the feedback signal; a FD voltage-to-current converter arranged to convert the frequency error into a first current; a phase detector (PD) arranged to receive orthogonal signal pairs and estimate a phase error between the reference signal and the feedback signal, and a PD voltage-to-current converter arranged to convert the phase error into a second current. 
     According to another embodiment of the invention, a phase-frequency detector is provided, comprising a first SSB mixer arranged to receive a reference signal and a feedback signal and output a first SSB output to serve as a phase error between the reference signal and the feedback signal; a second SSB mixer arranged to receive the reference signal and the feedback signal and output a second SSB output; and a flip-flop arranged to latch the first SSB output according to the second SSB output to generate a frequency error between the reference signal and the feedback signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a block diagram of a conventional Phase-Locked Loop (PLL). 
         FIG. 2  is a block diagram of an exemplary Phase-Locked Loop (PLL) according to the invention. 
         FIG. 3   a  shows the relationship of frequency divisions and the required locking range for each division. 
         FIG. 3   b  shows the relationship of operating ranges with respect to input frequency f o  for different types of frequency dividers. 
         FIG. 4   a  is a circuit schematic of an exemplary Voltage controlled oscillator (VCO) according to the invention, incorporated in  FIG. 2 . 
         FIG. 4   b  shows the relationship of Vctrl and the output frequency of VCO output signal CK OUT , incorporating the VCO in  FIG. 4   a.    
         FIG. 5   a  is a circuit schematic of another exemplary VCO according to the invention. 
         FIG. 5   b  shows the relationship of control voltage V etrl  and the output frequency of VCO output signal CK OUT , incorporating the VCO in  FIG. 5   a.    
         FIG. 6  shows a layout arrangement of a ground shield for the inductor in the VCO in  FIG. 5   a.    
         FIG. 7   a  is a circuit schematic of still another exemplary VCO according to the invention. 
         FIGS. 7   b  and  7   c  show the relationship of supply voltage VDD and drain currents I SS  and I C , and the oscillation frequency of the VCO in  FIG. 7   a.    
         FIG. 8  is a circuit schematic of yet another exemplary VCO according to the invention. 
         FIG. 9  is a block diagram of an exemplary phase and frequency detector (PFD) according to the invention. 
         FIG. 10   a  is a block diagram of an exemplary phase detector in  FIG. 9 . 
         FIG. 10   b  depicts the relationship of phase detector voltage VPD and error θ, incorporating the phase detector in  FIG. 10   a.    
         FIG. 10   c  is a circuit schematic of an exemplary phase detector in  FIG. 10   a.    
         FIG. 11  is a block diagram of an exemplary frequency detector in  FIG. 9 . 
         FIG. 12   a  is a circuit schematic of an exemplary hysteretic buffer in  FIG. 9 . 
         FIG. 12   b  shows the relationship of input voltage V in  and output voltage V out  for the phase detector in  FIG. 10   a.    
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 2  is a block diagram of an exemplary Phase-Locked Loop (PLL) according to the invention, comprising divide-by-2 divider  20 , phase-frequency detector (PFD)  22 , loop filter  24 , voltage controlled oscillator (VCO)  26 , and 3-stage frequency divider  28 . Divide-by-2 divider  20  is coupled to phase-frequency detector  22 . Phase-frequency detector  22 , loop filter  24 , voltage controlled oscillator  26 , and 3-stage frequency divider  28  are coupled in a loop. 
     PLL  2  is implemented to produce a clock signal with low jitter and wide operating range. Divide-by-2 divider  20  provides quadrature reference inputs CK ref,i , CK ref,q . Phase-frequency detector  22  receives reference signals CK ref,i , CK ref,q  and feedback signals CK div,i , CK div,q  to determine phase and frequency errors. Loop filter  24  then filters the phase and frequency errors to generate control voltage V ctrl . Voltage controlled oscillator  26  generates VCO output signal CK out  according to the control voltage V ctrl . And 3-stage frequency divider  28  divides the frequency of VCO output signal CK out  3 times to generate feedback signals CK div,i , CK div,q . 
     Phase-frequency detector  22  comprises phase detector (PD)  220 , frequency detector (FD), PD voltage-to-current converter  224 , and FD voltage-to-current converter  226 . Phase-frequency detector  22  may be implemented with the conventional charge pump circuit configuration, or SSB (single sideband) mixers and low-pass filters to suppress the reference feedthrough. Frequency detector  222  and FD voltage-to-current converter  226  estimates the frequency error between reference signals CK ref,i , CK ref,q  and feedback signals CK div,i , CK div,q , and converts the frequency error signal to a current. Note that both are turned off upon frequency lock to reduce the disturbance to the VCO. Phase detector  220  and PD voltage-to-current converter  224  estimates the phase error between reference signals CK ref,i , CK ref,q  and feedback signals CK div,i , CK div,q , and converts the phase error to a current, running continuously throughout the PLL operation. Frequency detector  222  and FD voltage-to-current converter  226  perform dominant coarse adjustment on control voltage Vctrl, while phase detector  220  and PD voltage-to-current converter  224  provides fine adjustment thereon. 
     Loop filter  24  comprises resistors R 240  through  8242 , and capacitors C 240  through C 244 . Loop filter  24  is realized on an integrated circuit to minimize the noise coupling through bonding wires. 9-layer interconnect metals in 90-nm process may be utilized for provision of high density fringe capacitors, reducing circuit size of loop filter  24  to 100×300 μm 2 . 
     3-stage frequency divider  28  comprises injection locked divider  280 , Miller divider  282 , and static divider  284 . Injection locked divider  280  is coupled to Miller divider  282 , and then to static divider  284 . 3-stage frequency divider  28  performs three frequency divisions on VCO output signal CK OUT  to derive feedback signals CK div,i , CK div,q . To accommodate the tradeoffs between the input frequency and operating range, several divider types are employed in 3-stage frequency divider  28 . Generally speaking, the injection-locked dividers provide the highest operating frequency due to the simple structure, but also the narrowest locking range. Static dividers, on the other hand, reveal a relatively wide range of operation, but only at low frequencies. Miller dividers, also known as regenerative dividers, provide a compromise between the injection-locked and Miller frequency dividers, generating an output signal with median locking range with moderate center frequency. As a result, 24 cascades the three types of frequency dividers in descending order of operating frequencies, i.e., the injection-locked, Miller, and then static dividers, to provide a low operating frequency and wide locking range for the feedback signal. 
     Now refer to  FIG. 3   a , showing the relationship of frequency divisions and the required locking range for each division. Each divider has an operating range as wide as the VCO tuning range, and division is perform on the locking range centered at VCO output frequency f o . The normalized locking range increases with the degree of frequency division, consequently a divide-by-8 frequency division requires at least 8 times locking range than that of a VCO output signal CK OUT . Further, typically twice of the locking range requirement is provided for taking the effects of PVT (process, voltage, temperature) variation and routing parasitic loading into the design consideration, wherein both can lead to considerable frequency shift in VCO output signal CK OUT . For example, a 20 μm routing path of metal corresponds to 1-2-fF parasitic capacitance, causing the center frequency of the first division stage deviating 300-500 MHz from the target locking range. 
       FIG. 3   b  shows the relationship of operating ranges with respect to input frequency f o  for different types of frequency dividers. Injection locked dividers, Miler dividers, and static dividers are capable of providing 5%, 25%, and 150% of the input frequency f o  for each operating range. In other words, Miller and static frequency dividers offer more flexible operating ranges than Injection locked dividers, thus 3-stage frequency divider  28  utilizes them at the last two division stage. Injection locked divider  280 , Miller divider  282 , and static divider  284  are implemented by current mode logic (CML) to provide reduced power consumption. 3-stage frequency divider  28  may further include a class-AB static CML frequency divider (not shown in  FIG. 1 ) between Miller divider  282  and static divider  284  to speed up the frequency division operation by removing the tail currents and using the gate control for switching. 
       FIG. 4   a  is a circuit schematic of an exemplary Voltage controlled oscillator (VCO) according to the invention, incorporated in  FIG. 2 , comprising current source  140 , transmission line pair L 40 , cross-coupled transistor pair M 40 , and transistors M 42  and M 44 . Current source  140  is coupled to transmission line pair L 40 , cross-coupled transistor pair M 40 , and subsequently to transistors M 42  and M 44 . 
     Transmission line pair L 40  is modeled as a short-circuited quarter-wavelength (λ/4) resonator, regardless of whether the oscillating “tube” is indeed a transmission line. The VCO oscillates at a frequency such that the wavelength thereof is 4 times that of the equivalent length L of the transmission line, leaving ends A and A′ coupled to cross-coupled transistor pair M 40  with maximum swings. Transistor M 42  serves as a varactor, varying the capacitance and VCO output frequency f o  of VCO output signal CK OUT  by Vctrl. Transistor M 44  is a buffer providing VCO output signal CK OUT  to external circuits and the feedback path. The device dimensions (width/length) for transistor pair M 40 , transistors M 42  and M 44  in  FIG. 4(   a ) are 8/0.1, 2/0.1, and 6/0.1, respectively. As resonance frequency f o  increases, the loading of varactor M 42 , buffer M 44 , and dividers (not shown) becomes comparable to that of the cross-coupled pair, limiting maximal frequency of VCO output frequency f o .  FIG. 4   b  shows the relationship of Vctrl and the output frequency of VCO output signal CK OUT , incorporating the VCO in  FIG. 4   a . With the device dimensions provided for the transistors, the maximal output frequency of the VCO circuit is only approximately 46 GHz. The device sizes provided herein are at minimal dimensions, as further miniaturization may cause significant swing degradation. 
       FIG. 5   a  is a circuit schematic of another exemplary VCO according to the invention, comprising current source  140 , transmission line pair L 50 , cross-coupled transistor pair M 40 , and transistors M 42  and M 44 . Current source  140  is coupled to transmission line pair L 50 , cross-coupled transistor pair M 40 , and subsequently to transistors M 42  and M 44 . 
     To counter the loading problem and increase the VCO output frequency for the VCO in  FIG. 4   a , a transmission line with an equivalent length of three-quarter wavelength of the VCO output is introduced, distributing the loading and increase the VCO output frequency. Transmission line pair L 50  has equivalent length 3L, each is short-circuited at one end and open-circuited at the other end, and provides VCO output signal CK OUT  with an initial VCO wavelength, such that equivalent length 3L of the transmission line pair is three quarter of the initial VCO wavelength. Cross-coupled transistor pair M 40  is coupled to one third of length 3L from the short circuited end. And varactor M 42  is coupled to the open-circuited ends of transmission line pair L 50 , adjusts the initial VCO wavelength of the VCO output signal according to control voltage Vctrl to output VCO wavelength. 
     Cross-coupled transistor pair M 40  provides negative resistance to compensate energy loss in the resonator L 50 . Cross-coupled transistor pair M 40  drives transmission line L 50  to produce peak swings at nodes A and A′. The differential signals at nodes A and A′ propagate along transmission line pair L 50 , and reflect at the open-circuited ends to form peak swings at nodes B and B′. The waveforms at nodes A and B (or A′ and B′) are 180° out of phase. The loading of varactor M 42 , buffer M 44 , and dividers (not shown) are removed from nodes A and A′, so that the VCO output frequency is driven up to around 75 GHz using the same device dimensions as for the VCO in  FIG. 4   a , increasing the VCO output frequency without extra power dissipation.  FIG. 5   b  shows the relationship of control voltage V ctrl  and the output frequency of VCO output signal CK OUT , incorporating the VCO in  FIG. 5   a . The VCO output frequency increases from 74 to 74.5 GHz as control voltage Vctrl increases from 0 to 1.5V. 
     Although varactor M 42  is connected to nodes B and B′, cross-coupled pair M 40  is still be able to observe the loading variation at the far ends through the 2 L length of the transmission lines. Since the resonance frequency (VCO initial frequency) is determined by the inductance of the first one-third transmission line segment and equivalent capacitance associated with nodes A and A′, the tuning of the VCO results in approximately linear increasing, similar to that of a conventional LC tank VCO. A stand-alone VCO with identical circuit implementation disclosed herein is developed for verification. From the measurement taken from the stand-alone VCO circuit, a constant increase of 800 MHz in the VCO output frequency is measured across 1.2 V control voltage Vctrl. 
     To achieve high Q and compact layout, the transmission lines are realized by three identical inductors in series.  FIG. 6  shows a layout arrangement of a ground shield for the transmission lines in the VCO in  FIG. 5   a . Two layers of ground shield comprise polysilicon Poly and metal 1  M 1  are placed alternately underneath the spirals (the transmission lines). Since the gaps between the spirals and the substrate are filled, the electric field lines are confined between the spiral and the shields, minimizing the capacitive coupling to the substrate and increase Q factor of the inductor. Simulation indicates the Q factor of the inductor of the VCO is 16 at 75 GHz. 
       FIG. 7   a  is a circuit schematic of still another exemplary VCO according to the invention, comprising bias circuit  70   a , transistors M 70  and M 72 , transmission lines L 50 , and cross-coupled transistor pair M 40 . Bias circuit  70   a  is coupled to transistor M 70 , subsequently coupled to transistor M 72 , transmission lines L 50  and cross-coupled transistor pair M 40 . 
     To suppress the coupling from power lines, the VCO is biased with supply-independent circuit  70   a , comprising transistors M 700  through M 706 , and resistor R S . Transistors M 700  and M 702 , and M 704  and M 706  are current mirrors, such that the drain currents through transistors M 700  through M 706 , and transistor M 70 , are only determined by device dimensions thereof, independent of supply voltage V DD . Transistor M 72  is introduced to absorb extra current variation in transistor M 70  due to channel-length modulation to further reject the supply noise. By proper device sizing we set: 
                            δ   ⁢           ⁢     I   ss         δ   ⁢           ⁢     V   DD              =            δ   ⁢           ⁢     I   C         δ   ⁢           ⁢     V   DD                      (   1   )               
where V DD  is the supply voltage, I SS  is the drain current through transistor M 70 , and I C  is the drain current through transistor M 70 .  FIG. 7   b  shows the relationship of supply voltage V DD  and drain currents I SS  and I C .  FIG. 7   b  suggests an identical slope for drain currents I SS  and I C  when supply voltage V DD  varies, thus the channel-length modulation current in I SS  is compensated by I C , the rest of the current flowing into the transmission lines remains constant, and the VCO resonance frequency is insensitive to supply perturbation, as in  FIG. 7   c , depicting the relationship of supply voltage V DD  and the oscillation frequency of the VCO in  FIG. 7   a . The power consumption of compensation transistor M 72  can be restrained to as low as 20-30%.
 
       FIG. 8  is a circuit schematic of yet another exemplary VCO according to the invention, comprising bias circuit  70 , VCO circuit  80 , frequency dividers  82 , inductors L 80 , resistors R 80 , buffer transistors M 80  and M 82 , and compensation inductor L R . 
     The description for bias circuit  70  and VCO circuit  80  are provided in the circuits of  FIGS. 7   a  and  5   a . A natural bias is established by cross-coupled transistor pair M 800  to facilitate dc coupling between VCO circuit  80  and external circuits or the feedback path. Frequency dividers  82  are the first division stage, implemented by injection locked frequency dividers. Two identical injection locked dividers  82  are used to preserve symmetry, one generates 37.5 GHz VCO output signal CK out  to the second divider stage, and the other provides a half-rate clock output for testing purpose. Dummy buffer M 80  is used along with careful layout to provide a loading balance between the loading at nodes B and B′. Inductor L R  is included to cancel out the parasitic capacitance associated with nodes C and C′, allowing stronger signal injection through transducer amplifiers M 82 . 
       FIG. 9  is a block diagram of an exemplary phase and frequency detector (PFD) according to the invention, comprising phase-frequency detector  22 , loop filters  90 , hysteresis buffers  92 , and flip-flop  94 . Phase-frequency detector  22  is coupled to loop filters  90 , hysteresis buffers  92 , and then to flip-flop  94 . 
     Phase and frequency detector (PFD) uses single sideband mixers to realize phase and frequency detection between reference signals CK ref,i , CK ref,q  and feedback signals CK div,i , CK div,q  and produce phase error V PD  and frequency error V FD , controlling control voltage Vctrl to adjust the output frequency of the VCO such that the phase and frequency errors are reduced. In the embodiment, the phase detection and frequency detection are integrated into one circuit to reduce circuit complexity, circuit dimension, and manufacturing cost. The single sideband approach reduces signal interference of reference spurs resulting from the charge pump approaches in the PFD in  FIG. 1 . 
       FIG. 10   a  is a block diagram of an exemplary phase detector in  FIG. 9 , comprising mixers  1000 ,  1002 , and adder  1004 . Mixers  1000  and  1002  are coupled to adder  1004  to produce phase error V PD . 
     Phase detector  220  is a single sideband mixer, in which mixer  1000  multiplies quadrature signal CK ref,q  of the reference signal with in-phase signal CK div,i  of the feedback signal to generate a first multiplication output, mixer  1002  multiplies in-phase signal CK ref,i  of the reference signal with quadrature signal CK div,q  of the feedback signal to generate a second multiplication output, and adder  1004  adding the first multiplication output with a negation of the second multiplication output to generate phase error V PD . 
     To prevent on-off pulses that produces reference spurs, the phase detection is performed by mixing the orthogonal components of the reference and feedback signals. A single sideband (SSB) mixer is employed to extract the phase error between the reference and feedback signals, rendering phase detector signal V PD  that exhibits a sinusoidal relationship with the actual phase error θ between the reference and feedback signals.  FIG. 10   b  depicts the relationship of phase detector voltage V PD  and error θ, incorporating the phase detector in  FIG. 10   a . Referring to  FIG. 10   b , since the waveform characteristic can be approximated to a linear relationship in the vicinity of origin, phase error θ is computed according to phase detector voltage V PD . By utilizing the SSB mixer in  FIG. 10   a  and the relationship in  FIG. 10   b , no pulse generation is involved in phase detection, resulting in a “quiet” phase examination and reducing reference spurs significantly. 
     Next, PD voltage-to-current converter  224  obtains phase error θ for current conversion proportional thereto, and outputs a positive or negative converted phase error current to loop filter  24 , which accordingly generates control voltage Vctrl. The current imbalance in PD voltage-to-current converter  224  is no longer an issue, since phase detector phase detector  220  creates an offset between the reference and feedback signals to compensate the offset. 
     In the presence of mismatches, finite “image” signal is observed at twice of the reference frequency of reference signals CK ref,i  and CK ref,j , and a low pass filter is inserted after the SSB mixer to suppress the image signal.  FIG. 10   c  is a circuit schematic of an exemplary phase detector capable of suppressing the image signal, comprising mixers  1000 ,  1002 , resistors R and capacitors C. The phase detector circuit in  FIG. 10   c  is realized by loading the SSB mixer with an RC network, for example, R=600Ω, C=32 pF, generating a corner frequency of 8.3 MHz and reject the image signal by more than 40 dB. The low-pass filter has little impact on the overall loop bandwidth, operated at around 2-3 MHz. The phase detector circuit in  FIG. 10   c  reveals a minimum ripple of only 15 V. 
       FIG. 11  is a block diagram of an exemplary frequency detector in  FIG. 9 , comprising mixers  1100 ,  1102 ,  1104 , and  1106 , and adders  1108  and  1110 . Mixers  1100  and  1102  are coupled to adder  1108 . Mixers  1104  and  1106  are coupled to adder  1110 . 
     Mixer  1100  multiplies the quadrature signal of the reference signal with the in-phase signal of the feedback signal to generate a first multiplication output. Mixer  1102  multiplies the in-phase signal of the reference signal with the quadrature signal of the feedback signal to generate a second multiplication output. Adder  1108  adds the first multiplication output with a negation of the second multiplication output to generate first SSB output V PD . Mixer  1104  multiplies the in-phase signal of the reference signal with the in-phase signal of the feedback signal to generate a third multiplication output. Mixer  1106  multiplies the quadrature signal of the reference signal with the quadrature signal of the feedback signal to generate a fourth multiplication output. Adder  1110  adds the first multiplication output with the second multiplication output to generate second SSB output V 2 . A flip-flop (not shown), coupled to the first and second FD adders, latches first SSB output V PD  by second SSB output V 2  to generate FD error V FD . 
     Frequency detector  222  is implemented by two SSB mixers. First SSB output V PD  also serves as the phase detector signal in phase detector circuit phase detector  220 . First SSB output V FD  and second SSB output V 2  are orthogonal in the presence of frequency error Δω in :
 
 V   PD   =kA   1   A   2  sin (Δω in   t +θ)  (2)
 
 V   2   =kA   1   A   2  cos (Δω in   t+θ )  (3)
 
Where Δω in  is a frequency difference between reference signal CK ref  and feedback signal CK div , k is a mixer gain of the SSB mixer, A 1  is an amplitude of reference signal CK ref , A 2  is an amplitude of reference signal CK div , θ is the phase error. Whether first SSB output V PD  leads or lags second SSB output V 2  is determined by the sign of frequency error Δω in . The flip-flop latches first SSB output V PD  by second SSB output V 2  to sample one signal with the other to obtain the sign of frequency error Δω in . Based on the flip-flop&#39;s output, V/I converter (V/I) FD  FD voltage-to-current converter  226  injects a positive or negative FD current to loop filter  24 . The FD current is 3 times larger than the peak current of V/I converter (V/I) PD  PD voltage-to-current converter  224  to provide a smooth frequency acquisition. To reduce the disturbance to control voltage Vctrl, the automatic switching-off function of frequency detector  222  and FD voltage-to-current converter  226  is provided in this design by applying signal ENFD to (V/I) FD  FD voltage-to-current converter  226 , disabling frequency detector  222  and FD voltage-to-current converter  226  upon frequency locked up to reduce power consumption and increase signal stability.
 
     When the frequencies of reference signal CK ref  and feedback signal CK d,v  are close, the sinusoidal SSB output V PD  and second SSB output V 2  becomes very slow, which may cause malfunction of the flip-flop if they drive the flip-flop directly, because the transitions signal CK ref  and feedback signal CK d,v  become extremely slow when the loop is close to be locked. The transient fluctuation caused by unwanted coupling or additive noise would make the transitions ambiguous, possibly resulting in false multiple zero crossings at the output of the flip-flop. To counter this problem, hysteresis buffers are employed to sharpen the waveforms.  FIG. 12   a  is a circuit schematic of an exemplary hysteretic buffer in  FIG. 9 , comprising cross-coupled transistor pairs M 1200  and M 1202 , resistors R, and current sources I SS1  and I SS2 . The cross-coupled pair M 1202  provides different switching thresholds for low-to-high transition LH and high-to-low HL transition, and the positive feedback helps to create square waves as well. In the embodiment, the aspect ratio of the device (W/L) M1200 =(W/L) M1200 =8/0.25, and a threshold difference of 46 mV is provided in  FIG. 12   b , showing the relationship of input voltage V in  and output voltage V out  for the phase detector in  FIG. 10   a.    
     The frequency detector  222  in  FIG. 11  may further comprises first and second hysteresis buffers. The first hysteresis buffer is coupled to adder  1108  and the flip-flop, outputs a “HIGH” voltage to the data port of the flip-flop when phase error θ exceeds a first LH threshold, and outputs a “LOW” voltage to the data port of the flip-flop when phase error θ is less than or equals to a first HL threshold. The first LH threshold exceeds the first HL threshold. The second hysteresis buffer is coupled to FD adder  1110  and the flip-flop, outputs a “HIGH” voltage to the clock port of the flip-flop when the frequency error exceeds a second LH threshold, and outputs a “LOW” voltage to the clock port the flip-flop when the frequency error is less than or equals to a second HL threshold. Again, the second LH threshold exceeds the second HL threshold. 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.