Abstract:
A hysteretic mode control circuit within a DC-to-DC converter is configured for varying the current limit that controls the switching interval and duration of a power switching section of the DC-to-DC converter to permit the DC-to-DC converter to manage large changes in output current load of the DC-to-DC converter. The hysteretic mode control circuit has a positive and a negative current limit section that develop a first and a second reference signal for turning on and turning off the first and the second switching device. The first and second reference signals are compared to an output voltage of the power switching section to determine if the first switching device or the second switching device is to be turned on or turned off.

Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates generally to circuits and methods for controlling operation of switching power converters. More particularly, the present disclosure relates to circuits and methods for controlling operation of a pulse frequency modulated buck DC-to-DC converter to decrease noise coupling and permit a variable current to accommodate large output currents. 
       BACKGROUND 
       [0002]    As is known in the art, a buck DC-to-DC converter is a voltage step down and current step up converter. A buck DC-to-DC converter has a power switching section and a low pass filter section. The power switching section reduces the DC component of the power supply voltage source and the filter section removes the high frequency harmonics created by the power switching section to generate the desired DC output voltage level. 
         [0003]    The power switching section has a first switch with a first terminal connected to one terminal of a power supply voltage source. The power supply voltage source may be a battery or the rectified AC power mains. The second terminal of the first switch is connected to a filter section of the buck DC-to-DC converter. A second switch in the power switching section has a first terminal connected to a ground reference voltage terminal. The second terminal of the second switch is connected to the second terminal of the first switch and the filter section of the buck DC-to-DC converter. The first and second switches each have a control terminal that is connected to control circuitry that determines the switching frequency and duration of the activations of the first and second switches based on a feedback signal from an output of the buck DC-to-DC converter. 
         [0004]    The input of the filter section is a first terminal of an inductor and the second terminal of the inductor is connected to a first terminal of a filter capacitor. The second terminal of the filter capacitor is connected to the ground reference voltage terminal. The output of the buck DC-to-DC converter is the common connection of the second terminal of the inductor and the first terminal of the filter capacitor. A sense circuit is commonly applied to the output terminal of the buck DC-to-DC converter to provide the feedback signal for the control circuitry. 
         [0005]    The buck DC-to-DC converter operates in a continuous, synchronous, or pulse width modulated mode for higher current or heavily loaded operation. The first and second switches are activated and deactivated at a fixed frequency and the period between each activation and deactivation is determined by comparing the feedback signal with a desired reference signal to create the desired output voltage. When the buck DC-to-DC converter operates in a discontinuous, asynchronous or pulse frequency modulated mode for low current or lightly loaded operation, the switches do not supply the current from the power supply voltage source on each cycle and the current then supplied during the commutation mode where current is provided from the collapsing field of the inductor. Often the discontinuous mode is used in portable electronics such as smart cellular telephones, tablet computers, digital readers, etc. as a “sleep mode”. The only current required by the system in these applications is monitoring current for system maintenance (i.e. system clocking and timers, cellular network monitoring, wireless network monitoring). 
         [0006]    In the pulse frequency modulation mode, the buck DC-to-DC converter turns on the first switch to apply the power supply voltage source to the inductor when the output voltage falls below a reference voltage. The first switch is then turned off when the current in the coil reaches a threshold value (sleep current limit). The second switch is turned on when the first switch is turned off. The second switch is then turned off when the current in the coil is fully discharged. The pulse frequency modulation mode is not typically used for large currents as the current limit is normally set low to maximize efficiency. 
         [0007]    Buck DC-to-DC converter converters operate in the pulse frequency modulation mode have serious problems with noise coupling when operating a high current levels. Further, when the second switch is open, there is no path from the filter section for negative currents resulting from overvoltage situations at the output of the buck DC-to-DC converter. 
       SUMMARY 
       [0008]    An object of this disclosure is to provide circuits and methods for operating a buck DC-to-DC converter in a pulse frequency mode with variable current limits to provide the ability to manage large output currents. 
         [0009]    Another object of this disclosure is to provide circuits and methods for operating a buck DC-to-DC converter in hysteretic mode where switching of the power supply voltage source is governed by output current and voltage thresholds. 
         [0010]    To accomplish at least one of these objects, a hysteretic mode control circuit within a DC-to-DC converter. The hysteretic mode control circuit is configured for varying the current limit that controls the switching interval and duration of a power switching section of the DC-to-DC converter to permit the DC-to-DC converter to manage large changes in its output current load. 
         [0011]    The hysteretic mode control circuit has a positive current limit section and a negative current limit section. The positive current limit section is configured for determining a first reference voltage that is used for controlling activation a first switching device of a switching section of the DC-to-DC converter for transferring current to a load device placed at the output of the DC-to-DC converter. In some embodiments, the positive current limit section has a first matching switching device having dimensions and electrical characteristics matching the first switching device. The matching switching device is connected to a first reference current source configured to develop a first reference signal for turning on and turning off the first switching device. The first reference signal is compared to an output voltage of the power switching section to determine if the first switching device is to be turned on or turned off. 
         [0012]    In some embodiments, the negative current limit section is configured for determining a second reference voltage that is used for controlling activation a second switching device of a switching section of the DC-to-DC converter for accepting current from the DC-to-DC converter. In some embodiments, the negative current limit section has a second matching switching device having dimensions and electrical characteristics matching the first switching device. The matching switching device is connected to a second reference current source configured to develop a second reference signal for turning on and turning off the second switching device. The second reference signal is compared to the output voltage of the power switching section to determine if the second switching device is to be turned on or turned off. 
         [0013]    In other embodiments, the positive current section has a dynamic current limit circuit that has a first reference current source providing a maximum reference current to a reference leg of a first current mirror. A mirror leg of the first current mirror is connected to provide a reference limit voltage for an output of the positive current section to determine the switching interval and duration of the first switching device of the power switching section to provide current to the filter section of the DC-to-DC converter. A feedback signal from the output of the DC-to-DC converter and a first reference voltage are inputs to a comparator for determining if the feedback signal is greater than or less than the first reference voltage. An output of the comparator is an input to a switching device that is activated or deactivated to divert current from the reference leg of the current mirror and thus modify the current in mirror leg of the current mirror and thus adjust the voltage level of the reference limit voltage. 
         [0014]    A load device is connected to the mirror leg of the current mirror for developing the reference limit voltage. In various embodiments, the dynamic current limit circuit has a second current source connected in parallel with the mirror leg of the current mirror to provide an optional minimum reference current. 
         [0015]    In various embodiments, hysteretic mode control circuit has a variable current limit section. A driver control circuit receives a first control signal developed by a comparison of a feedback signal from the output of the DC-to-DC converter with a reference voltage and a second control signal developed by the variable current limit section for controlling activation the first switching device of a switching section of the DC-to-DC converter for transferring current to a load device placed at the output of the DC-to-DC converter. 
         [0016]    The variable current limit section is configured for determining the second control signal by sensing a voltage level present at the input to the low pass filter of the DC-to-DC converter. The voltage level sensing signal is applied to a first terminal of a adjustable differential current source. A control terminal of the adjustable differential current source is controlled by the comparison of the feedback signal from the output of the DC-to-DC converter with the reference voltage. The second control signal developed across the adjustable differential current source is applied to the driver control circuit to permit activation of the first and second switching devices according to the level of the necessary voltage across or current through the low pass filter. 
         [0017]    In various embodiments, the variable current limit section has a compensation current source that is connected in parallel with the adjustable differential current source. The compensation current source provides a fixed ramp current that is summed with the adjustable differential current source for providing compensation to prevent sub-harmonic oscillation. 
         [0018]    In various embodiments that accomplish at least one of these objects, a DC-to-DC converter includes a hysteretic mode control circuit configured for varying the current limit that controls the switching interval and duration of a power switching section of the DC-to-DC converter to permit the DC-to-DC converter to manage large changes in output current load of the DC-to-DC converter. 
         [0019]    In various embodiments that accomplish at least one of these objects, a method for providing hysteretic mode control within a DC-to-DC converter. The method provides the mode control through a hysteretic mode control circuit that varies the current limit that controls the switching interval and duration of a power switching section of the DC-to-DC converter to permit the DC-to-DC converter to manage large changes in output current load of the DC-to-DC converter. 
         [0020]    The method begins by determining a limit signal proportional to a positive limit current and a negative limit current for the current flowing in the low pass filter of the DC-to-DC converter. In various embodiments, the limit signal is a voltage that is compared to a voltage that is developed at the input of the low pass filter of the DC-to-DC converter. If a positive voltage that is developed at the input of the low pass filter of the DC-to-DC converter is greater than a positive limit signal voltage, a first latching circuit is reset and a positive switching device is disabled to prevent current from flowing into the low pass filter. Alternately, if the positive voltage that is developed at the input of the low pass filter of the DC-to-DC converter is less than the positive limit signal voltage, the first latching circuit is not reset and the positive switching device is enabled to allow current to flow into the low pass filter. 
         [0021]    If a negative voltage that is developed at the input of the low pass filter of the DC-to-DC converter is greater than a negative limit signal voltage, a second latching circuit is reset and a negative switching device is disabled to prevent current from flowing from the low pass filter. Alternately, if the negative voltage that is developed at the input of the low pass filter of the DC-to-DC converter is less than the negative limit signal voltage, second first latching circuit is not reset and the negative switching device is enabled to allow current to flow from the low pass filter. 
         [0022]    In some embodiments, first setting a maximum reference current and a minimum reference current develop the positive and negative limit signals. A difference between a reference voltage of the DC-to-DC converter and a feedback voltage of the DC-to-DC converter is determined as difference voltage. The difference voltage is converted to a difference current. The difference current is subtracted from the maximum reference current to form a variable limit current. A positive variable limit current is mirrored and converted to the positive limit signal and a negative variable limit current is mirrored and converted to the negative limit signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a schematic of a DC-to-DC converter operating with a pulse width modulation mode and pulse frequency modulation mode. 
           [0024]      FIG. 2  is a schematic of DC-to-DC converter operating with a pulse width modulation mode and pulse frequency modulation mode embodying the principals of the present disclosure. 
           [0025]      FIG. 3  is a schematic of a positive and negative current limit circuit incorporated within a DC-to-DC converter embodying the principals of the present disclosure. 
           [0026]      FIG. 4  is a schematic of an embodiment of a positive dynamic current limit circuit and a negative dynamic current limit circuit incorporated within a DC-to-DC converter of  FIG. 2 . 
           [0027]      FIG. 5  is a schematic of a DC-to-DC converter with a dynamic sleep mode embodying the principals of the present disclosure. 
           [0028]      FIG. 6  is a plot of the waveforms of the signals the DC-to-DC converter of  FIG. 5  with a dynamic sleep mode with a continuous loading. 
           [0029]      FIG. 7  is a plot of the waveforms of the signals the DC-to-DC converter of  FIG. 5  in dynamic sleep mode operation illustrating a change in load current. 
           [0030]      FIGS. 8 and 9  are flowcharts of a method for providing hysteretic mode control within a DC-to-DC converter embodying the principals of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]      FIG. 1  is a schematic of a DC-to-DC converter operating with a pulse width modulation mode and pulse frequency modulation mode. The power switching section  120  has a switching control circuit  125  that generates control signals that are applied to a positive input of a driver circuit  130   a  and a negative input of a driver circuit  130   b . The output of the driver circuit  130   a  is applied to the gate of the PMOS transistor MP 1  and the output of the driver circuit  130   b  is applied to the gate of the NMOS transistor MN 1 . The source of the PMOS transistor MP 1  is connected to the power supply voltage source VDD and the source of the NMOS transistor MN 1  is connected to the substrate supply voltage source VSS. The substrate supply voltage source VSS is often the ground reference voltage source, but in some applications is a negative voltage level. The commonly connected drains of the PMOS transistor MP 1  and the NMOS transistor MN 1  are connected to an input terminal of the filter section  135 . The input terminal is a first terminal of an inductor L 1 . The control circuit  125  determines that during the continuous mode or pulse width modulation mode the control signals  116  and  118  are applied to the driver circuit  130   a  and the driver circuit  130   b  such that the PMOS transistor MP 1  is turned on and the NMOS transistor MN 1  is turned off, a current from the power supply voltage source VDD from the first terminal of the inductor L 1  out the second terminal of the inductor L 1  into the first terminal of the output capacitor C OUT  and to the substrate supply voltage source VSS. The output voltage V OUT  is present at the junction of the second terminal of the inductor L 1  and the output capacitor C OUT . 
         [0032]    It is known in the art, that the voltage (V L1 ) across the inductor L 1  is determined by the formula: 
         [0000]    
       
         
           
             
               V 
               
                 L 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               L 
                
               
                 
                    
                   
                     I 
                     L 
                   
                 
                 
                    
                   t 
                 
               
             
           
         
       
     
         [0000]    The output voltage V OUT  is equal to the difference of the power supply voltage source VDD and the voltage V L1  across the inductor L 1  in the on state and equal to the negative of the voltage −V L1  across the inductor L 1  in the off state. The duty cycle of the buck DC-to-DC converter determines the on state time and the off state time. It can be shown that the output voltage V OUT  is equal to the duty cycle of the buck DC-to-DC converter multiplied by the voltage level of the power supply voltage source VDD. 
         [0033]    The feedback stage  140  has three inputs. The first input  107  is the feedback voltage V FB  that is developed from the output voltage V OUT  at common connection of the second terminal of the inductor L 1  and the first terminal of the output capacitor C OUT . The second and third inputs are the first and second reference voltages V REF1  and V REF2  generated by the switch control circuit  105 . The switch control circuit  105  has a digital-to-analog converter  110  that receives a reference control word  112  and an offset control word  114 . The digital-to-analog converter  110  converts the reference control word  112  to the first reference voltage V REF1  and the offset control word  114  to the second reference voltage V REF2 . The first reference voltage V REF1  and the second reference voltage V REF2  are the second and third inputs to the feedback stage  115 . The feedback control stage  115  has a first comparator  117  for providing a first control signal  116  and a second comparator  119  for providing a second control signal  118 . The first control signal  116  is applied to a data input D of a first data flip-flop  127  of the switching control circuit  125 . The second control signal  118  is applied to a data input D of a second data flip-flop  129  of the switching control circuit  125 . An oscillator  150  generates the clock pulse signal  152  that is applied to the clock CK input of the first data flip-flop  127  and the second data flip-flop  129 . The output of the first data flip-flop  127  is applied to the input of the positive driver circuit  130   a  and the output of the second data flip-flop  129  is applied to the input of the negative driver circuit  130   b . The output of the first driver circuit  130   a  is applied to the gate of the PMOS transistor MP 1  and the output of the second driver circuit  130   b  is applied to the gate of the NMOS transistor MN 1 . 
         [0034]    A current/voltage sense circuit  140  is placed at the junction of the second terminal of the inductor L 1  and the output capacitor C OUT . The current/voltage sense circuit  140  determines the feedback voltage V FB  and the feedback current I FB . The feedback voltage V FB  is fed back as the first input to the first comparator  117  and the second comparator  118 . The feedback current I FB  is fed back to a pulse width modulation/pulse frequency modulation control circuit  145 . Based on the feedback current I FB  as determined by the load current I OUT , the pulse width modulation/pulse frequency modulation control circuit  145  resets the first data flip-flop  127  and the second data flip-flop  129 . If the DC-to-DC converter is operating in the pulse width modulation mode, the first data flip-flop  127  and the second data flip-flop  129  are not reset and the data outputs of the first data flip-flop  127  and the second data flip-flop  129  are controlled by the feedback voltage V FB  to determine the pulse width of the control signals driving the first driver circuit  130   a  and the second driver circuit  130   b  and thus the PMOS transistor MP 1  and the NMOS transistor MN 1 . 
         [0035]    When the load current I OUT  decreases to a predetermined level, the DC-to-DC converter is set to the pulse frequency modulation mode. The feedback current I FB  is interpreted by the pulse width modulation/pulse frequency modulation control circuit  145  such that the second data flip-flop  129  is reset. This turns off the NMOS transistor MN 1 . The pulse width modulation/pulse frequency modulation control circuit  145  resets the first data flip-flop  127  and the PMOS transistor MP 1  is turned off. If the output voltage V OUT  decreases below a threshold, the output current I OUT  is increasing and the pulse width modulation/pulse frequency modulation control circuit  145  releases the reset of the first data flip-flop  127  to activate the PMOS transistor MP 1  to allow current to flow into the filter section  135 . 
         [0036]    Since the NMOS transistor MN 1  is turned off, the DC-to-DC converter can not accept current from the load, therefore any overvoltage of the output voltage V OUT  is not discharged. Further, the PMOS transistor MP 1  is turned on asynchronously at high load creating serious implications for noise being coupled to the system that is load being powered. 
         [0037]      FIG. 2  is a schematic of a DC-to-DC converter operating with pulse width modulation mode and pulse frequency modulation mode embodying the principals of the present disclosure. A switch control circuit  205  has a digital-to-analog converter  210  that receives a reference control word  212  and an offset control word  214 . The digital-to-analog converter  210  converts the reference control word  112  to the first reference voltage V REF1  and converts the offset control word  114  to the second reference voltage V REF2 . The first reference voltage V REF1  and the second reference voltage V REF2  are two of the three inputs to the feedback stage  215 . The feedback stage  215  has a first comparator  217  that receives the first reference voltage V REF1  and a second comparator  219  that receives the second reference voltage V REF2 . The third  207  of the three inputs to the feedback stage  215  receives the feedback voltage V FB  that is compared to the first reference voltage V REF1  and the second reference voltage V REF2 . As described previously, the feedback voltage V FB  that is developed from the output voltage V OUT  at common connection of the second terminal of the inductor L 1  and the first terminal of the output capacitor C OUT  of the filter section  235 . 
         [0038]    The outputs  216  and  218  of the first comparator  217  and a second comparator  219  are the inputs to the switching control circuit  225 . The first comparator  217  provides the first control signal  216  is applied to a data input D of a first data flip-flop  227  of the switching control circuit  225 . The second comparator  219  provides the second control signal  218  that is applied to a data input D of a second data flip-flop  229  of the switching control circuit  225 . An oscillator  250  generates the clock pulse signal  252  that is applied to the clock CK input of the first data flip-flop  227  and the second data flip-flop  229 . The output of the first data flip-flop  227  is applied to the input of the positive driver circuit  230   a  and the output of the second data flip-flop  229  is applied to the input of the negative driver circuit  230   b . The output of the first driver circuit  230   a  is applied to the gate of the PMOS transistor MP 1  and the output of the second driver circuit  230   b  is applied to the gate of the NMOS transistor MN 1 . 
         [0039]    The source of the PMOS transistor MP 1  is connected to the power supply voltage source VDD and the source of the NMOS transistor MN 1  is connected to the substrate supply voltage source VSS. The substrate supply voltage source VSS is often the ground reference voltage source, but in some applications is a negative voltage level. The commonly connected drains of the PMOS transistor MP 1  and the NMOS transistor MN 1  are connected to an input terminal of the filter section  235 . The input terminal is a first terminal of an inductor L 1 . The control signals  216  and  218  are applied to the driver circuit  230   a  and the driver circuit  230   b  such that the PMOS transistor MP 1  is turned on and the NMOS transistor MN 1  is turned off, a current from the power supply voltage source VDD from the first terminal of the inductor L 1  out the second terminal of the inductor L 1  into the first terminal of the output capacitor C OUT  and to the substrate supply voltage source VSS. The output voltage V OUT  is present at the junction of the second terminal of the inductor L 1  and the output capacitor C OUT . 
         [0040]    A positive current limit stage  240   a  is connected in proximity with the PMOS transistor MP 1  and the negative current limit circuit  240   b  is connected in proximity with the NMOS transistor MN 1 . The positive current limit circuit  240   a  and the negative current limit circuit  240   b  are connected between the power supply voltage source VDD and the substrate supply voltage source VSS. The output of the driver circuit  230   a  is connected to the positive current limit stage  240   a  and the driver circuit  230   b  is connected to the negative current limit circuit  240   b . The output of the positive current limit circuit  240   a  is a positive reference limit voltage  242  and the output of the negative current limit circuit  240   b  is a negative reference limit voltage  244 . The positive reference limit voltage  242  and the negative reference limit voltage  244  are the inputs to the pulse width modulation/pulse frequency modulation control circuit  245 . The pulse width modulation/pulse frequency modulation control circuit  245  compares the positive reference limit voltage  242  with the voltage V LX  developed at the first terminal of an inductor L 1  for selectively resetting of the first data flip-flop  227  to control operation of PMOS transistor MP 1 . The pulse width modulation/pulse frequency modulation control circuit  245  compares the negative reference limit voltage  244  with the voltage V LX  developed at the first terminal of an inductor L 1  for selectively resetting of the second data flip-flop  229  to control operation of the NMOS transistor MN 1 . 
         [0041]      FIG. 3  is a schematic of the positive current limit circuit  240   a  and the negative current limit circuit  240   b  incorporated within a DC-to-DC converter embodying the principals of the present disclosure. The positive current limit circuit  240   a  has a PMOS transistor MP 2  that is a dummy transistor having characteristic that are matched to the geometry and impurity implantations of the PMOS transistor MP 1 . The PMOS transistor MP 2  is used to generate the reference voltage V LIM+  for the current limit of the current passing through the PMOS transistor MP 1  across the positive reference current source I 1 . The PMOS transistor MP 2  has a gate connected to the output of the positive driver circuit  230   a . The source of the PMOS transistor MP 2  is connected to the power supply voltage source VDD and the drain of the PMOS transistor MP 2  is connected to a first terminal of the positive reference current source I 1 . The second terminal of the positive reference current source I 1  is connected to the substrate supply voltage source VSS. 
         [0042]    The negative current limit circuit  240   a  has an NMOS transistor MN 2  that is a dummy transistor characteristic that are matched to the geometry and impurity implantations of the NMOS transistor MN 1 . The NMOS transistor MN 2  is used to generate the reference voltage V LIM−  for the current limit of the current passing through the NMOS transistor MN 1  across the negative reference current source I 2 . The first terminal of the negative reference current source I 2  is connected to the power supply voltage source VDD. The drain of the NMOS transistor MN 2  is connected to a second terminal of the negative reference current source I 2  and the source of the NMOS transistor MN 2  is connected to the substrate supply voltage source VSS. The NMOS transistor MN 2  has a gate connected to the output of the negative driver circuit  230   b.    
         [0043]    The junction  242  of the PMOS transistor MP 2  and the first terminal of the first current source I 1  is connected to a first terminal of the third comparator  247  of the pulse width modulation/pulse frequency modulation control circuit  245 . Similarly, the junction  244  of the NMOS transistor MN 2  and the second terminal of the second current source I 2  is connected to a first terminal of the fourth comparator  249  of the pulse width modulation/pulse frequency modulation control circuit  245 . The second terminals of the third comparator  247  and fourth comparator  249  are connected to the connection of the drains of the PMOS transistor MP 1  and the NMOS transistor MN 1  with the first terminal of the inductor L 1  of  FIG. 2 . The reference voltage V LIM+  and reference voltage V LIM−  are compared with the voltage V LX  developed at the connection of the drains of the PMOS transistor MP 1  and the NMOS transistor MN 1  with the first terminal of the inductor L 1  during the corresponding part of the duty cycle to determine when the output current is too high. The results of the comparison of the reference voltage V LIM+  and reference voltage V LIM−  with the voltage V LX  are applied to the control logic circuit  246  to generate the reset signals V RST+  and V RST−  that are transferred respectively to the reset terminals R of the first data flip-flop  227  and the second data flip-flop  229 . 
         [0044]    As noted above, the output of the first driver circuit  230   a  controls the gate of the PMOS transistor MP 1  and the output of the second driver circuit  230   b  controls the gate of the NMOS transistor MN 1 . With the input of the driver circuit  230   a  being controlled by the output of the first data flip-flop  227  and the input of the driver circuit  230   b  being controlled by the second data flip-flop  229 . If the first control signal  216  or the second control signal  218  as applied to the data inputs of the first data flip-flop  227  and the input of the second data flip-flop  229  are active at the receipt of the triggering edge of the clock pulse signal  252 , the output of the first data flip-flop  227  and the output of the second data flip-flop  229  turn on the corresponding PMOS transistor MP 1  or NMOS transistor MN 1 . The activated PMOS transistor MP 1  or NMOS transistor MN 1  is then turned off by the corresponding reset signals V RST+  and V RST− . 
         [0045]    It should be noted that the control logic circuit  246  has circuitry that will permit the reset signals V RST+  and V RST−  to turn on the either the activated PMOS transistor MP 1  or NMOS transistor MN 1 , as required. In some embodiments, the second comparator  219  is offset by approximately 10 mV as determined by the second reference voltage V ref2  to allow a small range of output voltages for which the PMOS transistor MP 1  or NMOS transistor are not switched to provide a saving in power for very low loads. 
         [0046]      FIG. 4  is a schematic of an embodiment of a positive dynamic current limit circuit  240   a  and a negative dynamic current limit circuit  240   b  incorporated within a DC-to-DC converter of  FIG. 2 . In the embodiment as shown, a first differential amplifier  241  receives the first reference voltage V REF1  and the feedback voltage V FB  to be compared. The output of the differential amplifier  241  is connected to a gate of a first NMOS switching transistor N 1 . The drain of the first NMOS switching transistor N 1  is connected to a first terminal of a third current source I 3  that sources a maximum positive reference current I MAX+ . A second terminal of the third current source I 3  is connected to the power supply voltage source VDD. 
         [0047]    The NMOS transistors N 2  and N 3  form a positive limit current mirror. The NMOS transistor N 2  is a diode-connected transistor that forms the reference leg of the positive limit current mirror and has its gate and drain commonly connected to the first terminal of the third current source I 3 . The source of the NMOS transistor N 2  is connected to the substrate supply voltage source VSS. The NMOS transistor N 3  forms the mirror leg of the positive limit current source and has its gate connected to the commonly connected gate and drain of the NMOS transistor N 2  of the reference leg. The drain of the NMOS transistor N 3  is connected to the drain of a dummy PMOS transistor P 1 . The source of the dummy PMOS transistor P 1  is connected to the power supply voltage source VDD and the gate of the dummy PMOS transistor P 1  is connected to the substrate supply voltage source VSS. The dummy PMOS transistor P 1  is matched to the geometry and impurity implantations of the PMOS transistor MP 1  of  FIG. 2 . 
         [0048]    The first differential amplifier  241  compares the first reference voltage V REF1  and the feedback voltage V FB  voltage. The voltage level of the output of the differential amplifier  241  causes the NMOS transistor N 1  to steal current from the third current source I 3  that sources a maximum positive reference current I MAX+ . The maximum positive reference current I MAX+  sets the maximum current limit possible. The current mirror formed by the NMOS transistors N 2  and N 3  then mirrors the remaining current through the dummy PMOS transistor P 1 . In various embodiments, a fourth current source I 4  provides a fixed minimum current that may optionally be necessary. The output reference voltage V LIM+  is applied to the input of the pulse width modulation/pulse frequency modulation control circuit  245 . 
         [0049]    A second differential amplifier  242  receives the second reference voltage V REF2  and the feedback voltage V FB  to be compared. The output of the differential amplifier  243  is connected to a gate of a second PMOS switching transistor P 2 . The drain of the second PMOS switching transistor P 2  is connected to a first terminal of a fifth current source I 5  that sources a maximum negative reference current I MAX− . A second terminal of the fifth current source I 5  is connected to the substrate supply voltage source VSS. 
         [0050]    The PMOS transistors P 3  and P 4  form a negative limit current mirror. The PMOS transistor P 3  is a diode-connected transistor that forms the reference leg of the positive limit current mirror and has its gate and drain commonly connected to the first terminal of the fifth current source I 5 . The source of the PMOS transistor P 3  is connected to the power supply voltage source VDD. The PMOS transistor P 4  forms the mirror leg of the negative limit current source and has its gate connected to the commonly connected gate and drain of the PMOS transistor P 3  of the reference leg. The drain of the PMOS transistor P 4  is connected to the drain of a dummy NMOS transistor N 4 . The source of the dummy NMOS transistor N 4  is connected to the substrate supply voltage source VSS and the gate of the dummy PMOS transistor P 1  is connected to the power supply voltage source VDD. The dummy NMOS transistor N 4  is matched to the geometry and impurity implantations of the NMOS transistor MN 1  of  FIG. 2 . 
         [0051]    The second differential amplifier  243  compares the second reference voltage V REF2  and the feedback voltage V FB  voltage. The voltage level of the output of the second differential amplifier  243  causes the PMOS transistor P 2  to steal current from the fifth current source I 5  that sinks a maximum negative reference current I MAX− . The maximum negative reference current I MAX−  sets the maximum negative current limit possible. The current mirror formed by the PMOS transistors P 3  and P 4  then mirrors the remaining current through the dummy NMOS transistor N 4 . In various embodiments, a sixth current source I 6  provides a fixed minimum current that may optionally be necessary. The output reference voltage V LIM−  is applied to the input of the pulse width modulation/pulse frequency modulation control circuit  245 . 
         [0052]    The reference voltage V LIM+  and reference voltage V LIM−  are compared in the comparators  247  and  249  with the voltage V LX  developed at the connection of the drains of the PMOS transistor MP 1  and the NMOS transistor MN 1  with the first terminal of the inductor L 1  during the corresponding part of the duty cycle to determine when the output current is too high. The results of the comparison of the reference voltage V LIM+  and reference voltage V LIM−  with the voltage V LX  are applied to the control logic circuit  246  to generate the reset signals V RST+  and V RST−  that are transferred respectively to the reset terminals R of the first data flip-flop  227  and the second data flip-flop  229 . 
         [0053]    As noted above, the output of the first driver circuit  230   a  controls the gate of the PMOS transistor MP 1  and the output of the second driver circuit  230   b  controls the gate of the NMOS transistor MN 1 . The input of the driver circuit  230   a  is controlled by the output of the first data flip-flop  227  and the input of the driver circuit  230   b  is controlled by the second data flip-flop  229 . If the first control signal  216  or the second control signal  218  as applied to the data inputs of the first data flip-flop  227  and the input of the second data flip-flop  229  are active at the receipt of the triggering edge of the clock pulse signal  252 , the output of the first data flip-flop  227  and the output of the second data flip-flop  229  turn on the corresponding PMOS transistor MP 1  or NMOS transistor MN 1 . The activated PMOS transistor MP 1  or NMOS transistor MN 1  is then turned off by the corresponding reset signals V RST+  and V RST− . 
         [0054]    As noted above, the control logic circuit  246  has circuitry that will permit the reset signals V RST+  and V RST−  to turn on the either the PMOS transistor MP 1  or the NMOS transistor MN 1 , as required. In some embodiments, the second comparator  219  is offset by approximately 10 mV as determined by the second reference voltage V ref2  to allow a small range of output voltages for which the PMOS transistor MP 1  or NMOS transistor MN 1  are not switched to provide a saving in power for very low loads. 
         [0055]      FIG. 5  is a schematic of a DC-to-DC converter with a dynamic sleep mode embodying the principals of the present disclosure. In various embodiments, the switch control circuit  305  has a digital-to-analog converter  310  that receives a reference control word  314 . The digital-to-analog converter  310  converts the reference control word  314  to the reference voltage V REF . The reference voltage V REF  is one of the two inputs to the feedback stage  315 . The feedback stage  315  has a first comparator  317  and a differential amplifier  319  that receive the reference voltage V REF . The second input  307  of the feedback stage  315  receives the feedback voltage V FB  that is compared to the reference voltage V REF . As described previously, the feedback voltage V FB  is developed from the output voltage V OUT  at common connection of the second terminal of the inductor L 1  and the first terminal of the output capacitor C OUT  of the filter section  235 . 
         [0056]    The output  316  of the first comparator  317  is the first input to the switching control circuit  325 . The first comparator  317  provides the positive control signal V UNDER+  that is applied to a data input of a first data flip-flop  326  of the switching control circuit  325 . The output  318  of the differential amplifier  319  provides a current control signal that is applied to a differential current source I 7 . The differential current source I 7  develops a reference limit current I LIM . The sense circuit  340  provides a load for the differential current source I 7  and thus the current limit flag signal V ILIMFLG . 
         [0057]    The current control signal from the output  318  of the differential amplifier  319  adjusts the differential current source I 7  such that the voltage levels are such that the data input of the second data flip-flop  328  of the switching control circuit  325  are at the correct logic levels for controlling the switching of the NMOS transistor MN 1 . 
         [0058]    An oscillator  350  generates the clock pulse signal  352  that is applied to the clock CK input of the first data flip-flop  326  and the second data flip-flop  328 . The output of the first data flip-flop  326  is applied to the input of the positive driver circuit  330   a  and the output of the second data flip-flop  329  is applied to the input of the negative driver circuit  330   b . The output of the first driver circuit  330   a  is applied to the gate of the PMOS transistor MP 1  and the output of the second driver circuit  330   b  is applied to the gate of the NMOS transistor MN 1 . 
         [0059]    The source of the PMOS transistor MP 1  is connected to the power supply voltage source VDD and the source of the NMOS transistor MN 1  is connected to the substrate supply voltage source VSS. The substrate supply voltage source VSS is often the ground reference voltage source, but in some applications is a negative voltage level. The commonly connected drains of the PMOS transistor MP 1  and the NMOS transistor MN 1  are connected to an input terminal of the filter section  235 . The input terminal is a first terminal of an inductor L 1 . The data output of the first data flip-flop  326  is applied to the driver circuit  330   a  and the data output of the second data flip-flop  327  is applied to the driver circuit  330   b . When states of the first flip-flop  326  and the second flip-flop  327  are such that the PMOS transistor MP 1  is turned on and the NMOS transistor MN 1  is turned off, a current from the power supply voltage source VDD from the first terminal of the inductor L 1  out the second terminal of the inductor L 1  into the first terminal of the output capacitor C OUT  and to the substrate supply voltage source VSS. The output voltage V OUT  is present at the junction of the second terminal of the inductor L 1  and the output capacitor C OUT . 
         [0060]    In the dynamic sleep mode, the reference limit current I LIM  from the differential current source I 7  is allowed to vary and thus enable the DC-to-DC converter to support very high loads. The sense circuit  340  senses the output current I OUT  when the PMOS transistor MP 1  is turned on. The sense circuit  340  generates a sense current I SENSE  produces a current proportional to the current in the PMOS transistor MP 1 . The sense current I SENSE  is compared to the reference limit current I LIM . When the sense current I SENSE  from sense circuit  340  is greater than the reference limit current I LIM  then the voltage on current limit flag signal V ILIMFLG  assumes a first logic level (1). When the sense current I SENSE  from sense circuit  340  is less than the reference limit current I LIM  then the voltage on current limit flag signal V ILIMFLG  assumes a second logic level (0). 
         [0061]    When the sense current I SENSE  is greater than the reference limit current I LIM , the current limit flag signal V ILIMFLG  indicates that current limit is achieved and the control circuit  328  generates the data applied to the input of the first flip-flop  326  that will force the first driver circuit  330   a  to turnoff the PMOS transistor MP 1 . The reference limit current I LIM  is modulated by the output voltage of the differential amplifier  319  as a result of the comparison of the feedback voltage V FB  with the reference voltage V REF . As the feedback voltage V FB  falls below the reference voltage V REF , the reference current is increased, and so the current limit value is also increased. 
         [0062]      FIG. 6  is a plot of the waveforms of the signals the DC-to-DC converter in dynamic sleep mode operation of  FIG. 5 . When the feedback voltage V FB  falls below the reference voltage V REF  from digital-to-analog converter  310 , the output of the first comparator  317  rises from the second level (0) to the first level (1) at the time τ 0  to activate the positive control signal V UNDER+ . The first level (1) is applied through the control circuit  328  to the first data flip-flop  326 . The data present at the data input D of the first data flip-flop  326  is not transferred to the output of the first data flip-flop  326  until the rising edge of the clock CLK at the time τ 1  at which time the gate of the PMOS transistor MP 1  is brought to the first level (0) to turn on the PMOS transistor MP 1  such that current I COIL  passes to the first terminal of the inductor L 1 . 
         [0063]    The current I COIL  through the inductor L 1  rises from the time τ 1  to the time τ 2  when the current I COIL  reaches the magnitude of the reference limit current I LIM . The voltage of the current limit flag signal V ILIMFLG , developed at the top of the differential current source I 7  is applied to the control circuit  328  and the control circuit  328  sets the data at the data inputs D of the first and second data flip-flops  326  and  327  such that the PMOS transistor MP 1  and the NMOS transistor MN 1  are turned off. With the PMOS transistor MP 1  and the NMOS transistor MN 1  are turned off, the current I COIL  falls toward zero and the DC-to-DC converter operates in the discontinuous mode. When the current I COIL  falls sufficiently less than the reference limit current I LIM , the voltage of the current limit flag signal I LIMFLG  is deactivated to essentially the first level (0) at the time τ 1 . 
         [0064]    In some embodiments as shown in  FIG. 5 , the limit current I LIM  is controlled by the sum of two reference currents. The first reference current is provided by the adjustable differential current source I 7 , as described above. The second reference current is fixed ramp current source I 8 . The reference limit current I LIM  of the adjustable differential current source I 7  and the compensation current I COMP  of the fixed ramp current source I 8  are additively combined to provide a degree of compensation to prevent sub-harmonic oscillation. The ramp waveform of the compensation current I COMP  should start at a high value and have a negative slope. In some embodiments, the compensation current I COMP  has a negative value thus subtracting current from differential current source I 7 . 
         [0065]      FIG. 7  is a plot of the waveforms of the signals the DC-to-DC converter of  FIG. 5  in dynamic sleep mode operation illustrating a change in output current I OUT  to the external load circuit. When the output current I OUT  increases at the time τ 0 , the feedback voltage V FB  starts to fall until it is below the below the reference voltage V REF  from digital-to-analog converter  310 , the output of the first comparator  317  rises at the time τ 1  from the second logic level (0) to the first logic level (1) to activate the positive control signal V UNDER+ . The first logic level (1) is applied through the control circuit  328  to the first data flip-flop  326 . The data present at the data input D of the first data flip-flop  326  is not transferred to the output of the first data flip-flop  326  until the rising edge of the clock CLK at the time τ 2  at which time the gate of the PMOS transistor MP 1  is brought to the first level (0) to turn on the PMOS transistor MP 1  such that current I COIL  passes to the first terminal of the inductor L 1 . 
         [0066]    The current I COIL  through the inductor L 1  rises from the time τ 2  to the time τ 3  when the coil current I COIL  reaches the magnitude of the reference limit current I LIM1 . The voltage of the current limit flag signal V ILIMFLG , developed at the top of the differential current source I 7  is applied at the time τ 3  to the control circuit  328  and the control circuit  328  sets the data at the data inputs D of the first and second data flip-flops  326  and  327  such that the PMOS transistor MP 1  and the NMOS transistor MN 1  are turned off. With the PMOS transistor MP 1  and the NMOS transistor MN 1  are turned off, the current I COIL  falls toward zero from the time τ 3  to the time τ 4  and the DC-to-DC converter operates in the discontinuous mode. When the current I COIL  falls sufficiently less than the first reference limit current I LIM1 , the voltage of the current limit flag signal V ILIMFLG  is deactivated to essentially the first level (0) shortly after the time τ 3 . 
         [0067]    The feedback voltage V FB  has also decreased from the time τ 3  to the time τ 4  and remains less than the reference voltage V REF  such that at the time τ 4 , the gate of the PMOS transistor MP 1  is activated with the rising edge of the clock pulse CLK. The coil current I COIL  begins to rise between the time τ 4  and the time τ 5 . In the time between the time τ 4  and the time τ 5 , the first reference limit current I LIM1  from the differential current source I 7  is adjusted by the differential voltage ΔV from the differential amplifier  319  to a second reference limit current I LIM2 . When the coil current I COIL  reaches the level of the second reference limit current I LIM2 , the current limit flag signal V ILIMFLG  is activated shortly before the time τ 5 . The gate of the PMOS transistor MP 1  is set to the first logic level (1) and the PMOS transistor MP 1  is turned off at the time at the time τ 5 . When the current I COIL  falls sufficiently less than the second reference limit current I LIM2 , the voltage of the current limit flag signal V ILIMFLG  is deactivated to essentially the second level (0) shortly after the time τ 5 . The coil current I COIL  falls between the time τ 5  and the time τ 6  such that the feedback voltage V FB  is decreasing from the time τ 5  to the time τ 6  and remains less than the reference voltage V REF  such that at the time τ 6  gate of the PMOS transistor MP 1  is activated with the rising edge of the clock pulse CLK. 
         [0068]    The cyclic operation from the time τ 4  to the time τ 12  is equivalent to that described between the time τ 4  and the time τ 6 . This process continues until the output current I OUT  decreases the normal dynamic sleep mode or the system commands the DC-to-DC converter to resume the normal continuous operation mode. 
         [0069]      FIG. 8  is flowchart of a method for providing hysteretic mode control within a DC-to-DC converter  200  of  FIG. 2 . The most positive voltage limit V ILM+  representing a maximum current I LIM+  to pass through the inductor L 1  of the low pass filter section  235  is determined (Box  400 ). Similarly, the most negative voltage limit V ILM−  representing a minimum current I LIM−  to pass through the inductor L 1  of the low pass filter section  235  is determined (Box  405 ). The voltage V LX  present at the junction of the drains of the PMOS transistor MP 1  and the NMOS transistor MN 1  with the first terminal of the inductor L 1  is compared (Box  405 ) with the positive voltage limit V ILM+ . If the voltage V LX  is greater than or equal to the positive voltage limit V ILM+ , the first data flip-flop  227  is reset (Box  405 ) and the PMOS transistor MP 1  is turned off. The voltage V LX  is compared (Box  430 ) with the negative voltage limit V ILM− . If the voltage V LX  is not greater than or equal to the negative voltage limit V ILM− , the NMOS transistor MN 1  is turned on (Box  445 ). The operational mode of the DC-to-DC converter  200  is queried (Box  450 ) to determine if the dynamic sleep mode is to be terminated and the normal continuous operational mode resumed. 
         [0070]    If the dynamic sleep mode is to be continued, the process then returns to the comparing (Box  405 ) of the voltage V LX  with the positive voltage limit V ILM+ . If, this instance, the voltage V LX  is not greater than or equal to the positive voltage limit V ILM+ , the PMOS transistor MP 1  is turned on. The voltage V LX  is compared (Box  430 ) with the negative voltage limit V ILM− . If the voltage V LX  is greater than or equal to the negative voltage limit V ILM− , the data flip-flop  229  is reset (Box  435 ) and the NMOS transistor MN 1  is turned off (Box  440 ). The operational mode of the DC-to-DC converter  200  is again queried (Box  450 ) to determine if the dynamic sleep mode is to be terminated and the normal continuous operational mode resumed. If the normal continuous operational mode is to be resumed the process is ended. If the dynamic sleep mode is to be continued, the process as above described, continues. 
         [0071]      FIG. 9  is flowchart of a method for providing hysteretic mode control within a DC-to-DC converter  300  of  FIG. 5 . When the DC-to-DC converter  300  is set to begin (Box  500 ) the dynamic sleep mode, the voltage reference V ref  and the feedback voltage V FB  are compared (Box  505 ) to determine the positive control signal V UNDER+ . The differential ΔV between the voltage reference V ref  and the feedback voltage V FB  is amplified (Box  510 ) and then converted (Box  515 ) to a differential current ΔV. The limiting current I LIM  is set (Box  520 ) as the subtractive combination of the sense current I SENSE  and the differential current ΔV. The limiting current I LIM  determines (Box  525 ) a current limit flag signal V ILIMFLG . 
         [0072]    From the positive control signal V UNDER+  and the current limit flag signal V ILIMFLG , the state of the voltage to be applied to the gate of the PMOS transistor MP 1  and the gate of the NMOS transistor MN 1  are determined (Box  530 ). The states of the voltage applied to the gate of the PMOS transistor MP 1  and the gate of the NMOS transistor MN 1  may be such that either the PMOS transistor MP 1  is turned on and the NMOS transistor MN 1  is turned off, or the PMOS transistor MP 1  is turned off and the NMOS transistor MN 1  is turned on, or the PMOS transistor MP 1  is turned off and the NMOS transistor MN 1  is turned off. The state of the gate of the PMOS transistor MP 1  is examined (Box  535 ) to determine if the PMOS transistor MP 1  is turned on. The NMOS transistor MN 1  is turned off (Box  540 ) and the PMOS transistor MP 1  is turned on (Box  545 ), if the state of the gate of the PMOS transistor MP 1  indicates the PMOS transistor MP 1  is to be turned on. If the state of the gate of the PMOS transistor MP 1  indicates the PMOS transistor MP 1  is to be turned off, the PMOS transistor MP 1  is turned off (Box  545 ) and the state of the gate of the NMOS transistor MN 1  is examined (Box  555 ) to determine if the NMOS transistor MN 1  is turned on. The NMOS transistor MN 1  is turned on (Box  560 ), if the state of the gate of the NMOS transistor MN 1  indicates the NMOS transistor MN 1  is to be turned on. If the state of the gate of the NMOS transistor MN 1  indicates the NMOS transistor MN 1  is to be turned off, the NMOS transistor MN 1  is turned off (Box  565 ). If the PMOS transistor MP 1  is turned on (Box  545 ) or the NMOS transistor MN 1  is turned on (Box  560 ), or the PMOS transistor MP 1  is turned off (Box  550 ) and NMOS transistor MN 1  is turned off (Box  565 ), the sleep mode is examined (Box  570 ) to determine if the continuous mode is to be resumed. If the sleep mode is to be continue, the next cycle is started  500  and the process as described above is repeated. If the sleep mode is to be discontinued, the continuous mode is resumed and the dynamic sleep mode is ended. 
         [0073]    While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure.