Abstract:
A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller&#39;s techniques for entering synchronous burst read mode. In some embodiments, the bit may selectively enable the memory to assume one of two synchronous burst read modes which are based on different arrangements of CLK and ADV# signals.

Description:
BACKGROUND 
     This relates generally to asynchronous memories and to latching in asynchronous memories. 
     An asynchronous memory, such as a flash memory, may have an asynchronous page mode and a synchronous burst mode for reading. These modes can accelerate flash reads. Flash read performance enables direct code execution from the flash memory. 
     The asynchronous page mode is an asynchronous read operation that improves read performance. On power up or reset, the memory defaults to asynchronous read array mode to enable processors to immediately read from the flash memory. Page mode may also be available. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit schematic for embodiment of the present invention; 
         FIG. 2  is a timing diagram showing the pertinent signals in one mode of burst transfer; 
         FIG. 3  is a timing diagram for another mode of burst transfer; and 
         FIG. 4  is a flow chart for one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , many processors and chipsets use an integrated memory controller  12  to access an external memory device  14 , such as a flash memory. A memory bus provides a hardware connection between the memory controller  12  and external memory device  14 . The memory bus may include address (ADD), data, and control signals (CE#, ADV#, OE, and CLK). The address signals specify the location for writing or reading data during memory access, while data signals transfer information to and from the selected memory device. Control signals are driven by the memory controller  12  to select a particular device and indicate the direction of data transfer. 
     Synchronous burst mode may use a clock synchronous read operation to improve the read performance for single reads and page mode reads. It may be enabled by programming a read configuration register of the memory device. 
     Generally, synchronous burst mode provides higher read performance because data is output on clock edges at the clock frequency. The synchronous burst mode uses a signal CLK that is the burst clock input used to synchronize the memory device  14  to the memory controller  12 . ADV# is the address valid input to the memory indicating when the address from the processor is valid. ADV# is used by the memory  14  to latch the initial address at the beginning of the burst access. 
     At the start of a synchronous burst access, the memory controller  12  may drive an initial address (ADD) onto the address buffer and assert CE#, ADV#, and output enable OE#. ADV# is deasserted to latch the initial address. 
     The memory controller  12  and the flash memory  14  may be separate devices packaged separately or may be packaged in the same device. The memory controller may be a processor or part of a processor in some embodiments. 
     In accordance with some embodiments, the memory controller  12  may select a configuration for synchronous burst reads by providing a signal CR to a read state machine  18   b . This signal selects one of two selectable burst mode read configurations. 
     The memory  14  may include an array  22  of flash memory devices coupled to the read state machine  18   b  and an output state machine  18   a . Address buffers  16  read the address signals ADD from the memory controller  12 . The memory controller  12  also supplies the signal ADV# to the output state machine  18   a , the clock signal CLK  26  to the output state machine  18   a , the chip enable signal CE# to the output state machine  18   a  and the output buffers  28 . The memory controller  12  may receive a signal from a wait module  30  that is coupled to the output buffers  28 . A system bus  32  receives the output from the memory  14 . 
     Referring to  FIG. 4 , in accordance with some embodiments of the present invention, a sequence  34  may selectively implement one of two different synchronous burst read modes. These synchronous burst read modes may be selected by the memory controller  12  using the signal CR to select a bit within the read state machine  18   b . The synchronous burst read mode selection sequence  34  may be implemented in hardware, software, or firmware. 
     Initially, a configuration register bit, for example in the read state machine  18   b , may be set or reset by the controller  12 , as indicated in diamond  36 . A check at diamond  36  determines whether the configuration bit is set or reset. If it is set, then the synchronous burst mode is enabled on the falling ADV# and falling clock CLK signals, as indicated in block  38 . The mode is latched on the CLK rising edge with ADV# low, as indicated in block  40 . 
     Alternatively, if the configuration bit is not set by the controller  12 , then the synchronous burst read mode is enabled on the falling ADV# and rising CLK signal, as indicated in block  42 . Then, the latency count is initiated and the circuit latches on the rising CLK signal with burst read enabled, as indicated in block  44 . 
     Some flash products have adopted an address latching mechanism called ADV#-or-CLK. In this mechanism, addresses are latched by the first of either the rising ADV# edge or the next valid CLK edge with ADV# low. This mechanism has set up and hold issues at high clock frequencies. The problem is emphasized by some memory controllers that generate critical timing issues. One critical timing issue occurs when ADV# and CLK# are synchronous and, particularly, when the falling edge of ADV# is synchronous with the rising edge of CLK. 
     In accordance with embodiments of the present invention, the memory  14  may be configured to optimize the communication channel between the memory controller  12  and the memory  14 , reducing the critical timing issues and allowing higher maximum frequencies. The synchronous burst read mode is enabled with the first falling CLK edge and the ADV# low and the addresses are latched on the first CLK rising edge with burst enable. A latency counter starts on the first CLK rising edge with burst enable. 
     A first type of memory controller selects a synchronous burst read by synchronizing the falling edge of ADV# with the falling edge of CLK, keeping for example, ADV# low for one clock cycle. The second type of memory controller selects the synchronous burst enable by synchronizing the falling edge of ADV# with the rising edge of CLK, keeping the ADV#, for example low, for one clock cycle. Thus, a different configuration bit may be set by the memory controller depending on memory controller type. 
     A memory controller sets this bit by providing the signal CR to the read state machine  18   b . With the first configuration, ADV# set up and hold timing requirements, with respect to CLK, are met. The addresses are latched on the first CLK rising edge with ADV# low, as shown in  FIG. 1 . The latency counter starts on the first CLK rising edge with ADV# low. 
     With the first configuration, shown in  FIG. 2 , the ADV# set up and hold timing, with respect to CLK, are met. The address is latched on the first CLK rising edge with the ADV# low, as indicated at B in  FIG. 2 . The latency counter starts in the first CLK rising edge with ADV# low, as indicated at B. 
     With the second configuration, shown in  FIG. 3 , ADV# set up and hold timing, with respect to CLK, is critical. The synchronous burst read is enabled with the first falling CLK edge with ADV# low. The addresses latched on the first CLK rising edge would burst enable. The latency counter starts on the first CLK rising edge with burst enabled. 
     As shown in  FIG. 3 , the addresses are latched at B. The latency count starts at B, namely, at the first rising CLK edge after ADV# is sampled low on the falling edge indicated at A. Note that in both configurations, ADV# is no longer a latching signal. The latching signal is, instead, the rising clock edge CLK. 
     References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application. 
     While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.