Abstract:
In a semiconductor memory device constructed a memory cell array including a plurality of read-only memory cells connected to a plurality of bit lines, a plurality of sense amplifiers each including a first MOS trnasistor connected to one of the bit lines, a reference voltage generating circuit for applying a reference voltage to a gate of the first MOS transistor, and a bit line selection circuit, for generating a plurality of bit line selection signals for selecting the bit lines respectively, a plurality of second MOS trnasistors, each of which is connected between one of the bit lines and the ground terminal, is provided. Also, a plurality of inverters, are connected between the bit line selection circuit and the second MOS transistors, so that the second MOS transistors are controlled by inverted signals of the bit line selection signals.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device including read-only memory (ROM) cells, and more particularly to the improvement of the read operation speed thereof. 
     2. Description of the Related Art 
     A prior art semiconductor memory device is constructed by a memory cell array including a plurality of ROM cells connected to a plurality of bit lines, a plurality of sense amplifiers each including a MOS transistor connected to one of the bit lines, a reference volatage generating circuit for applying a reference voltage to a gate of the MOS transistor, and a bit line selection circuit for generating a plurality of bit line selection signals for selecting the respective bit lines. 
     In the above-described prior art ROM device, however, the reference voltage may be decreased due to the capacitive coupling of the gate and source (drain) of the MOS transistor. As a result, the speed of the read operation is decreased. This will be explained later in detail 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to suppress the reduction of the speed of the read operation of a semiconductor memory device including ROM cells. 
     According to the present invention, in a semiconductor memory device constructed by a memory cell array including a plurality of ROM cells connected to a plurality of bit lines, a plurality of sense amplifiers each including a first MOS transistor connected to one of the bit lines, a reference voltage generating circuit for applying a reference voltage to a gate of the first MOS transistor, and a bit line selection circuit for generating a plurality of bit line selection signals for selecting the bit lines respectively, a plurality of second MOS transistors, each of which is connected between one of the bit lines and the ground terminal, is provided. Also, a plurality of inverters are connected between the bit line selection circuit and the second MOS transistors, so that the second MOS transistors are controlled by inverted signals of the bit line selection signals. 
     Thus, only one selected bit line is precharged while the other non-selected bit lines are decreased to ground or remain at ground. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram illustrating a prior art ROM device; 
     FIG. 2 is a timing diagram showing the operation of the device of FIG. 1; 
     FIG. 3 is a circuit diagram illustrating a first embodiment of the ROM device according to the present invention; 
     FIG. 4 is a timing diagram showing the operation of the device of FIG. 3; 
     FIG. 5 is a circuit diagram illustrating a second embodiment of the ROM device according to the present invention; 
     FIG. 6 is a timing diagram showing the operation of the device of FIG. 5; and 
     FIGS. 7A,  7 B,  7 C and  7 D are circuit diagrams of modifications of the memory cell array of FIGS.  3  and  5 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiments, a prior art ROM device will be explained with reference to FIGS. 1 and 2. 
     In. FIG. 1, reference numeral  1  designates a memory cell array  2 - 1 ,  2 - 2  . . . designate sense amplifiers, and  3  designates a reference voltage generating circuit. 
     The memory cell array  1  is formed by nonvolatile memory cells MC 11 , MC 12,  . . . MC 21,  MC 22,  . . . , each having a source connected to the ground terminal GND, a drain connected to one of bit lines BL 1 , BL 2,  . . . , a floating gate, a control gate connected to one of word lines WL 1 , WL 2,  . . . . For example, a threshold voltage of one memory cell is 6V for data “0”, and a threshold voltage of one memory cell is 2V for data “ 1 ”. 
     One of X address signals X 1 , X 2 , . . . is made high by a row decoder DECX, and therefore, one of the word lines WL 1 , WL 2,  . . . , is selected. In this case, the voltage at a selected word line is 4V, and the voltage at non-selected word lines is 0V. Simultaneously, one of Y address signals Y 1 , Y 2 , . . . is made high by a column decoder DECY, and therefore, one of the bit lines BL 1,  BL 2,  . . . is selected by the sense amplifiers  2 - 1 ,  2 - 2 , . . . . Thus, data is read from a selected memory cell. 
     The sense amplifier  2 - 1  ( 2 - 2 , . . . ) is constructed by a NAND circuit  211  ( 221 , . . . ) for receiving the Y address signal Y 1  (Y 2 , . . . ) and a precharge signal PRC, a P-channel MOS transistor  212  ( 222 , . . . ) having a source connected to a power supply terminal V DD  and a gate connected to the output terminal of the NAND circuit  211  ( 221 , . . . ), an N-channel MOS transistor  213  connected between the drain of the P-channel MOS transistor  212  ( 222 , . . . ) and the bit line BL 1  (BL 2 , . . . ), and an inverter  214  ( 224 , . . . ) connected to the drains of the transistors  212  ( 222 , . . . ) and  213  ( 223 , . . . ) for generating a sense amplifier output signal S 1  (S 2,  . . . ). Also, a reference voltage V REF  is applied by the reference voltage generating circuit  3  to the gates of the transistors  213 ,  223 , . . . . Note that the precharge signal PRC is generated from a control circuit CONT. 
     The reference voltage generating circuit  3  is constructed by a P-channel MOS transistor  301  having a grounded gate and two drain-gate-connected N-channel MOS transistors  302  and  303 . In this case, the ON-resistance value of the P-channel MOS transistor  301  is sufficiently large. Also, if the threshold voltage V thn  of the N-channel MOS transistors  302  and  303  is given by 0.7V, the reference voltage V REF  is 
     
       
           V   REF =2· V   thn =1.4  V    
       
     
     The operation of the device of FIG. 1 is explained next with reference to FIG.  2 . Here assume that the memory cells MC 11  and MC 12  store data “ 0 ”, and the memory cells MC 21  and MC 22  store data “ 1 ”. 
     A read operation for the memory cell MC 11  is carried out from time t 1  to time t 3 . 
     First, at time t 1 , in order to perform a precharging operation upon the bit line BL 1 , the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made high (=V DD ) and low (=GND), respectively. As a result, the voltage at the node N 1  of the NAND circuit  211  becomes low while the voltage at the node N 2  of the NAND circuit  221  remains high. Therefore, the transistors  212  and  222  are turned ON and OFF, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2V thn ), the bit line BL 1  is precharged to V REF −V thn , while the voltage at the bit line BL 2  remains low. 
     Next, at time t 2 , in order to preform a data sampling operation upon the memory cell MC 11,  the X address signal X 1  is made high to select the word line WL 1,  while the X address signal X 2  remains low. In this case, since the memory cell MC 11  stores data “ 0 ”, the memory cell MC 11  remains in an OFF state, so that the voltages at the bit lines BL 1  and BL 2  remain high (=V REF −V thn ) and low, respectively. As a result, the sense amplifier output signal S 1  shows low (=data “ 0 ”). 
     A read operation for the memory cell MC 12  is carried out next from time t 3  to time t 5 . 
     At time t 3 , in order to perform a precharging operation upon the bit line BL 2,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made low (=GND) and high (=V DD ), respectively. As a result, the voltage at the node N 2  of the NAND circuit  221  becomes low while the voltage at the node N 1  of the NAND circuit  211  remains high. Therefore, the transistors  212  and  222  are turned OFF and ON, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2V thn ), the bit line BL 2  is precharged to V REF −V thn , while the voltage at the bit line BL 1  remains high (=V REF −V thn ). 
     Next, at time t 4 , in order to perform a data sampling operation upon the memory cell MC 12,  the X address signal X 1  is made high to select the word line WL 1,  while the X address signal X 2  remains low. In this case, since the memory cell MC 12  stores data “ 0 ”, the memory cell MC 12  remains in OFF state, so that the voltages at the bit lines BL 1  and BL 2  both remain high (=V REF −V thn ). As a result, the sense amplifier output signal S 2  shows low (=data “ 0 ”). 
     A read operation for the memory cell MC 21  is carried out next from time t 5  to time t 7 . 
     At time t 5 , in order to perform a precharging operation upon the bit line BL 1,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made high (=V DD ) and low (=GND), respectively. As a result, the voltage at the node N 1  of the NAND circuit  211  becomes low while the voltage at the node N 2  of the NAND circuit  221  remains high. Therefore, the transistors  212  and  222  are turned ON and OFF, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . Also, the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2V thn ). In this case, the voltages at the bit lines BL 1  and BL 2  both remain at V REF −V thn . 
     Next, at time t 6 , in order to perform a data sampling operation upon the memory cell MC 21,  the X address signal X 2  is made high to select the word line WL 2,  while the X address signal X 1  remains low. In this case, since the memory cell MC 21  stores data “ 1 ”, the memory cell MC 21  is turned ON, so that the voltage at the bit line BL 1  becomes low. As a result, the sense amplifier output signal S 1  shows high (=data “ 1 ”). 
     In the above-mentioned state, since the memory cell MC 22  also stores data “ 1 ”, the memory cell MC 22  is also turned ON, so that the voltage at the bit line BL 2  also becomes low. That is, when the voltages at the bit lines BL 1  and BL 2  are simultaneously decreased, the reference voltage V REF  is also decreased due to the capacitive coupling of the gate and source (drain) of each of the transistors  213  and  223  as indicated by C 1  and C 2  in FIG.  1 . 
     Note that the greater the number of bit lines whose voltages are simultaneously decreased, the lower the reference voltage V REF.  When the reference voltage V REF  is made lower, the reference voltage V REF  is gradually increased as indicated in FIG.  2 , since the ON-resistance of the transistor  301  is relatively large. 
     A read operation for the memory cell MC 22  is carried out next from time t 7  to time t 9 . 
     At time t 7 , in order to perform a precharging operation upon the bit line BL 2,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made low (=GND) and high (=V DD ), respectively. As a result, the voltage at the node N 2  of the NAND circuit  221  becomes low while the voltage at the node N 1  of the NAND circuit  211  remains high. Therefore, the transistors  212  and  222  are turned OFF and ON, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . In this case, since the transistors  213  and  223  are in an incomplete ON state by the low reference voltage V REF , the bit line BL 2  is gradually precharged to V REF −V thn , while the voltage at the bit line BL 1  remains low. 
     Next, at time t 8 , in order to perform a data sampling operation upon the memory cell MC 22,  the X address signal X 2  is made high to select the word line WL 2,  while the X address signal X 1  remains low. In this case, since the memory cell MC 22  stores data “ 1 ”, the memory cell MC 22  is turned ON, so that the voltage at the bit lines BL 2  becomes low. As a result, the sense amplifier output signal S 2  shows high (=data “ 1 ”). 
     In the above-mentioned state where the reference voltage V REF  is lower than 2·V thn , if a memory cell storing data “ 1 ” needs to be read, the speed of the read operation for such a memory cell is decreased, since the ON resistance of the transistor  213  ( 223 ) is high so that the voltage at the precharged input of the inveter  214  ( 224 ) is hard to fall. 
     Thus, in the device of FIG. 1, the reference voltage V REF  is made lower to decrease the speed of the read operation. 
     In FIG. 3, which illustrates a first embodiment of the present invention, a pull down circuit  4  is added to the elements of FIG.  1 . That is, the pull down circuit  4  is constructed by N-channel MOS transistors  411 ,  421 , . . . . Each of the transistors  411 ,  421 , . . . has a drain connected to one of the bit lines BL 1,  BL 2  . . . , a source connected to the ground terminal GND, and a gate for receiving one of the Y address signals Y 1 , Y 2 , . . . , via inverters one of  412 ,  422 , . . . . 
     The operation of the device of FIG. 3 is explained next with reference to FIG.  4 . Here assume that the memory cells MC 11  and MC 12  store data “ 0 ”, and the memory cells MC 21  and MC 22  store data “ 1 ”. 
     A read operation for the memory cell MC 11  is carried out from time t 1  to time t 3 . 
     First, at time t 1 , in order to perform a precharging operation upon the bit line BL 1,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made high (=V DD ) and low (=GND), respectively. As a result, the voltage at the node N 1  of the NAND circuit  211  becomes low while the voltage at the node N 2  of the NAND circuit  221  remains high. Therefore, the transistors  212  and  222  are turned ON and OFF, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . On the other hand, the signals {overscore (Y 1 )} and {overscore (Y 2 )} are made low and high, respectively, so that the transistors  411  and  421  are turned OFF and ON, respectively. In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2V thn ), the bit line BL 1  is precharged to V REF −V thn , while the voltage at the bit line BL 2  remains low. 
     Next, at time t 2 , in order to perform a data sampling operation upon the memory cell MC 11,  the X address signal X 1  is made high to select the word line WL 1,  while the X address signal X 2  remains low. In this case, since the memory cell MC 11  stores data “ 0 ”, the memory cell MC 11  remains in on OFF state, so that the voltages at the bit lines BL 1  and BL 2  remain high (=V REF −V thn ) and low, respectively. As a result, the sense amplifier output signal S 1  shows low (=data “ 0 ”). 
     A read operation for the memory cell MC 12  is carried out next from time t 3  to time t 5 . 
     At time t 3 , in order to perform a precharging operation upon the bit line BL 2,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made low (=GND) and high (=V DD ), respectively. As a result, the voltage at the node N 2  of the NAND circuit  221  becomes low while the voltage at the node N 1  of the NAND circuit  211  remains high. Therefore, the transistors  212  and  222  are turned OFF and ON, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . On the other hand, the signals {overscore (Y 1 )} and {overscore (Y 2 )} are made high and low, respectively, so that the transistors  411  and  421  are turned ON and OFF, respectively. In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2V thn ), the bit line BL 2  is precharged to V REF −V thn , while the voltage at the bit line BL 1  remains low. 
     Next, at time t 4 , in order to perform a data sampling operation upon the memory cell MC 12,  the X address signal X 1  is made high to select the word line WL 1,  while the X address signal X 2  remains low. In this case, since the memory cell MC 12  stores data “ 0 ”, the memory cell MC 12  remains in an OFF state, so that the voltages at the bit lines BL 1  and BL 2  remain low and high (=V REF −V thn ), respectively. As a result, the sense amplifier output signal S 2  shows low (=data “ 0 ”). 
     A read operation for the memory cell MC 21  is carried out next from time t 5  to time t 7 . 
     At time t 5 , in order to perform a precharging operation upon the bit line BL 1,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made high (=V DD ) and low (=GND), respectively. As a result, the voltage at the node N 1  of the NAND circuit  211  becomes low while the voltage at the node N 2  of the NAND circuit  221  remains high. Therefore, the transistors  212  and  222  are turned ON and OFF, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . On the other hand, the signals {overscore (Y 1 )} and {overscore (Y 2 )} are made low and high, respectively, so that the transistors  411  and  421  are turned OFF and ON, respectively. In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2V thn ), the bit line BL 1  is precharged to V REF −V thn , while the voltage at the bit line BL 2  remains low. 
     Next, at time t 6 , in order to perform a data sampling operation upon the memory cell MC 21,  the X address signal X 2  is made high to select the word line WL 2,  while the X address signal X 1  remains low. In this case, since the memory cell MC 21  stores data “ 1 ”, the memory cell MC 21  is turned ON, so that the voltage at the bit line BL 1  becomes low. As a result, the sense amplifier output signal S 1  shows high (=data “ 1 ”). 
     In the above-mentioned state, since the memory cell MC 22  also stores data “ 1 ”, the memory cell MC 22  is also turned ON. In this case, however, the voltage at the bit line BL 2  already becomes low. Therefore, even when the voltage at the bit line BL 1  is decreased, the reference voltage V REF  is not decreased due to the capacitive coupling of the gate and source (drain) of each the transistors  213  and  223 . 
     A read operation for the memory cell MC 22  is carried out next from time t 7  to time t 9 . 
     At time t 7 , in order to perform a precharging operation upon the bit line BL 2,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made low (=GND) and high (=V DD ), respectively. As a result, the voltage at the node N 2  of the NAND circuit  221  becomes low while the voltage at the node N 1  of the NAND circuit  211  remains high. Therefore, the transistors  212  and  222  are turned OFF and ON, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . On the other hand, the signals {overscore (Y 1 )} and {overscore (Y 2 )} are made high and low, respectively, so that the transistors  411  and  421  are turned ON and OFF, respectively. In this case, since the transistors  213  and  223  are in a ON state by the reference voltage V REF  (=2V thn ), the bit line BL 2  is precharged to V REF −V thn , while the voltage at the bit line BL 1  remains low. 
     Next, at time t 8 , in order to perform a data sampling operation upon the memory cell MC 22,  the X address signal X 2  is made high to select the word line WL 2,  while the X address signal X 1  remains low. In this case, since the memory cell MC 22  stores data “ 1 ”, the memory cell MC 22  is turned On, so that the voltage at the bit line BL 2  becomes low. As a result, the sense amplifier output signal S 2  shows high (=data “ 1 ”). 
     In the above-described first embodiment, during a precharging time period, only one selected bit line is precharged while the voltages at non-selected bit lines remain low (=GND). As a result, even when the voltage at the selected bit line falls from high to low at the beginning of a data sampling time period, the reduction of the reference voltage V REF  due to the capacitive coupling of the transistors  213 ,  223 , . . . hardly occurs, since the voltages at all the other non-selected bit lines do not change. Thus, the reduction of the speed of the read operation can be suppressed. 
     In FIG. 5, which illustrates a second embodiment of the present invention, the pull-down circuit  4  is modified to a pull-down circuit  4 ′ where NOR circuits  413 ,  423 , . . . are added to receive a data sense recognition signal SASTP. 
     The data sense recognition signal SASTP is generated by a data sense recognition signal generating circuit  5  formed by a delay circuit  501  and an OR circuit  502 . The delay circuit  501  has a long enough delay time τ to complete transmitssion of data from a selected memory cell to a corresponding bit line. In this case, the delay time τ is smaller than a data sampling time period. Also, the OR circuit  502  performs an OR logic operation upon the precharge signal PRC and a signal PRC′ from the delay circuit  501  to generate the data sense recognition signal SASTP. Note that the data sense recognition signal SASTP serves to substantially stop a data sampling period. 
     The operation of the device of FIG. 5 is explained next with reference to FIG.  6 . Here assume that the memory cells MC 11  and MC 12  store data “ 0 ”, and the memory cells MC 21 and MC   22  store data “ 1 ”. 
     As shown in FIG. 6, the delay circuit  501  delays the precharge signal PRC by the delay time τ to generate the signal PRC′. Also, the OR circuit  502  generates the data sense recognition signal SASTP which falls at times t 2 ′, t 4 ′, t 6 ′, t 8 ′, . . . and rises at times t 3 , t 5 , t 7 , t 9 , . . . . 
     A read operation for the memory cell MC 11  is carried out from time t 1  to time t 2 ′. 
     First, at time t 1 , in order to perform a precharging operation upon the bit line BL 1,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made high (=V DD ) and low (=GND), respectively. As a result, the voltage at the node N 1  of the NAND circuit  211  becomes low while the voltage at the node N 2  of the NAND circuit  221  remains high. Therefore, the transistors  212  and  2 Z 2  are turned ON and OFF, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . On the other hand, the signals {overscore (Y 1 )} and {overscore (Y 2 )} are made low and high, respectively; however, the data sense recognition signal SASTP is high, so that the transistors  411  and  421  are both turned OFF. In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2 V thn ), the bit line BL 1  is precharged to V REF −V thn , while the voltage at the bit line BL 2  remains low. 
     Next, at time t 2 , in order to preform a data sampling operation upon the memory cell MC 11,  the X address signal X 1  is made high to select the word line WL 1,  while the X address signal X 2  remains low. In this case, since the memory cell MC 11  stores data “ 0 ”, the memory cell MC 11  remains in an OFF state, so that the voltages at the bit lines BL 1  and BL 2  remain high (=V REF −V thn ) and low, respectively. As a result, the sense amplifier output signal S 1  shows low (=data “ 0 ”). 
     Next, at time t 2 ′, since the data sense recognition signal SASTP falls on the condition that the Y address signal Y 1  is high, the signal Y 1 ′ of the NOR circuit  413  is made high so that the transistor  411  is turned ON to discharge the bit line BL 1.  Thus, the data sampling period for the memory cell MC 11  is substantially completed before the next precharging period starts at time t 3 . 
     A read operation for the memory cell MC 12  is carried out next from time t 3  to time t 4 ′. 
     At time t 3 , in order to perform a precharging operation upon the bit line BL 2,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made low (=GND) and high (=V DD ), respectively. As a result, the voltage at the node N 2  of the NAND circuit  221  becomes low while the voltage at the node N 1  of the NAND circuit  211  remains high. Therefore, the transistors  212  and  222  are turned OFF and ON, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . On the other hand, the signals {overscore (Y 1 )} and {overscore (Y 2 )} are made high and low, respectively; however, the data sense recognition signal SASTP is high, so that the transistors  411  and  421  are both turned OFF. In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2V thn ), the bit line BL 2  is precharged to V REF −V thn , while the voltage at the bit line BL 1  remains low. 
     Next, at time t 4 , in order to perform a data sampling operation upon the memory cell MC 12,  the X address signal X 1  is made high to select the word line WL 1,  while the X address signal X 2  remains low. In this case, since the memory cell MC 12  stores data “ 0 ”, the memory cell MC 12  remains in an OFF state, so that the voltages at the bit lines BL 1  and BL 2  remain low and high (=V REF −V thn ), respectively. As a result, the sense amplifier output signal S 2  shows low (=data “ 0 ”). 
     Next, at time t 4 ′, since the data sense recognition signal SASTP falls on the condition that the Y address signal Y 2  is high, the signal Y 2 ′ of the NOR circuit  423  is made high so that the transistor  421  is turned ON to discharge the bit line BL 2.  Thus, the data sampling period for the memory cell MC 12  is substantially completed before the next precharging period starts at time t 5 . 
     A read operation for the memory cell MC 21  is carried out next from time t 5  to time t 6 ′. 
     At time t 5 , in order to perform a precharging operation upon the bit line BL 1,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made high (=V DD ) and low (=GND), respectively. As a result, the voltage at the node N 1  of the NAND circuit  211  becomes low while the voltage at the node N 2  of the NAND circuit  221  remains high. Therefore, the transistors  212  and  222  are turned ON and OFF, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . On the other hand, the signals {overscore (Y 1 )} and {overscore (Y 2 )} are made low and high, respectively; however, the data sense recognition signal SASTP is high, so that the transistors  411  and  421  are both turned OFF. In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2 V thn ), the bit line BL 1  is precharged to V REF −V thn , while the voltage at the bit line BL 2  remains low. 
     Next, at time t 6 , in order to perform a data sampling operation upon the memory cell MC 21,  the X address signal X 2  is made high to select the word line WL 2,  while the X address signal X 1  remains low. In this case, since the memory cell MC 21  stores data “ 1 ”, the memory cell MC 21  is turned ON, so that the voltage at the bit line BL 1  becomes low. As a result, the sense amplifier output signal S 1  shows high (=data “ 1 ”). 
     Next, at time t 6 ′, since the data sense recognition signal SASTP falls on the condition that the Y address signal Y 2  is high, the signal Y 2 ′ of the NOR circuit  413  is made high so that the transistor  411  is turned ON to discharge the bit line BL 1.  Thus, the data sampling period for the memory cell MC 21  is substantially completed before the next precharging period starts at time t 7 . 
     In the above-mentioned state, since the memory cell MC 22  also stores data “ 1 ”, the memory cell MC 22  is also turned ON. In this case, however, the voltage at the bit line BL 2  already becomes low. Therefore, even when the voltage at the bit line BL 1  is decreased, the reference voltage V REF  is not decreased due to the capacitive coupling of the gate and source (drain) of each the transistors  213  and  223 . 
     A read operation for the memory cell MC 22  is carried out next from time t 7  to time t 8 ′. 
     At time t 7 , in order to perform a precharging operation upon the bit line BL 2,  the precharge signal PRC is made high (=V DD ) and the Y address signals Y 1  and Y 2  are made low (=GND) and high (=V DD ), respectively. As a result the voltage at the node N 2  of the NAND circuit  221  becomes low while the voltage at the node N 1  of the NAND circuit  211  remains high. Therefore, the transistors  212  and  222  are turned OFF and ON, respectively. Note that all the memory cells are turned OFF by the low X address signals X 1  and X 2 . On the other hand, the signals {overscore (Y 1 )} and {overscore (Y 2 )} are made high and low, respectively; however, the data sense recognition signal SASTP is high, so that the transistors  411  and  421  are both turned OFF. In this case, since the transistors  213  and  223  are in an ON state by the reference voltage V REF  (=2V thn ), the bit line BL 2  is precharged to V REF −V thn , while the voltage at the bit line BL 1  remains low. 
     Next, at time t 8 , in order to perform a data sampling operation upon the memory cell MC 22,  the X address signal X 2  is made high to select the word line WL 2,  while the X address signal X 1  remains low. In this case, since the memory cell MC 22  stores data “ 1 ”, the memory cell MC 22  is turned ON, so that the voltage at the bit line BL 2  becomes low. As a result, the sense amplifier output signal S 2  shows high (=data “ 1 ”). 
     Next, at time t 8 ′, since the data sense recognition signal SASTP falls on the condition that the Y address signal Y 2  is high, the signal Y 2 ′ of the NOR circuit  423  is made high so that the transistor  421  is turned ON to discharge the bit line BL 2.  Thus, the data sampling period for the memory cell MC 22  is substantially completed before the next precharging period starts at time t 9 . 
     In the above-described second embodiment, during a precharging time period, only one selected bit line is precharged while the voltages at non-selected bit lines remains low (=GND). In addition, at the end of a data sampling time period before the next precharing time period starts, the voltage at the selected bit line becomes low. As a result, even when the voltage at the selected bit line falls from high to low at the beginning of a data sampling time period, the reduction of the reference voltage V REF  due to the capacitive coupling of the transistors  213 ,  223 , . . . hardly occurs, since the voltages at all the other non-selected bit lines do not change. Thus, the reduction of the speed of the read operation can be suppressed. 
     In FIGS. 3 and 5 the memory cell array  1  can be constructed by mask ROM cells. For example, as illustrated in FIG. 7A, data “ 0 ” or “ 1 ” of a memory cell corresponds to the presence or absence of an enhancement type transistor. Also, as illustrated in FIG. 7B, data “ 0 ” or “ 1 ” corresponds to the low or high threshold voltage of a transistor. Further, as illustrated in FIG. 7C, data “ 0 ” or “ 1 ” corresponds to the depletion type or enhancement type of a transistor. Further, as illustrated in FIG. 7D, data “ 0 ” or “ 1 ” corresponds to the presence or absence of a contact window (throughhole) which connects a transistor to one bit line. 
     As explained hereinbefore, according to the present invention, since the reference voltage supplied to the sense amplifiers is hardly decreased, the reduction of the speed of the read operation can be suppressed.