Abstract:
A control circuit equipped with electrostatic discharge (ESD) protection includes a plurality of shift registers, a plurality of buses coupled to the plurality of shift registers, a common line, a set of ESD protection components coupled to a set of the plurality of the buses for protecting the plurality of buses from ESD events; and a set of current paths coupled between the set of the ESD protection components and the common line for providing the ESD current paths to pass through.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention provides control circuits with ESD protection, and more particularly, control circuits with ESD protection of a LCD. 
         [0003]    2. Description of the Prior Art 
         [0004]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional liquid crystal display (LCD)  100 . The conventional LCD  100  comprises a first glass substrate  110 , a liquid crystal layer  120 , and a second glass substrate  130 . The first glass substrate  110  comprises a color filter. The second glass substrate  130  comprises thin film transistors. 
         [0005]    Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating the second glass substrate  130 . As shown in  FIG. 2 , the second glass substrate  130  comprises a plurality of gate lines, a plurality of data lines, and a plurality of pixel areas, such as the pixel area  210 , formed by the gate lines interwoven with the data lines. For example, the pixel area  210  comprises a thin film transistor Q 1  and a storage capacitor C 1 . The gate of the thin film transistor Q 1  is coupled to the adjacent gate line, the source of the thin film transistor Q 1  is coupled to the adjacent data line, and the drain of the thin film transistor Q 1  is coupled to the storage capacitor C 1 . One end of the storage capacitor C 1  is coupled to the drain of the thin film transistor Q 1  and the other end of the storage capacitor C 1  is coupled to a common line VCOM. All the storage capacitors of the pixel areas have one end conjointly coupled to the common line VCOM for storing voltages based on the same voltage level. 
         [0006]    Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating a glass substrate  330  with electrostatic discharge (ESD) protection. Because the gate lines and the data lines of the glass substrate  330  are coupled to the margin of the glass substrate  330  for receiving gate signals and source signals from external devices, ESD events easily happen and break the internal thin film transistors. Therefore, ESD protection components are disposed at the margin of the glass substrate  330 . As shown in  FIG. 3 , The ESD protection component E 1  is coupled to the first gate line, the ESD protection component E 2  is coupled to the second gate line, and so on. Each of the ESD protection components have one end coupled to a common line VA which is known as a short ring. In this way, ESD currents are dispersed and the internal thin film transistors are protected. 
         [0007]    However, another kind of glass substrate is not completely protected from ESD events by the method described above. Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating a glass substrate  400 . The glass substrate  400  comprises a pixel module  410 , a shift register  420 , and a bus module  430 . The pixel module  410  comprises a plurality of pixel areas and an ESD protection module  412 . The pixel module  410  is designed similarly to  FIG. 2  and  FIG. 3 , which is also constructed of a plurality of pixel areas such as the pixel area  411  formed by the gate lines interwoven with the data lines. The ESD protection module  412  comprises a plurality of ESD protection components E 5  to En, and a common line VA. The shift register module  420  comprises a plurality of shift registers S 1  to Sn. Each shift register is coupled to a corresponding gate line. 
         [0008]    The first shift register S 1  receives a start signal ST for transmitting a first gate driving signal to the first gate line after a predetermined period, the second shift register S 1  receives the first gate driving signal for transmitting a second gate driving signal to the second gate line after the predetermined period, and so on. The scanning of a frame is achieved by sequentially driving the n gate lines of the LCD. The bus module  430  comprises buses B 1 , B 2 , and B 3  for respectively providing a voltage VSS, a clock signal XCK, and a clock signal CK to the shift register module  420 . The difference between the glass substrates  130  and  400  is that the glass substrate  400  has the shift register module  420  and the bus module  430 , but there is no ESD protection component designed for shift register module  420  and the bus module  430 . Besides, because the bus module  430  receives the voltage VSS, the clock signals XCK and CK from external devices, the bus module  430  also has to be coupled to the margin of the glass substrate  400 , which is easier to be affected or broken by an ESD event. Thus, when producing the glass substrate  400 , it easily fails and thereby lowers the yield rate. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention provides a control circuit with electrostatic discharge protection. The control circuit comprises a plurality of shift registers; a plurality of buses coupled to the plurality of shift registers; a common line; a set of electrostatic discharge protection components coupled to a set of buses of the plurality of the buses for protecting the plurality of the buses from electrostatic discharge events; and a set of dispersion paths coupled to the set of the electrostatic discharge protection components and the common line for providing dispersion paths to currents of the electrostatic discharge events. 
         [0010]    The present invention further provides a liquid crystal display having control circuits with electrostatic discharge protection. The liquid crystal display comprises a first glass substrate comprising a plurality of control circuits; a plurality of buses coupled to the plurality of the control circuits; a common line; a set of electrostatic discharge protection components coupled to a set of buses of the plurality of the buses for protecting the plurality of the buses from electrostatic discharge events; and a set of dispersion paths coupled to the set of the electrostatic discharge protection components and the common line for providing dispersion paths to currents of the electrostatic discharge events; a second glass substrate; and a liquid crystal layer disposed between the first glass substrate and the second glass substrate. 
         [0011]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a diagram illustrating a conventional liquid crystal display. 
           [0013]      FIG. 2  is a diagram illustrating the second glass substrate. 
           [0014]      FIG. 3  is a diagram illustrating a glass substrate with electrostatic discharge protection. 
           [0015]      FIG. 4  is a diagram illustrating a glass substrate. 
           [0016]      FIG. 5  is a diagram illustrating a control circuit with ESD protection of the present invention. 
           [0017]      FIG. 6  is a glass substrate with ESD protection of the present invention. 
           [0018]      FIG. 7  is a diagram illustrating a control circuit of another embodiment of the present invention. 
           [0019]      FIG. 8  is a glass substrate with ESD protection of another embodiment of the present invention. 
           [0020]      FIG. 9  is a diagram illustrating the ESD protection component of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating a control circuit  500  with ESD protection of the present invention. As shown in  FIG. 5 , the control circuit  500  comprises a bus module  510 , a shift register module  520 , two ESD protection modules  530  and  540 , two dispersion paths P 1  and P 2 , and a common line Vx. The bus module  510  comprises buses B 4 , B 5 , and B 6  for respectively providing a voltage VSS, clock signals XCK and CK to the shift register module  520 . The shift register module  520  comprises a plurality of shift registers S 1  to Sn. Each shift register is coupled to a corresponding gate line. The first shift register S 1  receives a start signal ST for transmitting a first gate driving signal to the first gate line after a predetermined period, the second shift register S 2  receives the first gate driving signal for transmitting a second gate driving signal to the second gate line after the predetermined period, and so on. The scanning of a frame is achieved by sequentially driving the n gate lines of the LCD. The ESD protection module  530  comprises three ESD protection components E 7 , E 8 , and E 9  respectively coupled to the buses B 4 , B 5 , and B 6  for protecting the buses B 4  to B 6  from ESD events. The ESD protection module  540  comprises three ESD protection components E 10 , E 11 , and E 12  respectively coupled to the buses B 4 , B 5 , and B 6  for protecting the buses B 4  to B 6  from ESD events. The ESD protection modules  530  and  540  are positioned at a distance from each other. The dispersion paths P 1  and P 2  are respectively coupled the ESD protection modules  530  and  540  for providing dispersion paths to the ESD currents. The common line Vx is coupled to the dispersion paths P 1  and P 2  for dispersing the ESD currents. For example, in a normal condition, the ESD protection module  530  is open. Therefore, with regards to the bus B 4 , the ESD protection component E 7  is open so that the operation of the bus B 4  is not interfered with. When an ESD event  501  happens at the upper part of the bus B 4 , the ESD protection component E 7  conducts the ESD current to the dispersion path P 1  so that the ESD current can be dispersed through the common line Vx. Thus, the bus B 4  is protected from the ESD event. When an ESD event  502  happens at the lower part of the bus B 4 , the ESD protection component E 10  conducts the ESD current to the dispersion path P 2  so that the ESD current can be dispersed through the common line Vx. Thus, the bus B 4  is again protected from the ESD event. Actually the positions of the ESD modules  530  and  540  are not limited to the upper or the lower parts of the buses. The related layout design is also to be considered when positioning the ESD modules  530  and  540 . Besides, the amount of the ESD protection modules can be more than 2 if needed. 
         [0022]    Please refer to  FIG. 6 .  FIG. 6  is a glass substrate  600  with ESD protection of the present invention. The glass substrate  600  comprises a pixel module  610  and a control circuit  500 . The pixel module  610  comprises a plurality of pixel areas and an ESD protection module  612 . The pixel module  610  is the same as the pixel module  410  as the pixel area  611  shown in  FIG. 6 . The ESD protection module  612  comprises a plurality of ESD protection components E 13  to En, and a common line VA. The common line Vx of the control circuit  500  can couple to the common line VCOM of the pixel module  610  or the common line VA of the ESD protection module  612 . Consequently when the ESD event happens at the bus module  510 , the ESD current can pass to the common lines VCOM or VA for being dispersed through the ESD protection module  530  or  540 , the dispersion paths P 1  or P 2 , and the common line Vx. Therefore, the bus module  510  is protected from the ESD event. 
         [0023]    Please refer to  FIG. 7 .  FIG. 7  is a diagram illustrating a control circuit  700  of another embodiment of the present invention. As shown in  FIG. 7 , the control circuit  700  comprises a bus module  710 , a shift register module  720 , two ESD protection modules  730  and  740 , two ESD protection components E 21  and E 22 , two dispersion paths P 3  and P 4 , and a common line Vx. The bus module  710  comprises three buses B 7 , B 8 , and B 9  for respectively providing a voltage VSS, clock signals XCK and CK to the shift register module  720 . The shift register module  720  comprises a plurality of shift registers S 1  to Sn. Each shift register is coupled to a corresponding gate line. The first shift register S 1  receives a start signal ST for transmitting a first gate driving signal to the first gate line after a predetermined period, the second shift register S 2  receives the first gate driving signal for transmitting a second gate driving signal to the second gate line after the predetermined period, and so on. The scanning of a frame is achieved by sequentially driving the n gate lines of the LCD. The ESD protection module  730  comprises three ESD protection components E 15 , E 16 , and E 17  respectively coupled to the upper parts of the buses B 7 , B 8 , and B 9  for protecting the buses B 7  to B 9  from ESD events. The ESD protection module  740  comprises three ESD protection components E 18 , E 19 , and E 20  respectively coupled to lower parts of the buses B 4 , B 5 , and B 6  for protecting the buses B 7  to B 9  from ESD events. The dispersion paths P 3  and P 4  are respectively coupled the ESD protection modules  730  and  740  for providing dispersion paths to the ESD currents. The common line Vx is coupled to the dispersion paths P 3  and P 4  through the ESD protection components E 22  and E 21  respectively for dispersing the ESD currents. The control circuit  700  is the same as the control circuit  500  except the control circuit  700  further comprises two ESD protection components E 21  and E 22  respectively coupled between the dispersion paths P 3 , P 4  and the common line Vx. The ESD components E 21  and E 22  are designed for preventing the dispersion paths P 3  or P 4  from shorting with the buses B 7 , B 8 , and B 9 . For example, when an ESD event  701  happens at the area A and punches through the area A, the dispersion path P 3  shorts with the bus B 8 . If the dispersion path P 3  shorts with the bus B 8 , because the common line Vx provides a fixed voltage level, the clock signal XCK on the bus B 8  is pulled by the fixed voltage level, causing the control circuit  700  to operate incorrectly. Therefore, the ESD protection component E 21  is disposed between the dispersion path P 3  and the common line Vx to prevent the bus B 8  from being directly coupled to the common line Vx. Besides, in the normal condition, the ESD protection component E 21  is open so the bus B 9  operates regularly. For example, in the normal condition, the ESD protection module  530  is open. It is also the same when the ESD event  701  happens at the areas B, C, and D. The ESD protection components E 21  and E 22  also prevent the buses B 7  to B 9  from directly coupling to the common line Vx. On the other hand, the areas A to D only represent the dispersion paths disposed across the buses, not coupled to the buses. For example, the bus B 8  is disposed vertically in the first layer and the dispersion path P 3  is disposed horizontally in the second layer. Therefore, in the normal condition, the first layer and the second layer are isolated so the bus B 8  is not coupled to the dispersion path P 3 . But when the ESD event  701  happens at the area A and punches through the area A, the bus B 8  of the first layer shorts with the dispersion path P 3  of the second layer. Actually the positions of the ESD modules  730  and  740  are not limited to the upper or the lower parts of the buses. The related layout design is also to be considered when positioning the ESD modules  730  and  740 . Besides, the amount of the ESD protection modules can be more than 2 if needed. 
         [0024]    Please refer to  FIG. 8 .  FIG. 8  is a glass substrate  800  with ESD protection of another embodiment of the present invention. The glass substrate  800  comprises a pixel module  810  and a control circuit  700 . The pixel module  810  comprises a plurality of pixel areas and an ESD protection module  812 . The pixel module  810  is the same as the pixel module  410  as the pixel area  811  shown in  FIG. 6 . The ESD protection module  812  comprises a plurality of ESD protection components E 23  to En, and a common line VA. The common line Vx of the control circuit  700  can couple to the common line VCOM of the pixel module  810  or the common line VA of the ESD protection module  812 . Consequently when the ESD event happens at the bus module  710 , the ESD current can pass to the common lines VCOM or VA for being dispersed through the ESD protection module  730  or  740 , the dispersion paths P 3  or P 4 , and the common line Vx. Therefore, the bus module  710  is protected from the ESD event. 
         [0025]    Please refer to  FIG. 9 .  FIG. 9  is a diagram illustrating the ESD protection component  900  of the present invention. The ESD protection component  900  can comprise a diode D 1  reversely parallel coupled to a diode D 2 , or any other component having the ESD protection function. 
         [0026]    To sum up, with the present invention, during production, the glass substrate is effectively protected from ESD events so that the circuits and the buses on the glass substrate are not broken by the ESD events. Thus the yield rate of the production is improved. Additionally, the design of the ESD protection of the present invention is not limited to the glass substrate and the LCD. Any other designs using ESD components, dispersion paths, and common lines are included in the present invention. 
         [0027]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.