Abstract:
Method and apparatus for testing electrical devices which generate digital signals from analog signals applied to the devices. The testing determines whether or not the electrical devices are capable of properly generating all the different digital codes that correspond to the different analog signals in a particular bandwidth. The method and apparatus provide an external signal indicating whether an electrical device being tested functions properly.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to methods and apparatus for testing electrical devices which generate digital signals from analog signals that are applied to the devices. 
     After an electrical device which generates digital signals related to analog signals, such as an analog-to-digital converter (&#34;ADC&#34;), is manufactured it is desirable to test the device to determine if it functions properly. A properly functioning ADC should generate the full range of digital signals which correspond to the full range of analog signals in the bandwidth which are applied to the ADC. 
     Previous methods of testing ADC&#39;s for digital signal generation have required the use of significant amounts of software and computer overhead. The previous methods may also require up to 30 seconds or more to test one ADC for generation of all digital signals. 
     The apparatus of the present invention utilizes hardware (an electrical circuit) to test an ADC. ADC&#39;s which took 30 seconds to test using prior methods may be tested in little more than a second using the novel methods and apparatus of the present invention. 
     Accordingly, an object of the present invention is to provide a novel method for testing electrical devices to determine whether the devices properly generate digital signals related to analog signals applied to the device. 
     Another object of the present invention is to provide a novel circuit for testing electrical devices for the proper generation of digital signals related to analog signals applied to the device. 
     A further object of the present invention is to provide external indication of whether an electrical device which generates digital signals related to analog signals applied to the device does or does not function properly. 
     These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram illustrating a novel circuit for carrying out a method of the invention. 
     FIG. 2 is a timing diagram illustrating the signal outputs for devices which are part of a novel circuit for carrying out a method of the invention. 
     FIG. 3 is a flow chart illustrating the steps included in one embodiment of a method of the invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     In a preferred embodiment of the novel method, analog signals are applied to an electrical device, such as an analog-to-digital converter 10 (ADC) shown in FIG. 1, during a first stage of the method. A properly functioning ADC generates digital signals related to the applied analog signals. For convenience of explanation, the present method will be described as it may be used with an ADC, although it is to be understood that the method may be used with any electrical device capable of generating digital signals related to analog signals. 
     The analog signals applied to the ADC preferably have a bandwidth at least as great as the predetermined bandwidth of the ADC, i.e. at least as great as the bandwidth of the analog signals the ADC is supposed to be capable of converting to digital signals. Application of analog signals covering the full range of the predetermined bandwidth of the ADC assures that the ADC will have the opportunity to generate all the different possible digital signals corresponding to the analog signals in the predetermined bandwidth. Additionally, a large number of cycles of the analog signals may be applied to the ADC to further guarantee that all possible related digital signals will be generated if the ADC is functioning properly. 
     Clocking signals are applied from a clock 12 to the ADC 10 at the same time the analog signals are being applied thereto, thereby driving the ADC to generate digital signals at an ADC output 14. The clock 12 is selectively connected to the ADC during the time the ADC is generating digital signals in response to received analog signals. 
     Once the digital signals are generated, they are applied in turn from the ADC output 14 to a bank of switches 16. The bank of switches temporarily stores the bit sequence of each of the generated digital signals as it is output from the ADC. The number of switches in the bank should be equivalent to or greater than the number of bits in the digital signals, so that there is a switch 18 (i.e. a temporary storage location) for each bit in the digital signal. 
     After an individual digital signal (including all of its component bits) is resident in the bank of switches, the digital signal is applied from the bank of switches output 20 to a RAM 22. Each complete digital signal serves as a RAM address, therefore the RAM should have at least as many storage cells 24 as there are different possible digital codes that may be generated by the ADC. Preferably, 2 N  storage cells will be provided when the digital signals output from the ADC are N bits in length. However many storage cells are provided, the steps of generating an individual digital signal, applying it to the bank of switches and from the bank of switches to the RAM, will have to be repeated a number of times equivalent to the number of storage cells. 
     Still during this first stage of the method, while the ADC is generating digital signals, the RAM input/output (I/O) port 28 is selected to write a &#34;code present&#34; signal to each of the storage cells which are addressed by the bank of switches output. Accordingly the writing of a &#34;code present&#34; signal to a particular storage cell is ultimately dependent upon the generation by the ADC of a digital code corresponding to that address. 
     If the ADC generates all the different possible digital signals for the predetermined ADC bandwidth, then there will be a &#34;code present&#34; signal in a storage cell for each and every different digital signal the ADC was supposed to be capable of generating. If, however, the ADC does not generate a particular digital signal that the ADC should have generated given the analog signals applied, then the storage cell with an address corresponding to that particular digital signal will not contain a &#34;code present&#34; signal. 
     The first stage of the method is complete when a sufficient number of analog signals have been applied to the ADC such that all the digital signals the ADC is capable of generating should have been generated, and all the storage cells with addresses corresponding to the generated digital signals will have had a &#34;code present&#34; signal stored therein. 
     The object of the second stage of the method is to read the signals present in each of the storage cells (the &#34;resident signals&#34;) after the completion of the first stage of the method, i.e., to scan the RAM 22. The resident signals are read to determine if any of the storage cells do not contain a &#34;code present&#34; signal, which would indicate that the ADC failed to generate the digital signal corresponding to the address of the storage cell in question. 
     With continued reference to FIG. 1, the second stage of the method is initiated by a test control 26 setting the I/O port 28 of the RAM 22 to read, and resetting an up counter 30, so that the up counter generates an initial digital signal and applies the signal to the bank of switches 16. The digital signals generated by the up counter should have the same number of bits as the digital signals generated by the ADC 10, so that they may also serve as storage cell addresses. 
     The initial digital signal is applied from the bank of switches, through the bank of switches output 20, to the RAM 22 as an address. The initial digital signal will correspond to an address for an initial storage cell 24 in the RAM 22. When the storage cell 24 is addressed, the signal stored within the storage cell (either a &#34;code present&#34; signal or not a &#34;code present&#34; signal) will be read by the I/O port 28, and applied therefrom to an inverter 32. The signal applied to the inverter will be inverted and the resultant signal will in turn be applied to a logic device 34. 
     The logic device receives input signals from both the inverter 32 and the clock 12. Selective connection of the clock to the logic device 34 may be controlled by test control device 26. When the logic device receives both a clocking signal from the clock 12 and an inverted &#34;code present&#34; signal from the inverter 32, a signal is output from the logic device to the up counter 30, thereby incrementing the up counter to generate a successive digital signal to that last generated. 
     The successive digital signal generated by the up counter is applied to the bank of switches 16 and the RAM 22, just as the initial digital signal was. The successive digital signal corresponds to an address for a storage cell successive to that of the initial storage cell. Accordingly, the generation of the successive digital signal causes the reading of the resident signal in the next storage cell. 
     The steps of the preceding two paragraphs are repeated so that a series of successive addresses for the storage cells is generated and so that the respective resident signals in the storage cells are read. If a &#34;code present&#34; signal is resident in each successive storage cell, the up counter will be incremented to generate a successive digital signal until all of the storage cells have been read. After the last storage cell is read and determined to have a &#34;code present&#34; signal resident therein, the test control may indicate there are &#34;no missing codes&#34;. 
     If a &#34;code present&#34; signal is absent from any one of the storage cells having an address corresponding to a digital signal which should have been generated by the ADC, then the up counter will not be incremented, and an alarm signal will be generated by the test control 26. More specifically an alarm signal is generated by the test control 26 as the result of a &#34;non-code present&#34; signal being read from a storage cell and applied through the inverter 32 to the logic device 34. The application of a clocking signal and the &#34;non-code present&#34; signal to the logic device does not cause a signal to be output from the logic device to the up counter 30. The up counter&#39;s failure to increment (as a result of not receiving a signal from the logic device) may then be detected by the test control and an appropriate alarm signal generated. 
     Referring to the signal timing diagram of FIG. 2, the test control signals 40, clock signals 42, ADC signals 44, up counter signals 46, and I/O port signals 48 are depicted for the first and second stages of the presently described method. 
     Time 1 designates the time at which analog signals are first applied to the ADC. Analog signals in the predetermined bandwidth are continuously applied after time 1 until time 2. The timing diagram shows that between time 1 and time 2, the up counter and the test control signals remain low, the I/O port signals remain high, and the clock signals are regularly cyclical. 
     The analog signals cease to be applied to the ADC after time 2. Correspondingly, the test control and up counter signals remain high after time 2 until time 3, the time when a &#34;code present&#34; signal fails to be resident in a storage cell being read thereby causing the I/O signal to go from high to low. The timing diagram shows time 3 as occurring after the second storage cell is read and no &#34;code present&#34; signal is found to be resident therein. 
     While preferred embodiments of the present invention have been described, it is to be understood that the embodiments described are illustrative only and the scope of the invention is to be defined solely by the appended claims when accorded a full range of equivalence, many variations and modifications naturally occurring to those of skill in the art from a perusal hereof.