Abstract:
A method of operating a pixel includes generating one of m possible data streams from an n-bit input that represents a desired intensity level. The data stream is usable to drive a pixel to the desired intensity level. Each of the m data streams includes a plurality of frames. The method further includes pseudo-randomly selecting a starting frame from the plurality of frames in the data stream for a specific pixel, using the selected data stream to drive the specific pixel, and pseudo-randomly selecting a different starting frame for a different specific pixel.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS  
       [0001]     This application is a non-provisional of, and claims the benefit of, co-pending, commonly assigned U.S. Provisional Patent Application No. 60/512,321, entitled, “METHOD AND SYSTEM FOR PROVIDING FRAME RATE CONTROL” (Attorney Docket No. 020824-007700), filed on Oct. 17, 2003, by Mark Flowers, et al., the entire disclosure of which is herein incorporated by reference for all purposes. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates generally to display systems. More specifically, the present invention relates to systems and methods for providing grayscale using frame rate control.  
         [0003]     Passive LCDs, such as the common STN display type, require display drive algorithms to generate shades of gray or multiple shades of color. STN display driver circuits are only capable of driving individual display pixels to either a full OFF or full ON condition. However, intermediate drive levels are required to generate shades of gray or other color. Intermediate levels are achieved by rapidly changing a pixel drive between ON and OFF resulting in the generation of a simulated intermediate drive level corresponding to the percentage of time that a pixel is driven ON. If the ON/OFF sequencing is fast relative to the visual response of the display, then an intermediate visual intensity level is achieved.  
         [0004]     Various approaches can be used to alternate pixels between ON and OFF to generate intermediate drive levels. Some of these approaches utilize Frame Rate Control (FRC). FRC approaches or algorithms sequence pixel ON/OFF transitions on a frame by frame basis with each pixel driven either ON or OFF for an entire frame. Other common approaches use Pulse Width Modulations (PWM). PWM implementations generate pixel ON/OFF transitions within an individual frame.  
         [0005]     FRC approaches typically result in slight flicker and some motion artifacts due to simulation of intermediate levels by ON/OFF drive sequencing from frame to frame. Straightforward FRC implementation uses fixed conversion of grayscale level to pixel ON/OFF state based on circular frame number. This approach creates significant flicker unless the rate of frame refresh is very high (500 Hz). Having a high refresh rate, however, is not practical because of high power consumption and low contrast that quickly diminishes with frame rate increase.  
         [0006]     Some improved approaches use more sophisticated conversion of grayscale level to pixel ON/OFF state. Many flavors of improved FRC were developed but, in general, use phase shift that is different for each pixel position (phase depends on x-y position). As mentioned above, a number of simplistic implementations of FRC also exhibit another problem—“motion artifacts,” or certain motion visible in static images. The motion appears due to human visual detection. When high-frequency blinking appears, adjacent pixels that blink with the same sequence but with different phase create imaginary motion effect.  
         [0007]     FRC algorithms are widely used in consumer and commercial products with monochrome and color passive LCDs. Product examples include PDAs, cell phones, digital cameras, and commercial equipment control panels. High performance LCDs with high resolution, such as a PC monitor, use TFT active displays which do not need FRC algorithms (active display drivers are capable of producing intermediate levels directly, therefore the algorithmic simulation of intermediate drive levels is not needed).  
         [0008]     FRC algorithms have been widely known and used for many years. Algorithm implementations are generally in hardware (rather than software) due to the requirement for high speed processing. Most implementations have some amount of software programmability to enable visual results to be optimized for different display manufactures. Products with FRC driven LCDs are generally designed in one of two approaches: (1) product engineers purchase a graphics controller IC which has a proprietary FRC algorithm built in, or (2) product engineers design a custom system ASIC which contains the FRC function and LCD controller.  
         [0009]     In the past decade, there has been a substantial market for graphic controller ICs with built-in FRC algorithms. Consequently, graphic controller IC manufacturers have invested heavily in the development of optimized and refined FRC algorithms. As a result, many graphic IC manufacturers have developed complex FRC algorithms with various claimed visual benefits. While many products with FRC algorithms now exist, it is still desirable to develop FRC algorithms that are designed specifically for a product specific ASIC to optimize product performance.  
         [0010]     Furthermore, STN LCD has a non-linear response curve (perceived intensity vs. drive level) that washes out color difference in some parts of intensity range and spreads shades further apart in others. Usually, such response curve has a shape of S, when high and low levels have almost indistinguishable intensity and intensity of medium levels grow rapidly creating big steps. Such response curve results in unpleasant color distortions.  
         [0011]     Moreover, different LCD panels behave differently with the same FRC algorithm. Some LCD panels behave better while some are worse with any fixed (non-programmable) FRC algorithm.  
         [0012]     Hence, it is desirable to provide a system with an improved FRC algorithm that will, amongst other things, minimize creation of flicker and motion artifacts, and compensate for LCD non-linearity (gamma correction).  
       BRIEF SUMMARY OF THE INVENTION  
       [0013]     Embodiments of the present invention thus provide a method of operating a pixel. The method includes generating one of m possible data streams from an n-bit input that represents a desired intensity level. The data stream is usable to drive a pixel to the desired intensity level. Each of the m data streams includes a plurality of frames. The method further includes pseudo-randomly selecting a starting frame from the plurality of frames in the data stream for a specific pixel, using the selected data stream to drive the specific pixel, and pseudo-randomly selecting a different starting frame for a different specific pixel. The intensity level may be a grayscale intensity level. In some cases, n=4 and m=33. The specific pixel may be a color pixel, in which case the method may include, for two additional color components, generating one of m possible data streams from an n-bit input that represents a desired intensity level. The data stream may be usable to drive a pixel to the desired intensity level. Each of the m data streams may include a plurality of frames. The method may include pseudo-randomly selecting a starting frame from the plurality of frames in the data stream for a specific pixel, using the selected data stream to drive the specific pixel, and pseudo-randomly selecting a different starting frame for a different specific pixel.  
         [0014]     In other embodiments, a computer-readable medium has stored thereon code for generating one of m possible data streams from an n-bit input that represents a desired intensity level. The data stream is usable to drive a pixel to the desired intensity level. Each of the m data streams includes a plurality of frames. The computer-readable medium also includes code for pseudo-randomly selecting a starting frame from the plurality of frames in the data stream for a specific pixel, and code for pseudo-randomly selecting a different starting frame for a different specific pixel.  
         [0015]     In still other embodiments, a frame rate controller includes a lookup table configured to receive video data. The video data includes an intensity level for a pixel. The lookup table is configured to use the intensity level to select a frame sequence comprising a plurality of frames. The frame rate controller also includes a phase randomizer configured to identify a starting frame in the plurality of frames and a display interface configured to sequentially receive the frame sequence, starting with the starting frame, and direct the frame sequence to a pixel, thereby driving the pixel to the intensity level. The phase randomizer may be configured to identify, for a different pixel, a different starting frame in a frame sequence. The phase randomizer may be a Linear Feedback Shift Register.  
         [0016]     In other embodiments, a video controller includes means for generating one of m possible data streams from an n-bit input that represents a desired intensity level. The data stream is usable to drive a pixel to the desired intensity level. Each of the m data streams includes a plurality of frames. The video controller also includes means for pseudo-randomly selecting a starting frame from the plurality of frames in the data stream for a specific pixel. The means for pseudo-randomly selecting a starting frame is configured to pseudo-randomly select a different starting frame for a different specific pixel. The video controller also includes means for using the selected data stream to drive the specific pixel. In some cases, m=2 n+1 +1. In some cases, n=4 and m=33. The means for generating one of m possible data streams may be a lookup table.  
         [0017]     In further embodiments, a method of operating a pixel includes receiving an n-bit input that represents a desired intensity level and generating a m-bit value representative of a data stream usable to drive a pixel to the desired intensity level. The data stream includes a number of active frames within a plurality of frames. The method further includes pseudo-randomly distributing the number of active frames throughout the plurality of frames and using the data stream to drive a specific pixel. The pixel may be a color pixel, in which case the method may include, for two additional color components, receiving an n-bit input that represents a desired intensity level and generating a m-bit value representative of a data stream usable to drive a pixel to the desired intensity level. The data stream includes a number of active frames within a plurality of frames. The method also includes pseudo-randomly distributing the number of active frames throughout the plurality of frames and using the data stream to drive the specific pixel.  
         [0018]     Is still further embodiments, a computer-readable medium has stored thereon code for receiving an n-bit input that represents a desired intensity level, code for generating a m-bit value representative of a data stream usable to drive a pixel to the desired intensity level, wherein the data stream includes a number of active frames within a plurality of frames, and code for pseudo-randomly distributing the number of active frames throughout the plurality of frames.  
         [0019]     In still other embodiments, a frame rate controller includes a lookup table configured to receive video data. The video data includes an intensity level for a pixel. The lookup table is configured to use the intensity level to determine a number of active frames within a plurality of frames. The frame rate controller also includes a pattern randomizer configured to distribute the active frames within the plurality of frames and a display interface configured to sequentially receive the plurality of frames and direct the frames to a pixel, thereby driving the pixel to the intensity. The intensity level may be a grayscale intensity level. The pattern randomizer may be configured to, for a different pixel, distribute the active frames within the plurality of frames differently. The pattern randomizer may be a Linear Feedback Shift Register.  
         [0020]     In other embodiments, a video controller includes means for receiving an n-bit input that represents a desired intensity level and generating a m-bit value representative of a data stream usable to drive a pixel to the desired intensity level. The data stream includes a number of active frames within a plurality of frames. The video controller also includes means for pseudo-randomly distributing the number of active frames throughout the plurality of frames and means for using the data stream to drive a specific pixel.  
         [0021]     In some embodiments of the present invention, a fully integrated system ASIC includes an FRC algorithm and an LCD driver interface. According to one exemplary aspect, there are two similar versions of the FRC algorithm. The FRC algorithm is designed based on a number of objectives including, for example: ability to take advantage of features offered by simple commonly-used approaches; ability to support monochrome and color displays; ability to provide software programmability so that the algorithm could be adjusted to optimize visual performance on different LCD panels.  
         [0022]     According to one exemplary aspect, the FRC algorithm is designed to produce sixteen shades of intensity based on a 4-bit input value. The system uses the same FRC algorithm when configured for either monochrome or color displays. In the case of a monochrome display, sixteen shades of gray can be produced. In the case of a color display, the same algorithm is used to create sixteen shades each of red, green and blue per pixel. In this manner, a total of twelve bits per pixel control 4,096 possible colors. In one embodiment, the system is run in color mode with a color LCD panel.  
         [0023]     In some embodiments, the system ASIC uses a passive STN LCD and an FRC algorithm. The system ASIC is additionally capable of interfacing to an active TFT LCD. In TFT mode, the FRC algorithm is disabled since TFT drivers can display intermediate levels directly. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]     A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings wherein like reference numerals are used throughout the several drawings to refer to similar components. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.  
         [0025]      FIG. 1  illustrates a simplified block diagram of a FRC controller that implements a first exemplary FRC algorithm according to embodiments of the present invention.  
         [0026]      FIG. 2  illustrates a lookup table used in association with the exemplary embodiment of  FIG. 1 .  
         [0027]      FIG. 3  illustrates a simplified block diagram of a FRC controller that implements a second exemplary FRC algorithm according to embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]     Embodiments of the present invention reduce visual artifacts in displays employing grayscale (color or monochrome) algorithms. In some embodiments, grayscale frame cycles are randomized spatially such that neighboring pixels generally experience different phases of the cycle. In some embodiments, active frames within a cycle are randomized. Exemplary embodiments are described in more detail hereinafter.  
         [0029]      FIG. 1  illustrates a first example of a video controller  100  according to embodiments of the present invention. The controller  100  is merely exemplary of a number of embodiments according to the invention. The controller  100  may be embodied in an ASIC, or other appropriate device or arrangement. According to this example, the controller  100  implements a Frame Rate Control (FRC) algorithm that provides 4-bit grayscale per channel. Thus, the algorithm produces sixteen possible intensity levels when operating in monochrome mode and 4096 possible colors (sixteen color shades in three color channels) when operating in color display mode.  
         [0030]     The FRC algorithm cycles through a sequence of thirty-two video frames. Within the 32-frame sequence, the algorithm directs an individual pixel (or individual pixel color components, e.g., red, green, and blue) to turn ON for n frames and OFF for 32-n frames. The resulting visual intensity of each pixel is proportional to the percentage of time that it is ON within the 32-frame sequence (i.e., proportional to the value of n).  
         [0031]     In this embodiment, the controller  100  receives video data from a video data source, such as RAM  102 , and sends pixel control signals to a display panel, such as LCD panel  104 , via an interface, such as LCD interface  106 . Although in this specific embodiment the controller  100  provides FRC for a color LCD panel, it should be apparent to those skilled in the art, that embodiments of the invention also may be used to provide FRC for a monochrome display or other displays.  
         [0032]     The controller  100  includes a display timing generator  110 , a phase randomizer  112 , a data sequencer  114 , a lookup table  116 , and a multiplexer  118 . The display timing generator  110  provides various clock signals and counters to properly sequence data through the controller  100 . For example, signals provided from the display timing generator  110  to the data sequencer  114  are used to select appropriate data from the video RAM  102 .  
         [0033]     In this specific embodiment, data pass from the data sequencer  114  to the lookup table  116  in four bit groups, each group representing a grayscale level for a pixel or pixel color component. The four bit groups essentially address intensity levels from the lookup table  116 . If multiple color components are included, each color component may have a different lookup table.  
         [0034]     As mentioned previously, a grayscale cycle in this embodiment is thirty-two frames long. Thus, thirty-three intensity levels are possible as a result of pixel activation in n out of thirty-two frames where n can range from zero to thirty-two. However, only sixteen intensity levels are desired. The lookup table maps each of the sixteen grayscale levels to one of the thirty-three possible drive intensity levels.  
         [0035]     In this specific embodiment, the lookup table performs two functions. First, the mapping of each of the sixteen grayscale levels to one of thirty-three possible drive intensity levels allows for the creation of an intensity control curve that matches the visual gamma response of an LCD panel. In other words, a one-quarter grayscale may not have exactly eight of the thirty-two frames ON to account for non-linearity in an LCD intensity curve. Second, the ON and OFF frames may be arranged within the 32-bit output so as to create a uniform or optimal distribution of the active frames within the 32-frame sequence. Such control of the frame pattern may minimize flicker, motion artifacts, and other undesired effects.  
         [0036]     To implement the two functions described immediately above, the lookup table may be software programmable in the controller, which provides for some amount of visual fine tuning to accommodate variances from different LCD manufacturers. Hardware implementations may leverage one table of values to implement the same mapping function for the red, green and blue components. In some embodiments, optimal table values are empirically determined for a given LCD manufacturer and permanently fixed in base ROM code. Further, lookup tables for different colors may have different forms. An exemplary lookup table is illustrated in  FIG. 2 .  
         [0037]      FIG. 2  illustrates a 4×32-bit lookup table  200  according to a specific embodiment of the invention. Four-bit grayscale intensity levels  202 , received from the data sequencer  114 , address 32-bit pixel drive waveforms  204  that provide thirty-three possible intensity levels. Only six of the sixteen gray scale intensity levels are shown for ease of illustration. In this exemplary embodiment, it is clear that the mapping of grayscale intensity levels  202  to pixel drive waveforms is not linear. For example, the third intensity level  206  corresponds to {fraction (2/16)} gray. The corresponding pixel drive waveform  208 , however, has five out of thirty-two ON frames. The difference in relative weighting accounts for non-linear LCD response characteristics and the like. Further, the five ON frames are distributed throughout the waveform to reduce or eliminate discernible visual artifacts that could occur if ON and OFF frames were grouped together. Those skilled in the art will appreciate other advantages in light of this disclosure.  
         [0038]     Once selected from the lookup table  116 , data for each color channel pass to multiplexers  118 . Individual bits of the 32-bit sequence are selected from the multiplexer  118  using signals from the phase randomizer  112 . As will be described in more detail below, bits are selected so as to spatially randomize the phase of the 32-bit sequence for each pixel.  
         [0039]     Conventional FRC algorithms tend to generate perceived motion artifacts in intermediate intensity levels. These artifacts may be reduced by varying the phase of the FRC sequence for some pixels. In other words, while every pixel follows the same 32-frame FRC sequence, at any moment in time, some pixels will be at different counts (called phase) in the 32-frame sequence.  
         [0040]     In some embodiments of the present invention, the system controller implements an approach to phase variation that works well with relatively low density of colors (4,096) and relatively low resolution (200×200 max). The phase of the 32-frame FRC sequence is varied for each pixel by a pseudo-random number generator  120 . The net result is a (pseudo) random spatial distribution of pixel phase assignments across the display area. The pseudo-random number generator  120  is reset with the same seed every frame resulting in a constant pseudo-random phase pattern across the display area. In color mode, three independent pseudo random number generators  120 - 1 ,  120 - 2 ,  120 - 3  are used, one each for red, green and blue, which further randomizes the spatial phasing of FRC frames. In a specific embodiment, the pseudo random number generators  120  are Linear Feedback Shift Registers.  
         [0041]     In this specific embodiment, linear feedback shift registers (LFSR) produce a random phase assignment spatially and repeat the pattern when re-seeded for the next frame. The frame counter is incremented to thereby cause each pixel to cycle through an entire intensity waveform before the next grayscale value is rendered in a subsequent 32-frame cycle. Those skilled in the art will appreciate other spatial randomization approaches other than using LFSRs. For example, in some embodiments, a pre-determined random phase value may be hard coded for each pixel, thus eliminating the need for pseudo-random number generation circuitry. Depending upon the number of pixels in the display, however, such embodiments may require more silicon real estate than the pseudo-random number generation circuitry.  
         [0042]     In some embodiments, this approach has no algorithmic defined (other than pseudo random) or otherwise constrained spatial phase relationships, does not use a tiled or group of pixels approach to define phase variance, does not dither pixels, and/or has no temporal phase variance. The foregoing approach is further illustrated in pseudo-code below: 
 
sequence=table[pixel];  (1) 
 
 {a 32-bit sequence is selected from a lookup table using a 4-bit grayscale value for a pixel}
 
phase=frame+ X+Y+rnd ( X )+ rnd ( Y ); (addition modulo  32  is used)  (2) 
 
 {a phase value is computed for a given pixel where: “frame” is a frame counter (counts from 0 to 31, i.e. 32 frames sequence); “X” is an X-counter (horizontal pixel position); “Y” is an Y-counter (vertical pixel position); “rnd(X)” is a pseudo-random generator for X with programmable seed, 15-bit wide LFSR (one for each color); “rnd(Y)” is a pseudo-random generator for Y with programmable seed, 9-bit wide LFSR (one for each color)}
 
out=sequence[phase];  (3) 
 
 {the pixel drive signal for a specific frame is selected from the sequence using the phase value}
 
 X═X+ 1 for each pixel;  Y═Y+ 1 for each line; reset rnd(X) and rnd(Y) at end of frame.  (4) 
 
 {the pseudo-random generators  120  are reset after each frame and the pixel position counters are incremented appropriately (X pseudo-random generator advances once for each pixel, Y advances once for each line)}
 
         [0043]     In summary, the first embodiment of the FRC algorithm involves: fixed 32-frame FRC sequence; controlling intensity by driving a pixel n out of thirty-two frames, thus yielding thirty-three possible output intensity levels; mapping sixteen input levels to thirty-three possible output intensity levels; assigning a fixed distribution of n enabled frames within a 32-frame sequence for each intensity level; using one lookup table to define the intensity mapping and active frame distribution assignment; using a pseudo-random generator to create a spatial phase variance of the 32-frame FRC sequence for each pixel; using three pseudo-random generators to create different variances for each red, green and blue components; and no dithering, no tiled assignment of phase variances and no temporal phase variance.  
         [0044]      FIG. 3  illustrates a second exemplary video controller  300  according to embodiments of the present invention. The second video controller  300  is similar to the first video controller  100  in that it implements a 32-frame FRC algorithm. In this embodiment, however, the FRC algorithm generates pseudo-random frame pattern assignment between pixels. In other words, for any given intensity level having n active frames within a 32-frame sequence, the second embodiment varies the distribution locations of n active frames from pixel-to-pixel. The first embodiment implements an FRC algorithm that produces a constant pattern that distributes the n active frames within the thirty-two frame sequence. In the second embodiment, the FRC algorithm does not address phase since phase is meaningless if the pattern varies from pixel to pixel. This is an alternative approach to minimizing motion artifacts.  
         [0045]     In this embodiment, the controller  300  receives video data from a video data source, such as RAM  102 , and sends pixel control signals to a display panel, such as LCD panel  104 , via an interface, such as LCD interface  106 . The controller  300  includes a display timing generator  110 , a pattern randomizer  318 , a data sequencer  114 , and a lookup table  316 . The lookup table  316 , in this specific embodiment, is a 4×5 bit table that maps sixteen grayscale intensity levels (four bits) to one of thirty-two possible gamma values represented by a 5-bit output.  
         [0046]     The pattern randomizer includes a pseudo-random number generator  120  for each color channel and a pattern randomizer  318  for each color channel. The pseudo-random number generator(s)  120  may be LFSRs or other appropriate arrangement. The pattern randomizer  318  randomizes the distribution of ON frames within a 32-frame sequence from pixel-to-pixel according to the algorithm described in detail immediately hereinafter. 
 
level=table[pixel];  (1) 
 
 {a pixel&#39;s 4-bit grayscale level is used to select one entry from the table, effectively converting it to a 5-bit value. If multiple colors are being rendered, then this function is performed once for each color} 
                   A   =       ⁢       (           frame   ⁡     [   0   ]       ?   level     ⁡     [     4   ⁢     :     ⁢   0     ]       :   0     )     +                     ⁢       (           frame   ⁡     [   1   ]       ?     ⁢     (       level   ⁡     [     3   ⁢     :     ⁢   0     ]       ⁢     &lt;&lt;   1       )       :   0     )     +                     ⁢       (           frame   ⁡     [   2   ]       ?     ⁢     (       level   ⁡     [     2   ⁢     :     ⁢   0     ]       ⁢     &lt;&lt;   2       )       :   0     )     +                     ⁢       (           frame   ⁡     [   3   ]       ?     ⁢     (       level   ⁡     [     2   ⁢     :     ⁢   0     ]       ⁢     &lt;&lt;   3       )       :   0     )     +                     ⁢       (           frame   ⁡     [   4   ]       ?     ⁢     (       level   ⁡     [   0   ]       ⁢     &lt;&lt;   4       )       :   0     )     ;           ⁢     (     addition   ⁢           ⁢   modulo   ⁢           ⁢   32   ⁢           ⁢   is   ⁢           ⁢   used     )                     (   2   )             
  B=A +level; (addition modulo  32  is used)  (3) 
 
 {intermediate values A and B (5-bit each) are calculated (for each color). “Frame” is a frame counter (counts from 0 to 31, i.e. 32 frames sequence). Brackets “[ ]” represent bit numbers, Question Marks “?” represents conditional execution, Less Than operators “&lt;&lt;” represent shift left operation that is implemented by wiring}
 
range_min=1 when (phase &gt;=A), 
 
range_min=0 otherwise; (1-bit value)  (4) 
 
range_max=1 when (phase&lt;B), 
 
range_max=0 otherwise; (1-bit value)  (5) 
 
 {two comparisons are performed}
 
phase= X+Y+rnd ( X )+ rnd ( Y )  (6) 
 
 {phase (5-bit value) is computed for each color were “X” is an X-counter (horizontal pixel position); “Y” is an Y-counter (vertical pixel position); “rnd(X)” is a pseudo-random generator for X with programmable seed, 15-bit wide LFSR (one for each color); “rnd(Y)” is a pseudo-random generator for Y with programmable seed, 9-bit wide LFSR (one for each color)}
 
OUT=1 when (level=31), 
 
OUT=(range_min OR range_max) when (A&gt;B), 
 
OUT=(range_min AND range_max) for all other cases (1-bit value)  (7) 
 
 {output pixel value (1-bit, ON or OFF) is calculated}
 
 All pseudo-random generators are reset at the start of each frame. X pseudo-random generator advances once for each pixel, Y advances once for each line. 
 
         [0047]     Any of the functions or methods described in this application can be embodied as code on a computer readable medium. The computer readable medium may comprise any suitable optical, electronic, or magnetic mode of data storage. The computer readable medium may be incorporated into an interactive apparatus using a display. In addition, code for any of the functions or methods described herein may be created using any suitable programming language including C, C++, etc.  
         [0048]     Embodiments of the invention can be used in an interactive apparatus using a display screen. Examples of such interactive apparatuses are described in U.S. patent application Ser. Nos. 10/775,830, 10/776,012, 60/446,829, and 60/512,326, which are herein incorporated by reference in their entirety for all purposes.  
         [0049]     The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed. Moreover, any one or more features of any embodiment of the invention may be combined with any one or more other features of any other embodiment of the invention, without departing from the scope of the invention.  
         [0050]     Also, it should be understood that the present invention as described above can be implemented in the form of control logic using computer software in a modular or integrated manner. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will know and appreciate other ways and/or methods to implement the present invention using hardware and a combination of hardware and software. Further, those skilled in the art will appreciate that the present invention is not limited to 4-bit grayscale algorithms, 32-bit drive sequences, RGB color displays, or any other specific embodiments described herein by way of example.  
         [0051]     All references, patent applications, and patents mentioned above are herein incorporated by reference in their entirety for all purposes. None of them is admitted to be prior art to the presently claimed inventions.