Abstract:
In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches&#39; current sources and reduces the amount of area used.

Description:
TECHNICAL FIELD 
       [0001]    The invention relates generally to pipelined analog-to-digital converters (ADCs) and, more particularly, to pipelined ADCs having a three-level or tri-state digital-to-analog converter (DAC) segments or switches. 
       BACKGROUND 
       [0002]    Turning to  FIG. 1 , an example of a conventional pipelined ADC  100  can be seen. ADC  100  generally comprises a pipeline (which receives an analog input signal AIN) that provides digital signals to a digital output circuit  106  so that a digital output signal DOUT can be generated. The pipeline is generally comprised of a buffer  108 , output ADC  104 , and ADC stages  102 - 1  to  102 -N (which are generally arranged in a sequence). Each of the ADC stages  102 - 1  to  102 -N generally comprises a track-and-hold (T/H) circuit  112 , a sub-ADC  118 , DAC  120 , and a residue amplifier  122 . In operation, as shown in this example, T/H circuit  112 , for each ADC stage  102 - 1  to  102 -N, receives an input signal (i.e., signal AIN or the residue from the previous stage) and samples the signal based on clock signal CLK. Sub-ADC  118  (which also uses the clock signal CLK) converts the sample to a digital signal, which is provided to digital output circuit  106  and DAC  120 . Residue amplifier  122  then amplifies the difference between the sampled signal (from T/H circuit  112 ) and the output from DAC  120 , which is the residue signal or residue of the stage. The final ADC stage  102 -N of the sequence then provides its residue to output ADC  104 , which provides a digital signal to digital output circuit  106 . 
         [0003]    Turning now to  FIG. 2 , a more detailed example of DAC  120  can be seen. Typically, sub-ADC  118  is a coarse ADC having 2 n  levels, which can provide a control word to the DAC  120 . This control word can be thermometer coded with 2 n  levels and can be used to control DAC switches  202 - 1  to  202 -R (where each switch  202 - 1  to  202 -R can generate a “+1” or “−1”). To accomplish this, control signals (which are generally derived from the control word) can be provided to transistors QU 1  to QUR and QD 1  to QDR so as to enable current to be sourced through the “+1” or “−1” paths (through the respective current source  204 - 1  to  204 -R). A problem, however, is that, regardless of the code for DAC  120 , the noise from the current sources  204 - 1  to  204 -R can be observed at the output of residue amplifier  122 . 
         [0004]    Therefore, there is a need for a DAC with improved performance. 
         [0005]    Some other conventional circuits are: U.S. Pat. No. 6,369,744; U.S. Pat. No. 6,373,418; U.S. Pat. No. 6,587,060. 
       SUMMARY 
       [0006]    A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a logic circuit that includes: a decoder that receives a control word and that generates a plurality of control signals from the control word; and a plurality of predrivers that are each coupled to the decoder so as to receive at least one of the control signals; and a plurality of three-state digital-to-analog converter (DAC) switches, wherein each three-state DAC is coupled to at least one of the predrivers. 
         [0007]    In accordance with a preferred embodiment of the present invention, each of the plurality of three-state DAC switches further comprises: a current source; a first transistor that is coupled to the current source and an associated predriver, wherein the associated predriver controls the first transistor; a second transistor that is coupled to the current source and the associated predriver, wherein the associated predriver controls the second transistor; and a third transistor that is coupled between the current source and ground and that is coupled to the associated predriver, wherein the associated predriver controls the third transistor. 
         [0008]    In accordance with a preferred embodiment of the present invention, the first second and third transistors are NPN transistors, and wherein each of the first, second, and third transistors is coupled to the current source at emitter and to the associated predriver at its base. 
         [0009]    In accordance with a preferred embodiment of the present invention, each predriver further compromises: a first current source; a second current source; a first cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; and a second cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder. 
         [0010]    In accordance with a preferred embodiment of the present invention, the first cascaded set further comprises: a first bipolar transistor that is coupled to the decoder at its base and to an associated three-state DAC switch at its collector; a second bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a third bipolar transistor that is coupled to the decoder at its base, to the emitters of the first and second bipolar transistors at its collector, and to the first current source at its emitter; and a fourth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the first current source at its emitter. 
         [0011]    In accordance with a preferred embodiment of the present invention, the second cascaded set further comprises: a fifth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a sixth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a seventh bipolar transistor that is coupled to the decoder at its base, to the emitters of the fifth and sixth bipolar transistors at its collector, and to the second current source at its emitter; and an eighth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the second current source at its emitter. 
         [0012]    In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a digital output circuit; a pipeline having a plurality of analog-to-digital converter (ADC) stages that are coupled in together in a sequence, wherein each ADC stage includes: a track-and-hold (T/H) circuit; a sub-ADC that is coupled to the T/H circuit and to the digital output circuit; a DAC that is coupled to the sub-ADC, wherein the DAC includes: a decoder that is coupled to the sub-ADC; a plurality of predrivers that are each coupled to the decoder; and a plurality of three-state DAC switches, wherein each three-state DAC is coupled to at least one of the predrivers; and a residue amplifier that is coupled to the DAC and the T/H circuit. 
         [0013]    In accordance with a preferred embodiment of the present invention, the pipeline further comprises: a buffer that receives an analog input signal and that is coupled to the first ADC stage of the sequence; and a plurality of output ADCs that are each coupled to the last ADC stage of the sequence and to the digital output circuit. 
         [0014]    In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a digital output circuit that generates a digital output signal; a buffer that receives an analog input signal; a plurality of ADC stages that are coupled in together in a sequence, the first ADC stage of the sequence is coupled to the buffer, and wherein each ADC stage includes: a T/H circuit; a sub-ADC that is coupled to the T/H circuit and to the digital output circuit; a DAC that is coupled to the sub-ADC, wherein the DAC includes: a decoder that is coupled to the sub-ADC; a plurality of predrivers, wherein each predriver includes: a first current source; a second current source; a first cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; a second cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; and a plurality of three-state DAC switches, wherein each three-state DAC includes: a current source; a first transistor that is coupled to the current source and an associated predriver, wherein the associated predriver controls the first transistor; a second transistor that is coupled to the current source and the associated predriver, wherein the associated predriver controls the second transistor; and a third transistor that is coupled between the current source and ground and that is coupled to the associated predriver, wherein the associated predriver controls the third transistor; and a residue amplifier that is coupled to the first and second transistors from each three-state DAC switch and the T/H circuit; and an output ADC that is coupled to the last ADC stage of the sequence and the digital output circuit. 
         [0015]    In accordance with a preferred embodiment of the present invention, the first second and third transistors are bipolar transistors, and wherein each of the first, second, and third transistors is coupled to the current source at emitter and to the associated predriver at its base. 
         [0016]    In accordance with a preferred embodiment of the present invention, the first cascaded set further comprises: a first bipolar transistor that is coupled to the decoder at its base and to an associated three-state DAC switch at its collector; a second bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a third bipolar transistor that is coupled to the decoder at its base, to the emitters of the first and second bipolar transistors at its collector, and to the first current source at its emitter; and a fourth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the first current source at its emitter. 
         [0017]    In accordance with a preferred embodiment of the present invention, the second cascaded set further comprises: a fifth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a sixth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a seventh bipolar transistor that is coupled to the decoder at its base, to the emitters of the fifth and sixth bipolar transistors at its collector, and to the second current source at its emitter; and an eighth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the second current source at its emitter. 
         [0018]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0020]      FIG. 1  is a diagram of an example of a conventional pipelined ADC; 
           [0021]      FIG. 2  is a diagram of an example of DAC of  FIG. 1 ; 
           [0022]      FIG. 3  is a diagram of an example of a DAC in accordance with a preferred embodiment of the present invention; 
           [0023]      FIG. 4  is a diagram of an example of a three-state DAC switch of  FIG. 3 ; 
           [0024]      FIG. 5  is a diagram of an example of the logic circuitry of  FIG. 3 ; and 
           [0025]      FIG. 6  is a diagram of an example of a predriver of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0026]    Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
         [0027]    Turning to  FIGS. 3 and 4 , an example of a DAC  300  in accordance with a preferred embodiment of the present invention can be seen. As shown, the DAC  300  generally comprises logic circuitry  304  and three-state DAC switches  302 - 1  to  302 - k . In operation, the logic circuitry  304  can receive a control word from ADC  118  and can generate control signals (i.e., control signals P, M, and C shown in  FIG. 4 ) for each of the three-state switches  302 - 1  to  302 - k . Typically, as shown in  FIG. 4 , each three-state DAC switch  302 - 1  to  302 - k  (referred to hereinafter as  302 ) includes transistors QU QD, QG (which can be NPN transistors) and a current source  402  so that, based on the control signals P, M, and C, the three-state DAC switch  302  can generate a “+1”, “−1”, or “0” as shown in Table 1 below. 
         [0000]    
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 P 
                 M 
                 C 
                 State 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 1 
                 0 
                 0 
                 +1 
               
               
                   
                 0 
                 1 
                 0 
                 −1 
               
               
                   
                 0 
                 0 
                 1 
                 0 
               
               
                   
                   
               
             
          
         
       
     
         [0028]    To generate the control signals P, M, and C, though, the logic circuitry  304  can employ decoder  504  and predrivers  502 - 1  to  502 - k  of  FIG. 5 . The decoder  504  generally receives a control word so as to generate control signals (i.e., two) for predrivers  502 - 1  to  502 - k . Each predriver  502 - 1  to  502 - k  (as shown in this example) outputs three control signals P 1 /M 1 /C 1  to Pk/Mk/Ck, which generally corresponds to the signal P, M, and C (as shown in  FIG. 4 ). 
         [0029]    Turning now to  FIG. 6 , an example of predrivers  502 - 1  to  502 - k  (referred to hereinafter as  502 ) can be seen in greater detail. As shown, predriver  502  generally comprises sets of cascaded differential pairs of transistors Q 1  through Q 4  and Q 5  through Q 8  (which can be NPN transistors), current sources  602 - 1  and  602 - 2 , and resistors R 1  through R 3 . In operation, control signals IN 1  and IN 2  can be provided by decoder  504  with inverted control signals  IN 1    and  IN 2    being generated by inverters  606  and  608 ; alternatively, inverted control signals  IN 1    and  IN 2    can be provided by decoder  504 . Typically, control signal IN 1  and inverted control signal  IN 1    are provided to differential pairs Q 1 /Q 2  and Q 5 /Q 8 , while control signal IN 2  and inverted control signal  IN 2    are provided to differential pairs Q 3 /Q 4  and Q 6 /Q 7 . Based on the state of control signals IN 1  and IN 2  (and the associated inverter control signals  IN 1    and  IN 2   ), the predriver  502  can generate the control signals P, M, and C shown in Table 1 above. As an illustration, the derivation of control signals P, M, and C from control signals IN 1  and IN 2  for predriver  502  can be seen in Table 2 below. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 IN1 
                 IN2 
                 P 
                 M 
                 C 
               
               
                   
               
             
             
               
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 0 
                 1 
                 1 
                 0 
                 0 
               
               
                 1 
                 0 
                 0 
                 1 
                 0 
               
               
                 1 
                 1 
                 X 
                 X 
                 X 
               
               
                   
               
             
          
         
       
     
         [0030]    A reason for using this DAC  300  is that transistor QG (for each switch  302 - 1  to  303 - k ) enables a reduction in noise contribution from current source  402  (for each switch  302 - 1  to  303 - k ) for a significant portion of the transfer response. For example, with DAC  120 , there would be a noise contribution from each current source  204 - 1  to  204 -R for a 0V output, but, with DAC  300 , there would be no noise contribution from current source  402  (from any of switches  302 - 1  to  203 - k ) for a 0V output. Additionally, because of this feature, to achieve 2 n  DAC levels, 2 n−1  three-state DAC switches (i.e.,  302 - 1 ) could be used in DAC  300  instead of 2 n  DAC switches (i.e.,  202 - 1 ) in DAC  120 , which results in a reduction in area. 
         [0031]    To further illustrate some of the benefits of DAC  300  over DAC  120 , Tables 3 and 4 are provided below. For the examples shown in Tables 3 and 4, each of DAC  120  and  300  has a total of 15 states (ranging from −7 to 7). As can clearly be seen, there are 14 DAC switches (labeled  202 - 1  to  202 - 14 ) used for DAC  120 , whereas there are 7 three-state DAC switches (labeled  302 - 1  to  302 - 7 ) used for DAC. Additionally, for DAC  120  (as shown in Table 3) there are noise contributions from each of the 14 current sources (one for each DAC switch  202 - 1  to  202 - 14 ) for all of the 15 states, whereas, for DAC  300 , the noise contribution rages from zero current sources (for the “0” state) to seven (for the “−7” and “+7” states). 
         [0000]    
       
         
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 DAC State 
                 −7 
                 −6 
                 −5 
                 −4 
                 −3 
                 −2 
                 −1 
                 0 
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
                 7 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
               
               
                 202-1 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
               
               
                 202-2 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
               
               
                 202-3 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-4 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-5 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-6 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-7 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-8 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-9 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-10 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-11 
               
               
                 DAC switch 
                 −1 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-12 
               
               
                 DAC switch 
                 −1 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-13 
               
               
                 DAC switch 
                 −1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 202-14 
               
               
                 Noise 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
                 14 
               
               
                 Contribution 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 4 
               
               
                   
               
               
                 DAC State 
                 −7 
                 −6 
                 −5 
                 −4 
                 −3 
                 −2 
                 −1 
                 0 
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
                 7 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Predriver 
                 P1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 502-1 
                 C1 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
               
               
                   
                 M1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
               
             
          
           
               
                 DAC switch 302-1 
                 −1 
                 −1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
               
             
          
           
               
                 Predriver 
                 P2 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 502-2 
                 C2 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 M2 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
               
             
          
           
               
                 DAC switch 302-2 
                 −1 
                 −1 
                 −1 
                 −1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
               
             
          
           
               
                 Predriver 
                 P3 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 502-3 
                 C3 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 M3 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
             
          
           
               
                 DAC switch 302-3 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
             
          
           
               
                 Predriver 
                 P4 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 502-4 
                 C4 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 M4 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
             
          
           
               
                 DAC switch 302-4 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
             
          
           
               
                 Predriver 
                 P5 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 502-5 
                 C5 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 M5 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
               
             
          
           
               
                 DAC switch 302-5 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
               
             
          
           
               
                 Predriver 
                 P6 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 502-6 
                 C6 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
               
               
                   
                 M6 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
               
             
          
           
               
                 DAC switch 302-6 
                 −1 
                 −1 
                 −1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
               
             
          
           
               
                 Predriver 
                 P7 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 502-7 
                 C7 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
               
               
                   
                 M7 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
               
             
          
           
               
                 DAC switch 302-7 
                 −1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 Noise Contribution 
                 7 
                 6 
                 5 
                 4 
                 3 
                 2 
                 1 
                 0 
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
                 7 
               
               
                   
               
             
          
         
       
     
         [0032]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.