Abstract:
A decoder for pulse width modulated (PWM) signals comprising an integrator and a sample-and-hold circuit wherein the sample-and-hold output signal is fed back to the input of the integrator. No periodic initialization of the integrator is required. The gains of the integrator and sample-and-hold circuits and the capacitance of the integrator capacitor affect only the settling time of the decoder, not the value to which the decoder output ultimately settles.

Description:
This is a continuation of application Ser. No. 220,869, filed Dec. 29, 1980 and now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to circuits for decoding or demodulating pulse width modulated (PWM) signals. 
     2. Description of the Prior Art 
     Pulse width modulation (PWM) is a method of encoding a sequence of numerical values by modulating the duty cycle of a fixed-frequency square-wave carrier signal. More specifically, the duty cycle of each successive period of the carrier signal is modulated so as to be proportional to the corresponding numerical value in the sequence. The information represented by the sequence of numerical values is typically either a succession of distinct measurement results or else periodic samples of a continuous waveform. 
     The purpose of a PWM decoder is to recover from the modulated signal the originally encoded sequence of numerical values, typically by generating an analog signal successively proportional thereto. One known PWM decoder comprises a resistor-capacitor integrator circuit. Before each successive period of the PWM signal, the integrator is initialized by discharging the integrator capacitor. During the period, a fixed current is supplied to the integrator capacitor during the time the PWM square-wave has one of its two alternating values. At the end of the period, the capacitor voltage is proportional to the duty cycle of the PWM signal during that period, and hence to the value of the encoded information. This capacitor voltage is typically stored by a sample-and-hold circuit so that the integrator can immediately thereafter be initialized to decode the next period of the PWM signal. 
     One disadvantage of the described prior art PWM decoder is that its output voltage is inversely proportional to the capacitance of the integrator capacitor. Since it generally is impractical to manufacture capacitors to high tolerances, such a PWM decoder generally requires expensive individual calibration to attain high accuracy. In addition, the integrator capacitor is subject to thermal drift which upsets the accuracy of such calibration. 
     Another disadvantage of the described prior art PWM decoder is that it requires initialization between each period of the PWM square-wave signal by discharging the integrator capacitor. However, capacitors suffer a dielectric absorption effect that prevents them from being completely discharged during the short time available before the beginning of each period. This introduces an offset error in the decoder output. 
     SUMMARY OF THE INVENTION 
     The present invention is a decoder for pulse width modulated (PWM) signals comprising an integrator and a sample-and-hold circuit wherein the sample-and-hold output signal is fed back to the input of the integrator. 
     One advantage of the present invention is that the integrator need not be initialized periodically. If the integrator is implemented with an integrator capacitor, the capacitor need not be discharged periodically, thereby avoiding offset errors due to the dielectric absorption of the capacitor. 
     Another advantage of the present invention is that, after an initial settling time, the decoder output settles to a value independent of the gains of the integrator and sample-and-hold circuits. In particular, if the integrator is implemented with an integrator capacitor, the settled value is independent of the capacitance of the integrator capacitor. As a result, high decoder accuracy can be achieved without calibrating the decoder to compensate for capacitor tolerances. In addition, the decoder accuracy is not degraded by the capacitor&#39;s thermal drift. The only effect of capacitor deviations is a change in the decoder&#39;s settling time. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a waveform diagram of a PWM signal having a fixed repetition period T, each period beginning with a &#34;low&#34; to &#34;high&#34; transition. 
     FIG. 2 is a waveform diagram of a PWM signal having a fixed repetition period T, each period beginning with a &#34;high&#34; to &#34;low&#34; transition. 
     FIG. 3 is a block diagram of a PWM decoder according to the present invention. 
     FIG. 4 is an electrical schematic of the preferred embodiment of a PWM decoder according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before discussing the operation of the PWM decoder according to the present invention, the characteristics of a PWM signal will be reviewed. 
     FIG. 1 depicts the waveform of a typical PWM signal. The signal alternates between &#34;high&#34; and &#34;low&#34; values V H  and V L  at a fixed frequency or repetition rate 1/T, or equivalently, a fixed repetition period T. The duty cycle of each period of the PWM signal is the ratio of the time &#34;t&#34; that the PWM signal is &#34;high&#34; during the period to the total duration &#34;T&#34; of the period. For example, FIG. 1 illustrates two periods of a PWM signal having duty cycles of t 1  /T and t 2  /T during the first and second periods, respectively. 
     Each period of the PWM signal shown in FIG. 1 consists of a first time interval when the PWM signal is &#34;high&#34;, followed by a second time interval when the PWM signal is &#34;low&#34;. FIG. 2 depicts a PWM signal identical to that shown in FIG. 1 except that the first and second time intervals are reversed. In other words, each period of the PWM signal shown in FIG. 2 consists of a first time interval when the PWM signal is &#34;low&#34;, followed by a second time interval when the PWM signal is &#34;high&#34;. In both Figures, the sum of the durations of the first and second time intervals within each period is the repetition period T of the PWM signal. In practice, a PWM signal may be encoded according to either one of the two formats illustrated in FIGS. 1 and 2. 
     FIG. 3 is a block diagram of a PWM decoder according to the present invention. The PWM decoder receives a PWM signal at input terminal 10 and produces a decoder output signal V o  at output terminal 12 whose value during each period of the PWM signal is proportional to the duty cycle of the PWM signal during the preceding period. 
     The PWM decoder includes an integrator 14 that produces an output signal 16 proportional to the time integral of its input signal 18. Sample-and-hold circuit 20 produces the decoder output signal V o  by sampling the integrator output signal 16 at a time related to the beginning of each period of the PWM signal 10. By so doing, the sampling may occur at any time within the repetition period T so long as the time period between sampling, that is, the sampling period, equals the repetition period T of the PWM signal. Such can be accomplished within the sample-and-hold circuit 20 by performing the sampling at a time related to the transition of the PWM signal from its second value to its first value. Conveniently, the sampling can occur at the beginning of each period of the PWM signal concurrently with the transition of the PWM signal from its second value to its first value. In such an instance, the decoder output signal 12 equals a proportionality factor G 3  times the value of the integrator output signal 16 at the time of the most recent transition of the PWM signal 10 from its second value to its first value. 
     The integrator input signal 18 is obtained by summing a first value equal to a proportionality factor G 1  times the input signal 10 and a second value equal to a proportionality factor G 2  times the decoder output signal 12. In FIG. 3, blocks 22, 24 and 26 are used to represent the proportionality factors G 1 , G 2  and G 3 . While such proportionality factors may be implemented as separate amplifiers, blocks 22, 24 and 26 are more preferably incorporated in the circuits which implement integrator 14 and sample-and-hold 20. For example sample-and-hold 20 may include an amplifier whose gain determines the proportionality factor G 3 . Thus, such an amplifier would be an element of both sample-and-hold 20 and block 26. Another example is the preferred embodiment of integrator 14 shown in FIG. 4, which includes capacitor 28, amplifier 34, and resistors 38 and 36. Although the circuit operation will be described more fully below, it may be recognized at this point that the proportionality factors G 1  and G 2  are inversely proportional to the resistances of resistors 38 and 36, respectively. Thus, blocks 22 and 24 respectively comprise resistors 38 and 36, such resistors also being elements of integrator 14. 
     Analysis of the PWM decoder system shown in FIG. 3 reveals that, after an initial settling time, the decoder output signal converges to a value V o  proportional to the duty cycle t/T of the PWM signal and independent of the proportionality factor or gain constant G 3 . More specifically, the value to which the decoder output signal settles is given by the following equation: 
     
         V.sub.o =(-G.sub.1 /G.sub.2)[V.sub.L +(V.sub.H -V.sub.L)(t/T)](1) 
    
     If the &#34;low&#34; value V L  of the PWM signal equals zero, then the preceding equation may be simplified as follows: 
     
         V.sub.o =-V.sub.H (G.sub.1 /G.sub.2)(t/T)                  (2) 
    
     The settling time required for the value V o  of the output signal to converge to the values given in Equations (1) and (2) above is determined by the product of the proportionality constants G 2  and G 3 . The PWM decoder is said to be critically damped when the product of G 2  and G 3  equals minus one times the repetition frequency 1/T of the PWM signal. When critically damped, the settling time of the PWM decoder is zero; that is, the value V o  of the decoder output signal assumes the values given in Equations (1) and (2) above immediately after each period of the PWM signal, without any initial settling time. 
     If the product G 2  G 3  differs somewhat from the critical damping value -1/T, a settling time will be required for the output signal V o  of the PWM decoder to converge to the values given in Equations (1) and (2). The greater the difference between the product G 2  G 3  and the critical damping value, the longer the required settling time. If the product G 2  G 3  is less than or equal to -2/T or is greater than or equal to zero, the PWM decoder will be unstable and the decoder output V o  will never converge to a stable value. 
     In practice, it is very easy to insure that the PWM decoder will always be stable. Even if the repetition frequency of the PWM signal is irregular or unknown, stability may be assured by establishing the product G 2  G 3  so that its sign is negative and its magnitude is less than two times the highest possible repetition frequency of the PWM signal. 
     FIG. 4 shows the preferred embodiment of a PWM decoder according to the present invention. In the preferred embodiment, integrator 14 comprises a capacitor 28 connected between inverting input 30 and output 32 of an operational amplifier 34. Because of the high gain of operational amplifier 34, the voltage at the amplifier inverting input 30 essentially equals zero volts, and the voltage at the amplifier output 32 equals the voltage across the capacitor 28. Sample-and-hold circuit 20 samples the capacitor voltage at the beginning of each period of the PWM signal and produces decoder output voltage V o  at output terminal 12 equal to the most recently sampled value of the capacitor voltage. If the PWM decoder is being used to decode a PWM signal of a type shown in FIG. 1, the sample-and-hold circuit 20 should be triggered by each &#34;low&#34; to &#34;high&#34; transition of the PWM signal 10. To decode PWM signals of the type shown in FIG. 2, the sample-and-hold circuit should trigger on &#34;high&#34; to &#34;low&#34; transitions of the PWM signal. 
     Resistor 36 connects between amplifier inverting input 30 and decoder output 12, thereby supplying to capacitor 28 a current proportional to the decoder output voltage V o . Similarly, resistor 38 connects to amplifier inverting input 30 to supply capacitor 28 a current proportional to the duty cycle of the PWM signal received at input terminal 10. However, resistor 38 is not connected directly to input terminal 10; instead, resistor 38 is switchably connected to a reference voltage source V R  through analog switch 40. Switch 40 is controlled by the PWM signal received at input terminal 10 so as to be closed and opened, respectively, when the PWM signal has its &#34;high&#34; and &#34;low&#34; values. Switch 40 makes the decoder operation independent of the amplitude of the incoming PWM signal by effectively replacing it with one having a fixed high value V R  and a fixed low value of zero. 
     In operation, the decoder output voltage V o  converges after an initial settling period to the value given by the following equation wherein R 1  and R 2  denote the resistances of resistors 38 and 36, respectively: 
     
         V.sub.o =-V.sub.R (R.sub.2 /R.sub.1)(t/T)                  (3) 
    
     Equation (3) shows that the decoder output voltage V o  is directly proportional to the duty cycle t/T of the PWM signal and is independent of the capacitance of capacitor 28. 
     The values of resistor 36 and capacitor 28 determine the stability and settling time of the PWM decoder shown in FIG. 4. The decoder will be critically damped and the settling time will be zero if the product of the resistance of resistor 36 and the capacitance of capacitor 28 equals the repetition period T of the PWM signal. The settling time of the decoder will increase as this resistance-capacitance product deviates from the critically damped value. However, the decoder will be stable so long as the resistance-capacitance product is greater than one-half the critically damped value, that is, greater than one-half the repetition period T. 
     An advantage of the described PWM decoder is that, unlike prior art designs, it does not require initialization by periodically discharging the integrator capacitor. The present invention thereby avoids offset errors inherent in prior art designs because of dielectric absorption which prevents the integrator capacitor from being completely discharged. 
     Another advantage of the described PWM decoder is that the value to which the decoder output voltage settles is independent of the capacitance of the integrator capacitor. As a result, the accuracy of the decoder will not be degraded by the use of an integrator capacitor subject to thermal drift and having only ordinary capacitance tolerances. 
     Another advantage of the present invention is that the decoder output is proportional to the true duty cycle t/T. In contrast, many prior art designs produce an output proportional only to the duration &#34;t&#34; of the &#34;high&#34; interval within each period of the PWM signal, independent of the repetition period T.