Abstract:
To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a method of forming semiconductor devices on a semiconductor wafer. More specifically, the invention relates to forming through via metallization. 
         [0003]    Silicon semiconductors containing through silicon (Si) vias are used in a variety of technologies, from imaging products and memory to high-speed logic and high voltage device products. One technology that relies heavily on vias formed through silicon semiconductor wafers (TSVs) is a three dimensional (3D) integrated circuit (IC). 3D ICs are created by stacking thinned semiconductor wafer chips and interconnecting them with through-silicon vias (TSVs). 
       SUMMARY OF THE INVENTION 
       [0004]    To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material. 
         [0005]    In another manifestation of the invention semiconductor structure with conductive fillings in through silicon vias formed by a method is provided. A dielectric layer is deposited over the through silicon vias. A tungsten containing barrier layer by CVD or ALD is deposited over the dielectric layer. The through silicon vias are filed with a conductive material. 
         [0006]    In another manifestation of the invention, a semiconductor structure is provided. A silicon substrate is provided with through silicon vias features etched into the silicon substrate. A dielectric layer is over the through silicon via features. A barrier layer comprising tungsten is over the dielectric layer;. A conductive filling is within the via features. 
         [0007]    These and other features of the present invention will be described in more details below in the detailed description of the invention and in conjunction with the following figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: 
           [0009]      FIG. 1  is a flow chart of an embodiment of the invention. 
           [0010]      FIGS. 2A-E  are schematic views of the formation of structures using the inventive process. 
           [0011]      FIG. 3  is a flow chart illustrating different embodiments of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0012]    The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention. 
         [0013]      FIG. 1  is a high level flow chart of an embodiment of the invention. Through silicon vias are provided (step  104 ). A dielectric (most often silicon oxide or silicon oxide based) layer is formed over the through silicon vias (step  108 ). A barrier layer is formed over the dielectric layer (step  112 ). An intermediate adhesion transition layer is formed over the barrier layer (step  114 ). The through silicon vias are filled (step  116 ). 
         [0014]    In a preferred embodiment of the invention, through silicon vias in a substrate are provided (step  104 ).  FIG. 2A  is a schematic cross-sectional view of a stack  200  with a substrate  204  with through silicon vias  208 . The through silicon vias  208  may pass entirely through the silicon substrate  204  or partially through the silicon substrate  204 . Normally, if the through silicon vias do not pass entirely through the silicon substrate  204 , a subsequent process is provided to remove the parts of the silicon substrate through which the through silicon vias  208  do not pass, so that the through silicon vias  208  pass through the remaining substrate. Preferably, the through silicon vias have a width less than 15 μm. More preferably, the through silicon vias have an aspect ratio greater than 8:1. Preferably, the through silicon vias have a depth greater than 20 μm. 
         [0015]    A dielectric layer is formed over the through silicon vias (step  108 ).  FIG. 2B  is a schematic cross-sectional view of the stack  200  after a silicon oxide layer  212  is formed over the through silicon vias  208 . Silicon oxide, the most commonly used dielectric, can be deposited by CVD or ALD processes or thermally grown from Si in an oxidizing atmosphere. 
         [0016]    A barrier layer is formed over the silicon oxide layer (step  112 ).  FIG. 2C  is a schematic cross-sectional view of the stack  200  after the barrier layer  216  is formed over the silicon oxide layer  212 . Preferably, the barrier layer comprises at least one of tungsten nitride, TiN, TiW, TiSN, WSiN, or RuTiN. More preferably, the barrier layer comprises &gt;10% tungsten by weight. The barrier can also be deposited with PVD, CVD and ALD processes though the latter two are preferred due to the higher conformality of the layer they can provide and hence CVD and ALD provide plating even in very high aspect ratio vias (&gt;17:1). 
         [0017]    An intermediate adhesion transition layer is formed over the barrier layer (step  114 ). Preferably, the intermediate adhesion transition layer is formed by an electroless deposition (ELD), atomic layer deposition (ALD), or chemical vapor deposition (CVD) process. More preferably, the intermediate adhesion transition layer is made of nickel, cobalt, palladium or a combination of these or is an alloy of nickel, cobalt, or palladium. In this example, the intermediate adhesion transition layer is nickel or a nickel alloy, which as a thickness of 50 Å to 5000 Å and more preferably 100 Å to 500 Å. An example of a recipe for providing the intermediate adhesion transition layer using ELD is cleaning the tungsten nitride (WN, where tungsten nitride is a material of tungsten and nitrogen, where the ratio of tungsten to nitrogen may be one of many different ratios) surface (if needed), deionized water (DI) rinsing the surface, applying activation solution to the surface to make the surface catalytically active, rinse the activated surface with DI water, acid or complexing agent containing solution, further rinsing the surface with DI water (if non-DI rinse was used after activation), electroless plating Ni or Ni alloy on the activated surface. The recipe may contain optional spin-off and/or drying step after each process step.  FIG. 2D  is a schematic cross-sectional view of the stack  200  after the intermediate adhesion transition layer  220  is formed over the barrier layer  216 . In other embodiments the intermediate adhesion transition layer may be tungsten silicide (WSi x  where x=1 or 2) and tungsten titanium (WTi x ). 
         [0018]      FIG. 3  is a chart of different methods of metalizing the through silicon vias. In this embodiment, after a tungsten nitride barrier is formed (step  304 ) an alloy seed layer is deposited by an ELD process (step  312 ). The ELD solution has a pH between 4.0 and 12.5 and more preferably between 7.5 and 10.5. The deposition is done at temperature between room temperature to 95° C. and more preferably between 65° C. to 85° C. The solution contains at least one or more metal compounds (such as but not limited to chloride or sulfate salts of the metal(s)), pH adjustor(s) which may also function as a complexing agent, additional complexing agent if needed, and one or more reducing agents. The electroless plating solution can also contain other additives such as surfactants, stabilizers, stress reducers, etc. An electroplating copper process (ECP) is used to fill the through silicon vias (step  324 ). The electroplating copper or copper alloy solution used for filling is acidic and operates at temperatures between 15° C. to 90° C., and more preferably between 20° C. and 45° C. The solution contains at least one or more metal compounds (such as but not limited to chloride or sulfate salts of the metal(s)), pH adjustor(s) and the necessary additives from the group of suppressors, accelerators and levelers that provides bottom up fill.  FIG. 2E  is a schematic cross-sectional view of the stack  200  after the through silicon vias are filled with a copper or copper alloy  224  using an ECP process. In this embodiment, the copper or copper alloy  224  outside the through silicon vias  208  has a thickness of less than  200  Å. A planarization process may be used to planarize the stack  200  to remove the copper or copper alloy  224 , the seed layer  220 , barrier layer  216 , and silicon oxide layer  212  above the through silicon vias  208 . 
         [0019]    As shown in  FIG. 3 , other processes may be used for metalizing the through silicon vias, after forming the tungsten nitride barrier layer (step  304 ). For example, a tungsten seed layer may be formed using a CVD process (step  308 ), followed by either an ELD metal or metal alloy layer (step  316 ) or an electroplating copper or copper alloy process (ECP) seed deposition (step  320 ). The ELD of a metal or metal alloy layer (step  316 ) would be followed by an electroplating copper or copper alloy seed deposition (step  328 ), which would be followed by an electroplating copper or copper alloy via fill (step  336 ). In the alternative the ELD of the metal or metal alloy layer (step  316 ) may be followed by an ELD seed layer deposition (step  330 ), which is then followed by an electroplating copper or copper alloy via fill (step  336 ). The ECP seed deposition (step  320 ) would be followed by an electroplating copper fill (step  332 ). In another embodiment, the ELD of a Ni alloy (step  312 ) may be followed by the ECP seed deposition of copper or copper alloy seed (step  320 ) followed by an electroplating copper or copper alloy fill (step  332 ). 
         [0020]    The use of a tungsten nitride barrier layer provides a lower cost barrier layer on which direct metal deposition may be performed with good adhesion. In this example, the pure nickel or nickel alloy seed layer may be directly deposited in the WN barrier layer. 
         [0021]    Silicon and silicon oxide have a coefficient of thermal expansion of about 4 ppm/° C. and less than 1 ppm/° C., respectively. Copper has a coefficient of thermal expansion of about 17 ppm/° C. Tungsten and tungsten nitride have a thermal expansion coefficients of about 4.5 ppm/° C. and 5.8 ppm/° C., respectively. Nickel and Ni alloys have a thermal expansion coefficient of 10-13 ppm/° C. Providing adjacent layers of materials with large differences between coefficients of thermal expansion increases stress between the layers as the temperature of the layers changes. By providing an ELD Ni or Ni alloy seed layer  220  between the barrier and the copper fill  224 , stress created by thermal expansion is reduced. In addition, nickel has good adhesion to tungsten, tungsten nitride, and copper. 
         [0022]    In other embodiments, the barrier layer comprises a combination of one or more of W, Ti, Ta, N, Si, O, or C. In other embodiments, the intermediate adhesion transition layer comprises a combination of one or more of W, Co, Ru, Ni, Pd, or any transition metal/metal alloys with reducible oxide (cobalt, ruthenium, etc.), catalytic activity (cobalt, ruthenium, palladium, etc.), or low resistivity (&lt;20 micro Ohms cm). 
         [0023]    Embodiments of the invention allow for the filling of through silicon vias at a reduced cost. More specifically, some embodiments of the invention may provide a cost reduction of more than 50% over conventional TSV metallization processes. In addition, various embodiments can provide a uniform barrier layer, even where aspect ratios of the TSV are 20:1 or higher. 
         [0024]    By replacing conventional PVD barrier/seed metallization processes with ALD and/or CVD and/or ELD and ECP processes costs may be reduced while being able to provide processes for through silicon vias of smaller diameters and higher aspect ratios. This is because CVD and ELD processes are more conformal and less sensitive to aspect ratio. Embodiments of the invention also lower planarization, such as chemical mechanical polishing (CMP), costs by reducing field thicknesses to less than 1 μm. 
         [0025]    In another embodiment, a first intermediate adhesion transition layer of Ni, Co, or Pd is formed using an electroless process. A second intermediate adhesion transition layer is then formed comprising copper using an electroless process. 
         [0026]    Other embodiments of the invention may provide additional liner, barrier or seed layers. Embodiments may use an ELD barrier layer of a Co or Ni alloy, where the alloying elements preferably comprise Co, Ni, Fe, W, Mo, P, B, Re, Mn, Cr, Ge, Sn, In, Ga, or Cu. Embodiments of the invention use an electroless liner or seed layer comprising a Co, Ni, or Cu alloy, where the alloying elements preferably comprise Co, Ni, Fe, W, Mo, P, B, Re, Mn, Cr, Ge, Sn, In, or Ga. In other embodiments, the electroplating seed can be metals or metal alloys that have low solubility in conventional acidic electroplating solutions used for filling TSV structures. For example, the seed can be Cu or Cu alloy, but is not restricted to CuNi, CuCo, CuMn, CuSn, and CuAg, but may be other metal alloy combinations, such as Ni, NiCo, Pd, Ru, etc. This allows the electroplated layer to be nearly the same as the electroplated seed. 
         [0027]    While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, and various substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and various substitute equivalents as fall within the true spirit and scope of the present invention.