Abstract:
An exciting circuit for a stepper motor requiring only a single decoder device yet being capable of controlling the speed of the stepper motor using plural different modes of excitation. A memory stores digital data representing a predetermined sequence of activation of the exciting coils. A counter drives the address input port of the memory in accordance with its output count. A clock signal generator supplies clock pulses to the counter in one of two patterns, representative of high and low speeds. The first of the patterns contains clock pulses spaced at equal intervals with a frequency such that the stepper motor can follow the corresponding changes in activation of the exciting coils of the motor. In the second pattern, the clock signals are supplied in bursts, the internal frequency of which is higher than the stepper motor can follow. In this latter case, portions of the normal excitation sequence are effectively omitted, thereby driving the motor at a different speed.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a stepper motor exciting circuit. Stepper motors have been extensively employed as a source of rotary power for conveying a recording sheet. A facsimile system is an example where such motors are used. In a recording sheet conveying mechanism, in order to reduce the recording time, the recording sheet is preferably moved at high speed for lines in which no data is recorded. For this purpose, it is necessary to provide a stepper motor exciting circuit which can switch the stepper motor among a plurality of speeds. 
     FIG. 1 shows a conventional stepper motor exciting circuit of this type. In this circuit, first terminals of two-phase exciting coils 1 and 2 are connected through a resistor 3 to a power supply terminal 4, while the other terminals of the exciting coils are selectively grounded through respective switching transistors 5 and 6. Similarly, first terminals of two-phase exciting coils 7 and 8 are connected through a resistor 9 to the power supply terminal 4, and the other terminals thereof are selectively grounded through respective switching transistors 11 and 12. The bases of the switching transistors 5, 6, 11 and 12 are connected to corresponding terminals of a changeover circuit 13. Four output terminals of a first decoder 14 and four output terminals of a second decoder 15 are connected to the input side of the changeover circuit 13. A counter 17 counts pulses of a clock signal 16 and supplies a signal representing the count value to the decoders 14 and 15. 
     In accordance with the count value of the counter 17, the first decoder 14 outputs a signal for &#34;two-phase&#34; excitation, for instance, while the second decoder 15 outputs a signal for &#34;W1-2 phase&#34; excitation, for instance. The changeover circuit 13 provides the output signal of the first decoder 14 or the output signal of the second decoder 15 at the four output terminals thereof according to an excitation changeover signal 18. As a result, the excitation system of the stepper mtor can be switched between the &#34;two-phase&#34; excitation mode or to the &#34;W1-2 phase&#34; excitation mode to change the speed of rotation of the stepper motor. 
     This stepper motor exciting circuit is disadvantageous in that it is intricate, and accordingly expensive, because it is necessary to provide as many decoders as there are modes of excitation. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing, an object of the invention is to provide a stepper motor exciting circuit in which only one type of decoder is needed to switch among a plurality of excitation modes. 
     The foregoing object of the invention has been achieved by the provision of a stepper motor exciting circuit which, according to the invention, includes clock pulse generating means for generating selectively a high speed pulse signal which the rotor of the step motor cannot follow and a low speed pulse which the rotor can follow, a hexademical counter for counting the pulses of the pulse signals generated by the clock pulse generating means, and decoder means for selecting an excitation phase and controlling phase currents with a &#34;W1-2 phase&#34; excitation sequence according to the count value of the counter so that portions of the phase excitation sequence generated when the clock pulse generating means produces the high speed clock pulse are effectively skipped, whereby an optimal excitation system can be selected. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a conventional stepper motor exciting circuit; 
     FIG. 2 is a circuit diagram of a stepper motor exciting circuit according to the invention; 
     FIG. 3 is a circuit diagram showing an example of a clock generator used in the circuit of FIG. 2; 
     FIGS. 4a-4c are waveform diagrams used for a description of the operation of the clock generator of FIG. 3; and 
     FIGS. 5a-5d are timing charts showing the relationship in time between motor clock signals and excitation phases. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention will now be described in more detail with reference to preferred embodiments. 
     FIG. 2 shows a stepper motor exciting circuit constructed in accordance with the teachings of the invention. In this exciting circuit, a chopper constant current device system is employed in order to improve the efficiency of the power source. That is, instead of the two resistors 3 and 9 in FIG. 1, two chopper transistors 21 and 22 are provided. The collectors of the chopper transistors 21 and 22 are connected to one terminal 23 of a motor driving power source. The emitter of the first chopper transistor 21 is connected to first terminals of bifilar-wound &#34;A phase&#34; and &#34;A phase&#34; exciting coils 24 and 25. Similarly, the emitter of the second chopper transistor 22 is connected to first terminals of bifilar-wound &#34;B phase&#34; and &#34;B phase&#34; exciting coils 26 and 27. The other terminals of the exciting coils 24 and 25 are connected, respectively, through switching transistors 28 and 29 to one terminal of a first current detecting resistor 31, the other terminal of which is grounded. Similarly, the other terminals of the exciting coils 26 and 27 are connected, respectively, through switching transistors 32 and 33 to one terminal of a second current detecting resistor 34, the other terminal of which is grounded. The voltages developed across the current detecting resistors 31 and 34 are applied to respective inputs of first and second comparators 35 and 36 where the voltages are compared with reference voltages provided by first and second reference voltage changeover circuits 37 and 38. The outputs of the comparators 35 and 36 are applied to turn on and off the first and second chopper transistors, respectively, and hence control the currents flowing through the exciting coils 24 through 27. 
     The on-off control of the switching transistors 28, 29, 32 and 33 and the voltage changeover control of the first and second reference voltage changeover circuits 37 and 38 are instructed by a read-only memory 41, the address input port of which is connected to a counter 42. When a motor clock signal 45, which is outputted by a clock generator 44 in response to a speed changeover signal 43, changes state, the counting speed of the counter 42 changes, and hence the control operation of the read-only memory 41 is changed. 
     FIG. 3 shows the clock generator 44 in more detail. The clock generator 44 includes a binary counter 441 to the clock terminal C of which a basic clock signal 51 (waveform (a) in FIG. 4) is applied. First, second and third clock signals 52, 53 and 54, which are obtained by frequency dividing the basic clock signal 51 by factors of 1/8, 1/16 and 1/64, respectively, are provided at corresponding first, second and third output terminals Q 1 , Q 2  and Q 3  of the binary counter. The clock signals 52, 53 and 54 are applied to a three-input AND gate 442 where they are ANDed to produce a fourth clock signal 55. The fourth clock signal 55 is applied to first input terminals of a two-input AND gate 443 and a three-input AND gate 444. A changeover signal 43 is applied to an inverter 445, which in turn outputs a changeover signal 56. The changeover signal 56 is applied to the remaining input terminal of the AND gate 443. The changeover signal 43 and the basic clock signal 51 are applied to the remaining input terminals of the AND gate 444. 
     When the stepper motor operated by this circuit is to be driven at low speed, the changeover signal 43 is set to the low (L) logical level, whereupon the two-input AND gate 443 outputs a &#34;W1-2 phase&#34; excitation clock signal 57 (waveform (b) of FIG. 4). When the stepper motor is to be driven at high speed, the changeover signal 43 is raised to the high (H) logical level, and a &#34;two-phase&#34; excitation clock signal 58 (waveform (c) in FIG. 4) is outputted. These signals are ORed by an OR gate 446, which outputs, in turn, a motor clock signal 45 which is supplied to the counter 42 (FIG. 2). 
     The operation of the circuit in the case of driving the stepper motor at low speed with the above-described clock generator 44 will be described. In this operation, the &#34;W1-2 phase&#34; excitation clock signal 57 is supplied, as the motor clock signal 45, to the counter 42, where the pulses of the signal 57 are counted. The counter 42 is a hexadecimal counter which counts the pulses of the motor clock signal 45 at equal intervals. The count value is applied to the read-only memory 41. In response to the count value, the read-only memory 41 outputs signals for selecting a excitation phase and setting a phase current with a &#34;W1-2 phase&#34; sequence. 
     FIG. 5 shows the relationships between the motor clock signal 45 and the excitation phases. As the motor clock signal 45 contains pulses at constant intervals (as shown at (b) in FIG. 5), the excitation phases are activated one by one, as shown at (a) in FIG. 5. For instance, when the read-only memory 41 selects an excitation from of BA phase in response to the motor clock signal pulse which occurs at the time instant t 1 , the following signal states are provided at the output terminals O 1  through O 6  of the read-only memory 41: O 1  =H, O 2  =L, O 3  =L, O 4  =H, O 5  =H, and O 6  =L. 
     In this case, the signals at the first and fourth output terminals O 1  and O 4  are at the &#34;H&#34; level, and therefore the switching transistors 28 and 33 are rendered conductive (on) so that the &#34;A phase&#34; and &#34;B phase&#34; coils are excited. As the signal at the fifth output terminal O 5  is at the &#34;H&#34; level, the first reference voltage changeover circuit 37 applies the higher of the two different reference voltages to the first comparator 35. Comparing this reference voltage to a voltage which is developed across the current detecting resistor 31, the first comparator 35 performs a constant current control operation which causes a current of one ampere to flow in the &#34;A phase&#34; excitating coil 24. On the other hand, the signal at the sixth output terminal O 6  is at the &#34;L&#34; level. Therefore, the second comparator 36 compares the lower reference voltage to a voltage which is developed across the current detecting resistor 34 and accordingly performs a constant current control operation such that a current of 0.4 ampere flows in the &#34;B phase&#34; exciting coil 33. Numerical values indicated in the lower portion of part (a) of FIG. 5 represent phase currents. When a motor clock signal (45) pulse occurs after a first period of time T 1  (at the time instant t 2 ), the excitation phase and the phase current are changed. In this case, the following signal states are present at the output terminals O 1  through O 6  : O 1  =H, O 2  =L, O 3  =L, O 4  =L, O 5  =H, and O 6  =(not applicable). (It is unnecessary to indicate the level of the signal at the output terminal O 6  because the &#34;B phase&#34; and &#34;B phase&#34; coils are not excited in this case.) 
     Similarly, as in the above-described case, whenever a pulse of the motor clock 45 occurs, the excitation phase and the phase current are changed. Thus, the stepper motor is driven at low speed according to the &#34;W1-2 phase&#34; excitation mode. 
     The operation of the circuit in the case of driving the stepper motor at high speed will now be described. When the changeover signal 43 is at the &#34;H&#34; level, the &#34;two-phase&#34; excitation clock signal 58 is supplied as the motor clock signal 45 to the counter 42, which counts the pulses of the signal 45. In this case, four motor clock signal pulses are provided in the form of a high frequency bunch, as shown at (c) in FIG. 5. Accordingly, the read-only memory 41 outputs signals which cause selection of phase excitation and setting a phase current such that excitation in the &#34;W1-2 phase&#34; mode is skipped every fourth step. 
     When four clock pulses are produced at high speed under the condition that, for instance, an excitation form of AB phase in which a current of one ampere flows both in the &#34;A phase&#34; exciting coil 24 and in the &#34;B phase&#34; exciting coil 26 (part (d) in FIG. 5), the read-only memory 41 sequentially changes the signals provided at the output terminals O 1  through O 6  at a corresponding speed. If the four-clock-pulse generation interval is set to several microseconds, the stepper motor will not be able to follow this change, and accordingly excitation of the stepper motor will be carried out with the excitation form and the phase current which are selected by the fourth clock pulse only; that is, the stepper motor is excited in an excitation form of BA phase in which case a phase current of one ampere flows in the &#34;B phase&#34; exciting coil 26. 
     Thereafter, similar to the above-described case, whenever four motor clock pulses are produced as described above, the excitation form of the stepper motor is changed; that is, the excitation takes the forms of AB phase, BA phase, AB phase, etc. Thus, substantially &#34;two-phase&#34; excitation sequence is carried out. 
     On the other hand, a two-bit monitor signal 59, which represents four variations of phase current, is outputted upon the remaining two output terminals O 7  and O 8 . The monitor signal 59 is applied to a control circuit (not shown) for monitoring the phase excitation. In the case of single phase excitation, the control circuit supplies two dummy pulses to the counter 42 for the above-described two-phase excitation. Thereafter, four motor clock pulses 45 are produced every time, so that the stepper motor is driven with the sequence appropriate for single-phase excitation, that is, &#34;A phase&#34;, &#34;B phase&#34;, &#34;A phase &#34; and &#34;B phase&#34;. 
     As has been described in detail, according to the invention, the pulse sequence for &#34;W1-2 phase&#34; excitation is partially omitted for low speed operation, whereby the step motor can be driven according to various excitation systems and according to a given load and a desired speed of rotation. Hence, an optimum driving form is provided. 
     In the description above, the &#34;W1-2 phase&#34; excitation sequence is skipped every fourth step; however, the invention is not limited thereby or thereto. For instance, &#34;1-2 phase&#34; excitation can be carried out by generating two motor clock signal pulses at high speed for every pulse period.