Abstract:
overvoltage protector uses a low-power shunt regulator to provide precise overvoltage protection at low voltages. The shunt regulator communicates with the current limiter to the input voltage allowing precise current measurement while protecting the shunt regulator from excessive power consumption.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     Background of the Invention 
       [0001]    The present invention relates to output voltage limiters for power supplies and the like and in particular to a low-voltage output limiter with high precision. 
         [0002]    Electrical circuits normally operate in conjunction with a power supply delivering required voltage and current levels to the electrical circuitry. Particularly in safety and high reliability applications, it may be desirable that the power supply include output limiting circuitry for controlling output power from the power supply, for example, in the event of a short circuit across power supply output terminals or an increase in power supply voltage such as would cause the electrical circuit to consume additional power. In some applications, the outlet limiting circuitry must operate accurately at low voltages, for example, on the order of 3 to 4 volts (with 5% tolerance). while accommodating much higher voltages of up to 36 volts. 
         [0003]    One way of providing such output limiting circuitry is to use a zener diode to control the biasing of a series transistor through which current must pass horn the power supply to the electrical circuitry. As the voltage rises the zener diode will limit the biasing of the series transistor thus decreasing the current flow between the power supply and electrical circuitry for protection. Such an approach normally requires that the zener diodes be screened and tested for low leakage current in order to provide such accurate level protection across a wide-temperature, range required of industrial applications. 
         [0004]    An alternative is to use a specialized integrated circuit that can monitor the output voltage of the power supply up to the highest expected voltage (e.g., 36 volts). Such integrated circuits may provide a precise comparator producing a switched output at a desired limited voltage. The switched output can then control a series transistor in place of the zener diode. The problem to this approach is that such integrated circuits that can tolerate high operating voltages are expensive 
       SUMMARY OF THE INVENTION 
       [0005]    The present invention provides an output protection circuit that uses, a lower-cost, power integrated circuit such as a shunt regulator to provide accurate sensing of overvoltage conditions. The shunt regulator is protected from excessive power consumption from high input voltages by a current limiter allowing a low-voltage part to be used to effectively sense high input voltages without being exposed directly to high input voltages. 
         [0006]    In one embodiment, the invention provides an overvoltage protection circuit having an input terminal for receiving power from a power source providing a voltage and an output terminal for providing power to an electrical circuit downstream from the overvoltage protection circuit. A series limiting solid-state device, such as, but not limited to, a transistor, operating in a continuous fashion or as a switching device, is positioned between the input terminal and output terminal for controlling current flow there between and a shunt regulator provides a signal controlling the bias of the series limiting device to decrease current flow through the series limiting device when the voltage at the input terminal rises above a predetermined voltage threshold measured by the shunt regulator. A first current limiter communicates between the shunt regulator and the input terminal to protect the shunt regulator from voltages on the input terminal higher than a voltage rating of the shunt regulator. 
         [0007]    It is thus a feature of at least one embodiment of the invention to allow the use of a flow power shunt regulator to provide precise low-voltage overvoltage protection without damage to the shunt regulator with occasional expected high voltages. 
         [0008]    The shunt regulator may communicate with the bias control transistor through a second current limiter. 
         [0009]    It is thus a feature of at least one embodiment of the invention to protect the shunt regulator from high voltages associated with controlling the series limiting device. 
         [0010]    In one embodiment, both of the first current limiter and second current limiter may operate as constant current sources. 
         [0011]    It is thus a feature of at least one embodiment of the invention to provide for a precise switching point for the overvoltage control despite removal of the shunt regulator from direct control of the series limiting device. This can be contrasted to a resistor network which would provide a lower gain control path. 
         [0012]    These particular objects and advantages may apply to only some embodiments falling within the claims and thus do not define the scope of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a diagram of an overvoltage protection circuit positionable between the power supply in load circuitry comprised of two overvoltage protection modules each using a shunt regulator as shown in successive expansions. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0014]    Referring now to  FIG. 1 , an overvoltage protection circuit  10  may be positioned between a power supply  12  and load circuitry  14  to protect the load, circuitry  14  from excessive power consumption cost, for example, by failure of the power supply  12  such as may produce high voltages. Generally the higher voltages received correctly by the load circuitry  14  may exceed voltage ratings of components on circuitry  14  or may cause excessive power consumption that can be damaging to those components. Generally, the overvoltage protection circuit  10  includes an input terminal  16  receiving power from the power supply  12  and an output terminal  18  for providing output power to the circuitry  14 . 
         [0015]    In one embodiment of the present invention the overvoltage protection circuit  10  may include a first overvoltage protection, circuit  20   a  connected in series with a second overvoltage protection circuit  20   b . Generally both overvoltage protection circuits  20  operate at the same voltage threshold and provide redundancy in the event of failure of one or the other. Current flowing from the power supply  12  must flow through both overvoltage protection circuits  20  before reaching the load circuitry  14 . 
         [0016]    Each overvoltage protection circuit  20  may in mm provide an input terminal  22  and an output terminal  24  with the input terminal  22  of overvoltage protection circuit  20   a  connected with input terminal  16  and the output terminal  24  of overvoltage protection circuit  20   b  connected to output terminal  18 . The output terminal  24  of overvoltage protection circuit  20   a  connects to the input terminal  22  of overvoltage protection circuit  20   b.    
         [0017]    In series between the input terminal  22  and output terminal  24  is a series current limiting solid-state device  26 . In one embodiment, series current limiting solid state device  26  may be a metal oxide silica and field effect transistor (MOSFET) having a source connected to input terminal  22  and a drain connected to output terminal  24 . The gate may connect through a bias resistor  28  to ground. The biasing of the series current limiting solid state device  26  is provided by a PNP transistor  30  having its emitter connected to the junction between bias resistor  28  and the gate of series current limiting solid state device  26 . The emitter of PNP transistor  30  is connected to the input terminal  22 . When transistor  30  conducts, it raises the voltage on bias resistor  28  turning off or reducing the current flow through the source and drain of, series current limiting solid state device  26 . 
         [0018]    The transistor  30  may be controlled by a shunt current regulator  32 , for example, a programmable precision reference shunt regulator manufactured by a variety of companies under the tradename of NCV431. Such a shunt current regulator  32  has three terminals only including a cathode terminal, a reference terminal, and an anode terminal. The latter is connected to ground and the reference terminal connects to a voltage derived from the voltage at the, input terminal  22  through a resistive divider comprised of resistors  34  and  36  in series connection with resistor  34  connecting to input terminal  22  and then to a junction  38  with resistor  36  which in turn leads to ground. This resistor divider may, for example, reduce the voltage on the input terminal  22  by two-thirds so as to stay comfortably within the voltage limits of, the shunt current regulator  32   
         [0019]    As is generally understood in the art, a series shunt regulator may provide for an internal transistor, for example, a PNP transistor  40  conducting current between the cathode and anode as biased by an operational amplifier  42 . The operational amplifier  42  receives at its positive or noninverting input a signal from the reference input and edits negative input at a precision voltage reference  44  biased with respect to ground on the anode. When the voltage on the reference exceeds the voltage of the precision voltage reference  44 , the transistor  40  conducts. The operational amplifier  42  will have a high gain so that the operation of the transistor  40  is to turn on sharply when the voltage programmed into the shunt current regulator  32  is exceeded at the reference input. 
         [0020]    Generally the amount of current received at the cathode must be limited so as not to exceed the power rating of the shunt current regulator  32  and thus the shunt current regulator  32  could not normally be connected directly to the base of bias transistor  30 . For this reason it connects through a current limiter  54  formed by JFET  50  providing a path from the base of transistor  30  through the drain and source of JFET  50  then through a current sensing resistor  52  to the cathode of the shunt current regulator  32 . The gate of the JFET  50  is connected directly to the cathode of the shunt current regulator  32  and in this way the JFET  50  is programmed to operate as a substantially constant current source with increased current through current sensing resistor  52  providing a biasing of the MET  50  tending to turn it toward the off state. In this way the amount of current received by the cathode of the shunt current regulator  32  is limited. The cathode of shunt current regulator  32  also connects with a current limiter circuit  56  formed of a JFET  58  and connecting between the input terminal  22  and the cathode of the shunt current regulator  32 . The WET  58  provides a path from input terminal  22  through its source and drain and then through current sensing resistor  62  to the cathode of shunt current regulator  32 . The gate of JFET  58  connects to the cathode of shunt current regulator  32  to provide feedback that tends to provide constant current flow through the NET  58 . En this way high voltages on input terminal  22  do not create excessive current input to the cathode of the shunt current regulator  32 . 
         [0021]    Certain terminology is used herein for purposes of reference only, and thus is not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, “bottom” and “side”, describe the orientation of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import. Similarly, the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context. 
         [0022]    When introducing elements or features of the present disclosure and the exemplary embodiments, the articles “a”, “an,” “the” and “said” are intended to mean that there are one or more of such elements or features. The terms “comprising”, “including” and “having” are intended to be inclusive and mean that there may be additional elements or features other than, those specifically noted. It is further to be understood that the method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed. 
         [0023]    It is specifically intended that the present invention not be limited to the embodiments and illustrations contained herein and the claims should be understood to include modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments as come within the scope of the following claims. All of the publications described herein, including patents and non-patent publications are hereby incorporated herein by reference in their entireties.