Abstract:
One embodiment of the invention is directed to a method of extending the input range of an analog-to-digital converter (ADC) having a nominal input voltage range. The method comprises an act of mapping an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code. Another embodiment of the invention is directed to an apparatus comprising an ADC having a nominal input voltage range, wherein the ADC is adapted to map an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit, under 35 U.S.C. §119(e), of the filing date of U.S. provisional application Ser. No. 60/360,499 entitled “Methods for Extending Offset Correction Range in Pipelined ADC System,” filed Feb. 28, 2002 and incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention is directed generally to the field of analog-to-digital converters. In particular, the invention relates to methods and apparatuses for analog-to-digital converters having an increased input range. 
   DESCRIPTION OF THE RELATED ART 
     FIG. 1A  illustrates a typical signal processing system  1 . Signal processing system  1  includes an analog signal processor (ASP)  3 , an analog-to-digital converter (ADC)  5 , and a digital signal processor (DSP)  7 . ASP  3  processes signals of an analog format, and ADC  5  converts the analog signals into a digital format. DSP  7  processes the signals of a digital format. 
   Offsets often exist in signal processing system  1 , which may result in a difference between a desired output code of ADC  5  and the actual output code for a given reference input. These offsets may be generated in ASP  3 , ADC  5 , and/or may exist at the input of ASP  3 . The offset that may exist at the input of ASP  3  is represented in  FIG. 1A  as V OS, INPUT , the offset that may be generated in ASP  3  is represented in  FIG. 1A  as V OS, ASP , and the offset that may be generated in ADC  5  is represented in  FIG. 1A  as V OS, ADC . Offsets V OS, INPUT , V OS, ASP , and V OS, ADC , are collectively represented in equivalent form at the input of ADC  5  as equivalent voltage offset V OS, EQ  in FIG.  2 . 
   It is often desirable to cancel this offset to simplify the interface between ADC  5  and DSP  7 , and to maintain the dynamic range and DC accuracy of the processed signal.  FIGS. 2A and 2B  illustrate two conventional methods for correction of offset V OS, EQ  shown in FIG.  2 .  FIG. 2A  illustrates analog offset correction, wherein a voltage representing the offset voltage at the output of DSP  7  is subtracted from the signal at the input of ADC  5  via offset calibration logic  9 .  FIG. 2B  illustrates digital offset correction, wherein a voltage representing the offset voltage at the output of DSP  7  is subtracted from the signal at the input of DSP  7  via offset calibration logic  8 . 
   Digital offset correction provides certain advantages over analog offset correction. In particular, digital offset correction provides good accuracy, no additional noise, and a flexible response to residual offset error. However, digital offset correction does not eliminate the presence of V OS, EQ  at the input of ADC  5 . The presence of equivalent offset voltage V OS, EQ  at the input of ADC  5  reduces the dynamic range of ADC  5 . Further, if equivalent offset voltage V OS, EQ  causes saturation of ADC  5  input, digital offset correction cannot be used to correct the offset. 
   In view of the foregoing, an object of the present invention to provide methods and apparatuses for increasing the input range of an ADC. 
   SUMMARY OF THE INVENTION 
   One embodiment of the invention is directed to a method of extending the input range of an analog-to-digital converter (ADC) having a nominal input voltage range. The method comprises an act of mapping an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code. 
   Another embodiment of the invention is directed to an apparatus comprising an ADC having a nominal input voltage range, wherein the ADC is adapted to map an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1A  is a block diagram of a conventional signal processing system with an input offset, analog signal processor offset, and analog-to-digital converter (ADC) offset; 
       FIG. 1B  is a block diagram of the signal processing system of  FIG. 1A  with an equivalent offset; 
       FIG. 2A  is a block diagram of the signal processing system of  FIG. 1A  with analog offset correction; 
       FIG. 2B  is a block diagram of the signal processing system of  FIG. 1A  with digital offset correction; 
       FIG. 3  is a block diagram of a pipelined ADC; 
       FIG. 4  is a schematic representation of a sub-ADC of the pipelined ADC of  FIG. 3 ; 
       FIG. 5  shows digital output codes that may be output from the sub-ADC of  FIGS. 3-4  and corresponding input voltages for the sub-DAC of  FIG. 3 ; 
       FIG. 6  shows the correspondence between the thermometer-coded and binary-coded outputs of the sub-ADC of  FIG. 4 ; 
       FIG. 7A  is a schematic representation of a sub-DAC of the pipelined ADC of  FIG. 3 ; 
       FIG. 7B  shows voltage signals used in the activation of switches in the sub-DAC of  FIG. 7A ; 
       FIG. 8A  is a schematic representation of the sub-DAC of  FIG. 7A  activated in a sample phase; 
       FIG. 8B  is a schematic representation of the sub-DAC of  FIG. 7A  activated in a hold phase; 
       FIG. 9A  shows the residue plot output of the sub-DAC of  FIG. 7A   
       FIG. 9B  shows the transfer function of the pipelined ADC of  FIG. 3 ; 
       FIG. 9C  shows an ideal transfer function for the sub-ADC of  FIG. 3 ; 
       FIG. 9D  shows an output of the sub-ADC of  FIG. 3 ; 
       FIGS. 10A-C  show one implementation of the error correction logic of  FIG. 3 ; 
       FIGS. 11A-C  show one example of mapping that may occur in the error correction logic of  FIG. 3 ; 
       FIG. 12  shows the usable input range of a pipelined ADC constructed in accordance with an embodiment of the invention; 
       FIG. 13  is a block diagram of a pipelined ADC in accordance with one embodiment of the invention: 
       FIG. 14  is a schematic representation of one implementation of the sub-ADC of  FIG. 13  in accordance with an embodiment of the invention; 
       FIG. 15  shows the correspondence between the thermometer-coded and binary-coded outputs of the sub-ADC of  FIG. 14 ; 
       FIGS. 16A-E  show an implementation of the error correction logic of  FIG. 3  in accordance with an embodiment of the invention; 
       FIGS. 17A-C  show an example of mapping that may occur in the error correction logic of  FIG. 3  in accordance with an embodiment of the invention; 
       FIG. 18A  shows a residue plot of a pipelined ADC constructed in accordance with another embodiment of the invention; 
       FIG. 18B  shows the transfer function of a pipelined ADC having the residue plot of  FIG. 18A ; 
       FIG. 19  is a block diagram of a pipelined ADC that corresponds to the residue plot of  FIG. 18A ; 
       FIG. 20  is a schematic representation of a sub-ADC of the pipelined ADC of  FIG. 19 ; 
       FIG. 21  shows digital output codes that may be output from the sub-ADC of FIG.  20  and corresponding input voltages for the sub-DAC of  FIG. 23A ; 
       FIG. 22  shows the correspondence between the thermometer-coded and binary-coded outputs of the sub-ADC of  FIG. 20 ; 
       FIG. 23A  is a schematic representation of a sub-DAC of the pipelined ADC of  FIG. 19 ; 
       FIG. 23B  shows voltage signals used in the activation of switches in the sub-DAC of  FIG. 23A ; 
       FIG. 24A  is a schematic representation of the sub-DAC of  FIG. 23A  activated in a sample phase; 
       FIG. 24B  is a schematic representation of the sub-DAC of  FIG. 23A  activated in a hold phase; and 
       FIGS. 25A-C  show an example of mapping that may occur in the error correction logic of FIG.  19 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   One aspect of the invention is directed to increasing the input range of an analog-to-digital converter (ADC). According to one embodiment of the invention, input range is increased by mapping one or more digital output codes to one or more portions of the analog input range that are beyond the nominal input voltage range of the ADC. The digital output codes may be unique, and therefore not assigned to voltages in the nominal input voltage range. 
   Increasing the input range of an ADC has many potential benefits. These benefits may have particular significance when an offset voltage is present at the input of the analog-to-digital converter. An offset voltage at the input of an ADC reduces the dynamic range of the converter. If the input range of an ADC having an input offset voltage is increased, the dynamic range of the ADC may be restored by increasing the input range by an amount greater than or equal to the input offset voltage. Further, if the ADC having the input offset voltage is saturated by an input signal, digital offset correction, which was discussed in connection with  FIG. 3B , will not be effective to correct the offset voltage. If the input range of the ADC is increased by an amount greater than or equal to the voltage exceeding the nominal input voltage range of the ADC, saturation may be avoided and digital offset correction may be performed. Although enabling digital offset correction is one benefit of increasing the input range of an ADC, it should be appreciated that many other benefits exist, and that the invention is not limited in this respect. The operation and construction of a conventional ADC will now be described. 
     FIG. 3  illustrates one implementation of a conventional ADC, such as ADC  5  of  FIGS. 1-3 . Many types of ADCs exist, such as flash ADCs, algorithmic ADCs, and pipelined ADCs.  FIG. 3  illustrates a block diagram of one exemplary ADC, which is a pipelined ADC  13  that generates m output bits and comprises n stages. Each stage of pipelined ADC  13  operates successively to resolve k bits of the m-bit output. Pipelined ADC  13  of  FIG. 3  comprises a first stage  15 , a second stage  17 , a final nth stage  21 , and one or more intermediate stages, such as ith stage  19 . First stage  15  accepts a sample of analog signal Ain as stage input  23 . Then, as illustrated for ith stage  19 , which generically illustrates the processing that occurs in each of stages  1  through n, stage input  23  is quantized to k bits by a sub-ADC  25 . These k bits are transmitted to error correction logic  35 , which implements synchronization and correction functions. The bits are also transmitted to a sub-digital-to-analog converter (DAC)  27 , which converts the digital voltage into an analog voltage. The analog voltage is subtracted from stage input  23  by an adder  29 . The result of this operation is then multiplied by a factor of 2 (ki−1)  by a multiplier  31 , where i is the stage number. The output of multiplier  31  represents the residue  33  of the stage, which is passed to the input of the next stage, if present, for further processing. After each stage has transmitted k bits to error correction logic  35 , the error correction logic assembles and outputs m bits as digital output  37 . 
     FIG. 4  illustrates one implementation of sub-ADC  25  of FIG.  3 . The sub-ADC  39  of  FIG. 4  comprises four comparators  41 A-D, each of which outputs one digital bit of a digital output code. Each of comparators  41 A-D comprises first and second input terminals  43 A-B. The first input terminal  43 A of each comparator  41 A-D is coupled to stage input  23 . The second input terminal  43 B of each comparator  41 A-D is coupled to a node  45 A-D on a string of resistors  51  coupled between two reference voltages −Vr and +Vr, where 2Vr is the nominal input range of sub-DAC  25 . As shown, resistors  47 A-C have a resistance that is twice that of resistors  49 A-B, although other implementations are possible. Because the string of resistors  51  acts as a voltage divider, each node  46 A-D on the string is at a different voltage level. Hence, each comparator  41 A-D compares stage input  23  with a different voltage level. A logic one is output by any comparator coupled to a node at a lower voltage than stage input  23 , and a logic zero is output by comparators coupled to a node at a higher voltage than stage input  23 . The voltage level to which stage input  23  is compared is successively higher for comparators  41 A,  41 B,  41 C, and  41 D, respectively. Accordingly, comparator  41 A outputs the least significant bit of the output code of sub-ADC  39 , and comparator  41 D outputs the most significant bit. 
   Comparators  41 A- 41 D may output five different output codes D 0 -D 3 , as shown in FIG.  5 . Each output code will contain a logic one for each comparator that is connected to a node having a lower voltage than stage input  23 . Hence, if none of the comparators is connected to a node on resistor string  51  having a lower voltage than stage input  23 , each of comparators  41 A-D will output a logic zero, and the output code will be 0000. Conversely, if all of the comparators are connected to a node having a lower voltage than stage input  23 , each of comparators  41 A-D will output a logic one, and the output code will be 1111. 
   The output of comparators  41 A- 41 D is transmitted to sub-DAC  27  of  FIG. 3  as bits D 0 -D 3 . The output is also transmitted to a thermometer-to-binary converter  48 , which converts the thermometer code output of comparators  41 A- 41 D to binary code bits B 0 -B 1 . The conversion is performed according to the thermometer-binary correspondences set forth in table a FIG.  6 . The binary code output of sub-ADC  51  is transmitted to error correction logic  35  (FIG.  3 ). 
     FIG. 7A , illustrates one implementation of the sub-DAC  27 , adder  29 , and multiplier  31  of FIG.  3 . In particular,  FIG. 7A  illustrates a block diagram of a conventional 2-bit multiplying digital-to-analog converter (MDAC)  53 . MDAC  53  comprises inputs INPUT+ and INPUT− for receiving a stage input. MDAC  53  further comprises four pairs of input capacitors, each input capacitor  55 A-H connected via a switch Q 1  to one of the inputs INPUT+ or INPUT−. Each of input capacitors  55 A-H is also connected to a reference voltage, either top reference voltage REFT or bottom reference voltage REFB, at a node V 0 P-V 3 N via a switch Q 2 . Half of the input capacitors are connected to a first input terminal  57 A of an operational amplifier  59 , and half of the input capacitors are connected to a second input terminal  57 B of operational amplifier  59 . The first and second input terminals  57 A-B are also connected to common mode level voltage CML, via switches Q 1 , and to first and second output terminals  61 A-B of operational amplifier  59  via switches Q 2  and feedback capacitors  63 A-B. Feedback capacitors  63 A-B may have a capacitance that is twice that of input capacitors  55 A-H. The first and second input terminals  57 A-B of operational amplifier  59  are linked via a switch Q 1 . 
   MDAC  53  is activated in two phases: a sample phase and a hold phase. The activation of the two phases may be controlled by signals that control switches Q 1  and Q 2 . An example of such signals is shown in FIG.  7 B. The sample phase, during which switches Q 1  are closed, is illustrated in FIG.  7 A. When switches Q 1  are closed, four input capacitors  55 A-D are connected in parallel between INPUT+ and common mode level voltage CML, and the remaining four input capacitors  55 E-H are connected in parallel between INPUT− and common mode level voltage CML. Each of input capacitors  55 A-H may have an equivalent capacitance. Because stage input  23  is applied between INPUT+ and INPUT−, input capacitors  55 A-H are charged according to the magnitude of stage input  23 . 
   After a time sufficient for input capacitors  55 A-H to charge, switches Q 1  are opened and switches Q 2  are closed. In one example, switches Q 2  may be closed after switches Q 1  are opened. The hold phase, during which switches Q 2  are closed, is illustrated in FIG.  8 B. When switches Q 2  are closed, each input capacitor  55 A-H is connected to a reference voltage, either top reference voltage REFT or bottom reference voltage REFB, selected according to the digital output of sub-ADC  39 .  FIG. 5  illustrates the voltage applied to each input capacitor  55 A-H in  FIG. 7A  for each of five possible output codes of sub-ADC  39 . As may appreciated from the table, each pair of input capacitors  55 A-H includes one capacitor coupled to top reference voltage REFT and one capacitor coupled to bottom reference voltage REFB. The difference between top reference voltage REFT and bottom reference voltage REFB is Vr. Hence, either +Vr or −Vr is applied to each pair of input capacitors, according to the output code of sub-ADC  39 . For example, if the output code of sub-ADC  39  is 0000, −Vr is applied to each pair, and if the output code of sub-ADC  39  is 1111, +Vr is applied to each pair. A charge proportional to the difference between stage input  23  and its quantized approximation is forced onto feedback capacitors  63 A-B, which produces residue voltage  33  across outputs  61 A-B. 
     FIG. 9A  illustrates an example of a residue plot for a conventional stage generating 2 bits (i.e., k= 2 ). The residue plot results from the subtraction of Ain, shown in  FIG. 9C  with relation to the Aout, and Ain quantized to two bits, shown in FIG.  9 D. The ideal transfer function of sub-ADC  27  of  FIG. 3  is shown as a voltage ramp in  FIG. 9C. A  2-bit quantization of the voltage ramp shown in  FIG. 9C  results in the step function shown in FIG.  9 D. As shown in  FIG. 9B , the nominal input range of sub-ADC  25  ( FIG. 3 ) spans from −1V to 1V. The nominal input range represents the range of Ain for which unique output codes ordinarily exist in a conventional ADC. Hence, the maximum analog voltage in the nominal input range is assigned to the maximum digital output code generated in a conventional ADC, and the minimum analog voltage in the nominal input range is assigned to the minimum digital output code. Above and below the nominal input range, the output is clipped to avoid duplicate output codes. 
     FIGS. 10A-C  illustrate one implementation of the error correction logic  35  of FIG.  3 . Error correction logic  109  accepts the binary output codes of the sub-ADC  25  of each stage of  FIG. 3  as input  111 , and generates an m-bit output code as output  113 . Offset corrector  123  corrects for quantization errors of the input  111 , and maps the received codes to the transfer function shown in FIG.  10 B. The transfer function of  FIG. 10B  maps those codes falling within the nominal input range of the ADC  13 , which is between −1V and +1V in the example of  FIGS. 10A-C . Error correction logic  109  detects codes representing an analog input voltage outside of the nominal input range. In particular, detector  115  detects “below-range” codes, or those corresponding to an analog input below −1V. Detector  117  detects “above-range” codes, or those corresponding to an analog input above +1V. Error correction logic  109  sets all “below-range” codes to a minimum limit code  121 , which may be “00” in one example. Conversely, error correction logic  109  sets all “above-range” codes to a minimum limit code  119 , which may be “ 11 ” in one example. Logic circuit  125  processes the outputs of detector  115 , detector  117 , and offset correction  123  and outputs m bits as output  113 . 
     FIGS. 11A-C  show one example of mapping that may occur in the error correction logic  109  of FIG.  10 A.  FIG. 11A  illustrates one example of an assignment of binary codes  127 , output from sub-ADC  39 , to the residue segments of the residue plot of FIG.  9 A. Mapping algorithm  129 , shown in  FIG. 11B , maps binary codes  127  to the transfer function of FIG.  11 C. Mapping algorithm  129 , which may be implemented as circuitry in the offset corrector  123  of  FIG. 10A , reassigns binary codes  127  to corrected binary codes  131 . The mapping algorithm computes the reassignment by identifying regions of the residue plot of  FIG. 11A  where Aout is less than zero, and subtracting one from the corresponding binary code  127  of each identified region. The mapping that occurs via mapping algorithm  129  results in a transfer function for pipe lined ADC  13  as shown in FIG.  11 C. 
   In the conventional ADC discussed above in connection with  FIGS. 1-11 , unique digital output codes are generated for the analog voltages within the nominal input range of the ADC. Hence, the minimum value digital code of 00 was assigned to the minimum analog voltage within the nominal input range (i.e., −1V) and the maximum value digital code of  11  was assigned to the maximum analog voltage within the nominal input range (i.e., +1V). According to this scheme, the ADC output m bits, and hence 2 m  output codes. 
   In accordance with one embodiment of the invention, the input range of a conventional ADC is extended to allow over-range input voltages outside of the nominal input range of the ADC. The over-range voltages may be converted to unique digital output codes. Hence, the number of output codes that may be generated by the ADC is increased with respect to a conventional ADC. The dynamic range of the ADC is also increased. A first illustrative embodiment of an ADC having an extended input range will be discussed below in connection with  FIGS. 12-17 . 
     FIG. 12  illustrates the residue plot of  FIG. 3  for an extended input range. The nominal input range  135  of the residue plot of  FIG. 12  extends from −1V to +1V, as was the case in FIG.  3 . However, in  FIG. 3 , analog output voltages falling outside of the nominal input range were clipped. In a conventional ADC, the voltages above and below the nominal input range are clipped, as these regions produced no unique output codes and are unnecessary for conversion of the analog input. These regions are also unusable for conversion of the analog output as no additional useful information exists in these regions. However, it may be appreciated from  FIG. 12  that the analog output Aout of a sub-DAC continues to change beyond the nominal input range in the “above-range” region above 1V and the “below-range” region below −1V. 
   In accordance with the present embodiment, an ADC may be adapted to convert above-range voltages and/or below-range voltages to unique output codes. One exemplary implementation of such an ADC will now be discussed in connection with pipelined ADC  12  of FIG.  13 . However, it should be appreciated that the invention is not limited in this respect, and that other types of ADCs, such as a flash ADC or algorithmic ADC, may be adapted to convert above-range voltages and/or below-range voltages to unique output codes by applying the principles described herein. 
     FIG. 13  illustrates a pipelined ADC  12  that is similar in many respects to the pipelined ADC  13  of  FIG. 3 , but has been modified in accordance with one implementation of the presently described embodiment. In particular, sub-ADC  26  has been modified as discussed in connection with  FIG. 14 , and error correction logic  34  has been modified as discussed in connection with  FIGS. 16-17  and generates an m+1 bit output  36 . In other respects, pipelined ADC  65  operates according to the same principles as the pipelined ADC  13  described in connection with FIG.  3 . 
   In the residue plot of  FIG. 13  nominal input range  135  extends from −Vr to +Vr, where Vr equals 1V. The usable input range  133  extends from −3/2Vr to +3/2Vr. Hence, as may be appreciated from the residue plot of  FIG. 12 , the usage input range of ADC  13  ( FIG. 3 ) may be increased by Vr/2 (k-2) , where k is the number of bits resolved in the stage. Hence, the dynamic range of the ADC may be increased by Vr, beyond the nominal input range of 2Vr, when k equals 2. 
     FIG. 14  illustrates an exemplary implementation of the sub-ADC  26  of  FIG. 13  in accordance with the presently described embodiment. Sub-ADC  133  of  FIG. 14  is implemented as shown and described for the sub-ADC  51  of  FIG. 4 , with the exception of thermometer-to-binary converter  135 . As shown in  FIG. 15 , thermometer-to-binary converter  135  converts the thermometer code output of comparators  41 A- 41 D to a three-bit binary code as bits B 0 -B 2 . The conversion is performed according to the thermometer-binary correspondences set forth in FIG.  15 . Since the output of comparators  41 A- 41 D is converted to a three-bit binary code, rather than a two-bit binary code as in the sub-ADC  51  of  FIG. 4 , a unique code may be assigned for each of the five possible thermometer output codes of comparators  41 A- 41 D. The three-bit binary code output of sub-ADC  133  is transmitted to error correction logic  35  (FIG.  3 ). 
     FIGS. 16A-E  illustrate an exemplary implementation of the error correction logic  34  of  FIG. 13  in accordance with the presently described embodiment. Error correction logic  139  accepts the binary output codes of the sub-ADC  26  of each stage of  FIG. 13 , which may be implemented as shown for sub-ADC  133  of  FIG. 14 , as input  137 . Error correction logic  139  generates an m+1 bit output code as output  141 . Error correction logic  139  detects codes representing an analog input voltage outside of nominal input range  135  (FIG.  12 ). In particular, detector  143  detects “below-range” codes, or those corresponding to an analog input below −1V. Detector  145  detects “above-range” codes, or those corresponding to an analog input above +1V. 
   Code mapper  147  processes the below-range codes by mapping the codes to the partial transfer function of FIG.  16 B. The transfer function of  FIG. 16B  maps those codes falling below the nominal input range of ADC  133 , which is below −1V in the present example. Similarly, code mapper  149  processes the above-range codes by mapping the codes to the partial transfer function of FIG.  16 C. The transfer function of  FIG. 16C  maps those codes falling above the nominal input range of ADC  133 , which is above +1V in the present example. Offset corrector  151  corrects for quantization errors of the input  137 , and processed the codes within the nominal input range by mapping the codes to the transfer function of FIG.  16 D. The transfer function of  FIG. 16D  maps those codes falling within the nominal input range of the ADC  133 , which is between −1V and +1V in the present example. 
   Logic circuit  153  processes the outputs of detectors  143 ,  145 , code mapper  147 , code mapper  149 , and offset corrector  151 , and outputs m+1 bits as output  141 . Thus, it should be appreciated that for an m−bit ADC, the techniques described in connection with  FIGS. 12-16  provide an additional output bit relative to the conventional ADC described previously. 
     FIGS. 17A-C  show one example of mapping that may occur in the error correction logic  139  of FIG.  16 A.  FIG. 17A , illustrates one example of an assignment of binary codes  155 , output from sub-ADC  133 , to the residue segments of the residue plot of FIG.  12 . Mapping algorithm  156 , shown in  FIG. 17B , maps binary codes  155  to the transfer function of FIG.  17 C. Mapping algorithm  156 , which may be implemented as circuitry in the code mappers  147 ,  149  and offset corrector  151  of  FIG. 16A , reassigns binary codes  155  to corrected binary codes  157 . The mapping algorithm computes the reassignment by identifying regions of the residue plot of  FIG. 17A  where Aout is less than zero, and subtracting one from the corresponding binary code  155  of each identified region. The mapping that occurs via mapping algorithm  156  results in a transfer function for pipelined ADC  13  as shown in FIG.  17 C. It should be appreciated that the mappings described above are given by way of example only, and that numerous alternative mappings are possible, and may be used in accordance with the invention. 
   According to another embodiment of the invention, an ADC may be modified to further increase the input range of the ADC by assigning one or more additional unique codes in the over-range regions. In one illustrative implementation, which will be described in connection with  FIGS. 18-25 , a pipelined ADC is modified so that, in one or more stages, a sub-ADC thereof generates one or more residue segments outside of the nominal input voltage range. Each additional residue segment may produce an additional stage output code. The stage output codes may be processed in error correction logic of the ADC to generate additional ADC output codes outside of the nominal input voltage range. 
     FIG. 18A  illustrates an example of a residue plot for a stage of an ADC having residue segments outside of the nominal input voltage range. The residue plot of  FIG. 18A  corresponds to an ADC having a nominal input voltage range of −1V to +1V. In  FIG. 18A , complete residue segments exist between each of −2V and −5/4V and +5/4V and +2V, beyond the nominal input voltage range of the ADC. A unique output code may be assigned to each segment, extending the usable input range of the ADC to between −2V and +2V. As shown in  FIG. 18B , the usable input range of the modified ADC is double that of the nominal input range. 
   As may be appreciated from the reside plot of  FIG. 18A , input range may be increased by Vr/2 (k-1)  for each residue segment added, where k is the number of bits resolved in the stage, and Vr is one half of the nominal input range. Hence, the dynamic range of the ADC may be increased by 2Vr beyond the nominal input range of 2Vr. As shown in  FIG. 18A , the usable input range extends between 2Vr and −2Vr, or 2V and −2V where Vr=1V. 
     FIG. 19  illustrates a pipelined ADC  65  that has been modified to be usable in an ADC constructed in accordance with the described embodiment. Pipelined ADC  65  operates according to the same principles as the pipelined ADC  13  described in connection with FIG.  3 . However, sub-ADC  77 , sub-DAC  79 , and error correction logic  82  are modified so that pipelined ADC  65  generates residue segments outside of the nominal input range of the ADC. Pipelined ADC  65  of  FIG. 3  comprises a first stage  67 , a second stage  69 , a final nth stage  73 , and one or more intermediate stages, such as ith stage  71 . First stage  67  accepts a sample of analog signal Ain as stage input  75 . Then, as illustrated for ith stage  71 , which generically illustrates the processing that occurs in each of stages  1  through n, stage input  75  is quantized to k bits by sub-ADC  77 . These k bits are transmitted to error correction logic  82 , which implements synchronization and correction functions. The bits are also transmitted to sub-digital-to-analog converter (DAC)  79 , which converts the digital voltage into an analog voltage. The analog voltage is subtracted from stage input  75  by adder  29 . The result of this operation is then multiplied by a factor of 2 (ki-1)  by multiplier  31 , where i is the stage number. The output of the multiplier  31  represents residue  81  of the stage, which is passed to the input of the next stage, if present, for further processing. After each stage has transmitted k bits to error correction logic  82 , the error correction logic assembles and outputs m+1 bits as digital output  83 . 
     FIG. 20  illustrates one implementation of the sub-ADC  77  of FIG.  19 . Sub-ADC  77  is constructed in a manner similar to sub-ADC  25  of  FIG. 3 , but includes two additional comparators and two additional resistors. As shown in  FIG. 21 , the six comparators  85 A-F may output six different output codes. Each of comparators  85 A-F comprises first and second input terminals  87 A-B. The first input terminal  87 A of each comparator  85 A-F is coupled to stage input voltage  75 . The second input terminal  87 B of each comparator  85 A-F is coupled to a node  89 A-F on a string of resistors  91  coupled between two reference voltages −3/2Vr and 3/2Vr. As shown, resistors  93 A-E have a resistance that is twice that of resistors  95 A-B, although other implementations are possible. 
   Because the string of resistors  91  acts as a voltage divider, each node  89 A-F on the string is at a different voltage level. Hence, each comparator  85 A-F compares stage input voltage  75  with a different voltage level. A logic one is output by any comparator coupled to a node at a lower voltage than stage input voltage  75 , and a logic zero is output by comparators coupled to a node at a higher voltage than stage input voltage  75 . The voltage level to which stage input voltage  75  is compared is successively higher for comparators  85 A,  85 B,  85 C,  85 D,  85 E, and  85 F, respectively. Accordingly, comparator  85 A outputs the least significant bit of the output code of sub-ADC  77 , and comparator  85 F outputs the most significant bit. 
   The output of comparators  85 A-F is transmitted to sub-DAC  77  of  FIG. 19  as bits D 0 -D 5 . The output is also transmitted to a thermometer-to-binary converter  90 , which converts the thermometer code output of comparators  85 A-F to binary code as bits B 0 -B 2 . The conversion is performed according to the thermometer-binary correspondences set forth in FIG.  22 . The binary code output of sub-ADC  91  is transmitted to error correction logic  82  (FIG.  19 ). 
     FIG. 23A  illustrates one implementation of the sub-DAC  79 , adder  29 , and multiplier  31  of FIG.  19 . In particular,  FIG. 23A  illustrates a block diagram of a multiplying digital-to-analog converter (MDAC)  99 . MDAC  99  comprises inputs INPUT+ and INPUT− for receiving a stage input. MDAC  99  further comprises five pairs of input capacitors  97 A-J. Four pairs, including input capacitors  97 B-I, are connected via a switch Q 1  to one of inputs INPUT+ or INPUT−. The fifth pair, including input capacitors  97 A, J, is connected via a switch Q 1  to common mode level voltage CML. The input capacitors  97 A, J may have a capacitance that is twice that of input capacitors  97 B-I. Each of input capacitors  97 A-J is also connected to a reference voltage at a node V 0 P-V 4 N via a switch Q 2 . The reference voltage may be common mode level voltage CML, top reference voltage REFT, or bottom reference voltage bottom reference voltage REEB. Half of the input capacitors are connected to a first input terminal  101 A of an operational amplifier  107 , and half of the input capacitors are connected to a second input terminal  101 B of operational amplifier  107 . The first and second inputs are also connected to common mode level voltage CML, via switches Q 1 , and to first and second output terminals  103 A-B of operational amplifier  107  via switches Q 2  and output capacitors  105 A-B. The first and second input terminals  101 A-B of operational amplifier  107  are linked via a switch Q 1 . 
   MDAC  99  is activated in two phases: a sample phase and a hold phase. The sample phase, during which switches Q 1  are closed, is illustrated in FIG.  24 A. When switches Q 1  are closed, four input capacitors  97 B-E are connected in parallel between INPUT+ and common mode level voltage CML, and four input capacitors  97 F-I are connected in parallel between INPUT− and common mode level voltage CML. Input capacitors  97 A, J are each connected between common mode level voltage CML, which is coupled to both sides of each capacitor. Each of input capacitors  97 A-J may have an equivalent capacitance. Because stage input  75  is applied between INPUT+ and INPUT−, input capacitors  97 B-I are charged according to the magnitude of stage input  75 . Input capacitors A, J, which are not connected between a voltage differential, are not charged. 
   After a time sufficient for input capacitors  97 B-I to charge, switches Q 1  are opened and switches Q 2  are closed. In one example, switches Q 2  may be closed after switches Q 1  are opened. The hold phase, during which switches Q 2  are closed, is illustrated in FIG.  24 B. When switches Q 2  are closed, each input capacitor  97 A-J is connected to a reference voltage. The reference voltage may be common mode level voltage CML, top reference voltage REFT, or bottom reference voltage REFB, and is selected according to the digital output of the sub-ADC.  FIG. 21  illustrates the voltage applied to each input capacitor  97 A-J in  FIG. 24B  for each of seven possible output codes of the sub-ADC  83  of FIG.  20 . As may be appreciated from the table, each pair of input capacitors  97 A-J includes one capacitor coupled to top reference voltage REFT and one capacitor coupled to bottom reference voltage REFB. The difference between top reference voltage REFT and bottom reference voltage REFB is Vr. Hence, either +Vr or −Vr is applied to each pair of input capacitors  97 A-J, according to the output code of sub-ADC  83 . For example, if the output code of sub-ADC  83  is 000000, −Vr is applied to each pair, and if the output code of the sub-ADC is 111111, +Vr is applied to each pair. The coupling of top reference voltage REFT or bottom reference voltage REFB to input capacitors  97 B-I alone produces the residue voltage of a conventional MDAC shown in  FIG. 9A  across outputs  103 A-B. 
   For a digital input of 000000, which corresponds to a stage input voltage of less than −Vr−Vr/2 k , input capacitor  97 A is switched to bottom reference voltage REFB and capacitor  97 J is switched to REFT, which adds +Vr to the residue obtained using input capacitors  97 B-I. For a digital input of 111111, which corresponds to a stage input voltage of greater than Vr+Vr/2 k , input capacitor  97 A is switched to top reference voltage REFT and capacitor  97 J is switched to bottom reference voltage REFB, which adds −Vr to the residue obtained using input capacitors  97 B-I. For a digital input of 100000, 110000, 111000, 111100, or 111110, which correspond to a stage input voltage between −Vr−Vr/2 k  and Vr+Vr/2 k , both input capacitor  97 A and input capacitor  97 J are connected to CML, resulting in the same residue as for a conventional MDAC. 
     FIGS. 25A-C  show one example of mapping that may occur in the error correction logic  82  of FIG.  19 .  FIG. 25A  illustrates one example of an assignment of binary codes  159 , output from sub-ADC  77 , to the residue segments of the residue plot of FIG.  18 A. Mapping algorithm  162  reassigns binary codes  159  to corrected binary codes  161 . The mapping algorithm computes the reassignment by identifying regions of the residue plot of  FIG. 25A  where Aout is less than zero, and subtracting one from the corresponding binary code  159  of each identified region. The mapping that occurs via mapping algorithm  162  results in a transfer function for pipelined ADC  65  as shown in FIG.  25 C. It should be appreciated that the mappings described above are given by way of example only, and that numerous alternative mappings are possible, and may be used in accordance with the invention. 
   It should be appreciated that sub-ADC  83  and sub-DAC  99 , illustrated in  FIGS. 20 and 23A , respectively may be modified so that additional residue segments are generated in the residue plot of FIG.  18 A. In particular, sub-ADC  83  may be modified by adding an additional comparator  85  and resistor  93  for each additional residue segment, and sub-DAC  99  may be modified by adding an additional pair of capacitors  97  for each additional residue segment. Error correction logic  82  can then be modified to produce a unique output code for each additional residue segment in a similar manner to that discussed above in connection with  FIG. 25A-C . 
   It should further be appreciated that the method of extending the input range of an ADC described above in connection with pipelined ADC  65  ( FIG. 19 ) may be applied with other types of ADCs. In particular, the input range of an algorithmic ADC and/or a flash ADC may also be extended by assigning unique digital output codes that correspond to analog input voltages outside of the nominal input voltage range. 
   Having thus described several illustrative embodiments of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.