Abstract:
Herein disclosed is a method of reducing the vertical smears which are generated in a solid state image sensor including a plurality of vertical signal lines for transferring signal charges in a vertical direction and at least one charge transfer device for transferring the signal charges in a horizontal direction. 
     The smear charges stored in the vertical signal lines and the signal charges generated in a photoelectric conversion element in response to an incident ray are inputted separately of each other for a horizontal blanking period to the charge transfer device for the horizontal transfer. During a tracing period, a smear voltage and a signal voltage are outputted separately of each other from said charge transfer device. The smear voltage adjusted is subtracted from the signal voltage to eliminate the smear component which has been mixed into the signal voltage.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a method of reducing the vertical smears to be generated in a solid state image sensor of the type including a plurality of photoelectric conversion elements arrayed regularly in horizontal and vertical directions, a plurality of vertical signal lines for transferring signal charges in a vertical direction, and at least one charge transfer device for transferring the signal charges in a horizontal direction, and a solid state imaging device for practicing the vertical smear reducing method. 
     One example of the solid state image sensor of this type is disclosed in European patent application Publication No. 0,054,244. The equivalent U.S. patent is U.S. Pat. No. 4,443,818. 
     The structure of the solid state image sensor of this type is shown in FIG. 1. With reference to this Figure, the operations of the solid state image sensor of this type will also be described. 
     The output pulses, which are consecutively sent to the output lines 2 1 , 2 2 , - - -, and 2 m  of a vertical shift register 1, are added to an interlace circuit 3 so that output pulses are generated at output lines 4 1 , 4 3 , - - -, and 4 2m-1  in an odd field and at output lines 4 2 , 4 4 , - - -, and 4 2m  in an even field. As a result, during a first horizontal scanning period of the odd field, vertical switching transistors 5 1-1 , 5 1=2 , - - -, and 5 1-n  are simultaneously turned on so that the signal charges generated in photo diodes 6 1-1 , 6 1-2 , - - -, and 6 1-n  are transferred to vertical signal lines 7 1 , 7 2 , - - -, and 7 n  corresponding thereto, respectively. Likewise, during a first horizontal scanning period of the even field, vertical switching transistors 5 2-2 , 5 2-2 , - - -, and 5 2-n  are simultaneously turned on so that the signal charges generated in photo diodes 6 2-1 ,6 2-2 , - - -, and 6 2-n  are transferred to the vertical signal lines 7 1 , 7 2 , - - -, and 7 n . By the ON signal from a control terminal 9, moreover, horizontal switching transistors 8 1 , 8 2 , - - -, and 8 n  are simultaneously turned on so that the signal charges of the vertical signal lines 7 1 , 7 2 , - - -, and 7 n  are transferred to a charge transfer device 10 (which will be shortly referred to as &#34;CTD&#34;). This CTD 10 acts as a horizontal shift register. 
     Here, a portion having photosensitivity is desired to be limited to a portion of a photo diode 6. As a matter of fact, however, the peripheral portion of the photo diode 6, e.g., the drain of a vertical switching transistor (e.g., a MOS transistor) 5 may have the photosensitivity. Those charges generated in the drain of the transistor 5 are transferred to the vertical signal lines 7 irrespective of the conductivity of the vertical switching transistors 5. With the respective vertical signal lines 7, however, there are connected all the drains of hundreds of vertical switching transistors 5 arrayed in the vertical direction so that the charges generated in all the drains are mixed and added until they are stored in the vertical signal lines 7. The charges thus stored are obtained such that they are superimposed on the normal signal charges generated in the photo diodes 6 for the respective horizontal scanning periods. As a result, if an object having such a bright portion as is shown in FIG. 2A, for example, is imaged, a vertical smear of the bright portion appears in a reproduced frame, as shown in FIG. 2B. This noise component intrinsic to the solid state image sensor is called the &#34;vertical smear.&#34; 
     The magnitude of the charges resulting in the vertical smear is proportional to their storage period in the vertical signal lines. When the horizontal switching transistors 8 are turned on, more specifically, the magnitude of the vertical smear charges to be transferred to the horizontal CTD is proportional to the period from the instant when the horizontal switching transistors 8 are previously turned off. 
     With this in mind, sweeping out transistors 11 1 , 11 2 , - - -, and 11 n  equipped with a common control terminal 13 are connected in parallel with the horizontal switching transistors 8 1 , 8 2 , - - -, and 8 n  such that they are turned on during the horizontal blanking period. 
     FIG. 3 is a time chart showing the driving pulses of FIG. 1. During the period t a  -t b  in the horizontal blanking period as shown in FIG. 3, a sweeping out transistor 11 is first supplied with a driving pulse to sweep out from a sweeping out terminal 12 to the outside the vertical smear charges Q V1  which are stored on and after the ON period (t e  &#39;-t f  &#39;) before the one horizontal scanning period. Subsequently, during a period t c  -t d , the vertical switching transistors 5 are turned on to transfer the signal charges Q S  of the photo diodes 6 to the vertical signal lines 7, and during the period t e  -t f  the horizontal switching transistors 8 are turned on to transfer the signal charges Q S  to the horizontal CTD. At this time, into these signal charges, there are mixed the vertical smear charges Q V2  which are stored in the period t b  -t f . 
     As a result of the transfer during the horizontal scanning period, the charges obtained from the output of the horizontal CTD 10 are converted by the gate capacitor C G  of a source follower transistor 14 into such a voltage signal V out  as is expressed by the following Equation until it appears at an output terminal 15: ##EQU1## 
     Here, if the one horizontal scanning period T 0  and the period t b  -t f  are designated by T 0  and T 1 , respectively, the ratio a between the vertical smear charges Q V0  (=Q V1  +Q V2 ) without the sweeping out operation and the vertical smear charges Q V2  with the sweeping out operation is expressed by the following Equation: 
     
         a=Q.sub.V2 /Q.sub.V0 =T.sub.1 /T.sub.0                     ( 2) 
    
     Since the one horizontal scanning period and the horizontal blanking period are about 64 μS and 11 μS, respectively, the ratio a is smaller than 1/6. Thus, a remarkable improvement can be obtained by conducting the sweeping out operation. In order to prevent the generation of the vertical smears for all the objects, however, that ratio has to be reduced to about 1/100. 
     In the aforementioned European Patent Application Publication No. 0,054,244, there is disclosed the steps of: transferring the noise charges, which are stored in vertical signal lines, to a horizontal CTD prior to the reading out of signal charges from photoelectric conversion conversion elements such as photo diodes located on horizontal lines a and b; reading out the signal charges and the noise charges from the horizontal CTD; and eliminating the noise charges mixed in the signal charges by subtracting the noise charges from the signal charges. 
     Despite this fact, however, the European Patent Application merely discloses the above-specified principle but does not disclose a method of accurately eliminating noise components from a signal. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a method of accurately eliminating the smear components which are mixed in a signal. 
     Another object of the present invention is to provide a solid state imaging device which can output a video signal having its smear components eliminated accurately. 
     These objects can be achieved by the method of the present invention comprising the steps of: 
     transferring smear chages stored in vertical signal lines to horizontal transfer means; 
     transferring signal charges from photoelectric conversion elements to said vertical signal lines, and transferring said signal charges from said signal lines to said horizontal transfer means; 
     transferring said smear charges and said signal charges in a separate state to an output terminal by said horizontal transfer means; 
     generating a smear voltage corresponding to said smear charges and a signal voltage corresponding to said signal charges at the output terminal of said horizontal tranfer means; 
     adjusting the magnitude of said smear voltage at a predetermined ratio; and 
     subtracting said adjusted smear voltage from said signal voltage to reduce the smear component contained in said signal voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing the solid state image sensor according to the prior art; 
     FIGS. 2A and 2B are diagrams showing an object image and a vertical smear appearing in a reproduced frame in a manner to accompany the former respectively; 
     FIG. 3 is a timing chart showing the driving pulses of elements of FIG. 1; 
     FIG. 4 is a circuit diagram showing a solid state imaging device according to one embodiment of the present invention; 
     FIGS. 5A to 5N are charts for explaining the structure and operations of the horizontal CTD of the embodiment of FIG. 4; 
     FIGS. 6A to 6C are charts showing clock pulses for driving the horizontal CTD of FIG. 5A; 
     FIG. 7 is a timing chart showing the driving pulses of the embodiment of FIG. 4; 
     FIG. 8 is a chart showing the output voltage and sampling pulses of the embodiment of FIG. 4; 
     FIGS. 9A to 9L are charts for explaining the structure and operations of another example of the horizontal CTD to be used in the present invention; 
     FIG. 10 is a chart showing clock pulses for driving the horizontal CTD of FIG. 9A; 
     FIG. 11 is a circuit diagram showing the solid state imaging device according to another embodiment of the present invention; 
     FIG. 12 is a circuit diagram showing the solid state imaging device according to another embodiment of the present invention; 
     FIG. 13 is a timing chart showing the driving pulses of the embodiment of FIG. 12; 
     FIG. 14 is a chart showing the output voltage and sampling pulses of the embodiment of FIG. 12; 
     FIG. 15 is a timing chart showing other driving pulses according to the present invention; 
     FIG. 16 is a circuit diagram showing a solid state imaging device according to a further embodiment of the present invention; and 
     FIG. 17 is a timing chart showing still other driving pulses according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 is a circuit diagram showing the solid state imaging device according to one embodiment of the present invention. 
     In order to transfer most of the charges of vertical smears separately of signal charges, as shown in FIG. 4, a horizontal CTD 10&#39; has a three-phase electrode structure, and sampling circuits 17 1  and 17 2 , a voltage adjusting circuit 18, a subtracting circuit 19 and a low pass filter 20 are newly added to the output side of the horizontal CTD 10&#39; so that the vertical smears mixed in the signal charges are eliminated by subtraction. 
     In FIG. 4, there exists no element which corresponds to the sweeping out transistors 11 of FIG. 1. 
     FIGS. 5A to 5N are charts showing the three-phase electrode structure of the horizontal CTD 10&#39; of FIG. 4 and the transitions of internal potentials, and an abscissa x designates a distance whereas an ordinate φ s  designates a potential. 
     The horizontal CTD 10&#39; of FIG. 4 has such a structure as is shown in FIG. 5A. More specifically, each of charge storage regions is constructed of a combination of: one electrode exhibiting a potential well which is relatively shallow relative to an identical voltage applied; and one electrode exhibiting potential well which is relatively deep. Three-phase pulses are applied to the adjacent three storage regions, i.e., three groups of electrodes. One stage of that CTD is composed of those three groups of electrodes which are driven in three phases. A plurality of stages thus composed are arrayed in a charge transferring direction. Each stage corresponds to each of the aforementioned horizontal switching transistors 8 and each of the vertical signal lines 7 connected with the former. 
     When all the clock pulses applied to the respective electrodes of the CTD 10&#39; are at a low level, the potential wells corresponding to the respective electrodes are so repeatedly arrayed with one group of high and low potentials as are shown in FIG. 5B. 
     FIGS. 6A, 6B and 6C are time charts showing the clock pulses which are to be applied to the respective three-phase electrodes H1, H2 and H3 shown in FIG. 5A. 
     It is assumed here that the three-phase pulses having a clock frequency f c , as shown in FIGS. 6A, 6B and 6C, are added to the respective electrodes H1, H2 and H3. Specifically: the pulses are applied to the electrode H1 at instants t 1 , t 7 , t 13  and so on; the pulses are applied to the electrode H2 at instants t 5 , t 11 , t 17  and so on; and the pulses are applied to the electrode H3 at instants t 3 , t 9 , t 15  and so on. As a result, the potential wells at the respective periods t 0  -t 13  are transmitted to the states shown in FIGS. 5B to 5N. Here, reference letters Q A  and Q B  on the potential wells indicate the signal charges or vertical smear charges which are sent from the vertical signal lines 7. If the horizontal switching transistors 8 are connected with the portion corresponding to the H1 electrode of the horizontal CTD 10&#39; so that they are turned on for the periods t 1  -t 2  and t 7  =t 8 , respectively, as shown in FIGS. 5C to 5N, the two charges Q A  and Q B  can be taken into each of the stages composed of three groups of three-phase driven electrodes so that they can be transferred in a separate manner. In FIG. 5C, more specifically, the electrode H1 takes a lower potential, because it is supplied with the pulse for the period t 1  -t 2 , and the charges Q A  are sent from the vertical signal lines 7 by turning on the horizontal switching transistors 8. Next, as shown in FIG. 5E, the electrode H3 is supplied with the pulse for the period t 3  -t 4  so that it takes a low potential but with the charges Q A  being unmoved. Next, as shown in FIG. 5G, the electrode H2 is supplied with the pulse for the period t 5  -t 6  so that it takes a lower potential so that the charges Q A  are transferred from an adjacent high potential. Next, as shown in FIG. 5I, the electrode H1 is supplied with the pulse for the period t 7  -t 8 , and the horizontal switching transistors 8 are turned on so that the charges Q B  are sent from the vertical signal lines 7. FIGS. 5J to 5N show the states in which the two charges Q A  and Q B  are transferred separately of each other to each of the stages composed of three storage regions formed below three groups of three-phase driven electrodes. 
     FIG. 7 shows the pulses for driving the switching transistors of the solid state imaging device of the present invention. FIG. 8 is a chart for explaining the output waveforms of FIG. 4. 
     The one horizontal scanning period is composed of: a tracing period for actually sending out a video signal; and a horizontal blanking period from the instant when the scanning operation of one scanning line is ended to the instant when the initial scanning point is restored. In the present invention, as shown in FIG. 7, the horizontal switching transistors 8 are turned on for the period t a  -t b  for the horizontal blanking period to transfer the vertical smear charges Q V1  (which corresponds to Q A  of FIG. 5 A , which are stored for the period from t&#39; f  in the preceding horizontal period to t b , to the horizontal CTD 10&#39;. The operations during this period correspond to those for the period t 1  -t 2  shown in FIGS. 5C and FIGS. 6A to 6C. Subsequently, during the period t c  -t d  of FIG. 7, the vertical switching transistors 5 are turned on to transfer the signal charges Q S  of the photo diodes 6 to the vertical signal lines 7, and the charges Q B  are transferred to the horizontal CTD 10&#39; by turning on again the horizontal switching transistors 8 for the period t e  -t f . The charges Q B  are the sum of the aforementioned signal charges Q S  and the vertical smear charges Q V2  which are stored for the period t b  -t f . 
     Incidentally, the operations for the periods t b  -t e  and t e  -t f  in FIG. 7 correspond to the operations for the period t 2  -t 7  of FIGS. 5D to 5H and for the period t 7  -t 8  of FIG. 5I, respectively. For the horizontal scanning period, moreover, if the horizontal CTD 10&#39; is driven by the three-phase clock pulse of FIGS. 6A, 6B, 6C with the horizontal switching transistors 8 being held inoperative, the two charges Q A  and Q B  are transferred separately of each other to the output terminal of the horizontal CTD 10&#39;. 
     Thus, as shown in FIG. 7, by turning on the horizontal switching transistors 8 for the period t a  -t b , the vertical smear charges Q V1  stored for the period t&#39; f  -t b  are transferred to the horizontal CTD 10&#39;. By turning on the horizontal switching transistors 8 for the period t e  -t f , both the signal charges Q S  transferred to the vertical signal lines 7 for the period t c  -t d  and the vertical smear charges Q V2  stored for the period t b  -t f  are transferred to the horizontal CTD 10&#39;. In other words, there are mixed in the signal charges the vertical smear charges Q V2  which are stored for the period t b  -t f . Now, if the period t&#39; f  -t b  is designated by T 1  whereas the period t b  -t f  is designated by T 2 , the relationship between the vertical smear charges Q V1  and Q V2  is expressed by the following Equation, because the one horizontal scanning period is 64 μS whereas the horizontal blanking period is about 11 μS: ##EQU2## 
     Thus, only the vertical smear charges Q V1  and the signal charges Q S  having the vertical smear charges Q V2  mixed therein are alternately outputted from the output terminal of the horizontal CTD 10&#39;. This output is converted by the gate capacitor C G  of the source follower transistor 14 into the voltage signal having the following relationship until it is sent out to the output terminal 15: ##EQU3## The charges of the gate are swept out, before the subsequent charges are transferred from the horizontal CTD 10&#39;, by a resetting transistor 16 which is adapted to be turned on by a resetting pulse having a frequency equal to the clock frequency f c . 
     In FIG. 8: there are shown the pulse which is applied to the final electrode H3 of the horizontal CTD 10&#39;; the resetting pulse for turning on the resetting transistor 16; the output voltages V 1  and V 2  which are expressed by the foregoing Equations (4) and (5); and sampling pulses SP1 and SP2 which are to be applied to the sampling circuits 17 1  and 17 2 . 
     The output voltages V 1  and V 2 , which are obtained alternately for the clock frequency f c , are applied separately of each other to the sampling circuits 17 1  and 17 2  shown in FIG. 4. These sampling circuits 17 1  and 17 2  are fed with the sampling pulses SP1 and SP2, respectively, so that they take the output voltages V 1  and V 2 . The voltage V 1  thus separated by the sampling circuit 17 1  is attenuated in the voltage adjusting circuit 18 in accordance with the ratio T 2  /T 1  of the storage period T 2  of the smear charges Q V2  to the storage time T 1  of the smear charges Q V1 . The voltage (T 2  /T 1 )·V 1  is inputted together with the other voltage V 2  to the subtracting circuit 19. The voltage V&#39; out  obtained from this subtracting circuit 19 is expressed by the following equation: ##EQU4## Since the Equation of Q V1  =(T 1  /T 2 )Q V2  is obtained from the foregoing Equation (3), the Equation (6) can be simplified into the following simple form: ##EQU5## 
     Hence, if the output of the subtracting circuit 19 is added to the low pass filter 20, it is possible to obtain a signal from which the vertical smears are eliminated. 
     Incidentally, as shown in FIG. 5A, the horizontal CTD 10&#39; used in this embodiment has the three-phase electrode structure having high and low potentials. Any CTD can be applied as the horizontal one of the present invention if it can transfer two or more changes by one group of plural storage regions. 
     FIGS. 9A to 9L are charts for explaining the electrode structure and potentials of the horizontal CTD according to another embodiment of the present invention, and an abscissa x designates a distance whereas an ordinate φ S  designates the potential. Moreover, FIG. 10 is a timing chart showing the driving pulses to be applied to the electrodes of FIG. 9A. 
     FIG. 9A shows a six-phase electrode structure. By applying the six-phase pulses shown in FIG. 10 to the electrodes H1 to H6, the two charges Q A  and Q B  can be transferred separately of each other in the repetitions of the stages composed of the six electrodes. 
     In FIG. 9B, a pulse is applied to the electrodes H1 and H4 at an instant t&#39; 1  so that the charges Q A  are sent to the electrode H1 of the horizontal CTD. In FIG. 9C, a pulse is applied to the respective electrodes H1, H2, H4 and H5 at an instant t&#39; 2  so that the charges Q A  of the electrode H1 are extended to the electrode H2. In FIG. 9D, a pulse is applied to the electrodes H2 and H5 at an instant t&#39; 3  so that the charges Q A  are transferred to the electrode H2. In FIG. 9H, the pulse is again applied to the electrodes H1 and H4 at an instant t&#39; 7  so that the charges Q A  are transferred to the electrode H4 whereas the subsequent charges Q B  are inputted to the electrode H1. In these ways, the two charges Q A  and Q B  are transferred separately of each other to each of the stages composed of the six storage regions formed below the six transfer electrodes. 
     FIG. 11 is a circuit diagram showing the structure of the solid state imaging device according to another embodiment of the present invention. 
     In the foregoing embodiment of FIG. 4, there has been described the method in which both the signal charges having the vertical smears mixed therein and only the vertical smears are transferred together by the single horizontal CTD 10&#39;. As shown in FIG. 11, however, absolutely the same effects can be obtained if the two ordinary CTDs 10 and 10&#34; for taking one charge into each of the stages composed of a plurality of transfer electrodes and for transferring the same are used two in number. In this case, two sets of the horizontal switching transistors 8 and 8&#39; are disposed in a manner to correspond to the horizontal CTDs 10 and 10&#34;, respectively, such that they take the charge of the twice ON operations shown in FIG. 7. Specifically, a pulse is applied to the horizontal switching transistors 8 for the period t a  -t b  (or t&#39; a  -t&#39; b ) of FIG. 7 to send the charges composed of the vertical smears only to the horizontal CTD 10, and a pulse is applied to the horizontal switching transistors 8&#39; for the period t e  -t f  (or t&#39; e  -t&#39; f ) of FIG. 7 to send the signal charges having the vertical smears mixed therein to the horizontal CTD 10&#34;. Moreover, the output voltage of the horizontal CTD 10 is applied, after it has been attenuated to T 2  T 1  by the voltage adjusting circuit 18, together with the output voltage of the horizontal CTD 10&#34; to the subtracting circuit 19. As a result, it is possible to obtain the outputs, which are expressed by the foregoing Equations (6) and (7), i.e., the outputs from which the vertical smears are eliminated. 
     FIG. 12 is a circuit diagram showing the solid state imaging device according to still another embodiment of the present invention. 
     In the embodiment of FIG. 12, as is different from the structure of the prior art shown in FIG. 1, the horizontal CTD 10&#39; has a three-phase electrode structure, and the sampling circuits 17 1  and 17 2 , an amplifying circuit 18&#39;, the subtracting circuit 19 and the low pass filter 20 are disposed at the output side so that the signal charges having the vertical smears mixed therein in the vertical CTD 10&#39; and the charges composed of the vertical smears only are taken out separately of each other and so that the vertical smears are eliminated by a subtraction. 
     The horizontal CTD 10&#39; in this embodiment is of the same type as the CTD 10&#39; of the foregoing embodiment of FIG. 4, and its structure and its transfer by the three-phase drive are absolutely the same as those of FIGS. 5A to 5N. 
     FIG. 13 is a time chart showing the driving pulses to be applied to the respective switching transistors of FIG. 12, and FIG. 14 is a chart showing the waveforms of the output voltages of the embodiment of FIG. 12 
     In the embodiment of FIG. 12, as shown in FIG. 13, the sweeping out transistors 11 are turned on for the period t a  -t b  during the horizontal blanking period to sweep out the vertical smear charges Q&#39; V1  which are stored on and after the ON period (t&#39; g  -t&#39; h ) of the horizontal switching transistors 8 before the one horizontal scanning period. For the succeeding period t c  -t d , the horizontal switching transistors 8 are turned on to transfer the vertical smear charges Q&#39; V2  (=Q A ), which are stored for the period t b  -t d , to the horizontal CTD 10&#39;. These operations for the period t c  -t d  correspond to those for the period t 1  -t 2  shown in FIG. 5C. For the succeeding period t e  -t f , the vertical switching transistors 5 are turned on to transfer the signal charges Q S  of the photo diodes 6 to the vertical signal lines 7. By turning on the horizontal switching transistors 8 again for the period t g  -t h , the charges Q B , which is the sum of the aforementioned signal charges Q S  and the vertical smear charges Q&#39; V3  stored for the period t d  -t h  are transferred to the horizontal CTD 10&#39;. The operations for the periods t d  -t g  and t g  -t h  correspond to those for the period t 2  -t 7  of FIGS. 5D to 5H and the period t 7  -t 8  of FIG. 5I, respectively. If, moreover, the horizontal CTD 10&#39; is driven by the three-phase clock pulses shown in FIGS. 6A to 6C while the horizontal switching transistors 8 are being held inconductive during the video period, the two charges Q A  and Q B  can be transferred separately of each other. 
     In the signal charges Q S , as has been described above, there are mixed the vertical smear charges Q&#39; V3  which are stored in the vertical signal lines 7 for the period t d  -t h . If the period t b  -t d  and the period t d  -t h  are designated by T&#39; 1  and T&#39; 2 , respectively, the relationship between the vertical smear charges Q&#39; V2  and the vertical smear charges Q&#39; V3  mixed in the signal charges Q S  is expressed by the following Equation: ##EQU6## 
     In these ways, from the output of the horizontal CTD 10&#39;, both only the vertical smear charges Q&#39; V2  and the signal charges Q S  having the vertical smear charges Q&#39; V3  mixed therein are alternately sent out in response to the clock frequency f c . These charges are converted by the gate capacitor C G  of the source follower transistor 14 into the voltage signals, as are expressed by the following Equations, and are sent out to the output terminal 15: ##EQU7## 
     One example of these output voltage V 1  and V 2  is shown in the schematic chart of FIG. 14. More specifically, the charges are sent out to the gate of the source follower transistor 14 by applying the pulse to the final electrode H3, and the charges of the gate are swept out to the outside, before the succeeding charges are transferred from the horizontal CTD 10&#39;, by the resetting transistor 16 which is adapted to be turned on by the resetting pulse having a frequency equal to the clock frequency f c . The output voltages V 1  and V 2 , which are obtained alternately in response to the clock frequency f c , are separated by the sampling circuits 17 1  and 17 2  shown in FIG. 12. The output voltages V 1  and V 2  are taken into the sampling circuits 17 1  and 17 2 , respectively, by applying the sampling pulses SP1 and SP2 shown in FIG. 14. The output voltage V 1  separated by the sampling circuit 17 1  is applied, after it has been amplified to a ratio T&#39; 2  /T&#39; 1  by the amplifying circuit 18&#39;, together with the other output voltage V 2  to the subtracting circuit 19. The signal V&#39; out  obtained from the subtracting circuit 19 is expressed by the following Equation: ##EQU8## 
     Since the equation of Q&#39; V2  =(T&#39; 1  /T&#39; 2 )·Q&#39; V3  holds from the foregoing Equation (8), the above Equation (11) is simplified into the following Equation: 
     
         V&#39;.sub.out =Q.sub.S /C.sub.G                               (12) 
    
     As a result, the signal, which is obtained by applying the output of the subtracting circuit 19 to the low pass filter 20, is cleared of the vertical smears. 
     Incidentally, the description thus far made is directed to the method in which the signal of the picture elements having the vertical smears mixed therein is sent after the vertical smears have been sent to the horizontal CTD, as shown in FIG. 13. It is, however, apparent that like effects can be obtained even if the vertical smears are sent to the horizontal CTD after the picture element signal having the vertical smears mixed therein has been sent in response to the pulse which is prepared by changing the phase of the driving pulse for driving the vertical switching transistors, as shown in FIG. 17. 
     Incidentally, in the solid state image sensor thus far described, the noise charges Q n , which are generated when the horizontal switching transistors 8 and the sweeping out transistors 11 are turned on, are sent out to either the horizontal CTD 10&#39; or the sweeping out terminal 12. At this time, since the charges of the vertical signal lines 7 become short by the quantities of the noise charges Q n  sent out, there are left in the vertical signal lines 7 the noise charges-Q n  which have the same magnitude as but the polarity opposite to those noise charges Q n . The noise charges-Q n  of the opposite polarity left on the vertical signal lines 7 are sent out, at the succeeding instant when the horizontal switching transistors 8 or the sweeping out transistors 11 are turned on, together with the noise charges generated at that instant to the horizontal CTD 10&#39; or the sweeping out terminal 13. 
     Next, the voltages V&#39; 1  and V&#39; 2  at the output terminal, which include the noise charges, are expressed by the following Equations, if they are taken into consideration: ##EQU9## 
     Here, reference characters Q n1  designate the noise charges when the sweeping out transistors 11 are turned on; characters Q n2  designate the noise charges when the horizontal switching transistors 8 are first turned on; and characters Q n3  designate the noise charges when the horizontal switching transistors 8 are second turned on. 
     From the above Equations (13) and (14), the output signal V&#34; out  of the subtracting circuit 19 is expressed by the following Equation: ##EQU10## 
     Since the Equation of T&#39; 1  ≈T&#39; 2  substantially holds, the magnitude of the noises to be mixed in the output signal is about √6 times as high as that of the noises which are generated by the once operations of the horizontal switching transistors 8 or the sweeping out transistors 11. 
     FIG. 15 is a timing chart showing the driving pulses in still another embodiment of the present invention. 
     The operations for the horizontal blanking period, as shown in FIG. 13, are changed into those shown in FIG. 15. As shown in FIG. 15, since the respective sweeping out transistors 11 are turned on before the horizontal switching transistors 8 are turned on, no correlation exists between the noise charges which are mixed into the two charges to be transferred to the horizontal CTD 10&#39;. In this case, the voltage V&#34; 1  and V&#34; 2  appearing in the output are expressed by the following Equations: ##EQU11## 
     Here, characters Q n1  and Q n3  designate the noise charges which are generated by turning on the sweeping out transistors 11, and characters Q n2  and Q n4  designate the noise charges which are generated by turning on the horizontal switches 8. 
     From the above Equations (16) and (17), the output signal V&#39;&#34; out  of the subtracting circuit 19 is expressed by the following Equation: ##EQU12## 
     Here, characters T&#34; 1  designate the period t b  -t d  shown in FIG. 15, and characters T&#34; 2  designate the period t f  -t j . Because of T&#34; 1  ≈T&#34; 2 , the magnitude of the noises is improved about two times as high as those which are generated by the operations of the horizontal switching transistors 8 or the sweeping out transistors 11. 
     In the embodiment of FIG. 12, the same effects can be obtained if the CTD having the six-phase electrode structure shown in FIGS. 9A to 9L is used as the horizontal CTD 10&#39;. 
     FIG. 16 is a circuit diagram showing the solid state imaging device according to a further embodiment of the present invention. 
     As shown in FIG. 16, there are used two sets of the ordinary horizontal CTDs 10 and 10&#34; for transferring a charge in each of the stages composed of plural electrodes. In this case, the horizontal switching transistors 8 1 , 8 2 , - - -, and 8 n , and 8&#39; 1 , 8&#39; 2 , - - -, and 8&#39; n  take the charges of the twice ON operations of the horizontal switching transistors shown in FIG. 13. 
     There appears at the output terminal 15 of the horizontal CTD 10 the voltage V 1  which is proportional to the charges Q&#39; V2  of the vertical smears, whereas there appears at the output terminal of the horizontal CTD 10&#34; the voltage V 2  which is proportional to the signal charges Q S  which has the vertical smear charges Q&#39;V 3  mixed therein. If T&#39; 1  ≈T&#39; 2 , the output is expressed by the following Equation by applying both the output voltages to the subtracting circuit 19 so that they may be subjected to the subtraction: ##EQU13## 
     It is quite natural that the pulses can be applied to the horizontal switching transistors 8 and 8&#39; so that the voltages V 2  and V 1  may be outputted to the output terminals 15 and 15&#39;, respectively. 
     In this embodiment, too, in order to precisely eliminate the vertical smears, it is preferable to adjust the magnitude of the vertical smear voltage V 1  prior to its application to the subtracting circuit 19. This adjustment can be effected either by adjusting the gain of the source follower transistor 14 or by connecting an amplifier having a suitable gain between the output terminal 15 and the subtracting circuit 19.