Abstract:
A gain controller for a signal mixer in which consistent circuit gain is maintained by using transistors in the gain control and signal mixing stages with equal corresponding device dimensions and by using a differential gain control voltage with inverse and noninverse differential voltage phases which individually track variations in the dc bias currents used to power the gain control and signal mixing stages. This provides a gain factor which is independent of variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures. Such a gain controller provides a self-compensating gain control signal which is based upon a variable gain control factor and tracks variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures by tracking variations in the dc biasing used to power the gain control and signal mixing stages. Such tracking of the biasing by the gain control advantageously provides for an increased dynamic range.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to adaptive signal equalizers for adaptively equalizing high data rate signals received via long lengths of cable, and in particular, to gain controllers for controlling the signal gain of such adaptive signal equalizers. 
     2. Description of the Related Art 
     As part of the process of recovering data which has been transmitted over a long length of cable at a high data rate, equalization of the received data signal is required in order to compensate for the loss and phase dispersion characteristics of the cable. For example, referring to FIG. 1, the signal losses associated with a cable increase with frequency, and such signal losses become greater as the cable length is increased from a virtually zero length L 0  to greater cable lengths L 1 , L 2 , L 3 , . . . . Therefore, higher order frequency components of the data signal become increasingly attenuated as compared to the lower order frequency components. Accordingly, the degree of signal equalization required increases with frequency as well as cable length. 
     Further, in those applications where the transmission cable lengths may vary, such equalization must be adaptive by being able to adapt to variations in the transfer function of the cable due to variations in the cable length. 
     Referring to FIG. 2, a conventional adaptive equalizer  20  includes a unity-gain buffer  22 , a high-pass filter  24 , a mixer  26  and a signal summation stage  28 , interconnected as shown. The input signal V i  is processed by both the unity-gain buffer stage  22  and filtered by the high-pass filter  24 . The high-pass filtered signal  25  is mixed with a gain control signal α in the mixer  26 . The unity-gain buffered signal  23  and gain-controlled, high-pass filtered signal  27  are summed together in the summation circuit  28  to produce the final output signal V o . 
     Referring to FIG. 3, it can be seen that by varying the value of the control signal α, the overall gain of the high-pass filter profile can be adjusted, thereby providing for adaptive equalization of the output signal V o . 
     While this conventional technique performs reasonably well, a number of disadvantages exist, particularly when more precise equalization control is desired. For example, depending upon a number of operating parameters of the equalization circuit  20 , such as variations in processing during manufacturing and variations in operating voltages and temperatures, the gain factor α may affect the DC biasing of portions of the circuit  20 . Further, the output signal V o  may be affected by variations in the DC bias components within the circuit  20 . Accordingly, it would be desirable to have a gain-controlled adaptive equalizer in which the gain factor α is independent of variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures. 
     SUMMARY OF THE INVENTION 
     A gain controller for an adaptive equalizer in accordance with the present invention provides a gain factor which is independent of variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures. Such a gain controller provides a self-compensating gain control signal which is based upon a variable gain control factor and tracks variations in circuit operation due to variations in circuit manufacturing processes and operating conditions (e.g., voltages and temperatures) by tracking variations in the dc biasing used to power the gain control and signal mixing stages. Such tracking of the biasing by the gain control advantageously provides for an increased dynamic range. 
     In accordance with one embodiment of the present invention, a gain controller for a signal combining circuit includes a reference signal generator circuit and a signal conversion circuit. The reference signal generator circuit is configured to receive a first bias signal and in accordance therewith provide first and second reference signals. Variations in the first bias signal are tracked by corresponding respective variations in the first and second reference signals. The signal conversion circuit, coupled to the reference signal generator circuit, is configured to receive an input control signal and the first and second reference signals and in accordance therewith provide first and second output control signals. The input control signal has a range of values with a minimum value and a maximum value. The first output control signal has a range of values which correspond to the input control signal values with minimum and maximum values which correspond to the minimum and maximum input control signal values, respectively. The second output control signal has a range of values which correspond to the input control signal values with minimum and maximum values which correspond to the maximum and minimum input control signal values, respectively. The first and second output control signals together form a differential control signal. 
     In accordance with another embodiment of the present invention, a gain controller for a signal combining circuit includes a reference signal generator circuit and a digital-to-analog signal conversion circuit. The reference signal generator circuit with a plurality of diode-connected transistors configured to receive a first bias current and in accordance therewith provide first and second reference voltages. Variations in the first bias current are tracked by corresponding respective variations in the first and second reference voltages. The digital-to-analog signal conversion circuit, coupled to the reference signal generator circuit, is configured to receive a digital control signal and the first and second reference voltages and in accordance therewith provide first and second analog control voltages. The digital control signal has a range of values with a minimum value and a maximum value. The first analog control voltage has a range of values which correspond to the digital control signal values with minimum and maximum values which correspond to the minimum and maximum digital control signal values, respectively. The second analog control voltage has a range of values which correspond to the digital control signal values with minimum and maximum values which correspond to the maximum and minimum digital control signal values, respectively. The first and second analog control voltages together form a differential control voltage. 
     In accordance with still another embodiment of the present invention, a method of providing gain control for a signal combining circuit includes the steps of: 
     receiving a first bias signal and in accordance therewith generating first and second reference signals, wherein variations in the first bias signal are tracked by corresponding respective variations in the first and second reference signals; and 
     receiving an input control signal and the first and second reference signals and in accordance therewith generating first and second output control signals, wherein 
     the input control signal has a range of values with a minimum value and a maximum value, 
     the first output control signal has a range of values which correspond to the input control signal values with minimum and maximum values which correspond to the minimum and maximum input control signal values, respectively, 
     the second output control signal has a range of values which correspond to the input control signal values with minimum and maximum values which correspond to the maximum and minimum input control signal values, respectively, and 
     the first and second output control signals together form a differential control signal. 
     In accordance with yet another embodiment of the present invention, a method of providing gain control for a signal combining circuit includes the steps of: 
     receiving a first bias current and in accordance therewith generating first and second reference voltages with a plurality of diode-connected transistors, wherein variations in the first bias current are tracked by corresponding respective variations in the first and second reference voltages; and 
     receiving a digital control signal and the first and second reference voltages and in accordance therewith generating first and second analog control voltages, wherein 
     the digital control signal has a range of values with a minimum value and a maximum value, 
     the first analog control voltage has a range of values which correspond to the digital control signal values with minimum and maximum values which correspond to the minimum and maximum digital control signal values, respectively, 
     the second analog control voltage has a range of values which correspond to the digital control signal values with minimum and maximum values which correspond to the maximum and minimum digital control signal values, respectively, and 
     the first and second analog control voltages together form a differential control voltage. 
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a graph of gain versus frequency for illustrating the complementary relationship between signal strength and corresponding equalization provided by a signal equalizer. 
     FIG. 2 is a functional block diagram of a conventional adaptive signal equalizer. 
     FIG. 3 is a graph of gain versus frequency for the gain-controlled, high-pass filtered portion of equalizer of FIG.  2 . 
     FIG. 4 is a functional block diagram of an adaptive signal equalizer in accordance with one embodiment of the present invention. 
     FIG. 5 is a schematic diagram of the unity-gain, voltage-to-current converter stage of the circuit of FIG.  4 . 
     FIG. 6 is a schematic diagram of the high-pass, voltage-to-current converter stage of the circuit of FIG.  4 . 
     FIG. 7 is a schematic diagram of the “noninverse component” section of the variable-gain mixer stage of the circuit of FIG.  4 . 
     FIG. 8 is a functional block diagram of the gain controller and tracking circuit stage of the circuit of FIG.  4 . 
     FIG. 9 is a graph of the voltage versus gain factor for the digital-to-analog converter stage of the circuit of FIG.  8 . 
     FIG. 10 is a schematic diagram of the gain control level generator stage of the circuit of FIG.  8 . 
     FIG. 11 is a schematic diagram of the “noninverse component” section of the current-to-voltage converter stage of the circuit of FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 4, an adaptive equalizer  40  in accordance with one embodiment of the present invention includes a unity-gain voltage-to-current converter  50 , a high-pass voltage-to-current converter  60 , a variable-gain mixer  70 , a gain controller and tracking circuit  80  and a current-to-voltage converter  110 , interconnected substantially as shown. The input signal voltage V i  (which is differential with noninverse V i   +  and inverse V i   −  components) is buffered by the unity-gain voltage-to-current converter  50  which is biased by a bias current I Bias  to produce a differential output current signal (I l +i l )/(I l −i l ) which includes a bias component I l  and a signal component i l . (As should be understood, the bias component is that which is due to the DC biasing of the circuit, while the signal component is that which is due to the input signal.) The input signal V i  is also high-pass filtered by the high-pass voltage-to-current converter  60 , which is also biased by the DC bias current I Bias . This stage  60  produces a differential high-pass filtered signal (I H(f) +i H(f) )/(I H(f) −i H(f) ) which includes a bias component I H(f)  and a signal component i H(f) . Both of these signals (I l +i l )/(I l −i l ), (I H(f) +i H(f) )/(I H(f) −i H(f) ) are provided to the variable-gain mixer  70 . 
     The gain controller and tracking circuit  80  is also biased by the DC bias current I Bias , and receives a digital (e.g., 8-bit) gain control signal α. In accordance with such gain control signal α, the gain controller and tracking circuit  80  generates a differential gain control signal V c , which has a noninverse component V c   +  and an inverse component V c   − . These differential control voltage components V c   + , V c   −  are provided to the variable-gain mixer  70 . 
     The variable-gain mixer  70  is also biased by the DC bias current I Bias . In accordance with the control voltage components V c   + , V c   − , which represent the gain factor α, the variable gain mixer  70  mixes its three input current signals: the DC bias current I Bias ; the unity-gain current signal (I l +i l ); and the high-pass filtered current signal (I H(f) +i H(f) )/(I H(f) −i H(f) ). Based upon the mixing of these signals, the variable-gain mixer  70  generates an output current (I O +i O )/(I O −i O ) which includes a bias component I O  and a signal component i O . 
     The output current (I O +i O )/(I O −i O ) from the variable-gain mixer  70  is converted to an output voltage V o  (which is differential with noninverse V o   +  and inverse V o   −  components) by the current-to-voltage converter  110 . 
     Referring to FIG. 5, the unity-gain voltage-to-current converter  50  includes a differential amplifier combined with two current mirrors biased between the positive VDD and negative VSS/GND terminals of the power supply. The differential amplifier includes transistors P 51 , P 52 , N 51 , N 52 , N 53  and N 54  (the prefix “P” designates a P-channel metal oxide semiconductor field effect transistor (P-MOSFET) and the prefix “N” designates an N-channel MOSFET (N-MOSFET)). The bias current mirror includes transistors N 55 , N 53  and N 54 . The signal current mirror includes transistors P 51 , P 52 , P 53  and P 54 . 
     The DC biasing for the differential amplifier includes driving the bias current mirror with the DC bias current I Bias . The gain for the differential amplifier is established by a resistor R connected between the two differential amplifier circuit branches. The inputs to the differential amplifier are driven by the noninverse V i   +  and inverse V i   −  components of the differential input signal voltage V i . The resulting differential currents, i.e., the drain currents of transistors N 51  and N 52 , are replicated by the signal current mirror to produce a differential output current with a noninverse component (I l +i l ) and an inverse component (I 1 −i l ). The bias component I l  is that component of the output current signal which corresponds to the DC biasing for the circuit, i.e., the input DC bias current I Bias . The signal component i l  is that component of the output current signal which corresponds to the input signal, i.e., the input signal voltage V i . 
     Referring to FIG. 6, the high-pass voltage-to-current converter  60  also includes a differential amplifier combined with two current mirror circuits biased between the positive VDD and negative VSS/GND terminals of the power supply. The differential amplifier includes transistors P 61 , P 62 , N 61 , N 62 , N 63  and N 64 . The bias current mirror includes transistors N 65 , N 63  and N 64 . The signal current mirror includes transistors P 61 , P 62 , P 63  and P 64 . 
     The DC biasing for the differential amplifier includes driving the input to the bias current mirror with the DC bias current I Bias . The high-pass filter transfer function for the differential amplifier is established by connecting a high-pass filter circuit  62  between the two differential amplifier circuit branches. The differential amplifier is driven by the noninverse V i   +  and inverse V i   −  components of the differential input signal voltage V i . The resulting differential currents, i.e., the drain currents of transistors N 61  and N 62 , are replicated by the signal current mirror to provide a differential output current with a noninverse component (I H(f) +i H(f) ) and an inverse component (I H(f) −i H(f) ). The bias component I H(f)  and signal component i H(f)  of the output current signals correspond to the DC bias current I Bias  and input signal voltage V i , respectively. 
     Referring to FIG. 7, the “noninverse component” section  70   n  of the variable-gain mixer  70  includes two cross-connected differential amplifier circuits: transistors N 71  and N 72 ; and transistors N 73  and N 74 . (Only that portion  70   n  of the variable-gain mixer  70  which is responsible for processing the noninverse components of the differential signals is shown here; however, it should be understood that a similar section is used for processing the inverse components.) All of the differential amplifier transistors N 71 , N 72 , N 73 , N 74  have equal channel widths W A  and lengths L A . The first differential amplifier is driven by the noninverse component (I H(f) +i H(f) ) of the high-pass filtered signal current and the differential control voltage V c  (which represents the gain factor α). This results in a differential output current with an inverse component (I 01   − +i 01   − ) which is provided to an output summing node  72  and a noninverse component (I 01   + +i 01   + ) which is provided to a “discard” summing node  74 . 
     The second differential amplifier is driven by the DC bias current I Bias  and the differential control voltage V c . This produces a differential output current with a noninverse component (I 02   + ) which is provided to the output summing node  72  and an inverse component (I O2   − ) which is provided to the “discard” summing node  74 . The output summing node  72  also receives the noninverse unity-gain signal current component (I l +i l ) and sums it together with the first inverse differential output current component (I 01   − +i 01   − ) and second noninverse differential output current component (I 02   + ) to produce an output current (I O +i O ). Similarly, the “discard node”  74  sums together the second noninverse differential output current component (I 01   + +i 01   + ) and second inverse differential output current component (I 02   − ) to produce a “discard” current (I D +i D ). 
     The output current (I O +i O ) can be expressed in terms of the DC bias current I Bias , the gain factor α (represented by the differential gain control signal V c ), the high-pass signal component (I H(f) +i H(f) ) and the unity-gain signal current component (I l +i l ) as shown below in Equation 1. 
     
       
         I O +i O =(I l +i l )+α(I H(f) +i H(f) )+(1−α)(I Bias )  Eq. 1  
       
     
     This expression can be rewritten to separate the bias and signal components as shown below in Equation 2. 
     
       
         I O +i O =(i l +αi H(f) )+(I l +αI H(f) +(1−α)I Bias )  Eq. 2  
       
     
     Accordingly, the signal i O  and bias I O  output current components can be expressed shown below in Equations 3 and 4, respectively. 
     
       
         i O =i l +αi H(f)   Eq. 3  
       
     
     
       
         I O =I l +αI H(f) +I Bias −αI Bias   Eq. 4  
       
     
     With the bias component I H(f)  of the high-pass filtered signal current component (I H(f) +i H(f) ) equal to the DC bias current I Bias , the bias component I O  of the output current (I O +i O ) can be expressed as shown below in Equation 5. 
     
       
         I O =I l +I Bias   Eq. 5  
       
     
     Similarly, the “discard” current (I D +i D ) can be expressed as shown below in Equation 6. 
     
       
         I D +i D =(1−α)(I H(f) +i H(f) )+αI Bias   Eq. 6  
       
     
     This expression can be rewritten to show its dependence upon the gain control factor α as shown below in Equation 7. 
     
       
         I D +i D =I H(f) −α(I H(f) −I Bias)+( 1α)i H(f)   Eq. 7  
       
     
     Accordingly, the signal i D  and bias I D  current components can be expressed as shown below in Equations 8 and 9, respectively. 
     
       
         i D =(1−α)i H(f)   Eq. 8  
       
     
     
       
         I D =I H(f) −αI H(f) +αI Bias   Eq. 9  
       
     
     With the bias component I H(f)  of the high-pass filtered signal (I H(f) +i H(f) ) equal to the DC bias current I Bias , as noted above, the “discard” current bias component I D  can be xpressed as shown below in Equation 10. 
     
       
         I D =I H(f)   Eq. 10  
       
     
     Referring to FIG. 8, a gain controller and tracking circuit  80  (FIG. 4) in accordance with one embodiment of the present invention includes a digital-to-analog converter  82  and a gain control level generator  100 . (Alternatively, instead of a digital-to-analog converter, a pulse density modulator could be used.) The digital-to-analog converter  82  converts the digital gain control factor α into the differential control voltage components V c   + , V c   −  used by the variable-gain mixer  70 . These differential control voltage components V c   + , V c   −  are generated based upon two reference voltages V High , V Low  provided by the gain control level generator  100  which is biased by the DC bias current I Bias . 
     Referring to FIG. 9, the differential control voltage components V c   + , V c   −  vary in value, in a differential manner, between the low V Low  and high V High  reference voltage values, in accordance with the value of the gain control factor α. For example, when the gain control factor α is equal to zero, the noninverse V c   +  and inverse V c   −  components are equal to the high V High  and low V Low  reference voltages, respectively. Conversely, when α is at its maximum value, e.g., FF(hex), the noninverse V c   +  and inverse V c   −  control voltage components are equal to the low V Low  and high V High  reference voltages, respectively. 
     Referring to FIG. 10, a gain control level generator  100  (FIG. 8) in accordance with one embodiment of the present invention includes four transistors P 101 , P 102 , P 103 , P 104 , a diode  103  and five current sources  101 ,  102 ,  104 ,  105 ,  106 , all interconnected substantially as shown. Transistors P 101  (with channel width and length dimensions of W B  and L B , respectively) and P 102  (with channel width and length dimensions of W C  and L C , respectively) are biased by a current source circuit  102  and current sink circuit  101 , each of which generates a bias current I B . The diode  103  is used to reduce the voltage drop across transistor P 102 , but is not necessary and, therefore, can be omitted by connecting the drain of transistor P 102  directly to VSS/GND. Transistors P 101  and P 102  have identical threshold voltages V th  and respective gate-to-source “on” voltages V on(P101)  and V on(P102) . Accordingly, the compensated voltage V(PVT) generated at the source of transistor P 102  can be expressed as shown below in Equation 11. 
     
       
         V(PVT)=VDD−V gs(P101) +V gs(P102)   Eq. 11  
       
     
     This expression can be rewritten by substituting for the gate-to-source voltages V gs(P101)  and V gs(P102)  of transistors P 101  and P 102 , respectively, as shown below in Equation 12. 
     
       
         V(PVT)=VDD−(V th +V on(P101) )+(V th +V on(P102) )  Eq. 12  
       
     
     Simplifying further, this expression reduces to that shown below in Equation 13. 
     
       
         V(PVT)=VDD−(V on(P101) −V on(P102)   Eq. 13  
       
     
     Accordingly, the voltage V on  across current sources  102  and  104 , which is set equal to or greater than the required voltage V P64  across the current mirror transistor P 64  providing the noninverse component of the high-pass filtered signal (I H(f) +i H(f) ) in the high-pass voltage-to-current converter  60  (FIG.  6 ), can be expressed as shown below in Equation 14. 
     
       
         V on =V on(P101) −V on(P102)   Eq. 14  
       
     
     This voltage V(PVT) is used, along with current sources  104 ,  105  and  106  to bias transistors P 103  and P 104  to generate the high V High  and low V Low  reference voltages. Diode-connected transistors P 103  and P 104  have equal channel width W A  and length L A  dimensions, which also equal the corresponding device dimensions of the transistors in the variable-gain mixer  70  (FIG.  7 ). Current source circuit  104  and sink circuit  105  generate bias currents I Bias  equal to the DC bias currents I Bias  used to bias the unity-gain voltage-to-current converter  50 , the high-pass voltage-to-current converter  60  and the variable-gain mixer  70  (FIG.  4 ). Current sink circuit  106  generates a trickle current I T  which is very low in value and is used to maintain transistor P 104  in a minimal on state. 
     This circuit  100 , because of the above-noted relationships between bias currents I Bias  and transistor channel dimensions W A , L A , generates the high V High  and low V Low  reference voltages such that these voltages V High , V Low  track variations in the bias current I Bias  as well as variations in the operating parameters of the transistors such as threshold voltage and charge carrier mobility. In turn, this allows the output current signal (I O +i O ) to also track variations in the bias current I Bias  as well as variations in the operating parameters of the transistors such as threshold voltage and charge carrier mobility (e.g., due to variations in manufacturing processes and operating voltages and temperatures). 
     Referring to FIG. 11, the “noninverse component” section  110   n  of the output current-to-voltage converter  110  (FIG. 4) can be implemented as follows. (Only that portion  110   n  of the output current-to-voltage converter  110  which is responsible for processing the noninverse component of the differential output current is shown here; however, it should be understood that a similar section is used for processing the inverse component.) The output current signal (I O +i O ) drives the input to a current mirror formed by transistors N 111  and N 112 . The output current through transistor N 112  produces a voltage drop across the load resistor R L , thereby generating the output voltage V o   + . 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.