Abstract:
A central processing unit (hereinafter &#34;CPU&#34;) has a number of functional units and a tuning port for modifying one or more parameters of the functional units (hereinafter &#34;tunable units&#34;). The combination (also called a &#34;tuning assembly&#34;) formed by a tuning port and the tunable units allows a CPU to be fine tuned, i.e. take on different configuration profiles (as defined by the tunable units&#39; parameters) for efficiently executing different application programs. Therefore, a CPU that includes a tuning assembly as described herein can take on a first configuration profile capable of most efficiently executing a first application program such as a computer game, and can take on a second configuration profile capable of most efficiently executing a second application program such as a spreadsheet and so on. The CPU&#39;s configuration profile can be changed even during the execution of an application program by changing the tunable units&#39; parameters. Such fine tuning allows the CPU to execute different portions of an application program more efficiently than possible in the prior art.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to and incorporates by reference herein in their entirety the following commonly owned, concurrently filed, copending U.S. Patent Applications: 
     1. &#34;A Method For Changing Operation of Circuitry in A CPU Based on a Statistic of Performance of the CPU&#34; by Sherman Lee and David G. Kyle, now U.S. Pat. No. 5,812,425; and 
     2. &#34;A Method For Identifying And Correcting Errors In A Central Processing Unit&#34; by Sherman Lee and David G. Kyle, U.S. application Ser. No. 08/710,336, filed Sep. 16, 1996. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to a device for changing the structure and operation of a central processing unit (CPU). In particular, this invention relates to a device, such as a port, in a CPU that can modify one or more parameters of a number of functional units included in the CPU, thereby to fine tune operation of the CPU. 
     BACKGROUND OF THE INVENTION 
     A conventional microprocessor, such as INTEL&#39;S P6, has a predetermined configuration (resulting from design trade-offs) that allows certain types of application programs to run faster than other types. For example, INTEL&#39;S P6 is optimized for 32-bit software, i.e. runs application programs having 32-bit programming model faster than application programs having 16-bit programming model. 
     Specifically, an article &#34;P6 stirs up software issues&#34;, by Alexander Wolfe, Electronic Engineering Times, Oct. 30, 1995, page 22 states: &#34;a 133-MHz P6 running Windows 3.1 runs 10 to 20% slower than a Pentium&#34;. The article also cites an INTEL warning that &#34;programs that intermix . . . use of 8-, 16- and 32-bit registers can result in partial pipeline stalls, which slow performance.&#34; 
     According to Wolfe, &#34;Intel is providing special optimizing compilers and a software performance aide called the Visualized Tuning Tool (V Tune).&#34; However, such tools fail to improve the performance of application programs (such as 16-bit code) that predate the P6. Therefore, to use INTEL&#39;s P6 a user must discard such preexisting software and buy a new generation of 32-bit software at a considerable expense. 
     Conventional microprocessors, such as INTEL&#39;s PENTIUM™ have one or more on-chip caches with &#34;modes&#34;, such as a &#34;cache disabled&#34; (CD) mode and a &#34;not write thru&#34; (NW) mode. The PENTIUM&#39;s modes are described in &#34;Pentium™ Processor User&#39;s Manual&#34; (see in particular Volume 1, Chapter 3) available from Intel Corporation, Literature Sales, PO Box 7641, Mt. Prospect, Ill. 60056-7641 that is incorporated by reference herein in its entirety. For example, setting a bit CD to 0 in register CR0 of the PENTIUM™, results in disabling a cache in the PENTIUM™(see Table 3-2 of the above-incorporated manual). Moreover, Intel states that &#34;the cache must be flushed after being disabled . . . &#34;. 
     SUMMARY 
     A central processing unit (hereinafter &#34;CPU&#34;) in accordance with the invention has a number of functional units and a tuning port for fine tuning the functional units. The tuning port can be used to modify one or more parameters of the functional units (hereinafter &#34;tunable units&#34;) so that the tunable units operate in harmony with software to be executed by the CPU. The functional units&#39; parameters (also called &#34;multi-valued parameters&#34;) can have one of a number (e.g. 4) of different values selectable from a predetermined range (e.g. programming model sizes of 8 bit, 16 bit, 32 bit and 64 bit). 
     Moreover, a combination (also called &#34;tuning assembly&#34;) formed by the tuning port and the tunable units allows the CPU as a whole to be fine tuned, i.e. take on different configuration profiles depending on the characteristics (such as loopiness) of the software to be executed. The configuration profiles are defined by the tunable units&#39; parameters (such as a cache&#39;s prefetch size) that can be changed for efficient execution of application programs having characteristics different from one another. As the parameters are multi-valued, the tunable units&#39; behavior can be changed gradually and incrementally, so that the CPU can be kept in tune with the changing needs of one or more application programs. 
     Specifically, a CPU (such as a microprocessor) that includes a tuning assembly as described herein can take on a first configuration profile capable of efficiently executing a first application program, such as a computer game. The same microprocessor can also take on a second configuration profile capable of efficiently executing a second application program, such as a spreadsheet. The microprocessor&#39;s configuration profile (hereinafter simply &#34;profile&#34;) can be changed &#34;on the fly&#34;, e.g. by interrupting the execution of an application program, changing the tunable units&#39; parameters and resuming execution of the application program. 
     Such &#34;on the fly&#34; fine tuning allows a microprocessor to execute different portions of an application program with profiles suitable to those portions, and therefore execute the application program as a whole more efficiently. Such &#34;on the fly&#34; fine tuning also allows efficient execution even in case a user switches between two different applications. Finally, &#34;on the fly&#34; fine tuning allows two different operating systems, such as MICROSOFT WINDOWS and APPLE MACINTOSH to fine tune the same CPU depending on their specific characteristics. 
     In one embodiment, the tuning port is responsive to signals (hereinafter &#34;parameter signals&#34;) that are indicative of parameters of a to-be-implemented profile, and that are received at a number of configuration input terminals included in the tuning port. The to-be-implemented profile&#39;s parameter signals (also called &#34;shadow parameter signals&#34;) may be received at external pins, e.g. from an in-circuit emulator, or from an on-board execution unit on execution of certain instructions. 
     The tuning port&#39;s configuration output lines are coupled to the tunable units, and pass to the tunable units the currently-implemented profile&#39;s parameters signals (also called &#34;current parameter signals&#34;). The tuning port also receives from the tunable units a number of statistics signals on a number of statistics input lines coupled to the tunable units. The tuning port makes the received statistics signals available (either unmodified or averaged in two embodiments) at a number of statistics output terminals included in the tuning port. 
     In one variant of this embodiment, the tuning port has a first set of storage elements (hereinafter &#34;shadow storage elements&#34;) that hold the received shadow parameter signals and a second set of storage elements (hereinafter &#34;current storage elements&#34;) that hold the current parameter signals. The tuning port copies the shadow parameter signals into the current storage elements and drives the copied parameter signals on to the configuration output lines in response to an active signal on the configuration switch terminal. 
     In this variant, the tuning port&#39;s storage elements can be organized into multi-parameter groups specific to each characteristic of the CPU. For example, a multi-parameter execution group of storage elements is associated with execution, a multi-parameter &#34;cache&#34; group of storage elements is associated with a cache and a multi-parameter FPU group of storage elements is associated with a floating point unit. 
     An active signal on the configuration switch terminal can be generated by a flip-flop, for example on execution of a return from interrupt instruction if signals in a current storage element and the corresponding shadow storage element differ from each other. Alternatively, an active signal on the configuration switch signal can be received at an external pin of the microprocessor, for example from an in-circuit emulator. 
     The tuning port also includes a number of statistics storage elements coupled between the unit statistics lines and the statistics terminals. The statistics storage elements store statistics signals from the unit statistics lines and drive the stored statistics signals on the statistics terminal. 
     Tunable units in one embodiment of the invention include a pipeline, an arithmetic logic unit, a bus interface unit, a cache, a branch prediction unit and a floating point unit. Each tunable unit has a unit input terminal coupled to a different one of the configuration output line of the tuning port. Depending on a signal on the unit input terminal, each tunable unit reorganizes itself into one of a number of predetermined structures specific to that unit. Each tunable unit also has a unit output terminal, and drives a statistics signal on the unit output terminal. The statistics signals can be used to determine efficiency of the tunable unit while operating in a specific predetermined structure. Such statistics signals can also be analyzed to determine the efficiency of the CPU as a whole. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates in a high level block diagram, a computer system included a tunable CPU having a fine tuning port and a number of fine tunable units in accordance with the invention. 
     FIG. 2 illustrates the various registers in the fine tuning port of FIG. 1. 
     FIGS. 3A and 3B illustrate respectively, two different predetermined structures of a tunable pipeline in accordance with the invention. 
     FIGS. 4A and 4B illustrate respectively, two different predetermined structures of a tunable arithmetic logic unit (ALU) in accordance with the invention. 
     FIGS. 5A and 5B illustrate respectively, two different predetermined structures of a tunable branch prediction unit (BPU) in accordance with the invention. 
     FIGS. 6A and 6B illustrate respectively, two different predetermined structures of a tunable multimedia execution unit (MEU) in accordance with the invention. 
     FIGS. 7A and 7B illustrate respectively, two different predetermined structures of a tunable floating point unit (FPU) in accordance with the invention. 
     FIGS. 8A-8B, 8C-8D, 8E-8F illustrate a cache with, respectively, two different cache sizes, two different prefetch sizes and two different cache replacement modes. 
     FIGS. 9A-9D illustrate a cache with four different cache organization modes. 
    
    
     DETAILED DESCRIPTION 
     A microprocessor in accordance with the invention includes a number of functional units and a tuning port for monitoring and fine tuning the functional units. The functional units (hereinafter &#34;tunable units&#34;) can be fine tuned by modifying one or more parameters so that the tunable units operate in harmony with (e.g. in tune with needs of) application programs being executed by the CPU. Each parameter (also called &#34;multi-valued parameter&#34;) can have one of a number (e.g. 1024) of different values selectable from a predetermined range (e.g. cache size in the range 0-1023 bytes). 
     Therefore, a CPU in accordance with the invention can take on different configuration profiles (defined by the parameters) depending on the application programs being executed. Such a degree of fine tuning is not possible when a cache is merely disabled and enabled, for example, by use of a single-valued signal (e.g. an ON/OFF signal). 
     In one embodiment, a computer system 10 includes a system bus 11 that is connected to a number of peripherals such as a floppy drive 12, a hard disk 13, a monitor 14, a keyboard 15 and a mouse 16. System bus 11 is coupled by a system bridge 20 to a CPU bus 21 that in turn is coupled to a main memory 22. CPU bus 21 also coupled to a central processing unit (hereinafter &#34;tunable CPU&#34;) 100 that includes a fine tuning port 110. Fine tuning port (hereinafter &#34;tuning port&#34;) 110 includes the first set of storage elements (hereinafter &#34;shadow storage elements&#34;) 111A-111N, that store a number of parameter signals received at a number of configuration input terminals 112. Tuning port 110 also includes a second set of storage elements (hereinafter &#34;current storage elements&#34;) 113A-113N that drive parameter signals on a number of configuration output lines 114A-114N. 
     Fine tuning port 110 also includes a flip-flop (hereinafter &#34;parameter update flip-flop&#34;) 115 that is coupled to a configuration switch terminal 116 of the fine tuning port 110. In response to an active signal on configuration switch terminal 116, parameter switch flip-flop drives a signal active on one of lines 117A-117N that cause current storage elements 113A-113N to clock a signal from shadow storage elements 111A-111N out to the configuration output lines 114A-114N. 
     A signal on configuration switch terminal 116 can be driven active on an eternal pin 116E either by an external device, such as an in-circuit emulator 30 (FIG. 1) or alternatively by execution unit 130 on execution of an instruction, e.g. a write into a model specific register 140. 
     Model specific register 140 can be implemented as described in, for example, &#34;The CPU and Undocumented Instructions,&#34;Chapter 3 &#34;The Undocumented PC&#34; by Frank Van Gilluwe, Addison-Wesley Publishing Company, Reading, Mass., that is incorporated by reference herein in its entirety. 
     Also, a signal on configuration switch terminal 116 can also be driven by use of boundary-scan (JTAG) and built-in self-test (BIST) structures, in a manner well known to a person of skill in the art of designing microprocessors in view of the enclosed disclosure. 
     Although specific circuitry is described herein for a particular embodiment of the invention, other such embodiments will be obvious to the skilled person in view of the enclosed disclosure. Accordingly, the embodiments described herein are merely illustrative and not limiting. 
     In this embodiment, fine tuning port 110 also includes a third set of storage elements (hereinafter &#34;statistics&#34; storage elements) 117A-117N that receive a number of statistics signals on statistics input lines 118A-118N also included in fine tuning port 110. Fine tuning port 110 supplies the stored statistics signals on statistics terminals 119. 
     In this embodiment, tunable CPU 100 also includes a number of fine tunable units 120A-120N that are coupled to fine tuning port 110. Specifically, fine tunable units 120A-120N receive a number of parameter signals at unit input terminals 121A-121N that are coupled to the configuration output lines 114A-114N of fine tuning port 110. Moreover, fine tunable units 120A-120N also have a number of unit output terminals 122A-122N that are coupled to statistics input lines 118A-118N of fine tuning port 110. 
     Tunable CPU 100 also includes an instruction execution unit 130 that is coupled to configuration input terminals 112A, configuration switch terminal 116 and statistics output terminals 119. Instruction execution unit 130 analyzes the statistics signals available at statistics output terminals 119 to determine the parameter signals to be supplied to configuration input terminals 112 and after supplying all of the necessary parameter signals, drives a signal active on the configuration switch terminal 116 to thereby cause tunable CPU 100 to assume a new configuration profile. 
     Fine tunable units 120A-120N have internal structures that can be changed (logically) to behave differently depending on the parameter signals received at unit input terminals 121A-121N. As a parameter signal can have one of a number of values, each of fine tunable units 120A-120N can be changed gradually and incrementally depending on the needs of the application programs. Fine tunable units 120A-120N also provide a measure of performance of the structures at the unit output terminals 122A-122N. 
     Although in the embodiment illustrated in FIG. 1, each of current storage elements 113A-113N is connected by one of configuration output lines 114A-114N to one of fine tunable units 120A-120N, any number of current storage elements can be coupled to a single fine tunable unit. Fine tunable units 120A-120N can be any type of a functional unit, such as a branch prediction unit, a floating point unit, a multimedia execution unit, a cache, a pipeline and an arithmetic logic unit. 
     Although in FIG. 1, each fine tuneable unit 120A-120N is illustrated as being coupled to only one of current storage elements 113A-113N and one of statistics storage elements 117A-117N, any number of such storage elements can be coupled to a single fine tuneable unit in tuneable CPU 100. 
     In one particular embodiment, a first group (hereinafter &#34;multi-parameter execution group&#34;) of storage elements 210 (FIG. 2) includes statistic storage elements 211-213 and 221-222 and current storage elements 214-217 and 223 all of which are coupled to an execution unit 219 (that includes a multimedia unit). Statistic storage elements 211-213, 221-222 respectively store the signals RATE OF 16 BIT INSTRUCTIONS, RATE OF 32 BIT INSTRUCTIONS, RATE OF BRANCH PREDICTIONS, RATE OF VIDEO OPERANDS and RATE OF AUDIO OPERANDS. 
     Current storage elements 214-217 and 223 store parameters signals INSTRUCTION WIDTH, PIPELINE SIZE, DEGREE OF OUT OF ORDER EXECUTION, BRANCH PREDICTION MODE and MEU BIT SIZE. After assessment of CPU 110&#39;s execution from the statistics signals in the statistic storage elements 211-213 and 221-222, the parameter signals and storage elements 214-217 and 223 can be changed as necessary, thereby to change the structure (logically) and operation of execution unit 219 as described more completely below in reference to FIGS. 3A-3B, 4A-4B, 5A-5B and 6A-6B. 
     Fine tuning port 110 also includes a second group (hereinafter &#34;multi-parameter FPU group&#34;) 230 formed of a number of statistics storage elements 231-234 and a number of current storage elements 235-236. Statistic storage elements 231-234 are used to store the statistic signals RATE OF 16 BITS OPERANDS, RATE OF 32 BIT OPERANDS, RATE OF OVERFLOWS and RATE OF UNDERFLOWS. Current storage elements 235 and 236 are used to store the parameter signals FPU PRECISION SIZE and FPU ROUNDING MODE. All of storage elements 231-236 and FPU tuning group 230 are coupled to, and are used to tune tuneable floating point unit 239 as described more completely below in reference to FIGS. 7A-7B. 
     Finally, fine tuning port 110 includes a third group (hereinafter &#34;multi-parameter cache group&#34;) 240 formed by statistics storage elements 241-243 and current storage elements 244-247 that are coupled to and are used to tune tuneable cache 249. Specifically, statistic storage elements 241-243 store the signals RATE OF HITS IN INSTRUCTION CACHE, RATE OF HITS IN DATA CACHE and NUMBER OF INSTRUCTIONS IN A LOOP. Current storage elements 244-247 store the parameter signals CACHE SIZE, CACHE REPLACEMENT MODE, PREFIX SIZE, CACHE ORGANIZATION MODE and MEMORY UPDATE MODE respectively. Storage elements 241-248 are coupled to and are used to tune i.e. change the structure and operation of tuneable cache 249, as described more completely below in reference to FIGS. 8A-8B . . . 12A-12D. 
     In one embodiment, tuneable execution unit 219 includes a tuneable pipeline 300 (FIG. 3A) having a pipeline configuration circuit 310 that is coupled to current storage element 215 and that is tuned by the parameter signal PIPELINE SIZE. Tuneable pipeline 300 also includes pipeline stages 321-325 of the type described in, for example, INTEL&#39;s &#34;Pentium™ Processor User&#39;s Manual&#34; Vol. 1, Chapter 3 that is incorporated by reference above. The five stages 321-325 included in tuneable pipeline 300 are determined by pipeline configuration circuit 310 based on the parameter signal PIPELINE SIZE being of value 5. 
     If parameter signal PIPELINE SIZE indicates, for example, 7 stages, then pipeline configuration circuit 310 rearranges the circuitry included in pipeline stages 321-325, and uses additional circuitry as necessary to form pipeline stages 331-337 (FIG. 3B). Pipeline stages 331-337 include two additional stages extract instructions stage 332 and operand fetch stage 335 in addition to the five stages described above. 
     Although two predetermined structures, a 5 stage pipeline and a 7 stage pipeline are illustrated in the respective FIGS. 3A and 3B as being included in tuneable pipeline 300, longer pipelines, such as a 12 stage pipeline described in, for example, &#34;Intel&#39;s P6 Users Decoupled Super Scaler Design&#34; by Linley Gwennap, Microprocessor Report, Feb. 16, 1995, pages 9-15 can also be used. 
     Alternatively, for serialized scaler operations, a smaller pipeline as described in, for example, &#34;i486™ Processor Hardware Reference Manual&#34;, Intel Corp., 1990, Chapter 2 that is incorporated by reference herein. The actual circuitry of tuneable pipeline 300 in one embodiment is obvious to a person skilled in the art of designing microprocessors in view of the enclosed disclosure. Depending on the embodiment, additional stages can be added to allow super-pipelined operation and increased frequency of operation. 
     Tuneable execution unit 219 also includes a tuneable arithmetic logic unit (ALU) 400 (FIG. 4A). Tuneable ALU 400 includes an ALU configuration circuit computation circuit 420 that has a 15 bit structure in FIG. 4A. The 15 bit structure is indicated to the ALU configuration circuit 410 by a value 16 of parameter signal OPERAND WIDTH from current storage element 214. When signaL OPERAND WIDTH indicates 32, ALU configuration circuit 410 rearranges the circuitry 420 to have a 32-bit structure, for example as illustrated in FIG. 4B. 
     During operation of circuitry 420 in either of the two predetermined structures, e.g. 16-bit structure and 32-bit structure, the circuit 420 drives signals RATE OF 16-BIT INSTRUCTIONS and RATE OF 32-BIT INSTRUCTIONS that are stored in statistics storage elements 211 and 212. Therefore, depending on the larger of the signals stored in statistics storage elements 211 and 212, circuit 420 can have one of the two structures, 16-bit structure and 32-bit structure illustrated in FIGS. 4A and 4B respectively. Although only two structures are illustrated for clarity in FIGS. 4A and 4B, other embodiments have more structures, for example, 8-bit structures, 16-bit structures, 32-bit structures and 64-bit structures. 
     Therefore, a CPU in accordance with the invention can be tuned to execute application programs having a 16-bit programming model faster than execution of application programs having a 32-bit programming model, or vice versa, depending on the structures and arrangement of the structures that is used. 
     Moreover, depending on the signal DEGREE OF OUT OF ORDER EXECUTION from current storage element 216, ALU configuration circuit 410 can use, for example, two ALUs in parallel, thereby to allow superscalar execution of sequential instructions, out of order with each other. The number of such instructions executed out of order depends on the number of reorder buffers which in turn depends on the parameter signal DEGREE OF OUT OF ORDER EXECUTION. Therefore, the same ALU configuration circuit 410 is responsive to two parameter signals (stored in respective current storage elements 214 and 216). 
     Tuneable execution unit 219 also includes a tuneable branch prediction unit (BPU) 500 (FIG. 5A) that includes a branch configuration circuit 510 coupled to current storage element 217 and statistics storage element 213. When signal BRANCH PREDICTION MODE in current storage element 217 is inactive, tuneable BPU 500 includes a &#34;backward taken forward not taken&#34; logic 520 that uses a branch target cache 530 for branch prediction. 
     Alternatively, when signal BRANCH PREDICTION MODE is active, branch configuration circuit 510 rearranges the circuitry in tuneable BPU 500 to form a branch prediction logic 540 that uses a branch target buffer 550. Branch target buffer 550 includes a branch target address cache 551, a branch history table 552 at one or more pattern tables 553 of the type described in, for example, the &#34;Pentium™ Processor User&#39;s Manual&#34; incorporated by reference above. 
     Therefore tuneable BPU 500 has one of two predetermined structures illustrated in FIGS. 5A and 5B, depending on the signal BRANCH PREDICTION MODE. Branch configuration circuit 510 drives the signal RATE OF BRANCH PREDICTIONS that is stored in statistics storage element 213, and can be used to change the signal BRANCH PREDICTION MODE. 
     In one embodiment, a tuneable multimedia execution unit (MEU) 600 includes a MEU configuration circuit 610 that is coupled to current storage element 223 and statistics storage elements 221 and 222. Tuneable MEU also includes a multimedia circuit 620 that includes a first predetermined structure formed by 4-bit shifters 621 and 622 that convert to video signals V1 and V2 into 4-bit signals S1 and S2. MEU configuration circuit 610 rearranges 4-bit shifters 621 and 622 into an 8-bit shifter 623 (FIG. 6B) by driving a control signal active to an AND gate 624 that couples 4-bit shifter 621 to 4-bit shifter 622. 8-bit shifter 623 converts an audio signal A into an 8-bit byte S. 
     MEU configuration circuit 610 drives the signal to AND gate 624 active or inactive, depending on the signal MEU SHIFTER SIZE stored in current storage element 223. MEU configuration circuit 610 keeps track of the rate of audio and video operands being processed therein and supplies signals RATE OF AUDIO OPERANDS and RATE OF VIDEO OPERANDS for storage in statistic storage elements 221 and 222. 
     Tuneable CPU 100 includes a tuneable floating point unit (FPU) 700 (FIG. 7A). Tuneable FPU 700 includes a FPU configuration 710 that is coupled to current storage element 236 and statistic storage elements 233 and 234. Tuneable FPU 700 includes a circuit 720 having &#34;round up&#34; logic 731 selected from logics 731-734 by multiplexer 735 depending on a signal from FPU configuration circuit 710. 
     Alternatively, circuit 720 can have a &#34;round to nearest even&#34; structure that is selected by multiplexer 735. Any one of the logics 731-734 can be selected by multiplexer 735 depending on the signal from FPU configuration circuit 710. FPU configuration circuit 710 simply passes the signal FPU ROUNDING MODE that is stored in current storage element 236. FPU configuration circuit 710 also keeps track of the number of times an overflow or an underflow situation occurs, and drives the signal RATE OF OVERFLOW and RATE OF UNDERFLOWS. 
     Although not illustrated in FIGS. 7A-7B tuneable FPU 700 is also responsive to a signal FPU PRECISION SIZE from current storage element 235 that is coupled to FPU configuration circuit 710. FPU configuration circuit 710 changes the number of bits used by tuneable FPU 700 depending on the signal storage element 235, in a manner similar to that described above for tuneable MEU 229. 
     Tuneable CPU 100 also includes a tuneable cache 800 (FIG. 8A) having a cache configuration circuit 810 that is coupled to current storage element 244 and statistics storage element 241 and 242. Tuneable cache 800 also includes a first set of storage elements I1, I2 . . . IK collectively referred to as instruction cache 820 and a second set of storage elements D1, D2 . . . DM collectively referred to as data cache 830. 
     In this embodiment, cache configuration circuit 810 separates the storage elements I1-IK from the storage elements D1-DM by defining a boundary B1 depending on a signal CACHE BOUNDARY from current storage element 244. Therefore, tuneable cache 800 changes from the structure illustrated in FIG. 8A to the structure illustrated in FIG. 8B, i.e. has a larger instruction cache 840 and a smaller data cache 850 when cache configuration circuit 810 redefines the boundary B2 as being between storage elements I1-IR and D1-D2 depending on the signal CACHE BOUNDARY. 
     Cache configuration circuit 810 keeps track of the rate of hits in the instruction cache and in the data cache for use in deciding allocation of storage elements between an instruction cache and a data cache. For example, a small instruction cache may be adequate when a function is repeatedly performed on a large amount of data, whereas a large instruction cache may be appropriate if a complex number crunching function is performed on a small amount of data. 
     Similarly, cache configuration circuit 810 changes boundary AP that defines the number of storage elements I1, I2 . . . IA used for prefetching of instructions depending on signal PREFETCH SIZE from current storage element 246. Therefore, tuneable cache 800 in FIG. 8D has a different structure that includes for example storage elements I1, I2 . . . IP that are smaller in number than the storage elements I1, I2 . . . IA, and therefore result in a nonaggressive prefetch. Cache configuration circuit 810 also drives the signal NUMBER OF INSTRUCTIONS IN A LOOP that is stored in statistics storage element 243, and is used to determine the appropriate value of the parameter signal PREFETCH SIZE. 
     Cache configuration circuit 810 is also responsive to a signal CACHE REPLACEMENT MODE from current storage element 245 and selects one of predetermined structures, such as FIFO logic 831 and LRU logic 832. Specifically, in response to an inactive signal CACHE REPLACEMENT MODE cache configuration circuit 810 selects FIFO logic 831 for use in replacement of entries from the storage elements in tuneable cache 800 to main memory 22 as illustrated in FIG. 8E. 
     Moreover, in response to an active signal CACHE REPLACEMENT MODE cache configuration circuit 810 selects LRU logic 832 for replacement of entries to main memory 22 as illustrated in FIG. 8F. As described above, cache configuration circuit 810 drives the signal RATE OF HITS IN INSTRUCTION CACHE and RATE OF HITS IN DATA CACHE. 
     Cache configuration circuit 810 is also responsive to a signal CACHE ORGANIZATION MODE from current storage element 246, having one of the four values DIRECT MAP, 2-WAY SET ASSOCIATIVE, 4-WAY SET ASSOCIATIVE and FULLY ASSOCIATIVE. Depending on the signal CACHE ORGANIZATION MODE cache configuration circuit 810 rearranges the storage elements in tuneable cache 800 into one of the four structures illustrated in FIGS. 9A-9D. 
     Numerous modifications and adaptions of the above described embodiments will be obvious to a person of skill in the art of designing microprocessors in view of the enclosed disclosure. For example, the devices and methods described herein can be used with the devices and methods described in the above-incorporated applications, U.S. Pat. No. 5,812,425 and U.S. patent application Ser. No. 08/710,336. Various such modifications and adaptions are encompassed by the attached claims.