Abstract:
A coaxial copper pillar for signal transmission with signal shield is disclosed so that signal integrity for the signal passes transmission is maintained. One embodiment shows at least one coaxial copper pillar is made as a terminal connector for a chip package, the coaxial copper pillars are made adaptive for electrically coupling the chip package to a mother board.

Description:
BACKGROUND 
       [0001]    Technical Field 
         [0002]    The present invention relates to a coaxial copper pillar, especially relates to a coaxial copper pillar designed for signal transmission in an electronic system. 
         [0003]    Description of Related Art 
         [0004]      FIG. 1  show a prior art 
         [0005]      FIG. 1  shows a prior art 
         [0006]      FIG. 1  shows a chip package and a mother board  11 . The chip package is ready to be mounted onto the mother board  11 . The mother board  11  has a plurality of metal pads  113  on a bottom surface. The chip package has a plurality of solder balls  123  adaptive for electrically coupled to the metal pads  113  of the mother board  11 . The chip package comprises a package substrate  12 . The package substrate  12  has a plurality of top metal pads  121 . A passivation layer  122  is configured on a top surface of the package substrate  12 . A chip  13  is configured on a bottom of the package substrate  12 . A finer metal connector to replace the solder ball connector is needed to develop for a compact chip package. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  show a prior art. 
           [0008]      FIGS. 2A ˜ 2 C show an embodiment according to the present invention. 
           [0009]      FIGS. 3 ˜ 2 C show a fabricating process for the embodiment according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0010]    A coaxial copper pillar is fabricated for maintaining a signal integrity during signal transmission. The coaxial copper pillar has a core copper pillar made for signal transmission and a dielectric layer wraps around the core copper pillar. A copper layer wraps around the dielectric layer as a signal shield. 
         [0011]      FIGS. 2A ˜ 2 C show an embodiment system according to the present invention. 
         [0012]      FIG. 2A  shows a mother board  21  having a coaxial metal pad  210  formed on a bottom surface of the mother board  121 . The coaxial metal pad  210  comprises a core metal pad  211  and a circular metal pad  212 . The circular metal pad  212  encircles the core metal pad  211 . The core metal pad  211  is made electrically coupled to a signal line of an electronic system (not shown). The circular metal pad  212  is made electrically coupled to a ground line of the electronic system. 
         [0013]      FIG. 2B  shows a bottom view of the coaxial metal pad of  FIG. 2A .  FIG. 2B  shows the circular metal pad  212  encircles the core metal pad  211 . The circular metal pad  212  functions as a signal shield for the core metal pad  211 . 
         [0014]      FIG. 2C  shows a chip package having a coaxial copper pillar according to the present invention. 
         [0015]      FIG. 2C  shows a package substrate  22 . The package substrate  22  has a plurality of top metal pads  121 . A coaxial copper pillar  310  is formed on a top surface of a selected top copper pillar  121 . 
         [0016]    The coaxial copper pillar  310  comprises a core copper pillar  125 . The core copper pillar  125  has a bottom end electrically coupled to the selected top metal pad  121 . The coaxial copper pillar  310  comprises a dielectric layer  225  wraps around an outer surface of the core copper pillar  125 . Further, a copper layer  325  wraps around an outer surface of the dielectric layer  225 . 
         [0017]    The package substrate  22  comprises a first redistribution layer RDL 1  and a second redistribution layer RDL 2 . The first redistribution layer RDL 1  has a first redistribution circuitry RDC 1  embedded in a first dielectric layer(s) D 1 , D 2 . The second redistribution layer RDL 2  configured on a top surface of the first redistribution layer RDL 1 . The second redistribution layer RDL 2  comprises a second redistribution circuitry RDC 2  embedded in a second dielectric layer(s) D 3 , D 4 . The top metal pad  121  is configured on a top surface of the package substrate  22  and is a portion of the second redistribution circuit RDC 2 . 
         [0018]    At lease one chip  13  is configured on a bottom surface of the package substrate  22 . The chip  13  is electrically coupled to a bottom metal pad of the package substrate  22 . An underfill material  126  is filled into a gap between the chip  13  and a bottom surface of the package substrate  22 . A molding compound  127  encapsulates the chip  13 . 
         [0019]    A passivation layer  122  is configured on a top surface of the package substrate  22  and exposes a central area of the top metal pad  121  for further electrical connection. 
         [0020]      FIGS. 3 ˜ 21  show a fabricating process for a coaxial copper pillar according to the present invention. 
         [0021]    A fabricating process for a coaxial copper pillar, comprises: 
         [0022]      FIG. 3  shows: preparing a substrate  22 ; wherein at least one metal pad  121  is configured on a top surface of the substrate  22 ; a passivation  122  is configured on a top surface of the substrate  22 ; and a central area of the metal pad  121  is exposed; 
         [0023]      FIG. 4  shows: forming a seed layer  123  on a top surface of each metal pad  121  and the passivation layer  122 ; 
         [0024]      FIG. 5  shows: forming a first photoresist layer (PR 1 ) on a top surface of the seed layer  123 ; 
         [0025]      FIG. 6  shows: patterning the first photoresist layer (PR 1 ) to form a plurality of first grooves  124 ; 
         [0026]      FIG. 7  shows: plating to fill metal, e.g. copper, in each first groove  124  to form a plurality of copper pillars  125 ; 
         [0027]      FIG. 8  shows: stripping the first photoresist layer (PR 1 ); 
         [0028]      FIG. 9  shows: stripping the seed layer  123  between the copper pillars  125 ; 
         [0029]      FIG. 10  shows: forming a second photoresist layer (PR 2 ) on a top surface of the passivation layer  122  and the copper pillars  125 ; 
         [0030]      FIG. 11  shows: patterning the second photoresist layer (PR 2 ) to form a plurality of second grooves  224  to expose selected copper pillars  125 ; 
         [0031]      FIG. 12  shows: filling dielectric material  225  into the second grooves  224 ; 
         [0032]      FIG. 13  shows: removing excessive materials on a top surface of the copper pillars  125 ; 
         [0033]      FIG. 14  shows: stripping the second photoresist layer (PR 2 ); 
         [0034]      FIG. 15  shows: forming a third photoresist layer (PR 3 ); 
         [0035]      FIG. 16  shows: patterning the third photoresist layer (PR 3 ) to form a plurality of third grooves  324  to expose the selected copper pillar  125  wrapped by the dielectric layer  225 ; 
         [0036]      FIG. 17  shows: electroless plating to form copper layer  325 ,  325 T wrapping an exposed surface of the dielectric layer; wherein the copper layer  325  wraps a side wall surface, and the copper layer  325 T is configured on a top surface of the selected copper pillar  125  wrapped by the dielectric layer  225 ; 
         [0037]      FIG. 18  shows: stripping the third photoresist layer (PR 3 ); 
         [0038]      FIG. 19  shows: removing the top copper layer  325 T on a top surface of the copper pillar  125  wrapped by the dielectric layer  225 ; 
         [0039]      FIG. 20  shows: mounting at least a chip  13  on a bottom surface of the bottom pads  221 ; and underfilling a space between the chip  13  and the substrate  22 ; and 
         [0040]      FIG. 21  shows: singulating to form a plurality of chip package units. 
         [0041]    While several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be configured without departs from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims.