Abstract:
A FLASH memory device comprising a substrate having a gate conductor formed thereover is provided. The gate conductor comprises a gate with a floating gate oxide layer formed thereon, the floating gate oxide layer including respective lateral tip portions, whereby the forward tunneling voltage of the FLASH memory is improved. In one embodiment, the respective tip portions have an average width of greater than or equal to about 250 Å.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation-in-part of copending Application Ser. No. 10/975,672 filed, Oct. 28, 2004, entitled “Method to Improve FLASH Forward Tunneling Voltage (FTV) Performance”, the entirety of which is hereby incorporated by reference herein, which is a continuation of U.S. patent application Ser. No. 10/290,644, filed Nov. 8, 2002, now U.S. Pat. No. 6,825,085, the entirety of which is hereby incorporated by reference herein. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to semiconductor fabrication and more specifically to formation of flash memory floating gate oxide.  
       BACKGROUND OF THE INVENTION  
       [0003]     The most important electrical parameter of Flash memory is Forward Tunneling Voltage (FTV). FTV is a measurement of the ease of erasing the cell by removing the charge from the floating gate (FG) to the control gate (GC). The trap-up rate, i.e. electron (e − ) trapping in oxide, is also an important electrical parameter.  
         [0004]     U.S. Pat. No. 6,031,264 B1 to Chien et al. describes a flash EEPROM process using polyoxide steps.  
         [0005]     U.S. Pat. No. 5,879,993 to Chien et al. describes a flash EEPROM process.  
         [0006]     U.S. Pat. No. 6,355,527 B1 to Lin et al. describes a flash EEPROM process.  
         [0007]     U.S. Pat. No. 6,088,269 to Lambertson and U.S. Pat. No. 6,358,796 B1 to Lin et al. each describe related Flash processes.  
       SUMMARY OF THE INVENTION  
       [0008]     A FLASH memory device comprising a substrate having a gate conductor formed thereover is provided. The gate conductor comprises a gate with a floating gate oxide layer formed thereon, the floating gate oxide layer including respective lateral tip portions, whereby the forward tunneling voltage of the FLASH memory is improved. In one embodiment, the respective tip portions have an average width of greater than or equal to about 250 Å.  
         [0009]     The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:  
         [0011]     FIGS.  1  to  3  schematically illustrate a preferred embodiment of the present invention;  
         [0012]      FIGS. 4 and 5  schematically illustrate further processing of the structure of  FIG. 3  in forming a flash memory. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0000]     Known to the Inventors—Not to be Considered Prior Art  
         [0013]     The following is known to the inventors and is not to be considered to be prior art for the purposes of this invention.  
         [0014]     The shape of the floating gate oxide is a key factor in the Forward Tunneling Voltage (FTV) and the trap-up rate of Flash memory. The inventors have discovered that achieving a tip-shape of the floating gate oxide improves the FTV of the Flash memory.  
         [0000]     Initial Structure— FIG. 1   
         [0015]     As shown in  FIG. 1 , a structure  10  is provided having an upper gate oxide layer  15  formed thereover.  
         [0016]     A polysilicon layer  11  is formed over gate oxide layer  15  to a thickness of preferably from about 900 to 1100 Å, more preferably from about 950 to 1050 Å and most preferably about 1000 Å.  
         [0017]     Structure  10  is preferably a silicon substrate or a germanium substrate, is more preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate.  
         [0018]     A thin silicon oxide layer  12  is then formed over polysilicon layer  11  to a thickness of preferably from about  26  to  34 A, more preferably from about  28  to  32 A and most preferably about  30 A.  
         [0019]     A nitride or silicon nitride (Si 3 N 4  or just SiN) layer  14  is formed over the thin oxide layer  12  to a thickness of preferably from about 720 to 880 Å, more preferably from about 760 to 840 Å and most preferably about 800 Å.  
         [0020]     SiN layer  14  is then patterned preferably using a dry etch process at the following parameters:  
         [0021]     temperature: preferably from about 15 to 25° C. and more preferably from about 17 to 23° C.;  
         [0022]     pressure: preferably from about 225 to 275 mTorr and more preferably from about 245 to 255 mTorr;  
         [0023]     RF power: preferably from about 1000 to 1400 W and more preferably from about 1080 to 1320 W;  
         [0024]     O 2  gas flow: preferably from about 4 to 6 sccm and more preferably from about 4.5 to 5.5 sccm;  
         [0025]     CF 4  gas flow: preferably from about 66 to 76 sccm and more preferably from about 68 to 74 sccm;  
         [0026]     Ar gas flow: preferably from about 750 to 950 sccm and more preferably from about 800 to 900 sccm; and  
         [0027]     time: preferably from about 45 to 55 seconds and more preferably from about 48 to 52 seconds.  
         [0028]     Patterned SiN layer  14  includes an opening  16  exposing a portion  17  of thin oxide layer  12 . Opening  16  has a width  18  corresponding to the critical dimension of the patterning process, preferably from about 0.34 to 0.40 μm and more preferably from about 0.36 to 0.38 μm.  
         [0000]     Formation of Undercut  20  in Thin Oxide Layer  12  Under Patterned SiN Layer  14 — FIG. 2   
         [0029]     As shown in  FIG. 2 , thin oxide layer  12  is etched to remove the exposed portion  17  of thin oxide layer  12  and to remove a portion of the thin oxide layer  12  adjacent opening  16  under patterned SiN layer  14 , forming undercuts  20  and exposing a portion  24  of underlying polysilicon layer  11 . Undercuts  20  extend preferably from about 30 to 70 Å under patterned SiN layer  14 , more preferably from about 40 to 60 Å and most preferably about 50 Å.  
         [0030]     Thin oxide layer  12  is preferably etched to form undercuts  20  using an oxide wet bench dip.  
         [0031]     The oxide wet bench is conducted at the following parameters:  
         [0032]     HF: H 2 O ratio: preferably from about 90:1 to 110:1, more preferably from about 95:1 to 105:1 and most preferably about 100:1;  
         [0033]     temperature: preferably from about 18.5 to 28.5° C. and more preferably from about 20.5 to 26.5° C.;  
         [0034]     pressure: preferably from about 740 to 780 mTorr and more preferably from about 750 to 770 mTorr; and  
         [0035]     time: preferably from about 80 to 100 seconds and more preferably from about 85 to 95 seconds.  
         [0000]     Oxidation of The Exposed Portion  24  of Polysilicon Layer  11 — FIG. 3   
         [0036]     As shown in  FIG. 3 , the exposed portion  24  of polysilicon layer  11  is oxidized to form floating gate oxide portion  30  having respective tip corners  32  that have a longer and sharper tip profile induced by undercuts  20  than found in conventional methods not having such undercuts  20  formed before the oxidation of polysilicon layer  11 . Floating gate oxide portion  30  is essentially indistinguishable from the adjacent etched thin oxide layer  12 ″ as shown in  FIG. 3 .  
         [0037]     Floating gate oxide portion  30  has a mid-thickness  34  of preferably from about 1000 to 2000 Å and more preferably from about 1400 to 1600 Å. Tip corners  32  each have an average width  35  of preferably from about 250 to 350 Å and more preferably from about 280 to 320 Å. Assuming a critical dimension of 0.37 μm, the ratio of tip width (2 times average width 35) (e.g., 500-700 Å) plus critical dimension to critical dimension is between about 1.13-1.19. Put another way, assuming tip width is defined as “TW” and critical dimension is defined as “CD”, then (2TW+CD)/CD is preferably between about 1.13-1.19. Those in the art will recognize that critical dimensions are dimensions of the smallest geometrical features (width of interconnect line, contacts, trenches, etc.) which can be formed during semiconductor device/circuit (e.g., FLASH memory device) manufacturing using given photolithography technology.  
         [0038]     As shown in  FIGS. 3-5 , the tips corners have top and bottom surfaces, and the top surfaces of tip corners  32  are substantially parallel to the horizontal plane defined by the top surface of the substrate  10  along their average width  35 .  
         [0039]     Further processing may then proceed in forming a flash memory  50  such as shown in  FIG. 4  through  FIG. 5  with, for example: the removal of nitride layer  14  and the remainder of etched thin oxide layer  12 ″; the patterning and removal of polysilicon layer  11  not under floating gate oxide portion  30  to form remaining polysilicon layer  11 ′; the formation of an interpoly oxide layer  38  over the structure and the formation of control gate  40 .  
         [0040]     The inventors have determined that the flash forward tunneling voltage (FTV) performance of flash memory is improved from about 8.0 to 7.0 and more preferably from about 7.6 to 7.4 when the method of the present invention is used to form the floating gate oxide layer  30  employed in the flash memory. Similarly, the FTV is decreased preferably from about 7.0 to 6.0 and more preferably from about 6.6 to 6.4 in such a flash memory.  
         [0041]     While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.