Abstract:
Disclosed herein is a method of manufacturing a semiconductor device. The method comprises forming a first silicon film on a semiconductor substrate, forming a second silicon film on the first silicon film, forming a third silicon film on the second silicon film, and forming a first diffusion barrier film on the third silicon film. The method further comprises performing a thermal treatment to diffuse an impurity included in the second silicon film into at least the first silicon film and the semiconductor substrate, respectively.

Description:
[0001]    This application is based upon and claims the benefit of priority from Japanese patent application No. 2011-118976, filed on May 27, 2011, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a method of manufacturing a semiconductor device. 
         [0004]    2. Description of Related Art 
         [0005]    An increase of the density of a metal oxide semiconductor field effect transistor (MOSFET) is making it difficult to arrange a gate, a source, and a drain as components of a MOSFET on a plane. A three-dimensional layout has been required in a dynamic random access memory (DRAM) having a minimum wiring pitch of 90 nm or less. Such a three-dimensional layout refers to a structure in which a source and a drain (S/D) are formed at an upper end and a lower end of a pillar of a semiconductor extending in a direction perpendicular to a principal plane of a semiconductor substrate (in a normal direction to a principal plane of a semiconductor substrate), a gate insulator film and a gate electrode (word line) are arranged on a surface of an intermediate portion of the pillar, and those components are stacked on the principal plane of the semiconductor substrate. In the following description, a transistor having such a structure is referred to as a vertical transistor. A pillar of a semiconductor as described above is referred to as a semiconductor pillar. In a case where a semiconductor is silicon, a pillar of a semiconductor is referred to as a silicon pillar. An example of a vertical transistor is disclosed in JP-A 2008-311641 (Patent Document 1). 
       SUMMARY 
       [0006]      FIG. 1  is a perspective view schematically showing vertical transistors forming memory cells of a DRAM. The X-direction, Y-direction, and Z-direction are indicated in the drawings as needed to provide an explanation using three directions of the X-direction, Y-direction, and Z-direction in the following description. Trenches  143   a ,  143   b ,  143   c , and  143   d  are formed in a semiconductor substrate  100  of silicon (hereinafter referred to as a silicon substrate  100 ). Those trenches  143   a ,  143   b ,  143   c , and  143   d  extend along the Y-direction. In the following description, those four trenches may collectively be referred to as trenches  143 . Silicon pillars  101   a ,  101   b ,  102   a , and  102   b  are formed in an area between the trenches  143   a  and  143   b  and in an area between the trenches  143   b  and  143   c . Those silicon pillars  101   a ,  101   b ,  102   a , and  102   b  extend along the Z-direction, which is a normal direction to a surface of the silicon substrate  100  (protrude vertical to a surface of the silicon substrate), and serve as channels of transistors. Similarly, a silicon pillar  101   c  is located between the trench  143   c  and another trench (not shown). In the following description, the silicon pillars  101   a ,  101   b , and  101   c  may collectively be referred to as silicon pillars  101 , and the silicon pillar  102   a  and  102   b  may collectively be referred to as silicon pillars  102 . A pair of buried gate electrodes  108   a  and  108   b  are formed on both sides of the silicon pillar  101   a  so as to extend along the X-direction. A pair of buried gate electrodes  108   c  and  108   d  are formed on both sides of the adjacent silicon pillar  102   a  so as to extend along the X-direction. In the following description, those four gate electrodes may collectively be referred to as gate electrodes  108 . The gate electrodes  108  serve as word lines. 
         [0007]    Diffusion layers  146   a ,  146   b ,  146   c ,  146   d ,  146   e ,  146   f , and  146   g  are formed within the silicon pillars. In the following description, the six diffusion layers except the dummy diffusion layer  146   a  may collectively be referred to as diffusion layers  146 . The diffusion layers  146  serve as bit lines. The trenches  143   a ,  143   b ,  143   c , and  143   d  are filled with insulator films  144   a ,  144   b ,  144   c , and  144   d , respectively, for insulating the diffusion layers  146   a  to  146   g  opposed on both sides of each of the trenches. In the following description, the four insulator films may collectively be referred to as insulator films  144 . Particularly, the insulator film  144   d , which is filled in the trench  143   d  surrounding the silicon pillars, forms a shallow trench isolation (STI)  145  to terminate ends of the trenches  143   a ,  143   b , and  143   c  and isolate the trenches  143   a ,  143   b , and  143   c  from each other. 
         [0008]    In a plan view, the diffusion layers  146 , which serve as bit lines, extend in a direction (Y-direction) perpendicular to a direction (X-direction) in which the word lines extend. The diffusion layers  146  provided in the silicon substrate  100  serve as one of a source and a drain (S/D) of a transistor. Diffusion layers (not shown) serving as another one of a source and a drain (S/D) of the transistor are formed at an upper portion of each of the silicon pillars  101  and  102 . Capacitors  113  are provided on each of the silicon pillars  101  and  102 . With regard to the silicon pillar  101   a , one vertical transistor is formed by the diffusion layers  146   b  and  146   c , which are formed within the silicon pillar  101   a  so as to serve as one of a source and a drain (S/D) of the transistor, a pair of gate electrodes  108   a  and  108   b  provided on both sides of the silicon pillar  101   a , and the diffusion layers formed at an upper portion of the silicon pillar  101   a  so as to serve as another one of a source and a drain (S/D) of the transistor. 
         [0009]    With such a vertical transistor, an area required for a unit memory cell can be reduced. Therefore, the density of a MOSFET can be increased. Since a vertical transistor has a layered structure in which a bit line is located below a gate electrode, the diffusion layers to be bit lines are formed within a semiconductor pillar near the bottom of the semiconductor pillar. Furthermore, an opening area of a trench to be filled with an insulator film should be reduced in order to reduce an area required for a MOSFET. Therefore, an aspect ratio (depth/opening area) of a trench tends to increase. Accordingly, an ion implantation method from above a trench cannot be used to form diffusion layers to be bit lines. This is because a silicon pillar in which diffusion layers are to be formed is located right below a silicon pillar to be a channel. With an ion implantation method, unnecessary ions would be implanted into the silicon pillar to be a channel because of variations in shape of trenches. Those unnecessary ions implanted induce subsequent malfunction of the transistor, thereby inhibiting use of an ion implantation method. 
         [0010]    The present invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part. 
         [0011]    In one embodiment, there is provided a first method of manufacturing a semiconductor device. The first method comprises forming a first silicon film over a semiconductor substrate, forming a second silicon film on the first silicon film, forming a third silicon film on the second silicon film, forming a first diffusion barrier film on the third silicon film, and performing a thermal treatment to diffuse an impurity included in the second silicon film into at least the first silicon film and the semiconductor substrate, respectively. 
         [0012]    In another embodiment, there is provided a second method of manufacturing a semiconductor device. The second method comprises forming a plurality of semiconductor pillars protruding vertical to a surface of a semiconductor substrate, forming an insulator film that covers side surfaces of grooves sandwiched between the plurality of semiconductor pillars, forming a first silicon film that covers inner surfaces of the grooves, forming, on the first silicon film, a second silicon film including an impurity that is diffused to the semiconductor substrate, forming a third silicon film on the second silicon film, forming, on the third silicon film, a first diffusion barrier film for preventing outer diffusion of the impurity, and forming diffusion layers by thermally diffusing the impurity from the second silicon film into the semiconductor pillars at regions of bottoms of the grooves. 
         [0013]    In still another embodiment, there is provided a third method of manufacturing a semiconductor device. The third method comprises forming first and second semiconductor fences protruding to a surface of a semiconductor substrate, forming an insulator film that covers a side surface of a groove sandwiched between the first and second semiconductor fences, forming a first silicon film that covers an inner surface of the groove, forming a second silicon film including an impurity on the first silicon film, forming a third silicon film on the second silicon film, forming, on the third silicon film, a first diffusion barrier film for preventing outer diffusion of the impurity, and forming a diffusion layer by thermally diffusing the impurity from the second silicon film into the first and second semiconductor fences at a bottom part of the groove. 
         [0014]    The third method may further comprises removing the first diffusion barrier film, the third silicon film, the second silicon film and the first silicon film, etching the diffusion layer at the bottom part of the groove so that the diffusion layer in the first and second semiconductor fences are left thereafter, etching the semiconductor substrate at the bottom of the groove, forming an insulator to fill the groove, and forming a plurality of semiconductor pillars by dividing the first and second semiconductor fences, wherein the first and second semiconductor fences are divided by etching using a line pattern mask crossing the first and second semiconductor fences. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings. 
           [0016]      FIG. 1  is a perspective view schematically showing an example of a plurality of vertical transistors, which form memory cells of a DRAM to which the present invention is applicable. 
           [0017]      FIG. 2  is a plan view of an arrangement of the vertical transistors as seen from above the vertical transistors in  FIG. 1 . 
           [0018]      FIG. 3  is a plan view showing an initial stage of a production process until buried bit lines are formed in a method of manufacturing a semiconductor device according to a first embodiment of the present invention. 
           [0019]      FIG. 4  is a cross-sectional view taken along line A-A of  FIG. 3 . 
           [0020]      FIG. 5  is a cross-sectional view showing a production step subsequent to  FIG. 4  in the method of manufacturing a semiconductor device according to the first embodiment of the present invention. 
           [0021]      FIG. 6  is a cross-sectional view showing a production step subsequent to  FIG. 5 . 
           [0022]      FIG. 7  is a cross-sectional view showing a production step subsequent to  FIG. 6 . 
           [0023]      FIG. 8  is a cross-sectional view showing a production step subsequent to  FIG. 7 . 
           [0024]      FIG. 9  is a cross-sectional view showing a production step subsequent to  FIG. 8 . 
           [0025]      FIG. 10  is a cross-sectional view showing a production step performed instead of the production step shown in  FIG. 9 . 
           [0026]      FIG. 11  is a cross-sectional view showing a production step subsequent to  FIG. 9 . 
           [0027]      FIG. 12  is a cross-sectional view showing a production step subsequent to  FIG. 10 . 
           [0028]      FIG. 13  is a cross-sectional view showing a production step subsequent to  FIG. 11 . 
           [0029]      FIG. 14  is a cross-sectional view showing a production step subsequent to  FIG. 12 . 
           [0030]      FIG. 15  is a cross-sectional view showing a production step subsequent to  FIG. 13 . 
           [0031]      FIG. 16  is a cross-sectional view showing a production step subsequent to  FIG. 14 . 
           [0032]      FIG. 17  is a cross-sectional view showing a production step subsequent to  FIG. 15  or  16 . 
           [0033]      FIG. 18  is a cross-sectional view showing a production step subsequent to  FIG. 17 . 
           [0034]      FIG. 19  is a cross-sectional view showing a production step subsequent to  FIG. 18 . 
           [0035]      FIG. 20  is a plan view of  FIG. 19 . 
           [0036]      FIG. 21  is a plan view showing an initial stage of a production process until buried word lines are formed in the method of manufacturing a semiconductor device according to the first embodiment of the present invention. 
           [0037]      FIG. 22A  is a cross-sectional view taken along line A-A of  FIG. 21 , which shows a production step subsequent to  FIG. 21 . 
           [0038]      FIG. 22B  is a cross-sectional view taken along line B-B of  FIG. 21 , which shows the production step of  FIG. 22A  from another angle. 
           [0039]      FIG. 23A  is a cross-sectional view showing a production step subsequent to  FIG. 22A . 
           [0040]      FIG. 23B  is a cross-sectional view showing the production step of  FIG. 23A  from another angle as with  FIG. 22B . 
           [0041]      FIG. 24A  is a cross-sectional view showing a production step subsequent to  FIG. 23A . 
           [0042]      FIG. 24B  is a cross-sectional view showing the production step of  FIG. 24A  from another angle as with  FIG. 23B . 
           [0043]      FIG. 25A  is a cross-sectional view showing a production step subsequent to  FIG. 24A . 
           [0044]      FIG. 25B  is a cross-sectional view showing the production step of  FIG. 25A  from another angle as with  FIG. 24B . 
           [0045]      FIG. 26A  is a cross-sectional view showing a production step subsequent to  FIG. 25A . 
           [0046]      FIG. 26B  is a cross-sectional view showing the production step of  FIG. 26A  from another angle as with  FIG. 25B . 
           [0047]      FIG. 27A  is a cross-sectional view showing a production step subsequent to  FIG. 26A . 
           [0048]      FIG. 27B  is a cross-sectional view showing the production step of  FIG. 27A  from another angle as with  FIG. 26B . 
           [0049]      FIG. 28A  is a cross-sectional view showing a production step subsequent to  FIG. 27A . 
           [0050]      FIG. 28B  is a cross-sectional view showing the production step of  FIG. 28A  from another angle as with  FIG. 27B . 
           [0051]      FIG. 29A  is a cross-sectional view showing a production step subsequent to  FIG. 28A . 
           [0052]      FIG. 29B  is a cross-sectional view showing the production step of  FIG. 29A  from another angle as with  FIG. 28B . 
           [0053]      FIG. 30  is a plan view of  FIG. 29A  or  29 B. 
           [0054]      FIG. 31  is a perspective view explanatory of a summary of another example of a plurality of vertical transistors, which form memory cells of a DRAM to which the present invention is applicable. 
           [0055]      FIG. 32  is a plan view of an arrangement of the vertical transistors as seen from above the vertical transistors in  FIG. 31 . 
           [0056]      FIG. 33  is a plan view showing an initial stage of a production process until buried bit lines are formed in a method of manufacturing a semiconductor device according to a second embodiment of the present invention. 
           [0057]      FIG. 34  is a cross-sectional view taken along line A-A of  FIG. 33 . 
           [0058]      FIG. 35  is a cross-sectional view showing a production step subsequent to  FIG. 34 . 
           [0059]      FIG. 36  is a cross-sectional view showing a production step subsequent to  FIG. 35 . 
           [0060]      FIG. 37  is a cross-sectional view showing a production step subsequent to  FIG. 36 . 
           [0061]      FIG. 38  is a cross-sectional view showing a production step subsequent to  FIG. 37 . 
           [0062]      FIG. 39  is a cross-sectional view showing a production step subsequent to  FIG. 38 . 
           [0063]      FIG. 40  is a cross-sectional view showing a production step subsequent to  FIG. 39 . 
           [0064]      FIG. 41  is a cross-sectional view showing a production step subsequent to  FIG. 40 . 
           [0065]      FIG. 42  is a cross-sectional view showing a production step subsequent to  FIG. 41 . 
           [0066]      FIG. 43  is a cross-sectional view showing a production step subsequent to  FIG. 42 . 
           [0067]      FIG. 44  is a cross-sectional view showing a production step subsequent to  FIG. 43 . 
           [0068]      FIG. 45  is a cross-sectional view showing a production step subsequent to  FIG. 44 . 
           [0069]      FIG. 46  is a cross-sectional view showing a production step subsequent to  FIG. 45 . 
           [0070]      FIG. 47  is a cross-sectional view showing a production step subsequent to  FIG. 46 . 
           [0071]      FIG. 48  is a cross-sectional view showing a production step subsequent to  FIG. 47 . 
           [0072]      FIG. 49  is a cross-sectional view showing a production step subsequent to  FIG. 48 . 
           [0073]      FIG. 50  is a cross-sectional view showing a production step subsequent to  FIG. 49 . 
           [0074]      FIG. 51  is a cross-sectional view showing a production step subsequent to  FIG. 50 . 
           [0075]      FIG. 52  is a cross-sectional view showing a production step subsequent to  FIG. 51 . 
           [0076]      FIG. 53  is a cross-sectional view showing a production step subsequent to  FIG. 52 . 
           [0077]      FIG. 54  is a cross-sectional view showing a production step subsequent to  FIG. 53 . 
           [0078]      FIG. 55  is a cross-sectional view showing a production step subsequent to  FIG. 54 . 
           [0079]      FIG. 56  is a cross-sectional view showing a production step subsequent to  FIG. 55 . 
           [0080]      FIG. 57  is a cross-sectional view showing a production step subsequent to  FIG. 56 . 
           [0081]      FIG. 58  is a cross-sectional view showing a production step subsequent to  FIG. 57 . 
           [0082]      FIG. 59  is a cross-sectional view showing a production step subsequent to  FIG. 58 . 
           [0083]      FIG. 60  is a cross-sectional view showing a production step subsequent to  FIG. 59 . 
           [0084]      FIG. 61  is a cross-sectional view showing a production step subsequent to  FIG. 60 . 
           [0085]      FIG. 62  is a cross-sectional view showing a production step subsequent to  FIG. 61 . 
           [0086]      FIG. 63  is a cross-sectional view showing a production step subsequent to  FIG. 62 . 
           [0087]      FIG. 64  is a cross-sectional view showing a production step subsequent to  FIG. 63 . 
           [0088]      FIG. 65  is a cross-sectional view showing a production step subsequent to  FIG. 64 . 
           [0089]      FIG. 66  is a cross-sectional view showing a production step subsequent to  FIG. 65 . 
           [0090]      FIG. 67  is a plan view showing a portion including a portion illustrated in  FIG. 66 . 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0091]    The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
         [0092]    A method of manufacturing buried bit lines and buried word lines of a semiconductor device according to a first embodiment of the present invention will be described below with reference to  FIGS. 3 to 30  in addition to  FIGS. 1 and 2 .  FIGS. 3 to 20  show a method of manufacturing buried bit lines of a semiconductor device according to a first embodiment of the present invention, and  FIGS. 21 to 30  show a method of manufacturing buried word lines of a semiconductor device according to a first embodiment of the present invention. 
         [0093]    First of all, a semiconductor device to which the present invention is applied will be summarized along with an example of a DRAM using  FIGS. 1 and 2 . 
         [0094]    Referring to  FIG. 1 , as described above, capacitors  113  are formed on silicon pillars  101   a ,  101   b ,  101   c ,  102   a , and  102   b , which have been formed by digging a silicon substrate  100 . In the following description, the silicon pillars  101   a ,  101   b , and  101   c  may collectively be referred to as silicon pillars  101 , and the silicon pillar  102   a  and  102   b  may collectively be referred to as silicon pillars  102 . Word lines  108   a ,  108   b ,  108   c , and  108   d  form gate electrodes of vertical transistors. The word lines  108   a  and  108   b  are formed so as to interpose the silicon pillars  101  therebetween, whereas the word lines  108   c  and  108   d  are formed so as to interpose the silicon pillars  102  therebetween. In the following description, the word lines  108   a ,  108   b ,  108   c , and  108   d  may collectively be referred to as word lines  108 . Diffusion layers  146   b ,  146   c ,  146   d ,  146   e ,  146   f , and  146   g  to be bit lines, which may collectively be referred to as diffusion layers  146  in the following description, are located at a height different from the height of the word lines  108 . The diffusion layers  146  extend in a direction perpendicular to a direction in which the word lines  108  extend. The diffusion layers  146  are formed within the corresponding silicon pillars  101  and  102 . Specifically, each of the word lines  108  extends along the X-direction (or in the X-direction) at a position higher than the height of the diffusion layers  146 . Each of the diffusion layers  146  is formed on a side surface of the corresponding silicon pillar. Each of the diffusion layers  146  extends along the Y-direction, which is perpendicular to the X-direction. A transistor constituting a unit cell is formed by two bit lines and two word lines. 
         [0095]    For example, the silicon pillar  101   a  includes the diffusion layers  146   b  and  146   c  to be bit lines and a pair of word lines  108   a  and  108   b  connected at ends of a cell region. Similarly, the silicon pillar  102   a  includes the diffusion layers  146   b  and  146   c  and a pair of word lines  108   c  and  108   d . Other pillars of the silicon pillars  101  and  102  are formed in the same manner. The word lines  108   b  and  108   c  are insulated from each other by an insulator film. Thus, a double gate structure having two word lines connected to one silicon pillar is provided. Meanwhile, the diffusion layers to be bit lines are formed on two opposed side surfaces of the silicon pillar. Therefore, the bit lines  146  formed on the silicon pillars are insulated from each other by the insulator films  143  filled between adjacent silicon pillars. 
         [0096]    Incidentally, a plurality of silicon pillars can be formed with the following manner. A plurality of silicon fences protruding to a surface of a silicon substrate are formed. A plurality of silicon pillars are formed by dividing each of the silicon fences. For example, each the silicon fences can be divided by etching using a line pattern mask crossing the silicon fences. 
         [0097]    Next, referring to  FIG. 2 , a memory cell to which the present invention is applied has silicon pillars  101   a ,  101   b , and  101   c  (collectively referred to as silicon pillars  101  in the following description), silicon pillars  102   a ,  102   b , and  102   c  (collectively referred to as silicon pillars  102  in the following description), and silicon pillars  103   a ,  103   b , and  103   c  (collectively referred to as silicon pillars  103  in the following description). Those silicon pillars are methodically arranged in the X-direction and the Y-direction, which is perpendicular to the X-direction. For convenience&#39; sake,  FIG. 2  illustrates nine silicon pillars. However, the present invention is not limited to the illustrated example. In practice, several thousands to several hundreds of thousands of silicon pillars are arranged. Therefore, the number of bit lines and word lines is on the order of several hundreds to several thousands. In each of the silicon pillars  101 ,  102 , and  103  arranged along the X-direction, diffusion layers  146   b ,  146   c ,  146   d ,  146   e ,  146   f , and  146   g  to be bit lines are formed so as to extend along the Y-direction. Each of the diffusion layers  146  is shared with a plurality of silicon pillars arranged along the Y-direction. For example, the diffusion layer  146   b  is shared with the silicon pillars  101   a ,  102   a , and  103   a . In  FIG. 2 , part of word lines is illustrated as being cut out in order to show the reference numerals. However, those word lines are not cut out in practice. 
         [0098]    Now a method of producing buried bit lines in the semiconductor device illustrated in  FIGS. 1 and 2  will be described with reference to  FIGS. 3 to 20 .  FIG. 3  is a plan view,  FIGS. 4 to 19  are cross-sectional views taken along line A-A of  FIG. 3 , and  FIG. 20  is a plan view of  FIG. 19 . 
         [0099]    As shown in  FIG. 4 , a mask film  104  of a silicon nitride film is deposited with a thickness of about 40 nm on a silicon substrate (semiconductor substrate)  100  by a low-pressure chemical vapor deposition (CVD) method. Then bit line openings  105   c  extending along the Y-direction are formed in the mask film  104  by photolithography and dry etching. The silicon substrate  100  is exposed at bottoms of the bit line openings  105   c . In the present embodiment, the bit line openings  105   c  have a width W 1  of 45 nm. 
         [0100]    Thereafter, as shown in  FIG. 5 , the silicon substrate  100  is subjected to anisotropic dry etching while the mask film  104  is used as a mask. Thus, new trenches  106  are formed in the silicon substrate  100 . The trenches  106  have a depth H 1  of 200 nm from the surface of the silicon substrate  100 . Those trenches  106  are used to form silicon pillars (semiconductor pillars)  100   b.    
         [0101]    Subsequently, a silicon oxide film is formed with a film thickness of 2.5 nm by a radical oxidation method so that inner sidewalls of the trenches  106  are covered with the silicon oxide film, and a silicon nitride film is stacked with a film thickness of 5 nm on the silicon oxide film by a thermal CVD method. Then an etchback is performed so as to form an insulator film  147  on the inner sidewalls of the trenches  106  as shown in  FIG. 6 . At that time, new trenches  148  are formed. 
         [0102]    Next, as shown in  FIG. 7 , a coating film  149 , which is to be a first silicon film, is deposited with a thickness of 5 nm by a CVD method so that inner walls of the trenches  148  are covered with the coating film  149 . For example, the following deposition conditions may be used. Monosilane (SiH 4 ) is used as a material gas. A flow rate of the gas is 1,500 sccm (standard cubic centimeter per minute), and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. At that time, new trenches  150  are formed. 
         [0103]    Then, as shown in  FIG. 8 , an impurity layer  151 , which is to be a second silicon film, is formed on the coating film  149  by adsorbing impurities of arsenic (As) on the exposed coating film  149  so that the concentration of the impurities is 1.0×10 15  atoms/cm 3 . For example, the following adsorption conditions may be used. Arsine (AsH 3 ) is used as a material gas. A flow rate of the gas is 400 sccm, and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. Within this temperature range, arsine is decomposed to produce arsenic. Thus, arsenic can readily be adsorbed on the coating film  149 . At that time, the trenches  150  remain. 
         [0104]    Thereafter, as shown in  FIG. 9 , a coating film  152 , which is to be a third silicon film, is deposited with a thickness of 8 nm on the impurity layer  151  by a CVD method so that inner walls of the trenches  150  are covered with the coating film  152 . For example, the following deposition conditions may be used. Monosilane (SiH 4 ) is used as a material gas. A flow rate of the gas is 1,500 sccm, and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. At that time, new trenches  153  are formed. As shown in  FIG. 10 , instead of  FIG. 9  showing a production step of the coating film  152 , a coating film  152 A (third silicon film) may be deposited on the impurity layer  151  with a thickness T 1  of 30 nm from a surface of the impurity layer  151 , so that the trenches  150  are filled with the coating film  152 A. 
         [0105]    Each of the first, second, and third silicon films may be deposited in either an amorphous state or a polycrystalline state. This holds true for a fourth silicon film and a fifth silicon film, which will be described later. Furthermore, each of the first and second silicon films may be formed by a selective epitaxial growth technique. This holds true for a second embodiment, which will be described later. 
         [0106]    Next, as shown in  FIG. 11  subsequent to  FIG. 9 , an insulator film  154  of a silicon oxide film, which is to be a first diffusion barrier film, is deposited with a thickness T 2  of 3 nm on the coating film  152  by a thermal oxidation method, so that the trenches  153  are filled with the insulator film  154 . For example, the following deposition conditions may be used. Oxygen (O 2 ) is used as a material gas. A flow rate of the gas is 3 SLM (standard liter per minute), and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. Furthermore, the film thickness of the insulator film  154  is not limited to 3 nm and may be in a range of 2 nm to 3 nm. Then a coating film  155 , which is to be a fourth silicon film, is deposited with a thickness of 35 nm on the insulator film  154  by a CVD method. For example, the following deposition conditions may be used. Monosilane (SiH 4 ) is used as a material gas. A flow rate of the gas is 1,500 sccm, and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. 
         [0107]    Then an insulator film  154   a  of a silicon oxide film, which is to be a second diffusion barrier film, is deposited with a thickness of 3 nm on the coating film  155  by a thermal oxidation method. In  FIG. 11 , the reference numerals  154  and  154   a  do not indicate any space or room but indicate insulator films. For example, the same deposition conditions as for the insulator film  154  may be used. Furthermore, a coating film  155   a , which is to be a fifth silicon film, is deposited with a thickness of 35 nm on the insulator film  154   a  by a CVD method. For example, the same deposition conditions as for the coating film  155  may be used. In a case where an insulator film is deposited on the coating film  152 A shown in  FIG. 10 , the insulator film  154 A becomes flat as shown in  FIG. 12  and covers the coating film  152 A. For example, the deposition conditions for the coating film  155 , the insulator film  154   a , and the coating film  155   a  may be the same as those described in connection with  FIG. 11 . 
         [0108]    Thereafter, as shown in  FIG. 13  subsequent to  FIG. 11 , the impurities in the impurity layer  151  ( FIG. 11 ) are thermally diffused into the coating film  149  ( FIG. 11 ) and the coating film  152  ( FIG. 11 ) by a lamp annealing method. At that time, annealing may be conducted under a nitrogen (N 2 ) atmosphere at a heating temperature of 1,000° C. The heating temperature is not limited to 1,000° C. and may be in a range of 800° C. to 1,200° C. As a result of this annealing process, the impurities in the impurity layer  151  are present in the coating films  149  and  152  with a uniform concentration gradient. Those films are incorporated into a doped layer  156 . However, since the coating films  149  and  152  have different film thicknesses, they have different impurity concentrations on surfaces opposite to surfaces facing the impurity layer  151  due to a difference of diffusion lengths. More specifically, the arsenic concentration at a contacting surface with the silicon pillars  100   b  is 2.0×10 19  atoms/cm 3 , whereas the arsenic concentration at a contacting surface with the insulator film  154  is 2.4×10 18  atoms/cm 3 . 
         [0109]    When the impurity layer  151  shown in  FIG. 12  is thermally diffused in the same manner by a lamp annealing method, a doped layer  156 A is formed as shown in  FIG. 14  so that the impurities in the impurity layer  151  ( FIG. 12 ) are present in the doped layer  156 A with a uniform concentration gradient. Since the coating film  152 A ( FIG. 12 ) is thicker than the coating film  149  ( FIG. 12 ) in this example, the arsenic concentration at a contacting surface with the insulator film  154 A becomes 5.2×10 17  atoms/cm 3  and is lower than that in  FIG. 13 . 
         [0110]    Subsequently, as shown in  FIG. 15  subsequent to  FIG. 13 , impurities are diffused from the doped layer  156  to the silicon substrate  100  at the bottoms of the trenches by a thermal treatment of 650° C. Thus, diffusion layers  157  are formed at regions corresponding to the bottoms of the trenches. Those impurities are diffused to the silicon substrate  100  not only in the Z-direction, but also in the X-direction. Therefore, part of the diffusion layers  157  is formed on side surfaces of the silicon pillars  100   b . By a production step using the same thermal treatment as described in connection with  FIG. 15 , impurities are diffused from the doped layer  156 A shown in  FIG. 14  so that a similar diffusion layer  157  is formed at regions corresponding to the bottoms of the trenches as shown in  FIG. 16 . 
         [0111]    Next, as shown in  FIG. 17 , the coating film  155  (including  155   a ), the insulator film  154  (including  154   a ), and the doped layer  156  shown in  FIG. 15  are removed by anisotropic dry etching. Thus, new trenches  158  are formed. Part of the diffusion layer  157  is exposed at the bottom of each of the trenches  158 . When the coating film  155  (including  155   a ), the insulator film  154 A (including  154   a ), and the doped layer  156 A are removed from the structure shown in  FIG. 16 , the structure illustrated in  FIG. 17  is produced. 
         [0112]    Then, as shown in  FIG. 18 , the silicon substrate  100  is subjected to anisotropic dry etching while the mask film  104  is used as a mask. Thus, new trenches  159  including trenches  159   a  having a depth H 2  of 50 nm from the bottoms of the trenches  158  are formed. Those trenches  159   a  divide the diffusion layers  157  into two parts in the X-direction. Accordingly, new diffusion layers  157   a ,  157   b ,  157   c , and  157   d  are formed within the silicon pillars  100   b.    
         [0113]    Thereafter, as shown in  FIG. 19 , an insulator film  127  of a silicon nitride film is formed with a thickness of 5 nm on the entire surface including inner surfaces of the trenches  159  by a CVD method. Furthermore, the trenches  159  are filled with a silicon oxide film by a spin coating method, and an etchback is performed. Thus, an insulator film  128  of a silicon oxide film is formed with a thickness of 120 nm. Therefore, the trenches  159  still remain in a shallowed state above the insulator film  128 . Then an insulator film  129  of a silicon oxide film is formed by a CVD method so that the shallowed trenches  159  are filled with the insulator film  129 .  FIG. 20  shows a plan view at that time. As with  FIG. 3 , a plurality of lines of the insulator film  129  filled in the trenches  158  ( FIG. 17 ) extend along the Y-direction in parallel to each other. 
         [0114]    By the aforementioned production steps, the diffusion layers  157   a ,  157   b ,  157   c , and  157   d  as buried bit lines are completed. 
         [0115]    Next, a method of producing buried word lines, which follows  FIG. 20 , will be described with reference to  FIGS. 21 to 30 .  FIGS. 21 and 30  are plan views,  FIGS. 22A to 29A  are cross-sectional views taken along line A-A of  FIG. 21 , and  FIGS. 22B to 29B  are cross-sectional views taken along line B-B of  FIG. 21 .  FIGS. 22A to 29A  illustrate the same portions as shown in the cross-sectional views for the aforementioned method of producing buried bit lines.  FIGS. 22A to 29A  are provided for clarifying a positional relationship between the word lines and the bit lines.  FIGS. 22B to 29B  show a positional relationship between word lines located adjacent to each other in a direction perpendicular to the bit lines. 
         [0116]    As shown in the plan view of  FIG. 21 , a word line opening  130   a  extending along the X-direction is formed in the mask film  104  and the silicon substrate  100 , which is to be silicon pillars  100   c  (semiconductor pillars  100   c ) ( FIGS. 22A and 22B ), by photolithography and dry etching. As shown in  FIGS. 22A and 22B , the silicon substrate  100  and the insulator film  128  are exposed at the bottoms of trenches  130  of the word line opening  130   a  ( FIG. 21 ). In the present embodiment, the trenches  130  have a width W 2  of 63 nm. 
         [0117]    Thereafter, as shown in  FIGS. 23A and 23B , an insulator film  131  of a silicon oxide film is formed with a thickness of 10 nm on the trenches  130  of the silicon substrate  100  by a thermal oxidation method. At that time, sidewall portions of the silicon pillars  100   c  (semiconductor pillars  100   c ) and an upper surface of the silicon substrate  100  (bottoms of the trenches  130 ) are covered with the insulator film  131 , which is to be a gate insulator film. 
         [0118]    Subsequently, as shown in  FIGS. 24A and 24B , a barrier film  132  of a titanium nitride is formed with a thickness of 4 nm on the entire surface including inner surfaces of the trenches  130  by a CVD method. Furthermore, a conductive film  133  of tungsten is formed by a CVD method so that the trenches  130  are filled with the conductive film  133 . Then the conductive film  133  present on the insulator film  129  is removed by a chemical mechanical polishing (CMP). At that time, as shown in  FIG. 24B , the silicon pillars  100   c  (semiconductor pillars  100   c ) are covered with the insulator film  131 , which is to be a gate insulator film, the barrier film  132 , and the conductive film  133 . 
         [0119]    Next, as shown in  FIGS. 25A and 25B , an etchback is performed on the conductive film  133  to produce conductive films  133   a  having a thickness of 50 nm. Thus, new trenches  134  are formed. Under the etchback conditions, the barrier film  132  is also removed at the same rate as the conductive film  133 . Therefore, as shown in  FIG. 25B , no barrier film  132  is left on side surfaces of the trenches  134 . Thus, the barrier film  132  remains at the bottoms of the trenches  134  as a barrier film  132   a  covering bottoms and sidewall portions of the conductive films  133   a.    
         [0120]    Then, as shown in  FIGS. 26A and 26B , an insulator film  135  of a silicon oxide film is deposited with a thickness of 18 nm by a CVD method so that inner walls of the trenches  134  are covered with the insulator film  135 . This insulator film  135  is deposited with a uniform thickness. Therefore, as shown in FIG.  26 B, new trenches  134   a  having a width W 3  of 27 nm are formed.  FIG. 26A  shows a cross-section of the insulator film  135  deposited on a sidewall portion of the trench  134   a . The insulator film  135  also covers an upper surface of the insulator film  129 . 
         [0121]    Thereafter, as shown in  FIGS. 27A and 27B , the insulator film  135  is divided at the trenches  134   a  by an etchback. Similarly, the conductive film  133   a  and the barrier film  132   a  are divided to produce conductive films  136   a ,  136   b ,  136   c , and  136   d  and barrier films  137   a ,  137   b ,  137   c , and  137   d . The conductive film  136   a  and the barrier film  137   a  form a word line  138   a  on the insulator film  131 , which is to be a gate insulator film. A word line  138   b , a word line  138   c , and a word line  138   d  are formed in the same manner. The word line  138   b  and the word line  138   c  jointly cover side surfaces of the silicon pillars  100   c  (semiconductor pillars  100   c ) and serve as double gates. Although word lines to be paired with the word lines  138   a  and  138   d  are not illustrated in the drawings, the word lines  138   a  and  138   d  also serve as double gates. New trenches  139  are formed by an etchback. In order to prevent adjacent word lines  138   a  to  138   d  from being short-circuited, the trenches  139  are formed such that their bottoms are located at a position lower than bottoms of the barrier films  137   a  to  137   d.    
         [0122]    Subsequently, as shown in  FIGS. 28A and 28B , the insulator film  135  of a silicon oxide film remaining in the trenches  139  is removed by wet etching. Thus, new trenches  140  are formed. At that time, the word lines  138  of tungsten and titanium nitride, the mask film  104  of a silicon nitride film, and the insulator film  127  are not removed. 
         [0123]    Next, as shown in  FIGS. 29A and 29B , an insulator film  141  of a silicon nitride film is deposited with a thickness of 8 nm by a CVD method so that inner walls of the trenches  140  are covered with the insulator film  141 . Furthermore, an insulator film  142  of a silicon oxide film is formed by a spin coating method so that the trenches  140  are filled with the insulator film  142 . Then the insulator film  142  on the insulator film  141  is removed and flattened by CMP.  FIG. 30  is a plan view of  FIG. 29A  or  29 B. As with  FIG. 21 , the trenches  140  in which the word lines  138  have been buried extend along the X-direction in parallel to each other. The trenches are not isolated at their right ends because an electrical control is collectively performed by incorporating the aforementioned two word lines having a double gate structure at their ends. As shown in  FIG. 29A , the bit lines  120   b  are insulated from the word lines  138  by the insulator films  128 . 
         [0124]    Then, the mask film  104  is removed. A semiconductor device, which corresponds to the DRAM shown in  FIG. 1 , is completed through a process of forming diffusion layers at upper portions of the silicon pillars, a process of forming capacitance contact plugs, a process of forming capacitors, a process of forming a wiring layer, and the like. 
         [0125]    Meanwhile, diffusion layers are usually formed in the following manner. Referring back to  FIG. 6 , the silicon pillars  100   b , which form side surfaces of the trenches  148 , are covered with the insulator film  147 . Then impurities are implanted in the silicon substrate  100  exposed at the bottoms of the trenches  148  by an ion implantation method. Thus, diffusion layers  157  as shown in  FIG. 15  are formed. At that time, if an angle of the ion implantation exceeds a control limit, impurities are also implanted in the insulator film  147 , which covers channel regions of transistors. As a result, as described in SUMMARY, part of the impurities going through the insulator film  147  reaches the channel regions in the silicon pillars  100   b , thereby causing malfunction of the transistors. 
         [0126]    In the aforementioned embodiment, however, the diffusion layers  157  ( FIG. 15 ) are formed by thermally diffusing impurities in the silicon substrate  100  exposed at the bottoms of the trenches  148  ( FIG. 6 ). At that time, the impurities thermally diffused in the silicon substrate  100  can readily be diffused to the silicon pillars  100   b . Therefore, the diffusion layers  157   a - 157   d  ( FIG. 18 ), which serve as one of a source and a drain (S/D), can readily be formed right below the channel regions. 
         [0127]    A production process of buried bit lines of a semiconductor device according to a second embodiment of the present invention will be described below with reference to  FIGS. 31 to 67 .  FIG. 31  is a perspective view schematically showing a semiconductor device to which the present invention is applied, and  FIG. 32  is a plan view of the semiconductor device.  FIGS. 33 to 67  show a production process of buried bit lines of a semiconductor device according to the present invention. 
         [0128]    A semiconductor device to which the present invention is applied will be summarized along with an example of a DRAM using  FIGS. 31 and 32 .  FIG. 31  is a perspective view showing part of a memory cell portion of a DRAM.  FIG. 32  is a plan view corresponding to  FIG. 31 . 
         [0129]    First, referring to  FIG. 31 , capacitors  113  are formed on silicon pillars  101   a ,  101   b ,  101   c ,  102   a , and  102   b , which have been formed by digging a semiconductor substrate  100  of silicon. Word lines  108   a ,  108   b ,  108   c , and  108   d  form gate electrodes of vertical transistors. The word lines  108   a ,  108   b ,  108   c , and  108   d  and the bit lines  105   a  and  105   b  are formed so as to surround the corresponding silicon pillars  101  and  102 . The word lines  108   a ,  108   b ,  108   c , and  108   d  and the bit lines  105   a  and  105   b  extend in perpendicular directions at different heights. Specifically, the word lines  108  extend along the X-direction at a location higher than the bit lines  105 , whereas the bit lines  105  extend along the Y-direction, which is perpendicular to the X-direction, at the deepest portions of the trenches. A transistor constituting a unit cell is formed by one bit line and two word lines. For example, the silicon pillar  101   a  includes a bit line  105   a  and a pair of word lines  108   a  and  108   b  connected at ends of a cell region. Similarly, the silicon pillar  102   a  includes a bit line  105   a  and a pair of word lines  108   c  and  108   d . Other pillars of the silicon pillars  101  and  102  are formed in the same manner. 
         [0130]    The word lines  108   b  and  108   c  are insulated from each other by an insulator film. Thus, a double gate structure having two word lines connected to one silicon pillar is provided. A bit line is connected only to one side of each silicon pillar. Therefore, the bit lines are disconnected from a silicon pillar opposite to the silicon pillar being connected by an insulator film (silicon oxide film) formed on a side surface of the silicon pillar. The insulator film is opened only on the side of the silicon pillar being connected. The bit lines are connected to diffusion layers formed within the silicon pillars. Accordingly, the bottoms of the bit lines are insulated from the silicon substrate by an insulator film. Thus, the semiconductor device of the second embodiment has the same basic configuration as in  FIG. 1 , which has been described in the description of SUMMARY. 
         [0131]    Referring to  FIG. 32 , in the memory cell according to the second embodiment, silicon pillars  101   a ,  101   b ,  101   c ,  102   a ,  102   b ,  102   c ,  103   a ,  103   b , and  103   c  are methodically arranged in the X-direction and the Y-direction, which is perpendicular to the X-direction. For convenience&#39; sake,  FIG. 32  illustrates nine silicon pillars. However, the present invention is not limited to the illustrated example. In practice, several thousands to several hundreds of thousands of silicon pillars are arranged. Therefore, the number of bit lines and word lines is on the order of several hundreds to several thousands. Bit lines  105   a  and  105   b  are formed so as to extend along the Y-direction between the silicon pillars  101  and between the silicon pillars  102 , which are arranged along the X-direction. Each of the bit lines  105  is shared with a plurality of silicon pillars arranged along the Y-direction. For example, the bit line  105   a  is shared with the silicon pillars  101   a ,  102   a , and  103   a.    
         [0132]    Now a method of producing buried bit lines in the semiconductor device illustrated in  FIGS. 31 and 32  will be described with reference to  FIGS. 33 to 67 .  FIGS. 33 and 67  are plan views, and  FIGS. 34 to 66  are cross-sectional views taken along line A-A of  FIG. 33 . 
         [0133]    As shown in  FIG. 34 , a mask film  104  of a silicon nitride film is deposited with a thickness of about 40 nm on a silicon substrate (semiconductor substrate)  100  by a low-pressure chemical vapor deposition (CVD) method. 
         [0134]    Then bit line openings  105   c  extending along the Y-direction are formed in the mask film  104  by photolithography and dry etching. As shown in the plan view of  FIG. 33 , an end of each of the bit line openings  105   c  is used as an area at which a contact is to be formed and is thus slightly widened. Nevertheless, such a configuration exerts no adverse influence on the formation of bit lines. The silicon substrate (semiconductor substrate)  100  is exposed at the bottoms of the bit line openings  105   c . In the second embodiment, the openings  105   c  have a width W 4  of 45 nm. 
         [0135]    Thereafter, as shown in  FIG. 35 , the silicon substrate (semiconductor substrate)  100  is subjected to anisotropic dry etching while the mask film  104  is used as a mask. Thus, trenches  106  are formed in the silicon substrate  100 . The trenches  106  have a depth H 3  of 250 nm from the surface of the silicon substrate  100 . Those trenches  106  are used to form a plurality of silicon pillars (semiconductor pillars)  100   b.    
         [0136]    Subsequently, as shown in  FIG. 36 , an insulator film  107  of a silicon oxide film is formed on inner walls of the trenches  106  and an upper surface of the mask film  104  by a radical oxidation method so that it has a film thickness T 3  of 10 nm at bottoms of the trenches  106 . 
         [0137]    Next, as shown in  FIG. 37 , a buried film  109  of a silicon film is formed by a low-pressure CVD method so that the trenches formed by adjacent silicon pillars (semiconductor pillars)  100   b  are filled with the buried film  109 . 
         [0138]    Then, as shown in  FIG. 38 , an etchback is performed with anisotropic dry etching that etches the buried film  109  and the insulator film  107  at the same rate, so that the height H 4  from the bottoms of the trenches  106  to upper surfaces of those films is 50 nm. As a result, insulator films  107   a  that cover the bottoms of the trenches  106  and buried films  109   a  that have been buried in the insulator films  107   a  are formed. Accordingly, new trenches  106   a  are formed above upper surfaces of the insulator films  107   a  and the buried films  109   a . At that time, the buried films  109   a  do not serve as bit lines. 
         [0139]    Thereafter, as shown in  FIG. 39 , an insulator film  110  of a silicon oxide film is formed with a film thickness T 4  of 3 nm on sidewalls (inner walls) of the trenches  106   a  by a thermal oxidation method. As a result, the remaining trenches  106   a  maintain an opening width W 5  of 39 nm. 
         [0140]    Subsequently, as shown in  FIG. 40 , the buried films  109   a  are selectively removed by wet etching with aqueous ammonia (NH 3 ). No silicon oxide film is etched by this wet etching process. Therefore, the insulator films  107   a  of a silicon oxide film remain in a state in which a film thickness T 3  of 10 nm is maintained at the bottoms of the insulator films  107   a . Furthermore, the insulator film  110  also remains in a state in which a film thickness T 5  of 3 nm is maintained. Now new trenches  106   b  are formed at the bottoms of the trenches  106   a  by removal of the buried films  109   a.    
         [0141]    Next, as shown in  FIG. 41 , a buried film  111  of a silicon film is formed on the entire surface of the substrate so that the trenches  106   a  and  106   b  are filled with the buried film  111 . 
         [0142]    Then, as shown in  FIG. 42 , an etchback is performed on the buried film  111  with anisotropic dry etching, so that portions of the insulator film  110  corresponding to the trenches  106   a  are exposed. Thus, new buried films  111   a  of the buried film  111  are formed so as to have an upper surface located at the same height as the upper surfaces of the insulator films  107   a . Furthermore, new trenches  112  are formed at that time. The trenches  112  maintain an opening width of 39 nm. 
         [0143]    Thereafter, as shown in  FIG. 43 , a silicon nitride film is formed with a thickness of 5 nm on the entire surface including inner surfaces of the trenches  112  by a CVD method. Subsequently, an etchback is performed with anisotropic dry etching so as to form sidewall insulator films  114  of a silicon nitride film. In  FIG. 43 , regions denoted by the reference numeral  114  do not refer to a space or room but insulator films. The sidewall insulator films  114  formed on the mask film  104  and the sidewall insulator films  114  formed on the buried films  111   a  are removed. The sidewall insulator films  114  serve to prevent the insulator films  110  from being etched during a subsequent wet etching process. At that time, the trenches  112  are formed into new trenches  112   a . The trenches  112   a  maintain an opening width W 6  of 29 nm. 
         [0144]    Next, as shown in  FIG. 44 , an etchback is performed on the buried films  111   a  having an exposed surface so as to dig the buried films  111   a  by 30 nm. Thus, the buried films  111   a , which have had a thickness of 40 nm in a vertical direction at the time of its formation in  FIG. 42 , are formed into buried films  111   b  having a thickness of 10 nm. Furthermore, new trenches  112   b  are formed in regions being dug. The trenches  112   b  constitute trenches  112   c  along with the trenches  112   a , which have been formed above the trenches  112   b.    
         [0145]    Then, as shown in  FIG. 45 , a titanium nitride film, which is to be an etching sacrificial layer, is formed with a thickness of 7 nm on the entire surface of the substrate by a CVD method. Thereafter, an etchback is performed with anisotropic dry etching so as to form sidewalls  115  on side surfaces of the trenches  112   c . Thus, the insulator films  107   a  exposed on side surfaces of the trenches  112   b  are covered with the sidewalls  115 . The sidewalls  115  are formed in a controlled state in which the titanium nitride film on the upper surfaces of the buried films  111   b  (portion indicated by the black circle in  FIG. 45 ) is removed while the upper surfaces of the sidewalls  115  are located at a height 23 nm below the upper surface of the mask film  104 . 
         [0146]    Subsequently, as shown in  FIG. 46 , an insulator film  116  of a silicon oxide film is formed so that spaces remaining in the trenches  112   c  ( FIG. 45 ) are filled with the insulator film  116 . The insulator film  116  may be formed by a CVD method, an atomic layer deposition (ALD) method, or a spin coating method. 
         [0147]    Next, as shown in  FIG. 47 , an etchback is performed on the insulator film  116  so as to form insulator films  116   a  covering the sidewalls  115  and form trenches  117  above the insulator films  116   a . The insulator films  116   a  are formed in a controlled state in which upper surfaces of the insulator films  116   a  are located at a height 15 nm below the upper surface of the mask film  104  while upper surfaces of the sidewalls  115  of a titanium nitride are not exposed. In the second embodiment, a vertical interval between the upper surfaces of the sidewalls  115  of a titanium nitride and the upper surfaces of the insulator films  116   a  is 10 nm. Nevertheless, that interval may be in a range of 5 nm to 15 nm. The trenches  117  have an opening width W 7  of 29 nm, which is the same as in the step shown in  FIG. 43 . 
         [0148]    Then, as shown in  FIG. 48 , a protective film  118  of a silicon film is formed with a thickness of 5 nm on the entire surface including inner surfaces of the trenches  117  by a CVD method. The protective film  118  is preferably formed of an amorphous silicon film (polysilicon) exerting no influence due to crystal grains that would cause uneven etching in a subsequent etching process. After the formation of the protective film  118 , boron fluoride (BF 2 ) is implanted by an oblique ion implantation method in order to dope impurities only into one of the protective films  118   b  and  118   c  formed on both side surfaces of the trenches  117 .  FIG. 48  shows an example of an oblique ion implantation method of doping impurities into the protective film  118   b . Impurities are doped into a protective film  118  formed on a sidewall opposite to a pillar on which a bit line contact is to be formed, which will be described later. 
         [0149]    Thus, impurities are doped into the protective film  118   a  formed on the mask film  104 , the protective film  118   b  having a vertical surface formed on the side surfaces of the trenches  117 , and part (left half) of the protective film  118  having a horizontal surface formed on the buried insulator film  116   a . Since ions should be implanted in the horizontal surfaces and the vertical surfaces in this example, two-stage implantation with different angles may be used to achieve optimum ion implantation for respective portions to be subjected to implantation. In the present embodiment, the implantation angle is set in a range of 27° to 45°. The implantation angle refers to an inclination angle from a perpendicular line to the surface of the semiconductor substrate. Furthermore, when the aforementioned two-stage implantation is used in the second embodiment, the implantation angles are set to be 27° and 45°. Nevertheless, the implantation angles may be changed in consideration of the depth and width of the trenches  117  and the film thickness of the protective film  118 . 
         [0150]    Next, as shown in  FIG. 49 , the protective films  118   c  in which no impurities have been implanted and the protective films  118  formed on right halves of the insulator films  116   a  are removed by wet etching with aqueous ammonia (NH 3 ). Thus, the sidewall insulator films  114  of a silicon nitride film and the right halves of the insulator films  116   a  are exposed. 
         [0151]    Then, as shown in  FIG. 50 , the right halves of the exposed insulator films  116   a  are removed by anisotropic dry etching while the protective film  118  is used as a mask. At that time, the leftward sidewalls  115  are covered with the insulator films  116   a  and the protective films  118  and are not exposed. Specifically, impurity doping regions of ion implantation should be controlled with the protective film  118  of  FIG. 48  such that the leftward sidewalls  115  are not exposed during this anisotropic dry etching process. Therefore, the implantation angle is determined in consideration of the depth and width of the trenches  117  and the film thickness of the protective film  118 . 
         [0152]    Thereafter, as shown in  FIG. 51 , the rightward sidewalls  115  of a titanium nitride, which have an exposed upper surface, are selectively removed by wet etching. A mixture liquid of ammonia and hydrogen peroxide or the like may be used as an etching liquid. Thus, the sidewall insulator films  114  of a silicon nitride film, part of the insulator films  107   a  formed within the trenches  106 , and part of the upper surfaces of the buried films  111   b  are exposed. 
         [0153]    Subsequently, as shown in  FIG. 52 , an ion implantation is performed, the protective film  118  in which ions were implanted ( FIG. 48 ) and remaining on a surface of the substrate ( FIG. 50 ) is removed by isotropic dry etching. The mask film  104  and the upper surfaces of the insulator films  116   a  are exposed by this isotropic dry etching. 
         [0154]    Next, as shown in  FIG. 53 , the insulator films  107   a  having an exposed side surface are etched with a hydrofluoric acid (HF) solution so as to form side openings  100   a , which expose part of the silicon pillars (semiconductor pillars)  100   b . The side openings  100   a  are formed between the bottoms of the sidewall insulator films  114  and the upper surfaces of the buried films  111   b . At that time, the insulator films  116   a  are also removed. However, the insulator films  110  remain as they are protected by the sidewall insulator films  114  of a silicon nitride film and are not etched. 
         [0155]    Then, as shown in  FIG. 54 , the sidewalls  115  of a titanium nitride exposed in the trenches ( FIG. 50 ) are selectively removed by wet etching. Thus, the trenches  112   c  formed in the step of  FIG. 44  are exposed. 
         [0156]    Thereafter, as shown in  FIG. 55 , a coating film  119 , which is to be a first silicon film, is deposited with a thickness of 10 nm so that inner surfaces of the trenches  112   c  are covered with the coating film  119 . For example, the following deposition conditions may be used. Monosilane (SiH 4 ) is used as a material gas. A flow rate of the gas is 1,500 sccm, and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. At that time, new trenches  112   d  are formed. 
         [0157]    Subsequently, as shown in  FIG. 56 , an impurity layer  120 , which is to be a second silicon film, is formed on the coating film  119  by adsorbing impurities of arsenic (As) on the exposed coating film  119  so that the concentration of the impurities is 1.0×10 15  atoms/cm 3 . For example, the following adsorption conditions may be used. Arsine (AsH 3 ) is used as a material gas. A flow rate of the gas is 400 sccm, and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. Within this temperature range, arsine is decomposed to produce a sufficient amount of arsenic. Thus, arsenic can readily be adsorbed on the coating film  119 . At that time, the trenches  112   d  remain. 
         [0158]    Next, as shown in  FIG. 57 , a buried film  121 , which is to be a third silicon film, is deposited on the impurity layer  120  by a CVD method so that the trenches  112   d  are filled with the buried film  121 . The thickness T 6  of the buried film  121  from a surface of the coating film  119  is 130 nm. For example, the following deposition conditions may be used. Monosilane (SiH 4 ) is used as a material gas. A flow rate of the gas is 1,500 sccm, and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. As shown in  FIG. 58 , which is an enlarged view of a portion surrounded by broken lines in  FIG. 57 , the interior of the side opening  100   a  surrounded by the insulator film  107 , the insulator film  110 , and the sidewall insulator film  114  is uniformly filled with the coating film  119 . 
         [0159]    Then, as shown in  FIG. 59 , an insulator film  122  of a silicon oxide film, which is to be a first diffusion barrier film, is deposited with a thickness of 3 nm on the buried film  121  by a thermal oxidation method. For example, the following deposition conditions may be used. Oxygen (O 2 ) is used as a material gas. A flow rate of the gas is 3 SLM, and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. Furthermore, the film thickness of the insulator film  122  is not limited to 3 nm and may be in a range of 2 nm to 3 nm. Thereafter, a coating film  123 , which is to be a fourth silicon film, is deposited with a thickness of 35 nm on the insulator film  122  by a CVD method. For example, the following deposition conditions may be used. Monosilane (SiH 4 ) is used as a material gas. A flow rate of the gas is 1,500 sccm, and a heating temperature is 550° C. The heating temperature is not limited to 550° C. and may be in a range of 500° C. to 600° C. Subsequently, an insulator film  122   a  of a silicon oxide film, which is to be a second diffusion barrier film, is deposited with a thickness of 3 nm on the coating film  123  by a thermal oxidation method. For example, the same deposition conditions as for the insulator film  122  may be used. In  FIG. 59 , the reference numerals  122  and  122   a  do not indicate any space or room but indicate insulator films. Furthermore, a coating film  123   a , which is to be a fifth silicon film, is deposited with a thickness of 35 nm on the insulator film  122   a  by a CVD method. For example, the same deposition conditions as for the coating film  123  may be used. 
         [0160]    Thus, insulator films of a silicon oxide film as a diffusion barrier film and coating films of a silicon film such as a polysilicon film are alternately deposited to produce a multilayered film. In this case, effects of preventing outer diffusion are improved as compared to a case of a single-layer polysilicon film having the same film thickness as the multilayered film. Therefore, the thickness of the multilayered film can be reduced. Accordingly, a throughput of deposition processes can be improved. The number of stacks of the multilayered film is not limited to two and may be designed in any way depending upon the permissible amount of outer diffusion. The coating film of a polysilicon film located at the uppermost layer of the multilayered film may be eliminated depending upon the permissible amount of outer diffusion. 
         [0161]    Separate production devices may be used in the production processes illustrated in  FIGS. 55 to 59 . Nevertheless, it is preferable to perform the production processes while a single production device changes processing recipes. With use of a single production device, it is not necessary to transport the silicon substrate  100  (silicon wafer) from one production device to another. Therefore, a throughput can be improved. 
         [0162]    Next, as shown in  FIG. 60 , the impurities in the impurity layer  120  ( FIG. 59 ) are thermally diffused into the coating film  119  ( FIG. 59 ) and the buried film  121  ( FIG. 59 ) by a lamp annealing method. At that time, annealing may be conducted under a nitrogen (N 2 ) atmosphere at a heating temperature of 1,000° C. The heating temperature is not limited to 1,000° C. and may be in a range of 800° C. to 1,200° C. As a result of this annealing process, the impurities in the impurity layer  120  are present in the coating film  119  and the buried film  121  with a uniform concentration gradient. Those films are incorporated into a doped layer  124 . However, since the coating film  119  and the buried film  121  have quite different film thicknesses, they have different impurity concentrations on surfaces opposite to surfaces facing the impurity layer  120  due to a difference of diffusion lengths. More specifically, the arsenic concentration at a contacting surface with the silicon pillars  100   b  is 1.0×10 18  atoms/cm 3 , whereas the arsenic concentration at a contacting surface with the insulator film  122  is 1.0×10 10  atoms/cm 3 . 
         [0163]    Then, as shown in  FIGS. 60 and 61 , an etchback is performed on the coating film  123 , the insulator film  122 , the doped layer  124 , and the buried film  111   b  with anisotropic dry etching. In each of the side openings  100   a , the doped layer  124  remains because the sidewall insulator film  114  serves as a mask. Thus, contacts  124   a  to the silicon pillars (semiconductor pillars)  100   b  are formed. 
         [0164]    Thereafter, as shown in  FIG. 62 , the sidewall insulator films  114  ( FIG. 61 ) of a silicon nitride film is selectively removed by wet etching, so that the insulator films  110  are exposed. In the side openings  100   a , a portion of the insulator film  107   a  forming the trenches  106   b  in the step of  FIG. 40  has been replaced with the contacts  124   a . At that time, new trenches  106   c , which serve as first grooves, are formed. 
         [0165]    Subsequently, as shown in  FIG. 63 , a barrier film  125  of a titanium nitride is formed with a thickness of 4 nm on the overall surface including inner surfaces of the trench  106   c , which serve as first grooves. Prior to the formation of the barrier film  125 , a titanium film is formed with a thickness of 1 nm on a surface of the silicon substrate  100  in the same reaction chamber for CVD. Because this titanium film deposits on surfaces of the contacts  124   a  formed of an arsenic-doped silicon film and forms a titanium silicide having a low resistance, the titanium film can reduce the resistance of the contacts. Titanium formed on the insulator films other than the silicon substrate  100  is nitrided at the time of the formation of a titanium nitride. Thus, titanium is formed into titanium nitride. Arsenic is diffused into the silicon substrate (semiconductor substrate)  100  from the contacts  124   a  by a thermal treatment of 650° C. for forming the barrier film  125 . Thus, a diffusion layer  120   a  is formed at one of side surfaces of each of the silicon pillars (semiconductor pillars)  100   b . The diffusion layers  120   a  may be formed continuously after the formation of the doped layers  124  in the step of  FIG. 60 . 
         [0166]    Next, as shown in  FIG. 64 , a conductive film  126  of tungsten is formed on the entire surface of the barrier film  125  by a CVD method so that the trenches  106   c  as first grooves are filled with the conductive film. 
         [0167]    Then, as shown in  FIG. 65  together with  FIG. 64 , an etchback is performed on the conductive film  126  and the barrier film  125  with anisotropic dry etching until surfaces of the conductive film  126  and the barrier film  125  are located at the same height as upper surfaces of the insulator films  107   a . Thus, a bit line  126   b  including the barrier film  125   a  and the conductive film  126   a , which are surrounded by the insulator film  107   a , is formed in each of the trenches  106   c  formed as the first grooves by the silicon pillars (semiconductor pillars)  100   b . The bit line  126   b  is connected to the diffusion layer  120   a  via a titanium silicide (not shown) and the contact  124   a  at a side surface of the bit line  126   b . Furthermore, a new trench  106   d  is formed above the bit line  126   b  by an etchback. Thereafter, the insulator film  110  ( FIG. 64 ) is removed by wet etching, so that part of the side surfaces of the silicon pillars (semiconductor pillars)  100   b  is exposed. 
         [0168]    Subsequently, as shown in  FIG. 66 , an insulator film  127  of a silicon nitride film is formed with a thickness of 10 nm on the entire surface including inner surfaces of the trenches  106   d  by a CVD method. Furthermore, the trenches  106   d  are filled with a silicon oxide film by a spin coating method. Next, an etchback is performed so as to form insulator films  128  of a silicon oxide film having a thickness of 70 nm. Accordingly, shallowed trenches remain above the insulator films  128 . Then an insulator film  129  of a silicon oxide film is formed by a CVD method so that the shallowed trenches are filled with the insulator film  129 . The plan view at that time is as shown in  FIG. 67 . Thus, as with  FIG. 33 , a plurality of trenches  106   c  in which the bit lines  126   b  ( FIG. 66 ) are buried extend along the Y-direction in parallel to each other. 
         [0169]    The buried bit lines are completed with the above processes. Then buried word lines are produced. Those buried word lines are produced in the same manner as described with reference to  FIGS. 21 to 30 . Therefore, the explanation of the method of producing buried word lines is omitted herein. 
         [0170]    In the second embodiment, the diffusion layers  120   a  are formed in the silicon pillars  100   b  by thermally diffusing impurities from the side openings  100   a , which expose part of the silicon pillars  100   b . At that time, the side openings  100   a  are formed right below the channel regions. Therefore, the diffusion layers  120   a , which serve as one of a source and a drain (S/D), can readily be formed right below the channel regions. 
         [0171]    According to the present invention, instead of ion implantation, a silicon film such as polysilicon in which impurities have been doped is formed near a semiconductor pillar in which a diffusion layer is provided. The impurities are diffused to the semiconductor pillar by a thermal diffusion method. In a semiconductor pillar of a vertical transistor, a diffusion layer is formed on one of side surfaces of the semiconductor pillar, and another diffusion layer or a bit line is provided on the other side surface of the semiconductor pillar. Therefore, the diffusion layer needs to be formed only on one of the side surfaces of the semiconductor pillar and does not need to reach the opposite side surface of the semiconductor pillar by thermal diffusion. In view of such structural limitations, arsenic (As) having a small diffusion coefficient is used as impurities. Since arsenic is a highly toxic substance, outer diffusion from a semiconductor substrate (wafer) into atmosphere needs to be minimized to avoid adverse influence on humans. Particularly, since a vertical transistor inevitably requires thermal diffusion of arsenic into a silicon pillar, outer diffusion caused by thermal diffusion should be prevented. 
         [0172]    According to the present invention, a diffusion barrier film is formed on a silicon film such as polysilicon including impurities. A multilayer film in which an insulator film of a silicon oxide film as a diffusion barrier film and a coating film of a silicon film such as polysilicon are alternately deposited is provided. Therefore, prevention of outer diffusion can be improved as compared to a single-layer polysilicon film having the same film thickness as the multilayer film. As a result, a safe manufacturing environment can be ensured. 
         [0173]    Furthermore, in a case where the prevention effects are constant, the multilayer film can be reduced in thickness as compared to a single-layer polysilicon film. Therefore, a throughput of a deposition process can be improved. The number of stacks of the multilayered film is not limited to two and may be designed in any way depending upon the permissible amount of outer diffusion. The coating film of a silicon film located at the uppermost layer of the multilayered film may be eliminated depending upon the permissible amount of outer diffusion. Separate production devices may be used in the production processes illustrated in  FIGS. 7 to 12  and  55  to  59 . Nevertheless, it is preferable to perform the production processes while a single production device changes processing recipes. With use of a single production device, it is not necessary to transport the silicon substrate  100  (silicon wafer) from one production device to another. Therefore, a throughput can be improved. 
         [0174]    According to the embodiments of the present invention, a side surface of a groove on which a semiconductor pillar is exposed is covered with an insulator film. Then a polysilicon film including impurities is formed within the entire space of the groove. The impurities are thermally diffused into the semiconductor pillar at a bottom of the groove. Thus, a diffusion layer to be a bit line can be formed only right below a channel region. Accordingly, malfunction of a transistor that has been caused by unnecessary ion implantation can be eliminated. 
         [0175]    While the present invention has been described with reference to several embodiments thereof, the present invention is not limited to those embodiments. As a matter of course, many modifications may be made therein without departing from the spirit and scope of the present invention.