Abstract:
A control circuit included within a multi-phase switched-mode converter is configured for adjusting operational signals for adding power stages of the multi-phase switched-mode converter to dynamically respond to transient changes in load current for minimizing undershoot while avoiding overshoot of an output voltage of the multi-phase switched-mode converter. The control circuit has panic comparators configured such that each panic comparator has an input terminal connected to receive the output voltage for comparison with one of a plurality of reference voltages. A panic controller receives panic indicator signals from the panic comparators and determines which of the power stages are to be activated to match the transient change to the load current to prevent for minimizing undershoot and for preventing overshoot of the output voltage of the multi-phase switched-mode converter. The multi-phase switched-mode converter may operate in a continuous or discontinuous conduction mode.

Description:
TECHNICAL FIELD 
     This disclosure relates generally to switched-mode power converters. More particularly, this disclosure relates to multiple phase switched-mode power converters. Even more particularly, this disclosure relates to multiple phase switched-mode power converters with circuits for instantaneously activating the deactivated phases of the multiple phase switched-mode power converters. 
     BACKGROUND 
     As is known in the art, switched-mode power supplies incorporate a switching regulator to convert electrical power efficiently. The switched-mode power supplies transfer power from a source to a load while converting voltage and current applied to the input of the circuit to an output voltage and current suitable for the load. The switched-mode power supplies consist of a power stage and a control circuit. The power stage performs the basic power conversion from the input voltage to the output voltage and includes switches and an output filter. The control stage receives necessary feedback signals from the power stage and control signals from system operating functions. The feedback and control signals are interpreted to provide the driving signals for the power stage. 
     In current hand-held mobile electronic devices such as cellular telephones, tablet computers, portable media players and the like require a higher dynamic range of output current from the switched-mode power supplies. What is needed is that as the range of output currents requirements expands, the switched-mode power supplies must operate more efficiently over a broad range of output currents. 
     Multi-phase switched-mode power supplies include a quantity of switched-mode converters that are coupled in parallel to deliver high output currents to a load. The multiple parallel switched-mode converters provide an energy efficient DC/DC converter for supplying high output currents. Switching loss and DC loss degrades the efficiency of a switched-mode converter. The DC loss is due to the voltage drop across resistances such as on-resistance of the switching devices in the power stage and it is proportional to the square of the load current. Contribution to the efficiency is proportional to the load current and dominant for higher load current. To improve the efficiency for higher load current, activating multiple phases in parallel reduces the effective on-resistance. However, switching loss of the switching devices in the power stage is almost constant regardless of the load current. For lower load current, the switching loss contribution becomes dominant, as the DC loss is essentially negligible. At the lower load currents, the number of active phases should be minimized for reducing the switching loss and improving the efficiency. To improve the efficiency, some of multi-phase switched-mode power supplies have a phase shedding function. The number of phase are deactivated or activated according to the output current to maximize the efficiency. 
     SUMMARY 
     An object of this disclosure is to provide circuits and methods for adjusting operational signals for adding at least one of a plurality of slave power stages of a multi-phase switched-mode converter to dynamically respond to transient changes in load current for minimizing undershoot while avoiding overshoot of an output voltage of the multi-phase switched-mode converter. 
     To accomplish at least this object, a control circuit included within the multi-phase switched-mode converter has a plurality of panic comparators. Each panic comparator has an input terminal connected to receive an output voltage of the multi-phase switched-mode converter. The control circuit has a plurality of panic reference voltage sources, wherein each panic reference voltage source is connected to a reference terminal of one panic comparator to provide a panic reference voltage to the one panic comparator. Each panic comparator is configured to compare the output voltage of the multi-phase switched-mode converter to one of the reference voltages from one of the panic reference voltage sources to generate a panic indicator signal at an output terminal of the one panic comparator. A panic controller is connected to each of the output terminals of the plurality of panic comparators to receive panic indicator signals from the plurality of panic comparators signifying that the output voltage of the multi-phase switched-mode converter is less than the panic reference voltage of at least one of the plurality panic reference voltage sources. The panic controller determines which of the slave power stages are to be activated to match the transient change to the load current for minimizing undershoot and for preventing overshoot of the output voltage of the multi-phase switched-mode converter. The panic reference voltage level of the plurality of panic reference voltage sources are separated by increments of voltage such that the panic controller will activate at least one of the slave power stages for minimizing undershoot and for preventing the overshoot. 
     Each of the plurality of panic reference voltage sources is adjustable to vary the panic reference voltage levels dependent upon a transient response of each of the plurality of slave power stages. 
     In various embodiments, the control circuit has a pulse frequency modulation controller that is configured to provide discontinuous conduction mode control signals to the master power stage for operating in a discontinuous conduction mode. The pulse frequency controller has a pulse frequency modulation comparator connected to receive the output voltage of the multi-phase switched-mode converter and configured to provide discontinuous control signal to the pulse frequency modulation controller. The pulse frequency controller has a pulse frequency modulation reference voltage source. The pulse frequency modulation reference voltage source provides a pulse frequency modulation reference voltage to the pulse frequency modulation comparator for controlling the discontinuous conduction mode of the multi-phase switched-mode converter. When the output voltage level is less than a voltage level of the pulse frequency modulation reference voltage and greater than the panic voltage levels of plurality of panic reference voltage sources, the multi-phase switched-mode converter operates in the discontinuous conduction mode. 
     When a large transient change in the load current occurs, the pulse frequency modulation controller activates the master power stage to operate in the continuous conduction mode and when the large transient becomes larger than the panic reference voltage level of at least one of the plurality panic reference voltage sources, the panic controller activates at least one of the slave power stages for minimizing undershoot and for preventing the overshoot of the voltage level of the output voltage. 
     In other embodiments that accomplish at least this object, a multi-phase switched-mode converter is configured for adding at least one of a plurality of slave power stages included within the multi-phase switched-mode converter to dynamically respond to transient changes in load current while avoiding overshoot of an output voltage of the multi-phase switched-mode converter. The multi-phase switched-mode converter includes at least the master power stage and one slave power stage. The multi-phase switched-mode converter includes a control circuit configured for adjusting operational signals of a master power stage included within the multi-phase switched-mode converter and the plurality of slave power stages of the multi-phase switched-mode converter. The control circuit has a plurality of panic reference voltage sources, wherein each panic reference voltage source is connected to a reference terminal of one panic comparator to provide a panic reference voltage to the one panic comparator. Each panic comparator is configured to compare the output voltage of the multi-phase switched-mode converter to one of the panic reference voltages from one of the panic reference voltage sources to generate a panic indicator signal at an output terminal of the one panic comparator. A panic controller is connected to each of the output terminals of the plurality of panic comparators to receive panic indicator signals from the plurality of panic comparators signifying that the output voltage of the multi-phase switched-mode converter is less than the panic reference voltage of at least one of the plurality panic reference voltage sources. The panic controller determines which of the slave power stages are to be activated to match the transient change to the load current for minimizing undershoot and for preventing overshoot of the output voltage of the multi-phase switched-mode converter. The panic reference voltage level of the plurality of panic reference voltage sources are separated by increments of voltage such that the panic controller will activate at least one of the slave power stages for minimizing undershoot and for preventing the overshoot. 
     Each of the plurality of panic reference voltage sources is adjustable to vary the panic reference voltage levels dependent upon a transient response of each of the plurality of slave power stages. 
     In various embodiments, the control circuit has a pulse frequency modulation controller that is configured to provide discontinuous conduction mode control signals to the master power stage for operating in a discontinuous conduction mode. The pulse frequency controller has a pulse frequency modulation comparator connected to receive the output voltage of the multi-phase switched-mode converter and configured to provide discontinuous control signal to the pulse frequency modulation controller. The pulse frequency controller has a pulse frequency modulation reference voltage source. The pulse frequency modulation reference voltage source provides a pulse frequency modulation reference voltage to the pulse frequency modulation comparator for controlling the discontinuous conduction mode of the multi-phase switched-mode converter. When the output voltage level is less than a voltage level of the pulse frequency modulation reference voltage and greater than the voltage levels of plurality of reference voltage sources, the multi-phase switched-mode converter operates in the discontinuous modulation mode. 
     When a large transient change in the load current occurs, the pulse frequency modulation controller activates the master power stage to operate in the continuous conduction mode and when the large transient becomes larger than the panic reference voltage level of at least one of the plurality panic reference voltage sources, the panic controller activates at least one of the slave power stages for minimizing undershoot and for preventing the overshoot of the voltage level of the output voltage. 
     In other embodiments that accomplishes at least this object, a method for operating a multi-phase switched-mode converter is structured for adding at least one of a plurality of slave power stages included within the multi-phase switched-mode converter to dynamically respond to transient changes in load current while avoiding overshoot and minimizing undershoot voltage changes. The method consists of steps for adjusting operational signals of a master power stage included within the multi-phase switched-mode converter and the plurality of slave power stages. The first step of adjusting the operational signals is providing at least one panic reference voltage source for generating at least one panic reference voltage level. The output voltage of the multi-phase switched-mode converter is compared with at least panic reference voltage level and at least one panic indicator signal signifying that the output voltage level of the multi-phase switched-mode converter is less than at least one panic reference voltage level is generated. Which of the slave power stages that are to be activated is determined so as to match the precipitous load current increase for minimizing undershoot and for preventing overshoot of the output voltage of the multi-phase switched-mode converter. 
     The method separates the plurality of panic reference voltage levels by incremental voltage levels such that at least one of the slave power stages is activated for minimizing the undershoot and for preventing the overshoot. The multi-phase switched-mode converter has at least two slave power stages for best operation of the method. The method further includes varying each of the plurality of panic reference voltage levels dependent upon a transient response of each of the plurality of slave power stages. 
     In various embodiments, the step of adjusting operational signals of the master power stage and the at least one slave power stage further provides a discontinuous conduction mode control signal to the master power stage for operating in a discontinuous conduction mode. A pulse frequency modulation reference voltage is compared with the received the output voltage level of the multi-phase switched-mode converter. When output voltage level is less than the pulse frequency modulation reference voltage level and greater than the plurality of panic reference voltage levels, the discontinuous conduction mode control signal is generated to be provided to the master power stage. 
     The step of adjusting operational signals of the master power stage and the plurality of slave power stages of the multi-phase switched-mode converter further includes the step of activating the master power stage to operate in the continuous conduction mode, when a large transient change in load current occurs. At least one of the slave power stages is activated for minimizing undershoot and for preventing the overshoot of the voltage level of the output voltage, when the large transient becomes larger than the panic reference voltage levels of at least one of the plurality panic reference voltage levels. 
     In other embodiments that accomplish at least this object, an apparatus is configured to include means for performing the steps of the method for operating a multi-phase switched-mode converter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1 a    is a schematic of a multi-phase switched-mode power supply incorporating a panic comparator of the related art known to the inventors of this disclosure. 
         FIG. 1 b    is a schematic of the phase power stages of the multi-phase switched-mode power supply  FIG. 1   a.    
         FIG. 2  is a plot illustrating the voltage and current waveforms within the multi-phase switched-mode power supply of  FIGS. 1 a    and  1   b.    
         FIG. 3 a    is a schematic of a multi-phase switched-mode power supply incorporating a panic comparator embodying the principle of the present disclosure. 
         FIG. 3 b    is a schematic of a multi-phase switched-mode power supply incorporating a panic comparator of  3   a  with three panic converters and four power stages embodying the principle of the present disclosure. 
         FIGS. 4-8  are plots illustrating the voltage and current waveforms within the multi-phase switched-mode power supply of  FIG. 3  under various operating conditions. 
         FIG. 9 a    is a schematic of a multi-phase switched-mode power supply incorporating a panic comparator embodying the principle of the present disclosure. 
         FIG. 9 b    is a schematic of a multi-phase switched-mode power supply incorporating a pulse frequency modulator circuit and two panic comparators of  9   a  with four power stages embodying the principle of the present disclosure. 
         FIG. 10  is a plot illustrating the voltage and current waveforms within the multi-phase switched-mode power supply of  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION 
     When a load current increases precipitously, the deactivated phases must be activated instantaneously to achieve a good load transient response (less output voltage disturbance) to support higher output load current. One solution for having the good load transient response implementing a so-called ‘panic’ comparator. The panic comparator detects a drop in the output voltage of the multi-phase switched-mode power supply as an under-voltage condition. The multi-phase switched-mode power supply instantly and asynchronously activates all the switched-mode converter phases. In this case, output voltage drop can be minimized. 
     This method may cause ‘over-shoot’ in a situation where the load transient is not too precipitous, but still triggers the panic comparator. With a moderate load transient, all the switched-mode converter phases are instantly activated, and a high current flows into the output capacitor. This current may be more than required and cause excess output voltage overshoot to occur. 
     One solution to this problem is lowering the panic reference voltage to avoid the overshoot at lower output current levels. This causes the panic comparator to function less effective at heavy load condition and result in more undershoot at heavy load transient conditions. 
       FIG. 1 a    is a schematic of a multi-phase switched-mode power supply incorporating a panic comparator that is related to the art as known to the inventors of this disclosure. The switched-mode converter is structured as a multiphase buck switched-mode converter. The multiphase buck switched-mode converter has a control circuit  5 , multiple power stages  25   a ,  25   b , . . . ,  25   n , and a filter stage  30 . The multiple power stages  25   a ,  25   b , . . . ,  25   n  include one master power stage  25   a  and multiple slave power stages  25   b , . . . ,  25   n . One power stage  25   a  of the multiple power stages  25   a ,  25   b , . . . ,  25   n  is designated as a master power stage with the remaining power stages  25   b , . . . ,  25   n  being designated as slave power stages. 
     The filter stage  30  has a multiple inductors L 1 , L 2 , . . . , L n  where a first terminal of each of the inductors L 1 , L 2 , . . . , L n  is connected to an output  26   a ,  26   b , . . . ,  26   n  of one of the power stages  25   a ,  25   b , . . . ,  25   n . The second terminals of the inductors L 1 , L 2 , . . . , L n  are commonly connected together and to the first plate of a load capacitor C L . The second plate of the load capacitor C L  is connected to the ground reference voltage source. The commonly connected second terminals of the inductors L 1 , L 2 , . . . , L n  and the first plate of the load capacitor C L  are connected to the load  35 . The load current I OUT  is the current flowing to the load  35 . The load current I OUT  is the total current from all the power stages  25   a ,  25   b , . . . ,  25   n.    
       FIG. 1 b    is a schematic of each of the phase power stages  25   a ,  25   b , . . . ,  25   n  of the multi-phase switched-mode power supply  FIG. 1 a   . Each of the power stages  25   a ,  25   b , . . . ,  25   n  includes a pulse width modulator  27  that receives the error voltage  17 . The outputs of the pulse width modulator  27  are applied to the gates of a PMOS transistor M P  and an NMOS transistor M N . The source of the PMOS transistor M P  is connected to the input supply voltage source VIN and the source of the NMOS transistor M N  is connected to the ground reference voltage source. The commonly connected drains of the PMOS transistor M P  and the NMOS transistor M N  are connected to the output terminal  26   a ,  26   b , . . . ,  26   n  of each of the power stages  25   a ,  25   b , . . . ,  25   n  that is connected to one of the input terminals of the filter section  30  that is a first terminal of each of inductors L 1 , L 2 , . . . , L n . 
     The NMOS transistor M N  has a current sensor  29  connected such that the current flowing in the current sensor  29  is detected. The current sensor  29  is connected to a current sense circuit  28  that conditions the detected current flowing in the NMOS transistor M N  for transfer as the current sense signal  41   n.    
     Returning to  FIG. 1 a   , the commonly connected second terminals of the inductors L 1 , L 2 , . . . , L n  and the first plate of the load capacitor C L  are connected to an input of the control circuit  5  to provide a feedback path  55  for comparing the output voltage V OUT  of the multiphase buck switched-mode converter with a reference voltage level V REF . The reference voltage generator  10  generates the reference voltage level V REF . 
     The control circuit  5  has an error amplifier  15  that receives the fed-back output voltage V OUT  and the reference voltage level V REF  from reference voltage generator  10 . The output of the error amplifier  15  is an error voltage  17  that is applied to each of the power stages  26   a ,  26   b , . . . ,  26   n.    
     The current sense signals  41   a , . . . ,  41   n  from each of the power stages  25   a ,  25   b , . . . ,  25   n  are inputs to the total current estimation circuit  40 . The total current estimation circuit  40  is a summation circuit that totals the current sense signals  41   a , . . . ,  41   n  to determine the estimated total current signal I EST . The estimated total current signal I EST  is applied to the phase shedding control circuit  20 . As the estimated total current signal I EST , the phase shedding control circuit  20  generates the phase shedding signals  22   a ,  22   b , . . . ,  22   n  for activating and deactivating selected power stages  25   a ,  25   b , . . . ,  25   n  for maintaining the efficiency of the operation of the multi-phase switched-mode power supply. 
     The control circuit  5  has a panic comparator  45  that compares the fed-back output voltage V FB  to a panic reference voltage V REFP . The voltage source  50  generates the panic reference voltage V REFP  a being a voltage level less than the reference voltage level V REF  as generated by the reference voltage generator  10 . The result of the comparison of the fed-back output voltage V FB  and the panic reference voltage V REFP  is the panic signal V PANIC  that is the output  47  of the panic comparator  45 . The panic signal V PANIC  is an input to the phase shedding control circuit  20  for activating all deactivated power stages  25   a ,  25   b , . . . ,  25   n  simultaneously. 
       FIG. 2  is a plot illustrating the voltage and current waveforms within the multi-phase switched-mode power supply of  FIGS. 1 a  and 1 b   . Prior to the time t 1 , the output voltage V OUT  with the output current I OUT  at a no load current level  59  with only one power stage  25   a  being activated  75 . At the time t 1 , the output load  35  requires that the output current I OUT  transit to a full load current level  65 . The output voltage V OUT  drops to a voltage level  60  less than the panic reference voltage V REFP  and the panic signal V PANIC  is activated from the low level  90  to the high level  70  to instruct the phase shedding control circuit  20  to activate all deactivated power stages  25   a ,  25   b , . . . ,  25   n  simultaneously. At the time t 2 , all the power stages  25   a ,  25   b , . . . ,  25   n  are activated  95  such that the output voltage V OUT  begins to rise until it is greater than the panic reference voltage V REFP  at the time t 4 . The output voltage V OUT  returns to its steady controlled state at the time t 6 . 
     At the time t 1 , if the output load  35  requires that the output current I OUT  transit to a moderate load current level  85 , the output voltage V OUT  drops to a level  62  that is less than the panic reference voltage V REFP  and the panic signal V PANIC  is again activated from the low level  90  to the high level  70  to instruct the phase shedding control circuit  20  to activate  95  all deactivated power stages  25   a ,  25   b , . . . ,  25   n  simultaneously. The output voltage V OUT  has an overshoot voltage level  80  that peaks at about the time t 4  and decays back to its steady controlled state at the time t 6 . The overshoot is the result of the all the power stages  25   a ,  25   b , . . . ,  25   n  being instantly activated. This causes a high output current I OUT  to flow into the output capacitor C L . This excess output current I OUT  is more than required, thus causing an excess of the output voltage V OUT  and the overshoot voltage level  80  to occur. 
     At the times t 3  and t 5 , the panic signal V PANIC  is deactivated to the low level  90  for the moderate load at the time t 3  and for the heavy load at the time t 5 . Once the panic signal V PANIC  is activated to the high level  70  at the time t 1 , the power stages  25   a ,  25   b , . . . ,  25   n  are activated and the full four phase control of the power stages  25   a ,  25   b , . . . ,  25   n  continues regardless of the state of the panic signal V PANIC    
       FIG. 3  is a schematic of a multi-phase switched-mode power supply incorporating a panic comparator embodying the principle of the present disclosure. The switched-mode converter of  FIG. 3  is structured as a multiphase buck switched-mode converter. The multiphase buck switched-mode converter has a control circuit  100 , multiple power stages  25   a ,  25   b ,  25   c , . . . ,  25   n , and a filter stage  30 . The multiple power stages  25   a ,  25   b ,  25   c , . . . ,  25   n , and a filter stage  30  are structured and function as described in  FIG. 1 . 
     The commonly connected second terminals of the inductors L 1 , L 2 , . . . , L n  and the first plate of the load capacitor C L  are connected to an input of the control circuit  100  to provide a feedback path  55  for comparing the output voltage V OUT  of the multiphase buck switched-mode converter with a reference voltage level V REF . The reference voltage generator  10  generates the reference voltage level V REF . 
     The control circuit  100  has an error amplifier  15  that receives the fed-back output voltage V FB  and the reference voltage level V REF  from reference voltage generator  10 . The output of the error amplifier  15  is an error voltage  17  that is applied to each of the power stages  25   a ,  25   b ,  25   c , . . . ,  25   n.    
     The current sense signals  41   a , . . . ,  41   n  from each of the power stages  25   a ,  25   b ,  25   c , . . . ,  25   n  are inputs to the total current estimation circuit  40 . The total current estimation circuit  40  is a summation circuit that totals the current sense signals  41   a , . . . ,  41   n  to determine the estimated total current signal I EST . The estimated total current signal I EST  is applied to the phase control circuit  110  and thus to the phase shedding control circuit  125 . As the estimated total current signal I EST  varies, the phase control circuit  125  generates the phase shedding signals  22   a ,  22   b , . . . ,  22   n  for activating and deactivating selected power stages  25   a ,  25   b ,  25   c , . . . ,  25   n  for maintaining the efficiency of the operation of the multi-phase switched-mode power supply. 
     The control circuit  100  has a panic comparator circuit  105  that compares the fed-back output voltage V FB  to multiple panic reference voltages V REFP1 , V REFP2 , . . . , V REFPn . The panic reference voltage sources  120   a ,  120   b , . . . ,  120   n  generates the multiple panic reference voltages V REFP1 , V REFP2 , . . . , V REFP1  that are at incremental voltage levels less than the reference voltage level V REF  as generated by the reference voltage generator  10 . The panic comparator circuit  105  has multiple panic comparators  115   a ,  115   b  . . . ,  115   n . Each of the multiple panic comparators  115   a ,  115   b  . . . ,  115   n  are connected to one of the incremental multiple panic reference voltages V REFP1 , V REFP2 , . . . , V REFPn . The result of the comparison of the fed-back output voltage V FB  and the incremental multiple panic reference voltages V REFP1 , V REFP2 , . . . , V REFPn  are the multiple panic signals V P1 , V P2 , . . . , V Pn  that is the outputs  117   a ,  117   b  . . . ,  117   n  of the multiple panic comparators  115   a ,  115   b  . . . ,  115   n . The multiple panic signals V P1 , V P2 , . . . , V Pn  are inputs to the phase control circuit  110  that is then transferred to the panic controller circuit  125  for activating all deactivated power stages  25   a ,  25   b ,  25   c , . . . ,  25   n  as required to dynamically respond to transient changes in load current for minimizing undershoot while avoiding overshoot of an output voltage of the multi-phase switched-mode converter. 
       FIG. 3 b    is a schematic of a multi-phase switched-mode power supply incorporating a panic comparator of  3   a  with three panic converters  115   a ,  115   b , and  115   c  and four power stages  25   a ,  25   b ,  25   c , and  25   d  embodying the principle of the present disclosure.  FIGS. 4-8  are plots illustrating the voltage and current waveforms within the multi-phase switched-mode power supply of  FIG. 3 b    under various operating conditions. In order to simplify the explanation of the operation of the multi-phase switched-mode power supply of  FIG. 3 a   , the multi-phase switched-mode power supply has a total of four power stages  25   a ,  25   b ,  25   c ,  25   d  as shown in  FIG. 3 b   . One power stage will be designated as the master stage and the remaining three power stages  25   b ,  25   d  will designated as the slave power stages. The multi-phase switched-mode power supply includes three panic comparators  115   a ,  115   b , and  115   c . Three panic reference voltage sources  120   a ,  120   b , and  120   c  are connected to the three panic comparators  115   a ,  115   b ,  115   c  to provide the three panic reference voltages V REFP1 , V REFP2 , . . . , V REFPn  generated by the three panic reference voltage sources  120   a ,  120   b , and  120   c . The three panic reference voltages V REFP1 , V REFP2 , and V REFP3  are at voltage level increments of 10 mv less than the reference voltage level V REF  as generated by the reference voltage generator  10  in this instance the reference voltage level V REF  is approximately 1.0V. Thus, the first panic comparator  115   a  has a reference voltage V REFP1  of approximately 990 mV (−10 mV), the second panic comparator  115   b  has a reference voltage V REFP2  of approximately 980 mV (−20 mV), and the third panic comparator  115   c  has a reference voltage V REFP3  of approximately 970 mV (−30 mV). For this example the full load required of the four power stage  25   a ,  25   b ,  25   c , and  25   d  operation is 40 A. As is apparent from  FIG. 3 a   , this example does not define any restrictions of the number of power stages  25   a ,  25   b ,  25   c , . . . ,  25   n , the voltage and current capacity of the multi-phase switched-mode power supply, or the number of panic comparators  115   a ,  115   b  . . . ,  115   n  with their panic reference voltages V REFP1 , V REFP2 , . . . , V REFPn . 
     Referring now to  FIGS. 3 b    and  4 , prior to the time t 1 , the output current I OUT  flowing through the load is approximately zero amps (0 A). The output voltage V OUT  is to be maintained at the reference voltage level V REF  as generated by the reference voltage generator  10 . The output voltage V OUT  and the output load current I OUT  is maintained by the master power stage  25   a  and the slave power stages  25   b ,  25   c , and  25   d  have been deactivated. The output panic signals V P1 , V P2 , and V P3  of the three panic comparators  115   a ,  115   b , and  115   c  are set to a deactivated logic level (0) with the master power stage  25   a  being the single stage activated. 
     At the time t 1 , the load circuit is actuated such that the output load current I OUT  increases to 40 A precipitously. The master power stage  25   a  is not able to respond with sufficient current. Thus the output current I OUT  is drawn from the load capacitor C L . This causes the output voltage V OUT  to decrease practically instantaneously until it reaches a level less than all the panic reference voltage levels V REFP1 , V REFP2 , and V REFP3 . All of the panic comparators  115   a ,  115   b , and  115   c  are activated and the panic signals V P1 , V P2 , and V P3  transit from the deactivated level (0) to the activated level (1). The slave power stages  25   b ,  25   c , and  25   d  are activated such that now the master power stage  25   a  and the slave power stages  25   b ,  25   c , and  25   d  begin to increase the current capacity such that the output voltage V OUT  rises toward the reference voltage level V REF  of approximately 1.0V. At the time t 2 , the third panic comparator  115   c  deactivates and the panic signal V Pn  transits from the activated level (1) to the deactivated level (0). At the time t 3 , the second panic comparator  115   b  deactivates and the panic signal V P 2 transits from the activated level (1) to the deactivated level (0). And at the time t 3 , the first panic comparator  115   a  deactivates and the panic signal V P1  transits from the activated level (1) to the deactivated level (0). Once the panic signals V P1 , V P2 , and V P3  are activated at the time t 1 , the power stages  25   a ,  25   b ,  25   c , and  25   d  are activated and the full four phase control of the power stages  25   a ,  25   b ,  25   c , and  25   d  continues regardless of the state of the panic signals V P1 , V P2 , and V P3 . At the time T 5 , the four power stage  25   a ,  25   b ,  25   c , and  25   d  are now regulating the output voltage V OUT . 
     Referring now to  FIGS. 3 b    and  5 , prior to the time t 1 , the output current I OUT  flowing through the load is approximately zero amps (0 A). The output voltage V OUT  is to be maintained at the reference voltage level V REF  as generated by the reference voltage generator  10 . The output voltage V OUT  and the output load current I OUT  are maintained by the master power stage  25   a  and the slave power stages  25   b ,  25   c , and  25   d  have been deactivated. The output panic signals V P1 , V P2 , and V P3  of the three panic comparators  115   a ,  115   b  and  115   d  are to a deactivated logic level (0) with the master power stage  25   a  being the single stage activated. 
     At the time t 1 , the load circuit is actuated such that the output current I OUT  increases to a moderate current level of approximately 20 A, again, precipitously. The master power stage  25   a  is not able to respond with sufficient current. Thus the output current I OUT  is drawn from the load capacitor C L . Thus causing the output voltage V OUT  to decrease practically instantaneously until it reaches a level less than the first panic reference voltage level V REFP1 . The first panic comparator  115   a  is activated and the panic signal V P1  transits from the deactivated level (0) to the activated level (1). The slave power stage  25   b  is activated such that now the master power stage  25   a  and the slave power stage  25   b  begin to increase the current capacity such that the output voltage V OUT  rises toward the reference voltage level V REF  of approximately 1.0V. At the time t 2 , the first panic comparator  115   a  deactivates and the panic signal V P1  transits from the activated level (1) to the deactivated level (0). As above, once the panic signal V P1  is activated at the time t 1 , the power stages  25   a  and  25   b  are activated and the phase control of the power stages  25   a  and  25   b  continues regardless of the state of the panic signals V P1 , V P2 , and V P3 . At the time t 3 , the two power stage  25   a  and  25   b  are now regulating the output voltage V OUT . 
     Referring now to  FIGS. 3 b    and  6 , prior to the time t 1 , the output current I OUT  flowing through the load is approximately zero amps (0 A). The output voltage V OUT  is to be maintained at the reference voltage level V REF  as generated by the reference voltage generator  10 . The output voltage V OUT  and the output current I OUT  is maintained by the master power stage  25   a  and the slave power stages  25   b ,  25   c , and  25   d  have been deactivated. The output panic signals V P1 , V P2 , . . . , V Pn  of the three panic comparators  115   a ,  115   b  and  115   d  are set to a deactivated logic level (0) with the master power stage  25   a  being the single stage activated. 
     At the time t 1 , the load circuit is actuated such that the output load current I OUT  increases to a higher load current level of approximately 30 A, again, precipitously. The master power stage  25   a  is not able to respond with sufficient current. Thus the output current I OUT  is drawn from the load capacitor C L . Thus causing the output voltage V OUT  to decrease practically instantaneously until it reaches a level less than the second panic reference voltage level V REFP2 . The first and second panic comparator  115   a  and  115   b  are activated and the panic signals V P1  and V P2  transit from the deactivated level (0) to the activated level (1). The two slave power stages  25   b  and  25   c  are activated such that now the master power stage  25   a  and the slave power stages  25   b  and  25   c  begin to increase the current capacity such that the output voltage V OUT  rises toward the reference voltage level V REF  of approximately 1.0V. At the time t 2 , the second panic comparator  115   b  deactivates and the panic signal V P2  transits from the activated level (1) to the deactivated level (0). At the time t 3 , the second panic comparator  115   b  deactivates and the panic signal V P2  transits from the activated level (1) to the deactivated level (0). As above, once the panic signals V P1  and V P2  are activated at the time t 1 , the power stages  25   a ,  25   b , and  25   c  are activated and the full four phase control of the power stages  25   a ,  25   b , and  25   c  continues regardless of the state of the panic signals V P1 , V P2 , and V P3 . At the time t 4 , the two power stage  25   a  and  25   b  are now regulating the output voltage V OUT . 
     Referring now to  FIGS. 3 b   ,  7 , and  8 , in some embodiments, it is possible to maintain a fewer number of panic comparators  115   a ,  115   b  . . . ,  115   n . Having fewer panic comparators  115   a ,  115   b  . . . ,  115   n  may be more practical as long as there is not a dramatic overshoot. For example, the multi-phase switched-mode power supply includes two panic comparators  115   a  and  115   c . Two panic reference voltage sources  120   a  and  120   n  are connected to the two panic comparators  115   a  and  115   c  to provide the two panic reference voltages V REFP1  and V REFP3  generated by the two panic reference voltage sources  120   a  and  120   c . The two panic reference voltages V REFP1  and V REFP3  are at voltage level increments of 20 mv between each other and the panic reference voltages V REFP1  being 10 mv less than the reference voltage level V REF  as generated by the reference voltage generator  10 . In this instance the reference voltage level V REF  is approximately 1.0V. Thus, the first panic comparator  115   a  has a reference voltage V REFP1  of approximately 990 mV (−10 mV), the second panic comparator  115   c  has a reference voltages V REFP3  of approximately 970 mV (−30 mV). For this example the full load required four power stages  25   a ,  25   b ,  25   c , and  25   d  operation is 40 A or 10 A for each of the power stages  25   a ,  25   b ,  25   c , and  25   d.    
     Referring now to  FIG. 7 , prior to the time t 1 , the output current I OUT  flowing through the load is approximately zero amps (0 A). The output voltage V OUT  is to be maintained at the reference voltage level V REF  as generated by the reference voltage generator  10 . The output voltage V OUT  and the output load current I OUT  is maintained by the master power stage  25   a  and the slave power stages  25   b ,  25   c  and  25   d  have been deactivated. The output panic signals V P1  and V P3  of the two panic comparators  115   a  and  115   c  are to a deactivated logic level (0) with the master power stage  25   a  being the single stage activated. 
     At the time t 1 , the load circuit is activated such that the output current I OUT  increases to a higher load current level of approximately 30 A, again, precipitously. The master power stage  25   a  is not able to respond with sufficient current. Thus the output current I OUT  is drawn from the load capacitor C L . Thus causing the output voltage V OUT  to decrease practically instantaneously until it reaches a level less than the first panic reference voltage level V REFP1 . The first panic comparator  115   a  is activated and the panic signal V P1  transits from the deactivated level (0) to the activated level (1). The slave power stage  25   b  is activated such that now the master power stage  25   a  and the slave power stage  25   b  begin to increase the current capacity to slow the decrease in the output voltage V OUT . At the time t 2 , the output voltage V OUT  decreases until it reaches a level less than the second panic reference voltage level V REFP3 . The second panic comparator  115   c  is activated and the panic signal V P3  transits from the deactivated level (0) to the activated level (1). The slave power stages  25   b ,  25   c , and  25   d  are activated such that now master power stage  25   a  and the slave power stages  25   b ,  25   c  and  25   d  begin to increase the current capacity such that the output voltage V OUT  rises toward the reference voltage level V REF  of approximately 1.0V. At the time t 3 , the second panic comparator  115   c  deactivates and the panic signal V P3  transits from the activated level (1) to the deactivated level (0). At the time t 4 , the first panic comparator  115   a  deactivates and the panic signal V P1  transits from the activated level (1) to the deactivated level (0). At the time t 5 , the capacity of the slave power stages  25   b ,  25   c  and  25   d  has not increased sufficiently and the output voltage V OUT  overshoots slightly until the time t 6 . At the time t 6 , the master power stage  25   a  and the three slave power stages  25   b ,  25   c  and  25   d  are now regulating the output voltage V OUT . Once the panic signals V P1  and V P3  are activated at the time t 2 , the power stages  25   a ,  25   b ,  25   c , and  25   d  are activated and the full four phase control of the power stages  25   a ,  25   b ,  25   c , and  25   d  continues regardless of the state of the panic signals V P1  and V P3 . 
     Referring now to  FIG. 8 , prior to the time t 1 , the output current I OUT  flowing through the load is approximately zero amps (0 A). The output voltage V OUT  is to be maintained at the reference voltage level V REF  as generated by the reference voltage generator  10 . The output voltage V OUT  and the output current I OUT  is maintained by the master power stage  25   a  and the slave power stages  25   b ,  25   c , and  25   d  have been deactivated. The output panic signals V P1  and V P3  of the two panic comparators  115   a  and  115   c  are to a deactivated logic level (0) with the master power stage  25   a  being the single stage activated. 
     At the time t 1 , the load circuit is actuated such that the output load current I OUT  increases to a higher load current level of approximately 30 A, again, precipitously. The master power stage  25   a  is not able to respond with sufficient current. Thus the output current I OUT  is drawn from the load capacitor C L . This causes the output voltage V OUT  to decrease practically instantaneously until it reaches a level less than the first panic reference voltage level V REFP1 . The first panic comparator  115   a  is activated and the panic signal V P1  transits from the deactivated level (0) to the activated level (1). The slave power stage  25   b  is activated such that now the master power stage  25   a  and the slave power stage  25   b  begin to increase the current capacity such that the output voltage V OUT  rises toward the reference voltage level V REF  of approximately 1.0V. With the activation of the slave power stage  25   b , the output voltage V OUT  does not decrease until it reaches a level less than the second panic reference voltage level V REFP3 . Consequently, only the master power stage  25   a  and the slave power stage  25   b  remain activated to provide the necessary output current I OUT  to the load  35 . 
     At the time t 2 , the second panic comparator  115   a  deactivates and the panic signal V P1  transits from the activated level (1) to the deactivated level (0). The deactivation of the panic signal V P1  has no impact on the functioning of the power stages  25   a ,  25   b ,  25   c , and  25   d  and they continue to function regardless of the state of the panic signals V P1  and V P3 . At the time t 3 , the two power stages  25   a ,  25   b  are now regulating the output voltage V OUT . 
       FIG. 9 a    is a schematic of a multi-phase switched-mode power supply incorporating a panic comparator  205  embodying the principles of the present disclosure. The switched-mode converter of  FIG. 9 a    is structured as a multiphase buck switched-mode converter. The multiphase buck switched-mode converter has a control circuit  200 , multiple power stages  25   a ,  25   b ,  25   c , . . . ,  25   n , and a filter stage  30 . The multiple power stages  25   a ,  25   b ,  25   c , . . . ,  25   n , and a filter stage  30  are structured and function as described in  FIG. 1 . 
     The commonly connected second terminals of the inductors L 1 , L 2 , . . . , L n  and the first plate of the load capacitor C L  are connected to an input of the control circuit  100  to provide a feedback path  255  for comparing the output voltage V OUT  of the multiphase buck switched-mode converter with a reference voltage level V REF . The reference voltage generator  10  generates the reference voltage level V REF . 
     The control circuit  200  has an error amplifier  15  that receives the feedback voltage V FB  that is returned from output voltage V OUT  and the reference voltage level V REF  from reference voltage generator  10 . The output of the error amplifier  15  is an error voltage  17  that is applied to each of the power stages  25   a ,  25   b ,  25   c , . . . ,  25   n.    
     The current sense signals  41   a , . . . ,  41   n  from each of the power stages  25   a ,  25   b , . . . ,  25   n  are inputs to the total current estimation circuit  40 . The total current estimation circuit  40  is a summation circuit that totals the current sense signals  41   a , . . . ,  41   n  to determine the estimated total current signal I EST . The estimated total current signal I EST  is applied to the phase control circuit  210  and thus to the phase shedding control circuit  225 . As the estimated total current signal I EST  varies, the phase control circuit  225  generates the phase shedding signals  22   a ,  22   b , . . . ,  22   n  for activating and deactivating selected power stages  25   a ,  25   b , . . . ,  25   n  for maintaining the efficiency of the operation of the multi-phase switched-mode power supply. 
     The control circuit  200  has a pulse frequency modulator (PFM) circuit  205  that compares the fed-back output voltage V FB  to pulse frequency reference voltages V PFM . The pulse frequency reference voltage source  240  generates the pulse frequency modulation reference voltage V PFM  that is at an incremental voltage level less than the reference voltage level V REF  as generated by the reference voltage generator  10 . The output  207  of the pulse frequency modulator circuit  205  transfers the pulse frequency activation signal V PFA  to the phase control circuit  210  and thus to the pulse frequency modulation control circuit  220 . The phase control circuit  210  generates the timing signals for activating the master power stage  25   a  to turn on the PMOS transistor M P  of the master power stage  25   a  for a brief period of time to maintain the output voltage V OUT  in the discontinuous conduction mode of operation. 
     The control circuit  200  has a panic comparator circuit  215  that compares the fed-back output voltage V FB  to multiple panic reference voltages V REFP1 , V REFP2 , . . . , V REFPn . The panic reference voltage sources  245   a ,  245   b , . . . ,  245   n  generate the multiple panic reference voltages V REFP1 , V REFP2 , . . . , V REFPn  that are at incremental voltage levels less than the reference voltage level V REF  as generated by the reference voltage generator  10  and the pulse frequency modulation reference voltage V PFM . The panic comparator circuit  215  has multiple panic comparators  235   a , . . . ,  235   n . Each of the multiple panic comparators  235   a , . . . ,  235   n  are connected to one of the incremental multiple panic reference voltages V REFP1 , . . . , V REFPn . The result of the comparison of the fed-back output voltage V FB  and the incremental multiple panic reference voltages V REFP1 , . . . , V REFPn  are the multiple panic signals V P1 , . . . , V Pn  that are the outputs  237   a , . . . ,  237   n  of the multiple panic comparators  235   a , . . . ,  235   n . The multiple panic signals V P1 , . . . , V Pn  are inputs to the phase control circuit  210  and is then transferred to the panic controller circuit  230  for activating all deactivated power stages  25   a ,  25   b , . . . ,  25   n  as required to dynamically respond to transient changes in load current I LOAD  for minimizing undershoot while avoiding overshoot of an output voltage V OUT  of the multi-phase switched-mode converter. 
     The structure of the control  200  is shown with any number of multiple panic comparators  235   a , . . . ,  235   n  and any number of multiple panic reference voltages V REFP1 , . . . , V REFPn . Similarly, the multi-phase switched-mode power supply may have any number of power stages  25   a ,  25   b ,  25   c , . . . ,  25   n  and the filter stage  30  may have any number of inductors L 1 , L 2 , . . . , L n , where each of the inductors L 1 , L 2 , . . . , L n  is connected to one of the power stages  25   a ,  25   b ,  25   c , . . . ,  25   n . The phase control circuit  210  is structured such that the panic control circuit  230  assumes control of the power stages  25   a ,  25   b ,  25   c , . . . ,  25   n  when the first panic comparator  235   a  is activated and forces the multi-phase switched-mode power supply into a continuous conduction mode from the discontinuous conduction mode when the multi-phase switched-mode power supply is operating under the phase frequency control circuit  220 . The panic control circuit  230  determines which of the power stages  25   a ,  25   b ,  25   c , . . . ,  25   n  are activated base on which of the multiple panic comparators  235   a , . . . ,  235   n  have their panic signals V P1 , . . . , V Pn  activated for minimizing undershoot and for preventing the overshoot of the voltage level of the output voltage V OUT , when the large transient becomes larger than any or all of the panic reference voltage levels V REFP1 , . . . , V REFPn . 
       FIG. 9 b    is a schematic of a multi-phase switched-mode power supply incorporating a pulse frequency modulator circuit  205  and two panic comparators  235   a  and  235   b  of  9   a  with four power stages  25   a ,  25   b ,  25   c , and  25   d  embodying the principle of the present disclosure.  FIG. 10  is a plot illustrating the voltage and current waveforms within the multi-phase switched-mode power supply of  FIG. 9 b   . In order to simplify the explanation of the operation of the multi-phase switched-mode power supply of  FIG. 9 a   , the multi-phase switched-mode power supply has a total of four power stages  25   a ,  25   b ,  25   c , and  25   d . One power stage will be designated as the master stage  25   a  and the remaining three power stages  25   b ,  25   c , and  25   d  will be designated as the slave power stages. The multi-phase switched-mode power supply includes the pulse frequency modulation comparator  205  and two panic comparators  235   a  and  235   b . The pulse frequency modulation comparator  205  is connected as described above to compare the fed back voltage V FB  that is provided from the connection  255  from the output of the multi-phase switched-mode power supply. Two panic reference voltage sources  245   a  and  245   b  are connected to the two panic comparators  235   a  and  235   b  to provide the two panic reference voltages V REFP1  and V REFP2 . The two panic reference voltages V REFP1  and V REFP2  are at voltage level increments of 10 mv less than the pulse frequency modulation reference voltage V PFM  that is at an incremental voltage level less than the reference voltage level V REF  as generated by the reference voltage generator  10 . Thus, the pulse frequency modulation comparator  205  has a pulse frequency reference voltage V PFM  of approximately 990 mV (−10 mV), the first panic comparator  235   a  has a reference voltages V REFP1  of approximately 980 mV (−20 mV), and the second panic comparator  235   b  has a reference voltages V REFP2  of approximately 970 mV (−30 mV). For this example the full load required full four power stage  25   a ,  25   b ,  25   c , . . . ,  25   n  operation is 30 A. 
     Referring now to  FIGS. 9 b    and  10 , prior to the time t 1 , the output current I OUT  flowing through the load is approximately 0.1 A. The output voltage V OUT  is decaying from the reference voltage level V REF . The output voltage V OUT  and the output current I OUT  is maintained by the master power stage  25   a  and the slave power stages  25   b ,  25   c , and  25   d  have been deactivated. The output panic signals V P1  and V P2  of the two panic comparators  235   a  and  235   b  are to a deactivated logic level (0) with the master power stage  25   a  being the single stage activated periodically in a discontinuous conduction mode of operation. 
     At the time t 1 , the output voltage V OUT  has decayed to the level of the pulse frequency reference voltage V PFM  and the pulse frequency modulation comparator  205  is activated to generate a single pulse of the pulse frequency activation signal V PFA  to cause the master power stage  25   a  to turn on the on the PMOS transistor M P  for a brief period of time to maintain the output voltage V OUT  in the discontinuous conduction mode of operation. The output voltage V OUT  rises to the reference voltage level V REF . The PMOS transistor M P  turns off and the output voltage V OUT  decays to the level of the pulse frequency reference voltage V PFM  at the time t 2 . At the time t 2 , the pulse frequency modulation comparator  205  is activated to generate a single pulse of the pulse frequency activation signal V PFA  to cause the master power stage  25   a  to turn on the on the PMOS transistor M P  for a brief period of time to maintain the output voltage V OUT  in the discontinuous conduction mode of operation. The output voltage V OUT  rises to the reference voltage level V REF . The PMOS transistor M P  turns off and the output voltage V OUT  begins to decay until the time t 3 . 
     At the time t 3 , the output current I OUT  increases precipitously from the 0.1 A level to the 30 A level. The master power stage  25   a  is not able to respond with sufficient current. Thus the output current I OUT  is drawn from the load capacitor C L . This causes the output voltage V OUT  to decrease practically instantaneously until it reaches a level less than the pulse frequency reference voltage V PFM  and the first panic reference voltage level V REFP1 . The first panic reference voltage level V REFP1  is activated to override the operation of the pulse frequency activation signal V PFA  and to turn on the master power stage  25   a . At almost the time t 3  the first panic comparator  235   a  is activated and the panic signal V P1  transits from the deactivated level (0) to the activated level (1). The first slave power stage  25   b  turns on its PMOS transistor M P . 
     The master power stage  25   a  has increased the current capacity for the output current I OUT  to cause output voltage V OUT  to slow its decrease until the time t 4 . The second panic comparator  235   a  is then activated and the panic signal V P2  transits from the deactivated level (0) to the activated level (1). The slave power stages  25   c , and  25   d  turn on their PMOS transistors M P . The master power stage  25   a  and the slave power stages  25   b ,  25   c , and  25   d  are all activated and begin to increase the current capacity such that the output voltage V OUT  rises toward the reference voltage level V REF  of approximately 1.0V. At the time t 5 , the second panic comparator  235   n  deactivates and the panic signal V P2  transits from the activated level (1) to the deactivated level (0). At the time t 6 , the first panic comparator  235   a  deactivates and the panic signal V P1  transits from the activated level (1) to the deactivated level (0). And at the time t 7 , the pulse frequency modulation comparator  205  deactivates and the pulse frequency activation signal V PFA  transits from the activated level (1) to the deactivated level (0). The deactivation of the panic signals V P1  and V P2  and the pulse frequency activation signal V PFA  have no impact on the functioning of the power stages  25   a ,  25   b ,  25   c , and  25   d  and they continue to function regardless of the state of the panic signals V P1  and V P2  and the pulse frequency activation signal V PFA . At the time T 8 , the four power stage  25   a ,  25   b ,  25   c , and  25   d  are now regulating the output voltage V OUT  at the voltage controlled by the reference voltage level V REF . 
     While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure.