Abstract:
Systems and methods for providing a rapid switchable high voltage power transistor driver with a constant gate-source control voltage have been disclosed. A low voltage control stage keeps the gate-source voltage constant in spite of temperature and process variations. A high voltage supply voltage can vary between about 5.5 Volts and about 40 Volts. The circuit allows a high switching frequency of e.g. 1 MHz and minimizes static power dissipation.

Description:
BACKGROUND 
     (1) Field of the Invention 
     This invention relates generally to transistor drivers and relates more specifically to a driver for a high voltage P-MOS power transistor having accurate control voltage and faster switching. 
     (2) Description of the Prior Art 
     For applications as e.g. automotive applications supply voltages up to 40 Volts and even higher are often required. High-Voltage CMOS devices are usually based on a 5V technology with an extended drain region to reach up to e.g. 40V drain-source breakdown capability. As the source side of the High-Voltage CMOS devices is the same as it is for 5-V CMOS devices, its bulk-source voltage, Vbs, as well as its gate-source voltage, Vgs, are limited to 5V. Static power dissipation of the high voltage (HV) transistors, achieving accurate control voltage of e.g. 5 Volts and high switching speed are key problems with high voltage CMOS devices, which should be overcome. 
     It is a challenge for engineers designing driver circuits for high voltage applications, i.e. supply voltages in the order of magnitude of 40 V to overcome above problems. 
     (U.S. Pat. No. 6,507,226 to Swonger et al.) discloses a circuit and method translating a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver adjacent thereto. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch. 
     (U.S. Pat. No. 5,325,258 to Choi et al.) discloses a circuit and method for driving a power transistor device. The circuit for driving a power transistor device has a driver having an input and an output, the output coupled to a control input of the power transistor device and the input coupled to a primary control voltage source for driving the power transistor device. A current sensing device is coupled to the power transistor device for providing a signal proportional to the current in the power transistor device. An amplifier is coupled to the current sensing device for providing a substantially linear control signal proportional to the current in the power transistor device, the linear control signal being provided to the input of the driver as a secondary drive signal for driving the power transistor device when a current level in the power transistor device greater than a threshold level is detected. A detector is provided for detecting when the current in the power transistor device is greater than the threshold level. The detector is coupled to the current sensing device and to a reference level source, and provides an overcurrent signal to the driver for switching the driver from being driven by the primary control voltage source to the secondary drive signal. The secondary drive signal drives the driver so as to reduce the current level in the power transistor device. The driven power transistor device is preferably a power MOSFET or IGBT. 
     (U.S. Pat. No. 4,937,477 to Tsoi et al.) proposes a high-voltage level translator circuit that is suitable for monolithic integration. The level translator circuit comprises serially connected current sources suitably ratioed so that the gating on of one current source causes a limited voltage rise across the other current source, which is ungated. The circuit is suitable for integration in a junction-isolated monolithic pseudo-complementary CMOS format. 
     SUMMARY 
     A principal object of the present invention is to achieve an accurate control voltage for a high voltage power transistor. 
     A further object of the invention is to establish an accurate control voltage independent of temperature and process variations. 
     A further object of the invention is to minimize static power dissipation of a high voltage power transistor. 
     Another object of the invention is to enhance switching speed of the high voltage power transistor. 
     In accordance with the objects of this invention a method to provide a fast switchable high voltage power transistor driver circuit has been achieved. The method invented comprises, firstly, the following steps: (1) providing a circuit comprising a port for a high voltage supply voltage, a port for a low voltage supply voltage, an input stage comprising a high voltage power transistor, an output port, and a port for a digital input signal, and a control stage to achieve a constant gate-source voltage of the high voltage power transistor, and (2) limiting the gate-source voltage of the high voltage power transistor using a voltage drop of a first reference current across a resistive load if the digital input signal is high. Furthermore the method invented comprises the steps: (3) pulling the gate of the high voltage power transistor to the level of the high voltage supply voltage if the digital input signal is low, and (4) generating a second reference current, which is controlled by a reference voltage via a differential amplifier, wherein the second reference current is mirrored to the first reference current in order to establish an accurate gate source voltage of the high voltage. 
     In accordance with the objects of this invention a fast switchable high voltage power transistor driver circuit has been achieved. The driver circuit invented comprises, firstly an input stage comprising: a port for a high voltage supply voltage, a port for a digital input signal, and a high voltage power transistor connected between said high voltage supply port and an output port of the circuit. Furthermore the input stage comprises a resistive load connected between a gate of the high voltage power transistor and the high voltage supply port, a high voltage transistor being connected between the gate of the high voltage power transistor and a low voltage transistor, and said low voltage transistor connected between the high voltage transistor and ground wherein the gate of the low voltage transistor is connected to a gate of a fourth transistor of a control stage. Furthermore the driver circuit comprises a control stage comprising: a port of a low voltage supply voltage, a differential amplifier having inputs and an output, wherein a first input is connected to a port of a reference voltage, a second input is a voltage of a first terminal of a first means of resistance, and the output is connected to a gate of a first transistor, and said means of resistance, wherein the first terminal is connected to the first transistor and a second terminal is connected to ground. Furthermore the control stage comprises said first transistor connected between said means of resistance and a second transistor, said second transistor connected between said first transistor and the port for low supply voltage, wherein the second transistor is forming a first current mirror with a third transistor, said third transistor connected between the port for the low voltage supply voltage and the fourth transistor, and said fourth transistor connected between the third transistor and ground, wherein the fourth transistor is forming a second current mirror with said low voltage transistor of the input stage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the accompanying drawings forming a material part of this description, there is shown: 
         FIG. 1  shows a schematic of the principles of the invented circuit driving a HV P-MOS power transistor. 
         FIG. 2  depicts the transient response of the circuit of  FIG. 1  with V DDB =25V and Cload=1 nF. 
         FIG. 3  shows a complete circuit for driving an HV-PMOS power transistor. 
         FIG. 4  shows the transient responses of the circuit of  FIG. 3  with VDDB=25V, and Cload=1 nF, and operating frequency of 50 kHz. 
         FIG. 5  shows the transient response of the circuit shown in  FIG. 3  with VDDB=25V, and operating frequency of 1 MHz. 
         FIG. 6  illustrates a flowchart of a method invented to achieve a fast switchable high voltage power transistor driver circuit. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Methods and circuits to achieve an accurate control voltage of a high voltage power transistor combined with a rapid switching-on and switching-off operation of a high voltage power transistor are disclosed. 
       FIG. 1  shows principles of a preferred embodiment of the present invention, i.e. a schematic of a circuit driving a HV P-MOS power transistor (HP 1 ). It should be noted that the invention could be applied to other power transistors with drain-source voltage capability higher than 5V and gate-source voltage limited to 5V. 
     The circuit shown in  FIG. 1  to drive the HV P-MOS power transistor, HP 1 , is supplied directly by power supply, V DDB , with an input comprised of HV N-MOS transistor, HN 1 , directly controlled by 5V digital signal. In the preferred embodiment the power supply voltage V DDB  can vary between 5.5 V and 40 V. Other ranges of voltages are possible as well, depending on e.g. the type of high voltage power transistor used. The HV power transistors deployed have an extended drain region to reach up to 40 V drain source breakdown capability. As the source side of the High-Voltage CMOS devices is the same as it is for 5-V CMOS devices, its bulk-source voltage, Vbs, as well as its gate-source voltage, Vgs, are limited to 5V. 
     The input stage has a resistive load of R 2  (e.g. 50 kΩ) that pulls the gate of HP 1  to V DDB , if the digital input signal ON is low (ON=0V). The resistive load, R 2 , together with the controlled input stage reference-current I REF  serves as gate source limitation of I REF *R 2  when the digital input signal ON is high (ON=5V). 
     However the gate-source limitation of I REF *R 2  varies with current and resistor temperature/process changes, which needs to be cancelled. The circuit that cancels the variation uses an amplifier  1  to mirror a fixed voltage, V REF , across a resistor R 1 , which is matched to that resistive load of R 2  according to the equation R 1 =R 2 /K., wherein the factor K corresponds to the equation K=V DDL /V REF  or, according to the values of voltages used in the preferred embodiment illustrated in  FIG. 1 , K=5V/1.65V=3.03. It should be understood that these values are examples only and that other values of K and voltages could be applied as well. These values depend also on the types of high voltage transistors used. 
     The accurate matching of 5V MOS devices allows an accurate current ratio to be generated. Using the current ratios CM 1 =P 3 /P 2 =1 of the 5V P-MOS mirror, comprising P-MOS transistors  2  and  3  (P 2  is the gate-drain connected P-MOS transistor) and CM 2 =N 1 /N 2 =1 of the 5V N-MOS mirror, comprising transistors N 1   5  and N 2   4 , which is a gate-drain connected N-MOS transistor, an output current is generated, resulting in an accurate voltage limitation of I REF *R 2 =(V REF / R 1 )*R 2 =K*V REF =5V. More generally formulated K=V DDL /V REF . 
     It should be noted that alternatively other current mirror ratios than 1:1 can be used as well, i.e. CM 1  and CM 2  result in an accurate voltage limitation of I REF *R 2 =(V REF /R 1 )*CM 1 *CM 2 *R 2 =CM 1 *CM 2 *(R 2 /R 1 )*V REF =V DDL =5V, and K=V DDL /V REF =CM 1 *CM 2 *(R 2 /R 1 ). 
     The HV-NMOS device HN 1 , also isolates the 5V-NMOS device N 1 , from the high voltage domain. 
     The output swing of the voltage V C  at the gate of the HV P-MOS transistor HP 1  is between V DDB  and V DDB −5V, and the output swing of voltage V H  is between V DDB  and 0V as shown in  FIG. 2 . 
       FIG. 2  illustrates the transient response of the circuit invented shown in  FIG. 1  with voltage V DDB =25V and C LOAD =1 nF. The load capacitance C LOAD  is limited by the slew rate from the output swing of voltage V H  of the HV P-MOS transistor HP 1  as
 
τ LOAD   =R   DSON     —     HP1   *C   LOAD  
 
for given requirement. The switching frequency is however only limited by the slew rate from the input swing of voltage V C  of the HV P-MOS transistor HP 1  as τ 1 =R 2 *C GS     —     HP1  in  FIG. 1 .
 
     Curve  20  shows the digital input signal ON. Curve  21  illustrates the drain voltage VH of the high voltage transistor HP 1 , curve  22  shows the voltage Vc at the gate of the high voltage transistor HP 1 , and curve  23  shows the power dissipation of the high voltage transistor HP 1 . Curve  23  shows the power dissipation in watt (=|I CTRL *(5V−V C (t,τ 1 )|) to turn-on and turn-off of the HP 1  in  FIG. 1 . 
       FIG. 2  demonstrates that the circuit invented provides a reliable solution to drive the HV P-MOS power transistor HP 1  with accurate gate-source control voltage Vc  22 . Furthermore  FIG. 2  shows the power dissipation  23  of the power transistor HP 1 , the output voltage VH  22  responding to the digital input signal ON  20 , which is driven with a frequency of 50 kHz. On the other hand, a rapid switchable on/off is expected to avoid drawing static power. 
     Because of the parasitic capacitance across the gate-source of the HP 1  due to its large sizing (W×L=16,000×2.7), its control voltage Vc  22  changes with a time constant, τ 1 =R 2 *C GS     —   HP 1 , from V DDB  to V DDB −5V, as well as from V DDB −5V to V DDB ., wherein C GS  is the gate-source capacitance of transistor HP 1  This limits the switching speed and makes larger static power loss during on/off phases. 
       FIG. 3  shows a complete circuit for driving HV-PMOS power transistor HP 1 . In order to simultaneously have a rapid switching operation, a new circuit structure is proposed in  FIG. 3 . The highlighted control switches are added between the gate of HP 1 , V C , and the power supply V DDB . To make switching on/off faster, two smaller sizing HV P-MOS devices, HP 2  and HP 3  (e.g. having a size of =100×2.7), are added. The control circuit of HP 2  and of HP 3  are identical as of the HP 1 , but they share the reference current I REF  and HP 3  is controlled by an inverted 5V digital signal inverted by inverter  30 . The resistors R 3  and R 4 , each connecting a gate of HP 3  or correspondently of HP 4  with the supply voltage V DDB , have the same resistance as resistor R 2  connecting a gate of HP 1  with the supply voltage V DDB , as shown already in  FIG. 1 . In the following the operation of the circuit of  FIG. 3  is described in two states, namely if the digital input signal ON is 5V and if the digital input signal ON is 0V. 
     When signal ON is 5V, the gate voltage of HP 2  V G     —   HP 2 , charges from V DDB  to V DDB −5V. The source voltage of HP 2  V S     —   HP 2 , which is above a diode threshold voltage higher than its gate voltage, charges from V DDB  to V DDB −V G     —   HP 2 +|V GS     —   HP 2 |˜V DDB −5V+0.7V=V DDB −4.3V having a time constant of τ 2 =R 3 *C GS     —   HP 2 . Therefore the control voltage, V C , settles now from V DDB  to V DDB −4.3V with τ 2 =R 3 *C GS     —   HP 2 , and then settles from V DDB −4.3V to V DDB −5V with time constant τ 1 =R 2 *C GS     —   HP 1 . Since the parasitic capacitance at the gate of HP 2  is much smaller than that at the gate of HP 1  resulting time constant τ 2 &lt;&lt;τ 1 ; thus a faster switching-on is achieved. 
     When signal ON is 0V and the inverted digital signal at the output of inverter  30  is 5V), the gate voltage of transistor HP 3 , V G     —   HP 3 , charges from V DDB  to V DDB −5V and closes its drain-source voltage with an on-resistance of R DSON     —   HP 3  above 200Ω. Therefore the control voltage V C  discharges now from V DDB −5V to V DDB  with τ 3 =R DSON     —   HP 3 *C GS     —   HP 1  rather than with τ 1 =R 2 *C GS     —   HP 1 ; thus a faster switching-off is achieved. 
       FIG. 4  shows the transient responses of the circuit of  FIG. 3  with supply voltage VDDB=25V, and Cload=1 nF.  FIG. 4  demonstrates that the circuit of  FIG. 3  provides a significant improved solution to drive the HV P-MOS power transistor HP 1  compared to the circuit shown in  FIG. 1 . The digital input signal ON, shown in  FIG. 4  is driven with the same frequency of 50 kHz as illustrated in the transient response charts of  FIG. 2 . 
     Comparing the response to the digital input signal ON  40  of the power dissipation  43  of the power transistor HP 1 , of the control voltage VC  42 , and of the output voltage VH  42  shown in  FIG. 4  with the correspondent curves of  FIG. 2  it is clearly demonstrated that the circuit of  FIG. 3  has less power dissipation and better time constants for V C  and V H  as outlined above. 
     Turning to  FIG. 5  now, the frequency of the digital input signal ON  50  of the circuit shown in  FIG. 3  has been increased from 50 kHz to 1 MHz.  FIG. 5  demonstrates that the circuit shown in  FIG. 3  can be operated with a frequency of 1 MHz. Moreover the power dissipation of transistor HP 1  has been further improved since the dissipation is only produced by the turn-on and turn-off of the transistor HP 1 , and is independent from the switching frequency as long as the switching period is larger than t ON +t OFF . 
       FIG. 6  illustrates a flowchart of a method invented to achieve a fast switchable high voltage power transistor driver circuit. 
     Step  60  of the method of  FIG. 6  illustrates the provision of a circuit comprising a port for a high voltage supply voltage, a port for a low voltage supply voltage, an input stage comprising a high voltage power transistor, an output port, and a port for a digital input signal, and a control stage to achieve a constant gate-source voltage of the high voltage power transistor. Step  61  limiting the gate-source voltage of the high voltage power transistor using a voltage drop of a first reference current across a resistive load if the digital input signal is high. Step  62  describes pulling the gate of the high voltage power transistor to the level of the high voltage supply voltage if the digital input signal is low and step  63  teaches generating a second reference current, which is controlled by a reference voltage via a differential amplifier, wherein the second reference current is mirrored to the first reference current in order to establish an accurate gate source voltage of the high voltage. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.