Abstract:
A design method of a semiconductor device that performs self-diagnosis by comparing an expected value with a signal that is obtained by applying a random pattern to a logic circuit to be tested, and by compressing an output of the logic circuit, wherein each bit of all or part of bits that make up the expected value is provided with one of a first cell that outputs an input signal A and a second cell that outputs an input signal B, corresponding to the expected value, thereby semiconductor design efficiency is enhanced.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention generally relates to a semiconductor device and testing method thereof, and specifically relates to a technology of self-diagnostics of the semiconductor device.  
           [0003]    2. Description of the Related Art  
           [0004]    BIST (Built In Self Test) has been known as a testing method of a semiconductor device, which is a testing method wherein a semiconductor device itself performs self-diagnosis. In order to realize BIST, a random number generator, a compressor, and an expected-value generation circuit are installed in the semiconductor device.  
           [0005]    As test data, a random pattern generated by the random number generator is supplied to a plurality of scanning chains of a user logic (for example, PLA: Programmable Logic Array), which is a logic circuit to be tested such that all the circuit elements in the user logic (for example, flip-flop) are tested. A flip-flop latches the test data synchronously with a test clock supplied. Data output through the scanning chains are compressed by the compressor. The compressed data are compared with an expected value generated by the expected-value generating circuit. A comparison result is output as a test result.  
           [0006]    Thus, the obtained compressed data serve as a pattern unique to a circuit configuration of the user logic. Therefore, the user logic is verifiable by comparing the obtained compressed data with the expected value. Then, the circuit configuration of the user logic is modified if needed.  
           [0007]    The BIST is disclosed by Japanese Patent 1-277779, for example.  
           [0008]    Change of the circuit configuration of the user logic also changes the expected value. That is, a circuit configuration of the expected-value generating circuit has to be changed such that an expected value corresponding to the user logic after the user logic is changed can be generated. {Conventionally, the change in the expected-value generating circuit is implemented by re-wiring, which is time consuming and, therefore, expensive.} It is desired that test efficiency is improved by facilitating the change of the expected-value generating circuit.  
           [0009]    Therefore, the present invention aims at raising the test efficiency, hence the design efficiency, solving the above problem of the conventional technology by facilitating a change of the expected-value generating circuit.  
         SUMMARY OF THE INVENTION  
         [0010]    It is a general object of the present invention to provide a semiconductor device and a design method that substantially obviate one or more of the problems caused by the limitations and disadvantages of the related art.  
           [0011]    Features and advantages of the present invention will be set forth in the description that follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor device and a design method particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.  
           [0012]    To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor device that includes an expected value generating circuit, change of which is facilitated, and a design method of the semiconductor device.  
           [0013]    The design method includes testing a semiconductor device, wherein a random pattern is supplied to a logic circuit to be tested, output from the logic circuit is compressed, and the compressed data are compared with an expected value generated by an expected-value generating circuit. Here, one of a first cell that outputs an input A and a second cell that outputs an input B is provided, according to the expected value, to each of all or part of bits that make up the expected value.  
           [0014]    When the expected value should be changed, a cell corresponding to a bit to be changed is replaced. If a cell that presently has a first cell is to be changed, the cell is replaced with a second cell, and vice versa. In this manner, re-wiring processing that is conventionally required is no longer necessary. Therefore, the present invention enhances design efficiency, with the expected-value generating circuit being changed easily in a short period time.  
           [0015]    In a semiconductor device, wherein a random pattern is supplied to a logic circuit to be tested, output from the logic circuit is compressed, and the compressed data are compared with an expected value generated by an expected-value generating circuit, the expected-value generation circuit of the present invention provides one of a cell that outputs an input A and a cell that outputs an input B to each bit of all or part of bits that make up the expected value, according to the expected value.  
           [0016]    Alternatively, in a semiconductor device, wherein a random pattern is supplied to a logic circuit to be tested, output from the logic circuit is compressed, and the compressed data are compared with an expected value generated by an expected-value generating circuit, the expected-value generation circuit of the present invention provides both of a cell that outputs an input A and a cell that outputs an input B to each bit of all or part of bits that make up the expected value. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 is a block diagram showing a configuration of a semiconductor device of the embodiment of the present invention;  
         [0018]    [0018]FIG. 2 is a block diagram showing a configuration example of a compressor shown in FIG. 1;  
         [0019]    [0019]FIG. 3 is a block diagram showing a configuration example of a conventional expected-value generation circuit;  
         [0020]    [0020]FIG. 4(A) shows a configuration of a cell that outputs an input A and a cell that outputs an input B;  
         [0021]    [0021]FIG. 4(B) shows an example of how the configuration in FIG. 4(A) is implemented;  
         [0022]    [0022]FIG. 4(C) shows how connections are made in the expected-value generating circuit;  
         [0023]    [0023]FIG. 4(D) shows an example of how the connections in FIG. 4(C) are implemented;  
         [0024]    [0024]FIG. 5(A) is a flowchart of a semiconductor device design method of the present invention; and  
         [0025]    [0025]FIG. 5(B) is a flowchart of a semiconductor device design method of a conventional technology. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]    In the following, embodiments of the present invention will be described with reference to the accompanying drawings.  
         [0027]    [0027]FIG. 1 is a block diagram of a semiconductor device  100  that includes a self-diagnosing function by BIST.  
         [0028]    The semiconductor device  100  includes a logic circuit  10  that is a testing target, a random number generator  12 , a compressor  14 , and an expected-value generation circuit  16 . A random pattern generated by the random number generator  12  is provided to the logic circuit  10 , which is the testing target. Data output from the logic circuit  10  are compressed by the compressor  14 . Then, the compressed data are compared with an expected-value generated by the expected-value generating circuit  16 . Thus, the semiconductor device  100  has a function of comparing the compressed data output with the expected value. Here, a block that shows the semiconductor device  100  is equivalent to a semiconductor chip.  
         [0029]    The logic circuit  10  is the testing target, and is a functional unit by itself. The logic circuit  10  is structured by, e.g., a PLA that is a logic circuit programmed according to a user&#39;s specification. The logic circuit  10  has n scanning chains  20  (n is an arbitrary integer). Each of the scanning chains  20  includes a plurality of circuit elements  18  that are cascade-connected. Each of the circuit elements  18  is a logical element, such as a flip-flop. In the following explanation, each of the circuit elements  18  is explained as a flip-flop. To a clock terminal of each of flip-flops  18 , a test clock CLK is supplied. The test clock may be a clock supplied from an external source, for example, when testing. The test clock may be a clock generated by an internal timing generator of the semiconductor device  100 .  
         [0030]    The random number generator  12  is connected on an input side of the scanning chain  20 . The random number generator  12  generates a random pattern. Each of the flip-flops  18  latches the random pattern input synchronously with the test clock, and outputs to a flip-flop  18  of the next stage. Thus, the data finally obtained through all the flip-flops  18  of the scanning chain  20  is output to the compressor  14 . The compressor  14  compares the data received from the logic circuit  10  with the expected value generated by the expected-value generating circuit  16 .  
         [0031]    [0031]FIG. 2 is a block diagram showing a configuration example of the compressor  14 . The compressor  14  has n input terminals  28   1  through  28   n  corresponding to the n scanning chains  20 . In FIG. 2, only three input terminals  28   2 ,  28   3 , and  28   4  are shown for convenience. Each of the input terminals  28   1  through  28   n  is connected to an input terminal of each of compression logic units  22   1  through  22   n . In FIG. 2, only three compression logic units  22   2 ,  22   3 , and  22   4  are shown for convenience. Each of the compression logic units  22   1  through  22   n  is connected to the compression logic of a preceding stage via flip-flops  24   1 - 24   n . In FIG. 2, only three flip-flops  24   2 ,  24   3 , and  24   4  are shown for convenience. For example, the compression logic  22   3  is connected with the compression logic  22   2  of the preceding stage through the flip-flop  24   2 , and is connected to the latter compression logic  22   4  through the flip-flop  24   3 .  
         [0032]    Each of the compression logic units  22   1 - 22   n  compresses data from a corresponding scanning chain  20  and data output from a compression logic  22  of a preceding stage (hereafter, a reference sign without a suffix means one of the corresponding units, for example, a compression logic unit  22  means one of the compression logic units  22   1 - 22   n ), using a predetermined logic, outputs to a flip-flop  24  located at an output stage. Each of the flip-flops  24   1 - 24   n  outputs and inputs data synchronously with the test clock CLK.  
         [0033]    Output of each of the flip-flops  24   1 - 24   n  is connected to an input terminal of each of comparators  26   1 - 26   n , respectively, while connected with an input of the compression logic  22  of the next stage. In FIG. 2, only three comparators  26   2 ,  26   3 , and  26   4  are shown for convenience. Another input terminal of each of the comparators  26   1 - 26   n  inputs data ED 1 -ED n , respectively, which are expected values generated by the expected-value generation circuit  16 . In FIG. 2, only three expected-values ED 2 , ED 3 , and ED 4  are shown for convenience. For example, a comparator  26   2  compares the expected-value ED2 with the output data of the flip-flop  24   2 . Comparison results of the comparators  26   1 - 26   n  are output through output terminals  30   1 - 30   n , respectively. Although these output terminals  30   1 - 30   n  are output terminals of the compressor  14 , the output terminals  30   1 - 30   n  may be made terminals of the semiconductor device  100 , serving an external connection.  
         [0034]    [0034]FIG. 3 shows a configuration example of a conventional expected-value generation circuit  16 . The configuration example of FIG. 3 belongs to a technology related to the present invention, and illustrates a preceding technology. An expected-value generation circuit  16  of the present invention is shown in FIG. 4, and described later.  
         [0035]    The conventional configuration shown in FIG. 3 includes a “1” generator  32 , a “0” generator  34 , and a wiring section  36 . The “1” generator  32  generates a bit “1.” The “0” generator  34  generates a bit “0.” The wiring section  36  includes wire-connections which set one of a bit “1” and a bit “0” to each of expected values ED1-EDn. In the example, the wiring section  36  connects the “1” generator  32  such that the expected-values ED2, ED3, and EDn carry “1”, and connects the “0” generator  34  such that the expected values ED1 and ED4 carry “0”. Here in FIG. 3, only the expected values ED1-ED4 and EDn are shown for convenience. Thus, the generated expected values ED1-EDn are output to corresponding comparators  26   1 - 26   n , respectively, as shown in FIG. 2.  
         [0036]    If the logic circuit  10  is changed, it is necessary also to change the expected values ED1-EDn. In order to change the expected values, re-wiring of the wiring section  36  is required. For example, in order to change the expected values ED2 and ED3 to “0” from “1”, it is necessary to remove present wiring to the “1” generator  32 , and to prepare new wiring to the “0” generator  34 . It is necessary to ensure that electrical properties, such as delay, do not change in the re-wiring.  
         [0037]    [0037]FIG. 4(C) and FIG. 4(D) show an example of an expected-value generation circuit  16  that avoids a complicated process of the re-wiring, which is mentioned above. Connections of the expected-value generation circuit  16  showed in FIG. 4(C) are implemented by a circuit configuration shown in FIG. 4(D). The expected-value generation circuit  16  shown in FIG. 4(D) includes a “1” generator  32 , a “0”; generator  34 , and a selection circuit  58 . In the selection circuit  58 , one of two cells  36 A and  36 B is provided to each of the expected values ED1-EDn. Each cell, being one of  36 A and  36 B, is connected to both the “1” generator  32  and the “0” generator  34 .  
         [0038]    [0038]FIG. 4(A) shows a configuration of the cells  36 A and  36 B. The cell A receives signals A and B and outputs the signal A as an output X. The cell B receives the signals A and B and outputs the signal B as an output X. Here, the signals A and B are equivalent to the data “1” generated by the “1” generator  32  of FIG. 4(D) and the “0” generated by the “0” generator  34  of FIG. 4(D), respectively.  
         [0039]    Therefore, in FIG. 4(D), the expected values ED2, ED3, and EDn are the same as the signal A (for example, “1”), and the expected values ED1 and ED4 are the same as the signal B (for example,  
         [0040]    The cells  36 A and  36 B are in the same dimensions and have the same capacity (capacitance). An example of circuit configuration of the cells  36 A and  36 B is shown in FIG. 4(B). The cell  36 A has input terminals  42  and  44 , an output terminal  46 , and two buffers  38  and  40 . The two buffers  38  and  40  are connected in series between the input terminal  42  and the output terminal  46 . The input terminal  44  is open. When the signals A and B are received at the input terminals  42  and  44 , respectively, the signal A is output as an output X from the output terminal  46 .  
         [0041]    The cell  36 B has input terminals  52  and  54 , and an output terminal  56 , and two buffers  48  and  50 . The two buffers  48  and  50  are connected in series between the input terminal  54  and the output terminal  56 . The input terminal  52  is open. When the signals A and B are received at the input terminals  52  and  54 , respectively, the signal B is output as an output X from the output terminal  56 .  
         [0042]    The buffers  38 ,  40 ,  48 , and  50  are in the same dimensions and have the same circuit configuration. Further, wire length between the input terminal  42  and the output terminal  46 , and wire length between the input terminal  54  and the output terminal  56  are the same. That is, the cells  36 A and  36 B have the same dimensions and the same capacity (capacitance).  
         [0043]    Therefore, when the expected value is changed, cells  36 A and  36 B of the selection circuit  58  of FIG. 4(D) are replaced as required, causing no change in electrical properties, such as delay. For example, if the expected value data ED2 of FIG. 4(D) is to be changed from “1” to “0”, the cell  36 A is replaced by a cell  36 B. Therefore, the necessity of performing complicated re-wiring as described with reference to FIG. 3 is dispensed with, and in this manner, change of the expected-value generating circuit  16 , i.e., change of an expected value, can be made easily in a short period of time.  
         [0044]    [0044]FIG. 5(A) is a flowchart that shows a design method of a semiconductor device of an embodiment of the present invention. FIG. 5(B) is a flowchart of a conventional design method of a semiconductor device. Specifically, FIG. 5(A) shows the design method using the expected-value generation circuit  16  showed in FIG. 4, and FIG. 5(B) shows the design method using the expected-value generation circuit  16  showed in FIG. 3.  
         [0045]    At step S 11 , the random number generator  12  and the expected-value generation circuit  16  are designed to the logic circuit  10 , all of which are shown in FIG. 1. This design process sets up such that data obtained by supplying a random pattern generated by the random number generator  12  to the logic circuit  10 , which is an internal circuit to be tested, is first compressed by the compressor  14 , and then, the compressed data are compared with the expected value generated by the expected-value generation circuit  16 .  
         [0046]    Here, a system design is assumed to have been performed prior to step S 11 . The system design includes a function design, a function description, function verification, logic synthesis, logic verification, and so on.  
         [0047]    Step S 12  is a layout verification process in which the layout of each circuit included in the semiconductor device  100  shown in FIG. 1 is verified. In this process, the layout of the scanning chain  20  of the logic circuit  10  is also verified, and a layout change of changing an arrangement of the flip-flops  18  in the scanning chain  20  is made if needed.  
         [0048]    Step S 13  is a correction process of the expected-value generation circuit  16 . If the logic circuit  10  and particularly the scan chain  20  are changed, it is also necessary to change the expected value of the expected-value generation circuit  16 . Change of expected value is performed by identifying one or more bits of the expected values ED0-EDn, which should be changed, and replacing corresponding cells with another type from the present type. The expected value is changed by this cell replacement process simply and certainly, without changing circuit properties.  
         [0049]    On the other hand, in the conventional process of FIG. 5(B), after identifying one or more bits of the expected values ED0-EDn that should be changed at step S 13 , a complicated re-wiring process should take place at step S 16 . By the design method of FIG. 5(A) according to the present invention, the re-wiring process of step S 16  is unnecessary.  
         [0050]    Step S 14 , following step S 13  of FIG. 5(A) and following step S 16  of FIG. 5(B), is timing verification processing. Step S 14  verifies whether the logic circuit  10  operates at suitable timing. For example, a circuit simulation is used for this verification.  
         [0051]    After step S 14 , an electric rule verification process is performed at step S 15 . Extraction of a parasitic element and the like are performed from a mask figure, and whether the circuit realized by the mask figure fulfills a desired electrical property is checked. This check is not performed on the entire semiconductor device  100 , but critical circuit portions are checked.  
         [0052]    The semiconductor device  100  is manufactured through a design procedure such as above. The flowchart shown in FIG. 5(A) can be called a part of the manufacturing method of the semiconductor device  100  according to the present invention. Since the semiconductor device  100  manufactured through such a procedure can cut down the cost and time concerning testing, it is advantageous in cost.  
         [0053]    As explained above, according to this invention, design efficiency can be raised because an expected-value generating circuit can be changed easily in a short period of time.  
         [0054]    Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.  
         [0055]    The present application is based on Japanese priority application No. 2001-298532 filed on Sep. 27, 2001 with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.