Abstract:
A current or voltage generator is integrated onto a silicon wafer and may include a first element including a first NMOS transistor having its source connected to ground through an electrical resistance, a second element including a second NMOS transistor having its source connected to ground, and a bias circuit for the first and second elements. The second element may include a voltage divider. The gate of the second NMOS transistor may be connected to a dividing node of the voltage divider, and the anode of the voltage divider may be connected to the gate of the first NMOS transistor. Both elements may be biased at an operating point corresponding to an identical temperature stability point for both elements.

Description:
FIELD OF THE INVENTION 
     The present invention relates to integrated circuits, and, more particularly to a current or voltage generator integrated onto a silicon wafer. 
     BACKGROUND OF THE INVENTION 
     A current or voltage generator  10  of the above-mentioned type is represented in FIG.  1 . The circuit  10  comprises two branches B 1  and B 2 . The branch B 1  comprises a PMOS transistor TP 1  the drain of which is connected to the drain of an NMOS transistor TN 1 , the source of the transistor TN 1  being connected to ground through a resistance R 1 . The branch B 2  comprises a PMOS transistor TP 2 , the drain of which is connected to the drain of an NMOS transistor TN 2 , and the source of the transistor TN 2  is connected to ground. The transistor TN 1  has a gate width to length ratio, or W/L ratio, equal to n times that of the transistor TN 2 , and is generally produced by n NMOS transistors TN 1 - 1 , TN 1 - 2 , . . . TN 1 -n in parallel, that are identical to the transistor TN 2 . The transistors TP 1 , TP 2  receive a voltage Vcc on sources S and are arranged as current mirrors, with the gate G of the transistor TP 2  being connected to the gate of the transistor TP 1  which is itself connected to the drain D of the transistor TP 1 . 
     So that the circuit  10  self-biases at a determined operating point, the gate of the transistor TN 1  is connected to the gate of the transistor TN 2  which is itself connected to the drain of the transistor TN 2 . After application of the voltage Vcc, the generator  10  sets to an operating point where the branches B 1 , B 2  are passed through by the same current I, taken to be constant. 
     The generator  10  delivers a reference voltage Vref that is, for example, sampled at the gate of the transistor TN 1 . To obtain a constant source of current, the voltage Vref is applied to the gate of an NMOS transistor TN 0  arranged in an external branch Be. The voltage Vref imposes a current Ie(Vref) in the branch Be. This current is equal to the current I if the transistor TN 0  is identical to the transistor TN 1 , otherwise it is proportional to the current I. The transistor TN 0  is therefore the equivalent of a current generator inserted into the branch Be. Other current generators can be created in this way by applying the voltage Vref to other transistors. 
     The current or voltage generator that has just been described provides the advantage of being very simple and small in size in terms of silicon surface. However, it is inconvenient in that it is sensitive to temperature variations, and to variations in the supply voltage Vcc. For a better understanding, FIG. 2 represents current Ie(Vref) curves according to the temperature T and to the voltage Vcc. It can be seen that the current Ie(Vref) varies with the temperature, for a given supply voltage Vcc. Furthermore, for a given temperature T, it can also be seen that the current increases when the voltage Vcc increases. 
     SUMMARY OF THE INVENTION 
     The purpose of the present invention is to overcome this shortcoming in a simple manner, without using complex stabilization circuits. 
     More particularly, the purpose of the present invention is to provide a current or voltage generator of the afore-mentioned type that has good temperature stability. 
     The purpose of the present invention is also to provide a current or voltage generator of the afore-mentioned type that remains stable when its supply voltage varies. 
     For these purposes, the present invention provides a generator comprising two elements that can have identical temperature stability points. More particularly, the present invention provides a current or voltage generator integrated onto a silicon wafer, comprising a first element comprising a first NMOS transistor having its source connected to ground through an electrical resistance, and a second element comprising a second NMOS transistor having its source connected to ground. The generator may also include a bias circuit for the first and second elements. The second element may comprise a voltage divider, the gate of the second NMOS transistor may be connected to a dividing node of the voltage divider, and the anode of the voltage divider may be connected to the gate of the first NMOS transistor. 
     According to one embodiment, the voltage divider comprises at least two resistances, and the gate of the second NMOS transistor is connected to the midpoint of the two resistances. 
     According to one embodiment, the bias circuit applies an identical drain-source current to the first and second elements, such that the first and second elements have a common operating point in current and in voltage. 
     According to one embodiment, the first and second elements are arranged to have the same temperature stability point, i.e. current/voltage curves according to the temperature of each element that meet at the same point. 
     According to one embodiment, the bias circuit is arranged so that the common operating point of the first and second elements corresponds to the temperature stability point of the first and second elements. 
     According to one embodiment, the bias circuit comprises a first branch connected to the drain of the first NMOS transistor, a second branch connected to the drain of the second NMOS transistor, and a third branch connected to the anode of the divider. The first branch and the second branch may be arranged as current mirrors. 
     According to one embodiment, the first branch and the second branch respectively may comprise a first PMOS transistor and a second PMOS transistor. 
     According to one embodiment, the first branch may comprise a third NMOS transistor arranged between the first PMOS transistor and the first NMOS transistor, the second branch may comprise a fourth NMOS transistor arranged between the second PMOS transistor and the second NMOS transistor, and the third branch may comprise a fifth NMOS transistor having its gate connected to those of the third and fourth NMOS transistors. 
     According to one embodiment, the bias circuit comprises a fourth branch comprising a third PMOS transistor in series with a sixth NMOS transistor. The third PMOS transistor and the sixth NMOS transistor may be arranged to maintain a voltage on the drain of the first PMOS transistor that is substantially identical to the drain voltage of the second PMOS transistor. 
     According to one embodiment, the gate of the third PMOS transistor may be connected to the drain of the first PMOS transistor, and the gate of the sixth NMOS transistor may be connected to the gate of the second NMOS transistor. 
     According to one embodiment, the second PMOS transistor may have its drain connected to its gate and its gate connected to the gate of the first PMOS transistor. 
     According to one embodiment, the first NMOS transistor may comprise a plurality of NMOS transistors in parallel. 
     According to one embodiment, the generator may comprise an output delivering a reference voltage equal to the gate voltage of the first NMOS transistor. 
     According to one embodiment, the generator may comprise an output delivering a reference voltage equal to the gate voltage of the second NMOS transistor. 
     According to one embodiment, at least one gate of the first or second NMOS transistor may be connected to the gate of a transistor arranged in an external branch to form a source of current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be explained in greater detail in the following description of a current or voltage generator according to the present invention, given in relation with, but not limited to, the following figures: 
     FIG. 1 previously described is the wiring diagram of a classical current or voltage generator according to the prior art; 
     FIG. 2 previously described shows the instability in temperature of a current produced by the generator in FIG. 1; 
     FIG. 3A represents a first element of the generator in FIG. 1; 
     FIG. 3B represents a second element of the generator in FIG. 1; 
     FIG. 3C represents an element according to the present invention; 
     FIG. 4 represents series of current/voltage curves of the prior art elements represented in FIGS. 3A and 3B; 
     FIG. 5 represents the series of curves in FIG.  4  and one series of current/voltage curves of the element represented in FIG. 3C; 
     FIG. 6 is the schematic diagram of a current or voltage generator according to the present invention; and 
     FIG. 7 is the complete wiring diagram of an example of an embodiment of a current or voltage generator according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIGS. 3A,  3 B illustrate two elements CE 1 , CE 2  forming the core of the generator  10  described in the background (FIG.  1 ). The element CE 1  comprises the transistor TN 1  and the resistance R 1 . The transistor TN 1  has its source connected to ground via the resistance R 1 , and its gate receives a bias voltage Vb. The transistor TN 1  is passed through by a drain-source current I. The element CE 2  comprises the transistor TN 2  that receives the bias voltage Vb at its gate and is passed through by the same drain-source current I. 
     FIG. 4 represents current/voltage curves of each of the elements CE 1 , CE 2 . A series of curves F 1 (CE 1 ) can be seen comprising current/voltage curves of the element CE 1  at various temperatures, here at temperatures of −40, 27, 90, and 130° C. A series of curves F 2 (CE 2 ) can also be seen comprising current/voltage curves of the element CE 2  at various temperatures, here −40, 27, 90, and 130° C. Each current/voltage curve represents the relationship that exists between the bias voltage Vb (on the abscissa and in Volts) and the drain-source current (on the ordinate and in μA) when the transistors are operating in a saturated mode. 
     When the elements CE 1 , CE 2  are arranged in the generator  10 , they have a common operating point imposed by the transistors TP 1 , TP 2 . This common operating point is located, for a given temperature, where the two curves belonging respectively to the series F 1  and to the series F 2  meet, in a zone A where the current/voltage curves of the two elements meet, proximate to a horizontal line  11 . When the temperature varies, the operating point can move horizontally along the line  11  or vertically about the line  11 . In other terms, the bias voltage Vb varies with the temperature and the generator  10  has an operating point that is not constant in current and in voltage. The jumps of the operating point from one curve to the other affect the stability of the current I, and that of the external current Ie(Vref) which is the image of the current I, as shown in FIG.  2 . 
     The present invention is based on the observation according to which the curves of the series of curves F 1 , F 2  have a common meeting point, respectively P 1 , P 2  in FIG.  4 . The point P 1  constitutes a temperature stability point of the element CE 1  as all the current/voltage curves of the element CE 1  have, at this point, the same voltage and the same current. For the same reason, the point P 2  represents a temperature stability point of the element CE 2 . 
     Therefore, one aspect of the present invention is to provide two elements that have the same temperature stability point, and to set these elements to a common operating point corresponding to their temperature stability point. However, as it will be understood by those skilled in the art, in practice, it is difficult to move the stability point P 2  of the element CE 2  so that it coincides with the stability point P 1  of the element CE 1 . There is a small degree of freedom in the design of the transistor TN 2 , which does not allow the points P 1  and P 2  to be superimposed. 
     The present invention suggests producing a current or voltage generator using a first element CE 1  conforming to the one represented in FIG. 3A and a second element CE 2 ′ represented in FIG. 3C, which replaces the conventional element CE 2  represented in FIG.  3 B. The element CE 2 ′ comprises the NMOS transistor TN 1  already present in the element CE 2  and comprises, in addition, a voltage divider Pd. The divider comprises for example two resistances R 2 , R 3 . One end of the resistance R 2  forms the anode of the divider Pd, the other end of the resistance R 2  is connected to one end of the resistance R 3 , the other end of the resistance R 3  is connected to ground. According to the present invention, the gate of the transistor TN 1  is connected to a dividing node  15  of the divider Pd, here the midpoint of the resistances R 2 , R 3 , and thus receives a gate voltage Vg which is a fraction of the voltage applied between the anode of the divider and the ground. 
     FIG. 5 represents the series of curves F 1 (CE 1 ), F 2 (CE 2 ) already represented in FIG. 4, and a series of current/voltage curves F 2 ′(CE 2 ′) of the element CE 2 ′. The series F 2 ′(CE 2 ′) here comprises four curves traced at the same temperatures as the series F 1 , F 2 . These curves have been traced by considering that the voltage applied to the divider Pd is the bias voltage Vb of the element CE 2 ′. It can be seen that the series F 2 ′ also has a temperature stability point P 2 ′, where all the curves meet. Furthermore, thanks to the possibility of adjusting the ratio Vg/Vb between the gate voltage Vg of the transistor TN 1  and the bias voltage Vb, it is possible to make the element CE 2 ′ have a stability point P 2 ′ that merges with the stability point P 1  of the element CE 1 , as shown in FIG.  5 . 
     FIG. 6 represents a current or voltage generator  20  according to the present invention, produced using the element CE 1  and the element CE 2 ′. The size of the transistors TN 1  and TN 2  and the value of the resistances R 1 , R 2 , R 3  are chosen so that the elements CE 1 , CE 2 ′ have identical stability points P 1 , P 2 ′, as shown in FIG. 5. A bias circuit BCT supplied by a voltage Vcc imposes the same drain-source current I in each element CE 1 , CE 2 ′, and applies a bias voltage Vb to the anode of the divider Pd. 
     According to the present invention, the anode of the divider Pd is connected to the gate of the transistor TN 1  of the element CE 1 , so that both elements receive the same bias voltage Vb. The current I and the voltage Vb define the common operating point of the elements CE 1 , CE 2 ′, which corresponds to the stability points P 1 , P 2 ′. The generator  20  therefore has excellent stability in temperature, its operating point I, Vb corresponding to the temperature stability point of the elements CE 1 , CE 2 ′. 
     As represented in FIG. 6, the generator  20  can deliver two reference voltages. One reference voltage Vref 1  can be sampled on the gate of the transistor TN 2  and be applied to an NMOS transistor TN 0  arranged in an external branch Be, to form a constant source of current. The voltage Vref 1  allows a constant current Ie that is equal to the current I if the transistor TN 0  has the same dimensions as the transistor TN 1  (same gate width to length ratio) to be imposed in the transistor TN 0 , by a current mirror effect. Furthermore as the voltage Vref 1  is a constant voltage, the gate of the transistor TN 2  can be used as a constant voltage generator. 
     A reference voltage Vref 2  can also be sampled on the gate of the transistor TN 1  (or on the anode of the divider Pd). This voltage Vref 2  is the bias voltage Vb and corresponds to the temperature stability point. The voltage Vref 2  is also constant and the gate of the transistor TN 1  can be used as a constant voltage generator. 
     An example of an embodiment of the bias circuit BCT will now be described in relation with FIG.  7 . One intended object is to bias the elements CE 1  and CE 2 ′ on the operating point I, Vb corresponding to their temperature stability point. Another intended object here is that the operating point I, Vb is not substantially sensitive to any variations in the supply voltage Vcc. 
     The circuit BCT comprises a branch B 1  connected to the element CE 1 , branches B 2  and B 3  connected to the element CE 2 ′, and a negative feedback branch B 4 . The branch B 1  comprises a PMOS transistor TP 1  and an NMOS transistor TN 3  in series. The branch B 2  comprises a PMOS transistor TP 2  and an NMOS transistor TN 4  in series. The transistor TP 1  receives the voltage Vcc at its source and its drain is connected to the drain of the transistor TN 3 . The source of the transistor TN 3  is connected to the drain of the transistor TN 1  of the element CE 1 , the source of which is connected to ground via the resistance R 1 . The transistor TP 2  receives the voltage Vcc at its source and its drain is connected to the drain of the transistor TN 4 . The source of the transistor TN 4  is connected to the drain of the transistor TN 2  of the element CE 2 ′, the source of which is connected to ground. The gates of the transistors TP 1  and TP 2  are interconnected, and the transistor TP 2  has, in addition, its gate connected to its drain. The gates of the transistors TN 3 , TN 4  are also interconnected. 
     The branch B 3  comprises an NMOS transistor TN 5  the drain of which receives the voltage Vcc and the source of which is connected to the anode of the divider Pd of the element CE 2 ′, here the end of the resistance R 2 . The gate of the transistor TN 5  is connected to the gates of the transistors TN 3 , TN 4 . The anode of the divider Pd is also connected to the gate of the transistor TN 1 , as described above. 
     The branch B 4  comprises a PMOS transistor TP 3  and an NMOS transistor TN 6  in series. The transistor TP 3  receives the voltage Vcc at its source and its drain is connected to the drain of the transistor TN 6 , the source of which is connected to ground. The gate of the transistor TN 6  is connected to the gate of the transistor TN 2  of the element CE 2 ′ (midpoint  15  of the resistances R 2 , R 3 ) and the gate of the transistor TP 3  is connected to the drain of the transistor TP 1 . Optionally, but advantageously, an anti-oscillation capacitor Cf is arranged between the gate of the transistor TP 3  and the gate of the transistor TN 3 . 
     Preferably, the transistors TP 1 , TP 2  and TP 3  are identical (same gate width to length ratio), the transistors TN 2 , TN 6  are identical. The transistor TN 1  also preferably comprises n transistors identical to the transistor TN 2  and therefore has a W/L ratio that is equal to n times the W/L ratio of the transistor TN 2 . Again preferably, the transistors TN 3 , TN 4 , TN 5  are identical and have a low threshold voltage, below that of the transistors TN 1 , TN 2 . The transistors TN 3 , TN 4 , TN 5  are for example native transistors (with undoped channels) having a threshold voltage in the order of 0.4 V, compared to 1 V for those of the transistors TN 1 , TN 2 , that are conventional enhancement transistors. 
     The branches Bi and B 2  are arranged as current mirrors and are passed through by currents I 1  and I 2  that aim to be equal to the drain-source current I required. The transistor TN 5  in the branch B 3  is arranged as a follower and aims to impose a current I 3  in the divider Pd, so that the bias voltage Vb at the operating point is equal to I 3 *(R 2 +R 3 ) and that the gate voltage of the transistor TN 2  is equal to I 3 *R 3  (or Vb*R 3 /R 2 +R 3 ). As indicated above, the current I 3  is chosen to correspond to the current of the temperature stability point of the elements CE 1 , CE 2 ′ and the resistances R 2  and R 3  are chosen so that the voltage Vd corresponds to the voltage of the temperature stability point. 
     The branch B 4  ensures the self-bias of the generator  20  at the operating point I, Vb. As an example, it will be assumed that the voltage Vb is higher than the voltage of the theoretical operating point. In this case, by observing FIG. 5, it can be seen that the current of the operating point on the series of curves CE 2 ′ is higher than the current of the operating point on the series of curves CE 1 . In this case, the gate voltage of the transistor TP 3  increases and the voltage Vb drops as the transistor TP 3  conducts less current. If, on the other hand, the voltage Vb becomes lower than that of the theoretical operating point, the current of the series of curves CE 2 ′ becomes lower than the current of the series of curves CE 1  and the gate voltage of the transistor TP 3  drops, so that the voltage Vb increases. Consequently, thanks to the branch B 4 , the generator according to the present invention always reacts in such a way as to bring the current back to the nominal value of the operating point. 
     Therefore, the branches B 1 , B 2 , B 3 , B 4  are passed through by the same current and the transistor TP 3  imposes a drain voltage on the transistor TP 1  that is identical to the drain voltage of the transistor TP 2 . As the transistors TP 1 , TP 2  receive the same voltage Vcc at their source, the drain-source voltages of these two transistors are checked and are maintained identical. If the voltage Vcc varies and becomes high, the transistors TN 1 , TN 2  are capable of not having the same drain current variation for the same drain voltage variation, as they are not identical, which could unbalance the generator  20 . The transistors TN 3 , TN 4  correct this phenomenon and maintain a constant drain voltage on the transistors TN 1 , TN 2 . In fact, the variations in the voltage Vcc affect the drain-source voltage of the transistors TN 3 , TN 4  but, as these are identical and biased in the same conditions, the variations of the voltage Vcc do not cause any shift of the operating point. 
     The current or voltage generator according to the present invention delivers a current I (Vref 1 ) or voltages Vref 1  and Vref 2  that have great temperature stability. As a numerical example, for a voltage Vcc of 1.85 V and a temperature varying between −40° C. and 130° C., and for the following nominal values: 
     
       
         Vref 1 =0.8V 
       
     
     
       
         I(Vref 1 ) (=I)=10.45μA 
       
     
     
       
         Vref 2 =1.235V 
       
     
     the measurable variations are as follows: 
     
       
         0.797V&lt;Vref 1 &lt;0.804V 
       
     
     
       
         10.4μA&lt;I(Vref 1 ) (=I)&lt;10.5μA 
       
     
     
       
         1.23V&lt;Vref 2 &lt;1.24V 
       
     
     and are therefore below ±0.5% over the whole range of temperatures.