Abstract:
Methods and apparatus are disclosed for controlling power distribution during transitory power-up period of multi-domain electronic circuits that are supplied by multiple power supplies. The power distribution is controlled by self-regulating power control circuits that operate based on power-up sequencing requirements. Described embodiments of the invention illustrate examples of power-switch and power-switch controller circuits used as elements of the power control circuitry.

Description:
TECHNICAL FIELD 
   The embodiments described below relate generally to electronic circuits, and more particularly, to power distribution in a multi-power-source, multi-domain, integrated circuit. 
   BACKGROUND 
   Logic control signals generated by the power-up reset signals of various power supplies are commonly used to determine the power-up sequence logic in an integrated circuit device. However, during power-up of an integrated circuit device that has multi-power domains, there is no sequencing control by the integrated circuit device over the external power supplies, and the traditional methods cannot control the sequencing of power supplies within functional blocks where specific power-up sequences are required. 
   The transitional instability of the power level of different power supplies during the power-up process is an important issue during the power-up process. Conventional level shifters can be used to transfer logic signals among various power levels when power supplies are stable; however, during power-up mode, not all power supplies are stable. In most cases, during power-up process, some power supplies become stable while others either continue to ramp up or remain inactivated. Specially designed level shifting circuits are needed to handle the power-up processes. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates an example of a power-up sequence control circuit, in accordance with an embodiment of the invention. 
       FIG. 2  illustrates a power-switch, which is an element of the power-up sequence control circuit of  FIG. 1 , in accordance with an embodiment of the invention. 
       FIG. 3  illustrates a power-switch controller, which is an element of the power-up sequence control circuit of  FIG. 1 , in accordance with another embodiment of the invention. 
       FIG. 4  illustrates a power-switch controller, in accordance with yet another embodiment of the invention. 
       FIG. 5  illustrates a power-switch controller, in accordance with yet another embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   Various embodiments of the invention will now be described. The following description provides specific details for a thorough understanding and enabling description of these embodiments. One skilled in the art will understand, however, that the invention may be practiced without many of these details. Additionally, some well-known structures or functions may not be shown or described in detail, so as to avoid unnecessarily obscuring the relevant description of the various embodiments. 
   The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific embodiments of the invention. Certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be overtly and specifically defined as such in this Detailed Description section. 
   The described embodiments illustrate the use of self-controlled power switches to control the power supplied by different power supplies to various functional blocks of an integrated circuit device. The required power-up sequence within a functional block is controlled by a set of power switches. When the power levels (voltages) of different power supplies are not the same, it is often required for a signal from a lower power supply level to control the power switches that control the higher power levels. 
   Another issue concerning the power-up process is the potential instability of the power being supplied during the power-up transition period of a power supply. When power supplies are stable, conventional level shifters may be used to transfer logic signals among various power levels; however, during power-up mode, not all power supplies are stable. In fact in most cases some power supplies become stable while others either continue to ramp up or remain inactivated. Therefore, especially designed level shifting circuits are needed to handle the power-up processes. 
   In circumstances where a power-up sequence is required, since not all power supplies may be stable or activated, the power switches must be controlled by the power-up sequence, rather than by a fixed logic that is only suitable for stable power levels. In these cases the controls to the power switches are designed to be self-timed and self-adjusted to satisfy the required power-up sequences. 
     FIG. 1  illustrates an example of a power-up sequence control circuit  100 , in accordance with an embodiment of the invention. In this example, there are three power supplies for the integrated circuit device, and the power levels of these power supplies are different. Power 1 , Power 2 , and Power 3  represent these three power supplies. 
   Power 3  has the highest power level (voltage), Power 2  has a power level lower than Power 3  but higher than Power 1 , and Power 1  has the lowest power level. During the power-up stage, Power 3  is the first to be stable, while Power 2  and Power 1  will be ramping up to stable levels. It is also required that Power 2  goes to the corresponding functional blocks after Power 1  is stable, regardless of the order in which they become stable. By controlling the power switch  110  located between Power 2  and the functional blocks supplied by Power 2 , the switch controller  112  regulates the required sequencing of Power 1  and Power 2 . 
     FIG. 2  is a schematic diagram of the power switch  110 , which consists of a PMOS transistor  210  whose body is connected to Power 2 , and whose gate is controlled by the switch controller  112 . There is also an NMOS transistor  212  serving as a leakage device when the power switch is not turned on. This leakage device discharges the Internal Power 2  Supply when the switch M 1  is turned off, so that the Internal Power 2  Supply is not in a floating state. 
     FIG. 3  is a schematic diagram of the power switch controller  112 . The power switch controller  112  has three parts:
         1-Power 1  detection circuit (M 2 , M 7 , M 1 , M 5 , M 6 )   2-Power 1  detection trigger circuit (M 3 , M 8 )   3-Power 1  signal to Power 3  signal level shifting circuit (M 3 , M 8 , INV 1 , INV 2 )       
   Transistors M 1 , M 5 , M 6  generate a bias voltage for M 7  to limit its current. The gate of transistor M 2  is tied to ground (GND) so that it becomes conducting as soon as Power 1  is above V t  (the device threshold turn-on voltage). M 3  is a weak PMOS device and M 8  is turned on only if Power 1  is high enough to offset the biased current sink by M 7 . 
   When Power 3  is on and Power 1  is off, the output of the circuit (Switch_en_b) is high (Power 3  level) because M 3  is on and M 8  is fully off. 
   When Power 1  starts to ramp up, M 2  starts conducting. When the voltage level at point A reaches V t  of M 8 , M 8  starts conducting, and the Voltage level at point B starts to drop. In this situation the output Switch_en_b changes from high to low. 
     FIG. 4  is a schematic diagram of another power switch controller  112 , where:
         M 4  is the feedback for the switch on lock-up (because M 3  is a weak pull-up device, it is sensitive to noise. M 4  reduces the noise sensitivity by providing a latch-like structure, especially when the Power 1  is not ready.);   D 1  is the diode for preset state (D 1  provides a discharge path for the gate of M 8  to turn off M 8  when Power 1  is off so that the control circuit can return back to the preset state.); and   C 1  is to reduce noise (in an integrated device, there are noise generated by other circuits. C 1  reduces the M 8  gate sensitivity to such noise.).       
     FIG. 5  is a schematic diagram of an alternative power switch controller  112 , where M 9  and M 10  are feedbacks for turning off bias and detection circuit static currents. M 9  and M 10  are for power management. When Power 1  is off, M 9  and M 10  are turned on so that the control circuit is ready to operate. After Power is up and stable, M 9  and M 10  are turned off so that the DC current I 1  and I 2  are eliminated, thus reducing the power consumption of the control circuit. 
   Conclusion 
   Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” As used herein, the terms “connected,” “coupled,” or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling of connection between the elements can be physical, logical, or a combination thereof. 
   Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. 
   The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
   The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. 
   Changes can be made to the invention in light of the above Detailed Description. While the above description describes certain embodiments of the invention, and describes the best mode contemplated, no matter how detailed the above appears in text, the invention can be practiced in many ways. Details of the compensation system described above may vary considerably in its implementation details, while still being encompassed by the invention disclosed herein. 
   As noted above, particular terminology used when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the invention with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the invention encompasses not only the disclosed embodiments, but also all equivalent ways of practicing or implementing the invention under the claims. 
   While certain aspects of the invention are presented below in certain claim forms, the inventors contemplate the various aspects of the invention in any number of claim forms. Accordingly, the inventors reserve the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the invention