Abstract:
A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the power sources and the isolated circuitry, and one or more controllers for turning the switches on or off according to one or more predetermined conditions.

Description:
BACKGROUND 
       [0001]    The present invention relates generally to an integrated circuit (IC) design, and, more particularly, to designs of power supply to built-in test circuitries in ICs. 
         [0002]    As semiconductor processing technology has progressed to deep submicron technologies, more and more devices can be packed in a single chip. Each device may have a small amount of leakage, but an accumulative leakage from a great number of devices can pose a problem, especially to a chip used in a hand-held equipment powered by batteries. 
         [0003]    Many complicated chips have built-in self test (BIST) circuitries to facilitating the testing of the chips prior to shipping them to customers. These BIST circuitries are used only during the chip testing phase, once a chip passes the test and is shipped to a customer, those BIST circuitries will not be used any more. But devices in the BIST circuitries are still coupled to a power supply, hence still produce leakage, even they have no functions during the chip operations. 
         [0004]    A traditional way to reduce leakage from BIST circuitries is to use devices with higher threshold voltage to build the BIST circuitries, as speed requirements for the BIST is normally very lose. High threshold voltage devices have lower leakage, but switching speed is also slower than their lower threshold voltage counterparts. But this method does not completely cut off the leakage, and some time it may require additional processing steps. 
         [0005]    So what is desired is a design that can reduce the number of devices, which can contribute to the overall leakage to the minimum. 
       SUMMARY 
       [0006]    In view of the foregoing, the following provides a method and system for reducing current leakages in an integrated circuit (IC). 
         [0007]    In one embodiment, the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the power sources and the isolated circuitry, and one or more controllers for turning the switches on or off according to one or more predetermined conditions. 
         [0008]    The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a block diagram illustrating a chip with a built-in self test (BIST) circuitry. 
           [0010]      FIG. 2  is a block diagram illustrating a power supply to a BIST circuitry controlled by a switch according to one embodiment of the present invention. 
           [0011]      FIG. 3A˜3D  are schematic diagrams illustrating implementations of the switch and switch controllers that control the power supply to the BIST circuitry according to embodiments of the present invention. 
       
    
    
     DESCRIPTION 
       [0012]    The present disclosure provides a system and method for supplying power to built-in self test (BIST) circuitries only when the BIST circuitry is in operation. 
         [0013]      FIG. 1  is a block diagram illustrating a chip  100  with a built-in self test (BIST) circuitry  110 . A mode pad  120  is used to determine whether the chip  100  is in normal operation or in test mode. Customarily when a logic high voltage is applied to the mode pad  120 , the chip  100  goes into test mode. The BIST circuitry  110  sends out a signal from node C to turn off a multiplexer  130  and turn on another multiplexer  140 , so that a main pad  150  becomes coupled to the BIST circuitry  110  during a test mode operation. Then the main pad  150  becomes an I/O pad for the BIST circuitry  110 , which in turn performs various test functions as designed. Referring to  FIG. 1 , the singular main pad  150  is only a representative of a plurality of main pads. 
         [0014]    Referring to  FIG. 1 , a main circuitry  160  is the main functional circuitry that chip  100  is all about. The BIST circuitry  110  is so designed to facilitate testing of the main circuitry  160 . 
         [0015]    Referring to  FIG. 1 , a power supply is hard wired to both main circuitry  160  and the BIST circuitry  110 . Even during normal operation when the BIST circuitry  110  is totally disengaged from the main circuitry  160 , the power supply is still provided to the BIST circuitry  110 , which will then inevitably produce some leakage current. 
         [0016]      FIG. 2  is a block diagram illustrating a power supply to the BIST circuitry  110  being controlled by a switch  210  according to one embodiment of the present invention. The switch  210  is controlled by a controller  220 , which is coupled to the mode pad  120 . When mode pad  120  is in logic high state, the BIST circuitry  110  is engaged, and the controller  220  closes the switch  210 , so that the power is supplied to the BIST circuitry to allow it to function normally. When mode pad  120  is in logic low state, the BIST circuitry  110  is disengaged, and the controller  220  opens the switch  210 , so that the power supply to the BIST circuitry  110  is cut off. Then the BIST circuitry  110  does not contribute any leakage. 
         [0017]    The present disclosure uses BIST as an example to illustrate the inventive concept. In fact, any circuitry that can be isolated from the main circuitry, and is disengaged from the main circuitry during normal operation, can employ the present invention. A boundary scan, or JTAG, circuitry is another example of such isolated circuitries. 
         [0018]      FIG. 3A˜3D  are schematic diagrams illustrating implementations of the switch  210  and the switch controller  220  that together control the power supply to the BIST circuitry. 
         [0019]      FIG. 3A  illustrates that an N-type metal-oxide-semiconductor (NMOS) transistor  310  is used as a power switch for the BIST circuitry  110 . A source and a drain of the NMOS transistor  310  is placed between the BIST circuitry  110  and a low supply voltage (Vss), and a gate of the NMOS transistor  310  is coupled to the mode pad  120 . When the mode pad  120  is in high logic state, the chip enters test mode, and the NMOS transistor  310  is turned on, so that the power supply to the BIST circuitry  110  can flow from a high supply voltage (Vdd) to the Vss. When the mode pad  120  is in low logic state, the chip enters normal operation, and the NMOS transistor  310  is turned off, so that the power supply to the BIST circuitry  110  is cut off. So the direct connection of the mode pad  120  to the gate of the NMOS transistor  310  serves as a controller for the NMOS transistor  310  switch. 
         [0020]      FIG. 3B  illustrates that a P-type metal-oxide-semiconductor (NMOS) transistor  320  is used as a power switch for the BIST circuitry  110 . A source and a drain of the PMOS transistor  320  is placed between the BIST circuitry  110  and the Vdd, and a gate of the PMOS transistor  320  is coupled to the mode pad  120  through an inverter  325 . When the mode pad  120  is in a high logic state, the chip enters test mode, and the PMOS transistor  320  is turned on, so that the power supply to the BIST circuitry  110  can flow from the Vdd to the Vss. When the mode pad  120  is in a low logic state, the chip enters normal operation, and the PMOS transistor  320  is turned off, so that the power supply to the BIST circuitry  110  is cut off. So the connection of the mode pad  120  to the gate of the PMOS transistor  320  through an inverter serves as a controller for the PMOS transistor  320  switch. 
         [0021]    In certain applications, once a chip passes the test and is packaged, its BIST circuitry will never be used and can be permanently disabled. Then other kinds of switch control schemes can be used, such as blowing a fuse. 
         [0022]      FIG. 3C  illustrates a fuse  330  and a resistor  340  connected at node V with the other terminal of the fuse  330  coupled to the Vdd, and the other terminal of the resistor  340  coupled to the Vss. The gate of the switching NMOS  310  is coupled to the node V. The resistance of the fuse  330  is normally less than  100  ohm. While the resistance of the resistor  340  can be set at higher than  20 K ohm to limit a current flowing through a path formed by the fuse  330  and the resistor  340 . The resistor  340  can be formed by passive semiconductor materials, such as Nwell, or by high-resistance always-on active devices. 
         [0023]    Referring to  FIG. 3C , before being blown, the fuse  330  provides a low resistance connection between the node V and the Vdd, so that the NMOS  310  is on to provide power supply to the BIST circuitry  110 . After the chip is tested, and the BIST circuit  110  is no longer useful, the fuse  330  can be blown, so that the connection between the node V and the Vdd is cut off, and the node V becomes coupled to the Vss which turns off the NMOS transistor  310 . Then the power supply to the BIST circuitry  110  is cut off. 
         [0024]      FIG. 3D  illustrates the fuse  330  and the resistor  340  connected at node V and with the other terminal of the fuse  330  coupled to the Vss, and the other terminal of the resistor  340  coupled to the Vdd. The gate of the switching PMOS  320  is coupled to the node V. The resistance of the fuse  330  is normally less than 100 ohm. While the resistance of the resistor  340  can be set at higher than 20K ohm to limit a current flowing through a path formed by the fuse  330  and the resistor  340 . The resistor  340  can be formed by passive semiconductor materials, such as Nwell, or by high-resistance always-on active devices. 
         [0025]    Referring to  FIG. 3D , before being blown, the fuse  330  provides a low resistance connection between the node V and the Vss, so that the PMOS  320  is on to provide power supply to the BIST circuitry  110 . After the chip is tested, and the BIST circuit  110  is no longer useful, the fuse  330  can be blown, so that the connection between the node V and the Vss is cut off, and the node V becomes coupled to the Vdd, which turns off the PMOS transistor  320 . Then the power supply to the BIST circuitry  110  is cut off. 
         [0026]    The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. 
         [0027]    Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.