Abstract:
A method and structure for minimizing one or more non-uniformities in image and position sensing detectors are provided. The structure is directed to a focal plane processor for removing non-uniformities which distort the computation of a de-sired property of an object of interest in an image field. The focal plane processor is capable of selectively disconnecting one or more rows and/or columns from further processing in the imaging array for those rows and/or columns which contribute to the presence of at least one non-uniformity in a video image generated by the focal plane processor. In one embodiment, the disconnection means is embodied as pre-processing circuitry which includes row and column shift registers which provide control signals to area-of-interest (AOI) switches. In another embodiment, the pixels which comprise the focal plane array are constructed in a manner which facilitates their individual isolation.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit of prior filed co-pending U.S. provisional application Ser. No. 60/248,902 filed on Nov. 15, 2000, the contents of which are hereby incorporated by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    This invention relates generally to image processors of the type which are located on the focal plane of an imaging array, and more particularly to an improved image processor for removing non-uniformities which can distort the image processor&#39;s computations.  
           [0004]    2. Description of the Related Art  
           [0005]    The class of image sensors known. as focal plane processors are integrated sensor circuits which combine some form of signal processing and an imaging array on a single die. The imaging array captures an image which strikes an array of pixel sensors lying on a focal plane. The focal plane is a light sensitive circuit on which the optical array focuses ambient light. The pixel sensors convert light into electrical signals. Generally, the focal plane is defined by the surface of a semiconductor device which has a plurality of light sensitive elements (photo-transconduction elements) formed thereon to achieve a pixel sensing capability.  
           [0006]    The signal processing of a focal plane processor is often done in the analog domain resulting in a compact, low-power method of performing the signal computation. Due to inherent variation in fabrication processing, a large focal plane processor may have one or more pixels that provide erroneous signals, i.e., the pixel may always signal that it is being impinged with bright light when in fact this is not the case. These “bad pixels” may cause the analog computation to generate an incorrect result. Additionally, a given image may have an object in the field of view that interferes with the desired computation of some property of the desired object in the image.  
           [0007]    As an example, image sensors are commonly used in a wide variety of image-tracking applications. One such application is that of a sun-based position sensor. In order to compute the sun&#39;s position using an imaging sensor, the sensor and associated computational circuitry must compute the centroid of the sun&#39;s image. Centroid computation is a very useful, well known quantity for image-tracking applications. Finding the centroid is an averaging process, the solution is robust to noise as well as insensitive to minor variations in illumination level. However, in practical applications, such as sun sensors, the illumination level of interfering objects that fall into the sensor&#39;s field of view (e.g., glint) may be significant enough so as to adversely affect the centroid computation, thereby causing an error in the reported sun position.  
           [0008]    [0008]FIG. 1 is an illustration of a prior art focal plane processor  10  (integrated circuit) including an n×n array  12  of imaging pixels  13  and signal processing means, e.g., computational blocks  18 ,  19 .  
           [0009]    [0009]FIG. 2 is a more detailed illustration a representative imaging pixel  13  from among the plurality of imaging pixels which makes up the nxn pixel array  12 . The imaging pixel  13  is shown to include transistors M 1 , M 2  and M 3 , image element  22 , row summing line r i , column summing line c i  and reset line, reset i . Each pixel  13  contributes a current that is summed over the pixel&#39;s respective row and column.  
           [0010]    Referring again to FIG. 1, the processor  10  generally operates as follows. For each column (c o -c n−1 ) and row (r 0 -r n−1 ) of the n×n array  12 , the imaging pixels are summed (each pixel contributes a current) after an integration period yielding n summed rows and n summed columns. Each summed row is passed to the row computational block  18  and each summed column is passed to the column computational block  19 . The row and column computational blocks  18 ,  19  use the respective n summed row and n column currents to compute some desired property of the image, e.g., a centroid. As stated above, a drawback of this prior art configuration is that in the case where one or more non-uniformities (e.g., undesirable objects, bad pixels) exist in the image, there is no provision for their removal.  
           [0011]    Thus, an improved processor would be desirable having a capability for removing the one or more non-uniformities thereby providing a more accurate computation of the desired property of the image.  
         SUMMARY OF THE INVENTION  
         [0012]    The present invention is generally directed to a focal plane processor and associated method for removing non-uniformities which can potentially distort the computation of a desired property of the image field. The method of the invention, according to one embodiment, removes identified non-uniformities in the image field by disconnecting from further processing and readout, one or more rows and/or columns of a focal plane array which contribute to the image field non-uniformities. In so doing, a more accurate computational result of some desired property of the image field is achieved.  
           [0013]    Thus, in a first aspect, the invention relates to a method for removing one or more non-uniformities from an imaging focal plane array, the method generally comprising: observing an image (i.e., video output) produced by a focal plane array processor to identify at least one row and/or column which contributes to a non-uniformity in the produced image; and means for removing the at least one row and/or column from further processing in the focal plane array.  
           [0014]    In a further aspect, the invention relates to a method for removing one or more non-uniformities from an imaging focal plane array, the method generally comprising: observing an image (i.e., video output) produced by a focal plane array processor to identify at least one pixel which contributes to a non-uniformity in the produced image; and means for removing the at least one pixel from further processing in the focal plane array.  
           [0015]    Circuitry for carrying out the above methods of the present invention includes at least a focal plane array, computational circuitry and processing circuitry all formed on a single substrate. The focal plane imaging array having current summing lines along each row and column and x and y position sensitive (computation) circuitry located on the edge of the array. The computation circuitry for computing some desirable property of the image field. In a first embodiment, the circuitry further includes circuitry for selectively disconnecting one or more rows and columns from the focal plane imaging array. The disconnection circuitry includes a plurality of row and column shift registers which provide control signals to area-of-interest (AOI) switches which selectively connect/disconnect the respective rows and columns of the array.  
           [0016]    In a further embodiment, the disconnection circuitry includes a plurality of row and column shift registers which provide control signals directly connected to the respective pixels for connecting/disconnecting the respective pixels. In this embodiment, control is more refined in the individual pixels rather than selectively disconnecting the entire rows and/or columns from further processing.  
           [0017]    Further advantages of the improved sensor include an increased readout rate of a critical region, and enhanced sensor dynamic range due to not processing regions with very high illumination.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    The present invention may be more fully understood from the detailed description given below and from the accompanying drawings of the preferred embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments but are for explanation and understanding only.  
         [0019]    [0019]FIG. 1 is a simplified schematic of a focal plane processor constructed in accordance with the prior art;  
         [0020]    [0020]FIG. 2 is a schematic of a representative pixel which is a component of the imaging array of the focal plane processor of FIG. 1;  
         [0021]    [0021]FIG. 3 is a schematic of a focal plane processor constructed in accordance with a first embodiment of the present invention;  
         [0022]    [0022]FIG. 4 is a schematic of an area-of-interest (AOI) circuit which is a component of the focal plane processor of FIG. 3;  
         [0023]    [0023]FIG. 5 is a detailed schematic of a representative pixel of the imaging array of the focal plane processor of FIG. 3, according to a second embodiment of the present invention;  
         [0024]    [0024]FIG. 6 is a detailed schematic of a modified representative pixel of the imaging array of the focal plane processor of FIG. 5, according to the second embodiment of the present invention; and  
         [0025]    [0025]FIG. 7 is a detailed schematic of a representative pixel according to a third embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]    [0026]FIG. 3 is an illustration of a focal plane processor  30  constructed in accordance with a first embodiment of the present invention. The processor  30  contains a number of components that are identical in construction, and perform identical functions, to components described above with regard to the prior art processor  10  of FIG. 1. In particular, the inventive processor  30  includes a conventional n×n array  12  of imaging pixels  13  and row and column computational blocks  18 ,  19 . It is also contemplated that the array is an m×n array, i.e., an array having a different number of rows and columns. Also shown in FIG. 3 are components which embody the functionality of the present invention. In particular, FIG. 3 further includes row and column n-bit shift registers  36 ,  38 , a plurality of row area-of-interest (AOI) circuits  33   a - n , and a plurality of column area-of-interest (AOI) circuits  35   a - n . The operation of the inventive processor circuit  30  is described as follows.  
         [0027]    In operation, the pixels  13  in each column (c o -c n−1 ) and row (r 0 -r n−1 ) of the n×n array  12  are summed after each integration period. In the illustrative embodiment of FIG. 3, after one integration period, n independent row summations and n independent column summations are performed. Subsequent to performing the row and column summing operations, each summed row (r 0 -r n−1 ) is passed, via a respective row current summing line, to a respective row AOI circuit  33   a - n . Similarly, each summed colurnn (c o -c n−1 ) is passed, via a respective column current summing line, to a respective column AOI circuit  35   a - n.    
         [0028]    [0028]FIG. 4 is a detailed schematic of an area of interest (AOI) circuit  40 . AOI circuit  40  illustrates the construction of each of the respective row and column AOI circuits  33   a - n ,  35   a - n  of FIG. 3. As previously described, each AOI circuit receives a summed row (column) current  42  from the n×n focal plane imaging array  12 . Each AOI circuit  40  includes a pFET  45  which functions as a pass/don&#39;t pass transistor. AOI circuit  40  also includes an nFET transistor  47  which acts as a shunt to ground. A summed row (column) signal  42  is supplied to one terminal  45   a  of pFET  45 . The signal is either passed through to the row (column) computational block  18  ( 19 ) dependent upon the control signal  44  (i.e., 0 or 1) supplied from the x-axis (y-axis) n-bit shift register  36  ( 38 ). A control signal  44  (bit value) of “ 0 ” supplied from the n-bit row (column) shift register  36  ( 38 ) indicates that the particular row r i  (column c i ) does not contain a non-uniformity, or a portion thereof In this case, the pFET  45  is turned “on” and the nFET  47  is turned “off” which allows the summed ith row (column) current  42  to pass through to the computational block  18  ( 19 ). In this case, the AOI circuit  40  behaves as a resistor to permit the current flow.  
         [0029]    In the case where the control signal  44  (bit value), supplied from the n-bit row r i  (column c i ) shift register  36  ( 38 ) is a “1” indicating the particular row (column) contains at least some portion of an error source to be removed, the pFET  45  is turned “off” and the nFET  47  is turned “on”. Under this condition, the row (column) signal  42  received by the computational block is zero and does not contribute to the computation.  
         [0030]    In this case, the summed ith row (column) current from the focal plane n×n array  12  is blocked. In order to avoid a floating point input to the computational block  18  ( 19 ), the nFET  47  shunts this node to ground.  
         [0031]    A second embodiment of a focal plane processor will be described with reference to FIG. 5. In the second embodiment of the invention, it is recognized that because identified row and current signals are not used by the computational block  18 ,  19  there is no requirement to actually sum the respective pixels that make up the removed rows and/or columns. This is achieved in one way by holding the cathode of the diode at a fixed voltage (e.g., V DD ). This prevents transistors M 2  and M 3  from passing any current to the row r i  and column c i  summing lines.  
         [0032]    [0032]FIG. 5 is an illustration of an array pixel  13  which incorporates the AOI function internally by holding the pixel  13  in “reset” such that transistors M 2  and M 3  do not contribute current to the row r i  and column c i  summing lines. The array pixel  13  of FIG. 5 is distinguished from the one described in FIG. 2 in that two transistors, M 4  and M 5 , are added. Transistor M 4  is controlled (see point B) by a binary signal from the AOI column shift register, AOIC j , while transistor M 5  is controlled (see point C) by a bit from the AOI row shift register, AOIR i . If either shift register presents a “0” value to the pixel, the cathode of the diode  22 , (see point A), becomes clamped to a fixed voltage (e.g., V DD ) and no current is applied to the respective row r i  and column c i  current summing lines. This approach eliminates the necessity of having a separate AOI circuit block at the periphery of the array as described in the first embodiment. It is noted that the clamping voltage can be other V DD . It is further contemplated to utilize two voltages for switching therebetween. In the present embodiment, the AOI (switching) function is performed as an integral part of the pixel  13 . This is distinguished from the first embodiment which required the AOI circuit block to perform the switching function.  
         [0033]    As shown in FIG. 6, a further modification to the second embodiment may be realized by noting that both the AOIR i  and RESET i  signals are common for all pixels in a given row. Since a pixel is held in “reset” if either of these signals is held low, transistor M 5  can be removed and transistor M 1  is then driven with a signal that is the logical OR of AOIRi and RESETi, while maintaining the same functionality as shown in FIG. 5.  
         [0034]    The second embodiment is advantageous in that the AOI function is performed as an integral part of the pixel. That is, it provides advantages over the first embodiment in that it removes the necessity of having additional circuitry (i.e., a separate AOI circuit block at the periphery of the array). A third embodiment further improves on the second embodiment by providing a further capability for disabling individual and/or particular blocks of pixels which constitute a number of pixels less than an entire row or column of pixels. In the previous embodiments, disablement can only occur at the resolution of an entire row or column. The third embodiment provides a capability for isolating less than a complete row or column for removal.  
         [0035]    [0035]FIG. 7 is an illustration of an array pixel  13  which provides the above stated capability. In the third embodiment, transistors M 4  and M 5  are connected in series. As shown, the gate of transistor M 4  receives a control signal AOIR i  from the row n-bit shift register. Also, the gate of transistor M 5  receives a control signal AOIC j  from the column n-bit AOI shift register. In the case where both control signals (i.e., AOIR i  and AOIC j ) are low, both transistors M 4  and M 5  are turned ‘on’ which causes the pixel  13  to be held in “reset”. That is, when both control signals are low, the V dd  voltage, which is maintained at the upper terminal of transistor M 4  is passed through the open switches (i.e., transistors M 4  and M 5 ) and appears at point A. When point A (the cathode of the diode  22 ) is at the V dd  voltage level, the gates of transistors M 2  and M 3  are high and therefore prevented from conducting and therefore contributing any current from pixel  13 . Conversely, if either control signal AOIR i  and AOIC j  is high, voltage V dd  cannot occur at point A. As such, the pixel  13  will contribute some current to the row and current summing lines.  
         [0036]    It is noted that the second and third embodiments differ from the first embodiment in their structure. In particular, the AOI function which is implemented by a plurality of AOI blocks in the first embodiment is alternatively implemented internally in each pixel element in the second and third embodiments thereby removing the necessity of including AOI structures in both the second and third embodiments.  
         [0037]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as falling within the true spirit and scope of the present invention.