Abstract:
Output circuit with reduced overshoot includes input end, output end, a circuit composed of PMOS and NMOS, rising and falling edge trigger bias circuits. The rising and falling edge trigger bias circuits output biasing voltages to the output end for clamping the voltage of the output signals respectively according to the rising edge and the falling edge of the input signal. In this way, the overshoot of the output signal is reduced.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an output circuit, and more particularly, to an output circuit with overshoot-reducing function. 
         [0003]    2. Description of the Prior Art 
         [0004]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional output circuit  100 . The output circuit  100  comprises an input end, an output end, an inverter INV 1 , delay circuits  110  and  120 , PMOS QP 1 , and NMOS QN 1 . 
         [0005]    The input end of the output circuit  100  receives an input signal D IN . The output end of the output circuit  100  outputs an output signal D OUT . It is assumed that the output end of the output circuit  100  is equivalently coupled to a capacitor C L . 
         [0006]    The PMOS Q P1  comprises a first end, a second end, and a control end. The NMOS Q N1  comprises a first end, a second end, and a control end. The inverter INV 1  is coupled between the input end of the output circuit  100 , and the delay circuits  110  and  120 . The delay circuit  110  is coupled between the inverter INV 1  and the control end of the PMOS Q P1 . The delay circuit  120  is coupled between the inverter INV 1  and the control end of the NMOS Q N1 . The first end of the PMOS Q P1  is coupled to a voltage source V DD  (supplying a voltage V DD ), the second end of the PMOS Q P1  is coupled to the output end of the output circuit  100 , and the control end of the PMOS Q P1  is coupled to the delay circuit  110 . The first end of the NMOS Q N1  is coupled to a voltage source V SS  (supply a voltage V SS ), the second of the NMOS Q N1  is coupled to the output end of the output circuit  100 , and the control end of the NMOS Q N1  is coupled to the delay circuit  120 . 
         [0007]    The inverter INV 1  is disposed for receiving the input signal D IN , inverting the received input signal D IN , and outputting the inverted input signal D IN . 
         [0008]    The delay circuit  110  is coupled between the inverter INV 1  and the control end of the PMOS Q P1  for receiving the inverted input signal D IN , delaying the received inverted input signal D IN  for a predetermined period DL 1 , and then inputting the delayed input signal D IN  to the control end of the PMOS Q P1  (the node D P ). The delay circuit  110  can be realized with an even number of the inverters coupled in series (the even number is “2m” as shown in  FIG. 1 ) for delaying the predetermined period DL 1 . 
         [0009]    The delay circuit  120  is coupled between the inverter INV 1  and the control end of the NMOS Q N1  for receiving the inverted input signal D IN , delaying the received inverted input signal D IN  for a predetermined period DL 2 , and then inputting the delayed input signal D IN  to the control end of the NMOS Q N1  (the node D N ). The delay circuit  120  can be realized with an even number of the inverters coupled in series (the even number is “2n” as shown in  FIG. 1 ) for delaying the predetermined period DL 2 . 
         [0010]    The voltage V DD  can be a high voltage, and the voltage V SS  can be ground. 
         [0011]    Additionally, the delay periods DL 1  and DL 2  are different, which means the numbers “2m” and “2n” of the inverters are different. The difference between the delay periods DL 1  and DL 2  avoids the PMOS Q P1  and the NMOS Q N1  being both turned on at the same time, which generates the current flows from the voltage source V DD  directly to the voltage source V SS . 
         [0012]    Please refer to  FIG. 2 .  FIG. 2  is a timing diagram illustrating the conventional output circuit  100 . As shown in  FIG. 2 , after the input signal D IN  is inputted, on the node D P , the signal inverted from the input signal D IN  and delayed for the predetermined period DL 1  is generated and inputted to the PMOS Q P1 . Meanwhile, on the node D N , the signal inverted from the input signal D IN  and delayed for the predetermined period DL 2  is generated and inputted to the NMOS Q N1 . In this way, the output signal D OUT  is generated by the PMOS Q P1  and the NMOS Q N1 . When the input signal D IN  is in a transient status (for example, in the period of the voltage of the signal D IN  changing from a high voltage to a low voltage, or vice versa), the voltage of the output signal D OUT  possibly rises over the voltage V DD  or falls over the voltage V SS , which is so-called overshoot, and damages the components in the circuit. 
         [0013]    A conventional method for reducing the overshoot problem is to couple a capacitor to the output end of the output circuit  100 . However, the capacitor on the output end lowers the slew rate of the output signal D OUT , and consequently the access speed of the output circuit  100  is also lowered. As the speed of internal components of systems increases, the demand for the speed of the memory is also increased. It is not satisfying the demand with just purely raising the frequency of the clock signal of the memories, and therefore the technologies of the Synchronous Dynamic Random Access Memory (SRAM), the Double Data Rate (DDR), and the second generation of the DDR (DDR2) have to be utilized to meet the demand. The frequencies of dies of the conventional memories equal to the frequencies of the input/output buffers (I/O buffers. However, the frequencies of the I/O buffers of the memories of the DDR2 technology is doubled than the frequencies of the cores of the memories. The method with adding capacitors to the output ends for reducing overshoots lowers the speed of the output circuit of the memory. 
         [0014]    Therefore, it is important to provide an innovative technology of Off-Chip Driver (OCD) with voltage-regulating circuits to reduce overshoots when the output circuit charges/discharges. 
       SUMMARY OF THE INVENTION 
       [0015]    The present invention provides an output circuit with overshoot-reducing function. The output circuit comprises an input end for receiving an input signal; an output end; a PMOS comprising a first end coupled to a first voltage source supplying a first voltage; a control end coupled to the input end; and a second end coupled to the output end; an NMOS comprising a first end coupled to a second voltage source supplying a second voltage; a control end coupled to the input end; and a second end coupled to the output end; a rising-edge trigger biasing circuit coupled between the input end and the output end for outputting a third voltage to the output end so as to reduce overshoot on the output end according to a rising edge of the input signal; and a falling-edge trigger biasing circuit coupled between the input end and the output end for outputting a fourth voltage to the output end so as to reduce overshoot on the output end according to a falling edge of the input signal; wherein the third voltage is higher than the second voltage, and the fourth voltage is lower than the first voltage. 
         [0016]    The present invention further provides an output circuit with overshoot-reducing function. The output circuit comprises an input end for receiving an input signal; an output end; a first switch coupled between a first voltage source supplying a first voltage and the output end for coupling the first voltage source to the output end; a second switch coupled between a second voltage source supplying a second voltage and the output end for coupling the second voltage source to the output end; a first trigger biasing circuit coupled between the input end, the output end and a third voltage source supplying a third voltage for outputting the third voltage to the output end according to a first status of the input signal; and a second trigger biasing circuit coupled between the input end, the output end and a fourth voltage source supplying a fourth voltage for outputting the fourth voltage to the output end according to a second status of the input signal; wherein the second switch is turned for coupling the second voltage source to the output end only after the first trigger biasing circuit outputs the third voltage to the output end for a first predetermined period, and the third voltage is different from the second voltage. 
         [0017]    The present invention further provides an output circuit with overshoot-reducing function. The output circuit comprises an input end for receiving an input signal; an output end; a first control device coupled between a first voltage source supplying a first predetermined voltage and the output end for coupling the first voltage source to the output end; and a second control device coupled between a second voltage source supplying a second predetermined voltage and the output end for coupling the second voltage source to the output end; wherein the first control device couples the first voltage source to the output end only after the second control device outputs the second predetermined voltage to the output end for a first predetermined period, and the first predetermined voltage is different from the second predetermined voltage. 
         [0018]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0019]      FIG. 1  is a diagram illustrating a conventional output circuit. 
           [0020]      FIG. 2  is a timing diagram illustrating the conventional output circuit. 
           [0021]      FIG. 3  is a diagram illustrating the output circuit of the present invention. 
           [0022]      FIG. 4  is a timing diagram illustrating the output circuit of the present invention. 
           [0023]      FIG. 5  is a diagram illustrating one switch of the present invention. 
           [0024]      FIG. 6  is a diagram illustrating another switch of the present invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0025]    Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating the output circuit  300  of the present invention. The output circuit  300  comprises an input end, an output end, an inverter INV 1 , delay circuits  110  and  120 , PMOS QP 1 , NMOS QN 1 , a falling-edge trigger biasing circuit  310 , and a rising-edge trigger biasing circuit  320 . 
         [0026]    The input end of the output circuit  300  receives an input signal D IN . The output end of the output circuit  300  outputs an output signal D OUT . It is assumed that the output end of the output circuit  300  is equivalently coupled to a capacitor C L . 
         [0027]    The PMOS Q P1  comprises a first end, a second end, and a control end. The NMOS Q N1  comprises a first end, a second end, and a control end. The inverter INV 1  is coupled between the input end of the output circuit  100 , and the delay circuits  110  and  120 . The delay circuit  110  is coupled between the inverter INV 1  and the control end of the PMOS Q P1 . The delay circuit  120  is coupled between the inverter INV 1  and the control end of the NMOS Q N1 . The first end of the PMOS Q P1  is coupled to a voltage source V DD  (supplying a voltage V DD ), the second end of the PMOS Q P1  is coupled to the output end of the output circuit  300 , and the control end of the PMOS Q P1  is coupled to the delay circuit  110 . The first end of the NMOS Q N1  is coupled to a voltage source V SS  (supply a voltage V SS ), the second of the NMOS Q N1  is coupled to the output end of the output circuit  300 , and the control end of the NMOS Q N1  is coupled to the delay circuit  120 . The falling-edge trigger biasing circuit comprises a falling-edge trigger circuit  301  and a biasing circuit  311 . The falling-edge trigger circuit  301  is coupled between the input end of the output circuit  300  and the biasing circuit  311 . The biasing circuit  311  is coupled between the falling-edge trigger circuit  301  and the output end of the output circuit  300 . The rising-edge trigger biasing circuit comprises a rising-edge trigger circuit  302  and a biasing circuit  321 . The rising-edge trigger circuit  302  is coupled between the input end of the output circuit  300  and the biasing circuit  321 . The biasing circuit  321  is coupled between the rising-edge trigger circuit  302  and the output end of the output circuit  300 . The biasing circuit  311  comprises a switch SW 1  and a voltage source V 1  supplying a voltage V 1 . The switch SW 1  comprises a first end  1 , a second end  2 , and a control end C. The first end  1  of the switch SW 1  is coupled to the voltage source V 1 , the second end  2  of the switch SW 1  is coupled to the output end of the output circuit  300 , and the control end C of the switch SW 1  is coupled to the falling-edge trigger circuit  301 . The biasing circuit  321  comprises a switch SW 2  and a voltage source V 2  supplying a voltage V 2 . The switch SW 2  comprises a first end  1 , a second end  2 , and a control end C. The first end  1  of the switch SW 2  is coupled to the voltage source V 2 , the second end  2  of the switch SW 2  is coupled to the output end of the output circuit  300 , and the control end C of the switch SW 2  is coupled to the rising-edge trigger circuit  302 . 
         [0028]    The inverter INV 1  is disposed for receiving the input signal D IN , inverting the received input signal D IN , and outputting the inverted input signal D IN . 
         [0029]    The delay circuit  110  is coupled between the inverter INV 1  and the control end of the PMOS Q P1  for receiving the inverted input signal D IN , delaying the received inverted input signal D IN  for a predetermined period DL 1 , and then inputting the delayed input signal D IN  to the control end of the PMOS Q P1  (the node D P ). The delay circuit  110  can be realized with an even number of the inverters coupled in series (the even number is “2m” as shown in  FIG. 1 ) for delaying the predetermined period DL 1 . 
         [0030]    The delay circuit  120  is coupled between the inverter INV 1  and the control end of the NMOS Q N1  for receiving the inverted input signal D IN , delaying the received inverted input signal D IN  for a predetermined period DL 2 , and then inputting the delayed input signal D IN  to the control end of the NMOS Q N1  (the node D N ). The delay circuit  120  can be realized with an even number of the inverters coupled in series (the even number is “2n” as shown in  FIG. 1 ) for delaying the predetermined period DL 2 . 
         [0031]    The voltage V DD  can be a high voltage, and the voltage V SS  can be ground. The voltage V 1  is lower than the voltage V DD  in principle, for example, the voltage V 1  can be in the range between the average of the voltages V DD  and V SS  and the voltage V DD . The voltage V 2  is higher than the voltage V SS  in principle, for example, the voltage V 2  can be in the range between the average of the voltages V DD  and V SS  and the voltage V SS . 
         [0032]    The falling-edge trigger circuit  301  triggers a pulse signal P F  with a predetermined period on the node S F  according to the input signal D IN . More particularly, the falling-edge trigger circuit  301  triggers a pulse signal with the predetermined period P F  on the node S F  when the input signal D IN  in the transient status that the voltage of the input signal D IN  falls from the high voltage to the low voltage (falling edges). The pulse signal P F  is transmitted to the control end C of the switch SW 1 . When the switch SW 1  does not receive the pulse signal P F , the first end  1  of the switch SW 1  is not coupled to the second end  2  of the switch SW 1 . That is, the voltage source V 1  does not transmit the voltage V 1  to the output end of the output circuit  300 , and thus the output signal D OUT  is not affected. When the switch SW 1  receives the pulse signal P F , the first end  1  of the switch SW 1  is coupled to the second end  2  of the switch SW 1 . That is, the voltage source V 1  transmits the voltage V 1  to the output end of the output circuit  300 , and thus the output signal D OUT  is affected. More particularly, at the time, the output signal D OUT  is clamped at the voltage V 1  for reducing the overshoots. In the conventional output circuit  100 , the output signal D OUT , at the time, steps down from the high voltage to the low voltage, which generates the overshoots. However, in the output circuit  300  of the present invention, the output signal D OUT , at the time, is clamped at the voltage V 1  by the falling-edge trigger circuit  310 , and the overshoots are reduced. The period of the pulse signal P F  can be designed according to the periods DL 1  and DL 2 . In one embodiment, the period of the pulse signal P F  can be designed to be shorter than the period of the transient status of the input signal D IN  for avoid generating the output signal D OUT  incorrectly. In another embodiment, the period of the pulse signal P F  can be designed to be longer than the entire period that the unstable overshoots are generated on the output signal D OUT , for example, the entire period of the transient status of the input signal D IN  changing from the high voltage to the low voltage. In this way, the overshoots on the output signal can be completely reduced. 
         [0033]    The rising-edge trigger circuit  302  triggers a pulse signal with a predetermined period P R  on the node S R  according to the input signal D IN . More particularly, the rising-edge trigger circuit  302  triggers a pulse signal P R  with the predetermined period on the node S F  when the input signal D IN  in the transient status that the voltage of the input signal D IN  rises from the low voltage to the high voltage (rising edges). The pulse signal P F  is transmitted to the control end C of the switch SW 2 . When the switch SW 2  does not receive the pulse signal P R , the first end  1  of the switch SW 2  is not coupled to the second end  2  of the switch SW 2 . That is, the voltage source V 2  does not transmit the voltage V 2  to the output end of the output circuit  300 , and thus the output signal D OUT  is not affected. When the switch SW 2  receives the pulse signal P R , the first end  1  of the switch SW 2  is coupled to the second end  2  of the switch SW 2 . That is, the voltage source V 2  transmits the voltage V 2  to the output end of the output circuit  300 , and thus the output signal D OUT  is affected. More particularly, at the time, the output signal D OUT  is clamped at the voltage V 2  for reducing the overshoots. In the conventional output circuit  100 , the output signal D OUT , at the time, steps up from the low voltage to the high voltage, which generates the overshoots. However, in the output circuit  300  of the present invention, the output signal D OUT , at the time, is clamped at the voltage V 2  by the rising-edge trigger circuit  320 , and the overshoots are reduced. The period of the pulse signal P R  can be designed according to the periods DL 1  and DL 2 . In one embodiment, the period of the pulse signal P R  can be designed to be shorter than the period of the transient status of the input signal D IN  for avoid generating the output signal D OUT  incorrectly. In another embodiment, the period of the pulse signal P R  can be designed to be longer than the entire period that the unstable overshoots are generated on the output signal D OUT , for example, the entire period of the transient status of the input signal D IN  changing from the low voltage to the high voltage. In this way, the overshoots on the output signal can be completely reduced. 
         [0034]    Additionally, the delay periods DL 1  and DL 2  are different, which means the numbers “2m” and “2n” of the inverters are different. The difference between the delay periods DL 1  and DL 2  avoids the PMOS Q P1  and the NMOS Q N1  being both turned on at the same time, which generates the current flows from the voltage source V DD  directly to the voltage source V SS . 
         [0035]    Please refer to  FIG. 4 .  FIG. 4  is a timing diagram illustrating the output circuit  300  of the present invention. As shown in  FIG. 4 , after the input signal D IN  is inputted, on the node D P , the signal inverted from the input signal D IN  and delayed for the predetermined period DL 1  is generated and inputted to the PMOS Q P1 . Meanwhile, on the node D N , the signal inverted from the input signal D IN  and delayed for the predetermined period DL 2  is generated and inputted to the NMOS Q N1 . 
         [0036]    In one embodiment of the present invention, when the input signal D IN  falls from the high voltage to the low voltage, the falling-edge trigger circuit  301  generates the pulse signal P F  on the node S F  for turning on the switch SW 1  so as to allow the output signal D OUT  to receive the voltage V 1 . After the switch SW 1  is turned on, the inverted inputted signal D IN  turns on the NMOS Q N1 . In this way, the voltage difference between the first end and the second end of the NMOS Q N1  reduces to (V 1 −V SS ) and the overshoot is consequently reduced. When the input signal D IN  rises from the low voltage to the high voltage, the rising-edge trigger circuit  302  generates the pulse signal P R  on the node S R  for turning on the switch SW 2  so as to allow the output signal D OUT  to receive the voltage V 2 . After the switch SW 2  is turned on, the inverted inputted signal D IN  turns on the PMOS Q P1 . In this way, the voltage difference between the first end and the second end of the PMOS Q P1  reduces to (V DD −V 2 ) and the overshoot is consequently reduced. 
         [0037]    Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating the switch SW 1  of the present invention. As shown in  FIG. 5 , the switch SW 1  comprises an inverter INV 2 , a PMOS Q P2  and an NMOS Q N2 . The PMOS Q P2  comprises a first end, a second end, and a third end. The NMOS Q N2  comprises a first end, a second end, and a third end. The inverter INV 2  comprises an input end and an output end. The input end of the inverter INV 2  is coupled to the control end C of the switch SW 1  for receiving the pulse signal P F  transmitted from the falling-edge trigger circuit  301 , and the inverter INV 2  accordingly generates the inverted pulse signal P F . The first end of the PMOS Q P2  is coupled to the first end of the switch SW 1  for coupling to the voltage source V 1 . The second end of the PMOS Q P2  is coupled to the second end of the switch SW 1  for coupling to the output end of the output circuit  300 . The control end of the PMOS Q P2  is coupled to the output end of the inverter INV 2  for receiving the inverted pulse signal P F . When the PMOS Q P2  receives the inverted pulse signal P F , the first end of the PMOS Q P2  is coupled to the second end of the PMOS Q P2  for transmitting the voltage V 1  to the output end of the output circuit  300 . The first end of the NMOS Q N2  is coupled to the first end of the switch SW 1  for coupling to the voltage source V 1 . The second end of the NMOS Q N2  is coupled to the second end of the switch SW 1  for coupling to the output end of the output circuit  300 . The control end of the NMOS Q N2  is coupled to the control end C of the switch SW 1  for receiving the pulse signal P F . When the NMOS Q N2  receives the pulse signal P F , the first end of the NMOS Q N2  is coupled to the second end of the NMOS Q N2  for transmitting the voltage V 1  to the output end of the output circuit  300 . In another embodiment of the present invention, a terminated resistor can be disposed between the first end of the switch SW 1  and the voltage source V 1  for increasing the integrity of the signal. The terminated resistor can be a normal resistor or a MOS resistor. 
         [0038]    Please refer to  FIG. 6 .  FIG. 6  is a diagram illustrating the switch SW 2  of the present invention. As shown in  FIG. 6 , the switch SW 2  comprises an inverter INV 3 , a PMOS Q P3  and an NMOS Q N3 . The PMOS Q P3  comprises a first end, a second end, and a third end. The NMOS Q N3  comprises a first end, a second end, and a third end. The inverter INV 3  comprises an input end and an output end. The input end of the inverter INV 3  is coupled to the control end C of the switch SW 2  for receiving the pulse signal P R  transmitted from the rising-edge trigger circuit  302 , and the inverter INV 3  accordingly generates the inverted pulse signal P R . The first end of the PMOS Q P3  is coupled to the first end of the switch SW 2  for coupling to the voltage source V 2 . The second end of the PMOS Q P3  is coupled to the second end of the switch SW 2  for coupling to the output end of the output circuit  300 . The control end of the PMOS Q P3  is coupled to the output end of the inverter INV 3  for receiving the inverted pulse signal P R . When the PMOS Q P3  receives the inverted pulse signal P R , the first end of the PMOS Q P3  is coupled to the second end of the PMOS Q P3  for transmitting the voltage V 2  to the output end of the output circuit  300 . The first end of the NMOS Q N3  is coupled to the first end of the switch SW 2  for coupling to the voltage source V 2 . The second end of the NMOS Q N3  is coupled to the second end of the switch SW 2  for coupling to the output end of the output circuit  300 . The control end of the NMOS Q N3  is coupled to the control end C of the switch SW 2  for receiving the pulse signal P R . When the NMOS Q N3  receives the pulse signal P R , the first end of the NMOS Q N3  is coupled to the second end of the NMOS Q N3  for transmitting the voltage V 2  to the output end of the output circuit  300 . In another embodiment of the present invention, a terminated resistor can be disposed between the first end of the switch SW 2  and the voltage source V 2  for increasing the integrity of the signal. The terminated resistor can be a normal resistor or a MOS resistor. 
         [0039]    To sum up, the output circuit provided by the present invention, with the falling-edge trigger circuit, rising-edge trigger circuit, and voltage sources, reduces the overshoot problem on the output signal so as to reduce the damage to the components, which provides great convenience. 
         [0040]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.