Abstract:
An electrostatic discharge protection circuit, comprising a semiconductor-controlled rectifier and a PMOS device. The semiconductor-controlled rectifier, coupled between two nodes, has an N-type semiconductor layer. The PMOS device, integrated with the semiconductor-controlled rectifier to share a first P-type doped region, has a PNP device located in the N-type semiconductor layer. When one of the nodes is coupled to the electrostatic discharge power, the PNP device will conduct to trigger the semiconductor-controlled rectifier.

Description:
The present application is a continuation-in-part of U.S. application Ser. No. 09/223,652, filed Dec. 30, 1998, now U.S. Pat. No. 6,147,369. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a semiconductor integrated circuit technique. More particularly, it relates to an electrostatic discharge protection circuit applied to a semiconductor integrated circuit, which is triggered to conduct through PNP bipolar action. 
     DESCRIPTION OF THE PRIOR ART 
     In the processes of measuring, assembling, installing and using an integrated circuit, Electrostatic Discharge (ESD) is unavoidable and may cause damage to integrated circuits. At present, there are many models explaining the causes of ESD, wherein the human body model is most common. The human body model refers to the ESD pulse caused by a human body&#39;s contact with the pins of an integrated circuit. Since the ESD pulse of the human body model lasts longest, the makers use this as a standard for integrated circuit ESD protection. 
     With the adoption of the Lightly Doped Drain (LDD) structure and the self-aligned mental salicide diffusion production process, the Lateral Semiconductor Controlled Rectifier has been applied as an ESD protection circuit in CMOS integrated circuits, as disclosed in U.S. Pat. No. 5,012,317. The Lateral Semiconductor Controlled Rectifier, disclosed in U.S. Pat. No. 5,012,317, is triggered by a P/N junction breakdown between the well region and the base. However, in practical applications, the trigger voltage is above 30V. For sub-micron or half-micron COMS devices, the gate oxide is damaged by this trigger voltage. Therefore, the Lateral Semiconductor Controlled Rectifier of the prior art doesn&#39;t provide effective ESD protection. 
     To reduce the trigger voltage, U.S. Pat. No. 5,465,189 provides a semiconductor controlled rectifier triggered by a low voltage. It uses a device similar to NMOS to provide a thickly doped region across the junction between the well region and the base. When the ESD occurs, the junction breakdown of the thickly doped region of the device causes the semiconductor controlled rectifier to be triggered to conduct; thereby, the trigger voltage of the ESD protection circuit is reduced. However, if the diffusion production process of the self-aligned mental salicide is applied to the source or drain of the device, the effect of ESD protection will be reduced. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide an ESD protection circuit for semiconductor integrated circuits, which triggers the semiconductor controlled rectifier by using the PMOS device through PNP bipolar action. According to the invention, the ESD protection circuit offers the advantages of ESD protection and compatibility with the self-aligned mental salicide diffusion production process. 
     To achieve the above-mentioned object, the present invention provides an ESD protection circuit. The ESD protection circuit comprises a semiconductor controlled rectifier and a PMOS device. The semiconductor controlled rectifier coupled between two nodes has an N-type semiconductor layer. The PMOS device shares a first P-type doped region with the semiconductor controlled rectifier and comprises a PNP device located in the N-type semiconductor layer. When one of the nodes is coupled to the ESD power, the PNP device will conduct to trigger the semiconductor controlled rectifier. 
     Therefore, since the semiconductor controlled rectifier conduction is triggered to conduct through the PNP bipolar action, the ESD protection circuit has the advantages of ESD protection and compatibility with the self-aligned mental salicide diffusion production process. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention can be more fully understood from the following detailed description and preferred embodiments with reference to the accompanying drawings in which: 
     FIG. 1 is a cross section of a first preferred embodiment of the ESD protection circuit according to the invention; 
     FIG. 2 is an equivalent circuit diagram of FIG. 1; 
     FIG. 3 is a cross section of a second preferred embodiment of the ESD protection circuit according to the invention; 
     FIG. 4 is a cross section of a third preferred embodiment of the ESD protection circuit according to the invention; 
     FIG. 5 is an equivalent circuit diagram of FIG. 4; and 
     FIG. 6 is a cross section of a fourth preferred embodiment of the ESD protection circuit according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     According to the invention, an ESD protection circuit for semiconductor integrated circuits is provided, which uses a PMOS device to trigger the semiconductor controlled rectifier through PNP bipolar action. In other words, by using the characteristics of PMOS devices, the ESD protection circuit has the advantages of ESD protection and compatibility with the self-aligned mental salicide diffusion production process. 
     The ESD protection circuit according to the invention is compatible with the CMOS production process; that is, the techniques such as N-type well region/P-type base, P-type well region/N-type base, or twin-well region can be adopted. All the following embodiments take N-type well region/P-type base as an example, but this is not intended to limit the scope of the invention, and those persons skilled in the art should know that the ESP protection circuit is also applied to P-type well region/N-type base, or twin-well region. 
     First Embodiment 
     Refer to FIG. 1, which shows a cross section of a first preferred embodiment of the ESD protection circuit according to the invention, wherein the reference number  10  represents a P-type semiconductor base  10 . An N-type well region  11  is located in a predetermined location in the P-type semiconductor base. A P + -type doped region  12  is located in the N-type well region  11 , and an N + -type doped region  13  is located in the P-type semiconductor base  10 . 
     Further, the N + -type doped region  14  and the P + -type doped region  12  are located separated from each other in the N-type well region to be the ohmic contact region of the N-type well region  11 . A P + -type doped region  15  located in the P-type semiconductor base  10  is the ohmic contact region of the P-type semiconductor base  10 . The N + -type doped region  13  and the P + -type doped region  15  can be located on the same side of the N-type well region  11 , or separately on both sides of the N-type well region  11  as shown in FIG.  1 . 
     As shown in FIG. 1, the P + -type doped region  12  and the N + -type doped region  14  are coupled to be a node  1 , and the N + -type doped region  13  and the P + -type doped region  15  are coupled to be a node  2 . The nodes  1  and  2  can be respectively coupled to a junction pad (input junction pad, output junction pad, input/output junction pad) and the V SS  power rail, respectively coupled to the V DD  power rail and a junction pad, or respectively coupled to the V DD  power rail and the V SS  power rail. 
     Further, a P + -type doped region  16  is located in the N-type well region  11  separated from the P + -type doped region  12  and coupled to the node  2 . Specifically, the P + -type doped region  16 , the P + -type doped region  12 , and a part of the N-type well region  11  in between construct a PNP transistor  18 . Preferably, the P + -type doped region  16  and the N + -type doped region  14  are separately located on both sides of the P + -type doped region  12 , as shown in FIG.  1 . Further, between the P + -type doped region  16  and the P + -type doped region  12  a gate  17  is located, and the gate  17  is coupled to a node  3  which can be coupled to the V DD  power rail. 
     Therefore, the P + -type doped region  12 , the N-type well region  11  and the P-type semiconductor base  10  respectively construct the emitter, the base, and the collector of a PNP bipolar junction transistor  20 . The N-type well region  11 , the P-type semiconductor base  10 , and the N + -type doped region  13  respectively construct the collector, the base, and the emitter of an NPN bipolar junction transistor  21 . In other words, the P + -type doped region  12 , the N-type well region  11 , the P-type semiconductor base  10 , and the N + -type doped region  13  construct a semiconductor controlled rectifier  4 ; the P + -type doped region  12  and the N + -type doped region  13  are respectively the anode and the cathode of the semiconductor controlled rectifier  4 . FIG. 2 is an equivalent circuit diagram of FIG. 1, wherein the resistors  22  and  23  respectively represent the spreading resistance of the N-type well region  11  and the P-type semiconductor base  10 . 
     Further, the PMOS device  5  shown in FIG. 2 is constructed by the gate  17 , the P + -type doped region  16 , and the P + -type doped region  12 , so the P + -type doped regions  16  and  12  are the source/drain pair of the PMOS device  5 . In other words, the P + -type doped region  12  is a common region of the semiconductor controlled rectifier  4  and the PMOS device  5 . 
     When ESD stress occurs at the node  1 , the PMOS device  5  will breakdown and further trigger the semiconductor controlled rectifier  4  to conduct. The trigger is activated when the PNP transistor  18  (parasitic in the PMOS device  5 ) conducts, further triggering the semiconductor controlled rectifier  4  to cause a snapback, conducting the current path between the nodes  1  and  2 , releasing the ESD stress at the node  1 , and clamping the voltage between the nodes  1  and  2  to the holding voltage of the semiconductor controlled rectifier  4 . 
     Second Embodiment 
     Refer to FIG. 3, which shows a cross section of a second preferred embodiment of the ESD protection circuit according to the invention. In this example, the P + -type doped regions  15  and  16  of the first embodiment are integrated to be a single common region  156 . The P + -type common region  156  overlies the junction between the N-type well region  11  and the P-type base  10 . 
     Third Embodiment 
     Refer to FIG. 4, which shows a cross section of a third preferred embodiment of the ESD protection circuit according to the invention, wherein the reference number  10  represents a P-type semiconductor base. An N-type well region  11  is located in the predetermined location in the P-type semiconductor base  10 . A P + -type doped region  12  is located in the N-type well region  11 , and an N + -type doped region  13  is located in the P-type semiconductor base  10 . 
     Further, the N-type well region  11  without the ohmic contact region is in a floating state. The P + -type doped region  15  located in the P-type semiconductor base  10  is the ohmic contact region of the P-type semiconductor base  10 . The N + -type doped region  13  and the P + -type doped region  15  can be on the same side of the N-type well region  11 , or separately on both sides of the N-type well region  11  as shown in FIG.  1 . 
     As shown in FIG. 4, the P + -type doped region  12  is coupled to a node  1 , and the N + -type doped region  13  and the P + -type doped region  15  are coupled to be a node  2 . The nodes  1  and  2  can be respectively coupled to a junction pad (input junction pad, output junction pad, input/output junction pad) and the V SS  power rail, respectively coupled to the V DD  power rail and the junction pad, or respectively coupled to the V DD  power rail and the V SS  power rail. 
     Further, a P + -type doped region  16  is located in the N-type well region  11  separated from the P + -type doped region  12  and coupled to the node  2 . Especially, the P + -type doped region  16 , the P + -type doped region  12 , and a part of the N-type well region  11  in between construct a PNP transistor  18 . Further, located between the P + -type doped region  16  and the P + -type doped region  12 , a gate  17  is coupled to a node  3  which can be coupled to the V DD  power rail. 
     Therefore, the P + -type doped region  12 , the N-type well region  11 , and the P-type semiconductor base  10  may respectively construct the emitter, the base and the collector of a PNP bipolar junction transistor  20 . The N-type well region  11 , the P-type semiconductor base  10 , the N + -type doped region  13  may respectively construct the collector, the base, and the emitter of an NPN bipolar junction transistor  21 . In other words, the P + -type doped region  12 , the N-type well region  11 , the P-type semiconductor base  10 , and the N + -type doped region  13  construct a semiconductor controlled rectifier  6 ; the P + -type doped region  12  and the N + -type doped region  13  are respectively the anode and the cathode of the semiconductor controlled rectifier  6 . FIG. 5 is an equivalent circuit diagram of FIG. 4, wherein the resistor  23  represents the spreading resistance of the P-type semiconductor base  10 . 
     Further, the PMOS device  7  shown in FIG. 5 is constructed by the gate  17 , the P + -type doped region  16  and the P + -type doped region  12 , so the P + -type doped regions  16  and  12  are the source/drain pair of the PMOS device  5 . In other words, the P + -type doped region  12  is a common region of the semiconductor controlled rectifier  6  and the PMOS device  7 . 
     When ESD stress occurs at the node  1 , PMOS device  7  will have a breakdown and further trigger the semiconductor controlled rectifier  4  to conduct. The trigger is activated when the PNP transistor  18  (parasitic in the PMOS device  5 ) conducts, triggering the semiconductor controlled rectifier  6  to cause a snapback, conducting the current path between the nodes  1  and  2 , releasing the ESD stress at the node  1 , and clamping the voltage between the nodes  1  and  2  to the holding voltage of the semiconductor controlled rectifier  6 . 
     Since there is no ohmic contact region between the N-type well region  11  and the node  1 , the N-type region  11  is in a floating state. Therefore, the holding voltage of the semiconductor controlled rectifier  6  is lower than that of the semiconductor controlled rectifier  4  of FIG.  1 . 
     Fourth Embodiment 
     Refer to FIG. 6, which according to the invention shows a cross section of a fourth preferred embodiment of the ESD protection circuit. In this example, the P + -type doped regions  15  and  16  of the third embodiment are integrated to be a single common region  156  which overlies the junction between the N-type well region  11  and the P-type base  10 . 
     To sum up the above-mentioned, the ESD protection circuit according to the invention uses a PMOS device to trigger the semiconductor controlled rectifier through PNP bipolar action, so the ESD circuit has the advantages of ESD protection and compatibility with the self-aligned mental salicide diffusion production process. 
     While the invention has been described with reference to various illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as may fall within the scope of the invention defined by the following claims and their equivalents.