Abstract:
An improved bi-directional transient blocking unit (TBU) is provided having a dual-gate central transistor. The gates of the central transistor are connected to the rest of the TBU such that high voltages can only appear between a gate and the central transistor terminal further from that gate. In this manner, the total device size required to provide a given breakdown voltage can be significantly reduced compared to a conventional symmetric lateral transistor having a single gates.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of U.S. provisional patent application 60/860,528, filed on Nov. 21, 2006, entitled “Dual gate GaN transient blocking units”, and hereby incorporated by reference in its entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to suppression of electrical transients. 
       BACKGROUND 
       [0003]    It has long been known that electrical circuits and devices can be damaged by electrical transients at their inputs. Accordingly, transient suppression has been extensively investigated, and various approaches have been developed to date. One such approach is the use of a transient blocking unit (TBU), which is an arrangement of two or more normally-on transistors configured to switch off current flow in response to an over-voltage or over-current condition. One early reference describing TBUs is U.S. Pat. No. 5,742,463, by Richard A. Harris. TBUs are placed in series with the load being protected. 
         [0004]      FIG. 1  shows an example of a prior art transient blocking unit. In this example, an electrical load  104  is connected to an electrical source  102  via a TBU circuit including transistors Q 1 , Q 2 , and Q 3 . Operation of the example of  FIG. 1  depends on the polarity of I TBU . For one polarity (e.g., positive), transistors Q 1  and Q 3  provide transient blocking, while for the other polarity (e.g., negative), transistors Q 2  and Q 3  provide transient blocking. For a current polarity where Q 1  and Q 3  are the relevant transistors, passage of I TBU  through Q 1  and Q 3  generates gate voltages at Q 1  and Q 3  that tend to turn both transistors off. If I TBU  exceeds a predetermined threshold, the positive feedback inherent in this arrangement acts to rapidly switch the TBU off, thereby protecting load  104  from an over-voltage or over-current condition. For the other current polarity, transistors Q 2  and Q 3  cooperate in the same way to provide transient blocking. 
         [0005]    In many cases of interest, it is desirable for TBUs to be able to withstand high voltages in the current blocking state. One known configuration is where transistors Q 1  and Q 2  on  FIG. 1  are high voltage transistors, and Q 3  is a low voltage transistor. However, the cost of such TBUs tends to be significantly driven by the cost of the high voltage TBU transistors. Accordingly, it would be an advance in the art to provide high voltage TBUs having improved cost-effectiveness. 
       SUMMARY 
       [0006]    An improved bi-directional TBU is provided having a dual-gate central transistor. The gates of the central transistor are connected to the rest of the TBU such that high voltages can only appear between a gate and the central transistor terminal further from that gate. In this manner, the total device size required to provide a given breakdown voltage can be significantly reduced compared to a conventional symmetric lateral transistor having a single gate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0007]      FIG. 1  shows a prior art TBU. 
           [0008]      FIG. 2  shows an illustrative transistor device geometry. 
           [0009]      FIG. 3   a  shows a TBU according to an embodiment of the invention. 
           [0010]      FIG. 3   b  shows an illustrative transistor device geometry suitable for use in embodiments of the invention. 
           [0011]      FIG. 3   c  shows an exemplary device structure corresponding to the embodiment of  FIG. 3   a.    
           [0012]      FIG. 4   a  shows dual gate geometry corresponding to the embodiment of  FIG. 3   a.    
           [0013]      FIG. 4   b  shows a connection of a dual gate transistor that is not suitable for practicing the invention. 
           [0014]      FIG. 5  shows a TBU according to a preferred embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0015]    In order to better appreciate the present invention, it is helpful to consider the implications of designing the circuit of  FIG. 1  to operate at high voltages by having Q 3  be a high voltage (HV) transistor and Q 1  and Q 2  be low voltage transistors. In such a situation, Q 3  would need to have a high breakdown voltage between gate and source for one polarity of I TBU  and it would also need to have a high breakdown voltage between gate and drain for the other polarity of I TBU . More briefly, Q 3  would need to have substantially symmetric breakdown voltages from its terminals (i.e., source or drain) to its gate. 
         [0016]    Such symmetry of breakdown voltages is not often encountered in practice. Many high voltage transistors have a vertical geometry, where it is difficult or even impossible to design for symmetric breakdown voltages. In lateral device designs, it is easier to provide symmetric breakdown voltages, but the resulting designs tend to lead to costly devices. 
         [0017]    This issue can be appreciated in connection with  FIG. 2 , which shows an illustrative lateral transistor device geometry. A transistor  110  has a source (or drain)  114 , a drain (or source)  116 , and a gate  118 . Terminals  114  and  116  act as source and drain respectively, or as drain and source respectively, depending on applied voltage. The transistor operates by controlling flow of a flow of current between source  114  and drain  116  in a channel  112 . A substantial gate to drain separation L 1  is required for the device of  FIG. 2  to have a high gate to drain breakdown voltage when terminal  114  acts as the drain. Similarly, a substantial gate to drain separation L 2  is required for the device of  FIG. 2  to have a high gate to drain breakdown voltage when terminal  116  acts as the drain. Thus the total channel length must be at least L 1 +L 2 , which tends to make the device of  FIG. 2  undesirably large and expensive. 
         [0018]    This issue of large device size is one of the main reasons that known high voltage TBU circuits tend to have the two outer transistors (e.g., Q 1  and Q 2  on  FIG. 1 ) being high voltage devices, as opposed to the apparently simpler approach of having only the center transistor be a high voltage device. The outer transistors of such a conventional HV TBU do not need to have symmetric breakdown voltages, so conventional HV design approaches are applicable (e.g., vertical transistors). 
         [0019]    However, it is possible to significantly alleviate the issue of large device size for a center HV transistor in a TBU by exploiting the following property of the TBU application: it is not required for the center transistor in a TBU to simultaneously provide high breakdown voltages between the gate and both other terminals T 1  and T 2 . Instead, at some times (i.e., when T 1  is acting as the drain) a high gate to T 1  breakdown voltage is needed, and at other times (i.e., when T 2  is acting as the drain), a high gate to T 2  breakdown voltage is needed, depending on the polarity of the transient being blocked. 
         [0020]      FIG. 3   a  shows a TBU according to an embodiment of the invention. A key aspect of this example is transistor Q 6  being a dual-gate transistor and having gates G 3  and G 4 . Since practice of the invention does not depend critically on the difference between source and drain, the drain/source terminals of the transistors are labeled as follows: transistor Q 4  has terminals T 1  and T 2 , transistor Q 5  has terminals T 3  and T 4 , and transistor Q 6  has terminals T 5  and T 6 . Transistors Q 4  and Q 5  have gates G 1  and G 2  respectively. Transistors Q 4 , Q 5 , and Q 6  are all depletion mode transistors. Gate G 1  controls a first current between terminals T 1  and T 2 . Gate G 2  controls a second current between terminals T 3  and T 4 . Gates G 3  and G 4  are independent and both control a third current between terminals T 5  and T 6 . 
         [0021]    Terminal T 2  is connected to T 5 , and T 6  is connected to T 3 , so the three transistors are connected in series. The gate connections are as follows: G 1  is connected to T 3 , G 2  is connected to T 2 , G 3  is connected to T 1 , and G 4  is connected to T 4 . Terminals T 1  and T 4  are the input/output terminals of the TBU, which provides an automatic shut-off function of a controllable current from T 1  to T 4  responsive to an over-voltage or over-current condition. The TBU is thereby capable of protecting a load  104  from over-voltage or over-current conditions. 
         [0022]    The significance of this example can be better appreciated in connection with  FIG. 3   b , which shows an illustrative transistor device geometry corresponding to the embodiment of  FIG. 3   a . Here transistor  202  has a source/drain  204 , a drain/source  206 , and two gates  208  and  210 . In cases where terminal  206  acts as the drain, gate  208  should be the relevant gate, and L 2  is the relevant gate to drain distance. In cases where terminal  204  acts as the drain, gate  210  should be the relevant gate, and L 1  is the relevant gate to drain distance. In this manner, the total channel length required to provide large separation between gate and drain can be substantially reduced in a symmetric device geometry where source and drain are reversible. More specifically, the distances L 1  and L 2  on  FIG. 3   b  overlap, in sharp contrast to the situation of  FIG. 2 , where there is no overlap of the relevant separations. 
         [0023]    Suppose that a gate to terminal separation of at least L min  is required to provide a specified breakdown voltage. With the arrangement of  FIG. 2 , the required total channel length of the device would be at least 2L min . With the improved arrangement of  FIG. 3 , the required total channel length of the device would be slightly more than L min . Reducing the channel length of a HV device by about a factor of two in this manner can provide significant cost advantages. 
         [0024]    In TBUs according to embodiments of the invention, it is preferred for the center transistor to be a high voltage transistor (e.g., breakdown voltage &gt;50 V, more preferably breakdown voltage &gt;100 V) as opposed to a low voltage device. It is further preferred for the center transistor to be a GaN high voltage transistor, such as a high electron mobility transistor (HEMT) or a metal-semiconductor field effect transistor (MESFET). The GaN material system is preferred for the center transistor, because it is difficult/costly to fabricate high performance HV lateral FETs in Silicon. For example, providing breakdown voltages above 50 V in a Silicon JFET tends to be highly cost ineffective. However, practice of the invention does not depend critically on material system or transistor type. 
         [0025]      FIG. 3   c  shows an exemplary GaN HEMT device structure suitable for use in embodiments of the invention. In this example, source and drain  204  and  206 , as well as gates  208  and  210  are disposed on an n-type AlGaN layer  212 , which in turn is disposed on an undoped GaN substrate  214 . Passivation layers  216   a - c  protect AlGaN layer  212 . Dual gate transistors (e.g., as described above) are known in the art in relation to applications other than TBU circuits. For example, in U.S. Pat. No. 5,821,813 and in U.S. Pat. No. 6,801,088, one gate is used a signal input and the other gate is employed as a bias input. Use of one gate for signal and the other gate for bias is similar to the arrangement of a pentode tube, in which the gates are located at the same end of the device, and cathode and anode (corresponding to source and drain) are not reversible. 
         [0026]    It is important in TBUs according to embodiments of the invention to connect the gates of the dual-gate transistor correctly to the remainder of the TBU circuit.  FIG. 4   a  shows the correct connections. Here the terminals of the dual-gate transistor are shown as  402  and  404 , while the two gates are shown as  406  and  408 . Assuming the outer transistors of the TBU are low voltage devices, it follows that source/drain  402  and gate  406  have roughly similar voltages, as do source/drain  404  and gate  408 . When the TBU is blocking high voltages, there is a high voltage between terminals  402  and  404 . Thus there can be high voltage between gate  406  and terminal  404 , and between gate  408  and terminal  402  (i.e., between a gate and its “far” terminal), but high voltage can never appear between gate  406  and terminal  402 , or between gate  408  and terminal  404  (i.e., between a gate and its “near” terminal). This behavior is just right for exploiting the device geometry of  FIG. 3   b  to reduce device size while providing high and symmetric breakdown voltages. 
         [0027]    In contrast,  FIG. 4   b  shows incorrect connections. Following the above line of reasoning, it is clear that with incorrect connections as on  FIG. 4   b , the high voltages appear between a gate and its corresponding “near” terminal. In this situation, no benefit is obtained from use of the dual-gate transistor. 
         [0028]    Therefore, the order of the gates as shown on the schematic of  FIG. 3   a  is significant in the following sense: gate G 3  is the gate of transistor Q 6  that is closer to T 5  than to T 6  (as measured along the channel of Q 6 ), and gate G 4  is the gate of transistor Q 6  that is closer to T 6  than to T 5 , as suggested by the way the schematic is drawn. The schematic of  FIG. 5  also follows this same convention. 
         [0029]      FIG. 5  shows a TBU according to a preferred embodiment of the invention. In this example, Q 7  and Q 8  are low voltage p-channel depletion mode transistors, and Q 9  is a high voltage, dual-gate depletion mode n-channel transistor, preferably a GaN HEMT or MESFET as described above. Having the HV device being n-channel is preferred because n-channel devices tend to provide better performance than p-channel devices. In this example, for positive I TBU  (i.e., in direction of I TBU  arrow), transistors Q 8  and Q 9  cooperate to provide transient blocking. For negative I TBU , transistors Q 7  and Q 9  cooperate to provide transient blocking. 
         [0030]    More specifically, for negative I TBU  exceeding a predetermined first threshold, a voltage between terminals T 1  and T 2  provides a voltage at G 3  tending to switch off Q 9 , which then acts to switch off Q 7 , thereby shutting off the TBU. Similarly, for positive I TBU  exceeding a predetermined second threshold, a voltage between terminals T 3  and T 4  provides a voltage at G 4  tending to switch off Q 9 , which then acts to switch off Q 8 , thereby shutting off the TBU. 
         [0031]    Diodes D 1  and D 4  act to block current flow to or from the gates of Q 7  and Q 8 . In some cases, the voltage handling capability of the gates of Q 7  and Q 8  may be insufficient to handle the high voltage developed across Q 9 . In such cases, resistance can be included in series with diodes D 1  and D 4  (or as a replacement to the diodes) to ensure the bypass current generated by this high voltage is limited to a level that the gates of Q 7  and Q 8  can handle. Also, in some cases, the junction voltages of Q 7  and Q 8  can be such that it is not necessary to provide diodes D 1  and D 4  to prevent current flow to or from the gates of Q 7  and Q 8 . 
         [0032]    In some cases, transistors Q 7  and Q 8  may exhibit current collapse, which is a transient decrease in channel conductivity responsive to a high applied voltage. For example, GaN transistors are prone to exhibit current collapse. In such cases, it is preferable to add optional diodes D 2  and D 3  as shown, which serve to protect Q 7  and Q 8  from damage cause by high reverse voltages. More specifically, Q 7  is relevant for blocking negative transients, so its corresponding diode D 2  permits the flow of positive current (i.e., build-up of high reverse voltage is prevented). Similarly, Q 8  is relevant for blocking positive transients, so its corresponding diode D 3  permits the flow of negative current. Here also, build-up of high reverse voltage is prevented by the diode shunt. 
         [0033]    In some cases, resistors may be placed in series with one or more of diodes D 1 -D 4  in order to adjust the biasing of the transistors. Such bias adjustment is within the skill of an ordinary art worker.