Abstract:
This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and dynamically changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed card speed grade. The SOC initially selects 3.3 volts to supply to the memory card. The SOC communicates with memory card vis input/output circuits to determine a memory type. The controller selects a 3.3 volt or 1.8 volt supply for the memory card based upon the determination. The SOC powers the input/output circuits at the same supply voltage as the memory card. This invention employes 1.8 volt transistors in the input/output circuits using a bias voltage to protect these transistor from the full 3.3 volt power when the memory card is powered to 3.3 volts.

Description:
CLAIM OF PRIORITY 
       [0001]    This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 62/325,767 filed Apr. 21, 2016. 
     
    
     TECHNICAL FIELD OF THE INVENTION 
       [0002]    The technical field of this invention is power supplied by a System On Chip (SOC) circuit to a SD memory card capable of operating at differing voltages. 
       BACKGROUND OF THE INVENTION 
       [0003]    This invention is preferably a power supply from a System on Chip (SOC) to a secure digital (SD) memory card embodied in a standard UHS-1 card interface. These SD memory cards come in several standard voltage/frequency ratings. It is advantageous for the SOC to be able to operate with any connected SD memory card and be capable of changing the supplied power supply voltage based upon the memory card requirements. 
         [0004]    The UHS-1 memory card interface permits these operating modes: 
         [0000]    
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Mode 
                 Name 
                 Voltage 
                 Speed (MHz) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 DS 
                 Default Speed 
                 3.3 
                 25 
               
               
                   
                 HS 
                 High Speed 
                 3.3 
                 50 
               
               
                   
                 SDR12 
                 Single Data Rate 
                 1.8 
                 25 
               
               
                   
                 SDR25 
                 Single Data Rate 
                 1.8 
                 50 
               
               
                   
                 SDR50 
                 Single Data Rate 
                 1.8 
                 100 
               
               
                   
                 SDR105 
                 Single Data Rate 
                 1.8 
                 208 
               
               
                   
                 DDR50 
                 Dual Data Rate 
                 1.8 
                 50 
               
               
                   
                   
               
             
          
         
       
     
         [0005]      FIG. 1  illustrates a simplified view of the UHS-1 standard manner of the SOC selecting the voltage and data rate for the SD memory card. Program  100  begins with detection of SD memory card insertion in decision block  101 . This detection generally triggers an interrupt to service the card interface. If a card insertion is not detected (No at decision block  101 ), then the system returns to decision block  101  and continues to wait for detection of SD memory card insertion. If card insertion is detected, (Yes at decision block  101 ), then the system supplies 3.3 volt power to the SD memory card at block  102 . 
         [0006]    The SOC and the SD memory card then communicate to set the voltage and speed of the interface (block  103 ). The result is determined by the SOC is a communications mode including supply voltage and frequency. This typically occurs by the SOC transmitting a series of commands to the SD memory card and making a communications mode decision bases upon the SD memory card responses. The interface frequency is not relevant to this invention and is not illustrated. 
         [0007]    Relevant to this invention is the determined supply voltage for the SD memory card. Decision block  104  determines if the selected voltage for the SD memory card is 3.3 volts or 1.8 volts. If the determined power supply voltage is 3.3 volts, then program continues with other processing at continue block  105 . If the determined power supply is 1.8 volts, then block  106  changes the electric power supplied to the SD memory card to 1.8 volts. Then program continues with other processing at continue block  105 . 
         [0008]    The prior art employed a separate power supply module between the SOC and the SD memory card. This separate power supply module required a separate power rail and an interface to the SOC to control the supplied voltage. This involves a separate control bus (typically an I 2 C bus) and programming in the SOC to control the power supply module vis this separate bus. This introduces additional overhead in code and time delay in the power supply control operation. This also presents problems in the input/output (I/O) of the SOC to the SD memory card. If the SOC uses a low geometry process which does not support 3.3V transistors, this prior art requires an additional supply rail to create an intermediate bias of the SOC I/O circuits. 
       SUMMARY OF THE INVENTION 
       [0009]    This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed SD memory card speed grade. This invention works with a Dual-Voltage I/O (input/output) with a 1.8 volts bias. 
         [0010]    This invention eliminates the need for an additional power supply rail and a custom power supply module requiring additional system bill of materials and an additional interface. This invention supports a 1.8 volt/3.3 volt dual-voltage I/O utilizing only 1.8 volt transistors via a bias voltage. This invention provides tighter integration between the SD memory card and the host controller. This inventions enables flexible power up/down sequence when switching SD memory card voltages. This invention employes 1.8 volt transistors in the I/O circuits using a bias voltage when the SD memory card is powered to 3.3 volts thereby reducing SOC cost by not requiring thick oxide for these transistors. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0012]      FIG. 1  illustrates a standard manner of the SOC selecting the voltage and data rate for the memory card; 
           [0013]      FIG. 2  illustrates how the SOC connects to the memory card; 
           [0014]      FIG. 3  illustrates details of the memory card power supply regulator; 
           [0015]      FIG. 4  illustrates another view of the memory card power supply regulator illustrating further details; and 
           [0016]      FIG. 5  shows the input voltage supply and the LDO power supply voltage output versus time. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0017]    In this invention the power supply for the SD memory card is embodied on the same integrated circuit as the SOC. The power supply includes a low drop out (LDO) voltage regulator to generate a 1.8 volt supply signal from a 3.3 volt supply applied to the SOC. This LDO voltage regulator supplies power to the SD memory card when the determined parameters indicate the SD memory card should be powered with a 1.8 volt supply. The LDO voltage regulator also supplies power to the SOC I/O (input/output) circuits. When the I/O circuits must interface with 3.3 volt circuits, the LDO voltage regulator supplies a bias voltage to prevent I/O circuit transistors from experiencing the entire 3.3 volt power supply when the SD memory card is powered at 3.3 volts. 
         [0018]      FIG. 2  illustrates how the SOC connects to the SD memory card. System  200  includes the SOC integrated circuit  210  and the SD memory card  220 . SOC integrated circuit  210  includes: memory card power supply regulator  211 ; SOC I/O circuits  212 ; central processing unit  213 ; other power domains  214 ; other logic circuits  215 ; and main bus  216 . SD memory card  220  includes: memory circuits  221 ; and memory card I/O circuits  222 . 
         [0019]    SOC IC  210  receives an external power supply voltage VIN. VIN powers memory card power supply regulator  211  in a manner that is the subject of this invention. VIN powers other power domains  214  in a conventional. Other power domains  214  supplies power to various parts of SOC IC  210  in a conventional manner known in the art. This portion of SOC IC  210  is not relevant to the current invention and will not be further described. 
         [0020]    Memory card power regulator  211  generates a power supply VCCIO supplied to both SD memory card  220  and SOC I/O circuits  212 . Internal power supply connection within SD memory card  220  is only outlined in  FIG. 2  and is conventional. Internal power supply within SOC I/O circuits  212  is different but also conventional. This will be further explained below. 
         [0021]    As previously described SOC IC  210  is constructed to operate with a variety of SD memory card  220 s having differing voltage and speed requirements. Upon initial connection of a SD memory card  220  to SOC IC  210 , central processing unit  213  participates in a negotiation as illustrated in  FIG. 1  via SOC I/O circuits  212  to determine the power and frequency needs of the recently connected SD memory card  220 . Initially SOC IC  210  supplies 3.3 volts power to SD memory card  220 . Central processing unit  213  supplies control signals to memory card power supply regulator  211  to produce a 3.3 volt supply to SD memory card  220 . Based upon the determination of memory type, SOC IC  210  may continue to supply 3.3 volt power or may switch to 1.8 volt power. Central processing unit  213  controls any power voltage switch via the controls supplied to memory card power supply regulator  211 . SOC I/O circuits  213  are powered by the same power voltage as supplied to SD memory card  210 . SOC I/O circuits  213  also receives a power supply VDDEQ from memory card power supply regulator  211  used in a manner further described below. 
         [0022]      FIG. 3  illustrates further details of memory card power supply regulator  211 .  FIG. 3  illustrates plural circuit domains. The first domain  301  is the part of SOC IC  210  that includes memory card power supply regulator  211 . The second domain  302  includes the semiconductor part of SOC IC  210  including such parts as SOC I/O circuits  212 , central processing unit  213  and other logic circuits  215 . This domain is also known as the die area. The third domain  303  further includes the bond pads which enable connection between the die area (third domain  303 ) and external circuits. The fourth domain  304  is the package including SOC IC  210 . The fifth domain  305  is a printed circuit board including other parts of the electronic system. These other parts include SD memory card  220  if connected. 
         [0023]      FIG. 3  further illustrates relevant IC pins connected to bonding pads. These include: pin  311 , receiving an external 3.3 volt power supply; pin  312 , supplying a selected voltage signal (3.3 volts or 1.8 volts) to both SD memory card  220  (external) and SOC I/O circuits  211  (internal); pin  313 , the output from LDO power supply  321 ; pin  314 , a first feedback signal from the LDO power supply  321  output, generally pins  313  and  314  are tied together; pin  315 , an analog ground input; pin  316 , a second feedback signal from the LDO power supply  321  output; and pin  317 , the voltage reference for LDO power supply  321 , generally the same as VIN, the power supply voltage.  FIG. 3  illustrates several signals internal to SOC IC  210  including: core domain power VDD  318 ; control signals  319  en18mode and hhv18; and test signals  320 . 
         [0024]    Table 2 shows a listing of the integrated circuit pins for SOC IC  210  of this invention. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 Pin 
                 Num- 
                   
                   
                   
               
               
                 Name 
                 ber 
                 Domain 
                 Description 
                 In/Out 
               
               
                   
               
             
             
               
                 VIN 
                 311 
                 3.3 
                 3.3 volt external power 
                 Input 
               
               
                   
                   
                   
                 supply 
               
               
                 VDDIO 
                 312 
                 VIN/VDDQ 
                 3.3 volt/1.8 volt supply 
                 Output 
               
               
                   
                   
                   
                 for IOs 
               
               
                 VDDQ 
                 313 
                 1.8 
                 1.8 LDO output, I/O bias 
                 Output 
               
               
                   
                   
                   
                 supply 
               
               
                 VDDQIN 
                 314 
                 1.8 
                 LDO feedback signal from 
                 Input 
               
               
                   
                   
                   
                 VDDQ chip pin 
               
               
                 VSSA 
                 315 
                 0.0 
                 Analog ground 
                 Input 
               
               
                 VDDQ_FB 
                 316 
                 1.8 
                 Shorted to VDDQ pad 
                 Input 
               
               
                   
                   
                   
                 inside IC 
               
               
                 VIN_REF 
                 317 
                 3.3 
                 Shorted to VIN inside IC 
                 Input 
               
               
                 VDD 
                 318 
                 1.0 
                 Core domain power supply 
                 Input 
               
               
                 en18mode 
                 319 
                 core (1.0) 
                 Control to switch VDDIO 
                 Input 
               
               
                   
                   
                   
                 between 3.3 and 1.8 
               
               
                 hhv18 
                 319 
                 1.8 
                 HHV signal 
                 Input 
               
               
                   
               
             
          
         
       
     
         [0025]    These signals are as follows. The VIN pin  311  receives a fixed 3.3 volt external power supply. The VDDQ pin  313  supplies a fixed 1.8 volt LDO (low drop out) output from LDO power supply  321 . The VDDIO pin  312  can input either VIN or 1.8 volts. During start up, VDDIO  312  will be at VIN as long as hhv18 is high (1.8 volts). When hhv18 goes low, VDDIO  312  can be at VIN or 1.8 volts depending on control logic at the en18mode pin. Both VDDIO  312  and VDDQ  313  output supplies are available as long as VIN is available. Switching the VDDIO pin  312  from 1.8 volts to 3.3 volts or vice versa should complete in 5 ms. A dummy load can be turned on during this switching time for quicker settling of the VDDIO  312  and VDDQ  313  voltages. Reliability is especially importance during VDDIO switching. This will be further explained below. 
         [0026]    Memory card power supply regulator  211  includes low drop out (LDO) power supply  321 . LDO power supply  321  is powered via the 3.3 volt supply received via pin VIN  311  and supplies a 1.8 volt output as controlled by the VIN REF  317  signal. The pin VIN  311  and the pin VIN REF  317  typically have the same voltage and are tied together. Memory card power supply regulator  211  includes two switches: switch S 1   322 ; and switch S 2   323 . These are switched in the opposite sense. When S 1   322  is closed, S 2   323  is open; when S 1   322  is open, S 2   323  is closed. This is controlled by central processing unit  213  via control lines  319  signals en18mode and hhv18. Initially the en18mode and the hhv18 signals select S 1   322  closed and S 2   323  open. This supplies 3.3 volts from VIN  311  to VDDIQ  312  to power the SD memory card. As illustrated in  FIG. 2 , VDDIQ  312  also powers SOC I/O circuits  212 . 
         [0027]    As previously described, central processing unit  213  communicates with SD memory card  220  via SOC I/O circuits  212  to determine a voltage and frequency of their interface. Depending upon the nature of SD memory card  220 , central processing unit  213  may continue to supply a 3.3 volt power input to SD memory card  220 . In this case central processing unit  213  continues to supply control signals to close switch S 1   322  and open switch S 2   323 . Switch S 1   322  connects the input supply VIN  311  (3.3 volts) to the power output to SD memory card  220  at VDDIQ  312 . Switch S 2   323  is open isolating the 1.8 volt output of LDO power supply  321  (VDDQ) from the power output to SD memory card  220  at VDDIQ  313 . 
         [0028]    In other cases, central processing unit  213  supplies a 1.8 volt power input to SD memory card  220 . In this case central processing unit  213  supplies control signals to open switch S 1   322  and close switch S 2   323 . With switch S 1   322  open, the output to SD memory card  220  at VDDIQ  312  is isolated from VIN  311 . With switch S 2   323  closed, the output of LDO power supply  321  (VDDQ  312 ) is connected to the power output to SD memory card  220  at VDDIQ  313 . 
         [0029]    This is better illustrated in  FIG. 4 , showing an exemplary embodiment of switches S 1   322  and S 2   323 . Switch S 1   322  is embodied by MOS transistor  401 . Transistor  401  has a source-drain path connected between VIN  311  and VDDIO  312 . Transistor  401  has a gate receiving a 1.8 volt enable signal (1.8_EN) from central processing unit  213 . Switch S 2   323  is embodied by transistor  402  and inverter  403 . MOS transistor  402  has a source-drain path connected between VDDIO  312  and VDDQ  313 . Transistor  401  has a gate receiving a 1.8 volt enable signal (1.8_EN) from central processing unit  213  as inverted by inverter  403 . In a first state of 1.8_EN, transistor  401  is conducting and transistor  402  is cut off. Thus the 3.3 volts from VIN  311  supplies VDDIO  312 . In a second state of 1.8_EN, transistor  401  is cut off and transistor  402  is conducting. Thus the 1.8 volts from LDO power supply  321  (VDDQ  313 ) supplies VDDIO  312 . 
         [0030]    In the preferred embodiment SOC I/O circuits  212  are constructed of transistors designed to operate at 1.8 volts. Ordinarily then, these 1.8 volt transistors would be overstressed and subject to reduced operating life when VDDIO is 3.3 volts. This invention supplies VDDQ  313  from LDO power supply  321  to SOC I/O circuits  212  as a bias voltage. Thus the transistors in SOC I/O circuits  212  never experience the whole 3.3 volt supply and are never overstressed. VDDIO  311  should never exceed VDDQ  313  by more than 2 volts under all conditions including power-up/down sequences. VDDQ  313  and VDDIO  312  should track each other when VDDIO  312  is configured as 1.8 volts. During initial powering of the SD memory card  220  at 3.3 volts, the SOC should delay closing switch S 1   302  until LDO power supply  321  brings up the bias at VDDQ. This prevents more than 2 volts applied across the transistor of SOC I/O circuits  212 . 
         [0031]    During failure of the 3.3 volt power supply to the system, powering LDO power supply  212  from the 3.3 volt source effectively prevents this overstress. This is illustrated in  FIG. 5 .  FIG. 5  shows the input voltage supply  501  and the LDO power supply  312  voltage output  502 . Before time t 1 , both supplies  501  and  502  are in steady state. The difference between these voltages is ΔV 1 , nominally 1.5 volts, which is below the overstress point of the 1.8 volt transistors employed in SOC I/O circuits  212 . At time t 1 , the 3.3 volt supply power is removed. Input voltage supply  501  falls toward 0.0 volts, which it reaches at time t 4 . At time t 1 , the output voltage  502  of LDO power supply  211  does not fall immediately due to the regulation character of this power supply. Only after the input voltage supply  501  falls to a voltage V brk  at time t 2  does output voltage  502  begin to fall. At time t 2  the difference between the input voltage supply  501  and the output voltage  502  is ΔV 2 . As illustrated in  FIG. 5 , ΔV 2  is less than ΔV 1 , which is below the overstress point of the 1.8 volt transistors employed in SOC I/O circuits  212 . These voltages  501  and  52  will tend to drop in parallel until time t 3 . These voltage will also tend to maintain a voltage difference of ΔV 2 . At time t 3  voltage  502  is 0.0 volts. However, voltage  501  will be near ΔV 2 , a voltage below the overstress point of the 1.8 volt transistors employed in SOC I/O circuits  212 . Thus this invention insures that the 1.8 volt transistors employed in SOC I/O circuits  212  are not overstressed during failure of the 3.3 volt supply. This is achieved by employing the same supply source (VIN  311 ) for VDDIO  312  and VDDQ  313 . 
         [0032]    This invention is advantageous over providing an external power supply regulator for the SD memory card. This invention eliminates the need for custom power solution. No software is required in the SOC to support an external power regulator. This eliminates a potential source of design error and delay.