Abstract:
A memory array includes a true bitline and a complementary bitline and a sense amplifier connected thereto; a row of normal cells with capacitors for data storage and bitline storage capacitors. A row of dummy cells with dummy cell capacitors is also provided. A clock provides wordline drive signals to the normal cells. When operating in the test mode, the clock provides at least one dummy wordline drive signal to the dummy cell switch in response to a testing signal for connecting the dummy cell capacitor to the bitline. A plurality of rows of dummy cells can be employed with various permutations of actuation thereof to provide various levels of capacitance connected to the bitlines in the test mode.

Description:
BACKGROUND 
   In the process of manufacturing semiconductor memory devices it is desirable to improve product reliability by performing screening examinations of memory devices such as semiconductor chips. One goal of such an examination is to determine which memory devices, e.g. chips, are defective. Another goal of such an examination is to determine which memory devices (chips) include weak cells. A most commonly used technique for attempting to achieve this objective is to measure the rate of data retention while varying the data retention time. However, there is the disadvantage that measuring data retention times during screening examinations of memory chips is a very expensive process. 
   Another concern is that there is no way to determine the relevant characteristics of each memory cell within an array. For example there is a concern about cell capacitors, bitline capacitors and the relationship between a particular cell capacitor and a particular bitline capacitor during the development phase. Even if one can make that determination, the result must be achieved with a special test vehicle; not by a measurement from an actual memory array. 
   U.S. Pat. No. 4,468,759 of Kung, et al. entitled “Testing method and apparatus for DRAM” states in the abstract “A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory and a potential lower than the reference potential is applied to the dummy cells when reading binary zeroes from the memory. This testing procedure detects weak cells and amplifiers and helps present the packaging of defective parts. In addition, a simplified means for programming redundant elements is described which requires substantially less substrate area than previous methods.” 
   U.S. Pat. No. 5,544,108 of Thomann entitled “Circuit And Method For Decreasing the Cell Margin During a Test Mode” indicated that during a read mode when a first cell has been selected the first access transistor of the selected first cell actuates and couples the charge stored on the first storage capacitor of the first cell to its respective digit line. The charge stored in the first storage capacitor has a potential different than the potential of the digit line. This difference between the potential of the first storage capacitor and the potential of the digit line is the cell margin. The patent states further that “The N-sense amplifier senses the cell margin and determines what data has been stored in the cell. Next the N-sense amplifier amplifies the potential of the digit line to reflect the value of the potential stored in the cell. Once amplified the digit line in electrical communication with the selected cell has a potential representing the data bit stored in the storage capacitor, and the remaining digit line of the digit line pair has a potential equal to the complement of the data bit stored in the storage capacitor of the selected cell.” 
   In accordance with this invention, a dummy memory cell within a memory array is used to simulate or measure the cell data margin. Additional capacitors added to the bit line capacitor from the dummy memory cell will vary the capacitor ratio between a bitline capacitor and a cell storage capacitor. This leads to a change in the signal value developed at the bitline from the normal memory cell when the nominal cell wordline is selected. In this way, one can easily detect which cells are the weak cells at an early phase of product development before commencement of refresh testing or prior to shipping of commercial products. 
   GLOSSARY 
   Cell margin . . . “The difference between the potential of a storage capacitor and the potential of the digit line” of U.S. Pat. No. 5,544,108 of Thomann (cited above); “The sense amplifiers then sense the differential, or cell margin, across the digit line pair.” U.S. Pat. No. 6,104,650 of Shore; and “For a single-bit memory cell, margin is defined as the additional voltage threshold needed to insure that the programmed cell will retain its stored value over time. U.S. Patent Application 20040242009 of Banks entitled “Electrically Alterable Non-Volatile Memory With N-Bits Per Cell.” 
   Cell data margin . . . Cell Margin and Cell data margin have the same meanings 
   Data margin . . . Short for cell data margin 
   Digit line . . . Bitline or bit line 
   Dummy cell . . . A cell within a memory cell array not used for regular storage. In some cases a dummy cell is added between regular memory cell array and peripheral circuits such as a Sense Amp to eliminate a topology gap. 
   Normal cell . . . A regular cell used for normal (regular) storage operations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic circuit diagram of a memory system in accordance with this invention including a bit line pair connection of a memory cell that includes two normal cells in a row of normal cells and two dummy cells in a row of dummy cells for screening defective cells by measuring the cell data margin. 
       FIGS. 2A and 2B  show two timing diagrams of the activated and un-activated mode of operation of the system of  FIG. 1 . 
       FIG. 3  is a schematic circuit diagram of a memory system in accordance with this invention for measuring the cell data margin in accordance with this invention in which a row of normal cells and multiple rows of dummy cells are used within an array. 
       FIGS. 4A ,  4 B,  4 C and  4 D show four timing diagrams of the activated and un-activated mode of operation of the system of  FIG. 3 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1  is a schematic circuit diagram of a memory system  10  in accordance with this invention including a one bit line pair connection of a memory cell that includes two normal cells NC 1  and NC 2  in a row of normal cells and two dummy cells DC 3  and DC 4  in a row of dummy cells for screening defective cells by measuring the cell data margin. The row of dummy cells represented by cell DC 3  and cell DC 4  and the row of normal cells represented by cell NC 1  and NC 2  are included within the same array. The bitline pair includes a true bitline BT connected to nodes  1 T to  5 T and a complementary bitline BC connected to nodes  1 C to  5 C. The true bitline BT is connected through the node  1 T to address dummy cell DC 3  and through the node  2 T to address true normal cell NC 1  and other elements of the circuit  10 . The complementary bitline BC is connected through node  1 C to address dummy cell DC 4  and through node  2 C to address complementary normal cell NC 2  and other elements of the circuit  10 .  FIGS. 2A and 2B  show two timing diagrams of the activated and un-activated mode of operation of the system  10  of  FIG. 1  from time t 1  to t 6 . 
   A clock  12  includes a TEST input  21 , output lines including dummy word line  13 , wordline WLi  14 , wordline WLj  15 , and lines to a cross coupled sense amplifier including SETN line  25  and SETP line  26 . 
   Each of the two normal cells NC 1  and NC 2  and each of the two dummy cells DC 3  and DC 4  includes a single storage capacitor Cs and an NFET transistor with the source drain circuit in series with one terminal of the capacitor Cs and the other terminal of the capacitor Cs connected to ground GND. 
   The normal cell NC 1  includes the NFET T 1  and the storage capacitor Cs 1 . Transistor T 1  has one end of its source/drain circuit connected to a terminal of a storage capacitor Cs 1 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuits of memory cell transistor T 1  is connected through node  2 T to the true bitline BT. 
   The normal cell NC 2  includes the NFET T 2  and the storage capacitor Cs 2 . Transistor T 2  has one end of its source/drain circuit connected to a terminal of a storage capacitor Cs 2 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuits of memory cell transistor T 2  is connected via node  2 C to the complementary bitline BC. 
   The dummy cell DC 3  includes NFET T 3  and storage capacitor Cs 3 . Transistor T 2  has one end of its source/drain circuit connected to a terminal of a storage capacitor Cs 3 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuit of the dummy cell transistor T 3  is connected through node  1 T to the true bitline BT. 
   The dummy cell DC 4  includes NFET T 4  and storage capacitor Cs 4 . Transistor T 4  has one end of its source/drain circuit connected to a terminal of a storage capacitor Cs 4 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuits of the dummy cell transistor T 4  is connected through node  1 C to the complementary bitline BC. 
   In summary, each of the transistors T 1 , T 2 , T 3 , and T 4  has one end of its source/drain circuit connected respectively to a terminal of a storage capacitor Cs 1 , Cs 2 , Cs 3 , and Cs 4 . Each of those capacitors is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuits of transistors T 1 /T 3  are connected through nodes  2 T/ 1 T to the true bitline BT. The other ends of the source/drain circuits of transistors T 2 /T 4  are connected through nodes  2 C/ 1 C to the complementary bitline BC. 
   The source/drain circuit of the transistor T 1  connects between the true bitline BT and one terminal of the capacitor Cs 1 . The source/drain circuit of the transistor T 2  connects between the complementary bitline BC and one terminal of the capacitor Cs 2 . The source/drain circuit of the transistor T 3  is connected between the true bitline BT and one terminal of the capacitor Cs 3 . The source/drain circuit of the transistor T 4  connects between the complementary bitline BC and one terminal of the capacitor Cs 4 . 
   The clock  12  includes an output line comprising dummy word line  13 , which is adapted to supply a test signal DWL on line  13  to the gates of the pair of dummy transistors T 3  and T 4  for activating testing by turning on the two dummy transistors T 3  and T 4 . 
   Normal wordlines  21  and  22  supply wordline signals WLi and WLj respectively to the gates of the transistors T 1  and T 2  of the normal cells NC 1  and NC 2  respectively. 
   The storage capacitors Cs 1 , Cs 2 , Cs 3 , and Cs 4  are assumed to have substantially equal capacitance values of Cs. 
   The true bitline BT and complementary bitline BC are also connected to the negative and positive terminals respectively of a sense amplifier SA. The dummy wordline  13  supplies a test signal DWL to the gates of NFETS T 1  and T 2 . 
   There is a precharge circuit VREFX-short-circuiting equalization circuit ESR which short circuits the true bitline BT and the complementary bitline BC together and at the same time connects them to precharge potential VREFX during times t 1  to t 2 , t 3  to t 4  and t 5  to t 6  in  FIGS. 2A and 2B . The precharge circuit ESR includes short circuiting NFET N 3  and reference potential NFETs N 2  and N 4 . All three equalization NFETs N 2 , N 3 , and N 4  of the VREFX-short-circuiting equalization circuit ESR have their gates connected via connections to line  27  to be turned ON when they receive the reference potential equalization pulse PRE on the reference potential equalization line  27 . The drain of the centrally located equalization NFET N 3  is connected via node  5 T to the true bitline BT and its source connected to the complementary bitline BC via node  5 C so that when the NFET N 3  conducts, it short circuits the true bitline BT to the complementary bitline BC. Equalization NFET N 2  has its drain connected to the true bitline BT via node  5 T, and its source connected to the reference potential source VREFX via node  58  and line  11 . The equalization NFET N 4  has its source connected to the complementary bitline BC via node  5 C and its drain connected to the voltage source VREFX via node  58  and line  11 . When NFETs N 2  and N 4  are ON they connect the true bitline BT and the complementary bitline BC to the reference potential source VREFX via node  58  and line  11 . At the same time, the NFET N 3  short circuits the lines BT and BC together via nodes  5 T and  5 C. The result is that the potential on the true bitline BT and the complementary bitline BC is equalized rapidly. 
   In operation, the precharge line  27  is connected to receive the short circuiting (reference potential) equalization pulse PRE which is shown in the signal timing diagrams of  FIGS. 2A and 2B  from clock  12 . During an equalization phase of operation of the system  10  from times t 1  to t 2 , t 3  to t 4  and t 5  to t 6  in each cycle the reference potential equalization pulse PRE from clock  12  is applied on the reference potential equalization line ERL to circuit ESR to raise the gate of NFET N 3  turning it ON to provide a short circuit connection between the true bitline BT and the complementary bitline BC. At the same time equalization pulse PRE is applied to the gates of NFETS N 2 /N 4  which turns them on so that they connect both the true bitline BT and the complementary bitline BC to charge or discharge them to the potential of the reference voltage source VREFX. 
   When the WLi signal on line  14  is high, it activates the gate of the NFET T 1  to turn normal cell NC 1  ON so that is conducts, thereby connecting the node of capacitor Cs 1  through node  2 T to true bitline BT. The WLi signal is high from time t 2  to t 3  as shown in  FIGS. 2A and 2B . 
   When the WLj signal on line  15  is high, it activates the gate of the NFET T 2  to turn normal cell NC 2  ON so that is conducts, thereby connecting the node of capacitor Cs 2  through node  2 C to complementary bitline BC. The WLj signal is high from time t 4  to t 5  as shown in  FIGS. 2A and 2B . 
   To differentiate between the normal access mode and the test mode, test signal DWL and signals WLi and WLj are controlled by using a test mode pin, as will be well understood by those skilled in the art. The test mode pin is an additional external PIN that is provided to permit changing modes of operation between the normal access mode and the test mode. The test signal is normally OFF, but is activated when test block  21  signals clock  12  to turn on signal DWL on line  13 . 
     FIGS. 2A and 2B  show two timing diagrams of the activated and un-activated mode of operation of the system  10  of  FIG. 1  from time t 1  to t 6 . 
   Referring to  FIG. 2A , the test signal DWL on the dummy wordline  13  is deactivated, i.e. OFF, when the mission mode (normal access mode) is enabled and the storage capacitors Cs 3  and Cs 4  of the dummy cells DC 3  and DC 4  are completely isolated from the true bitline BT and the complementary bitline BC. 
   Referring to  FIG. 2B , the signal DWL on dummy wordline  13  is activated (i.e. turned ON) only when test mode is enabled and the storage capacitors Cs 3  and Cs 4  of the dummy cells  17  and  18  are both charged to the same level as bitline precharge level, because the test signal DWL raises the gates of the dummy cells transistors DT 1  and DT 2 . 
   During operation in the normal access mode of operation, at time t 2  the signal WLi on the wordline  14  turns ON raising the gate of transistor T 1 , which connects the node  2 T to the node of capacitor Cs 1 , which as stated above has its other terminal connected to GND. Thus charge flows between the bitline BT and the capacitor Cs 1  to contribute charge to capacitor Cs 1  until time t 2  when the signal WLi is OFF on wordline  14 . At time t 4  the signal WLj on wordline  15  turns ON raising the gate of transistor T 2 , which connects the node  2 C to the node of capacitor Cs 2 , which as stated above has its other terminal connected to GND. Thus charge flows between the bitline BC and capacitor Cs 2  to contribute charge to capacitor Cs 2  until time t 5  when signal WLj is OFF on wordline  15 . 
   During operation in the normal access mode of operation continuously from times t 1  to t 6 , the dummy cells DC 1  and DC 2  are unable to contribute charge to the true bitline capacitor C BL1  or to complementary bitline capacitor C BL2 . When wordline WLi is activated, the signal developed at true bitline BT is determined by the capacitor ratio of the capacitance value C BL  of the true bitline capacitor C BL1  to the capacitance value Cs of the storage capacitor Csi, as follows:
 
 Vsignal=Cs*VDD /( Cs+C   BL )  (Equation 1)
 
where:
     Cs is the capacitance of each normal cell and each dummy cell   C BL  is the capacitance of a bitline   VDD is the voltage from power supply.   

   The source of VDD in  FIG. 1  which determines the voltage Vsignal on the bitline in equation 1 is the stored voltage at the cell node of a capacitor such as Cs 1  or Cs 2 . 
   The stored voltage is written to the cell node through SA operation and cell access transistor. 
   During the test mode of operation, the storage capacitors Cs 1  and Cs 2  of dummy cells NC 1  and NC 2  are activated continuously, as in that mode of operation the signal DWL is turned ON continuously from time t 1  to t 6  connecting the node of capacitor Cs 3  via node  1 T to true bitline BT and the node of capacitor Cs 4  via node  1 C to complementary bitline BC. Total bitline and complementary bitline capacitance connected to each of the true bitline BT and the complementary bitline BC is increased from a value of about C BL  for each of the capacitors C BL1 /C BL2  to a value of about C BL +Cs respectively. 
   Accordingly, when WLi is activated to measure a cell data margin of memory cell of T 1 , the signal developed at the true bitline BT is determined by the capacitor ratio of the capacitance of the bitline capacitor C BL1  to the capacitances Cs of the storage capacitor Cs 1  and the dummy capacitor Cs 3 . The sensing signal developed at true bitline BL is expressed by Equation 2.
 
 Vsignal=Cs*VDD (2*( Cs )+ C   BL )  (Equation 2)
 
   Likewise, when WLj is activated to measure a cell data margin of memory cell of T 2 , the signal developed at complementary bitline BC is determined by the capacitor ratio for complementary bitline BC capacitor C BL2  to the storage capacitor Cs 2  and the dummy capacitor Cs 4 . The signal change developed at the complementary bitline BC by the dummy cell is also shown by Equation 2. 
     FIG. 3  is a schematic circuit diagram of a memory system  30  in accordance with this invention for measuring the cell data margin in which a row of normal cells and multiple rows of dummy cells are used within an array. As in  FIG. 1  there is a bitline pair connection to memory cells, which includes a true bitline BT and a complementary bitline BC. The system includes two columns of normal and dummy cells including column “1” for the true bitline and column “2” for the complementary bitline. The first column (for the true bitline) includes several dummy cells DC 11 , . . . , DCN 1 , . . . DCN 1  and a normal cell NC 1 . The second column (for the complementary bitline) includes several dummy cells DC 12 , . . . , DCi 2 , . . . , DCN 2  and the normal cell NC 2 .  FIGS. 4A ,  4 B,  4 C and  4 D show four timing diagrams of the activated and un-activated mode of operation of the system  30  of  FIG. 3 . 
   The true bitline BT is connected through the node  2 T to address true normal cell NC 1  and other elements of the circuit  10 . The complementary bitline BC is connected through node  2 C to address complementary normal cell NC 2  and other elements of the circuit  10 . 
   A clock  34  includes a TEST input  39 , several clock output lines including several dummy word lines  13 - 1 , . . . ,  13 - i , . . . and  13 -N, wordline WLi  14 , wordline WLj  15 , and lines to a cross coupled sense amplifier SETN line  25  and SETP line  26 . 
   Each of the two normal cells NC 1  and NC 2  and each of the several dummy cells DC 11 , . . . , DCN 1 , . . . DCN 1  and a normal cell NC 1 ; and dummy cells DC 12 , . . . DCi 2 , . . . , DC 2  includes a single storage capacitor Cs and an NFET transistor with the source drain circuit in series with one terminal of a capacitor with a capacitance value of Cs and the other terminal of the capacitor Cs connected to ground GND. 
   The dummy cell DC 11  includes NFET T 11  and storage capacitor Cs 11 . Transistor T 11  has one end of its source/drain circuit connected to a terminal of a storage capacitor Cs 11 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuit of the dummy cell transistor T 11  is connected through node  6 T to the true bitline BT. 
   The dummy cell DC 12  includes NFET T 12  and storage capacitor Cs 12 . Transistor T 12  has one end of its source/drain circuit connected to a terminal of a storage capacitor Cs 12 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuits of the dummy cell transistor T 12  is connected through node  6 C to the complementary bitline BC. 
   The dummy cell DCi 1  includes NFET Ti 1  and storage capacitor Csi 1 . Transistor Ti 1  has one end of its source/drain circuit connected to a terminal of a storage capacitor Csi 1 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuit of the dummy cell transistor Ti 1  is connected through node  7 T to the true bitline BT. 
   The dummy cell DCi 2  includes NFET Ti 2  and storage capacitor Csi 2 . Transistor Ti 2  has one end of its source/drain circuit connected to a terminal of a storage capacitor Csi 2 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuits of the dummy cell transistor Ti 2  is connected through node  7 C to the complementary bitline BC. 
   The dummy cell DCN 1  includes NFET TN 1  and storage capacitor CsN 1 . Transistor TN 1  has one end of its source/drain circuit connected to a terminal of a storage capacitor CsN 1 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuit of the dummy cell transistor TN 1  is connected through node  8 T to the true bitline BT. 
   The dummy cell DCN 2  includes NFET TN 2  and storage capacitor CsN 2 . Transistor TN 2  has one end of its source/drain circuit connected to a terminal of a storage capacitor CsN 2 , which is connected at its other terminal to reference potential ground (GND). The other ends of the source/drain circuits of the dummy cell transistor TN 2  is connected through node  8 C to the complementary bitline BC. 
   In summary, each of the transistors T 11  T 12 , Ti 1 , Ti 2 , TN 1 , TN 2 , T 1 , and T 2 , has one end of its source/drain circuit connected respectively to a terminal of a storage capacitor Cs 11 , Cs 12 , Csi 1 , Csi 2 , CsN 1 , CsN 2 , Csi, and Csj. Each of those capacitors is connected at its other terminal to the reference potential ground (GND). The other ends of the source/drain circuits of transistors T 11 , Ti 1 , TN 1 , and Ti are connected through nodes  6 T to  9 T to the true bitline BT. The other ends of the source/drain circuits of transistors T 12 , Ti 2 , TN 2 , and T 2  are connected through nodes  6 C to  9 C to complementary bitline BC. 
   The normal cell NCi includes the NFET Ti and the storage capacitor Csi. Transistor T 1  has one end of its source/drain circuit connected to a terminal of a storage capacitor Cs 1 , which is connected at its other terminal to reference potential ground (GND). The other end of the source/drain circuit of memory cell transistor Ti is connected via node  9 T to the true bitline BT. 
   The normal cell NC 2  includes the NFET Tj and the storage capacitor Cs 2 . Transistor Tj has one end of its source/drain circuit connected to a terminal of a storage capacitor Csj, which is connected at its other terminal to reference potential ground (GND). The other end of the source/drain circuit of memory cell transistor Tj is connected via node  9 C to the complementary bitline BC. 
   The source/drain circuit of the transistor T 11  connects between the true bitline BT and one terminal of the capacitor Cs 11 . The source/drain circuit of the transistor T 12  connects between the complementary bitline BC and one terminal of the capacitor Cs 12 . The source/drain circuit of the transistor Ti 1  is connected between the true bitline BT and one terminal of the capacitor Csi 1 . The source/drain circuit of the transistor Ti 2  connects between the complementary bitline BC and one terminal of the capacitor Csi 2 . 
   The source/drain circuit of the transistor TN 1  connects between the true bitline BT and one terminal of the capacitor CsN 1 . The source/drain circuit of the transistor TN 2  connects between the complementary bitline BC and one terminal of the capacitor CsN 2 . The source/drain circuit of the transistor Ti is connected between the true bitline BT and one terminal of the capacitor Cs 1 . The source/drain circuit of the transistor Tj connects between the complementary bitline BC and one terminal of the capacitor Cs 2 . 
   The multiple dummy wordline signals DWL 1 , . . . , DWLi, . . . , and DWLN (where “i” is an integer between 1 to N) are connected by the horizontally extending, parallel lines  13 - 1 , . . . ,  13 - i , . . . , and  13 -N to the gate electrodes of NFET devices in two columns of dummy cells. The line  13 - 1  is connected to the gate electrodes of the transistors T 11  and T 12  in both of the dummy cells DC 11  and DC 12  respectively in row “1.” The line  13 - i  is connected to the gate electrodes of transistors TN 1  and Ti 2  in dummy cells DCN 1  and DCi 2  respectively in row “i.” The line  13 -N is connected to the gate electrodes of transistors TN 1  and TN 2  in the dummy cells DCN 1  and DCN 2  in row “N.” 
   During the test mode, each dummy wordline signal DWL (DWLi) is controlled independently to give different combinations of bitline capacitor capacitance values as shown in  FIGS. 4A–4D . For example, referring to  FIG. 4A , if we turn on DWL 1  from time t 2  to t 3 , the situation will be same as single DWL case as in  FIG. 1 . However, as shown in  FIG. 4B , if we turn on all of the dummy wordline signals DWL 1 , . . . , DWLi, . . . DWLN, then the true bitline BT and complementary bitline BC capacitor will be increased to (C BL +Cs*i) where “i” is the number of rows of dummy and normal cells. 
   This reduces the signal development at the true bitline BT or the complementary bitline BC.  FIG. 4C  illustrates a situation in which dummy wordlines DWL 1  and DWLN are ON but dummy wordline DWLi is OFF,  FIG. 4D  illustrates a situation in which dummy wordlines DWL 1  and DWLi are ON but dummy wordline DWLN is OFF so that any permutation of wordlines DWL 1 , . . . DWLi, . . . DWLN can be on or OFF to give varying different values of capacitance for a given bitline pair BT/BC. 
   By using multiple dummy cells, we can simulate to very tiny signal. The sensing signal development at the bitline BT or BC is expressed by Equation 3.
 
 Vsignal=Cs*VDD (( N+ 1)*( Cs )+ C   BL )  (Equation 3)
 
where:
     N is the Number of rows of dummy cells   Cs is the capacitance of each normal cell and each dummy cell   C BL  is the capacitance of a bitline   VDD is the voltage from power supply   

   By using this method, we can measure the cell data margin of each memory cell.