Abstract:
An AC electrical system has a source voltage and current interconnected through an energy storage device with a load. A unity power factor control circuit maintains unity power factor incorporating the steps of producing a sample and hold voltage related to the input voltage and an output voltage where the sample and hold voltage maintains constant values between pulses of a clock signal. A modulated signal at each clock pulse fall produces a current feedback voltage proportional to the source current, and as long as it is less then the sample and hold voltage, an inductor stores energy, and delivers it to the load each time the feedback voltage exceeds the sample and hold voltage and energy stored in the inductor is thereby delivered to the load, whereby controlling the amount of energy stored, the input voltage and current are drawn into phase thereby maintaining unity power factor.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Present Disclosure 
     This disclosure relates generally to the field of electric power distribution and, in particular, to power factor correction in single phase and multi-phase systems using a sample and hold technique. 
     2. Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98 
     Neufeld, U.S. Pat. No. 5,006,975, discloses a power factor correction circuit in which a divided-down version of a rectified input waveform is sampled approximately at its peak by a sample-and-hold circuit. The peak value is then processed to produce a correction signal which is subtracted from the original divided down rectified signal. This produces a reference signal which is then multiplied by the output of an error amplifier to produce a sinusoidal reference signal for the input current. The output of the error amplifier which is used is that which is sampled periodically when the divided-down rectified signal approaches zero volts. The sinusoidal reference is used by peak and valley comparators whose other inputs come from a current sense amplifier. The outputs of the comparators are used to switch a shunting transistor which controls the input current to achieve near unit y power factor. 
     Kammiller et al, U.S. Pat. No. 5,619,405, discloses a regulated power supply having power factor correction control which includes a state variable integrator/error amplifier that provides a low distortion error signal during steady state operation and fast transient response for tight output voltage control. 
     Curtiss et al, U.S. Pat. No. 4,356,440, discloses a discrete-time, closed loop power factor corrector system controlling the coupling of a delta-connected switched capacitor array to a 3- or 4-wire power line which may have time-varying, unbalanced, inductive loads. For inductive loads that cannot be exactly compensated with a delta-connected capacitance, the corrector system minimizes the total RMS reactive current drawn from the power line. 
     Ball et al, U.S. Pat. No. 6,756,771, discloses a power factor correction device which stores the output of an error amplifier on a storage element. A zero crossing detector detects the zero crossings of the AC input voltage and enables the power factor correction device to adjust the value of the voltage stored on the storage element. 
     Bridgeman, U.S. Pat. No. 6,147,475, discloses a method for predicting harmonic-distortion values for the application of a desired step change of capacitance to an AC system, an initial step change is applied and, from this change, and a value of harmonic impedance of the system for each of a number of harmonics is determined. From these harmonic-impedance values corresponding values of damping resistance are, in turn, determined and, using the determined harmonic-impedance and damping-resistance values, corresponding values of an electrical load parameter, preferably load voltage, are determined for the desired step capacitance change. The method is conveniently extended to cover a method and apparatus for applying power-factor correction capacitance, in which the load-voltage values for the various harmonics are evaluated to see if they represent a potential resonance condition and, if so, a step change other than the desired change is applied. Where no resonance is indicated, the originally intended step change is applied. 
     Allinder, U.S. Pat. No. 7,400,517, discloses a power factor correction circuit configured to use a stored value of a feedback signal to assist in regulating the value of an output voltage and to bypass the sample and hold circuit if the output voltage increase to an upper limit or decreases to a lower limit. 
     Coleman, U.S. Pat. No. 7,315,150, discloses a ripple current mode power converter comprised of a magnetic energy storage element, and a method of determining magnetic storage element charge duration based on periodic magnetic storage element current samples. In the preferred embodiment a controller processes a magnetic storage element ripple current, and average sampled current, to achieve high power factor forgoing the need to sense the AC signal current and voltage levels. The controller element periodically calculates the magnetic storage element charge duration to control the state of the switch element to maintain the AC input current proportional to the AC input voltage. 
     Li, U.S. Pat. No. 7,359,224, discloses a circuit for providing power factor correction in accordance with an embodiment of the present application which may include a boost converter circuit and a control circuit receiving as inputs; a rectified AC input voltage from a rectifier, a signal proportional to current through the boost inductor and the DC bus voltage across the capacitor of the boost converter. The control circuit provides a pulse width modulated signal to control the on time of a PFC switch. The control circuit further includes a voltage regulator and a current regulator. The current regulator includes a difference device operable to subtract a signal proportional to the inductor current from the current reference signal, a PI controller adapted to receive the output of the difference device and provide a first control signal, a feed forward device operable to receive the rectified AC input voltage and to provide a second control signal with a smaller dynamic range than the AC input voltage, and an adder operable to add the first control signal to the second control signal to provide a PWM reference signal for generating the pulse width modulated signal. A zero crossing detector and vector rotator may be provided to provide a clean sinusoidal reference to the current regulator. A partial PFC regulator may be provide to provide partial mode PFC if desired. 
     Shteynberg et al, U.S. Pat. No. 7,149,097, discloses a switch mode AC/DC converter with input current shaped for unity power factor. Input current is modulated by input voltage, an input inductor and an isolation transformer driven with the same duty ratio, with a low voltage across a bulk capacitor. This voltage is determined only by input voltage amplitude. Energy stored in a leakage inductance of the transformer is returned back to the internal DC source. A soft switching circuit is connected to the primary side, eliminating the need for high side drive. Sources of the main and auxiliary switches and primary winding of the transformer are connected to ground for easy primary voltage sensing. Overvoltage protection circuit of the output is connected to exclusively primary side signals. Secondary synchronous rectifier is driven by a circuit synchronized with the system clock. The circuit can be coupled to either the primary or the secondary winding of the isolation transformer. 
     Acatrinei, US application 2005/0212501, discloses a low cost high performances power factor correction method, system and apparatus, comprising an AC power source able to provide a low frequency supply signal, a low frequency pass filter circuit able to protect the power source against reverse high frequency signal noise, a rectifier circuit able to provide a fully rectified low frequency supply signal, a high frequency DC/DC converter circuit able to convert the fully rectified low frequency supply signal into a rectified high frequency supply signal having the capability to absorb and deliver at any moment a current amount contingent and linearly proportional in amplitude to its supply voltage amount and/or its driving pulses duty cycle ratio, a small signal controller circuit able to control the converter circuit and a complex load circuit including at least one capacitor able to store the rectified high frequency supply signal, so the small signal controller circuit controls the large signal converter circuit by means of a pulse width modulation driving signal consisting of trains of pulses constant in frequency and duty cycle during a period of time equal or longer than one of the AC power source supply signal semi-cycle period so during each the supply signal&#39;s semi-cycle period, as long as the controlling pulse is constant, the current amount absorbed by the large signal circuit from the AC power source is contingent and linearly proportional to the AC power source&#39;s voltage amount only, so the AC power source&#39;s output current and voltage amount follows an identical graphic shape and so the energy transfer&#39;s power factor parameter of the AC power source and the complex load system is improved to near unity. 
     The related art described above discloses circuits using sample-hold technique for power factor correction in a power system. However, the present invention using a sample and hold circuit that distinguishes over the prior art providing heretofore unknown advantages as described in the following summary. In the present AC electrical system a source produces an input voltage and current. The source is interconnected through an energy storage device with a load across which an output voltage appears, and a unity power factor control circuit is operated according to a method for maintaining unity power factor. This method comprises the steps of producing a sample and hold voltage derived from the input voltage and the output voltage wherein the sample and hold voltage maintains constant values between pulses of a clock signal. A modulated signal is turned on at each clock pulse fall. Sampling of the input voltage is initiated each time the clock signal turns on and holds the input voltage when the clock signal turns off. The held voltage value continues to be held until a current feedback voltage equals the held voltage whereupon the modulated signal turns off thereby drawing the input voltage and the input current into phase over a plurality of cycles of the clock signal. 
     BRIEF SUMMARY OF THE INVENTION 
     This disclosure teaches certain benefits in construction and use which give rise to the objectives described below. 
     A power factor correction method uses a sample and hold circuit to take timed samples of a source or “mains” voltage in accordance with a pulse width modulator. The resultant signals of the sample and hold circuit are processed through a further logic circuit to correct the phase angle between the voltage and current waveforms of the mains. 
     A primary objective inherent in the above described apparatus and method of use is to provide advantages not taught by the prior art. 
     Another objective is to reduce power loss by maintaining unity power factor. 
     A further objective is to provide a power factor correction circuit that can be implemented at low cost. 
     A further objective is to provide such a circuit that can be implemented using either a hard wired circuit or a software enablement. 
     A further objective is to provide such a circuit that is able to bring power factor in a AC system close to unity quickly. 
     Other features and advantages of the present invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the presently described apparatus and method of its use. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S) 
       Illustrated in the accompanying drawing(s) is at least one of the best mode embodiments of the present invention in such drawing(s): 
         FIG. 1  is an electrical schematic diagram of a power factor correction circuit according to the presently described invention; 
         FIG. 2  is a logic flow diagram of a logic portion thereof; 
         FIG. 3  is a waveform chart showing line voltage and current and digital waveforms for control signals; 
         FIG. 4  is a waveform chart showing how power factor is controlled; 
         FIG. 5  is a waveform chart showing mains voltage and current at unity power factor and their responses with respect to the step change of the load current; and 
         FIG. 6  is a waveform chart similar to  FIG. 5  but showing a takeoff of the voltage and current as full-wave rectified waveforms. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The above described drawing figures illustrate the described apparatus and its method of use in at least one of its preferred, best mode embodiment, which is further defined in detail in the following description. Those having ordinary skill in the art may be able to make alterations and modifications to what is described herein without departing from its spirit and scope. Therefore, it should be understood that what is illustrated is set forth only for the purposes of example and should not be taken as a limitation on the scope of the present apparatus and its method of use. 
     Described herein is a power distribution system incorporating a preferred power factor correction (PFC) circuit as shown in  FIG. 1 . Described also, is a method of its use for power factor correction. The power distribution system per se, comprises a sinusoidal power supply, referred to herein as a “mains” which drives load Z 1  through an energy storage device such as inductance L 1 . In the present embodiment, the mains voltage and current are full sinusoids as shown in  FIG. 5 , wherein mains voltage is pinned and mains current varies in accordance with load demand as shown by the load current signal shown at the bottom of  FIG. 5 . In the present description, supply voltage Vs and supply current Is are shown as full wave rectified signals in  FIG. 6  due to bridge circuit D 1 , D 2 , D 3  and D 4 . The PFC circuit is energized by input voltage V 1  derived from a voltage divider circuit R 1  and R 2  as would be necessary when supply voltage Vs is large. 
     The method of this invention is summarized in the waveform diagram of  FIG. 3  which show the relationship between V 5 , V 6 , V 8  and V 9 . At the bottom of the diagram we see a clock signal V 5  which has a fixed time sequence of pulses with cycle time T, the inverse of the fixed clock frequency fs. At the top of the diagram is sample and hold voltage V 6 . As shown, V 6  is held constant between consecutive pulses of V 5 , that is, during the time when clock signal V 5  is zero. Modulated signal V 9  is a pulse width modulated signal controlled by V 8  and |V 8 | grows linearly in magnitude until it equals |V 6 | whereupon it drops to zero. These relationships and their method of controlling power factor will be described below. 
     Referring now to  FIG. 1 , this circuit provides an output voltage Vo which is combined with a reference voltage V 3  in a feedback compensator G(s) to produce a resultant voltage V 2  which is proportional to Vo so as to provide a current reference voltage V 4  through the multiplier U 2 , that is, as multiplied by V 1 . V 1  and V 2  are multiplied producing the current reference voltage V 4 . The clock circuit U 9  produces a clock pulse signal V 5 , as described above, which is a time sequence of on-state pulses; see  FIG. 3 . A sample and hold circuit U 3 , driven by clock signal V 5  samples the value of current reference voltage V 4  at each on-state of V 5  thereby producing the sample and hold voltage V 6 . 
     In one embodiment of the present method, and as shown in  FIG. 1 , four voltages are provided to logic circuit LC 1  including: sample and hold voltage V 6 , clock pulse signal V 5 , inverted clock pulse signal V 7 , which is the output signal of inverter U 8 , and current to sensing voltage V 8 . In a further embodiment, the logic function of LC 1  may be alternately implemented by a software program as shown in  FIG. 2 . 
     The output of LC 1  is the modulated signal V 9  with is a pulse width modulated signal delivered to a gate driver DR 1 . DR 1  delivers a driver signal V 10  to a first switch M 1 . First switch M 1  is closed each time inverted clock pulse signal V 7  is high, i.e., when clock circuit U 9  turns off During the time that first switch M 1  is closed, V 8  rises linearly (see  FIG. 3 ) and in proportion to the current flowing through sensing resistor R 4 . M 1  remains closed until V 8  rises above the level of V 6 , the sample and hold voltage, whereupon M 1  opens and V 8  drops to zero. 
     During the time first switch M 1  is closed, energy storage device L 1  stores energy. When M 1  opens the energy stored in L 1  is delivered to the load Z 1  through diode D 5 . A capacitance C 1  may be placed across load Z 1  in order to store energy and also to reduce voltage ripple across load Z 1 . 
     First switch M 1  opens and closes in a series of cycles which draws Vs and Is into phase over a few cycles of the clock signal V 5  which is a small fraction of a cycle of the mains voltage. Therefore, as long as the present inventive circuit is operational with the mains voltage Vs and the load Z 1 , the power factor will effectively be unity. This is true in that when the power factor tends to instantaneously drop below unity, Vo also tends to drop and V 4  and V 6  will tend to increase proportionately as V 8  rises which causes the duty cycle of DR 1  to increase. Therefore, the average current through M 1  increases which means that the energy stored in L 1  increases. Each time M 1  opens the energy in L 1  is delivered to Z 1  and C 1 . Thus, by changing the duty cycle of DR 1  in this manner, power factor is maintained at unity. 
     In  FIG. 4  the horizontal axis is time and the vertical axis shows the on/off sense and voltage magnitude of several operational signals. At the bottom of this waveform chart we see V 5  the clock pulse waveform and above it is shown the inverse waveform of V 7 . Above this is shown the waveforms of S 2 , S 4  and V 10 .  FIG. 1  identifies these points in the circuit diagram. Above the waveform chart for V 10  we see the time based waveforms for voltages V 6  and V 8 . During each clock cycle, defined by V 6 , voltage V 8  ramps linearly until it equals voltage V 6  whereupon V 8  drops to zero for the remainder of the cycle. 
     The above described circuit and method is wholly applicable to a single or multiphase system. 
     In  FIG. 1 , LC 1  shows a hardware enablement of the logic circuit of the invention. Here we see that comparator U 1  receives V 6  and V 8  and its output S 1  is high when V 8  is greater than V 6 . OR gate U 4  receives S 1  and V 5  and its output S 2  is high when either, or both, S 1  and V 5  are present. Comparator U 1  receives V 6  and V 8  and its output S 1  is high when V 8  is greater than V 6 . Digital power supply U 10  provides voltage Vdd across resistor R 3  to pull down input D of the D-flip-flop U 5  when the V 5  pulse of clock U 9  switches M 2  on. At that instant U 5  is reset and the output S 3  is low. S 4  is high during the V 5  pulse which resets RS-flip-flop U 6 . This drives V 9  low and driver DR 1  opens switch M 1 . After each V 5  pulse, V 7  goes high which forces the output V 9  of U 6  high and V 10  of driver DR 1  closes switch M 1 . At this time a switch current Isw flows across switch M 1  and through R 4 . Voltage V 8  is the product of current Isw and the value of resistor R 4 . As previously described if V 8  is greater than V 6  then M 1  opens for the rest of the cycle of clock U 9 . If, however, V 8  is less than V 6 , then M 1  remains closed until V 8  is greater than V 6 . 
     In  FIG. 2  a software enablement is described which may be used to replace LC 1 . Here, software values are assigned to the variables and associated with LC 1  and the value of “n” is assigned as a cycle number. These values include clock pulse V 5 , inverted clock pulse V 7 , the reference voltage V 3  and n is set to unity. The sample and hold voltage V 4  is assumed to be zero at time t 1  when a pulse of clock signal V 5  appears. V 4  is held constant when V 5  is off so that V 6  equals V 4  at a time t 2 . As long as V 5  is off, V 7  is on and switch M 1  closes. V 8  and V 6  are compared and when V 8  is less than V 6 , M 1  closes, otherwise M 1  opens and n is incremented to n+1. This cycle is repeated starting with the sampling function. 
     The enablements described in detail above are considered novel over the prior art of record and are considered critical to the operation of at least one aspect of the apparatus and its method of use and to the achievement of the above described objectives. The words used in this specification to describe the instant embodiments are to be understood not only in the sense of their commonly defined meanings, but to include by special definition in this specification: structure, material or acts beyond the scope of the commonly defined meanings. Thus if an element can be understood in the context of this specification as including more than one meaning, then its use must be understood as being generic to all possible meanings supported by the specification and by the word or words describing the element. 
     The definitions of the words or drawing elements described herein are meant to include not only the combination of elements which are literally set forth, but all equivalent structure, material or acts for performing substantially the same function in substantially the same way to obtain substantially the same result. In this sense it is therefore contemplated that an equivalent substitution of two or more elements may be made for any one of the elements described and its various embodiments or that a single element may be substituted for two or more elements in a claim. 
     Changes from the claimed subject matter as viewed by a person with ordinary skill in the art, now known or later devised, are expressly contemplated as being equivalents within the scope intended and its various embodiments. Therefore, obvious substitutions now or later known to one with ordinary skill in the art are defined to be within the scope of the defined elements. This disclosure is thus meant to be understood to include what is specifically illustrated and described above, what is conceptually equivalent, what can be obviously substituted, and also what incorporates the essential ideas. 
     The scope of this description is to be interpreted only in conjunction with the appended claims and it is made clear, here, that each named inventor believes that the claimed subject matter is what is intended to be patented.