Abstract:
A method and system in which the numeric values to which counters in resampling control circuitry may be reduced. As a result, smaller registers to hold such reduced numeric values may be designed into hardware implementing said circuitry. These smaller registers present savings in processing power and hardware allocation, thereby potentially improving response times and cost efficiency of said hardware.

Description:
TECHNICAL FIELD OF THE INVENTION 
     This invention relates to control over data resampling and more specifically to resampling control circuitry whose processing power requirements are sensitive to the numeric levels to which such circuitry may count in analyzing data to be resampled. 
     BACKGROUND OF THE INVENTION 
     It is well understood in the video art that adaptations of sampled digital data, such as resizing a pixelated image, may be accomplished using resampling techniques. In the resized image example, an image will have already been digitally sampled, and interpolation or decimation of the samples may be required to make the image larger or smaller respectively. Generation of new samples according to the required interpolation or decimation is normally enabled by circuitry controlling a resampling filter. The resampling filter then analyzes the existing sampling data and creates new samples from characteristics of the existing samples according to design functionality of the particular filter. 
     The present invention is directed to control circuitry of the resampling filter. Conventional techniques in controlling a resampling filter use logic whereby an instruction to generate a new sample is created according to a step, which is a function of the interval of the existing samples. In the application of resizing a video image, it will be understood that the step may be a function of the scale factor by which the image is to be enlarged or reduced. 
     Control logic is known where input counters increment numerically the existing samples as they are encountered in the incoming data stream, as &#34;source&#34; counters (referring to an eventual &#34;source&#34; signal for the resampling filter) increment values of the chosen step in partial synchrony with the input counters. Between each increment of the input counter, the input counter is compared with the integer value of the source counter, and if greater than or equal to the integer value of the source counter, the circuit will (1) send an instruction to the resampling filter to generate a sample, and (2) increment the source counter by one step. In decimation, the input counter will then also be incremented by one. In interpolation, however, the input counter may or may not then be incremented, depending on whether the step value is sufficiently large to cause another data sample to be encountered. 
     If, on the other hand, the integer value of the source counter is determined to be less than the input counter, then the circuit will not send an instruction to the resampling filter and instead will simply allow the cycle to repeat by adding one more to the input counter. This existing art is illustrated in FIG. 3, and will be discussed in greater detail below. 
     It is a necessary evil of this type of resampling control to have to analyze the entire length of the incoming data stream before the resampling exercise can be completed, (and, in the application suggested above, the video image can be resized). This means that all of the existing input samples must be counted before the job is done. And, according to the conventional technique described above, this means that the input and source integer counters may have to increment to high values. This creates problems in hardware design and performance. First, registers must be allocated for the input counter and the integer value of the source counter to receive count values of considerable size. This represents potentially inefficient use of hardware, and also requires that a fixed maximum register size must be pre-designed. Second, considerable processing power must be allocated incrementing these registers to high values as the incoming data stream is analyzed. This draw on processing power may take capacity away from other functions as well as potentially slowing response time. With regard to processing power, it will be understood that when counting, a savings of only one or two bits may result in exponential decrease in processing power requirements. 
     Accordingly, a need exists for resampling filter control circuitry that will resample an incoming data stream without incrementing counters to high values. Specifically, it would be highly desirable to control the resampling of a given data stream by counting to lower values, especially if the limits of such control were more flexible, and not directly dependent on some pre-designed maximum data sample count. 
     SUMMARY OF THE INVENTION 
     One advantage of this invention is that it reduces the numeric values to which resampling filter control circuitry may need to count in resampling a data stream of a given length. As more fully described below, the invention does this by recognizing that once the logic has sent one or more instructions to resample, much of the numeric value of the input count and the source integer count has become essentially redundant, and may be cleared. 
     The present invention therefore makes periodic adjustments to reduce the input count and the source integer count as instructions to resample are sent. By doing this, the numeric capacity of these counters becomes independent of the length of the data stream being analyzed, and instead becomes a function of the particular step being used in the resampling process. As applied to the example of resizing a video image, this means that the required numeric capacity of these counters becomes a function of the numeric value of the resize scale rather than of the size of the image. 
     Another advantage of this invention is that it improves speed and cost-effectiveness in hardware. Once again with reference to the example of resizing a video image, let it be assumed that a full screen video image on a 1024 pixel/line computer monitor is desired to be reduced to a screen icon 32 pixels wide. The reduction scale is 32:1, and, assuming linear resampling, the decimation step will be 32. Under conventional resampling control circuitry, 11-bit registers capable of storing binary count values of at least 1024 would be required. As will be shown in greater detail below, with the present invention, 6-bit registers capable of storing binary count values of only 32 will be required. As a result, considerable potential savings on processing power may contribute to faster, more cost-effectively designed hardware. 
     Yet another advantage of the invention is that control over resampling is now no longer directly dependent on a pre-designed maximum length of data stream that may be resampled. Although having limits related to data stream length, the invention&#39;s key design parameter is step. Thus, in theory, any length data stream may be resampled to a limit of a pre-designed maximum step. Of course, a data stream length limitation may arise above which the maximum step, when applied to that data stream, is no longer compatible with the level of interpolation or decimation desired of the resampling. Before that limit is reached, however, the invention will have provided substantially improved flexibility and processing power economy in resampling. Further, again with reference to the video image resizing example, a practical application of the invention suggests that in normal use, enlargement or reduction of images much above a factor of 64 would be highly specialized. 
     It will be further recognized that although the foregoing summary has been illustrated by reference to an example of resizing a video image, those of skill in this art will understand that the present invention as described herein is not limited to such applications. Being directed to control circuitry over resampling generally, it will be understood that the present invention has applications wherever faster, more cost-effective, and/or more flexible control over resampling may be advantageous. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a high level block diagram of a circuit embodying the present invention; 
     FIG. 2 is a flow chart illustrating the logic of the present invention; 
     FIG. 3 is a flow chart of currently known logic on which the present invention improves; and 
     FIG. 4 is a high level block diagram illustrating how output from the circuit illustrated in FIG. 1 may be used to control a resampling filter. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As noted above, control circuits are known with logic as illustrated in FIG. 3. Let it be assumed that an input counter is incrementing data samples encountered in an existing data stream, and a source counter, when instructed to do so, is incrementing values of a step. The numeric value of the input counter is compared with the integer value of the source counter (block 301). If the input counter is less than the integer value of the source counter, then a condition found only in decimation will have been encountered, when the step value is sufficiently large to require at this time one or more of the existing data samples to be skipped. The input counter is incremented by 1 (block 302), and the cycle repeats. 
     If, however, the input counter is greater than or equal to the integer value of the source counter, then a resample is required in this cycle. The control circuit sends an instruction to the resampling filter to resample (block 303), and a calculated value &#34;NEXTSRC&#34; acquires the value of the source counter incremented by one step (block 304). The integer value of the source counter is then compared with the integer value of NEXTSRC (block 305). They are equal, then a condition found only in interpolation will have been encountered, when the step value is sufficiently small to require at this time that the next resample be generated from the same existing data sample neighborhood. In this case, as illustrated in block 306, the source counter is assigned the value of NEXTSRC (i.e. incremented by one step by virtue of the operation of block 304), but the input counter is not incremented in this cycle. 
     If, on the other hand, the comparison in block 305 shows that the integer values of the source counter and NEXTSRC are not the same, then the source counter is assigned the value of NEXTSRC (block 307) and the input counter is incremented by one (block 308). 
     As explained in greater detail above, this logic lacks any mechanism to minimize the numeric values of the input counter and the source integer value, and so the circuit must be designed with register capacity to accommodate large numeric values in order to handle long data streams or data streams with many existing data samples. 
     The logic of a control circuit embodying the present invention is illustrated on FIG. 2. Again, let it be assumed that an input counter is incrementing data samples encountered in an existing data stream, and a source counter, when instructed to do so, is incrementing values of a step. Logic similar to FIG. 3 applies if, when the numeric value of the input counter is compared with the integer value of the source counter (block 201), the integer value of the source counter is less than input counter. As before, a condition peculiar to decimation has been encountered whereby one or more existing data samples needs to be skipped, and so resampling is not needed in this cycle. The input counter is therefore incremented by 1 (block 202), and the cycle repeats. 
     If, however, the input counter is greater than or equal to the integer value of the source counter, then a resample is required in this cycle. As before, the control circuit sends an instruction to the resampling filter to resample (block 203), and calculated value NEXTSRC acquires the value of the source counter incremented by one step (block 204). Once again, the integer value of NEXTSRC is compared with the integer value of the source counter to see if they are equal (block 205). 
     At this point, the present invention comes into effect. The input counters and the source integer counters are now readjusted downwards (blocks 206, 207, 208 and 209). It will be understood, however, that the integrity of the source counter&#39;s fraction value must be preserved, since the resampling filter relies on this fraction value to determine, among other information, the phase in which to resample. 
     Accordingly, if the integer value of NEXTSRC is found to be equal to the integer value of the source counter, the integer value of the source counter is reset to zero, and the fraction value of the source counter is assigned the fraction value of NEXTSRC (block 206). The input counter is then reset to 0 (block 207). This process takes account of the condition encountered only in interpolation when the step is sufficiently small for the next resample to be required to be generated with reference to the same input date samples. As a result, the input counter is not incremented on this cycle. 
     If, on the other hand, the integer values of NEXTSRC and the source counter are found not to be equal, then the integer value of the source counter is assigned the integer value of NEXTSRC minus (INP+1), where INP is the current numeric value of the input counter (block 208). The fraction value of the source counter is assigned the fraction value of NEXTSRC. The input counter is then reset to 0 (block 209). 
     The effect of the foregoing improvement is to limit substantially the numeric values to which the input counter and the source integer counter must count. As best described by example below, let it be assumed resampling is required in order to decimate, and that the step is a value of 1.4. Under logic illustrated in FIG. 3, the first 14 cycles will yield results as follows: 
     
         ______________________________________Input Source   Inp &gt;= (Int)Src?                      Gen Sample?                               NEXTSRC______________________________________0     0        Yes         Yes      1.41     1.4      Yes         Yes      2.82     2.8      Yes         Yes      4.23     4.2      No          No       4.24     4.2      Yes         Yes      5.65     5.6      Yes         Yes      7.06     7.0      No          No       7.07     7.0      Yes         Yes      8.48     8.4      Yes         Yes      9.89     9.8      Yes         Yes      11.210    11.2     No          No       11.211    11.2     Yes         Yes      12.612    12.6     Yes         Yes      14.013    14.0     No          No       14.014    14.0     Yes         Yes      15.4______________________________________ 
    
     The input counters and the source integer counters are both at 14. Now compare with results yielded by the logic illustrated in FIG. 2: 
     
         ______________________________________Input Source   Inp &gt;= (Int)Src?                      Gen Sample?                               NEXTSRC______________________________________0     0        Yes         Yes      1.40     0.4      Yes         Yes      1.80     0.8      Yes         Yes      2.20     1.2      No          No       2.21     1.2      Yes         Yes      2.60     0.6      Yes         Yes      2.00     1.0      No          No       2.01     1.0      Yes         Yes      2.40     0.4      Yes         Yes      1.80     0.8      Yes         Yes      2.20     1.2      No          No       2.21     1.2      Yes         Yes      2.60     0.6      Yes         Yes      2.00     1.0      No          No       2.01     1.0      Yes         Yes      2.4______________________________________ 
    
     It will be seen immediately that the logic of the present invention has accomplished the same task as in FIG. 3, but that in doing so, the input and source integer counters at no time exceeded 1. Note also that the integrity of the source counter fraction values remain preserved under the logic illustrated by FIG. 2. It will be still further seen by analogy that for any value of step chosen, the input and source counters will never exceed the integer value of the step. Long data streams, or data streams with many samples may thus be analyzed without the need to count to numerically high numbers in the resampling filter control circuitry. 
     Similar improvements arise if the resampling is instead required in order to interpolate. Let it be assumed that now the step is a value of 0.8. Under the logic illustrated in FIG. 3, the first 14 cycles will yield results as follows: 
     
         ______________________________________Input Source   Inp &gt;= (Int)Src?                      Gen Sample?                               NEXTSRC______________________________________0     0        Yes         Yes      0.80     0.8      Yes         Yes      1.61     1.6      Yes         Yes      2.42     2.4      Yes         Yes      3.23     3.2      Yes         Yes      4.04     4.0      Yes         Yes      4.84     4.8      Yes         Yes      5.65     5.6      Yes         Yes      6.46     6.4      Yes         Yes      7.27     7.2      Yes         Yes      8.08     8.0      Yes         Yes      8.88     8.8      Yes         Yes      9.69     9.6      Yes         Yes      10.410    10.4     Yes         Yes      11.2______________________________________ 
    
     It will be seen that the value of the input counter and the integer value of the source counter are increasing rapidly, and will continue to do so as long as new data samples continued to be encountered in the data stream. 
     In contrast, however, under the logic illustrated in FIG. 2, the first 14 cycles will yield results as follows: 
     
         ______________________________________Input Source   Inp &gt;= (Int)Src?                      Gen Sample?                               NEXTSRC______________________________________0     0        Yes         Yes      0.80     0.8      Yes         Yes      1.60     0.6      Yes         Yes      1.40     0.4      Yes         Yes      1.20     0.2      Yes         Yes      1.00     0        Yes         Yes      0.80     0.8      Yes         Yes      1.60     0.6      Yes         Yes      1.40     0.4      Yes         Yes      1.20     0.2      Yes         Yes      1.00     0        Yes         Yes      0.80     0.8      Yes         Yes      1.60     0.6      Yes         Yes      1.40     0.4      Yes         Yes      1.2______________________________________ 
    
     Again, the same logic result has been achieved, and the integrity of the source counter fraction values has been preserved, but the input counter and the source integer counter never get above zero. In an interpolation mode, therefore, the present invention also allows long data streams, or data streams with many samples to be analyzed without the need to count to numerically high numbers in the resampling filter control circuitry. 
     An embodiment of the present invention in a resampling filter control circuit is illustrated on FIGS. 1 and 4. Turning first to FIG. 1, control circuit 10 comprises an input counter 102 and a source counter 103. It will be seen that source counter 103 is able to analyze integer and fraction values separately. The input count is analyzed at gate 104 to see if it is greater than or equal to source count integer value, and the result is fed to control logic 108. If it is not, then control logic 108 adds one to input counter 102 by instructing multiplexer 109 to feed input counter 102 with a cycle from adder 101. The cycle then repeats. 
     If it is, then control logic 108 sends an instruction to output control to generate a resample, and then looks to gate 107. Gate 107 is analyzing the integer value of source counter 103 to see if it is equal to the integer value of NEXTSRC, the calculated value in adder 105 as it increments the current full, combined integer and fraction value of source counter 103 by the step. If it is equal, then control logic instructs multiplexer 110 to set the integer value of the source counter to zero, while the fraction value of NEXTSRC is extracted from adder 105 and is assigned as the fraction value of source counter 103. Control logic 108 then sends an instruction to multiplexer 109 to reset input counter 102 to zero, and the cycle then repeats. 
     If gate 107 determines that the source counter integer value is not equal to the integer value of NEXTSRC residing in adder 106, however, then control logic 108 instructs multiplexer 109 to cycle adder 101 and yield a value of the current input count plus one. Subtractor 106 then subtracts this value from the integer value of NEXTSRC residing in adder 105, and the result is assigned as the integer value of source counter 103. The fraction value of NEXTSRC is extracted from adder 105 and is assigned as the fraction value of source counter 103. Control logic 108 then sends an instruction to multiplexer 109 to reset input counter 102 to zero, and the cycle then repeats. 
     Turning now to FIG. 4, it will be seen that resampling filter 40 is analyzing an incoming data stream and creating a series of output data samples in accordance with the output control circuit 10 as described above on FIG. 1. The phase of the incoming data stream is also fed to resampling filter 40 so that information may be extracted therefrom, if desired, in combination with the fraction value of the source counter as described above. 
     It will also be understood by those in this art that the logic of the present invention may also be embodied by software executable on a general purpose computer having memory, a central processing unit, and advantageously also a display means. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.