Abstract:
A control circuit for adjusting leading edge blanking time is disclosed. The control circuit is applied to a power converting system. The control circuit adjusts a leading edge blanking time according to a feedback signal relative to a load connected to the output terminal of the power converting system. An over-current protection mechanism of the power converting system is disabled within the leading edge blanking time.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a control circuit for leading edge blanking time, and more particularly, to a control circuit for adjusting a leading edge blanking time and a power converting system including such a control circuit. 
   2. Description of the Prior Art 
     FIG. 1  is a diagram of a flyback converter  10  according to the prior art. A pulse-width modulation (PWM) control chip  100  outputs a PWM signal V PWM  at an output pin OUT to control the turn-on and turn-off of a power switch  101  for transforming an input voltage Vin into an output voltage Vout. In order to prevent a large primary-side current lp of the flyback converter  10  from damaging elements, the PWM control chip  100  further detects a voltage level Vcs (Vcs=Rs×lp, which is generated by the primary-side current lp flowing through a sensing resistor Rs) at a current sensing pin CS. When the voltage level Vcs reaches a predetermined reference voltage level for over-current protection, the PWM control chip  100  enables an over-current protection mechanism. The output pin OUT stops outputting the PWM signal V PWM  to turn off the power switch  101 , which cuts off the primary-side current lp and thereby prevents the over-current phenomenon. 
   However, a spike is generated at the transient when turning on the power switch  101 , which makes the voltage level Vcs detected by the current sensing pin CS rise immediately. Therefore, a fault trigger in the over-current protection mechanism of the PWM control chip  100  may happen. If the power switch  101  is wrongly turned off without an over-current phenomenon, the operations of the flyback converter  10  will be influenced. One solution is to add a leading edge blanking mechanism to the PWM control chip  100 . The voltage signal Vcs detected by the current sensing pin CS is ignored (i.e., the over-current protection mechanism is not enabled) by the PWM control chip  100  within a leading edge blanking time, which begins at the moment when the power switch  101  is turned on. 
   Presently, most of the PWM control chips with current mode control have a built-in control circuit with a fixed leading edge blanking time. However, the control circuit with the fixed leading edge blanking time exhibits two disadvantages listed below: 
   When the power switch  101  is turned off, its drain voltage is Vd=Vin+(Vout/N)+lp×(Lk/Cd) 1/2 , wherein N is a turn ratio between the secondary-side winding and the primary-side winding of the transformer, Lk is a leakage inductor of the primary-side winding of the transformer, and Cd is the stray capacitor of the power switch  101 . When the flyback converter  10  is turned on, a secondary-side current Is charges an output capacitor Co to increase the output voltage Vout from zero gradually. If the flyback converter  10  is at full load condition, the output voltage Vout will rise up slower. As can be known from the equation of Vout=L×(dls/dt), it&#39;s very difficult to fully release energy from the primary-side winding of the transformer T 1  to the secondary-side winding of the transformer T 1 . Because the power switch  101  is turned on within the leading edge blanking time, the primary-side current lp accumulates a huge value if the fixed leading edge blanking time is too long. If the input voltage Vin of the flyback converter  10  is high, the excessively high drain voltage Vd of the power switch  101  may damage the power switch  101 . 
   Most of the PWM control chips have a burst mode function. When the system is at light load condition, the PWM control chip  100  enters burst mode. At this time, if the voltage value of the feedback signal V COMP  of the PWM control chip  100  is smaller than a threshold level, the output pin OUT stops outputting the PWM signal V PWM . When the voltage value of the feedback signal V COMP  is greater than the threshold level, the system enters a normal current mode control and the output pin OUT starts to output the PWM signal V PWM , which makes the waveform of the feedback signal V COMP  a sine-wave-like pattern nearby the threshold level. When the PWM control chip  100  enters burst mode, the energy delivered from the input voltage Vin to the system may be smaller if the leading edge blanking time is too short. Therefore, the frequency of the sine-wave-like waveform of the feedback signal V COMP  gets higher, resulting in a higher switching loss and thus making the power-saving capability of the system poor. 
   SUMMARY OF THE INVENTION 
   It is one of the objectives of the claimed invention to provide a control circuit for adjusting leading edge blanking time, which is applied to a power converting system to solve the abovementioned problems. The control circuit adjusts a leading edge blanking time according to a feedback signal relative to a load connected to an output terminal of the power converting system to make an over-current protection mechanism of the power converting system disabled within the leading edge blanking time. The control circuit includes a variable charging current generating circuit, a capacitor, a charge/discharge switch, and a first comparator. 
   The variable charging current generating circuit generates a charging current proportional to a voltage value of the feedback signal. 
   The charge/discharge switch is coupled to the capacitor. When a power switch of the power converting system is turned on, the charge/discharge switch is turned off to charge the capacitor with the charging current. When the power switch is turned off, the charge/discharge switch is turned on to discharge the capacitor. 
   The first comparator has an input terminal coupled to the capacitor. When a voltage of the capacitor reaches a reference voltage of the first comparator, an output signal of the first comparator makes the power converting system enable the over-current protection mechanism. A time interval from the time the power switch is turned on until the time the voltage of the capacitor reaches the reference voltage of the first comparator is the leading edge blanking time. 
   The control circuit for adjusting leading edge blanking time can further include a charging current limit mechanism. If the voltage value of the feedback signal is smaller than a first threshold value, the charging current with a fixed minimum value is used for charging the capacitor when the power switch of the power converting system is turned on. If the voltage value of the feedback signal is greater than a second threshold value, the charging current with a fixed maximum value is used for charging the capacitor when the power switch of the power converting system is turned on. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram of a flyback converter according to the prior art. 
       FIG. 2(   a ) is a diagram showing a power converting system for adjusting leading edge blanking time according to the present invention. 
       FIG. 2(   b ) is a diagram showing a control circuit for adjusting leading edge blanking time according to a first embodiment of the present invention. 
       FIG. 3  is a diagram showing a control circuit for adjusting leading edge blanking time according to a second embodiment of the present invention. 
       FIG. 4  is a diagram showing a relationship between the leading edge blanking time and the voltage value of the feedback signal of the power converting system of the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 2(   a ) is a diagram showing a power converting system  20  for adjusting leading edge blanking time according to the present invention. The power converting system  20  includes a transformer T 2 , a power switch  202 , a current sensing resistor Rs, a feedback circuit  290 , and a PWM controller  2000 . The feedback circuit  290  outputs a feedback signal V COMP  having a voltage value proportional to a load connected to an output terminal of the power converting system  20 . 
   The PWM controller  2000  includes a control circuit  200  for adjusting leading edge blanking time, a PWM signal generator  201 , an over-current comparator  204 , and a logic gate  205 . The PWM signal generator  201  generates a PWM signal V PWM  to control the power switch  202  according to the feedback signal V COMP . 
   The over-current comparator  204  has a first input terminal (inverting input terminal) and a second input terminal (non-inverting input terminal), wherein the first input terminal receives an over-current protection reference voltage Vref 0  and the second input terminal receives a sensing voltage Vcs. Vcs=Rs×lp, which is generated by the primary-side current lp flowing through the sensing resistor Rs. 
     FIG. 2(   b ) is a diagram showing the control circuit  200  for adjusting a leading edge blanking time according to a first embodiment of the present invention. The control circuit  200  includes a voltage-to-current converting circuit  210 , a current mirror  220 , a capacitor  232 , a charge/discharge switch  234 , a first comparator  240 , a second comparator  250 , a first current source  260 , and a second current source  270 . 
   The voltage-to-current converting circuit  210  generates a first current IR 1  proportional to the voltage value of the feedback signal V COMP  (IR 1 =V COMP /R 1 ). The current mirror  220  generates a second current la identical to the first current IR 1 . The voltage-to-current converting circuit  210  and the current mirror  220  constitute a variable charging current generating circuit. 
   When the power switch  202  is turned on (i.e., the PWM signal V PWM  is at logic high voltage), the charge/discharge switch  234  (an NMOS transistor) is turned off. A charging current IC 1  charges the capacitor  232 , wherein the charging current IC 1  is provided by the second current Ia at this time. When a voltage VC 1  of the capacitor  232  is charged to the reference voltage Vref 1  of the first comparator  240 , an output signal V LEB  of the first comparator  240  changes from logic low into logic high to make the output signal of the logic gate  205  not fixed at logic low (please refer to  FIG. 2(   a )). In other words, the output signal of the over-current comparator  204  is delivered to the PWM signal generator  201  through the logic gate  205 . At this time, if the sensing voltage Vcs reaches the voltage level of the over-current protection reference voltage Vref 0 , the PWM signal V PWM  outputted from the PWM signal generator  201  changes from logic high to logic low according to the output signal with logic high voltage outputted from the over-current comparator  204 , and the power switch  202  changes from turn-on state into turn-off state. 
   When the power switch  202  is turned off (i.e., the PWM signal V PWM  is at logic low voltage), the charge/discharge switch  234  is turned on. Therefore, the capacitor  232  discharges through the charge/discharge switch  234  until the voltage VC 1  of the capacitor  232  decreases to zero. 
   A time interval from the time the power switch  202  is turned on, which results in the capacitor  232  starting to charge, until the time the voltage VC 1  of the capacitor  232  reaches the reference voltage Vref 1  of the first comparator  240  is called the leading edge blanking time T LEB . Within the leading edge blanking time T LEB , the output signal V LEB  of the first comparator  240  is at logic low voltage, which fixes the output signal of the logic gate  205  at logic low voltage. In this time, if the sensing voltage Vcs reaches the voltage level of the over-current protection reference voltage Vref 0 , a signal with logic high voltage at the output terminal of the over-current comparator  204  can&#39;t be delivered to the PWM signal generator  201  through the logic gate  205 . The PWM signal V PWM  outputted from the PWM signal generator  201  still maintains at logic high voltage and the power switch  202  is still turned on. 
   If the voltage value of the feedback signal V COMP  decreases, both the first current IR 1  and the second current Ia decrease. When the voltage value of the feedback signal V COMP  is smaller than a first threshold value Vth 1  (that is, the reference voltage Vref 2  of the second comparator  250 ), the second comparator  250  outputs a logic low signal to turn off a transistor Q 1  and turn on a transistor Q 2 . At this time, the charging current IC 1  is provided by a first current source  260 , and the charging current IC 1  is restricted at a minimum value, i.e., the current value of the first current source  260 . After the power switch  202  is turned on, the voltage VC 1  of the capacitor  232  rises to the reference voltage Vref 1  of the first comparator  240  with a slowest speed. Thus, the leading edge blanking time T LEB  is restricted at a fixed maximum value. Therefore, when the voltage value of the feedback signal V COMP  decreases to a very small value, the leading edge blanking time T LEB  being too long beyond a reasonable range can be avoided. 
   If the voltage value of the feedback signal V COMP  increases, both the first current IR 1  and the second current Ia increase. When the voltage value of the feedback signal V COMP  is greater than a second threshold value Vth 2 , a sum of the current values of the first current IR 1  and the second current Ia exceeds the current value of a second current source  270 . Due to the second current source  270  being unable to provide more current anymore, through the operation of the current mirror  220 , both of the first current IR 1  and the second current Ia are clamped at a half of the current value of the second current source  270 . Hence, the second threshold value Vth 2  is equal to [(½)×(the current value of the second current source  270 )×(the resistance R 1 )]. At this time, the transistor Q 1  is turned on and the transistor Q 2  is turned off (when the voltage value of the feedback signal V COMP  is greater than the reference voltage Vref 2  of the second comparator  250 , the second comparator  250  outputs a logic high signal to turn on the transistor Q 1  and turn off the transistor Q 2 ). The charging current IC 1  is equal to the second current Ia, and the charging current IC 1  has a maximum value at this time, i.e., a half of the current value of the second current source  270 . After the power switch  202  is turned on, the voltage VC 1  of the capacitor  232  rises to the reference voltage Vref 1  of the first comparator  240  with a fastest speed. Thus the leading edge blanking time T LEB  is restricted at a fixed minimum value. When the voltage value of the feedback signal V COMP  increases to a very large value, the leading edge blanking time T LEB  being too short beyond a reasonable range can be avoided. 
   When the voltage value of the feedback signal V COMP  is between the first threshold value Vth 1  (i.e., the reference voltage Vref 2 ) and the second threshold value Vth 2 , the transistor Q 1  is turned on and the transistor Q 2  is turned off. The charging current IC 1  is the second current Ia; that is, the current value of the second current Ia is equal to that of the first current IR 1 , and both are V COMP /R 1 . Therefore, when the voltage value of the feedback signal V COMP  becomes larger, the charging current IC 1  becomes larger and the leading edge blanking time T LEB  becomes shorter. That is to say, the leading edge blanking time T LEB  and the voltage value of the feedback signal V COMP  are inversely proportional. 
     FIG. 3  is a diagram showing a control circuit  300  for adjusting leading edge blanking time according to a second embodiment of the present invention. Compared with the control circuit  200  for adjusting leading edge blanking time according to the first embodiment, a third comparator  350  having a reference voltage Vref 3  is added into the control circuit  300 . Moreover, the configuration position of the second current source  270  is different from that in the first embodiment. 
   In the second embodiment, the reference voltage Vref 3  is used as the second threshold value Vth 2  and the reference voltage Vref 2  is used as the first threshold value Vth 1 . When the voltage value of the feedback signal V COMP  is between the reference voltage Vref 2  and the reference voltage Vref 3  (Vth 1 &lt;V COMP &lt;Vth 2 ), both the second comparator  250  and the third comparator  350  output a logic high signal to turn on the transistors Q 1  and Q 4  and to turn off the transistors Q 2  and Q 5 . The charging current IC 1  is provided by the second current Ia, and the current value of the second current Ia is equal to the current value of the first current IR 1 , both are V COMP /R 1 . Therefore, when the voltage value of the feedback signal V COMP  becomes larger, the charging current IC 1  becomes larger and the leading edge blanking time T LEB  becomes shorter. That is to say, the leading edge blanking time T LEB  and the voltage value of the feedback signal V COMP  are inversely proportional. 
   When the voltage value of the feedback signal V COMP  is smaller than the first threshold Vth 1  (i.e., the reference voltage Vref 2 ), the second comparator  250  outputs a logic low signal and the third comparator  350  outputs a logic high signal to turn on the transistors Q 2  and Q 4  and to turn off the transistors Q 1  and Q 5 . The charging current IC 1  is provided by the first current source  260  and is restricted at a minimum value; i.e., the current value of the first current source  260 . After the power switch  202  is turned on, the voltage VC 1  of the capacitor  232  rises to the reference voltage Vref 1  of the first comparator  240  with a slowest speed. Thus the leading edge blanking time T LEB  is restricted at a fixed maximum value. When the voltage value of the feedback signal V COMP  decreases to a very small value, the leading edge blanking time T LEB  being too long beyond a reasonable range can be avoided. 
   When the voltage value of the feedback signal V COMP  is greater than the reference voltage Vref 3 , the transistors Q 1  and Q 5  are turned on and the transistors Q 2  and Q 4  are turned off. The charging current IC 1  is provided by the second current source  270  and is restricted at a maximum value, i.e., the current value of the second current source  270 . After the power switch  202  is turned on, the voltage VC 1  of the capacitor  232  rises to the reference voltage Vref 1  of the first comparator  240  with a fastest speed. Thus the leading edge blanking time T LEB  is restricted at a fixed minimum value. When the voltage value of the feedback signal V COMP  increases to a very large value, the leading edge blanking time T LEB  being too short beyond a reasonable range can be avoided. 
     FIG. 4  is a diagram showing a relationship between the leading edge blanking time T LEB  and the voltage value of the feedback signal V COMP  of the power converting system  20  according to the first and second embodiments of the present invention. When the voltage value of the feedback signal V COMP  is smaller than the first threshold value Vth 1 , the leading edge blanking time T LEB  has a fixed maximum value T LEB(MAX) . When the voltage value of the feedback signal V COMP  is greater than the second threshold value Vth 2 , the leading edge blanking time T LEB  has a fixed minimum value T LEB(MIN) . When the voltage value of the feedback signal V COMP  is between the first threshold value Vth 1  and the second threshold value Vth 2  (Vth 1 &lt;V COMP &lt;Vth 2 ), the leading edge blanking time T LEB  is inversely proportional to the voltage value of the feedback signal V COMP . 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.