Abstract:
A read-out circuit capable of achieving an improvement in the reliability of a reference potential generating cell by utilizing a 1T-1C (one transistor—one ferroelectric capacitor) type FRAM which enables a reduction in area to constitute the reference potential generating cell is provided. A read-out circuit that amplifies a binary signal through a sense amplifier and reads out the amplified signal as a bit line potential is provided with a 0-level setting circuit that resets the lower potential signal in the binary signal to 0 V at a stage preceding the sense amplifier. By adopting this structure, a constant potential can be used as a reference potential, to achieve stable operation. In addition since a constant potential can be used as the reference potential, the degree of change occurring over time can be reduced. Furthermore, since the capacity of the reference potential line does not require a particularly large capacity, the power consumption during a read-out operation can be reduced.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to a read-out circuit in a ferroelectricity memory.  
           [0002]    The publication “FRAM IC Card Technology” (Hidemi Takasu and Toshinori Takuma, published by: Science Forum, 1999, p.p. 35˜40) explains the basic operation of a 1T-1C (one transistor—one ferroelectric capacitor) type ferroelectricity (FeRAM) and clarifies the problems arising therein.  
           [0003]    Description of the Related Art  
           [0004]    It has been noted that a reference potential generating cell (also referred to as a dummy memory cell), which is accessed more frequently compared to data memory cells, quickly becomes degraded to result in the reduction in the degree of change in the electrical charge occurring during a polarization inversion and a lower reference potential.  
           [0005]    When a 1T-1C type FRAM is used to constitute a reference potential generating cell, too, the reference potential generating cell which is accessed more frequently than data memory cells becomes degraded readily, resulting in a reduction in the degree of change in the electrical charge occurring during a polarization inversion and a lower reference potential, as described above. Thus, a problem in that an erroneous read-out tends to occur readily arises.  
           [0006]    In addition, while the publication mentions a 2T-2C type FRAM as a means for improving the reliability, it also asserts that since its memory cell array area is almost double the memory cell array area of the 1T-1C FRAM, its use will become extremely limited as further miniaturization is pursued in the future.  
           [0007]    The main object of the present invention, which has been completed by addressing the problem of read-out circuits in the prior art, is to provide a new and improved read-out circuit through which the reliability of the reference potential generating cell is improved while utilizing a 1T-1C type FRAM with a smaller area to constitute the reference potential generating cell.  
         SUMMARY OF THE INVENTION  
         [0008]    In order to achieve the object described above, the read-out circuit according to the present invention that amplifies a binary signal through a sense amplifier and reads out the amplified signal as a bit line potential is provided with a potential setting circuit that resets the signal corresponding to the lower potential in the binary signal to a given potential, at a stage preceding the stage at which the sense amplifier is provided. It is to be noted that the potential setting circuit may reset the lower potential signal to a potential near 0 V.  
           [0009]    By adopting this structure in which a constant potential can be used as the reference potential, stable operation is realized. In addition, since a constant potential is used as the reference potential, the degree of change occurring over time can be reduced. Furthermore, since the reference potential line is not required to have a large capacity, the power consumption during a read-out operation can be reduced.  
           [0010]    It is desirable that the potential setting circuit include a transistor the substrate potential of which can be set freely and that the operating point of the potential setting circuit can be adjusted via the transistor substrate potential. When such a structure is adopted, the operating point can be adjusted in conformance to the characteristics of the ferroelectricity capacitor when the process is completed. As a result, the operating point of the potential setting circuit can be set freely for a specific use.  
           [0011]    In addition, it is desirable that the potential setting circuit include a transistor and another transistor that is provided to forcibly discharge the charge stored at the gate of the first transistor. In such a structure, the electrical charge stored at the gate of the first transistor is forcibly discharged even during a high-speed operation, eliminating any residual charge at the gate, to enable stable operation.  
           [0012]    Moreover, the read-out circuit according to the present invention that amplifies a binary signal through a sense amplifier and reads out the amplified signal as a bit line potential, having, a potential setting circuit that resets a lower potential signal in the binary signal to a given potential, provided at a stage preceding the sense amplifier, wherein, the potential setting circuit includes, a first transistor having a gate thereof connected to a bit line, which is turned on when the potential generated at the bit line is equal to or lower than a specific threshold voltage, and a second transistor which is turned on in response to the first transistor entering an ON state and resets the potential at the bit line to a given potential is provided. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The above and other features of the invention and the concomitant advantages will be better understood and appreciated by persons skilled in the field to which the invention pertains in view of the following description given in conjunction with the accompanying drawings which illustrate preferred embodiments.  
         [0014]    [0014]FIG. 1 illustrates the read-out circuit in a first embodiment;  
         [0015]    [0015]FIG. 2 is a timing chart of the read-out and the rewrite;  
         [0016]    [0016]FIG. 3 illustrates the relationship between the potential and the bit line capacity;  
         [0017]    [0017]FIG. 4 illustrates the range of the bit line voltage fluctuation;  
         [0018]    [0018]FIG. 5 illustrates the read-out circuit in a second embodiment;  
         [0019]    [0019]FIG. 6 presents a diagram provided to illustrate the threshold voltage (operating point) setting for the 0-level setting circuit;  
         [0020]    [0020]FIG. 7 illustrates the read-out circuit in a third embodiment;  
         [0021]    [0021]FIG. 8 is a time chart of the read-out and the rewrite;  
         [0022]    [0022]FIG. 9 illustrates the read-out circuit in a fourth embodiment;  
         [0023]    [0023]FIG. 10 something a diagram provided to illustrate the threshold of value of voltage (operating point) setting for the 0-level setting circuit; and  
         [0024]    [0024]FIG. 11 illustrates the read-out circuit in a fifth embodiment. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0025]    The following is a detailed explanation of the preferred embodiments of the read-out circuit according to the present invention, given in reference to the attached drawings. It is to be noted that the same reference numbers are assigned to components having essentially identical functions and structural features in the specification and the drawings, to preclude the necessity for repeated explanation thereof.  
         [0026]    (First Embodiment)  
         [0027]    The first embodiment of the present invention is now explained in reference to FIGS.  1 ˜ 3 .  
         [0028]    A read-out circuit 100 that reads out stored data in a 1T-1C type FRAM (hereafter simply referred to as the “read-out circuit”) in the embodiment is characterized in that it includes a 0-level setting circuit 120 provided between a sense amplifier 110 and a bit line BL1 as shown in FIG. 1.  
         [0029]    the  0 -level setting circuit 120 engages in operation prior to the sense amplifier operation during a read-out to drive the potential at the bit line BL1 to 0 V when the potential at the bit line BL1 is currently set to “0”.  
         [0030]    A constant voltage should be supplied to a terminal SA as a reference potential Vref.  
         [0031]    [0031]FIG. 2 presents a timing chart of the read-out and the rewrite. In the initial state, all the terminals are set at 0 V. First, the level of an equalize signal EQ is raised at a time point t 0  to charge the bit line BL1 so as to set the bit line BL1 to 0 V.  
         [0032]    After lowering the level of the equalize signal EQ at a time point t 1 , the level at a word line WL 1  is raised to connect a memory cell Cm to the bit line BL 1 .  
         [0033]    At a time point t 2 , a source potential Vcc is applied to a plate line PL and the information in the memory cell Cm is read-out to the bit line BL 1 . The level of the potential generated at the bit line BL 1  at this point varies depending upon the polarization state of the memory cell Cm. It is assumed that the memory cell Cm is capable of holding information indicating “1” with a residual dielectric polarization P 1  and holding information indicating “0” with a residual dielectric polarization P 0 , as shown in FIG. 3. When information has been written, the memory cell Cm must have either the residual dielectric polarization P 1  or the residual dielectric polarization P 0 .  
         [0034]    When the memory cell Cm has the residual dielectric polarization P 1 , a read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and a bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 1  generated at the two ends of the bit line capacitor Cb, i.e., at the bit line BL 1 . Likewise, when the memory cell Cm has the residual dielectric polarization P 0 , the read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and the bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 0  generated at the bit line BL 1 .  
         [0035]    The level at a terminal A is raised at a time point t 3  to drive the 0-level setting circuit 120. the 0-level setting circuit 120 has a function of setting only the information indicating “0”, i.e., the bit line voltage V0 induced by the residual dielectric polarization P0, to 0V.  
         [0036]    Now, the operation of the 0-level setting circuit 120 is explained.  
         [0037]    the 0-level setting circuit 1 20  has a threshold voltage Vr0. The threshold voltage Vr0 is set by ensuring that; bit line voltage V0&lt;threshold voltage Vr0&lt;bit line voltage V1. It is known that, as presented as an example in FIG. 4, the characteristics (capacity) on the side on which the polarization is inverted tend to charge readily whereas the characteristics (capacity) on the polarization non-inversion side are relatively stable when the ferroelectricity characteristics become degraded due to fatigue or the like. Thus, it is desirable to set the threshold voltage Vr 0  toward the side on which the polarization is not inverted during a read-out, i.e., closer to the low potential side (toward the bit line voltage V 0 ) of the voltage generated at the bit line BL 1 , to ensure stable operation.  
         [0038]    The operation of the 0-level setting circuit 120 is performed as described below.  
         [0039]    If the potential generated at the bit line BL is equal to or lower than the threshold voltage Vr0 (“0” state), the bit line BL is grounded.  
         [0040]    If the potential generated at the bit line BL is higher than the threshold voltage Vr0 (“1” state), the bit line BL is floated to sustain the potential.  
         [0041]    At a time point t 4 , the level at the terminal SA is raised to amplify the information at the bit line BL 1  with the sense amplifier  110 , i.e., to amplify the “1” state to the source potential Vcc and amplify the “0” state to 0 V. It is assumed that a given constant voltage is supplied to the sense amplifier  110  as the reference potential Vref at this point. Since the potential at the bit line BL 1  is set to 0 V in advance by the 0-level setting circuit  120  if information indicating “0” is present at the bit line BL1, the reference potential Vref needs only to be at a level which corresponds to the detection sensitivity of the sense amplifier  110 . For instance, if the detection sensitivity of the sense amplifier  110  is 300 mV, the reference potential Vref may be set to Vref&gt;300 mV.  
         [0042]    In addition, since the bit line voltage V 1  is generated at the bit line BL 1  if information indicating “1” is present at the bit line BL 1 , the reference potential Vref should be set to; 300 mV&lt;reference potential Vref&lt;bit line voltage V 1  by taking into consideration the detection sensitivity of the sense amplifier  110 . As the example presented in FIG. 4 indicates, it is known that when the ferroelectricity characteristics have been degraded due to fatigue or the like, the characteristics on the side on which the polarization becomes inverted tend to change readily whereas the characteristics (capacity) on the polarization non-inversion side remain relatively stable. Thus, it is desirable to set the reference potential Vref to a low level within the setting range. The potential on the low potential side, which is sustained by the 0-level setting circuit  120  at a constant level of 0 V and does not change over time, is stable.  
         [0043]    In the polarization state shown in FIG. 3, P 1  changes to P 0 ′and then to P 0  if the memory cell Cm, whereas P 0  changes to P 0 ′(the “0” state is written again) if the “0” state has been written in the memory cell Cm.  
         [0044]    At a time point t 5 , the levels at the terminal A and the plate line PL are set to 0 V. In the polarization state shown in FIG. 3, P 0  changes to P 1 ′ and the “1” state is written again if the “1” state has been written in the memory cell Cm, whereas P 0 ′ changes to P 0  if the “0” state has been written in the memory cell Cm.  
         [0045]    At a time point t 6 , the bit line BL 1  is caused to float by setting the level at the terminal SA to 0 V. In the polarization state shown in FIG. 3, P 1 ′changes to P 1  if the “1” state has been written in the memory cell Cm, whereas P 0  is held if the “0” state has been written in the memory cell Cm, thereby ending rewrite of either data.  
         [0046]    At a time point t 7 , the level of the equalize signal EQ is raised to set the bit line BL1 to 0V.  
         [0047]    At a time point t 8 , the level of the equalize signal EQ is lowered to float the bit line BL 1 , and then the level at the word line WL 1  is lowered at a time point t 9  to complete the read-out/rewrite operation.  
         [0048]    As explained in detail above, since a constant potential can be utilized as the reference potential in the embodiment, a higher degree of stability is achieved and the degree of change occurring over time is reduced compared to the method in which the reference potential is generated by a dedicated capacitor, as explained as the prior art. In addition, since a constant potential Vref is supplied as the reference potential, the reference potential line does not require a particularly large capacity. As a result, a reduction in the power consumption is realized.  
         [0049]    It is to be noted that while the 0-level setting circuit  120  in the embodiment includes a ground line, this line may be utilized as a terminal through which an arbitrary level of voltage is supplied instead of grounding it. In such a case, the bit line potential is set in correspondence to the arbitrary voltage applied to the ground line of the 0-level setting circuit  120  in the “0” state.  
         [0050]    (Second Embodiment)  
         [0051]    The second embodiment of the present invention is now explained in reference to FIGS.  4 ˜ 6 . In reference to the embodiment, the circuit illustrated in FIG. 5 is explained as an example of the  0 level setting circuit mentioned earlier. A 0-level setting circuit  220  comprises an enhancement-type PMOS transistor TRP and an enhancement-type NMOS transistor TRN as shown in FIG. 5. It is assumed that the transistor TRP is constituted of a PMOS with a small W/L shape and a low drive force.  
         [0052]    the 0-level setting circuit  220  engages in operation prior to the sense amplifier operation during a read-out to drive the bit line potential to 0 V when the potential at bit line BL1 is currently set to  
         [0053]    A constant voltage should be supplied to a terminal SA as a reference potential Vref.  
         [0054]    [0054]FIG. 2 presents a timing chart of the read-out and the rewrite. In the initial state, all the terminals are set at 0 V. First, an equalize signal EQ is raised at a time point t 0  to charge the bit line BLl so as to set the bit line BL1 to 0 V.  
         [0055]    After lowering the level of the equalize signal EQ at a time point t 1 , the level at a word line WL 1  is raised to connect a memory cell Cm to the bit line BL 1 .  
         [0056]    At a time point t 2 , a source potential Vcc is applied to a plate line PL and the information in the memory cell Cm is read-out to the bit line BL 1 . The level of the potential generated at the bit line BL 1  at this point varies depending upon the polarization state of the memory cell Cm. It is assumed that the memory cell Cm is capable of holding information indicating “1” with a residual dielectric polarization P 1  and holding information indicating “0” with a residual dielectric polarization P 10 , as shown in FIG. 3. When information has been written, the memory cell Cm must have either the residual dielectric polarization P 1  or the residual dielectric polarization P 0 .  
         [0057]    When the memory cell Cm has the residual dielectric polarization P 1 , a read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and a bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 1  generated at the two ends of the bit line capacitor Cb, i.e., at the bit line BL 1 . Likewise, when the memory cell Cm has the residual dielectric polarization P 0 , the read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and a bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 0  generated at the bit line BL 1 .  
         [0058]    The level at a terminal A is raised at a time point t 3  to drive the 0-level setting circuit  220 . The 0-level setting circuit  220  has a function of setting only the information indicating “0”, i.e., the bit line voltage V0 induced by the residual dielectric polarization P0, to 0V.  
         [0059]    Now, the operation of the 0-level setting circuit  220  is explained.  
         [0060]    The threshold voltage Vr0 of the 0-level setting circuit  220  is set at; threshold voltage Vr0=source potential Vcc-|threshold voltage Vtp|in correspondence to the threshold voltage Vtp at the transistor TRP as shown in FIG. 6. If a voltage higher than the threshold voltage Vr 0  is applied to the gate of the transistor TRP, the connection between the source and the drain is electrically open, the potential at the gate of the transistor TRN is held at a low level, the connection between the source and the drain of the transistor TRN is electrically open and the bit line BL 1  is caused to float.  
         [0061]    If a voltage lower than the threshold voltage Vr 0  is applied to the gate of the transistor TRP, the connection between the source and the drain is electrically shorted, the potential at the terminal A is applied to the gate of the transistor TRN, the connection between the source and the drain of the transistor TRN is electrically shorted and the bit line BL 1  is grounded.  
         [0062]    The threshold voltage Vr 0  is set by ensuring that; bit line voltage V 0 &lt;threshold voltage Vr 0 &lt;bit line voltage V 1 . It is known that, as presented as an example in FIG. 4, the characteristics (capacity) on the side on which the polarization is inverted tend to change readily whereas the characteristics (capacity) on the polarization non-inversion side are relatively stable when the ferroelectricity characteristics become degraded due to fatigue or the like. Thus, it is desirable to set the threshold voltage Vr 0  toward the side on which the polarization is not inverted during a read-out, i.e., closer to the low potential side (toward the bit line voltage V 0 ) of the voltage generated at the bit line BL 1 , to ensure stable operation.  
         [0063]    The operation of the 0-level setting circuit  220  is performed as described below.  
         [0064]    If the potential generated at the bit line BL 1  is equal to or lower than the threshold voltage Vr 0  (“ 0 ” state), the bit line BL 1  is grounded.  
         [0065]    If the potential generated at the bit line BL 1  is higher than the threshold voltage Vr 0  (“1” state), the bit line BL 1  is floated to sustain the potential.  
         [0066]    At a time point t 4 , the level at the terminal SA is raised to amplify the information at the bit line BL 1  with the sense amplifier  110 , i.e., to amplify the “1” state to the source potential Vcc and amplify the “ 0 ” state to  0  V. It is assumed that a given constant voltage is supplied to the sense amplifier  110  as the reference potential Vref at this point. Since of the potential at the bit line BL 1  is set to 0 V in advance by the 0-level setting circuit if information indicating “ 0 ” is present at the bit line BL 1 , the reference potential Vref needs only to be at a level which corresponds to the detection sensitivity of the sense amplifier  110 . For instance, if the detection sensitivity of the sense amplifier 110 is 300 mV, the reference potential Vref may be set to Vref&gt; 300  mV.  
         [0067]    In addition, since the bit line voltage V 1  is generated at the bit line BL 1  if information indicating “1” is present at the bit line BL 1 , the reference potential Vref should be set to; 300 mV&lt;reference potential Vref&lt;bit line voltage V 1  but also taking into consideration the detection sensitivity of the sense amplifier  110 . As the example presented in FIG. 4 indicates, it is known that when the ferroelectricity characteristics have been degraded due to fatigue or the like, the characteristics on the side on which the polarization becomes inverted tend to change readily whereas the characteristics (capacity) on the polarization non-inversion side remain relatively stable. Thus, it is desirable to set the reference potential Vref to a low level within the setting range. The potential on the low potential side, which is sustained by the 0-level setting circuit  220  at a constant level of 0 V and does not change over time, is stable.  
         [0068]    In the polarization state shown in FIG. 3, P 1  changes to P 0 ′ and then to P 0  if the “1” state has been written in the memory cell Cm, whereas P 0  changes to P 0 ′ (the “ 0 ” state is written again) if the “ 0 ” state has been written in the memory cell Cm.  
         [0069]    At a time point t 5 , the levels at the terminal A and the plate line PL are set to 0 V. In the polarization state shown in FIG. 3, P 0  changes to P 1 ′ and the “1” state is written again if the “1” state has been written in the memory cell Cm, whereas P 0 ′ changes to P 0  if the “0” state has been written in the memory cell Cm.  
         [0070]    At a time point t 6 , the bit line BL 1  is caused to float by setting the level at the terminal SA to 0 V. In the polarization state shown in FIG. 3, P 1 ′ changes to P 1  if the “1” state has been written in the memory cell Cm, whereas P 0  is held if the “0” state has been written in the memory cell Cm, thus the rewrite of either data ends.  
         [0071]    At a time point t 7 , the level of the equalize signal EQ is raised to set the bit line BL 1  to 0V.  
         [0072]    At a time point t 8 , the level of the equalize signal EQ is lowered to float the bit line BL 1 , and then the level at the word line WL 1  is lowered at a time point t 9  to complete the read-out/rewrite operation.  
         [0073]    As explained in detail above, in the embodiment provided with the 0-level setting circuit  220  constituted of only two transistors, as shown in FIG. 5, the device area is minimized. In addition, since a constant potential can be utilized as the reference potential, a higher degree of stability is achieved and only a lesser degree of change occurs over time compared to the method in which the reference potential is generated by a dedicated capacitor, as explained as the prior art. Furthermore, since a constant potential Vref is supplied as the reference potential, the reference potential line does not require a particularly large capacity. As a result, a reduction in the power consumption is realized.  
         [0074]    (Third Embodiment)  
         [0075]    The third embodiment of the present invention is now explained in reference to FIGS. 7 and 8. In reference to the embodiment, the circuit illustrated in FIG. 7 is explained as an example of the 0-level setting circuit mentioned earlier. A 0-level setting circuit  320  comprises an enhancement-type PMOS transistor TRP and an enhancement-type NMOS transistor TRN as shown in FIG. 7. It is assumed that the transistor TRP is constituted of a PMOS with a small W/L shape and a low drive force. In addition, the substrate potential at the transistor TRP can be extracted through a terminal B for control.  
         [0076]    the 0-level setting circuit  320  engages in operation prior to the sense amplifier operation during a read-out to drive the bit line potential to a voltage Vbb which has been arbitrarily set when the potential at the bit line BL 1  is currently set to “0”.  
         [0077]    A constant voltage should be supplied to a terminal SA as a reference potential Vref.  
         [0078]    [0078]FIG. 8 presents a timing chart of the read-out and the rewrite. In the initial state, all the terminals are set at 0 V. First, an equalize signal EQ is raised at a time point t 0  to charge the bit line BL 1  so as to set the bit line BL 1  to 0 V.  
         [0079]    After lowering the level of the equalize signal EQ at a time point t 1 , the level at a word line WL 1  is raised to connect a memory cell Cm to the bit line BL 1 . The arbitrary voltage Vbb is applied to a terminal B.  
         [0080]    At a time point t 2 , a source potential Vcc is applied to a plate line PL and the information in the memory cell Cm is read-out to the bit line BL 1 . The level of the potential generated at the bit line BL 1  at this point varies depending upon the polarization state of the memory cell Cm. It is assumed that the memory cell Cm is capable of holding information indicating “1” with a residual dielectric polarization P 1  and holding information indicating “0” with a residual dielectric polarization P 0 , as shown in FIG. 3. When information has been written, the memory cell Cm must have either the residual dielectric polarization P 1  or the residual dielectric polarization P 0 .  
         [0081]    When the memory cell Cm has the residual dielectric polarization P 1 , a read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and a bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 1  generated at the two ends of the bit line capacitor Cb, i.e., at the bit line BL 1 . Likewise, when the memory cell Cm has the residual dielectric polarization P 0 , the read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and the bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 0  generated at the bit line BL 1 .  
         [0082]    The level at a terminal A is raised at a time point t 3  to drive the 0-level setting circuit  320 . The 0-level setting circuit  320  has a function of setting only the information indicating “0”, i.e., the bit line voltage V 0  induced by the residual dielectric polarization P 0 , to  0 V.  
         [0083]    Now, the operation of the 0-level setting circuit  320  is explained.  
         [0084]    The threshold voltage Vr 0  of the 0-level setting circuit  320  is set at; threshold voltage Vr 0 =source potential Vcc−|threshold voltage Vtp|in correspondence to the threshold voltage Vtp at the transistor TRP as shown in FIG. 6. The substrate potential Vbb at the transistor TRP can be set freely through the terminal B. Thus, the transistor TRP has a function of adjusting the threshold voltage Vr 0  by varying the threshold voltage Vtp in conformance to the voltage Vbb at the terminal B. Through this adjustment function, an adjustment of the threshold voltage (operating point) Vr 0  can be achieved in conformance to the characteristics of the ferroelectricity capacitor when the process is completed.  
         [0085]    If a voltage higher than threshold voltage Vr 0  is applied to the gate of the transistor TRP, the connection between the source and the drain is electrically open, the potential at the gate of the transistor TRN is sustained at a low level, the connection between the source and the drain of the transistor TRN is electrically open and the bit line BL 1  is caused to float. if a voltage lower than the threshold voltage Vr 0  is applied to the gate of the transistor TRP, the connection between the source and the drain is electrically shorted, the potential at the terminal A is applied to the gate of the transistor TRN, the connection between the source and the drain of the transistor TRN is electrically shorted and the bit line BL 1  is grounded.  
         [0086]    The threshold voltage Vr 0  is set by ensuring that; bit line voltage V 0 &lt;threshold voltage Vr 0 &lt;bit line voltage V 1 . It is known that, as presented as an example in FIG. 4, the characteristics (capacity) on the side on which the polarization is inverted tend to change readily whereas the characteristics (capacity) on the polarization non-inversion side are relatively stable when the ferroelectricity characteristics become degraded due to fatigue or the like. Thus, it is desirable to set the threshold voltage Vr 0  toward the side on which the polarization is not inverted during a read-out, i.e., closer to the low potential side (toward the bit line voltage V 0 ) of the voltage generated at the bit line BL 1 , to ensure stable operation.  
         [0087]    The operation of the 0-level setting circuit  320  is performed as described below.  
         [0088]    If the potential generated at the bit line BL 1  is equal to or lower than the threshold voltage Vr 0  (“0” state), the bit line BL 1  is grounded.  
         [0089]    If the potential generated at the bit line BL 1  is higher than the threshold voltage Vr 0  (“1” state), the bit line BL  1  is floated to sustain the potential.  
         [0090]    At a time point t 4 , the level at the terminal SA is raised to amplify the information at the bit line BL 1  with the sense amplifier  110 , i.e., to amplify the “1” state to the source potential Vcc and amplify the “0” state to  0  V. It is assumed that a given constant voltage is supplied to the sense amplifier  110  as the reference potential Vref at this point. Since the potential at the bit line BL 1  is set to  0  V in advance by the 0-level setting circuit  320  if information indicating “0” is present at the bit line BL 1 , the reference potential Vref needs only to be at a level which corresponds to the detection sensitivity of the sense amplifier  110 . For instance, if the detection sensitivity of the sense amplifier 110 is 300 mV, the reference potential Vref may be set to Vref&gt;300 mV.  
         [0091]    In addition, since the bit line voltage V 1  is generated at the bit line BL 1  if information indicating “1” is present at the bit line BL  1 , the reference potential Vref should be set to; 300 mV&lt;reference potential Vref&lt;bit line voltage V 1  by taking into consideration the detection sensitivity of the sense amplifier  110 . As the example presented in FIG. 4 indicates, it is known that when the ferroelectricity characteristics have been degraded due to fatigue or the like, the characteristics on the side on which the polarization becomes inverted tend to change readily whereas the characteristics (capacity) on the polarization non-inversion side remain relatively stable. Thus, it is desirable to set the reference potential Vref to a low level within the setting range. The potential on the low potential side, which is sustained by the 0-level setting circuit  320  at a constant level of 0 V and does not change over time, is stable.  
         [0092]    In the polarization state shown in FIG. 3, P 1  changes to P 0 ′ and then to P 0  if the “1” state has been written in the memory cell Cm, whereas P 0  changes to P 0 ′ (the “0” state is written again) if the “0” state has been written in the memory cell Cm.  
         [0093]    At a time point t 5 , the levels at the terminals A and B and the plate line PL are set to 0 V. In the polarization state shown in FIG. 3, P 0  changes to P 1 ′ and the “1” state is written again if the “1”, state has been written in the memory cell Cm, whereas P 0 ′ changes to P 0  if the “0” state has been written in the memory cell Cm.  
         [0094]    At a time point t 6 , the bit line BL 1  is caused to float by setting the level at the terminal SA to 0 V. In the polarization state shown in FIG. 3, P 1 ′ changes to P 1  if the “1” state has been written in the memory cell Cm, whereas P 0  is held if the “0” state has been written in the memory cell, thus rewrite of either data ends.  
         [0095]    At a time point t 7 , the level of the equalize signal EQ is raised to set the bit line BL1 to 0V.  
         [0096]    At a time point t 8 , the level of the equalize signal EQ is lowered to float the bit line BL 1 , and then the level at the word line WL 1  is lowered at a time point t 9  to complete the read-out/rewrite operation.  
         [0097]    As explained in detail above, the threshold voltage (operating point) of the 0-level setting circuit can be set when the process is completed in the embodiment. In addition, since the 0-level setting circuit  320  is constituted of only two transistors, as shown in FIG. 7, the device area is minimized. Furthermore, since a constant potential can be utilized as the reference potential in the embodiment, a higher degree of stability is achieved and only a lesser degree of change occurs over time compared to the method in which the reference potential is generated by a dedicated capacitor, as explained as the prior art. In addition, since a constant potential Vref is supplied as the reference potential, it is not necessary to set a special capacity for the reference potential line does not require a particularly large capacity. As a result, a reduction in the power consumption is realized.  
         [0098]    (Fourth Embodiment)  
         [0099]    The fourth embodiment of the present invention is now explained in reference to FIGS. 9 and 10. In reference to the embodiment, the circuit illustrated in FIG. 9 is explained as an example of the 0-level setting circuit mentioned earlier. A 0-level setting circuit  420  comprises an enhancement-type PMOS transistor TRP and enhancement-type NMOS transistors TRN  1  and TRN 2  as shown in FIG. 9. It is assumed that the transistor TRP is constituted of a PMOS with a small W/L shape and a low drive force. the 0-level setting circuit  420  engages in operation prior to the sense amplifier operation during a read-out to drive the bit line potential to 0 V when the potential at the bit line BL 1  is currently set to “0”.  
         [0100]    A constant voltage should be supplied to a terminal SA as a reference potential Vref.  
         [0101]    [0101]FIG. 2 presents a timing chart of the read-out and the rewrite. In the initial state, all the terminals are set at 0 V. First, an equalize signal EQ is raised at a time point t 0  to charge the bit line BL 1  so as to set the bit line BL 1  to 0 V.  
         [0102]    After lowering the level of the equalize signal EQ at a time point t 1 , the level at a word line WL 1  is raised to connect a memory cell Cm to the bit line BL 1 .  
         [0103]    At a time point t 2 , a source potential Vcc is applied to a plate line PL and the information in the memory cell Cm is read-out to the bit line BL 1 . The level of the potential generated at the bit line BL 1  at this point varies depending upon the polarization state of the memory cell Cm. It is assumed that the memory cell Cm is capable of holding information indicating “1” with a residual dielectric polarization P 1  and holding information indicating “0” with a residual dielectric polarization P 0 , as shown in FIG. 3. When information has been written, the memory cell Cm must have either the residual dielectric polarization P 1  or the residual dielectric polarization P 0 .  
         [0104]    When the memory cell Cm has the residual dielectric polarization P 1 , a read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and a bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 1  generated at the two ends of the bit line capacitor Cb, i.e., at the bit line BL 1 . Likewise, when the memory cell Cm has the residual dielectric polarization P 0 , the read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and the bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 0  generated at the bit line BL 1 .  
         [0105]    The level at a terminal A is raised at a time point t 3  to drive the 0-level setting circuit  420 . the 0-level setting circuit  420  has a function of setting only the information indicating “0”, i.e., the bit line voltage V0 induced by the residual dielectric polarization P 0 , to 0V.  
         [0106]    Now, the operation of the 0-level setting circuit  420  is explained.  
         [0107]    As shown in FIG. 10, the threshold voltage (operating point) of the 0-level setting circuit  420  is determined in correspondence to the threshold voltage Vtp of the transistor TRP and the threshold voltage Vtn of the transistor TRN  1 . A threshold voltage Vr 0  used to set the bit line voltage V0 to 0V is set to; threshold voltage Vr0=source potential Vcc−|threshold voltage Vtp|in conformance to the threshold voltage Vtp of the transistor TRP. When the bit line voltage V 1  is generated, the threshold voltage Vtn for setting the bit line in a floating state is the threshold voltage of the transistor TRN  1 , which is set to satisfy; threshold voltage Vtn≧threshold voltage Vr 0 .  
         [0108]    If a voltage higher than the threshold voltage Vr 0  is applied to the gate of the transistor TRP from the bit line BL 1 , the connection between the source and the drain of the transistor TRP is electrically opened, the potential at the gate of the transistor TRN 2  is sustained at a low level, the connection between the source and the drain of the transistor TRN 2  is electrically opened and the bit line BL 1  is caused to float.  
         [0109]    At this time, if the potential at the bit line BL 1  is higher than the threshold voltage Vtn, the connection between the source and the drain of the transistor TRNL is electrically shorted and the connection between the source and the drain of the transistor TRN  2  is electrically opened to set the potential at the gate of the transistor TRN 2 to 0 V, thereby setting the bit line BL 1  in a floating state. If the potential at the bit line BL 1  is within the range of; threshold voltage Vr0&lt;potential at the bit line BL 1 &lt;threshold voltage Vtn, the transistor TRN  1  does not function and, as a result, an operation similar to that in the second embodiment is performed.  
         [0110]    The charge stored at the transistor TRN  2  is discharged via the pn junction at the drain of the transistor TRP when the terminal A is grounded in the second embodiment. In this embodiment, the charge stored at the gate of the transistor TRN  2  can be forcibly discharged by the transistor TRN  1 . Thus, since no residual charge remains at the gate of the transistor TRN  2  even during a high-speed operation, stable operation is enabled.  
         [0111]    If a voltage lower than the threshold voltage Vr 0  is applied to the gate of the transistor TRP, the connection between the source and the drain is electrically shorted, the potential at the terminal A is applied to the gate of the transistor TRN  2 , the connection between the source and the drain of the transistor TRN  2  is electrically shorted and the bit line BL 1  is grounded.  
         [0112]    The threshold voltage Vr 0  is set by ensuring that; bit line voltage V 0 &lt;threshold voltage Vr 0 &lt;bit line voltage V 1 . It is known that, as presented as an example in FIG. 4, the characteristics (capacity) on the side on which the polarization is inverted tend to readily change whereas the characteristics (capacity) on the polarization non-inversion side are relatively stable when the ferroelectricity characteristics become degraded due to fatigue or the like. Thus, it is desirable to set the threshold voltage Vr 0  toward the side on which the polarization is not inverted during a read-out, i.e., closer to the low potential side (toward the bit line voltage VO) of the voltage generated at the bit line BL 1 , to ensure stable operation.  
         [0113]    The operation of the 0-level setting circuit  420  is performed as described below.  
         [0114]    If the potential generated at the bit line BL  1  is equal to or lower than the threshold voltage Vr 0  (“0” state), the bit line BL 1  is grounded.  
         [0115]    If the potential generated at the bit line BL 1  is higher than the threshold voltage Vr 0  (“1” state), the bit line BL 1  is floated to sustain the potential.  
         [0116]    At a time point t 4 , the level at the terminal SA is raised to amplify the information at the bit line BL 1  with the sense amplifier  110 , i.e., to amplify the “1” state to the source potential Vcc and amplify the “0” state to 0 V. It is assumed that a given constant voltage is supplied to the sense amplifier  110  as the reference potential Vref at this point. Since of the potential at the bit line BLl is set to 0 V in advance by the 0-level setting circuit  420  if information indicating “0” is present at the bit line BL 1 , the reference potential Vref needs only to be at a level which corresponds to the detection sensitivity of the sense amplifier  110 . For instance, if the detection sensitivity of the sense amplifier  110  is 300 mV, the reference potential Vref may be set to Vref&gt;300 mV.  
         [0117]    In addition, since the bit line voltage V 1  is generated at the bit line BL  1  if information indicating “1” is present at the bit line BL  1 , the reference potential Vref should be set to;  300  mV &lt;reference potential Vref&lt;bit line voltage V 1  by taking into consideration the detection sensitivity of the sense amplifier  110 . As the example presented in FIG. 4 indicates, it is known that when the ferroelectricity characteristics have been degraded due to fatigue or the like, the characteristics on the side on which the polarization becomes inverted tend to change readily whereas the characteristics (capacity) on the polarization non-inversion side remain relatively stable. Thus, it is desirable to set the reference potential Vref to a low level within the setting range. The potential on the low potential side, which is sustained by the 0-level setting circuit  420  at a constant level of 0 V and does not change over time, is stable.  
         [0118]    In the polarization state shown in FIG. 3, P 1  changes to P 0 ′ and then to P 0  if the “1” state has been written in the memory cell Cm, whereas P 0  changes to P 0 ′ (the “0” state is written again) if the “0” state has been written in the memory cell Cm.  
         [0119]    At a time point t 5 , the levels at the terminal A and the plate line PL are set to 0 V. In the polarization state shown in FIG. 3, P 0  changes to P 1 ′ and the “1” state is written again if the “1” state has been written in the memory cell Cm, whereas P 0 ′ changes to P 0  if the “0” state has been written in the memory cell Cm.  
         [0120]    At a time point t 6 , the bit line BL 1  is caused to float by setting the level at the terminal SA to 0 V. In the polarization state shown in FIG. 3, P 1 ′ changes to P 1  if the “1” state has been written in the memory cell Cm, whereas P 0  is held if the “0” state has been written in the memory cell Cm, thereby ending rewrite of either data.  
         [0121]    At a time point t 7 , the level of the equalize signal EQ is raised to set the bit line BL 1  to 0V.  
         [0122]    At a time point t 8 , the level of the equalize signal EQ is lowered to float the bit line BL 1 , and then the level at the word line WL 1  is lowered at a time point t 9  to complete the read-out/rewrite operation.  
         [0123]    As explained in detail above, a high degree of stability is achieved even during a high-speed operation in the embodiment since the charge stored at the gate of the transistor TRN 2  can be extracted through the transistor TRN 1 . In addition, since a constant potential can be utilized as the reference potential, a higher degree of stability is achieved and only a lesser degree of change occurs over time compared to the method in which the reference potential is generated by a dedicated capacitor, as explained as the prior art. Furthermore, since a constant potential Vref is supplied as the reference potential, the reference potential line does not require a particularly large capacity. As a result, a reduction in the power consumption is realized.  
         [0124]    (Fifth Embodiment)  
         [0125]    The fifth embodiment of the present invention is now explained in reference to FIG. 11. In reference to the embodiment, the circuit illustrated in FIG. 11 is explained as an example of the 0-level setting circuit mentioned earlier. A 0-level setting circuit  520  comprises an enhancement-type PMOS transistor TRP and enhancement-type NMOS transistors TRN  1  and TRN  2  as shown in FIG. 11. It is assumed that the transistor TRP is constituted of a PMOS with a small W/L shape and a low drive force. In addition, the substrate potential at the transistor TRP can be extracted through a terminal B for control.  
         [0126]    the 0-level setting circuit  520  engages in operation prior to the sense amplifier operation during a read-out to drive the bit line potential to a voltage Vbb which has been arbitrarily set when the potential at a bit line BALANCE I is currently set to “0”.  
         [0127]    A constant voltage should be supplied to a terminal SA as a reference potential Vref.  
         [0128]    [0128]FIG. 8 presents a timing chart of the read-out and the rewrite. In the initial state, all the terminals are set at 0 V. First, an equalize signal EQ is raised at a time point t 0  to charge the bit line BL 1  so as to set the bit line BL 1  to 0 V.  
         [0129]    After lowering the level of the equalize signal EQ at a time point t 1 , the level at a word line WL 1  is raised to connect a memory cell Cm to the bit line BL 1 . The arbitrary voltage Vbb is applied to the terminal B.  
         [0130]    At a time point t 2 , a source potential Vcc is applied to a plate line PL and the information in the memory cell Cm is read-out to the bit line BL 1 . The level of the potential generated at the bit line BL 1  at this point varies depending upon the polarization state of the memory cell Cm. It is assumed that the memory cell Cm is capable of holding information indicating “1” with a residual dielectric polarization P 1  and holding information indicating “0” with a residual dielectric polarization P 0 . When information has been written, the memory cell Cm must have either the residual dielectric polarization P 1  or the residual dielectric polarization P 0 .  
         [0131]    When the memory cell Cm has the residual dielectric polarization P 1 , a read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and a bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 1  generated at the two ends of the bit line capacitor Cb, i.e., at the bit line BL 1 . Likewise, when the memory cell Cm has the residual dielectric polarization P 0 , the read-out voltage Vr is divided at the serial circuit constituted of the memory cell Cm and the bit line capacitor Cb by applying the read-out voltage Vr to the plate line PL, resulting in a bit line voltage V 0  generated at the bit line BL 1 .  
         [0132]    The level at a terminal A is raised at a time point t 3  to drive the 0-level setting circuit  520 . The 0-level setting circuit  520  has a function of setting only the information indicating “0”, i.e., the bit line voltage V0 induced by the residual dielectric polarization P0, to 0V.  
         [0133]    Now, the operation of the 0-level setting circuit  520  is explained.  
         [0134]    As shown in FIG. 10, the threshold voltage (operating point) of the 0-level setting circuit  520  is determined in correspondence to the threshold voltage Vtp of the transistor TRP and the threshold voltage Vtn of the transistor TRN  1 . A threshold voltage Vr 0  used to set the bit line voltage V0 to 0V is set to; threshold voltage Vr0=source potential Vcc|threshold voltage Vtp|in conformance to the threshold voltage Vtp of the transistor TRP. When the bit line voltage V 1  is generated, the threshold voltage Vtn for setting the bit line in a floating state is the threshold voltage of the transistor TRN  1 , which is set to satisfy; threshold voltage Vtn≧threshold voltage Vr 0 .  
         [0135]    The substrate potential Vbb at the transistor TRP can be set freely through the terminal B. Thus, the transistor TRP has a function of adjusting the threshold voltage Vr 0  by varying the threshold voltage Vtp in conformance to the voltage Vbb at the terminal B. Through this adjustment function, an adjustment of the threshold voltage Vr 0  can be achieved in conformance to the characteristics of the ferroelectricity capacitor when the process is completed.  
         [0136]    If a voltage higher than the threshold voltage Vr 0  is applied to the gate of the transistor TRP from the bit line BL 1 , the connection between the source and the drain of the transistor TRP is electrically opened, the potential at the gate of the transistor TRN 2  is sustained at a low level, the connection between the source and the drain of the transistor TRN 2  is electrically opened and the bit line BL 1  is caused to float.  
         [0137]    At this time, if the potential at the bit line BL 1  is higher than the threshold voltage Vtn, the connection between the source and the drain of the transistor TRN  1  is electrically shorted and the connection between the source and the drain of the transistor TRN  2  is electrically opened to set the potential at the gate of the transistor TRN  2  to 0 V, thereby setting the bit line BL 1  in a floating state.  
         [0138]    If the potential at the bit line BL 1  is within the range of; threshold voltage Vr 0 &lt; potential at bit line BL 1 &lt; threshold voltage Vtn, the transistor TRN  1  does not function and, as a result, an operation similar to that in the third embodiment is performed.  
         [0139]    The charge stored at the gate of the transistor TRN  2  is discharged via the pn junction at the drain of the transistor TRP when the terminal B is grounded in the third embodiment. In this embodiment, the charge stored at the gate of the transistor TRN  2  can be forcibly discharged by the transistor TRN  1 . Thus, since no residual charge remains at the gate of the transistor TRN  2  even during a high-speed operation, stable operation is enabled.  
         [0140]    If a voltage lower than the threshold voltage Vr 0  is applied to the gate of the transistor TRP, the connection between the source and the drain is electrically shorted, the potential at the terminal A is applied to the gate of the transistor TRN  2  , the connection between the source and the drain of the transistor TRN  2  is electrically shorted and the bit line BL 1  is grounded.  
         [0141]    The threshold voltage Vr 0  is set by ensuring that; bit line voltage V 0 &lt;threshold voltage Vr 0 &lt;bit line voltage V 1 . It is known that, as presented as an example in FIG. 4, the characteristics (capacity) on the side on which the polarization is inverted tend to change readily whereas the characteristics (capacity) on the polarization non-inversion side are relatively stable when the ferroelectricity characteristics become degraded due to fatigue or the like. Thus, it is desirable to set the threshold voltage Vr 0  toward the side on which the polarization is not inverted during a read-out, i.e., closer to the low potential side (toward the bit line voltage VO) of the voltage generated at the bit line BL 1 , to ensure stable operation.  
         [0142]    The operation of the 0-level setting circuit  520  is performed as described below.  
         [0143]    If the potential generated at the bit line BL 1  is equal to or lower than the threshold voltage Vr 0  (“0” state), the bit line BL 1  is grounded.  
         [0144]    If the potential generated at the bit line BL 1  is higher than the threshold voltage Vr 0  (“1” state), the bit line BL 1  is floated to sustain the potential.  
         [0145]    At a time point t 4 , the level at the terminal SA is raised to amplify the information at the bit line BL 1  with the sense amplifier  110 , i.e., to amplify the “1” state to the source potential Vcc and amplify the “0” state to  0  V. It is assumed that a given constant voltage is supplied to the sense amplifier  110  as the reference potential Vref at this point. Since the potential at the bit line BL 1  is set to  0  V in advance by the 0-level setting circuit  520  if information indicating “0” is present at the bit line BL 1 , the reference potential Vref needs only to be at a level which corresponds to the detection sensitivity of the sense amplifier  110 . For instance, if the detection sensitivity of the sense amplifier  110  is 300 mV, the reference potential Vref may be set to Vref&gt; 300  mV.  
         [0146]    In addition, since the bit line voltage V 1  is generated at the bit line BL  1  if information indicating “1” is present at the bit line BL  1 , the reference potential Vref should be set to; 300 mV&lt;reference potential Vref&lt;bit line voltage V 1  by taking into consideration the detection sensitivity of the sense amplifier  110 . As the example presented in FIG. 4 indicates, it is known that when the ferroelectricity characteristics have been degraded due to fatigue or the like, the characteristics on the side on which the polarization becomes inverted tend to change readily whereas the characteristics (capacity) on the polarization non-inversion side remain relatively stable. Thus, it is desirable to set the reference potential Vref to a low level within the setting range. The potential on the low potential side, which is sustained by the 0-level setting circuit  520  at a constant level of 0 V and does not change over time, is stable.  
         [0147]    In the polarization state shown in FIG. 3, P 1  changes to P 0 ′ and then to P 0  if the “1” state has been written in the memory cell Cm, whereas P 0  changes to P 0 ′ (the “0” state is written again) if the “0” state has been written in the memory cell Cm.  
         [0148]    At a time point t 5 , the levels at the terminals A and B and the plate line PL are set to 0 V. In the polarization state shown in FIG. 3, P 0 ′ changes to P 0  and the “1” state is written again if the “1” state has been written in the memory cell Cm.  
         [0149]    At a time point t 6 , the bit line BL 1  is caused to float by setting the level at the terminal SA to 0 V. In the polarization state shown in FIG. 3, P 1 ′ changes to P 1  if the “1” state has been written in the memory cell Cm, whereas P 0  is held if the “0” state has been written in the memory cell Cm, thereby ending rewrite of either data.  
         [0150]    At a time point t 7 , the level of the equalize signal EQ is raised to set the bit line BL1 to 0V.  
         [0151]    At a time point t 8 , the level of the equalize signal EQ is lowered to set the bit line BL 1  in a floating state, and then the level at the word line WL 1  is lowered at a time point t 9  to complete the read-out/rewrite operation.  
         [0152]    As explained in detail above, a high degree of stability is achieved even during a high-speed operation in the embodiment since the charge stored at the gate of the transistor TRN 2  can be extracted through the transistor TRN 1 . It is also possible to set the threshold voltage (operating point) of the 0-level setting circuit  520  after the process is completed. In addition, since a constant potential can be utilized as the reference potential, a higher degree of stability is achieved and only a lesser degree of change occurs over time compared to the method in which the reference potential is generated by a dedicated capacitor, as explained as the prior art. Furthermore, since a constant potential Vref is supplied as the reference potential, the reference potential line does not require a particularly large capacity. As a result, a reduction in the power consumption is realized.  
         [0153]    While the invention has been particularly shown and described with respect to preferred embodiments of the read-out circuit according to the present invention by referring to the attached drawings, the present invention is not limited to these examples and it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit, scope and teaching of the invention.  
         [0154]    As explained in detail in reference to the embodiments, by adopting the 0-level setting circuit according to the present invention in a 1T-1C FRAM device, a highly reliable ferroelectricity memory capable of performing stable read-out is realized.  
         [0155]    As is obvious from the detailed explanation of the operation of the 0-level setting circuit according to the present invention, the  0 level setting circuit according to the present invention may also be adopted in a 2T-2C type FRAM device.  
         [0156]    As is obvious from the detailed explanation of the operation achieved in the 0-level setting circuit according to the present invention, the 0-level setting circuit according to the present invention may also be adopted in another type of memory device having a system for detecting a potential difference manifesting at a bit line.  
         [0157]    As explained above, according to the present invention in which a constant potential can be used as a reference potential, a higher degree of stability is achieved and a lesser degree of change occurs over time compared to the method in which the reference potential is generated by a dedicated capacitor as explained as the prior art. In addition, since a constant potential Vref can be supplied as the reference potential, it is not necessary to set a particular capacity for the reference potential line, thereby achieving a reduction in power consumption.  
         [0158]    Since the present invention does not require numerous additional elements, the device area is minimized, thereby preventing the problem of an increase in the area.  
         [0159]    Furthermore, since the operating point of the potential setting circuit can be set after the process is completed, the operating point of the potential setting circuit can be set freely in conformance to the requirements of a specific use.  
         [0160]    Moreover, a high degree of stability is achieved even during a high-speed operation.