Abstract:
An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM&#39;s array reads out the full N bits simultaneously, the array&#39;s address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array&#39;s address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is a continuation of U.S. application Ser. No. 10/274,773, filed Oct. 21, 2002, pending, which is a continuation of U.S. application Ser. No. 09/642,355, filed Aug. 21, 2000, now U.S. Pat. No. 6,469,954, issued Oct. 22, 2002, which application is related to co-pending U.S. patent application Ser. No. 09/146,472, filed Sep. 3, 1998, now U.S. Pat. No. 6,219,283, issued Apr. 17, 2001 and co-pending U.S. patent application Ser. No. 09/034,203, filed Mar. 3, 1998, now U.S. Pat. No. 5,978,3 11, issued Nov. 2, 1999. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    This invention relates in general to semiconductor memory devices and, more specifically, to devices and methods for reducing idle cycles in semiconductor memory devices, such as synchronous Static Random Access Memory (SRAM) devices.  
           [0004]    2. State of the Art  
           [0005]    Modern synchronous SRAM devices are typically burst-oriented, which means that they perform read or write operations on a sequence of internal addresses in response to receiving a single, externally supplied address. Thus, for example, in a modern 64K×32 SRAM device with a burst length of four, a single, externally-generated address supplied to the device during a read operation causes the device to sequentially output four, 32-bit wide data words. Similarly, a single, externally-generated address supplied to the device during a write operation causes the device to sequentially write in four, 32-bit wide data words. Because internal addresses can be generated within burst-oriented SRAM devices much faster than external addresses can be latched into such devices, read and write operations occur more rapidly in burst-oriented SRAM devices than in older, non-burst-oriented SRAM devices.  
           [0006]    Despite the speed boost provided by burst operations, read operations in modern burst-oriented SRAM devices are not as fast as is desirable. For example, as shown in FIG. 1, sequential read operations  10  and  12  (only a portion of read operation  12  is shown in FIG. 1) in a conventional burst-oriented SRAM (not shown) are separated by an idle cycle  14 , which adds to the total time it takes to perform the read operations  10  and  12 .  
           [0007]    More specifically, the first read operation  10  is initiated at time t 0  when the address register signal ADSC* is activated, causing the first address A0 to be registered into the SRAM. The registered address A0 is then presented to the memory array (not shown) of the SRAM at time t 1 , and the data D0 specified by the address A0 is output from the array at time t 2  and from the SRAM at time t 3 . Next, an internally-generated burst address A0+1 is presented to the memory array at time t 4 , causing the array to output the data D0+1 specified by the address A0+1 at the same time. The data D0+1 is then output from the SRAM at time t 5 . Thereafter, internally-generated burst addresses A0+2 and A0+3, respectively, are presented to the memory array at times t 6  and t 8 , respectively, causing the array to output the data D0+2 and D0+3 specified by the addresses A0+2 and A0+3, respectively, at the same times. The data D0+2 and D0+3 are then output from the SRAM at times t 7  and t10, respectively. Before the data D0+3 is output from the SRAM at time t 10 , the address register signal ADSC* is activated again at time t 9 , causing the second address A1 to be registered into the SRAM at the same time. The read operation  12  then proceeds in the same manner as the read operation  10 .  
           [0008]    It should be noted that because the address A0+3 is still being presented to the array when the second address A1 is registered at time t 9 , the idle cycle  14  is necessary to provide sufficient recovery time from the operation performed at A0+3.  
           [0009]    Write operations in modern burst-oriented SRAM devices are also not as fast as is desirable. For example, as shown in FIG. 2, sequential write operations  20  and  22  (only a portion of write operation  22  is shown in FIG. 2) in a conventional burst-oriented SRAM (not shown) are separated by a recovery period  24 , which adds to the total time it takes to perform the write operations  20  and  22 .  
           [0010]    More specifically, the first write operation  20  is initiated at time t 0  when the address register signal ADSC* is activated, causing the first address A0 to be registered into the SRAM. The registered address A0 is then presented to the memory array (not shown) of the SRAM at time t 1 , and the first data D0 is registered into the SRAM at time t 2 . Next, the registered data D0 is written into the array at time t 3  at the location specified by the address A0, and the data D0+1 is registered into the SRAM at time t 4 . Thereafter, internally-generated burst addresses A0+1 and A0+2 are presented to the memory array at times t 5  and t 7 , respectively, the data D0+2 and D0+3 is registered into the SRAM at times t 6  and t 8 , respectively, and the data D0+1 and D0+2 is written into the array at the locations specified by the addresses A0+1 and A0+2, respectively, at times t 5  and t 7 . An internally-generated burst address A0+3 is then presented to the memory array at time t 9 , causing the data D0+3 to be written into the array at the location specified by the address A0+3 at the same time. Next, the address register signal ADSC* is activated again at time t 10 , causing the second address A 1  to be registered into the SRAM. The second write operation  22  then proceeds in the same manner as the first write operation  20  after the recovery period  24  has passed.  
           [0011]    Accordingly, because conventional synchronous SRAMs include idle cycles during read and write operations that limit the bandwidth of such SRAMs, there is a need in the art for a device and method that reduces the number of idle cycles necessary in read and write operations of semiconductor memory devices, such as sequential SRAMs, thereby further accelerating read and write operations in such devices.  
         BRIEF SUMMARY OF THE INVENTION  
         [0012]    In one embodiment of this invention, a memory operation (e.g., a read or write operation) is performed in a semiconductor memory (e.g., a synchronous, burst-oriented Static Random Access Memory (SRAM)) by selecting an N-bit wide row of the semiconductor memory. Then, a number (X) of data portions of N/X bits each are simultaneously transferred between the selected row and N-bit wide temporary storage that is in communication with the selected row.  
           [0013]    In another embodiment, N data bits are read from a semiconductor memory by first selecting a row of the semiconductor memory in accordance with an externally supplied address. N data bits stored in the selected row are then simultaneously accessed and temporarily stored (e.g., in N latched sense amplifiers). A portion of the temporarily stored N data bits are then selected in accordance with the externally supplied address and read out of the semiconductor memory. Next, one or more internal burst addresses are generated from the externally supplied address and, for each internal burst address generated, another portion of the temporarily stored N data bits is selected in accordance with the internal burst address and read out of the semiconductor memory.  
           [0014]    In still another embodiment, N data bits are written into a semiconductor memory. The N data bits are first received in a plurality of sequential portions, and one of the sequential portions of the N data bits is temporarily stored in accordance with an externally supplied address. Also, one or more internal burst addresses are generated from the externally supplied address and, for each internal burst address generated, another one of the sequential portions of the N data bits is temporarily stored in accordance with the internal burst address. A row of the semiconductor memory is then selected in accordance with the externally supplied address, and the temporarily stored sequential portions of the N data bits are simultaneously written into the selected row.  
           [0015]    In yet another embodiment of this invention, a burst-oriented SRAM having a burst length of X includes a memory array having a plurality of N-bit wide rows. Storage circuitry temporarily stores N bits, and buffer circuitry buffers X sequential data portions of N/X bits each. Multiplexing circuitry between the storage circuitry and the buffer circuitry sequentially transfers the X sequential data portions between the storage circuitry and the buffer circuitry, and circuitry connected to the storage circuitry directs the storage circuitry to simultaneously transfer N bits between a selected N-bit wide row of the memory array and the storage circuitry.  
           [0016]    In an additional embodiment of this invention, a semiconductor memory includes a memory array and storage circuitry that temporarily stores N bits. Buffer circuitry buffers X sequential data portions of N/X bits each, and circuitry connected between the storage circuitry and the buffer circuitry sequentially transfers the X sequential data portions between the storage circuitry and the buffer circuitry. Also, circuitry connected to the storage circuitry directs the storage circuitry to simultaneously transfer N bits between the memory array and the storage circuitry.  
           [0017]    In further embodiments of this invention, the semiconductor memory described above is incorporated into an electronic system, such as a computer system, and is fabricated on the surface of a semiconductor substrate, such as a semiconductor wafer.  
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0018]    In the drawings, which illustrate what is currently regarded as the best mode for carrying out the invention, and in which like reference numerals refer to like parts in different views or embodiments:  
         [0019]    [0019]FIG. 1 is a timing diagram illustrating successive reads in a prior art SRAM architecture;  
         [0020]    [0020]FIG. 2 is a timing diagram illustrating successive writes in a prior art SRAM architecture;  
         [0021]    [0021]FIG. 3 is a timing diagram illustrating successive reads in an SRAM architecture in accordance with this invention;  
         [0022]    [0022]FIG. 4 is a timing diagram illustrating successive writes in the SRAM architecture of FIG. 3;  
         [0023]    [0023]FIG. 5 is a block diagram illustrating an SRAM embodying the SRAM architecture of FIG. 3;  
         [0024]    [0024]FIG. 6 is a block diagram showing a sub-array of the SRAM of FIG. 5 in more detail;  
         [0025]    [0025]FIG. 7 is a block diagram showing an electronic system incorporating the SRAM of FIG. 5; and  
         [0026]    [0026]FIG. 8 is a diagram illustrating a semiconductor wafer having the SRAM of FIG. 5 fabricated on its surface. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]    The terms “bit,” “signal,” “line,” “signal line,” “terminal” and “node” are used interchangeably herein and each refers to a physical conductive circuit trace upon which an electrical signal, in the form of a voltage potential, which may vary with time, may be measured. The terms “multiplexer” and “MUX” are used interchangeably herein to indicate an electrical device that connects one of a plurality of data inputs to its output terminal, based on one or more input signals. Furthermore, each input to, and the output from, a multiplexer may include a plurality of signal lines.  
         [0028]    As shown in FIGS. 3 and 5, sequential read operations  30  and  32  in a synchronous SRAM  50  constructed in accordance with an SRAM architecture of this invention occur without interruption by idle cycles, in contrast to the conventional architecture described above. It will be understood by those having skill in the technical field of this invention that the invention is applicable not only to SRAM devices, but also to other semiconductor memory devices.  
         [0029]    More specifically, the read operation  30  is initiated at time t 0  when the address register signal ADSC* is activated, causing an address register  52  of the SRAM  50  to register the first address A0. The registered address A0 is then presented to a memory array  54  and burst control logic  56  of the SRAM  50  at time t 1 . Subsequently, at time t 2  the memory array  54  senses the data D0 specified by the address A0 simultaneously with the data D0+1, D0+2, and D0+3. At the same time, the array  54  loads the data D0 onto a global data line GDL (described in more detail below with respect to FIG. 6), and at time t 3  the SRAM  50  reads out the data D0. At time t 4 , the array  54  loads the already sensed data D0+1 onto the global data line GDL in accordance with an internally-generated burst address A0+1 presented to the SRAM  50 , causing the array  54  to read out the data D0+1 at time t 5 . Similarly, at time t 6 , the array  54  loads the already sensed data D0+2 onto the global data line GDL in accordance with an internally-generated burst address A0+2 presented to the array  54 , causing the SRAM  50  to read out the data D0+2 at time t 8 .  
         [0030]    Before the array  54  reads out the data D0+2, the read operation  32  is initiated at time t 7  when the address register signal ADSC* is again activated, causing the address register  52  to register the second address A1. Subsequently, the registered address A1 is presented to the array  54  and burst control logic  56  at time t 9 . At time t 10 , the array  54  loads the already sensed data D0+3 onto the global data line GDL in accordance with an internally-generated burst address A0+3 presented to the array  54 , causing the array  54  to read out the data D0+3 at time t 11 . The read operation  32  then proceeds in the same manner as the read operation  30 .  
         [0031]    It should be noted that because the data D0, D0+1, D0+2, and D0+3 are sensed from the array  54  simultaneously at time t 2 , the array address lines ArrayAdd[2:14] are free at time t 9  to present the subsequent address A1. As a result, the array  54  can immediately begin reading out the data D1, etc. after the data D0+3 is read out. This will be explained in more detail below with respect to FIG. 6.  
         [0032]    As shown in FIGS. 4 and 5, sequential write operations  40  and  42  in the synchronous SRAM  50  occur without interruption by idle cycles, in contrast to the conventional architecture described above.  
         [0033]    More specifically, the write operation  40  is initiated at time t 0  when the address register signal ADSC* is activated, causing the address register  52  of the SRAM  50  to register the first address A0. Next, at times t 1 , t 2 , t 3 , and t 4 , respectively, the data D0, D0+1, D0+2, and D0+3 is received by the SRAM  50  and latched into the array  54  in accordance with the two least significant bits (referred to as MuxAdd(0:1)) of the registered address A0 and burst-generated addresses A0+1, A0+2, and A0+3, respectively. Using only the two least significant bits of the registered address is by way of example only. It is within the scope of this invention to use two or more of the least significant bits of the registered address. This will be explained in more detail below with respect to FIG. 6.  
         [0034]    At time t 5 , the write operation  42  is initiated when the address register signal ADSC* is activated again, causing the address register  52  of the SRAM  50  to register the second address A1. Then, at time t 6 , the first address A0 is latched into the array  54 , causing the previously latched-in data D0, D0+1, D0+2, and D0+3 to be written into the array  54  simultaneously. The remainder of the write operation  42  then continues in the same manner as the write operation  40 .  
         [0035]    As shown in FIG. 5, the SRAM  50  includes a 16-bit address bus  58  that provides synchronous addresses (A0-15) to the address register  52 . The two least significant bits of the registered synchronous array address, ArrayAdd&lt;0:1&gt;, are directed toward the burst control logic  56 , while the fourteen most significant bits, ArrayAdd&lt;2:15&gt;, are directed toward the memory array  54 . The burst control logic  56  takes the two least significant bits of the registered synchronous address, ArrayAdd&lt;0:1&gt;, and generates additional signals, MuxAdd&lt;0:1&gt;, MuxAddEven&lt;0:1&gt;, MuxAddOdd&lt;0:1&gt; and WBA&lt;0:3&gt; for generating two-bit burst addresses during burst read and burst write cycles. The invention is not limited to generating two-bit burst addresses. Using only the two least significant bits of the registered address is by way of example only. It is within the scope of this invention to use two or more of the least significant bits of the registered address.  
         [0036]    Write controller  60  generates Sense and Write signals during read and write operations, respectively, for the memory array  54 . The write controller  60  also enables input buffers (not shown) within data I/O  66  to place input data on a 32-bit internal I/O data bus  64  in response to a global write signal GW* being active.  
         [0037]    When the global write signal GW* is inactive, a read operation takes place, in which case the inactive global write signal GW* causes data output enable circuitry  65  to enable output buffers (not shown) in data I/O  66  for outputting a 32-bit wide data word from the 32-bit external I/O data bus  68  to the 32-bit internal I/O data bus  64 .  
         [0038]    The memory array  54  includes thirty-two memory sub-array blocks  130 , each of size 64K×1. FIG. 6, details a single, memory sub-array block  130  and I/O logic  118 . Each memory sub-array block  130  includes a sub-array  70 , four column pass circuits  76 ,  78 ,  80  and  82 , four latching sense amplifiers  86 ,  88 ,  90  and  92 , four latched write drivers  108 ,  110 ,  112  and  114 , three 1of 2 multiplexers  94 ,  96  and  98 , and address circuitry block  72 . I/O logic  118  includes an I/O logic with output pad  120  and two tristateable data-in logic blocks  104  and  106 . This invention is not limited to the use of latching sense amplifiers. One could replace a latching sense amplifier with a sense amplifier and a register and still be within the scope of the invention.  
         [0039]    The memory sub-array block  130  receives array addresses, ArrayAdd&lt;2:15&gt;, generated by address register  52  from registered sequential address bits A&lt;2:15&gt;. Each memory cell in the sub-array  70  is accessed by a particular row and column in the sub-array  70 . The ten most significant registered address bits, ArrayAdd&lt;6:15&gt;, from address register  52 , form row address bits going directly into sub-array  70 . The four other registered address bits go into address circuitry  72 . The address circuitry  72  may comprise, for example, pre-decoding logic. The address circuitry  72  generates signals Block Select and CP&lt;0:2&gt;. Signals CP&lt;0:2&gt; are all coupled to each column pass circuit  76 ,  78 ,  80  and  82 . Each column pass circuit  76 ,  78 ,  80  and  82  multiplexes 1 of 8 column lines from the sub-array  70  to internal nodes ArrayData — 0, ArrayData — 2, ArrayData — 1 and ArrayData — 3, respectively, based on CP&lt;0:2&gt;. Node ArrayData — 0 is coupled to the input of latching sense amplifier  86  and is also coupled to the output of latched write driver  108 . Similarly, ArrayData — 2 is coupled to the input of latching sense amplifier  88  and is also coupled to the output of latched write driver  110 ; ArrayData — 1 is coupled to the input of latching sense amplifier  90  and is also coupled to the output of latched write driver  112 ; and ArrayData — 3 is coupled to the input of latching sense amplifier  92  and is also coupled to the output of latched write driver  114 .  
         [0040]    Signal lines Sense, Write and Block Select are all coupled to the latching sense amplifiers  86 ,  88 ,  90  and  92  and to the latched write drivers  108 ,  110 ,  112  and  114 . Output nodes GDL — 0 and GDL — 2, from latching sense amplifiers  86  and  88 , respectively, are coupled to the inputs of 1 of 2 MUX  94 . Similarly, output nodes GDL — 1 and GDL — 3, of latching sense amplifiers  90  and  92 , respectively, are coupled to inputs of 1 of 2 MUX  96 . Nodes GDL_Even and GDL_Odd, are coupled to the output terminals of multiplexers  94  and  96 , respectively, and the inputs of 1 of 2 MUX  98 . Nodes GDL_Even and GDL_Odd, are also coupled to outputs of tristateable data-in logic  104  and  106 . The output, GDL, of 1 of 2 MUX  96  is coupled to the input of I/O logic with output pad  120 . An output of I/O logic with output pad  120  is coupled to node DataIn, which is also coupled to inputs on tristateable data-in logic  104  and  106 .  
         [0041]    Referring to FIG. 5, burst control logic  56  receives the two least significant registered address bits ArrayAdd&lt;0:1&gt; registered by address register  52 . The burst control logic  56  latches in the registered address bits, ArrayAdd&lt;0:1&gt;, generates look ahead addresses even when the address register  52  (FIG. 5) is receiving and registering the next address (e.g., A1) in sequence. As a result, the memory array  54  can continue working in accordance with a previous address (e.g., A0) while the next address in sequence (e.g., A1) is being registered.  
         [0042]    A read operation will now be described in detail with reference to FIG. 5 and a single sub-array  70 , FIG. 6, of which there are thirty-two such sub-arrays  70  on the exemplary memory device die. In a read operation, the latched-in array address, ArrayAdd&lt;2:15&gt; causes the sub-array  70  to output all thirty-two bits of a row selected in accordance with the array address, ArrayAdd&lt;2:15&gt;, to column pass circuits  76 ,  78 ,  80  and  82 . Each column pass circuit  76 ,  78 ,  80  and  82  passes one of the eight input data bits to nodes ArrayData — 0, ArrayData — 2, ArrayData — 1 and ArrayData — 3, respectively, in accordance with control signals CP&lt;0:2&gt;. All four data bits are latched in latching sense amplifiers  86 ,  88 ,  90  and  92 , in response to an active Sense signal from the write controller  60  (FIG. 5). Simultaneously, of course, thirty-one other sub-arrays (not shown) each latch four data bits in analogous latching sense amplifiers.  
         [0043]    Once latched into the sense amplifiers  86 ,  88 ,  90 , and  92 , the four latched bits are sequentially selected and output from the sense amplifiers  86 ,  88 ,  90 , and  92 , through multiplexers  94 ,  96 , and  98 , and onto one of thirty-two global data lines, GDL, in accordance with signals MuxAdd(0), MuxAddEven(1), and MuxAddOdd(1) generated by the burst control logic  56  (FIG. 5), as discussed above. All thirty-two of the global data lines, GDL, (only one of which is shown in FIG. 6) are then sent to an I/O logic with output pad  12  and placed on the 32-bit wide I/O data bus  68  as DQ0-31 (FIG. 5) in accordance with a Output Enable signal generated by data output enable circuitry  65  (FIG. 5).  
         [0044]    In a write operation, 32-bit wide data words, DQ0-31, are sequentially received by data I/O  66  from I/O data bus  68  and presented on DataIn nodes, one of which is shown in FIG. 6, and passed to tristateable data-in logic blocks  104  and  106  in accordance with MuxAdd(0). Tristateable data-in logic blocks  104  and  106  then output the received data bit on node GDL_Even to inputs of write drivers  108  and  110 , and node GDL_Odd to inputs of write drivers  112  and  114 . At the same time, burst control logic  56  (FIG. 5) generates write burst address bits, WBA&lt;0:3&gt;, which controls which of the write drivers  108 ,  110 ,  112 , and  114  latch in the data bit in each cycle. Once all of the write drivers  108 ,  110 ,  112 , and  114  have latched in a bit, a Write signal from the write controller  60  (FIG. 5) causes all the write drivers  108 ,  110 ,  112 , and  114  to simultaneously write their respective latched bits into the row of the sub-array  70  specified by ArrayAdd&lt;2:15&gt;.  
         [0045]    Of course, it will be understood that the present invention is applicable to memory arrays of any type and size and, specifically, is not limited to 64K×32 arrays and 64K×1 sub-arrays. It will also be understood that this invention may easily be extended to memory arrays that incorporate a parity bit, e.g., 64K×36.  
         [0046]    As shown in FIG. 7, an electronic system  140  includes an input device  142 , an output device  144 , a processor device  146 , and a memory system  148  that incorporates the SRAM  50  of FIG. 5. It will be understood that the SRAM  50  may be incorporated into one of the input, output, and processor devices  142 ,  144 , and  146  instead of the memory system  148 .  
         [0047]    As shown in FIG. 8, the SRAM  50  of FIG. 5 is fabricated on the surface of a semiconductor wafer  150  in accordance with this invention. Of course, it should be understood that the SRAM  50  may be fabricated on semiconductor substrates other than a silicon wafer, such as a silicon-on-insulator (SOI) substrate, a silicon-on-glass (SOG) substrate, and a silicon-on-sapphire (SOS) substrate. Semiconductor materials other than silicon, such as gallium arsenide and indium phosphide may also be employed to fabricate SRAM  50 .  
         [0048]    Although this invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. For example, this invention is not limited to the use of latching sense amplifiers. One could replace a latching sense amplifier with a sense amplifier and a register and still be within the scope of the invention. This invention is limited only by the appended claims, which include within their scope all equivalent devices or methods that operate according to the principles of the invention as described.