Abstract:
In general, in one aspect, the disclosure describes dedicated, unidirectional connections between processor cores of a processor featuring heterogeneous processor cores.

Description:
BACKGROUND  
       [0001]     In the past, processors such as CPUs (central processing units) featured a single execution unit to process instructions of a program. Recently, multi-core architectures have emerged that amass multiple processor cores on a single integrated silicon die. Each of the processor cores can simultaneously execute program instructions. This parallel operation of the processor cores can improve performance of a variety of applications. For example, some network devices (e.g., switches and routers) incorporate programmable multi-core processors known as network processors. The multiple cores of the network processors enable the network devices to keep apace the large volume network traffic flowing through the device. For instance, while one core determines how to forward one network packet further toward its destination, a different core can determine how to forward another. The multiple cores can enable the network processors to achieve speeds rivaling “hard-wired” ASICs (Application Specific Integrated Circuits) while remaining programmable. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0002]      FIG. 1  depicts a heterogeneous multi-core processor having dedicated connections between cores.  
         [0003]      FIGS. 2A-2C  depict different configurations of dedicated connections between cores.  
         [0004]      FIG. 3  depicts a network processor.  
         [0005]      FIGS. 4 and 5  depict different processor cores of a network processor.  
         [0006]      FIG. 6  depicts a network device.  
     
    
     DETAILED DESCRIPTION  
       [0007]      FIG. 1  depicts a multi-core processor  106  architecture that enables processor cores  100   a - 100   c  integrated on a single semiconductor die to communicate. For example, as shown, cores  100   a ,  100   b , and  100   c  are connected by dedicated unidirectional connections  104   a ,  104   b  between the cores  100   a - 100   c . For instance, core  100   a  can send data to core  100   b  via connection  104   a . In operation, such a connection  104   a  may be used, for example, by core  100   a  to send network packet related data (e.g., a pointer to a packet payload or flow data) to core  100   b . Unlike a shared bus, a dedicated connection permits inter-core communication without contention, negotiating for bus control, and so forth.  
         [0008]     As shown, each connection  104   a ,  104   b  terminates in one or more processor core registers  102   a ,  102   b ,  102   c  that stores the transmitted data. Thus, a given processor core (e.g.,  100   b ) can access its registers (e.g.,  102   b ) to read data written by the preceding core (e.g.,  100   a ). Potentially, a given processor core (e.g.,  100   b ) can also write data into its own registers (e.g.,  102   b ).  
         [0009]     The processor cores  102   a - 102   c  may feature logic that uses the registers  102   a - 102   c  to implement a queue. For example, the logic may generate a queue FULL signal when a set of processor core registers  102   a - 102   c  exceeds a threshold of consumed queue entries. Similarly, the logic may also generate an EMPTY signal. This logic may also manage queue head and tail indexes to implement a queue ring that perpetually wraps around the registers as entries are produced and consumed. The signals produced by the logic may be used both by the receiving processor core  100   a - 100   c  and by the upstream processor core writing to the registers  102   a - 102   c  to determine the state of a queue.  
         [0010]     The processor cores  100   a - 100   c  depicted in  FIG. 1  are heterogeneous. That is, the processor cores  100   a - 100   c  may provide different functional operationality. For example,  FIG. 1  features a first set of cores (cores A 1   100   a  and A 2   100   c ) having the same functional operationality and a core B 1  (shaded) having different functional operationality. For instance, the “A” cores and “B” core(s) may differ in the instruction set offered by the cores. The heterogeneous cores may also feature different internal core architectures. For instance,  FIGS. 4 and 5  depict the different component architectures of a microengine processor core and an XScale(r) processor core. While  FIG. 1  depicted a single core  100   b  having a different functional operationality than the other cores  100   a ,  100   c , other implementations may have more than one such core.  
         [0011]     Data transmissions over connections  104   a ,  104   b  depicted in  FIG. 1  are asynchronous with respect to one another. That is, while the connections may be commonly clocked, a transfer of data across any one of the connections is independent with respect to data transfer over the other connections. For example, core A 1   100   a  can transfer data to core B 1   100   b  irrespective of whether core B 1  is transferring data to core A 2   100   c.    
         [0012]     Though not shown, the cores  102   a - 102   c  may feature additional circuitry to signal transfer of a data across the connections. For example, core  102   a  may send a signal to core  102   b  after writing data into register(s)  104   b.    
         [0013]     As shown in  FIG. 1 , the connections between the heterogeneous cores  100   a - 100   c  may form a unidirectional chain of connected cores. As shown in  FIGS. 2A-2C , the connections between cores may form different core networks. For example, the processor shown in  FIG. 2A  features two clusters of homogeneous processor cores  100   a - 100   h ,  100   j - 100   p  linked by connections to/from processor core  100   i  having a different functional operationality. In this example, like the architecture shown in  FIG. 1 , the unidirectional connections form an acyclic graph.  
         [0014]     Instead of being the source of a single dedicated unidirectional connection, a given core may feature multiple such connections. For example, as shown in  FIG. 2B , core  100   i  has unidirectional connections to cores  100   j  and  100   h . A core may also be the destination of multiple unidirectional connections. For example, core  100   i  receives data from cores  100   j  and  100   h . In such embodiments, a given processor core  100   i  may feature different sets of registers  104   n  terminating each in-bound unidirectional connection. In other implementations, the interconnections between processor cores  100  may not be limited to a linear chain. For example, the processor shown in  FIG. 2C  may feature processor cores interconnected by a number of different unidirectional connections. Additionally, in other implementations (not shown), the processor cores  100  may not be co-planar. In such implementations, the different unidirectional connections may be between cores on different planes (e.g., a unidirectional connection extending in the x, y, or z dimension).  
         [0015]     The inter-core connections described above can be implemented in a variety of processors. For example, the techniques may be used within a network processor. For instance,  FIG. 3  depicts an example of network processor  200  that can be programmed to process packets received over a network. The network processor  200  shown is an Intel® Internet eXchange network Processor (IXP). Other processors feature different designs.  
         [0016]     The network processor  200  shown features a collection of programmable processor cores  220   a  known as microengines on a single integrated semiconductor die. Each processor core  220   a  may be a Reduced Instruction Set Computer (RISC) processor tailored for packet processing. For example, the processor cores  220   a  may not provide floating point or integer division instructions commonly provided by the instruction sets of general purpose processors. Individual processor cores  220   a  may provide multiple threads of execution. For example, a processor core  220   a  may store multiple program counters and other context data for different threads.  
         [0017]     The network processor  200  also includes an additional general purpose processor core  220   b  (e.g., a StrongARM® XScale® or Intel Architecture core) that is often programmed to perform “control plane” or “slow path” tasks involved in network operations while the cores  220   a  are often programmed to perform “data plane” or “fast path” tasks. The network processor  200 , thus, includes a heterogeneous set of processor cores (e.g., the microengines  220   a  and the XScale  220   b ).  
         [0018]     As shown, other components of the network processor  200  include an interface  202  that can carry packets between the processor  200  and other network components. For example, the processor  200  can feature a switch fabric interface  202  (e.g., a Common Switch Interface (CSIX)) that enables the processor  200  to transmit a packet to other processor(s) or circuitry connected to a switch fabric. The processor  200  can also feature an interface  202  (e.g., a System Packet Interface (SPI) interface) that enables the processor  200  to communicate with physical layer (PHY) and/or link layer devices (e.g., MAC or framer devices). The processor  200  may also include an interface  204  (e.g., a Peripheral Component Interconnect (PCI) bus interface) for communicating, for example, with a host or other network processors.  
         [0019]     As shown, the processor  200  includes other components shared by the processor cores  220   a ,  220   b  such as a cryptography core  210 , internal scratchpad memory  208 , and memory controllers  216 ,  218  that provide access to external memory shared by the cores  220   a . The processor cores  220  may communicate with other processor cores  220  via the shared resources (e.g., by writing data to external memory or the scratchpad  208 ). The cores  220  may also communicate via a CAP (CSR (Control Status Register) Access Proxy)  211  unit that routes data between cores  220 .  
         [0020]     The cores  220  may also communicate using the unidirectional connections described above. As shown, the connections between the processor cores includes a connection between one of the microengine cores  220   a  and XScale core  220   b  and between the XScale core  220   b  and one of the microengine cores  220   a . In IXP parlance, the XScale core  220   b  is the “next neighbor” of the upstream microengine core  220   a  sending the XScale core  220   b  data, though the term neighbor need not imply a geographic proximity on the die. Likewise, the downstream core  220   a  receiving data from the XScale core  220   b  is the XScale core&#39;s  220   b  next neighbor.  
         [0021]     The direct connection from a microengine  220   a  to the XScale  220   b  can dramatically improve performance of the network processor. That is, instead of using cycles of a microengine core  220   a  to write data to the scratchpad  208  for the XScale core  220   b  to read, data (e.g., packet or packet meta-data data or pointers) can be directly delivered to the XScale  220   b  in a single cycle. In addition to speeding data transfer to the XScale  220   b , the connection frees the scratchpad  208  for other purposes.  
         [0022]      FIG. 4  depicts a sample microengine processor core  220   a  component architecture in greater detail. As shown the core  220   a  includes an instruction store  312  to store programming instructions processed by a datapath  314 . The datapath  314  may include an ALU (Arithmetic Logic Unit), Content Addressable Memory (CAM), shifter, and/or other hardware to perform other operations. The core  220   a  includes a variety of memory resources such as local memory  302  and general purpose registers  304 . The core  220   a  shown also includes read and write transfer registers  308 ,  310  that store information being sent to/received from components external to the core; next neighbor registers  306  that store information being directly received from an upstream “neighbor” core  220   a  over the unidirectional connection; and next neighbor registers  316  that buffer information being transferred to a downstream neighbor core  220   a.    
         [0023]     The next neighbor registers  306 ,  316  may be used as register operands in the microengine instructions. The microengine may feature the instruction set, for example, listed in Appendix A of “Using IXP2400/2800 Development Tools” by Donald Hooper, copyright 2004 Intel Press.  
         [0024]      FIG. 5  depicts the component architecture of an XScale  220   b  processor core. As shown, the XScale processor core components features an execution core  410  (e.g., an ARM core) and next neighbor registers  412  that terminate a unidirectional connection from a source microengine. The XScale ARM instruction set (described, for example, in “ARM: Architecture Reference Manual”, by David Seal, 2nd edition, copyright 2000, Addison-Wesley) can include the registers  412  as register operands in the XScale data processing instructions. The next neighbor registers  412  may be used to both buffer data being written over a unidirectional connection to the XScale&#39;s next neighbor and to buffer data received from an upstream next neighbor. Additionally, the XScale may include ring registers to store ring queue indexes (e.g., head and tail) and flags identifying the state of a queue implemented on the registers  412 .  
         [0025]     As shown, the XScale processor core  220   b  executes instructions provided by instruction cache  422 . The instruction cache  422  is loaded in response to request from the ARM core  410  and by instruction memory management unit  424  in the case of prefetch requests. A branch target buffer  426  includes a history of particular instructions branches taken during execution.  
         [0026]     The XScale  220   b  can access memory through caches  416 ,  414 . Fetching from external memory is handled by the memory management unit  418 . Data being written to external memory can be buffered in the write buffer  420  to speed write operations. The XScale  220   b  shown also features a co-processor  402  that handles multiply and accumulate operations commonly used in audio media applications. The XScale  220   b  also includes other components such as a performance monitor  430  having programmable event and clock counters, system management unit  404  that permits clock and power management, and a JTAG (Joint Test Access Group) port  406  that can provide access to a debug unit  408  that permits debugging operations (e.g., stop execution) to be performed by an external host system.  
         [0027]     While  FIGS. 4 and 5  depicted specific processor core architectures, a wide variety of other architectures may be used. For example, an IA (Intel Architecture) core may be used in lieu of an XScale core. Other manufactures provide cores with different architectures, featuring different components, and providing different functional operationality.  
         [0028]      FIG. 6  depicts a network device that includes a heterogeneous multi-core processor described above. As shown, the device features a collection of blades  508 - 520  holding integrated circuitry interconnected by a switch fabric  510  (e.g., a crossbar or shared memory switch fabric). As shown the device features a variety of blades performing different operations such as I/O blades  508   a - 508   n , data plane switch blades  518   a - 518   b , trunk blades  512   a - 512   b , control plane blades  514   a - 514   n , and service blades. The switch fabric, for example, may conform to CSIX or other fabric technologies such as HyperTransport, Infiniband, PCI, Packet-Over-SONET, RapidIO, and/or UTOPIA (Universal Test and Operations PHY Interface for ATM).  
         [0029]     Individual blades (e.g.,  508   a ) may include one or more physical layer (PHY) devices (not shown) (e.g., optic, wire, and wireless PHYs) that handle communication over network connections. The PHYs translate between the physical signals carried by different network mediums and the bits (e.g., “0”-s and “1”-s) used by digital systems. The line cards  508 - 520  may also include framer devices (e.g., Ethernet, Synchronous Optic Network (SONET), High-Level Data Link (HDLC) framers or other “layer 2” devices)  502  that can perform operations on frames such as error detection and/or correction. The blades  508   a  shown may also include one or more network processors  504 ,  506  having the unidirectional connections described above that perform packet processing operations for packets received via the PHY(s)  502  and direct the packets, via the switch fabric  510 , to a blade providing an egress interface to forward the packet. Potentially, the network processor(s)  506  may perform “layer 2” duties instead of the framer devices  502 .  
         [0030]     While  FIGS. 3-6  described specific examples of a network processor and a device incorporating network processors, the techniques may be implemented in a variety of processor architectures. Additionally, the techniques may be used in a wide variety of network devices (e.g., a router, switch, bridge, hub, traffic generator, and so forth).  
         [0031]     The term logic as used herein includes hardwired circuitry, digital circuitry, analog circuitry, programmable circuitry, and so forth. The programmable circuitry may operate on computer programs.  
         [0032]     Other embodiments are within the scope of the following claims.