Abstract:
Efficient calibration of circuits is performed using injection imprecise voltage by using different voltages in a subtractive manner to be able to calibrate with respect to a voltage that is out of a desirable measurable range using measuring circuitry. Efficient background calibration of circuits is also achieved by providing an equivalent circuit element to circuit elements receiving an injected calibration signal, and switching circuit elements. Such imprecise voltages can be determined through such calibration, and then used to calibrate a second circuit generating the imprecise voltages.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to calibration of circuits, such as analog-to-digital converters and precision resistor based circuits.  
       BACKGROUND OF THE INVENTION  
       [0002]     In precision circuits where the values of resistors, capacitors, transistors, and other components whose values in actual circuit implementations may be different from design specifications, either statically or transiently due to environmental conditions such as temperature, calibration of such values is of paramount importance. When a component value is calibrated and an error is detected, a physical component value can be changed or “trimmed” accordingly to compensate for an error, or the circuit components can be left alone and the error corrected or compensated for either by built-in compensation circuitry or computation logic or by external compensation. In cases of unacceptable errors or a lack of suitable compensation mechanism, the circuit may need to be discarded.  
         [0003]     Calibration may be performed in a variety of ways. Two general types can be defined: background calibration; and foreground calibration. In foreground calibration, operation of the circuit is stopped while calibration is carried out, while in background calibration, circuit operation continues while calibration is carried out. Foreground calibration has the inherent advantage that test signals can be injected into the circuit without concern for the normal operation, and the desired values to be calibrated can be measured as a function of test signals. Measurement of the output values of the circuit as a whole or from selected circuit components or subcircuits is typically performed by additional testing logic, whether built-in or off-circuit. In the case of an ADC for example, a test analog signal can be swept though the dynamic range of the ADC, and the digital output response can be compared. Additionally or alternatively, key components can be fed specific test signals, and responses measured. Such test signals and response measurement are normally done by dedicated circuitry not involved in the normal operation of the circuit. In the case of calibrating a device, such as an analog-to-digital converter (ADC), there is significant advantage to being able to maintain precision of the device through background calibration without removing the device from normal continuous use. However, it is inherently more challenging to measure circuit values without disrupting normal operation by the use of known rest signals.  
         [0004]     In some types of precision circuit devices, such as pipelined ADC&#39;s, the devices comprise interconnected stages, such as first stage precision circuitry whose output is measured by second stage precision circuitry. In the case of pipelined ADC&#39;s, the first stage converts one or more most-significant bits (MSB) of the analog signal, generates from those bits an analog signal to be subtracted from the input analog signal, and the difference is amplified and measured in the next stage. The next stage measures the next lesser significant bits, and the number of stages may be two, three or more. The last stage is often essentially a flash ADC. Flash ADC devices gain complexity and consume power almost geometrically for each additional bit of resolution added. Pipelined ADC&#39;s allow greater resolution without geometrically increasing complexity and power consumption, with the trade-off that each stage beyond the first introduces a sample delay in the output of the ADC.  
       SUMMARY OF THE INVENTION  
       [0005]     It has been discovered that efficient calibration of circuits can be performed using imprecise voltages by using different voltages in a subtractive manner to be able to calibrate with respect to a voltage that is out of a desirable measurable range using measuring circuitry. The resulting calibration becomes independent of the exact value of the imprecise voltages. It has been further discovered that such imprecise voltages can be determined through such calibration, and then used to calibrate a second circuit generating the imprecise voltages.  
         [0006]     It has been discovered that efficient background calibration of circuits can be performed by providing an equivalent circuit element to circuit elements receiving a calibration signal, and switching circuit elements.  
         [0007]     According to one aspect of the invention, a digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), amplifier finite DC gain, and reference voltage inaccuracy in multi-bit/stage pipelined analog-to-digital converter (ADC) is provided. By injecting subtractive imprecise voltages (SIV) in a modified conventional multi-bit multiplying digital-to-analog converter (MDAC) and performing correlation based successive coefficient measurements (SCM), a background calibration is achieved. This calibration does not need accurate calibration voltages or increasing the SDAC resolution.  
         [0008]     Further, a global gain correction (GGC) for time-interleaved ADCs is provided. Techniques to shorten the calibration duration are further provided. Simulation results demonstrate that in the presence of realistic capacitor and resistance mismatch and finite op-amp gain, these techniques improve the linearity by several bits in single and multi-channel pipelined ADC.  
         [0009]     According to one aspect of the invention, there is provided a method of background calibrating a circuit to be calibrated having a plurality of circuit elements and providing an output residue. The method comprises switching one of the circuit elements to be substituted by an equivalent circuit element within the circuit, and injecting at least one calibration signal into at least one of the circuit elements, wherein the calibration signal causes a measurable change in the output residue. The measurable change is measured and a calibration parameter for the circuit is calculated based on the change, and a calibration correction to an output of the circuit is performed using the parameter. Optionally, the calibration correction comprises correcting for the measurable change.  
         [0010]     In the case that the output residue is essentially an AC signal, the change may be measured by obtaining an average of the output residue with the calibration signal injected and an average of the output residue without the calibration signal injected, the change being a difference between the averages. In this case, the injecting may comprise alternating between no injecting and injecting of the calibration signal from measurement to measurement. So that the averages may be free of aliasing, the injecting may alternate in a random or pseudorandom manner.  
         [0011]     In some embodiments, the circuit is a pipelined ADC comprising a plurality of stages, the measuring being performed using the stages downstream of one of the stages whose circuit elements are being calibrated, the magnitude of the measurable change being small enough such that the output residue is within a dynamic range of the downstream stages.  
         [0012]     According to another aspect of the invention, there is provided a method of calibrating a voltage reference. The method comprises providing a first circuit having a plurality of calibrated circuit elements and generating an output residue having a dynamic range for measurement, the calibrated circuit elements having a known value. At least two calibration signals are provided to operate in the first circuit in a subtractive manner so that the output residue remains within the dynamic range. This involves providing a group of different imprecise voltages for the calibration signals having at least one value that used alone would cause the residue to lie outside the dynamic range and at least one value that used alone would cause the residue to lie within the dynamic range, selecting a series of different combinations of ones of the group of imprecise voltages for injection in the subtractive manner, the series of combinations including one of the imprecise voltages to be isolated once, a remainder of the imprecise voltages each used in two of the different combinations, with one of the different combinations comprising a zero voltage and one of the imprecise voltages having a value that used alone would cause the residue to lie within the dynamic range, and injecting in the first circuit each of the different combinations of the imprecise voltages as the calibration signals. The measurable change for each of the different combinations is measured, and from a sum of the change measured for each of the different combinations, a value is calculated that is a function of the one of the imprecise voltages to be isolated independently of the remainder of the imprecise voltages. Preferably, the first circuit may comprise circuitry that outputs as the residue a difference between the calibration signals, the reference value being the value calculated that is equal to the one of the imprecise voltages to be isolated.  
         [0013]     In a preferred embodiment, the group of imprecise voltages comprises a string resistance connected at one end to a reference voltage and to the zero voltage at another end. In this case, steps of the method can be repeated to identify a ratio of resistances in the string resistance.  
         [0014]     According to another aspect of the invention, there is provided a multiplying-digital-to-analog (MDAC) circuit for use in a background calibrated pipelined analog-to-digital (ADC) circuit. The MDAC comprises a plurality, n, of inputs from a sub-digital-to-analog converter (SDAC), an amplifier, a feedback capacitor and switches for connecting the feedback capacitor in a first state between ground and a first modulated voltage, and in a second state between an input of the amplifier and an output of the amplifier, a switch matrix having a plurality, n+1, of outputs for controllably directing, in response to a control signal, the inputs from the SDAC and a second modulated voltage, and a plurality, n+1, of summing capacitors connected on one side to the input of the amplifier and connected on another side, in the first state, via switches to a stage input voltage and, in the second state, via switches to an output of a corresponding one of the switch matrix outputs. Preferably, the switch matrix comprises a plurality, n+1, of multiplexers, wherein n of the multiplexers have one input connected to a corresponding one of the inputs from the SDAC, and an (n+1)th one of the multiplexers has an input from each of the inputs from the SDAC, the multiplexers each having an input from the second modulated voltage, and providing a corresponding one of the switch matrix outputs.  
         [0015]     According to a further aspect of the invention, there is provided a method of background calibrating a pipelined ADC circuit to be calibrated having a plurality of circuit elements and providing an output residue. The method comprises injecting at least one calibration signal into at least one of the circuit elements of a stage of the ADC under calibration, wherein the calibration signal causes a measurable change in the output residue of the stage, predicting a value of the output residue of the stage without the injecting, using a backend ADC of the pipelined ADC to measure an output residue of a stage upstream of the stage under calibration, and predicting a value of a sub-DAC output of the stage under calibration, measuring the change using the output residue of the stage under calibration using the backend ADC, the predicted value of the output residue of the stage without the injecting, and the predicted value of the sub-DAC output of the stage under calibration, calculating a calibration parameter for the circuit based on the change, and performing a calibration correction to an output of the circuit using the parameter. Preferably, the measuring of the change may comprise obtaining an average of the comparison of the output residue with the predicted value.  
         [0016]     According to a further aspect of the invention, there is provided a method of background calibrating a circuit to be calibrated having a plurality of circuit elements and providing an output residue in which the residue occupying an identified frequency range during normal operation. The method comprises injecting at least one calibration signal into at least one of the circuit elements of the circuit, wherein the calibration signal causes a measurable change in the output residue of the stage, and alternating between no injecting and injecting of the calibration signal from measurement to measurement at an injection frequency resulting in the measurable change having a frequency outside of the frequency range. The method then comprises detecting the identified frequency range, and setting the injection frequency such that the measurable change has a frequency outside the identified frequency range, filtering the residue to detect the change at the frequency outside of the frequency range, calculating a calibration parameter for the circuit based on the change, and performing a calibration correction to an output of the circuit using the parameter. In some embodiments, when there is no suitable injection frequency resulting in the measurable change having a frequency outside of the frequency range, then the change may be measured by obtaining an average of the output residue with the calibration signal injected and an average of the output residue without the calibration signal injected, the change being a difference between the averages, the injecting alternating in a random or pseudorandom manner, whereby the averages are free of aliasing. In the case that the circuit is a pipelined ADC circuit, the step of filtering may comprise using a backend ADC of the pipelined ADC to measure the filtered residue.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The invention will be better understood by way of the following detailed description of a preferred embodiment with reference to the appended drawings, in which:  
         [0018]      FIG. 1  is a block diagram of a multi-bit/stage pipelined ADC according to the prior art;  
         [0019]      FIG. 2  is a circuit diagram of a 2.5 bit per stage multiplying digital-to-analog converter (MDAC) according to the prior art;  
         [0020]      FIG. 3A  is a plot of the residue of a realistic 2.5 bit per stage MDAC compared to an ideal one;  
         [0021]      FIG. 3B  is a similar plot of the residue of a realistic 2.5 bit per stage MDAC illustrating the change in the residue as a result of injecting a calibration signal;  
         [0022]      FIG. 4  is a plot of the input-output relationship of the overall pipelined ADC comparing ideal, uncalibrated and calibrated responses;  
         [0023]      FIG. 5  is a block diagram showing digital calibration logic used in the final digital output construction in a pipelined multi-bit per stage ADC;  
         [0024]      FIG. 6  is a plot illustrating the transfer functional of 2 ADC&#39;s compared with an ideal one;  
         [0025]      FIG. 7  is a block diagram of a modified 2.5 bit per stage multiplying digital-to-analog converter (MDAC) according to the preferred embodiment in which the modified MDAC is used for background calibration of a multibit per stage pipelined ADC digital calibration;  
         [0026]      FIG. 8A  is a block diagram of a simplified example wherein the subtractive imprecise voltage (SIV) background calibration technique is applied to the first stage of a pipelined ADC;  
         [0027]      FIG. 8B  is a block diagram of a multi-bit/stage pipelined ADC including background calibration according to the preferred embodiment;  
         [0028]      FIG. 8C  is a block diagram identical to  FIG. 8B  with the addition that the imprecise voltage source being shared with a precise-resistive based application circuit;  
         [0029]      FIG. 9  is a block diagram of a switching matrix used to generate calibration voltages V 1  and V 2  from a string resistance dividing the voltage (+V R )−(−V R );  
         [0030]      FIG. 10  illustrates a filter characteristic of a filter used to measure injected calibration signals in a residual output, the residual output having a maximum frequency during normal operation less than fs/2, and the injected signal being injected at a frequency of fs/2;  
         [0031]      FIG. 11  is a block diagram of an embodiment of a background calibrated pipelined ADC in which the backend stage operates at double frequency to be able to measure the residual of two stages;  
         [0032]      FIG. 12  is a block diagram of an embodiment of a background calibrated pipelined time-interleaved ADC;  
         [0033]      FIG. 13  shows a matrix used to generate the voltages V 1  and V 2  when K=4;  
         [0034]      FIG. 14  is a circuit diagram of a resistor string DAC;  
         [0035]      FIG. 15  is a circuit diagram of an R/2R DAC;  
         [0036]      FIG. 16  is a circuit diagram of an op-amp/filter having control switches for configuration between calibration and normal operation phases;  
         [0037]      FIG. 17  is a circuit diagram of a charge capacitive DAC;  
         [0038]      FIG. 18  is a circuit diagram of a trimmed analog circuit using a feedback voltage;  
         [0039]      FIG. 19  is a circuit diagram of a prior art sample-and-hold circuit;  
         [0040]      FIG. 20  is a circuit diagram of a modified sample-and-hold circuit according to an embodiment of the invention; and  
         [0041]      FIGS. 21   a ,  21   b  and  21   c  illustrate the transfer function of the sample-and-hold circuit according to the embodiment of  FIG. 20 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0042]     According to the preferred embodiment, a novel digital background calibration technique that corrects for the nonlinearity and gain error in the sub-DAC (SDAC), amplifier finite DC gain and reference voltage inaccuracy in a multi-bit/stage pipelined ADC is provided. This background calibration technique does not rely on accurate injected calibration voltages that are difficult to be obtained on chip or that would increase the SDAC or SADC precision or even split up the capacitor sizes that limit the maximal achievable speed. Also a global gain correction (GCC) useful for time-interleaved ADC (TIADC) and techniques to shorten the calibration duration are provided.  
         [0000]     Multibit/Stage Pipelined ADC Digital Calibration  
         [0043]     The general block diagram of a pipelined ADC where front-end stages resolve several bits (e.g 2.3 or 3.5) is shown in  FIG. 1 . The output residue V n  of stage i is expressed as: 
 
 V   n   =G   1 ·( V   1   −V   z,999  )   (1) 
 
 Where V z,999  and G 1  are the SDAC analog output and the interstage gain respectively. 
 
         [0044]     The input of the entire pipelined ADC can be obtained by:  
               V   in     =       V     dac   ⁢           ⁢   1       +       V     dac   ⁢           ⁢   2         G   1       +       V     dac   ⁢           ⁢   3           G   1     ⁢     G   2         +   …   +       V   dacp         G   1     ⁢     G   2     ⁢   …   ⁢           ⁢     G     p   -   1           +   Δ             (   2   )             
 
 where Δ stands for the quantization error of the entire ADC. 
 
         [0045]     According to Eq. (2) the input signal can be accurately generated when the effective values of V z,999  and G 1  are used. Capacitor mismatch creates non-linearity in the SDAC that limits the precision of V z,999  . Also the capacitor mismatch and the finite opamp gain deviate G 1  from its ideal value.  
         [0046]     The MDAC circuit of  FIG. 2  includes the SDAC, the adder and the amplifier illustrated in the schematic expansion of the Stage 2 block of  FIG. 1 . On φ 1 , the analog voltage from the sample and hold circuit, SHA, is loaded onto the capacitors, while on φ 2 , the amplifier feedback through C 1 —is connected, and the digital values from the sub-ADC (SDAC) are loaded on the capacitors to measure the difference between V i  and V DAC . For a 2.5 bit/stage multiplying digital-to-analog converter (MDAC), as shown in  FIG. 2 , the residue voltage can be derived as:  
               V   p     =           G   A     ·     G   p     ·     (       ⁢     V   1       -     V     dac   ⁢           ⁢   1       +             C   T     +     C   p         C   t       ·     V   as       ⁢     
     ⁢   where               (   3   )                 C   T     =       C   f     +     C   1     +     C   2     +     C   3               (   4   )                 G   A     =     1   /     (     1   +     1   /   Af       )               (   5   )             
 
         [0047]     and G A  is the interstage gain due to the finite opamp gain A that is ideally equal 1.  
         [0048]     The feedback factor f is equal: 
 
 f=C   f /( C   T   +C   P )   (6) 
 
         [0049]     C P  is the virtual ground parasitic capacitance. 
 
 G   C =( C   1   +C   2   +C   3   +C   i )/ C   f    (7) 
 
         [0050]     G C  is the interstage gain due to SDAC ideally equal 2 2 . 
 
 G   1   =G   A   ·G   C    (8) 
 
 V   z,999  =( d   1   ·C   1   +d   2   ·C   2   +d   3   ·C   3 )· V   R   /C   T    (9) 
 
         [0051]     G 1  is the interstage gain and V z,999  is the SDAC output.  
         [0052]     V R  is the reference voltage and d 1  are the digital output code of the SADC where d 1 ∈{−1,0,1 } and d=Σ z,999    3 d i .  
         [0053]      FIG. 3A  depicts the residue plot of a realistic 2.5 bit/stage given by Eq. (3) compared with an ideal one. Nonlinearity of the SDAC and the inter-stage gain error, due to the deviation of G 1  from 2 2 , introduce mismatch in the residue jumps in the different boundaries of the digital code d.  FIG. 3A  shows the effect of this error on the input-output relationship of the overall pipelined ADC when the stage i is considered as the first stage and the remaining stages were ideal. The discontinuities, generally referred to as major-carry jumps in the uncalibrated ADC curve shown in  FIG. 3A , cause deleterious missing codes and harmonic distortion that degrade considerably the ADC performance.  
         [0054]     By measuring exactly the value of the jumps G A ·(C i /C f )·V n  in the residue and by using the following equation, the residue output becomes linear when it is referred to the input of the stage i despite the gain errors of the SDAC and the opamp, and the reference voltage inaccuracy.  
                 V   o     -       ∑     l   =   1     3     ⁢       d   1     ·     G   A     ·       C   i       C   f       ·     V   R           =       G   A     ·     G   C     ·     V   i               (   10   )             
 
         [0055]     Ideally the gain is equal to 2 n−1  for n-bit SADC in the stage i. After the correction using Eq. (10) the backend, constituted now from the stage i and the following stage, is linear with a global gain G i −G A ·G C .  
         [0056]     When the stage i is the first stage and after calibrating the ADC the calibrated transfer curve is shown in  FIG. 4 , where the input-output relationship is linearized and the global gain is equal to the ideal gain multiplied by G 1 /2 n−1 . After measuring the errors associated with stage i, stage i−1 can be calibrated using the linearized backend formed from stage i and its following stages.  
         [0057]     The final digital output D out  is constructed, as shown in  FIG. 5 , by starting the correction from the least significant stages to the most significant ones.  
         [0000]     Global Gain Correction  
         [0058]     Several calibration methods cause the slope of the overall ADC transfer characteristic to depend on the actual residue gains and is therefore not well controlled.  FIG. 4  shows that the final gain is multiplied by G i /2 n−1  in the case of correction of the first stage. The global gain mismatch is harmful for some applications such as time interleaved ADC (TIADC) that are inevitable when increasing the speed is desired with high resolution ADCs to overcome the technology limits. With gain mismatch between the different channels, inband distortions are created and that degrades considerably performance of time-interleaved ADC systems, as for example is known from the article by N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara and K. Kobayashi, titled “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” and published in  IEEE Trans. Circuits Syst. I , vol. 48, pp. 261-271, March 2001. In  FIG. 6 , the transfer functions of 2 ADCs are compared with an ideal one. By succeeding in measuring the global gain G i /2 n−1 , and G 2 /2 −2 for the channels ADC 1  and ADC 2 , a global gain correction is possible by dividing the final digital output of each ADC by 2 n−1 /G 1  and 2 n−1 /G 2  respectively ( FIG. 6 ).  
         [0059]     In the case of calibrating the first stages in ADC 1  and ADC 2 , the gain G 1  (i=1,2) can be computed using the following equation,  
                     G   1     =       G   A     ·     G   C                   =       (         C   f     +     C   1     +     C   2     +     C   3         C   f       )     ·     G   A                   =       G   A     +       G   A     ·       C   1       C   f         +       G   A     ·       C   2       C   f         +       G   A     ·       C   3       C   f                         (   11   )             
 
         [0060]     This equation indicates that for a global gain correction (GGC), a separate measurement for the gain G A  from the other products in Eq.(10) needs to be performed.  
         [0000]     Digital Background Calibration  
         [0061]     In the background calibration method of the preferred embodiment, the team G A (C i /C f )V R  is measured for the different values of C i  to enable the usage of Eq. (10). A schematic of a modified 2.5-bit MDAC according to the preferred embodiment is shown in  FIG. 7 . The most significant modification of this MDAC from the conventional one is the addition of an extra capacitor C 4 . Furthermore, voltage V 1 ·P N  is sampled onto the feedback capacitor C f  when φ 1  is high, where P N  is a pseudorandom signal alternating between 0 and 1.  FIG. 3B  illustrates the influence of P N  on the MDAC response.  
         [0062]     Capacitor C 4  is used instead of C f  to sample the input voltage when φ 1 , is high. By doing so, a voltage equal G A ·V 1  is injected in the residue output. In background calibration, V in  is an unknown, and thus an average of the residue is calculated. With reference to the residue plot of  FIG. 3 , it will be appreciated that the residue average across all d i  values has a “DC” mean value, the latter being increased when P N  is 1 by ΔV=G A ·(V 1 −(C 4 /C f )V 3 ) and then returning its normal value when P N  is 0. When the averaging is complete for C 4 , and ΔV is measured, the multiplexers in  FIG. 7  are controlled to calibrate the next in the remainder of the capacitors.  
         [0063]     To not consume much from the offset correctable range of the SADC, V 1  should be a small and stable analog voltage. A voltage could be injected by splitting up the unit capacitor but the voltage V 1  cannot be made arbitrarily small. Also, splitting up the capacitors will limit the maximal achievable speed because, in this case, sampling capacitors bigger than the minimal possible size will be used. For this reason, a voltage V 2 −P N  is sampled onto the capacitor C 4  in the next phase when φz, 999  is high. The voltage V 1  and V 2  do not need to be accurate (as explained below). By injecting these voltages, a subtractive imprecise voltage (SIV) is injected in output residue for the stage under calibration given by:  
               V   o     =         G   A     ·     (         G   C     ·     V   1       -             d   1     ·     C   1       +       d   2     ·     C   2       +       d   3     ·     C   3           C   f       ·     V   R       +       P   N     ·     V   1       -       P   N     ·       C   2       C   f       ·     V   2       +             ∑     t   =   1     N     ⁢     C   1       +     C   f     +     C   P         C   f       ·     V     o   ⁢           ⁢   3           )       =         G   A     ·     (       V   1     -       V   2     ·       C   o       C   f           )     ·     P   N       +     V     o   ⁢           ⁢   1                   (   12   )             
 
 where G C =(C 1 +C 2 +C 3 +C 4 )/C f  and V z,999  is the remaining term in V n . 
 
         [0064]     A simplified example wherein the SIV technique is applied to the first stage is shown in  FIG. 8A . By correlating the backend ADC digital output D[V n ] with P N  the term ΔV=G A ·(V 1 −(C 4 /C f )V 2 ) is extracted. P N1  is used for correlation instead of P N , Where P N1 alternates between −1 and +1 instead of 0 and 1 in P N . That substitution averages out the mean of the remaining term D[V n1 ] since P N1  has a mean value of 0.  
         [0065]     The output of the averager Δe is given by:  
                     Δ   ⁢           ⁢   e     =       ⁢       1   N     ⁢       ∑     k   =   1     N     ⁢     (       D   ⁡     [       V   o     ⁡     (   k   )       ]       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         )                     =       ⁢         1   N     ⁢       ∑     k   =   1     N     ⁢     (       D   ⁡     [     Δ   ⁢           ⁢   V     ]       ·       P   N     ⁡     (   k   )       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         )         +                     ⁢       1   N     ⁢       ∑     k   =   1     N     ⁢     (       D   ⁡     [       V     o   ⁢           ⁢   1       ⁡     (   k   )       ]       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         )                       (   13   )             
 
         [0066]     The expected value of Δe is:  
                     E   ⁡     [     Δ   ⁢           ⁢   e     ]       =       ⁢           D   ⁡     [     Δ   ⁢           ⁢   V     ]       N     ⁢       ∑     k   =   1     N     ⁢     (       E   ⁡     [         P   N     ⁡     (   k   )       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         ]       ·     )         +                     ⁢       1   N     ⁢       ∑     k   =   1     N     ⁢     E   ⁡     [       D   ⁡     [       V     o   ⁢           ⁢   1       ⁡     (   k   )       ]       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         ]                       =       ⁢       1   2     ·     D   ⁡     [     Δ   ⁢           ⁢   V     ]                       (   14   )             
 
         [0067]     Since D[V o1 ] and P N1  are uncorrelated and E[P N (k)·P N1 (k)]=½, the variance, σ z,999    2 , of Δe is:  
                     σ     Δ   ⁢           ⁢   σ     2     =       E   ⁡     [     Δ   ⁢           ⁢     e   2       ]       -       E   ⁡     [     Δ   ⁢           ⁢   e     ]       3                   =       1     N   2       ⁢       ∑     t   =   1     N     ⁢     (       E   ⁡     [       D   ⁡     [       V     n   ⁢           ⁢   1       ⁡     (   k   )       ]       2     ]       ·     E   ⁡     [       P     N   ⁢           ⁢   1     2     ⁡     (   k   )       ]         )                     =       1   N     ⁢     σ     D   ⁡     [     V     o   ⁢           ⁢   1       ]       2                     (   15   )             
 
 where σ VN1   2 =E[P N1   2 (k)]=1. 
 
         [0068]     The averager output is not constant in the steady state. Instead, it contains a random fluctuation caused by the term involving the variance of D[V n1 ]. Because this term is accumulated, however, it can be made arbitrarily small by increasing the number of samples (N) at the input of the averager in  FIG. 8A .  
         [0069]     In the simplified example of  FIG. 8A , only the first stage is calibrated. It will be appreciated that the modified MDAC of  FIG. 7  is used to perform calibration for each term related to each capacitor in order to achieve full calibration. In the complete block diagram of  FIG. 8B  illustrating the preferred embodiment, two stages  20   a  and  20   b  are calibrated, and the calibration control system  50  is shown. The pseudorandom generator  54  provides two uncorrelated streams of binary signals, P N1  and P N2 . As in  FIG. 8A , the signals may be converted from a 0 and 1 state used in the  FIG. 7  into a −1 and +1 state for use in correlation so that the mean correlation has a value of 0. The imprecise voltages V 1  and V 2  used in MDAC  24   a  and V 3  and V 4  used in MDAC  24   b  are provided by a voltage switching matrix  52 . The control unit  50  outputs control signals for the switching matrix  52  and the muxes of the MDAC&#39;s  24  to select a capacitor to receive the imprecise voltage selected. The controls signals are also communicated to the successive coefficient measurement unit  46  that analyses the averaged errors Δe 1  and Δe 2  to determine the correction values associated with each capacitor in the MDAC&#39;s. The ADC calibration logic  40  uses the correction values from unit  46  along with the random values P N1  and P N2  to process each sample from the ADC uncorrected output from the digital error correction unit  30  to provide the desired corrected output samples. Global gain correction, that is particularly desirable in the context of a time-interleaved ADC, is schematically illustrated as being performed in unit  48  on the output of calibration logic  40 . Of course, global gain correction can be performed within logic  40 .  
         [0070]     The voltages injected into MDAC  24   b  cause a measurable change in the residual V o2  that is measured by the backend ADC  20   c . The residue V o1  is measured by the sub-ADC of stage  20   b . Measurement of the measurable change caused by the subtractive injection is done using a correlator  44   a , 44   b  and averaging unit  42   a , 42   b  for the respective stages under calibration to provide the respective averaged errors Δe 1  and Δe 2 .  
         [0071]     Increasing the number of samples N to achieve calibration means increasing the required calibration time. In the following, two techniques to accelerate the convergence rate at a low overhead are described. In the preferred embodiment, the term G A (C 4 /C f )V R  is found by injecting subtractive imprecise voltages (SIV) and performing successive coefficient measurements (SCM) as explained below. In the first coefficient measurement, V 1  is set equal to (K−1)V R /K and V 3  equal to V k  where K is an even number. In that case, a term g 1  is measured. In the second one V 1  is set to (K−1)V R /K, V 2  equal to (K−2)V R /K and coefficient g 1  is obtained. At the K−1 measurement V 1  is set to V R /K, V 2  to 2·V n /K, and it gives g R−1 . Finally V 1  is set to V R /K and V 3  to ground and g k  is obtained.  
         [0072]     Using the following equations: 
 
 g   1   =G   A ·((( K− 1)· V   R   /K )−( C   4   /C   f )· V   R   /K ) 
 
 g   1   =G   A ·((( K− 1)· V   R   /K )−( C   4   /C   f )·(( K− 2)· V   R   /K ))) 
 
 g   3   =G   A ·(( K− 3)·( V   R   /K )−( C   4   /C   f )·(( K− 2)·( V   R   /K ))) 
 
 g   4   =G   A ·(( K− 3)·( V   R   /K )−( C   4   /C   f )·(( K− 4)·( V   R   /K ))) 
 
 g   K−2   =G   A ·((3 ·V   R   /K )−( C   4   /C   f )·(2 ·V   R   /K )) 
 
 g   K−1   =G   A ·(( V   R   /K )−( C   4   /C   f )·(2 ·V   R   /K))  
 
 g   K   =G   A ·( V   R   /K)    (16) 
 
 the term G A (C 4 /C f )V n  is obtained by: 
 
 G   A ( C   4   /C   f ) V   n   =−g   1   +g   2   −g   3   +g   4   − . . . +g   K−2   −g   K−1   +g   K    (17) 
 
         [0073]     The same procedure is repeated for every capacitors where C 4  will replace the one used in the coefficient measurement procedure.  
         [0074]     The reference voltages used in SGM do not need to be accurate because there are eliminated from Eq. (17) and a simple string resistance can be used to measure the gain term. The same string resistance used to generate the references of the SADC could be used.  
         [0075]     If K is chosen to be equal 8, in every coefficient measurement a voltage around V R /8 is injected in the second stage. Injecting such small voltage means that the non-overload range equal V R /2−V R /8 is left for SADC correction. That non-overload range can correct SADC offset up to =(¾)V R /8 instead of =V R /8 in 2.5 b/stage without this method. This will alleviate the comparator requirements compared to other calibration methods where a precise voltage of V R /4 is injected leaving non-overload range of V R /4 and offset correctable range of ±(½)V R /8 (see E. Siragusa and I. Galton, “A digitally enhanced 1.8V 15 b 50 MS/s CMOS pipelined ADC,”  ISSCC Dig. Tech. Papers , pp. 452-453, February 2004). Moreover ilte comparator offset correctable range can increase arbitrarily to approach ±V R /8 by using more reference voltages and by performing more SGM.  
         [0076]     Setting K equal to 8 means 8 calibration cycles are needed to measure every coefficient G A (C i /C f )V R . The addition of the 8 coefficients means that the variance in eq. (15) is now 8 times higher. To obtain the same resolution for the gain as one coefficient measurement, the number of samples in every measurement needs to be 8·N instead of N. Knowing that we need 8 gain measurements so the total number of samples needed is 8·(8·N). To shorten the gain calibration to only one cycle of measurement (e.g. 8·N) the calibration voltages are applied in the following manner. In the first sample V 1  is set equal to (K−1)V R /K and V 2  equal to V N  so the injected coefficient is equal to g 1 . In the second sample, we set V 1  and V 3  to obtain g 1  and so on until injecting the voltage that gives the coefficients g z,999  . After g z,999  , the injected voltages are repeated to obtain g 1  again and so on. In this case the averager output is written as:  
                     Δ   ⁢           ⁢   e     =       ⁢       1   N     ⁢       ∑     k   =   1     N     ⁢     (       D   ⁡     [       V   o     ⁡     (   k   )       ]       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         )                     =       ⁢         1   N     ⁢       ∑     k   =   1     N     ⁢     (       D   ⁡     [     g   1     ]       ·       P     Ns   ⁢           ⁢   1       ⁡     (   k   )       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         )         +   …   +                     ⁢         1   N     ⁢       ∑     k   =   1     N     ⁢     (       D   ⁡     [     g   8     ]       ·       P     Ns   ⁢           ⁢   8       ⁡     (   k   )       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         )         +                     ⁢       1   N     ⁢       ∑     k   =   1     N     ⁢     (       D   ⁡     [       V     o   ⁢           ⁢   1       ⁡     (   k   )       ]       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         )                       (   18   )                       8   ·     E   ⁡     [     Δ   ⁢           ⁢   e     ]         =       ⁢         1   2     ·     (         D   ⁡     [     g   1     ]       ⁢   ⋯     +     D   ⁡     [     g   A     ]         )       +                     ⁢       1   N     ⁢       ∑     k   =   1     N     ⁢     E   ⁡     [       D   ⁡     [       V     o   ⁢           ⁢   1       ⁡     (   k   )       ]       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         ]                       =       ⁢       1   2     ·     D   ⁡     [         G   A     ⁡     (       C   t     /     C   f       )       ⁢     V   R       ]                       (   19   )                       where   ⁢           ⁢     E   ⁡     [         P   Nu     ⁡     (   k   )       ·       P     N   ⁢           ⁢   1       ⁡     (   k   )         ]         =       ⁢       1   16     ⁢           ⁢   and   ⁢           ⁢   the   ⁢           ⁢   variance   ⁢           ⁢   of                     ⁢       Δ   ⁢           ⁢     e   1       =       8   ·   Δ     ⁢           ⁢   e   ⁢           ⁢   is   ⁢     :     ⁢           ⁢     σ     Δ   ⁢           ⁢     e   1       2                         ⁢       8     N   2       ⁢       ∑     t   =   1     N     ⁢     (       E   ⁡     [       D   ⁡     [       V     o   ⁢           ⁢   1       ⁡     (   k   )       ]       2     ]       ·                           ⁢     E   ⁡     [       P     N   ⁢           ⁢   1     2     ⁡     (   k   )       ]       )               =       ⁢       8   N     ⁢     σ     D   ⁡     [     V     o   ⁢           ⁢   1       ]       2                     (   20   )             
 
         [0077]     So to obtain the same resolution as the one coefficient (e.g. g 1 ) measurement N should be multiplied by 2 3  and only one measurement is sufficient to determine G 4 (C i /C f )V R . It will be appreciated that the gain measurement does not need the injection of an accurate analog voltage or an increasing in the SDAC linearity or even splitting up the minimal size capacitor that limit the speed.  
         [0078]     By using the capacitor C 4  instead of C f  to sample the input voltage when φ 1  is high in the modified MDAC, the interstage gain G A ·G C  is now constant despite periodically changing of the capacitor under measurement. Also this modification avoids the need to measure G A  and G A (C i /C f ) separately as indicated in eq. (11). In this embodiment, the term given in eq. (11) is constructed for the modified MDAC of  FIG. 7  in the digital domain by summing the already measured terms G A (C i /C f ) related to every capacitor:  
                     D   ⁡     [     G   1     ]       =       ⁢     D   ⁡     [       (       (       C   1     +     C   2     +     C   3     +     C   4       )     /     C   f       )     ·     G   A       ]                   =       ⁢       D   ⁡     [       G   A     ·     (       C   1     /     C   f       )       ]       +     D   ⁡     [       G   A     ·     (       C   2     /     C   f       )       ]       +                     ⁢       D   ⁡     [       G   A     ·     (       C   3     /     C   f       )       ]       +     D   ⁡     [       G   A     ·     (       C   4     /     C   f       )       ]                       (   21   )             
 
 and then the corrected digital output of the ADC is divided by G 1 . In the case of several stages to be corrected, G A  given in eq. (21) will be measured directly multiplied by the new gain of the backend ADC (G z,999  ) where G A =G z,999  ·(1/(1+1/Af)). And then, G 1  is constructed by the same equation given in eq. (21). 
 
 Calibration Duration Shortening 
 
         [0079]     Two techniques that shorten the calibration duration are provided Eq. (15) indicates that the calibration cycles can be shortened by increasing N or by reducing the variance of D[Vol]. The first technique is applicable when an anti-aliasing filter precedes the ADC (e.g. the ADC is not used for under-sampling) and that only the first stage of the ADC needs to be calibrated. In this case, this filter could be made to provide a 0 power at the frequency f z,999  /2. In this case, P N  could be alternate between +1 and 0 periodically to modulate the calibration term at f z,999  /2 as shown in  FIG. 10 . That will eliminate the interference between the calibration term and the full-scale spread input signal and that will reduce the number of samples needed.  
         [0080]     It will be appreciated that The residue or residual voltage D[Vol] occupies an identified frequency range during normal operation. The injecting of the calibration signal involves alternating between no injecting and injecting of the calibration signal from measurement to measurement at a frequency resulting in the measurable change in D[Vol] having a frequency outside of the identified frequency range. The measuring of the change uses filtering of the residue D[Vol] to detect the change at the frequency outside of said frequency range. This gives the value of the change in D[Vol] without long averaging. Since the frequency range of the ADC input can occupy any or all of the range of the ADC, the frequency range can be detected during operation. It can then be determined whether there is a suitable frequency resulting in the measurable change having a frequency outside of the frequency range of D[Vol]. If there is such a suitable frequency then a filter is advantageously to obtain the measure of the change more quickly. If not, then the change is measured by obtaining an average of the output residue with the calibration signal injected and an average of the output residue without the calibration signal injected. The change is then a difference between the two averages, and the injecting is done in a random or pseudorandom manner, so that the averages are free of aliasing.  
         [0081]     When the ADC has no empty spectrum to modulate the calibration signal on it, the input signal will be spread all over the bandwidth when multiplied by a pseudo-random P N  sequence. Knowing that the input signal is preferred to be full-scale to maximize the dynamic range, the input variance can be decreased by subtracting Vol from eq. (15). To calibrate a multibit per stage pipelined ADC, the input to be subtracted is the input of the stage under calibration and not necessarily the input signal (except for the first stage). Usually a multibit per stage pipetined ADC has front-end stages resolving several bits (e.g 2.3 or 3.5) and a backend constituted from 1.5 b/stages as shown in  FIG. 1 . In this embodiment, the backend ADC and the SADC for the stages under calibration are used to predict the variance of Vol during the normal operation of the ADC. Knowing that the accuracy required from the backend ADC is relaxed and also knowing that the stages in the backend are configured as 1.5 b/stage, this backend can be run at double speed without the need for additional overhead (see  FIG. 11 ).  
         [0082]     When stage 2 is undergoing calibration in one cycle, the backend ADC is connected to the input of stage 2 (Cal=1) to estimate the input signal V z,999  . In the next period, the backend ADC performs its normal operation for the whole ADC. V z,999  is sampled at f z,999  while the backend is operating at 2·f z,999  that means that this voltage is constant during the 2 operations.  
         [0083]     The value obtained by backend ADC during the normal operation of the ADC is: 
 
 V   z,999 2   =G   2 ·( V   z,999 1   −V   DAC2 )+Δ V·PN    (22) 
 
         [0084]     If we subtract from V z,999  the value estimated by the backend {circumflex over (v)} z,999  multiplied by 2 2  instead of G 2  and by using the output of SADC to estimate the SDAC output ({circumflex over (V)} z,999  ) multiplied by 2 2  Eq. (22) becomes:  
                     V     res   ⁢           ⁢   2   ⁢   _new       =       ⁢       (         G   2     ·     V     res   ⁢           ⁢   1         -       2   2     ·       V   ^       res   ⁢           ⁢   1           )     +                     ⁢       (         G   2     ·     V     DAC   ⁢           ⁢   2         -       2   2     ·       V   ^       DAC   ⁢           ⁢   2           )     +     Δ   ⁢           ⁢     V   ·   PN                       (   23   )             
 
         [0085]     For capacitor mismatch of ±0.2% and opamp DC gain of 60 dB we find that: 
 
G 2 2 2 ·(1+ε·2 −7 )   (24) 
 
 Where ε is between −1 and +1. 
 
         [0086]     The estimated value {circumflex over (V)} is equal to V-Q(V) where Q(V) is the quantization error between the backend ADC and the ADC formed from stage 2 and the same backend or the error between the estimated output {circumflex over (V)} z,999  of SDAC of stage 2 and V z,999  . Also Var[Q(V)] Var[V]/2 2h  where the precision of the backend is 10-bit.  
         [0087]     From eq. (23), the variance σ z,999    2  of the output of the averager Δe can be estimated by:  
               σ     Δ   ⁢           ⁢   e     2     =       1       2   10     ⁢   N       ⁢     σ     D   ⁡     [   Vol   ]       2               (   25   )             
 
         [0088]     Thus the number of samples needed without this signal subtraction is divided by 2 z,999 0 . That means, for ADC with 14-bit resolution, instead of requiring a number of 2 30  iterations now only 2 20  iterations are sufficient. That shortens the calibration cycle by 1000.  
         [0089]     After calibration of stage 2, stage 1 is calibrated using the same manner. The residue obtained from the stage 1 in the normal operation of the ADC is given by: 
 
 V   res1   =G   1 ·( V   in   −V   DAC1 )+Δ V·PN    (26) 
 
         [0090]     Again to reduce the variance of the G 1 ·(V z,999  −V DAC1 ) the terrn V z,999  could be estimated using the already calibrated stage 2 and the following stages but that means that stage 2 need to run at double speed and that is not desirable. Instead the same backend used to predict V z,999  is now used to predict V in  as shown in  FIG. 7 . The control signal (cal) switches the input of the backend to the input of the stage 1. The other term V DAC1  is replaced by estimated value from SADC of stage 1 obtained during the normal operation.  
         [0091]     As described above, global gain correction GGC equalizes the gain mismatch in the channels of TIADC&#39;s. For offset mismatch compensation, a chopper-based background calibration is known in the art, for example in S. M. Jamal, D. Fu, S. H. Lewis, and P. J. Hurst, “A 10-bit 120 M sample/s time-interleaved analog-to-digital converter with digital background calibration,”  IEEE J. Solid - State Circuits , vol. 37, pp. 1618-1627, December 2002. In this method, the input signal is converted to a white signal by a random chopper at the input. The output for each channel will contain little information at DC in addition to the offset and then a low-pass filter is used to extract the offset from every channel. The extraction of the offset is inaccurate especially when a full-scale input signal is spread so its power at DC is significant. To accelerate the extraction cycles the same backend used to shorten the calibration cycles for the ADC linearity could be used to predict the input signal before chopping as shown in  FIG. 12 . Thus instead of low-pass filtering the ADC output given by: 
 
 D[V   c1   ]=V   in1   ·P   N1   +V   ox1    (27) 
 
 the offset is extracted from the output given by: 
 
 D[V   c1     —     new ]=( V   in1   −{circumflex over (V)}   in1 )·P N1   +V   z,999    ·P   N1   +V   os1    (28) 
 
 where V z,999  is the offset of the backend ADC and {circumflex over (V)} in1  is the input signal estimated by the ADC&#39;s backend. Though the backend offset will be spread and it may have some component at DC but this spreading will slightly influence the offset extracting compared to the case where the full-scale analog input V in1  is spread and that will accelerate greatly the calibration cycles. 
 
       RESULTS  
       [0092]     Simulations have been performed to verify the effectiveness of these background calibration techniques on a 14-bit pipelined ADC. This ADC has two 2.5-bit front-end stages and a backend pan of nine 1.5-bit stages. A capacitor mismatch of ±0.2%, comparator offsets of ±V R /10, and opamp DC gain of 60 dB were used in all the stages. The reference voltages for each flash sub-ADC and the calibration voltages circuit were generated by a simulated resistor ladder wherein each resistance was chosen with a random error of ±0.2% standard deviation. Only the 2 front-end 2.5-bit stages were calibrated. Without any special consideration to shorten the calibration cycles a number of samples around 2 31  for the coefficients measurement (K=8) were needed. When the backend ADC and the SADC of the stage under calibration are used to shorten the calibration duration, the number of samples are shortened to 2 21 . A similar number of samples were needed when the input signal was supposed to have 0 power at fs/2 frequency and when the coefficient to be measured were shifted at this frequency.  
         [0093]     A sinewave slightly lower that the full-scale signal around 1/20 the sampling frequency (f s ) was applied to the input of the 14-bit ADC before and after calibration. The signal-to-noise-and-distortion ratio (SNDR) is 64 dB resulting in an effective number of bits (ENOB) of 10.3 bits, and the spurious free dynamic range (SFDR) is 68.4 dB. The SNDR becomes 84 dB resulting an ENOB of 13.7 bits, and the SFDR is increased to 98 dB.  
         [0094]     A 2-channel time-interleaved ADC was simulated before and after GGC. The 2 channels have the same configuration of the one used in the foregoing simulation and that were already calibrated by the proposed method and offset mismatch subtracted by shortening the calibration cycles as described above. Before GGC, the SNDR was 71 dB resulting an effective number of bits ENOB of 11.5 bits, and the SFDR was 74 dB. The SNDR became 82 dB resulting in an ENOB of 13.3 bits, and the SFDR was increased to 91 dB.  
         [0095]     It will be appreciated that in the above described embodiments, there is provided a digital background calibration technique to compensate for the nonlinearity and the interstage gain error of the internal SDAC, amplifier finite DC gain and reference voltage inaccuracy in multi-bit/stage pipelined ADC. By injecting subtractive imprecise voltages (SIV) in a modified conventional multi-bit multiplying digital-to-analog converter (MDAC) and performing correlation based successive coefficient measurements (SCM), a background calibration is performed. Global gain correction of the ADC is also provided, and it is feasible to shorten the calibration duration. Simulation results demonstrate the effectiveness, of the above embodiments.  
         [0096]     It will also be appreciated that the invention is not limited to calibration of components in an MDAC, but can be applied to other circuits in which the output of a first circuit or stage in which the components to be calibrated are found is measured by a second circuit or stage. It will also be appreciated that the invention can be used to calibrate a voltage reference to be used in a precise-voltage based application circuit.  
         [0000]     Calibration of a Voltage Reference  
         [0097]     In the embodiment of  FIG. 8C , the invention is used to calibrate a voltage reference using the already calibrated pipelined ADC, so that a precision-voltage circuit  65  can make use of the calibration of the voltage reference.  
         [0098]     In this embodiment, the ratio of the resistances in a string-resistor  60  used to calibrate the ADCs or used by any other circuits integrated in the same chip is identified. To simplify the teaching of this embodiment, the string resistance  60  presented in  FIG. 9  is redrawn in  FIG. 13  with K=4 and equation 16 is rewritten as follows: 
 
 g   1   =G   A ·( V   R3 −( C   4   /C   f )· V   R )   (29.1) 
 
 g   2   =G   A ·( V   R3 −( C   4   /C   f )· V   R2 )   (29.2) 
 
 g   3   =G   A =( V   R1 −( C   4   /C   f )· V   R2 )   (29.3) 
 
 g   4   =G   A   ·V   R1    (29.4) 
 
         [0099]     The term G A (C 4 /C f )V n  is obtained independently from the resistance values using: 
 
 G   A ( C   4   /C   f ) V   R   =−g   1   +g   2   −g   3   +g   4    (30) 
 
         [0100]     Now by repeating the eqs (29) by choosing the voltages in the manner written in the following equations: 
 
 g   1   =G   A ·( V   R −( C   4   /C   f )· V   R3 )   (31.1) 
 
 g   2   =G   A ·( V   R2 −( C   4   /C   f )· V   3 )   (31.2) 
 
 g   3   =G   A ·( V   R2 −( C   4   /C   f ) ·V   R1 )   (31.3) 
 
 g   4   =−G   A ·( C   4   /C   f )· V   R1    (31.4) 
 
         [0101]     The term G A ·V R  is obtained by: 
 
 G   A   ·V   R   =g   1   −g   2   +g   3   −g   4    (32) 
 
         [0102]     By replacing (32) in (29.1) we obtain G A ·Y R3  which is the needed V R3  multiplied by G A .  
         [0103]     Now by dividing G A ·V R3  by (32) we obtain V R3 /V R =a (33) independently from G A .  
         [0104]     By replacing (31.4) in (31.3) we obtain G A ·V R2 =g 3 −g 4 .  
         [0105]     Now by dividing G A ·V R2  by (32) we obtain V R2 /V R =b (34) independently from G A .  
         [0106]     From (29.4) we have G A ·V R1 . Again by dividing The latter value by (32) we obtain V R1 /V R =c (35).  
         [0107]     It will now be shown how to find a digital ratio between V R  and V Rt  . . . i∈{1,2,3}, as performed by the Resistor/Voltage Ratio Estimator  62  shown in  FIG. 8C .  
         [0108]     The equations (33)-(35) can also be used directly to obtain the resistances values compared to R T =R 1 +R 2 +R 3 +R 4  by using the following equations. 
 
 R   1   /R   T   =c    (36) 
 
( R   1   +R   2 )/ R   T   =b  then  R   2   /R   T   =b−c    (37) 
 
( R   1   +R   2   +R   3 )/ R   T   =c  then  R   3   /R   T   =a−b    (38) 
 
         [0109]     To obtain R a /R T  we can switch the left side of R 1 , in  FIG. 1 . a , to V R  and the right side of R 4  to the ground and compute (29.4) again as: 
 
 g   4-new   =G   A   ·V   R1-new    (39) 
 
         [0110]     By dividing (39) by (32) we obtain V R1-new /V R =R 4 /R T =d (40).  
         [0111]     Moreover, we can find all the resistance compared to R 1  as: 
 
 R   2   /R   1 =( b−c )/ c    (41) 
 
 R   3   /R   1 =( a−b )/ c    (42) 
 
 R   4   /R   1   =d/c    (43). 
 
         [0112]     The equations (33-35) can be used to trim the voltage values compared to V R . In addition (36-38) or (41-43) can be used to trim the ratio between the resistances.  
         [0113]     This string-resistance can be used in different applications such as resistor-string-DAC ( FIG. 14 ) and R/2R-DAC ( FIG. 15 ) or any other circuits that relies on high precision resistances and reference voltages. In the case of a resistor-string-DAC and R/2R-DAC the trimming of the resistance values is carried out without interrupting the operation of the DACs.  
         [0114]     Since, the sting-resistances are available for the DAC&#39;s usage and the Calibrating ADC (calibrated using the method of the preferred embodiment), digital values corresponding to a,b,c, . . . etc are used to modify the digital input b 1  the DAC (see  FIG. 15 ) by corrective digital coefficients to compensate the non-linearity in the DAC-analog output due to the resistor mismatch.  
         [0115]     In other applications, such as operational amplifier, gain stage or filter (see  FIG. 16 ), the string resistances are not available to normal use and calibration. In this case, control switches c 1 , c 2  are used to configure the circuits between the calibration phase and the normal operation phase. For instance when c 1 =1 and c 2 =0 the string resistance is configured in trimming mode. When c 1 =0 and c 2 =1 the circuit is configured in the normal operation mode.  
         [0116]     Also, the reference voltages used in the injection could be generated not only from string resistance but also from reference voltages of different analog blocks  66  (see  FIG. 8C ) that their outputs will converted to digital values after signal processing. Digital coefficients could be found to take into consideration the mismatch between these voltages V R1 ,V R2  and V R  in order to compensate the effect of the reference voltage mismatch.  
         [0117]     Also, passive trimming is not exclusive for resistor-based circuits. Capacitive based circuits could be calibrated also. For instance, the voltage used in this subtractive injection could be generated directly from a charge capacitive DAC, as shown in  FIG. 17 . In this case, the DAC output V p  can be used instead of V 1  and V 2  in order to find corrective coefficient to compensate the DAC-nonlinearity due to the capacitor mismatch.  
         [0118]     It will be appreciated that these equations can be used not only to determine the ratio of the resistances or voltages in the digital domain but also to trim the resistances or the capacitors values in a feedback manner using an adaptive algorithm (e.g. LMS). A matrix of passive element is used in parallel of the passive element used in the circuit to perform the trimming in the analog domain as shown in  FIG. 18 .  
         [0119]     First the difference between voltage to be trimmed V R1 (R 2 ) and V R  is found using the Background Calibrated ADC as G A ·(V R−V   R1 (n)). The latter term is divided by G A ·V R  and subtracted from the desired value (V R −V R1     —     z,999  )/V R . An error signal e(n) is used to update the coefficients of an LMS filter. The negative feedback in the circuit will help the convergence of G A ·(V R −V R1 (n)) to the desire value (V R −V R1     —     z,999  )/V R .  
         [0000]     Calibration of a Sample and Hold Circuit in a Flash ADC  
         [0120]     The invention can be applied to calibrate other circuits such as a sample-and-hold (S/H) circuit to correct gain error, for example. A prior art S/H is shown in  FIG. 19  where the output voltage is given by:  
               V   a     =         1     1   +     1   /   Af         ·       C   1       C   f       ·     V   1       =       G   A     ·     G   C     ·     V   1                 (   44   )             
 
         [0121]     Gain error correction due to capacitor and finite op-amp gain is essential for S/H&#39;s, especially when they are used in time-interleaved applications.  
         [0122]     For calibration purposes, the front-end S/H circuit according to this embodiment of the invention is changed as shown in  FIG. 20 . In this case, there is no need to add a capacitor to perform voltage subtraction. Instead, the sign of the input signal V 1  is monitored using a comparator and a voltage equal to V R  is injected without affecting the dynamic range of the S/H as shown in  FIG. 21   a . Here, V 1  is chosen to be equal to ground and V 2 =sign(V 1 )·V R  where sign(V 1 )=−1 when V 1  is positive and sign(V 1 )=1 when V 1  is negative. In this case, the S/H output will be given by: 
 
 V   o   =G   A ·G C ·( V   1   −PN ·sign( V   1 )· V   R )   (45) 
 
         [0123]     Using one comparator to compare V 1  with the ground and to find sign(V 1 ) may lead to distortion in the S/H transfer function when the comparator is not accurate as shown in point A in  FIG. 21   b  where V o  exceeds the reference voltage V R . Therefore, instead of using an accurate comparator, two imprecise comparators are used. One comparator compares V 1  with  
       -       V   R     4         
 
 and the other compares V 1  with  
         V   R     4       
 
 Thus, the voltage V 2  is chosen equal to sign(V 1 )·V R  when  
         V   1     ≥         V   R     4     ⁢           ⁢   or   ⁢           ⁢     V   1       ≤     -         V   R     4     .           
 
 Otherwise, V 2  is chosen equal 0 by forcing PN to be 0 (see  FIG. 21   c ). In this case, an offset in every comparator as large as  
         V   R     4       
 
 is tolerated without overloading the S/H output. 
 
         [0124]     The output of the S/H V o  is correlated with PN·sign(V 1 ) in the background to extract the gain G A ·G C  of the S/H. A multiplication by 1/G A ·G C  for the final output of the ADC will compensate the gain error resulting from the S/H circuit.