Abstract:
A semiconductor device for use in a sense amplifier of a memory circuit includes a first load, a second load, third loads and first and second enhancement-type transistors. The first enhancement-type transistor is connected between the first load and the third loads and receives a data signal. The second enhancement-type transistor is connected between the second load and the third loads and receives a reference voltage. The reference voltage is compensated for by a temperature-compensating circuit so that the reference voltage is changed in accordance with a change in temperature.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device for use in a sense amplifier of a memory circuit. Particularly, it relates to a differential amplifier for amplifying the difference in potential between a data signal and a reference voltage. 
     2. Description of the Prior Art 
     Generally, in a metal-oxide semiconductor (MOS) static memory circuit, a sense amplifier and an output buffer are provided at the output portion thereof. The sense amplifier usually consists of one or more stages of differential amplifiers, including a differential amplifier for amplifying the difference in potential between a data signal and a reference voltage. 
     The conductance g m  of an MOS transistor decreases as the temperature increases. Therefore, a high level, i.e., an on-output level, of the output buffer, obtained from an output of the differential amplifier, has a negative temperature coefficient. A change in the on-output level of the output buffer creates a serious problem in a circuit such as an emitter-coupled logic (ECL) circuit. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a semiconductor device for use in a sense amplifier in which a reference voltage is changed in accordance with a change in the temperature of the device, thereby stabilizing the on-output level of an output buffer. 
     The above-mentioned object can be achieved, according to the present invention, by a sense amplifier circuit which includes first, second and third loads, and first and second enhancement-type transistors. The first enhancement-type transistor is connected between the first and the third loads and receives a data signal. The second enhancement-type transistor is connected between the second and the third loads and receives a reference voltage. The reference voltage is compensated for by a temperature-type compensating circuit so that the reference voltage is changed in accordance with a change in temperature. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the following description made with reference to the accompanying drawings wherein: 
     FIG. 1 is a graph illustrating an example of the margin between ECL levels; 
     FIG. 2 is a circuit diagram illustrating an embodiment of the semiconductor device according to the present invention; 
     FIG. 3 is a circuit diagram illustrating another embodiment of the semiconductor device according to the present invention; 
     FIG. 4 is a graph illustrating the characteristics of the reference voltage V REF  of FIG. 2 and FIG. 3; and 
     FIG. 5 is a graph illustrating the characteristics of the on-output V OH  of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As is illustrated in FIG. 1, in an ECL circuit, two levels, i.e., a high level V OH  and a low level V OL , are used. The low level V OL  increases slightly as the temperature increases. On the other hand, the high level V OH  increases greatly as the temperature increases. The semiconductor device according to the present invention is used for generating signals for an ECL circuit having bi-level signals, as is shown in FIG. 1. 
     In FIG. 2, which illustrates an embodiment of the present invention, C OO  designates a memory cell, WL O  designates a word line, BL O  and BL O  designate bit lines, Q LO   and Q&#39; LO  designate load transistors, Q BO  and Q&#39; BO  designate column selection transistors selected by a column selection signal Y O , DB and DB designate data bit or bus lines, SA designates a sense amplifier, and OB designates an output buffer. 
     V cc  designates a first power supply and its potential and V ss  designates a second power supply and its potential. For an ECL level circuit, V cc  is the ground level and V ss  is -5.2 volts while for a transistor-transistor logic level, V cc  is +5 volts and V ss  is the ground level. 
     The memory cell C OO  comprises resistors R 1  and R 2 , cross-coupled driver transistors Q 1  and Q 2 , and transfer transistors Q 3  and Q 4 . 
     The sense amplifier SA comprises a first differential amplifier DA 1 , a second differential amplifier DA 2 , and a temperature-compensating circuit CP 1 . The first differential amplifier DA 1  comprises depletion-type load transistors Q 11  and Q 12  connected to the power supply V cc , enhancement-type input transistors Q 13  and Q 14  for receiving the data signals of the data bit lines DB and DB, and enhancement-type load transistors Q 15  and Q 16  connected between the input transistors Q 13  and Q 14  and the power supply V ss . The second differential amplifier DA 2  has the same configuration as the first differential amplifier DA 1 . That is, the elements Q 21  through Q 26  of the second differential amplifier DA 2  correspond to the elements Q 11  through Q 16  of the first differential amplifier DA 1 . The first differential amplifier DA 1  detects and amplifies the difference in potential between the data bit lines DB and DB, while the second differential amplifier DA 2  detects and amplifies the difference in potential between an output SD of the first differential amplifier DA 1  and a reference voltage V REF  to transmit its outputs D and D to the output buffer OB. 
     The reference voltage V REF  is changed by the temperature-compensating circuit CP 1 , which comprises resistors R 1 , R 2  and R 3 , and an enhancement-type transistor Q 27 . 
     The circuit of FIG. 2 is operated by making the potential at the word line WL O  high so as to turn on the transfer transistors Q 3  and Q 4  and by simultaneously or subsequently making the column selection signal Y O  high so as to turn on the transistors Q BO  and Q&#39; BO . In this state, if the transistors Q 1  and Q 2  are in an on state and in an off state, respectively, the potential at the node N 1  is low and the potential at the node N 2  is high, and, accordingly, the potential at the bit line BL O  is low and the potential at the bit line BL O  is high. In addition, the potential at the data bit line DB is low and the potential at the data bit line DB is high. The difference in potential between the data bit lines DB and DB is detected and amplified by the first differential amplifier DA 1 . 
     Next, the difference in potential between the output SD of the first differential amplifier DA 1  and the reference voltage V REF  is detected and amplified by the second differential amplifier DA 2 , whose outputs D and D are transmitted to the gates of the transistors Q 31  and Q 32  of the output buffer OB, respectively. Therefore, if the potential of the output D is low and the potential of the output D is high, the potential of the output D OUT  is low. This low potential is referred to as V OL . Contrary to this, if the potential of the output D is high and the potential of the output D is low, the potential of the output D OUT  is high. This high potential is referred to as V OH . In this case, the low potential V OL  and the high potential V OH  of the output D OUT  are determined by the ratio of the conductance g m  of the transistor Q 31  to that of the transistor Q 32 . 
     Therefore, even if the high potential of the output D and the low potential of the output D are definite, when the temperature increases, the high potential V OH  of the output D OUT  decreases. This is because the conductance g m  of each of the transistors Q 31  and Q 32  decreases as the temperature increases. Thus, the reduced high potential V OH  creates a disadvantage in an ECL circuit which has the characteristics shown in FIG. 1. 
     According to the present invention, the above-mentioned disadvantage is eliminated since the reference voltage V REF  is increased by the temperature-compensating circuit CP 1  as the temperature increases. 
     The temperature-compensating circuit CP 1  will now be explained in more detail. Since the potential at the node N 3  between the resistors R 2  and R 3  is almost constant regardless of the temperature, the gate potential of the transistor Q 27  is also almost constant. In the transistor Q 27 , when the temperature increases, the conductance g m  of the transistor Q 27  decreases so as to increase the saturation voltage between the drain and source of the transistor Q 27 , i.e., the reference voltage V REF  indicated by the line A in FIG. 4. The line B in FIG. 4 indicates the reference voltage V REF  of the prior art. 
     Therefore, in the second differential amplifier DA 2 , the difference in potential between the output SD and the reference voltage V REF  increases as the temperature increases. As a result, the high potential of the output D becomes high and the low potential of the output D becomes low. Therefore, in the output buffer OB, the transistor Q 31  is fully controlled in the on direction while the transistor Q 32  is fully controlled in the off direction. 
     Thus, the decrease in the conductance g m  of the transistor Q 31  due to the increase in temperature is compensated for by the increase in the gate potential applied to the transistor Q 31 . Accordingly, the high potential V OH  of the output D OUT  never decreases and has a positive temperature coefficient, as is shown by the line E in FIG. 5. The line F in FIG. 5 shows the temperature coefficient of the prior art. 
     In FIG. 3, which illustrates another embodiment of the present invention, a temperature-compensating circuit CP 2 , comprising a resistor R&#39; 1  and a depletion-type transistor Q&#39; 27 , is used as the temperature-compensating circuit CP 1  of FIG. 2. This depletion-type transistor Q&#39; 27  is manufactured by the same process as the transistors Q 11 , Q 12 , Q 21 , and Q 22 . 
     A change in the reference voltage V REF  of the temperature-compensating circuit CP 2  due to a change in temperature is made in the same as that of the temperature-compensating circuit CP 1 . In addition to temperature compensation, the embodiment of FIG. 3 has an advantage in that fluctuation of the conductance g m  of each of the depletion-type transistors Q 21  and Q 22  is compensated for. That is, if the conductance g m  of each of the transistors Q 21  and Q 22  decreases due to fluctuations in the manufacturing process, the high potential of the output D decreases. As a result, the high potential V OH  of the output D OUT  decreases and the low potential V OL  of the output D OUT  increases. However, in this embodiment, the conductance g m  of the transistor Q&#39; 27  also decreases so as to increase the reference voltage V REF . As a result, the high potential of the output D becomes high and the low potential of the output D becomes low. Thus, fluctuation of the conductance g m  of the transistors Q 21  and Q 22  due to the manufacturing process is compensated. 
     Note that the characteristics of a depletion-type transistor are greatly dependent upon the process for ion-implanting impurities in a channel area of an enhancement-type transistor to change the transistor from an enhancement-type transistor to a depletion-type transistor. As was explained above, in the embodiment of FIG. 3, the depletion-type transistor Q&#39; 27 , which is manufactured by the same process as the transistors Q 21  and Q 22 , enables the fluctuation of the manufacturing process to be compensated. 
     As explained hereinbefore, according to the present invention, the reference voltage V REF  of the differential amplifier DA 2  increases as the temperature increases. As a result, the difference between the high potential of the output D and the low potential of the output D of the differential amplifier DA 2  can be increased, and, accordingly, when the outputs D and D are used in the output buffer OB, the high potential V OH  of the output D OUT  is never decreased.