Abstract:
A voltage controlled transconductor (VCT) for receiving a differential input signal comprising a first voltage signal and a second voltage signal, and for providing a differential output signal comprising a first output current signal and a second output current signal. The VCT includes a first side transconductor circuit having two parts of the same construction, the first part being capable of conducting a first current signal and the second part being capable of conducting a second current signal, the first current signal and the second current signal being controlled by the first voltage signal. The VCT also includes a second side transconductor circuit having two parts of the same construction, the first part being capable of conducting a third current signal and the second part being capable of conducting a fourth current signal, the third current signal and the fourth current signal being controlled by the second voltage signal. A first control circuit is adapted to control the first and second current signals of the first side transconductor circuit, while a second control circuit is adapted to control the third and fourth current signals of the second side transconductor circuit. The first side transconductor circuit is connected to the second side transconductor circuit to provide the first output current signal comprising a difference of the second current signal and the third current signal and to provide the second output current signal comprising a difference of the first current signal and the fourth current signal.

Description:
TECHNICAL FIELD OF THE INVENTION 
     This invention relates to fully differential voltage controlled transconductors, and more particularly relates to such transconductors that operate at low voltage with highly linear performance and wide input and control ranges. 
     BACKGROUND OF THE INVENTION 
     Voltage controlled transconductors are used in a wide range of applications, for example in active filters circuits-such as Gm-C filters-multipliers and oscillators. Detailed descriptions of their construction and principles of operation are readily available. For example, see Analog Integrated Circuit Design, by David A. Johns and Ken Martin, John Wiley &amp; Sons, New York© 1997, pages 605-607. FIG. 1 shows a representative prior art voltage controlled transconductor (VCT) circuit that is based on the linear mode of operation of MOSFETs. As is known, linear mode based transconductors provide better performance than saturation mode transconductors. The circuit comprises transistors M 1  through M 9  and operational amplifiers  101 ,  102  and  103 , interconnected as shown. The circuit provides differential output currents Io+ and Io− in response to a differential input voltage Vid which is superimposed on a constant common-mode voltage signal Vcm. The drain-to-source voltages (Vds) of input transistors M 1  and M 2  are held to a control voltage Vc to control the current flowing into transistors M 1  and M 2 , thereby controlling the transconductance of the entire circuit. 
     In applications where high precision is required, a VCT circuit like that of FIG. 1 can provide less than adequate performance in certain key areas. For example, such a circuit may not be truly fully differential. In other words, the absolute values of gm+ and gm− may not be exactly the same. In addition, such a circuit suffers from nonlinearities in currents Io+ and Io−. That is, the values of gm+ and gm− are functions of Vid, instead of being constants. These nonlinearities and that the circuit is not truly differential can be understood because the theoretical circuit operation is based on the ideal behavior of MOSFET transistors in the linear mode, which does not take into account the second order effects and the non-idealities. 
     Another problem is that the range of the control voltage Vc may be insufficient to provide an adequately robust and controlled performance. This is because in the circuit of FIG. 1 if a wide input range is needed then the control voltage range must decrease in order to keep transistors M 1  and M 2  in the linear mode of operation, and vice versa, which is a disadvantage at low supply voltages. 
     Finally, the VCT circuit of FIG. 1 requires a third operational amplifier  103 , for the common mode input Vcm. The common mode itself must be extracted from the input signal, which needs an extra circuit, as well. 
     It is therefore desirable to have a VCT circuit that overcomes some or all of the above-described problems. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention there is provided a voltage controlled transconductor (VCT) for receiving a differential input signal comprising a first voltage signal and a second voltage signal, and for providing a differential output signal comprising a first output current signal and a second output current signal. The VCT includes a first side transconductor circuit having two parts of the same construction, the first part being capable of conducting a first current signal and the second part being capable of conducting a second current signal, the first current signal and the second current signal being controlled by the first voltage signal. The VCT also includes a second side transconductor circuit having two parts of the same construction, the first part being capable of conducting a third current signal and the second part being capable of conducting a fourth current signal, the third current signal and the fourth current signal being controlled by the second voltage signal. A first control circuit is adapted to control the first and second current signals of the first side transconductor circuit, while a second control circuit is adapted to control the third and fourth current signals of the second side transconductor circuit. The first side transconductor circuit is connected to the second side transconductor circuit to provide the first output current signal comprising a difference of the second current signal and the third current signal and to provide the second output current signal comprising a difference of the first current signal and the fourth current signal. 
    
    
     These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a representative prior art voltage controlled transconductor (VCT) circuit. 
     FIG. 2 is a circuit diagram of a VCT circuit in accordance with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The numerous innovative teachings of the present invention will be described with particular reference to the presently preferred exemplary embodiments. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses and innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit the invention, as set forth in different aspects in the various claims appended hereto. Moreover, some statements may apply to some inventive aspects, but not to others. 
     To better understand the embodiments of the present invention described herein, it is useful to understand the circuit of FIG. 1 in more detail. In the circuit of FIG. 1, assuming linear mode of operation,              l1   =     K        [         (     Vcm   +     Vid   2     -   Vt     )        Vc     -       Vc   2     2       ]               Eq   .                (   1   )                 l2   =     K        [         (     Vcm   -     Vid   2     -   Vt     )        Vc     -       Vc   2     2       ]               Eq   .                (   2   )                 lcm   =     K        [         (     Vcm   -   Vt     )        Vc     -       Vc   2     2       ]               Eq   .                (   3   )                     lo        +     =   lcm     -   l2     =       K   2        VidVc             Eq   .                (   4   )                     lo        -     =   K1     -   lcm     =       K   2        VidVc             Eq   .                (   5   )                 gm   +=     gm   -=       K   2        Vc               Eq   .                (   6   )                                  
     where Vid is the differential input voltage, Vcm is the common mode voltage of the input, Vc is the control voltage, gm+ is the positive side output transconductance, gm− is the negative side output transconductance, Vt is the threshold voltage of the NMOS transistors M 1 , M 2  and M 7 , K is the transconductance factor μ n C ox (W/L) for transistors M 1 , M 2  and M 7  in their triode region, I 1  is the current through transistor M 1 , I 2  is the current through transistor M 2 , Icm is the current through transistor M 7 , Io+ is the positive side output current and Io− is the negative side output current. In the transconductance factor, W is the width and L is the length of the channel, μ n  is the average electron mobility in the channel, and C ox  is the gate oxide capacitance per unit area, for the transistor. 
     Now, it was mentioned above that certain problems exist with this circuit. That is, the absolute values of gm+ and gm− may not be exactly the same. In addition, the range of the control voltage Vc may be insufficient to provide an adequately robust and controlled performance. Further, the VCT circuit of FIG. 1 requires a third operational amplifier  103 , for the common mode input Vcm. And finally, the linearity of the output currents Io+ and Io− may be inadequate. 
     Regarding the problem of the limitation of the range of the control voltage, note that Equations (1) through (6) assume the ideal linear mode of operation for transistors M 1 , M 2  and M 7 . However, for this to be the case, the condition              Vc   &lt;     Vcm   -     Vid   2     -   Vt             Eq   .                (   7   )                                  
     must be met. However, this implies that if a wide input range is needed then the control range must decrease, and vice versa, which is a disadvantage at low supply voltages. 
     Regarding the problem that the linearity of the output currents Io+ and Io− may be inadequate, in order to understand this, second order effects must be considered. Equations (1) through (7) assume that in the linear mode of operation the current is linearly proportional to the gate-to-source voltage (Vgs), i.e., perform according to the ideal MOSFET current formula. However, that is not very accurate, especially for short channel transistors. In order to model the nonlinearity with respect to the Vgs for a MOSFET, the current equation for the linear mode of operation could be written:              Id   =     K        [         (       (     Vgs   +     α                   Vgs   2       +       α   1          Vgs   3       +   …                )     -   Vt     )        Vds     -       Vds   2     2       ]               Eq   .                (   8   )                                  
     where Id is the drain current, Vgs is the gate-to-source voltage, Vds is the drain-to-source voltage and α is a process dependent parameter. Other symbols are as defined above. Since the cubic and higher order terms are very small, they can be discarded for the purpose of this analysis. Equation (8) then becomes:              Id   =     K        [         (       (     Vgs   +     α                   Vgs   2                    )     -   Vt     )        Vds     -       Vds   2     2       ]               Eq   .                (   9   )                                  
     Using the formulation set forth in Equation (9), Equations (1) through (6) can be expressed as follows:              l1   =     K        [         (       (     Vcm   +     Vid   2       )     +       α        (     Vcm   +     Vid   2       )       2     -   Vt     )        Vc     -       Vc   2     2       ]               Eq   .                (   10   )                 l2   =     K        [         (       (     Vcm   -     Vid   2       )     +       α        (     Vcm   -     Vid   2       )       2     -   Vt     )        Vc     -       Vc   2     2       ]               Eq   .                (   11   )                 lcm   =     K        [         (       (   Vcm   )     +       α        (   Vcm   )       2     -   Vt     )        Vc     -       Vc   2     2       ]               Eq   .                (   12   )                     lo        +     =   lcm     -   l2     =     K        [       (       Vid   2     +       α        (       2      Vcm     -     Vid   2       )            Vid   2         )        Vc     ]               Eq   .                (   13   )                     lo        -     =   K1     -   lcm     =     K        [       (       Vid   2     +       α        (       2      Vcm     +     Vid   2       )            Vid   2         )        Vc     ]               Eq   .                (   14   )                   gm        +     =       ∂               ∂   Vid          lo     +=       K        [       1   2     +     2      α                 Vcm     -       α   4        Vid       ]          Vc             Eq   .                (   15   )                   gm        -     =       ∂               ∂   Vid          lo     -=       K        [       1   2     +     2      α                 Vcm     +       α   4        Vid       ]          Vc             Eq   .                (   16   )                                  
     Equations (15) and (16) aid in understanding all of the problems mentioned above in connection with the circuit of FIG.  1 . First, the values of both gm+ and gm− are dependent on the value of Vid, which introduces nonlinearity to the output. This nonlinearity increases the total harmonic distortion in the output. If a specific linearity performance is required, then the input range must be limited to a small value. 
     Second, note that gm+ and gm− are not equal, and neither are the absolute values of Io+ and Io−. This means that the circuit is not truly fully differential. This introduces common mode distortion in the output. 
     Third, regarding the problem of the control voltage range, Equations (15) and (16) assume that both transistors M 1  and M 2  are in the linear mode of operation, the condition for which is set forth in Equation (7). Therefore, with high magnitude differential input signals, the linear control voltage range is limited to the value set forth in Equation (7), as described above. In many applications, the linearity of the transconductance with respect to the control voltage is not very important, but, instead, the range of control the control voltage has over the transconductance is more important. In order to aid in understanding how the transconductance is affected when the control voltage is higher than the value set forth in Equation (7), consider such a case in which there is a positive differential voltage. In that case, transistor M 1  will continue to be in the linear mode of operation, while transistor M 2  will enter the saturation mode of operation. The current equation for transistor M 2  is set forth in the following equation:              l2   =       K   2            (     VCM   -     Vid   2     -   Vt     )     2               Eq   .                (   17   )                                  
     Thus:                gm        +     =       ∂               ∂   Vid          lo     +=       K        (     Vcm   -     Vid   2     -   Vt     )                     and             Eq   .                (   18   )                     gm        -     =       ∂               ∂   Vid          lo     -=       K        (       1   2     +     2      α                 Vcm     +       α                 Vid     4     -   Vt     )                     Vc                          Eq   .                (   19   )                                  
     As Equations (18) and (19) show, the transconductance of the positive output is saturated and does not depend on Vc, which means that it cannot be controlled any further, while the transconductance of the negative output, although it is dependent on Vid, but it can still be controlled with Vc. This means that in order for the two outputs to be fully differential, the control voltage range must always be limited to the value stated in Equation (18). Otherwise, one current output will be changing with Vc, while the other output will, be constant, which is a very undesirable performance. 
     Fourth, as mentioned above, a third operational amplifier  103  must be used to generate the ICM current, and extra circuitry must be used to extract the common mode voltage, which increases the size and power consumption of the transconductor circuit. 
     FIG. 2 is a circuit diagram of an embodiment of a VCT circuit in accordance with a preferred embodiment of the present invention. In this circuit, NMOS transistors M 1  and M 5  and PMOS transistor M 9  are connected in series between the supply voltage V DD  and ground, NMOS transistors M 3  and M 7  and PMOS transistor M 11  are connected in series between the supply voltage V DD  and ground, NMOS transistors M 2  and M 6  and PMOS transistor M 10  are connected in series between the supply voltage V DD  and ground, and NMOS transistors M 4  and M 8  and PMOS transistor M 12  are connected in series between the supply voltage V DD  and ground, all as shown. A first operational amplifier  201  is connected to receive a control voltage Vc at its non-inverting input, while its inverting input is connected to the common connection node of transistors M 1  and M 5 . The output of the first operational amplifier  201  is connected to the gates of transistors M 5  and M 7 . A second operational amplifier  202  is connected to receive the control voltage Vc at its non-inverting input, while its inverting input is connected to the common connection node of transistors M 2  and M 6 . The output of the second operational amplifier  202  is connected to the gates of transistors M 6  and M 8 . The positive side of a differential input voltage Vid is connected to the, gates of transistors M 1  and M 3 , while the negative side of a differential input voltage Vid is connected to the gates of transistors M 2  and M 4 . The gates of transistors M 9  and M 12  are connected together and to the common connection node of transistors M 8  and M 12 . The gates of transistors M 10  and M 11  are connected together and to the common connection node of transistors M 7  and M 11 . The positive side of an output current node providing current Io+ is connected to the common connection node of transistors M 6  and M 10 . The negative side of an output current node providing current Io− is connected to the common connection node of transistors M 5  and M 9 . 
     The VCT circuit of FIG. 2 is based on the circuit of FIG. 1, but is modified in accordance with the principles of the present invention to significantly increase the linearity of the transconductor by making both gm+ and gm− independent of Vid. The modification also makes the circuit truly differential by making gm+ and gm− equal for the entire input range and the entire control range. Further, the modification also significantly increases the voltage control range by making both gm+ and gm− proportional to Vc, even when the input transistors M 1  and M 3 , or M 2  and M 4 , enter the saturation region. Still further, the modification eliminates the need for a third operational amplifier and for a common mode extraction circuit, which saves power and integrated circuit area. 
     In the circuit of FIG. 2, the positive side input transconductor stage, or circuit, comprising transistors M 1 , M 5 , and M 9 , is provided in duplicate form. That is, corresponding transistors M 3 , M 7 , and M 11 , are provided, being of substantially the same construction as transistors M 1 , M 5 , and M 9 , respectively, with the gates of transistors M 1  and M 3  being connected together and to the positive side of the differential input voltage Vid, and the gates of transistors M 5  and M 7  being connected together and to the output of operational amplifier  201 . The negative input side input transconductor stage, or circuit, comprising transistors M 2 , M 6 , and M 1  , is similarly provided in duplicate form. That is, corresponding transistors M 4 , M 8 , and M 12 , are provided, being of substantially the same construction as transistors M 2 , M 6 , and M 1  , respectively, with the gates of transistors M 2  and M 4  being connected together and to the negative side of the differential input voltage Vid, and the gates of transistors M 6  and M 8  being connected together and to, the output of operational amplifier  202 . In addition, transistors M 9  and M 12  are connected together in a current mirror configuration, and, similarly, transistors M 10  and M 11  are connected together in a current mirror configuration. 
     In the positive side of the input stage, since transistors M 1  and M 5  are connected in a cascode configuration, and transistors M 3  and M 7  are also connected in a cascode configuration, then if transistors M 5  and M 7  operate in the saturation region, a condition that can be met by properly sizing transistors M 9 , M 10 , M 11  and M 12 , the output impedance at the drains of both transistors M 5  and M 7  is substantially high. The consequence of this is that the drain voltages of transistors M 5  and M 7  have a very small effect on the values of the currents I 1  and I 3 , respectively. Since transistors M 5  and M 7  are constructed to be substantially identical, and they have the same gate voltage, then the currents I 1  and I 3  are identical if the source voltages of transistors M 5  and M 7  are identical. Furthermore, since transistors M 1  and M 3  are constructed to be substantially identical, and they have the same Vgs, and further since they both operate in the linear mode, then the currents I 1  and I 3  are identical if the drain voltages of transistors M 1  and M 3  are identical. Now, assuming that current I 3  is less than current I 1 , then the source voltage of transistor M 7  (which is the same as the drain voltage of transistor M 1 ) will have to be higher than the source voltage of transistor M 7  (which is the same as the drain voltage of transistor M 3 ). However, having a higher drain voltage on transistor M 1  means that current I 3  will be higher than current I 1 , which contradicts the assumption. Furthermore, assuming that current I 1  is less than current I 3 , then the source voltage of transistor M 5  (which is the same as the drain voltage of transistor M 1 ) will have to be higher than the source voltage of transistor M 7  (which is the same as the drain voltage of transistor M 3 ). However, having a higher drain voltage on M 1  means that current I 3  will be higher than current I 1 , which, again, contradicts the assumption. Thus, the only stable condition for the circuit occurs when the currents I 1  and I 3  flowing in transistors M 1  and M 3 , respectively, are substantially equal, and when the source voltages of transistors M 5  and M 7  (which are the same as the drain voltages of transistors M 1  and M 3 , respectively), are also substantially identical. In other words, a virtual short circuit between the drains of transistors M 1  and M 3  is established. Since operational amplifier  201  sets the drain voltage of transistor M 1  at Vc, the voltage at the drain of transistor M 3  is also set at Vc. This guarantees that the control voltage Vc is controlling the drains of both transistors M 1  and M 3 , and that the currents I 1  and I 3  are identical, without the need for an extra operational amplifier to force Vc on the drain of transistor M 3 . 
     The same considerations apply to the negative side of the input stage. Thus, since transistors M 2  and M 6  are connected in a cascode configuration, and transistors M 4  and M 8  are also connected in a cascode configuration, then if transistors M 6  and M 8  operate in the saturation region, a condition that can be met by properly sizing transistors M 9 , M 10 , M 11  and M 12 , the output impedance at the drains of both transistors M 6  and M 8  is substantially high. The consequence of this is that the drain voltages of transistors M 6  and M 8  have a very small effect on the values of the currents I 2  and I 4 , respectively. Since transistors M 6  and M 8  are constructed to be substantially identical, and they have the same gate voltage, then the currents I 2  and I 4  are identical if the source voltages of transistors M 6  and M 8  are identical. Furthermore, since transistors M 2  and M 4  are constructed to be substantially identical, and they have the same Vgs, and further since they both operate in the linear mode, then the currents I 2  and I 4  are identical if the drain voltages of transistors M 2  and M 4  are identical. Now, assuming that current I 4  is less than current I 2 , then the source voltage of transistor M 8  (which is the same as the drain voltage of transistor M 4 ) will have to be higher than the source voltage of transistor M 6  (which is the same as the drain voltage of transistor M 2 ). However, having a higher drain voltage on transistor M 4  means that current I 4  will be higher than current I 2 , which contradicts the assumption. Furthermore, assuming that current I 2  is less than current I 4 , then the source voltage of transistor M 6  (which is the same as the drain voltage of transistor M 2 ) will have to be higher than the source voltage of transistor M 8  (which is the same as the drain voltage of transistor M 4 ). However, having a higher drain voltage on M 2  means that current I 4  will be higher than current I 2 , which, again, contradicts the assumption. Thus, the only stable condition for the circuit occurs when the currents I 2  and I 4  flowing in transistors M 2  and M 4 , respectively, are substantially equal, and when the source voltages of transistors M 6  and M 8  (which are the same as the drain voltages of transistors M 2  and M 4 , respectively), are also substantially identical. In other words, a virtual short circuit between the drains of transistors M 2  and M 4  is established. Since operational amplifier  201  sets the drain voltage of transistor M 2  at Vc, the voltage at the drain of transistor M 4  is also set at Vc. This guarantees that the control voltage Vc is controlling the drains of both transistors M 2  and M 4 , and that the currents I 2  and I 4  are identical, without the need for an extra operational amplifier to force Vc on the drain of transistor M 4 . 
     The following equations help to show with even more clarity how the inventive improvements to the VCT circuit of FIG. 2 improve the linearity, control voltage, and input range of the transconductor. Using Equation (9):              l1   =     l3   =     K        [         (       (     Vcm   +     Vid   2       )     +       α        (     Vcm   +     Vid   2       )       2     -   Vt     )        Vc     -       Vc   2     2       ]                 Eq   .                (   20   )                 l2   =     l4   =     K        [         (       (     Vcm   -     Vid   2       )     +       α        (     Vcm   -     Vid   2       )       2     -   Vt     )        Vc     -       Vc   2     2       ]                 Eq   .                (   21   )                                  Io+=I   3 − I   2 = K [(1+2 αVcm ) VidVc]   Eq. (22) 
     
       
           Io−=I   1 − I   4 = K [(1+2 αVcm ) VidVc]   Eq. (23) 
       
     
     
       
         
           
             
               
                 
                   
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                     ( 
                     25 
                     ) 
                   
                 
               
             
           
         
                 
         
             
         
      
     
     Comparing Equations (22) through (25), it can be seen that both the positive and negative current outputs, as well at the positive and negative transconductances are equal for the VCT circuit of FIG.  2 . These equalities show that the circuit is, indeed, truly fully differential, and has reduced common mode distortion as well as offsets that occur when Io+ and Io− are not equal. Further, these equations show that the transconductances of the circuit of FIG. 2 are constant with respect to the differential input, which can be contrasted the circuit of FIG. 1, as shown in Equations (15) and (16). Since the circuit of FIG. 2 has constant transconductances, the output currents Io+ and Io− are linear with respect to differential input. This significantly reduces the total harmonic distortion, as compared with prior art circuits. If a certain amount of error in the transconductances, i.e., nonlinearity in the output currents, is acceptable, the circuit of FIG. 2 provides a much wider differential input range for the same amount of error than the circuit in FIG.  1 . 
     Now, in order to understand how the improvements in the VCT circuit of FIG. 2 extend the control range as well, consider the condition where transistors M 2  and M 4  enter the saturation mode of operation. This means that:              Vc   &lt;     Vcm   -     Vid   2     -   Vt             Eq   .                (   27   )                 l2   =     l4   =       K   2          [       (     Vcm   -     Vid   2     -   Vt     )     2     ]                 Eq   .                (   28   )                   gm        +       =           ∂               ∂   Vid          lo        +     =       K   2          [     Vcm   -     Vid   2     -   Vt     ]         +       K        [       1   2     +     α        (     Vcm   +     Vid   2       )         ]          Vc               Eq   .                (   29   )                   gm        -       =           ∂               ∂   Vid          lo        -     =       K   2          [     Vcm   -     Vid   2     -   Vt     ]         +       K        [       1   2     +     α        (     Vcm   +     Vid   2       )         ]          Vc               Eq   .                (   30   )                                  
     Comparing Equations (29) and (30) with Equations (18) and (19), Equations (29) and (30) shown that for high values of Vc when some of the transistors go into the saturation region, the transconductances, although dependent on Vid, still can be controlled by Vc linearly. This is very beneficial, especially at low supply voltages, e.g., 1.8 volts or lower. Equations (29) and (30) also show that both gm+ and gm− are equal, thereby maintaining the fully differential nature of the circuit, even when the transistors enter the saturation region of operation. 
     Thus, the present invention provides an approach to design voltage controlled transconductors with improved linearity by splitting the respective sides of the differential transconductor into two identical circuits and connecting them together such that the current of the duplicate circuit of one side is subtracted from the current of the primary circuit of the other side to produce the respective differential output currents. The improved linearity enables a high differential input range as well as a high control voltage range with a low supply voltage. The approach enables this high performance by substantially eliminating second order effects in linear mode based transconductors. The approach also eliminates the need for an extra operational amplifier and common mode extraction circuitry, which saves power and integrated circuit area without compromising the high performance. VCT circuits designed in accordance with the principles of the present invention may be used in any application calling for a VCT circuit requiring highly linear performance, for example in Gm-C filters. The voltage controlled performance also makes such circuits tolerant to process variations, e.g. RC constants. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.