Abstract:
A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.

Description:
FIELD OF THE INVENTION 
   The present invention pertains to the field of circuit design in integrated circuits. More particularly, the present invention relates to a clocking circuit for helping to reduce or prevent skew, metastability, dither, and jitter in the clock distribution network. 
   BACKGROUND OF THE INVENTION 
   Most integrated circuits such as a microprocessor consist of multiple circuit elements fabricated on a semiconductor material such as silicon. Generally, a clock signal is routed to many, if not most, of the circuit elements. This clock signal is used for the timing of the circuit elements. 
   The current trends in integrated circuit design are toward smaller device dimensions, higher levels of integration, and higher operating frequencies. Unfortunately, these trends tend to increase clocking inaccuracies. In order to meet narrowed timing requirements associated with higher operating frequencies, it would be desirable to not only prevent increased clocking inaccuracies, but to decrease clocking inaccuracies. Thus, generating and distributing highly accurate and stable clocks on a large integrated die present a challenge. 
   One method to manage and lower clock inaccuracies is to incorporate a Digital De-skew System (DDS) in the-global clock distribution of an integrated circuit. The integrated circuit die is typically divided into domains. A DDS is then inserted between domains to dynamically or statically lower the clock skew between them. A DDS typically consists of phase detectors, buffer control circuits, and adjustable buffers distributed throughout a clock distribution structure.  FIG. 1  shows an example of such a DDS in a global clock distribution of an integrated circuit. The phase detectors  110 – 116  measure the phase error between two clocks and generate lead/lag signals depending on the relationship between the two clocks. The lead/lad signals are then processed by buffer control circuits which control the adjustable buffers  128 – 133 ,  143 ,  145 ,  155 – 157 ,  159 – 161 . 
   Existing DDS&#39; typically suffer from at least three problems. A first problem is that the generated delays from the adjustable buffers are not linear.  FIG. 2  shows a graph of an output  215  of a nonlinear delay buffer. The y-axis  205  represents adjustable delay steps of the buffer measured in picoseconds. The x-axis  210  represents control bits that adjust the buffer. In order to achieve stability and convergence within a DDS, the delay steps of the buffer should be linear. Output  215 , however, is not linear; delay steps gradually decrease as the control bit value asserted increases. Nonlinearity decreases the controllable delay range of the buffer. 
   A second problem is metastability and dither. Metastability may occur when a phase detector detects two perfectly aligned incoming clocks under ideal conditions. In contrast, dither may occur when the phase detector detects a phase difference between two clocks, but the delay step is too large to correct the difference between the two clocks. Thus, the phase error between the two clocks toggle around an equilibrium point. 
   A third problem is jitter when updates occur. Jitter is any cycle to cycle variation in a clock. In general, the larger the change in generated delays, the larger the resulting clock jitter. 
   Therefore, it would be desirable for a DDS to generate linear delays having a wide controllable delay range, detect phase differences without being susceptible to metastability and dither, and prevent large sudden changes in generated delays. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
       FIG. 1  is a diagram of a prior art Digital De-Skew System in an integrated circuit clocking scheme; 
       FIG. 2  is a graph of a prior art delay buffer; 
       FIG. 3  is a diagram of a modified Digital De-Skew System in an integrated circuit clocking scheme; 
       FIG. 4  is a diagram of a circuit for generating linear adjustable delays; 
       FIG. 5A  is a graph of an output signal of a delay buffer; 
       FIG. 5B  is a graph of an output signal of a delay buffer having inverted control bits; 
       FIG. 5C  is a graph of an ideal output signal of a circuit that combines a first delay buffer and a second delay buffer having inverted control bits; 
       FIG. 5D  is a graph of a simulation output of a circuit that combines a first delay buffer and a second delay buffer having inverted control bits; 
       FIG. 6  is a diagram of a phase detector that helps to prevent metastability and dither; 
       FIG. 7  is a graph of signals from the phase detector; and 
       FIG. 8  is a NOR gate used in the phase detector. 
   

   DETAILED DESCRIPTION 
   In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. 
     FIG. 3  depicts one embodiment of a modified DDS as taught by the present invention designed to help provide linearly adjustable delay buffers, prevent dither and metastability, and reduce jitter. Phase detector  305  receives two clocks of a clock distribution network as input and compares the two clocks. The clock distribution network may comprise a plurality of clock buffers  335 . Depending on the phase relationship between input clocks, phase detector  305  generates lead/lag signals that are coupled to a buffer control circuit  315 . Phase detector  305  is shown in  FIG. 6  and is discussed in further detail below. The buffer control circuit  315  generates binary signals that increase or decrease step delays of adjustable delay buffers  320  and  340 . The adjustable delay buffers  320  and  340  may then be coupled to clock distribution buffers  335 . For one embodiment of the invention, buffer control circuit  315  is a shift register. For another embodiment of the invention, buffer control circuit  315  is an up/down counter. 
   Phase detector  305  is also coupled to a digital sampling filter  310 . The digital sampling filter  310  controls the sampling of clocks by the phase detector  305  to ensure system stability. For one embodiment of the invention, the digital sampling filters  310  may be a divider circuit that masks out a fraction of the input clock edges. The digital sampling filter  310  is discussed in further detail below. 
   A scan register  325  is coupled to the buffer control circuit  315  to provide test functionality to the system. The scan register  325  is thus only enabled in a testing mode. The DDS may enter testing mode when either a load register signal or a load control circuit signal is asserted. If the load register signal is asserted, data is read from the DDS. Otherwise, if the load control circuit signal is asserted, data is written to the DDS. A test clock input, Tclk, determines the speed in which data is read from or written to the DDS during testing mode. 
     FIG. 4  depicts one embodiment of a DDS that generates linearly adjustable delays. As shown in  FIG. 2 , buffers in integrated circuits often generate delays which are not linear over the entire adjustable range. Linear delay steps, however, help to achieve system stability and convergence. In  FIG. 4 , clock adjustment circuit  330  comprises a digital sampling filter, a phase detector, and an up/down counter. The clock adjustment circuit  330  is coupled to delay buffers  430  and  440 . Delay buffers  430  and  440  are coupled to a plurality of clock buffers  450 . 
   The clock adjustment circuit  330  receives as input two clock signals from a clock distribution network of an integrated circuit. Ideally, the two input clock signals are aligned with respect to one another. If there is a skew or phase error between the two incoming clocks, clock adjustment circuit  330  generates binary control signals to increase or decrease the step delay of delay buffers  430  and  440 . For one embodiment of the invention, inverter  420  inverts the control signal coupled to delay buffer  440 . The control signal coupled to delay buffer  430  is not inverted. As a result, if the delay of delay buffer  430  is increased, the delay of delay buffer  440  is decreased. Further, if the delay of delay buffer  430  is decreased, the delay of delay buffer  440  is increased. 
     FIGS. 5A ,  5 B, and  5 C depict graphs of the operation of the DDS of  FIG. 4  that generates linearly adjustable delays. Specifically,  FIG. 5A  is a graph of the output signal generated by delay buffer  430 . X-axis  510  represents the adjustable control bits of delay buffer  430  and y-axis  515  represents the step delay of each asserted control bit as measured in picoseconds. Signal  520  is the output delay of delay buffer  430 . As shown by  FIG. 520 , the step delay gradually decreases with each increased control bit asserted. 
   Similarly,  FIG. 5B  is a graph of the output signal generated by delay buffer  440 . X-axis  530  represents the adjustable control bits as controlled by circuit adjustment circuit  330 . Y-axis  535  represents the step delay as measured in picoseconds. Signal  540  is the output delay output of delay buffer  440 . However, because the control bits of delay buffer  440  is inverted with respect to the control bits of delay buffer  430 , as the number of control bits  510  enabled is increased, the step delay of each additional control bit gradually increases with respect to the previously asserted control bit as shown by the signal  540 . 
   Therefore, when signals  520  and  540  are combined or used in conjunction with one another as in  FIG. 5C , the resulting generated delay between the buffers  430  and  440  is linear as shown by signal  560 . The x-axis  550  represents the control bits asserted by clock adjustment circuit  330  and the y-axis  555  represents the step delay of combined delay buffers  430  and  440  as measured in picoseconds. 
     FIG. 5D  depicts a graph of actual simulation results of the buffer of  FIG. 4 . X-axis  570  represents the adjustable control bits as controlled by clock adjustment circuit  330 . Y-axis  575  represents the step delay as measured in picoseconds. Signal  580  is the effective delay change of delay buffers  430  and  440 . When compared with  FIG. 2 , it can be seen that the graph of linearity of the step delays have been improved. Moreover, since each step delay has been increased, the delay range has also been widened. 
   Even though the circuit of  FIG. 4  helps to provide linear step delays, the circuit on its own may still be susceptible to dither. As discussed above, dither occurs when the step delay adjustments are too large to correct the difference between two clocks causing the phase error to toggle around an equilibrium point. As an example, clk 1  and clk 2  are two input clocks to a phase detector  305  as shown in  FIG. 3 . There is a skew between clk 1  and clk 2 , wherein clk 1  leads clk 2  by two picoseconds. The phase detector  305  is coupled to an up/down counter  315 , which generates a binary control signal. The control signal adjusts delay buffers  430  and  440  to compensate for the skew. However, the delay buffer has a step delay of three picoseconds. Therefore, after correction, clk 2  will lead clk 1  by one picosecond. Because the step delay of the delay buffers are greater than the actual clock skew, the DDS is in dither. Thus, in this example, the phase error between the clocks toggle between 2 picoseconds and minus one picosecond. 
     FIG. 6  depicts one embodiment of a phase detector circuit  305  used to help prevent dither. The circuit comprises NAND combinational gates  610 ,  620 ,  630 , and  640  and NOR combinational gates  650  and  660  of  FIG. 8 . NAND gates  610  and  620  are coupled to each other and to NOR gates  650  and  660 . NAND gates  630  and  640  are coupled to each other and to NOR gates  650  and  660 . As stated above, two clocks are input to the phase detector  305 . For reference, the input clocks are named clk 1  and clk 2  in this instance. NAND gates  620  and  630  are sized slower to emulate a delayed copy of clk 1  and clk 2 , referred to as clk 1   d  and clk 2   d.    
   Using the previous example where clk 1  leads clk 2  by two picoseconds, signals  710  and  720  of  FIG. 7  depict the relationship between clk 1  and clk 2 . Moreover, clk 1   d  and clk 2   d  are also depicted as signals  730  and  740 . The phase detector of  FIG. 6  compares the rising edges of clocks clk 1  with clk 2   d  and clk 2  with clk 1   d . The phase detector  305  then generates lead/lag signals (lead 1 , lag 1 , lead 2 , and lag 2 ) from NAND gates  610 ,  620 ,  630 , and  640  respectively. Lead 1  is asserted if clk 1  leads clk 2   d ; lag 1  is asserted if clk 1  lags clk 2   d ; lead 2  is asserted if clk 1   d  leads clk 2 ; and lag 2  is asserted if clk 1   d  lags clk 2 . 
   The amount of delay (e.g. the delay of clk 1   d  with respect to clk 1  and clk 2   d  with respect to clk 2 ) created by the sizing of NAND gates  620  and  630  establishes a dither control threshold. Thus, if clk 1  and clk 2  skews are within the threshold, then neither lead or lag signals are asserted and the buffers  430  and  440  do not change delays. The lead signal output from NOR gate  650  is asserted only if both lead 1  (clk 1  leads clk 2   d ) and lead 2  (clk 1   d  leads clk 2 ) signals are both asserted indicating clk 1  is leading clk 2  by at least the delay threshold. 
   Likewise, the lag signal output from NOR gate  660  is asserted only if both lag 1  (clk 1  lags clk 2   d ) and lag 2  (clk 1   d  lags clk 2 ) signals are both asserted indicating clk 1  is lagging clk 2  by at least the delay threshold. When the skew between clk 1  and clk 2  is less than the threshold, then the lead or lag signal remains low. As a result, a delay threshold is established, which helps to eliminate dither. 
   In the example of  FIG. 7 , the dither control threshold is set to be three picoseconds, the delay threshold is three picoseconds, and clk 1  leads clk 2  by two picoseconds. As a result, lead 1  will be asserted since clk 1  leads clk 2   d . Lead 2 , however, will not be asserted since clk 1   d  does not lead clk 2 . Clk 1   d , in fact, lags clk 2  by one picosecond in this example. Because lead 1  is asserted and lead 2  is not asserted, the lead signal output from NOR gate  650  remains low. The lead and lag signals of phase detector  305  do not change the delay of the buffers  430  and  440  unless the clock skew is measured to be greater than the established delay threshold. 
   In the event that the clock skew is equal to the established delay threshold, metastability could occur at the output of the NAND gates  610 ,  620 ,  630 , and  640 . Metastability is the condition where a circuit node is in neither an asserted state nor a deasserted state. Metastability in a circuit is highly undesirable because the circuit may be unable to generate valid results until the circuit exits the metastable state and enters into a known state. Metastability, however, will only occur in phase detector  305  at either lead 1 /lag 1  or lead 2 /lag 2  because of the introduced delays of NAND gates  620  and  630 . Therefore, at least one input of the NOR gates  650  and  660  will be at a known voltage state. 
   The transistors of the NOR gates  650  and  660  must be sized to ensure that the NOR gate will generate a low signal in the instance where one of the inputs is in a metastable state.  FIG. 8  depicts such a NOR gate. In this circuit, p-transistors  810  and  820  are sized such that n-transistors  830  and  840  have greater transistor widths than p-transistors  810  and  820 . Thus, if an input to NOR gates  650  and  660  is in a metastable state, the NOR gates  650  and  660  will output a low signal since the transistors are sized such that the width of the n-transistors  830  and  840  are greater than the widths of the p-transistors  810  and  820  in addition to the mobility difference between p-transistors and n-transistors. The circuit of  FIG. 8  helps to ensure a known voltage value to be output at the NOR gates  650  and  660  at the expense of slight voltage contention. The voltage contention would be negligible since the p-transistors are significantly weaker than the n-transistors. 
   The negative effects of metastability may also be minimized in a DDS through the use of the digital sampling filter  310 . As stated above, the digital filter  310  controls the sampling of clocks. By periodically sampling input clocks instead of sampling on every rising or falling clock transition, the phase detector  305  is given more time to resolve metastability conditions. In addition, periodic sampling gives the phase detector  305  more time to resolve glitches in input clocks. 
   The digital sampling filter may also be used to stagger the sampling of input clocks through the use of periodic sampling. In a dynamic DDS having multi-levels in the clocking network, all updates typically occur at the same. This potentially creates large changes in delays since all delay buffers are adjusted simultaneously. The large changes in delays can cause clock jitter. Therefore, staggering, or alternating sampling, of different levels of the clocking network help to reduce jitter and improve stability. 
   For one embodiment of the invention, staggered sampling is implemented in the digital sampling filter  310  using a counter. The counter enables the phase detector  305  during only when certain specified counter values are reached. 
   For another embodiment of the invention, staggered sampling is implemented in the digital sampling filter  310  using a control signal generated by a state machine or processor. The state machine or processor controls when the phase detector  305  is enabled. 
   Finally, the digital sampling filter helps to reduce bandwidth. Clock adjustments in a DDS depend upon the several components. Components such the phase detector  305 , up/down counter  315 , and adjustable delay buffers  320  require calculation times. Therefore, a DDS may sample clocks faster than the components can correct. As a result, staggered sampling helps to prevent wasted bandwidth by limiting inputs to be sampled by the phase detector  305 . 
   As stated above, the functionality of the DDS and its components may be placed in a testing mode. For one embodiment of the invention, the buffer control circuit  315  is an up/down counter. The functionality of the up/down counter  315  and adjustable delay buffer  320  may be checked using the scan register  325 . To perform this test, the load control circuit signal is asserted and phase detector  305  and digital sampling filter  310  are disabled. Lead/lag signals, which are generated by the phase detector in normal operation, are not generated in testing mode. Instead, the up/down counter  315  receives inputs from scan register  325 . Values are loaded into scan register  325  serially. The values are then communicated to the up/down counter  315  by asserting the up/down counter&#39;s load control signal. The values provided by the phase detector logic  305  to the up/down counter  315  are ignored. 
   For another embodiment of the invention, the functionality of the phase detector  305  and digital sampling filter  310  may be tested. The load register signal of the up/down counter  315  is asserted. For this embodiment of the invention, the values of the up/down counter  315  are loaded into the scan register  325 . The lead/lag signals are then read from the scan register  325  through a serial output. 
   The scan register  325  may further be used for testing other system functionality not described above. The DDS is placed in testing mode to test the functionality of a component or a plurality of components of the system. At all other times, the DDS remains in an operating mode. 
   In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modification and changes may be made thereto without departure from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.