Abstract:
A memory controller device. The memory controller includes a first circuit to capture a first bit of data in response to a rising edge of a strobe signal and a second circuit to capture a second bit of data in response to a falling edge of the strobe signal. The memory controller device also includes a first register circuit coupled with the first circuit where, in operation, the first register circuit samples the first bit of data from the first circuit in response to a clock signal and is adjustable to select which transition of the clock signal is employed to sample the first bit of data. The memory controller device additionally includes a second register circuit coupled with the second circuit. The second register circuit, in operation, samples the second bit of data from the second circuit in response to the clock signal and is adjustable to select which transition of the clock signal is employed to sample the second bit of data.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 09/638,562, filed on Aug. 14, 2000 now U.S. Pat. No. 6,782,459. The entire disclosure of application Ser. No. 09/638,562 is herein incorporated by reference. 

   FIELD OF INVENTION 
   The present invention relates to memory devices. More specifically, it relates to a read valid window of a synchronous memory device. 
   BACKGROUND OF THE INVENTION 
   Computer systems generally include a memory subsystem that contains memory devices where instructions and data are held for use by a processor of the computer system. Because the processor is typically capable of operating at a higher rate than the memory subsystem, the operational speed of the memory subsystem has a significant impact on the performance of the computer system. 
   In the past, the memory devices making up the memory subsystem, such as Dynamic Random Access Memory (DRAM), were typically asynchronous devices, i.e. the memory devices stored or output data in response to control signals from the processor. However, asynchronous operation results in a delay between the time that a control signal, e.g. a read command and address value, is received by the memory device and the time that the device responds, e.g. the data becomes available at the output of the memory device. This delay between the reception of a control signal and the device response typically lasts for several operational cycles of the processor. During the delay, the processor is typically unable to perform useful functions and the operational cycles are consequently wasted. 
   To avoid wasting operational cycles while waiting for a response from memory, synchronous memory devices, such as synchronous DRAM (SDRAM), have been developed. SDRAM exploits the fact that most memory accesses are sequential and is designed to fetch data words in a burst as fast as possible. SDRAM typically operates by outputting a sequence, or “burst”, of several words or bytes of data in response to a single control signal from the processor. For example, a burst cycle, such as 5-1-1-1, consists of a sequence of four data word transfers where only the address of the first word is supplied via the address bus input to the memory device. The 5-1-1-1 refers to the number of clock cycles required for each word of the burst. In this example, the first word is available at the output of the data device at five clock cycles after the input cycle of the command signal and another word is output by the memory device at each subsequent clock cycle to complete the burst. 
   An SDRAM device typically employs a memory controller through which the processor accesses the DRAM memory cells. When the memory controller receives a data request from the processor, it accesses the rows and columns of the DRAM memory array to access the data and must wait for the data to become available from the DRAM memory array before sending it to the processor. With SDRAM a burst counter in the controller typically allows the column part of the memory address to be incremented very rapidly, which helps speed up retrieval of information in sequential reads considerably. The controller synchronizes the timing of the memory system to the processor&#39;s system clock in order to supply the data words to the processor as fast as the processor can take them. Note that for synchronous memory schemes to function properly, the data words from the DRAM cells must be available and valid at, typically, the rising edge of each clock cycle. 
   Another approach that has been developed to improve memory performance is called double data-rate (DDR), such as is available in DDR DRAM devices. In a DDR DRAM, data during a burst is output on both the rising and falling edge of the clock cycles, which effectively doubles the rate of operational frequency of the memory subsystem. 
   However, in DDR, a data word must be available and valid from the data cells of the memory at both the rising and falling edge of the clock signal driving the memory system. The effect of this is that the performance of the memory subsystem becomes very sensitive to the round-trip delay between the controller and memory. 
     FIG. 1  is a functional block diagram of a memory architecture  10  that illustrates an example of a DDR memory controller  20  according to the conventional art. Memory controller  20  contains a clock generation circuit  22  that generates a clock zero signal CLK 0 . The CLK 0  drives an even clock domain zero register  24  and an odd clock domain zero register  26 . The CLK 0  signal is also output to a DDR DRAM block  90  and arrives at the clock input (CLK) of the DDR DRAM device after a propagation delay time interval t PD , as represented in  FIG. 1  by block  92 . 
   DRAM device  90 , in turn, generates a data output signal at output DQ after a output to clock delay interval t DQCK , which experiences another propagation delay t PD  represented by block  94  and which results in a delayed data signal DQ 1  arriving at the memory controller  20 . After a clock to output delay interval t DQSCK , DRAM device  90  also outputs a data output synchronize signal DQS that is also delayed by propagation delay interval t PD , as represented by block  96 , and results in a delayed version of the DQS signal called DQS 1  that is input to the controller  20 . 
   The DQ 1  and DQS 1  signals are received by a DQS domain circuit  70  of the controller  20 . The DQ 1  signal is input to sample and hold registers  74  and  76 . The DQS 1  signal enters t 1  delay circuit  72 , which results in delayed signal DQS 2 . The rising edge of the DQS2 signal drives sample and hold register  74  and a falling edge of the DQS 2  signal drives sample and hold register  76 , which latch even and odd data words, respectively, of the DQ 1  signal. 
   After a data valid time interval t v , sample and hold register  74  generates data signal DQ 2  which is input to even clock zero domain register  24 , which is clocked on a rising edge of the CLK 0  signal generated by clock generation circuit  22 . Also, after data valid interval t v , sample and hold register  76  outputs a delay data signal DQ 3  to odd clock zero domain register  26  which is clocked on the falling edge of the clock zero signal. 
   In the conventional device shown in  FIG. 1 , the data from the DQ output of the DDR DRAM device  90  must typically be available and valid at the input of the even clock zero domain register  24  within a single clock cycle interval t CC  in order for the memory controller to make the data available at the appropriate time the processor to read the data word. 
     FIG. 2  is a timing diagram illustrating an example of the function of controller  FIG. 1  and illustrating the effect of the delay in the circuit in  FIG. 1  on the setup time t S  for the even and odd clock zero domain register  24  and  26 . Measured from a rising edge of the CLK 0  signal generated by clock zero register circuit  22 , a first propagation delay interval t PD , represented in  FIG. 1  as delay  92 , is received in DRAM device  90  at clock input CLK. From the time that the delayed CLK 0  signal is received at the CLK input of DRAM device  90  to the time that the DQS signal is output involves a delay t DQSCK . The DQS signal is then delayed by another propagation delay interval, represented in  FIG. 1  as delay  96 , that results in the DQS 1  signal that is received by DQS circuit  70 . The DQS 1  signal, in turn, is delayed by time interval t 1  by delay element  72 , which results in the DQS 2  signal. The delay element  96  introduces delay t 1  so that the DQ 1  signal meets the set-up time requirements for registers  74  and  76 . 
   The set-up time for registers  74  and  76  can be derived from the formula
 
 t   Smin   &lt;=t   1min +( t   DQSCKmin   −t   DQCKmax )
 
   which, inserting typical values, produces 0.2 ns&lt;=t 1min −0.5 ns, which, in turn, yields, 0.7 ns&lt;=t 1min . The hold time for registers  74  and  76  can be derived from the formula
 
 t   Hmin   &lt;=t   CHmin +( t   DQCKmin   −t   DQSCKmax )− t   1max  
         where t CHmin  is the minimum clock high cycle time, which is typically one third of the clock cycle t cc . Inserting typical values, this formula produces 0.2 ns&lt;=2.5 ns−0.5 ns−t 1max , which, in turn, yields 1.8 ns&lt;=t 1max .       

   From the rising edge of the DQS 2  signal to the time that the data signal DQ 2  is valid at the output of sample and hold register  74  of  FIG. 1 , is represented by the delay t v . Subtracting the sequence of time delays from the total available time for a single clock cycle period t cc  for setup of the even and odd data output of controller circuit  20 , the maximum round trip propagation delay time that can be tolerated for the even and odd clock zero domain register  24  and  26  can be obtained and is shown in the following equation (1).
 
 t   S,min   &lt;=t   CC,min   −t   PD,max   −t   DQSCK,max   −t   PD,max   −t   1,max   −t   V,max   (1)
 
   By plugging in typical numbers for a clock cycle period of 7.5 nanoseconds (ns) yields:
 
0.2 ns&lt;=7.5 ns−t PD,max −0.75 ns−t PD,max −1.8  ns− 0.25 ns
 
   and
 
t PD,max &lt;=1.75 ns.
 
   The controller circuit  20  of  FIG. 1  also has limitations on the minimal propagation delay due to the minimum hold time required by the even and odd clock zero domain registers  24  and  26 . Equation (2) below illustrates the time requirements introduced by the hold time required in order to latch even and odd words of the DQ signal in registers  74  and  76 .
 
 t   H,min   &lt;=t   PD,min   +t   DQSCK,min   +t   PD,min   +t   1,min   +t   V,min   (2)
 
   Plugging in typical values for these time intervals yields:
 
0.2 ns&lt;= t   PD,min +0.75 ns+ t   PD,min +0.7 ns+0 ns
 
   Which reduces to:
 
0.25 ns&lt;=t PD,min  
 
   Thus, the propagation delay must be in the range of 0.25 ns&lt;=t PD &lt;=1.75 ns in order for the memory system to operate correctly. As the size of memory cores, such as that in DRAM device  90 , become larger and, therefore, require longer access times, and as clock frequencies become faster, resulting in shorter clock cycles and, therefore, less time available for set-up, this constraint can become a significant problem for memory system design. 
   Therefore, the need remains for improved ways for handling propagation delay in high performance memory systems. 
   SUMMARY 
   In a first embodiment of a memory controller, the memory controller includes a first circuit to capture a first bit of data in response to a rising edge of a strobe signal and a second circuit to capture a second bit of data in response to a falling edge of the strobe signal. The memory controller further includes a first register circuit that is coupled with the first circuit and a second register that is coupled with the second circuit. The first register circuit, in operation. samples the first bit of data from the first circuit in response to a clock signal and is adjustable to select which transition of the clock signal is employed to sample the first bit of data. The second register circuit, in operation, samples the second bit of data from the second circuit in response to the clock signal and is adjustable to select which transition of the clock signal is employed to sample the second bit of data. 
   In a second embodiment of a memory controller, the memory controller includes a latch circuit to capture data in response to a strobe signal. The memory controller also includes a register circuit coupled with the latch circuit. The register circuit, in operation, samples the data from the latch circuit in response to a clock signal and is adjustable to select which transition of the clock signal is employed to sample the data from the latch circuit. 
   In third embodiment of a memory controller, the memory controller includes a latch circuit to capture a bit of data in response to a strobe signal and a register circuit, coupled with the latch circuit, to sample the bit of data from the latch circuit in response to a clock signal. In this embodiment, a point of the clock signal at which the bit of data is sampled from the latch circuit is adjustable. In a fourth embodiment of a memory controller, the memory controller includes a first latch circuit to capture a first bit of data in response to a rising edge transition of a strobe signal and a second latch circuit to capture a second bit of data in response to a falling edge transition of the strobe signal. The memory controller of this embodiment also includes a plurality of registers, coupled with the first latch circuit and the second latch circuit, to sample the first bit of data and the second bit of data from the first latch circuit and the second latch circuit in response to a clock signal. A first point of the clock signal at which the first bit of data is sampled is adjustable and a second point of the clock signal at which the second bit of data is sampled is also adjustable. 
   In a fifth embodiment of a memory controller, the memory controller includes means for capturing data in response to consecutive transitions of a strobe signal and means for sampling the data from the means for capturing the data. The means for sampling the data samples the data in response to a clock signal, where a point of the clock signal at which the data is sampled from the means for capturing the data is adjustable. 
   These and other aspects will become apparent to those of ordinary skill in the art by reading the following detailed description, with reference, where appropriate, to the accompanying drawings. Further, it should be understood that the embodiments noted in this summary are not intended to limit the scope of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is described in the context of an embodiment of the invention with reference to the following drawings, wherein: 
       FIG. 1  is a simplified functional block diagram illustrating an example of a conventional controller for a synchronous memory device; 
       FIG. 2  is a timing diagram illustrating an example of the function of the controller of  FIG. 1 ; 
       FIG. 3  is a functional block diagram illustrating an embodiment of a controller circuit for a synchronous memory according to the present invention; 
       FIG. 4  is a timing diagram illustrating an embodiment of the function of the controller circuit of  FIG. 3  when the MODE signal is logical 1; 
       FIG. 5  is a timing diagram illustrating an embodiment of the function of the controller circuit of  FIG. 3  when the MODE signal is logical 0; 
       FIG. 6  is a functional block diagram illustrating another embodiment of a controller circuit for a synchronous memory according to the present invention; 
       FIG. 7  is a timing diagram illustrating an embodiment of the function of the controller circuit of  FIG. 6  for EVEN data when the MODE signal is logical 1; 
       FIG. 8  is a timing diagram illustrating an embodiment of the function of the controller circuit of  FIG. 6  for ODD data when the MODE signal is logical 1; 
       FIG. 9  is a timing diagram illustrating an embodiment of the function of the controller circuit of  FIG. 6  for EVEN data when the MODE signal is logical 0; 
       FIG. 10  is a timing diagram illustrating an embodiment of the function of the controller circuit of  FIG. 6  for ODD data when the MODE signal is logical 0; 
       FIG. 11  is a timing diagram illustrating an embodiment of the function of the controller circuit of  FIG. 6  with respect to the signals generated by an embodiment of the DQS domain circuit of  FIG. 6 . 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The present invention is directed toward a method and apparatus for controlling a read valid window in a synchronous memory device. The present invention permits the sampling point for read data in a memory controller to be adjusted in one half clock cycle increments. 
     FIG. 3  is simplified functional block illustrating an embodiment of a controller circuit  120  for synchronous memory according to the present invention. In controller circuit  120 , a first multiplexer (MUX)  130  selects between a first even data path, composed of registers  132  and  134 , and second even data path, composed of registers  136  and  138 , for capturing and transferring the data of the DQ 2  signal to the EVEN output of MUX  130 . Similarly, a second multiplexer  140  is used to select between a first odd data path, composed of register  142 , and the second odd data path, composed of registers  146  and  148 , for capturing and transferring the data of the DQ 3  signal to the ODD output of MUX  140 . 
   In the first odd data path for the DQ 2  signal, register  134  is driven by the falling edge of the CLK 0  signal generated by circuit  22  and the second register  132  is driven by the rising edge of the clock zero signal. Thus, the first even data path captures a word of the odd data signal DQ 2  on the first falling edge of the CLK 0  signal after a rising edge of the DQS 2  signal and transfers the odd data word to MUX  130  on the subsequent rising edge of the CLK 0  signal. 
   In contrast, the second even data path involves both registers  136  and  138  being driven by the rising edge of the clock zero signal. Thus, if the MODE signal controlling MUX  130  is set to logic one (MODE=1), then the odd data word from DQ 2  is captured at the rising edge of the CLK 0  signal, which is one half of a clock cycle sooner than the first data path that is selected when the MODE signal is set to a logic zero (MODE=0). 
   Along the same lines, register  142  for the first odd data path is driven by a rising edge of the clock zero circuit and captures an odd data word from the DQ 3  signal at the first rising clock edge of the CLK 0  signal after a falling edge of the DQS 2  signal. The second odd data path involves register  148  being driven by the falling edge of the CLK 0  signal while register  146  is driven by the rising edge of the clock zero signal. Therefore, if the second odd data path is selected by MODE=1, then the odd data word is captured one half clock cycle sooner than when MODE=0. 
   By controlling the value of the MODE signal, the data path for data signals DQ 2  and DQ 3  can be adjusted in order to accommodate a proportionally greater propagation delay and still allow the controller to perform valid read operations. The addition of selective delay circuitry, MUXes  130  and  140  and associated data paths, to the CLK 0  domain of circuit  120  allows the controller to move the sampling points for the data received from DRAM device  90  in increments of one half of a clock cycle. Delay magnitudes on the order of increments of clock cycles may be accommodated by sampling the EVEN and ODD outputs after the appropriate rising edge of CLK 0 . The present invention will align data to rising CLK 0  edges and handle clock domain crossing and data misalignment issues. If, for example, the magnitude of the propagation delay requires an additional clock cycle of delay, then the function of the controller may be modified to sample at t 6  instead of t 4 . Similarly, if two additional clock cycles of delay are required to cope with the magnitude of the propagation delay, then the function of the controller may be modified to sample at t 8  instead of t 6  or t 4 . Thus, large propagation delays may be accommodated. 
     FIG. 4  is a timing diagram illustrating the operation of circuit  120  of FIG. a when the value of the MODE signal is set to one, thereby selecting an even data path for DQ 2  through registers  136  and  138  and an odd data path for DQ 3  through registers  146  and  148 . When MODE=1, then the function of controller  120  is similar to that of the conventional device as illustrated in the timing diagram of  FIG. 2 . When MODE=1, the even path for DQ 2  through register  136  and  138  to MUX  130  is selected and the data from the DQ 2  signal is latched at the first rising edge of the second clock cycle of CLK 0 . At the same time, the odd data path for DQ 3  through registers  146  and  148  and to MUX  140  is selected and the DQ 3  signal is latched into register  148  at the first falling edge of the CLK 0  signal after the falling edge of the DQS 2  signal. The addition of MUXes  130  and  140  results in an additional MUX delay time t MUX  in addition to a register output validation time t v . 
     FIG. 5  is a timing diagram illustrating the operation of circuit  120  of  FIG. 3  when the value of the MODE signal is set to zero, thereby selecting an even data path for DQ 2  through registers  132  and  134  and an odd data path for DQ 3  through register  142 . As can be seen from  FIG. 5 , the DQ 2  signal output by sample and hold register  174  is latched by register  134  on the falling edge of the second cycle of the CLK 0  signal and subsequently latched on the rising edge of the CLK 0  signal by register  132 , thereby holding the DQ 2  signal for an additional half a clock cycle before being output on the even line. 
   The DQ 3  signal output from sample and hold register  176  is latched by register  142  and made available on the ODD signal output from MUX  140  one half clock cycle after the DQ 2  signal is available on the EVEN output of the MUX  130 . 
   When operating in MODE=0, the set-up time is described by equation (3) below:
 
 t   S,min   &lt;=t   CC,min   +t   CC,half   −t   PD,max   −t   DQSC,max   −t   PD,max   −t   1,max   −t   V,max   (3)
 
   which, when the numbers used in the example above are used to reduce the equation, yields:
 
0.2 ns&lt;=7.5 ns+3.375 ns− t   PD,max −0.75 ns− t   PD,max −1.8 ns−0.25 ns,
 
   and,
 
t PD,max =&lt;=3.938 ns,
 
   which represents a significantly larger propagation delay that may be handled by the memory system of  FIG. 3 , as illustrated in the longer propagation delays t PD  shown in  FIG. 5 . Note that the MUX delays for MUX  130  and  140  are omitted in the interest of simplicity. 
   However, the hold time requirements are also affected by the selectable delay circuitry of  FIG. 3 . Equation (2) above becomes equation (4) below:
 
 t   H,min   &lt;=t   PD,min   +t   DQSCK,min   +t   PD,min   +t   1,min   +t   V,min   −t   CC,half   (4)
 
   Plugging in typical values for these time intervals yields:
 
0.2 ns&lt;= t   PD,min +0.75 ns+ t   PD,min +0.7 ns+0 ns−4.125 ns
 
   Which reduces to:
 
2.338 ns&lt;=t PD,min  
 
   Thus, the propagation delay that may be accommodated in MODE=0 must be in the range of 2.338 ns&lt;=t PD &lt;=3.938 ns in order for the memory system to operate correctly. The embodiment for a memory controller  120  according to the present invention is able to accommodate greater propagation delay through the round trip between the CLK 0  signal being received by DRAM device  90  and the DQ 1  and DQS 2  being received back from the DRAM device. However, controller  120  leaves a gap between the propagation delays that may be accommodated when MODE=0 and MODE=1. 
     FIG. 6  is a simplified functional block diagram illustrating another embodiment of the controller circuit, according to the present invention, for controlling a synchronous memory device. In controller  220  of  FIG. 5 , the DQ 1  signal is divided by DQS domain circuit  270  into a pair of even data signals DQ 2   0  and DQ 2   1 , latched by synchronous source signals DQSE 0  and DQSE 1 , respectively, and a pair of odd data signals DQ 3   0  and DQ 3   1 , latched by synchronous source signals DQSO 0  and DQSO 1 , respectively. 
   A first even MUX  230  outputs a signal EVEN 0  received from one of two data paths for DQ 2   0 , where the MODE signal selects between a first EVEN 0  data path through registers  232  and  234  and the second EVEN 0  data path through registers  236  and  238 . The second even MUX  240  outputs an EVEN 1  signal received through one of two data paths for DQ 2   1 , where the MODE signal selects between a first EVEN 1  data path through registers  242  and  244  and a second EVEN 1  data path through registers  246  and  248 . 
   Similarly, a first odd MUX  250  outputs an ODD 0  signal received from one of two data paths for DQ 3   0 , where the MODE signal selects between a first ODD 0  data path through register  252  or a second ODD 0  data path through registers  256  and  258 . The second odd MUX  260  outputs an ODD 1  signal received from one of two data paths for DQ 3   1 , where the MODE signal selections between a first ODD 1  data path through register  262  and a second ODD 1  data path through registers  266  and  268 . 
   DQS domain circuit  270  includes multi-cycle source synchronous timing logic (gates  276  and  278 , gates  286  and  288 , toggle register  280  with inverter  281 , and register  290 ) that processes the DQS 1  signal in order to capture the DQ 1  signal output from DRAM device  90  and produces the DQSE 0 , DQSE 1 , DQSO 0  and DQSO 1  signals that latch the DQ 1  signal in sample and hold registers  272 ,  274 ,  282  and  284 , respectively. The DQS 1  signal enters the DQS domain circuit  270  through delay  292 , which delays DQS 1  signal by time delay t 1  in order to produce signal DQS 2 . DQS 2  signal input to logic gates  276 ,  278 ,  286  and  288  and is also input to the clock inputs of registers  280  and  290 . Register  280  is configured to be a toggle register that outputs an ENEVEN signal that is inverted by inverter  281  and input back to register  280 . An asynchronous clear signal ASYNC is generated at initialization of the system to initialize register  280  to a known state. The ENEVEN signal is input to logic gates  276  and  278  where it is combined with the DQS 2  signal in order to generate the signals DQSE 0  and DQSE 1  signals, respectively. 
   Note that it is assumed that the DDR DRAM  90  is a typical DDR device that only generates edges at the DQS output when there is valid read data at the DQ output. If a device is selected that operates differently, i.e. generates edges independent of valid data cycles, then the control logic in the CLK 0  domain must track the state of ENEVEN output from the toggle flip-flop  280 . 
   Register  290  captures the ENEVEN signal value output by register  280  at the falling edge of the DQS 2  signal and outputs an enable odd signal ENODD. The ENODD signal is input to an inverting logic input of logic gate  286 , which logically combines the ENODD and DQS 2  signals to generate the DQSO 0  signal that drives the clock input of register  282 . The ENODD signal is also logically combined with the DQS 2  signal in logic gate  288  in order to produce the DQSO 1  signal that drives the clock input of register  284 . Consequently, registers  282  and  284  capture signal DQ 1  under the control of the DQSO 0  and DQSO 1  signals, respectively, in order to obtain the DQ 3   0  and DQ 3   1  signals that are output to the ODD 0  and ODD 1  outputs from MUXes  250  and  260 , respectively. 
     FIGS. 7 and 8  are timing diagrams illustrating the function of the controller circuit  220  of  FIG. 6  when MODE=1 for EVEN and ODD data, respectively. Similarly,  FIGS. 9 and 10  are timing diagrams illustrating the function of the controller circuit  220  of  FIG. 6  when MODE=0 for EVEN and ODD data, respectively. When MODE=1, the DQ2 0  signal is latched by register  238  at the rising edge t 2  of the second CLK 0  cycle in  FIG. 7 , while, when MODE=0, the DQ 2   0  signal is latched by register  234  at the falling edge t 3  of the second CLK 0  cycle in  FIG. 9  in order to accommodate a larger relative value for t PD . Similarly, when MODE=1, the DQ 2   1  signal is latched by register  248  at the rising edge t 4  of the second CLK 0  cycle in  FIG. 7 , while, when MODE=0, the DQ 2   1  signal is latched by register  244  at the falling edge t 5  of the second CLK 0  cycle in  FIG. 9  in order to accommodate a larger relative value for t PD . 
   Similarly, when MODE=1, the DQ 3   0  signal is latched by register  258  at the falling edge t 3  of the second CLK 0  cycle in  FIG. 8 , while, when MODE=0, the DQ 3   0  signal is latched by register  252  at the rising edge  4  of the third CLK 0  cycle in  FIG. 10  in order to accommodate a larger relative value for t PD . Likewise, when MODE=1, the DQ 3   1  signal is latched by register  268  at the falling edge t 5  of the third CLK 0  cycle in  FIG. 8 , while, when MODE=0, the DQ 3   1  signal is latched by register  262  at the rising edge t 6  of the fourth CLK 0  cycle in  FIG. 10  in order to accommodate a larger relative value for t PD . Because the path through MUXes  250  and  260  when MODE=0 involves only one register, registers  252  and  262 , respectively, the respective ODD data words are not delayed by an additional clock cycle from arriving at outputs ODD 0  and ODD 1 , respectively. 
   Note that the timing diagrams discussed above show multiple transitions in the CLK 0  signal, CLK signal and DQS signal, though the function of the controller  220  is illustrated with respect to a transition for a first data access cycle. The additional transitions pertain to additional data access cycles that are essentially the same as the first data access cycle and the response of controller  220  to these additional transitions is not addressed in order to simplify the diagrams by removing redundant material. 
     FIG. 11  is a timing diagram illustrating how the multi-cycle source synchronous timing logic of DQS circuit  270  functions. Note how each rising and falling edge of the DQS 2  signal results in a rising edge of one of the DQSE 0 , DQSE 1 , DQSO 0  and DQSO 1  signals that latch the DQ 1  signal in sample and hold registers  272 ,  274 ,  282  and  284 , respectively. Responsive to the first rising edge of DQS 2 , the DQSE 0  signal produces a rising edge that latches a first even word of the DQ 1  signal in register  272 . Responsive to the first falling edge of DQS 2 , the DQSO 0  signal produces a rising edge that latches a first odd word of the DQ 1  signal in register  282 . Responsive to the second rising edge of DQS 2 , the DQSE 1  signal produces a rising edge that latches a second even word of the DQ 1  signal in register  274 . Finally, responsive to the second falling edge of DQS 2 , the DQSO 1  signal produces a rising edge that latches a second odd word of the DQ 1  signal in register  284 . The ASYNC signal at initialization clears the ENEVEN signal for initial operation of the controller. The values of ENEVEN and ENODD toggle to control the function of the DQSE 0 , DQSE 1 , DQSO 0  and DQSO 1  signals over two cycles of the DQS 2  signal. 
   Note that the multi-cycle source synchronous timing logic may be further refined. For example, registers  274  and  284  may be configured with inverting clock inputs driven by the DQSE 0  and DQSE 1  signals, respectively. 
   Unlike the circuit of  FIG. 3 , the controller  220  of  FIG. 6  is not constrained as to the holding time because there is an additional sample and hold register for each of the even and odd data from DQ 1 . Each of the first and second sample and hold registers  272  and  274  for the even data latch and hold their data for an additional clock cycle, which allows the range of propagation times that can be accommodated to be larger, but also permits the operational ranges for MODE=0 and MODE=1 to overlap. This makes the transfer of data from the DQS domain to the CLK 0  domain easier and scales more robustly with increasing clock frequency. As before, the valid range for t PD  when MODE=1 is 0&lt;=t PD &lt;=1.75 ns. However, when MODE=0, the valid range is 0&lt;=t PD &lt;=3.938 ns. 
   It should be understood that the programs, processes, methods, systems and apparatus described herein are not related or limited to any particular type of computer apparatus (hardware or software), unless indicated otherwise. Various types of general purpose or specialized computer apparatus may be used along with the present invention or perform operations in accordance with the teachings described herein. 
   In view of the wide variety of embodiments to which the principles of the invention can be applied, it should be understood that the illustrated embodiments are exemplary only, and should not be taken as limiting the scope of the present invention. For example, further refinements to the multi-cycle source synchronous timing logic may be made, and more or fewer elements or components may be used in the logic, as well as different components without departing from the spirit of the present invention. For another example, the controller may be adapted to substitute the edge-triggered registers shown in the drawings with level sensitive latches. In addition, the present invention can be practiced with hardware, or a combination of hardware and software. 
   It should be further noted that the CLK 0  domain registers of the present invention may be “pushed-through” or positioned downstream from the multiplexors in a configuration that reduces the number of registers and, therefore, the number of gates required to implement the present invention. With respect to  FIG. 3 , registers  132  and  136  may be combined into a single register positioned at the output of MUX  130 . Likewise, registers  142  and  146  may be combined into a single register positioned at the output of MUX  140 . Similarly, with respect to  FIG. 6 , registers  232  and  236  may be combined into a single register at the output of MUX  230 , registers  242  and  246  may be combined into a single register at the output of MUX  240 , registers  252  and  256  may be combined into a single register at the output of MUX  250 , and registers  262  and  266  may be combined into a single register at the output of MUX  260 . When the CLK 0  registers are pushed-through the multiplexors, then the MODE signal must be valid one clock cycle earlier than the logic configurations illustrated in  FIGS. 3 and 6 . Thus, the configurations of  FIGS. 3 and 6  have greater margin for error with regard to the timing limitations of the circuit because the variation in the delay introduced by the MUX is dealt with in a separate clock cycle and does not need to be handled downstream. 
   Furthermore, while the present invention is discussed above in the context of accommodating longer propagation delay times, it may also be applied to accommodating shorter propagation delay times. For example, while the discussion above addresses moving the sample point for a first word of even data from t 2  to t 3  by changing the MODE signal from logic 1 to logic 0, such as between  FIGS. 4 and 5  and between  FIGS. 7 and 9 , the same approach may be used to move the sample point from t 2  to t 1 . If the magnitude of t PD  is sufficiently small that the EVEN data is valid within at least a set-up interval t S  before t 1 , then the present invention may be used to capture the EVEN data word at t 1  when MODE=0. However, the controller receiving the data output from the MUXes must have its timing adjusted to receive the data word when it is available from the outputs of the devices  120  and  220  according to the present invention. 
   The claims should not be read as limited to the described order or elements unless stated to that effect. Therefore, all embodiments that come within the scope and spirit of the following claims and equivalents thereto are claimed as the invention.