Abstract:
A process for fabricating a VLSI device comprising trench isolation regions. The trench isolation regions of a VLSI device is fabricated by a process comprising the following steps: Depositing and patterning pad layers on a substrate to form active regions separated from pad-layer-covered regions; forming side walls at each active region to cover portions of the active region other than its central portion; depositing a first oxide at the space surrounded by the side walls and the central portion of the active region; removing the side walls to form trenches at the active region; and depositing a second oxide on the substrate to fill the trenches and cover the first oxide, the second oxide and the first oxide together forming an oxide trench isolation region.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to processes for fabricating very-large-scale integrated (VLSI) circuits, and in particular to a new process for forming line-width-independent self-aligned trench isolations that separate VLSI circuit elements. 
     2. Description of the Prior Art 
     Semiconductor devices are constantly being miniaturized. As both the overall dimensions of semiconductor devices and the lithographic line widths for making such devices are made smaller and smaller hundreds of thousands of integrated circuit (IC) elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are formed within each square centimeter of a semiconductor substrate surface. To prevent these elements from short-circuiting or electronically interfering with one another, isolation regions must be formed at the surface of the substrate to define and separate each of the regions where the IC elements are to be formed. Conventional art for forming such isolation regions include, for example, the use of the local oxidation of silicon (LOCOS) process to form field oxide (FOX) regions, and the shallow trench isolation (STI) process, both of which are well-known to those skilled in the art. 
     As an example of the current state of the conventional art, FIGS. 1A-1G depict various stages of a process that combines the features of LOCOS and STI to form isolation regions on a semiconductor substrate. As shown in FIG. 1A, a pad oxide (e.g., silicon oxide) layer  12  and a pad nitride (e.g., silicon nitride) layer  14  are sequentially formed on a semiconductor substrate  10 . Conventional lithographic and etching techniques are used to remove portions of the pad nitride  14  and the pad oxide  12 , exposing a plurality of surface areas of the substrate. Each such surface area defines an active region  16 . 
     Next, a thin polysilicon (poly-Si) layer  18  is deposited on the substrate, covering the pad nitride layers  14  as well as the active regions  16 . Silicon nitride side walls  20  are then formed on portions of the active region  16  and next to the side walls of the poly-Si-coated pad nitride layers  14 , leaving the central portion of the active region  16  covered only by the poly-Si layer  18 . 
     Next, as shown in FIG. 1B, through a thermal oxidation process, a field oxide region  22 , partly inset in the substrate  10 , is formed at the central portion of the active region  16 . The exposed portions of poly-Si  18 ′ located at the top of the pad nitride are also oxidized as a result of this oxidation process. 
     Next, the silicon nitride side walls  20  are removed by a phosphoric acid etch; see FIG.  1 C. The phosphoric acid etch process is continued until trenches  24  are formed in the substrate  10 ; see FIG.  1 D. Typically, the oxidized side walls of the trenches  24  are further implanted with ions to prevent channeling across the trenches. 
     Subsequently, another poly-Si layer  26  is deposited to fill up the trenches  24 . This second poly-Si layer  26  is back-etched to form the profile shown in FIG.  1 E. The top portion of this poly-Si layer  26  is then oxidized to form silicon oxide  28  as shown in FIG.  1 F. Finally, after pad nitride  14 , pad oxide  12  and the top part of the silicon oxide  28  are removed, the substrate  10  is left with filled trenches  24 , which will function as the isolation regions separating the IC elements to be fabricated on the substrate  10 . 
     Although the aforesaid conventional process for forming isolation regions has enabled the fabrication of IC elements that do not interfere or cross-talk with one another, the constant miniaturization of VLSI devices dictates that additional improvements be made to the formation of these isolation regions. For example, the aforesaid field oxide formation process is very time-consuming and tends to reduce the throughput of the overall process. More important, as the lithographic line width is reduced to 0.25 μm or smaller (i.e., sub-quarter-micron or deep sub-micron), it becomes more and more difficult to control the critical dimensions of the isolation regions through conventional exposure and etching schemes. Device miniaturization also reduces the tolerance for misalignment in lithographic and etching processes involved in conventional trench-formation processes. In short, there is plenty of room for improvement in the fabrication of isolation regions of VLSI semiconductor devices. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a new isolation formation process for forming isolation regions between the circuit elements of the VLSI device. 
     In accordance with the object described above, the present invention provides a method of fabricating oxide trench isolation regions of a VLSI device, which method includes the following processing steps: 
     Depositing and patterning pad layers on a substrate to form active regions separated from pad-covered regions; 
     forming side walls at each active region to cover portions of the active region other than its central portion; 
     depositing a first oxide at the space surrounded by the side walls and the central portion of the active region; 
     removing the side walls and forming trenches at the active region; forming a second oxide on the substrate to fill the trenches and cover the first oxide, the second oxide and the first oxide together forming an oxide trench isolation region; and 
     removing the pad layers. 
     In accordance with the object described above, the present invention provides another method of fabricating isolation regions of a VLSI device, which method includes the following processing steps: 
     Depositing and patterning pad layers on a substrate to form active regions separated from pad-covered regions; 
     forming side walls at each active region to cover portions of the active region other than its central portion; 
     depositing a first oxide at the space surrounded by the side walls and the central portion of the active region; 
     removing the side walls and forming trenches at the active region; 
     depositing polysilicon on the substrate to fill the trenches and cover the first oxide, 
     oxidizing the top portion of the polysilicon to form a second oxide, the second oxide and the first oxide forming an oxide mass, the oxide mass and the bottom portion of the polysilicon together forming a trench isolation region; and 
     removing the pad layers. 
     Essentially, the trench isolation fabrication processes disclosed herein have the following significant advantages over those taught in the conventional art: 
     An advantage of the present invention is that, by eliminating a time-consuming thermal oxidation processing step, the throughput of the VLSI fabrication process is increased. 
     Another advantage of the present invention is that it is more compatible with deep sub-micron semiconductor processes than the conventional art because the definition of the isolation regions is not dependent upon a single high-resolution lithographic step. 
     These and other objects, features and advantages of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiment which is illustrated in the several figures of the drawing. 
    
    
     IN THE DRAWINGS 
     FIG. 1A is a schematic, cross-sectional representation of the substrate of a prior-art semiconductor device after formation of pad oxide, pad nitride, the poly-Si layer and the nitride side walls. 
     FIG. 1B is a schematic, cross-sectional representation of the substrate of FIG. 1A after formation of the field oxide region. 
     FIG. 1C is a schematic, cross-sectional representation of the substrate of FIG. 1B after removal of the nitride side walls. 
     FIG. 1D is a schematic, cross-sectional representation of the substrate of FIG. 1C after formation of trenches in the substrate. 
     FIG. 1E is a schematic, cross-sectional representation of the substrate of FIG. 1D after filling of the trenches with poly-Si. 
     FIG. 1F is a schematic, cross-sectional representation of the substrate of FIG. 1E after partial oxidation of the poly-Si. 
     FIG. 1G is a schematic, cross-sectional representation of the substrate of FIG. 1F after formation of trench isolations in the substrate. 
     FIG. 2A is a schematic, cross-sectional representation of the substrate of a semiconductor device of the present invention after formation of pad oxide and pad nitride, removal of a portion of the substrate, and formation of the poly-Si layer and the nitride side walls. 
     FIG. 2B is a schematic, cross-sectional representation of the substrate of FIG. 2A after deposition of the first oxide. 
     FIG. 2C is a schematic, cross-sectional representation of the substrate of FIG. 2B after removal of the side walls. 
     FIG. 2D is a schematic, cross-sectional representation of the substrate of FIG. 2C after formation of trenches in the substrate. 
     FIG. 2E is a schematic, cross-sectional representation of the substrate of FIG. 2D after deposition of the second oxide. 
     FIG. 2F is a schematic, cross-sectional representation of the substrate of FIG. 2E after removal of the top portion of the oxide mass. 
     FIG. 2G is a schematic, cross-sectional representation of the substrate of FIG. 2F after formation of the trench isolation regions. 
     FIG. 3A is a schematic, cross-sectional representation of the substrate of a semiconductor device of the present invention after formation of pad oxide and pad nitride, removal of a portion of the substrate, and formation of the poly-Si layer and the nitride side walls. 
     FIG. 3B is a schematic, cross-sectional representation of the substrate of FIG. 3A after deposition of the first oxide. 
     FIG. 3C is a schematic, cross-sectional representation of the substrate of FIG. 3B after removal of the side walls. 
     FIG. 3D is a schematic, cross-sectional representation of the substrate of FIG. 3C after formation of trenches in the substrate. 
     FIG. 3E is a schematic, cross-sectional representation of the substrate of FIG. 3D after deposition of polysilicon in the trenches. 
     FIG. 3F is a schematic, cross-sectional representation of the substrate of FIG. 3E after oxidation of the top portion of the polysilicon. 
     FIG. 3G is a schematic, cross-sectional representation of the substrate of FIG. 3F after formation of the trench isolation regions. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     While the present invention may be embodied in many forms, details of a preferred embodiment are schematically shown in FIGS. 2A through 3G, with the understanding that the present disclosure is not intended to limit the invention to the embodiment illustrated. 
     The process for forming trench isolation regions in a VLSI device disclosed herein has three unique features: (a) the time-consuming thermal oxidation step generally required in the conventional art is no longer necessary; (b) the definition of the trench isolation regions of the present invention does not rely on merely one single lithographic step, thus greatly reducing the lithographic line width constraints and making the present invention more compatible with deep sub-micron semiconductor processes; and (c) the trench isolation regions of the present invention are formed in a self-aligned manner, such that trench isolation regions having very fine dimensions can be made without relying solely on lithographic steps. 
     In accordance with a specific embodiment of the present invention, trench isolation regions are formed at the surface of a semiconductor substrate to define regions for VLSI circuit elements to be fabricated thereon; see FIGS. 2A-2G. 
     As shown in FIG. 2A, a pad oxide layer  32  and a pad nitride layer  34  are sequentially deposited on top of a semiconductor (e.g., silicon) substrate  30 . Typically, the pad oxide layer  32  is silicon oxide and is approximately 10 to 50 nm thick, and the pad nitride layer  34  is silicon nitride and is approximately 100 to 300 nm. The as-deposited deposited pad oxide and pad nitride are then patterned by conventional lithographic and etching techniques. Notably, this etching process removes not only those portions of the pad nitride and the pad oxide which are not masked by photoresist (not shown) but also the surface regions of the substrate that are located directly underneath the removed portions of the pad oxide. Each of the substrate regions thus formed defines an active region  36 , wherein a trench isolation region will be fabricated as part of the VLSI device. Preferably, approximately 20-100 nm deep of the substrate  30  is removed from an active region  36 . 
     Referring again to FIG. 2A, a thin polysilicon (poly-Si) layer  38  is then deposited on the substrate, covering the pad nitride  34  as well as the active regions  36 . As shown in FIG. 2A the pad oxide layer  32  may be previously etched slightly beyond the edges of the pad nitride  32 , creating undercuts that are now filled with poly-Si  38 . Typically, this poly-Si layer is formed by a chemical vapor deposition (CVD) process and is approximately 10-50 nm thick. Subsequently, side walls  40  are formed along the side of the poly-Si-coated pad nitride  34 , covering portions of the active region  36  shown in FIG.  2 A. However, the central portion of the active region  36  is covered only by the poly-Si layer  38 . Preferably., side walls  40  are either silicon nitride or silicon oxynitride formed by a plasma-enhanced chemical vapor deposition (PECVD) process. 
     Next, as shown in FIG. 2B, a first oxide layer  42  is deposited in the space surrounded by the side walls  40  and the poly-Si-covered central portion of the active region  36 . Preferably, this first oxide layer is a CVD silicon oxide. 
     Next, as shown in FIG. 2C, the side walls  40  are removed by a phosphoric acid etch. This etching process is continued until trenches  44  are formed in the substrate  30 ; see FIG.  2 D. As a result of etching, the thin poly-Si layer  38  on top of the pad nitride  34  is also removed, while an oxide layer  32 ′ is formed at the sides and bottoms of the trenches  44 . Note that the as-deposited first oxide  42  may also be slightly etched, as evidenced by its rounded corners shown in FIGS. 2C and 2D. However, the etch rates for nitride (or oxynitride) and silicon in the phosphoric acid are much greater than the etch rate for oxide, and as a result deep trenches  44  are formed in the substrate  30 . Preferably, the trenches  44  thus formed are approximately 200 to 500 nm deep as measured from the original surface of the substrate  30 . Typically, the oxidized side and bottom surfaces of the trenches  44  are doped with suitable ions (boron or phosphor ions) to prevent channeling across the trenches. 
     Referring to FIG. 2E, a second oxide  46  is deposited on the entire substrate  30 , filling the trenches and covering the first oxide  42  and the pad nitride  34 . In effect, this second oxide  46  and the first oxide  42  form a continuous mass of oxide  48  (shown in FIG.  2 F). Preferably, this second oxide layer is formed by a CVD or high-density plasma chemical vapor deposition (HDPCVD) process. A back-etch process is then conducted to remove the portions of the second oxide  46  located on top of the pad nitride  34  and to form a typically slightly concave surface for the oxide mass  48  that fills the trenches  44 ; see FIG.  2 F. 
     Finally, a chemical-mechanical polishing (CMP) process is conducted to remove the pad nitride  34 , pad oxide  32  and the top portion of the oxide mass  48 . The substrate  30  is left with trenches  44 , which will function as the trench isolation regions separating IC elements to be fabricated on the substrate  30 . See FIG.  2 G. These trenches  44  are filled with oxide mass  48 . Typically, the top surface of the remaining oxide mass  48  is slightly convex because the CMP process removes the pad nitride  34  at a slightly higher rate than the oxide  48 . 
     In accordance with another specific embodiment of the present invention, trench isolation regions are formed at the surface of a semiconductor substrate to define active regions for VLSI circuit elements to be fabricated thereon; see FIGS. 3A-3G. As shown in FIG. 3A, a pad oxide layer  52  and a pad nitride layer  54  are sequentially deposited on top of a semiconductor (e.g., silicon) substrate  50 . Typically, the pad oxide layer  52  is silicon oxide and has a thickness of approximately 10 to 50 nm; the pad nitride layer  54  is silicon nitride and has a thickness of approximately 100 to 300 nm. The as deposited pad oxide and pad nitride are then patterned by conventional lithographic and etching techniques. Again, in the present invention, this etching process removes not only those portions of nitride and oxide which are not masked by photoresist (not shown) but also the surface regions of the substrate that are located directly underneath the removed portions of the pad oxide. Each of the substrate regions thus formed defines an active region  56 , wherein a trench isolation region will be fabricated as part of the VLSI device. Preferably, approximately 20 to 100 nm deep of the substrate  50  is removed from an active region  56 . 
     Referring again to FIG. 3A, a thin polysilicon (poly-Si) layer  58  is then deposited on the substrate, covering the pad nitride  54  as well as the active regions  56 . Typically, this poly-Si layer is formed by a chemical vapor deposition (CVD) process and is approximately 10-50 nm thick. Subsequently, side walls  60  are formed along the side of the poly-Si-coated pad nitride  54 , covering portions of the active region  56  shown in FIG.  3 A. however, the central portion of the active region  56  is covered only by the poly-Si layer  58 . Preferably, side walls  60  are either silicon nitride or silicon oxynitride formed by a plasma-enhanced chemical vapor deposition (PECVD) process. 
     Next, as shown in FIG. 3B, a first oxide layer  62  is deposited in the space surrounded by the side walls  60  and the poly-Si-covered central portion of the active region  56 . Preferably, this first oxide layer is a CVD silicon oxide. 
     Next, as shown in FIG. 3C, the side walls  60  are removed by a phosphoric acid etch. This etching process is continued until trenches  64  are formed in the substrate  50 ; see FIG.  2 D. As a result of etching, the thin poly-Si layer  58  on top of the pad nitride  54  is also removed, while an oxide layer  52 ′ is formed at the sides and bottoms of the trenches  64 . Note that the as-deposited first oxide  62  may also be slightly etched, as evidenced by its rounded corners shown in FIGS. 3C and 3D. However, the etch rates of the nitride (or oxynitride) and silicon in the phosphoric acid are much greater, thus forming deep trenches  64  in the substrate  50 . Preferably, the trenches thus formed are approximately 200 to 500 nm deep as measured from the original surface of the substrate  50 . Typically, the oxidized side and bottoms surfaces of the trenches  64  are doped with suitable ions (e.g., boron or phosphor ions) to prevent channeling across the trenches. 
     Referring to FIG. 3E, poly-Si  66  is deposited to till the trenches  64  and cover the first oxide  62 . Preferably, poly-Si  66  is formed by a CVD process. The top portion of this poly-Si  66  is then oxidized by a thermal process. The pad nitride  54  remains largely intact because its thermal oxidation rate is much lower. The resulting new oxide, the first oxide  62  and the oxide  52 ′ form a continuous mass of oxide  68 ; see FIG.  3 F. 
     Finally, a chemical-mechanical polishing (CMP) process is conducted to remove the pad nitride  54 , the pad oxide  52  and the top portion of the oxide  68 , leaving the substrate  50  with trenches  64 , which will function as the trench isolation regions separating IC elements to be fabricated on the substrate  50 . See FIG.  3 G. Typically, the top surface of the oxide  68  is slightly convex because the CMP process removes the pad nitride  54  at a slightly higher rate than the oxide  68 . 
     While the invention has been particularly shown and described with reference to the above preferred embodiment, it will be understood by those skilled in the art that many other modifications and variations may be made thereto without departing from the broader spirit and scope of the invention as set forth in the claims. The specification and drawings are accordingly to be regarded as an illustrative, rather than restrictive.