Abstract:
An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to semiconductor wafer testing and more particularly to an apparatus and method for reducing the pin count necessary to test Rambus dynamic random access memory (RDRAM). 
     2. Description of the Related Art 
     Rambus DRAM (RDRAM) is a general-purpose, high-performance, packet-oriented dynamic random-access memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and other applications. FIG. 1 schematically illustrates a RDRAM device  10  interconnected with a central processing unit  11  as part of a typical computer system. The RDRAM  10  receives clock signals  12 , control logic  14  and address information  16  from the CPU  11  via a controller  20 . Data  17  is written to and read from the RDRAM  10 . 
     FIG. 2 is a block diagram illustrating one RDRAM configuration in the normal mode. The RDRAM comprises two major blocks: a “core” block  18  comprising banks  22 , sense amps  24  and I/O gating  26  similar to those found in other types of DRAM, and a control logic: block  19  which permits an external controller  10  to access the core  18 . The RDRAM core  18  is internally configured as  32  banks  22 . Each bank  22  has 32,768 144-bit storage locations. 
     FIG. 3 is a diagram indicating that each of the banks  22  is organized as 512 rows  28  by 64 columns  30  by 144 bits  32 . The 144 bits  32  in each column  30  are serially multiplexed onto the RDRAM&#39;s I/O pins as eight 18-bit words  34 . The most significant bits  17 - 9  are communicated on I/O pins DQA &lt; 8 : 0 &gt;, and the least significant bits  8 - 0  are communicated on the I/O pins DQB &lt; 8 : 0 &gt;. The nine. bits on each set of pins are output or input on successive clock edges so that the bits in the eight words are transferred on eight clock edges. The control logic  19  in FIG. 2 receives the CMD, SCK, SIO 0 , and SIO 1  strobes that supply the RDRAM configuration information to the controller  10 , and that select the operating modes of the chip  10 . The CFM, CFMN, CTM and CTNN pins generate the internal clocks used to transmit read data, receive write data, and receive the row and column pins used to manage the transfer of data between the banks  22  and the sense amps  24  of the RDRAM  10 . 
     Eight RQ pins carry control and address information. The RQ pins are divided into two groups. Three ROW pins are de-multiplexed into row packets that manage the transfer of data between the banks  22  and the sense amps  24 . Five COL pins are de-multiplexed into column packets and manage the transfer of data between the data pins and the sense amps  24  of the RDRAM  10 . More detailed information on the operation of RDRAM can be found in Reference A, Direct RDRAM Preliminary Information, Document DL0059 Version 0.9 by Rambus Inc. which is incorporated herein by reference. 
     Semiconductor chips, such as RDRAM chips  10 , contain circuit elements formed in the semiconductor layers which make up the integrated circuits. FIGS. 4A and 4B illustrate a chip  10  with exposed bonding pads  46  made of metal, such as aluminum or the like that are formed as terminals of integrated circuits. In normal operation, the control signals  14 , the address signals  16 , and the data  17  are exchanged with the CPU  11  through connections at these bonding pads  46 . 
     In the manufacturing process, a large number of semiconductor chips  10 , each having a predetermined circuit pattern, are formed on a semiconductor wafer  48  such as that shown in FIG.  5 . FIG. 5 illustrates the semiconductor wafer  48  prior to being diced into individual semiconductor chips. Although FIG. 5 only shows a relatively small number of chips on the wafer, one skilled in the art will appreciate that many chips can be cut from a single wafer. The semiconductor chips  10  are subjected to electrical characteristic tests while they are on the wafer  48  through the use of a testing apparatus, e.g., a wafer probe  50  having a plurality of pins  52 . Note that only the head of the wafer probe  50  is shown in FIG.  5 . Wafer probe testing is commonly used to quality sort individual chips  10  before they are diced from the wafer  48 . The primary goal of wafer probe testing is to identify and mark for easy discrimination defective chips early in the manufacturing process. Wafer testing significantly improves manufacturing efficiency and product quality by detecting defects at the earliest possible stages in the manufacturing and assembly process. In some circumstances, wafer probe testing, provides information to enable certain defects to be corrected. 
     FIG. 6 shows a plurality of the conductive pins  52  of the wafer probe  50  of FIG.  5 . The pins have respective tip ends  54  positionally adjusted to align with the bonding pads  46  of the chip  10  to be tested. A wafer probe  50  has a limited number of pins  52  (e.g., 100 pins) available to supply the test signals to the chips  10  in the wafer  48 . The chips  10  could be tested in their normal mode, but this would require in excess of 40 pins  52  on the wafer probe  50  to test each chip  10 . Others have recognized the benefits of creating a special test mode that enables a chip to be tested with fewer pins. Therefore, one skilled in the art will recognize that it is not required to have a pin  52  for every bonding pad  46  on the chip  10 . However, prior testing methodology references such as Direct RDRAM Test Mode Specification Revision 0.5, Rambus Confidential Information, for RDRAM chips requires at least 34 pins  52  on the wafer probe  50  to test each Rambus DRAM chip  10 , thus constraining the 100 pin wafer probe to test, at most, two chips at one time. As a result, the production time and chip costs are negatively impacted by this limitation. 
     As set forth above, the prior art method of wafer testing RDRAM chips requires 34 pins  52  to test each chip  10 , of which 18 pins are address and data pins. Following this method, the first operation in selecting the address on the RDRAM core entails precharging the bank  22 . Precharging is necessary because adjacent banks  22  share the same sense amps  4  and cannot, therefore be simultaneously activated. Precharging a particular bank  22  deactivates the particular bank and prepares that bank  22  and the sense amps  24  for subsequent activation. For example, when the row  28  in the particular bank  22  is activated, the two adjacent sense amps  24  are connected to or associated with that bank, and therefore are not available for use by the two adjacent banks. Precharging, the bank  22  also automatically causes the two adjacent banks to be precharged, thereby ensuring that adjacent banks are not activated at the same time. 
     Selecting one of the 32 banks  22  to precharge requires five address bits to specify the bank address. These address bits are provided in a first control signal. The next operation in selecting an address is activating a row  28  in a selected bank using a second control signal. This operation requires nine address bits to select one of the 512 rows  28 , and five address bits to select one of the  32  banks  22 , for a total of 14 address bits. The next operation reads a column  30  in an open bank using a third control signal. 
     This operation requires five bank bits. This operation also requires six column bits to select one of the 64 columns  30 . 
     Reducing the number of address bits required to specify the address location to be tested reduces the number of pin connections  52  required on the wafer probe  50  to test each individual chip  10 . Reducing the required number of pin connections  52  therefore allows more chips  10  to be tested at the same time, thus permitting an important reduction in production time and chip costs. As chip sizes continue to decrease, there i.; a corresponding increase in the number of chips on each semiconductor wafer to be tested. Therefore, the ability to test an increased number of devices at the same time grows in importance. 
     SUMMARY OF THE INVENTION 
     The invention comprises a method of testing computer memory devices, such as Rambus DRAM. The method requires fewer pin connections to test each chip on a semiconductor wafer than previously known methods. The test is performed on a semiconductor water using a wafer probe. The number of pins required is reduced by using a trailing edge, of a precharge clock to latch the bank address, thus eliminating the need to perform this function on a later step. In combination with such use of the precharge clock&#39;s trailing edge, the number of pins required is further reduced by dividing the chip to be tested into a plurality of array cores and compressing the output data so that only one data pin per array core is required. By reducing the pin count, more DRAMs can be tested at the same time, thus reducing the overall test cost and time for testing a complete wafer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating a RDRAM device as part of a computer system. 
     FIG. 2 is a functional block diagram illustrating the RDRAM chip configuration in the normal mode. 
     FIG. 3 is a conceptual drawing illustrating the RDRAM bank configured in rows, columns, words, and bits in the normal mode. 
     FIGS. 4A is a top plan view of a RDRAM chip illustrating the bonding pads. 
     FIGS. 4B is a side elevation of the RDRAM of FIG.  4 A. 
     FIG. 5 is a perspective view of a RDRAM semiconductor wafer comprising a plurality of chips with a wafer probe. 
     FIG. 6 is a top plan view of the bonding pads of a RDRAM chip aligned with the conductive pins. connected to a wafer probe. 
     FIG. 7 is a functional block diagram illustrating the RDRAM chip configuration in the DFT mode. 
     FIGS. 8A and 8B are conceptual drawings, illustrating the RDRAM bank configured in rows, columns, words, and bits and being further divided so that the data from two rows can be compressed for 2× row compression and output compressed into a single DQ for Do compression. 
     FIG. 9 is a block diagram illustrating the RDRAM core divided up into four quadrants with a single DQ output after DQ compression. 
     FIG. 10 is a timing diagram illustrating a typical write cycle in the DFT mode. 
     FIG. 11 is a timing diagram illustrating a typical read cycle in the DFT mode. 
     FIG. 12 is a timing diagram illustrating the compressed data output for a DQ in a window manner showing a fault detection. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The RDRAM in accordance with the invention has two modes of operation: (1) a high speed packet mode for normal operation; and (2) a low speed asynchronous mode for testing, which bypasses the packetizing hardware, often called “design for test” circuits or DFT. This second mode, shown as a block diagram in FIG. 7 is realized by including DFT mode control logic  58  and data compression logic  59  in the chip  10  to facilitate testing. In one embodiment of the invention, in the DFT test mode, the RDRAM behaves similar to an asynchronous DRAM, although data is still input/output in bursts of  8 . 
     As shown in FIG. 7, the RDRAM comprises three major blocks: a “core” block  56 , the DFT control logic block  58  and the Data Compression/Expansion Logic box  59 . As shown in FIGS. 8A and 8B, the core  56  is internally configured as 32 banks  22  organized as 512 rows  28  by 64 columns  30  by 144-bit storage locations. The 144 bits are multiplexed as eight 18-bit words. The core is further divided for testing purposes as will be discussed below. 
     The DFT control logic  58  receives a number of signals from the wafer probe  50 , including, TestBSENSE, TestPRECH, TestWRITE, TestCOLLAT, TestCLK_R/W, SIO 0 , SIO 1 , CMD, SCK and Burn PRECH_EN. The Data Compression/Expansion Logic  59  compresses data so that only four data pins are required, as will be discussed below. 
     The pins required for the DFT mode of operation are a subset of the pins used in the normal mode o)f operation. Many of the functions of the normal mode pins are redefined (as discussed below) for the DFT mode. The mapping of the normal mode pins to the DFT mode functions is illustrated below in Table 1. 
     
       
         
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 DFT Pin Mapping 
               
             
          
           
               
                   
                 Pin 
                 DFT Function 
               
               
                   
                   
               
               
                   
                 SCK 
                 SCK 
               
               
                   
                 CMD 
                 CMD 
               
               
                   
                 SIO&lt;1:0&gt; 
                 SIO&lt;1:0&gt; 
               
               
                   
                 CFM/CTM 
                 TestClkR/W 
               
               
                   
                 RQ&lt;0&gt; 
                 TestBSENSE 
               
               
                   
                 RQ&lt;1&gt; 
                 TestPRECH 
               
               
                   
                 RQ&lt;2&gt; 
                 TestWrite 
               
               
                   
                 RQ&lt;3&gt; 
                 TestCOLLAT 
               
               
                   
                 DQB&lt;2:0&gt; 
                 ADR&lt;2:0&gt; 
               
               
                   
                 DQA&lt;3:0&gt; 
                 ADR&lt;6:3&gt; 
               
               
                   
                 DQB&lt;3&gt; 
                 ADR&lt;7&gt; 
               
               
                   
                 DQB&lt;6&gt; 
                 ADR&lt;8&gt; 
               
               
                   
                 DQB&lt;8&gt; 
                 Burn PRECH_EN 
               
               
                   
                 DQA&lt;5:4&gt; 
                 DQ&lt;1:0&gt; 
               
               
                   
                 DQB&lt;5:4&gt; 
                 DQ&lt;3:2&gt; 
               
               
                   
                 CFMN/CTMN 
                 VCC/2 
               
               
                   
                 VCMOS 
                 VCMOS 
               
               
                   
                   
               
             
          
         
       
     
     To test a specific location on the RDRAM core, the location must be referenced by its bank address, row address, and column address. In the normal configuration, selecting the bank address of one of the 32 banks requires five address bits, selecting a row address of one of the 512 rows requires nine address bits, and selecting a column address of one of the 64 columns requires six address bits. In accordance with the present invention, the chip  10  is wafer tested using DQ compression and 2× row compression. 
     In DQ compression, the chip  10  is divided into four quadrants,  60 A,  60 B,  60 C, and  60 D, as illustrated in FIG. 9, with each quadrant corresponding to a respective  36  megabit array core  61 A,  61 B,  61 C, and  61 D. Each array core  61 A,  61 B,  61 C, and  61 D is an independent repair region. The lower two quadrants,  60 A and  60 B, comprise banks  0 - 15 . The upper two quadrants,  60 C and  60 D, comprise banks  16 - 31 . This division is based or physical design parameters of the chip  10 . The lower left quadrant  60 A comprises bits  9 - 17  of banks  0 - 15 . The lower right quadrant  60 B comprises bits  0 - 8  of banks  0 - 15 . The upper left quadrant  60 C comprises bits  9 - 17  of banks  16 - 31 . The upper right quadrant  60 D comprises bits  0 - 8  of banks  16 - 31 . As discussed below, for testing, only a single bit of data is transferred into and out of each quadrant  60 A,  60 B,  60 C, and  60 D. In particular, as will be discussed below, a data bit DQ 0  is used to test the upper left quadrant  60 C. A data bit DQ 1  is used to test the upper right quadrant  60 D. A data bit DQ 2  is used to test the lower left quadrant  60 A. A data bit DQ 3  is used to test the lower right quadrant  60 B. Therefore, only four data bits are required to test the entire memory. Note further that the upper banks ( 16 - 31 ) and the lower banks ( 0 - 15 ) have separate data connections in the DFT mode. Thus, the most significant bank bit that distinguishes the upper and lower sets of banks is not required, and the number of bank bits is reduced from five bits to four bits. 
     The 2× row compression further reduces the number of bank address bits required. In particular, the data from corresponding rows in two alternating banks (e.g., bank n with bank n+2 and bank n+16 with bank n+18) are combined as shown in FIGS. 8A and 8B so that the data are transferred to and from both rows using a common DQ bit. This reduces the number of selectable banks in each quadrant from sixteen to eight. Thus, only three bank bits are required to select one of the eight banks in each quadrant. 
     The data from the two rows of the alternating banks are transferred (either written to the memory or read from the memory) one byte at a time, as in the normal mode. However, because only one data pin is available for each quadrant  60 A,  60 B,  60 C, and  60 D, the nine bits of data from each of the two rows (18 bits of data in all) in each quadrant are combined into a respective single bit (i.e., DQ 0 , DQ 1 , DQ 2 , or DQ 3 ). Thus, for each quadrant the data from a column in the two rows are output as a sequence of eight single data bits. 
     The compression of the data bits is performed by the data compression/expansion logic  59 . Data are written to the memory by applying a data bit to each of the compressed data pins (i.e., to DQ 0 , DQ 1 , DQ 2 , DQ 3 ). On each clock edge the data compression/expansion logic  59  fans out the single data bit to the eighteen data locations addressed by the bank, row and column bits. Thus, the same data are written into all eighteen locations. Thereafter, when the memory locations are read to test the integrity of the memory, the data from the eighteen locations read during each clock edge are compared to determine if any location has a different data output. If the data are the same, the output on the DQ line has a first constant state (e.g., a logic one or a logic zero in accordance with the data written during the write operation) to indicate pass. If any bit in any of the eighteen locations is different, the data output on the DQ line is force(d to have a transition to indicate a failure. 
     The result of the DQ compression and the 2× row compression is that the array cores  61 A,  61 B,  61 C and  61 D are configured as 8 banks by 512 rows by 64 columns by eight nine-bit bytes. Therefore, only three bank select bits, nine row address bits, and six column address bits are required to identify a particular location in the array core. This results in the ability to test each chip  10  using only nine pins on the wafer probe  50  for defining a specific address location. When the row is activated, nine row address bits identify one of the 512 rows. When a column in an open bank is read, the three bank bits and the six column bits (a total of nine bits) identify the bank and the column in the bank to be written to or read from. 
     FIG. 10 is a timing diagram that illustrates a typical write cycle that is used to select the bank, row, and column address and strobe in the data. FIG. 11 is a timing diagram that similarly illustrates a typical read cycle. In these cycles, a precharge clock, TestPRECH  62 , is used to select the bank address. The leading edge of TestPRECH  62  is used to precharge the bank, designated by the bank address present on the address pins  64 . Precharging the bank prepares the bank and the sense amps for activation. Since adjacent inner banks share the same sense amps, adjacent banks cannot be activated at the same time. Precharging any bank automatically causes adjacent banks to be precharged also, thereby ensuring that adjacent banks are not open at the same time. This happens in all modes of operation, not just the DFT mode. 
     On the falling edge of TestPRECH  62 , the bank corresponding to the bank address on the address pins  64  is latched. This activates the latched bank, allowing the rows in that bank to be sensed. Multiple banks can be active at any one time. That is, banks previously activated and not subsequently deactivated by precharging remain active in addition to the newly activated bank. Precharging banks and latching banks are accomplished using different edges of the same TestPRECH signal  62 . Thus, the present invention eliminates the need to provide separate control signals for the precharge function and the latching function. 
     Next, a row address is selected using address pins and a row sense clock, TestBSENSE  66 . TestBSENSE  66  causes the selected row of all latched (i.e., active) banks to be sensed The row address to be sensed is the address present on the address pins  64 ,  68  and  70  at the falling edge of TestBSENSE  66 . Because there are 512 rows, nine address pins are required to select the row to be tested. Because the bank was latched using the other edge of the TestPRECH  62 , it is not required to select a bank in this operation. Thus, unlike other known methods, the bank select bits do not have to be applied at this time and only the nine address bits need to be applied. 
     Data are then either read from or written to the column and bank in accordance with the address present on the address pins at the rising edge of a column latch clock, TestCOLLAT  72 . Three address pins  64  select the bank, and six address pins  68  and  70  select the column. Thus, nine bits are sufficient to provide the necessary address bits. The bank must be one of the banks that was active when TestBSENSE  66  was applied. A TestWrite clock  74  determines whether the operation performed at TestCOLLAT  72  time is a read or a write function. If TestWrite=1 at the rising edge of TestCOLLAT  72 , then the data present in a write buffer are written to the RDRAM core. If TestWrite=0 at the rising edge of TestCOLLAT  72 , then the data are read from the RDRAM core t,) a read buffer. 
     FIGS. 10 and 11 show a TestClkR/W clock  76  strobing data into the write buffer or out of the read buffer depending on the state of TestWrite  74 . If TestWrite=1, then data are input into the write buffer from the tester on sequential edges of TestClkR/W  76 , beginning with the first falling edge. Eight clock edges transfer data. It takes a total of six TesClkR/W  76  cycles to completely load the write buffer. Additional clock cycles will initiate another load sequence. A load sequence is not terminated until the exact number of clock cycles are provided. If TestWrite=0, then data are read from the read buffer to the external bus on each edge of TestClkR/W  76 , beginning with the second falling edge. Eight clock edges transfer the data. It takes a total of six TestClkR/W  76  cycles to completely empty the read buffer. The chip under test remains in the output mode until all data are read out of the read buffer. Any additional clock cycles initiates a new read sequence. Note that any transition on TestClkR/W  76  initiates a read or write sequence depending on the state of TestWrite  74 . 
     FIG. 12 is a timing diagram that illustrates the compressed data being output in a window manner when reading the compressed DQs. If the expected data is a “0”, then the DQ will be low during the entire window. A failure is indicated if the wrong data is present, or if a data transition is detected during the window. If the expected data is “1”, then the DQ should remain high throughout the window. 
     If a fault is; indicated, it is not necessary to determine which bit failed, it is sufficient to localize the fault to a row. The tester has the capability to reconfigure the chip so that a spare row is used to replace the row with the fault. The technology for such reconfiguration is well known in the field. 
     Note that by reducing the required address bits to three and by using both edges of the TestPRECH control signal, the maximum number of address bits required is nine, which with the addition of the four data bits, totals thirteen. This is significantly fewer than the eighteen data and address bits used in other known test methods. 
     Although specific implementations and operation of the invention have been described above with reference to specific embodiments, the invention may be embodied in other forms without departing from the spirit or central characteristics of the invention. The: described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning of equivalency of the claims are to be embraced within their scope.