Abstract:
A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and a complement of the input signal. The sense amplifier includes cross-coupled transistors. Each unique cross-coupled transistor is coupled to a corresponding unique transistor formed as a diode. A resistor is coupled in series between one cross-coupled resistor and an input port receiving the input signal, and another resistor is coupled in series between the other cross-coupled transistor and another input port receiving the complement of the input signal. Resistances associated with the sources of each cross-coupled transistor provide the resistance of the resistors.

Description:
RELATED APPLICATIONS  
       [0001]    This application is a divisional of U.S. patent application Ser. No. 09/547,987 by Sim et al. entitled “Sense Amplifier of Semiconductor Integrated Circuit”, which is incorporated herein by reference, which claims priority from Republic of Korea Application Serial No. 99-27890. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to semiconductor integrated circuits, and more particularly, to sense amplifiers and differential amplifiers.  
           [0004]    2. Description of the Related Art  
           [0005]    There are two types of sense amplifiers commonly used for amplifying signals in semiconductor integrated circuits, current sense amplifiers and voltage sense amplifiers. Current sense amplifiers are widely used since they can operate faster than voltage sense amplifiers. FIG. 1 shows a conventional sense amplifier circuit that includes a-current sense amplifier  10 , a full differential amplifier  12 , and a latch  14 . When an enable signal EN is at a high level, NMOS transistors MN 11 , MN 5 , and MN 8  are on and provide current paths to enable operation of the current amplifier  10 , the full differential amplifier  12 , and the latch  14 , respectively. During a sensing time when the enable signal EN is at a high level, the voltage swings of the output signals SAOUT and SAOUTB of the current sense amplifier  10  are small. Accordingly, the amplification speed of the current sense amplifier  10  cannot directly convert the output signals SAOUT and SAOUTB to a CMOS voltage level. To increase the amplification speed, the full differential amplifier  12  further amplifies the output signal of the current sense amplifier  10  and outputs the amplified signals OUT and OUTB to the latch  14 . The latch  14  latches the output signals OUT and OUTB from the full differential amplifier  12  and provides latched output signals DOUT and DOUTB.  
           [0006]    In differential amplifier  12 , a first NMOS transistor MN 1 , a second NMOS transistor MN 2 , a first PMOS transistor MP 1 , and a second PMOS transistor MP 2  operate as a first differential amplifying unit that generates the output signal OUT. When the voltage of an input signal SAOUT input through node  16  functioning as an input port becomes higher than the voltage of a complementary input signal SAOUTB input through node  18  functioning as a complementary input port, the voltage of the output signal OUT at an output port  24  increases. A third NMOS transistor MN 3 , a fourth NMOS transistor MN 4 , a third PMOS transistor MP 3 , and a fourth PMOS transistor MP 4  operate as a second differential amplifying unit that generates the complementary output signal OUTB. Accordingly, the voltage of the complementary output signal OUTB at a complementary output port  26  decreases when the voltage of the input signal SAOUT becomes higher than that of the complementary input signal SAOUTB.  
           [0007]    When the voltage of the input signal SAOUT becomes lower than the voltage of the complementary input signal SAOUTB, the first differential amplifying unit decreases the voltage of the output signal OUT, and the second differential amplifying unit increases the voltage of the complementary output signal OUTB. The voltage difference between the output signal OUT and the complementary output signal OUTB is proportionate to the voltage difference between the input signal IN and the complementary input signal INB.  
           [0008]    The output signal OUT and the complementary output signal OUTB are the input signals of the latch  14 . The latch  14  includes a sixth NMOS transistor MN 6 , a seventh NMOS transistor MN 7 , an eighth NMOS transistor MN 8 , a fifth PMOS transistor MP 5 , and a sixth PMOS transistor MP 6 . The latch  14  performs an effective latch operation when the voltage levels of the output signal OUT and the complementary output signal OUTB from the full differential amplifier  12  near the turn-on voltage of the NMOS transistors MN 6  and MN 7 , respectively. If either the output signal OUT or the complementary output signal OUTB is higher than the turn-on voltage of the corresponding NMOS transistor MN 6  or MN 7 , the latch  14  performs the latch operation when the other signal OUTB or OUT is lower than the turn-off voltage of the corresponding NMOS transistor MN 7  or MN 6 . In FIG. 1, the latch circuit  14  outputs the output signal DOUT and the complementary output signal DOUTB.  
           [0009]    In general, transistors in the sense amplifier of FIG. 1 are sized so that when a supply voltage VDD is low, the mean value of the output signal OUT and the complementary output signal OUTB is around the turn-on voltage of the NMOS transistors MN 6  and MN 7 . However, the channel length modulation effect of the PMOS transistors (e.g., transistors MP 1 , MP 2 , MP 3 , and MP 4 ) becomes larger than the channel length modulation effect of the NMOS transistors (e.g., MN 1 , MN 2 , MN 3 , and MN 4 ) as the supply voltage VDD increases. Accordingly, when the supply voltage VDD increases, the mean voltage of the output signal OUT and the complementary output signal OUTB increases. Accordingly, the NMOS transistors MN 6  and MN 7  in the latch  14  do not operate effectively. More specifically, the output signal OUT, which is applied to the gate of the sixth NMOS transistor MN 6 , and the complementary output signal OUTB, which is applied to the gate of the seventh NMOS transistor MN 7 , strongly turn on transistors MN 6  and MN 7 . This can cause errors in the latch operation. Accordingly, the latch circuit  14  can malfunction when the semiconductor integrated circuit is tested in a high voltage test enable (HITE) mode, where the supply voltage is a high voltage. Therefore, normal testing of the semiconductor integrated circuit in the HITE mode is not possible.  
           [0010]    To solve the above problem, the design of the full differential amplifier  12  can make the second PMOS transistor MP 2  and the third PMOS transistor MP 3  smaller. In this case, the gain of the full differential amplifier is reduced.  
           [0011]    The current sense amplifier  10  shown in FIG. 1 is widely used since the current sense amplifier  10  operates faster than a voltage sense amplifier. However, the operation of the current sense amplifier  10  becomes unstable since a positive feedback circuit is used to effectively receive a current input signal. For the current sense amplifier  10 , reference numerals I 1  and I 2  denote current signals input through the input ports  15  and  17 , respectively. Signals SAOUT and SAOUTB are output through node  16  functioning as an output port and node  18  functioning as a complementary output port, respectively.  
           [0012]    To explain the operation of the current sense amplifier  10 , the transconductance of the ninth NMOS transistor MN 9  and the tenth NMOS transistor MN 10  is referred to herein as gmn. The transconductance of the seventh PMOS transistor MP 7  and the eighth PMOS transistor MP 8  is referred to as gmp. ΔI is the difference between the input current I 1  and the complementary input current I 2  (ΔI=I 1 ×I 2 ). The voltage difference between the output voltage SAOUT and the complementary output voltage SAOUTB is about equal to ΔI/gmn. The difference between the current value amplified by the seventh PMOS transistor MP 7  and the current value amplified by the eighth PMOS transistor MP 8  is ΔI×gmp/gmn. Since this value must be equal to ΔI, which is the difference between the input current signals I 1  and I 2 , the transconductance gmp of the PMOS transistors MP 7  and MP 8  must be equal to the transconductance gmn of the NMOS transistors MN 9  and MN 10 .  
           [0013]    When the sizes of the seventh PMOS transistor MP 7  and the eighth PMOS transistor MP 8  are increased to increase the gains of the seventh PMOS transistor MP 7  and the eighth PMOS transistor MP 8 , transconductance gmp becomes larger than transconductance gmn. Accordingly, the seventh PMOS transistor MP 7  and the eighth PMOS transistor MP 8  amplify the input current signals with a current difference larger than ΔI, which is the difference between the input current signals. Therefore, the values associated with the input current signals I 1  and I 2  can be exchanged, and the current sense amplifier  10  goes to an unstable state. The transconductance gmp must be less than or equal to transconductance gmn for stability. However, as transconductance gmp becomes smaller than transconductance gmn, the operation speed is reduced since the efficiency of the current sense amplifier sensing the current deteriorates. Therefore, the values of transconductances gmn and gmp must be determined considering a trade-off between stability and speed.  
           [0014]    In general, since the channel length modulation effect of the PMOS transistor is larger than the channel length modulation effect of the NMOS transistor, the transconductance of the PMOS transistor is larger than the transconductance of the NMOS transistor.  
           [0015]    [0015]FIG. 2 shows an NMOS diode and a PMOS diode for illustrating the transconductances of an NMOS transistor and a PMOS transistor, respectively. The transistors have gates and drains connected to form diodes. The current-voltage characteristic curves of the transistor diodes shown in FIG. 2 are shown in FIG. 3. The slopes of the current-voltage characteristic curves indicate the transconductances at different voltages.  
           [0016]    As shown in FIG. 3, at gate-source voltages Vgsn and Vsgp larger than a voltage Vc, the slope of the current-voltage characteristic curve of the PMOS transistor is larger than the slope of the current-voltage characteristic curve of the NMOS transistor. The transconductance gmp becomes larger than the transconductance gmn as the applied voltage increases. In the conventional current sense amplifier, when the transconductance gmp of a PMOS transistor is equal to the transconductance gmn of an NMOS transistor at a low voltage, the transconductance gmp of the PMOS transistor becomes larger than the transconductance gmn of the NMOS transistor as the supply voltage increases. Therefore, the operation of the current sense amplifier becomes unstable.  
         SUMMARY OF THE INVENTION  
         [0017]    In accordance with an aspect of the present invention, a sense amplifier of a semiconductor integrated circuit includes a full differential amplifier capable of stabilizing the operation of a latch circuit and easily controlling voltage gain by reducing the mean voltage level of an output signal even when a supply voltage increases.  
           [0018]    Another aspect of the present invention provides a current sense amplifier that stably operates at high speed.  
           [0019]    In one embodiment of the invention, a semiconductor integrated circuit includes a sense amplifier that receives and amplifies complementary input signals, a full differential amplifier that amplifies the output of the sense amplifier, and a latch that latches the output of the full differential amplifier. The full differential amplifier includes a first differential amplifying unit, a second differential amplifying unit, and an output voltage level control circuit. The first differential amplifying unit increases the voltage of a first output port when the level of an input signal input through a first input port becomes higher than the level of a complementary input signal input through a first complementary input port and decreases the voltage of the first output port when the level of the input signal becomes lower than the level of the complementary input signal. The second differential amplifying unit decreases the voltage of a first complementary output port when the level of the input signal becomes higher than the level of the complementary input signal and increases the voltage of the first complementary output port when the level of the input signal becomes lower than the level of the first complementary input signal. The output voltage level control circuit is connected between the first output port and the first complementary output port and controls the voltage levels of the signals output from the first output port and the first complementary output port.  
           [0020]    The output voltage level control circuit preferably includes an output voltage mean value sensing unit and an output voltage mean value controller. The output voltage mean value sensing unit senses the mean value of the voltage levels of the signals output from the first output port and the first complementary output port, and the output voltage mean value controller prevents the mean value of the output voltage levels from increasing beyond a predetermined limit. The output voltage mean value sensing unit preferably includes a first resistor and a second resistor serially connected between the first output port and the first complementary output port, and the mean value of the output voltage levels is output from a node between the first resistor and the second resistor. The resistance of the first resistor is preferably equal to the resistance of the second resistor. One embodiment of the output voltage mean value controller includes an NMOS transistor, wherein the gate and the drain of the NMOS transistor are connected to the node between the first resistor and the second resistor, and the source of the NMOS transistor is grounded.  
           [0021]    Another embodiment of the output voltage mean value controller preferably includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor and the gate of the second NMOS transistor are connected to the node between the first resistor and the second resistor. The drain of the first NMOS transistor is connected to the first output port, and the drain of the second NMOS transistor is connected to the first complementary output port. The sources of the first NMOS transistor and the second NMOS transistor are grounded.  
           [0022]    Preferably, the full differential amplifier further includes an operation controller connected to the first differential amplifying unit, the second differential amplifying unit, and the output voltage level control circuit. The operation controller controls the operation of the first differential amplifying unit, the second differential amplifying unit, and the output voltage level control circuit according to an enable signal.  
           [0023]    In an exemplary embodiment, the first differential amplifying unit includes first and second PMOS transistors and first and second NMOS transistors. A supply voltage is applied to the sources of the first and second PMOS transistors. The drain and the gate of the first PMOS transistor are connected. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the first output port. The gate of the first NMOS transistor is connected to the first input port, and the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor. The gate of the second NMOS transistor is connected to the first complementary input port, and the drain of the second NMOS transistor is connected to the first output port. The second differential amplifying unit includes third and fourth PMOS transistors and third and fourth NMOS transistors. The supply voltage is applied to the sources of the third and fourth PMOS transistors. The drain of the third PMOS transistor is connected to the first complementary output port. The drain and the gate of the fourth PMOS transistor are connected to the gate of the third PMOS transistor. The gate of the third NMOS transistor is connected to the first input port, and the drain of the third NMOS transistor is connected to the first complementary output. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fourth NMOS transistor is connected to the first complementary input port. The operation controller includes a fifth NMOS transistor wherein the drain of the fifth NMOS transistor is connected to the sources of the first, second, third, and fourth NMOS transistors and the output voltage mean value controller.  
           [0024]    The sense amplifier includes: a second input port; a second complementary input port; first, second, third, and fourth transistors; and first and second resistors. The second input port receives a first current signal, and the second complementary input port receives a second current signal. The first and second transistors, which are cross coupled to each other, receive current signals from the second input port and the second complementary input port, respectively, and output a first output signal and a second output signal, respectively, to a second output port and a second complementary output port, respectively. The third and fourth transistors supply current to the second output port and the second complementary output port, respectively. The first resistor is between the second input port and the first transistor, and a second resistor is between the second complementary input port and the second transistor. The first resistor and the second resistor are preferably as close as possible to the first transistor and the second transistor, respectively.  
           [0025]    Preferably, the sense amplifier further includes a fifth transistor that forms a current path so that the third transistor and the fourth transistor operate in response to an enable signal. The third transistor and the fourth transistor of the sense amplifier are preferably connected to each other to form diodes. The first transistor and the second transistor are preferably PMOS transistors, and the third transistor, the fourth transistor, and the fifth transistor are preferably NMOS transistors.  
           [0026]    The first resistor can be directly formed in the first transistor by forming one contact to the source electrode of the first transistor and forming multiple contacts to the drain electrode of the first transistor, so that the contact resistance of the source electrode of the first transistor provides the resistance associated with the first resistor. Similarly, the second resistor can be directly formed in the second transistor by forming one contact to the source electrode of the second transistor and forming multiple contacts to the drain electrode of the second transistor, so that the contact resistance of the source electrode of the second transistor provides the resistance of the second resistor.  
           [0027]    Alternatively, the first resistor is directly formed in the first transistor by having the contact of the source electrode of the first transistor separated from the gate electrode of the first transistor so that the resistance of the source electrode provides the resistance of the first resistor. Similarly, the second resistor can be directly formed in the second transistor by having the contact of the source electrode of the second transistor separated from the gate electrode of the second transistor so that the resistance of the source electrode provides the resistance of the second resistor.  
           [0028]    In another alternative, the first resistor can be directly formed in the first transistor by forming a shallow active region for the source electrode of the first transistor so that the active resistance of the source electrode is equal to the resistance of the first resistor. The second resistor is directly formed in the second transistor by forming a shallow active region for the source electrode of the second transistor so that the active resistance of the source is equal to the resistance of the second resistor.  
           [0029]    In yet another alternative, the first resistor can be directly formed in the first transistor having a low dopant density for the source of the first transistor so that the active resistance associated with the source of the first transistor provides the resistance of the first resistor. Similarly, the second resistor can be directly formed in the second transistor having a low dopant density for the source of the second transistor so that the active resistance associated with the source of the second transistor provides the resistance of the second resistor.  
           [0030]    In accordance with another embodiment of the invention, a full differential amplifier includes a first differential amplifying unit, a second differential amplifying unit, and an output voltage level control circuit. The first differential amplifying unit increases the voltage of a first output port when the level of an input signal input through a first input port becomes higher than the level of a complementary input signal input through a first complementary input port and reduces the voltage of the first output port when the level of the input signal becomes lower than the level of the complementary input signal. The second differential amplifying unit reduces the voltage of a first complementary output port when the level of the input signal becomes higher than the level of the complementary input signal and increases the voltage of the first complementary output port when the level of the input signal becomes lower than the level of the first complementary input signal. The output voltage level control circuit, which is between the first output port and the first complementary output port, controls the mean voltage level of the output signals from the first output port and the first complementary output port.  
           [0031]    In accordance with another embodiment of the invention, a current sense amplifier includes a first input port for receiving a first current signal and a first complementary input port for receiving a second current signal. A first transistor and a second transistor, which are cross coupled to each other, receive the current signals from the first input port and the first complementary input port and output a first output signal and a second output signal to a first output port and a first complementary output port. A third transistor and a fourth transistor supply current to the first output port and the first complementary output port. The current sense amplifier further includes a first resistor serially connected between the first input port and the first transistor and a second resistor serially connected between the first complementary input port and the second transistor. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]    The aspects and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0033]    [0033]FIG. 1 shows a conventional sense amplifier;  
         [0034]    [0034]FIG. 2 shows an NMOS diode and a PMOS diode;  
         [0035]    [0035]FIG. 3 shows the current-voltage characteristic curves of the NMOS diode and the PMOS diode shown in FIG. 2;  
         [0036]    [0036]FIG. 4 shows a sense amplifier of a semiconductor integrated circuit according to an embodiment of the present invention;  
         [0037]    [0037]FIGS. 5 and 6 show other full differential amplifiers in accordance with embodiments of the invention;  
         [0038]    [0038]FIG. 7 shows waveforms of input signals for a simulation of a full differential amplifier;  
         [0039]    [0039]FIG. 8 shows waveforms for the output signals of a full differential amplifier according to an embodiment of the present invention and a conventional full differential amplifier according to a simulation experiment;  
         [0040]    [0040]FIG. 9 shows waveforms for the output signals of a latch where the output of a full differential amplifier according to the present invention is an input and where the output of the conventional full differential amplifier is an input, respectively, according to the simulation experiment;  
         [0041]    [0041]FIG. 10 shows a PMOS diode for describing the operation of a current sense amplifier in the sense amplifier according to an embodiment of the present invention;  
         [0042]    [0042]FIG. 11 shows the current-voltage characteristic curves of the PMOS diode shown in FIG. 10;  
         [0043]    [0043]FIG. 12 is a circuit diagram of a current sense amplifier in the sense amplifier according to the embodiment of the present invention;  
         [0044]    [0044]FIG. 13 shows waveforms of the output voltage signals of the current sense amplifier according to an embodiment of the present invention and a conventional current sense amplifier, according to the simulation experiment;  
         [0045]    [0045]FIG. 14 shows waveforms of the input current signals of the current sense amplifier according to the embodiment of the present invention and the conventional current sense amplifier, according to the simulation experiment; and  
         [0046]    [0046]FIGS. 15, 16A,  16 B, and  17  illustrate methods of directly forming the resistors of the current sense amplifier in FIG. 4 in transistors. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0047]    [0047]FIG. 4 shows a sense amplifier of a semiconductor integrated circuit according to an embodiment of the present invention. The sense amplifier includes a current sense amplifier  40 , a full differential amplifier  42  for amplifying the output of the current sense amplifier  40 , and a latch  44  for latching the output of the full differential amplifier  42  and outputting the latched output.  
         [0048]    In FIG. 4, the full differential amplifier  42  includes a first differential amplifying unit, a second differential amplifying unit, and an output voltage level control circuit  60 . The first differential amplifying unit includes a first PMOS transistor MP 9 , a second PMOS transistor MP 10 , a first NMOS transistor MN 12 , and a second NMOS transistor MN 13 . The second differential amplifying unit includes a third PMOS transistor MP 11 , a fourth PMOS transistor MP 12 , a third NMOS transistor MN 14 , and a fourth NMOS transistor MN 15 . A fifth NMOS transistor MN 16  turns on or off to enable or disable the first and second differential amplifying units and the output voltage level control circuit  60 . The output voltage level control circuit  60  includes a first resistor R 1 , a second resistor R 2 , and a sixth NMOS transistor MN 17 .  
         [0049]    The output signal OUT and the complementary output signal OUTB of the full differential amplifier  42  are the input signals of the latch  44 . The latch  44  includes a seventh NMOS transistor MN 18 , an eighth NMOS transistor MN 19 , a ninth NMOS transistor MN 20 , a fifth PMOS transistor MP 13 , and a sixth PMOS transistor MP 14 .  
         [0050]    In the full differential amplifier  42 , the first PMOS transistor MP 9  has a source at a supply voltage VDD and a drain and a gate connected together. The second PMOS transistor MP 10  has a source at the supply voltage VDD, a gate connected to the gate of the first PMOS transistor MP 9 , and a drain connected to the first output port  46 . The first NMOS transistor MN 12  has a gate connected to a node  52  functioning as a first input port and a drain connected to the drain of the first PMOS transistor MP 9 . The second NMOS transistor MN 13  has a gate connected to a node  54  functioning as a first complementary input port and a drain connected to the first output port  46 .  
         [0051]    In the second differential amplifying unit, the third PMOS transistor MP 11  has a source at the supply voltage VDD and a drain connected to the first complementary output port  48 . The fourth PMOS transistor MP 12  has a source at the supply voltage VDD and a drain and a gate connected to the gate of the third PMOS transistor MP 11 . The third NMOS transistor MN 14  has a gate connected to node  52  and a drain connected to the first complementary output port  48 . The fourth NMOS transistor MN 15  has a gate connected to node  54  and a drain connected to the drain of the fourth PMOS transistor MP 12 . The fifth NMOS transistor MN 16  is an operation controller connected to the first differential amplifying unit, the second differential amplifying unit, and the output voltage level control circuit  60 . The drain of the fifth NMOS transistor MN 16  is connected to the sources of the first NMOS transistor MN 12 , the second NMOS transistor MN 13 , the third NMOS transistor MN 14 , the fourth NMOS transistor MN 15 , and the sixth NMOS transistor MN 17 , and a ground voltage VSS is applied to the source of the fifth NMOS transistor MN 16 . The enable signal EN is applied to the gate of the fifth NMOS transistor to control the operation of the first differential amplifying unit, the second differential amplifying unit, and the output voltage level control circuit  60 .  
         [0052]    The output voltage level control circuit  60  includes an output voltage mean value sensing unit and an output voltage mean value controller. The output voltage mean value sensing unit includes the first and second resistors R 1  and R 2  serially connected between the first output port  46  and the first complementary output port  48 . The resistors R 1  and R 2  have the same resistance, so that a node  50  between the resistors is at a voltage halfway between the voltages of the output signals OUT and OUTB. The output voltage mean value controller includes the sixth NMOS transistor MN 17 . The drain and gate of the sixth NMOS transistor MN 17  are connected to the node  50  between the first resistor R 1  and the second resistor R 2 .  
         [0053]    The operation of the full differential amplifier  42  in the sense amplifier according to the above-described embodiment of the present invention is described below.  
         [0054]    The first differential amplifying unit including the first PMOS transistor MP 9 , the second PMOS transistor MP 10 , the first NMOS transistor MP 12 , and the second NMOS transistor MN 13  increases the voltage of the first output port  46  when the voltage level of the input signal SAOUT becomes higher than the voltage level of the complementary input signal SAOUTB. Conversely, the first differential amplifying unit reduces the voltage of the first output port  46  when the voltage level of the input signal SAOUT becomes lower than the voltage level of the complementary input signal SAOUTB. The second differential amplifying unit including the third PMOS transistor MP 11 , the fourth PMOS transistor MP 12 , the third NMOS transistor MN 14 , and the fourth NMOS transistor MN 15 , reduces the voltage of the first complementary output port  48  when the voltage level of the input signal SAOUT becomes higher than the voltage level of the complementary input signal SAOUTB. Conversely, the second differential amplifying unit increases the voltage of the first complementary output port  48  when the voltage level of the input signal SAOUT becomes lower than the voltage level of the complementary input signal SAOUTB.  
         [0055]    The voltage at the node  50  between the first resistor R 1  and the second resistor R 2  is equal to the mean value of the voltage levels of the output signal OUT and the complementary output signal OUTB. The sixth NMOS transistor MN 17  is wired to form a diode and turns on when the mean value voltage on the node  50  becomes larger than the diode turn-on voltage of the sixth NMOS transistor MN 17 . The fifth NMOS transistor MN 16  turns on when the enable signal EN is at a high level, and thus the fifth NMOS transistor MN 16  completes a path for current that flows through the sixth NMOS transistor MN 17  and the fifth NMOS transistor MN 16  to ground. Accordingly, when the mean value of the voltage levels of the output signal OUT and the complementary output signal OUTB exceeds the diode turn-on voltage of the sixth NMOS transistor MN 17 , the NMOS sixth transistor turns on and reduces the mean value voltage of the output signals OUT and OUTB. Accordingly, when the enable signal EN is at the high level, the output voltage level control circuit  60  prevents the mean value of the voltage levels of the output signal OUT and the complementary output signal OUTB from increasing beyond the turn-on voltage of the sixth NMOS transistor MN 17 .  
         [0056]    When the supply voltage VDD increases during testing of the semiconductor integrated circuit in a high voltage test enable (HITE) mode (where a high voltage is used as the supply voltage), the channel length modulation effect of the PMOS transistors becomes larger than the channel length modulation effect of the NMOS transistors. Accordingly, the currents through the first through fourth PMOS transistors MP 9 , MP 10 , MP 11 , and MP 12  increase. Therefore, the voltage levels of the output signal OUT and the complementary output signal OUTB simultaneously increase, and the operating voltage of the first through fourth PMOS transistors MP 9 , MP 10 , MP 11 , and MP 12  becomes higher. Accordingly, the mean value of the output voltage levels of the output signal OUT and the complementary output signal OUTB increases. At this time, the output voltage mean value sensing unit, which includes the first resistor R 1  and the second resistor R 2 , senses the mean value of the voltage levels of the output signal OUT and the complementary output signal OUTB and outputs the sensed mean value to the node  50 .  
         [0057]    When the increased mean value is output to the node  50 , the voltages of the gate and the drain of the sixth NMOS transistor MN 17  increase, thus turning on the sixth NMOS transistor MN 17 . Accordingly, some of the current provided by the first through fourth PMOS transistors MP 9 , MP 10 , MP 11 , and MP 12  flows through the sixth NMOS transistor MN 17  and the fifth NMOS transistor MN 16  to the ground. Therefore, the mean value of the output voltages of the output signal OUT and the complementary output signal OUTB is reduced, to thus stabilize the operation of the latch  44 .  
         [0058]    Since the first resistor R 1  and the second resistor R 2  are between the first output port  46  and the first complementary output port  48 , it is possible to control the voltage gain of the full differential amplifier by controlling the resistances of the first resistor R 1  and the second resistor R 2 . The voltage gain of the full differential amplifier is proportionate to the transconductances of the NMOS transistors MN  13  and MN 14  connected to the first output port  46  and the first complementary output port  48 , respectively, and the resistance of the first resistor R 1  or the second resistor R 2 .  
         [0059]    [0059]FIGS. 5 and 6 show other embodiments of the full differential amplifier. In the full differential amplifier shown in FIG. 5, an output voltage level control circuit  62  includes the output voltage mean value sensing unit and the output voltage mean value controller. The output voltage mean value sensing unit includes the first resistor R 1  and the second resistor R 2 . The first resistor R 1  and the second resistor R 2  are serially connected to each other between the first output port  46  and the first complementary output port  48  and have the same resistance. The output voltage mean value controller includes the sixth NMOS transistor MN 17  and a tenth NMOS transistor MN 24 . The sixth NMOS transistor MN 17  has a gate and a drain connected to the node  50  between the first resistor R 1  and the second resistor R 2 . The tenth NMOS transistor  24  has a drain connected to the source of the sixth NMOS transistor MN 17 , a gate that receives the enable signal EN, and a source that is grounded (i.e., at the ground voltage VSS).  
         [0060]    In the full differential amplifier shown in FIG. 6, an output voltage level control circuit  64  includes an eleventh NMOS transistor MN 25  and a twelfth NMOS transistor MN 26 . The eleventh NMOS transistor MN 25  has a gate connected to the node  50  between the first resistor R 1  and the second resistor R 2 , a drain connected to the first output port  46 , and a source connected to the drain of the fifth NMOS transistor MN 16 . The twelfth NMOS transistor MN 26  has a gate connected to the node  50  between the first resistor R 1  and the second resistor R 2 , a drain connected to the first complementary output port  48 , and a source connected to the drain of the fifth NMOS transistor MN 16 .  
         [0061]    In the full differential amplifier of FIG. 6, the output voltage level control circuit  64  is such that a bypass current path does not pass through the first resistor R 1  and the second resistor R 2 . This more stably controls the mean value of the output voltage levels of the output signal OUT and the complementary output signal OUTB.  
         [0062]    [0062]FIGS. 7 through 9 show waveforms resulting from a simulation experiment for verifying the performances of the full differential amplifiers in the sense amplifiers according to embodiments of the present invention. FIG. 7 shows a waveform of the input signals SAOUT and SAOUTB used for the simulation experiment. FIG. 8 shows output signals of a full differential amplifier according to the present invention and of a conventional full differential amplifier. FIG. 9 shows output signals of a latch when the output of the full differential amplifier according to the present invention is used as an input and when the output of the conventional full differential amplifier is used as an input.  
         [0063]    For the simulation, the supply voltage VDD is 4 volts, and the difference between the input signal IN and the complementary input signal INB is about 0.1 volts. Referring to FIGS. 7 through 9, the conventional full differential amplifier may mis-operate since the mean value of the voltage levels of the output signal and the complementary output signal is higher and the output signals DOUT and DOUTB of the latch go to a low level as a result. However, the full differential amplifier in the sense amplifier according to the present invention outputs normal output signals OUT and OUTB since the mean value of the voltage levels of the output signal and the complementary output signal are reduced, and the latch operates normally.  
         [0064]    [0064]FIG. 10 shows a PMOS diode for describing the operation of the current sense amplifier  40  in the sense amplifier according to the embodiment of the present invention shown in FIG. 4. In the circuit shown in FIG. 10, a resistor RP is serially connected to and close to the source of a PMOS diode MP. The current-voltage characteristic curves of the elements and the circuit shown in FIG. 10 are shown in FIG. 11.  
         [0065]    As shown in FIG. 11, a voltage Vsgp is the sum of the voltage difference between the source and drain of the PMOS transistor MP and the voltage drop across the resistance RP. Accordingly, the resistance RP has a slight effect on the voltage Vsgp when the current through the PMOS diode MP is low. However, the effective transconductance of the circuit of FIG. 10 is reduced when the current is large. When the resistance RP is referred to as R and the transconductance value of the PMOS diode MP is referred to as gmp, the effective transconductance of the circuit of FIG. 10 is gmp/(1+gmp×R). Namely, when transconductance gmp is small, the influence of the resistance R is small. However, when transconductance gmp is large, the influence of the resistance R makes the effective transconductance smaller than transconductance gmp.  
         [0066]    In FIG. 4, the current sense amplifier  40  includes a cross-coupled PMOS transistor structure  59  including a third resistor R 3 , a fourth resistor R 4 , a seventh PMOS transistor MP 15 , and an eighth PMOS transistor MP 16 . A thirteenth NMOS transistor MN 21 ; a fourteenth NMOS transistor MN 22 ; and a fifteenth NMOS transistor MN 23  provide current paths between the cross-coupled PMOS transistor structure  59  and ground.  
         [0067]    The cross-coupled PMOS transistor structure  59  amplifies the current signals I 1  and I 2  input to a second input port  55  and a second complementary input port  57 , and outputs output voltage signals SAOUT and SAOUTB to node  52  functioning as a second output port and to node  54  functioning as a second complementary output port. The thirteenth NMOS transistor MN 21  and the fourteenth NMOS transistor MN 22  are serially connected to node  52  and node  54 , respectively. The gate and the drain of the thirteenth NMOS transistor MN 21  are connected together, and the gate and the drain of the fourteenth NMOS transistor MN 22  are connected together. The fifteenth NMOS transistor MN 23  is connected to the sources of the thirteenth NMOS transistor MN 21  and the fourteenth NMOS transistor MN 22  and to ground voltage VSS. The enable signal EN determines the conductivity state of the fifteenth NMOS transistor and thereby enables or enables operation of the current sense amplifier  40 . The third resistor R 3  is serially connected between the second input port IN and the source of the seventh PMOS transistor MP 15 . The fourth resistor R 4  is serially connected between of the second complementary input port INB and the source of the eighth PMOS transistor MP 16 .  
         [0068]    The current sense amplifier  40  in the sense amplifier according to the embodiment of the present invention shown in FIG. 4 operates stably since the third and fourth resistors R 3  and R 4  make the effective transconductances of the PMOS transistors MP 15  and MP 16  smaller than the transconductances of the NMOS transistors MN 21  and MN 22 .  
         [0069]    It is preferable to minimize parasitic resistances in the wiring between the third resistor R 3  and the source of the seventh PMOS transistor MP 15  and in the wiring between the fourth resistor R 4  and the source of the eighth PMOS transistor MP 16 . Locating the third resistor R 3  and the fourth resistor R 4  as close as possible to the sources of the seventh PMOS transistor MP 15  and the eighth PMOS transistor MP 16 , respectively, minimizes the RC delay time of the current sense amplifier, arising from the third and fourth resistors R 3  and R 4 . When the third and fourth resistors R 3  and R 4  are as close as possible to the sources of the seventh and eighth PMOS transistors MP 15  and MP 16 , respectively, and the third and fourth resistors R 3  and R 4  have resistance R, the RC delay time according to the resistance component is Rx(the contact capacitance of the source of the seventh PMOS transistor or the eighth PMOS transistor), which is negligible. Preferably, the resistance R of the third resistor R 3  and the fourth resistor R 4  is less than about 100Ω.  
         [0070]    [0070]FIG. 12 is a circuit diagram used for a simulation experiment for verifying the performance of the current sense amplifier  40  in the sense amplifier according to the embodiment of the present invention of FIG. 4. In FIG. 12, PMOS current sources MP 17  and MP 18  are connected to the third resistor R 3  and the fourth resistor R 4 , respectively. The resistance R of the third resistor R 3  and the fourth resistor R 4  is 60Ω. The channel width/channel length of the seventh PMOS transistor MP 15  and the eighth PMOS transistor MP 16  is 40/0.6. The channel width/channel length of the thirteenth NMOS transistor MN 21  and the fourteenth NMOS transistor MN 22  is 12/0.6. The supply voltage supplied to the PMOS current sources MP 17  and MP 18  is 4 volts and the magnitude of the input currents I 1  and I 2  is about 1.28 mA±0.3 mA.  
         [0071]    [0071]FIG. 13 shows waveforms of the output voltage signals of the current sense amplifier  10  (FIG. 1) in the conventional sense amplifier and the output voltage signals of the current sense amplifier  40  in the sense amplifier according to the embodiment of the present invention shown in FIG. 4. FIG. 14 shows waveforms of the input current signals of the current sense amplifier  10  in the conventional sense amplifier and the input current signals of the current sense amplifier  40  in the sense amplifier according to the embodiment of the present invention shown in FIG. 4.  
         [0072]    The current sense amplifier in the conventional sense amplifier operates unstably since the transconductance of the PMOS transistors becomes larger than the transconductance of the NMOS transistors, to thus affect the input current signal and the output voltage signal, as shown in FIGS. 13 and 14. However, the current sense amplifier in the sense amplifier according to the present invention stably operates since the resistance components prevent the oscillation phenomenon.  
         [0073]    [0073]FIGS. 15, 16A,  16 B, and  17  illustrate methods for directly forming the third resistor R 3  or the fourth resistor R 4  of the current sense amplifier  40  in FIG. 4, in the transistors MP 15  or MP 16 .  
         [0074]    In FIG. 15, the contact resistance of the source electrodes of a PMOS transistor provides the desired resistance R. The resistances of the third resistor R 3  or the fourth resistor R 4  can thus be realized as the contact resistance of the source electrodes of the transistors MP 15  and MP 16 . In FIG. 15, one contact  66  connects to the source electrode of the transistor, and multiple contacts  68 ,  70 , and  72  connect to the drain electrode. For example, if each contact  66 ,  68 ,  70 , and  72  has a resistance of 100Ω, the source electrode has a contact resistance of 100Ω, and the drain electrode has a contact resistance of 100/3Ω in the transistor.  
         [0075]    [0075]FIG. 16A illustrates an embodiment where the resistances of the third resistor R 3  or the fourth resistor R 4  are realized as the resistance of the active region of the source electrode. More particularly, the separation of a contact  74  of the source electrode of the transistor from one edge of the gate electrode is greater than the separation of a contact  76  of the drain electrode from the opposite edge of the gate electrode. FIG. 16B is an equivalent circuit of FIG. 16A. In FIG. 16B, Rcd, Rcs, Rjd, and Rjs respectively denote a drain contact resistance, a source contact resistance, a drain junction resistance, and a source junction resistance.  
         [0076]    [0076]FIG. 17 illustrates an embodiment in which a depth d 3  of the active region of the source electrode is thin, to increase the active resistance on the source side of a transistor. The active resistance increases as the depth, that is, the thickness of the active region, is reduced. FIG. 17 also illustrates that the thin active region can be used in combination with the contact resistance as described above in regard to FIG. 15.  
         [0077]    Also, it is possible to realize the resistance of the third resistor R 3  or the fourth resistor R 4  by reducing the impurity density of the active region of the source electrode of the transistor, thus increasing the active resistance of the source.  
         [0078]    While this invention has been particularly shown and described with reference to exemplary embodiments thereof, various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Also, the sense amplifier and the full differential amplifier included in the sense amplifier of the semiconductor integrated circuit according to the present invention can be used in other application fields as independent circuits as well as in the sense amplifier as shown in the embodiments of the present invention.  
         [0079]    The sense amplifier of the semiconductor integrated circuit according to the present invention can stabilize the operation of the latch by reducing the mean voltage level of the output signal even when the supply voltage increases, easily control the voltage gain of the full differential amplifier by controlling the resistance, and stably operate at high speed by preventing an oscillation phenomenon which can occur when the gain of the PMOS transistor increases.