Abstract:
An accumulated statistics CFAR method and device operates using integrated data to maximize the probability of target detection for a given false alarm rate. The CFAR hardware varies its detection criteria as a function of the statistics of the range gate in question. The detection threshold is based on other range gates seen in the past which contain the same terrain type.

Description:
This application is a continuation-in-part of prior application Ser. No. 215,119, filed July 5, 1988 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention generally relates to constant false alarm rate (CFAR) signal processors, and in particular, to a CFAR which determines a threshold level based upon accumulated statistics. 
     In prior art, CFARs have been developed which use a range cell or range gate averaging technique. These CFARs average the data from cells near a test cell with the assumption that the terrain and environmental conditions covered by these cells are similar to the terrain and environmental conditions of the test cell. The difficulties with this type of CFAR are that terrain conditions may vary drastically from one cell to the next. This could result in a threshold level being set too high for the test cell and masking actual targets. Another problem is multiple targets. Using cell averaging techniques, if there are subsequent targets located in the cells to be averaged, they may cancel out a target located in the test cell. In CFAR using cell averaging, in order to obtain an acceptable false alarm rate, threshold levels may be higher than necessary due to inaccuracies in terrain and environmental conditions data resulting in a reduced probability of target detection. 
     SUMMARY OF THE INVENTION 
     The present invention pertains to an accumulated statistics CFAR. The CFAR circuitry of the present invention operates on the integrated data streams consisting of sixteen consecutive filter values from an FFT (fast Fourier transform) or some integrated number of FFTs to maximize the probability of target detection for a given false alarm rate. Each set of sixteen consecutive filter values form a clutter spread representing a terrain type. The accumulated statistics CFAR comprises a microprocessing unit (MPU), statistics means, threshold means and histogram means. The statistics means contains a statistics memory and logic circuitry which stores the average of each frequency filter value having the same amplitude, for all range gates having the same clutter spread and clutter amplitude (i.e. having the same terrain type). 
     Histogram means coupled to the microprocessing unit and containing a histogram memory records the frequency with which each terrain type occurs, and records target detection counts for each filter for each terrain type. 
     The MPU is coupled to threshold circuitry which contains a threshold memory. After the CFAR has operated for a given amount of time and the statistical means has gathered sufficient samples, the MPU reads the data from the statistics memory. It then uses these values to set a threshold level. The MPU also clears the histogram memory. The threshold level is then tested and corrected by the MPU with subsequent runnings of the device. 
     It is an object of the present invention to provide a new and improved CFAR. 
     It is a further object of the present invention to improve target detection sensitivity. 
     It is a further object of the present invention to eliminate false alarms due to abruptly changing terrain. 
     It is another object of the present invention to increase detection probability in multiple targets situations. 
     It is a further object of the present invention to provide a CFAR with a false alarm rate that is customer selectible and is measurable in the CFAR circuitry. 
     It is another object of the present invention to provide a CFAR capable of separate target thresholding for any range cells which may contain second-time-around clutter. 
     These and other objects of the present invention will become apparent to those skilled in the art upon consideration of the accompanying specification, claims and drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram of an embodiment of the present invention; and 
     FIG. 2 is a simplified block diagram of a modification to the device illustrated in FIG. 1. 
     FIG. 3 is a flow diagram of the operation of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention is an accumulated statistics CFAR signal processor which may be used in any radar system requiring high performance moving target detection. The present invention processes radar video signals which have been divided into range gates. The number of range gates the video signal is divided into is a function of how much resolution is desired. In an embodiment of the present invention, a 150 kilometer field with 30 meter resolution is desired, thus resulting in 5,120 range gates. In the present invention, the signal from each range gate is integrated by an FFT resulting in an integrated data stream. The signal from each range gate is represented in the integrated data stream by frequency data consisting of, in this embodiment, the amplitude values of 16 frequency filters,(F 0  through F 16 ). These terms and methods are well-known in the art and for that reason, have not been discussed in greater detail. 
     The flowchart of FIG. 3 is provided to help one with skill in the art of radar to better understand the following detailed description of the present invention. As shown in FIG. 3, an accumulated statistics CFAR (constant false alarm rate) 10 receives a filter bank output 90. Filter bank output 90 is a set of equally spaced (in the frequency domain) band pass filters such as an FFT (fast Fourier transform) output. Each range gate contains an independently calculated filter bank output. An environmental condition is extracted from filter bank output 90 as represented by box 92. The environmental condition is comprised of at least one of the filter bank outputs, and may be a combination of more than one filter bank output, such as a DC amplitude output and a CFS (clutter frequency spread) amplitude output. The environmental condition may also contain a processed parameter, such as an average output or peak detected output. The environmental condition may be combined with other parameters such as a filter number, as represented by box 94, radar PRF (pulse repetition frequency) number, or RF (radar frequency) number. This combination defines a threshold memory address which is input into a threshold memory, represented by box 96. A threshold stored in a memory location defined by the threshold memory address is then output to a comparator (represented by box 98). The comparator compares the threshold value from the threshold memory with the filter value received from filter bank output 90. If the filter value is greater than the value of the threshold memory, a target is declared as detected (box 100). 
     Referring now to FIG. 1, a simplified block diagram of an accumulated statistics CFAR is designated 10. Integrated data bus 12, filter number bus 14 and leads 16 and 18 are connected to address logic 20. Address logic 20 logically prepares data from integrated data bus 12 to produce an address. An address bus 22 connects address logic 20 and a holding register 24. A microprocessor address bus 28 is connected to a holding register 26. A control lead 30 is coupled to holding register 26 and an inverter 32. Inverter 32 is then coupled to holding register 24. Control lead 30 carries a bit which determines which holding register operates at a given time. It should be understood that there are many ways of controlling which of two holding registers is operating at a given time and in this embodiment inverter 32 is used. An address bus 34 couples holding register 24 and holding register 26 to histogram memory 36, statistics memory 38 and threshold memory 40. A data bus 42 connects statistics memory 38, an averaging logic circuit 44 and a microprocessor 60. A data bus 46 connects threshold memory 40, a comparator 48 and microprocessor 60. Data bus 12 is connected to averaging logic 44 and comparator 48. Data bus 50 connects histogram memory 36, summer 52 and microprocessor 60. Comparator 48 is connected to summer 52 via bus 54. 
     As the signal from the range gate of interest is processed, 16 filter values are produced resulting in a means for determining terrain type. Filters F 0  and F 2  are used to address statistics memory 38 in which filters F 3  through F 16  are stored. F 0 , F 2  determine clutter amplitude, clutter spread, respectively. Each clutter spread, clutter amplitude combination represents a terrain type. When the values from filters F 0  and F 2  from one range gate equal the values from another rage gate, it can be assumed that these terrain types are closely matching. F 1  is not used because it provides little new information due to the properties of weighing in the FFT. 
     Each one of the sixteen consecutive filter values for the range gate of interest, in this embodiment, enters CFAR 10 sequentially via integrated data bus 12 as a 10-bit data stream. The data from filters F 0  and F 2  enter address logic 20 where each is compressed into 4 bits. In this specific embodiment, the 4 bits used for F 0  are actually the 4 most significant bits of the full F 0  amplitude, and the 4 bits of filter 2 data are a logarithmically compressed version of the full F 2  amplitude. While this is the preferred embodiment, for data having second-time-around (S-T-A) possibilities, F 0  data can be replaced with a logarithmically compressed versions of the average of the 3 smallest amplitudes within F 4  to F 8  inclusive of the range gate of interest, and F 2  data can be replaced with a logarithmically compressed version of the average of the 6 smallest amplitudes within F 9  to F 16  inclusive of the range gate of interest. The reason the two largest amplitudes are eliminated in each case is to allow for the possibility of a target in the range gate of interest. FIG. 2 is a simplified block diagram of S-T-A compensator circuitry generally designated 70, used when an S-T-A compensated address is desired. An integrated data stream enters S-T-A compensator 70 via a data bus 72. Summer logic 74 having an input coupled to data bus 72 and having an output, first, produces the sum of, in this embodiment, the three lowest amplitudes from filter values F 4  through F 8 , and the sum of the six smallest amplitudes from filter values F 9  to F 16 . Filter values F 0  through F 3  are not used since being low frequency filters, they would almost certainly be included in the high amplitudes that are discarded. An output memory 76 having an input coupled to the output of said summer logic 74 and having an output, stores the data produced in summer logic 74. A delay 78 having an input coupled to data bus 72 and an output, delays the integrated data stream until summer logic 74 has processed said filter values from said integrated data stream. A selective multiplexer 80 has a first input coupled to said output of said output memory 76, a second input coupled to said output of said delay 78 and a third input coupled to said microprocessor 60 and having an output connected to said integrated data bus 12 of CFAR 10 in FIG. 1. Selective multiplexer 80, upon a signal from microprocessor 60 can pass data from either output memory 76 or delay 78 to CFAR 10 of FIG. 1. Delay 78 delays the integrated data stream so that the F 0  data enters selective multiplexer 80 at the same time the F 4  through F 8  data from output memory 76 enters selective multiplexer 80 and the F 2  data from delay 78 enter selective multiplexer 80 at the same time the F 9  through F 16  data from output memory 76 enters selective multiplexer 80. Upon the possibility of S-T-A clutter, microprocessor 60 signals selective multiplexer 80 to allow data from output memory 76 to enter CFAR 10 of FIG. 1 and the F 0  and F 2  data from delay 78 is not allowed to pass. The data from output memory 76 is now logarithmically compressed in address logic 20 of FIG. 1. It then enters holding register 24 as part of an address. The rest of the integrated data steam, filters F 3  through F 16  pass through the selective multiplexer 80 and enter CFAR 10 of FIG. 1. If S-T-A clutter is not possible, the selective mutliplexer 80 is signalled by microprocessor 60 to block the output of output memory 76 and allow filter values F 0  through F 16  from delay 78 to enter CFAR 10. 
     Alternatively, F 2  data can be replaced with any other filter amplitude logarithmically compressed to 4 bits. It is anticipated that the averages described above will be utilized only when operating on a range gate with an S-T-A clutter possibility, since in such an area an S-T-A occurrence will manifest itself as noise in a non-coherent environment, and thus will tend to affect all frequency filters equally. Using an amplitude average as part of the thresholding lookup provides a means for automatically raising the target threshold in such an area. However, the MPU can choose whether to replace the F 0  and F 2  values or not. Since an address bit is already allocated for S-T-A areas, using F 0  and F 2  and simply raising the threshold for the S-T-A side of the threshold memory is another possibility. A way of checking the effectiveness of both approaches is borne from the histogram memory, which is described later. In this embodiment, address logic 20 inserts the altered portion of the integrator data stream, which in the preferred embodiment is the compressed filter F 0  and F 2  values into holding register 24. A 14-bit address is then formed using data from bus 14, lead 16 and lead 18. Statistics memory 38 is divided into 4 parts. Lead 16 and lead 18 each carry a bit which together address one of these quadrants. Since the statistics vary with PRF (pulse repetition frequency), half of the statistics memory is dedicated to each PRF of the given mode. For example, half of the memory is dedicated for the lower PRF of 650 hertz and half is dedicated to the data corresponding to the higher PRF or 850 hertz. Thus, lead 16 carries a bit which addresses between the two halves. The two PRF modes are used so that a target having the same frequency as one of the modes, and thus being masked, would become visible with the other mode. Also, the statistics are expected to vary more in range areas where there exists the possibility of a second-time-around (S-T-A) clutter, so the memory is again divided in half as a function of the possibility of such clutter. Effectively, this gives 4 separate statistics memories. Lead 18, carries a bit which specifies whether the possibility of second-time-around exists or not. The control bit which indicates whether or not S-T-A clutter is possible is under the ultimate control of the microprocessor, which calculates where this bit should change value as a function of range and aircraft altitude, and which commands the CFAR control hardware to cause the transition at the proper point in real time. Bus 14 supplies 4 bits which specify which of the sixteen consecutive filters is being stored in statistics memory 38. The address of a filter value, is the altered integrated data stream data in holding register 24, which will only be changed when each new integrated data stream is entered into CFAR 10, the filter number data, which is changted with each filter value, the S-T-A clutter data, and the PRF mode data. Address logic 20 regulates the combination of the filter number data with the other data to form an address for each filter value. 
     As each filter value is stored in statistics memory 38 sequentially from F 3  to F 16  under its specific terrain type, designated by filters F 0  and F 2  and the filter number, address locations for each terrain type will begin to fill. Holding register 24 containing an address, addresses the statistics memory 38 for a given terrain type and filter number. If there is any data in the memory at this address, it is inserted into averaging logic 44 where it is averaged with the incoming data then restored in the statistics memory 38. Averaging logic 44 averages a percentage of the new value with a percentage of the old value. The statistics memory stores the data calculated by the following equation: 
     
         S.sub.new =K×S.sub.old +(1-K)×D 
    
     where 
     D=data from the integrator for the filter of interest for the range gate of interest; 
     S old  =data already stored in the statistics memory for the filter of interest from other range gates containing the same filter 0 value and the same filter 2 value (the same terrain type); 
     K=a constant controlled by the MPU; and 
     S new  =new data to store in the statistics memory. 
     Thus, statistics memory 38 contains, in the steady state, the average of each filter amplitude for all range gates having the same clutter level and range type spread. The address from holding register 24, that is, the F 0  and F 2  compressed values address a F 0  location in histogram memory 36 which is incremented by 1, thereby keeping an account of how many times a specific terrain type has been encountered. 
     After a sufficient amount of operating time, control lead 30 signals inverter 32, which blocks holding register 24 and activates holding register 26. Holding register 26 will hold the addresses from microprocessor 60 via address bus 28. Microprocessor 60 can now read the data from the statistics memory to get an estimate of the averaged values. It then sets the corresponding thresholds to that averaged value and stores them in threshold memory 40 addressed by holding register 26 via address bus 34. Microprocessor 60, at this point, also clears histogram memory 36. CFAR 10 is then operated again for a predetermined amount of time with the data for each filter being compared with the threshold level for that filter in comparator 48. In histogram memory 36, the number of times a terrain type occurs is stored in the filter F 0 , location. This is also the maximum number of times each filter in that type of terrain or clutter spread could exceed its target threshold. The filter F 0  location is used to count the number of times each terrain type occurs, because the filter F 0  value is not used for target detection, and this location is not used for counting target detections. Filters F 3  through F 16  memory locations store the number of times a target was detected in those filters for each terrain type. If the incoming filter data is greater than the threshold data from threshold memory 40, when compared in comparator 48 indicating a target detection, summer 52 increments that filter location of the given terrain type in histogram memory 36. Each filter location for each terrain type contains the number of times that filter&#39;s amplitude did exceed its corresponding threshold. The memory is limited to 16 bits, in this embodiment, so once the terrain type count location reaches 65,535, updating to all associated filter target detection counts is disabled. Once CFAR 10 has run for a predetermined amount of time comparing filter values to their corresponding threshold level, the microprocessor can calculate the false alarm rate by dividing filter target detection counts by the associated count in the terrain type location. Once the false alarm rate has been determined, the following equation can be used to set the final threshold level to obtain the desired false alarm rate: 
     
         TC1/TCf=T1/Tf 
    
     where 
     T1=actual threshold value used initially; 
     TC1=normalized threshold value corresponding to T1; 
     TCf=desired final normalized threshold value; and 
     Tf=final actual threshold to give desired false alarm rate. 
     The initial calculation of the false alarm rate by the microprocessor implicitly assumes real target detections are negligible when compared with false alarm detections. A measured actual false alarm rate of less than 3%, where real target detections mights start to manifest their statistical significance, is given special treatment in threshold calculations. 
     Another method for determining the final threshold level is that once the microprocessor knows the false alarm rate for the given thresholds, it then increases the thresholds by 15% or 20%, clears the histogram memory and runs the CFAR for a specified amount of time as before, until the histogram contains sufficient data. The microprocessor calculates the new false alarm rates corresponding to the new thresholds. The microprocessor now has, for each filter for each terrain type, two different false alarm rates corresponding to two different thresholds, and can then determine the threshold for the desired false alarm rate. This determination is made by utilizing the following equation: 
     
         Tf=T1+(TCf-TC1)×(T2-T1)/(TC2-TC1) 
    
     where 
     T1=actual threshold value used initially; 
     T2=actual second threshold value; 
     TC1=normalized threshold value corresponding to T1; 
     TC2=normalized threshold value corresponding to TC; 
     TCf=desired final normalized threshold value; and 
     Tf=final actual threshold to give desired false alarm rate. 
     The values for TC1 and TC2 are precalculated for 1000 different false alarm rates for both a 4-record integration period and an 8-record integration period. Thus, the false alarm rate associated with T1 is rounded to the nearest 0.1% and is then used as an address to a TC look-up table. TCF is known since the desired false alarm rate is known. Thus, the MPU has all information necessary to calculate TF. 
     If, for T1 and T2, the measured false alarm rate is less than 0.03, the following equation is utilized: 
     
         TF=(T1 or T2) * k 
    
     where 
     k=a number solely based on integration period. 
     A second embodiment of the present invention includes the addition of another parameter in the environmental condition. The parameter is the average of the high frequency filter outputs after one or more of the highest amplitude high frequency filters have been removed. If the range gate in question has a target within the high frequency filters, the target must be removed to calculate the threshold for that particular range gate. When a range gate has STA clutter, the average of the high frequency filters is increased. Therefore, if a few of the highest amplitude high frequency filters are removed, the effect on the average is negligible. Therefore, a target may be removed from the threshold without adversely affecting the threshold determination. 
     An additional embodiment of the present invention removes threshold memory of FIGS. 1 and 3 from the operational loop. Referring to FIG. 1, a multiplier (not shown) is coupled to the output of statistics memory 38. The multiplier is then coupled to comparator 48 in lieu of threshold memory 40. The output of statistics memory 38 is multiplied in the multiplier with a number or set of numbers which are functions of the desired false alarm rate. The products of statistics memory output and the false alarm rate factors are the final thresholds which would otherwise be received from threshold memory 40. It should be noted that this process only takes information from range gates having similar clutter statistics rather than from surrounding range rates. 
     There is thus provided by the present invention a substantially improved CFAR. In setting the target detection thresholds, the CFAR hardware actually measures the mean and standard deviation for the amplitudes of all frequency components in all types of terrain. Thus, false alarms due varying terrain types is greatly reduced. 
     Having thus described the invention, it will be apparent to those of skill in the art, that various modifications can be made within the spirit and scope of the present invention.