Abstract:
The disclosed embodiments relate to a low cost signal adjustment or calibration method and apparatus for generating a stable clock signal that is used to drive a communications interface (e.g., a UART port). More specifically, a processor within a microcontroller uses a low frequency crystal oscillator and a scaling module to remove a frequency offset error contained in an unstable clock signal generated by a high frequency RC oscillator. The processor detects and removes the frequency offset error when specific triggering events occur such as when the microcontroller is powered up, awaken from a sleep or stand by mode, or experiences a communications error.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention generally relates to providing a stable clock signal, and more particularly, to a technique for providing a stable Universal Asynchronous Receiver/Transmitter (UART) clock signal. 
       BACKGROUND OF THE INVENTION 
       [0002]    This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. 
         [0003]    Referring now to  FIG. 1 , an exemplary processing arrangement  10  typically found in portable Audio/Video (AV) devices such as AV MP3 players is shown. It should be appreciated that, for purposes of clarity, every feature or element of processing arrangement  10  is not shown or described herein. The use of features or elements not shown or discussed herein is deemed within the knowledge of one skilled in the art of AV devices. Processing arrangement  10  includes a main processor  12  and a microcontroller (MCU)  14  communicatively connected to main processor  12  via a serial bus such as a Universal Asynchronous Receiver/Transmitter (UART) bus  16 . Main processor  12  is a sophisticated processor responsible for control of AV device functions including, but not limited to, AV playback, User Interface (UI) navigation, file system management and embedded Operating System (OS) execution. MCU  14  is a low cost controller responsible for control of AV device functions such as key matrix scanning  16 , battery detection  18 , power control  20 , IR remote controller detection  22  and real time clock (RTC) generation  24 . MCU  14  communicates with Main Processor  12  by transmitting signals TXD  26  and receiving signals RXD  28  over UART bus  16 . 
         [0004]    Referring now to  FIG. 2 , the timing circuitry of a conventional MCU  14  is illustrated. The timing circuitry includes an RC oscillator  42  connected to a resistor  44  and capacitor  46 , a crystal oscillator  48  connected to a crystal  50  such as a 32.768 KHz crystal, and a UART clock  52  connected to a UART module or port  54 . The RC oscillator  42  is a high speed oscillator used as the main system clock for the MCU  14  and MCU peripherals  16 - 22 . In general, the RC oscillator frequency may be within the range of 2 to 8 MHz. The frequency of the RC oscillator  42  varies with temperature, resistor  44  and capacitor  46  values, power supply fluctuations and the like. As a result, the RC oscillator  42  may have a frequency offset error as high as 10%. The crystal oscillator  48  is a low speed oscillator used for the RTC generation  24 . The RTC is used by the AV device to track real time so the AV device can timestamp content, maintain a calendar, and provide the display of a on screen clock to a user. The RTC can also serve as the system clock when the AV device is in standby mode or some other low current consumption mode. The performance of the crystal oscillator is typical very good (e.g., 32.768 kHz+/−100 ppm). To ensure proper communication between MCU  14  and main processor  12 , the UART module  54  needs to driven by a 115.2 kHz clock signal that has a frequency offset error of less than 5%. One possible approach to ensure that the UART module  54  operates at the proper frequency and below the 5% frequency offset error tolerance is to have a dedicated UART clock such as a 115.2 kHz crystal oscillator clock. A drawback of using a dedicated UART clock is that it increases the cost of the MCU  14  and, as a result, the cost of the AV device. Another approach would be to use either the RC oscillator  42  or the crystal oscillator  48  as the UART clock  52 . However, the drawbacks with this approach are that the frequency offset of the RC oscillator  42  exceeds the 5% frequency offset error tolerance of the UART module  54  and the frequency of the crystal oscillator (e.g., 32.768 kHz) can not support the 115.2 kHz clock signal required to drive the UART module  54 . Yet another approach would be to replace the RC oscillator  42  with a 2 to 8 MHz crystal oscillator and have the main system clock share the oscillator with the UART module  54 . Although this shared approach is less costly than having a dedicated 32.768 kHz UART clock, it still has the drawback of undesirably increasing the cost of the MCU  14  and, as a result, the cost of the AV device. 
         [0005]    The present invention is directed towards overcoming these drawbacks. 
       SUMMARY OF THE INVENTION 
       [0006]    The disclosed embodiments relate to a low cost signal adjustment or calibration method and apparatus for generating a stable clock signal that is used to drive a communications interface (e.g., a UART port). More specifically, a processor within a microcontroller uses a low frequency crystal oscillator and a scaling module to remove a frequency offset error contained in an unstable clock signal generated by a high frequency RC oscillator. The processor detects and removes the frequency offset error when specific triggering events occur such as when the microcontroller is powered up, awaken from a sleep or stand by mode, or experiences a communications error. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    In the drawings: 
           [0008]      FIG. 1  is a block diagram showing an exemplary MCU and main processor arrangement in an AV device; 
           [0009]      FIG. 2  is a block diagram illustrating conventional MCU timing circuitry; 
           [0010]      FIG. 3  is a block diagram illustrating MCU timing circuitry of the present invention; and 
           [0011]      FIG. 4  is a process flow diagram illustrating the operation of the MCU timing circuitry of  FIG. 3  in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0012]    One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. 
         [0013]    Referring now to  FIG. 3 , the timing circuitry of the MCU  60  of the present invention is illustrated. It should be appreciated that the timing circuitry may be implemented in hardware, software or a combination of hardware and software. The timing circuitry includes a processor  61  connected to a main system clock  62  (including an RC oscillator  64 , resistor  66  and capacitor  68 ), an RTC  70  (including a crystal oscillator  72  and a crystal  74  such as a 32.768 KHz crystal), and a communications interface  76  (such as a UART module or port) via a scaling module  78 . Main system clock  62  is also connected to the UART module or port  76  via the scaling module  78 . 
         [0014]    The RC oscillator  64  of the main system clock  62  is a high speed oscillator operating within the range of 2 to 8 MHz. The frequency of the RC oscillator  64  varies with temperature, resistor  66  and capacitor  68  values, power supply fluctuations and the like. As a result, the frequency offset error of the RC oscillator  64  may be as high as 10%. The crystal oscillator  72  of the RTC  70  is a low speed oscillator used for the RTC signal generation. The RTC is used by the AV device to track real time so the AV device can timestamp content, maintain a calendar, and provide the display of a on screen clock to a user. The RTC can also serve as the system clock when the AV device is in standby mode or some other low current consumption mode. The crystal oscillator  72  can also serve as the system clock when the AV device is in standby mode or some other low current consumption mode. The performance of the crystal oscillator is typical very good (e.g., 32.768 kHz+/−100 ppm). 
         [0015]    As discussed above, to ensure proper communication between MCU  60  and main processor  12 , the UART module  76  should be driven by a stable 115.2 kHz clock signal having a frequency offset error of less than 5%. Also, as discussed above, it is desirable to achieve the UART clock frequency and frequency error tolerance goals without significantly increasing the cost of the MCU and AV device. The present invention achieves these goals through the use of the system clock  62  and RTC  70  in conjunction with the scaling module  78  and a software routine executed by processor  61 . More specifically, the clock signal generated by main system clock  62  is passed to scaling module  78 . Scaling module  78  adjusts the received clock signal based on a scaling factor K and outputs a scaled clock signal that is used to drive the UART module  76 . As discussed in further detail below, the scaling factor is used to adjust the clock signal generated by main system clock  62  to ensure that scaled signal used to drive UART module  76  is approximately 115.2 kHz give or take a less than 5% frequency offset error. The relationship between the frequency of the clock signal generated by the main system clock  62 , the frequency of the scaled clock signal output by scaling module  78  and the scaling factor K is as follows: 
         [0000]    
       
      
       F 
       U 
       =F 
       m 
       /K  
      
     
         [0000]    Wherein Fm is the frequency of the clock signal generated by main system clock  62  and Fu is frequency of the scaled clock signal output by scaling module  78 . Since the frequency of the main system clock&#39;s  62  RC oscillator  64  varies with temperature, resistor  66  and capacitor  68  values, power supply fluctuations and the like, scaling factor K must be periodically adjusted to ensure that the frequency Fu of the scaled clock signal is stable. 
         [0016]    Referring now to  FIG. 4 , the software routine  90  executed by processor  61  to calculate and adjust or calibrate the scaling factor K is shown. Processor  61 , at step  92 , starts the execution of the software routine. Since the routine consumes time and system resources, it is important to execute the software routine at the appropriate times. In other words, when the appropriate triggering events occur. In AV devices, such as AV MP3 players, software routine  90  should be executed before enabling power to main processor  12 , before waking main processor  12  from a sleep or stand by mode, and anytime a UART communication physical layer error occurs. It should be noted that a physical layer error (e.g., a parity error) will occur if the scaled clock signal used to drive UART module  76  contains a frequency offset error greater than or equal to 5%. Next, at step  94 , processor  61  instructs main system clock  62  to generate a clock signal for a predetermined time period (e.g., 10 ms). Then, at step  96 , processor  61  instructs the more accurate RTC  70  to generate a signal (e.g., a 32.768 kHz signal) that processor  61  uses, at step  98 , to measure the actual time period of the clock signal generated by main system clock  62 . One way processor  61  can use RTC signal to measure the requested main system clock signal is by implementing a counter based on the RTC signal. The counter is then used to count the actual time period of the requested main system clock signal. Afterwards, at step  100 , processor  61  determines if the offset between the actual time period and the requested time period is equal to or greater than a predetermined limit (e.g., 5%). It should be appreciated that this offset is equivalent to frequency offset error of the RC oscillator  64  of system clock  62 . If the offset does not exceed a predetermined limit, processor  61 , at step  104 , does not adjust the scaling factor K and waits for the next software routine execution request (i.e., a request based detecting one of the events discussed above). If the offset does exceed a predetermined limit, processor  61 , at step  102 , adjusts the scaling factor K to remove the frequency offset error from the scaled clock signal used to drive UART module  76 . Alternatively, processor  61  may adjusts the scaling factor K to reduce the frequency offset error in the scaled clock signal so the frequency offset error falls below the predetermined limit. Afterwards, processor  61  returns to step  94  and re-executes steps  94 - 100  to ensure that the frequency offset error in the scaled clock signal has been removed or reduced below the predetermined limit. 
         [0017]    While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.